From 957022853c51088496b04209cd3d23743b9d2fd8 Mon Sep 17 00:00:00 2001 From: Jean Guyader Date: Thu, 8 Oct 2009 18:11:57 +0100 Subject: [PATCH] Rebase with carbon/trunk dom0.pq. changeset: 663:308bd4f49eba tag: tip user: Ian Campbell date: Thu Oct 08 09:06:17 2009 +0100 summary: CP-1074: Re-enable MLNX4 driver, with update utility kernel configuration this time. --- master/CA-30778-backend-bound-sysfs.diff | 119 + master/CA-30953-wild-ptr-deref.diff | 32 + master/CA-32254-shutdown-closed-backends.diff | 101 + master/CA-32943-wild-ptr-deref.diff | 20 + master/CXD-99-gnterr-status.diff | 55 + master/blk-latency-stats | 196 +- master/blkback-pagemap-cleanup.diff | 43 + master/blktap-initwait-fix | 278 + master/bnx2-1.9.20b.patch | 33329 ++++++ master/bnx2i-1.8.9n.patch | 12981 +++ master/bnx2x-1.50.13.patch | 84269 ++++++++++++++ master/bonding-balance-slb-fixes.patch | 12 +- master/bonding-balance-slb.patch | 8 + master/cifs-no-tcp-sharing.patch | 37 + ...-linux-2.6.18-xen.hg-918.71a61b393cdf.diff | 36 + master/clear-ts_usedfpu-on-new-threads | 53 + master/clts-when-calling-math_state_restore | 18 + master/cxgb3-1.3.1.7.patch | 32310 ++++++ master/debug-dump-skb-info-when-invalid | 6 +- master/e1000-8.0.16.patch | 31374 ++++++ master/e1000e-1.0.2.5.patch | 24819 +++++ master/feature-gso-tcpv4-prefix | 2 +- ...8766a2bae1b208470e7cc934ac462561e3cb.patch | 48 + ...d4cfcdc71ce01535b31cc4d57d59a1fae1fc.patch | 51 + ...c2e7fa8ca63a575792534b63c5092099c286.patch | 37 + ...7ef36ec834fee1719636b30d2f28f4cb0166.patch | 51 + ...1da4e3f323b7673b061e6f7e0d0c12dc2b49.patch | 44 + master/ibft-find.patch | 44 + master/igb-1.3.28.4.patch | 23508 ++++ .../increase-maximum-number-of-loop-devices | 12 + .../intel-net-driver-conflicting-names.patch | 316 +- master/intel-net-driver-kcompat.patch | 234 +- master/itpm | 12 +- master/ixgbe-2.0.38.2.patch | 26874 +++++ master/kernel-configuration | 61 +- master/kexec-larger-max-pfn-for-oldmem.patch | 50 + master/linux-2.6.18-xen.hg-918.71a61b393cdf | 35 + master/linux-2.6.27.25-0.1.1.patch | 8029 ++ master/linux-2.6.27.29-0.1.1.patch | 90475 ++++++++++++++++ ...egaraid_sas-v00.00.04.12-compile-fix.patch | 21 + master/megaraid_sas-v00.00.04.12.patch | 1638 + master/mlnx_en-1.4.1.patch | 9250 ++ master/mlnx_en-fix-warnings.patch | 65 + master/mpt2sas-02.00.00.00.patch | 25277 +++++ master/mptlinux-4.20.00.01.patch | 18891 ++++ ...k-call-skb_checksum_setup-at-receive.patch | 109 + master/netback-drop-xen-skb-members.patch | 171 + ...tback-force-CHECKSUM_PARTIAL-for-GSO.patch | 34 + .../netback-tcp-and-ip-in-different-fragments | 4 +- master/netxen_nic-4.0.50.patch | 12431 +++ master/open-iscsi-gfpkernel.patch | 16 +- master/pciback-flr-82599 | 29 + master/s2io-2-0-27-1.patch | 729 + master/s2io-2.1.37.17590.patch | 18447 ++++ master/s2io-2.1.37.18446.patch | 12 + master/s2io-fix-paths.patch | 20 + master/series | 146 +- master/vswitch-build-integration.patch | 129 +- master/vswitch.patch | 6774 ++ master/vxge-2.0.6.18061.patch | 26814 +++++ 60 files changed, 490611 insertions(+), 375 deletions(-) create mode 100644 master/CA-30778-backend-bound-sysfs.diff create mode 100644 master/CA-30953-wild-ptr-deref.diff create mode 100644 master/CA-32254-shutdown-closed-backends.diff create mode 100644 master/CA-32943-wild-ptr-deref.diff create mode 100644 master/CXD-99-gnterr-status.diff create mode 100644 master/blkback-pagemap-cleanup.diff create mode 100755 master/blktap-initwait-fix create mode 100644 master/bnx2-1.9.20b.patch create mode 100644 master/bnx2i-1.8.9n.patch create mode 100644 master/bnx2x-1.50.13.patch create mode 100644 master/cifs-no-tcp-sharing.patch create mode 100644 master/cleanup-linux-2.6.18-xen.hg-918.71a61b393cdf.diff create mode 100644 master/clear-ts_usedfpu-on-new-threads create mode 100644 master/clts-when-calling-math_state_restore create mode 100644 master/cxgb3-1.3.1.7.patch create mode 100644 master/e1000-8.0.16.patch create mode 100644 master/e1000e-1.0.2.5.patch create mode 100644 master/git-3c598766a2bae1b208470e7cc934ac462561e3cb.patch create mode 100644 master/git-641cd4cfcdc71ce01535b31cc4d57d59a1fae1fc.patch create mode 100644 master/git-6ff9c2e7fa8ca63a575792534b63c5092099c286.patch create mode 100644 master/git-fa4a7ef36ec834fee1719636b30d2f28f4cb0166.patch create mode 100644 master/git-ffd71da4e3f323b7673b061e6f7e0d0c12dc2b49.patch create mode 100644 master/ibft-find.patch create mode 100644 master/igb-1.3.28.4.patch create mode 100644 master/increase-maximum-number-of-loop-devices create mode 100644 master/ixgbe-2.0.38.2.patch create mode 100644 master/kexec-larger-max-pfn-for-oldmem.patch create mode 100644 master/linux-2.6.18-xen.hg-918.71a61b393cdf create mode 100644 master/linux-2.6.27.25-0.1.1.patch create mode 100644 master/linux-2.6.27.29-0.1.1.patch create mode 100644 master/megaraid_sas-v00.00.04.12-compile-fix.patch create mode 100644 master/megaraid_sas-v00.00.04.12.patch create mode 100644 master/mlnx_en-1.4.1.patch create mode 100644 master/mlnx_en-fix-warnings.patch create mode 100644 master/mpt2sas-02.00.00.00.patch create mode 100644 master/mptlinux-4.20.00.01.patch create mode 100644 master/netback-call-skb_checksum_setup-at-receive.patch create mode 100644 master/netback-drop-xen-skb-members.patch create mode 100644 master/netback-force-CHECKSUM_PARTIAL-for-GSO.patch create mode 100644 master/netxen_nic-4.0.50.patch create mode 100644 master/pciback-flr-82599 create mode 100644 master/s2io-2-0-27-1.patch create mode 100644 master/s2io-2.1.37.17590.patch create mode 100644 master/s2io-2.1.37.18446.patch create mode 100644 master/s2io-fix-paths.patch create mode 100644 master/vswitch.patch create mode 100644 master/vxge-2.0.6.18061.patch diff --git a/master/CA-30778-backend-bound-sysfs.diff b/master/CA-30778-backend-bound-sysfs.diff new file mode 100644 index 0000000..bffbc67 --- /dev/null +++ b/master/CA-30778-backend-bound-sysfs.diff @@ -0,0 +1,119 @@ +CA-30778: Bind sysfs create/remove to backend init/exit + +Moves the per-backend sysfs create/remove code into backend +init/exit. Attribute existence bound to guest ring connection state +does not seem to serve any particular purpose, and keeping +backend_changed() small makes later extensions, such as switching the +physical node in VBD paused state, more straightforward. + +diff -r 336053aae576 drivers/xen/blkback/xenbus.c +--- a/drivers/xen/blkback/xenbus.c Wed Jul 15 17:20:14 2009 -0700 ++++ b/drivers/xen/blkback/xenbus.c Wed Jul 15 17:23:19 2009 -0700 +@@ -194,7 +194,7 @@ + VBD_SHOW(physical_device, "%x:%x\n", be->major, be->minor); + VBD_SHOW(mode, "%s\n", be->mode); + +-int xenvbd_sysfs_addif(struct xenbus_device *dev) ++static int xenvbd_sysfs_addif(struct xenbus_device *dev) + { + int error; + struct backend_info *be = dev->dev.driver_data; +@@ -221,7 +221,7 @@ + return error; + } + +-void xenvbd_sysfs_delif(struct xenbus_device *dev) ++static void xenvbd_sysfs_delif(struct xenbus_device *dev) + { + struct backend_info *be = dev->dev.driver_data; + if (be->group_added == 0) +@@ -341,8 +341,6 @@ + blkif->be->major = 0; + blkif->be->minor = 0; + blkif->remove_requested = 0; +- if (blkif->be->dev) +- xenvbd_sysfs_delif(blkif->be->dev); + + up(&blkback_dev_sem); + +@@ -516,6 +514,12 @@ + /* setup back pointer */ + be->blkif->be = be; + ++ err = xenvbd_sysfs_addif(dev); ++ if (err) { ++ xenbus_dev_fatal(dev, err, "creating sysfs entries"); ++ goto fail; ++ } ++ + err = xenbus_watch_path2(dev, dev->nodename, "physical-device", + &be->backend_watch, backend_changed); + if (err) +@@ -673,14 +677,6 @@ + if (err) + return; + +- err = xenvbd_sysfs_addif(dev); +- if (err) { +- vbd_free(&be->blkif->vbd); +- be->major = be->minor = 0; +- xenbus_dev_fatal(dev, err, "creating sysfs entries"); +- return; +- } +- + /* We're potentially connected now */ + update_blkif_status(be->blkif); + } +diff -r 336053aae576 drivers/xen/blktap/xenbus.c +--- a/drivers/xen/blktap/xenbus.c Wed Jul 15 17:20:14 2009 -0700 ++++ b/drivers/xen/blktap/xenbus.c Wed Jul 15 17:23:19 2009 -0700 +@@ -380,11 +380,6 @@ + tap_blkif_disconnect(blkif); + blkif->tapif->remove_requested = 0; + +- down(&blktap_dev_sem); +- if (blkif->be->dev) +- xentap_sysfs_delif(blkif->be->dev); +- up(&blktap_dev_sem); +- + backend_release(blkif->be); + blkif->xenblkd = NULL; + } +@@ -500,8 +495,6 @@ + + static void tap_update_blkif_status(blkif_t *blkif) + { +- int err; +- + /* Not ready to connect? */ + if(!blkif->irq || !blkif->sectors) { + return; +@@ -515,15 +508,6 @@ + connect(blkif->be); + if (blkif->be->dev->state != XenbusStateConnected) + return; +- +- if (!blkif->be->group_added) { +- err = xentap_sysfs_addif(blkif->be->dev); +- if (err) { +- xenbus_dev_fatal(blkif->be->dev, err, +- "creating sysfs entries"); +- return; +- } +- } + } + + int tap_blkif_connected(blkif_t *blkif) +@@ -584,6 +568,12 @@ + be->blkif->be = be; + be->blkif->sectors = 0; + ++ err = xentap_sysfs_addif(dev); ++ if (err) { ++ xenbus_dev_fatal(dev, err, "creating sysfs entries"); ++ goto fail; ++ } ++ + /* set a watch on disk info, waiting for userspace to update details*/ + err = xenbus_watch_path2(dev, dev->nodename, "info", + &be->backend_watch, tap_backend_changed); diff --git a/master/CA-30953-wild-ptr-deref.diff b/master/CA-30953-wild-ptr-deref.diff new file mode 100644 index 0000000..88aea34 --- /dev/null +++ b/master/CA-30953-wild-ptr-deref.diff @@ -0,0 +1,32 @@ +CA-30953: Fix dangling pointer deref after backend release. + +Call to backend_release() may free the blkif struct if the xenbus +device is already gone. Accessing xenblkd dereferences a dangling +pointer, so rather clear it beforehand. + +diff -r eb04d7ac9138 -r 1bd6fa33a406 drivers/xen/blkback/xenbus.c +--- a/drivers/xen/blkback/xenbus.c Wed Jul 15 17:31:27 2009 -0700 ++++ b/drivers/xen/blkback/xenbus.c Fri Jul 17 10:45:37 2009 -0700 +@@ -344,8 +344,8 @@ + + up(&blkback_dev_sem); + ++ blkif->xenblkd = NULL; + backend_release(blkif->be); +- blkif->xenblkd = NULL; + } + + static int xenbus_write_state(struct xenbus_device *dev, +diff -r eb04d7ac9138 -r 1bd6fa33a406 drivers/xen/blktap/xenbus.c +--- a/drivers/xen/blktap/xenbus.c Wed Jul 15 17:31:27 2009 -0700 ++++ b/drivers/xen/blktap/xenbus.c Fri Jul 17 10:45:37 2009 -0700 +@@ -380,8 +380,8 @@ + tap_blkif_disconnect(blkif); + blkif->tapif->remove_requested = 0; + ++ blkif->xenblkd = NULL; + backend_release(blkif->be); +- blkif->xenblkd = NULL; + } + + static int xenbus_write_state(struct xenbus_device *dev, diff --git a/master/CA-32254-shutdown-closed-backends.diff b/master/CA-32254-shutdown-closed-backends.diff new file mode 100644 index 0000000..26662d1 --- /dev/null +++ b/master/CA-32254-shutdown-closed-backends.diff @@ -0,0 +1,101 @@ +CA-32254: Fix shutdown-done-after-frontend-close. + + * Do *not* signal shutdown on kthread exit, notably frontend + disconnect. The backend remains ref'd. Xenstore observers might + draw the wrong conclusions. + + * But *if* there is a request, then *do* signal shutdown-done. + Immediately, even if the kthread is already gone. + +diff -r fdc7d8f7d93b drivers/xen/blktap/xenbus.c +--- a/drivers/xen/blktap/xenbus.c Wed Oct 07 20:42:54 2009 -0700 ++++ b/drivers/xen/blktap/xenbus.c Wed Oct 07 22:42:30 2009 -0700 +@@ -274,11 +274,16 @@ + be->group_added = 0; + } + ++static int kthread_running(struct backend_info *be) ++{ ++ return be->blkif && be->blkif->xenblkd; ++} ++ + static int kthread_remove(struct backend_info *be) + { + blkif_t *blkif = be->blkif; + +- if (!blkif || !blkif->xenblkd) ++ if (!kthread_running(be)) + return 0; + + blkif->tapif->remove_requested = 1; +@@ -287,10 +292,18 @@ + return -EBUSY; + } + +-static void signal_shutdown(struct backend_info *be) ++static void __signal_shutdown(struct backend_info *be) + { + int err; + ++ err = xenbus_write(XBT_NIL, be->nodename, "shutdown-done", ""); ++ if (err) ++ WPRINTK("Error writing shutdown-done for %s: %d\n", ++ be->nodename, err); ++} ++ ++static void signal_shutdown(struct backend_info *be) ++{ + down(&blktap_dev_sem); + + if (be->shutdown_signalled) +@@ -308,10 +321,8 @@ + the agent. any later write would risk recreating the + xenstore directory, racing against xenbus. */ + +- err = xenbus_write(XBT_NIL, be->nodename, "shutdown-done", ""); +- if (err) +- WPRINTK("Error writing shutdown-done for %s: %d\n", +- be->nodename, err); ++ if (be->shutdown_requested) ++ __signal_shutdown(be); + + be->shutdown_signalled = 1; + +@@ -419,9 +430,7 @@ + struct backend_info *be + = container_of(watch, struct backend_info, shutdown_watch); + struct xenbus_device *dev = be->dev; +- +- if (be->shutdown_signalled) +- return; ++ int shutdown_done; + + type = xenbus_read(XBT_NIL, dev->nodename, "shutdown-request", &len); + err = (IS_ERR(type) ? PTR_ERR(type) : 0); +@@ -434,17 +443,19 @@ + return; + } + +- xenbus_write_state(dev, XenbusStateClosing); +- +- be->shutdown_requested = BLKTAP_SHUTDOWN_NORMAL; +- + if (len == sizeof("force") - 1 && !memcmp(type, "force", len)) { + be->shutdown_requested = BLKTAP_SHUTDOWN_FORCE; +- if (!kthread_remove(be)) +- signal_shutdown(be); /* shutdown immediately */ ++ shutdown_done = !kthread_remove(be); ++ } else { ++ be->shutdown_requested = BLKTAP_SHUTDOWN_NORMAL; ++ shutdown_done = !kthread_running(be); + } ++ kfree(type); + +- kfree(type); ++ if (shutdown_done) ++ __signal_shutdown(be); ++ else ++ xenbus_write_state(dev, XenbusStateClosing); + } + + int signal_tapdisk(struct backend_info *be) diff --git a/master/CA-32943-wild-ptr-deref.diff b/master/CA-32943-wild-ptr-deref.diff new file mode 100644 index 0000000..052a1d5 --- /dev/null +++ b/master/CA-32943-wild-ptr-deref.diff @@ -0,0 +1,20 @@ +CA-32943: Fix dangling pointer deref after backdev release. + +A put_disk() before blk_cleanup_queue() would free gd before gd->queue +is read. + +diff -r ebd0574c414a drivers/xen/blktap/backdev.c +--- a/drivers/xen/blktap/backdev.c Mon Sep 21 16:09:37 2009 -0700 ++++ b/drivers/xen/blktap/backdev.c Tue Sep 22 17:16:52 2009 -0700 +@@ -99,10 +99,9 @@ + spin_unlock_irq(&backdev_io_lock); + + del_gendisk(info->gd); ++ blk_cleanup_queue(info->gd->queue); + put_disk(info->gd); + +- blk_cleanup_queue(info->gd->queue); +- + if (uinfo->blkif->xenblkd) + wake_up_process(uinfo->blkif->xenblkd); + diff --git a/master/CXD-99-gnterr-status.diff b/master/CXD-99-gnterr-status.diff new file mode 100644 index 0000000..cf9cd23 --- /dev/null +++ b/master/CXD-99-gnterr-status.diff @@ -0,0 +1,55 @@ +CXD-99: Make blkback/tap show op/status info for failing grant map ops. + +diff -r 7586d89f9254 drivers/xen/blkback/blkback.c +--- a/drivers/xen/blkback/blkback.c Tue Sep 08 15:21:57 2009 -0700 ++++ b/drivers/xen/blkback/blkback.c Tue Sep 08 15:23:01 2009 -0700 +@@ -557,7 +557,8 @@ + + for (i = 0; i < nseg; i++) { + if (unlikely(map[i].status != 0)) { +- DPRINTK("invalid buffer -- could not remap it\n"); ++ DPRINTK("grant map of dom %u gref %u failed: status %d\n", ++ blkif->domid, req->seg[i].gref, map[i].status); + map[i].handle = BLKBACK_INVALID_HANDLE; + ret |= 1; + continue; +diff -r 7586d89f9254 drivers/xen/blktap/blktap.c +--- a/drivers/xen/blktap/blktap.c Tue Sep 08 15:21:57 2009 -0700 ++++ b/drivers/xen/blktap/blktap.c Tue Sep 08 15:23:01 2009 -0700 +@@ -1288,15 +1288,19 @@ + kvaddr = idx_to_kaddr(mmap_idx, pending_idx, i/2); + + if (unlikely(map[i].status != 0)) { +- WPRINTK("invalid kernel buffer -- " +- "could not remap it\n"); ++ WPRINTK("grant map of dom %u gref %u failed:" ++ " status %d\n", ++ blkif->domid, req->seg[i].gref, ++ map[i].status); + ret |= 1; + map[i].handle = INVALID_GRANT_HANDLE; + } + + if (unlikely(map[i+1].status != 0)) { +- WPRINTK("invalid user buffer -- " +- "could not remap it\n"); ++ WPRINTK("grant map of dom %u gref %u failed:" ++ " status %d\n", ++ blkif->domid, req->seg[i+1].gref, ++ map[i+1].status); + ret |= 1; + map[i+1].handle = INVALID_GRANT_HANDLE; + } +@@ -1328,8 +1332,10 @@ + kvaddr = idx_to_kaddr(mmap_idx, pending_idx, i); + + if (unlikely(map[i].status != 0)) { +- WPRINTK("invalid kernel buffer -- " +- "could not remap it\n"); ++ WPRINTK("grant map of dom %u gref %u failed:" ++ " status %d\n", ++ blkif->domid, req->seg[i].gref, ++ map[i].status); + ret |= 1; + map[i].handle = INVALID_GRANT_HANDLE; + } diff --git a/master/blk-latency-stats b/master/blk-latency-stats index 28af96a..f0315ce 100644 --- a/master/blk-latency-stats +++ b/master/blk-latency-stats @@ -1,7 +1,7 @@ -diff -r 06f5ea5ad38a drivers/xen/blkback/blkback.c ---- a/drivers/xen/blkback/blkback.c Mon Apr 28 10:50:29 2008 -0700 -+++ b/drivers/xen/blkback/blkback.c Mon Apr 28 17:49:52 2008 -0700 -@@ -76,6 +76,7 @@ typedef struct { +diff -r 21a7f933b3c7 drivers/xen/blkback/blkback.c +--- a/drivers/xen/blkback/blkback.c Wed Jul 15 16:15:19 2009 -0700 ++++ b/drivers/xen/blkback/blkback.c Wed Jul 15 17:17:46 2009 -0700 +@@ -77,6 +77,7 @@ atomic_t pendcnt; unsigned short operation; int status; @@ -9,12 +9,10 @@ diff -r 06f5ea5ad38a drivers/xen/blkback/blkback.c struct list_head free_list; } pending_req_t; -@@ -182,6 +183,44 @@ static void fast_flush_area(pending_req_ - ret = HYPERVISOR_grant_table_op( - GNTTABOP_unmap_grant_ref, unmap, invcount); +@@ -185,6 +186,44 @@ BUG_ON(ret); -+} -+ + } + +static inline s64 timeval_to_us(struct timeval *tv) +{ + return ((s64)tv->tv_sec * USEC_PER_SEC) + tv->tv_usec; @@ -51,10 +49,12 @@ diff -r 06f5ea5ad38a drivers/xen/blkback/blkback.c + + *sum += interval; + *cnt += 1; - } - ++} ++ /****************************************************************** -@@ -323,6 +362,7 @@ static void __end_block_io_op(pending_re + * QUEUE MANAGEMENT FUNCTIONS + */ +@@ -324,6 +363,7 @@ blkif_t *blkif = pending_req->blkif; fast_flush_area(pending_req); @@ -62,7 +62,7 @@ diff -r 06f5ea5ad38a drivers/xen/blkback/blkback.c make_response(pending_req->blkif, pending_req->id, pending_req->operation, pending_req->status); blkif_put(pending_req->blkif); -@@ -488,6 +528,7 @@ static void dispatch_rw_block_io(blkif_t +@@ -489,6 +529,7 @@ pending_req->operation = req->operation; pending_req->status = BLKIF_RSP_OKAY; pending_req->nr_pages = nseg; @@ -70,10 +70,10 @@ diff -r 06f5ea5ad38a drivers/xen/blkback/blkback.c for (i = 0; i < nseg; i++) { uint32_t flags; -diff -r 06f5ea5ad38a drivers/xen/blkback/common.h ---- a/drivers/xen/blkback/common.h Mon Apr 28 10:50:29 2008 -0700 -+++ b/drivers/xen/blkback/common.h Mon Apr 28 17:49:52 2008 -0700 -@@ -104,6 +104,12 @@ typedef struct blkif_st { +diff -r 21a7f933b3c7 drivers/xen/blkback/common.h +--- a/drivers/xen/blkback/common.h Wed Jul 15 16:15:19 2009 -0700 ++++ b/drivers/xen/blkback/common.h Wed Jul 15 17:17:46 2009 -0700 +@@ -104,6 +104,12 @@ int st_br_req; int st_rd_sect; int st_wr_sect; @@ -86,10 +86,18 @@ diff -r 06f5ea5ad38a drivers/xen/blkback/common.h wait_queue_head_t waiting_to_free; -diff -r 06f5ea5ad38a drivers/xen/blkback/xenbus.c ---- a/drivers/xen/blkback/xenbus.c Mon Apr 28 10:50:29 2008 -0700 -+++ b/drivers/xen/blkback/xenbus.c Mon Apr 28 17:49:52 2008 -0700 -@@ -138,12 +138,51 @@ static void update_blkif_status(blkif_t +diff -r 21a7f933b3c7 drivers/xen/blkback/xenbus.c +--- a/drivers/xen/blkback/xenbus.c Wed Jul 15 16:15:19 2009 -0700 ++++ b/drivers/xen/blkback/xenbus.c Wed Jul 15 17:17:46 2009 -0700 +@@ -124,19 +124,50 @@ + struct device_attribute *attr, \ + char *buf) \ + { \ +- struct xenbus_device *dev = to_xenbus_device(_dev); \ +- struct backend_info *be = dev->dev.driver_data; \ +- \ ++ struct backend_info *be = _dev->driver_data; \ + return sprintf(buf, format, ##args); \ } \ static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL) @@ -100,28 +108,22 @@ diff -r 06f5ea5ad38a drivers/xen/blkback/xenbus.c + { \ + int ret = -ENODEV; \ + s64 cnt, sum, max; \ -+ struct backend_info *be; \ -+ struct xenbus_device *dev = to_xenbus_device(_dev); \ ++ struct backend_info *be = _dev->driver_data; \ + \ -+ down(&blkback_dev_sem); \ -+ be = dev->dev.driver_data; \ -+ if (be) { \ -+ cnt = _cnt; \ -+ sum = _sum; \ -+ max = _max; \ ++ cnt = _cnt; \ ++ sum = _sum; \ ++ max = _max; \ + \ -+ if (cnt) \ -+ do_div(sum, cnt); \ -+ ret = sprintf(buf, "requests: %lld, " \ -+ "avg usecs: %llu, " \ -+ "max usecs: %llu\n", \ -+ cnt, sum, max); \ ++ if (cnt) \ ++ do_div(sum, cnt); \ ++ ret = sprintf(buf, "requests: %lld, " \ ++ "avg usecs: %llu, " \ ++ "max usecs: %llu\n", \ ++ cnt, sum, max); \ + \ -+ (_sum) = 0; \ -+ (_cnt) = 0; \ -+ (_max) = 0; \ -+ } \ -+ up(&blkback_dev_sem); \ ++ (_sum) = 0; \ ++ (_cnt) = 0; \ ++ (_max) = 0; \ + \ + return ret; \ + } \ @@ -141,7 +143,7 @@ diff -r 06f5ea5ad38a drivers/xen/blkback/xenbus.c static struct attribute *vbdstat_attrs[] = { &dev_attr_oo_req.attr, -@@ -152,6 +191,8 @@ static struct attribute *vbdstat_attrs[] +@@ -145,6 +176,8 @@ &dev_attr_br_req.attr, &dev_attr_rd_sect.attr, &dev_attr_wr_sect.attr, @@ -150,10 +152,10 @@ diff -r 06f5ea5ad38a drivers/xen/blkback/xenbus.c NULL }; -diff -r 06f5ea5ad38a drivers/xen/blktap/backdev.c ---- a/drivers/xen/blktap/backdev.c Mon Apr 28 10:50:29 2008 -0700 -+++ b/drivers/xen/blktap/backdev.c Mon Apr 28 17:49:52 2008 -0700 -@@ -393,6 +393,7 @@ process_backdev_request(struct tap_blkif +diff -r 21a7f933b3c7 drivers/xen/blktap/backdev.c +--- a/drivers/xen/blktap/backdev.c Wed Jul 15 16:15:19 2009 -0700 ++++ b/drivers/xen/blktap/backdev.c Wed Jul 15 17:17:46 2009 -0700 +@@ -393,6 +393,7 @@ pending_req->operation = blkif_req.operation; pending_req->status = BLKIF_RSP_OKAY; pending_req->nr_pages = blkif_req.nr_segments; @@ -161,10 +163,10 @@ diff -r 06f5ea5ad38a drivers/xen/blktap/backdev.c /*record [mmap_idx,pending_idx] to [usr_idx] mapping*/ uinfo->idx_map[usr_idx] = MAKE_ID(mmap_idx, pending_idx); -diff -r 06f5ea5ad38a drivers/xen/blktap/blktap.c ---- a/drivers/xen/blktap/blktap.c Mon Apr 28 10:50:29 2008 -0700 -+++ b/drivers/xen/blktap/blktap.c Mon Apr 28 17:49:52 2008 -0700 -@@ -853,6 +853,42 @@ static void fast_flush_area(pending_req_ +diff -r 21a7f933b3c7 drivers/xen/blktap/blktap.c +--- a/drivers/xen/blktap/blktap.c Wed Jul 15 16:15:19 2009 -0700 ++++ b/drivers/xen/blktap/blktap.c Wed Jul 15 17:17:46 2009 -0700 +@@ -855,6 +855,42 @@ req->nr_pages << PAGE_SHIFT, NULL); } @@ -207,7 +209,7 @@ diff -r 06f5ea5ad38a drivers/xen/blktap/blktap.c /****************************************************************** * SCHEDULER FUNCTIONS */ -@@ -995,6 +1031,7 @@ static int blktap_read_ufe_ring(tap_blki +@@ -997,6 +1033,7 @@ ID_TO_IDX(info->idx_map[usr_idx]))); pending_req = &pending_reqs[mmap_idx][pending_idx]; @@ -215,7 +217,7 @@ diff -r 06f5ea5ad38a drivers/xen/blktap/blktap.c if (pending_req->inuse == 2) backdev_finish_req(info, usr_idx, &res, pending_req); -@@ -1169,6 +1206,8 @@ static void dispatch_rw_block_io(blkif_t +@@ -1189,6 +1226,8 @@ pending_req->operation = operation; pending_req->status = BLKIF_RSP_OKAY; pending_req->nr_pages = nseg; @@ -224,10 +226,10 @@ diff -r 06f5ea5ad38a drivers/xen/blktap/blktap.c op = 0; for (i = 0; i < nseg; i++) { unsigned long uvaddr; -diff -r 06f5ea5ad38a drivers/xen/blktap/blktap.h ---- a/drivers/xen/blktap/blktap.h Mon Apr 28 10:50:29 2008 -0700 -+++ b/drivers/xen/blktap/blktap.h Mon Apr 28 17:49:52 2008 -0700 -@@ -76,6 +76,7 @@ typedef struct pending_req { +diff -r 21a7f933b3c7 drivers/xen/blktap/blktap.h +--- a/drivers/xen/blktap/blktap.h Wed Jul 15 16:15:19 2009 -0700 ++++ b/drivers/xen/blktap/blktap.h Wed Jul 15 17:17:46 2009 -0700 +@@ -77,6 +77,7 @@ int status; struct list_head free_list; int inuse; @@ -235,10 +237,10 @@ diff -r 06f5ea5ad38a drivers/xen/blktap/blktap.h } pending_req_t; extern pending_req_t *pending_reqs[MAX_PENDING_REQS]; -diff -r 06f5ea5ad38a drivers/xen/blktap/common.h ---- a/drivers/xen/blktap/common.h Mon Apr 28 10:50:29 2008 -0700 -+++ b/drivers/xen/blktap/common.h Mon Apr 28 17:49:52 2008 -0700 -@@ -81,6 +81,12 @@ typedef struct blkif_st { +diff -r 21a7f933b3c7 drivers/xen/blktap/common.h +--- a/drivers/xen/blktap/common.h Wed Jul 15 16:15:19 2009 -0700 ++++ b/drivers/xen/blktap/common.h Wed Jul 15 17:17:46 2009 -0700 +@@ -81,6 +81,12 @@ int st_oo_req; int st_rd_sect; int st_wr_sect; @@ -251,49 +253,57 @@ diff -r 06f5ea5ad38a drivers/xen/blktap/common.h wait_queue_head_t waiting_to_free; -diff -r 06f5ea5ad38a drivers/xen/blktap/xenbus.c ---- a/drivers/xen/blktap/xenbus.c Mon Apr 28 10:50:29 2008 -0700 -+++ b/drivers/xen/blktap/xenbus.c Mon Apr 28 17:49:52 2008 -0700 -@@ -201,11 +201,49 @@ static int blktap_name(blkif_t *blkif, c - } \ - static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL) +diff -r 21a7f933b3c7 drivers/xen/blktap/xenbus.c +--- a/drivers/xen/blktap/xenbus.c Wed Jul 15 16:15:19 2009 -0700 ++++ b/drivers/xen/blktap/xenbus.c Wed Jul 15 17:17:46 2009 -0700 +@@ -182,15 +182,41 @@ + * sysfs interface for I/O requests of blktap device + */ +-#define VBD_SHOW(name, format, args...) \ +- static ssize_t show_##name(struct device *_dev, \ ++#define VBD_SHOW(name, format, args...) \ ++ static ssize_t show_##name(struct device *_dev, \ + struct device_attribute *attr, \ + char *buf) \ + { \ +- struct xenbus_device *dev = to_xenbus_device(_dev); \ +- struct backend_info *be = dev->dev.driver_data; \ ++ struct backend_info *be = _dev->driver_data; \ ++ return sprintf(buf, format, ##args); \ ++ } \ ++ static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL) ++ +#define VBD_SHOW_AVG(name, _cnt, _sum, _max) \ -+ static ssize_t show_##name(struct device *_dev, \ ++ static ssize_t show_##name(struct device *_dev, \ + struct device_attribute *attr, \ + char *buf) \ + { \ -+ int ret = -ENODEV; \ ++ int ret; \ + s64 cnt, sum, max; \ -+ struct backend_info *be; \ -+ struct xenbus_device *dev = to_xenbus_device(_dev); \ ++ struct backend_info *be = _dev->driver_data; \ + \ +- return sprintf(buf, format, ##args); \ ++ cnt = _cnt; \ ++ sum = _sum; \ ++ max = _max; \ + \ -+ down(&blktap_dev_sem); \ -+ be = dev->dev.driver_data; \ -+ if (be) { \ -+ cnt = _cnt; \ -+ sum = _sum; \ -+ max = _max; \ ++ if (cnt) \ ++ do_div(sum, cnt); \ ++ ret = sprintf(buf, "requests: %lld, " \ ++ "avg usecs: %llu, " \ ++ "max usecs: %llu\n", \ ++ cnt, sum, max); \ + \ -+ if (cnt) \ -+ do_div(sum, cnt); \ -+ ret = sprintf(buf, "requests: %lld, " \ -+ "avg usecs: %llu, " \ -+ "max usecs: %llu\n", \ -+ cnt, sum, max); \ -+ \ -+ (_sum) = 0; \ -+ (_cnt) = 0; \ -+ (_max) = 0; \ -+ } \ -+ up(&blktap_dev_sem); \ ++ (_sum) = 0; \ ++ (_cnt) = 0; \ ++ (_max) = 0; \ + \ + return ret; \ -+ } \ -+ static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL) -+ - VBD_SHOW(oo_req, "%d\n", be->blkif->st_oo_req); - VBD_SHOW(rd_req, "%d\n", be->blkif->st_rd_req); + } \ + static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL) + +@@ -199,6 +225,10 @@ VBD_SHOW(wr_req, "%d\n", be->blkif->st_wr_req); VBD_SHOW(rd_sect, "%d\n", be->blkif->st_rd_sect); VBD_SHOW(wr_sect, "%d\n", be->blkif->st_wr_sect); @@ -304,7 +314,7 @@ diff -r 06f5ea5ad38a drivers/xen/blktap/xenbus.c static struct attribute *tapstat_attrs[] = { &dev_attr_oo_req.attr, -@@ -213,6 +251,8 @@ static struct attribute *tapstat_attrs[] +@@ -206,6 +236,8 @@ &dev_attr_wr_req.attr, &dev_attr_rd_sect.attr, &dev_attr_wr_sect.attr, diff --git a/master/blkback-pagemap-cleanup.diff b/master/blkback-pagemap-cleanup.diff new file mode 100644 index 0000000..49aa787 --- /dev/null +++ b/master/blkback-pagemap-cleanup.diff @@ -0,0 +1,43 @@ +CXD-99: grantmap entries save grep/handle pairs, not bus/device ids. + +diff -r 0701b452ff02 -r b4005ea35061 drivers/xen/blkback/blkback-pagemap.c +--- a/drivers/xen/blkback/blkback-pagemap.c Fri Sep 04 13:41:50 2009 -0700 ++++ b/drivers/xen/blkback/blkback-pagemap.c Fri Sep 04 13:51:43 2009 -0700 +@@ -25,7 +25,7 @@ + + void + blkback_pagemap_set(int idx, struct page *page, +- domid_t domid, busid_t busid, grant_ref_t gref) ++ domid_t domid, grant_handle_t handle, grant_ref_t gref) + { + struct blkback_pagemap *entry; + +@@ -37,13 +37,13 @@ + + entry = blkback_pagemap + idx; + if (!blkback_pagemap_entry_clear(entry)) { +- printk("overwriting pagemap %d: d %u b %u g %u\n", +- idx, entry->domid, entry->busid, entry->gref); ++ printk("overwriting pagemap %d: d %u h %u g %u\n", ++ idx, entry->domid, entry->handle, entry->gref); + BUG(); + } + + entry->domid = domid; +- entry->busid = busid; ++ entry->handle = handle; + entry->gref = gref; + } + +diff -r 0701b452ff02 -r b4005ea35061 drivers/xen/blkback/blkback-pagemap.h +--- a/drivers/xen/blkback/blkback-pagemap.h Fri Sep 04 13:41:50 2009 -0700 ++++ b/drivers/xen/blkback/blkback-pagemap.h Fri Sep 04 13:51:43 2009 -0700 +@@ -8,7 +8,7 @@ + + struct blkback_pagemap { + domid_t domid; +- busid_t busid; ++ grant_handle_t handle; + grant_ref_t gref; + }; + diff --git a/master/blktap-initwait-fix b/master/blktap-initwait-fix new file mode 100755 index 0000000..33e8410 --- /dev/null +++ b/master/blktap-initwait-fix @@ -0,0 +1,278 @@ +diff -r 2998321447f6 drivers/xen/blktap/blktap.c +--- a/drivers/xen/blktap/blktap.c Tue Aug 11 17:59:10 2009 +0100 ++++ b/drivers/xen/blktap/blktap.c Fri Aug 14 18:14:17 2009 +0100 +@@ -935,8 +935,7 @@ + + create_backdev(info); + +- if (debug_lvl) +- printk(KERN_DEBUG "%s: started\n", current->comm); ++ printk(KERN_INFO "%s[%d]: starting\n", __FUNCTION__, current->pid); + + while (1) { + if (try_to_freeze()) +@@ -984,8 +983,8 @@ + + if (log_stats) + print_stats(blkif); +- if (debug_lvl) +- printk(KERN_DEBUG "%s: exiting\n", current->comm); ++ ++ printk(KERN_INFO "%s[%d]: exiting\n", __FUNCTION__, current->pid); + + backdev_end_requests(info); + if (info->backdev) +diff -r 2998321447f6 drivers/xen/blktap/xenbus.c +--- a/drivers/xen/blktap/xenbus.c Tue Aug 11 17:59:10 2009 +0100 ++++ b/drivers/xen/blktap/xenbus.c Fri Aug 14 18:14:17 2009 +0100 +@@ -299,8 +299,10 @@ + if (be->blkif) + disassociate_blkif(be->blkif->domid, be->xenbus_id); + +- if (be->dev) ++ if (be->dev) { + xenbus_switch_state(be->dev, XenbusStateClosed); ++ DPRINTK("backend closed: %s\n", be->nodename); ++ } + + /* NB. shutdown-done goes last: it triggers our deletion by + the agent. any later write would risk recreating the +@@ -459,6 +461,46 @@ + return err; + } + ++static void start_tapdisk(struct xenbus_device *dev) ++{ ++ struct xenbus_transaction xbt; ++ int junk; ++ int err; ++ ++again: ++ err = xenbus_transaction_start(&xbt); ++ if (err) { ++ xenbus_dev_fatal(dev, err, "starting transaction"); ++ return; ++ } ++ ++ err = xenbus_scanf(xbt, dev->nodename, "start-tapdisk", "%d", &junk); ++ if (!XENBUS_EXIST_ERR(err)) { ++ WPRINTK("%s: tapdisk already started\n", dev->nodename); ++ xenbus_transaction_end(xbt, 1); ++ return; ++ } ++ ++ printk(KERN_INFO "%s: %s: starting tapdisk\n", ++ __FUNCTION__, dev->nodename); ++ ++ err = xenbus_write(xbt, dev->nodename, "start-tapdisk", "1"); ++ if (err) { ++ xenbus_dev_fatal(dev, err, "starting tapdisk"); ++ xenbus_transaction_end(xbt, 1); ++ return; ++ } ++ ++ err = xenbus_transaction_end(xbt, 0); ++ if (err) { ++ if (err == -EAGAIN) ++ goto again; ++ ++ xenbus_dev_fatal(dev, err, "completing transaction"); ++ return; ++ } ++} ++ + static void blktap_reconnect(struct backend_info *be) + { + int err; +@@ -486,11 +528,11 @@ + be->shutdown_requested = 0; + be->shutdown_signalled = 0; + +- xenbus_switch_state(dev, XenbusStateInitWait); ++ err = xenbus_switch_state(dev, XenbusStateInitialising); ++ if (err) ++ xenbus_dev_fatal(be->dev, err, "changing state"); + +- err = xenbus_write(XBT_NIL, be->nodename, "start-tapdisk", ""); +- if (err) +- xenbus_dev_fatal(be->dev, err, "restarting tapdisk"); ++ start_tapdisk(dev); + } + + static void tap_update_blkif_status(blkif_t *blkif) +@@ -522,11 +564,18 @@ + * InitWait. + */ + static int blktap_probe(struct xenbus_device *dev, +- const struct xenbus_device_id *id) ++ const struct xenbus_device_id *id) + { + int err; +- struct backend_info *be = kzalloc(sizeof(struct backend_info), +- GFP_KERNEL); ++ struct backend_info *be; ++ ++ if (dev->state != XenbusStateInitialising) { ++ xenbus_dev_fatal(dev, -EINVAL, ++ "bad device state"); ++ return -EINVAL; ++ } ++ ++ be = kzalloc(sizeof(struct backend_info), GFP_KERNEL); + if (!be) { + xenbus_dev_fatal(dev, -ENOMEM, + "allocating backend structure"); +@@ -590,13 +639,7 @@ + if (err) + goto fail; + +- err = xenbus_switch_state(dev, XenbusStateInitWait); +- if (err) +- goto fail; +- +- err = xenbus_write(XBT_NIL, dev->nodename, "start-tapdisk", ""); +- if (err) +- goto fail; ++ start_tapdisk(dev); + + return 0; + +@@ -619,6 +662,7 @@ + struct backend_info *be + = container_of(watch, struct backend_info, backend_watch); + struct xenbus_device *dev = be->dev; ++ char name[TASK_COMM_LEN]; + + DPRINTK("tap_backend_changed %s\n", vec[XS_WATCH_PATH]); + +@@ -628,16 +672,19 @@ + */ + err = xenbus_gather(XBT_NIL, dev->nodename, "info", "%lu", &info, + NULL); +- if (XENBUS_EXIST_ERR(err)) ++ if (XENBUS_EXIST_ERR(err)) { ++ DPRINTK("%s/info: not found\n", dev->nodename); + return; ++ } + if (err) { + xenbus_dev_error(dev, err, "getting info"); + return; + } + +- if (dev->state != XenbusStateInitWait) { +- WPRINTK("%s: tapdisk ready, but blktap at %s\n", +- __func__, xenbus_strstate(dev->state)); ++ if (dev->state != XenbusStateInitialising) { ++ WPRINTK("%s: tapdisk ready, but blktap in state %s\n", ++ __FUNCTION__, xenbus_strstate(dev->state)); ++ kobject_uevent(&be->dev->dev.kobj, KOBJ_CHANGE); + return; + } + +@@ -648,48 +695,61 @@ + return; + } + +- if (be->blkif->xenblkd == NULL) { +- char name[TASK_COMM_LEN]; ++ if (be->blkif->xenblkd != NULL) { ++ WPRINTK("%s: thread %d already running\n", ++ __FUNCTION__, be->blkif->xenblkd->pid); ++ goto done; ++ } + +- /* Associate blkif with tap_blkif */ +- be->blkif->tapif = associate_blkif(be->blkif->domid, +- be->xenbus_id, be->blkif); +- if (be->blkif->tapif == NULL) { +- xenbus_dev_error(be->dev, err, "associate blkif"); +- return; +- } ++ /* Associate blkif with tap_blkif */ ++ be->blkif->tapif = associate_blkif(be->blkif->domid, ++ be->xenbus_id, be->blkif); ++ if (be->blkif->tapif == NULL) { ++ xenbus_dev_error(be->dev, err, "associate blkif"); ++ return; ++ } + +- /* Create name */ +- err = blktap_name(be->blkif, name); +- if (err) { +- xenbus_dev_error(be->dev, err, "get blktap dev name"); +- return; +- } ++ /* Create name */ ++ err = blktap_name(be->blkif, name); ++ if (err) { ++ xenbus_dev_error(be->dev, err, "get blktap dev name"); ++ return; ++ } + +- /* Create kernel thread */ +- be->blkif->xenblkd = kthread_run(tap_blkif_schedule, be->blkif, +- name); +- if (IS_ERR(be->blkif->xenblkd)) { +- err = PTR_ERR(be->blkif->xenblkd); +- be->blkif->xenblkd = NULL; +- xenbus_dev_fatal(be->dev, err, "start xenblkd"); +- WPRINTK("Error starting thread\n"); +- return; +- } ++ /* Create kernel thread */ ++ be->blkif->xenblkd = kthread_run(tap_blkif_schedule, be->blkif, ++ name); ++ if (IS_ERR(be->blkif->xenblkd)) { ++ err = PTR_ERR(be->blkif->xenblkd); ++ be->blkif->xenblkd = NULL; ++ xenbus_dev_fatal(be->dev, err, "start xenblkd"); ++ WPRINTK("%s: error starting thread\n", __FUNCTION__); ++ return; ++ } + +- atomic_inc(&be->refcnt); +- be->kthread_pid = be->blkif->xenblkd->pid; ++ atomic_inc(&be->refcnt); ++ be->kthread_pid = be->blkif->xenblkd->pid; + +- err = xenbus_printf(XBT_NIL, dev->nodename, "kthread-pid", +- "%d", be->blkif->xenblkd->pid); +- if (err) { +- xenbus_dev_error(be->dev, err, "write kthread-pid"); +- return; +- } ++ err = xenbus_printf(XBT_NIL, dev->nodename, "kthread-pid", ++ "%d", be->blkif->xenblkd->pid); ++ if (err) { ++ xenbus_dev_error(be->dev, err, "write kthread-pid"); ++ return; ++ } + +- DPRINTK("tap_backend_changed created thread %s\n", name); +- kobject_uevent(&be->dev->dev.kobj, KOBJ_CHANGE); ++ printk(KERN_INFO "%s: %s: created thread %d\n", ++ __FUNCTION__, dev->nodename, be->blkif->xenblkd->pid); ++ ++ err = xenbus_rm(XBT_NIL, dev->nodename, "start-tapdisk"); ++ if (err) { ++ xenbus_dev_fatal(dev, err, "removing start-tapdisk"); ++ return; + } ++ ++ xenbus_switch_state(dev, XenbusStateInitWait); ++ kobject_uevent(&be->dev->dev.kobj, KOBJ_CHANGE); ++ ++done: + tap_update_blkif_status(be->blkif); + } + +@@ -720,7 +780,8 @@ + /* Ensure we connect even when two watches fire in + close successsion and we miss the intermediate value + of frontend_state. */ +- if (dev->state != XenbusStateConnected && dev->state != XenbusStateClosing) { ++ if (dev->state != XenbusStateConnected && ++ dev->state != XenbusStateClosing) { + err = connect_ring(be); + if (err) + break; diff --git a/master/bnx2-1.9.20b.patch b/master/bnx2-1.9.20b.patch new file mode 100644 index 0000000..625f04c --- /dev/null +++ b/master/bnx2-1.9.20b.patch @@ -0,0 +1,33329 @@ +diff -r 5f108bc568be drivers/net/5710_hsi_cnic.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/5710_hsi_cnic.h Tue Sep 01 13:50:08 2009 +0100 +@@ -0,0 +1,2936 @@ ++#ifndef __5710_HSI_CNIC_LE__ ++#define __5710_HSI_CNIC_LE__ ++ ++/* ++ * common data for all protocols ++ */ ++struct b577xx_doorbell_hdr { ++ u8 header; ++#define B577XX_DOORBELL_HDR_RX (0x1<<0) ++#define B577XX_DOORBELL_HDR_RX_SHIFT 0 ++#define B577XX_DOORBELL_HDR_DB_TYPE (0x1<<1) ++#define B577XX_DOORBELL_HDR_DB_TYPE_SHIFT 1 ++#define B577XX_DOORBELL_HDR_DPM_SIZE (0x3<<2) ++#define B577XX_DOORBELL_HDR_DPM_SIZE_SHIFT 2 ++#define B577XX_DOORBELL_HDR_CONN_TYPE (0xF<<4) ++#define B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT 4 ++}; ++ ++/* ++ * doorbell message sent to the chip ++ */ ++struct b577xx_doorbell { ++#if defined(__BIG_ENDIAN) ++ u16 zero_fill2; ++ u8 zero_fill1; ++ struct b577xx_doorbell_hdr header; ++#elif defined(__LITTLE_ENDIAN) ++ struct b577xx_doorbell_hdr header; ++ u8 zero_fill1; ++ u16 zero_fill2; ++#endif ++}; ++ ++/* ++ * iSCSI context region, used only in iSCSI ++ */ ++struct ustorm_iscsi_rq_db { ++ struct regpair pbl_base; ++ struct regpair curr_pbe; ++}; ++ ++/* ++ * iSCSI context region, used only in iSCSI ++ */ ++struct ustorm_iscsi_r2tq_db { ++ struct regpair pbl_base; ++ struct regpair curr_pbe; ++}; ++ ++/* ++ * iSCSI context region, used only in iSCSI ++ */ ++struct ustorm_iscsi_cq_db { ++#if defined(__BIG_ENDIAN) ++ u16 cq_sn; ++ u16 prod; ++#elif defined(__LITTLE_ENDIAN) ++ u16 prod; ++ u16 cq_sn; ++#endif ++ struct regpair curr_pbe; ++}; ++ ++/* ++ * iSCSI context region, used only in iSCSI ++ */ ++struct rings_db { ++ struct ustorm_iscsi_rq_db rq; ++ struct ustorm_iscsi_r2tq_db r2tq; ++ struct ustorm_iscsi_cq_db cq[8]; ++#if defined(__BIG_ENDIAN) ++ u16 rq_prod; ++ u16 r2tq_prod; ++#elif defined(__LITTLE_ENDIAN) ++ u16 r2tq_prod; ++ u16 rq_prod; ++#endif ++ struct regpair cq_pbl_base; ++}; ++ ++/* ++ * iSCSI context region, used only in iSCSI ++ */ ++struct ustorm_iscsi_placement_db { ++ u32 sgl_base_lo; ++ u32 sgl_base_hi; ++ u32 local_sge_0_address_hi; ++ u32 local_sge_0_address_lo; ++#if defined(__BIG_ENDIAN) ++ u16 curr_sge_offset; ++ u16 local_sge_0_size; ++#elif defined(__LITTLE_ENDIAN) ++ u16 local_sge_0_size; ++ u16 curr_sge_offset; ++#endif ++ u32 local_sge_1_address_hi; ++ u32 local_sge_1_address_lo; ++#if defined(__BIG_ENDIAN) ++ u16 reserved6; ++ u16 local_sge_1_size; ++#elif defined(__LITTLE_ENDIAN) ++ u16 local_sge_1_size; ++ u16 reserved6; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 sgl_size; ++ u8 local_sge_index_2b; ++ u16 reserved7; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved7; ++ u8 local_sge_index_2b; ++ u8 sgl_size; ++#endif ++ u32 rem_pdu; ++ u32 place_db_bitfield_1; ++#define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0) ++#define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0 ++#define USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24) ++#define USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT 24 ++ u32 place_db_bitfield_2; ++#define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0) ++#define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0 ++#define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24) ++#define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT 24 ++ u32 nal; ++#define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0) ++#define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0 ++#define USTORM_ISCSI_PLACEMENT_DB_EXP_PADDING_2B (0x3<<24) ++#define USTORM_ISCSI_PLACEMENT_DB_EXP_PADDING_2B_SHIFT 24 ++#define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0x7<<26) ++#define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT 26 ++#define USTORM_ISCSI_PLACEMENT_DB_NAL_LEN_3B (0x7<<29) ++#define USTORM_ISCSI_PLACEMENT_DB_NAL_LEN_3B_SHIFT 29 ++}; ++ ++/* ++ * Ustorm iSCSI Storm Context ++ */ ++struct ustorm_iscsi_st_context { ++ u32 exp_stat_sn; ++ u32 exp_data_sn; ++ struct rings_db ring; ++ struct regpair task_pbl_base; ++ struct regpair tce_phy_addr; ++ struct ustorm_iscsi_placement_db place_db; ++ u32 data_rcv_seq; ++ u32 rem_rcv_len; ++#if defined(__BIG_ENDIAN) ++ u16 hdr_itt; ++ u16 iscsi_conn_id; ++#elif defined(__LITTLE_ENDIAN) ++ u16 iscsi_conn_id; ++ u16 hdr_itt; ++#endif ++ u32 nal_bytes; ++#if defined(__BIG_ENDIAN) ++ u8 hdr_second_byte_union; ++ u8 bitfield_0; ++#define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) ++#define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0 ++#define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) ++#define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1 ++#define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x3F<<2) ++#define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 2 ++ u8 task_pdu_cache_index; ++ u8 task_pbe_cache_index; ++#elif defined(__LITTLE_ENDIAN) ++ u8 task_pbe_cache_index; ++ u8 task_pdu_cache_index; ++ u8 bitfield_0; ++#define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) ++#define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0 ++#define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) ++#define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1 ++#define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x3F<<2) ++#define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 2 ++ u8 hdr_second_byte_union; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 reserved3; ++ u8 reserved2; ++ u8 acDecrement; ++#elif defined(__LITTLE_ENDIAN) ++ u8 acDecrement; ++ u8 reserved2; ++ u16 reserved3; ++#endif ++ u32 task_stat; ++#if defined(__BIG_ENDIAN) ++ u8 hdr_opcode; ++ u8 num_cqs; ++ u16 reserved5; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved5; ++ u8 num_cqs; ++ u8 hdr_opcode; ++#endif ++ u32 negotiated_rx; ++#define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0) ++#define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0 ++#define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24) ++#define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT 24 ++ u32 negotiated_rx_and_flags; ++#define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0) ++#define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0 ++#define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24) ++#define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT 24 ++#define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25) ++#define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT 25 ++#define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26) ++#define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT 26 ++#define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27) ++#define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT 27 ++#define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28) ++#define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT 28 ++#define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE (0x3<<29) ++#define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT 29 ++#define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31) ++#define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT 31 ++}; ++ ++/* ++ * TCP context region, shared in TOE, RDMA and ISCSI ++ */ ++struct tstorm_tcp_st_context_section { ++ u32 flags1; ++#define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_20B (0xFFFFFF<<0) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_20B_SHIFT 0 ++#define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT 24 ++#define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT 25 ++#define TSTORM_TCP_ST_CONTEXT_SECTION_ISLE_EXISTS (0x1<<26) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_ISLE_EXISTS_SHIFT 26 ++#define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT 27 ++#define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT 28 ++#define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT 29 ++#define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT 30 ++#define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED3 (0x1<<31) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED3_SHIFT 31 ++ u32 flags2; ++#define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_20B (0xFFFFFF<<0) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_20B_SHIFT 0 ++#define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT 24 ++#define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT 25 ++#define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26) ++#define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT_SHIFT 26 ++#define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27) ++#define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT_SHIFT 27 ++#define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 28 ++#define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29) ++#define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 29 ++#define __TSTORM_TCP_ST_CONTEXT_SECTION_SECOND_ISLE_DROPPED (0x1<<30) ++#define __TSTORM_TCP_ST_CONTEXT_SECTION_SECOND_ISLE_DROPPED_SHIFT 30 ++#define __TSTORM_TCP_ST_CONTEXT_SECTION_DONT_SUPPORT_OOO (0x1<<31) ++#define __TSTORM_TCP_ST_CONTEXT_SECTION_DONT_SUPPORT_OOO_SHIFT 31 ++#if defined(__BIG_ENDIAN) ++ u16 reserved_slowpath; ++ u8 tcp_sm_state_3b; ++ u8 rto_exp_3b; ++#elif defined(__LITTLE_ENDIAN) ++ u8 rto_exp_3b; ++ u8 tcp_sm_state_3b; ++ u16 reserved_slowpath; ++#endif ++ u32 rcv_nxt; ++ u32 timestamp_recent; ++ u32 timestamp_recent_time; ++ u32 cwnd; ++ u32 ss_thresh; ++ u32 cwnd_accum; ++ u32 prev_seg_seq; ++ u32 expected_rel_seq; ++ u32 recover; ++#if defined(__BIG_ENDIAN) ++ u8 retransmit_count; ++ u8 ka_max_probe_count; ++ u8 persist_probe_count; ++ u8 ka_probe_count; ++#elif defined(__LITTLE_ENDIAN) ++ u8 ka_probe_count; ++ u8 persist_probe_count; ++ u8 ka_max_probe_count; ++ u8 retransmit_count; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 statistics_counter_id; ++ u8 ooo_support_mode; ++ u8 snd_wnd_scale_4b; ++ u8 dup_ack_count; ++#elif defined(__LITTLE_ENDIAN) ++ u8 dup_ack_count; ++ u8 snd_wnd_scale_4b; ++ u8 ooo_support_mode; ++ u8 statistics_counter_id; ++#endif ++ u32 retransmit_start_time; ++ u32 ka_timeout; ++ u32 ka_interval; ++ u32 isle_start_seq; ++ u32 isle_end_seq; ++#if defined(__BIG_ENDIAN) ++ u16 mss; ++ u16 recent_seg_wnd; ++#elif defined(__LITTLE_ENDIAN) ++ u16 recent_seg_wnd; ++ u16 mss; ++#endif ++ u32 reserved4; ++ u32 max_rt_time; ++#if defined(__BIG_ENDIAN) ++ u16 lsb_mac_address; ++ u16 vlan_id; ++#elif defined(__LITTLE_ENDIAN) ++ u16 vlan_id; ++ u16 lsb_mac_address; ++#endif ++ u32 msb_mac_address; ++ u32 reserved2; ++}; ++ ++/* ++ * Termination variables ++ */ ++struct iscsi_term_vars { ++ u8 BitMap; ++#define ISCSI_TERM_VARS_TCP_STATE (0xF<<0) ++#define ISCSI_TERM_VARS_TCP_STATE_SHIFT 0 ++#define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4) ++#define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4 ++#define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5) ++#define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5 ++#define ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6) ++#define ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT 6 ++#define ISCSI_TERM_VARS_RSRV (0x1<<7) ++#define ISCSI_TERM_VARS_RSRV_SHIFT 7 ++}; ++ ++/* ++ * iSCSI context region, used only in iSCSI ++ */ ++struct tstorm_iscsi_st_context_section { ++#if defined(__BIG_ENDIAN) ++ u16 rem_tcp_data_len; ++ u16 brb_offset; ++#elif defined(__LITTLE_ENDIAN) ++ u16 brb_offset; ++ u16 rem_tcp_data_len; ++#endif ++ u32 b2nh; ++#if defined(__BIG_ENDIAN) ++ u16 rq_cons; ++ u8 flags; ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0 ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1 ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2 ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3 ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4 ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_FLAGS_RSRV (0x7<<5) ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_FLAGS_RSRV_SHIFT 5 ++ u8 hdr_bytes_2_fetch; ++#elif defined(__LITTLE_ENDIAN) ++ u8 hdr_bytes_2_fetch; ++ u8 flags; ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0 ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1 ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2 ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3 ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4 ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_FLAGS_RSRV (0x7<<5) ++#define TSTORM_ISCSI_ST_CONTEXT_SECTION_FLAGS_RSRV_SHIFT 5 ++ u16 rq_cons; ++#endif ++ struct regpair rq_db_phy_addr; ++#if defined(__BIG_ENDIAN) ++ struct iscsi_term_vars term_vars; ++ u8 scratchpad_idx; ++ u16 iscsi_conn_id; ++#elif defined(__LITTLE_ENDIAN) ++ u16 iscsi_conn_id; ++ u8 scratchpad_idx; ++ struct iscsi_term_vars term_vars; ++#endif ++ u32 reserved2; ++}; ++ ++/* ++ * The iSCSI non-aggregative context of Tstorm ++ */ ++struct tstorm_iscsi_st_context { ++ struct tstorm_tcp_st_context_section tcp; ++ struct tstorm_iscsi_st_context_section iscsi; ++}; ++ ++/* ++ * The tcp aggregative context section of Xstorm ++ */ ++struct xstorm_tcp_tcp_ag_context_section { ++#if defined(__BIG_ENDIAN) ++ u8 __tcp_agg_vars1; ++ u8 __da_cnt; ++ u16 mss; ++#elif defined(__LITTLE_ENDIAN) ++ u16 mss; ++ u8 __da_cnt; ++ u8 __tcp_agg_vars1; ++#endif ++ u32 snd_nxt; ++ u32 tx_wnd; ++ u32 snd_una; ++ u32 local_adv_wnd; ++#if defined(__BIG_ENDIAN) ++ u8 __agg_val8_th; ++ u8 __agg_val8; ++ u16 tcp_agg_vars2; ++#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) ++#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 ++#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) ++#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_CF_EN (0x1<<7) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_CF_EN_SHIFT 7 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX8_CF (0x3<<14) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX8_CF_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 tcp_agg_vars2; ++#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) ++#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 ++#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) ++#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_CF_EN (0x1<<7) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_CF_EN_SHIFT 7 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX8_CF (0x3<<14) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX8_CF_SHIFT 14 ++ u8 __agg_val8; ++ u8 __agg_val8_th; ++#endif ++ u32 ack_to_far_end; ++ u32 rto_timer; ++ u32 ka_timer; ++ u32 ts_to_echo; ++#if defined(__BIG_ENDIAN) ++ u16 __agg_val7_th; ++ u16 __agg_val7; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __agg_val7; ++ u16 __agg_val7_th; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 __tcp_agg_vars5; ++ u8 __tcp_agg_vars4; ++ u8 __tcp_agg_vars3; ++ u8 __force_pure_ack_cnt; ++#elif defined(__LITTLE_ENDIAN) ++ u8 __force_pure_ack_cnt; ++ u8 __tcp_agg_vars3; ++ u8 __tcp_agg_vars4; ++ u8 __tcp_agg_vars5; ++#endif ++ u32 tcp_agg_vars6; ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX8_CF_EN (0x1<<1) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX8_CF_EN_SHIFT 1 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24 ++#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26) ++#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30 ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31) ++#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31 ++#if defined(__BIG_ENDIAN) ++ u16 __agg_misc6; ++ u16 __tcp_agg_vars7; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __tcp_agg_vars7; ++ u16 __agg_misc6; ++#endif ++ u32 __agg_val10; ++ u32 __agg_val10_th; ++#if defined(__BIG_ENDIAN) ++ u16 __reserved3; ++ u8 __reserved2; ++ u8 __da_only_cnt; ++#elif defined(__LITTLE_ENDIAN) ++ u8 __da_only_cnt; ++ u8 __reserved2; ++ u16 __reserved3; ++#endif ++}; ++ ++/* ++ * The iscsi aggregative context of Xstorm ++ */ ++struct xstorm_iscsi_ag_context { ++#if defined(__BIG_ENDIAN) ++ u16 agg_val1; ++ u8 agg_vars1; ++#define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) ++#define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 ++#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) ++#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 ++#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) ++#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 ++#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) ++#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 ++#define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) ++#define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 ++#define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) ++#define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5 ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 ++#define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) ++#define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 ++ u8 state; ++#elif defined(__LITTLE_ENDIAN) ++ u8 state; ++ u8 agg_vars1; ++#define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) ++#define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 ++#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) ++#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 ++#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) ++#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 ++#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) ++#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 ++#define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) ++#define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 ++#define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) ++#define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5 ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 ++#define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) ++#define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 ++ u16 agg_val1; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 cdu_reserved; ++ u8 agg_vars4; ++#define XSTORM_ISCSI_AG_CONTEXT_R2TQ_PROD_CF (0x3<<0) ++#define XSTORM_ISCSI_AG_CONTEXT_R2TQ_PROD_CF_SHIFT 0 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX21_CF (0x3<<2) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX21_CF_SHIFT 2 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX18_CF_EN (0x1<<4) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX18_CF_EN_SHIFT 4 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX19_CF_EN (0x1<<5) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX19_CF_EN_SHIFT 5 ++#define __XSTORM_ISCSI_AG_CONTEXT_R2TQ_PROD_CF_EN (0x1<<6) ++#define __XSTORM_ISCSI_AG_CONTEXT_R2TQ_PROD_CF_EN_SHIFT 6 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX21_CF_EN (0x1<<7) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX21_CF_EN_SHIFT 7 ++ u8 agg_vars3; ++#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) ++#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX19_CF (0x3<<6) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX19_CF_SHIFT 6 ++ u8 agg_vars2; ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0 ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4 ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5 ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 ++#elif defined(__LITTLE_ENDIAN) ++ u8 agg_vars2; ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0 ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4 ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5 ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) ++#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 ++ u8 agg_vars3; ++#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) ++#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX19_CF (0x3<<6) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX19_CF_SHIFT 6 ++ u8 agg_vars4; ++#define XSTORM_ISCSI_AG_CONTEXT_R2TQ_PROD_CF (0x3<<0) ++#define XSTORM_ISCSI_AG_CONTEXT_R2TQ_PROD_CF_SHIFT 0 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX21_CF (0x3<<2) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX21_CF_SHIFT 2 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX18_CF_EN (0x1<<4) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX18_CF_EN_SHIFT 4 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX19_CF_EN (0x1<<5) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX19_CF_EN_SHIFT 5 ++#define __XSTORM_ISCSI_AG_CONTEXT_R2TQ_PROD_CF_EN (0x1<<6) ++#define __XSTORM_ISCSI_AG_CONTEXT_R2TQ_PROD_CF_EN_SHIFT 6 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX21_CF_EN (0x1<<7) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX21_CF_EN_SHIFT 7 ++ u8 cdu_reserved; ++#endif ++ u32 more_to_send; ++#if defined(__BIG_ENDIAN) ++ u16 agg_vars5; ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0 ++#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) ++#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 ++#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) ++#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14 ++ u16 sq_cons; ++#elif defined(__LITTLE_ENDIAN) ++ u16 sq_cons; ++ u16 agg_vars5; ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0 ++#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) ++#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 ++#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) ++#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14 ++#endif ++ struct xstorm_tcp_tcp_ag_context_section tcp; ++#if defined(__BIG_ENDIAN) ++ u16 agg_vars7; ++#define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) ++#define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3 ++#define XSTORM_ISCSI_AG_CONTEXT_AUX18_CF (0x3<<4) ++#define XSTORM_ISCSI_AG_CONTEXT_AUX18_CF_SHIFT 4 ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6 ++#define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) ++#define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8 ++#define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) ++#define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX2_FLAG (0x1<<15) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX2_FLAG_SHIFT 15 ++ u8 agg_val3_th; ++ u8 agg_vars6; ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0 ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3 ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6 ++#elif defined(__LITTLE_ENDIAN) ++ u8 agg_vars6; ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0 ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3 ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6 ++ u8 agg_val3_th; ++ u16 agg_vars7; ++#define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) ++#define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3 ++#define XSTORM_ISCSI_AG_CONTEXT_AUX18_CF (0x3<<4) ++#define XSTORM_ISCSI_AG_CONTEXT_AUX18_CF_SHIFT 4 ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6) ++#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6 ++#define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) ++#define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8 ++#define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) ++#define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14 ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX2_FLAG (0x1<<15) ++#define __XSTORM_ISCSI_AG_CONTEXT_AUX2_FLAG_SHIFT 15 ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 __agg_val11_th; ++ u16 __agg_val11; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __agg_val11; ++ u16 __agg_val11_th; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 __reserved1; ++ u8 __agg_val6_th; ++ u16 __agg_val9; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __agg_val9; ++ u8 __agg_val6_th; ++ u8 __reserved1; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 hq_prod; ++ u16 hq_cons; ++#elif defined(__LITTLE_ENDIAN) ++ u16 hq_cons; ++ u16 hq_prod; ++#endif ++ u32 agg_vars8; ++#define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) ++#define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2_SHIFT 0 ++#define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3 (0xFF<<24) ++#define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3_SHIFT 24 ++#if defined(__BIG_ENDIAN) ++ u16 r2tq_prod; ++ u16 sq_prod; ++#elif defined(__LITTLE_ENDIAN) ++ u16 sq_prod; ++ u16 r2tq_prod; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 agg_val3; ++ u8 agg_val6; ++ u8 agg_val5_th; ++ u8 agg_val5; ++#elif defined(__LITTLE_ENDIAN) ++ u8 agg_val5; ++ u8 agg_val5_th; ++ u8 agg_val6; ++ u8 agg_val3; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 __agg_misc1; ++ u16 agg_limit1; ++#elif defined(__LITTLE_ENDIAN) ++ u16 agg_limit1; ++ u16 __agg_misc1; ++#endif ++ u32 hq_cons_tcp_seq; ++ u32 exp_stat_sn; ++ u32 agg_misc5; ++}; ++ ++/* ++ * The tcp aggregative context section of Tstorm ++ */ ++struct tstorm_tcp_tcp_ag_context_section { ++ u32 __agg_val1; ++#if defined(__BIG_ENDIAN) ++ u8 __tcp_agg_vars2; ++ u8 __agg_val3; ++ u16 __agg_val2; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __agg_val2; ++ u8 __agg_val3; ++ u8 __tcp_agg_vars2; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 __agg_val5; ++ u8 __agg_val6; ++ u8 __tcp_agg_vars3; ++#elif defined(__LITTLE_ENDIAN) ++ u8 __tcp_agg_vars3; ++ u8 __agg_val6; ++ u16 __agg_val5; ++#endif ++ u32 snd_nxt; ++ u32 rtt_seq; ++ u32 rtt_time; ++ u32 __reserved66; ++ u32 wnd_right_edge; ++ u32 tcp_agg_vars1; ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 ++#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) ++#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 ++#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) ++#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 ++#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) ++#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 ++#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) ++#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) ++#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 ++ u32 snd_max; ++ u32 snd_una; ++ u32 __reserved2; ++}; ++ ++/* ++ * The iscsi aggregative context of Tstorm ++ */ ++struct tstorm_iscsi_ag_context { ++#if defined(__BIG_ENDIAN) ++ u16 ulp_credit; ++ u8 agg_vars1; ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_CF (0x3<<4) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_CF_SHIFT 4 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX4_FLAG (0x1<<7) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX4_FLAG_SHIFT 7 ++ u8 state; ++#elif defined(__LITTLE_ENDIAN) ++ u8 state; ++ u8 agg_vars1; ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) ++#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_CF (0x3<<4) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_CF_SHIFT 4 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX4_FLAG (0x1<<7) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX4_FLAG_SHIFT 7 ++ u16 ulp_credit; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 __agg_val4; ++ u16 agg_vars2; ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX5_FLAG (0x1<<0) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX5_FLAG_SHIFT 0 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_FLAG (0x1<<1) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_FLAG_SHIFT 1 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<2) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX4_CF_SHIFT 2 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX5_CF (0x3<<4) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX5_CF_SHIFT 4 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10 ++#define TSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<11) ++#define TSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 11 ++#define TSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN (0x1<<12) ++#define TSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN_SHIFT 12 ++#define TSTORM_ISCSI_AG_CONTEXT_AUX5_CF_EN (0x1<<13) ++#define TSTORM_ISCSI_AG_CONTEXT_AUX5_CF_EN_SHIFT 13 ++#define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) ++#define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 ++#define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) ++#define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 ++#elif defined(__LITTLE_ENDIAN) ++ u16 agg_vars2; ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX5_FLAG (0x1<<0) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX5_FLAG_SHIFT 0 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_FLAG (0x1<<1) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_FLAG_SHIFT 1 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<2) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX4_CF_SHIFT 2 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX5_CF (0x3<<4) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX5_CF_SHIFT 4 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8 ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) ++#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10 ++#define TSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<11) ++#define TSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 11 ++#define TSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN (0x1<<12) ++#define TSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN_SHIFT 12 ++#define TSTORM_ISCSI_AG_CONTEXT_AUX5_CF_EN (0x1<<13) ++#define TSTORM_ISCSI_AG_CONTEXT_AUX5_CF_EN_SHIFT 13 ++#define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) ++#define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 ++#define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) ++#define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 ++ u16 __agg_val4; ++#endif ++ struct tstorm_tcp_tcp_ag_context_section tcp; ++}; ++ ++/* ++ * The iscsi aggregative context of Cstorm ++ */ ++struct cstorm_iscsi_ag_context { ++ u32 agg_vars1; ++#define CSTORM_ISCSI_AG_CONTEXT_STATE (0xFF<<0) ++#define CSTORM_ISCSI_AG_CONTEXT_STATE_SHIFT 0 ++#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<8) ++#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 8 ++#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9) ++#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 9 ++#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10) ++#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 10 ++#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11) ++#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 11 ++#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12) ++#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN_SHIFT 12 ++#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13) ++#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN_SHIFT 13 ++#define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION3_CF (0x3<<14) ++#define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION3_CF_SHIFT 14 ++#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16) ++#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66_SHIFT 16 ++#define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18) ++#define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN_SHIFT 18 ++#define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION0_CF_EN (0x1<<19) ++#define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION0_CF_EN_SHIFT 19 ++#define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION1_CF_EN (0x1<<20) ++#define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION1_CF_EN_SHIFT 20 ++#define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION2_CF_EN (0x1<<21) ++#define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION2_CF_EN_SHIFT 21 ++#define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION3_CF_EN (0x1<<22) ++#define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION3_CF_EN_SHIFT 22 ++#define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE (0x7<<23) ++#define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE_SHIFT 23 ++#define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26) ++#define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE_SHIFT 26 ++#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28) ++#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52_SHIFT 28 ++#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30) ++#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53_SHIFT 30 ++#if defined(__BIG_ENDIAN) ++ u8 __aux1_th; ++ u8 __aux1_val; ++ u16 __agg_vars2; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __agg_vars2; ++ u8 __aux1_val; ++ u8 __aux1_th; ++#endif ++ u32 rel_seq; ++ u32 rel_seq_th; ++#if defined(__BIG_ENDIAN) ++ u16 hq_cons; ++ u16 hq_prod; ++#elif defined(__LITTLE_ENDIAN) ++ u16 hq_prod; ++ u16 hq_cons; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 __reserved62; ++ u8 __reserved61; ++ u8 __reserved60; ++ u8 __reserved59; ++#elif defined(__LITTLE_ENDIAN) ++ u8 __reserved59; ++ u8 __reserved60; ++ u8 __reserved61; ++ u8 __reserved62; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 __reserved64; ++ u16 __cq_u_prod0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __cq_u_prod0; ++ u16 __reserved64; ++#endif ++ u32 __cq_u_prod1; ++#if defined(__BIG_ENDIAN) ++ u16 __agg_vars3; ++ u16 __cq_u_prod2; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __cq_u_prod2; ++ u16 __agg_vars3; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 __aux2_th; ++ u16 __cq_u_prod3; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __cq_u_prod3; ++ u16 __aux2_th; ++#endif ++}; ++ ++/* ++ * The iscsi aggregative context of Ustorm ++ */ ++struct ustorm_iscsi_ag_context { ++#if defined(__BIG_ENDIAN) ++ u8 __aux_counter_flags; ++ u8 agg_vars2; ++#define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) ++#define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0 ++#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) ++#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2 ++#define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) ++#define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 ++#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) ++#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 ++ u8 agg_vars1; ++#define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) ++#define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 ++#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) ++#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 ++#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) ++#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 ++#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) ++#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 ++#define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) ++#define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4 ++#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) ++#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6 ++ u8 state; ++#elif defined(__LITTLE_ENDIAN) ++ u8 state; ++ u8 agg_vars1; ++#define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) ++#define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 ++#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) ++#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 ++#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) ++#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 ++#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) ++#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 ++#define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) ++#define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4 ++#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) ++#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6 ++ u8 agg_vars2; ++#define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) ++#define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0 ++#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) ++#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2 ++#define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) ++#define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 ++#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) ++#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 ++ u8 __aux_counter_flags; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 cdu_usage; ++ u8 agg_misc2; ++ u16 __cq_local_comp_itt_val; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __cq_local_comp_itt_val; ++ u8 agg_misc2; ++ u8 cdu_usage; ++#endif ++ u32 agg_misc4; ++#if defined(__BIG_ENDIAN) ++ u8 agg_val3_th; ++ u8 agg_val3; ++ u16 agg_misc3; ++#elif defined(__LITTLE_ENDIAN) ++ u16 agg_misc3; ++ u8 agg_val3; ++ u8 agg_val3_th; ++#endif ++ u32 agg_val1; ++ u32 agg_misc4_th; ++#if defined(__BIG_ENDIAN) ++ u16 agg_val2_th; ++ u16 agg_val2; ++#elif defined(__LITTLE_ENDIAN) ++ u16 agg_val2; ++ u16 agg_val2_th; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 __reserved2; ++ u8 decision_rules; ++#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) ++#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0 ++#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) ++#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 ++#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) ++#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6 ++#define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) ++#define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7 ++ u8 decision_rule_enable_bits; ++#define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) ++#define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0 ++#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) ++#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 ++#define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) ++#define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2 ++#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) ++#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 ++#define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) ++#define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4 ++#define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) ++#define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5 ++#define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) ++#define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 ++#define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) ++#define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 ++#elif defined(__LITTLE_ENDIAN) ++ u8 decision_rule_enable_bits; ++#define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) ++#define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0 ++#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) ++#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 ++#define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) ++#define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2 ++#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) ++#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 ++#define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) ++#define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4 ++#define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) ++#define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5 ++#define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) ++#define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 ++#define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) ++#define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 ++ u8 decision_rules; ++#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) ++#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0 ++#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) ++#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 ++#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) ++#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6 ++#define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) ++#define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7 ++ u16 __reserved2; ++#endif ++}; ++ ++/* ++ * Timers connection context ++ */ ++struct iscsi_timers_block_context { ++ u32 __reserved_0; ++ u32 __reserved_1; ++ u32 __reserved_2; ++ u32 flags; ++#define __ISCSI_TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) ++#define __ISCSI_TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 ++#define ISCSI_TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) ++#define ISCSI_TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 ++#define __ISCSI_TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) ++#define __ISCSI_TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 ++}; ++ ++/* ++ * Ethernet context section, shared in TOE, RDMA and ISCSI ++ */ ++struct xstorm_eth_context_section { ++#if defined(__BIG_ENDIAN) ++ u8 remote_addr_4; ++ u8 remote_addr_5; ++ u8 local_addr_0; ++ u8 local_addr_1; ++#elif defined(__LITTLE_ENDIAN) ++ u8 local_addr_1; ++ u8 local_addr_0; ++ u8 remote_addr_5; ++ u8 remote_addr_4; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 remote_addr_0; ++ u8 remote_addr_1; ++ u8 remote_addr_2; ++ u8 remote_addr_3; ++#elif defined(__LITTLE_ENDIAN) ++ u8 remote_addr_3; ++ u8 remote_addr_2; ++ u8 remote_addr_1; ++ u8 remote_addr_0; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 reserved_vlan_type; ++ u16 params; ++#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) ++#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 ++#define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) ++#define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12 ++#define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) ++#define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 ++#elif defined(__LITTLE_ENDIAN) ++ u16 params; ++#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) ++#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 ++#define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) ++#define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12 ++#define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) ++#define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 ++ u16 reserved_vlan_type; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 local_addr_2; ++ u8 local_addr_3; ++ u8 local_addr_4; ++ u8 local_addr_5; ++#elif defined(__LITTLE_ENDIAN) ++ u8 local_addr_5; ++ u8 local_addr_4; ++ u8 local_addr_3; ++ u8 local_addr_2; ++#endif ++}; ++ ++/* ++ * IpV4 context section, shared in TOE, RDMA and ISCSI ++ */ ++struct xstorm_ip_v4_context_section { ++#if defined(__BIG_ENDIAN) ++ u16 __pbf_hdr_cmd_rsvd_id; ++ u16 __pbf_hdr_cmd_rsvd_flags_offset; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __pbf_hdr_cmd_rsvd_flags_offset; ++ u16 __pbf_hdr_cmd_rsvd_id; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 __pbf_hdr_cmd_rsvd_ver_ihl; ++ u8 tos; ++ u16 __pbf_hdr_cmd_rsvd_length; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __pbf_hdr_cmd_rsvd_length; ++ u8 tos; ++ u8 __pbf_hdr_cmd_rsvd_ver_ihl; ++#endif ++ u32 ip_local_addr; ++#if defined(__BIG_ENDIAN) ++ u8 ttl; ++ u8 __pbf_hdr_cmd_rsvd_protocol; ++ u16 __pbf_hdr_cmd_rsvd_csum; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __pbf_hdr_cmd_rsvd_csum; ++ u8 __pbf_hdr_cmd_rsvd_protocol; ++ u8 ttl; ++#endif ++ u32 __pbf_hdr_cmd_rsvd_1; ++ u32 ip_remote_addr; ++}; ++ ++/* ++ * context section, shared in TOE, RDMA and ISCSI ++ */ ++struct xstorm_padded_ip_v4_context_section { ++ struct xstorm_ip_v4_context_section ip_v4; ++ u32 reserved1[4]; ++}; ++ ++/* ++ * IpV6 context section, shared in TOE, RDMA and ISCSI ++ */ ++struct xstorm_ip_v6_context_section { ++#if defined(__BIG_ENDIAN) ++ u16 pbf_hdr_cmd_rsvd_payload_len; ++ u8 pbf_hdr_cmd_rsvd_nxt_hdr; ++ u8 hop_limit; ++#elif defined(__LITTLE_ENDIAN) ++ u8 hop_limit; ++ u8 pbf_hdr_cmd_rsvd_nxt_hdr; ++ u16 pbf_hdr_cmd_rsvd_payload_len; ++#endif ++ u32 priority_flow_label; ++#define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL (0xFFFFF<<0) ++#define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL_SHIFT 0 ++#define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS (0xFF<<20) ++#define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS_SHIFT 20 ++#define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER (0xF<<28) ++#define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER_SHIFT 28 ++ u32 ip_local_addr_lo_hi; ++ u32 ip_local_addr_lo_lo; ++ u32 ip_local_addr_hi_hi; ++ u32 ip_local_addr_hi_lo; ++ u32 ip_remote_addr_lo_hi; ++ u32 ip_remote_addr_lo_lo; ++ u32 ip_remote_addr_hi_hi; ++ u32 ip_remote_addr_hi_lo; ++}; ++ ++union xstorm_ip_context_section_types { ++ struct xstorm_padded_ip_v4_context_section padded_ip_v4; ++ struct xstorm_ip_v6_context_section ip_v6; ++}; ++ ++/* ++ * TCP context section, shared in TOE, RDMA and ISCSI ++ */ ++struct xstorm_tcp_context_section { ++ u32 snd_max; ++#if defined(__BIG_ENDIAN) ++ u16 remote_port; ++ u16 local_port; ++#elif defined(__LITTLE_ENDIAN) ++ u16 local_port; ++ u16 remote_port; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 original_nagle_1b; ++ u8 ts_enabled_1b; ++ u16 tcp_params; ++#define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) ++#define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0 ++#define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) ++#define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8 ++#define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) ++#define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9 ++#define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) ++#define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10 ++#define XSTORM_TCP_CONTEXT_SECTION_KA_STATE (0x1<<11) ++#define XSTORM_TCP_CONTEXT_SECTION_KA_STATE_SHIFT 11 ++#define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) ++#define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12 ++#define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) ++#define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13 ++#define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) ++#define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 tcp_params; ++#define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) ++#define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0 ++#define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) ++#define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8 ++#define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) ++#define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9 ++#define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) ++#define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10 ++#define XSTORM_TCP_CONTEXT_SECTION_KA_STATE (0x1<<11) ++#define XSTORM_TCP_CONTEXT_SECTION_KA_STATE_SHIFT 11 ++#define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) ++#define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12 ++#define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) ++#define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13 ++#define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) ++#define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14 ++ u8 ts_enabled_1b; ++ u8 original_nagle_1b; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 pseudo_csum; ++ u16 window_scaling_factor; ++#elif defined(__LITTLE_ENDIAN) ++ u16 window_scaling_factor; ++ u16 pseudo_csum; ++#endif ++ u32 reserved2; ++ u32 ts_time_diff; ++ u32 __next_timer_expir; ++}; ++ ++/* ++ * Common context section, shared in TOE, RDMA and ISCSI ++ */ ++struct xstorm_common_context_section { ++ struct xstorm_eth_context_section ethernet; ++ union xstorm_ip_context_section_types ip_union; ++ struct xstorm_tcp_context_section tcp; ++#if defined(__BIG_ENDIAN) ++ u16 reserved; ++ u8 statistics_params; ++#define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) ++#define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0 ++#define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) ++#define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1 ++#define XSTORM_COMMON_CONTEXT_SECTION_STATISTICS_COUNTER_ID (0x1F<<2) ++#define XSTORM_COMMON_CONTEXT_SECTION_STATISTICS_COUNTER_ID_SHIFT 2 ++#define XSTORM_COMMON_CONTEXT_SECTION_RESERVED0 (0x1<<7) ++#define XSTORM_COMMON_CONTEXT_SECTION_RESERVED0_SHIFT 7 ++ u8 ip_version_1b; ++#elif defined(__LITTLE_ENDIAN) ++ u8 ip_version_1b; ++ u8 statistics_params; ++#define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) ++#define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0 ++#define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) ++#define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1 ++#define XSTORM_COMMON_CONTEXT_SECTION_STATISTICS_COUNTER_ID (0x1F<<2) ++#define XSTORM_COMMON_CONTEXT_SECTION_STATISTICS_COUNTER_ID_SHIFT 2 ++#define XSTORM_COMMON_CONTEXT_SECTION_RESERVED0 (0x1<<7) ++#define XSTORM_COMMON_CONTEXT_SECTION_RESERVED0_SHIFT 7 ++ u16 reserved; ++#endif ++}; ++ ++/* ++ * Flags used in ISCSI context section ++ */ ++struct xstorm_iscsi_context_flags { ++ u8 flags; ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA (0x1<<0) ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA_SHIFT 0 ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T (0x1<<1) ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T_SHIFT 1 ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST (0x1<<2) ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST_SHIFT 2 ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST (0x1<<3) ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST_SHIFT 3 ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN (0x1<<4) ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN_SHIFT 4 ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ (0x1<<5) ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ_SHIFT 5 ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT (0x1<<6) ++#define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT_SHIFT 6 ++#define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4 (0x1<<7) ++#define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4_SHIFT 7 ++}; ++ ++struct iscsi_task_context_entry_x { ++ u32 data_out_buffer_offset; ++ u32 itt; ++ u32 data_sn; ++}; ++ ++struct iscsi_task_context_entry_xuc_x_write_only { ++ u32 tx_r2t_sn; ++}; ++ ++struct iscsi_task_context_entry_xuc_xu_write_both { ++ u32 sgl_base_lo; ++ u32 sgl_base_hi; ++#if defined(__BIG_ENDIAN) ++ u8 sgl_size; ++ u8 sge_index; ++ u16 sge_offset; ++#elif defined(__LITTLE_ENDIAN) ++ u16 sge_offset; ++ u8 sge_index; ++ u8 sgl_size; ++#endif ++}; ++ ++/* ++ * iSCSI context section ++ */ ++struct xstorm_iscsi_context_section { ++ u32 first_burst_length; ++ u32 max_send_pdu_length; ++ struct regpair sq_pbl_base; ++ struct regpair sq_curr_pbe; ++ struct regpair hq_pbl_base; ++ struct regpair hq_curr_pbe_base; ++ struct regpair r2tq_pbl_base; ++ struct regpair r2tq_curr_pbe_base; ++ struct regpair task_pbl_base; ++#if defined(__BIG_ENDIAN) ++ u16 data_out_count; ++ struct xstorm_iscsi_context_flags flags; ++ u8 task_pbl_cache_idx; ++#elif defined(__LITTLE_ENDIAN) ++ u8 task_pbl_cache_idx; ++ struct xstorm_iscsi_context_flags flags; ++ u16 data_out_count; ++#endif ++ u32 seq_more_2_send; ++ u32 pdu_more_2_send; ++ struct iscsi_task_context_entry_x temp_tce_x; ++ struct iscsi_task_context_entry_xuc_x_write_only temp_tce_x_wr; ++ struct iscsi_task_context_entry_xuc_xu_write_both temp_tce_xu_wr; ++ struct regpair lun; ++ u32 exp_data_transfer_len_ttt; ++ u32 pdu_data_2_rxmit; ++ u32 rxmit_bytes_2_dr; ++#if defined(__BIG_ENDIAN) ++ u16 rxmit_sge_offset; ++ u16 hq_rxmit_cons; ++#elif defined(__LITTLE_ENDIAN) ++ u16 hq_rxmit_cons; ++ u16 rxmit_sge_offset; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 r2tq_cons; ++ u8 rxmit_flags; ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0 ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1 ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2 ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3 ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4 ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5 ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7 ++ u8 rxmit_sge_idx; ++#elif defined(__LITTLE_ENDIAN) ++ u8 rxmit_sge_idx; ++ u8 rxmit_flags; ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0 ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1 ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2 ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3 ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4 ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5 ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) ++#define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7 ++ u16 r2tq_cons; ++#endif ++ u32 hq_rxmit_tcp_seq; ++}; ++ ++/* ++ * Xstorm iSCSI Storm Context ++ */ ++struct xstorm_iscsi_st_context { ++ struct xstorm_common_context_section common; ++ struct xstorm_iscsi_context_section iscsi; ++}; ++ ++/* ++ * CQ DB CQ producer and pending completion counter ++ */ ++struct iscsi_cq_db_prod_pnd_cmpltn_cnt { ++#if defined(__BIG_ENDIAN) ++ u16 cntr; ++ u16 prod; ++#elif defined(__LITTLE_ENDIAN) ++ u16 prod; ++ u16 cntr; ++#endif ++}; ++ ++/* ++ * CQ DB pending completion ITT array ++ */ ++struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr { ++ struct iscsi_cq_db_prod_pnd_cmpltn_cnt prod_pend_comp[8]; ++}; ++ ++/* ++ * Cstorm CQ sequence to notify array, updated by driver ++ */ ++struct iscsi_cq_db_sqn_2_notify_arr { ++ u16 sqn[8]; ++}; ++ ++/* ++ * Cstorm iSCSI Storm Context ++ */ ++struct cstorm_iscsi_st_context { ++ struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_c_prod_pend_comp_ctr_arr; ++ struct iscsi_cq_db_sqn_2_notify_arr cq_c_prod_sqn_arr; ++ struct iscsi_cq_db_sqn_2_notify_arr cq_c_sqn_2_notify_arr; ++ struct regpair hq_pbl_base; ++ struct regpair hq_curr_pbe; ++ struct regpair task_pbl_base; ++ struct regpair cq_db_base; ++#if defined(__BIG_ENDIAN) ++ u16 hq_bd_itt; ++ u16 iscsi_conn_id; ++#elif defined(__LITTLE_ENDIAN) ++ u16 iscsi_conn_id; ++ u16 hq_bd_itt; ++#endif ++ u32 hq_bd_data_segment_len; ++ u32 hq_bd_buffer_offset; ++#if defined(__BIG_ENDIAN) ++ u8 timer_entry_idx; ++ u8 cq_proc_en_bit_map; ++ u8 cq_pend_comp_itt_valid_bit_map; ++ u8 hq_bd_opcode; ++#elif defined(__LITTLE_ENDIAN) ++ u8 hq_bd_opcode; ++ u8 cq_pend_comp_itt_valid_bit_map; ++ u8 cq_proc_en_bit_map; ++ u8 timer_entry_idx; ++#endif ++ u32 hq_tcp_seq; ++#if defined(__BIG_ENDIAN) ++ u16 flags; ++#define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) ++#define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0 ++#define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) ++#define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1 ++#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) ++#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2 ++#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) ++#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3 ++#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) ++#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4 ++#define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) ++#define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5 ++ u16 hq_cons; ++#elif defined(__LITTLE_ENDIAN) ++ u16 hq_cons; ++ u16 flags; ++#define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) ++#define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0 ++#define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) ++#define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1 ++#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) ++#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2 ++#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) ++#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3 ++#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) ++#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4 ++#define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) ++#define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5 ++#endif ++ struct regpair rsrv1; ++}; ++ ++/* ++ * Iscsi connection context ++ */ ++struct iscsi_context { ++ struct ustorm_iscsi_st_context ustorm_st_context; ++ struct tstorm_iscsi_st_context tstorm_st_context; ++ struct xstorm_iscsi_ag_context xstorm_ag_context; ++ struct tstorm_iscsi_ag_context tstorm_ag_context; ++ struct cstorm_iscsi_ag_context cstorm_ag_context; ++ struct ustorm_iscsi_ag_context ustorm_ag_context; ++ struct iscsi_timers_block_context timers_context; ++ struct regpair upb_context; ++ struct xstorm_iscsi_st_context xstorm_st_context; ++ struct regpair xpb_context; ++ struct cstorm_iscsi_st_context cstorm_st_context; ++}; ++ ++ ++ ++/* ++ * CQ DB pending completion ITT array ++ */ ++struct iscsi_cq_db_pnd_comp_itt_arr { ++ u16 itt[8]; ++}; ++ ++/* ++ * CQ DB ++ */ ++struct iscsi_cq_db { ++ struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_u_prod_pend_comp_ctr_arr; ++ struct iscsi_cq_db_pnd_comp_itt_arr cq_c_pend_comp_itt_arr; ++ struct iscsi_cq_db_sqn_2_notify_arr cq_drv_sqn_2_notify_arr; ++ u32 reserved[4]; ++}; ++ ++ ++ ++ ++ ++ ++/* ++ * iSCSI KCQ CQE parameters ++ */ ++union iscsi_kcqe_params { ++ u32 reserved0[4]; ++}; ++ ++/* ++ * iSCSI KCQ CQE ++ */ ++struct iscsi_kcqe { ++ u32 iscsi_conn_id; ++ u32 completion_status; ++ u32 iscsi_conn_context_id; ++ union iscsi_kcqe_params params; ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define ISCSI_KCQE_RESERVED0 (0x7<<0) ++#define ISCSI_KCQE_RESERVED0_SHIFT 0 ++#define ISCSI_KCQE_RAMROD_COMPLETION (0x1<<3) ++#define ISCSI_KCQE_RAMROD_COMPLETION_SHIFT 3 ++#define ISCSI_KCQE_LAYER_CODE (0x7<<4) ++#define ISCSI_KCQE_LAYER_CODE_SHIFT 4 ++#define ISCSI_KCQE_LINKED_WITH_NEXT (0x1<<7) ++#define ISCSI_KCQE_LINKED_WITH_NEXT_SHIFT 7 ++ u8 op_code; ++ u16 qe_self_seq; ++#elif defined(__LITTLE_ENDIAN) ++ u16 qe_self_seq; ++ u8 op_code; ++ u8 flags; ++#define ISCSI_KCQE_RESERVED0 (0x7<<0) ++#define ISCSI_KCQE_RESERVED0_SHIFT 0 ++#define ISCSI_KCQE_RAMROD_COMPLETION (0x1<<3) ++#define ISCSI_KCQE_RAMROD_COMPLETION_SHIFT 3 ++#define ISCSI_KCQE_LAYER_CODE (0x7<<4) ++#define ISCSI_KCQE_LAYER_CODE_SHIFT 4 ++#define ISCSI_KCQE_LINKED_WITH_NEXT (0x1<<7) ++#define ISCSI_KCQE_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++}; ++ ++ ++ ++/* ++ * iSCSI KWQE header ++ */ ++struct iscsi_kwqe_header { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0) ++#define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0 ++#define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4) ++#define ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT 4 ++#define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7) ++#define ISCSI_KWQE_HEADER_RESERVED1_SHIFT 7 ++ u8 op_code; ++#elif defined(__LITTLE_ENDIAN) ++ u8 op_code; ++ u8 flags; ++#define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0) ++#define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0 ++#define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4) ++#define ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT 4 ++#define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7) ++#define ISCSI_KWQE_HEADER_RESERVED1_SHIFT 7 ++#endif ++}; ++ ++/* ++ * iSCSI firmware init request 1 ++ */ ++struct iscsi_kwqe_init1 { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u8 reserved0; ++ u8 num_cqs; ++#elif defined(__LITTLE_ENDIAN) ++ u8 num_cqs; ++ u8 reserved0; ++ struct iscsi_kwqe_header hdr; ++#endif ++ u32 dummy_buffer_addr_lo; ++ u32 dummy_buffer_addr_hi; ++#if defined(__BIG_ENDIAN) ++ u16 num_ccells_per_conn; ++ u16 num_tasks_per_conn; ++#elif defined(__LITTLE_ENDIAN) ++ u16 num_tasks_per_conn; ++ u16 num_ccells_per_conn; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 sq_wqes_per_page; ++ u16 sq_num_wqes; ++#elif defined(__LITTLE_ENDIAN) ++ u16 sq_num_wqes; ++ u16 sq_wqes_per_page; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 cq_log_wqes_per_page; ++ u8 flags; ++#define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0) ++#define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0 ++#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4) ++#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE_SHIFT 4 ++#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5) ++#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE_SHIFT 5 ++#define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6) ++#define ISCSI_KWQE_INIT1_RESERVED1_SHIFT 6 ++ u16 cq_num_wqes; ++#elif defined(__LITTLE_ENDIAN) ++ u16 cq_num_wqes; ++ u8 flags; ++#define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0) ++#define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0 ++#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4) ++#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE_SHIFT 4 ++#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5) ++#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE_SHIFT 5 ++#define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6) ++#define ISCSI_KWQE_INIT1_RESERVED1_SHIFT 6 ++ u8 cq_log_wqes_per_page; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 cq_num_pages; ++ u16 sq_num_pages; ++#elif defined(__LITTLE_ENDIAN) ++ u16 sq_num_pages; ++ u16 cq_num_pages; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 rq_buffer_size; ++ u16 rq_num_wqes; ++#elif defined(__LITTLE_ENDIAN) ++ u16 rq_num_wqes; ++ u16 rq_buffer_size; ++#endif ++}; ++ ++/* ++ * iSCSI firmware init request 2 ++ */ ++struct iscsi_kwqe_init2 { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u16 max_cq_sqn; ++#elif defined(__LITTLE_ENDIAN) ++ u16 max_cq_sqn; ++ struct iscsi_kwqe_header hdr; ++#endif ++ u32 error_bit_map[2]; ++ u32 tcp_keepalive; ++ u32 reserved1[4]; ++}; ++ ++/* ++ * Initial iSCSI connection offload request 1 ++ */ ++struct iscsi_kwqe_conn_offload1 { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u16 iscsi_conn_id; ++#elif defined(__LITTLE_ENDIAN) ++ u16 iscsi_conn_id; ++ struct iscsi_kwqe_header hdr; ++#endif ++ u32 sq_page_table_addr_lo; ++ u32 sq_page_table_addr_hi; ++ u32 cq_page_table_addr_lo; ++ u32 cq_page_table_addr_hi; ++ u32 reserved0[3]; ++}; ++ ++/* ++ * iSCSI Page Table Entry (PTE) ++ */ ++struct iscsi_pte { ++ u32 hi; ++ u32 lo; ++}; ++ ++/* ++ * Initial iSCSI connection offload request 2 ++ */ ++struct iscsi_kwqe_conn_offload2 { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ struct iscsi_kwqe_header hdr; ++#endif ++ u32 rq_page_table_addr_lo; ++ u32 rq_page_table_addr_hi; ++ struct iscsi_pte sq_first_pte; ++ struct iscsi_pte cq_first_pte; ++ u32 num_additional_wqes; ++}; ++ ++/* ++ * Everest specific - Initial iSCSI connection offload request 3 ++ */ ++struct iscsi_kwqe_conn_offload3 { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ struct iscsi_kwqe_header hdr; ++#endif ++ u32 reserved1; ++ struct iscsi_pte qp_first_pte[3]; ++}; ++ ++/* ++ * iSCSI connection update request ++ */ ++struct iscsi_kwqe_conn_update { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ struct iscsi_kwqe_header hdr; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 session_error_recovery_level; ++ u8 max_outstanding_r2ts; ++ u8 reserved2; ++ u8 conn_flags; ++#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0) ++#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0 ++#define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST (0x1<<1) ++#define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST_SHIFT 1 ++#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T (0x1<<2) ++#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2 ++#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3) ++#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3 ++#define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0xF<<4) ++#define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 4 ++#elif defined(__LITTLE_ENDIAN) ++ u8 conn_flags; ++#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0) ++#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0 ++#define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST (0x1<<1) ++#define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST_SHIFT 1 ++#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T (0x1<<2) ++#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2 ++#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3) ++#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3 ++#define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0xF<<4) ++#define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 4 ++ u8 reserved2; ++ u8 max_outstanding_r2ts; ++ u8 session_error_recovery_level; ++#endif ++ u32 context_id; ++ u32 max_send_pdu_length; ++ u32 max_recv_pdu_length; ++ u32 first_burst_length; ++ u32 max_burst_length; ++ u32 exp_stat_sn; ++}; ++ ++/* ++ * iSCSI destroy connection request ++ */ ++struct iscsi_kwqe_conn_destroy { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u16 iscsi_conn_id; ++#elif defined(__LITTLE_ENDIAN) ++ u16 iscsi_conn_id; ++ struct iscsi_kwqe_header hdr; ++#endif ++ u32 context_id; ++ u32 reserved1[6]; ++}; ++ ++/* ++ * iSCSI KWQ WQE ++ */ ++union iscsi_kwqe { ++ struct iscsi_kwqe_init1 init1; ++ struct iscsi_kwqe_init2 init2; ++ struct iscsi_kwqe_conn_offload1 conn_offload1; ++ struct iscsi_kwqe_conn_offload2 conn_offload2; ++ struct iscsi_kwqe_conn_offload3 conn_offload3; ++ struct iscsi_kwqe_conn_update conn_update; ++ struct iscsi_kwqe_conn_destroy conn_destroy; ++}; ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++struct iscsi_rq_db { ++#if defined(__BIG_ENDIAN) ++ u16 reserved0; ++ u16 rq_prod; ++#elif defined(__LITTLE_ENDIAN) ++ u16 rq_prod; ++ u16 reserved0; ++#endif ++ u32 reserved1[3]; ++}; ++ ++ ++struct iscsi_sq_db { ++#if defined(__BIG_ENDIAN) ++ u16 reserved0; ++ u16 sq_prod; ++#elif defined(__LITTLE_ENDIAN) ++ u16 sq_prod; ++ u16 reserved0; ++#endif ++ u32 reserved1[3]; ++}; ++ ++ ++ ++/* ++ * SCSI read/write SQ WQE ++ */ ++struct iscsi_cmd_pdu_hdr_little_endian { ++#if defined(__BIG_ENDIAN) ++ u8 opcode; ++ u8 op_attr; ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0) ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0 ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3) ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3 ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5) ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5 ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6) ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6 ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 ++ u16 rsrv0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 rsrv0; ++ u8 op_attr; ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0) ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0 ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3) ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3 ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5) ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5 ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6) ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6 ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 ++ u8 opcode; ++#endif ++ u32 data_fields; ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) ++#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 ++ struct regpair lun; ++ u32 itt; ++ u32 expected_data_transfer_length; ++ u32 cmd_sn; ++ u32 exp_stat_sn; ++ u32 scsi_command_block[4]; ++}; ++ ++ ++/* ++ * Buffer per connection, used in Tstorm ++ */ ++struct iscsi_conn_buf { ++ struct regpair reserved[8]; ++}; ++ ++ ++/* ++ * PDU header of an iSCSI DATA-OUT ++ */ ++struct iscsi_data_pdu_hdr_little_endian { ++#if defined(__BIG_ENDIAN) ++ u8 opcode; ++ u8 op_attr; ++#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) ++#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 ++#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) ++#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 ++ u16 rsrv0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 rsrv0; ++ u8 op_attr; ++#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) ++#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 ++#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) ++#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 ++ u8 opcode; ++#endif ++ u32 data_fields; ++#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) ++#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 ++#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) ++#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 ++ struct regpair lun; ++ u32 itt; ++ u32 ttt; ++ u32 rsrv2; ++ u32 exp_stat_sn; ++ u32 rsrv3; ++ u32 data_sn; ++ u32 buffer_offset; ++ u32 rsrv4; ++}; ++ ++ ++/* ++ * PDU header of an iSCSI login request ++ */ ++struct iscsi_login_req_hdr_little_endian { ++#if defined(__BIG_ENDIAN) ++ u8 opcode; ++ u8 op_attr; ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0) ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0 ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2) ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2 ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4) ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4 ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7) ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7 ++ u8 version_max; ++ u8 version_min; ++#elif defined(__LITTLE_ENDIAN) ++ u8 version_min; ++ u8 version_max; ++ u8 op_attr; ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0) ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0 ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2) ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2 ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4) ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4 ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7) ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7 ++ u8 opcode; ++#endif ++ u32 data_fields; ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) ++#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 ++ u32 isid_lo; ++#if defined(__BIG_ENDIAN) ++ u16 isid_hi; ++ u16 tsih; ++#elif defined(__LITTLE_ENDIAN) ++ u16 tsih; ++ u16 isid_hi; ++#endif ++ u32 itt; ++#if defined(__BIG_ENDIAN) ++ u16 cid; ++ u16 rsrv1; ++#elif defined(__LITTLE_ENDIAN) ++ u16 rsrv1; ++ u16 cid; ++#endif ++ u32 cmd_sn; ++ u32 exp_stat_sn; ++ u32 rsrv2[4]; ++}; ++ ++/* ++ * PDU header of an iSCSI logout request ++ */ ++struct iscsi_logout_req_hdr_little_endian { ++#if defined(__BIG_ENDIAN) ++ u8 opcode; ++ u8 op_attr; ++#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0) ++#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0 ++#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) ++#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 ++ u16 rsrv0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 rsrv0; ++ u8 op_attr; ++#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0) ++#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0 ++#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) ++#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 ++ u8 opcode; ++#endif ++ u32 data_fields; ++#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) ++#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 ++#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) ++#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 ++ u32 rsrv2[2]; ++ u32 itt; ++#if defined(__BIG_ENDIAN) ++ u16 cid; ++ u16 rsrv1; ++#elif defined(__LITTLE_ENDIAN) ++ u16 rsrv1; ++ u16 cid; ++#endif ++ u32 cmd_sn; ++ u32 exp_stat_sn; ++ u32 rsrv3[4]; ++}; ++ ++/* ++ * PDU header of an iSCSI TMF request ++ */ ++struct iscsi_tmf_req_hdr_little_endian { ++#if defined(__BIG_ENDIAN) ++ u8 opcode; ++ u8 op_attr; ++#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0) ++#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0 ++#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) ++#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 ++ u16 rsrv0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 rsrv0; ++ u8 op_attr; ++#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0) ++#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0 ++#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) ++#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 ++ u8 opcode; ++#endif ++ u32 data_fields; ++#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) ++#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 ++#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) ++#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 ++ struct regpair lun; ++ u32 itt; ++ u32 referenced_task_tag; ++ u32 cmd_sn; ++ u32 exp_stat_sn; ++ u32 ref_cmd_sn; ++ u32 exp_data_sn; ++ u32 rsrv2[2]; ++}; ++ ++/* ++ * PDU header of an iSCSI Text request ++ */ ++struct iscsi_text_req_hdr_little_endian { ++#if defined(__BIG_ENDIAN) ++ u8 opcode; ++ u8 op_attr; ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0) ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7) ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7 ++ u16 rsrv0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 rsrv0; ++ u8 op_attr; ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0) ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7) ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7 ++ u8 opcode; ++#endif ++ u32 data_fields; ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) ++#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 ++ struct regpair lun; ++ u32 itt; ++ u32 ttt; ++ u32 cmd_sn; ++ u32 exp_stat_sn; ++ u32 rsrv3[4]; ++}; ++ ++/* ++ * PDU header of an iSCSI Nop-Out ++ */ ++struct iscsi_nop_out_hdr_little_endian { ++#if defined(__BIG_ENDIAN) ++ u8 opcode; ++ u8 op_attr; ++#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) ++#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 ++#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7) ++#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7 ++ u16 rsrv0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 rsrv0; ++ u8 op_attr; ++#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) ++#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 ++#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7) ++#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7 ++ u8 opcode; ++#endif ++ u32 data_fields; ++#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) ++#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 ++#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) ++#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 ++ struct regpair lun; ++ u32 itt; ++ u32 ttt; ++ u32 cmd_sn; ++ u32 exp_stat_sn; ++ u32 rsrv3[4]; ++}; ++ ++/* ++ * iscsi pdu headers in little endian form. ++ */ ++union iscsi_pdu_headers_little_endian { ++ u32 fullHeaderSize[12]; ++ struct iscsi_cmd_pdu_hdr_little_endian command_pdu_hdr; ++ struct iscsi_data_pdu_hdr_little_endian data_out_pdu_hdr; ++ struct iscsi_login_req_hdr_little_endian login_req_pdu_hdr; ++ struct iscsi_logout_req_hdr_little_endian logout_req_pdu_hdr; ++ struct iscsi_tmf_req_hdr_little_endian tmf_req_pdu_hdr; ++ struct iscsi_text_req_hdr_little_endian text_req_pdu_hdr; ++ struct iscsi_nop_out_hdr_little_endian nop_out_pdu_hdr; ++}; ++ ++struct iscsi_hq_bd { ++ union iscsi_pdu_headers_little_endian pdu_header; ++#if defined(__BIG_ENDIAN) ++ u16 reserved1; ++ u16 lcl_cmp_flg; ++#elif defined(__LITTLE_ENDIAN) ++ u16 lcl_cmp_flg; ++ u16 reserved1; ++#endif ++ u32 sgl_base_lo; ++ u32 sgl_base_hi; ++#if defined(__BIG_ENDIAN) ++ u8 sgl_size; ++ u8 sge_index; ++ u16 sge_offset; ++#elif defined(__LITTLE_ENDIAN) ++ u16 sge_offset; ++ u8 sge_index; ++ u8 sgl_size; ++#endif ++}; ++ ++ ++ ++ ++ ++ ++struct iscsi_task_context_entry_xuc_c_write_only { ++ u32 total_data_acked; ++}; ++ ++struct iscsi_task_context_r2t_table_entry { ++ u32 ttt; ++ u32 desired_data_len; ++}; ++ ++struct iscsi_task_context_entry_xuc_u_write_only { ++ u32 exp_r2t_sn; ++ struct iscsi_task_context_r2t_table_entry r2t_table[4]; ++#if defined(__BIG_ENDIAN) ++ u16 data_in_count; ++ u8 cq_id; ++ u8 valid_1b; ++#elif defined(__LITTLE_ENDIAN) ++ u8 valid_1b; ++ u8 cq_id; ++ u16 data_in_count; ++#endif ++}; ++ ++struct iscsi_task_context_entry_xuc { ++ struct iscsi_task_context_entry_xuc_c_write_only write_c; ++ u32 exp_data_transfer_len; ++ struct iscsi_task_context_entry_xuc_x_write_only write_x; ++ u32 lun_lo; ++ struct iscsi_task_context_entry_xuc_xu_write_both write_xu; ++ u32 lun_hi; ++ struct iscsi_task_context_entry_xuc_u_write_only write_u; ++}; ++ ++struct iscsi_task_context_entry_u { ++ u32 exp_r2t_buff_offset; ++ u32 rem_rcv_len; ++ u32 exp_data_sn; ++}; ++ ++struct iscsi_task_context_entry { ++ struct iscsi_task_context_entry_x tce_x; ++#if defined(__BIG_ENDIAN) ++ u16 data_out_count; ++ u16 rsrv0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 rsrv0; ++ u16 data_out_count; ++#endif ++ struct iscsi_task_context_entry_xuc tce_xuc; ++ struct iscsi_task_context_entry_u tce_u; ++ u32 rsrv1[7]; ++}; ++ ++ ++ ++ ++ ++ ++ ++ ++struct iscsi_task_context_entry_xuc_x_init_only { ++ struct regpair lun; ++ u32 exp_data_transfer_len; ++}; ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++/* ++ * ipv6 structure ++ */ ++struct ip_v6_addr { ++ u32 ip_addr_lo_lo; ++ u32 ip_addr_lo_hi; ++ u32 ip_addr_hi_lo; ++ u32 ip_addr_hi_hi; ++}; ++ ++ ++ ++/* ++ * l5cm- connection identification params ++ */ ++struct l5cm_conn_addr_params { ++ u32 pmtu; ++#if defined(__BIG_ENDIAN) ++ u8 remote_addr_3; ++ u8 remote_addr_2; ++ u8 remote_addr_1; ++ u8 remote_addr_0; ++#elif defined(__LITTLE_ENDIAN) ++ u8 remote_addr_0; ++ u8 remote_addr_1; ++ u8 remote_addr_2; ++ u8 remote_addr_3; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 params; ++#define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0) ++#define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0 ++#define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1) ++#define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1 ++ u8 remote_addr_5; ++ u8 remote_addr_4; ++#elif defined(__LITTLE_ENDIAN) ++ u8 remote_addr_4; ++ u8 remote_addr_5; ++ u16 params; ++#define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0) ++#define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0 ++#define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1) ++#define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1 ++#endif ++ struct ip_v6_addr local_ip_addr; ++ struct ip_v6_addr remote_ip_addr; ++ u32 ipv6_flow_label_20b; ++ u32 reserved1; ++#if defined(__BIG_ENDIAN) ++ u16 remote_tcp_port; ++ u16 local_tcp_port; ++#elif defined(__LITTLE_ENDIAN) ++ u16 local_tcp_port; ++ u16 remote_tcp_port; ++#endif ++}; ++ ++/* ++ * l5cm-xstorm connection buffer ++ */ ++struct l5cm_xstorm_conn_buffer { ++#if defined(__BIG_ENDIAN) ++ u16 rsrv1; ++ u16 params; ++#define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0) ++#define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0 ++#define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) ++#define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1 ++#elif defined(__LITTLE_ENDIAN) ++ u16 params; ++#define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0) ++#define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0 ++#define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) ++#define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1 ++ u16 rsrv1; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 mss; ++ u16 pseudo_header_checksum; ++#elif defined(__LITTLE_ENDIAN) ++ u16 pseudo_header_checksum; ++ u16 mss; ++#endif ++ u32 rcv_buf; ++ u32 rsrv2; ++ struct regpair context_addr; ++}; ++ ++/* ++ * l5cm-tstorm connection buffer ++ */ ++struct l5cm_tstorm_conn_buffer { ++ u32 snd_buf; ++ u32 rcv_buf; ++#if defined(__BIG_ENDIAN) ++ u16 params; ++#define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0) ++#define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0 ++#define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) ++#define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1 ++ u8 ka_max_probe_count; ++ u8 ka_enable; ++#elif defined(__LITTLE_ENDIAN) ++ u8 ka_enable; ++ u8 ka_max_probe_count; ++ u16 params; ++#define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0) ++#define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0 ++#define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) ++#define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1 ++#endif ++ u32 ka_timeout; ++ u32 ka_interval; ++ u32 max_rt_time; ++}; ++ ++/* ++ * l5cm connection buffer for active side ++ */ ++struct l5cm_active_conn_buffer { ++ struct l5cm_conn_addr_params conn_addr_buf; ++ struct l5cm_xstorm_conn_buffer xstorm_conn_buffer; ++ struct l5cm_tstorm_conn_buffer tstorm_conn_buffer; ++}; ++ ++ ++ ++/* ++ * The l5cm opaque buffer passed in add new connection ramrod passive side ++ */ ++struct l5cm_hash_input_string { ++ u32 seed; ++#if defined(__BIG_ENDIAN) ++ u16 remote_tcp_port; ++ u16 local_tcp_port; ++#elif defined(__LITTLE_ENDIAN) ++ u16 local_tcp_port; ++ u16 remote_tcp_port; ++#endif ++ struct ip_v6_addr local_ip_addr; ++ struct ip_v6_addr remote_ip_addr; ++ u32 remote_isn; ++ u32 zero_padded[5]; ++}; ++ ++ ++/* ++ * syn cookie component ++ */ ++struct l5cm_syn_cookie_comp { ++ u32 syn_cookie_chip_comp; ++#define L5CM_SYN_COOKIE_COMP_SEED_INDEX (0x7<<0) ++#define L5CM_SYN_COOKIE_COMP_SEED_INDEX_SHIFT 0 ++#define L5CM_SYN_COOKIE_COMP_RX_MSS_INDEX (0x7<<3) ++#define L5CM_SYN_COOKIE_COMP_RX_MSS_INDEX_SHIFT 3 ++#define L5CM_SYN_COOKIE_COMP_RX_WND_SCL_EN (0x1<<6) ++#define L5CM_SYN_COOKIE_COMP_RX_WND_SCL_EN_SHIFT 6 ++#define L5CM_SYN_COOKIE_COMP_RX_TS_EN (0x1<<7) ++#define L5CM_SYN_COOKIE_COMP_RX_TS_EN_SHIFT 7 ++#define L5CM_SYN_COOKIE_COMP_RX_WND_SCALE (0xF<<8) ++#define L5CM_SYN_COOKIE_COMP_RX_WND_SCALE_SHIFT 8 ++#define L5CM_SYN_COOKIE_COMP_DO_NOT_USE (0xF<<12) ++#define L5CM_SYN_COOKIE_COMP_DO_NOT_USE_SHIFT 12 ++#define L5CM_SYN_COOKIE_COMP_DO_NOT_USE1 (0xFFFF<<16) ++#define L5CM_SYN_COOKIE_COMP_DO_NOT_USE1_SHIFT 16 ++}; ++ ++/* ++ * data related to listeners of a TCP port ++ */ ++struct l5cm_port_listener_data { ++ u8 params; ++#define L5CM_PORT_LISTENER_DATA_ENABLE (0x1<<0) ++#define L5CM_PORT_LISTENER_DATA_ENABLE_SHIFT 0 ++#define L5CM_PORT_LISTENER_DATA_IP_INDEX (0xF<<1) ++#define L5CM_PORT_LISTENER_DATA_IP_INDEX_SHIFT 1 ++#define L5CM_PORT_LISTENER_DATA_NET_FILTER (0x1<<5) ++#define L5CM_PORT_LISTENER_DATA_NET_FILTER_SHIFT 5 ++#define L5CM_PORT_LISTENER_DATA_DEFFERED_MODE (0x1<<6) ++#define L5CM_PORT_LISTENER_DATA_DEFFERED_MODE_SHIFT 6 ++#define L5CM_PORT_LISTENER_DATA_MPA_MODE (0x1<<7) ++#define L5CM_PORT_LISTENER_DATA_MPA_MODE_SHIFT 7 ++}; ++ ++/* ++ * Opaque structure passed from U to X when final ack arrives ++ */ ++struct l5cm_opaque_buf { ++ u32 rcv_nxt; ++ u32 snd_nxt; ++ u32 ts_to_echo; ++ u32 snd_wnd; ++ struct l5cm_syn_cookie_comp syn_cookie; ++#if defined(__BIG_ENDIAN) ++ u16 rsrv2; ++ u8 rsrv; ++ struct l5cm_port_listener_data listener_data; ++#elif defined(__LITTLE_ENDIAN) ++ struct l5cm_port_listener_data listener_data; ++ u8 rsrv; ++ u16 rsrv2; ++#endif ++}; ++ ++ ++/* ++ * l5cm slow path element ++ */ ++struct l5cm_packet_size { ++ u32 size; ++ u32 rsrv; ++}; ++ ++ ++/* ++ * The final-ack union structure in PCS entry after final ack arrived ++ */ ++struct l5cm_pcse_ack { ++ struct l5cm_xstorm_conn_buffer tx_socket_params; ++ struct l5cm_opaque_buf opaque_buf; ++ struct l5cm_tstorm_conn_buffer rx_socket_params; ++}; ++ ++ ++/* ++ * The syn union structure in PCS entry after syn arrived ++ */ ++struct l5cm_pcse_syn { ++ struct l5cm_opaque_buf opaque_buf; ++ u32 rsrv[12]; ++}; ++ ++ ++/* ++ * pcs entry data for passive connections ++ */ ++struct l5cm_pcs_attributes { ++#if defined(__BIG_ENDIAN) ++ u16 pcs_id; ++ u8 status; ++ u8 flags; ++#define L5CM_PCS_ATTRIBUTES_NET_FILTER (0x1<<0) ++#define L5CM_PCS_ATTRIBUTES_NET_FILTER_SHIFT 0 ++#define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH (0x1<<1) ++#define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH_SHIFT 1 ++#define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT (0x1<<2) ++#define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT_SHIFT 2 ++#define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT (0x1<<3) ++#define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT_SHIFT 3 ++#define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC (0x1<<4) ++#define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC_SHIFT 4 ++#define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD (0x1<<5) ++#define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD_SHIFT 5 ++#define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET (0x1<<6) ++#define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET_SHIFT 6 ++#define L5CM_PCS_ATTRIBUTES_RSRV (0x1<<7) ++#define L5CM_PCS_ATTRIBUTES_RSRV_SHIFT 7 ++#elif defined(__LITTLE_ENDIAN) ++ u8 flags; ++#define L5CM_PCS_ATTRIBUTES_NET_FILTER (0x1<<0) ++#define L5CM_PCS_ATTRIBUTES_NET_FILTER_SHIFT 0 ++#define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH (0x1<<1) ++#define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH_SHIFT 1 ++#define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT (0x1<<2) ++#define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT_SHIFT 2 ++#define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT (0x1<<3) ++#define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT_SHIFT 3 ++#define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC (0x1<<4) ++#define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC_SHIFT 4 ++#define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD (0x1<<5) ++#define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD_SHIFT 5 ++#define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET (0x1<<6) ++#define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET_SHIFT 6 ++#define L5CM_PCS_ATTRIBUTES_RSRV (0x1<<7) ++#define L5CM_PCS_ATTRIBUTES_RSRV_SHIFT 7 ++ u8 status; ++ u16 pcs_id; ++#endif ++}; ++ ++ ++union l5cm_seg_params { ++ struct l5cm_pcse_syn syn_seg_params; ++ struct l5cm_pcse_ack ack_seg_params; ++}; ++ ++/* ++ * pcs entry data for passive connections ++ */ ++struct l5cm_pcs_hdr { ++ struct l5cm_hash_input_string hash_input_string; ++ struct l5cm_conn_addr_params conn_addr_buf; ++ u32 cid; ++ u32 hash_result; ++ union l5cm_seg_params seg_params; ++ struct l5cm_pcs_attributes att; ++#if defined(__BIG_ENDIAN) ++ u16 rsrv; ++ u16 rx_seg_size; ++#elif defined(__LITTLE_ENDIAN) ++ u16 rx_seg_size; ++ u16 rsrv; ++#endif ++}; ++ ++/* ++ * pcs entry for passive connections ++ */ ++struct l5cm_pcs_entry { ++ struct l5cm_pcs_hdr hdr; ++ u8 rx_segment[1516]; ++}; ++ ++ ++ ++ ++/* ++ * l5cm connection parameters ++ */ ++union l5cm_reduce_param_union { ++ u32 passive_side_scramble_key; ++ u32 pcs_id; ++}; ++ ++/* ++ * l5cm connection parameters ++ */ ++struct l5cm_reduce_conn { ++ union l5cm_reduce_param_union param; ++ u32 isn; ++}; ++ ++/* ++ * l5cm slow path element ++ */ ++union l5cm_specific_data { ++ u8 protocol_data[8]; ++ struct regpair phy_address; ++ struct l5cm_packet_size packet_size; ++ struct l5cm_reduce_conn reduced_conn; ++}; ++ ++/* ++ * l5 slow path element ++ */ ++struct l5cm_spe { ++ struct spe_hdr hdr; ++ union l5cm_specific_data data; ++}; ++ ++ ++ ++ ++/* ++ * Termination variables ++ */ ++struct l5cm_term_vars { ++ u8 BitMap; ++#define L5CM_TERM_VARS_TCP_STATE (0xF<<0) ++#define L5CM_TERM_VARS_TCP_STATE_SHIFT 0 ++#define L5CM_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4) ++#define L5CM_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4 ++#define L5CM_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5) ++#define L5CM_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5 ++#define L5CM_TERM_VARS_TERM_ON_CHIP (0x1<<6) ++#define L5CM_TERM_VARS_TERM_ON_CHIP_SHIFT 6 ++#define L5CM_TERM_VARS_RSRV (0x1<<7) ++#define L5CM_TERM_VARS_RSRV_SHIFT 7 ++}; ++ ++ ++ ++ ++/* ++ * Tstorm Tcp flags ++ */ ++struct tstorm_l5cm_tcp_flags { ++ u16 flags; ++#define TSTORM_L5CM_TCP_FLAGS_VLAN_ID (0xFFF<<0) ++#define TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT 0 ++#define TSTORM_L5CM_TCP_FLAGS_RSRV0 (0x1<<12) ++#define TSTORM_L5CM_TCP_FLAGS_RSRV0_SHIFT 12 ++#define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<13) ++#define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 13 ++#define TSTORM_L5CM_TCP_FLAGS_RSRV1 (0x3<<14) ++#define TSTORM_L5CM_TCP_FLAGS_RSRV1_SHIFT 14 ++}; ++ ++ ++/* ++ * Xstorm Tcp flags ++ */ ++struct xstorm_l5cm_tcp_flags { ++ u8 flags; ++#define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED (0x1<<0) ++#define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED_SHIFT 0 ++#define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<1) ++#define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 1 ++#define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN (0x1<<2) ++#define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN_SHIFT 2 ++#define XSTORM_L5CM_TCP_FLAGS_RSRV (0x1F<<3) ++#define XSTORM_L5CM_TCP_FLAGS_RSRV_SHIFT 3 ++}; ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++#endif /* __5710_HSI_CNIC_LE__ */ +diff -r 5f108bc568be drivers/net/57xx_iscsi_constants.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/57xx_iscsi_constants.h Tue Sep 01 13:50:08 2009 +0100 +@@ -0,0 +1,212 @@ ++#ifndef __57XX_ISCSI_CONSTANTS_H_ ++#define __57XX_ISCSI_CONSTANTS_H_ ++ ++/** ++* This file defines HSI constants for the iSCSI flows ++*/ ++ ++/* iSCSI request op codes */ ++#define ISCSI_OPCODE_NOP_OUT (0 | 0x40) ++#define ISCSI_OPCODE_SCSI_CMD (1) ++#define ISCSI_OPCODE_TMF_REQUEST (2 | 0x40) ++#define ISCSI_OPCODE_LOGIN_REQUEST (3 | 0x40) ++#define ISCSI_OPCODE_TEXT_REQUEST (4 | 0x40) ++#define ISCSI_OPCODE_DATA_OUT (5) ++#define ISCSI_OPCODE_LOGOUT_REQUEST (6 | 0x00) ++#define ISCSI_OPCODE_CLEANUP_REQUEST (7) ++ ++/* iSCSI response/messages op codes */ ++#define ISCSI_OPCODE_NOP_IN (0x20) ++#define ISCSI_OPCODE_SCSI_RESPONSE (0x21) ++#define ISCSI_OPCODE_TMF_RESPONSE (0x22) ++#define ISCSI_OPCODE_LOGIN_RESPONSE (0x23) ++#define ISCSI_OPCODE_TEXT_RESPONSE (0x24) ++#define ISCSI_OPCODE_DATA_IN (0x25) ++#define ISCSI_OPCODE_LOGOUT_RESPONSE (0x26) ++#define ISCSI_OPCODE_CLEANUP_RESPONSE (0x27) ++#define ISCSI_OPCODE_R2T (0x31) ++#define ISCSI_OPCODE_ASYNC_MSG (0x32) ++#define ISCSI_OPCODE_REJECT (0x3f) ++#define ISCSI_OPCODE_NOPOUT_LOCAL_COMPLETION (0) ++ ++/* iSCSI stages */ ++#define ISCSI_STAGE_SECURITY_NEGOTIATION (0) ++#define ISCSI_STAGE_LOGIN_OPERATIONAL_NEGOTIATION (1) ++#define ISCSI_STAGE_FULL_FEATURE_PHASE (3) ++ ++/* iSCSI parameter defaults */ ++#define ISCSI_DEFAULT_HEADER_DIGEST (0) ++#define ISCSI_DEFAULT_DATA_DIGEST (0) ++#define ISCSI_DEFAULT_INITIAL_R2T (1) ++#define ISCSI_DEFAULT_IMMEDIATE_DATA (1) ++#define ISCSI_DEFAULT_MAX_PDU_LENGTH (0x2000) ++#define ISCSI_DEFAULT_FIRST_BURST_LENGTH (0x10000) ++#define ISCSI_DEFAULT_MAX_BURST_LENGTH (0x40000) ++#define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1) ++ ++/* iSCSI parameter limits */ ++#define ISCSI_MIN_VAL_MAX_PDU_LENGTH (0x200) ++#define ISCSI_MAX_VAL_MAX_PDU_LENGTH (0xffffff) ++#define ISCSI_MIN_VAL_BURST_LENGTH (0x200) ++#define ISCSI_MAX_VAL_BURST_LENGTH (0xffffff) ++#define ISCSI_MIN_VAL_MAX_OUTSTANDING_R2T (1) ++#define ISCSI_MAX_VAL_MAX_OUTSTANDING_R2T (0xff) /* 0x10000 according to RFC */ ++ ++/* SCSI command response codes */ ++#define ISCSI_SCSI_CMD_RESPONSE_CMD_COMPLETED (0x00) ++#define ISCSI_SCSI_CMD_RESPONSE_TARGET_FAILURE (0x01) ++ ++/* SCSI command status codes */ ++#define ISCSI_SCSI_CMD_STATUS_GOOD (0x00) ++#define ISCSI_SCSI_CMD_STATUS_CHECK_CONDITION (0x02) ++#define ISCSI_SCSI_CMD_STATUS_INTERMIDIATE (0x10) ++ ++/* TMF codes */ ++#define ISCSI_TMF_ABORT_TASK (1) ++#define ISCSI_TMF_LOGICAL_UNIT_RESET (5) ++ ++/* TMF response codes */ ++#define ISCSI_TMF_RESPONSE_FUNCTION_COMPLETE (0x00) ++#define ISCSI_TMF_RESPONSE_TASK_DOESNT_EXIST (0x01) ++#define ISCSI_TMF_RESPONSE_LUN_DOESNT_EXIST (0x02) ++#define ISCSI_TMF_RESPONSE_TASK_STILL_ALLEGIANT (0x03) ++#define ISCSI_TMF_RESPONSE_FUNCTION_NOT_SUPPORTED (0x05) ++#define ISCSI_TMF_RESPONSE_FUNCTION_AUTHORIZATION_FAILED (0x06) ++#define ISCSI_TMF_RESPONSE_FUNCTION_REJECTED (0xff) ++ ++/* Logout reason codes */ ++/*#define ISCSI_LOGOUT_REASON_CLOSE_CONNECTION (1) */ ++ ++/* Logout response codes */ ++#define ISCSI_LOGOUT_RESPONSE_CONNECTION_CLOSED (0) ++#define ISCSI_LOGOUT_RESPONSE_CID_NOT_FOUND (1) ++#define ISCSI_LOGOUT_RESPONSE_CLEANUP_FAILED (3) ++ ++/* iSCSI task types */ ++#define ISCSI_TASK_TYPE_READ (0) ++#define ISCSI_TASK_TYPE_WRITE (1) ++#define ISCSI_TASK_TYPE_MPATH (2) ++ ++/* initial CQ sequence numbers */ ++#define ISCSI_INITIAL_SN (1) ++ ++/* KWQ (kernel work queue) layer codes */ ++#define ISCSI_KWQE_LAYER_CODE (6) ++ ++/* KWQ (kernel work queue) request op codes */ ++#define ISCSI_KWQE_OPCODE_OFFLOAD_CONN1 (0) ++#define ISCSI_KWQE_OPCODE_OFFLOAD_CONN2 (1) ++#define ISCSI_KWQE_OPCODE_UPDATE_CONN (2) ++#define ISCSI_KWQE_OPCODE_DESTROY_CONN (3) ++#define ISCSI_KWQE_OPCODE_INIT1 (4) ++#define ISCSI_KWQE_OPCODE_INIT2 (5) ++ ++/* KCQ (kernel completion queue) response op codes */ ++#define ISCSI_KCQE_OPCODE_OFFLOAD_CONN (0x10) ++#define ISCSI_KCQE_OPCODE_UPDATE_CONN (0x12) ++#define ISCSI_KCQE_OPCODE_DESTROY_CONN (0x13) ++#define ISCSI_KCQE_OPCODE_INIT (0x14) ++#define ISCSI_KCQE_OPCODE_CLEAN_TASK (0x15) ++#define ISCSI_KCQE_OPCODE_TCP_RESET (0x16) ++#define ISCSI_KCQE_OPCODE_TCP_SYN (0x17) ++#define ISCSI_KCQE_OPCODE_TCP_FIN (0X18) ++#define ISCSI_KCQE_OPCODE_TCP_ERROR (0x19) ++#define ISCSI_KCQE_OPCODE_CQ_EVENT_NOTIFICATION (0x20) ++#define ISCSI_KCQE_OPCODE_ISCSI_ERROR (0x21) ++ ++/* KCQ (kernel completion queue) completion status */ ++#define ISCSI_KCQE_COMPLETION_STATUS_SUCCESS (0) ++#define ISCSI_KCQE_COMPLETION_STATUS_INVALID_OPCODE (1) ++#define ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE (2) ++#define ISCSI_KCQE_COMPLETION_STATUS_CTX_FREE_FAILURE (3) ++#define ISCSI_KCQE_COMPLETION_STATUS_NIC_ERROR (4) ++ ++#define ISCSI_KCQE_COMPLETION_STATUS_HDR_DIG_ERR (0x5) ++#define ISCSI_KCQE_COMPLETION_STATUS_DATA_DIG_ERR (0x6) ++/*#define ISCSI_KCQE_COMPLETION_STATUS_DATA_DIG_ERR_DATA_IN (0x6) */ ++/*#define ISCSI_KCQE_COMPLETION_STATUS_DATA_DIG_ERR_RESPONSE (0x7) */ ++/*#define ISCSI_KCQE_COMPLETION_STATUS_DATA_DIG_ERR_REJECT (0x8) */ ++/*#define ISCSI_KCQE_COMPLETION_STATUS_DATA_DIG_ERR_ASYNC (0x9) */ ++ ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_UNEXPECTED_OPCODE (0xa) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_OPCODE (0xb) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_AHS_LEN (0xc) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_ITT (0xd) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_STATSN (0xe) ++ /* Response */ ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_EXP_DATASN (0xf) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T (0x10) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATA_SEG_LEN_IS_ZERO (0x2c) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATA_SEG_LEN_TOO_BIG (0x2d) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_0 (0x11) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_1 (0x12) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_2 (0x13) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_3 (0x14) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_4 (0x15) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_5 (0x16) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_6 (0x17) ++ /* Data-In */ ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REMAIN_RCV_LEN (0x18) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_MAX_RCV_PDU_LEN (0x19) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_F_BIT_ZERO (0x1a) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_TTT_NOT_RSRV (0x1b) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATASN (0x1c) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REMAIN_BURST_LEN (0x1d) ++ ++ /* R2T */ ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_BUFFER_OFF (0x1f) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_LUN (0x20) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_R2TSN (0x21) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_0 (0x22) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_1 (0x23) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T_EXCEED (0x24) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_TTT_IS_RSRV (0x25) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_MAX_BURST_LEN (0x26) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATA_SEG_LEN_NOT_ZERO (0x27) ++ /* TMF */ ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REJECT_PDU_LEN (0x28) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_ASYNC_PDU_LEN (0x29) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_NOPIN_PDU_LEN (0x2a) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T_IN_CLEANUP (0x2b) ++ ++/* IP/TCP processing errors: */ ++#define ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_IP_FRAGMENT (0x40) ++#define ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_IP_OPTIONS (0x41) ++#define ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_URGENT_FLAG (0x42) ++#define ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_MAX_RTRANS (0x43) ++ ++/* iSCSI licensing errors */ ++/* general iSCSI license not installed */ ++#define ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED (0x50) ++/* additional LOM specific iSCSI license not installed */ ++#define ISCSI_KCQE_COMPLETION_STATUS_LOM_ISCSI_NOT_ENABLED (0x51) ++ ++/* SQ/RQ/CQ DB structure sizes */ ++#define ISCSI_SQ_DB_SIZE (16) ++#define ISCSI_RQ_DB_SIZE (16) ++#define ISCSI_CQ_DB_SIZE (80) ++ ++/* Page size codes (for l5_wqe_flags in connection offload request) */ ++#define ISCSI_PAGE_SIZE_256 (0) ++#define ISCSI_PAGE_SIZE_512 (1) ++#define ISCSI_PAGE_SIZE_1K (2) ++#define ISCSI_PAGE_SIZE_2K (3) ++#define ISCSI_PAGE_SIZE_4K (4) ++#define ISCSI_PAGE_SIZE_8K (5) ++#define ISCSI_PAGE_SIZE_16K (6) ++#define ISCSI_PAGE_SIZE_32K (7) ++#define ISCSI_PAGE_SIZE_64K (8) ++#define ISCSI_PAGE_SIZE_128K (9) ++#define ISCSI_PAGE_SIZE_256K (10) ++#define ISCSI_PAGE_SIZE_512K (11) ++#define ISCSI_PAGE_SIZE_1M (12) ++#define ISCSI_PAGE_SIZE_2M (13) ++#define ISCSI_PAGE_SIZE_4M (14) ++#define ISCSI_PAGE_SIZE_8M (15) ++ ++/* Iscsi PDU related defines */ ++#define ISCSI_HEADER_SIZE (48) ++#define ISCSI_DIGEST_SHIFT (2) ++#define ISCSI_DIGEST_SIZE (4) ++ ++#endif /*__57XX_ISCSI_CONSTANTS_H_ */ +diff -r 5f108bc568be drivers/net/Kconfig +--- a/drivers/net/Kconfig Tue Sep 01 13:49:15 2009 +0100 ++++ b/drivers/net/Kconfig Tue Sep 01 13:50:08 2009 +0100 +@@ -2191,6 +2191,16 @@ + To compile this driver as a module, choose M here: the module + will be called bnx2. This is recommended. + ++config CNIC ++ tristate "Broadcom CNIC support" ++ depends on BNX2 ++ help ++ This driver supports offload features of Broadcom NetXtremeII ++ gigabit Ethernet cards. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called cnic. This is recommended. ++ + config SPIDER_NET + tristate "Spider Gigabit Ethernet driver" + depends on PCI && (PPC_IBM_CELL_BLADE || PPC_CELLEB) +diff -r 5f108bc568be drivers/net/Makefile +--- a/drivers/net/Makefile Tue Sep 01 13:49:15 2009 +0100 ++++ b/drivers/net/Makefile Tue Sep 01 13:50:08 2009 +0100 +@@ -67,6 +67,9 @@ + obj-$(CONFIG_FEALNX) += fealnx.o + obj-$(CONFIG_TIGON3) += tg3.o + obj-$(CONFIG_BNX2) += bnx2.o ++CFLAGS_bnx2.o += -DHAVE_LE32 -DHAVE_IP_HDR -DNEW_SKB ++obj-$(CONFIG_CNIC) += cnic.o ++CFLAGS_cnic.o += -DHAVE_LE32 -DHAVE_IP_HDR -DNEW_SKB + obj-$(CONFIG_BNX2X) += bnx2x.o + bnx2x-objs := bnx2x_main.o bnx2x_link.o + spidernet-y += spider_net.o spider_net_ethtool.o +diff -r 5f108bc568be drivers/net/bnx2.c +--- a/drivers/net/bnx2.c Tue Sep 01 13:49:15 2009 +0100 ++++ b/drivers/net/bnx2.c Tue Sep 01 13:50:08 2009 +0100 +@@ -1,6 +1,6 @@ + /* bnx2.c: Broadcom NX2 network driver. + * +- * Copyright (c) 2004-2008 Broadcom Corporation ++ * Copyright (c) 2004-2009 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -9,9 +9,23 @@ + * Written by: Michael Chan (mchan@broadcom.com) + */ + ++#include ++ ++#if (LINUX_VERSION_CODE < 0x020612) ++#include ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x020500) ++#if defined(CONFIG_MODVERSIONS) && defined(MODULE) && ! defined(MODVERSIONS) ++#define MODVERSIONS ++#include ++#endif ++#endif + + #include ++#if (LINUX_VERSION_CODE >= 0x020600) + #include ++#endif + + #include + #include +@@ -25,7 +39,9 @@ + #include + #include + #include ++#if (LINUX_VERSION_CODE >= 0x020600) + #include ++#endif + #include + #include + #include +@@ -39,26 +55,38 @@ + #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) + #define BCM_VLAN 1 + #endif ++ ++/* For driver stability, disable IPv6 checksum and TSO. */ ++#define __VMKLNX_NO_IPV6_CSUM__ 1 ++ ++#ifdef NETIF_F_TSO + #include + #include + #include ++#define BCM_TSO 1 ++#endif ++#if (LINUX_VERSION_CODE >= 0x020600) + #include ++#endif ++#ifndef BNX2_BOOT_DISK + #include ++#endif + #include + #include + #include ++#if (LINUX_VERSION_CODE >= 0x20617) && !defined(NETIF_F_MULTI_QUEUE) + #include +- ++#endif ++ ++#include "cnic_drv.h" + #include "bnx2.h" + #include "bnx2_fw.h" + #include "bnx2_fw2.h" + +-#define FW_BUF_SIZE 0x10000 +- + #define DRV_MODULE_NAME "bnx2" + #define PFX DRV_MODULE_NAME ": " +-#define DRV_MODULE_VERSION "1.8.0" +-#define DRV_MODULE_RELDATE "Aug 14, 2008" ++#define DRV_MODULE_VERSION "1.9.20b" ++#define DRV_MODULE_RELDATE "July 9, 2009" + + #define RUN_AT(x) (jiffies + (x)) + +@@ -69,14 +97,29 @@ + "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; + + MODULE_AUTHOR("Michael Chan "); +-MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709 Driver"); ++MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver"); + MODULE_LICENSE("GPL"); + MODULE_VERSION(DRV_MODULE_VERSION); + + static int disable_msi = 0; + ++#if (LINUX_VERSION_CODE >= 0x20600) + module_param(disable_msi, int, 0); + MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); ++#endif ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++static int disable_netq = 0; ++ ++module_param(disable_netq, int, 0); ++MODULE_PARM_DESC(disable_netq, "Disable NetQueue support on 5709/5716"); ++ ++static int force_netq = -1; ++module_param(force_netq, int, 0); ++MODULE_PARM_DESC(force_netq, "Enforce the number of NetQueues per port " ++ "(allowed values: 2-7, <2 is default value)"); ++ ++#endif + + typedef enum { + BCM5706 = 0, +@@ -131,7 +174,7 @@ + { PCI_VENDOR_ID_BROADCOM, 0x163b, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 }, + { PCI_VENDOR_ID_BROADCOM, 0x163c, +- PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 }, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S }, + { 0, } + }; + +@@ -235,6 +278,41 @@ + + MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); + ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++static int bnx2_netqueue_ops(vmknetddi_queueops_op_t op, void *args); ++static void bnx2_stop_netqueue_hw(struct bnx2 *bp); ++static int bnx2_start_netqueue_hw(struct bnx2 *bp); ++static void bnx2_netqueue_service_bnx2_msix(struct bnx2_napi *bnapi); ++#ifdef BNX2_DEBUG ++static u32 bnx2_read_ctx(struct bnx2 *bp, u32 offset); ++#endif ++ ++#define TRUE 1 ++#define FALSE 0 ++ ++#define for_each_nondefault_rx_queue(bp, var) \ ++ for (var = 1; var < bp->num_rx_rings; var++) ++#define for_each_nondefault_tx_queue(bp, var) \ ++ for (var = 1; var < bp->num_tx_rings; var++) ++#define is_multi(bp) (bp->num_rx_ring > 1) ++#endif /* defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) */ ++ ++#ifdef BNX2_BOOT_DISK ++u32 ether_crc_le(size_t len, unsigned char const *p) ++{ ++ u32 crc = ~0; ++ int i; ++#define CRCPOLY_LE 0xedb88320 ++ ++ while (len--) { ++ crc ^= *p++; ++ for (i = 0; i < 8; i++) ++ crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); ++ } ++ return crc; ++} ++#endif ++ + static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr) + { + u32 diff; +@@ -310,6 +388,184 @@ + spin_unlock_bh(&bp->indirect_lock); + } + ++#ifdef BCM_CNIC ++static int ++bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info) ++{ ++ struct bnx2 *bp = netdev_priv(dev); ++ struct drv_ctl_io *io = &info->data.io; ++ ++ switch (info->cmd) { ++ case DRV_CTL_IO_WR_CMD: ++ bnx2_reg_wr_ind(bp, io->offset, io->data); ++ break; ++ case DRV_CTL_IO_RD_CMD: ++ io->data = bnx2_reg_rd_ind(bp, io->offset); ++ break; ++ case DRV_CTL_CTX_WR_CMD: ++ bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data); ++ break; ++ default: ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static void bnx2_setup_cnic_irq_info(struct bnx2 *bp) ++{ ++ struct cnic_ops *c_ops; ++ struct cnic_eth_dev *cp = &bp->cnic_eth_dev; ++ struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; ++ int sb_id; ++ ++ rcu_read_lock(); ++ c_ops = rcu_dereference(bp->cnic_ops); ++ if (!c_ops) ++ goto done; ++ ++ if (bp->flags & BNX2_FLAG_USING_MSIX) { ++ cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; ++ bnapi->cnic_present = 0; ++ sb_id = bp->irq_nvecs; ++ cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; ++ } else { ++ cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; ++ bnapi->cnic_tag = bnapi->last_status_idx; ++ bnapi->cnic_present = 1; ++ sb_id = 0; ++ cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; ++ } ++ ++ cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector; ++ cp->irq_arr[0].status_blk = (void *) ++ ((unsigned long) bnapi->status_blk.msi + ++ (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id)); ++ cp->irq_arr[0].status_blk_num = sb_id; ++ cp->num_irq = 1; ++ ++done: ++ rcu_read_unlock(); ++} ++ ++static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops, ++ void *data) ++{ ++ struct bnx2 *bp = netdev_priv(dev); ++ struct cnic_eth_dev *cp = &bp->cnic_eth_dev; ++ ++ if (ops == NULL) ++ return -EINVAL; ++ ++#if !defined(__VMKLNX__) ++ if (!try_module_get(ops->cnic_owner)) ++ return -EBUSY; ++#endif ++ if (atomic_read(&bp->intr_sem) != 0) ++ return -EBUSY; ++ ++ spin_lock(&bp->cnic_lock); ++ if (cp->drv_state & CNIC_DRV_STATE_REGD) { ++ spin_unlock(&bp->cnic_lock); ++ return -EBUSY; ++ } ++ bp->cnic_data = data; ++ rcu_assign_pointer(bp->cnic_ops, ops); ++ ++ cp->num_irq = 0; ++ cp->drv_state = CNIC_DRV_STATE_REGD; ++ ++ bnx2_setup_cnic_irq_info(bp); ++ spin_unlock(&bp->cnic_lock); ++ ++ return 0; ++} ++ ++static int bnx2_unregister_cnic(struct net_device *dev) ++{ ++ struct bnx2 *bp = netdev_priv(dev); ++ struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; ++ struct cnic_eth_dev *cp = &bp->cnic_eth_dev; ++ ++ spin_lock(&bp->cnic_lock); ++ cp->drv_state = 0; ++#if !defined(__VMKLNX__) ++ module_put(bp->cnic_ops->cnic_owner); ++#endif ++ bnapi->cnic_present = 0; ++ rcu_assign_pointer(bp->cnic_ops, NULL); ++ spin_unlock(&bp->cnic_lock); ++#if !defined(__VMKLNX__) ++ synchronize_rcu(); ++#endif ++ return 0; ++} ++ ++struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev) ++{ ++ struct bnx2 *bp = netdev_priv(dev); ++ struct cnic_eth_dev *cp = &bp->cnic_eth_dev; ++ ++ cp->drv_owner = THIS_MODULE; ++ cp->chip_id = bp->chip_id; ++ cp->pdev = bp->pdev; ++ cp->io_base = bp->regview; ++ cp->drv_ctl = bnx2_drv_ctl; ++ cp->drv_register_cnic = bnx2_register_cnic; ++ cp->drv_unregister_cnic = bnx2_unregister_cnic; ++ ++ return cp; ++} ++EXPORT_SYMBOL(bnx2_cnic_probe); ++ ++static void ++bnx2_cnic_stop(struct bnx2 *bp) ++{ ++ struct cnic_ops *c_ops; ++ struct cnic_ctl_info info; ++ ++ rcu_read_lock(); ++ c_ops = rcu_dereference(bp->cnic_ops); ++ if (c_ops) { ++ info.cmd = CNIC_CTL_STOP_CMD; ++ c_ops->cnic_ctl(bp->cnic_data, &info); ++ } ++ rcu_read_unlock(); ++} ++ ++static void ++bnx2_cnic_start(struct bnx2 *bp) ++{ ++ struct cnic_ops *c_ops; ++ struct cnic_ctl_info info; ++ ++ rcu_read_lock(); ++ c_ops = rcu_dereference(bp->cnic_ops); ++ if (c_ops) { ++ if (!(bp->flags & BNX2_FLAG_USING_MSIX)) { ++ struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; ++ ++ bnapi->cnic_tag = bnapi->last_status_idx; ++ } ++ info.cmd = CNIC_CTL_START_CMD; ++ c_ops->cnic_ctl(bp->cnic_data, &info); ++ } ++ rcu_read_unlock(); ++} ++ ++#else ++ ++static void ++bnx2_cnic_stop(struct bnx2 *bp) ++{ ++} ++ ++static void ++bnx2_cnic_start(struct bnx2 *bp) ++{ ++} ++ ++#endif ++ + static int + bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) + { +@@ -457,32 +713,48 @@ + int i; + + atomic_inc(&bp->intr_sem); ++ if (!netif_running(bp->dev)) ++ return; ++ + bnx2_disable_int(bp); + for (i = 0; i < bp->irq_nvecs; i++) ++#if (LINUX_VERSION_CODE >= 0x2051c) + synchronize_irq(bp->irq_tbl[i].vector); ++#else ++ synchronize_irq(); ++#endif + } + + static void + bnx2_napi_disable(struct bnx2 *bp) + { ++#ifdef BNX2_NEW_NAPI + int i; + + for (i = 0; i < bp->irq_nvecs; i++) + napi_disable(&bp->bnx2_napi[i].napi); ++#else ++ netif_poll_disable(bp->dev); ++#endif + } + + static void + bnx2_napi_enable(struct bnx2 *bp) + { ++#ifdef BNX2_NEW_NAPI + int i; + + for (i = 0; i < bp->irq_nvecs; i++) + napi_enable(&bp->bnx2_napi[i].napi); ++#else ++ netif_poll_enable(bp->dev); ++#endif + } + + static void + bnx2_netif_stop(struct bnx2 *bp) + { ++ bnx2_cnic_stop(bp); + bnx2_disable_int_sync(bp); + if (netif_running(bp->dev)) { + bnx2_napi_disable(bp); +@@ -499,6 +771,7 @@ + netif_tx_wake_all_queues(bp->dev); + bnx2_napi_enable(bp); + bnx2_enable_int(bp); ++ bnx2_cnic_start(bp); + } + } + } +@@ -566,10 +839,11 @@ + struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; + struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; + +- txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); ++ txr->tx_buf_ring = kmalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); + if (txr->tx_buf_ring == NULL) + return -ENOMEM; + ++ memset(txr->tx_buf_ring, 0, SW_TXBD_RING_SIZE); + txr->tx_desc_ring = + pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE, + &txr->tx_desc_mapping); +@@ -663,9 +937,11 @@ + + /* Combine status and statistics blocks into one allocation. */ + status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block)); ++#ifdef CONFIG_PCI_MSI + if (bp->flags & BNX2_FLAG_MSIX_CAP) + status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC * + BNX2_SBLK_MSIX_ALIGN_SIZE); ++#endif + bp->status_stats_size = status_blk_size + + sizeof(struct statistics_block); + +@@ -704,7 +980,12 @@ + bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; + + if (CHIP_NUM(bp) == CHIP_NUM_5709) { ++ /* NetQ uses CID 100, so we need 16K of context memory */ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ bp->ctx_pages = 0x4000 / BCM_PAGE_SIZE; ++#else + bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE; ++#endif + if (bp->ctx_pages == 0) + bp->ctx_pages = 1; + for (i = 0; i < bp->ctx_pages; i++) { +@@ -1116,6 +1397,7 @@ + val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT); + } + bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); ++ + } + + static void +@@ -1131,7 +1413,7 @@ + } + } + +-static int ++static void + bnx2_set_mac_link(struct bnx2 *bp) + { + u32 val; +@@ -1197,8 +1479,6 @@ + + if (CHIP_NUM(bp) == CHIP_NUM_5709) + bnx2_init_all_rx_contexts(bp); +- +- return 0; + } + + static void +@@ -1499,6 +1779,8 @@ + + static int + bnx2_setup_remote_phy(struct bnx2 *bp, u8 port) ++__releases(&bp->phy_lock) ++__acquires(&bp->phy_lock) + { + u32 speed_arg = 0, pause_adv; + +@@ -1556,6 +1838,8 @@ + + static int + bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port) ++__releases(&bp->phy_lock) ++__acquires(&bp->phy_lock) + { + u32 adv, bmcr; + u32 new_adv = 0; +@@ -1643,7 +1927,7 @@ + if (bp->link_up) { + bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); + spin_unlock_bh(&bp->phy_lock); +- msleep(20); ++ bnx2_msleep(20); + spin_lock_bh(&bp->phy_lock); + } + +@@ -1658,7 +1942,7 @@ + * exchanging base pages plus 3 next pages and + * normally completes in about 120 msec. + */ +- bp->current_interval = SERDES_AN_TIMEOUT; ++ bp->current_interval = BNX2_SERDES_AN_TIMEOUT; + bp->serdes_an_pending = 1; + mod_timer(&bp->timer, jiffies + bp->current_interval); + } else { +@@ -1853,7 +2137,11 @@ + { + u32 evt_code; + +- evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB); ++ spin_lock(&bp->indirect_lock); ++ REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, ++ bp->shmem_base + BNX2_FW_EVT_CODE_MB); ++ evt_code = REG_RD(bp, BNX2_PCICFG_REG_WINDOW); ++ spin_unlock(&bp->indirect_lock); + switch (evt_code) { + case BNX2_FW_EVT_CODE_LINK_EVENT: + bnx2_remote_phy_event(bp); +@@ -1868,6 +2156,8 @@ + + static int + bnx2_setup_copper_phy(struct bnx2 *bp) ++__releases(&bp->phy_lock) ++__acquires(&bp->phy_lock) + { + u32 bmcr; + u32 new_bmcr; +@@ -1937,7 +2227,7 @@ + /* Force link down */ + bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); + spin_unlock_bh(&bp->phy_lock); +- msleep(50); ++ bnx2_msleep(50); + spin_lock_bh(&bp->phy_lock); + + bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); +@@ -1965,6 +2255,8 @@ + + static int + bnx2_setup_phy(struct bnx2 *bp, u8 port) ++__releases(&bp->phy_lock) ++__acquires(&bp->phy_lock) + { + if (bp->loopback == MAC_LOOPBACK) + return 0; +@@ -2001,6 +2293,9 @@ + bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val); + val &= ~MII_BNX2_SD_1000XCTL1_AUTODET; + val |= MII_BNX2_SD_1000XCTL1_FIBER; ++ /* NEMO temp. FIX */ ++ if (bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG) & 0x80000000) ++ val |= (1 << 3); + bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); + + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); +@@ -2178,6 +2473,8 @@ + + static int + bnx2_init_phy(struct bnx2 *bp, int reset_phy) ++__releases(&bp->phy_lock) ++__acquires(&bp->phy_lock) + { + u32 val; + int rc = 0; +@@ -2251,7 +2548,7 @@ + for (i = 0; i < 10; i++) { + if (bnx2_test_link(bp) == 0) + break; +- msleep(100); ++ bnx2_msleep(100); + } + + mac_mode = REG_RD(bp, BNX2_EMAC_MODE); +@@ -2280,8 +2577,8 @@ + return 0; + + /* wait for an acknowledgement. */ +- for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) { +- msleep(10); ++ for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) { ++ bnx2_msleep(10); + + val = bnx2_shmem_rd(bp, BNX2_FW_MB); + +@@ -2476,12 +2773,21 @@ + struct sw_pg *rx_pg = &rxr->rx_pg_ring[index]; + struct rx_bd *rxbd = + &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)]; +- struct page *page = netdev_alloc_page(bp->dev); ++ struct page *page = alloc_page(GFP_ATOMIC); + + if (!page) + return -ENOMEM; + mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE, + PCI_DMA_FROMDEVICE); ++#if (LINUX_VERSION_CODE >= 0x02061b) ++ if (pci_dma_mapping_error(bp->pdev, mapping)) { ++#else ++ if (pci_dma_mapping_error(mapping)) { ++#endif ++ __free_page(page); ++ return -EIO; ++ } ++ + rx_pg->page = page; + pci_unmap_addr_set(rx_pg, mapping, mapping); + rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; +@@ -2501,7 +2807,7 @@ + pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE, + PCI_DMA_FROMDEVICE); + +- netdev_free_page(bp->dev, page); ++ __free_page(page); + rx_pg->page = NULL; + } + +@@ -2524,6 +2830,14 @@ + + mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size, + PCI_DMA_FROMDEVICE); ++#if (LINUX_VERSION_CODE >= 0x02061b) ++ if (pci_dma_mapping_error(bp->pdev, mapping)) { ++#else ++ if (pci_dma_mapping_error(mapping)) { ++#endif ++ dev_kfree_skb(skb); ++ return -EIO; ++ } + + rx_buf->skb = skb; + pci_unmap_addr_set(rx_buf, mapping, mapping); +@@ -2589,17 +2903,21 @@ + { + struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; + u16 hw_cons, sw_cons, sw_ring_cons; ++#ifndef BCM_HAVE_MULTI_QUEUE ++ int tx_pkt = 0; ++#else + int tx_pkt = 0, index; + struct netdev_queue *txq; + + index = (bnapi - bp->bnx2_napi); + txq = netdev_get_tx_queue(bp->dev, index); ++#endif + + hw_cons = bnx2_get_hw_tx_cons(bnapi); + sw_cons = txr->tx_cons; + + while (sw_cons != hw_cons) { +- struct sw_bd *tx_buf; ++ struct sw_tx_bd *tx_buf; + struct sk_buff *skb; + int i, last; + +@@ -2608,14 +2926,16 @@ + tx_buf = &txr->tx_buf_ring[sw_ring_cons]; + skb = tx_buf->skb; + ++ /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */ ++ prefetch(&skb->end); ++ ++#ifdef BCM_TSO + /* partial BD completions possible with TSO packets */ +- if (skb_is_gso(skb)) { ++ if (tx_buf->is_gso) { + u16 last_idx, last_ring_idx; + +- last_idx = sw_cons + +- skb_shinfo(skb)->nr_frags + 1; +- last_ring_idx = sw_ring_cons + +- skb_shinfo(skb)->nr_frags + 1; ++ last_idx = sw_cons + tx_buf->nr_frags + 1; ++ last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1; + if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) { + last_idx++; + } +@@ -2623,12 +2943,12 @@ + break; + } + } +- ++#endif + pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping), + skb_headlen(skb), PCI_DMA_TODEVICE); + + tx_buf->skb = NULL; +- last = skb_shinfo(skb)->nr_frags; ++ last = tx_buf->nr_frags; + + for (i = 0; i < last; i++) { + sw_cons = NEXT_TX_BD(sw_cons); +@@ -2643,12 +2963,17 @@ + + sw_cons = NEXT_TX_BD(sw_cons); + ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ bnapi->stats.tx_packets++; ++ bnapi->stats.tx_bytes += skb->len; ++#endif + dev_kfree_skb(skb); + tx_pkt++; + if (tx_pkt == budget) + break; + +- hw_cons = bnx2_get_hw_tx_cons(bnapi); ++ if (hw_cons == sw_cons) ++ hw_cons = bnx2_get_hw_tx_cons(bnapi); + } + + txr->hw_tx_cons = hw_cons; +@@ -2661,6 +2986,25 @@ + */ + smp_mb(); + ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ if ((bnapi->netq_flags & BNX2_NETQ_FREE_TX_QUEUE_STATE) && ++ (sw_cons == txr->tx_prod)) { ++ bp->netq_flags = L2_KCQE_OPCODE_VALUE_VM_FREE_TX_QUEUE; ++ wake_up(&bp->netq_wait); ++ } ++ ++#endif ++ ++#ifndef BCM_HAVE_MULTI_QUEUE ++ if (unlikely(netif_queue_stopped(bp->dev)) && ++ (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) { ++ netif_tx_lock(bp->dev); ++ if ((netif_queue_stopped(bp->dev)) && ++ (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) ++ netif_wake_queue(bp->dev); ++ netif_tx_unlock(bp->dev); ++ } ++#else + if (unlikely(netif_tx_queue_stopped(txq)) && + (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) { + __netif_tx_lock(txq, smp_processor_id()); +@@ -2669,7 +3013,7 @@ + netif_tx_wake_queue(txq); + __netif_tx_unlock(txq); + } +- ++#endif + return tx_pkt; + } + +@@ -2679,10 +3023,30 @@ + { + struct sw_pg *cons_rx_pg, *prod_rx_pg; + struct rx_bd *cons_bd, *prod_bd; +- dma_addr_t mapping; +- int i; +- u16 hw_prod = rxr->rx_pg_prod, prod; ++ int i; ++ u16 hw_prod, prod; + u16 cons = rxr->rx_pg_cons; ++ ++ cons_rx_pg = &rxr->rx_pg_ring[cons]; ++ ++ /* The caller was unable to allocate a new page to replace the ++ * last one in the frags array, so we need to recycle that page ++ * and then free the skb. ++ */ ++ if (skb) { ++ struct page *page; ++ struct skb_shared_info *shinfo; ++ ++ shinfo = skb_shinfo(skb); ++ shinfo->nr_frags--; ++ page = shinfo->frags[shinfo->nr_frags].page; ++ shinfo->frags[shinfo->nr_frags].page = NULL; ++ ++ cons_rx_pg->page = page; ++ dev_kfree_skb(skb); ++ } ++ ++ hw_prod = rxr->rx_pg_prod; + + for (i = 0; i < count; i++) { + prod = RX_PG_RING_IDX(hw_prod); +@@ -2692,20 +3056,6 @@ + cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)]; + prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; + +- if (i == 0 && skb) { +- struct page *page; +- struct skb_shared_info *shinfo; +- +- shinfo = skb_shinfo(skb); +- shinfo->nr_frags--; +- page = shinfo->frags[shinfo->nr_frags].page; +- shinfo->frags[shinfo->nr_frags].page = NULL; +- mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE, +- PCI_DMA_FROMDEVICE); +- cons_rx_pg->page = page; +- pci_unmap_addr_set(cons_rx_pg, mapping, mapping); +- dev_kfree_skb(skb); +- } + if (prod != cons) { + prod_rx_pg->page = cons_rx_pg->page; + cons_rx_pg->page = NULL; +@@ -2791,6 +3141,8 @@ + skb_put(skb, hdr_len); + + for (i = 0; i < pages; i++) { ++ dma_addr_t mapping_old; ++ + frag_len = min(frag_size, (unsigned int) PAGE_SIZE); + if (unlikely(frag_len <= 4)) { + unsigned int tail = 4 - frag_len; +@@ -2813,13 +3165,15 @@ + } + rx_pg = &rxr->rx_pg_ring[pg_cons]; + +- pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), +- PAGE_SIZE, PCI_DMA_FROMDEVICE); +- ++ /* Don't unmap yet. If we're unable to allocate a new ++ * page, we need to recycle the page and the DMA addr. ++ */ ++ mapping_old = pci_unmap_addr(rx_pg, mapping); + if (i == pages - 1) + frag_len -= 4; + +- skb_add_rx_frag(skb, i, rx_pg->page, 0, frag_len); ++ bnx2_skb_fill_page_desc(skb, i, rx_pg->page, 0, ++ frag_len); + rx_pg->page = NULL; + + err = bnx2_alloc_rx_page(bp, rxr, +@@ -2832,7 +3186,13 @@ + return err; + } + ++ pci_unmap_page(bp->pdev, mapping_old, ++ PAGE_SIZE, PCI_DMA_FROMDEVICE); ++ + frag_size -= frag_len; ++ skb->data_len += frag_len; ++ skb->truesize += frag_len; ++ skb->len += frag_len; + + pg_prod = NEXT_RX_BD(pg_prod); + pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons)); +@@ -2898,18 +3258,8 @@ + + rx_hdr = (struct l2_fhdr *) skb->data; + len = rx_hdr->l2_fhdr_pkt_len; +- +- if ((status = rx_hdr->l2_fhdr_status) & +- (L2_FHDR_ERRORS_BAD_CRC | +- L2_FHDR_ERRORS_PHY_DECODE | +- L2_FHDR_ERRORS_ALIGNMENT | +- L2_FHDR_ERRORS_TOO_SHORT | +- L2_FHDR_ERRORS_GIANT_FRAME)) { +- +- bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons, +- sw_ring_prod); +- goto next_rx; +- } ++ status = rx_hdr->l2_fhdr_status; ++ + hdr_len = 0; + if (status & L2_FHDR_STATUS_SPLIT) { + hdr_len = rx_hdr->l2_fhdr_ip_xsum; +@@ -2919,6 +3269,36 @@ + pg_ring_used = 1; + } + ++ if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC | ++ L2_FHDR_ERRORS_PHY_DECODE | ++ L2_FHDR_ERRORS_ALIGNMENT | ++ L2_FHDR_ERRORS_TOO_SHORT | ++ L2_FHDR_ERRORS_GIANT_FRAME))) { ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ bnapi->stats.rx_errors++; ++ ++ if (status & L2_FHDR_ERRORS_BAD_CRC) ++ bnapi->stats.rx_crc_errors++; ++ ++ if (status & ++ (L2_FHDR_ERRORS_TOO_SHORT | ++ L2_FHDR_ERRORS_GIANT_FRAME)) ++ bnapi->stats.rx_frame_errors++; ++#endif ++ ++ bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons, ++ sw_ring_prod); ++ if (pg_ring_used) { ++ int pages; ++ ++ pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT; ++ ++ bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); ++ } ++ goto next_rx; ++ } ++ + len -= 4; + + if (len <= bp->rx_copy_thresh) { +@@ -2932,9 +3312,15 @@ + } + + /* aligned copy */ ++#if (LINUX_VERSION_CODE >= 0x20616) + skb_copy_from_linear_data_offset(skb, + BNX2_RX_OFFSET - 6, + new_skb->data, len + 6); ++#else ++ memcpy(new_skb->data, skb->data + BNX2_RX_OFFSET - 6, ++ len + 6); ++#endif ++ + skb_reserve(new_skb, 6); + skb_put(new_skb, len); + +@@ -2958,7 +3344,7 @@ + struct vlan_ethhdr *ve = (struct vlan_ethhdr *) + __skb_push(skb, 4); + +- memmove(ve, skb->data + 4, ETH_ALEN * 2); ++ bcm_memmove(ve, skb->data + 4, ETH_ALEN * 2); + ve->h_vlan_proto = htons(ETH_P_8021Q); + ve->h_vlan_TCI = htons(vtag); + len += 4; +@@ -2985,6 +3371,8 @@ + skb->ip_summed = CHECKSUM_UNNECESSARY; + } + ++ skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]); ++ + #ifdef BCM_VLAN + if (hw_vlan) + vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag); +@@ -2992,8 +3380,16 @@ + #endif + netif_receive_skb(skb); + ++#if (LINUX_VERSION_CODE < 0x02061b) || defined(__VMKLNX__) + bp->dev->last_rx = jiffies; ++#endif + rx_pkt++; ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ /* Update queue specific stats */ ++ bnapi->stats.rx_packets++; ++ bnapi->stats.rx_bytes += len; ++#endif + + next_rx: + sw_cons = NEXT_RX_BD(sw_cons); +@@ -3024,15 +3420,19 @@ + + } + ++#ifdef CONFIG_PCI_MSI + /* MSI ISR - The only difference between this and the INTx ISR + * is that the MSI interrupt is always serviced. + */ + static irqreturn_t ++#if (LINUX_VERSION_CODE >= 0x20613) + bnx2_msi(int irq, void *dev_instance) ++#else ++bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs) ++#endif + { + struct bnx2_napi *bnapi = dev_instance; + struct bnx2 *bp = bnapi->bp; +- struct net_device *dev = bp->dev; + + prefetch(bnapi->status_blk.msi); + REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, +@@ -3043,17 +3443,24 @@ + if (unlikely(atomic_read(&bp->intr_sem) != 0)) + return IRQ_HANDLED; + +- netif_rx_schedule(dev, &bnapi->napi); ++#ifdef BNX2_NEW_NAPI ++ napi_schedule(&bnapi->napi); ++#else ++ netif_rx_schedule(bp->dev); ++#endif + + return IRQ_HANDLED; + } + + static irqreturn_t ++#if (LINUX_VERSION_CODE >= 0x20613) + bnx2_msi_1shot(int irq, void *dev_instance) ++#else ++bnx2_msi_1shot(int irq, void *dev_instance, struct pt_regs *regs) ++#endif + { + struct bnx2_napi *bnapi = dev_instance; + struct bnx2 *bp = bnapi->bp; +- struct net_device *dev = bp->dev; + + prefetch(bnapi->status_blk.msi); + +@@ -3061,17 +3468,25 @@ + if (unlikely(atomic_read(&bp->intr_sem) != 0)) + return IRQ_HANDLED; + +- netif_rx_schedule(dev, &bnapi->napi); ++#ifdef BNX2_NEW_NAPI ++ napi_schedule(&bnapi->napi); ++#else ++ netif_rx_schedule(bp->dev); ++#endif + + return IRQ_HANDLED; + } ++#endif + + static irqreturn_t ++#if (LINUX_VERSION_CODE >= 0x20613) + bnx2_interrupt(int irq, void *dev_instance) ++#else ++bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs) ++#endif + { + struct bnx2_napi *bnapi = dev_instance; + struct bnx2 *bp = bnapi->bp; +- struct net_device *dev = bp->dev; + struct status_block *sblk = bnapi->status_blk.msi; + + /* When using INTx, it is possible for the interrupt to arrive +@@ -3098,10 +3513,17 @@ + if (unlikely(atomic_read(&bp->intr_sem) != 0)) + return IRQ_HANDLED; + +- if (netif_rx_schedule_prep(dev, &bnapi->napi)) { ++#ifdef BNX2_NEW_NAPI ++ if (napi_schedule_prep(&bnapi->napi)) { + bnapi->last_status_idx = sblk->status_idx; +- __netif_rx_schedule(dev, &bnapi->napi); +- } ++ __napi_schedule(&bnapi->napi); ++ } ++#else ++ if (netif_rx_schedule_prep(bp->dev)) { ++ bnapi->last_status_idx = sblk->status_idx; ++ __netif_rx_schedule(bp->dev); ++ } ++#endif + + return IRQ_HANDLED; + } +@@ -3129,6 +3551,11 @@ + if (bnx2_has_fast_work(bnapi)) + return 1; + ++#ifdef BCM_CNIC ++ if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx)) ++ return 1; ++#endif ++ + if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != + (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS)) + return 1; +@@ -3136,6 +3563,52 @@ + return 0; + } + ++#ifdef CONFIG_PCI_MSI ++static void ++bnx2_chk_missed_msi(struct bnx2 *bp) ++{ ++ struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; ++ u32 msi_ctrl; ++ ++ if (bnx2_has_work(bnapi)) { ++ msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL); ++ if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE)) ++ return; ++ ++ if (bnapi->last_status_idx == bp->idle_chk_status_idx) { ++ REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl & ++ ~BNX2_PCICFG_MSI_CONTROL_ENABLE); ++ REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl); ++#if (LINUX_VERSION_CODE >= 0x20613) ++ bnx2_msi(bp->irq_tbl[0].vector, bnapi); ++#else ++ bnx2_msi(bp->irq_tbl[0].vector, bnapi, NULL); ++#endif ++ } ++ } ++ ++ bp->idle_chk_status_idx = bnapi->last_status_idx; ++} ++#endif ++ ++#ifdef BCM_CNIC ++static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi) ++{ ++ struct cnic_ops *c_ops; ++ ++ if (!bnapi->cnic_present) ++ return; ++ ++ rcu_read_lock(); ++ c_ops = rcu_dereference(bp->cnic_ops); ++ if (c_ops) ++ bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data, ++ bnapi->status_blk.msi); ++ rcu_read_unlock(); ++} ++#endif ++ ++#ifdef BNX2_NEW_NAPI + static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi) + { + struct status_block *sblk = bnapi->status_blk.msi; +@@ -3188,7 +3661,7 @@ + rmb(); + if (likely(!bnx2_has_fast_work(bnapi))) { + +- netif_rx_complete(bp->dev, napi); ++ napi_complete(napi); + REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | + BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | + bnapi->last_status_idx); +@@ -3210,17 +3683,29 @@ + + work_done = bnx2_poll_work(bp, bnapi, work_done, budget); + +- if (unlikely(work_done >= budget)) +- break; ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ if ((disable_netq == 0) && ++ (bp->flags & BNX2_FLAG_USING_MSIX) && ++ (CHIP_NUM(bp) == CHIP_NUM_5709)) ++ bnx2_netqueue_service_bnx2_msix(bnapi); ++#endif ++ ++#ifdef BCM_CNIC ++ bnx2_poll_cnic(bp, bnapi); ++#endif + + /* bnapi->last_status_idx is used below to tell the hw how + * much work has been processed, so we must read it before + * checking for more work. + */ + bnapi->last_status_idx = sblk->status_idx; ++ ++ if (unlikely(work_done >= budget)) ++ break; ++ + rmb(); + if (likely(!bnx2_has_work(bnapi))) { +- netif_rx_complete(bp->dev, napi); ++ napi_complete(napi); + if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) { + REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, + BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | +@@ -3242,6 +3727,77 @@ + return work_done; + } + ++#else ++ ++static int ++bnx2_poll(struct net_device *dev, int *budget) ++{ ++ struct bnx2 *bp = netdev_priv(dev); ++ struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; ++ struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; ++ struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; ++ struct status_block *sblk = bnapi->status_blk.msi; ++ u32 status_attn_bits = sblk->status_attn_bits; ++ u32 status_attn_bits_ack = sblk->status_attn_bits_ack; ++ ++ if ((status_attn_bits & STATUS_ATTN_EVENTS) != ++ (status_attn_bits_ack & STATUS_ATTN_EVENTS)) { ++ ++ bnx2_phy_int(bp, bnapi); ++ ++ /* This is needed to take care of transient status ++ * during link changes. ++ */ ++ REG_WR(bp, BNX2_HC_COMMAND, ++ bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); ++ REG_RD(bp, BNX2_HC_COMMAND); ++ } ++ ++ if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons) ++ bnx2_tx_int(bp, bnapi, 0); ++ ++ if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) { ++ int orig_budget = *budget; ++ int work_done; ++ ++ if (orig_budget > dev->quota) ++ orig_budget = dev->quota; ++ ++ work_done = bnx2_rx_int(bp, bnapi, orig_budget); ++ *budget -= work_done; ++ dev->quota -= work_done; ++ } ++ ++#ifdef BCM_CNIC ++ bnx2_poll_cnic(bp, bnapi); ++#endif ++ ++ bnapi->last_status_idx = sblk->status_idx; ++ rmb(); ++ ++ if (!bnx2_has_work(bnapi)) { ++ netif_rx_complete(dev); ++ if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) { ++ REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, ++ BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | ++ bnapi->last_status_idx); ++ return 0; ++ } ++ REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, ++ BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | ++ BNX2_PCICFG_INT_ACK_CMD_MASK_INT | ++ bnapi->last_status_idx); ++ ++ REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, ++ BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | ++ bnapi->last_status_idx); ++ return 0; ++ } ++ ++ return 1; ++} ++#endif ++ + /* Called with rtnl_lock from vlan functions and also netif_tx_lock + * from set_multicast. + */ +@@ -3250,7 +3806,9 @@ + { + struct bnx2 *bp = netdev_priv(dev); + u32 rx_mode, sort_mode; ++#ifdef HAVE_SET_RX_MODE + struct dev_addr_list *uc_ptr; ++#endif + int i; + + if (!netif_running(dev)) +@@ -3309,6 +3867,7 @@ + sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN; + } + ++#ifdef HAVE_SET_RX_MODE + uc_ptr = NULL; + if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) { + rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; +@@ -3327,6 +3886,7 @@ + } + + } ++#endif + + if (rx_mode != bp->rx_mode) { + bp->rx_mode = rx_mode; +@@ -3338,6 +3898,83 @@ + REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA); + + spin_unlock_bh(&bp->phy_lock); ++} ++ ++#define FW_BUF_SIZE 0x10000 ++ ++static int ++bnx2_gunzip_init(struct bnx2 *bp) ++{ ++ if ((bp->gunzip_buf = vmalloc(FW_BUF_SIZE)) == NULL) ++ goto gunzip_nomem1; ++ ++ if ((bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL)) == NULL) ++ goto gunzip_nomem2; ++ ++ bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL); ++ if (bp->strm->workspace == NULL) ++ goto gunzip_nomem3; ++ ++ return 0; ++ ++gunzip_nomem3: ++ kfree(bp->strm); ++ bp->strm = NULL; ++ ++gunzip_nomem2: ++ vfree(bp->gunzip_buf); ++ bp->gunzip_buf = NULL; ++ ++gunzip_nomem1: ++ printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for " ++ "uncompression.\n", bp->dev->name); ++ return -ENOMEM; ++} ++ ++static void ++bnx2_gunzip_end(struct bnx2 *bp) ++{ ++ kfree(bp->strm->workspace); ++ ++ kfree(bp->strm); ++ bp->strm = NULL; ++ ++ if (bp->gunzip_buf) { ++ vfree(bp->gunzip_buf); ++ bp->gunzip_buf = NULL; ++ } ++} ++ ++static int ++bnx2_gunzip(struct bnx2 *bp, const u8 *zbuf, ++ int len, void **outbuf, int *outlen) ++{ ++ int rc; ++ ++ bp->strm->next_in = zbuf; ++ bp->strm->avail_in = len; ++ bp->strm->next_out = bp->gunzip_buf; ++ bp->strm->avail_out = FW_BUF_SIZE; ++ ++ rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); ++ if (rc != Z_OK) ++ return rc; ++ ++ rc = zlib_inflate(bp->strm, Z_FINISH); ++ ++ *outlen = FW_BUF_SIZE - bp->strm->avail_out; ++ *outbuf = bp->gunzip_buf; ++ ++ if ((rc != Z_OK) && (rc != Z_STREAM_END)) ++ printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n", ++ bp->dev->name, bp->strm->msg); ++ ++ zlib_inflateEnd(bp->strm); ++ ++ if (rc == Z_STREAM_END) ++ return 0; ++ ++ return rc; + } + + static void +@@ -3394,14 +4031,20 @@ + + /* Load the Text area. */ + offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); ++ + if (fw->gz_text) { +- int j; +- +- rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text, +- fw->gz_text_len); +- if (rc < 0) ++ u32 text_len; ++ void *text; ++ ++ rc = bnx2_gunzip(bp, fw->gz_text, fw->gz_text_len, &text, ++ &text_len); ++ if (rc) + return rc; + ++ fw->text = text; ++ } ++ if (fw->text) { ++ int j; + for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { + bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j])); + } +@@ -3465,13 +4108,15 @@ + bnx2_init_cpus(struct bnx2 *bp) + { + struct fw_info *fw; +- int rc, rv2p_len; +- void *text, *rv2p; ++ int rc = 0, rv2p_len; ++ void *text; ++ const void *rv2p; ++ u32 text_len; ++ ++ if ((rc = bnx2_gunzip_init(bp)) != 0) ++ return rc; + + /* Initialize the RV2P processor. */ +- text = vmalloc(FW_BUF_SIZE); +- if (!text) +- return -ENOMEM; + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + rv2p = bnx2_xi_rv2p_proc1; + rv2p_len = sizeof(bnx2_xi_rv2p_proc1); +@@ -3479,11 +4124,11 @@ + rv2p = bnx2_rv2p_proc1; + rv2p_len = sizeof(bnx2_rv2p_proc1); + } +- rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len); +- if (rc < 0) ++ rc = bnx2_gunzip(bp, rv2p, rv2p_len, &text, &text_len); ++ if (rc) + goto init_cpu_err; + +- load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1); ++ load_rv2p_fw(bp, text, text_len, RV2P_PROC1); + + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + rv2p = bnx2_xi_rv2p_proc2; +@@ -3492,11 +4137,11 @@ + rv2p = bnx2_rv2p_proc2; + rv2p_len = sizeof(bnx2_rv2p_proc2); + } +- rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len); +- if (rc < 0) ++ rc = bnx2_gunzip(bp, rv2p, rv2p_len, &text, &text_len); ++ if (rc) + goto init_cpu_err; + +- load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2); ++ load_rv2p_fw(bp, text, text_len, RV2P_PROC2); + + /* Initialize the RX Processor. */ + if (CHIP_NUM(bp) == CHIP_NUM_5709) +@@ -3504,7 +4149,6 @@ + else + fw = &bnx2_rxp_fw_06; + +- fw->text = text; + rc = load_cpu_fw(bp, &cpu_reg_rxp, fw); + if (rc) + goto init_cpu_err; +@@ -3515,7 +4159,6 @@ + else + fw = &bnx2_txp_fw_06; + +- fw->text = text; + rc = load_cpu_fw(bp, &cpu_reg_txp, fw); + if (rc) + goto init_cpu_err; +@@ -3526,7 +4169,6 @@ + else + fw = &bnx2_tpat_fw_06; + +- fw->text = text; + rc = load_cpu_fw(bp, &cpu_reg_tpat, fw); + if (rc) + goto init_cpu_err; +@@ -3537,7 +4179,6 @@ + else + fw = &bnx2_com_fw_06; + +- fw->text = text; + rc = load_cpu_fw(bp, &cpu_reg_com, fw); + if (rc) + goto init_cpu_err; +@@ -3548,11 +4189,12 @@ + else + fw = &bnx2_cp_fw_06; + +- fw->text = text; + rc = load_cpu_fw(bp, &cpu_reg_cp, fw); ++ if (rc) ++ goto init_cpu_err; + + init_cpu_err: +- vfree(text); ++ bnx2_gunzip_end(bp); + return rc; + } + +@@ -3573,7 +4215,7 @@ + + if (pmcsr & PCI_PM_CTRL_STATE_MASK) + /* delay required during transition out of D3hot */ +- msleep(20); ++ bnx2_msleep(20); + + val = REG_RD(bp, BNX2_EMAC_MODE); + val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; +@@ -4406,7 +5048,7 @@ + */ + if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || + (CHIP_ID(bp) == CHIP_ID_5706_A1)) +- msleep(20); ++ bnx2_msleep(20); + + /* Reset takes approximate 30 usec */ + for (i = 0; i < 10; i++) { +@@ -4462,7 +5104,7 @@ + static int + bnx2_init_chip(struct bnx2 *bp) + { +- u32 val; ++ u32 val, mtu; + int rc, i; + + /* Make sure the interrupt is not active. */ +@@ -4527,8 +5169,11 @@ + val = REG_RD(bp, BNX2_MQ_CONFIG); + val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; + val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; +- if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1) +- val |= BNX2_MQ_CONFIG_HALT_DIS; ++ if (CHIP_NUM(bp) == CHIP_NUM_5709) { ++ val |= BNX2_MQ_CONFIG_BIN_MQ_MODE; ++ if (CHIP_REV(bp) == CHIP_REV_Ax) ++ val |= BNX2_MQ_CONFIG_HALT_DIS; ++ } + + REG_WR(bp, BNX2_MQ_CONFIG, val); + +@@ -4554,13 +5199,24 @@ + REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); + + /* Program the MTU. Also include 4 bytes for CRC32. */ +- val = bp->dev->mtu + ETH_HLEN + 4; ++ mtu = bp->dev->mtu; ++ val = mtu + ETH_HLEN + ETH_FCS_LEN; + if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) + val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; + REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); + ++ if (mtu < 1500) ++ mtu = 1500; ++ ++ bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu)); ++ bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu)); ++ bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu)); ++ ++ memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size); + for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) + bp->bnx2_napi[i].last_status_idx = 0; ++ ++ bp->idle_chk_status_idx = 0xffff; + + bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE; + +@@ -4595,7 +5251,7 @@ + REG_WR(bp, BNX2_HC_CMD_TICKS, + (bp->cmd_ticks_int << 16) | bp->cmd_ticks); + +- if (CHIP_NUM(bp) == CHIP_NUM_5708) ++ if (bp->flags & BNX2_FLAG_BROKEN_STATS) + REG_WR(bp, BNX2_HC_STATS_TICKS, 0); + else + REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks); +@@ -4616,7 +5272,7 @@ + } + + if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI) +- val |= BNX2_HC_CONFIG_ONE_SHOT; ++ val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM; + + REG_WR(bp, BNX2_HC_CONFIG, val); + +@@ -4803,6 +5459,14 @@ + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + val = REG_RD(bp, BNX2_MQ_MAP_L2_5); + REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM); ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ /* Set in the RX context the proper CID location ++ * for the completion ++ */ ++ if(disable_netq == 0) ++ bnx2_ctx_wr(bp, rx_cid_addr, 0x04, 1 << 16); ++#endif + } + + bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); +@@ -4926,7 +5590,7 @@ + static void + bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size) + { +- u32 rx_size, rx_space, jumbo_size; ++ u32 rx_size, rx_space; + + /* 8 for CRC and VLAN */ + rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8; +@@ -4938,10 +5602,11 @@ + bp->rx_pg_ring_size = 0; + bp->rx_max_pg_ring = 0; + bp->rx_max_pg_ring_idx = 0; ++#if !defined(__VMKLNX__) + if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) { + int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; + +- jumbo_size = size * pages; ++ u32 jumbo_size = size * pages; + if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT) + jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT; + +@@ -4952,6 +5617,7 @@ + rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET; + bp->rx_copy_thresh = 0; + } ++#endif + + bp->rx_buf_use_size = rx_size; + /* hw alignment */ +@@ -4976,7 +5642,7 @@ + continue; + + for (j = 0; j < TX_DESC_CNT; ) { +- struct sw_bd *tx_buf = &txr->tx_buf_ring[j]; ++ struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; + struct sk_buff *skb = tx_buf->skb; + int k, last; + +@@ -4999,8 +5665,8 @@ + skb_shinfo(skb)->frags[j].size, + PCI_DMA_TODEVICE); + } ++ j += last + 1; + dev_kfree_skb(skb); +- j += k + 1; + } + } + } +@@ -5533,6 +6199,12 @@ + return -ENODEV; + + if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { ++ int i; ++ ++ for (i = 0; i < 6 && !bp->link_up; i++) { ++ if (bnx2_msleep_interruptible(500)) ++ break; ++ } + if (bp->link_up) + return 0; + return -ENODEV; +@@ -5572,7 +6244,7 @@ + break; + } + +- msleep_interruptible(10); ++ bnx2_msleep_interruptible(10); + } + if (i < 10) + return 0; +@@ -5624,7 +6296,7 @@ + } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { + u32 bmcr; + +- bp->current_interval = bp->timer_interval; ++ bp->current_interval = BNX2_TIMER_INTERVAL; + + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); + +@@ -5653,7 +6325,7 @@ + bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; + } + } else +- bp->current_interval = bp->timer_interval; ++ bp->current_interval = BNX2_TIMER_INTERVAL; + + if (check_link) { + u32 val; +@@ -5694,15 +6366,15 @@ + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); + if (bmcr & BMCR_ANENABLE) { + bnx2_enable_forced_2g5(bp); +- bp->current_interval = SERDES_FORCED_TIMEOUT; ++ bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT; + } else { + bnx2_disable_forced_2g5(bp); + bp->serdes_an_pending = 2; +- bp->current_interval = bp->timer_interval; ++ bp->current_interval = BNX2_TIMER_INTERVAL; + } + + } else +- bp->current_interval = bp->timer_interval; ++ bp->current_interval = BNX2_TIMER_INTERVAL; + + spin_unlock(&bp->phy_lock); + } +@@ -5718,13 +6390,19 @@ + if (atomic_read(&bp->intr_sem) != 0) + goto bnx2_restart_timer; + ++#ifdef CONFIG_PCI_MSI ++ if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) == ++ BNX2_FLAG_USING_MSI) ++ bnx2_chk_missed_msi(bp); ++#endif ++ + bnx2_send_heart_beat(bp); + + bp->stats_blk->stat_FwRxDrop = + bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT); + + /* workaround occasional corrupted counters */ +- if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks) ++ if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks) + REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | + BNX2_HC_COMMAND_STATS_NOW); + +@@ -5774,19 +6452,25 @@ + free_irq(irq->vector, &bp->bnx2_napi[i]); + irq->requested = 0; + } ++#ifdef CONFIG_PCI_MSI + if (bp->flags & BNX2_FLAG_USING_MSI) + pci_disable_msi(bp->pdev); + else if (bp->flags & BNX2_FLAG_USING_MSIX) + pci_disable_msix(bp->pdev); + + bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI); +-} +- ++#endif ++} ++ ++#ifdef CONFIG_PCI_MSI + static void + bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) + { ++#ifdef BNX2_NEW_NAPI + int i, rc; + struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC]; ++ struct net_device *dev = bp->dev; ++ const int len = sizeof(bp->irq_tbl[0].name); + + bnx2_setup_msix_tbl(bp); + REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); +@@ -5796,9 +6480,6 @@ + for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { + msix_ent[i].entry = i; + msix_ent[i].vector = 0; +- +- strcpy(bp->irq_tbl[i].name, bp->dev->name); +- bp->irq_tbl[i].handler = bnx2_msi_1shot; + } + + rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC); +@@ -5807,21 +6488,36 @@ + + bp->irq_nvecs = msix_vecs; + bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI; +- for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) ++ for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { + bp->irq_tbl[i].vector = msix_ent[i].vector; +-} ++ snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); ++ bp->irq_tbl[i].handler = bnx2_msi_1shot; ++ } ++#endif ++} ++#endif + + static void + bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi) + { ++#ifdef CONFIG_PCI_MSI + int cpus = num_online_cpus(); ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ int max_rings = (bp->dev->mtu <= 1500) ? RX_MAX_RINGS : 4; ++ int msix_vecs = min(cpus + 1, max_rings); ++ if(force_netq >= 2) ++ msix_vecs = min(force_netq, RX_MAX_RINGS); ++#else + int msix_vecs = min(cpus + 1, RX_MAX_RINGS); ++#endif ++#endif + + bp->irq_tbl[0].handler = bnx2_interrupt; + strcpy(bp->irq_tbl[0].name, bp->dev->name); + bp->irq_nvecs = 1; + bp->irq_tbl[0].vector = bp->pdev->irq; + ++#ifdef CONFIG_PCI_MSI + if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1) + bnx2_enable_msix(bp, msix_vecs); + +@@ -5838,10 +6534,28 @@ + bp->irq_tbl[0].vector = bp->pdev->irq; + } + } +- ++#endif ++#ifdef BCM_CNIC ++ spin_lock(&bp->cnic_lock); ++ bnx2_setup_cnic_irq_info(bp); ++ spin_unlock(&bp->cnic_lock); ++#endif ++ ++#ifndef BCM_HAVE_MULTI_QUEUE ++ bp->num_tx_rings = 1; ++#else ++#if defined(__VMKLNX__) ++#if defined(__VMKNETDDI_QUEUEOPS__) ++ bp->num_tx_rings = bp->irq_nvecs; ++ bp->dev->real_num_tx_queues = bp->num_tx_rings; ++#else ++ bp->num_tx_rings = 1; ++#endif ++#else + bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs); ++#endif + bp->dev->real_num_tx_queues = bp->num_tx_rings; +- ++#endif + bp->num_rx_rings = bp->irq_nvecs; + } + +@@ -5858,7 +6572,9 @@ + bnx2_disable_int(bp); + + bnx2_setup_int_mode(bp, disable_msi); ++#ifdef BNX2_NEW_NAPI + bnx2_napi_enable(bp); ++#endif + rc = bnx2_alloc_mem(bp); + if (rc) + goto open_err; +@@ -5877,6 +6593,7 @@ + + bnx2_enable_int(bp); + ++#ifdef CONFIG_PCI_MSI + if (bp->flags & BNX2_FLAG_USING_MSI) { + /* Test MSI to make sure it is working + * If MSI test fails, go back to INTx mode +@@ -5905,17 +6622,32 @@ + bnx2_enable_int(bp); + } + } ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ if ((disable_netq == 0) && ++ (bp->flags & BNX2_FLAG_USING_MSIX) && ++ (CHIP_NUM(bp) == CHIP_NUM_5709)) { ++ rc = bnx2_start_netqueue_hw(bp); ++ ++ if (rc != 0) ++ goto open_err; ++ } ++#endif ++ + if (bp->flags & BNX2_FLAG_USING_MSI) + printk(KERN_INFO PFX "%s: using MSI\n", dev->name); + else if (bp->flags & BNX2_FLAG_USING_MSIX) + printk(KERN_INFO PFX "%s: using MSIX\n", dev->name); ++#endif + + netif_tx_start_all_queues(dev); + + return 0; + + open_err: ++#ifdef BNX2_NEW_NAPI + bnx2_napi_disable(bp); ++#endif + bnx2_free_skbs(bp); + bnx2_free_irq(bp); + bnx2_free_mem(bp); +@@ -5923,9 +6655,17 @@ + } + + static void ++#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) + bnx2_reset_task(struct work_struct *work) +-{ ++#else ++bnx2_reset_task(void *data) ++#endif ++{ ++#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) + struct bnx2 *bp = container_of(work, struct bnx2, reset_task); ++#else ++ struct bnx2 *bp = data; ++#endif + + if (!netif_running(bp->dev)) + return; +@@ -5944,7 +6684,11 @@ + struct bnx2 *bp = netdev_priv(dev); + + /* This allows the netif to be shutdown gracefully before resetting */ ++#if (LINUX_VERSION_CODE >= 0x20600) + schedule_work(&bp->reset_task); ++#else ++ schedule_task(&bp->reset_task); ++#endif + } + + #ifdef BCM_VLAN +@@ -5954,15 +6698,43 @@ + { + struct bnx2 *bp = netdev_priv(dev); + +- bnx2_netif_stop(bp); ++ if (netif_running(dev)) ++ bnx2_netif_stop(bp); + + bp->vlgrp = vlgrp; ++ ++ if (!netif_running(dev)) ++ return; ++ + bnx2_set_rx_mode(dev); + if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN) + bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1); + + bnx2_netif_start(bp); + } ++ ++#if (LINUX_VERSION_CODE < 0x20616) ++/* Called with rtnl_lock */ ++static void ++bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid) ++{ ++ struct bnx2 *bp = netdev_priv(dev); ++ ++ if (netif_running(dev)) ++ bnx2_netif_stop(bp); ++ ++ vlan_group_set_device(bp->vlgrp, vid, NULL); ++ ++ if (!netif_running(dev)) ++ return; ++ ++ bnx2_set_rx_mode(dev); ++ if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN) ++ bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1); ++ ++ bnx2_netif_start(bp); ++} ++#endif + #endif + + /* Called with netif_tx_lock. +@@ -5975,10 +6747,14 @@ + struct bnx2 *bp = netdev_priv(dev); + dma_addr_t mapping; + struct tx_bd *txbd; +- struct sw_bd *tx_buf; ++ struct sw_tx_bd *tx_buf; + u32 len, vlan_tag_flags, last_frag, mss; + u16 prod, ring_prod; + int i; ++#ifndef BCM_HAVE_MULTI_QUEUE ++ struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; ++ struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; ++#else + struct bnx2_napi *bnapi; + struct bnx2_tx_ring_info *txr; + struct netdev_queue *txq; +@@ -5988,10 +6764,15 @@ + bnapi = &bp->bnx2_napi[i]; + txr = &bnapi->tx_ring; + txq = netdev_get_tx_queue(dev, i); ++#endif + + if (unlikely(bnx2_tx_avail(bp, txr) < + (skb_shinfo(skb)->nr_frags + 1))) { ++#ifndef BCM_HAVE_MULTI_QUEUE ++ netif_stop_queue(dev); ++#else + netif_tx_stop_queue(txq); ++#endif + printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n", + dev->name); + +@@ -6012,14 +6793,20 @@ + (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16)); + } + #endif ++#ifdef BCM_TSO + if ((mss = skb_shinfo(skb)->gso_size)) { +- u32 tcp_opt_len, ip_tcp_len; ++ u32 tcp_opt_len; + struct iphdr *iph; + ++ tcp_opt_len = tcp_optlen(skb); ++ ++ if (skb_transport_offset(skb) + tcp_opt_len + ++ sizeof(struct tcphdr) + mss >= skb->len) ++ goto abort_tso; ++ + vlan_tag_flags |= TX_BD_FLAGS_SW_LSO; + +- tcp_opt_len = tcp_optlen(skb); +- ++#ifndef BCM_NO_TSO6 + if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { + u32 tcp_off = skb_transport_offset(skb) - + sizeof(struct ipv6hdr) - ETH_HLEN; +@@ -6036,31 +6823,32 @@ + TX_BD_FLAGS_TCP6_OFF4_SHL); + mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL; + } +- } else { +- if (skb_header_cloned(skb) && +- pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { +- dev_kfree_skb(skb); +- return NETDEV_TX_OK; +- } +- +- ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); +- ++ } else ++#endif ++ { + iph = ip_hdr(skb); +- iph->check = 0; +- iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); +- tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, +- iph->daddr, 0, +- IPPROTO_TCP, +- 0); + if (tcp_opt_len || (iph->ihl > 5)) { + vlan_tag_flags |= ((iph->ihl - 5) + + (tcp_opt_len >> 2)) << 8; + } + } +- } else ++ } ++ else ++abort_tso: ++#endif ++ { + mss = 0; ++ } + + mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE); ++#if (LINUX_VERSION_CODE >= 0x02061b) ++ if (pci_dma_mapping_error(bp->pdev, mapping)) { ++#else ++ if (pci_dma_mapping_error(mapping)) { ++#endif ++ dev_kfree_skb(skb); ++ return NETDEV_TX_OK; ++ } + + tx_buf = &txr->tx_buf_ring[ring_prod]; + tx_buf->skb = skb; +@@ -6074,6 +6862,8 @@ + txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START; + + last_frag = skb_shinfo(skb)->nr_frags; ++ tx_buf->nr_frags = last_frag; ++ tx_buf->is_gso = skb_is_gso(skb); + + for (i = 0; i < last_frag; i++) { + skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; +@@ -6108,9 +6898,17 @@ + dev->trans_start = jiffies; + + if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) { ++#ifndef BCM_HAVE_MULTI_QUEUE ++ netif_stop_queue(dev); ++#else + netif_tx_stop_queue(txq); ++#endif + if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh) ++#ifndef BCM_HAVE_MULTI_QUEUE ++ netif_wake_queue(dev); ++#else + netif_tx_wake_queue(txq); ++#endif + } + + return NETDEV_TX_OK; +@@ -6122,10 +6920,21 @@ + { + struct bnx2 *bp = netdev_priv(dev); + ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ if ((disable_netq == 0) && ++ (bp->flags & BNX2_FLAG_USING_MSIX) && ++ (CHIP_NUM(bp) == CHIP_NUM_5709)) ++ bnx2_stop_netqueue_hw(bp); ++#endif ++ ++#if (LINUX_VERSION_CODE >= 0x20616) + cancel_work_sync(&bp->reset_task); ++#endif + + bnx2_disable_int_sync(bp); ++#ifdef BNX2_NEW_NAPI + bnx2_napi_disable(bp); ++#endif + del_timer_sync(&bp->timer); + bnx2_shutdown_chip(bp); + bnx2_free_irq(bp); +@@ -6187,7 +6996,8 @@ + stats_blk->stat_EtherStatsOverrsizePkts); + + net_stats->rx_over_errors = +- (unsigned long) stats_blk->stat_IfInMBUFDiscards; ++ (unsigned long) (stats_blk->stat_IfInFTQDiscards + ++ stats_blk->stat_IfInMBUFDiscards); + + net_stats->rx_frame_errors = + (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors; +@@ -6220,8 +7030,8 @@ + net_stats->tx_carrier_errors; + + net_stats->rx_missed_errors = +- (unsigned long) (stats_blk->stat_IfInMBUFDiscards + +- stats_blk->stat_FwRxDrop); ++ (unsigned long) (stats_blk->stat_IfInFTQDiscards + ++ stats_blk->stat_IfInMBUFDiscards + stats_blk->stat_FwRxDrop); + + return net_stats; + } +@@ -6391,6 +7201,11 @@ + strcpy(info->version, DRV_MODULE_VERSION); + strcpy(info->bus_info, pci_name(bp->pdev)); + strcpy(info->fw_version, bp->fw_version); ++ ++#if defined(VMWARE_ESX_DDK_VERSION) && \ ++ (VMWARE_ESX_DDK_VERSION >= 35000) && (VMWARE_ESX_DDK_VERSION < 40000) ++ info->eedump_len = bnx2_get_eeprom_len(dev); ++#endif + } + + #define BNX2_REGDUMP_LEN (32 * 1024) +@@ -6518,11 +7333,11 @@ + bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); + spin_unlock_bh(&bp->phy_lock); + +- msleep(20); ++ bnx2_msleep(20); + + spin_lock_bh(&bp->phy_lock); + +- bp->current_interval = SERDES_AN_TIMEOUT; ++ bp->current_interval = BNX2_SERDES_AN_TIMEOUT; + bp->serdes_an_pending = 1; + mod_timer(&bp->timer, jiffies + bp->current_interval); + } +@@ -6536,6 +7351,9 @@ + return 0; + } + ++#if (LINUX_VERSION_CODE >= 0x20418) || \ ++ (defined(VMWARE_ESX_DDK_VERSION) && \ ++ ((VMWARE_ESX_DDK_VERSION >= 35000) && (VMWARE_ESX_DDK_VERSION < 40000))) + static int + bnx2_get_eeprom_len(struct net_device *dev) + { +@@ -6546,7 +7364,9 @@ + + return (int) bp->flash_size; + } +- ++#endif ++ ++#ifdef ETHTOOL_GEEPROM + static int + bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, + u8 *eebuf) +@@ -6563,7 +7383,9 @@ + + return rc; + } +- ++#endif ++ ++#ifdef ETHTOOL_SEEPROM + static int + bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, + u8 *eebuf) +@@ -6580,6 +7402,7 @@ + + return rc; + } ++#endif + + static int + bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) +@@ -6635,7 +7458,7 @@ + 0xff; + + bp->stats_ticks = coal->stats_block_coalesce_usecs; +- if (CHIP_NUM(bp) == CHIP_NUM_5708) { ++ if (bp->flags & BNX2_FLAG_BROKEN_STATS) { + if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC) + bp->stats_ticks = USEC_PER_SEC; + } +@@ -6764,6 +7587,7 @@ + return 0; + } + ++#ifdef BCM_TSO + static int + bnx2_set_tso(struct net_device *dev, u32 data) + { +@@ -6778,12 +7602,11 @@ + NETIF_F_TSO_ECN); + return 0; + } +- +-#define BNX2_NUM_STATS 46 ++#endif + + static struct { + char string[ETH_GSTRING_LEN]; +-} bnx2_stats_str_arr[BNX2_NUM_STATS] = { ++} bnx2_stats_str_arr[] = { + { "rx_bytes" }, + { "rx_error_bytes" }, + { "tx_bytes" }, +@@ -6828,9 +7651,64 @@ + { "tx_xoff_frames" }, + { "rx_mac_ctrl_frames" }, + { "rx_filtered_packets" }, ++ { "rx_ftq_discards" }, + { "rx_discards" }, + { "rx_fw_discards" }, +-}; ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ { "[0] rx_packets" }, ++ { "[0] rx_bytes" }, ++ { "[0] rx_errors" }, ++ { "[0] tx_packets" }, ++ { "[0] tx_bytes" }, ++ { "[1] rx_packets" }, ++ { "[1] rx_bytes" }, ++ { "[1] rx_errors" }, ++ { "[1] tx_packets" }, ++ { "[1] tx_bytes" }, ++ { "[2] rx_packets" }, ++ { "[2] rx_bytes" }, ++ { "[2] rx_errors" }, ++ { "[2] tx_packets" }, ++ { "[2] tx_bytes" }, ++ { "[3] rx_packets" }, ++ { "[3] rx_bytes" }, ++ { "[3] rx_errors" }, ++ { "[3] tx_packets" }, ++ { "[3] tx_bytes" }, ++ { "[4] rx_packets" }, ++ { "[4] rx_bytes" }, ++ { "[4] rx_errors" }, ++ { "[4] tx_packets" }, ++ { "[4] tx_bytes" }, ++ { "[5] rx_packets" }, ++ { "[5] rx_bytes" }, ++ { "[5] rx_errors" }, ++ { "[5] tx_packets" }, ++ { "[5] tx_bytes" }, ++ { "[6] rx_packets" }, ++ { "[6] rx_bytes" }, ++ { "[6] rx_errors" }, ++ { "[6] tx_packets" }, ++ { "[6] tx_bytes" }, ++ { "[7] rx_packets" }, ++ { "[7] rx_bytes" }, ++ { "[7] rx_errors" }, ++ { "[7] tx_packets" }, ++ { "[7] tx_bytes" }, ++ { "[8] rx_packets" }, ++ { "[8] rx_bytes" }, ++ { "[8] rx_errors" }, ++ { "[8] tx_packets" }, ++ { "[8] tx_bytes" }, ++#endif ++}; ++ ++#define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\ ++ sizeof(bnx2_stats_str_arr[0])) ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++#define BNX2_NUM_NETQ_STATS 45 ++#endif + + #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4) + +@@ -6879,6 +7757,7 @@ + STATS_OFFSET32(stat_OutXoffSent), + STATS_OFFSET32(stat_MacControlFramesReceived), + STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), ++ STATS_OFFSET32(stat_IfInFTQDiscards), + STATS_OFFSET32(stat_IfInMBUFDiscards), + STATS_OFFSET32(stat_FwRxDrop), + }; +@@ -6891,7 +7770,7 @@ + 4,0,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4, +- 4,4,4,4,4,4, ++ 4,4,4,4,4,4,4, + }; + + static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = { +@@ -6899,7 +7778,7 @@ + 4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4, +- 4,4,4,4,4,4, ++ 4,4,4,4,4,4,4, + }; + + #define BNX2_NUM_TESTS 6 +@@ -6915,6 +7794,7 @@ + { "link_test (online)" }, + }; + ++#ifdef ETHTOOL_GFLAGS + static int + bnx2_get_sset_count(struct net_device *dev, int sset) + { +@@ -6927,6 +7807,13 @@ + return -EOPNOTSUPP; + } + } ++#else ++static int ++bnx2_self_test_count(struct net_device *dev) ++{ ++ return BNX2_NUM_TESTS; ++} ++#endif + + static void + bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) +@@ -6965,7 +7852,7 @@ + for (i = 0; i < 7; i++) { + if (bp->link_up) + break; +- msleep_interruptible(1000); ++ bnx2_msleep_interruptible(1000); + } + } + +@@ -7002,6 +7889,14 @@ + } + } + ++#ifndef ETHTOOL_GFLAGS ++static int ++bnx2_get_stats_count(struct net_device *dev) ++{ ++ return BNX2_NUM_STATS; ++} ++#endif ++ + static void + bnx2_get_ethtool_stats(struct net_device *dev, + struct ethtool_stats *stats, u64 *buf) +@@ -7023,8 +7918,11 @@ + stats_len_arr = bnx2_5706_stats_len_arr; + else + stats_len_arr = bnx2_5708_stats_len_arr; +- ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ for (i = 0; i < BNX2_NUM_STATS - BNX2_NUM_NETQ_STATS; i++) { ++#else + for (i = 0; i < BNX2_NUM_STATS; i++) { ++#endif + if (stats_len_arr[i] == 0) { + /* skip this counter */ + buf[i] = 0; +@@ -7041,6 +7939,23 @@ + bnx2_stats_offset_arr[i])) << 32) + + *(hw_stats + bnx2_stats_offset_arr[i] + 1); + } ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ /* Copy over the NetQ specific statistics */ ++ { ++ int j; ++ ++ for (j = 0; j < BNX2_MAX_MSIX_VEC; j++) { ++ struct bnx2_napi *bnapi = &bp->bnx2_napi[j]; ++ ++ buf[i + (j*5) + 0] = (u64) (bnapi->stats.rx_packets); ++ buf[i + (j*5) + 1] = (u64) (bnapi->stats.rx_bytes); ++ buf[i + (j*5) + 2] = (u64) (bnapi->stats.rx_errors); ++ buf[i + (j*5) + 3] = (u64) (bnapi->stats.tx_packets); ++ buf[i + (j*5) + 4] = (u64) (bnapi->stats.tx_bytes); ++ } ++ } ++#endif + } + + static int +@@ -7070,7 +7985,7 @@ + BNX2_EMAC_LED_TRAFFIC_OVERRIDE | + BNX2_EMAC_LED_TRAFFIC); + } +- msleep_interruptible(500); ++ bnx2_msleep_interruptible(500); + if (signal_pending(current)) + break; + } +@@ -7083,18 +7998,26 @@ + return 0; + } + ++#if (LINUX_VERSION_CODE >= 0x20418) + static int + bnx2_set_tx_csum(struct net_device *dev, u32 data) + { + struct bnx2 *bp = netdev_priv(dev); + + if (CHIP_NUM(bp) == CHIP_NUM_5709) ++#if (LINUX_VERSION_CODE < 0x2060c) ++ return (bnx2_set_tx_hw_csum(dev, data)); ++#elif (LINUX_VERSION_CODE >= 0x20617) + return (ethtool_op_set_tx_ipv6_csum(dev, data)); ++#else ++ return (ethtool_op_set_tx_hw_csum(dev, data)); ++#endif + else + return (ethtool_op_set_tx_csum(dev, data)); + } +- +-static const struct ethtool_ops bnx2_ethtool_ops = { ++#endif ++ ++static struct ethtool_ops bnx2_ethtool_ops = { + .get_settings = bnx2_get_settings, + .set_settings = bnx2_set_settings, + .get_drvinfo = bnx2_get_drvinfo, +@@ -7104,9 +8027,15 @@ + .set_wol = bnx2_set_wol, + .nway_reset = bnx2_nway_reset, + .get_link = ethtool_op_get_link, ++#if (LINUX_VERSION_CODE >= 0x20418) + .get_eeprom_len = bnx2_get_eeprom_len, ++#endif ++#ifdef ETHTOOL_GEEPROM + .get_eeprom = bnx2_get_eeprom, ++#endif ++#ifdef ETHTOOL_SEEPROM + .set_eeprom = bnx2_set_eeprom, ++#endif + .get_coalesce = bnx2_get_coalesce, + .set_coalesce = bnx2_set_coalesce, + .get_ringparam = bnx2_get_ringparam, +@@ -7115,21 +8044,45 @@ + .set_pauseparam = bnx2_set_pauseparam, + .get_rx_csum = bnx2_get_rx_csum, + .set_rx_csum = bnx2_set_rx_csum, ++ .get_tx_csum = ethtool_op_get_tx_csum, ++#if (LINUX_VERSION_CODE >= 0x20418) + .set_tx_csum = bnx2_set_tx_csum, ++#endif ++ .get_sg = ethtool_op_get_sg, + .set_sg = ethtool_op_set_sg, ++#ifdef BCM_TSO ++ .get_tso = ethtool_op_get_tso, + .set_tso = bnx2_set_tso, ++#endif ++#ifndef ETHTOOL_GFLAGS ++ .self_test_count = bnx2_self_test_count, ++#endif + .self_test = bnx2_self_test, + .get_strings = bnx2_get_strings, + .phys_id = bnx2_phys_id, ++#ifndef ETHTOOL_GFLAGS ++ .get_stats_count = bnx2_get_stats_count, ++#endif + .get_ethtool_stats = bnx2_get_ethtool_stats, ++#ifdef ETHTOOL_GPERMADDR ++#if (LINUX_VERSION_CODE < 0x020617) ++ .get_perm_addr = ethtool_op_get_perm_addr, ++#endif ++#endif ++#ifdef ETHTOOL_GFLAGS + .get_sset_count = bnx2_get_sset_count, ++#endif + }; + + /* Called with rtnl_lock */ + static int + bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) + { ++#if (LINUX_VERSION_CODE >= 0x020607) + struct mii_ioctl_data *data = if_mii(ifr); ++#else ++ struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_ifru; ++#endif + struct bnx2 *bp = netdev_priv(dev); + int err; + +@@ -7216,9 +8169,32 @@ + { + struct bnx2 *bp = netdev_priv(dev); + +- disable_irq(bp->pdev->irq); +- bnx2_interrupt(bp->pdev->irq, dev); +- enable_irq(bp->pdev->irq); ++#if defined(RED_HAT_LINUX_KERNEL) && (LINUX_VERSION_CODE < 0x020600) ++ if (netdump_mode) { ++ bnx2_interrupt(bp->pdev->irq, &bp->bnx2_napi[0], NULL); ++ if (dev->poll_list.prev) { ++ int budget = 64; ++ ++ bnx2_poll(dev, &budget); ++ } ++ } ++ else ++#endif ++ { ++ int i; ++ ++ for (i = 0; i < bp->irq_nvecs; i++) { ++ unsigned int irq = bp->irq_tbl[i].vector; ++ ++ disable_irq(irq); ++#if (LINUX_VERSION_CODE >= 0x20613) ++ bnx2_interrupt(irq, &bp->bnx2_napi[i]); ++#else ++ bnx2_interrupt(irq, &bp->bnx2_napi[i], NULL); ++#endif ++ enable_irq(irq); ++ } ++ } + } + #endif + +@@ -7321,7 +8297,12 @@ + u32 reg; + u64 dma_mask, persist_dma_mask; + ++#if (LINUX_VERSION_CODE < 0x20610) ++ SET_MODULE_OWNER(dev); ++#endif ++#if (LINUX_VERSION_CODE >= 0x20419) + SET_NETDEV_DEV(dev, &pdev->dev); ++#endif + bp = netdev_priv(dev); + + bp->flags = 0; +@@ -7348,7 +8329,9 @@ + } + + pci_set_master(pdev); ++#if (LINUX_VERSION_CODE >= 0x020611) + pci_save_state(pdev); ++#endif + + bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); + if (bp->pm_cap == 0) { +@@ -7363,10 +8346,26 @@ + + spin_lock_init(&bp->phy_lock); + spin_lock_init(&bp->indirect_lock); ++ spin_lock_init(&bp->cnic_lock); ++#if (LINUX_VERSION_CODE >= 0x20600) ++#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) + INIT_WORK(&bp->reset_task, bnx2_reset_task); ++#else ++ INIT_WORK(&bp->reset_task, bnx2_reset_task, bp); ++#endif ++#else ++ INIT_TQUEUE(&bp->reset_task, bnx2_reset_task, bp); ++#endif + + dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0); +- mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS); ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ if(disable_netq == 0) ++ mem_len = MB_GET_CID_ADDR(NETQUEUE_KCQ_CID + 2); ++ else ++ mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1); ++#else ++ mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1); ++#endif + dev->mem_end = dev->mem_start + mem_len; + dev->irq = pdev->irq; + +@@ -7408,12 +8407,15 @@ + rc = -EIO; + goto err_out_unmap; + } +- } +- ++ bp->flags |= BNX2_FLAG_BROKEN_STATS; ++ } ++ ++#ifdef CONFIG_PCI_MSI + if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) { + if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) + bp->flags |= BNX2_FLAG_MSIX_CAP; + } ++#endif + + if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) { + if (pci_find_capability(pdev, PCI_CAP_ID_MSI)) +@@ -7506,7 +8508,7 @@ + reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); + if (reg & BNX2_CONDITION_MFW_RUN_MASK) + break; +- msleep(10); ++ bnx2_msleep(10); + } + } + reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); +@@ -7539,20 +8541,19 @@ + + bp->rx_csum = 1; + +- bp->tx_quick_cons_trip_int = 20; ++ bp->tx_quick_cons_trip_int = 2; + bp->tx_quick_cons_trip = 20; +- bp->tx_ticks_int = 80; ++ bp->tx_ticks_int = 18; + bp->tx_ticks = 80; + +- bp->rx_quick_cons_trip_int = 6; +- bp->rx_quick_cons_trip = 6; ++ bp->rx_quick_cons_trip_int = 2; ++ bp->rx_quick_cons_trip = 12; + bp->rx_ticks_int = 18; + bp->rx_ticks = 18; + + bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS; + +- bp->timer_interval = HZ; +- bp->current_interval = HZ; ++ bp->current_interval = BNX2_TIMER_INTERVAL; + + bp->phy_addr = 1; + +@@ -7595,7 +8596,8 @@ + + if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || + (CHIP_ID(bp) == CHIP_ID_5708_B0) || +- (CHIP_ID(bp) == CHIP_ID_5708_B1)) { ++ (CHIP_ID(bp) == CHIP_ID_5708_B1) || ++ !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) { + bp->flags |= BNX2_FLAG_NO_WOL; + bp->wol = 0; + } +@@ -7612,6 +8614,7 @@ + bp->cmd_ticks_int = bp->cmd_ticks; + } + ++#ifdef CONFIG_PCI_MSI + /* Disable MSI on 5706 if AMD 8132 bridge is found. + * + * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes +@@ -7628,21 +8631,22 @@ + while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_8132_BRIDGE, + amd_8132))) { +- +- if (amd_8132->revision >= 0x10 && +- amd_8132->revision <= 0x13) { ++ u8 rev; ++ ++ pci_read_config_byte(amd_8132, PCI_REVISION_ID, &rev); ++ if (rev >= 0x10 && rev <= 0x13) { + disable_msi = 1; + pci_dev_put(amd_8132); + break; + } + } + } +- ++#endif + bnx2_set_default_link(bp); + bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; + + init_timer(&bp->timer); +- bp->timer.expires = RUN_AT(bp->timer_interval); ++ bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL); + bp->timer.data = (unsigned long) bp; + bp->timer.function = bnx2_timer; + +@@ -7692,6 +8696,7 @@ + + for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { + struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; ++#ifdef BNX2_NEW_NAPI + int (*poll)(struct napi_struct *, int); + + if (i == 0) +@@ -7700,9 +8705,36 @@ + poll = bnx2_poll_msix; + + netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64); ++#endif ++ + bnapi->bp = bp; + } +-} ++#ifndef BNX2_NEW_NAPI ++ bp->dev->poll = bnx2_poll; ++ bp->dev->weight = 64; ++#endif ++} ++ ++#ifdef HAVE_NET_DEVICE_OPS ++static const struct net_device_ops bnx2_netdev_ops = { ++ .ndo_open = bnx2_open, ++ .ndo_start_xmit = bnx2_start_xmit, ++ .ndo_stop = bnx2_close, ++ .ndo_get_stats = bnx2_get_stats, ++ .ndo_set_rx_mode = bnx2_set_rx_mode, ++ .ndo_do_ioctl = bnx2_ioctl, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_set_mac_address = bnx2_change_mac_addr, ++ .ndo_change_mtu = bnx2_change_mtu, ++ .ndo_tx_timeout = bnx2_tx_timeout, ++#ifdef BCM_VLAN ++ .ndo_vlan_rx_register = bnx2_vlan_rx_register, ++#endif ++#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) ++ .ndo_poll_controller = poll_bnx2, ++#endif ++}; ++#endif + + static int __devinit + bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) +@@ -7718,56 +8750,100 @@ + printk(KERN_INFO "%s", version); + + /* dev zeroed in init_etherdev */ ++#if (LINUX_VERSION_CODE >= 0x20418) ++#ifndef BCM_HAVE_MULTI_QUEUE ++ dev = alloc_etherdev(sizeof(*bp)); ++#else + dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS); ++#endif ++#else ++ dev = init_etherdev(NULL, sizeof(*bp)); ++#endif + + if (!dev) + return -ENOMEM; + + rc = bnx2_init_board(pdev, dev); + if (rc < 0) { ++#if (LINUX_VERSION_CODE >= 0x20418) + free_netdev(dev); +- return rc; +- } +- ++#else ++ unregister_netdev(dev); ++ kfree(dev); ++#endif ++ return rc; ++ } ++ ++#ifndef HAVE_NET_DEVICE_OPS + dev->open = bnx2_open; + dev->hard_start_xmit = bnx2_start_xmit; + dev->stop = bnx2_close; + dev->get_stats = bnx2_get_stats; ++#ifdef HAVE_SET_RX_MODE + dev->set_rx_mode = bnx2_set_rx_mode; ++#else ++ dev->set_multicast_list = bnx2_set_rx_mode; ++#endif + dev->do_ioctl = bnx2_ioctl; + dev->set_mac_address = bnx2_change_mac_addr; + dev->change_mtu = bnx2_change_mtu; + dev->tx_timeout = bnx2_tx_timeout; +- dev->watchdog_timeo = TX_TIMEOUT; + #ifdef BCM_VLAN + dev->vlan_rx_register = bnx2_vlan_rx_register; +-#endif ++#if (LINUX_VERSION_CODE < 0x20616) ++ dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid; ++#endif ++#endif ++#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) ++ dev->poll_controller = poll_bnx2; ++#endif ++#else ++ dev->netdev_ops = &bnx2_netdev_ops; ++#endif ++ dev->watchdog_timeo = TX_TIMEOUT; + dev->ethtool_ops = &bnx2_ethtool_ops; + + bp = netdev_priv(dev); + bnx2_init_napi(bp); + +-#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) +- dev->poll_controller = poll_bnx2; +-#endif +- + pci_set_drvdata(pdev, dev); + + memcpy(dev->dev_addr, bp->mac_addr, 6); ++#ifdef ETHTOOL_GPERMADDR + memcpy(dev->perm_addr, bp->mac_addr, 6); +- bp->name = board_info[ent->driver_data].name; +- ++#endif ++ ++#ifdef NETIF_F_IPV6_CSUM + dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; + if (CHIP_NUM(bp) == CHIP_NUM_5709) + dev->features |= NETIF_F_IPV6_CSUM; +- ++#else ++ dev->features |= NETIF_F_SG; ++ if (CHIP_NUM(bp) == CHIP_NUM_5709) ++ dev->features |= NETIF_F_HW_CSUM; ++ else ++ dev->features |= NETIF_F_IP_CSUM; ++#endif + #ifdef BCM_VLAN + dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; + #endif ++#ifdef BCM_TSO + dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN; + if (CHIP_NUM(bp) == CHIP_NUM_5709) + dev->features |= NETIF_F_TSO6; +- ++#endif ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ if (CHIP_NUM(bp) == CHIP_NUM_5709) { ++ if (disable_netq == 0) { ++ VMKNETDDI_REGISTER_QUEUEOPS(dev, bnx2_netqueue_ops); ++ printk(KERN_INFO "NetQueue Ops registered\n"); ++ } else ++ printk(KERN_INFO "NetQueue Ops not registered\n"); ++ } ++#endif ++ ++#if (LINUX_VERSION_CODE >= 0x20418) + if ((rc = register_netdev(dev))) { + dev_err(&pdev->dev, "Cannot register net device\n"); + if (bp->regview) +@@ -7778,11 +8854,11 @@ + free_netdev(dev); + return rc; + } +- ++#endif + printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, " + "IRQ %d, node addr %s\n", + dev->name, +- bp->name, ++ board_info[ent->driver_data].name, + ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', + ((CHIP_ID(bp) & 0x0ff0) >> 4), + bnx2_bus_string(bp, str), +@@ -7798,14 +8874,20 @@ + struct net_device *dev = pci_get_drvdata(pdev); + struct bnx2 *bp = netdev_priv(dev); + ++#if (LINUX_VERSION_CODE >= 0x20600) + flush_scheduled_work(); ++#endif + + unregister_netdev(dev); + + if (bp->regview) + iounmap(bp->regview); + ++#if (LINUX_VERSION_CODE >= 0x20418) + free_netdev(dev); ++#else ++ kfree(dev); ++#endif + pci_release_regions(pdev); + pci_disable_device(pdev); + pci_set_drvdata(pdev, NULL); +@@ -7817,21 +8899,29 @@ + struct net_device *dev = pci_get_drvdata(pdev); + struct bnx2 *bp = netdev_priv(dev); + ++#if (LINUX_VERSION_CODE >= 0x2060b) + /* PCI register 4 needs to be saved whether netif_running() or not. + * MSI address and data need to be saved if using MSI and + * netif_running(). + */ + pci_save_state(pdev); ++#endif + if (!netif_running(dev)) + return 0; + ++#if (LINUX_VERSION_CODE >= 0x20600) + flush_scheduled_work(); ++#endif + bnx2_netif_stop(bp); + netif_device_detach(dev); + del_timer_sync(&bp->timer); + bnx2_shutdown_chip(bp); + bnx2_free_skbs(bp); ++#if (LINUX_VERSION_CODE < 0x2060b) ++ bnx2_set_power_state(bp, state); ++#else + bnx2_set_power_state(bp, pci_choose_state(pdev, state)); ++#endif + return 0; + } + +@@ -7841,7 +8931,9 @@ + struct net_device *dev = pci_get_drvdata(pdev); + struct bnx2 *bp = netdev_priv(dev); + ++#if (LINUX_VERSION_CODE >= 0x2060b) + pci_restore_state(pdev); ++#endif + if (!netif_running(dev)) + return 0; + +@@ -7852,6 +8944,8 @@ + return 0; + } + ++#if !defined(__VMKLNX__) ++#if (LINUX_VERSION_CODE >= 0x020611) + /** + * bnx2_io_error_detected - called when PCI error is detected + * @pdev: Pointer to PCI device +@@ -7938,6 +9032,9 @@ + .resume = bnx2_io_resume, + }; + ++#endif ++#endif ++ + static struct pci_driver bnx2_pci_driver = { + .name = DRV_MODULE_NAME, + .id_table = bnx2_pci_tbl, +@@ -7945,16 +9042,60 @@ + .remove = __devexit_p(bnx2_remove_one), + .suspend = bnx2_suspend, + .resume = bnx2_resume, ++#if !defined(__VMKLNX__) ++#if (LINUX_VERSION_CODE >= 0x020611) + .err_handler = &bnx2_err_handler, +-}; ++#endif ++#endif ++}; ++ ++#if defined(VMWARE_ISCSI) ++static vmk_IscsiNetDriverData iscsinet_bnx2_drv_data = { ++ .drvData = bnx2_cnic_probe, ++ .privData = NULL, ++}; ++#endif + + static int __init bnx2_init(void) + { +- return pci_register_driver(&bnx2_pci_driver); ++ int rc; ++#if defined(VMWARE_ISCSI) ++ VMK_ReturnStatus vm_err; ++#endif ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ /* sanity check the force_netq parameter */ ++ if(force_netq > 7) { ++ printk(KERN_ERR "bnx2x: please use a 'force_netq'value " ++ "between (2-7)\n"); ++ return -EINVAL; ++ } ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x020613) ++ rc = pci_module_init(&bnx2_pci_driver); ++#else ++ rc = pci_register_driver(&bnx2_pci_driver); ++#endif ++#if !defined(VMWARE_ISCSI) ++ return rc; ++#else ++ if (rc) ++ return rc; ++ vm_err = vmk_IscsiNetDriverRegister(THIS_MODULE->moduleID, &iscsinet_bnx2_drv_data); ++ if (vm_err != VMK_OK) { ++ pci_unregister_driver(&bnx2_pci_driver); ++ return vm_err; ++ } ++ return 0; ++#endif + } + + static void __exit bnx2_cleanup(void) + { ++#if defined(VMWARE_ISCSI) ++ vmk_IscsiNetDriverUnregister(THIS_MODULE->moduleID); ++#endif + pci_unregister_driver(&bnx2_pci_driver); + } + +@@ -7962,4 +9103,1110 @@ + module_exit(bnx2_cleanup); + + +- ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ ++#ifdef BNX2_DEBUG ++static u32 bnx2_read_ctx(struct bnx2 *bp, u32 offset) ++{ ++ int i; ++ ++ if (CHIP_NUM(bp) != CHIP_NUM_5709) { ++ REG_WR(bp, BNX2_CTX_DATA_ADR, offset); ++ return REG_RD(bp, BNX2_CTX_DATA); ++ } ++ ++ REG_WR(bp, BNX2_CTX_CTX_CTRL, offset | BNX2_CTX_CTX_CTRL_READ_REQ); ++ for (i = 0; i < 5; i++) { ++ udelay(5); ++ if (REG_RD(bp, BNX2_CTX_CTX_CTRL) & BNX2_CTX_CTX_CTRL_READ_REQ) ++ continue; ++ break; ++ } ++ ++ return REG_RD(bp, BNX2_CTX_CTX_DATA); ++} ++ ++static void dump_ctx(struct bnx2 *bp, u32 cid) ++{ ++ u32 addr = cid * 128; ++ int i; ++ ++ for (i = 0; i < 8; i++) { ++ u32 val, val1, val2, val3; ++ ++ val = bnx2_read_ctx(bp, addr); ++ val1 = bnx2_read_ctx(bp, addr+4); ++ val2 = bnx2_read_ctx(bp, addr+8); ++ val3 = bnx2_read_ctx(bp, addr+0xc); ++ printk(KERN_ALERT "ctx %08x: %08x %08x %08x %08x\n", ++ addr, val, val1, val2, val3); ++ addr += 0x10; ++ } ++} ++#endif ++ ++#define BNX2_NETQ_WAIT_EVENT_TIMEOUT msecs_to_jiffies(500) ++ ++#define L2_KWQ_PAGE_CNT 4 ++#define L2_KCQ_PAGE_CNT 16 ++ ++#define L2_KWQE_CNT (BCM_PAGE_SIZE / sizeof(struct l2_kwqe)) ++#define L2_KCQE_CNT (BCM_PAGE_SIZE / sizeof(struct l2_kcqe)) ++#define MAX_L2_KWQE_CNT (L2_KWQE_CNT - 1) ++#define MAX_L2_KCQE_CNT (L2_KCQE_CNT - 1) ++ ++#define MAX_L2_KWQ_IDX ((L2_KWQ_PAGE_CNT * L2_KWQE_CNT) - 1) ++#define MAX_L2_KCQ_IDX ((L2_KCQ_PAGE_CNT * L2_KCQE_CNT) - 1) ++ ++#define L2_KWQ_PG(x) (((x) & ~MAX_L2_KWQE_CNT) >> (BCM_PAGE_BITS - 5)) ++#define L2_KWQ_IDX(x) ((x) & MAX_L2_KWQE_CNT) ++ ++#define L2_KCQ_PG(x) (((x) & ~MAX_L2_KCQE_CNT) >> (BCM_PAGE_BITS - 5)) ++#define L2_KCQ_IDX(x) ((x) & MAX_L2_KCQE_CNT) ++ ++/* ++ * krnlq_context definition ++ */ ++#define L2_KRNLQ_FLAGS 0x00000000 ++#define L2_KRNLQ_SIZE 0x00000000 ++#define L2_KRNLQ_TYPE 0x00000000 ++#define KRNLQ_FLAGS_PG_SZ (0xf<<0) ++#define KRNLQ_FLAGS_PG_SZ_256 (0<<0) ++#define KRNLQ_FLAGS_PG_SZ_512 (1<<0) ++#define KRNLQ_FLAGS_PG_SZ_1K (2<<0) ++#define KRNLQ_FLAGS_PG_SZ_2K (3<<0) ++#define KRNLQ_FLAGS_PG_SZ_4K (4<<0) ++#define KRNLQ_FLAGS_PG_SZ_8K (5<<0) ++#define KRNLQ_FLAGS_PG_SZ_16K (6<<0) ++#define KRNLQ_FLAGS_PG_SZ_32K (7<<0) ++#define KRNLQ_FLAGS_PG_SZ_64K (8<<0) ++#define KRNLQ_FLAGS_PG_SZ_128K (9<<0) ++#define KRNLQ_FLAGS_PG_SZ_256K (10<<0) ++#define KRNLQ_FLAGS_PG_SZ_512K (11<<0) ++#define KRNLQ_FLAGS_PG_SZ_1M (12<<0) ++#define KRNLQ_FLAGS_PG_SZ_2M (13<<0) ++#define KRNLQ_FLAGS_QE_SELF_SEQ (1<<15) ++#define KRNLQ_SIZE_TYPE_SIZE ((((0x28 + 0x1f) & ~0x1f) / 0x20) << 16) ++#define KRNLQ_TYPE_TYPE (0xf<<28) ++#define KRNLQ_TYPE_TYPE_EMPTY (0<<28) ++#define KRNLQ_TYPE_TYPE_KRNLQ (6<<28) ++ ++#define L2_KRNLQ_HOST_QIDX 0x00000004 ++#define L2_KRNLQ_HOST_FW_QIDX 0x00000008 ++#define L2_KRNLQ_NX_QE_SELF_SEQ 0x0000000c ++#define L2_KRNLQ_QE_SELF_SEQ_MAX 0x0000000c ++#define L2_KRNLQ_NX_QE_HADDR_HI 0x00000010 ++#define L2_KRNLQ_NX_QE_HADDR_LO 0x00000014 ++#define L2_KRNLQ_PGTBL_PGIDX 0x00000018 ++#define L2_KRNLQ_NX_PG_QIDX 0x00000018 ++#define L2_KRNLQ_PGTBL_NPAGES 0x0000001c ++#define L2_KRNLQ_QIDX_INCR 0x0000001c ++#define L2_KRNLQ_PGTBL_HADDR_HI 0x00000020 ++#define L2_KRNLQ_PGTBL_HADDR_LO 0x00000024 ++ ++#define BNX2_PG_CTX_MAP 0x1a0034 ++ ++static int ++bnx2_netq_free_rx_queue_update(struct net_device *netdev, ++ vmknetddi_queueops_queueid_t qid, ++ int update); ++ ++static inline u32 ++bnx2_netqueue_kwq_avail(struct bnx2 *bp) ++{ ++ return MAX_L2_KWQ_IDX - ++ ((bp->netq_kwq_prod_idx - bp->netq_kwq_con_idx) & ++ MAX_L2_KWQ_IDX); ++} ++ ++static int ++bnx2_netqueue_submit_kwqes(struct bnx2 *bp, struct l2_kwqe *wqes) ++{ ++ struct l2_kwqe *prod_qe; ++ u16 prod, sw_prod; ++ ++ if (1 > bnx2_netqueue_kwq_avail(bp)) { ++ printk(KERN_WARNING "%s: No kwq's available\n", bp->dev->name); ++ return -EAGAIN; ++ } ++ ++ prod = bp->netq_kwq_prod_idx; ++ sw_prod = prod & MAX_L2_KWQ_IDX; ++ ++ prod_qe = &bp->netq_kwq[L2_KWQ_PG(sw_prod)][L2_KWQ_IDX(sw_prod)]; ++ memcpy(prod_qe, wqes, sizeof(struct l2_kwqe)); ++ prod++; ++ sw_prod = prod & MAX_L2_KWQ_IDX; ++ ++ bp->netq_kwq_prod_idx = prod; ++ ++ REG_WR16(bp, bp->netq_kwq_io_addr, bp->netq_kwq_prod_idx); ++ mmiowb(); ++ ++ return 0; ++} ++ ++static void ++bnx2_netqueue_free_dma(struct bnx2 *bp, struct netq_dma *dma) ++{ ++ int i; ++ ++ if (!dma->pg_arr) ++ return; ++ ++ for (i = 0; i < dma->num_pages; i++) { ++ if (dma->pg_arr[i]) { ++ pci_free_consistent(bp->pdev, BCM_PAGE_SIZE, ++ dma->pg_arr[i], dma->pg_map_arr[i]); ++ dma->pg_arr[i] = NULL; ++ } ++ } ++ if (dma->pgtbl) { ++ pci_free_consistent(bp->pdev, dma->pgtbl_size, ++ dma->pgtbl, dma->pgtbl_map); ++ dma->pgtbl = NULL; ++ } ++ kfree(dma->pg_arr); ++ dma->pg_arr = NULL; ++ dma->num_pages = 0; ++} ++ ++static void ++bnx2_netqueue_free_resc(struct bnx2 *bp) ++{ ++ bnx2_netqueue_free_dma(bp, &bp->netq_kwq_info); ++ bnx2_netqueue_free_dma(bp, &bp->netq_kcq_info); ++} ++ ++static void ++bnx2_netqueue_setup_page_tbl(struct bnx2 *bp, ++ struct netq_dma *dma) ++{ ++ int i; ++ u32 *page_table = dma->pgtbl; ++ ++ for (i = 0; i < dma->num_pages; i++) { ++ /* Each entry needs to be in big endian format. */ ++ *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32); ++ page_table++; ++ *page_table = (u32) dma->pg_map_arr[i]; ++ page_table++; ++ } ++} ++ ++static int ++bnx2_netqueue_alloc_dma(struct bnx2 *bp, struct netq_dma *dma, ++ int pages, int use_pg_tbl) ++{ ++ int i, size; ++ ++ size = pages * (sizeof(void *) + sizeof(dma_addr_t)); ++ dma->pg_arr = kzalloc(size, GFP_ATOMIC); ++ if (dma->pg_arr == NULL) { ++ printk(KERN_ERR "%s: Couldn't alloc space for dma page array\n", ++ bp->dev->name); ++ return -ENOMEM; ++ } ++ ++ dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages); ++ dma->num_pages = pages; ++ ++ for (i = 0; i < pages; i++) { ++ dma->pg_arr[i] = pci_alloc_consistent(bp->pdev, ++ BCM_PAGE_SIZE, ++ &dma->pg_map_arr[i]); ++ if (dma->pg_arr[i] == NULL) { ++ printk(KERN_ERR "%s: Couldn't alloc dma page\n", ++ bp->dev->name); ++ ++ goto error; ++ } ++ } ++ if (!use_pg_tbl) ++ return 0; ++ ++ dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) & ++ ~(BCM_PAGE_SIZE - 1); ++ dma->pgtbl = pci_alloc_consistent(bp->pdev, dma->pgtbl_size, ++ &dma->pgtbl_map); ++ if (dma->pgtbl == NULL) ++ goto error; ++ ++ bnx2_netqueue_setup_page_tbl(bp, dma); ++ ++ return 0; ++ ++error: ++ bnx2_netqueue_free_dma(bp, dma); ++ return -ENOMEM; ++} ++ ++static int ++bnx2_netqueue_alloc_resc(struct bnx2 *bp) ++{ ++ int ret; ++ ++ ret = bnx2_netqueue_alloc_dma(bp, &bp->netq_kwq_info, ++ L2_KWQ_PAGE_CNT, 1); ++ if (ret) { ++ printk(KERN_ERR "%s: Couldn't alloc space for kwq\n", ++ bp->dev->name); ++ goto error; ++ } ++ bp->netq_kwq = (struct l2_kwqe **) bp->netq_kwq_info.pg_arr; ++ ++ ret = bnx2_netqueue_alloc_dma(bp, &bp->netq_kcq_info, ++ L2_KCQ_PAGE_CNT, 1); ++ if (ret) { ++ printk(KERN_ERR "%s: Couldn't alloc space for kwq\n", ++ bp->dev->name); ++ goto error; ++ } ++ bp->netq_kcq = (struct l2_kcqe **) bp->netq_kcq_info.pg_arr; ++ ++ return 0; ++ ++error: ++ bnx2_netqueue_free_resc(bp); ++ return ret; ++} ++ ++static void ++bnx2_init_netqueue_context(struct bnx2 *bp, u32 cid) ++{ ++ u32 cid_addr; ++ int i; ++ ++ cid_addr = GET_CID_ADDR(cid); ++ ++ for (i = 0; i < CTX_SIZE; i += 4) ++ bnx2_ctx_wr(bp, cid_addr, i, 0); ++} ++ ++static int ++bnx2_netqueue_get_kcqes(struct bnx2 *bp, u16 hw_prod, u16 *sw_prod) ++{ ++ u16 i, ri, last; ++ struct l2_kcqe *kcqe; ++ int kcqe_cnt = 0, last_cnt = 0; ++ ++ i = ri = last = *sw_prod; ++ ri &= MAX_L2_KCQ_IDX; ++ ++ while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) { ++ kcqe = &bp->netq_kcq[L2_KCQ_PG(ri)][L2_KCQ_IDX(ri)]; ++ bp->netq_completed_kcq[kcqe_cnt++] = kcqe; ++ i = (i + 1); ++ ri = i & MAX_L2_KCQ_IDX; ++ if (likely(!(kcqe->flags & L2_KCQE_FLAGS_NEXT))) { ++ last_cnt = kcqe_cnt; ++ last = i; ++ } ++ } ++ ++ *sw_prod = last; ++ return last_cnt; ++} ++ ++ ++static void ++bnx2_service_netq_kcqes(struct bnx2_napi *bnapi, int num_cqes) ++{ ++ struct bnx2 *bp = bnapi->bp; ++ int i, j; ++ ++ i = 0; ++ j = 1; ++ while (num_cqes) { ++ u32 kcqe_op_flag = bp->netq_completed_kcq[i]->opcode; ++ u32 kcqe_layer = bp->netq_completed_kcq[i]->flags & ++ L2_KCQE_FLAGS_LAYER_MASK; ++ ++ printk(KERN_INFO "kcwe service [reserved: 0x%x, status: 0x%x, qid: 0x%x, qe_self_seq: 0x%x, opcode: 0x%x, flags: 0x%x]\n", ++ bp->netq_completed_kcq[i]->reserved, ++ bp->netq_completed_kcq[i]->status, ++ bp->netq_completed_kcq[i]->qid, ++ bp->netq_completed_kcq[i]->qe_self_seq, ++ bp->netq_completed_kcq[i]->opcode, ++ bp->netq_completed_kcq[i]->flags); ++ ++ while (j < num_cqes) { ++ u32 next_op = bp->netq_completed_kcq[i + j]->opcode; ++ ++ if ((next_op & L2_KCQE_FLAGS_LAYER_MASK) != kcqe_layer) ++ break; ++ j++; ++ } ++ ++ if (kcqe_layer != L2_KCQE_FLAGS_LAYER_MASK_L2) { ++ printk(KERN_ERR PFX "%s: Unknown type of KCQE(0x%x)\n", ++ bp->dev->name, kcqe_op_flag); ++ goto end; ++ } ++ ++ bp->netq_flags = kcqe_op_flag; ++ wake_up(&bp->netq_wait); ++ ++end: ++ num_cqes -= j; ++ i += j; ++ j = 1; ++ } ++ ++ ++ return; ++} ++ ++static void ++bnx2_netqueue_service_bnx2_msix(struct bnx2_napi *bnapi) ++{ ++ struct bnx2 *bp = bnapi->bp; ++ struct status_block *status_blk = bp->bnx2_napi[0].status_blk.msi; ++ u32 status_idx = status_blk->status_idx; ++ u16 hw_prod, sw_prod; ++ int kcqe_cnt; ++ ++ bp->netq_kwq_con_idx = status_blk->status_cmd_consumer_index; ++ ++ hw_prod = status_blk->status_completion_producer_index; ++ sw_prod = bp->netq_kcq_prod_idx; ++ ++ /* Ensure that there is a NetQ kcq avaliable */ ++ if (sw_prod == hw_prod) ++ return; ++ ++ while (sw_prod != hw_prod) { ++ kcqe_cnt = bnx2_netqueue_get_kcqes(bp, hw_prod, &sw_prod); ++ if (kcqe_cnt == 0) ++ goto done; ++ ++ bnx2_service_netq_kcqes(bnapi, kcqe_cnt); ++ ++ /* Tell compiler that status_blk fields can change. */ ++ barrier(); ++ if (status_idx != status_blk->status_idx) { ++ status_idx = status_blk->status_idx; ++ bp->netq_kwq_con_idx = status_blk->status_cmd_consumer_index; ++ hw_prod = status_blk->status_completion_producer_index; ++ } else ++ break; ++ } ++ ++done: ++ REG_WR16(bp, bp->netq_kcq_io_addr, sw_prod); ++ ++ bp->netq_kcq_prod_idx = sw_prod; ++ bp->netq_last_status_idx = status_idx; ++} ++ ++static void ++bnx2_stop_netqueue_hw(struct bnx2 *bp) ++{ ++ u32 val; ++ ++ /* Disable the CP and COM doorbells. These two processors polls the ++ * doorbell for a non zero value before running. This must be done ++ * after setting up the kernel queue contexts. This is for ++ * KQW/KCQ #1. */ ++ ++ val = bnx2_reg_rd_ind(bp, BNX2_CP_SCRATCH + 0x20); ++ val &= ~KWQ1_READY; ++ bnx2_reg_wr_ind(bp, BNX2_CP_SCRATCH + 0x20, val); ++ ++ val = bnx2_reg_rd_ind(bp, BNX2_COM_SCRATCH + 0x20); ++ val &= ~KCQ1_READY; ++ bnx2_reg_wr_ind(bp, BNX2_COM_SCRATCH + 0x20, val); ++ ++ /* Return back all the used resources */ ++ bnx2_netqueue_free_resc(bp); ++} ++ ++static int ++bnx2_start_netqueue_hw(struct bnx2 *bp) ++{ ++ u32 val; ++ int err; ++ ++ /* Initialize the bnx2 netqueue structures */ ++ init_waitqueue_head(&bp->netq_wait); ++ ++ err = bnx2_netqueue_alloc_resc(bp); ++ if (err != 0) { ++ printk(KERN_ERR "%s: Couldn't allocate netq resources\n", ++ bp->dev->name); ++ return err; ++ } ++ ++ val = REG_RD(bp, BNX2_MQ_CONFIG); ++ val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; ++ if (BCM_PAGE_BITS > 12) ++ val |= (12 - 8) << 4; ++ else ++ val |= (BCM_PAGE_BITS - 8) << 4; ++ ++ REG_WR(bp, BNX2_MQ_CONFIG, val); ++ ++ REG_WR(bp, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8); ++ REG_WR(bp, BNX2_HC_COM_TICKS, (64 << 16) | 220); ++ REG_WR(bp, BNX2_HC_CMD_TICKS, (64 << 16) | 220); ++ ++ bnx2_init_netqueue_context(bp, NETQUEUE_KWQ_CID); ++ bnx2_init_netqueue_context(bp, NETQUEUE_KCQ_CID); ++ ++ bp->netq_kwq_cid_addr = GET_CID_ADDR(NETQUEUE_KWQ_CID); ++ bp->netq_kwq_io_addr = MB_GET_CID_ADDR(NETQUEUE_KWQ_CID) + ++ L2_KRNLQ_HOST_QIDX; ++ ++ bp->netq_kwq_prod_idx = 0; ++ bp->netq_kwq_con_idx = 0; ++ ++ /* Initialize the kernel work queue context. */ ++ val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE | ++ (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ; ++ bnx2_ctx_wr(bp, bp->netq_kwq_cid_addr, L2_KRNLQ_TYPE, val); ++ ++ val = (BCM_PAGE_SIZE / sizeof(struct l2_kwqe) - 1) << 16; ++ bnx2_ctx_wr(bp, bp->netq_kwq_cid_addr, L2_KRNLQ_QE_SELF_SEQ_MAX, val); ++ ++ val = ((BCM_PAGE_SIZE / sizeof(struct l2_kwqe)) << 16) | L2_KWQ_PAGE_CNT; ++ bnx2_ctx_wr(bp, bp->netq_kwq_cid_addr, L2_KRNLQ_PGTBL_NPAGES, val); ++ ++ val = (u32) ((u64) bp->netq_kwq_info.pgtbl_map >> 32); ++ bnx2_ctx_wr(bp, bp->netq_kwq_cid_addr, L2_KRNLQ_PGTBL_HADDR_HI, val); ++ ++ val = (u32) bp->netq_kwq_info.pgtbl_map; ++ bnx2_ctx_wr(bp, bp->netq_kwq_cid_addr, L2_KRNLQ_PGTBL_HADDR_LO, val); ++ ++ bp->netq_kcq_cid_addr = GET_CID_ADDR(NETQUEUE_KCQ_CID); ++ bp->netq_kcq_io_addr = MB_GET_CID_ADDR(NETQUEUE_KCQ_CID) + ++ L2_KRNLQ_HOST_QIDX; ++ bp->netq_kcq_prod_idx = 0; ++ ++ /* Initialize the kernel complete queue context. */ ++ val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE | ++ (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ; ++ bnx2_ctx_wr(bp, bp->netq_kcq_cid_addr, L2_KRNLQ_TYPE, val); ++ ++ val = (BCM_PAGE_SIZE / sizeof(struct l2_kcqe) - 1) << 16; ++ bnx2_ctx_wr(bp, bp->netq_kcq_cid_addr, L2_KRNLQ_QE_SELF_SEQ_MAX, val); ++ ++ val = ((BCM_PAGE_SIZE / sizeof(struct l2_kcqe)) << 16)|L2_KCQ_PAGE_CNT; ++ bnx2_ctx_wr(bp, bp->netq_kcq_cid_addr, L2_KRNLQ_PGTBL_NPAGES, val); ++ ++ val = (u32) ((u64) bp->netq_kcq_info.pgtbl_map >> 32); ++ bnx2_ctx_wr(bp, bp->netq_kcq_cid_addr, L2_KRNLQ_PGTBL_HADDR_HI, val); ++ ++ val = (u32) bp->netq_kcq_info.pgtbl_map; ++ bnx2_ctx_wr(bp, bp->netq_kcq_cid_addr, L2_KRNLQ_PGTBL_HADDR_LO, val); ++ ++ /* Enable Commnad Scheduler notification when we write to the ++ * host producer index of the kernel contexts. */ ++ REG_WR(bp, BNX2_MQ_KNL_CMD_MASK1, 2); ++ ++ /* Enable Command Scheduler notification when we write to either ++ * the Send Queue or Receive Queue producer indexes of the kernel ++ * bypass contexts. */ ++ REG_WR(bp, BNX2_MQ_KNL_BYP_CMD_MASK1, 7); ++ REG_WR(bp, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7); ++ ++ /* Notify COM when the driver post an application buffer. */ ++ REG_WR(bp, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000); ++ ++ /* Set the CP and COM doorbells. These two processors polls the ++ * doorbell for a non zero value before running. This must be done ++ * after setting up the kernel queue contexts. This is for ++ * KQW/KCQ 1. */ ++ bnx2_reg_wr_ind(bp, BNX2_CP_SCRATCH + 0x20, KWQ1_READY); ++ bnx2_reg_wr_ind(bp, BNX2_COM_SCRATCH + 0x20, KCQ1_READY); ++ ++ mmiowb(); ++ ++ printk(KERN_INFO "%s: NetQueue hardware support is enabled\n", ++ bp->dev->name); ++ ++ return 0; ++} ++ ++ ++ ++static int ++bnx2_netq_get_netqueue_features(vmknetddi_queueop_get_features_args_t *args) ++{ ++ args->features = VMKNETDDI_QUEUEOPS_FEATURE_NONE; ++ args->features |= VMKNETDDI_QUEUEOPS_FEATURE_RXQUEUES; ++ args->features |= VMKNETDDI_QUEUEOPS_FEATURE_TXQUEUES; ++ return VMKNETDDI_QUEUEOPS_OK; ++} ++ ++static int ++bnx2_netq_get_queue_count(vmknetddi_queueop_get_queue_count_args_t *args) ++{ ++ struct bnx2 *bp = netdev_priv(args->netdev); ++ ++ /* workaround for packets duplicated */ ++ if (bp->num_tx_rings + bp->num_rx_rings > 1) ++ bp->netq_enabled = 1; ++ ++ if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_RX) { ++ args->count = max_t(u16, bp->num_rx_rings - 1, 0); ++ ++ printk(KERN_INFO "%s: Using %d RX NetQ rings\n", ++ args->netdev->name, args->count); ++ ++ return VMKNETDDI_QUEUEOPS_OK; ++ } else if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_TX) { ++ args->count = max_t(u16, bp->num_tx_rings - 1, 0); ++ ++ printk(KERN_INFO "%s: Using %d TX NetQ rings\n", ++ args->netdev->name, args->count); ++ ++ return VMKNETDDI_QUEUEOPS_OK; ++ } else { ++ printk(KERN_ERR "%s: Counting queue: invalid queue type\n", ++ bp->dev->name); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++} ++ ++static int ++bnx2_netq_get_filter_count(vmknetddi_queueop_get_filter_count_args_t *args) ++{ ++ /* Only support 1 Mac filter per queue */ ++ args->count = 1; ++ return VMKNETDDI_QUEUEOPS_OK; ++} ++ ++static int ++bnx2_netq_alloc_rx_queue(struct net_device *netdev, ++ vmknetddi_queueops_queueid_t *p_qid, ++ struct napi_struct **napi_p) ++{ ++ int i; ++ struct bnx2 *bp = netdev_priv(netdev); ++ ++ /* We need to count the default ring as part of the number of RX rings ++ avaliable */ ++ if (bp->n_rx_queues_allocated >= (bp->num_rx_rings - 1)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ for_each_nondefault_rx_queue(bp, i) { ++ struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; ++ if (!bnapi->rx_queue_allocated) { ++ int rc; ++ struct l2_kwqe_vm_alloc_rx_queue kwqe_alloc_rx; ++ ++ /* Ensure that the NetQueue is freed */ ++ rc = bnx2_netq_free_rx_queue_update(netdev, VMKNETDDI_QUEUEOPS_MK_RX_QUEUEID(i), 1); ++ if(rc == VMKNETDDI_QUEUEOPS_ERR) { ++ printk(KERN_ERR "%s: Couldn't clean/free RX " ++ "queue during RX alloc\n", ++ bp->dev->name); ++ ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++ /* Prepare the kwqe to be passed to the firmware */ ++ memset(&kwqe_alloc_rx, 0, sizeof(kwqe_alloc_rx)); ++ ++ kwqe_alloc_rx.kwqe_flags = KWQE_FLAGS_LAYER_MASK_L2; ++ kwqe_alloc_rx.kwqe_opcode = L2_KWQE_OPCODE_VALUE_VM_ALLOC_RX_QUEUE; ++ kwqe_alloc_rx.queue_type = L2_NET_QUEUE; ++ kwqe_alloc_rx.qid = i - 1; ++ ++ rc = bnx2_netqueue_submit_kwqes(bp, ++ (struct l2_kwqe *)&kwqe_alloc_rx); ++ if (rc != 0) { ++ printk(KERN_ERR "%s: Couldn't submit alloc rx kwqe\n", ++ bp->dev->name); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++ bp->netq_flags = 0; ++ rc = wait_event_timeout(bp->netq_wait, ++ (bp->netq_flags & ++ L2_KCQE_OPCODE_VALUE_VM_ALLOC_RX_QUEUE), ++ BNX2_NETQ_WAIT_EVENT_TIMEOUT); ++ ++ if (rc != 0) { ++ bnapi->rx_queue_allocated = TRUE; ++ bp->n_rx_queues_allocated++; ++ *p_qid = VMKNETDDI_QUEUEOPS_MK_RX_QUEUEID(i); ++ *napi_p = &bnapi->napi; ++ ++ printk(KERN_INFO "%s: RX NetQ allocated on %d\n", ++ bp->dev->name, kwqe_alloc_rx.qid); ++ return VMKNETDDI_QUEUEOPS_OK; ++ } else { ++ printk(KERN_INFO "%s: Timeout RX NetQ allocate on %d\n", ++ bp->dev->name, kwqe_alloc_rx.qid); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ } ++ } ++ printk(KERN_ERR "%s: No free rx queues found!\n", bp->dev->name); ++ return VMKNETDDI_QUEUEOPS_ERR; ++} ++ ++static int ++bnx2_netq_alloc_tx_queue(struct net_device *netdev, ++ vmknetddi_queueops_queueid_t *p_qid, ++ u16 *queue_mapping) ++{ ++ int i; ++ struct bnx2 *bp = netdev_priv(netdev); ++ ++ if (bp->n_tx_queues_allocated >= (bp->num_tx_rings - 1)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ for_each_nondefault_tx_queue(bp, i) { ++ struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; ++ if (!bnapi->tx_queue_allocated) { ++ ++ bnapi->tx_queue_allocated = TRUE; ++ bp->n_tx_queues_allocated++; ++ *p_qid = VMKNETDDI_QUEUEOPS_MK_TX_QUEUEID(i); ++ *queue_mapping = i; ++ ++ printk(KERN_INFO "%s: TX NetQ allocated on %d\n", ++ bp->dev->name, i); ++ return VMKNETDDI_QUEUEOPS_OK; ++ } ++ } ++ ++ printk(KERN_ERR "%s: no free tx queues found!\n", ++ bp->dev->name); ++ return VMKNETDDI_QUEUEOPS_ERR; ++} ++ ++static int ++bnx2_netq_alloc_queue(vmknetddi_queueop_alloc_queue_args_t *args) ++{ ++ struct net_device *netdev = args->netdev; ++ struct bnx2 *bp = netdev_priv(netdev); ++ ++ if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_TX) { ++ return bnx2_netq_alloc_tx_queue(args->netdev, &args->queueid, ++ &args->queue_mapping); ++ } else if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_RX) { ++ return bnx2_netq_alloc_rx_queue(args->netdev, &args->queueid, ++ &args->napi); ++ } else { ++ printk(KERN_ERR "%s: Trying to alloc invalid queue type: %x\n", ++ bp->dev->name, args->type); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++} ++ ++static int ++bnx2_netq_free_tx_queue(struct net_device *netdev, ++ vmknetddi_queueops_queueid_t qid) ++{ ++ struct bnx2 *bp = netdev_priv(netdev); ++ struct bnx2_napi *bnapi; ++ struct bnx2_tx_ring_info *txr; ++ int rc; ++ ++ u16 index = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(qid); ++ if (index > bp->num_tx_rings) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ bnapi = &bp->bnx2_napi[index]; ++ if (bnapi->tx_queue_allocated != TRUE) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ txr = &bnapi->tx_ring; ++ if (txr->tx_cons == txr->tx_prod) ++ goto free_tx_ring; ++ ++ /* Wait for the TX to flush all packets */ ++ bnapi->netq_flags |= BNX2_NETQ_FREE_TX_QUEUE_STATE; ++ rc = wait_event_timeout(bp->netq_wait, ++ (bp->netq_flags & ++ L2_KCQE_OPCODE_VALUE_VM_FREE_TX_QUEUE), ++ BNX2_NETQ_WAIT_EVENT_TIMEOUT); ++ bnapi->netq_flags &= ~BNX2_NETQ_FREE_TX_QUEUE_STATE; ++ ++ if (rc == 0) { ++ printk(KERN_INFO "%s: Timeout submiting free NetQ TX Queue: %x\n", ++ bp->dev->name, index); ++ ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++free_tx_ring: ++ bnapi->tx_queue_allocated = FALSE; ++ bp->n_tx_queues_allocated--; ++ ++ printk(KERN_INFO "%s: Free NetQ TX Queue: %x\n", ++ bp->dev->name, index); ++ ++ return VMKNETDDI_QUEUEOPS_OK; ++} ++ ++static int ++bnx2_netq_free_rx_queue_update(struct net_device *netdev, ++ vmknetddi_queueops_queueid_t qid, ++ int force) ++{ ++ int rc; ++ struct bnx2 *bp = netdev_priv(netdev); ++ struct bnx2_napi *bnapi; ++ struct l2_kwqe_vm_free_rx_queue kwqe_free_rx; ++ ++ u16 index = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(qid); ++ if (index > bp->num_rx_rings) { ++ printk(KERN_INFO "%s: Error Free NetQ RX Queue: " ++ "index(%d) > bp->num_rx_rings(%d)\n", ++ bp->dev->name, index, bp->num_rx_rings); ++ ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++ bnapi = &bp->bnx2_napi[index]; ++ if ((bnapi->rx_queue_allocated != TRUE) && (force == 0)) { ++ printk(KERN_INFO "%s: Error Free NetQ RX Queue %d " ++ "already allocated\n", ++ bp->dev->name, index); ++ ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++ memset(&kwqe_free_rx, 0, sizeof(kwqe_free_rx)); ++ ++ kwqe_free_rx.flags = KWQE_FLAGS_LAYER_MASK_L2; ++ kwqe_free_rx.opcode = L2_KWQE_OPCODE_VALUE_VM_FREE_RX_QUEUE; ++ kwqe_free_rx.qid = index; ++ ++ rc = bnx2_netqueue_submit_kwqes(bp, ++ (struct l2_kwqe *) &kwqe_free_rx); ++ if (rc != 0) { ++ printk(KERN_ERR "%s: Couldn't submit free rx kwqe\n", ++ bp->dev->name); ++ ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++ bp->netq_flags = 0; ++ rc = wait_event_timeout(bp->netq_wait, ++ (bp->netq_flags & ++ L2_KCQE_OPCODE_VALUE_VM_FREE_RX_QUEUE), ++ BNX2_NETQ_WAIT_EVENT_TIMEOUT); ++ if (rc != 0) { ++ bnapi->rx_queue_allocated = FALSE; ++ ++ if(force != 1) ++ bp->n_rx_queues_allocated--; ++ ++ printk(KERN_INFO "%s: Free NetQ RX Queue (forced: %d): %x\n", ++ bp->dev->name, force, index); ++ ++ return VMKNETDDI_QUEUEOPS_OK; ++ } else { ++ printk(KERN_INFO "%s: Timeout free NetQ RX Queue " ++ "(force: %d): %x\n", ++ bp->dev->name, force, index); ++ ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++} ++ ++static int ++bnx2_netq_free_rx_queue(struct net_device *netdev, ++ vmknetddi_queueops_queueid_t qid) ++{ ++ return bnx2_netq_free_rx_queue_update(netdev, qid, 0); ++} ++ ++static int ++bnx2_netq_free_queue(vmknetddi_queueop_free_queue_args_t *args) ++{ ++ if (VMKNETDDI_QUEUEOPS_IS_TX_QUEUEID(args->queueid)) { ++ return bnx2_netq_free_tx_queue(args->netdev, args->queueid); ++ } else if (VMKNETDDI_QUEUEOPS_IS_RX_QUEUEID(args->queueid)) { ++ return bnx2_netq_free_rx_queue(args->netdev, args->queueid); ++ } else { ++ printk(KERN_ERR "%s: free netq: invalid queue type\n", ++ args->netdev->name); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++} ++ ++static int ++bnx2_netq_get_queue_vector(vmknetddi_queueop_get_queue_vector_args_t *args) ++{ ++ int qid; ++ struct bnx2 *bp = netdev_priv(args->netdev); ++ qid = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(args->queueid); ++ if (qid > bp->num_rx_rings) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++#ifdef CONFIG_PCI_MSI ++ args->vector = bp->bnx2_napi[qid].int_num; ++#endif ++ return VMKNETDDI_QUEUEOPS_OK; ++} ++ ++static int ++bnx2_netq_get_default_queue(vmknetddi_queueop_get_default_queue_args_t *args) ++{ ++ struct bnx2 *bp = netdev_priv(args->netdev); ++ ++ if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_RX) { ++ args->queueid = VMKNETDDI_QUEUEOPS_MK_RX_QUEUEID(0); ++ args->napi = &bp->bnx2_napi[0].napi; ++ return VMKNETDDI_QUEUEOPS_OK; ++ } else if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_TX) { ++ args->queueid = VMKNETDDI_QUEUEOPS_MK_TX_QUEUEID(0); ++ args->queue_mapping = 0; ++ return VMKNETDDI_QUEUEOPS_OK; ++ } else ++ return VMKNETDDI_QUEUEOPS_ERR; ++} ++ ++static int ++bnx2_netq_remove_rx_filter(vmknetddi_queueop_remove_rx_filter_args_t *args) ++{ ++ struct bnx2 *bp = netdev_priv(args->netdev); ++ u16 qid = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(args->queueid); ++ u16 fw_qid = qid - 1; ++ u16 fid = VMKNETDDI_QUEUEOPS_FILTERID_VAL(args->filterid); ++ struct bnx2_napi *bnapi; ++ struct l2_kwqe_vm_remove_rx_filter kwqe_remove_rx_filter; ++ int rc; ++ ++ bnapi = &bp->bnx2_napi[qid]; ++ ++ if (!VMKNETDDI_QUEUEOPS_IS_RX_QUEUEID(args->queueid)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ if (qid > bp->num_rx_rings) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ /* Only support one Mac filter per queue */ ++ if (fid != 0 || bnapi->rx_queue_active == 0) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ memset(&kwqe_remove_rx_filter, 0, sizeof(kwqe_remove_rx_filter)); ++ ++ kwqe_remove_rx_filter.flags = KWQE_FLAGS_LAYER_MASK_L2; ++ kwqe_remove_rx_filter.opcode = L2_KWQE_OPCODE_VALUE_VM_REMOVE_RX_FILTER; ++ kwqe_remove_rx_filter.filter_type = L2_VM_FILTER_MAC; ++ kwqe_remove_rx_filter.qid = fw_qid; ++ ++ rc = bnx2_netqueue_submit_kwqes(bp, ++ (struct l2_kwqe *) &kwqe_remove_rx_filter); ++ if (rc != 0) { ++ printk(KERN_ERR "Couldn't submit rx filter kwqe\n"); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++ bp->netq_flags = 0; ++ rc = wait_event_timeout(bp->netq_wait, ++ (bp->netq_flags & ++ L2_KCQE_OPCODE_VALUE_VM_REMOVE_RX_FILTER), ++ BNX2_NETQ_WAIT_EVENT_TIMEOUT); ++ if (rc != 0) { ++ printk(KERN_INFO "%s: NetQ remove RX filter: %d\n", ++ bp->dev->name, qid); ++ ++ return VMKNETDDI_QUEUEOPS_OK; ++ } else { ++ printk(KERN_INFO "%s: Timeout NetQ remove RX filter: %d\n", ++ bp->dev->name, qid); ++ ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++} ++ ++static int ++bnx2_netq_apply_rx_filter(vmknetddi_queueop_apply_rx_filter_args_t *args) ++{ ++ u8 *macaddr; ++ struct bnx2_napi *bnapi; ++ struct bnx2 *bp = netdev_priv(args->netdev); ++ vmknetddi_queueops_filter_class_t class; ++ u16 queueid = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(args->queueid); ++ u16 fw_queueid = queueid - 1; ++ struct l2_kwqe_vm_set_rx_filter kwqe_set_rx_filter; ++ int rc; ++ DECLARE_MAC_BUF(mac); ++ u16 vlan_id; ++ ++ if (!VMKNETDDI_QUEUEOPS_IS_RX_QUEUEID(args->queueid)) { ++ printk(KERN_ERR "%s: invalid NetQ RX ID: %x\n", ++ args->netdev->name, args->queueid); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++ class = vmknetddi_queueops_get_filter_class(&args->filter); ++ if ((class != VMKNETDDI_QUEUEOPS_FILTER_MACADDR) && ++ (class != VMKNETDDI_QUEUEOPS_FILTER_VLANMACADDR)) { ++ printk(KERN_ERR "%s: recieved invalid RX NetQ filter: %x\n", ++ args->netdev->name, class); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++ if (queueid > bp->num_rx_rings) { ++ printk(KERN_ERR "%s: applying filter with invalid RX NetQ %d ID\n", ++ args->netdev->name, queueid); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++ bnapi = &bp->bnx2_napi[queueid]; ++ ++ if (bnapi->rx_queue_active || !bnapi->rx_queue_allocated) { ++ printk(KERN_ERR "%s: RX NetQ %d already active\n", ++ args->netdev->name, queueid); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++ macaddr = (void *)vmknetddi_queueops_get_filter_macaddr(&args->filter); ++ memcpy(bnapi->mac_filter_addr, macaddr, ETH_ALEN); ++ vlan_id = vmknetddi_queueops_get_filter_vlanid(&args->filter); ++ ++ bnx2_set_mac_addr(bp, bnapi->mac_filter_addr, ++ fw_queueid + QID_TO_PM_OFFSET); ++ ++ /* Apply RX filter code here */ ++ args->filterid = VMKNETDDI_QUEUEOPS_MK_FILTERID(queueid); ++ ++ memset(&kwqe_set_rx_filter, 0, sizeof(&kwqe_set_rx_filter)); ++ ++ kwqe_set_rx_filter.flags = KWQE_FLAGS_LAYER_MASK_L2; ++ kwqe_set_rx_filter.opcode = L2_KWQE_OPCODE_VALUE_VM_SET_RX_FILTER; ++ ++#if defined(__LITTLE_ENDIAN) ++ memcpy(&kwqe_set_rx_filter.mac_addr_hi, bnapi->mac_filter_addr, 2); ++ memcpy(&kwqe_set_rx_filter.mac_addr_lo, bnapi->mac_filter_addr + 2, 4); ++#else ++ memcpy(&kwqe_set_rx_filter.mac_addr, bnapi->mac_filter_addr, 6); ++#endif ++ ++ if (class == VMKNETDDI_QUEUEOPS_FILTER_MACADDR) { ++ kwqe_set_rx_filter.filter_type = L2_VM_FILTER_MAC; ++ } else { ++ kwqe_set_rx_filter.filter_type = L2_VM_FILTER_MAC_VLAN; ++ kwqe_set_rx_filter.vlan = vlan_id; ++ } ++ kwqe_set_rx_filter.qid = fw_queueid; ++ ++ rc = bnx2_netqueue_submit_kwqes(bp, ++ (struct l2_kwqe *) &kwqe_set_rx_filter); ++ if (rc != 0) { ++ printk(KERN_ERR "Couldn't submit rx filter kwqe\n"); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++ bp->netq_flags = 0; ++ rc = wait_event_timeout(bp->netq_wait, ++ (bp->netq_flags & ++ L2_KCQE_OPCODE_VALUE_VM_SET_RX_FILTER), ++ BNX2_NETQ_WAIT_EVENT_TIMEOUT); ++ ++ if (rc != 0) { ++ printk(KERN_INFO "%s: NetQ set RX Filter: %d [%s %d]\n", ++ bp->dev->name, ++ queueid, print_mac(mac, macaddr), vlan_id); ++ ++ return VMKNETDDI_QUEUEOPS_OK; ++ } else { ++ printk(KERN_INFO "%s: Timeout submitting NetQ set RX Filter: %d [%s]\n", ++ bp->dev->name, queueid, print_mac(mac, macaddr)); ++ ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++} ++ ++static int ++bnx2_netq_get_queue_stats(vmknetddi_queueop_get_stats_args_t *args) ++{ ++ u16 queueid = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(args->queueid); ++ struct bnx2_napi *bnapi; ++ struct bnx2 *bp = netdev_priv(args->netdev); ++ ++ bnapi = &bp->bnx2_napi[queueid]; ++ ++ args->stats = &bnapi->stats; ++ ++ return VMKNETDDI_QUEUEOPS_OK; ++} ++ ++static int ++bnx2_netq_get_netqueue_version(vmknetddi_queueop_get_version_args_t *args) ++{ ++ return vmknetddi_queueops_version(args); ++} ++ ++static int ++bnx2_netqueue_ops(vmknetddi_queueops_op_t op, void *args) ++{ ++ switch (op) { ++ case VMKNETDDI_QUEUEOPS_OP_GET_VERSION: ++ return bnx2_netq_get_netqueue_version( ++ (vmknetddi_queueop_get_version_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_GET_FEATURES: ++ return bnx2_netq_get_netqueue_features( ++ (vmknetddi_queueop_get_features_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_GET_QUEUE_COUNT: ++ return bnx2_netq_get_queue_count( ++ (vmknetddi_queueop_get_queue_count_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_GET_FILTER_COUNT: ++ return bnx2_netq_get_filter_count( ++ (vmknetddi_queueop_get_filter_count_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_ALLOC_QUEUE: ++ return bnx2_netq_alloc_queue( ++ (vmknetddi_queueop_alloc_queue_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_FREE_QUEUE: ++ return bnx2_netq_free_queue( ++ (vmknetddi_queueop_free_queue_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_GET_QUEUE_VECTOR: ++ return bnx2_netq_get_queue_vector( ++ (vmknetddi_queueop_get_queue_vector_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_GET_DEFAULT_QUEUE: ++ return bnx2_netq_get_default_queue( ++ (vmknetddi_queueop_get_default_queue_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_APPLY_RX_FILTER: ++ return bnx2_netq_apply_rx_filter( ++ (vmknetddi_queueop_apply_rx_filter_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_REMOVE_RX_FILTER: ++ return bnx2_netq_remove_rx_filter( ++ (vmknetddi_queueop_remove_rx_filter_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_GET_STATS: ++ return bnx2_netq_get_queue_stats( ++ (vmknetddi_queueop_get_stats_args_t *)args); ++ break; ++ ++ /* Unsupported for now */ ++ case VMKNETDDI_QUEUEOPS_OP_SET_TX_PRIORITY: ++ return VMKNETDDI_QUEUEOPS_ERR; ++ break; ++ ++ default: ++ printk(KERN_WARNING "Unhandled NETQUEUE OP %d\n", op); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++ return VMKNETDDI_QUEUEOPS_ERR; ++} ++#endif /* defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) */ ++ +diff -r 5f108bc568be drivers/net/bnx2.h +--- a/drivers/net/bnx2.h Tue Sep 01 13:49:15 2009 +0100 ++++ b/drivers/net/bnx2.h Tue Sep 01 13:50:08 2009 +0100 +@@ -12,6 +12,890 @@ + + #ifndef BNX2_H + #define BNX2_H ++ ++#if (LINUX_VERSION_CODE >= 0x020610) ++#define BCM_CNIC 1 ++#endif ++ ++#if defined(__VMKLNX__) && (VMWARE_ESX_DDK_VERSION >= 41000) ++#define VMWARE_ISCSI ++#endif ++ ++#if defined(__VMKLNX__) ++#define HAVE_LE32 1 ++#define HAVE_IP_HDR 1 ++#define NEW_SKB 1 ++#define BNX2_NEW_NAPI 1 ++#endif ++ ++#ifndef ADVERTISE_1000XFULL ++#define ADVERTISE_1000XFULL 0x0020 ++#define ADVERTISE_1000XHALF 0x0040 ++#define ADVERTISE_1000XPAUSE 0x0080 ++#define ADVERTISE_1000XPSE_ASYM 0x0100 ++#endif ++ ++#ifndef ADVERTISE_PAUSE_CAP ++#define ADVERTISE_PAUSE_CAP 0x0400 ++#define ADVERTISE_PAUSE_ASYM 0x0800 ++#endif ++ ++#ifndef MII_CTRL1000 ++#define MII_CTRL1000 0x9 ++#define MII_STAT1000 0xa ++#endif ++ ++#ifndef BMCR_SPEED1000 ++#define BMCR_SPEED1000 0x0040 ++#endif ++ ++#ifndef ADVERTISE_1000FULL ++#define ADVERTISE_1000FULL 0x0200 ++#define ADVERTISE_1000HALF 0x0100 ++#endif ++ ++#ifndef SPEED_2500 ++#define SPEED_2500 2500 ++#endif ++ ++#ifndef SUPPORTED_2500baseX_Full ++#define SUPPORTED_2500baseX_Full (1 << 15) ++#define ADVERTISED_2500baseX_Full (1 << 15) ++#endif ++ ++#ifndef ETH_FCS_LEN ++#define ETH_FCS_LEN 4 ++#endif ++ ++#ifndef PCI_DEVICE_ID_NX2_5706 ++#define PCI_DEVICE_ID_NX2_5706 0x164a ++#define PCI_DEVICE_ID_NX2_5706S 0x16aa ++#endif ++ ++#ifndef PCI_DEVICE_ID_NX2_5708 ++#define PCI_DEVICE_ID_NX2_5708 0x164c ++#define PCI_DEVICE_ID_NX2_5708S 0x16ac ++#endif ++ ++#ifndef PCI_DEVICE_ID_NX2_5709 ++#define PCI_DEVICE_ID_NX2_5709 0x1639 ++#endif ++ ++#ifndef PCI_DEVICE_ID_NX2_5709S ++#define PCI_DEVICE_ID_NX2_5709S 0x163a ++#endif ++ ++#ifndef PCI_DEVICE_ID_AMD_8132_BRIDGE ++#define PCI_DEVICE_ID_AMD_8132_BRIDGE 0x7458 ++#endif ++ ++#ifndef IRQ_RETVAL ++typedef void irqreturn_t; ++#define IRQ_RETVAL(x) ++#define IRQ_HANDLED ++#define IRQ_NONE ++#endif ++ ++#ifndef IRQF_SHARED ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#ifndef NETDEV_TX_OK ++#define NETDEV_TX_OK 0 ++#endif ++ ++#ifndef NETDEV_TX_BUSY ++#define NETDEV_TX_BUSY 1 ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x020547) ++#define pci_set_consistent_dma_mask(pdev, mask) (0) ++#endif ++ ++#ifndef PCI_CAP_ID_EXP ++#define PCI_CAP_ID_EXP 0x10 ++#endif ++ ++#ifndef DEFINE_PCI_DEVICE_TABLE ++#define DEFINE_PCI_DEVICE_TABLE(_table) \ ++ struct pci_device_id _table[] ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x020604) ++#define MODULE_VERSION(version) ++#endif ++ ++#ifndef SET_MODULE_OWNER ++#define SET_MODULE_OWNER(dev) do { } while (0) ++#endif ++ ++#ifndef CHECKSUM_PARTIAL ++#define CHECKSUM_PARTIAL CHECKSUM_HW ++#endif ++ ++#ifndef DMA_64BIT_MASK ++#define DMA_64BIT_MASK ((u64) 0xffffffffffffffffULL) ++#define DMA_32BIT_MASK ((u64) 0x00000000ffffffffULL) ++#endif ++ ++#ifndef DMA_40BIT_MASK ++#define DMA_40BIT_MASK ((u64) 0x000000ffffffffffULL) ++#endif ++ ++#ifndef mmiowb ++#define mmiowb() ++#endif ++ ++#if !defined(__iomem) ++#define __iomem ++#endif ++ ++#if !defined(__rcquires) ++#define __acquires(x) ++#define __releases(x) ++#endif ++ ++#ifndef HAVE_LE32 ++typedef u32 __le32; ++typedef u32 __be32; ++#endif ++ ++#ifndef USEC_PER_SEC ++#define USEC_PER_SEC 1000000L ++#endif ++ ++#ifndef __maybe_unused ++#define __maybe_unused ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x2060b) ++typedef u32 pm_message_t; ++typedef u32 pci_power_t; ++#define PCI_D0 0 ++#define PCI_D3hot 3 ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x020605) ++#define pci_dma_sync_single_for_cpu(pdev, map, len, dir) \ ++ pci_dma_sync_single(pdev, map, len, dir) ++ ++#define pci_dma_sync_single_for_device(pdev, map, len, dir) ++#endif ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ ++#define QID_TO_PM_OFFSET 4 ++ ++/* u32 fw_doorbell_ready */ ++#define KWQ_READY (1<<0) ++#define KWQ1_READY (1<<1) ++#define KWQ2_READY (1<<2) ++#define KWQ3_READY (1<<3) ++ ++#define KCQ_READY (1<<0) ++#define KCQ1_READY (1<<1) ++#define KCQ2_READY (1<<2) ++#define KCQ3_READY (1<<3) ++ ++typedef u16 l2_kcqe_errors_t; ++ #define L2_KCQE_ERRORS_BAD_CRC (1<<1) ++ #define L2_KCQE_ERRORS_PHY_DECODE (1<<2) ++ #define L2_KCQE_ERRORS_ALIGNMENT (1<<3) ++ #define L2_KCQE_ERRORS_TOO_SHORT (1<<4) ++ #define L2_KCQE_ERRORS_GIANT_FRAME (1<<5) ++ ++typedef u16 l2_kcqe_status_t; ++ #define L2_KCQE_STATUS_RULE_CLASS (0x7<<0) ++ #define L2_KCQE_STATUS_RULE_P2 (1<<3) ++ #define L2_KCQE_STATUS_RULE_P3 (1<<4) ++ #define L2_KCQE_STATUS_RULE_P4 (1<<5) ++ #define L2_KCQE_STATUS_L2_VLAN_TAG (1<<6) ++ #define L2_KCQE_STATUS_L2_LLC_SNAP (1<<7) ++ #define L2_KCQE_STATUS_L2_HASH (0x1f<<8) ++ #define L2_KCQE_STATUS_IP_DATAGRAM (1<<13) ++ #define L2_KCQE_STATUS_TCP_SEGMENT (1<<14) ++ #define L2_KCQE_STATUS_UDP_DATAGRAM (1<<15) ++ ++typedef u8 l2_kcqe_opcode_t; ++ #define L2_KCQE_OPCODE_VALUE (0xff<<0) ++ #define L2_KCQE_OPCODE_VALUE_RX_PACKET (0<<0) ++ #define L2_KCQE_OPCODE_VALUE_ENABLE_RSS (1<<0) ++ #define L2_KCQE_OPCODE_VALUE_DISABLE_RSS (2<<0) ++ #define L2_KCQE_OPCODE_VALUE_UPDATE_RSS (3<<0) ++ #define L2_KCQE_OPCODE_VALUE_FLUSH_BD_CHAIN (4<<0) ++ #define L2_KCQE_OPCODE_VALUE_DEBUG (5<<0) ++ #define L2_KCQE_OPCODE_VALUE_VM_ALLOC_TX_QUEUE (6<<0) ++ #define L2_KCQE_OPCODE_VALUE_VM_FREE_TX_QUEUE (7<<0) ++ #define L2_KCQE_OPCODE_VALUE_VM_ALLOC_RX_QUEUE (8<<0) ++ #define L2_KCQE_OPCODE_VALUE_VM_FREE_RX_QUEUE (9<<0) ++ #define L2_KCQE_OPCODE_VALUE_VM_SET_RX_FILTER (10<<0) ++ #define L2_KCQE_OPCODE_VALUE_VM_REMOVE_RX_FILTER (11<<0) ++ ++typedef u8 l2_kcqe_flags_t; ++ #define L2_KCQE_FLAGS_LAYER_MASK (0x7<<4) ++ #define L2_KCQE_FLAGS_LAYER_MASK_MISC (0<<4) ++ #define L2_KCQE_FLAGS_LAYER_MASK_L2 (2<<4) ++ #define L2_KCQE_FLAGS_LAYER_MASK_L3 (3<<4) ++ #define L2_KCQE_FLAGS_LAYER_MASK_L4 (4<<4) ++ #define L2_KCQE_FLAGS_LAYER_MASK_L5 (5<<4) ++ #define L2_KCQE_FLAGS_NEXT (1<<7) ++ ++/* ++ * l2_kcqe_l definition ++ */ ++#if defined(__BIG_ENDIAN) ++struct l2_kcqe { ++ u8 qid; ++ u8 status; ++ u16 reserved; ++ u32 reserved1[6]; ++ ++ l2_kcqe_flags_t flags; ++ l2_kcqe_opcode_t opcode; ++ u16 qe_self_seq; ++}; ++#elif defined(__LITTLE_ENDIAN) ++struct l2_kcqe { ++ u8 qid; ++ u8 status; ++ u16 reserved; ++ u32 reserved1[6]; ++ ++ u16 qe_self_seq; ++ l2_kcqe_opcode_t opcode; ++ l2_kcqe_flags_t flags; ++}; ++#endif ++ ++/* ++ * l2_kcqe_vm_alloc_tx_queue definition ++ */ ++#if defined(BIG_ENDIAN) ++struct l2_kcqe_vm_alloc_tx_queue { ++ u8 qid; ++ u8 status; ++ u16 reserved; ++ u32 reserved1[5]; ++ ++ l2_kcqe_flags_t flags; ++ l2_kcqe_opcode_t opcode; ++ u16 qe_self_seq; ++}; ++#elif defined(LITTLE_ENDIAN) ++struct l2_kcqe_vm_alloc_tx_queue { ++ u16 reserved; ++ u8 status; ++ u8 qid; ++ u32 reserved1[5]; ++ ++ u16 qe_self_seq; ++ l2_kcqe_opcode_t opcode; ++ l2_kcqe_flags_t flags; ++}; ++#endif ++ ++/* ++ * l2_kcqe_vm_free_tx_queue definition ++ */ ++#if defined(BIG_ENDIAN) ++struct l2_kcqe_vm_free_tx_queue { ++ u8 qid; ++ u8 status; ++ u16 nx_bidx; ++ u32 reserved1[5]; ++ ++ l2_kcqe_flags_t flags; ++ l2_kcqe_opcode_t opcode; ++ u16 qe_self_seq; ++}; ++#elif defined(LITTLE_ENDIAN) ++struct l2_kcqe_vm_free_tx_queue { ++ u16 nx_bidx; ++ u8 status; ++ u8 qid; ++ u32 reserved1[5]; ++ ++ u16 qe_self_seq; ++ l2_kcqe_opcode_t opcode; ++ l2_kcqe_flags_t flags; ++}; ++#endif ++ ++/* ++ * l2_kcqe_vm_alloc_rx_queue definition ++ */ ++#if defined(BIG_ENDIAN) ++struct l2_kcqe_vm_alloc_rx_queue_b { ++ u8 qid; ++ u8 status; ++ u16 reserved; ++ u32 reserved1[5]; ++ ++ l2_kcqe_flags_t flags; ++ l2_kcqe_opcode_t opcode; ++ u16 qe_self_seq; ++}; ++#elif defined(LITTLE_ENDIAN) ++struct l2_kcqe_vm_alloc_rx_queue_l { ++ u16 reserved; ++ u8 status; ++ u8 qid; ++ u32 reserved1[5]; ++ ++ u16 qe_self_seq; ++ l2_kcqe_opcode_t opcode; ++ l2_kcqe_flags_t flags; ++}; ++#endif ++ ++/* ++ * l2_kcqe_vm_free_rx_queue definition ++ */ ++#if defined(BIG_ENDIAN) ++struct l2_kcqe_vm_free_rx_queue { ++ u8 qid; ++ u8 status; ++ u16 nx_bidx; ++ u32 reserved1[5]; ++ ++ l2_kcqe_flags_t flags; ++ l2_kcqe_opcode_t opcode; ++ u16 qe_self_seq; ++}; ++#elif defined(LITTLE_ENDIAN) ++struct l2_kcqe_vm_free_rx_queue { ++ u16 nx_bidx; ++ u8 status; ++ u8 qid; ++ u32 reserved1[5]; ++ ++ u16 qe_self_seq; ++ l2_kcqe_opcode_t opcode; ++ l2_kcqe_flags_t flags; ++}; ++#endif ++ ++/* ++ * l2_kcqe_vm_set_rx_filter definition ++ */ ++#if defined(BIG_ENDIAN) ++struct l2_kcqe_vm_set_rx_filter { ++ u8 qid; ++ u8 status; ++ u16 reserved1; ++ u32 reserved2[5]; ++ ++ l2_kcqe_flags_t flags; ++ l2_kcqe_opcode_t opcode; ++ u16 qe_self_seq; ++}; ++#elif defined(LITTLE_ENDIAN) ++struct l2_kcqe_vm_set_rx_filter { ++ u16 reserved1; ++ u8 status; ++ u8 qid; ++ u32 reserved2[5]; ++ ++ u16 qe_self_seq; ++ l2_kcqe_opcode_t opcode; ++ l2_kcqe_flags_t flags; ++}; ++#endif ++ ++/* ++ * l2_kcqe_vm_remove_rx_filter definition ++ */ ++#if defined(BIG_ENDIAN) ++struct l2_kcqe_vm_remove_rx_filter { ++ u8 qid; ++ u8 status; ++ u16 reserved1; ++ u32 reserved2[5]; ++ ++ l2_kcqe_flags_t flags; ++ l2_kcqe_opcode_t opcode; ++ u16 qe_self_seq; ++}; ++#elif defined(LITTLE_ENDIAN) ++struct l2_kcqe_vm_remove_rx_filter { ++ u16 reserved1; ++ u8 status; ++ u8 qid; ++ u32 reserved2[5]; ++ ++ u16 qe_self_seq; ++ l2_kcqe_opcode_t opcode; ++ l2_kcqe_flags_t flags; ++}; ++#endif ++ ++/* ++ * kwqe definition ++ */ ++#if defined(__BIG_ENDIAN) ++struct l2_kwqe { ++ u8 kwqe_flags; ++ #define KWQE_FLAGS_LAYER_MASK (0x7<<4) ++ #define KWQE_FLAGS_LAYER_MASK_MISC (0<<4) ++ #define KWQE_FLAGS_LAYER_MASK_L2 (2<<4) ++ #define KWQE_FLAGS_LAYER_MASK_L3 (3<<4) ++ #define KWQE_FLAGS_LAYER_MASK_L4 (4<<4) ++ #define KWQE_FLAGS_LAYER_MASK_L5 (5<<4) ++ #define KWQE_FLAGS_NEXT (1<<7) ++ u8 kwqe_opcode; ++ u16 kwqe_info; ++ u32 kwqe_info0; ++ u32 kwqe_info1; ++ u32 kwqe_info2; ++ u32 kwqe_info3; ++ u32 kwqe_info4; ++ u32 kwqe_info5; ++ u32 kwqe_info6; ++}; ++#elif defined(__LITTLE_ENDIAN) ++struct l2_kwqe { ++ u16 kwqe_info; ++ u8 kwqe_opcode; ++ u8 kwqe_flags; ++ #define KWQE_FLAGS_LAYER_MASK (0x7<<4) ++ #define KWQE_FLAGS_LAYER_MASK_MISC (0<<4) ++ #define KWQE_FLAGS_LAYER_MASK_L2 (2<<4) ++ #define KWQE_FLAGS_LAYER_MASK_L3 (3<<4) ++ #define KWQE_FLAGS_LAYER_MASK_L4 (4<<4) ++ #define KWQE_FLAGS_LAYER_MASK_L5 (5<<4) ++ #define KWQE_FLAGS_GET_DEBUG_TRACE (7<<4) ++ #define KWQE_FLAGS_NEXT (1<<7) ++ u32 kwqe_info0; ++ u32 kwqe_info1; ++ u32 kwqe_info2; ++ u32 kwqe_info3; ++ u32 kwqe_info4; ++ u32 kwqe_info5; ++ u32 kwqe_info6; ++}; ++#endif ++ ++typedef u8 l2_kwqe_flags_t; ++ #define L2_KWQE_FLAGS_LAYER_MASK (0x7<<4) ++ #define L2_KWQE_FLAGS_LAYER_MASK_MISC (0<<4) ++ #define L2_KWQE_FLAGS_LAYER_MASK_L2 (2<<4) ++ #define L2_KWQE_FLAGS_LAYER_MASK_L3 (3<<4) ++ #define L2_KWQE_FLAGS_LAYER_MASK_L4 (4<<4) ++ #define L2_KWQE_FLAGS_LAYER_MASK_L5 (5<<4) ++ #define L2_KWQE_FLAGS_NEXT (1<<7) ++ ++typedef u8 l2_kwqe_opcode_t; ++ #define L2_KWQE_OPCODE_VALUE (0xff<<0) ++ #define L2_KWQE_OPCODE_VALUE_NOP (0<<0) ++ #define L2_KWQE_OPCODE_VALUE_ENABLE_RSS (1<<0) ++ #define L2_KWQE_OPCODE_VALUE_DISABLE_RSS (2<<0) ++ #define L2_KWQE_OPCODE_VALUE_UPDATE_RSS (3<<0) ++ #define L2_KWQE_OPCODE_VALUE_FLUSH_BD_CHAIN (4<<0) ++ #define L2_KWQE_OPCODE_VALUE_VM_ALLOC_TX_QUEUE (5<<0) ++ #define L2_KWQE_OPCODE_VALUE_VM_FREE_TX_QUEUE (6<<0) ++ #define L2_KWQE_OPCODE_VALUE_VM_ALLOC_RX_QUEUE (7<<0) ++ #define L2_KWQE_OPCODE_VALUE_VM_FREE_RX_QUEUE (8<<0) ++ #define L2_KWQE_OPCODE_VALUE_VM_SET_RX_FILTER (9<<0) ++ #define L2_KWQE_OPCODE_VALUE_VM_REMOVE_RX_FILTER (10<<0) ++ ++typedef u8 l2_kwqe_vm_filter_t; ++ #define L2_VM_FILTER_UNDEFINED 0 ++ #define L2_VM_FILTER_MAC 1 ++ #define L2_VM_FILTER_MAC_VLAN 2 ++ #define L2_VM_FILTER_VLAN 3 ++ ++typedef u8 l2_kwqe_queue_t; ++ #define L2_NORMAL_QUEUE 0 ++ #define L2_NET_QUEUE 1 ++ #define L2_VM_QUEUE 2 ++ #define L2_VM_DROP_QUEUE 3 ++ ++/* ++ * l2_kwqe_vm_alloc_tx_queue definition ++ */ ++#if defined(__BIG_ENDIAN) ++struct l2_kwqe_vm_alloc_tx_queue { ++ l2_kwqe_flags_t flags; ++ l2_kwqe_opcode_t opcode; ++ u8 queue_type; ++ u8 qid; ++ u32 reserved1[6]; ++}; ++#elif defined(__LITTLE_ENDIAN) ++struct l2_kwqe_vm_alloc_tx_queue { ++ u8 qid; ++ u8 queue_type; ++ l2_kwqe_opcode_t opcode; ++ l2_kwqe_flags_t flags; ++ u32 reserved1[6]; ++}; ++#endif ++ ++/* ++ * l2_kwqe_vm_free_tx_queue definition ++ */ ++#if defined(__BIG_ENDIAN) ++struct l2_kwqe_vm_free_tx_queue { ++ l2_kwqe_flags_t flags; ++ l2_kwqe_opcode_t opcode; ++ u8 qid; ++ u8 reserved; ++ u32 reserved1[6]; ++}; ++#elif defined(__LITTLE_ENDIAN) ++struct l2_kwqe_vm_free_tx_queue { ++ u8 reserved; ++ u8 qid; ++ l2_kwqe_opcode_t opcode; ++ l2_kwqe_flags_t flags; ++ u32 reserved1[6]; ++}; ++#endif ++ ++/* ++ * l2_kwqe_vm_alloc_rx_queue definition ++ */ ++#if defined(__BIG_ENDIAN) ++struct l2_kwqe_vm_alloc_rx_queue { ++ l2_kwqe_flags_t flags; ++ l2_kwqe_opcode_t opcode; ++ u8 queue_type; ++ u8 qid; ++ u32 reserved1[6]; ++}; ++#elif defined(__LITTLE_ENDIAN) ++struct l2_kwqe_vm_alloc_rx_queue { ++ u8 qid; ++ u8 queue_type; ++ l2_kwqe_opcode_t kwqe_opcode; ++ l2_kwqe_flags_t kwqe_flags; ++ u32 reserved1[6]; ++}; ++#endif ++ ++/* ++ * l2_kwqe_vm_free_rx_queue definition ++ */ ++#if defined(__BIG_ENDIAN) ++struct l2_kwqe_vm_free_rx_queue { ++ l2_kwqe_flags_t flags; ++ l2_kwqe_opcode_t opcode; ++ u8 qid; ++ u8 reserved; ++ u32 reserved1[6]; ++}; ++#elif defined(__LITTLE_ENDIAN) ++struct l2_kwqe_vm_free_rx_queue { ++ u8 reserved; ++ u8 qid; ++ l2_kwqe_opcode_t opcode; ++ l2_kwqe_flags_t flags; ++ u32 reserved1[6]; ++}; ++#endif ++ ++/* ++ * l2_kwqe_vm_set_rx_filter definition ++ */ ++#if defined(__BIG_ENDIAN) ++struct l2_kwqe_vm_set_rx_filter { ++ l2_kwqe_flags_t flags; ++ l2_kwqe_opcode_t opcode; ++ u8 qid; ++ l2_kwqe_vm_filter_t filter_type; ++ u16 vlan; ++ u8 mac_addr[6]; ++ u32 reserved1[4]; ++} l2_kwqe_vm_set_rx_filter_b_t; ++#elif defined(__LITTLE_ENDIAN) ++struct l2_kwqe_vm_set_rx_filter { ++ l2_kwqe_vm_filter_t filter_type; ++ u8 qid; ++ l2_kwqe_opcode_t opcode; ++ l2_kwqe_flags_t flags; ++ ++ u16 mac_addr_hi; ++ u16 vlan; ++ u32 mac_addr_lo; ++ u32 reserved1[4]; ++}; ++#endif ++ ++/* ++ * l2_kwqe_vm_remove_rx_filter ++ */ ++#if defined(BIG_ENDIAN) ++struct l2_kwqe_vm_remove_rx_filter { ++ l2_kwqe_flags_t flags; ++ l2_kwqe_opcode_t opcode; ++ u8 qid; ++ l2_kwqe_vm_filter_t filter_type; ++ u32 reserved1[6]; ++}; ++#elif defined(__LITTLE_ENDIAN) ++struct l2_kwqe_vm_remove_rx_filter { ++ l2_kwqe_vm_filter_t filter_type; ++ u8 qid; ++ l2_kwqe_opcode_t opcode; ++ l2_kwqe_flags_t flags; ++ u32 reserved1[6]; ++}; ++#endif ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x020612) ++static inline struct sk_buff *netdev_alloc_skb(struct net_device *dev, ++ unsigned int length) ++{ ++ struct sk_buff *skb = dev_alloc_skb(length); ++ if (skb) ++ skb->dev = dev; ++ return skb; ++} ++#endif ++ ++static inline void bnx2_skb_fill_page_desc(struct sk_buff *skb, int i, ++ struct page *page, int off, int size) ++{ ++#if (LINUX_VERSION_CODE < 0x020600) ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ ++ frag->page = page; ++ frag->page_offset = off; ++ frag->size = size; ++ skb_shinfo(skb)->nr_frags = i + 1; ++#else ++ skb_fill_page_desc(skb, i, page, off, size); ++#endif ++} ++ ++#ifndef NETIF_F_GSO ++static inline void netif_tx_lock(struct net_device *dev) ++{ ++ spin_lock(&dev->xmit_lock); ++ dev->xmit_lock_owner = smp_processor_id(); ++} ++ ++static inline void netif_tx_unlock(struct net_device *dev) ++{ ++ dev->xmit_lock_owner = -1; ++ spin_unlock(&dev->xmit_lock); ++} ++#endif ++ ++#if !defined(HAVE_NETDEV_PRIV) && (LINUX_VERSION_CODE != 0x020603) && (LINUX_VERSION_CODE != 0x020604) && (LINUX_VERSION_CODE != 0x20605) ++static inline void *netdev_priv(struct net_device *dev) ++{ ++ return dev->priv; ++} ++#endif ++ ++#ifdef OLD_NETIF ++static inline void netif_poll_disable(struct net_device *dev) ++{ ++ while (test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state)) { ++ /* No hurry. */ ++ current->state = TASK_INTERRUPTIBLE; ++ schedule_timeout(1); ++ } ++} ++ ++static inline void netif_poll_enable(struct net_device *dev) ++{ ++ clear_bit(__LINK_STATE_RX_SCHED, &dev->state); ++} ++ ++static inline void netif_tx_disable(struct net_device *dev) ++{ ++ spin_lock_bh(&dev->xmit_lock); ++ netif_stop_queue(dev); ++ spin_unlock_bh(&dev->xmit_lock); ++} ++ ++#endif ++ ++#if (LINUX_VERSION_CODE >= 0x20418) && (LINUX_VERSION_CODE < 0x2060c) ++static inline int bnx2_set_tx_hw_csum(struct net_device *dev, u32 data) ++{ ++ if (data) ++ dev->features |= NETIF_F_HW_CSUM; ++ else ++ dev->features &= ~NETIF_F_HW_CSUM; ++ ++ return 0; ++} ++#endif ++ ++#ifndef VLAN_GROUP_ARRAY_SPLIT_PARTS ++static inline void vlan_group_set_device(struct vlan_group *vg, int vlan_id, ++ struct net_device *dev) ++{ ++ if (vg) ++ vg->vlan_devices[vlan_id] = dev; ++} ++#endif ++ ++#ifdef NETIF_F_TSO ++#ifndef NETIF_F_GSO ++static inline int skb_is_gso(const struct sk_buff *skb) ++{ ++ return skb_shinfo(skb)->tso_size; ++} ++#define gso_size tso_size ++#define gso_segs tso_segs ++#endif ++#ifndef NETIF_F_TSO6 ++#define NETIF_F_TSO6 0 ++#define BCM_NO_TSO6 1 ++#endif ++#ifndef NETIF_F_TSO_ECN ++#define NETIF_F_TSO_ECN 0 ++#endif ++ ++#ifndef HAVE_IP_HDR ++static inline struct iphdr *ip_hdr(const struct sk_buff *skb) ++{ ++ return skb->nh.iph; ++} ++#endif ++ ++#ifndef NEW_SKB ++static inline int skb_transport_offset(const struct sk_buff *skb) ++{ ++ return (int) (skb->h.raw - skb->data); ++} ++ ++static inline unsigned int ip_hdrlen(const struct sk_buff *skb) ++{ ++ return ip_hdr(skb)->ihl * 4; ++} ++ ++static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb) ++{ ++ return skb->h.th; ++} ++ ++static inline unsigned int tcp_optlen(const struct sk_buff *skb) ++{ ++ return (tcp_hdr(skb)->doff - 5) * 4; ++} ++ ++#endif ++#endif /* #ifdef NETIF_F_TSO */ ++ ++#ifndef VMWARE_ESX_40_DDK ++#if ((LINUX_VERSION_CODE >= 0x20617) && !defined(NETIF_F_MULTI_QUEUE)) || defined(__VMKLNX__) ++ ++#define BCM_HAVE_MULTI_QUEUE ++ ++#else ++ ++static inline void netif_tx_wake_all_queues(struct net_device *dev) ++{ ++ netif_wake_queue(dev); ++} ++ ++static inline void netif_tx_start_all_queues(struct net_device *dev) ++{ ++ netif_start_queue(dev); ++} ++ ++#endif ++#else ++#define BCM_HAVE_MULTI_QUEUE ++#endif ++ ++ ++#ifndef NET_SKB_PAD ++#define NET_SKB_PAD 16 ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x02061e) ++static inline void skb_record_rx_queue(struct sk_buff *skb, u16 rx_queue) ++{ ++} ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x020600) ++#define dev_err(unused, format, arg...) \ ++ printk(KERN_ERR "bnx2: " format , ## arg) ++#else ++#ifndef dev_err ++#ifndef dev_printk ++#define dev_printk(level, dev, format, arg...) \ ++ printk(level "bnx2 %s: " format , (dev)->bus_id , ## arg) ++#endif ++#define dev_err(dev, format, arg...) \ ++ dev_printk(KERN_ERR , dev , format , ## arg) ++#endif ++#endif ++ ++#ifndef DECLARE_MAC_BUF ++#define DECLARE_MAC_BUF(var) char var[18] ++#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" ++static inline char *print_mac(char *buf, const u8 *addr) ++{ ++ sprintf(buf, MAC_FMT, ++ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); ++ return buf; ++} ++#endif ++ ++#ifndef ARRAY_SIZE ++#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) ++#endif ++ ++#if (LINUX_VERSION_CODE >= 0x020618) ++#define BNX2_NEW_NAPI 1 ++#endif ++ ++static inline void bnx2_msleep(unsigned int msecs) ++{ ++#if (LINUX_VERSION_CODE < 0x20607) ++ current->state = TASK_UNINTERRUPTIBLE; ++ schedule_timeout((msecs * HZ / 1000) + 1); ++#else ++ msleep(msecs); ++#endif ++} ++ ++static inline unsigned long bnx2_msleep_interruptible(unsigned int msecs) ++{ ++#if (LINUX_VERSION_CODE < 0x20609) ++ current->state = TASK_INTERRUPTIBLE; ++ return schedule_timeout((msecs * HZ / 1000) + 1); ++#else ++ return msleep_interruptible(msecs); ++#endif ++} ++ ++#ifdef __VMKLNX__ ++/** ++ * THIS FUNCTION SHOULD BE REMOVED ONCE PR 379263 IS RESOLVED ++ */ ++static void *bcm_memmove(void *dest, const void *src, size_t count) ++{ ++ char *tmp; ++ const char *s; ++ ++ if (dest <= src) { ++ tmp = dest; ++ s = src; ++ while (count--) ++ *tmp++ = *s++; ++ } else { ++ tmp = dest; ++ tmp += count; ++ s = src; ++ s += count; ++ while (count--) ++ *--tmp = *--s; ++ } ++ return dest; ++} ++#else ++#define bcm_memmove memmove ++#endif /* __VMKLNX__ */ + + /* Hardware data structures and register definitions automatically + * generated from RTL code. Do not modify. +@@ -66,7 +950,7 @@ + * status_block definition + */ + struct status_block { +- u32 status_attn_bits; ++ volatile u32 status_attn_bits; + #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) + #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) + #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) +@@ -98,84 +982,85 @@ + #define STATUS_ATTN_BITS_EPB_ERROR (1L<<30) + #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) + +- u32 status_attn_bits_ack; +-#if defined(__BIG_ENDIAN) +- u16 status_tx_quick_consumer_index0; +- u16 status_tx_quick_consumer_index1; +- u16 status_tx_quick_consumer_index2; +- u16 status_tx_quick_consumer_index3; +- u16 status_rx_quick_consumer_index0; +- u16 status_rx_quick_consumer_index1; +- u16 status_rx_quick_consumer_index2; +- u16 status_rx_quick_consumer_index3; +- u16 status_rx_quick_consumer_index4; +- u16 status_rx_quick_consumer_index5; +- u16 status_rx_quick_consumer_index6; +- u16 status_rx_quick_consumer_index7; +- u16 status_rx_quick_consumer_index8; +- u16 status_rx_quick_consumer_index9; +- u16 status_rx_quick_consumer_index10; +- u16 status_rx_quick_consumer_index11; +- u16 status_rx_quick_consumer_index12; +- u16 status_rx_quick_consumer_index13; +- u16 status_rx_quick_consumer_index14; +- u16 status_rx_quick_consumer_index15; +- u16 status_completion_producer_index; +- u16 status_cmd_consumer_index; +- u16 status_idx; +- u8 status_unused; +- u8 status_blk_num; +-#elif defined(__LITTLE_ENDIAN) +- u16 status_tx_quick_consumer_index1; +- u16 status_tx_quick_consumer_index0; +- u16 status_tx_quick_consumer_index3; +- u16 status_tx_quick_consumer_index2; +- u16 status_rx_quick_consumer_index1; +- u16 status_rx_quick_consumer_index0; +- u16 status_rx_quick_consumer_index3; +- u16 status_rx_quick_consumer_index2; +- u16 status_rx_quick_consumer_index5; +- u16 status_rx_quick_consumer_index4; +- u16 status_rx_quick_consumer_index7; +- u16 status_rx_quick_consumer_index6; +- u16 status_rx_quick_consumer_index9; +- u16 status_rx_quick_consumer_index8; +- u16 status_rx_quick_consumer_index11; +- u16 status_rx_quick_consumer_index10; +- u16 status_rx_quick_consumer_index13; +- u16 status_rx_quick_consumer_index12; +- u16 status_rx_quick_consumer_index15; +- u16 status_rx_quick_consumer_index14; +- u16 status_cmd_consumer_index; +- u16 status_completion_producer_index; +- u8 status_blk_num; +- u8 status_unused; +- u16 status_idx; +-#endif +-}; ++ volatile u32 status_attn_bits_ack; ++#if defined(__BIG_ENDIAN) ++ volatile u16 status_tx_quick_consumer_index0; ++ volatile u16 status_tx_quick_consumer_index1; ++ volatile u16 status_tx_quick_consumer_index2; ++ volatile u16 status_tx_quick_consumer_index3; ++ volatile u16 status_rx_quick_consumer_index0; ++ volatile u16 status_rx_quick_consumer_index1; ++ volatile u16 status_rx_quick_consumer_index2; ++ volatile u16 status_rx_quick_consumer_index3; ++ volatile u16 status_rx_quick_consumer_index4; ++ volatile u16 status_rx_quick_consumer_index5; ++ volatile u16 status_rx_quick_consumer_index6; ++ volatile u16 status_rx_quick_consumer_index7; ++ volatile u16 status_rx_quick_consumer_index8; ++ volatile u16 status_rx_quick_consumer_index9; ++ volatile u16 status_rx_quick_consumer_index10; ++ volatile u16 status_rx_quick_consumer_index11; ++ volatile u16 status_rx_quick_consumer_index12; ++ volatile u16 status_rx_quick_consumer_index13; ++ volatile u16 status_rx_quick_consumer_index14; ++ volatile u16 status_rx_quick_consumer_index15; ++ volatile u16 status_completion_producer_index; ++ volatile u16 status_cmd_consumer_index; ++ volatile u16 status_idx; ++ volatile u8 status_unused; ++ volatile u8 status_blk_num; ++#elif defined(__LITTLE_ENDIAN) ++ volatile u16 status_tx_quick_consumer_index1; ++ volatile u16 status_tx_quick_consumer_index0; ++ volatile u16 status_tx_quick_consumer_index3; ++ volatile u16 status_tx_quick_consumer_index2; ++ volatile u16 status_rx_quick_consumer_index1; ++ volatile u16 status_rx_quick_consumer_index0; ++ volatile u16 status_rx_quick_consumer_index3; ++ volatile u16 status_rx_quick_consumer_index2; ++ volatile u16 status_rx_quick_consumer_index5; ++ volatile u16 status_rx_quick_consumer_index4; ++ volatile u16 status_rx_quick_consumer_index7; ++ volatile u16 status_rx_quick_consumer_index6; ++ volatile u16 status_rx_quick_consumer_index9; ++ volatile u16 status_rx_quick_consumer_index8; ++ volatile u16 status_rx_quick_consumer_index11; ++ volatile u16 status_rx_quick_consumer_index10; ++ volatile u16 status_rx_quick_consumer_index13; ++ volatile u16 status_rx_quick_consumer_index12; ++ volatile u16 status_rx_quick_consumer_index15; ++ volatile u16 status_rx_quick_consumer_index14; ++ volatile u16 status_cmd_consumer_index; ++ volatile u16 status_completion_producer_index; ++ volatile u8 status_blk_num; ++ volatile u8 status_unused; ++ volatile u16 status_idx; ++#endif ++}; ++ + + /* + * status_block definition + */ + struct status_block_msix { + #if defined(__BIG_ENDIAN) +- u16 status_tx_quick_consumer_index; +- u16 status_rx_quick_consumer_index; +- u16 status_completion_producer_index; +- u16 status_cmd_consumer_index; +- u32 status_unused; +- u16 status_idx; +- u8 status_unused2; +- u8 status_blk_num; +-#elif defined(__LITTLE_ENDIAN) +- u16 status_rx_quick_consumer_index; +- u16 status_tx_quick_consumer_index; +- u16 status_cmd_consumer_index; +- u16 status_completion_producer_index; +- u32 status_unused; +- u8 status_blk_num; +- u8 status_unused2; +- u16 status_idx; ++ volatile u16 status_tx_quick_consumer_index; ++ volatile u16 status_rx_quick_consumer_index; ++ volatile u16 status_completion_producer_index; ++ volatile u16 status_cmd_consumer_index; ++ volatile u32 status_unused; ++ volatile u16 status_idx; ++ volatile u8 status_unused2; ++ volatile u8 status_blk_num; ++#elif defined(__LITTLE_ENDIAN) ++ volatile u16 status_rx_quick_consumer_index; ++ volatile u16 status_tx_quick_consumer_index; ++ volatile u16 status_cmd_consumer_index; ++ volatile u16 status_completion_producer_index; ++ volatile u32 status_unused; ++ volatile u8 status_blk_num; ++ volatile u8 status_unused2; ++ volatile u16 status_idx; + #endif + }; + +@@ -361,6 +1246,9 @@ + #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) + + #define BNX2_L2CTX_HOST_BDIDX 0x00000004 ++#define BNX2_L2CTX_STATUSB_NUM_SHIFT 16 ++#define BNX2_L2CTX_STATUSB_NUM(sb_id) \ ++ (((sb_id) > 0) ? (((sb_id) + 7) << BNX2_L2CTX_STATUSB_NUM_SHIFT) : 0) + #define BNX2_L2CTX_HOST_BSEQ 0x00000008 + #define BNX2_L2CTX_NX_BSEQ 0x0000000c + #define BNX2_L2CTX_NX_BDHADDR_HI 0x00000010 +@@ -378,6 +1266,9 @@ + * pci_config_l definition + * offset: 0000 + */ ++#define BNX2_PCICFG_MSI_CONTROL 0x00000058 ++#define BNX2_PCICFG_MSI_CONTROL_ENABLE (1L<<16) ++ + #define BNX2_PCICFG_MISC_CONFIG 0x00000068 + #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) + #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) +@@ -4199,7 +5090,14 @@ + + #define BNX2_RBUF_CONFIG 0x0020000c + #define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) ++#define BNX2_RBUF_CONFIG_XOFF_TRIP_VAL(mtu) \ ++ ((((mtu) - 1500) * 31 / 1000) + 54) + #define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) ++#define BNX2_RBUF_CONFIG_XON_TRIP_VAL(mtu) \ ++ ((((mtu) - 1500) * 39 / 1000) + 66) ++#define BNX2_RBUF_CONFIG_VAL(mtu) \ ++ (BNX2_RBUF_CONFIG_XOFF_TRIP_VAL(mtu) | \ ++ (BNX2_RBUF_CONFIG_XON_TRIP_VAL(mtu) << 16)) + + #define BNX2_RBUF_FW_BUF_ALLOC 0x00200010 + #define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) +@@ -4221,11 +5119,25 @@ + + #define BNX2_RBUF_CONFIG2 0x0020001c + #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) ++#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL(mtu) \ ++ ((((mtu) - 1500) * 4 / 1000) + 5) + #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) ++#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL(mtu) \ ++ ((((mtu) - 1500) * 2 / 100) + 30) ++#define BNX2_RBUF_CONFIG2_VAL(mtu) \ ++ (BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL(mtu) | \ ++ (BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL(mtu) << 16)) + + #define BNX2_RBUF_CONFIG3 0x00200020 + #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) ++#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL(mtu) \ ++ ((((mtu) - 1500) * 12 / 1000) + 18) + #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) ++#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL(mtu) \ ++ ((((mtu) - 1500) * 2 / 100) + 30) ++#define BNX2_RBUF_CONFIG3_VAL(mtu) \ ++ (BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL(mtu) | \ ++ (BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL(mtu) << 16)) + + #define BNX2_RBUF_PKT_DATA 0x00208000 + #define BNX2_RBUF_CLIST_DATA 0x00210000 +@@ -4509,6 +5421,10 @@ + #define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) + #define BNX2_MQ_MEM_RD_DATA2_VALUE_XI (0x7fffffffL<<0) + ++#define BNX2_MQ_CONFIG2 0x00003d00 ++#define BNX2_MQ_CONFIG2_CONT_SZ (0x7L<<4) ++#define BNX2_MQ_CONFIG2_FIRST_L4L5 (0x1fL<<8) ++ + #define BNX2_MQ_MAP_L2_3 0x00003d2c + #define BNX2_MQ_MAP_L2_3_MQ_OFFSET (0xffL<<0) + #define BNX2_MQ_MAP_L2_3_SZ (0x3L<<8) +@@ -4520,6 +5436,7 @@ + + #define BNX2_MQ_MAP_L2_5 0x00003d34 + #define BNX2_MQ_MAP_L2_5_ARM (0x3L<<26) ++ + + /* + * tsch_reg definition +@@ -5876,6 +6793,7 @@ + #define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + + #define BNX2_RXP_SCRATCH 0x000e0000 ++#define BNX2_RXP_SCRATCH_RXP_FLOOD 0x000e0024 + #define BNX2_RXP_SCRATCH_RSS_TBL_SZ 0x000e0038 + #define BNX2_RXP_SCRATCH_RSS_TBL 0x000e003c + #define BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES 128 +@@ -6165,6 +7083,8 @@ + #define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + + #define BNX2_CP_SCRATCH 0x001a0000 ++ ++#define BNX2_FW_MAX_ISCSI_CONN 0x001a0080 + + + /* +@@ -6459,8 +7379,8 @@ + #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd)) + #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) + +-#define MAX_RX_RINGS 4 +-#define MAX_RX_PG_RINGS 16 ++#define MAX_RX_RINGS 16 ++#define MAX_RX_PG_RINGS 64 + #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd)) + #define MAX_RX_DESC_CNT (RX_DESC_CNT - 1) + #define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS) +@@ -6516,6 +7436,11 @@ + #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) + #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) + ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++#define NETQUEUE_KWQ_CID 97 ++#define NETQUEUE_KCQ_CID 100 ++#endif ++ + struct sw_bd { + struct sk_buff *skb; + DECLARE_PCI_UNMAP_ADDR(mapping) +@@ -6526,10 +7451,17 @@ + DECLARE_PCI_UNMAP_ADDR(mapping) + }; + ++struct sw_tx_bd { ++ struct sk_buff *skb; ++ unsigned short is_gso; ++ unsigned short nr_frags; ++ DECLARE_PCI_UNMAP_ADDR(mapping) ++}; ++ + #define SW_RXBD_RING_SIZE (sizeof(struct sw_bd) * RX_DESC_CNT) + #define SW_RXPG_RING_SIZE (sizeof(struct sw_pg) * RX_DESC_CNT) + #define RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) +-#define SW_TXBD_RING_SIZE (sizeof(struct sw_bd) * TX_DESC_CNT) ++#define SW_TXBD_RING_SIZE (sizeof(struct sw_tx_bd) * TX_DESC_CNT) + #define TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) + + /* Buffered flash (Atmel: AT45DB011B) specific information */ +@@ -6596,7 +7528,11 @@ + #define BNX2_TX_INT_NUM (BNX2_TX_VEC << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT) + + struct bnx2_irq { ++#if (LINUX_VERSION_CODE < 0x020613) ++ irqreturn_t (*handler)(int, void *, struct pt_regs *); ++#else + irq_handler_t handler; ++#endif + unsigned int vector; + u8 requested; + char name[16]; +@@ -6609,7 +7545,7 @@ + u32 tx_bseq_addr; + + struct tx_bd *tx_desc_ring; +- struct sw_bd *tx_buf_ring; ++ struct sw_tx_bd *tx_buf_ring; + + u16 tx_cons; + u16 hw_tx_cons; +@@ -6639,20 +7575,55 @@ + }; + + struct bnx2_napi { ++#ifdef BNX2_NEW_NAPI + struct napi_struct napi ____cacheline_aligned; ++#endif + struct bnx2 *bp; + union { + struct status_block *msi; + struct status_block_msix *msix; + } status_blk; +- u16 *hw_tx_cons_ptr; +- u16 *hw_rx_cons_ptr; ++ volatile u16 *hw_tx_cons_ptr; ++ volatile u16 *hw_rx_cons_ptr; + u32 last_status_idx; + u32 int_num; + ++ u32 cnic_tag; ++ int cnic_present; ++ + struct bnx2_rx_ring_info rx_ring; + struct bnx2_tx_ring_info tx_ring; +-}; ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ u8 rx_queue_allocated; ++ u8 tx_queue_allocated; ++ u8 rx_queue_active; ++ u8 tx_queue_active; ++ ++ u8 mac_filter_addr[6]; ++ u16 netq_flags; ++#define BNX2_NETQ_FREE_TX_QUEUE_STATE 0x0001 ++ ++ struct net_device_stats stats; ++#endif ++}; ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++struct netq_dma { ++ int num_pages; ++ void **pg_arr; ++ dma_addr_t *pg_map_arr; ++ int pgtbl_size; ++ u32 *pgtbl; ++ dma_addr_t pgtbl_map; ++}; ++ ++struct netq_ctx { ++ u32 cid; ++ void *ctx; ++ dma_addr_t mapping; ++}; ++#endif + + struct bnx2 { + /* Fields used in the tx and intr/napi performance paths are grouped */ +@@ -6679,6 +7650,7 @@ + BNX2_FLAG_USING_MSIX) + #define BNX2_FLAG_JUMBO_BROKEN 0x00000800 + #define BNX2_FLAG_CAN_KEEP_VLAN 0x00001000 ++#define BNX2_FLAG_BROKEN_STATS 0x00002000 + + struct bnx2_napi bnx2_napi[BNX2_MAX_MSIX_VEC]; + +@@ -6699,14 +7671,22 @@ + int tx_ring_size; + u32 tx_wake_thresh; + ++ struct cnic_ops *cnic_ops; ++ void *cnic_data; ++ + /* End of fields used in the performance code paths. */ + +- char *name; +- +- int timer_interval; +- int current_interval; ++ unsigned int current_interval; ++#define BNX2_TIMER_INTERVAL HZ ++#define BNX2_SERDES_AN_TIMEOUT (HZ / 3) ++#define BNX2_SERDES_FORCED_TIMEOUT (HZ / 10) ++ + struct timer_list timer; ++#if (LINUX_VERSION_CODE >= 0x020600) + struct work_struct reset_task; ++#else ++ struct tq_struct reset_task; ++#endif + + /* Used to synchronize phy accesses. */ + spinlock_t phy_lock; +@@ -6819,8 +7799,10 @@ + u8 flow_ctrl; /* actual flow ctrl settings */ + /* may be different from */ + /* req_flow_ctrl if autoneg */ ++#ifndef FLOW_CTRL_TX + #define FLOW_CTRL_TX 1 + #define FLOW_CTRL_RX 2 ++#endif + + u32 advertising; + +@@ -6836,8 +7818,6 @@ + #define PHY_LOOPBACK 2 + + u8 serdes_an_pending; +-#define SERDES_AN_TIMEOUT (HZ / 3) +-#define SERDES_FORCED_TIMEOUT (HZ / 10) + + u8 mac_addr[8]; + +@@ -6855,11 +7835,53 @@ + + int status_stats_size; + ++ struct z_stream_s *strm; ++ void *gunzip_buf; ++ + struct bnx2_irq irq_tbl[BNX2_MAX_MSIX_VEC]; + int irq_nvecs; + + u8 num_tx_rings; + u8 num_rx_rings; ++ ++ u32 idle_chk_status_idx; ++ ++ spinlock_t cnic_lock; ++ struct cnic_eth_dev cnic_eth_dev; ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ u16 n_rx_queues_allocated; ++ u16 n_tx_queues_allocated; ++ ++ /* KWQ/KCQ for NetQueue */ ++ u32 netq_kwq_cid_addr; ++ u32 netq_kcq_cid_addr; ++ ++ struct netq_dma netq_kwq_info; ++ struct l2_kwqe **netq_kwq; ++ ++ u16 netq_kwq_prod_idx; ++ u32 netq_kwq_io_addr; ++ ++ u16 netq_kwq_con_idx; ++ ++ struct netq_dma netq_kcq_info; ++ struct l2_kcqe **netq_kcq; ++ ++ u16 netq_kcq_prod_idx; ++ u32 netq_kcq_io_addr; ++ ++ u32 netq_last_status_idx; ++ ++#define MAX_COMPLETED_KCQE 64 ++ struct l2_kcqe *netq_completed_kcq[MAX_COMPLETED_KCQE]; ++ ++ u8 netq_flags; ++ u8 netq_enabled; ++ u8 reserved1[2]; ++ ++ wait_queue_head_t netq_wait; ++#endif + }; + + #define REG_RD(bp, offset) \ +@@ -6902,7 +7924,7 @@ + const u32 text_len; + const u32 text_index; + __le32 *text; +- u8 *gz_text; ++ const u8 *gz_text; + const u32 gz_text_len; + + /* Data section. */ +@@ -6935,14 +7957,14 @@ + /* This value (in milliseconds) determines the frequency of the driver + * issuing the PULSE message code. The firmware monitors this periodic + * pulse to determine when to switch to an OS-absent mode. */ +-#define DRV_PULSE_PERIOD_MS 250 ++#define BNX2_DRV_PULSE_PERIOD_MS 250 + + /* This value (in milliseconds) determines how long the driver should + * wait for an acknowledgement from the firmware before timing out. Once + * the firmware has timed out, the driver will assume there is no firmware + * running and there won't be any firmware-driver synchronization during a + * driver reset. */ +-#define FW_ACK_TIME_OUT_MS 1000 ++#define BNX2_FW_ACK_TIME_OUT_MS 1000 + + + #define BNX2_DRV_RESET_SIGNATURE 0x00000000 +diff -r 5f108bc568be drivers/net/bnx2_fw.h +--- a/drivers/net/bnx2_fw.h Tue Sep 01 13:49:15 2009 +0100 ++++ b/drivers/net/bnx2_fw.h Tue Sep 01 13:50:08 2009 +0100 +@@ -15,854 +15,856 @@ + */ + + static u8 bnx2_COM_b06FwText[] = { +- 0xcd, 0x7c, 0x0d, 0x70, 0x5c, 0xd5, 0x95, 0xe6, 0xe9, 0xd7, 0xdd, 0x52, +- 0x4b, 0x96, 0xe5, 0x27, 0xb9, 0x51, 0x1a, 0xa2, 0x24, 0xef, 0xa9, 0x9f, +- 0xa4, 0x06, 0x29, 0xe4, 0xd9, 0x08, 0x10, 0x49, 0x0f, 0x34, 0xdd, 0x92, +- 0x11, 0x89, 0x77, 0x24, 0x40, 0x61, 0xbc, 0x3b, 0xae, 0xac, 0xa6, 0x2d, +- 0x13, 0x42, 0x31, 0x35, 0xae, 0x0a, 0x3b, 0x71, 0xb2, 0x04, 0x37, 0x2d, +- 0x99, 0x38, 0x8c, 0xec, 0x56, 0x64, 0x59, 0x66, 0x67, 0xd8, 0xd9, 0x4e, +- 0x4b, 0xb2, 0x19, 0xa6, 0xed, 0xc6, 0x90, 0x1f, 0xa6, 0x92, 0x0c, 0x5a, +- 0xe3, 0x00, 0x93, 0xcd, 0x56, 0x41, 0x2a, 0xb5, 0xcb, 0x6c, 0x51, 0xbb, +- 0x5e, 0x27, 0x4c, 0xb2, 0xa9, 0xda, 0x0a, 0x3b, 0x93, 0xda, 0x65, 0xf2, +- 0x33, 0x6f, 0xbf, 0xef, 0xbe, 0xfb, 0xa4, 0x96, 0xac, 0x38, 0x4c, 0xa6, +- 0x52, 0x35, 0xaa, 0xea, 0xba, 0xef, 0xde, 0x77, 0x7f, 0xce, 0x3d, 0xf7, +- 0xdc, 0x73, 0xbe, 0x73, 0xee, 0x7d, 0xba, 0x55, 0xa4, 0x59, 0xf4, 0xdf, +- 0x56, 0xfc, 0x06, 0x7e, 0xff, 0x0f, 0xf6, 0xdd, 0x78, 0xbd, 0x7b, 0x3d, +- 0xf3, 0x46, 0x54, 0x22, 0x4c, 0xc3, 0xf8, 0xc5, 0xf1, 0xdb, 0xa9, 0x9f, +- 0x37, 0xfb, 0x33, 0xf1, 0xbb, 0x29, 0x24, 0x32, 0xf1, 0x23, 0x91, 0xd0, +- 0x86, 0x77, 0xb1, 0x4d, 0xea, 0x7b, 0xde, 0x2f, 0xe9, 0x48, 0xff, 0x19, +- 0xf8, 0x59, 0x57, 0xae, 0xb2, 0x3a, 0xee, 0xaf, 0xfb, 0x17, 0xd6, 0xcd, +- 0xb7, 0xea, 0x9f, 0xc4, 0x8c, 0xf4, 0xc5, 0xdf, 0xce, 0x3a, 0x12, 0x0b, +- 0xa7, 0xbf, 0x3b, 0xba, 0xcf, 0x11, 0xc9, 0x54, 0xfb, 0xac, 0x9c, 0xfc, +- 0xc2, 0x2b, 0xc4, 0x23, 0xc2, 0xf2, 0xf7, 0xa4, 0x7f, 0x7e, 0xe8, 0x1b, +- 0x37, 0xdb, 0x6f, 0x95, 0xc3, 0x12, 0x33, 0xd3, 0x6f, 0x8b, 0xd9, 0x23, +- 0xb1, 0x4e, 0xb4, 0x79, 0xb2, 0xf7, 0x29, 0x43, 0x5a, 0x83, 0xbe, 0xcc, +- 0x89, 0x70, 0x5a, 0xc6, 0x26, 0x67, 0x0e, 0x79, 0x86, 0x23, 0x85, 0x6b, +- 0xd2, 0x8e, 0x55, 0x94, 0x96, 0xc1, 0xe9, 0x81, 0x9b, 0x05, 0xf9, 0xb1, +- 0xc9, 0x6a, 0x4c, 0xb2, 0xb5, 0x42, 0x8b, 0xe1, 0x38, 0x48, 0x63, 0x85, +- 0x77, 0xa7, 0x25, 0xd6, 0x90, 0x9e, 0x6f, 0x7c, 0xc9, 0xe1, 0xf8, 0x89, +- 0xd1, 0xac, 0xf3, 0x6e, 0x89, 0x38, 0x9e, 0x37, 0x8d, 0xf1, 0x77, 0x55, +- 0x7f, 0xe1, 0x3d, 0x1a, 0xf1, 0xc7, 0x36, 0xd2, 0x07, 0xc3, 0x4c, 0x43, +- 0x69, 0x6b, 0xb4, 0xab, 0xaa, 0xf2, 0x0d, 0x7e, 0xde, 0xd1, 0xf9, 0x58, +- 0xb3, 0x4f, 0xbb, 0x34, 0x81, 0xf6, 0x58, 0x24, 0x9d, 0x6e, 0x42, 0x1f, +- 0xb1, 0x68, 0xfa, 0x99, 0xdf, 0x5a, 0x56, 0xf5, 0xee, 0xd7, 0xf5, 0xee, +- 0x8f, 0xfa, 0xed, 0x26, 0x47, 0x7b, 0xaa, 0x4c, 0x1f, 0x1a, 0xed, 0x56, +- 0xe9, 0xc3, 0xa3, 0x49, 0x95, 0x16, 0x54, 0xbd, 0x50, 0x7a, 0x7a, 0xd4, +- 0x51, 0x69, 0xa7, 0x2e, 0x4f, 0x8d, 0x5a, 0x2a, 0xed, 0xd7, 0xa9, 0xab, +- 0xd3, 0x01, 0x9d, 0x0e, 0xea, 0x34, 0xad, 0xd3, 0x8c, 0x4e, 0x87, 0x74, +- 0x3f, 0x23, 0x3a, 0xbf, 0x5b, 0xa7, 0x63, 0x3a, 0x1d, 0xd7, 0xe9, 0x1e, +- 0x9d, 0xee, 0xd5, 0x74, 0x4d, 0xe8, 0xf4, 0x41, 0x5d, 0x7e, 0x40, 0xd3, +- 0x79, 0x10, 0xf4, 0x7c, 0xa6, 0x51, 0xcb, 0x2d, 0xe6, 0x6b, 0xc9, 0xbe, +- 0x99, 0x98, 0x14, 0x4b, 0x61, 0xc9, 0xa9, 0xf5, 0xfc, 0x7c, 0x54, 0x9a, +- 0x63, 0x32, 0x55, 0x8b, 0xc9, 0x45, 0x25, 0xae, 0x3f, 0xf4, 0xbe, 0xd1, +- 0x6b, 0xca, 0x33, 0xb5, 0xb8, 0xbc, 0x50, 0x93, 0xd0, 0x58, 0x6f, 0x93, +- 0x18, 0x73, 0xd7, 0x48, 0xc6, 0x0c, 0x49, 0x58, 0xf1, 0xd5, 0x92, 0xec, +- 0x4c, 0x07, 0xf2, 0x76, 0x42, 0xe4, 0xe5, 0xa8, 0xbf, 0x8e, 0x31, 0x09, +- 0x2f, 0x70, 0x5d, 0x16, 0x46, 0x5f, 0x9a, 0x4f, 0x48, 0xe4, 0x98, 0x85, +- 0xfe, 0x5b, 0x24, 0xba, 0x20, 0x9d, 0x61, 0xe9, 0x4e, 0xdc, 0x87, 0x1a, +- 0x43, 0xd5, 0x88, 0x0c, 0x57, 0x43, 0x58, 0xab, 0x18, 0xe4, 0xa4, 0x05, +- 0x3f, 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0x88, 0xae, 0xe2, 0x0d, 0x7f, 0xac, 0x62, 0x7b, +- 0x80, 0x35, 0xfc, 0x39, 0xf8, 0x58, 0xc3, 0x97, 0xf3, 0x49, 0x89, 0x40, +- 0x8e, 0xc3, 0x6b, 0x72, 0x0c, 0xdc, 0xe3, 0xef, 0x99, 0x29, 0x9e, 0xdb, +- 0x29, 0x3e, 0x53, 0x0e, 0x29, 0xbf, 0x5c, 0xc7, 0xfa, 0xb5, 0xbe, 0xf1, +- 0x97, 0xac, 0xf5, 0x85, 0xf6, 0x00, 0x3f, 0xfc, 0xd3, 0xf6, 0xc1, 0xd7, +- 0xda, 0xd7, 0xf6, 0xc1, 0x35, 0xbf, 0xa1, 0x7d, 0xb0, 0x51, 0x2e, 0xeb, +- 0x65, 0xca, 0x84, 0x3c, 0x71, 0xbd, 0x28, 0x4f, 0x94, 0x23, 0xf2, 0x92, +- 0xfa, 0xb4, 0x91, 0xbe, 0x53, 0xe2, 0xa2, 0xfa, 0x3e, 0x62, 0x1a, 0x3a, +- 0xa8, 0x3d, 0x54, 0x86, 0x5f, 0x5e, 0x5c, 0xba, 0x49, 0xc9, 0xf4, 0xd3, +- 0x35, 0xea, 0xa5, 0x2b, 0xcd, 0x7d, 0xbd, 0xce, 0xcd, 0x6f, 0xd0, 0xb9, +- 0xf9, 0x55, 0x9d, 0xdb, 0xa6, 0xfd, 0xa5, 0x7f, 0x8a, 0xce, 0x8d, 0xd7, +- 0x9d, 0x85, 0x04, 0xe7, 0x20, 0x12, 0xca, 0xf6, 0x36, 0xcb, 0xae, 0xd9, +- 0xb8, 0x8c, 0xcc, 0xec, 0x96, 0x3f, 0x9a, 0x99, 0x56, 0xf7, 0x82, 0xfe, +- 0xca, 0x4d, 0x26, 0xee, 0x0f, 0x79, 0xf2, 0x61, 0xf8, 0xbb, 0x13, 0x9d, +- 0x0d, 0xb2, 0xeb, 0xfd, 0xea, 0x7c, 0xcf, 0xcc, 0x86, 0x3a, 0x84, 0x91, +- 0xe7, 0x9c, 0x6b, 0xbb, 0x56, 0x88, 0x77, 0xc4, 0x1a, 0x65, 0x22, 0xde, +- 0x22, 0xbb, 0x81, 0x9d, 0x0a, 0x57, 0xb9, 0xea, 0x9b, 0xed, 0x8c, 0x3a, +- 0x3f, 0xe9, 0xde, 0xee, 0x8f, 0x0b, 0x3e, 0xb4, 0x9a, 0xf2, 0xe7, 0xb5, +- 0x6e, 0xf5, 0xfd, 0xf1, 0x0b, 0xa5, 0x3f, 0x6f, 0x5b, 0x9f, 0xe7, 0xf3, +- 0x7f, 0x42, 0x9d, 0x38, 0x78, 0x55, 0x7f, 0xdf, 0x26, 0xac, 0xf8, 0x59, +- 0x2c, 0x8f, 0xab, 0x7b, 0x4c, 0x17, 0xc3, 0xe4, 0x97, 0xf2, 0x9b, 0x12, +- 0xd9, 0x30, 0x30, 0xce, 0x2c, 0x90, 0xb4, 0x43, 0x9f, 0x4f, 0xe3, 0x4f, +- 0xe8, 0xff, 0x7d, 0xea, 0x3c, 0x75, 0x05, 0xbc, 0xf1, 0x54, 0xbc, 0x35, +- 0x1f, 0x27, 0xae, 0x5f, 0xbb, 0xb3, 0x7b, 0x39, 0xbe, 0xf7, 0xbf, 0xf1, +- 0xd2, 0xb1, 0x7f, 0x1d, 0x9f, 0xd1, 0x3e, 0xb8, 0x3a, 0xcb, 0xda, 0xec, +- 0xff, 0x50, 0xf8, 0xdf, 0xec, 0x67, 0x4b, 0xc4, 0x76, 0xf6, 0x91, 0xb2, +- 0xf4, 0x6f, 0x57, 0xb1, 0x26, 0xf2, 0xb7, 0x82, 0x75, 0x3a, 0x96, 0x08, +- 0xec, 0x79, 0xa8, 0xeb, 0x6c, 0xbd, 0x1f, 0xc8, 0x3e, 0x62, 0xea, 0x0e, +- 0xc4, 0xda, 0xff, 0xbd, 0x61, 0x4c, 0x25, 0x13, 0xba, 0xab, 0x34, 0x2d, +- 0xe1, 0xb9, 0x31, 0x89, 0x1c, 0x63, 0xfc, 0x3a, 0x23, 0xc5, 0xb8, 0x27, +- 0xf7, 0xb9, 0xeb, 0x7d, 0x93, 0x2e, 0x63, 0x23, 0xed, 0x0f, 0xcb, 0xd0, +- 0xc9, 0x47, 0x25, 0x3a, 0xc7, 0x77, 0xeb, 0xce, 0x2e, 0xa0, 0x8f, 0xb6, +- 0x48, 0x39, 0xce, 0x18, 0x6e, 0x54, 0x9d, 0x05, 0x9f, 0x1f, 0x5f, 0x90, +- 0x22, 0xb0, 0x42, 0x5e, 0xe9, 0x16, 0xa4, 0xab, 0xbe, 0xc4, 0xf4, 0x76, +- 0xee, 0x29, 0xf8, 0x98, 0xa1, 0x89, 0x72, 0x54, 0xdd, 0xc9, 0x39, 0x1f, +- 0x67, 0x5d, 0xf8, 0xef, 0x73, 0xc4, 0x19, 0xd0, 0x1d, 0x63, 0x12, 0x62, +- 0x3e, 0x3c, 0xb7, 0x86, 0x33, 0xa8, 0x13, 0x86, 0xdc, 0xb8, 0x44, 0x4e, +- 0xf9, 0x73, 0xe7, 0x3f, 0x52, 0x32, 0x16, 0x76, 0x4b, 0xf8, 0x18, 0x9f, +- 0xeb, 0xfd, 0x21, 0x62, 0x77, 0xd8, 0x86, 0xb3, 0x9f, 0x45, 0x7f, 0x7c, +- 0x97, 0xd1, 0xdf, 0xc2, 0x22, 0x5f, 0xf9, 0xc7, 0xfe, 0xcf, 0x04, 0xca, +- 0xfe, 0xff, 0x07, 0x3b, 0x97, 0x22, 0x9a, 0xb0, 0x4e, 0x00, 0x00, 0x00 }; ++ 0xcd, 0x7c, 0x7f, 0x70, 0x5b, 0xd7, 0x95, 0xde, 0x79, 0x0f, 0x00, 0x09, ++ 0x91, 0x14, 0xf5, 0x44, 0xc3, 0x0c, 0xec, 0x30, 0x09, 0x1e, 0xf9, 0x48, ++ 0xc2, 0x26, 0x9d, 0x3c, 0x31, 0x8c, 0xc2, 0x64, 0x51, 0x1b, 0x06, 0x48, ++ 0x99, 0x4e, 0xc4, 0x2e, 0x6d, 0x33, 0x5e, 0x4d, 0xab, 0xa6, 0x28, 0x48, ++ 0x79, 0x1d, 0x8f, 0x33, 0xd1, 0x34, 0x6e, 0xab, 0xa4, 0x8e, 0x05, 0x81, ++ 0xb4, 0x23, 0x67, 0x21, 0x81, 0x91, 0x28, 0xc9, 0xed, 0x64, 0xba, 0x0c, ++ 0x48, 0x4a, 0x8e, 0x17, 0x12, 0xe4, 0x1f, 0x49, 0xbc, 0xd9, 0xd8, 0xe6, ++ 0x32, 0x8a, 0xec, 0xb8, 0xe9, 0x8e, 0x9d, 0x71, 0x3b, 0x9a, 0xae, 0xdb, ++ 0x6a, 0x14, 0xa7, 0x71, 0xd3, 0x6d, 0xeb, 0x6e, 0xf2, 0x87, 0x77, 0xeb, ++ 0xe4, 0xf5, 0xfb, 0xee, 0xbb, 0x8f, 0x04, 0x69, 0xda, 0xce, 0xee, 0x4e, ++ 0x67, 0xca, 0x19, 0xcc, 0x7d, 0xef, 0xbe, 0xfb, 0xf3, 0x9c, 0x73, 0xcf, ++ 0xf9, 0xce, 0xb9, 0xf7, 0x72, 0x58, 0xa4, 0x49, 0xf4, 0xdf, 0x56, 0xfc, ++ 0x3e, 0xf6, 0xf9, 0x2f, 0x4c, 0xba, 0x1f, 0x76, 0x3f, 0x8c, 0xc7, 0x7b, ++ 0x4c, 0x91, 0x08, 0xf3, 0x43, 0xf8, 0xc5, 0xf0, 0x1b, 0xd0, 0xcf, 0x9b, ++ 0xfd, 0x59, 0xf8, 0xed, 0x34, 0x44, 0x72, 0xbf, 0xd0, 0x95, 0xea, 0xfe, ++ 0xa2, 0xef, 0x50, 0xe7, 0xdd, 0xfe, 0xcc, 0xdf, 0xb2, 0x9c, 0xf5, 0xb7, ++ 0x68, 0xfb, 0xbd, 0xfe, 0x42, 0xba, 0xd9, 0xad, 0xfa, 0x27, 0x51, 0x33, ++ 0x25, 0x63, 0x19, 0x47, 0xa2, 0xa1, 0xd4, 0x5b, 0x63, 0x93, 0x8e, 0x48, ++ 0xba, 0xda, 0x97, 0xc8, 0xca, 0xaf, 0xbd, 0x42, 0x2c, 0x2c, 0xcc, 0xff, ++ 0x40, 0xea, 0xad, 0x83, 0xcf, 0x7c, 0xdc, 0x7e, 0x63, 0x3e, 0x24, 0x51, ++ 0x2b, 0x65, 0x19, 0x56, 0x8f, 0x44, 0x3b, 0x50, 0xe7, 0x1b, 0xbd, 0x31, ++ 0x53, 0x5a, 0x83, 0xb6, 0x5e, 0xf7, 0x9e, 0xe9, 0x8d, 0xc9, 0x73, 0x35, ++ 0x4b, 0xce, 0xd7, 0xa2, 0x46, 0xe6, 0x94, 0xec, 0xcf, 0xba, 0x92, 0x30, ++ 0x9d, 0x66, 0xc9, 0x5b, 0x46, 0x22, 0x9f, 0xfc, 0x88, 0xa4, 0x63, 0x36, ++ 0x7b, 0x4e, 0x9b, 0x4e, 0x37, 0xf2, 0xd4, 0x60, 0x72, 0xa6, 0xd3, 0x83, ++ 0x67, 0xe6, 0xcf, 0x81, 0x57, 0xa8, 0x5f, 0x16, 0x63, 0xbc, 0x77, 0x8b, ++ 0x98, 0xc7, 0xae, 0x95, 0xb4, 0x65, 0x48, 0xc8, 0xe1, 0xf8, 0x12, 0x92, ++ 0x29, 0xb5, 0xe3, 0xdd, 0x8e, 0x8b, 0xf4, 0x45, 0xfc, 0x3e, 0xa3, 0x12, ++ 0x3a, 0x29, 0xd1, 0x86, 0xd4, 0xb3, 0x63, 0x17, 0xe7, 0xe2, 0x12, 0x3e, ++ 0x9a, 0x90, 0x62, 0xb9, 0x45, 0x22, 0x27, 0xa5, 0x23, 0x24, 0xdd, 0xf1, ++ 0xbb, 0x50, 0x62, 0xb8, 0x1a, 0x96, 0x91, 0xaa, 0x21, 0x61, 0x27, 0x8a, ++ 0x39, 0xb5, 0xe0, 0x67, 0xe1, 0x17, 0xc3, 0x2f, 0x8e, 0xdf, 0x38, 0xda, ++ 0xe9, 0x90, 0x6c, 0x95, 0x6d, 0x1e, 0x47, 0xdf, 0xb6, 0x95, 0x93, 0x67, ++ 0x42, 0x7e, 0xdb, 0xfe, 0xbb, 0xc8, 0xa1, 0x6d, 0xfe, 0x3b, 0x9f, 0x39, ++ 0x36, 0xcc, 0xad, 0x1c, 0x95, 0xcb, 0xa1, 0xb8, 0x3c, 0xd3, 0x7b, 0x19, ++ 0xf3, 0xe5, 0x5c, 0xe3, 0x98, 0x73, 0x4c, 0x1e, 0xaf, 0x71, 0xdc, 0xcd, ++ 0x12, 0xc2, 0xb8, 0x4d, 0xf4, 0xb7, 0xfd, 0xe4, 0x3f, 0x94, 0x7c, 0xcc, ++ 0x4e, 0x8a, 0x18, 0xd2, 0x39, 0x80, 0xfe, 0x35, 0x2b, 0xcd, 0xa3, 0x31, ++ 0x8c, 0x7b, 0x65, 0xbb, 0x89, 0x1c, 0x13, 0xed, 0xfe, 0x03, 0xf9, 0x73, ++ 0xf4, 0x55, 0x90, 0xec, 0x62, 0x30, 0xcf, 0xa4, 0x2e, 0xbb, 0x3a, 0x4f, ++ 0xd0, 0xb2, 0xc5, 0xc8, 0x9e, 0x4a, 0xc8, 0x83, 0xe5, 0x1b, 0x25, 0xe3, ++ 0x7a, 0xde, 0xa4, 0x2b, 0x20, 0x7c, 0xb7, 0x95, 0xc5, 0xd7, 0x4a, 0x55, ++ 0x8c, 0x4c, 0x39, 0xa0, 0x43, 0x18, 0xef, 0xed, 0x28, 0xdb, 0x6a, 0x0c, ++ 0x9f, 0x02, 0xed, 0x53, 0xa4, 0x85, 0xe7, 0xcd, 0xb8, 0xdd, 0xf1, 0x29, ++ 0xd0, 0x6b, 0xa1, 0xda, 0xed, 0xae, 0x88, 0x85, 0xf6, 0xda, 0x50, 0x86, ++ 0x74, 0x61, 0x3b, 0x6c, 0x8f, 0x6d, 0xb5, 0xa0, 0x6e, 0x0c, 0xdf, 0x3c, ++ 0x2f, 0xe3, 0x5a, 0x78, 0x8e, 0xa3, 0xdd, 0x18, 0xd2, 0x66, 0x23, 0x73, ++ 0xdc, 0x43, 0xbf, 0x71, 0x3c, 0xfb, 0x34, 0x3b, 0x5d, 0xe5, 0x58, 0xd3, ++ 0x18, 0xab, 0xa1, 0xe4, 0xc3, 0xc0, 0x73, 0x67, 0x95, 0xf2, 0x33, 0x2c, ++ 0x93, 0x25, 0x13, 0xf3, 0x0d, 0x8b, 0x33, 0x60, 0xc8, 0xa4, 0xfa, 0x36, ++ 0x2c, 0x5d, 0xa0, 0x77, 0xc1, 0xea, 0x4b, 0x9a, 0xf2, 0xb4, 0x99, 0x01, ++ 0xfd, 0xb2, 0xe1, 0x04, 0xe8, 0xc0, 0x36, 0x72, 0x75, 0x6d, 0xe4, 0xd0, ++ 0xc6, 0xff, 0x01, 0x2d, 0x0c, 0x89, 0x38, 0xed, 0xa0, 0x11, 0x69, 0x57, ++ 0x30, 0x33, 0xb5, 0x30, 0xca, 0xce, 0x98, 0xd9, 0x33, 0x87, 0xf1, 0x2c, ++ 0x96, 0x99, 0x7a, 0x9a, 0x29, 0xea, 0xee, 0xad, 0xab, 0xbb, 0x17, 0x75, ++ 0xc1, 0x07, 0x8c, 0xf7, 0x71, 0xc5, 0x23, 0xdb, 0x9a, 0x17, 0xf2, 0x29, ++ 0xf1, 0x2e, 0x7c, 0x0a, 0x69, 0x3e, 0x7d, 0x9e, 0x7c, 0x4a, 0xbc, 0x37, ++ 0x9f, 0x32, 0xc6, 0x7a, 0x3e, 0x75, 0xff, 0x7f, 0xc2, 0xa7, 0x98, 0xcc, ++ 0x63, 0xee, 0xf3, 0xef, 0xc1, 0x1b, 0x13, 0x7c, 0xc8, 0x94, 0xc2, 0xd2, ++ 0x35, 0x10, 0xe4, 0x0f, 0x23, 0xff, 0x5a, 0xc9, 0x59, 0xe4, 0xd7, 0x7b, ++ 0xf1, 0xe5, 0x5f, 0x18, 0xe4, 0x4b, 0xd8, 0xe7, 0x4b, 0xe2, 0x6f, 0xc6, ++ 0x97, 0x03, 0xa8, 0x4b, 0xde, 0x5c, 0xc5, 0xf5, 0x8b, 0xba, 0x61, 0x23, ++ 0x5b, 0x4e, 0xe4, 0xcc, 0x54, 0x0c, 0x6b, 0x0f, 0xfa, 0xa5, 0xf4, 0x1b, ++ 0x23, 0xe4, 0x78, 0xa1, 0x8c, 0xdb, 0x2c, 0x59, 0xc5, 0x07, 0xd2, 0x69, ++ 0x19, 0x74, 0x7f, 0xcb, 0xcb, 0x80, 0x3f, 0x99, 0x7e, 0x9f, 0x03, 0x21, ++ 0x27, 0xfd, 0xa1, 0x10, 0xf5, 0x45, 0x2a, 0xf6, 0x39, 0xac, 0x59, 0x94, ++ 0x5b, 0xcf, 0xef, 0xc2, 0x2a, 0xbf, 0x05, 0xed, 0x8b, 0x61, 0x3a, 0x21, ++ 0xc9, 0x8f, 0xaf, 0x6c, 0x0f, 0x29, 0xdd, 0xc4, 0x34, 0xe0, 0x63, 0x41, ++ 0xd2, 0x8b, 0x2c, 0xab, 0x74, 0x91, 0xe4, 0x8f, 0xf3, 0x19, 0x33, 0xaa, ++ 0x05, 0x79, 0xab, 0xdf, 0x0c, 0xca, 0x47, 0x31, 0x26, 0x5a, 0x47, 0xbe, ++ 0x55, 0x37, 0xaf, 0xb7, 0x30, 0xaf, 0x3f, 0xc4, 0xbc, 0x12, 0x52, 0x71, ++ 0xf9, 0x6d, 0xa6, 0xee, 0xdb, 0x0c, 0xbe, 0x31, 0x9f, 0xb2, 0x64, 0xc9, ++ 0x82, 0xfa, 0x0e, 0xd9, 0x58, 0xfd, 0x1e, 0x35, 0x3a, 0xab, 0x7e, 0x9f, ++ 0xec, 0x2b, 0x67, 0x05, 0xed, 0x87, 0xeb, 0xca, 0x84, 0xeb, 0xca, 0x28, ++ 0xfd, 0x5c, 0xf7, 0x4d, 0xea, 0xbe, 0xbd, 0xae, 0x64, 0xfb, 0x39, 0xc8, ++ 0xf4, 0x70, 0x6f, 0x54, 0xa6, 0x21, 0x57, 0x79, 0xf7, 0xfd, 0x6a, 0xa6, ++ 0x77, 0xb9, 0x3e, 0x4f, 0x6f, 0x0e, 0x73, 0x3d, 0x6d, 0xc6, 0xd3, 0xff, ++ 0x8e, 0xf1, 0xa3, 0x6e, 0x19, 0x7a, 0x13, 0xba, 0x75, 0x7a, 0x6e, 0x6d, ++ 0xbd, 0x15, 0x4b, 0xbf, 0x0d, 0x5f, 0x83, 0xfa, 0x0d, 0xb2, 0x6c, 0xd9, ++ 0xc9, 0x1c, 0xe8, 0x35, 0x5c, 0x2e, 0x1b, 0xfe, 0x5a, 0xf8, 0x85, 0xe1, ++ 0xaf, 0x63, 0xd0, 0xaf, 0x4c, 0x7e, 0x37, 0x4a, 0x76, 0x9c, 0xed, 0xd7, ++ 0x97, 0xc1, 0x7c, 0x31, 0xbe, 0x62, 0x8d, 0xf9, 0x6c, 0x27, 0x58, 0xb3, ++ 0xd4, 0xad, 0xec, 0xef, 0x30, 0xfa, 0x03, 0x2f, 0x7b, 0x5b, 0x64, 0xdf, ++ 0x5c, 0xd0, 0xef, 0x61, 0xb5, 0xce, 0xa7, 0x4a, 0xb6, 0x35, 0x02, 0x86, ++ 0x8e, 0xcc, 0x0e, 0xc9, 0x70, 0xad, 0x43, 0xf2, 0xa5, 0x37, 0x3d, 0xd8, ++ 0x89, 0x0f, 0x47, 0xc4, 0xc1, 0xfa, 0x80, 0x4c, 0x0d, 0xa6, 0x24, 0x53, ++ 0x8b, 0x88, 0x99, 0x72, 0x91, 0xd6, 0xdb, 0xbe, 0x70, 0x78, 0x64, 0xdd, ++ 0x7b, 0x03, 0xca, 0xa0, 0xed, 0xc1, 0x8d, 0xe5, 0x44, 0x32, 0x90, 0xab, ++ 0x8c, 0xfb, 0x6b, 0x2f, 0x6d, 0x05, 0x32, 0xc1, 0x5c, 0xea, 0x92, 0xb8, ++ 0x3c, 0x51, 0xb3, 0x72, 0xa1, 0x54, 0x87, 0xd6, 0x27, 0xd4, 0x2d, 0x32, ++ 0x3e, 0x55, 0x3a, 0xe8, 0x99, 0x8e, 0x14, 0xae, 0x4d, 0x39, 0x89, 0xa2, ++ 0xb4, 0x0c, 0xcd, 0x0c, 0x7e, 0x1c, 0xfa, 0x05, 0xf9, 0x58, 0x7b, 0x6d, ++ 0xa9, 0xa1, 0xb1, 0xdb, 0x7b, 0x20, 0xcb, 0xb5, 0x42, 0x8b, 0xe9, 0x38, ++ 0x48, 0xa3, 0x85, 0xf7, 0xa7, 0xa8, 0x0b, 0xfa, 0x1b, 0x2e, 0x3a, 0xb6, ++ 0x95, 0x36, 0x3b, 0xb0, 0xb6, 0xb0, 0xfe, 0x61, 0x7b, 0x77, 0x55, 0x7f, ++ 0xed, 0x1d, 0x0a, 0xfb, 0x76, 0xd7, 0x4c, 0xdd, 0x6b, 0xe8, 0x35, 0x3c, ++ 0xe6, 0xaf, 0xe1, 0x70, 0x58, 0xaf, 0x5d, 0xfd, 0xfe, 0x74, 0xa3, 0xa6, ++ 0x8b, 0x7e, 0xdf, 0x6b, 0xfa, 0x76, 0x7c, 0xb0, 0x81, 0xba, 0x37, 0x9c, ++ 0xba, 0xdc, 0x80, 0x36, 0xa3, 0x91, 0xd4, 0xf8, 0xef, 0x2c, 0xa9, 0x72, ++ 0xf3, 0xba, 0xdc, 0xaf, 0x22, 0x5a, 0x56, 0xc7, 0x7a, 0xaa, 0x4c, 0xe7, ++ 0xc6, 0xba, 0x55, 0xfa, 0x8d, 0xb1, 0x2e, 0x95, 0x2e, 0x8e, 0x39, 0x2a, ++ 0x7d, 0x54, 0x95, 0x37, 0x52, 0x29, 0x9d, 0x3f, 0x3a, 0x96, 0x50, 0xe9, ++ 0x6e, 0x9d, 0x8e, 0xeb, 0x74, 0x42, 0xa7, 0x7b, 0x74, 0xba, 0x57, 0xa7, ++ 0x39, 0x9d, 0x4e, 0xe9, 0xf6, 0xee, 0xd6, 0xef, 0xf7, 0xea, 0x74, 0xbf, ++ 0x4e, 0xef, 0xd3, 0xe9, 0x01, 0x9d, 0xde, 0xaf, 0xc7, 0x55, 0xd0, 0x69, ++ 0x49, 0xe7, 0xcf, 0xea, 0x71, 0x3e, 0x82, 0xf1, 0xfc, 0x49, 0x83, 0x2f, ++ 0x47, 0x10, 0xda, 0xd4, 0x7e, 0xf0, 0x10, 0x3c, 0x2b, 0xc5, 0x20, 0x4f, ++ 0x9c, 0x7f, 0x02, 0x76, 0x28, 0x4c, 0xd9, 0x93, 0xac, 0xc5, 0xef, 0xbf, ++ 0x0c, 0x4b, 0x6b, 0x58, 0xa6, 0x6b, 0x7e, 0xd9, 0x5d, 0x83, 0x2c, 0x33, ++ 0x8f, 0x32, 0xa4, 0xc5, 0xa2, 0xd2, 0x8b, 0x59, 0x2b, 0x26, 0x33, 0x65, ++ 0x35, 0x77, 0xd8, 0xab, 0x7f, 0x23, 0xd9, 0x33, 0x22, 0x2f, 0x96, 0x58, ++ 0xee, 0xfb, 0xba, 0xdc, 0xd3, 0x28, 0xd7, 0x95, 0x18, 0x36, 0x6c, 0xe8, ++ 0x68, 0x3b, 0x0d, 0xbd, 0x9f, 0x40, 0x6a, 0x8d, 0xe2, 0x37, 0x4c, 0xe5, ++ 0x8f, 0x72, 0x3e, 0x8d, 0x9e, 0xa6, 0xbe, 0x95, 0xdb, 0x20, 0xf3, 0x9d, ++ 0x03, 0xaf, 0x42, 0x7e, 0x62, 0xf2, 0x35, 0xc8, 0xd6, 0xc5, 0x12, 0xf9, ++ 0xf0, 0x7d, 0x59, 0x2a, 0x91, 0x2f, 0x4f, 0xcb, 0x4c, 0xa9, 0xcb, 0x7d, ++ 0x51, 0xec, 0xe4, 0x69, 0x85, 0x2d, 0xfa, 0x5c, 0xa4, 0x90, 0x1b, 0x3b, ++ 0xf1, 0x10, 0xec, 0x50, 0xef, 0x80, 0xdf, 0x5e, 0xb7, 0x6e, 0xcf, 0xa9, ++ 0x7e, 0x48, 0x2e, 0x2b, 0x3d, 0x4d, 0xdd, 0x08, 0xdb, 0x53, 0xe3, 0xda, ++ 0x79, 0x14, 0x29, 0x6d, 0xf3, 0x61, 0xac, 0x27, 0x4f, 0xc6, 0xdd, 0x0f, ++ 0x88, 0xf9, 0xe1, 0xb0, 0xa4, 0x27, 0x0a, 0xd0, 0x3a, 0x7f, 0x80, 0xbc, ++ 0x1f, 0x9a, 0x3e, 0xf6, 0xb5, 0xad, 0xdb, 0x29, 0xcf, 0xa5, 0x2d, 0x6f, ++ 0xa6, 0x15, 0xb9, 0x22, 0xb4, 0x5b, 0x69, 0xea, 0x9b, 0x35, 0x3d, 0xcc, ++ 0xf7, 0x21, 0xc3, 0x5f, 0xe7, 0x83, 0x75, 0xeb, 0x7c, 0x10, 0x73, 0x61, ++ 0xbf, 0xad, 0xa8, 0x13, 0x46, 0x9a, 0x46, 0xbf, 0xec, 0x8f, 0x63, 0xf8, ++ 0xb4, 0xc6, 0x4a, 0xac, 0x7b, 0x40, 0xd7, 0x1d, 0xaa, 0xab, 0x3b, 0x84, ++ 0xba, 0xac, 0xf3, 0x08, 0x68, 0x40, 0xba, 0x17, 0xea, 0xea, 0x16, 0xa8, ++ 0xa3, 0xb7, 0x99, 0x4e, 0x04, 0xb6, 0x97, 0x4d, 0x1c, 0xc6, 0xb7, 0x6f, ++ 0x48, 0xe6, 0xcc, 0x5f, 0x73, 0xcc, 0x68, 0x8f, 0x7a, 0x79, 0x1c, 0x3a, ++ 0x9f, 0xb8, 0x03, 0x76, 0x29, 0xc6, 0xbc, 0x1b, 0x74, 0x7f, 0x9c, 0x23, ++ 0xdf, 0xb7, 0xb6, 0xae, 0xf5, 0xff, 0xb4, 0xee, 0x3f, 0x55, 0xd7, 0x7f, ++ 0x0a, 0xfd, 0x7f, 0x99, 0xed, 0xa1, 0x6f, 0x99, 0xf5, 0xd7, 0x79, 0x37, ++ 0x68, 0x9c, 0x80, 0xce, 0xc0, 0x18, 0xca, 0xbf, 0xf1, 0xd2, 0x61, 0x5f, ++ 0x07, 0x6b, 0x3d, 0x5b, 0x58, 0x2b, 0xe3, 0xdb, 0x92, 0xe1, 0xda, 0x65, ++ 0x85, 0x69, 0xfd, 0x35, 0x6e, 0x1f, 0x2e, 0xd0, 0xe6, 0xd4, 0xcc, 0x10, ++ 0xe9, 0x7d, 0xde, 0xfd, 0x0a, 0xc6, 0x68, 0x27, 0x12, 0x66, 0x77, 0xc1, ++ 0x34, 0xbf, 0x22, 0xfb, 0x17, 0xee, 0x93, 0xfd, 0x65, 0xb6, 0xd1, 0x8c, ++ 0xef, 0x0e, 0xf2, 0xb6, 0x88, 0xb4, 0xd3, 0x46, 0xbd, 0x69, 0xf8, 0x7d, ++ 0x99, 0xd0, 0x07, 0xcb, 0xc6, 0x6d, 0xb5, 0x0b, 0x46, 0x66, 0x81, 0x7a, ++ 0x15, 0xf9, 0xb5, 0x7a, 0x1b, 0x16, 0xd8, 0xaf, 0x40, 0xa7, 0xcf, 0x10, ++ 0x43, 0x9b, 0x19, 0x37, 0xa2, 0xed, 0x66, 0xc6, 0xf2, 0xe7, 0x7b, 0x73, ++ 0xc8, 0xb7, 0xc5, 0xa4, 0xd9, 0x16, 0x49, 0x87, 0xa9, 0x3b, 0xf9, 0x2c, ++ 0x5e, 0x28, 0x45, 0xfd, 0x27, 0xe1, 0x50, 0x2a, 0x04, 0x9a, 0xb1, 0xcc, ++ 0x8d, 0x18, 0xa3, 0xaf, 0x5b, 0x0b, 0xab, 0xba, 0xd5, 0xc0, 0x38, 0x3a, ++ 0x25, 0xb7, 0xd0, 0x2e, 0xf9, 0x33, 0x69, 0xe8, 0x63, 0x2b, 0xe4, 0xeb, ++ 0xea, 0x7a, 0xfc, 0x4e, 0xfa, 0x7b, 0x32, 0xec, 0x26, 0x64, 0x7a, 0xc8, ++ 0x95, 0xe2, 0x50, 0x5f, 0x3c, 0x24, 0x7d, 0x90, 0x40, 0x27, 0x9e, 0x87, ++ 0xff, 0x90, 0xb3, 0xc6, 0xd1, 0x46, 0x1e, 0xb6, 0x91, 0x98, 0x78, 0x54, ++ 0xe3, 0x43, 0xcf, 0xcb, 0x92, 0x9f, 0xfd, 0x7b, 0x85, 0x32, 0xff, 0x5c, ++ 0xb9, 0x80, 0x86, 0xb9, 0x7e, 0x5e, 0xd8, 0x3d, 0x09, 0x1d, 0x97, 0x55, ++ 0x32, 0x08, 0x9b, 0xe8, 0xa3, 0x2b, 0xd0, 0x88, 0x7d, 0xb7, 0x80, 0x66, ++ 0xc3, 0x18, 0x3b, 0x68, 0xd3, 0xce, 0x71, 0xb5, 0x48, 0xbe, 0xd6, 0xac, ++ 0xbf, 0x31, 0x3f, 0x2c, 0xe3, 0xb1, 0x00, 0x77, 0x3f, 0xbd, 0x8d, 0x38, ++ 0xe2, 0x19, 0xd8, 0x83, 0x7c, 0xf9, 0xc9, 0x90, 0x2f, 0xdb, 0x96, 0xe4, ++ 0x4f, 0x0d, 0x43, 0x96, 0x88, 0x85, 0xb6, 0x68, 0x59, 0x62, 0x3b, 0x96, ++ 0x9a, 0x1b, 0x68, 0xa2, 0x6d, 0xd8, 0x10, 0xd2, 0xef, 0x85, 0x7c, 0xff, ++ 0x82, 0x75, 0x82, 0xfa, 0xc1, 0x38, 0xda, 0x56, 0xdb, 0x19, 0x77, 0x81, ++ 0x35, 0xd4, 0x58, 0x90, 0x77, 0x66, 0xfd, 0x58, 0xcc, 0xf6, 0x60, 0x2c, ++ 0xb0, 0x3e, 0x6a, 0x2c, 0x6d, 0x75, 0x6d, 0xc5, 0xea, 0xc6, 0xd2, 0x80, ++ 0xb1, 0xb0, 0xac, 0x3f, 0x96, 0xf3, 0xe0, 0x71, 0xfe, 0xcc, 0x95, 0x36, ++ 0xbf, 0x4e, 0xac, 0xae, 0x4e, 0xfb, 0x86, 0x3a, 0x2c, 0x1f, 0xf4, 0x41, ++ 0xfe, 0x3c, 0xd6, 0xec, 0xd7, 0x61, 0xb9, 0x06, 0xf8, 0x4f, 0xca, 0x3f, ++ 0x8a, 0x2a, 0x7d, 0xb7, 0x2a, 0xe7, 0xfb, 0x21, 0xe7, 0xf5, 0x7e, 0xc9, ++ 0x3a, 0x3e, 0x1a, 0xe3, 0x65, 0xf2, 0x72, 0x8b, 0x91, 0x55, 0xfc, 0xfc, ++ 0x10, 0xda, 0x5f, 0x82, 0xbf, 0x95, 0x90, 0x7c, 0x12, 0x3e, 0x90, 0x35, ++ 0x84, 0xf7, 0x26, 0x3c, 0xc3, 0x37, 0xb2, 0x9a, 0x15, 0x1e, 0xce, 0x27, ++ 0xfb, 0x35, 0xae, 0xfd, 0x99, 0xe4, 0x20, 0xb3, 0xf9, 0x24, 0xfc, 0x91, ++ 0x18, 0xec, 0xa4, 0xf2, 0xd3, 0xd8, 0xff, 0x77, 0xc3, 0xb4, 0xfb, 0xe7, ++ 0xcb, 0x9f, 0xc5, 0x3b, 0x7c, 0xbb, 0xe4, 0xab, 0x7a, 0x5c, 0xad, 0x28, ++ 0xf3, 0x45, 0xe4, 0xf1, 0x1b, 0xcb, 0xb0, 0x8d, 0x65, 0xbc, 0x7f, 0x02, ++ 0x65, 0xb0, 0xa8, 0x21, 0x81, 0xa6, 0xb3, 0x13, 0xbf, 0x17, 0x91, 0xf7, ++ 0x71, 0xe4, 0x3d, 0x85, 0xbc, 0x8f, 0xe1, 0xfd, 0x4f, 0x37, 0xb4, 0xdb, ++ 0x87, 0xf7, 0x43, 0xf8, 0x8e, 0xf9, 0x5a, 0x2f, 0xe0, 0xfb, 0x27, 0xf0, ++ 0x7b, 0x6a, 0x43, 0x99, 0x7f, 0xb5, 0xe1, 0x3d, 0xc0, 0xe4, 0x7f, 0xac, ++ 0x65, 0x2f, 0xc0, 0xe4, 0xbe, 0xbe, 0x9c, 0x2e, 0xb7, 0x18, 0x23, 0xa7, ++ 0xa2, 0xc6, 0xae, 0x53, 0xa0, 0x45, 0x35, 0xac, 0x70, 0x78, 0x18, 0x38, ++ 0x7c, 0x66, 0x4e, 0xfa, 0x23, 0xd0, 0x27, 0x79, 0xe5, 0xeb, 0xc8, 0x60, ++ 0x83, 0x74, 0xbb, 0x17, 0xb0, 0x4e, 0xf2, 0xd5, 0x0e, 0xbc, 0x73, 0xfd, ++ 0x40, 0xd6, 0xaa, 0x4d, 0x90, 0xef, 0xee, 0x64, 0x05, 0xb2, 0xb6, 0x0f, ++ 0x58, 0x3b, 0x07, 0xfc, 0x91, 0xab, 0x76, 0xc8, 0x5d, 0xd5, 0x23, 0x61, ++ 0xed, 0xaf, 0xea, 0xbe, 0xff, 0xf5, 0x86, 0xbe, 0xa3, 0xc4, 0xf6, 0x90, ++ 0xff, 0x67, 0xc7, 0x26, 0xe7, 0xd8, 0xbf, 0xd9, 0x09, 0x23, 0x84, 0x31, ++ 0xd0, 0x4f, 0x95, 0x9e, 0xb0, 0x74, 0x27, 0xa6, 0x85, 0xfd, 0x17, 0x24, ++ 0x94, 0xea, 0x86, 0x1d, 0x50, 0xef, 0xf0, 0x4b, 0xa1, 0xdf, 0xaa, 0x6b, ++ 0xfe, 0xea, 0xc8, 0xaa, 0xbf, 0xda, 0x01, 0x7f, 0x16, 0x86, 0x4a, 0xad, ++ 0xfd, 0x16, 0xe8, 0x86, 0xab, 0x41, 0x77, 0x5f, 0x9f, 0x73, 0x8d, 0x67, ++ 0xdc, 0xed, 0xfa, 0x9d, 0x32, 0x0d, 0x7d, 0x61, 0x46, 0x94, 0x7e, 0x12, ++ 0x13, 0xdf, 0x06, 0x29, 0xc7, 0x78, 0x5f, 0xa0, 0x2c, 0x24, 0xb4, 0x5e, ++ 0xfd, 0x3c, 0x6c, 0x1e, 0xbf, 0x07, 0xf2, 0xb6, 0xc7, 0xf2, 0x65, 0x8d, ++ 0x78, 0xf9, 0x3b, 0x1b, 0xe6, 0x36, 0xb9, 0x61, 0x6e, 0xe1, 0x55, 0xba, ++ 0x72, 0x8e, 0x11, 0xcc, 0x71, 0x69, 0x8e, 0xb4, 0xed, 0x87, 0x9c, 0x8a, ++ 0x13, 0x16, 0xca, 0x33, 0xf5, 0x68, 0x2b, 0x74, 0x33, 0x69, 0x17, 0x96, ++ 0x29, 0xcc, 0x29, 0x87, 0x39, 0xe5, 0x30, 0xa7, 0x5c, 0x1d, 0x1d, 0xf7, ++ 0xad, 0xce, 0x29, 0x18, 0x37, 0xca, 0xa9, 0x75, 0xc7, 0x67, 0x35, 0x7e, ++ 0x3c, 0x07, 0x18, 0x96, 0x63, 0x49, 0x6f, 0x18, 0x0b, 0x69, 0xc1, 0xb1, ++ 0xac, 0x8e, 0x23, 0xc6, 0xe8, 0xca, 0xfe, 0x2a, 0xf9, 0xca, 0x3e, 0x77, ++ 0xcb, 0x54, 0xf9, 0x43, 0x7a, 0x1c, 0x2d, 0x18, 0xc7, 0x38, 0xf4, 0x07, ++ 0xfb, 0x83, 0x1e, 0xa8, 0x4e, 0xe0, 0x39, 0x46, 0xfe, 0xeb, 0xb1, 0x04, ++ 0xb4, 0x80, 0x2f, 0xa5, 0x68, 0x81, 0xee, 0x9d, 0x6e, 0x29, 0x8e, 0x33, ++ 0xaf, 0xb2, 0xcd, 0x1f, 0x53, 0x42, 0xf7, 0xef, 0xd3, 0x16, 0xbe, 0x07, ++ 0xf1, 0xab, 0xd6, 0x07, 0xf5, 0xf4, 0x8c, 0x37, 0x68, 0x7d, 0x05, 0xde, ++ 0xd7, 0xe7, 0x0f, 0x35, 0xac, 0x95, 0xe5, 0xfb, 0x3f, 0xd2, 0xef, 0x5b, ++ 0x8d, 0x91, 0xe3, 0x41, 0xde, 0x99, 0x86, 0xb7, 0xb7, 0x37, 0xdd, 0x10, ++ 0xe8, 0x8f, 0xf5, 0x71, 0x88, 0x03, 0xe6, 0x9a, 0x7d, 0x29, 0xc8, 0xcc, ++ 0x60, 0xda, 0x1c, 0xae, 0x0d, 0x9b, 0xbe, 0x8d, 0x61, 0x99, 0x03, 0x0a, ++ 0xbf, 0x87, 0x53, 0x2f, 0x52, 0xde, 0x41, 0xc3, 0x57, 0xc6, 0x32, 0x25, ++ 0xcf, 0x9b, 0x76, 0x97, 0xa1, 0xd3, 0xa9, 0x97, 0x89, 0x95, 0x99, 0xff, ++ 0x12, 0xf2, 0x61, 0xbf, 0x6b, 0xd0, 0xed, 0xa8, 0xb7, 0x39, 0x26, 0x4e, ++ 0x68, 0x4c, 0xec, 0x83, 0xe9, 0x8c, 0xc2, 0x4b, 0xcb, 0xc0, 0x88, 0x61, ++ 0xfd, 0x7c, 0x61, 0x8c, 0xbe, 0x4f, 0x1d, 0xee, 0x46, 0xbb, 0x2f, 0x8c, ++ 0x65, 0xe6, 0xb8, 0x0e, 0x7e, 0x8c, 0x75, 0x40, 0x1e, 0xfd, 0x19, 0x78, ++ 0x64, 0xc8, 0x8c, 0xb2, 0x09, 0x1c, 0x07, 0xeb, 0xbd, 0x30, 0xd6, 0xb9, ++ 0xc8, 0xf4, 0xc5, 0x31, 0x67, 0x31, 0x24, 0xfb, 0xb4, 0xcf, 0xc5, 0xf7, ++ 0xc4, 0x62, 0x60, 0x9f, 0x9b, 0x24, 0x92, 0xa2, 0x6e, 0xb3, 0x93, 0xd0, ++ 0xbe, 0x98, 0xcf, 0xf9, 0xb1, 0x19, 0x87, 0x76, 0xf2, 0xdb, 0x90, 0x83, ++ 0x26, 0x69, 0x50, 0xf2, 0xf1, 0x84, 0xee, 0xeb, 0xcf, 0xd0, 0xd7, 0x36, ++ 0x8c, 0x35, 0x04, 0x1d, 0x19, 0x8e, 0xa3, 0x9f, 0x83, 0xa6, 0xd3, 0x87, ++ 0xfe, 0xe8, 0x4b, 0x76, 0x00, 0x07, 0x2a, 0x9f, 0x30, 0xac, 0x75, 0x04, ++ 0xea, 0x7d, 0x0f, 0xf5, 0x68, 0x27, 0x49, 0x4f, 0xf6, 0x57, 0x01, 0x16, ++ 0x69, 0xc2, 0x3c, 0x6c, 0x2b, 0x13, 0x6a, 0x90, 0xec, 0x5c, 0x50, 0x86, ++ 0x63, 0xfa, 0xce, 0x58, 0xd7, 0x62, 0x17, 0xda, 0xea, 0xa0, 0xcc, 0x41, ++ 0xd6, 0x42, 0xf8, 0xb1, 0x6d, 0xd6, 0x83, 0x4e, 0x1e, 0x0a, 0xec, 0xf7, ++ 0x5a, 0xfd, 0xa0, 0x5e, 0xe7, 0xe2, 0x36, 0x2d, 0xb3, 0x7f, 0xe5, 0xa5, ++ 0x27, 0xf8, 0x9d, 0x7d, 0xd6, 0xeb, 0x6d, 0xd6, 0x0b, 0xca, 0x84, 0xb4, ++ 0x1e, 0xfe, 0x40, 0x64, 0x6d, 0x9c, 0xcb, 0xe0, 0x11, 0xeb, 0x48, 0x38, ++ 0xdb, 0x3b, 0xa4, 0xf9, 0x76, 0x01, 0x79, 0xbe, 0xac, 0x4e, 0xd7, 0xea, ++ 0xfd, 0x1e, 0xbf, 0xdd, 0x02, 0x30, 0x46, 0x11, 0x3e, 0x5a, 0x28, 0x95, ++ 0xde, 0xee, 0xc7, 0x22, 0xde, 0xcd, 0xd7, 0x01, 0x4f, 0xd1, 0x4e, 0x71, ++ 0xb5, 0x2e, 0x7d, 0x94, 0x0b, 0x63, 0x17, 0xd1, 0xfe, 0x83, 0x65, 0x7f, ++ 0x8d, 0xf9, 0x74, 0x20, 0x2e, 0x32, 0x64, 0xc9, 0x01, 0xce, 0x76, 0x68, ++ 0x87, 0x12, 0xf2, 0xbc, 0x13, 0xe0, 0x24, 0x62, 0x24, 0x94, 0xaf, 0x71, ++ 0x3c, 0x9c, 0xf7, 0xf7, 0x30, 0x6f, 0x4f, 0x66, 0x5d, 0x5f, 0x3e, 0x7a, ++ 0xb1, 0x26, 0xff, 0x34, 0x6c, 0x1f, 0xa6, 0xef, 0x75, 0x39, 0x5c, 0x3f, ++ 0xaf, 0xc0, 0x9e, 0x2d, 0x6b, 0x1f, 0xe5, 0x7b, 0x9a, 0x97, 0x2f, 0x80, ++ 0x97, 0x7d, 0x09, 0x4b, 0x7a, 0x30, 0x76, 0x94, 0xe9, 0xef, 0x06, 0xde, ++ 0x86, 0x8e, 0x8c, 0xc5, 0x31, 0x1e, 0x0b, 0x32, 0xbf, 0x4d, 0xdb, 0xfd, ++ 0x9b, 0x23, 0xd4, 0x13, 0xdb, 0x95, 0xff, 0xf3, 0x3d, 0x25, 0x6b, 0xbe, ++ 0xec, 0x85, 0xf4, 0xf7, 0x80, 0xdf, 0x21, 0x9a, 0x5d, 0x59, 0x8b, 0xdb, ++ 0x04, 0x3a, 0x9a, 0xe5, 0xbf, 0x8f, 0xf2, 0x8c, 0x5b, 0x79, 0xde, 0x94, ++ 0x1a, 0xef, 0xb3, 0xe0, 0x75, 0x68, 0x35, 0x06, 0xc0, 0xf7, 0xc4, 0x62, ++ 0x83, 0x48, 0x5b, 0xbd, 0xdc, 0x50, 0x56, 0x16, 0x22, 0x8c, 0x17, 0x26, ++ 0xcc, 0x80, 0x77, 0x61, 0x62, 0x36, 0xbc, 0x07, 0xbc, 0xe3, 0xf3, 0x66, ++ 0x58, 0x8f, 0x31, 0x1f, 0xcf, 0x5b, 0x72, 0x19, 0x83, 0x6c, 0x94, 0x82, ++ 0xe5, 0xe3, 0x97, 0xa2, 0x4b, 0x39, 0xcd, 0x24, 0xc2, 0x62, 0xc7, 0xf7, ++ 0xc9, 0x1f, 0xa1, 0xed, 0x74, 0x32, 0xa2, 0xe3, 0x12, 0x39, 0xa1, 0xbf, ++ 0xed, 0x79, 0x17, 0xe1, 0x2b, 0x56, 0xa0, 0x3a, 0xe1, 0xd7, 0x49, 0xb1, ++ 0x8a, 0x35, 0xd0, 0x14, 0xc6, 0x9a, 0x5a, 0x8b, 0x2b, 0xcc, 0xa3, 0xcc, ++ 0x02, 0xbe, 0x3d, 0x54, 0x0d, 0xb8, 0xec, 0xc1, 0x3f, 0xf5, 0xbc, 0x49, ++ 0xe7, 0xaf, 0xbd, 0x7c, 0xac, 0xbe, 0x6c, 0x80, 0xbb, 0x88, 0x99, 0x88, ++ 0x79, 0x88, 0x55, 0xf8, 0x8d, 0xf8, 0xe3, 0x20, 0xc6, 0x42, 0x19, 0x6e, ++ 0x95, 0x68, 0xca, 0x8e, 0x8f, 0x4a, 0xa0, 0x83, 0x2f, 0x81, 0xff, 0x05, ++ 0xaf, 0xd1, 0xe9, 0x90, 0x27, 0x6b, 0xf4, 0x87, 0x03, 0xde, 0x27, 0xc0, ++ 0x7b, 0xbb, 0x50, 0x10, 0x4f, 0x1e, 0x77, 0x9d, 0xc4, 0x57, 0x91, 0xfe, ++ 0xc4, 0xfd, 0x08, 0x69, 0xf1, 0x08, 0x4c, 0x1d, 0xf0, 0x34, 0x6c, 0xc4, ++ 0x6c, 0x80, 0xeb, 0x5b, 0x89, 0xeb, 0x35, 0x1d, 0x2f, 0xa3, 0x4d, 0xdb, ++ 0x32, 0x01, 0x96, 0x6e, 0x41, 0x39, 0x5f, 0xae, 0x83, 0xbc, 0x83, 0x28, ++ 0xcb, 0x31, 0xd0, 0xd7, 0x7a, 0x05, 0x6b, 0xc9, 0xf3, 0xee, 0x70, 0xfb, ++ 0xea, 0xd6, 0xc4, 0xb3, 0xe0, 0x81, 0x92, 0xcd, 0xc1, 0xed, 0xc2, 0xb8, ++ 0x99, 0xf4, 0xb7, 0x29, 0x9f, 0x80, 0xcf, 0x90, 0xd1, 0x41, 0xda, 0x02, ++ 0x8c, 0x0b, 0xf8, 0x8d, 0x36, 0xe7, 0x09, 0xd0, 0xfe, 0x8b, 0x55, 0xf2, ++ 0xa1, 0x45, 0xe9, 0xfc, 0x27, 0xcb, 0xb4, 0xeb, 0x3e, 0x46, 0xcb, 0xa9, ++ 0x58, 0x31, 0x6d, 0x41, 0x12, 0xbc, 0xa1, 0x0d, 0xa0, 0x9d, 0x67, 0x5d, ++ 0x96, 0x63, 0xdd, 0x7a, 0xfe, 0xb1, 0xcc, 0x36, 0xe0, 0x2a, 0xca, 0x60, ++ 0x2b, 0xf0, 0xc8, 0x76, 0xd9, 0x97, 0x6c, 0x04, 0xdd, 0xdb, 0x14, 0x8e, ++ 0x32, 0x9d, 0x4f, 0xc2, 0x66, 0x35, 0x30, 0xb6, 0xed, 0xae, 0xf9, 0x18, ++ 0x1f, 0x43, 0xde, 0x5b, 0xa0, 0x3f, 0xf3, 0x5e, 0x8a, 0xf8, 0x18, 0xe9, ++ 0x3e, 0xac, 0xbf, 0xf9, 0x6d, 0x19, 0xc5, 0x0f, 0xf2, 0x21, 0xd0, 0x03, ++ 0x81, 0xdd, 0xb3, 0x34, 0x8e, 0x24, 0x6f, 0x02, 0xfc, 0xce, 0xb2, 0xc4, ++ 0xf0, 0xf5, 0xfe, 0x09, 0xd7, 0x9d, 0xe7, 0x3d, 0xee, 0x2a, 0x3b, 0x0a, ++ 0x1e, 0xdc, 0x04, 0x5b, 0x1f, 0xd6, 0xb4, 0x6e, 0xf1, 0x63, 0x6b, 0xb0, ++ 0xad, 0x89, 0x36, 0xe8, 0x1d, 0xe7, 0x47, 0x9a, 0x7e, 0xc4, 0x08, 0xbf, ++ 0xf1, 0x42, 0x0e, 0xfd, 0x06, 0xe2, 0x03, 0x8e, 0x1d, 0xf5, 0x16, 0x58, ++ 0x96, 0x36, 0xf8, 0x10, 0xfa, 0x08, 0x49, 0xa2, 0x9d, 0xef, 0x37, 0x68, ++ 0x7f, 0x9b, 0xcf, 0x9e, 0xf4, 0x0c, 0xd4, 0xcb, 0xf3, 0x10, 0xc6, 0xc9, ++ 0xf9, 0x04, 0xf1, 0xd6, 0x0e, 0xa5, 0x03, 0xd6, 0xe4, 0x22, 0x18, 0x53, ++ 0xd0, 0x2f, 0xc7, 0x16, 0x97, 0x36, 0x8c, 0xed, 0x36, 0xe8, 0xe8, 0x81, ++ 0x36, 0xb6, 0x19, 0xf4, 0x5d, 0x3f, 0xa6, 0x00, 0xb7, 0xf8, 0x76, 0x37, ++ 0xe2, 0x34, 0xca, 0x40, 0x3b, 0x69, 0xd7, 0xa1, 0x74, 0xf5, 0x1a, 0x3f, ++ 0x68, 0x7f, 0xd9, 0xf7, 0xc6, 0xfc, 0x4f, 0xd4, 0x8d, 0xeb, 0x75, 0x1d, ++ 0x07, 0x26, 0x36, 0x26, 0x66, 0xd8, 0x89, 0x6f, 0x1c, 0x13, 0x9c, 0xe1, ++ 0x98, 0x27, 0xbb, 0x14, 0xdd, 0x38, 0xb6, 0xfa, 0x71, 0x10, 0x3b, 0x71, ++ 0xcc, 0x1c, 0xc3, 0x46, 0x4c, 0xc2, 0xf1, 0x7c, 0xa3, 0xc1, 0xe7, 0xe1, ++ 0x4b, 0x7a, 0x5e, 0x01, 0x86, 0xe9, 0x42, 0xdd, 0x3f, 0xc4, 0x1c, 0xf8, ++ 0xcc, 0x79, 0x04, 0x36, 0xbb, 0xcb, 0x6f, 0xa7, 0x29, 0xd8, 0x3f, 0x88, ++ 0xd7, 0xc5, 0x90, 0xb8, 0x66, 0x02, 0x3a, 0xb5, 0x69, 0x1e, 0xdd, 0xb4, ++ 0xa1, 0x5f, 0xdb, 0x5d, 0xaf, 0x47, 0x3e, 0x56, 0x37, 0xbf, 0x7e, 0x29, ++ 0x2c, 0x50, 0x2e, 0x6e, 0x40, 0x1a, 0x60, 0x82, 0x41, 0xe8, 0xfe, 0x34, ++ 0xec, 0x3f, 0xb1, 0xc1, 0xdb, 0x30, 0x41, 0x2e, 0x94, 0x92, 0x89, 0x3c, ++ 0x7c, 0x32, 0xa5, 0xfb, 0xd5, 0x5a, 0x8c, 0xe2, 0xbd, 0x05, 0xfa, 0xff, ++ 0x76, 0xca, 0xd8, 0x44, 0xae, 0xea, 0x4e, 0x4c, 0x55, 0x07, 0x27, 0x88, ++ 0xa3, 0x7c, 0x99, 0x43, 0xf9, 0x2a, 0x63, 0xb0, 0x32, 0x91, 0x51, 0xf5, ++ 0x54, 0x2c, 0x61, 0x93, 0x76, 0x5a, 0xb8, 0x1e, 0x73, 0x7e, 0x5f, 0xd1, ++ 0x89, 0x2c, 0x74, 0xd0, 0xc2, 0x2c, 0xec, 0x92, 0x63, 0xa7, 0x29, 0x97, ++ 0x93, 0xae, 0x3d, 0xaa, 0x64, 0x2f, 0x66, 0x8f, 0x93, 0x97, 0x95, 0xd9, ++ 0x0f, 0xca, 0xc2, 0x9c, 0x27, 0xb7, 0x42, 0x17, 0xde, 0x03, 0x59, 0x95, ++ 0xb3, 0x50, 0x84, 0x67, 0xa1, 0xbc, 0xce, 0xc6, 0xc4, 0x3c, 0xd1, 0x21, ++ 0x91, 0x23, 0x71, 0x09, 0x1f, 0x21, 0xa6, 0xec, 0xb2, 0x6e, 0x15, 0x81, ++ 0x1d, 0xfb, 0xc1, 0xc7, 0x4d, 0xb1, 0x87, 0xd2, 0xd2, 0x95, 0x78, 0x08, ++ 0xb6, 0xb7, 0x82, 0xb4, 0x28, 0x5d, 0xc9, 0x33, 0x68, 0x2b, 0x72, 0x16, ++ 0x65, 0x51, 0x6f, 0xcb, 0x52, 0x02, 0xbf, 0x76, 0x69, 0x5a, 0xf2, 0xd7, ++ 0x4a, 0xd3, 0xd2, 0x7a, 0x3f, 0x7c, 0x78, 0xd5, 0x0f, 0xe7, 0xf7, 0x37, ++ 0x75, 0xfc, 0xe0, 0x29, 0xe8, 0x9c, 0xc0, 0x7f, 0xa2, 0x3d, 0x52, 0x3e, ++ 0x14, 0xf4, 0xfe, 0x53, 0xf0, 0xb1, 0x1c, 0xc9, 0x96, 0xe1, 0x3f, 0xa5, ++ 0x3c, 0x79, 0xcc, 0x2d, 0x78, 0x99, 0x41, 0x4f, 0x2e, 0xb9, 0x4e, 0x21, ++ 0x2f, 0xf6, 0x9b, 0xd4, 0x77, 0xff, 0xcb, 0xfd, 0x1d, 0xd9, 0xb3, 0xdd, ++ 0xde, 0x93, 0x36, 0x0a, 0x5e, 0x0b, 0x7c, 0xaa, 0x6b, 0x52, 0x07, 0x65, ++ 0x72, 0xc7, 0x32, 0x04, 0x25, 0x7d, 0x0d, 0x70, 0x16, 0xfc, 0x66, 0xb6, ++ 0xff, 0xaa, 0xf2, 0xdb, 0xee, 0xee, 0x3e, 0x28, 0x5b, 0x77, 0xd8, 0xd6, ++ 0x95, 0x10, 0x31, 0xd0, 0x41, 0xc9, 0x42, 0xff, 0x67, 0x43, 0x8e, 0xb5, ++ 0x5b, 0xec, 0xd1, 0x2f, 0x09, 0xe3, 0x83, 0x8e, 0x74, 0x1e, 0x71, 0xe2, ++ 0xf7, 0x1a, 0x3d, 0xfb, 0xef, 0x05, 0x2d, 0x3b, 0xcf, 0xf2, 0xdd, 0x93, ++ 0xe8, 0x0e, 0x0b, 0xcf, 0x31, 0xe9, 0x3c, 0x91, 0x90, 0x2e, 0xd0, 0xa5, ++ 0x57, 0xd1, 0x84, 0xfb, 0x02, 0x71, 0xe9, 0x39, 0x42, 0x4c, 0xa2, 0x68, ++ 0xd3, 0x0b, 0xda, 0x24, 0x41, 0x1b, 0xf8, 0x32, 0x7d, 0xd6, 0x15, 0xa4, ++ 0x2b, 0xd2, 0x35, 0xf4, 0x33, 0xd0, 0xa6, 0x17, 0xb4, 0xe9, 0x39, 0x9b, ++ 0x40, 0x7d, 0xb4, 0xb1, 0xd4, 0x89, 0xb4, 0x49, 0x3e, 0x7d, 0x75, 0x3b, ++ 0x9e, 0x1d, 0xe9, 0x3a, 0x12, 0x45, 0x1f, 0x86, 0xec, 0xea, 0x2e, 0xc8, ++ 0xc8, 0x0e, 0x60, 0xe7, 0xd8, 0x41, 0xb9, 0x00, 0x3b, 0x54, 0x86, 0xdf, ++ 0xf6, 0xd8, 0x90, 0x3d, 0xbe, 0x0c, 0x5d, 0x5a, 0xbb, 0xcd, 0x93, 0x17, ++ 0x76, 0xfc, 0xc8, 0x8b, 0x5f, 0x6d, 0xef, 0x11, 0x63, 0x50, 0x66, 0xca, ++ 0xca, 0x3e, 0xc4, 0x33, 0x21, 0x85, 0x75, 0x30, 0xc7, 0x02, 0x6c, 0x0c, ++ 0xe3, 0x9f, 0x0e, 0x74, 0xfd, 0x97, 0xe4, 0x9e, 0xf9, 0x69, 0xfc, 0x80, ++ 0xb7, 0x4b, 0x2c, 0xbb, 0x1f, 0x38, 0xfb, 0x3e, 0xd9, 0x57, 0x02, 0x16, ++ 0x4b, 0x61, 0xdc, 0x83, 0x0e, 0xf0, 0x78, 0xa8, 0x51, 0x5a, 0x91, 0x07, ++ 0xda, 0x8e, 0xd7, 0x36, 0xe2, 0xda, 0x65, 0xf0, 0x61, 0x48, 0x9e, 0xad, ++ 0x0d, 0xca, 0x77, 0x6b, 0xfd, 0xf2, 0x6d, 0xd8, 0x96, 0x27, 0x6a, 0x1d, ++ 0x58, 0x2b, 0x71, 0xf0, 0x24, 0x05, 0xfe, 0xb8, 0xf2, 0x9d, 0x5a, 0x52, ++ 0x9e, 0x02, 0xad, 0x9e, 0xc4, 0x6f, 0xa4, 0x9c, 0x94, 0x5d, 0xe5, 0x7e, ++ 0xcd, 0x23, 0xf2, 0x87, 0xb1, 0x0a, 0x07, 0x73, 0xb7, 0x1f, 0x2d, 0x60, ++ 0xfd, 0x2d, 0xd4, 0x9c, 0x37, 0x2a, 0xf2, 0x3c, 0x74, 0x98, 0x25, 0xa7, ++ 0x57, 0xed, 0x4b, 0xc1, 0xb3, 0x1c, 0xfb, 0x70, 0x0e, 0x7c, 0xa8, 0x60, ++ 0x9d, 0x8e, 0x2b, 0xda, 0xaf, 0xd9, 0x9e, 0x8a, 0x6f, 0x7b, 0x82, 0xf9, ++ 0xcd, 0xe6, 0xe5, 0x27, 0x92, 0x39, 0x36, 0x23, 0x93, 0xf0, 0xa5, 0x7f, ++ 0xcf, 0xf5, 0x20, 0xc7, 0xd4, 0xc5, 0x83, 0xd4, 0xf1, 0x89, 0x5c, 0xc8, ++ 0x54, 0xfe, 0xad, 0x8f, 0x35, 0xce, 0xb5, 0x61, 0xcd, 0x26, 0xd3, 0xe6, ++ 0xb4, 0x74, 0x1d, 0x9b, 0x96, 0xce, 0x63, 0x90, 0x05, 0x97, 0x6d, 0x2d, ++ 0x5b, 0xe6, 0xdb, 0xe4, 0x81, 0xfd, 0xd8, 0x43, 0x59, 0x71, 0xac, 0x37, ++ 0x24, 0x89, 0xfe, 0x0f, 0x48, 0x37, 0xea, 0x38, 0xa8, 0x73, 0x45, 0xf5, ++ 0xdd, 0x82, 0xbe, 0x1b, 0xe5, 0xc1, 0x98, 0x0d, 0x59, 0xa3, 0x0d, 0xff, ++ 0xdf, 0x92, 0xa9, 0x30, 0xfd, 0x4b, 0xc9, 0x9c, 0x7e, 0xae, 0x51, 0x9a, ++ 0xf8, 0x0c, 0xd5, 0x70, 0x92, 0xf9, 0x9d, 0x48, 0x99, 0xef, 0x88, 0x79, ++ 0xf4, 0x57, 0x92, 0x39, 0xc7, 0xbe, 0xdf, 0x40, 0xfe, 0x0b, 0x92, 0x39, ++ 0xfa, 0x16, 0xde, 0x2f, 0x20, 0x7d, 0x13, 0xe9, 0xb8, 0x74, 0x1e, 0x85, ++ 0x6f, 0x7c, 0xee, 0xc7, 0x78, 0x87, 0x2f, 0x77, 0xee, 0x41, 0x94, 0xbb, ++ 0x09, 0xe3, 0xbb, 0x36, 0x0a, 0xac, 0x01, 0x9d, 0xf7, 0xb2, 0x1e, 0x3f, ++ 0xf3, 0x99, 0xc7, 0x6f, 0x0f, 0x42, 0xa7, 0xfd, 0x17, 0xe8, 0x34, 0xfd, ++ 0xbc, 0xc0, 0x77, 0xea, 0x36, 0x3e, 0x4f, 0x83, 0x26, 0x07, 0x54, 0xcc, ++ 0xe8, 0x3e, 0x97, 0xf6, 0x66, 0xa7, 0x4c, 0x58, 0x05, 0xaf, 0x09, 0xb8, ++ 0xa2, 0x05, 0xeb, 0x60, 0x7a, 0x60, 0xf3, 0x75, 0x70, 0xb8, 0xe7, 0xa0, ++ 0x6c, 0xd9, 0x11, 0xcc, 0x3f, 0x98, 0xaf, 0x63, 0xfd, 0x42, 0xd1, 0xc1, ++ 0x2e, 0xdc, 0x2b, 0x9c, 0x87, 0x13, 0xff, 0x9a, 0xd9, 0xb3, 0xe7, 0x1e, ++ 0xac, 0x03, 0xf3, 0x1c, 0xdf, 0xfd, 0x75, 0x60, 0x9e, 0x83, 0x6e, 0x38, ++ 0x09, 0x5f, 0xf6, 0x64, 0x87, 0x34, 0x1e, 0x5d, 0x5b, 0x07, 0x0d, 0x47, ++ 0xdf, 0x7b, 0x1d, 0x34, 0x9e, 0x43, 0xb9, 0x73, 0xa4, 0x19, 0xda, 0x38, ++ 0x4d, 0x9a, 0xb5, 0x23, 0xfd, 0x12, 0xe6, 0xca, 0xb1, 0x37, 0x62, 0xec, ++ 0x3e, 0x2e, 0xfa, 0x38, 0xe4, 0xfd, 0xee, 0x1d, 0x07, 0x74, 0xfe, 0xbf, ++ 0xf3, 0x46, 0x63, 0xf6, 0xbc, 0x18, 0xa4, 0x29, 0xca, 0x56, 0x48, 0xc3, ++ 0x2f, 0x83, 0x36, 0xfb, 0xa5, 0x93, 0xf4, 0xab, 0xec, 0xc6, 0x7b, 0xc1, ++ 0x8b, 0xd0, 0x37, 0x57, 0xf4, 0x04, 0x4e, 0x1a, 0x64, 0xfe, 0xcb, 0x90, ++ 0x19, 0x62, 0xcc, 0x57, 0x65, 0xb2, 0xe4, 0xc9, 0x84, 0xda, 0x0f, 0x7a, ++ 0x8d, 0x7e, 0xec, 0x8e, 0x98, 0x2c, 0x27, 0x62, 0xa0, 0xc9, 0x02, 0x74, ++ 0xfb, 0x05, 0xf1, 0xe9, 0xc0, 0x98, 0xf2, 0x2e, 0x71, 0xe2, 0x23, 0xe2, ++ 0x24, 0x7f, 0x06, 0x3a, 0x8c, 0x40, 0xf6, 0xb3, 0x35, 0xca, 0xce, 0x4b, ++ 0x32, 0x0c, 0x99, 0xf8, 0xa9, 0x6b, 0x27, 0x81, 0x85, 0xa0, 0x2f, 0x28, ++ 0x17, 0x94, 0x89, 0x56, 0xa5, 0x93, 0x4e, 0xba, 0xf6, 0x23, 0x15, 0xb9, ++ 0x5e, 0x4e, 0xb6, 0xf9, 0xfa, 0xd7, 0x3c, 0xaa, 0xec, 0x45, 0x32, 0x67, ++ 0x72, 0x9f, 0x32, 0x29, 0x56, 0xcf, 0x95, 0x86, 0x60, 0xaf, 0x3e, 0x7f, ++ 0xcc, 0x90, 0xe9, 0x1e, 0xf2, 0x8a, 0xed, 0xe2, 0xbd, 0x52, 0xf0, 0xc2, ++ 0xce, 0x1b, 0xde, 0xa9, 0xf6, 0x84, 0x7c, 0xb1, 0x67, 0x55, 0x2e, 0xe7, ++ 0x45, 0xfc, 0x75, 0x31, 0xac, 0xf8, 0x11, 0x8c, 0x3b, 0x98, 0x4b, 0xf0, ++ 0xad, 0xbf, 0xee, 0x1b, 0xe7, 0x42, 0x59, 0x5f, 0x5d, 0x3b, 0x89, 0xb7, ++ 0x8f, 0x15, 0x0a, 0xb7, 0xc9, 0x7e, 0xa4, 0x28, 0x97, 0x20, 0x7b, 0xa0, ++ 0xe1, 0x39, 0xa6, 0xa4, 0xe1, 0x34, 0xe4, 0xfe, 0x65, 0xd9, 0x75, 0x8c, ++ 0x6b, 0xe6, 0x65, 0xcc, 0x55, 0xe9, 0x12, 0xe8, 0x08, 0xb6, 0xe7, 0xc9, ++ 0x8c, 0xcb, 0x18, 0xc9, 0xf5, 0xf1, 0x29, 0xf8, 0x70, 0x39, 0xcb, 0x93, ++ 0x25, 0xb7, 0x20, 0x4b, 0x43, 0xa8, 0x53, 0xf9, 0x12, 0x7e, 0xff, 0x5e, ++ 0xcf, 0xed, 0x01, 0xd0, 0xdd, 0x4e, 0xcc, 0x9b, 0x5f, 0x06, 0xdd, 0xef, ++ 0x93, 0xae, 0xa3, 0xab, 0xba, 0x86, 0x71, 0x4b, 0xa5, 0x6b, 0xba, 0xce, ++ 0x59, 0x52, 0x29, 0x3b, 0xf2, 0x59, 0xea, 0x90, 0x32, 0xe7, 0x05, 0x1d, ++ 0xc3, 0x7d, 0xee, 0x32, 0xf4, 0x4c, 0x19, 0x3a, 0x05, 0x3a, 0xe4, 0xdb, ++ 0xc8, 0x7f, 0x0a, 0x65, 0x9e, 0x84, 0xcf, 0xf3, 0x04, 0xb0, 0xdf, 0xe3, ++ 0xc0, 0x14, 0xe7, 0xcb, 0x69, 0xed, 0x1b, 0xaa, 0xf9, 0xc2, 0x66, 0x29, ++ 0x7f, 0x45, 0x2a, 0xf3, 0xa4, 0xc7, 0xaf, 0x14, 0x6f, 0x33, 0xee, 0x36, ++ 0xe2, 0x2c, 0x8c, 0x4c, 0x64, 0x7e, 0x3e, 0xa0, 0x09, 0x75, 0x1f, 0x63, ++ 0xfb, 0x81, 0xae, 0x6c, 0xd9, 0xa0, 0x2b, 0x45, 0x7e, 0x50, 0xf5, 0xf1, ++ 0x24, 0xf1, 0x71, 0xb1, 0x04, 0xb9, 0xd1, 0xd8, 0xbc, 0x08, 0xbb, 0xb9, ++ 0x02, 0xbf, 0x24, 0x9a, 0x7a, 0x51, 0xa2, 0x27, 0x3c, 0xef, 0xe7, 0xb0, ++ 0x9b, 0x05, 0xf0, 0xc4, 0x34, 0x90, 0xbf, 0xc8, 0x6f, 0x94, 0x7b, 0xca, ++ 0xb6, 0xc1, 0x98, 0xb8, 0x3c, 0x8f, 0xbc, 0x8a, 0xef, 0x6b, 0x63, 0x3c, ++ 0x7a, 0x7c, 0x2a, 0x8f, 0xe5, 0x1a, 0x25, 0x3b, 0x91, 0x94, 0x87, 0xca, ++ 0x7d, 0x56, 0x23, 0xea, 0xcf, 0x2f, 0xb2, 0x8e, 0x3d, 0x84, 0xaa, 0xa8, ++ 0xc7, 0xfc, 0x0e, 0xb9, 0x50, 0x4a, 0xa9, 0x31, 0x54, 0xe6, 0x52, 0xe2, ++ 0xc7, 0x24, 0xa9, 0xaf, 0x38, 0x56, 0xbc, 0xd3, 0xb7, 0x2c, 0xd3, 0xce, ++ 0x86, 0xa5, 0x10, 0x27, 0xad, 0xe3, 0xb2, 0x52, 0xfa, 0xf3, 0x28, 0x63, ++ 0x37, 0x19, 0x87, 0xcf, 0x41, 0xec, 0xc0, 0xfa, 0x2d, 0x62, 0x07, 0x8c, ++ 0x17, 0x84, 0x61, 0xcb, 0x54, 0x0c, 0x01, 0x69, 0xa2, 0xce, 0x67, 0xe5, ++ 0xf7, 0x60, 0x9f, 0x2d, 0xc0, 0x46, 0xc4, 0x93, 0x9c, 0xaf, 0x5d, 0x58, ++ 0x16, 0xee, 0xa7, 0x5d, 0x94, 0xdb, 0x4f, 0xfa, 0xf3, 0x33, 0x4f, 0x0b, ++ 0xcf, 0x81, 0xc8, 0x95, 0x39, 0xdb, 0xbd, 0x0c, 0x4c, 0x91, 0x8d, 0xb9, ++ 0xe0, 0xd7, 0xf9, 0x28, 0xf4, 0xd7, 0x50, 0xda, 0xdc, 0xba, 0xc5, 0xc7, ++ 0x67, 0x61, 0x99, 0xe6, 0x7e, 0x50, 0x09, 0xba, 0x0d, 0x18, 0xf2, 0x9f, ++ 0x84, 0xf1, 0x5c, 0xe5, 0x3b, 0xfc, 0x34, 0xdf, 0x07, 0xc5, 0xb3, 0xdf, ++ 0x1e, 0x69, 0x6e, 0x9e, 0xe4, 0xdc, 0x0d, 0xb9, 0x1d, 0xe8, 0x44, 0xd0, ++ 0x7e, 0xa7, 0xee, 0xab, 0xf3, 0x74, 0x92, 0xb1, 0x3b, 0xe9, 0x82, 0xbe, ++ 0xc8, 0xcc, 0x85, 0xd1, 0x57, 0x87, 0xc6, 0xe6, 0xfc, 0xb6, 0x11, 0x7b, ++ 0x06, 0x3e, 0x5e, 0x52, 0x1e, 0x2e, 0x07, 0x58, 0x2f, 0x09, 0x1b, 0x2b, ++ 0xe1, 0xd1, 0x5e, 0x4f, 0x7e, 0xee, 0x92, 0x5e, 0xfd, 0x78, 0x77, 0xe5, ++ 0x70, 0xed, 0x9d, 0xf6, 0x2b, 0xeb, 0xff, 0x80, 0xcb, 0x88, 0xcd, 0x4a, ++ 0x18, 0x1f, 0xf0, 0x11, 0xc7, 0x6e, 0xc2, 0x9e, 0x17, 0x81, 0xbb, 0xcc, ++ 0xb3, 0x1d, 0xea, 0x9b, 0x09, 0x6c, 0x50, 0x29, 0x41, 0x37, 0x9e, 0xe5, ++ 0x9e, 0x2e, 0x74, 0xdb, 0xd9, 0x88, 0x14, 0x67, 0x29, 0x97, 0xd2, 0x66, ++ 0x82, 0x5f, 0x2c, 0x5f, 0x29, 0x75, 0x20, 0x6d, 0x41, 0x9a, 0x50, 0xed, ++ 0x54, 0x4a, 0x8e, 0xaa, 0x5f, 0x29, 0x25, 0x55, 0xbd, 0x4a, 0xa9, 0x1f, ++ 0xa9, 0x2b, 0x0d, 0x67, 0xe1, 0x38, 0x9d, 0xed, 0x91, 0xe9, 0x53, 0xb0, ++ 0x2f, 0x83, 0xa6, 0x3a, 0x23, 0x91, 0x83, 0xfd, 0x09, 0xc3, 0xcb, 0xba, ++ 0x6c, 0x0d, 0x01, 0x63, 0xed, 0x04, 0x06, 0xd9, 0x29, 0xce, 0x09, 0xce, ++ 0x9f, 0xba, 0x77, 0x85, 0xf1, 0xa4, 0xf8, 0xe7, 0x24, 0x2d, 0xfb, 0x66, ++ 0x1b, 0xb1, 0x5e, 0xc3, 0x56, 0x51, 0xba, 0xad, 0x11, 0xbc, 0xe7, 0xe7, ++ 0x49, 0xb7, 0x3b, 0x95, 0xef, 0x96, 0x71, 0xef, 0x03, 0x4f, 0x52, 0xe8, ++ 0xe3, 0xb7, 0xa9, 0xdf, 0xcb, 0x3d, 0x07, 0xdd, 0x46, 0x0a, 0xe3, 0xa9, ++ 0xa7, 0x07, 0xf7, 0x6e, 0xd3, 0xef, 0xb1, 0x77, 0x4b, 0xb9, 0x26, 0x7d, ++ 0xef, 0x94, 0x15, 0x27, 0x25, 0xcf, 0x3b, 0x49, 0xb9, 0xe0, 0x0c, 0xc8, ++ 0x0f, 0x61, 0xa7, 0x2f, 0x3a, 0xff, 0x33, 0x4a, 0x2c, 0x50, 0x51, 0x7b, ++ 0x30, 0x01, 0xaf, 0x1c, 0x15, 0xe3, 0x68, 0x48, 0xbd, 0x2e, 0x17, 0x4b, ++ 0xc4, 0xce, 0xde, 0x4d, 0x93, 0x6e, 0x81, 0x76, 0x0b, 0x3a, 0x99, 0x58, ++ 0xad, 0x00, 0xfb, 0x77, 0x10, 0xbe, 0x02, 0xed, 0x9e, 0xb2, 0x51, 0xf1, ++ 0x5d, 0xfe, 0x7a, 0x76, 0xf3, 0xd0, 0xab, 0x2b, 0xb3, 0xd4, 0x4b, 0x58, ++ 0x53, 0xc2, 0x35, 0x80, 0xf7, 0x79, 0xf2, 0xde, 0x91, 0xaf, 0x95, 0x39, ++ 0xd7, 0xe2, 0x55, 0x4d, 0x12, 0x92, 0x51, 0x85, 0x19, 0x5a, 0xe5, 0x07, ++ 0x8b, 0xcd, 0x62, 0xc2, 0x4a, 0x99, 0xd7, 0x45, 0xd4, 0x7e, 0x3d, 0x7d, ++ 0x70, 0xd9, 0xce, 0xf3, 0x4e, 0x4f, 0x83, 0x3e, 0x8c, 0x07, 0x60, 0x7e, ++ 0xdb, 0x39, 0x9b, 0xe0, 0xbd, 0x1f, 0x6b, 0x8c, 0xcf, 0x86, 0x64, 0x9d, ++ 0x18, 0x9e, 0x99, 0x72, 0xdd, 0x31, 0xf6, 0xb4, 0x45, 0xd2, 0xe3, 0x86, ++ 0x34, 0x3a, 0xbd, 0xc2, 0x73, 0x0f, 0x15, 0x85, 0x41, 0x2e, 0xa8, 0xb2, ++ 0x8d, 0xce, 0x8d, 0xc0, 0x79, 0x94, 0x5f, 0xa4, 0x4b, 0xfe, 0x18, 0xb2, ++ 0xc0, 0x75, 0xf9, 0xfe, 0x2d, 0xf4, 0xcb, 0x93, 0x05, 0xac, 0x8d, 0x9c, ++ 0x2a, 0xbf, 0x13, 0xeb, 0xeb, 0x95, 0x2d, 0xc4, 0x13, 0xbb, 0x20, 0x9b, ++ 0x17, 0x4b, 0x7c, 0xe6, 0x77, 0xfa, 0x5b, 0x8c, 0xb7, 0x5d, 0x1a, 0x9b, ++ 0x71, 0x6c, 0xbd, 0x9e, 0xc4, 0xb8, 0xb5, 0x17, 0xb8, 0xf4, 0x48, 0x03, ++ 0xe6, 0x65, 0x27, 0x12, 0x86, 0xd9, 0x6e, 0x02, 0xd7, 0xef, 0x52, 0x36, ++ 0x98, 0x63, 0xb0, 0x93, 0xcb, 0xa0, 0xcf, 0xf3, 0xc9, 0x56, 0x59, 0xb1, ++ 0x40, 0x53, 0xae, 0x6b, 0x6b, 0x07, 0xf3, 0xf1, 0xdb, 0x82, 0xbc, 0x6e, ++ 0xa4, 0x8d, 0x48, 0x6f, 0x90, 0xe2, 0xf1, 0x5f, 0xea, 0x36, 0x23, 0x1b, ++ 0xde, 0x4b, 0x3a, 0x7d, 0x56, 0xfb, 0x58, 0xec, 0x2b, 0x22, 0xce, 0xd7, ++ 0x5b, 0xa4, 0xfb, 0x88, 0x05, 0xbc, 0x1b, 0x07, 0xfe, 0xed, 0x90, 0xe4, ++ 0x91, 0x84, 0x5c, 0x77, 0x24, 0x88, 0x1d, 0xfd, 0xe7, 0xb1, 0x2e, 0x15, ++ 0x47, 0xfc, 0x4f, 0x63, 0xce, 0x3c, 0xd3, 0xd7, 0xf4, 0x7e, 0xf1, 0xeb, ++ 0x7a, 0x1f, 0xf9, 0x8d, 0xb1, 0x5e, 0x95, 0xfe, 0x6a, 0x2c, 0xa9, 0xd2, ++ 0x37, 0xc7, 0xae, 0xab, 0xfa, 0x3e, 0x53, 0x71, 0x21, 0x29, 0x5f, 0x2d, ++ 0x13, 0x73, 0x0e, 0x02, 0x4f, 0xba, 0xd0, 0x3d, 0xfd, 0xd0, 0x3d, 0x49, ++ 0xe8, 0x9e, 0x21, 0xea, 0x1e, 0xc6, 0x47, 0xa1, 0xcb, 0x5d, 0xf9, 0x29, ++ 0x64, 0xf8, 0xbc, 0xdb, 0x08, 0xac, 0xe8, 0x79, 0x23, 0x6a, 0xbe, 0xf6, ++ 0x23, 0xcb, 0xe0, 0x77, 0xe5, 0x8c, 0x44, 0xb7, 0x43, 0x2f, 0xed, 0x38, ++ 0xd9, 0x20, 0x0b, 0x31, 0xcf, 0x3b, 0xe6, 0x3a, 0x72, 0x05, 0xe5, 0x33, ++ 0x0e, 0xd7, 0x76, 0x7f, 0x13, 0x7d, 0xb4, 0x2b, 0xa5, 0x01, 0xe8, 0x29, ++ 0xae, 0x81, 0xa8, 0x54, 0x26, 0xe2, 0xb2, 0x08, 0x9f, 0x6d, 0xad, 0x4c, ++ 0x12, 0xcf, 0xd4, 0x09, 0x9f, 0x44, 0xd9, 0x24, 0x6c, 0x86, 0x25, 0x4b, ++ 0xbd, 0x09, 0x39, 0xdd, 0x6b, 0x0f, 0x25, 0x4c, 0xea, 0xb3, 0x84, 0xcc, ++ 0xc3, 0xff, 0xaf, 0x94, 0x59, 0x9e, 0xe5, 0xb0, 0x66, 0xcb, 0x7e, 0xbd, ++ 0x99, 0x72, 0xa0, 0x3b, 0x20, 0xb3, 0x73, 0x8c, 0x0d, 0xfa, 0x76, 0xc1, ++ 0x34, 0x1b, 0xe1, 0xdb, 0xba, 0xa0, 0xff, 0x04, 0xf2, 0x07, 0x79, 0xc6, ++ 0x03, 0x79, 0xc4, 0x47, 0x7f, 0xbf, 0x89, 0x7c, 0xce, 0xba, 0x13, 0xc8, ++ 0x63, 0x1d, 0x3b, 0xde, 0x85, 0xfc, 0x71, 0xe9, 0x8a, 0xe7, 0xd5, 0x39, ++ 0xa3, 0x76, 0xe4, 0xb1, 0x8d, 0x90, 0x8e, 0xd1, 0xec, 0x6d, 0xa2, 0x2c, ++ 0x85, 0x9c, 0x20, 0xbf, 0x4f, 0xc5, 0x0b, 0xd2, 0x96, 0x8b, 0x35, 0xc2, ++ 0xbc, 0x2e, 0x8b, 0xf5, 0xb2, 0xae, 0xab, 0xf4, 0xe3, 0x1d, 0x7a, 0x0f, ++ 0xe3, 0xf6, 0x6a, 0x8b, 0x64, 0xab, 0x0d, 0xef, 0x62, 0x13, 0x82, 0x75, ++ 0xba, 0x12, 0xb7, 0x84, 0xfb, 0xea, 0xfe, 0xda, 0x0f, 0x0f, 0x70, 0x8d, ++ 0x80, 0xee, 0xb0, 0xc9, 0x4f, 0x62, 0xbe, 0x4f, 0xc0, 0x26, 0x3f, 0x0e, ++ 0x9b, 0x7c, 0xbe, 0xbc, 0xa6, 0x53, 0x7c, 0x5b, 0x4c, 0xbd, 0xf0, 0x28, ++ 0x78, 0x36, 0x0e, 0x5f, 0x60, 0x37, 0x7c, 0x84, 0x51, 0xf8, 0x03, 0xc3, ++ 0xe0, 0x5f, 0x0a, 0xbc, 0x9b, 0x00, 0xdf, 0xd2, 0xe0, 0xe3, 0x90, 0xda, ++ 0xcf, 0x9c, 0x55, 0x7b, 0xf8, 0xaf, 0x2b, 0x7b, 0xfc, 0x50, 0xd9, 0x84, ++ 0xcd, 0x28, 0x78, 0x57, 0x39, 0x36, 0x30, 0xe1, 0xea, 0x1a, 0x1f, 0xfa, ++ 0x01, 0x74, 0xcd, 0x2f, 0x31, 0xae, 0x27, 0x66, 0x69, 0xe3, 0x51, 0xc6, ++ 0xc7, 0xe0, 0x2e, 0xe3, 0x5f, 0x58, 0xe3, 0x87, 0x57, 0x64, 0x19, 0x58, ++ 0x24, 0x4d, 0x39, 0x86, 0x4f, 0x61, 0x9f, 0x9f, 0x97, 0x1e, 0xea, 0x45, ++ 0xe0, 0xa4, 0x21, 0x19, 0x3c, 0x1a, 0x07, 0xfe, 0x03, 0xba, 0x57, 0x7b, ++ 0x78, 0x78, 0x3e, 0xb7, 0x55, 0x4c, 0x62, 0x40, 0x97, 0xfb, 0x34, 0xd4, ++ 0x25, 0x01, 0x6e, 0x5a, 0x1e, 0x6a, 0x93, 0xf4, 0x8e, 0x36, 0xa5, 0x4f, ++ 0x6c, 0xf7, 0x79, 0xf4, 0xbb, 0x4b, 0x1a, 0x81, 0xeb, 0x0a, 0xe8, 0xe3, ++ 0x80, 0xfc, 0x57, 0x97, 0x71, 0x2b, 0xdf, 0x1f, 0xc4, 0x58, 0xa2, 0xa0, ++ 0xd9, 0x96, 0x49, 0xc7, 0x8a, 0xee, 0xaa, 0xb1, 0xfd, 0xa8, 0xc2, 0x5d, ++ 0x59, 0x61, 0xfb, 0xb0, 0x1d, 0xe8, 0xb3, 0xeb, 0x28, 0x65, 0xbf, 0x0f, ++ 0x7c, 0xfb, 0x7b, 0xfa, 0x2c, 0x91, 0xd5, 0xac, 0xf7, 0x36, 0x31, 0xfe, ++ 0x65, 0x62, 0x0c, 0xc6, 0xd9, 0x7d, 0x5f, 0x7d, 0x75, 0x6c, 0x3b, 0x61, ++ 0xd3, 0xfe, 0x4a, 0xc9, 0xc0, 0x84, 0x0b, 0x5f, 0xf0, 0xa8, 0x6f, 0xc3, ++ 0x3b, 0xcf, 0xa1, 0xd6, 0x31, 0x69, 0xe7, 0x0e, 0xa8, 0x29, 0xd7, 0xc9, ++ 0xcd, 0x61, 0xbf, 0x1d, 0xf3, 0xa4, 0x05, 0x59, 0xa5, 0x2e, 0x68, 0x87, ++ 0x9c, 0xf3, 0x9d, 0x7a, 0x85, 0x7a, 0x81, 0xb2, 0xe0, 0xf0, 0x0c, 0xcf, ++ 0x16, 0x9e, 0x3d, 0x9b, 0x27, 0xcd, 0x4e, 0x52, 0x57, 0xbc, 0x2e, 0x33, ++ 0x1b, 0xf4, 0xe7, 0xb0, 0x04, 0xbe, 0x6e, 0x8b, 0x44, 0x52, 0x8e, 0x75, ++ 0x87, 0x9a, 0xa3, 0xaf, 0x43, 0xf7, 0x11, 0x93, 0xce, 0xa6, 0xed, 0x36, ++ 0xd1, 0x78, 0x54, 0x61, 0xaa, 0xd7, 0x30, 0x57, 0xb6, 0xa1, 0xe8, 0x34, ++ 0x34, 0xec, 0xfb, 0x07, 0x2a, 0x0e, 0x08, 0x6c, 0x1c, 0xff, 0x25, 0xf4, ++ 0x4b, 0x96, 0x58, 0x05, 0x74, 0xee, 0x3c, 0x46, 0x39, 0xf2, 0xcf, 0x97, ++ 0xcd, 0x9b, 0x49, 0xea, 0x70, 0x59, 0x3c, 0x0a, 0x1c, 0x66, 0xde, 0x28, ++ 0x79, 0xca, 0x2b, 0xf7, 0xc1, 0x17, 0x4d, 0x99, 0x99, 0x6b, 0x95, 0xee, ++ 0x93, 0x8c, 0xb9, 0x36, 0x37, 0x49, 0x2b, 0xe3, 0xae, 0xb4, 0x4b, 0x83, ++ 0x92, 0x45, 0x7e, 0xe7, 0xc9, 0x90, 0x8a, 0x91, 0xcd, 0x9b, 0xa4, 0x51, ++ 0x3f, 0xf4, 0x01, 0x74, 0x98, 0x79, 0x32, 0xea, 0xe3, 0x4a, 0xc8, 0x52, ++ 0x19, 0x32, 0x56, 0x86, 0x8c, 0x95, 0x21, 0x63, 0x65, 0xc8, 0x18, 0xf0, ++ 0xe0, 0x13, 0x58, 0x7f, 0x8f, 0x97, 0x87, 0xb4, 0xad, 0xdf, 0xa3, 0x6c, ++ 0x7d, 0xb1, 0xfc, 0x92, 0xc7, 0xf4, 0x29, 0xe5, 0xaf, 0xf6, 0x43, 0x06, ++ 0xe9, 0x9f, 0x06, 0x7e, 0x2b, 0x30, 0xfc, 0xec, 0xcb, 0x92, 0x9d, 0xa5, ++ 0xcc, 0x78, 0x72, 0xcc, 0xb5, 0x64, 0x61, 0x81, 0x7e, 0xe4, 0x25, 0xb9, ++ 0xad, 0xf4, 0xaa, 0xdc, 0x51, 0xea, 0x93, 0x7f, 0x6a, 0x29, 0x3c, 0xa1, ++ 0xe7, 0x0f, 0xba, 0x1f, 0x27, 0x0d, 0x0a, 0x5e, 0x83, 0x93, 0xb6, 0xc3, ++ 0xbe, 0xcc, 0x58, 0xc3, 0x8a, 0x8e, 0x0e, 0x6c, 0x92, 0x4f, 0xbf, 0xec, ++ 0x2a, 0xa6, 0x84, 0xdf, 0x0e, 0xbb, 0xbf, 0xd8, 0x4b, 0xdd, 0x61, 0x17, ++ 0x3a, 0xb1, 0xa6, 0xf7, 0x9b, 0x90, 0xbf, 0x30, 0xfd, 0x5f, 0xd2, 0xd8, ++ 0xb1, 0x56, 0xc4, 0xf7, 0x71, 0xd2, 0x31, 0xfb, 0xb0, 0x98, 0x8a, 0xee, ++ 0x58, 0x9b, 0x9c, 0x27, 0xe9, 0xfe, 0x99, 0x66, 0xee, 0xa7, 0x56, 0x8e, ++ 0x7f, 0xa9, 0x89, 0xb1, 0xc7, 0x98, 0x43, 0x5a, 0x5e, 0x92, 0xfd, 0x55, ++ 0xe6, 0xbd, 0x8c, 0xef, 0x4c, 0x2f, 0x79, 0xb7, 0xaf, 0xee, 0xb3, 0x03, ++ 0x43, 0xb5, 0x63, 0x8e, 0xe5, 0x67, 0x35, 0xfe, 0xee, 0x57, 0x98, 0xfa, ++ 0xed, 0xd8, 0x99, 0xf4, 0x71, 0x41, 0x9f, 0x4b, 0x2a, 0x36, 0xb8, 0x49, ++ 0xcc, 0xf8, 0x11, 0xac, 0xa7, 0xc2, 0x65, 0x61, 0xfc, 0x92, 0xb1, 0x5d, ++ 0xc6, 0x8d, 0xeb, 0x35, 0x85, 0xda, 0x33, 0x95, 0xdb, 0xa0, 0x57, 0x6e, ++ 0x87, 0x5e, 0xb9, 0xe3, 0x6d, 0x67, 0x79, 0x83, 0x18, 0x7e, 0x77, 0x21, ++ 0x64, 0x76, 0xc8, 0x78, 0xb5, 0xbe, 0x2e, 0x63, 0xba, 0x9b, 0xc5, 0x70, ++ 0x19, 0xdf, 0x4d, 0x6e, 0x88, 0x0b, 0x52, 0x26, 0x3c, 0xb9, 0xe8, 0x32, ++ 0x06, 0x17, 0x9c, 0xd5, 0xda, 0x0c, 0x8b, 0x4d, 0x35, 0x07, 0xf1, 0xe7, ++ 0x70, 0xea, 0xb2, 0xf0, 0xdc, 0x56, 0xb1, 0x44, 0x6c, 0xa0, 0xf6, 0x05, ++ 0x55, 0x1c, 0x3b, 0xeb, 0xc7, 0x12, 0x90, 0x0f, 0x8b, 0x0b, 0xdf, 0x87, ++ 0x71, 0x6c, 0x6b, 0xc0, 0xb6, 0xc6, 0x43, 0xfe, 0x79, 0x45, 0xae, 0x61, ++ 0x5f, 0x87, 0x41, 0x66, 0x56, 0x63, 0xbe, 0x3c, 0x6b, 0xc0, 0xb9, 0x5c, ++ 0x06, 0xef, 0xe9, 0x1f, 0xc0, 0x77, 0x00, 0x7f, 0xa7, 0xa1, 0x97, 0xf2, ++ 0xaa, 0xbd, 0x28, 0xf9, 0x9c, 0xce, 0x84, 0x4c, 0x89, 0x9c, 0xa0, 0x5f, ++ 0xe4, 0xc7, 0x5d, 0xb2, 0x21, 0x5b, 0xe9, 0x6d, 0x8c, 0x1d, 0x58, 0x8d, ++ 0xeb, 0x32, 0x91, 0x6b, 0x4c, 0x35, 0x48, 0x05, 0xf8, 0x67, 0xba, 0xc6, ++ 0xf8, 0x00, 0xd6, 0xec, 0xd2, 0x2b, 0xb2, 0x6f, 0xee, 0xe1, 0x66, 0x5f, ++ 0xee, 0x19, 0x53, 0xe6, 0xfc, 0x82, 0x31, 0xac, 0x6f, 0xdb, 0x3c, 0x21, ++ 0xd1, 0x26, 0xd8, 0xb2, 0x4f, 0x9d, 0x20, 0x16, 0x68, 0x94, 0xe5, 0x18, ++ 0xdb, 0xf5, 0xd7, 0xca, 0x4c, 0x99, 0x6d, 0xbf, 0x22, 0x23, 0x73, 0x7f, ++ 0xd9, 0x4c, 0xfd, 0xb1, 0x84, 0xf5, 0xbf, 0x62, 0xd1, 0x76, 0x4e, 0xc0, ++ 0xb6, 0xb5, 0xcb, 0x6b, 0x73, 0xb4, 0x8b, 0x5d, 0xd6, 0x69, 0xe9, 0x8b, ++ 0x9f, 0xc6, 0x98, 0x1e, 0x76, 0xc3, 0xf4, 0xd7, 0xbc, 0x61, 0xe4, 0xfd, ++ 0x50, 0xba, 0xac, 0x4e, 0x83, 0xcf, 0x7d, 0xd6, 0xd7, 0x84, 0x67, 0x0e, ++ 0xba, 0xac, 0xeb, 0x0d, 0xca, 0x11, 0xfc, 0xef, 0xa5, 0xb5, 0x71, 0xfe, ++ 0x6c, 0x4e, 0xf9, 0x4c, 0x4a, 0xbf, 0x2c, 0xb9, 0xec, 0xef, 0x61, 0xad, ++ 0xd3, 0xae, 0x87, 0xec, 0x07, 0x67, 0x74, 0x51, 0x87, 0xb8, 0xc6, 0x0d, ++ 0xeb, 0xf7, 0x07, 0x24, 0x73, 0x2a, 0x06, 0x3d, 0xc6, 0xb6, 0x02, 0x3f, ++ 0x82, 0xb6, 0x31, 0xc0, 0xde, 0xb4, 0x73, 0x37, 0xc2, 0xde, 0x5d, 0xab, ++ 0xc6, 0x33, 0xea, 0xf6, 0xcb, 0xf4, 0x71, 0xf6, 0xdd, 0x0b, 0x1d, 0x1e, ++ 0x57, 0x72, 0x5b, 0x2c, 0xaf, 0xc4, 0xa3, 0xd0, 0xc5, 0xd1, 0x1d, 0xa4, ++ 0xe7, 0x27, 0xe5, 0x16, 0x67, 0x42, 0x6e, 0x85, 0xec, 0x0c, 0x3b, 0xae, ++ 0x8c, 0x80, 0x17, 0xbb, 0x1c, 0xd8, 0x1b, 0x85, 0xa7, 0x1b, 0xe1, 0x83, ++ 0xb1, 0x6f, 0x9e, 0x49, 0x67, 0x5d, 0x1f, 0x4b, 0x7e, 0xab, 0xe6, 0xd3, ++ 0x28, 0x33, 0xd7, 0xdc, 0x42, 0xda, 0x8c, 0xba, 0x3b, 0xb5, 0x7d, 0x6d, ++ 0x95, 0xac, 0x2a, 0xb7, 0x53, 0xd9, 0xe1, 0xe2, 0xe2, 0x9d, 0x48, 0x61, ++ 0x93, 0x17, 0xa1, 0x67, 0x80, 0xbf, 0x8b, 0xd5, 0x01, 0xbc, 0xc3, 0x76, ++ 0x2e, 0xa6, 0x90, 0x7e, 0x12, 0x29, 0xcb, 0xfe, 0xdb, 0x66, 0x3f, 0xae, ++ 0xbb, 0xf1, 0x5c, 0x90, 0x18, 0x9f, 0x52, 0x7b, 0xdd, 0x97, 0xd5, 0x59, ++ 0x32, 0xf8, 0x98, 0x63, 0x99, 0x59, 0x89, 0xb6, 0x00, 0xfb, 0x94, 0x4e, ++ 0xd8, 0xc9, 0x11, 0xe3, 0x26, 0xf9, 0x34, 0xfc, 0xfa, 0x8a, 0x4b, 0x5e, ++ 0x0e, 0xc8, 0xe7, 0x3e, 0x41, 0x19, 0xb9, 0x49, 0x26, 0x3f, 0x61, 0xc8, ++ 0x64, 0xbf, 0x9d, 0xe6, 0xb8, 0xaf, 0xbb, 0x21, 0xf0, 0xad, 0xbb, 0x47, ++ 0xbb, 0x8c, 0x41, 0xf9, 0x1a, 0x64, 0xac, 0x00, 0xf9, 0x1a, 0xa9, 0x91, ++ 0xe6, 0xd4, 0xf3, 0xd4, 0xef, 0x49, 0xe0, 0xe6, 0x00, 0xf7, 0x39, 0x52, ++ 0xaa, 0x35, 0x4a, 0xe2, 0x6a, 0xc6, 0x96, 0x13, 0xfe, 0x9e, 0xdb, 0x67, ++ 0x7c, 0x7f, 0xc0, 0x1c, 0x84, 0x4f, 0xa2, 0x9e, 0x99, 0x1f, 0x91, 0xfc, ++ 0xd5, 0xa4, 0x7b, 0x8c, 0xfe, 0xb0, 0x47, 0x8c, 0xe7, 0x9f, 0xf3, 0xa7, ++ 0x7d, 0x60, 0x7a, 0x77, 0xcb, 0x2a, 0xb6, 0x6b, 0xb5, 0x93, 0x39, 0x03, ++ 0x42, 0xa0, 0xf2, 0x37, 0x93, 0xc7, 0x20, 0x0e, 0x37, 0x8f, 0x79, 0xd3, ++ 0x9e, 0xdb, 0xb0, 0xfd, 0x05, 0x6f, 0xbb, 0xb3, 0x47, 0x9e, 0x85, 0x6d, ++ 0xff, 0xee, 0xaa, 0x6d, 0xdf, 0x0b, 0x9a, 0x6c, 0xb4, 0xff, 0x8e, 0x75, ++ 0x1b, 0xe6, 0x33, 0x0a, 0x9e, 0xde, 0x8a, 0xdf, 0x2d, 0xe5, 0x75, 0x71, ++ 0xbd, 0xd9, 0x02, 0xb0, 0x64, 0x83, 0xc3, 0xf6, 0xd6, 0xc5, 0xf7, 0x0a, ++ 0x79, 0x59, 0x8d, 0x1d, 0x0e, 0x5d, 0x11, 0xda, 0xbc, 0x37, 0x24, 0xd2, ++ 0xe3, 0xbc, 0xd1, 0x69, 0x38, 0x4f, 0x9b, 0x06, 0xf7, 0x99, 0x5d, 0x39, ++ 0x53, 0x23, 0x06, 0xbb, 0x20, 0xe6, 0x39, 0xe2, 0xaf, 0x17, 0x54, 0x4c, ++ 0xaa, 0x52, 0xfe, 0x31, 0x52, 0xea, 0xea, 0x97, 0x61, 0x73, 0x15, 0x6d, ++ 0x15, 0x4e, 0xa1, 0xdd, 0xbd, 0x15, 0xbc, 0x98, 0xc6, 0xaf, 0x73, 0xc7, ++ 0xf5, 0x56, 0x5e, 0xed, 0x0b, 0x32, 0x16, 0xd6, 0x63, 0xed, 0x30, 0xf8, ++ 0x6d, 0xb3, 0xb8, 0xd8, 0x4f, 0x24, 0x7c, 0x0c, 0x76, 0xce, 0xa4, 0x8e, ++ 0xe0, 0x3c, 0xa8, 0xe3, 0x61, 0x27, 0x8e, 0x73, 0xbd, 0x6f, 0x56, 0x3e, ++ 0x28, 0x1b, 0xcc, 0x45, 0xd9, 0x82, 0x74, 0x9e, 0x31, 0xcf, 0x32, 0x79, ++ 0xe0, 0x82, 0x07, 0x9e, 0x9c, 0x70, 0xb7, 0x43, 0x77, 0xc7, 0x24, 0x74, ++ 0x82, 0xe7, 0x80, 0x88, 0xf1, 0xfa, 0x80, 0xb7, 0xb6, 0x6a, 0xcc, 0x10, ++ 0x93, 0xf0, 0x89, 0x0e, 0x69, 0x04, 0xa6, 0x6e, 0x38, 0x42, 0xfb, 0xd8, ++ 0x95, 0x18, 0x06, 0xd3, 0xc2, 0xea, 0x6c, 0xa2, 0x3d, 0xf4, 0x9a, 0xf4, ++ 0x25, 0x5e, 0x13, 0x62, 0xa5, 0x2b, 0xe0, 0x9f, 0xed, 0x5e, 0xd8, 0xa4, ++ 0x7c, 0x71, 0xad, 0x3c, 0x64, 0x89, 0xb1, 0x36, 0xd6, 0x61, 0xec, 0xad, ++ 0x6b, 0xe8, 0xa7, 0x8c, 0xb9, 0xc1, 0xf7, 0x6c, 0x38, 0xeb, 0x8f, 0xc1, ++ 0x5c, 0x6a, 0x93, 0xca, 0x29, 0xae, 0x53, 0xc6, 0x5d, 0x2c, 0xdf, 0x6f, ++ 0x2d, 0xd3, 0x7f, 0xe5, 0xf7, 0x84, 0xfe, 0xde, 0xa9, 0xbf, 0xd3, 0x3f, ++ 0xa5, 0xfd, 0x83, 0xbd, 0x83, 0x0e, 0xbd, 0x73, 0xc0, 0x51, 0x36, 0xef, ++ 0xce, 0x55, 0x9e, 0xed, 0x16, 0xf3, 0x28, 0xfc, 0xd6, 0xf2, 0x41, 0x71, ++ 0x76, 0x2c, 0x27, 0xc3, 0x32, 0x0e, 0x5e, 0xf0, 0x5d, 0xd9, 0xcb, 0xe4, ++ 0x83, 0xb2, 0x5f, 0xf1, 0xa6, 0x72, 0xdc, 0x3e, 0x9c, 0x30, 0xa6, 0xc5, ++ 0xac, 0x28, 0xfb, 0x86, 0xf4, 0x41, 0x60, 0x1d, 0x3f, 0x96, 0x69, 0x56, ++ 0xd6, 0xd3, 0x12, 0xf8, 0x02, 0xb6, 0xb5, 0x7f, 0xd3, 0x98, 0x17, 0xbf, ++ 0x0f, 0x4b, 0x60, 0x7b, 0xd7, 0xe2, 0x5e, 0x59, 0x93, 0x38, 0x26, 0xf8, ++ 0x4e, 0x5e, 0x90, 0x5f, 0xb0, 0xc3, 0xc7, 0x83, 0x18, 0x58, 0xab, 0xe6, ++ 0x0b, 0xf9, 0x53, 0x92, 0xc7, 0x2d, 0x7b, 0x94, 0xf2, 0xf7, 0xd1, 0x81, ++ 0x6b, 0x24, 0xd7, 0xce, 0xf8, 0x5b, 0xfd, 0x18, 0x36, 0xc6, 0xd5, 0xea, ++ 0xfb, 0xdf, 0x18, 0x8f, 0x63, 0xdf, 0x7e, 0xcc, 0x2d, 0xb3, 0x2e, 0xe6, ++ 0x56, 0xdf, 0x1f, 0xfb, 0xda, 0x0a, 0xdf, 0xa9, 0xe0, 0xc5, 0x1c, 0xf2, ++ 0xa8, 0x3b, 0x31, 0xc7, 0xf7, 0x6f, 0x9a, 0xe0, 0x63, 0x0c, 0xb6, 0x84, ++ 0xbc, 0x0c, 0xf6, 0xa2, 0xc9, 0xd3, 0xae, 0xc4, 0x83, 0x3e, 0x3f, 0x87, ++ 0x7c, 0xbe, 0xfb, 0xfc, 0xbf, 0xb0, 0xca, 0x47, 0xda, 0x08, 0xf2, 0xb1, ++ 0x5d, 0x04, 0xba, 0xd6, 0x3c, 0x42, 0x1e, 0x32, 0x25, 0x0f, 0xf9, 0x8d, ++ 0x3c, 0xec, 0xd4, 0xdf, 0xc8, 0x3f, 0x60, 0xb4, 0xaf, 0x03, 0x67, 0xb8, ++ 0x19, 0x75, 0xa7, 0xa7, 0xb3, 0x27, 0x58, 0x8b, 0x49, 0x79, 0x72, 0xa1, ++ 0x49, 0xac, 0x94, 0x3f, 0xaf, 0x89, 0x75, 0xf1, 0x77, 0xee, 0x67, 0xf5, ++ 0x13, 0x77, 0x06, 0xf3, 0x8a, 0x73, 0x5e, 0xfb, 0xe5, 0x12, 0x30, 0x4e, ++ 0x18, 0xfe, 0x5f, 0x12, 0x18, 0xa7, 0x1f, 0x3a, 0x97, 0xbe, 0x39, 0xf2, ++ 0xaa, 0xc4, 0x2c, 0xb4, 0x77, 0x49, 0xac, 0x15, 0xea, 0x61, 0x62, 0x12, ++ 0x60, 0xad, 0xf9, 0x40, 0xc7, 0xa0, 0x7d, 0x33, 0x68, 0x9f, 0x74, 0x4e, ++ 0x5f, 0x77, 0x95, 0x2c, 0x27, 0xae, 0x12, 0x3b, 0xb1, 0x28, 0x6b, 0x7c, ++ 0x9d, 0xd8, 0x9c, 0xee, 0xee, 0x9d, 0xa1, 0x35, 0xd9, 0x98, 0xd8, 0x84, ++ 0xf7, 0x53, 0x12, 0x7c, 0x0f, 0x78, 0xbf, 0x29, 0x1f, 0x0a, 0x2f, 0x09, ++ 0x79, 0x41, 0x1a, 0x10, 0xc3, 0x45, 0xe4, 0x9f, 0xc5, 0xb8, 0x1e, 0x0b, ++ 0x6a, 0xbf, 0xb3, 0xcb, 0xec, 0x51, 0x3a, 0x63, 0xd8, 0xf5, 0xe5, 0xb5, ++ 0x80, 0x7e, 0xa2, 0xdd, 0xff, 0xdc, 0x1b, 0x8e, 0xc1, 0xc7, 0xed, 0xa6, ++ 0x7e, 0x09, 0xd6, 0x74, 0x93, 0x5a, 0xd3, 0x0f, 0xbb, 0x86, 0x14, 0x1d, ++ 0x43, 0xa6, 0x9d, 0x83, 0x0a, 0xdf, 0x7f, 0x06, 0x6d, 0x7d, 0x4e, 0xb7, ++ 0x35, 0x2d, 0x3d, 0x5a, 0xff, 0x1c, 0x80, 0x9c, 0x7b, 0x72, 0x87, 0x3b, ++ 0x20, 0x1f, 0xdd, 0xce, 0x35, 0x10, 0xcc, 0xff, 0xa0, 0x74, 0x0f, 0x2c, ++ 0x27, 0xe0, 0x15, 0x5c, 0x17, 0x59, 0xa5, 0x01, 0xd7, 0x59, 0x20, 0xdf, ++ 0x3e, 0x1d, 0xfc, 0xf9, 0xaf, 0x9b, 0xab, 0x9e, 0x27, 0xe7, 0xcc, 0x72, ++ 0x9c, 0x6b, 0x80, 0x43, 0x83, 0xb9, 0x06, 0xe5, 0x5b, 0x20, 0x4b, 0x76, ++ 0x42, 0x8c, 0x7a, 0xda, 0xac, 0xea, 0xa8, 0x51, 0xc6, 0x4c, 0x78, 0x77, ++ 0x20, 0x61, 0x04, 0xb1, 0x69, 0xa5, 0x3b, 0xe3, 0x9d, 0xc0, 0xe0, 0x4e, ++ 0x4f, 0x4f, 0x32, 0xaf, 0x62, 0xa6, 0xa6, 0x9a, 0xd7, 0x34, 0x70, 0xd9, ++ 0x82, 0xfb, 0x92, 0xf7, 0x45, 0xe0, 0xd6, 0x9c, 0xdc, 0x27, 0xa1, 0x75, ++ 0xb1, 0x5d, 0xbc, 0x9f, 0x63, 0x7c, 0xd7, 0x4e, 0xa4, 0xc1, 0xe3, 0xdf, ++ 0x83, 0xff, 0x5e, 0x81, 0xde, 0xff, 0x2c, 0x6d, 0x43, 0x19, 0xf6, 0x02, ++ 0xd8, 0xe4, 0xbb, 0xef, 0x8a, 0xdf, 0x73, 0x75, 0xb1, 0x5d, 0x1f, 0xa3, ++ 0x3e, 0xae, 0x70, 0x29, 0x31, 0xfb, 0x61, 0xe3, 0xb6, 0xde, 0x10, 0x7c, ++ 0x8c, 0x82, 0x17, 0x75, 0x88, 0xe5, 0x0e, 0xca, 0x2d, 0xe0, 0xcf, 0x99, ++ 0x85, 0x82, 0xb1, 0xab, 0x1c, 0xc8, 0x2a, 0x7c, 0xca, 0x9a, 0x9d, 0x5c, ++ 0x01, 0x3d, 0x1e, 0xd5, 0xb8, 0x8f, 0xfb, 0x37, 0x15, 0xed, 0xaf, 0x30, ++ 0x56, 0x54, 0xac, 0x1d, 0x94, 0x19, 0xd7, 0xf4, 0xcf, 0x93, 0xc5, 0xd2, ++ 0xd7, 0x34, 0xae, 0xd2, 0xc8, 0x06, 0x26, 0xb7, 0x93, 0xd4, 0xdf, 0x15, ++ 0xbd, 0xff, 0xf1, 0xa8, 0x92, 0xaf, 0x00, 0xd3, 0x13, 0xa3, 0x13, 0xbf, ++ 0x77, 0x5b, 0xa3, 0x7c, 0x9e, 0xa7, 0x0c, 0x68, 0xdc, 0xee, 0xde, 0x23, ++ 0xe9, 0xf1, 0x84, 0xc2, 0x2e, 0x0f, 0x95, 0xb9, 0x5e, 0x88, 0xfd, 0x2f, ++ 0xc9, 0x0a, 0xd6, 0x07, 0x7d, 0x07, 0xf8, 0x00, 0xe8, 0x9b, 0xeb, 0x02, ++ 0x79, 0x55, 0xeb, 0x1d, 0xd6, 0xc5, 0x42, 0x2b, 0x71, 0xc6, 0x73, 0x65, ++ 0xee, 0x8d, 0xd9, 0x89, 0x65, 0x09, 0x62, 0xe9, 0x0a, 0x0f, 0x16, 0x32, ++ 0x21, 0x43, 0xba, 0x8e, 0xfd, 0x4b, 0xc8, 0xd0, 0xef, 0xc2, 0x3f, 0x62, ++ 0x39, 0x51, 0xfb, 0x59, 0xc3, 0xc0, 0x5d, 0xa6, 0xf3, 0x3e, 0x29, 0x5a, ++ 0x11, 0x29, 0xaa, 0xb3, 0x9a, 0x11, 0x15, 0x7b, 0xa2, 0xcd, 0x2f, 0x5a, ++ 0xc4, 0xfd, 0x8b, 0xad, 0xbe, 0xad, 0x6f, 0xc3, 0x3b, 0xeb, 0xf1, 0x9d, ++ 0xf9, 0xd3, 0x12, 0x39, 0x76, 0x40, 0x1a, 0x8e, 0xdd, 0x27, 0x8d, 0x47, ++ 0x89, 0xf3, 0x18, 0x33, 0x33, 0x6f, 0x6c, 0x14, 0xe2, 0xee, 0x66, 0xf0, ++ 0xf0, 0xa0, 0xfc, 0xdc, 0x0d, 0xc6, 0xf4, 0x05, 0x8c, 0x91, 0x65, 0x82, ++ 0xf7, 0x00, 0x93, 0xdf, 0x88, 0xf1, 0x70, 0xfe, 0x09, 0x8d, 0xfd, 0x6e, ++ 0xac, 0xf3, 0x5b, 0x1b, 0xb4, 0xdf, 0xca, 0x7a, 0x43, 0x98, 0xcb, 0x71, ++ 0x89, 0x38, 0x41, 0xfd, 0x9b, 0x50, 0x2e, 0x5e, 0x77, 0x26, 0x82, 0x65, ++ 0xf4, 0x19, 0x81, 0x56, 0x62, 0x1f, 0xee, 0xbf, 0x33, 0xcf, 0x3f, 0x03, ++ 0x60, 0x56, 0x9a, 0x43, 0xeb, 0xfb, 0xdf, 0x59, 0x57, 0x36, 0xc8, 0x0b, ++ 0xea, 0x44, 0x7c, 0x7f, 0x7f, 0x30, 0x52, 0x57, 0x6f, 0x8f, 0xe5, 0xa7, ++ 0xbe, 0xff, 0xe1, 0xfb, 0x42, 0x9c, 0x43, 0xb2, 0x0e, 0xe7, 0xd4, 0xfb, ++ 0x1f, 0xbc, 0xef, 0x12, 0x85, 0xcf, 0x1a, 0x9c, 0x2b, 0x33, 0x31, 0x17, ++ 0xbb, 0x40, 0x1f, 0xc6, 0xe2, 0xd9, 0xdc, 0xb9, 0x02, 0xf7, 0xe8, 0xd4, ++ 0xd9, 0x22, 0x9e, 0xe5, 0x40, 0xb9, 0x84, 0x8f, 0x41, 0xf9, 0x1e, 0x07, ++ 0xcf, 0x6f, 0xe8, 0x30, 0x53, 0xff, 0xe3, 0x9a, 0xcc, 0x20, 0xf1, 0xcd, ++ 0x36, 0xee, 0x4b, 0x02, 0x3b, 0xab, 0x33, 0x7f, 0x90, 0xb3, 0x46, 0xb5, ++ 0x0f, 0x54, 0x2c, 0xd3, 0xa7, 0xcb, 0x43, 0x7e, 0x78, 0x3e, 0x8e, 0xbe, ++ 0x5f, 0x5e, 0xc7, 0x67, 0x39, 0x4e, 0xe2, 0xfa, 0xc0, 0x47, 0x60, 0x9b, ++ 0x9b, 0xdd, 0x79, 0x0c, 0xfc, 0x36, 0xca, 0x5b, 0x5c, 0x8d, 0x79, 0x64, ++ 0x83, 0xcf, 0xf2, 0x20, 0x74, 0xc1, 0x02, 0xe4, 0x79, 0x0a, 0x3a, 0x70, ++ 0x38, 0xc4, 0xf5, 0xa9, 0x6c, 0xb5, 0xda, 0x17, 0xce, 0xaa, 0xfb, 0x77, ++ 0xb0, 0x1d, 0x47, 0x5f, 0x95, 0x69, 0xe8, 0xff, 0x99, 0x5a, 0x97, 0xba, ++ 0xb3, 0x93, 0x8e, 0xf3, 0x4c, 0x18, 0xf3, 0x3b, 0xd0, 0xff, 0xab, 0xc0, ++ 0xc4, 0xcd, 0xa0, 0xa7, 0xa9, 0x79, 0xf5, 0x11, 0x1d, 0x87, 0x8a, 0x32, ++ 0x36, 0x0f, 0xbd, 0x59, 0xf4, 0xb1, 0x66, 0x6c, 0x06, 0xe9, 0x7f, 0xd0, ++ 0xd8, 0xf2, 0x23, 0xdb, 0x7c, 0x79, 0xe3, 0x39, 0xf0, 0x43, 0x42, 0x1a, ++ 0xfb, 0x73, 0xb2, 0xb5, 0xbf, 0x12, 0x81, 0xcc, 0x71, 0x5e, 0x1f, 0x44, ++ 0x39, 0xca, 0x5a, 0xaf, 0xde, 0xab, 0x6d, 0x52, 0xfa, 0x31, 0x0b, 0x59, ++ 0xca, 0x2b, 0x5f, 0x02, 0x18, 0xdf, 0x65, 0xbd, 0x6b, 0xb7, 0x71, 0x2f, ++ 0xb4, 0xc1, 0x51, 0xfe, 0x45, 0x7b, 0x48, 0x82, 0xbc, 0x9b, 0x91, 0x47, ++ 0x39, 0x7b, 0x1f, 0x78, 0xc3, 0xbc, 0x0c, 0xde, 0xd9, 0xd7, 0x35, 0xba, ++ 0x1f, 0xf6, 0xf1, 0x70, 0xf3, 0xfa, 0x31, 0x71, 0x2e, 0xed, 0x7a, 0x2e, ++ 0x0d, 0xbc, 0x93, 0xa2, 0xf3, 0xde, 0xa7, 0xf3, 0xc2, 0x7a, 0x7e, 0xdf, ++ 0xd2, 0x77, 0x1a, 0xec, 0xc3, 0x69, 0x09, 0xd6, 0x27, 0xc7, 0x17, 0x55, ++ 0xf5, 0xd2, 0x96, 0x2f, 0x3b, 0x0f, 0x82, 0x1f, 0xe1, 0xd4, 0x43, 0xdc, ++ 0xa3, 0x05, 0x7d, 0x83, 0x35, 0x11, 0x57, 0xbe, 0x67, 0xc2, 0xf4, 0xcf, ++ 0x32, 0x3d, 0xbe, 0xee, 0x3e, 0x41, 0x70, 0x1e, 0xdc, 0x91, 0xf1, 0x55, ++ 0x5e, 0x91, 0x6f, 0xe4, 0xd7, 0x3b, 0xf1, 0x8a, 0x7c, 0x24, 0xbf, 0xf2, ++ 0x52, 0x9c, 0x25, 0x9f, 0x28, 0x2f, 0xe3, 0x4a, 0x5e, 0x8a, 0xf3, 0x01, ++ 0x4e, 0xa6, 0x2e, 0xe1, 0x5d, 0x87, 0xcd, 0xf6, 0xef, 0x83, 0xb3, 0x62, ++ 0x1f, 0x20, 0xfd, 0x8c, 0x91, 0xde, 0x2d, 0xb2, 0x30, 0xab, 0x74, 0x0a, ++ 0xec, 0x62, 0x5c, 0xe9, 0x8a, 0xfc, 0x04, 0xdf, 0xf7, 0x83, 0x46, 0x3c, ++ 0x5f, 0xc2, 0xfc, 0x76, 0xcd, 0xd7, 0xf7, 0xa9, 0xf3, 0x4e, 0x5c, 0x83, ++ 0xc5, 0xf9, 0x2f, 0xab, 0xef, 0x67, 0xe6, 0x1a, 0x54, 0xf9, 0x33, 0x73, ++ 0x1b, 0xcf, 0x2c, 0x31, 0xef, 0xfd, 0x72, 0x7a, 0x56, 0x64, 0xb1, 0xd4, ++ 0x20, 0x4b, 0x73, 0x53, 0xf4, 0x15, 0x53, 0x8d, 0x6b, 0xf7, 0x3a, 0xd4, ++ 0xdd, 0xb8, 0xe2, 0x9c, 0x27, 0x23, 0x90, 0x9b, 0x85, 0xa1, 0x19, 0xa9, ++ 0x0c, 0xd1, 0x17, 0x52, 0x67, 0x09, 0x31, 0xdf, 0x06, 0x60, 0x60, 0xe0, ++ 0x42, 0x87, 0xb1, 0xe7, 0xad, 0x5a, 0x9f, 0x7c, 0xb4, 0x25, 0x88, 0x49, ++ 0x57, 0x62, 0x05, 0xaf, 0xe2, 0x04, 0x77, 0x65, 0xd8, 0x26, 0xef, 0xcb, ++ 0x90, 0x67, 0x26, 0xea, 0xf3, 0x8c, 0x26, 0x70, 0xaa, 0xf3, 0x8a, 0xd6, ++ 0x75, 0x41, 0xec, 0xfd, 0x66, 0xcd, 0xf7, 0x7f, 0xac, 0xd3, 0x07, 0x64, ++ 0xf2, 0xf8, 0x97, 0x79, 0x0e, 0x3f, 0xb8, 0xe3, 0x58, 0x77, 0xbf, 0x25, ++ 0xac, 0xef, 0x6a, 0x3c, 0x80, 0x3c, 0xc6, 0xe1, 0x1e, 0x50, 0x73, 0xe2, ++ 0x59, 0xbf, 0x82, 0xbc, 0xd7, 0x99, 0x95, 0xc0, 0x27, 0xe4, 0x79, 0xaa, ++ 0x26, 0xdd, 0xde, 0x2e, 0x2d, 0x4b, 0x13, 0x32, 0x09, 0x7b, 0x97, 0x2f, ++ 0x7f, 0x45, 0x9d, 0x41, 0xcb, 0x85, 0xea, 0xfb, 0x0c, 0xd6, 0x93, 0x1f, ++ 0x6f, 0x08, 0xce, 0x42, 0x84, 0x94, 0x4f, 0xb4, 0x1a, 0xbb, 0xd0, 0xf9, ++ 0x13, 0xb2, 0xaf, 0xac, 0x62, 0x18, 0x6a, 0x0f, 0x73, 0x06, 0x7a, 0x61, ++ 0x58, 0xd9, 0xb4, 0xa8, 0x31, 0x52, 0x4d, 0x49, 0xfe, 0xd4, 0x6e, 0xf4, ++ 0xc3, 0x38, 0x60, 0x5a, 0xef, 0x15, 0xee, 0x95, 0xc9, 0x9a, 0xdf, 0xf7, ++ 0x54, 0x99, 0xdf, 0xbb, 0x80, 0x13, 0xf8, 0x3d, 0x1b, 0xf7, 0xef, 0x60, ++ 0x5e, 0x8f, 0xba, 0x0d, 0x9a, 0xce, 0x3c, 0x7f, 0xcd, 0xfa, 0xd4, 0x01, ++ 0x6f, 0x80, 0x56, 0x59, 0x7c, 0x67, 0x9d, 0xa0, 0xbd, 0x29, 0xd8, 0x2d, ++ 0xfa, 0xe8, 0xf7, 0xcb, 0xf2, 0xfc, 0x8c, 0xac, 0xcc, 0x07, 0xb2, 0xce, ++ 0xb3, 0xd8, 0x1c, 0xfb, 0x2d, 0xea, 0x8e, 0xe5, 0x73, 0xe5, 0x34, 0xf8, ++ 0xb3, 0x9e, 0x56, 0xd9, 0x75, 0xf7, 0x6c, 0xd0, 0x9b, 0xba, 0xab, 0x78, ++ 0x93, 0x3a, 0xd3, 0xb5, 0x7e, 0xcd, 0xb1, 0x9d, 0x7e, 0x8b, 0x7b, 0x1d, ++ 0xfe, 0xb9, 0xb4, 0xf6, 0xba, 0xef, 0x31, 0x7d, 0x16, 0xec, 0x93, 0x96, ++ 0xcf, 0x47, 0xd2, 0x73, 0x5c, 0x8f, 0x37, 0x89, 0xf5, 0xcf, 0x36, 0x0f, ++ 0x69, 0xbe, 0x21, 0x5d, 0x38, 0xa4, 0xce, 0xdc, 0x65, 0xfa, 0x2d, 0x7d, ++ 0x16, 0xbf, 0xfe, 0x0c, 0x5e, 0x43, 0x5d, 0x7f, 0xac, 0x47, 0xbb, 0x14, ++ 0x9c, 0x05, 0x67, 0xde, 0x71, 0x7d, 0xd6, 0xef, 0x4c, 0x5d, 0x5e, 0x70, ++ 0x26, 0x8d, 0x74, 0x62, 0x1c, 0x13, 0x69, 0x6d, 0x5c, 0x3f, 0x8f, 0xd7, ++ 0xdd, 0x95, 0x09, 0xda, 0x0c, 0xb3, 0x0d, 0x7d, 0xbe, 0xac, 0xfe, 0x6c, ++ 0x31, 0xef, 0x07, 0x51, 0x06, 0x4d, 0xde, 0x23, 0xa6, 0xff, 0x07, 0xcc, ++ 0xb6, 0x55, 0xa6, 0xd4, 0x78, 0x0a, 0xea, 0xdc, 0x06, 0xef, 0xcf, 0x0c, ++ 0x5b, 0xfe, 0xfb, 0xd4, 0xc2, 0x46, 0xf9, 0x64, 0xfe, 0x17, 0x1a, 0xa5, ++ 0xa9, 0x80, 0x7e, 0xf8, 0x7d, 0xfd, 0xfd, 0x53, 0xdf, 0x76, 0x71, 0x5d, ++ 0xba, 0xa8, 0xe3, 0xa2, 0xce, 0xc3, 0x94, 0xf3, 0x42, 0x61, 0xf5, 0xbc, ++ 0x68, 0xc1, 0xbf, 0xc3, 0x64, 0x06, 0xe7, 0x36, 0x79, 0x47, 0x5a, 0xe4, ++ 0x7c, 0x95, 0xf7, 0x93, 0x6e, 0x52, 0xe7, 0x69, 0xfc, 0x3d, 0x4a, 0x8e, ++ 0xab, 0x5b, 0xd9, 0x83, 0x4a, 0xb5, 0x88, 0x6f, 0x81, 0x4d, 0x8f, 0x68, ++ 0x9b, 0x4e, 0xdd, 0x35, 0x0a, 0xdd, 0xf5, 0x80, 0xe6, 0x07, 0xeb, 0xa7, ++ 0xd5, 0x39, 0xef, 0x74, 0x8c, 0x7b, 0x64, 0x87, 0xd4, 0x5c, 0x68, 0x1f, ++ 0x50, 0xf7, 0x83, 0x21, 0x15, 0xeb, 0x54, 0x77, 0xb0, 0x21, 0x97, 0xbc, ++ 0x57, 0x0d, 0xdd, 0x5e, 0xe6, 0xfd, 0xe9, 0x51, 0xa4, 0xbc, 0x3b, 0xbd, ++ 0x5b, 0x9d, 0xff, 0xaf, 0xa8, 0x3b, 0x01, 0x81, 0x1c, 0x86, 0x74, 0x5f, ++ 0xc7, 0xd0, 0x87, 0xcf, 0xef, 0x7c, 0x99, 0x77, 0xdf, 0x83, 0xb3, 0xa6, ++ 0xcd, 0xcb, 0x5c, 0x0b, 0xa2, 0xfc, 0x7b, 0xff, 0xce, 0x75, 0x45, 0xdd, ++ 0x23, 0x48, 0xf0, 0xfe, 0x20, 0xec, 0xd6, 0x1e, 0x3c, 0x73, 0x7f, 0x79, ++ 0x2f, 0x52, 0xe8, 0x9d, 0x6a, 0x0e, 0xe9, 0x7d, 0x92, 0x55, 0x31, 0xbf, ++ 0x16, 0xbc, 0x4f, 0xa9, 0xbe, 0x8b, 0xd5, 0xbb, 0x65, 0xf2, 0xd4, 0x3d, ++ 0xbc, 0x2f, 0xa1, 0xee, 0x7e, 0x67, 0x5c, 0x8e, 0x31, 0x26, 0xd3, 0x6a, ++ 0xde, 0x05, 0x4d, 0xfb, 0x60, 0xff, 0xe5, 0xa2, 0xba, 0x9b, 0x51, 0xa8, ++ 0xb6, 0x60, 0x8c, 0x86, 0x3e, 0x6f, 0x4a, 0x3f, 0x20, 0x98, 0x7f, 0x13, ++ 0xcf, 0x30, 0x7a, 0xdc, 0x43, 0x9c, 0x2c, 0xf3, 0x3c, 0x69, 0x97, 0x8e, ++ 0x0f, 0x30, 0x6e, 0xc8, 0x3d, 0x09, 0xca, 0x36, 0xef, 0xe8, 0x66, 0x81, ++ 0xd2, 0xe2, 0xdc, 0xe3, 0xd6, 0x73, 0x69, 0xa9, 0x9b, 0x0b, 0xcf, 0xd0, ++ 0xfa, 0xf3, 0xe1, 0x7d, 0x88, 0x7c, 0xb9, 0xfe, 0x4e, 0x85, 0xba, 0x83, ++ 0xce, 0xbb, 0x33, 0x92, 0xab, 0xde, 0x2b, 0x77, 0x95, 0xb7, 0xea, 0xfb, ++ 0x14, 0x51, 0xb9, 0xab, 0xfa, 0xaa, 0xa2, 0x69, 0x5e, 0xdd, 0xeb, 0x88, ++ 0x68, 0x9e, 0x05, 0x77, 0x2a, 0xfc, 0xf6, 0xf6, 0xf1, 0xbe, 0xf6, 0x2a, ++ 0x96, 0x88, 0x48, 0x6e, 0xe1, 0x8f, 0xc3, 0x9b, 0xdf, 0x65, 0xb8, 0x5f, ++ 0x32, 0xa7, 0x68, 0x9b, 0x67, 0xe4, 0xa1, 0x79, 0xcf, 0xbb, 0xc5, 0x25, ++ 0xa6, 0x6c, 0x96, 0x95, 0xd8, 0xf8, 0xae, 0x9f, 0x3a, 0x6d, 0x46, 0x65, ++ 0xb6, 0x11, 0x6b, 0x8b, 0x38, 0x46, 0x9a, 0xf8, 0xbe, 0x30, 0xcb, 0xf5, ++ 0x19, 0xc6, 0x1c, 0x6d, 0xeb, 0x8a, 0xfc, 0xc6, 0x62, 0xcc, 0xed, 0x16, ++ 0xf8, 0xb0, 0xbf, 0xef, 0xfa, 0x7a, 0xfa, 0xab, 0x8b, 0xbb, 0xe5, 0xab, ++ 0xd5, 0xa8, 0x51, 0x29, 0xf1, 0xdc, 0xa1, 0x3d, 0x3a, 0x2f, 0x5d, 0x28, ++ 0xc7, 0xf6, 0x21, 0x2f, 0xf1, 0xab, 0xe4, 0xb1, 0xe3, 0x6f, 0x79, 0x57, ++ 0x1c, 0x7c, 0x87, 0x8e, 0x59, 0x71, 0x83, 0xb8, 0xe2, 0x38, 0x7c, 0x56, ++ 0x96, 0xbb, 0x0a, 0x72, 0x00, 0xcc, 0x80, 0x35, 0x47, 0xff, 0xf6, 0x8a, ++ 0xd6, 0x57, 0xe6, 0x91, 0x6b, 0xe5, 0xca, 0xea, 0xb9, 0xe5, 0x4b, 0x90, ++ 0xed, 0x84, 0x4f, 0x7f, 0x15, 0xb7, 0x3f, 0x20, 0xa1, 0xaf, 0xc3, 0x96, ++ 0x7c, 0xbd, 0x41, 0xe9, 0x74, 0xda, 0x34, 0xf8, 0x3e, 0xf0, 0x6f, 0xc2, ++ 0x68, 0xe7, 0x2f, 0xb4, 0xcc, 0xce, 0x88, 0x7c, 0x73, 0x8b, 0xa4, 0xb7, ++ 0xd3, 0x7f, 0x96, 0xf7, 0xd0, 0x5b, 0xf5, 0xeb, 0x2c, 0x29, 0xdf, 0xe2, ++ 0x1a, 0xaf, 0x71, 0x2e, 0x5d, 0xf1, 0xff, 0x26, 0x5f, 0x94, 0x5c, 0x9c, ++ 0x73, 0xb9, 0x5f, 0x0a, 0xf3, 0x87, 0xf0, 0xe3, 0x3c, 0x39, 0xee, 0x31, ++ 0x7d, 0xa6, 0x61, 0x5c, 0x8a, 0xa5, 0x94, 0x4c, 0xcf, 0x4d, 0xf1, 0xae, ++ 0xe9, 0xe8, 0x2d, 0x6a, 0x5f, 0xcf, 0x8e, 0x77, 0x19, 0x7d, 0x89, 0x69, ++ 0x9e, 0xe1, 0x50, 0xf3, 0x99, 0xc2, 0x7c, 0x7e, 0x77, 0x3b, 0xcf, 0xae, ++ 0x5f, 0x81, 0xde, 0x35, 0x4f, 0x50, 0x0e, 0x6d, 0xab, 0xd3, 0xe0, 0xfb, ++ 0x5e, 0xf8, 0xed, 0xcc, 0xdb, 0x2b, 0xa1, 0x23, 0xab, 0xfa, 0x1d, 0xf9, ++ 0x7d, 0x6a, 0x8d, 0xf8, 0xb4, 0xfa, 0x2c, 0xea, 0xa2, 0xdc, 0x91, 0xa0, ++ 0x6e, 0x50, 0x86, 0x75, 0x39, 0xcf, 0xdd, 0xd2, 0x78, 0x36, 0x18, 0x17, ++ 0xe4, 0x30, 0x5e, 0x4f, 0xef, 0xa6, 0x0d, 0xf4, 0x0e, 0x13, 0xeb, 0x82, ++ 0x5e, 0xa4, 0x71, 0x48, 0xd3, 0xb8, 0x80, 0xf6, 0x03, 0x1e, 0xdc, 0x82, ++ 0x3c, 0x4b, 0xdf, 0x49, 0xfa, 0x6d, 0xe8, 0x4e, 0x9a, 0xb3, 0xfc, 0x5f, ++ 0xe8, 0x7b, 0x4d, 0x1c, 0xcf, 0x66, 0x34, 0x5f, 0xda, 0xee, 0xf3, 0x65, ++ 0x2f, 0xe8, 0xc5, 0xf3, 0xa5, 0x7d, 0xea, 0x9e, 0x41, 0x7a, 0x62, 0x2f, ++ 0x64, 0x27, 0x98, 0x57, 0x1f, 0x64, 0x8c, 0x7b, 0x26, 0x2c, 0x5f, 0x4f, ++ 0x13, 0xdf, 0xde, 0x85, 0x18, 0xf3, 0x70, 0x38, 0x57, 0xe0, 0xd1, 0x6f, ++ 0xd2, 0x36, 0xf1, 0x9e, 0xfb, 0xfb, 0xb5, 0x6d, 0x7a, 0x2f, 0x1e, 0xff, ++ 0xc9, 0x76, 0xdf, 0x36, 0x59, 0xa0, 0x49, 0xab, 0xae, 0xb3, 0x17, 0xd8, ++ 0x98, 0xb1, 0xe0, 0xae, 0xf8, 0xe7, 0x24, 0xe8, 0xc7, 0xbb, 0x89, 0xfe, ++ 0xee, 0xf0, 0x60, 0x1f, 0xd0, 0x8a, 0x3a, 0xbb, 0x13, 0xe7, 0x59, 0xa0, ++ 0x2e, 0x63, 0xaf, 0x3a, 0xc7, 0xb1, 0xfe, 0x1e, 0x49, 0x52, 0x1e, 0x5b, ++ 0x93, 0x95, 0xd1, 0x5f, 0x88, 0x2d, 0x89, 0x6b, 0x28, 0x2b, 0x6c, 0x77, ++ 0x8a, 0xf3, 0x8c, 0xdf, 0xa3, 0xe6, 0x09, 0x3b, 0x35, 0xce, 0x33, 0x17, ++ 0x96, 0x51, 0x99, 0x23, 0xdf, 0x91, 0x2e, 0xf2, 0x39, 0xd8, 0xe3, 0x55, ++ 0x7a, 0x05, 0xfd, 0x32, 0x8f, 0xba, 0x91, 0xdf, 0x53, 0x7a, 0x0f, 0xf8, ++ 0x3f, 0x52, 0x6e, 0x30, 0x2e, 0xcb, 0x98, 0x5f, 0xdc, 0x7c, 0x6c, 0xbf, ++ 0xaf, 0xe4, 0xe0, 0x7e, 0xd0, 0xbd, 0xb3, 0x4d, 0x9a, 0x0e, 0x21, 0xe5, ++ 0x1c, 0x53, 0xab, 0x7c, 0x27, 0xbd, 0x3f, 0x25, 0x43, 0x90, 0x0b, 0xbe, ++ 0xdf, 0x0f, 0x9c, 0x49, 0x3b, 0x8a, 0x74, 0x9e, 0xcf, 0xd4, 0xf5, 0x8e, ++ 0x3e, 0x57, 0xc5, 0xb1, 0xec, 0xc5, 0x58, 0xd4, 0x3c, 0xb5, 0x3c, 0xed, ++ 0xd1, 0xf5, 0x26, 0x56, 0x69, 0x75, 0xcf, 0xdb, 0x70, 0x46, 0x64, 0x15, ++ 0x67, 0xf8, 0x7d, 0x6d, 0x69, 0x0b, 0x30, 0x86, 0x3f, 0x07, 0x1f, 0x63, ++ 0xf8, 0x72, 0x3e, 0x25, 0x61, 0xc8, 0x71, 0x68, 0x4d, 0x8e, 0x81, 0x77, ++ 0xfc, 0x35, 0x33, 0xcd, 0x7d, 0x37, 0x45, 0x67, 0xca, 0x21, 0xe5, 0x97, ++ 0x7c, 0xac, 0xe7, 0xf5, 0xc7, 0xde, 0x81, 0xd7, 0x9f, 0x6e, 0x0b, 0x70, ++ 0xc3, 0xdf, 0x6d, 0x1d, 0x64, 0xda, 0xd6, 0xd6, 0xc1, 0xb5, 0xff, 0x8f, ++ 0xd6, 0xc1, 0x46, 0xb9, 0xac, 0x97, 0x29, 0x0b, 0xf2, 0x44, 0x7e, 0x51, ++ 0x9e, 0x28, 0x47, 0xa4, 0x25, 0xf5, 0x69, 0x23, 0xfd, 0xb6, 0xf8, 0x65, ++ 0xb5, 0x17, 0x38, 0x03, 0x1d, 0xd4, 0x66, 0xcc, 0xcf, 0xc7, 0xa4, 0xb8, ++ 0xf8, 0x8c, 0x92, 0xe9, 0xc7, 0x6a, 0xd4, 0x4b, 0xef, 0x36, 0xf7, 0xf5, ++ 0x3a, 0x37, 0xbf, 0x41, 0xe7, 0xe6, 0x57, 0x75, 0xee, 0x76, 0xed, 0xab, ++ 0xfd, 0x5d, 0x74, 0x6e, 0xac, 0x6e, 0x5f, 0x28, 0xd8, 0x13, 0x12, 0x23, ++ 0xd3, 0xdb, 0x24, 0xbb, 0x60, 0x47, 0x46, 0x4b, 0xbb, 0xe5, 0x0f, 0x4a, ++ 0x33, 0xea, 0xbc, 0xd4, 0x8f, 0xdc, 0xae, 0xf8, 0xdd, 0x86, 0x27, 0x9f, ++ 0x82, 0xaf, 0x9d, 0xeb, 0x68, 0x90, 0x5d, 0x37, 0xa8, 0xbd, 0x4e, 0x2b, ++ 0x63, 0xb4, 0x0b, 0x23, 0xf0, 0x59, 0xd7, 0x76, 0x13, 0x06, 0xcf, 0xce, ++ 0x35, 0x4a, 0x2e, 0xd6, 0x22, 0xbb, 0x81, 0x9d, 0x0a, 0x57, 0x13, 0xf7, ++ 0x34, 0xab, 0x7b, 0x49, 0xcf, 0x95, 0xab, 0x9a, 0xef, 0xa0, 0x43, 0xab, ++ 0x25, 0x7f, 0x54, 0xab, 0xb6, 0xf9, 0xff, 0x03, 0x65, 0x60, 0xc3, 0x3b, ++ 0x9f, 0x6f, 0x87, 0x1f, 0x17, 0x03, 0xad, 0xea, 0xcf, 0x21, 0x85, 0x14, ++ 0x3d, 0x8b, 0xf3, 0x13, 0xea, 0x7c, 0xd7, 0xe5, 0x10, 0xe9, 0xa5, 0x7c, ++ 0xa7, 0x78, 0x26, 0x04, 0x8c, 0x33, 0x0b, 0x04, 0xed, 0xd0, 0xdf, 0xd4, ++ 0xb8, 0x13, 0xfa, 0x7f, 0x72, 0x56, 0xdd, 0xa3, 0x02, 0x6d, 0x3c, 0x15, ++ 0x77, 0xce, 0xc7, 0x88, 0xe7, 0xd7, 0xce, 0x32, 0xbf, 0x1d, 0xd7, 0x2b, ++ 0x4c, 0x1f, 0xec, 0x81, 0xe8, 0x38, 0x95, 0xf6, 0xff, 0xd5, 0xbe, 0xde, ++ 0x46, 0x5a, 0x05, 0x7e, 0x3f, 0xef, 0xf1, 0x13, 0xdb, 0xd9, 0x87, 0xe7, ++ 0xe5, 0x49, 0xe5, 0x83, 0xa6, 0x49, 0xdf, 0x0a, 0xf8, 0x74, 0x34, 0x1e, ++ 0xd8, 0x73, 0xa3, 0xf3, 0x5c, 0xbd, 0x0f, 0xca, 0x36, 0xa2, 0xea, 0x1c, ++ 0xc8, 0xda, 0xff, 0xe1, 0x61, 0x6c, 0x29, 0x6d, 0xdc, 0x56, 0x9e, 0x91, ++ 0xd0, 0xb1, 0x71, 0x09, 0x1f, 0x65, 0x1c, 0x3f, 0x2d, 0xc5, 0x98, 0x27, ++ 0x77, 0xb9, 0xeb, 0x7d, 0x92, 0x4e, 0x73, 0xe3, 0xd8, 0xef, 0x97, 0xe1, ++ 0x53, 0x87, 0x24, 0x72, 0x8c, 0xdf, 0xd6, 0xed, 0xe1, 0x40, 0x1f, 0x35, ++ 0xcb, 0x7c, 0x8c, 0xb1, 0xec, 0x88, 0xba, 0x4b, 0xbd, 0x32, 0xf1, 0x6a, ++ 0xa4, 0x08, 0xac, 0x90, 0x57, 0xba, 0x05, 0xe9, 0xaa, 0x0f, 0xd1, 0x7c, ++ 0x15, 0xd7, 0x14, 0xfc, 0x4c, 0x23, 0x37, 0x1f, 0xf1, 0xcf, 0x25, 0xc5, ++ 0x58, 0xf6, 0x10, 0xfc, 0x6d, 0xe2, 0x0c, 0xe8, 0x8e, 0x71, 0x69, 0xe2, ++ 0x7b, 0xe8, 0xd8, 0x1a, 0xce, 0xa0, 0x4e, 0x18, 0x76, 0x63, 0x12, 0x3e, ++ 0xed, 0xcf, 0x9d, 0xff, 0xbc, 0xc7, 0x3c, 0xb9, 0x5b, 0x42, 0x47, 0xf9, ++ 0x5c, 0xef, 0x07, 0x11, 0xbb, 0xc3, 0x36, 0x9c, 0xfb, 0x0a, 0xda, 0xe3, ++ 0xb7, 0xb4, 0xbe, 0x87, 0x8b, 0xf7, 0xca, 0xdf, 0xf4, 0x7f, 0x02, 0x50, ++ 0xf6, 0xff, 0x2f, 0x8c, 0xe0, 0xd9, 0x60, 0xcc, 0x4c, 0x00, 0x00, 0x00 }; + + static const u32 bnx2_COM_b06FwData[(0x0/4) + 1] = { 0x0 }; + static const u32 bnx2_COM_b06FwRodata[(0x14/4) + 1] = { +- 0x08000f04, 0x08000f4c, 0x08000f80, 0x08000fcc, 0x08001000, 0x00000000 ++ 0x08000d98, 0x08000de0, 0x08000e20, 0x08000e6c, 0x08000ea0, 0x00000000 + }; + + static struct fw_info bnx2_com_fw_06 = { +- /* Firmware version: 4.0.5 */ +- .ver_major = 0x4, +- .ver_minor = 0x0, +- .ver_fix = 0x5, +- +- .start_addr = 0x080000f8, ++ /* Firmware version: 5.0.0j */ ++ .ver_major = 0x5, ++ .ver_minor = 0x0, ++ .ver_fix = 0x0, ++ ++ .start_addr = 0x08000110, + + .text_addr = 0x08000000, +- .text_len = 0x4eac, ++ .text_len = 0x4cc8, + .text_index = 0x0, + .gz_text = bnx2_COM_b06FwText, + .gz_text_len = sizeof(bnx2_COM_b06FwText), +@@ -872,15 +874,15 @@ + .data_index = 0x0, + .data = bnx2_COM_b06FwData, + +- .sbss_addr = 0x08004ee0, ++ .sbss_addr = 0x08004d00, + .sbss_len = 0x38, + .sbss_index = 0x0, + +- .bss_addr = 0x08004f18, +- .bss_len = 0xbc, +- .bss_index = 0x0, +- +- .rodata_addr = 0x08004eac, ++ .bss_addr = 0x08004d38, ++ .bss_len = 0xc4, ++ .bss_index = 0x0, ++ ++ .rodata_addr = 0x08004cc8, + .rodata_len = 0x14, + .rodata_index = 0x0, + .rodata = bnx2_COM_b06FwRodata, +@@ -902,1232 +904,1245 @@ + .mips_view_base = 0x8000000, + }; + +- + static u8 bnx2_CP_b06FwText[] = { +- 0x9d, 0xbc, 0x0d, 0x78, 0x13, 0xe7, 0x99, 0x2e, 0x7c, 0xcf, 0x48, 0xb2, +- 0x65, 0x5b, 0xb6, 0xc7, 0xb6, 0x0c, 0x22, 0x65, 0x41, 0x83, 0x47, 0x20, +- 0x62, 0x27, 0x1d, 0x81, 0x49, 0x94, 0xac, 0x36, 0xa8, 0xc6, 0x01, 0x93, +- 0x90, 0xc6, 0x34, 0xb4, 0x75, 0x7a, 0xd2, 0x8d, 0x62, 0x0c, 0x21, 0x84, +- 0x10, 0x67, 0x9b, 0x9e, 0xe3, 0x7c, 0x5f, 0xce, 0x5a, 0x35, 0x06, 0x0c, +- 0xc8, 0x96, 0x31, 0x0e, 0x90, 0xfd, 0x7a, 0x9d, 0x18, 0x6c, 0x30, 0x49, +- 0x65, 0x8b, 0x34, 0x74, 0x97, 0xf4, 0xa3, 0x45, 0x07, 0xf2, 0xe3, 0xfc, +- 0x35, 0xa4, 0xed, 0x76, 0xdb, 0x3d, 0x39, 0x89, 0x0f, 0x25, 0x84, 0xb4, +- 0xdd, 0xfc, 0xb4, 0xdd, 0x2d, 0x69, 0x9b, 0xcc, 0x77, 0x3f, 0x23, 0x09, +- 0x0c, 0x4d, 0x7f, 0xf6, 0xf3, 0x75, 0xcd, 0x65, 0xcd, 0xcc, 0xfb, 0xf3, +- 0xbc, 0xcf, 0xfb, 0x3c, 0xf7, 0x73, 0x3f, 0xef, 0xbc, 0x33, 0xb3, 0x80, +- 0x62, 0xe4, 0xfe, 0x4a, 0x79, 0x5c, 0x5d, 0xdf, 0xbe, 0x1a, 0x8b, 0xae, +- 0x36, 0xe5, 0xdc, 0xe9, 0x82, 0x13, 0x7f, 0xe1, 0x9f, 0xff, 0x2f, 0x2d, +- 0x38, 0xe5, 0xcf, 0x01, 0x68, 0xf9, 0x7e, 0xe5, 0x80, 0x5b, 0x8d, 0x3c, +- 0xf3, 0x5f, 0x1a, 0x0c, 0xb8, 0x1d, 0x91, 0x9e, 0xd6, 0xd5, 0x06, 0x10, +- 0x4d, 0xd5, 0xfa, 0x97, 0xe0, 0x23, 0x2b, 0xee, 0x75, 0x42, 0xae, 0xff, +- 0x55, 0xe4, 0xf7, 0x9d, 0xdf, 0xb9, 0x56, 0x7f, 0x7f, 0xc8, 0x01, 0xb7, +- 0x16, 0xe9, 0x80, 0x36, 0x17, 0xee, 0x99, 0xac, 0xf3, 0xf5, 0x79, 0xdb, +- 0x15, 0x94, 0xe5, 0xdb, 0x3a, 0x67, 0x7d, 0x67, 0x9e, 0x2f, 0x56, 0x14, +- 0xd1, 0x70, 0x3c, 0x8d, 0xe6, 0xba, 0xde, 0x4e, 0xab, 0xd4, 0x08, 0xc1, +- 0x6d, 0x18, 0x2d, 0xbd, 0x8a, 0x27, 0xbc, 0x7e, 0x11, 0x3c, 0x85, 0x06, +- 0xe2, 0x57, 0x44, 0xd0, 0x7c, 0xe5, 0x58, 0x71, 0xdc, 0x19, 0x71, 0xa3, +- 0x29, 0xed, 0x8e, 0x7f, 0x2a, 0x62, 0x60, 0x59, 0xfa, 0xfa, 0x62, 0x94, +- 0xb9, 0xd1, 0x9d, 0xfe, 0xa8, 0x28, 0xdb, 0x5e, 0x73, 0xee, 0xff, 0xec, +- 0xaa, 0xec, 0xff, 0x69, 0x31, 0x67, 0x04, 0xd8, 0x9c, 0xb0, 0xac, 0x82, +- 0xc8, 0x6d, 0xb7, 0xa9, 0x11, 0xc3, 0x77, 0x10, 0x8b, 0xd1, 0xaa, 0xe1, +- 0xe1, 0x2d, 0xf5, 0xbf, 0x54, 0x4e, 0x0c, 0xb2, 0xe1, 0x51, 0x07, 0xa2, +- 0xda, 0x33, 0xfc, 0x3f, 0x6b, 0x56, 0x4b, 0xd8, 0xc0, 0xde, 0xd1, 0xf3, +- 0xbc, 0xee, 0xb4, 0xaf, 0x6d, 0xda, 0x33, 0x6b, 0xd6, 0xed, 0xe1, 0x67, +- 0xf0, 0xe8, 0xa8, 0xfc, 0xbe, 0x1b, 0x9d, 0x75, 0x0a, 0x26, 0x6f, 0x5b, +- 0x0b, 0x87, 0x61, 0xa0, 0x7b, 0x8f, 0xe2, 0xec, 0xaa, 0x53, 0x11, 0xf5, +- 0xea, 0xc1, 0x18, 0x95, 0xef, 0x34, 0x10, 0x2b, 0x8c, 0x84, 0x9d, 0xef, +- 0x24, 0x22, 0x9a, 0xc3, 0xb0, 0xac, 0x60, 0x68, 0x3a, 0x1c, 0x15, 0x96, +- 0xf5, 0xb4, 0xe9, 0x81, 0xff, 0x8b, 0xcf, 0x21, 0x3e, 0xdc, 0x0c, 0xd5, +- 0x78, 0x0e, 0x5d, 0xc3, 0xcf, 0xe1, 0xb1, 0x5d, 0xc5, 0x98, 0xac, 0xe2, +- 0x78, 0x93, 0x3e, 0x7c, 0x67, 0x9e, 0xf4, 0x2d, 0x72, 0xd4, 0xf1, 0x70, +- 0x63, 0xd2, 0xf1, 0x06, 0xff, 0x4b, 0x99, 0xf3, 0xd6, 0xe4, 0xf4, 0x8b, +- 0x65, 0x36, 0xb3, 0x4c, 0xf7, 0x65, 0x65, 0xe2, 0xc3, 0x11, 0xbc, 0x94, +- 0x50, 0xb0, 0x3e, 0x54, 0x86, 0x68, 0x85, 0x8c, 0xd7, 0xb2, 0x46, 0xcd, +- 0xb3, 0xd6, 0xa4, 0x26, 0x7d, 0x4d, 0xe0, 0x65, 0xde, 0xdb, 0x12, 0x3a, +- 0x63, 0x65, 0xbc, 0xd2, 0x5e, 0x3b, 0x6d, 0x67, 0x25, 0xaf, 0x3b, 0x91, +- 0x4c, 0x20, 0x56, 0x16, 0xb9, 0x8d, 0xe7, 0xba, 0xf9, 0xae, 0xe2, 0x76, +- 0xbf, 0x97, 0x70, 0x7f, 0xb1, 0xd4, 0x50, 0x1f, 0x2c, 0xa7, 0x01, 0xbd, +- 0x42, 0x99, 0x8f, 0x9a, 0x6b, 0xe1, 0x32, 0x1e, 0x10, 0x5b, 0xe3, 0xb8, +- 0x7e, 0x68, 0x61, 0x7a, 0xbe, 0xbe, 0xb4, 0xeb, 0xc6, 0x96, 0xa4, 0x65, +- 0x6d, 0x33, 0xa3, 0xd7, 0x15, 0xd1, 0x20, 0x4e, 0x26, 0x9a, 0xe1, 0x8e, +- 0x04, 0xfc, 0xe7, 0x10, 0xc6, 0x92, 0xb4, 0x17, 0xcf, 0x26, 0xe0, 0x6c, +- 0x98, 0xe7, 0x45, 0x57, 0x3a, 0x82, 0x1b, 0xd3, 0x26, 0x1a, 0xd3, 0x7f, +- 0xde, 0xb2, 0x6e, 0x4e, 0xfa, 0x39, 0x86, 0x8f, 0xac, 0xec, 0x18, 0x64, +- 0x7c, 0xd9, 0xff, 0xdd, 0xc9, 0x2b, 0xb0, 0x9d, 0x73, 0xb4, 0x95, 0xf3, +- 0xb7, 0x3c, 0x94, 0x89, 0x16, 0x41, 0x37, 0xcf, 0x21, 0x82, 0xa5, 0x69, +- 0x83, 0x73, 0x1a, 0xc1, 0x92, 0x64, 0x8d, 0x36, 0x8c, 0xf9, 0x88, 0xfa, +- 0xb2, 0x36, 0xbd, 0x83, 0xe3, 0x6d, 0x0d, 0x34, 0xa3, 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0xf6, 0xd5, 0x3f, 0x2a, 0xbe, 0xb2, 0xb4, 0x2a, 0xfb, +- 0xbe, 0xee, 0x54, 0xae, 0x93, 0xaf, 0xeb, 0x20, 0x36, 0xe6, 0xef, 0xff, +- 0x08, 0x77, 0x32, 0x7e, 0x9d, 0x59, 0x78, 0x2a, 0x67, 0xf3, 0xd3, 0xab, +- 0xb3, 0xf8, 0xf5, 0x49, 0xdf, 0x0b, 0xfa, 0x2b, 0xfb, 0xdb, 0x3b, 0xd9, +- 0x6f, 0x1f, 0x01, 0xcf, 0x26, 0x0a, 0xe4, 0x29, 0xc1, 0x62, 0x17, 0x54, +- 0xaf, 0x0b, 0x85, 0x8c, 0x01, 0xd5, 0xd8, 0xe4, 0xb5, 0x70, 0xa3, 0x59, +- 0x80, 0x43, 0x75, 0xb7, 0x00, 0x15, 0xf1, 0x16, 0x97, 0xfd, 0x4e, 0xde, +- 0xef, 0xbf, 0xf4, 0x87, 0xef, 0xe4, 0x9d, 0xb1, 0xf3, 0xe1, 0x52, 0xe3, +- 0x76, 0xbc, 0x62, 0xc7, 0x09, 0x05, 0x25, 0x73, 0x65, 0x5d, 0xd2, 0x8f, +- 0x17, 0x8d, 0x5a, 0x7f, 0x85, 0x3c, 0x6f, 0x52, 0xce, 0x5a, 0x71, 0xaf, +- 0xbc, 0x87, 0xf7, 0xc7, 0xf6, 0x8f, 0x3f, 0x87, 0xad, 0xbb, 0xc2, 0x90, +- 0xf7, 0x3b, 0x9c, 0x46, 0xa1, 0x37, 0x2b, 0xbf, 0xc8, 0x26, 0xeb, 0x44, +- 0xb7, 0x71, 0x1c, 0x67, 0xe8, 0x8b, 0x67, 0xec, 0x75, 0x2a, 0xb7, 0xf1, +- 0xd7, 0x08, 0x56, 0xe4, 0xc7, 0x2f, 0x39, 0x8d, 0x92, 0xd5, 0x41, 0xf6, +- 0xfd, 0xda, 0x6a, 0xc1, 0xfe, 0x2d, 0xc9, 0x33, 0xf6, 0x9a, 0xac, 0xcb, +- 0xf8, 0x0f, 0xeb, 0x2d, 0x6f, 0x25, 0xcb, 0x3e, 0x95, 0xbb, 0x3f, 0x29, +- 0xeb, 0x38, 0xa6, 0x7c, 0xbb, 0xca, 0x69, 0xd7, 0x11, 0xbd, 0x5f, 0xac, +- 0xb3, 0x89, 0xbc, 0x7a, 0xb6, 0x71, 0xca, 0xea, 0xf4, 0xca, 0x18, 0xd6, +- 0x5c, 0x56, 0x47, 0xd6, 0x08, 0x34, 0xe9, 0x37, 0x2c, 0x63, 0xee, 0x4a, +- 0xff, 0x61, 0x9f, 0xb2, 0x7e, 0x5b, 0x60, 0x94, 0xe0, 0x6c, 0x45, 0x76, +- 0x4d, 0xe5, 0xa2, 0x8c, 0xed, 0xd5, 0xb2, 0xef, 0xae, 0xd0, 0x3e, 0xb7, +- 0xfb, 0x35, 0x2f, 0xd6, 0x7b, 0x30, 0x37, 0xde, 0x4a, 0xfb, 0x9d, 0x9a, +- 0x47, 0x6d, 0xae, 0xe3, 0x98, 0x32, 0xee, 0xdf, 0x78, 0x2f, 0xed, 0xe7, +- 0xf3, 0xb9, 0x7e, 0x45, 0x1e, 0xef, 0x94, 0x3e, 0x44, 0xae, 0xde, 0x5c, +- 0x1d, 0x3d, 0x1c, 0xb5, 0xfb, 0x57, 0x11, 0xde, 0x93, 0xef, 0xd3, 0xb2, +- 0x0a, 0x16, 0xe6, 0xdb, 0xc8, 0xd0, 0x0f, 0xad, 0xce, 0x42, 0xc6, 0xab, +- 0xb3, 0xf5, 0x0f, 0x62, 0x73, 0x42, 0xf4, 0x2c, 0xdf, 0x70, 0x25, 0x2e, +- 0xdb, 0xfc, 0xcb, 0xc5, 0x5c, 0xf6, 0x1a, 0x0c, 0x69, 0x71, 0xec, 0xaf, +- 0x93, 0x77, 0xc8, 0x5c, 0xf4, 0x85, 0x38, 0x71, 0xb0, 0x90, 0x38, 0x1a, +- 0xb7, 0xf7, 0x94, 0x1c, 0x34, 0xf5, 0xe8, 0xb3, 0xf2, 0x8d, 0xb2, 0xab, +- 0xec, 0xb5, 0xa7, 0xa6, 0x21, 0xc8, 0xf5, 0xfc, 0x7a, 0x52, 0xfe, 0xaf, +- 0x88, 0xb6, 0x23, 0x72, 0x89, 0x0d, 0x50, 0xba, 0x84, 0xbc, 0xeb, 0x54, +- 0x1b, 0x23, 0x67, 0xc4, 0x2b, 0x29, 0xd9, 0x7f, 0xf0, 0x5b, 0x2b, 0x5e, +- 0x2d, 0xfb, 0x1c, 0xa7, 0xd6, 0x29, 0x20, 0x97, 0x0b, 0x84, 0xcb, 0x94, +- 0xfc, 0xfb, 0x4e, 0x17, 0xff, 0x6e, 0xa5, 0xcd, 0x9c, 0xb3, 0xdf, 0x51, +- 0x93, 0xb3, 0x08, 0x1a, 0x92, 0xf2, 0xad, 0x52, 0x7d, 0x62, 0x39, 0x6a, +- 0x33, 0x35, 0x0e, 0x67, 0x8e, 0x93, 0x84, 0xb1, 0x82, 0x76, 0xb3, 0x25, +- 0x10, 0xb6, 0xdf, 0xc5, 0x5a, 0x96, 0xac, 0x09, 0x3e, 0xce, 0x1c, 0xfa, +- 0x1d, 0x96, 0xbf, 0x25, 0xfd, 0x3d, 0x6b, 0xc8, 0x2b, 0x63, 0xca, 0x63, +- 0xc3, 0x29, 0xfa, 0x06, 0xf5, 0x18, 0x11, 0xff, 0xf0, 0xa0, 0x22, 0x12, +- 0xa6, 0xff, 0x4a, 0x4c, 0x97, 0xf7, 0xb8, 0xf4, 0xbd, 0x71, 0x98, 0xc4, +- 0xfc, 0x1e, 0xda, 0x91, 0xec, 0x5b, 0xd6, 0xfd, 0x2b, 0x19, 0x5b, 0x8e, +- 0x5f, 0x78, 0xc6, 0x2f, 0x1c, 0xe0, 0xd9, 0xea, 0xdc, 0xde, 0x66, 0xf7, +- 0x6c, 0xc6, 0x3c, 0xcb, 0x7e, 0x6e, 0xdf, 0x66, 0x63, 0x8a, 0x66, 0xe8, +- 0x87, 0x7e, 0xe5, 0xe8, 0xc4, 0xd3, 0x0b, 0x8c, 0x8e, 0xc3, 0x6a, 0x66, +- 0xc8, 0x47, 0x7c, 0xb9, 0xde, 0x11, 0xdd, 0xc9, 0xff, 0xfe, 0xd7, 0xec, +- 0x6f, 0xab, 0x48, 0x5d, 0x3d, 0xb8, 0x4a, 0x95, 0xfd, 0x40, 0xcd, 0x18, +- 0xeb, 0x95, 0x77, 0x06, 0xf4, 0x96, 0xa7, 0x94, 0x4e, 0x6c, 0x08, 0x19, +- 0xcd, 0xed, 0x8a, 0xde, 0xf4, 0x0f, 0x8a, 0xee, 0x0f, 0x29, 0x52, 0x2e, +- 0xc8, 0xbc, 0xeb, 0x62, 0x3c, 0x75, 0xb1, 0x8f, 0x03, 0x09, 0x3d, 0x5c, +- 0xc5, 0xb2, 0x67, 0x4d, 0xc3, 0xf7, 0x3e, 0xdb, 0xfc, 0x57, 0x1e, 0x3b, +- 0xed, 0xf7, 0xc4, 0xa5, 0x7c, 0x74, 0xbe, 0xcb, 0xfe, 0xbe, 0x69, 0x0b, +- 0xe3, 0xae, 0x7c, 0x23, 0x38, 0x06, 0xad, 0x6f, 0x26, 0x4d, 0x4c, 0xef, +- 0xb9, 0x0d, 0xb2, 0xe7, 0xa0, 0x89, 0x09, 0xba, 0x07, 0xde, 0x48, 0x27, +- 0xe6, 0x2e, 0x30, 0x7c, 0x8b, 0x54, 0xbb, 0x7e, 0x30, 0xaa, 0x4a, 0x7d, +- 0xdd, 0x3f, 0x08, 0x69, 0x23, 0x63, 0x69, 0x73, 0xcb, 0xed, 0x3a, 0x0b, +- 0xd4, 0xcf, 0xc0, 0x75, 0xf5, 0xaf, 0xe5, 0x5b, 0x46, 0x5a, 0xa5, 0x21, +- 0x75, 0xe2, 0x3b, 0x35, 0xfc, 0xb1, 0x7a, 0x82, 0x2b, 0xbf, 0xb2, 0x30, +- 0x4d, 0xea, 0xc9, 0x9e, 0xb1, 0x3b, 0x70, 0xaf, 0xfd, 0x3d, 0x16, 0xf1, +- 0x47, 0x3d, 0xfa, 0x15, 0xf2, 0xcf, 0x62, 0x45, 0xb8, 0xa7, 0xf0, 0x84, +- 0x56, 0x74, 0x33, 0x8e, 0x69, 0x21, 0xbd, 0xe7, 0x0a, 0xd5, 0x83, 0xc2, +- 0xc8, 0x63, 0xb2, 0x6f, 0x66, 0xef, 0x3c, 0x35, 0xbb, 0xbf, 0x26, 0xc6, +- 0x76, 0x8f, 0xff, 0xd1, 0xe7, 0xb8, 0xec, 0xab, 0xd8, 0x94, 0xf7, 0x5b, +- 0xec, 0x35, 0xc5, 0xd6, 0x84, 0x23, 0xb7, 0x5f, 0x30, 0x3f, 0xb7, 0x1a, +- 0xda, 0xc8, 0xf5, 0xd7, 0xc8, 0x37, 0x31, 0x39, 0xd6, 0xb5, 0x09, 0x59, +- 0x4d, 0xfa, 0xff, 0x00, 0x85, 0x57, 0x0f, 0xe7, 0xe8, 0x59, 0x00, 0x00, +- 0x00 }; ++ 0xbd, 0xbc, 0x7d, 0x74, 0x14, 0xe7, 0x95, 0x26, 0xfe, 0x54, 0x75, 0xb7, ++ 0xd4, 0xfa, 0x2e, 0x89, 0x06, 0x37, 0x8e, 0x02, 0x5d, 0xa8, 0x5a, 0x6a, ++ 0x2c, 0x39, 0xae, 0x06, 0x61, 0xb7, 0x3d, 0x1d, 0xab, 0x23, 0x64, 0x10, ++ 0x36, 0xb1, 0xc5, 0x84, 0x49, 0xe4, 0x2c, 0x1b, 0xda, 0x20, 0x40, 0xc6, ++ 0xc4, 0xc1, 0x13, 0x66, 0x57, 0x9e, 0xf5, 0x8e, 0x3a, 0x42, 0x80, 0x80, ++ 0x56, 0xb7, 0x24, 0x64, 0x81, 0x67, 0x72, 0xd6, 0x02, 0x01, 0xc2, 0x49, ++ 0x4b, 0xcd, 0x38, 0xce, 0x84, 0xe4, 0x90, 0x75, 0x0f, 0xf8, 0x43, 0xfe, ++ 0xc0, 0x26, 0x89, 0xd7, 0xe3, 0xcd, 0xe6, 0x4c, 0xb4, 0x18, 0x63, 0x92, ++ 0x38, 0x36, 0x93, 0x0f, 0x0f, 0xce, 0x87, 0x6b, 0x9f, 0x5b, 0xdd, 0x0d, ++ 0xb2, 0xe3, 0xc9, 0x64, 0x7e, 0x7f, 0xfc, 0x74, 0x4e, 0x1d, 0x75, 0x55, ++ 0xbd, 0x1f, 0xf7, 0xbd, 0xef, 0xbd, 0xcf, 0x7d, 0xee, 0x5b, 0x6f, 0xd5, ++ 0x02, 0xa0, 0x18, 0xb9, 0xbf, 0x32, 0x1e, 0x9f, 0x58, 0xb2, 0x75, 0xfd, ++ 0x66, 0xf3, 0x13, 0xa6, 0x9c, 0x3b, 0x01, 0x17, 0xfe, 0xc4, 0x3f, 0xdf, ++ 0x9f, 0x5a, 0x30, 0xf7, 0xa7, 0xf0, 0xa8, 0xff, 0xd0, 0x35, 0x07, 0xa0, ++ 0xe5, 0xe5, 0x90, 0x03, 0x6e, 0x35, 0x7c, 0xfe, 0xf3, 0xcd, 0x06, 0xdc, ++ 0x8e, 0xf0, 0xf1, 0x7b, 0xd6, 0x1b, 0x40, 0x24, 0x55, 0xef, 0x5b, 0x8a, ++ 0xdf, 0x5b, 0x31, 0x8f, 0x13, 0x72, 0xfd, 0xe3, 0xe1, 0xdf, 0x75, 0x7f, ++ 0xf7, 0x26, 0xfd, 0xd2, 0xa8, 0x03, 0x6e, 0x2d, 0xdc, 0x07, 0xad, 0x16, ++ 0xee, 0x6a, 0xd6, 0xf9, 0x6a, 0xdd, 0x51, 0x05, 0xe5, 0xf9, 0xb6, 0x2e, ++ 0x5a, 0xdf, 0xad, 0xf3, 0x46, 0x8b, 0xc2, 0x1a, 0x9e, 0x4c, 0xa3, 0xad, ++ 0xa1, 0xbf, 0xdb, 0x2a, 0x33, 0x82, 0x70, 0x1b, 0x46, 0x7b, 0xbf, 0x52, ++ 0x1a, 0xda, 0xbc, 0x04, 0xa5, 0x85, 0x06, 0x62, 0xd7, 0x86, 0xd1, 0x76, ++ 0xdd, 0x44, 0x71, 0xcc, 0x19, 0x76, 0xa3, 0x35, 0xed, 0x8e, 0x7d, 0x2c, ++ 0x6c, 0x60, 0x79, 0x3a, 0x5c, 0x84, 0x72, 0x0d, 0xbd, 0x69, 0xcb, 0x9d, ++ 0x6d, 0x6f, 0x65, 0xee, 0xff, 0xeb, 0x55, 0xd9, 0xff, 0x73, 0xa2, 0xce, ++ 0x30, 0xb0, 0x23, 0x6e, 0x59, 0x05, 0xe1, 0xcf, 0x7c, 0x46, 0x0d, 0x1b, ++ 0xde, 0xa3, 0x58, 0x8e, 0x75, 0x1a, 0x1e, 0xda, 0xd9, 0xf8, 0x0b, 0xe5, ++ 0xd4, 0x70, 0x03, 0x62, 0xe3, 0x0e, 0x44, 0xb4, 0x17, 0xf9, 0x7f, 0xde, ++ 0xbc, 0xf6, 0x50, 0x03, 0x0e, 0x8c, 0x5f, 0xe6, 0x75, 0xa7, 0x7d, 0x6d, ++ 0xfb, 0xfe, 0x79, 0xf3, 0xee, 0x0e, 0xbd, 0x88, 0x47, 0xc6, 0xe5, 0xf7, ++ 0x26, 0x74, 0x37, 0x28, 0x98, 0xfe, 0xcc, 0x46, 0x38, 0x8c, 0x06, 0xf4, ++ 0xee, 0x57, 0x9c, 0x3d, 0x0d, 0x2a, 0x22, 0x1e, 0x3d, 0x10, 0xe5, 0x64, ++ 0x38, 0x0d, 0x44, 0x0b, 0xc3, 0x21, 0xe7, 0x4f, 0xe2, 0x61, 0xcd, 0x61, ++ 0x58, 0x56, 0x20, 0x38, 0x1f, 0x8e, 0x4a, 0xcb, 0xfa, 0xb6, 0xa9, 0xc1, ++ 0xf7, 0xb9, 0x97, 0x10, 0x1b, 0x6b, 0x83, 0x6a, 0xbc, 0x84, 0x9e, 0xb1, ++ 0x97, 0xf0, 0xe8, 0xbe, 0x0a, 0xb6, 0xf3, 0x22, 0x76, 0x8c, 0x4b, 0xbf, ++ 0xfc, 0xbf, 0x9f, 0x63, 0x4f, 0x8a, 0x2c, 0x8d, 0x3c, 0x2e, 0xf0, 0x80, ++ 0x5b, 0x09, 0xc7, 0xe0, 0x4f, 0xb9, 0x31, 0xed, 0xf0, 0xe2, 0xbb, 0x75, ++ 0x52, 0xe7, 0xd7, 0xd6, 0xf4, 0xe7, 0x72, 0xe5, 0x67, 0xd4, 0xe9, 0xfd, ++ 0x23, 0x75, 0x62, 0x63, 0x61, 0xbc, 0x10, 0x57, 0xb0, 0x39, 0x58, 0x8e, ++ 0x48, 0xa5, 0xe8, 0xc3, 0xb2, 0xc6, 0xcd, 0x7f, 0xb6, 0xa6, 0x35, 0x91, ++ 0x65, 0x0a, 0x2f, 0xf2, 0xde, 0xce, 0xe0, 0x8f, 0xac, 0x8c, 0x47, 0xda, ++ 0xdf, 0x46, 0x5b, 0x5b, 0xc5, 0xeb, 0x4e, 0x24, 0xe3, 0x88, 0x96, 0x87, ++ 0x3f, 0xc7, 0x73, 0xdd, 0x7c, 0x5b, 0x71, 0xbb, 0xdf, 0x89, 0xbb, 0x3f, ++ 0x57, 0x66, 0xa8, 0xdb, 0x2a, 0x68, 0x73, 0x67, 0x38, 0xa6, 0x13, 0xe6, ++ 0x46, 0xb8, 0x8c, 0xbf, 0x12, 0xdb, 0xe4, 0xb8, 0x5f, 0xb4, 0x70, 0x4d, ++ 0xbe, 0xbe, 0xb4, 0xab, 0x61, 0x67, 0xd2, 0xb2, 0x76, 0x9b, 0x91, 0x9b, ++ 0x8b, 0x68, 0x30, 0xa7, 0xe3, 0x6d, 0x70, 0x87, 0xfd, 0xbe, 0x8b, 0x08, ++ 0x61, 0x69, 0xda, 0x83, 0xa7, 0xe3, 0x70, 0x36, 0xd7, 0x55, 0xa3, 0x27, ++ 0x1d, 0xc6, 0x6d, 0x69, 0x13, 0x2d, 0xe9, 0x7f, 0xdf, 0x1a, 0xef, 0x48, ++ 0xfa, 0x38, 0x86, 0xdf, 0x5b, 0xd9, 0x31, 0xc8, 0xf8, 0xe4, 0x3f, 0xe7, ++ 0x3d, 0x79, 0x2d, 0xf6, 0x0c, 0x1b, 0xd8, 0xc5, 0xf9, 0x5d, 0x11, 0xcc, ++ 0x44, 0x8a, 0xa0, 0x9b, 0x17, 0x11, 0xc6, 0xb2, 0xb4, 0xc1, 0x39, 0x0f, ++ 0x63, 0x69, 0xb2, 0x46, 0x1b, 0xc3, 0x42, 0x44, 0xbc, 0x59, 0x1f, 0xd8, ++ 0xcb, 0xf1, 0xae, 0xf3, 0xb7, 0xa1, 0x8c, 0x36, 0x94, 0x5a, 0x12, 0x42, ++ 0x33, 0xfb, 0x5f, 0xf9, 0x27, 0xf4, 0x7f, 0x17, 0xfb, 0x7f, 0x9b, 0xfd, ++ 0x67, 0xec, 0xfe, 0xe1, 0xbc, 0x9d, 0xe7, 0x6e, 0xda, 0xeb, 0x9e, 0x94, ++ 0xd3, 0xb9, 0x22, 0xe9, 0xc1, 0xee, 0x94, 0x49, 0x9b, 0x94, 0x5b, 0x5e, ++ 0xec, 0x1c, 0xae, 0xc6, 0xae, 0x61, 0xdd, 0xfb, 0x2c, 0x7f, 0x6f, 0x3f, ++ 0x7c, 0x2d, 0x76, 0x0c, 0x2b, 0x38, 0x64, 0x5c, 0x8b, 0x1e, 0xfe, 0x3e, ++ 0x30, 0x3c, 0x0f, 0x8f, 0x0c, 0x3b, 0x10, 0x9a, 0x35, 0x73, 0x1c, 0xf2, ++ 0xff, 0x5a, 0xc4, 0x0e, 0xfb, 0xd0, 0x13, 0x7f, 0xd5, 0xd6, 0x61, 0x59, ++ 0xf8, 0xd9, 0xbc, 0xdf, 0xd3, 0xb7, 0x7c, 0x58, 0x1f, 0xf7, 0xa2, 0x27, ++ 0x29, 0x7e, 0xe2, 0xa6, 0xed, 0x8a, 0x9f, 0xbc, 0x0f, 0x94, 0xb3, 0xfd, ++ 0x74, 0xfe, 0xbe, 0x02, 0x27, 0xe7, 0xad, 0x83, 0xf7, 0x76, 0x27, 0xc5, ++ 0x2e, 0xf2, 0x36, 0x20, 0xbf, 0xab, 0x68, 0x97, 0xc5, 0xf0, 0x1d, 0x29, ++ 0x46, 0xe0, 0x61, 0x0d, 0x6f, 0x34, 0xca, 0x75, 0xfa, 0x43, 0x50, 0xca, ++ 0x0c, 0xe0, 0x68, 0x4a, 0xfc, 0xd8, 0x87, 0xe6, 0xf8, 0x14, 0xdb, 0x6f, ++ 0x64, 0xdb, 0x26, 0xfe, 0x67, 0xba, 0x01, 0xdf, 0x4a, 0x07, 0xf0, 0x0f, ++ 0xd4, 0xe3, 0x37, 0xd3, 0x3e, 0x3c, 0x91, 0xae, 0xc6, 0x37, 0xd2, 0x5e, ++ 0x3c, 0xce, 0xf9, 0xfb, 0xfb, 0x74, 0x1b, 0x7d, 0x43, 0xc3, 0xf1, 0xb4, ++ 0xe8, 0xbf, 0x80, 0xe3, 0x2d, 0xc6, 0xf6, 0xe1, 0x9a, 0xc0, 0x69, 0xda, ++ 0xd6, 0x3f, 0x98, 0xb7, 0x23, 0x53, 0xc5, 0x36, 0x92, 0x5e, 0xec, 0xe6, ++ 0xf5, 0x3d, 0xc3, 0x35, 0x91, 0xeb, 0x14, 0xcb, 0x52, 0x83, 0xf5, 0xa1, ++ 0x53, 0xaa, 0x8a, 0x69, 0x8f, 0xee, 0xcb, 0xa8, 0xba, 0x2f, 0x42, 0xe0, ++ 0x8a, 0xd3, 0x77, 0x62, 0xb3, 0xf5, 0xd1, 0x18, 0x6d, 0xca, 0x63, 0x4c, ++ 0x70, 0x3c, 0xba, 0x2f, 0xa6, 0x6a, 0xd8, 0x95, 0xd4, 0x0f, 0xc4, 0x54, ++ 0x0f, 0x62, 0xe9, 0x62, 0xfc, 0x7c, 0x58, 0xef, 0x8b, 0xa9, 0x77, 0x22, ++ 0x56, 0x65, 0x59, 0x8f, 0x07, 0xb1, 0xf5, 0x9a, 0x30, 0x22, 0xb3, 0xc3, ++ 0x88, 0xce, 0x0b, 0x57, 0x23, 0x99, 0x04, 0xde, 0xee, 0x37, 0xbc, 0xff, ++ 0xa4, 0xb4, 0xe1, 0xaf, 0xda, 0x74, 0x9f, 0x4f, 0xad, 0x8f, 0x8d, 0xa9, ++ 0x4b, 0xe8, 0xf2, 0xf0, 0x79, 0xc3, 0xcb, 0xd1, 0x65, 0x5f, 0x53, 0xa0, ++ 0x19, 0x1e, 0x6c, 0x4f, 0xde, 0x8c, 0xa8, 0xa7, 0xa6, 0x7d, 0x50, 0xad, ++ 0xb9, 0x6c, 0xaa, 0xfa, 0x54, 0x9b, 0x6a, 0x59, 0xff, 0xb2, 0xf8, 0x6d, ++ 0xcb, 0x37, 0xc7, 0xb2, 0x16, 0x2d, 0x96, 0x3e, 0x7d, 0xa8, 0x0c, 0x9b, ++ 0x58, 0x65, 0xcf, 0x61, 0x31, 0x2e, 0x0c, 0x57, 0xb1, 0x0f, 0x0d, 0xff, ++ 0xeb, 0x26, 0x3d, 0xb0, 0x51, 0x2d, 0xc6, 0x1b, 0x87, 0x8b, 0x71, 0x8e, ++ 0xe3, 0xf9, 0xc5, 0xb0, 0x17, 0xbf, 0x1a, 0xb6, 0xac, 0xcf, 0x99, 0x7f, ++ 0x86, 0xa1, 0xaa, 0x01, 0x7c, 0x6b, 0xd2, 0x83, 0x9f, 0xc7, 0x35, 0x9c, ++ 0x8f, 0x47, 0x1e, 0x98, 0x05, 0x3d, 0x32, 0xa9, 0x9c, 0x5e, 0x5b, 0x8e, ++ 0xfa, 0xb6, 0x72, 0x45, 0x6f, 0xdd, 0x0b, 0xdd, 0x7b, 0x9d, 0xe2, 0xc1, ++ 0xc5, 0x94, 0x86, 0xd7, 0x53, 0x35, 0xa1, 0x1f, 0xb0, 0xcf, 0x77, 0xcd, ++ 0x6f, 0x5b, 0x99, 0x39, 0xa2, 0x37, 0xd1, 0x11, 0xf5, 0x4c, 0xff, 0xfd, ++ 0x56, 0x92, 0x7a, 0x4e, 0x52, 0xcf, 0x94, 0xe1, 0x89, 0x24, 0xf5, 0x4c, ++ 0xdd, 0x3d, 0x4e, 0x9b, 0xfa, 0x7b, 0xce, 0xe3, 0x71, 0x7b, 0x1e, 0x43, ++ 0x9c, 0xaf, 0x8f, 0xe1, 0x6f, 0x6c, 0xec, 0x7d, 0xd1, 0xfa, 0xaf, 0x1e, ++ 0x19, 0xd3, 0x27, 0xe6, 0x64, 0xf1, 0x4d, 0xc6, 0xf6, 0x82, 0x15, 0xd5, ++ 0x64, 0x5c, 0x32, 0x3e, 0x5b, 0x7f, 0xbe, 0xad, 0xca, 0xa0, 0x82, 0x62, ++ 0xcb, 0xda, 0x67, 0xe6, 0xee, 0x7b, 0xf2, 0xe3, 0xfb, 0xcf, 0x4a, 0xd6, ++ 0xae, 0x8e, 0x14, 0x52, 0xdf, 0x81, 0x88, 0xba, 0x8a, 0xe7, 0x7a, 0x2c, ++ 0x82, 0x3b, 0x1c, 0x1f, 0x3c, 0x7f, 0xd7, 0x23, 0xf3, 0xe1, 0xbb, 0x72, ++ 0x4e, 0x7b, 0xb4, 0xfb, 0xfb, 0x32, 0xcf, 0x65, 0x2c, 0x62, 0x8b, 0x62, ++ 0x03, 0x1e, 0xda, 0xcb, 0xcd, 0xb9, 0x7b, 0x88, 0xa9, 0xe1, 0xad, 0x68, ++ 0x6b, 0x7c, 0xc2, 0xee, 0xa3, 0x20, 0x21, 0x7e, 0xa3, 0xe0, 0xed, 0x9b, ++ 0x15, 0x9c, 0x0a, 0x1a, 0xb4, 0x99, 0x63, 0xc4, 0x05, 0xa0, 0x30, 0x01, ++ 0x77, 0x69, 0x38, 0x8c, 0x78, 0x3f, 0xdc, 0x45, 0xe1, 0x10, 0x16, 0xf6, ++ 0xd7, 0x74, 0x5e, 0x80, 0x1e, 0xe8, 0x57, 0xf4, 0x36, 0xc6, 0x1c, 0x73, ++ 0x82, 0x7a, 0xbc, 0x4e, 0xd1, 0x7d, 0x05, 0x8a, 0xe0, 0x59, 0x98, 0x78, ++ 0x76, 0x0c, 0xbb, 0xd2, 0xf2, 0x3b, 0x04, 0x23, 0x85, 0x5c, 0xdc, 0x10, ++ 0xbb, 0xdf, 0x4a, 0xbb, 0xbf, 0xc0, 0xb1, 0xeb, 0x3e, 0xe2, 0xaf, 0xdb, ++ 0x15, 0xee, 0xc4, 0x91, 0x38, 0xdc, 0x05, 0xe1, 0x2d, 0x78, 0x26, 0xfe, ++ 0xdd, 0xd9, 0xf9, 0x72, 0x0a, 0xcb, 0xf9, 0x52, 0x33, 0x65, 0xf9, 0x67, ++ 0x2b, 0xe2, 0xc9, 0xca, 0x52, 0x9c, 0x38, 0x86, 0xbd, 0x49, 0xa9, 0x1b, ++ 0xb6, 0xeb, 0x3a, 0xd9, 0x47, 0x6f, 0xbc, 0xa6, 0xf5, 0x0e, 0x45, 0x0f, ++ 0x3d, 0xc6, 0xf9, 0xeb, 0x41, 0x7d, 0xe4, 0x27, 0xd0, 0xb5, 0x4e, 0x64, ++ 0x65, 0xa9, 0x4b, 0x65, 0xe5, 0x58, 0x40, 0x39, 0xd6, 0x26, 0x61, 0xcd, ++ 0x35, 0x50, 0xea, 0x35, 0x0c, 0xdf, 0x7b, 0x8e, 0x2a, 0x1c, 0xe0, 0xfc, ++ 0xf4, 0xd2, 0x57, 0x04, 0xcf, 0xbe, 0xb8, 0xcf, 0x87, 0x52, 0xc3, 0xc2, ++ 0xd1, 0x60, 0x15, 0x5e, 0x24, 0xd6, 0x96, 0xd3, 0x37, 0x5f, 0xd2, 0x10, ++ 0x99, 0x1b, 0x0e, 0x29, 0x77, 0xa7, 0x27, 0x72, 0x73, 0x70, 0x77, 0x2e, ++ 0x46, 0x7d, 0xf8, 0xfa, 0x5c, 0xe5, 0xa3, 0xaf, 0x43, 0x69, 0x4f, 0xea, ++ 0x81, 0x18, 0x2c, 0x54, 0x2c, 0xd6, 0x7d, 0xd3, 0xca, 0x65, 0x15, 0xe5, ++ 0xc4, 0xea, 0xf4, 0x87, 0xcb, 0xd5, 0x6b, 0x87, 0xa9, 0x26, 0x87, 0x51, ++ 0x44, 0x9d, 0xeb, 0x64, 0x0a, 0x91, 0x80, 0xcb, 0xbe, 0xe6, 0xc0, 0xa8, ++ 0x33, 0xe2, 0x75, 0xe0, 0x77, 0x56, 0x64, 0xb5, 0x5c, 0x2b, 0x46, 0xb4, ++ 0xad, 0xde, 0xeb, 0x44, 0x7d, 0x68, 0x07, 0x7d, 0x70, 0x7a, 0x75, 0x33, ++ 0xef, 0xf9, 0xcd, 0xd3, 0xa8, 0xf1, 0xed, 0x80, 0xfc, 0x7e, 0x8f, 0x76, ++ 0xd3, 0x2c, 0x75, 0x59, 0x46, 0xec, 0x50, 0xd7, 0xc4, 0xc7, 0x7b, 0x4d, ++ 0xcb, 0x3a, 0x62, 0x9e, 0x50, 0x9a, 0x93, 0xef, 0x5b, 0x11, 0x67, 0x2c, ++ 0x52, 0x18, 0xf6, 0x9b, 0xbb, 0x08, 0xc6, 0x8e, 0x70, 0x4c, 0x89, 0xa4, ++ 0x7b, 0x95, 0xdb, 0xd2, 0x7d, 0xca, 0xb2, 0xb4, 0x94, 0x3f, 0xa1, 0x2c, ++ 0x4d, 0x4b, 0xf9, 0x7c, 0xd9, 0x10, 0xcb, 0x02, 0x47, 0xe3, 0xfe, 0x40, ++ 0xbe, 0xfc, 0x32, 0x96, 0xbd, 0xed, 0x4a, 0xd9, 0x10, 0x6d, 0xd5, 0xe4, ++ 0xbc, 0x94, 0x60, 0xa3, 0xa6, 0x47, 0x62, 0xd4, 0x79, 0x61, 0xb8, 0x7d, ++ 0xcd, 0x9b, 0x46, 0x26, 0xe0, 0xe0, 0x1c, 0x8c, 0x73, 0x64, 0x2d, 0xc4, ++ 0xb9, 0xf5, 0x86, 0x0b, 0x7d, 0x5a, 0x05, 0xd6, 0x9b, 0xbf, 0xb1, 0x36, ++ 0xae, 0x96, 0x7b, 0x59, 0xd9, 0x60, 0x97, 0x5f, 0xc3, 0xf2, 0xba, 0x39, ++ 0x9e, 0xc3, 0xd6, 0x53, 0x71, 0x0c, 0x38, 0xc2, 0xc4, 0xfc, 0x46, 0xbf, ++ 0xaf, 0x07, 0x32, 0x37, 0x3e, 0xdc, 0x46, 0x59, 0x46, 0x9d, 0x33, 0xf1, ++ 0x17, 0xb1, 0xab, 0x65, 0xe4, 0x9a, 0x94, 0x9b, 0xa6, 0x7d, 0x0b, 0xd6, ++ 0x59, 0xd6, 0xa0, 0x29, 0x76, 0xee, 0xa5, 0x9d, 0xcf, 0x86, 0xaf, 0x4a, ++ 0x8f, 0x8d, 0x8a, 0xf7, 0xc4, 0x67, 0x61, 0x54, 0x53, 0x89, 0xb9, 0xdb, ++ 0x4b, 0x51, 0x1e, 0x51, 0x0a, 0xc8, 0x7d, 0x30, 0x29, 0xe3, 0x2c, 0x43, ++ 0xc4, 0xa9, 0x07, 0x64, 0xee, 0x0a, 0x18, 0xf3, 0x6a, 0x55, 0xd6, 0xbb, ++ 0xe2, 0xcb, 0x32, 0x66, 0x1f, 0x7d, 0x39, 0x66, 0xeb, 0xa8, 0xe5, 0xca, ++ 0xb8, 0xa5, 0xbd, 0xbc, 0x8e, 0xfe, 0x23, 0xf5, 0x2c, 0x6b, 0xe7, 0x15, ++ 0xdd, 0x16, 0x44, 0x8a, 0xa8, 0xdb, 0x63, 0x71, 0x7f, 0xe8, 0x39, 0xc4, ++ 0x94, 0xd6, 0xb4, 0x13, 0x87, 0xe3, 0x52, 0xaf, 0x97, 0xe5, 0xfb, 0x94, ++ 0xe5, 0x57, 0xea, 0x4c, 0xe7, 0xfc, 0x56, 0xc6, 0x23, 0xe3, 0xbb, 0x15, ++ 0xeb, 0xf7, 0xe9, 0xb1, 0x18, 0xc4, 0xae, 0x22, 0x58, 0x67, 0xea, 0x3e, ++ 0xa0, 0x82, 0x76, 0x03, 0x54, 0x26, 0xba, 0xdc, 0x59, 0x0c, 0x00, 0x36, ++ 0xed, 0x6b, 0xe3, 0x58, 0x2d, 0xbc, 0x61, 0x56, 0xe1, 0x30, 0xbd, 0xb4, ++ 0x22, 0x21, 0xd7, 0x67, 0xca, 0x18, 0x56, 0xd6, 0x8d, 0x87, 0x8a, 0x50, ++ 0x2c, 0x72, 0xee, 0x52, 0xb3, 0xf6, 0xfb, 0x51, 0xf5, 0x7f, 0x61, 0x1d, ++ 0xf6, 0x64, 0xaf, 0x55, 0x24, 0x84, 0x13, 0xb6, 0x41, 0x4b, 0x94, 0x32, ++ 0xde, 0xc5, 0xac, 0x12, 0x43, 0x6f, 0xbb, 0xa4, 0x74, 0xe3, 0xce, 0xa0, ++ 0x1e, 0xfd, 0xa1, 0xa2, 0x47, 0xfa, 0x15, 0x83, 0x7e, 0x18, 0xc0, 0x8a, ++ 0xf4, 0x87, 0xfb, 0x7a, 0x15, 0xea, 0x11, 0xe9, 0x47, 0xfa, 0x3b, 0x8b, ++ 0x3e, 0x7b, 0x4c, 0xf9, 0xf1, 0xc8, 0xd8, 0x14, 0x6c, 0xb4, 0xc7, 0xd4, ++ 0x66, 0xfb, 0xc7, 0xf7, 0x4c, 0x17, 0x3a, 0xf6, 0x9d, 0x5a, 0x28, 0x06, ++ 0xb2, 0x61, 0x3c, 0x82, 0xed, 0x8d, 0x2e, 0xac, 0x1f, 0xbb, 0x5b, 0x15, ++ 0xd9, 0xa0, 0xde, 0x52, 0x94, 0xfd, 0xaf, 0x90, 0xb7, 0x94, 0x62, 0x5d, ++ 0x9a, 0x73, 0x47, 0x0c, 0x5d, 0x37, 0x2e, 0x73, 0x5b, 0xc5, 0xff, 0x32, ++ 0xb7, 0x1e, 0xfe, 0x97, 0x79, 0x9e, 0xc3, 0xff, 0x15, 0xf0, 0xcd, 0x11, ++ 0x59, 0x1a, 0x11, 0xdf, 0x0f, 0x77, 0x49, 0xb8, 0x0b, 0xf7, 0xf5, 0x5b, ++ 0x56, 0x9f, 0xdf, 0xb2, 0x8a, 0x82, 0xe4, 0x59, 0xfe, 0xfa, 0xd0, 0x75, ++ 0x4a, 0x01, 0xa6, 0xb5, 0x46, 0xf4, 0x8d, 0x17, 0x44, 0x2b, 0xc2, 0x84, ++ 0x69, 0xf2, 0xa1, 0x9f, 0x2f, 0x69, 0xc3, 0xe4, 0xc4, 0xcc, 0x31, 0x64, ++ 0xed, 0xec, 0xbb, 0x75, 0x79, 0x3b, 0x13, 0xf9, 0x45, 0x76, 0xbd, 0x6f, ++ 0x94, 0x7e, 0x19, 0xd3, 0x10, 0xa5, 0x7f, 0x50, 0xa6, 0x2a, 0xf4, 0x5c, ++ 0xe1, 0xdc, 0x1f, 0x55, 0xff, 0x72, 0x7d, 0x67, 0xfc, 0x7d, 0x2b, 0x9b, ++ 0x07, 0x64, 0xea, 0x1f, 0x48, 0x7d, 0xd0, 0x6e, 0x8a, 0x6c, 0xbb, 0x91, ++ 0xb2, 0x97, 0xeb, 0xef, 0x4d, 0xb5, 0xd9, 0x63, 0x1e, 0x65, 0xe1, 0x0d, ++ 0xfb, 0x44, 0xa7, 0xa2, 0x03, 0x0b, 0xc7, 0xcd, 0x5b, 0x89, 0x15, 0x6f, ++ 0x5a, 0x8e, 0x39, 0xf6, 0x9c, 0x29, 0x2d, 0xb4, 0xa7, 0x98, 0xb3, 0x10, ++ 0xe4, 0xdc, 0x5a, 0x41, 0x38, 0xa2, 0xac, 0xb2, 0xf5, 0xdf, 0xa2, 0x2c, ++ 0x1f, 0x9b, 0xd9, 0x76, 0x17, 0x7d, 0xf7, 0x39, 0x35, 0x3b, 0xdf, 0x17, ++ 0xed, 0x31, 0x64, 0xe5, 0xf7, 0xa1, 0x2d, 0x29, 0xed, 0x88, 0x5e, 0xb3, ++ 0xfe, 0xd6, 0x26, 0x31, 0xe2, 0x8a, 0xcc, 0x59, 0xee, 0x71, 0x15, 0x13, ++ 0x96, 0x7c, 0x00, 0x3f, 0x6e, 0x23, 0x7e, 0x44, 0xfe, 0x4d, 0xfc, 0xb8, ++ 0xf1, 0xdf, 0x29, 0x7b, 0x96, 0x72, 0x08, 0x4f, 0x91, 0xb8, 0x27, 0xbc, ++ 0x45, 0xf8, 0x4a, 0x80, 0x72, 0x09, 0x7f, 0xc9, 0xdb, 0x86, 0x65, 0x7d, ++ 0xd3, 0xac, 0x43, 0xb4, 0x4a, 0x1f, 0x00, 0xaa, 0x31, 0x40, 0x59, 0x1d, ++ 0x09, 0xc4, 0x38, 0x4e, 0xea, 0x5a, 0xbd, 0xd5, 0x01, 0xb5, 0xc1, 0x81, ++ 0x6e, 0x9c, 0x37, 0x8d, 0xbe, 0x8d, 0xf8, 0x38, 0x7a, 0x3c, 0x16, 0x8e, ++ 0x98, 0x01, 0xe2, 0x52, 0x31, 0x3a, 0x1b, 0x38, 0x11, 0xab, 0x3c, 0x18, ++ 0x4c, 0xc6, 0xda, 0x09, 0x1b, 0x8c, 0x61, 0xd3, 0xed, 0x71, 0xbf, 0xde, ++ 0xb6, 0x85, 0xa9, 0xd2, 0x8a, 0x7e, 0x37, 0x7c, 0x92, 0x32, 0x31, 0x66, ++ 0x3c, 0xce, 0x38, 0xbf, 0xc1, 0x34, 0xa8, 0xdb, 0x5e, 0xda, 0x90, 0x4a, ++ 0x7b, 0x91, 0x7e, 0x02, 0xe4, 0x33, 0x52, 0x97, 0x71, 0xa1, 0x56, 0xc1, ++ 0x1d, 0xb5, 0xb4, 0x4f, 0xf2, 0xa2, 0xbf, 0x0c, 0x3a, 0xed, 0xfb, 0xf1, ++ 0x74, 0x7d, 0xe4, 0x33, 0xea, 0x8f, 0x2c, 0xcc, 0xb6, 0xdb, 0xd0, 0x22, ++ 0x2a, 0xe5, 0xfe, 0xa3, 0x9c, 0xc0, 0x84, 0x70, 0xb5, 0x32, 0xe3, 0x5d, ++ 0x4c, 0x78, 0xa4, 0x4e, 0x39, 0x4a, 0x86, 0x62, 0x73, 0x8a, 0x69, 0xc3, ++ 0x85, 0x61, 0x1d, 0xf7, 0x8d, 0x95, 0xc1, 0x31, 0xa4, 0x5f, 0x5e, 0xee, ++ 0x40, 0xb4, 0x40, 0xf8, 0xe1, 0x58, 0x15, 0x2a, 0x47, 0xac, 0x6e, 0x77, ++ 0xd8, 0xb2, 0x4a, 0x97, 0x84, 0xf1, 0xc0, 0xb8, 0x06, 0x75, 0xc4, 0x85, ++ 0x12, 0xe6, 0x29, 0xab, 0xcd, 0x5e, 0x6c, 0x23, 0xbf, 0x9b, 0x9b, 0x08, ++ 0xe0, 0x76, 0x62, 0xd1, 0xe5, 0x64, 0x6b, 0xcb, 0xcb, 0xf1, 0xda, 0xad, ++ 0x73, 0x1d, 0xc2, 0xfd, 0x57, 0x62, 0x63, 0x7a, 0x25, 0xee, 0x65, 0xec, ++ 0x3c, 0x63, 0xa0, 0x7b, 0x2e, 0xfd, 0xf5, 0x5e, 0xf2, 0xbf, 0x8e, 0xe4, ++ 0x6a, 0x74, 0xa4, 0xb7, 0xf2, 0x5e, 0x3b, 0xbe, 0xc8, 0x63, 0x43, 0x52, ++ 0xfc, 0x7b, 0x0d, 0x36, 0xa4, 0x6b, 0x10, 0x1d, 0xeb, 0xc0, 0x96, 0xf4, ++ 0x4d, 0x94, 0xc1, 0x43, 0xdd, 0xb6, 0x62, 0x7d, 0xba, 0x15, 0x0f, 0x70, ++ 0x2c, 0x0f, 0x70, 0x3e, 0xd4, 0xc4, 0x16, 0xfa, 0x58, 0x29, 0x3c, 0x43, ++ 0x37, 0x62, 0xdb, 0xd8, 0xad, 0xd8, 0xcc, 0x38, 0xb9, 0x76, 0xc9, 0xad, ++ 0xe8, 0x1e, 0xdb, 0x86, 0xae, 0xa4, 0xd1, 0x35, 0x97, 0xa9, 0xd8, 0xdb, ++ 0x4b, 0xb6, 0xe1, 0x7e, 0xca, 0xb1, 0x75, 0x9f, 0x85, 0xa2, 0x45, 0x8b, ++ 0x55, 0xa3, 0x32, 0x66, 0x79, 0x0d, 0x89, 0xcd, 0xaf, 0xad, 0xe9, 0x35, ++ 0x86, 0x73, 0xd8, 0xe2, 0x44, 0x81, 0xa1, 0x88, 0x8d, 0x66, 0xaf, 0xc7, ++ 0xff, 0x3b, 0x36, 0x8e, 0xb9, 0xb0, 0x69, 0xac, 0x4b, 0xb9, 0x5d, 0x6c, ++ 0xc5, 0xa5, 0x72, 0x3e, 0x23, 0xc4, 0xbe, 0x16, 0xa5, 0x79, 0xcc, 0x9e, ++ 0x67, 0xcd, 0x13, 0xee, 0x52, 0x56, 0xa7, 0xbf, 0xec, 0x40, 0xb1, 0xcc, ++ 0xc5, 0x4d, 0x98, 0x68, 0xf8, 0xaa, 0x35, 0x9a, 0x9d, 0xcf, 0x51, 0xba, ++ 0x8f, 0xdb, 0x1b, 0x76, 0xdf, 0xed, 0xad, 0xd3, 0xbb, 0x0e, 0xa8, 0xc2, ++ 0x2b, 0xdd, 0xc8, 0xd8, 0xf3, 0x59, 0xc0, 0x7e, 0x2a, 0x71, 0xd4, 0x93, ++ 0xe5, 0x12, 0xf3, 0xd9, 0x97, 0x95, 0x74, 0x71, 0xac, 0x94, 0x9b, 0xe3, ++ 0x99, 0x9b, 0xf0, 0xe2, 0x41, 0xea, 0xa7, 0x8b, 0x73, 0xd4, 0x45, 0xbd, ++ 0x7c, 0x29, 0x79, 0x8a, 0x31, 0x62, 0x2b, 0xbe, 0x94, 0xeb, 0xa7, 0x37, ++ 0x5d, 0x88, 0x62, 0xa3, 0x17, 0x5f, 0xd3, 0x0a, 0xe8, 0x63, 0xc2, 0x33, ++ 0x5e, 0x5b, 0x73, 0xc4, 0xf8, 0x02, 0xc7, 0xf0, 0x15, 0xb6, 0x21, 0x72, ++ 0xd5, 0x6b, 0x95, 0xc8, 0x96, 0xed, 0x21, 0x66, 0x17, 0x1b, 0xef, 0x5a, ++ 0x5f, 0xf3, 0xb4, 0xd9, 0x65, 0xcb, 0x59, 0xf6, 0xa5, 0x7e, 0x1f, 0xee, ++ 0xa4, 0x7d, 0x17, 0x25, 0x22, 0xd4, 0xbb, 0x9b, 0x9c, 0xaa, 0x85, 0x3a, ++ 0xe7, 0x1c, 0x53, 0xaf, 0x9b, 0x68, 0xcf, 0xce, 0xc4, 0x4a, 0xce, 0x83, ++ 0x86, 0xb2, 0x44, 0x2f, 0xe7, 0xc1, 0x03, 0x77, 0xa2, 0x0d, 0x9d, 0x94, ++ 0xcb, 0x95, 0x58, 0xcd, 0xb9, 0xa8, 0x46, 0x69, 0xa2, 0x9d, 0x73, 0x01, ++ 0xdc, 0x47, 0x5d, 0x6e, 0x0b, 0xfe, 0x5a, 0xd9, 0x5e, 0x25, 0xc3, 0x68, ++ 0xe5, 0xfc, 0x45, 0xb0, 0x31, 0x59, 0x13, 0xda, 0x29, 0x71, 0xdf, 0xc9, ++ 0x84, 0xcc, 0xf8, 0x67, 0x72, 0x61, 0x5a, 0xbf, 0xd1, 0xc3, 0xdf, 0x79, ++ 0x39, 0xf3, 0x38, 0x2e, 0x72, 0x4a, 0x7c, 0xcd, 0xcb, 0xe9, 0x42, 0x11, ++ 0x73, 0xbe, 0xc7, 0x3c, 0xf0, 0xb9, 0x58, 0xb6, 0x98, 0x65, 0x6f, 0xa7, ++ 0x9c, 0xb7, 0x53, 0xfe, 0xf9, 0x89, 0x35, 0xe8, 0xa6, 0x9c, 0x73, 0x87, ++ 0xdc, 0xe4, 0xa8, 0x3a, 0x1e, 0xa4, 0xee, 0x0f, 0x24, 0x8b, 0x50, 0xc1, ++ 0x79, 0xfe, 0x12, 0x7f, 0xef, 0xa4, 0x1f, 0xbd, 0x34, 0x60, 0xe1, 0xa9, ++ 0xa0, 0x86, 0x01, 0xad, 0x08, 0xdb, 0x03, 0x5b, 0xc8, 0xcb, 0x65, 0xae, ++ 0x98, 0x4f, 0x19, 0x25, 0x8c, 0xeb, 0x88, 0xb9, 0x1a, 0x75, 0xec, 0x08, ++ 0xb8, 0x31, 0xea, 0x41, 0xc4, 0x65, 0x44, 0x68, 0xe3, 0x2e, 0xf4, 0x6b, ++ 0x0a, 0x5c, 0xc4, 0xc3, 0x42, 0xfa, 0xd3, 0x2e, 0xc6, 0x5d, 0x57, 0x58, ++ 0xee, 0xd1, 0x4e, 0xc8, 0xc1, 0x2a, 0xc2, 0x46, 0xec, 0x65, 0xc5, 0xdf, ++ 0xea, 0x52, 0xb7, 0x51, 0x47, 0x25, 0x78, 0x6a, 0xe0, 0x2b, 0xe8, 0x60, ++ 0x5f, 0xbd, 0xc9, 0x52, 0xe6, 0x26, 0x7f, 0xa7, 0x64, 0x6c, 0xfc, 0x2c, ++ 0x45, 0x62, 0xf8, 0x49, 0x6b, 0xbe, 0x21, 0x76, 0x13, 0xc6, 0xfd, 0xe3, ++ 0xe5, 0x18, 0x18, 0xb8, 0x15, 0x5b, 0x59, 0x6e, 0x77, 0xb2, 0x02, 0xc6, ++ 0x60, 0x93, 0x5d, 0x67, 0x98, 0xfe, 0xd5, 0x9f, 0xd8, 0x86, 0xe5, 0xc9, ++ 0x9a, 0xc0, 0xb8, 0x12, 0xa5, 0x0e, 0x3d, 0xe8, 0x4b, 0x74, 0xd8, 0x3a, ++ 0x8d, 0x8f, 0x74, 0x62, 0xcb, 0xf8, 0xb5, 0xd8, 0x3b, 0xb2, 0x19, 0xf7, ++ 0x8d, 0x33, 0x7f, 0xb5, 0x6d, 0x59, 0xc5, 0xf6, 0x91, 0x5b, 0x95, 0xf5, ++ 0x6c, 0x6f, 0xcf, 0x10, 0xed, 0x99, 0x36, 0xfd, 0xe0, 0x3e, 0x23, 0xd3, ++ 0xe4, 0xd8, 0xac, 0xf8, 0xaa, 0x6e, 0x45, 0x97, 0x6d, 0x7b, 0x59, 0xbd, ++ 0xed, 0x4c, 0x2f, 0x60, 0x9e, 0xf3, 0x37, 0xd6, 0x13, 0x9e, 0x42, 0x7b, ++ 0x7e, 0x55, 0xea, 0xad, 0x39, 0x5e, 0x4a, 0x7b, 0x61, 0xee, 0x95, 0xb3, ++ 0x97, 0xed, 0xe9, 0xc5, 0xe4, 0x8d, 0x1e, 0xa4, 0xb4, 0x00, 0xf5, 0x91, ++ 0x9f, 0x07, 0x33, 0x67, 0x2f, 0x97, 0x59, 0xc6, 0xb6, 0xe5, 0x0f, 0xf9, ++ 0x82, 0xcc, 0x6f, 0x1b, 0x2a, 0x19, 0x5f, 0xd7, 0x07, 0x57, 0x2b, 0x0f, ++ 0x68, 0x57, 0xe6, 0xcc, 0x9b, 0x9f, 0x33, 0xc9, 0x13, 0xed, 0xb6, 0xe2, ++ 0x5f, 0xb1, 0x6d, 0xf7, 0xb6, 0x74, 0x23, 0x3a, 0xc7, 0x66, 0xb6, 0x9f, ++ 0xaf, 0x53, 0xc4, 0xb9, 0xc8, 0xcf, 0xb3, 0xde, 0x27, 0x58, 0xe6, 0x5f, ++ 0x94, 0xc7, 0xb2, 0x2f, 0xe7, 0xfa, 0x3f, 0x68, 0x31, 0x26, 0x39, 0x5d, ++ 0x86, 0x03, 0xc3, 0x81, 0xff, 0xa2, 0xc4, 0xaa, 0x9c, 0x94, 0x59, 0x21, ++ 0x96, 0xfc, 0x9d, 0xb5, 0x77, 0xb5, 0xcc, 0xcb, 0x72, 0x1a, 0x32, 0x14, ++ 0xd7, 0x15, 0x9f, 0x5d, 0x89, 0x75, 0x49, 0x91, 0xb5, 0x0d, 0xeb, 0x93, ++ 0xb6, 0x5c, 0xbe, 0xbc, 0x5c, 0xbd, 0xb4, 0x19, 0x2d, 0xb1, 0xc7, 0x96, ++ 0xa9, 0x8d, 0x76, 0x75, 0xff, 0x3e, 0x15, 0xcf, 0x05, 0x37, 0x28, 0xbe, ++ 0xd9, 0x12, 0x87, 0x6b, 0xd0, 0xb5, 0x4f, 0xfe, 0xfb, 0xc8, 0x77, 0xa3, ++ 0xca, 0xf4, 0xec, 0x7e, 0x96, 0x6b, 0xc2, 0xba, 0x7d, 0x55, 0x98, 0xcb, ++ 0xb1, 0xae, 0x35, 0xff, 0x93, 0xf2, 0xde, 0x2c, 0x19, 0x4f, 0x5b, 0x2e, ++ 0x96, 0xd7, 0x60, 0xdb, 0x3e, 0xf1, 0x21, 0xf9, 0xdd, 0x8c, 0xed, 0x37, ++ 0xd6, 0xe4, 0xe2, 0xfc, 0x7f, 0xe7, 0xbc, 0x74, 0x29, 0x77, 0x10, 0x17, ++ 0xa2, 0xc4, 0x05, 0xda, 0x94, 0xd2, 0x46, 0x5c, 0xb8, 0x2d, 0x87, 0x0b, ++ 0xa5, 0xc4, 0x85, 0x95, 0xe9, 0xf7, 0x28, 0x8f, 0xf8, 0xe2, 0x07, 0xe5, ++ 0xf9, 0x22, 0xe5, 0x39, 0x16, 0x9c, 0x0b, 0xd8, 0xf2, 0x34, 0x91, 0xc7, ++ 0x54, 0x71, 0x0e, 0x2d, 0xc6, 0x07, 0x45, 0x19, 0xb6, 0xf5, 0xdc, 0x44, ++ 0x99, 0xc5, 0xa6, 0x2c, 0xca, 0xfd, 0x3b, 0xd4, 0xda, 0xeb, 0x03, 0x57, ++ 0xe5, 0x59, 0xb7, 0xef, 0x7d, 0xe6, 0x08, 0xf2, 0x9b, 0x78, 0xd1, 0x58, ++ 0x43, 0x9c, 0x6b, 0x22, 0xee, 0xb9, 0x38, 0x2e, 0xc1, 0x3a, 0x91, 0xcd, ++ 0x45, 0xbf, 0x90, 0xb6, 0x45, 0x27, 0x11, 0x47, 0x76, 0x1e, 0xf2, 0xf3, ++ 0xec, 0xa4, 0x1f, 0xbb, 0x51, 0x11, 0xd6, 0x23, 0x77, 0x39, 0x64, 0xce, ++ 0x88, 0xf2, 0x83, 0x6d, 0xb9, 0xbe, 0xfe, 0x5a, 0xa9, 0xad, 0xec, 0xa3, ++ 0x9c, 0x27, 0x94, 0xbb, 0x39, 0x2e, 0x5f, 0x61, 0x79, 0xa4, 0x34, 0xec, ++ 0x6f, 0x8f, 0x7f, 0x28, 0x36, 0xde, 0x91, 0xce, 0xf2, 0x4b, 0x75, 0x30, ++ 0x66, 0x15, 0xd3, 0xf6, 0x9d, 0x86, 0xff, 0xf2, 0xed, 0xec, 0x61, 0xfe, ++ 0x41, 0xe1, 0x33, 0x26, 0xdb, 0xca, 0xf7, 0x55, 0x4d, 0x2c, 0xf9, 0xb3, ++ 0x9c, 0x1d, 0xac, 0x54, 0x98, 0x37, 0xb4, 0x46, 0x6c, 0x7b, 0xd8, 0x4d, ++ 0x7d, 0x9d, 0x50, 0x3e, 0x2d, 0x9c, 0xd9, 0xe6, 0x18, 0x31, 0x65, 0x05, ++ 0x71, 0xa5, 0x22, 0xa1, 0x44, 0x3c, 0xe1, 0xfa, 0xad, 0x95, 0xf0, 0xb7, ++ 0x3e, 0xc1, 0x3e, 0x2b, 0xc9, 0x33, 0xef, 0x62, 0xac, 0x4d, 0xb0, 0xcf, ++ 0x15, 0xec, 0x73, 0x55, 0x7a, 0x1b, 0xdb, 0x15, 0x6c, 0x55, 0x31, 0x77, ++ 0x04, 0x6e, 0x0f, 0xed, 0x60, 0xb8, 0xd6, 0x89, 0xd0, 0xe2, 0x5f, 0x00, ++ 0xb3, 0x10, 0x55, 0x99, 0xbf, 0xcf, 0x4f, 0x48, 0x2e, 0xf5, 0xda, 0x9a, ++ 0xa6, 0x94, 0x60, 0xa9, 0x86, 0xd2, 0x21, 0x8f, 0xc4, 0x23, 0xf4, 0x06, ++ 0xab, 0x95, 0xbd, 0x36, 0xde, 0xaa, 0x28, 0x1a, 0x51, 0x70, 0x7d, 0xf0, ++ 0x71, 0x65, 0x74, 0x76, 0x16, 0xf3, 0x55, 0xea, 0xa3, 0x67, 0x52, 0xb0, ++ 0x71, 0x9a, 0xd8, 0x78, 0x4c, 0xc9, 0xae, 0xc7, 0xd0, 0xef, 0x93, 0x88, ++ 0x95, 0x87, 0x65, 0x0d, 0xc4, 0xdf, 0xf9, 0x09, 0x65, 0x1b, 0xb1, 0xd0, ++ 0xc5, 0x38, 0x54, 0x4a, 0x6c, 0xb4, 0xe3, 0xf4, 0x9a, 0x78, 0x7f, 0x35, ++ 0xfa, 0xe8, 0xdb, 0x1d, 0xe3, 0xa7, 0xee, 0x2e, 0x45, 0x15, 0xff, 0x7b, ++ 0x78, 0xcc, 0xe1, 0xe1, 0xa6, 0x2f, 0xbb, 0xe1, 0xe8, 0x17, 0xbe, 0xd7, ++ 0xc0, 0x58, 0x55, 0x8a, 0xe2, 0x7e, 0x13, 0x9b, 0x29, 0x4f, 0xe1, 0x60, ++ 0x23, 0xe3, 0x09, 0xfd, 0x3c, 0x59, 0x89, 0xdb, 0x06, 0x96, 0x60, 0x83, ++ 0x8d, 0x5f, 0x55, 0x38, 0x3b, 0x70, 0xa3, 0x8d, 0x1b, 0x8f, 0x26, 0x67, ++ 0xe1, 0xbd, 0x7d, 0x37, 0xd9, 0x18, 0x37, 0xc0, 0xd8, 0xec, 0x1d, 0x09, ++ 0xa1, 0x8b, 0x6d, 0x7a, 0x46, 0x6e, 0xc1, 0xb6, 0x71, 0x2f, 0x75, 0x64, ++ 0x30, 0x0e, 0xa8, 0xef, 0xfb, 0x3e, 0x2b, 0x76, 0x3e, 0x13, 0xfb, 0x65, ++ 0xae, 0xa5, 0xce, 0x3f, 0xd0, 0x58, 0xe5, 0xb7, 0xd3, 0xe6, 0xc2, 0x59, ++ 0x1d, 0x65, 0x75, 0x72, 0x03, 0x75, 0x72, 0x57, 0x9a, 0xe6, 0x30, 0xe4, ++ 0xe4, 0x5c, 0x93, 0x43, 0x54, 0x56, 0xd1, 0x2f, 0x0b, 0x78, 0xd0, 0xfe, ++ 0xc7, 0x3e, 0xc6, 0xd8, 0x9e, 0xe1, 0x7c, 0xf2, 0xb7, 0x29, 0xf3, 0x29, ++ 0xf1, 0xd3, 0x41, 0xcc, 0x55, 0xa8, 0xdf, 0x7f, 0x04, 0xae, 0xc9, 0xe6, ++ 0x36, 0x79, 0x5d, 0xa9, 0x1c, 0x7f, 0x73, 0x3c, 0x63, 0x73, 0x7a, 0x66, ++ 0x44, 0xba, 0xca, 0x7b, 0x1d, 0xe3, 0xe4, 0xdc, 0x09, 0xf1, 0x59, 0x0f, ++ 0xed, 0xb9, 0x81, 0xfa, 0xd2, 0x18, 0x3b, 0x4c, 0xe2, 0xdc, 0x1c, 0xb8, ++ 0x38, 0x8e, 0x0d, 0xd4, 0x4f, 0x29, 0xc7, 0xb1, 0x85, 0xe5, 0xee, 0xe3, ++ 0xbd, 0xfb, 0xc6, 0xab, 0x78, 0x78, 0x78, 0xcc, 0xe1, 0xf1, 0x33, 0x62, ++ 0x56, 0x23, 0xed, 0xd8, 0x81, 0x82, 0x21, 0x15, 0xcf, 0x9a, 0x0a, 0x2e, ++ 0x35, 0xb0, 0xbf, 0xda, 0xab, 0x58, 0x27, 0xb1, 0xcc, 0x93, 0xf8, 0x0a, ++ 0x71, 0xce, 0x87, 0xd5, 0xe4, 0x04, 0x9d, 0xfb, 0x34, 0xb8, 0x82, 0x29, ++ 0xe6, 0x4c, 0x22, 0xc3, 0x89, 0x1c, 0xc7, 0x9c, 0xcf, 0x5c, 0xa7, 0x3e, ++ 0x44, 0x1b, 0xd2, 0x36, 0xda, 0x36, 0x14, 0x63, 0x7c, 0x0e, 0x30, 0xd7, ++ 0xcf, 0xda, 0x6e, 0xf3, 0x07, 0xec, 0x88, 0x3e, 0xc6, 0xf1, 0xcc, 0x0d, ++ 0xeb, 0xbe, 0xbb, 0xe9, 0x0b, 0xc2, 0xf9, 0x0a, 0x13, 0xc0, 0x81, 0x81, ++ 0x36, 0x54, 0xd0, 0x66, 0x3c, 0x8b, 0xc7, 0x91, 0xac, 0xea, 0xb3, 0x6d, ++ 0x35, 0xdb, 0x76, 0x51, 0xa4, 0x2c, 0x5c, 0x1f, 0x95, 0xb6, 0x27, 0x72, ++ 0x6d, 0x2f, 0x63, 0xdb, 0x71, 0xb6, 0xbd, 0xfc, 0x0f, 0xda, 0x9e, 0x19, ++ 0xef, 0x7a, 0x72, 0x71, 0x59, 0xf2, 0xe6, 0x3c, 0x6e, 0xe7, 0x39, 0xc6, ++ 0x7f, 0x9b, 0x7d, 0x15, 0x27, 0x07, 0x64, 0xee, 0xbc, 0x59, 0x9f, 0xfd, ++ 0x20, 0x36, 0x5f, 0x6d, 0x6b, 0x6f, 0x3e, 0xc6, 0x9b, 0x95, 0x33, 0xda, ++ 0x9a, 0xcb, 0xfb, 0x37, 0x27, 0x85, 0x4b, 0xb4, 0xc1, 0xa2, 0xac, 0x2f, ++ 0x1a, 0x7a, 0x57, 0x93, 0xc3, 0xd8, 0x7a, 0x99, 0xb9, 0xce, 0x9d, 0x57, ++ 0xfa, 0x92, 0xb5, 0x91, 0x36, 0x2c, 0xec, 0xd7, 0x3b, 0x77, 0x93, 0x8f, ++ 0x1e, 0x09, 0xea, 0x91, 0xef, 0x40, 0x8f, 0x15, 0x2a, 0xaf, 0xa1, 0x60, ++ 0xf2, 0x2c, 0x06, 0xd2, 0x3f, 0x62, 0xbe, 0x79, 0x8a, 0x6d, 0xba, 0x95, ++ 0xd2, 0xc9, 0x5e, 0x44, 0x59, 0xcf, 0xcd, 0x7a, 0xee, 0x7e, 0xb8, 0xcb, ++ 0x58, 0x6f, 0xa2, 0x3f, 0x66, 0xb9, 0xc8, 0x05, 0xd5, 0xb0, 0xde, 0x5e, ++ 0xa6, 0x18, 0xd1, 0x0d, 0x6c, 0x7b, 0x25, 0x63, 0x59, 0x71, 0xa2, 0x9b, ++ 0x3c, 0x40, 0xf7, 0xfe, 0xad, 0xaa, 0x77, 0xad, 0xc3, 0x6b, 0xf8, 0x29, ++ 0xc9, 0xe3, 0xfc, 0xc4, 0x59, 0x24, 0xd9, 0x9e, 0x35, 0xa1, 0x91, 0xcf, ++ 0xbc, 0x6f, 0x85, 0xea, 0x66, 0x3b, 0xa5, 0xdd, 0xcb, 0x13, 0x75, 0xef, ++ 0xc7, 0xaf, 0xe2, 0xb9, 0xe6, 0x32, 0x96, 0x7c, 0x08, 0x9f, 0x1a, 0x5a, ++ 0x96, 0xc5, 0xd7, 0x6d, 0x71, 0x85, 0xb7, 0x3e, 0x78, 0xbc, 0x31, 0x6b, ++ 0xb7, 0xbe, 0x94, 0x1b, 0x67, 0x3d, 0xe2, 0x4b, 0xcc, 0x7f, 0xf6, 0x37, ++ 0x60, 0xcf, 0x7e, 0xe6, 0x95, 0x6a, 0x7d, 0xa8, 0x58, 0xa9, 0x64, 0x4e, ++ 0x34, 0x64, 0xf3, 0x61, 0xa7, 0x71, 0xd0, 0xce, 0x99, 0x25, 0x3e, 0x48, ++ 0x9d, 0x05, 0x29, 0x89, 0x7f, 0xb2, 0x9e, 0xf3, 0xda, 0x9a, 0xf5, 0x71, ++ 0xfa, 0xad, 0xb6, 0x9d, 0x65, 0xb6, 0xe4, 0xd6, 0xf1, 0x65, 0x0d, 0x63, ++ 0xfb, 0x0c, 0x4e, 0xf2, 0x85, 0x19, 0xb1, 0xaa, 0xde, 0x57, 0x79, 0x25, ++ 0x8e, 0x6c, 0xcd, 0x95, 0xbf, 0xc5, 0x95, 0x95, 0xcd, 0x3d, 0x03, 0xcf, ++ 0x06, 0x78, 0x2d, 0xeb, 0x0b, 0x57, 0xe3, 0xdd, 0xae, 0xdc, 0xdc, 0xa4, ++ 0x5c, 0x59, 0xdc, 0xdf, 0xe6, 0xce, 0xaf, 0x17, 0x65, 0xcb, 0xb4, 0x14, ++ 0xa0, 0x78, 0xef, 0x95, 0xd8, 0x12, 0x23, 0x96, 0x6f, 0xdd, 0x97, 0x5d, ++ 0x9f, 0x2c, 0xbb, 0x51, 0x70, 0xbb, 0x06, 0x5f, 0xb4, 0xfd, 0xfe, 0x9b, ++ 0xae, 0xac, 0x1d, 0x38, 0x73, 0xe3, 0x32, 0x69, 0x83, 0xd7, 0xc9, 0x33, ++ 0x81, 0x1c, 0x7e, 0xea, 0xbc, 0xbf, 0x1d, 0x32, 0x17, 0x2e, 0xfa, 0xe7, ++ 0x93, 0xa6, 0x03, 0xd3, 0xb3, 0xb2, 0x7c, 0x5d, 0x1d, 0x69, 0x40, 0xcf, ++ 0x61, 0xe2, 0x0d, 0x7d, 0xa8, 0x35, 0xb8, 0xca, 0x42, 0xa5, 0xac, 0x1b, ++ 0x54, 0xa1, 0x64, 0x44, 0x78, 0x33, 0x79, 0xc6, 0xe1, 0x17, 0xed, 0xb1, ++ 0x6c, 0x4f, 0x65, 0xd7, 0x45, 0x76, 0x25, 0x7b, 0xdf, 0xdf, 0xa4, 0x09, ++ 0x5e, 0x88, 0x6d, 0xac, 0x59, 0xb3, 0xd0, 0x9f, 0xf1, 0x39, 0xa0, 0x9b, ++ 0xbb, 0x79, 0xe1, 0x95, 0xf8, 0x17, 0xb0, 0xa3, 0x4a, 0x41, 0x97, 0x51, ++ 0x01, 0xc7, 0xe2, 0xdf, 0x58, 0x9b, 0x56, 0xcb, 0x3d, 0xb7, 0x2b, 0x8b, ++ 0x2f, 0x1f, 0x65, 0xdf, 0x32, 0x6e, 0xe1, 0x74, 0x6e, 0x94, 0xd0, 0xa7, ++ 0xee, 0x70, 0x08, 0xe7, 0x54, 0x18, 0x3b, 0xed, 0xb9, 0xc0, 0xf6, 0x51, ++ 0x05, 0x7b, 0x46, 0x05, 0x33, 0x9d, 0xc4, 0x41, 0x2f, 0x76, 0x8d, 0x0a, ++ 0x0e, 0xba, 0x88, 0x83, 0x73, 0xb1, 0x63, 0x54, 0x70, 0xb0, 0x00, 0x3f, ++ 0x1e, 0xb8, 0x16, 0x8f, 0xf2, 0xf7, 0x23, 0xc9, 0x42, 0x84, 0xf6, 0x7d, ++ 0x0c, 0x07, 0x46, 0x85, 0x3f, 0xb9, 0x91, 0x1c, 0xaa, 0x46, 0x72, 0x34, ++ 0xcb, 0x25, 0xca, 0x87, 0x3e, 0x8e, 0x04, 0x7f, 0xf7, 0x93, 0xf7, 0xa5, ++ 0x06, 0xe7, 0x21, 0xce, 0xdf, 0xb2, 0xde, 0x56, 0x4a, 0xf9, 0xe3, 0xfe, ++ 0x12, 0xac, 0x1f, 0x94, 0x1c, 0xba, 0x7d, 0xcd, 0x7d, 0xfe, 0xf9, 0xec, ++ 0xb3, 0x1a, 0x7b, 0xc8, 0xd9, 0x5a, 0x07, 0x7d, 0xe8, 0xe3, 0xef, 0x5d, ++ 0xc9, 0x32, 0xbc, 0x31, 0xa0, 0xdb, 0xfd, 0xf5, 0x24, 0x97, 0x2d, 0x73, ++ 0x19, 0xe5, 0x58, 0x36, 0xb0, 0x00, 0x3b, 0x47, 0x05, 0x7b, 0x2b, 0x88, ++ 0xbd, 0x35, 0x78, 0x64, 0x54, 0xf8, 0xa5, 0x06, 0xcf, 0x3e, 0x03, 0xc3, ++ 0xa3, 0xb2, 0x26, 0x5c, 0x89, 0x4b, 0x83, 0x7e, 0x0c, 0xd8, 0xfd, 0x9b, ++ 0x48, 0x24, 0x43, 0x94, 0xcf, 0x83, 0xb2, 0x91, 0x8c, 0xb7, 0x1c, 0x0a, ++ 0xa6, 0xfc, 0x01, 0xf4, 0x1f, 0x9e, 0x83, 0xe2, 0x11, 0xdd, 0xdc, 0x02, ++ 0xfd, 0xf2, 0x7d, 0xb8, 0x0e, 0x7b, 0x0e, 0x7b, 0x51, 0x38, 0x52, 0x01, ++ 0x77, 0xb0, 0x01, 0xbb, 0x0e, 0x7f, 0x02, 0x3b, 0x0e, 0x57, 0x13, 0x3b, ++ 0x81, 0xe7, 0x52, 0x26, 0xfa, 0x88, 0xc1, 0x73, 0x19, 0x63, 0xce, 0xa5, ++ 0x65, 0x1e, 0x65, 0x7e, 0x14, 0x94, 0xfa, 0x2b, 0x18, 0xa3, 0xe4, 0xb7, ++ 0x5c, 0x0b, 0xd9, 0xd8, 0x9e, 0x5d, 0xa7, 0xd2, 0x63, 0xbb, 0x60, 0xeb, ++ 0x1b, 0x99, 0x94, 0xe8, 0x5e, 0xd6, 0x84, 0x66, 0xda, 0xd3, 0x2e, 0x7b, ++ 0x8d, 0xfe, 0xaa, 0x5d, 0xde, 0x96, 0xb3, 0x4b, 0x7b, 0x4d, 0x0d, 0xcf, ++ 0x5c, 0xc9, 0x73, 0xc1, 0xc2, 0x7e, 0xd3, 0xa9, 0xc0, 0xc7, 0x7c, 0xd7, ++ 0xf7, 0xec, 0x87, 0xd6, 0xd6, 0xae, 0xae, 0xff, 0xcc, 0x5c, 0x83, 0x95, ++ 0x67, 0x4f, 0x2a, 0xe3, 0x79, 0x01, 0x62, 0x9a, 0xac, 0x51, 0xd5, 0x6b, ++ 0xd4, 0xca, 0x87, 0xf2, 0xee, 0xf2, 0x68, 0x51, 0xb8, 0x11, 0xbe, 0x89, ++ 0x6a, 0xdf, 0x1b, 0x71, 0xd1, 0xe9, 0xef, 0x2c, 0xb7, 0x61, 0x78, 0x8f, ++ 0xa1, 0xda, 0xf7, 0x7a, 0xea, 0xbd, 0x02, 0x94, 0x97, 0xe2, 0xb6, 0xf8, ++ 0x47, 0xd7, 0x53, 0xc3, 0x50, 0x96, 0x37, 0x7a, 0xc9, 0xfb, 0xe1, 0xbc, ++ 0xbd, 0x0e, 0x33, 0xfe, 0xc8, 0x47, 0xc2, 0x50, 0x4f, 0x37, 0x86, 0x98, ++ 0xeb, 0x67, 0x9f, 0xe7, 0x2c, 0x4d, 0xeb, 0xde, 0x88, 0x92, 0x7d, 0x66, ++ 0xd3, 0x19, 0xfc, 0x3d, 0xed, 0xba, 0x5b, 0x38, 0x0b, 0xfb, 0x02, 0xb6, ++ 0xc4, 0x2d, 0xeb, 0x19, 0xea, 0x40, 0x9e, 0x15, 0xbe, 0x95, 0xfa, 0xad, ++ 0x35, 0xe5, 0x71, 0xe2, 0x4d, 0x63, 0x66, 0x7b, 0xe4, 0x7a, 0x61, 0x93, ++ 0xb1, 0xcf, 0x3e, 0x51, 0x27, 0x8c, 0xfa, 0xad, 0x47, 0x98, 0x27, 0x2f, ++ 0xf4, 0xeb, 0xbe, 0x04, 0xfe, 0xaf, 0x25, 0xbc, 0x70, 0x54, 0xc9, 0xaf, ++ 0xdb, 0x7d, 0x78, 0xed, 0xa4, 0x3c, 0xea, 0xe2, 0xf8, 0x0e, 0xc5, 0xf5, ++ 0xbe, 0x18, 0xf3, 0xb6, 0x88, 0x07, 0x51, 0x67, 0xb8, 0xda, 0xb7, 0x2b, ++ 0x6e, 0x8f, 0xd3, 0xbc, 0xc8, 0xb9, 0x3b, 0xdd, 0x58, 0xed, 0xdb, 0x9e, ++ 0x12, 0x1b, 0x54, 0x38, 0x96, 0x46, 0x3c, 0x96, 0x52, 0x71, 0xef, 0xc3, ++ 0x1e, 0x6c, 0xe8, 0x2f, 0xc5, 0xd6, 0xfe, 0xaf, 0xc0, 0xb8, 0xde, 0x89, ++ 0x4d, 0xcc, 0xfd, 0x36, 0xf6, 0x17, 0x52, 0x8f, 0x1a, 0x36, 0xf7, 0x3b, ++ 0xd1, 0x70, 0x7d, 0x39, 0x62, 0xb3, 0x0b, 0xf1, 0x12, 0x7d, 0xf7, 0xfa, ++ 0x60, 0x09, 0x46, 0x6d, 0xce, 0x21, 0xd8, 0x20, 0xbc, 0x4d, 0xf4, 0xc6, ++ 0x38, 0x68, 0x08, 0x86, 0x7c, 0xd4, 0xfa, 0xcc, 0xbb, 0x56, 0x66, 0xf6, ++ 0x5e, 0x9b, 0x4f, 0x3a, 0xc2, 0xa2, 0x1b, 0xa9, 0x2b, 0x6b, 0x4d, 0x1e, ++ 0xc6, 0xc8, 0x0f, 0xe8, 0x51, 0x99, 0x1f, 0xf6, 0x4f, 0x35, 0x29, 0x0e, ++ 0x84, 0xfc, 0xe5, 0xd1, 0x8a, 0x70, 0x08, 0xcb, 0xd3, 0x3d, 0x5e, 0xaf, ++ 0xfd, 0x2c, 0x2b, 0x8c, 0x8b, 0x4b, 0x4c, 0xdc, 0x9d, 0x86, 0x73, 0x39, ++ 0x75, 0xdf, 0x42, 0xbd, 0xee, 0x34, 0x7f, 0x6f, 0x65, 0xf3, 0x1a, 0x37, ++ 0xf1, 0xd2, 0xb2, 0x36, 0x52, 0xbf, 0xcc, 0x29, 0xf0, 0xb3, 0x9c, 0x7e, ++ 0x45, 0xa7, 0x25, 0x13, 0xbf, 0xb5, 0x4e, 0x53, 0xbf, 0x6e, 0xb6, 0xe7, ++ 0x66, 0x7b, 0x45, 0x13, 0x1f, 0xd4, 0x73, 0x21, 0xe5, 0x59, 0x6e, 0xcb, ++ 0xa0, 0xcb, 0xb3, 0x00, 0x5f, 0x44, 0xc9, 0xf3, 0xd0, 0x7f, 0x6f, 0x4c, ++ 0xaf, 0xd9, 0xeb, 0x6d, 0x8f, 0xa7, 0x2d, 0x6b, 0xc8, 0x14, 0xfd, 0xfb, ++ 0xa8, 0x7f, 0x59, 0x77, 0x91, 0x39, 0x68, 0x40, 0xa4, 0x4a, 0xef, 0x03, ++ 0xbe, 0xcd, 0xc4, 0x57, 0xc1, 0x2c, 0xe6, 0x6f, 0xdf, 0x68, 0x2b, 0xc5, ++ 0x1b, 0xf1, 0x32, 0x7b, 0xdc, 0x37, 0xd7, 0x5a, 0x56, 0x70, 0xb1, 0x0f, ++ 0x97, 0x8d, 0xfa, 0xd0, 0x22, 0x55, 0x67, 0x4c, 0xa0, 0xff, 0xd2, 0x7e, ++ 0x7b, 0x92, 0xf3, 0x38, 0x5f, 0xe2, 0xf3, 0xd8, 0x4a, 0x7b, 0xf2, 0x39, ++ 0xc2, 0xc0, 0xf9, 0xb8, 0x11, 0xd8, 0xc9, 0xfe, 0xc7, 0x3c, 0x61, 0xec, ++ 0x48, 0xaa, 0x2d, 0x4e, 0x92, 0xcf, 0x22, 0xe6, 0x7a, 0xbb, 0xf1, 0x53, ++ 0x6b, 0xd4, 0x63, 0xa1, 0x80, 0xbc, 0xa8, 0xd8, 0xf8, 0x04, 0x9e, 0xd7, ++ 0x1c, 0x78, 0x21, 0x30, 0x07, 0xd1, 0x4a, 0x07, 0xf3, 0x90, 0x37, 0xad, ++ 0x1f, 0x78, 0xa4, 0x1f, 0x19, 0x4b, 0x21, 0xc7, 0xa5, 0xd8, 0x78, 0xb7, ++ 0x2b, 0x19, 0xa6, 0xbe, 0x3f, 0xdc, 0xff, 0xff, 0xb5, 0xa6, 0x3d, 0xd2, ++ 0xbf, 0xae, 0xf9, 0xc8, 0xcf, 0x9f, 0xfc, 0xc8, 0x75, 0x96, 0x00, 0xc7, ++ 0x7b, 0x2d, 0x5e, 0xd4, 0x9c, 0xcc, 0x43, 0xcf, 0x5a, 0x67, 0x3c, 0xd9, ++ 0x36, 0x12, 0x66, 0x66, 0x6e, 0xf9, 0x15, 0x1e, 0x03, 0xad, 0x22, 0xec, ++ 0xf4, 0x69, 0xf4, 0xd1, 0xa5, 0x39, 0xee, 0xd2, 0x46, 0x7e, 0x71, 0x57, ++ 0xfa, 0x09, 0x5b, 0x07, 0x37, 0xd7, 0x8a, 0x3e, 0x25, 0x7f, 0x7a, 0xd2, ++ 0xc2, 0x1c, 0x91, 0xe5, 0x1b, 0xbc, 0x1e, 0x46, 0x2c, 0x9d, 0x97, 0x51, ++ 0x74, 0xfe, 0xfd, 0x42, 0xc1, 0xfa, 0x5d, 0xc9, 0xe5, 0xd9, 0x73, 0x55, ++ 0x7e, 0xff, 0xc0, 0x2e, 0xd7, 0x43, 0x3d, 0xf7, 0xd0, 0xf6, 0x18, 0x53, ++ 0x18, 0x67, 0xe4, 0xe9, 0xac, 0x46, 0xac, 0xb6, 0xb0, 0xc3, 0x74, 0x31, ++ 0x47, 0xae, 0xc0, 0x2e, 0x93, 0xf6, 0x6a, 0xa8, 0x0b, 0x9c, 0xb0, 0x70, ++ 0xda, 0x94, 0x73, 0x17, 0xa6, 0x3d, 0x0e, 0xec, 0x36, 0x9d, 0xe8, 0x34, ++ 0x54, 0x5d, 0xae, 0x3b, 0x82, 0x72, 0xee, 0x82, 0x6f, 0xb6, 0x82, 0xbd, ++ 0x21, 0x15, 0x9b, 0x8d, 0x1e, 0x9f, 0x5c, 0x5f, 0x1a, 0x94, 0x73, 0x05, ++ 0x1d, 0xd4, 0x65, 0x8c, 0x39, 0xf6, 0x16, 0xb6, 0xbb, 0x3d, 0x98, 0x5d, ++ 0x4f, 0x8f, 0xc2, 0xb2, 0xf6, 0x9a, 0xcd, 0x37, 0x97, 0xb0, 0xdc, 0x05, ++ 0x53, 0x62, 0xce, 0x6b, 0xff, 0x69, 0xa1, 0x3f, 0x16, 0x29, 0x80, 0x1e, ++ 0x2d, 0xa2, 0x7f, 0xef, 0xea, 0x9f, 0xcf, 0x7a, 0x12, 0x33, 0x9c, 0xde, ++ 0x3d, 0x90, 0x75, 0x32, 0xbf, 0xef, 0x75, 0x72, 0xf6, 0x51, 0x4f, 0x1d, ++ 0x67, 0xc4, 0xf0, 0x9d, 0xe3, 0x7c, 0x57, 0x18, 0xce, 0xad, 0x2f, 0x43, ++ 0xef, 0x2c, 0x52, 0xea, 0x02, 0xe5, 0x70, 0x21, 0x46, 0x5e, 0x7f, 0x78, ++ 0x82, 0x79, 0x79, 0xd2, 0xd0, 0x8e, 0xda, 0x6b, 0xed, 0xa5, 0x1c, 0x5f, ++ 0x29, 0xe3, 0x8c, 0x5f, 0x9b, 0x52, 0xf2, 0xe7, 0xf3, 0x05, 0x53, 0xa2, ++ 0x8e, 0xb0, 0xe0, 0x62, 0xcc, 0x7a, 0xba, 0x91, 0xea, 0x30, 0xdc, 0xbe, ++ 0x68, 0xaa, 0x94, 0x87, 0xc6, 0xc3, 0xe3, 0xdb, 0x90, 0xf2, 0xfa, 0x3a, ++ 0x52, 0xf0, 0xad, 0x4b, 0xe5, 0xed, 0x39, 0x8f, 0x09, 0x82, 0x89, 0x96, ++ 0x25, 0xcf, 0xa0, 0x9f, 0x4c, 0x4b, 0x5b, 0xd9, 0xf8, 0x57, 0x40, 0xd9, ++ 0x9f, 0xa1, 0x8f, 0xb8, 0x18, 0xe3, 0x76, 0x1b, 0x31, 0x42, 0xac, 0x65, ++ 0x19, 0xe4, 0x41, 0x05, 0x8a, 0x0f, 0xbb, 0x1a, 0x7e, 0x43, 0x3b, 0x00, ++ 0x36, 0xa4, 0x3e, 0xe9, 0xce, 0xce, 0x85, 0xf8, 0xa7, 0x60, 0x87, 0x8f, ++ 0x71, 0xdb, 0xeb, 0xeb, 0x61, 0x3f, 0x3b, 0x52, 0x33, 0x7d, 0x47, 0xc1, ++ 0xed, 0x6c, 0xab, 0x39, 0x08, 0xe7, 0xb2, 0x86, 0x7f, 0xb5, 0x32, 0x9e, ++ 0x99, 0xcf, 0x5b, 0xdd, 0x8c, 0xd5, 0x70, 0xae, 0x6b, 0x90, 0x73, 0x05, ++ 0xcd, 0x21, 0x39, 0x57, 0xb0, 0xce, 0x90, 0x73, 0x62, 0x7d, 0x5a, 0xce, ++ 0x2d, 0xeb, 0xea, 0xf9, 0x87, 0x31, 0xcc, 0xc4, 0x7d, 0x49, 0x59, 0xb3, ++ 0x13, 0x0c, 0x73, 0xfb, 0x5e, 0x48, 0x35, 0x60, 0x73, 0x52, 0x9e, 0xab, ++ 0x31, 0x47, 0x31, 0x4a, 0x7d, 0xcf, 0xa7, 0x6e, 0xc1, 0xbd, 0xfb, 0x43, ++ 0xe8, 0xdc, 0x8f, 0x86, 0x22, 0x8e, 0xa1, 0x30, 0xe8, 0xf7, 0x8d, 0x43, ++ 0xf3, 0x3d, 0x45, 0x9d, 0x9c, 0xa2, 0x9c, 0xa7, 0x3f, 0x20, 0xa7, 0xe8, ++ 0x10, 0xbe, 0x2f, 0xc6, 0xdd, 0x48, 0x05, 0xdf, 0xb3, 0x62, 0x76, 0x0e, ++ 0xe5, 0xf1, 0xdd, 0x1f, 0xf7, 0x21, 0x63, 0xe7, 0x72, 0x54, 0x38, 0x31, ++ 0xbf, 0x37, 0x19, 0x8b, 0xa8, 0xc8, 0xcf, 0xaf, 0x1e, 0x92, 0xb9, 0x3d, ++ 0x1f, 0x97, 0x7b, 0x91, 0xaf, 0xa8, 0x8c, 0x67, 0xaa, 0x6a, 0x59, 0x03, ++ 0xf2, 0x5c, 0x40, 0x9d, 0x2f, 0xfa, 0x91, 0x67, 0x1b, 0x31, 0xc9, 0x35, ++ 0x1b, 0x78, 0x5d, 0x5b, 0x44, 0xb7, 0xa3, 0x9e, 0x8a, 0x0d, 0x8f, 0xaf, ++ 0x7e, 0xd2, 0xeb, 0x33, 0x27, 0xe1, 0xbb, 0x6e, 0x72, 0xa6, 0x08, 0xe4, ++ 0x18, 0xea, 0x47, 0x61, 0x88, 0xc7, 0xb7, 0x31, 0x3e, 0x9f, 0xfc, 0x34, ++ 0x66, 0x2d, 0x6d, 0xbc, 0x68, 0xcd, 0x0f, 0x1b, 0x99, 0xd3, 0x94, 0xe1, ++ 0xbd, 0x9b, 0xf4, 0xd8, 0x5c, 0xc7, 0xa9, 0x07, 0xb5, 0x19, 0x7d, 0x5c, ++ 0x0a, 0xfe, 0x7f, 0xed, 0x23, 0x1f, 0x1f, 0x69, 0x0f, 0x8d, 0x32, 0x06, ++ 0x89, 0x93, 0xcc, 0xa1, 0xaa, 0x64, 0x2c, 0x9f, 0xcc, 0xf1, 0xbd, 0xfc, ++ 0xb8, 0x14, 0xce, 0xb5, 0x9b, 0xba, 0xc8, 0xc7, 0x3e, 0xcb, 0xda, 0x6e, ++ 0x78, 0x73, 0x6b, 0xe7, 0x9c, 0xb3, 0xf4, 0xa9, 0x9b, 0x9d, 0xcc, 0xf5, ++ 0x2f, 0x98, 0xcd, 0x7f, 0xe6, 0x44, 0xc4, 0x5b, 0xc8, 0x98, 0x2c, 0x6b, ++ 0x56, 0x4f, 0x35, 0x4c, 0x5b, 0x53, 0xcc, 0x9f, 0x9a, 0xd3, 0xf2, 0x5c, ++ 0xca, 0x41, 0xfb, 0xb6, 0xf0, 0x98, 0x29, 0xf7, 0x05, 0x9f, 0x62, 0x51, ++ 0x07, 0x6d, 0xc5, 0x6d, 0xe8, 0xed, 0x7f, 0xab, 0x94, 0xd3, 0x95, 0x9d, ++ 0x81, 0x29, 0xe8, 0xa1, 0xcd, 0x0a, 0xfd, 0xb0, 0xb2, 0xce, 0x94, 0x29, ++ 0xf8, 0x49, 0xdc, 0x6f, 0xfa, 0x73, 0xf1, 0xec, 0x02, 0xe7, 0xee, 0xed, ++ 0xb8, 0xd1, 0xf9, 0x4c, 0xee, 0xfc, 0xe7, 0xa9, 0x99, 0xeb, 0xea, 0x62, ++ 0x8f, 0x6e, 0xf7, 0x8e, 0x38, 0x2e, 0x39, 0x1a, 0x71, 0xe9, 0x90, 0x59, ++ 0x80, 0xa5, 0x6d, 0x62, 0xa7, 0x6e, 0xf7, 0xae, 0x38, 0xa6, 0x9d, 0xbc, ++ 0x76, 0xc1, 0x9c, 0x87, 0xa7, 0x34, 0x7b, 0xdd, 0x53, 0x62, 0x4b, 0x54, ++ 0x63, 0x5c, 0x2e, 0x0e, 0x7b, 0xdc, 0xc5, 0x93, 0xd0, 0x8a, 0xc8, 0x9d, ++ 0xdc, 0x61, 0xb4, 0x38, 0x12, 0xba, 0xaf, 0xd5, 0xd1, 0x80, 0x15, 0x69, ++ 0x1f, 0xf9, 0xf7, 0x9b, 0xe4, 0xab, 0xf6, 0xf3, 0x41, 0xda, 0xa4, 0x93, ++ 0x15, 0x06, 0xe7, 0xa8, 0x61, 0xc9, 0x09, 0xcb, 0x71, 0x9f, 0xb6, 0xe5, ++ 0x93, 0x6a, 0x78, 0x00, 0x77, 0x35, 0xba, 0x5b, 0x2a, 0x26, 0xf3, 0x3a, ++ 0x41, 0xb4, 0x34, 0x0c, 0xad, 0xdc, 0x80, 0x5a, 0x16, 0x16, 0xdd, 0xf8, ++ 0x5a, 0x12, 0x13, 0x22, 0xab, 0xe6, 0xee, 0x9f, 0x28, 0x2f, 0x42, 0x71, ++ 0x84, 0x98, 0xf6, 0x43, 0xef, 0x7f, 0xac, 0xde, 0x39, 0xb7, 0x60, 0xa4, ++ 0xcb, 0x90, 0xff, 0xb6, 0x6d, 0x31, 0x8f, 0x39, 0xbf, 0xd6, 0xed, 0xb7, ++ 0x2c, 0xc6, 0x57, 0x2f, 0x94, 0x79, 0x1c, 0x0f, 0x7d, 0x8d, 0xf1, 0xac, ++ 0x23, 0xf5, 0x7b, 0xeb, 0x53, 0x4e, 0x9b, 0x3b, 0x90, 0x6f, 0x45, 0xa3, ++ 0x6f, 0x1a, 0xbf, 0xb3, 0x84, 0xc7, 0x38, 0xe9, 0xd3, 0x05, 0xc6, 0x7c, ++ 0xec, 0x31, 0x9d, 0xad, 0xcb, 0x14, 0x05, 0xbd, 0x46, 0x9d, 0x56, 0xc4, ++ 0xf8, 0xb6, 0x9d, 0x7e, 0x1d, 0xf5, 0x18, 0x81, 0x43, 0x60, 0xb9, 0xd4, ++ 0xc6, 0x8d, 0xae, 0xf0, 0xfd, 0xf7, 0x1c, 0x6e, 0x14, 0x2c, 0xf0, 0xdd, ++ 0xf3, 0x8c, 0xd1, 0x4e, 0xde, 0xf6, 0x55, 0xf2, 0xbb, 0x6c, 0x3f, 0x19, ++ 0xcc, 0xff, 0x88, 0x7e, 0x36, 0x6e, 0x2c, 0x0c, 0x0b, 0x7f, 0x9b, 0x8e, ++ 0x1e, 0x31, 0x5a, 0x99, 0xbb, 0xdd, 0x7f, 0xcf, 0x85, 0xc6, 0x03, 0xfc, ++ 0x9f, 0xad, 0x33, 0x8a, 0x8a, 0x8f, 0xac, 0x53, 0x12, 0x96, 0x3e, 0xa2, ++ 0xd1, 0x67, 0x8c, 0xfb, 0xef, 0xe9, 0x5c, 0x72, 0x18, 0x3b, 0xd2, 0x5b, ++ 0xff, 0xdd, 0x7e, 0xca, 0xc2, 0xb2, 0x8e, 0x3a, 0x7a, 0xcf, 0xed, 0xfe, ++ 0xfb, 0xef, 0x49, 0x2d, 0x19, 0x60, 0x1f, 0x6b, 0x98, 0xab, 0x66, 0xeb, ++ 0x44, 0x14, 0xc7, 0x47, 0xea, 0xa0, 0x28, 0x7c, 0xfc, 0x9e, 0x85, 0xfe, ++ 0xdf, 0x59, 0x75, 0xfd, 0x05, 0xb6, 0x0e, 0x5c, 0xd4, 0xc1, 0x23, 0xa6, ++ 0x33, 0xe3, 0x77, 0xd8, 0x3a, 0xe8, 0xf2, 0x52, 0x07, 0x09, 0xea, 0x20, ++ 0x33, 0xdb, 0x08, 0xbd, 0x43, 0x1d, 0xd4, 0x4d, 0x6c, 0xdc, 0x58, 0x14, ++ 0x86, 0xd3, 0x61, 0xfc, 0xc8, 0xc1, 0x7c, 0x4a, 0x75, 0x19, 0x1b, 0xa9, ++ 0xb7, 0xfb, 0xef, 0x59, 0xb0, 0xc4, 0xd6, 0xf9, 0x1a, 0xb7, 0x7f, 0x1b, ++ 0xed, 0xa6, 0x85, 0xb6, 0xbe, 0x85, 0x47, 0x1b, 0x8f, 0x5e, 0x1e, 0x71, ++ 0xec, 0x49, 0x77, 0x50, 0x57, 0x2b, 0x39, 0x8e, 0xd5, 0x94, 0xab, 0x8b, ++ 0xbf, 0xa3, 0xfc, 0x1d, 0xe3, 0x6f, 0x99, 0x1f, 0xf5, 0x8a, 0x6c, 0xd1, ++ 0x2b, 0xb2, 0x39, 0x28, 0x4f, 0xa9, 0xbd, 0xc6, 0x59, 0x1c, 0xbe, 0xb4, ++ 0xe6, 0x76, 0x7f, 0x27, 0xdb, 0xf8, 0x66, 0x91, 0xec, 0x47, 0x70, 0x19, ++ 0x31, 0xaf, 0x13, 0x22, 0x9f, 0xde, 0xde, 0x89, 0x0c, 0xb1, 0xf7, 0xb7, ++ 0x59, 0xec, 0xa5, 0x6c, 0xe5, 0x9c, 0x9f, 0x33, 0x4b, 0x46, 0xaf, 0x29, ++ 0x35, 0xe0, 0x75, 0x1b, 0x7d, 0xe8, 0x4f, 0x0f, 0x53, 0x07, 0x62, 0x27, ++ 0x0f, 0x51, 0x7f, 0xdd, 0xac, 0x73, 0x8a, 0xb1, 0x4c, 0x8f, 0xd0, 0x67, ++ 0x69, 0xb3, 0x7a, 0x88, 0x07, 0xed, 0xe5, 0x45, 0xb6, 0x3b, 0x4a, 0x99, ++ 0x0a, 0x68, 0xbf, 0x0a, 0xe4, 0xd9, 0xef, 0x53, 0x6c, 0xff, 0x88, 0xf1, ++ 0xeb, 0x92, 0x53, 0x1c, 0x7b, 0xc4, 0xb3, 0x11, 0x63, 0x0d, 0xa2, 0xab, ++ 0x51, 0xea, 0x4a, 0xf7, 0xfa, 0x66, 0xe8, 0xf2, 0xaa, 0xbc, 0xd7, 0x92, ++ 0x87, 0x58, 0xd6, 0xeb, 0x46, 0xf3, 0x42, 0x26, 0x93, 0x18, 0xb5, 0x73, ++ 0x2c, 0xcb, 0x2a, 0xb0, 0xf7, 0xb5, 0x8d, 0xde, 0xb3, 0xde, 0x10, 0x79, ++ 0xeb, 0xdb, 0x76, 0xd0, 0x38, 0x37, 0xa6, 0xe8, 0xcf, 0xfe, 0xdf, 0x5a, ++ 0x91, 0xd9, 0x52, 0x6f, 0x3e, 0xce, 0x31, 0xf6, 0x46, 0xb4, 0x58, 0xa7, ++ 0x5b, 0xf2, 0x02, 0xc3, 0x19, 0x5a, 0x89, 0x58, 0xbb, 0x9b, 0x72, 0xdd, ++ 0x4b, 0xce, 0x7a, 0xc1, 0xc8, 0xfa, 0xf1, 0xd1, 0x94, 0x1e, 0x79, 0x8c, ++ 0xe7, 0xe4, 0xce, 0xe4, 0x60, 0xf9, 0x38, 0x15, 0x20, 0x5f, 0x2e, 0x85, ++ 0x93, 0xb9, 0x57, 0x8b, 0xa3, 0x27, 0xe0, 0x02, 0x7d, 0xb1, 0x58, 0xc6, ++ 0x15, 0xe3, 0x18, 0x05, 0xb7, 0xdd, 0x5a, 0x87, 0x8d, 0xe5, 0xb1, 0x85, ++ 0x2e, 0x94, 0x6a, 0x1b, 0x52, 0xf9, 0x18, 0x57, 0xaa, 0xad, 0x8b, 0x0b, ++ 0x2e, 0xc8, 0xf3, 0xda, 0x10, 0xf5, 0x2c, 0xf8, 0xf0, 0x3b, 0x7b, 0x0f, ++ 0x1c, 0x31, 0xa2, 0xdc, 0x69, 0x64, 0xdb, 0xd5, 0xd8, 0x6e, 0x9b, 0x43, ++ 0xc3, 0x55, 0x1f, 0xd7, 0xb5, 0x36, 0x87, 0xec, 0xcf, 0x23, 0x7a, 0xa5, ++ 0x72, 0xf5, 0xb2, 0x38, 0xd7, 0xe4, 0xb2, 0x71, 0x8e, 0x6d, 0x30, 0x5f, ++ 0x59, 0x1a, 0xff, 0x70, 0xff, 0xd2, 0x9f, 0xf4, 0xdb, 0x53, 0xa9, 0x42, ++ 0xf6, 0x07, 0xc9, 0xb3, 0xb4, 0x4e, 0xe6, 0x79, 0x33, 0xf7, 0x08, 0xe9, ++ 0x27, 0xd8, 0xfe, 0xf1, 0x18, 0xe7, 0x73, 0x9e, 0x21, 0xfb, 0x87, 0xe4, ++ 0xd9, 0xdb, 0xcc, 0xfd, 0x42, 0x22, 0xdb, 0xcd, 0xc5, 0xc2, 0x65, 0x8e, ++ 0x10, 0x27, 0x23, 0x6d, 0x52, 0xdf, 0xb2, 0xfe, 0xb9, 0x2e, 0x80, 0xcc, ++ 0x2c, 0x27, 0x86, 0x6b, 0x81, 0xa1, 0x84, 0xe8, 0x7a, 0x7a, 0xed, 0x7a, ++ 0xe3, 0x5f, 0xad, 0x48, 0x55, 0xbd, 0xb6, 0x5d, 0x95, 0x75, 0x90, 0xf3, ++ 0x6b, 0x7a, 0x8d, 0x1a, 0xad, 0x57, 0xcd, 0x1c, 0x63, 0x1c, 0x3a, 0x00, ++ 0xb4, 0x16, 0x0b, 0x56, 0x54, 0x1a, 0x91, 0xbe, 0x4a, 0xd4, 0xc2, 0x67, ++ 0x3f, 0xcb, 0xd0, 0x63, 0xdf, 0x50, 0x8d, 0xc0, 0x2a, 0xe1, 0xad, 0xea, ++ 0x7b, 0xd6, 0x28, 0x6d, 0xe0, 0xcb, 0xb5, 0xae, 0xe2, 0x2c, 0xb6, 0x47, ++ 0x3a, 0xe7, 0x70, 0x5e, 0xde, 0x5a, 0xa4, 0xfb, 0x52, 0x8a, 0xe8, 0x48, ++ 0xf8, 0xd6, 0x30, 0x76, 0x33, 0x1e, 0xff, 0x6b, 0x6d, 0x18, 0x47, 0xf9, ++ 0xff, 0x67, 0xb7, 0xc8, 0xde, 0x38, 0xcb, 0x0a, 0xf8, 0xeb, 0x42, 0x95, ++ 0x1c, 0xc3, 0xf3, 0xbc, 0xdf, 0x97, 0x7e, 0xd3, 0xba, 0x30, 0xc7, 0x18, ++ 0x58, 0xce, 0xa0, 0x38, 0x34, 0xa9, 0x6b, 0xd3, 0xea, 0x7f, 0x74, 0xaf, ++ 0x8e, 0xbd, 0x3e, 0xb9, 0xf6, 0x25, 0x7f, 0xbd, 0x96, 0x50, 0x1b, 0x8b, ++ 0x45, 0xaf, 0x43, 0x93, 0xaf, 0xe5, 0xe2, 0x7c, 0xf6, 0x19, 0xe9, 0x93, ++ 0x57, 0xf4, 0x23, 0xcf, 0x7b, 0xe7, 0xd3, 0xe6, 0x22, 0xa4, 0x91, 0x70, ++ 0xcf, 0xe2, 0x98, 0xbf, 0x5c, 0xfb, 0x15, 0x7b, 0x9c, 0x55, 0xc6, 0x5c, ++ 0x8e, 0x51, 0x81, 0x56, 0x5b, 0x5d, 0x9c, 0xe5, 0x84, 0xcd, 0x64, 0x69, ++ 0xa3, 0x56, 0x0b, 0x7d, 0xa8, 0x80, 0x75, 0x6e, 0x33, 0x0f, 0x5e, 0xd3, ++ 0xd3, 0xa0, 0x7b, 0xbf, 0x4c, 0x5b, 0x0d, 0xd6, 0xfe, 0xca, 0x8a, 0x68, ++ 0x4e, 0xf3, 0x71, 0x8e, 0xfa, 0xde, 0xb8, 0x94, 0x95, 0x79, 0x35, 0x22, ++ 0xb5, 0xca, 0xdb, 0x16, 0x66, 0xfb, 0x43, 0xb5, 0xf6, 0xf8, 0x81, 0x4d, ++ 0xa9, 0x61, 0xe6, 0xd8, 0xd2, 0xa6, 0x82, 0xe5, 0xfe, 0x9f, 0x58, 0xbe, ++ 0x39, 0xc3, 0xd8, 0x95, 0xfe, 0x63, 0xdc, 0xf7, 0xab, 0xe4, 0xde, 0x7a, ++ 0x7b, 0x2c, 0xeb, 0x77, 0xad, 0x60, 0xbf, 0xc5, 0x86, 0x9d, 0xbf, 0x47, ++ 0xe3, 0x7e, 0x59, 0x6b, 0x3a, 0xbf, 0x76, 0xc2, 0x2f, 0x7b, 0x3a, 0x3c, ++ 0xc8, 0xb4, 0x49, 0x99, 0x1a, 0x6d, 0x02, 0x19, 0x32, 0x4c, 0xd9, 0x7f, ++ 0xf2, 0x9d, 0xe2, 0xec, 0xfa, 0x83, 0x43, 0xd6, 0xcf, 0xb5, 0xf3, 0xe4, ++ 0x84, 0xad, 0x86, 0xb4, 0xa1, 0x60, 0xa1, 0x7f, 0x16, 0xea, 0x57, 0xfd, ++ 0xe8, 0xc7, 0x05, 0xfe, 0xac, 0xdf, 0xf6, 0x1a, 0xc6, 0xd6, 0xd3, 0xf8, ++ 0x35, 0xb1, 0x4a, 0xf6, 0xa7, 0x9c, 0x90, 0x7a, 0x6c, 0xab, 0x16, 0x29, ++ 0xf2, 0xee, 0x31, 0x43, 0xf6, 0x57, 0x5a, 0xd6, 0xed, 0xfe, 0x37, 0xe8, ++ 0x77, 0x94, 0x27, 0xed, 0xcc, 0xd5, 0x95, 0x32, 0xb9, 0xbd, 0x1f, 0x4a, ++ 0xf3, 0x3d, 0xa2, 0x93, 0xa7, 0xcd, 0x18, 0xb3, 0x0d, 0x89, 0x0f, 0xe7, ++ 0xd7, 0xbe, 0x69, 0x08, 0xf7, 0xd7, 0xcd, 0xe5, 0x4a, 0x05, 0xe3, 0xad, ++ 0xd3, 0x77, 0xd8, 0x5e, 0x07, 0x89, 0x12, 0xcb, 0x85, 0x87, 0x4a, 0x4e, ++ 0xe9, 0xc4, 0x33, 0x46, 0x25, 0x9e, 0xd6, 0xb2, 0x9c, 0x8e, 0x98, 0x88, ++ 0x97, 0xe3, 0x75, 0x19, 0x7a, 0x08, 0xb9, 0xb1, 0xd1, 0x79, 0x59, 0xf9, ++ 0x35, 0xf3, 0x4d, 0xe0, 0x4c, 0xaa, 0x0b, 0x8f, 0xc8, 0xf3, 0x2f, 0xa5, ++ 0xa6, 0xb5, 0xde, 0x21, 0xfd, 0x75, 0x61, 0xb7, 0xbd, 0x9e, 0x7b, 0x7e, ++ 0xed, 0x11, 0xe3, 0x54, 0x4e, 0x56, 0xc1, 0xfc, 0xf3, 0x6b, 0x9f, 0x31, ++ 0xfe, 0x8f, 0x3d, 0x77, 0xb2, 0xd7, 0xa1, 0xcf, 0x14, 0x6c, 0x2c, 0x86, ++ 0xca, 0xbc, 0xc4, 0x61, 0xac, 0x81, 0xa3, 0xf2, 0x30, 0x6d, 0x4f, 0xd6, ++ 0x89, 0xd6, 0xc2, 0x59, 0xe9, 0xa2, 0x6f, 0x6e, 0x82, 0xab, 0x52, 0x38, ++ 0x7d, 0x9e, 0x6f, 0xb7, 0xf2, 0xbe, 0xe8, 0xd6, 0x77, 0x8f, 0xe8, 0xd6, ++ 0x49, 0xec, 0xe9, 0x95, 0xbc, 0xd1, 0xa8, 0xa0, 0x8e, 0xf4, 0x76, 0x59, ++ 0x0f, 0x2f, 0x23, 0xb6, 0x32, 0x8e, 0xba, 0x2b, 0x58, 0xe6, 0x1d, 0xea, ++ 0xbd, 0xae, 0xbf, 0x84, 0x5c, 0xdf, 0xb2, 0xde, 0x23, 0xd7, 0x5f, 0xe8, ++ 0xaf, 0xcf, 0x18, 0x8c, 0x7f, 0xf8, 0x8c, 0xde, 0x2a, 0xcf, 0x96, 0xd7, ++ 0x1b, 0x97, 0xad, 0xe8, 0x6a, 0x29, 0xa3, 0x7b, 0xa3, 0x4a, 0xbe, 0x8f, ++ 0x45, 0xf0, 0xcd, 0xb2, 0xe0, 0x0a, 0x5b, 0xc4, 0x2e, 0xdd, 0x8c, 0xa0, ++ 0x59, 0xf6, 0x08, 0xb5, 0xc9, 0xf8, 0x5d, 0xf2, 0x9c, 0x02, 0x91, 0x29, ++ 0x17, 0x8c, 0xcc, 0x51, 0x99, 0xb3, 0x6b, 0x2c, 0xf8, 0x17, 0xff, 0x96, ++ 0xb9, 0x96, 0xcc, 0x4f, 0x4d, 0xa6, 0x41, 0xc9, 0x04, 0xbc, 0xe4, 0xfe, ++ 0x5f, 0x83, 0xde, 0x16, 0xa7, 0xae, 0x5b, 0x82, 0x36, 0xe6, 0x79, 0xe3, ++ 0xb0, 0xf9, 0xbe, 0x79, 0x0e, 0x9f, 0x42, 0x19, 0x73, 0xe3, 0xda, 0x89, ++ 0x95, 0x28, 0xaf, 0x8c, 0x78, 0x8b, 0x71, 0x23, 0xcf, 0xb7, 0x30, 0x8f, ++ 0xf9, 0x2c, 0xca, 0x57, 0x45, 0x11, 0x4f, 0x4a, 0x0e, 0xf5, 0x79, 0x5e, ++ 0xeb, 0x45, 0x22, 0xe9, 0xe2, 0x38, 0x7e, 0x68, 0x95, 0xcf, 0x16, 0xd9, ++ 0x4c, 0x4f, 0x89, 0xc1, 0x7c, 0xdd, 0xd6, 0x05, 0xb1, 0x3c, 0x29, 0x5c, ++ 0xaa, 0x3e, 0xb2, 0x19, 0xbf, 0xa7, 0xed, 0xea, 0xed, 0x1d, 0x4a, 0x8c, ++ 0x36, 0x1b, 0xa7, 0xce, 0xa5, 0xac, 0x65, 0xad, 0xf0, 0x57, 0x95, 0xa0, ++ 0x38, 0xc6, 0x73, 0xc3, 0xf7, 0x06, 0xd4, 0x1b, 0x0b, 0x71, 0xd6, 0x8a, ++ 0x69, 0x5e, 0xda, 0xa5, 0xba, 0x5a, 0x78, 0xd7, 0xb2, 0xe0, 0xb5, 0xbc, ++ 0xaf, 0xe5, 0xec, 0x74, 0x3a, 0x9a, 0xd5, 0xa5, 0x8f, 0xba, 0x54, 0xec, ++ 0xeb, 0x0e, 0xfb, 0x7a, 0x34, 0x77, 0x7d, 0x3a, 0xda, 0x6b, 0x80, 0xd7, ++ 0x07, 0xa8, 0x7b, 0xf5, 0x5a, 0xa9, 0xbf, 0xd1, 0x94, 0xfa, 0xa4, 0x23, ++ 0x46, 0x3c, 0x37, 0x1f, 0xa3, 0xb9, 0xf9, 0x38, 0x9e, 0x6b, 0xc3, 0xc9, ++ 0x36, 0x62, 0x91, 0x62, 0x98, 0x28, 0xf1, 0x0b, 0xce, 0x8b, 0x5c, 0x9c, ++ 0xbb, 0xb4, 0xc8, 0xb5, 0x85, 0x71, 0xb1, 0xe7, 0xb9, 0x62, 0xc4, 0xba, ++ 0xe6, 0xda, 0x76, 0x38, 0x4d, 0x9e, 0xa2, 0xfb, 0xde, 0x54, 0x9a, 0xbd, ++ 0xb2, 0x1c, 0x94, 0x24, 0xe7, 0x7d, 0xd0, 0x74, 0x86, 0x1a, 0x1c, 0x75, ++ 0x99, 0x42, 0x18, 0xd1, 0xcb, 0xca, 0x0d, 0x25, 0x82, 0x0f, 0xf1, 0x54, ++ 0x33, 0x33, 0xb4, 0x58, 0x80, 0xb9, 0x55, 0x20, 0x4d, 0xdd, 0xae, 0x23, ++ 0x62, 0x9f, 0xb0, 0xf7, 0x3a, 0x39, 0xa7, 0x56, 0xa2, 0x59, 0x77, 0xa0, ++ 0x2e, 0x34, 0x97, 0x19, 0x1a, 0xed, 0xd2, 0x2c, 0x74, 0xe8, 0xbe, 0xbb, ++ 0xf0, 0x65, 0xbb, 0xde, 0xd1, 0x54, 0xa6, 0xb3, 0x98, 0x73, 0xfa, 0x75, ++ 0xca, 0xb1, 0xc7, 0x2f, 0x72, 0x1c, 0xce, 0xc9, 0x11, 0x65, 0xcc, 0x35, ++ 0xb5, 0x3b, 0xfc, 0x03, 0x57, 0xf4, 0xf6, 0x9c, 0xad, 0xb7, 0x5e, 0x9e, ++ 0x17, 0x62, 0x27, 0xf9, 0xe3, 0xa9, 0x06, 0x4f, 0xee, 0x99, 0x80, 0xe4, ++ 0x74, 0x82, 0xbf, 0xe7, 0xef, 0x5e, 0x6f, 0xe8, 0x21, 0x87, 0xcd, 0xff, ++ 0xdd, 0x88, 0xd9, 0xdc, 0xda, 0x01, 0xe1, 0x8e, 0x8f, 0xd9, 0xe5, 0x5c, ++ 0xd4, 0x49, 0x09, 0xbe, 0x96, 0xf3, 0x97, 0x12, 0xc6, 0xb7, 0xaf, 0xdb, ++ 0xbf, 0x47, 0x39, 0xb7, 0x2e, 0xfa, 0x6a, 0x3e, 0x46, 0xc9, 0xba, 0xe2, ++ 0xa8, 0xed, 0xfb, 0xa3, 0x78, 0xdb, 0xfe, 0x9f, 0xc9, 0xe6, 0x65, 0xe8, ++ 0xa5, 0x4f, 0x38, 0xd8, 0xc6, 0x76, 0x7b, 0x0f, 0xab, 0xac, 0x31, 0xdc, ++ 0x82, 0x9d, 0x1c, 0x95, 0xdb, 0xe8, 0x44, 0x9f, 0x26, 0x36, 0xd1, 0x8d, ++ 0x84, 0x66, 0x7a, 0xd2, 0x0d, 0x33, 0x73, 0x2a, 0x13, 0x87, 0x1a, 0x7e, ++ 0xc7, 0x58, 0x2e, 0xd7, 0xce, 0x5a, 0xf4, 0xb9, 0x20, 0x3d, 0xb8, 0xb3, ++ 0xc0, 0xd6, 0xaf, 0xef, 0x1e, 0x7b, 0xbf, 0x17, 0x65, 0x7e, 0x2e, 0x2e, ++ 0x71, 0x74, 0x3e, 0x52, 0xa6, 0xc8, 0xe6, 0x6c, 0xdb, 0xcb, 0x39, 0xe9, ++ 0x4d, 0xfa, 0x23, 0xd7, 0xf1, 0xde, 0x14, 0x63, 0xd9, 0x76, 0xea, 0x33, ++ 0xda, 0x26, 0x3c, 0x6e, 0x0b, 0x0e, 0xd0, 0xc6, 0x26, 0x4d, 0xcb, 0x3a, ++ 0x4a, 0x8c, 0xa8, 0xa8, 0x53, 0x91, 0x99, 0xbd, 0x05, 0x49, 0xc6, 0xa6, ++ 0xa3, 0x46, 0xf3, 0xa7, 0x0a, 0x10, 0xf3, 0x31, 0x86, 0x7b, 0x77, 0x71, ++ 0x34, 0x0f, 0x72, 0xbe, 0x4e, 0x99, 0xc2, 0x2f, 0x9d, 0x97, 0x97, 0xc1, ++ 0x08, 0x35, 0x39, 0x7e, 0x68, 0x4d, 0x8b, 0xec, 0xc9, 0x9e, 0x7f, 0xa4, ++ 0x0c, 0x5b, 0xc5, 0x79, 0x2b, 0x38, 0xc7, 0xef, 0xf8, 0xf5, 0xd6, 0x97, ++ 0xd9, 0x4f, 0x7d, 0x7f, 0x73, 0xa7, 0xc8, 0x70, 0x24, 0xe8, 0x8c, 0x1e, ++ 0x85, 0xbf, 0x6d, 0x8b, 0x92, 0xcf, 0x21, 0x80, 0xeb, 0x26, 0x4c, 0x8c, ++ 0x37, 0x3c, 0x4f, 0xbe, 0x23, 0xf5, 0x0b, 0xf1, 0x6d, 0xf3, 0x59, 0xab, ++ 0xe6, 0x9a, 0x97, 0xac, 0x63, 0x86, 0xba, 0x99, 0xda, 0x8e, 0x96, 0x41, ++ 0xd6, 0x42, 0xa7, 0xa3, 0xf7, 0xf9, 0x75, 0x73, 0x2f, 0xdb, 0x7a, 0x2a, ++ 0x7e, 0x2a, 0xe0, 0x66, 0x5b, 0x5f, 0x33, 0x25, 0x87, 0x70, 0xb6, 0xb6, ++ 0x72, 0x6e, 0x7b, 0x92, 0x7e, 0xaf, 0xac, 0xf7, 0x4a, 0x9e, 0xb7, 0x36, ++ 0x2e, 0x7b, 0xd1, 0x0f, 0x73, 0x3c, 0x91, 0xad, 0x2e, 0x34, 0x3f, 0x58, ++ 0x4e, 0xfb, 0xa9, 0x40, 0xde, 0xd6, 0x75, 0x2f, 0xf1, 0x0e, 0xf7, 0xb1, ++ 0xcc, 0x8f, 0xfd, 0xf3, 0x71, 0x26, 0xd8, 0xbc, 0x6a, 0x3e, 0x9c, 0xd1, ++ 0x63, 0x8a, 0xbf, 0x75, 0x8b, 0x12, 0xd3, 0xc4, 0x16, 0xef, 0x4d, 0xe9, ++ 0x81, 0x16, 0x08, 0x76, 0x47, 0xa9, 0x8f, 0xf9, 0x78, 0x6f, 0xb1, 0xc8, ++ 0xe5, 0x0c, 0x05, 0x1c, 0xfe, 0xae, 0x67, 0x65, 0x9b, 0x65, 0x9d, 0xc8, ++ 0x0e, 0xa4, 0xed, 0xfd, 0xe4, 0x51, 0x24, 0xd2, 0x67, 0xdf, 0x39, 0x62, ++ 0xc0, 0x79, 0xa2, 0xe1, 0x11, 0x0b, 0xb3, 0xa4, 0x6c, 0xb3, 0xcc, 0x43, ++ 0xbb, 0xcc, 0x43, 0x31, 0xfd, 0xe9, 0x76, 0xca, 0xbd, 0xd9, 0x96, 0x7b, ++ 0x3e, 0xc6, 0x4c, 0x59, 0x5f, 0x73, 0x6a, 0xf7, 0x62, 0x80, 0xd8, 0xe9, ++ 0xbf, 0xdc, 0xc3, 0x7e, 0x7e, 0x4c, 0x99, 0xeb, 0xa8, 0xf7, 0xe9, 0x36, ++ 0xe1, 0xb7, 0xbd, 0xe8, 0xb7, 0xf7, 0x29, 0x4b, 0x1f, 0x0a, 0x52, 0x7e, ++ 0xe9, 0xa3, 0x97, 0x7c, 0xaf, 0xc7, 0x9a, 0x9e, 0x2d, 0xd7, 0x47, 0xb1, ++ 0x33, 0x19, 0xd1, 0xe8, 0x0f, 0xd4, 0x3b, 0xf4, 0xf9, 0xd0, 0xa7, 0xce, ++ 0x3b, 0x22, 0xf4, 0x01, 0xd3, 0x73, 0x99, 0xd8, 0x70, 0x02, 0x5d, 0x16, ++ 0x2a, 0x6d, 0x7b, 0xf8, 0xd9, 0x61, 0xa3, 0x4c, 0xd6, 0xe8, 0x03, 0x19, ++ 0xea, 0x40, 0xe5, 0x9c, 0x88, 0x0e, 0xca, 0xe8, 0xb3, 0x13, 0x7e, 0xdd, ++ 0x77, 0x86, 0xf2, 0xec, 0xa5, 0x3c, 0x2b, 0xb3, 0x73, 0xe8, 0xdd, 0xa9, ++ 0x88, 0x4f, 0xfb, 0xdb, 0xd6, 0xf3, 0xfa, 0x1e, 0xca, 0xe3, 0xef, 0x57, ++ 0x30, 0x4a, 0x34, 0xeb, 0x25, 0x9f, 0x3d, 0x30, 0x43, 0x1e, 0xb7, 0x3d, ++ 0x67, 0x31, 0x72, 0x81, 0x42, 0x1c, 0x31, 0x05, 0xbf, 0x35, 0x8c, 0xd1, ++ 0x4e, 0x0f, 0x71, 0x46, 0x22, 0x1e, 0x15, 0x85, 0x86, 0x60, 0xc0, 0x6c, ++ 0x5e, 0x73, 0x71, 0x6e, 0x2a, 0x70, 0x4c, 0x1b, 0x65, 0x9c, 0xcc, 0x73, ++ 0xbb, 0xdf, 0x5b, 0xe3, 0x1e, 0xe1, 0x67, 0xb2, 0xfe, 0x26, 0xcf, 0x3b, ++ 0x1e, 0x2f, 0xc9, 0xee, 0xcb, 0x94, 0x7d, 0x13, 0xd9, 0xeb, 0xcf, 0x69, ++ 0xc2, 0x91, 0xf3, 0xe5, 0xff, 0xc5, 0x7a, 0xda, 0x2e, 0x2f, 0xe5, 0x5c, ++ 0x36, 0x97, 0x2f, 0xb6, 0xcb, 0xfd, 0x8b, 0xf5, 0xbc, 0xe6, 0x9c, 0x51, ++ 0x2e, 0xbf, 0x77, 0xef, 0xd4, 0x57, 0x5c, 0xc4, 0x3c, 0x47, 0x6d, 0x13, ++ 0x9e, 0x36, 0xce, 0xd6, 0xac, 0x6b, 0xe8, 0x66, 0x1c, 0xcb, 0x73, 0xad, ++ 0x6a, 0xfa, 0x95, 0x85, 0x41, 0xf3, 0xd4, 0x60, 0x01, 0x7a, 0xc8, 0x1d, ++ 0x85, 0x0b, 0x08, 0x47, 0x95, 0xf5, 0xc1, 0xbf, 0x2c, 0xbe, 0x9a, 0xf3, ++ 0xea, 0x01, 0x9f, 0x1a, 0xb5, 0xb9, 0x61, 0x44, 0x15, 0xdc, 0xad, 0xb6, ++ 0xc7, 0x7e, 0x35, 0xfe, 0x4b, 0xac, 0x98, 0xb9, 0xde, 0xd7, 0x8d, 0x43, ++ 0x46, 0x9e, 0xb3, 0x9c, 0x7a, 0x44, 0x25, 0x4e, 0x0e, 0x99, 0x4d, 0x12, ++ 0x9b, 0x7d, 0xac, 0x1f, 0x88, 0xaa, 0x33, 0xb9, 0xcd, 0xc3, 0x25, 0x28, ++ 0xef, 0xd9, 0xed, 0x80, 0xec, 0x1b, 0x96, 0xbd, 0xde, 0xd2, 0x57, 0x51, ++ 0x6e, 0xfd, 0xea, 0xa3, 0xb8, 0x46, 0xbe, 0x2f, 0xe1, 0x1b, 0x35, 0x79, ++ 0x19, 0x03, 0x11, 0x5b, 0xce, 0x5f, 0x5a, 0xab, 0xb4, 0xcc, 0x5c, 0x0d, ++ 0x1f, 0x94, 0x3d, 0x92, 0x93, 0x3d, 0xfa, 0x91, 0xeb, 0x76, 0xd2, 0xcf, ++ 0xcc, 0x36, 0xf3, 0x7b, 0x56, 0x65, 0x4d, 0x57, 0xee, 0x29, 0xe8, 0x21, ++ 0x0e, 0x45, 0xb4, 0x66, 0xc6, 0x79, 0xdd, 0xbb, 0x81, 0xf3, 0x11, 0xf3, ++ 0xc8, 0x7e, 0xd8, 0x7c, 0x8c, 0x2c, 0x44, 0x76, 0x6d, 0x15, 0x38, 0x94, ++ 0x5b, 0x4f, 0xa5, 0xdd, 0xa3, 0x27, 0xf5, 0x5b, 0x2b, 0xe3, 0x71, 0x32, ++ 0x16, 0x5e, 0xdd, 0xb7, 0x3f, 0x4a, 0xbd, 0x8e, 0xf1, 0xde, 0xce, 0x2b, ++ 0xeb, 0x2e, 0xb2, 0xf6, 0x24, 0xb1, 0xf7, 0x37, 0xd6, 0xba, 0x0f, 0x94, ++ 0x9d, 0xb9, 0x67, 0x76, 0x76, 0x54, 0xf6, 0xb1, 0x8d, 0xe7, 0xd6, 0xf5, ++ 0x5b, 0xfe, 0x70, 0x1f, 0x1b, 0x6d, 0x09, 0x91, 0x9d, 0xe4, 0x76, 0x31, ++ 0xf4, 0x62, 0x3c, 0x5e, 0xaf, 0xed, 0x82, 0x26, 0xeb, 0xd9, 0xfc, 0xeb, ++ 0xc5, 0xb1, 0x38, 0x22, 0x05, 0xd7, 0x57, 0x90, 0x6f, 0x21, 0xe2, 0x90, ++ 0xbd, 0x45, 0xf1, 0xfa, 0xd6, 0x3d, 0x1c, 0x93, 0x6f, 0x55, 0x2f, 0xc6, ++ 0xe2, 0xcd, 0x9f, 0x67, 0x1c, 0xf1, 0x95, 0x64, 0xb9, 0xce, 0xe7, 0x8f, ++ 0x10, 0x07, 0x76, 0xe4, 0xd6, 0xc6, 0xd6, 0xc5, 0x7f, 0x45, 0xf9, 0x6d, ++ 0x21, 0x59, 0xef, 0x8f, 0x95, 0x3b, 0x8b, 0xed, 0xc9, 0xb3, 0xd8, 0x38, ++ 0xa0, 0x88, 0x7d, 0x61, 0xc3, 0xa8, 0xc8, 0x73, 0x16, 0x1d, 0x03, 0xdf, ++ 0xc7, 0xa1, 0x81, 0x6b, 0xd0, 0x62, 0xeb, 0xa6, 0x0b, 0x5b, 0xf6, 0x9d, ++ 0xc4, 0xde, 0xa4, 0x85, 0x3d, 0xc1, 0x52, 0x6c, 0x3e, 0xa8, 0x60, 0x85, ++ 0xff, 0x29, 0xec, 0xda, 0x67, 0x61, 0x41, 0xb0, 0x1b, 0xad, 0x66, 0x09, ++ 0x0a, 0x2b, 0xeb, 0x3a, 0x55, 0x96, 0x5b, 0x37, 0xd6, 0xa5, 0xdc, 0xc9, ++ 0x71, 0x67, 0x5c, 0xc7, 0x89, 0x05, 0x2a, 0xbc, 0x86, 0xac, 0x97, 0x46, ++ 0x94, 0xbb, 0xd3, 0x2d, 0x4a, 0xfb, 0x98, 0xcd, 0xa7, 0x94, 0xbb, 0xd2, ++ 0x66, 0x99, 0xc4, 0xf4, 0x43, 0xc1, 0xb3, 0x18, 0x1d, 0xad, 0x2d, 0xcb, ++ 0xfa, 0x4b, 0x7e, 0x9d, 0xf9, 0x04, 0x86, 0x92, 0x33, 0xd7, 0x98, 0xc5, ++ 0xd6, 0x9e, 0xc0, 0x3e, 0x72, 0xf1, 0xbb, 0x13, 0x31, 0xe6, 0x3a, 0xef, ++ 0x58, 0xe5, 0x61, 0x62, 0xf5, 0xa4, 0x81, 0xf6, 0x44, 0x31, 0xa2, 0x87, ++ 0x2c, 0xeb, 0xcc, 0x12, 0x27, 0xba, 0x26, 0x1b, 0xb0, 0x6a, 0xe8, 0x51, ++ 0xab, 0x24, 0x6c, 0x59, 0x9b, 0x97, 0x94, 0xe2, 0x81, 0x43, 0xa5, 0xf8, ++ 0x52, 0x22, 0x02, 0x77, 0xb8, 0x84, 0xbf, 0xfd, 0xd1, 0x4b, 0x8a, 0xd1, ++ 0xda, 0xaf, 0x18, 0xa1, 0xeb, 0x14, 0xbf, 0x79, 0x11, 0xa5, 0xd8, 0x38, ++ 0xe9, 0xc4, 0x6d, 0x09, 0x2f, 0xa2, 0x93, 0x16, 0xf3, 0x32, 0x0f, 0x36, ++ 0xb0, 0xfe, 0xd2, 0x84, 0x65, 0xf5, 0x34, 0xba, 0x11, 0x3d, 0x6a, 0x5c, ++ 0x5e, 0xc7, 0x39, 0xe8, 0x9e, 0x74, 0xb3, 0xcf, 0xe3, 0x18, 0x48, 0x56, ++ 0xe1, 0xce, 0x11, 0x1f, 0xfb, 0x2c, 0xc5, 0xaa, 0x84, 0xd5, 0xf4, 0x5a, ++ 0x30, 0xf6, 0xa0, 0x17, 0x06, 0x1e, 0x98, 0xf4, 0xe0, 0xd3, 0x09, 0x9d, ++ 0x6d, 0x2b, 0x78, 0x21, 0x18, 0xc0, 0x17, 0x27, 0xbd, 0xb8, 0x3d, 0x71, ++ 0xea, 0x53, 0xa5, 0x88, 0xdd, 0x51, 0x82, 0x06, 0x6c, 0x9e, 0xac, 0xc6, ++ 0xb2, 0x84, 0xac, 0xb1, 0x55, 0x63, 0xd3, 0x51, 0x93, 0x7d, 0xaa, 0xb8, ++ 0x8d, 0xed, 0xb4, 0x24, 0xe6, 0x61, 0xc3, 0xd1, 0x46, 0x74, 0x4c, 0x2e, ++ 0xc6, 0xd2, 0x21, 0x27, 0xe3, 0xbf, 0x0b, 0x11, 0x72, 0xb7, 0x65, 0x43, ++ 0x32, 0x17, 0x0f, 0xa1, 0x3b, 0x6e, 0xb2, 0x6f, 0x39, 0x3f, 0x29, 0xb6, ++ 0x81, 0xa3, 0xa3, 0x8b, 0xd1, 0x32, 0xa4, 0xd2, 0x8e, 0x0b, 0x99, 0x4f, ++ 0x29, 0xb8, 0x93, 0xd7, 0x77, 0x25, 0x65, 0x8f, 0x07, 0xf0, 0x93, 0x81, ++ 0x6c, 0xcc, 0xbb, 0x38, 0x9a, 0xbd, 0xde, 0x9f, 0x7c, 0x92, 0xb9, 0xe7, ++ 0x8f, 0x2d, 0xc1, 0x95, 0xc9, 0x83, 0x27, 0xc9, 0xa5, 0xca, 0xb0, 0x72, ++ 0xb0, 0x1b, 0x7b, 0x83, 0x65, 0xb8, 0x83, 0xe7, 0x3b, 0x79, 0x3e, 0x35, ++ 0x60, 0x50, 0xa6, 0x32, 0x3c, 0x3b, 0x7a, 0x12, 0x83, 0xf4, 0xa3, 0x0d, ++ 0x89, 0x32, 0xd4, 0x0c, 0x29, 0x8c, 0xbb, 0x91, 0xf7, 0x54, 0x18, 0x53, ++ 0x1d, 0xf0, 0x67, 0x9a, 0x1c, 0x65, 0x08, 0x1d, 0x3a, 0x89, 0x3e, 0x8e, ++ 0xbd, 0x6d, 0xe4, 0x2c, 0xfb, 0x53, 0xa1, 0x1d, 0x11, 0x9d, 0x9d, 0xc4, ++ 0xcf, 0x07, 0x1c, 0x48, 0x9b, 0x35, 0xc4, 0x5e, 0x07, 0x5e, 0x0c, 0xea, ++ 0x5a, 0x8a, 0x5c, 0xf5, 0xeb, 0xcc, 0x56, 0xa2, 0xb3, 0x1b, 0xd1, 0x62, ++ 0x98, 0x3c, 0x4e, 0xe2, 0x5f, 0x06, 0x8c, 0xd8, 0xdf, 0xcb, 0x5e, 0x87, ++ 0x45, 0x2a, 0xa6, 0x99, 0x3f, 0x6f, 0x37, 0xc4, 0xbe, 0x53, 0xc2, 0xbb, ++ 0x64, 0x0d, 0x19, 0x8e, 0x09, 0xc6, 0xc8, 0x83, 0x4d, 0x68, 0x1d, 0x4a, ++ 0xb1, 0x6d, 0x85, 0xf2, 0xa7, 0x28, 0x4b, 0x13, 0xc7, 0xec, 0xa4, 0x7e, ++ 0x54, 0xd4, 0x1e, 0x0d, 0x63, 0xc3, 0xfe, 0xdf, 0xd3, 0xef, 0x2d, 0xeb, ++ 0xb8, 0x19, 0x9b, 0xa5, 0xc2, 0xef, 0x23, 0x71, 0x6d, 0x76, 0x84, 0xfd, ++ 0x97, 0xb7, 0xb3, 0xdd, 0xa6, 0xc9, 0x14, 0x75, 0x13, 0xe2, 0xfc, 0x78, ++ 0xf1, 0xed, 0x54, 0x23, 0x6d, 0xa1, 0x1a, 0x27, 0x52, 0xa5, 0x18, 0x25, ++ 0x31, 0x19, 0x4d, 0x79, 0x30, 0x7a, 0x78, 0x0e, 0x0f, 0x1f, 0x8f, 0x05, ++ 0x3c, 0x0c, 0xfb, 0xda, 0xba, 0x84, 0x62, 0xeb, 0x4f, 0xd6, 0xf2, 0x3e, ++ 0x2a, 0x07, 0x3a, 0x94, 0xfa, 0x78, 0x99, 0x3c, 0x5f, 0xfe, 0x6e, 0xdd, ++ 0x59, 0xea, 0x49, 0xf6, 0x97, 0x36, 0xd0, 0x0e, 0xff, 0xad, 0xf7, 0x62, ++ 0xc4, 0x36, 0xa7, 0x71, 0x7a, 0xf8, 0x1c, 0x4e, 0x0d, 0x7f, 0x0a, 0x4b, ++ 0x35, 0x59, 0xef, 0x28, 0xc7, 0x9c, 0xf0, 0x59, 0x3c, 0x35, 0xf0, 0x3d, ++ 0xea, 0x58, 0x30, 0x93, 0xb6, 0x15, 0xac, 0x0f, 0xb5, 0xa8, 0x2d, 0x98, ++ 0x66, 0xde, 0xb3, 0xa2, 0xf6, 0x26, 0xec, 0xd6, 0x8e, 0x33, 0xf6, 0x88, ++ 0x1f, 0xae, 0xc1, 0x91, 0x78, 0xcc, 0xf2, 0x18, 0x7a, 0xf4, 0x04, 0xf3, ++ 0x8f, 0x61, 0xa5, 0x01, 0x9f, 0x4e, 0x9f, 0xc3, 0xf3, 0xc3, 0x32, 0x57, ++ 0x7a, 0xeb, 0x5f, 0x2b, 0x56, 0x77, 0x4b, 0x50, 0x8f, 0xdc, 0xa8, 0x30, ++ 0xd3, 0x83, 0x7e, 0x8c, 0x89, 0x14, 0xc6, 0x47, 0x64, 0x1f, 0x41, 0x3b, ++ 0x2c, 0xe6, 0xf1, 0xbf, 0x36, 0x63, 0x73, 0x67, 0x33, 0x4e, 0xbe, 0xee, ++ 0xd0, 0xfb, 0xe6, 0x3a, 0xba, 0xb1, 0x78, 0x91, 0xde, 0xf5, 0xd7, 0xaa, ++ 0x11, 0x6b, 0x54, 0x1b, 0xd0, 0x96, 0xd6, 0x0f, 0xbc, 0xcb, 0xf9, 0xbd, ++ 0x9f, 0xba, 0x7c, 0x3a, 0xd8, 0x9a, 0xdb, 0x87, 0x71, 0xce, 0x96, 0x55, ++ 0x8e, 0xd7, 0x86, 0x11, 0x63, 0xce, 0xd2, 0xdd, 0xcd, 0x38, 0xf9, 0x5e, ++ 0x9d, 0xd5, 0x1d, 0x5c, 0x6c, 0xc4, 0x9c, 0xe4, 0x01, 0x95, 0xea, 0x39, ++ 0xbc, 0x7c, 0xf8, 0x1c, 0x5e, 0x1a, 0x86, 0xbb, 0x2a, 0x1c, 0xc5, 0x9f, ++ 0x27, 0xac, 0xee, 0x57, 0x82, 0x3f, 0xc6, 0x90, 0x9d, 0x7b, 0x7b, 0xf1, ++ 0x97, 0x09, 0x59, 0x83, 0xb1, 0xac, 0x65, 0xb5, 0x0d, 0xb4, 0x65, 0xd1, ++ 0xd1, 0x34, 0xa6, 0xd8, 0xde, 0x73, 0xc3, 0xa7, 0xac, 0x80, 0xbd, 0xde, ++ 0x4c, 0x7d, 0xfd, 0xd1, 0x9c, 0x59, 0x67, 0xe4, 0xcc, 0xef, 0x67, 0xfd, ++ 0x3e, 0xce, 0x10, 0x73, 0x6e, 0xaf, 0xb5, 0x90, 0x0a, 0xea, 0xed, 0x71, ++ 0x5c, 0xb2, 0x36, 0x57, 0xfe, 0xff, 0xad, 0x9b, 0xef, 0x30, 0xdf, 0x11, ++ 0xb9, 0x35, 0x6c, 0x4c, 0x64, 0x32, 0x55, 0xe4, 0xf8, 0xf7, 0x27, 0x22, ++ 0x83, 0x55, 0xd0, 0xbb, 0xda, 0x55, 0xbd, 0xfd, 0x4b, 0x8e, 0x9a, 0xce, ++ 0x97, 0xd0, 0x87, 0x2d, 0x7e, 0xd5, 0x7e, 0xcf, 0xed, 0x8b, 0xb4, 0xb9, ++ 0x78, 0xba, 0x0f, 0xeb, 0x0e, 0x86, 0xb1, 0x79, 0xbf, 0x89, 0x8e, 0x84, ++ 0xd8, 0x6c, 0xd6, 0x46, 0xdb, 0x82, 0xb1, 0x1a, 0xda, 0x68, 0xeb, 0x40, ++ 0xd6, 0x46, 0x23, 0x35, 0x8a, 0x13, 0x01, 0x62, 0xcc, 0x26, 0x96, 0x89, ++ 0xd3, 0x87, 0xbb, 0x13, 0x6e, 0xe6, 0x43, 0xd5, 0xd8, 0x35, 0xe1, 0xc5, ++ 0xa3, 0x13, 0x44, 0x88, 0x09, 0x8d, 0x47, 0x31, 0x36, 0x0c, 0x59, 0xe4, ++ 0x86, 0x1e, 0x3c, 0x72, 0xc4, 0x8d, 0xae, 0x91, 0x52, 0xe6, 0x6a, 0x73, ++ 0x70, 0xe0, 0x48, 0x31, 0x1e, 0xe0, 0xf5, 0x1b, 0x16, 0xf9, 0x90, 0xe4, ++ 0xf5, 0xad, 0x23, 0x2e, 0x54, 0x1a, 0x0b, 0x30, 0xc0, 0xc0, 0x14, 0x9b, ++ 0x28, 0xa1, 0xec, 0x0c, 0x59, 0xcc, 0x39, 0x9f, 0xa1, 0xcf, 0xed, 0x3c, ++ 0xa2, 0xa0, 0xff, 0xa0, 0x89, 0xfb, 0xd8, 0x4f, 0x4f, 0xf2, 0x38, 0xfd, ++ 0xd5, 0x8d, 0x3b, 0x52, 0xc2, 0xd1, 0x56, 0xe3, 0xf6, 0x7e, 0xdd, 0xd7, ++ 0x4a, 0xdc, 0x1b, 0x86, 0xec, 0xab, 0x17, 0xce, 0xbf, 0x1a, 0xeb, 0xe3, ++ 0x7a, 0xa8, 0x13, 0xdd, 0xb0, 0x4c, 0x7d, 0xea, 0x37, 0x0e, 0x3d, 0xe3, ++ 0x77, 0xc8, 0x58, 0x4f, 0x92, 0x0f, 0x67, 0x70, 0x20, 0x4d, 0x76, 0x72, ++ 0x50, 0x70, 0xfe, 0x49, 0xf2, 0x87, 0x1f, 0xd3, 0x9e, 0x55, 0xdc, 0xff, ++ 0xb0, 0x31, 0x7a, 0x56, 0xf1, 0x0f, 0x3c, 0xac, 0xaa, 0xf8, 0xcb, 0x23, ++ 0x2a, 0x36, 0x0e, 0x36, 0xe1, 0x0c, 0x33, 0xc9, 0xd4, 0x12, 0x15, 0x5b, ++ 0x0e, 0x0a, 0x3e, 0x9c, 0x65, 0xbf, 0x56, 0x77, 0x69, 0xd8, 0x09, 0x4c, ++ 0x3c, 0x84, 0xdb, 0x19, 0x43, 0xf7, 0x2e, 0xc9, 0x3e, 0xc3, 0x28, 0x9e, ++ 0x28, 0x83, 0x93, 0xd8, 0xb3, 0x9b, 0x70, 0x5f, 0xc4, 0xb2, 0x8f, 0x12, ++ 0x7b, 0x7e, 0xbd, 0xcf, 0x08, 0x8d, 0xa9, 0x65, 0x78, 0x73, 0x4c, 0xb0, ++ 0xa7, 0x0c, 0x37, 0x0f, 0x19, 0x94, 0x41, 0xb0, 0xa6, 0x91, 0x78, 0x7d, ++ 0xd2, 0xe6, 0x89, 0xe9, 0x89, 0x06, 0xce, 0x83, 0x89, 0xad, 0x89, 0x1a, ++ 0xf6, 0xed, 0xc1, 0x13, 0xd4, 0xd9, 0xe3, 0x6c, 0x67, 0xd9, 0x22, 0x2f, ++ 0x8e, 0x1e, 0x14, 0xec, 0x33, 0xb1, 0x99, 0x7e, 0x7f, 0x3e, 0x2e, 0xef, ++ 0x0c, 0x18, 0x91, 0x1e, 0xf8, 0x8f, 0x15, 0x91, 0x7b, 0xff, 0x3a, 0x55, ++ 0x8c, 0xf5, 0x43, 0xd5, 0x78, 0x7d, 0xd4, 0x8d, 0xee, 0x91, 0x93, 0x76, ++ 0x1c, 0x7b, 0x24, 0x39, 0x0f, 0x4f, 0x1e, 0x96, 0xb6, 0x64, 0xbe, 0xca, ++ 0xec, 0xbd, 0x8d, 0xfe, 0xa4, 0xc4, 0xb8, 0xc8, 0x6e, 0x15, 0xf8, 0x47, ++ 0x15, 0x27, 0x31, 0x39, 0xa0, 0x77, 0x85, 0x54, 0xc9, 0x8f, 0x55, 0xbc, ++ 0x22, 0x99, 0x59, 0x95, 0x1e, 0xab, 0x50, 0x63, 0xb2, 0x0e, 0x15, 0x9b, ++ 0x4d, 0xdd, 0x3c, 0x3e, 0xe0, 0xc4, 0x6a, 0xe2, 0x58, 0xac, 0x2a, 0x36, ++ 0x45, 0x8e, 0x1a, 0x9b, 0xab, 0x9a, 0xb6, 0xac, 0x7b, 0x93, 0x88, 0x15, ++ 0x30, 0x47, 0x7f, 0x3b, 0x58, 0xd3, 0x59, 0x4e, 0x2c, 0xa4, 0x1d, 0x6b, ++ 0xa5, 0x2a, 0xf1, 0x7c, 0xe2, 0x1c, 0x0e, 0xd3, 0x2f, 0xbe, 0xc6, 0x63, ++ 0x6c, 0xd8, 0xea, 0x6e, 0x63, 0xee, 0xec, 0xac, 0xb5, 0xba, 0x77, 0x9b, ++ 0x46, 0x64, 0x23, 0xfc, 0x7d, 0x45, 0xca, 0x39, 0xfc, 0x3d, 0xfd, 0x6c, ++ 0x7c, 0x58, 0xd6, 0x80, 0xa2, 0xf8, 0x32, 0xfd, 0xcc, 0x32, 0xab, 0xf0, ++ 0x4b, 0x7b, 0xaf, 0x08, 0x31, 0xc8, 0xe6, 0x3e, 0xf5, 0xe5, 0xd9, 0x35, ++ 0xf2, 0x73, 0x38, 0x33, 0x6c, 0x44, 0x0f, 0xb3, 0xce, 0x8b, 0xac, 0xf3, ++ 0xc2, 0x00, 0xf1, 0x86, 0xd8, 0xb2, 0x39, 0x78, 0x6a, 0x45, 0x31, 0xea, ++ 0x7c, 0x45, 0xc8, 0x7c, 0xca, 0xc9, 0xf9, 0xfc, 0x0b, 0xd3, 0x1f, 0x3a, ++ 0xa6, 0xd6, 0xb1, 0xce, 0x39, 0xe2, 0x3a, 0xdb, 0x1f, 0x36, 0x42, 0xb5, ++ 0xf4, 0xe7, 0x71, 0xd6, 0x79, 0x92, 0x75, 0x9e, 0x60, 0x9d, 0x5f, 0x2e, ++ 0x3e, 0xf5, 0xdc, 0x2c, 0xd4, 0x0d, 0xcc, 0x65, 0xf9, 0x03, 0x8b, 0x32, ++ 0x8f, 0x55, 0xc1, 0x6f, 0xce, 0x76, 0x48, 0x7f, 0xe7, 0x18, 0x63, 0xf2, ++ 0xfd, 0xe5, 0xf9, 0x93, 0x17, 0x2d, 0xc4, 0xbb, 0xec, 0xfb, 0x3a, 0x1e, ++ 0x34, 0x27, 0x8f, 0x13, 0x0f, 0x03, 0xc4, 0xbc, 0xb3, 0x8c, 0x87, 0x21, ++ 0x62, 0xe1, 0x4a, 0x62, 0x63, 0x2b, 0xfe, 0x67, 0xba, 0x05, 0xdf, 0x4a, ++ 0x47, 0x88, 0x91, 0x61, 0x62, 0x64, 0x23, 0xf1, 0xd1, 0x24, 0x3e, 0x36, ++ 0x10, 0x1f, 0x89, 0xc1, 0xe3, 0xdf, 0x43, 0x01, 0x63, 0x9a, 0x6b, 0xc8, ++ 0xb2, 0x86, 0x89, 0x85, 0x4f, 0xf1, 0x18, 0x33, 0xeb, 0xb5, 0x0e, 0xcc, ++ 0xe3, 0xbd, 0x07, 0xec, 0xf7, 0x0a, 0x47, 0xd9, 0x5e, 0xd1, 0x50, 0xfd, ++ 0x01, 0x0f, 0x39, 0x66, 0x20, 0x58, 0x13, 0xea, 0x63, 0xff, 0xbf, 0x30, ++ 0xea, 0xfb, 0xaa, 0x60, 0x74, 0x2d, 0x56, 0xff, 0x0a, 0xd3, 0xab, 0x34, ++ 0xe2, 0x47, 0x15, 0xbc, 0x23, 0x9a, 0xec, 0x2d, 0xfc, 0x95, 0x07, 0x35, ++ 0x27, 0xe6, 0x3a, 0xf0, 0xc4, 0x35, 0x70, 0x78, 0xe6, 0xe0, 0xba, 0x63, ++ 0x3d, 0xb4, 0xcb, 0xd1, 0x39, 0x0e, 0x63, 0x9e, 0xcd, 0x3d, 0xeb, 0x2f, ++ 0xb7, 0xc8, 0x7b, 0x87, 0xb3, 0x24, 0xd6, 0xe8, 0xde, 0x88, 0x8a, 0x46, ++ 0xb2, 0xf9, 0xea, 0x02, 0xc8, 0x1e, 0xfd, 0x22, 0xc6, 0x37, 0xfb, 0xfd, ++ 0xdd, 0x03, 0xc2, 0x15, 0x67, 0x19, 0xb2, 0xcf, 0x3a, 0x76, 0xf7, 0x2c, ++ 0x72, 0x01, 0x37, 0xe3, 0x7e, 0x47, 0x50, 0x43, 0x71, 0xd8, 0x1f, 0xda, ++ 0x23, 0xef, 0x7b, 0xd6, 0x85, 0xe8, 0x2f, 0x27, 0x98, 0x53, 0x87, 0xd1, ++ 0x9a, 0xce, 0x3f, 0x37, 0xff, 0xe3, 0x7f, 0x9f, 0x26, 0xde, 0xa5, 0x82, ++ 0xbf, 0xb7, 0x62, 0x95, 0xd7, 0x6d, 0x9d, 0x05, 0x43, 0xfb, 0x9e, 0xa2, ++ 0x1f, 0x03, 0x32, 0x4a, 0x36, 0xe7, 0xce, 0xe2, 0x5a, 0x09, 0xfd, 0xef, ++ 0xbe, 0xfe, 0x98, 0x55, 0x49, 0x9e, 0x35, 0x6f, 0x48, 0xf7, 0x75, 0x29, ++ 0x86, 0x36, 0x88, 0xb3, 0x98, 0x3b, 0x14, 0x40, 0x33, 0xe3, 0xc9, 0x6d, ++ 0xfd, 0xb2, 0xae, 0xd4, 0x8e, 0x67, 0xe2, 0x70, 0x5f, 0xc3, 0xb2, 0xff, ++ 0x4a, 0xae, 0x31, 0x4e, 0x2c, 0x2b, 0x84, 0x1e, 0x39, 0xcd, 0xf1, 0xb9, ++ 0x1d, 0xc6, 0x65, 0x29, 0x5f, 0x32, 0xd4, 0x80, 0xb5, 0x94, 0xa9, 0x75, ++ 0xd0, 0xc2, 0xab, 0x8b, 0x89, 0x13, 0x8b, 0xf5, 0xad, 0x97, 0xd5, 0xc8, ++ 0x3d, 0x73, 0x90, 0xe9, 0xac, 0xe0, 0xdc, 0x3e, 0x17, 0xd4, 0x43, 0xfd, ++ 0x8a, 0x1e, 0xb8, 0x45, 0x91, 0x3d, 0xc2, 0xdd, 0xcc, 0xff, 0xed, 0xbd, ++ 0x61, 0xc7, 0x0f, 0x21, 0x22, 0x3c, 0x7d, 0x6a, 0x93, 0x43, 0xbf, 0xfc, ++ 0x43, 0x34, 0xc1, 0x1d, 0x2c, 0xc7, 0xbc, 0xb0, 0x7e, 0xe2, 0x46, 0xb5, ++ 0x0f, 0xa1, 0x3a, 0xbd, 0xef, 0x7d, 0x87, 0x1b, 0x15, 0xd7, 0xa7, 0x88, ++ 0x03, 0x27, 0xb1, 0x9f, 0x78, 0x30, 0x92, 0x4e, 0x2a, 0xd3, 0x95, 0x4f, ++ 0x60, 0x30, 0x2d, 0x6b, 0xde, 0xb2, 0xce, 0xf9, 0xbb, 0xbb, 0x5f, 0xf2, ++ 0xeb, 0xd1, 0x49, 0xf2, 0x8d, 0xdd, 0x57, 0xde, 0x81, 0xf8, 0x3e, 0xca, ++ 0x39, 0xc7, 0x65, 0xb9, 0x39, 0x7c, 0x3e, 0x28, 0x78, 0x5e, 0x43, 0x3c, ++ 0xd7, 0x7d, 0x77, 0x28, 0x96, 0x35, 0x74, 0x65, 0x2e, 0x13, 0xcc, 0xf5, ++ 0xb2, 0x58, 0xfb, 0x78, 0x92, 0xb6, 0x93, 0xa4, 0xed, 0x30, 0xee, 0x37, ++ 0xdf, 0x42, 0xfb, 0x49, 0xd2, 0x7e, 0x92, 0xb4, 0x1f, 0xb1, 0xab, 0x24, ++ 0x6d, 0x88, 0xfe, 0xfd, 0x78, 0x92, 0x36, 0xc4, 0x58, 0x92, 0x5d, 0x9b, ++ 0x6c, 0xb3, 0xf3, 0xb4, 0xf6, 0x41, 0x1f, 0xae, 0x59, 0xec, 0x54, 0xa7, ++ 0xab, 0x14, 0xcc, 0x21, 0xc7, 0x98, 0x3f, 0xa4, 0x1f, 0x17, 0x7e, 0xff, ++ 0xde, 0xe2, 0x32, 0xf8, 0x66, 0x29, 0x98, 0x67, 0x78, 0xd0, 0xda, 0xdf, ++ 0x0b, 0x47, 0xa2, 0xfe, 0xb8, 0x43, 0x61, 0x9e, 0x3f, 0x47, 0x37, 0xa1, ++ 0xf4, 0xa2, 0x20, 0xd1, 0x01, 0x57, 0xa2, 0x3e, 0xf4, 0x34, 0x72, 0xef, ++ 0xa4, 0xa2, 0x03, 0xce, 0x84, 0xac, 0x61, 0xd3, 0xae, 0xfb, 0x3b, 0x50, ++ 0x92, 0xa8, 0x37, 0xef, 0xe0, 0xbd, 0x8c, 0x47, 0x6c, 0x48, 0xee, 0xd5, ++ 0x9c, 0x18, 0x61, 0xbb, 0xd3, 0x9f, 0x55, 0xd9, 0x66, 0xbd, 0xef, 0x0b, ++ 0x6a, 0xab, 0x12, 0xb3, 0xf3, 0x19, 0xf2, 0x8d, 0xfe, 0x52, 0xdc, 0x40, ++ 0x1e, 0xea, 0x25, 0x07, 0xbd, 0x79, 0xb2, 0x11, 0x6d, 0xfd, 0x8f, 0x92, ++ 0x8f, 0xfa, 0xa3, 0x97, 0x89, 0xf7, 0xe6, 0x64, 0x13, 0x56, 0x0c, 0x0a, ++ 0x1f, 0x35, 0x7c, 0xfd, 0x8a, 0x8f, 0xf6, 0xf4, 0x0e, 0xf9, 0x68, 0x09, ++ 0x16, 0x1e, 0x12, 0xbb, 0xb2, 0xac, 0x75, 0x4b, 0x8c, 0xc0, 0x39, 0xda, ++ 0x5e, 0x41, 0xf8, 0x04, 0x31, 0xcc, 0x3f, 0x75, 0x94, 0xb6, 0x77, 0x33, ++ 0x39, 0xe4, 0xeb, 0x71, 0x2f, 0x7c, 0x93, 0xbf, 0xb5, 0xdc, 0xe4, 0xa1, ++ 0x35, 0xe4, 0x90, 0x97, 0x89, 0xa1, 0xf3, 0x97, 0x18, 0x5b, 0x9b, 0x1c, ++ 0xd5, 0x08, 0x91, 0x83, 0xbe, 0x13, 0xd7, 0x63, 0xff, 0xa4, 0x1a, 0xb8, ++ 0x81, 0xfc, 0xf3, 0xe7, 0xf1, 0x06, 0xf6, 0x53, 0x8a, 0x4f, 0x4c, 0xfa, ++ 0x70, 0xfd, 0x64, 0x80, 0xf5, 0x42, 0xf0, 0x1d, 0xbd, 0x85, 0x87, 0x07, ++ 0x6f, 0xc5, 0x6b, 0x5a, 0x47, 0x94, 0x9a, 0xb6, 0x9b, 0x94, 0x4a, 0x44, ++ 0x98, 0x2f, 0x5f, 0x37, 0xf9, 0x49, 0xbc, 0x4d, 0xec, 0x6a, 0x48, 0x00, ++ 0x46, 0x02, 0xf7, 0x96, 0x7f, 0xf0, 0xbd, 0xcb, 0xf6, 0x3d, 0xcc, 0x9b, ++ 0x36, 0x52, 0x6e, 0x3f, 0xb9, 0xe6, 0x02, 0x96, 0x7d, 0x7d, 0xa0, 0x18, ++ 0x35, 0x87, 0x4e, 0x10, 0xd3, 0x0b, 0x30, 0xff, 0x61, 0x37, 0x9a, 0x8e, ++ 0xa6, 0x88, 0x71, 0xb2, 0xcf, 0x48, 0xde, 0xe3, 0x05, 0x36, 0x1e, 0x14, ++ 0x4e, 0x96, 0xa2, 0xff, 0x5b, 0xd6, 0x21, 0x53, 0xe2, 0x9e, 0x0f, 0x87, ++ 0xc8, 0x8b, 0xc6, 0x92, 0xb1, 0xa5, 0x2a, 0x4e, 0x10, 0x53, 0xfd, 0x53, ++ 0xf2, 0x18, 0x7c, 0x7e, 0x58, 0xf8, 0xa3, 0x13, 0x5e, 0xc6, 0xcb, 0x5e, ++ 0xce, 0x69, 0x9a, 0xe3, 0x4b, 0x92, 0xa3, 0x1d, 0x8f, 0x57, 0x63, 0x80, ++ 0x1c, 0x2d, 0x46, 0x8e, 0x16, 0x23, 0x1f, 0x8b, 0x91, 0xa3, 0xc9, 0x7b, ++ 0xd0, 0x31, 0x72, 0xb4, 0x18, 0x39, 0x5a, 0x2c, 0xd5, 0x84, 0xf1, 0x01, ++ 0x15, 0xbb, 0x0e, 0x6b, 0x6a, 0x86, 0x73, 0x5c, 0xc6, 0xf8, 0x33, 0xfd, ++ 0xe7, 0x9f, 0x64, 0x1e, 0x72, 0x2b, 0x0f, 0x79, 0x0e, 0x2f, 0xfb, 0xd4, ++ 0xa4, 0x4d, 0x37, 0x46, 0x52, 0xc2, 0x95, 0x1b, 0x99, 0x9b, 0x9f, 0xc4, ++ 0x97, 0x58, 0xe7, 0x6d, 0x62, 0x6c, 0x66, 0x95, 0xc9, 0xf3, 0x13, 0x8c, ++ 0x47, 0x27, 0x89, 0xfb, 0x27, 0xd1, 0xc9, 0x60, 0xbc, 0x96, 0xe3, 0xd7, ++ 0x88, 0xd1, 0x2f, 0x2f, 0x02, 0x9a, 0xc6, 0x4e, 0xd0, 0x0f, 0x4f, 0x32, ++ 0x1e, 0x93, 0xbb, 0xaa, 0x6c, 0x7f, 0x1f, 0x32, 0xb2, 0xaf, 0xfd, 0xf9, ++ 0xa0, 0xc4, 0xd0, 0x93, 0x1c, 0xd7, 0x09, 0xf2, 0x53, 0x3d, 0xf4, 0x2e, ++ 0x6d, 0xc1, 0x39, 0x52, 0x85, 0xda, 0x87, 0xf5, 0xd0, 0x4f, 0x61, 0xb4, ++ 0xef, 0x80, 0xd5, 0x74, 0xda, 0xf4, 0x6b, 0xeb, 0xe5, 0xf9, 0xd7, 0x51, ++ 0x95, 0x76, 0xe7, 0xa4, 0xef, 0x34, 0xd1, 0xee, 0x22, 0x08, 0xdd, 0xc4, ++ 0x1c, 0xe7, 0x10, 0x6d, 0xa7, 0x4a, 0xe2, 0x8d, 0x1e, 0xba, 0x08, 0xe1, ++ 0x45, 0x4e, 0x8c, 0xa7, 0xe4, 0xfd, 0x83, 0x87, 0x70, 0x3a, 0xce, 0xdc, ++ 0xe0, 0x13, 0x3f, 0xb6, 0x2a, 0x88, 0x37, 0x63, 0xa9, 0x32, 0x1c, 0x1b, ++ 0x88, 0xdc, 0x5b, 0x42, 0x1f, 0x55, 0xc9, 0xc7, 0x0f, 0x8d, 0x4a, 0x9f, ++ 0x65, 0xf4, 0x7f, 0xc3, 0xe6, 0xdb, 0xde, 0x43, 0x59, 0xbe, 0x7e, 0xe7, ++ 0xa0, 0x11, 0x95, 0x77, 0x1c, 0xfa, 0xc9, 0x53, 0x56, 0x1c, 0x3c, 0xc1, ++ 0xf6, 0x24, 0xd6, 0xf8, 0xf0, 0x6c, 0x5c, 0xc3, 0xa6, 0x09, 0x03, 0x4f, ++ 0xc7, 0xc9, 0xd9, 0x27, 0x02, 0x78, 0x8a, 0x7a, 0xed, 0x60, 0xac, 0x3c, ++ 0x1d, 0x17, 0x0c, 0xaf, 0xc6, 0xfa, 0x09, 0x15, 0x6e, 0xe3, 0xab, 0x98, ++ 0xfa, 0x9c, 0x60, 0xf4, 0x59, 0x24, 0x93, 0x19, 0xb6, 0xa7, 0xfb, 0xa6, ++ 0xd5, 0xb3, 0xb8, 0x38, 0x78, 0x16, 0x3f, 0xe3, 0xf1, 0x26, 0x31, 0x43, ++ 0xa3, 0x8f, 0xde, 0x1f, 0x8c, 0xdc, 0xab, 0x21, 0x13, 0xa0, 0x4d, 0x78, ++ 0x8f, 0x10, 0x27, 0x7e, 0x42, 0x3e, 0xb0, 0xde, 0x11, 0x09, 0x16, 0x41, ++ 0xbf, 0xfc, 0x3c, 0x39, 0xcf, 0x82, 0x3a, 0xf2, 0x09, 0xe2, 0xc0, 0xa3, ++ 0xe4, 0x3b, 0xb7, 0x8e, 0xc9, 0x5c, 0xcb, 0xbc, 0xfb, 0x70, 0x22, 0x19, ++ 0x5b, 0x4f, 0x53, 0x68, 0xae, 0x20, 0xc7, 0x39, 0xa0, 0x9c, 0xa0, 0x2e, ++ 0xfd, 0xed, 0x15, 0xb4, 0xa1, 0x12, 0xda, 0x61, 0x6f, 0xbf, 0xd8, 0x8b, ++ 0xfd, 0x5c, 0xf7, 0x66, 0x17, 0x44, 0xb6, 0x46, 0x24, 0xfa, 0xad, 0xee, ++ 0x0a, 0xe6, 0x64, 0x17, 0x97, 0x54, 0xe3, 0xfe, 0x89, 0x5b, 0xb1, 0x7d, ++ 0xb0, 0x1a, 0xf7, 0xf6, 0x7b, 0xb1, 0xb1, 0x1f, 0xab, 0x1c, 0x50, 0xbf, ++ 0x44, 0x3c, 0xca, 0x30, 0x27, 0xd3, 0x7e, 0x4e, 0xec, 0x2e, 0x76, 0xe8, ++ 0x53, 0xa7, 0x18, 0x5f, 0xc5, 0xee, 0xbb, 0x18, 0xf3, 0xb7, 0x92, 0x27, ++ 0x45, 0xc9, 0x93, 0xa2, 0xac, 0xd7, 0x3b, 0xe8, 0xc2, 0x7c, 0x43, 0x78, ++ 0x8f, 0x07, 0x1d, 0xcc, 0x43, 0x12, 0x0f, 0x1b, 0x91, 0x8b, 0xaa, 0x8c, ++ 0x6d, 0x0e, 0xee, 0x3f, 0x72, 0x2b, 0x76, 0x10, 0x1b, 0x36, 0xf0, 0x7a, ++ 0xff, 0xc3, 0x0b, 0xf0, 0x45, 0xf2, 0xa4, 0xe8, 0x44, 0x13, 0x76, 0x0d, ++ 0xaa, 0xd8, 0x74, 0x44, 0xfa, 0xfc, 0x24, 0x76, 0x0f, 0xd6, 0xb4, 0xd5, ++ 0x30, 0x4f, 0x5b, 0xe6, 0x57, 0x68, 0xc7, 0xa9, 0x9c, 0x8d, 0xb8, 0xf1, ++ 0xb9, 0x94, 0xd8, 0x85, 0xe8, 0x5d, 0x6c, 0x43, 0xc5, 0x5d, 0x0f, 0x57, ++ 0xa1, 0x7c, 0xff, 0x93, 0x96, 0xd7, 0x30, 0x3a, 0x2b, 0x54, 0xab, 0xe9, ++ 0xe9, 0xa0, 0x3f, 0x74, 0x84, 0xf3, 0xbe, 0x9c, 0xdc, 0x67, 0xe5, 0xa0, ++ 0x70, 0xa2, 0x26, 0xec, 0x0e, 0x46, 0x50, 0x43, 0xfe, 0xb3, 0xf4, 0xa0, ++ 0xb4, 0x71, 0xd6, 0xfe, 0xfe, 0x41, 0x11, 0x73, 0x1a, 0x5f, 0xfa, 0x21, ++ 0xbc, 0x40, 0xde, 0xea, 0xe0, 0x5c, 0xd7, 0xa7, 0xcb, 0xb0, 0x60, 0x1f, ++ 0x62, 0x25, 0xe1, 0x6e, 0xac, 0x25, 0xff, 0x91, 0x3e, 0x12, 0x9c, 0xdb, ++ 0xb3, 0x83, 0x46, 0x97, 0x97, 0xfc, 0xe7, 0xe5, 0x83, 0x62, 0x87, 0x65, ++ 0xe8, 0x1f, 0x34, 0xd8, 0x7e, 0x19, 0x76, 0xd9, 0xb9, 0x99, 0x86, 0xe7, ++ 0xe8, 0x17, 0xaf, 0xa6, 0xbc, 0x78, 0x7e, 0xc0, 0x7f, 0x7c, 0x29, 0x39, ++ 0xcd, 0xab, 0xb4, 0x91, 0xa4, 0x2d, 0x9b, 0x17, 0xe7, 0xfa, 0x8d, 0xcb, ++ 0x77, 0xc0, 0x3f, 0x75, 0xd1, 0xe1, 0xc5, 0x7b, 0xd4, 0x89, 0xb6, 0xaf, ++ 0x1a, 0x97, 0x68, 0x1f, 0x89, 0xa4, 0xf0, 0x26, 0xc9, 0xd1, 0xc8, 0x69, ++ 0x1f, 0x9e, 0x87, 0x23, 0x47, 0xb2, 0x3c, 0xe7, 0x8d, 0xb8, 0x5c, 0x8b, ++ 0xdc, 0xc3, 0xf9, 0xd2, 0x85, 0xe7, 0xfc, 0x74, 0x40, 0x6f, 0xed, 0x55, ++ 0x64, 0xad, 0x45, 0xc5, 0x67, 0xc9, 0x73, 0x32, 0x55, 0xba, 0xf9, 0x13, ++ 0x35, 0x76, 0x9c, 0x3c, 0xc7, 0x7c, 0x95, 0xf7, 0xdf, 0xa2, 0xaf, 0xf4, ++ 0x0a, 0xff, 0xd1, 0x1c, 0xf8, 0xe9, 0xa2, 0x58, 0xc6, 0xc5, 0xeb, 0xaf, ++ 0x31, 0xd7, 0x2a, 0xa2, 0x8f, 0xed, 0x4f, 0xd6, 0x68, 0xd7, 0x29, 0x0e, ++ 0x8e, 0x45, 0x9f, 0xfa, 0x31, 0xaf, 0xbd, 0x37, 0x29, 0x36, 0x17, 0x82, ++ 0xff, 0xe8, 0x59, 0xfb, 0xdd, 0x93, 0x8c, 0x83, 0xf9, 0x9f, 0x47, 0x3f, ++ 0x1e, 0x85, 0xbc, 0x6b, 0xb7, 0x13, 0x99, 0xcf, 0x9e, 0x60, 0x1d, 0xc1, ++ 0x7e, 0x0d, 0x45, 0x23, 0x35, 0x6d, 0x0f, 0xab, 0x3e, 0x78, 0xc2, 0xba, ++ 0xf6, 0x98, 0xaa, 0xd1, 0x87, 0x4c, 0xac, 0x4e, 0x5b, 0xd6, 0xea, 0x60, ++ 0x36, 0x1e, 0xcc, 0xa2, 0xaf, 0xcd, 0x1f, 0xa9, 0xcc, 0xf1, 0x9f, 0x52, ++ 0x5c, 0x43, 0xae, 0x5c, 0x9a, 0x88, 0x3d, 0x47, 0x0e, 0xcf, 0x84, 0xf4, ++ 0x74, 0xdd, 0x5c, 0xd4, 0x1f, 0x9f, 0xab, 0xe8, 0x5d, 0x94, 0xbd, 0xfd, ++ 0x5d, 0x85, 0xf1, 0x9a, 0x98, 0x58, 0x32, 0x59, 0x7f, 0xcc, 0x03, 0x23, ++ 0xb6, 0x44, 0xbd, 0xef, 0x7d, 0x54, 0x89, 0x0c, 0xcb, 0x2a, 0xb2, 0xeb, ++ 0x08, 0x1e, 0x94, 0x8c, 0xc8, 0xbb, 0x14, 0x96, 0xb5, 0x3e, 0x98, 0xd9, ++ 0x4a, 0xfb, 0x0a, 0x4d, 0x22, 0xcc, 0x18, 0x2e, 0x7b, 0xca, 0xc3, 0x8c, ++ 0xd3, 0x35, 0x97, 0xce, 0xe0, 0x46, 0x64, 0x3e, 0x96, 0x8d, 0xdb, 0x6e, ++ 0xe6, 0x84, 0xaa, 0x5f, 0x63, 0xde, 0xe6, 0xc6, 0xcb, 0x37, 0x66, 0xbf, ++ 0x11, 0x71, 0xd7, 0x9f, 0x10, 0xef, 0x65, 0x5f, 0x5e, 0xdc, 0x94, 0x78, ++ 0x6f, 0x9f, 0x3a, 0xef, 0xe6, 0xf9, 0x35, 0x6c, 0x63, 0xee, 0xa4, 0xd3, ++ 0xf9, 0x17, 0xc9, 0x52, 0xcc, 0x9e, 0x34, 0xf1, 0xb9, 0x6c, 0x3b, 0x8c, ++ 0xe9, 0x2d, 0x8c, 0xe9, 0x0a, 0xbc, 0xc6, 0x0f, 0xf0, 0x9a, 0xcd, 0x07, ++ 0xaa, 0x50, 0x38, 0x22, 0x79, 0x4e, 0x84, 0x79, 0x8e, 0xde, 0x39, 0xce, ++ 0xf3, 0x32, 0xe2, 0xf7, 0xbc, 0x11, 0x05, 0xcf, 0xd5, 0x79, 0x50, 0xc4, ++ 0xdf, 0xea, 0x88, 0x65, 0xb5, 0x98, 0xcf, 0x5a, 0x3b, 0x57, 0xcb, 0x38, ++ 0x85, 0x8f, 0xe9, 0x15, 0x28, 0x67, 0xb2, 0x72, 0x54, 0x78, 0xbc, 0x41, ++ 0x1e, 0x5f, 0x05, 0xd7, 0x48, 0xcd, 0xd6, 0xa5, 0xa8, 0x31, 0x27, 0x59, ++ 0xbf, 0xe0, 0xe8, 0xca, 0x4a, 0x14, 0x4b, 0x59, 0x40, 0x4d, 0xac, 0xad, ++ 0x94, 0x67, 0x1f, 0x73, 0xc2, 0x0a, 0x3e, 0x3b, 0x28, 0xdf, 0x0f, 0x68, ++ 0xee, 0x9a, 0x03, 0xda, 0xca, 0xec, 0x79, 0x38, 0xb6, 0xdf, 0x83, 0xb5, ++ 0xfd, 0xc8, 0x54, 0x1a, 0x56, 0xd3, 0xfb, 0x8b, 0x8d, 0xa9, 0x4a, 0x45, ++ 0xde, 0x85, 0x8b, 0xc2, 0x9b, 0xf4, 0x9f, 0xb8, 0xd5, 0x61, 0x35, 0xbd, ++ 0xb1, 0xa8, 0xbe, 0xed, 0x04, 0x24, 0x7e, 0xcc, 0xc3, 0xb7, 0xc6, 0xe5, ++ 0x9d, 0xdd, 0x76, 0x68, 0x89, 0xe3, 0xb4, 0xc1, 0xd8, 0x03, 0x2e, 0xc4, ++ 0xac, 0x52, 0x43, 0xa7, 0x5f, 0xe8, 0xad, 0x93, 0x4a, 0x37, 0x8c, 0xa0, ++ 0xd1, 0xde, 0x40, 0x7b, 0xfa, 0x5b, 0xd9, 0xdf, 0x1c, 0x6e, 0xc0, 0x1d, ++ 0x69, 0xdd, 0x3c, 0x84, 0x32, 0x3c, 0x4b, 0x3b, 0x7a, 0xbd, 0xb1, 0x0c, ++ 0xa7, 0x47, 0x9b, 0x72, 0x5c, 0x56, 0xe6, 0x47, 0x9e, 0x11, 0x8a, 0x4d, ++ 0x28, 0xf8, 0x76, 0x2d, 0x52, 0x73, 0x51, 0x33, 0xb0, 0x54, 0x75, 0xa4, ++ 0x66, 0x23, 0x82, 0xcb, 0xb5, 0xd7, 0xf9, 0xbe, 0xa1, 0x8a, 0xad, 0xc8, ++ 0x33, 0x26, 0x5d, 0x36, 0x27, 0x93, 0x17, 0xd1, 0xe6, 0xd3, 0xdb, 0x2a, ++ 0x64, 0x1c, 0xa9, 0x74, 0x15, 0x3e, 0xfb, 0xf0, 0x71, 0xe2, 0xbe, 0x65, ++ 0x3d, 0xbd, 0xe8, 0x17, 0xa5, 0xa2, 0x87, 0x7f, 0x18, 0x97, 0x36, 0x4f, ++ 0x54, 0x66, 0xf7, 0x63, 0x4b, 0x5c, 0x26, 0x1f, 0x39, 0xea, 0xb0, 0x9f, ++ 0xeb, 0x49, 0x5c, 0xfe, 0x5c, 0x7f, 0x31, 0x7c, 0x87, 0xc4, 0x6f, 0x9c, ++ 0xb8, 0x69, 0x32, 0x86, 0x8a, 0x70, 0x13, 0x4a, 0xf7, 0x95, 0xc2, 0x38, ++ 0x54, 0x8a, 0x40, 0xe2, 0x51, 0x3b, 0x2e, 0x37, 0x1c, 0xf2, 0x7b, 0x2b, ++ 0xc8, 0x51, 0xee, 0x5f, 0xf2, 0x8e, 0xe5, 0x0a, 0x8b, 0x6c, 0x46, 0xe7, ++ 0xfd, 0xf2, 0xcd, 0x94, 0x46, 0xc3, 0x1c, 0xa7, 0x9d, 0xd5, 0x32, 0x36, ++ 0xbf, 0x9f, 0xa8, 0x82, 0x35, 0x72, 0x9c, 0x78, 0xa1, 0xe1, 0x56, 0x9e, ++ 0x5f, 0x4a, 0x48, 0xac, 0xf6, 0xf1, 0xf0, 0x30, 0x0e, 0x1b, 0xfc, 0xef, ++ 0xc5, 0x4f, 0xc8, 0xd3, 0x2e, 0x2d, 0x8e, 0x91, 0xa9, 0x06, 0xb0, 0x90, ++ 0xb6, 0xf9, 0x5e, 0x42, 0xcf, 0x34, 0x13, 0x6b, 0xde, 0x5a, 0x6c, 0x52, ++ 0x96, 0x52, 0xfc, 0x2c, 0x21, 0x6b, 0x15, 0xa7, 0x1e, 0xf4, 0x22, 0x56, ++ 0x53, 0x4a, 0x9b, 0x3e, 0x4f, 0x3c, 0x29, 0x67, 0x2e, 0x18, 0x38, 0x7a, ++ 0x23, 0x65, 0x6e, 0x40, 0x3d, 0xe3, 0xef, 0xe4, 0x68, 0x18, 0x9b, 0x18, ++ 0x5b, 0xf7, 0x24, 0x25, 0x7f, 0xb4, 0xac, 0x9f, 0x9b, 0x7e, 0x73, 0x8c, ++ 0xb8, 0xba, 0x6c, 0xe2, 0x04, 0xfe, 0x47, 0xd2, 0xde, 0xa3, 0x96, 0x71, ++ 0x1b, 0x21, 0x7c, 0x8f, 0x31, 0xaf, 0xc0, 0xf0, 0x62, 0x15, 0xb1, 0xf5, ++ 0x39, 0xe6, 0xd7, 0x2b, 0x88, 0x91, 0x11, 0x62, 0x64, 0x64, 0xc2, 0x83, ++ 0xc8, 0x91, 0x39, 0x3c, 0x7c, 0x3c, 0x16, 0xf0, 0x30, 0x78, 0x8d, 0x7e, ++ 0xce, 0xfc, 0xb0, 0x99, 0x78, 0xf7, 0x28, 0x31, 0x44, 0x62, 0xe2, 0x01, ++ 0x62, 0xde, 0xbb, 0xb4, 0xcb, 0x9b, 0xf6, 0x01, 0xd7, 0x8c, 0x09, 0x7e, ++ 0x0b, 0xbe, 0x28, 0xc4, 0x57, 0x05, 0xe7, 0x0f, 0x0a, 0x8e, 0xa8, 0xf8, ++ 0xfa, 0xc3, 0xc6, 0xd6, 0x4e, 0xc5, 0x1f, 0x38, 0x4b, 0x39, 0x8f, 0x10, ++ 0xf7, 0xc6, 0x99, 0xf3, 0xbd, 0x6e, 0xaa, 0x18, 0x3b, 0x28, 0x31, 0xf7, ++ 0x24, 0xe7, 0xe1, 0x24, 0x1e, 0x60, 0xcc, 0xbd, 0x75, 0x11, 0x63, 0xee, ++ 0x67, 0xe4, 0xbd, 0x22, 0x27, 0x76, 0xa6, 0x1e, 0xc2, 0x97, 0xe2, 0x4f, ++ 0xda, 0xd8, 0x97, 0x64, 0x9c, 0xeb, 0x1b, 0xe8, 0x46, 0x09, 0x63, 0xdc, ++ 0xde, 0xd1, 0x93, 0xf6, 0xde, 0xee, 0xb7, 0x07, 0x8c, 0xc0, 0x69, 0xe2, ++ 0xdc, 0x1b, 0x3c, 0xff, 0x1f, 0x3c, 0x3f, 0xb3, 0xcf, 0x87, 0xa3, 0x4b, ++ 0xca, 0xf0, 0x0c, 0x65, 0xd8, 0x93, 0x3c, 0x69, 0xbf, 0x2b, 0xdb, 0xd6, ++ 0xaf, 0xd9, 0x3a, 0x5d, 0xd1, 0xef, 0xa1, 0x1e, 0xc9, 0x89, 0x19, 0x27, ++ 0x16, 0x4c, 0x92, 0xeb, 0xf6, 0x57, 0xa3, 0x69, 0xf2, 0xe3, 0x33, 0x6c, ++ 0x69, 0x91, 0x3d, 0xef, 0x19, 0xb5, 0x0a, 0xc5, 0x76, 0xde, 0x6f, 0x30, ++ 0xef, 0xd7, 0x0f, 0xfc, 0xd4, 0x51, 0x85, 0x59, 0x57, 0xfc, 0x80, 0x31, ++ 0x7d, 0x34, 0x65, 0x3f, 0xff, 0x2f, 0xa5, 0x4c, 0x0d, 0x13, 0x2b, 0x35, ++ 0x79, 0x7f, 0x7c, 0x7b, 0x52, 0xd6, 0xd5, 0xc5, 0xe6, 0xdb, 0x68, 0xf3, ++ 0x33, 0xdf, 0x8d, 0xa7, 0x7d, 0xa5, 0xb7, 0xe1, 0x81, 0x7d, 0x7a, 0x97, ++ 0xd3, 0x11, 0xb3, 0x34, 0xa3, 0x9b, 0x9c, 0xa2, 0x1b, 0xfe, 0x45, 0x46, ++ 0xfb, 0x25, 0x45, 0xef, 0xfc, 0xa1, 0x52, 0x8c, 0xd2, 0xf0, 0x53, 0xd8, ++ 0x31, 0xa6, 0x07, 0x52, 0x8a, 0x41, 0x5b, 0xd7, 0xf0, 0xd8, 0x70, 0x01, ++ 0x3a, 0xf7, 0xaf, 0xc3, 0xd1, 0x01, 0x3d, 0x14, 0x83, 0xc9, 0x39, 0xaa, ++ 0xf1, 0x15, 0x29, 0x97, 0x70, 0xda, 0x64, 0x7e, 0x99, 0x9e, 0x8b, 0x75, ++ 0x9a, 0xec, 0x43, 0x5b, 0xc7, 0xfc, 0xf2, 0x92, 0x55, 0x66, 0xb4, 0xa1, ++ 0xd8, 0x30, 0xc8, 0x9d, 0x2d, 0xec, 0x0d, 0xde, 0x80, 0xcd, 0x36, 0x6e, ++ 0x14, 0xca, 0xf7, 0x4b, 0x4a, 0xe7, 0x1b, 0x06, 0xf9, 0xbc, 0xac, 0x91, ++ 0x78, 0x67, 0xec, 0xc5, 0x96, 0xb5, 0xf8, 0xba, 0x8a, 0xec, 0x5e, 0x80, ++ 0x3f, 0x56, 0x66, 0x1a, 0x87, 0x86, 0x25, 0xdf, 0x9c, 0xa5, 0x3c, 0x39, ++ 0x50, 0xeb, 0xed, 0xa1, 0xfd, 0x3e, 0x68, 0x66, 0xf0, 0xe6, 0xe2, 0x22, ++ 0x72, 0x5d, 0x05, 0xc1, 0x1b, 0x42, 0xd2, 0x07, 0xff, 0x2e, 0x58, 0xbe, ++ 0xcf, 0x4a, 0x3b, 0xe7, 0x72, 0x7a, 0xfc, 0x1b, 0x2a, 0x4f, 0xce, 0xe5, ++ 0x5d, 0x50, 0x7b, 0x7d, 0x28, 0x77, 0xfd, 0x47, 0x56, 0xc4, 0x23, 0xd7, ++ 0x17, 0xb0, 0x9e, 0xe8, 0x6b, 0x96, 0x72, 0xef, 0x40, 0x13, 0x16, 0x04, ++ 0x67, 0x29, 0xeb, 0x46, 0xf3, 0x75, 0x5e, 0x41, 0x7a, 0xf8, 0x15, 0xc6, ++ 0x2b, 0x3d, 0x30, 0x0d, 0x57, 0xee, 0xbb, 0x08, 0xb2, 0x77, 0xcf, 0xc5, ++ 0xfc, 0x4a, 0x9e, 0x9f, 0x5c, 0xc0, 0xe0, 0x7e, 0xf1, 0x4b, 0xcb, 0xf2, ++ 0xd7, 0x5e, 0xc0, 0x8e, 0xf1, 0x13, 0x4a, 0x7b, 0xf2, 0x7d, 0x0b, 0x85, ++ 0xb3, 0xa2, 0x73, 0xed, 0xbd, 0xed, 0xd2, 0x46, 0xaf, 0xd2, 0x96, 0xf6, ++ 0x87, 0x1e, 0x64, 0x00, 0xd0, 0xc2, 0xf2, 0xcd, 0x02, 0x19, 0xdb, 0x09, ++ 0x5e, 0x33, 0xec, 0xf7, 0xc3, 0x8e, 0xdb, 0xe3, 0xfc, 0xb0, 0x1e, 0xbe, ++ 0x69, 0x45, 0xda, 0xa4, 0x6e, 0x5e, 0xae, 0x71, 0xca, 0x23, 0xb2, 0xe5, ++ 0xef, 0x4f, 0xe4, 0x64, 0x2f, 0x84, 0xaf, 0x2a, 0x5b, 0xa6, 0x93, 0xb2, ++ 0x17, 0x30, 0x5e, 0x9f, 0x6a, 0x9c, 0x29, 0x7f, 0x7e, 0xac, 0x07, 0x3f, ++ 0xd0, 0x5e, 0xb6, 0xec, 0x3f, 0x55, 0xc9, 0xde, 0xb6, 0x53, 0x8d, 0x53, ++ 0xf8, 0x3b, 0x3b, 0xf7, 0x7d, 0x0b, 0xb1, 0xb4, 0x7c, 0xdf, 0xa8, 0x39, ++ 0x52, 0x84, 0x4f, 0x41, 0xbd, 0x3e, 0xb6, 0xb0, 0x08, 0x92, 0x47, 0x46, ++ 0xda, 0x8a, 0x88, 0x5d, 0x6e, 0x23, 0xf2, 0xa0, 0x1b, 0x99, 0x8c, 0x9b, ++ 0x7c, 0xfa, 0xb2, 0x72, 0x4c, 0xd9, 0xe4, 0xd7, 0xb7, 0xbe, 0x43, 0x7e, ++ 0xf7, 0xa2, 0x3f, 0xc6, 0x39, 0x37, 0xbc, 0xe4, 0xdb, 0xe6, 0x06, 0xf2, ++ 0x6e, 0xe1, 0x54, 0x1d, 0xfe, 0x3e, 0xfb, 0x39, 0xb5, 0x12, 0x5e, 0x89, ++ 0xeb, 0xec, 0x6f, 0x8b, 0xb4, 0xc1, 0x48, 0xbd, 0x42, 0x5b, 0x91, 0xdf, ++ 0x51, 0x2c, 0xb4, 0xaf, 0x75, 0x20, 0x60, 0xff, 0x5f, 0x9d, 0xfb, 0xfe, ++ 0x48, 0x3b, 0x6a, 0xec, 0xff, 0x6b, 0x50, 0x9b, 0xba, 0xf2, 0x7c, 0x01, ++ 0xdb, 0x99, 0xa3, 0x3f, 0x63, 0xca, 0xbb, 0x89, 0x57, 0xde, 0x23, 0x58, ++ 0xe9, 0x80, 0x3f, 0x44, 0x8a, 0x1c, 0xcd, 0x7e, 0x7f, 0xe9, 0xea, 0xbb, ++ 0x81, 0xcb, 0x3e, 0xf0, 0x1e, 0x81, 0xfd, 0x5e, 0x9b, 0xfd, 0xfd, 0xad, ++ 0xba, 0x25, 0x4e, 0xf2, 0x95, 0xf2, 0x68, 0x29, 0x7f, 0xef, 0x58, 0x52, ++ 0x80, 0xcd, 0xe4, 0xc1, 0xad, 0xd7, 0x3f, 0x85, 0x8b, 0x29, 0x27, 0xb9, ++ 0x65, 0x2c, 0x78, 0x98, 0xfd, 0x9d, 0x8a, 0xab, 0x38, 0x3d, 0xdc, 0x1b, ++ 0x3c, 0x64, 0xf7, 0x7d, 0x1e, 0xdb, 0xc7, 0x25, 0xfe, 0xb4, 0x31, 0xfe, ++ 0x5c, 0x24, 0x0e, 0x48, 0x5b, 0x31, 0x4b, 0x35, 0xf4, 0x4c, 0x07, 0x8c, ++ 0x29, 0xd5, 0x11, 0xc0, 0xdd, 0x8c, 0xb3, 0x67, 0xe2, 0xdd, 0x70, 0x2d, ++ 0xd6, 0xbb, 0xbe, 0xc3, 0x58, 0x5e, 0x1e, 0xd6, 0x03, 0x6f, 0x2b, 0xed, ++ 0x98, 0x60, 0xfd, 0xa9, 0xb8, 0xf8, 0x85, 0x7c, 0x9f, 0x68, 0x0d, 0x8e, ++ 0x31, 0x07, 0x78, 0x91, 0x7c, 0xf6, 0x62, 0x63, 0x29, 0x52, 0xcc, 0x09, ++ 0x5e, 0x88, 0xbb, 0xf1, 0x75, 0x72, 0x9f, 0xaf, 0x0d, 0xcb, 0x3b, 0x6c, ++ 0x2d, 0x68, 0x8e, 0xcb, 0x33, 0x06, 0x0f, 0x1e, 0x3b, 0xec, 0xa1, 0x6d, ++ 0x5b, 0xd6, 0x76, 0xf3, 0x1a, 0xfa, 0xd3, 0x59, 0xf6, 0x29, 0x6b, 0x5b, ++ 0x11, 0xdc, 0xde, 0x5f, 0x85, 0xaf, 0x1d, 0xf6, 0xe2, 0xa5, 0xb8, 0x81, ++ 0x04, 0xeb, 0x9d, 0x89, 0xfb, 0xd0, 0x4f, 0xde, 0xf4, 0x2c, 0xf3, 0xa3, ++ 0x5d, 0x3c, 0x97, 0x6f, 0x5d, 0x15, 0x18, 0x01, 0xc4, 0x53, 0x27, 0x51, ++ 0xd2, 0x7f, 0x2d, 0x36, 0xae, 0x7a, 0x02, 0x6a, 0xff, 0x09, 0x1e, 0xb7, ++ 0xa0, 0xe7, 0xf0, 0x2d, 0x48, 0x0e, 0x87, 0x91, 0x3c, 0xfc, 0x0a, 0xfa, ++ 0x86, 0x65, 0x5c, 0xf2, 0xcd, 0x22, 0xd9, 0x37, 0x66, 0x60, 0x61, 0xbf, ++ 0xac, 0x1d, 0x4b, 0x3f, 0x55, 0xec, 0xfb, 0x4f, 0x6d, 0xff, 0xa7, 0xd6, ++ 0xc6, 0xbf, 0x90, 0xb6, 0x9f, 0xf8, 0x23, 0xed, 0x8b, 0xae, 0x64, 0x7f, ++ 0x41, 0x1b, 0xe2, 0xfd, 0xf2, 0xfd, 0x0b, 0x37, 0xdb, 0x2c, 0x85, 0x23, ++ 0x9c, 0x59, 0x55, 0xc6, 0x98, 0xb0, 0x47, 0x31, 0x5a, 0x4b, 0x94, 0x8b, ++ 0xd8, 0x93, 0x96, 0xb5, 0xba, 0x42, 0xc6, 0x50, 0xea, 0x30, 0xa8, 0x6b, ++ 0xdf, 0xa1, 0xed, 0x2c, 0x25, 0xdf, 0x3a, 0x6f, 0xde, 0x40, 0x5e, 0x26, ++ 0xfa, 0x2b, 0xc4, 0xcb, 0x03, 0x6e, 0x62, 0x53, 0x18, 0xd9, 0xf7, 0x21, ++ 0x4b, 0xf1, 0xbf, 0x99, 0x0f, 0x3c, 0x15, 0xaf, 0xcf, 0x18, 0x8e, 0x5a, ++ 0x79, 0xdf, 0xd2, 0xbe, 0x76, 0x2a, 0xde, 0x81, 0x43, 0x94, 0xf7, 0x4c, ++ 0xfc, 0x32, 0xe7, 0xa7, 0x93, 0xfa, 0x17, 0x7d, 0xc7, 0x72, 0xba, 0xee, ++ 0xa5, 0xae, 0xab, 0xf1, 0x7c, 0xfc, 0x21, 0x7c, 0x8d, 0xf2, 0x3f, 0x36, ++ 0x60, 0x44, 0x16, 0x28, 0x27, 0x71, 0x6c, 0xb4, 0x10, 0xa7, 0xd9, 0xf6, ++ 0x26, 0xd3, 0x89, 0x69, 0xe9, 0x8b, 0xb8, 0x9c, 0x66, 0xde, 0xf5, 0xf6, ++ 0x92, 0x93, 0x8c, 0x4f, 0x85, 0xf8, 0xdf, 0x03, 0xf2, 0xce, 0x61, 0x05, ++ 0xfb, 0x10, 0xfd, 0xf8, 0xec, 0xdc, 0xab, 0x87, 0x71, 0x60, 0x45, 0xe3, ++ 0x49, 0xec, 0x1e, 0x95, 0x6b, 0xeb, 0x88, 0xfb, 0x97, 0xe0, 0x08, 0x16, ++ 0x60, 0x93, 0xa7, 0x91, 0xb6, 0xce, 0xfc, 0x23, 0xf5, 0xed, 0x59, 0x59, ++ 0x5e, 0xb6, 0x6f, 0x96, 0xbc, 0x7f, 0x77, 0x2a, 0x5e, 0x88, 0x17, 0x58, ++ 0x67, 0x23, 0xb1, 0x22, 0xfb, 0xdc, 0x8d, 0x31, 0x87, 0x7c, 0x21, 0xc5, ++ 0x3e, 0xe2, 0x76, 0x1b, 0xb3, 0x94, 0x03, 0xf4, 0xc3, 0x8a, 0xc5, 0xb3, ++ 0x94, 0x24, 0xcf, 0x13, 0xc9, 0x57, 0xc8, 0x69, 0xb3, 0x3a, 0x3c, 0x64, ++ 0x76, 0x60, 0x34, 0x35, 0x3c, 0xeb, 0xea, 0xf3, 0x22, 0xc1, 0x6f, 0x79, ++ 0xf7, 0xc7, 0xc8, 0x7d, 0xf7, 0xe1, 0xea, 0x73, 0xd1, 0x6f, 0xa4, 0xcb, ++ 0xc9, 0x2b, 0x8b, 0x69, 0x6b, 0x05, 0x51, 0x0f, 0xe3, 0x69, 0xc7, 0x22, ++ 0x0d, 0xfb, 0x6e, 0xbc, 0x40, 0x72, 0xaf, 0x39, 0x7f, 0xd5, 0xf8, 0x0a, ++ 0xfb, 0x29, 0x8f, 0x56, 0x86, 0x4f, 0xd9, 0x7b, 0xe9, 0x82, 0x37, 0xce, ++ 0x46, 0xf9, 0x90, 0xbd, 0xcf, 0x14, 0x6f, 0xc6, 0xab, 0xa2, 0x55, 0xe1, ++ 0x0a, 0x9c, 0x09, 0x5e, 0x42, 0xff, 0x98, 0x13, 0xe5, 0xb2, 0x6e, 0x4b, ++ 0x0e, 0xe0, 0x1e, 0xd1, 0xc8, 0x51, 0xaf, 0xc5, 0xdc, 0x91, 0x79, 0xf0, ++ 0x8e, 0x54, 0xa3, 0x82, 0xfc, 0xac, 0x34, 0x68, 0x59, 0x3f, 0x5b, 0x6c, ++ 0x59, 0xd7, 0xf1, 0x28, 0xe2, 0x71, 0x21, 0x28, 0x7e, 0x1a, 0x41, 0xbd, ++ 0xed, 0xaf, 0x06, 0x1a, 0xec, 0xff, 0x2d, 0xf4, 0xf5, 0xae, 0xe0, 0xc2, ++ 0xc9, 0x87, 0x82, 0xb5, 0x93, 0xb3, 0xa1, 0x0e, 0xcd, 0x81, 0x83, 0x6d, ++ 0xfd, 0xf9, 0x8d, 0x16, 0x5a, 0x4c, 0x59, 0x97, 0x12, 0x7e, 0xd8, 0x41, ++ 0x7e, 0xd8, 0x17, 0x34, 0x26, 0x9f, 0xc0, 0x6d, 0xe4, 0x15, 0xee, 0x21, ++ 0x2f, 0xfb, 0x51, 0x98, 0xef, 0x38, 0x33, 0xf3, 0xc9, 0x4f, 0x6e, 0x58, ++ 0x2c, 0x5c, 0xb1, 0x5d, 0xbe, 0x1b, 0x83, 0xf6, 0xc9, 0x93, 0xb8, 0x8b, ++ 0x65, 0x4a, 0x87, 0x5e, 0x43, 0x22, 0xfd, 0x23, 0xf4, 0xa7, 0x25, 0x9e, ++ 0x64, 0x70, 0x07, 0xdb, 0x2e, 0x1e, 0x6a, 0xc5, 0xa6, 0xc9, 0x95, 0xd8, ++ 0x38, 0x69, 0x61, 0x45, 0x70, 0x0a, 0x2b, 0x26, 0x1f, 0xc2, 0x86, 0xc9, ++ 0xbc, 0xbf, 0xca, 0x5e, 0x81, 0x95, 0x90, 0x77, 0x0d, 0xdd, 0xc4, 0x16, ++ 0x79, 0x77, 0x50, 0xa5, 0x1f, 0x36, 0xd3, 0xbe, 0x9f, 0x4c, 0xc6, 0xb0, ++ 0x7e, 0x52, 0x30, 0x77, 0x1b, 0xb6, 0x4f, 0xca, 0x9a, 0xfd, 0x57, 0x83, ++ 0x0b, 0x26, 0x7f, 0x84, 0xe6, 0xc9, 0xd1, 0x60, 0xdd, 0xe4, 0x61, 0xca, ++ 0x1d, 0xa7, 0x6c, 0x03, 0xc1, 0x9a, 0xc9, 0xe1, 0x60, 0x60, 0xf2, 0x40, ++ 0xd0, 0x3f, 0xd9, 0x86, 0x5d, 0x93, 0xab, 0xb1, 0x73, 0x72, 0x2b, 0x76, ++ 0x4c, 0x0a, 0x6e, 0x4f, 0x63, 0xf9, 0xe4, 0x79, 0x2c, 0x9b, 0x7c, 0x11, ++ 0x2d, 0x93, 0x67, 0xb1, 0x74, 0xf2, 0x15, 0xb4, 0x4e, 0xbe, 0xc6, 0xb1, ++ 0xc8, 0x33, 0x00, 0x59, 0xff, 0xcf, 0x3f, 0x9b, 0x9d, 0xb9, 0xff, 0x5d, ++ 0xf6, 0xf6, 0xc9, 0x7b, 0x7f, 0x32, 0x87, 0x2e, 0xac, 0xd2, 0x2e, 0xa0, ++ 0x77, 0xbf, 0x7c, 0x77, 0xaf, 0x5e, 0xdb, 0x0e, 0x79, 0xee, 0xfe, 0x8a, ++ 0xbc, 0x07, 0x42, 0x1b, 0x9b, 0xb9, 0xd7, 0x5b, 0xd7, 0xa6, 0xaf, 0x3c, ++ 0xa7, 0x96, 0xf7, 0xef, 0x24, 0xf6, 0x5c, 0x64, 0x9e, 0xfa, 0xae, 0x15, ++ 0xd1, 0xa4, 0xac, 0xbc, 0x17, 0x28, 0xf6, 0x70, 0x01, 0x8f, 0xee, 0xbf, ++ 0x48, 0xbe, 0x33, 0x45, 0x3e, 0xa3, 0xe0, 0x9d, 0x3a, 0xf9, 0x26, 0x93, ++ 0x8f, 0xd8, 0x74, 0x01, 0xc9, 0x71, 0x72, 0xad, 0x83, 0xe2, 0x87, 0x1d, ++ 0xf4, 0xc3, 0x29, 0xf1, 0xc9, 0x18, 0x31, 0xf9, 0x0b, 0xa5, 0xd8, 0x86, ++ 0x17, 0x52, 0x05, 0xc8, 0x1c, 0x2e, 0xc6, 0x73, 0xc3, 0x31, 0xe6, 0xee, ++ 0xf2, 0x9d, 0x1a, 0x83, 0xb9, 0x69, 0x31, 0x5e, 0xe3, 0xb5, 0xa9, 0x01, ++ 0xf8, 0xbc, 0x86, 0xdf, 0x3b, 0x9f, 0xe7, 0xa7, 0x47, 0xa7, 0xc8, 0x69, ++ 0xba, 0x30, 0xcd, 0xff, 0x92, 0xf3, 0x03, 0xdb, 0x31, 0x3a, 0x2a, 0xfa, ++ 0x6c, 0xa3, 0x3e, 0x05, 0x17, 0xf5, 0xae, 0x16, 0xe2, 0xa1, 0xa5, 0x08, ++ 0x1e, 0xaa, 0xcc, 0x47, 0x84, 0x4b, 0xd8, 0xdf, 0xb9, 0x31, 0xfb, 0x95, ++ 0x57, 0xf0, 0xc2, 0x61, 0x95, 0xbc, 0x85, 0x79, 0x23, 0xb1, 0xb2, 0x3c, ++ 0xac, 0x18, 0x2b, 0xfc, 0x17, 0xf0, 0xdc, 0x61, 0x27, 0x73, 0x11, 0x27, ++ 0xa6, 0x88, 0x93, 0x8e, 0x84, 0xec, 0xf9, 0x60, 0x76, 0x4e, 0xec, 0xcb, ++ 0x10, 0x8b, 0x32, 0xf6, 0x33, 0x59, 0xe1, 0x56, 0xdf, 0xb3, 0xfb, 0x71, ++ 0x52, 0xf6, 0xde, 0xb8, 0xac, 0xbb, 0x7f, 0x1f, 0x2d, 0xa3, 0xa5, 0xf6, ++ 0x3b, 0x9d, 0x7b, 0x92, 0xe7, 0x91, 0xdc, 0x5f, 0x8d, 0xb5, 0xf6, 0x7b, ++ 0x9d, 0x26, 0x39, 0xbf, 0x17, 0x77, 0x4f, 0x98, 0xe4, 0x81, 0xab, 0xb1, ++ 0xea, 0xc8, 0x67, 0x79, 0xcc, 0xc1, 0x5d, 0x47, 0x3a, 0x71, 0xe7, 0x44, ++ 0x0c, 0xed, 0x13, 0xbd, 0x3c, 0xd6, 0xe1, 0xd3, 0x83, 0x15, 0x48, 0x05, ++ 0x35, 0xec, 0x5d, 0xb2, 0x0e, 0x77, 0x1c, 0x94, 0x3c, 0x76, 0x3d, 0x9e, ++ 0x23, 0xee, 0x04, 0x82, 0xeb, 0x31, 0x65, 0xfb, 0xa2, 0xec, 0x8b, 0x5d, ++ 0x8f, 0x1d, 0x03, 0x86, 0x36, 0x86, 0xf5, 0xe8, 0xe1, 0xb5, 0x41, 0x7b, ++ 0x0e, 0x4e, 0xa2, 0x69, 0x48, 0xc1, 0x7b, 0x37, 0x9d, 0xc4, 0xcd, 0x87, ++ 0xa4, 0xef, 0x4b, 0x48, 0xee, 0xeb, 0x60, 0x9b, 0x19, 0xb4, 0x4d, 0xfc, ++ 0x00, 0x77, 0x0e, 0xe2, 0xde, 0x0a, 0x54, 0xe0, 0xc5, 0xa0, 0xbf, 0xbd, ++ 0x5f, 0xf9, 0x81, 0xdd, 0xf6, 0x8e, 0xe4, 0x8f, 0xc8, 0xc5, 0x2e, 0xe2, ++ 0xb1, 0xd4, 0x6b, 0xe8, 0x4b, 0xce, 0x9c, 0x53, 0x99, 0xcb, 0xb7, 0x18, ++ 0x0f, 0x5e, 0xc5, 0xd1, 0xc3, 0xd3, 0xc4, 0xde, 0x73, 0x3c, 0x3e, 0xbc, ++ 0x07, 0x22, 0xfb, 0xce, 0x75, 0xd6, 0x6e, 0x9c, 0x1c, 0x5f, 0x9e, 0xbf, ++ 0xc5, 0xac, 0x0a, 0x23, 0xb3, 0x7b, 0x2e, 0xf4, 0xad, 0x21, 0xb5, 0x9b, ++ 0x3e, 0x2b, 0xeb, 0x26, 0x7a, 0xdb, 0x77, 0xc8, 0xdd, 0x4b, 0xc2, 0xf2, ++ 0x0e, 0xac, 0x1e, 0xb9, 0x83, 0xfa, 0x2e, 0x7a, 0xf8, 0x55, 0x38, 0x1f, ++ 0x76, 0xa2, 0x90, 0x39, 0x61, 0x30, 0x28, 0xdf, 0x10, 0x92, 0xef, 0xd5, ++ 0x64, 0xf4, 0x42, 0xf9, 0xae, 0x48, 0x62, 0x8a, 0xb1, 0x3f, 0xb3, 0xb0, ++ 0x00, 0xf2, 0xce, 0xfd, 0xad, 0xe8, 0x18, 0x88, 0xa0, 0xc7, 0x94, 0xf7, ++ 0xc9, 0xb2, 0xe3, 0x9f, 0xdf, 0xf8, 0x2a, 0xb6, 0x33, 0xfe, 0xac, 0x23, ++ 0x26, 0xae, 0xb5, 0x9f, 0x15, 0xbd, 0x8a, 0xde, 0xe1, 0x97, 0xdd, 0xc2, ++ 0x77, 0x7a, 0x4d, 0xc9, 0x33, 0x75, 0xf3, 0x83, 0xdf, 0x2b, 0x5a, 0x20, ++ 0xfb, 0x10, 0x69, 0x13, 0x99, 0x85, 0x2e, 0x14, 0xcf, 0xca, 0x7e, 0x33, ++ 0xe7, 0xa3, 0xbe, 0x2f, 0xf5, 0x71, 0xfb, 0xfb, 0x52, 0xb2, 0x17, 0x43, ++ 0xbe, 0x4d, 0xf6, 0x74, 0x5c, 0xbe, 0x19, 0xa2, 0x36, 0xb9, 0xa0, 0x7a, ++ 0x5c, 0xe4, 0x85, 0xe7, 0xcd, 0xd9, 0xd8, 0xee, 0xb1, 0x70, 0x1b, 0x65, ++ 0x39, 0xd6, 0xf0, 0x69, 0xa0, 0x32, 0xd6, 0xee, 0xb2, 0xbf, 0x43, 0x53, ++ 0xfd, 0xf9, 0x3f, 0xfc, 0x0e, 0xcd, 0x5b, 0xc4, 0x49, 0x59, 0x2f, 0xbb, ++ 0x1b, 0x67, 0xec, 0x98, 0xa0, 0xa0, 0xa4, 0xd6, 0xb2, 0xb6, 0x06, 0x7d, ++ 0x78, 0xde, 0xa8, 0xf7, 0x55, 0xca, 0xb3, 0x0d, 0xe5, 0x82, 0x15, 0xf3, ++ 0x54, 0x33, 0xbe, 0xfc, 0x5b, 0xef, 0x4f, 0xbc, 0x84, 0x5d, 0xfb, 0x42, ++ 0xe4, 0x8c, 0x1e, 0xca, 0xff, 0xc2, 0xac, 0xfc, 0x7b, 0xb7, 0x3b, 0xed, ++ 0xdc, 0xa3, 0x8a, 0xe0, 0xf2, 0x16, 0xfd, 0xec, 0x2d, 0xfb, 0xf9, 0xad, ++ 0xdb, 0xf8, 0x33, 0x04, 0x2a, 0x67, 0x65, 0xdf, 0x89, 0xb3, 0xf7, 0x67, ++ 0xcb, 0xb7, 0x59, 0x8a, 0x73, 0x75, 0xa4, 0xac, 0xd4, 0x7b, 0xcb, 0x7e, ++ 0x66, 0xec, 0x32, 0xde, 0xb5, 0xde, 0xf0, 0x54, 0xb1, 0xec, 0x7f, 0xcd, ++ 0xdd, 0xbf, 0x28, 0x3e, 0x63, 0x46, 0x20, 0xd7, 0xa4, 0x8e, 0xe8, 0xea, ++ 0x6a, 0x9d, 0xed, 0x49, 0x07, 0x71, 0xef, 0xac, 0xd5, 0xed, 0x91, 0x31, ++ 0x2c, 0xfc, 0x50, 0x9d, 0xec, 0x73, 0xb8, 0xac, 0x7e, 0x45, 0x9e, 0x3f, ++ 0xec, 0x33, 0x69, 0xaf, 0x57, 0x96, 0xe0, 0x42, 0x65, 0x76, 0x6d, 0xe1, ++ 0xaa, 0x8c, 0x37, 0xcc, 0x96, 0xbd, 0x9a, 0x85, 0xf6, 0xb9, 0xdd, 0xaf, ++ 0x79, 0xb5, 0x5e, 0xc8, 0x93, 0x6b, 0xc7, 0x7e, 0x2f, 0xed, 0x11, 0x9b, ++ 0xd7, 0x38, 0x66, 0x8c, 0xfb, 0x29, 0xcf, 0x07, 0xfb, 0x99, 0x9b, 0xeb, ++ 0x57, 0xb5, 0xdf, 0xed, 0xbb, 0xda, 0x87, 0xc8, 0xb5, 0x32, 0x57, 0x47, ++ 0x0f, 0x45, 0xec, 0xfe, 0x55, 0x84, 0xf6, 0xe7, 0xfb, 0xa4, 0x3f, 0x2d, ++ 0xce, 0xb7, 0x31, 0x25, 0xf6, 0xd5, 0x5d, 0xc8, 0xd8, 0x74, 0xa1, 0x71, ++ 0x1b, 0x76, 0xc4, 0x45, 0xcf, 0xf2, 0xbd, 0x52, 0x62, 0xb0, 0xcd, 0xb5, ++ 0x5c, 0xf4, 0xb7, 0x1b, 0x31, 0xaa, 0xc5, 0x70, 0xa8, 0x41, 0x9e, 0x49, ++ 0xb8, 0x68, 0xd3, 0x31, 0x14, 0x91, 0xdb, 0x46, 0x78, 0x4d, 0xf6, 0x21, ++ 0x1d, 0x35, 0xf5, 0xc8, 0xd3, 0xf8, 0x0a, 0x1c, 0xd7, 0xdb, 0x6b, 0x2f, ++ 0xad, 0xa3, 0x90, 0xeb, 0x26, 0x73, 0x93, 0x99, 0x2b, 0x15, 0x45, 0xb4, ++ 0x1d, 0x7b, 0xff, 0xbc, 0x29, 0xef, 0x69, 0xf6, 0xc7, 0xe5, 0x7d, 0xc1, ++ 0xfa, 0x28, 0xf9, 0x21, 0xce, 0xa4, 0x64, 0xcf, 0xca, 0x6f, 0xac, 0xd8, ++ 0x6c, 0xd9, 0x1b, 0x3b, 0xb3, 0x4e, 0x01, 0x71, 0xc9, 0x1f, 0x2a, 0x57, ++ 0xfe, 0xf0, 0xd9, 0xc7, 0x5d, 0xb4, 0x99, 0x8b, 0xf6, 0x7b, 0x9e, 0x72, ++ 0x16, 0x46, 0x73, 0x52, 0xbe, 0xbb, 0xa9, 0x4f, 0xad, 0x40, 0x7d, 0xa6, ++ 0xc6, 0xe1, 0xcc, 0xf1, 0x8f, 0x10, 0x56, 0xd2, 0x6e, 0x76, 0xfa, 0x43, ++ 0xf6, 0xfb, 0x8c, 0xf2, 0x7d, 0x95, 0xc7, 0xa0, 0x77, 0xfe, 0x84, 0xe5, ++ 0x3f, 0x9d, 0x7e, 0xc9, 0x1a, 0xf5, 0xc8, 0x98, 0xf2, 0x3e, 0x2e, 0xcf, ++ 0xd9, 0xa9, 0xc7, 0xb0, 0xf8, 0x47, 0x29, 0x2a, 0xc3, 0x21, 0xfa, 0xa1, ++ 0xc4, 0x6f, 0x79, 0x17, 0x52, 0x3f, 0x20, 0x79, 0x55, 0x73, 0x5a, 0xde, ++ 0xf5, 0x97, 0xbd, 0xee, 0xba, 0x6f, 0x95, 0x23, 0x90, 0xdb, 0x73, 0x9e, ++ 0x8f, 0xf7, 0xbd, 0xb3, 0x73, 0xfb, 0xe1, 0x99, 0x07, 0xae, 0x64, 0x1e, ++ 0x28, 0xd8, 0xd0, 0x61, 0x63, 0x83, 0x66, 0xe8, 0xc7, 0x7e, 0xe9, 0xe8, ++ 0xc6, 0xb7, 0x17, 0x19, 0x5d, 0xc7, 0xd5, 0xcc, 0xa8, 0x97, 0x38, 0x71, ++ 0x8b, 0x23, 0x32, 0xc8, 0xff, 0xbe, 0xef, 0x11, 0x9b, 0xef, 0xb2, 0xeb, ++ 0xea, 0x81, 0xd5, 0x6a, 0xfe, 0x3d, 0x7a, 0x79, 0x4f, 0x46, 0x6f, 0xff, ++ 0x86, 0xd2, 0x8d, 0x2d, 0x41, 0xa3, 0x6d, 0xab, 0xa2, 0xb7, 0xfe, 0xad, ++ 0xa2, 0xfb, 0x82, 0x8a, 0x94, 0xb3, 0xbf, 0x97, 0x74, 0x25, 0x76, 0xba, ++ 0xd8, 0xc7, 0x91, 0xb8, 0x1e, 0x9a, 0xc5, 0xb2, 0x17, 0x4c, 0xc3, 0x7b, ++ 0x89, 0x6d, 0xfe, 0x90, 0xc7, 0x20, 0x02, 0x58, 0x6a, 0xb7, 0x1b, 0x59, ++ 0xe8, 0xb2, 0xbf, 0x99, 0xdb, 0xce, 0x98, 0x20, 0xeb, 0x28, 0x51, 0x68, ++ 0x89, 0x6a, 0x9a, 0x90, 0xde, 0xf7, 0x19, 0xc4, 0xac, 0xd9, 0x46, 0xe1, ++ 0x1c, 0x14, 0x97, 0xc2, 0x13, 0xee, 0x46, 0xed, 0x22, 0xc3, 0xbb, 0x44, ++ 0xb5, 0xeb, 0x07, 0xe4, 0x5b, 0x50, 0x4b, 0x39, 0xce, 0x61, 0x48, 0x1b, ++ 0x19, 0x4b, 0xab, 0xad, 0xb0, 0xeb, 0x2c, 0x52, 0x3f, 0x05, 0xd7, 0x27, ++ 0x7e, 0x65, 0x8d, 0x6a, 0xd0, 0xaa, 0x0c, 0xa9, 0x13, 0x1b, 0xd4, 0xf0, ++ 0x6f, 0xd5, 0x13, 0x5c, 0xf9, 0xa5, 0x85, 0x39, 0x52, 0x4f, 0x9e, 0x3b, ++ 0xad, 0xb1, 0x9f, 0x3b, 0x15, 0x1b, 0xe2, 0x8f, 0x7a, 0xe4, 0xcb, 0xe4, ++ 0x9a, 0xc5, 0x4a, 0xf6, 0x99, 0xb0, 0x33, 0xbc, 0x8e, 0x78, 0xd6, 0x0d, ++ 0x2d, 0xa8, 0xf7, 0x5d, 0xab, 0xca, 0xf7, 0xa4, 0xbe, 0x27, 0x7b, 0xad, ++ 0x0e, 0xd4, 0xa9, 0xd9, 0x3d, 0x59, 0xd1, 0x3f, 0xfa, 0x6d, 0x2a, 0xf6, ++ 0x55, 0x2c, 0xcf, 0xf2, 0xab, 0xed, 0x77, 0x8a, 0xd6, 0xc5, 0x1d, 0xb9, ++ 0x3d, 0xa6, 0x57, 0xbf, 0xd9, 0xda, 0x41, 0x5e, 0xbf, 0x41, 0xbe, 0xcf, ++ 0xc8, 0xb1, 0x6e, 0x8c, 0xcb, 0x32, 0xda, 0xff, 0x03, 0x23, 0xa0, 0xef, ++ 0xde, 0xe4, 0x58, 0x00, 0x00, 0x00 }; + + static const u32 bnx2_CP_b06FwData[(0x84/4) + 1] = { + 0x00000000, 0x0000001b, 0x0000000f, 0x0000000a, 0x00000008, 0x00000006, +@@ -2136,50 +2151,52 @@ + 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, + 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, + 0x00000001, 0x00000001, 0x00000001, 0x00000000 }; +-static const u32 bnx2_CP_b06FwRodata[(0x130/4) + 1] = { +- 0x08001f1c, 0x08001da8, 0x08001ef8, 0x08001ed4, 0x08001eb0, 0x08001e8c, +- 0x08001e64, 0x08001e3c, 0x08001e10, 0x08002014, 0x08002004, 0x08001dc4, +- 0x08001dc4, 0x08001dc4, 0x08001f44, 0x08001f44, 0x08001dc4, 0x08001dc4, +- 0x08001ff4, 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001fe4, +- 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, +- 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, +- 0x08001dc4, 0x08001dc4, 0x08001fd4, 0x08001dc4, 0x08001dc4, 0x08001fc4, +- 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, +- 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, +- 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001dc4, 0x08001fac, +- 0x08001dc4, 0x08001dc4, 0x08001f9c, 0x08001f8c, 0x080031e8, 0x080031f0, +- 0x080031b8, 0x080031c4, 0x080031d0, 0x080031dc, 0x08005644, 0x08005604, +- 0x080055d0, 0x080055a4, 0x08005580, 0x0800553c, 0x00000000 }; ++static const u32 bnx2_CP_b06FwRodata[(0x154/4) + 1] = { ++ 0x08000f58, 0x08000db0, 0x08000fec, 0x08001094, 0x08000f80, 0x08000fc0, ++ 0x080011cc, 0x08000dcc, 0x080011f0, 0x08000e1c, 0x080014c0, 0x08001468, ++ 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x0800127c, 0x0800127c, 0x08000dcc, ++ 0x08000dcc, 0x08001708, 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, ++ 0x080013fc, 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, ++ 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, ++ 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000fe0, 0x08000dcc, 0x08000dcc, ++ 0x080016b8, 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, ++ 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, ++ 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, 0x08000dcc, ++ 0x080015e4, 0x08000dcc, 0x08000dcc, 0x08001370, 0x080012e0, 0x08002eb0, ++ 0x08002eb8, 0x08002e80, 0x08002e8c, 0x08002e98, 0x08002ea4, 0x080046d0, ++ 0x08003f1c, 0x08004650, 0x080046d0, 0x080046d0, 0x080044d0, 0x080046d0, ++ 0x08004718, 0x08005540, 0x08005500, 0x080054cc, 0x080054a0, 0x0800547c, ++ 0x08005438, 0x00000000 }; + + static struct fw_info bnx2_cp_fw_06 = { +- /* Firmware version: 4.0.5 */ +- .ver_major = 0x4, +- .ver_minor = 0x0, +- .ver_fix = 0x5, +- +- .start_addr = 0x08000078, ++ /* Firmware version: 5.0.0j */ ++ .ver_major = 0x5, ++ .ver_minor = 0x0, ++ .ver_fix = 0x0, ++ ++ .start_addr = 0x08000088, + + .text_addr = 0x08000000, +- .text_len = 0x59e4, ++ .text_len = 0x58e0, + .text_index = 0x0, + .gz_text = bnx2_CP_b06FwText, + .gz_text_len = sizeof(bnx2_CP_b06FwText), + +- .data_addr = 0x08005b40, ++ .data_addr = 0x08005a60, + .data_len = 0x84, + .data_index = 0x0, + .data = bnx2_CP_b06FwData, + +- .sbss_addr = 0x08005bc4, +- .sbss_len = 0xe9, +- .sbss_index = 0x0, +- +- .bss_addr = 0x08005cb0, ++ .sbss_addr = 0x08005ae4, ++ .sbss_len = 0xf1, ++ .sbss_index = 0x0, ++ ++ .bss_addr = 0x08005bd8, + .bss_len = 0x5d8, + .bss_index = 0x0, + +- .rodata_addr = 0x080059e4, +- .rodata_len = 0x130, ++ .rodata_addr = 0x080058e0, ++ .rodata_len = 0x154, + .rodata_index = 0x0, + .rodata = bnx2_CP_b06FwRodata, + }; +@@ -2201,761 +2218,755 @@ + }; + + static u8 bnx2_RXP_b06FwText[] = { +- 0xec, 0x5b, 0x5d, 0x70, 0x5c, 0xd7, 0x5d, 0xff, 0xdf, 0xb3, 0x2b, 0x69, +- 0x2d, 0x4b, 0xf2, 0x95, 0xbc, 0x71, 0x56, 0xa9, 0x92, 0xec, 0x5a, 0x57, +- 0xd2, 0xa6, 0x12, 0xe1, 0xca, 0x6c, 0x12, 0x75, 0xd8, 0x69, 0xb6, 0xbb, +- 0xb2, 0xa3, 0xb4, 0x66, 0x46, 0x49, 0x0d, 0xcd, 0xb4, 0x65, 0x10, 0xbb, +- 0x0e, 0xa4, 0x0f, 0x0c, 0xc6, 0x40, 0x26, 0x80, 0xc1, 0xcb, 0x4a, 0x71, +- 0x94, 0x74, 0xad, 0xdd, 0xda, 0x0a, 0x86, 0x69, 0x61, 0x94, 0xd5, 0x87, +- 0x53, 0x66, 0xad, 0x4d, 0xcb, 0x4b, 0x99, 0xd6, 0xb1, 0xea, 0xb8, 0x26, +- 0x0f, 0x3c, 0xa4, 0x94, 0xce, 0x64, 0x20, 0x33, 0x35, 0xb2, 0x63, 0xfb, +- 0x81, 0x8f, 0xc0, 0x4c, 0x49, 0x20, 0x6e, 0x2e, 0xbf, 0xdf, 0xb9, 0xf7, +- 0xca, 0x2b, 0x45, 0xd0, 0x3c, 0xf0, 0x78, 0xcf, 0x8c, 0xe6, 0xde, 0x7b, +- 0xce, 0xff, 0xfc, 0xcf, 0xff, 0xfb, 0xe3, 0xac, 0xfd, 0x3b, 0x1d, 0xd2, +- 0x2e, 0xde, 0xe8, 0xc4, 0x5f, 0xea, 0xc8, 0x33, 0x47, 0x47, 0xef, 0x1f, +- 0xbd, 0x9f, 0xdf, 0x21, 0xc3, 0x08, 0xf3, 0x69, 0x48, 0x30, 0x82, 0x11, +- 0x8c, 0x60, 0x04, 0x23, 0x18, 0xc1, 0x08, 0x46, 0x30, 0x82, 0x11, 0x8c, +- 0x60, 0x04, 0x23, 0x18, 0xc1, 0x08, 0x46, 0x30, 0x82, 0x11, 0x8c, 0x60, +- 0x04, 0x23, 0x18, 0xc1, 0x08, 0x46, 0x30, 0x82, 0x11, 0x8c, 0x60, 0x04, +- 0x23, 0x18, 0xc1, 0x08, 0x46, 0x30, 0x82, 0x11, 0x8c, 0x60, 0x04, 0x23, +- 0x18, 0xc1, 0x08, 0x46, 0x30, 0x82, 0x11, 0x8c, 0x60, 0x04, 0x23, 0x18, +- 0xc1, 0x08, 0x46, 0x30, 0xfe, 0x3f, 0x47, 0x48, 0xc4, 0xe4, 0xb3, 0xd3, +- 0xfb, 0x93, 0x88, 0x4a, 0xc7, 0x8f, 0x66, 0x2d, 0x89, 0x84, 0xd2, 0x97, +- 0x9e, 0x2e, 0x58, 0x22, 0x99, 0xfa, 0x70, 0x3c, 0x27, 0x3f, 0x71, 0x8a, +- 0xd1, 0xb0, 0x70, 0xfe, 0xee, 0xf4, 0xad, 0xe3, 0xe7, 0x1f, 0x4a, 0xbc, +- 0xb3, 0x10, 0x92, 0x88, 0x99, 0x7e, 0x63, 0xd4, 0x1c, 0x94, 0x48, 0x1f, +- 0xf6, 0x7c, 0x6d, 0x68, 0x6d, 0x97, 0x74, 0xf9, 0xb8, 0x44, 0x6a, 0xe5, +- 0x84, 0x7d, 0x40, 0x86, 0xcd, 0x8b, 0x12, 0x96, 0x0c, 0xce, 0x58, 0xa9, +- 0x8b, 0x94, 0xca, 0x06, 0x71, 0x48, 0xa9, 0x1e, 0x91, 0x2b, 0x21, 0x42, +- 0x7d, 0xcb, 0xc8, 0x56, 0x3e, 0x70, 0x32, 0x61, 0x9c, 0x6b, 0xe1, 0xbd, +- 0xe1, 0xcf, 0x47, 0x44, 0xa5, 0x13, 0xc9, 0x6c, 0x68, 0x42, 0x6a, 0xf3, +- 0x8e, 0x33, 0x63, 0x7f, 0x0c, 0x38, 0x7a, 0x64, 0xc6, 0x72, 0xbf, 0xb3, +- 0xf6, 0xc7, 0xcd, 0x71, 0xb9, 0x13, 0x73, 0x21, 0x51, 0xd6, 0x5d, 0xf8, +- 0x8b, 0x1b, 0xb9, 0xd3, 0x5f, 0x36, 0xb2, 0x8b, 0x1d, 0x52, 0xaa, 0x38, +- 0x52, 0xb0, 0x25, 0x93, 0xb5, 0x77, 0x60, 0xfd, 0x03, 0xa7, 0xb0, 0xb1, +- 0x67, 0xd8, 0xcc, 0x49, 0x8b, 0x64, 0xa2, 0x31, 0xc0, 0xcc, 0x1b, 0xb9, +- 0xb3, 0x7f, 0xdd, 0x21, 0xed, 0xa0, 0x27, 0xc5, 0xef, 0x0f, 0x9c, 0x90, +- 0x65, 0x61, 0x9d, 0xe7, 0xe3, 0xbb, 0x41, 0xbc, 0x7c, 0x27, 0xce, 0x2b, +- 0xce, 0xf9, 0xa1, 0x98, 0x7c, 0xb3, 0x11, 0x95, 0x6f, 0x34, 0x4c, 0x79, +- 0xa5, 0xd1, 0x27, 0x17, 0x1a, 0x8e, 0xf3, 0x0d, 0xdb, 0x71, 0xde, 0xc0, +- 0xdf, 0x7f, 0xd8, 0x1b, 0x3c, 0x60, 0x14, 0x8d, 0xf1, 0xc6, 0x57, 0x3b, +- 0xa4, 0x2b, 0x11, 0x17, 0xd5, 0x21, 0xd3, 0x95, 0x98, 0xcc, 0x54, 0xca, +- 0xc6, 0x63, 0x67, 0xe7, 0x8c, 0xc9, 0xb3, 0x55, 0x9c, 0x19, 0xc6, 0x9c, +- 0x14, 0x4b, 0xf6, 0xcb, 0x46, 0xae, 0x31, 0x6b, 0x3c, 0x7e, 0xb6, 0x0b, +- 0x34, 0xf2, 0xfc, 0x3d, 0x46, 0xf6, 0xf4, 0x2d, 0xc9, 0xda, 0x94, 0x71, +- 0xc2, 0xfc, 0x3c, 0xc4, 0x9e, 0x2d, 0x93, 0xe6, 0x56, 0x8f, 0x5e, 0xc7, +- 0x51, 0x69, 0xe7, 0x78, 0x36, 0x65, 0x99, 0x25, 0x21, 0x7d, 0x7a, 0xee, +- 0x82, 0x4b, 0xf3, 0x8a, 0x91, 0x3d, 0xdb, 0x61, 0xe4, 0xce, 0x84, 0x41, +- 0x87, 0xf4, 0x85, 0x84, 0xfb, 0x06, 0x62, 0x79, 0xa9, 0xe3, 0x0c, 0x31, +- 0x55, 0x9a, 0x72, 0x05, 0xcd, 0xa0, 0xe5, 0x9b, 0x15, 0xf0, 0x50, 0x01, +- 0x0f, 0x15, 0xf2, 0x16, 0x97, 0xf3, 0x43, 0x3e, 0x6f, 0x8e, 0xf3, 0x77, +- 0x36, 0x69, 0x4f, 0xc4, 0x33, 0xca, 0xe7, 0xd3, 0x71, 0xfe, 0xdd, 0x26, +- 0xaf, 0xe4, 0xc7, 0x71, 0x5e, 0xb1, 0x63, 0xa0, 0xdd, 0xb9, 0xa0, 0xac, +- 0x32, 0x78, 0xb1, 0x80, 0x9f, 0xb2, 0x9e, 0x03, 0x0f, 0xb3, 0xe0, 0x6f, +- 0x05, 0xbc, 0x55, 0x41, 0xc7, 0x4f, 0x3b, 0xaf, 0x68, 0xe4, 0x86, 0x36, +- 0xe4, 0x15, 0xa7, 0x8c, 0xf3, 0x4b, 0x0a, 0xb2, 0xde, 0x29, 0xf9, 0x05, +- 0x53, 0xa6, 0x96, 0xfc, 0xfd, 0xbe, 0x1d, 0x1c, 0x91, 0x83, 0x95, 0x1e, +- 0xc8, 0x86, 0xb2, 0x4c, 0xd8, 0x22, 0x0e, 0x64, 0x54, 0x4a, 0x2a, 0x11, +- 0x23, 0x6f, 0x1f, 0xd7, 0xfa, 0x5f, 0xb2, 0x24, 0x93, 0xb7, 0x29, 0x47, +- 0x89, 0xe7, 0xed, 0x62, 0x2c, 0x0c, 0x7b, 0x5b, 0xb2, 0x8a, 0x66, 0x58, +- 0x28, 0xc7, 0x44, 0xec, 0xf7, 0x21, 0xcb, 0x27, 0xcb, 0x92, 0xf9, 0x74, +- 0xd9, 0x97, 0xb1, 0x2b, 0xdf, 0xcf, 0x94, 0x3f, 0xd5, 0x29, 0xed, 0xea, +- 0x9e, 0x16, 0xf9, 0x0d, 0xec, 0x25, 0xee, 0x4d, 0x7b, 0xb1, 0xcf, 0x85, +- 0x73, 0xf7, 0x26, 0x9e, 0x10, 0x21, 0x6c, 0xa9, 0xbf, 0x45, 0xfb, 0x88, +- 0x18, 0x59, 0xab, 0x18, 0x0b, 0x01, 0x2e, 0x2f, 0xa5, 0x51, 0x6f, 0xae, +- 0x25, 0x6b, 0xdd, 0x0a, 0xcd, 0xd8, 0x89, 0x78, 0x49, 0x6e, 0x85, 0x2e, +- 0xdb, 0x7a, 0x6e, 0x47, 0xd6, 0x72, 0x64, 0x19, 0xd8, 0x9f, 0x83, 0x3f, +- 0x5c, 0x04, 0x47, 0x5f, 0x2a, 0xeb, 0xf9, 0x4e, 0xec, 0x4f, 0xb6, 0x00, +- 0x67, 0xbb, 0x24, 0x92, 0x35, 0xcc, 0x5f, 0x76, 0xe7, 0xbb, 0x5d, 0xbc, +- 0xa5, 0xfe, 0x76, 0x8d, 0x5b, 0xe4, 0x65, 0x77, 0xfe, 0x0e, 0x17, 0x77, +- 0xe9, 0x3e, 0xcc, 0x03, 0xff, 0xe0, 0xc4, 0x90, 0xa1, 0xe7, 0x7b, 0xe9, +- 0x4f, 0xbf, 0x5e, 0xbe, 0x15, 0x5a, 0xb6, 0x1d, 0xc9, 0x8d, 0x0e, 0x4e, +- 0x0c, 0x1a, 0x2e, 0xbe, 0x13, 0xee, 0xbe, 0xbb, 0x5d, 0x7c, 0x83, 0x13, +- 0x49, 0xc3, 0xc5, 0xb7, 0x54, 0xd6, 0x7b, 0x25, 0x5f, 0x26, 0xec, 0xe0, +- 0x84, 0x65, 0xdc, 0x2d, 0x53, 0xdd, 0x83, 0x13, 0x7b, 0x0d, 0x75, 0xcf, +- 0x4e, 0x97, 0x8f, 0x84, 0x4f, 0xc3, 0x4e, 0x4d, 0x03, 0xcf, 0xd5, 0xf3, +- 0x03, 0x59, 0xab, 0x74, 0xdf, 0x4e, 0x7d, 0x3e, 0xcf, 0xd4, 0x73, 0xf7, +- 0x91, 0x2e, 0x9e, 0x5d, 0x18, 0xdd, 0x74, 0xee, 0xcf, 0xdc, 0x96, 0xcf, +- 0x76, 0x67, 0xf2, 0x3c, 0x89, 0x84, 0xd3, 0xe1, 0xd1, 0x99, 0xf2, 0x11, +- 0xc9, 0x56, 0xe2, 0x32, 0x3d, 0xb2, 0x43, 0xa6, 0xcc, 0xfe, 0xa9, 0x83, +- 0xc2, 0xd8, 0x13, 0x19, 0x2d, 0x78, 0x3a, 0xcc, 0x89, 0x21, 0xd3, 0xe0, +- 0xf1, 0x60, 0x5d, 0x22, 0x06, 0xe0, 0xfb, 0xeb, 0x61, 0x79, 0xbe, 0x61, +- 0x48, 0xab, 0xf6, 0xcf, 0x84, 0xb9, 0x06, 0x3b, 0x7c, 0xb6, 0x42, 0x3b, +- 0xa6, 0xcd, 0x4a, 0xa6, 0x06, 0x3b, 0xbd, 0xa0, 0x7d, 0xb5, 0x9d, 0x7a, +- 0x2d, 0x16, 0x05, 0xae, 0x98, 0xb6, 0xcc, 0x9a, 0xb4, 0x49, 0x66, 0x52, +- 0x8a, 0x5c, 0xf7, 0x7c, 0x27, 0xb6, 0x28, 0xdf, 0x85, 0x0d, 0x88, 0x99, +- 0x4d, 0x71, 0x9e, 0xf0, 0x4d, 0xb0, 0xa6, 0xeb, 0x77, 0x21, 0xf8, 0x5d, +- 0x21, 0x45, 0x58, 0x29, 0xea, 0x58, 0xd1, 0x80, 0x2d, 0x36, 0xee, 0xee, +- 0x74, 0x63, 0x5d, 0x04, 0xfe, 0xd9, 0x01, 0x1f, 0xbf, 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0x1b, +- 0x1f, 0xc5, 0x8c, 0x4b, 0x85, 0xcd, 0xb0, 0x0f, 0x92, 0xba, 0x04, 0xff, +- 0xe7, 0x52, 0xa9, 0x07, 0x7c, 0x86, 0xfb, 0x25, 0x07, 0xbf, 0xd0, 0x99, +- 0xa5, 0x01, 0xc8, 0x39, 0xf7, 0x62, 0xcb, 0xc2, 0x56, 0x9c, 0x1d, 0x71, +- 0x44, 0x8a, 0x1f, 0xff, 0x2f, 0xce, 0xd7, 0x7f, 0xef, 0x1d, 0x6a, 0xa7, +- 0xe7, 0x75, 0x5f, 0xb0, 0xcb, 0x88, 0x01, 0xb2, 0xfd, 0xc6, 0x6e, 0xa7, +- 0x23, 0x6d, 0x92, 0xbe, 0x9b, 0x76, 0xbc, 0x5d, 0x63, 0x44, 0xe5, 0xc5, +- 0x08, 0xef, 0xbf, 0xb3, 0xd1, 0xd0, 0x2f, 0x5c, 0xd7, 0xbe, 0x8e, 0xdf, +- 0x56, 0xe9, 0x70, 0xf8, 0x6b, 0xe3, 0xf7, 0xed, 0x8d, 0xac, 0xef, 0x76, +- 0x38, 0x49, 0xac, 0xf5, 0x5b, 0x2f, 0x5f, 0x80, 0xeb, 0x79, 0x3e, 0xb3, +- 0xc1, 0x5b, 0x97, 0xf3, 0xb6, 0x62, 0x9e, 0x16, 0x6f, 0xad, 0x56, 0xcd, +- 0x4f, 0x9a, 0xb5, 0x10, 0xe3, 0x16, 0xfe, 0xb2, 0x51, 0xbf, 0x35, 0x86, +- 0xbd, 0xa8, 0x6d, 0xff, 0x79, 0x23, 0x71, 0x73, 0x1d, 0x4e, 0xab, 0x62, +- 0x3c, 0x6f, 0xb6, 0xb7, 0xe3, 0x9a, 0x6b, 0x72, 0x8c, 0xc9, 0x87, 0xcf, +- 0x95, 0x38, 0x3f, 0xdb, 0x29, 0x39, 0xa1, 0xf9, 0x0c, 0x83, 0xe5, 0x9b, +- 0x2b, 0xdc, 0x2f, 0x13, 0xe7, 0x15, 0x5f, 0x37, 0x93, 0xb7, 0xf8, 0xdd, +- 0x0b, 0xbf, 0x97, 0xa3, 0x2f, 0x31, 0x26, 0x07, 0x71, 0x7e, 0x97, 0xe1, +- 0x53, 0x2d, 0x99, 0xef, 0x62, 0xf1, 0x77, 0x00, 0xe7, 0x12, 0x82, 0x8c, +- 0x51, 0x46, 0x29, 0x53, 0x38, 0xbf, 0x71, 0x5b, 0xde, 0x1d, 0xa0, 0x3c, +- 0x0f, 0xc8, 0x95, 0x8a, 0x3c, 0xe7, 0x20, 0xcf, 0x94, 0xe5, 0x1c, 0x64, +- 0xda, 0xf0, 0xf5, 0x7e, 0x7e, 0x67, 0x1d, 0x83, 0xbd, 0x52, 0x1f, 0xe2, +- 0x25, 0xf0, 0xb5, 0xed, 0x7d, 0x2b, 0x15, 0xd0, 0x1c, 0x4e, 0x76, 0xb6, +- 0xc1, 0xfb, 0x0e, 0x00, 0xd7, 0x57, 0x9e, 0x93, 0xf4, 0x6c, 0x33, 0xbf, +- 0xe7, 0xea, 0xe2, 0x99, 0x65, 0xaf, 0xf0, 0xdf, 0xe7, 0x45, 0xe2, 0x4d, +- 0xe9, 0xcf, 0xf2, 0x9a, 0x71, 0xde, 0x26, 0x8c, 0x19, 0x04, 0x9d, 0x9b, +- 0x31, 0x3f, 0xf7, 0xb8, 0xda, 0x38, 0xde, 0x0f, 0x55, 0xe1, 0x53, 0x7d, +- 0x7a, 0xaf, 0xd5, 0x35, 0xb3, 0xfd, 0xcd, 0xde, 0xfb, 0xf1, 0x1c, 0x94, +- 0xef, 0xc1, 0xb7, 0xf4, 0x89, 0xc9, 0x2f, 0x29, 0x3d, 0x87, 0xb9, 0x02, +- 0xf9, 0x37, 0xa4, 0x39, 0x8c, 0x2c, 0x6c, 0xcb, 0x5e, 0x1d, 0x1f, 0x5b, +- 0x91, 0xef, 0xae, 0x80, 0xc6, 0xdd, 0xd9, 0xc2, 0x1a, 0xe9, 0x56, 0x1d, +- 0xd4, 0xe5, 0xf1, 0x36, 0xec, 0x85, 0x62, 0xb9, 0x0f, 0xc8, 0xf1, 0xd2, +- 0x20, 0xe8, 0x10, 0x93, 0xa7, 0xe0, 0x37, 0x3f, 0x53, 0xba, 0x43, 0x96, +- 0x23, 0xd8, 0x57, 0x45, 0xc6, 0x86, 0xe5, 0xfb, 0xf3, 0x09, 0xef, 0x3a, +- 0xe1, 0x2e, 0x5b, 0x3b, 0xb0, 0x07, 0xca, 0x13, 0xe5, 0x8a, 0xe3, 0x82, +- 0x88, 0x45, 0x38, 0xef, 0xd3, 0x46, 0xb7, 0x61, 0xde, 0x62, 0x84, 0xf2, +- 0xcb, 0xbd, 0x85, 0x3c, 0x99, 0x65, 0x5c, 0xc5, 0x77, 0x36, 0x36, 0x29, +- 0x53, 0x73, 0x16, 0x09, 0xc5, 0x81, 0xae, 0x9c, 0x81, 0x3f, 0x8f, 0x2f, +- 0x97, 0xfe, 0x77, 0x14, 0xd4, 0xa3, 0xb0, 0x95, 0x05, 0xd8, 0xca, 0x02, +- 0x6c, 0x24, 0x64, 0xe1, 0x5a, 0x01, 0x36, 0xb2, 0x00, 0x1b, 0x09, 0x7d, +- 0xf6, 0x3a, 0x62, 0xbb, 0xd7, 0xc0, 0x43, 0xc6, 0xd7, 0x3e, 0x4a, 0x5f, +- 0x1b, 0x7f, 0xff, 0x03, 0x4c, 0x03, 0x3a, 0xe1, 0xd4, 0x71, 0x00, 0x00, +- 0x00 }; ++ 0xec, 0x5c, 0x5d, 0x6c, 0x1c, 0xd7, 0x75, 0x3e, 0x33, 0xbb, 0x24, 0x57, ++ 0x14, 0x7f, 0x46, 0xd4, 0x9a, 0x5a, 0xc9, 0xb4, 0xb3, 0x4b, 0x8e, 0x44, ++ 0xd6, 0x64, 0xed, 0x11, 0xb1, 0x92, 0xd9, 0x74, 0x61, 0x8f, 0x87, 0x54, ++ 0x4c, 0x1b, 0x4a, 0x4d, 0xdb, 0x82, 0x6b, 0x24, 0x46, 0xbb, 0xd8, 0x95, ++ 0x1d, 0xa3, 0xc8, 0x83, 0xe5, 0xd4, 0x8e, 0xe3, 0xba, 0xd5, 0x66, 0x49, ++ 0x5b, 0xaa, 0xb3, 0xd2, 0xb0, 0x91, 0x60, 0x15, 0x48, 0x83, 0xd2, 0xfc, ++ 0x11, 0x15, 0x77, 0xe9, 0x91, 0xdc, 0xa4, 0x55, 0xd1, 0xca, 0x62, 0x25, ++ 0x59, 0xf5, 0x43, 0x5a, 0x04, 0x68, 0x50, 0xb8, 0x40, 0x90, 0x08, 0x54, ++ 0x2c, 0x1b, 0x28, 0xda, 0x1a, 0x09, 0x82, 0x2a, 0xb5, 0xa2, 0xe9, 0xf7, ++ 0xdd, 0x99, 0xa1, 0xd6, 0x84, 0x8a, 0xfa, 0xa5, 0x6f, 0x73, 0x01, 0x62, ++ 0xe6, 0xde, 0x39, 0xf7, 0xdc, 0x73, 0xce, 0x3d, 0xff, 0x2b, 0xfb, 0xf9, ++ 0x36, 0x69, 0x95, 0x70, 0xb4, 0xe3, 0x6f, 0xc7, 0x33, 0x2f, 0x3c, 0x6b, ++ 0xdd, 0x69, 0xdd, 0x89, 0xd7, 0xdf, 0x4b, 0x88, 0x34, 0x71, 0x5d, 0x93, ++ 0x78, 0xc4, 0x23, 0x1e, 0xf1, 0x88, 0x47, 0x3c, 0xe2, 0x11, 0x8f, 0x78, ++ 0xc4, 0x23, 0x1e, 0xf1, 0x88, 0x47, 0x3c, 0xe2, 0x11, 0x8f, 0x78, 0xc4, ++ 0x23, 0x1e, 0xf1, 0x88, 0x47, 0x3c, 0xe2, 0x11, 0x8f, 0x78, 0xc4, 0x23, ++ 0x1e, 0xf1, 0x88, 0x47, 0x3c, 0xe2, 0x11, 0x8f, 0x78, 0xc4, 0x23, 0x1e, ++ 0xf1, 0x88, 0x47, 0x3c, 0xe2, 0x11, 0x8f, 0x78, 0xc4, 0x23, 0x1e, 0xf1, ++ 0x88, 0x47, 0x3c, 0xe2, 0x11, 0x8f, 0x78, 0xfc, 0x7f, 0x8c, 0x84, 0x88, ++ 0xc1, 0x67, 0x7b, 0xf8, 0x27, 0x29, 0xbd, 0x50, 0xdc, 0xe7, 0x98, 0x92, ++ 0x4a, 0x14, 0xe4, 0xf9, 0xb2, 0x29, 0x62, 0xd7, 0x07, 0xb3, 0xa3, 0xf2, ++ 0x2b, 0xbf, 0x92, 0x4e, 0x0a, 0xd7, 0x6f, 0x2b, 0x5c, 0xdb, 0x7f, 0xe6, ++ 0xee, 0xdc, 0x47, 0x33, 0x09, 0x49, 0x19, 0x85, 0xf7, 0xb6, 0x1b, 0xdb, ++ 0x24, 0xd5, 0x83, 0x3d, 0x7f, 0xd6, 0xff, 0xef, 0x86, 0x74, 0x44, 0xb8, ++ 0x7c, 0x7f, 0xc1, 0xf2, 0xe5, 0xa2, 0x55, 0xd1, 0x46, 0xfb, 0x4f, 0x6b, ++ 0x8e, 0x7b, 0xdd, 0xb7, 0x93, 0xba, 0xe8, 0xc0, 0xb7, 0xb7, 0x9e, 0x92, ++ 0x27, 0xe7, 0x5b, 0xe5, 0xa9, 0x99, 0xf5, 0x52, 0x9a, 0x11, 0x43, 0x2f, ++ 0x64, 0xe4, 0x4b, 0x58, 0xbb, 0x94, 0x00, 0x9c, 0x27, 0xc5, 0x44, 0xe1, ++ 0xea, 0x43, 0xa5, 0x1a, 0xe1, 0x45, 0xd7, 0x0b, 0xcb, 0x0f, 0xed, 0xad, ++ 0x5f, 0x78, 0xa8, 0x54, 0x27, 0x1c, 0x61, 0xf0, 0xad, 0xde, 0x26, 0xd5, ++ 0xa3, 0x69, 0x79, 0xc5, 0xcc, 0x8d, 0xcc, 0x88, 0xbe, 0x51, 0x97, 0x8a, ++ 0xa1, 0x4b, 0xce, 0xae, 0xca, 0xa0, 0xf1, 0xae, 0xfc, 0xb6, 0xd8, 0x46, ++ 0xc0, 0xd9, 0xf9, 0xe9, 0x75, 0x52, 0x1a, 0x7a, 0x58, 0xec, 0x09, 0x4d, ++ 0xce, 0x4d, 0x57, 0x0c, 0x70, 0x0a, 0x9e, 0xda, 0xf6, 0x95, 0xcd, 0x9c, ++ 0x31, 0x8a, 0xef, 0x4e, 0x2d, 0x25, 0xb6, 0x82, 0xd4, 0x00, 0xdb, 0x0a, ++ 0xda, 0x3e, 0x2b, 0xa5, 0x34, 0xe7, 0x7d, 0x46, 0xb3, 0xd6, 0x2a, 0xce, ++ 0xd0, 0x4e, 0xb1, 0xd3, 0xba, 0x5c, 0x04, 0xcd, 0x2b, 0x35, 0xd1, 0x9c, ++ 0x3c, 0x9e, 0x75, 0x01, 0x2e, 0xc2, 0xeb, 0x72, 0x61, 0x3a, 0x21, 0xef, ++ 0x4c, 0x4b, 0x0f, 0xf0, 0x76, 0xeb, 0xb2, 0x95, 0x38, 0x7b, 0x93, 0x78, ++ 0x8e, 0xe1, 0x6f, 0x97, 0x24, 0xb1, 0x2f, 0x79, 0x33, 0x78, 0xc0, 0x72, ++ 0xcf, 0xcd, 0xe0, 0xdf, 0x68, 0x93, 0xd6, 0x14, 0xf6, 0x10, 0x1e, 0xcc, ++ 0x9b, 0xdd, 0xa0, 0x27, 0x38, 0x9f, 0x38, 0x2e, 0x4c, 0x8b, 0x5c, 0xae, ++ 0x49, 0x97, 0xae, 0xf6, 0x24, 0xa5, 0x9c, 0xe7, 0xb7, 0x36, 0xc0, 0xbf, ++ 0xa1, 0xfe, 0xfb, 0x9c, 0xcb, 0x6a, 0x5f, 0x02, 0xfb, 0x52, 0xab, 0xfb, ++ 0x40, 0x37, 0xd6, 0x34, 0xbc, 0xa7, 0xc4, 0xc9, 0x1b, 0x72, 0x79, 0x26, ++ 0x80, 0x5d, 0x51, 0xf2, 0xd6, 0x00, 0x1b, 0xd0, 0xa6, 0x9b, 0xba, 0x94, ++ 0x20, 0xc5, 0x0b, 0x66, 0x2e, 0x2b, 0x1a, 0x61, 0x72, 0x56, 0x45, 0xf8, ++ 0xe4, 0x5e, 0xca, 0x2f, 0x58, 0x3b, 0x27, 0xdc, 0x97, 0x83, 0x84, 0x3f, ++ 0xf4, 0xcf, 0xf4, 0xa7, 0xe5, 0xac, 0x67, 0xc8, 0x49, 0xef, 0xfa, 0x06, ++ 0xe9, 0xc8, 0x55, 0x2a, 0xd2, 0x24, 0xa5, 0x23, 0xd7, 0xfd, 0x04, 0x71, ++ 0xe8, 0x26, 0xf8, 0xc3, 0x77, 0x17, 0xdf, 0x5d, 0xac, 0xcf, 0xb5, 0x74, ++ 0x49, 0x6b, 0x46, 0xce, 0xf4, 0x73, 0x1f, 0xf7, 0x70, 0x6f, 0xa6, 0x33, ++ 0xd8, 0x27, 0xd8, 0x37, 0x21, 0x09, 0xd3, 0x17, 0xc7, 0x4a, 0xca, 0x68, ++ 0x5a, 0x34, 0xdd, 0xac, 0x40, 0x17, 0x7a, 0xdb, 0x71, 0x26, 0x70, 0x55, ++ 0x34, 0xdb, 0xe3, 0x33, 0xc2, 0xf7, 0xb5, 0xce, 0x00, 0x57, 0x05, 0xb8, ++ 0x5e, 0x90, 0xb7, 0xbd, 0xdf, 0x97, 0xbf, 0xf6, 0xf6, 0xca, 0x5f, 0x7a, ++ 0x2f, 0x01, 0xe7, 0x33, 0xf2, 0x57, 0xde, 0x97, 0xe5, 0x7b, 0xde, 0xd3, ++ 0xf2, 0x5d, 0xaf, 0x28, 0x6f, 0x79, 0x4f, 0xc8, 0x29, 0xef, 0x71, 0x9c, ++ 0x37, 0xa0, 0x4d, 0xb8, 0xf7, 0x4a, 0xf9, 0x08, 0x69, 0xcc, 0x7d, 0x04, ++ 0xfd, 0x94, 0xaf, 0x58, 0xfd, 0xe0, 0x58, 0xc3, 0x99, 0xb9, 0xd3, 0x22, ++ 0x4f, 0xe1, 0xae, 0x27, 0x64, 0xc6, 0xeb, 0xd6, 0x9c, 0x23, 0x5d, 0xda, ++ 0xe8, 0x11, 0xd2, 0xe2, 0x4b, 0xd9, 0xca, 0x65, 0x1d, 0xf0, 0x3b, 0x9a, ++ 0x10, 0x7b, 0x97, 0x99, 0x91, 0xaa, 0x9b, 0xa1, 0x7e, 0xd9, 0x7f, 0x62, ++ 0x26, 0xa1, 0xd3, 0x9a, 0x24, 0x0a, 0xe4, 0x73, 0x63, 0xa8, 0x73, 0x6d, ++ 0x32, 0x57, 0xb3, 0xa4, 0xe4, 0x7e, 0x4f, 0x2b, 0xa5, 0x29, 0x5b, 0x03, ++ 0xf3, 0x21, 0xcc, 0x4f, 0x85, 0x73, 0xe8, 0xd7, 0x31, 0xb1, 0x27, 0x8f, ++ 0xfa, 0xbe, 0x63, 0xd5, 0xc3, 0xb5, 0x11, 0xac, 0xe9, 0xd2, 0xf7, 0x1a, ++ 0xd7, 0x16, 0xc3, 0x35, 0xca, 0xc3, 0x97, 0x51, 0x8b, 0x62, 0x04, 0xbd, ++ 0xc6, 0x04, 0x9e, 0xcd, 0x78, 0xf2, 0x8c, 0x2f, 0xb7, 0x07, 0xff, 0x2d, ++ 0x16, 0x6d, 0xec, 0x39, 0xbc, 0x5b, 0xa0, 0x59, 0x52, 0xb7, 0x17, 0x96, ++ 0xf7, 0xfd, 0xb8, 0xff, 0xc6, 0x5c, 0x2f, 0xfc, 0x08, 0xfa, 0xad, 0x29, ++ 0x7b, 0xd5, 0xf0, 0xde, 0x5b, 0x7f, 0xb7, 0x2b, 0xb0, 0xcd, 0x04, 0x64, ++ 0x07, 0x39, 0xb9, 0xa4, 0x3f, 0x0b, 0xfa, 0xdb, 0x25, 0xff, 0x4d, 0xf2, ++ 0x30, 0x98, 0xd5, 0xc5, 0xce, 0x25, 0xc5, 0x92, 0x79, 0x2f, 0xa9, 0x8d, ++ 0xba, 0xb6, 0xe8, 0x05, 0x33, 0x53, 0x12, 0x5d, 0x8a, 0x69, 0x5b, 0x0e, ++ 0xe4, 0x73, 0x23, 0x15, 0xc9, 0x4a, 0x75, 0xd8, 0x92, 0x45, 0x0f, 0x90, ++ 0xe9, 0x8a, 0x5c, 0xc9, 0xe7, 0xac, 0x4b, 0xb2, 0x5e, 0x96, 0x0d, 0x4b, ++ 0x8e, 0x7b, 0x29, 0x79, 0xe7, 0xc8, 0x6e, 0xf9, 0x92, 0xcb, 0x7b, 0x92, ++ 0xc1, 0x26, 0xf9, 0xba, 0x2c, 0xe4, 0xbf, 0xfe, 0xd1, 0x82, 0x75, 0xa8, ++ 0x4d, 0x3a, 0xe8, 0x07, 0xa4, 0x33, 0xa0, 0xfb, 0x1e, 0xf0, 0x66, 0x43, ++ 0xb6, 0x1d, 0x90, 0x59, 0x32, 0xe0, 0xeb, 0xb1, 0x2e, 0x3c, 0xb9, 0xef, ++ 0x5f, 0x36, 0x42, 0x1f, 0xac, 0xac, 0x1e, 0xd1, 0x08, 0xde, 0xbb, 0xb9, ++ 0x67, 0x63, 0x3b, 0xd6, 0xb3, 0x37, 0x68, 0xdf, 0xa2, 0x8d, 0x1e, 0xeb, ++ 0x10, 0xf3, 0xb5, 0x1d, 0xc0, 0x95, 0x94, 0x97, 0x87, 0x7d, 0xff, 0x79, ++ 0x2b, 0x99, 0x1d, 0x93, 0x3d, 0xa4, 0x5d, 0x86, 0x0f, 0xdf, 0x22, 0x33, ++ 0x46, 0x4a, 0x76, 0x1c, 0x8e, 0xce, 0x6a, 0x09, 0xef, 0x27, 0x43, 0xfc, ++ 0x59, 0x5b, 0x6f, 0x8f, 0x7c, 0x44, 0x48, 0xd3, 0x18, 0xee, 0xa8, 0xcf, ++ 0x70, 0xf4, 0x5d, 0x1a, 0x7c, 0x0e, 0xc6, 0x78, 0x38, 0xbf, 0x4f, 0xbb, ++ 0x2f, 0xd9, 0x2d, 0x49, 0x33, 0xd1, 0x21, 0xad, 0x49, 0x39, 0xe7, 0x46, ++ 0xeb, 0xf0, 0x1b, 0x0a, 0x8e, 0x72, 0x96, 0xed, 0x37, 0xe4, 0x2c, 0xdb, ++ 0x7b, 0xeb, 0xbf, 0xe8, 0x08, 0x70, 0xda, 0x21, 0xec, 0x3a, 0xb1, 0x33, ++ 0x6d, 0xbc, 0xd3, 0x10, 0xf6, 0x9a, 0x1c, 0x1d, 0xce, 0x9d, 0xa4, 0xcf, ++ 0xb9, 0xb1, 0x87, 0xdf, 0x2d, 0x99, 0xf5, 0xd4, 0x9e, 0xec, 0x23, 0xb8, ++ 0xdb, 0x4a, 0xe6, 0x0e, 0xe3, 0x82, 0xde, 0xad, 0xd9, 0xca, 0x1f, 0x35, ++ 0xcb, 0x6b, 0xe9, 0x3e, 0xcc, 0x35, 0xa9, 0x7e, 0x96, 0xfa, 0x6a, 0x84, ++ 0xeb, 0x5c, 0xcb, 0x4d, 0x8f, 0xe9, 0xff, 0x86, 0x7b, 0xf7, 0xfd, 0xc7, ++ 0x2c, 0xca, 0x48, 0xc7, 0x1d, 0x6d, 0x01, 0x7f, 0x06, 0x9e, 0x11, 0xff, ++ 0x1b, 0xe0, 0x03, 0x49, 0xbf, 0xb2, 0x53, 0xc8, 0x39, 0x83, 0xf3, 0xee, ++ 0x85, 0x4d, 0xae, 0xb5, 0x57, 0xd8, 0x68, 0x07, 0x6d, 0xf5, 0x37, 0xc0, ++ 0x73, 0x6e, 0x00, 0x34, 0x42, 0x5e, 0x19, 0x69, 0x36, 0xf5, 0x4e, 0xfa, ++ 0x01, 0xdd, 0xdc, 0x84, 0xf5, 0x75, 0x57, 0x03, 0x9f, 0x19, 0xad, 0x5d, ++ 0x0d, 0x65, 0xb9, 0x5b, 0xca, 0xee, 0x1e, 0xc5, 0xf3, 0xac, 0xfe, 0x73, ++ 0xb1, 0x7b, 0xfa, 0x8c, 0x39, 0xd0, 0xeb, 0x24, 0x73, 0x27, 0x8a, 0x92, ++ 0xc1, 0xbd, 0x18, 0xb0, 0xc5, 0x34, 0x6c, 0x33, 0x0b, 0xfb, 0xb2, 0xe5, ++ 0x49, 0xb7, 0x20, 0xe5, 0x63, 0xb4, 0xb1, 0x9c, 0x41, 0xfb, 0x52, 0x77, ++ 0xe7, 0xfa, 0x7e, 0xd9, 0x12, 0xdb, 0x31, 0x07, 0x33, 0x93, 0xd4, 0x43, ++ 0xe8, 0xe7, 0xac, 0x37, 0x20, 0x0b, 0xde, 0xd6, 0xac, 0x9a, 0x7b, 0x26, ++ 0xde, 0x87, 0xa0, 0xdf, 0x79, 0xd8, 0x37, 0x79, 0x4b, 0x85, 0xbc, 0xc1, ++ 0x3f, 0x42, 0xef, 0xb2, 0xfa, 0x88, 0x2c, 0xf4, 0xcf, 0x43, 0xdf, 0x46, ++ 0x00, 0xb3, 0x5e, 0xec, 0x3d, 0x5c, 0x1f, 0x91, 0x59, 0x17, 0xbe, 0x9b, ++ 0x3a, 0xa0, 0xe0, 0x0a, 0x32, 0xe7, 0x16, 0x15, 0x9d, 0x25, 0xdc, 0xc1, ++ 0x68, 0xb2, 0x28, 0x65, 0x8f, 0xeb, 0xe4, 0xcb, 0x90, 0xf9, 0x7e, 0xdc, ++ 0x83, 0xab, 0x03, 0xaf, 0x86, 0xfd, 0xd7, 0x71, 0x57, 0x91, 0x0c, 0xef, ++ 0x06, 0x9f, 0x69, 0xec, 0x25, 0x8f, 0x5b, 0x64, 0xb6, 0x1b, 0x77, 0x31, ++ 0x9c, 0x56, 0x36, 0x5e, 0xea, 0xba, 0x45, 0x4a, 0x77, 0x34, 0xe3, 0x7b, ++ 0x37, 0xe6, 0xbc, 0xcb, 0x16, 0xac, 0xf1, 0xfb, 0xef, 0x86, 0xba, 0xd0, ++ 0xb4, 0x66, 0xfe, 0x05, 0x3c, 0x3b, 0x64, 0x93, 0xc9, 0xa7, 0x81, 0xe7, ++ 0xef, 0xe0, 0xd9, 0x85, 0x67, 0x1f, 0xce, 0x3a, 0x83, 0xfb, 0xe0, 0x5d, ++ 0xe0, 0x7d, 0x8e, 0x7b, 0x36, 0x87, 0xe7, 0x12, 0x6f, 0x07, 0xf0, 0xb4, ++ 0x87, 0x67, 0x75, 0x60, 0xde, 0x1a, 0x9e, 0x65, 0x82, 0xe6, 0xaf, 0x76, ++ 0xf0, 0x3e, 0x1c, 0xfa, 0xfe, 0x4f, 0xcc, 0x9f, 0xeb, 0x60, 0x4c, 0xd9, ++ 0x64, 0x76, 0x28, 0x1f, 0xbf, 0xd2, 0xdd, 0x8d, 0x77, 0x9e, 0x49, 0x18, ++ 0x7e, 0xc7, 0xd3, 0x23, 0x7e, 0xce, 0x6d, 0xf9, 0x8a, 0xcb, 0xd8, 0x08, ++ 0x3d, 0xf4, 0xf6, 0x60, 0xbe, 0x53, 0xf6, 0x82, 0xf7, 0xb2, 0x9b, 0x3b, ++ 0x38, 0xab, 0xfb, 0xbe, 0x9e, 0x4f, 0x1a, 0x55, 0xc9, 0xc1, 0x27, 0x8c, ++ 0x43, 0x66, 0xb0, 0x79, 0x37, 0x25, 0xe7, 0x94, 0x1d, 0x93, 0xa7, 0xc7, ++ 0x21, 0x97, 0xa4, 0xf4, 0x76, 0xd3, 0xd6, 0xb7, 0x68, 0xce, 0x31, 0xc8, ++ 0x6f, 0xc2, 0x90, 0x8b, 0x79, 0xfa, 0x85, 0xbc, 0x2c, 0xae, 0xfa, 0x85, ++ 0x0a, 0xfc, 0x02, 0x7d, 0x42, 0x05, 0xbe, 0x21, 0xb0, 0x91, 0x47, 0x65, ++ 0x13, 0x6c, 0x24, 0xc3, 0x7b, 0x82, 0x8d, 0xfc, 0x29, 0x6c, 0xc4, 0x80, ++ 0xbc, 0x61, 0x37, 0x06, 0xf5, 0xeb, 0x69, 0xf8, 0x47, 0xf0, 0x9b, 0x0e, ++ 0xdf, 0x17, 0x5f, 0x14, 0xe7, 0x18, 0x62, 0xb3, 0xf9, 0xb7, 0x4a, 0x66, ++ 0xa5, 0x45, 0xfe, 0x45, 0x7a, 0xfd, 0x87, 0x90, 0x1f, 0x7c, 0xb2, 0xd2, ++ 0x67, 0xf0, 0x96, 0xff, 0x1b, 0xc0, 0x4c, 0xc8, 0x9c, 0xd7, 0x0a, 0xfc, ++ 0xa4, 0xf1, 0x66, 0x70, 0xfc, 0x8e, 0xbc, 0x26, 0x4f, 0xdd, 0xc7, 0xfa, ++ 0x5c, 0x74, 0xdf, 0x6d, 0xea, 0xcc, 0xea, 0x70, 0x6b, 0xc8, 0x1f, 0xe5, ++ 0x40, 0x1b, 0xca, 0xc0, 0x06, 0x34, 0x29, 0x2b, 0x3b, 0xb0, 0x95, 0x1c, ++ 0xa0, 0x2f, 0x9d, 0xf4, 0x0f, 0x8e, 0x45, 0x19, 0x18, 0xf2, 0x70, 0xe0, ++ 0x6b, 0x6e, 0xf8, 0x8a, 0x1e, 0x0d, 0x7b, 0x38, 0x5f, 0x27, 0x8e, 0xf2, ++ 0x67, 0x3d, 0xa1, 0x9d, 0x34, 0x85, 0x7e, 0xe4, 0x71, 0xd9, 0xe7, 0x4d, ++ 0x40, 0xbf, 0x33, 0xf2, 0xac, 0xd7, 0x23, 0xcf, 0x41, 0x77, 0x2f, 0x75, ++ 0x4d, 0x00, 0x6f, 0x44, 0xef, 0xbd, 0xf2, 0x55, 0xc6, 0x4f, 0xf5, 0x0e, ++ 0x9f, 0xab, 0xdf, 0x4d, 0x1a, 0xe8, 0xcb, 0x60, 0xa3, 0x84, 0x4b, 0x84, ++ 0x34, 0x7e, 0xab, 0x2d, 0x80, 0x69, 0x92, 0xe5, 0xae, 0x1c, 0x38, 0x26, ++ 0x6d, 0xc9, 0xd0, 0x46, 0x72, 0x46, 0x51, 0xc8, 0x33, 0x69, 0xe5, 0x7b, ++ 0xa3, 0x2c, 0xf8, 0x6c, 0x94, 0x41, 0x84, 0x27, 0xb2, 0xf1, 0x31, 0xb1, ++ 0x3d, 0x3e, 0xe9, 0x7b, 0x11, 0x6f, 0x5d, 0xc4, 0x5b, 0x17, 0x71, 0xd6, ++ 0x45, 0x9c, 0x75, 0x11, 0x67, 0x5d, 0xc4, 0x5e, 0xd8, 0xd4, 0x5b, 0x2e, ++ 0x62, 0xad, 0x8b, 0x58, 0xeb, 0x32, 0x47, 0xa8, 0x20, 0x3e, 0x27, 0xe5, ++ 0x00, 0xf2, 0x8f, 0x57, 0x6a, 0xcc, 0x17, 0x72, 0x23, 0xef, 0xcb, 0xe0, ++ 0xc0, 0xfb, 0xc2, 0x1c, 0x22, 0x67, 0xbd, 0x83, 0xfc, 0xe5, 0x80, 0xca, ++ 0x41, 0xf0, 0xbd, 0x1e, 0xe5, 0x87, 0xb8, 0x7f, 0x93, 0x39, 0x60, 0xb0, ++ 0x0e, 0xf7, 0x8a, 0x18, 0x94, 0x1b, 0x70, 0x12, 0xe3, 0x32, 0x8b, 0x98, ++ 0x39, 0x65, 0xdd, 0x0a, 0x3e, 0xbb, 0x64, 0xca, 0x0c, 0xe6, 0x8e, 0x75, ++ 0x07, 0xfc, 0x06, 0x74, 0xc7, 0x60, 0xce, 0xb3, 0x05, 0x7f, 0x59, 0xc4, ++ 0xed, 0x6f, 0x68, 0xce, 0x9c, 0x20, 0x4e, 0x33, 0x76, 0xc3, 0x97, 0x28, ++ 0x3d, 0xba, 0xee, 0x97, 0x57, 0xf7, 0x0c, 0x42, 0xbf, 0x21, 0x77, 0xe4, ++ 0xb2, 0x55, 0xf7, 0xa8, 0x36, 0xba, 0x58, 0x50, 0x3c, 0x3a, 0x79, 0xce, ++ 0xaf, 0x87, 0xb6, 0xc7, 0xf3, 0x31, 0xf7, 0x82, 0x5c, 0xea, 0x52, 0x82, ++ 0x38, 0x2f, 0x21, 0xd7, 0xc8, 0x28, 0x1f, 0x76, 0x4a, 0xe5, 0x3c, 0x3d, ++ 0xc8, 0x35, 0x7c, 0xff, 0x94, 0xe5, 0xfb, 0x3f, 0xc0, 0xdf, 0xcf, 0xac, ++ 0x55, 0x1e, 0x30, 0x2a, 0xda, 0x98, 0x97, 0x95, 0x31, 0xef, 0xf6, 0xce, ++ 0x40, 0x8e, 0x22, 0x93, 0xb8, 0x87, 0x29, 0xb7, 0xa6, 0x3d, 0xbc, 0x78, ++ 0x58, 0x9b, 0x58, 0x9c, 0xc6, 0xb9, 0x29, 0xac, 0x49, 0xa5, 0x6a, 0x9d, ++ 0xd0, 0x46, 0xbd, 0x83, 0xda, 0x23, 0x8b, 0x41, 0x3c, 0xac, 0xba, 0xcc, ++ 0x3f, 0xae, 0xa9, 0x3c, 0xc8, 0x41, 0x9e, 0xfa, 0x05, 0x28, 0x9e, 0x53, ++ 0x23, 0xdd, 0xcd, 0x21, 0xcd, 0xb0, 0xc3, 0x82, 0xbf, 0xdf, 0xc9, 0x9b, ++ 0xb0, 0x45, 0xd2, 0xa8, 0xd6, 0xce, 0x06, 0x74, 0x1f, 0xd7, 0x9c, 0xc5, ++ 0x36, 0xc4, 0x46, 0xc6, 0x76, 0xe6, 0x98, 0xdc, 0xb7, 0x15, 0xf6, 0x5a, ++ 0xc7, 0x19, 0xcc, 0x9f, 0x29, 0x5b, 0xd0, 0x0d, 0x1d, 0x7e, 0xcb, 0x05, ++ 0x1f, 0x2a, 0x97, 0x22, 0x7f, 0x59, 0xdc, 0x15, 0x6d, 0x6f, 0x04, 0x39, ++ 0xc3, 0xbb, 0xe0, 0x73, 0x00, 0x7c, 0x5a, 0xe0, 0x6f, 0x08, 0x39, 0x95, ++ 0x09, 0x7e, 0xb3, 0xe0, 0x37, 0x37, 0xcd, 0x0b, 0xe9, 0x00, 0xcc, 0x3f, ++ 0x6d, 0x65, 0xfc, 0xf7, 0xfd, 0xcf, 0x9b, 0xb9, 0xa7, 0xc9, 0xed, 0x94, ++ 0x2b, 0x76, 0xd5, 0x52, 0x76, 0x02, 0x7e, 0xb2, 0xcc, 0x1b, 0x40, 0x5b, ++ 0x33, 0xfd, 0x2d, 0xe6, 0xab, 0xf4, 0xc1, 0xa7, 0x7f, 0x9b, 0xf1, 0xd6, ++ 0x70, 0xf2, 0x84, 0x8d, 0xe0, 0x5a, 0x42, 0xbe, 0x7d, 0x3f, 0x01, 0xbe, ++ 0xca, 0x79, 0xc2, 0x49, 0x45, 0xdd, 0x07, 0xfc, 0xf2, 0x24, 0xf2, 0xb9, ++ 0x71, 0xb7, 0x0b, 0x32, 0x81, 0x9e, 0xb8, 0x8c, 0x17, 0xd5, 0x01, 0x88, ++ 0x53, 0x3b, 0x67, 0x8d, 0xaa, 0x7b, 0x9f, 0x37, 0xc5, 0x3e, 0x67, 0x19, ++ 0x3c, 0x3b, 0x7b, 0xce, 0xaa, 0x00, 0x53, 0x20, 0xb3, 0xd1, 0x5a, 0x12, ++ 0xdf, 0x38, 0x47, 0x0e, 0xe6, 0x45, 0x72, 0x4c, 0xc3, 0xd7, 0x45, 0xf2, ++ 0x8d, 0xd6, 0x2e, 0xa8, 0x5c, 0x72, 0xd6, 0xbb, 0x0b, 0x38, 0xfe, 0xaf, ++ 0xfd, 0x19, 0xc4, 0x15, 0xe2, 0xc8, 0xc8, 0x77, 0xdc, 0xdc, 0x08, 0x74, ++ 0x3a, 0x4b, 0x1d, 0x6d, 0x83, 0x3f, 0xfd, 0x0b, 0xc8, 0xaf, 0xb5, 0x20, ++ 0xda, 0x83, 0x5b, 0x73, 0xc6, 0x5e, 0x2d, 0x21, 0x38, 0xea, 0x8e, 0x24, ++ 0x98, 0xcd, 0x6e, 0x08, 0x6a, 0x11, 0x07, 0x39, 0xf8, 0x14, 0x62, 0xc3, ++ 0xe4, 0x50, 0xce, 0x98, 0x0d, 0xea, 0x15, 0xe3, 0x41, 0x55, 0x83, 0xfc, ++ 0xdc, 0x2f, 0xa6, 0xb7, 0x8d, 0xac, 0x00, 0x51, 0xb2, 0x90, 0xdc, 0x3e, ++ 0x55, 0x7b, 0x46, 0x98, 0x97, 0x4d, 0x0e, 0xad, 0x93, 0xa2, 0xd1, 0x67, ++ 0x8f, 0xab, 0x9a, 0x25, 0xb5, 0xbd, 0x6c, 0x06, 0xb4, 0x8d, 0xc2, 0x86, ++ 0x27, 0x91, 0x1f, 0x8e, 0xd7, 0x99, 0x3b, 0x24, 0xb7, 0xf7, 0xd5, 0xff, ++ 0xb3, 0x93, 0xfe, 0xfd, 0x80, 0x77, 0x3b, 0xee, 0xbd, 0x07, 0x7e, 0x57, ++ 0xc5, 0x50, 0x64, 0xff, 0xbc, 0x77, 0xe8, 0x98, 0xd7, 0x86, 0x35, 0xf0, ++ 0x03, 0xf9, 0x8e, 0x59, 0xf4, 0xe1, 0x89, 0xb0, 0xc6, 0xf9, 0x18, 0xfb, ++ 0xb2, 0x82, 0x50, 0x61, 0x3b, 0x2a, 0x3e, 0x32, 0xde, 0x19, 0x9c, 0x1b, ++ 0xe7, 0xac, 0xb4, 0xaa, 0x99, 0x1e, 0xd9, 0x99, 0x85, 0x7f, 0x47, 0x1c, ++ 0x4d, 0x53, 0x77, 0x4c, 0xe3, 0x1c, 0x12, 0xc8, 0x60, 0x5d, 0x3a, 0x70, ++ 0x57, 0xed, 0xcc, 0x0f, 0xcf, 0x53, 0xc7, 0xf2, 0xb4, 0xa9, 0x96, 0xe8, ++ 0x1b, 0xf4, 0x68, 0xa8, 0x21, 0xf7, 0x1c, 0x42, 0xee, 0xd9, 0xa4, 0xd6, ++ 0x9b, 0x0a, 0x79, 0x59, 0xa8, 0x99, 0x32, 0xb3, 0x87, 0x3a, 0x83, 0x1a, ++ 0xce, 0xcd, 0xa9, 0x18, 0x3d, 0xe5, 0xf2, 0xfe, 0x69, 0xab, 0xb7, 0x85, ++ 0x73, 0xed, 0x33, 0xc0, 0x7d, 0xf0, 0x9c, 0x04, 0xb5, 0x61, 0xef, 0x63, ++ 0x4a, 0xc7, 0xf4, 0xaa, 0x75, 0x0b, 0x69, 0xc1, 0x7b, 0x87, 0x36, 0x71, ++ 0x8c, 0x35, 0x41, 0x16, 0x7e, 0x09, 0x37, 0xb4, 0xcd, 0xf7, 0x8d, 0xe1, ++ 0xc8, 0xd6, 0x92, 0xb0, 0x2b, 0xff, 0x2c, 0x63, 0xdd, 0xd8, 0xce, 0x20, ++ 0x7f, 0xd5, 0xcd, 0x1a, 0xec, 0x82, 0x3e, 0x81, 0xb6, 0x77, 0x50, 0x1b, ++ 0x5b, 0x3c, 0x0e, 0xfb, 0x9b, 0xc6, 0xda, 0x69, 0xed, 0x61, 0xef, 0x5f, ++ 0x0d, 0xe5, 0xe3, 0x94, 0x2e, 0xb6, 0x51, 0x8f, 0x70, 0x26, 0x79, 0x78, ++ 0x0f, 0x3c, 0x74, 0x68, 0x9f, 0x3b, 0x56, 0x51, 0xfe, 0xde, 0x31, 0x7d, ++ 0xff, 0xa2, 0xa5, 0x4b, 0x93, 0xe2, 0xe9, 0x3d, 0xf0, 0x74, 0x19, 0xfb, ++ 0x12, 0xd2, 0x62, 0x72, 0xdf, 0xae, 0x28, 0x9f, 0xc4, 0x3e, 0x0b, 0xfb, ++ 0xda, 0x43, 0x9d, 0x26, 0x4f, 0xca, 0x2e, 0x3a, 0x51, 0x27, 0x50, 0xaf, ++ 0x35, 0xbd, 0x10, 0xf9, 0x1f, 0x82, 0x13, 0xbf, 0x2e, 0xf7, 0xef, 0xbc, ++ 0x04, 0x5c, 0x3c, 0xa7, 0x1d, 0x79, 0xab, 0x68, 0x55, 0xca, 0x1c, 0x7b, ++ 0x02, 0x9a, 0x44, 0x4f, 0x14, 0x5a, 0x64, 0x14, 0xf9, 0x6c, 0xd5, 0x35, ++ 0x8d, 0xcf, 0x43, 0x07, 0x7e, 0x0b, 0x76, 0xef, 0x4c, 0xd3, 0x3f, 0x7c, ++ 0x03, 0xfb, 0x96, 0x73, 0x7a, 0x58, 0xc9, 0xbf, 0xe2, 0x52, 0xc6, 0x3f, ++ 0x80, 0x8c, 0xf5, 0xee, 0x66, 0xa4, 0xb6, 0x13, 0xb8, 0xd3, 0xd9, 0x11, ++ 0xd0, 0x3e, 0xd4, 0x26, 0x89, 0x3b, 0xe9, 0x1f, 0x50, 0xbb, 0xa4, 0x97, ++ 0xe1, 0x8c, 0xaf, 0xf9, 0xfa, 0x36, 0xec, 0x1f, 0xc2, 0x3d, 0xef, 0x09, ++ 0x72, 0xc6, 0x00, 0x8e, 0x30, 0x8c, 0x25, 0x4e, 0x57, 0xb3, 0x10, 0x37, ++ 0xbf, 0x0d, 0x66, 0x0c, 0xe1, 0x3a, 0xfc, 0xe8, 0x04, 0xf7, 0x92, 0xe6, ++ 0x60, 0x4f, 0x93, 0xc9, 0x9a, 0x95, 0x72, 0xb9, 0x0f, 0xb2, 0xff, 0xd8, ++ 0xbf, 0x7f, 0x38, 0xfa, 0x4e, 0x7e, 0xc8, 0x97, 0xd2, 0xad, 0xd4, 0x86, ++ 0x82, 0x29, 0xdb, 0x0f, 0x53, 0xc7, 0xc6, 0x55, 0x4c, 0xef, 0x1d, 0xce, ++ 0x55, 0xb2, 0xfa, 0x26, 0xf0, 0x9a, 0x94, 0x47, 0x87, 0xc9, 0xef, 0x2d, ++ 0x61, 0xac, 0x6f, 0xe4, 0xb9, 0x33, 0xe4, 0x59, 0x9d, 0x37, 0x62, 0xeb, ++ 0x37, 0x78, 0x1f, 0x9b, 0x8e, 0xce, 0x85, 0x4f, 0x35, 0x97, 0x51, 0xb3, ++ 0xf0, 0x7c, 0xd2, 0x73, 0xdd, 0xd7, 0x4d, 0xb3, 0xd2, 0xab, 0x7f, 0xec, ++ 0x3f, 0x32, 0xac, 0xa9, 0xdc, 0x08, 0x29, 0xb4, 0xe8, 0xc3, 0xe0, 0x75, ++ 0x98, 0xf9, 0x88, 0x0e, 0x3d, 0x24, 0xbe, 0x9f, 0x90, 0x37, 0xe0, 0x6c, ++ 0x0d, 0x6a, 0x90, 0xe1, 0xe8, 0x0c, 0xf2, 0xd5, 0xc8, 0x13, 0x71, 0x12, ++ 0x17, 0x61, 0xd4, 0x9d, 0xf0, 0x4e, 0x53, 0x8e, 0x95, 0x0a, 0xef, 0x3b, ++ 0xda, 0x27, 0x5a, 0xd2, 0x5c, 0xbb, 0x2f, 0x23, 0xc5, 0x6e, 0xf8, 0x50, ++ 0xb7, 0xb1, 0xff, 0x21, 0x59, 0x55, 0x9b, 0xcf, 0x53, 0x27, 0xd9, 0xfb, ++ 0x30, 0xa4, 0x38, 0x1f, 0xf9, 0xe5, 0x2b, 0x06, 0x6b, 0xb7, 0xb3, 0x2e, ++ 0x69, 0xe2, 0x33, 0xd2, 0x8d, 0x46, 0x9a, 0x88, 0x97, 0xf8, 0x79, 0x36, ++ 0x61, 0xe0, 0x9f, 0x5d, 0xf8, 0x6a, 0xe4, 0x6e, 0xa7, 0xe0, 0x33, 0x4e, ++ 0xba, 0x8c, 0xb3, 0xf4, 0xe7, 0x23, 0x0d, 0x75, 0x76, 0x5b, 0x31, 0x59, ++ 0x60, 0xad, 0x2d, 0x13, 0xd5, 0xda, 0x7e, 0xc4, 0x37, 0xa9, 0x6c, 0x51, ++ 0x35, 0x6b, 0xdb, 0x88, 0x93, 0xc7, 0x5a, 0x9d, 0x31, 0x0e, 0xae, 0xa6, ++ 0x80, 0x5c, 0xda, 0x4b, 0xa5, 0xf4, 0xc3, 0xa9, 0xca, 0xad, 0x05, 0xea, ++ 0x78, 0x56, 0xb2, 0xf5, 0x8f, 0x10, 0x3f, 0x90, 0x8b, 0x29, 0xdd, 0x28, ++ 0xdc, 0xca, 0x5a, 0xa0, 0x8a, 0x98, 0x97, 0x2c, 0x48, 0x52, 0x2f, 0x34, ++ 0xa7, 0x26, 0xf3, 0x6d, 0x88, 0x9b, 0xe3, 0x9b, 0xf5, 0x37, 0x77, 0x6f, ++ 0x4e, 0xbc, 0xd9, 0x5d, 0x6c, 0x2a, 0x54, 0x36, 0xeb, 0x87, 0x05, 0x35, ++ 0xaf, 0xe8, 0x88, 0x4f, 0x99, 0xbd, 0x82, 0xf9, 0x9b, 0x8f, 0x3e, 0xaa, ++ 0x17, 0x94, 0xcf, 0x79, 0x69, 0x1e, 0x3e, 0x7d, 0xb6, 0x96, 0xcb, 0x4e, ++ 0xc8, 0x4b, 0x52, 0xad, 0xbd, 0x20, 0x93, 0x70, 0x92, 0x55, 0xc4, 0xd2, ++ 0x49, 0x4f, 0x2a, 0x7a, 0x01, 0x7e, 0x2f, 0x2f, 0x32, 0x5a, 0x83, 0x3c, ++ 0x91, 0x1f, 0x4d, 0x7a, 0x39, 0xab, 0x08, 0x2e, 0x3f, 0xac, 0x51, 0xa7, ++ 0xaf, 0x41, 0xa7, 0xe9, 0x1f, 0xaf, 0xca, 0x54, 0xad, 0xcf, 0x6a, 0xd6, ++ 0x54, 0x3e, 0x31, 0x70, 0x5c, 0x06, 0xad, 0xe3, 0xf0, 0xc1, 0xc8, 0x49, ++ 0xb3, 0xaf, 0x08, 0x69, 0xbe, 0x26, 0x5b, 0x95, 0x5f, 0xbc, 0x2a, 0x66, ++ 0x1d, 0x99, 0x11, 0xf2, 0x22, 0x7d, 0xf8, 0x3f, 0x7c, 0xdb, 0xc8, 0x59, ++ 0xfc, 0xdf, 0x93, 0x5c, 0xb9, 0x09, 0xae, 0x77, 0x15, 0x1e, 0xe2, 0x6b, ++ 0xc4, 0xa5, 0x49, 0xcb, 0x70, 0x84, 0xaf, 0x47, 0x0e, 0x7a, 0x11, 0xce, ++ 0xbd, 0x72, 0x09, 0x9e, 0x5b, 0x1f, 0x1e, 0x50, 0xb5, 0xb3, 0xe3, 0xa9, ++ 0x38, 0x8b, 0x5a, 0x19, 0x7a, 0xa1, 0x7a, 0x19, 0x49, 0xf2, 0xa2, 0x7c, ++ 0xad, 0x9e, 0x6f, 0x0e, 0xfd, 0x6c, 0x87, 0xb6, 0xeb, 0x18, 0xcf, 0xfb, ++ 0x08, 0xba, 0xfa, 0xc5, 0x0d, 0xe1, 0xff, 0x47, 0x25, 0xf4, 0xb9, 0xeb, ++ 0x57, 0xf5, 0x28, 0x80, 0xf9, 0x10, 0x30, 0x1d, 0xc0, 0xc3, 0xde, 0x59, ++ 0xb4, 0xf6, 0xee, 0xf6, 0x29, 0xf3, 0xd9, 0xd5, 0x7d, 0xa3, 0x88, 0xd9, ++ 0x55, 0xe8, 0x48, 0x80, 0x3b, 0x89, 0x39, 0x64, 0xe8, 0xae, 0x3d, 0xeb, ++ 0x74, 0xc3, 0x9e, 0x68, 0xed, 0x52, 0x03, 0x6e, 0xfa, 0xa9, 0xe5, 0xa0, ++ 0xff, 0x65, 0x28, 0xdf, 0x8a, 0xf9, 0x85, 0x06, 0x9f, 0x7d, 0x01, 0xfe, ++ 0xed, 0xcf, 0xc3, 0xfd, 0x46, 0xe8, 0x1b, 0x5b, 0x55, 0xfe, 0x31, 0xa9, ++ 0x60, 0xb3, 0x0d, 0xb0, 0x59, 0xc0, 0x7e, 0x2d, 0xf0, 0xbd, 0xf2, 0xed, ++ 0x70, 0x0f, 0xfd, 0xaf, 0x69, 0x30, 0xfe, 0x04, 0xfc, 0xf9, 0x07, 0x56, ++ 0xe7, 0xe9, 0x62, 0x88, 0xaf, 0x29, 0xfc, 0xb6, 0xad, 0x3d, 0xd0, 0xe7, ++ 0x68, 0xef, 0x87, 0x1b, 0x82, 0x79, 0xb3, 0xea, 0xb3, 0x00, 0x16, 0xf2, ++ 0xcd, 0x16, 0x75, 0xe8, 0xf0, 0x68, 0x3d, 0x90, 0x01, 0xf2, 0x14, 0xf6, ++ 0x09, 0x59, 0x83, 0xe2, 0x2e, 0xf6, 0xf9, 0xcc, 0x3b, 0xf4, 0x82, 0xcd, ++ 0xbb, 0xb0, 0x93, 0xa4, 0xcd, 0x1b, 0xe7, 0x9d, 0x3c, 0x13, 0xf4, 0x2f, ++ 0x7e, 0x5d, 0xf6, 0xaa, 0x73, 0x06, 0x8d, 0x49, 0xe2, 0x4c, 0x0b, 0x70, ++ 0xc1, 0x0e, 0xe1, 0x53, 0x4b, 0x0a, 0xff, 0x4f, 0xc3, 0x73, 0xfb, 0xc3, ++ 0xfe, 0x8a, 0x9a, 0x63, 0x7d, 0x1c, 0xf8, 0x92, 0xcc, 0x97, 0x11, 0x4b, ++ 0x99, 0x77, 0xac, 0x97, 0xd1, 0x34, 0xf2, 0xba, 0x7e, 0x1b, 0xb8, 0x23, ++ 0x7b, 0xee, 0x51, 0xbd, 0x9a, 0xc9, 0xfa, 0x7a, 0xa9, 0xce, 0x44, 0x76, ++ 0x1c, 0xed, 0x6f, 0xcc, 0x07, 0x89, 0x8b, 0x78, 0xe0, 0xcf, 0x42, 0xdb, ++ 0xaf, 0xce, 0x70, 0x0d, 0x77, 0x39, 0x3f, 0x86, 0xa7, 0x29, 0xd5, 0xfa, ++ 0xda, 0xfd, 0x6d, 0x61, 0xbf, 0x26, 0x9a, 0x3f, 0x70, 0x6b, 0x30, 0xe7, ++ 0xfb, 0x0b, 0x21, 0xff, 0x9b, 0xf9, 0x0d, 0xbc, 0x43, 0x97, 0xdc, 0x7b, ++ 0x82, 0x3c, 0x5f, 0xd5, 0x49, 0xf0, 0xb3, 0x1e, 0xd7, 0x96, 0x5b, 0x1c, ++ 0x2b, 0x92, 0xf3, 0x6e, 0xac, 0x4d, 0xe0, 0x2f, 0xea, 0xfb, 0xed, 0xc1, ++ 0xbb, 0x1d, 0xc2, 0xc9, 0x48, 0x10, 0xff, 0xa3, 0x3c, 0x3f, 0xca, 0xbf, ++ 0x65, 0x5a, 0x2f, 0x30, 0x37, 0xde, 0x0a, 0xbb, 0x60, 0x3e, 0x0b, 0xd9, ++ 0xae, 0xf2, 0xb4, 0x0a, 0x53, 0xb9, 0x01, 0x13, 0xe4, 0x92, 0x63, 0x5e, ++ 0x94, 0x2b, 0x33, 0x47, 0x8e, 0xf2, 0x65, 0x5b, 0x9b, 0x70, 0xc7, 0xb5, ++ 0x87, 0x5d, 0xc2, 0xeb, 0x47, 0x37, 0x88, 0x99, 0xed, 0xd5, 0x7d, 0x19, ++ 0x1d, 0x66, 0x5d, 0xfa, 0x2a, 0x64, 0xdf, 0x29, 0xa5, 0x81, 0x2e, 0xd0, ++ 0x7a, 0x37, 0x9e, 0xcd, 0x58, 0xfb, 0x4d, 0xac, 0xe1, 0x8e, 0x06, 0x98, ++ 0x1f, 0xae, 0x53, 0xf9, 0x7d, 0x51, 0xc5, 0x88, 0xad, 0xe1, 0x3d, 0xfd, ++ 0x7d, 0x57, 0x70, 0x6f, 0x7f, 0x80, 0xf9, 0x7a, 0xac, 0x7f, 0x11, 0x4f, ++ 0xdf, 0xef, 0x1d, 0x8e, 0xd6, 0xa9, 0x7b, 0x23, 0x58, 0xdf, 0x01, 0x1c, ++ 0x15, 0xbc, 0x7f, 0x06, 0xef, 0x7f, 0xb4, 0x66, 0xef, 0x8b, 0x98, 0x57, ++ 0xb0, 0xee, 0xac, 0x59, 0x8f, 0xee, 0x8e, 0xe7, 0x55, 0xb4, 0x09, 0x6f, ++ 0x0a, 0xb9, 0x06, 0x73, 0xf4, 0x57, 0x51, 0x07, 0xf0, 0xfe, 0x58, 0x0f, ++ 0x4c, 0x23, 0x97, 0xe7, 0xdd, 0xfd, 0x1d, 0xf6, 0xcc, 0xe3, 0x3e, 0x5a, ++ 0x55, 0x56, 0xa7, 0x2b, 0x9b, 0x38, 0xb9, 0xaf, 0x77, 0x86, 0xcf, 0xd3, ++ 0xfb, 0xac, 0x3a, 0x61, 0xf8, 0xfe, 0xdd, 0x7d, 0xbd, 0xf5, 0xf3, 0x80, ++ 0x65, 0xfe, 0xdd, 0xd8, 0x0f, 0x3f, 0xbe, 0xe6, 0xcc, 0xa0, 0x7e, 0x98, ++ 0x50, 0x3d, 0xbc, 0x93, 0xfb, 0x9c, 0x69, 0xc6, 0x63, 0xd6, 0x72, 0xcc, ++ 0x03, 0x4f, 0xef, 0x2b, 0xd7, 0xa6, 0xc2, 0x7a, 0x21, 0xfa, 0xce, 0x6f, ++ 0x94, 0xff, 0xcd, 0x68, 0x23, 0x5d, 0x8d, 0x78, 0x82, 0xdc, 0x26, 0x01, ++ 0x5a, 0xca, 0x35, 0xd6, 0x1d, 0xaa, 0xdf, 0xae, 0xe8, 0xcd, 0xce, 0xdc, ++ 0x8c, 0x36, 0xe2, 0xe2, 0x59, 0x11, 0xbe, 0x6f, 0x22, 0x67, 0x7a, 0x9b, ++ 0xf4, 0x02, 0xcf, 0x6d, 0x61, 0x0e, 0xd3, 0xa4, 0x7a, 0x70, 0xaa, 0x3f, ++ 0xa2, 0xe6, 0x51, 0x5d, 0xd9, 0xb4, 0xa6, 0xae, 0x6c, 0x0a, 0xfb, 0x4d, ++ 0x84, 0xd5, 0x43, 0x58, 0xf5, 0x7b, 0x03, 0xd6, 0xb2, 0x61, 0xef, 0x37, ++ 0xc5, 0xde, 0x6f, 0x83, 0x2c, 0x9a, 0x42, 0xf9, 0xab, 0x9a, 0x2e, 0xb4, ++ 0x8f, 0x46, 0xfa, 0x98, 0x03, 0x4e, 0xe1, 0x7b, 0x74, 0x37, 0x11, 0xef, ++ 0xf3, 0x58, 0x27, 0xbd, 0x27, 0x00, 0x1f, 0xd1, 0xfb, 0x69, 0xef, 0x94, ++ 0x7b, 0x4f, 0xe0, 0x2f, 0x3a, 0x2f, 0x92, 0x0b, 0x69, 0xfd, 0xdf, 0x6a, ++ 0xa7, 0x20, 0xd6, 0x06, 0xfd, 0xec, 0xe0, 0xfe, 0x6c, 0xe8, 0xfc, 0x59, ++ 0xf6, 0x3c, 0x24, 0xea, 0x55, 0xb3, 0x7e, 0xa5, 0xef, 0xe5, 0x7d, 0xb5, ++ 0x40, 0x57, 0x08, 0xa7, 0x49, 0x95, 0xb2, 0x30, 0x9c, 0x2c, 0x72, 0xfb, ++ 0xcc, 0x93, 0xf2, 0x43, 0x9c, 0x65, 0x0f, 0x34, 0x85, 0x3d, 0xf6, 0x22, ++ 0xfc, 0xd5, 0x32, 0x74, 0x9a, 0x7d, 0xfc, 0x59, 0xd4, 0x23, 0x0b, 0x78, ++ 0x56, 0xeb, 0x3f, 0xee, 0x62, 0xaf, 0x61, 0xca, 0xbc, 0x51, 0x23, 0xcf, ++ 0x00, 0x66, 0xce, 0x64, 0x1d, 0x1d, 0x26, 0x82, 0xc8, 0xc9, 0x75, 0xe4, ++ 0x0b, 0x65, 0xf3, 0xbf, 0xfd, 0x52, 0xba, 0x11, 0xf6, 0x66, 0x3d, 0xfb, ++ 0xa8, 0xfe, 0xcf, 0x36, 0xd4, 0xff, 0xb9, 0x86, 0x5e, 0xfb, 0xb7, 0xda, ++ 0x42, 0xfa, 0x65, 0xd2, 0xf2, 0x25, 0xfa, 0x4d, 0xe7, 0xfe, 0xfe, 0x46, ++ 0x7d, 0x1d, 0x50, 0xbe, 0xb7, 0xac, 0x7e, 0x1f, 0xa1, 0x7c, 0x93, 0x72, ++ 0x09, 0xb5, 0xfd, 0xe5, 0xf9, 0x56, 0x59, 0x99, 0x09, 0xfc, 0xdd, 0x8a, ++ 0xf2, 0x8f, 0x86, 0xbc, 0x8f, 0x82, 0xed, 0x52, 0x7d, 0x00, 0x7f, 0x5d, ++ 0x72, 0x65, 0x3e, 0xfa, 0xcd, 0x27, 0x92, 0xdf, 0xbd, 0xa0, 0xa5, 0x2b, ++ 0xd4, 0x85, 0x76, 0xe4, 0x7f, 0xfc, 0x0d, 0x22, 0xe8, 0xcd, 0xaa, 0xf8, ++ 0x93, 0xa4, 0x4c, 0xd9, 0x83, 0x8d, 0xfa, 0x93, 0x7d, 0xa8, 0x49, 0x90, ++ 0xfd, 0x25, 0xbb, 0xa4, 0x59, 0xf5, 0x43, 0x82, 0x78, 0x75, 0xd6, 0x8d, ++ 0x7c, 0x18, 0xe9, 0x66, 0x3d, 0x3b, 0x04, 0x1f, 0x94, 0x3b, 0x38, 0x83, ++ 0x9c, 0xe9, 0x2d, 0xf0, 0xbe, 0xd0, 0x9f, 0x9b, 0xae, 0x08, 0xfb, 0x85, ++ 0x79, 0x9c, 0x39, 0x00, 0x59, 0xb0, 0x67, 0x68, 0xa0, 0xb6, 0x63, 0xaf, ++ 0x80, 0xfd, 0xe1, 0x94, 0xf4, 0x1e, 0x9e, 0x92, 0x92, 0xf7, 0x33, 0xc8, ++ 0xc3, 0x96, 0xa2, 0x37, 0x82, 0xf3, 0x0e, 0x21, 0xf7, 0xfa, 0xc7, 0x8d, ++ 0xec, 0x39, 0x35, 0x9b, 0x51, 0xef, 0xb1, 0x53, 0xf5, 0x59, 0x57, 0xfb, ++ 0x8b, 0xaa, 0x4f, 0x17, 0xf5, 0x16, 0x53, 0x61, 0x6f, 0xf1, 0xb1, 0x8d, ++ 0x81, 0x7d, 0x17, 0x81, 0x87, 0xfb, 0xfe, 0x2b, 0xec, 0x31, 0xdc, 0x13, ++ 0xf6, 0x9a, 0x52, 0xa1, 0x3d, 0x24, 0x80, 0x17, 0x79, 0x8a, 0xe4, 0xb1, ++ 0x76, 0xb7, 0x94, 0x8f, 0x4c, 0xc9, 0x5e, 0x77, 0xf5, 0x37, 0x88, 0xcc, ++ 0x53, 0x52, 0xc9, 0x24, 0x90, 0xab, 0xb0, 0x4f, 0x3f, 0x2f, 0xeb, 0x43, ++ 0xfd, 0x61, 0x0f, 0x15, 0x74, 0xaa, 0xbe, 0x69, 0x9f, 0xb1, 0x0b, 0xb9, ++ 0x7a, 0x09, 0xf2, 0x28, 0x2a, 0x1b, 0xe2, 0xfa, 0xb3, 0x38, 0xbb, 0xaf, ++ 0xb2, 0x0b, 0x70, 0x25, 0xd4, 0x85, 0x13, 0xc8, 0xe5, 0xe6, 0x10, 0xd3, ++ 0x4a, 0xc8, 0x9b, 0x51, 0xeb, 0xc2, 0xcb, 0xf6, 0x80, 0xf6, 0x17, 0x01, ++ 0x33, 0x68, 0xe8, 0x7a, 0x46, 0xd7, 0xef, 0x84, 0x8f, 0x98, 0xc0, 0xd3, ++ 0x9c, 0xe4, 0x3e, 0xa3, 0x09, 0xb6, 0x5b, 0xb6, 0x12, 0xac, 0x43, 0x81, ++ 0x9b, 0xb0, 0x7c, 0xe6, 0x2a, 0xb6, 0x54, 0x90, 0x0f, 0x32, 0x5e, 0x54, ++ 0xc4, 0x30, 0x03, 0x7b, 0xb7, 0x75, 0x4d, 0xf5, 0x3e, 0x4b, 0x8a, 0x47, ++ 0x3b, 0x6b, 0xc8, 0x7e, 0xd0, 0x4e, 0x1e, 0x93, 0x90, 0x25, 0x73, 0x05, ++ 0xf6, 0x14, 0x0b, 0xf2, 0xcc, 0xe2, 0x04, 0xe8, 0xea, 0x90, 0xbe, 0xd7, ++ 0x58, 0xcb, 0x3e, 0x8e, 0x35, 0xce, 0xd9, 0xff, 0x7d, 0x02, 0xef, 0x84, ++ 0xcd, 0xe0, 0x49, 0xf9, 0xf7, 0xe0, 0x49, 0xd9, 0x52, 0x3e, 0xb8, 0xfb, ++ 0x3d, 0x59, 0x99, 0x3d, 0xb2, 0x53, 0x8a, 0x73, 0x3b, 0x81, 0xff, 0x27, ++ 0x90, 0xe1, 0x8e, 0x50, 0x7e, 0x91, 0x2c, 0x97, 0x36, 0xb2, 0x0e, 0xee, ++ 0x3d, 0xcc, 0x75, 0x3e, 0x77, 0x63, 0xbf, 0x09, 0xdc, 0xaa, 0x7f, 0x09, ++ 0x18, 0xe8, 0x8d, 0xd7, 0xf8, 0x3b, 0x53, 0x17, 0xe3, 0x39, 0xf3, 0x61, ++ 0xf8, 0xc7, 0x99, 0xed, 0x4e, 0x2d, 0x67, 0x38, 0xaa, 0x07, 0x3e, 0x20, ++ 0x81, 0xcf, 0xe4, 0x5a, 0x4a, 0xcc, 0xc3, 0xa8, 0x9d, 0x0a, 0xfc, 0xb6, ++ 0x7f, 0xb5, 0x57, 0x3d, 0x2a, 0xef, 0xc9, 0x18, 0xf4, 0xbb, 0xef, 0x30, ++ 0xe2, 0xb6, 0xf7, 0x23, 0xe4, 0x25, 0x41, 0x6f, 0xce, 0xd6, 0x47, 0x42, ++ 0xbd, 0x6c, 0x6d, 0xd0, 0x47, 0xe8, 0x98, 0x0b, 0xbd, 0x43, 0xae, 0x7e, ++ 0x0a, 0xb9, 0xfa, 0xc9, 0x55, 0xdd, 0x1c, 0x69, 0xf0, 0x1b, 0xed, 0xf2, ++ 0x0f, 0xd3, 0xb9, 0x81, 0x65, 0xe8, 0xee, 0x15, 0xf0, 0xba, 0x8c, 0x9a, ++ 0x64, 0x05, 0xbe, 0x70, 0xae, 0xc6, 0x5e, 0x33, 0x7f, 0xf7, 0xe1, 0x7c, ++ 0x13, 0x74, 0x24, 0xf2, 0x29, 0x1b, 0xdb, 0x03, 0x9b, 0x6c, 0x57, 0xfd, ++ 0xb0, 0xcb, 0xb8, 0xd7, 0x65, 0x83, 0xdf, 0xa2, 0x3d, 0xed, 0x12, 0xfd, ++ 0xb6, 0x14, 0xe8, 0x2d, 0x69, 0xa1, 0xde, 0xfe, 0x72, 0x23, 0xfb, 0xcd, ++ 0x67, 0x5d, 0xfe, 0xde, 0xc2, 0x9c, 0x9c, 0xef, 0x77, 0x6d, 0x0c, 0x70, ++ 0x35, 0xda, 0xcc, 0x55, 0xd0, 0x55, 0xd1, 0x9c, 0x7e, 0xf8, 0x1d, 0xcf, ++ 0x97, 0x57, 0xad, 0x4f, 0xda, 0xfa, 0xe7, 0xdc, 0x48, 0x3e, 0x94, 0xdf, ++ 0x6e, 0x79, 0xc5, 0xcb, 0xc1, 0x0e, 0x29, 0x3b, 0xb3, 0x41, 0x76, 0x22, ++ 0xdf, 0x41, 0x5e, 0x7c, 0xc2, 0xe5, 0x37, 0x25, 0xbb, 0x8c, 0x93, 0x68, ++ 0x65, 0x3f, 0x0f, 0x3a, 0xfa, 0x43, 0xd9, 0x7b, 0x54, 0x64, 0x11, 0xdf, ++ 0x17, 0x5c, 0xfa, 0x07, 0x13, 0x79, 0xf3, 0x7a, 0x99, 0x9d, 0x41, 0xed, ++ 0xe0, 0x4a, 0xd1, 0xd9, 0x41, 0x5f, 0x99, 0x92, 0x15, 0x55, 0x1b, 0x21, ++ 0x43, 0x5c, 0x4a, 0x4a, 0x72, 0x09, 0x45, 0x0a, 0x64, 0x7e, 0xa6, 0x3f, ++ 0xea, 0x0f, 0x06, 0x7e, 0xa6, 0x5a, 0xc3, 0x5e, 0xa5, 0x97, 0x78, 0xaf, ++ 0x97, 0xa5, 0x34, 0xcd, 0xb3, 0xf0, 0x9c, 0xc9, 0xe2, 0xdb, 0x90, 0x4c, ++ 0x1e, 0x31, 0xe5, 0x65, 0xf6, 0xf3, 0xf3, 0x36, 0xce, 0xb8, 0x47, 0x2a, ++ 0x8b, 0x58, 0xaf, 0xff, 0x54, 0x66, 0xe6, 0xcb, 0x32, 0x3b, 0x7d, 0xb6, ++ 0xa1, 0xdf, 0x87, 0xf9, 0x4c, 0x63, 0xad, 0xb6, 0x9b, 0xb5, 0x9e, 0x94, ++ 0xea, 0xa6, 0xca, 0x03, 0x4b, 0xf5, 0xc9, 0xe2, 0x27, 0x6b, 0xb7, 0xe8, ++ 0xf7, 0x68, 0xd2, 0x63, 0xcb, 0x41, 0xdc, 0x6f, 0xf5, 0x88, 0xa9, 0xf2, ++ 0xe3, 0x96, 0xc2, 0xf7, 0x9f, 0xfb, 0xc0, 0xec, 0x33, 0xc6, 0x55, 0xde, ++ 0x78, 0x4d, 0x1e, 0xb0, 0x0e, 0xca, 0x93, 0xe6, 0x18, 0xea, 0xf3, 0x84, ++ 0x3c, 0x68, 0xad, 0x93, 0xec, 0x06, 0xde, 0x21, 0xe8, 0x35, 0x59, 0x2b, ++ 0xf9, 0x32, 0x66, 0xdd, 0x61, 0xfc, 0xb1, 0xf0, 0xf7, 0x5b, 0xfa, 0xf8, ++ 0x5f, 0xfa, 0xcc, 0xb3, 0x3f, 0x30, 0xe1, 0x8b, 0x14, 0x9c, 0x16, 0xc0, ++ 0x4d, 0x13, 0x6e, 0xd0, 0x78, 0x95, 0x70, 0x33, 0x5a, 0x08, 0xa7, 0x01, ++ 0x2e, 0x21, 0xe7, 0x68, 0xcf, 0x69, 0x1b, 0x7c, 0xa2, 0xde, 0xd9, 0x1e, ++ 0xfd, 0xb6, 0xb5, 0x0e, 0x71, 0xe1, 0xc6, 0xfe, 0xf3, 0xe1, 0xfe, 0x97, ++ 0xc3, 0xfd, 0x17, 0x57, 0xf7, 0x47, 0xb1, 0xe1, 0x57, 0xbe, 0x34, 0xd0, ++ 0x75, 0xbe, 0x16, 0xc0, 0x1f, 0x0c, 0xe9, 0xba, 0xb8, 0x4a, 0x57, 0x04, ++ 0x0f, 0x79, 0x2a, 0x9e, 0x19, 0x0f, 0x18, 0x17, 0xfa, 0x20, 0x47, 0xfe, ++ 0x66, 0x69, 0xb2, 0xaf, 0x33, 0x52, 0x51, 0xbd, 0x2a, 0x5d, 0x96, 0xd3, ++ 0x07, 0x65, 0xdc, 0xcc, 0x8d, 0x4c, 0x4a, 0x02, 0x3a, 0xdc, 0xa4, 0xfc, ++ 0xdc, 0x2c, 0x7c, 0x0a, 0x9f, 0x25, 0xeb, 0xe6, 0xb4, 0x5e, 0x6e, 0xa0, ++ 0x35, 0xf1, 0x3a, 0x69, 0x0c, 0x68, 0x4d, 0x6d, 0xbd, 0x41, 0x6b, 0x00, ++ 0x1f, 0xd0, 0x7a, 0xb9, 0xd6, 0x00, 0xbf, 0x94, 0x0c, 0xe1, 0x93, 0x0d, ++ 0xf0, 0xd4, 0x67, 0xc6, 0x44, 0xea, 0x33, 0x69, 0xbb, 0x4b, 0xf5, 0x71, ++ 0xd6, 0x15, 0xbe, 0xbf, 0xef, 0xd7, 0xb6, 0xfa, 0x92, 0x42, 0xac, 0x6c, ++ 0xe6, 0x6f, 0xe5, 0xd3, 0x8c, 0xa3, 0x7a, 0x6f, 0xb3, 0x6c, 0x83, 0xce, ++ 0xf2, 0xee, 0x82, 0x3e, 0xdd, 0x03, 0xc2, 0x3e, 0x9d, 0x2f, 0x4f, 0x5a, ++ 0xa4, 0xe5, 0x17, 0xfe, 0x89, 0xf4, 0x36, 0xab, 0x2a, 0xfd, 0x46, 0x33, ++ 0xce, 0x9f, 0xf5, 0x14, 0xce, 0x01, 0xd2, 0x72, 0xbc, 0xbf, 0xcf, 0x78, ++ 0x07, 0x7c, 0x8e, 0x4d, 0x6b, 0x32, 0x6b, 0xe6, 0x32, 0x67, 0x80, 0x63, ++ 0x17, 0xee, 0x66, 0x76, 0x88, 0xf4, 0x88, 0xec, 0x85, 0x7e, 0xcf, 0xaa, ++ 0x9c, 0x81, 0x7a, 0x9c, 0x1b, 0xaf, 0x20, 0x4e, 0xbf, 0xa1, 0xe2, 0xa9, ++ 0xef, 0x7f, 0x80, 0x98, 0x3a, 0xbe, 0x46, 0xf7, 0xf4, 0xa5, 0x40, 0xf7, ++ 0xf4, 0x25, 0xd4, 0x58, 0x87, 0x52, 0xd2, 0xb2, 0x00, 0xfb, 0x79, 0xbd, ++ 0x5b, 0xe9, 0x9f, 0xfe, 0x3a, 0x7b, 0xdd, 0xf0, 0x73, 0x87, 0x92, 0x62, ++ 0x1e, 0x52, 0x31, 0x42, 0xf9, 0xc1, 0xc9, 0x63, 0xf4, 0xa5, 0xa6, 0x6c, ++ 0x3d, 0xc4, 0xfb, 0x60, 0xae, 0x37, 0xb3, 0xbd, 0x0c, 0x1b, 0x61, 0xbf, ++ 0x4d, 0x5f, 0xf8, 0x50, 0xca, 0x26, 0xe5, 0xd0, 0x21, 0xad, 0x0b, 0x86, ++ 0x24, 0x16, 0xe0, 0x13, 0x16, 0x32, 0xd2, 0x04, 0xdb, 0xd2, 0x97, 0xd2, ++ 0x5a, 0xf5, 0x28, 0x63, 0x13, 0x7b, 0xc6, 0x03, 0x98, 0x67, 0x34, 0xda, ++ 0x8f, 0xbe, 0x44, 0x3d, 0x47, 0x58, 0x5a, 0xa2, 0x9e, 0x93, 0x8e, 0xc8, ++ 0x5e, 0xf0, 0xbe, 0x64, 0xaa, 0xbe, 0xed, 0x07, 0x16, 0x79, 0xf9, 0x67, ++ 0x71, 0xa6, 0xa3, 0x7f, 0xf3, 0x21, 0x1b, 0x74, 0x91, 0x4e, 0xc7, 0xda, ++ 0x3a, 0xb2, 0x22, 0x9f, 0x96, 0xaf, 0x4d, 0x9f, 0x8a, 0xaf, 0x29, 0xb7, ++ 0x91, 0x2f, 0xf2, 0xd4, 0x21, 0x4d, 0x8a, 0xaf, 0x88, 0x1f, 0x08, 0x1a, ++ 0x74, 0xf5, 0x1e, 0xca, 0x00, 0xff, 0x13, 0xf0, 0x01, 0xa8, 0xd1, 0x96, ++ 0x1e, 0xc7, 0x13, 0x29, 0xcd, 0x12, 0x79, 0x27, 0xaf, 0x57, 0xa4, 0x7a, ++ 0x34, 0xe2, 0xb3, 0x88, 0xf7, 0xb7, 0x65, 0xf2, 0xa8, 0xbf, 0x1f, 0xb1, ++ 0x96, 0xbd, 0xd3, 0x2e, 0x5d, 0xe9, 0xee, 0x5a, 0xde, 0xdf, 0x96, 0x40, ++ 0x3e, 0xec, 0xdf, 0xe2, 0x7d, 0x7e, 0xad, 0x2c, 0x1a, 0x7d, 0x47, 0x26, ++ 0xfc, 0x77, 0x2e, 0xf4, 0x13, 0x94, 0xd1, 0x15, 0x71, 0x8e, 0x1a, 0xf0, ++ 0x1d, 0x01, 0xbe, 0xe2, 0xea, 0xbf, 0x75, 0x69, 0xdc, 0x33, 0x00, 0xb8, ++ 0x1e, 0xc0, 0x91, 0xae, 0x65, 0xca, 0x0f, 0x3e, 0x67, 0x73, 0x83, 0xaf, ++ 0x69, 0xdc, 0x67, 0xc9, 0x01, 0xe4, 0x06, 0xe7, 0xad, 0x4f, 0xc8, 0xb5, ++ 0xc8, 0xfc, 0x6b, 0xb6, 0x3e, 0x0e, 0x9b, 0x6c, 0x82, 0x2f, 0x33, 0x64, ++ 0xa5, 0xd6, 0x2c, 0xb3, 0xc8, 0xb1, 0xe6, 0xe6, 0xe9, 0x0b, 0x49, 0x7b, ++ 0x2b, 0xd6, 0x03, 0xff, 0x45, 0x5f, 0xbb, 0x52, 0x43, 0x7c, 0x85, 0x6d, ++ 0xaf, 0xb0, 0x2f, 0xfe, 0x3f, 0x9d, 0x5b, 0x4d, 0x6c, 0x1c, 0x67, 0x19, ++ 0x7e, 0x77, 0x76, 0xfd, 0x17, 0x62, 0x67, 0x6c, 0xaf, 0x9d, 0xb5, 0x6b, ++ 0x9a, 0x5d, 0xef, 0xd8, 0x59, 0xc9, 0x0e, 0x9a, 0xa4, 0x16, 0x35, 0xa9, ++ 0x1b, 0x6f, 0x77, 0x63, 0x27, 0x29, 0x11, 0x24, 0x21, 0xad, 0x7a, 0x40, ++ 0x60, 0xd6, 0x29, 0xa4, 0x5c, 0xda, 0x14, 0x2a, 0x45, 0xa2, 0x95, 0xb7, ++ 0x6b, 0x87, 0xba, 0x68, 0x59, 0x6f, 0x5d, 0x43, 0x7a, 0x01, 0x2d, 0x6b, ++ 0xab, 0x05, 0xc9, 0xb2, 0x53, 0x95, 0x03, 0x87, 0x86, 0x04, 0xa7, 0x20, ++ 0x0e, 0x3d, 0x40, 0x51, 0x25, 0x0e, 0x3d, 0x44, 0x56, 0x4a, 0x11, 0x97, ++ 0xf6, 0x88, 0x54, 0x95, 0xe1, 0x79, 0xde, 0x6f, 0xc6, 0x5e, 0x6f, 0xdd, ++ 0x46, 0x70, 0x58, 0xcd, 0x7e, 0x33, 0xf3, 0xfd, 0xbe, 0x7f, 0xcf, 0xfb, ++ 0x33, 0xab, 0x7d, 0xb8, 0x3a, 0xb8, 0xc6, 0x71, 0x4d, 0xe1, 0x3a, 0x8c, ++ 0xeb, 0x30, 0xae, 0x58, 0x7f, 0x31, 0x86, 0x6b, 0x80, 0x87, 0x39, 0xd6, ++ 0xf6, 0xbe, 0x0b, 0x3a, 0x1f, 0xf3, 0x4a, 0xb4, 0x65, 0x11, 0x37, 0x0b, ++ 0x3f, 0x31, 0x33, 0x1c, 0xd4, 0x77, 0xfc, 0xc7, 0xb3, 0x1d, 0xfa, 0x9f, ++ 0xf9, 0xd0, 0x84, 0xe6, 0x17, 0xca, 0xb0, 0x0b, 0xaf, 0x74, 0xc9, 0x1e, ++ 0xc7, 0x9e, 0xd4, 0x58, 0xe9, 0x12, 0xda, 0xfc, 0x0f, 0xec, 0x14, 0x9d, ++ 0x83, 0x7d, 0xa2, 0xfe, 0xf4, 0xd0, 0x27, 0x07, 0x3d, 0xbe, 0x0f, 0xf2, ++ 0x97, 0x86, 0xde, 0xc6, 0xff, 0xca, 0x85, 0x2e, 0x63, 0x4b, 0x13, 0xf6, ++ 0x36, 0x2e, 0x0d, 0x6c, 0x55, 0x0a, 0x7d, 0x76, 0xcb, 0xcd, 0xc0, 0x06, ++ 0x96, 0x13, 0xe5, 0x0a, 0x64, 0xf0, 0xaf, 0xee, 0x8c, 0xe2, 0x49, 0xd2, ++ 0xe2, 0x0a, 0xf0, 0x7b, 0xb6, 0x44, 0xdc, 0xfb, 0x2c, 0x30, 0x35, 0xfc, ++ 0x91, 0x28, 0xfd, 0x4f, 0xda, 0x02, 0xe2, 0xdf, 0x3f, 0x60, 0x6d, 0xb4, ++ 0x03, 0x2f, 0x60, 0x3e, 0xec, 0x6b, 0xd9, 0xc3, 0x99, 0x9d, 0x00, 0x0e, ++ 0xf5, 0xbc, 0x88, 0x33, 0x21, 0xf1, 0x73, 0xd4, 0x39, 0x82, 0xfe, 0x26, ++ 0x26, 0x42, 0xac, 0x95, 0x3e, 0xa3, 0x39, 0x2a, 0x30, 0xd7, 0x5f, 0xd0, ++ 0xb7, 0x4b, 0x4c, 0x9c, 0xa3, 0x45, 0x73, 0xcd, 0x13, 0x25, 0x83, 0xa3, ++ 0x2d, 0xa7, 0x76, 0xbc, 0xfb, 0xfc, 0xf1, 0xf8, 0xdc, 0xd2, 0x71, 0xaa, ++ 0xd2, 0x6d, 0xe2, 0x90, 0x63, 0x29, 0xd8, 0x88, 0xa8, 0x6c, 0x80, 0x2e, ++ 0xb7, 0x40, 0x93, 0xb7, 0x8a, 0xe4, 0xf5, 0x21, 0xf0, 0x7d, 0x03, 0xf3, ++ 0x77, 0x18, 0x6b, 0x58, 0xe7, 0xde, 0x28, 0x42, 0x77, 0x52, 0xff, 0x59, ++ 0xa1, 0x6e, 0xe2, 0x51, 0xda, 0x41, 0x33, 0x4e, 0x9f, 0x79, 0x4f, 0x82, ++ 0x67, 0x9d, 0xba, 0x9e, 0xaa, 0xc6, 0x52, 0x78, 0x4e, 0xe0, 0xc1, 0x62, ++ 0xa7, 0xff, 0xce, 0xc7, 0x5d, 0xa6, 0xb6, 0x86, 0xf7, 0xb8, 0x8f, 0x61, ++ 0xc9, 0x94, 0x82, 0x7e, 0xed, 0xe8, 0xd7, 0x52, 0x33, 0xd6, 0xfe, 0xba, ++ 0x3d, 0x58, 0xfe, 0x1e, 0xf8, 0xbc, 0xde, 0x27, 0x4a, 0xc0, 0xa3, 0x0e, ++ 0xfc, 0x22, 0xda, 0x5f, 0xd2, 0x66, 0x04, 0xfd, 0x03, 0xfa, 0xf4, 0xf9, ++ 0xfe, 0x47, 0x62, 0x3e, 0x2f, 0xc0, 0x8b, 0x51, 0xd2, 0xc8, 0x85, 0x5c, ++ 0x5f, 0x8b, 0x4a, 0x9b, 0x2b, 0xe5, 0x62, 0x93, 0x58, 0x1d, 0x0d, 0x5a, ++ 0x0f, 0x12, 0xb7, 0x6a, 0xe7, 0xfc, 0xb6, 0x3f, 0x27, 0xfc, 0xc7, 0x45, ++ 0xe2, 0x74, 0xb5, 0x33, 0x78, 0x67, 0x6f, 0xdd, 0xda, 0x1e, 0xf1, 0xdf, ++ 0xe3, 0xf3, 0xb8, 0xe4, 0x81, 0x3f, 0xb3, 0x25, 0x78, 0x11, 0xd0, 0xdf, ++ 0xd6, 0x18, 0x73, 0x15, 0x8c, 0x09, 0x0d, 0xc5, 0x67, 0xb1, 0xc6, 0xbc, ++ 0x3d, 0xca, 0x38, 0x23, 0xc6, 0xe8, 0xa9, 0x1b, 0xe3, 0xb8, 0x3f, 0xc6, ++ 0x31, 0x29, 0x5c, 0x4d, 0x43, 0xd6, 0x46, 0x61, 0xdf, 0x93, 0xf6, 0x09, ++ 0xf9, 0x8a, 0x48, 0x3b, 0xee, 0xbd, 0xe6, 0x30, 0x17, 0xe5, 0x4d, 0xb8, ++ 0xa7, 0xb1, 0xee, 0x37, 0x61, 0x5b, 0x03, 0xcc, 0x53, 0x00, 0x46, 0x0f, ++ 0xc9, 0x53, 0x2e, 0xe3, 0x88, 0x79, 0x20, 0xb2, 0x84, 0x6d, 0x85, 0x86, ++ 0x52, 0x55, 0xe0, 0xba, 0x0a, 0x2c, 0x69, 0xc1, 0xe1, 0x3e, 0x5b, 0xa5, ++ 0x60, 0x87, 0xc6, 0xc3, 0xc0, 0x35, 0x99, 0x12, 0xe5, 0x48, 0x06, 0xc2, ++ 0x63, 0x8d, 0xc0, 0xa2, 0x9e, 0xbc, 0x0f, 0x55, 0x53, 0x28, 0xce, 0xcb, ++ 0xc6, 0xaa, 0x8d, 0xeb, 0x77, 0x40, 0x87, 0x57, 0xf0, 0xff, 0x4a, 0x94, ++ 0x35, 0x31, 0x22, 0xa3, 0xe0, 0xdd, 0xb8, 0xe2, 0x19, 0xe2, 0x88, 0x2a, ++ 0xec, 0xad, 0x05, 0x5b, 0x03, 0x5c, 0x35, 0x4a, 0x99, 0x7b, 0x61, 0xf9, ++ 0x8e, 0xbc, 0xb5, 0x94, 0xc0, 0x5c, 0xb4, 0xcb, 0xc7, 0xa9, 0x0f, 0xec, ++ 0xb9, 0x11, 0xdc, 0x5b, 0xa1, 0x2e, 0x43, 0x7b, 0x1d, 0x02, 0xd4, 0x01, ++ 0x8c, 0x00, 0x8c, 0xbd, 0xe9, 0x40, 0x6e, 0xf1, 0xfe, 0xc6, 0x52, 0x44, ++ 0x96, 0x1d, 0xe2, 0x22, 0x89, 0x67, 0xf0, 0xee, 0xc6, 0xca, 0xf3, 0xdd, ++ 0x26, 0xe6, 0xcf, 0xfe, 0x40, 0xf9, 0xc0, 0x75, 0x27, 0xb4, 0xef, 0xdd, ++ 0xe8, 0xcc, 0x35, 0xd5, 0xfa, 0x96, 0xd3, 0xb2, 0x41, 0x79, 0xd2, 0x38, ++ 0x39, 0xb1, 0xc1, 0xb3, 0xe0, 0x59, 0x62, 0x76, 0xfa, 0x01, 0xf8, 0xbf, ++ 0xca, 0xe7, 0xdc, 0x3b, 0xae, 0x95, 0x24, 0xce, 0x86, 0x72, 0x0f, 0x9f, ++ 0xfc, 0x20, 0xec, 0xa8, 0x45, 0x59, 0x2f, 0xa8, 0x2e, 0x28, 0x2c, 0x4c, ++ 0xc3, 0xa6, 0x30, 0x17, 0xdf, 0x03, 0x5e, 0x3c, 0x09, 0x5a, 0xba, 0x78, ++ 0xaf, 0xce, 0x96, 0xac, 0x15, 0x14, 0x97, 0x59, 0xaf, 0x1a, 0xbd, 0x66, ++ 0x55, 0x81, 0xd1, 0x20, 0x3f, 0xd6, 0x1a, 0x78, 0x0b, 0x32, 0x64, 0xad, ++ 0x45, 0x71, 0x85, 0x3e, 0x5e, 0x83, 0x5f, 0x01, 0xfd, 0x66, 0xad, 0xc1, ++ 0x27, 0x80, 0x7e, 0xb3, 0xd6, 0x52, 0xb8, 0x42, 0xc7, 0xaf, 0x05, 0x7a, ++ 0x8d, 0xe3, 0x73, 0x1d, 0x81, 0x7e, 0x21, 0x96, 0xa4, 0x7e, 0x09, 0xf0, ++ 0xa4, 0xe1, 0x85, 0x1f, 0x2f, 0x50, 0x87, 0x90, 0xaf, 0x93, 0xd0, 0x5b, ++ 0xe4, 0x05, 0x83, 0x25, 0x57, 0xca, 0xe6, 0xcc, 0x66, 0xd7, 0x6f, 0xa8, ++ 0x8d, 0x98, 0x14, 0x07, 0x3c, 0xc6, 0xb3, 0xc3, 0x33, 0xb5, 0x01, 0xd7, ++ 0x25, 0xad, 0x57, 0x9e, 0xd9, 0xef, 0x25, 0x0d, 0x3f, 0xf8, 0x27, 0xaa, ++ 0xb7, 0xb6, 0xe2, 0x63, 0xe0, 0xb1, 0x18, 0xce, 0x2f, 0x2e, 0x2f, 0xbe, ++ 0x7c, 0x47, 0x32, 0x3f, 0xa3, 0xde, 0x1a, 0x8a, 0xb5, 0x84, 0xa8, 0xab, ++ 0x3c, 0x59, 0x85, 0x6d, 0x3a, 0xe1, 0x26, 0x1e, 0x63, 0xbd, 0xe6, 0x14, ++ 0x78, 0xa5, 0xf1, 0x70, 0xc2, 0x8d, 0x87, 0x92, 0x8f, 0xb5, 0x84, 0x68, ++ 0x1b, 0x87, 0xec, 0x8b, 0x72, 0xc4, 0x8f, 0xa9, 0x34, 0xc9, 0x45, 0xc5, ++ 0xfe, 0x10, 0xdb, 0xd2, 0xc7, 0x1a, 0xef, 0xff, 0x60, 0x84, 0x67, 0x8d, ++ 0xf6, 0x9a, 0xc6, 0x3e, 0x9a, 0x3f, 0x18, 0x69, 0x90, 0x42, 0x97, 0xe7, ++ 0x3d, 0x7e, 0xf8, 0xdd, 0xa8, 0x89, 0xd5, 0x74, 0xef, 0x37, 0xba, 0xa0, ++ 0xb1, 0xcb, 0xb4, 0x4f, 0xe1, 0x4a, 0xde, 0xa6, 0xbd, 0xa5, 0x7d, 0x24, ++ 0xdd, 0x70, 0x5d, 0xe1, 0x7f, 0xda, 0xde, 0x79, 0xd8, 0x5e, 0xda, 0xcb, ++ 0x7d, 0x92, 0x65, 0xfe, 0xc8, 0xd2, 0xfb, 0x79, 0x83, 0xa5, 0xfd, 0xf7, ++ 0xca, 0x53, 0x32, 0x5b, 0x26, 0x86, 0xda, 0x80, 0x2d, 0x63, 0x9d, 0x1d, ++ 0x6d, 0xda, 0x0c, 0xec, 0x39, 0xf3, 0x92, 0x78, 0x56, 0x61, 0xbf, 0x44, ++ 0x2a, 0x6e, 0x61, 0xcf, 0x5b, 0x3c, 0x35, 0xdf, 0xcd, 0x9c, 0xe4, 0xf5, ++ 0x83, 0xa0, 0xfb, 0x4b, 0xf4, 0x2d, 0x06, 0x94, 0x47, 0x32, 0xbf, 0xe2, ++ 0xd9, 0x7b, 0xde, 0x49, 0x17, 0x6c, 0xd8, 0x6e, 0x64, 0x80, 0x38, 0xe0, ++ 0xab, 0x38, 0x97, 0x49, 0xf7, 0x0e, 0x6d, 0xf7, 0x87, 0x96, 0x33, 0x94, ++ 0xba, 0x18, 0xa2, 0x6c, 0xa3, 0xbd, 0x12, 0x96, 0x4a, 0x94, 0xfb, 0xc7, ++ 0x79, 0x85, 0x28, 0x3b, 0xbb, 0x9d, 0x43, 0xfd, 0x19, 0x1c, 0xc3, 0x19, ++ 0xf0, 0x2c, 0x83, 0x33, 0xe0, 0xff, 0x34, 0xe8, 0x45, 0x9f, 0x21, 0xa9, ++ 0x35, 0x31, 0x85, 0x75, 0x33, 0x37, 0x6b, 0x00, 0xb7, 0xd7, 0xcc, 0xf5, ++ 0x92, 0xa6, 0xd7, 0x25, 0xab, 0xf4, 0x9d, 0x97, 0x6c, 0xf9, 0xba, 0x4c, ++ 0x94, 0xe7, 0xe5, 0x94, 0x33, 0x8e, 0xfd, 0xde, 0xf6, 0xa6, 0x1d, 0xf5, ++ 0x55, 0x46, 0x73, 0x98, 0x7b, 0x7a, 0xb8, 0x47, 0xfe, 0x89, 0x7d, 0x5c, ++ 0x59, 0xb6, 0xe1, 0x57, 0xbb, 0xf2, 0xa2, 0xe6, 0x3e, 0xe8, 0x9f, 0x84, ++ 0xe8, 0xa7, 0x81, 0xef, 0x9b, 0x45, 0xba, 0x9c, 0xd8, 0xa6, 0x10, 0x53, ++ 0x36, 0x80, 0xd6, 0x71, 0x83, 0x9b, 0x6d, 0xf3, 0x7c, 0xf0, 0x25, 0x60, ++ 0x77, 0xf7, 0xdd, 0xee, 0x20, 0xc6, 0x69, 0xf0, 0xed, 0xdf, 0xfd, 0x5c, ++ 0x0f, 0xf4, 0x27, 0xd6, 0xf3, 0x5b, 0xd5, 0xb3, 0x0e, 0x78, 0xa9, 0x4f, ++ 0xde, 0x58, 0x8f, 0x69, 0xcc, 0xa3, 0xa1, 0xa4, 0x71, 0x40, 0xe8, 0xa8, ++ 0x11, 0xea, 0xae, 0xf1, 0x65, 0x97, 0xb1, 0x82, 0xa8, 0xfc, 0xad, 0x48, ++ 0x3d, 0x1c, 0x97, 0x77, 0x8a, 0x97, 0xb1, 0x9e, 0x44, 0x85, 0x31, 0xb9, ++ 0x5b, 0xe5, 0x3c, 0x71, 0x92, 0xe2, 0xf9, 0x8c, 0xfb, 0x03, 0xb5, 0x03, ++ 0x71, 0xab, 0xd0, 0xd9, 0xa0, 0xfa, 0xe6, 0x49, 0xcd, 0x19, 0xc6, 0xad, ++ 0x3e, 0xb9, 0xb5, 0xc4, 0xfd, 0xa6, 0x30, 0x76, 0x34, 0x94, 0x5d, 0xa1, ++ 0x5d, 0x4a, 0xc6, 0x72, 0x56, 0x93, 0x3c, 0x1e, 0x3d, 0xa0, 0xbe, 0x27, ++ 0xf4, 0x33, 0x6c, 0xe1, 0x90, 0x9d, 0x63, 0x0d, 0x8c, 0xda, 0x9f, 0x58, ++ 0x9d, 0x9e, 0x7d, 0xd2, 0xd7, 0xb3, 0x7c, 0x36, 0x0a, 0x9a, 0xd2, 0x16, ++ 0xb1, 0x9e, 0x2d, 0x09, 0x9b, 0x67, 0xd3, 0xf7, 0x52, 0x1d, 0xfe, 0xf4, ++ 0xea, 0x45, 0xe0, 0xef, 0x21, 0xfb, 0x1c, 0xed, 0xaa, 0x3d, 0x82, 0x77, ++ 0x39, 0xff, 0x17, 0xeb, 0xc6, 0xfa, 0xa6, 0x3f, 0x16, 0x9f, 0x43, 0xce, ++ 0xe1, 0x9b, 0x4f, 0x17, 0x99, 0x37, 0x35, 0x6b, 0xdd, 0xf9, 0xee, 0xd9, ++ 0xad, 0x79, 0xc9, 0xe3, 0x85, 0xa2, 0xa9, 0x83, 0x2a, 0x00, 0x0b, 0x7d, ++ 0xa3, 0x83, 0x73, 0x72, 0xbe, 0x36, 0xc9, 0x3c, 0x0a, 0xfd, 0x52, 0xe2, ++ 0x2f, 0xef, 0xd7, 0x79, 0xc2, 0x5f, 0x89, 0xf6, 0xee, 0x62, 0x9b, 0x1e, ++ 0xf4, 0xc7, 0x7b, 0x07, 0x3c, 0x14, 0xad, 0x79, 0x9f, 0xf1, 0x14, 0xb6, ++ 0x61, 0x87, 0x56, 0x79, 0xf5, 0xbc, 0x0e, 0xa7, 0x51, 0xce, 0xd9, 0xf7, ++ 0xd4, 0x8d, 0x71, 0x08, 0xf7, 0x0c, 0x26, 0x08, 0x97, 0x42, 0x3e, 0xb6, ++ 0x38, 0x40, 0xdc, 0xe4, 0xff, 0x67, 0xde, 0x84, 0xef, 0xf7, 0xd6, 0xed, ++ 0xe3, 0xc0, 0x96, 0x1d, 0x8e, 0x5b, 0xd4, 0x9d, 0xaf, 0xe1, 0x19, 0x79, ++ 0xc8, 0x53, 0x1c, 0x1f, 0x01, 0xce, 0xcf, 0x42, 0x17, 0x44, 0x9d, 0xa6, ++ 0x18, 0x30, 0x97, 0xc6, 0x0e, 0xe2, 0x56, 0xab, 0xfa, 0xdb, 0x37, 0xc8, ++ 0x27, 0xc0, 0x9b, 0x6f, 0xec, 0xd0, 0xe9, 0x29, 0xf0, 0x32, 0xc6, 0xdf, ++ 0xc3, 0xf1, 0x53, 0xfe, 0x39, 0x27, 0xdc, 0xbc, 0xf5, 0x65, 0xc9, 0x2d, ++ 0x19, 0xfe, 0xcb, 0x38, 0xe0, 0xbd, 0x36, 0xb4, 0x57, 0x68, 0x13, 0x3e, ++ 0x6b, 0x9c, 0xc0, 0x36, 0xa4, 0xd4, 0x36, 0xcc, 0x2e, 0x90, 0x3f, 0xc9, ++ 0x97, 0x01, 0x3f, 0x06, 0x3a, 0x8f, 0x3c, 0x4a, 0x3d, 0xeb, 0xca, 0x4b, ++ 0x0b, 0x3c, 0x9b, 0xb4, 0xe6, 0x00, 0x07, 0x16, 0xa7, 0x35, 0x37, 0xda, ++ 0x5f, 0x4a, 0xbc, 0x92, 0x97, 0x71, 0xb9, 0xe6, 0xf2, 0xcc, 0x12, 0x95, ++ 0xa9, 0x70, 0x6b, 0xcd, 0xfe, 0xcf, 0xf9, 0x67, 0xe6, 0x28, 0x5f, 0xf5, ++ 0x97, 0x9e, 0xdd, 0xa2, 0xf7, 0x94, 0xd5, 0x56, 0x77, 0x4e, 0x01, 0x86, ++ 0x8b, 0x0b, 0xf1, 0x43, 0xa4, 0x83, 0x7d, 0x38, 0x2f, 0x31, 0x1f, 0xe7, ++ 0xa2, 0x6d, 0xbd, 0x97, 0xb9, 0x77, 0xa1, 0x1f, 0x17, 0x79, 0xd4, 0x60, ++ 0x8b, 0x29, 0xeb, 0x2c, 0xce, 0x6d, 0x8f, 0xd6, 0xd9, 0xcd, 0xfe, 0xfc, ++ 0x13, 0xf4, 0x9f, 0xf2, 0xf1, 0xf9, 0x08, 0xc6, 0xe3, 0xde, 0x29, 0x53, ++ 0xc5, 0xc3, 0xe4, 0xcd, 0x09, 0xcd, 0x2d, 0xb1, 0x0f, 0xe5, 0x96, 0x67, ++ 0x44, 0x3a, 0x5c, 0x8e, 0x19, 0x7b, 0x7a, 0xa8, 0x6e, 0x3d, 0x49, 0x7f, ++ 0x3d, 0xc1, 0xf3, 0x06, 0x89, 0x74, 0x53, 0xa7, 0x45, 0x25, 0x59, 0xa2, ++ 0x8f, 0x02, 0x5b, 0x75, 0x86, 0x63, 0xdd, 0x5d, 0xf7, 0x4e, 0xfd, 0x9f, ++ 0xba, 0x77, 0xca, 0x9a, 0xd7, 0x35, 0x36, 0x38, 0xff, 0x0b, 0x1d, 0x6b, ++ 0x6b, 0xb7, 0x0d, 0xdd, 0x5e, 0x58, 0xa0, 0x7d, 0x4a, 0x6b, 0x6d, 0xf9, ++ 0x3f, 0x8a, 0x3c, 0x4b, 0xae, 0xf1, 0x1a, 0xd7, 0x38, 0xbe, 0xa1, 0xb5, ++ 0x56, 0x5f, 0x53, 0x99, 0xbd, 0xb2, 0x40, 0x9d, 0xd2, 0x2a, 0xcb, 0xe5, ++ 0x40, 0xaf, 0x9c, 0xf2, 0x31, 0x6d, 0xa1, 0xb3, 0x11, 0x72, 0x72, 0xd2, ++ 0xb5, 0xb4, 0xce, 0xcc, 0x7a, 0x84, 0xf7, 0xfa, 0xa4, 0xba, 0x44, 0x3b, ++ 0x9b, 0x84, 0x5f, 0x11, 0x0d, 0x55, 0x57, 0x98, 0xbb, 0x65, 0x4d, 0xc3, ++ 0x38, 0x6b, 0x5f, 0x71, 0x76, 0xb3, 0x90, 0xaf, 0x18, 0xfc, 0x7e, 0x62, ++ 0x78, 0xc6, 0xc7, 0xea, 0xe9, 0x3d, 0xba, 0x85, 0x01, 0x77, 0xd2, 0xf9, ++ 0x3a, 0xce, 0x9b, 0x7c, 0xed, 0xd8, 0xb7, 0x60, 0x27, 0xb3, 0x51, 0xfe, ++ 0xcf, 0x01, 0xfb, 0xd3, 0xd7, 0x88, 0xab, 0xaf, 0x51, 0xad, 0x8c, 0xc9, ++ 0xbc, 0xf2, 0x7e, 0xab, 0x1f, 0x4b, 0x6a, 0x55, 0xfe, 0x20, 0x8f, 0x4d, ++ 0x29, 0xe6, 0x1e, 0x51, 0x3d, 0x55, 0x28, 0x0e, 0x99, 0x9a, 0x08, 0x3b, ++ 0xe6, 0xd7, 0x2e, 0xd7, 0xce, 0x1f, 0xf3, 0xe7, 0x7f, 0xdf, 0xa7, 0xaf, ++ 0xad, 0x3a, 0x46, 0xcf, 0xda, 0x4a, 0x6a, 0x8c, 0x71, 0x76, 0x81, 0xfc, ++ 0x41, 0x3e, 0xa1, 0x9e, 0x0b, 0xde, 0x0b, 0x68, 0x12, 0xb4, 0xf9, 0x3e, ++ 0x79, 0x3e, 0xc0, 0x24, 0xb1, 0x1a, 0xf9, 0x0c, 0xee, 0x05, 0x34, 0xe2, ++ 0xb3, 0x5a, 0x3b, 0x40, 0x59, 0x8b, 0x33, 0x27, 0xb1, 0x25, 0x6f, 0x1d, ++ 0xa5, 0x6d, 0xda, 0x64, 0x8e, 0x70, 0xfd, 0xb3, 0x8c, 0x77, 0x43, 0xc6, ++ 0x76, 0xa3, 0xcf, 0x73, 0x4a, 0x9f, 0x29, 0xd0, 0xa7, 0x43, 0xf5, 0x3e, ++ 0x7d, 0xbc, 0xcb, 0x3e, 0xcf, 0xb5, 0xe2, 0xcc, 0x18, 0x97, 0x85, 0x7e, ++ 0x3b, 0x4f, 0x3d, 0xdf, 0xd5, 0x43, 0xfd, 0xc2, 0x98, 0x62, 0xfa, 0xcc, ++ 0x5e, 0xe8, 0x30, 0xb6, 0x0f, 0x2a, 0x06, 0x31, 0x3e, 0x56, 0x5c, 0x63, ++ 0x8b, 0x61, 0xe8, 0xe4, 0x6a, 0x11, 0xf8, 0x8c, 0xb5, 0x5f, 0x3b, 0xe8, ++ 0x75, 0xc9, 0x3f, 0xaf, 0x13, 0x3d, 0xa4, 0x0f, 0xe5, 0x80, 0xba, 0xb2, ++ 0x1d, 0xe3, 0x9d, 0x8d, 0x3a, 0xe0, 0xb1, 0x07, 0x70, 0x7f, 0x40, 0x7d, ++ 0x88, 0x30, 0xe4, 0x7c, 0xb3, 0xd8, 0xed, 0xfb, 0x6d, 0x0e, 0xda, 0xf0, ++ 0x55, 0x8b, 0x1d, 0xf4, 0x23, 0xd0, 0x4e, 0x49, 0x63, 0x09, 0x3e, 0x2b, ++ 0x74, 0xf7, 0x86, 0xda, 0xa0, 0x61, 0x3c, 0xff, 0x02, 0xe3, 0xd7, 0x5a, ++ 0x3b, 0xba, 0x59, 0xf4, 0xeb, 0x94, 0xa2, 0x83, 0x7a, 0xa6, 0xd5, 0x22, ++ 0xe3, 0xea, 0x43, 0xea, 0xcb, 0xd2, 0x3e, 0x15, 0x16, 0xfa, 0x6b, 0xd6, ++ 0x75, 0x5a, 0xce, 0xee, 0x58, 0x13, 0xe9, 0xd1, 0x6a, 0xea, 0x6e, 0xdc, ++ 0x49, 0x8c, 0x81, 0xb3, 0x5d, 0xe0, 0x7d, 0xfa, 0xd5, 0xc0, 0xf4, 0x65, ++ 0x63, 0x1f, 0x0a, 0x15, 0x47, 0xeb, 0x70, 0xc2, 0x63, 0xab, 0x38, 0x67, ++ 0x62, 0xd4, 0xdb, 0xc0, 0xe5, 0x29, 0x9c, 0x2f, 0x71, 0xb8, 0x37, 0x33, ++ 0xe7, 0xa6, 0x99, 0xeb, 0x81, 0x7d, 0x9b, 0x91, 0x2c, 0xfc, 0x84, 0x6c, ++ 0xb8, 0x8d, 0xf1, 0x65, 0x60, 0xc5, 0xbc, 0x1f, 0x8b, 0x1c, 0x66, 0x0c, ++ 0x55, 0x16, 0x57, 0xb8, 0x2f, 0xca, 0xbe, 0xf1, 0xc5, 0xab, 0x45, 0xee, ++ 0xc5, 0xc4, 0x25, 0xd8, 0xb6, 0x4a, 0x2e, 0xae, 0x3c, 0xa7, 0x11, 0x5c, ++ 0x8f, 0x42, 0x5e, 0xf8, 0x2e, 0xae, 0x2b, 0xb7, 0xe5, 0x4f, 0x4b, 0x81, ++ 0xad, 0x0f, 0xc9, 0x5b, 0x8e, 0x37, 0x33, 0xeb, 0x76, 0xf2, 0x7c, 0xdc, ++ 0x3c, 0x73, 0xb5, 0x8e, 0xe3, 0x16, 0xc4, 0xf3, 0x36, 0xdc, 0x8d, 0x4e, ++ 0x93, 0xd7, 0xa6, 0x7e, 0x98, 0xc3, 0x1e, 0x6f, 0xde, 0x67, 0x89, 0xa1, ++ 0x2d, 0xe9, 0x76, 0xe3, 0x73, 0x6d, 0x43, 0xa0, 0x1f, 0xc9, 0xab, 0xe4, ++ 0xd9, 0xdb, 0x32, 0xa9, 0xf6, 0x60, 0xb7, 0x7e, 0xb5, 0x3a, 0x24, 0xc0, ++ 0xbb, 0xd4, 0xf7, 0xe4, 0xd3, 0x98, 0xfa, 0x0b, 0x83, 0xa5, 0x7a, 0x9d, ++ 0xf1, 0x2d, 0xf2, 0x65, 0x7e, 0x77, 0xbe, 0x7c, 0xcc, 0xd7, 0x1b, 0xa3, ++ 0x8a, 0xa5, 0xd3, 0x36, 0xf5, 0x87, 0xa3, 0x35, 0x11, 0xd3, 0x57, 0x6b, ++ 0x75, 0x34, 0xfd, 0x40, 0xa3, 0x5b, 0xf4, 0x5b, 0x03, 0xc5, 0xc6, 0x96, ++ 0xf4, 0x2f, 0x36, 0xa8, 0xef, 0x98, 0x2c, 0x75, 0xc9, 0xd4, 0x99, 0xb0, ++ 0x24, 0x17, 0xaf, 0xf7, 0x18, 0xec, 0x4b, 0xde, 0x84, 0x2c, 0xea, 0x3d, ++ 0xb6, 0xff, 0x88, 0xfb, 0xfb, 0x84, 0x73, 0x1b, 0x5e, 0x87, 0xac, 0x9f, ++ 0x0f, 0x9e, 0xd9, 0x75, 0xfc, 0x7b, 0xd4, 0xe7, 0x5f, 0x3e, 0xb7, 0x4c, ++ 0x1e, 0x04, 0xef, 0xf6, 0x2f, 0x72, 0x8d, 0xa6, 0x5f, 0xff, 0xa2, 0xf1, ++ 0xdf, 0x77, 0xf6, 0x1b, 0xde, 0xea, 0x87, 0xe7, 0xc0, 0xc2, 0x66, 0xec, ++ 0xc9, 0x51, 0x60, 0xbc, 0x61, 0xd6, 0xdc, 0xd0, 0x9e, 0x0f, 0x80, 0xdb, ++ 0x28, 0x0b, 0x09, 0x9f, 0x1f, 0xa9, 0x8b, 0x3a, 0x7c, 0x5d, 0xb4, 0x6d, ++ 0x7f, 0xb2, 0xa6, 0xb6, 0x81, 0x31, 0x92, 0x1a, 0xfb, 0x13, 0xee, 0xfd, ++ 0xb4, 0xfd, 0xd9, 0xe7, 0x8f, 0x13, 0x3c, 0x0b, 0x74, 0x4e, 0xd0, 0x0e, ++ 0x74, 0x4e, 0x3d, 0xc6, 0x0d, 0x68, 0x5f, 0x7b, 0xbf, 0xd6, 0x07, 0x1c, ++ 0xf3, 0x7d, 0x7d, 0x4b, 0x65, 0xeb, 0xf5, 0x2d, 0x1f, 0x9f, 0x34, 0x4e, ++ 0x80, 0xf5, 0x8a, 0x90, 0xfb, 0x4f, 0xd4, 0xa7, 0xbe, 0x72, 0x35, 0xad, ++ 0x71, 0x9e, 0xaa, 0xd2, 0xfa, 0x39, 0xad, 0x3b, 0x98, 0x5b, 0x38, 0x19, ++ 0xf5, 0xeb, 0x1b, 0xb0, 0xa7, 0xb7, 0x9f, 0xc9, 0xf8, 0x98, 0x26, 0x2d, ++ 0x6d, 0xdd, 0x8c, 0x0b, 0xb0, 0xee, 0xa8, 0xc5, 0xf9, 0x91, 0x9c, 0x32, ++ 0x38, 0xa9, 0xb9, 0x79, 0xec, 0xbd, 0x67, 0x9a, 0x7f, 0x1a, 0xf0, 0x39, ++ 0xf9, 0xe7, 0xed, 0x67, 0xa6, 0xcb, 0xde, 0x78, 0xe4, 0xf0, 0x90, 0x5d, ++ 0x10, 0xd6, 0x09, 0x8f, 0xcb, 0xf7, 0xb4, 0xce, 0xe5, 0xd7, 0x78, 0x7e, ++ 0x9a, 0xfe, 0x65, 0x22, 0xa2, 0xb5, 0xeb, 0x89, 0xd8, 0x05, 0xc8, 0x5e, ++ 0xce, 0x65, 0x5d, 0xf1, 0x5e, 0xad, 0x2f, 0xae, 0x0a, 0x71, 0x16, 0x73, ++ 0xe8, 0x97, 0xe5, 0xbb, 0xee, 0x80, 0xbb, 0x21, 0x06, 0xff, 0xe6, 0x34, ++ 0x17, 0xd4, 0x24, 0x17, 0xdc, 0x48, 0x73, 0x66, 0xdd, 0xf0, 0xfc, 0xf1, ++ 0x70, 0xba, 0x65, 0xce, 0x89, 0x36, 0x4f, 0xae, 0x43, 0xa6, 0xd7, 0x61, ++ 0x0b, 0xd6, 0x63, 0xa1, 0xec, 0x2a, 0xf7, 0x1e, 0x36, 0x35, 0x0b, 0xea, ++ 0x7b, 0x51, 0xbf, 0x3c, 0x28, 0x9b, 0xf6, 0x41, 0xd9, 0x4c, 0xf1, 0xdb, ++ 0xa0, 0x23, 0x68, 0xf7, 0x2b, 0x26, 0xde, 0x84, 0x2e, 0xda, 0x4c, 0x35, ++ 0x2b, 0x0f, 0xaa, 0x8f, 0x06, 0x1d, 0xb6, 0x69, 0x53, 0x77, 0xdd, 0xcb, ++ 0x2b, 0x71, 0x36, 0xe8, 0xc0, 0x7a, 0x86, 0x43, 0x68, 0x53, 0xe7, 0xd9, ++ 0x75, 0xf7, 0x7b, 0xd1, 0xbe, 0x0f, 0x63, 0x34, 0xea, 0x1e, 0x2d, 0xe7, ++ 0xb0, 0xc9, 0xaf, 0xee, 0x78, 0xa7, 0xbd, 0xae, 0x7d, 0x71, 0x3f, 0x7d, ++ 0x9a, 0xb8, 0xf5, 0x0b, 0xd2, 0x38, 0x9f, 0x96, 0x7f, 0xc5, 0x76, 0xb6, ++ 0x17, 0x7b, 0x76, 0xb6, 0xdb, 0xa4, 0xa5, 0x8b, 0xa4, 0xd8, 0x57, 0xf7, ++ 0x5e, 0xc0, 0x43, 0x41, 0x7b, 0x3f, 0xf5, 0x0a, 0x6d, 0x9a, 0xfa, 0x53, ++ 0x9b, 0x51, 0xce, 0xf5, 0x7c, 0x5d, 0x1f, 0xfe, 0x67, 0x1f, 0xf6, 0x65, ++ 0x6c, 0xef, 0x97, 0x86, 0xcf, 0x2c, 0xc6, 0x05, 0x18, 0xdb, 0x08, 0x69, ++ 0x3e, 0xf5, 0xd3, 0xbe, 0x56, 0x42, 0xbf, 0x53, 0xd9, 0x9d, 0xd7, 0x02, ++ 0x3d, 0x12, 0xf3, 0xe3, 0x0d, 0x26, 0x27, 0x65, 0x62, 0xc2, 0xa4, 0x9d, ++ 0xe6, 0xa4, 0x62, 0xb7, 0x40, 0xe7, 0xc7, 0x41, 0xe7, 0x89, 0x30, 0xfd, ++ 0x42, 0xe6, 0x9e, 0x1c, 0xc9, 0xae, 0x93, 0xde, 0xb4, 0xf9, 0xe4, 0x4d, ++ 0x60, 0x8c, 0x75, 0xea, 0x14, 0x0b, 0xf8, 0x68, 0x0c, 0x6b, 0x7c, 0x13, ++ 0xf7, 0x2d, 0x3f, 0x1f, 0x3b, 0x02, 0x7b, 0xe7, 0xe2, 0x47, 0xba, 0xc3, ++ 0xdf, 0x5f, 0x26, 0x8d, 0x59, 0x33, 0xc5, 0x38, 0x41, 0x5a, 0xeb, 0xae, ++ 0xf9, 0xcd, 0x4e, 0xce, 0x4e, 0x6b, 0xfd, 0xaa, 0x53, 0x3a, 0x24, 0xf9, ++ 0x33, 0x69, 0xc5, 0x06, 0xfd, 0xb0, 0x5d, 0xb3, 0xee, 0x31, 0x99, 0x7b, ++ 0xed, 0x00, 0xe4, 0x94, 0x31, 0x00, 0x8d, 0x6f, 0x78, 0x0d, 0xca, 0xd3, ++ 0xc4, 0x23, 0x8c, 0xc9, 0x99, 0x1c, 0xb7, 0x91, 0xd9, 0x96, 0x5e, 0x69, ++ 0x3b, 0x26, 0xe5, 0xab, 0xb6, 0xd6, 0x7a, 0xa4, 0xe5, 0x13, 0x8f, 0x34, ++ 0xcc, 0x9d, 0x8f, 0x43, 0x4f, 0x11, 0xd7, 0x0f, 0x46, 0xcd, 0x99, 0x7e, ++ 0xd8, 0x4b, 0xff, 0x38, 0x59, 0xaa, 0x1d, 0x43, 0xeb, 0x43, 0xf0, 0xec, ++ 0xe1, 0xfd, 0x46, 0x7e, 0xe8, 0x2b, 0xdf, 0xf1, 0xd2, 0x51, 0xce, 0xc9, ++ 0x77, 0x99, 0xef, 0x25, 0xaf, 0x70, 0x6d, 0x1f, 0xfb, 0x7c, 0x7d, 0x14, ++ 0xe3, 0xc5, 0xa5, 0x7f, 0x2d, 0xad, 0xfe, 0xcf, 0xec, 0x0e, 0x7f, 0xd6, ++ 0xc4, 0x0e, 0x8c, 0x4f, 0x7b, 0x53, 0x2e, 0xac, 0x92, 0x4e, 0xb4, 0xfd, ++ 0x21, 0xf9, 0x8d, 0x33, 0x64, 0x3f, 0xa1, 0x35, 0xb2, 0x89, 0x34, 0x73, ++ 0x35, 0x7b, 0x9c, 0xa4, 0xbd, 0x2c, 0x91, 0xd1, 0x87, 0x85, 0xdf, 0x43, ++ 0xb0, 0x96, 0x61, 0xc8, 0x7d, 0x42, 0x82, 0x7a, 0x86, 0x81, 0x74, 0x53, ++ 0xe8, 0xdf, 0xde, 0xcd, 0xf3, 0x7c, 0xc7, 0xff, 0x66, 0x30, 0x44, 0xba, ++ 0xbd, 0x77, 0x2f, 0x6b, 0x7a, 0x77, 0xc6, 0x02, 0x1f, 0x7a, 0xf2, 0xdc, ++ 0x48, 0x62, 0x9e, 0xfe, 0x6c, 0x83, 0xe3, 0xf5, 0x9a, 0xbd, 0xe6, 0xf3, ++ 0xed, 0xa2, 0xb9, 0xb4, 0x4b, 0x1f, 0x38, 0xfc, 0x66, 0x32, 0x11, 0x6b, ++ 0xb2, 0x18, 0x13, 0xd7, 0xef, 0x92, 0xa4, 0xea, 0x30, 0xfe, 0x86, 0x36, ++ 0xf0, 0xc4, 0xab, 0xc3, 0x96, 0x3c, 0x14, 0x49, 0xc7, 0x2d, 0x19, 0x8c, ++ 0x2f, 0x0a, 0xe6, 0x64, 0xae, 0x65, 0x35, 0x91, 0xe7, 0xfb, 0x91, 0x12, ++ 0xc7, 0x8b, 0xab, 0xef, 0x92, 0x1c, 0xf4, 0xbc, 0x4b, 0xae, 0x84, 0x92, ++ 0x5f, 0x7a, 0xdf, 0x63, 0x8e, 0xdc, 0x5a, 0xfb, 0xbc, 0x5a, 0xf8, 0xf2, ++ 0xf7, 0x4d, 0x7d, 0xdb, 0xcd, 0x4b, 0xfd, 0xab, 0x6c, 0x7f, 0xf4, 0x75, ++ 0xbf, 0x36, 0x0e, 0xed, 0x46, 0xbf, 0xce, 0xe7, 0xcf, 0x97, 0xfa, 0x2b, ++ 0x1d, 0xf7, 0x18, 0x5f, 0x9c, 0xd8, 0x2b, 0xf0, 0x6f, 0xe2, 0x3b, 0xea, ++ 0x9e, 0xce, 0x2e, 0x9c, 0x0c, 0x9d, 0x5c, 0xb0, 0x96, 0x9a, 0x99, 0x1f, ++ 0x3b, 0xe2, 0x49, 0xe7, 0xe1, 0x20, 0x86, 0xc5, 0x98, 0x97, 0x48, 0xfb, ++ 0xda, 0x71, 0x93, 0x0f, 0x59, 0xb3, 0x14, 0x27, 0x75, 0xbc, 0xca, 0x38, ++ 0x56, 0x54, 0x75, 0x43, 0xe7, 0x1a, 0xeb, 0x9d, 0xba, 0x24, 0xa7, 0x3a, ++ 0xa3, 0x4b, 0xf5, 0x81, 0xe1, 0xbb, 0x0e, 0x8d, 0xd1, 0x12, 0x4b, 0xdd, ++ 0x58, 0x18, 0xeb, 0x63, 0x8d, 0xca, 0x1b, 0x0b, 0x4f, 0xa1, 0x4d, 0x3d, ++ 0x73, 0x7f, 0xdd, 0xfd, 0xda, 0x7c, 0x6d, 0xc2, 0xee, 0xb7, 0xea, 0x73, ++ 0xb5, 0xbc, 0x57, 0x9f, 0xa3, 0x7d, 0x53, 0xa6, 0xba, 0x99, 0x97, 0x0d, ++ 0x62, 0xf1, 0xae, 0x1f, 0x8b, 0x7f, 0xa0, 0x8f, 0x3c, 0x08, 0xdf, 0x67, ++ 0x2a, 0x32, 0xd6, 0x3c, 0x3c, 0x5b, 0x0c, 0x7f, 0xb4, 0x1d, 0x57, 0x45, ++ 0x7b, 0x75, 0x2b, 0x77, 0x8e, 0x67, 0x3f, 0x04, 0x26, 0x29, 0x00, 0x5f, ++ 0xe4, 0x83, 0x7a, 0x74, 0x3c, 0xdf, 0xea, 0x7f, 0x97, 0x35, 0xed, 0xd1, ++ 0xbc, 0x7b, 0xff, 0x8e, 0xbc, 0xfb, 0xd1, 0x3e, 0xe2, 0xcc, 0xc2, 0xfa, ++ 0x76, 0xdf, 0x06, 0xbf, 0xef, 0xc4, 0x5d, 0xf7, 0x53, 0x2b, 0x33, 0x57, ++ 0x54, 0xff, 0xce, 0xae, 0xcf, 0x4b, 0xce, 0xe9, 0x90, 0xec, 0x52, 0x60, ++ 0x27, 0xbc, 0xf1, 0x69, 0x37, 0xdf, 0x13, 0x16, 0xf6, 0xe7, 0x7c, 0x01, ++ 0x46, 0xe3, 0xf8, 0x7b, 0x7d, 0x9c, 0x46, 0x9b, 0x60, 0xf0, 0x9e, 0x19, ++ 0xeb, 0x69, 0xc5, 0x8e, 0x73, 0x7a, 0xcf, 0x36, 0xf1, 0x11, 0xc5, 0x86, ++ 0x8f, 0xfa, 0x39, 0x8b, 0xda, 0xdc, 0xf9, 0x67, 0xd1, 0x9a, 0x74, 0x0e, ++ 0xce, 0x25, 0xef, 0x35, 0x42, 0x46, 0x07, 0x59, 0x8f, 0xb3, 0xb5, 0x1f, ++ 0xda, 0x35, 0xb5, 0x5f, 0xba, 0xd7, 0x49, 0x7f, 0xaf, 0x61, 0xac, 0x79, ++ 0xba, 0x18, 0xbc, 0x33, 0x23, 0x07, 0x8f, 0x24, 0x62, 0x49, 0x4b, 0xd7, ++ 0xae, 0x36, 0x2e, 0xe3, 0xce, 0xc0, 0x76, 0xd1, 0xce, 0xa9, 0xee, 0x03, ++ 0xd6, 0xa5, 0xee, 0xa3, 0x0d, 0x53, 0xbb, 0x17, 0x2f, 0x60, 0x2f, 0xd9, ++ 0x75, 0xcd, 0x5f, 0xc4, 0x4e, 0x84, 0x13, 0xe5, 0x9c, 0xea, 0x43, 0xee, ++ 0x85, 0x6b, 0x87, 0xcd, 0x0e, 0xd5, 0xe6, 0xa6, 0xe8, 0x9f, 0x32, 0x8f, ++ 0x43, 0x0c, 0x2c, 0xf2, 0x3a, 0x64, 0xe0, 0xda, 0x0a, 0xe5, 0x32, 0xdc, ++ 0x6d, 0x7c, 0xcc, 0x8d, 0xfb, 0x2d, 0xe9, 0xd6, 0x7c, 0x6f, 0x01, 0x67, ++ 0x0a, 0x0c, 0x36, 0x1e, 0x3e, 0x02, 0x3f, 0x43, 0xeb, 0x2c, 0x18, 0xa3, ++ 0x9d, 0x86, 0x4f, 0x5a, 0x1b, 0x57, 0x82, 0x1e, 0x39, 0xc3, 0xfb, 0x39, ++ 0x9c, 0xdb, 0x76, 0xae, 0xa7, 0x50, 0x99, 0xd3, 0x78, 0x6e, 0x75, 0xa5, ++ 0x55, 0x6d, 0x4a, 0xb5, 0x32, 0x80, 0x73, 0x91, 0x83, 0xd6, 0x58, 0xc1, ++ 0xbf, 0xdf, 0x20, 0x95, 0x0a, 0xdb, 0xd2, 0xd7, 0xa8, 0x3c, 0x15, 0xe4, ++ 0xb3, 0x6c, 0x59, 0x06, 0x1e, 0xae, 0xac, 0x3a, 0xf8, 0xa5, 0xf0, 0x1b, ++ 0xc6, 0xef, 0xb4, 0x64, 0x4a, 0xc4, 0xe8, 0xcc, 0x5f, 0xb5, 0xd6, 0xcd, ++ 0xdf, 0xa0, 0xdf, 0xa0, 0xb0, 0xae, 0xab, 0xe0, 0xfb, 0x79, 0x85, 0xca, ++ 0x6e, 0xf8, 0x95, 0xf1, 0xe1, 0x94, 0xaf, 0x0f, 0x7f, 0xe7, 0xd7, 0x5d, ++ 0xfe, 0x17, 0x55, 0xe6, 0x5c, 0xa1, 0x10, 0x71, 0x00, 0x00, 0x00 }; + + static const u32 bnx2_RXP_b06FwData[(0x0/4) + 1] = { 0x0 }; + static const u32 bnx2_RXP_b06FwRodata[(0x24/4) + 1] = { +- 0x08004590, 0x08004590, 0x08004508, 0x08004540, 0x08004574, 0x08004598, +- 0x08004598, 0x08004598, 0x08004478, 0x00000000 }; ++ 0x080033f8, 0x080033f8, 0x08003370, 0x080033a8, 0x080033dc, 0x08003400, ++ 0x08003400, 0x08003400, 0x080032e0, 0x00000000 }; + + static struct fw_info bnx2_rxp_fw_06 = { +- /* Firmware version: 4.1.1 */ +- .ver_major = 0x4, +- .ver_minor = 0x1, +- .ver_fix = 0x1, +- +- .start_addr = 0x080031d0, ++ /* Firmware version: 5.0.0j */ ++ .ver_major = 0x5, ++ .ver_minor = 0x0, ++ .ver_fix = 0x0, ++ ++ .start_addr = 0x080031d8, + + .text_addr = 0x08000000, +- .text_len = 0x71d0, ++ .text_len = 0x710c, + .text_index = 0x0, + .gz_text = bnx2_RXP_b06FwText, + .gz_text_len = sizeof(bnx2_RXP_b06FwText), +@@ -2965,15 +2976,15 @@ + .data_index = 0x0, + .data = bnx2_RXP_b06FwData, + +- .sbss_addr = 0x08007220, +- .sbss_len = 0x58, +- .sbss_index = 0x0, +- +- .bss_addr = 0x08007278, +- .bss_len = 0x44c, +- .bss_index = 0x0, +- +- .rodata_addr = 0x080071d0, ++ .sbss_addr = 0x08007160, ++ .sbss_len = 0x50, ++ .sbss_index = 0x0, ++ ++ .bss_addr = 0x080071b0, ++ .bss_len = 0x450, ++ .bss_index = 0x0, ++ ++ .rodata_addr = 0x0800710c, + .rodata_len = 0x24, + .rodata_index = 0x0, + .rodata = bnx2_RXP_b06FwRodata, +@@ -2996,687 +3007,571 @@ + }; + + static u8 bnx2_rv2p_proc1[] = { +- /* Date: 12/07/2007 15:02 */ +- 0xd5, 0x56, 0x41, 0x6b, 0x13, 0x51, 0x10, 0x9e, 0xdd, 0x6c, 0xbb, 0xdb, +- 0x64, 0xb3, 0x59, 0xaa, 0xd6, 0x50, 0x53, 0x93, 0x06, 0x2f, 0xad, 0x29, +- 0x6d, 0xaa, 0x82, 0x42, 0xa1, 0x92, 0x4b, 0xc1, 0xf6, 0x20, 0xf5, 0x22, +- 0x22, 0xd8, 0x46, 0xd1, 0x5f, 0x21, 0x06, 0xdb, 0xd4, 0x73, 0x05, 0x0b, +- 0xf5, 0xa0, 0x3d, 0x59, 0x11, 0xc1, 0x04, 0x14, 0x44, 0x04, 0x41, 0x45, +- 0x04, 0x3d, 0x78, 0xa8, 0x60, 0x2f, 0xad, 0x22, 0x56, 0x3c, 0x78, 0xd4, +- 0x93, 0x26, 0xbe, 0x37, 0x33, 0xaf, 0xdd, 0xdd, 0x66, 0x9b, 0x2a, 0x82, +- 0x18, 0x68, 0x3f, 0xde, 0xec, 0xbc, 0x37, 0x33, 0xdf, 0xcc, 0x9b, 0x79, +- 0x2e, 0x00, 0xe8, 0x50, 0xaa, 0xa6, 0x05, 0x82, 0xa5, 0x69, 0x96, 0x00, +- 0x0d, 0xe0, 0xae, 0x8d, 0x58, 0xea, 0x77, 0x05, 0xda, 0xda, 0x70, 0x46, +- 0x62, 0x04, 0x86, 0xbb, 0x25, 0xee, 0x87, 0x27, 0x99, 0xa4, 0xc0, 0x9f, +- 0x75, 0x28, 0xc9, 0xf5, 0xee, 0xca, 0xc3, 0x6a, 0x0c, 0xcf, 0x59, 0xed, +- 0x07, 0xfc, 0xbd, 0x8b, 0x10, 0x1e, 0xce, 0x59, 0x88, 0x25, 0x46, 0xe8, +- 0x73, 0x11, 0x96, 0x66, 0x2d, 0x34, 0x57, 0xea, 0xb3, 0x70, 0x1f, 0xe8, +- 0x24, 0x5f, 0x99, 0x4d, 0x88, 0xff, 0x29, 0x78, 0x5f, 0x90, 0x6b, 0x2b, +- 0x3a, 0x8d, 0x7a, 0x15, 0xde, 0x2f, 0xfe, 0x50, 0xff, 0xb8, 0xd8, 0x07, +- 0xfc, 0x53, 0xfb, 0x5c, 0x3c, 0xa7, 0x98, 0x93, 0x7e, 0xb5, 0x0b, 0x83, +- 0xca, 0x1f, 0x9b, 0xe2, 0x4b, 0x93, 0xb6, 0x89, 0xdf, 0xd7, 0x84, 0xdf, +- 0xca, 0x6e, 0x33, 0x7b, 0x41, 0x7f, 0x83, 0x76, 0xe5, 0x79, 0x86, 0xb0, +- 0xe7, 0xb7, 0x03, 0x20, 0xe5, 0xcb, 0xf5, 0x75, 0x79, 0x8f, 0xff, 0xfb, +- 0x6a, 0xaf, 0x3c, 0xaf, 0x05, 0xa0, 0x57, 0xea, 0x2d, 0xb1, 0x3f, 0x83, +- 0xb0, 0x4f, 0x4f, 0xe2, 0x77, 0x03, 0xf7, 0xef, 0x11, 0xe7, 0x4a, 0xec, +- 0x62, 0xec, 0x66, 0x1c, 0x67, 0xbc, 0xca, 0xb8, 0x8b, 0x71, 0x27, 0xe3, +- 0x0e, 0xc6, 0x76, 0xc6, 0x97, 0x8c, 0x2e, 0x63, 0x82, 0xd1, 0x61, 0x7c, +- 0xce, 0x68, 0x33, 0xc6, 0x18, 0x5f, 0x30, 0xbe, 0x62, 0xb4, 0x18, 0x6f, +- 0x30, 0x7e, 0x61, 0xfc, 0xaa, 0xfc, 0xd0, 0x08, 0x1f, 0xf1, 0xfa, 0x10, +- 0xaf, 0x8f, 0x30, 0x02, 0xf3, 0xa4, 0x05, 0x78, 0xba, 0xcf, 0x75, 0x24, +- 0x79, 0xe6, 0xef, 0x3d, 0x4a, 0x8f, 0xf3, 0x84, 0x3c, 0xdd, 0x63, 0xbd, +- 0xf6, 0xca, 0x42, 0xa0, 0xde, 0x32, 0x5b, 0xd6, 0x59, 0xaa, 0x41, 0xde, +- 0x12, 0x18, 0xcf, 0xc4, 0x48, 0x02, 0xed, 0x38, 0xad, 0x24, 0x57, 0x6e, +- 0x9d, 0x4c, 0x10, 0x9e, 0x8b, 0x12, 0x7e, 0x62, 0x3c, 0x1f, 0x23, 0x9c, +- 0x8c, 0x2b, 0x9e, 0xd5, 0x39, 0xca, 0x9f, 0x66, 0x7e, 0x84, 0xd9, 0x53, +- 0x7e, 0x35, 0xb3, 0x4b, 0x58, 0xd4, 0xfd, 0xf1, 0x5f, 0x1f, 0x20, 0x34, +- 0xf2, 0x44, 0xea, 0x9c, 0xdd, 0x26, 0xa0, 0x5e, 0x9f, 0xb7, 0x0d, 0xb9, +- 0x3e, 0x38, 0xff, 0x1a, 0xef, 0xc7, 0xe0, 0x5c, 0x95, 0xfd, 0x4b, 0x28, +- 0x9e, 0xe9, 0xde, 0x64, 0x81, 0xd6, 0xe3, 0xc8, 0xbb, 0xa8, 0xb0, 0x1e, +- 0xee, 0x03, 0x59, 0x7f, 0xbe, 0xa8, 0x6e, 0x23, 0x9c, 0x8f, 0x8b, 0x9c, +- 0x8f, 0xae, 0x90, 0x7c, 0x84, 0xdd, 0xa3, 0xcd, 0xf7, 0xf7, 0x4c, 0x26, +- 0xc8, 0x5b, 0xd8, 0x7d, 0x53, 0x7c, 0x93, 0xf4, 0x77, 0x79, 0xbc, 0xc0, +- 0x3c, 0x16, 0x89, 0xc7, 0xe4, 0xe7, 0x86, 0x3c, 0x65, 0x3c, 0x3c, 0xc9, +- 0x38, 0xf7, 0x86, 0xe4, 0x39, 0x2c, 0xbe, 0xdc, 0x1f, 0xe7, 0x39, 0xe0, +- 0x1f, 0x9c, 0xc5, 0xfe, 0xe4, 0x42, 0x71, 0x44, 0xf9, 0xeb, 0xe7, 0xb9, +- 0x93, 0xf2, 0x0d, 0xd3, 0x79, 0x29, 0xaf, 0x03, 0x3c, 0xd5, 0x71, 0x6d, +- 0x14, 0x34, 0x09, 0x56, 0x31, 0x4f, 0xfb, 0x1d, 0x5d, 0xe7, 0xf5, 0x76, +- 0xeb, 0x42, 0xe5, 0x5d, 0x62, 0x2b, 0x14, 0x26, 0x39, 0xce, 0x2c, 0xd9, +- 0xa3, 0x3a, 0x30, 0xb8, 0x0e, 0x86, 0xb8, 0x7f, 0x05, 0xf9, 0xb0, 0x2a, +- 0x0b, 0xb3, 0xde, 0x7b, 0x9d, 0x84, 0x62, 0x9e, 0xea, 0x6a, 0x73, 0x5e, +- 0xd5, 0xdc, 0x51, 0x7d, 0x09, 0xc5, 0x95, 0x52, 0xc4, 0x17, 0xef, 0x51, +- 0xc8, 0x79, 0x79, 0xd6, 0x1a, 0xd4, 0x47, 0x33, 0x3b, 0xbe, 0xf3, 0x1c, +- 0xc8, 0x35, 0xea, 0x37, 0x26, 0xc7, 0xd5, 0xcd, 0xf5, 0xdd, 0xb1, 0xa9, +- 0xbe, 0xd5, 0x7c, 0xfb, 0x7b, 0x75, 0xce, 0xf1, 0x9b, 0xa8, 0x97, 0x5a, +- 0x79, 0xe0, 0x9d, 0x67, 0x51, 0xcf, 0x3c, 0xa3, 0x6d, 0xa6, 0xf2, 0x3b, +- 0xed, 0x9d, 0x43, 0xb1, 0x90, 0x3c, 0x78, 0xe7, 0x57, 0x30, 0x5e, 0x7f, +- 0x3d, 0x52, 0x5e, 0xa3, 0x1c, 0xbf, 0xd6, 0xa4, 0x2f, 0xb7, 0xb1, 0xde, +- 0x8f, 0x5a, 0xb8, 0x1e, 0x9d, 0x5b, 0xe8, 0xf1, 0xf6, 0xf1, 0xef, 0x35, +- 0x9a, 0x07, 0xdf, 0x6a, 0x8a, 0xdf, 0xc7, 0x21, 0xfc, 0x0e, 0xfd, 0x53, +- 0x7e, 0x21, 0xc0, 0xef, 0x6a, 0x6d, 0x7b, 0xfc, 0x02, 0xc7, 0x0f, 0x21, +- 0xfc, 0xb6, 0x32, 0x0f, 0x6f, 0xb7, 0xe0, 0x4d, 0xea, 0xc5, 0x58, 0xef, +- 0x8d, 0x47, 0x0f, 0xfd, 0x1e, 0xa2, 0x7b, 0x65, 0x16, 0xd7, 0x02, 0xbc, +- 0xe5, 0x73, 0xf2, 0x7e, 0x5f, 0x82, 0x2a, 0xc7, 0xbf, 0xec, 0xe3, 0x21, +- 0x2e, 0xfc, 0x73, 0xd1, 0xfe, 0xed, 0xaa, 0xe2, 0x8b, 0x3e, 0x67, 0x72, +- 0x84, 0x8b, 0xa8, 0xef, 0x7a, 0x78, 0xf3, 0xbe, 0xaf, 0x5c, 0xb8, 0x55, +- 0x55, 0xfd, 0x4c, 0xf6, 0x15, 0x13, 0x06, 0x78, 0x4e, 0x4e, 0x70, 0xff, +- 0xfa, 0x10, 0xa5, 0x3e, 0x59, 0x1c, 0xc5, 0x3e, 0x03, 0x1d, 0xeb, 0xfd, +- 0x8c, 0xd6, 0x9d, 0x71, 0x7a, 0x47, 0x0e, 0x98, 0x36, 0xea, 0x75, 0xc6, +- 0x09, 0x3b, 0x62, 0x72, 0x5f, 0x12, 0x3e, 0x8e, 0xa1, 0x7a, 0x6e, 0xa3, +- 0x3f, 0x05, 0xfb, 0x12, 0xc7, 0x79, 0x40, 0xca, 0x3b, 0x02, 0xfd, 0x48, +- 0xe8, 0xf4, 0x92, 0x7f, 0x37, 0x81, 0xe3, 0x52, 0xfb, 0xd2, 0x92, 0xc7, +- 0xc5, 0x9a, 0xea, 0xe3, 0xd9, 0x11, 0xe9, 0x4f, 0x02, 0x1c, 0x93, 0xf2, +- 0x48, 0x28, 0xf4, 0x74, 0x53, 0x6e, 0x4b, 0x95, 0x75, 0x5a, 0x97, 0x2f, +- 0xe3, 0x31, 0x63, 0x65, 0x25, 0x2f, 0x60, 0x61, 0x8e, 0xdf, 0x79, 0x86, +- 0x72, 0xa7, 0x1a, 0x21, 0xb9, 0x39, 0xaa, 0xf8, 0x48, 0x60, 0x7c, 0x73, +- 0xc4, 0xc7, 0xe9, 0x6b, 0x84, 0xa7, 0xe0, 0x18, 0x62, 0x74, 0x63, 0x2e, +- 0x5b, 0x88, 0x10, 0xf7, 0xf6, 0xdf, 0x16, 0xe1, 0x1e, 0xf6, 0x4d, 0x4f, +- 0x7e, 0x82, 0x73, 0xb5, 0x59, 0x9e, 0xbc, 0x73, 0x5d, 0xe6, 0xa9, 0xd1, +- 0xfc, 0x8e, 0x73, 0x5d, 0x95, 0x9b, 0xd4, 0x9f, 0xea, 0x83, 0x25, 0xae, +- 0xfb, 0x46, 0xef, 0x1a, 0x89, 0x4e, 0xc8, 0xfc, 0x4f, 0xad, 0xfb, 0x95, +- 0x0e, 0x7d, 0x77, 0x91, 0xfe, 0xf6, 0xde, 0x5b, 0x6e, 0xc8, 0x1c, 0xfe, +- 0x1f, 0xde, 0x55, 0x5b, 0xbd, 0xa7, 0x1c, 0xe6, 0xf9, 0x04, 0xf3, 0x6c, +- 0x40, 0x4b, 0x04, 0x89, 0xb1, 0x8d, 0x29, 0x3c, 0x57, 0x2f, 0xd3, 0x58, +- 0xb7, 0x5b, 0x66, 0x70, 0xae, 0x3b, 0xf6, 0x0c, 0xe9, 0x19, 0x24, 0x4f, +- 0x2a, 0xbc, 0x32, 0x45, 0xef, 0x6c, 0x1d, 0x7e, 0x01, 0x50, 0xb6, 0x82, +- 0xa7, 0xd8, 0x0d, 0x00, 0x00, 0x00 }; ++ /* Date: 02/03/2009 14:20 */ ++ 0xa5, 0x56, 0x4f, 0x68, 0x14, 0x67, 0x14, 0x7f, 0x33, 0xbb, 0xb3, 0xb3, ++ 0x99, 0x9d, 0xd9, 0xdd, 0x92, 0x18, 0x96, 0x18, 0xcc, 0x1a, 0x84, 0x92, ++ 0x75, 0xb7, 0x6e, 0x6c, 0x0f, 0x42, 0x03, 0x29, 0xb9, 0x08, 0x35, 0x87, ++ 0x12, 0x11, 0x8a, 0x2d, 0x68, 0xb7, 0x22, 0x14, 0x0a, 0xa5, 0x07, 0x8f, ++ 0xa5, 0x83, 0x71, 0x53, 0x5a, 0xbc, 0xe4, 0xd0, 0x80, 0x42, 0x35, 0x27, ++ 0x5b, 0x62, 0x0e, 0x3b, 0xe0, 0xa1, 0x88, 0xe0, 0x41, 0x8f, 0x7a, 0xaa, ++ 0x7f, 0x5a, 0x28, 0x46, 0x29, 0xb5, 0x87, 0x82, 0xc7, 0xde, 0x9a, 0xe9, ++ 0xf7, 0xfe, 0x7c, 0xbb, 0x33, 0x5f, 0x66, 0x13, 0xa1, 0x42, 0xfc, 0xf1, ++ 0xbd, 0x79, 0xef, 0xfb, 0xde, 0x9f, 0xdf, 0x7b, 0x6f, 0xab, 0x00, 0x60, ++ 0x43, 0x18, 0x4d, 0x29, 0x04, 0x2b, 0x67, 0x15, 0x11, 0x00, 0x36, 0x81, ++ 0xff, 0x39, 0x3e, 0x9d, 0xc3, 0x23, 0x72, 0x3e, 0xcc, 0x10, 0x1e, 0xae, ++ 0xaa, 0xff, 0x3f, 0x85, 0xf9, 0x3a, 0x62, 0x0e, 0xe6, 0x0f, 0x22, 0x1e, ++ 0x85, 0xbb, 0xf5, 0x9a, 0xc2, 0x7f, 0x63, 0x08, 0xf1, 0x1c, 0xf4, 0x7e, ++ 0x8e, 0x4a, 0x74, 0xff, 0x96, 0xd8, 0xff, 0x9a, 0x63, 0x3c, 0xd6, 0xac, ++ 0x12, 0x3e, 0x5a, 0xc5, 0xf7, 0x4e, 0x9d, 0x82, 0x02, 0xda, 0x5d, 0x50, ++ 0x17, 0x23, 0x96, 0xd4, 0x83, 0x45, 0xb2, 0x03, 0xbb, 0xa2, 0x70, 0x12, ++ 0x9e, 0x2f, 0xa0, 0xfe, 0x1b, 0xde, 0xa5, 0x55, 0xc4, 0x12, 0x74, 0x9a, ++ 0xa8, 0x77, 0x00, 0xb2, 0xf5, 0x6a, 0x4a, 0x0f, 0xe5, 0x11, 0x84, 0x4d, ++ 0xc4, 0x11, 0x80, 0x56, 0xf2, 0x3d, 0xd7, 0x0a, 0x5b, 0x68, 0xff, 0x85, ++ 0xbc, 0xb7, 0x4f, 0xee, 0x51, 0x71, 0x47, 0x88, 0x3d, 0xb1, 0x53, 0x7f, ++ 0x2d, 0x96, 0xb3, 0xfe, 0x67, 0x4a, 0x4f, 0xc7, 0xe3, 0x73, 0xde, 0xa6, ++ 0x38, 0x1e, 0x57, 0xe2, 0x79, 0xb6, 0xaa, 0xf3, 0x86, 0xfa, 0xbf, 0xc7, ++ 0x69, 0x7d, 0xd8, 0x43, 0xff, 0x89, 0xd2, 0x4f, 0xdf, 0xcb, 0xf2, 0x5f, ++ 0x06, 0xf2, 0x99, 0xf4, 0xf7, 0xad, 0x06, 0xfa, 0xe7, 0x00, 0x34, 0x24, ++ 0x8f, 0xa4, 0xff, 0x30, 0xe6, 0x78, 0xe6, 0xe0, 0x90, 0x5d, 0x23, 0xbd, ++ 0x3c, 0xd4, 0x28, 0x3f, 0x1c, 0xef, 0x01, 0xc1, 0x25, 0xc1, 0x6b, 0x82, ++ 0x3f, 0x08, 0xc2, 0xff, 0xc4, 0xad, 0x21, 0xf2, 0x7d, 0x82, 0xfb, 0x0d, ++ 0xf9, 0x2d, 0xc1, 0xb7, 0x0c, 0x7b, 0xcf, 0x62, 0x7c, 0xac, 0xbf, 0xcb, ++ 0xf9, 0x5d, 0xc3, 0xfe, 0x4b, 0xe0, 0xfc, 0x58, 0x46, 0xde, 0x36, 0x85, ++ 0x87, 0x58, 0x77, 0xf9, 0x3e, 0xa3, 0xf5, 0x84, 0x37, 0x8d, 0xa4, 0xfe, ++ 0x8d, 0x5d, 0xf4, 0x59, 0x6d, 0x61, 0x26, 0xcb, 0xee, 0x7a, 0x2c, 0x79, ++ 0x14, 0x7b, 0xaf, 0x77, 0x67, 0x08, 0xef, 0xe7, 0x32, 0x79, 0x3f, 0x2e, ++ 0x71, 0xa8, 0xa6, 0x23, 0xfb, 0xdb, 0x16, 0xf3, 0xdb, 0x11, 0x5e, 0xee, ++ 0xc6, 0x63, 0xe1, 0xd5, 0x8c, 0xe6, 0x57, 0x9a, 0x57, 0xcc, 0x8f, 0x82, ++ 0xc1, 0x8f, 0x6f, 0xf7, 0xc8, 0x4b, 0xc9, 0x88, 0x6f, 0x39, 0xd6, 0xf9, ++ 0xb6, 0x45, 0x7c, 0xb1, 0x50, 0xa5, 0x7b, 0xbf, 0x8b, 0xe8, 0x38, 0xe6, ++ 0xaf, 0xe0, 0x39, 0x0f, 0x97, 0x23, 0x6d, 0x27, 0xfd, 0xd4, 0xd0, 0xef, ++ 0xb0, 0x7d, 0x20, 0x9f, 0x6d, 0x47, 0xfb, 0xc9, 0x72, 0x0f, 0xf0, 0x3c, ++ 0xda, 0x5b, 0x37, 0xf2, 0x56, 0xa7, 0xb8, 0x41, 0xe2, 0x07, 0x23, 0x7e, ++ 0x9d, 0xbf, 0x57, 0xc2, 0xf7, 0x49, 0x95, 0x0f, 0xfe, 0x3e, 0x05, 0xfa, ++ 0x7e, 0x9c, 0x0b, 0x45, 0x38, 0x7b, 0xbc, 0x42, 0xfe, 0x94, 0x0b, 0x7c, ++ 0xcd, 0x87, 0x15, 0xc6, 0x73, 0x1e, 0xe3, 0x9f, 0x9e, 0xca, 0x2d, 0xc4, ++ 0xf1, 0xf9, 0x12, 0x9f, 0x3f, 0x09, 0xf0, 0xde, 0x51, 0xf5, 0xb0, 0xb6, ++ 0xd7, 0x7e, 0xed, 0xe6, 0x0f, 0xbe, 0xaf, 0xdf, 0xd1, 0x7e, 0xe8, 0xf7, ++ 0xd2, 0x75, 0x19, 0xfe, 0x2e, 0x63, 0xc7, 0x4e, 0xe7, 0x21, 0x3f, 0xcb, ++ 0x78, 0xb5, 0x4d, 0x50, 0x5b, 0xf3, 0xd9, 0xee, 0x8a, 0x9f, 0xc7, 0xf3, ++ 0x3b, 0x57, 0x1e, 0xe0, 0xfd, 0xf6, 0xd1, 0xb5, 0x48, 0xfc, 0xab, 0xe8, ++ 0xba, 0x92, 0x1c, 0xa6, 0x81, 0xcf, 0x4b, 0xc2, 0x93, 0x25, 0xe2, 0x71, ++ 0x59, 0x7d, 0x42, 0x9c, 0x80, 0xd0, 0x26, 0x3d, 0xef, 0x3e, 0xd9, 0xe7, ++ 0x44, 0xae, 0xea, 0x37, 0x9d, 0xe6, 0xff, 0x16, 0xf3, 0xa2, 0x98, 0xe6, ++ 0xd3, 0x7c, 0x62, 0xce, 0x25, 0xf3, 0x61, 0xf5, 0x79, 0xb4, 0xb3, 0x8e, ++ 0xe9, 0x7a, 0x3d, 0x5a, 0xd5, 0xf9, 0x61, 0xbe, 0xb2, 0x9e, 0x2a, 0x56, ++ 0x8b, 0xd5, 0xc3, 0xb6, 0x24, 0x72, 0x56, 0xbe, 0xb7, 0x4c, 0xde, 0x66, ++ 0xf1, 0xbe, 0x6a, 0xf0, 0xb8, 0x21, 0xbc, 0x1f, 0xe9, 0xad, 0xbf, 0xd6, ++ 0x7e, 0xb8, 0x29, 0xbc, 0xaf, 0x0e, 0xf6, 0xc3, 0x26, 0xed, 0x27, 0x75, ++ 0x26, 0xf5, 0x5e, 0x98, 0x4b, 0xd5, 0xe9, 0x3d, 0xc8, 0xec, 0xef, 0xab, ++ 0x72, 0x4f, 0x5b, 0xfa, 0xbc, 0x90, 0xd8, 0x23, 0xa4, 0x5e, 0x06, 0xf2, ++ 0xc3, 0x35, 0xfa, 0x74, 0x2c, 0x96, 0x77, 0x54, 0xbf, 0x65, 0xc5, 0xeb, ++ 0xc2, 0x5f, 0xc2, 0x83, 0x0e, 0xf5, 0x93, 0x33, 0xf6, 0xf9, 0xed, 0x54, ++ 0x9d, 0x00, 0x0e, 0xea, 0xfd, 0x90, 0xf4, 0x2b, 0xb9, 0xdf, 0xf0, 0xbe, ++ 0x1a, 0x74, 0x66, 0x93, 0x7b, 0xee, 0x72, 0xbf, 0xdf, 0x03, 0xea, 0xa3, ++ 0xf2, 0x8e, 0xbe, 0xd4, 0xf3, 0xac, 0xde, 0x4c, 0xf6, 0xf7, 0x98, 0xcc, ++ 0x2f, 0x5b, 0xf6, 0x73, 0xc9, 0x8c, 0x53, 0xed, 0xbd, 0xec, 0x7a, 0x71, ++ 0xbc, 0xff, 0x6c, 0xbf, 0xde, 0xbc, 0xdb, 0xab, 0xee, 0x9e, 0x51, 0xf7, ++ 0xbf, 0xb7, 0x75, 0x1e, 0x6d, 0x27, 0x6b, 0xbf, 0x7f, 0xa0, 0xee, 0x15, ++ 0x7d, 0x99, 0x1b, 0x67, 0xea, 0x59, 0x7c, 0x2d, 0xee, 0xd0, 0x4b, 0xcf, ++ 0x2f, 0xed, 0xe7, 0xc6, 0x06, 0xd7, 0xfd, 0xa3, 0xb8, 0xbf, 0x97, 0x52, ++ 0xf3, 0x75, 0x44, 0xea, 0xac, 0xf4, 0xc8, 0xbf, 0xa7, 0xdb, 0x83, 0x79, ++ 0x9c, 0xe4, 0xcd, 0x49, 0xe1, 0xab, 0x3d, 0xb7, 0x4e, 0xfd, 0xe1, 0x76, ++ 0x5e, 0x1a, 0x75, 0x98, 0x6d, 0x62, 0xfd, 0xbf, 0x86, 0x48, 0xfc, 0xfc, ++ 0x2d, 0xe5, 0x6f, 0x20, 0xfd, 0x55, 0x80, 0x9f, 0x22, 0x1d, 0x97, 0xae, ++ 0x1b, 0xe3, 0x8f, 0x4d, 0xe9, 0x93, 0x7e, 0x7c, 0xf8, 0xee, 0xa2, 0xbc, ++ 0x5b, 0x85, 0x1b, 0x91, 0x9e, 0x63, 0x38, 0xd7, 0x5c, 0x68, 0xcb, 0xdc, ++ 0x3c, 0x2b, 0xf3, 0xeb, 0x85, 0xc7, 0xf3, 0xb1, 0x73, 0x82, 0x78, 0x08, ++ 0xe3, 0x32, 0xc7, 0x3a, 0x01, 0x9f, 0x27, 0x02, 0xfe, 0x7d, 0xd8, 0x76, ++ 0x7d, 0xd2, 0x9b, 0x08, 0x18, 0xc7, 0x4b, 0x68, 0x57, 0x83, 0x3f, 0x16, ++ 0x49, 0xbd, 0x39, 0x98, 0x63, 0xe6, 0xfc, 0x92, 0x38, 0xdf, 0x46, 0xb9, ++ 0xda, 0x93, 0xd3, 0x7c, 0xe6, 0x3a, 0xfb, 0x7d, 0x5e, 0x5f, 0x97, 0xaa, ++ 0xd4, 0x2b, 0xc9, 0x3c, 0xeb, 0x3e, 0xba, 0x69, 0xe4, 0x57, 0xd7, 0xe7, ++ 0xcd, 0x58, 0xcf, 0xf7, 0xe9, 0xe3, 0xe8, 0x6f, 0x05, 0xca, 0x2e, 0xf3, ++ 0x82, 0x51, 0xdd, 0x63, 0xbb, 0x68, 0x36, 0xd9, 0x95, 0x79, 0xd8, 0xbd, ++ 0x48, 0xd7, 0x2c, 0x76, 0xb5, 0x7c, 0x81, 0x1a, 0x61, 0x69, 0xe3, 0x1e, ++ 0xc9, 0xcb, 0x51, 0x8e, 0xe5, 0xee, 0x09, 0x9d, 0xaf, 0x0a, 0xc5, 0xbf, ++ 0xc6, 0xf9, 0xfa, 0xf8, 0x7b, 0xc6, 0xd3, 0xf0, 0x3e, 0xa1, 0x37, 0x98, ++ 0xe3, 0x45, 0x42, 0x08, 0x92, 0x73, 0xdc, 0x51, 0xee, 0x55, 0xc9, 0x9f, ++ 0x41, 0xfd, 0xcc, 0xfd, 0xb8, 0x5b, 0x1d, 0x47, 0x13, 0xfc, 0xd3, 0x75, ++ 0x34, 0xe7, 0x39, 0xf1, 0xc4, 0xe0, 0x63, 0x77, 0x08, 0x1f, 0xad, 0x21, ++ 0x7c, 0x36, 0xe7, 0xd6, 0x57, 0xd2, 0xc7, 0x79, 0x70, 0x72, 0xb4, 0x70, ++ 0xfd, 0xfc, 0x32, 0xd5, 0xd5, 0xee, 0xf2, 0x0f, 0x08, 0xdf, 0x59, 0xb1, ++ 0x28, 0x5f, 0xfe, 0x0a, 0xeb, 0xe5, 0x59, 0x5e, 0xd3, 0xf8, 0xcd, 0xb2, ++ 0xfe, 0xbd, 0xf1, 0x1f, 0xb6, 0x34, 0x9b, 0xb9, 0xa0, 0x0c, 0x00, 0x00, ++ 0x00 }; + + static u8 bnx2_rv2p_proc2[] = { +- /* Date: 12/07/2007 15:02 */ +- 0xed, 0x59, 0x5d, 0x6c, 0x54, 0xc7, 0x15, 0x9e, 0xbd, 0xbb, 0x7b, 0xf7, +- 0x7a, 0x7d, 0xf7, 0xae, 0x71, 0xa8, 0xff, 0xf9, 0xb3, 0x09, 0xd8, 0xa9, +- 0x21, 0xce, 0x9a, 0x98, 0x02, 0x55, 0x63, 0x39, 0x95, 0x81, 0xa6, 0x55, +- 0x0c, 0x49, 0x9b, 0xbe, 0x35, 0x76, 0x02, 0xb6, 0xa9, 0x4d, 0x2d, 0x43, +- 0x83, 0x4a, 0x1b, 0x65, 0x85, 0xd7, 0xf6, 0xcb, 0x26, 0xea, 0x22, 0xc0, +- 0x24, 0xaa, 0xa8, 0x1b, 0xa4, 0x28, 0xea, 0xdb, 0x56, 0x6a, 0x6d, 0xda, +- 0x97, 0xfe, 0x10, 0xb7, 0x4a, 0xa4, 0x42, 0xa5, 0xf6, 0xa1, 0x52, 0x85, +- 0x44, 0xda, 0x62, 0x99, 0xc4, 0x20, 0x63, 0xba, 0x79, 0x21, 0x75, 0x67, +- 0xce, 0x77, 0xe6, 0xee, 0xbd, 0xeb, 0xb5, 0x21, 0x2d, 0x8f, 0xdd, 0x07, +- 0x1f, 0x66, 0xee, 0x99, 0x33, 0xe7, 0xe7, 0x9b, 0x33, 0x67, 0x0e, 0x65, +- 0x42, 0x08, 0x43, 0x24, 0xb3, 0x1b, 0x24, 0x15, 0x56, 0x20, 0x20, 0xf0, +- 0x7b, 0xac, 0x8c, 0xc8, 0x9f, 0xb3, 0x96, 0xfc, 0x1b, 0x16, 0xcf, 0x1b, +- 0x55, 0x34, 0x0e, 0x09, 0x45, 0x1d, 0x21, 0x92, 0x5e, 0x5a, 0xce, 0xf4, +- 0x67, 0x4c, 0x77, 0x1b, 0xa0, 0x3d, 0x4c, 0xeb, 0x98, 0x9e, 0x64, 0xba, +- 0x91, 0xe9, 0x56, 0xa6, 0x27, 0x98, 0x7e, 0x8f, 0xe9, 0x07, 0x4c, 0x77, +- 0xb2, 0x3c, 0xf9, 0x4b, 0xda, 0xf2, 0x4f, 0x40, 0x24, 0x9b, 0xb4, 0x7e, +- 0x36, 0xa6, 0x9b, 0xa0, 0xe7, 0x73, 0x1b, 0x15, 0xdf, 0xcd, 0xa5, 0x3c, +- 0x1f, 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0x46, +- 0xb9, 0xad, 0x54, 0x2f, 0x5e, 0x38, 0x39, 0xad, 0xf8, 0x62, 0xee, 0xbb, +- 0xcc, 0xaf, 0xdf, 0xc4, 0x43, 0xf0, 0x23, 0xbd, 0x3f, 0x44, 0xaf, 0xb3, +- 0x92, 0xbf, 0xf0, 0x7e, 0x5a, 0x98, 0xd6, 0xfe, 0xb6, 0xc9, 0x4e, 0xd4, +- 0xd3, 0x17, 0x0a, 0xfc, 0x68, 0x78, 0xfc, 0x08, 0xfe, 0x95, 0x71, 0xef, +- 0x7f, 0x97, 0x03, 0x17, 0xaf, 0x16, 0xc1, 0x3d, 0xf5, 0xf7, 0x1e, 0xd8, +- 0xce, 0x03, 0xad, 0x5e, 0xbb, 0x1a, 0xc4, 0x4c, 0x16, 0xf8, 0xef, 0x62, +- 0x9c, 0xbc, 0xc8, 0x79, 0xf6, 0x7a, 0x54, 0x4d, 0x58, 0xa2, 0xe7, 0x19, +- 0xe4, 0xe9, 0x8a, 0x52, 0xd8, 0xdd, 0xf3, 0x55, 0xed, 0x27, 0xcc, 0xd7, +- 0xc4, 0x50, 0x57, 0x77, 0x45, 0xf0, 0xbe, 0xa8, 0x89, 0x81, 0x56, 0x70, +- 0x9e, 0x9e, 0x71, 0xfb, 0x29, 0xa0, 0xf9, 0xfa, 0x12, 0x7d, 0xa5, 0xdf, +- 0x9a, 0xa8, 0xc3, 0x45, 0x13, 0xd7, 0xcf, 0x94, 0xef, 0x82, 0xe2, 0x60, +- 0x13, 0x70, 0x22, 0xea, 0xfd, 0x79, 0x8a, 0xf3, 0xec, 0xb2, 0x7a, 0x0d, +- 0x7d, 0x99, 0x12, 0x4f, 0x5f, 0x42, 0xef, 0xa7, 0xfd, 0xa8, 0xe5, 0xd2, +- 0x70, 0x85, 0xba, 0x72, 0x91, 0xf3, 0xd8, 0x23, 0xe2, 0x0f, 0x59, 0xd8, +- 0x35, 0x93, 0x2d, 0xc4, 0x95, 0xde, 0x4f, 0xcb, 0x83, 0xde, 0xda, 0x8e, +- 0xbc, 0x7c, 0xec, 0x7f, 0x88, 0xf5, 0xfc, 0x07, 0xf5, 0x33, 0x2b, 0xd8, +- 0x1e, 0x25, 0x17, 0xf3, 0xfb, 0xb8, 0x4f, 0x94, 0x74, 0xc7, 0xfe, 0xfe, +- 0x4e, 0x17, 0xe9, 0xb5, 0x86, 0x71, 0x54, 0xe1, 0xc1, 0x39, 0xf8, 0xd7, +- 0xb6, 0x80, 0x9e, 0x6d, 0xd1, 0x71, 0xd0, 0xf1, 0xd2, 0xf1, 0x41, 0x1c, +- 0x2b, 0xd0, 0x4f, 0xda, 0xd1, 0xf3, 0x04, 0xdd, 0x0f, 0x2d, 0x3d, 0x0b, +- 0xfa, 0xdc, 0x61, 0xfd, 0x81, 0x66, 0xc5, 0xff, 0x9a, 0xf8, 0x13, 0xf7, +- 0x1b, 0xfe, 0xca, 0xb4, 0xb0, 0x6f, 0x82, 0xbe, 0x8b, 0x8c, 0x5b, 0x98, +- 0x03, 0xd2, 0xaa, 0xf3, 0xac, 0xf7, 0x9d, 0xa0, 0xcf, 0xdf, 0xd6, 0x65, +- 0x78, 0xcd, 0xe7, 0x4b, 0x6d, 0x9f, 0xe2, 0x6f, 0x66, 0x1c, 0xca, 0xf7, +- 0xe9, 0x5e, 0xa5, 0x47, 0x5c, 0xde, 0xdb, 0xc8, 0xc7, 0x4e, 0xc4, 0x1b, +- 0x27, 0x89, 0x87, 0x92, 0x88, 0x1a, 0xd6, 0x95, 0x97, 0x90, 0x1d, 0xa7, +- 0xdf, 0xff, 0x80, 0x3e, 0xbf, 0x3d, 0x51, 0x8a, 0xf9, 0xca, 0x67, 0xe2, +- 0xe4, 0x87, 0x73, 0xc0, 0xf1, 0x8f, 0xce, 0x82, 0xbe, 0x25, 0xbe, 0x82, +- 0xf5, 0xe5, 0xa7, 0xe8, 0xfe, 0xb7, 0x2a, 0x19, 0x97, 0x55, 0x38, 0xf7, +- 0x69, 0xd4, 0x0f, 0x4b, 0x4b, 0x22, 0x86, 0xba, 0x4d, 0xdf, 0x03, 0xc0, +- 0x65, 0xc8, 0x13, 0xdf, 0xfb, 0xe1, 0x54, 0x51, 0xbb, 0xf0, 0x9d, 0x64, +- 0x15, 0xe2, 0x55, 0xfb, 0xa3, 0xca, 0x28, 0x8a, 0xcf, 0x36, 0x3f, 0x3e, +- 0x4d, 0xc6, 0xe7, 0x5d, 0xb7, 0x8e, 0x5a, 0x2e, 0x97, 0xde, 0x89, 0x12, +- 0xb7, 0x0f, 0x0b, 0xaf, 0xa0, 0xfb, 0x1a, 0xd4, 0xfe, 0x95, 0xcb, 0xf2, +- 0xeb, 0x06, 0x5f, 0x9c, 0x6f, 0xde, 0xd3, 0x7a, 0x9d, 0x32, 0xbd, 0xdf, +- 0x5b, 0xdc, 0x7b, 0x66, 0x98, 0xfb, 0xfc, 0x39, 0xf4, 0xa3, 0x12, 0xf3, +- 0x69, 0x1a, 0xda, 0xd5, 0xef, 0x52, 0xdf, 0x22, 0x31, 0xcc, 0xf9, 0xf3, +- 0xfd, 0xa0, 0xae, 0xb7, 0x30, 0xbe, 0xc2, 0x79, 0xe3, 0x0e, 0xeb, 0x75, +- 0x80, 0x61, 0x39, 0xdf, 0x48, 0x79, 0x37, 0xa1, 0xeb, 0xb4, 0x61, 0x7e, +- 0x5f, 0xe8, 0x3e, 0xd5, 0x97, 0x83, 0x9c, 0x4f, 0xc9, 0x8f, 0xa1, 0xc4, +- 0xed, 0x29, 0xdd, 0x4f, 0xd0, 0xfd, 0x05, 0xd6, 0x07, 0xfd, 0x30, 0x71, +- 0x30, 0x02, 0x2a, 0x9a, 0xfc, 0xf1, 0x11, 0xae, 0x9d, 0x18, 0x99, 0x05, +- 0xfd, 0x86, 0x08, 0xf7, 0x09, 0x27, 0x58, 0xbf, 0x33, 0xfc, 0xbe, 0x73, +- 0xc8, 0x4f, 0x65, 0xd2, 0x7e, 0xea, 0x5b, 0x25, 0x8e, 0x4d, 0xc3, 0xae, +- 0x01, 0xf7, 0xfd, 0x06, 0x3e, 0xa6, 0xce, 0x9b, 0xdc, 0x2f, 0xe3, 0xbe, +- 0x9a, 0x63, 0x8e, 0xc0, 0x9e, 0x81, 0x1c, 0xc6, 0x8b, 0x78, 0x17, 0x39, +- 0xff, 0xe2, 0x3a, 0xef, 0xf8, 0x49, 0xfd, 0x1e, 0x2c, 0xbe, 0x4e, 0xd7, +- 0x85, 0x83, 0xf4, 0x2e, 0x79, 0x61, 0x92, 0xfb, 0xea, 0xa2, 0x9f, 0xea, +- 0xd1, 0xaf, 0xdb, 0x39, 0x1e, 0xe7, 0xfb, 0x07, 0xfe, 0xbe, 0x81, 0xae, +- 0xbf, 0xe7, 0xd0, 0xff, 0x9c, 0xcc, 0xa5, 0x81, 0x97, 0x64, 0x89, 0x17, +- 0xe7, 0x25, 0x89, 0x4a, 0x8e, 0xdb, 0xda, 0x27, 0x41, 0xcf, 0x3e, 0x89, +- 0x77, 0xf2, 0xc0, 0x2b, 0xec, 0x97, 0x1d, 0x14, 0xa7, 0xed, 0xe8, 0xbf, +- 0x78, 0xeb, 0x50, 0x85, 0x9b, 0x4f, 0x5c, 0x3c, 0xcf, 0x91, 0x5e, 0xb5, +- 0x93, 0x39, 0xe2, 0xab, 0x11, 0x8f, 0xd0, 0xbd, 0x57, 0xed, 0x2c, 0x40, +- 0xcf, 0xc4, 0x04, 0xdb, 0x37, 0xf4, 0x05, 0xd0, 0x57, 0x38, 0xce, 0x3a, +- 0x7e, 0x57, 0xdd, 0x3e, 0x1e, 0xf4, 0xd5, 0xf7, 0xf1, 0xf2, 0xf7, 0x3b, +- 0xc6, 0xd5, 0xad, 0x48, 0x60, 0x7d, 0xc7, 0x8b, 0xf7, 0xa7, 0xfc, 0x78, +- 0x50, 0x78, 0xd1, 0xb8, 0xf4, 0xe2, 0xa8, 0xf0, 0x9c, 0xe5, 0x71, 0xe1, +- 0x34, 0x55, 0x91, 0xbf, 0x70, 0x9f, 0x98, 0x89, 0x89, 0xcc, 0xea, 0x7e, +- 0x7a, 0x13, 0x7e, 0x4a, 0xb0, 0xde, 0x76, 0xff, 0x08, 0xee, 0xa1, 0x31, +- 0x8e, 0xd3, 0x5c, 0x23, 0xd7, 0x11, 0xac, 0xdf, 0xc7, 0xfc, 0xce, 0x40, +- 0x3c, 0x23, 0xf6, 0xe1, 0x69, 0x8e, 0x1f, 0xe3, 0xea, 0x08, 0xdb, 0xfd, +- 0x11, 0xec, 0xb6, 0xb5, 0xdd, 0xfd, 0xae, 0xdd, 0xba, 0x4e, 0xf1, 0xca, +- 0x29, 0x97, 0xb8, 0xa0, 0x7a, 0xc7, 0xbe, 0x4a, 0x79, 0x24, 0xcc, 0x76, +- 0x4a, 0xbe, 0x56, 0xfd, 0xff, 0x8e, 0xf0, 0x57, 0xef, 0x76, 0xef, 0xba, +- 0x52, 0x5e, 0x17, 0x95, 0xeb, 0x30, 0x8f, 0xf3, 0x67, 0xaf, 0xe0, 0x4f, +- 0xe5, 0x37, 0x2d, 0xb7, 0xf0, 0x7c, 0x79, 0xfd, 0x47, 0x95, 0x1d, 0xfd, +- 0x90, 0x57, 0x64, 0x9c, 0xe8, 0x1e, 0xb2, 0xdd, 0xbc, 0x72, 0x87, 0xea, +- 0xc0, 0xe8, 0x85, 0x41, 0xe4, 0x81, 0x0b, 0x83, 0xef, 0x72, 0x1d, 0xce, +- 0x7e, 0xe9, 0xa2, 0xff, 0xaf, 0x92, 0xb1, 0xab, 0xf7, 0xe7, 0x15, 0xbf, +- 0x1e, 0xb5, 0x1e, 0x3d, 0xf4, 0xbe, 0xff, 0x01, 0xfe, 0xf0, 0x11, 0xdc, +- 0xa0, 0x1d, 0x00, 0x00, 0x00 }; ++ /* Date: 02/03/2009 14:20 */ ++ 0xad, 0x57, 0x4d, 0x68, 0x5c, 0x55, 0x14, 0x3e, 0xf3, 0xe6, 0xef, 0xcd, ++ 0xcc, 0x9b, 0xcc, 0x34, 0x8d, 0x93, 0x31, 0x29, 0x26, 0x4d, 0x68, 0xea, ++ 0xc8, 0x44, 0xf3, 0x47, 0x05, 0x5d, 0x18, 0x46, 0x48, 0x7f, 0x2c, 0x34, ++ 0x8d, 0x2e, 0x8a, 0x9b, 0x36, 0x53, 0x3b, 0x3a, 0x6d, 0xed, 0xc2, 0xec, ++ 0xdc, 0xf8, 0xb0, 0x35, 0x41, 0x98, 0x45, 0x53, 0x4c, 0x13, 0x44, 0xa8, ++ 0xe8, 0xce, 0xdd, 0x88, 0x9a, 0xd6, 0x8d, 0x50, 0x68, 0x28, 0x76, 0x51, ++ 0x04, 0x05, 0xed, 0x42, 0x10, 0xad, 0xa1, 0x15, 0x41, 0x51, 0xb3, 0x92, ++ 0x8c, 0xf7, 0x9e, 0xef, 0xdc, 0x37, 0xef, 0x4d, 0xa6, 0xa4, 0x0b, 0x67, ++ 0xf3, 0xe5, 0xdc, 0x77, 0xee, 0xb9, 0xe7, 0xe7, 0x3b, 0xe7, 0xde, 0x64, ++ 0x89, 0x28, 0x42, 0x6e, 0xbd, 0x4f, 0x21, 0x85, 0xc2, 0x21, 0x5b, 0x41, ++ 0x83, 0x28, 0x9a, 0xd7, 0x32, 0x59, 0x24, 0xbf, 0x27, 0xb2, 0x0c, 0xdf, ++ 0xd6, 0x1d, 0xad, 0x46, 0x6e, 0x41, 0xeb, 0xd9, 0xf4, 0x92, 0x05, 0xbd, ++ 0x08, 0x69, 0x54, 0x3a, 0xae, 0xc6, 0x1d, 0x82, 0xcf, 0x08, 0x46, 0x42, ++ 0xc0, 0xb0, 0xa0, 0xd5, 0x82, 0x24, 0x7a, 0x5d, 0x22, 0x6f, 0x8a, 0xec, ++ 0x08, 0xe6, 0x65, 0xfd, 0xb4, 0xe0, 0xab, 0xb2, 0x7e, 0x47, 0x70, 0x5d, ++ 0xa1, 0xf1, 0x53, 0xcb, 0xbf, 0x35, 0x9a, 0xb2, 0x03, 0xf3, 0x05, 0xf8, ++ 0xff, 0x62, 0x3f, 0xeb, 0x37, 0x82, 0xfa, 0x77, 0x1b, 0xc6, 0x0f, 0x13, ++ 0xaf, 0x15, 0xd5, 0xfa, 0xbb, 0x27, 0x2e, 0x2f, 0x62, 0xdf, 0xf1, 0x7e, ++ 0xac, 0x3f, 0x56, 0xd4, 0x71, 0xc7, 0xc8, 0x15, 0xa4, 0x61, 0x9b, 0xe3, ++ 0x70, 0x87, 0x4d, 0xa2, 0xa0, 0xff, 0xe3, 0x22, 0xa4, 0xd9, 0x34, 0xec, ++ 0x26, 0x03, 0x76, 0x73, 0x5b, 0xec, 0x7e, 0x9f, 0xf0, 0xdb, 0xff, 0x54, ++ 0xec, 0x27, 0xb7, 0xb5, 0x5f, 0x4e, 0x03, 0x77, 0x16, 0xdb, 0x9d, 0x93, ++ 0xd8, 0xc6, 0xff, 0xd3, 0xdb, 0xda, 0x7f, 0xd3, 0xf3, 0xdf, 0xac, 0x03, ++ 0xfb, 0xf0, 0xf9, 0x13, 0xf7, 0x29, 0x93, 0x47, 0x13, 0xaf, 0xf8, 0x15, ++ 0x06, 0x4e, 0x16, 0x19, 0x6a, 0x27, 0x25, 0xb1, 0x53, 0x43, 0xfa, 0xbc, ++ 0x4e, 0x8a, 0x58, 0xda, 0xce, 0x5e, 0x3b, 0x76, 0x0d, 0xeb, 0xc7, 0x32, ++ 0xc0, 0x57, 0x24, 0x80, 0xbb, 0x49, 0x9d, 0x90, 0x46, 0xa3, 0x92, 0x12, ++ 0xfb, 0x28, 0x23, 0xb9, 0x29, 0xec, 0x5f, 0x73, 0xb4, 0x5f, 0xb7, 0x54, ++ 0xdd, 0xb4, 0x1c, 0x26, 0x37, 0x13, 0xf4, 0xff, 0x0a, 0x41, 0x6f, 0xc7, ++ 0x5e, 0xac, 0x5e, 0xac, 0x40, 0xee, 0xfd, 0x38, 0xcb, 0xfa, 0x2b, 0x75, ++ 0x13, 0x87, 0x5e, 0x57, 0xfc, 0xcf, 0xc0, 0x0e, 0x0d, 0xd8, 0x7c, 0x18, ++ 0xf2, 0xa3, 0x0e, 0x1d, 0x36, 0xf6, 0xf0, 0xbb, 0xbc, 0xc7, 0xf0, 0x09, ++ 0x72, 0x25, 0xc6, 0x90, 0x9f, 0x9d, 0xd7, 0xfe, 0x66, 0xe8, 0x84, 0xa5, ++ 0x1d, 0xb1, 0x24, 0xbe, 0xb0, 0xed, 0x7c, 0x01, 0xfd, 0xaf, 0xfa, 0x1c, ++ 0xf6, 0xad, 0x32, 0x8e, 0x7d, 0x5d, 0x63, 0xc0, 0xa5, 0xb1, 0xa8, 0x86, ++ 0x62, 0x65, 0x8e, 0xc5, 0x27, 0x7f, 0x1e, 0xb5, 0x59, 0xcf, 0x1d, 0x36, ++ 0x7c, 0x35, 0x79, 0xd7, 0xf1, 0x5e, 0x6c, 0xf2, 0x76, 0x10, 0xf9, 0xf9, ++ 0x75, 0x8f, 0xd6, 0x57, 0x49, 0x1a, 0xc0, 0x39, 0x33, 0xd5, 0x76, 0x7c, ++ 0x7f, 0x57, 0xed, 0x7b, 0xb8, 0xfa, 0x4d, 0x72, 0xdc, 0x93, 0x12, 0x7f, ++ 0xbf, 0xf0, 0x63, 0x57, 0x1b, 0x7e, 0x64, 0xf8, 0xef, 0xfb, 0xa5, 0x2c, ++ 0xe7, 0xef, 0x08, 0xd6, 0x2f, 0x4d, 0xad, 0x22, 0xcf, 0x07, 0x39, 0x7e, ++ 0x4a, 0x5e, 0xf8, 0x1c, 0xbb, 0x66, 0xd3, 0x5a, 0x7e, 0x79, 0xa2, 0xf2, ++ 0x25, 0xe4, 0x72, 0x58, 0xcb, 0xc7, 0x9c, 0x93, 0x57, 0xa1, 0x1f, 0x3d, ++ 0x9f, 0xe5, 0xbc, 0x1d, 0x91, 0x53, 0x0e, 0xaa, 0x51, 0xa1, 0x7e, 0xb5, ++ 0xd8, 0x79, 0x16, 0x9d, 0x35, 0xfe, 0x9e, 0xa5, 0x85, 0x3a, 0xbe, 0x9f, ++ 0x4b, 0xe9, 0xb8, 0xce, 0xa8, 0xb8, 0x58, 0xaf, 0xab, 0x1a, 0xc3, 0xfe, ++ 0xda, 0xa2, 0xb6, 0x17, 0xa2, 0x7b, 0x9f, 0x69, 0xf9, 0x70, 0xf1, 0x1e, ++ 0xf4, 0x8b, 0xd5, 0x79, 0x31, 0x6c, 0x21, 0x6f, 0xf7, 0x2d, 0xe8, 0x0b, ++ 0xad, 0x92, 0x11, 0xae, 0x5b, 0x88, 0x9c, 0x29, 0xe0, 0x3b, 0xfc, 0xfd, ++ 0xdf, 0x50, 0x8d, 0xf3, 0xf5, 0x7c, 0x47, 0x64, 0xd5, 0xe4, 0x47, 0x30, ++ 0x63, 0xe2, 0x02, 0x3e, 0x2c, 0x6f, 0xe7, 0x1d, 0xc3, 0x57, 0xa9, 0x57, ++ 0xe1, 0x41, 0x7c, 0x05, 0x4e, 0x0d, 0x01, 0x63, 0x83, 0x5a, 0x2f, 0xda, ++ 0x86, 0xb7, 0xc1, 0xba, 0x48, 0x5d, 0x7d, 0xfc, 0x62, 0x50, 0xbc, 0x0a, ++ 0xf0, 0x4c, 0xf1, 0x98, 0xe7, 0x90, 0xca, 0xa7, 0xe1, 0x8b, 0x36, 0x14, ++ 0xa7, 0x33, 0x62, 0xaf, 0x2a, 0x71, 0x9d, 0x95, 0xb8, 0x7e, 0x4f, 0x9a, ++ 0xbc, 0x9b, 0x78, 0x80, 0x0b, 0x5e, 0x3c, 0x86, 0x6f, 0xb8, 0x1f, 0x66, ++ 0xaa, 0x01, 0x7f, 0x6a, 0x37, 0x06, 0xf0, 0x47, 0xef, 0x20, 0xd0, 0x8b, ++ 0x73, 0x88, 0xfb, 0xa4, 0xa3, 0xfb, 0xaa, 0xf1, 0x43, 0xd7, 0x75, 0x43, ++ 0xf8, 0x6a, 0xa9, 0x78, 0xfd, 0xfd, 0xd9, 0xd3, 0xa6, 0x3f, 0x83, 0xfd, ++ 0x62, 0xe2, 0x3f, 0x97, 0xe6, 0x01, 0x34, 0x71, 0x7b, 0x3d, 0xd8, 0x0f, ++ 0xe0, 0x7f, 0xdc, 0xe3, 0x51, 0xd7, 0x3e, 0xc9, 0x93, 0x60, 0xee, 0x69, ++ 0x6d, 0x6f, 0x5a, 0xec, 0x8f, 0x88, 0x7d, 0xc7, 0xd7, 0x8f, 0xda, 0xbf, ++ 0x3e, 0xaf, 0x0f, 0x4d, 0x7d, 0x9a, 0xfd, 0x68, 0xf2, 0xc4, 0xe7, 0x17, ++ 0x6f, 0xaf, 0xeb, 0xfd, 0xbd, 0xdb, 0xf4, 0xe7, 0x23, 0x9e, 0xbd, 0xef, ++ 0xbc, 0x7e, 0xd4, 0xdf, 0x53, 0xf4, 0x9c, 0x88, 0xc1, 0x39, 0xf3, 0x87, ++ 0x9a, 0x33, 0x1c, 0x87, 0xed, 0xac, 0xca, 0x5c, 0x99, 0xd3, 0xe7, 0xe4, ++ 0xc5, 0xef, 0xbc, 0x99, 0xeb, 0xca, 0x6f, 0x99, 0x3f, 0xc7, 0xfd, 0x73, ++ 0x24, 0xde, 0xe6, 0x3c, 0xc0, 0x64, 0xb1, 0x35, 0x5f, 0xc8, 0x3b, 0xec, ++ 0xaa, 0xfc, 0x9b, 0x39, 0x30, 0x6e, 0xec, 0x43, 0x74, 0x47, 0xfd, 0xfa, ++ 0xad, 0xf5, 0x89, 0x3c, 0x60, 0x9e, 0x6d, 0x6c, 0xe2, 0xde, 0xfd, 0x67, ++ 0xb3, 0x79, 0x1f, 0x07, 0xea, 0xe8, 0x12, 0xd7, 0x3d, 0xae, 0xea, 0xcf, ++ 0xef, 0x03, 0xef, 0x9e, 0xb7, 0xa2, 0x7a, 0x5d, 0xe5, 0x42, 0x78, 0xf5, ++ 0xfa, 0xe3, 0xb2, 0xbf, 0x80, 0xb9, 0xf4, 0xda, 0x29, 0xce, 0xff, 0x7b, ++ 0x67, 0x37, 0x78, 0x3e, 0x7d, 0xf8, 0xc6, 0x35, 0x1d, 0xd7, 0xa3, 0xb4, ++ 0x3e, 0xe7, 0xb0, 0x3f, 0xa5, 0xdd, 0x50, 0xdf, 0x78, 0xb6, 0xb5, 0x1e, ++ 0x78, 0xd7, 0xa0, 0x5e, 0x4a, 0x6f, 0x36, 0x78, 0xaf, 0x36, 0xfd, 0x43, ++ 0xbf, 0xec, 0xcf, 0x40, 0xdf, 0xf4, 0x73, 0xb0, 0xae, 0x77, 0x36, 0x9b, ++ 0x73, 0xd7, 0xe4, 0x3b, 0xc8, 0xd3, 0xa3, 0xe3, 0x7e, 0xbb, 0x83, 0xb4, ++ 0x56, 0x87, 0xdd, 0x69, 0xe9, 0xc3, 0x13, 0x72, 0xf0, 0x4f, 0xc9, 0x0c, ++ 0x9f, 0x53, 0x7e, 0x81, 0x79, 0x46, 0xb9, 0x14, 0xe2, 0x2c, 0x1f, 0xc6, ++ 0xf7, 0x72, 0x1a, 0xeb, 0x3d, 0x69, 0xdc, 0x6f, 0xd3, 0x71, 0x87, 0xf5, ++ 0x7b, 0xd2, 0xc0, 0x9c, 0xf4, 0xeb, 0x9a, 0x37, 0x8f, 0x80, 0x2b, 0x31, ++ 0x7f, 0xff, 0x46, 0xe8, 0x7a, 0x4c, 0x2b, 0xa8, 0xcb, 0xba, 0x80, 0xfe, ++ 0x2b, 0x0d, 0x39, 0xfc, 0x7d, 0xa6, 0x80, 0xb9, 0x4a, 0x03, 0xc1, 0xfb, ++ 0x50, 0xfa, 0xb9, 0xa7, 0x39, 0xb7, 0xfc, 0x73, 0x2d, 0x31, 0xb6, 0x5c, ++ 0x0f, 0xde, 0x97, 0x2b, 0x31, 0xff, 0x9c, 0xd0, 0x76, 0x59, 0x54, 0xf3, ++ 0xc1, 0x3f, 0xd7, 0xc2, 0x52, 0xef, 0xbf, 0x64, 0x0e, 0xec, 0xa4, 0x9b, ++ 0x75, 0xc4, 0xb5, 0x56, 0x6f, 0xcd, 0xb3, 0x39, 0xcf, 0xd8, 0x83, 0xdf, ++ 0x26, 0x8e, 0xa6, 0x7d, 0x9c, 0x7f, 0x4a, 0xfc, 0xfc, 0x85, 0xdf, 0x21, ++ 0x39, 0x89, 0x47, 0xdb, 0xc5, 0xfa, 0x01, 0x99, 0xb3, 0xae, 0x27, 0x07, ++ 0xe7, 0xe3, 0x34, 0xfb, 0xd5, 0x49, 0x78, 0x77, 0xe4, 0xbc, 0xbe, 0x36, ++ 0xf1, 0x75, 0x8d, 0x00, 0x97, 0x46, 0x4c, 0x1d, 0x4c, 0xbd, 0x4c, 0x7d, ++ 0x50, 0xc7, 0xdc, 0x28, 0xab, 0x4d, 0x94, 0x47, 0x99, 0xa7, 0x23, 0xe5, ++ 0x3f, 0x83, 0xef, 0xb4, 0xa3, 0x45, 0xad, 0xff, 0x16, 0x7d, 0xc3, 0x7d, ++ 0x44, 0xf4, 0x83, 0x60, 0x73, 0x1e, 0x49, 0x01, 0x02, 0xef, 0xb2, 0x30, ++ 0x5d, 0x8f, 0xca, 0xf2, 0xb8, 0xe9, 0x9b, 0x60, 0xdf, 0x5d, 0xe1, 0x77, ++ 0xfa, 0xc2, 0xe6, 0xd6, 0xfe, 0x37, 0xf1, 0x69, 0xbd, 0x61, 0xe1, 0xa1, ++ 0x4d, 0xa5, 0xfd, 0x78, 0xd7, 0x74, 0xc4, 0xc1, 0xf3, 0x8e, 0xb8, 0xbf, ++ 0x4e, 0x8a, 0x0f, 0x89, 0xb8, 0x16, 0x77, 0x75, 0x26, 0x38, 0x8e, 0x4b, ++ 0x5f, 0xdf, 0xe2, 0xcf, 0x1f, 0x2d, 0xa7, 0xb0, 0xde, 0x5d, 0x82, 0xf9, ++ 0x08, 0xf3, 0x35, 0x4c, 0x17, 0xc0, 0xe7, 0x0f, 0x96, 0x80, 0xef, 0xd3, ++ 0x21, 0xd8, 0xe9, 0x7c, 0x9b, 0xef, 0x71, 0xbb, 0x1b, 0xe9, 0xac, 0x2d, ++ 0x0b, 0x4f, 0xf3, 0x16, 0xff, 0x3f, 0xd2, 0xa0, 0xb4, 0xbc, 0x5b, 0xa5, ++ 0xcf, 0xc0, 0xcf, 0x88, 0xaf, 0xce, 0xdb, 0xf1, 0x55, 0xa3, 0xa3, 0xf8, ++ 0x88, 0xed, 0xc2, 0x5b, 0xbb, 0x95, 0xb7, 0xa6, 0x8e, 0x79, 0xab, 0x2d, ++ 0x4f, 0xf7, 0x05, 0x79, 0x1a, 0x13, 0x9e, 0xfe, 0xed, 0xcd, 0xd3, 0xad, ++ 0x76, 0x31, 0xc7, 0x6f, 0xfe, 0x6f, 0xbc, 0x05, 0x1e, 0x18, 0xd4, 0xe7, ++ 0x77, 0xfb, 0xf8, 0x67, 0xfc, 0xf2, 0xcf, 0x9f, 0x43, 0x6a, 0xae, 0xfe, ++ 0x07, 0x92, 0xe2, 0x88, 0x7c, 0xe0, 0x0d, 0x00, 0x00, 0x00 }; + + static u8 bnx2_TPAT_b06FwText[] = { +- 0xbd, 0x59, 0x6f, 0x70, 0x5c, 0xd5, 0x7d, 0x3d, 0x6f, 0xf7, 0xed, 0xee, +- 0x93, 0xb4, 0x92, 0x9e, 0x90, 0x0c, 0xab, 0x56, 0x8d, 0xf6, 0x59, 0x6f, +- 0xa5, 0xc5, 0xab, 0xd8, 0x6f, 0x2d, 0xb9, 0xac, 0x87, 0x37, 0xcd, 0xb3, +- 0x2c, 0x29, 0x8b, 0xec, 0xd8, 0xeb, 0x42, 0x66, 0xe4, 0x09, 0x1d, 0x0b, +- 0x59, 0xd8, 0xc2, 0x18, 0xa2, 0x12, 0x3e, 0xa8, 0x13, 0x4f, 0xbd, 0xe8, +- 0x9f, 0x85, 0xbd, 0xd2, 0x23, 0x02, 0x2c, 0x3b, 0x93, 0x0e, 0x1e, 0xf9, +- 0x8f, 0x18, 0x58, 0x6b, 0xa1, 0xfd, 0x92, 0x69, 0xc3, 0x44, 0x13, 0x1b, +- 0xec, 0x90, 0x38, 0x4e, 0xa7, 0x5f, 0xcc, 0xb4, 0x9d, 0xaa, 0x80, 0x29, +- 0x50, 0x70, 0xdc, 0xce, 0xa4, 0x63, 0x0a, 0xf5, 0xed, 0xb9, 0x6f, 0x57, +- 0x46, 0x38, 0x4e, 0x3f, 0xd6, 0x33, 0x8b, 0x76, 0xef, 0x7b, 0xf7, 0xde, +- 0xdf, 0xbd, 0xbf, 0x73, 0xce, 0xef, 0xdc, 0xcb, 0x6a, 0x1f, 0xca, 0x51, +- 0xfa, 0x57, 0xc9, 0x4f, 0xfb, 0x23, 0x43, 0x4f, 0x6f, 0x58, 0x6b, 0xad, +- 0x95, 0xbf, 0x95, 0x00, 0x54, 0xfc, 0x3f, 0xfe, 0xf3, 0x03, 0xfa, 0x72, +- 0x1c, 0xf2, 0x03, 0xcd, 0x67, 0x2f, 0xae, 0xee, 0x30, 0xa1, 0xf9, 0xed, +- 0x87, 0x5a, 0x76, 0x9b, 0x80, 0x93, 0x4f, 0x44, 0x37, 0xe3, 0x7f, 0x44, +- 0xb6, 0x4e, 0x85, 0x6c, 0xff, 0x23, 0xfb, 0x8b, 0x75, 0x6f, 0xdc, 0x67, +- 0x5c, 0x3f, 0xe1, 0x87, 0xa6, 0xdb, 0x93, 0x9a, 0xde, 0x0c, 0xad, 0x81, +- 0x7d, 0x7e, 0xd4, 0xb2, 0x2b, 0x88, 0xaa, 0xe5, 0xb1, 0x80, 0x93, 0x39, +- 0xc3, 0xda, 0x83, 0x84, 0x7e, 0x8e, 0x0b, 0x72, 0x38, 0xc7, 0x99, 0x3c, +- 0x70, 0x28, 0xa7, 0xe0, 0x2a, 0xc7, 0x1c, 0xcf, 0x6b, 0x58, 0xf2, 0x7b, +- 0xd3, 0xf5, 0x95, 0xd9, 0xc8, 0x98, 0x53, 0x07, 0x45, 0xc8, 0x44, 0xf6, +- 0x0f, 0x6c, 0x33, 0x7e, 0x08, 0xe1, 0xd4, 0x5c, 0x3b, 0x32, 0xab, 0xcf, +- 0x6a, 0xd8, 0xe9, 0x36, 0xf4, 0x69, 0x36, 0xf8, 0x8e, 0x82, 0xd4, 0x7d, +- 0x1a, 0x7a, 0x0b, 0x71, 0x64, 0x0b, 0x59, 0x38, 0x85, 0x31, 0x7e, 0x34, +- 0x84, 0xa6, 0x34, 0x6d, 0xdd, 0xd4, 0xdd, 0xf2, 0x1d, 0x84, 0xa7, 0xae, +- 0x8b, 0x6b, 0x49, 0x1d, 0x6f, 0x6f, 0x14, 0xa2, 0xd2, 0x46, 0xb6, 0xa2, +- 0x3d, 0x0b, 0xbf, 0x6d, 0x58, 0x5b, 0xfc, 0x0a, 0x3a, 0xbf, 0x6e, 0xc6, +- 0xa7, 0x94, 0x07, 0x1f, 0xf4, 0xd9, 0xd0, 0x14, 0x3b, 0xaa, 0x35, 0xe5, +- 0x1b, 0x30, 0x51, 0xd0, 0x71, 0xa8, 0x50, 0x87, 0xb1, 0x02, 0x0e, 0xf8, +- 0x37, 0x04, 0x31, 0xa7, 0xc3, 0xf9, 0x4e, 0xcb, 0x01, 0xec, 0xcb, 0x0d, +- 0x63, 0x77, 0x2e, 0x85, 0xc3, 0x05, 0x19, 0x63, 0x14, 0xa3, 0x05, 0x15, +- 0xc1, 0x29, 0x23, 0xf2, 0x73, 0xdc, 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0xfb, 0x48, 0x4f, 0xc7, +- 0x4e, 0xf2, 0xd9, 0x44, 0x7e, 0xb9, 0x46, 0x51, 0x33, 0x4d, 0x21, 0x76, +- 0x9b, 0xff, 0x2d, 0xfa, 0xbf, 0xf2, 0xae, 0x10, 0xd3, 0x8c, 0xe1, 0x8a, +- 0x85, 0x03, 0x01, 0xc4, 0xfa, 0x6e, 0xb0, 0xae, 0x5f, 0xda, 0x68, 0x64, +- 0xf2, 0x4a, 0xa2, 0x77, 0xab, 0x22, 0xbd, 0x9e, 0xaf, 0xb3, 0x8c, 0xef, +- 0xb4, 0xd0, 0x1b, 0x7d, 0xc8, 0x0c, 0x06, 0xf9, 0xfd, 0x4d, 0xcb, 0xa0, +- 0x7f, 0x16, 0xa2, 0x3f, 0x25, 0xc7, 0x10, 0xa2, 0xc3, 0x92, 0xe7, 0x80, +- 0x31, 0x9e, 0x03, 0xb2, 0xa2, 0xc2, 0xbc, 0x42, 0x6d, 0x32, 0x32, 0x63, +- 0x8a, 0xc9, 0xbe, 0x51, 0x78, 0x3a, 0xcb, 0x67, 0xda, 0x54, 0x04, 0x7f, +- 0xed, 0xf9, 0xe7, 0x28, 0x35, 0xab, 0x01, 0x7f, 0xe3, 0xe9, 0x96, 0x8a, +- 0x3d, 0xcf, 0x1b, 0x29, 0x55, 0x39, 0x88, 0xf7, 0x2d, 0x43, 0xff, 0x21, +- 0xe3, 0xa6, 0xd6, 0x3c, 0xb7, 0x19, 0x51, 0x70, 0x8e, 0x6c, 0x9f, 0xbf, +- 0x46, 0xd1, 0x58, 0x3b, 0xbe, 0xdf, 0x22, 0x6b, 0xf7, 0x10, 0xba, 0x9b, +- 0xf7, 0xf3, 0xa3, 0xa2, 0x76, 0x46, 0x55, 0x76, 0xd0, 0x93, 0x54, 0xcf, +- 0x54, 0x63, 0xef, 0x7a, 0x21, 0xd6, 0xae, 0x77, 0xc0, 0x33, 0x5f, 0xfc, +- 0x02, 0x6b, 0xd0, 0x89, 0x1a, 0x23, 0x0d, 0xfc, 0x04, 0x3b, 0xe9, 0x65, +- 0x53, 0x6d, 0x39, 0xe0, 0x1e, 0xb9, 0xc6, 0x9f, 0x60, 0xb3, 0xf4, 0xc0, +- 0x56, 0xb5, 0xf4, 0x5b, 0x1e, 0x7e, 0x8b, 0x77, 0x48, 0x4c, 0xf5, 0xd1, +- 0xac, 0x28, 0x37, 0x8d, 0xbe, 0x79, 0xd6, 0xdb, 0x4b, 0xb1, 0xbb, 0xf5, +- 0x6f, 0xcd, 0x4b, 0x0f, 0x6c, 0x46, 0xb7, 0x28, 0x82, 0xb9, 0x78, 0x86, +- 0xb9, 0x88, 0x39, 0x61, 0x5a, 0x86, 0x6a, 0x3b, 0xe6, 0x54, 0x2b, 0xc3, +- 0xca, 0x83, 0xe4, 0x43, 0x5f, 0xb0, 0x9c, 0x1e, 0xc2, 0xa1, 0x7f, 0xf0, +- 0xa1, 0xf2, 0xa8, 0xf4, 0x14, 0x21, 0x6a, 0x4d, 0x53, 0x2f, 0x4f, 0x17, +- 0xd8, 0x97, 0x94, 0xfe, 0x83, 0x58, 0x3f, 0x7a, 0x53, 0x6c, 0xa6, 0xc7, +- 0xdd, 0x5c, 0xf2, 0xb8, 0xbb, 0x66, 0xd3, 0xf4, 0xc0, 0x9a, 0x22, 0xef, +- 0xd3, 0x52, 0x6d, 0x3c, 0x94, 0x3e, 0x28, 0x7d, 0x88, 0x5c, 0x83, 0x8e, +- 0x6b, 0x49, 0x89, 0x5d, 0x1d, 0xa3, 0xed, 0x46, 0x24, 0x0b, 0x79, 0x7f, +- 0x73, 0xbb, 0xbf, 0x80, 0x9e, 0xfe, 0x1d, 0xcf, 0x01, 0x7d, 0x07, 0x63, +- 0x31, 0x82, 0x42, 0xd4, 0x26, 0xfd, 0xe8, 0xf3, 0xce, 0x73, 0x11, 0x3d, +- 0x4d, 0xde, 0x5f, 0xa4, 0x4f, 0xf0, 0xf3, 0xdc, 0x7c, 0x90, 0x58, 0xfa, +- 0xac, 0x65, 0xe4, 0x58, 0x3d, 0xb2, 0x93, 0xb5, 0x30, 0xac, 0xfb, 0xa9, +- 0xab, 0x57, 0x72, 0x0f, 0xb2, 0x9e, 0xfb, 0xda, 0x23, 0x3c, 0x03, 0x34, +- 0xce, 0x64, 0x45, 0x3d, 0xfd, 0xe0, 0x37, 0x78, 0xee, 0xad, 0x69, 0x8b, +- 0xd3, 0x6f, 0x2f, 0xef, 0x95, 0x0f, 0x4f, 0x59, 0x26, 0x1c, 0xef, 0x77, +- 0x58, 0xef, 0x9a, 0xbd, 0x29, 0xe6, 0xcc, 0xbb, 0xf5, 0x8e, 0x62, 0x5c, +- 0x6a, 0x99, 0x6d, 0xa1, 0x65, 0x03, 0xcf, 0x8e, 0x77, 0x88, 0xa9, 0x47, +- 0x7a, 0x9f, 0x40, 0xb1, 0xdf, 0x9f, 0xce, 0x36, 0xe8, 0xdb, 0x59, 0xef, +- 0x16, 0x89, 0x95, 0x5d, 0xeb, 0x2d, 0x19, 0xcb, 0xa2, 0x8c, 0x85, 0xfe, +- 0xd2, 0xb9, 0xdf, 0x47, 0x5f, 0x92, 0x04, 0xaa, 0xcf, 0x3e, 0x45, 0x5e, +- 0xf9, 0x5a, 0xab, 0x91, 0x1d, 0x62, 0x8c, 0xc7, 0xfe, 0x91, 0x5b, 0x33, +- 0x30, 0x8d, 0x01, 0x1f, 0xfb, 0x4c, 0x59, 0xc0, 0x13, 0x0b, 0x3c, 0x97, +- 0x4e, 0xc7, 0xe8, 0xcb, 0xe9, 0x23, 0x17, 0x34, 0x3c, 0x3a, 0x5b, 0x8e, +- 0xef, 0xcd, 0x86, 0xb1, 0x6f, 0xd6, 0xbb, 0xd7, 0xda, 0x5a, 0xcb, 0xf7, +- 0x3a, 0x92, 0x42, 0xcc, 0x5b, 0xeb, 0xf1, 0x1e, 0x3d, 0xd4, 0x6a, 0xc5, +- 0x87, 0xc8, 0x51, 0xe8, 0x3a, 0x71, 0x53, 0xd3, 0xf2, 0x3d, 0x26, 0x58, +- 0x08, 0x73, 0xbd, 0xd4, 0xc9, 0x67, 0xbc, 0xef, 0x63, 0xf4, 0x8f, 0x19, +- 0x89, 0x41, 0x97, 0x18, 0x74, 0x89, 0xc9, 0x5b, 0x9e, 0x5a, 0x62, 0x39, +- 0x4e, 0x1f, 0xfd, 0xb4, 0x28, 0x62, 0xe3, 0x0b, 0x71, 0xda, 0x7c, 0x95, +- 0xfc, 0x55, 0xa9, 0xa1, 0xc0, 0xdf, 0xe7, 0x22, 0xfa, 0x8e, 0x82, 0xcc, +- 0xff, 0x5f, 0x96, 0xf2, 0xbf, 0x18, 0x2a, 0xea, 0x85, 0xe1, 0xcc, 0xa3, +- 0x01, 0xd3, 0x6e, 0x83, 0xbe, 0xd5, 0x1d, 0x19, 0xd6, 0x90, 0x8d, 0x56, +- 0xc3, 0x18, 0x9c, 0x86, 0xaf, 0x35, 0x0c, 0xb9, 0x76, 0x20, 0xef, 0xad, +- 0x51, 0x88, 0x09, 0xea, 0x9b, 0xcc, 0xc1, 0xbf, 0xe7, 0xd0, 0xea, 0x63, +- 0x3e, 0x1c, 0xc6, 0xbe, 0x8f, 0x7b, 0xf0, 0x71, 0x5e, 0xde, 0x73, 0xc6, +- 0xd2, 0x5d, 0xb8, 0xee, 0x8d, 0xf9, 0x51, 0x3e, 0x85, 0x23, 0xee, 0x25, +- 0x71, 0xa4, 0xae, 0xa8, 0xf1, 0x69, 0x9e, 0x8f, 0xaa, 0x8f, 0x96, 0xbc, +- 0x10, 0x39, 0x5c, 0xc9, 0xf5, 0x5e, 0x4b, 0x7a, 0xde, 0x9f, 0x35, 0x72, +- 0x50, 0x3b, 0x6d, 0x6e, 0xe4, 0xda, 0x6e, 0x8a, 0x89, 0x58, 0xb3, 0x56, +- 0x8c, 0x29, 0xa1, 0x9f, 0x42, 0x19, 0xb1, 0x2b, 0xcf, 0x48, 0x52, 0x3f, +- 0xe4, 0x6f, 0x9e, 0x4f, 0x54, 0x27, 0xe2, 0xe7, 0xba, 0x9c, 0x87, 0x64, +- 0x5b, 0xa8, 0xe4, 0x57, 0x97, 0xbd, 0x48, 0x07, 0x9f, 0x49, 0x2f, 0xf2, +- 0xb9, 0xe8, 0xab, 0xeb, 0xb8, 0xa5, 0x39, 0x59, 0xbe, 0x31, 0xee, 0xca, +- 0xfb, 0xab, 0x16, 0x3a, 0x62, 0x05, 0xe7, 0x18, 0xf9, 0xa9, 0xd6, 0x98, +- 0x3e, 0xca, 0xf1, 0x1c, 0x5d, 0x27, 0x97, 0x0f, 0xd2, 0x2f, 0xf3, 0x9d, +- 0x42, 0x0b, 0xfb, 0x48, 0x2d, 0xdb, 0xc1, 0xb5, 0xfe, 0xb6, 0x59, 0x62, +- 0x7b, 0xd4, 0x7d, 0xc3, 0xa7, 0x9a, 0x72, 0x9d, 0x89, 0xd4, 0x28, 0xe3, +- 0x59, 0xd2, 0xa5, 0xb7, 0x76, 0xa8, 0x6d, 0x09, 0xaf, 0x7f, 0x56, 0x95, +- 0x71, 0x78, 0xf1, 0xb0, 0x4d, 0x6a, 0x96, 0x91, 0x39, 0x87, 0x84, 0x33, +- 0x20, 0xcd, 0xc1, 0x2a, 0x19, 0x43, 0x53, 0x64, 0x80, 0xf1, 0x9c, 0xa8, +- 0xf3, 0xf4, 0x90, 0xcf, 0x38, 0x9f, 0xeb, 0xdb, 0x5a, 0x0e, 0x81, 0xd5, +- 0x49, 0xef, 0xdc, 0x5f, 0xfa, 0x7f, 0x18, 0x2a, 0x7d, 0x88, 0xc4, 0xe2, +- 0xff, 0x02, 0xc7, 0x2a, 0x26, 0xcf, 0x94, 0x1a, 0x00, 0x00, 0x00 }; ++ 0xbd, 0x58, 0x6d, 0x70, 0x5c, 0xd5, 0x79, 0x7e, 0xce, 0xbd, 0x77, 0xb5, ++ 0xd7, 0xd2, 0x4a, 0xba, 0xb2, 0xd6, 0x66, 0x5d, 0xdc, 0xfa, 0x1e, 0x74, ++ 0x57, 0x52, 0x58, 0x01, 0x77, 0x6d, 0x01, 0xeb, 0xe6, 0xb6, 0xbe, 0xc8, ++ 0xb2, 0xbc, 0xfe, 0x00, 0xe4, 0xc0, 0x4c, 0xe4, 0x96, 0x8e, 0x37, 0xc6, ++ 0x18, 0xd9, 0x90, 0xa9, 0x28, 0xfc, 0x58, 0x37, 0x4c, 0xbd, 0x95, 0x65, ++ 0x63, 0xc3, 0x4a, 0x6b, 0x0c, 0xb1, 0x4c, 0xda, 0x99, 0x78, 0x84, 0xb1, ++ 0x4c, 0x22, 0x7b, 0x0d, 0xe4, 0x07, 0x49, 0xc3, 0xa0, 0xc1, 0x0e, 0x08, ++ 0x06, 0xf3, 0x31, 0x6d, 0x67, 0x98, 0xe9, 0xa4, 0xf5, 0x18, 0xf3, 0x11, ++ 0x92, 0x18, 0x87, 0x4e, 0x3a, 0xa2, 0x10, 0x9f, 0x3e, 0x67, 0x77, 0xc5, ++ 0x57, 0x32, 0xd3, 0xfe, 0xaa, 0x66, 0x56, 0x7b, 0xf7, 0xec, 0xf9, 0x78, ++ 0xcf, 0xfb, 0x3e, 0xef, 0xf3, 0x3e, 0xef, 0x5e, 0x21, 0x50, 0x8f, 0xda, ++ 0x5f, 0x23, 0x5f, 0xd7, 0x7e, 0x6b, 0xe8, 0x3e, 0xff, 0x6a, 0xff, 0x6a, ++ 0x3e, 0x6e, 0x17, 0x40, 0x04, 0xff, 0x8f, 0x7f, 0x26, 0xe0, 0xcc, 0xd9, ++ 0xa1, 0x5f, 0xb0, 0x8d, 0xa0, 0x70, 0x79, 0x8f, 0x07, 0xdb, 0x0c, 0xe2, ++ 0xee, 0xed, 0x1e, 0x10, 0x4e, 0xa5, 0xdc, 0x95, 0xf8, 0x9d, 0x2a, 0xc4, ++ 0x2d, 0xe8, 0xf1, 0x3f, 0x0e, 0x3e, 0xbd, 0xe6, 0xb9, 0xeb, 0xe5, 0xc5, ++ 0xc3, 0x26, 0x6c, 0x27, 0xd8, 0x6b, 0x39, 0xed, 0xb0, 0x17, 0x73, 0xcd, ++ 0x3f, 0x76, 0xfc, 0x85, 0x40, 0xd3, 0xdc, 0x5e, 0x4a, 0x8d, 0xf8, 0x51, ++ 0x0c, 0xfb, 0x09, 0xec, 0x2e, 0x19, 0x08, 0x9d, 0x28, 0x76, 0x79, 0xb3, ++ 0x6a, 0x8b, 0x2f, 0xfd, 0xdd, 0x50, 0x4b, 0x4e, 0xfb, 0x32, 0xd1, 0x6b, ++ 0x22, 0xfc, 0x8e, 0xb7, 0x18, 0xbb, 0xcb, 0x09, 0x8c, 0x94, 0x6d, 0x9c, ++ 0x35, 0x47, 0xd0, 0x5b, 0x9e, 0x5b, 0xe7, 0x72, 0x5d, 0x27, 0xf6, 0x7c, ++ 0x79, 0xad, 0xbb, 0x1b, 0xa9, 0xc4, 0x1e, 0x18, 0xc8, 0xc5, 0x3d, 0xae, ++ 0x6b, 0x73, 0xf7, 0x40, 0x76, 0x72, 0x9f, 0x42, 0x5d, 0xb7, 0xcb, 0x3d, ++ 0x0a, 0x5c, 0x2f, 0xdd, 0xa3, 0xd0, 0x7b, 0x65, 0xf8, 0xf9, 0x2d, 0xf5, ++ 0x5c, 0xc7, 0x62, 0x3c, 0xc3, 0xfd, 0x9f, 0x2e, 0x3b, 0x38, 0x59, 0xf6, ++ 0xf0, 0x7c, 0xd9, 0xc5, 0x8f, 0xca, 0x71, 0x3c, 0x55, 0xb6, 0x73, 0x76, ++ 0x80, 0xfe, 0xf8, 0xe8, 0x4e, 0x95, 0xf0, 0x50, 0xf8, 0xa3, 0xc0, 0x3b, ++ 0x74, 0xc8, 0x88, 0x65, 0xfe, 0xe6, 0x3a, 0xf4, 0xcf, 0x3f, 0x6e, 0x63, ++ 0x43, 0x69, 0x71, 0x2e, 0x1a, 0x80, 0x73, 0x04, 0xfc, 0xeb, 0x6c, 0xf4, ++ 0x73, 0x8f, 0x02, 0xf7, 0x0f, 0xcb, 0x23, 0x7c, 0xd9, 0x78, 0xb7, 0x68, ++ 0xdb, 0xcd, 0xa3, 0x0b, 0xf5, 0x1c, 0xfc, 0xaa, 0x78, 0x51, 0x5d, 0x48, ++ 0x3b, 0x78, 0x65, 0xb9, 0x52, 0x8d, 0x01, 0x0a, 0x0d, 0xdd, 0x05, 0x98, ++ 0x81, 0xcc, 0xae, 0x33, 0x05, 0x7a, 0xaf, 0xf2, 0x3a, 0x47, 0xc5, 0x2d, ++ 0xb7, 0x18, 0x01, 0x6c, 0x11, 0xb8, 0x56, 0xdb, 0x54, 0x06, 0xfb, 0xca, ++ 0xbc, 0x17, 0xed, 0x19, 0x29, 0x23, 0xfc, 0xcb, 0x0e, 0x13, 0x13, 0x71, ++ 0xdc, 0xff, 0x76, 0xb7, 0x85, 0x8f, 0x8b, 0x32, 0xd1, 0x69, 0xde, 0x8f, ++ 0x9d, 0xc5, 0x3c, 0xee, 0x28, 0xa2, 0x60, 0x04, 0x43, 0xf8, 0x46, 0x77, ++ 0xc0, 0x7b, 0x86, 0xf8, 0x7e, 0x19, 0x76, 0x6b, 0x70, 0xfa, 0xf2, 0x7b, ++ 0xdb, 0xe5, 0xe1, 0xd0, 0x00, 0xb2, 0x63, 0x40, 0x5f, 0x49, 0xe0, 0x54, ++ 0x46, 0x60, 0x8b, 0x7f, 0x19, 0x0a, 0x4e, 0x37, 0xf6, 0x96, 0x65, 0xb6, ++ 0xc0, 0xef, 0xae, 0x1a, 0x85, 0xbd, 0x28, 0xb8, 0xcd, 0x5a, 0x5e, 0x82, ++ 0xdd, 0x12, 0x0c, 0x58, 0xe9, 0xb1, 0xb6, 0xd9, 0x63, 0x42, 0xe6, 0x57, ++ 0x98, 0x32, 0x04, 0x64, 0xa6, 0xd3, 0x48, 0x15, 0x94, 0x90, 0x43, 0x17, ++ 0xa1, 0x6d, 0xba, 0xcd, 0xba, 0x66, 0x4a, 0xbf, 0x0f, 0x58, 0x57, 0x4f, ++ 0x01, 0xeb, 0xb9, 0xe7, 0x43, 0xcb, 0x05, 0xb6, 0xa7, 0x7f, 0xad, 0xc2, ++ 0x05, 0x32, 0x3c, 0x2c, 0xba, 0x31, 0x5a, 0x06, 0x6e, 0x1a, 0x83, 0x1d, ++ 0xe3, 0xdc, 0x22, 0xf7, 0xae, 0xe7, 0xdc, 0xb5, 0xa3, 0x6d, 0x83, 0x33, ++ 0x42, 0xf2, 0x6e, 0x72, 0x00, 0x48, 0xf9, 0xc7, 0x21, 0xdd, 0x75, 0x42, ++ 0x3a, 0x7b, 0x6a, 0x7b, 0x26, 0x6b, 0x7b, 0x5e, 0x31, 0x65, 0x8b, 0x55, ++ 0x25, 0x88, 0xde, 0x12, 0xdc, 0x27, 0x7d, 0xf0, 0x2e, 0x31, 0xde, 0xbb, ++ 0x1e, 0x6e, 0x8b, 0xf4, 0x0f, 0x73, 0x6e, 0x34, 0xe8, 0xb2, 0xde, 0x2b, ++ 0x0a, 0x7c, 0xe8, 0xe9, 0xf9, 0x5d, 0xda, 0x96, 0xd0, 0x09, 0x32, 0xa2, ++ 0xbf, 0xbc, 0x7f, 0x2e, 0x47, 0x8c, 0x93, 0x7e, 0x1c, 0x58, 0x88, 0xe6, ++ 0x16, 0x6f, 0x3e, 0x1e, 0x76, 0xd0, 0x18, 0xf5, 0x96, 0x19, 0x0f, 0x38, ++ 0x75, 0x38, 0xe9, 0xff, 0x56, 0xe1, 0x1b, 0x7a, 0x3e, 0xf0, 0xed, 0x47, ++ 0x1c, 0xc4, 0xbc, 0x8b, 0x38, 0x9a, 0xde, 0x66, 0xbc, 0xea, 0x0c, 0xa1, ++ 0xc9, 0xfb, 0xb9, 0xf1, 0x9a, 0x13, 0xc7, 0x43, 0xbc, 0xcf, 0x9d, 0xc9, ++ 0x38, 0x1e, 0x28, 0x7f, 0x75, 0x5f, 0x4b, 0x64, 0xc7, 0xdf, 0x51, 0x68, ++ 0xa9, 0xac, 0x0f, 0x9f, 0xf5, 0x27, 0x80, 0xcb, 0xf4, 0x78, 0x5e, 0x6c, ++ 0x2c, 0x5d, 0x52, 0x6e, 0x34, 0x83, 0x07, 0x4a, 0x36, 0xe6, 0xd1, 0xae, ++ 0x88, 0x67, 0xe3, 0xed, 0x62, 0x5e, 0xac, 0x2a, 0x87, 0x62, 0xcd, 0x64, ++ 0x8f, 0x08, 0x27, 0x2d, 0xd1, 0x33, 0x0e, 0x62, 0x53, 0xa9, 0x35, 0xbe, ++ 0xc0, 0x7f, 0xf8, 0xff, 0x6a, 0x9c, 0x6d, 0x95, 0xa1, 0x2b, 0x2e, 0x29, ++ 0x2f, 0x69, 0xa0, 0xde, 0xeb, 0x13, 0x6b, 0x27, 0x95, 0xda, 0xeb, 0x67, ++ 0x45, 0xef, 0x24, 0xec, 0x86, 0x20, 0xb0, 0xee, 0x1a, 0x3d, 0x6d, 0xe4, ++ 0x16, 0xc4, 0x50, 0x2a, 0xb9, 0x38, 0xe5, 0x6b, 0xfc, 0xce, 0x83, 0xe5, ++ 0x09, 0xbe, 0x10, 0x3b, 0xe3, 0xc3, 0x8a, 0xf1, 0x79, 0x6a, 0x83, 0x85, ++ 0x91, 0xee, 0xb5, 0x95, 0x35, 0x11, 0x62, 0xe5, 0x89, 0x62, 0x16, 0x06, ++ 0xf1, 0xb7, 0x28, 0x48, 0xce, 0x4e, 0x10, 0xf3, 0x6f, 0xf9, 0xc9, 0xce, ++ 0x8f, 0x4d, 0x0b, 0x68, 0x95, 0x09, 0x1a, 0x2a, 0xac, 0x20, 0xd9, 0x79, ++ 0x04, 0x02, 0xa6, 0x67, 0xe1, 0x15, 0x3f, 0x82, 0x70, 0x83, 0x8d, 0x5d, ++ 0xc4, 0x55, 0x1d, 0xc7, 0x8f, 0x56, 0xc6, 0xf5, 0x67, 0x38, 0xab, 0xca, ++ 0x5f, 0xcd, 0x79, 0x8e, 0x97, 0xda, 0x90, 0xab, 0xe4, 0x3d, 0x9c, 0x75, ++ 0xbc, 0xef, 0xb7, 0x2a, 0x9c, 0xf3, 0x27, 0x9f, 0x8d, 0xdd, 0x48, 0x3b, ++ 0xcd, 0xc0, 0xcb, 0x3d, 0x2e, 0x16, 0xa1, 0xd0, 0x02, 0xda, 0x6d, 0xe0, ++ 0x42, 0x7a, 0x21, 0xa6, 0x5b, 0xf4, 0xd7, 0x71, 0xa7, 0x7f, 0xbc, 0x55, ++ 0xc7, 0x44, 0xef, 0xe5, 0xac, 0x1a, 0x57, 0xea, 0x79, 0xbf, 0x0e, 0xb3, ++ 0x1d, 0xc3, 0x33, 0xcc, 0x12, 0x7f, 0x11, 0x73, 0xf2, 0x25, 0x9e, 0xdf, ++ 0xb2, 0xcc, 0x84, 0xb9, 0xcc, 0x35, 0xdd, 0xf9, 0xc0, 0x44, 0x51, 0x73, ++ 0x82, 0x9c, 0x7d, 0x89, 0xff, 0xcf, 0x95, 0x35, 0x3e, 0x7d, 0xe2, 0x53, ++ 0xa0, 0xbd, 0x43, 0xc7, 0xdd, 0xb7, 0xda, 0x89, 0xbd, 0xed, 0xf4, 0x67, ++ 0x84, 0x79, 0xf0, 0x20, 0xed, 0x3d, 0x57, 0xfc, 0x9e, 0xb1, 0xca, 0x91, ++ 0xae, 0x3e, 0xe1, 0x9d, 0x22, 0xc4, 0xf3, 0xfe, 0xdf, 0x69, 0x1f, 0xbb, ++ 0xdc, 0x96, 0x98, 0xb9, 0x8f, 0x98, 0xd1, 0xdc, 0xb3, 0xde, 0x72, 0xc6, ++ 0xe4, 0xc0, 0xfb, 0x34, 0x22, 0x11, 0x0c, 0x59, 0x89, 0x52, 0x6a, 0xef, ++ 0x20, 0xbf, 0xb7, 0x83, 0xac, 0x65, 0x8f, 0xca, 0x3c, 0xcf, 0xcb, 0x59, ++ 0x86, 0x4c, 0x34, 0x9b, 0xa9, 0xa1, 0x11, 0x21, 0x07, 0x9b, 0x85, 0xec, ++ 0xbf, 0x07, 0xd2, 0x39, 0x21, 0xf4, 0x99, 0xeb, 0xad, 0xae, 0x0a, 0x46, ++ 0xb3, 0xc4, 0xa8, 0x7e, 0xbf, 0xcf, 0x4a, 0x55, 0xde, 0x87, 0xac, 0x2b, ++ 0xa7, 0x12, 0x18, 0x2d, 0x49, 0xdf, 0x15, 0x51, 0x7c, 0x2d, 0x6d, 0xe3, ++ 0x44, 0x52, 0x2d, 0x79, 0x21, 0x2d, 0x73, 0x3d, 0xe6, 0x62, 0xe6, 0x42, ++ 0x02, 0xc3, 0xc4, 0xd2, 0x3f, 0x24, 0x47, 0xd0, 0x53, 0x36, 0x89, 0x63, ++ 0x17, 0xfb, 0x4b, 0x51, 0xcc, 0x90, 0x9f, 0xea, 0xd2, 0x9d, 0x18, 0x29, ++ 0xc9, 0xce, 0x37, 0x90, 0xca, 0x1f, 0x61, 0xbc, 0xce, 0x2e, 0xf0, 0xb0, ++ 0xbf, 0xdc, 0xc6, 0x18, 0x49, 0x77, 0x15, 0x39, 0xca, 0xec, 0x96, 0xce, ++ 0x2e, 0xfa, 0xb6, 0x2e, 0x20, 0xb7, 0x95, 0x33, 0xdc, 0xa7, 0x80, 0x55, ++ 0xe5, 0xbc, 0xe8, 0x2b, 0xcf, 0xe1, 0xf4, 0xe7, 0xc4, 0xa6, 0xc6, 0xaa, ++ 0x8d, 0xcd, 0x25, 0xe0, 0xce, 0x92, 0x8f, 0x16, 0xcf, 0x78, 0x31, 0x8a, ++ 0x8b, 0xf4, 0xe3, 0x04, 0xee, 0x71, 0x42, 0x2c, 0xf2, 0xd6, 0xa9, 0x1d, ++ 0x71, 0x3d, 0x3f, 0x2f, 0xd6, 0x32, 0x6e, 0x61, 0x04, 0xc6, 0xa4, 0x6f, ++ 0xe2, 0x6c, 0x7c, 0x78, 0x7e, 0xa4, 0xc2, 0xbb, 0xfa, 0xdd, 0x44, 0xbf, ++ 0x8f, 0x35, 0x0e, 0xe4, 0x90, 0x2f, 0x0a, 0x83, 0x4d, 0xf4, 0xc3, 0x49, ++ 0x51, 0x18, 0x88, 0x41, 0x16, 0xee, 0x65, 0x79, 0xb1, 0xc7, 0x48, 0x12, ++ 0x0b, 0xe6, 0x78, 0xda, 0xc2, 0x5f, 0x97, 0x9e, 0x32, 0xce, 0x45, 0xea, ++ 0x60, 0x1e, 0x88, 0x20, 0x7a, 0xc0, 0x42, 0xf3, 0x01, 0x41, 0xdc, 0x15, ++ 0x3a, 0xa3, 0x7a, 0x1d, 0x12, 0xd8, 0x37, 0x6a, 0xe3, 0x9e, 0x8e, 0x08, ++ 0x2e, 0x24, 0xe5, 0xe0, 0x15, 0x62, 0xd8, 0x6f, 0xe2, 0xd8, 0xe8, 0x71, ++ 0xe9, 0xba, 0x46, 0x21, 0x82, 0xa6, 0x38, 0x22, 0xed, 0x75, 0x68, 0xe0, ++ 0xba, 0x9d, 0x25, 0xb5, 0xd3, 0x0e, 0x0a, 0x6e, 0x03, 0xa4, 0xff, 0x30, ++ 0xf7, 0x3d, 0x55, 0x54, 0xaa, 0xfe, 0x5a, 0x6f, 0xe6, 0x03, 0x53, 0x4e, ++ 0xef, 0xe0, 0xe7, 0xb7, 0xa6, 0xaa, 0xfb, 0xcf, 0x3b, 0x60, 0xa3, 0xf1, ++ 0x60, 0x65, 0xff, 0xd9, 0xa7, 0x68, 0xc1, 0x87, 0x25, 0x9d, 0x4f, 0x4a, ++ 0x45, 0x03, 0xaf, 0xff, 0x3d, 0xa1, 0xd4, 0x4d, 0xbe, 0xcc, 0xbd, 0x2c, ++ 0xda, 0x06, 0x46, 0xf9, 0x3c, 0x98, 0x4e, 0xba, 0x59, 0xda, 0x7c, 0xbe, ++ 0x1c, 0xa5, 0x7d, 0xcc, 0x05, 0x6f, 0x9b, 0xb1, 0xc3, 0x31, 0x51, 0xe7, ++ 0xed, 0x30, 0xb6, 0x56, 0xb0, 0xea, 0x60, 0xd1, 0x58, 0x3d, 0x96, 0x78, ++ 0xa1, 0xd8, 0xc4, 0xdc, 0xdc, 0x38, 0x69, 0x71, 0x9e, 0xce, 0x4d, 0x81, ++ 0xa8, 0xd7, 0x2b, 0x56, 0x4e, 0xf6, 0x55, 0xf2, 0x75, 0x60, 0xdc, 0xc0, ++ 0x9b, 0xfe, 0x0d, 0x88, 0x04, 0x59, 0x31, 0x30, 0xa9, 0xf3, 0x67, 0xad, ++ 0x58, 0x3d, 0xc9, 0xf8, 0xcd, 0xd7, 0xb9, 0x73, 0x83, 0x88, 0x04, 0x3a, ++ 0x5f, 0x3e, 0xcf, 0x21, 0x9b, 0x39, 0x74, 0xec, 0x7f, 0xc9, 0xa1, 0x87, ++ 0x4a, 0x16, 0x72, 0x2d, 0xd5, 0x7c, 0xe9, 0x65, 0x2c, 0xfe, 0xde, 0xaa, ++ 0x7e, 0xb3, 0x9d, 0xe3, 0xd1, 0x03, 0x3a, 0x87, 0x7b, 0x99, 0xc3, 0x1a, ++ 0xcf, 0x96, 0xd8, 0x34, 0x0e, 0xbb, 0x39, 0x08, 0xad, 0x0f, 0x47, 0x15, ++ 0xde, 0xf6, 0x95, 0xfa, 0x78, 0x99, 0xf6, 0x89, 0x1c, 0x7c, 0x96, 0x78, ++ 0x04, 0x09, 0xe9, 0x5d, 0x4f, 0xa9, 0x19, 0x3f, 0x95, 0x7d, 0x96, 0xbc, ++ 0x7c, 0x4e, 0xe8, 0xfb, 0x47, 0xe1, 0xa4, 0x35, 0x1e, 0x7b, 0xad, 0xab, ++ 0x2a, 0xb8, 0x0c, 0x89, 0x57, 0xd6, 0xea, 0xf9, 0x1a, 0x9b, 0x51, 0x34, ++ 0x24, 0x67, 0xe9, 0x1b, 0x39, 0xd4, 0x28, 0xd4, 0x92, 0x57, 0xd3, 0x55, ++ 0x5c, 0x16, 0x59, 0x9b, 0xd6, 0xf3, 0xac, 0xde, 0x71, 0x59, 0x58, 0x6f, ++ 0x56, 0xeb, 0xe8, 0x5e, 0x62, 0x43, 0x73, 0xdc, 0xe5, 0xed, 0x51, 0xec, ++ 0x23, 0x46, 0xbd, 0xb4, 0x8b, 0x61, 0xd6, 0xd5, 0xdd, 0x25, 0xe9, 0x0e, ++ 0x13, 0xa7, 0xbb, 0x6b, 0x38, 0x1d, 0x66, 0x2d, 0xdd, 0x0d, 0xb9, 0x57, ++ 0xd7, 0xd2, 0x08, 0x71, 0x4a, 0x1a, 0xab, 0xe0, 0x74, 0xa4, 0x86, 0xd3, ++ 0xde, 0x0a, 0x4e, 0x77, 0x1b, 0x1a, 0x9f, 0x1a, 0x7b, 0x9b, 0x78, 0xdf, ++ 0xb3, 0x51, 0x18, 0x3f, 0xe0, 0xfe, 0xe1, 0x82, 0xe1, 0x9e, 0x1a, 0xf6, ++ 0x7a, 0x34, 0xf6, 0x8c, 0x34, 0xee, 0x31, 0x78, 0xb7, 0x17, 0x44, 0x21, ++ 0xd7, 0x08, 0x99, 0x1d, 0x16, 0x85, 0xce, 0x79, 0xc4, 0xde, 0x33, 0x9c, ++ 0xd1, 0x40, 0xec, 0x55, 0x7d, 0xa6, 0xe7, 0xc7, 0x88, 0xbd, 0xff, 0x14, ++ 0x67, 0x23, 0x9a, 0x6b, 0x75, 0x6c, 0x81, 0x45, 0x27, 0x34, 0xd7, 0x46, ++ 0x49, 0x18, 0x16, 0xf2, 0x25, 0x63, 0x71, 0x02, 0x0a, 0x5b, 0xc9, 0x6d, ++ 0x6f, 0x7a, 0xc3, 0x7e, 0x0b, 0x6e, 0xc0, 0xe9, 0x2e, 0x03, 0x5a, 0x87, ++ 0x98, 0x13, 0x55, 0xec, 0xde, 0x45, 0xce, 0x68, 0x0a, 0x64, 0xe7, 0x59, ++ 0xea, 0x8d, 0x2d, 0xe9, 0x06, 0x94, 0xbc, 0xe1, 0xb0, 0x99, 0xd5, 0xd0, ++ 0xe6, 0xb9, 0xab, 0xa1, 0x6b, 0x61, 0x1c, 0x56, 0xbb, 0x8d, 0x86, 0xa3, ++ 0x5e, 0xee, 0x84, 0xd0, 0x78, 0x05, 0xba, 0x8e, 0xdb, 0xb4, 0x1f, 0x4e, ++ 0x7d, 0xe0, 0x65, 0x3e, 0x30, 0x1f, 0x17, 0x67, 0x9d, 0x6a, 0x3d, 0xe8, ++ 0x1b, 0xd7, 0x18, 0xfb, 0x95, 0x7a, 0xd3, 0x33, 0x70, 0x47, 0xb7, 0x52, ++ 0xde, 0xd2, 0x28, 0x22, 0x13, 0x36, 0xea, 0x0e, 0xb6, 0xe2, 0xa5, 0xae, ++ 0x08, 0xce, 0xde, 0xaa, 0xbf, 0x8f, 0xa2, 0x9e, 0x38, 0xdc, 0x74, 0x6d, ++ 0x14, 0x4b, 0x26, 0xaa, 0x98, 0x6c, 0xf0, 0x7e, 0x22, 0xee, 0x22, 0x26, ++ 0xe7, 0x79, 0x67, 0xc4, 0x36, 0x27, 0x83, 0xbd, 0xb4, 0xe9, 0x75, 0x72, ++ 0xfc, 0xf9, 0xe4, 0xae, 0x19, 0x8b, 0xf6, 0xaf, 0x58, 0x56, 0xe8, 0x5c, ++ 0x42, 0x51, 0xb7, 0x68, 0x42, 0x0e, 0x1c, 0xd3, 0x15, 0x66, 0xd4, 0x12, ++ 0x1b, 0x88, 0x77, 0xcd, 0xaf, 0x26, 0xe3, 0x74, 0xc5, 0xd2, 0xb6, 0xa1, ++ 0x9b, 0x71, 0x49, 0x9d, 0x49, 0x26, 0xb3, 0xa3, 0xc4, 0xfa, 0xb6, 0xe3, ++ 0x11, 0xd4, 0x1d, 0xf8, 0x2f, 0x65, 0x04, 0xcc, 0x85, 0x6e, 0x45, 0x7c, ++ 0x16, 0x32, 0xf5, 0xe4, 0x90, 0x8b, 0x88, 0xe3, 0xb1, 0xfd, 0x3b, 0xd5, ++ 0x12, 0x8e, 0xbf, 0x77, 0x7d, 0x33, 0xda, 0x96, 0xc9, 0xfc, 0x56, 0xee, ++ 0x3f, 0x9b, 0x2e, 0x74, 0x26, 0x18, 0xbb, 0x93, 0x70, 0x71, 0xd5, 0x98, ++ 0xcc, 0x1d, 0x43, 0x1d, 0x9a, 0x27, 0xbc, 0xec, 0x09, 0x11, 0x43, 0xe3, ++ 0x89, 0x18, 0xf6, 0x1d, 0xd7, 0xf9, 0x19, 0x83, 0x35, 0xe6, 0xcd, 0x76, ++ 0x88, 0x42, 0x3f, 0xf3, 0x73, 0xa6, 0x5f, 0xb4, 0xa3, 0x7d, 0x5c, 0x4e, ++ 0x67, 0x85, 0x17, 0x3e, 0x00, 0x0f, 0xed, 0xac, 0xcb, 0xf6, 0x09, 0x17, ++ 0x2b, 0x74, 0xfd, 0x28, 0xeb, 0xfc, 0xd1, 0xf5, 0xd4, 0xe0, 0x9d, 0x42, ++ 0xb1, 0xbe, 0x52, 0xf3, 0x7a, 0xf9, 0xea, 0x63, 0xfd, 0xb3, 0xc4, 0xba, ++ 0x71, 0x9d, 0x5b, 0x06, 0x66, 0xfc, 0x4b, 0x6a, 0x7b, 0x32, 0xcb, 0x5a, ++ 0x37, 0x8f, 0x79, 0x55, 0xcd, 0x27, 0xb4, 0xe8, 0xdc, 0x9a, 0x57, 0xcb, ++ 0x27, 0x0b, 0x67, 0x18, 0xbb, 0xc3, 0xff, 0xe7, 0xba, 0x64, 0x21, 0x71, ++ 0xc0, 0x40, 0x4b, 0x47, 0x14, 0xd7, 0x2c, 0x6d, 0x73, 0x9a, 0x11, 0xc5, ++ 0x4d, 0xbe, 0x83, 0x26, 0x62, 0x62, 0x3f, 0x73, 0x0a, 0xf3, 0xab, 0xb9, ++ 0xb6, 0x52, 0xd7, 0xab, 0x5a, 0xae, 0xe5, 0x4b, 0x09, 0xd6, 0x26, 0x5d, ++ 0x0b, 0x7a, 0x59, 0x0b, 0x2c, 0x1c, 0x2a, 0x6b, 0xdf, 0x3a, 0x78, 0x97, ++ 0x9c, 0xfd, 0x8a, 0xaf, 0x7d, 0xbb, 0x18, 0x25, 0xe6, 0xc6, 0x83, 0xcc, ++ 0x8d, 0xb5, 0xe5, 0x4b, 0x6a, 0x8d, 0xa7, 0xeb, 0x71, 0xc8, 0x7a, 0x6c, ++ 0x89, 0x9b, 0xc6, 0xe5, 0xa0, 0x2b, 0x4e, 0xdd, 0x49, 0x6c, 0x76, 0x36, ++ 0x1a, 0x4a, 0xbd, 0x9c, 0x4e, 0x85, 0xd4, 0x31, 0x99, 0xbb, 0x85, 0x74, ++ 0xdf, 0x27, 0x37, 0xad, 0x35, 0xa3, 0x58, 0x5e, 0xcb, 0xc1, 0x64, 0x2d, ++ 0x07, 0x3d, 0xe6, 0xa0, 0xdb, 0x8a, 0xf0, 0x13, 0xda, 0xd8, 0xc6, 0x1c, ++ 0xdc, 0x46, 0x9d, 0xfa, 0xfd, 0x52, 0x85, 0xf7, 0x33, 0x2b, 0x44, 0x6a, ++ 0xe6, 0x3c, 0xf3, 0xc9, 0xbd, 0xcc, 0xa3, 0x5e, 0x6b, 0xcb, 0x9c, 0x67, ++ 0xcc, 0x56, 0xd7, 0xf2, 0x69, 0x77, 0x8d, 0xf7, 0x1f, 0xa8, 0xe5, 0xd3, ++ 0xea, 0x2f, 0xe5, 0x93, 0xe6, 0xa7, 0x17, 0x7e, 0x87, 0x56, 0xad, 0x45, ++ 0xf2, 0x42, 0xdf, 0x2f, 0x67, 0x21, 0xfc, 0xb1, 0xaf, 0xcf, 0xb2, 0x61, ++ 0x05, 0x8d, 0x15, 0xbe, 0xb1, 0x82, 0x50, 0xf4, 0xb2, 0x76, 0xda, 0x5e, ++ 0x5e, 0x64, 0xe9, 0x3b, 0xbd, 0x6e, 0x2d, 0x63, 0xb1, 0x33, 0xfd, 0x0b, ++ 0x9c, 0x6d, 0x55, 0xaa, 0x2f, 0x7d, 0x49, 0xbd, 0xc1, 0xb8, 0xc4, 0xa8, ++ 0x3f, 0xd6, 0x4f, 0x66, 0x45, 0xff, 0xa4, 0xf6, 0x4d, 0x23, 0x22, 0xde, ++ 0x5a, 0xb1, 0x6a, 0x12, 0xb8, 0x87, 0x7a, 0xe6, 0x1c, 0xfd, 0xb2, 0xc6, ++ 0x97, 0x43, 0x6b, 0x78, 0xb7, 0x33, 0xbe, 0x85, 0x87, 0xcb, 0x55, 0xff, ++ 0xec, 0x2b, 0xcb, 0xcc, 0x34, 0x46, 0xb0, 0x86, 0x35, 0xed, 0x30, 0xf9, ++ 0xe2, 0xdf, 0x92, 0x51, 0xbc, 0x48, 0xbe, 0x78, 0x89, 0xf7, 0x3b, 0x54, ++ 0xbd, 0x9f, 0x3f, 0x8b, 0x54, 0xe6, 0xb4, 0xe6, 0x0b, 0x6a, 0xef, 0x43, ++ 0xe5, 0x36, 0xff, 0x34, 0xf1, 0xf8, 0x60, 0x49, 0x0e, 0xf4, 0xf1, 0x8e, ++ 0x76, 0xb7, 0x9c, 0x1d, 0x14, 0x02, 0x1b, 0x93, 0x70, 0xcc, 0x40, 0xdf, ++ 0xc3, 0xa5, 0xc6, 0xcd, 0xd0, 0x0f, 0x05, 0xf4, 0xf1, 0xae, 0x2b, 0x59, ++ 0xe3, 0x1e, 0x2b, 0x7f, 0x49, 0xd7, 0x61, 0x5b, 0x49, 0x73, 0x95, 0x52, ++ 0x1d, 0x69, 0xad, 0x95, 0xf2, 0xe2, 0x66, 0xcd, 0x29, 0x91, 0x28, 0x94, ++ 0xdf, 0x96, 0x58, 0xc2, 0xd8, 0xe7, 0x89, 0xaf, 0x77, 0xbd, 0x7a, 0xf2, ++ 0x42, 0x48, 0x5e, 0xef, 0x21, 0x6f, 0xf7, 0x8a, 0xbe, 0x0a, 0x9f, 0x67, ++ 0x45, 0x76, 0xd2, 0x16, 0x3d, 0xd4, 0x28, 0x1b, 0x98, 0x67, 0xee, 0xc2, ++ 0x79, 0xc4, 0x94, 0xc6, 0x95, 0x81, 0x1f, 0xf8, 0x6b, 0xc9, 0xf9, 0x37, ++ 0xd0, 0x57, 0xe4, 0xa5, 0x0a, 0x16, 0x6f, 0xa0, 0x4e, 0xaa, 0x62, 0xf1, ++ 0x87, 0xc4, 0x62, 0xae, 0x86, 0xc5, 0x48, 0x90, 0x24, 0xdf, 0x7d, 0x8e, ++ 0xc5, 0xde, 0x3f, 0xc0, 0xef, 0x5f, 0xc4, 0xdc, 0x7a, 0xcd, 0xef, 0x91, ++ 0x39, 0xcc, 0xb1, 0x3e, 0x77, 0x04, 0xe4, 0x61, 0x8d, 0x37, 0x1b, 0x7d, ++ 0x8f, 0xd6, 0x63, 0xc3, 0xa3, 0x31, 0xdc, 0xfc, 0xa8, 0x52, 0xaf, 0xf9, ++ 0xf0, 0x5a, 0xc8, 0x45, 0xbf, 0x48, 0x4f, 0xe0, 0x4c, 0x4b, 0xd2, 0xdd, ++ 0x07, 0xdd, 0x47, 0xf5, 0x5a, 0xb7, 0x17, 0xb5, 0x46, 0x09, 0xa9, 0x51, ++ 0x64, 0xff, 0xfb, 0xcc, 0xf5, 0x4d, 0x49, 0x99, 0xdf, 0x59, 0xe1, 0xfe, ++ 0x94, 0x4f, 0x2d, 0xbe, 0xd7, 0x30, 0x65, 0xb6, 0xdd, 0xa8, 0x62, 0xed, ++ 0x9a, 0x1a, 0xd6, 0xbe, 0x36, 0x65, 0xe3, 0x97, 0xac, 0x0b, 0x9b, 0xd3, ++ 0x51, 0xac, 0xd6, 0x35, 0xde, 0xd1, 0xbd, 0x54, 0x14, 0xfd, 0x8c, 0x8b, ++ 0xb1, 0x54, 0x51, 0x6f, 0x50, 0x77, 0x30, 0x96, 0xab, 0xd8, 0x4f, 0x9d, ++ 0xa1, 0x3e, 0xb9, 0xd1, 0xac, 0xf6, 0x52, 0xa3, 0x35, 0x7d, 0x72, 0x63, ++ 0x59, 0xe7, 0xa3, 0x4b, 0x0c, 0x44, 0x71, 0x9a, 0x6b, 0xf6, 0xf8, 0x55, ++ 0x7d, 0xf2, 0x3a, 0x52, 0x59, 0xad, 0x4f, 0x5c, 0xf2, 0x7e, 0xa9, 0xa2, ++ 0x4f, 0xb4, 0x1e, 0xd1, 0x5a, 0x44, 0xf7, 0x0b, 0xdd, 0xec, 0x17, 0xe4, ++ 0xb4, 0xd6, 0x2b, 0x46, 0xb7, 0xf4, 0x0d, 0x33, 0xc2, 0x1a, 0x99, 0x61, ++ 0x2c, 0x2f, 0xc3, 0xae, 0x47, 0x9a, 0x18, 0x8b, 0x46, 0xec, 0x70, 0x56, ++ 0x58, 0x4b, 0x3c, 0xcd, 0x9f, 0xd4, 0x20, 0xbf, 0xa7, 0x5d, 0x8e, 0x6a, ++ 0x8e, 0x65, 0xfc, 0xe7, 0xc6, 0xff, 0xbd, 0x36, 0xae, 0xe7, 0x67, 0x59, ++ 0xa3, 0xf5, 0x9a, 0x1f, 0x59, 0x55, 0xdc, 0xa3, 0xb9, 0xc9, 0xfb, 0x33, ++ 0x5c, 0xa0, 0x8d, 0x6f, 0x7e, 0x29, 0x8e, 0x36, 0xf3, 0x42, 0xc7, 0xf1, ++ 0x13, 0xae, 0xd5, 0xf1, 0xb6, 0xf1, 0x0e, 0x7d, 0x7c, 0x8e, 0x3e, 0xfe, ++ 0xe5, 0xa3, 0x01, 0xb9, 0x09, 0x9f, 0x1a, 0xf4, 0xf1, 0x76, 0xe2, 0xe6, ++ 0xc7, 0xfe, 0xf5, 0x68, 0x6f, 0x4d, 0xba, 0x1f, 0x98, 0x73, 0xf5, 0x16, ++ 0xf6, 0x12, 0xfa, 0x4e, 0xd1, 0xcf, 0xba, 0xd7, 0x39, 0x46, 0xff, 0x32, ++ 0x97, 0x2b, 0x1a, 0xa4, 0xdd, 0xac, 0xfa, 0xb7, 0xa3, 0xe6, 0xdf, 0xcc, ++ 0xd4, 0x36, 0x9e, 0xa3, 0xeb, 0xa9, 0xd6, 0xa3, 0xf7, 0x57, 0xfa, 0x25, ++ 0x33, 0xb8, 0xb5, 0x12, 0xab, 0xba, 0x20, 0x6f, 0xbd, 0x58, 0xd4, 0x35, ++ 0xbb, 0x9f, 0x35, 0x9b, 0x3d, 0x93, 0x29, 0x07, 0x07, 0x91, 0x9a, 0xe6, ++ 0x5e, 0x7b, 0x4f, 0x23, 0x15, 0xb2, 0x9f, 0x1a, 0x3a, 0xcf, 0xde, 0x27, ++ 0x63, 0xc8, 0xdc, 0x4c, 0x45, 0x4f, 0xde, 0x5a, 0xab, 0xd3, 0xfd, 0x35, ++ 0x5d, 0x79, 0x7f, 0xed, 0x9c, 0x3c, 0x75, 0xe5, 0xdc, 0x39, 0xfa, 0x2e, ++ 0x97, 0x5b, 0xfa, 0x59, 0xf7, 0x01, 0x6f, 0xf8, 0x3f, 0x53, 0x58, 0xd8, ++ 0x58, 0xd1, 0x1d, 0x9f, 0xdf, 0xd9, 0x12, 0x1b, 0xc7, 0x2f, 0xaa, 0x4c, ++ 0xc7, 0x5d, 0x26, 0xea, 0x95, 0xb2, 0x96, 0x85, 0x28, 0x96, 0x66, 0x54, ++ 0x31, 0x2e, 0x0b, 0x1a, 0x94, 0x2d, 0xc1, 0xdd, 0x8c, 0x0f, 0x6c, 0x2b, ++ 0x18, 0xb4, 0x46, 0x8a, 0x72, 0x88, 0xbd, 0x5c, 0x9e, 0x7d, 0x58, 0xb8, ++ 0x1f, 0x5a, 0xdf, 0xea, 0xf3, 0xee, 0xd6, 0x7d, 0x1c, 0xdf, 0x07, 0x69, ++ 0xcf, 0xdc, 0xb9, 0x21, 0x1e, 0x2b, 0xfd, 0x95, 0x7a, 0x2c, 0x2e, 0x73, ++ 0x7a, 0x8f, 0x08, 0xe7, 0x3c, 0x51, 0xd1, 0xcf, 0x83, 0x5a, 0x3f, 0xbb, ++ 0x1a, 0x8f, 0x63, 0x9e, 0x9c, 0x3d, 0x81, 0xd4, 0xc0, 0x05, 0x53, 0xf6, ++ 0xc7, 0xa8, 0x99, 0xd7, 0xd5, 0xf6, 0x5a, 0x51, 0xdb, 0xab, 0x6d, 0xea, ++ 0x21, 0xda, 0xad, 0xf1, 0x58, 0xad, 0x6f, 0x46, 0x10, 0x43, 0xd3, 0xa8, ++ 0xc7, 0x1a, 0x9f, 0xcc, 0x1d, 0x61, 0x9d, 0x89, 0x1d, 0xdf, 0x51, 0xb1, ++ 0xf7, 0x75, 0xff, 0x49, 0xb3, 0x92, 0xdf, 0x27, 0x74, 0x9d, 0xb0, 0x60, ++ 0xb1, 0xee, 0x5c, 0x39, 0x26, 0xc3, 0x2d, 0xe2, 0x23, 0xb5, 0x24, 0xe9, ++ 0x25, 0x56, 0x0b, 0xad, 0x7d, 0x92, 0xd4, 0x3e, 0x31, 0x64, 0x4e, 0xfc, ++ 0x0b, 0xed, 0xd3, 0xfa, 0x4d, 0xd7, 0x42, 0x07, 0x2d, 0xa3, 0x5e, 0x67, ++ 0x9b, 0x91, 0xa4, 0x76, 0x76, 0xd0, 0xfc, 0xd9, 0x7e, 0x96, 0x58, 0xc5, ++ 0x7d, 0xea, 0x0e, 0x38, 0xb8, 0x66, 0x4c, 0x3a, 0x47, 0x71, 0x81, 0x1c, ++ 0xee, 0x0d, 0x6a, 0x9d, 0x78, 0x75, 0x3a, 0xc9, 0x9a, 0xee, 0xa0, 0xeb, ++ 0xb3, 0x7d, 0x62, 0xa8, 0x1b, 0xd3, 0x67, 0x17, 0xa6, 0x4d, 0xc6, 0xc9, ++ 0x31, 0x8f, 0x72, 0xdc, 0x45, 0xfb, 0x89, 0x46, 0xf6, 0x5b, 0x4a, 0xf5, ++ 0xb3, 0x1e, 0x58, 0xac, 0xb9, 0xbd, 0x68, 0x1f, 0x1c, 0x11, 0xa9, 0x81, ++ 0x46, 0xa4, 0xfa, 0x63, 0xf0, 0x9c, 0x75, 0x42, 0xff, 0xc6, 0x30, 0xa7, ++ 0x49, 0x80, 0xc7, 0x8b, 0x7f, 0xce, 0x75, 0x49, 0x67, 0x0b, 0x31, 0xd6, ++ 0xf2, 0xa7, 0xa9, 0x7c, 0x0b, 0x52, 0x43, 0x0e, 0x3c, 0xf7, 0x75, 0xce, ++ 0x2b, 0x7c, 0x61, 0xde, 0xb3, 0x95, 0x79, 0xf4, 0xc5, 0xf5, 0x5a, 0x6b, ++ 0x29, 0xf5, 0x04, 0xf5, 0x56, 0xc1, 0xd1, 0x9c, 0x23, 0x30, 0xec, 0xeb, ++ 0x3d, 0x7b, 0x5c, 0x0b, 0x32, 0x71, 0x07, 0x3e, 0x51, 0x85, 0x78, 0xd8, ++ 0x19, 0xa9, 0xfc, 0x2e, 0x21, 0x9d, 0x1c, 0xb9, 0x6d, 0xba, 0xda, 0x67, ++ 0xb1, 0x2f, 0x52, 0xea, 0x45, 0x72, 0xd3, 0x13, 0xd4, 0x3e, 0xc3, 0x53, ++ 0x9f, 0xa8, 0x69, 0x6a, 0x9b, 0x11, 0x4f, 0xcf, 0xab, 0x72, 0xd0, 0x61, ++ 0x47, 0xa9, 0xc7, 0xf9, 0xdd, 0x9e, 0xa9, 0x39, 0x5e, 0xe2, 0x79, 0xe4, ++ 0x84, 0xdb, 0xbd, 0xff, 0x56, 0x9b, 0xbf, 0x34, 0x57, 0xa9, 0x31, 0xda, ++ 0xf0, 0x96, 0x8f, 0xfb, 0x23, 0x48, 0xe6, 0x66, 0xe9, 0x9f, 0x33, 0xcb, ++ 0x65, 0xff, 0x14, 0xef, 0xb9, 0x5e, 0xc8, 0x2c, 0xef, 0xd8, 0x3b, 0x0f, ++ 0x9a, 0x6b, 0x25, 0xf3, 0xc1, 0xf0, 0xea, 0xf8, 0xfc, 0x33, 0x5f, 0x26, ++ 0x8e, 0xf0, 0x7d, 0x73, 0x46, 0xef, 0xa1, 0x54, 0x8f, 0xaf, 0x7b, 0xfc, ++ 0x11, 0xf6, 0xf8, 0x05, 0xd5, 0xe0, 0xbd, 0xa1, 0x9e, 0xeb, 0x90, 0xfd, ++ 0x23, 0xc2, 0xe3, 0x5a, 0x97, 0x75, 0x41, 0xf7, 0x55, 0x23, 0xec, 0xab, ++ 0x5c, 0x3c, 0x4d, 0x8e, 0x39, 0x59, 0xee, 0xc4, 0xf3, 0x65, 0x0f, 0xcf, ++ 0xb0, 0x7e, 0x3c, 0x55, 0xb6, 0xb0, 0xf5, 0x11, 0x99, 0xb1, 0xc4, 0x4e, ++ 0x9c, 0xf7, 0xa5, 0xf3, 0x3d, 0xda, 0x6d, 0x06, 0x72, 0xff, 0x4a, 0xf2, ++ 0x0a, 0xcf, 0x28, 0xe4, 0xcc, 0x16, 0x61, 0x07, 0x36, 0xbe, 0xd3, 0x61, ++ 0xe0, 0x70, 0x7c, 0x08, 0x7d, 0xed, 0x77, 0xf3, 0x65, 0xa1, 0xf5, 0x80, ++ 0xae, 0xd5, 0xba, 0xdf, 0x68, 0xc6, 0x9d, 0xe4, 0xb3, 0xab, 0x97, 0x86, ++ 0xf8, 0x75, 0xba, 0xad, 0xf3, 0x25, 0x41, 0xcd, 0xd0, 0x22, 0xb3, 0xc0, ++ 0x4f, 0xb1, 0x91, 0xfd, 0x42, 0x66, 0xd9, 0xfe, 0x5a, 0x6f, 0xfe, 0x53, ++ 0xac, 0xd4, 0x7d, 0x86, 0xdf, 0xcc, 0x7a, 0x57, 0x8d, 0xc3, 0xe1, 0x8a, ++ 0x1f, 0x0d, 0x34, 0x1d, 0x2c, 0xa8, 0x7a, 0x4f, 0xe6, 0x26, 0x2b, 0x3a, ++ 0x6a, 0xa1, 0x73, 0x23, 0xfb, 0x80, 0x86, 0x03, 0x9e, 0xbb, 0x4e, 0x28, ++ 0xc6, 0x62, 0x37, 0x63, 0x91, 0x0c, 0x63, 0x6c, 0xb7, 0x9b, 0x83, 0x64, ++ 0xd8, 0x2c, 0xf2, 0xe2, 0x16, 0x5d, 0x63, 0xeb, 0xea, 0xd9, 0x7f, 0xb3, ++ 0xa6, 0x4e, 0x1a, 0xec, 0x47, 0x74, 0x3f, 0x1e, 0xc5, 0x54, 0xba, 0x8d, ++ 0x7d, 0x52, 0x14, 0xdb, 0xd3, 0x3d, 0xd4, 0x35, 0x06, 0x8c, 0x83, 0x97, ++ 0xd4, 0xca, 0x2f, 0xf4, 0x11, 0x9b, 0xc6, 0x35, 0x87, 0xd9, 0x62, 0x23, ++ 0xf3, 0x37, 0xb3, 0x8c, 0x62, 0xed, 0x16, 0xdd, 0xc3, 0xeb, 0x3b, 0x38, ++ 0xec, 0x8f, 0x0d, 0x4c, 0x2f, 0x70, 0xb0, 0xab, 0x5b, 0x26, 0x0a, 0xd0, ++ 0xb9, 0xfc, 0xd5, 0x9a, 0x02, 0x27, 0xfb, 0x7b, 0x75, 0x06, 0xce, 0x06, ++ 0xda, 0x22, 0xeb, 0x94, 0x6a, 0x4d, 0x9b, 0xc8, 0x55, 0xea, 0x4d, 0xc2, ++ 0xc9, 0xb2, 0xff, 0x9b, 0x99, 0x62, 0x4f, 0x76, 0x50, 0xa9, 0x9d, 0xc4, ++ 0xd2, 0xc7, 0x1d, 0xc3, 0x87, 0xd8, 0x89, 0xef, 0x6d, 0x65, 0x6f, 0xf5, ++ 0x75, 0xb6, 0x6f, 0x6f, 0x15, 0xbf, 0x49, 0xfe, 0x36, 0xba, 0x13, 0xd0, ++ 0xfd, 0x4e, 0x41, 0x45, 0x3c, 0x6f, 0xf6, 0x71, 0x6a, 0xc1, 0xdf, 0x2c, ++ 0xeb, 0x82, 0x3b, 0xbf, 0xea, 0xab, 0xd5, 0xd4, 0x52, 0x1f, 0x91, 0xf3, ++ 0xc3, 0xca, 0xe7, 0x98, 0xb3, 0x6e, 0xfc, 0x92, 0xda, 0x4c, 0xdf, 0xf4, ++ 0x54, 0xed, 0xb2, 0xea, 0x03, 0x36, 0x89, 0xd7, 0xc2, 0x59, 0xf3, 0x07, ++ 0x6c, 0xfa, 0xbc, 0xde, 0xc5, 0x9c, 0x35, 0xe3, 0x8b, 0x69, 0xa3, 0x74, ++ 0xa7, 0x2b, 0xf8, 0xf1, 0xf1, 0x91, 0x37, 0x9c, 0x98, 0x8f, 0x42, 0x27, ++ 0x73, 0x6c, 0xf6, 0x9f, 0x38, 0xd6, 0xbe, 0x14, 0xf8, 0x4d, 0xf9, 0xbb, ++ 0xe4, 0x7d, 0xa3, 0xab, 0x05, 0x85, 0x19, 0xda, 0x78, 0xe8, 0xeb, 0xc4, ++ 0x64, 0x7e, 0x0c, 0xf7, 0xb1, 0x8d, 0xc0, 0xb3, 0xac, 0xb7, 0xc7, 0xc8, ++ 0x19, 0xcd, 0x69, 0x07, 0x65, 0x3e, 0x1f, 0x29, 0x25, 0x07, 0x4f, 0x33, ++ 0x6f, 0x8f, 0xf3, 0xf9, 0x28, 0xef, 0xb9, 0x95, 0xfa, 0xee, 0xde, 0xf1, ++ 0x7a, 0x7c, 0x7b, 0x3c, 0x86, 0xad, 0xe3, 0x01, 0x35, 0x05, 0x6e, 0x6b, ++ 0xe4, 0xbe, 0xaf, 0x12, 0xcf, 0x9b, 0x97, 0x5e, 0x87, 0xb5, 0x4e, 0xd2, ++ 0xbd, 0x9b, 0xb9, 0x57, 0x77, 0x10, 0x8e, 0x43, 0x1c, 0xfd, 0xb3, 0xb7, ++ 0x5c, 0xa0, 0x89, 0x7a, 0x7f, 0xa9, 0x25, 0xd6, 0x8f, 0xaf, 0xae, 0x3c, ++ 0x8f, 0xa4, 0xf3, 0xd4, 0x16, 0xc4, 0x64, 0x89, 0x98, 0x64, 0x6c, 0x9e, ++ 0x2e, 0x11, 0x97, 0xd4, 0x86, 0x27, 0x4b, 0x1a, 0xdb, 0x3e, 0x9e, 0xeb, ++ 0x18, 0x52, 0x55, 0xac, 0x7c, 0xaa, 0x9e, 0xf0, 0x5e, 0x8b, 0xa0, 0xde, ++ 0xd2, 0xbf, 0xed, 0xe0, 0xcd, 0x62, 0xc2, 0xd9, 0x50, 0xd6, 0x78, 0xf8, ++ 0xdb, 0x1a, 0x1e, 0xde, 0x8e, 0x54, 0xf5, 0x89, 0x9c, 0x99, 0x84, 0xe6, ++ 0xba, 0xc5, 0xce, 0x4d, 0xa5, 0xe1, 0x69, 0xfa, 0x3e, 0x4f, 0x8d, 0xed, ++ 0xbe, 0xcf, 0x90, 0x8f, 0x4d, 0x19, 0x5d, 0xec, 0xa9, 0xe9, 0x0f, 0x7d, ++ 0x67, 0xe6, 0x6f, 0x5a, 0x76, 0xea, 0x98, 0x1c, 0x2f, 0xe2, 0x56, 0xf6, ++ 0x3d, 0x7e, 0x88, 0xea, 0xdd, 0xa6, 0x78, 0xe7, 0x87, 0x78, 0xe7, 0x1f, ++ 0xf2, 0x79, 0xa2, 0x94, 0xcc, 0xf6, 0xf0, 0xce, 0x4f, 0xf2, 0x79, 0xb2, ++ 0xd4, 0x5a, 0xa7, 0xcf, 0x98, 0x9c, 0x0a, 0x59, 0x07, 0x5e, 0x56, 0xa5, ++ 0x78, 0x25, 0x1c, 0xec, 0x81, 0x0d, 0x34, 0x1c, 0x9c, 0xe3, 0x67, 0xfd, ++ 0xdb, 0x92, 0xae, 0x71, 0x9a, 0xf3, 0x07, 0x75, 0x4d, 0xce, 0x5c, 0x29, ++ 0x2e, 0xa9, 0x8f, 0x3c, 0x19, 0x3e, 0x8d, 0x53, 0x6a, 0x3e, 0x52, 0x33, ++ 0xf3, 0x85, 0x9c, 0x5e, 0x61, 0x48, 0x77, 0x91, 0x59, 0xe5, 0xea, 0xce, ++ 0x1a, 0x57, 0x7b, 0x53, 0x37, 0xd6, 0x55, 0xef, 0x90, 0x72, 0x8e, 0x60, ++ 0x1e, 0xb1, 0xaf, 0x6b, 0xaa, 0xe6, 0x1f, 0xfd, 0x99, 0xfa, 0xce, 0x0a, ++ 0x13, 0x26, 0xfd, 0x10, 0xde, 0xaa, 0xc7, 0xa2, 0xb5, 0xdf, 0x7c, 0x52, ++ 0xbe, 0xee, 0x05, 0xa7, 0xe3, 0x3d, 0xfc, 0x4e, 0xf7, 0x82, 0x9f, 0xa8, ++ 0x5c, 0xbc, 0xe7, 0x33, 0xce, 0x2a, 0xa0, 0x8b, 0xda, 0xe3, 0x7d, 0x72, ++ 0x42, 0x07, 0x55, 0x94, 0xc0, 0x29, 0xf6, 0x61, 0x47, 0xba, 0x92, 0xce, ++ 0x2e, 0xee, 0x17, 0x3a, 0x0e, 0xb9, 0x60, 0x27, 0x75, 0x26, 0xe7, 0x94, ++ 0x3b, 0xb8, 0x46, 0x73, 0xe1, 0x7d, 0xf4, 0xcd, 0x6f, 0xdb, 0x2d, 0xcf, ++ 0xc7, 0xae, 0xd2, 0x73, 0x86, 0xe5, 0x69, 0xbf, 0xa4, 0x32, 0xbb, 0x68, ++ 0xcf, 0x59, 0xda, 0x13, 0xf1, 0x42, 0x72, 0x63, 0xaa, 0xb2, 0xbe, 0x60, ++ 0x69, 0x3b, 0x2a, 0xf6, 0x70, 0x4c, 0x73, 0x9e, 0xec, 0x3f, 0xc5, 0x1a, ++ 0xbb, 0x05, 0xfa, 0x77, 0x0a, 0x6d, 0x43, 0x5b, 0x62, 0x0b, 0xed, 0x39, ++ 0x1c, 0xaf, 0xf0, 0x29, 0xbf, 0xe3, 0x79, 0x25, 0x63, 0x7d, 0x3d, 0xf1, ++ 0x7e, 0x45, 0x3a, 0xc1, 0xd8, 0x76, 0x51, 0xdf, 0x57, 0xe3, 0xbc, 0xaf, ++ 0x82, 0xe5, 0xff, 0x01, 0x04, 0x0e, 0xb3, 0xf0, 0x60, 0x17, 0x00, 0x00, ++ 0x00 }; + + static const u32 bnx2_TPAT_b06FwData[(0x0/4) + 1] = { 0x0 }; + static const u32 bnx2_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x0 }; + + static struct fw_info bnx2_tpat_fw_06 = { +- /* Firmware version: 4.0.5 */ +- .ver_major = 0x4, +- .ver_minor = 0x0, +- .ver_fix = 0x5, +- +- .start_addr = 0x08000888, +- +- .text_addr = 0x08000800, +- .text_len = 0x1a90, ++ /* Firmware version: 5.0.0j */ ++ .ver_major = 0x5, ++ .ver_minor = 0x0, ++ .ver_fix = 0x0, ++ ++ .start_addr = 0x08000488, ++ ++ .text_addr = 0x08000400, ++ .text_len = 0x175c, + .text_index = 0x0, + .gz_text = bnx2_TPAT_b06FwText, + .gz_text_len = sizeof(bnx2_TPAT_b06FwText), +@@ -3686,11 +3581,11 @@ + .data_index = 0x0, + .data = bnx2_TPAT_b06FwData, + +- .sbss_addr = 0x080022c0, ++ .sbss_addr = 0x08001b80, + .sbss_len = 0x44, + .sbss_index = 0x0, + +- .bss_addr = 0x08002304, ++ .bss_addr = 0x08001bc4, + .bss_len = 0x450, + .bss_index = 0x0, + +@@ -3717,862 +3612,876 @@ + }; + + static u8 bnx2_TXP_b06FwText[] = { +- 0xad, 0x7b, 0x7f, 0x70, 0x9b, 0x75, 0x7a, 0xe7, 0xe7, 0xd5, 0x0f, 0x5b, +- 0xb2, 0x65, 0x59, 0x0e, 0x4a, 0x90, 0x77, 0xbd, 0x8d, 0x5e, 0xf4, 0xca, +- 0x16, 0xd8, 0x49, 0x5e, 0x25, 0xce, 0xc6, 0x59, 0xab, 0x44, 0x75, 0x1c, +- 0xdb, 0x71, 0x1c, 0x30, 0xc1, 0xdd, 0x3a, 0x3d, 0xae, 0xf1, 0x25, 0x26, +- 0x31, 0x10, 0xc0, 0xe9, 0xa6, 0x7b, 0x62, 0x8f, 0xd6, 0xc2, 0x76, 0x82, +- 0x43, 0x64, 0xbf, 0xce, 0x2a, 0x59, 0x87, 0x4e, 0x67, 0xd6, 0x60, 0x07, +- 0x07, 0x56, 0x8e, 0x60, 0xdb, 0x6b, 0xbb, 0x73, 0xbb, 0x83, 0x8e, 0x40, +- 0xf0, 0x72, 0x01, 0xb6, 0xfd, 0xa3, 0x47, 0x6f, 0xee, 0xda, 0xcc, 0x02, +- 0x59, 0xa0, 0x4b, 0xa0, 0x3b, 0x7b, 0x53, 0x67, 0x0b, 0xbc, 0xf7, 0x79, +- 0xde, 0x57, 0x4a, 0xb2, 0x94, 0x4e, 0x67, 0x3a, 0xe7, 0x19, 0x8f, 0xac, +- 0xf7, 0xc7, 0xf3, 0x7d, 0x7e, 0x3f, 0x9f, 0xe7, 0xf9, 0x7e, 0x5d, 0x0f, +- 0x54, 0xa0, 0xf8, 0x53, 0xc5, 0xdf, 0xe6, 0xe1, 0xd4, 0xe1, 0x8d, 0x6b, +- 0xf5, 0xb5, 0xd6, 0x05, 0x37, 0x5c, 0x72, 0xf3, 0xab, 0x0a, 0x30, 0xf0, +- 0x01, 0xfe, 0x5d, 0x3f, 0x5f, 0xf9, 0xf7, 0xbd, 0x66, 0xfd, 0x38, 0x81, +- 0x40, 0x89, 0x2f, 0xf9, 0x85, 0xc7, 0x91, 0x40, 0x6b, 0x9b, 0x06, 0x8f, +- 0x33, 0xf1, 0x67, 0x89, 0x7d, 0x1a, 0x90, 0xcc, 0x35, 0x86, 0xb7, 0xe2, +- 0x53, 0x33, 0x1d, 0x74, 0x41, 0xae, 0x7f, 0x25, 0xf1, 0xc9, 0xc8, 0x8f, +- 0x36, 0xa9, 0x1f, 0xcf, 0x3a, 0xe1, 0x09, 0x24, 0x4e, 0x23, 0x50, 0x0f, +- 0x4f, 0x1d, 0xdf, 0xf9, 0x93, 0x86, 0x6a, 0x27, 0xfc, 0x25, 0x5a, 0x2d, +- 0x18, 0x33, 0x90, 0xf6, 0x24, 0x86, 0x51, 0xbe, 0x11, 0x78, 0x37, 0x13, +- 0xd5, 0xc7, 0x80, 0x69, 0x47, 0x22, 0x1a, 0x7e, 0x09, 0x3a, 0x8e, 0xe4, +- 0xc3, 0x68, 0xe7, 0xef, 0x76, 0xe3, 0x33, 0x33, 0xec, 0x46, 0xda, 0xc9, +- 0xe7, 0xf6, 0x36, 0x03, 0xdb, 0x32, 0x3a, 0x8e, 0x1a, 0xf0, 0xd4, 0x26, +- 0x1e, 0xc5, 0x66, 0x7e, 0xfa, 0x13, 0x29, 0xbc, 0x31, 0x19, 0x09, 0x3f, +- 0x03, 0xb5, 0x5f, 0x73, 0xaa, 0x29, 0xa0, 0x71, 0x68, 0x50, 0x51, 0x07, +- 0xde, 0x54, 0xd4, 0xde, 0x49, 0x05, 0x1e, 0x85, 0xcf, 0x35, 0xe6, 0xe4, +- 0x33, 0x85, 0xdb, 0x72, 0x1e, 0x5c, 0x72, 0xca, 0xfa, 0xbf, 0x49, 0x7d, +- 0x2b, 0x70, 0x69, 0x2d, 0x18, 0x27, 0x0f, 0xee, 0x84, 0x82, 0xa7, 0x9b, +- 0xa3, 0xa1, 0x51, 0xc8, 0xfd, 0x30, 0xb6, 0xe6, 0xe5, 0x53, 0xa5, 0xd4, +- 0xa6, 0x39, 0xae, 0x9b, 0xe6, 0x19, 0xbd, 0x1c, 0xe9, 0x80, 0x1a, 0x02, +- 0x14, 0x8c, 0xea, 0x0e, 0x24, 0x03, 0x6d, 0x61, 0x17, 0xd4, 0xd0, 0xbd, +- 0xf8, 0x67, 0xca, 0x9c, 0x8c, 0xb9, 0x61, 0x3f, 0x3f, 0x80, 0x72, 0x14, +- 0x02, 0xb6, 0xd6, 0x9e, 0xce, 0x98, 0xe6, 0x05, 0xcd, 0x85, 0x33, 0xd4, +- 0xcf, 0x68, 0xee, 0x9f, 0xcd, 0x02, 0x75, 0x33, 0xae, 0x95, 0xd6, 0xf7, +- 0x60, 0x36, 0x60, 0x9a, 0x73, 0xbc, 0x77, 0x34, 0x57, 0xd2, 0xb3, 0x69, +- 0x3a, 0x34, 0xd3, 0xdc, 0xa7, 0xfd, 0xca, 0xdc, 0xfb, 0x6b, 0xcf, 0x9a, +- 0xe6, 0x13, 0xfa, 0x4d, 0x38, 0x9b, 0x6d, 0x57, 0xba, 0x17, 0x56, 0xf9, +- 0xb7, 0xcf, 0x98, 0xb8, 0xa0, 0x23, 0xe0, 0x48, 0x74, 0x28, 0xdb, 0x17, +- 0xba, 0x94, 0x6d, 0xf9, 0x5d, 0x4a, 0xc7, 0xdc, 0xef, 0x2a, 0x5d, 0x0b, +- 0x03, 0x4a, 0x67, 0x3e, 0x84, 0x79, 0x23, 0x88, 0x39, 0xa3, 0x5f, 0x69, +- 0x5f, 0xe8, 0x53, 0x6c, 0x39, 0x52, 0x4a, 0x5b, 0xbe, 0x44, 0xeb, 0xba, +- 0x1e, 0xb7, 0x67, 0x12, 0x98, 0x30, 0xca, 0xb9, 0xce, 0xb2, 0xf9, 0xa3, +- 0x86, 0x65, 0xca, 0xa9, 0xe3, 0x58, 0xfe, 0x09, 0xec, 0x9c, 0x31, 0xcd, +- 0x5c, 0x1c, 0xc8, 0xe5, 0x81, 0xef, 0x19, 0x91, 0xde, 0x21, 0xc5, 0x34, +- 0x3b, 0xa3, 0xe6, 0xea, 0xcb, 0x7a, 0x63, 0xec, 0x65, 0xfc, 0x93, 0x39, +- 0x1b, 0x44, 0xda, 0x47, 0x1a, 0xc7, 0x69, 0xb3, 0xfb, 0x27, 0xe1, 0x29, +- 0x4f, 0x8c, 0xe3, 0x67, 0x19, 0x78, 0xca, 0x12, 0x69, 0x5c, 0xc8, 0x8c, +- 0x06, 0x3c, 0x88, 0x84, 0xb6, 0x2b, 0xe9, 0x94, 0x03, 0xea, 0xf0, 0xdb, +- 0x50, 0xc3, 0xb4, 0xc7, 0xd2, 0x79, 0x45, 0x2d, 0xbc, 0x0c, 0x35, 0xf9, +- 0x2b, 0x45, 0xed, 0xaa, 0x75, 0x22, 0xe9, 0x88, 0x7a, 0xf0, 0xa3, 0x06, +- 0xb1, 0xc9, 0x38, 0xd6, 0x5a, 0xb6, 0x49, 0xe3, 0xd6, 0x6b, 0xb6, 0x49, +- 0x60, 0x94, 0x7c, 0x1d, 0x25, 0x5f, 0xaf, 0xe8, 0x6a, 0xe8, 0x69, 0x98, +- 0xab, 0x07, 0x75, 0xb9, 0x97, 0xc0, 0x78, 0xde, 0x0c, 0xfb, 0x13, 0x97, +- 0xc8, 0x2f, 0xd2, 0x5f, 0x4a, 0x78, 0xd2, 0xd5, 0x89, 0x4f, 0xcd, 0xd7, +- 0x37, 0x86, 0xf0, 0x62, 0x3e, 0x88, 0x17, 0xf2, 0x01, 0x3c, 0x9f, 0x6f, +- 0x87, 0x91, 0x87, 0x7f, 0x67, 0xfe, 0x8b, 0xfc, 0xd8, 0x84, 0x8f, 0xcf, +- 0x93, 0x6f, 0xff, 0x8e, 0xbc, 0x6b, 0xa0, 0x2c, 0x81, 0xde, 0x1f, 0x67, +- 0x46, 0xcc, 0x0a, 0x0d, 0x03, 0x35, 0x09, 0x2d, 0x79, 0x9b, 0xe2, 0x6b, +- 0xa1, 0x1f, 0xf6, 0xbe, 0x9a, 0x6b, 0x71, 0x69, 0x53, 0x5e, 0xb8, 0xa9, +- 0xff, 0x6d, 0x79, 0xd3, 0x1c, 0xd3, 0x0f, 0xad, 0xdb, 0xdb, 0xf2, 0xa7, +- 0x85, 0x5e, 0xad, 0x07, 0xe9, 0xfc, 0x20, 0xe0, 0x4f, 0xf0, 0x93, 0xa1, +- 0xb8, 0xab, 0xa9, 0x3d, 0x7c, 0xee, 0x41, 0x97, 0xed, 0xcf, 0xe4, 0x81, +- 0x7a, 0x7f, 0xc1, 0x20, 0x0f, 0xc6, 0xb4, 0x1f, 0x15, 0x61, 0xca, 0xf7, +- 0x13, 0xf2, 0x19, 0xc3, 0xf7, 0xf3, 0x1a, 0x79, 0x6b, 0x22, 0x8f, 0x61, +- 0xf2, 0xe7, 0xc1, 0xde, 0xac, 0x3a, 0x9d, 0x86, 0x3a, 0x31, 0x8b, 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0xbf, 0xaf, 0xcf, 0xdf, 0x78, 0x5e, +- 0x39, 0xc0, 0xbc, 0xde, 0xd8, 0x1b, 0x52, 0x5e, 0x35, 0x93, 0xbf, 0xad, +- 0x50, 0xce, 0x07, 0xab, 0x50, 0x61, 0xc9, 0x8a, 0xd1, 0x6c, 0xa9, 0xa6, +- 0x54, 0x4b, 0x2f, 0xd7, 0x9b, 0x2e, 0xfa, 0x60, 0x25, 0x63, 0xfd, 0x18, +- 0x6b, 0x74, 0xf9, 0x09, 0xa9, 0x25, 0xec, 0x5f, 0x94, 0x2d, 0xc4, 0xc2, +- 0x82, 0x1b, 0x3c, 0x78, 0x20, 0xa0, 0xb6, 0xc8, 0x99, 0xed, 0x67, 0xf3, +- 0x1d, 0x2e, 0x39, 0x3b, 0xf5, 0x5c, 0x5e, 0x6a, 0xb9, 0xe4, 0x82, 0xd2, +- 0x7a, 0x21, 0xd4, 0x4e, 0x8a, 0x8d, 0x86, 0x5b, 0x3f, 0x9a, 0xf4, 0xc9, +- 0xf9, 0xfa, 0x11, 0x07, 0x7b, 0x6d, 0xcf, 0xa4, 0x69, 0xee, 0x69, 0xd6, +- 0x86, 0xb6, 0x38, 0x65, 0x6f, 0x39, 0x32, 0x70, 0x4e, 0x51, 0x5b, 0x26, +- 0x94, 0x1b, 0xe9, 0xfc, 0xb7, 0x2a, 0x89, 0x91, 0x34, 0xe5, 0x7c, 0xdc, +- 0x92, 0x69, 0x8a, 0x32, 0x95, 0xce, 0x16, 0x55, 0xe1, 0xf2, 0x34, 0x34, +- 0x46, 0x2d, 0xce, 0xeb, 0x4c, 0x4e, 0x81, 0x68, 0xb2, 0x1d, 0xe2, 0xff, +- 0xea, 0x80, 0x60, 0xa8, 0x4a, 0xe6, 0xe4, 0xb9, 0x69, 0xa9, 0x31, 0x8a, +- 0xe0, 0x93, 0x34, 0xd7, 0xc6, 0x95, 0x8d, 0xc0, 0xab, 0x93, 0xf6, 0xde, +- 0x7b, 0xf1, 0x2c, 0xb8, 0x75, 0xe6, 0xe1, 0x11, 0xeb, 0x2c, 0x83, 0xd0, +- 0x3f, 0x8c, 0x33, 0x19, 0xc1, 0x94, 0xc3, 0xc4, 0x94, 0x91, 0x14, 0xf1, +- 0x66, 0x4b, 0xde, 0x3e, 0x97, 0xa5, 0x7f, 0x44, 0x9f, 0x7f, 0x9a, 0x58, +- 0xf5, 0x28, 0xec, 0xbd, 0xf7, 0x86, 0xe2, 0x59, 0x85, 0x48, 0xae, 0x4b, +- 0xd9, 0x91, 0x97, 0x18, 0x9b, 0x66, 0x8c, 0xb5, 0x2b, 0xdb, 0x17, 0x3a, +- 0x94, 0xee, 0x85, 0x1e, 0x65, 0x77, 0x5e, 0x7a, 0xd6, 0xc9, 0xd6, 0x07, +- 0x4e, 0xec, 0x52, 0x76, 0xcc, 0xf5, 0x29, 0xc4, 0xb4, 0x01, 0x4f, 0xa2, +- 0x5f, 0xe9, 0x59, 0xb0, 0xe7, 0xe7, 0x5d, 0xec, 0xbb, 0x76, 0x18, 0xa5, +- 0x7e, 0x5e, 0xfe, 0xdf, 0x2b, 0x28, 0xff, 0x5b, 0x31, 0xb0, 0x4d, 0x31, +- 0xcd, 0xdb, 0xe2, 0x7f, 0x27, 0xf6, 0x30, 0x9f, 0x8d, 0xb3, 0x36, 0x1a, +- 0x55, 0x18, 0x64, 0xdf, 0x31, 0xaa, 0xdf, 0x5a, 0xdc, 0x2f, 0x13, 0x99, +- 0xe4, 0x3c, 0x85, 0xf8, 0x2b, 0xd2, 0xe5, 0xe4, 0xe1, 0x1f, 0xc8, 0xff, +- 0x81, 0xa2, 0x5c, 0x3d, 0x72, 0xa6, 0xc0, 0x7d, 0xfd, 0xbc, 0xd9, 0xf1, +- 0xc9, 0xeb, 0x72, 0x31, 0xd7, 0x63, 0x9c, 0xf8, 0xf4, 0x80, 0xa2, 0xa6, +- 0x9e, 0xb1, 0xe5, 0x5a, 0xba, 0xcc, 0x18, 0x1e, 0xb5, 0x62, 0xd8, 0x96, +- 0x6b, 0x5d, 0x51, 0xae, 0xb5, 0xb9, 0x2e, 0xeb, 0x1c, 0x17, 0xf1, 0x7a, +- 0xeb, 0xe2, 0xa4, 0x9c, 0x37, 0x93, 0xd9, 0xa5, 0xc8, 0x26, 0x72, 0x9c, +- 0x30, 0x2b, 0xb4, 0x1e, 0x65, 0xa7, 0x75, 0xfe, 0x4c, 0xce, 0x7e, 0xc9, +- 0x5e, 0x7f, 0x49, 0x2e, 0xa9, 0xe3, 0x2b, 0xfc, 0x1d, 0x33, 0x72, 0x1e, +- 0xdb, 0x34, 0x5f, 0xd3, 0x83, 0x7e, 0x91, 0xe5, 0xac, 0x2e, 0xb2, 0xc8, +- 0xb9, 0x92, 0x92, 0x3c, 0x5f, 0x2b, 0xca, 0x23, 0xb6, 0xba, 0x6e, 0xa7, +- 0xd2, 0xff, 0x09, 0xbe, 0x9d, 0xb1, 0xcf, 0x9c, 0x94, 0xe4, 0xf1, 0x27, +- 0x84, 0xff, 0x8b, 0xad, 0xe3, 0xd3, 0xc3, 0x78, 0x95, 0xf7, 0x7f, 0x9e, +- 0x29, 0xc9, 0xe5, 0xc4, 0xfc, 0x5c, 0xe9, 0x2c, 0x1d, 0x5b, 0x4a, 0x23, +- 0xa2, 0x8f, 0xd1, 0x8f, 0x6c, 0xf9, 0xe4, 0x2c, 0x5d, 0x63, 0xe1, 0xb2, +- 0x35, 0xf7, 0x8a, 0x26, 0xd9, 0x2f, 0xe3, 0x6c, 0xfe, 0xd7, 0xed, 0xd7, +- 0x94, 0xab, 0x60, 0x8f, 0x2c, 0xb4, 0x5f, 0x27, 0x6d, 0x39, 0x73, 0xa2, +- 0xe0, 0x99, 0x39, 0x60, 0xce, 0xe0, 0xb2, 0x89, 0x11, 0x3c, 0xa9, 0x9b, +- 0xe6, 0xd3, 0xcd, 0x9a, 0x9c, 0x15, 0xba, 0x50, 0x6b, 0xcd, 0x85, 0xa0, +- 0x57, 0x69, 0xb2, 0x77, 0x27, 0xe7, 0x4d, 0xfa, 0xa8, 0x03, 0x91, 0x5d, +- 0x7c, 0xa0, 0x64, 0x7b, 0x39, 0x07, 0x97, 0xa6, 0x7e, 0x44, 0x37, 0xa5, +- 0xf3, 0x70, 0x32, 0x73, 0xb9, 0x51, 0x27, 0x5d, 0x96, 0x4e, 0x9e, 0xd5, +- 0xc5, 0x5f, 0x99, 0x7d, 0xe8, 0xab, 0xf3, 0xc4, 0x0f, 0x63, 0xba, 0xdb, +- 0xc2, 0x6a, 0x47, 0x89, 0x4f, 0x26, 0x18, 0x3b, 0x8f, 0x1b, 0x4b, 0x58, +- 0xca, 0xbd, 0x8c, 0x57, 0xaf, 0xfd, 0xcf, 0x9c, 0xf8, 0x8b, 0xde, 0xd2, +- 0x6d, 0x9d, 0x79, 0xfa, 0xa4, 0xe5, 0xd6, 0xa8, 0xe4, 0xa1, 0x1f, 0x36, +- 0xc9, 0x19, 0xa8, 0xf2, 0x44, 0xe0, 0x6b, 0xb2, 0xbf, 0x55, 0x96, 0x98, +- 0xfd, 0xea, 0x05, 0x4d, 0x74, 0xa3, 0x35, 0x9f, 0xd1, 0x44, 0xae, 0x1e, +- 0x7d, 0xdc, 0xfa, 0x1f, 0xce, 0x96, 0x4d, 0xfb, 0x34, 0x89, 0x1d, 0xdf, +- 0xc6, 0x36, 0x2b, 0x27, 0x9c, 0x4e, 0xdc, 0x66, 0xe9, 0xe0, 0x64, 0xe2, +- 0x56, 0xeb, 0x73, 0x3a, 0x11, 0xb3, 0x3e, 0xff, 0x24, 0x61, 0xeb, 0x26, +- 0x97, 0xa8, 0xb7, 0x3e, 0xe7, 0x13, 0xf6, 0xd9, 0xe9, 0xd9, 0x84, 0x66, +- 0x7d, 0x3e, 0x9f, 0x88, 0x58, 0x9f, 0x67, 0x13, 0xb7, 0x5c, 0xe7, 0x8b, +- 0x3f, 0xff, 0x0f, 0x4c, 0xd3, 0x85, 0x76, 0xdc, 0x3a, 0x00, 0x00, 0x00 }; ++ 0x9d, 0x7b, 0x0d, 0x70, 0x5c, 0xd5, 0x95, 0xe6, 0x77, 0xbb, 0x5b, 0x52, ++ 0xb7, 0x2c, 0xb5, 0x5a, 0xa6, 0x6d, 0x5a, 0x33, 0xce, 0xb8, 0x1f, 0xfd, ++ 0x9e, 0xd4, 0x20, 0xd9, 0xbc, 0x96, 0x65, 0x2c, 0x26, 0x2f, 0xb8, 0x23, ++ 0xcb, 0xb6, 0xfc, 0x07, 0xb2, 0x51, 0x32, 0xf2, 0x2c, 0xbb, 0x68, 0x6c, ++ 0x81, 0x05, 0x36, 0x46, 0x04, 0x6d, 0x56, 0x64, 0x33, 0xa3, 0x46, 0x92, ++ 0x8d, 0xc1, 0x2d, 0x3d, 0x09, 0x99, 0xc8, 0xa4, 0xa6, 0x26, 0xc2, 0x92, ++ 0x91, 0x21, 0x2d, 0x35, 0x04, 0x92, 0x22, 0x5b, 0x64, 0xd2, 0x0b, 0xc6, ++ 0x28, 0x8c, 0xf9, 0x09, 0x93, 0x9a, 0x62, 0xb6, 0x66, 0x2b, 0x2e, 0x7e, ++ 0x8c, 0x61, 0x13, 0x48, 0xa6, 0x66, 0x77, 0x4d, 0x02, 0x7e, 0xfb, 0x9d, ++ 0xd7, 0xdd, 0xb6, 0xa1, 0x32, 0x53, 0x5b, 0xa3, 0xaa, 0xae, 0xd7, 0xfd, ++ 0x7e, 0xce, 0xbd, 0xf7, 0xfc, 0x7c, 0xe7, 0x3b, 0xe7, 0x5d, 0x5d, 0x03, ++ 0x94, 0xa3, 0xf0, 0x57, 0xc9, 0xcf, 0xea, 0xde, 0xfe, 0x3e, 0x73, 0xa5, ++ 0xb9, 0x92, 0x5f, 0xef, 0xe4, 0xa7, 0x44, 0x2e, 0x5e, 0xa7, 0x80, 0xae, ++ 0x0f, 0xf1, 0xef, 0xfa, 0x5b, 0xfa, 0xef, 0x7b, 0x0c, 0x87, 0xae, 0xc8, ++ 0x1f, 0xff, 0xa9, 0xe4, 0xd2, 0x39, 0x2f, 0x10, 0x2a, 0xce, 0x53, 0x3e, ++ 0xf0, 0x7b, 0xac, 0xae, 0x2f, 0xb7, 0xe8, 0xf0, 0x7b, 0xad, 0xf0, 0x57, ++ 0x76, 0xeb, 0x40, 0x32, 0x53, 0x1f, 0x5d, 0x87, 0xcf, 0x9c, 0x54, 0xd8, ++ 0x07, 0x39, 0xff, 0x25, 0xeb, 0xd3, 0x81, 0x9f, 0xac, 0xd1, 0x7e, 0x33, ++ 0xe5, 0x85, 0x3f, 0x64, 0x9d, 0x40, 0xa8, 0x16, 0xfe, 0x65, 0x7c, 0xe6, ++ 0xaf, 0xeb, 0xfe, 0x9b, 0x07, 0xc1, 0xa2, 0xac, 0x66, 0x0c, 0xd9, 0x48, ++ 0xf9, 0xad, 0x5e, 0x94, 0xad, 0x06, 0xde, 0x4b, 0x1b, 0xe6, 0x10, 0x30, ++ 0xe6, 0xb1, 0x8c, 0xe8, 0x0b, 0x30, 0x71, 0x20, 0x1b, 0x45, 0x2b, 0x3f, ++ 0x9b, 0xec, 0x0b, 0x4e, 0xb4, 0x04, 0x29, 0x2f, 0xef, 0xdb, 0xd5, 0x04, ++ 0xac, 0x4f, 0x9b, 0x38, 0x68, 0xc3, 0x5f, 0x63, 0x7d, 0x1b, 0xd7, 0xf3, ++ 0x18, 0xb4, 0xfa, 0xf1, 0xda, 0x48, 0x2c, 0xfa, 0x38, 0xb4, 0x4e, 0xdd, ++ 0xab, 0xf5, 0x03, 0xf5, 0x3d, 0xdd, 0x4a, 0xeb, 0x7a, 0x5d, 0x69, 0xed, ++ 0x23, 0x0a, 0x7e, 0xc5, 0xfb, 0xea, 0x33, 0x72, 0xec, 0xc7, 0x35, 0x19, ++ 0x3f, 0xce, 0x78, 0x65, 0xfc, 0xaf, 0x52, 0xff, 0x0a, 0x3e, 0xbd, 0x19, ++ 0xc3, 0x9c, 0x43, 0x89, 0xa5, 0x70, 0xac, 0xc9, 0x88, 0x0c, 0x42, 0xae, ++ 0x47, 0xb1, 0x2e, 0x2b, 0x47, 0x8d, 0xab, 0x76, 0x9c, 0x61, 0xd3, 0x71, ++ 0x8e, 0x9b, 0x65, 0x48, 0x85, 0xb4, 0x08, 0xa0, 0x30, 0x68, 0x7a, 0x90, ++ 0x0c, 0xb5, 0x44, 0x7d, 0xd0, 0x22, 0xb7, 0xe1, 0xf7, 0x5c, 0x73, 0x32, ++ 0x5e, 0x82, 0xfc, 0xfd, 0x5d, 0x28, 0x43, 0x2e, 0x94, 0xd7, 0xda, 0xb1, ++ 0xb4, 0xe3, 0x9c, 0xd2, 0x7d, 0x38, 0x4e, 0xfd, 0x0c, 0x66, 0x7e, 0xef, ++ 0xe4, 0xa8, 0x9b, 0x61, 0xbd, 0x38, 0xbe, 0x1f, 0x53, 0x21, 0xc7, 0x99, ++ 0xe6, 0xb5, 0x83, 0x99, 0xa2, 0x9e, 0x1d, 0xc7, 0xa3, 0x3b, 0xce, 0x6e, ++ 0xfd, 0x77, 0xce, 0xae, 0xcf, 0xdd, 0xeb, 0x38, 0x0f, 0x99, 0x57, 0xe0, ++ 0xc4, 0x44, 0xab, 0xda, 0x3c, 0xbb, 0x34, 0xb8, 0x69, 0xd2, 0xc1, 0x29, ++ 0x13, 0x21, 0x8f, 0xb5, 0x41, 0x6d, 0x9a, 0x6d, 0x53, 0xeb, 0xb3, 0x3b, ++ 0xd4, 0x86, 0xe9, 0x3f, 0x57, 0x6d, 0xb3, 0x5d, 0x6a, 0x63, 0x36, 0x82, ++ 0x19, 0x3b, 0x8c, 0x69, 0xbb, 0x53, 0xb5, 0xce, 0x76, 0xa8, 0xfc, 0x3a, ++ 0xfa, 0x55, 0x4b, 0xb6, 0x28, 0xeb, 0x92, 0x1e, 0x37, 0xa5, 0x69, 0x6d, ++ 0xbb, 0x8c, 0xe3, 0x9c, 0x77, 0x7e, 0x52, 0x77, 0x9e, 0xeb, 0x34, 0xf1, ++ 0x60, 0xf6, 0x21, 0x6c, 0x9b, 0x74, 0x9c, 0x4c, 0x02, 0xc8, 0x64, 0x81, ++ 0xef, 0xdb, 0xb1, 0xf6, 0x1e, 0xe5, 0x38, 0x1b, 0x0d, 0x67, 0xf9, 0x59, ++ 0xb3, 0x3e, 0x7e, 0x12, 0xff, 0xd7, 0x99, 0x0a, 0x23, 0x55, 0x41, 0x19, ++ 0x87, 0x69, 0xb3, 0x3b, 0x47, 0xe0, 0x2f, 0xb3, 0x86, 0xf1, 0x7e, 0x1a, ++ 0xfe, 0x52, 0x2b, 0x85, 0x53, 0xe9, 0xc1, 0x90, 0x1f, 0xb1, 0xc8, 0x26, ++ 0x95, 0xea, 0xf7, 0x40, 0xeb, 0x7d, 0x07, 0x5a, 0x94, 0xf6, 0x58, 0x78, ++ 0x51, 0x69, 0xb9, 0x93, 0xd0, 0x92, 0xbf, 0x53, 0x5a, 0x5b, 0x8d, 0x17, ++ 0x49, 0x8f, 0xe1, 0xc7, 0x4f, 0xea, 0xc4, 0x26, 0xc3, 0x58, 0xe9, 0xda, ++ 0x26, 0x85, 0xab, 0x2f, 0xda, 0x86, 0xfa, 0xe2, 0xbc, 0x0e, 0x72, 0x5e, ++ 0x2f, 0x99, 0x5a, 0xe4, 0x18, 0x9c, 0xe5, 0xdd, 0x66, 0xfe, 0xda, 0x70, ++ 0xb6, 0x19, 0x0f, 0xd8, 0x49, 0x3c, 0x64, 0x3f, 0xc7, 0x39, 0xb7, 0xd2, ++ 0x0f, 0x92, 0xf8, 0x51, 0xb6, 0x15, 0x3f, 0xcd, 0x5a, 0xf8, 0x21, 0xaf, ++ 0x3d, 0x9b, 0x6d, 0xc2, 0x33, 0x59, 0x13, 0x3f, 0xc8, 0x36, 0xe0, 0xe9, ++ 0x6c, 0x1c, 0x4f, 0x65, 0x7d, 0x6a, 0xbd, 0x9d, 0xc1, 0xa6, 0x91, 0x14, ++ 0x36, 0xd2, 0x97, 0x16, 0xd2, 0xb1, 0xe6, 0x27, 0xa0, 0x3d, 0x45, 0x87, ++ 0x0e, 0xb6, 0x65, 0x43, 0xc1, 0x56, 0x5b, 0x6b, 0x03, 0xc2, 0xc1, 0xd6, ++ 0xac, 0x8e, 0x17, 0xd2, 0x91, 0x60, 0x4b, 0x36, 0x12, 0x5c, 0x67, 0x2f, ++ 0x0b, 0xae, 0xcb, 0x1a, 0xea, 0x4c, 0x48, 0x21, 0xb6, 0xc2, 0x8f, 0xbd, ++ 0x13, 0xbf, 0x40, 0x57, 0xb5, 0xcc, 0x2a, 0x84, 0xfd, 0xd4, 0xcd, 0xab, ++ 0x89, 0xfa, 0xae, 0x5f, 0xe3, 0x75, 0xa4, 0x96, 0xe4, 0xcf, 0xf5, 0xf2, ++ 0x5c, 0x55, 0x23, 0x82, 0x37, 0x51, 0x5f, 0x3b, 0x6c, 0x3f, 0xb6, 0x37, ++ 0x7e, 0xe6, 0x44, 0x17, 0xbb, 0x36, 0x0e, 0x76, 0x4c, 0xfa, 0x82, 0x1b, ++ 0x6c, 0xc7, 0x39, 0xd0, 0xa8, 0xf0, 0x8c, 0xd9, 0xa8, 0xba, 0x16, 0x17, ++ 0x7d, 0x3f, 0x39, 0xf5, 0x9c, 0x99, 0xc4, 0x12, 0x3d, 0x87, 0x25, 0x57, ++ 0x60, 0xea, 0x09, 0x73, 0x85, 0x8a, 0x56, 0xe7, 0xfd, 0x62, 0x60, 0x82, ++ 0x6b, 0xbd, 0x22, 0x2f, 0x7b, 0x37, 0x65, 0xef, 0x35, 0xeb, 0x93, 0x7f, ++ 0x27, 0x31, 0x58, 0x9d, 0x44, 0xc6, 0x8c, 0xa9, 0x94, 0x7b, 0x9f, 0x85, ++ 0x03, 0xb3, 0x4d, 0x38, 0x48, 0xbb, 0xde, 0x3e, 0xa1, 0xc5, 0xcf, 0x20, ++ 0x8a, 0xd9, 0xac, 0xae, 0x72, 0xe1, 0x28, 0x9e, 0xa9, 0xab, 0x40, 0x17, ++ 0xf5, 0x31, 0x38, 0x89, 0xe4, 0x46, 0xfa, 0xea, 0x99, 0xf0, 0x52, 0x78, ++ 0xf5, 0x20, 0x3f, 0x65, 0xc9, 0x1a, 0xbd, 0x1c, 0xbb, 0xa7, 0xc3, 0xb8, ++ 0x2f, 0x7b, 0x03, 0x1e, 0x9a, 0x08, 0xa3, 0x8f, 0x7a, 0xee, 0x4c, 0x24, ++ 0x9f, 0x8c, 0xc0, 0x18, 0x7b, 0xc4, 0x13, 0xc6, 0x37, 0xf8, 0xdc, 0xf0, ++ 0x64, 0x18, 0xbd, 0x76, 0x08, 0xe3, 0xa6, 0xd1, 0x5f, 0xcd, 0x73, 0x77, ++ 0xf3, 0xdc, 0xe8, 0xa4, 0x1f, 0xaf, 0x26, 0x36, 0xaa, 0xa9, 0x6a, 0x2d, ++ 0x4e, 0x7d, 0x61, 0x8f, 0x2d, 0xfe, 0x87, 0xfb, 0x2b, 0x2c, 0x23, 0xfe, ++ 0x36, 0x7f, 0xdf, 0x96, 0x2d, 0x0f, 0x6e, 0x98, 0x0c, 0xc2, 0xaf, 0x7f, ++ 0xea, 0x94, 0x34, 0x39, 0xce, 0x8b, 0xa6, 0xd1, 0xb9, 0x0f, 0x3e, 0xec, ++ 0xcd, 0x7a, 0xd0, 0x33, 0x5d, 0xce, 0x35, 0xf9, 0xf0, 0x41, 0x5d, 0x39, ++ 0xee, 0x98, 0xb6, 0x70, 0x70, 0x92, 0x73, 0x98, 0xc0, 0xf2, 0xd3, 0xe6, ++ 0xd0, 0xce, 0x0a, 0xfa, 0xc4, 0x6e, 0x15, 0xc7, 0x72, 0x23, 0x80, 0x81, ++ 0xe9, 0x0a, 0xfa, 0x76, 0x08, 0x77, 0xcc, 0x06, 0x70, 0xdf, 0x84, 0x07, ++ 0xd7, 0xd4, 0xc9, 0xdc, 0x62, 0x27, 0x22, 0x8c, 0xa9, 0xa7, 0x1b, 0x17, ++ 0xe1, 0x9e, 0xe9, 0x00, 0xfa, 0x26, 0x42, 0xe8, 0x9e, 0x6c, 0xc2, 0xb8, ++ 0x6d, 0xc1, 0x66, 0x1c, 0x3c, 0xdc, 0xa8, 0xa5, 0x5a, 0x3d, 0x5a, 0x6f, ++ 0x89, 0x27, 0x89, 0x5f, 0x27, 0x4a, 0x30, 0x55, 0xed, 0x38, 0x27, 0x13, ++ 0xf5, 0xf1, 0x71, 0xfa, 0xf9, 0x62, 0x2b, 0xcc, 0x18, 0xd3, 0xa6, 0xe8, ++ 0x7f, 0xcd, 0xba, 0xe7, 0x8f, 0xd5, 0x19, 0xea, 0xe6, 0xb8, 0x1d, 0x0e, ++ 0x6e, 0xb3, 0x43, 0xc1, 0x6d, 0xd9, 0x65, 0xc1, 0x16, 0x5b, 0xec, 0x0d, ++ 0xda, 0x1e, 0xb8, 0x89, 0x76, 0xfb, 0x28, 0xf1, 0x99, 0x93, 0xab, 0x2e, ++ 0xda, 0x4d, 0x3b, 0x94, 0x82, 0x36, 0x26, 0x7a, 0x3e, 0x32, 0xeb, 0x0b, ++ 0xb6, 0xdb, 0x0a, 0x61, 0xbd, 0x09, 0x63, 0x59, 0x19, 0xdf, 0x71, 0x1e, ++ 0x31, 0x81, 0x9e, 0xd1, 0xd8, 0xf9, 0x6a, 0x15, 0xc0, 0x99, 0x2b, 0x81, ++ 0x81, 0x79, 0xea, 0xc0, 0x6e, 0xc5, 0x61, 0xfa, 0xe3, 0xe3, 0x4d, 0x61, ++ 0xdc, 0x4e, 0xdf, 0xda, 0x6a, 0x47, 0xb1, 0x6f, 0x4e, 0xfc, 0x49, 0xc7, ++ 0xee, 0x39, 0x3f, 0xf6, 0x4c, 0xbc, 0x49, 0x5b, 0x88, 0xfc, 0xbf, 0x01, ++ 0x82, 0x21, 0x62, 0x4f, 0x1b, 0x1e, 0xb4, 0xd1, 0xe8, 0xb7, 0xb4, 0x78, ++ 0x12, 0x0e, 0x6a, 0x13, 0xf8, 0xb4, 0x14, 0x46, 0xfb, 0x39, 0xaf, 0xc2, ++ 0xf5, 0x46, 0x1b, 0x1e, 0xe5, 0xbc, 0x36, 0x67, 0x02, 0xe8, 0x9f, 0x28, ++ 0x47, 0xef, 0x84, 0x03, 0xdf, 0x2a, 0xf4, 0xf9, 0x78, 0x5f, 0x55, 0xa3, ++ 0xd1, 0xf3, 0xba, 0xf2, 0x61, 0x5b, 0xa6, 0x8d, 0x71, 0xf2, 0x21, 0x92, ++ 0xa5, 0x7e, 0x1c, 0xcb, 0x54, 0x60, 0x2a, 0x63, 0x61, 0x88, 0x76, 0xda, ++ 0x4b, 0x9b, 0x77, 0x2d, 0x29, 0x45, 0xbc, 0xd6, 0xc3, 0x4f, 0x38, 0x78, ++ 0xe3, 0xe4, 0xb2, 0xe0, 0x7a, 0xdb, 0x47, 0x9b, 0x79, 0x70, 0xd7, 0x84, ++ 0xe8, 0xc7, 0xc1, 0xb1, 0x44, 0x08, 0xc7, 0xb2, 0x61, 0xec, 0xb3, 0x23, ++ 0x38, 0x91, 0x3d, 0xcc, 0xf9, 0x84, 0x19, 0xef, 0x32, 0xa7, 0x97, 0x91, ++ 0xc7, 0x67, 0xe0, 0x1b, 0xa3, 0x25, 0x48, 0xba, 0x69, 0x24, 0x8c, 0x6e, ++ 0xfb, 0xa7, 0x4e, 0x89, 0xae, 0x1f, 0x3d, 0xc0, 0xef, 0xf7, 0x66, 0x2b, ++ 0x70, 0x9f, 0xad, 0x35, 0xaf, 0xf6, 0x56, 0x60, 0x0f, 0xfd, 0xef, 0x3f, ++ 0xd3, 0x5f, 0xa7, 0xdc, 0xfb, 0x4a, 0xa9, 0xf4, 0xfc, 0xfd, 0x03, 0xb6, ++ 0xf3, 0xf1, 0x22, 0xeb, 0x82, 0xd3, 0xb3, 0x5a, 0x6f, 0x3b, 0xe7, 0x0d, ++ 0xe3, 0x0e, 0xde, 0xd7, 0x37, 0x2d, 0xfa, 0xdf, 0xe0, 0x41, 0xb9, 0x16, ++ 0x8d, 0x32, 0x0b, 0x6c, 0xcc, 0xfe, 0xef, 0x42, 0x0e, 0xec, 0x57, 0x3b, ++ 0x05, 0xe3, 0xcb, 0xe0, 0x5f, 0x4e, 0x3c, 0x1c, 0xb6, 0xfb, 0xd5, 0xad, ++ 0xc4, 0xa1, 0x2d, 0xd4, 0xf3, 0x9d, 0x89, 0x58, 0x5b, 0x2b, 0xf1, 0x27, ++ 0x4e, 0xfc, 0xf1, 0x24, 0xfc, 0x58, 0xd7, 0xf0, 0x89, 0xd3, 0xe5, 0xea, ++ 0xb0, 0x0d, 0xa3, 0x76, 0x33, 0x46, 0x18, 0xbf, 0x39, 0x62, 0x4c, 0x2b, ++ 0x75, 0x76, 0xca, 0x40, 0x55, 0x05, 0x75, 0x7a, 0x30, 0x1b, 0x6b, 0xfe, ++ 0x80, 0x01, 0x76, 0x50, 0x77, 0xf0, 0x0a, 0x7d, 0x22, 0x53, 0xcd, 0x24, ++ 0xa0, 0xdf, 0x80, 0xf1, 0x89, 0x32, 0x98, 0x8d, 0xc9, 0x6f, 0x85, 0x88, ++ 0xe1, 0xe7, 0x56, 0x23, 0xc3, 0xa1, 0x55, 0xc4, 0x32, 0xa6, 0x9e, 0x23, ++ 0x9c, 0x1f, 0xa1, 0x2e, 0x27, 0xec, 0xeb, 0xf0, 0x03, 0xe2, 0xcc, 0x8c, ++ 0xe9, 0xc3, 0xdf, 0x67, 0x26, 0x89, 0xf7, 0x86, 0xb9, 0x58, 0x95, 0x53, ++ 0x7f, 0xe0, 0x38, 0xb8, 0xdf, 0x63, 0x39, 0xce, 0x69, 0xce, 0xe1, 0xfb, ++ 0x86, 0x91, 0x1c, 0x54, 0x08, 0x79, 0x2d, 0x67, 0xf9, 0x6d, 0x89, 0x52, ++ 0xda, 0x2a, 0x88, 0xe5, 0x7a, 0x97, 0x6a, 0xcb, 0x1a, 0xe6, 0x8b, 0xf8, ++ 0x73, 0x75, 0xeb, 0x2c, 0x98, 0xbb, 0x3a, 0xd5, 0xce, 0xd9, 0x72, 0xda, ++ 0xbb, 0x99, 0x72, 0x51, 0xb5, 0x58, 0xf7, 0xe0, 0x1b, 0x3b, 0x14, 0x96, ++ 0xea, 0x49, 0x9c, 0x6a, 0x0a, 0x05, 0x3b, 0xe9, 0x2b, 0x47, 0xe8, 0x1f, ++ 0x47, 0xe7, 0x23, 0xc1, 0xaf, 0xd1, 0x3f, 0x1e, 0x99, 0x0f, 0xd3, 0x46, ++ 0xad, 0xc4, 0xf2, 0x65, 0xc1, 0x9d, 0x76, 0x9b, 0xda, 0x49, 0x4c, 0xdf, ++ 0x3c, 0x8d, 0x50, 0xb9, 0xd5, 0xa1, 0x36, 0x64, 0xfb, 0xd5, 0xe6, 0xec, ++ 0xff, 0xbc, 0x70, 0x26, 0x2c, 0x78, 0x64, 0x4c, 0x7d, 0x13, 0x57, 0x52, ++ 0xcf, 0xc4, 0x3c, 0xdb, 0xcd, 0x5d, 0x55, 0x4b, 0xf5, 0x61, 0x7c, 0x27, ++ 0x94, 0xd7, 0xe3, 0x7a, 0xea, 0x71, 0xca, 0x87, 0xaa, 0x25, 0xfa, 0x7e, ++ 0x3c, 0xe2, 0x9e, 0x0b, 0x07, 0x37, 0xda, 0x49, 0x8f, 0x47, 0x47, 0x68, ++ 0xb9, 0xd5, 0xca, 0xfc, 0xb0, 0x8c, 0x98, 0xd7, 0xa6, 0x5a, 0x29, 0x3f, ++ 0xc9, 0x9c, 0x91, 0x64, 0xce, 0x48, 0x72, 0xae, 0x49, 0xe6, 0x8a, 0x96, ++ 0xac, 0xe8, 0x5d, 0xe4, 0x12, 0x53, 0x19, 0x5f, 0x3f, 0xa4, 0xfc, 0x67, ++ 0x6d, 0xe2, 0xa9, 0x4d, 0x3c, 0xb5, 0x89, 0xa7, 0x36, 0xf1, 0xd4, 0x16, ++ 0x1c, 0x6e, 0x23, 0x76, 0xbf, 0x71, 0x21, 0x17, 0x16, 0x0c, 0x0b, 0x33, ++ 0x8e, 0x5a, 0x39, 0x0f, 0xc1, 0xd1, 0x28, 0xf3, 0xdc, 0xb2, 0xe0, 0x76, ++ 0xae, 0x67, 0x3c, 0x13, 0xf4, 0x48, 0x7e, 0x8d, 0xad, 0xc8, 0xc7, 0xea, ++ 0x43, 0x93, 0x12, 0x8f, 0xda, 0x89, 0x28, 0xe3, 0xb4, 0x33, 0x61, 0x3a, ++ 0xb8, 0x52, 0xe2, 0x92, 0xb1, 0xce, 0x58, 0x7e, 0x98, 0xf8, 0x78, 0x7d, ++ 0x62, 0x35, 0x1a, 0xaf, 0x90, 0x5c, 0xa1, 0xb5, 0xa5, 0x30, 0x75, 0x21, ++ 0x15, 0xd6, 0x9a, 0xa7, 0x50, 0x94, 0xfd, 0x87, 0xe4, 0x06, 0x70, 0xe7, ++ 0xc4, 0x22, 0xc6, 0x86, 0x83, 0x76, 0xfa, 0x73, 0xd5, 0x2a, 0xad, 0xb7, ++ 0xca, 0x53, 0x8e, 0x17, 0x0c, 0xc7, 0x69, 0x37, 0x25, 0xbe, 0x28, 0xcb, ++ 0xd3, 0x26, 0x3c, 0xe1, 0xab, 0xcb, 0x99, 0xdb, 0x5f, 0xa5, 0x5f, 0x8c, ++ 0x64, 0x03, 0xd8, 0x37, 0xe1, 0xe6, 0xce, 0xd6, 0x52, 0xc6, 0xd1, 0x50, ++ 0xc2, 0x83, 0xbd, 0xba, 0xd1, 0xb6, 0x48, 0x19, 0x0b, 0x6b, 0xc9, 0xb4, ++ 0x76, 0x32, 0x86, 0xf6, 0x10, 0x1f, 0x5a, 0x27, 0x8d, 0xf8, 0x3f, 0x13, ++ 0xbb, 0xd6, 0x67, 0x2e, 0xc5, 0xcd, 0x9d, 0x13, 0x2e, 0x0f, 0xe0, 0xdc, ++ 0x43, 0x78, 0x8e, 0x71, 0x73, 0x37, 0xe3, 0xe6, 0xe9, 0x42, 0xdc, 0x64, ++ 0xb3, 0x8f, 0x2b, 0xf1, 0x69, 0x78, 0x7c, 0xc4, 0xdd, 0x1b, 0xf8, 0x9d, ++ 0xf1, 0x37, 0x9d, 0xf7, 0x73, 0xb8, 0x18, 0xd2, 0xab, 0x64, 0xce, 0x61, ++ 0x5d, 0x74, 0xf0, 0x08, 0xbf, 0x57, 0xe0, 0x07, 0xcc, 0xf9, 0xe3, 0x94, ++ 0xab, 0x1b, 0x92, 0xa7, 0xfd, 0x30, 0x6b, 0x9d, 0xe5, 0x55, 0x8d, 0x9f, ++ 0x28, 0x89, 0x07, 0x3b, 0xbb, 0x95, 0x36, 0x69, 0x40, 0x3e, 0x1f, 0x84, ++ 0xe8, 0x0f, 0xad, 0xf4, 0x07, 0xc1, 0x91, 0x24, 0xf2, 0x76, 0x6c, 0x63, ++ 0x5e, 0xff, 0xd7, 0xec, 0x57, 0xc7, 0x71, 0xc5, 0x86, 0xa5, 0x85, 0xe7, ++ 0xfd, 0xc4, 0xe5, 0x24, 0x4e, 0x13, 0x13, 0xf2, 0xf9, 0xaa, 0xd2, 0xf5, ++ 0x93, 0x6d, 0xe2, 0x27, 0x25, 0x79, 0xf9, 0x37, 0x4f, 0xa2, 0x64, 0xb1, ++ 0x85, 0x68, 0x90, 0xdc, 0xe3, 0xce, 0x46, 0x23, 0xb7, 0x43, 0x6d, 0x55, ++ 0x9d, 0xd9, 0x70, 0xf0, 0x26, 0x17, 0xe3, 0x5b, 0xd5, 0x4d, 0xf4, 0x99, ++ 0x76, 0xfa, 0x4c, 0xbb, 0x3b, 0xa6, 0xf8, 0xdc, 0xe7, 0xc7, 0xbd, 0x31, ++ 0xbb, 0x84, 0x63, 0x0a, 0xc7, 0x08, 0x07, 0x37, 0x71, 0xae, 0x9b, 0x78, ++ 0xff, 0x3a, 0x7b, 0x94, 0xe7, 0x64, 0xbe, 0x4e, 0x34, 0x68, 0x9d, 0x61, ++ 0xae, 0x46, 0xea, 0x8f, 0x2c, 0x7f, 0xaa, 0xca, 0xfa, 0xcc, 0x79, 0x75, ++ 0xf5, 0x32, 0xe6, 0xeb, 0x08, 0x73, 0x74, 0x98, 0x3a, 0x0c, 0x31, 0x47, ++ 0x27, 0xb9, 0x66, 0x10, 0x93, 0xff, 0x10, 0x1f, 0x75, 0x50, 0xc1, 0x67, ++ 0xc8, 0x35, 0x82, 0x5b, 0xb2, 0xbe, 0xae, 0x52, 0x0b, 0xed, 0x3f, 0x4b, ++ 0x0f, 0x38, 0xe5, 0x3a, 0x53, 0xb2, 0xa5, 0x27, 0xaf, 0x51, 0x15, 0xcd, ++ 0xe4, 0x8e, 0xed, 0x2f, 0x67, 0x9a, 0x7d, 0xfa, 0x68, 0x00, 0x25, 0xe4, ++ 0x4c, 0xeb, 0xb3, 0x8e, 0x33, 0x64, 0xde, 0x73, 0xed, 0xae, 0xe6, 0x67, ++ 0x72, 0xed, 0xb4, 0x7b, 0x2a, 0xdb, 0xe3, 0x62, 0x5a, 0x2a, 0x4b, 0x23, ++ 0xef, 0x68, 0x68, 0x8d, 0xce, 0xaf, 0xf6, 0xf1, 0x77, 0xaa, 0xda, 0x3a, ++ 0x11, 0x44, 0xb0, 0x17, 0xe6, 0x75, 0xc2, 0x27, 0xe0, 0x5f, 0x6c, 0x2d, ++ 0x7c, 0x79, 0x47, 0xad, 0x76, 0x08, 0x1e, 0x6a, 0x6d, 0x14, 0xb8, 0x95, ++ 0x98, 0xff, 0xc9, 0x97, 0x15, 0x9a, 0x57, 0x11, 0xe0, 0xaf, 0x30, 0x71, ++ 0x28, 0xab, 0xb5, 0x11, 0xb7, 0x50, 0x47, 0xce, 0x53, 0x65, 0xed, 0xc3, ++ 0xc7, 0x3c, 0x56, 0x58, 0x3d, 0x48, 0x8f, 0xc4, 0x72, 0xe7, 0xa0, 0xc5, ++ 0xcf, 0x2b, 0x8d, 0x03, 0xd5, 0x9b, 0xcf, 0x91, 0x87, 0x8e, 0x28, 0x2d, ++ 0x79, 0xbb, 0xcb, 0x3d, 0xf7, 0xc1, 0x70, 0xf9, 0x4d, 0x0f, 0xe2, 0xb4, ++ 0x79, 0x2b, 0x65, 0x0e, 0x35, 0x2b, 0xec, 0x32, 0x7f, 0xed, 0x24, 0xc3, ++ 0x5a, 0xf2, 0x0c, 0x79, 0xee, 0x03, 0x5c, 0x77, 0xc5, 0x28, 0xfc, 0x25, ++ 0xbc, 0xf7, 0x38, 0x79, 0x94, 0x8f, 0xf7, 0x0e, 0xa7, 0x63, 0xe6, 0x21, ++ 0xa5, 0x35, 0x93, 0xd3, 0x32, 0x8a, 0xeb, 0x93, 0x67, 0xc9, 0x35, 0x07, ++ 0xa1, 0x9d, 0xe7, 0x00, 0xae, 0xcc, 0xba, 0x82, 0xcc, 0xb5, 0x19, 0xa8, ++ 0x4d, 0xf6, 0x21, 0xec, 0x34, 0x5a, 0x99, 0x2f, 0x9a, 0xc9, 0xdf, 0xc8, ++ 0x97, 0x29, 0xaf, 0x6c, 0x54, 0xe4, 0x5e, 0x6e, 0x67, 0xa2, 0x33, 0xc7, ++ 0x58, 0x64, 0xf5, 0x61, 0xef, 0x88, 0x8c, 0xd1, 0x2b, 0x63, 0xc4, 0x5f, ++ 0xa6, 0xcc, 0xdb, 0x54, 0x7e, 0x8c, 0xf7, 0xbc, 0x5a, 0x33, 0xc7, 0x58, ++ 0x38, 0xc7, 0x31, 0x02, 0xba, 0xc8, 0xef, 0x13, 0xf9, 0x3c, 0xf6, 0xe2, ++ 0xfa, 0x4c, 0x3f, 0xed, 0xea, 0x57, 0x9d, 0x13, 0x37, 0xe0, 0xe8, 0xf4, ++ 0x0d, 0xb0, 0x27, 0x14, 0xf3, 0xe5, 0x12, 0xe4, 0x96, 0xb8, 0x1c, 0xbe, ++ 0x32, 0xa8, 0xd7, 0x60, 0x7f, 0x08, 0x55, 0x55, 0xfa, 0x97, 0x70, 0x77, ++ 0x81, 0xff, 0xee, 0x1c, 0x6f, 0x47, 0x84, 0x18, 0x7c, 0xf5, 0x2a, 0x1f, ++ 0x9a, 0xab, 0x91, 0x5c, 0x6e, 0x35, 0xd3, 0x3f, 0xdf, 0xf7, 0xe4, 0x31, ++ 0xff, 0x23, 0x7f, 0x3e, 0xcf, 0xb8, 0xba, 0xff, 0xc2, 0xb5, 0x1b, 0x30, ++ 0x32, 0x51, 0x0a, 0x72, 0xd0, 0xed, 0x15, 0x78, 0x4d, 0x62, 0xf9, 0xad, ++ 0x1d, 0x6a, 0x9d, 0x57, 0xfc, 0x49, 0xec, 0xf4, 0xc7, 0x56, 0x9b, 0xf5, ++ 0x5f, 0xeb, 0x5e, 0x2b, 0xe4, 0xa9, 0xcb, 0xcf, 0xf7, 0xfc, 0x81, 0xf3, ++ 0x0a, 0x4f, 0x8e, 0x85, 0xc8, 0x63, 0x43, 0xc8, 0xa4, 0x1d, 0x78, 0x2d, ++ 0x1f, 0x7a, 0x46, 0x24, 0x2f, 0x87, 0x31, 0x97, 0xd6, 0xba, 0xce, 0x90, ++ 0x5b, 0xef, 0x6a, 0xd2, 0x71, 0xd7, 0x5c, 0x04, 0xb3, 0x69, 0x38, 0x01, ++ 0x4b, 0xcf, 0x05, 0xc8, 0x47, 0xf6, 0xcc, 0x2d, 0xc3, 0x7c, 0x5a, 0x5f, ++ 0x18, 0x54, 0x46, 0x7f, 0x8d, 0xd7, 0x87, 0xbb, 0xe7, 0x1a, 0xb0, 0x9f, ++ 0x39, 0x7c, 0x8e, 0x32, 0x36, 0x27, 0x96, 0xf1, 0x7e, 0x0f, 0x9e, 0x38, ++ 0xc2, 0xbc, 0x44, 0x3c, 0xe8, 0x99, 0x03, 0x66, 0xc7, 0x18, 0xf3, 0xc7, ++ 0x19, 0xff, 0x8f, 0x01, 0x7b, 0x1e, 0xf3, 0x60, 0x7a, 0xcc, 0xa1, 0x8d, ++ 0x07, 0x6b, 0x3c, 0x28, 0x41, 0x17, 0x79, 0x64, 0x09, 0xf9, 0xd7, 0x6d, ++ 0xa1, 0x3c, 0xbf, 0x3b, 0xc3, 0x5c, 0x75, 0xe7, 0x63, 0x71, 0xbc, 0x95, ++ 0x4e, 0x61, 0xf3, 0xea, 0x08, 0xfa, 0x39, 0x97, 0xd7, 0xd3, 0xc4, 0x94, ++ 0x39, 0x13, 0xaf, 0xa5, 0xfd, 0x1c, 0xa7, 0x01, 0x27, 0xd3, 0x72, 0x8f, ++ 0xdc, 0x5b, 0x81, 0x6e, 0xce, 0xe5, 0xd5, 0x74, 0x84, 0x63, 0x86, 0xf1, ++ 0x33, 0xde, 0x77, 0xc7, 0x9c, 0x4e, 0x1e, 0xeb, 0xe7, 0xb8, 0x51, 0xbc, ++ 0x9c, 0x26, 0x66, 0xf1, 0xfc, 0x0b, 0xe9, 0x6e, 0x0c, 0xa5, 0xeb, 0x17, ++ 0xd6, 0x91, 0x2b, 0x45, 0xaf, 0xc8, 0xe7, 0xe0, 0x17, 0xd2, 0xef, 0x3a, ++ 0x5b, 0xdd, 0x5c, 0x29, 0xe3, 0x14, 0xc7, 0xed, 0xc6, 0x60, 0xfa, 0x51, ++ 0x6f, 0xb1, 0xf6, 0x7c, 0x72, 0x4c, 0xb8, 0xff, 0x32, 0x3c, 0x61, 0xf3, ++ 0xfb, 0x34, 0x30, 0x6f, 0xa7, 0x9c, 0x2a, 0x8b, 0x9c, 0x80, 0x98, 0xfc, ++ 0xf6, 0xea, 0x06, 0x8e, 0xab, 0x77, 0xbd, 0xa0, 0xa4, 0x16, 0xf0, 0x21, ++ 0xfa, 0x98, 0xe8, 0xcb, 0x83, 0x29, 0xe6, 0xb7, 0xe7, 0x88, 0x8b, 0x75, ++ 0x23, 0x5a, 0x84, 0x3e, 0xda, 0x39, 0x05, 0xad, 0x3d, 0x87, 0xda, 0xf8, ++ 0x5d, 0x18, 0x70, 0x4a, 0x2d, 0x62, 0x31, 0xf1, 0x76, 0xae, 0xc1, 0x71, ++ 0x3e, 0x5a, 0xed, 0x38, 0xff, 0xd8, 0x04, 0xc7, 0x63, 0xe9, 0x66, 0x8d, ++ 0x37, 0xf7, 0xa5, 0x4a, 0xe8, 0x0b, 0x41, 0xa5, 0xe7, 0xde, 0x86, 0xd1, ++ 0xfb, 0x22, 0x44, 0xaf, 0xc0, 0xca, 0x39, 0x1f, 0xae, 0xe5, 0x7a, 0xd6, ++ 0x8f, 0x70, 0x6c, 0x72, 0x04, 0x83, 0x6b, 0xda, 0x36, 0xe2, 0x90, 0x6b, ++ 0x54, 0x60, 0x05, 0x75, 0xdc, 0xf3, 0x88, 0xe3, 0x94, 0x51, 0xc7, 0x75, ++ 0xb4, 0xcf, 0xed, 0xe3, 0x0e, 0x5e, 0x30, 0x5f, 0xa0, 0x4e, 0x15, 0xba, ++ 0xda, 0x9b, 0xf8, 0x4c, 0x98, 0xf7, 0x93, 0x57, 0x8d, 0x48, 0x2d, 0xb1, ++ 0x8c, 0xf7, 0x9c, 0xc6, 0xe1, 0x74, 0x1c, 0x0d, 0xd4, 0x5f, 0x94, 0x32, ++ 0xeb, 0xf9, 0x4c, 0x74, 0x2e, 0x5f, 0xcf, 0x45, 0xe7, 0x04, 0x83, 0x2e, ++ 0xc7, 0x1c, 0xc1, 0x20, 0xe0, 0xe8, 0x98, 0x76, 0x28, 0x47, 0x8c, 0xa9, ++ 0xb4, 0x06, 0x98, 0x43, 0x80, 0xd7, 0xa7, 0x14, 0x46, 0xc7, 0x58, 0xff, ++ 0xac, 0x86, 0x53, 0xce, 0x75, 0xbc, 0x36, 0xf5, 0x27, 0x78, 0xfc, 0x08, ++ 0xd7, 0x7e, 0x2c, 0x8c, 0xef, 0xa7, 0x7d, 0xb8, 0x7a, 0x54, 0x4b, 0x4d, ++ 0x41, 0x8f, 0xef, 0x53, 0x82, 0x3d, 0xda, 0x58, 0x0a, 0x46, 0xb4, 0x44, ++ 0x79, 0x50, 0xfb, 0xb8, 0x0f, 0xfa, 0x7c, 0x14, 0x25, 0xb5, 0x7e, 0xe8, ++ 0xb5, 0xdf, 0xa4, 0x0f, 0x7a, 0x50, 0x4a, 0x2e, 0xb3, 0xf1, 0xe1, 0x38, ++ 0xcf, 0x85, 0x79, 0x0e, 0x7f, 0x52, 0x06, 0xef, 0x52, 0x2f, 0xf3, 0x4a, ++ 0xa9, 0xce, 0x02, 0xc8, 0xe7, 0x38, 0x5e, 0x72, 0x82, 0x9d, 0xdf, 0x71, ++ 0x9c, 0xd8, 0xaa, 0x6f, 0xba, 0x7c, 0x30, 0x36, 0xaf, 0xf3, 0x3e, 0xce, ++ 0x8b, 0xb9, 0xe5, 0x07, 0xac, 0xe1, 0x9e, 0xa6, 0xcf, 0x3e, 0x65, 0x7b, ++ 0xe9, 0x3b, 0x9a, 0x29, 0x36, 0x44, 0x79, 0x94, 0xeb, 0x7c, 0xcb, 0xb5, ++ 0xd7, 0xd3, 0xc4, 0xcf, 0xa7, 0x18, 0xeb, 0xb2, 0x86, 0x13, 0x63, 0x8a, ++ 0x38, 0x6b, 0xf1, 0xde, 0xb5, 0xf0, 0x26, 0x84, 0xb7, 0x86, 0xb1, 0x2b, ++ 0xd4, 0x8c, 0x27, 0xed, 0x12, 0x2c, 0xd2, 0x97, 0x62, 0x6f, 0x7b, 0x08, ++ 0x4f, 0x66, 0xb5, 0x28, 0xed, 0x14, 0xcf, 0xe1, 0x9f, 0xbc, 0x8c, 0x27, ++ 0x13, 0x9e, 0xe7, 0xa1, 0x3f, 0xec, 0xc1, 0x90, 0xe9, 0xa5, 0x7f, 0x9a, ++ 0x28, 0xad, 0x05, 0x72, 0x19, 0x1f, 0x4e, 0xe9, 0x94, 0x69, 0x53, 0x3e, ++ 0xe7, 0xf0, 0x94, 0xad, 0x85, 0x72, 0xae, 0xbf, 0xc6, 0x39, 0xae, 0xd6, ++ 0x9c, 0x54, 0x7f, 0xee, 0x95, 0x79, 0x72, 0x5c, 0x5f, 0xde, 0x7f, 0x1e, ++ 0xf3, 0x4a, 0xfe, 0xbb, 0xf4, 0xbb, 0x1c, 0x1e, 0x4b, 0x8b, 0xb4, 0x78, ++ 0x05, 0x5f, 0x32, 0xd6, 0xb0, 0xfe, 0x47, 0x97, 0xcd, 0xbd, 0x03, 0x43, ++ 0xd9, 0x4b, 0xb5, 0x67, 0x5b, 0xda, 0xf5, 0x9b, 0x36, 0xd1, 0xfd, 0x43, ++ 0xa6, 0x60, 0x6b, 0xbf, 0x6a, 0x25, 0x56, 0xa5, 0x7c, 0xf9, 0xda, 0xf2, ++ 0x20, 0x6b, 0xcb, 0x97, 0xd2, 0xd2, 0x5f, 0xe8, 0xc3, 0x6e, 0x1e, 0x23, ++ 0x3c, 0x17, 0xb1, 0x63, 0xd1, 0x13, 0xd0, 0x7a, 0xba, 0x89, 0x51, 0xc4, ++ 0xab, 0xfe, 0x19, 0xa5, 0xf5, 0xd6, 0x78, 0xa5, 0xce, 0xcf, 0x63, 0xd5, ++ 0x8a, 0x02, 0x56, 0x35, 0x64, 0xc2, 0xc1, 0x36, 0xe6, 0xa1, 0x36, 0xe6, ++ 0xd1, 0x8d, 0x2e, 0x8f, 0xea, 0x54, 0x5b, 0x66, 0xfd, 0x6a, 0x03, 0x79, ++ 0xea, 0x4b, 0xa6, 0xc2, 0x54, 0x07, 0x42, 0x57, 0xaf, 0x46, 0x60, 0xcb, ++ 0x44, 0x3b, 0xca, 0x88, 0x4f, 0x77, 0x26, 0xca, 0xb0, 0xd1, 0xcd, 0x95, ++ 0x92, 0xef, 0xa5, 0x9e, 0xee, 0x20, 0xd6, 0x21, 0x14, 0xb0, 0xf2, 0xb5, ++ 0xb3, 0xe0, 0xde, 0x36, 0x3e, 0x7b, 0x82, 0x7e, 0x88, 0x7c, 0x4e, 0x55, ++ 0x37, 0xb1, 0x0e, 0xf9, 0x28, 0xa1, 0x90, 0xdb, 0xee, 0x07, 0x65, 0x71, ++ 0xbd, 0xa1, 0xaf, 0x0c, 0x8f, 0xb5, 0xab, 0xd6, 0xe9, 0x99, 0xc0, 0x3a, ++ 0x5b, 0xf2, 0xf3, 0x54, 0x80, 0xdc, 0x85, 0x39, 0xf1, 0x8b, 0xb2, 0xa4, ++ 0x6f, 0x71, 0xda, 0xba, 0x9e, 0x3c, 0xaa, 0x79, 0xd5, 0x6f, 0x1d, 0xfc, ++ 0x99, 0x3c, 0x7f, 0x6f, 0x41, 0x7f, 0x49, 0xce, 0x27, 0xec, 0xdf, 0x98, ++ 0x0d, 0xf9, 0x93, 0xd9, 0x56, 0x3e, 0xdf, 0x4e, 0x59, 0x1d, 0x81, 0x56, ++ 0xfb, 0x96, 0xc0, 0x7a, 0x7b, 0x6b, 0x60, 0x83, 0xcd, 0xd8, 0xcd, 0xb6, ++ 0x53, 0x8f, 0x5b, 0x59, 0x07, 0xdf, 0x42, 0x8e, 0x29, 0x32, 0xbb, 0xc8, ++ 0x77, 0x03, 0x5c, 0xdb, 0x00, 0xd7, 0x96, 0x8b, 0x90, 0xb1, 0x6b, 0x25, ++ 0xcc, 0x19, 0x43, 0xae, 0xdd, 0x0e, 0xb9, 0xbd, 0x98, 0x72, 0xeb, 0xe7, ++ 0xd6, 0xe6, 0x71, 0x62, 0xba, 0xf5, 0x8a, 0x75, 0xf5, 0x23, 0xa8, 0x2e, ++ 0xb1, 0x60, 0xd1, 0x52, 0x88, 0x1b, 0x86, 0x79, 0x0e, 0x46, 0xe4, 0x25, ++ 0xde, 0x3b, 0x48, 0x5f, 0x1d, 0x72, 0xeb, 0x6f, 0x1a, 0x20, 0xd3, 0x80, ++ 0xcd, 0xb6, 0x3f, 0x70, 0x23, 0xeb, 0xb9, 0x2a, 0x4b, 0x6b, 0xbe, 0xc9, ++ 0x2b, 0x35, 0x6f, 0xee, 0xab, 0x95, 0x68, 0x40, 0x5b, 0xd6, 0x1f, 0x58, ++ 0x37, 0xf9, 0x47, 0xf8, 0xd5, 0x11, 0x2d, 0x99, 0x82, 0xf8, 0x9d, 0xe3, ++ 0x1c, 0x4e, 0x00, 0x87, 0x33, 0xcb, 0xf0, 0x41, 0xde, 0xa6, 0x5d, 0x39, ++ 0xfa, 0xf8, 0x83, 0x99, 0x28, 0xde, 0x25, 0x46, 0xf9, 0xe6, 0x6a, 0xf0, ++ 0xce, 0x98, 0x17, 0xbb, 0x59, 0xeb, 0xee, 0x72, 0xf1, 0xcf, 0x83, 0xdb, ++ 0xe2, 0xf7, 0x62, 0x2a, 0x2c, 0xf1, 0x71, 0x23, 0x6e, 0x77, 0xcf, 0x79, ++ 0x99, 0x27, 0xfe, 0x0c, 0xfd, 0xf9, 0xbc, 0xc1, 0x79, 0xe6, 0x38, 0xcf, ++ 0xa6, 0xc0, 0xfa, 0x09, 0x2d, 0xb0, 0x61, 0x42, 0xfa, 0x3b, 0xa7, 0xac, ++ 0xd7, 0x1e, 0x61, 0xcd, 0x62, 0x0e, 0x2e, 0xb0, 0x2a, 0xc4, 0x7b, 0x47, ++ 0x1c, 0x9c, 0x34, 0x3b, 0xf1, 0xc0, 0x24, 0x4e, 0xd5, 0xd0, 0x68, 0xac, ++ 0x89, 0x9c, 0x6b, 0x13, 0x46, 0xc8, 0xeb, 0xd5, 0x58, 0x17, 0x19, 0x0b, ++ 0xdb, 0x58, 0x0f, 0x10, 0xa2, 0x92, 0xa5, 0x96, 0x91, 0xab, 0xf5, 0x62, ++ 0xab, 0x8f, 0xf3, 0x09, 0x10, 0xa3, 0x23, 0x73, 0xd1, 0xc0, 0x4d, 0xcc, ++ 0x2b, 0x5e, 0xd6, 0x85, 0x01, 0x03, 0xdf, 0xac, 0x82, 0xd1, 0xf3, 0xa2, ++ 0xf2, 0xa3, 0x72, 0xae, 0x81, 0xba, 0x56, 0x78, 0x4f, 0x77, 0x06, 0x1e, ++ 0x37, 0x2b, 0xe0, 0x99, 0x33, 0x03, 0x3b, 0xc9, 0x75, 0x3d, 0x46, 0x27, ++ 0x0e, 0xce, 0x86, 0x50, 0x33, 0xd7, 0x4c, 0x1b, 0x84, 0xb9, 0x16, 0x1f, ++ 0x31, 0x25, 0x19, 0xe8, 0x14, 0xdb, 0xcd, 0xad, 0xa1, 0x2c, 0xf8, 0x2b, ++ 0xad, 0x37, 0xac, 0xb9, 0xf1, 0x10, 0xf1, 0xc5, 0xa1, 0x3f, 0x68, 0x91, ++ 0xd3, 0x0a, 0x7b, 0x08, 0x6b, 0xad, 0x95, 0x30, 0x3a, 0x0f, 0xb1, 0x6e, ++ 0xd9, 0xb3, 0xba, 0x82, 0xb8, 0x24, 0x7a, 0xa5, 0x4e, 0xb3, 0xc5, 0xb5, ++ 0x49, 0xae, 0x7f, 0xc5, 0x3a, 0x7e, 0x44, 0x78, 0xc4, 0xf3, 0xd6, 0xc7, ++ 0x8f, 0xe8, 0x78, 0x97, 0xb9, 0xa4, 0x36, 0xa1, 0xf5, 0x3e, 0x8e, 0x18, ++ 0xd7, 0x20, 0x6b, 0xfa, 0x67, 0xe7, 0x98, 0x61, 0x2c, 0xec, 0xa2, 0x3e, ++ 0x22, 0xc4, 0xc2, 0x1a, 0x62, 0x7c, 0x64, 0x8e, 0x0a, 0x9a, 0x5b, 0xa0, ++ 0xaf, 0x44, 0xe0, 0x37, 0x74, 0x9c, 0x3d, 0x12, 0xa7, 0x2e, 0x2e, 0xca, ++ 0xfc, 0x76, 0x29, 0xd0, 0xc7, 0x54, 0x7f, 0xff, 0xaf, 0xe9, 0x8f, 0x27, ++ 0x39, 0x6e, 0x25, 0xef, 0xf7, 0xb9, 0xf7, 0x87, 0x79, 0xff, 0xa5, 0xb1, ++ 0x3d, 0x1c, 0xbb, 0xe5, 0x88, 0xf4, 0x6b, 0x9e, 0xb7, 0x4e, 0x1d, 0xc9, ++ 0x8f, 0x6d, 0x24, 0xe2, 0x38, 0x7f, 0x44, 0x5b, 0x58, 0x8f, 0x58, 0x3f, ++ 0x75, 0xb6, 0x2c, 0x02, 0xec, 0xf3, 0xe1, 0x23, 0xe7, 0x23, 0xce, 0x61, ++ 0x3f, 0x65, 0x1e, 0x5b, 0x9d, 0x9f, 0x87, 0x67, 0x4e, 0xf4, 0x11, 0xe1, ++ 0x5c, 0xc2, 0x85, 0xb9, 0x2c, 0xa3, 0xec, 0x87, 0x0b, 0x35, 0x99, 0x8e, ++ 0x77, 0x2e, 0xcd, 0x27, 0x4c, 0x3d, 0xf8, 0x77, 0x36, 0xc9, 0xdc, 0xe5, ++ 0xbe, 0x10, 0xef, 0x13, 0x3d, 0xfc, 0x8b, 0xf2, 0xe8, 0xe7, 0x88, 0x61, ++ 0x82, 0x23, 0x61, 0xe2, 0x57, 0x97, 0xe4, 0xf7, 0x54, 0x8a, 0xbe, 0x5f, ++ 0x42, 0xdf, 0x5f, 0x2f, 0xfe, 0x6d, 0xd3, 0xbf, 0x6d, 0xfa, 0xb7, 0xad, ++ 0x45, 0x7a, 0x11, 0x0b, 0x75, 0xd3, 0x7e, 0xc9, 0x88, 0xf8, 0x7d, 0x07, ++ 0x76, 0xf3, 0x73, 0x3b, 0xaf, 0x1f, 0x64, 0x0d, 0x0a, 0xb7, 0xd6, 0xec, ++ 0x23, 0xa7, 0xba, 0x1f, 0x3d, 0x13, 0xf8, 0x5d, 0xa0, 0xa9, 0x0c, 0x65, ++ 0x2b, 0x4a, 0x70, 0x26, 0xa4, 0x85, 0x1e, 0xc4, 0xfd, 0xe4, 0xfa, 0xff, ++ 0xa2, 0x16, 0xe9, 0xbe, 0xf6, 0xc3, 0xe4, 0x37, 0xad, 0xaa, 0x02, 0xbb, ++ 0xb2, 0xb7, 0x04, 0x6e, 0xb4, 0x63, 0x3d, 0x2f, 0xb1, 0x76, 0x9e, 0xaa, ++ 0xe1, 0xd8, 0x8c, 0xab, 0x9b, 0x38, 0x8e, 0x2d, 0xf3, 0x70, 0xb1, 0x96, ++ 0xda, 0xa6, 0x6e, 0x7f, 0x52, 0xd7, 0xcd, 0xf1, 0xf3, 0xf3, 0x18, 0x64, ++ 0xfd, 0xd1, 0xcd, 0x39, 0xed, 0x76, 0x63, 0xad, 0x83, 0x32, 0x2e, 0x61, ++ 0xd8, 0xba, 0xb4, 0xe4, 0x4e, 0x07, 0x0f, 0xb0, 0x2e, 0x78, 0x82, 0x9f, ++ 0x05, 0xe2, 0xd8, 0xd0, 0x65, 0x38, 0xe6, 0xe1, 0x7d, 0x3b, 0x79, 0x5f, ++ 0x33, 0x31, 0x7c, 0x76, 0x5a, 0xfa, 0x64, 0x7d, 0xd2, 0x27, 0x43, 0xc6, ++ 0x16, 0xdd, 0xf7, 0xe2, 0x54, 0x3a, 0xd6, 0xef, 0xf5, 0x3a, 0x03, 0x41, ++ 0x4b, 0x5b, 0xf8, 0x98, 0x3e, 0xfc, 0xea, 0x6a, 0xad, 0x9d, 0x3a, 0x8c, ++ 0x93, 0x3b, 0x46, 0x5e, 0x41, 0x6e, 0xa3, 0x1f, 0xf5, 0xd1, 0x6b, 0xbd, ++ 0x46, 0x88, 0x98, 0x97, 0xeb, 0xe6, 0x4a, 0x8f, 0x65, 0xf3, 0x38, 0x77, ++ 0x7d, 0x01, 0xe7, 0x9a, 0x33, 0xe5, 0xc4, 0x21, 0xe6, 0xe3, 0x69, 0x27, ++ 0x15, 0x64, 0xae, 0xca, 0x4e, 0x8b, 0xec, 0x01, 0xd4, 0x27, 0x44, 0x96, ++ 0xde, 0x36, 0xa2, 0xf0, 0xf5, 0x45, 0x30, 0x98, 0xa7, 0x60, 0x96, 0xe9, ++ 0x29, 0x87, 0xf9, 0x28, 0x54, 0x62, 0x49, 0xae, 0xdc, 0x4a, 0x6c, 0xec, ++ 0x20, 0x36, 0x0a, 0x7f, 0x97, 0xde, 0x61, 0x1e, 0x9b, 0xd6, 0x67, 0xc5, ++ 0x2e, 0x62, 0x13, 0xb1, 0x4d, 0x1f, 0x6e, 0xb3, 0x91, 0x92, 0x7c, 0x3e, ++ 0x66, 0x1a, 0xd1, 0xc7, 0x21, 0x76, 0xea, 0xa3, 0x2e, 0x4a, 0xb0, 0x9b, ++ 0x58, 0xb8, 0xab, 0x89, 0xba, 0x0a, 0x96, 0x60, 0xd7, 0xb4, 0xd4, 0x3d, ++ 0x45, 0xfd, 0x95, 0xd0, 0x86, 0x8a, 0x71, 0xbd, 0xbf, 0x24, 0xaf, 0xc7, ++ 0x3c, 0xef, 0xf7, 0x5a, 0x22, 0x2f, 0x42, 0xb9, 0x92, 0x7b, 0xf3, 0xba, ++ 0xdb, 0x98, 0x16, 0xb9, 0x0e, 0x4e, 0x98, 0x79, 0x9e, 0x5a, 0xd4, 0x99, ++ 0xe0, 0x7c, 0xf5, 0x1a, 0xe0, 0xda, 0x51, 0x89, 0xad, 0x3e, 0xcc, 0x8d, ++ 0x08, 0x7e, 0xf5, 0x62, 0xf3, 0x48, 0xac, 0xf7, 0x7d, 0xa5, 0xc5, 0xe7, ++ 0xc9, 0x37, 0x84, 0x63, 0xcf, 0x33, 0x77, 0x6c, 0x21, 0x3f, 0xae, 0x2d, ++ 0x60, 0xbf, 0x91, 0x21, 0x6f, 0x47, 0x5e, 0x2f, 0x75, 0x99, 0xaa, 0x02, ++ 0x4e, 0xf7, 0x61, 0x17, 0x79, 0x4c, 0x4d, 0xed, 0x00, 0xfc, 0x8d, 0x9e, ++ 0x0b, 0x1e, 0x0c, 0xe0, 0xbd, 0x55, 0x8c, 0x92, 0x25, 0x0e, 0xae, 0x5a, ++ 0x95, 0x72, 0xca, 0xf4, 0xda, 0x68, 0x99, 0x47, 0x7a, 0xb0, 0x46, 0x6a, ++ 0x88, 0x79, 0xc8, 0xd3, 0xa8, 0xa5, 0x92, 0xf0, 0x87, 0xaa, 0xf5, 0xae, ++ 0x02, 0x87, 0x8c, 0xf8, 0x37, 0x91, 0xe7, 0x18, 0x89, 0xcf, 0x9c, 0xa9, ++ 0xf0, 0x00, 0x22, 0x8d, 0xb9, 0xfe, 0x08, 0x92, 0xf7, 0x44, 0x20, 0x38, ++ 0x73, 0x08, 0x19, 0x23, 0xe2, 0xdf, 0x9a, 0x4d, 0x05, 0x36, 0xd7, 0x45, ++ 0xb1, 0x65, 0xa4, 0x55, 0x6d, 0xc9, 0xea, 0xd8, 0x30, 0xd2, 0xc6, 0x7a, ++ 0xbd, 0x5d, 0xb5, 0x4f, 0x8b, 0x7e, 0x44, 0xbf, 0x5a, 0x28, 0xea, 0xe1, ++ 0xda, 0x2f, 0xe6, 0xf3, 0x3c, 0x1f, 0xf9, 0x49, 0xdd, 0x39, 0xd7, 0x77, ++ 0x86, 0xcd, 0x10, 0xf5, 0xf2, 0xe3, 0x12, 0x04, 0x1d, 0x1c, 0x37, 0xc5, ++ 0xe7, 0x42, 0x6e, 0xfd, 0xbd, 0xbe, 0x69, 0xcc, 0xf1, 0xe9, 0x52, 0x7f, ++ 0x45, 0x5c, 0x7b, 0x49, 0xbd, 0xd7, 0x3a, 0xdd, 0x41, 0x1b, 0x15, 0xfb, ++ 0xb9, 0x37, 0x04, 0xd6, 0x89, 0x1d, 0xcc, 0x4a, 0x24, 0x43, 0x4a, 0x05, ++ 0xac, 0x72, 0x7f, 0x9c, 0x39, 0xf3, 0x50, 0xa6, 0x0f, 0x1b, 0x39, 0xe7, ++ 0x07, 0x32, 0xe2, 0x63, 0x6f, 0x58, 0xa7, 0xc8, 0x7d, 0x5f, 0x32, 0x4b, ++ 0x31, 0xd5, 0xee, 0x27, 0xae, 0x77, 0xe1, 0x4e, 0x8e, 0xff, 0x10, 0xeb, ++ 0xdc, 0x7c, 0x6f, 0x59, 0x0b, 0xa5, 0x10, 0x2d, 0x95, 0x7a, 0x74, 0x58, ++ 0xbf, 0xdc, 0xf6, 0x6b, 0x89, 0xbb, 0x5a, 0xfb, 0x14, 0x52, 0xf1, 0x12, ++ 0xc4, 0x9a, 0x0f, 0x40, 0x78, 0x17, 0x71, 0x53, 0x97, 0xd8, 0x3e, 0xc5, ++ 0xd8, 0x7e, 0xcb, 0x39, 0xa7, 0xfb, 0x68, 0xeb, 0x35, 0x58, 0x17, 0x12, ++ 0x1c, 0xb7, 0x02, 0xed, 0x93, 0x3e, 0x4f, 0x95, 0x85, 0x26, 0xd6, 0xd5, ++ 0x4e, 0xd0, 0xed, 0x4f, 0x01, 0x23, 0x99, 0x1b, 0x02, 0x5b, 0x27, 0xa2, ++ 0x38, 0x9c, 0xf0, 0x17, 0xfa, 0xa7, 0xd7, 0x71, 0xce, 0x5e, 0xe5, 0xb1, ++ 0xe0, 0xbd, 0xb5, 0xc9, 0xc1, 0x7d, 0xa6, 0x91, 0x5b, 0xeb, 0xf5, 0x53, ++ 0x8e, 0x0f, 0x47, 0x33, 0x4d, 0xbc, 0xa6, 0x05, 0x76, 0x4e, 0x0c, 0x9e, ++ 0x2f, 0x81, 0xcb, 0x9d, 0x73, 0x1e, 0x1e, 0xaf, 0x5d, 0x85, 0xfd, 0xc4, ++ 0xa2, 0x3e, 0x62, 0x75, 0xd7, 0xbc, 0x32, 0xa2, 0x0f, 0x2a, 0x24, 0x03, ++ 0x96, 0x91, 0x7a, 0x10, 0x6f, 0x39, 0xbf, 0xc9, 0xac, 0xe1, 0x33, 0x6d, ++ 0x8c, 0x61, 0xc1, 0x64, 0x79, 0x46, 0x5b, 0xd8, 0x0c, 0xad, 0x77, 0xad, ++ 0x37, 0xd6, 0x75, 0x5e, 0xe1, 0xee, 0x20, 0x8c, 0xf6, 0xc7, 0x89, 0xc1, ++ 0x07, 0x12, 0xa9, 0xce, 0xe5, 0x30, 0xda, 0xd6, 0xd3, 0x5f, 0x7a, 0x54, ++ 0x94, 0xb9, 0x40, 0xec, 0x1b, 0xc7, 0x6f, 0x38, 0xae, 0x4f, 0x17, 0x3b, ++ 0xad, 0x45, 0xf7, 0x34, 0x6b, 0xa0, 0x8b, 0x7e, 0x2c, 0xba, 0x11, 0xbd, ++ 0xd3, 0x59, 0xca, 0x17, 0x73, 0x7d, 0x6f, 0xb8, 0x78, 0x15, 0xd0, 0xe3, ++ 0xf8, 0x11, 0x6d, 0xfc, 0x43, 0xf2, 0xae, 0x67, 0x2f, 0xf2, 0x48, 0xf1, ++ 0xb9, 0x37, 0xac, 0xab, 0xa7, 0x1a, 0xa8, 0xbb, 0x65, 0x78, 0xc6, 0xad, ++ 0x6b, 0xfd, 0x81, 0xb6, 0x49, 0x07, 0x8f, 0x98, 0x41, 0x48, 0xcf, 0xa8, ++ 0x2c, 0x91, 0x23, 0xc3, 0x68, 0xc0, 0x06, 0x9e, 0x6f, 0x9d, 0x5c, 0xa4, ++ 0x5a, 0x27, 0x1c, 0x3c, 0x6b, 0x6a, 0xa9, 0x16, 0x2f, 0xf1, 0xc2, 0x94, ++ 0x5e, 0x74, 0x99, 0xea, 0x0a, 0x89, 0xff, 0xfa, 0x50, 0xa1, 0xe7, 0xe5, ++ 0x35, 0x4c, 0xdd, 0x40, 0x7e, 0x22, 0xf1, 0xeb, 0x5d, 0x59, 0x8e, 0x2d, ++ 0x6a, 0xca, 0x97, 0xef, 0x79, 0x25, 0xb3, 0x8b, 0x18, 0xf3, 0x51, 0xe6, ++ 0x9a, 0x52, 0xe4, 0x7b, 0x95, 0x37, 0x04, 0x3a, 0x27, 0xf0, 0x37, 0x11, ++ 0x78, 0xbf, 0x73, 0x05, 0xf6, 0xaa, 0x64, 0xa9, 0x9c, 0x93, 0x31, 0x92, ++ 0x05, 0x6e, 0xd7, 0x8e, 0x09, 0x62, 0xd9, 0x20, 0xe3, 0xe0, 0x66, 0xfd, ++ 0x86, 0xc0, 0x46, 0xfa, 0xcc, 0x59, 0xd3, 0x83, 0x1c, 0xd1, 0x79, 0xb1, ++ 0x2e, 0xbd, 0x89, 0x06, 0xd4, 0x7c, 0xa7, 0x89, 0x32, 0x24, 0x9f, 0x75, ++ 0xe2, 0xd1, 0x59, 0xd6, 0xdb, 0xab, 0xdc, 0x5c, 0xd6, 0x73, 0xa3, 0x27, ++ 0xd5, 0x59, 0x49, 0x6e, 0xbf, 0x8f, 0xb5, 0xec, 0x76, 0x37, 0xce, 0x4e, ++ 0x59, 0xf1, 0x99, 0x08, 0x4a, 0x1e, 0x16, 0xbc, 0xd3, 0x22, 0x01, 0xf7, ++ 0xdc, 0x82, 0x15, 0xe3, 0xb9, 0xea, 0x87, 0xbd, 0x88, 0x2e, 0x2d, 0xc7, ++ 0x1e, 0xbd, 0xd2, 0xe5, 0x81, 0x7b, 0xc8, 0x0b, 0x7e, 0x63, 0xca, 0xf5, ++ 0x57, 0x78, 0x5d, 0x8e, 0x39, 0x2b, 0xea, 0x1e, 0x9f, 0xe7, 0xb1, 0xd8, ++ 0x9f, 0xf9, 0xae, 0x4f, 0x8e, 0x49, 0xce, 0x61, 0x0b, 0xf9, 0xc6, 0x66, ++ 0xf2, 0x8d, 0x0a, 0xf2, 0x8d, 0xad, 0xe4, 0x1b, 0xeb, 0x13, 0xb9, 0x4d, ++ 0x25, 0x3c, 0xbf, 0xa9, 0xc0, 0x37, 0x7e, 0x4b, 0xbe, 0x91, 0x24, 0xdf, ++ 0x58, 0x4e, 0xb9, 0xb5, 0x8d, 0xc0, 0x06, 0xf2, 0x8d, 0xb7, 0xc9, 0xc7, ++ 0x3d, 0x73, 0x5f, 0xe4, 0x19, 0xff, 0x80, 0x01, 0xfa, 0xe4, 0x5d, 0xf1, ++ 0x65, 0x6a, 0x6a, 0x89, 0x07, 0x41, 0x3d, 0xa8, 0xf6, 0x87, 0xbc, 0xa8, ++ 0xd2, 0xdf, 0x29, 0xd6, 0xa5, 0x17, 0xf9, 0xc5, 0x8d, 0xf4, 0xb7, 0xed, ++ 0x13, 0x82, 0x2f, 0xa7, 0xac, 0xcd, 0xe4, 0x17, 0xaf, 0x26, 0xae, 0xc1, ++ 0x27, 0x47, 0x06, 0x23, 0x95, 0x10, 0x6e, 0xe1, 0xa0, 0xa1, 0x11, 0x2b, ++ 0x99, 0xc3, 0x98, 0xf5, 0x24, 0x37, 0x3b, 0x4e, 0x4b, 0xc2, 0x38, 0x3f, ++ 0x43, 0xdc, 0xd9, 0xc0, 0xda, 0xe5, 0x03, 0xaf, 0xd6, 0x5b, 0x47, 0x1a, ++ 0x1f, 0xb1, 0x8c, 0x1e, 0xfa, 0x5a, 0x5a, 0xe0, 0xa2, 0x92, 0xfc, 0xa0, ++ 0x9a, 0x1c, 0x63, 0x6b, 0x81, 0x63, 0x54, 0x1b, 0x58, 0x59, 0x01, 0x23, ++ 0x44, 0xe8, 0xe7, 0x3c, 0x1b, 0x02, 0x9b, 0xc8, 0x31, 0xde, 0x25, 0xc7, ++ 0xf8, 0x1e, 0x39, 0x46, 0x80, 0x1c, 0x63, 0x03, 0x39, 0x46, 0x80, 0x1c, ++ 0xe3, 0x7b, 0xe4, 0x18, 0xa5, 0xe4, 0x18, 0x3b, 0x6d, 0xcd, 0x8c, 0xaa, ++ 0x30, 0xf3, 0xa5, 0x0f, 0xab, 0xe6, 0x0b, 0x3c, 0x63, 0x3e, 0xcf, 0x33, ++ 0x2a, 0xe8, 0x13, 0x69, 0xe1, 0x19, 0xf3, 0x79, 0xdb, 0xbc, 0xa9, 0x70, ++ 0x2d, 0x35, 0xbd, 0x2c, 0x2f, 0xdf, 0x71, 0x36, 0x32, 0xcf, 0xd6, 0xcd, ++ 0x53, 0x8f, 0x59, 0xf1, 0x1b, 0x3f, 0xee, 0x4d, 0x54, 0xa2, 0x6b, 0xb1, ++ 0x52, 0x55, 0xc4, 0x85, 0xf7, 0x57, 0xc7, 0x51, 0x36, 0xd7, 0x47, 0x1d, ++ 0x0b, 0x7f, 0x81, 0xff, 0x0a, 0xca, 0xba, 0xf7, 0x61, 0xd6, 0xad, 0x8d, ++ 0x5c, 0x1d, 0xf9, 0x6b, 0x94, 0xf1, 0xd0, 0xef, 0x72, 0x9a, 0x0a, 0xd4, ++ 0x1a, 0xcd, 0xc8, 0xb9, 0x79, 0x75, 0x6d, 0xe0, 0x56, 0xae, 0x63, 0x29, ++ 0x63, 0x44, 0x38, 0xf2, 0x27, 0xab, 0xde, 0xc4, 0x75, 0x57, 0x78, 0xe0, ++ 0x67, 0xac, 0xaf, 0x63, 0xac, 0x57, 0xd0, 0xaf, 0xbb, 0x4d, 0x23, 0xce, ++ 0x74, 0x86, 0x97, 0x18, 0xe7, 0x2d, 0xf4, 0xc9, 0x4d, 0xa6, 0xbf, 0xd0, ++ 0x73, 0xba, 0x8e, 0x73, 0xf0, 0xaa, 0x2b, 0x18, 0xe7, 0xfb, 0xaf, 0x73, ++ 0x70, 0x57, 0xc2, 0x38, 0x34, 0xcf, 0x9c, 0xfb, 0x73, 0xf2, 0xcb, 0x32, ++ 0xbd, 0x29, 0xb0, 0xc9, 0x8d, 0x73, 0xc7, 0xd9, 0x92, 0x70, 0xb0, 0x36, ++ 0x31, 0xf8, 0xd4, 0x72, 0xc6, 0x79, 0xf3, 0x2a, 0x7c, 0x7d, 0x29, 0xf0, ++ 0xed, 0x08, 0x8c, 0xa3, 0x37, 0xa9, 0x54, 0x7c, 0x31, 0xb9, 0xd9, 0x5e, ++ 0x0f, 0x92, 0x41, 0x2b, 0xd6, 0xfe, 0x12, 0xe4, 0xf9, 0xb7, 0x9c, 0xed, ++ 0x73, 0xf9, 0x78, 0xbf, 0x95, 0xf1, 0xbe, 0x89, 0xf1, 0xbe, 0xcf, 0xd4, ++ 0x42, 0x0f, 0xab, 0xc1, 0x68, 0x19, 0xeb, 0x81, 0x56, 0xf2, 0x96, 0x0f, ++ 0xbc, 0x78, 0x99, 0x7c, 0xf0, 0x59, 0x56, 0x91, 0xc9, 0xa5, 0xf4, 0xa1, ++ 0xf7, 0x13, 0x86, 0xc9, 0xc8, 0xa2, 0xaf, 0x9d, 0x77, 0x36, 0x50, 0xa7, ++ 0x8b, 0x0b, 0xb1, 0xfe, 0x8d, 0xe9, 0x97, 0x0b, 0xfe, 0x27, 0x3d, 0x9f, ++ 0x37, 0xac, 0x1d, 0xf4, 0xdd, 0xf6, 0x46, 0xe6, 0x8c, 0xc5, 0xac, 0x91, ++ 0x3c, 0x12, 0x2b, 0x0a, 0x1b, 0xf5, 0x76, 0xe6, 0xa5, 0x76, 0xec, 0x21, ++ 0xdf, 0xe8, 0xb1, 0x63, 0x94, 0xc3, 0x98, 0x89, 0x68, 0xd1, 0x33, 0xe8, ++ 0x40, 0xb7, 0xcd, 0x0f, 0xf3, 0xe3, 0x56, 0xfb, 0x5f, 0xd4, 0xb0, 0xc1, ++ 0xfa, 0x5c, 0x6a, 0x2b, 0x8f, 0x16, 0x4f, 0x79, 0x7a, 0xd0, 0x35, 0x2b, ++ 0x58, 0x8e, 0x50, 0xd8, 0x6a, 0xc7, 0x88, 0x5d, 0x8a, 0xaf, 0x35, 0x6d, ++ 0x55, 0xdb, 0xb2, 0x6d, 0x18, 0xb7, 0x89, 0x0f, 0xb4, 0xf7, 0x8f, 0x28, ++ 0x3b, 0x56, 0xdb, 0x46, 0x9e, 0x40, 0xac, 0xb0, 0x77, 0xa8, 0xed, 0xd3, ++ 0x52, 0xeb, 0x75, 0xa8, 0xaf, 0x09, 0x9e, 0xd8, 0xfd, 0xaa, 0x43, 0xf0, ++ 0xc5, 0x26, 0xbe, 0x5c, 0xc4, 0x21, 0x93, 0x38, 0x74, 0x79, 0x8c, 0x6f, ++ 0x47, 0x4b, 0xa9, 0x07, 0xd5, 0x7a, 0x2c, 0xd0, 0x3a, 0x21, 0xf5, 0xdb, ++ 0xef, 0x2f, 0x74, 0x85, 0x58, 0x03, 0xb8, 0x31, 0x7e, 0xfe, 0xc2, 0x0b, ++ 0x2e, 0x0f, 0x2b, 0xe6, 0xaf, 0xb5, 0xb8, 0x63, 0x62, 0xa9, 0x6b, 0xbf, ++ 0x78, 0xa2, 0x02, 0x65, 0xd5, 0x82, 0xb5, 0x45, 0x5f, 0x52, 0xf2, 0xfe, ++ 0xce, 0xc5, 0x9a, 0xfa, 0xa9, 0xb5, 0xd2, 0xdf, 0xc4, 0xba, 0xc4, 0x6d, ++ 0xb8, 0x2d, 0x54, 0x8e, 0x4a, 0xfd, 0x3f, 0xe1, 0xae, 0x10, 0xb9, 0x9e, ++ 0xab, 0x2f, 0x91, 0x33, 0x5a, 0x5a, 0xe8, 0x17, 0x5c, 0xe4, 0x90, 0x3e, ++ 0xc6, 0xf5, 0x30, 0xb9, 0xde, 0x72, 0xc6, 0xb3, 0x33, 0xa9, 0x93, 0x3b, ++ 0xb2, 0x8e, 0x4d, 0x68, 0x0b, 0x43, 0xb4, 0xc3, 0x5a, 0x2f, 0xf6, 0x45, ++ 0xc8, 0x5f, 0xc9, 0x1d, 0x89, 0xd9, 0x8c, 0x2f, 0x46, 0x50, 0x05, 0xf9, ++ 0x62, 0xb9, 0xcb, 0x5f, 0xcf, 0x94, 0xe6, 0xf9, 0xeb, 0x25, 0x59, 0xcb, ++ 0x29, 0xcb, 0x99, 0x94, 0xba, 0xe8, 0x79, 0xeb, 0x7a, 0xca, 0xfa, 0x98, ++ 0xb2, 0x74, 0xf2, 0xd1, 0x8f, 0x8e, 0x68, 0xb9, 0x77, 0xbd, 0xb1, 0x9e, ++ 0x1a, 0x2f, 0x1a, 0x68, 0x9d, 0x8e, 0x20, 0xf9, 0x68, 0xc6, 0x30, 0x0e, ++ 0x6d, 0x55, 0xe4, 0xa3, 0x4d, 0xcc, 0x6f, 0x05, 0x3e, 0x5a, 0x4d, 0x3e, ++ 0x5a, 0xea, 0xf2, 0x51, 0x91, 0x2d, 0x7c, 0x74, 0x18, 0xfb, 0xe9, 0x23, ++ 0xdb, 0xec, 0x67, 0x2e, 0x4c, 0x55, 0xb7, 0x63, 0x94, 0xba, 0xad, 0x2a, ++ 0xe0, 0xea, 0xb5, 0x53, 0x23, 0x17, 0xd7, 0x22, 0xbf, 0x13, 0xc4, 0xd9, ++ 0x5b, 0x27, 0xa4, 0x2f, 0x1f, 0xa5, 0x8f, 0x9f, 0xb8, 0x10, 0xbd, 0xd2, ++ 0x4f, 0xdd, 0xca, 0x7a, 0x19, 0xcb, 0xba, 0x4e, 0x7e, 0x1d, 0x27, 0xf6, ++ 0x5c, 0xe2, 0xb4, 0xe4, 0xd7, 0x4d, 0x74, 0xf1, 0xfb, 0x5b, 0x39, 0xfe, ++ 0x8b, 0x8c, 0x39, 0x1f, 0xc7, 0xf7, 0xba, 0xe3, 0x0a, 0xc7, 0x3e, 0x77, ++ 0xa1, 0xc8, 0x83, 0x9d, 0x4b, 0xcf, 0x9c, 0x5e, 0xce, 0xb1, 0x9a, 0xd7, ++ 0x54, 0x90, 0x33, 0xcb, 0x7d, 0xc2, 0x83, 0x57, 0x96, 0x49, 0x5e, 0xf1, ++ 0xeb, 0x5b, 0x31, 0x40, 0x5f, 0x1a, 0xa0, 0x8f, 0xdd, 0x67, 0x4f, 0xf2, ++ 0x5a, 0x3b, 0xee, 0xcb, 0xae, 0x25, 0xa7, 0xfa, 0xa2, 0xde, 0xc3, 0xb4, ++ 0x45, 0x99, 0x1f, 0xe5, 0x72, 0xed, 0x0f, 0xf1, 0x86, 0xbf, 0x42, 0x3f, ++ 0xeb, 0xbf, 0xfb, 0x26, 0x52, 0xd8, 0x3f, 0xf1, 0x2d, 0x72, 0x61, 0x37, ++ 0x6f, 0xde, 0x2e, 0x1c, 0xbe, 0x8a, 0xb1, 0xf5, 0x77, 0x09, 0x43, 0xb8, ++ 0xe0, 0x8e, 0x45, 0x10, 0x6e, 0x61, 0x34, 0x5f, 0xa3, 0x1c, 0x94, 0x26, ++ 0xd0, 0xdb, 0xda, 0x64, 0xc4, 0xcf, 0xe2, 0x7e, 0x47, 0x7a, 0xca, 0xde, ++ 0x02, 0xcf, 0x90, 0xda, 0x57, 0xde, 0x0d, 0xb4, 0x14, 0x38, 0xe1, 0xba, ++ 0xec, 0x5b, 0x5f, 0xe8, 0x9b, 0x44, 0x0b, 0x79, 0x2e, 0xa0, 0x5a, 0x38, ++ 0xce, 0x41, 0x72, 0xb8, 0xa7, 0xcc, 0x17, 0x22, 0xa5, 0x0c, 0x26, 0x5f, ++ 0xa3, 0xc2, 0x3d, 0x66, 0x09, 0x52, 0x61, 0x07, 0x3b, 0x78, 0xdc, 0x43, ++ 0x1c, 0x7a, 0x8f, 0xfc, 0x64, 0x2a, 0x14, 0x22, 0x37, 0x26, 0xce, 0x7b, ++ 0x8e, 0x73, 0xbe, 0x5a, 0x3c, 0xea, 0x91, 0xf7, 0xee, 0xf9, 0x3e, 0xc3, ++ 0x33, 0x9f, 0xeb, 0x75, 0x08, 0x1f, 0x29, 0xf6, 0x1b, 0x08, 0xf2, 0x6e, ++ 0xbf, 0x3a, 0xa0, 0xc8, 0x0b, 0xe2, 0x20, 0x77, 0xdb, 0x65, 0xe6, 0xa2, ++ 0x84, 0x84, 0x4f, 0x3c, 0xd0, 0x8e, 0xbe, 0xcb, 0xda, 0xf6, 0xbe, 0x5a, ++ 0xed, 0xe8, 0x97, 0x49, 0x4a, 0xfa, 0x47, 0xfd, 0xb8, 0x7b, 0x74, 0x03, ++ 0xaa, 0xdc, 0xbe, 0xd7, 0x30, 0xe3, 0xd3, 0xc3, 0x7a, 0x72, 0xf0, 0x33, ++ 0x1f, 0xeb, 0xca, 0x4f, 0x56, 0x7d, 0x1b, 0xcd, 0xee, 0xf9, 0x21, 0xdc, ++ 0x3e, 0x11, 0x50, 0x9b, 0x27, 0x7c, 0xd8, 0xb0, 0xfd, 0xdb, 0x28, 0x69, ++ 0xec, 0xe2, 0xbc, 0xe4, 0xbc, 0x7c, 0xbf, 0x99, 0xf5, 0xa8, 0xcc, 0xaf, ++ 0x94, 0x39, 0x8c, 0x73, 0x6b, 0xd4, 0x31, 0x30, 0xea, 0x53, 0x3b, 0xed, ++ 0x7f, 0x70, 0x3e, 0xb9, 0x92, 0x38, 0x01, 0x39, 0x57, 0x2e, 0xef, 0xff, ++ 0x79, 0x4f, 0x92, 0xb5, 0x62, 0x37, 0x73, 0x6a, 0x29, 0x6e, 0x76, 0x9f, ++ 0xdf, 0x5b, 0x9a, 0x5f, 0x53, 0x92, 0xb5, 0x7a, 0x2b, 0xeb, 0x04, 0xb9, ++ 0x07, 0xc5, 0x73, 0xfe, 0xfc, 0x1e, 0x03, 0xf1, 0x85, 0x6e, 0x5c, 0x4d, ++ 0x23, 0xd4, 0x1a, 0xe2, 0x77, 0xdd, 0xa8, 0xcd, 0x2c, 0x2e, 0x6c, 0xd1, ++ 0x18, 0xc6, 0x5d, 0x76, 0x0e, 0x41, 0x4b, 0x67, 0xac, 0x50, 0x77, 0x4b, ++ 0xe4, 0xf9, 0xa0, 0xff, 0xf3, 0xcf, 0x0b, 0xd7, 0x22, 0xa7, 0x0e, 0x0a, ++ 0xb7, 0xfe, 0x43, 0xd7, 0xbf, 0x0a, 0xb9, 0xe6, 0xd3, 0xff, 0x12, 0x7b, ++ 0x27, 0x8c, 0xf6, 0x45, 0x1e, 0xf1, 0x9f, 0xbf, 0xc4, 0x9d, 0xd3, 0x43, ++ 0xbc, 0x2e, 0xf2, 0xfb, 0x58, 0x33, 0xf9, 0x54, 0x9b, 0xad, 0x63, 0xcf, ++ 0xa8, 0xe7, 0xc6, 0x52, 0xfc, 0xc8, 0x29, 0x5b, 0x32, 0x80, 0xda, 0xc4, ++ 0x10, 0xef, 0x57, 0x68, 0x25, 0x3f, 0x7e, 0xc8, 0x5c, 0x87, 0x0d, 0xd5, ++ 0x0e, 0x76, 0x27, 0x9e, 0x72, 0xba, 0x3b, 0x44, 0x87, 0x0a, 0xeb, 0x79, ++ 0xfe, 0x69, 0x53, 0xea, 0x6e, 0x1f, 0x6a, 0x17, 0x4b, 0x0f, 0x53, 0x1b, ++ 0x4b, 0xe2, 0xeb, 0xee, 0x98, 0xd5, 0xac, 0x27, 0xaa, 0x74, 0xbd, 0xf7, ++ 0x26, 0x4f, 0xed, 0xd8, 0xeb, 0xf4, 0xa7, 0x96, 0xc6, 0xcb, 0xaf, 0x15, ++ 0x75, 0x62, 0x92, 0x33, 0x3f, 0xe9, 0xe0, 0x8a, 0x41, 0x84, 0x1a, 0x2f, ++ 0xb7, 0x7f, 0x71, 0xde, 0x7d, 0x8c, 0x53, 0xa4, 0xaa, 0x2c, 0xe9, 0x71, ++ 0x19, 0x94, 0xd3, 0x87, 0x6f, 0x64, 0x87, 0x70, 0xcf, 0x44, 0xa1, 0x86, ++ 0xa0, 0x6f, 0xeb, 0x8d, 0x97, 0xd6, 0x76, 0xd7, 0x84, 0xd1, 0x55, 0x59, ++ 0x58, 0xdb, 0xbe, 0x69, 0xe9, 0x65, 0x77, 0x60, 0x2f, 0x75, 0xda, 0xeb, ++ 0xea, 0xb4, 0x03, 0x66, 0xe6, 0x92, 0xdc, 0x1e, 0xca, 0x0d, 0x58, 0xa2, ++ 0x37, 0xa3, 0x39, 0x40, 0xb9, 0x7b, 0x28, 0x77, 0xf7, 0x65, 0x72, 0xbb, ++ 0xcd, 0x4b, 0x72, 0x77, 0x4d, 0x18, 0x47, 0x3d, 0x05, 0xb9, 0xf7, 0x4e, ++ 0x17, 0x65, 0xa4, 0xb0, 0xad, 0x31, 0x85, 0xcc, 0xf5, 0xfb, 0x9c, 0x7d, ++ 0xae, 0x3e, 0x9e, 0x70, 0xcf, 0xaf, 0xaf, 0x5d, 0x60, 0x3c, 0xf0, 0xab, ++ 0x65, 0x32, 0x0e, 0x1a, 0xc8, 0x05, 0xe3, 0xe4, 0x82, 0x3a, 0xe3, 0x21, ++ 0xca, 0x18, 0x29, 0xf6, 0xe5, 0xb4, 0xb7, 0x36, 0x7b, 0x93, 0xe4, 0x8b, ++ 0x61, 0xff, 0xa6, 0x2f, 0xf4, 0x72, 0x36, 0xb0, 0xe6, 0xdc, 0x68, 0x6f, ++ 0x0d, 0xb4, 0xd9, 0x7e, 0x72, 0xb4, 0x45, 0x6a, 0xfd, 0x84, 0xf4, 0x74, ++ 0x24, 0x9e, 0x0b, 0xfc, 0x3f, 0x2b, 0xb5, 0xed, 0x2d, 0xcc, 0x3d, 0xd7, ++ 0xd0, 0xc6, 0x5d, 0x38, 0x94, 0xed, 0x53, 0xc9, 0x30, 0xc7, 0xb2, 0x25, ++ 0xb7, 0x20, 0xb0, 0x6d, 0xa2, 0x1d, 0x8b, 0xe8, 0x4f, 0x4b, 0xac, 0x43, ++ 0xd6, 0x0f, 0x6b, 0x1d, 0xe9, 0x91, 0x33, 0x87, 0x1d, 0xb5, 0x76, 0xb0, ++ 0x68, 0x3f, 0xec, 0xe6, 0x5e, 0xed, 0x44, 0xfe, 0x9d, 0x53, 0x40, 0x6d, ++ 0xe7, 0xbd, 0xdf, 0xb3, 0xe5, 0x9d, 0xee, 0x00, 0x56, 0x36, 0xe6, 0x7a, ++ 0x82, 0x48, 0xfe, 0x45, 0x10, 0x1a, 0xeb, 0xcb, 0x43, 0x78, 0x56, 0x8f, ++ 0xf8, 0x3b, 0xb2, 0x3e, 0xb5, 0xc9, 0x9e, 0x09, 0x6c, 0xb6, 0x83, 0x58, ++ 0x64, 0x69, 0xb9, 0x2d, 0xde, 0x58, 0xe8, 0x1a, 0x97, 0xd3, 0x65, 0xac, ++ 0xab, 0x32, 0x9d, 0x9c, 0x6f, 0x1e, 0x23, 0xf5, 0x29, 0x7f, 0x60, 0xe3, ++ 0x64, 0xcc, 0x1c, 0x70, 0x31, 0xf3, 0x29, 0xab, 0x36, 0xe3, 0x38, 0xe7, ++ 0xcc, 0xdc, 0xcf, 0xfc, 0xee, 0xef, 0x5f, 0x58, 0x6b, 0x33, 0x0d, 0xd8, ++ 0x49, 0x9e, 0xd6, 0x32, 0xd9, 0x80, 0xd0, 0x24, 0xf0, 0xf4, 0x68, 0x04, ++ 0x55, 0x13, 0xda, 0xd1, 0x3e, 0x6f, 0x27, 0xc6, 0x66, 0x5b, 0x31, 0x91, ++ 0x0d, 0x9c, 0x8f, 0x7a, 0x1c, 0xfc, 0x26, 0xe1, 0xc1, 0x8d, 0xe6, 0x13, ++ 0x2a, 0xb7, 0x44, 0xe1, 0x26, 0xf3, 0x3f, 0xaa, 0x33, 0x05, 0xfe, 0x2a, ++ 0x75, 0xcc, 0xed, 0x05, 0x4e, 0x1a, 0xd6, 0xe5, 0xbd, 0xe0, 0x0c, 0xb9, ++ 0x8f, 0xc2, 0x15, 0x2e, 0x66, 0xbf, 0x65, 0x35, 0xb3, 0x36, 0xb8, 0x89, ++ 0xfc, 0x74, 0x3b, 0xf1, 0xe6, 0x57, 0xe4, 0x0c, 0x2b, 0x1b, 0xb5, 0x9e, ++ 0x51, 0x4f, 0x2a, 0x2e, 0xdc, 0x34, 0x03, 0xad, 0xb3, 0xbd, 0xc0, 0x43, ++ 0xeb, 0x67, 0xf2, 0x1c, 0xf5, 0x9a, 0x19, 0xe1, 0x18, 0xac, 0xf1, 0x12, ++ 0x5a, 0xd4, 0xe3, 0x09, 0x61, 0xcc, 0x95, 0x73, 0xd2, 0x32, 0x67, 0x4a, ++ 0x99, 0x0b, 0x45, 0x27, 0xf2, 0xfb, 0xb4, 0x55, 0x97, 0xb9, 0x05, 0x87, ++ 0xec, 0x4e, 0xe1, 0x5d, 0x29, 0x20, 0x16, 0x5f, 0xae, 0xb6, 0x93, 0x67, ++ 0xc7, 0xa2, 0x6b, 0xbd, 0x64, 0x20, 0xbe, 0x7a, 0x73, 0x06, 0xdb, 0x55, ++ 0x61, 0x2f, 0x8f, 0xbb, 0x6e, 0x23, 0x03, 0xb4, 0x8c, 0x06, 0xce, 0x27, ++ 0x91, 0xef, 0x63, 0xad, 0x33, 0x7f, 0x8b, 0xae, 0xb0, 0x76, 0x48, 0x78, ++ 0x69, 0x2b, 0xf1, 0x38, 0xd5, 0xe1, 0xe3, 0x75, 0x89, 0xf5, 0x67, 0xad, ++ 0xab, 0x47, 0x90, 0x2b, 0x67, 0x9d, 0x42, 0x7d, 0x06, 0xdb, 0xb3, 0xc0, ++ 0x7a, 0xe6, 0xf2, 0xef, 0x9b, 0x9f, 0x39, 0x5d, 0x85, 0x77, 0x72, 0xdb, ++ 0x26, 0x15, 0x42, 0xba, 0x85, 0x91, 0x59, 0x5f, 0x70, 0xab, 0xdd, 0x84, ++ 0x74, 0xd6, 0x77, 0x99, 0x6c, 0xe3, 0xd0, 0x55, 0x1e, 0x0f, 0xd7, 0x79, ++ 0x37, 0x75, 0x55, 0xcc, 0xbb, 0xcf, 0xbb, 0xb9, 0xb2, 0x94, 0xeb, 0x3c, ++ 0x75, 0x44, 0xf2, 0xef, 0xdf, 0xba, 0xf9, 0x37, 0xc2, 0xb1, 0x22, 0xb6, ++ 0xd6, 0x29, 0x75, 0x70, 0x15, 0x75, 0x25, 0xef, 0xa4, 0x96, 0x5b, 0x6f, ++ 0x32, 0x9f, 0x6a, 0x91, 0x6e, 0x25, 0x39, 0x50, 0x5b, 0x08, 0x78, 0x3d, ++ 0xd8, 0xaf, 0x6b, 0xf1, 0xb5, 0x5e, 0x4d, 0xea, 0x22, 0x97, 0x93, 0xd7, ++ 0xcf, 0x74, 0x63, 0x24, 0x9b, 0xd7, 0x6f, 0x43, 0x26, 0xcf, 0xcf, 0x0d, ++ 0x97, 0x97, 0xcb, 0xfe, 0x80, 0x36, 0x3c, 0x60, 0x0b, 0x2f, 0x97, 0xf3, ++ 0x3f, 0xb7, 0xea, 0xa6, 0xfc, 0x9c, 0x9b, 0xc2, 0x39, 0xbd, 0x8d, 0xfe, ++ 0x58, 0x9c, 0x63, 0x9e, 0xb3, 0x6f, 0x22, 0x67, 0x2f, 0x27, 0x67, 0xdf, ++ 0xec, 0x95, 0x9c, 0x9d, 0xab, 0xf1, 0xa1, 0x1d, 0x0f, 0x91, 0xeb, 0xac, ++ 0x2b, 0xf0, 0xf6, 0xb3, 0x2e, 0x6f, 0x77, 0x9c, 0x5f, 0x9a, 0xc0, 0xad, ++ 0xe4, 0xec, 0x9f, 0x90, 0xb3, 0xef, 0xcc, 0x44, 0x71, 0x9e, 0x9c, 0xbd, ++ 0x33, 0x53, 0x83, 0x8f, 0xc9, 0xd9, 0xdf, 0x49, 0xfc, 0x1e, 0xf7, 0x16, ++ 0x7a, 0x83, 0xbb, 0xe2, 0x57, 0xd2, 0xdf, 0x3d, 0x8c, 0xdb, 0x80, 0xba, ++ 0x8d, 0xbc, 0xbd, 0x42, 0x7f, 0x1e, 0xfb, 0xbe, 0xc0, 0xdb, 0x6f, 0x25, ++ 0x7f, 0xdc, 0xea, 0xf6, 0xde, 0x4e, 0x59, 0x73, 0x8f, 0x08, 0x37, 0x95, ++ 0x9e, 0xe0, 0x60, 0xae, 0x86, 0xb9, 0xce, 0x4e, 0x74, 0x22, 0x3d, 0x89, ++ 0xa5, 0xf9, 0x9a, 0x51, 0xe6, 0x64, 0x34, 0xdf, 0x08, 0xcd, 0x9c, 0x51, ++ 0xc6, 0xf9, 0xb3, 0xe4, 0x89, 0x34, 0x61, 0xd2, 0x6b, 0x19, 0xb9, 0x77, ++ 0xbc, 0xd8, 0x5a, 0x23, 0x15, 0xfe, 0x9c, 0xf4, 0x06, 0xf3, 0x7d, 0xc1, ++ 0x60, 0xbe, 0x2f, 0xb8, 0x9f, 0xb5, 0x66, 0x7c, 0x5e, 0x91, 0x2b, 0x91, ++ 0xb3, 0x6f, 0xa0, 0x1f, 0x0e, 0x1a, 0xce, 0xc0, 0x46, 0x72, 0xf6, 0x52, ++ 0x72, 0xf6, 0x56, 0x9b, 0xb5, 0xc1, 0x6c, 0x1c, 0xa5, 0x86, 0xf4, 0xd6, ++ 0x9a, 0x19, 0x23, 0x5a, 0x34, 0xc7, 0xfc, 0xec, 0xa5, 0x9c, 0x6b, 0xe6, ++ 0x92, 0xe4, 0xa6, 0x7e, 0xac, 0x25, 0x4f, 0xdd, 0xe9, 0xf6, 0x2d, 0xdf, ++ 0xb0, 0x5e, 0x2b, 0xf4, 0x06, 0x9b, 0x57, 0x69, 0xfd, 0x74, 0xef, 0x3d, ++ 0xe4, 0x31, 0xfb, 0x58, 0x97, 0x32, 0x06, 0x1d, 0xe7, 0x18, 0xf9, 0xc3, ++ 0x55, 0x73, 0x79, 0xce, 0x2e, 0x75, 0xd9, 0x87, 0x66, 0x15, 0x92, 0xdb, ++ 0x2b, 0xd0, 0x39, 0xaa, 0x94, 0x97, 0xbc, 0xfd, 0x8e, 0x26, 0xd6, 0x07, ++ 0xe4, 0xed, 0x9b, 0xc9, 0xdb, 0x5f, 0xc9, 0x08, 0xde, 0xbd, 0x61, 0xed, ++ 0xa5, 0xbc, 0x9e, 0x44, 0x9e, 0xb7, 0xe7, 0x58, 0xcf, 0xdf, 0xc6, 0xf1, ++ 0x5e, 0x62, 0x3d, 0x7f, 0x52, 0x97, 0xe7, 0x02, 0xe7, 0x91, 0xdf, 0x3f, ++ 0x45, 0x5f, 0x78, 0xc5, 0xfa, 0xd8, 0xed, 0xf5, 0xfd, 0xad, 0xd5, 0x72, ++ 0x44, 0xeb, 0x7d, 0x9b, 0xfc, 0xf5, 0xa4, 0xf1, 0xb2, 0x6b, 0xdf, 0x61, ++ 0x53, 0xfc, 0x28, 0x63, 0x9d, 0x4a, 0x8b, 0x0e, 0x9f, 0xb5, 0xe6, 0x46, ++ 0x62, 0xcd, 0xaf, 0x22, 0x1f, 0xf7, 0x75, 0x99, 0xd2, 0xc2, 0x1e, 0x95, ++ 0x62, 0x9f, 0x9a, 0xd5, 0xd9, 0x9a, 0x7c, 0xbc, 0x34, 0x64, 0x0e, 0x90, ++ 0x23, 0xcb, 0x1e, 0x97, 0x90, 0xf4, 0xd7, 0x31, 0x46, 0x9e, 0xea, 0x9f, ++ 0x8f, 0x04, 0x6f, 0x65, 0x5e, 0x59, 0x3e, 0x2f, 0xfb, 0xfc, 0x72, 0x56, ++ 0xe8, 0x3b, 0x45, 0xee, 0xf9, 0xf9, 0x7e, 0xde, 0x83, 0xf9, 0x5e, 0x5e, ++ 0xfb, 0x1d, 0xd2, 0xcb, 0xab, 0xb9, 0xd4, 0xcb, 0xdb, 0xc3, 0x6b, 0x0f, ++ 0x7c, 0xa1, 0x97, 0x77, 0xd7, 0x04, 0x7e, 0x17, 0x6c, 0x2a, 0xc3, 0xe3, ++ 0x2b, 0x4a, 0x90, 0x0b, 0x69, 0x91, 0x51, 0xdc, 0x4f, 0x7e, 0x23, 0x7d, ++ 0x43, 0x5f, 0xbf, 0xc7, 0xab, 0x45, 0xde, 0x55, 0x15, 0x7c, 0xf6, 0x96, ++ 0xc0, 0x56, 0xfb, 0x16, 0x3c, 0x6a, 0xc7, 0xa2, 0x8f, 0x2a, 0x2f, 0x52, ++ 0x11, 0x79, 0xfe, 0x96, 0x40, 0x3b, 0xcf, 0x8d, 0x65, 0x8b, 0xfc, 0xa9, ++ 0x5d, 0xe6, 0x8a, 0xb6, 0xd1, 0x3c, 0x4e, 0xd5, 0x67, 0xa8, 0x1f, 0x95, ++ 0x5f, 0xdb, 0x72, 0xae, 0xd5, 0xb1, 0x3f, 0xbd, 0x70, 0xe6, 0x4a, 0xc1, ++ 0x04, 0x5d, 0xe2, 0x93, 0xf8, 0xd5, 0x4d, 0xdf, 0x6d, 0xc7, 0x11, 0x7b, ++ 0x39, 0xaa, 0x2c, 0xa9, 0x01, 0x3b, 0xdc, 0xb9, 0x4f, 0xb0, 0x76, 0xde, ++ 0x66, 0xa6, 0x9c, 0x8f, 0x56, 0xeb, 0x6d, 0xf3, 0xc8, 0xb1, 0xb2, 0x0a, ++ 0xa1, 0x91, 0x1c, 0x61, 0x03, 0xf1, 0x7f, 0xcf, 0x8c, 0xce, 0x1a, 0xb5, ++ 0x15, 0x77, 0x72, 0x9d, 0x7d, 0x5c, 0xcf, 0xbd, 0xd9, 0xbf, 0x42, 0xf2, ++ 0xeb, 0x3e, 0x3c, 0x37, 0x9a, 0x64, 0xee, 0x6a, 0x24, 0x26, 0xf8, 0x89, ++ 0x87, 0x15, 0xc8, 0xd0, 0x36, 0x29, 0x77, 0x6c, 0xc1, 0x72, 0xe6, 0x0d, ++ 0xd6, 0x02, 0xcf, 0x52, 0x6f, 0xcf, 0x50, 0x87, 0x3f, 0xb8, 0xf8, 0xbe, ++ 0x45, 0xb8, 0x4f, 0xb3, 0xbb, 0x2f, 0xee, 0xdf, 0xe6, 0xd9, 0x71, 0x72, ++ 0x64, 0x97, 0x6b, 0xf7, 0x92, 0x6b, 0x37, 0x70, 0xe9, 0xdd, 0x55, 0xe4, ++ 0xc6, 0xaf, 0x1a, 0x86, 0x39, 0x52, 0xe0, 0xc6, 0xde, 0x02, 0x37, 0x2e, ++ 0x25, 0x37, 0xf6, 0xba, 0xdc, 0xf8, 0xb5, 0x40, 0x9e, 0x1b, 0x07, 0xd4, ++ 0xc6, 0x89, 0x66, 0xe2, 0x1e, 0x2e, 0x94, 0xc1, 0x58, 0x38, 0xe7, 0x4d, ++ 0x11, 0xbb, 0xa7, 0x88, 0xb7, 0x33, 0x81, 0x9b, 0x6d, 0x77, 0x6f, 0x43, ++ 0xb0, 0x93, 0x3c, 0x8f, 0xf5, 0x47, 0xb0, 0x23, 0xbb, 0x2c, 0x78, 0x73, ++ 0xb6, 0x85, 0xcf, 0x45, 0x78, 0x14, 0x0c, 0x97, 0xf9, 0x5f, 0xbe, 0x96, ++ 0x81, 0x72, 0x94, 0xcb, 0x7a, 0xa2, 0xe8, 0x3a, 0x7e, 0x15, 0xee, 0x3d, ++ 0xde, 0xc4, 0xdf, 0x3a, 0xee, 0x9d, 0xcb, 0xe3, 0x65, 0x34, 0xb3, 0x3f, ++ 0x20, 0xfc, 0xb5, 0x65, 0x34, 0xff, 0x5b, 0xbf, 0xec, 0xf7, 0xbf, 0xcd, ++ 0xfd, 0x5d, 0xde, 0xdf, 0x4b, 0xde, 0xcf, 0x75, 0xfd, 0xb3, 0xac, 0x8b, ++ 0xf1, 0x52, 0x81, 0xf5, 0x8c, 0x01, 0x8f, 0x1e, 0x76, 0xd7, 0x95, 0x5f, ++ 0xcf, 0xa5, 0x3e, 0xf8, 0x65, 0x7d, 0x67, 0xbd, 0x14, 0xf8, 0x94, 0x61, ++ 0x70, 0xff, 0xa3, 0xd4, 0xc3, 0xf9, 0x35, 0xd2, 0x7f, 0x0e, 0x31, 0xce, ++ 0xe5, 0x7e, 0xe1, 0xe8, 0xbf, 0xbe, 0xc8, 0xd1, 0x3f, 0xbe, 0xf4, 0x0c, ++ 0xb1, 0x02, 0xfe, 0x57, 0xdd, 0x9e, 0xb9, 0xdc, 0x17, 0x72, 0xf5, 0xb4, ++ 0xc3, 0xe5, 0x9d, 0xc2, 0xe5, 0x1c, 0xb4, 0x36, 0xfe, 0xff, 0xd8, 0xad, ++ 0x18, 0x7f, 0xf7, 0x95, 0xcb, 0xbb, 0x67, 0xbd, 0xf1, 0x0e, 0x27, 0xef, ++ 0xd7, 0xe1, 0x60, 0x07, 0xe3, 0xe5, 0x61, 0x3e, 0xd3, 0x31, 0x4f, 0x9d, ++ 0xda, 0xbb, 0x5d, 0x3d, 0xdd, 0x3c, 0xbf, 0x8c, 0x35, 0x9b, 0xbc, 0x47, ++ 0x81, 0xf2, 0x59, 0x07, 0xb0, 0x71, 0x2c, 0x8a, 0x77, 0xcc, 0x00, 0xba, ++ 0x0a, 0x78, 0x57, 0x46, 0x9f, 0x7d, 0x3f, 0x1d, 0xa1, 0x0f, 0xc6, 0xa2, ++ 0xef, 0x90, 0x17, 0xa7, 0x7c, 0x3e, 0x3c, 0x38, 0x41, 0xbc, 0x24, 0x57, ++ 0x85, 0x2a, 0xf6, 0xef, 0xe4, 0xd9, 0xe2, 0xf7, 0x45, 0xac, 0xbf, 0x63, ++ 0xcd, 0x7b, 0x10, 0x45, 0x9a, 0x39, 0x25, 0x40, 0xec, 0x3c, 0x3c, 0xee, ++ 0xc1, 0x9d, 0x09, 0x45, 0x5c, 0x31, 0xf9, 0xbb, 0xbe, 0xe7, 0x03, 0xfc, ++ 0xd6, 0x99, 0x5a, 0x22, 0xcf, 0xcb, 0x1e, 0xa9, 0x4f, 0x9d, 0x1a, 0x5d, ++ 0xcf, 0xfd, 0x18, 0x7a, 0xff, 0x27, 0xa8, 0xef, 0x3d, 0x8f, 0x0f, 0x9d, ++ 0x1c, 0xaf, 0x9d, 0x63, 0x3c, 0xbd, 0x60, 0xc6, 0x22, 0x1e, 0x4e, 0x5e, ++ 0x72, 0xf2, 0x1d, 0xa6, 0xbc, 0xc3, 0xd3, 0x7a, 0x9f, 0x80, 0xd6, 0x73, ++ 0x4a, 0xc9, 0xde, 0xc7, 0x33, 0x4e, 0xaa, 0x5a, 0xc6, 0x55, 0xb8, 0x76, ++ 0x45, 0x7d, 0x5b, 0x29, 0xb4, 0xe6, 0x12, 0xa5, 0x9b, 0x1f, 0xa8, 0xff, ++ 0xe1, 0xe4, 0xc2, 0x9f, 0x3a, 0xef, 0xea, 0x45, 0xb9, 0x5a, 0xd4, 0xef, ++ 0xbd, 0xd8, 0x67, 0x64, 0x2c, 0xca, 0xbb, 0xcf, 0xe7, 0x71, 0xe7, 0xb8, ++ 0x0f, 0xad, 0x89, 0x5f, 0x39, 0xa9, 0xb0, 0xc8, 0x5c, 0xb1, 0x08, 0xe5, ++ 0x22, 0x3f, 0xff, 0x4e, 0xe0, 0xa7, 0x59, 0xa8, 0x0d, 0xb6, 0xf0, 0x74, ++ 0xf1, 0x8d, 0x31, 0x38, 0xb6, 0xf4, 0x69, 0x1d, 0xdc, 0x94, 0x18, 0xc0, ++ 0xb9, 0x44, 0xf2, 0x2f, 0xfc, 0xc4, 0xf0, 0xb3, 0x5e, 0x2d, 0xd7, 0xe0, ++ 0x8d, 0xaa, 0x40, 0x9d, 0xde, 0x5b, 0xe7, 0xe6, 0xb3, 0xd0, 0x57, 0xae, ++ 0x9d, 0xaa, 0xf0, 0xdf, 0x98, 0x15, 0x3c, 0x1b, 0xc3, 0xdc, 0x48, 0x0a, ++ 0x3e, 0x72, 0xca, 0xc1, 0x26, 0xad, 0xf3, 0x71, 0xa5, 0x45, 0xf6, 0xa9, ++ 0xa8, 0xba, 0x4d, 0xef, 0xc7, 0x93, 0xa6, 0x91, 0x6c, 0x51, 0xcb, 0xfc, ++ 0x6d, 0xd9, 0xa2, 0xec, 0x24, 0xe3, 0x40, 0xcb, 0x9d, 0xf5, 0x96, 0xa1, ++ 0x66, 0x95, 0xde, 0x56, 0xe6, 0xd5, 0xfa, 0xff, 0x94, 0xb5, 0xc7, 0xa6, ++ 0x6c, 0x2e, 0xf0, 0x81, 0xc1, 0xfc, 0xfb, 0x88, 0xc8, 0x4b, 0x17, 0x7a, ++ 0xd0, 0x63, 0xd8, 0x3c, 0xe2, 0xac, 0x3d, 0x9d, 0xd0, 0x22, 0x8f, 0xab, ++ 0x94, 0xec, 0x5b, 0x8c, 0xef, 0x85, 0x1e, 0x9d, 0x65, 0x1e, 0x6c, 0xcd, ++ 0x7a, 0x70, 0x95, 0xeb, 0xcb, 0x69, 0xca, 0x3c, 0x80, 0xb2, 0x71, 0x67, ++ 0xed, 0x4e, 0x53, 0xeb, 0x3f, 0xeb, 0x4d, 0xfd, 0xf7, 0x1a, 0xea, 0x6d, ++ 0x83, 0xd2, 0x7a, 0xce, 0xab, 0x01, 0x9c, 0xe6, 0x1a, 0xbe, 0x9f, 0xd0, ++ 0xe2, 0xdf, 0x55, 0x5a, 0xfb, 0xb7, 0xe8, 0xcf, 0x5e, 0x2b, 0xc8, 0x79, ++ 0x6a, 0xf1, 0x69, 0xc8, 0xfb, 0x89, 0x28, 0xce, 0x9a, 0xa9, 0xc0, 0xc6, ++ 0xba, 0x06, 0xf2, 0xc1, 0x65, 0xcc, 0xb3, 0xba, 0xbb, 0x97, 0xe3, 0x40, ++ 0xb6, 0x94, 0x18, 0x18, 0x77, 0x7b, 0x11, 0x9e, 0x91, 0x0a, 0x35, 0x93, ++ 0x8e, 0x99, 0xad, 0xf8, 0x2f, 0xc8, 0xb9, 0x78, 0x77, 0x00, 0x15, 0xe3, ++ 0xbf, 0x74, 0x2a, 0x75, 0xbd, 0x79, 0x44, 0x71, 0xdc, 0xc7, 0x96, 0x51, ++ 0xc7, 0x7c, 0x8e, 0x3e, 0xfa, 0x00, 0x71, 0xeb, 0xb6, 0x91, 0x08, 0x9f, ++ 0xaf, 0xc4, 0xb5, 0xe3, 0xd2, 0x2f, 0xbc, 0xb2, 0xd0, 0x2f, 0x54, 0xf4, ++ 0x03, 0xfa, 0xd1, 0x74, 0x05, 0x52, 0x1c, 0xe3, 0xdd, 0x74, 0x05, 0x0e, ++ 0xd0, 0x7f, 0xcb, 0x75, 0xfa, 0x17, 0xe3, 0x3e, 0xe5, 0x72, 0x82, 0xbf, ++ 0x25, 0x87, 0x92, 0xe3, 0x9b, 0x56, 0x74, 0x46, 0x2d, 0x72, 0xdf, 0x17, ++ 0x33, 0x5e, 0x0e, 0xb8, 0xbd, 0xe9, 0x30, 0xe7, 0x57, 0x89, 0x13, 0x63, ++ 0x52, 0x2f, 0xb6, 0x5c, 0xef, 0x2f, 0xec, 0x67, 0x78, 0x9b, 0xfc, 0x6d, ++ 0xed, 0xb8, 0x72, 0xf7, 0x7b, 0x7c, 0xb2, 0x6a, 0x50, 0xab, 0xc1, 0xf5, ++ 0x38, 0x1a, 0x92, 0x7e, 0xd1, 0x7f, 0xc0, 0xa1, 0x50, 0x03, 0x0e, 0x72, ++ 0x5e, 0xef, 0xa5, 0xff, 0x98, 0x75, 0x56, 0x54, 0xf8, 0x17, 0xae, 0x1a, ++ 0x2f, 0xe1, 0x98, 0x6b, 0xb1, 0xc1, 0xdc, 0x88, 0x57, 0x42, 0xc2, 0xb7, ++ 0xfd, 0xbc, 0xc7, 0x87, 0xe1, 0xe9, 0x90, 0xfb, 0x6e, 0xe7, 0xe0, 0xe7, ++ 0xe6, 0xf6, 0x87, 0xe6, 0x94, 0x8f, 0xe1, 0x7f, 0x7b, 0x4e, 0x7e, 0xf2, ++ 0x0c, 0x9d, 0x9c, 0xe3, 0x24, 0x3e, 0xa2, 0xec, 0xd4, 0x74, 0x5e, 0xe6, ++ 0x68, 0x36, 0x2f, 0xf7, 0xa0, 0x1d, 0xeb, 0xaf, 0xf1, 0x8a, 0xfc, 0x90, ++ 0xec, 0x3f, 0xfa, 0x77, 0x8e, 0x41, 0xe6, 0x38, 0xce, 0xba, 0xdc, 0xac, ++ 0x43, 0x6b, 0x88, 0xf6, 0xb2, 0x65, 0x0c, 0x8d, 0x35, 0xb0, 0x3c, 0x1b, ++ 0xc1, 0xca, 0x11, 0x67, 0x20, 0x62, 0xc9, 0x79, 0xc7, 0xa9, 0x5a, 0xa3, ++ 0x47, 0x5e, 0x67, 0xdc, 0x0e, 0x65, 0xfd, 0xd4, 0xc1, 0x30, 0x4e, 0xa4, ++ 0xeb, 0x89, 0xbf, 0x1e, 0x44, 0x59, 0x63, 0x9e, 0xf1, 0x0e, 0x63, 0x26, ++ 0xfd, 0x3c, 0x63, 0xc1, 0x8f, 0xe1, 0x6c, 0x85, 0x9a, 0x4e, 0x7f, 0x77, ++ 0x91, 0xe0, 0xdb, 0x10, 0xeb, 0x89, 0x86, 0x11, 0x99, 0xab, 0x33, 0x50, ++ 0x49, 0x39, 0x0f, 0x52, 0xce, 0xf4, 0x6a, 0xbd, 0x73, 0x48, 0x89, 0xce, ++ 0x42, 0x38, 0x9c, 0x3d, 0x4d, 0x7e, 0x21, 0x7a, 0x5b, 0x58, 0x24, 0x7d, ++ 0xfc, 0x83, 0xac, 0xd3, 0x5f, 0x29, 0xc8, 0x79, 0x28, 0xbb, 0x80, 0xe9, ++ 0xb4, 0xe3, 0x7e, 0x1f, 0x62, 0xae, 0x1a, 0x66, 0xdd, 0x9a, 0x49, 0x87, ++ 0x31, 0x92, 0xae, 0xef, 0x1c, 0x51, 0xbe, 0x42, 0x4f, 0xbe, 0x5b, 0xf6, ++ 0xa9, 0xbb, 0xf7, 0x0c, 0xf2, 0xd9, 0xc1, 0x8b, 0xdf, 0x45, 0x47, 0xf9, ++ 0x3d, 0x13, 0xf9, 0xf7, 0x36, 0x65, 0xb4, 0x9d, 0xd4, 0xff, 0x3a, 0xe7, ++ 0x52, 0x22, 0xfb, 0xd0, 0x70, 0x72, 0x6c, 0x2d, 0x86, 0xcc, 0x1f, 0x61, ++ 0x17, 0xd7, 0x3d, 0x4c, 0x7d, 0x8e, 0xdb, 0xb2, 0x37, 0x22, 0x4e, 0xec, ++ 0x91, 0xf7, 0x9b, 0x4f, 0x59, 0xc7, 0xc9, 0xf5, 0x0e, 0x33, 0x66, 0x6e, ++ 0x4f, 0xd4, 0xb7, 0xbf, 0x44, 0xbf, 0x4b, 0x7e, 0x4d, 0xf6, 0x1f, 0xf8, ++ 0x30, 0x32, 0x71, 0x2f, 0xa6, 0xaa, 0xeb, 0xcf, 0x3f, 0x45, 0x4c, 0x38, ++ 0x4a, 0x9c, 0xf2, 0x11, 0x13, 0xaa, 0x26, 0x3c, 0x85, 0xf7, 0xe9, 0x26, ++ 0x7f, 0xd7, 0x2f, 0xcc, 0xe0, 0xe7, 0xd4, 0x8b, 0xcc, 0x2f, 0x16, 0x9f, ++ 0x81, 0xdc, 0x9b, 0xef, 0x1d, 0xeb, 0x33, 0x3d, 0x38, 0x73, 0x65, 0xbe, ++ 0x77, 0xe7, 0x65, 0x0e, 0xdf, 0x9d, 0xae, 0x0f, 0x0d, 0x89, 0xec, 0x0e, ++ 0x2d, 0x92, 0xa2, 0xad, 0x0e, 0xb9, 0xdc, 0xfe, 0x59, 0x2b, 0x96, 0x91, ++ 0xfd, 0x88, 0x95, 0xf0, 0xd1, 0xf7, 0x87, 0x4c, 0xd9, 0x2f, 0x12, 0x09, ++ 0x6e, 0xa2, 0x0d, 0x87, 0xec, 0xfa, 0xe6, 0x98, 0xda, 0x89, 0x33, 0x05, ++ 0x8c, 0xf5, 0xf1, 0xde, 0xe1, 0xb4, 0xd6, 0xf9, 0x20, 0xea, 0xdb, 0xf7, ++ 0xe2, 0xeb, 0x48, 0x56, 0xd7, 0x77, 0x8d, 0x21, 0x66, 0xde, 0x01, 0xe1, ++ 0x75, 0x79, 0x59, 0xb5, 0x19, 0x82, 0xfa, 0xe2, 0x4f, 0x9d, 0xe5, 0xfa, ++ 0x43, 0x18, 0x23, 0x27, 0xad, 0x6b, 0xd4, 0x17, 0xbe, 0x57, 0xb8, 0x96, ++ 0x7f, 0x17, 0x27, 0xfe, 0x52, 0x41, 0x1d, 0x94, 0xc1, 0xb7, 0x98, 0xe3, ++ 0x89, 0x2e, 0xb2, 0x32, 0xc7, 0xd3, 0xb8, 0x87, 0xfe, 0x36, 0x96, 0x55, ++ 0x30, 0x6b, 0x4f, 0xa3, 0x57, 0xf2, 0x17, 0x9f, 0x69, 0x49, 0x87, 0xc8, ++ 0x33, 0x22, 0xe4, 0x1d, 0xb1, 0xe8, 0x20, 0xd7, 0xd7, 0x42, 0x2c, 0x18, ++ 0x26, 0x86, 0xa4, 0x42, 0x21, 0xc6, 0x6b, 0x88, 0xe7, 0x97, 0xb9, 0xff, ++ 0xdf, 0x20, 0xb5, 0x57, 0xdd, 0x94, 0xec, 0x09, 0x38, 0x80, 0xd3, 0x63, ++ 0x39, 0x1c, 0x4e, 0x24, 0xb1, 0xa7, 0x9a, 0xf6, 0xb3, 0x97, 0xb8, 0xfd, ++ 0x0a, 0xa9, 0xf1, 0x36, 0x4f, 0xf4, 0xb1, 0xb6, 0x74, 0xb0, 0x3e, 0xe1, ++ 0xa9, 0x95, 0x7d, 0x31, 0xd3, 0xac, 0xf5, 0xc6, 0x58, 0xa9, 0xdd, 0x63, ++ 0x7e, 0x0b, 0xe6, 0x62, 0xc1, 0xce, 0x21, 0xbc, 0x38, 0x25, 0x79, 0xee, ++ 0x34, 0x6b, 0x12, 0xd1, 0x8f, 0x07, 0x95, 0x8c, 0xb5, 0x06, 0xb7, 0xf7, ++ 0x57, 0xfd, 0x95, 0x15, 0x53, 0x45, 0x6e, 0x27, 0x75, 0x62, 0x25, 0x82, ++ 0xd4, 0xd7, 0xa9, 0x44, 0x9e, 0x77, 0xc9, 0xfb, 0x7d, 0xbf, 0x9e, 0x5f, ++ 0x67, 0x3c, 0xa3, 0x30, 0xd4, 0x74, 0xf9, 0x7b, 0x2c, 0xf9, 0x5f, 0x87, ++ 0xe2, 0xbb, 0xac, 0x62, 0x5f, 0xff, 0xbb, 0xce, 0x19, 0xd9, 0xc3, 0xe9, ++ 0x69, 0xaf, 0x90, 0xbd, 0x8f, 0x53, 0x17, 0xf5, 0x2b, 0x3a, 0x9d, 0x77, ++ 0xf2, 0xfb, 0xd6, 0x8b, 0xef, 0xbc, 0xb5, 0xde, 0x77, 0x55, 0x3d, 0xf3, ++ 0x09, 0xfd, 0xaa, 0xda, 0x87, 0xc1, 0x06, 0x74, 0x2d, 0xb7, 0x7c, 0x1d, ++ 0x9f, 0xd8, 0x6b, 0xc9, 0x95, 0xdf, 0x73, 0x70, 0x65, 0x0b, 0xbc, 0xba, ++ 0x9c, 0x9f, 0x72, 0x92, 0x21, 0xf9, 0x3e, 0x5f, 0x21, 0xf1, 0xf0, 0x53, ++ 0x3b, 0xe7, 0xac, 0x58, 0x92, 0xe7, 0x8a, 0xbf, 0x4c, 0xcb, 0xbb, 0xc5, ++ 0x94, 0xc3, 0x1a, 0x7f, 0xe1, 0x1d, 0x6f, 0x1f, 0xfe, 0x91, 0xfc, 0xf4, ++ 0xad, 0x31, 0x1f, 0x82, 0xba, 0xac, 0x65, 0x2d, 0xaa, 0x56, 0x19, 0xc9, ++ 0xf7, 0x88, 0x8b, 0x0b, 0x53, 0x45, 0xbf, 0xa8, 0xfe, 0xca, 0xca, 0x29, ++ 0x45, 0x59, 0x95, 0x28, 0xe5, 0x3a, 0x7f, 0x66, 0x7a, 0x11, 0x2d, 0xd4, ++ 0x57, 0x5e, 0xce, 0x53, 0xf6, 0x99, 0x08, 0x07, 0x8e, 0x65, 0x8e, 0x57, ++ 0xe4, 0xfb, 0x6e, 0x21, 0xe2, 0xe8, 0x30, 0x0e, 0xa5, 0xeb, 0xe3, 0xe7, ++ 0x64, 0xdf, 0x13, 0x6b, 0xbd, 0x33, 0x18, 0xc6, 0x78, 0xba, 0x88, 0xa1, ++ 0x11, 0xf9, 0xff, 0x01, 0xe9, 0x67, 0xb9, 0x18, 0x19, 0xf5, 0x68, 0xa9, ++ 0xa8, 0xe7, 0xba, 0x0a, 0xe1, 0x19, 0x83, 0xd9, 0x58, 0xa4, 0x8c, 0x64, ++ 0xe0, 0x76, 0x33, 0xef, 0x1f, 0xb5, 0x33, 0x25, 0x88, 0x2e, 0x96, 0xbc, ++ 0x2c, 0x39, 0xd9, 0xc7, 0x9c, 0xbc, 0x04, 0xc9, 0x25, 0x3e, 0xbc, 0xaa, ++ 0x8b, 0x3e, 0xde, 0x2c, 0xea, 0xc3, 0x9c, 0xc7, 0x7e, 0x27, 0xd7, 0x2e, ++ 0xbe, 0x54, 0x82, 0x03, 0x0d, 0xd3, 0xce, 0x54, 0x58, 0xd6, 0xee, 0xc5, ++ 0x51, 0xe2, 0x2b, 0xae, 0x8c, 0x45, 0x8e, 0x32, 0x67, 0x0f, 0xe9, 0x45, ++ 0x1f, 0xff, 0x46, 0x61, 0x9e, 0x7a, 0xe7, 0x2c, 0xbe, 0xcb, 0xef, 0xb5, ++ 0x91, 0x3d, 0x2a, 0x3f, 0xde, 0x8a, 0x19, 0x4f, 0xe5, 0xa5, 0x3e, 0xe7, ++ 0xb3, 0xe4, 0x62, 0x73, 0xbc, 0x2e, 0xb2, 0x42, 0xf4, 0xcf, 0x32, 0xa9, ++ 0x5b, 0x43, 0x70, 0xe3, 0x45, 0xde, 0xd9, 0x92, 0xe4, 0x8c, 0xcb, 0x9e, ++ 0x0a, 0x2f, 0x0e, 0x5c, 0xdc, 0xa3, 0x96, 0xc7, 0xaf, 0x72, 0x9e, 0xdf, ++ 0x94, 0x78, 0xe1, 0xfa, 0x00, 0x7e, 0xe7, 0x9c, 0x09, 0x2f, 0x23, 0x26, ++ 0x88, 0x4d, 0x9f, 0x77, 0x39, 0xa9, 0x97, 0xfc, 0x44, 0x74, 0x56, 0x23, ++ 0x71, 0x60, 0x5f, 0x5c, 0x47, 0xae, 0x1b, 0x1d, 0xb2, 0xb7, 0xae, 0xb0, ++ 0x37, 0x27, 0x46, 0xac, 0xf9, 0x12, 0xba, 0xa4, 0xd8, 0xc2, 0x32, 0xfa, ++ 0x57, 0x03, 0x75, 0x10, 0x0a, 0x6e, 0x99, 0x94, 0xf7, 0x2d, 0x3e, 0x1c, ++ 0x18, 0x89, 0x99, 0x77, 0x91, 0x4b, 0x1e, 0x1a, 0x71, 0x9c, 0xd7, 0x4c, ++ 0x6c, 0x0f, 0x32, 0xbf, 0x3f, 0x49, 0x3e, 0x41, 0xbe, 0x11, 0x2d, 0x53, ++ 0xf5, 0x91, 0x6b, 0x98, 0xeb, 0x87, 0x88, 0x19, 0x8f, 0xce, 0x01, 0x47, ++ 0xe7, 0xca, 0x61, 0x8f, 0xcb, 0xbb, 0xd7, 0x72, 0x8c, 0x3c, 0xd6, 0xc0, ++ 0xb9, 0x2f, 0xa6, 0x1c, 0x3f, 0x16, 0x1d, 0x6f, 0x46, 0xf9, 0x23, 0x0a, ++ 0x9b, 0x8c, 0x66, 0x04, 0x8e, 0x57, 0x32, 0xff, 0xfa, 0x71, 0xb6, 0x89, ++ 0x36, 0x7e, 0xac, 0xb8, 0x0e, 0xc1, 0x31, 0x1f, 0x1e, 0x98, 0xd0, 0x61, ++ 0xd3, 0x7f, 0xe7, 0x6c, 0x79, 0xe7, 0x5e, 0xe1, 0x62, 0xe9, 0x42, 0x61, ++ 0x2f, 0x2a, 0x71, 0x2d, 0x72, 0x42, 0x55, 0xe2, 0xc3, 0xf1, 0xdc, 0x95, ++ 0x65, 0x70, 0x7e, 0xba, 0xdc, 0x32, 0x3a, 0x77, 0xd1, 0xff, 0x57, 0xae, ++ 0x88, 0xb0, 0xce, 0x71, 0x9c, 0x4f, 0xd6, 0x48, 0xad, 0xfd, 0x0b, 0xd6, ++ 0xda, 0xc5, 0xda, 0x4a, 0xef, 0xb9, 0x4f, 0xa5, 0x36, 0x06, 0xe1, 0x7c, ++ 0x5c, 0x66, 0x39, 0xbf, 0x29, 0xb1, 0x0c, 0x3e, 0x1f, 0xa5, 0xae, 0x1c, ++ 0xe7, 0xed, 0x26, 0xc7, 0xc9, 0x34, 0xc5, 0x3a, 0x43, 0xde, 0x10, 0x8e, ++ 0xd7, 0xc9, 0xfb, 0x51, 0x0f, 0x3e, 0x34, 0xf4, 0xc8, 0x2e, 0xc8, 0x3e, ++ 0x07, 0xe2, 0xfd, 0x12, 0x2d, 0x29, 0x7b, 0x8d, 0xda, 0xec, 0xc5, 0x78, ++ 0x72, 0x76, 0x0d, 0xba, 0x4a, 0xe0, 0xf6, 0xe8, 0x1d, 0x13, 0xaf, 0x2f, ++ 0x87, 0xe4, 0x70, 0xa3, 0xf9, 0x3e, 0xd6, 0x94, 0xb3, 0xd9, 0x03, 0xb8, ++ 0x7b, 0x1c, 0x7e, 0x3f, 0x6b, 0x70, 0xff, 0xb8, 0xf3, 0xcb, 0x88, 0x95, ++ 0x23, 0x46, 0x3a, 0x4e, 0xf9, 0x9a, 0xfa, 0x48, 0xd0, 0xad, 0x61, 0x4e, ++ 0x4a, 0x4d, 0xd0, 0xf3, 0x21, 0xaa, 0x71, 0x62, 0x3a, 0x79, 0xa5, 0x17, ++ 0x46, 0xdb, 0x31, 0x15, 0xc2, 0x8f, 0xb9, 0xc6, 0x27, 0xb2, 0xc2, 0x59, ++ 0xfe, 0xde, 0xda, 0x3c, 0xbe, 0x14, 0x3f, 0x9d, 0x0d, 0xe3, 0x84, 0xad, ++ 0x93, 0x33, 0x41, 0x2d, 0xb2, 0x9c, 0xaa, 0x2a, 0xce, 0x75, 0x91, 0xd7, ++ 0x8b, 0x8d, 0x09, 0xd9, 0xa3, 0xa7, 0xf7, 0x54, 0x28, 0x2c, 0x2d, 0x83, ++ 0x7e, 0x7e, 0x3f, 0xd0, 0x1b, 0xb0, 0x8c, 0x85, 0x63, 0xca, 0xe8, 0xfc, ++ 0xc0, 0x1b, 0xc6, 0x8f, 0x89, 0x45, 0xdf, 0xcf, 0xca, 0xde, 0x34, 0xe2, ++ 0x0d, 0x73, 0x67, 0x9a, 0xb8, 0xe6, 0xa9, 0xad, 0xc4, 0x41, 0xc6, 0xce, ++ 0x49, 0xb3, 0x94, 0x78, 0x25, 0x7b, 0xd5, 0x04, 0xeb, 0x73, 0xd6, 0x71, ++ 0xf2, 0xf6, 0xa7, 0xf4, 0x7c, 0x1f, 0xc1, 0x9c, 0x89, 0x5c, 0xf6, 0x9e, ++ 0x3b, 0x4c, 0x8c, 0xaf, 0x6f, 0x8f, 0xa8, 0x97, 0x9d, 0xe4, 0xd7, 0x94, ++ 0x60, 0x19, 0xfd, 0x52, 0xd6, 0xca, 0xd8, 0x9e, 0x28, 0xe6, 0x17, 0xd6, ++ 0xbd, 0x21, 0xad, 0x3d, 0x55, 0xf0, 0xc7, 0x45, 0xc4, 0xa7, 0x07, 0xc9, ++ 0x11, 0xca, 0xc6, 0x25, 0xaf, 0x90, 0x83, 0xab, 0xb5, 0xe4, 0xc5, 0xc2, ++ 0x21, 0xfc, 0xd8, 0x1b, 0x12, 0xdf, 0x08, 0x71, 0x7d, 0x41, 0x9f, 0xec, ++ 0x3d, 0x7b, 0x32, 0x2b, 0x79, 0x5d, 0x70, 0xa1, 0x38, 0x5e, 0x04, 0x35, ++ 0xee, 0xfe, 0xdc, 0x67, 0xad, 0x8f, 0x47, 0x42, 0x1c, 0xdb, 0x19, 0xf0, ++ 0xb0, 0xae, 0xf7, 0xd3, 0xbf, 0x6e, 0x6d, 0xd2, 0x7b, 0xd6, 0x7a, 0xb5, ++ 0xde, 0xf3, 0x2a, 0xd6, 0x35, 0xaf, 0xb4, 0xe6, 0x43, 0xea, 0x72, 0x39, ++ 0x7f, 0x5f, 0x29, 0x3d, 0x7f, 0xe1, 0x08, 0x0f, 0xb8, 0x6b, 0x7a, 0xd3, ++ 0xdd, 0x9f, 0xe3, 0x21, 0x36, 0xb6, 0xa4, 0x2b, 0x71, 0x76, 0x0c, 0x3a, ++ 0x23, 0x18, 0x2f, 0x72, 0x1e, 0x5d, 0x21, 0x23, 0xd9, 0x0a, 0x89, 0x05, ++ 0xad, 0x4b, 0xf8, 0xd4, 0x22, 0xe2, 0xf3, 0xf4, 0x98, 0xe4, 0x1b, 0x25, ++ 0x5c, 0x25, 0x55, 0x65, 0xf5, 0xe2, 0xa3, 0xd5, 0xc0, 0xcb, 0x23, 0xf9, ++ 0xbd, 0x0d, 0x9d, 0xf6, 0x05, 0x07, 0x65, 0xf9, 0x7d, 0x23, 0xf7, 0xb9, ++ 0xfb, 0x41, 0x44, 0x7e, 0x9f, 0xbb, 0xd7, 0xb7, 0x92, 0xe7, 0x58, 0x7f, ++ 0xf7, 0x93, 0x7b, 0x36, 0x67, 0xf3, 0x7b, 0x7d, 0xcd, 0x8f, 0xe9, 0xfb, ++ 0xc7, 0xc8, 0x5b, 0x0f, 0x22, 0xbf, 0xb7, 0xa1, 0xae, 0xb0, 0xdf, 0x23, ++ 0x96, 0x69, 0x53, 0x5b, 0xdc, 0xfd, 0x63, 0xbf, 0x60, 0xbc, 0xb5, 0xaa, ++ 0x4d, 0xb3, 0x1b, 0xd4, 0xe6, 0xd9, 0xad, 0x6a, 0x67, 0x56, 0x7a, 0x03, ++ 0x3f, 0xb7, 0xf6, 0x8e, 0xef, 0x50, 0x5b, 0xa6, 0x3b, 0x14, 0xf9, 0x6d, ++ 0xc8, 0x6f, 0x75, 0xaa, 0xad, 0xb3, 0xf9, 0x1e, 0x7e, 0x1b, 0xeb, 0xb8, ++ 0x2d, 0xb6, 0xf8, 0xc3, 0xb3, 0xd6, 0xe6, 0x11, 0xf9, 0xff, 0xb1, 0x70, ++ 0x70, 0xdb, 0xa4, 0xd6, 0xb5, 0x5e, 0x39, 0xce, 0x35, 0x89, 0xff, 0x23, ++ 0xf6, 0x70, 0x9e, 0x48, 0xe8, 0xc4, 0x85, 0x4a, 0x74, 0xb3, 0x06, 0x19, ++ 0x34, 0xaf, 0xa6, 0x3d, 0xdc, 0x5e, 0x22, 0xd7, 0x24, 0x7b, 0x52, 0xc4, ++ 0x5f, 0x91, 0x2a, 0xe3, 0x1c, 0xfe, 0x17, 0xe7, 0xbf, 0xa7, 0xb0, 0xae, ++ 0xad, 0xb2, 0x67, 0xa3, 0x04, 0x29, 0x59, 0x43, 0x86, 0xeb, 0x3d, 0x3c, ++ 0x72, 0x69, 0x5d, 0x85, 0xfd, 0xc5, 0xe6, 0x1e, 0xa5, 0xf5, 0x17, 0xf6, ++ 0x30, 0x2f, 0x9c, 0x55, 0x5a, 0x6e, 0x10, 0x82, 0x0b, 0xf9, 0x75, 0x5d, ++ 0x5b, 0x58, 0xd7, 0x4a, 0xae, 0x6b, 0x93, 0xcb, 0xdd, 0x7f, 0x61, 0xcd, ++ 0x8d, 0xb4, 0xaa, 0xb6, 0x59, 0xe9, 0x9d, 0xca, 0xda, 0x64, 0x1d, 0xe3, ++ 0x4e, 0xb9, 0x2e, 0xef, 0xd0, 0x64, 0x1f, 0x9f, 0xec, 0xa5, 0x93, 0x3d, ++ 0x15, 0xc5, 0x75, 0x49, 0x4e, 0x5f, 0x1c, 0xdc, 0x30, 0x19, 0x0a, 0xae, ++ 0x9f, 0x74, 0x9c, 0x57, 0xcc, 0x86, 0xa0, 0xac, 0xe5, 0x84, 0x29, 0x6b, ++ 0x91, 0xbd, 0x39, 0xc5, 0xf5, 0xfc, 0x69, 0x61, 0x3d, 0x62, 0xab, 0x4b, ++ 0x76, 0x2a, 0xfe, 0xdf, 0xe1, 0x3b, 0xe9, 0xfc, 0xbe, 0x9d, 0xe2, 0x7a, ++ 0x82, 0x56, 0x71, 0x3f, 0x5f, 0x2f, 0x5e, 0xe6, 0xf5, 0x5f, 0xa5, 0x8b, ++ 0xeb, 0xf2, 0x62, 0x66, 0x5a, 0xf4, 0xdf, 0x2b, 0xff, 0x77, 0x48, 0x1c, ++ 0x89, 0x99, 0x43, 0x17, 0xf7, 0x68, 0x6b, 0xfd, 0x57, 0x79, 0xeb, 0x73, ++ 0x67, 0x21, 0x3d, 0x36, 0x23, 0x39, 0x4f, 0x4c, 0x3b, 0x91, 0xfd, 0xbc, ++ 0xfd, 0x1a, 0x32, 0xe5, 0x4a, 0xf6, 0xb3, 0xf9, 0x98, 0x87, 0x86, 0xc7, ++ 0x64, 0xdf, 0x8e, 0xc2, 0xe3, 0xd3, 0xc0, 0xb4, 0xcd, 0x61, 0xad, 0x01, ++ 0x3c, 0x6a, 0x4a, 0x4f, 0x48, 0xef, 0xdf, 0x05, 0xd9, 0xd7, 0x66, 0xd0, ++ 0x4f, 0x61, 0x56, 0x72, 0xed, 0x37, 0x66, 0x65, 0xcf, 0x4e, 0x07, 0x75, ++ 0x20, 0x6b, 0x17, 0x1f, 0x28, 0xda, 0x5e, 0xf6, 0x15, 0xa6, 0xa8, 0x1f, ++ 0xd1, 0x4d, 0x71, 0x7f, 0x61, 0x84, 0xb6, 0xbe, 0x5c, 0x27, 0x5d, 0xae, ++ 0x4e, 0x9e, 0x30, 0xc5, 0x5f, 0x89, 0x3e, 0xf4, 0xd5, 0x19, 0x72, 0x89, ++ 0x21, 0xb3, 0xc4, 0xe5, 0x6d, 0x12, 0x53, 0x87, 0xec, 0x0a, 0xfa, 0xfc, ++ 0x02, 0x16, 0x32, 0x27, 0xf1, 0xf2, 0xa5, 0xff, 0xc1, 0x93, 0x9a, 0xa7, ++ 0x79, 0xb3, 0xfb, 0x9e, 0xee, 0x96, 0xeb, 0xaf, 0x36, 0x04, 0x87, 0x42, ++ 0x2b, 0xe4, 0xbd, 0x1d, 0xfd, 0xe0, 0x4f, 0xdf, 0xd7, 0xa5, 0x87, 0x84, ++ 0x35, 0xa7, 0x74, 0xd1, 0x4d, 0x7f, 0xd3, 0x71, 0x5d, 0xd6, 0x35, 0x65, ++ 0x0e, 0xbb, 0xff, 0x13, 0x7a, 0x74, 0xcd, 0x6e, 0x5d, 0x62, 0x67, 0xdf, ++ 0xea, 0x16, 0x17, 0x13, 0xc6, 0xac, 0x6b, 0x5c, 0x1d, 0xa4, 0xad, 0xab, ++ 0xdd, 0xe3, 0x21, 0xf2, 0x09, 0x39, 0x1e, 0xb1, 0xf2, 0xba, 0x99, 0x21, ++ 0xc7, 0x92, 0xe3, 0x5f, 0x5b, 0xf9, 0xbd, 0xf2, 0x47, 0x2d, 0xdd, 0x3d, ++ 0x9e, 0x60, 0x8e, 0x93, 0xe3, 0x94, 0x75, 0xd5, 0x65, 0xff, 0x1b, 0x08, ++ 0xfc, 0x3f, 0x3d, 0x30, 0x38, 0x77, 0x3c, 0x3b, 0x00, 0x00, 0x00 }; + + static const u32 bnx2_TXP_b06FwData[(0x0/4) + 1] = { 0x0 }; + static const u32 bnx2_TXP_b06FwRodata[(0x0/4) + 1] = { 0x0 }; + + static struct fw_info bnx2_txp_fw_06 = { +- /* Firmware version: 4.0.5 */ +- .ver_major = 0x4, +- .ver_minor = 0x0, +- .ver_fix = 0x5, +- +- .start_addr = 0x08000098, ++ /* Firmware version: 5.0.0j */ ++ .ver_major = 0x5, ++ .ver_minor = 0x0, ++ .ver_fix = 0x0, ++ ++ .start_addr = 0x080000a8, + + .text_addr = 0x08000000, +- .text_len = 0x3ad8, ++ .text_len = 0x3b38, + .text_index = 0x0, + .gz_text = bnx2_TXP_b06FwText, + .gz_text_len = sizeof(bnx2_TXP_b06FwText), +@@ -4582,11 +4491,11 @@ + .data_index = 0x0, + .data = bnx2_TXP_b06FwData, + +- .sbss_addr = 0x08003b00, ++ .sbss_addr = 0x08003b60, + .sbss_len = 0x68, + .sbss_index = 0x0, + +- .bss_addr = 0x08003b68, ++ .bss_addr = 0x08003bc8, + .bss_len = 0x14c, + .bss_index = 0x0, + +@@ -4611,3 +4520,4 @@ + .spad_base = BNX2_TXP_SCRATCH, + .mips_view_base = 0x8000000, + }; ++ +diff -r 5f108bc568be drivers/net/bnx2_fw2.h +--- a/drivers/net/bnx2_fw2.h Tue Sep 01 13:49:15 2009 +0100 ++++ b/drivers/net/bnx2_fw2.h Tue Sep 01 13:50:09 2009 +0100 +@@ -15,848 +15,855 @@ + */ + + static u8 bnx2_COM_b09FwText[] = { +- 0xcd, 0x7c, 0x7f, 0x6c, 0x5c, 0xd7, 0x75, 0xe6, 0x79, 0x6f, 0xde, 0x90, +- 0x43, 0x8a, 0xa2, 0x1e, 0x99, 0x31, 0x33, 0x8e, 0xd8, 0x7a, 0x86, 0xf3, +- 0x48, 0xd1, 0x21, 0xe3, 0x3e, 0x33, 0x63, 0x99, 0x76, 0xa6, 0xd6, 0x64, +- 0x66, 0x28, 0x2b, 0x0e, 0x69, 0xd0, 0x8e, 0x82, 0x4d, 0x01, 0x03, 0xe5, +- 0x0e, 0xa9, 0x54, 0xd9, 0xf5, 0x22, 0xda, 0x34, 0x45, 0x8a, 0xa2, 0x88, +- 0x26, 0x24, 0xe5, 0x2a, 0xcd, 0x88, 0x1c, 0xcb, 0x34, 0x1b, 0x14, 0x5e, +- 0x64, 0x3c, 0xa4, 0x14, 0xb7, 0x1d, 0x89, 0x72, 0xe2, 0x2d, 0xbc, 0x58, +- 0x07, 0x66, 0xa9, 0x1f, 0x4e, 0x83, 0x14, 0xf0, 0x2e, 0xbc, 0x68, 0x60, +- 0xa4, 0x80, 0x20, 0xbb, 0x8d, 0xb3, 0xc8, 0x62, 0x83, 0xdd, 0x00, 0x71, +- 0x02, 0x27, 0x6f, 0xbf, 0xef, 0xde, 0xfb, 0xc8, 0xd1, 0x88, 0x76, 0xd2, +- 0xfc, 0xb5, 0x04, 0x06, 0xf7, 0xfd, 0xb8, 0x3f, 0xce, 0x3d, 0xf7, 0xdc, +- 0x73, 0xbe, 0x73, 0xee, 0x79, 0x7c, 0x40, 0xa4, 0x53, 0xcc, 0xdf, 0x5e, +- 0xfc, 0x32, 0xff, 0xe1, 0xb3, 0xb3, 0x63, 0x77, 0x65, 0xee, 0xc2, 0xe5, +- 0x87, 0xed, 0xf7, 0x3b, 0x0e, 0x9f, 0x47, 0xf0, 0x8b, 0xe3, 0x37, 0x66, +- 0xae, 0x77, 0xfb, 0x73, 0xf1, 0x3b, 0x68, 0x89, 0xcc, 0xfc, 0x4f, 0x11, +- 0xab, 0xe5, 0x5d, 0xec, 0x5d, 0xda, 0xbc, 0xd7, 0x9f, 0xfd, 0x1b, 0xb4, +- 0xf9, 0xd7, 0xfe, 0x45, 0x34, 0xd9, 0x6a, 0xde, 0xfc, 0x49, 0xcc, 0xce, +- 0xce, 0x4c, 0xe6, 0x3d, 0x89, 0x45, 0xb2, 0x47, 0xa7, 0x66, 0x3d, 0x91, +- 0x5c, 0x63, 0x24, 0x59, 0x90, 0x5f, 0x04, 0xe5, 0xb8, 0x23, 0x7c, 0xfe, +- 0x5b, 0xd9, 0x77, 0xbe, 0xf6, 0xad, 0x7b, 0x53, 0x3f, 0xae, 0x45, 0x24, +- 0xe6, 0x66, 0xdf, 0x16, 0x77, 0x48, 0x62, 0xfd, 0x68, 0xf3, 0xcc, 0x81, +- 0x57, 0x6d, 0xe9, 0x0e, 0xfb, 0x72, 0x67, 0x22, 0x59, 0x99, 0x3e, 0x56, +- 0x39, 0x19, 0xd8, 0x9e, 0x94, 0x9d, 0xac, 0x37, 0x5c, 0x97, 0xae, 0xf1, +- 0x73, 0x99, 0x7b, 0x05, 0xf7, 0xd3, 0xc7, 0x1a, 0x31, 0x99, 0x6f, 0x94, +- 0xbb, 0x6c, 0xcf, 0x43, 0x29, 0xb1, 0xb6, 0xec, 0x62, 0xec, 0x9a, 0xc7, +- 0xb1, 0xbf, 0x8a, 0xb1, 0xf7, 0x4b, 0xd4, 0x0b, 0x82, 0x73, 0x18, 0xfb, +- 0x70, 0xe3, 0x17, 0xc1, 0xb3, 0x8e, 0x1e, 0xd7, 0xce, 0x9e, 0x88, 0xb0, +- 0xb4, 0xb2, 0xb5, 0xc9, 0x81, 0x06, 0xef, 0x8b, 0xed, 0x9a, 0x4e, 0xbf, +- 0x13, 0x74, 0xc6, 0x9c, 0xec, 0x89, 0xce, 0x45, 0x94, 0xd1, 0x6c, 0x7c, +- 0xec, 0x9c, 0xaa, 0xb7, 0x6e, 0xea, 0x3d, 0x1e, 0xd5, 0xed, 0xde, 0x9a, +- 0x1c, 0x6a, 0xb0, 0xfc, 0xc9, 0xe4, 0xa0, 0x2a, 0xdf, 0x99, 0x4c, 0xab, +- 0x52, 0xa6, 0x06, 0x54, 0xe9, 0x4c, 0x79, 0xaa, 0x7c, 0xc6, 0x3c, 0x7f, +- 0x6e, 0x32, 0xa9, 0xca, 0x86, 0x29, 0x2f, 0x99, 0xf2, 0x05, 0x53, 0xbe, +- 0x68, 0xca, 0x97, 0x4c, 0xb9, 0x69, 0xca, 0x2b, 0x93, 0xba, 0x9f, 0x6f, +- 0x9b, 0xfb, 0xef, 0x9a, 0xf2, 0x55, 0x53, 0xbe, 0x66, 0xca, 0xef, 0x99, +- 0xf2, 0xfb, 0x86, 0xae, 0xeb, 0xa6, 0x7c, 0xd3, 0x94, 0x3f, 0x32, 0xef, +- 0x7f, 0x6c, 0xe8, 0x7d, 0x1b, 0x74, 0xfd, 0x49, 0xd4, 0xc8, 0x2a, 0xe6, +- 0x9d, 0x94, 0xd9, 0x8a, 0x23, 0xf3, 0xcb, 0x11, 0x29, 0xa8, 0x35, 0xfc, +- 0xca, 0x5e, 0xe9, 0x74, 0x64, 0x61, 0x23, 0x26, 0xd7, 0x95, 0x88, 0xbe, +- 0x15, 0x7c, 0xeb, 0x80, 0x94, 0xed, 0xac, 0x2b, 0x97, 0x36, 0xe2, 0xf2, +- 0xf2, 0x86, 0x58, 0xd3, 0x99, 0x0e, 0xb1, 0xcf, 0x7e, 0x40, 0x72, 0xae, +- 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0x03, 0x96, 0xdd, 0x54, +- 0xe2, 0x3a, 0xe4, 0xe1, 0x46, 0xe5, 0x99, 0x1e, 0xfe, 0xaf, 0x8a, 0x3a, +- 0xec, 0xe1, 0x0d, 0x95, 0x83, 0x94, 0x62, 0xcc, 0x04, 0xf7, 0xfd, 0x26, +- 0x0f, 0x8a, 0xe3, 0xf0, 0x5d, 0xbf, 0xbc, 0x51, 0xd9, 0xb6, 0xbf, 0x1c, +- 0xc7, 0x7c, 0x03, 0xcf, 0xb1, 0x2e, 0xf4, 0x50, 0x0f, 0x71, 0x3c, 0xdd, +- 0x47, 0x58, 0x87, 0x7c, 0x0d, 0xe3, 0x9a, 0xea, 0x5b, 0xcb, 0xa4, 0x58, +- 0x96, 0xb4, 0x79, 0x9c, 0xfb, 0x54, 0x8f, 0xc6, 0x40, 0x6c, 0x97, 0x76, +- 0x0f, 0xab, 0xfe, 0x78, 0xb6, 0xc7, 0xf3, 0xaf, 0xb0, 0x1f, 0xe6, 0x43, +- 0x31, 0xe7, 0x8a, 0xba, 0xaf, 0x99, 0x06, 0x6d, 0xff, 0xdf, 0x50, 0xb1, +- 0xf4, 0x71, 0xd4, 0xa7, 0x8d, 0x86, 0xbc, 0xd4, 0x12, 0xdb, 0xdf, 0x7c, +- 0x68, 0x5e, 0xf2, 0xfa, 0x99, 0xed, 0x6f, 0x32, 0xec, 0xbb, 0x5d, 0xf3, +- 0x3e, 0xc4, 0xa5, 0xfd, 0xd8, 0xaf, 0x8f, 0x49, 0x7d, 0x25, 0x9d, 0xf8, +- 0xb4, 0x84, 0xfd, 0x06, 0x87, 0x78, 0xde, 0x51, 0xcc, 0x8c, 0xb8, 0x0b, +- 0x8a, 0x9e, 0x54, 0x82, 0x39, 0xc8, 0x97, 0x31, 0x5e, 0xbd, 0xd1, 0x1a, +- 0x7b, 0x48, 0xe5, 0x36, 0x25, 0xed, 0xeb, 0xb5, 0x19, 0x92, 0x4d, 0xac, +- 0xcd, 0x9f, 0x9b, 0xb5, 0xf9, 0x18, 0xfa, 0xf6, 0xce, 0x8c, 0x4a, 0xfa, +- 0x4c, 0x3a, 0x79, 0x5a, 0x78, 0x96, 0xb8, 0x8f, 0x31, 0x2c, 0xeb, 0xc1, +- 0x4c, 0x12, 0xf3, 0x4d, 0x61, 0xbe, 0x28, 0x1b, 0xbc, 0x1e, 0x81, 0x6f, +- 0xbe, 0x87, 0x7b, 0xfb, 0x10, 0x75, 0x26, 0x79, 0x51, 0x54, 0xef, 0x80, +- 0x4f, 0x9e, 0x26, 0x4d, 0x00, 0xca, 0x9d, 0x29, 0x15, 0x07, 0xbc, 0xde, +- 0xe0, 0xf9, 0xa2, 0xa6, 0xaf, 0x00, 0xfa, 0xe6, 0x34, 0x7d, 0xc9, 0x99, +- 0x6d, 0xec, 0x9a, 0x4a, 0x9c, 0x12, 0xe2, 0x25, 0xe2, 0x17, 0xe2, 0xfa, +- 0x47, 0x7a, 0xc3, 0x6f, 0x5a, 0xf2, 0x77, 0xe7, 0xb6, 0xe7, 0xde, 0x86, +- 0xba, 0x57, 0x32, 0x2a, 0xbf, 0xd9, 0x3d, 0x22, 0x1f, 0x91, 0xdc, 0xa7, +- 0x52, 0xc9, 0x9c, 0xe5, 0x19, 0x0c, 0x88, 0xb2, 0xc6, 0x6b, 0xea, 0x5c, +- 0xcf, 0x60, 0x0b, 0xae, 0x4d, 0x06, 0x63, 0x29, 0xde, 0xc2, 0x67, 0xea, +- 0x87, 0xcc, 0x53, 0xd6, 0x7e, 0x07, 0x7b, 0x48, 0xff, 0x9f, 0x8e, 0xcb, +- 0xe0, 0xe3, 0x3c, 0xf8, 0x78, 0xfc, 0x16, 0x0c, 0x16, 0xdd, 0xc6, 0x60, +- 0x5b, 0x6a, 0xbc, 0x7b, 0x41, 0x53, 0xc1, 0x25, 0xfe, 0x9a, 0xdf, 0x96, +- 0x15, 0xd2, 0x34, 0xca, 0xff, 0xb5, 0x23, 0x57, 0x33, 0x5c, 0x0f, 0x60, +- 0x30, 0xf4, 0xb7, 0xb6, 0x23, 0x4b, 0x98, 0xbf, 0x92, 0x5f, 0xc8, 0x6e, +- 0xca, 0x75, 0x2c, 0xae, 0x05, 0xfb, 0x13, 0xeb, 0x1a, 0x68, 0xd9, 0x52, +- 0x72, 0xa0, 0x65, 0x60, 0xab, 0xd6, 0xf9, 0x1e, 0x32, 0xc0, 0x79, 0x52, +- 0xfe, 0x42, 0xd9, 0xdb, 0xc9, 0xa7, 0xe8, 0x00, 0x4f, 0x3e, 0x78, 0x4f, +- 0x56, 0xf2, 0x67, 0x78, 0x16, 0x26, 0xd6, 0xc8, 0x3d, 0x94, 0x49, 0xe2, +- 0x04, 0x60, 0xc8, 0x04, 0x79, 0xac, 0xf1, 0xe0, 0xcc, 0xb3, 0x7b, 0xf1, +- 0x7b, 0xb3, 0x87, 0x39, 0x33, 0xf9, 0x73, 0xd4, 0x57, 0x62, 0xdd, 0x79, +- 0x8f, 0xf6, 0x0f, 0x6f, 0xc4, 0xc1, 0x73, 0xbc, 0x1f, 0x78, 0xb2, 0x0d, +- 0xfa, 0xca, 0x31, 0xf3, 0xe6, 0x3d, 0xf9, 0x8a, 0xf2, 0xd9, 0x29, 0xa3, +- 0x03, 0xa8, 0x47, 0xc4, 0xec, 0x8b, 0xb2, 0xcc, 0x31, 0x46, 0x9f, 0xe9, +- 0x94, 0x09, 0xe8, 0xb5, 0x23, 0x95, 0x71, 0xf9, 0x72, 0xa5, 0x4b, 0xe1, +- 0x86, 0xbf, 0xf6, 0xd3, 0x89, 0x61, 0x2b, 0x90, 0x07, 0x81, 0x7f, 0x66, +- 0xfa, 0xdb, 0xe4, 0xcd, 0x51, 0x9d, 0xfb, 0x7b, 0x83, 0xc9, 0x8d, 0x2e, +- 0xf3, 0x55, 0x39, 0x1f, 0xe8, 0x7d, 0x0b, 0xbe, 0x80, 0xd5, 0x2e, 0x33, +- 0xf1, 0x2e, 0xf9, 0xb8, 0x8f, 0xf2, 0x36, 0x5f, 0x7d, 0x63, 0x9c, 0x8b, +- 0x37, 0xeb, 0x91, 0x37, 0xcd, 0xd8, 0x5f, 0x34, 0xe5, 0xbf, 0xe9, 0x6d, +- 0xa2, 0xc5, 0x9a, 0xcb, 0x44, 0xd4, 0xfc, 0xe6, 0x6b, 0xd4, 0x6f, 0x6c, +- 0x03, 0x7d, 0xd2, 0xe0, 0x39, 0x51, 0x59, 0xd6, 0xa0, 0x5f, 0x4a, 0x55, +- 0xb1, 0xce, 0x65, 0x80, 0xa8, 0x3d, 0x8d, 0x3f, 0x4b, 0x90, 0xaf, 0xd9, +- 0xaa, 0x8a, 0x59, 0xaa, 0xbc, 0xed, 0x59, 0x60, 0x5d, 0xf8, 0xc4, 0xc0, +- 0x10, 0x26, 0x7f, 0xa5, 0x93, 0xf1, 0x90, 0x66, 0x1d, 0x16, 0xfe, 0x2f, +- 0x9d, 0xff, 0xd4, 0x2b, 0xdd, 0x65, 0xac, 0x4b, 0x88, 0xb9, 0xc1, 0x53, +- 0x8c, 0x99, 0x57, 0xeb, 0x14, 0xae, 0x09, 0x75, 0x4f, 0x73, 0xbe, 0x78, +- 0x88, 0x39, 0xb8, 0x67, 0x69, 0x2f, 0xa4, 0x1c, 0x03, 0xa6, 0xed, 0x38, +- 0x03, 0xdb, 0x5d, 0xcd, 0x42, 0x56, 0xc6, 0x55, 0xde, 0xe7, 0x3c, 0xb0, +- 0xdb, 0x1f, 0xf8, 0x7f, 0x2a, 0xf6, 0xd3, 0x07, 0x64, 0xad, 0xda, 0x01, +- 0x7e, 0xd0, 0x2e, 0x44, 0x95, 0x7f, 0x7d, 0xe3, 0x28, 0xed, 0x1d, 0x6d, +- 0x89, 0x5e, 0x8b, 0xad, 0xda, 0xf7, 0x7a, 0xf5, 0xb7, 0x33, 0x7b, 0x65, +- 0xb3, 0x16, 0xda, 0x42, 0xf8, 0x87, 0xd5, 0xa8, 0xb1, 0xcb, 0x9d, 0xd0, +- 0xdd, 0xdf, 0x8f, 0xd6, 0x95, 0xaf, 0xce, 0xf9, 0xd3, 0x06, 0x45, 0x99, +- 0x17, 0xd7, 0x59, 0xf7, 0x38, 0xf7, 0x66, 0x1b, 0xa4, 0x71, 0x87, 0x7b, +- 0x90, 0xe3, 0x31, 0x87, 0x82, 0x73, 0x8c, 0x4b, 0xf4, 0xfc, 0x63, 0x62, +- 0xc3, 0x6f, 0x89, 0x2c, 0x11, 0xeb, 0xdd, 0xec, 0xbb, 0x44, 0x2e, 0xba, +- 0xe6, 0x5b, 0xec, 0x41, 0x8d, 0x65, 0x32, 0x28, 0xeb, 0xe1, 0xf7, 0xd9, +- 0xfc, 0x35, 0xdb, 0xcd, 0xd0, 0xb7, 0xd8, 0xd5, 0x96, 0xe2, 0xef, 0xff, +- 0x01, 0x37, 0x64, 0x26, 0x2b, 0x1c, 0x4c, 0x00, 0x00, 0x00 }; ++ 0xcd, 0x7c, 0x7f, 0x6c, 0x1c, 0xd7, 0x9d, 0xdf, 0x77, 0x66, 0x67, 0xc9, ++ 0x25, 0x45, 0x51, 0x23, 0x66, 0xcd, 0xac, 0x1d, 0x46, 0xde, 0xe5, 0x0e, ++ 0x29, 0xda, 0xa2, 0x9d, 0x31, 0xb1, 0x92, 0x99, 0x64, 0x1a, 0x6f, 0x76, ++ 0x57, 0xb2, 0x1c, 0x3a, 0x29, 0xe5, 0xe8, 0x70, 0x69, 0xcf, 0xe8, 0xf1, ++ 0x96, 0x94, 0x23, 0x07, 0x6e, 0xa3, 0x4b, 0xdc, 0xc2, 0x97, 0x06, 0xd1, ++ 0x78, 0x49, 0xe9, 0x94, 0x76, 0xc5, 0x5d, 0xd3, 0xb4, 0x92, 0x02, 0x29, ++ 0x6e, 0xbd, 0xa4, 0xe4, 0x5c, 0xbb, 0x12, 0xed, 0xc4, 0xd7, 0xf8, 0xd0, ++ 0xcb, 0x59, 0xa0, 0x24, 0x27, 0x2d, 0x7a, 0x81, 0x53, 0x18, 0x6d, 0x9a, ++ 0x16, 0x2d, 0x21, 0xfb, 0xee, 0xdc, 0x22, 0x05, 0x52, 0x20, 0xd7, 0x24, ++ 0xad, 0x9d, 0xed, 0xe7, 0xf3, 0xde, 0x1b, 0x6a, 0x45, 0xc9, 0x76, 0xee, ++ 0xfe, 0x2a, 0x81, 0xc5, 0x9b, 0x79, 0xf3, 0xde, 0x9b, 0xef, 0xfb, 0xfe, ++ 0xfe, 0x7e, 0xdf, 0x77, 0x58, 0x12, 0xe9, 0x15, 0xf3, 0xb7, 0x1d, 0xbf, ++ 0xbd, 0x7f, 0xff, 0xf3, 0xb3, 0xfe, 0xdd, 0xfe, 0xdd, 0xb8, 0xfc, 0x9c, ++ 0x2d, 0x12, 0x67, 0x7f, 0x0c, 0xbf, 0x24, 0x7e, 0x13, 0xe6, 0xfa, 0x66, ++ 0x7f, 0x2e, 0x7e, 0xfb, 0x2c, 0x91, 0x99, 0xff, 0x61, 0x26, 0x75, 0xfc, ++ 0x25, 0xde, 0x61, 0xce, 0xbb, 0xfd, 0xd9, 0xbf, 0xe6, 0x38, 0xf7, 0x6f, ++ 0xb0, 0xf6, 0x7b, 0xfd, 0xc5, 0xcc, 0xb2, 0xdb, 0xcd, 0x4f, 0x12, 0x76, ++ 0x90, 0x9e, 0x2a, 0x78, 0x92, 0x88, 0x05, 0x0f, 0x3f, 0x38, 0xeb, 0x89, ++ 0xe4, 0x5b, 0x7b, 0xd2, 0x45, 0x79, 0xbb, 0x1d, 0x26, 0x1d, 0x61, 0xff, ++ 0x07, 0x83, 0xb7, 0xfe, 0xe0, 0xbb, 0xf7, 0x66, 0x7e, 0xda, 0x88, 0x49, ++ 0xc2, 0x0d, 0x5c, 0xcb, 0x1d, 0x95, 0xc4, 0x10, 0xe6, 0x7c, 0x63, 0xf7, ++ 0x6f, 0xdb, 0xd2, 0x1f, 0xad, 0xb5, 0xd1, 0xfe, 0xee, 0xee, 0x94, 0xbc, ++ 0xbc, 0x96, 0x94, 0x17, 0xd6, 0x5c, 0x79, 0x7e, 0x4d, 0x42, 0x27, 0x48, ++ 0x58, 0x95, 0x65, 0x39, 0x56, 0xf4, 0x25, 0x6d, 0x7b, 0xdb, 0xa4, 0xec, ++ 0x5a, 0xe9, 0xf2, 0xd8, 0x3e, 0xc9, 0x27, 0x33, 0x84, 0x20, 0x6f, 0x7b, ++ 0xe3, 0xe8, 0x53, 0x40, 0xcd, 0xd8, 0xde, 0x5d, 0xb8, 0x66, 0xff, 0x3f, ++ 0x07, 0xcd, 0xb0, 0x4e, 0x4d, 0xac, 0xa7, 0x72, 0x3d, 0xe2, 0x2d, 0xa5, ++ 0xc4, 0x5f, 0x4c, 0x4b, 0xe8, 0x5a, 0x12, 0xf3, 0x7a, 0xc4, 0xf6, 0xba, ++ 0xa4, 0x92, 0x4c, 0x4b, 0xa5, 0x96, 0x08, 0xed, 0xe0, 0x36, 0x29, 0x2c, ++ 0x4b, 0xd2, 0x96, 0x91, 0xd0, 0xb6, 0xd9, 0xd7, 0x27, 0x85, 0xea, 0x2d, ++ 0x92, 0x77, 0x33, 0x29, 0x91, 0x2f, 0x6d, 0xd7, 0xb0, 0xa5, 0x65, 0xbe, ++ 0x96, 0x10, 0xef, 0xcc, 0x10, 0x9e, 0xef, 0x92, 0xd9, 0xe5, 0x3e, 0x19, ++ 0x39, 0x23, 0x9e, 0x23, 0x23, 0xe9, 0x79, 0x3c, 0x9d, 0x6e, 0x39, 0xb2, ++ 0xbf, 0x95, 0xc0, 0x9e, 0xfb, 0xf0, 0x73, 0xf1, 0x4b, 0xe2, 0x97, 0xc2, ++ 0x6f, 0x48, 0x4a, 0xad, 0x67, 0xb1, 0x86, 0x25, 0x8e, 0xc7, 0xf5, 0xbe, ++ 0x01, 0xb8, 0x32, 0xee, 0x8c, 0x3c, 0xe4, 0xe8, 0x75, 0xf5, 0x3d, 0xe0, ++ 0xed, 0xd3, 0xf7, 0xbc, 0x26, 0xdc, 0xd8, 0x7f, 0x0d, 0xfb, 0xc7, 0x3b, ++ 0x37, 0x62, 0x69, 0xf9, 0xee, 0x6e, 0xc2, 0x45, 0xdc, 0x10, 0x27, 0x11, ++ 0x7e, 0x08, 0x27, 0xb6, 0x14, 0x88, 0xb5, 0x73, 0x31, 0x07, 0x78, 0x39, ++ 0x2f, 0x82, 0x77, 0x48, 0x4e, 0xd4, 0xda, 0xc7, 0x1d, 0x6f, 0x4f, 0xfa, ++ 0x29, 0xdc, 0xbd, 0xd0, 0x72, 0xac, 0xd8, 0x62, 0xc2, 0xb2, 0xcf, 0xc8, ++ 0x50, 0x4c, 0xda, 0xed, 0x82, 0x3f, 0x92, 0x2a, 0x8b, 0x23, 0x2b, 0xad, ++ 0x5e, 0xcb, 0x5e, 0x4a, 0x5a, 0xb1, 0x33, 0x6d, 0x29, 0xf8, 0xed, 0xf6, ++ 0xac, 0xaf, 0xf0, 0xe0, 0x16, 0xc1, 0x8f, 0xcd, 0x56, 0x1f, 0xfa, 0xfb, ++ 0xb7, 0xcc, 0xe9, 0xc3, 0x1c, 0x17, 0xfd, 0x03, 0x5b, 0xfa, 0x5d, 0xf4, ++ 0xa7, 0x2c, 0x7b, 0x31, 0x89, 0x79, 0x43, 0x68, 0x53, 0x68, 0x13, 0x12, ++ 0x2a, 0x1c, 0x8b, 0x54, 0xbe, 0x16, 0x4f, 0x3b, 0xc1, 0x48, 0xaa, 0x24, ++ 0x16, 0x78, 0x61, 0x08, 0x63, 0xff, 0xb3, 0x92, 0xa9, 0xca, 0x73, 0xa9, ++ 0x7c, 0x2c, 0xd8, 0x05, 0xfc, 0xf3, 0x9d, 0x43, 0x98, 0x13, 0xe1, 0xaa, ++ 0x13, 0x07, 0xc4, 0x49, 0x84, 0x07, 0x09, 0xbb, 0x82, 0x97, 0xec, 0xf5, ++ 0x2a, 0xe9, 0x98, 0x90, 0x8f, 0x3b, 0x99, 0xb1, 0x50, 0xf1, 0xde, 0x0c, ++ 0x70, 0x61, 0x29, 0x3e, 0xb3, 0x70, 0x3d, 0xdc, 0xe2, 0x78, 0xe2, 0x19, ++ 0x74, 0xab, 0x0e, 0x4a, 0x65, 0x39, 0xb4, 0x2f, 0xb5, 0xde, 0x6a, 0x17, ++ 0xbc, 0x05, 0x7b, 0x7d, 0x95, 0xe3, 0x1f, 0xc6, 0x78, 0x47, 0x16, 0xaa, ++ 0xfd, 0xb2, 0xb2, 0x1c, 0xcd, 0x7b, 0x18, 0xf3, 0xc4, 0xb5, 0x83, 0x93, ++ 0xf6, 0xa5, 0xd5, 0x53, 0xf6, 0xe5, 0x16, 0xe9, 0x85, 0x77, 0x6d, 0xae, ++ 0x15, 0xe1, 0x9f, 0x38, 0x4f, 0xc9, 0xb7, 0xd6, 0x86, 0x0c, 0x1d, 0xc4, ++ 0x1a, 0xd8, 0xb7, 0x4d, 0x8a, 0x4b, 0xb7, 0x81, 0xaf, 0x12, 0x72, 0xe8, ++ 0xcc, 0xdf, 0x95, 0x72, 0x32, 0x33, 0x26, 0xd8, 0xeb, 0xf0, 0x04, 0x78, ++ 0xc0, 0xd5, 0x38, 0x28, 0x2c, 0xe6, 0xb3, 0xb6, 0xdc, 0x27, 0x76, 0x00, ++ 0x9c, 0xe5, 0xf6, 0xb8, 0x25, 0xe0, 0x3f, 0xef, 0xe6, 0x25, 0x16, 0x24, ++ 0xa5, 0x70, 0xc6, 0xb3, 0xc0, 0x07, 0xe4, 0x25, 0xd0, 0x49, 0x2c, 0xf2, ++ 0x67, 0xf9, 0x30, 0xfb, 0xc9, 0x9f, 0x90, 0x9f, 0xfa, 0x0e, 0xd0, 0x47, ++ 0x46, 0x6c, 0x61, 0xdf, 0x88, 0x5b, 0x91, 0x50, 0xec, 0x0b, 0xbf, 0x69, ++ 0x69, 0xbd, 0x44, 0x3e, 0x18, 0xc3, 0x5a, 0xbc, 0x8e, 0xe8, 0x4f, 0x5a, ++ 0x93, 0x7e, 0xe4, 0x83, 0x8f, 0x6d, 0xa1, 0xad, 0x00, 0xcf, 0x78, 0xc7, ++ 0xa2, 0x83, 0x76, 0x50, 0xd1, 0xd8, 0x39, 0xa3, 0x60, 0x54, 0xf4, 0x5c, ++ 0x00, 0x3d, 0xe7, 0x80, 0xef, 0x88, 0xce, 0xce, 0x99, 0x5d, 0x72, 0x60, ++ 0xb9, 0xf3, 0x19, 0x79, 0x00, 0xb2, 0x18, 0x8c, 0xf8, 0xeb, 0x92, 0xc4, ++ 0x7b, 0x48, 0x2f, 0xf2, 0x81, 0x8b, 0xf5, 0x22, 0x1e, 0xd8, 0x06, 0xbe, ++ 0x22, 0x4f, 0xa5, 0x0c, 0x4d, 0x87, 0xe4, 0x5c, 0x8b, 0x78, 0xcf, 0x77, ++ 0xd0, 0x29, 0x4f, 0x7c, 0x43, 0x5f, 0x94, 0x64, 0xb6, 0x6a, 0x03, 0x57, ++ 0x8e, 0x78, 0x13, 0x96, 0xcc, 0xaa, 0x67, 0x25, 0xc9, 0x92, 0x7f, 0xdc, ++ 0x3d, 0x63, 0xb6, 0x64, 0xd2, 0x79, 0x1b, 0xb8, 0xae, 0x01, 0xe7, 0x9b, ++ 0x3c, 0xf1, 0x3a, 0xf8, 0x87, 0xfc, 0xb0, 0xb5, 0x3f, 0xe3, 0x36, 0x36, ++ 0x79, 0xe5, 0xbd, 0xe8, 0x15, 0x03, 0xbd, 0x3e, 0x07, 0x5a, 0x91, 0x66, ++ 0xa4, 0xd5, 0xfb, 0x37, 0x69, 0x55, 0x5c, 0x8c, 0xe8, 0x94, 0xcf, 0xc6, ++ 0x84, 0xb4, 0x8a, 0x4b, 0x7e, 0x9a, 0x74, 0x21, 0xfe, 0x49, 0xb3, 0x45, ++ 0x43, 0xaf, 0x5f, 0x87, 0x4e, 0x7f, 0xda, 0x41, 0xa7, 0x91, 0xff, 0x4f, ++ 0xe8, 0x94, 0x94, 0x06, 0xf4, 0x53, 0xe3, 0x3d, 0x68, 0x63, 0x83, 0x0e, ++ 0x94, 0x93, 0xec, 0x44, 0xd4, 0x5f, 0x52, 0xb2, 0x35, 0xe3, 0x92, 0x5e, ++ 0xef, 0x46, 0x17, 0xea, 0x4f, 0x3e, 0xa3, 0xfe, 0x76, 0xac, 0xf9, 0x6a, ++ 0x7a, 0xc6, 0x06, 0x9f, 0x17, 0xa1, 0x27, 0x0b, 0xd5, 0x5f, 0x59, 0x31, ++ 0xaf, 0x1d, 0x2b, 0xf8, 0x7d, 0x52, 0x4c, 0xaa, 0x31, 0x56, 0xa5, 0xba, ++ 0x7e, 0xab, 0x2d, 0x6f, 0xb5, 0xcb, 0x90, 0x9f, 0xc2, 0x78, 0x0c, 0x73, ++ 0x6d, 0xc0, 0xfa, 0x36, 0xee, 0x9d, 0x74, 0x89, 0x7a, 0x3d, 0x48, 0x3e, ++ 0x5a, 0x6a, 0xdd, 0x48, 0xeb, 0x4e, 0xbd, 0xe0, 0x40, 0x0f, 0xce, 0x57, ++ 0x49, 0xa3, 0x98, 0x94, 0xa7, 0x49, 0x0f, 0xda, 0x13, 0x4d, 0x97, 0x62, ++ 0x9d, 0x63, 0x77, 0x08, 0x70, 0xfb, 0xc1, 0x98, 0x9a, 0x13, 0xca, 0x7c, ++ 0xeb, 0xc9, 0xee, 0x85, 0xf1, 0x5e, 0x30, 0x07, 0x65, 0x55, 0x30, 0x2e, ++ 0x61, 0xc1, 0x0e, 0xa4, 0x63, 0x9e, 0x1c, 0x2b, 0xf8, 0x71, 0xc0, 0xf6, ++ 0x62, 0x7b, 0x7e, 0x37, 0xe7, 0xc7, 0x41, 0xd7, 0xb6, 0xec, 0xf7, 0x79, ++ 0x1f, 0xa6, 0xe3, 0x42, 0xba, 0x5f, 0x74, 0xe3, 0x92, 0x75, 0xf7, 0x63, ++ 0xe2, 0x42, 0x95, 0x3c, 0xfc, 0x93, 0xa9, 0x59, 0xef, 0x22, 0xa0, 0xce, ++ 0x90, 0x6e, 0x61, 0x2c, 0xa8, 0xcb, 0x5c, 0x4b, 0xc3, 0x56, 0x59, 0xd3, ++ 0xfa, 0x43, 0xc3, 0xaa, 0x6c, 0x96, 0x45, 0x3d, 0x51, 0x49, 0x8a, 0xb1, ++ 0x9b, 0x6f, 0x75, 0xe0, 0xfd, 0x2d, 0xe0, 0xd7, 0xb3, 0x89, 0xc3, 0xa6, ++ 0xcf, 0x67, 0x0b, 0x1d, 0xcf, 0x16, 0xf0, 0x8c, 0xfd, 0xb0, 0x33, 0x2e, ++ 0xf4, 0xad, 0x7a, 0x0e, 0x98, 0x37, 0x9f, 0x27, 0x2c, 0xad, 0xf7, 0xd4, ++ 0xb2, 0xa0, 0x51, 0xb4, 0xbe, 0xd3, 0x31, 0xc6, 0xe9, 0x18, 0xc3, 0x67, ++ 0xd2, 0xf1, 0x4c, 0x3a, 0x9e, 0xbd, 0xd9, 0x21, 0x3b, 0x49, 0xc8, 0x8d, ++ 0x58, 0xce, 0xbe, 0x84, 0xcc, 0x2f, 0x3b, 0x52, 0x06, 0x6e, 0x48, 0x9f, ++ 0x47, 0x7c, 0xf4, 0x6f, 0xd2, 0x3c, 0x05, 0x1a, 0x74, 0x01, 0x2b, 0x99, ++ 0xb1, 0x19, 0xec, 0xcf, 0x59, 0x4c, 0x1a, 0x9b, 0xfe, 0x5b, 0xd8, 0x8b, ++ 0xa5, 0xf4, 0x62, 0xa5, 0x46, 0x1b, 0xd4, 0x2d, 0x45, 0x57, 0xe3, 0xe0, ++ 0xda, 0x18, 0x07, 0x3c, 0x8e, 0xe7, 0x6b, 0xec, 0x8f, 0xd6, 0x24, 0x1c, ++ 0x5c, 0xf3, 0x47, 0x84, 0x63, 0x26, 0x16, 0x0c, 0xc9, 0xb7, 0xd7, 0xd2, ++ 0x80, 0x83, 0x72, 0xbc, 0xe9, 0x1b, 0x4c, 0xcf, 0x55, 0x8f, 0xb7, 0x6d, ++ 0xc0, 0xfe, 0xbe, 0x60, 0x7a, 0xea, 0x8b, 0xa3, 0x5e, 0xba, 0x22, 0x7d, ++ 0x93, 0x0b, 0x39, 0xf4, 0xb7, 0x48, 0xcf, 0x7b, 0x95, 0x8d, 0x28, 0x82, ++ 0x8f, 0xbb, 0x82, 0x7c, 0xe2, 0x15, 0x0f, 0x3a, 0x1c, 0xfc, 0x4a, 0x19, ++ 0x58, 0x80, 0x7f, 0x72, 0xa0, 0xf5, 0x76, 0xfb, 0x49, 0x47, 0xfb, 0x26, ++ 0x76, 0xf0, 0x98, 0xa5, 0x71, 0xf0, 0x99, 0x29, 0xcd, 0xf7, 0x2f, 0xc5, ++ 0x8d, 0x4d, 0x30, 0xf7, 0x0b, 0xb6, 0xbe, 0xff, 0xba, 0xb9, 0x4f, 0x38, ++ 0xda, 0xd7, 0x39, 0x98, 0xa0, 0xbe, 0x72, 0x82, 0x9f, 0x25, 0xb0, 0x66, ++ 0x22, 0x1e, 0x24, 0xef, 0x3a, 0xab, 0xc6, 0xbd, 0x64, 0xc6, 0xad, 0x76, ++ 0xeb, 0x79, 0x8d, 0xa9, 0xd1, 0x16, 0xdb, 0xd6, 0xd4, 0x88, 0x6a, 0x5f, ++ 0x9c, 0xca, 0xaa, 0xf6, 0x4f, 0xa6, 0x3c, 0xd5, 0x5e, 0x54, 0xe3, 0xad, ++ 0xe0, 0xb0, 0xe9, 0x9f, 0x99, 0x4a, 0xab, 0x76, 0xce, 0xb4, 0x47, 0x4d, ++ 0xfb, 0x98, 0x69, 0x8f, 0x99, 0xf6, 0x71, 0xd3, 0x3e, 0x61, 0xda, 0x2f, ++ 0x9b, 0xf5, 0x42, 0x73, 0xbf, 0x60, 0xda, 0x53, 0xa6, 0xad, 0x9a, 0xb6, ++ 0x6e, 0xda, 0x65, 0x03, 0xd7, 0x37, 0x4c, 0xbb, 0x6a, 0xfa, 0xbf, 0x69, ++ 0xe0, 0x7c, 0x1e, 0xf0, 0x3c, 0x19, 0xd7, 0x74, 0x22, 0x4e, 0x8f, 0x49, ++ 0x21, 0x07, 0x5b, 0x56, 0xed, 0x03, 0xbd, 0x1c, 0xf8, 0x44, 0xca, 0xef, ++ 0xc3, 0xfd, 0xed, 0xf4, 0xbb, 0x4e, 0x89, 0xbc, 0xd8, 0x5e, 0xda, 0x4d, ++ 0xff, 0xee, 0x27, 0x53, 0xf4, 0xef, 0xf4, 0x33, 0x4b, 0xe2, 0x9e, 0x93, ++ 0x1a, 0xb1, 0x3d, 0xf8, 0x83, 0x0e, 0xf8, 0xc0, 0x83, 0x8c, 0xf4, 0x49, ++ 0x69, 0xda, 0x92, 0x7b, 0x46, 0xa9, 0xe3, 0xd3, 0x52, 0x5f, 0xa3, 0xce, ++ 0xe5, 0xfa, 0x75, 0xd0, 0xab, 0x04, 0x9d, 0xd4, 0x27, 0xf1, 0x0b, 0x57, ++ 0x15, 0xef, 0xdc, 0x33, 0xda, 0x27, 0x72, 0x81, 0x2d, 0x74, 0xce, 0xdd, ++ 0x93, 0xe2, 0x8e, 0xfe, 0xf7, 0x76, 0x1e, 0x3e, 0xe5, 0x43, 0x9b, 0xeb, ++ 0x63, 0x4d, 0xc5, 0xa7, 0xc7, 0xa4, 0x7b, 0x1f, 0x38, 0x17, 0xb0, 0x9d, ++ 0xac, 0x91, 0x16, 0x7f, 0x22, 0x67, 0xab, 0xa4, 0xcd, 0x4b, 0x90, 0xd1, ++ 0xac, 0xdf, 0x65, 0x91, 0xbf, 0x32, 0x63, 0xe7, 0x20, 0xbf, 0x15, 0xd9, ++ 0xe3, 0xb3, 0x3d, 0x29, 0x8a, 0x06, 0xa2, 0xf7, 0xfa, 0x92, 0x00, 0x77, ++ 0xb2, 0x13, 0x3c, 0x3a, 0x3c, 0xf1, 0xfd, 0x76, 0xde, 0xed, 0x93, 0x53, ++ 0x80, 0xeb, 0x2f, 0xaa, 0x37, 0xae, 0xf5, 0x7d, 0xbd, 0x0e, 0xd6, 0xd3, ++ 0xeb, 0x54, 0xd4, 0x5a, 0x96, 0xec, 0x9e, 0xd8, 0xba, 0x5e, 0x46, 0x36, ++ 0x94, 0xae, 0xa4, 0x1e, 0x4f, 0xc3, 0x16, 0x90, 0xd7, 0xbf, 0x89, 0xf6, ++ 0x7f, 0x5b, 0xc0, 0x29, 0x64, 0x40, 0xdb, 0xc9, 0xa2, 0xff, 0x41, 0x29, ++ 0x8f, 0xc3, 0x1f, 0x38, 0x1c, 0xba, 0x31, 0xb8, 0x20, 0xd2, 0x0f, 0xb3, ++ 0xd3, 0xab, 0xfd, 0xc1, 0x4f, 0x0b, 0xf1, 0xdd, 0xf3, 0x8b, 0xbc, 0x22, ++ 0x01, 0x7d, 0x06, 0xe2, 0xc9, 0xb1, 0x8a, 0x9b, 0x3a, 0x95, 0x78, 0xc8, ++ 0xd1, 0x17, 0xcc, 0x43, 0x07, 0x42, 0xf7, 0x50, 0x9e, 0x27, 0xad, 0x39, ++ 0x05, 0x43, 0x0e, 0x3a, 0x83, 0xef, 0x87, 0x4f, 0xea, 0x3a, 0x84, 0x03, ++ 0x78, 0xca, 0x1b, 0x58, 0x08, 0x43, 0x1e, 0x30, 0xfc, 0xeb, 0x98, 0xa1, ++ 0x6f, 0xde, 0x0e, 0x9e, 0xb0, 0xec, 0x0b, 0x5c, 0x6f, 0xb2, 0x43, 0xef, ++ 0x4c, 0x62, 0x0d, 0xce, 0x0d, 0xdb, 0xfa, 0xdd, 0x5c, 0x23, 0xec, 0x58, ++ 0x23, 0xc4, 0x1a, 0x21, 0xfd, 0x96, 0x1d, 0xb6, 0xd7, 0x0d, 0x7b, 0x48, ++ 0x9d, 0x79, 0x0a, 0xcf, 0x37, 0x60, 0x27, 0x95, 0x7f, 0x08, 0x7a, 0xff, ++ 0x36, 0xf6, 0x43, 0x5b, 0x18, 0x6a, 0xfe, 0xa9, 0x4f, 0x43, 0x36, 0xe9, ++ 0x1f, 0x40, 0x1f, 0x28, 0x3d, 0xf8, 0x75, 0x03, 0x03, 0x74, 0xbf, 0xba, ++ 0xaf, 0xf6, 0x18, 0x98, 0x00, 0x4b, 0xb0, 0x65, 0x6f, 0x2f, 0x99, 0xbd, ++ 0x05, 0x80, 0xeb, 0x12, 0x78, 0x44, 0xc1, 0x54, 0xb7, 0xf9, 0x2c, 0x37, ++ 0x02, 0x5a, 0xf0, 0x3e, 0x0d, 0xbf, 0x9b, 0xe3, 0xd3, 0x52, 0xae, 0xfe, ++ 0xaa, 0x9d, 0x77, 0xb4, 0x4e, 0x34, 0x7a, 0x2f, 0xe4, 0xd8, 0x62, 0x8e, ++ 0xbe, 0xbb, 0xd6, 0xd1, 0xa5, 0x16, 0x7d, 0x85, 0x48, 0xaf, 0x64, 0x4e, ++ 0x85, 0xf4, 0xc1, 0xd7, 0x1e, 0x05, 0x4c, 0x6d, 0x79, 0xde, 0x6f, 0xb5, ++ 0xe7, 0x6b, 0x99, 0x74, 0xda, 0x1e, 0x91, 0x72, 0x9d, 0x31, 0xc2, 0x88, ++ 0x1c, 0x6b, 0xa4, 0xe4, 0x58, 0x95, 0xeb, 0x3c, 0x8e, 0x31, 0x1e, 0xfa, ++ 0x40, 0xac, 0x41, 0x15, 0x6f, 0xe0, 0x9d, 0xbf, 0xb0, 0xf4, 0x3b, 0x6d, ++ 0xe8, 0xbd, 0x8b, 0xd6, 0xef, 0xb6, 0x2e, 0x5b, 0xe5, 0x06, 0xfd, 0x4a, ++ 0xf4, 0xb7, 0x6e, 0xe6, 0xdb, 0x6b, 0x5d, 0x0b, 0x1d, 0x8b, 0xb9, 0x0b, ++ 0x56, 0x79, 0x59, 0xec, 0x82, 0xd2, 0xb1, 0x99, 0xb4, 0xc8, 0xd5, 0x1d, ++ 0x1a, 0x0f, 0x17, 0x62, 0x94, 0x05, 0xc7, 0x3b, 0x85, 0xb5, 0x7b, 0x81, ++ 0x0c, 0x8c, 0xaf, 0xf1, 0x5a, 0xda, 0xb1, 0x80, 0xf2, 0x24, 0x4e, 0x8c, ++ 0x76, 0x2e, 0xc9, 0x31, 0xad, 0x36, 0xe2, 0x1a, 0xe0, 0x98, 0x63, 0x32, ++ 0x6e, 0x28, 0x91, 0x2e, 0x7d, 0x1e, 0xfd, 0xf4, 0x9b, 0x29, 0x8f, 0xb7, ++ 0x49, 0xbe, 0xc1, 0x71, 0x83, 0x52, 0x5c, 0xe5, 0x3e, 0x7e, 0x0f, 0xeb, ++ 0xe7, 0xad, 0x52, 0xb5, 0xd5, 0x3e, 0xa1, 0xe2, 0x8c, 0xa1, 0xad, 0xba, ++ 0x56, 0x9a, 0xb0, 0x81, 0x25, 0x1f, 0xfe, 0xf4, 0xa4, 0x2f, 0x95, 0xc9, ++ 0x3d, 0x29, 0xfa, 0x45, 0xb6, 0x78, 0xf0, 0xfd, 0xe3, 0xb4, 0x35, 0x58, ++ 0x63, 0x1a, 0xfb, 0x7d, 0x12, 0x76, 0x4d, 0xdb, 0x7d, 0x3b, 0x38, 0x68, ++ 0xd1, 0x6e, 0xd2, 0xa7, 0x29, 0x7a, 0x71, 0xf0, 0xf7, 0x97, 0x8c, 0x4f, ++ 0x40, 0x1e, 0xa7, 0xee, 0xdc, 0xf8, 0xc4, 0xac, 0xa7, 0xec, 0x25, 0xe8, ++ 0x0b, 0x9b, 0xa6, 0x03, 0xcb, 0x70, 0x27, 0xf8, 0xd3, 0x5b, 0x24, 0xee, ++ 0x5b, 0xed, 0x25, 0xc4, 0x62, 0xd3, 0x8b, 0x25, 0x6b, 0x78, 0x11, 0xb8, ++ 0x1c, 0xa4, 0x1d, 0x81, 0x0f, 0x75, 0x81, 0x38, 0xe7, 0x18, 0xf6, 0x77, ++ 0xc9, 0x74, 0x72, 0xab, 0x5f, 0xf0, 0xd0, 0x0e, 0xed, 0x83, 0x60, 0xec, ++ 0xe2, 0x01, 0x47, 0xcb, 0x11, 0x7c, 0x9e, 0x65, 0xfa, 0x08, 0x25, 0xf8, ++ 0x08, 0xe4, 0xc9, 0x1e, 0xf8, 0x7d, 0xec, 0xe7, 0x9a, 0x78, 0xb6, 0x9a, ++ 0x87, 0x0f, 0x22, 0x76, 0x45, 0xf9, 0xff, 0x93, 0x68, 0x3f, 0x89, 0x79, ++ 0x43, 0xca, 0x16, 0x35, 0x97, 0xa3, 0x35, 0xc0, 0xef, 0x5e, 0x3f, 0xed, ++ 0x36, 0x60, 0x1c, 0x50, 0xeb, 0xc1, 0x77, 0xb5, 0x66, 0xd5, 0x7a, 0xf1, ++ 0x8e, 0xf5, 0xf0, 0x6c, 0x35, 0x6d, 0xe6, 0x0f, 0x74, 0xcc, 0xef, 0xdc, ++ 0xd7, 0x00, 0xfc, 0xc3, 0x92, 0x95, 0x5d, 0x6c, 0xb7, 0xa7, 0x7d, 0x5b, ++ 0x62, 0x83, 0x7a, 0x5e, 0xe1, 0xdc, 0xf5, 0x7b, 0xb3, 0x07, 0xb7, 0xee, ++ 0xed, 0x5b, 0x31, 0xbd, 0x37, 0xce, 0x8f, 0xd6, 0x4d, 0x6e, 0x81, 0x25, ++ 0x01, 0x58, 0x38, 0x8f, 0x6b, 0x76, 0xce, 0xc5, 0xb8, 0xd5, 0xa3, 0x03, ++ 0x7a, 0x7e, 0xb2, 0x03, 0xae, 0xc1, 0x9b, 0xcc, 0xe7, 0xdc, 0xad, 0xef, ++ 0xc6, 0xb8, 0xd5, 0x89, 0x6d, 0x7a, 0x3e, 0xe7, 0x74, 0x41, 0x56, 0x15, ++ 0xad, 0x13, 0xca, 0x2e, 0x6c, 0xea, 0x8b, 0x63, 0x90, 0xcb, 0xce, 0x79, ++ 0x11, 0x9f, 0xff, 0x48, 0xc5, 0xf6, 0xdf, 0x5a, 0xe3, 0xfe, 0xc9, 0x57, ++ 0xb4, 0xe7, 0xb4, 0xeb, 0xda, 0xcf, 0xa0, 0x2f, 0x72, 0x28, 0x27, 0xd6, ++ 0x74, 0x15, 0xfc, 0xb0, 0xd4, 0x23, 0xd9, 0x25, 0xf2, 0xdb, 0xed, 0x80, ++ 0xe3, 0x5f, 0xc2, 0xb6, 0x40, 0x8e, 0xc7, 0x6e, 0x05, 0xff, 0x4c, 0xe2, ++ 0xbe, 0x17, 0xd7, 0xdb, 0x71, 0xbd, 0x4d, 0xf9, 0x15, 0xe5, 0xb1, 0xbb, ++ 0x8d, 0xdf, 0x1e, 0xb3, 0x66, 0x20, 0x73, 0xe5, 0xb1, 0x3b, 0x01, 0x17, ++ 0xef, 0x81, 0x3f, 0x6f, 0x54, 0xcd, 0x7d, 0xb9, 0x76, 0x2c, 0x4e, 0x7a, ++ 0x7c, 0xbb, 0x36, 0x83, 0xfb, 0x6d, 0x18, 0xf3, 0x4b, 0x35, 0xe6, 0xe5, ++ 0x5a, 0x3f, 0xc6, 0x3c, 0xa1, 0xc6, 0x54, 0x36, 0xc7, 0xfc, 0x10, 0xf7, ++ 0x1f, 0xc6, 0x18, 0xc8, 0x19, 0xa4, 0xc7, 0xf6, 0xf6, 0xe1, 0xf7, 0x06, ++ 0xfa, 0xee, 0x45, 0xdf, 0x3a, 0xfa, 0xf6, 0xe2, 0xfe, 0x47, 0x5b, 0xd6, ++ 0x65, 0xde, 0xe1, 0x49, 0x3c, 0x07, 0x4e, 0xdc, 0xef, 0xe3, 0xf9, 0x87, ++ 0xf1, 0xfb, 0xfe, 0x96, 0x31, 0xcd, 0x2d, 0xf7, 0x51, 0xae, 0xe1, 0x3f, ++ 0x28, 0xf8, 0xaf, 0xc5, 0xee, 0xa4, 0x85, 0x58, 0xb3, 0xd0, 0x93, 0xe5, ++ 0x2a, 0xe3, 0x82, 0x84, 0x7c, 0x76, 0xb9, 0x4f, 0x1e, 0x59, 0x66, 0x3c, ++ 0xe0, 0xc8, 0x5c, 0x55, 0xc5, 0x00, 0xb9, 0x2e, 0xd8, 0x82, 0xd5, 0xd6, ++ 0x2e, 0x39, 0xb8, 0x9c, 0xc2, 0x38, 0x09, 0xba, 0x65, 0x64, 0xf2, 0x4d, ++ 0x15, 0xb7, 0x0f, 0xe1, 0x9e, 0x7a, 0xa0, 0x0f, 0xd7, 0xbd, 0xd4, 0x59, ++ 0xf0, 0xff, 0x5d, 0xf8, 0xf8, 0x91, 0xcf, 0x3f, 0x24, 0xcf, 0xb5, 0x3e, ++ 0x14, 0x27, 0x1d, 0x5f, 0xde, 0x84, 0xe1, 0x8f, 0xb6, 0xc0, 0xa0, 0x72, ++ 0x23, 0xe2, 0x9d, 0x61, 0x9e, 0x63, 0x97, 0x14, 0x97, 0xed, 0x61, 0x26, ++ 0x2c, 0x46, 0x55, 0xfe, 0x43, 0x46, 0x4d, 0xde, 0x63, 0x3c, 0x8e, 0xf8, ++ 0x26, 0x16, 0x8c, 0xc0, 0x16, 0xea, 0x3c, 0x48, 0x1e, 0xf0, 0xe5, 0x3b, ++ 0xf2, 0x20, 0xfb, 0xaf, 0xcb, 0x83, 0xdc, 0x1d, 0xd7, 0x3a, 0xac, 0x4f, ++ 0x86, 0xcf, 0xa4, 0x8c, 0x9e, 0x87, 0x6f, 0xbd, 0xe4, 0x42, 0x47, 0x24, ++ 0xcd, 0x3d, 0xe5, 0x03, 0x7a, 0xcf, 0x66, 0x3f, 0x5b, 0x3c, 0xcb, 0x51, ++ 0x26, 0x70, 0xdf, 0x24, 0x5f, 0xa4, 0x8d, 0xdd, 0x38, 0x45, 0x3f, 0x12, ++ 0xcf, 0x09, 0x33, 0x71, 0xd9, 0xc9, 0x6f, 0x53, 0xae, 0xf4, 0x8e, 0x81, ++ 0xdf, 0xe8, 0xff, 0x7f, 0xde, 0xec, 0x93, 0x7b, 0xfc, 0xf2, 0x96, 0x3d, ++ 0xc2, 0xa6, 0x2d, 0x0e, 0xc9, 0x02, 0x9e, 0x65, 0xcf, 0x88, 0x54, 0x5a, ++ 0xb4, 0x5b, 0xe3, 0xb2, 0x7f, 0xf9, 0x5a, 0x8c, 0x75, 0xd6, 0x67, 0x4c, ++ 0xd5, 0x0f, 0xbb, 0x38, 0x92, 0x3a, 0x22, 0xc4, 0x23, 0x7c, 0x1e, 0xc6, ++ 0xa5, 0xd8, 0x5f, 0x88, 0xfd, 0x85, 0xd8, 0x5f, 0x88, 0xfd, 0x85, 0xd8, ++ 0xdf, 0xc9, 0xcd, 0xfd, 0x45, 0x7b, 0x78, 0xbe, 0xfd, 0x74, 0x8d, 0x2d, ++ 0xe1, 0xef, 0x93, 0x99, 0x73, 0xbc, 0x86, 0x9e, 0xed, 0xa7, 0xfe, 0x8d, ++ 0xf0, 0xfe, 0x9b, 0x5b, 0x60, 0x22, 0x6e, 0x86, 0xe8, 0x57, 0x25, 0x99, ++ 0xdd, 0x3b, 0x06, 0x7c, 0x96, 0x19, 0x6f, 0xb5, 0x26, 0xa5, 0xb4, 0xa8, ++ 0xe7, 0xcc, 0xb5, 0x02, 0x39, 0xb0, 0xb8, 0x0b, 0x70, 0xde, 0x0e, 0xb8, ++ 0x5c, 0x79, 0xa4, 0x35, 0x32, 0xd6, 0x04, 0x5c, 0xe5, 0x45, 0xbe, 0x3b, ++ 0x29, 0xb4, 0x31, 0x33, 0x80, 0xe7, 0x48, 0xeb, 0x66, 0xb8, 0x41, 0xbc, ++ 0xa7, 0x70, 0x93, 0x56, 0x3c, 0x5a, 0x71, 0xf9, 0x7c, 0xd2, 0xd8, 0x98, ++ 0x9c, 0x81, 0xe5, 0x46, 0x1b, 0x76, 0xec, 0x3a, 0x1b, 0x16, 0xe1, 0xf4, ++ 0x9d, 0xf0, 0xff, 0x64, 0xbf, 0x7e, 0x07, 0x79, 0xe7, 0x9d, 0xc6, 0x9c, ++ 0x33, 0x63, 0xf8, 0x7c, 0xeb, 0xb3, 0x1f, 0xf6, 0x47, 0xf4, 0x1b, 0x59, ++ 0xba, 0xd9, 0xf3, 0xe1, 0x1d, 0xd7, 0xe6, 0xde, 0x6c, 0xed, 0x5f, 0xf6, ++ 0x47, 0x7b, 0xbc, 0xf1, 0x19, 0x75, 0xd1, 0x98, 0x8a, 0x17, 0x63, 0xc1, ++ 0x13, 0xf6, 0xb5, 0x3d, 0xe6, 0xed, 0xb9, 0x56, 0xc9, 0xd6, 0x7b, 0xe4, ++ 0x18, 0x3c, 0x6b, 0x5d, 0xdc, 0xe9, 0x28, 0xdb, 0x99, 0x87, 0xef, 0x0f, ++ 0x3a, 0xaf, 0xf0, 0xfa, 0x16, 0xb4, 0x9d, 0x73, 0x53, 0xa0, 0x49, 0x1e, ++ 0x63, 0xb9, 0xc6, 0xd6, 0xf9, 0x8c, 0x5b, 0x79, 0xed, 0x1c, 0x2e, 0x54, ++ 0x7d, 0x99, 0xaf, 0xc7, 0x31, 0x26, 0x93, 0x0f, 0xe5, 0x3e, 0xc4, 0xa1, ++ 0x99, 0x83, 0xe4, 0xfd, 0x72, 0x32, 0x33, 0x2d, 0xf2, 0xa0, 0x54, 0xea, ++ 0x9f, 0x42, 0x6c, 0xd5, 0x96, 0x07, 0x60, 0x2b, 0x3f, 0x87, 0xb8, 0x58, ++ 0xce, 0xc3, 0xb5, 0x3c, 0x8f, 0x20, 0xe5, 0x7c, 0x52, 0xec, 0x67, 0x86, ++ 0x24, 0x7e, 0x3a, 0x25, 0xce, 0x69, 0xea, 0xe6, 0xac, 0xfb, 0x00, 0x5c, ++ 0x54, 0x5b, 0x2e, 0xdd, 0x8b, 0x58, 0x73, 0x32, 0x2f, 0x59, 0xf8, 0x9d, ++ 0x7b, 0xdc, 0x26, 0xda, 0x8a, 0x64, 0xc7, 0x9e, 0x13, 0x8c, 0x3d, 0x8f, ++ 0xb1, 0x98, 0xd7, 0x73, 0x36, 0x8d, 0xdf, 0xa0, 0xf4, 0x9e, 0x25, 0x0c, ++ 0xc3, 0xa6, 0x25, 0x9d, 0x23, 0x3d, 0x9c, 0x08, 0x07, 0xe0, 0x1f, 0xbd, ++ 0xa8, 0x74, 0x30, 0xf5, 0xb1, 0x07, 0x7d, 0xac, 0x74, 0xb1, 0x75, 0x68, ++ 0x1f, 0x61, 0x27, 0xdc, 0xe0, 0xc7, 0x25, 0x49, 0x24, 0x83, 0x9f, 0xcb, ++ 0xb2, 0xf2, 0x53, 0x69, 0x17, 0xee, 0xa1, 0xaf, 0xff, 0x75, 0x68, 0x46, ++ 0x5c, 0xe7, 0xb0, 0x87, 0x50, 0xa6, 0xf7, 0x15, 0x06, 0x34, 0x0f, 0x3d, ++ 0x28, 0xce, 0xd2, 0x57, 0x10, 0x2f, 0x1c, 0x97, 0x05, 0x3f, 0xe3, 0x96, ++ 0xed, 0xb0, 0x1d, 0xf3, 0xbc, 0x14, 0x63, 0x62, 0x27, 0x58, 0x56, 0xb2, ++ 0xb3, 0x7f, 0x89, 0x63, 0x8e, 0x43, 0x86, 0xbb, 0x80, 0xc7, 0x6e, 0x39, ++ 0x91, 0xcc, 0x84, 0x45, 0xc8, 0x9a, 0xed, 0xed, 0x94, 0xe1, 0x26, 0xdb, ++ 0x01, 0x19, 0x3e, 0xf7, 0x06, 0x78, 0x8c, 0xd7, 0x20, 0xf1, 0x19, 0xf6, ++ 0x0f, 0xa3, 0x65, 0xbf, 0x27, 0x88, 0x15, 0xb1, 0x56, 0x52, 0x86, 0xe1, ++ 0x4b, 0x9e, 0xc8, 0x3d, 0x08, 0xbf, 0x04, 0x71, 0x7f, 0xce, 0x95, 0x72, ++ 0x23, 0x90, 0x66, 0x15, 0xba, 0xb0, 0x75, 0x54, 0x2a, 0x55, 0xe8, 0xeb, ++ 0xd6, 0x1c, 0xda, 0x0d, 0xb4, 0x8f, 0xa1, 0x7d, 0x13, 0x2d, 0x61, 0x3f, ++ 0x2a, 0xcd, 0x86, 0x74, 0x49, 0x2f, 0xd7, 0xf8, 0x2d, 0x03, 0x33, 0x7c, ++ 0xd2, 0x7d, 0x47, 0xe1, 0x0f, 0x45, 0xfd, 0x47, 0xa1, 0x68, 0x1f, 0xc5, ++ 0x2f, 0x50, 0xf7, 0x76, 0x10, 0xca, 0x7c, 0x6e, 0x92, 0x3a, 0xd6, 0x3a, ++ 0x91, 0x7b, 0xcc, 0xac, 0xf3, 0x28, 0xde, 0x77, 0x05, 0xef, 0x46, 0x4c, ++ 0x0c, 0x1f, 0xe7, 0x90, 0x7f, 0x5c, 0xbe, 0xe0, 0x7f, 0x40, 0x26, 0x06, ++ 0x12, 0x61, 0x22, 0xe0, 0xfe, 0xe9, 0x2f, 0xde, 0x6c, 0xff, 0xd1, 0xbe, ++ 0xb9, 0xe7, 0x3e, 0xec, 0x65, 0xbb, 0xf6, 0xf3, 0xec, 0xa7, 0x4c, 0x8c, ++ 0x65, 0xc9, 0xf0, 0x28, 0xd7, 0x0b, 0x24, 0xb6, 0x34, 0xea, 0xe6, 0x6c, ++ 0xfa, 0x58, 0x59, 0xfc, 0x8e, 0x83, 0x67, 0xbc, 0x53, 0xc3, 0x76, 0x2f, ++ 0x60, 0xc2, 0xb3, 0x26, 0xdf, 0x83, 0xf8, 0x61, 0xef, 0xab, 0xd8, 0x5b, ++ 0x28, 0xdd, 0x7b, 0x03, 0xb9, 0xda, 0xe2, 0xb5, 0x88, 0x7d, 0xfe, 0x41, ++ 0xf9, 0xf3, 0xfa, 0x15, 0x39, 0x59, 0x7f, 0x50, 0x5e, 0x47, 0xbb, 0x50, ++ 0x0f, 0x81, 0x47, 0x0f, 0x3a, 0x82, 0x6b, 0xb4, 0x41, 0x17, 0xea, 0xeb, ++ 0x3b, 0x53, 0x73, 0xa0, 0xdf, 0x8c, 0xdb, 0x96, 0xb3, 0x7e, 0x28, 0x67, ++ 0x27, 0x31, 0xa7, 0xd1, 0x23, 0xf1, 0x67, 0xb9, 0xdf, 0x7e, 0x29, 0xd6, ++ 0x43, 0x29, 0xe5, 0x24, 0x8c, 0x07, 0xbd, 0x52, 0x84, 0xaf, 0x0b, 0x9f, ++ 0xe9, 0xb8, 0xce, 0x87, 0xd1, 0xdf, 0xc3, 0x7d, 0xeb, 0x17, 0x56, 0x73, ++ 0xd3, 0xaf, 0xbe, 0x68, 0x7d, 0xbb, 0xe5, 0x29, 0x5b, 0xf2, 0xe2, 0x0d, ++ 0xf2, 0x46, 0x1e, 0xb9, 0x6c, 0x35, 0x1b, 0x4a, 0xe6, 0x8c, 0x6c, 0x60, ++ 0x6e, 0x8b, 0xfe, 0xe4, 0x86, 0xe1, 0x43, 0xe5, 0x37, 0x90, 0x2e, 0xf0, ++ 0x09, 0x7f, 0x26, 0xf0, 0x41, 0x94, 0x3d, 0x78, 0x41, 0xe5, 0xeb, 0xb4, ++ 0x3f, 0xde, 0x00, 0xac, 0xc5, 0x64, 0x06, 0x50, 0x89, 0x34, 0x1a, 0x5f, ++ 0x51, 0xb8, 0x62, 0x4e, 0xbf, 0x5e, 0x23, 0x7e, 0x33, 0xae, 0x6d, 0x7b, ++ 0x26, 0xef, 0xe2, 0x81, 0x3e, 0xd1, 0xf3, 0x0c, 0xfc, 0xf2, 0xe3, 0xe2, ++ 0x4e, 0xf4, 0x62, 0x4f, 0xbc, 0x16, 0x99, 0xbe, 0xb0, 0xd5, 0xa7, 0x89, ++ 0x7c, 0x93, 0x2e, 0xa9, 0x2c, 0xc7, 0x41, 0xcb, 0x3e, 0x39, 0x51, 0x75, ++ 0xe5, 0x24, 0xf8, 0xe8, 0xf7, 0x61, 0x7b, 0x4f, 0xc1, 0xd6, 0x32, 0xbf, ++ 0x63, 0x05, 0x3f, 0x98, 0x1a, 0x5e, 0x65, 0xfb, 0x67, 0x53, 0xd9, 0x06, ++ 0xdb, 0xd7, 0x4c, 0x7c, 0xfc, 0x23, 0x13, 0x37, 0x6f, 0x4c, 0xed, 0x56, ++ 0xed, 0x1b, 0x53, 0x63, 0xaa, 0x7d, 0x13, 0x71, 0xf8, 0x66, 0x2e, 0x46, ++ 0xf9, 0x36, 0x85, 0x5c, 0x4e, 0x4a, 0x55, 0x65, 0xdb, 0x9d, 0x23, 0xe0, ++ 0xa7, 0xb9, 0x16, 0x63, 0x2c, 0x4f, 0x4e, 0xac, 0x05, 0x80, 0x19, 0xba, ++ 0x21, 0xf0, 0xd1, 0x8a, 0xf9, 0x8b, 0xe6, 0x76, 0x31, 0x0f, 0x49, 0x9a, ++ 0x99, 0xb8, 0xc6, 0x67, 0x5c, 0xd3, 0xf9, 0xc7, 0xf5, 0xc0, 0x9b, 0xb4, ++ 0xa1, 0x6f, 0x33, 0x3e, 0x73, 0xca, 0x39, 0xce, 0xf5, 0x18, 0x13, 0xcb, ++ 0xfa, 0xb2, 0x24, 0x12, 0xc1, 0xbf, 0x95, 0xc4, 0x33, 0xed, 0xf6, 0x5f, ++ 0x42, 0xe7, 0x84, 0x88, 0x27, 0x6d, 0x0b, 0xfd, 0xab, 0x7c, 0x46, 0x7d, ++ 0xb2, 0xc7, 0xbd, 0x0a, 0x9e, 0xcb, 0x1f, 0x16, 0xf9, 0x1e, 0xfa, 0xe0, ++ 0x07, 0x82, 0x06, 0xff, 0x0e, 0x34, 0x30, 0x34, 0x51, 0x7d, 0x1c, 0xc7, ++ 0x38, 0x8d, 0xfb, 0xd8, 0xe3, 0x76, 0x63, 0x7e, 0x63, 0x95, 0x73, 0x32, ++ 0x93, 0x98, 0x8a, 0x79, 0x7a, 0x7f, 0x07, 0x72, 0x63, 0x72, 0xa9, 0x2a, ++ 0xc6, 0xcf, 0xfe, 0x15, 0xe6, 0xe8, 0x7c, 0x58, 0x59, 0x02, 0xd8, 0x56, ++ 0xfc, 0xaa, 0x59, 0x75, 0xe6, 0x30, 0x93, 0x22, 0xd8, 0x9e, 0xac, 0x57, ++ 0xff, 0x53, 0x17, 0xed, 0x65, 0xc1, 0xe3, 0xf5, 0x24, 0xc6, 0x20, 0x7e, ++ 0x08, 0x68, 0xef, 0xb9, 0xa7, 0x4e, 0x5c, 0xe8, 0xbf, 0x32, 0x68, 0x61, ++ 0xf6, 0xa8, 0xfe, 0xf4, 0x7b, 0x30, 0xdf, 0xbc, 0xa7, 0x04, 0x83, 0x5e, ++ 0xc4, 0xfb, 0xb3, 0xe7, 0x1d, 0x87, 0x39, 0x81, 0xe1, 0xf3, 0x10, 0x2b, ++ 0xc5, 0x6f, 0x88, 0x57, 0x5a, 0x11, 0xaf, 0x45, 0xf1, 0x0c, 0x79, 0x8b, ++ 0x38, 0xc8, 0x84, 0x17, 0x81, 0xec, 0x81, 0xe0, 0x15, 0x79, 0xe8, 0x8c, ++ 0xde, 0xb3, 0x7d, 0x0e, 0x51, 0x28, 0xfc, 0x81, 0xab, 0xcb, 0x19, 0x7f, ++ 0x43, 0x98, 0x07, 0xf4, 0xc1, 0x2b, 0x17, 0xba, 0x20, 0xd3, 0x93, 0x79, ++ 0xdb, 0xed, 0xd6, 0x3e, 0x33, 0xfc, 0x00, 0xe6, 0x1d, 0xaa, 0x79, 0xcc, ++ 0xe9, 0x96, 0xdf, 0x71, 0x70, 0xdd, 0xe2, 0x3d, 0xfc, 0x1f, 0x47, 0xc3, ++ 0x57, 0x31, 0x38, 0x44, 0x4c, 0x01, 0xdd, 0x45, 0x1c, 0x5a, 0xf2, 0x10, ++ 0xb4, 0xbd, 0x60, 0xfd, 0x61, 0xf3, 0xae, 0xe1, 0x73, 0x11, 0x6f, 0x00, ++ 0xee, 0x33, 0x88, 0x73, 0x97, 0x1d, 0x93, 0x13, 0xa5, 0x8e, 0xe1, 0xf3, ++ 0x77, 0xe2, 0x57, 0xee, 0x87, 0x73, 0x53, 0x2a, 0x37, 0x47, 0xde, 0x3a, ++ 0x68, 0x78, 0xeb, 0x51, 0xf0, 0xd6, 0x51, 0xc5, 0x5b, 0x6d, 0xf9, 0x4b, ++ 0xdf, 0x93, 0xaf, 0xde, 0x94, 0xbf, 0xb6, 0xfe, 0xf5, 0x01, 0x5e, 0xfe, ++ 0x06, 0x64, 0xfe, 0x6b, 0x78, 0x2f, 0xec, 0x4f, 0xa5, 0x9a, 0xc9, 0xcf, ++ 0xd0, 0x47, 0x82, 0x3d, 0xa9, 0x20, 0x3e, 0x1b, 0x3e, 0x3f, 0xa4, 0xc6, ++ 0x0c, 0xc3, 0xb6, 0x34, 0xc1, 0x6f, 0xc4, 0x6f, 0xa5, 0x0a, 0x3d, 0x7c, ++ 0x3e, 0x0e, 0xfb, 0x45, 0x99, 0x95, 0x01, 0x1b, 0xba, 0x81, 0xe3, 0x9b, ++ 0x90, 0x9d, 0xe1, 0xf3, 0xf0, 0x3f, 0x41, 0x33, 0xae, 0xd5, 0x04, 0x9f, ++ 0x73, 0x7e, 0xb3, 0x3a, 0xa6, 0xe6, 0x35, 0xab, 0xe3, 0x68, 0xa1, 0xdf, ++ 0x73, 0xbe, 0x8c, 0x9e, 0xcf, 0x49, 0xfa, 0xbc, 0x25, 0xe5, 0xe9, 0x76, ++ 0x3b, 0x01, 0xd8, 0xc7, 0xce, 0xef, 0x94, 0x0d, 0x95, 0xbf, 0x4d, 0xa8, ++ 0x9c, 0xee, 0x42, 0x6e, 0x1a, 0xb2, 0x49, 0xfc, 0x21, 0xde, 0x3f, 0x5f, ++ 0x82, 0x9d, 0x2c, 0xc9, 0x89, 0x65, 0xe2, 0x87, 0xb9, 0xf2, 0x75, 0xc4, ++ 0xa1, 0x19, 0xe8, 0xb2, 0xc3, 0x32, 0x57, 0xef, 0x86, 0x2e, 0x73, 0x60, ++ 0x0b, 0xff, 0x31, 0x68, 0x34, 0x42, 0x7e, 0x00, 0x5e, 0x02, 0xac, 0x5d, ++ 0x82, 0xff, 0x5a, 0x92, 0xd2, 0xf2, 0xb5, 0xf1, 0x65, 0xe9, 0x86, 0x4c, ++ 0x1d, 0x96, 0x23, 0x75, 0xae, 0xe3, 0xb8, 0x15, 0xd9, 0xcd, 0x58, 0xd6, ++ 0xdd, 0x8f, 0x75, 0x60, 0xc3, 0x3b, 0xfe, 0x28, 0x7f, 0xf9, 0x77, 0xe1, ++ 0xc9, 0x48, 0xee, 0x12, 0x61, 0x57, 0x30, 0x6d, 0xad, 0xe7, 0xc4, 0x99, ++ 0xcd, 0x7d, 0xc2, 0xfa, 0x5e, 0x2e, 0x67, 0x5d, 0xce, 0xe5, 0xad, 0x2b, ++ 0xb9, 0x92, 0xf5, 0x0a, 0x6c, 0x53, 0x73, 0xed, 0x7f, 0x81, 0x7f, 0x3c, ++ 0x99, 0xe7, 0xd9, 0xdd, 0x26, 0x0d, 0x5d, 0x95, 0x3f, 0xeb, 0x0a, 0xde, ++ 0x94, 0x57, 0xaa, 0xf4, 0x23, 0xda, 0xf7, 0xcd, 0xfa, 0xe1, 0xad, 0x80, ++ 0xcf, 0x3d, 0xa0, 0xf2, 0xc8, 0xd7, 0x6c, 0x47, 0x57, 0x00, 0xd9, 0x52, ++ 0xb6, 0xa3, 0x8f, 0xb6, 0xc3, 0x2f, 0xca, 0x76, 0x59, 0xaf, 0x53, 0x77, ++ 0x43, 0x06, 0x85, 0x32, 0x83, 0xfb, 0x86, 0x2b, 0x5f, 0xad, 0x45, 0xfc, ++ 0xc4, 0x3d, 0x57, 0xde, 0xd7, 0x23, 0x31, 0x39, 0xa8, 0x6c, 0x76, 0xbf, ++ 0x5c, 0x5a, 0x45, 0xbc, 0x04, 0xcf, 0xc1, 0xbe, 0x43, 0xe7, 0x6f, 0x19, ++ 0x4b, 0xcb, 0x4e, 0xe6, 0x03, 0x2e, 0x01, 0x5f, 0x3c, 0xeb, 0xc2, 0x5e, ++ 0x77, 0x72, 0x57, 0xd1, 0xfd, 0x38, 0xe4, 0x92, 0xd7, 0x96, 0x14, 0xe1, ++ 0xff, 0xf0, 0xcc, 0xad, 0x88, 0x78, 0x72, 0xbd, 0xba, 0x07, 0xb0, 0x21, ++ 0x36, 0x9a, 0xb6, 0xa4, 0xdb, 0xdb, 0x2d, 0xcc, 0xb7, 0x37, 0xa1, 0x1b, ++ 0x62, 0xc1, 0xab, 0x6a, 0x6c, 0xb7, 0xc7, 0xd8, 0xe5, 0x41, 0x29, 0xab, ++ 0x73, 0x35, 0xb4, 0xab, 0x1a, 0x8e, 0x22, 0xe2, 0xdc, 0xf2, 0x78, 0x0f, ++ 0xed, 0xdd, 0x58, 0x48, 0x3d, 0x90, 0xd4, 0x3e, 0xe7, 0xfa, 0xf2, 0x46, ++ 0x37, 0x6d, 0xfd, 0x01, 0x7f, 0x12, 0x78, 0xe0, 0x35, 0x9f, 0x67, 0x7c, ++ 0x2a, 0x41, 0x27, 0xf8, 0xfe, 0xd4, 0x82, 0x37, 0x62, 0x64, 0xae, 0x0e, ++ 0x9e, 0x3f, 0x2a, 0xff, 0x6a, 0x6d, 0x4e, 0xfe, 0x68, 0x6d, 0x06, 0x7e, ++ 0xcb, 0xc3, 0xf0, 0x5b, 0x3e, 0x03, 0x99, 0x3e, 0x0c, 0x99, 0x7e, 0x0c, ++ 0x72, 0x30, 0xad, 0xf2, 0x14, 0xf5, 0x6a, 0xe6, 0xf9, 0x50, 0xe5, 0x8d, ++ 0xde, 0x84, 0x0c, 0x4c, 0x88, 0x83, 0x58, 0x63, 0x1e, 0x76, 0x22, 0xe9, ++ 0xb5, 0xef, 0x83, 0x4f, 0x02, 0xda, 0x87, 0x19, 0x47, 0xf1, 0x8c, 0xe7, ++ 0x3e, 0x0e, 0xdc, 0xbe, 0x2f, 0xc8, 0xd4, 0x49, 0xf2, 0xb3, 0xf5, 0x31, ++ 0x29, 0x5f, 0xc0, 0xf8, 0xa5, 0x3e, 0xe0, 0x90, 0xb6, 0x32, 0x73, 0xaa, ++ 0x2c, 0x17, 0xc1, 0x27, 0x79, 0xe1, 0xb9, 0x72, 0x25, 0x99, 0xf9, 0xa6, ++ 0xc8, 0xa4, 0xec, 0x5d, 0x04, 0x8f, 0x2f, 0xda, 0x88, 0x57, 0x74, 0x7c, ++ 0x3d, 0x7c, 0x21, 0x10, 0x7b, 0x89, 0xba, 0x69, 0x87, 0x89, 0x61, 0xb4, ++ 0xfd, 0x6f, 0xd0, 0x4e, 0xd6, 0xf8, 0xbe, 0x27, 0x64, 0x0e, 0x36, 0x16, ++ 0x31, 0x04, 0x74, 0xb8, 0x97, 0xc2, 0x3b, 0x13, 0xb3, 0x17, 0xdc, 0xc4, ++ 0xdc, 0x05, 0xae, 0x93, 0x90, 0xd8, 0x22, 0x69, 0xcd, 0x75, 0x20, 0x13, ++ 0x58, 0x3b, 0xbb, 0x48, 0xbc, 0xed, 0xc1, 0xbc, 0xbf, 0x15, 0xe5, 0xf0, ++ 0x11, 0xf7, 0x68, 0x7d, 0x81, 0x18, 0xa8, 0xc3, 0x46, 0x82, 0x1e, 0xd0, ++ 0x27, 0xf9, 0xa6, 0xb6, 0x77, 0x25, 0x65, 0x0f, 0xb5, 0x2d, 0x3c, 0x2c, ++ 0x7f, 0x91, 0x90, 0x5e, 0x4f, 0xed, 0x27, 0xb6, 0x74, 0x91, 0xf6, 0x1f, ++ 0xef, 0xe0, 0x9c, 0x78, 0x07, 0xdc, 0x39, 0xe8, 0xa1, 0x87, 0x13, 0xc4, ++ 0xfd, 0x6f, 0xc0, 0xde, 0x0e, 0xab, 0xf7, 0xb2, 0xdf, 0xc7, 0x7e, 0x64, ++ 0x90, 0x59, 0x09, 0x1b, 0xfe, 0xe4, 0xc7, 0x95, 0x3e, 0x9b, 0x80, 0x0e, ++ 0x73, 0x65, 0x75, 0x37, 0x69, 0x83, 0xd8, 0xff, 0x39, 0xde, 0x93, 0x46, ++ 0xa4, 0xb7, 0x3e, 0x53, 0xaa, 0xac, 0x81, 0x4e, 0xfd, 0x43, 0xd2, 0x58, ++ 0xe3, 0xb3, 0x94, 0xe2, 0x6d, 0x07, 0x34, 0x58, 0xa8, 0xb6, 0xef, 0x2b, ++ 0xf8, 0x21, 0x38, 0x8f, 0x38, 0x27, 0x3e, 0x88, 0xf7, 0x71, 0xc0, 0x46, ++ 0x1c, 0xf7, 0xd3, 0x36, 0xa3, 0x6f, 0x3b, 0xe2, 0x54, 0xf2, 0x37, 0xda, ++ 0xc6, 0x76, 0xf8, 0x9c, 0x94, 0xab, 0x27, 0x78, 0xe6, 0x86, 0xbd, 0x6b, ++ 0x9e, 0x2e, 0x81, 0xa7, 0x2a, 0x88, 0x81, 0x2f, 0x2d, 0x32, 0xdf, 0xff, ++ 0x8a, 0x7c, 0x91, 0x3a, 0x15, 0xfc, 0x55, 0x59, 0x9d, 0x00, 0xaf, 0xf5, ++ 0x43, 0x7f, 0xb6, 0xdb, 0x87, 0xe1, 0x3f, 0x1f, 0xf3, 0x89, 0xa3, 0x57, ++ 0x81, 0xa3, 0xee, 0xd4, 0x31, 0xd0, 0x6b, 0xe5, 0xb9, 0x8f, 0x29, 0xfd, ++ 0x01, 0xdf, 0x47, 0xd9, 0x31, 0x9d, 0xa7, 0xf1, 0xe9, 0x2b, 0x29, 0x99, ++ 0x2e, 0x78, 0xd4, 0x8f, 0x0b, 0xc0, 0xc3, 0xb8, 0xd2, 0xe7, 0x5a, 0xd7, ++ 0xf4, 0x48, 0xf9, 0x70, 0x1e, 0xfb, 0x9d, 0xdc, 0x32, 0x2e, 0x87, 0x7b, ++ 0xf8, 0x82, 0xad, 0xa7, 0x13, 0xcc, 0x3b, 0xc6, 0x82, 0x49, 0x39, 0xbb, ++ 0xfb, 0xa0, 0x9c, 0xdb, 0x9d, 0x99, 0x9c, 0xb1, 0x69, 0x23, 0x0e, 0x4a, ++ 0xe3, 0xb9, 0xbc, 0xac, 0xd4, 0xb4, 0xad, 0x9e, 0xf5, 0x26, 0x99, 0xcf, ++ 0xc6, 0x7d, 0xc0, 0x3c, 0x2d, 0xc6, 0x47, 0x7a, 0x38, 0xda, 0x53, 0x81, ++ 0x7b, 0x82, 0xce, 0xd0, 0xb6, 0xd8, 0xb6, 0xbb, 0x41, 0x1f, 0xea, 0x89, ++ 0x4f, 0xa1, 0xbf, 0x00, 0x5d, 0x47, 0x7a, 0x66, 0x41, 0xbb, 0x3f, 0x54, ++ 0x74, 0x2a, 0xfa, 0x8c, 0x13, 0x38, 0x27, 0x93, 0x9a, 0x45, 0xff, 0xb4, ++ 0xd0, 0xa6, 0x72, 0x6f, 0xd1, 0x7a, 0x81, 0x81, 0x3f, 0x66, 0xf2, 0xaa, ++ 0x7f, 0x9c, 0xa0, 0x4c, 0xc6, 0xbc, 0xa8, 0x7f, 0x8f, 0xcb, 0x7c, 0x1d, ++ 0xdf, 0x51, 0xa9, 0xb1, 0x2f, 0xeb, 0x72, 0x7e, 0xd1, 0xf7, 0xd4, 0xb9, ++ 0xe7, 0x6f, 0x98, 0xf8, 0xfd, 0x30, 0xe2, 0xdb, 0x62, 0xab, 0xeb, 0x3d, ++ 0xec, 0xf1, 0x35, 0xdd, 0xa7, 0xf5, 0xf4, 0x7a, 0xca, 0x35, 0xba, 0xf8, ++ 0x08, 0x74, 0xb1, 0x3d, 0x61, 0x49, 0x17, 0x74, 0xeb, 0x01, 0x19, 0x31, ++ 0x7a, 0x95, 0xfb, 0xe9, 0x57, 0xb6, 0xaf, 0x38, 0x9d, 0x94, 0x93, 0x2b, ++ 0x7f, 0x1d, 0xbe, 0x7e, 0x67, 0x3f, 0xaf, 0x74, 0x13, 0x3f, 0xef, 0xd5, ++ 0x0b, 0xd0, 0x07, 0x35, 0xe8, 0x8a, 0x1a, 0x74, 0x45, 0x0d, 0xba, 0xa2, ++ 0x06, 0x5d, 0x51, 0x83, 0xae, 0xa8, 0x41, 0x57, 0xd4, 0xa6, 0x8d, 0x1d, ++ 0x3d, 0x66, 0x72, 0x52, 0x8c, 0x7f, 0x3a, 0x7d, 0x03, 0xe6, 0xa5, 0x18, ++ 0xdf, 0x64, 0xc2, 0x0d, 0xe0, 0xe6, 0x05, 0x9f, 0xb1, 0x79, 0x5b, 0xfe, ++ 0xbd, 0xdf, 0xb9, 0x7b, 0xe6, 0x41, 0x58, 0x13, 0x22, 0x72, 0x08, 0x38, ++ 0x7b, 0x08, 0x38, 0xfb, 0xf4, 0x0d, 0xb5, 0x1f, 0xac, 0x13, 0x19, 0x09, ++ 0x63, 0x88, 0x5f, 0xa7, 0xaf, 0xc3, 0x1d, 0xe3, 0xf4, 0x77, 0x8b, 0xcd, ++ 0x99, 0x77, 0xf8, 0x39, 0xe9, 0x2d, 0xaf, 0x18, 0xba, 0x16, 0x73, 0xfd, ++ 0xe0, 0x71, 0xfa, 0x72, 0xaf, 0x28, 0x5f, 0xee, 0x80, 0xef, 0xc8, 0xc5, ++ 0x24, 0xed, 0xe7, 0x8f, 0xe5, 0xc8, 0x72, 0xa9, 0x87, 0xe7, 0x6f, 0x0b, ++ 0xb5, 0xdd, 0xb2, 0xae, 0xf4, 0xc5, 0xa7, 0x30, 0x36, 0x90, 0x39, 0xd0, ++ 0x7b, 0x3f, 0xe2, 0xc5, 0x73, 0xb2, 0x27, 0x75, 0x0e, 0xfb, 0xf8, 0x7d, ++ 0xcc, 0x81, 0xbf, 0xdf, 0x2e, 0xa1, 0xef, 0x0a, 0x62, 0x8a, 0xab, 0xc2, ++ 0xeb, 0x3d, 0xee, 0x29, 0x20, 0x31, 0xef, 0x66, 0xdd, 0x37, 0x25, 0xe2, ++ 0x21, 0xf2, 0x0b, 0xf3, 0xf4, 0xcc, 0x0d, 0x33, 0x06, 0xeb, 0x87, 0x8c, ++ 0xfd, 0x18, 0x36, 0x97, 0xef, 0xa0, 0xcc, 0x13, 0xbe, 0x21, 0xbc, 0x33, ++ 0x3d, 0xd3, 0x1d, 0xdc, 0x09, 0x3b, 0x4b, 0x9d, 0xae, 0xe3, 0xa4, 0x22, ++ 0xe6, 0x28, 0xbd, 0xef, 0x47, 0xe7, 0x14, 0x5f, 0x81, 0x4f, 0x93, 0x04, ++ 0x8d, 0xd1, 0xbf, 0x1a, 0xf9, 0xb4, 0x91, 0xef, 0xa2, 0x73, 0xcc, 0xcf, ++ 0x2b, 0xff, 0xa5, 0x00, 0x7b, 0xf5, 0x20, 0xc6, 0x32, 0xc7, 0xd7, 0x6e, ++ 0x1f, 0x85, 0x3e, 0x9a, 0x7f, 0x9a, 0x7a, 0xea, 0x0e, 0x93, 0xcb, 0xa4, ++ 0x7d, 0x15, 0xeb, 0xd5, 0xdc, 0xba, 0x9b, 0x80, 0x6d, 0x9c, 0x06, 0x3f, ++ 0x15, 0xc0, 0x63, 0xb1, 0x7b, 0x0e, 0xc2, 0xd6, 0xaa, 0x73, 0x04, 0xf0, ++ 0x31, 0xdf, 0xfb, 0x29, 0xeb, 0xdf, 0xe4, 0xc6, 0x61, 0x7b, 0x3f, 0x06, ++ 0xdb, 0x3b, 0x88, 0xb5, 0x0a, 0xb0, 0xbf, 0xb4, 0xbd, 0xae, 0xfc, 0xe1, ++ 0x5a, 0x01, 0x7a, 0xe9, 0x77, 0x7a, 0x28, 0x47, 0x07, 0x37, 0xe5, 0xa5, ++ 0x64, 0xe4, 0x69, 0x87, 0x14, 0x55, 0x6e, 0xba, 0xa4, 0xe4, 0xae, 0xb2, ++ 0x4a, 0x9f, 0x03, 0x32, 0xb8, 0x4a, 0xf9, 0xa7, 0xff, 0x48, 0xbd, 0x00, ++ 0x3d, 0xb2, 0xfa, 0x09, 0xb4, 0x07, 0xd1, 0x6a, 0xbf, 0xec, 0xf9, 0xda, ++ 0xed, 0x3d, 0x3a, 0x1f, 0x9a, 0xea, 0xf0, 0xcd, 0x1a, 0xd8, 0xdf, 0x83, ++ 0xac, 0x33, 0x08, 0x77, 0x06, 0x9f, 0xc1, 0x1e, 0x0f, 0x83, 0xbf, 0xa6, ++ 0xc1, 0x5f, 0x07, 0xb1, 0xd7, 0x53, 0xd6, 0xe8, 0xbe, 0x18, 0x6c, 0xf7, ++ 0x71, 0x29, 0x41, 0x67, 0xae, 0xae, 0x84, 0xd6, 0xc4, 0xa2, 0xa8, 0xfb, ++ 0xa2, 0xcf, 0x7a, 0x84, 0x8f, 0x22, 0xb6, 0x4e, 0xc9, 0xd2, 0x9a, 0x63, ++ 0x72, 0x89, 0x0e, 0xfa, 0x68, 0xab, 0xa1, 0x8f, 0x5c, 0xac, 0x55, 0xbb, ++ 0x6b, 0x9b, 0xf4, 0x62, 0xbd, 0xda, 0x27, 0x71, 0xcf, 0x7c, 0xc2, 0x21, ++ 0xeb, 0xfa, 0x7e, 0xe6, 0x2c, 0x32, 0x6e, 0x01, 0x71, 0xa7, 0xe3, 0x31, ++ 0x6f, 0xe1, 0x81, 0x3e, 0x79, 0x29, 0x8e, 0xc2, 0xff, 0x52, 0xfa, 0xb6, ++ 0xd7, 0xe8, 0x5b, 0xe8, 0xb2, 0x7a, 0x20, 0x2b, 0x6b, 0xf4, 0x93, 0x02, ++ 0x15, 0x3b, 0x53, 0x47, 0x95, 0xeb, 0xf0, 0x75, 0xfc, 0xcf, 0x5b, 0x79, ++ 0xb5, 0x66, 0x42, 0x9d, 0xfd, 0x86, 0x2b, 0x62, 0xb9, 0xfb, 0x5e, 0x45, ++ 0xac, 0x9a, 0x83, 0x7c, 0x06, 0xd0, 0x89, 0x2e, 0x74, 0x1e, 0x6d, 0xd6, ++ 0x55, 0xe8, 0x7b, 0xf4, 0x5f, 0x80, 0x7f, 0xf3, 0x34, 0x65, 0xf2, 0x8a, ++ 0xd8, 0xcd, 0x77, 0xcb, 0x8b, 0x30, 0x27, 0x72, 0xd8, 0x9c, 0xeb, 0x8c, ++ 0x03, 0x5e, 0xfd, 0x8e, 0x38, 0x7c, 0xf8, 0x4b, 0xf5, 0x6d, 0x88, 0x07, ++ 0x0f, 0x59, 0xc5, 0x24, 0xfb, 0x42, 0x59, 0xcd, 0xd1, 0xe7, 0x64, 0x5e, ++ 0x24, 0xc1, 0xf8, 0xde, 0xe4, 0x22, 0xb6, 0xc6, 0xa1, 0xb4, 0xf1, 0x2f, ++ 0x8a, 0xea, 0x6f, 0x45, 0x67, 0x43, 0xea, 0x6c, 0x55, 0x86, 0x5b, 0x51, ++ 0xfe, 0x8a, 0x70, 0x5c, 0xb4, 0xca, 0xad, 0x9f, 0xf5, 0x4a, 0x2f, 0x61, ++ 0xe1, 0x9e, 0xf4, 0xfb, 0xec, 0xa5, 0xbd, 0xe6, 0x7d, 0xae, 0x15, 0xdf, ++ 0x97, 0xc2, 0xbe, 0x62, 0xd0, 0x57, 0xd1, 0xbb, 0x32, 0xfd, 0x1a, 0xce, ++ 0x31, 0xf4, 0x6f, 0xe0, 0x39, 0xef, 0xf9, 0x7c, 0x4c, 0x9a, 0x35, 0xb1, ++ 0x62, 0xfb, 0x10, 0x3d, 0xc3, 0x5e, 0x37, 0xa1, 0x63, 0x6c, 0xd8, 0xcb, ++ 0x66, 0xed, 0x31, 0xb4, 0x58, 0xe3, 0xe9, 0x2b, 0x32, 0xab, 0xe3, 0x6d, ++ 0xf8, 0x94, 0x23, 0xca, 0xe6, 0x4e, 0xfb, 0xcc, 0x85, 0x1c, 0x87, 0x3e, ++ 0xbc, 0x13, 0x7d, 0x8c, 0x9b, 0x42, 0x71, 0x3f, 0xf2, 0x95, 0x78, 0x54, ++ 0xef, 0x55, 0xd0, 0x39, 0x02, 0x8c, 0x5d, 0x06, 0x8d, 0xb8, 0x06, 0xed, ++ 0xdb, 0xcf, 0xe5, 0x8b, 0x1d, 0x79, 0x94, 0x82, 0xbd, 0x99, 0x37, 0xc8, ++ 0xb3, 0x4e, 0x6a, 0xa5, 0x46, 0xb9, 0xcc, 0x81, 0x07, 0xf2, 0xf2, 0xcd, ++ 0xb5, 0x5b, 0x81, 0xff, 0xa4, 0xc4, 0x9e, 0x61, 0xbe, 0x9c, 0xb6, 0x60, ++ 0x0f, 0x74, 0xb0, 0x6b, 0x7c, 0x87, 0xa4, 0x38, 0xcf, 0x0c, 0x49, 0xf7, ++ 0xe9, 0x94, 0x74, 0x9d, 0x66, 0x5d, 0x48, 0x96, 0xf5, 0x14, 0xf4, 0x7f, ++ 0x26, 0xdf, 0xd0, 0xe7, 0x97, 0x69, 0xb4, 0xfe, 0x3a, 0x7e, 0x97, 0xb1, ++ 0x6e, 0x37, 0x7c, 0xf7, 0xae, 0xf3, 0x9f, 0x04, 0xae, 0xf4, 0x9a, 0x5b, ++ 0xe7, 0x56, 0xf4, 0x5c, 0x9e, 0xa3, 0xa6, 0x42, 0xc9, 0x62, 0x1e, 0xe7, ++ 0x67, 0x31, 0x37, 0x3b, 0xf9, 0xfa, 0xe6, 0x7c, 0xce, 0xa5, 0x0d, 0x4c, ++ 0x42, 0xe6, 0x6f, 0x93, 0xe6, 0xd7, 0x28, 0xfb, 0xf0, 0xfd, 0xa1, 0xe3, ++ 0xca, 0x2d, 0xb6, 0x7d, 0x68, 0x39, 0x26, 0x6d, 0x9e, 0x0f, 0x9b, 0xe7, ++ 0x9e, 0xb2, 0x8b, 0xce, 0x66, 0xbe, 0x05, 0x71, 0x42, 0x2d, 0x73, 0x0a, ++ 0x46, 0x08, 0xfd, 0xbc, 0x66, 0x2c, 0x85, 0xd8, 0xe2, 0x69, 0xf8, 0x94, ++ 0x0d, 0xb6, 0x3d, 0x52, 0x69, 0x1c, 0x95, 0x19, 0x75, 0xfd, 0x90, 0x1c, ++ 0x72, 0x89, 0xbb, 0xe3, 0xe2, 0x4f, 0x68, 0xff, 0x4b, 0x6c, 0x8d, 0xdb, ++ 0x6e, 0xef, 0xb8, 0x1c, 0xf0, 0x95, 0xcd, 0x70, 0xef, 0x07, 0x8e, 0xcb, ++ 0xad, 0x2e, 0xca, 0x00, 0x60, 0x0f, 0x20, 0x77, 0x79, 0x39, 0xb7, 0x86, ++ 0xb1, 0xa0, 0xd5, 0xfd, 0xbc, 0x6f, 0x00, 0x9f, 0xcc, 0x59, 0x3c, 0x43, ++ 0x7c, 0x72, 0xef, 0xb4, 0x99, 0xc4, 0x29, 0x71, 0x40, 0x3b, 0xcc, 0xdc, ++ 0x5b, 0x66, 0xf2, 0xaa, 0x30, 0x6e, 0x26, 0xce, 0xb8, 0x4e, 0xb4, 0x6f, ++ 0x3d, 0xcf, 0x3e, 0x3b, 0x08, 0x67, 0x32, 0x21, 0xf6, 0x69, 0x57, 0xec, ++ 0xf3, 0x6c, 0xfb, 0xd0, 0xf2, 0x19, 0x40, 0x3a, 0x3b, 0x6c, 0x9e, 0x79, ++ 0xe8, 0x83, 0xdf, 0xf8, 0x14, 0xe5, 0xed, 0x36, 0xc8, 0x39, 0xf3, 0x3e, ++ 0x93, 0xf2, 0xfc, 0xca, 0x8d, 0x32, 0x17, 0x3b, 0xad, 0xfd, 0x90, 0xeb, ++ 0x65, 0x6e, 0xf2, 0x6f, 0x20, 0x73, 0x7c, 0x07, 0xf5, 0x8c, 0x23, 0x5f, ++ 0x4c, 0x66, 0xd2, 0x79, 0x1d, 0x5f, 0xb8, 0x59, 0x7b, 0x34, 0x4d, 0xff, ++ 0xb3, 0xf9, 0xf4, 0xa3, 0xbd, 0xb4, 0x39, 0x4f, 0xf9, 0x11, 0x7f, 0xf5, ++ 0x82, 0xbf, 0xda, 0x52, 0x87, 0x3d, 0xae, 0x78, 0x96, 0xcc, 0x7b, 0xc7, ++ 0x95, 0xff, 0xf8, 0xe9, 0x64, 0x5b, 0x8e, 0xf9, 0x7a, 0xee, 0xbc, 0x8c, ++ 0x1a, 0x1e, 0x57, 0xf1, 0x1a, 0x74, 0x32, 0xe9, 0xc5, 0xfb, 0x5b, 0xc5, ++ 0x1f, 0x38, 0x2e, 0xc3, 0x13, 0x17, 0x89, 0x2f, 0xd0, 0x81, 0xba, 0xe8, ++ 0x1d, 0x73, 0x61, 0xaa, 0x1e, 0xa0, 0x58, 0x25, 0x4c, 0xdb, 0xc0, 0xb7, ++ 0x79, 0xc4, 0x4b, 0xd7, 0xf2, 0x61, 0xd9, 0xd1, 0xb0, 0x1d, 0xc7, 0xbb, ++ 0xcb, 0x88, 0x1f, 0x3e, 0x9d, 0xf4, 0xd2, 0x23, 0xf6, 0x68, 0xea, 0x84, ++ 0xfc, 0x99, 0x82, 0xf5, 0x77, 0x7d, 0xcd, 0x2f, 0x0b, 0xb9, 0x9b, 0xe5, ++ 0xa8, 0x3a, 0xf3, 0xd8, 0x5c, 0xeb, 0xa2, 0xf5, 0x85, 0x96, 0xce, 0x47, ++ 0x5d, 0xcb, 0x65, 0x5f, 0xd3, 0x43, 0x8e, 0xd1, 0x0b, 0x95, 0xfa, 0x87, ++ 0x24, 0xd2, 0x43, 0xf5, 0x1c, 0x68, 0xb5, 0x44, 0x1a, 0xa5, 0x4d, 0xdd, ++ 0x56, 0xa2, 0xc3, 0x37, 0x8e, 0xb3, 0xfe, 0x30, 0x9d, 0xb7, 0xcf, 0x41, ++ 0x37, 0x3c, 0x2d, 0x71, 0x2f, 0x5a, 0xab, 0x07, 0x63, 0x52, 0xe6, 0x9c, ++ 0x62, 0x3b, 0xf3, 0x56, 0x18, 0xf3, 0x61, 0x3c, 0xff, 0x18, 0xc6, 0xd1, ++ 0x7e, 0xf2, 0x7c, 0x80, 0xb6, 0x94, 0xe7, 0xaf, 0x03, 0xaa, 0x1e, 0xb5, ++ 0xd8, 0x78, 0xdc, 0xf4, 0x45, 0x6b, 0xec, 0xeb, 0x18, 0x1f, 0xf5, 0xe9, ++ 0x73, 0x85, 0xbc, 0x1d, 0x57, 0xeb, 0x2f, 0xc0, 0xff, 0x88, 0xce, 0x46, ++ 0xec, 0xe6, 0x94, 0xab, 0xe7, 0x73, 0x1c, 0xed, 0x00, 0xec, 0x4d, 0x0d, ++ 0x36, 0xa8, 0x76, 0xd0, 0xd8, 0xa5, 0x19, 0xd1, 0x36, 0x57, 0xac, 0xfd, ++ 0x39, 0xda, 0xe5, 0xbc, 0x55, 0x50, 0xb5, 0x8f, 0x5c, 0x9f, 0x78, 0x07, ++ 0xef, 0xac, 0x69, 0x1f, 0xd9, 0xce, 0x75, 0xf1, 0x9c, 0x0a, 0xb6, 0x5d, ++ 0xdb, 0xfe, 0x26, 0x6c, 0xff, 0xd9, 0xe5, 0x21, 0x65, 0x37, 0xcf, 0xfa, ++ 0x91, 0x0d, 0x7f, 0xa9, 0xcd, 0x1c, 0x3a, 0x63, 0x74, 0xc6, 0xa6, 0xdf, ++ 0x5a, 0x2b, 0xc1, 0xce, 0xe5, 0xe5, 0x4f, 0xd7, 0x02, 0xf9, 0xce, 0xda, ++ 0x24, 0x62, 0xb4, 0x1c, 0x62, 0x34, 0x1f, 0x31, 0xda, 0x38, 0x6c, 0x9f, ++ 0xa7, 0xce, 0xfa, 0x68, 0xe7, 0x1f, 0xca, 0x09, 0xec, 0x32, 0xfc, 0x99, ++ 0x2a, 0x7c, 0x82, 0xc5, 0xd7, 0x64, 0x15, 0xba, 0xbb, 0x01, 0x1f, 0x60, ++ 0x7e, 0x2d, 0x0b, 0x3b, 0xf4, 0x90, 0xe4, 0x53, 0xe4, 0x7d, 0x3e, 0xcb, ++ 0xfc, 0x54, 0xe4, 0x35, 0x55, 0x43, 0x7a, 0xa9, 0xce, 0x3c, 0xeb, 0x71, ++ 0x79, 0x9c, 0x75, 0x6b, 0x2b, 0xaf, 0xca, 0xb7, 0xab, 0xaf, 0xc9, 0x77, ++ 0x94, 0x9f, 0xf8, 0x51, 0x39, 0xec, 0xd2, 0xf6, 0xe8, 0xf8, 0x6e, 0xa7, ++ 0xa7, 0x79, 0xad, 0x2c, 0xe4, 0xb5, 0x3c, 0x7c, 0x6f, 0xcf, 0x3d, 0xa4, ++ 0x72, 0x9e, 0x12, 0xde, 0x12, 0xf4, 0x86, 0x83, 0xb0, 0x7b, 0xff, 0x48, ++ 0x3c, 0x69, 0x22, 0xee, 0x29, 0xe3, 0xfd, 0xc6, 0x8e, 0x85, 0x65, 0xf8, ++ 0xd1, 0x3f, 0xb5, 0xc7, 0x24, 0xef, 0x24, 0x61, 0x0f, 0x69, 0x03, 0x3d, ++ 0x77, 0xd8, 0xe6, 0xfa, 0xb7, 0xb2, 0xc6, 0xf8, 0xeb, 0x4a, 0xff, 0xd0, ++ 0x2e, 0xe6, 0x68, 0x27, 0xf9, 0x3e, 0xda, 0x19, 0xe6, 0xc2, 0x09, 0x0f, ++ 0x6d, 0xd0, 0xcf, 0xd4, 0xd9, 0x67, 0x79, 0xda, 0x95, 0xc6, 0x0a, 0x75, ++ 0x0f, 0xec, 0xfa, 0xd3, 0xd7, 0x62, 0xb1, 0x43, 0xea, 0x9d, 0x51, 0x7f, ++ 0xe4, 0xab, 0x66, 0xc2, 0x41, 0xbb, 0x01, 0xba, 0x26, 0x81, 0x17, 0xca, ++ 0xb4, 0xe2, 0x2d, 0x13, 0xbb, 0xbf, 0x0a, 0x7f, 0xd1, 0x95, 0x15, 0xbc, ++ 0x67, 0x97, 0x77, 0x05, 0xbc, 0xf1, 0x08, 0xc6, 0xe9, 0xf7, 0xd2, 0x0f, ++ 0x58, 0x7f, 0xff, 0x7b, 0x9d, 0x3f, 0x50, 0xe6, 0xb7, 0xc1, 0xb7, 0xb6, ++ 0x0d, 0x0f, 0x7e, 0xc1, 0xc4, 0x02, 0x90, 0xcf, 0x33, 0x84, 0xbb, 0xc2, ++ 0xf3, 0x0e, 0xf8, 0x55, 0x0b, 0xcc, 0x31, 0xa9, 0x77, 0x3e, 0x90, 0xeb, ++ 0x93, 0xe1, 0xd3, 0x5d, 0x92, 0x7d, 0xc6, 0x06, 0x5f, 0x93, 0x0f, 0xee, ++ 0x93, 0xfd, 0x3e, 0x63, 0xfb, 0x1d, 0xd2, 0x04, 0x8e, 0xe7, 0xd7, 0x60, ++ 0xf7, 0xc6, 0x58, 0x77, 0x76, 0x0f, 0xcf, 0x30, 0x14, 0x1c, 0x4d, 0x77, ++ 0x44, 0x58, 0xef, 0xd1, 0x74, 0x6f, 0x91, 0xca, 0xd3, 0xff, 0x75, 0x9b, ++ 0x8e, 0xd1, 0xb7, 0xde, 0x9f, 0xe9, 0x56, 0xb9, 0x70, 0xeb, 0xef, 0xf5, ++ 0x99, 0x1a, 0xfa, 0x5f, 0x03, 0xf6, 0x68, 0x2c, 0xe1, 0x89, 0x8b, 0xf7, ++ 0x54, 0x9f, 0x8c, 0x40, 0x97, 0x8e, 0xc2, 0x0e, 0xed, 0x3e, 0x3d, 0x24, ++ 0x63, 0xa7, 0xd3, 0x72, 0xc7, 0xe9, 0xc8, 0xd6, 0xff, 0x60, 0x2a, 0x6b, ++ 0xf2, 0xb2, 0xde, 0xaf, 0x99, 0x97, 0xbd, 0x43, 0xad, 0x0f, 0x18, 0x57, ++ 0xa0, 0xdf, 0x92, 0x4f, 0x2a, 0x9f, 0x40, 0xe3, 0xfd, 0xc7, 0xb2, 0x7f, ++ 0x39, 0x2e, 0x07, 0x94, 0x6c, 0x91, 0xd7, 0xe9, 0x7f, 0xdf, 0x8e, 0xb1, ++ 0x19, 0xc8, 0xc2, 0xc3, 0x26, 0x6e, 0xec, 0x05, 0x5e, 0x89, 0x43, 0xd8, ++ 0x2e, 0xc4, 0x92, 0xac, 0xdf, 0x2d, 0xfb, 0x9d, 0xf3, 0x39, 0xf7, 0x83, ++ 0x98, 0x93, 0x87, 0xaf, 0xc0, 0xe7, 0x32, 0x18, 0x93, 0x9b, 0x3d, 0xff, ++ 0x38, 0x9e, 0x53, 0x87, 0x1c, 0x80, 0x0e, 0xd9, 0xfa, 0xbc, 0x80, 0x67, ++ 0x7c, 0xff, 0xad, 0x78, 0xef, 0x90, 0xd1, 0xdd, 0x11, 0x4e, 0x48, 0xd7, ++ 0x41, 0xd6, 0xb0, 0x51, 0x77, 0x4a, 0xc9, 0x65, 0x6e, 0x88, 0x7d, 0xef, ++ 0x37, 0xb4, 0x9e, 0x30, 0xb4, 0xa6, 0x9c, 0x6d, 0x53, 0x35, 0x1b, 0x05, ++ 0x7f, 0x9b, 0x94, 0x92, 0x99, 0x90, 0x67, 0xba, 0xcc, 0xc7, 0xad, 0x56, ++ 0x23, 0x7f, 0x23, 0xbf, 0x93, 0xe7, 0x0a, 0x0b, 0xbe, 0xca, 0x95, 0xa5, ++ 0x63, 0x01, 0xfd, 0x15, 0x3f, 0xc1, 0x7a, 0xe7, 0xa6, 0xaa, 0x87, 0x8f, ++ 0xe1, 0x07, 0x3c, 0x3b, 0x96, 0xb8, 0x1e, 0xfb, 0x42, 0x6d, 0xab, 0xa6, ++ 0xe9, 0xb3, 0xab, 0x31, 0xe9, 0x82, 0x3f, 0x68, 0xee, 0x53, 0xb2, 0x52, ++ 0xbd, 0x6b, 0xc8, 0x0e, 0xfe, 0xe7, 0xad, 0x85, 0xdc, 0x4e, 0xc8, 0x82, ++ 0xf2, 0xeb, 0x21, 0x1b, 0xaf, 0x41, 0x36, 0xe2, 0x26, 0x3e, 0x70, 0x00, ++ 0x23, 0xf7, 0xf9, 0x13, 0xf0, 0xf4, 0xd6, 0x3d, 0x77, 0x99, 0x3d, 0x73, ++ 0xbf, 0xc4, 0x37, 0xe7, 0x47, 0x76, 0x8b, 0x38, 0x4f, 0x98, 0x98, 0x02, ++ 0x76, 0xaa, 0x76, 0xbb, 0x39, 0xb7, 0xe1, 0x35, 0xf4, 0x4e, 0x0d, 0x7a, ++ 0x07, 0xbe, 0xeb, 0x77, 0x6a, 0xd0, 0x3b, 0x35, 0xe8, 0x9d, 0x1a, 0xf4, ++ 0x4e, 0x0d, 0x7a, 0xa7, 0x06, 0xbd, 0x04, 0x9f, 0xe2, 0x05, 0xe8, 0x49, ++ 0xad, 0x03, 0x0f, 0x42, 0x07, 0x2a, 0xdf, 0x8c, 0x7e, 0x4c, 0xdd, 0x0e, ++ 0xba, 0x7f, 0xed, 0x7a, 0xa1, 0x58, 0x10, 0xcd, 0xeb, 0x96, 0xb2, 0x9a, ++ 0x93, 0x96, 0xb9, 0xd6, 0xcd, 0xc6, 0xea, 0x7a, 0xd1, 0x6b, 0xfb, 0xd4, ++ 0xf2, 0x55, 0x50, 0x39, 0x04, 0xea, 0xd8, 0xf7, 0xe2, 0xfd, 0xce, 0xfa, ++ 0x4b, 0xd2, 0x56, 0xd5, 0x05, 0x21, 0xc6, 0x49, 0xc8, 0xd5, 0x65, 0xfa, ++ 0x77, 0x15, 0x99, 0x9f, 0x5c, 0x90, 0xca, 0xa4, 0x25, 0xb3, 0xe3, 0xa0, ++ 0xcd, 0x38, 0x6b, 0xef, 0xef, 0x82, 0xcd, 0x9c, 0xc7, 0x3a, 0x94, 0xbb, ++ 0x7d, 0xa0, 0x87, 0x6b, 0x6a, 0x32, 0x5e, 0x9b, 0x2a, 0xd4, 0xc5, 0xba, ++ 0x5c, 0x65, 0x8e, 0xf1, 0x07, 0x53, 0xaf, 0x2c, 0x53, 0xa6, 0x27, 0x64, ++ 0x65, 0xf2, 0x3e, 0x69, 0x5e, 0x37, 0x1f, 0xf8, 0x47, 0xdc, 0x7b, 0x72, ++ 0x8d, 0x67, 0x9b, 0xdd, 0x32, 0x03, 0x7b, 0xb5, 0xa1, 0x6a, 0x5d, 0x06, ++ 0xa4, 0xa9, 0x78, 0x89, 0x36, 0x61, 0x87, 0xac, 0xab, 0x6b, 0xf6, 0xc7, ++ 0xd1, 0x9f, 0x19, 0xdb, 0x80, 0x6f, 0xf9, 0x7a, 0x95, 0x36, 0x62, 0x9b, ++ 0xd2, 0x7d, 0x2f, 0xd7, 0xa2, 0x7c, 0x1d, 0x6d, 0x0a, 0x73, 0x41, 0xcc, ++ 0x0d, 0xbd, 0xd6, 0x47, 0xdd, 0xf5, 0x72, 0xed, 0x8c, 0xd1, 0x71, 0xbc, ++ 0x3e, 0xdc, 0x13, 0xd5, 0x8b, 0x56, 0x92, 0x61, 0xbb, 0xe2, 0x39, 0xd6, ++ 0xa5, 0xcd, 0x5a, 0xb6, 0xde, 0xed, 0x7a, 0x3c, 0xf9, 0xd6, 0x06, 0x7c, ++ 0xa4, 0xf9, 0xb0, 0xaa, 0xd1, 0x79, 0xb9, 0xb6, 0x7f, 0x9b, 0x9e, 0xe7, ++ 0x98, 0x6f, 0x37, 0xd8, 0xf7, 0x4f, 0xfb, 0x74, 0x1f, 0xcf, 0xd2, 0x77, ++ 0xa9, 0xdc, 0xe2, 0x06, 0xe2, 0xd1, 0xd7, 0xeb, 0x29, 0x95, 0x97, 0x2c, ++ 0x27, 0x07, 0xd1, 0xfe, 0x15, 0xc6, 0x24, 0x40, 0x13, 0xe6, 0x7e, 0xde, ++ 0xaf, 0xf6, 0x15, 0xf3, 0x74, 0xbc, 0x5a, 0xc8, 0xd1, 0xf6, 0xda, 0xdb, ++ 0xf9, 0xfc, 0xb9, 0x65, 0x55, 0xbb, 0x86, 0x96, 0x76, 0xf9, 0x57, 0x88, ++ 0x9f, 0xe2, 0x52, 0xac, 0x7b, 0xf0, 0xa5, 0xe3, 0xe4, 0x57, 0xf4, 0x7f, ++ 0x40, 0xce, 0xd5, 0x05, 0xf2, 0xd3, 0x05, 0x7b, 0xa8, 0xf6, 0x0b, 0x0e, ++ 0x62, 0x9c, 0x9e, 0x52, 0xb9, 0xdc, 0x97, 0x37, 0x6b, 0x56, 0xd3, 0x72, ++ 0x42, 0xd5, 0x3d, 0xdf, 0x09, 0x19, 0xc9, 0x41, 0x2e, 0x2e, 0x62, 0x27, ++ 0x3f, 0x55, 0x31, 0xc1, 0xba, 0xe8, 0xd8, 0x6b, 0xbe, 0x85, 0x98, 0xa1, ++ 0xaa, 0xf3, 0x47, 0xd7, 0xce, 0x3d, 0xde, 0xed, 0xcc, 0x23, 0x21, 0xeb, ++ 0x7e, 0x97, 0x89, 0xa9, 0x13, 0x8e, 0xf2, 0x8d, 0x5b, 0x7d, 0x68, 0xef, ++ 0xda, 0xce, 0x3c, 0x5f, 0xb3, 0xc5, 0xb3, 0x8f, 0xb4, 0xac, 0xb4, 0x78, ++ 0xf6, 0xc1, 0xfb, 0xb4, 0xc4, 0x02, 0x9d, 0x83, 0x62, 0xde, 0xc9, 0x09, ++ 0x98, 0xef, 0xa2, 0xcc, 0x63, 0x2d, 0xe0, 0xee, 0x24, 0x64, 0x86, 0xcf, ++ 0x2a, 0xad, 0x3b, 0xe5, 0xd2, 0xf2, 0x98, 0xac, 0x2f, 0x8f, 0xcb, 0xe5, ++ 0xe5, 0xbb, 0xe5, 0xca, 0x32, 0xeb, 0xef, 0x79, 0x96, 0xd2, 0x6e, 0xcf, ++ 0xf9, 0xe8, 0x5f, 0xb5, 0xe5, 0x44, 0x12, 0x63, 0x56, 0xef, 0x94, 0x8b, ++ 0x9b, 0xf1, 0x7b, 0x1a, 0xf2, 0x4a, 0xfe, 0x74, 0x10, 0xbb, 0xb9, 0xb2, ++ 0x40, 0xda, 0xac, 0x31, 0x3e, 0xea, 0x85, 0x0c, 0xf3, 0xd9, 0x00, 0x62, ++ 0xe4, 0xbb, 0x11, 0x57, 0xb3, 0x16, 0x3e, 0x06, 0x3d, 0xed, 0xc0, 0xe7, ++ 0x83, 0x6f, 0xe6, 0x31, 0x6f, 0x6c, 0x2b, 0x3f, 0x6a, 0xbe, 0xc5, 0xda, ++ 0x8c, 0xbe, 0x8e, 0x6f, 0x6b, 0x5c, 0x15, 0x4f, 0xb3, 0x2e, 0xa9, 0xbc, ++ 0x7c, 0x9b, 0xcc, 0xaa, 0xb9, 0x72, 0x8b, 0x2d, 0xe4, 0x4f, 0xb5, 0x67, ++ 0xbc, 0xbb, 0x81, 0xbd, 0x70, 0xac, 0x83, 0x7b, 0xe8, 0x3e, 0x8c, 0x2b, ++ 0x2f, 0x8b, 0x1c, 0xa9, 0x0e, 0xca, 0xdc, 0x6a, 0x56, 0xc1, 0xcc, 0xfc, ++ 0xd6, 0x7e, 0x25, 0x8b, 0xe0, 0xed, 0xc9, 0xa8, 0xae, 0x4e, 0x8f, 0x2f, ++ 0xaa, 0xba, 0x8e, 0x59, 0xbc, 0x93, 0x79, 0x8d, 0xff, 0xdb, 0xce, 0x1f, ++ 0x66, 0x7f, 0x27, 0xdd, 0xa2, 0xf1, 0xb3, 0x9b, 0xf5, 0x21, 0xac, 0x87, ++ 0x38, 0x51, 0xfb, 0x07, 0x9b, 0x70, 0x9e, 0xa8, 0xe9, 0x33, 0x96, 0x72, ++ 0x8e, 0x7a, 0x74, 0x08, 0xf2, 0xcc, 0xf9, 0x3c, 0xcb, 0xf3, 0xd4, 0xd9, ++ 0xf3, 0x77, 0x77, 0x77, 0x9e, 0xb5, 0xa8, 0xb3, 0x7f, 0x69, 0xb4, 0xd2, ++ 0x4a, 0xbf, 0xb1, 0x3e, 0xaf, 0x52, 0xa5, 0xce, 0x1d, 0x31, 0x39, 0xac, ++ 0x77, 0xcb, 0xa9, 0xf1, 0x1d, 0x8e, 0x84, 0x6a, 0x0d, 0xbe, 0x87, 0x34, ++ 0xeb, 0xac, 0x51, 0xe4, 0xb9, 0x8f, 0x23, 0x97, 0x40, 0xeb, 0x2b, 0x84, ++ 0xa3, 0x46, 0x3f, 0xfd, 0x36, 0xd0, 0x90, 0xf4, 0x03, 0xcf, 0xc0, 0x5f, ++ 0x5f, 0x40, 0xfb, 0x9c, 0x87, 0x31, 0x2d, 0xce, 0xc7, 0xb3, 0x55, 0x4f, ++ 0xbe, 0xd7, 0xea, 0x92, 0x67, 0x1d, 0xd6, 0xe9, 0xc6, 0xe5, 0xaa, 0x73, ++ 0x1b, 0xe8, 0x9e, 0x56, 0x79, 0xfd, 0x02, 0xc6, 0xae, 0xb7, 0x78, 0x3f, ++ 0x06, 0x7e, 0xb0, 0xc4, 0xb9, 0x9b, 0x7e, 0x3d, 0xf5, 0x83, 0x67, 0xbe, ++ 0x7d, 0xe0, 0x33, 0x5d, 0xc7, 0x7d, 0x6d, 0xdc, 0x9e, 0xb4, 0x2b, 0xd1, ++ 0x38, 0xda, 0x90, 0x6e, 0x93, 0xff, 0xc6, 0x18, 0x9e, 0x83, 0x25, 0x5d, ++ 0x9e, 0xad, 0x00, 0xc6, 0x1d, 0x90, 0x3b, 0xe2, 0xae, 0xae, 0xbe, 0xed, ++ 0xd9, 0xa9, 0x6a, 0x5f, 0xc6, 0x40, 0x0f, 0x7e, 0x77, 0x15, 0xe5, 0x29, ++ 0xfb, 0x36, 0x71, 0x2e, 0x83, 0x1c, 0xfb, 0xa5, 0x0e, 0x9c, 0xef, 0x82, ++ 0x1c, 0x0d, 0xc9, 0xaa, 0x3a, 0x4f, 0x60, 0xae, 0xd2, 0x96, 0xb9, 0x24, ++ 0xfa, 0x56, 0x77, 0x49, 0x63, 0x15, 0x46, 0x71, 0x40, 0xc7, 0xb9, 0x4d, ++ 0xac, 0xb7, 0x72, 0x03, 0xdf, 0x90, 0x67, 0x7e, 0xa1, 0xe4, 0xbb, 0xd1, ++ 0xea, 0xa4, 0x6b, 0xc6, 0x4d, 0xdb, 0x11, 0x5d, 0x79, 0x7d, 0xb3, 0xba, ++ 0xcc, 0x88, 0xdf, 0xc7, 0x54, 0x2d, 0x59, 0x2c, 0xf8, 0xeb, 0xd0, 0xce, ++ 0x33, 0x75, 0xff, 0x63, 0x12, 0x5e, 0x57, 0xff, 0xaf, 0xf5, 0xe9, 0x82, ++ 0x4f, 0x5b, 0xc7, 0x33, 0x96, 0x6e, 0x09, 0x5d, 0x1d, 0xe7, 0x54, 0x7c, ++ 0xca, 0x46, 0x21, 0xcd, 0xb3, 0x89, 0x23, 0xf2, 0xfe, 0x7e, 0xf8, 0x10, ++ 0x63, 0x71, 0x89, 0xbe, 0x3d, 0x62, 0x6d, 0x7d, 0xbb, 0xfd, 0x0a, 0xcf, ++ 0x64, 0x81, 0xdb, 0xb3, 0xea, 0x5c, 0x11, 0x32, 0xd7, 0xeb, 0x80, 0xce, ++ 0xd7, 0x6a, 0xfe, 0x1b, 0x18, 0xb3, 0x82, 0x67, 0x27, 0x37, 0x61, 0xa3, ++ 0x7e, 0x86, 0x3f, 0xe7, 0xfd, 0x9f, 0x76, 0x39, 0x79, 0xdd, 0x58, 0xa3, ++ 0xff, 0x98, 0xeb, 0x63, 0xae, 0xd7, 0x85, 0x4c, 0x0c, 0xe0, 0x07, 0x1d, ++ 0xac, 0xe4, 0x9c, 0x32, 0x42, 0x3a, 0xbd, 0x53, 0x7e, 0xb4, 0x4f, 0xee, ++ 0xaf, 0x86, 0x88, 0x0b, 0xc3, 0x76, 0x8f, 0xd7, 0x1f, 0x26, 0x02, 0xc6, ++ 0x95, 0x99, 0x10, 0x4e, 0x46, 0xd8, 0x1b, 0x78, 0xe9, 0x07, 0xb0, 0x87, ++ 0xa3, 0x88, 0x0b, 0x5f, 0xf0, 0x99, 0x37, 0xbd, 0x43, 0x36, 0x5c, 0xf8, ++ 0xd1, 0xfc, 0xee, 0x61, 0x74, 0x5c, 0x4a, 0xe7, 0xbd, 0xb1, 0x07, 0x84, ++ 0xb1, 0x5f, 0x26, 0x7d, 0x90, 0x78, 0xdb, 0xac, 0x05, 0x76, 0x0c, 0x2f, ++ 0x8c, 0xcb, 0xfe, 0xf3, 0x3f, 0x56, 0xf9, 0xea, 0x4f, 0xfb, 0x9d, 0xf5, ++ 0x68, 0xaa, 0x2e, 0x6a, 0x7c, 0xa7, 0xf0, 0x7b, 0x31, 0x81, 0x16, 0x07, ++ 0x8f, 0xe7, 0x58, 0xfb, 0xc4, 0xba, 0x65, 0xd5, 0xca, 0x31, 0x55, 0xf3, ++ 0xe4, 0xc8, 0x8c, 0xaa, 0x3f, 0x4c, 0xc8, 0x17, 0x5b, 0xa4, 0x69, 0x9f, ++ 0xaa, 0x87, 0xfa, 0x36, 0x68, 0x3b, 0xd7, 0xd2, 0x75, 0x90, 0x33, 0x2d, ++ 0xfd, 0x8d, 0xd9, 0x4c, 0x8b, 0xf9, 0x56, 0xe6, 0x5d, 0xdf, 0xa9, 0x5e, ++ 0xea, 0x5a, 0xbd, 0x10, 0xf3, 0x8f, 0xeb, 0xb0, 0x83, 0xc5, 0xba, 0xab, ++ 0xce, 0xd3, 0xca, 0xee, 0x4e, 0x39, 0x32, 0xd6, 0x0d, 0x9c, 0x0f, 0x28, ++ 0xb9, 0xb0, 0xbd, 0x8f, 0x20, 0x66, 0x63, 0xec, 0x44, 0xfb, 0x17, 0xe1, ++ 0x79, 0x2f, 0xfa, 0xde, 0x02, 0xee, 0xd9, 0x87, 0x78, 0x4e, 0xf9, 0x70, ++ 0x8f, 0x43, 0x3e, 0x58, 0x53, 0xdc, 0xd8, 0x51, 0x50, 0xf4, 0x60, 0x3e, ++ 0x24, 0xd2, 0x3d, 0x51, 0x7d, 0x18, 0xe3, 0x51, 0xd7, 0x9c, 0x03, 0x33, ++ 0x1f, 0x32, 0x20, 0xe5, 0x55, 0xea, 0x17, 0x2d, 0x83, 0x1b, 0xb1, 0xdb, ++ 0x24, 0x6c, 0xdc, 0xec, 0x4c, 0xbb, 0xdd, 0xfe, 0x96, 0xaf, 0xe2, 0xc4, ++ 0x53, 0xa1, 0xa1, 0xf1, 0x74, 0x8e, 0xf1, 0xa8, 0x63, 0x70, 0xdc, 0x67, ++ 0xce, 0xf1, 0xe1, 0xcb, 0x0f, 0xf4, 0x62, 0xad, 0xbd, 0x26, 0xcf, 0xc5, ++ 0x98, 0xf2, 0x57, 0xc6, 0x2f, 0x64, 0x3c, 0x39, 0xa0, 0x7c, 0x7c, 0xbb, ++ 0x19, 0xf1, 0x09, 0xeb, 0x59, 0x18, 0x6b, 0xee, 0x96, 0x7c, 0x23, 0x26, ++ 0xf9, 0x41, 0xde, 0xff, 0x33, 0x33, 0x97, 0xd7, 0x6d, 0x39, 0x30, 0xb1, ++ 0xf5, 0xac, 0x7a, 0x52, 0xc7, 0xb0, 0xbd, 0xd1, 0x79, 0xf5, 0xd6, 0x9a, ++ 0x62, 0x05, 0x27, 0x78, 0x26, 0x82, 0x41, 0xbf, 0x6b, 0x3f, 0xe0, 0x6d, ++ 0xc2, 0x7e, 0x0f, 0x78, 0xac, 0x83, 0x89, 0xc9, 0xc4, 0x40, 0x06, 0x4e, ++ 0x87, 0x86, 0xa7, 0xd9, 0x80, 0xef, 0x51, 0x8f, 0xe0, 0xd4, 0xb1, 0x6f, ++ 0xb3, 0x91, 0x51, 0x75, 0x60, 0x71, 0xd8, 0xf7, 0x89, 0x41, 0xe2, 0x79, ++ 0x2b, 0x1c, 0xbf, 0x17, 0xbb, 0xf9, 0xb7, 0x62, 0x1f, 0xee, 0x80, 0xef, ++ 0x4d, 0x13, 0xcf, 0x12, 0xae, 0xa4, 0x39, 0x53, 0x87, 0x4f, 0xb1, 0xcc, ++ 0x38, 0x9c, 0x30, 0x0e, 0x40, 0x9f, 0x61, 0x8f, 0x0a, 0xb7, 0x9d, 0xf2, ++ 0x13, 0xc5, 0xef, 0x71, 0xc5, 0x17, 0xb3, 0x39, 0xee, 0x25, 0x6e, 0xe2, ++ 0x79, 0xc2, 0x95, 0x31, 0x35, 0x7f, 0x84, 0x6f, 0x70, 0x87, 0xa6, 0xff, ++ 0xc7, 0xcc, 0x7e, 0xa3, 0x3a, 0x41, 0xae, 0xf5, 0x01, 0xcc, 0xff, 0x83, ++ 0x36, 0xde, 0x45, 0x07, 0x0b, 0xf2, 0x1f, 0x7d, 0x07, 0xf3, 0x01, 0xbd, ++ 0x96, 0xf2, 0x31, 0xb6, 0x7e, 0x1b, 0x4b, 0xf9, 0x8a, 0x70, 0xc8, 0x35, ++ 0x06, 0x4c, 0xde, 0x9e, 0x30, 0xf4, 0x6c, 0x81, 0x21, 0xe3, 0x5f, 0xaf, ++ 0xe3, 0xf6, 0x76, 0xec, 0x9d, 0xbc, 0xd6, 0x2f, 0xf3, 0xf5, 0x5e, 0xa9, ++ 0xd4, 0xb7, 0x31, 0x5f, 0x31, 0x26, 0x42, 0x1f, 0x68, 0xda, 0xd4, 0x8a, ++ 0x8b, 0xe8, 0x3a, 0xee, 0x48, 0x3e, 0xfb, 0x31, 0x8e, 0xba, 0x18, 0x6d, ++ 0x43, 0xeb, 0xa7, 0x86, 0xdc, 0x58, 0x33, 0x38, 0xb7, 0x59, 0x33, 0xa8, ++ 0x6b, 0x7e, 0xca, 0x9b, 0x35, 0x18, 0xac, 0x3b, 0xeb, 0xac, 0xef, 0x09, ++ 0xe5, 0xd0, 0xbe, 0x1e, 0x19, 0x5e, 0xea, 0x35, 0x3c, 0xfa, 0x11, 0xf3, ++ 0x1e, 0xbc, 0x6f, 0x71, 0x52, 0x86, 0x17, 0xbf, 0x0c, 0xff, 0x52, 0xd5, ++ 0x19, 0x63, 0x4c, 0xa4, 0x2b, 0x46, 0x38, 0xc6, 0xe4, 0x31, 0x38, 0x0e, ++ 0xf4, 0xda, 0x97, 0x19, 0x4b, 0xdb, 0x43, 0xd0, 0x65, 0x0f, 0xcb, 0xf0, ++ 0x99, 0x49, 0x61, 0x6d, 0x75, 0xc1, 0xe7, 0x49, 0x37, 0x7d, 0xae, 0x21, ++ 0xc9, 0x5e, 0xd0, 0xeb, 0x79, 0x8b, 0x7c, 0x9e, 0x85, 0x5f, 0xc7, 0xe7, ++ 0xc5, 0x94, 0xfe, 0xda, 0xec, 0x4e, 0xf0, 0x53, 0x97, 0xc9, 0xf1, 0x38, ++ 0x52, 0x58, 0xe4, 0x7c, 0xe6, 0xfb, 0x16, 0x40, 0xb3, 0x62, 0xda, 0x16, ++ 0xce, 0x51, 0xeb, 0xe1, 0x3a, 0x3a, 0x93, 0x21, 0xae, 0xc7, 0x65, 0x15, ++ 0xb6, 0x3f, 0xdf, 0xd0, 0xb5, 0xe9, 0xe5, 0x46, 0x54, 0x4b, 0xf9, 0xb7, ++ 0x37, 0xbf, 0x7f, 0x23, 0x8c, 0xa5, 0xea, 0x56, 0xde, 0x7b, 0xc0, 0xd4, ++ 0xa8, 0xf7, 0xa8, 0xb3, 0xce, 0x0e, 0xfd, 0x67, 0xc6, 0x5f, 0xde, 0xc1, ++ 0x73, 0x70, 0x11, 0x3e, 0x1f, 0x34, 0xcf, 0xe1, 0xc3, 0x24, 0x93, 0x4a, ++ 0x0e, 0x86, 0x9b, 0xd1, 0xb8, 0xff, 0xb8, 0x43, 0xd7, 0x99, 0x13, 0x4f, ++ 0x81, 0x81, 0xd9, 0x47, 0x4c, 0xc9, 0xbe, 0xdd, 0x98, 0x4b, 0x3a, 0xa1, ++ 0x6d, 0xf2, 0x1a, 0xfb, 0x1a, 0x1f, 0xa4, 0x8d, 0x0e, 0xdd, 0xa0, 0x47, ++ 0xdd, 0xeb, 0x75, 0x7b, 0x3a, 0xde, 0xbb, 0x15, 0x4e, 0xe6, 0xb5, 0xce, ++ 0x19, 0x3e, 0xe1, 0x73, 0xde, 0x6f, 0x1d, 0x33, 0xbc, 0x23, 0x7a, 0xee, ++ 0x2c, 0x46, 0xf2, 0x41, 0x1c, 0xf2, 0x7c, 0x16, 0xed, 0x85, 0x00, 0xb0, ++ 0xf1, 0x1a, 0xad, 0xa9, 0xdd, 0x77, 0x16, 0xf9, 0xdb, 0xba, 0x8e, 0x83, ++ 0xb5, 0x23, 0x59, 0xbd, 0x59, 0xcd, 0x0b, 0x75, 0xf0, 0x29, 0x6b, 0xbd, ++ 0xca, 0x5a, 0x83, 0x50, 0x8e, 0xe4, 0xfa, 0x65, 0xb6, 0x6e, 0x23, 0x46, ++ 0x55, 0x79, 0x6f, 0x9e, 0x25, 0xc3, 0x2f, 0x20, 0x6d, 0x46, 0x4d, 0xdc, ++ 0xdb, 0x83, 0xf8, 0x98, 0x7c, 0x3c, 0x2a, 0xab, 0x0d, 0xf2, 0x4d, 0xc4, ++ 0xc7, 0x5d, 0x86, 0xbf, 0x5e, 0x8c, 0x4b, 0x6f, 0x88, 0xf8, 0x28, 0x92, ++ 0xe5, 0x51, 0x29, 0x35, 0x3a, 0xcf, 0xa8, 0x58, 0x3f, 0xd3, 0xf9, 0xdd, ++ 0xa8, 0xaa, 0x45, 0xab, 0x87, 0xe0, 0x93, 0x8d, 0x24, 0x73, 0x03, 0x1c, ++ 0xb7, 0xdd, 0xd8, 0xd9, 0x7d, 0xae, 0xf4, 0x42, 0x71, 0x7b, 0x84, 0x0d, ++ 0xb6, 0x41, 0xbd, 0x27, 0x2b, 0x07, 0x92, 0x21, 0xe2, 0xc5, 0x51, 0xf3, ++ 0xde, 0xdb, 0x71, 0xcf, 0xb1, 0x3b, 0xcc, 0xf3, 0x0f, 0x98, 0xfb, 0x5e, ++ 0x73, 0x1f, 0xc3, 0x7d, 0xab, 0x5d, 0xaf, 0x71, 0x4d, 0xb6, 0xfc, 0x5e, ++ 0x83, 0x67, 0x48, 0x81, 0xc4, 0x2f, 0x88, 0xec, 0x6f, 0xf5, 0xca, 0x23, ++ 0x0d, 0x85, 0x5f, 0xcb, 0x5b, 0xa4, 0x23, 0xf0, 0xb8, 0xb9, 0xbe, 0x51, ++ 0xf6, 0xbe, 0x70, 0x5d, 0xbd, 0xee, 0xbd, 0xae, 0xe6, 0x91, 0x4e, 0x78, ++ 0xef, 0x05, 0xac, 0xef, 0x54, 0x5b, 0x44, 0xdb, 0xa4, 0xe3, 0xd6, 0x52, ++ 0x55, 0xd7, 0xd0, 0x1c, 0xa9, 0x02, 0xd6, 0xfa, 0xdb, 0x3b, 0x74, 0x7d, ++ 0x47, 0x54, 0x23, 0x88, 0xb8, 0xbc, 0x3e, 0x6a, 0xea, 0x0a, 0x38, 0x97, ++ 0xb5, 0x8a, 0xd1, 0xd9, 0x5e, 0xa7, 0x9f, 0x4a, 0x1b, 0x44, 0xfb, 0xe2, ++ 0x83, 0x06, 0x3e, 0xc6, 0x9e, 0xa0, 0x8e, 0x81, 0x7d, 0x8a, 0x6a, 0xa0, ++ 0x2b, 0x37, 0x7c, 0xbb, 0x7e, 0x12, 0xb0, 0xfe, 0xb0, 0xc5, 0x5c, 0x6b, ++ 0x8f, 0xc4, 0x96, 0xa2, 0xda, 0x22, 0xd2, 0x98, 0xfe, 0x97, 0x03, 0x1f, ++ 0xf4, 0x93, 0x5b, 0xf2, 0xb0, 0x6a, 0x53, 0xfc, 0x1e, 0x4f, 0x66, 0xab, ++ 0xff, 0xd0, 0x65, 0xdd, 0xa6, 0x1b, 0x44, 0xb9, 0x5b, 0x7e, 0x53, 0x44, ++ 0x5f, 0x6b, 0xb7, 0xe8, 0x6f, 0xad, 0xf8, 0x2c, 0x94, 0x9d, 0xfb, 0x3e, ++ 0xc9, 0xda, 0xd6, 0x5d, 0x31, 0x05, 0xbf, 0xfa, 0xe6, 0x16, 0x7a, 0x22, ++ 0x01, 0x7f, 0xd9, 0x87, 0x8e, 0xd0, 0xb0, 0x5d, 0x6e, 0xe5, 0x64, 0x64, ++ 0x91, 0xf5, 0xef, 0xdb, 0x2e, 0xd2, 0x36, 0x5c, 0x69, 0x71, 0x0c, 0x65, ++ 0x0d, 0x3a, 0x15, 0x3a, 0x7a, 0xbd, 0x15, 0xa8, 0x9a, 0x8d, 0x75, 0xf3, ++ 0x1d, 0xed, 0xa5, 0x96, 0x23, 0xb6, 0xaa, 0x29, 0x67, 0xed, 0x24, 0x7d, ++ 0xb4, 0x34, 0x9e, 0xb3, 0x36, 0x6c, 0x48, 0xd5, 0x7a, 0x54, 0x5a, 0x9f, ++ 0x41, 0xfb, 0x38, 0x62, 0x42, 0x9d, 0xf3, 0xae, 0xb4, 0x58, 0xf3, 0xe1, ++ 0xaa, 0xf3, 0xc5, 0xe1, 0xc5, 0x12, 0xe4, 0x37, 0xfa, 0xf6, 0x37, 0x89, ++ 0x3e, 0xc2, 0x17, 0x6e, 0xf1, 0x8d, 0x58, 0x6b, 0xfe, 0xc7, 0x2e, 0x65, ++ 0x84, 0xf0, 0xb1, 0x56, 0x44, 0xfb, 0x22, 0xf4, 0xf3, 0x12, 0x18, 0xcf, ++ 0xfd, 0xf6, 0xd2, 0x56, 0xb5, 0xa9, 0x8f, 0xb2, 0x78, 0x57, 0x53, 0xd5, ++ 0xdd, 0x31, 0x1f, 0xe0, 0xb9, 0x65, 0xc6, 0x5f, 0x4a, 0xbf, 0xf3, 0x3b, ++ 0xcd, 0xa2, 0x1b, 0x67, 0xde, 0xb7, 0xc5, 0xb5, 0xb8, 0x1f, 0xee, 0xb3, ++ 0xef, 0x22, 0x6b, 0xdd, 0xcb, 0xea, 0x7c, 0x5b, 0xef, 0xa9, 0xd8, 0x4a, ++ 0xa8, 0xef, 0x11, 0xca, 0xea, 0xbb, 0x3f, 0x7e, 0x8f, 0x10, 0xc2, 0xce, ++ 0xa9, 0x6f, 0x9d, 0xd4, 0xf7, 0x08, 0x8d, 0xd6, 0x41, 0xf3, 0x4d, 0x02, ++ 0xf9, 0x28, 0x01, 0x7d, 0xd8, 0x87, 0x3e, 0x17, 0xbf, 0x38, 0xe4, 0x93, ++ 0xf5, 0xf3, 0xdb, 0xe1, 0x9f, 0x11, 0xcf, 0xea, 0x3b, 0x64, 0x7e, 0xaf, ++ 0x0c, 0x5e, 0xe3, 0x77, 0x08, 0xf4, 0xc1, 0xf8, 0xed, 0x31, 0xfd, 0x2f, ++ 0x2d, 0xf3, 0x37, 0xfa, 0xe0, 0xe4, 0xc3, 0x2f, 0x03, 0xae, 0xa8, 0xc6, ++ 0x90, 0xb5, 0x90, 0xed, 0xf6, 0x11, 0x9f, 0x67, 0x9f, 0xd3, 0x07, 0x56, ++ 0xb0, 0xc7, 0xcb, 0x0d, 0xe0, 0xf1, 0x30, 0xfb, 0x58, 0x13, 0xd5, 0x0d, ++ 0x1d, 0xa7, 0xf2, 0x6e, 0xbd, 0x2b, 0xde, 0x76, 0xb9, 0x54, 0x4f, 0xaa, ++ 0xfa, 0xae, 0x32, 0x7c, 0xfc, 0xa6, 0xfc, 0x95, 0xcb, 0x1c, 0xf6, 0x7e, ++ 0x35, 0x3f, 0x92, 0x79, 0xbe, 0x27, 0x29, 0xfb, 0x57, 0xb5, 0x4e, 0x39, ++ 0x9a, 0x83, 0xcf, 0x72, 0x5e, 0xac, 0xcf, 0xe6, 0x86, 0xe4, 0x6a, 0x95, ++ 0xef, 0xca, 0x62, 0x1e, 0xf8, 0x27, 0x45, 0x79, 0x7f, 0xab, 0xdd, 0x04, ++ 0xbc, 0x57, 0x5b, 0xf4, 0xd5, 0xe1, 0x3f, 0x4d, 0x73, 0x4e, 0x20, 0xf6, ++ 0x69, 0x8e, 0x19, 0x00, 0x0f, 0xc6, 0xb1, 0x1f, 0x07, 0x71, 0x00, 0x73, ++ 0xa6, 0x7c, 0xc6, 0xeb, 0x94, 0xc9, 0xa1, 0x10, 0xff, 0x3f, 0x02, 0xfe, ++ 0xd2, 0x4a, 0x2f, 0x45, 0xe7, 0xe5, 0xac, 0xd5, 0x9c, 0xad, 0x3f, 0x08, ++ 0x39, 0x72, 0x8c, 0x5f, 0xe6, 0x60, 0x8d, 0xff, 0xe6, 0x6a, 0x3f, 0x81, ++ 0xe7, 0xe9, 0xda, 0x0f, 0xd1, 0xf6, 0x85, 0xe7, 0x69, 0x0e, 0xe2, 0x80, ++ 0x48, 0x36, 0x1f, 0x30, 0xfe, 0x44, 0x67, 0xce, 0x28, 0x9b, 0x3a, 0xc7, ++ 0x1c, 0xcb, 0xda, 0xa7, 0x64, 0x06, 0x30, 0x9f, 0x32, 0xfb, 0xbc, 0x1f, ++ 0xf1, 0xc8, 0x46, 0x83, 0xe7, 0xdd, 0xbb, 0xd1, 0xb2, 0x8e, 0x8f, 0x30, ++ 0xef, 0x31, 0xb5, 0x8a, 0x01, 0xf6, 0xfa, 0xb0, 0xbc, 0xbe, 0x3c, 0x2e, ++ 0x6f, 0x54, 0xb3, 0xfe, 0x7e, 0x95, 0xff, 0xcd, 0xa4, 0x2e, 0xc9, 0x9e, ++ 0xf4, 0x3c, 0x64, 0x2d, 0x74, 0x33, 0xa9, 0x0d, 0xf8, 0xe4, 0x57, 0xab, ++ 0x07, 0x77, 0xf2, 0x7f, 0x55, 0x34, 0x61, 0x0b, 0xaf, 0xaa, 0x5a, 0x92, ++ 0x0c, 0xf3, 0x19, 0xb8, 0x1f, 0x32, 0xf5, 0x2c, 0x7c, 0x0f, 0x9f, 0x0d, ++ 0xa9, 0xbc, 0x90, 0xb1, 0xbd, 0x7c, 0x0f, 0xf8, 0x39, 0x66, 0x6c, 0xeb, ++ 0xdf, 0xd9, 0x49, 0x5d, 0xc4, 0xf7, 0xe9, 0x35, 0xa2, 0x31, 0xc4, 0x6b, ++ 0x94, 0x13, 0x74, 0xf5, 0xb7, 0x05, 0x16, 0xeb, 0x47, 0xb8, 0xf7, 0x5f, ++ 0xba, 0xda, 0xff, 0xe1, 0xbc, 0xac, 0x7b, 0x40, 0xad, 0xc7, 0x73, 0xd4, ++ 0x21, 0xf9, 0xf3, 0x56, 0xb4, 0x0e, 0xeb, 0x5a, 0x18, 0x7f, 0x52, 0xff, ++ 0x75, 0xc2, 0xa0, 0x6d, 0xff, 0xeb, 0x2a, 0xcf, 0x36, 0x89, 0xf1, 0xb4, ++ 0xcf, 0xe0, 0x97, 0x46, 0x4a, 0x7d, 0x43, 0xfd, 0xf2, 0xa6, 0x9e, 0xe3, ++ 0x35, 0xf1, 0xa9, 0x73, 0x39, 0xf6, 0x3d, 0xae, 0x79, 0x1e, 0xf9, 0xa4, ++ 0x43, 0x90, 0xd9, 0x87, 0x11, 0x63, 0x66, 0x53, 0x8f, 0x48, 0xb4, 0x6e, ++ 0xfb, 0x3e, 0x9e, 0x37, 0x95, 0x72, 0x7b, 0xdc, 0x79, 0x05, 0x0f, 0xcf, ++ 0x44, 0x33, 0xee, 0x25, 0xf5, 0x7f, 0x2c, 0xb6, 0xe6, 0x15, 0x32, 0xf9, ++ 0x8b, 0x92, 0xf5, 0x35, 0x6d, 0x46, 0xe5, 0x22, 0x68, 0xf3, 0x4f, 0x0c, ++ 0x6d, 0x1e, 0xc0, 0xda, 0xde, 0xe9, 0x71, 0xc9, 0x9e, 0xce, 0xa6, 0x4f, ++ 0x09, 0xcf, 0x6e, 0x77, 0xf0, 0xec, 0xd6, 0xba, 0x3f, 0x97, 0xc6, 0x7e, ++ 0x59, 0x0b, 0x88, 0xb6, 0xc5, 0x6b, 0xfe, 0x1f, 0x82, 0x6d, 0x94, 0xed, ++ 0xfb, 0x98, 0xaf, 0x24, 0x2e, 0x4a, 0xea, 0x19, 0x7c, 0x93, 0x67, 0x08, ++ 0xd3, 0x05, 0xd2, 0x47, 0xe5, 0x26, 0x37, 0x5a, 0xfc, 0x1e, 0x55, 0xc3, ++ 0x57, 0x04, 0x7c, 0x73, 0x1a, 0xbe, 0xf4, 0xcc, 0xa6, 0xdf, 0x9a, 0x49, ++ 0x9d, 0x10, 0xca, 0x36, 0x7d, 0x17, 0xfa, 0xf4, 0x6f, 0xef, 0xd4, 0x79, ++ 0x37, 0xc4, 0xb0, 0xf7, 0xe4, 0x37, 0xf7, 0xde, 0x85, 0xb1, 0x97, 0x73, ++ 0xaa, 0x76, 0xd7, 0x3d, 0x28, 0x1f, 0x95, 0xfc, 0x67, 0x32, 0xe9, 0xbc, ++ 0xe5, 0x19, 0xff, 0x0f, 0x6d, 0x83, 0xd7, 0xd4, 0xbb, 0x9e, 0xa9, 0xdd, ++ 0x21, 0x6d, 0x72, 0x78, 0x97, 0xc2, 0x2d, 0xe2, 0xa5, 0x21, 0xf0, 0x3c, ++ 0x79, 0xed, 0x43, 0x90, 0x21, 0x57, 0xc5, 0x66, 0x97, 0x80, 0xc7, 0x0a, ++ 0xf0, 0x78, 0xf4, 0x06, 0xff, 0x2b, 0xbe, 0xe9, 0x7f, 0xad, 0xab, 0xf7, ++ 0xbd, 0x0e, 0x98, 0x8a, 0x2e, 0x7d, 0xaf, 0xca, 0x26, 0xaf, 0x10, 0xa6, ++ 0x71, 0xe8, 0xac, 0x50, 0xae, 0xe4, 0x48, 0x0f, 0xf8, 0x5f, 0x58, 0x6f, ++ 0xe5, 0x1a, 0x2f, 0x61, 0xff, 0x8a, 0x7f, 0xc1, 0xbb, 0x19, 0xd7, 0xb1, ++ 0x86, 0x94, 0x8e, 0x5a, 0x87, 0x1d, 0x7b, 0x05, 0xb0, 0xac, 0x6b, 0x3e, ++ 0x50, 0x3c, 0xb0, 0xde, 0xe8, 0x7d, 0x17, 0x1e, 0xe0, 0x3e, 0xc9, 0x7f, ++ 0x11, 0xef, 0x45, 0xb4, 0x4c, 0x84, 0x3d, 0xc0, 0xc9, 0x9d, 0x7b, 0x03, ++ 0x29, 0x9c, 0x6e, 0xcb, 0xbc, 0x2f, 0xd6, 0x9e, 0xbd, 0xe4, 0x49, 0xfa, ++ 0x0a, 0xf0, 0x1f, 0x53, 0xc4, 0xb1, 0xf6, 0x05, 0x67, 0xa0, 0xd6, 0x66, ++ 0x9e, 0xad, 0xef, 0xe4, 0x19, 0x4f, 0xe1, 0x2c, 0xf5, 0x95, 0x58, 0x77, ++ 0xec, 0xd5, 0xb1, 0xe1, 0xd5, 0x24, 0x70, 0x8e, 0xe7, 0xc3, 0x4f, 0x75, ++ 0x99, 0x1c, 0xa7, 0xb6, 0xcd, 0xc3, 0x4f, 0x11, 0xaf, 0x68, 0x9f, 0xfd, ++ 0xa5, 0xd1, 0x01, 0x4a, 0xf7, 0x1a, 0xb9, 0x08, 0x65, 0x2e, 0xc7, 0xda, ++ 0xca, 0x5e, 0xd9, 0x0f, 0xbd, 0x76, 0xb0, 0x3a, 0x29, 0x5f, 0xad, 0xf6, ++ 0x29, 0xdf, 0xe1, 0x5f, 0xf8, 0xd9, 0xd4, 0x98, 0xd5, 0x96, 0xfb, 0xe1, ++ 0x03, 0xcd, 0x0c, 0x75, 0xc9, 0x1b, 0xe3, 0xba, 0xae, 0xf5, 0x2a, 0x8b, ++ 0xd4, 0x5c, 0xd6, 0x5e, 0x72, 0x3f, 0xd0, 0xfb, 0x16, 0xe2, 0x00, 0x8b, ++ 0x39, 0xde, 0x3e, 0x99, 0xf2, 0xd1, 0xde, 0xe2, 0xab, 0x6f, 0x70, 0xa3, ++ 0xbc, 0x8d, 0xd6, 0x23, 0x84, 0x99, 0xed, 0x9d, 0xa6, 0x8d, 0x0d, 0x74, ++ 0xc0, 0x62, 0xcd, 0xe5, 0x62, 0x6a, 0x7f, 0x95, 0x06, 0xf5, 0x9b, 0xc9, ++ 0x4f, 0xb5, 0x58, 0xc7, 0x11, 0xca, 0x0a, 0xf4, 0x4b, 0xb9, 0x2e, 0xd6, ++ 0xd9, 0x1c, 0xbc, 0x69, 0x4f, 0xfb, 0x9e, 0x65, 0xf0, 0xd7, 0x6c, 0x9d, ++ 0xfa, 0xef, 0xa0, 0xaa, 0x49, 0x9e, 0x85, 0x2d, 0x43, 0x3c, 0x3c, 0xd3, ++ 0x1d, 0xdc, 0xec, 0x5c, 0xf1, 0xda, 0xb7, 0xb0, 0x76, 0xf0, 0xc0, 0x00, ++ 0xbf, 0x2d, 0x2e, 0x55, 0x23, 0x7f, 0x1b, 0x38, 0x6d, 0xf0, 0xff, 0x47, ++ 0x44, 0xb9, 0x42, 0xfd, 0x6e, 0x1d, 0x57, 0x44, 0xb5, 0xd0, 0x91, 0xdf, ++ 0x41, 0x99, 0xa5, 0xbd, 0x90, 0x30, 0x01, 0xbf, 0xb6, 0xe7, 0x74, 0x1f, ++ 0x6c, 0x41, 0x00, 0x5e, 0x99, 0x84, 0x3d, 0x9c, 0x94, 0x0a, 0xfc, 0xb7, ++ 0xcf, 0xfa, 0x5f, 0x16, 0xfb, 0x99, 0xdd, 0xb2, 0x52, 0xef, 0x01, 0x3e, ++ 0x68, 0x17, 0xe2, 0x2a, 0xb6, 0xbe, 0x7a, 0x98, 0xf1, 0x10, 0x6d, 0x89, ++ 0xa6, 0xc5, 0x7a, 0x63, 0x61, 0x40, 0x7f, 0x17, 0xb2, 0x5d, 0x2e, 0x36, ++ 0x74, 0xad, 0x5b, 0x85, 0xb1, 0x61, 0x3d, 0x6e, 0x6c, 0x73, 0x2f, 0x74, ++ 0xf7, 0x7f, 0x89, 0x37, 0x55, 0x9c, 0xce, 0xfd, 0xd3, 0x06, 0xa9, 0xff, ++ 0x17, 0xd2, 0xdb, 0xf4, 0xb8, 0xf7, 0x4e, 0x1b, 0xa4, 0x7d, 0x0f, 0x77, ++ 0x1f, 0xdf, 0xc7, 0x73, 0x31, 0xee, 0x31, 0x29, 0xf1, 0x73, 0x0f, 0x8b, ++ 0x8d, 0x98, 0x25, 0xb6, 0x48, 0x7f, 0xef, 0xfa, 0xb8, 0x25, 0x76, 0xe1, ++ 0x51, 0xf3, 0x4d, 0xe8, 0x88, 0xf6, 0x67, 0x72, 0x68, 0x9b, 0xd1, 0x77, ++ 0xa2, 0xfc, 0x75, 0xda, 0xcd, 0x28, 0xae, 0xb8, 0xa9, 0x2d, 0xc5, 0xdf, ++ 0xff, 0x03, 0x4c, 0x1c, 0xdd, 0xc0, 0xcc, 0x4a, 0x00, 0x00, 0x00 }; + + static const u32 bnx2_COM_b09FwData[(0x0/4) + 1] = { 0x0 }; +-static const u32 bnx2_COM_b09FwRodata[(0x30/4) + 1] = { +- 0x80080100, 0x80080080, 0x80080000, 0x80080240, 0x08000e20, 0x08000e78, +- 0x08000ebc, 0x08000f50, 0x08000f94, 0x80080100, 0x80080080, 0x80080000, +- 0x00000000 }; ++static const u32 bnx2_COM_b09FwRodata[(0x38/4) + 1] = { ++ 0x80080100, 0x80080080, 0x80080000, 0x00000c80, 0x00003200, 0x80080240, ++ 0x08000f6c, 0x08000fc4, 0x08001008, 0x080010a0, 0x080010e0, 0x80080100, ++ 0x80080080, 0x80080000, 0x00000000 }; + + static struct fw_info bnx2_com_fw_09 = { +- /* Firmware version: 4.4.23 */ +- .ver_major = 0x4, +- .ver_minor = 0x4, +- .ver_fix = 0x17, +- +- .start_addr = 0x080000f8, ++ /* Firmware version: 5.0.0j */ ++ .ver_major = 0x5, ++ .ver_minor = 0x0, ++ .ver_fix = 0x0, ++ ++ .start_addr = 0x08000110, + + .text_addr = 0x08000000, +- .text_len = 0x4c18, ++ .text_len = 0x4ac8, + .text_index = 0x0, + .gz_text = bnx2_COM_b09FwText, + .gz_text_len = sizeof(bnx2_COM_b09FwText), +@@ -866,1210 +873,1217 @@ + .data_index = 0x0, + .data = bnx2_COM_b09FwData, + +- .sbss_addr = 0x08004c60, +- .sbss_len = 0x38, +- .sbss_index = 0x0, +- +- .bss_addr = 0x08004c98, +- .bss_len = 0xbc, +- .bss_index = 0x0, +- +- .rodata_addr = 0x08004c18, +- .rodata_len = 0x30, ++ .sbss_addr = 0x08004b20, ++ .sbss_len = 0x2c, ++ .sbss_index = 0x0, ++ ++ .bss_addr = 0x08004b50, ++ .bss_len = 0x10c, ++ .bss_index = 0x0, ++ ++ .rodata_addr = 0x08004ac8, ++ .rodata_len = 0x38, + .rodata_index = 0x0, + .rodata = bnx2_COM_b09FwRodata, + }; + + static u8 bnx2_CP_b09FwText[] = { +- 0xad, 0xbc, 0x0b, 0x74, 0x1c, 0xd5, 0x95, 0x2e, 0xfc, 0x55, 0x75, 0xb7, +- 0xd4, 0x92, 0xda, 0x52, 0x4b, 0x6e, 0xcb, 0x6d, 0xd0, 0xe0, 0x6a, 0xab, +- 0xda, 0x6a, 0x2c, 0x01, 0xd5, 0xb2, 0x0c, 0x4d, 0xa6, 0xc0, 0x1d, 0x5b, +- 0x80, 0x0c, 0x26, 0x11, 0xc6, 0xb9, 0x23, 0xe6, 0x7a, 0xfe, 0xf4, 0x18, +- 0x03, 0x86, 0x90, 0x5c, 0x33, 0x93, 0x9b, 0x71, 0xb8, 0x9e, 0xeb, 0x8a, +- 0xe4, 0x87, 0xc0, 0xa5, 0xee, 0x96, 0x90, 0x1f, 0xac, 0x35, 0xeb, 0xa7, +- 0x2d, 0xcb, 0x92, 0x21, 0xad, 0x16, 0x49, 0x98, 0x19, 0xe7, 0xe6, 0x81, +- 0xc6, 0xd8, 0x60, 0x93, 0xf0, 0xc8, 0x6b, 0xfd, 0x4c, 0xfe, 0xb9, 0x7f, +- 0x3c, 0xb6, 0x79, 0x83, 0xe3, 0x3c, 0x47, 0x9e, 0xc1, 0xa9, 0xff, 0xdb, +- 0xd5, 0xdd, 0xb6, 0xec, 0x40, 0x1e, 0xeb, 0x8e, 0xd6, 0xaa, 0xa5, 0xee, +- 0xaa, 0x73, 0xf6, 0x39, 0x67, 0x9f, 0xbd, 0xbf, 0xfd, 0xed, 0x73, 0x4e, +- 0xb5, 0x06, 0x54, 0xa3, 0xf4, 0x37, 0x8b, 0xd7, 0xd5, 0x1d, 0x1b, 0xee, +- 0x5e, 0xdc, 0x7e, 0x75, 0x87, 0x7c, 0xf7, 0xce, 0xf5, 0x7a, 0xf1, 0x61, +- 0x7f, 0x26, 0x12, 0x97, 0xde, 0xd2, 0x3e, 0xb4, 0xe0, 0x47, 0xfc, 0x25, +- 0x10, 0x91, 0x7f, 0xad, 0xa5, 0xaf, 0x1e, 0x20, 0x58, 0x6e, 0x5f, 0x2e, +- 0xf8, 0x55, 0xb3, 0xf3, 0xbf, 0x2e, 0xd3, 0xe1, 0xf7, 0x98, 0x9f, 0xff, +- 0x8b, 0xbb, 0x75, 0x20, 0x99, 0x6f, 0xd5, 0x96, 0xe3, 0x9c, 0x63, 0x85, +- 0xbc, 0x90, 0xfb, 0x7f, 0x62, 0x7e, 0xf0, 0xc4, 0xb7, 0xae, 0x8b, 0x9c, +- 0xc9, 0x79, 0xe0, 0x0f, 0x9a, 0x16, 0x82, 0x0b, 0xe1, 0x6f, 0x62, 0x9d, +- 0xbf, 0x6b, 0xd9, 0xa6, 0xa2, 0xb6, 0x2c, 0x2b, 0x12, 0xce, 0x21, 0x12, +- 0xb4, 0x10, 0x89, 0x59, 0x40, 0xca, 0x6b, 0x22, 0x55, 0x69, 0xfa, 0x51, +- 0xa1, 0x57, 0x20, 0x15, 0xdc, 0xa8, 0x6d, 0xe1, 0x18, 0x97, 0xd9, 0x7e, +- 0xed, 0x44, 0x1e, 0xb8, 0xdb, 0xf6, 0xe3, 0xb8, 0x27, 0xa0, 0x9d, 0xcc, +- 0xef, 0xab, 0x2b, 0xea, 0x23, 0x09, 0x8f, 0x8e, 0x94, 0x6a, 0xca, 0x7d, +- 0x68, 0xcb, 0xf3, 0x48, 0xf9, 0xcc, 0xcf, 0x6b, 0xe3, 0x36, 0xd0, 0x9b, +- 0x69, 0x36, 0x4e, 0xa0, 0x35, 0x7c, 0x18, 0x95, 0x48, 0x85, 0x22, 0x31, +- 0xe0, 0x83, 0x73, 0x8f, 0x66, 0x14, 0xf8, 0xf4, 0xd9, 0xe8, 0xdc, 0x0b, +- 0x3c, 0x92, 0x89, 0x24, 0x75, 0x05, 0xe8, 0x9f, 0x94, 0xba, 0x91, 0x60, +- 0x8e, 0xcf, 0xb7, 0x64, 0x80, 0xad, 0x99, 0xd9, 0xd8, 0x96, 0x75, 0xf0, +- 0x9c, 0xd1, 0x1c, 0xdc, 0xc7, 0x16, 0x7a, 0xdd, 0xe7, 0xb3, 0x61, 0xe5, +- 0xe4, 0xf9, 0x5b, 0xce, 0xb7, 0x5a, 0x82, 0x78, 0x7a, 0x32, 0x84, 0x67, +- 0x27, 0xeb, 0xf1, 0x48, 0xb6, 0x1e, 0xdb, 0xb3, 0x31, 0xa8, 0xba, 0x83, +- 0x58, 0x3c, 0x86, 0x8a, 0xeb, 0x1d, 0x9c, 0x34, 0xda, 0xb0, 0x95, 0x82, +- 0x5f, 0x6d, 0x6b, 0xc4, 0xda, 0x60, 0x13, 0xb6, 0xe8, 0xd7, 0xa1, 0x38, +- 0xd6, 0x0f, 0xce, 0x65, 0x32, 0xd2, 0x3f, 0xaf, 0xaa, 0xea, 0x37, 0xe2, +- 0xf4, 0x4e, 0x13, 0xef, 0xef, 0xc4, 0x9a, 0x5a, 0x38, 0x4e, 0x3e, 0x1e, +- 0xed, 0x7e, 0x50, 0x09, 0x6a, 0x4f, 0xe5, 0xd9, 0xa1, 0x55, 0x5e, 0xca, +- 0x83, 0x36, 0x92, 0x9f, 0x39, 0x15, 0x6c, 0x2f, 0xc3, 0x76, 0x33, 0xd2, +- 0x97, 0x30, 0xbe, 0xd5, 0xf2, 0xdf, 0x68, 0x0f, 0xc5, 0x31, 0x6d, 0xcd, +- 0xbc, 0xc6, 0x3e, 0x69, 0xec, 0x4f, 0x13, 0xbe, 0x36, 0x19, 0xc6, 0x57, +- 0xd9, 0xb7, 0xaf, 0x4c, 0x4a, 0x1f, 0x23, 0x7b, 0x2c, 0xd4, 0x63, 0x34, +- 0xdb, 0x84, 0xa7, 0xf5, 0x36, 0x7c, 0x85, 0x7d, 0xec, 0x33, 0x62, 0x58, +- 0x9b, 0xb8, 0x8b, 0xfd, 0x51, 0xb0, 0xaa, 0xed, 0x2f, 0x4b, 0xfd, 0x8a, +- 0x68, 0x50, 0x55, 0x24, 0x1b, 0x22, 0x31, 0x4d, 0x15, 0x99, 0x17, 0xfa, +- 0x3b, 0x90, 0x81, 0xe5, 0x37, 0xa5, 0xcf, 0x37, 0x22, 0xcf, 0xfe, 0x7e, +- 0x79, 0x67, 0xd4, 0x58, 0xaf, 0x62, 0x65, 0x80, 0x7d, 0x7e, 0x20, 0x1e, +- 0x4d, 0x2c, 0x62, 0x9f, 0xc7, 0xf3, 0x2a, 0xc7, 0x13, 0xd2, 0xc6, 0xd8, +- 0xf7, 0xe4, 0x2a, 0x95, 0x7d, 0x67, 0x5f, 0x32, 0xec, 0x4b, 0x86, 0x7d, +- 0xc9, 0xb0, 0x2f, 0x6e, 0xbf, 0x63, 0xec, 0x73, 0x71, 0x8e, 0x46, 0xf2, +- 0xc7, 0xd9, 0xdf, 0x99, 0xfd, 0x6c, 0x62, 0xdf, 0x91, 0xaa, 0xe7, 0xbc, +- 0x35, 0xa7, 0x65, 0xde, 0x1c, 0xe7, 0x55, 0xc3, 0x71, 0x7e, 0x6e, 0x04, +- 0xa8, 0xbf, 0x0c, 0xed, 0xa0, 0xdc, 0x9f, 0xf9, 0x56, 0x85, 0x89, 0x4e, +- 0x9a, 0xa0, 0x73, 0xa4, 0x23, 0x9a, 0x68, 0x50, 0x54, 0x78, 0xf5, 0xa0, +- 0xd6, 0x52, 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0x32, 0xcb, 0xfb, 0x96, 0xe5, 0xfd, 0x06, 0x0b, 0x5f, 0x5d, 0x22, +- 0x3c, 0x53, 0xd6, 0x81, 0x2a, 0xc8, 0x27, 0xbb, 0x31, 0xbe, 0xf3, 0x3d, +- 0x3c, 0x32, 0xa8, 0xde, 0x5c, 0xc3, 0xd8, 0x7a, 0x8b, 0xb2, 0x19, 0x9e, +- 0xb8, 0xbc, 0x47, 0x2a, 0x6b, 0xe5, 0xcc, 0x5d, 0x26, 0xb3, 0xe8, 0xdb, +- 0x57, 0x83, 0x43, 0x41, 0xc7, 0x79, 0xda, 0x98, 0x27, 0x3f, 0x13, 0x20, +- 0xb8, 0x19, 0xa8, 0xa0, 0x2f, 0xdc, 0xfc, 0x5b, 0xbf, 0xdd, 0x58, 0xde, +- 0x3b, 0xd8, 0x88, 0xbb, 0x76, 0x3d, 0x8c, 0x9e, 0x5d, 0x7f, 0x8b, 0x4f, +- 0x0e, 0x2d, 0xec, 0x9f, 0xe7, 0x71, 0x9c, 0xab, 0xdb, 0xa7, 0x70, 0x2a, +- 0xce, 0xd8, 0x18, 0x52, 0xf0, 0xbd, 0xab, 0x16, 0x8a, 0x1c, 0xfe, 0xbd, +- 0xef, 0x68, 0xae, 0xbc, 0x5b, 0x4b, 0x3e, 0x92, 0x98, 0xc3, 0xf1, 0x53, +- 0xf6, 0x8a, 0xfa, 0xd2, 0xbb, 0xc2, 0x7f, 0x40, 0x5b, 0x3f, 0x16, 0x19, +- 0xfc, 0x2b, 0xcb, 0x78, 0xcd, 0x49, 0xae, 0x96, 0x7a, 0x15, 0xa5, 0x36, +- 0xfe, 0x96, 0x9c, 0x90, 0xbc, 0xd0, 0xe0, 0xff, 0x91, 0xeb, 0x44, 0x3e, +- 0x9f, 0x95, 0xe5, 0xbf, 0xe4, 0x24, 0xbb, 0xe5, 0xbb, 0x94, 0x59, 0xc7, +- 0x67, 0x52, 0xae, 0xfc, 0xec, 0xf9, 0x92, 0x9c, 0x4a, 0x68, 0x0d, 0x45, +- 0x39, 0x9f, 0xa6, 0x9c, 0x33, 0x8b, 0x93, 0x50, 0xaf, 0x9d, 0x29, 0xab, +- 0xdc, 0xee, 0xff, 0x3a, 0x2f, 0xab, 0x58, 0xee, 0x6f, 0xe6, 0xc8, 0xbe, +- 0x80, 0x7a, 0xed, 0xcc, 0x75, 0xf2, 0x0a, 0xfa, 0x6f, 0x34, 0xb8, 0xd5, +- 0x5d, 0x9f, 0x36, 0xb0, 0xf6, 0xe2, 0x1c, 0x4b, 0xb0, 0x03, 0xe3, 0x76, +- 0xb0, 0x94, 0x53, 0xc9, 0x2d, 0x13, 0x5f, 0x66, 0xce, 0xf6, 0x94, 0x1d, +- 0xe9, 0x5a, 0xa7, 0xb4, 0x26, 0x17, 0x31, 0xce, 0xa0, 0x5e, 0xd6, 0xb0, +- 0x13, 0xee, 0xef, 0xf9, 0xe5, 0xa3, 0x09, 0xe4, 0x69, 0x8f, 0xaf, 0xd8, +- 0x91, 0x0d, 0xa7, 0xdc, 0xfd, 0x3b, 0x13, 0x2f, 0xe7, 0x5f, 0x2d, 0xed, +- 0x33, 0x95, 0x7f, 0x4f, 0x6c, 0xe6, 0x1a, 0xaa, 0xcc, 0xbf, 0x9c, 0xb1, +- 0x6e, 0x90, 0xb5, 0x0a, 0xcb, 0xa2, 0x9f, 0xf7, 0x66, 0xac, 0xb0, 0x8a, +- 0xeb, 0x90, 0x0a, 0xc9, 0xbe, 0xc4, 0xd6, 0xd2, 0x6f, 0x52, 0xb1, 0xde, +- 0xef, 0x58, 0x13, 0x02, 0x8c, 0xd2, 0x39, 0xb6, 0x18, 0xac, 0xc9, 0x2b, +- 0xc8, 0xc5, 0x64, 0xbd, 0x01, 0xd6, 0x6c, 0x53, 0x43, 0x48, 0x3f, 0xcc, +- 0x71, 0xfb, 0x30, 0x87, 0xf9, 0x54, 0x7c, 0x61, 0x6b, 0x77, 0xbb, 0x3a, +- 0x57, 0x70, 0x36, 0x98, 0x54, 0x63, 0x12, 0x07, 0x50, 0x99, 0x96, 0xb3, +- 0x26, 0x56, 0x97, 0x9f, 0x98, 0xba, 0x98, 0xd8, 0x52, 0x11, 0x85, 0xf7, +- 0xbe, 0xbc, 0x17, 0xc1, 0x85, 0xbf, 0x70, 0x7e, 0x18, 0x8a, 0x61, 0xdb, +- 0x64, 0xb9, 0x0f, 0x06, 0xfe, 0x7b, 0xe1, 0xd2, 0x8c, 0xb3, 0x2c, 0xf3, +- 0x3d, 0x27, 0x39, 0x47, 0xda, 0x2e, 0xca, 0xfd, 0xe8, 0xbe, 0x4a, 0x1f, +- 0xa5, 0xaf, 0xcd, 0x1a, 0x51, 0x15, 0x5b, 0x8d, 0x89, 0x39, 0xf2, 0x9b, +- 0x3f, 0xf7, 0xb8, 0x67, 0xd3, 0x65, 0x0e, 0xe4, 0xfd, 0xf1, 0x04, 0xee, +- 0x93, 0xf7, 0x30, 0x19, 0xb3, 0xee, 0xcd, 0xbb, 0xef, 0x77, 0x42, 0x7e, +- 0x17, 0xf1, 0xde, 0x7c, 0x51, 0x7f, 0x0f, 0xe5, 0x03, 0xe4, 0xdd, 0x01, +- 0xcb, 0x6b, 0x6e, 0x80, 0x4f, 0x97, 0x33, 0x67, 0x65, 0x5d, 0xfe, 0xdf, +- 0x73, 0x24, 0x97, 0xff, 0x2a, 0xfd, 0xc9, 0xbb, 0x50, 0x3e, 0x5b, 0xf2, +- 0xae, 0xa2, 0x52, 0xfc, 0x7c, 0xc6, 0x7d, 0xef, 0x5d, 0x35, 0xd7, 0xd1, +- 0x2f, 0x67, 0xbb, 0xef, 0xeb, 0x89, 0x7e, 0x42, 0xa6, 0xe5, 0xcc, 0xd6, +- 0x03, 0xb4, 0x91, 0xde, 0x39, 0xa5, 0x77, 0x0f, 0xba, 0xee, 0x20, 0x8e, +- 0x2c, 0x22, 0xb7, 0x5a, 0xac, 0x44, 0xb4, 0x55, 0x4a, 0x37, 0xeb, 0x51, +- 0x4f, 0x05, 0x91, 0xa1, 0xb8, 0xbf, 0xbd, 0xeb, 0xa3, 0x8c, 0xfd, 0x76, +- 0xab, 0xe6, 0x53, 0x7f, 0x5e, 0x3a, 0x7b, 0x2d, 0x7b, 0xf1, 0x29, 0x3c, +- 0x6f, 0xcf, 0xc1, 0xd4, 0x6f, 0xc9, 0x3d, 0xbf, 0x66, 0xfd, 0x4f, 0x41, +- 0x62, 0x88, 0x4f, 0x8f, 0x6c, 0x8c, 0x7b, 0x22, 0xeb, 0xa7, 0xe9, 0xd3, +- 0x85, 0xb8, 0x9e, 0xfa, 0x1a, 0xdb, 0xf8, 0x3e, 0xb9, 0x85, 0x3d, 0x43, +- 0x7e, 0x51, 0x56, 0x6b, 0x4f, 0x85, 0x7a, 0xc6, 0x29, 0xbe, 0x77, 0x2d, +- 0xbf, 0xfb, 0xbb, 0x06, 0xc1, 0xb4, 0xe5, 0x84, 0x28, 0x73, 0xbe, 0x19, +- 0xd9, 0x53, 0xaf, 0xea, 0xd9, 0xcf, 0xab, 0x9b, 0xb1, 0x56, 0x8e, 0x7c, +- 0x98, 0x11, 0xed, 0xd3, 0xb4, 0x8f, 0x76, 0x57, 0x46, 0x32, 0x56, 0x81, +- 0x8f, 0x3a, 0xd3, 0xc6, 0xf1, 0x41, 0xd6, 0x28, 0x59, 0xce, 0xdd, 0xe3, +- 0x97, 0xf7, 0x77, 0x98, 0x63, 0xdb, 0xf2, 0xbb, 0xa6, 0x6e, 0x33, 0xa5, +- 0x7d, 0x24, 0xe6, 0xc8, 0x8c, 0x97, 0xf7, 0xc8, 0x6f, 0xc8, 0x55, 0x07, +- 0x70, 0xaf, 0x2d, 0xeb, 0x0e, 0xff, 0x3f, 0x45, 0x18, 0xff, 0x64, 0x3c, +- 0x59, 0x00, 0x00, 0x00 }; ++ 0xa5, 0xbc, 0x0d, 0x74, 0x5b, 0xe5, 0x99, 0x2e, 0xfa, 0xec, 0x2d, 0xc9, ++ 0x96, 0x6d, 0xd9, 0xde, 0x76, 0x14, 0xa3, 0x80, 0x4b, 0xa4, 0x78, 0xcb, ++ 0x11, 0xb1, 0x81, 0x2d, 0xc7, 0x01, 0xd1, 0x6e, 0x88, 0xea, 0x38, 0xc1, ++ 0x40, 0xa0, 0x4e, 0x08, 0xd4, 0xe1, 0xb0, 0x2e, 0x3a, 0x49, 0x00, 0x43, ++ 0xd3, 0x39, 0xa6, 0x87, 0xe9, 0x75, 0xb9, 0xe9, 0xf5, 0x6e, 0xec, 0xc4, ++ 0x86, 0xc8, 0x92, 0x6d, 0xf2, 0xc7, 0x3a, 0xb3, 0x06, 0xc5, 0x71, 0xe2, ++ 0x40, 0x25, 0x19, 0x5a, 0x66, 0x26, 0xbd, 0xb7, 0x1d, 0x3c, 0x21, 0x81, ++ 0xa4, 0xfc, 0x77, 0x3a, 0xa7, 0xb4, 0xeb, 0xcc, 0xd4, 0x13, 0x08, 0xff, ++ 0xd0, 0x94, 0xf6, 0xf4, 0x84, 0xe9, 0xa4, 0xfb, 0x3e, 0xef, 0x96, 0x95, ++ 0x98, 0xf4, 0x6f, 0xce, 0xba, 0x5e, 0x4b, 0xcb, 0xda, 0x7b, 0x7f, 0x3f, ++ 0xef, 0xf7, 0x7e, 0xef, 0xfb, 0xbc, 0xcf, 0xfb, 0x7d, 0xdf, 0xd6, 0x22, ++ 0xa0, 0x1c, 0xb3, 0x7f, 0x95, 0xfc, 0x5c, 0xb1, 0xac, 0x67, 0xe3, 0xfd, ++ 0xc6, 0x15, 0x86, 0x5c, 0xbb, 0x01, 0x0f, 0xfe, 0xd0, 0x9f, 0x89, 0xd8, ++ 0x85, 0xb7, 0x82, 0x7f, 0xb0, 0xe0, 0x1f, 0xf9, 0x8b, 0x21, 0xa4, 0xf0, ++ 0x5f, 0xd3, 0x05, 0xb7, 0x5d, 0x80, 0x56, 0x94, 0x43, 0x3e, 0xf0, 0xaa, ++ 0x66, 0x7b, 0x57, 0x9b, 0x0e, 0xaf, 0xcb, 0x7c, 0xf0, 0x8e, 0x8d, 0x3a, ++ 0x10, 0xcf, 0x36, 0x05, 0x57, 0xe0, 0xac, 0x6d, 0xf9, 0xdd, 0x90, 0xfb, ++ 0x9f, 0x33, 0xff, 0xfd, 0xf1, 0x1f, 0x5c, 0x1d, 0x3a, 0x9d, 0x71, 0xc1, ++ 0xab, 0x99, 0x43, 0xd0, 0x1a, 0xe1, 0xad, 0x67, 0x9d, 0xbf, 0x5a, 0x9c, ++ 0x52, 0x51, 0x55, 0x6c, 0x2b, 0x14, 0xc8, 0x20, 0xa4, 0x59, 0x08, 0x45, ++ 0x2c, 0x20, 0xe1, 0x36, 0x91, 0x28, 0x35, 0xbd, 0x28, 0xd1, 0x4b, 0x90, ++ 0xd0, 0x7a, 0x83, 0x03, 0xad, 0x40, 0x5b, 0xd2, 0x1b, 0x3c, 0x99, 0x05, ++ 0x36, 0x26, 0xbd, 0x98, 0x71, 0xf9, 0x82, 0x6f, 0x66, 0xbf, 0x52, 0x55, ++ 0xd0, 0x4b, 0x1c, 0x2e, 0x1d, 0x09, 0xd5, 0x94, 0xfb, 0x08, 0xae, 0xc8, ++ 0x4a, 0x5d, 0x60, 0x7b, 0xfa, 0xc1, 0xe0, 0xa9, 0x64, 0x48, 0xdb, 0x8e, ++ 0xa6, 0xc0, 0x38, 0x4a, 0x91, 0xf0, 0x87, 0x22, 0x40, 0xf6, 0xec, 0x23, ++ 0x69, 0x05, 0x1e, 0x7d, 0x1e, 0xda, 0xf7, 0x01, 0x0f, 0xa7, 0x43, 0x71, ++ 0x9d, 0xc3, 0x1c, 0x9a, 0x92, 0xba, 0x21, 0x2d, 0xc3, 0xe7, 0x03, 0x69, ++ 0x60, 0x5b, 0x7a, 0x1e, 0xb6, 0x8f, 0xd8, 0x78, 0xce, 0x68, 0xd0, 0xf6, ++ 0xb3, 0x87, 0xad, 0xce, 0xf3, 0x79, 0xb0, 0x32, 0xf2, 0xfc, 0x5d, 0xfb, ++ 0x07, 0x8b, 0x35, 0x3c, 0x35, 0xe5, 0xc7, 0xb3, 0x53, 0x35, 0x78, 0x78, ++ 0xa4, 0x06, 0x83, 0x23, 0x11, 0xa8, 0xba, 0x8d, 0x48, 0x34, 0x82, 0x92, ++ 0x6b, 0x6c, 0xbc, 0x69, 0x34, 0x63, 0x1b, 0x1b, 0x7e, 0xad, 0xb9, 0x0e, ++ 0x1b, 0xb4, 0x7a, 0x0c, 0xe8, 0xd7, 0xa0, 0x30, 0xd6, 0xec, 0xd9, 0x74, ++ 0x1a, 0x09, 0x8f, 0xe9, 0x56, 0x55, 0xfd, 0x3a, 0x7c, 0xbc, 0xcb, 0xc4, ++ 0x47, 0xbb, 0x70, 0x67, 0x15, 0x6c, 0x3b, 0x1b, 0x0d, 0x77, 0x6e, 0x56, ++ 0xb4, 0xe0, 0x93, 0x59, 0x0a, 0xb4, 0xd6, 0xcd, 0xf6, 0x10, 0x1c, 0xcf, ++ 0xce, 0xd5, 0x3d, 0xfb, 0x4b, 0xb3, 0xdf, 0xb4, 0xc8, 0x12, 0xc0, 0x0f, ++ 0x16, 0x3f, 0x40, 0xbb, 0x28, 0x8c, 0x69, 0x5b, 0xfa, 0x0d, 0xca, 0x14, ++ 0xa4, 0x3c, 0xf5, 0xf8, 0xee, 0x54, 0x00, 0xdf, 0xa1, 0x6c, 0x4f, 0x4f, ++ 0x89, 0x8c, 0xa1, 0xbd, 0x16, 0x6a, 0x30, 0x31, 0x52, 0x8f, 0xa7, 0xf4, ++ 0x66, 0x3c, 0x4d, 0x19, 0xfb, 0x8d, 0x08, 0x36, 0xc4, 0xfe, 0x13, 0xe5, ++ 0x51, 0xb0, 0xb6, 0x79, 0xe3, 0xac, 0x5c, 0xa1, 0x20, 0x54, 0x15, 0xf1, ++ 0xda, 0x50, 0x24, 0xa8, 0x4a, 0x9b, 0xe7, 0xe5, 0x1d, 0x4e, 0xc3, 0xf2, ++ 0x9a, 0x22, 0xf3, 0x75, 0xc8, 0x52, 0xde, 0x6f, 0xef, 0x0a, 0x1b, 0xdd, ++ 0x2a, 0x56, 0xfb, 0x28, 0xf3, 0xfd, 0xd1, 0x70, 0x6c, 0x09, 0x65, 0x9e, ++ 0xcc, 0xaa, 0x1c, 0x8f, 0x3f, 0x78, 0x90, 0xb2, 0xc7, 0xd7, 0xaa, 0x94, ++ 0x9d, 0xb2, 0xa4, 0x29, 0x4b, 0x9a, 0xb2, 0xa4, 0x29, 0x8b, 0x23, 0x77, ++ 0x84, 0x32, 0x17, 0xe6, 0x68, 0x3c, 0x3b, 0x43, 0x79, 0xe7, 0xca, 0x59, ++ 0x4f, 0xd9, 0x91, 0xa8, 0x31, 0x1f, 0x0c, 0x36, 0xa4, 0xa8, 0xef, 0xb4, ++ 0x6d, 0xbf, 0x66, 0xd8, 0xf6, 0x27, 0x86, 0x8f, 0xfa, 0x4b, 0xd3, 0x0e, ++ 0x8a, 0xf2, 0x2c, 0xb4, 0x4a, 0x4c, 0xb4, 0xd3, 0x04, 0xed, 0x63, 0xad, ++ 0xe1, 0x58, 0xad, 0xa2, 0xc2, 0xad, 0x6b, 0xc1, 0xc5, 0xf9, 0x10, 0xbd, ++ 0xc1, 0x1f, 0x0c, 0xe7, 0x11, 0xd4, 0xf3, 0x6c, 0xeb, 0x33, 0xfd, 0x86, ++ 0xb4, 0x69, 0x48, 0xbf, 0x41, 0xf6, 0x3f, 0x33, 0x3b, 0x77, 0xd2, 0x7e, ++ 0x80, 0x7d, 0x4a, 0xff, 0xd2, 0xb6, 0x6d, 0xff, 0xd2, 0x80, 0xae, 0x21, ++ 0x6c, 0x8d, 0xd2, 0xfe, 0x5c, 0xa6, 0x16, 0xec, 0xc9, 0xf2, 0xf9, 0xb9, ++ 0x36, 0x0a, 0xf3, 0xb1, 0x21, 0x1b, 0x9c, 0x1d, 0x43, 0x88, 0x22, 0x88, ++ 0x1d, 0x04, 0x12, 0x15, 0xa6, 0x26, 0xb2, 0x77, 0xfe, 0x97, 0xe1, 0x3e, ++ 0x3b, 0xa0, 0x3f, 0x60, 0xf9, 0x5a, 0xf5, 0x9e, 0x33, 0x8a, 0x2f, 0xf6, ++ 0xf2, 0xb2, 0x28, 0xca, 0x75, 0x58, 0x65, 0x26, 0x3a, 0xbf, 0x9a, 0x2b, ++ 0xa7, 0x0e, 0xbf, 0x7f, 0xeb, 0xe6, 0x9c, 0x17, 0x4b, 0x72, 0xff, 0xe4, ++ 0x46, 0x95, 0x41, 0x9b, 0x7b, 0xd4, 0x5d, 0x18, 0x53, 0xc7, 0xec, 0xd8, ++ 0x1c, 0x9b, 0xf7, 0x9e, 0x4a, 0x9e, 0xb6, 0x4b, 0xf4, 0xb2, 0x2f, 0xbb, ++ 0x4c, 0x3d, 0x78, 0x10, 0x38, 0xbd, 0xa1, 0xb5, 0x13, 0x5b, 0x35, 0x05, ++ 0x0b, 0xf4, 0x18, 0xac, 0xa9, 0xb3, 0x15, 0x85, 0xb2, 0x75, 0x09, 0xea, ++ 0x01, 0x47, 0x93, 0x7e, 0xd6, 0xc9, 0xe0, 0x54, 0xd2, 0xb6, 0x59, 0x5e, ++ 0xeb, 0xc7, 0xad, 0xb7, 0x2e, 0x34, 0x8f, 0x2c, 0xf4, 0xe0, 0x5a, 0xdc, ++ 0xa5, 0x61, 0xcb, 0xb1, 0xd6, 0x4f, 0x94, 0xf1, 0x9d, 0x9d, 0xb0, 0x26, ++ 0x5d, 0x88, 0x6b, 0x09, 0xfe, 0xbf, 0xf4, 0xd2, 0x9b, 0x62, 0x9d, 0xd8, ++ 0x31, 0x79, 0x86, 0xf7, 0xdd, 0xbc, 0x17, 0xc3, 0x70, 0xfa, 0xd2, 0x4b, ++ 0x57, 0xc7, 0x12, 0x48, 0x4e, 0xca, 0x77, 0x37, 0x32, 0x35, 0x09, 0x0c, ++ 0xec, 0x09, 0xa2, 0x4a, 0xef, 0x44, 0x6a, 0x52, 0xbe, 0x7f, 0x0b, 0xe9, ++ 0x66, 0x05, 0x33, 0x6b, 0x2c, 0xea, 0xba, 0x13, 0xdb, 0xf6, 0x28, 0xee, ++ 0xc3, 0xbc, 0xc6, 0xad, 0x70, 0x7b, 0x1c, 0xbf, 0x8b, 0xb9, 0x57, 0x24, ++ 0x4d, 0x6d, 0x81, 0x6e, 0xdb, 0x7d, 0x86, 0x0b, 0x9f, 0xce, 0xb3, 0xed, ++ 0x41, 0xa3, 0x1a, 0x33, 0x9d, 0x9d, 0x9c, 0xb7, 0x0d, 0xb0, 0xf6, 0x6f, ++ 0xc0, 0xd0, 0xa3, 0x54, 0xd7, 0x1a, 0xb6, 0x35, 0x29, 0x32, 0x24, 0xd8, ++ 0x06, 0x75, 0x96, 0x16, 0xb9, 0xba, 0xf8, 0xf9, 0x3a, 0x3f, 0xf0, 0x2a, ++ 0xa6, 0x85, 0x70, 0xb6, 0x68, 0xdb, 0x1b, 0xb0, 0xdd, 0xa9, 0xf7, 0x6b, ++ 0x1b, 0xb7, 0x15, 0xea, 0x0c, 0x4c, 0xb2, 0xef, 0x49, 0xa9, 0x27, 0xf5, ++ 0xff, 0x58, 0x3d, 0xab, 0xd3, 0x85, 0x50, 0xc7, 0x2a, 0xc5, 0x8d, 0xc8, ++ 0x30, 0xa8, 0xa3, 0x6a, 0x45, 0x7c, 0xa4, 0x44, 0x71, 0xf1, 0x7f, 0x0c, ++ 0x8f, 0x71, 0xde, 0xfb, 0x0d, 0xea, 0x3e, 0xdd, 0x8c, 0xc1, 0x74, 0x3c, ++ 0x44, 0x34, 0xb3, 0x3c, 0x66, 0x27, 0x54, 0x33, 0xdc, 0xb1, 0x15, 0x52, ++ 0x1e, 0x4a, 0xb9, 0x09, 0x77, 0xb6, 0x75, 0xc6, 0xfb, 0x72, 0x52, 0xef, ++ 0x7a, 0x52, 0xf1, 0xd0, 0x28, 0x45, 0xdf, 0x33, 0xde, 0x57, 0x93, 0x0a, ++ 0xde, 0xd1, 0xc3, 0x3d, 0xef, 0x2b, 0x33, 0xde, 0x57, 0xb2, 0x1a, 0x16, ++ 0x0c, 0x87, 0xba, 0x2c, 0x25, 0x86, 0xef, 0x65, 0xfd, 0x08, 0x0c, 0x9b, ++ 0x38, 0x9c, 0x35, 0xf0, 0xc4, 0x67, 0xfc, 0xf5, 0x0f, 0xfe, 0x59, 0x2e, ++ 0xce, 0xdb, 0xa6, 0x64, 0x10, 0x5b, 0x8d, 0xb3, 0x76, 0x5c, 0x43, 0xa2, ++ 0xda, 0x9c, 0xf1, 0x7e, 0x34, 0x0c, 0xa5, 0xca, 0xd4, 0x03, 0x79, 0xe5, ++ 0x5f, 0xed, 0x84, 0x5f, 0x8a, 0x51, 0x3e, 0x07, 0x73, 0x4c, 0xec, 0x98, ++ 0x32, 0x88, 0x47, 0xa7, 0xed, 0x0a, 0xda, 0x52, 0x89, 0x79, 0x31, 0x26, ++ 0x77, 0xea, 0x78, 0x82, 0xf3, 0xfd, 0xa1, 0x31, 0x1d, 0xf3, 0x41, 0xef, ++ 0xfc, 0x00, 0xa1, 0xf8, 0x12, 0xc5, 0xc4, 0xf1, 0xac, 0x8e, 0x89, 0xa4, ++ 0x89, 0xe7, 0x92, 0x0d, 0xb4, 0x83, 0xa5, 0x88, 0x07, 0xa4, 0x9d, 0x20, ++ 0x72, 0x94, 0x7b, 0x3c, 0xdc, 0x89, 0x6a, 0x33, 0x86, 0x23, 0x94, 0xfb, ++ 0xe3, 0x65, 0xd2, 0x8e, 0x81, 0x57, 0xfe, 0x03, 0xb2, 0x12, 0x87, 0xf1, ++ 0x18, 0x65, 0x8d, 0x2d, 0x3d, 0x6b, 0x63, 0x9e, 0x17, 0x27, 0x8d, 0x8b, ++ 0x68, 0x33, 0x62, 0xd3, 0x5e, 0xf7, 0x50, 0x52, 0xc3, 0xa1, 0xac, 0xcf, ++ 0xdd, 0x9f, 0xf4, 0x63, 0x3f, 0xfd, 0x62, 0x81, 0x09, 0x2b, 0xc0, 0x76, ++ 0x17, 0x10, 0x7f, 0xf2, 0x3b, 0xeb, 0x31, 0xb5, 0x33, 0x64, 0xbc, 0xaa, ++ 0x04, 0x70, 0x70, 0xe2, 0x62, 0xe4, 0x76, 0x2a, 0x98, 0x0c, 0x53, 0x76, ++ 0x7e, 0xff, 0xf6, 0xce, 0x4b, 0x91, 0xdd, 0xe9, 0xc2, 0x0e, 0x47, 0xaf, ++ 0x0e, 0x1e, 0xcc, 0xfe, 0xbf, 0x18, 0x99, 0x09, 0xb8, 0x97, 0x0c, 0x6b, ++ 0x78, 0x32, 0xeb, 0x76, 0xeb, 0xc3, 0x7e, 0x4c, 0x64, 0x9f, 0xe4, 0xbc, ++ 0x49, 0xdb, 0x41, 0x8c, 0x27, 0xc7, 0xf8, 0x5d, 0xc6, 0x61, 0x29, 0x05, ++ 0xdc, 0x2f, 0xe0, 0xf0, 0xb3, 0x53, 0x47, 0x95, 0x82, 0x4f, 0x18, 0xc4, ++ 0x73, 0xb1, 0x0f, 0xd1, 0x71, 0x39, 0x82, 0x07, 0xca, 0x11, 0xd9, 0xe5, ++ 0xc6, 0xe2, 0x5d, 0x62, 0x17, 0xb6, 0xed, 0x89, 0x56, 0xe3, 0x6d, 0x03, ++ 0xf3, 0x4b, 0x10, 0x0e, 0x8e, 0x3b, 0xfd, 0x59, 0xd8, 0x94, 0x85, 0xd7, ++ 0xc3, 0xb6, 0x0f, 0x24, 0xdd, 0xe8, 0xff, 0x0c, 0xae, 0x6b, 0xd8, 0xaf, ++ 0x85, 0x18, 0x8a, 0x14, 0xda, 0xbc, 0xdb, 0x70, 0xab, 0xe2, 0x8b, 0xba, ++ 0xf6, 0x1c, 0x4a, 0xd0, 0xde, 0xa9, 0x30, 0x86, 0x59, 0x01, 0x96, 0x3c, ++ 0x3b, 0xb8, 0xb8, 0x1c, 0x96, 0x3f, 0x14, 0xb8, 0x17, 0x72, 0x4f, 0x45, ++ 0xd9, 0x15, 0xbf, 0xb2, 0x83, 0xb7, 0x49, 0x5b, 0x6e, 0x6c, 0x9b, 0xba, ++ 0x10, 0xaf, 0x81, 0xee, 0xa4, 0xd8, 0x9b, 0x4e, 0xbd, 0x3d, 0xaf, 0x08, ++ 0xfe, 0x4a, 0x2c, 0x2c, 0xf4, 0xff, 0x01, 0xc7, 0x24, 0xf5, 0x25, 0x36, ++ 0xb9, 0x03, 0xdb, 0xa8, 0x10, 0x37, 0xef, 0x0f, 0x24, 0x8f, 0x53, 0xa6, ++ 0x56, 0xca, 0x23, 0xbe, 0x6d, 0xe0, 0xef, 0xa7, 0x9a, 0xf1, 0x77, 0x53, ++ 0x11, 0xfc, 0xed, 0x94, 0x8e, 0xbf, 0x99, 0x0a, 0xe2, 0x99, 0xcf, 0xe0, ++ 0xfd, 0x5a, 0xce, 0x8d, 0xc8, 0x6f, 0x60, 0x20, 0x5d, 0x82, 0xc1, 0x9d, ++ 0xe5, 0x18, 0xda, 0xd9, 0x60, 0xbc, 0x4b, 0x9c, 0xfe, 0xef, 0xc6, 0x6a, ++ 0x4c, 0xd7, 0xb6, 0x3a, 0xb8, 0xb8, 0x83, 0xf7, 0x93, 0x3b, 0x1b, 0x18, ++ 0x6b, 0x6c, 0xbb, 0x2d, 0xda, 0xd4, 0x71, 0x84, 0xb8, 0x1f, 0x9c, 0x1f, ++ 0x0a, 0x4e, 0xab, 0xa1, 0x60, 0x9c, 0x64, 0x22, 0xdd, 0xac, 0x62, 0x66, ++ 0x7e, 0x28, 0x43, 0x6f, 0x87, 0x5f, 0xbf, 0x95, 0x72, 0x86, 0x82, 0x96, ++ 0x6a, 0xd0, 0x5f, 0x18, 0x4b, 0xd4, 0x56, 0x62, 0x50, 0x39, 0x4e, 0xef, ++ 0x0c, 0x0d, 0x59, 0x2a, 0xfd, 0xb7, 0xd6, 0xb6, 0x6b, 0x5b, 0xd0, 0x73, ++ 0x91, 0x89, 0xf8, 0x7c, 0xc6, 0x88, 0x4b, 0x4d, 0x13, 0x8f, 0x31, 0x7e, ++ 0xc6, 0xd2, 0x7a, 0xe0, 0x22, 0xd7, 0x5a, 0xfc, 0xa5, 0xd6, 0x74, 0x66, ++ 0xbf, 0x1a, 0xc3, 0xcc, 0x45, 0x08, 0xaa, 0xe6, 0x8d, 0xc4, 0x72, 0x99, ++ 0x27, 0x8e, 0x5b, 0x6f, 0xa5, 0x8e, 0x58, 0xc1, 0xdf, 0xd0, 0x33, 0xaa, ++ 0x36, 0x04, 0x0c, 0xf6, 0xdd, 0xa9, 0xda, 0xf6, 0x03, 0xc6, 0x2f, 0xec, ++ 0x60, 0x9d, 0x6d, 0x8f, 0x19, 0xd2, 0x5f, 0x10, 0xb5, 0xb4, 0xa9, 0x1a, ++ 0xda, 0x54, 0x4b, 0xbe, 0x1c, 0x1f, 0xee, 0x84, 0x75, 0x91, 0x19, 0xea, ++ 0xda, 0xac, 0x96, 0xe3, 0x83, 0x89, 0x72, 0xbc, 0x4f, 0xfc, 0x7a, 0x6f, ++ 0xa7, 0x6d, 0xaf, 0xe4, 0xbc, 0x46, 0xa2, 0x58, 0xe6, 0x45, 0xf8, 0xf4, ++ 0x41, 0x58, 0xf8, 0x1d, 0xcb, 0xfe, 0x7a, 0x67, 0x00, 0xff, 0x73, 0xe7, ++ 0x17, 0xf0, 0x4c, 0x6d, 0xbc, 0x66, 0x1e, 0xe3, 0xe6, 0x5b, 0xb4, 0xd5, ++ 0x33, 0xc9, 0x50, 0xcf, 0x56, 0x84, 0x8e, 0x93, 0xd3, 0x58, 0x47, 0x94, ++ 0x50, 0xef, 0x02, 0x57, 0xa8, 0xfb, 0xb4, 0xe2, 0xc7, 0xc7, 0xf4, 0x89, ++ 0x8f, 0xb2, 0x0d, 0xb1, 0x7f, 0x64, 0xff, 0xbf, 0x31, 0xfe, 0xce, 0x9e, ++ 0xae, 0x13, 0xfd, 0x89, 0xae, 0xa8, 0x6f, 0xe2, 0xc4, 0xdf, 0x31, 0x6e, ++ 0xfd, 0x6d, 0x9a, 0xfa, 0xa6, 0x3c, 0xcf, 0xfc, 0x5e, 0x4c, 0x93, 0xb9, ++ 0x8d, 0x71, 0x6e, 0xeb, 0xf1, 0x7f, 0x3b, 0x63, 0x3b, 0x61, 0xff, 0x9f, ++ 0x7e, 0x19, 0x5f, 0xcf, 0xfc, 0x82, 0x4d, 0xca, 0x38, 0x8f, 0xdb, 0x89, ++ 0x4e, 0x19, 0xa3, 0x8c, 0xd5, 0xd1, 0x63, 0xf7, 0x6b, 0x4a, 0xaf, 0x8a, ++ 0x72, 0xdb, 0xfe, 0x6e, 0x74, 0xf6, 0xb9, 0xbf, 0x38, 0xd6, 0x2f, 0xf2, ++ 0xbe, 0x8c, 0xf7, 0x77, 0x2e, 0xd1, 0x7b, 0x50, 0x5d, 0xc6, 0xeb, 0x90, ++ 0x15, 0x87, 0x7c, 0x9f, 0xef, 0xe5, 0xbd, 0x48, 0xfc, 0xdc, 0xbd, 0x97, ++ 0x2a, 0x3f, 0x5b, 0xc6, 0x9a, 0xf5, 0x83, 0x3b, 0x78, 0x2d, 0xe3, 0x79, ++ 0x8d, 0xb6, 0xf3, 0xc7, 0x6c, 0xa5, 0xd9, 0xb1, 0xf1, 0xa7, 0xa6, 0xde, ++ 0x96, 0xd8, 0x63, 0xd5, 0x9a, 0x5e, 0x4b, 0x35, 0x11, 0x24, 0xdc, 0x10, ++ 0x4f, 0x7b, 0x10, 0xcc, 0x5a, 0xb8, 0xbd, 0xd5, 0x85, 0x07, 0x5b, 0x15, ++ 0xcc, 0xd7, 0x7b, 0xb0, 0xe6, 0x2a, 0xcb, 0x9e, 0xa7, 0x3f, 0xa1, 0x8a, ++ 0xdf, 0x35, 0x32, 0x3e, 0x07, 0x52, 0x0a, 0xaa, 0xbf, 0xa0, 0xe0, 0x64, ++ 0x54, 0xa7, 0xcd, 0x0d, 0x90, 0x6b, 0x01, 0x8b, 0x53, 0xf0, 0x56, 0x72, ++ 0xfe, 0x73, 0xc3, 0xf0, 0x96, 0x13, 0x6b, 0x6e, 0x1c, 0x6e, 0xe8, 0x79, ++ 0x9b, 0xd8, 0x94, 0x57, 0x42, 0x5d, 0xd4, 0xb9, 0x51, 0xa5, 0x84, 0x3a, ++ 0x6e, 0x52, 0x42, 0xc1, 0x46, 0x45, 0xfa, 0x30, 0x11, 0xc9, 0x0e, 0x10, ++ 0xe3, 0xe4, 0x7b, 0x0c, 0x7a, 0xf6, 0x27, 0x22, 0xbb, 0xa5, 0x99, 0xe2, ++ 0x0f, 0x3d, 0xf4, 0x87, 0xb7, 0xed, 0x8c, 0x16, 0x0a, 0x66, 0x20, 0xd7, ++ 0xdd, 0xbc, 0x86, 0xb7, 0xc4, 0xdc, 0x8c, 0xe7, 0x93, 0xf3, 0x66, 0xf5, ++ 0x5a, 0x94, 0x73, 0xae, 0x2c, 0xff, 0x62, 0xc7, 0xfd, 0x05, 0x59, 0x9a, ++ 0x52, 0x03, 0x48, 0xa6, 0xe1, 0x2d, 0x65, 0x3f, 0xef, 0xb0, 0x6e, 0x19, ++ 0xfb, 0xb8, 0x6c, 0x58, 0x6c, 0x3e, 0x14, 0x79, 0x9f, 0x5c, 0x73, 0x91, ++ 0xd2, 0x14, 0x7c, 0x12, 0xa1, 0x33, 0x9b, 0x50, 0x90, 0x25, 0x9c, 0x75, ++ 0x38, 0x8e, 0x23, 0xcb, 0xf2, 0x2c, 0x94, 0x05, 0xc3, 0xf0, 0xb9, 0xf4, ++ 0x32, 0x34, 0xcc, 0x73, 0xfa, 0x52, 0x2a, 0x87, 0x2d, 0x63, 0xfc, 0xf2, ++ 0x25, 0x88, 0xaf, 0x73, 0x30, 0x51, 0xa9, 0x1a, 0xfe, 0x56, 0xf4, 0xf8, ++ 0xe5, 0x8d, 0x20, 0xb5, 0x72, 0xae, 0xab, 0x53, 0x6e, 0xbc, 0x59, 0x43, ++ 0x0e, 0xc5, 0xb2, 0x81, 0xd4, 0xb7, 0x6c, 0x6d, 0xb1, 0x0d, 0x77, 0x0b, ++ 0x94, 0xf5, 0xa9, 0xdf, 0x72, 0x5c, 0x3a, 0xd6, 0xe7, 0x0b, 0xe5, 0xb6, ++ 0x27, 0x5d, 0x98, 0xf6, 0x17, 0xb8, 0x5c, 0xe6, 0x76, 0xc4, 0xe5, 0x5e, ++ 0x7f, 0x12, 0xca, 0xe3, 0xc9, 0xd0, 0x21, 0x40, 0x8f, 0xfc, 0x57, 0xc4, ++ 0xff, 0xc1, 0x83, 0x3e, 0x7c, 0xba, 0x34, 0x6c, 0x2d, 0x70, 0x85, 0x7b, ++ 0xfd, 0xaa, 0xe1, 0x4d, 0x53, 0x9e, 0x14, 0xcb, 0x0c, 0xf3, 0x73, 0x3c, ++ 0xac, 0x6b, 0xf3, 0x94, 0xf8, 0x7a, 0x95, 0x65, 0x0a, 0x7c, 0x31, 0x1c, ++ 0x5b, 0xa7, 0x18, 0xde, 0xc1, 0xac, 0xb4, 0x15, 0x53, 0xda, 0xf3, 0xe3, ++ 0xea, 0x6c, 0xae, 0xc0, 0x76, 0x83, 0x58, 0x48, 0x1e, 0xd6, 0x4f, 0x1d, ++ 0x1d, 0x1b, 0xb3, 0xb1, 0xdf, 0xf0, 0xa2, 0x4f, 0xeb, 0x44, 0x99, 0xfe, ++ 0xcf, 0xf6, 0x7d, 0xb3, 0xe3, 0x18, 0x48, 0x36, 0xf9, 0x0b, 0xfa, 0xfc, ++ 0x44, 0xea, 0x39, 0xf7, 0xb6, 0x25, 0x5f, 0x28, 0x45, 0x95, 0xc4, 0xfa, ++ 0xe2, 0xbd, 0x26, 0x6d, 0x82, 0x3e, 0x2b, 0xfa, 0x88, 0x6b, 0xc2, 0xb3, ++ 0xe2, 0x11, 0x0f, 0xe4, 0x9e, 0x0b, 0x19, 0x77, 0x3c, 0xe0, 0xc2, 0xbf, ++ 0xdb, 0xf1, 0x75, 0x72, 0xaf, 0x1c, 0x89, 0xce, 0xa6, 0x80, 0x1b, 0x4d, ++ 0xb1, 0x6d, 0xc4, 0x8e, 0x99, 0x75, 0x6d, 0x7c, 0x16, 0x36, 0x9e, 0x43, ++ 0x43, 0x70, 0x1b, 0xe4, 0xfb, 0xa7, 0xb4, 0xf3, 0x36, 0xa9, 0xcb, 0x32, ++ 0x05, 0x0e, 0xf5, 0x1c, 0xb1, 0x69, 0xc0, 0xb0, 0xf1, 0xbc, 0x01, 0xab, ++ 0xd4, 0x3c, 0xac, 0x9c, 0x4c, 0xfe, 0xce, 0x8e, 0xbb, 0xb1, 0x9a, 0x18, ++ 0x6d, 0x90, 0x3e, 0x07, 0xbd, 0x66, 0x38, 0x48, 0x87, 0xd5, 0x5c, 0xc4, ++ 0xfc, 0x99, 0xec, 0x80, 0x72, 0x2a, 0x3b, 0xa4, 0xbc, 0xe5, 0xc4, 0xfa, ++ 0xc3, 0xca, 0x9b, 0x59, 0x89, 0xd7, 0xf5, 0xc1, 0x63, 0xe4, 0x4b, 0xe4, ++ 0x66, 0x6a, 0xbf, 0x41, 0xfd, 0x1a, 0x55, 0xcc, 0x17, 0xf4, 0xc8, 0x38, ++ 0xe5, 0x3d, 0xd0, 0x0a, 0x63, 0xd0, 0xf0, 0x60, 0x46, 0x83, 0xaf, 0xdf, ++ 0x70, 0xcb, 0x35, 0xf3, 0x0a, 0xa9, 0x5b, 0x1f, 0xdc, 0x96, 0x3d, 0x6b, ++ 0x27, 0xb4, 0xc2, 0xf5, 0x81, 0xd6, 0xe2, 0xbd, 0x5f, 0xd9, 0xd3, 0xeb, ++ 0x54, 0x5e, 0x7f, 0xc9, 0xc5, 0xa1, 0xb0, 0xee, 0xdc, 0x78, 0x20, 0xdc, ++ 0x4c, 0x25, 0x9f, 0xe1, 0x84, 0x33, 0x2e, 0x64, 0x98, 0x5e, 0xf5, 0xa7, ++ 0x57, 0xd1, 0x47, 0x03, 0x8c, 0xe5, 0x26, 0xf9, 0xaa, 0xcc, 0xbd, 0xc2, ++ 0xe7, 0x3e, 0xac, 0x4c, 0x5e, 0xed, 0x2a, 0xe8, 0x54, 0x25, 0x4d, 0x73, ++ 0x91, 0x37, 0x0a, 0x57, 0xbc, 0x30, 0x16, 0xd4, 0x07, 0xdf, 0xa5, 0xdc, ++ 0x65, 0xba, 0x1e, 0x29, 0x53, 0xea, 0x83, 0xa7, 0xb2, 0x26, 0x71, 0x61, ++ 0x33, 0xfb, 0xf5, 0x91, 0xcb, 0x55, 0x91, 0x53, 0x85, 0xe2, 0x12, 0x7c, ++ 0x56, 0xb5, 0x06, 0x38, 0x5f, 0x73, 0x43, 0x72, 0x27, 0xc8, 0x4f, 0x84, ++ 0x43, 0xa8, 0xd7, 0x2f, 0x8b, 0xa1, 0x3b, 0x0b, 0xf7, 0xa6, 0x56, 0x13, ++ 0x77, 0x93, 0x7b, 0xdc, 0xcb, 0x79, 0xde, 0xcc, 0x39, 0xdf, 0x11, 0xe5, ++ 0xd8, 0x6a, 0x6c, 0xbb, 0x54, 0xef, 0x93, 0xbc, 0x08, 0xc3, 0xe4, 0x0a, ++ 0x1b, 0x75, 0x37, 0x73, 0x10, 0xe0, 0xe5, 0xec, 0x6f, 0xed, 0x7b, 0x99, ++ 0x97, 0x3d, 0xff, 0x99, 0x36, 0xa1, 0x4e, 0xe8, 0x4d, 0x91, 0x6d, 0xe4, ++ 0x0a, 0x6c, 0xd7, 0xaa, 0x32, 0x6d, 0xfb, 0xb2, 0x70, 0x28, 0xee, 0x51, ++ 0x0c, 0x3c, 0x97, 0x9b, 0xb1, 0x19, 0x1b, 0x98, 0x93, 0x15, 0xe3, 0xb4, ++ 0x8c, 0x55, 0x72, 0x0d, 0xc1, 0x12, 0xc9, 0x37, 0xe6, 0x72, 0x78, 0x15, ++ 0xab, 0x76, 0x4a, 0xbe, 0x11, 0xc0, 0xda, 0xe4, 0xb7, 0xf0, 0x5c, 0xb3, ++ 0x1b, 0x1d, 0xcc, 0xd5, 0xae, 0x4f, 0xfa, 0xb0, 0x86, 0xf8, 0x7b, 0x43, ++ 0x92, 0x39, 0x98, 0xe6, 0xc7, 0x8d, 0x8c, 0xb5, 0x47, 0x9b, 0x99, 0x4b, ++ 0xf9, 0x4b, 0xf1, 0x01, 0xf9, 0xe2, 0x31, 0x43, 0x43, 0xc6, 0xc1, 0xce, ++ 0x1d, 0xc4, 0x4d, 0xea, 0x51, 0x95, 0x1c, 0x44, 0x74, 0xe8, 0xa2, 0x3e, ++ 0x55, 0x24, 0xce, 0xe9, 0xf0, 0x0f, 0xe5, 0x14, 0x22, 0x97, 0xe4, 0x15, ++ 0xbf, 0xb4, 0x13, 0xf3, 0xa5, 0x3e, 0x2c, 0x9f, 0x29, 0xe3, 0x50, 0x68, ++ 0xfb, 0x06, 0xfa, 0x73, 0xad, 0x78, 0x7c, 0x6a, 0xee, 0x50, 0x4f, 0xdb, ++ 0x0b, 0xf4, 0x6a, 0xbc, 0xa1, 0xeb, 0xc4, 0xff, 0xd7, 0xa0, 0xd1, 0xdf, ++ 0x87, 0x72, 0xe1, 0x9e, 0xd3, 0x8a, 0x0b, 0x2f, 0xeb, 0x55, 0x09, 0x2f, ++ 0xb1, 0x60, 0x30, 0x07, 0xf7, 0xb6, 0x65, 0x06, 0x52, 0xb9, 0xad, 0xb1, ++ 0x4a, 0x8e, 0xd7, 0xbd, 0xac, 0xc0, 0xd9, 0xbe, 0x42, 0xdd, 0x6e, 0x88, ++ 0x3a, 0x9c, 0xad, 0xc0, 0x57, 0x34, 0xdb, 0x7e, 0x53, 0x17, 0x3d, 0x03, ++ 0x87, 0x66, 0x75, 0x7c, 0x80, 0xdf, 0x87, 0x66, 0x75, 0x3c, 0xc0, 0xf6, ++ 0xe8, 0x93, 0xd8, 0xfe, 0x19, 0x9e, 0x15, 0x04, 0x73, 0x53, 0xf2, 0x2f, ++ 0xe2, 0x36, 0xb1, 0x28, 0x4e, 0x1d, 0xbf, 0x90, 0xdd, 0x22, 0x58, 0xcf, ++ 0xe9, 0x5e, 0xe5, 0x60, 0x7e, 0x5c, 0xfd, 0x3e, 0xed, 0x40, 0xf4, 0x50, ++ 0xcc, 0x91, 0x24, 0x1e, 0x8a, 0x8e, 0xeb, 0x67, 0x31, 0xbb, 0x12, 0xf1, ++ 0xba, 0xd0, 0x10, 0x51, 0xce, 0xcd, 0x72, 0x5a, 0x50, 0x75, 0x91, 0x33, ++ 0x2c, 0xc6, 0xb6, 0x4e, 0xb1, 0x9d, 0x4a, 0x27, 0xbe, 0x36, 0x37, 0xda, ++ 0xf6, 0x68, 0x34, 0x88, 0x0f, 0xf4, 0xa6, 0xce, 0x16, 0x75, 0x01, 0xe2, ++ 0x35, 0xc2, 0x23, 0x5b, 0x39, 0x77, 0x75, 0x88, 0xfb, 0xc5, 0xd6, 0xd0, ++ 0x53, 0x52, 0xc0, 0x7b, 0xd6, 0x11, 0x6e, 0xa3, 0xa1, 0xdf, 0xdf, 0xce, ++ 0xb8, 0xa7, 0xb6, 0x7b, 0x20, 0xfc, 0x4e, 0xb7, 0x9e, 0xc0, 0x7b, 0xcc, ++ 0xe1, 0x6d, 0x94, 0x44, 0x2b, 0xf0, 0xc3, 0xe6, 0x0f, 0xec, 0x78, 0x8d, ++ 0xb4, 0x6b, 0x75, 0x97, 0x70, 0xf0, 0x55, 0xe6, 0xbf, 0xdf, 0xf6, 0x4a, ++ 0x38, 0x94, 0xc8, 0x33, 0x0d, 0xd8, 0x31, 0xec, 0x45, 0x42, 0x96, 0x0a, ++ 0x20, 0xb2, 0x5c, 0x98, 0x7b, 0x15, 0xf3, 0x2e, 0x99, 0xcf, 0x01, 0x62, ++ 0xca, 0x1b, 0x36, 0xea, 0xa4, 0x7f, 0x1f, 0x65, 0x6f, 0x27, 0x97, 0x60, ++ 0xae, 0xa9, 0xfe, 0x1f, 0x2e, 0xe1, 0x42, 0x6e, 0xfd, 0xfc, 0xfd, 0xad, ++ 0xe7, 0xee, 0x8b, 0x5f, 0x7d, 0xc1, 0x2d, 0x46, 0x3f, 0x98, 0xde, 0x5f, ++ 0xb8, 0x56, 0xe7, 0x96, 0xb3, 0xed, 0x29, 0x63, 0x7a, 0x41, 0xb5, 0xc3, ++ 0x55, 0x0f, 0x2b, 0x23, 0xc4, 0x0f, 0x94, 0xb8, 0x83, 0xe4, 0xa2, 0x5a, ++ 0x80, 0x98, 0xd1, 0x4f, 0xcc, 0xb0, 0x88, 0x19, 0x8f, 0x65, 0x0f, 0x2b, ++ 0x7b, 0xb3, 0x95, 0xac, 0x23, 0x63, 0x50, 0x71, 0x72, 0xc4, 0x05, 0x7b, ++ 0xc4, 0xc1, 0xeb, 0xcf, 0xab, 0x08, 0x47, 0x6c, 0xc8, 0x5a, 0x43, 0xd1, ++ 0x6f, 0xff, 0xd9, 0x2e, 0xf8, 0xad, 0xf4, 0x23, 0x76, 0x57, 0xec, 0x4b, ++ 0xc5, 0x29, 0xa7, 0xce, 0x1d, 0xbc, 0x2e, 0x63, 0x79, 0x37, 0x4e, 0x91, ++ 0xc7, 0xbe, 0x37, 0xa2, 0xe2, 0xcd, 0x11, 0xb4, 0x52, 0x6f, 0x6d, 0x65, ++ 0x10, 0xbc, 0x0a, 0x47, 0xfa, 0x09, 0x20, 0x25, 0xba, 0x94, 0x93, 0xf2, ++ 0x73, 0xeb, 0x55, 0xf0, 0xfe, 0x91, 0x1b, 0xdc, 0x58, 0x8e, 0xc5, 0xd1, ++ 0xb6, 0x15, 0x6e, 0xca, 0xad, 0x9a, 0xf1, 0xa0, 0x17, 0x56, 0x9d, 0x8b, ++ 0x58, 0xfd, 0x76, 0x73, 0x33, 0x56, 0x30, 0x37, 0x7e, 0x9f, 0xe0, 0xb7, ++ 0x55, 0x97, 0x58, 0x61, 0xe3, 0x09, 0x43, 0xd6, 0x45, 0x6c, 0x5c, 0x1f, ++ 0xb5, 0x12, 0x44, 0x14, 0xab, 0x92, 0xb6, 0x5d, 0x4e, 0x3f, 0x19, 0x56, ++ 0xaa, 0x50, 0x61, 0xba, 0x25, 0x9e, 0x19, 0x3b, 0xc8, 0xdb, 0x82, 0x35, ++ 0x8b, 0x63, 0xb2, 0x14, 0xf4, 0x4a, 0x32, 0x1c, 0x3b, 0xa6, 0x14, 0xfc, ++ 0xf5, 0x05, 0xda, 0xde, 0x1b, 0x49, 0xbd, 0xb7, 0xd4, 0x55, 0xb8, 0x7e, ++ 0xd5, 0xc9, 0xbb, 0x8b, 0xfe, 0x1a, 0x98, 0xc5, 0x35, 0xaf, 0xf7, 0xad, ++ 0x24, 0x4e, 0x93, 0xda, 0x31, 0xff, 0xc6, 0xe9, 0x7e, 0x63, 0x5a, 0xf1, ++ 0xe8, 0x55, 0xd4, 0xa7, 0x60, 0x7d, 0x09, 0x39, 0x9b, 0xf0, 0x19, 0xaf, ++ 0xf7, 0x7d, 0x96, 0xb9, 0x21, 0x8a, 0x99, 0xc8, 0x35, 0x4d, 0x31, 0x2f, ++ 0xe2, 0x56, 0x29, 0x07, 0x56, 0x69, 0xfa, 0xbd, 0x97, 0xe7, 0xad, 0x3a, ++ 0x1f, 0xfd, 0xae, 0x82, 0x79, 0xf9, 0xe2, 0xd4, 0x5f, 0x56, 0xa1, 0xaa, ++ 0x19, 0x9b, 0x73, 0x1c, 0x59, 0xed, 0x68, 0x9d, 0x6a, 0x0a, 0x9f, 0xd5, ++ 0xe0, 0xa9, 0xdd, 0x7c, 0xad, 0x6a, 0xce, 0xa0, 0xab, 0xd5, 0xdb, 0x1e, ++ 0xcb, 0xc3, 0x5b, 0x63, 0x6e, 0x41, 0x34, 0x25, 0xf9, 0xb5, 0x60, 0x78, ++ 0x7c, 0x1b, 0x51, 0xb5, 0xae, 0xfa, 0xaa, 0xa2, 0xcd, 0x40, 0xad, 0x32, ++ 0xc5, 0x66, 0x82, 0xed, 0xaf, 0x3a, 0x58, 0xaf, 0x31, 0xdf, 0xfa, 0x59, ++ 0xe0, 0xff, 0x5f, 0xfd, 0x07, 0x9d, 0xb9, 0xf7, 0xe8, 0xf2, 0x5f, 0xd6, ++ 0x37, 0x40, 0x4a, 0xaf, 0x61, 0xeb, 0x24, 0x35, 0x3f, 0xe9, 0xd8, 0x01, ++ 0xf9, 0xc5, 0x1b, 0x5d, 0xcf, 0xd3, 0x9f, 0x3d, 0xd4, 0xfd, 0xc3, 0xba, ++ 0xc5, 0x30, 0x64, 0xdb, 0x7a, 0x34, 0x14, 0x28, 0x51, 0x82, 0x18, 0x6c, ++ 0xfe, 0x37, 0x7b, 0x86, 0x71, 0xfb, 0x6e, 0xe2, 0xad, 0x5b, 0xaf, 0x65, ++ 0x2e, 0x5a, 0x3e, 0xa7, 0x5e, 0xd7, 0xfa, 0x62, 0xbd, 0x61, 0xdd, 0x4a, ++ 0x48, 0xbd, 0x89, 0x68, 0xa8, 0x6b, 0x3b, 0xeb, 0x3d, 0xc2, 0x7a, 0xf1, ++ 0xf9, 0xac, 0x97, 0xf3, 0xb3, 0xbc, 0x8f, 0x9f, 0xaa, 0xb9, 0xfd, 0x9d, ++ 0xab, 0xf7, 0x98, 0x6e, 0x4d, 0x3b, 0xfd, 0x2d, 0x0d, 0xf5, 0x96, 0xb8, ++ 0xdc, 0x48, 0xb1, 0xde, 0x34, 0xeb, 0x9d, 0xca, 0xc9, 0xba, 0x0b, 0xae, ++ 0x9d, 0x4c, 0xa6, 0x67, 0x5c, 0xba, 0xae, 0xbd, 0x89, 0x38, 0x63, 0x82, ++ 0x33, 0x97, 0xd7, 0x1e, 0xcc, 0xf6, 0x61, 0x50, 0x3f, 0x12, 0x2d, 0x65, ++ 0xbd, 0x63, 0xfa, 0x91, 0x80, 0x87, 0x7e, 0xbf, 0x89, 0xed, 0x6d, 0x65, ++ 0x5e, 0xa8, 0xa2, 0x9e, 0x32, 0x0a, 0x9f, 0x31, 0xb0, 0x38, 0x1b, 0x28, ++ 0xf8, 0x99, 0xac, 0xf1, 0x40, 0xe6, 0x54, 0xc6, 0x17, 0x8a, 0x4c, 0x3a, ++ 0xe3, 0x53, 0x2e, 0x3a, 0xd4, 0x4c, 0xc3, 0xa8, 0xb1, 0xd0, 0xdf, 0x2c, ++ 0xf1, 0x59, 0x61, 0x6c, 0x08, 0x45, 0xa6, 0x89, 0xe1, 0xdb, 0xa7, 0x3e, ++ 0x87, 0x69, 0xad, 0x0e, 0xdb, 0x27, 0x6d, 0xfb, 0x87, 0x7a, 0x5b, 0x0d, ++ 0x69, 0x85, 0xd7, 0x4b, 0x99, 0xbd, 0xe1, 0x72, 0xe1, 0x01, 0x4e, 0x5b, ++ 0x71, 0x08, 0xfe, 0x29, 0x48, 0xe9, 0x56, 0xb7, 0xc8, 0x7f, 0x34, 0x1a, ++ 0x4a, 0x1c, 0x52, 0x9a, 0xba, 0xb6, 0xe3, 0xdf, 0x88, 0xc7, 0x20, 0x96, ++ 0x2e, 0xc4, 0x38, 0x79, 0x47, 0xbc, 0xd3, 0x62, 0x04, 0x16, 0x0e, 0xe1, ++ 0x3e, 0xbe, 0x82, 0x11, 0xd4, 0x8d, 0x50, 0x6f, 0x07, 0xcb, 0xc7, 0x0a, ++ 0xeb, 0x41, 0x38, 0x93, 0x0b, 0xd1, 0x6f, 0x44, 0x17, 0xc0, 0xb6, 0x6c, ++ 0x31, 0xd6, 0xd8, 0xf6, 0x01, 0xc3, 0xb6, 0x9f, 0x37, 0x16, 0xe2, 0x90, ++ 0x11, 0x4a, 0x88, 0x0f, 0xbc, 0x63, 0xb4, 0x5d, 0xe6, 0x41, 0xa8, 0x13, ++ 0x10, 0xd9, 0x14, 0xc6, 0x46, 0x05, 0x15, 0xfc, 0x04, 0xc2, 0xee, 0x60, ++ 0x85, 0x42, 0x2f, 0x5e, 0xda, 0xd8, 0xdb, 0x48, 0xbd, 0x57, 0x5d, 0xa3, ++ 0xe0, 0xa3, 0xcb, 0x15, 0x1c, 0xb9, 0x3c, 0x1c, 0x18, 0x57, 0x2a, 0x19, ++ 0x77, 0xc2, 0x9d, 0xed, 0x8a, 0x75, 0x9c, 0x75, 0xe3, 0xcd, 0xae, 0x50, ++ 0x80, 0x8c, 0x8d, 0xf8, 0xbd, 0x38, 0x28, 0x54, 0xc9, 0x3d, 0x1c, 0x0e, ++ 0x3c, 0xc2, 0xff, 0xae, 0x9c, 0x82, 0x9c, 0x1e, 0x8a, 0xc3, 0x69, 0x9f, ++ 0x7d, 0x47, 0x15, 0x5c, 0x11, 0xb6, 0xed, 0x13, 0xd1, 0x26, 0xed, 0x04, ++ 0xde, 0x21, 0xee, 0x4b, 0x3f, 0x45, 0xd9, 0x80, 0xf2, 0x61, 0x3d, 0xde, ++ 0xae, 0xdc, 0x21, 0xb4, 0x87, 0x71, 0x58, 0xb8, 0x42, 0x51, 0xde, 0x22, ++ 0x67, 0xb0, 0xed, 0x77, 0x8c, 0x42, 0x5b, 0x5a, 0x6b, 0x28, 0x01, 0x2c, ++ 0xc4, 0x94, 0x1e, 0xea, 0x98, 0xa6, 0x1e, 0x02, 0xf4, 0xf5, 0x05, 0x7a, ++ 0x1d, 0x66, 0x3c, 0x21, 0x6d, 0x46, 0x59, 0xf1, 0xa9, 0x8a, 0x25, 0xdd, ++ 0x8f, 0x2b, 0x4d, 0x3d, 0x65, 0xd0, 0xc9, 0x97, 0x2f, 0x92, 0xf9, 0x08, ++ 0xf8, 0x88, 0xa7, 0x9b, 0xe0, 0xf0, 0x17, 0xdc, 0x94, 0x74, 0xc7, 0xcf, ++ 0xa0, 0x81, 0x7e, 0xa7, 0x77, 0xdd, 0xab, 0x84, 0x62, 0xc0, 0x17, 0x99, ++ 0x70, 0x89, 0xac, 0x75, 0x48, 0xdc, 0x66, 0xdb, 0xf7, 0x51, 0xd6, 0x1d, ++ 0x94, 0x75, 0x73, 0xf4, 0x43, 0xfb, 0x5f, 0x9d, 0x36, 0xaf, 0xc3, 0xb8, ++ 0x7e, 0x61, 0xbb, 0x1f, 0xd8, 0x98, 0x2f, 0xed, 0x7a, 0xb0, 0x6a, 0xbe, ++ 0x6d, 0xab, 0xad, 0x82, 0xb1, 0xd7, 0x79, 0x88, 0xa9, 0x31, 0xc1, 0x6e, ++ 0xa8, 0x17, 0x72, 0x14, 0x97, 0xe4, 0x85, 0x81, 0x84, 0xa2, 0xd6, 0x57, ++ 0x30, 0x3e, 0x78, 0x75, 0x1b, 0xf7, 0x93, 0x4f, 0xc5, 0xe7, 0x57, 0xe3, ++ 0x2f, 0x38, 0xa7, 0x95, 0x61, 0xf5, 0x62, 0xa2, 0x28, 0x0e, 0x45, 0xe5, ++ 0xda, 0x83, 0xe9, 0xf9, 0x2e, 0xf4, 0x71, 0x96, 0xb5, 0xb0, 0xba, 0x40, ++ 0xee, 0x7b, 0x5b, 0xe4, 0x9a, 0xf2, 0x5f, 0xa4, 0xe0, 0x3e, 0x5a, 0xa4, ++ 0x1a, 0xde, 0x1a, 0x90, 0xfb, 0x1d, 0x86, 0x5c, 0x2b, 0x68, 0x88, 0xba, ++ 0x39, 0x2f, 0x36, 0x5c, 0x94, 0xbd, 0x3c, 0xcc, 0xfb, 0x51, 0xf9, 0x1e, ++ 0xbf, 0x8f, 0xe3, 0x8e, 0xef, 0x57, 0x04, 0xe3, 0xfe, 0xc9, 0xfe, 0x21, ++ 0x63, 0xac, 0xc6, 0xe7, 0x7f, 0xc1, 0xbe, 0x8f, 0x47, 0x9f, 0xb7, 0x17, ++ 0x30, 0x06, 0x9d, 0x88, 0x91, 0xd7, 0x5e, 0x5e, 0x8f, 0x99, 0x5b, 0x65, ++ 0xcc, 0x0a, 0x2a, 0xf5, 0xd7, 0x3d, 0xb2, 0x46, 0x50, 0xa5, 0x5f, 0x84, ++ 0x55, 0x6b, 0x0a, 0xf7, 0xca, 0xc2, 0xb2, 0x16, 0x1b, 0x44, 0xd9, 0xe5, ++ 0xb5, 0x08, 0xce, 0xde, 0x5b, 0x11, 0x76, 0x77, 0x56, 0x2a, 0xba, 0x76, ++ 0x93, 0x22, 0xcf, 0x7f, 0xcd, 0x5c, 0xc1, 0xb6, 0xef, 0xe7, 0x7c, 0x2d, ++ 0x8e, 0xfa, 0xf0, 0x31, 0xfb, 0xd9, 0x4a, 0xfd, 0xad, 0x3e, 0x37, 0x5f, ++ 0xc5, 0xfa, 0x9f, 0x30, 0x9f, 0x97, 0xba, 0xd2, 0x46, 0x63, 0xc7, 0x2a, ++ 0x65, 0x87, 0x47, 0xf2, 0xb6, 0xcd, 0x51, 0x47, 0x67, 0x2c, 0xfb, 0xcf, ++ 0xce, 0xb5, 0xd6, 0xfa, 0xc6, 0xb9, 0x75, 0xc5, 0xd3, 0x4e, 0xac, 0x6e, ++ 0xbb, 0x46, 0xc3, 0x8c, 0x5d, 0xd3, 0x62, 0x69, 0xa5, 0x10, 0xae, 0xd4, ++ 0x10, 0x79, 0x9a, 0xed, 0xfe, 0xa3, 0x51, 0x88, 0xe7, 0x07, 0x8c, 0xd0, ++ 0x88, 0x45, 0xff, 0x49, 0x30, 0xef, 0x6d, 0x17, 0x5e, 0x33, 0x75, 0x1f, ++ 0xe7, 0x61, 0x21, 0x4a, 0x5b, 0x42, 0x43, 0x8b, 0x98, 0x87, 0xba, 0x5a, ++ 0x85, 0x07, 0xc8, 0xfc, 0x38, 0x65, 0xd8, 0x57, 0x19, 0x56, 0x50, 0xc6, ++ 0x68, 0x8b, 0xc4, 0xd8, 0x3f, 0xc5, 0x83, 0xa4, 0x1d, 0x27, 0x16, 0x0f, ++ 0xc5, 0xf1, 0xe7, 0xca, 0x82, 0x11, 0x4c, 0xd6, 0x3a, 0xbd, 0xd7, 0x26, ++ 0xb2, 0x2a, 0x39, 0x58, 0x89, 0xb6, 0xb5, 0xb5, 0x8e, 0x1f, 0x79, 0xee, ++ 0xbe, 0x76, 0x43, 0xf6, 0xdc, 0x5a, 0x29, 0x46, 0x8c, 0x12, 0xa8, 0x57, ++ 0x48, 0xbc, 0xa0, 0x2f, 0x6b, 0x32, 0x3e, 0x8b, 0x56, 0x2e, 0x6b, 0xfe, ++ 0x91, 0xdb, 0x37, 0x12, 0x2f, 0x9e, 0x63, 0x8f, 0x13, 0xe4, 0x7a, 0x96, ++ 0xe3, 0x19, 0x82, 0x0d, 0x73, 0xd7, 0x4e, 0x25, 0x7e, 0x15, 0x79, 0x40, ++ 0x1d, 0x46, 0xf7, 0xac, 0x41, 0xb0, 0xae, 0x80, 0x81, 0xaa, 0xb9, 0x14, ++ 0x6d, 0x23, 0xed, 0x25, 0x85, 0x9c, 0xa5, 0x16, 0xc3, 0x7b, 0xa2, 0xc8, ++ 0xcc, 0x97, 0x67, 0x72, 0xcf, 0x0b, 0xc1, 0xe8, 0xc1, 0x3d, 0x17, 0x63, ++ 0xc6, 0x4f, 0x9f, 0x65, 0xbb, 0x09, 0xfa, 0x8e, 0xaa, 0x93, 0x97, 0x68, ++ 0xd2, 0xfe, 0x91, 0xcb, 0x88, 0x23, 0xc6, 0x4a, 0x34, 0x75, 0x1d, 0xc4, ++ 0x5b, 0xe4, 0xbc, 0x4e, 0x0e, 0x17, 0x2c, 0x35, 0xa7, 0xa9, 0x84, 0x70, ++ 0x62, 0x92, 0x38, 0xe0, 0xcb, 0x79, 0xc9, 0xdd, 0x16, 0xca, 0xda, 0xbc, ++ 0xdd, 0x46, 0x6c, 0x49, 0x90, 0xf7, 0x7f, 0xd1, 0xed, 0xc6, 0x46, 0x62, ++ 0xc6, 0x01, 0xbd, 0xa9, 0xe7, 0x20, 0xfe, 0x27, 0x71, 0x56, 0xca, 0x5f, ++ 0xc1, 0xfe, 0xa4, 0x4d, 0x2f, 0xfb, 0x93, 0xb5, 0x97, 0x37, 0xba, 0xc8, ++ 0x97, 0xdd, 0x1e, 0xfd, 0x3d, 0x8f, 0x70, 0x93, 0x12, 0xca, 0xb1, 0x63, ++ 0x8f, 0x82, 0x76, 0xb6, 0xf3, 0x08, 0x6d, 0xe6, 0xbe, 0x30, 0xdc, 0x1d, ++ 0x97, 0x93, 0xbf, 0x81, 0x2e, 0x38, 0x5f, 0xc3, 0xc3, 0x93, 0x88, 0x65, ++ 0xf5, 0xe9, 0x05, 0x3e, 0xb4, 0x39, 0x72, 0x5b, 0x8c, 0x0f, 0x85, 0x76, ++ 0xba, 0xd6, 0x7f, 0xb6, 0x9d, 0x5a, 0x3c, 0x36, 0xdb, 0xce, 0x5e, 0xb6, ++ 0x73, 0xe5, 0x62, 0xb8, 0xab, 0xae, 0x94, 0xb9, 0x6a, 0xa6, 0xff, 0xd4, ++ 0x22, 0xed, 0xc4, 0x15, 0x72, 0x8f, 0xcf, 0x43, 0xd1, 0x1b, 0x25, 0x37, ++ 0xaa, 0x2b, 0x91, 0x7a, 0x2b, 0x9b, 0xa7, 0xcf, 0xd4, 0x10, 0xb8, 0x4f, ++ 0x2f, 0x9e, 0xa6, 0xa3, 0x16, 0x75, 0x73, 0x31, 0xb6, 0xed, 0xa9, 0x2a, ++ 0xca, 0xcb, 0x7e, 0x8a, 0x7d, 0xd4, 0xf1, 0x5e, 0x00, 0x0f, 0xa7, 0x59, ++ 0x8f, 0xfd, 0x1c, 0x32, 0x84, 0xa7, 0x36, 0x19, 0x65, 0x8a, 0xac, 0x11, ++ 0x04, 0xc8, 0x29, 0xea, 0xd0, 0xef, 0xc4, 0xa1, 0x7a, 0xd6, 0xbf, 0xab, ++ 0xaa, 0xc0, 0xa9, 0xe0, 0xb9, 0x91, 0x65, 0xdb, 0xa3, 0x85, 0xfe, 0x88, ++ 0xc3, 0xcc, 0xbb, 0x5b, 0x70, 0x60, 0xe7, 0xb9, 0xe7, 0xa1, 0x95, 0xfa, ++ 0xdc, 0xf9, 0x9a, 0x0e, 0x79, 0xb0, 0x85, 0xff, 0xcb, 0x25, 0xce, 0x7c, ++ 0x66, 0xec, 0x03, 0x93, 0xbb, 0xf9, 0xbf, 0x0a, 0xdb, 0x26, 0x6d, 0x0c, ++ 0x38, 0x39, 0x54, 0x09, 0xb6, 0x36, 0xfb, 0x67, 0xb9, 0xeb, 0x7c, 0x89, ++ 0x1d, 0xb1, 0x0c, 0x24, 0xbe, 0x8a, 0xfd, 0xc4, 0x1d, 0xfb, 0x71, 0x29, ++ 0x73, 0xed, 0xa7, 0x0f, 0x2f, 0xe9, 0x47, 0xd6, 0x94, 0xe2, 0xc8, 0x7a, ++ 0xd9, 0x63, 0xe8, 0x89, 0xe2, 0xe8, 0xf5, 0xf4, 0xcd, 0x53, 0xc4, 0x9c, ++ 0x81, 0xc5, 0x8c, 0x5f, 0x0e, 0x66, 0x29, 0x28, 0xd5, 0xfd, 0xd8, 0xbe, ++ 0x27, 0x14, 0x2c, 0x21, 0x6e, 0x0d, 0x4c, 0xfe, 0xde, 0x5a, 0x1b, 0xe5, ++ 0x37, 0x70, 0x20, 0x79, 0xe4, 0x1b, 0xa5, 0xa4, 0xb9, 0xf4, 0x89, 0x9f, ++ 0xbf, 0xc5, 0x36, 0x56, 0x1a, 0x45, 0x5d, 0x89, 0x9e, 0x8a, 0xed, 0xd4, ++ 0x21, 0xb5, 0xa7, 0x58, 0x5f, 0xc1, 0xcb, 0xe1, 0xc0, 0xec, 0x1a, 0x7f, ++ 0x1d, 0x86, 0x27, 0x8f, 0x9c, 0x20, 0xcf, 0x61, 0x9c, 0x3a, 0xd2, 0x1b, ++ 0xa0, 0x2c, 0xa7, 0xa3, 0xc5, 0x39, 0x15, 0xdf, 0x9c, 0xdb, 0x86, 0xd8, ++ 0x2e, 0x94, 0xaa, 0x46, 0x0c, 0x54, 0xd1, 0x46, 0xb3, 0x61, 0x24, 0x2a, ++ 0xcc, 0x5a, 0x24, 0x27, 0xe9, 0x5b, 0xb9, 0x12, 0xb8, 0xaf, 0x92, 0xb8, ++ 0x2b, 0x5c, 0xcb, 0x7d, 0xed, 0xc9, 0x64, 0x09, 0xee, 0x32, 0xce, 0xda, ++ 0x82, 0x8b, 0x27, 0x74, 0x5c, 0x52, 0x42, 0x4c, 0x6c, 0x8c, 0x86, 0xe3, ++ 0x9b, 0x98, 0x33, 0x1f, 0x6b, 0x76, 0x5f, 0xfb, 0x6e, 0xf6, 0x37, 0x76, ++ 0xc6, 0x7f, 0xe1, 0x78, 0x44, 0x1f, 0x38, 0x7e, 0x43, 0x58, 0xfa, 0x94, ++ 0xfe, 0x8a, 0x36, 0x2a, 0xfd, 0xdb, 0x76, 0x38, 0x2a, 0x7e, 0x72, 0x7e, ++ 0x0c, 0x6f, 0xeb, 0xc5, 0x31, 0x68, 0x4e, 0xfc, 0x66, 0x8e, 0x4d, 0xcc, ++ 0x91, 0xbc, 0xe3, 0xb0, 0x72, 0xc4, 0xc9, 0xb1, 0xad, 0x38, 0x73, 0xeb, ++ 0xd8, 0xd0, 0x6c, 0x6e, 0x3d, 0x4d, 0x9e, 0x7c, 0x8c, 0x3c, 0xf9, 0x85, ++ 0xd9, 0xdc, 0xfa, 0xb9, 0xac, 0xd4, 0x99, 0x5b, 0x3e, 0xc6, 0xf2, 0xc0, ++ 0x64, 0x32, 0x1c, 0x29, 0xd6, 0x79, 0x81, 0xe5, 0x8f, 0x9d, 0x2b, 0x7f, ++ 0x27, 0xf3, 0xe1, 0x75, 0xd8, 0x9e, 0xae, 0xc0, 0x3d, 0x9a, 0x93, 0xbb, ++ 0x7a, 0x4b, 0xcd, 0x77, 0xd7, 0xbf, 0xa3, 0x4f, 0x47, 0x5c, 0xc4, 0xa1, ++ 0x49, 0x0e, 0xbe, 0x3d, 0xa9, 0xd0, 0xef, 0x3c, 0x18, 0xd2, 0xaa, 0xb1, ++ 0xd1, 0xf8, 0x37, 0xfb, 0x9e, 0x75, 0xf2, 0xac, 0xb8, 0x97, 0x22, 0xe5, ++ 0x3f, 0x64, 0xf9, 0x90, 0x31, 0x39, 0x9b, 0x6b, 0x1e, 0x49, 0x62, 0x44, ++ 0xf2, 0xb8, 0x0d, 0xad, 0xe1, 0xe0, 0x56, 0x67, 0xdd, 0x3c, 0x88, 0x4d, ++ 0xd9, 0x20, 0xee, 0xa6, 0x3c, 0x19, 0xf7, 0x6c, 0x0e, 0x56, 0x88, 0xc5, ++ 0x96, 0xf0, 0xcc, 0x15, 0x2c, 0xd7, 0x3f, 0x8b, 0x33, 0xed, 0xe7, 0x78, ++ 0x2e, 0xf3, 0x20, 0xa3, 0xc8, 0x75, 0x19, 0x0b, 0x6a, 0x25, 0x77, 0x07, ++ 0xed, 0xa2, 0x06, 0x19, 0xbf, 0xec, 0x1d, 0xcd, 0x1d, 0x23, 0xe2, 0xa5, ++ 0x66, 0x38, 0xb8, 0x58, 0x9d, 0x8b, 0x5d, 0x32, 0x56, 0xc1, 0x2d, 0xcb, ++ 0xd1, 0xcf, 0xd1, 0x73, 0xe3, 0xfd, 0x72, 0xa9, 0x60, 0xd6, 0x81, 0x64, ++ 0x9e, 0xfe, 0x02, 0xb5, 0x44, 0xec, 0x01, 0x85, 0x7b, 0xc8, 0xcb, 0xfe, ++ 0xc7, 0xdc, 0x76, 0x4b, 0xe2, 0x4c, 0x5f, 0xf0, 0x44, 0x32, 0x1c, 0x7f, ++ 0x1f, 0x96, 0x72, 0x22, 0xeb, 0xa6, 0xad, 0x4b, 0xbb, 0x03, 0x6c, 0x6f, ++ 0x48, 0x39, 0x7e, 0xae, 0xcd, 0x43, 0x67, 0x0b, 0x6b, 0xd0, 0x45, 0x5f, ++ 0xf1, 0xe2, 0xde, 0x91, 0xe2, 0x9e, 0x68, 0x1c, 0x6f, 0x1b, 0x82, 0x8b, ++ 0x5e, 0xf2, 0x1e, 0xa0, 0x33, 0xc9, 0x59, 0x70, 0xfc, 0x52, 0x3e, 0xc5, ++ 0x79, 0x7f, 0xdd, 0x2d, 0x18, 0xf6, 0x83, 0xc5, 0x9b, 0x4b, 0x0b, 0x31, ++ 0xe0, 0x4f, 0x95, 0x29, 0x62, 0xfb, 0xa1, 0xb3, 0x23, 0xe9, 0xfa, 0x39, ++ 0x79, 0x3c, 0xed, 0x6b, 0x2c, 0x34, 0x64, 0xe1, 0x3a, 0xb6, 0xe1, 0xc6, ++ 0x8f, 0x18, 0xbf, 0xdd, 0x63, 0x47, 0x2e, 0x93, 0xa5, 0x7a, 0xcf, 0xc1, ++ 0x38, 0xfa, 0x99, 0xe5, 0xb8, 0xc6, 0x3b, 0x4a, 0x0b, 0xeb, 0x8e, 0xff, ++ 0xe8, 0x2e, 0xfc, 0x17, 0x4c, 0xf6, 0x41, 0xcd, 0x4b, 0xde, 0x4e, 0x1a, ++ 0x71, 0x50, 0xf4, 0x5a, 0xcb, 0xff, 0xa2, 0x17, 0x3f, 0xff, 0x8b, 0x8e, ++ 0xea, 0xf8, 0xbf, 0x9a, 0x79, 0xab, 0xe4, 0x87, 0x5d, 0x48, 0x12, 0xb3, ++ 0x2a, 0xcc, 0x5e, 0x7c, 0x65, 0xd8, 0xb6, 0x87, 0xe8, 0x97, 0x65, 0x8c, ++ 0xf1, 0xf7, 0x87, 0x9b, 0x62, 0x4b, 0x94, 0x12, 0xf2, 0x9d, 0x2e, 0x0c, ++ 0x4d, 0x96, 0x24, 0xaa, 0xcd, 0x3a, 0xc6, 0x74, 0x0d, 0x1f, 0x2d, 0xeb, ++ 0x44, 0x3e, 0xf7, 0xc7, 0xf2, 0xca, 0xe2, 0x3c, 0x07, 0x66, 0x75, 0xe6, ++ 0x96, 0xf5, 0x99, 0x21, 0xe2, 0x0b, 0x65, 0x2a, 0xc5, 0xd6, 0x73, 0x7b, ++ 0xd5, 0x73, 0xe7, 0xb4, 0x58, 0xf7, 0x3a, 0x67, 0x1c, 0x19, 0x1c, 0x3a, ++ 0xbb, 0x3d, 0x2d, 0xe3, 0xf0, 0xe0, 0xd8, 0x88, 0x8c, 0xcd, 0xc6, 0x53, ++ 0xc6, 0x75, 0xe4, 0xaa, 0xbf, 0xb4, 0x09, 0x01, 0x8e, 0x7d, 0x79, 0xcc, ++ 0x5e, 0x65, 0x82, 0x73, 0x69, 0xb9, 0x4b, 0xc9, 0x83, 0xa0, 0x95, 0x9a, ++ 0x71, 0xe5, 0xe9, 0xac, 0xd4, 0x69, 0x57, 0x0e, 0x65, 0xe6, 0xb6, 0xdd, ++ 0xab, 0x4c, 0x66, 0x77, 0x95, 0x0a, 0x1f, 0x39, 0xaf, 0xe3, 0xe2, 0x3e, ++ 0xa3, 0xac, 0x6f, 0x06, 0x51, 0x93, 0x92, 0x26, 0x45, 0x77, 0x41, 0xb8, ++ 0xf3, 0xbc, 0xce, 0xff, 0x21, 0xd9, 0x2e, 0xf4, 0xbf, 0x65, 0x9f, 0xf1, ++ 0xd7, 0x63, 0xf4, 0xd7, 0xe9, 0x3f, 0xe9, 0xaf, 0x57, 0xfd, 0x99, 0xf2, ++ 0xb2, 0x36, 0x2c, 0xeb, 0xc2, 0xb6, 0xbd, 0xcb, 0x90, 0x35, 0x62, 0x59, ++ 0x1f, 0x6e, 0xfe, 0x03, 0xfb, 0xc7, 0xb6, 0xfd, 0xb7, 0xc6, 0x62, 0x64, ++ 0x6a, 0x43, 0x19, 0x59, 0xfb, 0x19, 0x4b, 0x03, 0x2b, 0x52, 0xd2, 0x4f, ++ 0x9c, 0xfa, 0x55, 0xaf, 0x63, 0xa4, 0x62, 0xf6, 0xd0, 0x87, 0xb7, 0x0c, ++ 0x7d, 0xef, 0x3d, 0xe4, 0xe4, 0x5b, 0x99, 0xaf, 0x1e, 0x30, 0x56, 0x13, ++ 0x0b, 0xca, 0xd1, 0xdd, 0x2c, 0x7b, 0x7e, 0xad, 0xc4, 0x04, 0xab, 0x8b, ++ 0x6e, 0xea, 0xf5, 0x99, 0x77, 0xde, 0x9e, 0x0c, 0x87, 0x3a, 0x37, 0x13, ++ 0xeb, 0x6f, 0x18, 0xf6, 0x22, 0x58, 0x58, 0x33, 0xe8, 0xf8, 0xb1, 0xea, ++ 0xe0, 0x57, 0x69, 0x61, 0x7d, 0x40, 0xd6, 0x7b, 0xa4, 0x9f, 0xd5, 0xcc, ++ 0x59, 0xa4, 0x6e, 0x10, 0x5d, 0x8d, 0x0a, 0xd2, 0x8d, 0xa1, 0x11, 0xb8, ++ 0x6c, 0xfb, 0xd7, 0xe4, 0x8c, 0xd3, 0x7e, 0x13, 0x7b, 0xa7, 0x9a, 0x22, ++ 0xbb, 0xd4, 0xff, 0x41, 0x9c, 0x2c, 0xac, 0x3b, 0x58, 0x2a, 0x65, 0xff, ++ 0xb3, 0xeb, 0xf4, 0x06, 0x64, 0x2f, 0xa5, 0x54, 0x5f, 0xa5, 0x4c, 0x3a, ++ 0xf5, 0xaa, 0x70, 0xfd, 0x58, 0xf6, 0xec, 0x63, 0x69, 0xf1, 0x01, 0xd4, ++ 0x05, 0xf4, 0x05, 0x58, 0xbc, 0xbf, 0x12, 0x37, 0x8e, 0x09, 0x8f, 0xf0, ++ 0x59, 0xa5, 0x66, 0x00, 0x4b, 0xf6, 0xd7, 0xa2, 0x7d, 0xb7, 0xec, 0xd1, ++ 0xd9, 0x7d, 0x35, 0xe6, 0x9d, 0x70, 0x1f, 0xd4, 0x70, 0xd7, 0x6e, 0xdb, ++ 0x5e, 0x74, 0x15, 0x69, 0x1f, 0xe3, 0xe5, 0xa9, 0xa5, 0xeb, 0xe0, 0xc9, ++ 0xd7, 0x63, 0x55, 0x2a, 0x82, 0x40, 0x0e, 0x78, 0x2f, 0xd9, 0xd1, 0xfe, ++ 0xf1, 0x70, 0x63, 0x77, 0xa3, 0x12, 0x32, 0x5e, 0x56, 0x62, 0x28, 0xc9, ++ 0xc7, 0xe0, 0x4a, 0x29, 0x78, 0x51, 0x47, 0x5f, 0x95, 0x69, 0xc2, 0x95, ++ 0x37, 0xe1, 0x4b, 0xb9, 0xd1, 0x4c, 0x7d, 0x57, 0x70, 0xee, 0xe7, 0xa5, ++ 0xea, 0x31, 0x2f, 0x7f, 0x09, 0x82, 0xfb, 0x9b, 0xe9, 0x3f, 0xb5, 0xec, ++ 0xcf, 0x8f, 0xf6, 0x54, 0x27, 0xe6, 0xe9, 0xad, 0xb4, 0x8d, 0x56, 0x2c, ++ 0x4c, 0xf9, 0xb1, 0x9c, 0xf3, 0xb1, 0x32, 0xd5, 0xc1, 0x7e, 0x7c, 0xe8, ++ 0x1a, 0xbb, 0x05, 0x81, 0x71, 0x2f, 0xaa, 0xc7, 0x82, 0x78, 0x6f, 0x99, ++ 0x17, 0x65, 0xe3, 0x01, 0x54, 0xa6, 0x64, 0xdf, 0x10, 0xf1, 0xcd, 0xad, ++ 0x01, 0xf8, 0xf2, 0x40, 0xc5, 0x98, 0x8d, 0xaf, 0x45, 0x73, 0xea, 0xad, ++ 0xb5, 0xb2, 0x66, 0x2f, 0x71, 0xa2, 0xfb, 0x8e, 0x01, 0xfd, 0xa1, 0x59, ++ 0x4c, 0x70, 0xd3, 0xae, 0x15, 0xb1, 0x61, 0x59, 0x57, 0xbf, 0xe3, 0x40, ++ 0x52, 0xd6, 0x4d, 0xc2, 0xf4, 0x69, 0x0f, 0xbc, 0xe3, 0xbd, 0xb3, 0xeb, ++ 0x27, 0xa2, 0x7f, 0x55, 0x96, 0xad, 0xb5, 0x4a, 0xda, 0xf9, 0xb6, 0x6c, ++ 0xbb, 0x92, 0xca, 0xf4, 0x2a, 0xc3, 0xd9, 0xeb, 0xbc, 0x28, 0x97, 0x79, ++ 0xb9, 0x1a, 0xb9, 0xe6, 0xc7, 0xec, 0x4c, 0x8d, 0x33, 0xb7, 0x96, 0x07, ++ 0x92, 0x8f, 0x0f, 0xdc, 0x1e, 0x6d, 0x0c, 0xf5, 0xd6, 0xa8, 0xc0, 0xc7, ++ 0x9c, 0xdb, 0x69, 0xa5, 0xd0, 0x97, 0xa6, 0xa7, 0xf0, 0x94, 0x5f, 0xd6, ++ 0x76, 0x65, 0xfe, 0xbb, 0xef, 0x48, 0x0e, 0x8b, 0xaf, 0x05, 0xf1, 0x21, ++ 0xed, 0xf0, 0xa6, 0x54, 0xf6, 0xec, 0xde, 0xb4, 0xac, 0x47, 0x1b, 0x78, ++ 0x91, 0xd7, 0x2b, 0x38, 0xee, 0xe7, 0xb2, 0x64, 0x11, 0xa9, 0x56, 0x67, ++ 0x9f, 0xf2, 0xc6, 0x54, 0x0c, 0x3f, 0xe4, 0xff, 0xf6, 0xd4, 0x3a, 0x1c, ++ 0xcd, 0xfa, 0x71, 0x57, 0xca, 0xc4, 0xcf, 0x99, 0xcb, 0xae, 0xa7, 0xfe, ++ 0x16, 0xd0, 0x4e, 0xbf, 0x94, 0x0a, 0xe2, 0xd5, 0x2c, 0xf0, 0xfa, 0x88, ++ 0x8d, 0x70, 0xcb, 0x37, 0xd5, 0x27, 0x1c, 0x5f, 0x6f, 0xc5, 0xeb, 0x49, ++ 0x03, 0xaf, 0x26, 0x1b, 0x8c, 0x2b, 0xd5, 0x5f, 0x61, 0xda, 0x9d, 0xa4, ++ 0x4d, 0x9d, 0x46, 0xa2, 0x56, 0xd6, 0x73, 0x0a, 0xf2, 0x6f, 0x9d, 0xf2, ++ 0x30, 0xff, 0xea, 0xc6, 0x61, 0xbf, 0xb3, 0x66, 0xf1, 0x19, 0xb9, 0x64, ++ 0xdd, 0x62, 0x05, 0xe5, 0x7a, 0x3c, 0x4d, 0x1e, 0xa9, 0xd7, 0x53, 0x1e, ++ 0x2f, 0xda, 0xc6, 0xbc, 0xa8, 0xa5, 0x6d, 0x9c, 0xdc, 0x6f, 0xe2, 0x91, ++ 0x74, 0x19, 0xda, 0x47, 0x03, 0x78, 0x8b, 0xdf, 0xb7, 0xd1, 0xc6, 0xbf, ++ 0xc7, 0xbe, 0xf5, 0xa5, 0x1a, 0xc6, 0xb4, 0x32, 0x0c, 0x45, 0xbe, 0x4f, ++ 0x2e, 0xa8, 0x32, 0x1f, 0x61, 0xde, 0xa0, 0x57, 0xe0, 0x61, 0x8d, 0xe3, ++ 0x6e, 0x0d, 0x61, 0x34, 0x42, 0x5b, 0xaf, 0x63, 0x6c, 0xd1, 0xe3, 0xa8, ++ 0x66, 0xfc, 0x4b, 0x33, 0x8f, 0x2c, 0x35, 0x2d, 0xca, 0xa0, 0x62, 0xaf, ++ 0xa6, 0xca, 0x7a, 0x20, 0x9f, 0x05, 0x70, 0x34, 0x09, 0xbb, 0xdc, 0xd4, ++ 0xcf, 0x3c, 0x82, 0xf0, 0xf1, 0x77, 0x18, 0xf3, 0x7f, 0x9a, 0xad, 0xc0, ++ 0x77, 0x46, 0x16, 0xe3, 0x47, 0x19, 0x59, 0x6b, 0xf6, 0xe1, 0xee, 0x9d, ++ 0x51, 0xb5, 0xb0, 0x4e, 0xea, 0xc3, 0xbd, 0x3b, 0x61, 0x2d, 0xa4, 0x3d, ++ 0xbe, 0x30, 0x51, 0x85, 0x0d, 0x23, 0xcf, 0xda, 0xcc, 0xab, 0x69, 0xd7, ++ 0x5e, 0x1c, 0xc9, 0x88, 0x8c, 0xd5, 0x94, 0xb1, 0x0c, 0x47, 0xf9, 0x7d, ++ 0x88, 0xb6, 0x5f, 0x3b, 0xfc, 0x20, 0x3e, 0x4d, 0x37, 0x44, 0xd6, 0xab, ++ 0x5d, 0x38, 0xe6, 0xec, 0x55, 0x37, 0xe3, 0x0d, 0xea, 0xb1, 0x7a, 0x97, ++ 0x6d, 0xff, 0x32, 0x1a, 0xc7, 0xeb, 0xd9, 0x8b, 0x51, 0xc6, 0xef, 0x46, ++ 0xb4, 0x1d, 0xaf, 0x65, 0xeb, 0x51, 0x35, 0xdc, 0x81, 0x57, 0x98, 0x0f, ++ 0x54, 0xee, 0xea, 0xc5, 0xcb, 0x6c, 0xdf, 0x37, 0xea, 0xc5, 0x4b, 0x19, ++ 0x2f, 0x5e, 0x1c, 0xd1, 0xb5, 0x8d, 0xca, 0x4f, 0x94, 0x44, 0x6d, 0xa1, ++ 0x9f, 0xb1, 0x74, 0x41, 0x9f, 0x83, 0x53, 0x25, 0x10, 0x9c, 0x3f, 0xe8, ++ 0x97, 0xb5, 0x63, 0x39, 0xe3, 0xd3, 0x7d, 0x87, 0x96, 0x9a, 0x38, 0x9b, ++ 0xa4, 0x3e, 0x5f, 0xcb, 0x05, 0x70, 0x73, 0x4a, 0x74, 0x9b, 0x3d, 0xbb, ++ 0x83, 0xd8, 0x31, 0x9c, 0x8b, 0xe1, 0x78, 0xd2, 0x23, 0x7b, 0xaa, 0x18, ++ 0xca, 0xc9, 0x5e, 0xf5, 0xb7, 0x38, 0x37, 0xc0, 0xc6, 0x5c, 0xa1, 0xad, ++ 0x81, 0xa9, 0x52, 0xea, 0xee, 0x26, 0x3c, 0xa1, 0x95, 0x48, 0x6c, 0x2e, ++ 0xd8, 0xa8, 0x7e, 0x33, 0x6d, 0xf7, 0x5b, 0xce, 0xfa, 0xe0, 0x58, 0xba, ++ 0x49, 0x9b, 0x87, 0xe2, 0x3c, 0x36, 0x60, 0xa1, 0xfe, 0x1b, 0xfb, 0x59, ++ 0xbf, 0xac, 0xf9, 0x0a, 0x97, 0xec, 0xbe, 0x63, 0x63, 0x52, 0xfa, 0x09, ++ 0xa2, 0x3f, 0x77, 0xe8, 0xec, 0x68, 0xda, 0x4d, 0xbf, 0x24, 0x67, 0x08, ++ 0xfb, 0xb1, 0xb2, 0x31, 0x82, 0xc6, 0xbc, 0xac, 0x27, 0x7f, 0xa5, 0x4a, ++ 0xce, 0x5e, 0xf4, 0x84, 0x9d, 0xb5, 0x3d, 0xc6, 0xc5, 0xe2, 0x3d, 0x2f, ++ 0x4e, 0xfd, 0x9e, 0xaf, 0x00, 0x8b, 0xc6, 0x3a, 0xd9, 0xaf, 0x8d, 0x1b, ++ 0x8d, 0x7f, 0xb5, 0xdb, 0x6f, 0x93, 0xfe, 0x6f, 0xaf, 0x2a, 0x3c, 0x5b, ++ 0x51, 0x26, 0x6b, 0x92, 0x63, 0xe9, 0xa5, 0xf4, 0xa5, 0x16, 0x1c, 0xf2, ++ 0x0b, 0x07, 0x11, 0x3f, 0xe8, 0xbe, 0x23, 0x4a, 0xfb, 0x79, 0x98, 0x32, ++ 0xac, 0xa1, 0xed, 0xdc, 0x48, 0x5c, 0xa8, 0xd6, 0x0f, 0x9d, 0x1d, 0x4e, ++ 0x1b, 0x58, 0x92, 0xf3, 0xd1, 0x96, 0x65, 0xdd, 0xb0, 0x15, 0x7a, 0x8e, ++ 0x38, 0x42, 0xfb, 0x5e, 0x9e, 0xf3, 0xd3, 0x9e, 0x83, 0xb8, 0x26, 0x27, ++ 0x3e, 0xae, 0x23, 0xcc, 0x38, 0xd7, 0xc5, 0x3a, 0xb1, 0x5c, 0x0d, 0xae, ++ 0xdc, 0xe7, 0xc6, 0x2d, 0xa9, 0x28, 0xf5, 0x13, 0x61, 0xfc, 0x3b, 0xaf, ++ 0xef, 0xed, 0x53, 0x8b, 0x50, 0xa3, 0x1f, 0xb6, 0x9f, 0x76, 0x30, 0xac, ++ 0xd4, 0xd1, 0x53, 0x80, 0xfd, 0x06, 0xd2, 0xb0, 0xaa, 0x19, 0x5f, 0xce, ++ 0xe4, 0x9e, 0xfe, 0x5d, 0xe2, 0x76, 0xd1, 0xe5, 0xdc, 0xf1, 0x08, 0xa6, ++ 0x1c, 0x3a, 0x2b, 0x7b, 0xb3, 0x2d, 0x8f, 0xda, 0x58, 0xd9, 0xb2, 0x59, ++ 0xf9, 0xae, 0x63, 0x4b, 0xd2, 0xae, 0xf0, 0x8a, 0xa2, 0xfe, 0x8b, 0x3a, ++ 0xff, 0xdc, 0xac, 0xce, 0x8b, 0xe3, 0x0c, 0xed, 0x15, 0x9c, 0xbe, 0xbb, ++ 0xa5, 0x88, 0xd3, 0x52, 0x5e, 0xee, 0xaf, 0xb1, 0x87, 0x35, 0xb8, 0x4b, ++ 0x75, 0x17, 0x06, 0x23, 0x4f, 0x2a, 0x33, 0x9a, 0xf8, 0xbc, 0x6c, 0x79, ++ 0xdd, 0x64, 0xd3, 0x6d, 0x69, 0xd7, 0x9f, 0xb2, 0x1c, 0x94, 0xd2, 0x73, ++ 0x73, 0x29, 0xdc, 0x64, 0xeb, 0xec, 0x5c, 0x0a, 0x27, 0x2e, 0x8e, 0xa9, ++ 0x28, 0x6b, 0x8c, 0xbc, 0x4f, 0xe4, 0x15, 0xdb, 0x90, 0x32, 0x8f, 0x95, ++ 0x15, 0xd6, 0x50, 0xb7, 0xce, 0xb1, 0x87, 0x22, 0xbf, 0x71, 0xda, 0xd0, ++ 0x70, 0xce, 0x1e, 0xdc, 0xe8, 0x4c, 0xc9, 0xbc, 0xc3, 0x2a, 0xa7, 0x1e, ++ 0x3a, 0x73, 0x1e, 0xce, 0x9f, 0xf0, 0x74, 0x15, 0xab, 0x8c, 0x41, 0x65, ++ 0xda, 0xff, 0x08, 0xdb, 0xc8, 0x9e, 0x65, 0x1d, 0xde, 0x1b, 0xe6, 0xf7, ++ 0x4b, 0x70, 0x13, 0x71, 0x74, 0x63, 0xd4, 0x52, 0x0a, 0x67, 0x2e, 0xca, ++ 0x70, 0xf9, 0x58, 0x2d, 0x7c, 0xba, 0xac, 0x69, 0xfc, 0x5f, 0x8a, 0xaf, ++ 0x46, 0xc6, 0x5f, 0xe0, 0x08, 0x50, 0x2f, 0xc1, 0xca, 0x31, 0x86, 0x6c, ++ 0x67, 0x7f, 0xa2, 0x0d, 0x4f, 0xb4, 0x5e, 0x82, 0x1b, 0x1c, 0x1e, 0x14, ++ 0xc6, 0x15, 0xe3, 0x82, 0xa1, 0xbd, 0xca, 0x28, 0xb1, 0x93, 0xc9, 0x08, ++ 0xfd, 0x3a, 0xae, 0x8c, 0x10, 0x33, 0xf7, 0x3a, 0x3e, 0x02, 0xad, 0x9a, ++ 0xcf, 0xd2, 0xd9, 0x76, 0x8e, 0x43, 0x6c, 0xf7, 0xbc, 0x8c, 0x0b, 0x29, ++ 0xe3, 0x69, 0x62, 0xd1, 0x35, 0xb3, 0x32, 0x2e, 0x5e, 0x2a, 0x79, 0xae, ++ 0xc8, 0x58, 0x86, 0x46, 0xca, 0x51, 0x4b, 0x39, 0x8e, 0x1a, 0x35, 0xca, ++ 0x98, 0x56, 0x90, 0xad, 0x81, 0xfd, 0x33, 0xe6, 0x60, 0x83, 0xe1, 0x53, ++ 0x6e, 0x74, 0xee, 0x15, 0x65, 0xcb, 0x9e, 0x1d, 0x4a, 0xff, 0xce, 0xf6, ++ 0xe9, 0x05, 0x39, 0xab, 0x46, 0x83, 0x78, 0x79, 0xd9, 0x25, 0xa8, 0xdc, ++ 0x57, 0x86, 0x16, 0xe2, 0x7a, 0xd3, 0x98, 0x3e, 0xb2, 0x59, 0x11, 0x59, ++ 0x3d, 0xbc, 0x76, 0xd6, 0x14, 0xa8, 0xcf, 0x32, 0xef, 0x67, 0xed, 0xd8, ++ 0x8d, 0x35, 0xa9, 0x82, 0x0d, 0x3b, 0xfe, 0xdb, 0x28, 0xf6, 0x2b, 0xeb, ++ 0x87, 0xb4, 0xe7, 0xac, 0x0b, 0xab, 0xd8, 0xf7, 0x51, 0xe3, 0x3e, 0xc5, ++ 0xd2, 0x0e, 0x9d, 0x95, 0xb3, 0x05, 0x2a, 0x65, 0xdc, 0x9a, 0xb9, 0x04, ++ 0x37, 0x8f, 0x4d, 0xdb, 0x5e, 0x7d, 0xb9, 0xec, 0x45, 0x76, 0x0d, 0x29, ++ 0x5e, 0xec, 0xc8, 0xb8, 0xb0, 0x62, 0x8c, 0x5c, 0xce, 0x48, 0x28, 0xb2, ++ 0xee, 0x29, 0x7c, 0xb5, 0x2d, 0xc5, 0x5c, 0x35, 0x2f, 0xb9, 0x63, 0xcf, ++ 0x1d, 0x6d, 0xc9, 0xbb, 0x94, 0xb8, 0x96, 0x3d, 0x9b, 0x4a, 0x1f, 0xf9, ++ 0x96, 0x4a, 0xde, 0xb5, 0x8d, 0xb8, 0xf6, 0xda, 0x01, 0x1f, 0x7d, 0x41, ++ 0xa1, 0x9f, 0xf8, 0xe9, 0xfb, 0xcd, 0xf8, 0x39, 0x7d, 0x63, 0x3d, 0xe3, ++ 0xe2, 0x4f, 0x73, 0x75, 0xb8, 0x7e, 0xb7, 0x89, 0x17, 0x0e, 0xf8, 0xd1, ++ 0xb5, 0xfb, 0x3a, 0xbc, 0xc1, 0x72, 0x53, 0x8c, 0x07, 0x53, 0x13, 0xb5, ++ 0xfc, 0xf8, 0xf9, 0xa9, 0xe3, 0x67, 0x23, 0xf1, 0xa8, 0x06, 0x27, 0xf6, ++ 0xb9, 0xd0, 0x3e, 0xa6, 0x62, 0xcc, 0x50, 0x70, 0xeb, 0x15, 0x32, 0x1e, ++ 0x2f, 0x36, 0x34, 0x9e, 0xb7, 0x8b, 0x55, 0x29, 0xe1, 0x70, 0x5e, 0x4b, ++ 0xce, 0x54, 0x1c, 0xa4, 0x5f, 0x5e, 0x4f, 0x0e, 0xf6, 0xf0, 0x48, 0x27, ++ 0xfd, 0xc8, 0xc6, 0xa2, 0xe8, 0xf7, 0xb1, 0x46, 0x1b, 0x92, 0x9c, 0xd7, ++ 0xd9, 0x43, 0x48, 0x73, 0x1e, 0x67, 0x3c, 0x4d, 0xd6, 0x3c, 0x94, 0xc5, ++ 0x03, 0x66, 0x58, 0x3b, 0x8c, 0xd5, 0x18, 0x99, 0x82, 0xa6, 0x91, 0x47, ++ 0x6d, 0x27, 0x8f, 0x1a, 0x24, 0x8f, 0xda, 0x9a, 0x3d, 0xcc, 0x39, 0x5e, ++ 0xce, 0xf6, 0x25, 0x06, 0xba, 0xe9, 0xbb, 0xc2, 0x89, 0xbc, 0x56, 0x19, ++ 0xdb, 0x3f, 0xc6, 0x98, 0xb4, 0x7c, 0xb4, 0x80, 0x1b, 0x9f, 0x2e, 0x7d, ++ 0x06, 0xfa, 0xbc, 0x21, 0xfa, 0x7c, 0xa1, 0xed, 0x47, 0x84, 0x9b, 0x79, ++ 0xaa, 0xe2, 0x55, 0x66, 0xb8, 0xfb, 0x15, 0x72, 0x33, 0x2f, 0xdb, 0xdc, ++ 0x36, 0xbb, 0x47, 0x31, 0xcc, 0x36, 0x87, 0x58, 0xb7, 0x69, 0xd4, 0xe2, ++ 0x5c, 0xba, 0x59, 0x3f, 0x1c, 0xd8, 0xac, 0x18, 0xac, 0xeb, 0xe4, 0x18, ++ 0x68, 0xd8, 0x77, 0x7e, 0xae, 0x3a, 0x89, 0x31, 0xa3, 0xb3, 0xfe, 0x7e, ++ 0x3a, 0x77, 0x09, 0xc2, 0x34, 0x92, 0x27, 0x8c, 0x2d, 0x08, 0xd2, 0x66, ++ 0x5d, 0xb3, 0x7d, 0x0d, 0xca, 0x38, 0xdc, 0x0b, 0xe3, 0x0b, 0xd9, 0xc7, ++ 0x48, 0x36, 0xac, 0xf5, 0xa1, 0xe9, 0xf8, 0x3c, 0xc8, 0x38, 0xa4, 0xbf, ++ 0xd5, 0x78, 0x6c, 0xea, 0xc2, 0x71, 0xd4, 0x13, 0x9f, 0x2e, 0x9b, 0xf5, ++ 0xad, 0x7f, 0x77, 0xf2, 0xf4, 0xb8, 0xe3, 0x63, 0x0f, 0x3b, 0xf2, 0x7b, ++ 0xd8, 0x66, 0x9e, 0x6d, 0x4e, 0x3b, 0xe7, 0x4d, 0x2d, 0xf2, 0xdc, 0x7a, ++ 0xca, 0xa1, 0xc4, 0x6b, 0xcc, 0xa6, 0xde, 0x79, 0x08, 0xc7, 0x5e, 0x67, ++ 0xdb, 0xf3, 0xd8, 0xf6, 0x53, 0x6c, 0x3b, 0xcd, 0xb6, 0x27, 0xd9, 0xf6, ++ 0x77, 0xcf, 0xb5, 0xad, 0x62, 0xfd, 0xee, 0xa2, 0x6d, 0xb9, 0x11, 0x5b, ++ 0xca, 0x8c, 0x70, 0x9e, 0xec, 0xbf, 0xd6, 0x73, 0xee, 0x45, 0x77, 0x41, ++ 0xc6, 0xf6, 0x82, 0xbd, 0x2d, 0x67, 0xec, 0xf9, 0xd2, 0x6e, 0x05, 0xef, ++ 0x44, 0xdf, 0xc1, 0x8c, 0xbf, 0xc0, 0x23, 0x8a, 0x36, 0xa4, 0xd1, 0x86, ++ 0xb4, 0xd4, 0x3f, 0xcb, 0x52, 0x11, 0xeb, 0x88, 0xfd, 0xc8, 0xde, 0x04, ++ 0xf9, 0x73, 0x52, 0xf4, 0x31, 0x41, 0xdc, 0x0d, 0x1f, 0x7f, 0x9b, 0xb1, ++ 0xf3, 0x7b, 0x59, 0x0f, 0x32, 0x19, 0x1f, 0x9e, 0xca, 0x0a, 0x36, 0xf6, ++ 0x10, 0x1b, 0x05, 0xef, 0xc9, 0x03, 0x27, 0x8e, 0x7c, 0x23, 0xc0, 0xca, ++ 0x4f, 0xd1, 0x7e, 0x9e, 0xa2, 0xfd, 0x3c, 0x35, 0xe1, 0xc3, 0x95, 0x07, ++ 0xbd, 0xf8, 0x98, 0x58, 0x33, 0xcc, 0x32, 0xc9, 0x74, 0x33, 0xae, 0x20, ++ 0xcf, 0x3a, 0x34, 0xcc, 0xb8, 0xcc, 0xf8, 0x1f, 0xc9, 0x6b, 0xd8, 0x31, ++ 0x5a, 0x83, 0xa6, 0x71, 0x89, 0xc1, 0x35, 0xb8, 0x7f, 0xc4, 0x8b, 0x25, ++ 0xfb, 0x64, 0x0f, 0x94, 0xbc, 0x70, 0xe4, 0x16, 0x4c, 0x38, 0x3e, 0x3e, ++ 0x8f, 0xfe, 0x51, 0x8b, 0xc6, 0x71, 0xf9, 0x4e, 0x9e, 0x42, 0x9b, 0x5d, ++ 0x7e, 0xb0, 0x8e, 0xe3, 0xbd, 0x0e, 0xd7, 0x1c, 0x0c, 0x10, 0xcf, 0xfd, ++ 0x88, 0xe5, 0x57, 0x9f, 0x15, 0x4c, 0x1e, 0x9c, 0x9a, 0x1b, 0xd3, 0xc4, ++ 0x0f, 0x1d, 0x0c, 0x8b, 0x15, 0x31, 0xec, 0xfc, 0xf3, 0xb9, 0x38, 0xd9, ++ 0x28, 0x18, 0xc8, 0x32, 0xc5, 0xd8, 0x33, 0x17, 0x17, 0xcf, 0xe3, 0x53, ++ 0xcb, 0x98, 0xfc, 0xd7, 0xd0, 0x75, 0x95, 0xf8, 0xfa, 0x25, 0x88, 0x39, ++ 0xf2, 0x24, 0xcb, 0x59, 0x2e, 0x50, 0xf0, 0xf7, 0xb9, 0x78, 0xee, 0x9b, ++ 0xf5, 0x53, 0x17, 0xe2, 0x35, 0x05, 0x2e, 0x7c, 0xd3, 0xee, 0x66, 0xec, ++ 0xa0, 0x3e, 0x3a, 0xe8, 0x47, 0xbe, 0xa8, 0x69, 0x5b, 0x35, 0x92, 0xd3, ++ 0xd6, 0xe2, 0x96, 0xdd, 0x7e, 0xc6, 0xf0, 0x8b, 0x91, 0x9a, 0xb8, 0x83, ++ 0x6d, 0xd5, 0x63, 0x78, 0x36, 0xd7, 0x1f, 0x4c, 0xdf, 0x68, 0xdf, 0xeb, ++ 0x9c, 0x07, 0x90, 0x7d, 0x81, 0x0f, 0xd7, 0x7b, 0xc3, 0xd3, 0x41, 0xe6, ++ 0xfa, 0x06, 0x73, 0x0e, 0x72, 0xb0, 0xe3, 0x08, 0xd7, 0x32, 0x77, 0xd7, ++ 0xab, 0xb1, 0x82, 0xb9, 0xfe, 0xbd, 0x7e, 0x79, 0xf6, 0x80, 0xc8, 0xe2, ++ 0x94, 0x3f, 0x3f, 0xc6, 0x1d, 0x73, 0xc6, 0xd8, 0x14, 0x9b, 0x87, 0x22, ++ 0x1f, 0xfb, 0x9d, 0xfd, 0x53, 0x1d, 0xca, 0x68, 0x98, 0x56, 0xdb, 0x12, ++ 0x1a, 0xb9, 0x57, 0xd1, 0xb5, 0xa5, 0x2a, 0xa1, 0x2b, 0xf7, 0x1a, 0x56, ++ 0xe5, 0x7f, 0x8c, 0x78, 0x9e, 0x0e, 0x4e, 0x59, 0xd6, 0xe7, 0xd7, 0x61, ++ 0x3a, 0x2b, 0xe7, 0x3b, 0xba, 0xef, 0xb8, 0x6c, 0xd8, 0x47, 0x1b, 0x85, ++ 0x72, 0xa8, 0x35, 0x82, 0xf7, 0xc8, 0x73, 0x3a, 0x53, 0xaf, 0x41, 0x63, ++ 0x7c, 0xbd, 0x25, 0xf5, 0x63, 0x54, 0x11, 0x53, 0x6e, 0x4e, 0xfd, 0xce, ++ 0x9e, 0x0c, 0xbf, 0xe8, 0xd4, 0x2b, 0xcd, 0xed, 0x3f, 0x3b, 0x72, 0x3e, ++ 0x3e, 0x69, 0xa5, 0xfa, 0xd9, 0xd2, 0xcf, 0xe2, 0x61, 0x73, 0x7b, 0x7f, ++ 0x32, 0xf7, 0x2f, 0x1e, 0xf3, 0x17, 0x7f, 0xff, 0x9d, 0xd6, 0x82, 0x5d, ++ 0x06, 0xb3, 0x5f, 0xc2, 0xd7, 0x1c, 0xdc, 0xdd, 0xb0, 0xd9, 0x6d, 0xf6, ++ 0x7c, 0x43, 0xd6, 0x49, 0x37, 0x38, 0x6b, 0x08, 0x5d, 0x78, 0x64, 0x4f, ++ 0x27, 0xfa, 0xf7, 0x08, 0xb6, 0x36, 0x75, 0xac, 0x50, 0x16, 0xd0, 0x0f, ++ 0xc7, 0x9c, 0x5c, 0xc6, 0xad, 0x5f, 0xea, 0xac, 0x0f, 0x78, 0x9c, 0xfd, ++ 0xb1, 0x20, 0x36, 0xe4, 0x0a, 0x6d, 0x2d, 0xca, 0x56, 0xd2, 0xbf, 0x4c, ++ 0xa4, 0x98, 0xb3, 0xf8, 0x18, 0x3b, 0xdd, 0xcc, 0x73, 0x5f, 0x1e, 0x95, ++ 0xb8, 0xa3, 0xc0, 0x77, 0x9b, 0xec, 0x85, 0xae, 0x46, 0x91, 0xaf, 0xc7, ++ 0xb5, 0x7e, 0x5e, 0x7f, 0xbf, 0xbc, 0x20, 0x57, 0xff, 0x05, 0xbc, 0xa8, ++ 0x68, 0x0f, 0xa2, 0xbb, 0xa2, 0x0d, 0x85, 0x59, 0x96, 0xf9, 0x37, 0xf9, ++ 0xe0, 0x79, 0x7f, 0x8e, 0x96, 0x3b, 0x6b, 0x86, 0xf9, 0xb9, 0xf1, 0x7d, ++ 0x70, 0x56, 0xf7, 0xb7, 0x94, 0x17, 0x63, 0x53, 0x41, 0x5e, 0x83, 0x58, ++ 0x78, 0x11, 0xe2, 0xfe, 0xa2, 0xff, 0xef, 0xe3, 0xf3, 0x7e, 0xc1, 0x80, ++ 0xd9, 0xba, 0xdb, 0x2b, 0x50, 0x3e, 0xe8, 0x70, 0xb8, 0xf3, 0xed, 0x1f, ++ 0xb9, 0xa0, 0xfd, 0xb9, 0xf6, 0x2b, 0xed, 0x4b, 0x9c, 0x16, 0x9d, 0xde, ++ 0xcd, 0xba, 0xa2, 0x3f, 0x07, 0xa3, 0x65, 0xbd, 0x96, 0xdc, 0xad, 0xd3, ++ 0xd9, 0xc3, 0x29, 0x27, 0x6f, 0xde, 0xca, 0x1c, 0xaa, 0x62, 0x1f, 0xbf, ++ 0x93, 0xfb, 0xdc, 0x30, 0x16, 0x40, 0xd9, 0x3e, 0x0f, 0x71, 0x7d, 0x01, ++ 0xdc, 0xfb, 0x4a, 0x68, 0xaf, 0xc2, 0x11, 0x3e, 0x5c, 0x3f, 0xa0, 0x5f, ++ 0x0c, 0xd7, 0xbe, 0x52, 0xf2, 0x72, 0xe1, 0x7c, 0xef, 0xae, 0xdf, 0xc8, ++ 0x38, 0xae, 0xee, 0xf3, 0x32, 0x3e, 0xd7, 0xc3, 0xc3, 0x98, 0xb7, 0x6a, ++ 0xec, 0x73, 0x28, 0xa1, 0xc8, 0x77, 0x8d, 0x5d, 0x8a, 0x85, 0xfb, 0x2a, ++ 0xb0, 0x7e, 0x6c, 0x21, 0x16, 0xec, 0x93, 0xdc, 0x29, 0x88, 0xc0, 0xbe, ++ 0x4a, 0xac, 0x19, 0x0b, 0xa1, 0x66, 0x5f, 0x15, 0x3a, 0xc7, 0x16, 0x41, ++ 0xdb, 0x57, 0x8d, 0x2f, 0x8d, 0x35, 0xa0, 0x7a, 0x9f, 0x86, 0x5b, 0xc6, ++ 0x74, 0x54, 0xed, 0xab, 0x61, 0x4c, 0x0b, 0x33, 0x76, 0xfa, 0xb1, 0x7a, ++ 0x37, 0xe7, 0xe6, 0x40, 0x1d, 0xfd, 0x62, 0x1d, 0x39, 0xf5, 0x9d, 0xd8, ++ 0x9b, 0x5e, 0x82, 0x8a, 0x03, 0x01, 0xdc, 0xb0, 0x7b, 0x5a, 0x23, 0xa5, ++ 0xc1, 0xca, 0x70, 0x33, 0xca, 0x0e, 0x48, 0xee, 0x17, 0x3a, 0xde, 0x8e, ++ 0xd0, 0x99, 0x15, 0xa8, 0x66, 0xee, 0x0b, 0xbc, 0x3d, 0x05, 0x2c, 0x9e, ++ 0x72, 0xe1, 0xb0, 0xb6, 0x0e, 0xdb, 0xa6, 0xf6, 0xcd, 0xda, 0xbc, 0xec, ++ 0x2d, 0x55, 0x73, 0x7e, 0xe5, 0xbb, 0xdc, 0xbb, 0x13, 0x43, 0x53, 0xc5, ++ 0x35, 0xb2, 0xd0, 0xc8, 0x20, 0x35, 0x38, 0x9d, 0x95, 0x67, 0xe2, 0x23, ++ 0xa0, 0x7d, 0x2b, 0x5b, 0xe5, 0x0c, 0xbc, 0xcb, 0x54, 0xab, 0xb6, 0xb6, ++ 0x76, 0x5f, 0x9b, 0xc8, 0x6e, 0x61, 0xde, 0x25, 0x39, 0xec, 0xe6, 0x6b, ++ 0x37, 0x64, 0xdf, 0x3d, 0xb7, 0xd7, 0x30, 0x62, 0xb4, 0x05, 0x34, 0x7c, ++ 0x11, 0x1b, 0x9c, 0xf5, 0x55, 0x95, 0x73, 0x26, 0xe7, 0x76, 0x9c, 0xf3, ++ 0xf0, 0xb4, 0xb3, 0x04, 0x0c, 0x07, 0x53, 0x37, 0xa1, 0x21, 0xeb, 0xac, ++ 0xe3, 0x46, 0x12, 0x78, 0x56, 0xed, 0xd0, 0xad, 0xd9, 0x73, 0x27, 0xd6, ++ 0x35, 0x1a, 0xe2, 0x86, 0x76, 0xee, 0x6c, 0x4a, 0x28, 0x38, 0x89, 0x50, ++ 0x60, 0x3b, 0x36, 0xa1, 0xdf, 0x39, 0x97, 0xd5, 0x25, 0xe7, 0xa2, 0xf8, ++ 0xff, 0x4e, 0xe8, 0xe7, 0xce, 0xd7, 0xca, 0xf9, 0x71, 0xd9, 0xe3, 0xb2, ++ 0x99, 0xf3, 0x4b, 0x9e, 0x7c, 0x58, 0x51, 0x87, 0x9d, 0xb5, 0xb3, 0x75, ++ 0x2e, 0xc6, 0x80, 0x76, 0x05, 0x89, 0x32, 0x33, 0x1c, 0x7c, 0x6f, 0x76, ++ 0xdd, 0xc1, 0x93, 0x1b, 0x50, 0x4a, 0x72, 0x43, 0x8a, 0x3b, 0x57, 0x58, ++ 0x77, 0x70, 0x91, 0xc7, 0x6e, 0x4f, 0xd7, 0xb2, 0x8c, 0x86, 0xc5, 0xcb, ++ 0xdc, 0x78, 0x31, 0x59, 0x95, 0xf0, 0xf1, 0xfb, 0xb6, 0x65, 0x25, 0xb8, ++ 0x9f, 0xb6, 0xdf, 0x71, 0xf9, 0x51, 0xbc, 0x9b, 0x25, 0xd7, 0x48, 0x5a, ++ 0xd1, 0x09, 0xf6, 0x79, 0x24, 0xa9, 0xe2, 0xb9, 0x9d, 0x03, 0xd1, 0x71, ++ 0xa7, 0xff, 0x07, 0xd1, 0x3f, 0x29, 0x79, 0x57, 0xab, 0x3d, 0x98, 0x36, ++ 0x6d, 0x89, 0xbb, 0xf9, 0x64, 0x2d, 0x73, 0x73, 0x0d, 0xef, 0x2e, 0xeb, ++ 0xc6, 0xc7, 0x2c, 0x93, 0x4b, 0x6e, 0xc6, 0x47, 0xe4, 0x08, 0xd9, 0xe4, ++ 0x6a, 0xbc, 0xc4, 0x5c, 0xf2, 0xdb, 0xc9, 0x0e, 0xe6, 0x96, 0xeb, 0xf0, ++ 0xc3, 0x9d, 0xce, 0x7b, 0x0a, 0x68, 0x4b, 0x2a, 0xb8, 0x21, 0xbc, 0x0e, ++ 0x27, 0x26, 0x98, 0x53, 0xee, 0x94, 0xb3, 0xc0, 0x17, 0xcd, 0x9e, 0x49, ++ 0x94, 0xe7, 0x71, 0x3e, 0x5f, 0x8b, 0x23, 0x13, 0x01, 0xec, 0x67, 0x0e, ++ 0xf9, 0x26, 0x31, 0x64, 0x3c, 0xd9, 0x8c, 0x93, 0xcc, 0x95, 0xbe, 0x97, ++ 0x8c, 0xe1, 0x53, 0x5e, 0x1f, 0x4e, 0xca, 0xda, 0x78, 0x2b, 0xce, 0x64, ++ 0xbf, 0x8f, 0x92, 0xe1, 0x05, 0x38, 0xd6, 0xf9, 0x0c, 0xa9, 0xe4, 0x61, ++ 0x7e, 0x3a, 0x70, 0x72, 0xa2, 0x03, 0x6f, 0xed, 0xbc, 0x11, 0x6f, 0x4d, ++ 0xfc, 0x0c, 0xef, 0xee, 0x14, 0x79, 0x6d, 0x5b, 0x8d, 0x4a, 0xbb, 0x3a, ++ 0xdb, 0x25, 0x4e, 0x4d, 0xfc, 0xef, 0xb4, 0xfd, 0x81, 0x7d, 0x6c, 0x9d, ++ 0xb4, 0xfb, 0xcc, 0x9f, 0x68, 0x5b, 0x74, 0x29, 0xb1, 0xde, 0x8b, 0x13, ++ 0x49, 0x2f, 0xf3, 0xaa, 0xe9, 0xcb, 0xca, 0x30, 0x7d, 0x0d, 0xb3, 0x4d, ++ 0x0c, 0x66, 0x4b, 0xf1, 0xdc, 0x88, 0x9b, 0x5c, 0xf1, 0xf3, 0xc4, 0x8f, ++ 0x5e, 0xda, 0x61, 0x29, 0xf3, 0x37, 0x2f, 0x75, 0x7c, 0x0d, 0xf1, 0x3e, ++ 0x46, 0xfd, 0xf9, 0xf0, 0x72, 0xd2, 0x8f, 0x57, 0x92, 0x4d, 0x89, 0xbc, ++ 0xd2, 0x02, 0xab, 0xa6, 0x90, 0x57, 0x1e, 0x49, 0xf6, 0x38, 0x32, 0xbd, ++ 0x98, 0x6c, 0xb5, 0xb7, 0x51, 0xc7, 0x43, 0xe9, 0x07, 0xf1, 0x01, 0xf5, ++ 0xf9, 0xc3, 0xe4, 0x19, 0x5b, 0xd5, 0x8f, 0xe3, 0x49, 0xea, 0xf4, 0x44, ++ 0x32, 0x81, 0x32, 0xe6, 0x29, 0x47, 0x93, 0xd3, 0x98, 0xa0, 0x5d, 0xbe, ++ 0x39, 0xa2, 0x1f, 0xdf, 0x80, 0x2d, 0xf8, 0x34, 0x53, 0x8a, 0x37, 0xd8, ++ 0x47, 0xf5, 0x52, 0x37, 0x66, 0x9c, 0xf6, 0xb6, 0xe0, 0xa3, 0x11, 0x05, ++ 0xd9, 0x65, 0x5b, 0xf0, 0x21, 0x9f, 0xbd, 0xca, 0xef, 0x1f, 0x47, 0x29, ++ 0xe1, 0xec, 0xb3, 0xb7, 0x46, 0x54, 0x27, 0x07, 0xde, 0xda, 0xba, 0x05, ++ 0x27, 0x33, 0x1f, 0x62, 0x3f, 0x73, 0xe9, 0x6f, 0x18, 0xf3, 0x10, 0x9b, ++ 0x47, 0xc0, 0xd5, 0x4b, 0x71, 0x82, 0xcf, 0x1b, 0x65, 0xbd, 0x47, 0x2b, ++ 0x94, 0xff, 0x80, 0xe3, 0xb9, 0x9f, 0x6d, 0xbd, 0x9f, 0xf9, 0x26, 0xdb, ++ 0x15, 0xce, 0xf9, 0x4d, 0xb6, 0xfb, 0x33, 0x4c, 0xce, 0xea, 0xe3, 0xa4, ++ 0x21, 0xe3, 0xfa, 0x6f, 0x3e, 0x94, 0xfb, 0x39, 0x8e, 0xbf, 0xe2, 0xff, ++ 0x1e, 0xcc, 0x64, 0x7f, 0xc0, 0xff, 0x2f, 0xe1, 0x50, 0x56, 0x62, 0x7b, ++ 0xf1, 0xdc, 0x92, 0xac, 0x6f, 0x89, 0xff, 0x04, 0x67, 0xd7, 0xe5, 0xe6, ++ 0x23, 0x3d, 0x5a, 0x95, 0x98, 0x47, 0x3b, 0xfa, 0xaf, 0x57, 0x55, 0xe3, ++ 0x83, 0xa8, 0x85, 0x1d, 0xfb, 0xdd, 0x48, 0x0f, 0x93, 0xcf, 0x0e, 0xd7, ++ 0xe2, 0xf1, 0x5d, 0x1a, 0x1e, 0xdb, 0x75, 0x31, 0x06, 0x76, 0x5d, 0x8a, ++ 0xbd, 0xbb, 0xea, 0x91, 0x62, 0xae, 0xfc, 0xd1, 0x52, 0xdb, 0x5e, 0xc2, ++ 0xcf, 0xc3, 0xf4, 0x05, 0x2f, 0xff, 0xbf, 0x10, 0x15, 0x3f, 0xd1, 0x71, ++ 0xb9, 0xe3, 0x2f, 0xed, 0xb8, 0xcc, 0xf9, 0x1f, 0xc7, 0x92, 0x6c, 0x6f, ++ 0xb4, 0x3b, 0xbf, 0x25, 0x7a, 0x6f, 0x7e, 0x3e, 0xb6, 0x8d, 0xd6, 0x61, ++ 0x74, 0x57, 0x6d, 0xa2, 0x96, 0xfd, 0xac, 0xbd, 0xca, 0xc6, 0x38, 0xeb, ++ 0x1a, 0x2d, 0x43, 0xd1, 0x0d, 0xf9, 0x67, 0xd0, 0x99, 0xf7, 0xa3, 0x7f, ++ 0x34, 0xc0, 0xbe, 0x64, 0x7d, 0xdf, 0x7d, 0xfc, 0x1e, 0xd8, 0xf6, 0x99, ++ 0xa5, 0x87, 0x19, 0xdf, 0xbe, 0x8f, 0x2e, 0x3e, 0x4b, 0x8d, 0x76, 0x93, ++ 0x53, 0x95, 0x24, 0xbc, 0xa6, 0x8d, 0x97, 0xa3, 0xd3, 0xb8, 0x99, 0xed, ++ 0x3d, 0x32, 0x5a, 0x45, 0x99, 0xca, 0x13, 0xa5, 0xbc, 0x77, 0x43, 0x74, ++ 0x33, 0x76, 0x4c, 0xc9, 0x1a, 0xe0, 0x71, 0xdc, 0x40, 0xce, 0x52, 0xb3, ++ 0xcc, 0xed, 0x43, 0x95, 0xe6, 0x3e, 0xdd, 0x2a, 0xf6, 0x97, 0xa0, 0xfd, ++ 0x09, 0x56, 0x6e, 0xc2, 0x46, 0xe7, 0x1c, 0x65, 0x17, 0x9e, 0x4f, 0x0a, ++ 0x4e, 0xdf, 0x89, 0x03, 0xc9, 0x4d, 0x18, 0x48, 0xcb, 0x1e, 0xe1, 0x6a, ++ 0x34, 0xe4, 0xff, 0x2a, 0x7a, 0x37, 0xe3, 0xa9, 0x2b, 0xff, 0x3f, 0xb0, ++ 0x32, 0x9f, 0xa1, 0x5c, 0x13, 0xd1, 0x8d, 0xf9, 0xbd, 0xd1, 0x7b, 0xf2, ++ 0x1d, 0x58, 0x94, 0x97, 0xf5, 0xb4, 0x4e, 0xe2, 0xbb, 0xac, 0xa7, 0xcd, ++ 0xa0, 0x2d, 0xff, 0x16, 0x56, 0xe4, 0xdf, 0x60, 0x2c, 0x16, 0xdc, 0x90, ++ 0x75, 0xb6, 0x12, 0x0f, 0xca, 0x65, 0x4f, 0xf1, 0xeb, 0xd8, 0xb6, 0x27, ++ 0xc1, 0x58, 0x58, 0xc4, 0xa8, 0x26, 0x6d, 0xbf, 0xe0, 0xcb, 0x94, 0xc7, ++ 0x89, 0x05, 0x23, 0xe9, 0xdb, 0x68, 0x8f, 0x2a, 0x79, 0xbe, 0xc4, 0x99, ++ 0x4d, 0xf4, 0xe5, 0x5e, 0xf2, 0x73, 0x89, 0x7f, 0x5f, 0x9a, 0xbd, 0x2f, ++ 0xbc, 0x4e, 0x62, 0x5f, 0x10, 0x47, 0xb2, 0xce, 0x3e, 0x47, 0xd0, 0xab, ++ 0xdf, 0xcc, 0x67, 0x52, 0xff, 0xeb, 0x48, 0xed, 0x89, 0xd9, 0x8f, 0x38, ++ 0x6b, 0x46, 0x0a, 0x8e, 0x85, 0xd9, 0x17, 0x69, 0xe4, 0x0d, 0xfb, 0xe4, ++ 0xdc, 0xe9, 0x26, 0x39, 0x77, 0x6a, 0xb9, 0xf4, 0x56, 0x7b, 0x20, 0x8d, ++ 0x7b, 0x2a, 0x11, 0xc0, 0xea, 0x5c, 0x09, 0xe2, 0x07, 0xca, 0x71, 0xd3, ++ 0x2e, 0x93, 0xb6, 0x6c, 0xd1, 0x7e, 0x75, 0x63, 0xa3, 0x52, 0x8e, 0x55, ++ 0xbc, 0x77, 0xd7, 0x68, 0xa8, 0x03, 0x08, 0x1f, 0x3f, 0xe9, 0x2a, 0xc7, ++ 0x7a, 0xc6, 0x8e, 0x4c, 0x66, 0x35, 0xe2, 0xfb, 0x8e, 0xc1, 0xca, 0xd0, ++ 0x26, 0x77, 0x13, 0x67, 0xf6, 0xb8, 0xa1, 0x9a, 0x3f, 0xc3, 0xde, 0x09, ++ 0x15, 0xd5, 0xbb, 0x9f, 0xb5, 0x03, 0xba, 0xa2, 0x7f, 0x1c, 0xce, 0x93, ++ 0x03, 0xb9, 0x51, 0x99, 0x6a, 0x47, 0x8e, 0x58, 0xe3, 0x4b, 0xc5, 0x91, ++ 0xcd, 0x76, 0x22, 0x43, 0x2c, 0xc9, 0x90, 0x37, 0x55, 0xa4, 0x0c, 0xc6, ++ 0xf2, 0x08, 0x76, 0xd0, 0x5f, 0x4a, 0x98, 0xcb, 0x6f, 0xcf, 0x5e, 0x07, ++ 0x6b, 0xe2, 0x16, 0x0c, 0x4e, 0x74, 0xf2, 0x43, 0xfe, 0x38, 0xf1, 0x20, ++ 0xda, 0x72, 0xc7, 0x31, 0x94, 0x4d, 0xd0, 0x1e, 0x3f, 0xc4, 0x60, 0xe6, ++ 0x28, 0x1e, 0x1f, 0x91, 0xb3, 0x9e, 0x47, 0xf1, 0x18, 0xbf, 0x8f, 0x8c, ++ 0xe8, 0xbd, 0x01, 0xf5, 0x28, 0xd2, 0x99, 0x2d, 0xb8, 0x65, 0x54, 0x61, ++ 0x0e, 0xb7, 0x05, 0x37, 0xef, 0xa3, 0x2d, 0x3e, 0xda, 0x83, 0x8e, 0xdc, ++ 0x4b, 0x48, 0x66, 0x9f, 0x67, 0x7e, 0xb5, 0x19, 0x43, 0xe9, 0x6e, 0x72, ++ 0xaf, 0x67, 0xd8, 0xce, 0x61, 0xfa, 0x79, 0x2f, 0xc7, 0xf8, 0x10, 0x3f, ++ 0xe7, 0x30, 0x5c, 0x0b, 0x2a, 0x45, 0xac, 0xa6, 0xdf, 0xa7, 0xf3, 0x8e, ++ 0x9e, 0xb7, 0xa7, 0x1f, 0xae, 0x74, 0xce, 0x97, 0xeb, 0xc5, 0x35, 0x69, ++ 0x99, 0x8b, 0xe2, 0xba, 0xb9, 0x1b, 0x65, 0x29, 0x59, 0x8f, 0x9e, 0x0e, ++ 0x95, 0x91, 0x03, 0x78, 0x53, 0xa2, 0x43, 0xd3, 0xde, 0x9a, 0x16, 0x2c, ++ 0x29, 0x70, 0xf3, 0x17, 0xb2, 0x3f, 0xc3, 0xb6, 0x9d, 0xf3, 0xb0, 0x62, ++ 0xa4, 0x1e, 0x09, 0xbf, 0x6d, 0x3f, 0x4d, 0x5f, 0x4b, 0x92, 0x82, 0xed, ++ 0x18, 0x8d, 0x13, 0x53, 0x2a, 0x50, 0xc8, 0xf5, 0x44, 0x37, 0x21, 0x23, ++ 0xf8, 0x99, 0xfd, 0x93, 0x45, 0x9c, 0x37, 0xe1, 0xae, 0xd3, 0x97, 0x55, ++ 0xa2, 0xc1, 0x57, 0x58, 0x17, 0xdf, 0x78, 0x8e, 0xdb, 0xfc, 0xc7, 0xca, ++ 0xff, 0xa7, 0xff, 0xcd, 0xf2, 0x73, 0xcf, 0xcd, 0x15, 0xdf, 0x2d, 0x92, ++ 0xb1, 0x5e, 0x2a, 0xef, 0x37, 0x59, 0xc2, 0x97, 0xe4, 0x8c, 0xf0, 0xb1, ++ 0x64, 0x09, 0xe3, 0xa4, 0xba, 0xdc, 0x03, 0xd5, 0xef, 0x41, 0x29, 0xe3, ++ 0x59, 0x1d, 0xfa, 0xfd, 0x36, 0x56, 0x1a, 0x25, 0x38, 0xd4, 0x1c, 0x97, ++ 0x33, 0x18, 0x5d, 0x1e, 0x87, 0x8f, 0x26, 0xbe, 0xfc, 0xfb, 0xeb, 0xd6, ++ 0x5b, 0xc8, 0xdd, 0xe4, 0xec, 0x41, 0x27, 0x5e, 0xae, 0x91, 0xf7, 0x9d, ++ 0xb6, 0xd0, 0x8e, 0x15, 0x94, 0x35, 0xca, 0x3a, 0x5a, 0x10, 0xc7, 0xf5, ++ 0xa6, 0x60, 0xad, 0xca, 0x78, 0xae, 0x9c, 0xb2, 0x2d, 0xbf, 0xc9, 0x58, ++ 0x2f, 0xe7, 0x2b, 0xfe, 0xd8, 0x1e, 0xc6, 0x06, 0x0c, 0x3e, 0xda, 0x8a, ++ 0x99, 0x75, 0x12, 0xff, 0x5f, 0xf7, 0x15, 0x39, 0xdd, 0xf6, 0xf4, 0x7b, ++ 0x95, 0x72, 0x66, 0x49, 0xda, 0x1e, 0x64, 0xfe, 0xe4, 0xd1, 0xa3, 0x38, ++ 0x25, 0x2c, 0xcd, 0xd9, 0x6b, 0x2a, 0x70, 0x8a, 0x52, 0xbd, 0x61, 0xb6, ++ 0xfc, 0xfb, 0x95, 0xc2, 0x0f, 0xb7, 0xa7, 0xb7, 0x90, 0x9b, 0x8b, 0x3c, ++ 0xbf, 0xb1, 0x37, 0xf8, 0x6b, 0x59, 0x76, 0xfb, 0xec, 0x73, 0xb1, 0x05, ++ 0x39, 0xaf, 0x23, 0xf7, 0xa4, 0x8e, 0xe8, 0x6c, 0x6e, 0x1d, 0x17, 0x73, ++ 0xe1, 0xcb, 0xf0, 0x00, 0x7d, 0x70, 0xa1, 0xfe, 0x8a, 0xdd, 0x27, 0x67, ++ 0x6b, 0x1a, 0xb5, 0x39, 0x7d, 0x95, 0x56, 0x89, 0x2c, 0xa5, 0x94, 0x65, ++ 0x34, 0x2d, 0xe7, 0x60, 0x3f, 0xb5, 0x1b, 0xeb, 0xe4, 0x79, 0x53, 0x65, ++ 0xa1, 0xfd, 0x06, 0xe7, 0x5c, 0xe1, 0xde, 0x74, 0x51, 0x6e, 0x59, 0x6f, ++ 0xf5, 0x17, 0xfb, 0x8a, 0x9c, 0x1f, 0x8f, 0xc8, 0xf6, 0x68, 0xe5, 0x67, ++ 0x65, 0x5e, 0xea, 0x2b, 0x9e, 0x97, 0x5d, 0xe0, 0xd4, 0x29, 0xf6, 0x29, ++ 0x32, 0x6e, 0x61, 0x9e, 0x7a, 0xe1, 0x18, 0x57, 0xcc, 0x19, 0x93, 0xd4, ++ 0x91, 0x71, 0x69, 0xb3, 0x76, 0x10, 0xa7, 0x9c, 0x52, 0x47, 0xb8, 0xab, ++ 0xe6, 0x70, 0xf0, 0x6a, 0xe1, 0xe5, 0x62, 0x1b, 0x55, 0xb6, 0xfd, 0xb6, ++ 0x13, 0x33, 0xa5, 0x1d, 0x8e, 0x63, 0x2a, 0x46, 0x3b, 0xb7, 0xfb, 0x88, ++ 0x9f, 0xf6, 0xdb, 0xad, 0x01, 0x6c, 0x4b, 0x8a, 0xae, 0xf5, 0xc0, 0x41, ++ 0x62, 0x47, 0xbf, 0xc3, 0x37, 0x3c, 0xd8, 0x9a, 0x29, 0xee, 0x9d, 0x96, ++ 0xca, 0xbe, 0x52, 0x40, 0x74, 0xbe, 0xd5, 0x20, 0xcf, 0xd2, 0xda, 0x82, ++ 0x6e, 0x72, 0xa5, 0xbb, 0xf1, 0x5b, 0xce, 0xaf, 0x9c, 0x7d, 0x2e, 0xec, ++ 0x63, 0x26, 0x68, 0x47, 0x85, 0x78, 0x05, 0xc6, 0x77, 0xf2, 0xa4, 0xd9, ++ 0x33, 0xa1, 0x5b, 0xb3, 0xbf, 0xb5, 0xa7, 0x9d, 0x33, 0xa1, 0xe7, 0xdf, ++ 0x77, 0xc9, 0x68, 0xb6, 0xbd, 0x9f, 0xcf, 0xce, 0x9f, 0x0f, 0x65, 0x4c, ++ 0xd7, 0xe5, 0x1c, 0xe9, 0xbf, 0x71, 0xee, 0xe6, 0x96, 0x9d, 0xae, 0x29, ++ 0x9c, 0x97, 0x8e, 0xab, 0x6d, 0x7a, 0x11, 0x57, 0x43, 0x96, 0xe5, 0xe0, ++ 0xaa, 0x55, 0x55, 0xd8, 0xc3, 0x0a, 0x75, 0x74, 0xc2, 0xb2, 0xcb, 0xf5, ++ 0x22, 0x0e, 0xe8, 0xc6, 0x12, 0xa5, 0x0f, 0x8b, 0xa3, 0xf2, 0xde, 0x19, ++ 0x42, 0x6e, 0x33, 0xa4, 0xbd, 0x8b, 0x70, 0xe4, 0xa8, 0xb3, 0x8f, 0x2a, ++ 0xd8, 0xa0, 0xe3, 0xee, 0xac, 0x4e, 0x9b, 0x95, 0xf7, 0x35, 0xe5, 0xbb, ++ 0xd3, 0x3e, 0xbf, 0x0b, 0x96, 0x76, 0x11, 0x4b, 0xad, 0xff, 0xec, 0x71, ++ 0xda, 0x0b, 0x75, 0x4d, 0x28, 0xa1, 0x8e, 0xcd, 0x4a, 0xb1, 0x3d, 0xdf, ++ 0x1f, 0x68, 0x2f, 0xc2, 0xfa, 0xc1, 0xd9, 0x77, 0x24, 0x75, 0xb6, 0x71, ++ 0xe1, 0x5e, 0xf3, 0xfc, 0x84, 0xec, 0x45, 0x1d, 0x9a, 0xe5, 0x84, 0x47, ++ 0x7f, 0x6f, 0x2f, 0xea, 0x0f, 0xf6, 0x19, 0x67, 0x9f, 0x1d, 0xe5, 0x4a, ++ 0x9c, 0x8c, 0xa1, 0x0f, 0xa5, 0xd1, 0x70, 0xe4, 0x05, 0x20, 0xe8, 0x36, ++ 0xc3, 0x81, 0x09, 0x67, 0xbf, 0xd7, 0xf0, 0xae, 0xc8, 0x16, 0xfc, 0xc7, ++ 0x9a, 0xfa, 0xd3, 0x3a, 0xa9, 0xd0, 0xf5, 0xce, 0x26, 0x25, 0x7e, 0x4d, ++ 0x39, 0xdb, 0x89, 0x44, 0x11, 0x2c, 0x31, 0x8b, 0x3a, 0x0a, 0x47, 0xde, ++ 0xe5, 0x7c, 0x1e, 0x69, 0x0d, 0x07, 0xc6, 0x9d, 0xf3, 0xa3, 0xa2, 0x17, ++ 0xc3, 0x5b, 0x98, 0x7b, 0x5d, 0xf8, 0x36, 0xf3, 0xc9, 0x04, 0x26, 0x93, ++ 0x5e, 0x8e, 0xa5, 0x49, 0x1b, 0x44, 0x0d, 0x6d, 0x1c, 0xf1, 0xfe, 0x66, ++ 0xe2, 0x77, 0x12, 0x71, 0xd7, 0xe5, 0xd5, 0x48, 0x90, 0x40, 0xbb, 0xf4, ++ 0x04, 0x39, 0x51, 0x53, 0xe4, 0x61, 0xda, 0x6f, 0xc6, 0x1f, 0x0a, 0x58, ++ 0x48, 0xe0, 0xb9, 0x64, 0xdb, 0x1d, 0x2e, 0x58, 0x46, 0x05, 0xe4, 0x5d, ++ 0x88, 0xe9, 0x2f, 0xdf, 0x18, 0x0e, 0x05, 0x7f, 0x38, 0xbb, 0x5f, 0xbd, ++ 0x35, 0xf9, 0x2b, 0x79, 0xc7, 0x8b, 0xf5, 0xfe, 0x54, 0x19, 0xe9, 0xdb, ++ 0x8b, 0x83, 0x23, 0x23, 0x18, 0x78, 0x94, 0x32, 0xea, 0x36, 0xda, 0x8c, ++ 0x3e, 0xe6, 0xd2, 0x3e, 0x6c, 0xd2, 0x16, 0xc7, 0x54, 0x96, 0x1b, 0xcf, ++ 0x14, 0xd6, 0x1d, 0xb7, 0x39, 0xfb, 0xe1, 0x43, 0xcc, 0x51, 0x9c, 0xf8, ++ 0xa9, 0x79, 0xcd, 0xb8, 0xf2, 0x48, 0xb6, 0x5d, 0x79, 0x38, 0x23, 0x6d, ++ 0xf5, 0x2a, 0x43, 0x59, 0x4f, 0x35, 0xca, 0x2d, 0x9c, 0x34, 0xde, 0x98, ++ 0xc5, 0xc5, 0x24, 0x73, 0xaf, 0xe2, 0xbb, 0xa2, 0x85, 0xb3, 0x6a, 0x4f, ++ 0x93, 0x0b, 0x3d, 0xca, 0x5c, 0x74, 0x7d, 0xca, 0x82, 0x66, 0xfe, 0xc2, ++ 0xae, 0x32, 0x81, 0x6f, 0xe4, 0x75, 0x74, 0xa5, 0xca, 0x91, 0x18, 0xb7, ++ 0xed, 0x97, 0xc9, 0xd5, 0x7b, 0xf3, 0xcd, 0xcc, 0x9d, 0x1e, 0xb7, 0x2b, ++ 0xe8, 0x2f, 0xf7, 0x2f, 0xf3, 0xe1, 0x81, 0x71, 0x1f, 0xfe, 0x0b, 0x63, ++ 0xa0, 0xd7, 0xac, 0xe0, 0xf7, 0x70, 0xe2, 0x34, 0xe7, 0x6b, 0x58, 0xd1, ++ 0x63, 0x4b, 0x94, 0xb0, 0xf1, 0x2e, 0xb9, 0xe4, 0x3d, 0x79, 0x59, 0x17, ++ 0x0b, 0x20, 0x91, 0xb7, 0xe1, 0xa6, 0xce, 0xef, 0x66, 0xfd, 0x15, 0x29, ++ 0xdb, 0x96, 0xbc, 0x39, 0x71, 0x50, 0x3f, 0xb3, 0x81, 0xfe, 0xd9, 0x97, ++ 0xf7, 0xb2, 0xcf, 0x21, 0xc6, 0x22, 0x59, 0x67, 0x08, 0xb2, 0x4f, 0x1f, ++ 0xd6, 0xa4, 0xec, 0xe5, 0x6f, 0x44, 0xad, 0x6f, 0x04, 0xa0, 0xe3, 0x81, ++ 0xbc, 0xac, 0x3d, 0x84, 0xd8, 0xb6, 0x82, 0x17, 0xa3, 0x11, 0x7c, 0x35, ++ 0x1f, 0xc0, 0x8d, 0xa9, 0x23, 0x5f, 0xf4, 0xc1, 0xba, 0xa9, 0x02, 0xcd, ++ 0xb8, 0xdf, 0xd9, 0x7b, 0x0b, 0xc5, 0xca, 0x94, 0x7a, 0xdc, 0x7b, 0xd0, ++ 0x60, 0x9f, 0x2a, 0x56, 0xb2, 0x9d, 0xf6, 0xd4, 0xa5, 0xb8, 0xfb, 0x60, ++ 0x2b, 0x36, 0xe5, 0x97, 0x32, 0x6f, 0x14, 0x1e, 0x5c, 0x22, 0xef, 0x6e, ++ 0xe0, 0xfa, 0x31, 0xe7, 0x3d, 0x17, 0x65, 0x45, 0xeb, 0x34, 0xfa, 0xc8, ++ 0xc3, 0xfb, 0xf2, 0x72, 0x8f, 0xb1, 0x3a, 0x6d, 0xe0, 0x85, 0xcc, 0x52, ++ 0xe6, 0x90, 0x2a, 0x26, 0xc4, 0xd7, 0x3b, 0x15, 0x8e, 0x55, 0x67, 0xac, ++ 0x15, 0xfb, 0x31, 0x50, 0x3e, 0x1a, 0xee, 0xb8, 0x49, 0x31, 0x98, 0x8f, ++ 0x16, 0xee, 0x8f, 0xa4, 0x9f, 0xb5, 0x7d, 0xfa, 0xcf, 0x6d, 0x37, 0x31, ++ 0xb9, 0x66, 0x5c, 0xc7, 0x30, 0x73, 0xd9, 0x80, 0x69, 0xa1, 0xe6, 0x6a, ++ 0x13, 0x53, 0xa3, 0x7d, 0xe4, 0xb9, 0x26, 0xf2, 0xfb, 0x74, 0x3c, 0x4c, ++ 0x3c, 0x6c, 0x1a, 0xd5, 0x19, 0x3b, 0x4c, 0x2c, 0xe1, 0xf5, 0xe3, 0xc4, ++ 0xfe, 0xee, 0x94, 0x89, 0xb7, 0x39, 0xa7, 0xa5, 0x97, 0xc7, 0x6b, 0x4a, ++ 0xa1, 0xd3, 0x87, 0xc4, 0xfe, 0x4c, 0xbc, 0x49, 0x30, 0x18, 0xa4, 0x1e, ++ 0xd6, 0xef, 0x6e, 0xc1, 0xa7, 0x13, 0xa2, 0xbb, 0x2d, 0xb8, 0x62, 0xcc, ++ 0x85, 0xa7, 0x8c, 0x86, 0x5e, 0x0d, 0x2e, 0x7c, 0x14, 0x0d, 0x69, 0x39, ++ 0xda, 0xd8, 0x4b, 0x51, 0x15, 0xd6, 0xfc, 0x56, 0xac, 0xa2, 0x5c, 0xab, ++ 0x74, 0x19, 0x8f, 0x85, 0x15, 0xe4, 0xd0, 0x7d, 0xe4, 0xe1, 0xcf, 0x42, ++ 0xd6, 0xd6, 0x54, 0xe0, 0x22, 0x37, 0x6d, 0x46, 0xde, 0x7b, 0xd5, 0x89, ++ 0xc9, 0x82, 0x91, 0xad, 0x90, 0x77, 0xa7, 0x17, 0xec, 0x5f, 0xce, 0x7c, ++ 0x57, 0x67, 0xec, 0xf2, 0x32, 0xef, 0x26, 0xb7, 0x58, 0xa6, 0xe0, 0x55, ++ 0xca, 0x35, 0x9a, 0x5e, 0xce, 0xbc, 0x57, 0xf2, 0x79, 0x15, 0x97, 0x1f, ++ 0xbc, 0x13, 0xf7, 0xef, 0xfa, 0x97, 0x2a, 0xc1, 0xcb, 0xce, 0xa8, 0x75, ++ 0x93, 0xca, 0xbc, 0xce, 0x50, 0xd0, 0x46, 0x1f, 0xa6, 0xbf, 0xb8, 0x11, ++ 0xce, 0xc7, 0x58, 0x4e, 0x27, 0xf6, 0x06, 0xc8, 0xff, 0x29, 0x47, 0xaa, ++ 0x1e, 0x07, 0x99, 0x17, 0x64, 0xc8, 0x7b, 0x32, 0xcc, 0x63, 0x32, 0x13, ++ 0x75, 0xfc, 0x04, 0xf9, 0x59, 0xc4, 0x8f, 0xee, 0xdc, 0xdb, 0x90, 0x52, ++ 0x10, 0xef, 0x54, 0xfe, 0xc8, 0x7b, 0xc1, 0xb4, 0xe5, 0xec, 0xd9, 0xaa, ++ 0x02, 0x7f, 0x94, 0xf7, 0xdd, 0xc4, 0xf6, 0x2d, 0x4c, 0xb4, 0xca, 0x7b, ++ 0x6f, 0x7f, 0xee, 0x9d, 0x37, 0xb1, 0xdf, 0x5e, 0xf4, 0xef, 0x7c, 0x08, ++ 0x5b, 0x77, 0xae, 0x71, 0xce, 0xc8, 0x79, 0xf4, 0xd0, 0x69, 0x0b, 0x95, ++ 0x1a, 0xf3, 0xee, 0xc3, 0x16, 0x6e, 0xc6, 0x0e, 0x4d, 0xde, 0xe5, 0x1a, ++ 0x92, 0x98, 0xef, 0x0d, 0x90, 0xf3, 0x06, 0x38, 0xa7, 0x35, 0x74, 0xef, ++ 0x3a, 0x53, 0xce, 0xda, 0xea, 0xd6, 0x2f, 0x95, 0x66, 0xbc, 0x96, 0x7f, ++ 0x08, 0x1f, 0xef, 0xee, 0xc3, 0x87, 0xd1, 0x2a, 0xab, 0xd2, 0xb4, 0xfb, ++ 0x5e, 0x8c, 0x86, 0x3a, 0x87, 0x95, 0x78, 0x47, 0x05, 0x42, 0x87, 0x96, ++ 0xc8, 0xd9, 0xa4, 0xdd, 0xb2, 0xc6, 0xd5, 0x05, 0xef, 0xb0, 0xc5, 0xf6, ++ 0xed, 0xe5, 0xbb, 0x0c, 0x39, 0x17, 0x6c, 0x5d, 0x33, 0x1f, 0xa1, 0xe3, ++ 0xf7, 0x42, 0x3f, 0x13, 0x76, 0x41, 0x51, 0xcd, 0xf0, 0xc8, 0x49, 0x57, ++ 0x1f, 0xf5, 0xef, 0xb3, 0x6a, 0x88, 0x89, 0x3f, 0xca, 0x87, 0x46, 0x6a, ++ 0x5c, 0x95, 0xe8, 0xa4, 0x5e, 0xab, 0x5b, 0xae, 0x66, 0x4e, 0x14, 0xda, ++ 0x3b, 0xa3, 0x3e, 0x84, 0x37, 0x77, 0x3f, 0x84, 0x77, 0xf9, 0x39, 0xb5, ++ 0x9b, 0xfe, 0xab, 0x33, 0xfe, 0x30, 0xef, 0x7d, 0x93, 0xff, 0x37, 0x18, ++ 0xfa, 0x99, 0x09, 0x87, 0x93, 0x3e, 0x84, 0x4f, 0x0f, 0x3e, 0x84, 0xb7, ++ 0xd9, 0xa7, 0x9f, 0xf8, 0xb3, 0x33, 0x65, 0xf7, 0xfd, 0x77, 0xe3, 0x1f, ++ 0xf0, 0xe3, 0x5a, 0x89, 0x05, 0xb2, 0x9e, 0x38, 0x44, 0xce, 0x1e, 0x8a, ++ 0x64, 0x54, 0xdb, 0x9e, 0xb7, 0xf8, 0xb0, 0x73, 0xde, 0xfa, 0xd6, 0x7c, ++ 0x2f, 0xfe, 0x69, 0xcf, 0x43, 0xf8, 0xf1, 0x1e, 0x0d, 0xbb, 0x6a, 0x25, ++ 0xde, 0xc9, 0x5a, 0x34, 0x14, 0x7d, 0x99, 0xd7, 0x2a, 0x27, 0x8e, 0x74, ++ 0x8c, 0x1e, 0xc3, 0x20, 0xb9, 0xa6, 0x3f, 0x2a, 0x79, 0x7b, 0x93, 0x31, ++ 0xa0, 0x7e, 0x8f, 0xf1, 0x48, 0xc1, 0x8e, 0xc6, 0x11, 0xa4, 0x68, 0x8b, ++ 0xc9, 0xc6, 0x50, 0x77, 0x0a, 0x7f, 0x67, 0x67, 0xe7, 0x8b, 0x9e, 0xfe, ++ 0xa3, 0xef, 0xbe, 0xc9, 0xfb, 0xf2, 0xc5, 0xf7, 0xdf, 0x42, 0xc1, 0x69, ++ 0xf4, 0x3b, 0x6b, 0x0c, 0x96, 0xaa, 0xe1, 0x26, 0x72, 0xe1, 0xd5, 0xb4, ++ 0x91, 0x01, 0x07, 0x93, 0xe4, 0xbd, 0x2b, 0x0d, 0x37, 0xd2, 0xd7, 0x1e, ++ 0xce, 0xdc, 0xc9, 0xf1, 0x1b, 0x8e, 0xfd, 0x8c, 0xa6, 0x0b, 0x36, 0xd6, ++ 0x63, 0x58, 0x2b, 0xe4, 0x0c, 0x3e, 0x29, 0x47, 0x5b, 0xa9, 0x19, 0xd6, ++ 0x26, 0x69, 0x63, 0x8b, 0x88, 0x1d, 0x77, 0xb1, 0xcc, 0x23, 0xe4, 0x69, ++ 0xeb, 0x53, 0x5e, 0x54, 0xe8, 0xf5, 0xb8, 0x2b, 0x17, 0xc0, 0xfa, 0x9c, ++ 0x0f, 0xf1, 0x1c, 0x41, 0x37, 0x47, 0x1e, 0x3f, 0x26, 0x39, 0x01, 0xa6, ++ 0xe5, 0x5c, 0xea, 0x6b, 0x86, 0x1f, 0x9d, 0x07, 0xbc, 0xe8, 0xda, 0x5d, ++ 0x87, 0x2e, 0xf2, 0xfb, 0x35, 0x63, 0xe2, 0x8f, 0x36, 0xae, 0x6c, 0x09, ++ 0xe2, 0x4b, 0xbc, 0x7f, 0xcb, 0x6e, 0x28, 0x35, 0x57, 0x2f, 0xc2, 0x2d, ++ 0x0c, 0xc6, 0xf1, 0x5c, 0x05, 0x6d, 0xdd, 0x66, 0xfe, 0xa8, 0x62, 0xf5, ++ 0x01, 0x05, 0x37, 0xed, 0x33, 0x70, 0x03, 0xfb, 0xea, 0xa7, 0x4f, 0x57, ++ 0x30, 0xe6, 0xde, 0x97, 0x35, 0xb0, 0x29, 0x23, 0x3e, 0xfe, 0x73, 0xdb, ++ 0xa5, 0xb7, 0xa0, 0x74, 0xb7, 0x4e, 0xbb, 0x0f, 0x6b, 0x7f, 0x83, 0x16, ++ 0xa8, 0x07, 0x5b, 0xb0, 0x70, 0x6c, 0x39, 0x39, 0x7b, 0x1c, 0x8d, 0x57, ++ 0xb7, 0xa0, 0x84, 0xbe, 0x9f, 0xa4, 0xbe, 0xac, 0xdc, 0x34, 0xae, 0x4c, ++ 0xc5, 0x90, 0xce, 0x99, 0xcc, 0xd5, 0xec, 0xbe, 0x6a, 0xb3, 0x8f, 0x79, ++ 0x9a, 0x89, 0xe1, 0x7d, 0xa2, 0x03, 0xdb, 0xfe, 0x78, 0x99, 0x89, 0x47, ++ 0x46, 0x74, 0x62, 0x88, 0x49, 0x1d, 0x88, 0xef, 0x98, 0x38, 0x34, 0xa2, ++ 0xc7, 0x5c, 0xbc, 0x9e, 0xcc, 0xb4, 0xa2, 0xcd, 0xd1, 0x87, 0x9c, 0x55, ++ 0x8c, 0x73, 0xec, 0xcd, 0x1c, 0xb3, 0xc1, 0xf1, 0x37, 0x18, 0xcb, 0x5d, ++ 0xed, 0x68, 0x64, 0xfe, 0x65, 0x8c, 0xf5, 0x21, 0xd0, 0xd2, 0x81, 0xd8, ++ 0xb8, 0x60, 0x92, 0x41, 0x4c, 0xec, 0x80, 0x6f, 0x58, 0xef, 0xca, 0x2b, ++ 0x7a, 0xe7, 0x6e, 0x45, 0xb0, 0xa9, 0x83, 0x39, 0x79, 0x39, 0xda, 0xc7, ++ 0x56, 0xc3, 0xcd, 0x7c, 0xe6, 0xfa, 0xdd, 0xd2, 0xc7, 0x2d, 0x98, 0x9c, ++ 0x30, 0xd0, 0x99, 0x12, 0x7d, 0xcb, 0x19, 0xb8, 0x04, 0xee, 0x4e, 0x32, ++ 0x4f, 0x1f, 0x8b, 0x7f, 0xaa, 0x42, 0xce, 0x2e, 0x82, 0xcc, 0x35, 0x64, ++ 0x9c, 0x74, 0xa9, 0xb8, 0x6a, 0xa9, 0x0b, 0xd3, 0xe4, 0xc6, 0x25, 0xaa, ++ 0xf5, 0x94, 0x07, 0x21, 0xab, 0x4e, 0xdd, 0x82, 0xaf, 0xd2, 0x6e, 0xbf, ++ 0x4b, 0x1d, 0x25, 0x6a, 0xad, 0x1e, 0xb9, 0x57, 0xa5, 0x1a, 0x9c, 0x57, ++ 0x58, 0x1e, 0xdd, 0x45, 0xce, 0xdf, 0xd0, 0x51, 0x4e, 0x4c, 0x92, 0xf3, ++ 0xf1, 0x6e, 0x55, 0x74, 0xd5, 0xca, 0xbc, 0xf1, 0x21, 0xbc, 0x35, 0x6b, ++ 0xdb, 0xbf, 0xdc, 0x5d, 0xb0, 0xeb, 0x93, 0xb4, 0xeb, 0xbb, 0x0c, 0xfd, ++ 0x78, 0x58, 0x0d, 0x73, 0x2c, 0xb4, 0x69, 0xda, 0xf5, 0x19, 0xda, 0x75, ++ 0x2d, 0xed, 0x7a, 0x2d, 0xed, 0xba, 0x7a, 0x69, 0x00, 0x9f, 0x38, 0xeb, ++ 0x01, 0x62, 0xd3, 0x87, 0x1d, 0xfb, 0xc9, 0xa8, 0xf2, 0xfd, 0xf8, 0xac, ++ 0x2d, 0x9d, 0x9d, 0x5d, 0xf3, 0x2e, 0xd3, 0x0a, 0x67, 0x44, 0xa5, 0x6d, ++ 0xdd, 0xd2, 0xe9, 0x47, 0xa7, 0xd9, 0xd6, 0x2f, 0xc6, 0x1e, 0xc2, 0x07, ++ 0x9c, 0xcb, 0x8f, 0xa3, 0x47, 0xee, 0xab, 0xc2, 0xe2, 0x44, 0x25, 0xa6, ++ 0xd7, 0xf8, 0x18, 0xe7, 0xef, 0x8b, 0x86, 0x83, 0x4b, 0x14, 0x17, 0xeb, ++ 0x50, 0xa6, 0x71, 0xf1, 0x25, 0x7d, 0xfa, 0x18, 0xeb, 0x9e, 0x99, 0xad, ++ 0xf3, 0x2b, 0xd6, 0xf9, 0x24, 0x7a, 0xe4, 0x81, 0x5a, 0x2c, 0xee, 0xae, ++ 0xc2, 0xf4, 0xd3, 0x95, 0xac, 0xb3, 0xb9, 0x25, 0x1c, 0xd9, 0xad, 0xd0, ++ 0x2f, 0xc7, 0xff, 0x1f, 0xd6, 0x13, 0x19, 0x84, 0xdb, 0x14, 0xf9, 0x5f, ++ 0x00, 0x9b, 0xb2, 0xf5, 0xb3, 0x3c, 0x89, 0x78, 0x96, 0x3c, 0xe4, 0xe0, ++ 0x54, 0x89, 0xd9, 0x49, 0x7c, 0x5a, 0x47, 0x9c, 0x5a, 0x4d, 0x8c, 0xea, ++ 0x20, 0x46, 0xb5, 0x13, 0xa3, 0xe2, 0xc4, 0x28, 0x93, 0x18, 0x15, 0x23, ++ 0x46, 0xb5, 0x12, 0xa3, 0x0c, 0x62, 0x14, 0x94, 0xe3, 0xad, 0xc7, 0xe0, ++ 0x19, 0xf5, 0xe2, 0x85, 0x11, 0xdb, 0xfe, 0x6b, 0x43, 0xce, 0xc9, 0xf4, ++ 0x31, 0x26, 0x2f, 0x09, 0xac, 0x94, 0x77, 0x01, 0x27, 0x2f, 0xe5, 0xe7, ++ 0x56, 0xf2, 0x09, 0x62, 0x28, 0x79, 0xd4, 0x09, 0xfa, 0x6a, 0x63, 0xb4, ++ 0x21, 0x78, 0x90, 0x9c, 0xf0, 0x51, 0x5d, 0xf6, 0xa2, 0x9a, 0x86, 0x2e, ++ 0x85, 0xde, 0x5b, 0xa3, 0x0e, 0x60, 0x66, 0x8d, 0x46, 0x3f, 0xf4, 0x5a, ++ 0x0b, 0xcc, 0xb5, 0xb8, 0x6a, 0x4f, 0x27, 0xae, 0xde, 0x83, 0xa3, 0x97, ++ 0xa2, 0xe1, 0xd0, 0x4f, 0x18, 0xba, 0xe6, 0xc3, 0xe5, 0xf7, 0x63, 0xc9, ++ 0xc8, 0x11, 0xce, 0x69, 0xbc, 0xce, 0xd5, 0x1c, 0x28, 0xcc, 0xb3, 0x7f, ++ 0x9e, 0x64, 0x3a, 0x58, 0x72, 0x46, 0xde, 0xe3, 0x9b, 0xf9, 0xb2, 0x70, ++ 0xa3, 0x32, 0xf4, 0x47, 0x54, 0xf9, 0x4d, 0x8c, 0x8c, 0x9c, 0xcd, 0xf5, ++ 0xeb, 0x82, 0x13, 0x1d, 0x58, 0x39, 0x6c, 0xdd, 0xe0, 0xc7, 0x6a, 0x74, ++ 0x0c, 0x17, 0xc6, 0xae, 0x47, 0x99, 0xcb, 0x92, 0xbb, 0x6d, 0x67, 0xf2, ++ 0xf5, 0x40, 0x6b, 0x8c, 0xe3, 0x4f, 0x92, 0x37, 0x9b, 0xe8, 0x9e, 0x7d, ++ 0xdf, 0xec, 0xcf, 0xfd, 0x9d, 0x7f, 0x1f, 0x6d, 0x49, 0xb7, 0x1f, 0xba, ++ 0xf6, 0x94, 0x72, 0x8d, 0xec, 0x2b, 0x1d, 0x12, 0x7c, 0xaa, 0x23, 0x2e, ++ 0xfd, 0x64, 0x4c, 0xde, 0x3d, 0x85, 0xd2, 0x9e, 0xea, 0xc3, 0x6f, 0x5a, ++ 0x0a, 0xf8, 0x31, 0x4d, 0xfc, 0xb8, 0x32, 0x25, 0xf7, 0x42, 0x23, 0xe4, ++ 0xc4, 0xcb, 0xff, 0x57, 0xf4, 0xbf, 0x39, 0xf7, 0x67, 0x18, 0xd6, 0xae, ++ 0xa0, 0xef, 0x1d, 0x89, 0x7a, 0xd1, 0x29, 0x67, 0x8b, 0xd6, 0xca, 0x3b, ++ 0x50, 0xd6, 0x19, 0xd5, 0x39, 0x47, 0x3a, 0xf4, 0xe5, 0x8d, 0x7a, 0xe8, ++ 0xf8, 0x9b, 0x2e, 0x79, 0xf7, 0xd8, 0xeb, 0xfc, 0x4c, 0x89, 0x70, 0xec, ++ 0x57, 0xc8, 0x9f, 0x76, 0x3c, 0x2a, 0xbe, 0xd8, 0x90, 0xc8, 0xc1, 0xc9, ++ 0xe1, 0x6a, 0xe4, 0xbc, 0xf6, 0xad, 0x61, 0xa9, 0xeb, 0xbc, 0x6f, 0xaa, ++ 0xb8, 0x53, 0x87, 0x8b, 0xed, 0xf3, 0xfb, 0xf1, 0x59, 0x19, 0xaa, 0x11, ++ 0xac, 0x15, 0xbd, 0x27, 0x21, 0xbf, 0x17, 0xf2, 0x44, 0x23, 0xb2, 0x65, ++ 0x68, 0xd8, 0xfb, 0x35, 0xd5, 0x95, 0x9d, 0x8f, 0x38, 0x56, 0x86, 0x97, ++ 0x3c, 0xf5, 0x8c, 0x2a, 0xcf, 0x15, 0x5c, 0xa4, 0xcb, 0x79, 0x33, 0x5d, ++ 0x7b, 0x4d, 0x4d, 0x62, 0xdb, 0xd4, 0x09, 0x3b, 0xee, 0xd7, 0x68, 0x0b, ++ 0x5e, 0xab, 0x94, 0xb6, 0xf1, 0xcb, 0x9d, 0xb2, 0x6f, 0x16, 0xa4, 0x0e, ++ 0x43, 0xc7, 0x9f, 0x56, 0x3b, 0x19, 0xd7, 0x0d, 0xc6, 0xca, 0x4e, 0xfc, ++ 0x7a, 0xe7, 0x5a, 0xbc, 0xb9, 0xb3, 0x21, 0xf1, 0x4f, 0xae, 0xcf, 0xe1, ++ 0x41, 0xc6, 0xac, 0xbf, 0x8e, 0xae, 0xc6, 0xa9, 0x64, 0x07, 0xde, 0x4b, ++ 0x5a, 0xff, 0x99, 0x31, 0xe5, 0xa9, 0x2c, 0xe4, 0xbc, 0x55, 0xd3, 0xa1, ++ 0x97, 0xd4, 0x50, 0x67, 0xab, 0x12, 0x3a, 0x7c, 0x9b, 0xb2, 0x1a, 0xbf, ++ 0xc9, 0x76, 0xe0, 0x7f, 0x65, 0x8b, 0x76, 0x60, 0xd9, 0x33, 0xf3, 0xc5, ++ 0x06, 0xc4, 0x16, 0xd6, 0x39, 0xbf, 0xa5, 0xf0, 0xf7, 0x94, 0x73, 0xc3, ++ 0xe7, 0x69, 0x87, 0x69, 0xda, 0x61, 0x9a, 0x76, 0x98, 0xa6, 0x1d, 0x12, ++ 0x67, 0xbe, 0x9b, 0xa6, 0x1d, 0xd2, 0x3f, 0x9f, 0x26, 0x6e, 0x14, 0x72, ++ 0xce, 0x2e, 0xe2, 0xf5, 0x3a, 0x7c, 0xb2, 0xb3, 0x1d, 0xbf, 0x20, 0x77, ++ 0xbc, 0xab, 0x65, 0x7a, 0x7a, 0x21, 0x42, 0x3d, 0x67, 0x88, 0x45, 0xf9, ++ 0x6c, 0x3b, 0x3e, 0x48, 0x9a, 0xc8, 0x25, 0x1b, 0xe2, 0x5f, 0x55, 0xbe, ++ 0x40, 0xc2, 0x20, 0x7a, 0x8c, 0xe3, 0x24, 0x73, 0xa3, 0x36, 0xe6, 0xba, ++ 0xa5, 0xec, 0xef, 0xad, 0x56, 0xb1, 0x8d, 0x18, 0x63, 0xb6, 0x21, 0xef, ++ 0xcf, 0xff, 0xd9, 0xbf, 0xaf, 0xd3, 0x06, 0x7e, 0xd2, 0x72, 0xd6, 0x9e, ++ 0xa9, 0xf5, 0x32, 0x2e, 0xae, 0x43, 0x64, 0xb7, 0xec, 0xcf, 0x8b, 0xef, ++ 0x28, 0x58, 0x10, 0x9d, 0x4e, 0x2c, 0xe0, 0x58, 0x1f, 0x51, 0xe0, 0xee, ++ 0x4f, 0xc9, 0x7a, 0x78, 0x3b, 0xde, 0x61, 0xf9, 0xf9, 0xb4, 0xc5, 0xe7, ++ 0xb2, 0x6e, 0xf7, 0xc3, 0x29, 0x59, 0x13, 0x5d, 0x8d, 0x13, 0xd9, 0xf5, ++ 0xea, 0x29, 0xcd, 0xc0, 0x6d, 0xb9, 0xb5, 0x58, 0xbe, 0x5b, 0xd6, 0xae, ++ 0xe2, 0x38, 0x90, 0x0c, 0x4d, 0x3f, 0x8b, 0xb5, 0x88, 0x1d, 0x5c, 0x87, ++ 0x2b, 0x77, 0x2b, 0xf8, 0x38, 0xbc, 0x0e, 0x57, 0xf0, 0x7b, 0xe3, 0x6e, ++ 0xdb, 0x3e, 0x6a, 0xb4, 0xda, 0x83, 0xeb, 0x44, 0x57, 0xe2, 0xbb, 0xff, ++ 0xa2, 0xa1, 0x6a, 0x1d, 0xe8, 0x4c, 0x5e, 0xb7, 0x49, 0x3c, 0x4e, 0xae, ++ 0xc5, 0xe2, 0xdd, 0x0d, 0x5a, 0x3b, 0x1a, 0x46, 0x4e, 0xb2, 0x7e, 0xcb, ++ 0x41, 0x95, 0x36, 0x21, 0x65, 0x65, 0x9c, 0xfb, 0x6b, 0xe4, 0x37, 0x06, ++ 0x4a, 0x29, 0x5b, 0x64, 0x4c, 0xf2, 0xdd, 0x3e, 0xa8, 0xd1, 0x7a, 0x5c, ++ 0xef, 0xbf, 0x14, 0xd9, 0x3d, 0xf4, 0xac, 0x14, 0xa6, 0x2b, 0x18, 0xff, ++ 0xdb, 0xa3, 0x7a, 0xc7, 0x0e, 0x45, 0xd6, 0xd2, 0x12, 0x78, 0x3e, 0x19, ++ 0x8e, 0xe8, 0x8a, 0xbd, 0x7c, 0xc2, 0x68, 0x1a, 0xda, 0x4e, 0xf3, 0x0a, ++ 0xd6, 0x5e, 0x8a, 0x03, 0x93, 0x72, 0x16, 0xa4, 0x0b, 0x51, 0xc6, 0xea, ++ 0xad, 0x69, 0xeb, 0x8b, 0x6e, 0xe6, 0x21, 0xa5, 0x7a, 0x28, 0xb0, 0x48, ++ 0x0d, 0x9d, 0xe9, 0x86, 0x7e, 0xfc, 0x1d, 0xf2, 0x84, 0x5f, 0x2c, 0x95, ++ 0xdf, 0x4b, 0xa8, 0xa2, 0xfd, 0x37, 0x63, 0xc1, 0x54, 0xa8, 0xfb, 0x13, ++ 0xa5, 0x12, 0xf9, 0x51, 0x37, 0x5e, 0x5b, 0x56, 0x89, 0xa7, 0xf6, 0xd5, ++ 0x56, 0xcb, 0xb9, 0xe2, 0x5a, 0x9d, 0x06, 0xab, 0xff, 0x29, 0x3b, 0xed, ++ 0xb2, 0x83, 0x75, 0x62, 0xa3, 0x5f, 0x95, 0x31, 0x38, 0xf6, 0xba, 0x9d, ++ 0x76, 0x70, 0x62, 0x24, 0x88, 0x70, 0xf4, 0x11, 0x25, 0x53, 0x78, 0x77, ++ 0x8b, 0x79, 0x82, 0x85, 0x24, 0x39, 0xe2, 0x8e, 0xd1, 0x20, 0xe3, 0x8c, ++ 0xf8, 0x95, 0x42, 0x0c, 0xaf, 0x46, 0xbc, 0x26, 0xe8, 0xf0, 0xff, 0xd7, ++ 0x92, 0x09, 0xa4, 0x92, 0x4d, 0xdd, 0x55, 0xaa, 0x4b, 0xce, 0xdf, 0xc7, ++ 0xa0, 0x26, 0x30, 0x98, 0x2c, 0xd4, 0xeb, 0x6f, 0xed, 0xc1, 0xd7, 0x92, ++ 0x4d, 0xbd, 0x9f, 0xc0, 0xf9, 0x5d, 0x80, 0xe0, 0x0c, 0x7a, 0xb0, 0x29, ++ 0x29, 0xef, 0x2f, 0x88, 0x8d, 0x5b, 0x38, 0xd5, 0xea, 0xc7, 0x4f, 0x93, ++ 0x3d, 0x78, 0x36, 0xd9, 0x34, 0xbd, 0xdc, 0x25, 0xdc, 0x33, 0x14, 0x0c, ++ 0xba, 0x7a, 0x30, 0x91, 0x6c, 0x08, 0x8c, 0xd1, 0x11, 0x13, 0x5a, 0x04, ++ 0xfb, 0xa7, 0x98, 0xb1, 0x90, 0xfb, 0x1d, 0x22, 0x7f, 0x3b, 0x90, 0x6e, ++ 0xd2, 0xee, 0x56, 0xff, 0x46, 0xf6, 0x97, 0x02, 0xf2, 0x33, 0x43, 0x47, ++ 0x93, 0x3e, 0xfa, 0xbb, 0x85, 0x00, 0x73, 0x0e, 0x3d, 0xdf, 0x8a, 0x57, ++ 0x92, 0x8f, 0xdb, 0x9a, 0x19, 0x4e, 0x9c, 0x51, 0xdc, 0xb8, 0x22, 0xbf, ++ 0x1c, 0x2f, 0x12, 0x2f, 0x2b, 0xaf, 0x92, 0xdc, 0x22, 0xc8, 0xf4, 0xff, ++ 0x17, 0x76, 0x09, 0xf3, 0x8d, 0xa6, 0x71, 0xf9, 0xdd, 0x19, 0xdb, 0x3e, ++ 0xd6, 0xaa, 0xc7, 0x4f, 0xd1, 0xcf, 0x55, 0x33, 0x49, 0xee, 0x1c, 0x0e, ++ 0xaa, 0x8a, 0x8f, 0x6d, 0xf8, 0xf1, 0x66, 0x32, 0x80, 0x60, 0x3e, 0x82, ++ 0x29, 0x72, 0x95, 0x06, 0xe6, 0x0c, 0x67, 0x92, 0xbf, 0xb5, 0x17, 0x12, ++ 0xcf, 0x3e, 0xbd, 0xba, 0x1e, 0xb1, 0xbc, 0xec, 0xf7, 0xea, 0xdd, 0x8f, ++ 0x31, 0xa6, 0x7d, 0x89, 0xb1, 0x4b, 0xf6, 0x7b, 0x3f, 0xa4, 0x0c, 0x97, ++ 0x93, 0xd7, 0x06, 0x0f, 0x7e, 0x9e, 0x9f, 0x66, 0x18, 0xf9, 0x20, 0x9a, ++ 0x59, 0x3f, 0xc8, 0xb6, 0x3e, 0x48, 0x46, 0xf0, 0x64, 0xba, 0xa1, 0xe3, ++ 0x6b, 0x4a, 0x03, 0x73, 0xe0, 0x1a, 0xe6, 0xf7, 0x1a, 0x63, 0xf2, 0xb5, ++ 0x38, 0x3d, 0xe2, 0x46, 0x73, 0x0a, 0x62, 0x13, 0xf7, 0x69, 0xc4, 0xd9, ++ 0x61, 0x45, 0xf6, 0xb8, 0x9a, 0x0c, 0xe2, 0x4c, 0x47, 0x1b, 0xf3, 0xd7, ++ 0x46, 0x45, 0xb8, 0x32, 0x10, 0x61, 0xd9, 0x37, 0x47, 0xca, 0xd1, 0x30, ++ 0x9e, 0x24, 0xff, 0x2f, 0xc1, 0xa7, 0x7b, 0xbc, 0xb8, 0xe6, 0xa0, 0xee, ++ 0xe4, 0x6b, 0xaa, 0x2e, 0x7e, 0x00, 0xb4, 0xed, 0xb3, 0x70, 0xa2, 0xf5, ++ 0x4e, 0x84, 0x77, 0xc9, 0x7b, 0x1f, 0x12, 0x4f, 0xe5, 0xdc, 0xbe, 0xf0, ++ 0x23, 0x9d, 0x3a, 0xd3, 0xb1, 0x3f, 0x6d, 0xfd, 0x56, 0xe5, 0xdc, 0x6e, ++ 0x4b, 0xa3, 0x8d, 0x39, 0x30, 0x71, 0x2e, 0x3c, 0xad, 0xbb, 0xdc, 0x08, ++ 0xe4, 0x85, 0x5f, 0xc4, 0x30, 0xc5, 0xf1, 0xa6, 0xc9, 0xc5, 0xf3, 0xc9, ++ 0x7a, 0xa4, 0xc8, 0xc5, 0x2d, 0x72, 0x71, 0x8b, 0xbc, 0xdb, 0x22, 0x17, ++ 0xb7, 0xc8, 0xc5, 0x2d, 0x72, 0x71, 0x8b, 0x5c, 0xdc, 0xca, 0x2e, 0xc7, ++ 0xe4, 0x88, 0x8a, 0xc1, 0x89, 0xa4, 0x12, 0x5f, 0x2b, 0xf6, 0x1d, 0xc1, ++ 0xb7, 0x29, 0x47, 0x62, 0xcd, 0xb5, 0x18, 0x1f, 0xb9, 0x8e, 0x1f, 0x05, ++ 0xab, 0x69, 0x73, 0xc9, 0x8c, 0xb4, 0xeb, 0xc5, 0x58, 0xb6, 0x90, 0xd7, ++ 0x68, 0x57, 0x6f, 0x41, 0x35, 0x73, 0xa3, 0x8f, 0xc9, 0x07, 0xa6, 0xe7, ++ 0xcb, 0x19, 0x4a, 0x83, 0x1f, 0x91, 0x47, 0xf6, 0xf0, 0x2c, 0x94, 0x2d, ++ 0x03, 0xf6, 0x8f, 0x6c, 0x41, 0x64, 0xd4, 0x85, 0xf5, 0x2d, 0x06, 0xfa, ++ 0x33, 0x32, 0x56, 0x19, 0x87, 0xec, 0x29, 0x2a, 0x38, 0xf3, 0x68, 0x43, ++ 0xef, 0x63, 0xc0, 0x74, 0x25, 0xf3, 0xa5, 0x00, 0x39, 0xcc, 0x63, 0xe9, ++ 0x24, 0x73, 0x10, 0x17, 0x4e, 0x45, 0x5b, 0xd0, 0xbc, 0xa7, 0x16, 0x2f, ++ 0xee, 0x0a, 0x75, 0x7c, 0x02, 0x9d, 0x9c, 0xdb, 0x5e, 0xbe, 0x21, 0x1a, ++ 0x36, 0xda, 0x94, 0x16, 0x34, 0x4e, 0xb6, 0xa0, 0xe1, 0xd1, 0x50, 0x2c, ++ 0x4c, 0x3d, 0x7a, 0xa3, 0xcb, 0xd1, 0x67, 0xc4, 0xf1, 0x16, 0x39, 0x97, ++ 0xbe, 0x5f, 0x7e, 0xa7, 0x48, 0xf8, 0x4d, 0x28, 0xf6, 0x2e, 0x24, 0x8f, ++ 0x69, 0xc5, 0x64, 0x16, 0xca, 0x8e, 0x65, 0xd3, 0xd8, 0x30, 0xac, 0xa0, ++ 0xfd, 0x0a, 0xe1, 0x6d, 0x82, 0x4f, 0x26, 0x9e, 0x1c, 0x89, 0x9f, 0x70, ++ 0x33, 0xb6, 0xaf, 0x22, 0x17, 0x3b, 0x98, 0x91, 0x7c, 0xec, 0x59, 0xf2, ++ 0x77, 0x13, 0x8b, 0x47, 0xc5, 0x6e, 0x4c, 0x44, 0xc8, 0xcf, 0xd2, 0xc4, ++ 0x48, 0x7b, 0x54, 0x9f, 0xa6, 0x4e, 0xad, 0x05, 0x2e, 0x13, 0xa7, 0xf7, ++ 0x25, 0xb1, 0x23, 0x2d, 0xf3, 0x13, 0xc4, 0x5f, 0x0c, 0xc7, 0x71, 0x4b, ++ 0x4e, 0xc7, 0x57, 0x87, 0xdb, 0x71, 0x73, 0x2e, 0x82, 0xcd, 0xc3, 0x1d, ++ 0x58, 0x9d, 0x6b, 0x66, 0x3f, 0xc2, 0x4b, 0x56, 0xa3, 0x2d, 0x17, 0xc4, ++ 0xc1, 0xb4, 0x9c, 0x15, 0xa8, 0xc1, 0x0b, 0x5a, 0x90, 0xf3, 0xd4, 0x44, ++ 0xa2, 0xd5, 0x60, 0xb9, 0xa1, 0xef, 0xed, 0x51, 0x43, 0x56, 0x02, 0xa1, ++ 0x91, 0x04, 0x6e, 0x77, 0xf0, 0x45, 0x03, 0xd9, 0xc6, 0x6e, 0x87, 0xbb, ++ 0x4b, 0x5c, 0xb3, 0x4f, 0x91, 0xb3, 0x4e, 0x4e, 0x66, 0xab, 0xc4, 0xcf, ++ 0x6b, 0x74, 0xa5, 0x56, 0xde, 0xb5, 0xa7, 0x9f, 0x13, 0xd3, 0x0b, 0x39, ++ 0xaa, 0x4e, 0xfd, 0x77, 0x8d, 0x48, 0x4c, 0xec, 0x83, 0x67, 0xa9, 0xe4, ++ 0x6c, 0x41, 0xda, 0x73, 0x04, 0x13, 0xe4, 0xc4, 0xaf, 0xee, 0x2b, 0xd8, ++ 0xc6, 0x08, 0xe5, 0xcc, 0xa5, 0xad, 0x2f, 0xd0, 0xeb, 0xda, 0x2a, 0xcc, ++ 0x70, 0xfc, 0x23, 0x14, 0xfc, 0xa0, 0x82, 0x3a, 0x73, 0xd3, 0x9e, 0x4f, ++ 0x25, 0xa5, 0x8c, 0xbc, 0xa7, 0x84, 0x05, 0xe5, 0xcc, 0x1d, 0x3c, 0xf4, ++ 0xaf, 0x0f, 0x93, 0x76, 0x9f, 0x97, 0xbe, 0xe0, 0x5e, 0x56, 0x0f, 0x5f, ++ 0xfe, 0x3a, 0xbc, 0x37, 0x52, 0x8f, 0x85, 0xcc, 0xd3, 0x03, 0x29, 0x9c, ++ 0x28, 0x83, 0x7a, 0x75, 0x19, 0x42, 0xdd, 0x9f, 0xba, 0xc2, 0xda, 0x3d, ++ 0x68, 0xea, 0xfd, 0x9e, 0x12, 0xea, 0x51, 0x5d, 0xa1, 0xae, 0x57, 0x99, ++ 0x5f, 0x57, 0xd2, 0x8f, 0x2a, 0xe8, 0x2b, 0xc8, 0xd3, 0xcc, 0x59, 0xef, ++ 0xd4, 0x88, 0xf8, 0x97, 0x87, 0x62, 0xf8, 0xe1, 0x39, 0xe8, 0x96, 0xdf, ++ 0xe7, 0x98, 0xf6, 0xe8, 0x7a, 0xd7, 0x5b, 0x4a, 0x1d, 0x7c, 0x07, 0xaf, ++ 0xc3, 0xfb, 0x23, 0xc4, 0x0a, 0xf1, 0x59, 0x3e, 0x7b, 0x7b, 0xe7, 0x22, ++ 0x94, 0xd0, 0xe6, 0x41, 0x7f, 0x7e, 0x93, 0xf6, 0xe7, 0x3a, 0x28, 0xfd, ++ 0x5e, 0x0b, 0x7b, 0xa4, 0xe1, 0xf8, 0x7b, 0x2e, 0x05, 0xb1, 0xc5, 0x8a, ++ 0x63, 0x17, 0x92, 0x47, 0x6b, 0xe4, 0x05, 0x53, 0x39, 0xc3, 0xc9, 0x9f, ++ 0xf7, 0xd2, 0x4e, 0xb6, 0xa6, 0xa1, 0x54, 0x5f, 0xd5, 0x02, 0x1f, 0xed, ++ 0xe4, 0xc6, 0x9d, 0x96, 0xad, 0xe9, 0x7a, 0x2c, 0x4b, 0x5e, 0xb0, 0x2a, ++ 0x1a, 0x0e, 0xbc, 0x4d, 0x4e, 0xee, 0xa2, 0x9d, 0x94, 0x3d, 0x2a, 0xf3, ++ 0x2a, 0xf3, 0xbe, 0x1c, 0xcb, 0xa3, 0x71, 0x7c, 0x4a, 0x3b, 0x59, 0xb0, ++ 0x5f, 0xb8, 0xb9, 0x6d, 0x07, 0xf4, 0x02, 0x3f, 0xff, 0x78, 0x38, 0x86, ++ 0x14, 0xf9, 0xf9, 0x30, 0xf3, 0xf3, 0x71, 0xda, 0xc3, 0xd6, 0x7d, 0x92, ++ 0x6f, 0x9b, 0x94, 0x53, 0x37, 0x56, 0x32, 0xf6, 0xbd, 0x9d, 0x11, 0xbb, ++ 0x34, 0x71, 0xd9, 0xa3, 0xfa, 0x99, 0x06, 0x5e, 0x2f, 0xdf, 0x5f, 0x90, ++ 0x67, 0x21, 0x63, 0xcd, 0xe1, 0x5c, 0x3b, 0xbe, 0x93, 0xeb, 0x60, 0x6e, ++ 0x2f, 0x7c, 0x45, 0xde, 0x17, 0xef, 0x70, 0xe4, 0x1b, 0x4c, 0x0b, 0xde, ++ 0x76, 0x50, 0xa7, 0xba, 0x36, 0xa6, 0x84, 0x3b, 0x6f, 0x42, 0x07, 0xde, ++ 0xcf, 0x5e, 0x87, 0x63, 0x23, 0x8c, 0xe7, 0xf4, 0x81, 0xa1, 0xb4, 0xee, ++ 0xfc, 0x16, 0x4c, 0xd9, 0xae, 0x5b, 0x70, 0xdf, 0x44, 0x02, 0xa7, 0xd2, ++ 0xc1, 0xd9, 0x77, 0x8c, 0xe3, 0xf6, 0x63, 0x9c, 0xcb, 0x7c, 0x3a, 0xfe, ++ 0x2d, 0x15, 0x5b, 0x70, 0xe5, 0xa3, 0xf8, 0x07, 0x72, 0xf1, 0xee, 0x80, ++ 0xaa, 0x92, 0x97, 0x0a, 0x67, 0x7b, 0x52, 0xde, 0xf1, 0x36, 0x5e, 0x56, ++ 0x84, 0x97, 0x31, 0xbf, 0x5f, 0xb6, 0x05, 0xf7, 0x11, 0x6f, 0x96, 0x47, ++ 0x5d, 0x98, 0x99, 0x27, 0xf5, 0xac, 0x04, 0x39, 0xb9, 0xf1, 0x92, 0xac, ++ 0x89, 0xeb, 0x32, 0xc7, 0x2e, 0xbc, 0x10, 0x6d, 0xe8, 0x9a, 0x54, 0x5c, ++ 0xe8, 0x8e, 0xca, 0xbb, 0x94, 0x72, 0x7e, 0x58, 0xb0, 0x25, 0x86, 0xf0, ++ 0x41, 0x38, 0xe7, 0x22, 0xe4, 0xfd, 0x9a, 0xd7, 0x47, 0x8e, 0x3b, 0xf6, ++ 0x14, 0x6e, 0x29, 0xf2, 0xea, 0x0f, 0x6a, 0x65, 0xcd, 0x7c, 0x3f, 0x6d, ++ 0x6b, 0x5b, 0x5a, 0xce, 0xde, 0xb9, 0x10, 0x60, 0x0e, 0x94, 0x99, 0x00, ++ 0xfd, 0xa7, 0x15, 0x3f, 0x4f, 0x96, 0x23, 0x93, 0x49, 0x3a, 0x67, 0x8e, ++ 0x9e, 0xcd, 0x5a, 0x70, 0x9b, 0xb2, 0x7e, 0xe0, 0xc3, 0xe1, 0x8c, 0x8f, ++ 0x58, 0xf3, 0xb8, 0x5d, 0x49, 0x2c, 0x9e, 0xca, 0x84, 0xe3, 0x47, 0x89, ++ 0xc5, 0xdf, 0x5e, 0xf6, 0x0b, 0xbb, 0x86, 0x38, 0xbc, 0x37, 0xad, 0x1b, ++ 0x15, 0xbc, 0xbe, 0xe6, 0x2a, 0x3d, 0xf1, 0x53, 0xf8, 0x90, 0x25, 0x0e, ++ 0xb9, 0xd2, 0xb5, 0x58, 0xb8, 0x67, 0xc8, 0x39, 0x83, 0xb3, 0x9f, 0xd7, ++ 0x65, 0xcc, 0x23, 0x33, 0xd9, 0xa0, 0xb3, 0x36, 0xf0, 0x44, 0x56, 0xd6, ++ 0x08, 0x02, 0x28, 0x4f, 0xdb, 0xcb, 0xdf, 0x5b, 0x6a, 0xd5, 0x94, 0x81, ++ 0x78, 0x4b, 0x9e, 0x5d, 0x9b, 0x0e, 0xf5, 0x5e, 0xcf, 0x38, 0xf5, 0xf1, ++ 0x52, 0x03, 0xdf, 0x21, 0xa6, 0x79, 0xd3, 0x32, 0x3f, 0x47, 0xee, 0xab, ++ 0x86, 0xd5, 0x50, 0x05, 0x59, 0x23, 0x54, 0xe9, 0x37, 0x32, 0xc6, 0x7a, ++ 0x7c, 0x7b, 0xa2, 0x95, 0x32, 0x37, 0xe3, 0x10, 0xf9, 0x48, 0x74, 0xbf, ++ 0x85, 0x9f, 0x12, 0x4b, 0x9b, 0xf7, 0x88, 0x6f, 0xa3, 0x4d, 0x78, 0xec, ++ 0x23, 0xd1, 0x70, 0x6c, 0x05, 0x7d, 0xe2, 0x9d, 0x9c, 0xd8, 0x93, 0xbc, ++ 0x7f, 0x89, 0xe9, 0x1a, 0x62, 0xc4, 0x5d, 0x49, 0xc1, 0xb2, 0x00, 0xec, ++ 0x5c, 0x2b, 0xd6, 0x12, 0x3b, 0x3f, 0x61, 0x7e, 0x39, 0xc3, 0xfc, 0x72, ++ 0x26, 0xe7, 0xc7, 0xcc, 0x81, 0x3a, 0x7e, 0x82, 0xfc, 0x2c, 0xe2, 0x47, ++ 0xe7, 0x3d, 0x15, 0xa7, 0x99, 0x2f, 0x9e, 0xe1, 0xbc, 0xef, 0x70, 0xf0, ++ 0xcb, 0x8b, 0x9e, 0x1c, 0xf0, 0xf2, 0xa8, 0x81, 0xaf, 0xee, 0x2b, 0xcc, ++ 0xf5, 0x80, 0xfc, 0xb6, 0xdc, 0x68, 0x14, 0xdb, 0x68, 0x4b, 0x63, 0xe9, ++ 0x16, 0xac, 0xde, 0xad, 0x77, 0x8e, 0x2a, 0xe1, 0xc0, 0x0d, 0xc4, 0xb3, ++ 0x15, 0xcc, 0x1d, 0xef, 0x22, 0x7f, 0x3d, 0xb9, 0xb4, 0x05, 0x6d, 0xe3, ++ 0x5b, 0x10, 0x7b, 0x54, 0x45, 0xf5, 0x52, 0x89, 0xa9, 0x52, 0x4f, 0xf0, ++ 0x54, 0xfc, 0xbe, 0x15, 0x83, 0xc4, 0xb2, 0xb5, 0xad, 0xd3, 0xcc, 0xff, ++ 0x9e, 0xb5, 0xab, 0x74, 0x62, 0x85, 0x1a, 0xc3, 0xe3, 0xc4, 0xb2, 0xbd, ++ 0xcc, 0x09, 0xaa, 0x97, 0x9a, 0x48, 0x67, 0x24, 0x07, 0x34, 0x51, 0x39, ++ 0x2a, 0xf9, 0x9f, 0x89, 0x8a, 0x7d, 0xb2, 0x7e, 0x65, 0x72, 0x6e, 0x83, ++ 0xb8, 0xe6, 0x2a, 0x13, 0x3f, 0xcd, 0x08, 0x1f, 0x10, 0x7c, 0x14, 0xcc, ++ 0x09, 0x62, 0xf5, 0xb0, 0xec, 0x53, 0xe9, 0x58, 0x41, 0x0c, 0xdb, 0x9f, ++ 0x8d, 0xe0, 0x06, 0x62, 0xd8, 0x13, 0xd9, 0x66, 0x5c, 0x3f, 0xbc, 0x9a, ++ 0xb8, 0xe9, 0xd8, 0x01, 0x7d, 0xee, 0xcb, 0x35, 0x85, 0xfc, 0x6a, 0x2d, ++ 0x5e, 0xde, 0x29, 0xef, 0x66, 0xe8, 0xf8, 0xca, 0x70, 0x68, 0xe8, 0xab, ++ 0xca, 0x5a, 0xbc, 0x3e, 0x51, 0xe4, 0x47, 0x0a, 0x06, 0x33, 0x85, 0x31, ++ 0x56, 0xd2, 0x46, 0x86, 0xb3, 0x19, 0xda, 0x8e, 0x13, 0x1f, 0xe8, 0xd1, ++ 0x7d, 0xf3, 0xe4, 0x9c, 0xc3, 0x8f, 0x30, 0xe3, 0xe4, 0x45, 0x95, 0x66, ++ 0x71, 0x8f, 0xb5, 0xb8, 0xf7, 0x62, 0xe1, 0x3b, 0xcb, 0x02, 0x58, 0x4d, ++ 0x5e, 0x7f, 0x68, 0x59, 0x09, 0x6e, 0xda, 0xdd, 0x89, 0xc9, 0x5d, 0x1f, ++ 0xa2, 0x6c, 0x54, 0xbd, 0xdd, 0x87, 0x86, 0xc8, 0xbd, 0x4a, 0x1f, 0x56, ++ 0x44, 0xe5, 0x3d, 0x28, 0xd9, 0x37, 0x18, 0x41, 0xff, 0x7e, 0xe2, 0xe4, ++ 0xd4, 0x25, 0x38, 0x42, 0x6e, 0xfc, 0x94, 0xf1, 0x21, 0x4a, 0x46, 0x3d, ++ 0xce, 0x79, 0xc8, 0x23, 0xc6, 0x52, 0xac, 0x9d, 0x3d, 0x0f, 0x89, 0xba, ++ 0x0b, 0xf7, 0x53, 0xe0, 0xab, 0x9c, 0xfd, 0xfd, 0x87, 0xc2, 0xbb, 0x4f, ++ 0xf4, 0xdf, 0xdc, 0x29, 0xad, 0x70, 0x3e, 0xea, 0x3f, 0x52, 0xb6, 0x17, ++ 0x5d, 0xcc, 0x5d, 0xd7, 0xec, 0xfe, 0x26, 0x6e, 0x19, 0x6b, 0xec, 0x8d, ++ 0xa9, 0xb6, 0xfd, 0x6e, 0x74, 0x1a, 0x47, 0xa3, 0x65, 0xb0, 0xfc, 0xc4, ++ 0xe8, 0xcb, 0xaf, 0x96, 0xd7, 0x6d, 0xf9, 0x77, 0xd2, 0x0e, 0xde, 0x2e, ++ 0xed, 0xfd, 0xbf, 0xd5, 0x05, 0x1f, 0xba, 0xde, 0x2f, 0x67, 0x8a, 0x9e, ++ 0x4d, 0xff, 0x8c, 0x5c, 0x4c, 0xae, 0x8b, 0xf7, 0xdf, 0x60, 0x2e, 0x20, ++ 0xf7, 0x17, 0xcd, 0xd6, 0xfb, 0xe6, 0xec, 0xfc, 0x7f, 0x93, 0xf3, 0x7f, ++ 0xae, 0x0e, 0xb1, 0x41, 0xf6, 0xe7, 0xe4, 0x1d, 0x1f, 0x59, 0xcf, 0x90, ++ 0xfd, 0x3a, 0xd9, 0x43, 0xfa, 0x3a, 0xfa, 0xf7, 0xc8, 0xfa, 0xae, 0x6d, ++ 0xdf, 0xad, 0xcb, 0x3e, 0x67, 0xf1, 0xec, 0xa0, 0xb4, 0x63, 0x29, 0x56, ++ 0x56, 0xea, 0x0e, 0x28, 0x23, 0xd9, 0xb9, 0x63, 0x9a, 0x27, 0xbf, 0x7b, ++ 0xa8, 0x55, 0x98, 0x73, 0xc7, 0x36, 0xa4, 0x0c, 0x66, 0x0f, 0x2b, 0x3b, ++ 0xb2, 0x17, 0xea, 0xe3, 0x69, 0x3b, 0xde, 0x29, 0x6d, 0x88, 0x4c, 0x0f, ++ 0x52, 0x16, 0x91, 0xab, 0xf8, 0xec, 0xc9, 0x59, 0xb9, 0x4b, 0xc9, 0x65, ++ 0x0b, 0x72, 0xaf, 0xa7, 0xdc, 0xc6, 0xd2, 0x38, 0xd4, 0xab, 0xe6, 0xca, ++ 0x5e, 0x1c, 0xe7, 0x5f, 0x9f, 0x6b, 0xab, 0x50, 0x6e, 0x3f, 0x9f, 0x4b, ++ 0xd9, 0xb9, 0xfb, 0x16, 0x25, 0xf0, 0x98, 0x61, 0x6d, 0x9b, 0xb3, 0x5f, ++ 0x60, 0x60, 0xc3, 0x67, 0xf3, 0x06, 0xc1, 0x27, 0x4c, 0x26, 0x35, 0xbc, ++ 0x6d, 0x9c, 0xb5, 0xa7, 0x67, 0xcf, 0x25, 0x7f, 0x9b, 0x79, 0xc8, 0x93, ++ 0xc9, 0x50, 0xc7, 0x26, 0xa5, 0x29, 0xbe, 0x84, 0xbe, 0x2b, 0xbf, 0xb5, ++ 0x23, 0x78, 0x26, 0xbf, 0x67, 0x96, 0x0d, 0xc7, 0x68, 0xd3, 0x26, 0x5e, ++ 0x4d, 0x86, 0x7a, 0xde, 0x52, 0x0a, 0xbf, 0x93, 0xf6, 0x8a, 0xf3, 0x4e, ++ 0x4b, 0xd1, 0xee, 0x22, 0xf2, 0x9b, 0x59, 0x73, 0xd6, 0x0b, 0xc5, 0x06, ++ 0x43, 0x23, 0x19, 0xc6, 0xe0, 0x8c, 0x5f, 0xf6, 0x09, 0x22, 0xc2, 0xcb, ++ 0x03, 0x2a, 0xae, 0x66, 0x0e, 0x2c, 0xfb, 0x44, 0x4f, 0xcf, 0xfe, 0x0e, ++ 0x0e, 0xeb, 0xfd, 0x89, 0xf5, 0x2e, 0xf9, 0x8d, 0xb1, 0x82, 0xbd, 0x44, ++ 0x60, 0x4d, 0x31, 0x67, 0xd7, 0x0a, 0x79, 0xe4, 0x3c, 0xea, 0xda, 0xaf, ++ 0x9f, 0xe6, 0xb8, 0x3d, 0xcc, 0x5d, 0xdc, 0x88, 0x36, 0xca, 0xef, 0x6e, ++ 0x5c, 0x44, 0x7e, 0x1d, 0xd2, 0xe2, 0x6a, 0x84, 0xfe, 0x0a, 0x94, 0xa6, ++ 0xe4, 0x6c, 0x8e, 0xd5, 0xe1, 0x45, 0x28, 0xb0, 0x54, 0x51, 0x50, 0x12, ++ 0x86, 0xfb, 0xde, 0xac, 0x1b, 0x5a, 0xe3, 0xaf, 0xec, 0x1f, 0xfb, 0x23, ++ 0xd8, 0x3e, 0x55, 0x94, 0xc1, 0xc0, 0x5f, 0xe6, 0x2f, 0xcc, 0xa2, 0x8a, ++ 0x6d, 0x7e, 0x68, 0xc7, 0xe7, 0x4b, 0xdf, 0x85, 0x76, 0xff, 0xb8, 0xac, ++ 0xc5, 0xf7, 0x5d, 0x1a, 0x18, 0x70, 0xaa, 0xb1, 0xcd, 0xf8, 0xa9, 0x5f, ++ 0xce, 0x0b, 0xde, 0x0d, 0xd9, 0x03, 0x90, 0x39, 0x90, 0x77, 0x30, 0x63, ++ 0xcc, 0xe1, 0x45, 0x2f, 0x26, 0xee, 0xc9, 0xca, 0x3b, 0x5f, 0x8c, 0xd1, ++ 0x9c, 0x9b, 0x7b, 0xb2, 0x05, 0xfd, 0x3d, 0x90, 0xf5, 0x11, 0x17, 0x7c, ++ 0xb4, 0xc1, 0x1e, 0xe6, 0x60, 0x3a, 0xf5, 0x59, 0xd4, 0xe5, 0x0f, 0xfd, ++ 0xf2, 0xbb, 0x37, 0xdf, 0xa1, 0x4f, 0xbb, 0x1b, 0xe5, 0xbb, 0x25, 0x67, ++ 0x67, 0x95, 0xc2, 0xf7, 0xd3, 0xce, 0xbb, 0xa3, 0xaa, 0xb9, 0x09, 0x6d, ++ 0xc9, 0x79, 0x92, 0xeb, 0x5b, 0xa2, 0x1f, 0xbf, 0x29, 0xef, 0xa2, 0xf8, ++ 0x18, 0x3b, 0x49, 0xa8, 0x0b, 0xef, 0xa4, 0x75, 0xac, 0x21, 0x2f, 0x5b, ++ 0x12, 0xd5, 0xe3, 0x4b, 0x95, 0x50, 0x70, 0xad, 0xd2, 0xc9, 0x7a, 0xd4, ++ 0x53, 0x5e, 0xda, 0x28, 0xfe, 0x2e, 0xda, 0x26, 0xe6, 0x78, 0x4d, 0x41, ++ 0x8f, 0xfa, 0x89, 0x6d, 0x39, 0xe7, 0x40, 0x8b, 0xf9, 0xd6, 0x7c, 0x72, ++ 0xf0, 0x0b, 0xdb, 0x85, 0x77, 0x01, 0xf3, 0xad, 0x6b, 0xd2, 0xd6, 0x3f, ++ 0x68, 0xcc, 0xe3, 0x3c, 0x7a, 0xa8, 0x37, 0xea, 0x0a, 0x75, 0x9f, 0x21, ++ 0xae, 0xe4, 0xa3, 0x7a, 0xe2, 0xbb, 0xec, 0xe3, 0x47, 0x4a, 0x04, 0xc9, ++ 0x39, 0xed, 0x17, 0xda, 0x6a, 0xea, 0x2a, 0x51, 0x4f, 0x3b, 0xbf, 0x55, ++ 0x20, 0xed, 0x6b, 0xe6, 0x9d, 0xd0, 0x52, 0x96, 0xed, 0x67, 0x9b, 0x0b, ++ 0xcd, 0xd0, 0xde, 0x1a, 0x82, 0xd1, 0x83, 0x6a, 0x1f, 0x36, 0xc8, 0x11, ++ 0x19, 0x33, 0x14, 0xbc, 0x8b, 0xf6, 0xd1, 0xe2, 0xb4, 0x11, 0x8f, 0x94, ++ 0x80, 0x3a, 0xf9, 0xc3, 0x76, 0x12, 0x04, 0x64, 0x0d, 0x96, 0xe5, 0x9c, ++ 0x35, 0x6d, 0xd3, 0xe1, 0x00, 0x1b, 0x92, 0xf2, 0x1b, 0x8c, 0x85, 0x75, ++ 0x89, 0xc2, 0xbe, 0x9e, 0xc6, 0x3c, 0xca, 0x8b, 0xbb, 0xe5, 0x37, 0xad, ++ 0xca, 0x7d, 0xb8, 0x27, 0x29, 0xb9, 0xf4, 0xff, 0x07, 0x95, 0xcd, 0xc7, ++ 0x2c, 0xec, 0x55, 0x00, 0x00, 0x00 }; + + static const u32 bnx2_CP_b09FwData[(0x84/4) + 1] = { + 0x00000000, 0x0000001b, 0x0000000f, 0x0000000a, 0x00000008, 0x00000006, +@@ -2078,1077 +2092,1156 @@ + 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, + 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, + 0x00000001, 0x00000001, 0x00000001, 0x00000000 }; +-static const u32 bnx2_CP_b09FwRodata[(0x16c/4) + 1] = { +- 0x80080100, 0x80080080, 0x80080000, 0x08001744, 0x08001744, 0x0800177c, +- 0x0800177c, 0x08001790, 0x08001760, 0x080019b8, 0x08001984, 0x08001a10, +- 0x08001a10, 0x08001a98, 0x080019c8, 0x80080240, 0x08003260, 0x080031cc, +- 0x08003288, 0x080032b0, 0x080032d8, 0x080032fc, 0x08003344, 0x08003320, +- 0x08003368, 0x08003234, 0x0800345c, 0x0800344c, 0x080031e8, 0x080031e8, +- 0x080031e8, 0x080033bc, 0x080033bc, 0x080031e8, 0x080031e8, 0x0800343c, +- 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x0800342c, 0x080031e8, +- 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, +- 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, +- 0x080031e8, 0x0800341c, 0x080031e8, 0x080031e8, 0x0800340c, 0x080031e8, +- 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, +- 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, +- 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080033f4, 0x080031e8, +- 0x080031e8, 0x080033e4, 0x080033d4, 0x08003d6c, 0x08003d40, 0x08003d0c, +- 0x08003ce0, 0x08003cc0, 0x08003c74, 0x80080100, 0x80080080, 0x80080000, +- 0x80080080, 0x00000000 }; ++static const u32 bnx2_CP_b09FwRodata[(0x1c0/4) + 1] = { ++ 0x80080100, 0x80080080, 0x80080000, 0x00000c00, 0x00003080, 0x08001030, ++ 0x080010dc, 0x080010f4, 0x08001108, 0x0800111c, 0x08001030, 0x08001030, ++ 0x08001150, 0x08001188, 0x08001198, 0x080011c0, 0x080018b0, 0x080018b0, ++ 0x080018e8, 0x080018e8, 0x080018fc, 0x080018cc, 0x08001b24, 0x08001af0, ++ 0x08001b7c, 0x08001b7c, 0x08001c04, 0x08001b34, 0x80080240, 0x08002290, ++ 0x080020dc, 0x080022b8, 0x08002350, 0x080024a0, 0x080024ec, 0x08002610, ++ 0x08002518, 0x0800259c, 0x0800214c, 0x08002ac4, 0x08002a68, 0x080020f8, ++ 0x080020f8, 0x080020f8, 0x08002684, 0x08002684, 0x080020f8, 0x080020f8, ++ 0x08002940, 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, 0x080029a0, ++ 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, ++ 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, ++ 0x080020f8, 0x080020f8, 0x0800250c, 0x080020f8, 0x080020f8, 0x08002a10, ++ 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, ++ 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, ++ 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, 0x080020f8, 0x08002864, ++ 0x080020f8, 0x080020f8, 0x080027cc, 0x08002728, 0x0800388c, 0x08003860, ++ 0x0800382c, 0x08003800, 0x080037e0, 0x08003794, 0x80080100, 0x80080080, ++ 0x80080000, 0x80080080, 0x080047f4, 0x0800482c, 0x08004774, 0x080047f4, ++ 0x080047f4, 0x08004554, 0x080047f4, 0x08004bc8, 0x00000000 }; + + static struct fw_info bnx2_cp_fw_09 = { +- /* Firmware version: 4.4.23 */ +- .ver_major = 0x4, +- .ver_minor = 0x4, +- .ver_fix = 0x17, +- +- .start_addr = 0x08000080, ++ /* Firmware version: 5.0.0j */ ++ .ver_major = 0x5, ++ .ver_minor = 0x0, ++ .ver_fix = 0x0, ++ ++ .start_addr = 0x08000088, + + .text_addr = 0x08000000, +- .text_len = 0x5938, ++ .text_len = 0x55e8, + .text_index = 0x0, + .gz_text = bnx2_CP_b09FwText, + .gz_text_len = sizeof(bnx2_CP_b09FwText), + +- .data_addr = 0x08005ac0, ++ .data_addr = 0x080057c0, + .data_len = 0x84, + .data_index = 0x0, + .data = bnx2_CP_b09FwData, + +- .sbss_addr = 0x08005b44, ++ .sbss_addr = 0x08005844, + .sbss_len = 0x91, + .sbss_index = 0x0, + +- .bss_addr = 0x08005bd8, ++ .bss_addr = 0x080058d8, + .bss_len = 0x19c, + .bss_index = 0x0, + +- .rodata_addr = 0x08005938, +- .rodata_len = 0x16c, ++ .rodata_addr = 0x080055e8, ++ .rodata_len = 0x1c0, + .rodata_index = 0x0, + .rodata = bnx2_CP_b09FwRodata, + }; + + static u8 bnx2_RXP_b09FwText[] = { +- 0xec, 0x5c, 0x7f, 0x70, 0x1c, 0xd5, 0x7d, 0xff, 0xbc, 0xbd, 0xbd, 0xbb, +- 0x95, 0x74, 0x3e, 0xed, 0x9d, 0x4e, 0xb2, 0x04, 0x06, 0xef, 0xa2, 0x95, +- 0x74, 0x58, 0xc6, 0xec, 0x9d, 0x4e, 0xb6, 0x48, 0xb7, 0xc9, 0xd5, 0x36, +- 0x20, 0x17, 0x52, 0x84, 0xa1, 0xc1, 0xcc, 0x30, 0x9d, 0x1b, 0x63, 0x8c, +- 0xb0, 0x1d, 0xa2, 0x00, 0x33, 0xc8, 0x29, 0x13, 0x16, 0xfc, 0xb3, 0xf8, +- 0xa4, 0x93, 0x8d, 0x8c, 0xc9, 0xf4, 0xd7, 0x21, 0xcb, 0x8a, 0x81, 0x93, +- 0xce, 0x04, 0xda, 0x98, 0x69, 0xa8, 0x15, 0x6c, 0x53, 0x87, 0x5f, 0x21, +- 0x19, 0x68, 0x4d, 0x9b, 0x99, 0xa8, 0x06, 0x1c, 0xd3, 0xa6, 0xd4, 0xb4, +- 0x0e, 0xb5, 0x8b, 0xeb, 0xd7, 0xef, 0x77, 0x4f, 0x97, 0x50, 0x42, 0xcb, +- 0x64, 0xa6, 0x7f, 0xee, 0x77, 0xe6, 0xe6, 0xf6, 0xde, 0xfb, 0xbe, 0xef, +- 0x7b, 0xdf, 0xdf, 0x9f, 0xb7, 0x1a, 0xfb, 0xbe, 0x08, 0x6a, 0x31, 0x4b, +- 0x73, 0xe8, 0x93, 0x19, 0x18, 0xbc, 0x27, 0xbd, 0x28, 0xb3, 0x88, 0x1e, +- 0xbb, 0x02, 0x73, 0x55, 0x95, 0xc7, 0x05, 0x7c, 0xf2, 0xc9, 0x27, 0x9f, +- 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xf2, +- 0xc9, 0x27, 0x9f, 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xf2, 0xc9, 0x27, +- 0x9f, 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c, +- 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xf2, 0xc9, +- 0x27, 0x9f, 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xfa, 0xff, 0xa4, 0x00, +- 0xa0, 0xf3, 0xf7, 0x9c, 0xd9, 0x0f, 0x34, 0xc5, 0x71, 0x37, 0x2e, 0xb5, +- 0xa0, 0x05, 0x9c, 0x33, 0x1b, 0x6f, 0xb7, 0x80, 0x6c, 0xa9, 0xd3, 0x58, +- 0x86, 0xff, 0x92, 0x6e, 0x42, 0x05, 0x8f, 0x5f, 0xe2, 0x9c, 0xff, 0xf3, +- 0x17, 0x96, 0x98, 0xa7, 0x8b, 0x01, 0x68, 0xba, 0xf3, 0x46, 0x4a, 0x6f, +- 0x87, 0x36, 0x8f, 0xd6, 0xfc, 0x49, 0xc7, 0x95, 0x71, 0x44, 0xab, 0xb2, +- 0xe0, 0x2a, 0x8e, 0x94, 0xfb, 0x6c, 0x89, 0x97, 0x6c, 0x57, 0xf4, 0x66, +- 0xe0, 0x06, 0x9c, 0x83, 0xe2, 0xae, 0xfc, 0x05, 0x69, 0x04, 0x2b, 0x3b, +- 0xab, 0x93, 0x1a, 0x82, 0xfb, 0xa0, 0xab, 0x8e, 0x82, 0xa0, 0x55, 0x8b, +- 0xd0, 0x13, 0x75, 0x08, 0x3e, 0xd1, 0x8c, 0xf0, 0xe4, 0x01, 0x91, 0x2b, +- 0x6a, 0x98, 0x09, 0x1c, 0x14, 0x6b, 0x4a, 0xc8, 0x05, 0x9d, 0xb3, 0x37, +- 0x8c, 0xd1, 0xba, 0xac, 0xf7, 0xef, 0x4b, 0xa6, 0x6f, 0x18, 0x2f, 0x41, +- 0x0f, 0x38, 0x50, 0x54, 0xe7, 0x08, 0x3d, 0x33, 0xdf, 0xd9, 0x1b, 0xf6, +- 0x96, 0x4e, 0xc9, 0x17, 0x3a, 0x12, 0x38, 0x54, 0xd6, 0x71, 0xa0, 0xfc, +- 0x10, 0x9d, 0xc3, 0x74, 0x5d, 0x68, 0xae, 0xea, 0xb8, 0xd8, 0x92, 0x09, +- 0x62, 0x62, 0xe4, 0x82, 0x0c, 0x58, 0xa6, 0x01, 0xc5, 0xd2, 0x0f, 0x83, +- 0xf8, 0x0a, 0xc4, 0x57, 0x08, 0x62, 0xac, 0xb8, 0x23, 0x8e, 0xda, 0x66, +- 0xbc, 0xd0, 0xc1, 0xeb, 0x79, 0x2d, 0xcb, 0xf8, 0x38, 0x5a, 0x5d, 0x1f, +- 0xa2, 0xf5, 0x47, 0x33, 0xc0, 0xf8, 0x48, 0x1f, 0x2d, 0x95, 0xd8, 0x64, +- 0x87, 0xb1, 0x5a, 0x87, 0x5b, 0xe3, 0xb0, 0xac, 0xaa, 0x1c, 0x57, 0x18, +- 0x93, 0xff, 0x5c, 0x5f, 0x91, 0x03, 0xa1, 0x59, 0x70, 0xc3, 0x9f, 0x9a, +- 0x3f, 0x55, 0xaa, 0xce, 0x6f, 0xa7, 0x7d, 0x34, 0x9a, 0xef, 0xc7, 0x5f, +- 0x96, 0xd7, 0xe0, 0x2f, 0xca, 0xb7, 0xe1, 0xd9, 0x72, 0x1f, 0xed, 0x7b, +- 0x1f, 0xed, 0x3b, 0x80, 0xbf, 0x2e, 0x6f, 0xc0, 0x77, 0xcb, 0x39, 0x3c, +- 0x57, 0x5e, 0x85, 0xef, 0x94, 0x6f, 0xc6, 0x33, 0x65, 0x78, 0x67, 0x38, +- 0x95, 0x49, 0x8a, 0x1f, 0xe5, 0x6b, 0xa0, 0xee, 0xdc, 0x8c, 0xe9, 0x52, +- 0x10, 0xc1, 0x9d, 0x12, 0x23, 0xb6, 0xf9, 0x38, 0xd0, 0xa1, 0x07, 0x21, +- 0xb0, 0xcc, 0x36, 0xf7, 0x03, 0x5f, 0x40, 0x2e, 0x61, 0x1e, 0x00, 0x9a, +- 0xc4, 0x8f, 0x47, 0x9b, 0xc4, 0x6b, 0xa3, 0xaa, 0x78, 0x3d, 0x2f, 0x50, +- 0xef, 0x20, 0xf2, 0x72, 0x46, 0xca, 0xeb, 0xd2, 0x52, 0x96, 0x52, 0x56, +- 0xef, 0x0f, 0x85, 0x69, 0x3f, 0x22, 0x2e, 0x85, 0xd1, 0x68, 0x66, 0xd7, +- 0x09, 0xcd, 0xad, 0x25, 0xf9, 0x2b, 0xba, 0x01, 0x6b, 0xa7, 0x41, 0x7e, +- 0x60, 0x1d, 0x37, 0xe1, 0x0e, 0x2f, 0x26, 0xfa, 0xd0, 0x60, 0x2d, 0xc5, +- 0xbd, 0x7d, 0x36, 0x8a, 0x65, 0x68, 0x31, 0xe7, 0x0c, 0x52, 0xc3, 0x02, +- 0x36, 0xf9, 0x5b, 0xd0, 0xb3, 0x5d, 0x5a, 0xdf, 0x50, 0xf1, 0x37, 0x9d, +- 0xbd, 0x40, 0x67, 0x2f, 0xd0, 0xd9, 0x0b, 0xa4, 0x57, 0x81, 0xf4, 0x2a, +- 0x90, 0x0e, 0x05, 0xd2, 0xad, 0x40, 0x7a, 0x14, 0x48, 0x8f, 0x02, 0xe9, +- 0x58, 0x60, 0x5f, 0x0d, 0x92, 0x0d, 0x22, 0xf8, 0xbb, 0xfc, 0x3c, 0x9c, +- 0xe1, 0xcf, 0x4a, 0x1d, 0xc7, 0xe9, 0x8c, 0x8a, 0xf5, 0x9b, 0xca, 0xf8, +- 0x6e, 0x84, 0x7c, 0x64, 0xfc, 0xe6, 0x7b, 0x2f, 0xc4, 0xc9, 0xfc, 0xbb, +- 0x32, 0x34, 0x97, 0xf7, 0xfc, 0x22, 0xe4, 0x28, 0x70, 0xe9, 0x6e, 0x29, +- 0xcf, 0x75, 0xcd, 0xc8, 0xb7, 0x6f, 0x61, 0x59, 0x0e, 0x4e, 0x8c, 0x2a, +- 0x08, 0xd0, 0xd8, 0xb5, 0xf6, 0xdf, 0xcb, 0x3b, 0x13, 0xcc, 0xf7, 0x51, +- 0x04, 0xb5, 0x6c, 0x27, 0x68, 0x0d, 0xce, 0xbb, 0x1b, 0xef, 0x6d, 0x87, +- 0x1b, 0x75, 0x54, 0xf1, 0xe6, 0x90, 0x81, 0xb9, 0x4e, 0x16, 0x73, 0x1c, +- 0x6b, 0x64, 0x8f, 0xd2, 0x39, 0x18, 0x47, 0xf6, 0xf2, 0x7a, 0xd8, 0xd8, +- 0x57, 0x56, 0xc5, 0xab, 0x43, 0x73, 0x10, 0xdf, 0x69, 0xad, 0x1a, 0x12, +- 0x0a, 0x72, 0x8d, 0x59, 0x8c, 0x67, 0x4c, 0xa3, 0x08, 0x03, 0xab, 0xd2, +- 0x0a, 0x30, 0xd7, 0xc5, 0xd6, 0x8c, 0x69, 0xbb, 0x78, 0x08, 0xd3, 0x09, +- 0x1b, 0x13, 0x65, 0x8d, 0x72, 0xc3, 0xc5, 0x9d, 0x19, 0x0d, 0x72, 0x24, +- 0x8b, 0x93, 0x5d, 0x21, 0x4c, 0xf7, 0x71, 0x8c, 0xa8, 0xb4, 0xf7, 0x56, +- 0x28, 0xf1, 0x38, 0xf9, 0xe5, 0xb0, 0x0c, 0xc6, 0x79, 0x0c, 0xe2, 0x5f, +- 0x32, 0xbc, 0xff, 0x45, 0xe2, 0xd5, 0xdd, 0x51, 0xd4, 0xee, 0xd6, 0xf0, +- 0xf4, 0x4e, 0x15, 0x2b, 0xc8, 0xb7, 0x7b, 0x52, 0xaa, 0xb1, 0x4e, 0x38, +- 0x18, 0x2f, 0xab, 0x48, 0x0c, 0xb5, 0xc0, 0x88, 0x69, 0xb8, 0x74, 0xc8, +- 0xc5, 0x3b, 0x24, 0x77, 0x90, 0xe4, 0xd6, 0x77, 0xe9, 0x98, 0x69, 0xac, +- 0xf8, 0xf5, 0xeb, 0xf9, 0x56, 0x77, 0xa7, 0x12, 0x02, 0x42, 0x70, 0x35, +- 0x27, 0x83, 0xfb, 0xf3, 0xad, 0xa4, 0xc3, 0xad, 0x58, 0x1a, 0xd2, 0xb0, +- 0x7a, 0x98, 0xc7, 0x96, 0x03, 0x93, 0x73, 0xe7, 0xa0, 0x96, 0xf5, 0xe7, +- 0x7c, 0x5e, 0x4a, 0xcf, 0x1c, 0x07, 0xbf, 0x9d, 0x60, 0xbb, 0xbb, 0xca, +- 0x7f, 0xc8, 0x6c, 0x82, 0xf9, 0x2a, 0x39, 0x72, 0x38, 0x93, 0xc1, 0xc6, +- 0x7c, 0x6b, 0xf6, 0x5b, 0x4a, 0x03, 0x10, 0x34, 0x0d, 0x43, 0x81, 0x96, +- 0x70, 0x90, 0x1a, 0xa5, 0x78, 0x79, 0xd4, 0x8b, 0x17, 0xa4, 0xba, 0x4a, +- 0x9c, 0x97, 0x9a, 0xab, 0x13, 0xff, 0xfc, 0xc5, 0x6d, 0xf8, 0xe8, 0x51, +- 0xe6, 0x53, 0xf1, 0x03, 0x7a, 0x7e, 0x7f, 0xef, 0x8e, 0xd9, 0xda, 0xf1, +- 0xa7, 0x9e, 0x5f, 0x0d, 0xa5, 0xba, 0xb7, 0x8d, 0x3b, 0xf3, 0xad, 0x67, +- 0xb7, 0x29, 0xe4, 0xbf, 0x8b, 0x23, 0xa8, 0xa1, 0xfa, 0x13, 0x24, 0x59, +- 0xfb, 0xf2, 0xe7, 0xb1, 0x32, 0x6d, 0x1e, 0xe4, 0x7f, 0x6f, 0x36, 0x66, +- 0x55, 0xe4, 0x5f, 0x56, 0xb2, 0xf1, 0x64, 0xd9, 0xc6, 0xed, 0x74, 0x8e, +- 0xfb, 0xf0, 0x8f, 0x40, 0xcb, 0x02, 0xe3, 0x94, 0x72, 0x42, 0xba, 0x37, +- 0xb3, 0xbc, 0x79, 0x38, 0x15, 0x6f, 0xcd, 0x9d, 0x52, 0xcc, 0xe2, 0x76, +- 0x85, 0x6d, 0xa5, 0xe0, 0xcb, 0xe9, 0x0c, 0x8a, 0x31, 0x1d, 0xb7, 0xa6, +- 0x35, 0xf7, 0x52, 0x3a, 0xd3, 0x1b, 0x4b, 0x34, 0x34, 0xed, 0xca, 0xe2, +- 0xad, 0xf4, 0x9b, 0x28, 0xae, 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0x0e, 0xef, 0x01, 0x9f, 0xe2, 0x35, 0x56, +- 0x29, 0x1a, 0xae, 0x8e, 0x7b, 0x67, 0x4a, 0xe9, 0x03, 0x37, 0xc6, 0x03, +- 0x98, 0x21, 0xae, 0x26, 0x27, 0xe5, 0xfc, 0xc9, 0x02, 0x0c, 0x4d, 0x7e, +- 0x4d, 0xb8, 0x81, 0x41, 0x4c, 0xb2, 0xce, 0x48, 0x3e, 0x2f, 0xbd, 0x4e, +- 0x67, 0x30, 0xcb, 0x61, 0x0c, 0x65, 0x53, 0x43, 0x09, 0x6e, 0x30, 0x3a, +- 0xfd, 0x6d, 0xba, 0x93, 0xf9, 0x1c, 0xde, 0xa8, 0x81, 0xfd, 0x3b, 0x6e, +- 0xd4, 0x25, 0xe7, 0xe0, 0x44, 0x5d, 0x39, 0xf2, 0x70, 0x6c, 0xf4, 0x45, +- 0x72, 0xfc, 0xee, 0xf6, 0x52, 0xe6, 0xa7, 0x13, 0xa3, 0x4e, 0xa4, 0x52, +- 0x52, 0x73, 0xb0, 0x7a, 0x96, 0xd3, 0x0e, 0xfa, 0x52, 0x7f, 0x02, 0x75, +- 0x35, 0x61, 0x7f, 0xb2, 0xc6, 0xae, 0x72, 0x8e, 0x4a, 0xa4, 0xd2, 0x1a, +- 0x3f, 0x01, 0x7e, 0x82, 0xfc, 0x34, 0xe2, 0xdb, 0xf4, 0xd9, 0x32, 0xe2, +- 0xed, 0xf7, 0xd3, 0x25, 0xf8, 0x24, 0xa9, 0x05, 0x74, 0xda, 0xc1, 0x28, +- 0x73, 0x04, 0xc3, 0xd2, 0x53, 0x09, 0xae, 0xd3, 0x4f, 0x5f, 0x0e, 0x95, +- 0xc0, 0x4c, 0xdd, 0x2d, 0x27, 0x94, 0xdc, 0x16, 0x6a, 0x61, 0x58, 0xf8, +- 0xe2, 0x31, 0x25, 0x95, 0x3d, 0xf3, 0xf5, 0xea, 0x38, 0xda, 0xcb, 0xc3, +- 0xae, 0xe0, 0xea, 0xb8, 0xfd, 0x13, 0x79, 0x9f, 0x75, 0x43, 0x83, 0xbc, +- 0xf3, 0xe4, 0x0a, 0x3e, 0x3d, 0xe1, 0x0a, 0xae, 0x8f, 0x1f, 0x53, 0x28, +- 0xcf, 0x81, 0x1a, 0xbb, 0x2b, 0xf8, 0xe4, 0xc4, 0xb1, 0x85, 0x99, 0xbc, +- 0x0f, 0xca, 0xd3, 0xb5, 0x06, 0x6d, 0x8c, 0x79, 0xef, 0x32, 0xe9, 0xcb, +- 0x68, 0x9d, 0x57, 0xec, 0x85, 0x46, 0x4d, 0xd8, 0xeb, 0xa9, 0xb1, 0xcb, +- 0xd9, 0x90, 0x69, 0xc4, 0x93, 0xf2, 0xae, 0x97, 0xd8, 0xfe, 0x3f, 0x99, +- 0x46, 0x99, 0x9c, 0xf5, 0xe8, 0x44, 0x5c, 0x2b, 0x67, 0xee, 0x24, 0x67, +- 0xcd, 0x8f, 0x86, 0xa2, 0xb1, 0x62, 0x79, 0x77, 0xb6, 0xe9, 0x7b, 0x21, +- 0x6f, 0xcb, 0xa0, 0x62, 0x3c, 0x5e, 0x04, 0xd9, 0xd7, 0x2e, 0xe2, 0xb7, +- 0xa6, 0x3a, 0x15, 0x6f, 0x63, 0x0f, 0x02, 0x38, 0x91, 0x16, 0x5d, 0x07, +- 0xe5, 0x8c, 0xba, 0xa5, 0xeb, 0x5b, 0x67, 0xae, 0x33, 0xb6, 0xb3, 0x2d, +- 0xea, 0xe0, 0x5f, 0xb1, 0x17, 0x1b, 0x63, 0x0a, 0xe3, 0x8a, 0x65, 0x33, +- 0xb7, 0x64, 0x5c, 0x57, 0xdb, 0x85, 0xc9, 0x50, 0xa1, 0xbc, 0x77, 0xcd, +- 0xb8, 0xee, 0x0d, 0x7c, 0xa2, 0x58, 0xf1, 0xdc, 0x28, 0x62, 0x9c, 0x7d, +- 0x61, 0xfc, 0xef, 0xcc, 0xf6, 0x6a, 0xc1, 0x2b, 0x3b, 0xc7, 0x5e, 0xc7, +- 0x6b, 0xa9, 0x5b, 0xe3, 0x5a, 0x38, 0xae, 0x90, 0xe3, 0x8a, 0xc2, 0x92, +- 0x3b, 0x7a, 0xf5, 0xb5, 0x8a, 0xe6, 0x29, 0x50, 0xa4, 0x57, 0xa6, 0xe1, +- 0xbd, 0xf4, 0xe4, 0x42, 0xc9, 0x79, 0x7b, 0x27, 0xcb, 0xb1, 0x6e, 0xaf, +- 0xd9, 0xb4, 0x68, 0xa9, 0xd9, 0x94, 0x0e, 0x45, 0xcd, 0x97, 0xab, 0x64, +- 0x4f, 0xa5, 0xff, 0x27, 0x63, 0x34, 0xd5, 0xc7, 0x5c, 0xf3, 0x6b, 0x7a, +- 0x6f, 0xf6, 0xcc, 0x2e, 0xed, 0x9a, 0xcf, 0x38, 0x9d, 0x12, 0x3b, 0xd9, +- 0xd1, 0xee, 0x62, 0x3e, 0x2a, 0xef, 0x87, 0x1e, 0xe5, 0xfe, 0x1f, 0x49, +- 0xfd, 0xcd, 0x42, 0x39, 0xc3, 0x2e, 0x67, 0x08, 0x80, 0xff, 0x0f, 0x1d, +- 0xab, 0x22, 0x97, 0x70, 0x78, 0x00, 0x00, 0x00 }; ++ 0xec, 0x5c, 0x7d, 0x70, 0x1c, 0xe5, 0x79, 0xff, 0xbd, 0x7b, 0x7b, 0xd2, ++ 0x4a, 0x3a, 0x9d, 0xf6, 0x4e, 0x27, 0xf9, 0x6c, 0x5c, 0xbc, 0x1b, 0xed, ++ 0x49, 0xb2, 0x65, 0xcc, 0xde, 0xe9, 0x64, 0xcb, 0x99, 0x6d, 0xd8, 0x62, ++ 0x9b, 0x88, 0x21, 0x05, 0x19, 0x1b, 0x2a, 0xa6, 0x69, 0x72, 0xe3, 0x6f, ++ 0x30, 0x29, 0x82, 0xd0, 0xd4, 0x24, 0xc6, 0x2c, 0xd8, 0x16, 0xae, 0x39, ++ 0xe9, 0x24, 0x5b, 0x76, 0xe9, 0xc7, 0x90, 0x8b, 0xbe, 0xfc, 0xc1, 0xc9, ++ 0x67, 0x13, 0x1b, 0xcc, 0x1f, 0xd8, 0x57, 0x62, 0xc0, 0x10, 0x8c, 0x61, ++ 0x42, 0x19, 0x67, 0x92, 0x29, 0x2a, 0x14, 0x4c, 0x27, 0x13, 0x70, 0x81, ++ 0xb4, 0xa2, 0x38, 0xda, 0x3e, 0xcf, 0x9d, 0x8f, 0x66, 0x9a, 0x4c, 0x66, ++ 0xf2, 0x47, 0xff, 0xdb, 0x67, 0x46, 0xb3, 0x77, 0xef, 0xbe, 0x1f, 0xcf, ++ 0xc7, 0xef, 0xf9, 0xbd, 0xcf, 0x73, 0x33, 0xf6, 0x77, 0x02, 0xa8, 0xc6, ++ 0x15, 0xa9, 0xa5, 0xbf, 0x8e, 0xde, 0x2d, 0xf7, 0x99, 0x8b, 0xcc, 0x45, ++ 0xf4, 0xf1, 0x2e, 0x1f, 0xe0, 0xe7, 0x71, 0x01, 0x4f, 0x3c, 0xf1, 0xc4, ++ 0x13, 0x4f, 0x3c, 0xf1, 0xc4, 0x13, 0x4f, 0x3c, 0xf1, 0xc4, 0x13, 0x4f, ++ 0x3c, 0xf1, 0xc4, 0x13, 0x4f, 0x3c, 0xf1, 0xc4, 0x13, 0x4f, 0x3c, 0xf1, ++ 0xc4, 0x13, 0x4f, 0x3c, 0xf1, 0xc4, 0x13, 0x4f, 0x3c, 0xf1, 0xc4, 0x13, ++ 0x4f, 0x3c, 0xf1, 0xc4, 0x13, 0x4f, 0x3c, 0xf1, 0xc4, 0x13, 0x4f, 0x3c, ++ 0xf1, 0xc4, 0x13, 0x4f, 0x3c, 0xf1, 0xc4, 0x13, 0x4f, 0xfe, 0x3f, 0xc4, ++ 0x07, 0xa8, 0xfc, 0xac, 0xbd, 0xf2, 0x07, 0x45, 0xb2, 0x52, 0x0f, 0x5e, ++ 0x6f, 0x40, 0xf1, 0x59, 0xda, 0xb6, 0xb5, 0x06, 0x60, 0xe7, 0xda, 0xb4, ++ 0x65, 0xf8, 0xb5, 0xeb, 0x44, 0x64, 0xf0, 0xf8, 0x1f, 0x59, 0x97, 0xbf, ++ 0xff, 0xdc, 0x12, 0xfd, 0x52, 0xd6, 0x07, 0x45, 0xb5, 0x2e, 0xc4, 0xd5, ++ 0x66, 0x28, 0x73, 0x69, 0xcd, 0x3f, 0xb6, 0xfc, 0x22, 0x84, 0x60, 0x79, ++ 0x2f, 0x38, 0x92, 0xe5, 0xba, 0xe3, 0xa6, 0x8b, 0x17, 0x4d, 0x47, 0x2c, ++ 0x4b, 0xc2, 0x51, 0xac, 0x93, 0xa2, 0xaa, 0x7f, 0xc6, 0xd5, 0xfc, 0xa5, ++ 0x93, 0xd7, 0xe5, 0x24, 0xc8, 0x86, 0x82, 0xf5, 0x63, 0xd5, 0xd8, 0x90, ++ 0xad, 0xc1, 0xba, 0x6c, 0x14, 0x1b, 0x73, 0x50, 0x7d, 0x96, 0x82, 0x29, ++ 0xdf, 0x49, 0xe1, 0x9b, 0x44, 0xca, 0x6f, 0x4d, 0xdf, 0x32, 0x92, 0x9e, ++ 0x71, 0x6d, 0x99, 0x57, 0x14, 0x6e, 0x19, 0x2b, 0xbe, 0x87, 0x24, 0x5b, ++ 0x67, 0xe8, 0x33, 0xcf, 0x9b, 0xbe, 0x65, 0x34, 0x17, 0x40, 0xdf, 0xb0, ++ 0xde, 0x9d, 0x45, 0x04, 0xbb, 0x0c, 0xa9, 0xad, 0x02, 0x8e, 0xea, 0x87, ++ 0xde, 0xb5, 0x1c, 0x6d, 0xd1, 0x2a, 0x11, 0x42, 0x4a, 0xbd, 0x62, 0xe9, ++ 0x50, 0x15, 0xd6, 0x2d, 0xac, 0x82, 0xd3, 0x2d, 0x30, 0x7b, 0xc8, 0x49, ++ 0x91, 0xe5, 0x4a, 0xad, 0x65, 0x6c, 0x9d, 0x8c, 0xe9, 0x3d, 0xfd, 0x02, ++ 0xd8, 0xd8, 0x4f, 0xfb, 0x15, 0x67, 0xf2, 0x7b, 0xdd, 0x9e, 0x2d, 0xda, ++ 0xcc, 0x2a, 0xf1, 0xb1, 0x5b, 0x58, 0xcd, 0x6b, 0xf9, 0x2c, 0x9d, 0x76, ++ 0x3a, 0x15, 0x40, 0xb5, 0x80, 0x12, 0x13, 0xa8, 0x1b, 0xaa, 0x46, 0xd0, ++ 0xb0, 0xf1, 0x61, 0x43, 0xd3, 0xd9, 0x56, 0x51, 0x8d, 0xce, 0x6b, 0xff, ++ 0x18, 0x98, 0x25, 0xa1, 0x36, 0x06, 0xf4, 0xf4, 0x57, 0xa0, 0x2e, 0x06, ++ 0x11, 0x5c, 0x02, 0xdc, 0x3c, 0x29, 0x21, 0x30, 0x24, 0xf0, 0xe4, 0x90, ++ 0x84, 0xb1, 0x21, 0x1f, 0x26, 0x86, 0xb0, 0x28, 0x00, 0x58, 0x35, 0x88, ++ 0xa9, 0x07, 0x80, 0x39, 0x32, 0x62, 0x67, 0x97, 0x21, 0x56, 0x68, 0xf6, ++ 0xc9, 0xe8, 0x99, 0xac, 0x40, 0x90, 0xe6, 0xfe, 0x92, 0xe6, 0x5e, 0xa4, ++ 0xb9, 0xef, 0x0d, 0xe1, 0x1b, 0xe4, 0xd2, 0x75, 0xb5, 0x88, 0x99, 0x77, ++ 0x0b, 0x7c, 0xa9, 0x92, 0xd6, 0x9c, 0x41, 0x2c, 0xba, 0x02, 0xd5, 0xa4, ++ 0x03, 0xeb, 0xa2, 0x60, 0xd9, 0x24, 0xeb, 0x42, 0xbe, 0x8c, 0x49, 0x50, ++ 0x0c, 0x81, 0x0f, 0x6e, 0xd3, 0x35, 0x4d, 0xf0, 0x3b, 0xdd, 0x76, 0xc8, ++ 0x96, 0x00, 0xed, 0x53, 0x63, 0x34, 0xe2, 0xb1, 0x86, 0x92, 0x1f, 0x7a, ++ 0xfa, 0x25, 0x3a, 0x83, 0x82, 0x17, 0x53, 0x50, 0xbb, 0x44, 0xc5, 0xcd, ++ 0x3f, 0x38, 0x55, 0xfc, 0xf7, 0x3d, 0x7f, 0x3a, 0xc9, 0x76, 0xcb, 0xa8, ++ 0x33, 0x6a, 0x70, 0xed, 0x2c, 0x9e, 0x29, 0xa1, 0x92, 0xe6, 0xc9, 0x43, ++ 0xc0, 0xb2, 0x7e, 0x2c, 0xe0, 0xb3, 0xc7, 0x20, 0x63, 0x43, 0x52, 0xa6, ++ 0xb5, 0x01, 0x5c, 0x3f, 0x59, 0x5a, 0x77, 0xc3, 0x24, 0xfb, 0x46, 0x40, ++ 0x32, 0x3e, 0x70, 0x9f, 0x6b, 0x89, 0xe0, 0x74, 0x5e, 0xc5, 0xd1, 0xfc, ++ 0xe1, 0x7a, 0x04, 0x75, 0xc7, 0x81, 0xe2, 0xc8, 0x96, 0x83, 0x9d, 0x49, ++ 0x3f, 0x26, 0x06, 0x67, 0x5c, 0x9f, 0xa1, 0x6b, 0x34, 0x51, 0xfd, 0x11, ++ 0xc5, 0xea, 0x74, 0x86, 0xe6, 0x65, 0xfc, 0x18, 0xc9, 0x1e, 0xaf, 0x47, ++ 0x75, 0x14, 0xcf, 0xb5, 0xf0, 0x7a, 0x5e, 0xcb, 0x7b, 0xdc, 0x5c, 0x57, ++ 0x5e, 0x5f, 0x41, 0xeb, 0x5f, 0x48, 0x02, 0x63, 0x83, 0xdd, 0xb4, 0xd4, ++ 0xc5, 0x76, 0xb3, 0x12, 0x6b, 0x54, 0x38, 0x55, 0x16, 0xef, 0x55, 0xde, ++ 0xc7, 0x11, 0xda, 0xe4, 0xcf, 0xea, 0x4a, 0xfb, 0x40, 0x28, 0x06, 0x9c, ++ 0xca, 0xff, 0xf3, 0xfe, 0x83, 0x5c, 0xf9, 0x7d, 0x2f, 0x9d, 0xa3, 0x10, ++ 0x1e, 0x1d, 0x3c, 0x9d, 0xdf, 0x8a, 0x13, 0xf9, 0xbb, 0x71, 0x2c, 0x9f, ++ 0xa6, 0x33, 0x77, 0xe1, 0x54, 0x7e, 0x07, 0x9e, 0xc9, 0x6f, 0xc1, 0xf1, ++ 0xfc, 0xfd, 0xf8, 0x61, 0xbe, 0x17, 0x4f, 0xe5, 0x37, 0x91, 0x3e, 0x0e, ++ 0xfc, 0x1d, 0xbc, 0x5f, 0xab, 0xf8, 0x38, 0x5d, 0x45, 0x7a, 0xec, 0xc0, ++ 0x54, 0x8e, 0xed, 0x71, 0x31, 0x64, 0xea, 0x07, 0x81, 0x96, 0x68, 0x05, ++ 0xf9, 0x79, 0x8d, 0xa9, 0x1f, 0x25, 0x14, 0xc1, 0x8e, 0x74, 0x23, 0x9b, ++ 0x07, 0x0e, 0x0d, 0x6a, 0xf0, 0x93, 0xbe, 0x46, 0xbc, 0x11, 0x3b, 0xd5, ++ 0x6e, 0x54, 0x1b, 0x69, 0xec, 0x2e, 0x61, 0x51, 0x09, 0x58, 0x3f, 0x47, ++ 0x9a, 0x40, 0xf7, 0x58, 0x0c, 0x8a, 0xa0, 0xcf, 0x6d, 0xb9, 0x6c, 0xa4, ++ 0x94, 0x3b, 0xa4, 0x47, 0x86, 0xf4, 0xc8, 0x90, 0x1e, 0x19, 0xd2, 0x2f, ++ 0x43, 0xfa, 0x65, 0x48, 0x9f, 0x0c, 0xe9, 0x93, 0x21, 0x7d, 0x32, 0xa4, ++ 0x6b, 0x86, 0x74, 0xca, 0xb0, 0xcf, 0x07, 0xc9, 0x96, 0x52, 0xae, 0xa9, ++ 0x96, 0x49, 0x67, 0x36, 0x8a, 0x79, 0xfb, 0x65, 0x31, 0x7b, 0x40, 0xc3, ++ 0xd5, 0x16, 0x02, 0xf5, 0x8b, 0x8d, 0xc2, 0x57, 0x7c, 0x6d, 0x27, 0xa3, ++ 0xb0, 0xe3, 0xb3, 0x60, 0x62, 0x22, 0x2f, 0x8b, 0xe0, 0x80, 0xeb, 0x7e, ++ 0xda, 0x6e, 0xa3, 0xce, 0xd2, 0x9d, 0xbd, 0x92, 0xb1, 0xe9, 0xbc, 0xa8, ++ 0x45, 0xfd, 0x9e, 0x2e, 0x64, 0x43, 0x36, 0xce, 0x24, 0x35, 0xac, 0x49, ++ 0x48, 0xa4, 0xbf, 0x83, 0xbe, 0xa4, 0x6e, 0x3a, 0xd8, 0x8b, 0x42, 0x84, ++ 0xd7, 0x29, 0x8e, 0x9f, 0x7c, 0x75, 0x30, 0xa9, 0x10, 0x1e, 0x6c, 0xbc, ++ 0x6f, 0x56, 0xa0, 0xd0, 0xcd, 0x71, 0x91, 0x51, 0x65, 0x8c, 0x60, 0x7e, ++ 0x38, 0x4c, 0xb6, 0xcd, 0xc7, 0x82, 0x30, 0x8f, 0x41, 0xbc, 0x49, 0xb9, ++ 0x3e, 0xcb, 0x9a, 0x23, 0x3e, 0xda, 0x1f, 0x44, 0xed, 0x7e, 0x05, 0x03, ++ 0x7b, 0x64, 0x6c, 0x4e, 0xb8, 0xee, 0x7f, 0xc5, 0xe5, 0xd4, 0x39, 0xb1, ++ 0x1a, 0xb9, 0xbc, 0x8c, 0xc8, 0x40, 0x1c, 0xa9, 0x90, 0x82, 0xab, 0x07, ++ 0x1c, 0xfc, 0x88, 0xf6, 0x7d, 0x60, 0xd0, 0x46, 0x67, 0x7b, 0x2b, 0xe5, ++ 0x0f, 0x9b, 0xd3, 0x8d, 0x6f, 0xa7, 0x9b, 0x06, 0xf7, 0x4a, 0x15, 0xb0, ++ 0x29, 0x99, 0x03, 0x56, 0x12, 0xdb, 0xd2, 0x4d, 0xce, 0x13, 0xd2, 0x76, ++ 0x48, 0x15, 0x0a, 0x46, 0x06, 0x78, 0x6c, 0x39, 0x9c, 0x49, 0xc6, 0xdc, ++ 0x1f, 0xea, 0xaf, 0x39, 0xb5, 0x84, 0x2b, 0xed, 0x0f, 0xf7, 0xf3, 0x77, ++ 0x6b, 0x29, 0x9f, 0xb4, 0x02, 0x44, 0x03, 0xaf, 0x77, 0xa4, 0xb7, 0x5d, ++ 0x3b, 0xc2, 0x7a, 0x28, 0x8e, 0x8f, 0x7c, 0xb3, 0x36, 0x99, 0xc4, 0x9a, ++ 0x74, 0xd3, 0xf4, 0x23, 0xd2, 0x2c, 0x4c, 0x55, 0x96, 0x62, 0xdc, 0x60, ++ 0x21, 0x7e, 0x62, 0x40, 0xe0, 0x58, 0x33, 0xc7, 0x18, 0xf1, 0x78, 0xae, ++ 0x98, 0x13, 0x9a, 0x2d, 0x29, 0x4e, 0x0d, 0xad, 0xe9, 0xed, 0x88, 0xa1, ++ 0x7a, 0x0f, 0x7f, 0x27, 0x5e, 0xed, 0xa0, 0x1c, 0x08, 0xc6, 0x20, 0x8d, ++ 0x3c, 0x11, 0x28, 0xcd, 0x39, 0x50, 0xcb, 0x3c, 0x23, 0x19, 0xbc, 0x8f, ++ 0xba, 0xed, 0x44, 0xf3, 0x9d, 0xf4, 0xbd, 0x14, 0xe7, 0x0d, 0xe9, 0x26, ++ 0xad, 0x4f, 0x52, 0xe0, 0x44, 0x03, 0xe4, 0x7f, 0x28, 0x0a, 0xed, 0xad, ++ 0xf4, 0x5f, 0xc6, 0xb7, 0x13, 0xfa, 0x49, 0xe6, 0xae, 0xca, 0x58, 0xe9, ++ 0xbc, 0x96, 0x9c, 0x89, 0x43, 0x79, 0x13, 0xeb, 0xd3, 0x4d, 0x9d, 0xc7, ++ 0xf1, 0x33, 0x4c, 0x45, 0x17, 0x74, 0x5f, 0x94, 0xfe, 0xc5, 0xb5, 0x8b, ++ 0x3c, 0xb0, 0x00, 0x17, 0xc3, 0x4d, 0x9b, 0x2e, 0x4a, 0x7a, 0xf6, 0x51, ++ 0xc9, 0x75, 0x9f, 0x89, 0x4b, 0xf8, 0xcb, 0x44, 0x12, 0x85, 0x90, 0x8a, ++ 0x87, 0x12, 0x8a, 0x13, 0x21, 0xfd, 0x06, 0x17, 0x2b, 0xa8, 0xdb, 0x63, ++ 0xe3, 0x3f, 0xe3, 0xaf, 0xa1, 0x70, 0x2b, 0xfb, 0x9d, 0xf5, 0x62, 0x1b, ++ 0xa2, 0xa8, 0x37, 0xaa, 0x50, 0x3f, 0xe2, 0x47, 0x74, 0xcf, 0x8c, 0x3b, ++ 0xdb, 0xe0, 0x71, 0xe3, 0xe4, 0x6c, 0x1f, 0xdb, 0xe0, 0xc7, 0xac, 0x91, ++ 0xa5, 0xc4, 0xeb, 0x3a, 0x05, 0xf3, 0xe7, 0x11, 0x9e, 0x5b, 0x61, 0x94, ++ 0x6d, 0x09, 0xe0, 0xe9, 0x3d, 0x25, 0x3e, 0xd8, 0x9e, 0xec, 0xc4, 0xc6, ++ 0x34, 0x9e, 0x6c, 0xc4, 0xc3, 0x38, 0xb6, 0x98, 0xd7, 0x3f, 0x7c, 0x29, ++ 0x96, 0xe8, 0x27, 0xdb, 0xf9, 0xbe, 0x28, 0xc7, 0xb7, 0xbc, 0x4e, 0xe0, ++ 0xee, 0x2f, 0x53, 0xae, 0xc4, 0xf3, 0x6e, 0xaa, 0x81, 0xf5, 0x9d, 0xae, ++ 0x2d, 0xfd, 0x7b, 0xc4, 0xaa, 0x69, 0x1b, 0x8d, 0x74, 0x56, 0x79, 0x1e, ++ 0xef, 0xf3, 0xaf, 0x1c, 0x9f, 0x56, 0x48, 0x5f, 0xa7, 0x31, 0x8e, 0xf1, ++ 0xfd, 0xee, 0x54, 0x7d, 0x29, 0x46, 0x9b, 0xe8, 0x4c, 0xb9, 0x5f, 0x66, ++ 0xff, 0xa9, 0x2f, 0xfa, 0xee, 0x71, 0xed, 0xb9, 0x7c, 0x4e, 0x53, 0xeb, ++ 0x19, 0xe2, 0xae, 0x11, 0x59, 0xbf, 0xe4, 0xd0, 0x45, 0x78, 0x9c, 0xb8, ++ 0xe7, 0x99, 0x7c, 0x14, 0x07, 0xf2, 0x70, 0xe6, 0x59, 0x9a, 0x78, 0xf7, ++ 0x6f, 0x4d, 0x54, 0xf5, 0x7f, 0x1d, 0x15, 0xfb, 0x56, 0xe3, 0xd9, 0x8c, ++ 0x89, 0x5c, 0xc6, 0x75, 0xd7, 0x98, 0xae, 0x7b, 0xc1, 0xd4, 0x7b, 0xbf, ++ 0x4a, 0x57, 0xe3, 0x47, 0x4b, 0xda, 0x36, 0x75, 0xfa, 0xf4, 0x9e, 0xf3, ++ 0x22, 0xd6, 0xdd, 0x2f, 0x34, 0x3c, 0x99, 0x6f, 0x2d, 0xfa, 0xfc, 0x70, ++ 0xde, 0xa0, 0xe7, 0x42, 0xca, 0xc9, 0x24, 0x71, 0x0a, 0xe7, 0x8d, 0x82, ++ 0x7f, 0x33, 0x33, 0x70, 0x22, 0xcc, 0x49, 0x32, 0xf9, 0x92, 0x75, 0x57, ++ 0x31, 0xd6, 0x42, 0x31, 0xca, 0x48, 0x68, 0x8d, 0xd3, 0x05, 0x74, 0xdb, ++ 0x0c, 0xc5, 0xb0, 0xe4, 0x9f, 0x34, 0xe5, 0xc4, 0x63, 0x94, 0x6b, 0x77, ++ 0xc5, 0xc3, 0xb0, 0x57, 0x1a, 0x18, 0xcb, 0xc8, 0xe8, 0x4f, 0x9f, 0xc2, ++ 0xa9, 0x10, 0xb9, 0x94, 0xfc, 0xb1, 0x3e, 0x11, 0x40, 0x56, 0xe5, 0xf1, ++ 0x00, 0xd9, 0xff, 0x26, 0x8c, 0x70, 0x2d, 0x5a, 0x16, 0xbc, 0x86, 0x29, ++ 0x35, 0x48, 0x98, 0xa8, 0x2e, 0xde, 0x03, 0xad, 0x14, 0xb3, 0x46, 0xc3, ++ 0xc0, 0x48, 0x46, 0x60, 0x39, 0x3d, 0xc7, 0xc8, 0xb6, 0x89, 0x4c, 0xc9, ++ 0x17, 0xeb, 0x93, 0xfa, 0x74, 0x1f, 0x71, 0xc2, 0xb1, 0xb4, 0x89, 0xd3, ++ 0xb9, 0x9b, 0xf1, 0xec, 0xa0, 0x89, 0x23, 0x69, 0xd7, 0x8d, 0x26, 0xe5, ++ 0x2d, 0x64, 0x0f, 0xf1, 0x42, 0x12, 0x93, 0x84, 0x9f, 0x89, 0x0c, 0xe5, ++ 0x2b, 0xe5, 0xc0, 0x2b, 0xa6, 0xde, 0xf3, 0xaa, 0x2f, 0x00, 0x3b, 0xd4, ++ 0x43, 0x36, 0x6a, 0x18, 0x4b, 0xf7, 0x50, 0x6e, 0x0c, 0x63, 0x50, 0xe5, ++ 0x78, 0x05, 0x30, 0xb2, 0x27, 0x89, 0x03, 0x19, 0xf6, 0x3f, 0x6e, 0x92, ++ 0xe0, 0xa0, 0xb5, 0x83, 0x63, 0xe9, 0x5c, 0xf2, 0xc7, 0x15, 0xf2, 0x31, ++ 0x61, 0xa9, 0xc3, 0x44, 0xcd, 0x40, 0x53, 0xf7, 0xbd, 0xa2, 0x17, 0xf6, ++ 0x6c, 0x07, 0x77, 0x50, 0x4e, 0x44, 0xad, 0xc7, 0xe3, 0xd1, 0x8c, 0xe3, ++ 0xce, 0x33, 0x8c, 0x2d, 0xd7, 0xf9, 0x1e, 0xc2, 0x35, 0xed, 0x60, 0x4e, ++ 0x71, 0x82, 0x96, 0x8a, 0x50, 0xfb, 0x20, 0xce, 0xe7, 0x92, 0xd0, 0xc2, ++ 0x7a, 0xeb, 0x11, 0xb1, 0x19, 0xa3, 0x83, 0x09, 0xa4, 0x56, 0x2b, 0x84, ++ 0x7f, 0xc2, 0xb7, 0xb1, 0x19, 0x07, 0xb2, 0xdf, 0xc5, 0x99, 0xe1, 0x6a, ++ 0xf4, 0x19, 0x61, 0x54, 0x4c, 0x28, 0x4e, 0x2d, 0x9d, 0x31, 0xde, 0xa1, ++ 0xe0, 0x18, 0xf1, 0xc8, 0xc2, 0x84, 0x0c, 0xa7, 0x81, 0xed, 0x14, 0x84, ++ 0xe9, 0x35, 0x28, 0x14, 0xf1, 0xee, 0x60, 0x1d, 0xf1, 0x5b, 0x86, 0xf4, ++ 0xfe, 0x61, 0xa6, 0x1a, 0x9f, 0x84, 0x20, 0xd6, 0xd2, 0x9d, 0xf2, 0x40, ++ 0xba, 0xa9, 0xf0, 0x77, 0xd2, 0x5f, 0x03, 0x57, 0xf5, 0xe0, 0x60, 0x46, ++ 0xc3, 0xae, 0x1c, 0x70, 0x7f, 0x4e, 0x20, 0x62, 0xc8, 0xd8, 0x96, 0xeb, ++ 0x26, 0x3c, 0x2c, 0x41, 0xa1, 0xb1, 0xc4, 0x49, 0x63, 0x14, 0x7f, 0x27, ++ 0xc2, 0x9f, 0xfd, 0x98, 0x0a, 0xeb, 0x51, 0x80, 0x63, 0x27, 0x63, 0x49, ++ 0x7c, 0xcf, 0xcc, 0xd4, 0xad, 0xba, 0x9a, 0xa2, 0xdc, 0xf3, 0x19, 0x7f, ++ 0xce, 0x3c, 0x41, 0x9f, 0x3f, 0xe3, 0x67, 0x67, 0x09, 0xa3, 0xb3, 0x7e, ++ 0x03, 0xa3, 0x6c, 0x03, 0x21, 0x6d, 0xb1, 0xa0, 0x38, 0x95, 0xf3, 0x29, ++ 0x8c, 0xaa, 0x09, 0x4a, 0xda, 0x3d, 0x82, 0xee, 0x8b, 0x6e, 0x8c, 0xe7, ++ 0x69, 0x5e, 0x07, 0xbf, 0x2b, 0x73, 0xc2, 0xa1, 0x20, 0xdd, 0xf3, 0x64, ++ 0x63, 0x27, 0xc6, 0x5b, 0x52, 0x38, 0x98, 0x3f, 0x48, 0xbe, 0xed, 0x24, ++ 0x6c, 0x7d, 0x8b, 0x38, 0x88, 0xbe, 0x67, 0x68, 0x3c, 0x03, 0x71, 0xd4, ++ 0xbc, 0xcb, 0xc5, 0xad, 0x8c, 0x2d, 0x0b, 0xa3, 0x99, 0x1e, 0x54, 0xf6, ++ 0x37, 0x69, 0x1b, 0xb1, 0xce, 0xdd, 0x2e, 0xf7, 0xc0, 0x37, 0x79, 0x1b, ++ 0xed, 0xc1, 0xef, 0xca, 0xfc, 0x72, 0x26, 0x58, 0xca, 0xa1, 0xff, 0xe5, ++ 0x24, 0xe6, 0xf8, 0xd1, 0x64, 0xf9, 0xdc, 0x2a, 0x7c, 0x27, 0xab, 0x9b, ++ 0x05, 0x69, 0x09, 0xe9, 0xce, 0x79, 0xcc, 0xf9, 0xfc, 0x3c, 0xad, 0x61, ++ 0x3f, 0x44, 0x09, 0x53, 0xa3, 0xae, 0xdd, 0xc3, 0x3a, 0x95, 0xd7, 0x33, ++ 0x97, 0x09, 0xaa, 0x33, 0xba, 0x09, 0x1f, 0xcc, 0x67, 0xbf, 0x4b, 0x7f, ++ 0x13, 0x4f, 0xa7, 0x15, 0x9c, 0x1a, 0x88, 0xd2, 0x9e, 0x02, 0xff, 0xdc, ++ 0x5c, 0x35, 0x5d, 0xf0, 0x99, 0x38, 0x41, 0x38, 0x7b, 0x2a, 0xc3, 0x7e, ++ 0xa3, 0x75, 0x09, 0xbe, 0x67, 0xe7, 0x88, 0xf7, 0x86, 0xef, 0x72, 0xb3, ++ 0xdd, 0x2a, 0x5e, 0x4c, 0xfe, 0x0d, 0xad, 0x65, 0x7c, 0x2d, 0xc0, 0xa2, ++ 0x70, 0x03, 0xae, 0x5d, 0x70, 0x35, 0xa6, 0x42, 0x8d, 0x98, 0x4d, 0x5c, ++ 0x12, 0x35, 0xbe, 0xe2, 0x76, 0xde, 0xce, 0xb9, 0xa0, 0x50, 0xae, 0x5e, ++ 0x85, 0x77, 0xf7, 0x3e, 0xe7, 0xaa, 0x46, 0x90, 0x31, 0x6f, 0xf6, 0xe2, ++ 0x2a, 0xbc, 0x3f, 0xba, 0x3e, 0xc8, 0x3e, 0x5f, 0x9f, 0x00, 0x1e, 0x4a, ++ 0xf7, 0xbb, 0x9f, 0x16, 0xef, 0x16, 0x99, 0x78, 0xa7, 0xc9, 0x7c, 0xc9, ++ 0xb7, 0xc3, 0xfd, 0x27, 0x99, 0x63, 0x7e, 0xfa, 0x8a, 0x1f, 0x16, 0xbb, ++ 0xf3, 0x1b, 0x39, 0x57, 0x7a, 0xe9, 0xbb, 0x4a, 0x7b, 0x04, 0x11, 0x32, ++ 0x4c, 0xf7, 0x8d, 0x5b, 0xf9, 0xf3, 0x3d, 0x34, 0xd6, 0x48, 0xcf, 0x2f, ++ 0xb9, 0x4b, 0x7f, 0xeb, 0x3c, 0xf5, 0x77, 0x9c, 0xb7, 0x8e, 0x9e, 0x61, ++ 0x1a, 0x07, 0x61, 0xf0, 0xa4, 0x58, 0x53, 0xaa, 0x5f, 0x15, 0xd9, 0x38, ++ 0x29, 0xd6, 0x15, 0x6b, 0xd6, 0xe2, 0xf5, 0x40, 0xfe, 0xee, 0xc2, 0xc8, ++ 0xb0, 0xeb, 0xee, 0x30, 0x67, 0xc3, 0x56, 0xc3, 0xd8, 0x61, 0x74, 0xe1, ++ 0xd0, 0x30, 0xaf, 0x71, 0xdd, 0xd6, 0xf8, 0x82, 0x4e, 0x59, 0xd4, 0x53, ++ 0x3e, 0x3b, 0x62, 0x43, 0x52, 0x13, 0xdf, 0x1a, 0xa6, 0x1b, 0x2b, 0x33, ++ 0x87, 0xfc, 0xeb, 0xba, 0x87, 0xe3, 0xb0, 0xb7, 0xc7, 0x6b, 0xf0, 0xe3, ++ 0xac, 0x4a, 0xb5, 0xed, 0x8c, 0xbb, 0x3c, 0xd6, 0x85, 0x3c, 0xed, 0xf3, ++ 0x61, 0xbc, 0xad, 0xf5, 0x8c, 0x20, 0x5e, 0xa0, 0x3a, 0xfd, 0xf1, 0x4c, ++ 0x04, 0x67, 0xc6, 0x64, 0xf4, 0x51, 0xee, 0x3f, 0x9f, 0xe4, 0x33, 0x65, ++ 0x3c, 0x92, 0x67, 0xdf, 0x52, 0x3d, 0x67, 0x38, 0xe2, 0x9d, 0xe2, 0x58, ++ 0x0d, 0x96, 0x67, 0x79, 0x2e, 0x73, 0xb8, 0xa1, 0xce, 0xf6, 0x95, 0xe7, ++ 0x5d, 0xa0, 0xfa, 0x48, 0x23, 0xec, 0xcf, 0xa5, 0x1a, 0x28, 0x42, 0xb5, ++ 0x11, 0xd7, 0x64, 0x06, 0xd5, 0x47, 0x51, 0xaa, 0x87, 0xf4, 0xa8, 0x03, ++ 0xd7, 0x3d, 0x4e, 0x1c, 0xf8, 0x06, 0xfd, 0x7d, 0x62, 0xf2, 0x9d, 0x74, ++ 0x52, 0x48, 0x03, 0x6c, 0xa3, 0x23, 0xc2, 0x8b, 0xa9, 0x56, 0x3c, 0x42, ++ 0xf5, 0xa7, 0x74, 0x1b, 0xd5, 0x6f, 0x1a, 0x7c, 0x47, 0x6c, 0xac, 0x4d, ++ 0x2c, 0xbd, 0x52, 0x83, 0x6b, 0xa2, 0x7a, 0x3f, 0xf3, 0x9b, 0x8d, 0x5d, ++ 0xa4, 0xef, 0x8d, 0xf1, 0x19, 0xb7, 0x25, 0xe6, 0xba, 0xfe, 0x78, 0x9b, ++ 0xf9, 0x1e, 0xf5, 0x21, 0x05, 0x55, 0x6f, 0x9d, 0x82, 0x8d, 0xc7, 0xe8, ++ 0xdd, 0xfa, 0x38, 0x38, 0xa7, 0xc5, 0x58, 0x47, 0x53, 0x2a, 0x26, 0x05, ++ 0xb1, 0x73, 0xcc, 0x40, 0xba, 0x68, 0x0f, 0x30, 0x44, 0x7c, 0x34, 0x98, ++ 0x61, 0x5b, 0x1c, 0xf1, 0x11, 0xd5, 0x1a, 0xaf, 0x11, 0xff, 0x7c, 0x3a, ++ 0xae, 0xe2, 0x3f, 0xc6, 0x5b, 0x71, 0x89, 0x6a, 0xd1, 0x4f, 0xc6, 0x6b, ++ 0x51, 0x58, 0xc9, 0xef, 0x1b, 0x85, 0x3b, 0x7c, 0xd9, 0xfd, 0xac, 0x5d, ++ 0x46, 0x67, 0x8b, 0x9e, 0xad, 0xf4, 0xc1, 0xde, 0x4b, 0xf5, 0xcf, 0x7d, ++ 0x09, 0x3f, 0xec, 0x46, 0x7e, 0xef, 0xba, 0xe4, 0xeb, 0x87, 0xd6, 0x24, ++ 0x0d, 0xf3, 0x79, 0xc2, 0x45, 0x5f, 0xde, 0x3d, 0x5d, 0x4d, 0xbe, 0x79, ++ 0x2f, 0x69, 0x74, 0xbd, 0x82, 0x66, 0x1c, 0x1a, 0x93, 0xc5, 0x07, 0xe9, ++ 0x85, 0x38, 0x48, 0x3d, 0x47, 0x05, 0xd9, 0xf8, 0x7e, 0x8e, 0x7c, 0x40, ++ 0x1c, 0x71, 0x3c, 0x43, 0x7e, 0xa1, 0x1c, 0x78, 0x8a, 0x7c, 0x7c, 0xac, ++ 0x58, 0x5b, 0xb2, 0xdf, 0x5a, 0xa9, 0x46, 0x08, 0x62, 0xe5, 0xc4, 0x68, ++ 0x1d, 0xe3, 0x98, 0xf4, 0xa4, 0xfe, 0xc7, 0x11, 0x2b, 0x48, 0x3f, 0x99, ++ 0xd6, 0x6e, 0x27, 0x0c, 0xa4, 0x64, 0x68, 0x95, 0x86, 0x44, 0xf7, 0xa1, ++ 0x82, 0x03, 0x63, 0x35, 0x98, 0xa0, 0xf8, 0x65, 0xc7, 0xa0, 0xfa, 0xe9, ++ 0xfd, 0xce, 0x2f, 0x70, 0x01, 0x5a, 0x7b, 0x96, 0xfc, 0x9f, 0x24, 0x7f, ++ 0xc3, 0x7e, 0xde, 0x34, 0x29, 0x0e, 0x0b, 0x29, 0x0e, 0xad, 0xe4, 0x7b, ++ 0x83, 0x62, 0xa1, 0x51, 0x2c, 0x1e, 0x26, 0xbc, 0x30, 0xb7, 0x68, 0x90, ++ 0x2d, 0x23, 0x7a, 0x06, 0xdb, 0xd8, 0xbf, 0xce, 0xcb, 0xa6, 0x8c, 0x9d, ++ 0x19, 0xf7, 0xb4, 0x42, 0x78, 0x3c, 0x4b, 0x5d, 0xdd, 0x28, 0xf1, 0x5b, ++ 0x5f, 0x1e, 0xda, 0x79, 0x73, 0x2b, 0xa6, 0x1a, 0x64, 0x84, 0xac, 0xd3, ++ 0x6e, 0xd8, 0x30, 0x7a, 0xee, 0xa3, 0x22, 0xe1, 0x27, 0x26, 0x61, 0x27, ++ 0x2c, 0xe3, 0x31, 0xda, 0x2f, 0x6a, 0x19, 0xd9, 0x0b, 0xa0, 0x42, 0x2b, ++ 0x0c, 0xa7, 0x8e, 0x6a, 0xba, 0x79, 0x96, 0x71, 0xf6, 0x6d, 0xfc, 0x04, ++ 0x5a, 0x3d, 0x08, 0xa3, 0x3c, 0x76, 0xb5, 0x78, 0x77, 0xdf, 0x5c, 0xf1, ++ 0xef, 0xfb, 0x5c, 0x77, 0x9d, 0x89, 0xe5, 0x55, 0x88, 0xb5, 0xee, 0x82, ++ 0x82, 0x9d, 0x79, 0x7e, 0x1f, 0x10, 0x4f, 0x0d, 0xc3, 0x3e, 0x46, 0x77, ++ 0x87, 0x9a, 0x3c, 0x05, 0x33, 0xec, 0xba, 0x5d, 0x09, 0xd8, 0xc7, 0xd3, ++ 0x10, 0x7b, 0x13, 0x02, 0xa9, 0xdb, 0x55, 0xe2, 0x6b, 0xa8, 0xaf, 0x98, ++ 0x0a, 0xdd, 0x1d, 0x02, 0x9f, 0x10, 0x07, 0xbf, 0x6a, 0x3e, 0x41, 0xfc, ++ 0x0c, 0x95, 0xce, 0xdd, 0x74, 0x01, 0xfb, 0x90, 0x6d, 0x40, 0xc0, 0x6f, ++ 0xf1, 0x3b, 0x88, 0x97, 0xcd, 0x6a, 0x68, 0x0d, 0x02, 0x41, 0x0b, 0xf6, ++ 0xda, 0xb8, 0x82, 0x54, 0xc4, 0xc8, 0xbe, 0x06, 0x31, 0x4f, 0x25, 0x1d, ++ 0x5f, 0x27, 0x9b, 0xea, 0xac, 0x5f, 0x20, 0x13, 0x86, 0x14, 0x8a, 0xf3, ++ 0x1c, 0x7e, 0xb7, 0x17, 0x4e, 0x23, 0xd4, 0x4a, 0xcb, 0xd0, 0x5e, 0x02, ++ 0x73, 0x54, 0x25, 0x01, 0x52, 0x77, 0xa8, 0x77, 0xd9, 0x46, 0x1d, 0x18, ++ 0x2e, 0xc5, 0x9d, 0x28, 0x41, 0x4f, 0xa9, 0xb2, 0x0a, 0x0f, 0xce, 0x8f, ++ 0xe9, 0xad, 0x77, 0x52, 0xdf, 0xb1, 0x27, 0xd3, 0x05, 0x3b, 0xac, 0xef, ++ 0x4a, 0x49, 0xfb, 0x69, 0x6e, 0xc9, 0xe7, 0xa3, 0x83, 0x7a, 0x67, 0x8a, ++ 0x6a, 0xaa, 0x94, 0xaa, 0x67, 0xb9, 0x27, 0x96, 0x8d, 0x87, 0xc5, 0x3a, ++ 0xb5, 0xd4, 0x4f, 0x9d, 0x1c, 0xec, 0x11, 0x4a, 0xbd, 0x8d, 0x37, 0xcd, ++ 0xc2, 0x0f, 0x54, 0x44, 0xc9, 0xc7, 0x02, 0xd9, 0x6e, 0x1b, 0x1b, 0x17, ++ 0xc3, 0x09, 0x91, 0x9e, 0xf3, 0x07, 0x20, 0xda, 0xe3, 0xbf, 0x26, 0x7f, ++ 0x7e, 0xee, 0x5e, 0x32, 0xb9, 0x6f, 0x36, 0xb0, 0x36, 0x2d, 0xe3, 0x63, ++ 0x8a, 0xc7, 0x46, 0x53, 0x88, 0xa9, 0x48, 0xa9, 0xa7, 0xb4, 0x6f, 0x97, ++ 0x89, 0xf7, 0x83, 0xa2, 0x79, 0x3f, 0xd7, 0x8f, 0x14, 0x3f, 0xaa, 0x03, ++ 0xde, 0xa0, 0x7c, 0x6e, 0x4e, 0x6c, 0xa5, 0x5c, 0x91, 0x88, 0xfb, 0xcf, ++ 0x91, 0x5e, 0x3c, 0x57, 0xb7, 0x01, 0x8a, 0x3f, 0xdd, 0x37, 0xc7, 0x33, ++ 0x14, 0xfb, 0x0c, 0xc5, 0x3e, 0x43, 0xb1, 0x27, 0xec, 0x1d, 0xcd, 0x50, ++ 0x0f, 0x2a, 0x18, 0x2b, 0x9d, 0xdc, 0xe7, 0x50, 0xcc, 0x6b, 0xc8, 0x5f, ++ 0x1a, 0x6a, 0x2c, 0x8e, 0xf3, 0xa3, 0xee, 0x54, 0x48, 0xc6, 0xf6, 0x0c, ++ 0xc7, 0xda, 0x70, 0xde, 0xc0, 0x4e, 0x17, 0x8d, 0x36, 0x36, 0x27, 0x39, ++ 0xee, 0x9f, 0x12, 0x2e, 0x39, 0xf6, 0x46, 0xf7, 0x8f, 0xf1, 0x2b, 0xd7, ++ 0x0e, 0xf1, 0x7c, 0x99, 0x38, 0xc5, 0x75, 0x83, 0x94, 0x03, 0xe7, 0x3a, ++ 0x0c, 0xf3, 0x1c, 0x5d, 0x92, 0xdb, 0x3b, 0x3e, 0xaa, 0x63, 0x3e, 0x24, ++ 0xdc, 0x50, 0x8f, 0xd2, 0x49, 0x3d, 0x0a, 0x94, 0x4a, 0x7a, 0x5e, 0x34, ++ 0x6e, 0x24, 0x63, 0x89, 0xab, 0x62, 0x6f, 0x91, 0xed, 0x45, 0x5c, 0x28, ++ 0xcc, 0xe7, 0x93, 0xfd, 0x55, 0xd4, 0x3b, 0x40, 0xbc, 0x6d, 0xc2, 0xde, ++ 0x14, 0xaf, 0x00, 0x42, 0xa8, 0x9b, 0x6d, 0x19, 0xbd, 0x3f, 0x25, 0x83, ++ 0x23, 0x56, 0x5b, 0x61, 0x40, 0x9a, 0x27, 0xb0, 0x8a, 0x73, 0xe0, 0xef, ++ 0x31, 0x55, 0x8f, 0xba, 0x2a, 0xcb, 0x50, 0x5f, 0xa6, 0xe0, 0xf8, 0xad, ++ 0xfd, 0x58, 0xa1, 0x2a, 0x94, 0xcb, 0x46, 0x8f, 0x21, 0xe9, 0x5b, 0x36, ++ 0x0a, 0x19, 0xef, 0x52, 0xef, 0xb9, 0xd1, 0x28, 0xe8, 0x95, 0xc5, 0x7e, ++ 0x26, 0x28, 0x2a, 0xf6, 0x4b, 0xe4, 0x63, 0x19, 0xe7, 0xc8, 0x47, 0x13, ++ 0x71, 0xf6, 0x0f, 0xfb, 0x89, 0xfd, 0xf3, 0x7b, 0x7c, 0x83, 0xb2, 0x6f, ++ 0xdc, 0x1a, 0xc9, 0x32, 0xa6, 0x5f, 0x20, 0xae, 0xba, 0x23, 0xd9, 0xd6, ++ 0x7b, 0x9d, 0x6f, 0x93, 0x5b, 0x58, 0x59, 0xc4, 0x98, 0x22, 0x5b, 0x0b, ++ 0xb1, 0x23, 0xed, 0xa7, 0xcf, 0x02, 0x8f, 0x1a, 0x5c, 0x2b, 0x2f, 0x44, ++ 0x4b, 0xee, 0x2a, 0x95, 0xec, 0x26, 0xfc, 0x71, 0xde, 0x06, 0xc5, 0x8a, ++ 0x61, 0x28, 0xf3, 0xac, 0x0b, 0x70, 0xa9, 0x37, 0x90, 0xf9, 0x7c, 0x53, ++ 0xe0, 0xb3, 0x16, 0xd6, 0x81, 0xe7, 0x5f, 0xc0, 0xd2, 0x1c, 0xeb, 0xe2, ++ 0x23, 0x6c, 0x13, 0xf1, 0x54, 0xb3, 0x3e, 0x2a, 0x3d, 0x35, 0xfa, 0xbe, ++ 0x5d, 0xe5, 0x3e, 0x81, 0x09, 0xde, 0x4f, 0x98, 0x1b, 0x37, 0x96, 0xf2, ++ 0xbe, 0x84, 0xaf, 0x5e, 0xea, 0x9f, 0x80, 0x60, 0x7f, 0x58, 0x8c, 0x0d, ++ 0x72, 0x5e, 0x73, 0x1f, 0xfb, 0x48, 0xd4, 0x07, 0x4a, 0x72, 0xd5, 0x87, ++ 0x75, 0x86, 0x43, 0x4c, 0xac, 0x3f, 0xbe, 0x93, 0xda, 0xaf, 0x7b, 0x07, ++ 0x64, 0xdc, 0x67, 0x38, 0x94, 0x8e, 0x2a, 0xe5, 0xbb, 0xbe, 0xc5, 0x4f, ++ 0x63, 0xbf, 0xec, 0x8f, 0x60, 0x92, 0xfa, 0xbb, 0x1c, 0xf1, 0xd9, 0xee, ++ 0xb8, 0xde, 0xb5, 0x82, 0xe0, 0x14, 0xeb, 0x8f, 0x52, 0xad, 0x10, 0xc5, ++ 0x64, 0x86, 0xf1, 0xc2, 0xd8, 0x57, 0x10, 0x30, 0x18, 0xeb, 0x10, 0xf3, ++ 0x63, 0xd3, 0x2a, 0xdf, 0x63, 0x87, 0x5b, 0x80, 0xd5, 0x83, 0x02, 0xe3, ++ 0x74, 0x5f, 0xe6, 0x17, 0xea, 0x8f, 0xdf, 0x0f, 0x67, 0xb0, 0x1e, 0xfa, ++ 0xae, 0x1b, 0x25, 0xaa, 0x5e, 0x06, 0x2a, 0xe8, 0x2e, 0x6d, 0xb6, 0x55, ++ 0xa1, 0xab, 0x2b, 0xc4, 0xaf, 0xdc, 0x5c, 0x04, 0x73, 0xfc, 0xf8, 0xd4, ++ 0xcd, 0xde, 0xc6, 0x6b, 0xa8, 0xbd, 0xb0, 0xd8, 0x06, 0x39, 0x3e, 0x9e, ++ 0xee, 0x45, 0xed, 0x12, 0x20, 0xd7, 0xaf, 0xe1, 0xf0, 0xc2, 0x2a, 0xca, ++ 0xe3, 0xa6, 0xae, 0x01, 0xe1, 0x4c, 0xfb, 0x8b, 0xbf, 0x15, 0x29, 0xf1, ++ 0xeb, 0x0d, 0xfd, 0xec, 0x3b, 0x54, 0x43, 0x1f, 0x31, 0x80, 0xf9, 0x79, ++ 0xf6, 0x8f, 0x1c, 0x5f, 0x94, 0xab, 0x50, 0xf9, 0xb7, 0x89, 0x5d, 0xf9, ++ 0x46, 0x57, 0x6b, 0x2c, 0xe6, 0xb3, 0x13, 0x26, 0xbf, 0xf6, 0xec, 0x77, ++ 0xc4, 0x4a, 0xba, 0x23, 0xb4, 0x23, 0x32, 0x6a, 0x5b, 0x5c, 0xf7, 0x68, ++ 0x9c, 0xeb, 0xe1, 0xd2, 0x5d, 0x61, 0xd3, 0xd8, 0xee, 0x0c, 0xf3, 0x9f, ++ 0x7b, 0x3a, 0x40, 0x3c, 0xb9, 0x69, 0xb1, 0xd1, 0xf3, 0x35, 0x21, 0x51, ++ 0xaf, 0x11, 0x40, 0xfb, 0x44, 0x10, 0xe6, 0x84, 0x82, 0xd6, 0x89, 0x66, ++ 0xb4, 0x4d, 0xa8, 0x68, 0x9e, 0x38, 0x29, 0x56, 0x1f, 0x29, 0xfb, 0xfe, ++ 0xdc, 0x15, 0x5c, 0xfc, 0x05, 0xfb, 0xde, 0x66, 0xdf, 0xfb, 0xac, 0xd7, ++ 0x29, 0x07, 0x03, 0xf0, 0x2f, 0xa2, 0xde, 0xa1, 0x53, 0x60, 0xf7, 0x35, ++ 0xc6, 0xe0, 0x0a, 0x71, 0xa7, 0x6b, 0x37, 0x16, 0x08, 0x24, 0x97, 0x5d, ++ 0xa5, 0x99, 0xce, 0xbf, 0xe6, 0x1b, 0x20, 0x5b, 0x09, 0x6b, 0xd4, 0xfb, ++ 0xd0, 0x9c, 0x37, 0xaf, 0x31, 0x0a, 0x3b, 0xa5, 0x3b, 0x80, 0x3f, 0xe3, ++ 0xb1, 0xeb, 0x5f, 0xa9, 0x40, 0x9b, 0xa6, 0xc2, 0x30, 0x0d, 0xdf, 0x5f, ++ 0x51, 0x1f, 0xcc, 0x98, 0xe7, 0xb5, 0x65, 0x6c, 0x7e, 0x9f, 0xce, 0x62, ++ 0x7c, 0x06, 0xc5, 0x02, 0xc2, 0xe9, 0xc7, 0x49, 0xce, 0x69, 0x19, 0xdd, ++ 0x74, 0x9f, 0x55, 0x50, 0xaf, 0xfb, 0xd5, 0x2f, 0x72, 0xba, 0xac, 0x53, ++ 0x50, 0xb4, 0xed, 0x87, 0x90, 0x0d, 0x1e, 0x93, 0x71, 0x0f, 0xcd, 0x7b, ++ 0x3f, 0xce, 0x73, 0x98, 0x07, 0x56, 0xaa, 0x57, 0xfe, 0x7f, 0x15, 0x7b, ++ 0x94, 0x78, 0x73, 0x8d, 0x79, 0x03, 0x61, 0x02, 0xe2, 0xbc, 0xc9, 0xbf, ++ 0xaf, 0x11, 0x79, 0x0e, 0x34, 0x80, 0xf3, 0xfa, 0xbe, 0x04, 0xea, 0x02, ++ 0x96, 0xd1, 0xfd, 0x2a, 0xe5, 0x4f, 0x8d, 0x15, 0xc2, 0x4d, 0x84, 0xe7, ++ 0x7a, 0xba, 0x4b, 0xfa, 0x32, 0x41, 0x71, 0x72, 0x98, 0xf7, 0x35, 0x7a, ++ 0xcf, 0x40, 0xcf, 0xbe, 0x44, 0xb9, 0xd4, 0x4f, 0x3d, 0xb7, 0xd2, 0xc2, ++ 0x9c, 0x26, 0xe3, 0x58, 0xac, 0xa0, 0x87, 0xc0, 0x67, 0x91, 0x6e, 0x74, ++ 0xe7, 0x56, 0x1a, 0x86, 0x53, 0x29, 0x7d, 0xee, 0xde, 0x9b, 0xe0, 0xf5, ++ 0x3d, 0xa8, 0x0f, 0x0b, 0xcc, 0x4b, 0x7c, 0x13, 0x53, 0xb3, 0x18, 0xfb, ++ 0x32, 0x7c, 0x54, 0x3f, 0xf3, 0x7d, 0x9d, 0xc9, 0x40, 0xb9, 0x14, 0x5f, ++ 0x03, 0x6a, 0xb1, 0xb8, 0x4f, 0x72, 0xed, 0xdb, 0x7f, 0xd3, 0xd7, 0x65, ++ 0xdf, 0x43, 0xbb, 0x60, 0x6e, 0x9b, 0xe1, 0x1c, 0xa7, 0xfa, 0xb1, 0x8b, ++ 0x30, 0x6c, 0xc7, 0x08, 0x9b, 0xdc, 0x67, 0xad, 0x35, 0x1c, 0x42, 0x36, ++ 0xf5, 0x38, 0x79, 0x7d, 0x7a, 0x05, 0xd9, 0xf6, 0x19, 0xdd, 0x99, 0xd9, ++ 0xfc, 0x45, 0x5a, 0x17, 0xc1, 0xb3, 0x79, 0xf6, 0x21, 0xe7, 0x49, 0xd9, ++ 0x8f, 0x87, 0x66, 0x9c, 0x30, 0x73, 0x2f, 0xeb, 0xa0, 0x8a, 0x6f, 0x92, ++ 0x3d, 0xcf, 0x72, 0x4d, 0xd3, 0x3e, 0x3a, 0xb3, 0x68, 0x15, 0xf3, 0xee, ++ 0x72, 0x95, 0x7f, 0xbb, 0xd9, 0x49, 0x3a, 0x11, 0xb7, 0x21, 0x4e, 0x7d, ++ 0x75, 0x4b, 0x62, 0x66, 0x66, 0x4a, 0x65, 0x1d, 0x82, 0x62, 0x62, 0x98, ++ 0xf7, 0xe0, 0xfd, 0xca, 0x7c, 0x31, 0x52, 0xdc, 0xd7, 0x6f, 0x04, 0x45, ++ 0x5f, 0xf1, 0x1d, 0xe7, 0xf1, 0x6f, 0xbf, 0x3b, 0x34, 0xcc, 0x6b, 0x4a, ++ 0x31, 0xb9, 0x8e, 0x63, 0xd2, 0xce, 0x7e, 0xfa, 0xdc, 0xdd, 0x98, 0x58, ++ 0x16, 0x42, 0x35, 0xc7, 0x5b, 0x50, 0xee, 0x0a, 0xaa, 0x05, 0xff, 0x61, ++ 0xe6, 0x5e, 0x55, 0xd0, 0x7d, 0x20, 0x51, 0x0d, 0xb6, 0x6d, 0x66, 0x73, ++ 0x84, 0x75, 0xb5, 0xf1, 0xba, 0xf9, 0xbd, 0x19, 0x84, 0xb9, 0x56, 0x51, ++ 0x45, 0x6e, 0x9f, 0x84, 0xc3, 0xa4, 0x73, 0x5f, 0x7c, 0x68, 0xe6, 0x86, ++ 0x10, 0xeb, 0x55, 0xd6, 0x59, 0x46, 0x22, 0xe1, 0x2b, 0xd6, 0x1c, 0x32, ++ 0x61, 0x6d, 0xe9, 0x62, 0xd7, 0x8d, 0xb7, 0xb3, 0x5e, 0x7a, 0xa7, 0x26, ++ 0x3d, 0x19, 0x2a, 0xf1, 0x05, 0x73, 0x0e, 0x7f, 0x2f, 0xd9, 0x70, 0x88, ++ 0xef, 0x85, 0x78, 0x19, 0x43, 0xdf, 0xa3, 0x39, 0x9f, 0xbb, 0xf1, 0x44, ++ 0x50, 0xec, 0xde, 0xc7, 0x73, 0x18, 0x47, 0x32, 0x6e, 0x22, 0x7d, 0x37, ++ 0x7c, 0x31, 0xe7, 0xe1, 0x50, 0x09, 0x43, 0xaf, 0x5f, 0xf9, 0x0d, 0x6d, ++ 0x21, 0xd5, 0x0f, 0x81, 0x94, 0x6a, 0xb5, 0xe2, 0x69, 0xaa, 0x1b, 0x4e, ++ 0xe4, 0xcb, 0xf5, 0x1c, 0xd7, 0x70, 0x5c, 0xd3, 0xa1, 0x3b, 0x30, 0xf0, ++ 0x90, 0x5b, 0x6b, 0x70, 0xcf, 0x65, 0xf4, 0xf4, 0x8b, 0x40, 0xe7, 0x5d, ++ 0x1d, 0x3e, 0xfe, 0x3d, 0xa1, 0xbb, 0xfa, 0x88, 0x82, 0x97, 0x73, 0x9c, ++ 0xc7, 0x1a, 0xb4, 0x5c, 0x6d, 0x63, 0x29, 0xde, 0x8d, 0xa9, 0x0a, 0x0b, ++ 0x78, 0x29, 0xad, 0xc2, 0x4f, 0x75, 0x93, 0x62, 0xad, 0x74, 0x46, 0x93, ++ 0x86, 0xf6, 0x01, 0x56, 0xad, 0x92, 0xac, 0xad, 0xab, 0x7c, 0x94, 0xbb, ++ 0x8f, 0x44, 0xb0, 0xf5, 0x85, 0xa4, 0x8c, 0xf3, 0x69, 0xa4, 0x82, 0x96, ++ 0xde, 0xfa, 0xa1, 0xd8, 0x8a, 0xa7, 0xd2, 0x5b, 0x40, 0xb5, 0x40, 0xaa, ++ 0xc1, 0xd2, 0xb4, 0xb1, 0xc5, 0x2a, 0xf6, 0xe4, 0x29, 0x9f, 0x8b, 0xbc, ++ 0xb2, 0x7a, 0xeb, 0x38, 0xf5, 0xa9, 0x15, 0x06, 0xf3, 0x42, 0x20, 0x45, ++ 0xf7, 0xa8, 0xd2, 0x40, 0x7c, 0x79, 0xa2, 0xf9, 0x69, 0xea, 0x35, 0x02, ++ 0x18, 0x26, 0x1e, 0x69, 0xb4, 0x9e, 0x7f, 0xf0, 0xad, 0xe6, 0xcb, 0xab, ++ 0xda, 0x8f, 0xf4, 0x62, 0x15, 0x71, 0xc6, 0x86, 0x81, 0xb9, 0x7c, 0x2f, ++ 0x61, 0xd3, 0x00, 0xaf, 0xbf, 0x8c, 0xf1, 0x34, 0xdf, 0x4d, 0xd3, 0xb8, ++ 0x48, 0xf5, 0x7c, 0x85, 0xd0, 0xa7, 0x27, 0xc0, 0xe9, 0xd9, 0xe6, 0xbc, ++ 0xef, 0xd3, 0xb5, 0x77, 0xa0, 0x9f, 0x1d, 0x04, 0xdb, 0x70, 0x19, 0xd7, ++ 0x15, 0x6d, 0x99, 0x26, 0xce, 0xa6, 0x2e, 0x6e, 0xc0, 0x87, 0x68, 0xe2, ++ 0x43, 0x17, 0xf5, 0xba, 0xc9, 0xff, 0x65, 0xd1, 0x03, 0xb4, 0x57, 0x84, ++ 0xe6, 0x0c, 0xd3, 0x33, 0x48, 0x73, 0x5e, 0xeb, 0x6f, 0x2a, 0xb4, 0x52, ++ 0x3f, 0xff, 0x38, 0xdd, 0x49, 0xb4, 0xd7, 0xa6, 0x2d, 0x42, 0x4f, 0x9d, ++ 0x17, 0x3a, 0xf5, 0xf6, 0xd4, 0xaf, 0x25, 0x4a, 0xfb, 0xb5, 0xe5, 0xe6, ++ 0x12, 0xaf, 0x95, 0xf6, 0x5c, 0x40, 0xbd, 0xb3, 0xd6, 0xc0, 0x75, 0x00, ++ 0xd5, 0x75, 0x89, 0xb7, 0xdc, 0x82, 0xca, 0x31, 0xb6, 0xc5, 0x70, 0x9a, ++ 0xba, 0x7b, 0x43, 0xc3, 0x70, 0xae, 0x4b, 0x3c, 0x9a, 0x96, 0x66, 0x2a, ++ 0xd1, 0x8b, 0x77, 0xdb, 0xbf, 0x2c, 0x7a, 0xd5, 0x3f, 0xc1, 0xe6, 0x85, ++ 0xc3, 0x48, 0xad, 0x4c, 0x11, 0x1e, 0x35, 0xf2, 0xb7, 0x1f, 0x77, 0xaa, ++ 0x44, 0xa9, 0x16, 0xe3, 0x7e, 0x8b, 0x58, 0x99, 0xd3, 0xc3, 0xa5, 0x38, ++ 0x76, 0x89, 0x34, 0xd5, 0x10, 0x5c, 0x8f, 0xee, 0x4a, 0x4a, 0x5f, 0x0b, ++ 0xc0, 0x45, 0x2c, 0x6e, 0x53, 0x1d, 0xf9, 0x09, 0x0e, 0xab, 0xff, 0xed, ++ 0x1e, 0x33, 0x2a, 0x70, 0xed, 0xa2, 0x30, 0xa6, 0x56, 0x72, 0xde, 0x2d, ++ 0x17, 0x7d, 0x69, 0x97, 0x7a, 0x4f, 0x17, 0xfc, 0x7b, 0xfb, 0x4f, 0xe9, ++ 0xef, 0x82, 0x19, 0x14, 0xbe, 0x7a, 0x19, 0x2d, 0x2d, 0x55, 0xa4, 0xc7, ++ 0x0c, 0x8e, 0xaa, 0xd5, 0x38, 0xfd, 0x3f, 0x95, 0x7d, 0x0b, 0x70, 0x53, ++ 0x67, 0x96, 0xe6, 0x77, 0x25, 0xd9, 0x96, 0x9f, 0x5c, 0x1b, 0x01, 0x32, ++ 0x10, 0xb8, 0x42, 0x57, 0x58, 0x8d, 0x4d, 0x72, 0x05, 0x66, 0x62, 0x7a, ++ 0xb5, 0x83, 0x3a, 0x31, 0xc4, 0x09, 0x90, 0x18, 0x42, 0x6a, 0x9d, 0xda, ++ 0xd9, 0x8d, 0x43, 0x80, 0xd0, 0x24, 0xdd, 0x71, 0x68, 0x76, 0xcb, 0x3d, ++ 0xd5, 0x85, 0xef, 0x98, 0x97, 0x01, 0xbd, 0x78, 0x25, 0xb0, 0x53, 0xbb, ++ 0x11, 0xb6, 0x79, 0x74, 0x22, 0x5b, 0x24, 0x9d, 0xa9, 0x72, 0xba, 0x66, ++ 0x0b, 0x37, 0x98, 0x40, 0x3a, 0x0f, 0xd2, 0x33, 0x3d, 0x5d, 0xcc, 0x56, ++ 0x76, 0xc3, 0xf2, 0x4e, 0x9a, 0xbc, 0xbb, 0xb7, 0xc9, 0x24, 0x9d, 0xbb, ++ 0xdf, 0xb9, 0x57, 0x02, 0x43, 0x91, 0x4c, 0x0d, 0x55, 0x2a, 0x21, 0xe9, ++ 0xde, 0xff, 0x71, 0x1e, 0xdf, 0xf9, 0xce, 0x39, 0xff, 0x85, 0xf0, 0x17, ++ 0x8c, 0xc1, 0x65, 0xb4, 0x5f, 0x2f, 0xf3, 0x5b, 0x1f, 0x5e, 0x55, 0x7d, ++ 0xb4, 0xcd, 0xe1, 0x5a, 0x89, 0xb7, 0xc2, 0x41, 0x0f, 0x91, 0xa3, 0x9e, ++ 0xf5, 0xb8, 0x30, 0x86, 0x38, 0xee, 0x26, 0x8f, 0x2e, 0x3d, 0x50, 0x8e, ++ 0x31, 0xfb, 0x5b, 0x94, 0xc1, 0x78, 0x61, 0x7d, 0x2a, 0xaa, 0x0e, 0x34, ++ 0x2b, 0x3f, 0x8f, 0xeb, 0x28, 0x1d, 0x80, 0x2a, 0xf5, 0xfc, 0xc3, 0xd9, ++ 0xd1, 0x6b, 0x76, 0xad, 0x21, 0x8b, 0xec, 0x28, 0xa1, 0x60, 0x5f, 0xd4, ++ 0x03, 0xed, 0xff, 0xa4, 0x70, 0x3d, 0xe4, 0x69, 0x1e, 0x8e, 0x97, 0xd8, ++ 0x7f, 0xd1, 0xea, 0xf7, 0xf9, 0xb0, 0x2d, 0x27, 0xf3, 0x75, 0xd6, 0xd8, ++ 0x7e, 0x91, 0x0b, 0x2b, 0xcb, 0x92, 0x1a, 0x96, 0x0d, 0x7a, 0x94, 0xfb, ++ 0xc8, 0xa1, 0x9a, 0x93, 0xc0, 0x16, 0xbb, 0xee, 0xeb, 0xc1, 0x46, 0x86, ++ 0xc5, 0xc7, 0xc8, 0xd5, 0xbd, 0x8d, 0xeb, 0x71, 0x65, 0xac, 0x83, 0x8d, ++ 0x75, 0xbc, 0xe6, 0x82, 0xb1, 0x32, 0xcf, 0xd9, 0xaa, 0x94, 0x79, 0xcf, ++ 0xc1, 0x5b, 0x1b, 0xbd, 0x8a, 0xb9, 0xf4, 0xff, 0x30, 0xff, 0x3e, 0x26, ++ 0x7a, 0x05, 0x9f, 0x24, 0xc4, 0x36, 0xde, 0x62, 0xcc, 0xb2, 0xac, 0x6b, ++ 0xb3, 0xe1, 0x2d, 0x8b, 0x9e, 0x8a, 0x3c, 0x90, 0xb0, 0xac, 0x0a, 0xc6, ++ 0xcc, 0x26, 0x77, 0xa0, 0x07, 0x8e, 0x8d, 0x74, 0x34, 0x29, 0x81, 0xd5, ++ 0x9f, 0x29, 0x81, 0x70, 0x16, 0x81, 0xb6, 0x41, 0xa5, 0xde, 0xe0, 0xbb, ++ 0xff, 0x1e, 0x25, 0xa0, 0xad, 0xb2, 0x6d, 0xe6, 0x2a, 0xbe, 0x67, 0xdb, ++ 0xcc, 0x15, 0xea, 0x5a, 0xde, 0xdf, 0x8a, 0x84, 0xec, 0xf7, 0x53, 0x11, ++ 0x3d, 0x2b, 0xb1, 0x65, 0x98, 0xb1, 0xa5, 0xde, 0xc6, 0xc8, 0x8d, 0x29, ++ 0xe1, 0x49, 0x23, 0x76, 0x2d, 0x77, 0x9b, 0x5d, 0x77, 0x1b, 0xa1, 0x4d, ++ 0xe8, 0xdc, 0x8b, 0xd6, 0x3e, 0x35, 0xea, 0xc3, 0x85, 0x9c, 0xbd, 0x76, ++ 0xa9, 0x8b, 0xc6, 0xc8, 0xa3, 0x94, 0x93, 0x59, 0xf9, 0xf8, 0x5f, 0x2c, ++ 0x73, 0xa9, 0xd8, 0x4b, 0x4c, 0x49, 0x4d, 0x37, 0xb1, 0x77, 0xba, 0x69, ++ 0x91, 0xb3, 0xf7, 0x5c, 0x51, 0xf4, 0x53, 0x5e, 0x77, 0xac, 0xb6, 0x16, ++ 0x5d, 0x70, 0xcd, 0x8e, 0x3d, 0x5b, 0xcd, 0xf7, 0x8b, 0x11, 0x68, 0x95, ++ 0xb4, 0xad, 0x17, 0xe7, 0x84, 0x5a, 0x96, 0x23, 0xd4, 0x7e, 0x42, 0x09, ++ 0x65, 0xb6, 0x29, 0xa1, 0xb6, 0x19, 0x8a, 0xe1, 0x7d, 0x33, 0x6b, 0x78, ++ 0x7f, 0x9b, 0x7d, 0xa0, 0x46, 0xb0, 0xac, 0x78, 0xd6, 0x33, 0xd6, 0x0a, ++ 0x9f, 0xe8, 0x69, 0xe6, 0x14, 0xc7, 0x5f, 0x6f, 0xb5, 0x27, 0x15, 0x95, ++ 0x51, 0xdd, 0x48, 0x60, 0x3e, 0xf3, 0x2c, 0xe1, 0x88, 0xd6, 0xd1, 0x31, ++ 0xba, 0x1e, 0x7e, 0x86, 0x7c, 0x39, 0xa3, 0x5a, 0x5b, 0xfc, 0x9c, 0xbf, ++ 0x93, 0x17, 0x6a, 0xe3, 0xdb, 0xe1, 0x25, 0xff, 0xef, 0xe1, 0xf7, 0x9a, ++ 0x2d, 0xf7, 0xc6, 0x4a, 0x67, 0xbc, 0xd3, 0x16, 0x63, 0x12, 0xf7, 0xf1, ++ 0x56, 0x7e, 0xbc, 0x5d, 0x63, 0x9d, 0xef, 0x99, 0xa4, 0x96, 0x15, 0xf4, ++ 0x53, 0x41, 0x79, 0xfc, 0x05, 0x2e, 0xe4, 0xf5, 0x73, 0x3f, 0x75, 0x52, ++ 0x1e, 0xbd, 0x80, 0xa7, 0x12, 0xc2, 0xa5, 0xce, 0x92, 0x4b, 0x59, 0x56, ++ 0x5d, 0x24, 0x30, 0xfc, 0xa4, 0x22, 0x18, 0x57, 0x1f, 0x2b, 0x71, 0x07, ++ 0x4e, 0x5d, 0xa0, 0x4e, 0xc2, 0x6e, 0x91, 0xdb, 0x05, 0x34, 0xd9, 0x32, ++ 0x3e, 0x8b, 0x48, 0xf6, 0x78, 0x7e, 0x8e, 0x2a, 0xe5, 0xb1, 0xe7, 0xaa, ++ 0x94, 0x16, 0x5b, 0xcf, 0x7f, 0xa0, 0x9e, 0x0b, 0xba, 0x15, 0x5d, 0x7f, ++ 0x6a, 0xeb, 0xba, 0xa0, 0xdf, 0x6b, 0xb3, 0x6f, 0xd5, 0xb1, 0xe8, 0xb6, ++ 0xa0, 0xe7, 0xeb, 0xfa, 0xa5, 0xae, 0x65, 0x8e, 0x3f, 0xe4, 0xf5, 0xfb, ++ 0x29, 0xf5, 0x7b, 0xb4, 0x46, 0xf0, 0x57, 0xf4, 0x5e, 0x45, 0xbc, 0x7b, ++ 0x87, 0x7a, 0x3c, 0x16, 0x72, 0xb0, 0x6f, 0x9a, 0xf4, 0x0b, 0xec, 0x5a, ++ 0x71, 0x61, 0x8f, 0x1e, 0x72, 0x7d, 0x15, 0xdb, 0x99, 0x9f, 0xd5, 0x8f, ++ 0x73, 0xd6, 0x77, 0xd7, 0x73, 0xb2, 0xa6, 0xbf, 0xb7, 0xd7, 0x54, 0x19, ++ 0x1d, 0x8a, 0x0c, 0x24, 0x24, 0x0f, 0x0f, 0xb4, 0x0e, 0x3a, 0x76, 0x66, ++ 0x3c, 0x48, 0xfc, 0xe8, 0x55, 0x02, 0xfe, 0xcd, 0xf6, 0xbc, 0x7f, 0x1f, ++ 0x99, 0x61, 0xcf, 0x3b, 0x14, 0x09, 0x5e, 0xdf, 0x63, 0x4c, 0xd9, 0x18, ++ 0x27, 0x77, 0x53, 0x9c, 0x5a, 0xc1, 0x8f, 0xe8, 0x83, 0x99, 0xa2, 0xc9, ++ 0x52, 0xf7, 0x45, 0x7f, 0xb6, 0x1c, 0xbd, 0x19, 0xa8, 0x55, 0xfc, 0xfe, ++ 0xc7, 0xd9, 0xdb, 0x61, 0xc4, 0x04, 0xbc, 0xa4, 0x9a, 0x99, 0x12, 0x94, ++ 0x13, 0x47, 0xab, 0xac, 0x83, 0x3e, 0xf1, 0x2d, 0x33, 0x5c, 0x82, 0x80, ++ 0xf1, 0x77, 0xb6, 0x8f, 0x29, 0x18, 0xce, 0x98, 0x2a, 0x3f, 0xab, 0xa4, ++ 0x74, 0x78, 0x28, 0x5d, 0xc4, 0xfc, 0xc0, 0xf6, 0x77, 0xc4, 0x32, 0x3e, ++ 0xb1, 0x01, 0xeb, 0x59, 0xdd, 0xfa, 0x46, 0x1b, 0xef, 0xc3, 0x8e, 0x51, ++ 0x7e, 0x69, 0xe6, 0x9e, 0xe1, 0xbb, 0x70, 0xdb, 0x40, 0xfb, 0x1e, 0x97, ++ 0xf8, 0xb4, 0x42, 0xff, 0x45, 0xbb, 0x3f, 0xaa, 0xf9, 0xcb, 0x99, 0xfb, ++ 0x94, 0xe9, 0x1e, 0xed, 0x43, 0x84, 0x4e, 0xad, 0x50, 0x02, 0xe6, 0x73, ++ 0x2e, 0xd7, 0xd7, 0xc5, 0x70, 0xc6, 0x9c, 0x7a, 0x50, 0xf3, 0xd7, 0xe6, ++ 0x7e, 0x2a, 0x6b, 0x23, 0x9e, 0xbc, 0x26, 0xf6, 0x71, 0x9b, 0x35, 0xcb, ++ 0x3e, 0xa1, 0xac, 0x88, 0xff, 0x25, 0xba, 0x25, 0x27, 0xb4, 0x73, 0xa3, ++ 0x16, 0xb4, 0x67, 0xa1, 0xac, 0x8a, 0x0f, 0x97, 0x9c, 0x30, 0x8a, 0x68, ++ 0x8f, 0xf2, 0xdd, 0x22, 0x7e, 0xd7, 0xca, 0x57, 0xa1, 0xb7, 0xb4, 0x8c, ++ 0x7f, 0x8f, 0xd9, 0xd7, 0xad, 0x8e, 0xa3, 0xa9, 0x24, 0xf2, 0xa5, 0x75, ++ 0x56, 0x75, 0xf2, 0x2a, 0x97, 0x2e, 0xd7, 0x34, 0xcb, 0x6f, 0x69, 0xa9, ++ 0xf9, 0x2d, 0x6f, 0x0c, 0x69, 0xdd, 0xf6, 0x3c, 0x1a, 0x56, 0x64, 0x35, ++ 0xac, 0x14, 0x99, 0xda, 0xfd, 0xc3, 0xeb, 0x39, 0x36, 0xd7, 0xa4, 0xe0, ++ 0x5e, 0x5e, 0xb7, 0xc1, 0xfe, 0x4e, 0x43, 0x73, 0xf6, 0x8c, 0xdd, 0xbb, ++ 0x62, 0x5c, 0x24, 0x7e, 0x6b, 0x8c, 0x9d, 0x85, 0x58, 0x29, 0xb1, 0x34, ++ 0xa6, 0xec, 0x8c, 0xb7, 0x28, 0xe9, 0x78, 0x15, 0xe7, 0x72, 0x31, 0x02, ++ 0x5a, 0x08, 0xce, 0x7a, 0x14, 0xcb, 0x55, 0x3d, 0xec, 0x71, 0x8d, 0xc1, ++ 0xaa, 0xf0, 0x58, 0xfa, 0xd4, 0xdd, 0x58, 0x13, 0x2e, 0xa6, 0xcc, 0x92, ++ 0x78, 0x92, 0x12, 0x5f, 0x1d, 0x9e, 0x09, 0x2c, 0x29, 0x25, 0xf6, 0x75, ++ 0xda, 0xb9, 0x79, 0x71, 0x54, 0xea, 0x7d, 0x47, 0x04, 0xeb, 0xe1, 0xf4, ++ 0x47, 0x39, 0xc7, 0xb7, 0xd6, 0x11, 0x1e, 0xa5, 0xe0, 0x9a, 0x50, 0xa9, ++ 0xcf, 0xc1, 0x53, 0xe1, 0x22, 0xb4, 0x57, 0x8b, 0x3c, 0xa7, 0x92, 0xdb, ++ 0x7f, 0x66, 0x3d, 0xed, 0x73, 0xd6, 0x2f, 0x78, 0x3d, 0xc4, 0x7d, 0xa1, ++ 0xc4, 0x54, 0x5e, 0x63, 0x5e, 0x31, 0x2b, 0x47, 0x0e, 0x47, 0x6e, 0x52, ++ 0x43, 0xba, 0x28, 0x1c, 0x4e, 0xcb, 0x79, 0x11, 0x39, 0x54, 0x86, 0x79, ++ 0x7d, 0xe5, 0x98, 0xd5, 0xa7, 0xc2, 0x38, 0xa4, 0xf3, 0xbb, 0x30, 0x5f, ++ 0x43, 0x4a, 0x6f, 0xf6, 0xbb, 0xe6, 0x0e, 0x62, 0x85, 0x5a, 0x4e, 0x3e, ++ 0xf1, 0x3b, 0x6b, 0xa5, 0xcf, 0xb2, 0xfc, 0xb3, 0x34, 0x31, 0x33, 0xce, ++ 0x77, 0xf5, 0x9b, 0x5d, 0xa9, 0x22, 0x74, 0x91, 0x57, 0x7e, 0x39, 0xfb, ++ 0xb4, 0xa5, 0xd9, 0xb5, 0xb4, 0x42, 0xed, 0x8f, 0x31, 0x2c, 0xdf, 0xc7, ++ 0x08, 0xcf, 0x71, 0x7a, 0x00, 0xab, 0x7b, 0x8b, 0xf0, 0x24, 0xaf, 0x3d, ++ 0x67, 0xb8, 0xf2, 0x3a, 0xb6, 0xfb, 0x54, 0x78, 0x6a, 0xa7, 0x46, 0x5b, ++ 0xb5, 0xb0, 0x26, 0x52, 0x86, 0x05, 0xe3, 0x9c, 0x7d, 0xf4, 0x73, 0x1f, ++ 0xa6, 0xc7, 0x54, 0x06, 0x1a, 0x8b, 0x50, 0xc5, 0xf5, 0x57, 0x90, 0x67, ++ 0xbc, 0x32, 0x50, 0x8e, 0xc1, 0xfd, 0x43, 0x4a, 0x36, 0xeb, 0x5c, 0xd3, ++ 0x67, 0xd7, 0x4f, 0x4c, 0x25, 0xd7, 0x28, 0xf9, 0x00, 0xf0, 0xf9, 0x00, ++ 0xf3, 0x6b, 0xc6, 0xa8, 0xcf, 0x0e, 0x94, 0xe1, 0x8b, 0xfd, 0xe5, 0x7c, ++ 0xa9, 0xf8, 0xf4, 0x80, 0x8e, 0xb3, 0x03, 0xcd, 0xca, 0xcb, 0x71, 0xa8, ++ 0xc2, 0x7b, 0x3e, 0x1b, 0x18, 0x52, 0x8e, 0x7c, 0xe7, 0x5e, 0x07, 0xac, ++ 0x1f, 0xa9, 0x26, 0xe7, 0xfc, 0x5b, 0xeb, 0xc7, 0xa3, 0xe4, 0x3a, 0x7a, ++ 0xae, 0x1a, 0xbd, 0x1c, 0x9f, 0xef, 0x97, 0x79, 0x64, 0xfc, 0x66, 0xe5, ++ 0x17, 0x71, 0x91, 0x6f, 0x0d, 0xbe, 0x38, 0x20, 0x72, 0xfc, 0xe3, 0x58, ++ 0xc9, 0xf9, 0x8e, 0xa6, 0x86, 0x94, 0xe3, 0xf9, 0x7b, 0xfe, 0x91, 0xba, ++ 0x58, 0x4b, 0x2e, 0xd4, 0x4e, 0xa0, 0xa9, 0xa1, 0x5d, 0x3e, 0x7b, 0xd0, ++ 0x45, 0xee, 0x58, 0x86, 0xb5, 0xbd, 0xe5, 0x78, 0x96, 0xb4, 0xb3, 0xe3, ++ 0x60, 0xb3, 0xf2, 0x6e, 0x5c, 0xea, 0x18, 0x3a, 0x3a, 0x06, 0xc3, 0xbc, ++ 0x6e, 0x48, 0x39, 0x9d, 0x35, 0x7c, 0xce, 0x38, 0x0e, 0x06, 0xac, 0xe2, ++ 0x58, 0xc3, 0x1c, 0x6b, 0x39, 0x73, 0x55, 0xc6, 0x8d, 0xf5, 0xaf, 0x93, ++ 0xc8, 0x2c, 0xcd, 0xda, 0xf5, 0xb1, 0x26, 0x31, 0xe2, 0x92, 0xa8, 0x77, ++ 0xfd, 0xe5, 0xb8, 0xcd, 0xb7, 0x95, 0x17, 0x1b, 0x5d, 0x76, 0x2d, 0xf5, ++ 0x2d, 0xf2, 0xae, 0xfb, 0xe8, 0x2b, 0x4b, 0x28, 0x8f, 0x45, 0x94, 0x47, ++ 0x33, 0xe5, 0xd1, 0xca, 0xf5, 0xbe, 0x14, 0x17, 0xfc, 0x0a, 0x84, 0x63, ++ 0x8a, 0x8e, 0x85, 0x03, 0x32, 0x86, 0x3d, 0x0f, 0x73, 0x60, 0xcf, 0xfa, ++ 0x8d, 0xf1, 0x5b, 0xe5, 0x22, 0x58, 0x23, 0x5c, 0x56, 0x64, 0x13, 0x26, ++ 0xfe, 0x0c, 0x29, 0x83, 0x03, 0x76, 0x2f, 0x69, 0xbd, 0x96, 0x29, 0xf8, ++ 0x4e, 0xb9, 0xf8, 0x27, 0xed, 0xb9, 0x59, 0xd9, 0x1b, 0x77, 0xa1, 0x56, ++ 0x77, 0x7e, 0x9f, 0x9b, 0x91, 0x77, 0xef, 0xfa, 0x59, 0x36, 0xbe, 0x79, ++ 0xd6, 0x37, 0x5d, 0xdf, 0xd3, 0x90, 0xf2, 0xbe, 0xf0, 0x0a, 0xda, 0xe9, ++ 0x49, 0xae, 0xb5, 0x54, 0x74, 0x97, 0xa5, 0xee, 0xb8, 0xd6, 0xcf, 0xfa, ++ 0xcb, 0xf0, 0x41, 0xa6, 0x9c, 0x2f, 0xca, 0xb6, 0x9f, 0xba, 0xcb, 0x36, ++ 0x2b, 0xa7, 0x6c, 0xf9, 0x86, 0x71, 0x85, 0x73, 0x1f, 0xbb, 0x3e, 0x86, ++ 0xd3, 0x17, 0x76, 0x7a, 0xc2, 0x05, 0xff, 0xe5, 0xe7, 0x94, 0xec, 0xcd, ++ 0x54, 0x62, 0xd7, 0xfb, 0xba, 0x52, 0x4b, 0x95, 0x33, 0x07, 0x76, 0x0d, ++ 0xc8, 0x2f, 0xd8, 0xd0, 0x2d, 0xf6, 0xa7, 0xde, 0xa3, 0x31, 0x2f, 0xf1, ++ 0xaf, 0xc4, 0x57, 0x96, 0xe9, 0x8b, 0xd1, 0xa3, 0x9c, 0x5e, 0x7e, 0x3b, ++ 0x63, 0xdc, 0x70, 0xbe, 0xfe, 0xd3, 0x4b, 0xbe, 0xf0, 0x3a, 0x39, 0x35, ++ 0x4d, 0x08, 0xdd, 0xd9, 0xaf, 0xac, 0x61, 0x1f, 0x39, 0x88, 0x7e, 0xbd, ++ 0x56, 0x2b, 0x31, 0xd2, 0xea, 0xe3, 0x6f, 0x9b, 0xb3, 0xc8, 0xff, 0xb1, ++ 0x2c, 0x17, 0x39, 0xfa, 0x13, 0xfa, 0xbf, 0x58, 0xcb, 0x6f, 0xba, 0xf6, ++ 0xdb, 0x7b, 0xe0, 0x1b, 0x1a, 0x43, 0x58, 0x99, 0xe6, 0x9a, 0x5d, 0x1a, ++ 0x7a, 0x1b, 0x9d, 0xda, 0xf8, 0xf2, 0x4c, 0x60, 0x54, 0x8f, 0xfa, 0x7f, ++ 0x54, 0xe4, 0xfb, 0xd7, 0xb4, 0x83, 0x6b, 0x1c, 0xc7, 0xb6, 0x01, 0xf4, ++ 0xe6, 0x2c, 0xc4, 0xc9, 0xe9, 0x06, 0xf8, 0x7a, 0xc7, 0x80, 0x59, 0x4e, ++ 0x1b, 0x59, 0x91, 0x10, 0x9f, 0x71, 0x56, 0xf2, 0xf3, 0x54, 0x58, 0x59, ++ 0x9d, 0xa0, 0x37, 0x32, 0x77, 0x3e, 0xc4, 0x57, 0x7f, 0x4a, 0xfa, 0x08, ++ 0x2e, 0x62, 0x55, 0x19, 0x36, 0x31, 0x4b, 0xe9, 0x4b, 0x21, 0xb6, 0x6f, ++ 0x8e, 0xd4, 0x19, 0xcb, 0x39, 0x1f, 0x30, 0xc4, 0x6b, 0xb2, 0x7c, 0x1d, ++ 0xe4, 0x2b, 0x47, 0x5f, 0xe0, 0x7c, 0x08, 0xd3, 0x9f, 0x62, 0x03, 0x24, ++ 0xe3, 0x03, 0x61, 0x0c, 0x53, 0x37, 0x5f, 0xf6, 0x93, 0x2f, 0x1c, 0xaa, ++ 0xc1, 0xc7, 0x07, 0x9c, 0xb3, 0x18, 0x2b, 0x07, 0xa4, 0xb7, 0x2b, 0x7b, ++ 0x93, 0x5e, 0xbc, 0xe8, 0xa2, 0x14, 0x87, 0xd2, 0x35, 0x76, 0x3f, 0xfe, ++ 0xbc, 0xc1, 0x71, 0x55, 0xe9, 0x17, 0xb7, 0xe2, 0x70, 0x3c, 0xa8, 0x49, ++ 0x6d, 0xd0, 0xf4, 0x88, 0x7e, 0x1a, 0xf1, 0x62, 0xbc, 0xd0, 0x0b, 0x0c, ++ 0xb6, 0xfc, 0x1a, 0x45, 0xd0, 0x8a, 0x6a, 0xe8, 0xff, 0xf2, 0x5b, 0x01, ++ 0xb7, 0x65, 0xbf, 0xef, 0xe5, 0x7b, 0xdf, 0xb7, 0x7e, 0x2f, 0x75, 0xd0, ++ 0x06, 0xa9, 0x81, 0xf4, 0x64, 0x60, 0xd8, 0x58, 0x7c, 0xa0, 0x2e, 0x90, ++ 0x36, 0x21, 0xf5, 0x65, 0xa9, 0x8f, 0x86, 0x29, 0x63, 0xe9, 0x85, 0xa8, ++ 0xcc, 0x2b, 0xff, 0x96, 0x38, 0xe3, 0x95, 0x9a, 0x30, 0x2e, 0x34, 0x32, ++ 0x27, 0x4e, 0x7b, 0x71, 0xc2, 0xf8, 0x21, 0x32, 0x3e, 0x95, 0x32, 0xf1, ++ 0x9a, 0x7e, 0xe9, 0xb9, 0xdc, 0x2d, 0xfd, 0x4c, 0x2f, 0x3e, 0x8e, 0xb8, ++ 0x30, 0x3c, 0x8e, 0xa4, 0x43, 0x97, 0xbc, 0x5c, 0x7a, 0xb1, 0xd5, 0x58, ++ 0xb9, 0xa3, 0x06, 0x6b, 0x76, 0x98, 0x58, 0x35, 0x67, 0x19, 0xde, 0x27, ++ 0x97, 0xbe, 0x3f, 0x12, 0xd0, 0xc2, 0xe4, 0xaf, 0x7d, 0x86, 0x49, 0xb6, ++ 0x14, 0x08, 0x2f, 0x47, 0xfd, 0xa9, 0xa3, 0xdc, 0x97, 0xc3, 0x89, 0xfe, ++ 0x0a, 0xef, 0xee, 0x5e, 0xc6, 0x3c, 0xc7, 0xb2, 0x2a, 0x67, 0x05, 0x3b, ++ 0x2e, 0x2a, 0xf5, 0x74, 0xf7, 0xdd, 0x4c, 0x02, 0x9c, 0xdf, 0xfe, 0x99, ++ 0x39, 0x60, 0x70, 0xb6, 0x07, 0x96, 0xb1, 0x8e, 0x7c, 0xdb, 0x64, 0x94, ++ 0x9b, 0x8c, 0xc3, 0xa9, 0x7a, 0x75, 0x35, 0x1e, 0x42, 0xac, 0xd5, 0x43, ++ 0x79, 0x05, 0xd5, 0x55, 0x30, 0xb1, 0xa0, 0xc1, 0x25, 0x3e, 0x6d, 0xc6, ++ 0xf8, 0x77, 0x55, 0xbf, 0xd1, 0x87, 0x91, 0xfe, 0xdc, 0xaa, 0x46, 0xe9, ++ 0x73, 0x55, 0xe0, 0x24, 0x75, 0x71, 0x2a, 0x1d, 0x5b, 0x4d, 0x33, 0x55, ++ 0x9e, 0x6c, 0xec, 0xc2, 0xd4, 0x88, 0x17, 0xef, 0x33, 0x98, 0xcd, 0x65, ++ 0xfe, 0xdb, 0x54, 0x67, 0xe0, 0x4c, 0x96, 0x6b, 0xe9, 0x8f, 0x72, 0x2d, ++ 0x55, 0x30, 0x9e, 0x0b, 0x74, 0x7c, 0xaa, 0x90, 0xc3, 0x64, 0xa3, 0x78, ++ 0x2b, 0x2e, 0x67, 0x5a, 0x26, 0xe3, 0x4d, 0xfa, 0xda, 0x0c, 0xf2, 0xea, ++ 0x0f, 0x39, 0xce, 0xf7, 0x92, 0x1e, 0x7c, 0x90, 0xa5, 0x0c, 0xa9, 0xf3, ++ 0x7e, 0x63, 0x16, 0xcc, 0x65, 0x1a, 0x0e, 0xee, 0x7a, 0x90, 0x1c, 0xe1, ++ 0x41, 0xbc, 0x91, 0x7e, 0xdf, 0x92, 0xde, 0x94, 0x3f, 0xea, 0xa5, 0x3f, ++ 0x52, 0x76, 0x94, 0x72, 0xe5, 0xdd, 0x72, 0x66, 0x41, 0xd7, 0x7a, 0xb9, ++ 0xef, 0x11, 0x7e, 0x37, 0x37, 0xd9, 0x84, 0xd7, 0x06, 0x7c, 0x18, 0x93, ++ 0x32, 0x70, 0x24, 0x21, 0x73, 0x35, 0x82, 0xf8, 0x80, 0xec, 0x0e, 0x0b, ++ 0xdb, 0x23, 0x0d, 0x58, 0x53, 0x0d, 0x65, 0xfe, 0xf4, 0x57, 0xf3, 0xfb, ++ 0x68, 0x1a, 0xd5, 0x03, 0x96, 0x3c, 0xcf, 0xa9, 0xd9, 0xbd, 0x92, 0xa2, ++ 0x3e, 0x53, 0xd4, 0xdb, 0x75, 0x3d, 0xdb, 0x75, 0x4c, 0xe5, 0x8a, 0xf1, ++ 0xef, 0x81, 0x6a, 0x9f, 0xdd, 0xb7, 0xda, 0x16, 0x0f, 0xb6, 0xac, 0xc1, ++ 0x2e, 0x4b, 0x2b, 0x92, 0xf5, 0xb4, 0x61, 0x43, 0xd6, 0x18, 0x27, 0xb5, ++ 0xac, 0x43, 0x29, 0xbf, 0xab, 0x44, 0x7f, 0xd9, 0x6a, 0x57, 0x83, 0xea, ++ 0x25, 0xca, 0xb4, 0x37, 0xf5, 0x08, 0xbf, 0x0f, 0xaa, 0x0b, 0xe0, 0xe8, ++ 0xb7, 0x92, 0xfa, 0xbd, 0x64, 0xaf, 0x53, 0xd6, 0xfd, 0x5d, 0x6b, 0xfd, ++ 0x9d, 0xb5, 0x66, 0x9c, 0xac, 0xd5, 0xb4, 0x8a, 0x75, 0x5d, 0x3d, 0x08, ++ 0x39, 0x4b, 0x12, 0xc6, 0x34, 0xc6, 0x93, 0xba, 0x64, 0x17, 0x75, 0x5e, ++ 0x41, 0x7f, 0x0d, 0x5c, 0x5b, 0x81, 0x77, 0x71, 0x99, 0x71, 0x34, 0x9c, ++ 0x0c, 0xe3, 0x85, 0xdc, 0x76, 0xce, 0xf5, 0x5b, 0x5c, 0xc9, 0x2d, 0xe5, ++ 0xbb, 0xdf, 0xb5, 0xbc, 0xc1, 0x8b, 0x60, 0xd2, 0xf1, 0xeb, 0xee, 0xc6, ++ 0x65, 0xb8, 0x37, 0x2b, 0x7b, 0x7e, 0x93, 0x7b, 0x35, 0x10, 0xcb, 0xca, ++ 0xde, 0x13, 0xf4, 0x41, 0xd9, 0x7b, 0xcd, 0xbf, 0xb2, 0xf7, 0x36, 0x98, ++ 0xd4, 0x4d, 0x3c, 0xfd, 0x27, 0xe6, 0xe2, 0x92, 0x87, 0x7b, 0xb1, 0x3d, ++ 0x53, 0xd8, 0xef, 0x32, 0x9c, 0x89, 0x2f, 0x96, 0x3d, 0xfa, 0x8b, 0xdc, ++ 0x05, 0x0c, 0xac, 0xc4, 0xc1, 0xb4, 0x8a, 0x93, 0x46, 0x05, 0xce, 0xaa, ++ 0x72, 0xbe, 0xc7, 0x6b, 0xd7, 0x6c, 0x9a, 0xe3, 0x5e, 0xf4, 0xf1, 0xb5, ++ 0x82, 0xd6, 0x2a, 0x7d, 0x80, 0x13, 0xc6, 0x64, 0x62, 0xd6, 0xad, 0xfe, ++ 0x24, 0xbf, 0xa9, 0xd0, 0xaa, 0x6b, 0xf0, 0xa6, 0x21, 0xfc, 0x49, 0x7e, ++ 0x97, 0x73, 0x30, 0x5e, 0x1c, 0x62, 0xae, 0x59, 0x9c, 0xf8, 0xa3, 0x75, ++ 0xc9, 0x27, 0xd7, 0xdf, 0xba, 0xfe, 0x5b, 0xc7, 0x91, 0xf3, 0x1e, 0x1f, ++ 0x50, 0x86, 0x79, 0x0c, 0x56, 0xa6, 0x8c, 0x73, 0x70, 0x4b, 0xf0, 0x78, ++ 0x62, 0x65, 0x1e, 0xc3, 0xc8, 0x8b, 0x3b, 0xdb, 0x88, 0xa7, 0x8c, 0x35, ++ 0xad, 0xff, 0x75, 0xa3, 0x2e, 0xb5, 0x42, 0xb3, 0xed, 0x1e, 0xe6, 0xad, ++ 0x6e, 0x3b, 0x66, 0xa8, 0xeb, 0x9d, 0x9c, 0xca, 0xb7, 0x5e, 0xb7, 0xdf, ++ 0xfd, 0xeb, 0xa7, 0xd9, 0xef, 0x93, 0xd7, 0x07, 0x33, 0x37, 0x70, 0xd7, ++ 0xe1, 0x7e, 0xf6, 0x59, 0x32, 0xf4, 0x18, 0xa6, 0x72, 0x5f, 0xa3, 0xc4, ++ 0x9e, 0x42, 0xbc, 0x95, 0x6b, 0xc2, 0xca, 0x89, 0xb8, 0x69, 0xf9, 0xf5, ++ 0x32, 0xc6, 0x2d, 0x28, 0x39, 0x5d, 0xef, 0xb8, 0xa6, 0x74, 0xe1, 0x6a, ++ 0x44, 0xa7, 0x1f, 0x04, 0x34, 0x39, 0xd7, 0x75, 0x31, 0xfb, 0xbf, 0xb0, ++ 0x9d, 0x29, 0x77, 0xe9, 0x1c, 0xa9, 0xe7, 0x5b, 0xd6, 0x9a, 0x88, 0x87, ++ 0xfe, 0xe0, 0xec, 0xe7, 0x83, 0xfe, 0x72, 0x5c, 0xc9, 0x48, 0xec, 0x91, ++ 0x1e, 0xc2, 0x10, 0xf3, 0xb3, 0x30, 0x73, 0x4f, 0x99, 0xb7, 0x8d, 0xf9, ++ 0xa9, 0x07, 0xfb, 0xe2, 0x61, 0x24, 0x52, 0x47, 0xad, 0x52, 0x3d, 0x38, ++ 0x1c, 0x72, 0x7b, 0xb0, 0x37, 0x3b, 0x82, 0xdc, 0x8e, 0x4f, 0x2c, 0xb7, ++ 0xde, 0x45, 0x1c, 0x19, 0x21, 0x47, 0xd1, 0x10, 0x8f, 0x37, 0x62, 0xfb, ++ 0xae, 0x30, 0x36, 0xa7, 0x5c, 0xd8, 0x36, 0x67, 0x11, 0xb6, 0xe7, 0x5a, ++ 0x60, 0x1e, 0xd2, 0xb0, 0x8d, 0xe4, 0x65, 0xb8, 0x7f, 0x84, 0xfe, 0xab, ++ 0x37, 0x95, 0x2a, 0x23, 0x38, 0x99, 0xe1, 0xd8, 0xa9, 0xf7, 0xa8, 0xef, ++ 0x11, 0x6c, 0x4a, 0xeb, 0x6a, 0x9f, 0xbd, 0xbf, 0x11, 0x74, 0x67, 0x6e, ++ 0xd7, 0x2b, 0x6a, 0xc3, 0xd6, 0xd4, 0x86, 0x76, 0xa7, 0x5f, 0x44, 0x8c, ++ 0x67, 0x4e, 0xd9, 0x43, 0x1d, 0x1d, 0xce, 0x16, 0x7a, 0x47, 0x82, 0xe7, ++ 0x0e, 0x36, 0x6f, 0xca, 0x36, 0xa2, 0x67, 0xd7, 0x22, 0x5e, 0x1f, 0x46, ++ 0x77, 0x4a, 0xfa, 0xf1, 0x41, 0xce, 0x67, 0xe1, 0x03, 0x23, 0xe0, 0x9f, ++ 0x26, 0x39, 0xb8, 0xd1, 0x89, 0xd5, 0xba, 0x8d, 0x35, 0x4d, 0xba, 0x12, ++ 0x68, 0x32, 0xe1, 0xc6, 0x05, 0xc3, 0x0d, 0xd3, 0xe7, 0xc6, 0x8b, 0x46, ++ 0x25, 0xb9, 0xa6, 0x1b, 0xf5, 0x91, 0x52, 0xda, 0x4b, 0xc0, 0x8e, 0x86, ++ 0x1f, 0xa5, 0x15, 0x3c, 0x48, 0x5c, 0x3f, 0x16, 0xa9, 0x6f, 0x9f, 0x2f, ++ 0xcc, 0x6d, 0xbf, 0x82, 0xcb, 0xfa, 0x97, 0x96, 0x39, 0x4e, 0xb1, 0xcf, ++ 0x8c, 0x39, 0xba, 0xf9, 0xc2, 0x6a, 0xb7, 0x73, 0xa0, 0xaf, 0xac, 0xc2, ++ 0x7d, 0xd7, 0xb8, 0xbe, 0x47, 0x79, 0xdf, 0xb4, 0xd9, 0xf5, 0x9d, 0x72, ++ 0x9f, 0x9f, 0x31, 0x45, 0xee, 0x93, 0xde, 0xd3, 0x8d, 0xfb, 0x1a, 0xb1, ++ 0x69, 0x57, 0xb3, 0xbd, 0xde, 0x2d, 0x29, 0xcc, 0xf2, 0x30, 0xc7, 0x75, ++ 0x47, 0xea, 0xd5, 0x8b, 0x40, 0xd7, 0x88, 0x31, 0x86, 0xb1, 0x3a, 0x14, ++ 0x5e, 0x01, 0x91, 0x93, 0xf8, 0xe4, 0x7b, 0xc4, 0x82, 0x7e, 0xcc, 0x18, ++ 0x90, 0x78, 0x18, 0x6a, 0xeb, 0x43, 0x06, 0x4f, 0x65, 0x33, 0x78, 0x5a, ++ 0xf8, 0xa2, 0x7d, 0x86, 0x30, 0x8b, 0x1f, 0xc5, 0xdf, 0x43, 0xc2, 0xce, ++ 0x11, 0x0e, 0x63, 0x79, 0x3c, 0x33, 0x1e, 0x65, 0x72, 0xef, 0x7c, 0x8e, ++ 0x2f, 0x32, 0x0d, 0xb4, 0x9a, 0xf8, 0x86, 0xe3, 0xcf, 0xc7, 0x86, 0x3e, ++ 0xcb, 0x7a, 0x89, 0xf1, 0xf3, 0x2d, 0xf2, 0x83, 0xcb, 0xb4, 0xa3, 0x96, ++ 0x46, 0x19, 0x7f, 0x48, 0xd1, 0xed, 0x38, 0xda, 0x46, 0x1d, 0x8f, 0x87, ++ 0x9f, 0x72, 0xae, 0x1c, 0xd0, 0x95, 0x69, 0x09, 0xd1, 0xb9, 0x07, 0xae, ++ 0x01, 0x0d, 0x8f, 0x26, 0xbc, 0x28, 0x39, 0xf0, 0xaa, 0x22, 0xb1, 0xb4, ++ 0x96, 0xbc, 0xca, 0xbf, 0x5f, 0x53, 0xee, 0xda, 0xe3, 0xc5, 0x83, 0x09, ++ 0xf2, 0xad, 0x44, 0x0b, 0x36, 0x3c, 0xaf, 0xf3, 0x9a, 0x80, 0x71, 0x5a, ++ 0x09, 0x84, 0x4f, 0x22, 0xa8, 0xf5, 0x91, 0x17, 0xf8, 0x89, 0xdb, 0x9e, ++ 0x03, 0x55, 0x28, 0x27, 0x67, 0x74, 0x1d, 0xa8, 0x41, 0xc5, 0x01, 0x3f, ++ 0x6a, 0x19, 0x5b, 0xfd, 0x03, 0x67, 0x90, 0xdb, 0x03, 0xb5, 0x3c, 0xfa, ++ 0x27, 0xab, 0x44, 0x97, 0x3c, 0x31, 0x8c, 0xaa, 0x81, 0x75, 0xc8, 0x26, ++ 0x1a, 0x50, 0x41, 0xae, 0x5a, 0xcf, 0xf9, 0x16, 0x24, 0x74, 0x8e, 0xe3, ++ 0xe4, 0x24, 0xf3, 0x19, 0x8b, 0x7b, 0x52, 0x81, 0x36, 0xe9, 0xb7, 0x5e, ++ 0x36, 0x5e, 0x47, 0xe9, 0x8e, 0x1b, 0x67, 0x2a, 0xf5, 0x88, 0x7d, 0x6e, ++ 0xb0, 0xf5, 0x49, 0x38, 0xe7, 0x2b, 0xef, 0xcb, 0xef, 0xa7, 0x41, 0xf6, ++ 0x53, 0xd4, 0x46, 0x3b, 0x98, 0x60, 0xd7, 0x71, 0xce, 0xd1, 0x6e, 0xe6, ++ 0x72, 0xad, 0x5f, 0x92, 0x07, 0x77, 0x72, 0x2f, 0x1f, 0xf6, 0xbf, 0xaa, ++ 0xd4, 0x72, 0x2f, 0xd7, 0xc8, 0xbb, 0x3e, 0xc9, 0x68, 0x4a, 0x90, 0x7b, ++ 0xf9, 0x31, 0x7f, 0xff, 0x11, 0xf7, 0xb2, 0xf1, 0xf9, 0x40, 0xeb, 0x71, ++ 0xe6, 0xab, 0x8b, 0x95, 0xa0, 0xba, 0x51, 0xa9, 0xc0, 0xb9, 0xfe, 0x2a, ++ 0x5c, 0x24, 0x0f, 0xf8, 0xb2, 0xbf, 0x06, 0x97, 0xfa, 0x7d, 0xf4, 0x11, ++ 0x9d, 0x63, 0x30, 0xe6, 0xe9, 0x7e, 0x5c, 0xcb, 0x3e, 0x8d, 0x31, 0x89, ++ 0xc9, 0xf8, 0x24, 0xbb, 0x1a, 0x55, 0x09, 0xe1, 0xb3, 0x1a, 0x3e, 0xe6, ++ 0xef, 0x1f, 0x65, 0x07, 0x51, 0xb6, 0x47, 0xb0, 0xcc, 0xb2, 0x16, 0x70, ++ 0x7f, 0x97, 0xb2, 0x1d, 0xa8, 0xd8, 0xb3, 0x16, 0x9e, 0x3d, 0x56, 0xd7, ++ 0x86, 0x08, 0x7e, 0xed, 0xe6, 0x5e, 0xba, 0x8d, 0xc0, 0xf0, 0x34, 0x77, ++ 0x03, 0xc7, 0x18, 0x52, 0xee, 0x1a, 0x58, 0x8b, 0xaa, 0x3d, 0x1a, 0xd6, ++ 0x50, 0x86, 0x83, 0xd0, 0xc3, 0x8b, 0x95, 0xb5, 0x28, 0x3e, 0xe0, 0xec, ++ 0x7f, 0xe5, 0x80, 0xe3, 0x17, 0x0b, 0x1a, 0x47, 0xf3, 0x72, 0xbf, 0xcd, ++ 0x21, 0x47, 0x98, 0x1b, 0xbf, 0x91, 0x11, 0xf9, 0x40, 0xf5, 0x44, 0x07, ++ 0x51, 0xb2, 0x87, 0x98, 0xd8, 0x6f, 0xd8, 0xdc, 0x45, 0x7c, 0xa2, 0x3f, ++ 0x7b, 0x3b, 0x9f, 0x32, 0xb0, 0x2d, 0x55, 0x4b, 0x7f, 0x9a, 0x8c, 0xfb, ++ 0xf7, 0x48, 0x8f, 0x7d, 0x78, 0xae, 0x97, 0x56, 0x74, 0x28, 0x7b, 0xab, ++ 0x3f, 0x35, 0xd1, 0x36, 0x05, 0x5b, 0x2d, 0x8c, 0x18, 0x0e, 0xde, 0x1c, ++ 0xb3, 0x7b, 0xf8, 0xe2, 0x93, 0xcb, 0xb0, 0x61, 0x17, 0xda, 0xf7, 0x35, ++ 0x8a, 0x4f, 0x16, 0xa1, 0x8f, 0xdc, 0xf5, 0x5c, 0x5c, 0x6a, 0x66, 0x7f, ++ 0x22, 0x26, 0x14, 0xa3, 0xb7, 0xdf, 0x8b, 0xd7, 0xfa, 0x35, 0xf8, 0x13, ++ 0x65, 0x18, 0xa2, 0x8c, 0x73, 0xe4, 0x5b, 0x1f, 0x33, 0x63, 0x1c, 0x64, ++ 0x1c, 0xfe, 0x28, 0xee, 0xc3, 0x40, 0x76, 0x32, 0xae, 0xc6, 0x75, 0x64, ++ 0xa9, 0x8f, 0xdf, 0x13, 0x5b, 0x5e, 0xca, 0x36, 0xe0, 0xc3, 0xb8, 0x60, ++ 0x4f, 0x03, 0x5e, 0xa4, 0xfc, 0x4a, 0x13, 0x7e, 0x8e, 0x2b, 0x38, 0xa4, ++ 0xa1, 0x28, 0xa1, 0x6b, 0x7d, 0x79, 0x5b, 0xf0, 0x0c, 0x2c, 0xa3, 0xdf, ++ 0xc8, 0xf9, 0x12, 0x89, 0x03, 0x1e, 0xa3, 0x8f, 0xf9, 0x63, 0x6f, 0x43, ++ 0xe1, 0xac, 0x64, 0xc0, 0x3f, 0x8c, 0xb1, 0xf4, 0x9d, 0x6f, 0x2c, 0x55, ++ 0x97, 0xfc, 0x20, 0x1d, 0xb9, 0x1c, 0xd7, 0x19, 0x23, 0xe5, 0xcc, 0xad, ++ 0xa9, 0x14, 0xcd, 0x29, 0x22, 0x37, 0xda, 0xc8, 0x7d, 0x87, 0xb9, 0x7e, ++ 0xa9, 0x29, 0x5a, 0xbc, 0xee, 0x2a, 0x66, 0xec, 0x8f, 0x4e, 0x70, 0x78, ++ 0x17, 0xfd, 0xf7, 0x3a, 0x07, 0x2d, 0x60, 0xbc, 0xe4, 0x1e, 0xbb, 0x23, ++ 0xaf, 0xc7, 0x7f, 0x3c, 0x81, 0x37, 0xa8, 0xc7, 0xc9, 0xbf, 0xb6, 0xa4, ++ 0xce, 0x72, 0xee, 0x42, 0xfd, 0x58, 0xe6, 0x9e, 0xcc, 0xb9, 0x2d, 0xbc, ++ 0x4b, 0x0c, 0xb9, 0x94, 0x16, 0x8e, 0x26, 0xdc, 0xac, 0x8b, 0xb1, 0xa7, ++ 0x12, 0x17, 0xa9, 0x9b, 0x4d, 0xcc, 0x2d, 0x82, 0xc9, 0x61, 0x72, 0xeb, ++ 0x3b, 0xc9, 0x0f, 0xab, 0x38, 0xcc, 0xe3, 0x9c, 0x6f, 0x19, 0xb6, 0xd1, ++ 0x17, 0x4b, 0xf5, 0x69, 0xb8, 0x9f, 0x9c, 0x5a, 0x6a, 0xa0, 0x58, 0x2a, ++ 0x71, 0x03, 0x98, 0x9e, 0x54, 0x51, 0x11, 0xd5, 0xdb, 0xde, 0xc2, 0x5c, ++ 0xb4, 0x8f, 0xf3, 0x4a, 0x7f, 0x77, 0xf5, 0x3b, 0x98, 0x87, 0xcc, 0x23, ++ 0x12, 0x5b, 0x5d, 0xd2, 0xa7, 0x36, 0xcf, 0x60, 0x2a, 0x50, 0xc3, 0x3d, ++ 0x44, 0x65, 0x3d, 0x3e, 0xca, 0x5e, 0xc5, 0x79, 0xca, 0xf5, 0x62, 0x3c, ++ 0x78, 0xed, 0x5e, 0x72, 0xb4, 0x8b, 0x6e, 0x72, 0xcc, 0xb1, 0x72, 0x7d, ++ 0x03, 0x74, 0x8e, 0xf7, 0x59, 0x3c, 0x82, 0x1d, 0xaa, 0x7c, 0xae, 0xb1, ++ 0x6b, 0x08, 0xdd, 0x7d, 0xb2, 0x06, 0xcb, 0xaa, 0x21, 0x1e, 0x2e, 0xb5, ++ 0xe7, 0x97, 0xb9, 0xb9, 0x8f, 0x9b, 0xf2, 0xa0, 0x00, 0xb3, 0x42, 0x47, ++ 0xee, 0xff, 0xb3, 0x6e, 0x04, 0x87, 0xd3, 0x94, 0xff, 0x9c, 0xe7, 0x29, ++ 0x87, 0x11, 0xf4, 0x67, 0xe4, 0x6c, 0x80, 0xf4, 0x5c, 0x0d, 0x6c, 0x67, ++ 0x4c, 0x4f, 0xf0, 0xfa, 0x6c, 0xa2, 0x1c, 0xe6, 0x38, 0x67, 0xce, 0x3b, ++ 0x93, 0x57, 0xad, 0xe1, 0x25, 0x76, 0xce, 0xc5, 0xcf, 0xaf, 0xf0, 0x9e, ++ 0x09, 0x72, 0xdc, 0x15, 0xab, 0x12, 0x97, 0xac, 0xe1, 0xd6, 0xd1, 0xdf, ++ 0x57, 0xe7, 0xcf, 0xab, 0x8d, 0xe3, 0xbb, 0x23, 0x97, 0x6e, 0xca, 0x65, ++ 0x8c, 0xfe, 0x9e, 0xf5, 0x90, 0xbd, 0xae, 0xfd, 0x13, 0xa4, 0x5e, 0x32, ++ 0x3d, 0x79, 0x66, 0x82, 0xf4, 0x4b, 0x5c, 0xcc, 0x4d, 0xbc, 0x51, 0xbd, ++ 0xe9, 0x14, 0x7e, 0x6b, 0x9d, 0xbd, 0x69, 0x9c, 0xb1, 0xfc, 0x4d, 0x62, ++ 0xcf, 0xd9, 0x7c, 0xfd, 0xc2, 0x9f, 0xcf, 0x3d, 0x46, 0x70, 0x3c, 0x2d, ++ 0xd8, 0xaf, 0x61, 0xb9, 0xd4, 0x59, 0xd4, 0x40, 0x8f, 0x89, 0x61, 0xbc, ++ 0x19, 0x7f, 0x9f, 0xb2, 0x57, 0xb0, 0x26, 0x34, 0x8c, 0x5f, 0x67, 0x47, ++ 0xc7, 0xa6, 0x18, 0xb9, 0xb2, 0xf4, 0x79, 0x04, 0x3f, 0x47, 0xb0, 0x25, ++ 0x7d, 0x94, 0x38, 0xf6, 0x09, 0xf9, 0x51, 0x17, 0xf9, 0xea, 0x08, 0x36, ++ 0x64, 0x5a, 0xf0, 0xc2, 0xf3, 0x8b, 0x88, 0x2b, 0x82, 0x8d, 0xc1, 0x53, ++ 0xe7, 0xdc, 0x2d, 0xd8, 0x77, 0x28, 0x8b, 0xcc, 0x01, 0x89, 0x87, 0x12, ++ 0x73, 0x25, 0x16, 0x86, 0x11, 0x4f, 0x9d, 0x84, 0xc9, 0xf7, 0x6d, 0xa9, ++ 0xb5, 0x88, 0x1d, 0x78, 0x8f, 0x39, 0xc5, 0x08, 0xe6, 0xef, 0xd0, 0xdb, ++ 0x0e, 0x62, 0x04, 0x0b, 0xf7, 0xeb, 0x48, 0xa7, 0x16, 0x71, 0xfc, 0x16, ++ 0x6c, 0x7e, 0x3e, 0x60, 0xd7, 0x4e, 0x86, 0x69, 0xb0, 0x9b, 0x72, 0xcd, ++ 0x30, 0xfb, 0xe4, 0x3c, 0x86, 0x17, 0x0d, 0x49, 0x4d, 0xf9, 0x68, 0xb7, ++ 0x07, 0xf5, 0x49, 0xa9, 0xb9, 0x07, 0xcc, 0x85, 0x4a, 0x50, 0x2b, 0x76, ++ 0x59, 0xd6, 0x66, 0xc6, 0x86, 0x53, 0x86, 0x82, 0xd2, 0xb9, 0x0a, 0x22, ++ 0x8c, 0x55, 0xda, 0x78, 0xc6, 0x90, 0xbe, 0x46, 0x6c, 0xde, 0xc5, 0xfd, ++ 0x5e, 0xd7, 0x9b, 0xe8, 0xab, 0x95, 0xe3, 0x89, 0xee, 0x16, 0x61, 0x73, ++ 0x2e, 0xd8, 0x71, 0x0a, 0x7e, 0x3b, 0x0f, 0xd9, 0xbc, 0xeb, 0x7a, 0x8e, ++ 0x5b, 0xf1, 0x49, 0x63, 0x20, 0x3c, 0x46, 0x91, 0x6b, 0x37, 0x12, 0xb3, ++ 0x46, 0x5f, 0x6f, 0x2a, 0xe9, 0x39, 0x72, 0x76, 0x50, 0xfc, 0xa2, 0xdb, ++ 0xf6, 0x17, 0x91, 0xc5, 0xe6, 0x74, 0x8c, 0x36, 0xfd, 0x4b, 0x2b, 0xd3, ++ 0xba, 0x8c, 0xeb, 0x6c, 0x92, 0x1e, 0x94, 0x8d, 0x09, 0x6f, 0xdb, 0xb5, ++ 0x3a, 0xc1, 0x84, 0xee, 0x76, 0xe9, 0x0b, 0x95, 0x10, 0x97, 0x4a, 0x07, ++ 0xbd, 0xf0, 0x1e, 0x2c, 0x47, 0x49, 0xaf, 0xf0, 0x31, 0xc9, 0xa7, 0x55, ++ 0xb8, 0x07, 0x2b, 0xe8, 0x03, 0xd4, 0xe1, 0x20, 0x7d, 0x2c, 0xee, 0xc7, ++ 0xd4, 0x41, 0x3f, 0x5e, 0x23, 0x06, 0xd4, 0x0e, 0xea, 0x18, 0x22, 0x06, ++ 0xf8, 0x07, 0xc3, 0xc8, 0xc5, 0x1b, 0x30, 0x66, 0x70, 0x48, 0x79, 0x27, ++ 0xfb, 0x35, 0x75, 0x2a, 0xf3, 0x88, 0x0c, 0x0b, 0x3a, 0x15, 0x7d, 0x2e, ++ 0x22, 0xd6, 0x89, 0x6e, 0x1b, 0xb0, 0x75, 0x57, 0x16, 0xf7, 0xec, 0xb1, ++ 0xf0, 0x1b, 0x43, 0xce, 0xb7, 0x4b, 0x7e, 0x69, 0x21, 0xcb, 0xb8, 0x76, ++ 0x9f, 0x11, 0x68, 0x93, 0xb3, 0x0b, 0xed, 0x3e, 0x0b, 0xc5, 0x91, 0x80, ++ 0x41, 0x74, 0x6f, 0x2b, 0x55, 0x24, 0x46, 0xd5, 0x6b, 0xab, 0x31, 0x29, ++ 0x7f, 0x76, 0xed, 0x5e, 0xac, 0x56, 0xa5, 0x86, 0xd7, 0x82, 0x6d, 0xd5, ++ 0xa6, 0xf7, 0x72, 0xa3, 0x9c, 0xb5, 0xf9, 0x3f, 0xe3, 0xed, 0x3a, 0xa7, ++ 0x6b, 0x0a, 0xf7, 0xdd, 0xc6, 0x3d, 0xcb, 0xbe, 0x3b, 0x90, 0xd8, 0xad, ++ 0x20, 0x1b, 0xea, 0x40, 0xbc, 0xbf, 0x43, 0xf8, 0x13, 0xf1, 0xa0, 0x87, ++ 0x78, 0x60, 0x75, 0x3d, 0x19, 0x79, 0x08, 0x97, 0xec, 0x88, 0x2f, 0xf7, ++ 0x04, 0xc2, 0x9a, 0x6b, 0xb4, 0x0e, 0xae, 0x4c, 0x90, 0x9c, 0x5d, 0xfc, ++ 0xa6, 0x79, 0x87, 0xf0, 0xeb, 0x50, 0xcf, 0x66, 0xea, 0x7e, 0xc9, 0x7e, ++ 0x89, 0x2f, 0x96, 0xd5, 0x43, 0x5e, 0x8a, 0x6a, 0xd9, 0x43, 0x18, 0xc9, ++ 0x94, 0xf5, 0x49, 0xad, 0x1e, 0xbc, 0xb6, 0x9d, 0x71, 0xfc, 0xcc, 0x9e, ++ 0xfa, 0xd5, 0xab, 0x85, 0xb3, 0xcc, 0xd6, 0x3b, 0x6b, 0xdd, 0x59, 0x9c, ++ 0x3e, 0x30, 0x03, 0x99, 0x25, 0xdc, 0x0f, 0xf5, 0x54, 0x94, 0xfc, 0xca, ++ 0x92, 0x73, 0x18, 0x6e, 0x72, 0xf5, 0xc3, 0xc4, 0x3d, 0xd7, 0x60, 0x08, ++ 0x1b, 0xaa, 0x61, 0x5e, 0x6e, 0x94, 0xf9, 0xaf, 0xaf, 0x9f, 0xfb, 0x6d, ++ 0xc1, 0xf6, 0xe7, 0x85, 0x57, 0x08, 0xff, 0x0a, 0x9a, 0xbf, 0xc7, 0x22, ++ 0xa4, 0x73, 0xce, 0x5c, 0xf1, 0xd4, 0xad, 0x76, 0x22, 0x3a, 0x3f, 0x89, ++ 0xad, 0xe4, 0x6f, 0x5e, 0x8e, 0xcf, 0x98, 0xc2, 0xf1, 0xf4, 0x70, 0xa9, ++ 0xcc, 0x37, 0xf8, 0x4b, 0x6b, 0xdb, 0x38, 0x91, 0x8d, 0x8c, 0x9f, 0x1d, ++ 0x2f, 0x78, 0xb1, 0x32, 0xf2, 0x5d, 0x7b, 0x7d, 0xc1, 0x8f, 0xb2, 0x40, ++ 0x8b, 0x23, 0x0f, 0xb9, 0x36, 0xfb, 0x2d, 0xeb, 0xa1, 0x73, 0x96, 0xc9, ++ 0x9a, 0x3a, 0xb0, 0x95, 0xe9, 0x22, 0x73, 0xab, 0xd8, 0x0c, 0xa5, 0x03, ++ 0x3d, 0x94, 0xef, 0xa6, 0x74, 0x07, 0xf6, 0xd1, 0x5f, 0x7b, 0x8d, 0x63, ++ 0xb5, 0x2e, 0xd4, 0x5d, 0x73, 0x63, 0xf8, 0x57, 0x53, 0x89, 0xa5, 0x77, ++ 0xcd, 0x0e, 0xd1, 0xb7, 0x3a, 0x90, 0xcc, 0x6c, 0xf1, 0xdb, 0x7d, 0x42, ++ 0x97, 0xc4, 0x3c, 0x91, 0x45, 0x27, 0xca, 0x76, 0x9c, 0x44, 0xd1, 0x8e, ++ 0x4e, 0x94, 0x86, 0xe6, 0xe1, 0xbe, 0xc8, 0x59, 0xeb, 0x92, 0xee, 0xf1, ++ 0x1f, 0xa7, 0x7c, 0x8e, 0x35, 0xd4, 0xe2, 0x49, 0xa3, 0x01, 0x9b, 0xfa, ++ 0x26, 0xd2, 0xef, 0x9b, 0xb0, 0x35, 0xc7, 0xb9, 0xa2, 0x2e, 0x2c, 0x9c, ++ 0x23, 0x75, 0x01, 0x85, 0x76, 0x3d, 0x1e, 0x67, 0x7d, 0xba, 0xfa, 0x94, ++ 0x7d, 0x66, 0x80, 0x9c, 0xcb, 0xa7, 0xe1, 0x09, 0xfa, 0x57, 0xbb, 0x2a, ++ 0xbf, 0xaf, 0x63, 0x1e, 0xb0, 0x0e, 0xb5, 0x09, 0xd3, 0x12, 0x79, 0x1f, ++ 0x47, 0xec, 0xa7, 0x2e, 0xae, 0xa3, 0x69, 0x76, 0x68, 0xf5, 0x35, 0x45, ++ 0xec, 0x39, 0xc4, 0x5c, 0xd7, 0xf0, 0x2e, 0x1a, 0x50, 0x10, 0xde, 0xc1, ++ 0xb1, 0x22, 0xff, 0xc9, 0xef, 0xd4, 0x75, 0x0b, 0xfc, 0x6e, 0x1d, 0x79, ++ 0xc1, 0x3a, 0x54, 0x26, 0x84, 0x93, 0x0b, 0x2e, 0xc4, 0x7e, 0x50, 0xc5, ++ 0xfb, 0xb3, 0x91, 0x50, 0x6b, 0x85, 0x22, 0xdc, 0x27, 0xd4, 0xb4, 0x50, ++ 0x11, 0xae, 0x22, 0xf7, 0x19, 0xde, 0xba, 0x81, 0x33, 0xf9, 0x7e, 0x65, ++ 0x13, 0xb1, 0x41, 0xb3, 0xcf, 0xdf, 0xbe, 0x6c, 0x9f, 0x35, 0xbb, 0x51, ++ 0x7f, 0x2d, 0x4a, 0x4a, 0xee, 0x70, 0x24, 0x72, 0x4f, 0x3c, 0x2a, 0x67, ++ 0x03, 0xe6, 0x1d, 0xa2, 0xdd, 0x9f, 0x83, 0x0f, 0xff, 0x10, 0x17, 0x4c, ++ 0xd3, 0xf0, 0x8f, 0xf1, 0x92, 0xfc, 0xb9, 0x9d, 0x4a, 0xbc, 0x99, 0x36, ++ 0x2d, 0xca, 0xb5, 0x65, 0x21, 0x6d, 0x29, 0x1c, 0xa9, 0x00, 0xc6, 0x75, ++ 0x3f, 0x51, 0x64, 0xd7, 0x0b, 0x2a, 0x51, 0x4d, 0xfc, 0xdf, 0xd1, 0xf7, ++ 0x6d, 0x67, 0xb8, 0x88, 0xc1, 0x65, 0x52, 0xf7, 0x72, 0x63, 0x53, 0xe4, ++ 0x0f, 0x56, 0x66, 0x99, 0xdc, 0x33, 0x19, 0xa7, 0x77, 0x8b, 0x9d, 0x86, ++ 0x51, 0x92, 0x3c, 0x43, 0x9b, 0x54, 0xf1, 0x76, 0x3c, 0x68, 0x2c, 0x76, ++ 0xfd, 0x15, 0xed, 0x7f, 0xea, 0x4d, 0xb8, 0x3d, 0x55, 0x7f, 0x10, 0x8f, ++ 0xd9, 0xb8, 0x1d, 0xc3, 0x06, 0xc6, 0x05, 0xf2, 0xb6, 0xbd, 0x4f, 0xb8, ++ 0x54, 0xc6, 0xf3, 0xa0, 0x1a, 0xa4, 0x4d, 0x6d, 0xe0, 0x1c, 0xc2, 0x27, ++ 0xc7, 0x92, 0xef, 0x3d, 0x19, 0xaf, 0xd7, 0xbe, 0xc0, 0x72, 0xfb, 0x2c, ++ 0xb0, 0xe6, 0x92, 0x3d, 0xe9, 0xa8, 0x48, 0xea, 0x38, 0xc1, 0x7d, 0x6c, ++ 0xaa, 0x76, 0xe6, 0xad, 0xca, 0x8f, 0x9d, 0xec, 0x13, 0xbe, 0x75, 0x37, ++ 0x16, 0xdb, 0x63, 0x1b, 0xf4, 0x4b, 0x1d, 0x7b, 0xe3, 0x0a, 0xc6, 0xd4, ++ 0xe9, 0x48, 0x65, 0x9b, 0xb1, 0xb6, 0x46, 0xc3, 0xbe, 0xd4, 0x3a, 0xcc, ++ 0x4a, 0xfd, 0x00, 0x0f, 0xd7, 0x98, 0x8c, 0x8b, 0xc4, 0xa0, 0xa4, 0xae, ++ 0xce, 0x50, 0xbe, 0x9f, 0xaf, 0xbb, 0xfa, 0xe0, 0x49, 0x4a, 0xbc, 0x2b, ++ 0xc6, 0x4e, 0x75, 0x12, 0xca, 0x75, 0x19, 0xdf, 0x19, 0x7b, 0x7b, 0x5f, ++ 0x20, 0x1f, 0x03, 0x89, 0x1a, 0x49, 0x45, 0x62, 0x6f, 0xf8, 0x69, 0xf2, ++ 0x88, 0x0c, 0xa3, 0x5f, 0x71, 0x54, 0xcf, 0xac, 0x42, 0x29, 0xcc, 0xf1, ++ 0x82, 0x87, 0x72, 0xcf, 0xc4, 0x5b, 0xd6, 0x54, 0x93, 0x5f, 0x53, 0xe1, ++ 0xf7, 0xbf, 0xe1, 0x6f, 0x62, 0x5b, 0xc2, 0x2d, 0xe4, 0xfb, 0x32, 0xb4, ++ 0xaa, 0x72, 0x8e, 0xd6, 0x40, 0x2a, 0x25, 0xbf, 0x07, 0x0c, 0xd3, 0xd5, ++ 0x88, 0xcf, 0xf7, 0x38, 0x36, 0xd8, 0x36, 0x9d, 0xfa, 0xaf, 0x6a, 0xc4, ++ 0xb5, 0x03, 0x12, 0xcb, 0xbe, 0x4d, 0x27, 0x85, 0x38, 0x2c, 0x7a, 0x11, ++ 0xb9, 0x06, 0x4e, 0x9d, 0x47, 0xfd, 0xf0, 0xa3, 0xae, 0xc3, 0x16, 0xc6, ++ 0x8a, 0x8c, 0x17, 0xd4, 0x4a, 0xae, 0xe9, 0x22, 0x87, 0x30, 0xb3, 0x1d, ++ 0xb5, 0x12, 0x27, 0x3d, 0x49, 0x60, 0x6a, 0xd2, 0x44, 0x49, 0x54, 0xdf, ++ 0x7b, 0xd9, 0xfd, 0xa5, 0xd5, 0x3e, 0x7e, 0xa2, 0xd4, 0x79, 0xae, 0xef, ++ 0xb9, 0x87, 0x6b, 0x77, 0xeb, 0xbf, 0xb4, 0xee, 0xf5, 0xc9, 0x1a, 0xf7, ++ 0xf1, 0x1e, 0x99, 0xfb, 0x0e, 0xca, 0xa5, 0x20, 0x13, 0x8b, 0xf6, 0xf3, ++ 0xdf, 0xac, 0x07, 0x6e, 0xfa, 0x5d, 0xb8, 0x8c, 0xd8, 0xe9, 0xe8, 0xfe, ++ 0xb9, 0xd8, 0xac, 0xf4, 0x09, 0x46, 0x70, 0x28, 0x2d, 0xb6, 0x2b, 0x32, ++ 0x8e, 0xe1, 0x1c, 0x79, 0x61, 0xf1, 0xce, 0x11, 0xf4, 0x92, 0x17, 0xba, ++ 0x93, 0x81, 0xbd, 0x94, 0x24, 0xd6, 0xaa, 0xf3, 0x88, 0xd5, 0x95, 0x5c, ++ 0x47, 0x61, 0x0d, 0xd3, 0x6d, 0xb9, 0x4b, 0x7c, 0xd9, 0xc6, 0xfd, 0x96, ++ 0x92, 0x23, 0x35, 0x27, 0x4a, 0xa0, 0x57, 0x57, 0xa1, 0x82, 0x6b, 0x6d, ++ 0xcf, 0xaf, 0x35, 0xce, 0xb5, 0x94, 0xeb, 0x93, 0xb0, 0xd0, 0xbe, 0x56, ++ 0xb3, 0xcf, 0x2f, 0xe8, 0x35, 0x12, 0x7f, 0x25, 0xe6, 0x92, 0x6f, 0xcf, ++ 0x91, 0x98, 0x1b, 0xe3, 0xda, 0x26, 0xe6, 0x7b, 0x26, 0x0b, 0xed, 0xdf, ++ 0xf7, 0xa6, 0xae, 0x7e, 0xb3, 0x33, 0xf5, 0x67, 0xde, 0xd3, 0x01, 0xf5, ++ 0xf9, 0x32, 0x2c, 0x79, 0xae, 0x1c, 0x46, 0x8d, 0x53, 0xf7, 0x9d, 0x1a, ++ 0x8d, 0x47, 0xac, 0x94, 0xf0, 0xa4, 0x29, 0xd0, 0x26, 0xc8, 0x5c, 0x82, ++ 0x01, 0xa2, 0x0b, 0xd1, 0x5d, 0xc0, 0xb8, 0x7d, 0x5f, 0x22, 0xa0, 0x0e, ++ 0x5f, 0xd7, 0xc3, 0x0c, 0xe8, 0x4b, 0x7d, 0xdc, 0x9b, 0x13, 0x23, 0xb6, ++ 0x32, 0x46, 0x84, 0x43, 0x0e, 0x86, 0x6d, 0xd9, 0x2d, 0x39, 0x7f, 0x8f, ++ 0xf4, 0x5e, 0xbb, 0xce, 0x19, 0x55, 0x98, 0x9f, 0x8f, 0x11, 0xed, 0xae, ++ 0x2b, 0xb6, 0x6d, 0x14, 0xe9, 0x5f, 0x51, 0x9e, 0x32, 0xc7, 0xcc, 0x9b, ++ 0xb8, 0xd8, 0x58, 0xfd, 0xff, 0x5a, 0x0f, 0xfb, 0x64, 0x8f, 0x5f, 0xd7, ++ 0x3a, 0xf5, 0xde, 0x0e, 0xec, 0x25, 0x3e, 0xd6, 0xea, 0x72, 0x8f, 0x9e, ++ 0xae, 0x75, 0x77, 0x60, 0x27, 0xc7, 0xdf, 0x41, 0x8c, 0x4c, 0x10, 0x23, ++ 0x8d, 0x59, 0xc7, 0x7e, 0xaa, 0xa2, 0xae, 0x83, 0xec, 0xe1, 0x71, 0xc1, ++ 0x96, 0x97, 0x88, 0x2d, 0x4f, 0x13, 0x23, 0xb7, 0x65, 0x64, 0x1e, 0x99, ++ 0xaf, 0x30, 0x8f, 0x8c, 0xf9, 0x3b, 0x6b, 0x95, 0x4f, 0xd6, 0x7a, 0xbb, ++ 0x75, 0xc8, 0x77, 0xe3, 0x26, 0xa2, 0xac, 0xcc, 0xe6, 0x50, 0x3d, 0xa9, ++ 0xd1, 0xcf, 0x1f, 0x8d, 0x10, 0x5f, 0xed, 0x3c, 0x80, 0xf1, 0x35, 0x86, ++ 0xfb, 0xe7, 0xa8, 0xb8, 0x14, 0x1f, 0x41, 0xe9, 0xfe, 0x02, 0x16, 0x59, ++ 0xf3, 0x4e, 0x10, 0x87, 0x7a, 0x21, 0xd8, 0x13, 0xa5, 0x0e, 0x4c, 0xfa, ++ 0x44, 0x25, 0x06, 0xd3, 0x3a, 0xf1, 0x51, 0x6a, 0x4c, 0x5e, 0x72, 0xd8, ++ 0xee, 0xe3, 0xc5, 0x76, 0x4c, 0xa8, 0x24, 0x5e, 0x17, 0xf8, 0xb5, 0x70, ++ 0xeb, 0xc7, 0xed, 0x18, 0xbf, 0xa1, 0xcf, 0x8d, 0xe2, 0xd9, 0x4e, 0xee, ++ 0x70, 0x7a, 0x99, 0x5c, 0x37, 0x19, 0xbd, 0xbb, 0xc5, 0xd6, 0x82, 0xa8, ++ 0xd5, 0xcf, 0x30, 0x97, 0x00, 0xae, 0xc4, 0x5d, 0x53, 0xbc, 0xe4, 0xc0, ++ 0x5d, 0xc6, 0x1c, 0x7c, 0x39, 0x76, 0x03, 0xfd, 0xdb, 0xcf, 0xef, 0x86, ++ 0x71, 0x30, 0xee, 0x45, 0xb1, 0x5d, 0x6f, 0xac, 0xe2, 0x7e, 0x1c, 0x7b, ++ 0xd9, 0x44, 0x7b, 0x29, 0x61, 0x6e, 0x76, 0x9f, 0xed, 0x97, 0x32, 0xce, ++ 0x88, 0xfd, 0x0c, 0x92, 0x3e, 0x47, 0x78, 0xab, 0xc1, 0x18, 0x58, 0x89, ++ 0xe4, 0x8e, 0x2e, 0xbc, 0x1d, 0xa9, 0x44, 0x62, 0xbf, 0xf8, 0xd3, 0x64, ++ 0xc1, 0x4d, 0xce, 0x1b, 0xa5, 0x7c, 0x54, 0xe2, 0x4a, 0x7d, 0xa7, 0xdb, ++ 0x5d, 0x89, 0xb3, 0xd5, 0xcc, 0x57, 0xed, 0xe7, 0xb4, 0x96, 0x61, 0x5f, ++ 0x5e, 0x47, 0x2a, 0xf9, 0x4d, 0xeb, 0x75, 0xbe, 0x5c, 0xd8, 0x4b, 0xc1, ++ 0x3f, 0x65, 0x4f, 0x2a, 0x36, 0xc7, 0x0d, 0xbc, 0x20, 0xf5, 0x20, 0x57, ++ 0x90, 0x71, 0x83, 0x79, 0x51, 0x4e, 0x64, 0x5d, 0xb0, 0xad, 0x8d, 0x13, ++ 0x9d, 0x73, 0x2e, 0x05, 0x1d, 0x14, 0x3e, 0xeb, 0x6d, 0x65, 0xca, 0x3f, ++ 0x5b, 0x6b, 0xc6, 0xc9, 0xfa, 0xae, 0x32, 0x0f, 0x7b, 0x96, 0xdf, 0x2f, ++ 0xc0, 0xe6, 0xbe, 0xd1, 0x71, 0x41, 0x7c, 0xae, 0xd0, 0x93, 0x73, 0x7c, ++ 0xaf, 0x3a, 0x29, 0x7d, 0xf8, 0x23, 0x91, 0x27, 0xa8, 0x87, 0xd0, 0xac, ++ 0x7a, 0xbb, 0x96, 0x42, 0x8e, 0xcb, 0xfc, 0x43, 0xf0, 0xd4, 0x64, 0x3c, ++ 0xaf, 0xc4, 0xaf, 0xd3, 0x12, 0x5f, 0x2d, 0x94, 0x44, 0xca, 0x19, 0xef, ++ 0xba, 0x9f, 0xaa, 0xb6, 0x39, 0x73, 0x25, 0x6a, 0x68, 0x7b, 0x3b, 0xfb, ++ 0x6e, 0x67, 0xe7, 0x37, 0x62, 0x40, 0x36, 0x22, 0x67, 0xd9, 0xff, 0x60, ++ 0x6d, 0x7f, 0xc4, 0xb9, 0xe7, 0x74, 0x5a, 0xea, 0xc6, 0xed, 0x18, 0xae, ++ 0x8e, 0x61, 0x57, 0xaa, 0x14, 0xed, 0xe3, 0xeb, 0xec, 0xe7, 0x59, 0xe4, ++ 0x59, 0xab, 0x33, 0xf1, 0x22, 0x34, 0x4d, 0xd0, 0xec, 0x7a, 0x92, 0x8b, ++ 0x38, 0xfe, 0x7e, 0x3c, 0xc6, 0x58, 0xa0, 0xdd, 0x14, 0x1f, 0x3c, 0xfa, ++ 0x6c, 0x34, 0x53, 0x7e, 0x45, 0x36, 0x86, 0x57, 0xa2, 0x27, 0xfd, 0x27, ++ 0xfa, 0x76, 0x95, 0x39, 0x95, 0x9c, 0xbe, 0x5c, 0xa9, 0xc4, 0x96, 0x8c, ++ 0x26, 0xf5, 0x10, 0x6f, 0x59, 0x34, 0x1b, 0x79, 0x20, 0xd1, 0x46, 0xdd, ++ 0x74, 0xe2, 0x83, 0xdd, 0x76, 0x1c, 0x51, 0xef, 0x55, 0xac, 0xae, 0x50, ++ 0x24, 0xa6, 0x31, 0x8e, 0x0d, 0x37, 0xd3, 0xde, 0x6b, 0x67, 0x9b, 0xf4, ++ 0x99, 0x40, 0xc7, 0x3c, 0xb7, 0x7d, 0x76, 0xa7, 0x73, 0x2c, 0x73, 0xe9, ++ 0xd3, 0x59, 0xe0, 0x37, 0x07, 0xc2, 0x8c, 0xbb, 0xc2, 0xd9, 0xc2, 0xa8, ++ 0x18, 0x68, 0x40, 0x59, 0xa2, 0x01, 0xe5, 0xc9, 0x00, 0x63, 0x61, 0x03, ++ 0x4a, 0xf9, 0xd9, 0x9d, 0x34, 0xe0, 0x1e, 0xf0, 0x31, 0x9e, 0x36, 0xa2, ++ 0x68, 0xe0, 0xfb, 0xcc, 0xc9, 0x15, 0x74, 0xeb, 0xdf, 0x87, 0xeb, 0x40, ++ 0x27, 0xac, 0xdd, 0x72, 0xd6, 0xec, 0x48, 0x44, 0x65, 0x1c, 0x38, 0x5f, ++ 0x67, 0x75, 0x3d, 0x6b, 0xd4, 0x11, 0x33, 0x02, 0x46, 0x3b, 0xf1, 0x20, ++ 0x65, 0xf7, 0x13, 0x44, 0x0e, 0xa2, 0xbb, 0x4e, 0x5c, 0x3a, 0x20, 0x98, ++ 0x71, 0x7b, 0x9c, 0xc8, 0x5c, 0xc7, 0x09, 0x99, 0x47, 0x7c, 0xfb, 0x0e, ++ 0xfc, 0x42, 0x0d, 0x73, 0x3f, 0x7e, 0xf2, 0xac, 0x61, 0xc6, 0xbe, 0x52, ++ 0x94, 0x8c, 0x93, 0x3e, 0xaa, 0x8e, 0x32, 0x62, 0xc8, 0x1b, 0x94, 0xdd, ++ 0xfd, 0xe3, 0x02, 0xb6, 0xff, 0x95, 0x24, 0x1b, 0x98, 0x9f, 0x8c, 0xc5, ++ 0xef, 0x6f, 0x8a, 0xad, 0xbf, 0xb0, 0xb1, 0xa1, 0x48, 0x2f, 0x9e, 0xe4, ++ 0x60, 0xc3, 0x3b, 0x13, 0x05, 0x93, 0xa5, 0x26, 0x58, 0x4c, 0x7e, 0xb1, ++ 0x8a, 0x3e, 0xfe, 0x76, 0xe4, 0xd8, 0x13, 0x95, 0xe4, 0xc0, 0x3b, 0x22, ++ 0x75, 0x66, 0x35, 0x2c, 0xfe, 0x3e, 0x3c, 0x5b, 0xc5, 0x1d, 0xbc, 0x3e, ++ 0xc4, 0xeb, 0x1a, 0xb8, 0x8e, 0xab, 0x56, 0x46, 0x0d, 0xda, 0x71, 0x22, ++ 0xc9, 0x58, 0xf9, 0x76, 0xa2, 0xbe, 0xfd, 0x80, 0x72, 0xd9, 0x32, 0x1f, ++ 0x99, 0xce, 0xef, 0x7c, 0x38, 0x1d, 0x0f, 0x0c, 0x1f, 0x42, 0xbd, 0x71, ++ 0x4d, 0xf1, 0x62, 0xd8, 0x27, 0x7b, 0x73, 0x74, 0xb4, 0x2f, 0xed, 0xc1, ++ 0xec, 0xd9, 0xaf, 0x33, 0x86, 0xc8, 0xbc, 0xbf, 0x9d, 0xe8, 0xf0, 0x1c, ++ 0x19, 0x77, 0x1a, 0xef, 0x3b, 0x3b, 0xca, 0x3e, 0x6f, 0xe4, 0x5d, 0x45, ++ 0xd7, 0xed, 0x52, 0xb8, 0x89, 0x35, 0xaf, 0xdf, 0xa8, 0x57, 0x37, 0x10, ++ 0x23, 0x62, 0xea, 0xed, 0xec, 0xb2, 0x94, 0x76, 0x19, 0x63, 0x1e, 0x59, ++ 0x09, 0xd5, 0x8e, 0x51, 0xcb, 0x90, 0xee, 0x1b, 0xcd, 0x2f, 0x1f, 0xcf, ++ 0xf3, 0x4b, 0x62, 0x49, 0x75, 0xf7, 0xf1, 0x22, 0x84, 0xa9, 0x8b, 0xab, ++ 0xdf, 0x24, 0x89, 0xed, 0x25, 0xc4, 0xf6, 0xab, 0x7b, 0xca, 0xf0, 0xf6, ++ 0x9e, 0x26, 0x64, 0xab, 0xe5, 0x1e, 0x37, 0x8a, 0xb8, 0xeb, 0x8c, 0x1d, ++ 0xf3, 0x5d, 0xa8, 0xdd, 0xf9, 0x83, 0x7c, 0xaf, 0x42, 0x47, 0x71, 0x92, ++ 0x48, 0xd9, 0xea, 0x86, 0x67, 0xa7, 0xcc, 0x31, 0xe6, 0x26, 0xbb, 0xf4, ++ 0xea, 0x25, 0x68, 0xf1, 0x09, 0x6e, 0x64, 0x26, 0x49, 0x2c, 0x3d, 0xca, ++ 0xb5, 0x1c, 0xa7, 0xad, 0xaf, 0x30, 0xee, 0x96, 0x1e, 0x1a, 0xaf, 0x97, ++ 0xfb, 0x24, 0xb7, 0xb1, 0xb0, 0xd5, 0x28, 0x42, 0xdd, 0x38, 0x0b, 0x29, ++ 0x23, 0xc6, 0xb8, 0x15, 0x41, 0x8c, 0x3c, 0xbe, 0x42, 0x97, 0xcf, 0x2a, ++ 0x2e, 0x32, 0x2f, 0x1b, 0x68, 0x50, 0xf0, 0xf1, 0x4c, 0xe1, 0x03, 0x21, ++ 0xe3, 0x6d, 0xe5, 0x6f, 0x6c, 0x2c, 0xd6, 0x5c, 0x96, 0xfd, 0x4c, 0x86, ++ 0x60, 0x47, 0x89, 0xcd, 0x8d, 0x26, 0xd8, 0x98, 0xa3, 0xb9, 0xe4, 0x4c, ++ 0x47, 0x3c, 0x32, 0x37, 0x55, 0x3f, 0x1c, 0x74, 0x93, 0xa7, 0xfd, 0x87, ++ 0x99, 0xe4, 0x67, 0x36, 0x4f, 0x18, 0x1d, 0x8f, 0x9a, 0x80, 0xd1, 0xf2, ++ 0x08, 0xa8, 0x67, 0xaf, 0xe7, 0xe5, 0xce, 0x1e, 0x76, 0xf4, 0xfd, 0x3f, ++ 0xab, 0xf5, 0xa6, 0xf5, 0x17, 0xf0, 0xe5, 0x85, 0x49, 0xce, 0xf3, 0x37, ++ 0xe2, 0x8f, 0xb4, 0x97, 0xe4, 0xaf, 0xac, 0xc7, 0x6c, 0x4e, 0x67, 0x4e, ++ 0x92, 0xb3, 0x0d, 0x9e, 0x9d, 0xeb, 0x26, 0x49, 0x8d, 0xdd, 0x35, 0x8a, ++ 0x1b, 0x38, 0xf1, 0xf6, 0xbc, 0xb5, 0xd0, 0x5e, 0xeb, 0x96, 0xfc, 0x75, ++ 0x92, 0x43, 0xcb, 0x5a, 0x14, 0xfc, 0x5c, 0xaf, 0x57, 0xdf, 0x40, 0x85, ++ 0xe0, 0x4c, 0x4c, 0x7a, 0x8b, 0x65, 0x7a, 0xd0, 0x7f, 0x90, 0xef, 0xdb, ++ 0xf9, 0xfb, 0xeb, 0xba, 0xa7, 0x69, 0x0d, 0xa4, 0xcf, 0xe8, 0xa2, 0xae, ++ 0xea, 0xfd, 0x6f, 0x20, 0x14, 0x2b, 0x51, 0xae, 0x59, 0xed, 0x3e, 0xb9, ++ 0x26, 0xff, 0xec, 0xb0, 0x72, 0xc6, 0xae, 0x9f, 0x38, 0x36, 0x33, 0xd9, ++ 0x3e, 0xcb, 0x7f, 0x34, 0x27, 0x7c, 0xe4, 0x2e, 0xee, 0x5d, 0x45, 0x5f, ++ 0x4e, 0xb8, 0x83, 0xd7, 0xe6, 0x47, 0xea, 0xf4, 0xe9, 0xda, 0x2a, 0x1c, ++ 0x9d, 0x24, 0xcf, 0xc3, 0x6d, 0x34, 0x30, 0xc5, 0x85, 0xf7, 0xa6, 0xb8, ++ 0xa2, 0x3f, 0x78, 0x66, 0x41, 0xe3, 0x65, 0xd9, 0x17, 0x23, 0xab, 0x5d, ++ 0xaf, 0xf5, 0xcb, 0xf3, 0xbd, 0xf3, 0xc9, 0xb7, 0x7a, 0x99, 0xe3, 0xcf, ++ 0x6f, 0xf8, 0x17, 0xeb, 0x71, 0x4f, 0x4c, 0x73, 0x63, 0xba, 0xb6, 0x19, ++ 0x5f, 0x5a, 0x19, 0x9f, 0xfc, 0x2e, 0x63, 0xc8, 0x73, 0xa8, 0x1c, 0x9f, ++ 0x1c, 0xe5, 0x7b, 0xd3, 0x2d, 0xe6, 0xcf, 0xae, 0x7b, 0xdc, 0xf4, 0x97, ++ 0x12, 0xfd, 0x9c, 0x55, 0x37, 0x7e, 0xba, 0xdf, 0xa5, 0xd4, 0xd1, 0x3a, ++ 0x7c, 0x78, 0x91, 0xf6, 0xfb, 0x62, 0x4e, 0xe2, 0xa2, 0x8a, 0xc3, 0xf4, ++ 0xdf, 0x43, 0x75, 0xc1, 0xce, 0x4b, 0xcc, 0x27, 0x3f, 0x22, 0xcf, 0x7f, ++ 0x47, 0x0f, 0xb4, 0x9f, 0x92, 0x5a, 0x63, 0xc4, 0x83, 0x37, 0x1b, 0xbe, ++ 0xb4, 0x6b, 0xbf, 0x89, 0xfd, 0x2a, 0x7a, 0x53, 0x0e, 0x0e, 0xbc, 0x4c, ++ 0xff, 0xbe, 0xd1, 0x57, 0x6f, 0xc4, 0x86, 0x5d, 0x67, 0xed, 0x67, 0x18, ++ 0xc4, 0xbf, 0x6e, 0xd4, 0x8a, 0xec, 0xe7, 0x47, 0xe8, 0x17, 0xcb, 0xa5, ++ 0x5f, 0x68, 0x66, 0xe0, 0xa1, 0x7c, 0xe7, 0x93, 0x07, 0x4b, 0xec, 0x6d, ++ 0x60, 0xce, 0xeb, 0xa1, 0xff, 0x9c, 0x62, 0xfe, 0xc1, 0xb5, 0x45, 0x2d, ++ 0xeb, 0x3c, 0xf3, 0xb1, 0x3e, 0xd4, 0xab, 0x27, 0xb0, 0x98, 0x5c, 0x96, ++ 0x3c, 0x27, 0xc7, 0x9c, 0xd5, 0xce, 0xa7, 0x82, 0xea, 0x7d, 0xca, 0x2c, ++ 0xee, 0xbf, 0x05, 0xdd, 0x87, 0x34, 0xf2, 0x1d, 0xcb, 0x5a, 0x64, 0xfc, ++ 0x0c, 0x35, 0xbb, 0xba, 0x3b, 0x6b, 0x28, 0x8f, 0xcf, 0x22, 0x66, 0x07, ++ 0xb1, 0x7e, 0xf5, 0x09, 0xa5, 0xbe, 0x2d, 0xa1, 0x3c, 0x4e, 0x7d, 0x84, ++ 0x6d, 0x8e, 0xbd, 0x35, 0xd5, 0x4a, 0xbf, 0xfe, 0xcf, 0xd8, 0xaa, 0x2a, ++ 0xf3, 0x18, 0xf2, 0xc8, 0x13, 0x11, 0x52, 0xa3, 0xfa, 0xa9, 0x73, 0xee, ++ 0xbf, 0x86, 0x31, 0xa1, 0x89, 0xbf, 0x49, 0xbc, 0x0f, 0xdb, 0xcf, 0x98, ++ 0x9c, 0x8f, 0x77, 0xe2, 0x78, 0x96, 0x76, 0x1d, 0xef, 0xc1, 0x89, 0xac, ++ 0xcc, 0x29, 0x3c, 0xab, 0x01, 0x89, 0x5d, 0x6e, 0x0c, 0x1a, 0xc1, 0x58, ++ 0x15, 0xe5, 0x52, 0x16, 0x09, 0xc4, 0x16, 0x13, 0x5b, 0x7b, 0xfa, 0xb2, ++ 0x78, 0x73, 0x77, 0xa0, 0xbd, 0x4e, 0xd1, 0x11, 0xcf, 0x41, 0xfd, 0xe1, ++ 0x9c, 0x2c, 0xde, 0xe8, 0x5f, 0x02, 0x6d, 0x7c, 0x40, 0x9b, 0xaf, 0x2c, ++ 0xc2, 0xc6, 0xdc, 0xbf, 0x56, 0x63, 0xd2, 0x39, 0xf7, 0x22, 0x98, 0x94, ++ 0xfd, 0x16, 0xb4, 0x4e, 0x16, 0x7c, 0xdb, 0x9c, 0xab, 0xc0, 0x54, 0xc6, ++ 0xa9, 0x17, 0xec, 0xf8, 0xeb, 0xf8, 0x51, 0xad, 0xfe, 0xb1, 0xf5, 0x68, ++ 0x3e, 0xb6, 0x7f, 0xb7, 0xbc, 0xfe, 0xce, 0x8a, 0xa9, 0x22, 0x2f, 0xb9, ++ 0xaf, 0x16, 0xa5, 0x1c, 0x67, 0x6b, 0x3e, 0x8e, 0x57, 0xeb, 0xff, 0xdb, ++ 0x5a, 0x62, 0x8f, 0x31, 0x8d, 0xf3, 0xc8, 0x9e, 0xc2, 0xf9, 0x7d, 0x1b, ++ 0xf8, 0x3c, 0x2e, 0xb5, 0x0e, 0x15, 0x27, 0x0c, 0xc1, 0x91, 0x45, 0xf4, ++ 0xd5, 0x22, 0xac, 0x6e, 0xa0, 0x3b, 0xda, 0x75, 0xfe, 0x11, 0x6c, 0x4b, ++ 0x7f, 0x6d, 0x3d, 0x45, 0x3b, 0xba, 0x9f, 0xdc, 0x46, 0x23, 0x0e, 0xac, ++ 0x88, 0xb4, 0x92, 0x8b, 0x72, 0xcf, 0x29, 0x0f, 0x31, 0x48, 0x41, 0xaa, ++ 0x89, 0xfe, 0x1f, 0xb9, 0x2b, 0xff, 0xbc, 0xdd, 0x3f, 0x4c, 0x72, 0x6a, ++ 0x8b, 0x3f, 0x9f, 0xec, 0xe0, 0xa6, 0xc8, 0xff, 0xdf, 0x22, 0xbf, 0x97, ++ 0x2d, 0xad, 0x46, 0xe4, 0xe7, 0x81, 0x3f, 0xd4, 0x80, 0xbd, 0xbc, 0xe6, ++ 0xf4, 0x6e, 0x0f, 0x76, 0xea, 0x8b, 0xb0, 0x33, 0x07, 0xed, 0x33, 0x5e, ++ 0xf3, 0x9b, 0xfe, 0x25, 0x93, 0x1d, 0x0e, 0xf1, 0x1e, 0xba, 0xe3, 0x4f, ++ 0x5b, 0xf7, 0xd4, 0xc8, 0x7e, 0x8b, 0xe0, 0xe7, 0x7e, 0xf7, 0x5e, 0xaf, ++ 0xf3, 0xad, 0xb2, 0x96, 0xda, 0x5c, 0x7e, 0x29, 0xaf, 0x15, 0x1d, 0x58, ++ 0xb8, 0x68, 0xac, 0xb6, 0xf3, 0x73, 0x40, 0x74, 0x2d, 0xba, 0x95, 0xb5, ++ 0xdd, 0x93, 0x97, 0xc7, 0xae, 0xf1, 0x37, 0xaf, 0x7b, 0x41, 0xde, 0x96, ++ 0xa5, 0x9f, 0x5e, 0xe0, 0xfe, 0x62, 0xcb, 0x62, 0xc7, 0x62, 0xd7, 0x81, ++ 0x34, 0xf0, 0x08, 0xed, 0xf9, 0xcf, 0x9c, 0x43, 0x6a, 0x2d, 0x8b, 0xe4, ++ 0x19, 0x1c, 0x6b, 0x95, 0x51, 0xaf, 0x9d, 0xc0, 0x7f, 0xa4, 0x6d, 0x37, ++ 0x62, 0xcb, 0x2e, 0xa9, 0xc3, 0x6a, 0x8a, 0x67, 0xcf, 0x52, 0x5c, 0x54, ++ 0x75, 0x62, 0xa7, 0xd8, 0xa1, 0xe0, 0x8a, 0xac, 0x43, 0xb0, 0xa5, 0x8d, ++ 0xbc, 0xc9, 0x3e, 0xcf, 0x11, 0xab, 0x8d, 0x76, 0x2a, 0x1f, 0xd5, 0x75, ++ 0xe2, 0x48, 0xc4, 0xb4, 0xaa, 0xf4, 0x50, 0x5b, 0xad, 0x0b, 0xa5, 0xb9, ++ 0xc6, 0x12, 0x0c, 0x45, 0x84, 0x57, 0xc2, 0x9b, 0xcd, 0x06, 0xcc, 0x31, ++ 0x6e, 0xd5, 0xfb, 0x52, 0x36, 0x8f, 0x95, 0xae, 0x8a, 0xc9, 0xf2, 0x2c, ++ 0x60, 0xda, 0xc6, 0x91, 0xd9, 0xb8, 0xd7, 0xd6, 0xad, 0xca, 0x7c, 0x52, ++ 0xea, 0xc0, 0x47, 0x22, 0x97, 0xe3, 0x82, 0x29, 0xd6, 0xbc, 0x8d, 0x91, ++ 0x7a, 0x75, 0x0b, 0x82, 0xc4, 0xae, 0x79, 0x78, 0xdb, 0x68, 0xa3, 0xcf, ++ 0x98, 0xcf, 0x7a, 0x20, 0xbd, 0xb9, 0xc3, 0x91, 0x8d, 0x71, 0x89, 0x4b, ++ 0xf3, 0x91, 0xde, 0x15, 0x88, 0xed, 0x25, 0x47, 0xaa, 0x52, 0xf4, 0x8e, ++ 0xad, 0x88, 0x2d, 0xa9, 0xb2, 0xfb, 0xa2, 0x5d, 0xd8, 0x67, 0x98, 0x18, ++ 0x13, 0x15, 0x9b, 0x8b, 0x95, 0x86, 0xe6, 0x28, 0x38, 0x37, 0x27, 0xd4, ++ 0xf4, 0xa8, 0xd2, 0x49, 0xdc, 0x2b, 0xc1, 0x66, 0x43, 0xfe, 0x3d, 0x86, ++ 0x0a, 0xf2, 0x98, 0xc0, 0xf0, 0x09, 0x84, 0xda, 0x96, 0x2b, 0xa1, 0xd6, ++ 0xf3, 0x08, 0x74, 0xce, 0x73, 0x13, 0x83, 0xff, 0xc2, 0xe3, 0xbd, 0x73, ++ 0x20, 0x8a, 0xbd, 0x39, 0x9f, 0xb7, 0x7e, 0x80, 0x79, 0x60, 0x2e, 0x8c, ++ 0x3b, 0x99, 0xff, 0x7a, 0x06, 0x0c, 0xef, 0x8c, 0x81, 0xf9, 0xe4, 0xab, ++ 0x22, 0x5b, 0x37, 0x63, 0x5f, 0x1d, 0x3a, 0x5a, 0xcf, 0x5a, 0x7d, 0x21, ++ 0xe6, 0xa0, 0xfa, 0x64, 0x3c, 0xcd, 0x58, 0x5d, 0x6c, 0xf3, 0x8d, 0xef, ++ 0xf2, 0x19, 0x37, 0xed, 0x70, 0xd0, 0xd2, 0x1e, 0x11, 0x59, 0x5e, 0x9c, ++ 0x2c, 0xcf, 0x25, 0xa6, 0xf3, 0x72, 0x5d, 0x79, 0x5d, 0xae, 0xd2, 0x97, ++ 0x23, 0xd7, 0xa1, 0xde, 0x56, 0x56, 0xdf, 0xd0, 0xcd, 0x72, 0x23, 0xd8, ++ 0xd6, 0x0b, 0xe9, 0xd3, 0xdd, 0x71, 0x07, 0xca, 0xa4, 0x36, 0x73, 0x37, ++ 0x0e, 0x56, 0x3b, 0xb9, 0x8a, 0xe6, 0x2a, 0x27, 0x16, 0x17, 0x62, 0x8b, ++ 0xfc, 0x1e, 0x48, 0xc7, 0xc8, 0x75, 0xd6, 0x36, 0x5c, 0xb3, 0x62, 0x35, ++ 0xe6, 0x35, 0xb7, 0x7d, 0xfe, 0xe6, 0x67, 0x3f, 0xbb, 0xac, 0x07, 0x4e, ++ 0x5d, 0xe6, 0x87, 0x99, 0xc4, 0xbc, 0x8c, 0xfd, 0x5f, 0x9f, 0xca, 0xd8, ++ 0x45, 0xe8, 0x6d, 0xb8, 0x03, 0xb1, 0x65, 0x32, 0xa6, 0x60, 0x95, 0x65, ++ 0xb5, 0x44, 0x82, 0x2d, 0x87, 0x51, 0x84, 0xbb, 0x66, 0xba, 0xc9, 0xab, ++ 0x2d, 0x34, 0x47, 0xbe, 0xb6, 0x06, 0x19, 0x33, 0x47, 0x22, 0xb2, 0x5e, ++ 0xe6, 0xf2, 0xf4, 0x1d, 0x7f, 0x8d, 0x82, 0x7d, 0xf4, 0x9d, 0x99, 0xb3, ++ 0xbf, 0x27, 0xcf, 0x42, 0x49, 0x4f, 0x13, 0x3b, 0xc8, 0xdd, 0x43, 0x3b, ++ 0x89, 0xd9, 0x8d, 0x23, 0x08, 0xf6, 0x16, 0xd6, 0x2e, 0xbe, 0x5a, 0x58, ++ 0xbf, 0xf4, 0x11, 0x65, 0x1e, 0x59, 0xa3, 0xec, 0xa5, 0xf0, 0xfd, 0x8d, ++ 0xcf, 0x6e, 0xbd, 0x48, 0xea, 0x64, 0xfc, 0x33, 0x77, 0xa2, 0x83, 0x21, ++ 0x85, 0xfd, 0x0c, 0xd7, 0xde, 0xfc, 0xf9, 0xbf, 0xdf, 0xf2, 0xfb, 0x84, ++ 0x5b, 0x7e, 0x9f, 0x3f, 0xe9, 0xe6, 0xcf, 0x05, 0x1f, 0xb9, 0x21, 0xd3, ++ 0xa7, 0x8d, 0x60, 0x53, 0x96, 0xfb, 0xb4, 0x1a, 0x0e, 0x5b, 0x67, 0x1f, ++ 0x96, 0xb5, 0x88, 0x6f, 0xc9, 0xfa, 0xde, 0xc3, 0xb1, 0xec, 0xad, 0x6b, ++ 0x7b, 0x37, 0xdf, 0x47, 0x10, 0xff, 0x09, 0xd3, 0x97, 0x46, 0x9f, 0x4f, ++ 0x77, 0xce, 0xe0, 0x55, 0x44, 0xc3, 0x4a, 0x4f, 0xc2, 0xb4, 0xc6, 0xe8, ++ 0x65, 0x66, 0x49, 0x14, 0x8a, 0x1a, 0x32, 0x51, 0x1e, 0xd2, 0x57, 0x8f, ++ 0x71, 0x75, 0xa1, 0x68, 0x96, 0xde, 0xf1, 0x8c, 0x92, 0x46, 0x72, 0x20, ++ 0x10, 0x3e, 0x44, 0x5c, 0x49, 0x0c, 0x5c, 0x65, 0x0e, 0xde, 0x85, 0x1f, ++ 0x46, 0x3c, 0x66, 0x59, 0x34, 0xe0, 0x9f, 0xa1, 0x2c, 0xc0, 0x96, 0xbe, ++ 0x9f, 0x61, 0x55, 0x5a, 0xf2, 0x01, 0x0d, 0x1b, 0x72, 0x2e, 0x1c, 0xa3, ++ 0xcd, 0xf7, 0x70, 0x2e, 0x62, 0xa2, 0x3f, 0x03, 0x39, 0x93, 0xd6, 0x08, ++ 0xa9, 0xa7, 0x78, 0x68, 0x23, 0x1b, 0xfb, 0xde, 0xc2, 0xaa, 0xb8, 0x85, ++ 0xcf, 0x0c, 0xc6, 0x23, 0x5d, 0xea, 0xc0, 0x92, 0x67, 0x2f, 0xb3, 0xf1, ++ 0xf5, 0xe1, 0xe4, 0x1d, 0xe4, 0xfa, 0xe2, 0xbf, 0xf3, 0xe9, 0xc7, 0x0a, ++ 0x3e, 0x97, 0x1e, 0x25, 0x73, 0xec, 0xa3, 0xe4, 0x91, 0x43, 0xf1, 0x75, ++ 0xe8, 0xa7, 0xef, 0xd4, 0xea, 0x7a, 0x4f, 0xad, 0xdb, 0x39, 0xaf, 0x9b, ++ 0x32, 0x42, 0xed, 0xa7, 0x15, 0x39, 0xb3, 0x1b, 0x62, 0xec, 0xf9, 0x06, ++ 0x7f, 0x34, 0xa4, 0xf6, 0x66, 0x78, 0x17, 0xd2, 0xde, 0xf7, 0xf4, 0xc9, ++ 0x7d, 0xdc, 0xeb, 0x6d, 0x6b, 0x1d, 0xd2, 0x8f, 0x36, 0xf2, 0x75, 0xc9, ++ 0xb7, 0x70, 0x30, 0xeb, 0xc5, 0xa3, 0x49, 0x4d, 0x99, 0xba, 0x47, 0xc5, ++ 0x82, 0x64, 0x60, 0x78, 0x9e, 0x9b, 0x9c, 0x64, 0xf6, 0x18, 0x8e, 0xa7, ++ 0xe0, 0xd5, 0x59, 0x12, 0x1f, 0xfe, 0x1d, 0xcc, 0xf1, 0xcd, 0x1c, 0x13, ++ 0x15, 0xc5, 0x73, 0x02, 0xea, 0x41, 0x57, 0xd0, 0xff, 0x47, 0x6c, 0x24, ++ 0xbf, 0x6f, 0x45, 0x37, 0xd7, 0x7f, 0x7f, 0x52, 0xfa, 0x5b, 0xf5, 0x00, ++ 0xed, 0x7e, 0xeb, 0x21, 0x53, 0xfa, 0x42, 0xe6, 0xb8, 0x28, 0x34, 0x5f, ++ 0xb4, 0x7c, 0x0a, 0xca, 0xbe, 0x21, 0x2f, 0x1f, 0x91, 0x5c, 0x75, 0x75, ++ 0x95, 0xcb, 0x62, 0xae, 0x33, 0x23, 0xdf, 0xbf, 0x98, 0x8f, 0x8d, 0xbb, ++ 0xa4, 0x36, 0x4f, 0x2c, 0x37, 0x98, 0x33, 0x55, 0xeb, 0xe1, 0x15, 0x2e, ++ 0xe9, 0x19, 0xad, 0x43, 0x30, 0xb1, 0x0e, 0xe1, 0x84, 0xf8, 0xac, 0xae, ++ 0x76, 0x20, 0xf6, 0x86, 0xd4, 0x04, 0xa7, 0x46, 0x42, 0x5c, 0x57, 0xa8, ++ 0xc7, 0xe7, 0x36, 0xbc, 0x2f, 0x0f, 0xaa, 0x18, 0x56, 0x9d, 0x9c, 0xf3, ++ 0x50, 0x5a, 0x6f, 0x2b, 0x71, 0xc9, 0x19, 0xbf, 0x4b, 0x56, 0xcc, 0x1e, ++ 0xf7, 0x28, 0x31, 0xaa, 0x05, 0x3b, 0x9e, 0xbf, 0xc2, 0xb8, 0x24, 0x73, ++ 0xfc, 0x99, 0x7c, 0xbe, 0x08, 0xf3, 0x97, 0x69, 0xb8, 0x37, 0x29, 0x35, ++ 0xd5, 0xbf, 0x1c, 0xef, 0x9c, 0x19, 0x91, 0xcf, 0x1e, 0x74, 0x18, 0x04, ++ 0xde, 0xf1, 0x5f, 0x59, 0x3e, 0x3b, 0x87, 0xfd, 0x95, 0x6d, 0x33, 0x9b, ++ 0x53, 0x57, 0xef, 0x10, 0x1f, 0xdf, 0x9c, 0x3b, 0xef, 0x77, 0x6c, 0xef, ++ 0x2b, 0x7e, 0x96, 0xb1, 0xf4, 0xbd, 0xeb, 0xd0, 0x36, 0x5e, 0x38, 0xce, ++ 0xc3, 0x83, 0xa3, 0xaf, 0x2f, 0xd4, 0x6b, 0x7c, 0x79, 0x9e, 0x55, 0xb0, ++ 0x37, 0xe9, 0x0b, 0xc6, 0x94, 0xa5, 0xf1, 0x16, 0x65, 0x61, 0xdc, 0x7e, ++ 0x1e, 0x23, 0x5e, 0x6e, 0x9f, 0xe7, 0xb4, 0xf0, 0x93, 0xc8, 0x90, 0xb2, ++ 0xc9, 0x3e, 0x2b, 0x6a, 0x2a, 0xe9, 0x46, 0xa0, 0x66, 0xb0, 0x59, 0xd9, ++ 0x12, 0xff, 0xd4, 0x5a, 0x61, 0xf7, 0xe0, 0xc7, 0x62, 0x43, 0x83, 0x07, ++ 0x25, 0x83, 0x5e, 0x54, 0x1f, 0x2c, 0x47, 0x71, 0xaf, 0x8e, 0xb1, 0x83, ++ 0x0f, 0x91, 0xcb, 0x0a, 0xff, 0x91, 0xe7, 0x5e, 0x24, 0x77, 0xfb, 0xfa, ++ 0x67, 0x0f, 0x84, 0x02, 0xe4, 0xf6, 0x80, 0x27, 0xe1, 0x85, 0x09, 0xfb, ++ 0x0f, 0xf3, 0xaa, 0xc3, 0xcc, 0xab, 0xac, 0x79, 0x3f, 0x89, 0x98, 0x5b, ++ 0xc7, 0x22, 0x70, 0xaa, 0xc6, 0x65, 0x5a, 0x92, 0x4f, 0x45, 0xdc, 0x50, ++ 0x16, 0x4d, 0x37, 0x71, 0xdf, 0x74, 0xf9, 0xb7, 0x06, 0x74, 0xff, 0x45, ++ 0xb1, 0x9f, 0x48, 0x17, 0x3e, 0x30, 0xba, 0xb0, 0xcd, 0x28, 0x33, 0xfd, ++ 0xf6, 0xb3, 0xf0, 0x15, 0x66, 0x65, 0x54, 0x57, 0x37, 0x41, 0x37, 0x36, ++ 0x29, 0x01, 0x73, 0x31, 0x63, 0xe4, 0xa5, 0x5c, 0x20, 0x76, 0x8d, 0xf6, ++ 0x7f, 0x3e, 0x17, 0xd8, 0x7b, 0xa7, 0x12, 0x66, 0x9e, 0x6d, 0x10, 0xff, ++ 0x89, 0xcf, 0xdc, 0xe7, 0xae, 0xdc, 0x4c, 0xe1, 0x0b, 0x66, 0x7b, 0xfe, ++ 0x3c, 0xf1, 0x53, 0xd2, 0xf7, 0x2c, 0x92, 0x5e, 0x99, 0xa9, 0xac, 0x6c, ++ 0x14, 0x9f, 0xac, 0xc4, 0x79, 0x46, 0xac, 0x57, 0xb2, 0xc5, 0x38, 0xd2, ++ 0x8f, 0xf1, 0x6e, 0xb8, 0xbf, 0x71, 0xa1, 0x2e, 0x3d, 0x15, 0xc7, 0xea, ++ 0x6a, 0xf0, 0xd7, 0xe4, 0xfc, 0x9d, 0x38, 0xa6, 0x77, 0xb7, 0xd7, 0xea, ++ 0xd2, 0xc7, 0x2c, 0x42, 0x26, 0xe3, 0x22, 0x0f, 0x29, 0xc7, 0xd1, 0x0c, ++ 0x26, 0x7b, 0xe8, 0x4b, 0xdb, 0x53, 0xa8, 0x73, 0x45, 0x43, 0xe9, 0xe5, ++ 0x8c, 0x7d, 0xaf, 0x64, 0x7d, 0xc8, 0x64, 0x75, 0xbe, 0xc2, 0x7c, 0x35, ++ 0xf0, 0xd5, 0x84, 0x9f, 0x24, 0xc4, 0xd6, 0xfc, 0xf8, 0x45, 0xb6, 0x12, ++ 0x17, 0xd2, 0x7a, 0x8f, 0x87, 0x76, 0x10, 0x9a, 0x25, 0x67, 0x7a, 0x35, ++ 0x3b, 0xb7, 0xb8, 0x4a, 0x3f, 0xed, 0x89, 0x54, 0xe2, 0x4a, 0xe6, 0x76, ++ 0xf9, 0x23, 0xd4, 0xca, 0xa8, 0xf8, 0x4b, 0x38, 0xef, 0x07, 0x43, 0xca, ++ 0xe2, 0x01, 0x28, 0x8f, 0x4d, 0x17, 0x79, 0x75, 0xe1, 0xda, 0x6c, 0x27, ++ 0xdf, 0xbd, 0xe8, 0x2e, 0x33, 0x6b, 0xa3, 0x01, 0xad, 0xd6, 0xad, 0x33, ++ 0xef, 0x1d, 0x41, 0x92, 0x76, 0x3c, 0x28, 0x3d, 0x90, 0xc8, 0x87, 0x96, ++ 0x59, 0x2d, 0xe7, 0x37, 0x3a, 0x91, 0xd4, 0x6b, 0x98, 0x1b, 0xc9, 0xd9, ++ 0xfc, 0xc3, 0x91, 0x78, 0xc2, 0x9a, 0xf7, 0x52, 0x24, 0xd0, 0xb2, 0x53, ++ 0x31, 0x97, 0x94, 0x43, 0xf4, 0xa3, 0x6b, 0x45, 0x94, 0xdb, 0x48, 0xb6, ++ 0x8b, 0x39, 0x58, 0x05, 0xc7, 0x0c, 0x68, 0x97, 0x50, 0x89, 0x0d, 0xf6, ++ 0x99, 0x0c, 0x0b, 0xf3, 0x8d, 0x33, 0xcc, 0x17, 0x99, 0x03, 0xe6, 0x2a, ++ 0xb1, 0x97, 0x7c, 0x68, 0xcc, 0xec, 0x7f, 0xb2, 0xce, 0x8e, 0x93, 0xf5, ++ 0xce, 0x9c, 0x50, 0x38, 0x7f, 0x28, 0xb2, 0xfd, 0x29, 0x65, 0xab, 0x39, ++ 0xff, 0xd6, 0x87, 0x6d, 0x2b, 0x6b, 0xe3, 0x1e, 0xbe, 0x8b, 0x7d, 0xc8, ++ 0x99, 0x4f, 0xc6, 0x11, 0xdb, 0x46, 0x9e, 0x9b, 0x92, 0x3f, 0xdb, 0xd9, ++ 0x5e, 0x13, 0xf5, 0x36, 0xcc, 0x4f, 0xba, 0x3f, 0x95, 0xe7, 0xbb, 0x97, ++ 0x37, 0xea, 0xd7, 0x7a, 0xe1, 0x6d, 0x78, 0x6c, 0xd0, 0xdb, 0xd0, 0x96, ++ 0x3c, 0xa2, 0xd4, 0x46, 0x43, 0x7b, 0x6b, 0xdd, 0xde, 0x86, 0x87, 0x6f, ++ 0x5c, 0xaf, 0x2c, 0x9e, 0xde, 0x85, 0x5c, 0xa4, 0x4c, 0xfe, 0xbd, 0x00, ++ 0x72, 0x81, 0x40, 0xf8, 0x53, 0xc5, 0xe6, 0x00, 0x66, 0x79, 0x54, 0xc7, ++ 0xd3, 0x03, 0x39, 0xe6, 0xa5, 0x82, 0x67, 0x6e, 0xce, 0x75, 0x15, 0x2f, ++ 0x67, 0x6e, 0xdc, 0xd7, 0xc2, 0xfb, 0xca, 0x78, 0x5f, 0x79, 0x54, 0xe2, ++ 0x7a, 0xc0, 0x58, 0xc8, 0xfd, 0x96, 0x2a, 0xd2, 0x5f, 0xd3, 0x71, 0x21, ++ 0xbb, 0x67, 0x8a, 0xd4, 0x38, 0x36, 0xe7, 0x6a, 0xf0, 0xc0, 0x6e, 0x6b, ++ 0x9e, 0x77, 0x96, 0x35, 0x6f, 0x51, 0x64, 0xa3, 0xd5, 0x33, 0x4e, 0x74, ++ 0x3e, 0x82, 0xd3, 0x69, 0x99, 0x4b, 0x6f, 0x39, 0xcd, 0xfc, 0x74, 0x66, ++ 0x64, 0xbd, 0x95, 0xb1, 0xe3, 0x07, 0xed, 0x9e, 0x73, 0x9c, 0xcc, 0x88, ++ 0x1d, 0x6d, 0x6c, 0xf7, 0x33, 0x87, 0x95, 0x67, 0x98, 0x87, 0x68, 0x1f, ++ 0x07, 0x33, 0xe6, 0x14, 0x79, 0xfe, 0x60, 0xaa, 0x2e, 0x72, 0xf8, 0xff, ++ 0x7a, 0x10, 0xad, 0x46, 0x28, 0x7c, 0x00, 0x00, 0x00 }; + + static const u32 bnx2_RXP_b09FwData[(0x0/4) + 1] = { 0x0 }; +-static const u32 bnx2_RXP_b09FwRodata[(0xf0/4) + 1] = { ++static const u32 bnx2_RXP_b09FwRodata[(0x124/4) + 1] = { ++ 0x0800330c, 0x0800330c, 0x080033e8, 0x080033bc, 0x080033a0, 0x080032f0, ++ 0x080032f0, 0x080032f0, 0x08003314, 0x80080100, 0x80080080, 0x80080000, + 0x5f865437, 0xe4ac62cc, 0x50103a45, 0x36621985, 0xbf14c0e8, 0x1bc27a1e, +- 0x84f4b556, 0x094ea6fe, 0x7dda01e7, 0xc04d7481, 0x80080100, 0x80080080, +- 0x80080000, 0x08004efc, 0x08004efc, 0x08004fd8, 0x08004fac, 0x08004f90, +- 0x08004ecc, 0x08004ecc, 0x08004ecc, 0x08004f04, 0x08007220, 0x0800726c, +- 0x0800722c, 0x08007150, 0x0800722c, 0x0800725c, 0x0800722c, 0x08007150, +- 0x08007150, 0x08007150, 0x08007150, 0x08007150, 0x08007150, 0x08007150, +- 0x08007150, 0x08007150, 0x08007150, 0x0800724c, 0x0800723c, 0x08007150, +- 0x08007150, 0x08007150, 0x08007150, 0x08007150, 0x08007150, 0x08007150, +- 0x08007150, 0x08007150, 0x08007150, 0x08007150, 0x08007150, 0x0800723c, +- 0x080077f4, 0x080076bc, 0x080077bc, 0x08007718, 0x080076e8, 0x080075a4, +- 0x00000000 }; ++ 0x84f4b556, 0x094ea6fe, 0x7dda01e7, 0xc04d7481, 0x080075b4, 0x08007600, ++ 0x080075c0, 0x080074e8, 0x080075c0, 0x080075f0, 0x080075c0, 0x080074e8, ++ 0x080074e8, 0x080074e8, 0x080074e8, 0x080074e8, 0x080074e8, 0x080074e8, ++ 0x080074e8, 0x080074e8, 0x080074e8, 0x080075e0, 0x080075d0, 0x080074e8, ++ 0x080074e8, 0x080074e8, 0x080074e8, 0x080074e8, 0x080074e8, 0x080074e8, ++ 0x080074e8, 0x080074e8, 0x080074e8, 0x080074e8, 0x080074e8, 0x080075d0, ++ 0x08007bac, 0x08007a54, 0x08007b74, 0x08007a54, 0x08007b44, 0x0800793c, ++ 0x08007a54, 0x08007a54, 0x08007a54, 0x08007a54, 0x08007a54, 0x08007a54, ++ 0x08007a54, 0x08007a54, 0x08007a54, 0x08007a54, 0x08007a54, 0x08007a54, ++ 0x08007a7c, 0x00000000 }; + + static struct fw_info bnx2_rxp_fw_09 = { +- /* Firmware version: 4.4.23 */ +- .ver_major = 0x4, +- .ver_minor = 0x4, +- .ver_fix = 0x17, +- +- .start_addr = 0x080031d0, ++ /* Firmware version: 5.0.0j */ ++ .ver_major = 0x5, ++ .ver_minor = 0x0, ++ .ver_fix = 0x0, ++ ++ .start_addr = 0x080031d8, + + .text_addr = 0x08000000, +- .text_len = 0x786c, ++ .text_len = 0x7c24, + .text_index = 0x0, + .gz_text = bnx2_RXP_b09FwText, + .gz_text_len = sizeof(bnx2_RXP_b09FwText), +@@ -3158,548 +3251,558 @@ + .data_index = 0x0, + .data = bnx2_RXP_b09FwData, + +- .sbss_addr = 0x08007980, +- .sbss_len = 0x58, +- .sbss_index = 0x0, +- +- .bss_addr = 0x080079d8, +- .bss_len = 0x1c, +- .bss_index = 0x0, +- +- .rodata_addr = 0x0800786c, +- .rodata_len = 0xf0, ++ .sbss_addr = 0x08007d60, ++ .sbss_len = 0x5c, ++ .sbss_index = 0x0, ++ ++ .bss_addr = 0x08007dc0, ++ .bss_len = 0x60, ++ .bss_index = 0x0, ++ ++ .rodata_addr = 0x08007c24, ++ .rodata_len = 0x124, + .rodata_index = 0x0, + .rodata = bnx2_RXP_b09FwRodata, + }; + + static u8 bnx2_xi_rv2p_proc1[] = { +- /* Date: 06/17/2008 16:52 */ +- 0xbd, 0x56, 0xcf, 0x6b, 0x1c, 0x75, 0x14, 0x7f, 0x3b, 0xbb, 0x33, 0x3b, +- 0x99, 0x9d, 0xdd, 0x99, 0xda, 0x34, 0x4c, 0xb7, 0x2b, 0xd9, 0x86, 0x5e, +- 0x36, 0x99, 0x62, 0xa2, 0x11, 0x0a, 0x46, 0x5b, 0x72, 0x09, 0xd8, 0x9e, +- 0x02, 0x95, 0x22, 0x82, 0x71, 0xa9, 0x3d, 0xd8, 0x96, 0xe2, 0x5f, 0xe0, +- 0x90, 0x9a, 0x08, 0x45, 0x0f, 0x0b, 0x36, 0x90, 0x20, 0x1a, 0x7b, 0x50, +- 0x09, 0x0a, 0x3b, 0x07, 0x41, 0x44, 0x2d, 0xa8, 0x88, 0x60, 0x3d, 0x08, +- 0x85, 0xda, 0x8b, 0x51, 0x8b, 0x8a, 0x07, 0x0f, 0x01, 0x8f, 0x9a, 0xf1, +- 0xfb, 0x7e, 0x7c, 0x37, 0x33, 0x93, 0xdd, 0x24, 0x27, 0x03, 0xed, 0x87, +- 0xf7, 0x9d, 0xf7, 0x7d, 0xdf, 0xf7, 0xde, 0xf7, 0xf3, 0x3e, 0xdf, 0xf5, +- 0x01, 0xc0, 0x80, 0x28, 0x1e, 0x55, 0x08, 0x87, 0x8c, 0xa2, 0xad, 0xa0, +- 0x00, 0xf0, 0x21, 0xf0, 0x9f, 0xe9, 0x92, 0x1d, 0x3d, 0x22, 0xf6, 0x04, +- 0x43, 0x34, 0xe1, 0xab, 0xff, 0xaf, 0xc2, 0xe9, 0x26, 0x62, 0x11, 0x4e, +- 0x1f, 0x47, 0x7c, 0x12, 0x6e, 0x37, 0x03, 0x85, 0xff, 0x26, 0x10, 0xa1, +- 0x3d, 0xdc, 0xfd, 0x24, 0xae, 0x50, 0xfc, 0x4d, 0xd9, 0xff, 0x63, 0x91, +- 0xf1, 0x54, 0x68, 0x73, 0x1c, 0x41, 0x38, 0xe9, 0x13, 0xdc, 0xed, 0xa0, +- 0x7d, 0xfe, 0x3c, 0x58, 0x18, 0xe7, 0x6d, 0xe5, 0x80, 0x76, 0xa3, 0x10, +- 0x9d, 0x94, 0xbc, 0x0c, 0xf6, 0xfb, 0xa9, 0xe3, 0xe1, 0x3a, 0xfc, 0x3c, +- 0x8b, 0xf6, 0x51, 0xe7, 0xd5, 0x0e, 0x62, 0x00, 0x97, 0x6c, 0x97, 0xeb, +- 0x19, 0xe5, 0xb0, 0x9b, 0xe3, 0xb8, 0x4f, 0xf9, 0x8e, 0x4b, 0x5c, 0x13, +- 0xe3, 0xfe, 0x99, 0x70, 0x5c, 0x8c, 0x97, 0x8e, 0xd3, 0x50, 0x71, 0x70, +- 0xdd, 0x92, 0xbc, 0xac, 0x5c, 0x5e, 0x96, 0xca, 0x43, 0xfa, 0x00, 0x3a, +- 0x0f, 0xc4, 0x23, 0xea, 0x5c, 0x8c, 0xbb, 0x25, 0x75, 0x03, 0x3c, 0xdf, +- 0x94, 0xf8, 0x31, 0xa2, 0x5b, 0xe0, 0x78, 0xea, 0x9f, 0xd4, 0xb1, 0x3b, +- 0x8e, 0xee, 0x53, 0x36, 0xff, 0x72, 0xa8, 0xbf, 0xeb, 0xfb, 0xc0, 0x73, +- 0x7e, 0x50, 0xe7, 0xa4, 0xfd, 0x61, 0x1f, 0xff, 0xef, 0x94, 0x7f, 0x36, +- 0x2e, 0xaf, 0x7f, 0xbb, 0xb3, 0xde, 0xea, 0xd7, 0x37, 0x33, 0xd7, 0xb7, +- 0x2f, 0xa5, 0x6f, 0x73, 0x70, 0xc2, 0x08, 0xc8, 0xaf, 0x04, 0x88, 0xc7, +- 0x54, 0x02, 0x88, 0x0f, 0x0b, 0x5e, 0x13, 0xbc, 0x25, 0xf8, 0xae, 0xe0, +- 0x11, 0xc1, 0x61, 0xc1, 0xc3, 0x82, 0x0f, 0x09, 0x6e, 0x09, 0xfa, 0x82, +- 0x9e, 0x60, 0x4d, 0xf0, 0x2f, 0x41, 0x57, 0xb0, 0x92, 0x8b, 0x57, 0x17, +- 0xb4, 0x05, 0x3f, 0x17, 0x7c, 0x22, 0xb7, 0xff, 0x68, 0x81, 0xf1, 0x81, +- 0xd8, 0x4f, 0x89, 0x7d, 0x41, 0x6c, 0x6c, 0xa8, 0xf0, 0x3e, 0xd3, 0xaf, +- 0x5b, 0xbd, 0xfb, 0xbd, 0xdb, 0x91, 0xef, 0x2d, 0xed, 0x67, 0x53, 0xff, +- 0x60, 0x3c, 0xed, 0xff, 0xd6, 0x1e, 0xfe, 0xec, 0x36, 0xdb, 0xea, 0xb7, +- 0xef, 0x66, 0xc2, 0x79, 0xbc, 0x29, 0xfb, 0x83, 0xee, 0x67, 0x03, 0xe6, +- 0x68, 0x26, 0xcc, 0xf3, 0xab, 0xdf, 0x1c, 0x3d, 0x2e, 0x73, 0x34, 0xbd, +- 0x8b, 0xbf, 0xcc, 0xd3, 0x33, 0xb2, 0x7f, 0x46, 0xf8, 0xd9, 0x18, 0xe0, +- 0x17, 0xa5, 0xe6, 0x95, 0xce, 0x1b, 0x30, 0x0f, 0x1f, 0x15, 0xda, 0x61, +- 0xc0, 0xfc, 0x89, 0xf6, 0xca, 0x0f, 0xf7, 0x0b, 0x7f, 0x5b, 0x9a, 0xc7, +- 0x59, 0xfe, 0x32, 0x0f, 0xad, 0x1c, 0x0f, 0x5f, 0xde, 0xe7, 0x1e, 0x2a, +- 0xb9, 0x7e, 0x5e, 0x56, 0xfe, 0x6c, 0x1a, 0x06, 0xe3, 0x1a, 0x63, 0xe8, +- 0x5a, 0x25, 0xc4, 0x69, 0xf7, 0x1b, 0x8e, 0x37, 0x4a, 0x75, 0xb8, 0xc1, +- 0x0a, 0xcd, 0x6d, 0x09, 0x56, 0xac, 0x21, 0x85, 0xff, 0x24, 0x6f, 0xb0, +- 0x5f, 0xdd, 0xfc, 0x9e, 0x30, 0x58, 0xbb, 0xc3, 0xfe, 0xf7, 0x9a, 0x9c, +- 0xf7, 0x33, 0x13, 0x90, 0xfb, 0xd3, 0xdf, 0x65, 0xde, 0x3d, 0xb4, 0xff, +- 0x2e, 0x44, 0xb1, 0x3e, 0x47, 0xf6, 0x5d, 0xd6, 0x73, 0xc4, 0x7f, 0x8b, +- 0x96, 0x4f, 0xf5, 0xde, 0x88, 0xc9, 0x1c, 0x76, 0x97, 0x7d, 0xfa, 0xfa, +- 0x7a, 0xac, 0xeb, 0x11, 0x5d, 0x19, 0xd7, 0xf5, 0xf3, 0xfe, 0x2a, 0x9d, +- 0x77, 0xb8, 0xbb, 0x9e, 0xe3, 0x49, 0xf3, 0x40, 0x3a, 0xbb, 0x95, 0xec, +- 0xe8, 0x6c, 0xba, 0x0f, 0x5a, 0x67, 0x6d, 0x58, 0x98, 0xf3, 0xe8, 0xdc, +- 0x9a, 0xc5, 0x61, 0x2e, 0x78, 0x8c, 0x17, 0x1d, 0xc6, 0xdf, 0x1c, 0xec, +- 0x53, 0x92, 0x5c, 0xaa, 0xb0, 0xfd, 0x42, 0x55, 0xcf, 0xb7, 0xde, 0xaf, +- 0xf3, 0xda, 0x2b, 0x1f, 0x3c, 0x5f, 0x9f, 0xa3, 0xf3, 0xd0, 0xe7, 0x65, +- 0x79, 0x31, 0xf8, 0x5c, 0xc6, 0xb6, 0x91, 0xed, 0xc3, 0xda, 0x24, 0x63, +- 0x69, 0x0a, 0xf3, 0xba, 0x9d, 0xf4, 0xe6, 0xbb, 0xe5, 0x93, 0xdf, 0x18, +- 0xb0, 0x3d, 0x2f, 0x3c, 0x9c, 0xa7, 0xb9, 0x54, 0xba, 0x63, 0x20, 0xd6, +- 0x21, 0xa2, 0x77, 0xc7, 0x70, 0xbe, 0x26, 0x5e, 0x14, 0x65, 0x5d, 0xdd, +- 0xc3, 0x58, 0x76, 0x9e, 0x37, 0x99, 0x77, 0x76, 0x96, 0xaf, 0xc7, 0x84, +- 0xaf, 0x4e, 0x77, 0xbd, 0xb3, 0xdf, 0x3c, 0x48, 0xc1, 0xbd, 0xfe, 0x6b, +- 0x3d, 0xd4, 0xef, 0xb2, 0xd6, 0x3d, 0xfa, 0xdc, 0x8d, 0x8a, 0x99, 0x3a, +- 0xcf, 0x40, 0xd8, 0xef, 0x7e, 0x3f, 0x16, 0x3d, 0x99, 0x16, 0x7d, 0x53, +- 0x97, 0x18, 0x65, 0xf6, 0xd5, 0x80, 0xf2, 0x29, 0xe7, 0xe6, 0xac, 0xd4, +- 0x9b, 0x9b, 0x45, 0x6b, 0x80, 0xde, 0x99, 0xfc, 0x7e, 0x2e, 0xcc, 0xe1, +- 0xb9, 0x76, 0xe3, 0x06, 0xcd, 0x7f, 0x19, 0xfe, 0x70, 0xf9, 0x5e, 0xda, +- 0x26, 0xda, 0xe6, 0xf0, 0x95, 0x4f, 0x33, 0xfd, 0x01, 0x38, 0xae, 0xdf, +- 0x97, 0xf4, 0x1c, 0x07, 0xd0, 0x9e, 0x3a, 0xe8, 0x7b, 0x99, 0xe6, 0x7d, +- 0x6d, 0x17, 0xef, 0xb5, 0x3e, 0x36, 0xc3, 0xf4, 0x9c, 0xe0, 0x3b, 0xc1, +- 0xf7, 0xcd, 0xfa, 0x54, 0xc9, 0xf7, 0x41, 0xbd, 0x9f, 0xba, 0xbe, 0x7e, +- 0xef, 0xe8, 0xaf, 0xdb, 0x07, 0xd3, 0xb3, 0x74, 0x9f, 0xfa, 0xe9, 0x99, +- 0x93, 0xd3, 0xa7, 0x7b, 0xdb, 0x3d, 0x7d, 0x32, 0xfb, 0xd5, 0xff, 0x7f, +- 0xe8, 0x36, 0xf7, 0xd3, 0x81, 0x74, 0x3d, 0x1b, 0x1b, 0xcc, 0x9f, 0xab, +- 0xa9, 0x79, 0x49, 0xdf, 0xff, 0x90, 0xf0, 0x45, 0xf9, 0x51, 0x1d, 0x5f, +- 0x6c, 0xef, 0xe8, 0x72, 0x9a, 0x7f, 0x2f, 0x0a, 0xff, 0x8d, 0x99, 0x75, +- 0xe6, 0x47, 0xfb, 0xf7, 0xdc, 0x7d, 0x4d, 0x85, 0xc8, 0x97, 0x57, 0x20, +- 0x96, 0x3c, 0xef, 0x67, 0xf2, 0xad, 0x8a, 0x2e, 0x95, 0xe1, 0x83, 0x58, +- 0xd7, 0xc5, 0x9f, 0x9b, 0x21, 0xe3, 0xfb, 0xe4, 0xef, 0xef, 0xf3, 0x2e, +- 0xf9, 0xf0, 0x5e, 0x4f, 0x7f, 0x3d, 0x8a, 0x37, 0x29, 0x3a, 0xb6, 0x20, +- 0x7a, 0xf2, 0x8b, 0xc3, 0x7a, 0xd5, 0x3e, 0x4b, 0xfc, 0x85, 0x11, 0xd1, +- 0x95, 0x76, 0x95, 0xed, 0x7a, 0x95, 0x7f, 0xef, 0x4e, 0x96, 0x5d, 0xf2, +- 0xab, 0x57, 0x19, 0x47, 0x2a, 0xb8, 0x2f, 0x80, 0x07, 0xe7, 0xc8, 0x3d, +- 0x5c, 0x75, 0xf9, 0x5d, 0x59, 0xbd, 0x23, 0x7a, 0xe7, 0xe9, 0xfe, 0x49, +- 0xbd, 0x8f, 0xe1, 0xfa, 0x88, 0xd2, 0x0f, 0xb6, 0x99, 0x17, 0x6e, 0x6f, +- 0x1e, 0xde, 0x91, 0xec, 0x9b, 0x5e, 0xba, 0xdf, 0x7a, 0x2e, 0x3b, 0xb9, +- 0x3e, 0xeb, 0x7b, 0x3a, 0x95, 0x68, 0xbd, 0x1d, 0x9b, 0xc3, 0x7c, 0x3d, +- 0xa8, 0x95, 0x99, 0x47, 0x8c, 0x2a, 0x8e, 0x51, 0xc6, 0x6d, 0x8d, 0x25, +- 0xd1, 0xaf, 0xa5, 0x45, 0x0a, 0x73, 0x6e, 0x49, 0xaf, 0xcf, 0xd2, 0xe0, +- 0xcc, 0x6f, 0x7c, 0x45, 0xeb, 0xb5, 0xb8, 0xc8, 0xeb, 0xe5, 0xb3, 0xba, +- 0x5f, 0x1e, 0xd5, 0xbf, 0xc2, 0xfd, 0x7a, 0xee, 0x26, 0xe3, 0xb3, 0xf0, +- 0x34, 0xa1, 0xb3, 0x22, 0x73, 0xbf, 0xea, 0xda, 0x84, 0x40, 0xfd, 0x32, +- 0x1e, 0xe5, 0xf7, 0xd4, 0x94, 0x77, 0x70, 0x28, 0x75, 0x8f, 0xf9, 0xf7, +- 0xea, 0xa0, 0xf7, 0x99, 0xd6, 0x6f, 0xfd, 0x9e, 0x16, 0x72, 0xbf, 0x5f, +- 0xab, 0x39, 0x7e, 0xbe, 0x34, 0x80, 0x9f, 0x87, 0x06, 0xf0, 0x3b, 0xaf, +- 0x87, 0x6d, 0x99, 0xff, 0x12, 0x98, 0x45, 0x7a, 0x08, 0xdd, 0xd2, 0x75, +- 0xba, 0x5f, 0x63, 0x89, 0x7f, 0x4f, 0xb8, 0xe6, 0x72, 0x81, 0xfa, 0xe6, +- 0x2e, 0xb3, 0x5f, 0x89, 0xd7, 0x03, 0x8d, 0xaf, 0x5d, 0xe7, 0x39, 0x33, +- 0xe0, 0x3f, 0xdd, 0xd1, 0x99, 0x07, 0x78, 0x0d, 0x00, 0x00, 0x00 }; ++ /* Date: 01/27/2009 19:01 */ ++#define XI_RV2P_PROC1_POST_WAIT_TIMEOUT_MSK 0xffff ++ 0xa5, 0x56, 0xdd, 0x6b, 0x1c, 0x55, 0x14, 0x3f, 0x33, 0xbb, 0x33, 0xb3, ++ 0xd9, 0x9d, 0xd9, 0x5d, 0x9a, 0x34, 0x8e, 0xb1, 0x34, 0xdb, 0x20, 0xca, ++ 0xa6, 0x13, 0xdd, 0x68, 0x1f, 0x04, 0x03, 0x2d, 0x01, 0x29, 0x98, 0xe2, ++ 0x43, 0xa0, 0x52, 0x8a, 0x60, 0x5c, 0xb4, 0x08, 0xf6, 0x2f, 0x10, 0xc1, ++ 0x21, 0x31, 0x11, 0xc4, 0xaf, 0x7d, 0xe8, 0x42, 0x02, 0x6a, 0x40, 0x50, ++ 0x09, 0x11, 0x77, 0xdf, 0x24, 0x16, 0x7c, 0x68, 0xf1, 0x41, 0xda, 0xa7, ++ 0x16, 0xd4, 0x97, 0x46, 0x11, 0xbf, 0x5e, 0x04, 0xd1, 0xc7, 0x9a, 0xf1, ++ 0x9e, 0x8f, 0xbb, 0x3b, 0x73, 0xb3, 0x9b, 0x14, 0x5c, 0x48, 0x7e, 0x9c, ++ 0x7b, 0xcf, 0x39, 0xf7, 0x7c, 0x9f, 0xa9, 0x02, 0x80, 0x0d, 0x71, 0x77, ++ 0x52, 0x21, 0x58, 0xb9, 0x5c, 0x01, 0x01, 0x60, 0x1b, 0xf8, 0xe7, 0xf8, ++ 0x44, 0xc7, 0x8f, 0x0a, 0x7d, 0x92, 0x21, 0x3e, 0x59, 0x55, 0xff, 0x2f, ++ 0xc3, 0xe9, 0x1a, 0x62, 0x0e, 0x4e, 0x9f, 0x40, 0x7c, 0x12, 0xbe, 0xae, ++ 0x85, 0x0a, 0xff, 0x4d, 0x20, 0x46, 0xfa, 0x68, 0xe7, 0xcb, 0x6e, 0x89, ++ 0xf4, 0xef, 0x8a, 0xfc, 0xf7, 0x39, 0xc6, 0x27, 0xa2, 0x02, 0xeb, 0x11, ++ 0x84, 0x99, 0x2a, 0xc1, 0xed, 0x16, 0xd2, 0xe7, 0xcf, 0x83, 0x8b, 0x7a, ++ 0xde, 0x53, 0x0c, 0x48, 0x1f, 0xb3, 0xe2, 0x19, 0xb1, 0xcb, 0x66, 0xbe, ++ 0x3b, 0xad, 0x0a, 0x9e, 0xc3, 0x8f, 0xf3, 0x48, 0xdf, 0x57, 0x7c, 0xa3, ++ 0x85, 0x38, 0x0e, 0x97, 0x0a, 0x3e, 0xfb, 0x53, 0x17, 0x9c, 0x64, 0xf5, ++ 0xbb, 0xd3, 0x28, 0xaf, 0x64, 0xa6, 0x45, 0xbf, 0x83, 0xfa, 0x7f, 0x4f, ++ 0x58, 0x3f, 0xea, 0x4d, 0xeb, 0xbb, 0x5f, 0xe9, 0xc3, 0x73, 0x57, 0xec, ++ 0x73, 0x0d, 0xfb, 0x5c, 0x65, 0x0f, 0xca, 0xaf, 0x00, 0xfb, 0x39, 0xaa, ++ 0xde, 0x45, 0xfa, 0xaf, 0xbe, 0xbe, 0x2e, 0xa2, 0x6f, 0xb1, 0xbc, 0xfa, ++ 0x13, 0xfb, 0x59, 0xee, 0x35, 0x25, 0xa7, 0xe3, 0x92, 0xb5, 0xd3, 0x8b, ++ 0xb4, 0x7f, 0x3a, 0xfe, 0xc8, 0x7f, 0x2b, 0xc9, 0xf2, 0xc3, 0x21, 0xfc, ++ 0x37, 0x15, 0x7f, 0x56, 0x2f, 0x9f, 0x7f, 0xdb, 0x3f, 0x1f, 0x18, 0x1f, ++ 0xc7, 0x88, 0xcf, 0x75, 0xf1, 0xe7, 0x29, 0x78, 0xd0, 0x0e, 0x89, 0x2f, ++ 0x0f, 0x21, 0xc5, 0x09, 0x62, 0xc4, 0xe3, 0x82, 0x2f, 0x09, 0x7e, 0x2e, ++ 0xb8, 0x2d, 0x08, 0xff, 0x13, 0xff, 0x1e, 0x72, 0x7e, 0x54, 0xf0, 0x01, ++ 0xe3, 0xfc, 0x9a, 0xe0, 0x23, 0x86, 0xfc, 0x71, 0x8b, 0xf1, 0x0f, 0xa1, ++ 0xe7, 0x85, 0x7e, 0xc6, 0x90, 0x8f, 0x81, 0xe3, 0x63, 0x19, 0x71, 0xfb, ++ 0x58, 0xea, 0x19, 0xf3, 0x2f, 0xf7, 0x75, 0xcd, 0x57, 0xa0, 0x38, 0xc2, ++ 0x74, 0x9a, 0xff, 0x83, 0x03, 0xf8, 0x99, 0x6d, 0xbe, 0x3e, 0x48, 0xae, ++ 0x9d, 0xb0, 0x1d, 0x57, 0x44, 0xbe, 0xd8, 0xb9, 0x3a, 0xa4, 0x7f, 0xe6, ++ 0xa2, 0x41, 0xfd, 0x52, 0x17, 0x3f, 0xbe, 0x92, 0xba, 0xdc, 0xb1, 0x9a, ++ 0x51, 0xc8, 0x79, 0xa5, 0x3c, 0x06, 0x52, 0x8f, 0x23, 0x46, 0x3d, 0x7b, ++ 0xaa, 0x9e, 0xa5, 0xae, 0xea, 0xba, 0xbe, 0xb2, 0x75, 0xc5, 0xf5, 0xe1, ++ 0x1a, 0xf5, 0x11, 0x1f, 0x12, 0x97, 0x92, 0xe1, 0xdf, 0xab, 0x09, 0x86, ++ 0x18, 0x7f, 0xb6, 0xcd, 0xb8, 0xc1, 0x18, 0xf9, 0x6e, 0x1e, 0xf1, 0x94, ++ 0xff, 0x0d, 0xeb, 0x9b, 0x04, 0x44, 0x3f, 0x6c, 0x53, 0x1f, 0xe5, 0xa1, ++ 0xed, 0x2a, 0x9b, 0xe1, 0x6e, 0xf2, 0x0e, 0xf3, 0x4d, 0x38, 0x37, 0x09, ++ 0xc3, 0x8d, 0x1b, 0xcc, 0xff, 0x5d, 0x8d, 0xed, 0x7e, 0x56, 0xe6, 0x53, ++ 0xff, 0xa7, 0xef, 0xa5, 0xff, 0x2a, 0x48, 0xff, 0x63, 0xc5, 0x5d, 0xfd, ++ 0x8e, 0xc8, 0xbd, 0xa2, 0xeb, 0x9b, 0x7f, 0xcb, 0x6e, 0x95, 0xfc, 0x7d, ++ 0xab, 0x4b, 0xe4, 0x98, 0xbf, 0x56, 0xa5, 0xdb, 0xb7, 0xbb, 0xda, 0x1f, ++ 0xe9, 0xf3, 0x69, 0xed, 0x3f, 0xcb, 0x07, 0x72, 0x6d, 0x3b, 0x3a, 0x7e, ++ 0x7c, 0x5e, 0x24, 0x3b, 0x46, 0x3b, 0x9b, 0x46, 0x3e, 0x6b, 0xf7, 0x34, ++ 0x07, 0xff, 0x4c, 0xfa, 0x73, 0x30, 0x1d, 0x1f, 0x3d, 0x07, 0x0b, 0xb0, ++ 0x74, 0xb6, 0x42, 0xf6, 0x94, 0x5d, 0x56, 0x73, 0xa1, 0xc2, 0xf8, 0x62, ++ 0x91, 0xf1, 0x97, 0x22, 0xc6, 0x2f, 0x49, 0x2e, 0x95, 0x98, 0x7e, 0x21, ++ 0x40, 0xbd, 0xa3, 0xea, 0x61, 0x2d, 0xaf, 0xed, 0x3a, 0xc8, 0x1e, 0x7c, ++ 0x5f, 0xbf, 0xa3, 0xed, 0xd0, 0xef, 0x65, 0xeb, 0x65, 0xf8, 0xbb, 0x8c, ++ 0x4d, 0x3b, 0x1b, 0x87, 0xfc, 0x2c, 0xe3, 0x46, 0x03, 0xed, 0xba, 0x9a, ++ 0xf4, 0xfa, 0xb0, 0x5e, 0x25, 0xbe, 0x29, 0x60, 0x7a, 0x51, 0xea, 0x73, ++ 0x91, 0xfa, 0xa7, 0xac, 0xae, 0x10, 0x27, 0x20, 0xa6, 0xbd, 0x60, 0x17, ++ 0xaf, 0x53, 0xbd, 0xe4, 0xe4, 0x5c, 0xe5, 0x67, 0x2a, 0xdb, 0x77, 0xbb, ++ 0x5c, 0x8f, 0x85, 0x6c, 0x1d, 0x3f, 0x9c, 0x9a, 0xaf, 0x69, 0x7f, 0xad, ++ 0x5e, 0xfd, 0xee, 0xcf, 0x53, 0x36, 0x1f, 0xb7, 0x5b, 0xda, 0x7f, 0x73, ++ 0x6f, 0x30, 0x7b, 0xdc, 0x90, 0x40, 0xcd, 0xca, 0xfd, 0x8c, 0xd9, 0x2f, ++ 0x83, 0xfa, 0xad, 0x6a, 0xf4, 0xcf, 0x11, 0xe9, 0xb7, 0x91, 0xce, 0x66, ++ 0xeb, 0xb0, 0x7e, 0x46, 0xfe, 0x2f, 0x64, 0x9e, 0x54, 0xa1, 0xb7, 0x97, ++ 0xb6, 0x91, 0x2e, 0x81, 0xf4, 0x61, 0x27, 0xce, 0x65, 0xf2, 0x70, 0x06, ++ 0x06, 0xce, 0x95, 0x0f, 0x45, 0x4f, 0x43, 0xe6, 0x8b, 0x9b, 0xda, 0x5f, ++ 0xc4, 0x5e, 0x06, 0xb2, 0xc3, 0x33, 0xe6, 0xc3, 0xdd, 0x3d, 0xdd, 0xef, ++ 0xcb, 0xee, 0x20, 0x7f, 0x3d, 0xf8, 0xcd, 0xe7, 0xfa, 0x68, 0x52, 0xbf, ++ 0x38, 0x63, 0x97, 0x77, 0x32, 0x79, 0x02, 0x38, 0xa1, 0xf7, 0x52, 0xda, ++ 0xae, 0xf4, 0x5e, 0x45, 0x7d, 0x21, 0x34, 0x67, 0xd3, 0xfb, 0xf5, 0xfd, ++ 0x44, 0xcf, 0xf5, 0x80, 0xfa, 0xa4, 0xbc, 0xaf, 0xef, 0xf4, 0x1c, 0xad, ++ 0x45, 0xe9, 0xfe, 0x1d, 0x93, 0xb9, 0x69, 0x03, 0xcf, 0xcd, 0x92, 0xe9, ++ 0xa7, 0xda, 0xb7, 0x83, 0xf3, 0xc5, 0xfe, 0xde, 0xd9, 0xbb, 0xb7, 0x39, ++ 0x7b, 0x58, 0xde, 0x8b, 0x46, 0xde, 0x6f, 0xf5, 0xe2, 0x68, 0x3b, 0x83, ++ 0xbe, 0x2b, 0x4e, 0x29, 0xbd, 0xc2, 0x2f, 0x73, 0xe1, 0x79, 0x9a, 0x77, ++ 0x67, 0x84, 0x6f, 0x2e, 0x55, 0xaf, 0x83, 0xf8, 0x62, 0xa3, 0xae, 0x0b, ++ 0xfb, 0xf8, 0xb2, 0x73, 0x4c, 0xfb, 0xb3, 0xb5, 0xc5, 0xf5, 0x71, 0x31, ++ 0xd5, 0xaf, 0xe9, 0xf9, 0x3f, 0x22, 0xf5, 0xa0, 0xf8, 0xc8, 0x8f, 0x9d, ++ 0xbd, 0xfe, 0xbe, 0x48, 0xd7, 0xd7, 0xa2, 0xd4, 0xb5, 0x3d, 0xb7, 0x49, ++ 0x7d, 0xe4, 0x35, 0x7f, 0x35, 0xf2, 0x35, 0x1b, 0x61, 0x9d, 0xbc, 0x0e, ++ 0x5d, 0xb1, 0xf3, 0x87, 0x8c, 0xbd, 0x81, 0xf4, 0xa1, 0x0b, 0x9f, 0x75, ++ 0xb5, 0x5f, 0x7c, 0x5d, 0x8b, 0x18, 0x3f, 0x8d, 0xa4, 0x9f, 0x7a, 0xfe, ++ 0xe1, 0xbb, 0x0b, 0xf2, 0x6e, 0x15, 0x3e, 0xe9, 0xed, 0x03, 0x9c, 0x6f, ++ 0x1e, 0x34, 0x64, 0x7e, 0x2e, 0xc9, 0x1c, 0xfb, 0xa9, 0xc8, 0x73, 0xb2, ++ 0xb9, 0x40, 0xf5, 0x0a, 0xe3, 0x32, 0xcf, 0x9a, 0x01, 0xd3, 0x13, 0x01, ++ 0x7f, 0x07, 0x37, 0x3c, 0x9f, 0xf8, 0x26, 0x02, 0xc6, 0xf1, 0x12, 0xca, ++ 0x85, 0xf0, 0xf3, 0x39, 0x62, 0x8f, 0xd6, 0x7d, 0xde, 0x73, 0xeb, 0x37, ++ 0x64, 0x9e, 0x54, 0x74, 0xdc, 0xc4, 0xcf, 0xc7, 0xf1, 0x7c, 0x5c, 0xcd, ++ 0x2d, 0xa6, 0xb9, 0x1e, 0xfc, 0x5e, 0xfd, 0x7f, 0x24, 0x59, 0xa9, 0x55, ++ 0xd2, 0x71, 0xd6, 0xfd, 0xf6, 0xae, 0x11, 0x5f, 0x9d, 0x9f, 0x87, 0x12, ++ 0x3d, 0xe7, 0xa7, 0xce, 0xa2, 0xbd, 0x15, 0x28, 0x7b, 0x5c, 0x3f, 0x8c, ++ 0x4a, 0x8f, 0xed, 0xa1, 0xd8, 0xb1, 0x55, 0x99, 0x9b, 0xab, 0xcb, 0xa4, ++ 0xe6, 0xdc, 0xaa, 0x3e, 0x9f, 0xa7, 0x86, 0x59, 0xdc, 0xba, 0x46, 0xe7, ++ 0xe5, 0x6e, 0x8e, 0xcf, 0xbd, 0x05, 0x1d, 0xaf, 0x0a, 0xf9, 0xdf, 0xe6, ++ 0x78, 0x3d, 0x77, 0x85, 0xf1, 0x22, 0x3c, 0x4d, 0x58, 0x6c, 0x4b, 0x9f, ++ 0xaf, 0xfb, 0x05, 0x42, 0xa0, 0x78, 0xd9, 0x8f, 0xf1, 0x7e, 0x77, 0x64, ++ 0x2f, 0x17, 0x52, 0xf9, 0x33, 0xf7, 0xe4, 0x41, 0x79, 0x3c, 0x62, 0xec, ++ 0x0b, 0xbd, 0xd7, 0x2d, 0xe3, 0xfb, 0x36, 0x30, 0xea, 0xf1, 0xe5, 0x21, ++ 0xf5, 0x08, 0x43, 0xea, 0xd9, 0x9c, 0x6f, 0x4b, 0xd2, 0xef, 0x79, 0x70, ++ 0x72, 0xb4, 0x78, 0xfd, 0xfc, 0x0a, 0xe5, 0xd5, 0x5e, 0xe5, 0xef, 0x1a, ++ 0xdf, 0x59, 0xb3, 0x28, 0x5e, 0xfe, 0x1a, 0xf3, 0xe5, 0xf9, 0x3c, 0xd4, ++ 0xf8, 0xe6, 0x0a, 0xf7, 0x95, 0x0d, 0xff, 0x01, 0xd7, 0x0e, 0x41, 0x60, ++ 0x88, 0x0d, 0x00, 0x00, 0x00 }; + + static u8 bnx2_xi_rv2p_proc2[] = { +- /* Date: 06/17/2008 16:52 */ ++ /* Date: 01/27/2009 19:01 */ + #define XI_RV2P_PROC2_MAX_BD_PAGE_LOC 5 + #define XI_RV2P_PROC2_BD_PAGE_SIZE_MSK 0xffff + #define XI_RV2P_PROC2_BD_PAGE_SIZE ((BCM_PAGE_SIZE / 16) - 1) +- 0xad, 0x58, 0x4d, 0x4c, 0x54, 0x57, 0x14, 0xbe, 0xf3, 0xc3, 0xcc, 0x30, +- 0xbc, 0x99, 0x41, 0x98, 0x0e, 0x7f, 0xa6, 0x22, 0x28, 0x82, 0x1d, 0x14, +- 0x06, 0xd4, 0xb6, 0x36, 0xa9, 0xc1, 0x06, 0xb5, 0xb5, 0x11, 0x69, 0x63, +- 0xba, 0x68, 0x8a, 0x60, 0x45, 0x06, 0xc1, 0x10, 0x31, 0x2e, 0xdc, 0x74, +- 0x02, 0x16, 0xbb, 0x98, 0x85, 0x98, 0xe2, 0x60, 0xd3, 0x18, 0x52, 0x37, +- 0xa6, 0x3b, 0x92, 0xb6, 0x62, 0xbb, 0x30, 0x31, 0x2d, 0xb1, 0xb6, 0x89, +- 0x36, 0xb1, 0x7f, 0x9b, 0xa6, 0xa6, 0x5a, 0x8a, 0x4a, 0x2d, 0xda, 0xb2, +- 0xaa, 0xd0, 0x77, 0xcf, 0x77, 0xee, 0x9b, 0x37, 0x33, 0x6f, 0x44, 0x53, +- 0xd9, 0x1c, 0xee, 0x7d, 0xe7, 0x9e, 0x7b, 0xce, 0x77, 0x7e, 0xef, 0xe4, +- 0x0b, 0x21, 0x9c, 0x22, 0x36, 0xbe, 0x4c, 0xa7, 0x62, 0x89, 0xdd, 0xe1, +- 0xd1, 0xc9, 0x82, 0x10, 0x39, 0xc5, 0x72, 0x2d, 0xec, 0x82, 0xff, 0x56, +- 0xe7, 0x13, 0xb9, 0x36, 0x2e, 0xbf, 0xbb, 0xc5, 0xeb, 0x76, 0x7c, 0x77, +- 0x0a, 0x49, 0x03, 0x42, 0xc4, 0x24, 0xcd, 0x67, 0xba, 0x9d, 0xe9, 0x4a, +- 0x1b, 0xe8, 0x46, 0xa6, 0x51, 0xa6, 0x2b, 0x98, 0xd6, 0xdb, 0x41, 0x57, +- 0x31, 0xad, 0xe6, 0x7d, 0x8d, 0xcf, 0xd7, 0xf2, 0xfe, 0x7b, 0x4c, 0x8f, +- 0xf2, 0xbe, 0xa6, 0xf3, 0x29, 0xbd, 0xe4, 0x7a, 0x66, 0x41, 0xc4, 0xf4, +- 0x33, 0x42, 0xdf, 0xae, 0x51, 0xfb, 0x1a, 0x91, 0x58, 0x0d, 0xf4, 0x7e, +- 0xad, 0x5c, 0xf2, 0xfd, 0x61, 0xc1, 0x27, 0xf7, 0x6f, 0x2e, 0x28, 0x79, +- 0x03, 0x0e, 0xb9, 0xfe, 0x55, 0x5f, 0xdb, 0xe4, 0x32, 0x18, 0x82, 0x98, +- 0x60, 0x71, 0x5c, 0xca, 0x71, 0x88, 0xd1, 0x61, 0x0f, 0xa1, 0x72, 0x52, +- 0xc3, 0x3a, 0x46, 0x78, 0xd8, 0xf4, 0x35, 0xcb, 0x63, 0x5a, 0xe2, 0xc3, +- 0xbd, 0xbb, 0xca, 0x71, 0xdf, 0x8f, 0xcf, 0x80, 0x2f, 0x16, 0x50, 0x80, +- 0xe2, 0xfb, 0x32, 0xc1, 0xdf, 0xf7, 0xcb, 0xf5, 0xac, 0xad, 0xd0, 0x06, +- 0x5c, 0xdd, 0xcc, 0x65, 0xcf, 0x91, 0xfb, 0xcb, 0x1b, 0x4f, 0x0e, 0x83, +- 0xbf, 0xad, 0x1c, 0xfb, 0x4f, 0x87, 0xa5, 0x3c, 0x97, 0x88, 0x31, 0x15, +- 0xb5, 0xa4, 0x97, 0x2d, 0x56, 0x9b, 0x2a, 0xff, 0x97, 0x61, 0xac, 0xda, +- 0x7d, 0x90, 0xeb, 0x4d, 0x91, 0x1b, 0xca, 0x90, 0xfb, 0x53, 0xae, 0x59, +- 0xbe, 0xdf, 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0x4a, 0xd5, 0xa3, 0xcc, +- 0xa4, 0x87, 0xba, 0x77, 0xb1, 0x39, 0x01, 0x73, 0xea, 0x16, 0x9a, 0x13, +- 0x3c, 0xc6, 0xbc, 0x9d, 0xda, 0x4f, 0x26, 0x1f, 0x3c, 0x6e, 0x3f, 0xd9, +- 0xd9, 0x60, 0xbe, 0xaf, 0x46, 0x4c, 0x8e, 0xe3, 0x9e, 0x16, 0xee, 0xdf, +- 0xbb, 0x39, 0xcf, 0xaf, 0x7b, 0x03, 0x74, 0x6f, 0xc7, 0x2b, 0x64, 0xaf, +- 0x08, 0xe5, 0xc1, 0xbe, 0x8e, 0xed, 0xf8, 0xde, 0xe1, 0xc3, 0x7e, 0xa9, +- 0x0f, 0xbf, 0xa3, 0xb4, 0xb8, 0x35, 0xe2, 0x2f, 0xf5, 0x81, 0x86, 0xb8, +- 0x3e, 0x4c, 0x1a, 0xef, 0x09, 0xd0, 0x51, 0x57, 0xb6, 0xf7, 0x04, 0xde, +- 0x65, 0x17, 0x5d, 0xa8, 0x1f, 0xa2, 0x06, 0x73, 0x74, 0x53, 0x95, 0x46, +- 0xdf, 0x5b, 0x6b, 0xd0, 0xa7, 0x51, 0x9f, 0x33, 0xed, 0x2a, 0x43, 0xbc, +- 0x96, 0x26, 0xdf, 0x1d, 0xe6, 0xf7, 0x89, 0x16, 0x49, 0x18, 0xf3, 0x7f, +- 0xaa, 0x1e, 0xc8, 0x33, 0x29, 0x9f, 0x96, 0xfa, 0x9c, 0xfd, 0x28, 0xef, +- 0x12, 0x07, 0xcf, 0x6d, 0x77, 0xf9, 0x77, 0x82, 0x42, 0x71, 0x69, 0x1c, +- 0x38, 0x4c, 0x8e, 0x5b, 0xe5, 0xb1, 0xd4, 0x43, 0xdd, 0x03, 0xbb, 0x94, +- 0x9d, 0xc9, 0x7b, 0xa1, 0xd7, 0x5e, 0xd6, 0xff, 0x06, 0xfd, 0x9e, 0x11, +- 0x62, 0x7b, 0xa5, 0x5c, 0xec, 0x6f, 0xa5, 0xf7, 0x53, 0x8e, 0x88, 0x19, +- 0xeb, 0xd4, 0x77, 0x4d, 0x0b, 0xe9, 0x55, 0xc0, 0xfd, 0x3d, 0x64, 0x9a, +- 0x43, 0xc0, 0x1f, 0xac, 0x03, 0x1d, 0xa9, 0x53, 0x7e, 0x53, 0xfe, 0x55, +- 0xfe, 0x84, 0xdf, 0x43, 0xf5, 0xc4, 0xd6, 0xd8, 0x51, 0x4f, 0x09, 0x5f, +- 0xd7, 0x31, 0xab, 0xfa, 0x3d, 0xce, 0xef, 0x0c, 0x4b, 0xfe, 0x77, 0xc4, +- 0x77, 0x61, 0x34, 0xd8, 0x9f, 0x99, 0x26, 0xe7, 0x7c, 0xc1, 0x7f, 0xe6, +- 0xf7, 0x82, 0x43, 0x5c, 0xcc, 0xe1, 0xed, 0x06, 0x35, 0xff, 0x66, 0x7b, +- 0xf7, 0x48, 0x3b, 0xba, 0x1f, 0xa4, 0xcf, 0xd3, 0xc9, 0x79, 0x58, 0xd9, +- 0x2b, 0xcf, 0xd5, 0x71, 0x1c, 0x7b, 0x44, 0xd3, 0x16, 0xfc, 0xce, 0xe1, +- 0x77, 0x23, 0x6f, 0xfc, 0x6e, 0xab, 0xf7, 0xa9, 0x1e, 0x47, 0xb9, 0x54, +- 0x30, 0x96, 0x16, 0xe4, 0x92, 0x7d, 0x27, 0x2e, 0x7f, 0x43, 0x6c, 0x1f, +- 0x25, 0xf2, 0xb0, 0x5f, 0xd4, 0x84, 0x6b, 0x9c, 0x14, 0xf7, 0x0e, 0x71, +- 0x14, 0x79, 0xf1, 0xe1, 0x08, 0xe8, 0x07, 0xe2, 0x65, 0xc8, 0x29, 0x18, +- 0xa0, 0xbe, 0xea, 0x29, 0x02, 0xcc, 0xf1, 0x04, 0xc7, 0x7b, 0xb1, 0x9d, +- 0x7e, 0x87, 0x5d, 0x10, 0x3e, 0xfe, 0x9d, 0x8c, 0xf3, 0x17, 0x71, 0xed, +- 0x34, 0xf9, 0xff, 0x51, 0xe3, 0x1c, 0xfd, 0x33, 0xc1, 0x7e, 0xe7, 0x78, +- 0xf7, 0xa4, 0xc7, 0xbb, 0xc2, 0xa9, 0xd8, 0x6e, 0x19, 0xdf, 0xeb, 0x33, +- 0xe3, 0x5b, 0xe9, 0x97, 0xda, 0x3f, 0x33, 0xe5, 0xe3, 0x1d, 0x75, 0xe9, +- 0x89, 0xc5, 0x37, 0xe8, 0xd6, 0x4a, 0x79, 0x7f, 0x51, 0xc6, 0xbc, 0x9c, +- 0x9e, 0x7f, 0xa8, 0x77, 0xd5, 0x7a, 0x3c, 0xfc, 0x07, 0xd7, 0x0d, 0x36, +- 0x4f, 0xf0, 0x16, 0x00, 0x00, 0x00 }; ++ 0xad, 0x57, 0x4d, 0x68, 0x5c, 0x55, 0x14, 0xbe, 0x33, 0x6f, 0x7e, 0xde, ++ 0xcc, 0xbc, 0xc9, 0x4c, 0x93, 0x38, 0x99, 0x26, 0xc5, 0xa4, 0x09, 0x8d, ++ 0x4e, 0x9d, 0x69, 0x27, 0x3f, 0x44, 0xb0, 0x42, 0x43, 0x90, 0xb4, 0xb5, ++ 0x4a, 0xd3, 0x28, 0xc5, 0x5d, 0x92, 0xa9, 0x1d, 0x8c, 0x69, 0x23, 0x18, ++ 0x70, 0xe1, 0xc6, 0x47, 0x5a, 0xd3, 0xcd, 0x2c, 0x4c, 0x31, 0x3f, 0x8a, ++ 0xa0, 0xd8, 0x9d, 0xb8, 0x19, 0x50, 0xdb, 0x8a, 0x22, 0x14, 0x0c, 0x52, ++ 0x17, 0x45, 0xb0, 0x58, 0x37, 0x8a, 0x58, 0x1b, 0x1a, 0x11, 0x8d, 0x8b, ++ 0xae, 0x24, 0xe3, 0xbd, 0xe7, 0x3b, 0xf7, 0xcd, 0xbc, 0xc9, 0x8b, 0x89, ++ 0x62, 0x36, 0x27, 0xe7, 0xbe, 0x73, 0xcf, 0x39, 0xf7, 0x9c, 0xef, 0x7c, ++ 0xf7, 0x4e, 0x52, 0x08, 0x11, 0x10, 0x76, 0xb9, 0x5d, 0x4a, 0xe1, 0x33, ++ 0x0c, 0x53, 0x8a, 0x8a, 0x10, 0xc1, 0xb4, 0xd2, 0x85, 0x5f, 0xf0, 0xdf, ++ 0xfe, 0x24, 0x89, 0x6f, 0xcb, 0x96, 0x32, 0x13, 0x76, 0x46, 0xd9, 0x45, ++ 0xc4, 0xb3, 0xfe, 0x88, 0x94, 0x87, 0xc5, 0x68, 0x06, 0xf6, 0x01, 0xa1, ++ 0xa4, 0xb4, 0xb5, 0x95, 0xdc, 0xc5, 0xf2, 0x38, 0xcb, 0xc7, 0x7d, 0x90, ++ 0x87, 0x58, 0x3e, 0x56, 0x27, 0x05, 0xdb, 0x3d, 0xcd, 0xfa, 0x00, 0x4b, ++ 0x8b, 0xd7, 0x47, 0x59, 0xff, 0x90, 0xa5, 0xcd, 0xeb, 0x61, 0xd6, 0x1f, ++ 0xf0, 0xa9, 0x25, 0xe4, 0xab, 0xf4, 0xb5, 0x4a, 0x55, 0xb7, 0xe0, 0x3e, ++ 0x83, 0x73, 0x3c, 0xd3, 0xa1, 0xbe, 0xdf, 0xad, 0xb8, 0xed, 0xef, 0x38, ++ 0xfa, 0xac, 0xa1, 0xf4, 0x1f, 0xa5, 0xee, 0x53, 0x6a, 0x73, 0x0a, 0xdb, ++ 0x9b, 0xd3, 0x25, 0xb5, 0xdf, 0x10, 0xcb, 0xf3, 0x26, 0x55, 0x67, 0xd1, ++ 0x82, 0x6e, 0x97, 0x4d, 0xaa, 0xcb, 0xa2, 0xc5, 0xfe, 0x58, 0xee, 0x8e, ++ 0x23, 0xde, 0xa9, 0x0e, 0xd4, 0xed, 0xbb, 0x47, 0x60, 0x67, 0x27, 0x74, ++ 0x61, 0xf1, 0xbd, 0x5d, 0xf0, 0xf7, 0x29, 0xa5, 0xaf, 0xfb, 0x9a, 0x7c, ++ 0xa8, 0x47, 0x98, 0xad, 0xfc, 0x41, 0xb5, 0xbe, 0xb7, 0x7f, 0x71, 0x1e, ++ 0xf6, 0x63, 0x1d, 0x58, 0x7f, 0x30, 0xab, 0xfc, 0x85, 0x84, 0xcd, 0x52, ++ 0xe4, 0x28, 0x2f, 0x9f, 0x9d, 0x73, 0xfb, 0xff, 0x61, 0x1e, 0xda, 0x44, ++ 0x1c, 0x7e, 0xa3, 0x2e, 0xbf, 0xa9, 0x4d, 0x7e, 0x6f, 0x47, 0x6a, 0xfd, ++ 0x37, 0xf8, 0xe0, 0x3f, 0xba, 0xad, 0xff, 0x42, 0x1c, 0xb2, 0x29, 0xeb, ++ 0x15, 0x27, 0xb2, 0x4d, 0xfe, 0x2f, 0x6e, 0xeb, 0xff, 0x55, 0x27, 0x7f, ++ 0xbd, 0x5e, 0x5f, 0x3f, 0x52, 0x3f, 0xb0, 0x0f, 0xf2, 0xf6, 0xfd, 0xfa, ++ 0xdc, 0x9c, 0x9f, 0x01, 0x39, 0x98, 0x25, 0x51, 0x3a, 0xcd, 0x00, 0x1f, ++ 0xee, 0x56, 0x71, 0x1b, 0x45, 0xc0, 0xaf, 0xfc, 0x1d, 0x30, 0x43, 0xd7, ++ 0xb0, 0xfe, 0x1c, 0xf7, 0xe9, 0x79, 0x3e, 0xc8, 0x2f, 0x51, 0x55, 0x98, ++ 0x4a, 0xa5, 0x18, 0x63, 0xff, 0xdc, 0x67, 0x3b, 0x86, 0xfd, 0x2b, 0x96, ++ 0xca, 0xef, 0x86, 0xc4, 0x8d, 0x57, 0xdf, 0x8d, 0x7f, 0xe8, 0x3b, 0xf6, ++ 0xef, 0x7a, 0x08, 0x5f, 0xdf, 0x28, 0x42, 0x6f, 0xbb, 0x9c, 0xa4, 0xfa, ++ 0x2c, 0x97, 0xbd, 0x70, 0x52, 0xef, 0x5f, 0xce, 0x71, 0x02, 0x71, 0x44, ++ 0xa7, 0x49, 0xc9, 0xa1, 0xae, 0xd2, 0x26, 0xe7, 0x59, 0x27, 0xb1, 0xb8, ++ 0x4f, 0xcf, 0x05, 0xf4, 0x62, 0x88, 0x44, 0x7a, 0x62, 0x4e, 0x9d, 0x33, ++ 0x21, 0xc6, 0xfd, 0x2a, 0x61, 0x3f, 0xd7, 0xc5, 0x30, 0xad, 0x4f, 0x60, ++ 0xff, 0x45, 0xbb, 0x45, 0x67, 0x28, 0xf6, 0x61, 0x5f, 0x73, 0x2f, 0xe4, ++ 0x42, 0x6f, 0x50, 0x89, 0x6c, 0x71, 0x86, 0xd4, 0x03, 0x3f, 0xf7, 0x98, ++ 0x64, 0x67, 0xe7, 0xf4, 0xdc, 0xe9, 0xbe, 0xa9, 0x3a, 0xbd, 0x52, 0x9d, ++ 0xbf, 0x2e, 0xd4, 0xf5, 0xee, 0x3e, 0x65, 0x2f, 0x8b, 0xdb, 0x89, 0x38, ++ 0xa3, 0x93, 0x5e, 0x73, 0xfb, 0x92, 0x53, 0xdf, 0x9d, 0xf6, 0x7f, 0x90, ++ 0xea, 0x30, 0xc8, 0xf5, 0xe8, 0x60, 0x9c, 0xed, 0xf1, 0xc0, 0x59, 0x82, ++ 0xfe, 0x5f, 0x1b, 0x4a, 0x52, 0x3d, 0x4f, 0x60, 0xfd, 0xd2, 0xf0, 0x15, ++ 0xf4, 0xe3, 0x18, 0xd5, 0x41, 0x44, 0x2f, 0x7c, 0x8c, 0x5d, 0x13, 0x34, ++ 0xdf, 0xe7, 0xfa, 0x8b, 0x9f, 0x42, 0x2f, 0x18, 0x4a, 0x9f, 0xb2, 0x4e, ++ 0x5f, 0x85, 0x7d, 0xf0, 0x7c, 0x92, 0xea, 0x77, 0x82, 0xa3, 0x1c, 0x33, ++ 0x88, 0x4f, 0x4a, 0xa1, 0xf3, 0xa4, 0x5a, 0x2b, 0xf4, 0x3d, 0x29, 0x2e, ++ 0x96, 0xf1, 0x7d, 0x3a, 0xa6, 0xce, 0x37, 0xe2, 0xf0, 0xce, 0x64, 0x08, ++ 0xfb, 0x4b, 0xf3, 0xe0, 0x8d, 0x7b, 0x1f, 0x29, 0x7d, 0x2c, 0x7b, 0x0f, ++ 0xf6, 0xd9, 0xc9, 0x39, 0x76, 0xec, 0x47, 0xfd, 0xd6, 0xfc, 0xb0, 0x67, ++ 0x58, 0x46, 0x03, 0xd4, 0x3f, 0x9f, 0xb0, 0x86, 0x21, 0x5f, 0xa7, 0xef, ++ 0x7f, 0xf9, 0x4a, 0x54, 0xb7, 0x53, 0x0d, 0x81, 0x2b, 0xba, 0x3e, 0x2c, ++ 0x13, 0xfa, 0x5c, 0x90, 0x3b, 0xc5, 0xfd, 0x9c, 0xb5, 0x15, 0xde, 0xb9, ++ 0x8f, 0x99, 0xed, 0xf0, 0x0e, 0x39, 0xdc, 0x0d, 0x19, 0xea, 0x22, 0xbe, ++ 0xf8, 0x17, 0xb8, 0xe7, 0xbc, 0x36, 0xcd, 0x15, 0x56, 0xab, 0xf8, 0x24, ++ 0x21, 0x71, 0xe9, 0xc2, 0xa9, 0x9c, 0x03, 0xe2, 0x57, 0xd9, 0x07, 0x8d, ++ 0x37, 0xe5, 0x30, 0x2c, 0xa6, 0xd8, 0xef, 0x24, 0xd7, 0xe3, 0x2c, 0xd7, ++ 0xe3, 0x37, 0x96, 0xd3, 0x31, 0x5d, 0x07, 0xc8, 0x8b, 0x34, 0xff, 0x69, ++ 0x8f, 0x7b, 0x43, 0xdf, 0x0f, 0xe8, 0xcf, 0x32, 0xf7, 0xf3, 0x2d, 0xe7, ++ 0x9e, 0xd0, 0x75, 0xdd, 0xea, 0xbe, 0xd0, 0xf8, 0xc7, 0xfa, 0xe8, 0xa4, ++ 0xe7, 0x39, 0x4b, 0x5f, 0x76, 0xc2, 0x4d, 0x63, 0x17, 0xa4, 0x53, 0xdf, ++ 0x6e, 0x9a, 0xdf, 0x86, 0x96, 0xab, 0xfa, 0x7c, 0x2a, 0xcf, 0x5f, 0xf5, ++ 0xfc, 0x35, 0x2c, 0xcd, 0x92, 0x8c, 0x36, 0x5e, 0x56, 0xf1, 0x5a, 0x3d, ++ 0xf8, 0xc3, 0x3d, 0xc7, 0xf5, 0xf5, 0x9d, 0x8e, 0x13, 0xb1, 0xf6, 0xdf, ++ 0x5c, 0x75, 0xcf, 0x2b, 0xe6, 0x33, 0xec, 0xe0, 0xbb, 0x79, 0x80, 0xfb, ++ 0xc0, 0x32, 0xf5, 0xa8, 0xf2, 0x3b, 0xc2, 0x71, 0xf2, 0x1c, 0xc7, 0xaa, ++ 0xe1, 0x0b, 0x95, 0xe7, 0xfa, 0x86, 0xe6, 0x09, 0x8d, 0x8f, 0x2a, 0x5f, ++ 0xe8, 0x3e, 0x50, 0xfc, 0xec, 0xcd, 0x55, 0xb5, 0xbf, 0x6d, 0x1b, 0xfe, ++ 0x58, 0x75, 0xfc, 0xdd, 0x72, 0x78, 0x22, 0x49, 0x71, 0x0f, 0xb3, 0xea, ++ 0xe6, 0xc1, 0x3f, 0x24, 0x0f, 0xaa, 0xef, 0xa6, 0x69, 0x39, 0xf3, 0xc2, ++ 0xfc, 0x37, 0xa3, 0xe2, 0xa5, 0x39, 0xff, 0xb4, 0xbe, 0xbf, 0x64, 0xfe, ++ 0xcc, 0x93, 0x63, 0xb5, 0x7c, 0x77, 0xdb, 0x23, 0xee, 0x7f, 0xf5, 0xc7, ++ 0xf3, 0x95, 0x65, 0xbe, 0xcf, 0x51, 0x9e, 0x95, 0xf1, 0x3c, 0xe3, 0x25, ++ 0x57, 0xdf, 0x07, 0xf4, 0x15, 0xf6, 0xb2, 0xbf, 0x9a, 0xf7, 0xfa, 0xb4, ++ 0x7f, 0xa8, 0x76, 0x4f, 0xad, 0x7d, 0x7d, 0xff, 0x03, 0x5b, 0xf0, 0xf8, ++ 0xe7, 0x1b, 0x78, 0x7f, 0x7d, 0xb6, 0x51, 0x7d, 0x4f, 0x79, 0xe2, 0xc4, ++ 0x16, 0x74, 0x3f, 0x85, 0x25, 0x9e, 0xe9, 0xbd, 0x26, 0xb4, 0xbd, 0x3f, ++ 0x88, 0xf7, 0xa4, 0x60, 0xfc, 0x9e, 0x7b, 0x98, 0xfd, 0x64, 0xc0, 0xc7, ++ 0x2f, 0x9c, 0xa1, 0xfe, 0xbe, 0x79, 0xf6, 0x3e, 0xf1, 0xf2, 0x7b, 0x2f, ++ 0x5f, 0x53, 0x7e, 0x77, 0x8b, 0xd5, 0x19, 0x8b, 0xf2, 0x1a, 0xda, 0x0b, ++ 0xf3, 0xfb, 0x87, 0xea, 0xfb, 0xad, 0xfc, 0x9a, 0x8c, 0x07, 0x69, 0x37, ++ 0xe1, 0x7e, 0x97, 0x6c, 0xce, 0x13, 0x73, 0x7f, 0x24, 0x81, 0x7d, 0x9a, ++ 0xbf, 0xdc, 0xf8, 0x79, 0x77, 0xa3, 0x7a, 0xff, 0xc0, 0xcd, 0xad, 0x83, ++ 0xde, 0x73, 0x71, 0xb2, 0xaf, 0x36, 0x4e, 0x46, 0xac, 0x94, 0xe1, 0x7f, ++ 0x84, 0x79, 0x65, 0x9c, 0x13, 0xf9, 0x29, 0x9a, 0xa0, 0x78, 0x85, 0xe3, ++ 0x84, 0x6b, 0x91, 0x8a, 0xe1, 0xdc, 0x85, 0xa7, 0xf0, 0xbd, 0x10, 0xc7, ++ 0x7a, 0x6b, 0x1c, 0xef, 0xcd, 0x91, 0xb0, 0x45, 0xf6, 0xad, 0x71, 0xc8, ++ 0x14, 0xf3, 0xcf, 0x8a, 0xc3, 0xcb, 0x90, 0xcb, 0xa1, 0xad, 0x78, 0x19, ++ 0xf7, 0xdb, 0xf5, 0x90, 0x5a, 0x97, 0x8f, 0xa0, 0x0c, 0x78, 0x69, 0xa8, ++ 0xdb, 0xa2, 0xef, 0xa3, 0x19, 0xe0, 0x48, 0x74, 0x7a, 0x9f, 0xab, 0x0d, ++ 0xfc, 0xd2, 0x5a, 0xe5, 0xef, 0x5a, 0x9e, 0xb7, 0x7a, 0x97, 0x1c, 0x1e, ++ 0x75, 0xe7, 0x01, 0xfe, 0x52, 0xfe, 0x49, 0x95, 0x7c, 0xb5, 0x13, 0x7e, ++ 0x37, 0x18, 0x2f, 0xbf, 0xf3, 0xbd, 0xdf, 0x24, 0xbe, 0x2a, 0xa3, 0x0e, ++ 0x2b, 0xe5, 0xfa, 0xfe, 0xe8, 0x3c, 0x74, 0x1c, 0x9c, 0x4b, 0x9f, 0xb3, ++ 0x1a, 0x17, 0x79, 0x9d, 0xe1, 0xfc, 0xef, 0xd0, 0xfb, 0x2f, 0xc5, 0xe7, ++ 0x55, 0x7e, 0xb1, 0x7e, 0x94, 0xee, 0xa1, 0xa0, 0x7c, 0xdf, 0x6b, 0xdd, ++ 0x7d, 0x3f, 0x8c, 0x50, 0x5e, 0x8d, 0x72, 0x41, 0xef, 0x77, 0x9f, 0xbb, ++ 0x39, 0x0f, 0xb9, 0x90, 0xd7, 0x7d, 0xd3, 0xfd, 0xd5, 0xfd, 0x44, 0xdf, ++ 0x53, 0x3d, 0x64, 0xd6, 0x5f, 0xe8, 0x21, 0x9c, 0xe7, 0x0b, 0xeb, 0xee, ++ 0x77, 0xf2, 0xc9, 0xac, 0xb2, 0x7f, 0x4d, 0x7c, 0x43, 0xf3, 0x28, 0xc4, ++ 0xf7, 0x2c, 0xab, 0x7c, 0x29, 0xf8, 0xaf, 0x96, 0x77, 0x0d, 0x71, 0x3d, ++ 0xc8, 0xcb, 0x7d, 0x7a, 0xee, 0xdc, 0xf3, 0x5b, 0xad, 0xbb, 0x3a, 0xc7, ++ 0x13, 0x1e, 0xfc, 0xa4, 0xcf, 0xa9, 0xec, 0xf3, 0x8c, 0x5f, 0x53, 0x0c, ++ 0x1d, 0xc1, 0xfb, 0xb0, 0x21, 0x8c, 0x39, 0x69, 0x08, 0x7b, 0xdd, 0xef, ++ 0x12, 0x3f, 0x11, 0xfa, 0x05, 0xb3, 0xa7, 0x31, 0x42, 0xe7, 0xba, 0x74, ++ 0xe3, 0x6b, 0x32, 0x7b, 0x7f, 0x29, 0x86, 0xf5, 0x96, 0x21, 0x84, 0x09, ++ 0x10, 0xde, 0x0d, 0x71, 0x01, 0xf3, 0xf0, 0xce, 0x02, 0xe4, 0xdb, 0xe2, ++ 0x49, 0xf8, 0x69, 0x9c, 0xa5, 0xfb, 0xd4, 0x6c, 0x41, 0x79, 0x4b, 0x4b, ++ 0x8c, 0xf3, 0xb4, 0x9f, 0x7e, 0xaf, 0x56, 0x44, 0x9c, 0x7f, 0x47, 0xf0, ++ 0xbc, 0x02, 0xcf, 0x81, 0x9a, 0xbe, 0xef, 0x14, 0xdf, 0x4a, 0x8f, 0x4b, ++ 0xfc, 0xc2, 0x0d, 0xe3, 0xdc, 0xac, 0xc7, 0xb9, 0xee, 0x6f, 0xda, 0xef, ++ 0x89, 0xeb, 0x81, 0xcd, 0xb8, 0xd6, 0xf9, 0xa9, 0x3a, 0xff, 0xe9, 0xbc, ++ 0x7b, 0x37, 0xfb, 0x57, 0xfb, 0x62, 0x12, 0xdf, 0xff, 0x17, 0xae, 0x21, ++ 0x8f, 0x76, 0xa9, 0xf8, 0x2d, 0x35, 0xf8, 0xf4, 0x9e, 0x3b, 0xf0, 0x9b, ++ 0x21, 0x79, 0xfc, 0x6f, 0x6a, 0x8c, 0x09, 0xd0, 0x18, 0x10, 0x00, 0x00, ++ 0x00 }; + + static u8 bnx2_TPAT_b09FwText[] = { +- 0xbd, 0x58, 0x5d, 0x6c, 0x1c, 0x57, 0x15, 0x3e, 0x73, 0xe7, 0xee, 0x7a, +- 0x6d, 0x39, 0xf1, 0xb8, 0x99, 0x96, 0x4d, 0x63, 0xd4, 0x99, 0x78, 0xfc, +- 0x43, 0x6d, 0x95, 0x69, 0x59, 0x15, 0x17, 0x56, 0x68, 0xba, 0xbb, 0x71, +- 0xad, 0xaa, 0xaa, 0x5c, 0x29, 0x88, 0x4a, 0x8d, 0x90, 0x59, 0x37, 0x6d, +- 0x79, 0x4b, 0x11, 0x0f, 0x48, 0x45, 0xca, 0xb2, 0x76, 0xd2, 0x08, 0x2d, +- 0x99, 0xd6, 0x85, 0x44, 0x42, 0x7d, 0x88, 0x9c, 0x3a, 0xee, 0xc3, 0xca, +- 0x9b, 0x8a, 0x07, 0x24, 0xa4, 0xa8, 0x55, 0x80, 0xc0, 0x1b, 0x7d, 0xa8, +- 0xf8, 0x79, 0x22, 0x12, 0x0f, 0x54, 0x08, 0x90, 0x85, 0x04, 0x2a, 0xa5, +- 0xe4, 0xf2, 0x7d, 0x77, 0x67, 0x92, 0xc5, 0x4d, 0x41, 0xe5, 0x81, 0x95, +- 0x56, 0x77, 0xe6, 0xde, 0x73, 0xce, 0x3d, 0xf7, 0xfc, 0x7c, 0xe7, 0xdc, +- 0x39, 0xec, 0xc8, 0x88, 0x64, 0xbf, 0x7d, 0xf8, 0x57, 0xbe, 0x72, 0xe2, +- 0xeb, 0x0f, 0xdc, 0x57, 0xb9, 0x0f, 0x8f, 0x0f, 0x3a, 0x77, 0x6b, 0x2d, +- 0xff, 0xc7, 0x9f, 0x2b, 0xe2, 0xe5, 0x7a, 0xf0, 0x2f, 0x25, 0x55, 0x4d, +- 0x0e, 0xd6, 0x22, 0x29, 0xb9, 0xd5, 0xea, 0xfc, 0x6a, 0x24, 0x92, 0x74, +- 0xe7, 0x82, 0xba, 0xfc, 0xd3, 0xb4, 0x7c, 0x2d, 0x9c, 0xff, 0x64, 0xf5, +- 0x83, 0x4f, 0x5f, 0xf9, 0x6c, 0xb8, 0x7b, 0xc1, 0x95, 0x92, 0x57, 0x3d, +- 0xa3, 0xbd, 0x69, 0x29, 0x4d, 0x80, 0xe7, 0xd5, 0x99, 0x6f, 0x17, 0x64, +- 0x7f, 0x2e, 0xab, 0x65, 0x54, 0x74, 0xdd, 0x5c, 0x99, 0x89, 0xbc, 0x36, +- 0x36, 0xb8, 0xdc, 0x0b, 0xa4, 0xd6, 0x2b, 0xcb, 0x9b, 0x3d, 0x5f, 0xde, +- 0xe8, 0x69, 0x39, 0xfe, 0xca, 0x49, 0x59, 0x8f, 0xc3, 0x72, 0xc3, 0x2d, +- 0x89, 0xaa, 0x86, 0xe5, 0xa6, 0x04, 0xb2, 0x15, 0x87, 0xad, 0x15, 0x77, +- 0xdc, 0x29, 0x55, 0x4b, 0xf2, 0xc2, 0x8c, 0x92, 0x0b, 0xfe, 0x31, 0x79, +- 0x26, 0x7a, 0x12, 0x7f, 0x2d, 0x6a, 0x43, 0x3b, 0xf5, 0xf3, 0x5a, 0xf4, +- 0xc6, 0x98, 0x3c, 0x12, 0x1b, 0xb3, 0x1a, 0x27, 0xe0, 0x9f, 0x9c, 0x7d, +- 0x56, 0x86, 0xa5, 0xe5, 0x85, 0x4b, 0x22, 0x05, 0xd2, 0x48, 0x2d, 0x2e, +- 0x48, 0xe2, 0xf5, 0xcf, 0x75, 0xc1, 0x8e, 0x1f, 0x98, 0x2d, 0xf0, 0x0f, +- 0x47, 0xf9, 0xfa, 0x1d, 0xd9, 0xba, 0x97, 0xad, 0x2b, 0x51, 0xe7, 0xc2, +- 0x60, 0x5b, 0xa6, 0x12, 0xed, 0xdc, 0x30, 0xb5, 0xe8, 0x2e, 0xaf, 0xb6, +- 0xad, 0xc5, 0xdd, 0xa0, 0xfe, 0x91, 0x57, 0x17, 0x03, 0x1e, 0x97, 0x3c, +- 0x5a, 0x55, 0xbf, 0x06, 0xbf, 0x4d, 0x25, 0xca, 0x11, 0xb9, 0xda, 0x29, +- 0x7b, 0xb5, 0xde, 0x37, 0x9c, 0x5a, 0x7a, 0xc3, 0x24, 0x7a, 0x44, 0x54, +- 0x94, 0x38, 0xb5, 0x6d, 0xca, 0x1a, 0x16, 0x1d, 0x0d, 0x81, 0x67, 0xd2, +- 0x53, 0xc2, 0xb1, 0x96, 0xcd, 0x53, 0x76, 0x03, 0xcf, 0x8b, 0x4e, 0xb2, +- 0xad, 0x9d, 0xda, 0xf9, 0x25, 0x3c, 0x97, 0xc0, 0x0f, 0xbb, 0xc4, 0x8e, +- 0x24, 0xcb, 0x0e, 0xf8, 0x78, 0x4e, 0x0f, 0xef, 0x4a, 0x12, 0xdf, 0x93, +- 0xb5, 0x4a, 0x58, 0x6e, 0xc9, 0xa3, 0x4e, 0x7d, 0xfb, 0x43, 0x4e, 0xf3, +- 0x96, 0x7a, 0x1f, 0x9e, 0xa3, 0x2e, 0x0f, 0x6b, 0x63, 0xd4, 0xfd, 0x43, +- 0xd9, 0x19, 0x29, 0x2f, 0xe9, 0xeb, 0xef, 0xf3, 0x1d, 0x3a, 0xa7, 0xd0, +- 0xbd, 0x5b, 0x84, 0x3e, 0xc6, 0x70, 0x9f, 0x5a, 0x54, 0x87, 0x9e, 0x09, +- 0xfe, 0xe1, 0x99, 0x26, 0x42, 0xe1, 0xf0, 0xb9, 0x7d, 0x12, 0x8c, 0x1b, +- 0xd3, 0x88, 0x43, 0x6f, 0x5b, 0x26, 0x64, 0x2d, 0x9d, 0xf0, 0x8e, 0xa4, +- 0x6d, 0xac, 0xb7, 0x48, 0x03, 0x7b, 0x88, 0x1c, 0xe9, 0x1a, 0x73, 0x29, +- 0x3e, 0x50, 0x94, 0xfd, 0x6a, 0xbe, 0x20, 0x61, 0x90, 0x60, 0xee, 0xf0, +- 0xa5, 0xbd, 0x36, 0xbb, 0x27, 0xd3, 0x81, 0x76, 0xc7, 0x3e, 0xf1, 0xa1, +- 0xec, 0x7d, 0xd4, 0xab, 0x9d, 0xcf, 0xed, 0x6c, 0xf5, 0x86, 0x5d, 0x63, +- 0xa9, 0x55, 0xa0, 0xff, 0x47, 0x9e, 0x29, 0xe7, 0xa3, 0x2e, 0xd4, 0x1b, +- 0xf4, 0xd1, 0x2d, 0x9d, 0x9e, 0xfa, 0x90, 0x4e, 0xd4, 0x47, 0x89, 0x3e, +- 0x57, 0x92, 0xf5, 0xe8, 0x71, 0x25, 0xfb, 0x8d, 0x59, 0x8f, 0xb5, 0xd3, +- 0x38, 0x7f, 0x2c, 0x7b, 0x46, 0x1c, 0xa6, 0x88, 0xc3, 0x14, 0x71, 0x99, +- 0x8a, 0xa7, 0xaa, 0x81, 0x5c, 0x99, 0x29, 0xc9, 0x75, 0x17, 0xfe, 0xec, +- 0xcd, 0x79, 0xaf, 0x21, 0xa6, 0x12, 0xcf, 0x11, 0x37, 0x4a, 0x66, 0x0b, +- 0xc2, 0x77, 0xc4, 0x92, 0x4e, 0xca, 0x2e, 0x62, 0x29, 0x39, 0xca, 0xb9, +- 0x21, 0x59, 0xb1, 0x67, 0x99, 0xf3, 0x4e, 0x09, 0x7d, 0x55, 0xc3, 0xda, +- 0x64, 0x70, 0x4a, 0x76, 0x11, 0x1f, 0x35, 0xac, 0x53, 0x56, 0xe8, 0xb5, +- 0x40, 0xd1, 0x4e, 0xdf, 0x45, 0x0e, 0xf8, 0x88, 0xfb, 0x99, 0xb2, 0x12, +- 0x47, 0x56, 0xe7, 0x61, 0x8b, 0xf9, 0x29, 0xd8, 0x88, 0x39, 0xc1, 0xb8, +- 0xfa, 0xeb, 0xb4, 0x8e, 0x4e, 0x22, 0x7e, 0x40, 0x8b, 0xf3, 0x9f, 0x4a, +- 0x67, 0xc0, 0x1f, 0x15, 0xa9, 0xe7, 0x56, 0xac, 0x65, 0x3d, 0xbd, 0xa2, +- 0x0a, 0xd1, 0xef, 0x1d, 0xd9, 0x1f, 0xb6, 0x12, 0x09, 0x5b, 0x4a, 0x29, +- 0x9f, 0x5b, 0xbf, 0x84, 0x3c, 0x7a, 0xd3, 0xea, 0xaf, 0xc1, 0x57, 0xce, +- 0xf4, 0xa7, 0xdd, 0x45, 0x36, 0x3b, 0x61, 0xbc, 0x08, 0xdd, 0xae, 0xc2, +- 0xff, 0xb4, 0xf9, 0xa5, 0x2e, 0x64, 0x77, 0x1c, 0xe6, 0xae, 0xb4, 0xbb, +- 0xa4, 0xb3, 0x69, 0xbe, 0xa2, 0xab, 0xb2, 0xdc, 0xee, 0x9c, 0x34, 0x6e, +- 0x24, 0x2b, 0x85, 0x2a, 0xfd, 0x36, 0xba, 0x00, 0x3f, 0x2c, 0xb7, 0xbb, +- 0x13, 0x8f, 0x6d, 0x76, 0xa4, 0x75, 0x77, 0x55, 0x5a, 0x6e, 0x45, 0xdd, +- 0xa5, 0x64, 0x0c, 0x72, 0xab, 0xd8, 0x87, 0x71, 0x15, 0x06, 0x75, 0x77, +- 0xe2, 0xb1, 0x8b, 0x9d, 0x7b, 0x90, 0xb7, 0xf2, 0x41, 0xad, 0x12, 0x21, +- 0x77, 0xaf, 0x1e, 0x74, 0x25, 0x92, 0xb5, 0x5e, 0x49, 0x6a, 0xe9, 0x84, +- 0xac, 0xf7, 0x24, 0x79, 0x6a, 0x06, 0xfb, 0x55, 0xf0, 0xde, 0x9b, 0x97, +- 0x56, 0x6f, 0x62, 0x45, 0x55, 0x5b, 0x92, 0xf4, 0xd6, 0xf1, 0x2f, 0x49, +- 0xa3, 0x53, 0x2a, 0x5d, 0xec, 0xb4, 0xc8, 0x5f, 0x72, 0xaa, 0x81, 0x3e, +- 0xdc, 0xdd, 0x65, 0xdc, 0x40, 0xce, 0xf0, 0x97, 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0x45, 0x7f, 0x10, 0x67, 0xb6, 0x4d, 0xb2, +- 0xb1, 0x4f, 0xd3, 0xef, 0x07, 0xbf, 0x9a, 0x61, 0xf2, 0x17, 0xfb, 0xf5, +- 0x47, 0xf2, 0x9c, 0x62, 0x0e, 0xd9, 0x9c, 0xe2, 0x79, 0x70, 0x0f, 0x37, +- 0x66, 0x19, 0x7e, 0x7c, 0x3e, 0xce, 0xf3, 0x08, 0xf1, 0xf4, 0x40, 0x9e, +- 0xe3, 0xb0, 0x53, 0x74, 0xc3, 0xe8, 0xe9, 0x04, 0x36, 0xe3, 0xdd, 0xb7, +- 0x81, 0xde, 0x89, 0x76, 0x5a, 0x72, 0x9e, 0xb8, 0x79, 0xdf, 0xdd, 0xdb, +- 0x27, 0xd1, 0x6e, 0xb4, 0xeb, 0xa0, 0xdd, 0xc2, 0x78, 0x5c, 0x11, 0x03, +- 0x6e, 0x87, 0x13, 0x79, 0x3d, 0x07, 0x06, 0x4d, 0xe7, 0x76, 0xfa, 0xd8, +- 0x35, 0x3d, 0xe9, 0x7f, 0x2b, 0xd8, 0x8b, 0x0f, 0xdb, 0xee, 0x00, 0x3e, +- 0xdc, 0xa6, 0xe7, 0xa4, 0x0c, 0xda, 0x00, 0xf5, 0xcd, 0xf6, 0x21, 0xec, +- 0x31, 0x6f, 0x18, 0xd7, 0xf6, 0x9b, 0xc4, 0x46, 0xf6, 0x99, 0xdf, 0x2c, +- 0xc8, 0xc8, 0x3e, 0xfb, 0x9e, 0x6c, 0x73, 0x64, 0x4c, 0x48, 0xbf, 0x6e, +- 0x59, 0xfd, 0x1f, 0xcf, 0xf4, 0xef, 0xeb, 0x2c, 0xea, 0xa3, 0x30, 0x8d, +- 0xba, 0x7a, 0xd0, 0x35, 0xcc, 0xed, 0xd2, 0x52, 0xd5, 0x13, 0xd2, 0xa8, +- 0xb0, 0x5f, 0x12, 0xdc, 0xb5, 0xa0, 0xc3, 0x02, 0xf5, 0x28, 0x43, 0x8f, +- 0x51, 0xdc, 0x4d, 0xc2, 0xa5, 0x96, 0x84, 0xc9, 0x0a, 0x08, 0x67, 0xbe, +- 0x43, 0xbb, 0x1d, 0xd3, 0x5b, 0x1d, 0xda, 0xed, 0x49, 0xbd, 0xde, 0x99, +- 0x44, 0x7f, 0x18, 0xc2, 0xdb, 0xe1, 0xec, 0x25, 0x61, 0x8c, 0xcd, 0xc5, +- 0x1c, 0x4f, 0x0b, 0xfb, 0xb1, 0x63, 0x7a, 0xaa, 0xcb, 0xf1, 0x49, 0x1d, +- 0x75, 0x07, 0xe5, 0xfe, 0xc9, 0x00, 0x13, 0x93, 0xeb, 0xc8, 0xa3, 0x17, +- 0x7b, 0xfd, 0xbd, 0x71, 0x3f, 0xcc, 0xe4, 0x62, 0x2e, 0xcd, 0x65, 0x0b, +- 0x71, 0x8a, 0xb2, 0x21, 0x77, 0x32, 0xfe, 0x99, 0xdd, 0x83, 0xf7, 0xa3, +- 0x8f, 0xda, 0xe3, 0xae, 0xfc, 0xfb, 0x04, 0x72, 0xa7, 0x60, 0xb1, 0x67, +- 0x2d, 0xc5, 0x9d, 0xda, 0x37, 0xa6, 0x19, 0xbd, 0x0d, 0xdb, 0xa1, 0x47, +- 0x98, 0xf7, 0xf0, 0x07, 0xae, 0x2e, 0x73, 0x0d, 0x7d, 0x38, 0xee, 0x82, +- 0xbc, 0xcf, 0xad, 0xa5, 0x5c, 0x63, 0x8c, 0xa3, 0x57, 0x9c, 0xff, 0x15, +- 0x68, 0xdf, 0x31, 0xad, 0x9e, 0xb2, 0xf7, 0x75, 0x15, 0xe1, 0x1e, 0xd6, +- 0x63, 0x3f, 0x23, 0x4e, 0x23, 0x95, 0xa0, 0x19, 0x2f, 0xd8, 0xfb, 0x5a, +- 0xe2, 0x05, 0xbc, 0x93, 0xa2, 0x07, 0x9d, 0x1f, 0xe8, 0x41, 0xe7, 0xd1, +- 0x83, 0x8e, 0x15, 0x11, 0xe7, 0x09, 0xee, 0xa1, 0xaa, 0xd9, 0xcf, 0x9b, +- 0x31, 0xde, 0x39, 0xdb, 0xbe, 0xec, 0x43, 0x77, 0x05, 0xdd, 0x22, 0xec, +- 0xcf, 0xf5, 0x3b, 0xb3, 0xef, 0x5a, 0xa3, 0xa0, 0x4f, 0x6c, 0x3f, 0xd6, +- 0xf6, 0x8b, 0xd2, 0x8c, 0x49, 0x73, 0x28, 0xa3, 0xf9, 0xf2, 0x1e, 0x9a, +- 0x3b, 0x79, 0x46, 0xca, 0x96, 0xe6, 0x2b, 0xcc, 0x3b, 0xd6, 0xd2, 0x62, +- 0x96, 0x6f, 0x27, 0xf0, 0x3c, 0x94, 0x3d, 0xe7, 0xf4, 0xf7, 0xee, 0xe1, +- 0x7f, 0xc8, 0xe9, 0xbf, 0xf3, 0x99, 0x3a, 0x27, 0xec, 0x93, 0x21, 0x6f, +- 0xc1, 0xe9, 0x7f, 0x27, 0xc1, 0x85, 0x73, 0x84, 0x3e, 0xe9, 0xf7, 0x17, +- 0xc0, 0x60, 0x74, 0x5f, 0x53, 0xb0, 0xbb, 0x31, 0xed, 0x05, 0xe2, 0xda, +- 0xdc, 0xec, 0x11, 0x8b, 0x6f, 0x6a, 0x42, 0x49, 0x8e, 0xb9, 0x83, 0xcf, +- 0x18, 0x17, 0xec, 0x37, 0x03, 0xbc, 0xf7, 0x65, 0x6c, 0xe1, 0xfe, 0x2c, +- 0xc8, 0xe1, 0x96, 0xd5, 0xcb, 0xe9, 0xdf, 0x8b, 0xbc, 0x1a, 0xeb, 0x01, +- 0xea, 0xc6, 0x0c, 0xf5, 0xba, 0xf9, 0x6d, 0x63, 0x05, 0xb5, 0xe6, 0x2d, +- 0xc4, 0x3e, 0xf2, 0xd3, 0xf6, 0x58, 0x5b, 0xf6, 0xdb, 0x02, 0xea, 0xd0, +- 0x08, 0xee, 0x4b, 0xd1, 0xcd, 0x6f, 0x0c, 0x72, 0x01, 0x34, 0x17, 0xb1, +- 0x76, 0xba, 0x9b, 0xf7, 0xbc, 0xe8, 0xf3, 0x81, 0x7b, 0xab, 0xd1, 0xfb, +- 0xa6, 0xe9, 0x0f, 0xd2, 0xf2, 0xf7, 0x2f, 0x97, 0xa2, 0x15, 0x3a, 0x18, +- 0x15, 0x00, 0x00, 0x00 }; ++ 0xbd, 0x58, 0x5d, 0x6c, 0x1c, 0xd5, 0x15, 0x3e, 0x33, 0x3b, 0xde, 0x1d, ++ 0x3b, 0x76, 0x32, 0x86, 0x25, 0xdd, 0x50, 0xc7, 0xcc, 0xd8, 0x63, 0x7b, ++ 0xa9, 0xad, 0x30, 0x94, 0x05, 0x16, 0x75, 0x68, 0xa7, 0xbb, 0x6b, 0xc7, ++ 0x0d, 0x79, 0x70, 0xd4, 0x54, 0x84, 0x92, 0x07, 0xb3, 0x4e, 0x08, 0x2d, ++ 0xad, 0x14, 0x68, 0x1f, 0xa2, 0xf2, 0x90, 0xed, 0xda, 0x09, 0x69, 0xbb, ++ 0xf1, 0x52, 0x53, 0x25, 0x2f, 0x7d, 0x88, 0x9c, 0x38, 0xe6, 0x61, 0xc9, ++ 0x86, 0xf6, 0xa9, 0x0f, 0x08, 0x2b, 0x94, 0x00, 0x0f, 0x15, 0xa2, 0xa2, ++ 0x55, 0x1f, 0x23, 0x40, 0x40, 0xa5, 0xb6, 0x8a, 0xaa, 0x82, 0x10, 0x4d, ++ 0x33, 0xfd, 0xbe, 0x3b, 0x33, 0xc9, 0xe6, 0x4f, 0x7d, 0xeb, 0x4a, 0xab, ++ 0xb9, 0x33, 0xf7, 0x9e, 0x73, 0xcf, 0x3d, 0x3f, 0xdf, 0x39, 0xe7, 0x0e, ++ 0x69, 0xd2, 0x23, 0xf1, 0xaf, 0x0f, 0xff, 0xfb, 0x9f, 0xd8, 0xff, 0x63, ++ 0x6f, 0x8b, 0xb7, 0x05, 0xc3, 0xef, 0x6b, 0x22, 0x5d, 0xf2, 0x7f, 0xfc, ++ 0xa5, 0x44, 0xac, 0x44, 0x0e, 0xfe, 0xc5, 0xd4, 0xfd, 0xb5, 0x81, 0x92, ++ 0x2b, 0x66, 0xca, 0xaf, 0xd8, 0x73, 0xae, 0x48, 0xd0, 0x1a, 0xb7, 0xcb, ++ 0xf2, 0x9f, 0xb0, 0x96, 0x35, 0x84, 0xdf, 0x37, 0xfb, 0x97, 0xee, 0x79, ++ 0xf5, 0x41, 0xe7, 0xe2, 0x89, 0x94, 0x98, 0x96, 0x7f, 0xc4, 0xb0, 0x46, ++ 0xc5, 0x1c, 0x00, 0xcd, 0xaf, 0xc7, 0xde, 0xd7, 0x65, 0x7d, 0xc2, 0xab, ++ 0x16, 0xea, 0xee, 0x85, 0xf0, 0xd5, 0x31, 0xd7, 0xaa, 0x63, 0x83, 0xb3, ++ 0x6d, 0x5b, 0x4a, 0xed, 0x9c, 0xbc, 0xd6, 0xce, 0xca, 0x2b, 0x6d, 0x43, ++ 0xf6, 0xbe, 0x78, 0x50, 0x16, 0x3c, 0x27, 0x57, 0x49, 0x99, 0xa2, 0xfb, ++ 0x4e, 0xae, 0x2a, 0xb6, 0xac, 0x78, 0x4e, 0x6d, 0x36, 0xd5, 0xaf, 0x99, ++ 0xbe, 0x29, 0xcf, 0x8d, 0xe9, 0x72, 0x22, 0xbb, 0x5b, 0x9e, 0x74, 0x77, ++ 0xe1, 0x6f, 0x88, 0xbe, 0x64, 0x68, 0xe5, 0xe3, 0x86, 0x18, 0x4b, 0x1b, ++ 0x64, 0xab, 0x17, 0x86, 0x73, 0x5e, 0x00, 0xfa, 0xe1, 0xfc, 0x3e, 0xe9, ++ 0x96, 0x9a, 0xe5, 0x4c, 0x53, 0x69, 0x58, 0x23, 0x25, 0xaf, 0x4b, 0x02, ++ 0x2b, 0x3a, 0xd7, 0x09, 0xf5, 0xbc, 0x14, 0xae, 0x80, 0xbe, 0xdb, 0x4d, ++ 0xe6, 0x6f, 0x8b, 0xe7, 0xad, 0x78, 0x5e, 0x17, 0xfd, 0x98, 0x63, 0xaf, ++ 0xca, 0x48, 0x60, 0x68, 0x97, 0xc3, 0x92, 0xbb, 0xd1, 0x2a, 0xad, 0x1a, ++ 0x92, 0x5a, 0xa2, 0xfc, 0xae, 0x55, 0x96, 0x10, 0x34, 0x29, 0xd2, 0x18, ++ 0xba, 0xff, 0x2c, 0xec, 0x36, 0x12, 0xe8, 0x30, 0xd1, 0xb9, 0x46, 0xce, ++ 0x2a, 0xb5, 0x0f, 0x68, 0xa5, 0xe6, 0xe5, 0x30, 0x30, 0x7a, 0x44, 0x77, ++ 0x03, 0xad, 0xb4, 0x4a, 0x5e, 0xdd, 0x62, 0xb8, 0x19, 0xd0, 0x0c, 0x5b, ++ 0xba, 0xf0, 0x59, 0x8a, 0xbf, 0x93, 0x77, 0x05, 0xe3, 0x29, 0x2d, 0x58, ++ 0x35, 0xb4, 0xd2, 0xf1, 0x69, 0x8c, 0x4d, 0xd0, 0x43, 0x2f, 0x9e, 0x26, ++ 0xc1, 0x8c, 0x06, 0x3a, 0x9e, 0xd3, 0xc2, 0xbb, 0x2e, 0x41, 0xd6, 0x92, ++ 0xf9, 0x82, 0x93, 0xab, 0xc9, 0x36, 0xad, 0xbc, 0x7a, 0x83, 0xd1, 0xac, ++ 0xe9, 0xf6, 0x8d, 0xdf, 0x28, 0xcb, 0x37, 0x8d, 0x30, 0xd4, 0xef, 0xcd, ++ 0xc4, 0x67, 0x24, 0xbf, 0x20, 0x92, 0x3f, 0xcb, 0x77, 0xc8, 0xdc, 0x84, ++ 0xec, 0xad, 0x34, 0xe4, 0x09, 0x43, 0xee, 0x53, 0x72, 0xcb, 0x90, 0x33, ++ 0xc0, 0xdf, 0x39, 0x52, 0x85, 0x2b, 0x0c, 0x1d, 0xeb, 0x13, 0xbb, 0x3f, ++ 0x0c, 0x2b, 0x9e, 0x63, 0xad, 0x8a, 0x2f, 0xf3, 0xcd, 0x01, 0x6b, 0xb2, ++ 0x59, 0xc7, 0x7c, 0x8d, 0x6b, 0xa0, 0x0f, 0x91, 0xc9, 0x56, 0x18, 0x9e, ++ 0xf6, 0xde, 0x85, 0xad, 0xf5, 0x89, 0x2e, 0x71, 0xec, 0x00, 0xdf, 0x86, ++ 0x4e, 0x5f, 0xaf, 0xb3, 0xbb, 0x62, 0x19, 0xa8, 0x77, 0xec, 0xe3, 0x7d, ++ 0x39, 0x7e, 0xef, 0xb5, 0x4a, 0xc7, 0x13, 0x3d, 0x2b, 0xb9, 0xa1, 0x57, ++ 0x4f, 0x4a, 0x05, 0xc8, 0x7f, 0xcb, 0x33, 0x25, 0x74, 0x94, 0x85, 0x72, ++ 0x63, 0xbd, 0x7b, 0x55, 0xa6, 0xc7, 0x6f, 0x90, 0x89, 0xf2, 0xe8, 0x62, ++ 0x1c, 0x33, 0x65, 0xc1, 0xfd, 0x58, 0x93, 0xf5, 0x61, 0xb8, 0xe0, 0x19, ++ 0x5a, 0xe5, 0xf8, 0xa7, 0xf1, 0x18, 0x7e, 0xd8, 0x84, 0x1f, 0x36, 0xe1, ++ 0x97, 0x4d, 0xb1, 0x74, 0xdf, 0x96, 0x57, 0xc7, 0x4c, 0xb9, 0x90, 0x82, ++ 0x3d, 0xdb, 0x9c, 0xcf, 0x48, 0xdd, 0x73, 0xe5, 0x50, 0x93, 0x9a, 0xc9, ++ 0xc8, 0xbc, 0xfb, 0x79, 0xb8, 0x07, 0xfa, 0x38, 0x25, 0xe1, 0x5d, 0x25, ++ 0xf8, 0x6c, 0x09, 0xea, 0x7c, 0xce, 0xcd, 0xcb, 0xa1, 0xb6, 0x2b, 0xf5, ++ 0x36, 0xe9, 0x16, 0x24, 0xa2, 0xdb, 0x00, 0xba, 0x09, 0xd0, 0x15, 0xe4, ++ 0xb0, 0xa2, 0xdd, 0x00, 0xda, 0x8b, 0x31, 0xed, 0x78, 0x6e, 0x4a, 0x3c, ++ 0xd0, 0x0c, 0xdb, 0x53, 0xf0, 0xb9, 0xd9, 0xec, 0x04, 0x68, 0x27, 0x64, ++ 0x01, 0xff, 0x7a, 0x53, 0x6a, 0x46, 0x81, 0x7c, 0x9d, 0xdc, 0x1e, 0xea, ++ 0x5c, 0xf1, 0xac, 0x81, 0x67, 0x16, 0x73, 0x26, 0xf8, 0x18, 0x78, 0x7e, ++ 0x18, 0xd6, 0x9b, 0xf0, 0xed, 0x2c, 0xc7, 0xaf, 0x85, 0xba, 0x0f, 0x3d, ++ 0x14, 0x5c, 0xbb, 0x2e, 0x7c, 0x4f, 0x4b, 0x19, 0xb6, 0xd4, 0xdd, 0x0d, ++ 0x52, 0xb5, 0x34, 0x4d, 0xf7, 0x53, 0x52, 0x85, 0x16, 0x82, 0x19, 0x43, ++ 0x7d, 0x9b, 0xb5, 0x34, 0xc4, 0xd8, 0x16, 0x3d, 0xc2, 0x9c, 0x2e, 0xac, ++ 0x81, 0xfd, 0xdd, 0x5e, 0xa9, 0x66, 0xfb, 0xb1, 0x16, 0x81, 0xd6, 0x33, ++ 0x82, 0x18, 0xed, 0xc7, 0x1a, 0x3e, 0x69, 0x07, 0xac, 0x77, 0xb9, 0xbe, ++ 0x17, 0x32, 0x26, 0xdf, 0x7a, 0xa5, 0x76, 0x8d, 0x7d, 0x28, 0xa3, 0xb2, ++ 0x0b, 0xf6, 0x37, 0x62, 0xdb, 0x76, 0xda, 0x2b, 0x99, 0xb7, 0x78, 0xbe, ++ 0xcf, 0xcb, 0xee, 0xb9, 0xbb, 0x75, 0xb9, 0x18, 0x2e, 0xbb, 0x5a, 0x6a, ++ 0x6e, 0x22, 0x05, 0x99, 0x4a, 0xb0, 0xdd, 0x77, 0x94, 0x4c, 0xf5, 0x56, ++ 0x0e, 0x7e, 0x36, 0x6e, 0x9d, 0x94, 0x75, 0x38, 0x9f, 0x53, 0x14, 0x19, ++ 0xc6, 0x58, 0x93, 0x29, 0x77, 0x00, 0xb4, 0x8e, 0x55, 0x15, 0x9c, 0xd5, ++ 0x1d, 0xb7, 0x26, 0x71, 0xd6, 0x60, 0x27, 0xfc, 0xdb, 0x8d, 0xe8, 0x0e, ++ 0xb7, 0x38, 0xfe, 0x6e, 0xcc, 0x03, 0xff, 0x06, 0x31, 0x4b, 0x36, 0xcf, ++ 0xb9, 0x41, 0x3f, 0xfc, 0xa2, 0x58, 0x56, 0x32, 0x38, 0xd6, 0x05, 0x08, ++ 0xd3, 0xed, 0xbb, 0x83, 0x77, 0x1f, 0x0d, 0x76, 0x40, 0x34, 0x73, 0x13, ++ 0xd6, 0x3c, 0x34, 0xe6, 0x1c, 0x58, 0x13, 0x67, 0xb6, 0x06, 0xde, 0xeb, ++ 0x5d, 0xee, 0xe9, 0x04, 0x8f, 0x69, 0x0f, 0xc0, 0xf7, 0x1d, 0x8f, 0xc2, ++ 0xe7, 0x7c, 0x7f, 0x30, 0x37, 0x26, 0x66, 0x9f, 0x1f, 0x0c, 0xbe, 0x3c, ++ 0x32, 0xbe, 0x6b, 0x83, 0xd4, 0xfa, 0xd3, 0xf0, 0xb5, 0x29, 0x59, 0xcb, ++ 0xd1, 0xe7, 0x0e, 0x60, 0x51, 0xa9, 0x61, 0x4b, 0xfd, 0x0e, 0xc7, 0xfe, ++ 0x21, 0xc6, 0xcb, 0x8d, 0x6e, 0xc8, 0x96, 0x13, 0xfd, 0x28, 0xf1, 0x33, ++ 0x3f, 0x58, 0x6a, 0x68, 0xc4, 0x4a, 0xca, 0x65, 0x6a, 0x78, 0x1f, 0x6a, ++ 0xbd, 0x03, 0x39, 0x1d, 0x5b, 0x80, 0x73, 0x5b, 0x9b, 0xdc, 0x63, 0x0d, ++ 0x32, 0x6e, 0x93, 0xd9, 0x7e, 0xe2, 0xe2, 0x80, 0x98, 0x47, 0x4d, 0xe9, ++ 0xf6, 0x45, 0x4e, 0x36, 0x9c, 0xdc, 0x93, 0x52, 0xcb, 0xa5, 0xb0, 0xc7, ++ 0x4f, 0xf0, 0xff, 0x16, 0x78, 0x57, 0xc0, 0xeb, 0xbc, 0xeb, 0xe4, 0x9e, ++ 0x92, 0x71, 0xeb, 0x1d, 0xf9, 0x2c, 0x64, 0x2c, 0xef, 0x69, 0xfd, 0x41, ++ 0x4f, 0x72, 0xc8, 0x42, 0x63, 0xdc, 0x5a, 0xa4, 0x6e, 0x66, 0xd4, 0xba, ++ 0xfd, 0x35, 0x9c, 0x7d, 0x4d, 0x38, 0x1e, 0xb7, 0xde, 0x96, 0x3f, 0x62, ++ 0x3d, 0x65, 0xa7, 0x4d, 0x21, 0x67, 0x8b, 0xf2, 0xd9, 0x90, 0x8f, 0xba, ++ 0x72, 0x07, 0xe7, 0x40, 0x5b, 0x96, 0xaf, 0x40, 0xef, 0x97, 0x43, 0xc3, ++ 0x75, 0xac, 0xc7, 0xb4, 0x1c, 0xce, 0x35, 0x0a, 0x7b, 0x86, 0x78, 0xaf, ++ 0x39, 0x19, 0xe8, 0xa2, 0x0b, 0xf2, 0xaf, 0x34, 0x1c, 0xfb, 0x79, 0xc9, ++ 0x49, 0xfa, 0xe8, 0x9a, 0x6d, 0xa8, 0x1c, 0xe1, 0x0f, 0x96, 0xb0, 0x1e, ++ 0xbe, 0x01, 0x3e, 0xc1, 0x20, 0xf3, 0xc4, 0xf6, 0x96, 0x26, 0x2b, 0x90, ++ 0x73, 0x5e, 0xcd, 0x57, 0x06, 0x79, 0xfe, 0xbd, 0xad, 0xb5, 0x7b, 0xd3, ++ 0x12, 0xe9, 0x60, 0xa4, 0xe5, 0xc0, 0x5f, 0x79, 0xfe, 0x01, 0x31, 0x5e, ++ 0xb6, 0x65, 0xaa, 0xdd, 0x23, 0x17, 0x94, 0xbe, 0x55, 0x0e, 0xc8, 0x23, ++ 0xae, 0xa0, 0x47, 0x25, 0x77, 0xee, 0x1d, 0xa1, 0xee, 0x0c, 0xf0, 0xfb, ++ 0x22, 0x9c, 0x85, 0xcf, 0x2f, 0xb8, 0xa0, 0x6b, 0x53, 0x7f, 0x91, 0x4d, ++ 0x69, 0xb7, 0x05, 0xe4, 0x81, 0xf3, 0x9e, 0xc0, 0xd3, 0x47, 0xf2, 0xa7, ++ 0xf1, 0x5e, 0x2f, 0x3a, 0xf0, 0x91, 0xf1, 0xfc, 0xa4, 0xf0, 0xa9, 0x0f, ++ 0xe8, 0xf4, 0x1b, 0x8f, 0x98, 0xd5, 0x39, 0xc6, 0xb3, 0x48, 0x1e, 0x7c, ++ 0x7f, 0x0b, 0xf9, 0xc9, 0x43, 0x4e, 0x9a, 0x90, 0xdf, 0xb6, 0xf3, 0xf2, ++ 0x1b, 0xc4, 0xf3, 0x2b, 0xc8, 0x53, 0x67, 0xdb, 0xe6, 0xac, 0xe1, 0xcb, ++ 0x4c, 0xbd, 0x71, 0x30, 0x4c, 0xb9, 0x32, 0x9b, 0xf6, 0x89, 0x69, 0xbd, ++ 0x45, 0x60, 0xd4, 0x4c, 0xbd, 0x35, 0xb0, 0xfd, 0x5c, 0x43, 0x6a, 0x77, ++ 0xfa, 0xfa, 0x46, 0x5d, 0x36, 0x00, 0xd7, 0x88, 0xb5, 0xf0, 0xd3, 0xf6, ++ 0xc0, 0xf6, 0xd7, 0x1b, 0x77, 0xe1, 0x1c, 0x72, 0x09, 0x71, 0x89, 0x7c, ++ 0x76, 0x6e, 0x53, 0x0a, 0xfa, 0x62, 0x2c, 0x03, 0x73, 0x83, 0xc7, 0xc7, ++ 0xe0, 0x0f, 0x05, 0x8c, 0xb1, 0x47, 0xad, 0x3d, 0x30, 0xab, 0xfb, 0x35, ++ 0x09, 0xda, 0x0b, 0xf8, 0x9b, 0x32, 0xd9, 0x30, 0xcd, 0xd7, 0xc1, 0x53, ++ 0x2f, 0x38, 0x76, 0x29, 0x75, 0x91, 0x18, 0x0a, 0xfa, 0x1a, 0x79, 0x41, ++ 0x6f, 0xb6, 0x31, 0xd4, 0xea, 0x7e, 0x14, 0xfa, 0x06, 0x56, 0x18, 0x88, ++ 0xd9, 0x02, 0x30, 0x84, 0xb6, 0xcc, 0xa6, 0xa4, 0x07, 0xf8, 0x00, 0x8c, ++ 0xa8, 0xb5, 0x1f, 0x96, 0x14, 0x73, 0x87, 0xcb, 0xf5, 0x45, 0xf8, 0x1a, ++ 0x9f, 0x85, 0xc1, 0x61, 0xf5, 0xf4, 0xe2, 0xe7, 0x84, 0x7a, 0xde, 0x0e, ++ 0xdf, 0xff, 0xd1, 0x28, 0xf2, 0xa8, 0x4b, 0x1b, 0xe5, 0x36, 0x97, 0x5c, ++ 0x13, 0xb4, 0xc8, 0xa7, 0xa0, 0x0f, 0x5a, 0xcc, 0xf5, 0x97, 0xc2, 0x27, ++ 0x0c, 0xf8, 0xa4, 0xbb, 0x06, 0xd4, 0x71, 0xac, 0x8a, 0x3c, 0xac, 0x72, ++ 0x3e, 0xf9, 0x0d, 0xb5, 0xb4, 0x78, 0x0f, 0x1b, 0x63, 0xc6, 0x1e, 0xc7, ++ 0x7e, 0xbc, 0x5f, 0x7e, 0xd0, 0x6e, 0xe1, 0x0c, 0xfe, 0x7e, 0xa9, 0x14, ++ 0x44, 0xe6, 0x1b, 0x88, 0x8f, 0x26, 0xce, 0x5c, 0xc4, 0x1f, 0x78, 0x1b, ++ 0x58, 0x45, 0xe8, 0xc2, 0x09, 0xe0, 0x9b, 0xde, 0x2c, 0x6c, 0x9b, 0x39, ++ 0x4a, 0xbf, 0xda, 0x6d, 0xac, 0xc0, 0x0f, 0x0d, 0x7f, 0x97, 0xb1, 0xd0, ++ 0x18, 0xf6, 0x3e, 0xc2, 0x7e, 0x88, 0x43, 0xd8, 0x72, 0xdc, 0x3b, 0x2d, ++ 0xf4, 0x15, 0xc7, 0x3e, 0xac, 0x7c, 0x67, 0xb7, 0x31, 0xa2, 0xf6, 0xd8, ++ 0x65, 0xb8, 0xad, 0x4e, 0xbe, 0x7f, 0x87, 0x6f, 0x3b, 0xde, 0x05, 0x29, ++ 0xca, 0xf3, 0xed, 0x68, 0x6f, 0xd8, 0x48, 0xb6, 0x36, 0x8a, 0xc0, 0xdf, ++ 0x1b, 0xf8, 0x17, 0x13, 0xfe, 0xab, 0x8a, 0x37, 0xb1, 0x75, 0xdc, 0x5b, ++ 0xbd, 0xe9, 0x1e, 0x1b, 0x93, 0xfc, 0x89, 0x3c, 0x1d, 0xd5, 0x13, 0xf3, ++ 0xcd, 0x0c, 0x30, 0x3b, 0x0c, 0xab, 0xee, 0x01, 0xe8, 0xbd, 0x07, 0xf8, ++ 0x6a, 0xe1, 0xcf, 0x98, 0xe3, 0x9c, 0x26, 0x55, 0xc6, 0x7a, 0x9b, 0x63, ++ 0xce, 0x31, 0xdf, 0x66, 0xf0, 0x3c, 0x88, 0xb5, 0x1f, 0x86, 0xb5, 0x36, ++ 0x73, 0x01, 0x75, 0x07, 0x0c, 0x6f, 0x9b, 0x5a, 0xb9, 0x29, 0x5a, 0xa5, ++ 0x29, 0x76, 0xd5, 0x33, 0x94, 0x7f, 0x04, 0x96, 0x05, 0xdb, 0xd2, 0x1e, ++ 0x13, 0x46, 0x8c, 0x1b, 0xb4, 0x17, 0xec, 0x6e, 0x64, 0x10, 0xe3, 0x01, ++ 0xfc, 0x40, 0xdf, 0x8b, 0x1c, 0x7e, 0x22, 0x2b, 0x1b, 0x74, 0xb7, 0x3b, ++ 0x55, 0xcf, 0x4a, 0x9f, 0xee, 0x52, 0xb6, 0x67, 0x52, 0x90, 0x8d, 0xf3, ++ 0x41, 0xd5, 0x7b, 0x19, 0x7b, 0xfa, 0x2a, 0x5f, 0x54, 0x1a, 0x49, 0x5d, ++ 0x02, 0x9e, 0x2e, 0x73, 0x9a, 0x19, 0xd7, 0x27, 0xa5, 0xb8, 0xf6, 0x40, ++ 0x3c, 0x21, 0x8f, 0xee, 0x40, 0xdd, 0x51, 0x57, 0xfe, 0xeb, 0xd4, 0x6c, ++ 0xfd, 0x72, 0x38, 0x3c, 0xca, 0x1c, 0x12, 0x86, 0xfb, 0xbd, 0x29, 0xac, ++ 0x6d, 0x41, 0xf6, 0x69, 0xd4, 0x1e, 0xac, 0x57, 0x54, 0xbc, 0x43, 0xb6, ++ 0xbe, 0xa8, 0x2e, 0x41, 0xcd, 0x52, 0x57, 0x35, 0x4a, 0x37, 0x7c, 0x47, ++ 0xc3, 0xdf, 0xb1, 0x67, 0x85, 0xdf, 0xa5, 0x5b, 0xc7, 0x7b, 0x15, 0x79, ++ 0x67, 0xa1, 0xb0, 0x4d, 0xab, 0xac, 0xbe, 0x99, 0x8a, 0x31, 0x0a, 0x72, ++ 0x23, 0xef, 0x64, 0x49, 0x97, 0x06, 0x5d, 0x1f, 0x68, 0xce, 0x63, 0xae, ++ 0x0b, 0xcf, 0x4e, 0x3e, 0xaa, 0xd6, 0x21, 0x3e, 0x61, 0xaf, 0x69, 0x31, ++ 0xfc, 0x1e, 0xe4, 0xf3, 0x11, 0xbb, 0x22, 0xf7, 0xc5, 0x75, 0x25, 0x73, ++ 0xcd, 0xd7, 0x3b, 0x72, 0x8d, 0x2d, 0x29, 0x15, 0x9b, 0x0f, 0xc5, 0x39, ++ 0x92, 0x75, 0xc6, 0x03, 0xf1, 0x7c, 0x16, 0xf5, 0xc2, 0x7d, 0x71, 0xdd, ++ 0x63, 0x62, 0xec, 0xcb, 0x11, 0x55, 0x3b, 0xa4, 0x59, 0x3b, 0x00, 0xc3, ++ 0x6b, 0x45, 0x60, 0xac, 0xf7, 0x09, 0x70, 0xb1, 0x0c, 0x04, 0xfa, 0x7d, ++ 0xc3, 0x40, 0x4e, 0x4a, 0x81, 0x9e, 0xb5, 0xab, 0x69, 0x00, 0xab, 0xad, ++ 0x4f, 0x70, 0x26, 0xe6, 0x1b, 0xe2, 0x4c, 0x97, 0xef, 0xda, 0x87, 0x64, ++ 0x34, 0x77, 0x08, 0x79, 0x3c, 0x05, 0x1c, 0x36, 0x84, 0xfb, 0x26, 0xb5, ++ 0x26, 0x7f, 0x7d, 0xf1, 0x13, 0x50, 0xe3, 0xb2, 0x3e, 0xcc, 0x80, 0xc7, ++ 0x88, 0x3d, 0x09, 0xbc, 0x99, 0x2f, 0xfe, 0x2f, 0x9a, 0x91, 0x98, 0x06, ++ 0x75, 0x57, 0x81, 0xfb, 0x02, 0xf3, 0x15, 0x4e, 0x7b, 0x1d, 0xfe, 0xe0, ++ 0xc1, 0x1f, 0x44, 0xaa, 0x4d, 0xe0, 0x00, 0x6c, 0xac, 0x7c, 0x0d, 0xeb, ++ 0xf5, 0x02, 0x72, 0x7e, 0x96, 0x7e, 0x4d, 0x7f, 0xdf, 0x19, 0xfb, 0xfb, ++ 0x0c, 0xfc, 0xdd, 0xc9, 0x9f, 0x45, 0x1c, 0x9d, 0xbd, 0x26, 0x8e, 0x76, ++ 0xc6, 0x3e, 0x3e, 0x03, 0x1f, 0xff, 0x22, 0x2d, 0x3d, 0x26, 0x71, 0x80, ++ 0x79, 0x53, 0x2b, 0xa1, 0x76, 0x81, 0x1f, 0xc4, 0x7c, 0xb6, 0xc7, 0x7c, ++ 0xa6, 0x6f, 0xc1, 0x67, 0x7b, 0xcc, 0x67, 0xba, 0x93, 0x0f, 0xe8, 0x2a, ++ 0x31, 0x5d, 0x70, 0x0b, 0xba, 0x4a, 0x4c, 0x17, 0x74, 0xd0, 0x99, 0x38, ++ 0x13, 0xcf, 0x45, 0x3c, 0xbd, 0x08, 0x5b, 0x78, 0xa2, 0x7c, 0xc5, 0x0a, ++ 0xf0, 0x7c, 0x5a, 0xab, 0x5a, 0x36, 0xed, 0x8a, 0x38, 0xa0, 0x1e, 0xba, ++ 0x18, 0x03, 0xd7, 0xe9, 0x6e, 0x06, 0xba, 0xbb, 0xe2, 0xef, 0xf8, 0x7d, ++ 0x0d, 0xbe, 0x62, 0xc9, 0xa9, 0x31, 0xd6, 0x4a, 0x4e, 0x2d, 0xb8, 0x66, ++ 0xed, 0xa3, 0x4a, 0xcf, 0xfa, 0xe2, 0xcd, 0x6c, 0x80, 0x3a, 0x82, 0x35, ++ 0x51, 0x33, 0x25, 0x65, 0x83, 0xb1, 0xfa, 0xf3, 0x2e, 0xe5, 0xbb, 0x67, ++ 0xb0, 0xfe, 0x4c, 0x14, 0x57, 0x93, 0x0d, 0x64, 0xc3, 0xe5, 0x5e, 0xd9, ++ 0x8b, 0x7a, 0x67, 0x0f, 0x7c, 0xe9, 0xa4, 0x87, 0x28, 0x94, 0x61, 0xf8, ++ 0x45, 0x08, 0xbf, 0x76, 0x94, 0x6d, 0x4b, 0xee, 0xfc, 0x11, 0x5d, 0x7e, ++ 0x2a, 0x43, 0x5b, 0x7a, 0xa4, 0xeb, 0x74, 0x54, 0xaf, 0x19, 0xcb, 0x9d, ++ 0xfb, 0x3c, 0x4b, 0x19, 0xcc, 0x0c, 0x72, 0xef, 0xc7, 0x0d, 0x4b, 0x5e, ++ 0x02, 0x9f, 0x6e, 0xd7, 0x01, 0x8a, 0xdc, 0x2e, 0x17, 0xac, 0xa8, 0xf6, ++ 0xe8, 0x45, 0x3e, 0x6d, 0x8c, 0x38, 0xf9, 0x9a, 0xe6, 0xe4, 0xd8, 0xbf, ++ 0x2c, 0x37, 0xee, 0x11, 0x7d, 0x87, 0x93, 0xfb, 0x01, 0x26, 0x4f, 0x35, ++ 0x4c, 0x7d, 0x0e, 0x79, 0xfd, 0x67, 0xc2, 0x9e, 0xc4, 0xd4, 0x91, 0x6f, ++ 0xa7, 0x81, 0xa9, 0x33, 0x49, 0xbe, 0x7f, 0x53, 0xfe, 0x15, 0x06, 0x3b, ++ 0x49, 0x43, 0x7b, 0xb8, 0x83, 0xb4, 0x47, 0x92, 0xef, 0xbb, 0x7d, 0x63, ++ 0xf3, 0xdd, 0x23, 0xcc, 0xd7, 0xfe, 0x20, 0x79, 0x2c, 0x5f, 0xd9, 0x8b, ++ 0x36, 0xcb, 0x0f, 0x2e, 0x60, 0xcd, 0x3a, 0xe4, 0xed, 0xa7, 0x47, 0xee, ++ 0x04, 0xef, 0xe0, 0x5e, 0x13, 0x35, 0x4f, 0x97, 0xca, 0xa5, 0x6b, 0xac, ++ 0xb3, 0x8b, 0x6f, 0x63, 0x8f, 0x05, 0xd7, 0xf1, 0x1e, 0x11, 0x27, 0x57, ++ 0x16, 0x95, 0xeb, 0xad, 0xed, 0x90, 0xe9, 0x29, 0xd4, 0x6f, 0x1f, 0xc5, ++ 0x39, 0x80, 0xf8, 0x5c, 0x51, 0x63, 0x17, 0xf9, 0xfe, 0x4f, 0x88, 0x01, ++ 0xe4, 0xfa, 0xc5, 0x6b, 0x6a, 0xa2, 0xb8, 0x1e, 0x7a, 0xcf, 0xa0, 0x7e, ++ 0xab, 0xad, 0x5a, 0x7f, 0x0f, 0xf6, 0xd8, 0x16, 0xed, 0x91, 0x67, 0x7f, ++ 0x81, 0x1a, 0xa8, 0xb8, 0x5d, 0xed, 0x15, 0x6c, 0x62, 0x8c, 0xbe, 0x8d, ++ 0xfd, 0xbe, 0x87, 0x35, 0x8f, 0x60, 0xee, 0x25, 0xec, 0x35, 0x7b, 0x65, ++ 0xaf, 0x1c, 0x7a, 0x19, 0x91, 0x0f, 0x5b, 0xdc, 0xc3, 0x47, 0xdd, 0x7d, ++ 0x47, 0x46, 0xd6, 0x3b, 0x9e, 0xad, 0x23, 0x4f, 0x36, 0x89, 0xb3, 0xc0, ++ 0xbd, 0xd3, 0xac, 0xef, 0x99, 0x4f, 0x4d, 0xc4, 0x77, 0x82, 0xe9, 0x19, ++ 0xf4, 0x2a, 0x7f, 0x43, 0x4d, 0xa9, 0xcb, 0x5c, 0x21, 0x0c, 0x27, 0xbd, ++ 0xbf, 0x42, 0x16, 0x7c, 0x5b, 0xe6, 0xdc, 0x45, 0x7c, 0xe7, 0x37, 0x53, ++ 0xd2, 0xc7, 0x6e, 0x97, 0x73, 0xac, 0xa3, 0x77, 0x72, 0x7d, 0x06, 0x7d, ++ 0x0c, 0x73, 0x38, 0x9e, 0xcb, 0x7c, 0xd7, 0x62, 0x3f, 0x4d, 0xe1, 0xb9, ++ 0x0e, 0xcf, 0x30, 0x7c, 0xd3, 0x33, 0xe1, 0x33, 0xba, 0xbc, 0xef, 0xd2, ++ 0x5f, 0x50, 0x3f, 0xf9, 0xbd, 0x52, 0x6e, 0xb8, 0xa8, 0xe9, 0x47, 0x72, ++ 0x7b, 0x81, 0x5d, 0xe5, 0x56, 0x06, 0xf3, 0x5c, 0x97, 0xcc, 0x5b, 0x1d, ++ 0xf3, 0x18, 0xb7, 0x38, 0x47, 0xfa, 0x79, 0xe8, 0x02, 0x7d, 0xd3, 0x32, ++ 0xfb, 0x2f, 0xf6, 0x52, 0xaa, 0xcf, 0xf1, 0xa8, 0x9b, 0x37, 0x1a, 0xc4, ++ 0x09, 0x83, 0xb8, 0xf9, 0x25, 0x1d, 0x3e, 0x53, 0xce, 0x26, 0x67, 0x0a, ++ 0x43, 0x60, 0x61, 0xee, 0xa4, 0xaa, 0x73, 0x86, 0xad, 0xad, 0xc2, 0x1e, ++ 0x6b, 0x24, 0x5f, 0x25, 0x4d, 0xab, 0x0b, 0x7d, 0xf3, 0x80, 0xa4, 0x16, ++ 0xe9, 0xa7, 0x57, 0xfb, 0xb8, 0xd2, 0x0b, 0xac, 0x5f, 0x54, 0x8e, 0x87, ++ 0x5c, 0xe8, 0x09, 0x96, 0x0d, 0xe2, 0x20, 0x78, 0xf5, 0x48, 0x0a, 0xfd, ++ 0xe1, 0x21, 0x2f, 0xe1, 0xf5, 0x67, 0xf0, 0x92, 0xac, 0x8e, 0x3a, 0x6b, ++ 0x19, 0x75, 0xe6, 0x1b, 0x2d, 0xea, 0x82, 0x3c, 0xf3, 0x32, 0xe7, 0xce, ++ 0xb3, 0x56, 0xc5, 0x19, 0xd0, 0x5b, 0x17, 0xd2, 0xd0, 0x61, 0x46, 0xf1, ++ 0xa9, 0x37, 0xff, 0x1d, 0x12, 0xdb, 0x51, 0x0b, 0x61, 0x2f, 0xbc, 0xb7, ++ 0x31, 0x07, 0x19, 0x32, 0xb0, 0xd3, 0xe1, 0x66, 0x54, 0xdf, 0xee, 0x83, ++ 0x4e, 0x2a, 0x8d, 0xcf, 0x92, 0x5e, 0x26, 0x0f, 0x9c, 0x40, 0xed, 0xdb, ++ 0x2b, 0xc6, 0x19, 0xc4, 0x58, 0x8b, 0xeb, 0x31, 0x5e, 0x3c, 0x18, 0xcf, ++ 0x93, 0xc6, 0xc5, 0xfe, 0xec, 0x79, 0x9c, 0xdc, 0xbe, 0x8e, 0x75, 0xfa, ++ 0x52, 0x74, 0xa6, 0xad, 0x72, 0x9b, 0x4c, 0xfe, 0xca, 0x42, 0x2f, 0x78, ++ 0xf5, 0xdb, 0x94, 0xf0, 0xdd, 0x92, 0x65, 0xf4, 0x4e, 0xa9, 0x25, 0xf6, ++ 0x05, 0x6a, 0x6f, 0xd0, 0x3b, 0xf6, 0xb7, 0x21, 0x57, 0xb5, 0x81, 0x1a, ++ 0xad, 0xb1, 0x1e, 0xb9, 0x3d, 0x8b, 0x38, 0x67, 0x6c, 0x78, 0xa8, 0x89, ++ 0xf1, 0x4d, 0xe1, 0x6f, 0x01, 0x3e, 0x3b, 0x8e, 0xfe, 0x63, 0x53, 0x82, ++ 0x17, 0xf8, 0x56, 0xc4, 0x37, 0xf6, 0x24, 0x51, 0x6d, 0x35, 0x04, 0x1f, ++ 0xd4, 0x17, 0x6d, 0x99, 0xbe, 0x52, 0xd3, 0xaf, 0x13, 0xfb, 0x36, 0xd6, ++ 0xf4, 0x49, 0x4d, 0xeb, 0xd8, 0x17, 0x58, 0xcb, 0xc6, 0x75, 0xed, 0xbb, ++ 0xec, 0x15, 0x5a, 0xac, 0x67, 0xa3, 0xba, 0x76, 0x05, 0x75, 0xed, 0x74, ++ 0xfb, 0x17, 0xd0, 0xbf, 0xa5, 0xea, 0xf3, 0xab, 0x38, 0xf1, 0x1e, 0x70, ++ 0xc2, 0xba, 0x7a, 0xaf, 0xe0, 0x32, 0x77, 0x57, 0xf0, 0x67, 0x6e, 0xa6, ++ 0x8d, 0x80, 0x9d, 0x3e, 0x6d, 0xcc, 0x7b, 0x04, 0xfa, 0x22, 0x73, 0xe5, ++ 0x36, 0x8c, 0x69, 0x3b, 0xf6, 0xfd, 0xaa, 0xee, 0x45, 0xbc, 0x75, 0xde, ++ 0x45, 0xdc, 0xa7, 0xb0, 0x11, 0xe7, 0x24, 0xe6, 0xf2, 0x7e, 0xc7, 0x98, ++ 0x03, 0x06, 0x11, 0x83, 0xeb, 0xed, 0xc8, 0x87, 0x4a, 0x1e, 0x79, 0x3a, ++ 0xc5, 0x40, 0x5e, 0x7f, 0x50, 0x57, 0xe7, 0x0d, 0x90, 0x83, 0xa8, 0xaf, ++ 0xf1, 0xfc, 0x3e, 0xa5, 0x4f, 0xe2, 0x41, 0x84, 0xe5, 0xc3, 0x31, 0x96, ++ 0x0f, 0xb5, 0xd0, 0x80, 0xc6, 0xbd, 0xe5, 0x8d, 0xf8, 0x6c, 0xa4, 0x6e, ++ 0xc4, 0xe7, 0xec, 0x2d, 0xf0, 0x79, 0x1d, 0xd6, 0x1a, 0x92, 0x5e, 0xc2, ++ 0x7c, 0x33, 0x27, 0x2b, 0x63, 0xac, 0x16, 0x76, 0x63, 0x7d, 0x4e, 0x4e, ++ 0xc0, 0x7f, 0x58, 0x6b, 0xe9, 0x8b, 0x9d, 0xeb, 0xfb, 0x53, 0x11, 0x9e, ++ 0xa7, 0x55, 0x8c, 0xea, 0x4b, 0x9d, 0x73, 0x1b, 0x31, 0x97, 0xe9, 0xb8, ++ 0x13, 0xba, 0x99, 0x4f, 0x12, 0x27, 0xba, 0x81, 0xf7, 0x5c, 0x47, 0x9f, ++ 0x61, 0x8c, 0xd0, 0xe7, 0x92, 0x18, 0xe9, 0x25, 0x96, 0x21, 0x07, 0x24, ++ 0x7c, 0xd0, 0x9f, 0xee, 0xe4, 0x3d, 0x07, 0x7d, 0x29, 0x8b, 0x75, 0x03, ++ 0xd2, 0xb5, 0x48, 0x7f, 0x62, 0x7f, 0xad, 0xf2, 0x1c, 0xe2, 0x18, 0xdf, ++ 0xcf, 0x20, 0x3f, 0xb4, 0xb8, 0xae, 0x87, 0x77, 0x4b, 0xf0, 0x15, 0x95, ++ 0x17, 0x5e, 0xd0, 0xd1, 0x0f, 0x2c, 0x37, 0xfb, 0x88, 0xdb, 0xf2, 0xcc, ++ 0x18, 0xcf, 0x58, 0x07, 0x7a, 0x0c, 0x7b, 0x25, 0x9d, 0x67, 0x8d, 0xce, ++ 0xb9, 0xac, 0xce, 0x49, 0xbe, 0x9d, 0x67, 0xf9, 0x06, 0xce, 0xc2, 0x6f, ++ 0x8e, 0x6d, 0xeb, 0x11, 0xc6, 0x05, 0x7a, 0x1a, 0xf1, 0x67, 0x20, 0x17, ++ 0x85, 0x07, 0xd1, 0x4b, 0xa0, 0x27, 0x73, 0xec, 0x5f, 0xe2, 0x4c, 0xac, ++ 0x09, 0x18, 0x4b, 0xcb, 0x4a, 0x16, 0xbc, 0xb7, 0x22, 0xd9, 0x29, 0x73, ++ 0x97, 0x3a, 0x43, 0x56, 0xed, 0x9f, 0x39, 0x16, 0xca, 0x8a, 0x57, 0xcb, ++ 0x03, 0xdf, 0xf3, 0xaf, 0x60, 0xdd, 0xa9, 0x38, 0xee, 0xd3, 0xf8, 0x3e, ++ 0xe7, 0x25, 0xbd, 0x12, 0xed, 0x1d, 0x86, 0x1f, 0xc0, 0x7f, 0xca, 0xf2, ++ 0x17, 0x85, 0x8b, 0x0b, 0x9e, 0xc2, 0x01, 0x75, 0xef, 0x70, 0xaa, 0x55, ++ 0x4e, 0x2b, 0xdc, 0x5c, 0xea, 0xe4, 0x25, 0x31, 0xaf, 0x4e, 0x3e, 0xc4, ++ 0x10, 0x85, 0x4f, 0xf6, 0xbc, 0xc2, 0x27, 0xd2, 0x63, 0x5d, 0x2b, 0xc1, ++ 0xd1, 0x34, 0xf0, 0x93, 0xe7, 0x24, 0x96, 0xf6, 0xc7, 0xe3, 0x27, 0xd3, ++ 0x8c, 0x89, 0xd4, 0x62, 0x54, 0xaf, 0x52, 0x97, 0x5d, 0xc7, 0x7a, 0xc5, ++ 0x5d, 0x8c, 0xe4, 0x9a, 0x94, 0x7f, 0x2a, 0x79, 0xae, 0xe5, 0x89, 0xf9, ++ 0x33, 0x37, 0xa3, 0xb3, 0x3a, 0xe8, 0xfe, 0x71, 0x13, 0x3a, 0xcc, 0x9f, ++ 0x21, 0x4d, 0xcf, 0x95, 0x3a, 0xb9, 0x7c, 0x25, 0x8e, 0x02, 0xc4, 0x19, ++ 0x69, 0xaf, 0xbf, 0xbb, 0xeb, 0x8c, 0xb9, 0xa4, 0x3e, 0x65, 0x5c, 0x71, ++ 0x4f, 0xc7, 0x66, 0x9f, 0x1a, 0xc5, 0x94, 0xd2, 0x29, 0xf5, 0x80, 0x1c, ++ 0xe4, 0xe4, 0x67, 0x25, 0x89, 0xbb, 0xab, 0xb1, 0xb5, 0x57, 0xf5, 0x59, ++ 0xe3, 0xc5, 0xbd, 0x0a, 0xc3, 0xae, 0x8f, 0x2d, 0xde, 0x79, 0xb2, 0x7e, ++ 0xea, 0x01, 0x66, 0x50, 0xff, 0xbc, 0xcf, 0x8a, 0x30, 0xbf, 0x72, 0x9c, ++ 0xef, 0x9f, 0xc6, 0xef, 0xcc, 0x73, 0xac, 0xf5, 0x35, 0xd4, 0x4a, 0xac, ++ 0x99, 0xc6, 0xa4, 0x9e, 0x85, 0x5e, 0x3d, 0xca, 0xb0, 0x4f, 0xae, 0xf6, ++ 0x09, 0x37, 0xab, 0x7d, 0xee, 0x34, 0x3a, 0x62, 0xf4, 0x66, 0x3d, 0x03, ++ 0xef, 0x78, 0xb4, 0xf2, 0x71, 0x2d, 0xee, 0x77, 0xd9, 0x23, 0x5c, 0x0e, ++ 0x53, 0xaa, 0x5f, 0x20, 0x1e, 0xb1, 0x4f, 0xf8, 0x1d, 0xf4, 0xde, 0xa7, ++ 0xde, 0x83, 0x55, 0x3e, 0xa9, 0x17, 0xea, 0xc3, 0x8c, 0xf1, 0x25, 0x91, ++ 0xfb, 0xc5, 0xb4, 0xba, 0x07, 0xd1, 0x4b, 0x89, 0x4c, 0x52, 0x7d, 0x91, ++ 0x75, 0x9f, 0x15, 0xe7, 0xd3, 0xfd, 0x78, 0xde, 0x1f, 0xfb, 0x40, 0x72, ++ 0x16, 0xa5, 0x57, 0xec, 0x1f, 0x86, 0x33, 0xf0, 0xa9, 0x67, 0xbc, 0x44, ++ 0x56, 0xf8, 0xf6, 0x57, 0x13, 0x6c, 0x83, 0xbd, 0xdc, 0xcb, 0xa1, 0x31, ++ 0x1a, 0x40, 0x16, 0xde, 0xb9, 0x56, 0xd0, 0x7f, 0x50, 0x96, 0x69, 0x6d, ++ 0xc7, 0x95, 0x7b, 0xd6, 0xeb, 0x7b, 0x0d, 0xda, 0x8f, 0xf6, 0xbd, 0x62, ++ 0x3f, 0xd4, 0x65, 0x15, 0xe3, 0x63, 0xe0, 0x7b, 0xbf, 0x4e, 0x1c, 0x14, ++ 0x33, 0x0d, 0x1b, 0x9c, 0x87, 0x8d, 0x02, 0xd4, 0x3f, 0x1f, 0xa8, 0xfe, ++ 0x51, 0x10, 0x73, 0xe3, 0x01, 0xc6, 0xde, 0x39, 0xd8, 0xd8, 0x18, 0x75, ++ 0xbc, 0xb7, 0xd4, 0x5d, 0x84, 0x89, 0xbe, 0x3c, 0xb2, 0xdd, 0x58, 0x6c, ++ 0xbb, 0xd1, 0xd6, 0xb5, 0x67, 0xb6, 0xf5, 0x87, 0xe2, 0x77, 0x9e, 0x89, ++ 0xb5, 0x90, 0xcd, 0x3a, 0x1e, 0x3a, 0x28, 0x6a, 0xd1, 0xdd, 0xe7, 0x83, ++ 0xec, 0x97, 0x6a, 0xcc, 0x77, 0xec, 0x39, 0x56, 0x3c, 0xd6, 0x7f, 0x19, ++ 0xa9, 0x45, 0xba, 0x88, 0x7a, 0x2e, 0xab, 0xc4, 0x58, 0x87, 0xcf, 0xac, ++ 0x83, 0x6e, 0x02, 0xc4, 0x5c, 0x74, 0x1f, 0x32, 0x2b, 0x69, 0x54, 0x50, ++ 0x61, 0x78, 0x9e, 0x77, 0x3c, 0x0d, 0xe6, 0x15, 0xde, 0x9f, 0x00, 0x2b, ++ 0x7a, 0x98, 0x6b, 0x92, 0xbb, 0x38, 0x53, 0x4e, 0x60, 0xcd, 0x49, 0x97, ++ 0x77, 0x67, 0x89, 0x0f, 0xb0, 0x8f, 0x67, 0xff, 0xff, 0x45, 0x58, 0xcd, ++ 0x76, 0xae, 0xe5, 0xef, 0xbf, 0x4c, 0xc8, 0x64, 0xeb, 0xa8, 0x18, 0x00, ++ 0x00, 0x00 }; + + static const u32 bnx2_TPAT_b09FwData[(0x0/4) + 1] = { 0x0 }; + static const u32 bnx2_TPAT_b09FwRodata[(0x4/4) + 1] = { + 0x00000001, 0x00000000 }; + + static struct fw_info bnx2_tpat_fw_09 = { +- /* Firmware version: 4.4.26 */ +- .ver_major = 0x4, +- .ver_minor = 0x4, +- .ver_fix = 0x1a, ++ /* Firmware version: 5.0.0j */ ++ .ver_major = 0x5, ++ .ver_minor = 0x0, ++ .ver_fix = 0x0, + + .start_addr = 0x08000488, + + .text_addr = 0x08000400, +- .text_len = 0x1514, ++ .text_len = 0x18a4, + .text_index = 0x0, + .gz_text = bnx2_TPAT_b09FwText, + .gz_text_len = sizeof(bnx2_TPAT_b09FwText), +@@ -3709,871 +3812,885 @@ + .data_index = 0x0, + .data = bnx2_TPAT_b09FwData, + +- .sbss_addr = 0x08001940, +- .sbss_len = 0x48, +- .sbss_index = 0x0, +- +- .bss_addr = 0x08001988, +- .bss_len = 0x12b4, +- .bss_index = 0x0, +- +- .rodata_addr = 0x08001914, ++ .sbss_addr = 0x08001cc0, ++ .sbss_len = 0x40, ++ .sbss_index = 0x0, ++ ++ .bss_addr = 0x08001d00, ++ .bss_len = 0x344, ++ .bss_index = 0x0, ++ ++ .rodata_addr = 0x08001ca4, + .rodata_len = 0x4, + .rodata_index = 0x0, + .rodata = bnx2_TPAT_b09FwRodata, + }; + + static u8 bnx2_TXP_b09FwText[] = { +- 0xc5, 0x7b, 0x7b, 0x74, 0x1c, 0x55, 0x9a, 0xdf, 0xef, 0x56, 0x3f, 0x54, +- 0xdd, 0x6a, 0xb5, 0x4a, 0x72, 0xdb, 0x6e, 0xed, 0x68, 0xc6, 0x5d, 0xee, +- 0x6a, 0xb9, 0xb1, 0x84, 0x5d, 0x2d, 0xb5, 0xec, 0x66, 0x5d, 0xb1, 0x7b, +- 0x8c, 0xb0, 0x65, 0x10, 0x3b, 0xc2, 0xeb, 0x9d, 0x88, 0x09, 0x27, 0xf4, +- 0x18, 0x19, 0x64, 0x63, 0x40, 0x30, 0x64, 0xa3, 0xd9, 0x25, 0xeb, 0x1a, +- 0xf9, 0x81, 0x1f, 0xad, 0xee, 0xd6, 0xc3, 0xc8, 0xec, 0xd9, 0x13, 0x64, +- 0x49, 0xb6, 0xcc, 0xd0, 0x0f, 0x33, 0xc0, 0xcc, 0x30, 0x27, 0x13, 0x77, +- 0x8c, 0x01, 0x03, 0x63, 0x98, 0xdd, 0x6c, 0x92, 0x99, 0x3d, 0x49, 0xd6, +- 0x07, 0xf3, 0xb0, 0xc1, 0x60, 0x32, 0x43, 0x12, 0xb1, 0xcb, 0x4c, 0xe5, +- 0xfb, 0xaa, 0x25, 0x63, 0x58, 0xb2, 0x9b, 0x6c, 0xfe, 0x88, 0xce, 0xd1, +- 0xe9, 0xee, 0xaa, 0x5b, 0xf7, 0x7e, 0xef, 0xef, 0xf7, 0x7d, 0xf7, 0x56, +- 0x04, 0xf0, 0x62, 0xee, 0xaf, 0x86, 0xfe, 0xe3, 0xfd, 0x03, 0x0f, 0xb7, +- 0xae, 0x88, 0xaf, 0xa0, 0xaf, 0x6d, 0x58, 0xec, 0x74, 0xf2, 0xcd, 0x55, +- 0x02, 0x48, 0xbd, 0x87, 0x7f, 0xd4, 0xdf, 0x57, 0xff, 0x71, 0x8f, 0xc1, +- 0x01, 0x28, 0xf3, 0x34, 0xf1, 0x3f, 0x64, 0xc9, 0x30, 0xd7, 0xac, 0xd7, +- 0x20, 0x3b, 0x8c, 0xc4, 0xda, 0xbb, 0x34, 0x20, 0x99, 0x6f, 0x0e, 0xdd, +- 0x88, 0xdf, 0x58, 0x66, 0xc0, 0x09, 0xbe, 0xfe, 0x55, 0xe3, 0xd3, 0x5d, +- 0x3f, 0x5d, 0xad, 0x7e, 0x34, 0xe1, 0x80, 0xac, 0x18, 0x63, 0x50, 0x9a, +- 0x20, 0x37, 0xd2, 0x33, 0x7f, 0xb6, 0xec, 0x79, 0x27, 0xfc, 0xf3, 0x73, +- 0xc1, 0x74, 0x19, 0x3a, 0x76, 0x67, 0xfb, 0x31, 0x13, 0x07, 0x2e, 0xa6, +- 0x23, 0xfa, 0x6e, 0x20, 0x27, 0x19, 0x91, 0xd0, 0x69, 0x84, 0x30, 0x9d, +- 0x87, 0x59, 0x65, 0x68, 0xd8, 0x5f, 0x0a, 0xe1, 0x52, 0xfa, 0xb7, 0x56, +- 0xc8, 0xd5, 0x8f, 0xb7, 0xe2, 0x90, 0x83, 0xc6, 0x23, 0x08, 0x66, 0x21, +- 0xd7, 0x18, 0x03, 0x28, 0x0c, 0x01, 0x7b, 0xd3, 0x6a, 0x3f, 0xa0, 0xf6, +- 0x14, 0x45, 0xf8, 0xec, 0x09, 0xa8, 0xdd, 0x0d, 0x8e, 0xe6, 0xd4, 0xed, +- 0x42, 0x4d, 0xee, 0x14, 0x90, 0x05, 0x8d, 0x5d, 0x9e, 0xe7, 0xcf, 0x01, +- 0x44, 0xf3, 0x32, 0xce, 0x3b, 0x78, 0x59, 0x83, 0xe4, 0x2c, 0xe0, 0xd4, +- 0x74, 0xec, 0xcd, 0xc2, 0x74, 0x1a, 0x02, 0xbb, 0xe3, 0x11, 0x65, 0x0a, +- 0x7c, 0x3f, 0x84, 0x41, 0x7b, 0x9c, 0x4a, 0x1c, 0x5b, 0xd6, 0x1e, 0xdd, +- 0xb2, 0x8e, 0xe9, 0x55, 0x30, 0x15, 0x35, 0x08, 0x08, 0x0c, 0xea, 0x12, +- 0x92, 0xca, 0xfa, 0x90, 0x13, 0x6a, 0x70, 0x1b, 0xfe, 0x96, 0xf8, 0x4d, +- 0x46, 0x5d, 0xa8, 0x8c, 0x4f, 0xa1, 0x0a, 0x65, 0xa5, 0x22, 0xb1, 0xc9, +- 0xb4, 0x65, 0xbd, 0xa4, 0x39, 0x71, 0x8c, 0x64, 0x33, 0x98, 0xff, 0x5b, +- 0xab, 0x4c, 0x72, 0xd9, 0xa3, 0xcd, 0xaf, 0x2f, 0x63, 0x42, 0xb1, 0xac, +- 0x29, 0xba, 0xb7, 0x2f, 0x3f, 0x2f, 0x63, 0xcb, 0x92, 0x34, 0xcb, 0xba, +- 0x4b, 0xfb, 0x1b, 0x6b, 0xeb, 0xe7, 0xc6, 0xc6, 0xf0, 0xfd, 0x9c, 0x82, +- 0xa7, 0xb2, 0x49, 0xe4, 0xd3, 0x16, 0x1c, 0x86, 0x13, 0x7d, 0x43, 0x21, +- 0xec, 0x2c, 0x74, 0xa0, 0x90, 0x56, 0x53, 0xe7, 0xe9, 0xb9, 0xad, 0x71, +- 0x0d, 0xf7, 0x15, 0x3a, 0x31, 0x93, 0x86, 0xe5, 0x31, 0xb4, 0xb2, 0x47, +- 0x44, 0x71, 0x4f, 0xa1, 0x0b, 0xc5, 0xb4, 0x76, 0x76, 0x50, 0x44, 0x06, +- 0x1a, 0x1c, 0x4e, 0x3c, 0x50, 0x68, 0xc1, 0xfd, 0x85, 0x04, 0x3d, 0x63, +- 0xe1, 0xe6, 0x58, 0x23, 0x8d, 0x6f, 0xc5, 0x93, 0x63, 0x96, 0x15, 0x8d, +- 0x29, 0xe8, 0x2b, 0xe8, 0x98, 0xc9, 0x49, 0x48, 0x1d, 0x73, 0x22, 0x75, +- 0x14, 0xb8, 0xe7, 0x68, 0x2b, 0xa6, 0x72, 0x16, 0xb6, 0xea, 0x83, 0x0d, +- 0x12, 0x5c, 0x48, 0x29, 0x02, 0x2e, 0xcd, 0x8f, 0x6d, 0x4a, 0x85, 0xf6, +- 0xf3, 0x0e, 0x81, 0x1d, 0x47, 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0x82, 0x88, 0x74, 0xbe, 0x89, 0x48, 0xcf, 0x05, +- 0x8a, 0x61, 0x4f, 0x95, 0xf8, 0x9c, 0xf0, 0x23, 0xf8, 0xeb, 0xe1, 0x85, +- 0x38, 0x35, 0xd5, 0x3f, 0xd7, 0x13, 0x83, 0xf7, 0xfa, 0x55, 0x06, 0x8e, +- 0x0f, 0x87, 0xc8, 0x7e, 0xdc, 0x14, 0xd7, 0x65, 0x48, 0x4d, 0x90, 0xeb, +- 0xa8, 0x4e, 0x88, 0x3d, 0x66, 0x59, 0x2b, 0x9a, 0x2a, 0x35, 0xcf, 0x8a, +- 0xe9, 0x6b, 0xdf, 0x71, 0x98, 0xef, 0xf7, 0x04, 0x49, 0x7f, 0xcd, 0xa9, +- 0x1d, 0xe2, 0x8c, 0x65, 0xfe, 0x81, 0x20, 0x9e, 0x7b, 0x6a, 0xe0, 0x65, +- 0xbe, 0x65, 0xec, 0x1e, 0xe5, 0x3e, 0x1c, 0xeb, 0x0d, 0xde, 0xce, 0x38, +- 0xef, 0x97, 0xb3, 0x8e, 0xca, 0xde, 0x0d, 0x71, 0x8a, 0x89, 0xc2, 0x4f, +- 0x78, 0xca, 0xf4, 0x74, 0x50, 0x7e, 0xaa, 0x1a, 0xe6, 0xf7, 0x2d, 0x7c, +- 0x38, 0x40, 0x71, 0xe3, 0xb2, 0x5e, 0x8d, 0x43, 0x75, 0x6a, 0x82, 0xeb, +- 0xe9, 0x27, 0x4b, 0xdc, 0x33, 0xdc, 0x89, 0xed, 0xfc, 0xbe, 0x4a, 0x69, +- 0xb5, 0x7d, 0xb6, 0x90, 0xae, 0x11, 0x36, 0x60, 0x3a, 0xe6, 0xd7, 0xef, +- 0xc4, 0x92, 0x21, 0xd6, 0xe3, 0xc7, 0x6b, 0x82, 0x24, 0xa3, 0xc7, 0xc9, +- 0x2e, 0x24, 0xa3, 0x03, 0xf2, 0x90, 0x65, 0xdd, 0x18, 0xbf, 0x76, 0x0e, +- 0xad, 0xff, 0x82, 0x83, 0xea, 0x3b, 0x07, 0xef, 0xeb, 0xa9, 0x89, 0x13, +- 0xe2, 0xda, 0x39, 0x0b, 0x35, 0xdc, 0x4f, 0x34, 0xa7, 0x2a, 0x79, 0xe9, +- 0x38, 0xe5, 0xa5, 0x97, 0x73, 0xec, 0x23, 0xf5, 0x06, 0xfb, 0x88, 0x44, +- 0xb1, 0x76, 0x7d, 0x3a, 0x84, 0x0b, 0x3a, 0x34, 0x37, 0x62, 0x44, 0x77, +- 0xa4, 0xbb, 0x63, 0x0e, 0xf3, 0xb9, 0x28, 0xfe, 0x4f, 0xe5, 0x78, 0xaf, +- 0x4d, 0xa0, 0x46, 0x63, 0x1b, 0xb0, 0x73, 0x01, 0xc5, 0xb4, 0x7e, 0xd4, +- 0xae, 0x06, 0x2e, 0x0d, 0xf1, 0xfe, 0x8c, 0x86, 0x03, 0xa5, 0x01, 0xd1, +- 0x30, 0xf4, 0x5b, 0x2b, 0x54, 0x35, 0xbf, 0x07, 0xf8, 0x30, 0xef, 0x01, +- 0x92, 0x0d, 0xf4, 0xdb, 0xe7, 0x7c, 0xde, 0x4c, 0xf3, 0x39, 0x9f, 0x70, +- 0x68, 0x13, 0xf9, 0x4e, 0x2f, 0x9a, 0xf5, 0x69, 0xc2, 0xce, 0xb3, 0x44, +- 0x67, 0x93, 0xa8, 0xec, 0x73, 0x45, 0xe6, 0xf6, 0xe9, 0x96, 0xe5, 0x3b, +- 0x45, 0x4d, 0x81, 0x69, 0x0a, 0x10, 0x4d, 0x1d, 0xa2, 0xfa, 0xd8, 0x06, +- 0xe1, 0x3b, 0xd6, 0x25, 0xa4, 0x02, 0xc7, 0xe4, 0x3a, 0x63, 0x4f, 0x8e, +- 0xf3, 0xd9, 0x66, 0xe1, 0x3c, 0xba, 0x45, 0x78, 0x0b, 0x3d, 0xc2, 0x7f, +- 0xcc, 0xc4, 0xfd, 0xf1, 0x2e, 0x9c, 0x1b, 0xe6, 0xb3, 0x6c, 0xf7, 0x89, +- 0x9a, 0xb9, 0xbd, 0x39, 0x6f, 0xa1, 0xd1, 0x5f, 0x48, 0x73, 0x7f, 0xf7, +- 0xe3, 0x35, 0xe9, 0xa1, 0x45, 0xfe, 0xa7, 0xc6, 0x02, 0xfe, 0x27, 0xc7, +- 0xd4, 0xfe, 0x7d, 0xc2, 0xb2, 0x76, 0xc6, 0xfe, 0x03, 0xeb, 0xd0, 0x6a, +- 0x8e, 0x55, 0xf0, 0xc1, 0x6e, 0x92, 0xc7, 0x36, 0xca, 0x2d, 0x93, 0x7a, +- 0xf3, 0x1c, 0x16, 0x51, 0x53, 0xfc, 0xee, 0x1b, 0xfd, 0x77, 0x73, 0x6e, +- 0xe3, 0x7d, 0x4d, 0x67, 0x3b, 0x28, 0xee, 0x7e, 0xc6, 0x6b, 0xcd, 0x10, +- 0x9f, 0x51, 0xeb, 0x87, 0xff, 0x4b, 0xf6, 0xf5, 0xce, 0x7d, 0xb6, 0xaf, +- 0x97, 0x78, 0x52, 0xa8, 0xe5, 0x19, 0xe2, 0xb7, 0xca, 0xf1, 0xb9, 0x3d, +- 0xbd, 0xb9, 0xfd, 0xbc, 0x4e, 0xe1, 0x2b, 0x70, 0x7d, 0x1e, 0x30, 0x5e, +- 0x1f, 0xea, 0x10, 0xde, 0x63, 0xc3, 0x94, 0x1f, 0x37, 0x10, 0xcf, 0x7c, +- 0x76, 0xac, 0x4b, 0xf8, 0x0b, 0x9b, 0x85, 0x8f, 0xf8, 0xac, 0x26, 0x3e, +- 0x71, 0xcc, 0x23, 0xbc, 0xc4, 0xa3, 0x87, 0x78, 0xf4, 0xce, 0xf1, 0xe8, +- 0x29, 0x04, 0xfd, 0xe9, 0x74, 0xbd, 0xff, 0xd1, 0x31, 0xc5, 0xbf, 0x6f, +- 0xcc, 0xb2, 0xde, 0xd7, 0x15, 0x3f, 0xf3, 0xf5, 0xaa, 0xfe, 0x45, 0xbe, +- 0x6e, 0x20, 0xbe, 0x2a, 0x7b, 0xb1, 0xa4, 0xc3, 0x14, 0xeb, 0x90, 0xcf, +- 0x71, 0xcc, 0xf3, 0x75, 0x30, 0xcd, 0xfb, 0x95, 0xbc, 0x6f, 0x39, 0x20, +- 0x56, 0x10, 0x5f, 0x65, 0xe2, 0x6b, 0xe5, 0x97, 0xf0, 0xf5, 0xe1, 0x35, +- 0x7c, 0xbd, 0xfa, 0xf7, 0xf2, 0xe5, 0x11, 0xcb, 0x87, 0x39, 0x0e, 0xdd, +- 0x66, 0xc8, 0xc3, 0x16, 0x61, 0x47, 0x07, 0xbe, 0x3f, 0x05, 0x14, 0xb3, +- 0xbb, 0x20, 0x53, 0xbc, 0x39, 0x1d, 0x8f, 0x84, 0x5e, 0xa1, 0x7a, 0x72, +- 0xba, 0xe4, 0x15, 0xcb, 0xec, 0x3d, 0x59, 0xac, 0x90, 0x89, 0xa6, 0x19, +- 0xfb, 0x5d, 0x33, 0xe8, 0xb5, 0x1a, 0xeb, 0x52, 0x3b, 0xbb, 0x15, 0x91, +- 0x72, 0xc4, 0xd1, 0x25, 0x12, 0x05, 0xde, 0x83, 0xdd, 0x22, 0x56, 0xda, +- 0xfb, 0xaf, 0x9d, 0xe2, 0xfa, 0x42, 0x87, 0x68, 0x21, 0xbb, 0x68, 0x3e, +- 0xc6, 0xe7, 0xc1, 0x36, 0x8b, 0xe6, 0x39, 0x79, 0x2c, 0x27, 0x79, 0x0c, +- 0x7d, 0x4e, 0x1e, 0x1b, 0x6c, 0x79, 0xfc, 0x4c, 0xbf, 0x78, 0x4d, 0x0f, +- 0x8d, 0xeb, 0x2a, 0xca, 0x86, 0x54, 0x3b, 0xd5, 0xce, 0xd5, 0x4e, 0x6f, +- 0xc5, 0xf8, 0x9c, 0x8f, 0x69, 0xd5, 0x68, 0x08, 0x39, 0x0d, 0xb5, 0xe7, +- 0xb4, 0xd0, 0x52, 0xf7, 0x89, 0xe4, 0x26, 0x1f, 0xd5, 0x3f, 0x3b, 0x62, +- 0x91, 0xe4, 0x72, 0x11, 0x49, 0x38, 0x05, 0xe7, 0x15, 0x5d, 0xae, 0x2a, +- 0x9a, 0xd8, 0x47, 0xf1, 0xed, 0xc5, 0x9c, 0x44, 0xd8, 0x81, 0xdf, 0x3f, +- 0x73, 0xe2, 0x46, 0x82, 0x12, 0x4f, 0x10, 0xee, 0x78, 0x3c, 0xdb, 0x87, +- 0x27, 0xf2, 0xbd, 0x78, 0x3c, 0xff, 0x77, 0xde, 0xb5, 0x91, 0xbd, 0x46, +- 0x63, 0xa2, 0x72, 0x16, 0xe1, 0xe3, 0xc4, 0x75, 0x11, 0x96, 0xcd, 0x89, +- 0x16, 0x39, 0xc2, 0xb5, 0xae, 0xf3, 0x77, 0xdf, 0xd5, 0xd8, 0x17, 0x7b, +- 0x56, 0xbd, 0x64, 0x63, 0x91, 0x93, 0x6d, 0xc7, 0xec, 0x33, 0x52, 0xe5, +- 0x95, 0x7b, 0xec, 0x77, 0x41, 0x7d, 0xab, 0xef, 0xd2, 0xd8, 0x1f, 0x4e, +- 0xc4, 0xd7, 0xdb, 0xf9, 0xb5, 0x71, 0x6d, 0xe5, 0x3d, 0x99, 0xe0, 0xda, +- 0x4a, 0xaf, 0x26, 0xb0, 0x36, 0x6a, 0x7f, 0x86, 0xd6, 0x56, 0xf6, 0xba, +- 0xf5, 0xb5, 0x4d, 0xf6, 0x67, 0x74, 0x6d, 0xc5, 0xa7, 0xb4, 0xb5, 0x9a, +- 0xfd, 0x19, 0x5f, 0x5b, 0xc9, 0xcb, 0x2d, 0x6b, 0x97, 0x5e, 0x7d, 0xbf, +- 0x86, 0xff, 0xfe, 0x17, 0x9f, 0xed, 0x4e, 0xb2, 0x20, 0x3b, 0x00, 0x00, +- 0x00 }; ++ 0xbd, 0x7b, 0x7f, 0x70, 0x5c, 0xd5, 0x95, 0xe6, 0x77, 0xbb, 0x5b, 0xd2, ++ 0xeb, 0x56, 0xab, 0xd5, 0x92, 0xdb, 0xa6, 0x35, 0xa3, 0xc4, 0xfd, 0xe8, ++ 0xd7, 0x72, 0x83, 0x84, 0x79, 0x2d, 0xb7, 0x4c, 0x33, 0x69, 0xc5, 0x8d, ++ 0x31, 0x46, 0x0e, 0x9a, 0x41, 0x61, 0x9d, 0x19, 0x91, 0xa2, 0x2a, 0x1a, ++ 0x23, 0x83, 0x30, 0x06, 0x44, 0x60, 0x32, 0x62, 0x96, 0x8d, 0x5e, 0xe4, ++ 0x1f, 0x18, 0xbb, 0xa5, 0xd6, 0x2f, 0xc7, 0x78, 0x36, 0x55, 0x08, 0x49, ++ 0xb6, 0x6c, 0xe8, 0x56, 0xf3, 0x33, 0x81, 0xaa, 0x9d, 0x42, 0x6b, 0x0c, ++ 0x38, 0x09, 0x04, 0x26, 0x33, 0xbb, 0xc5, 0xcc, 0x66, 0x13, 0x2d, 0xe6, ++ 0x87, 0x0d, 0x06, 0x0c, 0x93, 0xd9, 0xc8, 0x3b, 0x24, 0x6f, 0xbf, 0xf3, ++ 0x5a, 0x32, 0x0e, 0x4b, 0xd5, 0xd6, 0xe6, 0x8f, 0x75, 0x95, 0xfc, 0xba, ++ 0xdf, 0xbb, 0xef, 0xde, 0x73, 0xce, 0x3d, 0xe7, 0xfb, 0xce, 0xb9, 0xf7, ++ 0xf6, 0xa5, 0x80, 0x0f, 0x8b, 0xff, 0xaa, 0xf8, 0xd7, 0xd2, 0xdb, 0x77, ++ 0xaf, 0xb9, 0xda, 0x5c, 0xcd, 0x8f, 0xdb, 0xf8, 0x57, 0x26, 0x0f, 0xd7, ++ 0x2a, 0xa0, 0xeb, 0x3d, 0xfc, 0x41, 0xff, 0x56, 0xfc, 0x61, 0xaf, 0x61, ++ 0xcf, 0xb2, 0xd2, 0xf5, 0x17, 0x65, 0x9f, 0xdd, 0x73, 0x03, 0xc1, 0x25, ++ 0x39, 0xe5, 0x0f, 0x9a, 0x2b, 0x6d, 0x7d, 0x65, 0xbd, 0x01, 0xcd, 0x9d, ++ 0x4e, 0x7e, 0xf5, 0x66, 0x03, 0xc8, 0xe4, 0x1b, 0x23, 0x57, 0xe3, 0xb7, ++ 0xb6, 0x15, 0xf2, 0x40, 0xee, 0x7f, 0x29, 0xfd, 0x69, 0xff, 0xdf, 0x5d, ++ 0xa1, 0x9f, 0x9d, 0x70, 0x43, 0x0b, 0xa6, 0x8f, 0x20, 0xd8, 0x00, 0xad, ++ 0x9e, 0xef, 0xfc, 0x60, 0xd5, 0xe5, 0x1e, 0x04, 0x96, 0xfa, 0x82, 0x55, ++ 0x96, 0xce, 0x60, 0x47, 0xae, 0x17, 0x47, 0x92, 0x40, 0xc5, 0x60, 0xcc, ++ 0xdc, 0x01, 0x0c, 0xbb, 0xd2, 0xb1, 0xc8, 0x31, 0x44, 0x30, 0x9d, 0x4f, ++ 0xe1, 0x81, 0x22, 0x2c, 0x4f, 0x3a, 0x82, 0x07, 0xb3, 0xbf, 0xb3, 0x23, ++ 0x8e, 0x44, 0xbd, 0xd8, 0xc9, 0xb6, 0xbb, 0xb2, 0xd0, 0xc2, 0xe9, 0xfb, ++ 0x11, 0xce, 0x41, 0xab, 0x4a, 0xf7, 0xa1, 0x30, 0x18, 0x3d, 0x31, 0x03, ++ 0xbd, 0xa3, 0xce, 0xad, 0xf7, 0x02, 0x8d, 0x5d, 0x37, 0x2a, 0xbd, 0x73, ++ 0x56, 0xe9, 0xa9, 0xed, 0x0a, 0x9a, 0x62, 0xbb, 0x4b, 0xf3, 0x72, 0xed, ++ 0xc3, 0xaa, 0xbc, 0x86, 0x79, 0xb7, 0xf4, 0x73, 0x15, 0xed, 0xaf, 0xe0, ++ 0x31, 0x32, 0xd8, 0x95, 0x93, 0x31, 0x14, 0x76, 0x24, 0x63, 0xc1, 0x29, ++ 0xc8, 0xf3, 0x08, 0x06, 0x9c, 0x76, 0x3a, 0xb5, 0xb6, 0xed, 0x9d, 0xa6, ++ 0x6d, 0x1f, 0x32, 0x2b, 0x60, 0x05, 0xf5, 0x30, 0xa0, 0x30, 0x60, 0xba, ++ 0x90, 0x09, 0xae, 0x8f, 0x78, 0xa0, 0x87, 0xb7, 0xe2, 0xdf, 0xa8, 0x73, ++ 0x26, 0x5e, 0x86, 0x52, 0xfb, 0x2e, 0x54, 0x60, 0x2e, 0x58, 0xb2, 0xda, ++ 0x64, 0xd6, 0xb6, 0x5f, 0x32, 0x3c, 0x38, 0x44, 0xfb, 0x0c, 0xe4, 0xff, ++ 0xcd, 0x9e, 0xa3, 0x6d, 0x76, 0x1a, 0x4b, 0xe3, 0x6b, 0x98, 0x08, 0xda, ++ 0xf6, 0x14, 0x9f, 0xed, 0xce, 0x2f, 0xd9, 0xd9, 0xb6, 0x5d, 0x86, 0x6d, ++ 0xdf, 0x6c, 0xfc, 0x2f, 0x7b, 0xcb, 0xef, 0xb5, 0x4d, 0xe0, 0xd1, 0xe1, ++ 0x20, 0x1e, 0xcb, 0x65, 0x90, 0xcf, 0xda, 0x70, 0xa7, 0x3d, 0xe8, 0x19, ++ 0x8c, 0x60, 0x7b, 0x61, 0x03, 0x0a, 0x59, 0xbd, 0x6b, 0x9e, 0xef, 0x6d, ++ 0x49, 0x1a, 0xb8, 0xa3, 0xd0, 0x86, 0x99, 0x2c, 0x6c, 0x6f, 0xda, 0x98, ++ 0xf3, 0xaa, 0x38, 0x6e, 0x2d, 0xb4, 0x63, 0x36, 0x6b, 0x9c, 0x18, 0x50, ++ 0xb1, 0xbe, 0x3a, 0xb7, 0x07, 0x77, 0x15, 0x9a, 0x70, 0x67, 0x21, 0xc5, ++ 0x77, 0x6c, 0x7c, 0x2d, 0x51, 0xcf, 0xf6, 0xcd, 0x38, 0x3a, 0x6e, 0xdb, ++ 0xf1, 0x44, 0x10, 0x3d, 0x05, 0x13, 0x33, 0xc3, 0x2e, 0x74, 0x1d, 0xf2, ++ 0xa0, 0xeb, 0x11, 0xe0, 0xd6, 0x47, 0x9a, 0x31, 0x35, 0x6c, 0x63, 0x8b, ++ 0x39, 0x50, 0xe7, 0x42, 0x19, 0xba, 0x82, 0x0a, 0x65, 0x46, 0x00, 0x5b, ++ 0x83, 0x25, 0xd9, 0xe7, 0xdd, 0x0a, 0xdb, 0x1e, 0x89, 0xe3, 0x8d, 0xac, ++ 0x85, 0xaf, 0xb5, 0x84, 0xd1, 0x57, 0x08, 0xe1, 0xb5, 0x6c, 0x88, 0x63, ++ 0x98, 0xf8, 0x59, 0x56, 0xe3, 0x38, 0x4d, 0x38, 0x9e, 0x95, 0x36, 0xd2, ++ 0xd6, 0x8f, 0xee, 0x42, 0x3d, 0x5e, 0xcd, 0x86, 0x39, 0x66, 0x08, 0x3f, ++ 0x66, 0xbb, 0xdb, 0x0a, 0x06, 0x4e, 0xb0, 0x5d, 0x4f, 0x21, 0x82, 0x97, ++ 0xb3, 0x7e, 0xca, 0x1a, 0xc2, 0xb1, 0x6c, 0x2f, 0x76, 0x64, 0x1b, 0x4f, ++ 0x5c, 0x4d, 0x1b, 0x46, 0x1c, 0x2f, 0x94, 0x7b, 0x6f, 0xd9, 0xed, 0x21, ++ 0xc7, 0x55, 0x38, 0xce, 0xd2, 0xb8, 0xbd, 0x18, 0xc8, 0xfe, 0x64, 0x31, ++ 0x7e, 0x4c, 0x3c, 0x38, 0xbc, 0x60, 0xff, 0xdd, 0xaa, 0x7a, 0x1c, 0xc9, ++ 0x01, 0x47, 0xa7, 0x80, 0xa9, 0x9c, 0x65, 0x57, 0xa5, 0x6d, 0x7b, 0xb2, ++ 0xa5, 0x89, 0xf6, 0x32, 0x3a, 0xb7, 0xb0, 0xd5, 0x63, 0x45, 0x0f, 0xf0, ++ 0x88, 0xde, 0x39, 0x07, 0x17, 0x26, 0x66, 0x3c, 0x28, 0x1f, 0xd4, 0xdb, ++ 0x26, 0xa0, 0x9f, 0xb8, 0x95, 0x11, 0x76, 0x28, 0xa7, 0x77, 0x58, 0xe8, ++ 0xb7, 0xc3, 0xe9, 0x86, 0x48, 0x93, 0xdb, 0x46, 0x80, 0xbe, 0x90, 0x6d, ++ 0xb2, 0xed, 0xea, 0x2b, 0x6c, 0xfb, 0xd5, 0x16, 0xd8, 0xae, 0xb4, 0x71, ++ 0xa2, 0x08, 0x63, 0xee, 0x03, 0x18, 0x7d, 0xc7, 0x30, 0xf7, 0x25, 0x3f, ++ 0x62, 0x3d, 0x51, 0x77, 0xac, 0x77, 0x81, 0xef, 0x56, 0x15, 0xe8, 0xce, ++ 0xd4, 0xc5, 0x18, 0x04, 0x0a, 0x45, 0x0d, 0x1e, 0xea, 0xd3, 0x34, 0x68, ++ 0xdb, 0x1e, 0xc3, 0x0f, 0x3f, 0xed, 0x7b, 0xed, 0x7e, 0xdb, 0x7e, 0xc7, ++ 0x0c, 0xa2, 0x9c, 0x73, 0x73, 0xcd, 0x88, 0x8d, 0x49, 0xf3, 0x18, 0xed, ++ 0xa9, 0xd0, 0xd5, 0x91, 0xe4, 0x3b, 0x21, 0xb6, 0x4f, 0xe1, 0xda, 0xc1, ++ 0x30, 0x1e, 0xcd, 0x69, 0xf8, 0xbb, 0x55, 0x71, 0x54, 0xb2, 0x2f, 0x1f, ++ 0x6d, 0x55, 0x41, 0xfb, 0xa1, 0x40, 0x77, 0x2b, 0x94, 0xfc, 0x11, 0x85, ++ 0x79, 0xea, 0x18, 0xc6, 0x93, 0xc5, 0x10, 0x9e, 0x28, 0x06, 0xf1, 0x78, ++ 0xb1, 0x1e, 0xcf, 0x17, 0x4d, 0x3c, 0x34, 0xac, 0xef, 0x99, 0x83, 0x8d, ++ 0xaa, 0x74, 0x3f, 0xaa, 0xd7, 0x00, 0xaf, 0x4d, 0x24, 0x30, 0x34, 0x6c, ++ 0xdb, 0x79, 0xca, 0xed, 0xa3, 0x1e, 0x3f, 0x9b, 0xf8, 0x32, 0x0e, 0x8f, ++ 0x7b, 0x10, 0x99, 0x0c, 0xe1, 0xb1, 0xac, 0x07, 0x97, 0x0c, 0xe9, 0xd6, ++ 0x04, 0x8c, 0xf8, 0x76, 0x65, 0x64, 0x2e, 0x55, 0xfa, 0xb0, 0x85, 0x58, ++ 0xa4, 0x4c, 0xb9, 0xd0, 0x70, 0xd8, 0x03, 0x63, 0x36, 0x82, 0xb2, 0x06, ++ 0x0d, 0x46, 0xc3, 0x77, 0x80, 0x80, 0x0b, 0xe5, 0x86, 0x89, 0x6b, 0x47, ++ 0xe3, 0xbc, 0x17, 0xe2, 0x3d, 0x7c, 0xb9, 0x02, 0xee, 0x15, 0x6e, 0xd0, ++ 0x76, 0x86, 0x1b, 0x19, 0x8f, 0x6d, 0xbb, 0x8d, 0x66, 0xdc, 0xf8, 0x7d, ++ 0xdb, 0x8e, 0xae, 0x91, 0xf6, 0x41, 0x44, 0x67, 0x69, 0x87, 0x06, 0xca, ++ 0x95, 0xa3, 0x9c, 0x39, 0xca, 0x99, 0xa3, 0x9c, 0x39, 0x37, 0xfd, 0x46, ++ 0x37, 0x65, 0xfe, 0xe0, 0x8b, 0x50, 0xc7, 0x37, 0x9c, 0xb9, 0x7a, 0xa2, ++ 0x18, 0xa6, 0x0e, 0x11, 0x47, 0x87, 0xa3, 0xc3, 0x0a, 0x2e, 0x43, 0xef, ++ 0x98, 0xc7, 0x3a, 0x44, 0x13, 0x7a, 0x66, 0x02, 0x19, 0xbe, 0xa7, 0xef, ++ 0xb1, 0xa0, 0xb7, 0xcd, 0xd1, 0x07, 0xb6, 0x04, 0x53, 0x98, 0xc9, 0x95, ++ 0xa1, 0xd2, 0xd0, 0x23, 0x9c, 0xb3, 0xf8, 0x1c, 0x96, 0xe1, 0xf6, 0x20, ++ 0xfb, 0x74, 0xf9, 0x55, 0x09, 0x4b, 0xee, 0x47, 0x6c, 0xd4, 0x85, 0x69, ++ 0xd3, 0xcd, 0x18, 0x35, 0xe1, 0x6e, 0xe0, 0x70, 0xb3, 0x49, 0x5e, 0xd9, ++ 0x7f, 0x8e, 0x63, 0x51, 0x1e, 0xf6, 0xc7, 0xd8, 0x14, 0x5b, 0xc6, 0x29, ++ 0xc3, 0x3e, 0x47, 0xde, 0xc7, 0x8b, 0xff, 0x4e, 0x95, 0x7c, 0x28, 0x4d, ++ 0x9f, 0xd1, 0x23, 0x50, 0x7a, 0x3c, 0xa2, 0x74, 0x33, 0xa3, 0x82, 0x98, ++ 0x2a, 0xfe, 0x9c, 0x6d, 0x42, 0x17, 0xb4, 0x11, 0xac, 0x0a, 0x06, 0xa6, ++ 0xb2, 0x6d, 0xd8, 0x99, 0x8b, 0x60, 0x47, 0x3e, 0x1c, 0x98, 0xcc, 0x4a, ++ 0x7f, 0x06, 0x63, 0x5b, 0x9e, 0x85, 0x2e, 0x78, 0x56, 0x7f, 0xc1, 0x33, ++ 0x3f, 0x06, 0xc6, 0xfe, 0x98, 0x78, 0x51, 0x8d, 0x1d, 0xc6, 0x59, 0xfa, ++ 0x85, 0x91, 0xea, 0x46, 0x1d, 0xe6, 0x83, 0x41, 0xec, 0x3b, 0x10, 0xc0, ++ 0xce, 0x03, 0x55, 0x78, 0x70, 0xac, 0xbe, 0xcb, 0x97, 0x1e, 0xe2, 0x38, ++ 0xd1, 0x4c, 0xb7, 0xd2, 0x7b, 0xdd, 0x2a, 0x1a, 0xef, 0xa6, 0x9f, 0x36, ++ 0xd4, 0xd8, 0xf6, 0xb1, 0x04, 0xfd, 0xd8, 0x6c, 0x34, 0xaf, 0xa5, 0xa2, ++ 0x73, 0x1d, 0x7a, 0xdb, 0x5b, 0xf0, 0xe3, 0x4f, 0xe9, 0x5f, 0x53, 0x09, ++ 0x74, 0xbb, 0xe1, 0x6e, 0xf2, 0xe3, 0x5f, 0xec, 0x47, 0x3c, 0x62, 0x5f, ++ 0xbb, 0xff, 0x66, 0x73, 0xb7, 0x12, 0x4c, 0x2b, 0x3f, 0x8f, 0x1b, 0xd2, ++ 0xbf, 0xbc, 0xc3, 0x39, 0x62, 0x3f, 0x3d, 0x89, 0xc6, 0x54, 0x0f, 0x16, ++ 0xec, 0xf9, 0xcd, 0x01, 0xec, 0x98, 0xa9, 0xc2, 0xde, 0xb1, 0x32, 0x64, ++ 0x6a, 0x14, 0xaa, 0x8d, 0xe8, 0xdc, 0xed, 0xc4, 0x63, 0x6b, 0x4a, 0xde, ++ 0x0b, 0xe0, 0xa1, 0x99, 0xd2, 0xf7, 0xdc, 0xf9, 0xef, 0x4b, 0xfd, 0x9d, ++ 0xe2, 0xdc, 0x89, 0xdd, 0x04, 0x13, 0x69, 0xea, 0x74, 0x23, 0x8e, 0x8c, ++ 0x85, 0x38, 0x87, 0x1b, 0x94, 0xe7, 0xf0, 0x8a, 0x80, 0xef, 0xfb, 0x36, ++ 0x5e, 0x32, 0x39, 0x9f, 0xb9, 0x8d, 0xca, 0x77, 0xb8, 0x4d, 0x95, 0xcd, ++ 0xde, 0xa0, 0xca, 0x27, 0xbf, 0xa9, 0xb4, 0xc3, 0x5d, 0xaa, 0x62, 0xb6, ++ 0x89, 0x36, 0xee, 0x54, 0xde, 0xc3, 0x7a, 0x24, 0xa2, 0xfe, 0x86, 0xf3, ++ 0xb6, 0x59, 0xb9, 0x67, 0x11, 0x74, 0xa5, 0xfb, 0x94, 0x6b, 0x96, 0x7d, ++ 0x38, 0xbe, 0x22, 0xe3, 0x84, 0x39, 0x3f, 0xb0, 0xdc, 0xe9, 0x5e, 0x6c, ++ 0x21, 0xce, 0x6f, 0xca, 0x02, 0x0f, 0xe4, 0x2a, 0x88, 0x85, 0x12, 0xe3, ++ 0x0b, 0x1c, 0x37, 0x85, 0x07, 0xc9, 0x09, 0x5a, 0x7a, 0x2f, 0x02, 0x8c, ++ 0xad, 0x57, 0x13, 0x12, 0x77, 0x40, 0x3e, 0x17, 0xed, 0x7c, 0x40, 0xd9, ++ 0xf6, 0xb6, 0x98, 0xbd, 0x72, 0x63, 0xa2, 0x31, 0x7e, 0x1c, 0xbf, 0xb1, ++ 0x27, 0x42, 0xbd, 0xa8, 0x6a, 0xe1, 0xb3, 0x41, 0x68, 0x65, 0xe9, 0x9d, ++ 0x38, 0x44, 0xce, 0xf0, 0xa5, 0x89, 0x23, 0x83, 0xd1, 0xce, 0x07, 0x95, ++ 0x60, 0xbb, 0x3e, 0xf7, 0x18, 0x06, 0x4e, 0x54, 0x40, 0x8f, 0xac, 0x57, ++ 0x8d, 0x66, 0xa5, 0xdb, 0x4a, 0xd5, 0x91, 0xca, 0xbc, 0x2d, 0x7a, 0xdf, ++ 0x6e, 0xe8, 0xc1, 0xd3, 0x90, 0x98, 0x14, 0xde, 0xd8, 0x89, 0x94, 0xc3, ++ 0x1f, 0x16, 0x2e, 0x3f, 0xcf, 0x1f, 0xc4, 0x74, 0xca, 0xb5, 0x9b, 0x72, ++ 0xbd, 0x68, 0xea, 0xe1, 0x49, 0xd8, 0x2b, 0xbb, 0xcd, 0xd2, 0xb3, 0x9d, ++ 0xc5, 0x36, 0x72, 0x4a, 0x06, 0x7b, 0x73, 0x8f, 0xdb, 0xa2, 0x8b, 0x27, ++ 0xbd, 0x01, 0x3f, 0x2a, 0xa6, 0xf0, 0x74, 0xb1, 0x89, 0x7e, 0xdf, 0x46, ++ 0x7b, 0x65, 0xf0, 0xc3, 0x62, 0x1a, 0xcf, 0x14, 0x93, 0x78, 0x8a, 0xfe, ++ 0xff, 0x64, 0x31, 0x4e, 0x9b, 0x7a, 0xd4, 0x03, 0x59, 0x03, 0x47, 0x89, ++ 0xa7, 0x7b, 0xf3, 0x11, 0x1c, 0xc9, 0x46, 0xf7, 0x9c, 0x86, 0xfe, 0x2c, ++ 0x89, 0x37, 0xb0, 0x27, 0x6f, 0xe0, 0x70, 0x56, 0x9f, 0x00, 0xc2, 0x81, ++ 0xdd, 0xf9, 0x60, 0x60, 0x20, 0x1b, 0x0a, 0x0c, 0xd0, 0xff, 0x76, 0x64, ++ 0xeb, 0x03, 0x3b, 0xf2, 0xff, 0x86, 0x48, 0x2d, 0xac, 0x15, 0x69, 0x0d, ++ 0xb7, 0x8f, 0x7d, 0x8c, 0xae, 0x1a, 0x91, 0x2c, 0x88, 0x3b, 0x0f, 0x88, ++ 0x6d, 0x1a, 0xbb, 0x2e, 0x73, 0x9d, 0x81, 0xb5, 0xbc, 0x74, 0xaf, 0x97, ++ 0xf7, 0xaa, 0x9b, 0x11, 0x78, 0x6d, 0x56, 0xfc, 0x15, 0x78, 0x8a, 0x3e, ++ 0xfa, 0xed, 0xe6, 0xdf, 0xda, 0x99, 0x5a, 0x07, 0xd3, 0x03, 0xcf, 0x8c, ++ 0x7b, 0x02, 0x33, 0xe4, 0xac, 0x43, 0xcd, 0x0a, 0x4f, 0x9b, 0xff, 0x03, ++ 0x56, 0xed, 0x12, 0x4f, 0x67, 0x26, 0x9e, 0x33, 0x33, 0x08, 0x1b, 0x17, ++ 0xa9, 0xd4, 0x32, 0x4c, 0x3c, 0x6d, 0xfe, 0x62, 0xf1, 0x99, 0x86, 0x7b, ++ 0xc6, 0x34, 0x74, 0xd5, 0x96, 0xfa, 0xbf, 0x8d, 0xfd, 0x5f, 0x9c, 0x68, ++ 0x8c, 0xbc, 0x09, 0x89, 0xc3, 0x0c, 0x0e, 0x9b, 0x3f, 0x5f, 0xe4, 0xc2, ++ 0x0d, 0xd8, 0x35, 0x93, 0x26, 0x97, 0x6b, 0xd8, 0x36, 0xa6, 0xa7, 0x22, ++ 0xae, 0x08, 0xed, 0xf0, 0x31, 0x32, 0xcb, 0x23, 0x78, 0x7a, 0x95, 0x1f, ++ 0x5d, 0x45, 0x3e, 0x3f, 0x80, 0xcc, 0x13, 0xe4, 0xd5, 0xc8, 0x8a, 0x15, ++ 0x70, 0x93, 0x67, 0xdc, 0x46, 0x45, 0x66, 0xb9, 0xe1, 0xc3, 0xcd, 0x53, ++ 0x21, 0xfc, 0x55, 0x71, 0x23, 0x86, 0xe9, 0x67, 0x77, 0xe5, 0x14, 0xea, ++ 0x9a, 0x33, 0xc7, 0xea, 0x10, 0xcb, 0x2c, 0xa8, 0x10, 0x7a, 0xf8, 0xde, ++ 0x03, 0x07, 0x42, 0xb8, 0x99, 0xbe, 0xf3, 0xa1, 0x19, 0xeb, 0xb9, 0x93, ++ 0x58, 0x71, 0x07, 0xef, 0x65, 0x0f, 0x68, 0xd8, 0x97, 0xd8, 0xaa, 0x4a, ++ 0xb6, 0x08, 0x61, 0x6b, 0x0e, 0xc1, 0xca, 0x34, 0x2c, 0x5f, 0x3a, 0xb6, ++ 0xe7, 0x31, 0x7e, 0xbf, 0xbb, 0xe8, 0x0b, 0x6c, 0xdc, 0x8f, 0xef, 0x79, ++ 0xd3, 0x01, 0x2c, 0x23, 0xdf, 0x1e, 0x33, 0x63, 0x91, 0x4d, 0xc4, 0xb5, ++ 0xee, 0xa2, 0x0b, 0xf7, 0x4c, 0xf9, 0xd0, 0x3f, 0xf6, 0xa9, 0x5d, 0x9e, ++ 0xf4, 0xe0, 0x93, 0x55, 0x3e, 0x7c, 0x7b, 0x6a, 0x03, 0x06, 0x0f, 0x20, ++ 0x92, 0x4f, 0xfc, 0x85, 0xb2, 0x6a, 0x4a, 0x38, 0x50, 0x91, 0x96, 0x7b, ++ 0xfe, 0xc0, 0x99, 0xf1, 0x0d, 0x18, 0x39, 0xb0, 0xbe, 0x93, 0x16, 0x9a, ++ 0xdb, 0x95, 0x70, 0x63, 0x5b, 0xc2, 0xbd, 0x8c, 0x29, 0x4a, 0xf0, 0x92, ++ 0xe6, 0xd8, 0x43, 0xeb, 0x95, 0xfb, 0x62, 0x2f, 0x62, 0x0b, 0xdd, 0xae, ++ 0xb9, 0xe1, 0x95, 0xa8, 0xc5, 0xb7, 0x67, 0x36, 0x60, 0xff, 0x01, 0x1f, ++ 0xee, 0x1b, 0x1b, 0xf8, 0xde, 0x72, 0xe2, 0x4d, 0xb8, 0x59, 0x27, 0x27, ++ 0xa7, 0x71, 0x2a, 0xe6, 0x45, 0xcf, 0x94, 0x3f, 0xf0, 0xe1, 0xb8, 0xbd, ++ 0xee, 0x05, 0xf2, 0xf0, 0xcd, 0x33, 0xb5, 0xb8, 0xf9, 0x80, 0x17, 0xb7, ++ 0x8e, 0xe9, 0xbd, 0x27, 0x89, 0x01, 0xaf, 0xc6, 0x2a, 0x90, 0x4f, 0x44, ++ 0x3b, 0xfd, 0xe4, 0xc4, 0xad, 0x89, 0x4a, 0x6c, 0x9d, 0xf2, 0xe2, 0xee, ++ 0xb1, 0x5a, 0x74, 0x1f, 0x08, 0x62, 0xdb, 0x01, 0x1b, 0x17, 0x37, 0xa7, ++ 0x31, 0x92, 0xdb, 0x80, 0x87, 0x19, 0xe7, 0x1b, 0xa0, 0x3f, 0x24, 0x98, ++ 0x7e, 0x8b, 0x2b, 0x83, 0x7f, 0x5d, 0x53, 0x86, 0x89, 0x5a, 0xdb, 0xde, ++ 0xd8, 0xdc, 0x98, 0xf9, 0x7b, 0xca, 0x5c, 0x9b, 0x66, 0x3e, 0x58, 0xa3, ++ 0x3f, 0xc4, 0xdc, 0xa8, 0xaf, 0xc1, 0xb5, 0x56, 0xcd, 0xd3, 0xf6, 0x33, ++ 0xcc, 0x7b, 0xc2, 0xc4, 0xad, 0x60, 0xae, 0x84, 0x6d, 0xc1, 0x62, 0x7d, ++ 0xa0, 0x2e, 0x17, 0x0e, 0xd4, 0x15, 0x11, 0x28, 0x67, 0x4c, 0x3d, 0x49, ++ 0xff, 0xf8, 0x06, 0xfd, 0x63, 0x62, 0xd1, 0x3f, 0x9e, 0x1f, 0x17, 0xae, ++ 0xd1, 0x87, 0x65, 0x3e, 0x1f, 0x9e, 0xf1, 0x04, 0x0e, 0x93, 0xdf, 0x97, ++ 0x19, 0x69, 0xec, 0x2e, 0x96, 0xe6, 0xbe, 0x85, 0xb1, 0x98, 0x1d, 0x8a, ++ 0x46, 0x46, 0x54, 0x58, 0x59, 0x9c, 0xf7, 0x9d, 0xb3, 0x1a, 0xf5, 0x78, ++ 0x03, 0xf3, 0x0e, 0x7f, 0xbf, 0xac, 0x04, 0x73, 0x3d, 0x46, 0x3b, 0x86, ++ 0x72, 0x68, 0x76, 0xa7, 0xf5, 0x78, 0x86, 0xbc, 0xf5, 0x52, 0x02, 0xe9, ++ 0x72, 0xc4, 0xba, 0x4e, 0x92, 0x13, 0x5f, 0x8d, 0xb5, 0x63, 0x90, 0xe3, ++ 0xb6, 0xe7, 0xbd, 0xd8, 0xe2, 0xe8, 0x28, 0x73, 0xc1, 0x5c, 0x85, 0xf9, ++ 0xd7, 0x3e, 0x53, 0x6f, 0xbb, 0x4e, 0xe1, 0x15, 0x2f, 0xdf, 0x39, 0xbb, ++ 0x26, 0x36, 0x67, 0x32, 0x9f, 0x79, 0x36, 0xdf, 0x8e, 0x1c, 0x75, 0xdf, ++ 0xc3, 0xf9, 0x71, 0x27, 0xdc, 0xaa, 0x2b, 0xa8, 0xa1, 0x98, 0xaf, 0xc5, ++ 0x5d, 0x94, 0xe5, 0x54, 0x42, 0xa9, 0x4c, 0xb9, 0x1f, 0x47, 0xf2, 0x1b, ++ 0x30, 0x4c, 0x7f, 0x28, 0x6b, 0x26, 0xef, 0x87, 0xca, 0x11, 0x6f, 0x70, ++ 0xf1, 0x4f, 0x62, 0x32, 0x14, 0xd8, 0x37, 0x5e, 0x1f, 0xd8, 0x45, 0x4e, ++ 0xbc, 0x35, 0xe7, 0xa2, 0x5f, 0xda, 0x76, 0x77, 0xc2, 0xc6, 0x26, 0xce, ++ 0xc1, 0x51, 0x72, 0x6c, 0x3f, 0x39, 0xe3, 0x48, 0x51, 0xb0, 0xad, 0xb0, ++ 0xc8, 0x31, 0x22, 0xfb, 0xd9, 0xc5, 0xcf, 0xc0, 0xe8, 0x10, 0xb1, 0x73, ++ 0x45, 0xc9, 0xbf, 0xee, 0xcb, 0x3d, 0x6f, 0x97, 0x19, 0xc6, 0x44, 0xcc, ++ 0x1d, 0xc2, 0xbd, 0x45, 0x3f, 0x6e, 0xcb, 0xe9, 0x0b, 0x2d, 0xca, 0x8f, ++ 0x7e, 0xfa, 0xfb, 0x5f, 0x31, 0x3e, 0x26, 0x9c, 0x76, 0xe5, 0x8b, 0x71, ++ 0x12, 0xc2, 0xed, 0x39, 0xfb, 0x23, 0x7f, 0xfa, 0x77, 0xf6, 0xce, 0x16, ++ 0xa3, 0xa3, 0x9b, 0x7e, 0xbc, 0x8d, 0xed, 0xee, 0x99, 0x92, 0xf9, 0xf8, ++ 0xaa, 0x1b, 0x3e, 0xe2, 0xa3, 0x0b, 0x81, 0xbf, 0x9f, 0xe5, 0xff, 0x3e, ++ 0x99, 0x17, 0xdd, 0x9e, 0x0f, 0x49, 0xfc, 0xdd, 0xc3, 0xb1, 0x05, 0x03, ++ 0x14, 0x46, 0x56, 0xc7, 0x1e, 0xbf, 0xc2, 0x75, 0x11, 0xe6, 0x6a, 0x89, ++ 0x25, 0x39, 0x27, 0x7f, 0xad, 0xbe, 0xc8, 0x78, 0x15, 0x3f, 0x0a, 0x8a, ++ 0x5e, 0x7d, 0xea, 0xa0, 0xe4, 0xca, 0x15, 0xa8, 0x5e, 0x6e, 0xbc, 0x8f, ++ 0x67, 0x3a, 0x4a, 0xba, 0x3e, 0x98, 0xcd, 0xb8, 0xca, 0x0c, 0x04, 0x43, ++ 0xe9, 0x0d, 0xea, 0x41, 0xf2, 0xd3, 0xc3, 0xd9, 0x36, 0xf5, 0x70, 0xfe, ++ 0x06, 0x65, 0x4d, 0x7c, 0x53, 0x59, 0xd3, 0x5d, 0xca, 0xca, 0x77, 0xf2, ++ 0xba, 0x59, 0xed, 0xca, 0xf7, 0xa9, 0xf1, 0xbc, 0xf4, 0x4b, 0xcc, 0x62, ++ 0xdf, 0x3f, 0xcc, 0x11, 0xa7, 0x72, 0xc4, 0xae, 0x1c, 0xb1, 0x2a, 0x47, ++ 0xac, 0xca, 0x11, 0xc3, 0x72, 0xf1, 0x45, 0xac, 0xee, 0x20, 0x3e, 0x96, ++ 0xfc, 0x6f, 0xec, 0x80, 0xf8, 0x98, 0x7e, 0x24, 0x42, 0xdf, 0xdb, 0xd6, ++ 0xfc, 0x1f, 0xec, 0xcc, 0x72, 0xf1, 0xb5, 0x20, 0x6e, 0x3f, 0x90, 0xa6, ++ 0x7c, 0xcc, 0x4f, 0x13, 0x93, 0xb8, 0x26, 0x48, 0x8e, 0x85, 0x3e, 0x61, ++ 0xe1, 0x6d, 0xc9, 0xa5, 0xf7, 0xcc, 0xe3, 0xe7, 0xbf, 0x8b, 0x38, 0xb6, ++ 0xa9, 0x76, 0x0b, 0x6f, 0x8d, 0xac, 0x16, 0xdc, 0xef, 0x53, 0xfd, 0x94, ++ 0x7f, 0xbe, 0x02, 0x9a, 0x47, 0x72, 0xe3, 0x5c, 0x9f, 0xea, 0xce, 0xcb, ++ 0xfd, 0xbd, 0xd8, 0xce, 0x5c, 0x75, 0x5f, 0x22, 0xda, 0x71, 0x0b, 0x71, ++ 0x7e, 0x13, 0x71, 0x3e, 0x9e, 0xd0, 0xe0, 0xba, 0xec, 0x9c, 0x9d, 0x71, ++ 0xfc, 0xcb, 0xf1, 0xab, 0xcc, 0x5d, 0x49, 0xa9, 0x27, 0xf4, 0x89, 0x79, ++ 0x76, 0x5a, 0x65, 0x28, 0xbc, 0x4c, 0x9f, 0x7a, 0xa0, 0xa8, 0x9b, 0xaf, ++ 0x21, 0xba, 0x27, 0xe9, 0x12, 0xde, 0xb0, 0xf1, 0x5f, 0x12, 0x65, 0xb8, ++ 0x83, 0xf9, 0x6c, 0x85, 0xb1, 0x11, 0x63, 0x63, 0x8a, 0x18, 0x98, 0x19, ++ 0xa8, 0xa5, 0x5d, 0x2b, 0xd6, 0x22, 0x44, 0xa8, 0x54, 0xde, 0xb4, 0xe0, ++ 0x01, 0x70, 0x9c, 0xfe, 0xf5, 0x70, 0x6e, 0x2d, 0x9e, 0x23, 0xae, 0x3f, ++ 0x6b, 0x7a, 0xf0, 0xab, 0x3c, 0x5d, 0x7f, 0x59, 0xec, 0xa1, 0x73, 0xf0, ++ 0x05, 0x2a, 0xf6, 0x43, 0xc6, 0xfb, 0x9e, 0x9b, 0x79, 0xe6, 0x07, 0x7c, ++ 0xfe, 0xd3, 0x58, 0x2c, 0x3e, 0xa5, 0x10, 0xf4, 0xa7, 0xed, 0x95, 0xdb, ++ 0x12, 0xe5, 0x18, 0x6d, 0x08, 0x90, 0x87, 0xbb, 0x54, 0x59, 0x21, 0xf6, ++ 0xd0, 0x76, 0xd7, 0x37, 0x55, 0xf9, 0x21, 0x60, 0x6f, 0xb1, 0x53, 0xd5, ++ 0x1e, 0xd2, 0x88, 0x71, 0xc2, 0x9d, 0x19, 0x1c, 0xe4, 0xbc, 0x85, 0x0d, ++ 0x17, 0x52, 0x4c, 0x31, 0x2e, 0x62, 0x1d, 0x72, 0xcf, 0xda, 0xed, 0xe2, ++ 0x5f, 0x7c, 0x16, 0x0a, 0xac, 0x1c, 0xd2, 0x23, 0x19, 0xd7, 0x06, 0xb5, ++ 0x72, 0xb6, 0x3e, 0x50, 0x3b, 0xd4, 0xa6, 0x6a, 0xc9, 0xa5, 0xcb, 0x27, ++ 0x37, 0xab, 0x65, 0xb3, 0xc2, 0x9d, 0x08, 0x2e, 0xa7, 0x9d, 0x96, 0xcf, ++ 0x5e, 0xe5, 0x2e, 0xe5, 0x26, 0x5e, 0xf4, 0x8d, 0x09, 0x6e, 0x54, 0xa2, ++ 0x87, 0xf1, 0x52, 0xbd, 0x46, 0x4f, 0x9d, 0x54, 0x36, 0x5c, 0x09, 0xbd, ++ 0xf7, 0x4d, 0x36, 0x78, 0x3d, 0x66, 0xdb, 0xc1, 0x66, 0x89, 0x3f, 0xda, ++ 0xdf, 0xd5, 0x4e, 0x9b, 0xe2, 0xaa, 0xba, 0xb4, 0xe0, 0x18, 0x63, 0xce, ++ 0x90, 0x98, 0xf3, 0x62, 0xbb, 0x13, 0x6f, 0xc2, 0xdf, 0x36, 0xf6, 0x26, ++ 0xce, 0xc7, 0x5b, 0x53, 0x39, 0x31, 0x68, 0x5d, 0x2c, 0x36, 0xf7, 0x3c, ++ 0xa4, 0x86, 0x00, 0xae, 0x67, 0x3e, 0xd3, 0x93, 0x0b, 0x11, 0xaf, 0x62, ++ 0xe1, 0x5a, 0xe5, 0xc1, 0xd5, 0xf4, 0xa5, 0xb7, 0x17, 0x63, 0xe8, 0x0e, ++ 0xc6, 0xd0, 0x71, 0xc6, 0x50, 0x9e, 0x31, 0x94, 0x67, 0xec, 0x6c, 0x61, ++ 0x0c, 0x3d, 0xe1, 0xc4, 0x4f, 0x08, 0x93, 0xc5, 0x0f, 0x5c, 0xe2, 0xdb, ++ 0x70, 0xb1, 0xbe, 0x20, 0xce, 0x76, 0x9d, 0xc7, 0xd5, 0xc7, 0x7e, 0x67, ++ 0x2d, 0x97, 0xfc, 0xa5, 0x16, 0x5d, 0x33, 0x12, 0xab, 0x3e, 0xea, 0x22, ++ 0xf3, 0x8d, 0x95, 0x75, 0xcd, 0x3b, 0xee, 0xab, 0x83, 0x4e, 0xac, 0x8f, ++ 0xa3, 0x82, 0x38, 0x79, 0x2b, 0x71, 0xf2, 0xce, 0xf1, 0xdd, 0xec, 0x87, ++ 0xfc, 0x36, 0x13, 0xc2, 0x9d, 0xf4, 0xcf, 0x57, 0x5b, 0xb6, 0x3b, 0xfd, ++ 0xdf, 0x51, 0x7c, 0xce, 0x55, 0xb2, 0x45, 0x29, 0x86, 0x38, 0x8d, 0xf6, ++ 0x55, 0x8c, 0xff, 0x09, 0xca, 0xfb, 0x6c, 0x16, 0x56, 0x5d, 0x3a, 0x36, ++ 0x5c, 0xe7, 0xfe, 0x67, 0xb6, 0xf1, 0xe3, 0xc9, 0xbc, 0x60, 0xd8, 0x33, ++ 0x2e, 0xf1, 0xb9, 0x65, 0x46, 0x99, 0x70, 0x99, 0x55, 0x95, 0xd6, 0x02, ++ 0x87, 0xf7, 0x67, 0xf0, 0x0f, 0xe6, 0xfa, 0xc5, 0x38, 0xed, 0x53, 0xc3, ++ 0xf4, 0x43, 0x86, 0xad, 0xc4, 0x7e, 0x60, 0x74, 0x1c, 0x65, 0x94, 0x29, ++ 0x52, 0x41, 0xbe, 0xe8, 0x6c, 0x8e, 0xf5, 0xb9, 0xdd, 0xed, 0x2a, 0x97, ++ 0x0f, 0x05, 0xf6, 0x64, 0xf9, 0x90, 0x31, 0xb5, 0x87, 0x76, 0x18, 0x60, ++ 0x4c, 0x0d, 0x7c, 0x41, 0x4c, 0x3d, 0xc0, 0x98, 0x1a, 0xca, 0xaf, 0x90, ++ 0xb9, 0x62, 0x2c, 0xb2, 0xc0, 0xa5, 0xad, 0x46, 0x1b, 0x4a, 0xbe, 0x50, ++ 0xdd, 0x60, 0xaf, 0x3c, 0x95, 0xf8, 0xae, 0x33, 0x8f, 0x7b, 0x8a, 0xed, ++ 0x7c, 0xa7, 0x6e, 0x91, 0x5b, 0x83, 0x81, 0xbd, 0xd9, 0x0d, 0x6a, 0xaf, ++ 0xc3, 0xf3, 0xb0, 0xfc, 0xf4, 0x97, 0x15, 0x46, 0x9b, 0xda, 0xe1, 0xc4, ++ 0x26, 0xc7, 0x78, 0x44, 0xe2, 0x93, 0xe3, 0x1c, 0x92, 0xf8, 0xe4, 0x58, ++ 0x05, 0x89, 0x51, 0x8e, 0x77, 0x48, 0xe2, 0x74, 0xb3, 0xfa, 0x7e, 0x41, ++ 0x62, 0x55, 0xe2, 0x77, 0x29, 0x5e, 0x11, 0xf4, 0xa4, 0x25, 0x5e, 0x25, ++ 0x6e, 0xfb, 0xd4, 0xce, 0x02, 0xf1, 0x8f, 0xfd, 0xef, 0xa3, 0xdc, 0x3b, ++ 0xb2, 0x7e, 0x8f, 0xc8, 0xe6, 0x4f, 0x0b, 0xc6, 0x48, 0x1c, 0x06, 0x29, ++ 0x8f, 0x60, 0xcc, 0xf9, 0x3a, 0x9d, 0xff, 0xfe, 0xc4, 0x0d, 0xe3, 0xd4, ++ 0xa2, 0x0e, 0x92, 0xc3, 0xdb, 0x91, 0x30, 0xeb, 0xf2, 0xa7, 0x8b, 0xe8, ++ 0xaa, 0xa0, 0x2f, 0x79, 0xd3, 0x41, 0xd4, 0x19, 0xbf, 0xb5, 0x43, 0x57, ++ 0x68, 0xe6, 0x39, 0xe6, 0x2b, 0xcf, 0xb3, 0x3e, 0x79, 0xaa, 0x78, 0x61, ++ 0xbd, 0x82, 0x40, 0xb2, 0x80, 0x2f, 0xf8, 0x67, 0x63, 0x59, 0xfa, 0xb7, ++ 0xf6, 0xb7, 0xd7, 0x22, 0xd0, 0x5c, 0xf0, 0x74, 0x91, 0xa7, 0x3b, 0x7a, ++ 0x07, 0xfb, 0xed, 0x1a, 0xc6, 0x45, 0x20, 0x6d, 0xf4, 0xd5, 0xb8, 0xfc, ++ 0xa9, 0x33, 0x2d, 0x5e, 0xf5, 0x6a, 0x4b, 0xb8, 0xfd, 0x03, 0xf2, 0x82, ++ 0xcf, 0x40, 0xc7, 0xf6, 0x42, 0xca, 0x73, 0x8a, 0xdc, 0x74, 0x29, 0x6b, ++ 0xc6, 0x48, 0xa1, 0xbe, 0xfd, 0x6d, 0xe6, 0x2c, 0xe5, 0x89, 0xbb, 0x2f, ++ 0x3f, 0x9e, 0x72, 0x7d, 0xb9, 0x0c, 0xd5, 0xac, 0x59, 0x9f, 0x9a, 0xdb, ++ 0x6d, 0x54, 0x30, 0xe7, 0xd6, 0x30, 0x50, 0xac, 0x6f, 0x3f, 0x99, 0x5d, ++ 0x09, 0xe6, 0x3b, 0x9f, 0x4e, 0x26, 0x8d, 0xc8, 0x16, 0x1c, 0x3b, 0xe7, ++ 0x21, 0xd7, 0x3f, 0x5c, 0xd4, 0xb4, 0x8f, 0xb2, 0xde, 0xbf, 0xa8, 0x4a, ++ 0xe3, 0x6c, 0xd0, 0x30, 0xba, 0xce, 0x32, 0xe7, 0x9f, 0x6d, 0x69, 0xe8, ++ 0x18, 0x52, 0x0d, 0x9d, 0x83, 0x4a, 0xa1, 0xe7, 0x32, 0x85, 0x4d, 0x97, ++ 0xc5, 0x52, 0x5e, 0xe5, 0xc5, 0x7c, 0x87, 0x9f, 0xb9, 0x71, 0x7d, 0x57, ++ 0x88, 0x39, 0xd6, 0xe8, 0x90, 0xf8, 0x8c, 0x1f, 0x63, 0x53, 0xb8, 0xff, ++ 0xeb, 0xcd, 0x41, 0x8c, 0xcc, 0x30, 0x60, 0x67, 0x24, 0x77, 0x6e, 0x87, ++ 0x55, 0x74, 0x63, 0x8e, 0x58, 0x64, 0xd1, 0x26, 0xe5, 0xe9, 0xa6, 0x0d, ++ 0x73, 0xf9, 0x70, 0x99, 0xc4, 0x73, 0x4d, 0x7a, 0x32, 0x80, 0x40, 0x2f, ++ 0xcc, 0xb5, 0xd0, 0x96, 0xa5, 0x4f, 0x7d, 0xe5, 0x9e, 0x06, 0x68, 0xa1, ++ 0x74, 0x4f, 0x7a, 0xbc, 0x81, 0x7e, 0x48, 0x1b, 0x6b, 0x43, 0xc0, 0x3a, ++ 0xf6, 0x7b, 0xee, 0x2b, 0x0a, 0xa9, 0x35, 0x04, 0xc4, 0x65, 0x92, 0xab, ++ 0xe8, 0x6d, 0x19, 0x3e, 0x5b, 0x35, 0x28, 0xeb, 0x1c, 0xdb, 0x17, 0xd7, ++ 0x39, 0x7a, 0x64, 0x9d, 0xc3, 0x3c, 0xc5, 0x1a, 0xa8, 0x7c, 0x71, 0x9d, ++ 0xe3, 0x30, 0x9c, 0x75, 0x8e, 0x4c, 0x69, 0x9d, 0x63, 0x3b, 0x62, 0x4e, ++ 0x9e, 0xda, 0x83, 0x78, 0x1e, 0x58, 0x3f, 0xa8, 0x70, 0x75, 0x4a, 0xa1, ++ 0xdb, 0xfc, 0xc0, 0xb6, 0x42, 0x7a, 0x86, 0x98, 0x88, 0xf0, 0x90, 0xe4, ++ 0xc2, 0xdb, 0x9d, 0x5c, 0xd8, 0xcf, 0x76, 0xd9, 0xc1, 0x68, 0x9f, 0xe6, ++ 0xd6, 0x53, 0x45, 0xe8, 0x3d, 0xec, 0xaf, 0xf3, 0x23, 0xc6, 0xdb, 0x20, ++ 0x73, 0xe3, 0xca, 0xc5, 0xfe, 0x56, 0x2d, 0xf6, 0x77, 0x71, 0x1e, 0x2a, ++ 0x3e, 0x64, 0xb1, 0xe6, 0xf3, 0x59, 0x2b, 0xd3, 0x19, 0x97, 0x27, 0x66, ++ 0xb4, 0xed, 0x40, 0x04, 0x71, 0xd6, 0x7c, 0x97, 0xcc, 0x12, 0x81, 0x86, ++ 0xfa, 0x71, 0xd0, 0xd4, 0x3b, 0xd6, 0xb9, 0x05, 0x57, 0xda, 0x88, 0x75, ++ 0x19, 0xfa, 0xb3, 0xe4, 0xea, 0x7d, 0xea, 0x1d, 0xc6, 0xd1, 0x9c, 0xa7, ++ 0x34, 0xdb, 0xa5, 0xf1, 0xef, 0x75, 0xc6, 0xaf, 0x62, 0x8e, 0x4f, 0x7d, ++ 0xfa, 0xbc, 0x6e, 0xbd, 0x93, 0xe3, 0x07, 0x45, 0x9f, 0xbb, 0x14, 0x73, ++ 0x69, 0xa5, 0xb7, 0x6d, 0x87, 0x83, 0xff, 0x1c, 0xfb, 0x5e, 0x34, 0x3a, ++ 0x32, 0xf4, 0xe2, 0x12, 0xc6, 0xd1, 0x5b, 0x79, 0x4d, 0xd9, 0xc3, 0x1b, ++ 0xf1, 0xf0, 0xd4, 0x46, 0x1c, 0x24, 0x76, 0x5f, 0xba, 0xa6, 0x9a, 0x35, ++ 0x0c, 0xaa, 0x58, 0x6a, 0x2d, 0x94, 0xc7, 0x94, 0xfb, 0xe5, 0xa6, 0x7a, ++ 0xd6, 0x56, 0xc7, 0xea, 0x34, 0x9c, 0xb5, 0xef, 0x33, 0xd6, 0x77, 0xd4, ++ 0x21, 0x73, 0x95, 0x0f, 0xbf, 0x11, 0xec, 0x7b, 0x63, 0x99, 0x42, 0xc6, ++ 0x97, 0x16, 0x0e, 0x48, 0x29, 0x5f, 0x61, 0xc0, 0x53, 0xc2, 0x8b, 0x06, ++ 0xb8, 0x6b, 0x50, 0x1d, 0x30, 0x2e, 0x45, 0xa0, 0x46, 0xb3, 0xca, 0x99, ++ 0xe3, 0xbf, 0xcc, 0xba, 0x63, 0x61, 0xb8, 0x83, 0x75, 0xab, 0x60, 0xe9, ++ 0xbf, 0xd8, 0x6f, 0x2f, 0x97, 0xf7, 0x7e, 0xe0, 0x5d, 0xe4, 0xfe, 0x2f, ++ 0xe8, 0xc3, 0xc3, 0xba, 0xaf, 0x71, 0xa1, 0x1b, 0x95, 0x98, 0xbf, 0x48, ++ 0xc3, 0x60, 0x4e, 0xef, 0x1a, 0x64, 0xcd, 0xb5, 0x2f, 0xd6, 0xd8, 0x76, ++ 0xb3, 0x2a, 0x47, 0x64, 0x79, 0x34, 0xd8, 0x8d, 0x8c, 0xee, 0x5a, 0x94, ++ 0x63, 0x1c, 0xbf, 0x94, 0xf7, 0xa4, 0x9f, 0x0b, 0xe2, 0xab, 0xc0, 0xf8, ++ 0xfa, 0xcd, 0x62, 0x7e, 0x71, 0xfe, 0xb9, 0xf6, 0xc7, 0xe9, 0x9e, 0xd6, ++ 0x7f, 0xbf, 0xea, 0x8b, 0xee, 0xef, 0xf9, 0x82, 0xfb, 0x73, 0x35, 0x1e, ++ 0xa7, 0xc6, 0xcd, 0xb8, 0x64, 0x0d, 0xce, 0x93, 0x7e, 0xa5, 0x75, 0xa7, ++ 0xf1, 0x47, 0xd4, 0xc3, 0x62, 0xed, 0x2d, 0x18, 0x3b, 0xef, 0xd4, 0xde, ++ 0xcf, 0xff, 0x7e, 0x5c, 0x92, 0x6f, 0xbc, 0xaa, 0x72, 0xd4, 0xb2, 0x6b, ++ 0x8d, 0xe5, 0xf4, 0xd7, 0x7e, 0x74, 0x27, 0x32, 0xe4, 0x74, 0xbd, 0xe3, ++ 0xeb, 0x30, 0x32, 0x37, 0x28, 0x76, 0x34, 0xeb, 0x55, 0xee, 0xd1, 0xc5, ++ 0x67, 0xa6, 0x45, 0x5e, 0x9b, 0x23, 0x77, 0x66, 0x98, 0x0f, 0x31, 0xc0, ++ 0x66, 0x43, 0x9a, 0x67, 0x36, 0xac, 0x95, 0xcf, 0xd6, 0x6b, 0x15, 0x6c, ++ 0xe7, 0x1f, 0xd5, 0x17, 0xbe, 0x8e, 0x7e, 0x2c, 0xac, 0xf1, 0x11, 0x73, ++ 0xf5, 0x60, 0x9d, 0xbb, 0x1f, 0x3b, 0x13, 0xf2, 0x6e, 0x1b, 0x63, 0x11, ++ 0xaa, 0x66, 0xc8, 0x82, 0x9f, 0xbc, 0xb3, 0x8b, 0x35, 0xd6, 0xc5, 0x2e, ++ 0xa3, 0xed, 0x13, 0xe5, 0xd1, 0xbc, 0xb3, 0x50, 0x81, 0x21, 0x17, 0x1e, ++ 0x6a, 0x81, 0xd7, 0xbb, 0x56, 0xef, 0x39, 0xa6, 0xfa, 0xf0, 0x58, 0x22, ++ 0xd6, 0xb1, 0x55, 0x45, 0x34, 0x1f, 0x9f, 0x95, 0x0d, 0x41, 0x69, 0x43, ++ 0x96, 0xb7, 0x6c, 0xad, 0x1e, 0x76, 0xa9, 0x0c, 0xba, 0x0d, 0xc3, 0x1c, ++ 0x85, 0xc6, 0x31, 0xa1, 0x2a, 0x86, 0xf4, 0x85, 0x37, 0x91, 0xc1, 0xb9, ++ 0x55, 0x7d, 0x68, 0x5e, 0x13, 0xdb, 0xd3, 0xe9, 0x32, 0xb4, 0x1a, 0xde, ++ 0xf7, 0x0c, 0xf9, 0x71, 0xf9, 0xfe, 0xa5, 0xb5, 0x08, 0xdb, 0xfe, 0x30, ++ 0x31, 0x77, 0x1b, 0x4d, 0xa5, 0x55, 0xcd, 0xc6, 0x35, 0xff, 0xac, 0x1f, ++ 0x8d, 0xfb, 0x65, 0x7d, 0x82, 0xf5, 0x62, 0x62, 0x8e, 0xfe, 0xd1, 0x44, ++ 0x1d, 0x3b, 0x30, 0x95, 0x95, 0x1a, 0x34, 0x8d, 0x49, 0xf2, 0x99, 0x31, ++ 0x58, 0xcf, 0x9a, 0x2b, 0x85, 0x99, 0xac, 0xac, 0x59, 0x74, 0x63, 0x47, ++ 0x71, 0x33, 0xe5, 0xef, 0x60, 0x6d, 0x77, 0x13, 0xf3, 0x5d, 0xb1, 0x71, ++ 0x97, 0xac, 0x4d, 0xb2, 0x9e, 0xfc, 0xb8, 0xf5, 0x6b, 0x23, 0xd0, 0xbc, ++ 0xe9, 0xf7, 0x5a, 0x2f, 0xd9, 0x8f, 0x1a, 0xe2, 0x4c, 0xda, 0xc7, 0xa0, ++ 0x8e, 0xc7, 0x62, 0x8c, 0xd3, 0x58, 0xf8, 0x45, 0xce, 0xc7, 0x00, 0xf3, ++ 0x98, 0x1d, 0x4e, 0xdd, 0xe8, 0x81, 0x95, 0x17, 0xac, 0x84, 0x37, 0xde, ++ 0x52, 0x83, 0x8a, 0x91, 0xb8, 0xb3, 0xee, 0x61, 0x11, 0x03, 0x4f, 0x9a, ++ 0x7a, 0xcf, 0x04, 0xf4, 0x2e, 0x59, 0x9f, 0xda, 0x12, 0xfc, 0xef, 0xbb, ++ 0x2b, 0x93, 0xd0, 0x2a, 0x0d, 0x89, 0xa5, 0xbf, 0xf5, 0xbd, 0x49, 0x7f, ++ 0xbc, 0x7a, 0xfc, 0x07, 0xbe, 0x85, 0xe4, 0x84, 0xef, 0x9d, 0xa4, 0x6d, ++ 0xdf, 0xc7, 0x99, 0xbc, 0x91, 0x58, 0x5a, 0x9d, 0xb3, 0x7c, 0xa7, 0x92, ++ 0xb2, 0x86, 0xe9, 0xc1, 0xf5, 0xfc, 0x2e, 0xeb, 0x6e, 0x7f, 0x56, 0xa8, ++ 0x43, 0xd9, 0x88, 0x1b, 0x53, 0xe6, 0x46, 0x74, 0x07, 0x5d, 0xb8, 0x2d, ++ 0xfe, 0x0c, 0xfd, 0xcf, 0xc5, 0x36, 0xc3, 0xfc, 0x2e, 0x6b, 0x31, 0xff, ++ 0x11, 0x5b, 0x83, 0xd3, 0xbe, 0xb7, 0x92, 0x22, 0xf3, 0xbc, 0xc8, 0xac, ++ 0x55, 0x18, 0x1d, 0xb8, 0xf5, 0xeb, 0x52, 0x0b, 0xc0, 0x72, 0x51, 0xb6, ++ 0x1b, 0x93, 0xb5, 0x88, 0x8f, 0xd5, 0x61, 0xf5, 0x98, 0xe5, 0xed, 0x4c, ++ 0x32, 0x06, 0x12, 0x71, 0x94, 0xe7, 0xf4, 0xf0, 0x19, 0x65, 0xa5, 0xdc, ++ 0xf4, 0x6b, 0x83, 0x1c, 0xff, 0xd3, 0x84, 0x1e, 0x7c, 0x0b, 0xb8, 0xac, ++ 0x12, 0xb1, 0xb9, 0xc3, 0xc0, 0xfd, 0x84, 0xaa, 0x2e, 0x2d, 0x1d, 0x0b, ++ 0x6b, 0x6e, 0xbb, 0xfc, 0x34, 0x6b, 0xee, 0xab, 0x0b, 0x1e, 0x6c, 0x2a, ++ 0x34, 0x61, 0x75, 0x4e, 0xb8, 0x3c, 0xed, 0xed, 0x4b, 0x8a, 0x6c, 0x26, ++ 0x56, 0x91, 0x8b, 0x36, 0xc5, 0xe0, 0xbd, 0x33, 0xe9, 0xc7, 0xb5, 0x85, ++ 0x24, 0x1a, 0x59, 0xbb, 0x5d, 0x47, 0xee, 0x32, 0x72, 0x21, 0x6c, 0x28, ++ 0xd4, 0x23, 0xc6, 0xf9, 0xba, 0xa6, 0x10, 0xc1, 0xc5, 0xb9, 0x7a, 0xac, ++ 0x2f, 0x18, 0x68, 0xe0, 0xfd, 0x8b, 0x63, 0x11, 0x6c, 0x2c, 0xc4, 0x11, ++ 0xcf, 0x19, 0x68, 0x73, 0xf4, 0xf6, 0xe0, 0x32, 0x5e, 0x2f, 0x2f, 0xf8, ++ 0x55, 0x37, 0x75, 0x36, 0x0a, 0xb5, 0x78, 0x79, 0x44, 0x70, 0xe5, 0x6c, ++ 0xeb, 0xa1, 0xe1, 0x20, 0x39, 0xc1, 0xc6, 0xfb, 0xa6, 0x6e, 0x12, 0x13, ++ 0xef, 0x22, 0x7d, 0xbf, 0x52, 0xc6, 0xfa, 0xe2, 0x39, 0xe6, 0x8c, 0x7b, ++ 0x5b, 0x4a, 0x6b, 0x91, 0x97, 0x16, 0x3e, 0xd3, 0xbd, 0x8e, 0xf3, 0x76, ++ 0xe5, 0x81, 0x69, 0xb1, 0xb1, 0x56, 0x9e, 0xfe, 0x45, 0xeb, 0x4b, 0xe3, ++ 0xcc, 0x71, 0xc6, 0x65, 0xbd, 0x44, 0x9f, 0x8b, 0xba, 0xa3, 0xbd, 0xe5, ++ 0x6e, 0xa4, 0xab, 0xf1, 0x89, 0x7d, 0x82, 0xf9, 0xdd, 0x29, 0x88, 0xad, ++ 0xfc, 0x94, 0x2f, 0x88, 0x0c, 0xb9, 0xe7, 0xba, 0xc2, 0x53, 0xf6, 0xad, ++ 0xcb, 0xc3, 0xf8, 0x5a, 0xcc, 0xb1, 0x9d, 0x57, 0xbb, 0x82, 0x40, 0x32, ++ 0x52, 0xc7, 0x79, 0xb5, 0x7c, 0xee, 0x2b, 0x6c, 0x7c, 0x98, 0x90, 0xfe, ++ 0xdf, 0x61, 0xff, 0x97, 0xe2, 0xae, 0xf1, 0x81, 0xce, 0x00, 0xe7, 0xf9, ++ 0x2d, 0xb3, 0x93, 0x35, 0x2b, 0x56, 0x54, 0x02, 0x4d, 0x1e, 0xda, 0xb2, ++ 0x81, 0xe3, 0x34, 0xb8, 0x63, 0x6d, 0xd7, 0x20, 0xd6, 0x9b, 0x52, 0x7a, ++ 0xe7, 0xbb, 0xc4, 0x28, 0x37, 0xf3, 0xcf, 0x17, 0x98, 0x7b, 0x55, 0x4a, ++ 0xe5, 0x4c, 0x3b, 0x5e, 0x53, 0x08, 0xc3, 0x35, 0x52, 0x8e, 0xf2, 0xb4, ++ 0x93, 0x17, 0xfd, 0xcc, 0x45, 0x9b, 0x37, 0xb8, 0x35, 0x74, 0xd2, 0xbe, ++ 0xd5, 0x83, 0x62, 0x5b, 0x85, 0xd3, 0x94, 0xeb, 0x7a, 0xda, 0xaf, 0x72, ++ 0xd0, 0xee, 0x5f, 0x9d, 0x08, 0xd1, 0xc6, 0x62, 0xd7, 0x25, 0x5b, 0x75, ++ 0x62, 0x68, 0x66, 0xc9, 0x5e, 0x62, 0x7b, 0xb1, 0xe9, 0x1f, 0x62, 0xb7, ++ 0x69, 0xdf, 0x69, 0xfa, 0xa2, 0xb1, 0x9f, 0x7e, 0xbb, 0xff, 0xbc, 0x0d, ++ 0xeb, 0x09, 0xed, 0xaf, 0x70, 0xfe, 0xbf, 0xd7, 0x97, 0x8c, 0xf5, 0x35, ++ 0xb2, 0x5d, 0x27, 0xed, 0x73, 0x7d, 0x61, 0xb2, 0x0c, 0xbe, 0x90, 0xd8, ++ 0xe6, 0xbc, 0xad, 0xcb, 0x68, 0xeb, 0x43, 0xe3, 0x9f, 0xd9, 0xf9, 0xa0, ++ 0x63, 0xe7, 0x38, 0xc2, 0xfb, 0xf5, 0xe0, 0x14, 0xa2, 0x7d, 0x1b, 0x81, ++ 0x74, 0x1d, 0x55, 0x0e, 0xe3, 0x43, 0xfb, 0x43, 0xda, 0x9b, 0xa9, 0xc8, ++ 0xf7, 0xde, 0xa2, 0x9f, 0x6c, 0x60, 0x7f, 0xd7, 0xd0, 0xde, 0x19, 0xda, ++ 0xe1, 0x3a, 0xa7, 0xdf, 0x7a, 0xf6, 0x7b, 0xbd, 0xdd, 0x15, 0x9a, 0x66, ++ 0x3c, 0xd0, 0xef, 0xc7, 0xcf, 0x8f, 0xb1, 0x21, 0x80, 0x58, 0xaa, 0x52, ++ 0x89, 0x6f, 0x49, 0xbb, 0x20, 0xdb, 0x89, 0xec, 0xaf, 0x57, 0xb8, 0x8c, ++ 0x2f, 0x5a, 0x3f, 0xed, 0x02, 0xf1, 0x78, 0x8f, 0x85, 0xcd, 0xd8, 0x93, ++ 0xeb, 0xc0, 0x03, 0x39, 0x8d, 0xf5, 0x96, 0x85, 0x27, 0x93, 0x7a, 0xbc, ++ 0x46, 0x09, 0x2e, 0x5a, 0x8c, 0xcf, 0x39, 0xb8, 0x8d, 0x68, 0x64, 0x06, ++ 0x61, 0xcd, 0x35, 0x2b, 0xfc, 0x50, 0xaf, 0xb9, 0x67, 0x19, 0xc7, 0xe1, ++ 0xcd, 0xd8, 0x55, 0xf4, 0xe0, 0xc5, 0xbc, 0x07, 0x3f, 0xce, 0x76, 0x90, ++ 0xe7, 0xbc, 0x88, 0xd4, 0x5a, 0x5e, 0xcf, 0xda, 0x6f, 0x96, 0x97, 0x30, ++ 0x79, 0x15, 0xda, 0x47, 0xef, 0x45, 0xe5, 0x90, 0xa7, 0x63, 0x40, 0xe9, ++ 0xe6, 0x75, 0x94, 0x69, 0xe3, 0xac, 0x3c, 0xaf, 0xc7, 0x50, 0xf6, 0x26, ++ 0xd6, 0xad, 0xd1, 0x9e, 0xd7, 0x98, 0x3f, 0x4f, 0xd4, 0xd5, 0x3b, 0x6b, ++ 0x94, 0xc3, 0xbc, 0x37, 0x5c, 0xfc, 0xfc, 0xda, 0xe9, 0x96, 0xc5, 0x35, ++ 0xd3, 0x6e, 0xe6, 0xec, 0x9b, 0x59, 0xd7, 0x74, 0x60, 0x60, 0x51, 0xc6, ++ 0xe9, 0x64, 0x07, 0x76, 0xe7, 0xd3, 0xe7, 0x71, 0x65, 0x32, 0x5f, 0x5a, ++ 0x33, 0xbb, 0x95, 0xf6, 0x38, 0x99, 0xb5, 0xf1, 0x80, 0x29, 0xf8, 0xbf, ++ 0x19, 0x3b, 0xb3, 0xb2, 0x6e, 0x66, 0xe3, 0x51, 0x53, 0x09, 0x0e, 0x91, ++ 0x47, 0x37, 0x93, 0xcb, 0x6d, 0x9c, 0x30, 0x53, 0xc4, 0x34, 0xc1, 0xa2, ++ 0x3e, 0x15, 0x1b, 0xfc, 0x9d, 0x3d, 0xe1, 0xe9, 0x45, 0x23, 0xe3, 0x76, ++ 0xeb, 0xa0, 0x1b, 0x33, 0x53, 0x92, 0x73, 0xdc, 0x2b, 0x39, 0x07, 0x9e, ++ 0xcb, 0x9d, 0xe7, 0xe9, 0xd4, 0x14, 0xec, 0x7e, 0x4f, 0x5a, 0xef, 0x93, ++ 0xfd, 0x86, 0x81, 0xa4, 0x9e, 0xaa, 0x70, 0x72, 0x10, 0xa3, 0xf3, 0x62, ++ 0xb7, 0x6e, 0xce, 0xaa, 0xc6, 0xae, 0x8f, 0x30, 0x77, 0xad, 0x06, 0x3d, ++ 0xfc, 0x0a, 0x62, 0xf1, 0x1e, 0x59, 0x57, 0x2f, 0x96, 0xf8, 0x7b, 0xd5, ++ 0x22, 0x7f, 0x47, 0xf3, 0x3e, 0x65, 0x8c, 0xb0, 0x0e, 0x9f, 0xb2, 0x89, ++ 0x33, 0x0a, 0xd3, 0x53, 0xc0, 0xb3, 0xb9, 0x7e, 0x5c, 0xcf, 0x7a, 0xe3, ++ 0xc6, 0xa4, 0xd1, 0xc3, 0xfa, 0xe2, 0x3b, 0xd5, 0xcc, 0x29, 0x2a, 0xd3, ++ 0xb1, 0xae, 0x59, 0x85, 0xc8, 0xb6, 0x16, 0xcb, 0xd6, 0x58, 0xb3, 0x96, ++ 0xa7, 0x65, 0x1d, 0xae, 0x5d, 0x35, 0x15, 0x36, 0xab, 0x4b, 0x0b, 0x9d, ++ 0x2a, 0x72, 0xe8, 0x06, 0x15, 0x7f, 0xa4, 0x94, 0xc7, 0x36, 0x14, 0x3e, ++ 0x5b, 0x2b, 0x6c, 0xa3, 0xde, 0x7b, 0x59, 0xbf, 0x1c, 0xa5, 0x6e, 0x7b, ++ 0x8a, 0xa5, 0x5a, 0x78, 0x57, 0xb6, 0xa4, 0xdb, 0x03, 0x7c, 0xfe, 0x7e, ++ 0xf6, 0xb3, 0xdc, 0xa3, 0x8e, 0xef, 0x5c, 0x99, 0x8b, 0x46, 0x7a, 0x94, ++ 0xde, 0x3b, 0x5d, 0xca, 0x3d, 0xe6, 0x8e, 0x2b, 0x72, 0x92, 0x93, 0xbf, ++ 0xe8, 0x3d, 0x0b, 0xaa, 0x24, 0xfb, 0xea, 0x3c, 0xc4, 0xc7, 0x1c, 0xf9, ++ 0x2f, 0xcb, 0x47, 0xf0, 0x4a, 0xb6, 0xb1, 0xd3, 0x4b, 0xb3, 0x9d, 0x4a, ++ 0x6e, 0x50, 0x67, 0x98, 0xe7, 0xfe, 0x38, 0x9b, 0x59, 0x5e, 0x89, 0x36, ++ 0x75, 0x3a, 0xdf, 0xa1, 0xde, 0x9b, 0x68, 0x87, 0x67, 0xe4, 0x0e, 0xf5, ++ 0xd6, 0x84, 0xc8, 0xd6, 0xa9, 0xe6, 0xa7, 0x4f, 0x39, 0xb6, 0xdf, 0x69, ++ 0x06, 0xe9, 0x6b, 0x3f, 0xa7, 0x5f, 0xd8, 0x38, 0x64, 0xca, 0x3c, 0xf2, ++ 0x7b, 0xae, 0xb4, 0xf7, 0xb5, 0x31, 0x39, 0x6c, 0x33, 0xcf, 0x09, 0xba, ++ 0xd2, 0x61, 0x47, 0xc7, 0x29, 0xd6, 0x0f, 0xd3, 0x13, 0x9b, 0xd5, 0xe1, ++ 0x7c, 0x49, 0xbf, 0xc9, 0xbc, 0xf8, 0xad, 0xc6, 0x7c, 0xe3, 0xf3, 0xbc, ++ 0x6d, 0x21, 0xd8, 0x12, 0x46, 0xf9, 0x90, 0xc8, 0x6b, 0x63, 0xd4, 0x8c, ++ 0x45, 0x5e, 0x46, 0x18, 0x9e, 0x59, 0xf1, 0x69, 0x1b, 0x4f, 0x98, 0x65, ++ 0x70, 0x8f, 0x6a, 0xb4, 0x0b, 0x7d, 0x28, 0x50, 0x06, 0xd7, 0xa4, 0xd4, ++ 0x93, 0xe7, 0x28, 0x83, 0x1e, 0x8f, 0xb8, 0xe4, 0xf3, 0xe7, 0x7d, 0xad, ++ 0x8c, 0xdc, 0x20, 0x6b, 0xc7, 0xe3, 0xe5, 0x25, 0x9f, 0x13, 0xf9, 0x2c, ++ 0xef, 0x14, 0x71, 0xfb, 0x96, 0x61, 0x0d, 0xc7, 0x4c, 0xe6, 0x59, 0x41, ++ 0xa5, 0x7c, 0x69, 0x9f, 0xb6, 0x89, 0x7e, 0xf2, 0x60, 0xfe, 0x5e, 0x1c, ++ 0x21, 0x4f, 0xee, 0xe1, 0xdc, 0x56, 0x10, 0x3f, 0xde, 0x25, 0x7e, 0xbc, ++ 0xcd, 0x3a, 0x78, 0xa2, 0x43, 0x23, 0xc7, 0x69, 0xac, 0xa7, 0x2c, 0xe4, ++ 0x5b, 0x3a, 0xb1, 0x6f, 0x50, 0xc3, 0x3e, 0xd6, 0x60, 0xa5, 0xbd, 0x2c, ++ 0x3d, 0x68, 0x21, 0x5d, 0x21, 0x35, 0xd8, 0x4e, 0xe3, 0x94, 0xb3, 0x36, ++ 0xaa, 0xa5, 0x45, 0x17, 0x59, 0x67, 0xb1, 0xbc, 0xe5, 0x2d, 0x5e, 0xbc, ++ 0x3c, 0xcc, 0x8a, 0xd3, 0x60, 0x1e, 0xd0, 0xe2, 0x70, 0xa2, 0x65, 0x91, ++ 0x13, 0x27, 0x98, 0x5f, 0x55, 0x1a, 0xf7, 0x91, 0x17, 0x5d, 0xcc, 0x3b, ++ 0x6e, 0xc2, 0x6b, 0xe3, 0x1e, 0x57, 0x40, 0xea, 0x6e, 0xe6, 0x08, 0xf4, ++ 0x13, 0xf8, 0x66, 0x35, 0xbc, 0x38, 0x1c, 0xc1, 0x34, 0xc7, 0xb7, 0x9c, ++ 0xf5, 0xc6, 0x3f, 0xc3, 0xb1, 0x61, 0xb7, 0x5a, 0x99, 0x86, 0xfb, 0x1c, ++ 0x71, 0xb8, 0xd3, 0x8c, 0x99, 0x75, 0xc4, 0xcb, 0x4a, 0xf2, 0x64, 0xf9, ++ 0x6c, 0x0d, 0xae, 0x1c, 0xa9, 0x45, 0xc3, 0x48, 0x0d, 0x8c, 0x11, 0x9b, ++ 0xf9, 0xf6, 0x40, 0x6f, 0x98, 0xb8, 0xfc, 0x1a, 0x73, 0xd7, 0xd7, 0x94, ++ 0xde, 0xd3, 0xce, 0xba, 0x79, 0x8f, 0x69, 0xdb, 0x8f, 0x12, 0x97, 0xdc, ++ 0x57, 0x5a, 0x71, 0x1f, 0x1a, 0xd1, 0x15, 0x8a, 0x66, 0xca, 0x5c, 0xb5, ++ 0x6c, 0x0f, 0x2b, 0x40, 0x9b, 0xfc, 0x13, 0x65, 0xdb, 0x65, 0xea, 0x61, ++ 0x86, 0x1c, 0x19, 0x55, 0x5f, 0xb8, 0x0e, 0xd8, 0xb9, 0x12, 0x76, 0xb9, ++ 0x77, 0xad, 0x07, 0xde, 0x02, 0xbc, 0x3f, 0x26, 0xb7, 0x37, 0x70, 0x8c, ++ 0xcb, 0x47, 0x06, 0xe6, 0x2a, 0x21, 0x1c, 0x67, 0xe3, 0x83, 0x84, 0x5f, ++ 0x1d, 0x1f, 0xd4, 0xe3, 0x79, 0xe6, 0xd6, 0xcf, 0x22, 0xba, 0xd0, 0xad, ++ 0xb0, 0xb3, 0x02, 0x58, 0x49, 0x2c, 0x3f, 0xd1, 0xcb, 0x78, 0x3a, 0xbd, ++ 0xe6, 0x53, 0xca, 0x10, 0xeb, 0xbd, 0xc4, 0xad, 0x47, 0x3a, 0x29, 0xc7, ++ 0x29, 0x65, 0x75, 0x78, 0xe0, 0xc7, 0x6c, 0xc1, 0xc1, 0x28, 0xcb, 0xa7, ++ 0x34, 0xce, 0x33, 0xef, 0x30, 0x97, 0x7b, 0xdf, 0x99, 0x53, 0xd6, 0xec, ++ 0x8f, 0xd0, 0x6f, 0x5d, 0x9f, 0x5f, 0x3b, 0xaf, 0x41, 0x8c, 0x1c, 0x14, ++ 0x1d, 0x91, 0x18, 0x7e, 0xa7, 0x35, 0x7c, 0x40, 0xf6, 0x9c, 0x06, 0x16, ++ 0x5c, 0xd4, 0xb1, 0xd7, 0xc4, 0xcf, 0x56, 0x02, 0xed, 0x41, 0xc4, 0xcc, ++ 0x4b, 0xdc, 0xb1, 0xde, 0x37, 0x98, 0xcb, 0x56, 0xa7, 0x63, 0xc4, 0x21, ++ 0xd1, 0x4b, 0xf6, 0xb2, 0x2e, 0x94, 0x5d, 0xf4, 0x14, 0xf9, 0x45, 0x76, ++ 0xd1, 0xe1, 0xff, 0x97, 0xfc, 0x7f, 0x46, 0xff, 0xa8, 0xe5, 0x3c, 0xbf, ++ 0x4e, 0xff, 0x30, 0xf0, 0x4c, 0x51, 0x6a, 0x4c, 0xa9, 0x25, 0xc5, 0x4f, ++ 0xe2, 0x17, 0xc4, 0x00, 0x88, 0xc5, 0x95, 0xea, 0x85, 0x61, 0x1b, 0x63, ++ 0x8c, 0xf9, 0xa7, 0x4d, 0x93, 0x75, 0x9f, 0x7e, 0x04, 0x18, 0xa0, 0x9f, ++ 0xea, 0x4c, 0x78, 0x2d, 0xef, 0x71, 0xfa, 0xee, 0x9e, 0x61, 0x7c, 0x55, ++ 0x83, 0x7b, 0x75, 0x05, 0x8e, 0x62, 0xc2, 0xc3, 0xca, 0xcf, 0xd8, 0x4c, ++ 0x9c, 0x97, 0x78, 0x3e, 0xdb, 0x6a, 0x4c, 0x48, 0xcd, 0xdb, 0x06, 0xcb, ++ 0xc1, 0x90, 0x4a, 0x75, 0x27, 0x7d, 0xe8, 0xc5, 0x44, 0x05, 0x26, 0x82, ++ 0x72, 0xdf, 0x72, 0x72, 0x96, 0xda, 0x31, 0x0c, 0xd5, 0xc2, 0xfd, 0xdd, ++ 0x1a, 0xcc, 0x62, 0xbe, 0x4c, 0x23, 0x6e, 0x55, 0xaa, 0x7d, 0xb4, 0xcd, ++ 0x6e, 0x72, 0xe2, 0xf1, 0xe1, 0x0c, 0xb6, 0x25, 0x1a, 0xdb, 0x7c, 0xcc, ++ 0xf1, 0xf6, 0x98, 0x6e, 0x48, 0xcd, 0x8a, 0xe5, 0xd1, 0xe1, 0xd3, 0xd0, ++ 0xf7, 0xc8, 0x3a, 0xb1, 0x3b, 0x6d, 0xf9, 0xfa, 0x92, 0xf0, 0x6e, 0x4b, ++ 0x36, 0xa1, 0xe2, 0x40, 0x0d, 0x36, 0xd0, 0xae, 0x9b, 0x46, 0xc2, 0x28, ++ 0x1b, 0xb3, 0xf1, 0x30, 0x65, 0x8e, 0x33, 0x87, 0x8a, 0xbb, 0xac, 0x13, ++ 0x2e, 0xc6, 0x6d, 0xd5, 0x98, 0xde, 0xb7, 0x8e, 0x78, 0x7a, 0x96, 0xfe, ++ 0xf7, 0x38, 0x7d, 0xeb, 0x75, 0xc5, 0x3c, 0x61, 0x46, 0xe4, 0x7c, 0xa7, ++ 0x75, 0xf5, 0xb4, 0x5c, 0x4f, 0xb5, 0x46, 0xa7, 0xdd, 0x98, 0x58, 0xee, ++ 0xc3, 0xed, 0x86, 0xd4, 0x0c, 0x72, 0xb5, 0xed, 0xde, 0x84, 0x3c, 0x7b, ++ 0x8f, 0xcf, 0xe4, 0x3a, 0xdf, 0x1a, 0x71, 0xae, 0xbf, 0xe0, 0x75, 0x69, ++ 0xbd, 0xe7, 0xee, 0x32, 0xb9, 0x66, 0xe0, 0xfc, 0xc5, 0x33, 0xae, 0xef, ++ 0xca, 0x77, 0x33, 0xe2, 0x8a, 0x57, 0x94, 0xee, 0x7f, 0x0b, 0x13, 0x2b, ++ 0xe4, 0x7a, 0x76, 0xb1, 0x3d, 0xb4, 0x1a, 0xda, 0x26, 0x31, 0xea, 0x46, ++ 0x4b, 0xf3, 0x0a, 0x4c, 0xd4, 0x6a, 0xac, 0x45, 0x37, 0x3b, 0xdc, 0x48, ++ 0xdf, 0xc7, 0xab, 0x2d, 0x0a, 0x67, 0x8c, 0x34, 0xf2, 0x05, 0xe1, 0x21, ++ 0x8f, 0xec, 0x4b, 0x44, 0x2c, 0x15, 0x1d, 0x7e, 0x85, 0x2f, 0x66, 0xfe, ++ 0x68, 0x33, 0xb2, 0xe4, 0xc4, 0xe9, 0xac, 0x70, 0x20, 0xaf, 0x79, 0x59, ++ 0x77, 0xb9, 0x17, 0x29, 0xbe, 0x5b, 0xcd, 0x77, 0xcf, 0xb6, 0xe8, 0xf1, ++ 0x4e, 0xfa, 0x44, 0xd9, 0xac, 0xf4, 0x69, 0x61, 0x7d, 0x8b, 0x1e, 0xe9, ++ 0x72, 0xe9, 0x71, 0xcb, 0x75, 0x3b, 0x32, 0x13, 0x82, 0x8f, 0xb0, 0x96, ++ 0x09, 0x67, 0xe5, 0xca, 0xf1, 0xad, 0x64, 0xbb, 0xea, 0x9e, 0x6d, 0x27, ++ 0x2f, 0xcb, 0x9a, 0x25, 0xfd, 0x20, 0xa7, 0xe0, 0x8d, 0xb5, 0x93, 0x67, ++ 0x05, 0xb3, 0x6e, 0x50, 0x3d, 0x93, 0x82, 0x5b, 0x9b, 0x55, 0xff, 0xac, ++ 0xf8, 0x4e, 0x9f, 0xba, 0x77, 0x96, 0xbe, 0x91, 0xa3, 0xaf, 0x90, 0x4b, ++ 0x9f, 0x72, 0x7c, 0xc9, 0xa4, 0x2f, 0x59, 0xde, 0x17, 0x38, 0x87, 0x77, ++ 0x0d, 0x0b, 0xaf, 0xb8, 0xef, 0x0c, 0x60, 0x0d, 0x26, 0xca, 0xe0, 0x3d, ++ 0x96, 0xfc, 0x63, 0xdc, 0x48, 0xbc, 0x5a, 0x69, 0x94, 0xfc, 0x60, 0xdd, ++ 0x84, 0x8b, 0x38, 0xf0, 0x5d, 0x1b, 0xcb, 0x44, 0xcf, 0x2e, 0xe2, 0xf3, ++ 0xfd, 0xf6, 0xad, 0x21, 0x99, 0x3f, 0xf1, 0x5d, 0x67, 0xed, 0x9b, 0x3c, ++ 0x69, 0x21, 0x46, 0x7c, 0x9a, 0x1e, 0x5e, 0x41, 0xdf, 0x14, 0x8c, 0xa8, ++ 0x42, 0x45, 0x4d, 0x69, 0xed, 0xed, 0xf0, 0xb0, 0xd4, 0xd2, 0x67, 0x5b, ++ 0xb3, 0x23, 0x1a, 0x7c, 0x7c, 0x76, 0x9c, 0x5c, 0xbb, 0xaf, 0xa5, 0xd4, ++ 0x77, 0xe3, 0xc4, 0xe5, 0xd8, 0x1b, 0xf4, 0xa1, 0xca, 0x88, 0x63, 0x30, ++ 0xe8, 0x27, 0xb6, 0x6d, 0x59, 0xec, 0xf3, 0x24, 0xfd, 0x5c, 0xc6, 0xcb, ++ 0x54, 0x94, 0x30, 0x99, 0x00, 0xe9, 0x2b, 0x8d, 0x55, 0xc9, 0xb1, 0xb6, ++ 0xb5, 0x6c, 0xc6, 0xb5, 0x83, 0x7e, 0xf5, 0xe3, 0xec, 0x66, 0x3b, 0x52, ++ 0xc3, 0x76, 0xf4, 0xf9, 0xf2, 0x45, 0x79, 0x1b, 0x26, 0xde, 0xac, 0x28, ++ 0xad, 0xd7, 0x68, 0xb8, 0x7b, 0xd8, 0x85, 0xda, 0xc5, 0xfb, 0xcd, 0x13, ++ 0x11, 0x98, 0xcd, 0xcc, 0x1a, 0x6b, 0x15, 0x96, 0x3b, 0x7e, 0x2e, 0x63, ++ 0x68, 0x08, 0x32, 0xe6, 0x6e, 0x4c, 0xa6, 0x10, 0xcd, 0xc9, 0x7a, 0x9d, ++ 0x07, 0xdf, 0xca, 0xa6, 0xb1, 0xae, 0xf8, 0xe1, 0x62, 0x1f, 0x4b, 0xed, ++ 0x3c, 0x6c, 0xe7, 0xc5, 0xe4, 0xc4, 0xe7, 0xe5, 0x0b, 0x51, 0xe6, 0xc3, ++ 0x94, 0x4d, 0x9e, 0x09, 0x66, 0x0b, 0x56, 0x7f, 0x56, 0x37, 0xba, 0x46, ++ 0xe5, 0x5c, 0x40, 0x89, 0xdb, 0x36, 0x98, 0x9a, 0xb5, 0x32, 0x1d, 0xc0, ++ 0xc2, 0x98, 0x85, 0x93, 0x57, 0x54, 0xe3, 0xdc, 0x58, 0x03, 0xee, 0x1c, ++ 0xf6, 0xe1, 0x34, 0xfd, 0xfd, 0xf2, 0x35, 0xb8, 0x25, 0x0c, 0x6c, 0xaf, ++ 0x86, 0xd4, 0x0e, 0xb1, 0x8e, 0x41, 0x05, 0x4a, 0x1a, 0x4b, 0x6d, 0x54, ++ 0x12, 0x07, 0xe8, 0xba, 0x26, 0x19, 0x8b, 0x9c, 0xc2, 0xf7, 0x6c, 0x62, ++ 0x7f, 0xd0, 0x9d, 0x6e, 0x57, 0x1e, 0x67, 0x4f, 0x70, 0xb3, 0xb3, 0x87, ++ 0xe8, 0x9a, 0xec, 0x53, 0xee, 0xd9, 0x0b, 0x31, 0xe2, 0x8b, 0x78, 0x55, ++ 0xb8, 0x54, 0x38, 0x7f, 0xd4, 0x2e, 0x33, 0x36, 0xab, 0xdd, 0xe4, 0xd1, ++ 0x5d, 0x13, 0xe7, 0xb9, 0xf6, 0x3c, 0xbf, 0xee, 0x58, 0xe4, 0xd5, 0x81, ++ 0xfc, 0x1b, 0x9f, 0xcb, 0x07, 0x23, 0x8b, 0x6b, 0x56, 0xc2, 0xa7, 0x5e, ++ 0xf5, 0x26, 0x71, 0x65, 0xb7, 0x29, 0xb1, 0x78, 0x2c, 0x2c, 0x6b, 0xa0, ++ 0x9e, 0x66, 0x85, 0xbb, 0xe5, 0x0c, 0x48, 0xc8, 0xc6, 0x0d, 0x66, 0xc9, ++ 0x1f, 0xd6, 0xb4, 0x94, 0xa1, 0x87, 0x1c, 0x5b, 0x96, 0xf0, 0x13, 0x33, ++ 0x82, 0xf8, 0x89, 0x29, 0xbc, 0xea, 0x5b, 0x9c, 0x4f, 0xd9, 0xd3, 0x2e, ++ 0xed, 0x3f, 0x3f, 0xf5, 0x7b, 0x3c, 0xbb, 0xb4, 0x07, 0x6d, 0x22, 0xb3, ++ 0x1c, 0xbe, 0xb7, 0x93, 0x06, 0x9e, 0x63, 0x0d, 0xf3, 0x6c, 0xf6, 0x5a, ++ 0xa4, 0x96, 0xe9, 0x19, 0x99, 0x7f, 0x89, 0xb3, 0x7f, 0x68, 0xe9, 0xc1, ++ 0x1d, 0xa3, 0x2e, 0x72, 0x96, 0xac, 0xa7, 0x5a, 0xd8, 0x57, 0x23, 0x78, ++ 0xd7, 0x8e, 0xfe, 0x51, 0xaf, 0x3a, 0x3e, 0xec, 0xc1, 0xc3, 0x1d, 0xf7, ++ 0x63, 0x59, 0xf3, 0xad, 0x80, 0xe3, 0x83, 0xf2, 0xf9, 0x9b, 0xe8, 0x92, ++ 0x38, 0x76, 0xc9, 0xfa, 0xb2, 0x82, 0xbf, 0x59, 0xf4, 0x80, 0xef, 0x7d, ++ 0xf6, 0xbf, 0x75, 0xd0, 0xa3, 0x4e, 0x65, 0x7f, 0x61, 0x1f, 0x09, 0x49, ++ 0x9e, 0x23, 0xcf, 0xaa, 0x60, 0xd5, 0x48, 0x5b, 0x99, 0x43, 0x3f, 0x6b, ++ 0xef, 0x6e, 0x0c, 0x52, 0xae, 0x57, 0x9d, 0xbe, 0x4e, 0x2c, 0xca, 0xef, ++ 0x57, 0xd5, 0x43, 0x1a, 0xeb, 0x1a, 0xe6, 0x19, 0x57, 0x74, 0xa0, 0x7a, ++ 0xf6, 0xc2, 0xfc, 0xe1, 0x9c, 0x26, 0x6b, 0xa7, 0x9c, 0x2b, 0x72, 0x7f, ++ 0x37, 0xde, 0xcd, 0x2a, 0xbc, 0xe3, 0xf8, 0x60, 0x37, 0x1a, 0xf2, 0x55, ++ 0x8b, 0x47, 0x8f, 0x9c, 0x76, 0xe5, 0x0e, 0xc6, 0xb8, 0x7a, 0x70, 0x17, ++ 0x75, 0xa9, 0x32, 0xa4, 0x26, 0xba, 0x98, 0xe3, 0xc8, 0xbd, 0x82, 0x56, ++ 0xf2, 0xb3, 0xa5, 0xbe, 0xae, 0x82, 0xac, 0x3d, 0x7a, 0x8c, 0x18, 0xb6, ++ 0x8f, 0xc6, 0x3a, 0xfd, 0x2e, 0xf1, 0xc3, 0x18, 0x6e, 0x9f, 0xbc, 0xd2, ++ 0x0b, 0x9f, 0xf4, 0x15, 0xc6, 0xcd, 0x43, 0x1e, 0xf5, 0x56, 0xd6, 0xc0, ++ 0xf3, 0x59, 0xd7, 0x0a, 0x37, 0x9e, 0xb1, 0x1f, 0x0e, 0xf5, 0xe3, 0x1a, ++ 0xb3, 0x1d, 0xb7, 0xd1, 0x07, 0x37, 0x34, 0xf4, 0x93, 0x07, 0x32, 0xd8, ++ 0x5a, 0x6b, 0x23, 0x9a, 0x28, 0xda, 0xdd, 0x21, 0xb1, 0xa3, 0x42, 0x1b, ++ 0xef, 0xd7, 0x24, 0x64, 0x2d, 0x9c, 0xde, 0xc6, 0xb8, 0xd0, 0x0c, 0x9d, ++ 0xa8, 0x5d, 0xee, 0x95, 0x31, 0x6b, 0x98, 0x0f, 0x94, 0x49, 0xbe, 0x13, ++ 0x90, 0xbc, 0xe7, 0xf3, 0xf2, 0x58, 0x76, 0x85, 0x61, 0xc4, 0xaf, 0x75, ++ 0x35, 0x0c, 0xcf, 0xd0, 0x67, 0xd7, 0x37, 0x5f, 0xf8, 0xde, 0x92, 0x8d, ++ 0x4c, 0x94, 0x37, 0x4f, 0xd9, 0x73, 0xc1, 0x01, 0x04, 0x9b, 0x2f, 0x9c, ++ 0xfb, 0xa5, 0x3e, 0x44, 0x66, 0xb9, 0x2f, 0xf7, 0x62, 0xc1, 0x5b, 0xf0, ++ 0x1a, 0xc7, 0x08, 0x63, 0x0b, 0x71, 0xad, 0x7b, 0xd4, 0xfd, 0x59, 0xbe, ++ 0x15, 0x10, 0x5f, 0xfe, 0x4c, 0xff, 0x6d, 0xa3, 0xb1, 0x36, 0xdf, 0xa2, ++ 0xfe, 0xb7, 0x4d, 0x7e, 0xd6, 0x57, 0xdf, 0x90, 0xe0, 0xa9, 0xf4, 0x27, ++ 0x6b, 0xf1, 0x4b, 0xf6, 0x0d, 0xe3, 0x2e, 0xa7, 0xbf, 0xef, 0x79, 0x25, ++ 0x86, 0x65, 0xad, 0x67, 0x63, 0xb3, 0x85, 0x9f, 0xa4, 0xee, 0xb4, 0xb7, ++ 0x39, 0x36, 0xf8, 0xa6, 0x23, 0x73, 0x5b, 0xc3, 0x9c, 0xe3, 0xef, 0xa5, ++ 0xb8, 0x4d, 0xd1, 0xd7, 0x93, 0xf8, 0x51, 0xd1, 0xc4, 0x0f, 0x8b, 0x4d, ++ 0xe4, 0xd8, 0x38, 0x39, 0xd6, 0xa0, 0xef, 0x47, 0x18, 0x0f, 0x5f, 0x22, ++ 0x3f, 0xc8, 0xf9, 0x0c, 0x4d, 0x79, 0x46, 0x2b, 0x55, 0xd9, 0xa8, 0xc8, ++ 0x36, 0xaf, 0x95, 0x62, 0xec, 0x24, 0x32, 0x21, 0xbe, 0x9b, 0x2b, 0xf9, ++ 0x7f, 0xbc, 0xe5, 0x76, 0xe0, 0x11, 0xcb, 0x5b, 0xb1, 0x16, 0x78, 0x67, ++ 0xb8, 0xc3, 0xf1, 0x87, 0x8b, 0xd2, 0x47, 0x5a, 0x7f, 0xd3, 0x60, 0xe3, ++ 0x05, 0x53, 0xd6, 0x3a, 0x9f, 0x6d, 0xbd, 0xa7, 0xc1, 0xcd, 0xbc, 0x4d, ++ 0xc6, 0x94, 0xbd, 0xec, 0xd2, 0x9e, 0x10, 0x71, 0xd7, 0x57, 0xb3, 0xd6, ++ 0xf2, 0x86, 0xd6, 0x7a, 0xd4, 0x8a, 0xa1, 0xcd, 0xf4, 0x3d, 0x03, 0xa9, ++ 0x21, 0xcb, 0x57, 0xb7, 0x36, 0x82, 0xd1, 0xa1, 0x25, 0x4c, 0x6e, 0x42, ++ 0xd3, 0x01, 0xe0, 0x5f, 0x87, 0xc2, 0x68, 0x1c, 0x8b, 0xf6, 0xfe, 0xa9, ++ 0x2b, 0xda, 0xf7, 0x86, 0x4b, 0x9e, 0xbd, 0xd2, 0x7a, 0xb9, 0x53, 0x4f, ++ 0xbc, 0xde, 0xba, 0xda, 0xb9, 0xfe, 0xba, 0xf5, 0xb2, 0x7c, 0x27, 0xb2, ++ 0x33, 0xde, 0x85, 0x09, 0x97, 0x8d, 0x6f, 0x27, 0x5c, 0xf8, 0x9a, 0xf9, ++ 0x0e, 0x63, 0x4b, 0xd1, 0x37, 0xfe, 0xb3, 0x70, 0xb9, 0x60, 0x2a, 0xf6, ++ 0x32, 0x4e, 0x3b, 0xf8, 0x0c, 0xf4, 0x9c, 0x90, 0x21, 0xfb, 0x68, 0x12, ++ 0x4f, 0x60, 0x8e, 0x00, 0xdf, 0x0b, 0x8c, 0x91, 0x3b, 0xb3, 0x35, 0xd8, ++ 0x35, 0x5c, 0x8b, 0x81, 0xe1, 0x1a, 0x1c, 0x64, 0xec, 0x3f, 0xcb, 0xd8, ++ 0xff, 0xba, 0xa9, 0x2f, 0x8c, 0xb8, 0xac, 0xc7, 0x99, 0xdb, 0x11, 0xbf, ++ 0xf4, 0xce, 0x37, 0x5c, 0xfa, 0x91, 0xeb, 0x5d, 0x41, 0xe4, 0x1b, 0xf4, ++ 0x9e, 0x6f, 0x33, 0x67, 0x5a, 0x9e, 0x96, 0xf1, 0x17, 0x16, 0xe5, 0x38, ++ 0xd5, 0x7a, 0x99, 0xc3, 0xbd, 0x6f, 0xb5, 0x36, 0x4d, 0x97, 0x78, 0xbb, ++ 0x71, 0xda, 0xf2, 0xfe, 0x70, 0xad, 0x60, 0xe8, 0x4d, 0x78, 0x90, 0xdc, ++ 0xf4, 0xf3, 0xa1, 0x72, 0xfa, 0x5f, 0xd4, 0x5c, 0xa5, 0xa2, 0xf4, 0x2b, ++ 0x69, 0x73, 0xa6, 0x35, 0x9e, 0x7f, 0x0a, 0x73, 0x1e, 0xd9, 0x8f, 0x78, ++ 0x82, 0xf9, 0x49, 0xa3, 0xf5, 0x22, 0x9e, 0x92, 0xad, 0x10, 0x47, 0x68, ++ 0xd1, 0xb1, 0x21, 0x0f, 0xdc, 0x3d, 0xe4, 0x5d, 0x88, 0x38, 0x6b, 0xf1, ++ 0xa2, 0xdb, 0xbd, 0xd4, 0x4d, 0xb7, 0x32, 0x8c, 0xe3, 0xeb, 0xcc, 0x1a, ++ 0x74, 0x7d, 0xc3, 0xc3, 0xe7, 0x52, 0xa3, 0xfd, 0x63, 0x6b, 0x61, 0x10, ++ 0x73, 0xcc, 0xe3, 0x88, 0x81, 0x4e, 0xfd, 0x14, 0xc8, 0xcf, 0x02, 0x0f, ++ 0x11, 0x5b, 0xaa, 0xd7, 0xfc, 0xd6, 0x9e, 0x77, 0x62, 0x5b, 0x0b, 0x3c, ++ 0x3c, 0xae, 0xc8, 0x17, 0xa5, 0xfd, 0xdb, 0x83, 0xe4, 0x81, 0x83, 0x45, ++ 0xcf, 0x05, 0xfd, 0xc7, 0x2c, 0x97, 0xcb, 0x05, 0x57, 0xf3, 0x51, 0x94, ++ 0xf6, 0xd4, 0xa0, 0x69, 0xcc, 0x25, 0xb4, 0xfd, 0x92, 0x13, 0x9c, 0x6a, ++ 0x4d, 0x7c, 0x5f, 0xea, 0xec, 0x5f, 0x3a, 0xb5, 0xbc, 0x9b, 0xe3, 0xdd, ++ 0x9c, 0xd5, 0x7b, 0x58, 0x27, 0x6b, 0x2b, 0x69, 0x03, 0x3b, 0x27, 0x58, ++ 0xf0, 0x49, 0xeb, 0xbb, 0xe3, 0xb2, 0xde, 0xad, 0x47, 0x8e, 0x2a, 0xbf, ++ 0x4a, 0x0d, 0xe9, 0xf1, 0x1e, 0xca, 0x7c, 0xd0, 0xd0, 0x7b, 0x67, 0xa0, ++ 0xf7, 0x9d, 0x74, 0x77, 0xe3, 0xa1, 0x62, 0xc9, 0x66, 0xa5, 0x39, 0x9c, ++ 0x5f, 0xcc, 0x6d, 0xde, 0xa3, 0xed, 0x24, 0x5f, 0xb1, 0x6d, 0x63, 0x4d, ++ 0x3b, 0xb2, 0x39, 0xc9, 0x47, 0xe4, 0xfe, 0xc7, 0xad, 0x4d, 0xac, 0xa5, ++ 0xb6, 0x0c, 0x91, 0x4f, 0xc9, 0xfd, 0xfb, 0x8a, 0xde, 0x85, 0x8c, 0x23, ++ 0x16, 0x6b, 0xef, 0x9c, 0x6e, 0x5a, 0xa5, 0x5c, 0x86, 0x6d, 0x97, 0x72, ++ 0x19, 0x3f, 0xb6, 0x51, 0x97, 0x8c, 0x2a, 0xbd, 0xaf, 0xb1, 0x5f, 0x6d, ++ 0xff, 0x92, 0xcc, 0x7a, 0x8a, 0x6c, 0x45, 0x9c, 0x3a, 0xeb, 0x8c, 0x73, ++ 0xdc, 0x5c, 0x5c, 0x1f, 0xcd, 0x2e, 0xe9, 0x12, 0x8d, 0xef, 0x40, 0xc9, ++ 0xbf, 0x62, 0xf9, 0x72, 0x4c, 0x2c, 0xea, 0xef, 0xe3, 0x1c, 0x7d, 0x6d, ++ 0x90, 0xdc, 0xd2, 0x52, 0x9a, 0xaf, 0x86, 0xfc, 0x55, 0xc8, 0xd4, 0xb6, ++ 0x51, 0xc6, 0x60, 0xa0, 0x71, 0xa8, 0x0d, 0xa3, 0x9c, 0xd7, 0xeb, 0x66, ++ 0xc3, 0x81, 0x8b, 0x87, 0x0c, 0xac, 0x9f, 0x95, 0x3e, 0xe7, 0x5b, 0x77, ++ 0x8e, 0xdf, 0xb4, 0xb8, 0x06, 0xb0, 0x19, 0x07, 0x89, 0xf9, 0x7d, 0x43, ++ 0x25, 0x3f, 0xbd, 0x32, 0xef, 0x5d, 0x40, 0xe9, 0xec, 0x88, 0x56, 0xcd, ++ 0x71, 0x3e, 0x1a, 0xbc, 0xcf, 0x9e, 0x5f, 0x2e, 0xfe, 0xd1, 0x89, 0xf1, ++ 0x03, 0x01, 0xe6, 0x3e, 0x41, 0x2c, 0x6f, 0xde, 0xc7, 0x77, 0x9b, 0x70, ++ 0xef, 0xe1, 0x0d, 0x98, 0xf8, 0x73, 0x0f, 0xfe, 0xe7, 0x50, 0x06, 0x2b, ++ 0x9b, 0xbf, 0x84, 0xf9, 0xbf, 0xd0, 0x70, 0x76, 0xc8, 0x8f, 0x93, 0xd4, ++ 0xaf, 0xcb, 0xe9, 0x42, 0xe2, 0x90, 0x31, 0x9c, 0x33, 0x9d, 0x3d, 0x9e, ++ 0x67, 0x72, 0x8c, 0x61, 0xc6, 0xd1, 0x53, 0x94, 0xe7, 0xc9, 0xf3, 0x67, ++ 0x9e, 0x9c, 0xb5, 0x60, 0x72, 0x8d, 0x57, 0x79, 0x47, 0x33, 0x92, 0x4b, ++ 0x7d, 0xd5, 0x0b, 0x59, 0x97, 0xb4, 0x58, 0x07, 0x45, 0x10, 0xa5, 0xcc, ++ 0xc6, 0x90, 0x9c, 0x75, 0x0a, 0x05, 0x84, 0x5f, 0x27, 0xa9, 0x93, 0x6b, ++ 0xb6, 0x3e, 0xe0, 0x99, 0xfd, 0x6f, 0xc4, 0x8c, 0x30, 0xaf, 0x94, 0xd7, ++ 0xf1, 0x8b, 0x0b, 0xc7, 0x1d, 0xf1, 0xc1, 0x27, 0x63, 0xd3, 0x8c, 0xc4, ++ 0xaf, 0x2a, 0x72, 0x9c, 0x75, 0xe8, 0x62, 0x0c, 0x1d, 0xfa, 0x2b, 0x9f, ++ 0x6c, 0xce, 0x0c, 0x16, 0x4a, 0x7e, 0x1b, 0xc9, 0x57, 0xfa, 0x24, 0x9f, ++ 0xb9, 0x7b, 0xa8, 0xf4, 0x3d, 0x76, 0xfe, 0xbb, 0x57, 0xd5, 0x8c, 0xea, ++ 0x71, 0xe2, 0xac, 0x83, 0x7b, 0x46, 0xf3, 0xff, 0x93, 0x1e, 0x0b, 0x73, ++ 0x8e, 0x3c, 0xfb, 0xd8, 0x97, 0xd8, 0xe5, 0x49, 0x3b, 0x73, 0x83, 0xd8, ++ 0x2e, 0x14, 0xf8, 0x21, 0xe7, 0x62, 0x8c, 0xef, 0x7c, 0x87, 0xf2, 0x3f, ++ 0x4d, 0xbd, 0xee, 0x9d, 0xdd, 0xc9, 0x36, 0xce, 0x33, 0x0c, 0xe4, 0x2c, ++ 0xdd, 0xb3, 0x78, 0x3e, 0x73, 0x00, 0x52, 0x87, 0x58, 0x78, 0x33, 0x79, ++ 0x1b, 0xae, 0x1e, 0xd6, 0x33, 0x16, 0xf3, 0xb7, 0xae, 0x20, 0x94, 0x27, ++ 0x2d, 0xfe, 0xfb, 0xeb, 0xd6, 0x77, 0xb3, 0x26, 0x73, 0x86, 0x68, 0xe4, ++ 0x24, 0xdb, 0x5b, 0x9e, 0x7a, 0x3c, 0x38, 0xe6, 0xc6, 0xc9, 0x10, 0xf3, ++ 0x62, 0xb5, 0x54, 0xbf, 0x4a, 0xdb, 0xa5, 0xcf, 0x95, 0x88, 0xd4, 0x44, ++ 0x53, 0x64, 0x61, 0xa9, 0x77, 0xbd, 0xf9, 0x96, 0xfb, 0xb1, 0x6f, 0xc4, ++ 0xc5, 0x9a, 0x20, 0x82, 0x4c, 0x0d, 0x13, 0x7f, 0xa3, 0xb1, 0xf7, 0x34, ++ 0x3e, 0xb6, 0xe7, 0x96, 0xcb, 0xfb, 0xd1, 0xd4, 0x69, 0x7c, 0x6a, 0xbb, ++ 0x0d, 0xe3, 0xc4, 0x14, 0x8c, 0xb9, 0x93, 0x68, 0xec, 0x3b, 0x87, 0xf7, ++ 0x38, 0xff, 0x7a, 0x44, 0x73, 0xbb, 0x99, 0x33, 0x46, 0x83, 0x1e, 0x84, ++ 0x30, 0x17, 0x72, 0x63, 0x93, 0x29, 0x6b, 0xf5, 0x7a, 0xdf, 0x51, 0xe8, ++ 0xbd, 0xef, 0xa8, 0xc6, 0x9e, 0x0f, 0x31, 0x6f, 0x4f, 0xd4, 0xc8, 0xb8, ++ 0x0a, 0xa9, 0xcb, 0x1a, 0x4f, 0x94, 0x43, 0x6f, 0x2b, 0x53, 0x46, 0xaa, ++ 0xce, 0xfd, 0xcf, 0xf6, 0x7c, 0xe8, 0x53, 0xdb, 0x88, 0x7d, 0xca, 0xbc, ++ 0xc9, 0x08, 0x4f, 0x32, 0xc7, 0xef, 0xc1, 0x92, 0x6c, 0xe7, 0xa8, 0xbf, ++ 0x49, 0x19, 0x4a, 0xb5, 0xcc, 0x6e, 0xca, 0xf6, 0x53, 0xe6, 0x0d, 0xdb, ++ 0x12, 0xa7, 0xed, 0xcc, 0x72, 0x39, 0xc3, 0xa7, 0x55, 0x96, 0xf6, 0x04, ++ 0xc4, 0xff, 0x6f, 0xc2, 0xcd, 0xd9, 0x30, 0xed, 0xb4, 0x94, 0xdf, 0x95, ++ 0x11, 0xb3, 0x25, 0x27, 0x9a, 0xbb, 0xc4, 0x0d, 0xcb, 0x35, 0x6d, 0x84, ++ 0xb0, 0x93, 0x79, 0xf7, 0x0e, 0x87, 0x3b, 0xe0, 0x73, 0xaf, 0x6d, 0xc6, ++ 0xd6, 0xf1, 0x7f, 0xf6, 0x71, 0xfe, 0xd6, 0x4d, 0x9b, 0xb2, 0xd6, 0x6e, ++ 0x21, 0x9c, 0x76, 0xa3, 0xfa, 0x0a, 0xfd, 0xc4, 0x00, 0x2c, 0x91, 0xa5, ++ 0xeb, 0x62, 0x77, 0x3f, 0x2e, 0x59, 0x93, 0x39, 0xe7, 0x47, 0x2c, 0x73, ++ 0xda, 0xdd, 0x87, 0xd5, 0x6b, 0x10, 0xac, 0x4a, 0xc7, 0x3a, 0xaa, 0x54, ++ 0xac, 0xf3, 0x35, 0x15, 0x87, 0x7f, 0xd6, 0xf2, 0x6a, 0x6b, 0xfd, 0x9a, ++ 0x7f, 0xb6, 0x49, 0xab, 0x9c, 0x35, 0x35, 0xdf, 0xec, 0x6d, 0x70, 0x8f, ++ 0xf8, 0x89, 0xc9, 0x7a, 0xaa, 0x41, 0x95, 0x73, 0x4e, 0x92, 0xcc, 0x79, ++ 0x09, 0xd0, 0x83, 0xdb, 0x51, 0x3e, 0x18, 0xe5, 0xbd, 0x7e, 0xcc, 0x87, ++ 0x4b, 0xf9, 0x31, 0xf5, 0x91, 0xfc, 0x9a, 0x35, 0xc4, 0x6d, 0xe8, 0x22, ++ 0xff, 0x74, 0xb4, 0xa4, 0xe0, 0x1a, 0x72, 0xf0, 0xdc, 0xf7, 0x62, 0x32, ++ 0x8d, 0x02, 0xeb, 0xb8, 0x23, 0x89, 0x3a, 0xe6, 0x46, 0x26, 0x06, 0x8a, ++ 0xe2, 0xa7, 0xc2, 0x9b, 0xb4, 0xc6, 0x15, 0xf5, 0x18, 0x9a, 0xe2, 0x17, ++ 0x72, 0x9d, 0x87, 0x3e, 0xb2, 0x8b, 0x7e, 0x15, 0x16, 0xff, 0x25, 0xff, ++ 0x59, 0x0e, 0x2e, 0xfd, 0xb2, 0x35, 0xe5, 0xe0, 0xd1, 0x27, 0xac, 0x9f, ++ 0x7e, 0xe9, 0x93, 0x3a, 0x49, 0xce, 0x06, 0x56, 0x8f, 0x2e, 0xd5, 0xa8, ++ 0xeb, 0xef, 0xae, 0x46, 0x13, 0xfb, 0x0c, 0x2f, 0xee, 0xa3, 0x2a, 0x1c, ++ 0x4b, 0x34, 0xe3, 0xb9, 0x61, 0x39, 0x43, 0xe7, 0xac, 0x25, 0xe8, 0x61, ++ 0xac, 0x43, 0x2e, 0xe8, 0x22, 0xc7, 0x6d, 0xc1, 0xc3, 0xc1, 0x39, 0xdf, ++ 0xb1, 0xa4, 0xb3, 0x66, 0xeb, 0xeb, 0x26, 0xc7, 0x1c, 0xcc, 0x7e, 0x09, ++ 0x91, 0x8b, 0xe0, 0xbd, 0x25, 0x49, 0x1f, 0x1b, 0x2e, 0x63, 0x9b, 0x75, ++ 0xac, 0x59, 0xdb, 0xf1, 0x2d, 0xe7, 0x6c, 0x6d, 0x04, 0xbb, 0xe9, 0xef, ++ 0xbb, 0xa6, 0xe2, 0xd8, 0x4d, 0xf9, 0x76, 0x17, 0x97, 0x64, 0xbe, 0x50, ++ 0xd6, 0x2f, 0x92, 0x51, 0x6c, 0xf2, 0x7f, 0x93, 0x91, 0xf5, 0x29, 0xf3, ++ 0xa6, 0xc1, 0x6c, 0x37, 0x7e, 0x9a, 0xfd, 0xac, 0xdf, 0x7d, 0xcc, 0x77, ++ 0xad, 0x29, 0xe9, 0x5f, 0xc6, 0x96, 0x31, 0xa2, 0x5d, 0x55, 0x4a, 0xc6, ++ 0x89, 0xb3, 0x8e, 0xfb, 0x43, 0xc7, 0x92, 0x73, 0xc4, 0xeb, 0x70, 0xd2, ++ 0x8c, 0xa3, 0xbb, 0x63, 0x8e, 0xf3, 0x61, 0xe0, 0xd1, 0xec, 0xc5, 0x92, ++ 0xeb, 0x7a, 0x4f, 0x24, 0xdb, 0xf0, 0x58, 0xd6, 0xee, 0xf7, 0xa7, 0x6d, ++ 0x7b, 0x57, 0x8b, 0x11, 0xdc, 0xaa, 0x64, 0xdd, 0x3c, 0x22, 0xfb, 0x42, ++ 0xde, 0xb2, 0x2b, 0x22, 0x18, 0x62, 0xed, 0x55, 0xcc, 0x36, 0xf6, 0xbc, ++ 0x46, 0x9c, 0x9e, 0x60, 0x5c, 0xcc, 0xa9, 0x2e, 0xd6, 0x92, 0x7f, 0x53, ++ 0x29, 0xeb, 0x51, 0x3b, 0x8b, 0xdb, 0xe1, 0x1a, 0xfc, 0x46, 0xa5, 0xd4, ++ 0x2c, 0xe5, 0xac, 0xd9, 0x1f, 0xcc, 0x8a, 0xcc, 0x76, 0xbf, 0x8f, 0x7d, ++ 0x75, 0xb4, 0x18, 0x29, 0x53, 0x69, 0xce, 0x19, 0xee, 0x32, 0xca, 0xfe, ++ 0x00, 0xdb, 0x5a, 0x79, 0xb1, 0xe5, 0x9e, 0x4a, 0xc1, 0xa4, 0xdd, 0xcc, ++ 0xf1, 0x37, 0x9c, 0xef, 0x87, 0x8c, 0x34, 0x78, 0xcc, 0xe9, 0x87, 0xb9, ++ 0x2d, 0xf9, 0xbf, 0x17, 0xbb, 0xb3, 0x21, 0x3c, 0x9e, 0x6d, 0x6c, 0x7b, ++ 0x1d, 0x1e, 0xc6, 0xb3, 0xe8, 0x28, 0xe7, 0x8b, 0x97, 0xda, 0x84, 0x30, ++ 0x79, 0xfe, 0xb3, 0xd8, 0xa8, 0xb4, 0x8e, 0xfc, 0xbc, 0x53, 0x37, 0x68, ++ 0xe4, 0x89, 0x52, 0x2d, 0x44, 0xfc, 0xf0, 0x3d, 0xc0, 0x79, 0x7d, 0x87, ++ 0xf3, 0xea, 0xe2, 0xbc, 0xbe, 0x60, 0xfe, 0x48, 0xf2, 0x1e, 0xef, 0xce, ++ 0x64, 0x44, 0xf6, 0xd2, 0x2c, 0x26, 0x1c, 0x4e, 0x9b, 0xa1, 0xa4, 0x07, ++ 0xaf, 0x0e, 0xca, 0x1a, 0xf8, 0xeb, 0xad, 0x2f, 0x65, 0xed, 0x75, 0x33, ++ 0x89, 0xc6, 0xae, 0x77, 0xc8, 0xe5, 0xd6, 0x37, 0x74, 0x73, 0x1e, 0xf5, ++ 0xc8, 0x8d, 0x7d, 0x07, 0xf3, 0x35, 0x8d, 0xc1, 0xd7, 0x61, 0x79, 0x0f, ++ 0x26, 0xef, 0x47, 0x6a, 0x8c, 0xb5, 0xc7, 0x9a, 0xbf, 0x66, 0xe0, 0x25, ++ 0xe1, 0x36, 0x1a, 0x17, 0x5e, 0xc0, 0x7f, 0xc5, 0xfc, 0x45, 0x51, 0xf3, ++ 0x05, 0x48, 0x9b, 0x52, 0xad, 0x1f, 0x9d, 0xbe, 0x83, 0x7c, 0x4d, 0xd7, ++ 0x73, 0x2d, 0x71, 0x5a, 0x63, 0xbc, 0x9b, 0x7d, 0x4e, 0x6c, 0x66, 0x7d, ++ 0xed, 0x9c, 0x5b, 0x85, 0xef, 0x28, 0xe3, 0x22, 0x3e, 0x22, 0xed, 0xff, ++ 0xb1, 0xd5, 0xc8, 0x47, 0xe0, 0x66, 0x2e, 0xd4, 0x15, 0xd2, 0xdb, 0xe4, ++ 0x4c, 0xe1, 0xd1, 0x6c, 0x13, 0xb9, 0xa1, 0xb1, 0x23, 0xae, 0xbe, 0x25, ++ 0x7b, 0xa9, 0x4e, 0x90, 0x95, 0xb1, 0xdd, 0xa1, 0xac, 0xde, 0x75, 0x14, ++ 0x8d, 0x9d, 0x7e, 0x75, 0x13, 0xba, 0x6a, 0x1a, 0x7b, 0x1e, 0x47, 0x94, ++ 0x1c, 0xaa, 0xc7, 0xe7, 0x51, 0xea, 0x67, 0x55, 0x9e, 0x64, 0x56, 0x2b, ++ 0xd8, 0x93, 0xc5, 0xe3, 0x41, 0x37, 0x2e, 0x6d, 0x36, 0x16, 0x26, 0xb1, ++ 0xe4, 0x2f, 0xa5, 0x36, 0xeb, 0xf2, 0x6c, 0xef, 0x36, 0x9c, 0x9a, 0xde, ++ 0x53, 0xab, 0x31, 0x16, 0xb6, 0x63, 0x5b, 0x56, 0xd6, 0x19, 0x68, 0x17, ++ 0xc6, 0x66, 0x47, 0x6c, 0x3b, 0x7a, 0xf3, 0x71, 0xec, 0xcb, 0x45, 0xf7, ++ 0xec, 0x82, 0xc1, 0x7b, 0xd1, 0xc8, 0x56, 0xe2, 0xc3, 0xce, 0xa2, 0x0b, ++ 0x91, 0xda, 0x30, 0x6b, 0xed, 0x20, 0xff, 0x4a, 0x35, 0xd1, 0x4b, 0xac, ++ 0x89, 0x5e, 0x65, 0xac, 0xf9, 0x17, 0xeb, 0xdd, 0x55, 0x13, 0x36, 0x66, ++ 0x12, 0xd7, 0xe2, 0x8c, 0x93, 0xe3, 0x85, 0x59, 0x9b, 0x09, 0xaf, 0x80, ++ 0xf5, 0xb3, 0x57, 0x6d, 0x1d, 0xb1, 0xbc, 0x77, 0xb7, 0x84, 0xc9, 0x71, ++ 0x92, 0xb7, 0xba, 0xfe, 0xdc, 0x4d, 0x7b, 0x4c, 0x19, 0xfd, 0xd8, 0x98, ++ 0xe8, 0x47, 0xaf, 0xf9, 0x5d, 0x94, 0xd7, 0x5a, 0xb6, 0xdf, 0x28, 0xad, ++ 0x4b, 0x9c, 0x6e, 0x69, 0x47, 0xf4, 0x11, 0xc9, 0x17, 0xce, 0xb4, 0x6a, ++ 0x83, 0x2e, 0xc1, 0x0b, 0xf6, 0x9f, 0xf8, 0xea, 0x6a, 0xe6, 0x1e, 0x55, ++ 0x8b, 0xbc, 0x7f, 0x59, 0x3e, 0x48, 0xdf, 0x02, 0xeb, 0x5b, 0xf8, 0xde, ++ 0xba, 0x82, 0x79, 0x13, 0x31, 0x26, 0xb5, 0xa6, 0x0c, 0x58, 0x26, 0x67, ++ 0x92, 0x4b, 0xb5, 0x90, 0xe8, 0x7b, 0x71, 0x5e, 0x61, 0x3a, 0x49, 0xff, ++ 0x38, 0x5f, 0xef, 0x09, 0x16, 0x97, 0xce, 0x70, 0x97, 0xce, 0x92, 0xca, ++ 0xda, 0xcc, 0x7e, 0x3b, 0x23, 0xbf, 0x25, 0x70, 0x2d, 0xf7, 0x13, 0x83, ++ 0xc3, 0x73, 0xa8, 0xf2, 0x0b, 0x56, 0xd3, 0x4c, 0x8b, 0x76, 0x17, 0x5b, ++ 0x1f, 0x11, 0xcc, 0x77, 0xe6, 0xc2, 0xc3, 0x77, 0x76, 0x8e, 0xeb, 0x7d, ++ 0xbb, 0xd0, 0xd8, 0xfb, 0xae, 0xaa, 0x80, 0xec, 0xf2, 0x4e, 0x36, 0xa1, ++ 0x6b, 0x65, 0xda, 0xb3, 0xf9, 0x5c, 0x6e, 0x1d, 0xe5, 0x38, 0x69, 0xe3, ++ 0xa2, 0xf5, 0xce, 0x3e, 0xe0, 0x64, 0xd3, 0xdf, 0xb2, 0x6f, 0xf9, 0xdc, ++ 0xc7, 0x3e, 0x45, 0x8e, 0xe7, 0xec, 0xf8, 0xf2, 0x92, 0x7d, 0x8e, 0x65, ++ 0xc5, 0x87, 0x5d, 0xa8, 0x33, 0x62, 0x0b, 0x9d, 0xfc, 0xfe, 0xab, 0x3c, ++ 0x2b, 0x86, 0x2b, 0x7a, 0xf0, 0x4f, 0x13, 0x69, 0x3c, 0x48, 0x6e, 0xa8, ++ 0x36, 0xf4, 0xe0, 0x84, 0xec, 0xe9, 0x27, 0x4a, 0xfa, 0x5f, 0x3e, 0x41, ++ 0xb2, 0xad, 0x09, 0x3a, 0x75, 0x4a, 0x49, 0xbf, 0x57, 0xa8, 0xdf, 0x9d, ++ 0x7e, 0x89, 0x85, 0x95, 0xe9, 0x38, 0x7d, 0xa6, 0x8b, 0x71, 0xd8, 0x18, ++ 0x97, 0xbc, 0x6a, 0x22, 0xa4, 0xef, 0x01, 0xe3, 0x75, 0x24, 0x2b, 0xf6, ++ 0x0f, 0x07, 0xba, 0x59, 0xe0, 0xfb, 0x0c, 0x67, 0xad, 0xd9, 0x8c, 0xb8, ++ 0xea, 0xb1, 0x77, 0xca, 0xc1, 0x53, 0x2b, 0xe2, 0xfa, 0x94, 0xb1, 0x24, ++ 0x98, 0x11, 0x0d, 0xfb, 0xe4, 0x9c, 0x7f, 0xad, 0x1b, 0xdd, 0x66, 0x89, ++ 0x3f, 0x67, 0xc8, 0x51, 0x67, 0x28, 0xc7, 0x3e, 0x62, 0x77, 0x17, 0x39, ++ 0x6a, 0xc8, 0x28, 0xf9, 0x92, 0x31, 0x2d, 0x6b, 0x99, 0x9f, 0xb4, 0x86, ++ 0x0f, 0xe8, 0x91, 0x32, 0x77, 0x63, 0xdf, 0x71, 0x6c, 0x67, 0x3e, 0x2b, ++ 0x3e, 0x55, 0x86, 0xc3, 0x4d, 0xd3, 0xf6, 0x5c, 0x48, 0xf4, 0x75, 0xe3, ++ 0x39, 0x39, 0x3f, 0x7a, 0x51, 0x34, 0xfc, 0x1c, 0x79, 0x76, 0x6a, 0x71, ++ 0x3e, 0xa2, 0xf9, 0x25, 0x7f, 0xfc, 0x8a, 0xd8, 0x3a, 0xde, 0x05, 0x23, ++ 0x95, 0xc7, 0x5f, 0xf2, 0x73, 0x43, 0xf8, 0xcc, 0xa2, 0xaf, 0xae, 0x9e, ++ 0xfe, 0xa9, 0x7f, 0xf1, 0x8c, 0xb7, 0xf3, 0x4e, 0x24, 0xff, 0xd7, 0xfc, ++ 0x2e, 0x7d, 0xc6, 0x99, 0x0b, 0x88, 0x3e, 0xf0, 0x6d, 0x6b, 0x29, 0x97, ++ 0x78, 0x09, 0xca, 0xef, 0x0d, 0x36, 0x8e, 0x94, 0x39, 0x67, 0x03, 0x8e, ++ 0x9b, 0x6e, 0xec, 0x3a, 0xff, 0x7b, 0x08, 0xb9, 0xb6, 0x61, 0xd3, 0x88, ++ 0xac, 0x67, 0x1c, 0xbb, 0x52, 0xc3, 0xff, 0x22, 0x37, 0x0b, 0x26, 0x9d, ++ 0xdf, 0xef, 0x22, 0xcf, 0xfe, 0x9a, 0x79, 0xe6, 0xd2, 0x1c, 0x9f, 0xd7, ++ 0xe9, 0xc4, 0x2d, 0xc4, 0x9d, 0xa1, 0xac, 0xde, 0x17, 0x73, 0xcb, 0xbe, ++ 0x43, 0x94, 0xb9, 0xfb, 0x97, 0x08, 0xd2, 0xd2, 0x5f, 0x3b, 0x3a, 0x47, ++ 0x92, 0xac, 0x8f, 0x82, 0x81, 0x3b, 0xf7, 0xcb, 0x59, 0x04, 0x0f, 0x8e, ++ 0x0e, 0x46, 0xcd, 0xd7, 0x14, 0xf0, 0xe8, 0xa0, 0x6d, 0xbf, 0x66, 0xe2, ++ 0x2f, 0xab, 0x59, 0x67, 0x37, 0x29, 0x3d, 0xc5, 0x7c, 0x21, 0x72, 0xad, ++ 0x6a, 0x0c, 0xe7, 0xa1, 0x9f, 0xd8, 0xc1, 0xfe, 0x0e, 0x15, 0x80, 0xe7, ++ 0x0a, 0x3e, 0x3c, 0x3b, 0xa2, 0xf7, 0x2e, 0x28, 0x1f, 0x66, 0x1f, 0xa9, ++ 0x0d, 0x6c, 0xdf, 0x9f, 0xc4, 0x5e, 0xf2, 0x48, 0xfb, 0xa1, 0x14, 0x36, ++ 0xed, 0x57, 0x88, 0xc7, 0x52, 0x68, 0x3b, 0x54, 0x85, 0x6b, 0x47, 0x34, ++ 0xbc, 0x9f, 0xac, 0xc2, 0x75, 0x8f, 0x2c, 0xe9, 0xf1, 0xc6, 0x62, 0xad, ++ 0x28, 0x78, 0x44, 0x6c, 0x24, 0xce, 0x6a, 0xc4, 0xbe, 0x07, 0x72, 0x92, ++ 0x4b, 0xd8, 0x76, 0xb8, 0xa5, 0xb4, 0x56, 0xf2, 0x44, 0x11, 0xbe, 0x83, ++ 0x2d, 0x46, 0x38, 0xec, 0x4a, 0xe3, 0xd2, 0xb1, 0xb9, 0x6f, 0x55, 0xc3, ++ 0x7e, 0x5e, 0xf6, 0x75, 0xce, 0x36, 0xd9, 0xf6, 0xa6, 0x64, 0x6c, 0xe1, ++ 0x76, 0x27, 0x07, 0xff, 0x35, 0x63, 0xca, 0x94, 0xb3, 0x6e, 0xd4, 0xf7, ++ 0x3d, 0xea, 0x6b, 0x74, 0x9e, 0x76, 0x5b, 0xfd, 0x41, 0xd8, 0x1f, 0x55, ++ 0xa4, 0xed, 0xb3, 0x65, 0xe9, 0x58, 0xf8, 0x2e, 0x25, 0x35, 0x43, 0x04, ++ 0x9b, 0x12, 0xb6, 0xfd, 0x66, 0xd2, 0xb6, 0x0b, 0x49, 0xcb, 0xbb, 0x7a, ++ 0x6d, 0x10, 0x87, 0x56, 0xc9, 0x6f, 0x10, 0xa2, 0x99, 0x3a, 0xfa, 0x97, ++ 0x6f, 0x95, 0x11, 0xde, 0x02, 0xd9, 0x0f, 0xe0, 0x1c, 0x2f, 0xd7, 0x3b, ++ 0x81, 0xfa, 0xc0, 0xbe, 0xc1, 0x5a, 0x3c, 0x3a, 0xf3, 0x27, 0x00, 0xc3, ++ 0x50, 0xd6, 0xe4, 0x3e, 0x32, 0xb1, 0xae, 0x9a, 0xf9, 0xc6, 0xad, 0x90, ++ 0x75, 0xda, 0x10, 0x8e, 0x14, 0x2d, 0x5c, 0x97, 0xec, 0xc1, 0xb6, 0x11, ++ 0xc9, 0xb7, 0x3f, 0x6e, 0xfd, 0x68, 0xc4, 0xfe, 0x95, 0x97, 0xf2, 0xaf, ++ 0x6b, 0x69, 0xec, 0xf2, 0x39, 0xbf, 0x61, 0x7a, 0xab, 0x75, 0xfd, 0x78, ++ 0x0d, 0x8a, 0x53, 0xc6, 0xdc, 0x4a, 0x95, 0x79, 0x8d, 0xb9, 0x4a, 0xb8, ++ 0xce, 0x1d, 0xc4, 0x0c, 0x63, 0x77, 0xaa, 0x28, 0x75, 0xcd, 0xbf, 0xb4, ++ 0xda, 0x63, 0x2b, 0x30, 0x39, 0xc3, 0xbe, 0x72, 0x46, 0xdb, 0x07, 0xcc, ++ 0xfd, 0x2a, 0xd3, 0x76, 0xb5, 0x2f, 0x1d, 0x3b, 0xd1, 0xa8, 0xdc, 0x58, ++ 0x58, 0x63, 0xdb, 0xed, 0x2d, 0x46, 0x5f, 0x95, 0x42, 0xaf, 0x2b, 0x6d, ++ 0xa4, 0x9a, 0xdc, 0xf8, 0x72, 0x18, 0xb1, 0xb6, 0x37, 0x11, 0xeb, 0x3c, ++ 0xa9, 0x42, 0x78, 0xac, 0x28, 0x67, 0x49, 0xef, 0xc7, 0xaf, 0x46, 0x96, ++ 0xe3, 0xf9, 0xa9, 0xef, 0x2c, 0xae, 0xab, 0xc1, 0x77, 0xd9, 0xda, 0x34, ++ 0x0e, 0x8f, 0x44, 0xe8, 0x3f, 0xe5, 0xc4, 0x75, 0x0d, 0xae, 0x06, 0xa9, ++ 0xaf, 0xe6, 0x59, 0x5f, 0xd9, 0xf6, 0xea, 0x86, 0xa5, 0xba, 0xe8, 0xc2, ++ 0xdf, 0x2e, 0x2c, 0xad, 0x19, 0x35, 0x71, 0xfe, 0x1a, 0xbb, 0xb6, 0xa9, ++ 0xe3, 0xb6, 0xf5, 0x0d, 0x39, 0xbf, 0xf8, 0x8d, 0x2a, 0xf8, 0x44, 0xef, ++ 0x7a, 0xec, 0x18, 0x93, 0xbd, 0x7b, 0x99, 0x37, 0xf8, 0xda, 0x92, 0x72, ++ 0xa6, 0x40, 0xe6, 0x68, 0xce, 0xb7, 0x31, 0x49, 0x4c, 0x54, 0x01, 0xe6, ++ 0x53, 0x96, 0x77, 0x03, 0xf9, 0xa9, 0x62, 0x44, 0x7e, 0x47, 0x11, 0x61, ++ 0x3d, 0xba, 0x0e, 0x67, 0xcc, 0x4a, 0xec, 0xab, 0x11, 0xdf, 0x11, 0x39, ++ 0x65, 0xdd, 0x71, 0x3b, 0x6e, 0x93, 0xdf, 0xa2, 0x14, 0xbf, 0xea, 0x9c, ++ 0xa9, 0x3b, 0xea, 0xe4, 0x07, 0x22, 0xc7, 0xd2, 0xf8, 0x6d, 0x58, 0xe9, ++ 0x9c, 0x47, 0xfa, 0xc7, 0xd6, 0x30, 0xf3, 0xf4, 0x83, 0xf4, 0x0b, 0x57, ++ 0x7a, 0x03, 0x34, 0xfa, 0xe2, 0xd5, 0xc9, 0x0b, 0xfb, 0x30, 0x7a, 0x4f, ++ 0xba, 0xe5, 0x7c, 0xb3, 0xec, 0x71, 0xea, 0xa9, 0x23, 0xea, 0xc2, 0x3e, ++ 0x1f, 0xad, 0x92, 0xfd, 0x5b, 0x6b, 0xaa, 0xc4, 0x4b, 0x87, 0xc9, 0x4b, ++ 0x2f, 0x0f, 0x4b, 0x8c, 0x7c, 0xe2, 0xc4, 0x88, 0x8b, 0x58, 0xbb, 0x9e, ++ 0xdc, 0x7e, 0xd2, 0x84, 0x51, 0x8e, 0x04, 0xe5, 0x8e, 0xb5, 0x71, 0x04, ++ 0x4b, 0x23, 0x4e, 0x97, 0x11, 0xff, 0xa7, 0x86, 0xe5, 0x9c, 0x92, 0x70, ++ 0x80, 0xde, 0x21, 0x57, 0x39, 0x23, 0x11, 0x4e, 0xf7, 0x32, 0xf7, 0x04, ++ 0x4e, 0x0d, 0xca, 0x9a, 0x97, 0xec, 0xfd, 0xf5, 0xa9, 0x73, 0xce, 0x19, ++ 0xd8, 0x5e, 0xbc, 0x9d, 0x94, 0xdf, 0x61, 0x49, 0xec, 0xdd, 0x0b, 0x89, ++ 0xbd, 0x6a, 0xb6, 0xfd, 0x68, 0x30, 0x1a, 0x69, 0x63, 0xdc, 0x74, 0x43, ++ 0x9f, 0x03, 0x1a, 0xcd, 0x69, 0x48, 0x8c, 0xe8, 0x99, 0x97, 0x16, 0xf7, ++ 0xfc, 0x62, 0x8b, 0xfb, 0x95, 0xf1, 0x7c, 0x9b, 0x3a, 0x93, 0x17, 0x99, ++ 0x7e, 0x4d, 0x99, 0x36, 0xa8, 0xf7, 0xa6, 0x37, 0xaa, 0xf7, 0xa7, 0xdb, ++ 0xd5, 0x9b, 0x79, 0xc1, 0xe4, 0x8f, 0x5b, 0x77, 0x0e, 0x0b, 0x9f, 0xdd, ++ 0xa0, 0xde, 0x9a, 0xd8, 0xac, 0x4e, 0xe7, 0x3b, 0xd5, 0x07, 0xd3, 0x16, ++ 0xee, 0x48, 0xb6, 0x23, 0x3f, 0x82, 0xa0, 0x37, 0x7d, 0x87, 0x3a, 0x33, ++ 0x51, 0x5a, 0x6b, 0x3c, 0x9d, 0xaf, 0x0f, 0xe4, 0x39, 0x76, 0x25, 0xed, ++ 0x76, 0xfb, 0xe0, 0x8a, 0xc0, 0xa3, 0xe3, 0xa1, 0xc0, 0xec, 0xb8, 0xde, ++ 0x23, 0xe7, 0x58, 0xaf, 0x4b, 0xfc, 0x5c, 0xe6, 0xd0, 0xfe, 0x49, 0xa2, ++ 0x94, 0x1f, 0xec, 0xa0, 0x3d, 0xb6, 0x92, 0x5b, 0x26, 0xcd, 0xcb, 0x91, ++ 0x71, 0xb0, 0x45, 0x7c, 0x5d, 0x74, 0x15, 0xae, 0x96, 0xfd, 0xb2, 0x5e, ++ 0x78, 0x5a, 0xc0, 0x7c, 0xee, 0x33, 0x5d, 0xcf, 0x50, 0x57, 0xab, 0x8c, ++ 0x7a, 0x51, 0xd7, 0x0f, 0x07, 0x65, 0x2d, 0xfa, 0x5e, 0x64, 0x07, 0x45, ++ 0xc6, 0x5e, 0xec, 0xcc, 0x46, 0x7b, 0x4e, 0x90, 0xb3, 0x07, 0x4b, 0xbf, ++ 0x77, 0x08, 0x0f, 0x50, 0xdf, 0x02, 0x04, 0x73, 0x7e, 0x5f, 0xd7, 0x2b, ++ 0xa9, 0xeb, 0xfb, 0x79, 0x99, 0xdb, 0x5f, 0x73, 0x6e, 0x47, 0xec, 0x6a, ++ 0x23, 0x43, 0x1e, 0x94, 0x7d, 0xbc, 0x0d, 0xea, 0x34, 0xf5, 0x7a, 0xac, ++ 0x65, 0x23, 0xf5, 0x6f, 0x57, 0x0b, 0xf9, 0x1b, 0xd4, 0x47, 0xd4, 0xf7, ++ 0xc3, 0xbc, 0xec, 0x6f, 0x7a, 0xd5, 0xc9, 0xe1, 0x76, 0x74, 0x8f, 0x78, ++ 0xd5, 0x7b, 0xc3, 0x25, 0x9d, 0xdf, 0x3b, 0xaf, 0x73, 0x38, 0xb0, 0x2f, ++ 0x5b, 0x1b, 0x78, 0x60, 0x3c, 0x18, 0xd8, 0x3d, 0x6e, 0xdb, 0xef, 0x99, ++ 0x55, 0x01, 0xd1, 0xf3, 0xc7, 0xe6, 0xe7, 0xf5, 0xbc, 0x92, 0x7a, 0xca, ++ 0x1e, 0xf5, 0xef, 0xcf, 0xe9, 0x92, 0x9e, 0x0f, 0x66, 0x9d, 0xb3, 0x56, ++ 0xce, 0x39, 0xb2, 0x2a, 0xd9, 0xa7, 0xa6, 0x9e, 0x01, 0xde, 0x7f, 0x79, ++ 0xf0, 0xb3, 0xbd, 0xdc, 0x25, 0x3d, 0x4f, 0x73, 0x3e, 0x0b, 0xa5, 0xbd, ++ 0x5c, 0xb3, 0xca, 0x2d, 0xb5, 0x88, 0xde, 0xd7, 0xe0, 0x2e, 0xe9, 0x99, ++ 0x5a, 0xd4, 0xf3, 0xf2, 0x3c, 0x6b, 0x61, 0xe2, 0x41, 0x80, 0xfc, 0xf6, ++ 0xb3, 0x11, 0x9b, 0xf3, 0xe7, 0x76, 0x7e, 0x33, 0x56, 0xc8, 0xf5, 0xe3, ++ 0xe5, 0x84, 0xfc, 0x8e, 0x2e, 0x16, 0x39, 0x42, 0x7c, 0x9d, 0x2e, 0xfa, ++ 0x54, 0xb9, 0xb3, 0x57, 0x8d, 0x9f, 0x55, 0x50, 0xa6, 0xc3, 0x53, 0xf2, ++ 0x3b, 0x31, 0x98, 0xcc, 0x0d, 0x82, 0xf2, 0xfb, 0xba, 0x49, 0xe7, 0x3c, ++ 0x6c, 0xbb, 0xaa, 0x2e, 0xc8, 0xde, 0xf4, 0x66, 0x15, 0x28, 0x74, 0x2a, ++ 0x1c, 0x6a, 0x53, 0xfe, 0xc2, 0x06, 0xe5, 0x3b, 0x64, 0xd9, 0x3e, 0x63, ++ 0xa3, 0xaa, 0x3c, 0x74, 0x83, 0xf2, 0x2d, 0xee, 0x53, 0x7b, 0x0b, 0xe1, ++ 0x40, 0xf6, 0x02, 0x7b, 0xbc, 0x6f, 0x5e, 0xeb, 0xd8, 0xe3, 0x27, 0xe6, ++ 0xd2, 0x6f, 0x6a, 0x9c, 0x73, 0xbf, 0x8c, 0x59, 0xb2, 0x36, 0xeb, 0xab, ++ 0xea, 0x03, 0xa5, 0xfa, 0xea, 0xad, 0x84, 0x9c, 0x8d, 0xb2, 0xec, 0x2a, ++ 0x03, 0x11, 0x4f, 0x5a, 0xef, 0x3c, 0xa6, 0x8c, 0xae, 0x3b, 0x54, 0x66, ++ 0x93, 0x1f, 0xfd, 0xac, 0xe5, 0x62, 0x99, 0x4b, 0x55, 0x2c, 0xe5, 0x71, ++ 0x72, 0x5f, 0x53, 0xab, 0x98, 0xb5, 0xb0, 0x9b, 0x78, 0xf7, 0xe2, 0xb0, ++ 0x8b, 0xb9, 0x84, 0xec, 0xfb, 0x79, 0x70, 0x75, 0x30, 0x82, 0x87, 0x99, ++ 0xdb, 0x1f, 0xcc, 0xf5, 0xe0, 0xe1, 0x7c, 0x37, 0x0e, 0xe6, 0xff, 0x8f, ++ 0xdf, 0xda, 0x68, 0xbe, 0x74, 0x30, 0x55, 0x3a, 0xa7, 0xb1, 0x90, 0xba, ++ 0x24, 0x26, 0x98, 0xbd, 0xa7, 0x49, 0x8b, 0x49, 0x3d, 0xac, 0xfd, 0xc9, ++ 0xbb, 0x86, 0xc4, 0x66, 0xfb, 0xda, 0x97, 0x9c, 0xdc, 0x64, 0x7a, 0xcd, ++ 0x21, 0xe7, 0x5c, 0xd9, 0xd3, 0x97, 0xef, 0x74, 0x7e, 0xfb, 0x89, 0x2b, ++ 0x6e, 0x36, 0x24, 0x3e, 0x7e, 0x90, 0x5c, 0xef, 0xf0, 0xed, 0xe3, 0xad, ++ 0xa5, 0xdf, 0x59, 0xe6, 0x5b, 0x2f, 0x71, 0xae, 0x47, 0x5a, 0xe3, 0xce, ++ 0xf5, 0xe9, 0xd6, 0xd2, 0x19, 0x80, 0xe3, 0xb2, 0x9e, 0xc5, 0xeb, 0x7f, ++ 0x6a, 0x2d, 0xf9, 0xdd, 0xb3, 0xcc, 0x45, 0xe5, 0x7a, 0x62, 0x91, 0xa7, ++ 0xe7, 0x98, 0x5f, 0x7c, 0xf6, 0xfb, 0x1a, 0xe0, 0x7f, 0x03, 0xd7, 0xef, ++ 0x57, 0x76, 0x24, 0x3b, 0x00, 0x00, 0x00 }; + + static const u32 bnx2_TXP_b09FwData[(0x0/4) + 1] = { 0x0 }; + static const u32 bnx2_TXP_b09FwRodata[(0x30/4) + 1] = { +@@ -4582,15 +4699,15 @@ + 0x00000000 }; + + static struct fw_info bnx2_txp_fw_09 = { +- /* Firmware version: 4.4.23 */ +- .ver_major = 0x4, +- .ver_minor = 0x4, +- .ver_fix = 0x17, +- +- .start_addr = 0x08000094, ++ /* Firmware version: 5.0.0j */ ++ .ver_major = 0x5, ++ .ver_minor = 0x0, ++ .ver_fix = 0x0, ++ ++ .start_addr = 0x080000a8, + + .text_addr = 0x08000000, +- .text_len = 0x3b1c, ++ .text_len = 0x3b20, + .text_index = 0x0, + .gz_text = bnx2_TXP_b09FwText, + .gz_text_len = sizeof(bnx2_TXP_b09FwText), +@@ -4601,14 +4718,14 @@ + .data = bnx2_TXP_b09FwData, + + .sbss_addr = 0x08003b80, +- .sbss_len = 0x6c, +- .sbss_index = 0x0, +- +- .bss_addr = 0x08003bec, ++ .sbss_len = 0x68, ++ .sbss_index = 0x0, ++ ++ .bss_addr = 0x08003be8, + .bss_len = 0x24c, + .bss_index = 0x0, + +- .rodata_addr = 0x08003b1c, ++ .rodata_addr = 0x08003b20, + .rodata_len = 0x30, + .rodata_index = 0x0, + .rodata = bnx2_TXP_b09FwRodata, +diff -r 5f108bc568be drivers/net/cnic.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cnic.c Tue Sep 01 13:50:09 2009 +0100 +@@ -0,0 +1,4740 @@ ++/* cnic.c: Broadcom CNIC core network driver. ++ * ++ * Copyright (c) 2006-2009 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ * ++ * Written by: John(Zongxi) Chen (zongxi@broadcom.com) ++ * Modified and maintained by: Michael Chan ++ */ ++ ++#include ++#if (LINUX_VERSION_CODE < 0x020612) ++#include ++#endif ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) ++#define BCM_VLAN 1 ++#endif ++#include ++#include ++#ifndef __VMKLNX__ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef HAVE_NETEVENT ++#include ++#endif ++#include ++#endif ++ ++#ifndef __VMKLNX__ ++#define NEW_BNX2X_HSI 1 ++#endif ++#include "cnic_drv.h" ++#include "bnx2.h" ++#include "../../bnx2x/src/bnx2x_reg.h" ++#include "../../bnx2x/src/bnx2x_fw_defs.h" ++#include "../../bnx2x/src/bnx2x_hsi.h" ++#include "cnic_if.h" ++#include "cnic.h" ++#include "cnic_defs.h" ++#include "5710_hsi_cnic.h" ++#include "57xx_iscsi_constants.h" ++ ++#define DRV_MODULE_NAME "cnic" ++#define PFX DRV_MODULE_NAME ": " ++ ++static char version[] __devinitdata = ++ "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n"; ++ ++MODULE_AUTHOR("John(Zongxi) Chen "); ++MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(CNIC_MODULE_VERSION); ++ ++static LIST_HEAD(cnic_dev_list); ++static DEFINE_RWLOCK(cnic_dev_lock); ++static DEFINE_MUTEX(cnic_lock); ++ ++struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE]; ++ ++static int cnic_service_bnx2(void *, void *); ++static int cnic_service_bnx2x(void *, void *); ++static int cnic_ctl(void *, struct cnic_ctl_info *); ++ ++static struct cnic_ops cnic_bnx2_ops = { ++ .cnic_owner = THIS_MODULE, ++ .cnic_handler = cnic_service_bnx2, ++ .cnic_ctl = cnic_ctl, ++}; ++ ++static struct cnic_ops cnic_bnx2x_ops = { ++ .cnic_owner = THIS_MODULE, ++ .cnic_handler = cnic_service_bnx2x, ++ .cnic_ctl = cnic_ctl, ++}; ++ ++static inline void cnic_hold(struct cnic_dev *dev) ++{ ++ atomic_inc(&dev->ref_count); ++} ++ ++static inline void cnic_put(struct cnic_dev *dev) ++{ ++ atomic_dec(&dev->ref_count); ++} ++ ++static inline void csk_hold(struct cnic_sock *csk) ++{ ++ atomic_inc(&csk->ref_count); ++} ++ ++static inline void csk_put(struct cnic_sock *csk) ++{ ++ atomic_dec(&csk->ref_count); ++} ++ ++static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ struct drv_ctl_info info; ++ struct drv_ctl_io *io = &info.data.io; ++ ++ info.cmd = DRV_CTL_CTX_WR_CMD; ++ io->cid_addr = cid_addr; ++ io->offset = off; ++ io->data = val; ++ ethdev->drv_ctl(dev->netdev, &info); ++} ++ ++static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ struct drv_ctl_info info; ++ struct drv_ctl_io *io = &info.data.io; ++ ++ info.cmd = DRV_CTL_CTXTBL_WR_CMD; ++ io->offset = off; ++ io->dma_addr = addr; ++ ethdev->drv_ctl(dev->netdev, &info); ++} ++ ++static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ struct drv_ctl_info info; ++ struct drv_ctl_io *io = &info.data.io; ++ ++ info.cmd = DRV_CTL_IO_WR_CMD; ++ io->offset = off; ++ io->data = val; ++ ethdev->drv_ctl(dev->netdev, &info); ++} ++ ++static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ struct drv_ctl_info info; ++ struct drv_ctl_io *io = &info.data.io; ++ ++ info.cmd = DRV_CTL_IO_RD_CMD; ++ io->offset = off; ++ ethdev->drv_ctl(dev->netdev, &info); ++ return io->data; ++} ++ ++static void cnic_kwq_completion(struct cnic_dev *dev, u32 count) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ struct drv_ctl_info info; ++ ++ info.cmd = DRV_CTL_COMPLETION_CMD; ++ info.data.comp.comp_count = count; ++ ethdev->drv_ctl(dev->netdev, &info); ++} ++ ++static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid) ++{ ++ u32 i; ++ ++ for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) { ++ if (cp->ctx_tbl[i].cid == cid) { ++ *l5_cid = i; ++ return 0; ++ } ++ } ++ return -EINVAL; ++} ++ ++ ++static int cnic_in_use(struct cnic_sock *csk) ++{ ++ return (test_bit(SK_F_INUSE, &csk->flags)); ++} ++ ++static int cnic_offld_prep(struct cnic_sock *csk) ++{ ++ if (!test_bit(SK_F_CONNECT_START, &csk->flags)) ++ return 0; ++ ++ if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags)) ++ return 0; ++ ++ return 1; ++} ++ ++static int cnic_close_prep(struct cnic_sock *csk) ++{ ++ if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) ++ return 1; ++ ++ return 0; ++} ++ ++static int cnic_abort_prep(struct cnic_sock *csk) ++{ ++ while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags)) ++ msleep(1); ++ ++ if (cnic_close_prep(csk)) { ++ csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP; ++ return 1; ++ } ++ ++ return 0; ++} ++ ++int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops) ++{ ++ struct cnic_dev *dev; ++ ++ if (ulp_type >= MAX_CNIC_ULP_TYPE) { ++ printk(KERN_ERR PFX "cnic_register_driver: Bad type %d\n", ++ ulp_type); ++ return -EINVAL; ++ } ++ mutex_lock(&cnic_lock); ++ if (cnic_ulp_tbl[ulp_type]) { ++ printk(KERN_ERR PFX "cnic_register_driver: Type %d has already " ++ "been registered\n", ulp_type); ++ mutex_unlock(&cnic_lock); ++ return -EBUSY; ++ } ++ ++#ifndef __VMKLNX__ ++ read_lock(&cnic_dev_lock); ++#endif ++ list_for_each_entry(dev, &cnic_dev_list, list) { ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]); ++ } ++#ifndef __VMKLNX__ ++ read_unlock(&cnic_dev_lock); ++#endif ++ ++ rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops); ++ mutex_unlock(&cnic_lock); ++ ++ /* Prevent race conditions with netdev_event */ ++#ifndef __VMKLNX__ ++ rtnl_lock(); ++ read_lock(&cnic_dev_lock); ++#endif ++ list_for_each_entry(dev, &cnic_dev_list, list) { ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type])) ++ ulp_ops->cnic_init(dev); ++ } ++#ifndef __VMKLNX__ ++ read_unlock(&cnic_dev_lock); ++ rtnl_unlock(); ++#endif ++ ++ return 0; ++} ++ ++int cnic_unregister_driver(int ulp_type) ++{ ++ struct cnic_dev *dev; ++ ++ if (ulp_type >= MAX_CNIC_ULP_TYPE) { ++ printk(KERN_ERR PFX "cnic_unregister_driver: Bad type %d\n", ++ ulp_type); ++ return -EINVAL; ++ } ++ mutex_lock(&cnic_lock); ++ if (!cnic_ulp_tbl[ulp_type]) { ++ printk(KERN_ERR PFX "cnic_unregister_driver: Type %d has not " ++ "been registered\n", ulp_type); ++ goto out_unlock; ++ } ++#ifndef __VMKLNX__ ++ read_lock(&cnic_dev_lock); ++#endif ++ list_for_each_entry(dev, &cnic_dev_list, list) { ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ if (rcu_dereference(cp->ulp_ops[ulp_type])) { ++ printk(KERN_ERR PFX "cnic_unregister_driver: Type %d " ++ "still has devices registered\n", ulp_type); ++#ifndef __VMKLNX__ ++ read_unlock(&cnic_dev_lock); ++#endif ++ goto out_unlock; ++ } ++ } ++#ifndef __VMKLNX__ ++ read_unlock(&cnic_dev_lock); ++#endif ++ ++ rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL); ++ ++ mutex_unlock(&cnic_lock); ++#ifndef __VMKLNX__ ++ synchronize_rcu(); ++#endif ++ return 0; ++ ++out_unlock: ++ mutex_unlock(&cnic_lock); ++ return -EINVAL; ++} ++ ++EXPORT_SYMBOL(cnic_register_driver); ++EXPORT_SYMBOL(cnic_unregister_driver); ++ ++static int cnic_start_hw(struct cnic_dev *); ++static void cnic_stop_hw(struct cnic_dev *); ++ ++static int cnic_register_device(struct cnic_dev *dev, int ulp_type, ++ void *ulp_ctx) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_ulp_ops *ulp_ops; ++ ++ if (ulp_type >= MAX_CNIC_ULP_TYPE) { ++ printk(KERN_ERR PFX "cnic_register_device: Bad type %d\n", ++ ulp_type); ++ return -EINVAL; ++ } ++ mutex_lock(&cnic_lock); ++ if (cnic_ulp_tbl[ulp_type] == NULL) { ++ printk(KERN_ERR PFX "cnic_register_device: Driver with type %d " ++ "has not been registered\n", ulp_type); ++ mutex_unlock(&cnic_lock); ++ return -EAGAIN; ++ } ++ if (rcu_dereference(cp->ulp_ops[ulp_type])) { ++ printk(KERN_ERR PFX "cnic_register_device: Type %d has already " ++ "been registered to this device\n", ulp_type); ++ mutex_unlock(&cnic_lock); ++ return -EBUSY; ++ } ++#ifndef __VMKLNX__ ++ if (!try_module_get(cnic_ulp_tbl[ulp_type]->owner)) { ++ mutex_unlock(&cnic_lock); ++ return -EBUSY; ++ } ++#endif ++ ++ clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]); ++ cp->ulp_handle[ulp_type] = ulp_ctx; ++ ulp_ops = cnic_ulp_tbl[ulp_type]; ++ rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops); ++ cnic_hold(dev); ++ if (!dev->use_count) { ++ if (!test_bit(CNIC_F_IF_GOING_DOWN, &dev->flags)) { ++ if (dev->netdev->flags & IFF_UP) ++ set_bit(CNIC_F_IF_UP, &dev->flags); ++ } ++ } ++ dev->use_count++; ++ ++ if (dev->use_count == 1) { ++ if (test_bit(CNIC_F_IF_UP, &dev->flags)) ++ cnic_start_hw(dev); ++ } ++ ++ if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) ++ if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type])) ++ ulp_ops->cnic_start(cp->ulp_handle[ulp_type]); ++ ++ mutex_unlock(&cnic_lock); ++ ++ return 0; ++ ++} ++ ++static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ if (ulp_type >= MAX_CNIC_ULP_TYPE) { ++ printk(KERN_ERR PFX "cnic_unregister_device: Bad type %d\n", ++ ulp_type); ++ return -EINVAL; ++ } ++ mutex_lock(&cnic_lock); ++ if (rcu_dereference(cp->ulp_ops[ulp_type])) { ++ dev->use_count--; ++#ifndef __VMKLNX__ ++ module_put(cp->ulp_ops[ulp_type]->owner); ++#endif ++ rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL); ++ if (dev->use_count == 0) { ++ cnic_stop_hw(dev); ++#ifdef __VMKLNX__ ++ if (cp->first_iscsiNetHandle.ptr) { ++ vmk_IscsiNetTcpPortFree( ++ cp->first_iscsiNetHandle, ++ &cp->cnic_local_port_nr, ++ &cp->cnic_local_port_min); ++ } ++#endif ++ } ++ cnic_put(dev); ++ } else { ++ printk(KERN_ERR PFX "cnic_unregister_device: device not " ++ "registered to this ulp type %d\n", ulp_type); ++ mutex_unlock(&cnic_lock); ++ return -EINVAL; ++ } ++ mutex_unlock(&cnic_lock); ++ ++#ifndef __VMKLNX__ ++ synchronize_rcu(); ++#endif ++ ++ return 0; ++} ++ ++static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id, ++ u32 next) ++{ ++ id_tbl->start = start_id; ++ id_tbl->max = size; ++ id_tbl->next = next; ++ spin_lock_init(&id_tbl->lock); ++ id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL); ++ if (!id_tbl->table) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++static u32 cnic_free_id_tbl(struct cnic_id_tbl *id_tbl) ++{ ++ kfree(id_tbl->table); ++ id_tbl->table = NULL; ++ return id_tbl->next; ++} ++ ++/* Returns -1 if not successful */ ++static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl) ++{ ++ u32 id; ++ ++ spin_lock(&id_tbl->lock); ++ id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next); ++ if (id >= id_tbl->max) { ++ id = -1; ++ if (id_tbl->next != 0) { ++ id = find_first_zero_bit(id_tbl->table, id_tbl->next); ++ if (id >= id_tbl->next) ++ id = -1; ++ } ++ } ++ ++ if (id < id_tbl->max) { ++ set_bit(id, id_tbl->table); ++ id_tbl->next = (id + 1) & (id_tbl->max - 1); ++ id += id_tbl->start; ++ } ++ ++ spin_unlock(&id_tbl->lock); ++ ++ return id; ++} ++ ++void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id) ++{ ++ if (id == -1) ++ return; ++ ++ id -= id_tbl->start; ++ if (id >= id_tbl->max) ++ return; ++ ++ clear_bit(id, id_tbl->table); ++} ++ ++static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma) ++{ ++ int i; ++ ++ if (!dma->pg_arr) ++ return; ++ ++ for (i = 0; i < dma->num_pages; i++) { ++ if (dma->pg_arr[i]) { ++ pci_free_consistent(dev->pcidev, BCM_PAGE_SIZE, ++ dma->pg_arr[i], dma->pg_map_arr[i]); ++ dma->pg_arr[i] = NULL; ++ } ++ } ++ if (dma->pgtbl) { ++ pci_free_consistent(dev->pcidev, dma->pgtbl_size, ++ dma->pgtbl, dma->pgtbl_map); ++ dma->pgtbl = NULL; ++ } ++ kfree(dma->pg_arr); ++ dma->pg_arr = NULL; ++ dma->num_pages = 0; ++} ++ ++static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma) ++{ ++ int i; ++ u32 *page_table = dma->pgtbl; ++ ++ for (i = 0; i < dma->num_pages; i++) { ++ /* Each entry needs to be in big endian format. */ ++ *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32); ++ page_table++; ++ *page_table = (u32) dma->pg_map_arr[i]; ++ page_table++; ++ } ++} ++ ++static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma) ++{ ++ int i; ++ u32 *page_table = dma->pgtbl; ++ ++ for (i = 0; i < dma->num_pages; i++) { ++ /* Each entry needs to be in little endian format. */ ++ *page_table = dma->pg_map_arr[i] & 0xffffffff; ++ page_table++; ++ *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32); ++ page_table++; ++ } ++} ++ ++static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma, ++ int pages, int use_pg_tbl) ++{ ++ int i, size; ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ size = pages * (sizeof(void *) + sizeof(dma_addr_t)); ++ dma->pg_arr = kzalloc(size, GFP_ATOMIC); ++ if (dma->pg_arr == NULL) ++ return -ENOMEM; ++ ++ dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages); ++ dma->num_pages = pages; ++ ++ for (i = 0; i < pages; i++) { ++ dma->pg_arr[i] = pci_alloc_consistent(dev->pcidev, ++ BCM_PAGE_SIZE, ++ &dma->pg_map_arr[i]); ++ if (dma->pg_arr[i] == NULL) ++ goto error; ++ } ++ if (!use_pg_tbl) ++ return 0; ++ ++ dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) & ++ ~(BCM_PAGE_SIZE - 1); ++ dma->pgtbl = pci_alloc_consistent(dev->pcidev, dma->pgtbl_size, ++ &dma->pgtbl_map); ++ if (dma->pgtbl == NULL) ++ goto error; ++ ++ cp->setup_pgtbl(dev, dma); ++ ++ return 0; ++ ++error: ++ cnic_free_dma(dev, dma); ++ return -ENOMEM; ++} ++ ++static void cnic_free_contex(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ int i; ++ ++ for (i = 0; i < cp->ctx_blks; i++) { ++ if (cp->ctx_arr[i].ctx) { ++ pci_free_consistent(dev->pcidev, cp->ctx_blk_size, ++ cp->ctx_arr[i].ctx, ++ cp->ctx_arr[i].mapping); ++ cp->ctx_arr[i].ctx = NULL; ++ } ++ } ++} ++ ++static void cnic_free_resc(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ cnic_free_contex(dev); ++ kfree(cp->ctx_arr); ++ cp->ctx_arr = NULL; ++ cp->ctx_blks = 0; ++ ++ cnic_free_dma(dev, &cp->gbl_buf_info); ++ cnic_free_dma(dev, &cp->conn_buf_info); ++ cnic_free_dma(dev, &cp->kwq_info); ++ cnic_free_dma(dev, &cp->kwq_16_data_info); ++ cnic_free_dma(dev, &cp->kcq_info); ++ kfree(cp->iscsi_tbl); ++ cp->iscsi_tbl = NULL; ++ kfree(cp->ctx_tbl); ++ cp->ctx_tbl = NULL; ++ ++ cnic_free_id_tbl(&cp->cid_tbl); ++} ++ ++static int cnic_alloc_context(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ if (CHIP_NUM(cp) == CHIP_NUM_5709) { ++ int i, k, arr_size; ++ ++ cp->ctx_blk_size = BCM_PAGE_SIZE; ++ cp->cids_per_blk = BCM_PAGE_SIZE / 128; ++ arr_size = BNX2_MAX_CID / cp->cids_per_blk * ++ sizeof(struct cnic_ctx); ++ cp->ctx_arr = kmalloc(arr_size, GFP_KERNEL); ++ if (cp->ctx_arr == NULL) ++ return -ENOMEM; ++ ++ memset(cp->ctx_arr, 0, arr_size); ++ ++ k = 0; ++ for (i = 0; i < 2; i++) { ++ u32 j, reg, off, lo, hi; ++ ++ if (i == 0) ++ off = BNX2_PG_CTX_MAP; ++ else ++ off = BNX2_ISCSI_CTX_MAP; ++ ++ reg = cnic_reg_rd_ind(dev, off); ++ lo = reg >> 16; ++ hi = reg & 0xffff; ++ for (j = lo; j < hi; j += cp->cids_per_blk, k++) ++ cp->ctx_arr[k].cid = j; ++ } ++ ++ cp->ctx_blks = k; ++ if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) { ++ cp->ctx_blks = 0; ++ return -ENOMEM; ++ } ++ ++ for (i = 0; i < cp->ctx_blks; i++) { ++ cp->ctx_arr[i].ctx = ++ pci_alloc_consistent(dev->pcidev, BCM_PAGE_SIZE, ++ &cp->ctx_arr[i].mapping); ++ if (cp->ctx_arr[i].ctx == NULL) ++ return -ENOMEM; ++ } ++ } ++ return 0; ++} ++ ++static int cnic_alloc_bnx2_resc(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ int ret; ++ ++ ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1); ++ if (ret) ++ goto error; ++ cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr; ++ ++ ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 1); ++ if (ret) ++ goto error; ++ cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr; ++ ++ ret = cnic_alloc_context(dev); ++ if (ret) ++ goto error; ++ ++ return 0; ++ ++error: ++ cnic_free_resc(dev); ++ return ret; ++} ++ ++static int cnic_alloc_bnx2x_context(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ int ctx_blk_size = cp->ethdev->ctx_blk_size; ++ int total_mem, blks, i; ++ ++ total_mem = BNX2X_ISCSI_CONTEXT_MEM_SIZE * MAX_ISCSI_TBL_SZ; ++ blks = total_mem / ctx_blk_size; ++ if (total_mem % ctx_blk_size) ++ blks++; ++ ++ if (blks > cp->ethdev->ctx_tbl_len) ++ return -ENOMEM; ++ ++ cp->ctx_arr = kzalloc(blks * sizeof(struct cnic_ctx), GFP_KERNEL); ++ if (cp->ctx_arr == NULL) ++ return -ENOMEM; ++ ++ cp->ctx_blks = blks; ++ cp->ctx_blk_size = ctx_blk_size; ++ if (BNX2X_CHIP_IS_E1H(cp->chip_id)) ++ cp->ctx_align = 0; ++ else ++ cp->ctx_align = ctx_blk_size; ++ ++ cp->cids_per_blk = ctx_blk_size / BNX2X_ISCSI_CONTEXT_MEM_SIZE; ++ ++ for (i = 0; i < blks; i++) { ++ cp->ctx_arr[i].ctx = ++ pci_alloc_consistent(dev->pcidev, cp->ctx_blk_size, ++ &cp->ctx_arr[i].mapping); ++ if (cp->ctx_arr[i].ctx == NULL) ++ return -ENOMEM; ++ ++ if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) { ++ if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) { ++ cnic_free_contex(dev); ++ cp->ctx_blk_size += cp->ctx_align; ++ i = -1; ++ continue; ++ } ++ } ++ } ++ return 0; ++} ++ ++static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ int i, j, n, ret, pages; ++ struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info; ++ ++ cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ, ++ GFP_KERNEL); ++ if (!cp->iscsi_tbl) ++ goto error; ++ ++ cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) * ++ MAX_CNIC_L5_CONTEXT, GFP_KERNEL); ++ if (!cp->ctx_tbl) ++ goto error; ++ ++ for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) { ++ cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i]; ++ cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI; ++ } ++ ++ pages = PAGE_ALIGN(MAX_CNIC_L5_CONTEXT * CNIC_KWQ16_DATA_SIZE) / ++ PAGE_SIZE; ++ ++ ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0); ++ if (ret) ++ return -ENOMEM; ++ ++ n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE; ++ for (i = 0, j = 0; i < MAX_ISCSI_TBL_SZ; i++) { ++ long off = CNIC_KWQ16_DATA_SIZE * (i % n); ++ ++ cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off; ++ cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] + ++ off; ++ ++ if ((i % n) == (n - 1)) ++ j++; ++ } ++ ++ ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 0); ++ if (ret) ++ goto error; ++ cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr; ++ ++ for (i = 0; i < KCQ_PAGE_CNT; i++) { ++ struct bnx2x_bd_chain_next *next = ++ (struct bnx2x_bd_chain_next *) ++ &cp->kcq[i][MAX_KCQE_CNT]; ++ int j = i + 1; ++ ++ if (j >= KCQ_PAGE_CNT) ++ j = 0; ++ next->addr_hi = (u64) cp->kcq_info.pg_map_arr[j] >> 32; ++ next->addr_lo = cp->kcq_info.pg_map_arr[j] & 0xffffffff; ++ } ++ ++ pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS * ++ BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE; ++ ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1); ++ if (ret) ++ goto error; ++ ++ pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE; ++ ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0); ++ if (ret) ++ goto error; ++ ++ ret = cnic_alloc_bnx2x_context(dev); ++ if (ret) ++ goto error; ++ ++ return 0; ++ ++error: ++ cnic_free_resc(dev); ++ return -ENOMEM; ++} ++ ++static inline u32 cnic_kwq_avail(struct cnic_local *cp) ++{ ++ return (cp->max_kwq_idx - ++ ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx)); ++} ++ ++static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[], ++ u32 num_wqes) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct kwqe *prod_qe; ++ u16 prod, sw_prod, i; ++ ++ if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) ++ return -EAGAIN; /* bnx2 is down */ ++ ++ spin_lock_bh(&cp->cnic_ulp_lock); ++ if (num_wqes > cnic_kwq_avail(cp) && ++ !(cp->cnic_local_flags & CNIC_LCL_FL_KWQ_INIT)) { ++ spin_unlock_bh(&cp->cnic_ulp_lock); ++ return -EAGAIN; ++ } ++ ++ cp->cnic_local_flags &= ~CNIC_LCL_FL_KWQ_INIT; ++ ++ prod = cp->kwq_prod_idx; ++ sw_prod = prod & MAX_KWQ_IDX; ++ for (i = 0; i < num_wqes; i++) { ++ prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)]; ++ memcpy(prod_qe, wqes[i], sizeof(struct kwqe)); ++ prod++; ++ sw_prod = prod & MAX_KWQ_IDX; ++ } ++ cp->kwq_prod_idx = prod; ++ ++ CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx); ++ ++ spin_unlock_bh(&cp->cnic_ulp_lock); ++ return 0; ++} ++ ++static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid, ++ union l5cm_specific_data *l5_data) ++{ ++ struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; ++ dma_addr_t map; ++ ++ map = ctx->kwqe_data_mapping; ++ l5_data->phy_address.lo = (u64) map & 0xffffffff; ++ l5_data->phy_address.hi = (u64) map >> 32; ++ return ctx->kwqe_data; ++} ++ ++static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid, ++ u32 type, union l5cm_specific_data *l5_data) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct l5cm_spe kwqe; ++ struct kwqe_16 *kwq[1]; ++ int ret; ++ ++ kwqe.hdr.conn_and_cmd_data = ++ cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) | ++ BNX2X_HW_CID(cid, cp->func))); ++ kwqe.hdr.type = cpu_to_le16(type); ++ kwqe.hdr.reserved = 0; ++ kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo); ++ kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi); ++ ++ kwq[0] = (struct kwqe_16 *) &kwqe; ++ spin_lock_bh(&cp->cnic_ulp_lock); ++ ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1); ++ spin_unlock_bh(&cp->cnic_ulp_lock); ++ ++ if (ret == 1) ++ return 0; ++ ++ return -EBUSY; ++} ++ ++static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type, ++ struct kcqe *cqes[], u32 num_cqes) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_ulp_ops *ulp_ops; ++ ++ rcu_read_lock(); ++ ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]); ++ if (likely(ulp_ops)) { ++ ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type], ++ cqes, num_cqes); ++ } ++ rcu_read_unlock(); ++} ++ ++static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe; ++ int func = cp->func, pages; ++ int hq_bds; ++ ++ cp->num_iscsi_tasks = req1->num_tasks_per_conn; ++ cp->num_ccells = req1->num_ccells_per_conn; ++ cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE * ++ cp->num_iscsi_tasks; ++ cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS * ++ BNX2X_ISCSI_R2TQE_SIZE; ++ cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE; ++ pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE; ++ hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE); ++ cp->num_cqs = req1->num_cqs; ++ ++ if (!dev->max_iscsi_conn) ++ return 0; ++ ++ /* init Tstorm RAM */ ++ CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(func), ++ req1->rq_num_wqes); ++ CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(func), ++ PAGE_SIZE); ++ CNIC_WR8(dev, BAR_TSTRORM_INTMEM + ++ TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT); ++ CNIC_WR16(dev, BAR_TSTRORM_INTMEM + ++ TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func), ++ req1->num_tasks_per_conn); ++ ++ /* init Ustorm RAM */ ++ CNIC_WR16(dev, BAR_USTRORM_INTMEM + ++ USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(func), ++ req1->rq_buffer_size); ++ CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(func), ++ PAGE_SIZE); ++ CNIC_WR8(dev, BAR_USTRORM_INTMEM + ++ USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT); ++ CNIC_WR16(dev, BAR_USTRORM_INTMEM + ++ USTORM_ISCSI_NUM_OF_TASKS_OFFSET(func), ++ req1->num_tasks_per_conn); ++ CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(func), ++ req1->rq_num_wqes); ++ CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(func), ++ req1->cq_num_wqes); ++ CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(func), ++ cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS); ++ ++ /* init Xstorm RAM */ ++ CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(func), ++ PAGE_SIZE); ++ CNIC_WR8(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT); ++ CNIC_WR16(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func), ++ req1->num_tasks_per_conn); ++ CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(func), ++ hq_bds); ++ CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(func), ++ req1->num_tasks_per_conn); ++ CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(func), ++ cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS); ++ ++ /* init Cstorm RAM */ ++ CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(func), ++ PAGE_SIZE); ++ CNIC_WR8(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT); ++ CNIC_WR16(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func), ++ req1->num_tasks_per_conn); ++ CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(func), ++ req1->cq_num_wqes); ++ CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(func), ++ hq_bds); ++ ++ return 0; ++} ++ ++static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe) ++{ ++ struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe; ++ struct cnic_local *cp = dev->cnic_priv; ++ int func = cp->func; ++ struct iscsi_kcqe kcqe; ++ struct kcqe *cqes[1]; ++ ++ memset(&kcqe, 0, sizeof(kcqe)); ++ if (!dev->max_iscsi_conn) { ++ kcqe.completion_status = ++ ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED; ++ goto done; ++ } ++ ++ CNIC_WR(dev, BAR_TSTRORM_INTMEM + ++ TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]); ++ CNIC_WR(dev, BAR_TSTRORM_INTMEM + ++ TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4, ++ req2->error_bit_map[1]); ++ ++ CNIC_WR16(dev, BAR_USTRORM_INTMEM + ++ USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn); ++ CNIC_WR(dev, BAR_USTRORM_INTMEM + ++ USTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]); ++ CNIC_WR(dev, BAR_USTRORM_INTMEM + ++ USTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4, ++ req2->error_bit_map[1]); ++ ++ CNIC_WR16(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn); ++ ++ kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS; ++ ++done: ++ kcqe.op_code = ISCSI_KCQE_OPCODE_INIT; ++ cqes[0] = (struct kcqe *) &kcqe; ++ cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1); ++ ++ return 0; ++} ++ ++static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; ++ ++ if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) { ++ struct cnic_iscsi *iscsi = ctx->proto.iscsi; ++ ++ cnic_free_dma(dev, &iscsi->hq_info); ++ cnic_free_dma(dev, &iscsi->r2tq_info); ++ cnic_free_dma(dev, &iscsi->task_array_info); ++ } ++ cnic_free_id(&cp->cid_tbl, ctx->cid); ++ ctx->cid = 0; ++} ++ ++static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid) ++{ ++ u32 cid; ++ int ret, pages; ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; ++ struct cnic_iscsi *iscsi = ctx->proto.iscsi; ++ ++ cid = cnic_alloc_new_id(&cp->cid_tbl); ++ if (cid == -1) { ++ ret = -ENOMEM; ++ goto error; ++ } ++ ++ ctx->cid = cid; ++ pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE; ++ ++ ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1); ++ if (ret) ++ goto error; ++ ++ pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE; ++ ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1); ++ if (ret) ++ goto error; ++ ++ pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE; ++ ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1); ++ if (ret) ++ goto error; ++ ++ return 0; ++ ++error: ++ cnic_free_bnx2x_conn_resc(dev, l5_cid); ++ return ret; ++} ++ ++static struct iscsi_context *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, ++ int init, ++ struct regpair *ctx_addr) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk; ++ int off = (cid - ethdev->starting_cid) % cp->cids_per_blk; ++ unsigned long align_off = 0; ++ dma_addr_t ctx_map; ++ struct iscsi_context *ctx; ++ ++ if (cp->ctx_align) { ++ unsigned long mask = cp->ctx_align - 1; ++ ++ if (cp->ctx_arr[blk].mapping & mask) ++ align_off = cp->ctx_align - ++ (cp->ctx_arr[blk].mapping & mask); ++ } ++ ctx_map = cp->ctx_arr[blk].mapping + align_off + ++ (off * BNX2X_ISCSI_CONTEXT_MEM_SIZE); ++ ctx = (struct iscsi_context *) (cp->ctx_arr[blk].ctx + align_off + ++ (off * BNX2X_ISCSI_CONTEXT_MEM_SIZE)); ++ if (init) ++ memset(ctx, 0, sizeof(*ctx)); ++ ++ ctx_addr->lo = ctx_map & 0xffffffff; ++ ctx_addr->hi = (u64) ctx_map >> 32; ++ return ctx; ++} ++ ++static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[], ++ u32 num) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct iscsi_kwqe_conn_offload1 *req1 = ++ (struct iscsi_kwqe_conn_offload1 *) wqes[0]; ++ struct iscsi_kwqe_conn_offload2 *req2 = ++ (struct iscsi_kwqe_conn_offload2 *) wqes[1]; ++ struct iscsi_kwqe_conn_offload3 *req3; ++ struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id]; ++ struct cnic_iscsi *iscsi = ctx->proto.iscsi; ++ u32 cid = ctx->cid; ++ u32 hw_cid = BNX2X_HW_CID(cid, cp->func); ++ struct iscsi_context *ictx; ++ struct regpair context_addr; ++ int i, j, n = 2, n_max; ++ ++ ctx->ctx_flags = 0; ++ if (!req2->num_additional_wqes) ++ return -EINVAL; ++ ++ n_max = req2->num_additional_wqes + 2; ++ ++ ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr); ++ if (ictx == NULL) ++ return -ENOMEM; ++ ++ req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++]; ++ ++ ictx->xstorm_ag_context.hq_prod = 1; ++ ++ ictx->xstorm_st_context.iscsi.first_burst_length = ++ ISCSI_DEF_FIRST_BURST_LEN; ++ ictx->xstorm_st_context.iscsi.max_send_pdu_length = ++ ISCSI_DEF_MAX_RECV_SEG_LEN; ++ ictx->xstorm_st_context.iscsi.sq_pbl_base.lo = ++ req1->sq_page_table_addr_lo; ++ ictx->xstorm_st_context.iscsi.sq_pbl_base.hi = ++ req1->sq_page_table_addr_hi; ++ ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi; ++ ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo; ++ ictx->xstorm_st_context.iscsi.hq_pbl_base.lo = ++ iscsi->hq_info.pgtbl_map & 0xffffffff; ++ ictx->xstorm_st_context.iscsi.hq_pbl_base.hi = ++ (u64) iscsi->hq_info.pgtbl_map >> 32; ++ ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo = ++ iscsi->hq_info.pgtbl[0]; ++ ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi = ++ iscsi->hq_info.pgtbl[1]; ++ ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo = ++ iscsi->r2tq_info.pgtbl_map & 0xffffffff; ++ ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi = ++ (u64) iscsi->r2tq_info.pgtbl_map >> 32; ++ ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo = ++ iscsi->r2tq_info.pgtbl[0]; ++ ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi = ++ iscsi->r2tq_info.pgtbl[1]; ++ ictx->xstorm_st_context.iscsi.task_pbl_base.lo = ++ iscsi->task_array_info.pgtbl_map & 0xffffffff; ++ ictx->xstorm_st_context.iscsi.task_pbl_base.hi = ++ (u64) iscsi->task_array_info.pgtbl_map >> 32; ++ ictx->xstorm_st_context.iscsi.task_pbl_cache_idx = ++ BNX2X_ISCSI_PBL_NOT_CACHED; ++/* ictx->xstorm_st_context.iscsi.max_outstanding_r2ts = ++ ISCSI_DEFAULT_MAX_OUTSTANDING_R2T;*/ ++ ictx->xstorm_st_context.iscsi.flags.flags |= ++ XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA; ++ ictx->xstorm_st_context.iscsi.flags.flags |= ++ XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T; ++ ++ ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE; ++ /* TSTORM requires the base address of RQ DB & not PTE */ ++ ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo = ++ req2->rq_page_table_addr_lo & PAGE_MASK; ++ ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi = ++ req2->rq_page_table_addr_hi; ++ ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id; ++ ictx->tstorm_st_context.tcp.cwnd = 0x5A8; ++ ictx->tstorm_st_context.tcp.flags2 |= ++ TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN; ++ ++ ictx->timers_context.flags |= ISCSI_TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG; ++ ++ ictx->ustorm_st_context.ring.rq.pbl_base.lo = ++ req2->rq_page_table_addr_lo & 0xffffffff; ++ ictx->ustorm_st_context.ring.rq.pbl_base.hi = ++ (u64) req2->rq_page_table_addr_hi >> 32; ++ ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi; ++ ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo; ++ ictx->ustorm_st_context.ring.r2tq.pbl_base.lo = ++ iscsi->r2tq_info.pgtbl_map & 0xffffffff; ++ ictx->ustorm_st_context.ring.r2tq.pbl_base.hi = ++ (u64) iscsi->r2tq_info.pgtbl_map >> 32; ++ ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo = ++ iscsi->r2tq_info.pgtbl[0]; ++ ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi = ++ iscsi->r2tq_info.pgtbl[1]; ++ ictx->ustorm_st_context.ring.cq_pbl_base.lo = ++ req1->cq_page_table_addr_lo; ++ ictx->ustorm_st_context.ring.cq_pbl_base.hi = ++ req1->cq_page_table_addr_hi; ++ ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN; ++ ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi; ++ ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo; ++ ictx->ustorm_st_context.task_pbe_cache_index = ++ BNX2X_ISCSI_PBL_NOT_CACHED; ++ ictx->ustorm_st_context.task_pdu_cache_index = ++ BNX2X_ISCSI_PDU_HEADER_NOT_CACHED; ++ ++ for (i = 1, j = 1; i < cp->num_cqs; i++, j++) { ++ if (j == 3) { ++ if (n >= n_max) ++ break; ++ req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++]; ++ j = 0; ++ } ++ ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN; ++ ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo = ++ req3->qp_first_pte[j].hi; ++ ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi = ++ req3->qp_first_pte[j].lo; ++ } ++ ++ ictx->ustorm_st_context.task_pbl_base.lo = ++ iscsi->task_array_info.pgtbl_map & 0xffffffff; ++ ictx->ustorm_st_context.task_pbl_base.hi = ++ (u64) iscsi->task_array_info.pgtbl_map >> 32; ++ ictx->ustorm_st_context.tce_phy_addr.lo = ++ iscsi->task_array_info.pgtbl[0]; ++ ictx->ustorm_st_context.tce_phy_addr.hi = ++ iscsi->task_array_info.pgtbl[1]; ++ ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id; ++ ictx->ustorm_st_context.num_cqs = cp->num_cqs; ++ ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN; ++ ictx->ustorm_st_context.negotiated_rx_and_flags |= ++ ISCSI_DEF_MAX_BURST_LEN; ++ ictx->ustorm_st_context.negotiated_rx |= ++ ISCSI_DEFAULT_MAX_OUTSTANDING_R2T << ++ USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT; ++ ++ ictx->cstorm_st_context.hq_pbl_base.lo = ++ iscsi->hq_info.pgtbl_map & 0xffffffff; ++ ictx->cstorm_st_context.hq_pbl_base.hi = ++ (u64) iscsi->hq_info.pgtbl_map >> 32; ++ ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0]; ++ ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1]; ++ ictx->cstorm_st_context.task_pbl_base.lo = ++ iscsi->task_array_info.pgtbl_map & 0xffffffff; ++ ictx->cstorm_st_context.task_pbl_base.hi = ++ (u64) iscsi->task_array_info.pgtbl_map >> 32; ++ /* CSTORM and USTORM initialization is different, CSTORM requires ++ * CQ DB base & not PTE addr */ ++ ictx->cstorm_st_context.cq_db_base.lo = ++ req1->cq_page_table_addr_lo & PAGE_MASK; ++ ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi; ++ ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id; ++ ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1; ++ for (i = 0; i < cp->num_cqs; i++) { ++ ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] = ++ ISCSI_INITIAL_SN; ++ ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] = ++ ISCSI_INITIAL_SN; ++ } ++ ++ ictx->xstorm_ag_context.cdu_reserved = ++ CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG, ++ ISCSI_CONNECTION_TYPE); ++ ictx->ustorm_ag_context.cdu_usage = ++ CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG, ++ ISCSI_CONNECTION_TYPE); ++ return 0; ++ ++} ++ ++static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[], ++ u32 num, int *work) ++{ ++ struct iscsi_kwqe_conn_offload1 *req1; ++ struct iscsi_kwqe_conn_offload2 *req2; ++ struct cnic_local *cp = dev->cnic_priv; ++ struct iscsi_kcqe kcqe; ++ struct kcqe *cqes[1]; ++ u32 l5_cid; ++ int ret; ++ ++ if (num < 2) { ++ *work = num; ++ return -EINVAL; ++ } ++ ++ req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0]; ++ req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1]; ++ if ((num - 2) < req2->num_additional_wqes) { ++ *work = num; ++ return -EINVAL; ++ } ++ *work = 2 + req2->num_additional_wqes;; ++ ++ l5_cid = req1->iscsi_conn_id; ++ if (l5_cid >= MAX_ISCSI_TBL_SZ) ++ return -EINVAL; ++ ++ memset(&kcqe, 0, sizeof(kcqe)); ++ kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN; ++ kcqe.iscsi_conn_id = l5_cid; ++ kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE; ++ ++ if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) { ++ atomic_dec(&cp->iscsi_conn); ++ ret = 0; ++ goto done; ++ } ++ ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid); ++ if (ret) { ++ atomic_dec(&cp->iscsi_conn); ++ ret = 0; ++ goto done; ++ } ++ ret = cnic_setup_bnx2x_ctx(dev, wqes, num); ++ if (ret < 0) { ++ cnic_free_bnx2x_conn_resc(dev, l5_cid); ++ atomic_dec(&cp->iscsi_conn); ++ goto done; ++ } ++ ++ kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS; ++ kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp->ctx_tbl[l5_cid].cid, ++ cp->func); ++ ++done: ++ cqes[0] = (struct kcqe *) &kcqe; ++ cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1); ++ return ret; ++} ++ ++ ++static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct iscsi_kwqe_conn_update *req = ++ (struct iscsi_kwqe_conn_update *) kwqe; ++ void *data; ++ union l5cm_specific_data l5_data; ++ u32 l5_cid, cid = BNX2X_SW_CID(req->context_id); ++ int ret; ++ ++ if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0) ++ return -EINVAL; ++ ++ data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data); ++ if (!data) ++ return -ENOMEM; ++ ++ memcpy(data, kwqe, sizeof(struct kwqe)); ++ ++ ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN, ++ req->context_id, ISCSI_CONNECTION_TYPE, &l5_data); ++ return ret; ++} ++ ++static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct iscsi_kwqe_conn_destroy *req = ++ (struct iscsi_kwqe_conn_destroy *) kwqe; ++ union l5cm_specific_data l5_data; ++ u32 l5_cid = req->iscsi_conn_id; ++ struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; ++ int ret = 0; ++ struct iscsi_kcqe kcqe; ++ struct kcqe *cqes[1]; ++ ++ if (!(ctx->ctx_flags & CTX_FL_OFFLD_START)) ++ goto skip_cfc_delete; ++ ++ while (!time_after(jiffies, ctx->timestamp + (2 * HZ))) ++ msleep(250); ++ ++ init_waitqueue_head(&ctx->waitq); ++ ctx->wait_cond = 0; ++ memset(&l5_data, 0, sizeof(l5_data)); ++ ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL, ++ req->context_id, ++ ETH_CONNECTION_TYPE | ++ (1 << SPE_HDR_COMMON_RAMROD_SHIFT), ++ &l5_data); ++ if (ret == 0) ++ wait_event(ctx->waitq, ctx->wait_cond); ++ ++skip_cfc_delete: ++ cnic_free_bnx2x_conn_resc(dev, l5_cid); ++ ++ atomic_dec(&cp->iscsi_conn); ++ ++ memset(&kcqe, 0, sizeof(kcqe)); ++ kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN; ++ kcqe.iscsi_conn_id = l5_cid; ++ kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS; ++ kcqe.iscsi_conn_context_id = req->context_id; ++ ++ cqes[0] = (struct kcqe *) &kcqe; ++ cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1); ++ ++ return ret; ++} ++ ++static void cnic_init_storm_conn_bufs(struct cnic_dev *dev, ++ struct l4_kwq_connect_req1 *kwqe1, ++ struct l4_kwq_connect_req3 *kwqe3, ++ struct l5cm_active_conn_buffer *conn_buf) ++{ ++ struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf; ++ struct l5cm_xstorm_conn_buffer *xstorm_buf = ++ &conn_buf->xstorm_conn_buffer; ++ struct l5cm_tstorm_conn_buffer *tstorm_buf = ++ &conn_buf->tstorm_conn_buffer; ++ struct regpair context_addr; ++ u32 cid = BNX2X_SW_CID(kwqe1->cid); ++ struct in6_addr src_ip, dst_ip; ++ int i; ++ u32 *addrp; ++ ++ addrp = (u32 *) &conn_addr->local_ip_addr; ++ for (i = 0; i < 4; i++, addrp++) ++ src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp); ++ ++ addrp = (u32 *) &conn_addr->remote_ip_addr; ++ for (i = 0; i < 4; i++, addrp++) ++ dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp); ++ ++ cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr); ++ ++ xstorm_buf->context_addr.hi = context_addr.hi; ++ xstorm_buf->context_addr.lo = context_addr.lo; ++ xstorm_buf->mss = 0xffff; ++ xstorm_buf->rcv_buf = kwqe3->rcv_buf; ++ if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE) ++ xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE; ++ xstorm_buf->pseudo_header_checksum = ++ swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0)); ++ ++ if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK)) ++ tstorm_buf->params |= ++ L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE; ++ if (kwqe3->ka_timeout) { ++ tstorm_buf->ka_enable = 1; ++ tstorm_buf->ka_timeout = kwqe3->ka_timeout; ++ tstorm_buf->ka_interval = kwqe3->ka_interval; ++ tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count; ++ } ++ tstorm_buf->rcv_buf = kwqe3->rcv_buf; ++ tstorm_buf->snd_buf = kwqe3->snd_buf; ++ tstorm_buf->max_rt_time = 0xffffffff; ++} ++ ++static void cnic_init_bnx2x_mac(struct cnic_dev *dev, u8 *mac) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ int func = CNIC_FUNC(cp); ++ ++ CNIC_WR8(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(func), mac[0]); ++ CNIC_WR8(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(func), mac[1]); ++ CNIC_WR8(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(func), mac[2]); ++ CNIC_WR8(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(func), mac[3]); ++ CNIC_WR8(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(func), mac[4]); ++ CNIC_WR8(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(func), mac[5]); ++ ++ CNIC_WR8(dev, BAR_TSTRORM_INTMEM + ++ TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func), mac[5]); ++ CNIC_WR8(dev, BAR_TSTRORM_INTMEM + ++ TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func) + 1, ++ mac[4]); ++ CNIC_WR8(dev, BAR_TSTRORM_INTMEM + ++ TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func), mac[3]); ++ CNIC_WR8(dev, BAR_TSTRORM_INTMEM + ++ TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 1, ++ mac[2]); ++ CNIC_WR8(dev, BAR_TSTRORM_INTMEM + ++ TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 2, ++ mac[1]); ++ CNIC_WR8(dev, BAR_TSTRORM_INTMEM + ++ TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 3, ++ mac[0]); ++} ++ ++static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN; ++ u16 tstorm_flags = 0; ++ ++ if (tcp_ts) { ++ xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED; ++ tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED; ++ } ++ ++ CNIC_WR8(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), xstorm_flags); ++ ++ CNIC_WR16(dev, BAR_TSTRORM_INTMEM + ++ TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), tstorm_flags); ++} ++ ++static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[], ++ u32 num, int *work) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct l4_kwq_connect_req1 *kwqe1 = ++ (struct l4_kwq_connect_req1 *) wqes[0]; ++ struct l4_kwq_connect_req3 *kwqe3; ++ struct l5cm_active_conn_buffer *conn_buf; ++ struct l5cm_conn_addr_params *conn_addr; ++ union l5cm_specific_data l5_data; ++ u32 l5_cid = kwqe1->pg_cid; ++ struct cnic_sock *csk = &cp->csk_tbl[l5_cid]; ++ struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; ++#ifdef __VMKLNX__ ++ char vmknic[VMK_VMKNIC_NAME_MAX]; ++ vmk_EthAddress srcMACAddr; ++#else ++ struct neighbour *neigh = csk->dst->neighbour; ++#endif ++ int ret; ++ ++ if (num < 2) { ++ *work = num; ++ return -EINVAL; ++ } ++ ++ if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) ++ *work = 3; ++ else ++ *work = 2; ++ ++ if (num < *work) { ++ *work = num; ++ return -EINVAL; ++ } ++ ++ if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) { ++ printk(KERN_ERR PFX "%s: conn_buf size too big\n", ++ dev->netdev->name); ++ return -ENOMEM; ++ } ++ conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data); ++ if (!conn_buf) ++ return -ENOMEM; ++ ++ memset(conn_buf, 0, sizeof(*conn_buf)); ++ ++ conn_addr = &conn_buf->conn_addr_buf; ++#ifdef __VMKLNX__ ++ conn_addr->remote_addr_0 = csk->ha[0]; ++ conn_addr->remote_addr_1 = csk->ha[1]; ++ conn_addr->remote_addr_2 = csk->ha[2]; ++ conn_addr->remote_addr_3 = csk->ha[3]; ++ conn_addr->remote_addr_4 = csk->ha[4]; ++ conn_addr->remote_addr_5 = csk->ha[5]; ++ ++ /* Retrieve the MAC of the vmknic */ ++ if (vmk_IscsiNetHandleGetVmknic(cp->iscsiNetHandle, vmknic) != VMK_OK) ++ return -EINVAL; ++ if (vmk_VmknicMACAddrGet(vmknic, srcMACAddr) != VMK_OK) ++ return -EINVAL; ++ ++ cnic_init_bnx2x_mac(dev, srcMACAddr); ++#else ++ conn_addr->remote_addr_0 = neigh->ha[0]; ++ conn_addr->remote_addr_1 = neigh->ha[1]; ++ conn_addr->remote_addr_2 = neigh->ha[2]; ++ conn_addr->remote_addr_3 = neigh->ha[3]; ++ conn_addr->remote_addr_4 = neigh->ha[4]; ++ conn_addr->remote_addr_5 = neigh->ha[5]; ++#endif ++ ++ if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) { ++ struct l4_kwq_connect_req2 *kwqe2 = ++ (struct l4_kwq_connect_req2 *) wqes[1]; ++ ++ conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4; ++ conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3; ++ conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2; ++ ++ conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4; ++ conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3; ++ conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2; ++ conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION; ++ } ++ kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1]; ++ ++ conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip; ++ conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip; ++ conn_addr->local_tcp_port = kwqe1->src_port; ++ conn_addr->remote_tcp_port = kwqe1->dst_port; ++ ++ conn_addr->pmtu = kwqe3->pmtu; ++ cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf); ++ ++ CNIC_WR16(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->func), csk->vlan_id); ++ ++ cnic_bnx2x_set_tcp_timestamp(dev, ++ kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP); ++ ++ ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT, ++ kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data); ++ if (!ret) ++ ctx->ctx_flags |= CTX_FL_OFFLD_START; ++ ++ return ret; ++} ++ ++static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe) ++{ ++ struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe; ++ union l5cm_specific_data l5_data; ++ int ret; ++ ++ memset(&l5_data, 0, sizeof(l5_data)); ++ ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE, ++ req->cid, ISCSI_CONNECTION_TYPE, &l5_data); ++ return ret; ++} ++ ++static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe) ++{ ++ struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe; ++ union l5cm_specific_data l5_data; ++ int ret; ++ ++ memset(&l5_data, 0, sizeof(l5_data)); ++ ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT, ++ req->cid, ISCSI_CONNECTION_TYPE, &l5_data); ++ return ret; ++} ++static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe) ++{ ++ struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe; ++ struct l4_kcq kcqe; ++ struct kcqe *cqes[1]; ++ ++ memset(&kcqe, 0, sizeof(kcqe)); ++ kcqe.pg_host_opaque = req->host_opaque; ++ kcqe.pg_cid = req->host_opaque; ++ kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG; ++ cqes[0] = (struct kcqe *) &kcqe; ++ cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1); ++ return 0; ++} ++ ++static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe) ++{ ++ struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe; ++ struct l4_kcq kcqe; ++ struct kcqe *cqes[1]; ++ ++ memset(&kcqe, 0, sizeof(kcqe)); ++ kcqe.pg_host_opaque = req->pg_host_opaque; ++ kcqe.pg_cid = req->pg_cid; ++ kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG; ++ cqes[0] = (struct kcqe *) &kcqe; ++ cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1); ++ return 0; ++} ++ ++static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[], ++ u32 num_wqes) ++{ ++ int i, work, ret; ++ u32 opcode; ++ struct kwqe *kwqe; ++ ++ if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) ++ return -EAGAIN; /* bnx2 is down */ ++ ++ for (i = 0; i < num_wqes; ) { ++ kwqe = wqes[i]; ++ opcode = KWQE_OPCODE(kwqe->kwqe_op_flag); ++ work = 1; ++ ++ switch (opcode) { ++ case ISCSI_KWQE_OPCODE_INIT1: ++ ret = cnic_bnx2x_iscsi_init1(dev, kwqe); ++ break; ++ case ISCSI_KWQE_OPCODE_INIT2: ++ ret = cnic_bnx2x_iscsi_init2(dev, kwqe); ++ break; ++ case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1: ++ ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i], ++ num_wqes - i, &work); ++ break; ++ case ISCSI_KWQE_OPCODE_UPDATE_CONN: ++ ret = cnic_bnx2x_iscsi_update(dev, kwqe); ++ break; ++ case ISCSI_KWQE_OPCODE_DESTROY_CONN: ++ ret = cnic_bnx2x_iscsi_destroy(dev, kwqe); ++ break; ++ case L4_KWQE_OPCODE_VALUE_CONNECT1: ++ ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i, ++ &work); ++ break; ++ case L4_KWQE_OPCODE_VALUE_CLOSE: ++ ret = cnic_bnx2x_close(dev, kwqe); ++ break; ++ case L4_KWQE_OPCODE_VALUE_RESET: ++ ret = cnic_bnx2x_reset(dev, kwqe); ++ break; ++ case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG: ++ ret = cnic_bnx2x_offload_pg(dev, kwqe); ++ break; ++ case L4_KWQE_OPCODE_VALUE_UPDATE_PG: ++ ret = cnic_bnx2x_update_pg(dev, kwqe); ++ break; ++ case L4_KWQE_OPCODE_VALUE_UPLOAD_PG: ++ ret = 0; ++ break; ++ default: ++ ret = 0; ++ printk(KERN_ERR PFX "%s: Unknown type of KWQE(0x%x)\n", ++ dev->netdev->name, opcode); ++ break; ++ } ++ if (ret < 0) ++ printk(KERN_ERR PFX "%s: KWQE(0x%x) failed\n", ++ dev->netdev->name, opcode); ++ i += work; ++ } ++ return 0; ++} ++ ++static void service_kcqes(struct cnic_dev *dev, int num_cqes) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ int i, j; ++ ++ i = 0; ++ j = 1; ++ while (num_cqes) { ++ struct cnic_ulp_ops *ulp_ops; ++ int ulp_type; ++ u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag; ++ u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK; ++ ++ if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION)) ++ cnic_kwq_completion(dev, 1); ++ ++ while (j < num_cqes) { ++ u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag; ++ ++ if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer) ++ break; ++ ++ if (unlikely(next_op & KCQE_RAMROD_COMPLETION)) ++ cnic_kwq_completion(dev, 1); ++ j++; ++ } ++ ++ if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA) ++ ulp_type = CNIC_ULP_RDMA; ++ else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI) ++ ulp_type = CNIC_ULP_ISCSI; ++ else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4) ++ ulp_type = CNIC_ULP_L4; ++ else { ++ printk(KERN_ERR PFX "%s: Unknown type of KCQE(0x%x)\n", ++ dev->netdev->name, kcqe_op_flag); ++ goto end; ++ } ++ ++ rcu_read_lock(); ++ ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]); ++ if (likely(ulp_ops)) { ++ ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type], ++ cp->completed_kcq + i, j); ++ } ++ rcu_read_unlock(); ++end: ++ num_cqes -= j; ++ i += j; ++ j = 1; ++ } ++ return; ++} ++ ++static u16 cnic_bnx2_next_idx(u16 idx) ++{ ++ return (idx + 1); ++} ++ ++static u16 cnic_bnx2_hw_idx(u16 idx) ++{ ++ return idx; ++} ++ ++static u16 cnic_bnx2x_next_idx(u16 idx) ++{ ++ idx++; ++ if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT) ++ idx++; ++ ++ return idx; ++} ++ ++static u16 cnic_bnx2x_hw_idx(u16 idx) ++{ ++ if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT) ++ idx++; ++ return idx; ++} ++ ++static int cnic_get_kcqes(struct cnic_dev *dev, u16 hw_prod, u16 *sw_prod) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ u16 i, ri, last; ++ struct kcqe *kcqe; ++ int kcqe_cnt = 0, last_cnt = 0; ++ ++ i = ri = last = *sw_prod; ++ ri &= MAX_KCQ_IDX; ++ ++ while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) { ++ kcqe = &cp->kcq[KCQ_PG(ri)][KCQ_IDX(ri)]; ++ cp->completed_kcq[kcqe_cnt++] = kcqe; ++ i = cp->next_idx(i); ++ ri = i & MAX_KCQ_IDX; ++ if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) { ++ last_cnt = kcqe_cnt; ++ last = i; ++ } ++ } ++ ++ *sw_prod = last; ++ return last_cnt; ++} ++ ++static int cnic_service_bnx2(void *data, void *status_blk) ++{ ++ struct cnic_dev *dev = data; ++ struct status_block *sblk = status_blk; ++ struct cnic_local *cp = dev->cnic_priv; ++ u32 status_idx = sblk->status_idx; ++ u16 hw_prod, sw_prod; ++ int kcqe_cnt; ++ ++ if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) ++ return status_idx; ++ ++ cp->kwq_con_idx = *cp->kwq_con_idx_ptr; ++ ++ hw_prod = sblk->status_completion_producer_index; ++ sw_prod = cp->kcq_prod_idx; ++ while (sw_prod != hw_prod) { ++ kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod); ++ if (kcqe_cnt == 0) ++ goto done; ++ ++ service_kcqes(dev, kcqe_cnt); ++ ++ /* Tell compiler that status_blk fields can change. */ ++ barrier(); ++ if (status_idx != sblk->status_idx) { ++ status_idx = sblk->status_idx; ++ cp->kwq_con_idx = *cp->kwq_con_idx_ptr; ++ hw_prod = sblk->status_completion_producer_index; ++ } else ++ break; ++ } ++ ++done: ++ CNIC_WR16(dev, cp->kcq_io_addr, sw_prod); ++ ++ cp->kcq_prod_idx = sw_prod; ++ return status_idx; ++} ++ ++static void cnic_service_bnx2_msix(unsigned long data) ++{ ++ struct cnic_dev *dev = (struct cnic_dev *) data; ++ struct cnic_local *cp = dev->cnic_priv; ++ struct status_block_msix *status_blk = cp->bnx2_status_blk; ++ u32 status_idx = status_blk->status_idx; ++ u16 hw_prod, sw_prod; ++ int kcqe_cnt; ++ ++ cp->kwq_con_idx = status_blk->status_cmd_consumer_index; ++ ++ hw_prod = status_blk->status_completion_producer_index; ++ sw_prod = cp->kcq_prod_idx; ++ while (sw_prod != hw_prod) { ++ kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod); ++ if (kcqe_cnt == 0) ++ goto done; ++ ++ service_kcqes(dev, kcqe_cnt); ++ ++ /* Tell compiler that status_blk fields can change. */ ++ barrier(); ++ if (status_idx != status_blk->status_idx) { ++ status_idx = status_blk->status_idx; ++ cp->kwq_con_idx = status_blk->status_cmd_consumer_index; ++ hw_prod = status_blk->status_completion_producer_index; ++ } else ++ break; ++ } ++ ++done: ++ CNIC_WR16(dev, cp->kcq_io_addr, sw_prod); ++ ++ cp->kcq_prod_idx = sw_prod; ++ cp->last_status_idx = status_idx; ++ CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num | ++ BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx); ++} ++ ++#if (LINUX_VERSION_CODE >= 0x20613) ++static irqreturn_t cnic_irq(int irq, void *dev_instance) ++#else ++static irqreturn_t cnic_irq(int irq, void *dev_instance, struct pt_regs *regs) ++#endif ++{ ++ struct cnic_dev *dev = dev_instance; ++ struct cnic_local *cp = dev->cnic_priv; ++ u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX; ++ ++ if (cp->ack_int) ++ cp->ack_int(dev); ++ ++ prefetch(cp->status_blk); ++ prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]); ++ ++ if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) ++ tasklet_schedule(&cp->cnic_irq_task); ++ ++ return IRQ_HANDLED; ++} ++ ++static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm, ++ u16 index, u8 op, u8 update) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 + ++ COMMAND_REG_INT_ACK); ++ struct igu_ack_register igu_ack; ++ ++ igu_ack.status_block_index = index; ++ igu_ack.sb_id_and_flags = ++ ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | ++ (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | ++ (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | ++ (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); ++ ++ CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack)); ++} ++ ++static void cnic_ack_bnx2x_msix(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID, 0, ++ IGU_INT_DISABLE, 0); ++} ++ ++static void cnic_service_bnx2x_bh(unsigned long data) ++{ ++ struct cnic_dev *dev = (struct cnic_dev *) data; ++ struct cnic_local *cp = dev->cnic_priv; ++ u16 hw_prod, sw_prod; ++#ifdef NEW_BNX2X_HSI ++ struct cstorm_status_block_c *sblk = ++ &cp->bnx2x_status_blk->c_status_block; ++#else ++ struct cstorm_status_block *sblk = ++ &cp->bnx2x_status_blk->c_status_block; ++#endif ++ u32 status_idx = sblk->status_block_index; ++ int kcqe_cnt; ++ ++ if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) ++ return; ++ ++ hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS]; ++ hw_prod = cp->hw_idx(hw_prod); ++ sw_prod = cp->kcq_prod_idx; ++ while (sw_prod != hw_prod) { ++ kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod); ++ if (kcqe_cnt == 0) ++ goto done; ++ ++ service_kcqes(dev, kcqe_cnt); ++ ++ /* Tell compiler that sblk fields can change. */ ++ barrier(); ++ if (status_idx == sblk->status_block_index) ++ break; ++ ++ status_idx = sblk->status_block_index; ++ hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS]; ++ hw_prod = cp->hw_idx(hw_prod); ++ } ++ ++done: ++ CNIC_WR16(dev, cp->kcq_io_addr, sw_prod + MAX_KCQ_IDX); ++ cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID, ++ status_idx, IGU_INT_ENABLE, 1); ++ ++ cp->kcq_prod_idx = sw_prod; ++ return; ++} ++ ++static int cnic_service_bnx2x(void *data, void *status_blk) ++{ ++ struct cnic_dev *dev = data; ++ struct cnic_local *cp = dev->cnic_priv; ++ u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX; ++ ++ prefetch(cp->status_blk); ++ prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]); ++ ++ if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) ++ tasklet_schedule(&cp->cnic_irq_task); ++ return 0; ++} ++ ++static void cnic_ulp_stop(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ int if_type; ++ ++ rcu_read_lock(); ++ for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) { ++ struct cnic_ulp_ops *ulp_ops; ++ ++ ulp_ops = rcu_dereference(cp->ulp_ops[if_type]); ++ if (!ulp_ops) ++ continue; ++ ++ if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type])) ++ ulp_ops->cnic_stop(cp->ulp_handle[if_type]); ++ } ++ rcu_read_unlock(); ++} ++ ++static void cnic_ulp_start(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ int if_type; ++ ++ rcu_read_lock(); ++ for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) { ++ struct cnic_ulp_ops *ulp_ops; ++ ++ ulp_ops = rcu_dereference(cp->ulp_ops[if_type]); ++ if (!ulp_ops) ++ continue; ++ ++ if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type])) ++ ulp_ops->cnic_start(cp->ulp_handle[if_type]); ++ } ++ rcu_read_unlock(); ++} ++ ++static int cnic_ctl(void *data, struct cnic_ctl_info *info) ++{ ++ struct cnic_dev *dev = data; ++#ifdef __VMKLNX__ ++ int i; ++#endif ++ ++ switch (info->cmd) { ++ case CNIC_CTL_STOP_CMD: ++ cnic_hold(dev); ++ mutex_lock(&cnic_lock); ++ ++ if (test_bit(CNIC_F_IF_UP, &dev->flags)) { ++ clear_bit(CNIC_F_IF_UP, &dev->flags); ++ cnic_ulp_stop(dev); ++#ifndef __VMKLNX__ ++ cnic_stop_hw(dev); ++#endif ++ } ++ ++ mutex_unlock(&cnic_lock); ++#ifdef __VMKLNX__ ++ i = 0; ++ while ((atomic_read(&dev->ref_count) > 1) && i < 100) { ++ msleep(100); ++ i++; ++ } ++ if (atomic_read(&dev->ref_count) > 1) ++ printk(KERN_ERR PFX "%s: cnic device did not unregister" ++ " during stop event.\n", dev->netdev->name); ++#endif ++ cnic_put(dev); ++ break; ++ case CNIC_CTL_START_CMD: ++ cnic_hold(dev); ++ mutex_lock(&cnic_lock); ++ ++ set_bit(CNIC_F_IF_UP, &dev->flags); ++ if (dev->use_count) { ++ if (!cnic_start_hw(dev)) ++ cnic_ulp_start(dev); ++ } ++ mutex_unlock(&cnic_lock); ++ cnic_put(dev); ++ break; ++ case CNIC_CTL_COMPLETION_CMD: { ++ u32 cid = BNX2X_SW_CID(info->data.comp.cid); ++ u32 l5_cid; ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) { ++ struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; ++ ++ ctx->wait_cond = 1; ++ wake_up(&ctx->waitq); ++ } ++ break; ++ } ++ default: ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static void cnic_ulp_init(struct cnic_dev *dev) ++{ ++ int i; ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ rcu_read_lock(); ++ for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) { ++ struct cnic_ulp_ops *ulp_ops; ++ ++ ulp_ops = rcu_dereference(cnic_ulp_tbl[i]); ++#ifdef __VMKLNX__ ++ if (!ulp_ops) ++#else ++ if (!ulp_ops || !try_module_get(ulp_ops->owner)) ++#endif ++ continue; ++ ++ if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i])) ++ ulp_ops->cnic_init(dev); ++ ++#ifndef __VMKLNX__ ++ module_put(ulp_ops->owner); ++#endif ++ } ++ rcu_read_unlock(); ++} ++ ++static void cnic_ulp_exit(struct cnic_dev *dev) ++{ ++ int i; ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ rcu_read_lock(); ++ for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) { ++ struct cnic_ulp_ops *ulp_ops; ++ ++ ulp_ops = rcu_dereference(cnic_ulp_tbl[i]); ++#ifdef __VMKLNX__ ++ if (!ulp_ops) ++#else ++ if (!ulp_ops || !try_module_get(ulp_ops->owner)) ++#endif ++ continue; ++ ++ if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i])) ++ ulp_ops->cnic_exit(dev); ++ ++#ifndef __VMKLNX__ ++ module_put(ulp_ops->owner); ++#endif ++ } ++ rcu_read_unlock(); ++} ++ ++static int cnic_queue_work(struct cnic_local *cp, u32 work_type, void *data) ++{ ++ struct cnic_work_node *node; ++ int bytes = sizeof(u32 *); ++ ++ spin_lock_bh(&cp->wr_lock); ++ ++ node = &cp->cnic_work_ring[cp->cnic_wr_prod]; ++ node->work_type = work_type; ++ if (work_type == WORK_TYPE_KCQE) ++ bytes = sizeof(struct kcqe); ++ if (work_type == WORK_TYPE_REDIRECT) ++ bytes = sizeof(struct cnic_redirect_entry); ++ memcpy(&node->work_data, data, bytes); ++ cp->cnic_wr_prod++; ++ cp->cnic_wr_prod &= WORK_RING_SIZE_MASK; ++ ++ spin_unlock_bh(&cp->wr_lock); ++ return 0; ++} ++ ++static int cnic_cm_offload_pg(struct cnic_sock *csk) ++{ ++ struct cnic_dev *dev = csk->dev; ++ struct l4_kwq_offload_pg *l4kwqe; ++ struct kwqe *wqes[1]; ++#ifdef __VMKLNX__ ++ struct cnic_local *cp = dev->cnic_priv; ++ char vmknic[VMK_VMKNIC_NAME_MAX]; ++ vmk_EthAddress srcMACAddr; ++#else ++ struct neighbour *neigh = csk->dst->neighbour; ++ struct net_device *netdev = neigh->dev; ++#endif ++ ++#ifdef __VMKLNX__ ++ /* Retrieve the MAC of the vmknic */ ++ if (vmk_IscsiNetHandleGetVmknic(cp->iscsiNetHandle, vmknic) != VMK_OK) ++ return -EINVAL; ++ if (vmk_VmknicMACAddrGet(vmknic, srcMACAddr) != VMK_OK) ++ return -EINVAL; ++#endif ++ ++#ifndef HAVE_NETEVENT ++#ifndef __VMKLNX__ ++ memcpy(csk->old_ha, &neigh->ha[0], 6); ++#endif ++#endif ++ l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1; ++ memset(l4kwqe, 0, sizeof(*l4kwqe)); ++ wqes[0] = (struct kwqe *) l4kwqe; ++ ++ l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG; ++ l4kwqe->flags = ++ L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT; ++ l4kwqe->l2hdr_nbytes = ETH_HLEN; ++#ifdef __VMKLNX__ ++ l4kwqe->da0 = csk->ha[0]; ++ l4kwqe->da1 = csk->ha[1]; ++ l4kwqe->da2 = csk->ha[2]; ++ l4kwqe->da3 = csk->ha[3]; ++ l4kwqe->da4 = csk->ha[4]; ++ l4kwqe->da5 = csk->ha[5]; ++ ++ l4kwqe->sa0 = srcMACAddr[0]; ++ l4kwqe->sa1 = srcMACAddr[1]; ++ l4kwqe->sa2 = srcMACAddr[2]; ++ l4kwqe->sa3 = srcMACAddr[3]; ++ l4kwqe->sa4 = srcMACAddr[4]; ++ l4kwqe->sa5 = srcMACAddr[5]; ++#else ++ l4kwqe->da0 = neigh->ha[0]; ++ l4kwqe->da1 = neigh->ha[1]; ++ l4kwqe->da2 = neigh->ha[2]; ++ l4kwqe->da3 = neigh->ha[3]; ++ l4kwqe->da4 = neigh->ha[4]; ++ l4kwqe->da5 = neigh->ha[5]; ++ ++ l4kwqe->sa0 = netdev->dev_addr[0]; ++ l4kwqe->sa1 = netdev->dev_addr[1]; ++ l4kwqe->sa2 = netdev->dev_addr[2]; ++ l4kwqe->sa3 = netdev->dev_addr[3]; ++ l4kwqe->sa4 = netdev->dev_addr[4]; ++ l4kwqe->sa5 = netdev->dev_addr[5]; ++#endif ++ ++ l4kwqe->etype = ETH_P_IP; ++ l4kwqe->ipid_count = DEF_IPID_COUNT; ++ l4kwqe->host_opaque = csk->l5_cid; ++ ++ if (csk->vlan_id) { ++ l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING; ++ l4kwqe->vlan_tag = csk->vlan_id; ++ l4kwqe->l2hdr_nbytes += 4; ++ } ++ ++ return (dev->submit_kwqes(dev, wqes, 1)); ++} ++ ++#ifndef __VMKLNX__ ++static int cnic_cm_update_pg(struct cnic_sock *csk) ++{ ++ struct cnic_dev *dev = csk->dev; ++ struct l4_kwq_update_pg *l4kwqe; ++ struct kwqe *wqes[1]; ++ struct neighbour *neigh = csk->dst->neighbour; ++ ++#ifndef HAVE_NETEVENT ++ memcpy(csk->old_ha, &neigh->ha[0], 6); ++#endif ++ l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1; ++ memset(l4kwqe, 0, sizeof(*l4kwqe)); ++ wqes[0] = (struct kwqe *) l4kwqe; ++ ++ l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG; ++ l4kwqe->flags = ++ L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT; ++ l4kwqe->pg_cid = csk->pg_cid; ++ l4kwqe->da0 = neigh->ha[0]; ++ l4kwqe->da1 = neigh->ha[1]; ++ l4kwqe->da2 = neigh->ha[2]; ++ l4kwqe->da3 = neigh->ha[3]; ++ l4kwqe->da4 = neigh->ha[4]; ++ l4kwqe->da5 = neigh->ha[5]; ++ ++ l4kwqe->pg_host_opaque = csk->l5_cid; ++ l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA; ++ ++ return (dev->submit_kwqes(dev, wqes, 1)); ++} ++#endif ++ ++static int cnic_cm_upload_pg(struct cnic_sock *csk) ++{ ++ struct cnic_dev *dev = csk->dev; ++ struct l4_kwq_upload *l4kwqe; ++ struct kwqe *wqes[1]; ++ ++ l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1; ++ memset(l4kwqe, 0, sizeof(*l4kwqe)); ++ wqes[0] = (struct kwqe *) l4kwqe; ++ ++ l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG; ++ l4kwqe->flags = ++ L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT; ++ l4kwqe->cid = csk->pg_cid; ++ ++ return (dev->submit_kwqes(dev, wqes, 1)); ++} ++ ++#ifdef HAVE_NETEVENT ++static void cnic_redirect(struct cnic_local *cp, struct dst_entry *new, ++ struct dst_entry *old) ++{ ++ int i, found = 0; ++ ++ for (i = 0; i < MAX_CM_SK_TBL_SZ && !found; i++) { ++ struct cnic_sock *csk; ++ struct cnic_redirect_entry cnic_redir; ++ ++ csk = &cp->csk_tbl[i]; ++ csk_hold(csk); ++ if (cnic_in_use(csk) && csk->dst == old) { ++ found = 1; ++ dst_hold(new); ++ dst_hold(old); ++ ++ cnic_redir.old_dst = old; ++ cnic_redir.new_dst = new; ++ cnic_queue_work(cp, WORK_TYPE_REDIRECT, &cnic_redir); ++ tasklet_schedule(&cp->cnic_task); ++ } ++ csk_put(csk); ++ } ++} ++ ++static void cnic_update_neigh(struct cnic_local *cp, struct neighbour *neigh) ++{ ++ int i, found = 0; ++ ++ for (i = 0; i < MAX_CM_SK_TBL_SZ && !found; i++) { ++ struct cnic_sock *csk; ++ ++ csk = &cp->csk_tbl[i]; ++ csk_hold(csk); ++ if (cnic_in_use(csk) && csk->dst) { ++ if (csk->dst->neighbour == neigh) { ++ found = 1; ++ neigh_hold(neigh); ++ ++ cnic_queue_work(cp, WORK_TYPE_NEIGH_UPDATE, ++ &neigh); ++ tasklet_schedule(&cp->cnic_task); ++ } ++ } ++ csk_put(csk); ++ } ++} ++ ++static int cnic_net_callback(struct notifier_block *this, unsigned long event, ++ void *ptr) ++{ ++ struct cnic_local *cp = container_of(this, struct cnic_local, cm_nb); ++ ++ if (event == NETEVENT_NEIGH_UPDATE) { ++ struct neighbour *neigh = ptr; ++ ++ cnic_update_neigh(cp, neigh); ++ ++ } else if (event == NETEVENT_REDIRECT) { ++ struct netevent_redirect *netevent = ptr; ++ struct dst_entry *old_dst = netevent->old; ++ struct dst_entry *new_dst = netevent->new; ++ ++ cnic_redirect(cp, new_dst, old_dst); ++ } ++ return 0; ++} ++#endif ++ ++static int cnic_cm_conn_req(struct cnic_sock *csk) ++{ ++ struct cnic_dev *dev = csk->dev; ++ struct l4_kwq_connect_req1 *l4kwqe1; ++ struct l4_kwq_connect_req2 *l4kwqe2; ++ struct l4_kwq_connect_req3 *l4kwqe3; ++ struct kwqe *wqes[3]; ++ u8 tcp_flags = 0; ++ int num_wqes = 2; ++ ++ l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1; ++ l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2; ++ l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3; ++ memset(l4kwqe1, 0, sizeof(*l4kwqe1)); ++ memset(l4kwqe2, 0, sizeof(*l4kwqe2)); ++ memset(l4kwqe3, 0, sizeof(*l4kwqe3)); ++ ++ l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3; ++ l4kwqe3->flags = ++ L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT; ++ l4kwqe3->ka_timeout = csk->ka_timeout; ++ l4kwqe3->ka_interval = csk->ka_interval; ++ l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count; ++ l4kwqe3->tos = csk->tos; ++ l4kwqe3->ttl = csk->ttl; ++ l4kwqe3->snd_seq_scale = csk->snd_seq_scale; ++ l4kwqe3->pmtu = csk->pmtu; ++ l4kwqe3->rcv_buf = csk->rcv_buf; ++ l4kwqe3->snd_buf = csk->snd_buf; ++ l4kwqe3->seed = csk->seed; ++ ++ wqes[0] = (struct kwqe *) l4kwqe1; ++ if (test_bit(SK_F_IPV6, &csk->flags)) { ++ wqes[1] = (struct kwqe *) l4kwqe2; ++ wqes[2] = (struct kwqe *) l4kwqe3; ++ num_wqes = 3; ++ ++ l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6; ++ l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2; ++ l4kwqe2->flags = ++ L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT | ++ L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT; ++ l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]); ++ l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]); ++ l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]); ++ l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]); ++ l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]); ++ l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]); ++ l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) - ++ sizeof(struct tcphdr); ++ } else { ++ wqes[1] = (struct kwqe *) l4kwqe3; ++ l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) - ++ sizeof(struct tcphdr); ++ } ++ ++ l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1; ++ l4kwqe1->flags = ++ (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) | ++ L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT; ++ l4kwqe1->cid = csk->cid; ++ l4kwqe1->pg_cid = csk->pg_cid; ++ l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]); ++ l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]); ++ l4kwqe1->src_port = be16_to_cpu(csk->src_port); ++ l4kwqe1->dst_port = be16_to_cpu(csk->dst_port); ++ if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK) ++ tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK; ++ if (csk->tcp_flags & SK_TCP_KEEP_ALIVE) ++ tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE; ++ if (csk->tcp_flags & SK_TCP_NAGLE) ++ tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE; ++ if (csk->tcp_flags & SK_TCP_TIMESTAMP) ++ tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP; ++ if (csk->tcp_flags & SK_TCP_SACK) ++ tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK; ++ if (csk->tcp_flags & SK_TCP_SEG_SCALING) ++ tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING; ++ ++ l4kwqe1->tcp_flags = tcp_flags; ++ ++ return (dev->submit_kwqes(dev, wqes, num_wqes)); ++} ++ ++static int cnic_cm_close_req(struct cnic_sock *csk) ++{ ++ struct cnic_dev *dev = csk->dev; ++ struct l4_kwq_close_req *l4kwqe; ++ struct kwqe *wqes[1]; ++ ++ l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2; ++ memset(l4kwqe, 0, sizeof(*l4kwqe)); ++ wqes[0] = (struct kwqe *) l4kwqe; ++ ++ l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE; ++ l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT; ++ l4kwqe->cid = csk->cid; ++ ++ return (dev->submit_kwqes(dev, wqes, 1)); ++} ++ ++static int cnic_cm_abort_req(struct cnic_sock *csk) ++{ ++ struct cnic_dev *dev = csk->dev; ++ struct l4_kwq_reset_req *l4kwqe; ++ struct kwqe *wqes[1]; ++ ++ l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2; ++ memset(l4kwqe, 0, sizeof(*l4kwqe)); ++ wqes[0] = (struct kwqe *) l4kwqe; ++ ++ l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET; ++ l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT; ++ l4kwqe->cid = csk->cid; ++ ++ return (dev->submit_kwqes(dev, wqes, 1)); ++} ++ ++static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid, ++ u32 l5_cid, struct cnic_sock **csk, void *context) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_sock *csk1; ++ ++ if (l5_cid >= MAX_CM_SK_TBL_SZ) ++ return -EINVAL; ++ ++ csk1 = &cp->csk_tbl[l5_cid]; ++ if (atomic_read(&csk1->ref_count)) ++ return -EAGAIN; ++ ++ if (test_and_set_bit(SK_F_INUSE, &csk1->flags)) ++ return -EBUSY; ++ ++ csk1->dev = dev; ++ csk1->cid = cid; ++ csk1->l5_cid = l5_cid; ++ csk1->ulp_type = ulp_type; ++ csk1->context = context; ++ ++ csk1->ka_timeout = DEF_KA_TIMEOUT; ++ csk1->ka_interval = DEF_KA_INTERVAL; ++ csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT; ++ csk1->tos = DEF_TOS; ++ csk1->ttl = DEF_TTL; ++ csk1->snd_seq_scale = DEF_SND_SEQ_SCALE; ++ csk1->rcv_buf = DEF_RCV_BUF; ++ csk1->snd_buf = DEF_SND_BUF; ++ csk1->seed = DEF_SEED; ++ ++ *csk = csk1; ++ ++ return 0; ++} ++ ++static void cnic_cm_cleanup(struct cnic_sock *csk) ++{ ++#ifndef __VMKLNX__ ++ if (csk->dst) { ++ if (csk->dst->neighbour) ++ neigh_release(csk->dst->neighbour); ++ dst_release(csk->dst); ++ csk->dst = NULL; ++ } ++ csk->src_port = 0; ++#endif ++ if (csk->src_port) { ++ struct cnic_dev *dev = csk->dev; ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ cnic_free_id(&cp->csk_port_tbl, ntohs(csk->src_port)); ++ csk->src_port = 0; ++ } ++} ++ ++static void cnic_close_conn(struct cnic_sock *csk) ++{ ++ if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) { ++ cnic_cm_upload_pg(csk); ++ clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags); ++ } ++ cnic_cm_cleanup(csk); ++ smp_mb__before_clear_bit(); ++ clear_bit(SK_F_OFFLD_SCHED, &csk->flags); ++} ++ ++static int cnic_cm_destroy(struct cnic_sock *csk) ++{ ++ if (!cnic_in_use(csk)) ++ return -EINVAL; ++ ++ csk_hold(csk); ++ clear_bit(SK_F_INUSE, &csk->flags); ++ smp_mb__after_clear_bit(); ++ while (atomic_read(&csk->ref_count) != 1) ++ msleep(1); ++ cnic_cm_cleanup(csk); ++ ++ csk->flags = 0; ++ csk_put(csk); ++ return 0; ++} ++ ++static inline u16 cnic_get_vlan(struct net_device *dev, ++ struct net_device **vlan_dev) ++{ ++#ifndef __VMKLNX__ ++ if (dev->priv_flags & IFF_802_1Q_VLAN) { ++#ifdef VLAN_DEV_INFO ++ *vlan_dev = VLAN_DEV_INFO(dev)->real_dev; ++ return VLAN_DEV_INFO(dev)->vlan_id; ++#else ++#ifdef VLAN_TX_COOKIE_MAGIC ++ *vlan_dev = vlan_dev_info(dev)->real_dev; ++ return vlan_dev_info(dev)->vlan_id; ++#else ++ *vlan_dev = vlan_dev_real_dev(dev); ++ return vlan_dev_vlan_id(dev); ++#endif ++#endif ++ } ++#endif ++ *vlan_dev = dev; ++ return 0; ++} ++ ++#ifndef __VMKLNX__ ++static int cnic_get_v4_route(struct sockaddr_in *dst_addr, ++ struct sockaddr_in *src_addr, ++ struct dst_entry **dst) ++{ ++ struct flowi fl; ++ int err; ++ struct rtable *rt; ++ ++ memset(&fl, 0, sizeof(fl)); ++ fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr; ++ if (src_addr) ++ fl.nl_u.ip4_u.saddr = src_addr->sin_addr.s_addr; ++ ++#if (LINUX_VERSION_CODE >= 0x020619) ++ err = ip_route_output_key(&init_net, &rt, &fl); ++#else ++ err = ip_route_output_key(&rt, &fl); ++#endif ++ if (!err) ++ *dst = &rt->u.dst; ++ return err; ++} ++ ++#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) ++static struct dst_entry *cnic_ip6_rte_output(struct sock *sk, struct flowi *fl) ++{ ++#if (LINUX_VERSION_CODE >= 0x02061a) ++ struct dst_entry *(*fn)(struct net *, struct sock *, struct flowi *); ++#else ++ struct dst_entry *(*fn)(struct sock *, struct flowi *); ++#endif ++ struct dst_entry *dst = NULL; ++ ++ fn = __symbol_get("ip6_route_output"); ++ if (fn) { ++#if (LINUX_VERSION_CODE >= 0x02061a) ++ dst = (*fn)(&init_net, sk, fl); ++#else ++ dst = (*fn)(sk, fl); ++#endif ++ __symbol_put("ip6_route_output"); ++ } ++ return dst; ++} ++ ++static int cnic_ipv6_addr_type(const struct in6_addr *addr) ++{ ++ int (*fn)(const struct in6_addr *addr); ++ int type = 0; ++ ++ fn = __symbol_get("__ipv6_addr_type"); ++ if (fn) { ++ type = fn(addr) & 0xffff; ++ __symbol_put("__ipv6_addr_type"); ++ } ++ return type; ++} ++ ++static int cnic_ipv6_get_saddr(struct dst_entry *dst, ++ const struct in6_addr *daddr, ++ struct in6_addr *saddr) ++{ ++ int rc = -ENOENT; ++ ++#if (LINUX_VERSION_CODE >= 0x02061b) ++ int (*fn)(struct net *, struct net_device *, ++ const struct in6_addr *daddr, unsigned int prefs, ++ struct in6_addr *saddr); ++ ++ fn = __symbol_get("ipv6_dev_get_saddr"); ++ if (fn) { ++ rc = fn(&init_net, dst->dev, daddr, 0, saddr); ++ __symbol_put("ipv6_dev_get_saddr"); ++ } ++ ++#elif (LINUX_VERSION_CODE >= 0x02061a) ++ int (*fn)(struct net_device *, ++ const struct in6_addr *daddr, unsigned int prefs, ++ struct in6_addr *saddr); ++ ++ fn = __symbol_get("ipv6_dev_get_saddr"); ++ if (fn) { ++ rc = fn(dst->dev, daddr, 0, saddr); ++ __symbol_put("ipv6_dev_get_saddr"); ++ } ++ ++#else ++ int (*fn)(struct dst_entry *, ++ const struct in6_addr *daddr, struct in6_addr *saddr); ++ ++ fn = __symbol_get("ipv6_get_saddr"); ++ if (fn) { ++ rc = fn(dst, daddr, saddr); ++ __symbol_put("ipv6_get_saddr"); ++ } ++#endif ++ return rc; ++} ++ ++#endif ++ ++static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr, ++ struct sockaddr_in6 *src_addr, ++ struct dst_entry **dst) ++{ ++#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) ++ struct flowi fl; ++ ++ memset(&fl, 0, sizeof(fl)); ++ ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr); ++ if (cnic_ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL) ++ fl.oif = dst_addr->sin6_scope_id; ++ ++ if (src_addr) ++ ipv6_addr_copy(&fl.fl6_src, &src_addr->sin6_addr); ++ ++ *dst = cnic_ip6_rte_output(NULL, &fl); ++ if (*dst) ++ return 0; ++#endif ++ ++ return -ENETUNREACH; ++} ++#endif /*__VMKLNX__*/ ++ ++#ifdef __VMKLNX__ ++static struct cnic_dev *cnic_cm_select_dev(vmk_IscsiNetHandle iscsiNetHandle, ++ struct sockaddr_in *dst_addr, ++ int ulp_type) ++{ ++ char vmknic[VMK_VMKNIC_NAME_MAX]; ++ char devName[VMK_UPLINK_DEVICE_NAME_MAX]; ++ struct cnic_dev *dev; ++ int found = 0; ++ VMK_ReturnStatus status; ++ ++ /* Retrieve the uplink device name corresponding to the vmknic */ ++ status = vmk_IscsiNetHandleGetVmknic(iscsiNetHandle, vmknic); ++ if (status != VMK_OK) ++ return NULL; ++ status = vmk_IscsiNetVmknicGetUplinkDevName(iscsiNetHandle, devName); ++ if (status != VMK_OK) ++ return NULL; ++ ++#ifndef __VMKLNX__ ++ read_lock(&cnic_dev_lock); ++#endif ++ list_for_each_entry(dev, &cnic_dev_list, list) { ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ if (dev->netdev && test_bit(CNIC_F_IF_UP, &dev->flags)) { ++ if (!strcmp(dev->netdev->name, devName)) { ++ found = 1; ++ strcpy(cp->vmknic, vmknic); ++ memcpy(&cp->iscsiNetHandle, &iscsiNetHandle, ++ sizeof(iscsiNetHandle)); ++ cp->iscsiNetHandle.ptr = cp->vmknic; ++ ++ /* Allocate TCP ports, only once per device */ ++ if (cp->csk_port_tbl.table) ++ break; ++ ++ strcpy(cp->first_vmknic, vmknic); ++ memcpy(&cp->first_iscsiNetHandle, ++ &iscsiNetHandle, sizeof(iscsiNetHandle)); ++ cp->first_iscsiNetHandle.ptr = cp->first_vmknic; ++ cp->cnic_local_port_nr = MAX_CM_SK_TBL_SZ; ++ cp->cnic_local_port_min = 1; ++ status = vmk_IscsiNetTcpPortAlloc( ++ cp->first_iscsiNetHandle, ++ &cp->cnic_local_port_nr, ++ &cp->cnic_local_port_min); ++ if (status != VMK_OK) ++ printk(KERN_ALERT "%s TCP port alloc failed %d\n", ++ dev->netdev->name, status); ++ if (status == VMK_OK || status == VMK_EXISTS) { ++ cnic_init_id_tbl(&cp->csk_port_tbl, ++ cp->cnic_local_port_nr, ++ cp->cnic_local_port_min, ++ cp->next_tcp_port); ++ } else { ++ found = 0; ++ } ++ break; ++ } ++ } ++ } ++#ifndef __VMKLNX__ ++ read_unlock(&cnic_dev_lock); ++#endif ++ ++ if (!found) ++ dev = NULL; ++ return dev; ++} ++ ++#else ++static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr, ++ int ulp_type) ++{ ++ struct cnic_dev *dev = NULL; ++ struct dst_entry *dst; ++ struct net_device *netdev = NULL; ++ int err = -ENETUNREACH, found = 0; ++ ++ if (dst_addr->sin_family == AF_INET) ++ err = cnic_get_v4_route(dst_addr, NULL, &dst); ++ else if (dst_addr->sin_family == AF_INET6) { ++ struct sockaddr_in6 *dst_addr6 = ++ (struct sockaddr_in6 *) dst_addr; ++ ++ err = cnic_get_v6_route(dst_addr6, NULL, &dst); ++ } else ++ return NULL; ++ ++ if (err) ++ return NULL; ++ ++ if (!dst->dev) ++ goto done; ++ ++ cnic_get_vlan(dst->dev, &netdev); ++ ++ read_lock(&cnic_dev_lock); ++ list_for_each_entry(dev, &cnic_dev_list, list) { ++ if (netdev == dev->netdev) { ++ found = 1; ++ break; ++ } ++ } ++ read_unlock(&cnic_dev_lock); ++ ++done: ++ dst_release(dst); ++ if (!found) ++ dev = NULL; ++ return dev; ++} ++#endif /*__VMKLNX__*/ ++ ++#ifndef __VMKLNX__ ++static int cnic_resolve_addr(struct cnic_sock *csk) ++{ ++ struct neighbour *neigh = csk->dst->neighbour; ++ int err = 0; ++#ifndef HAVE_NETEVENT ++ int retry = 0; ++#endif ++ ++ if (neigh->nud_state & NUD_VALID) { ++ err = -EINVAL; ++ if (cnic_offld_prep(csk)) ++ err = cnic_cm_offload_pg(csk); ++ goto done; ++ } ++ ++ set_bit(SK_F_NDISC_WAITING, &csk->flags); ++ neigh_event_send(neigh, NULL); ++#ifndef HAVE_NETEVENT ++ while (!(neigh->nud_state & NUD_VALID) && (retry < 3)) { ++ msleep(1000); ++ retry++; ++ } ++ if (!(neigh->nud_state & NUD_VALID)) ++ err = -ETIMEDOUT; ++ else { ++ err = -EINVAL; ++ if (cnic_offld_prep(csk)) ++ err = cnic_cm_offload_pg(csk); ++ } ++ clear_bit(SK_F_NDISC_WAITING, &csk->flags); ++#endif ++done: ++ return err; ++} ++ ++static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr) ++{ ++ struct cnic_dev *dev = csk->dev; ++ int is_v6, err; ++ struct dst_entry *dst; ++ struct net_device *realdev; ++ ++ if (saddr->local.v6.sin6_family == AF_INET6 && ++ saddr->remote.v6.sin6_family == AF_INET6) ++ is_v6 = 1; ++ else if (saddr->local.v4.sin_family == AF_INET && ++ saddr->remote.v4.sin_family == AF_INET) ++ is_v6 = 0; ++ else ++ return -EINVAL; ++ ++ clear_bit(SK_F_IPV6, &csk->flags); ++ ++ if (is_v6) { ++#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) ++ set_bit(SK_F_IPV6, &csk->flags); ++ err = cnic_get_v6_route(&saddr->remote.v6, ++ &saddr->local.v6, &dst); ++ if (err) ++ return err; ++ ++ if (!dst || dst->error || !dst->dev) ++ goto err_out; ++ ++ cnic_ipv6_get_saddr(dst, &saddr->remote.v6.sin6_addr, ++ &saddr->local.v6.sin6_addr); ++ ++ memcpy(&csk->src_ip[0], &saddr->local.v6.sin6_addr, ++ sizeof(struct in6_addr)); ++ memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr, ++ sizeof(struct in6_addr)); ++ csk->src_port = saddr->local.v6.sin6_port; ++ csk->dst_port = saddr->remote.v6.sin6_port; ++#else ++ return -ENETUNREACH; ++#endif ++ ++ } else { ++ err = cnic_get_v4_route(&saddr->remote.v4, &saddr->local.v4, ++ &dst); ++ if (err) ++ return err; ++ ++ if (!dst || dst->error || !dst->dev) ++ goto err_out; ++ ++ csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr; ++ csk->src_ip[0] = saddr->local.v4.sin_addr.s_addr; ++ csk->src_port = saddr->local.v4.sin_port; ++ csk->dst_port = saddr->remote.v4.sin_port; ++ ++ if (csk->src_ip[0] == 0) { ++ csk->src_ip[0] = ++ inet_select_addr(dst->dev, csk->dst_ip[0], ++ RT_SCOPE_LINK); ++ } ++ } ++ ++ csk->vlan_id = cnic_get_vlan(dst->dev, &realdev); ++ if (realdev != dev->netdev) ++ goto err_out; ++ ++ csk->dst = dst; ++ csk->pmtu = dst_mtu(csk->dst); ++ return 0; ++ ++err_out: ++ dst_release(dst); ++ return -ENETUNREACH; ++} ++#else ++ ++static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr) ++{ ++ struct cnic_dev *dev = csk->dev; ++ struct cnic_local *cp = dev->cnic_priv; ++ char vmknic[VMK_VMKNIC_NAME_MAX]; ++ vmk_SocketAddress srcIPAddr, dstIPAddr; ++ vmk_EthAddress nextHopMAC; ++ vmk_int32 pmtu; ++ vmk_uint16 vlanId; ++ int err, retry = 0; ++ int local_port; ++ ++ if (saddr->local.v4.sin_family != AF_INET && ++ saddr->remote.v4.sin_family != AF_INET6) ++ return -EINVAL; ++ ++ /* Currently we only support IPv4 */ ++ memcpy(&dstIPAddr, &saddr->remote, sizeof(vmk_SocketIPAddress)); ++ dstIPAddr.sa_family = VMK_SOCKET_AF_INET; ++ ++ /* Next hop (arp) resolve */ ++ while (retry++ < 10) { ++ err = vmk_IscsiNetNextHopMACLookup(cp->iscsiNetHandle, dstIPAddr, nextHopMAC); ++ if (nextHopMAC[0] || nextHopMAC[1] || nextHopMAC[2]) { ++ if (!err) ++ break; ++ } ++ msleep(100); ++ } ++ ++ if (err) ++ return err; ++ ++ if (!nextHopMAC[0] && !nextHopMAC[1] && !nextHopMAC[2]) { ++ printk(KERN_ALERT "Zero next hop address, aborting\n"); ++ return -EINVAL; ++ } ++ ++ if (!cnic_offld_prep(csk)) ++ return -EINVAL; ++ ++ clear_bit(SK_F_IPV6, &csk->flags); ++ ++ memcpy(csk->ha, nextHopMAC, 6); ++ local_port = cnic_alloc_new_id(&cp->csk_port_tbl); ++ if (local_port == -1) { ++ clear_bit(SK_F_OFFLD_SCHED, &csk->flags); ++ return -ENOMEM; ++ } ++ ++ if (vmk_IscsiNetPmtuLookup(cp->iscsiNetHandle, dstIPAddr, &pmtu) == VMK_OK) ++ csk->pmtu = pmtu; ++ else ++ csk->pmtu = 1500; ++ ++ /* Retrieve the IP Address of the vmknic */ ++ srcIPAddr.sa_family = VMK_SOCKET_AF_INET; ++ if (vmk_IscsiNetHandleGetVmknic(cp->iscsiNetHandle, vmknic) != VMK_OK) ++ return -EINVAL; ++ if (vmk_VmknicIPAddrGet(vmknic, &srcIPAddr) != VMK_OK) ++ return -EINVAL; ++ ++ csk->src_ip[0] = ((vmk_SocketIPAddress *)&srcIPAddr)->sin_addr.s_addr; ++ csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr; ++ csk->src_port = htons(local_port); ++ csk->dst_port = saddr->remote.v4.sin_port; ++ ++ if (vmk_IscsiNetVmknicGetVlanID(cp->iscsiNetHandle, &vlanId) != VMK_OK) ++ return -EINVAL; ++ ++ csk->vlan_id = vlanId; ++ ++ err = cnic_cm_offload_pg(csk); ++ ++ return err; ++} ++#endif /*__VMKLNX__*/ ++ ++static void cnic_init_csk_state(struct cnic_sock *csk) ++{ ++ csk->state = 0; ++ clear_bit(SK_F_OFFLD_SCHED, &csk->flags); ++ clear_bit(SK_F_CLOSING, &csk->flags); ++} ++ ++static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr) ++{ ++#ifndef __VMKLNX__ ++ struct neighbour *neigh; ++#endif ++ int err = 0; ++ ++ if (!cnic_in_use(csk)) ++ return -EINVAL; ++ ++ if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags)) ++ return -EINVAL; ++ ++ cnic_init_csk_state(csk); ++ ++ err = cnic_get_route(csk, saddr); ++ if (err) ++ goto err_out; ++ ++#ifndef __VMKLNX__ ++ neigh = csk->dst->neighbour; ++ if (!neigh) ++ goto err_out; ++ ++ neigh_hold(neigh); ++ ++ err = cnic_resolve_addr(csk); ++ if (!err) ++ return 0; ++ ++ neigh_release(neigh); ++ ++#endif ++err_out: ++#ifndef __VMKLNX__ ++ if (csk->dst) { ++ dst_release(csk->dst); ++ csk->dst = NULL; ++ } ++#endif ++ clear_bit(SK_F_CONNECT_START, &csk->flags); ++ return err; ++} ++ ++static int cnic_cm_abort(struct cnic_sock *csk) ++{ ++ struct cnic_local *cp = csk->dev->cnic_priv; ++ u32 opcode; ++ ++ if (!cnic_in_use(csk)) ++ return -EINVAL; ++ ++ clear_bit(SK_F_NDISC_WAITING, &csk->flags); ++ clear_bit(SK_F_CONNECT_START, &csk->flags); ++ smp_mb__after_clear_bit(); ++ if (cnic_abort_prep(csk)) ++ return (cnic_cm_abort_req(csk)); ++ ++ /* Getting here means that we haven't started connect, or ++ * connect was not successful. ++ */ ++ ++ csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP; ++ if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) ++ opcode = csk->state; ++ else ++ opcode = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD; ++ cp->close_conn(csk, opcode); ++ ++ return 0; ++} ++ ++static int cnic_cm_close(struct cnic_sock *csk) ++{ ++ if (!cnic_in_use(csk)) ++ return -EINVAL; ++ ++ if (cnic_close_prep(csk)) { ++ csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP; ++ return (cnic_cm_close_req(csk)); ++ } ++ return 0; ++} ++ ++static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk, ++ u8 opcode) ++{ ++ struct cnic_ulp_ops *ulp_ops; ++ int ulp_type = csk->ulp_type; ++ ++ rcu_read_lock(); ++ ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]); ++ if (ulp_ops) { ++ if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE) ++ ulp_ops->cm_connect_complete(csk); ++ else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) ++ ulp_ops->cm_close_complete(csk); ++ else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) ++ ulp_ops->cm_remote_abort(csk); ++ else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP) ++ ulp_ops->cm_abort_complete(csk); ++ else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED) ++ ulp_ops->cm_remote_close(csk); ++ } ++ rcu_read_unlock(); ++} ++ ++static int cnic_cm_set_pg(struct cnic_sock *csk) ++{ ++#ifndef __VMKLNX__ ++ struct neighbour *neigh = csk->dst->neighbour; ++ int valid = neigh->nud_state & NUD_VALID; ++ ++ if (!valid) { ++ if (test_and_clear_bit(SK_F_NDISC_WAITING, &csk->flags)) { ++ clear_bit(SK_F_CONNECT_START, &csk->flags); ++ cnic_cm_cleanup(csk); ++ return -ETIMEDOUT; ++ } ++ } ++ ++ if (cnic_offld_prep(csk)) { ++ if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) ++ cnic_cm_update_pg(csk); ++ else ++ cnic_cm_offload_pg(csk); ++ } ++ clear_bit(SK_F_NDISC_WAITING, &csk->flags); ++#endif ++ return 0; ++} ++ ++static void cnic_cm_process_neigh(struct cnic_dev *dev, struct neighbour *neigh) ++{ ++#ifndef __VMKLNX__ ++ struct cnic_local *cp = dev->cnic_priv; ++ int i; ++ ++ for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) { ++ struct cnic_sock *csk; ++ int abort = 0; ++ ++ csk = &cp->csk_tbl[i]; ++ csk_hold(csk); ++ if (cnic_in_use(csk) && csk->dst && ++ csk->dst->neighbour == neigh) { ++ if (cnic_cm_set_pg(csk)) ++ abort = 1; ++ } ++ if (abort) ++ cnic_cm_upcall(cp, csk, ++ L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE); ++ csk_put(csk); ++ } ++ neigh_release(neigh); ++#endif ++} ++ ++static void cnic_cm_process_redirect(struct cnic_dev *dev, ++ struct cnic_redirect_entry *redir) ++{ ++#ifndef __VMKLNX__ ++ struct cnic_local *cp = dev->cnic_priv; ++ int i; ++ ++ for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) { ++ struct cnic_sock *csk; ++ int abort = 0; ++ ++ csk = &cp->csk_tbl[i]; ++ csk_hold(csk); ++ if (cnic_in_use(csk) && csk->dst == redir->old_dst) { ++ csk->dst = redir->new_dst; ++ dst_hold(csk->dst); ++ neigh_hold(csk->dst->neighbour); ++ if (redir->old_dst->neighbour); ++ neigh_release(redir->old_dst->neighbour); ++ dst_release(redir->old_dst); ++ if (cnic_cm_set_pg(csk)) ++ abort = 1; ++ } ++ if (abort) ++ cnic_cm_upcall(cp, csk, ++ L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE); ++ csk_put(csk); ++ } ++ ++ dst_release(redir->new_dst); ++ dst_release(redir->old_dst); ++#endif ++} ++ ++static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ u32 l5_cid = kcqe->pg_host_opaque; ++ u8 opcode = kcqe->op_code; ++ struct cnic_sock *csk = &cp->csk_tbl[l5_cid]; ++ ++ csk_hold(csk); ++ if (!cnic_in_use(csk)) ++ goto done; ++ ++ if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) { ++ clear_bit(SK_F_OFFLD_SCHED, &csk->flags); ++ goto done; ++ } ++ /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */ ++ if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) { ++ clear_bit(SK_F_OFFLD_SCHED, &csk->flags); ++ cnic_cm_upcall(cp, csk, ++ L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE); ++ goto done; ++ } ++ ++ csk->pg_cid = kcqe->pg_cid; ++ set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags); ++ cnic_cm_conn_req(csk); ++ ++done: ++ csk_put(csk); ++} ++ ++static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe; ++ u8 opcode = l4kcqe->op_code; ++ u32 l5_cid; ++ struct cnic_sock *csk; ++ ++ if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG || ++ opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) { ++ cnic_cm_process_offld_pg(dev, l4kcqe); ++ return; ++ } ++ ++ l5_cid = l4kcqe->conn_id; ++ /* Hack */ ++ if (opcode & 0x80) ++ l5_cid = l4kcqe->cid; ++ if (l5_cid >= MAX_CM_SK_TBL_SZ) ++ return; ++ ++ csk = &cp->csk_tbl[l5_cid]; ++ csk_hold(csk); ++ ++ if (!cnic_in_use(csk)) { ++ csk_put(csk); ++ return; ++ } ++ ++ switch (opcode) { ++ case L5CM_RAMROD_CMD_ID_TCP_CONNECT: ++ if (l4kcqe->status != 0) { ++ clear_bit(SK_F_OFFLD_SCHED, &csk->flags); ++ cnic_cm_upcall(cp, csk, ++ L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE); ++ } ++ break; ++ case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE: ++ if (l4kcqe->status == 0) ++ set_bit(SK_F_OFFLD_COMPLETE, &csk->flags); ++ ++ smp_mb__before_clear_bit(); ++ clear_bit(SK_F_OFFLD_SCHED, &csk->flags); ++ cnic_cm_upcall(cp, csk, opcode); ++ break; ++ ++ case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED: ++ if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) ++ csk->state = opcode; ++ /* fall through */ ++ case L4_KCQE_OPCODE_VALUE_CLOSE_COMP: ++ case L4_KCQE_OPCODE_VALUE_RESET_COMP: ++ case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE: ++ case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD: ++ cp->close_conn(csk, opcode); ++ break; ++ ++ case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED: ++ cnic_cm_upcall(cp, csk, opcode); ++ break; ++ } ++ csk_put(csk); ++} ++ ++static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num_cqe) ++{ ++ struct cnic_dev *dev = data; ++ int i; ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ for (i = 0; i < num_cqe; i++) ++ cnic_queue_work(cp, WORK_TYPE_KCQE, kcqe[i]); ++ ++ tasklet_schedule(&cp->cnic_task); ++} ++ ++static void cnic_cm_indicate_event(void *data, unsigned long event) ++{ ++} ++ ++static void cnic_cm_dummy(void *data) ++{ ++} ++ ++static struct cnic_ulp_ops cm_ulp_ops = { ++ .cnic_start = cnic_cm_dummy, ++ .cnic_stop = cnic_cm_dummy, ++ .indicate_kcqes = cnic_cm_indicate_kcqe, ++ .indicate_netevent = cnic_cm_indicate_event, ++ .indicate_inetevent = cnic_cm_indicate_event, ++}; ++ ++static void cnic_task(unsigned long data) ++{ ++ struct cnic_local *cp = (struct cnic_local *) data; ++ struct cnic_dev *dev = cp->dev; ++ u32 cons = cp->cnic_wr_cons; ++ u32 prod = cp->cnic_wr_prod; ++ ++ while (cons != prod) { ++ struct cnic_work_node *node; ++ ++ node = &cp->cnic_work_ring[cons]; ++ if (node->work_type == WORK_TYPE_KCQE) ++ cnic_cm_process_kcqe(dev, &node->work_data.kcqe); ++ else if (node->work_type == WORK_TYPE_NEIGH_UPDATE) ++ cnic_cm_process_neigh(dev, node->work_data.neigh); ++ else if (node->work_type == WORK_TYPE_REDIRECT) ++ cnic_cm_process_redirect(dev, ++ &node->work_data.cnic_redir); ++ cons++; ++ cons &= WORK_RING_SIZE_MASK; ++ } ++ cp->cnic_wr_cons = cons; ++} ++ ++static void cnic_free_dev(struct cnic_dev *dev) ++{ ++ int i = 0; ++ ++ while ((atomic_read(&dev->ref_count) != 0) && i < 10) { ++ msleep(100); ++ i++; ++ } ++ if (atomic_read(&dev->ref_count) != 0) ++ printk(KERN_ERR PFX "%s: Failed waiting for ref count to go" ++ " to zero.\n", dev->netdev->name); ++ ++ printk(KERN_INFO PFX "Removed CNIC device: %s\n", dev->netdev->name); ++ dev_put(dev->netdev); ++ kfree(dev); ++} ++ ++static void cnic_cm_free_mem(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ kfree(cp->csk_tbl); ++ cp->csk_tbl = NULL; ++ cp->next_tcp_port = cnic_free_id_tbl(&cp->csk_port_tbl); ++} ++ ++static int cnic_cm_alloc_mem(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ cp->csk_tbl = kmalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ, ++ GFP_KERNEL); ++ if (!cp->csk_tbl) ++ return -ENOMEM; ++ memset(cp->csk_tbl, 0, sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ); ++ ++ return 0; ++} ++ ++#ifndef HAVE_NETEVENT ++#ifndef __VMKLNX__ ++static void cnic_timer(unsigned long data) ++{ ++ struct cnic_local *cp = (struct cnic_local *) data; ++ struct cnic_dev *dev = cp->dev; ++ int i, found = 0; ++ struct neighbour *neigh = NULL; ++ ++ if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) ++ return; ++ ++ for (i = 0; i < MAX_CM_SK_TBL_SZ && !found; i++) { ++ struct cnic_sock *csk; ++ ++ csk = &cp->csk_tbl[i]; ++ csk_hold(csk); ++ if (cnic_in_use(csk) && csk->dst && ++ test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) { ++ neigh = csk->dst->neighbour; ++ if (memcmp(csk->old_ha, neigh->ha, 6)) { ++ found = 1; ++ neigh_hold(neigh); ++ ++ cnic_queue_work(cp, WORK_TYPE_NEIGH_UPDATE, ++ &neigh); ++ tasklet_schedule(&cp->cnic_task); ++ } ++ } ++ csk_put(csk); ++ } ++ ++ cp->cnic_timer.expires = jiffies + cp->cnic_timer_off; ++ add_timer(&cp->cnic_timer); ++} ++#endif ++#endif ++ ++static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode) ++{ ++ if ((opcode == csk->state) || ++ (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED && ++ csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)) { ++ if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) ++ return 1; ++ } ++ return 0; ++} ++ ++static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode) ++{ ++ struct cnic_dev *dev = csk->dev; ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ clear_bit(SK_F_CONNECT_START, &csk->flags); ++ if (cnic_ready_to_close(csk, opcode)) { ++ cnic_close_conn(csk); ++ cnic_cm_upcall(cp, csk, opcode); ++ } ++} ++ ++static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev) ++{ ++} ++ ++static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev) ++{ ++ u32 seed; ++ ++#if (LINUX_VERSION_CODE >= 0x020612) ++ get_random_bytes(&seed, 4); ++#else ++ seed = 0x12345678; ++#endif ++ cnic_ctx_wr(dev, 45, 0, seed); ++ return 0; ++} ++ ++static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode) ++{ ++ struct cnic_dev *dev = csk->dev; ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid]; ++ union l5cm_specific_data l5_data; ++ u32 cmd = 0; ++ int close_complete = 0; ++ ++ switch (opcode) { ++ case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED: ++ case L4_KCQE_OPCODE_VALUE_CLOSE_COMP: ++ case L4_KCQE_OPCODE_VALUE_RESET_COMP: ++ if (cnic_ready_to_close(csk, opcode)) ++ cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE; ++ break; ++ case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE: ++ cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD; ++ break; ++ case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD: ++ close_complete = 1; ++ break; ++ } ++ if (cmd) { ++ memset(&l5_data, 0, sizeof(l5_data)); ++ ++ cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE, ++ &l5_data); ++ } else if (close_complete) { ++ ctx->timestamp = jiffies; ++ cnic_close_conn(csk); ++ cnic_cm_upcall(cp, csk, csk->state); ++ } ++} ++ ++static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev) ++{ ++} ++ ++static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ int func = CNIC_FUNC(cp); ++ struct net_device *netdev = dev->netdev; ++ ++ cnic_init_bnx2x_mac(dev, netdev->dev_addr); ++ cnic_bnx2x_set_tcp_timestamp(dev, 1); ++ ++ CNIC_WR16(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_LOCAL_VLAN_OFFSET(func), 0); ++ ++ CNIC_WR(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(func), 1); ++ CNIC_WR(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(func), ++ DEF_MAX_DA_COUNT); ++ ++ CNIC_WR8(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(func), DEF_TTL); ++ CNIC_WR8(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(func), DEF_TOS); ++ CNIC_WR8(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(func), 2); ++ CNIC_WR(dev, BAR_XSTRORM_INTMEM + ++ XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(func), DEF_SWS_TIMER); ++ ++ CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(func), ++ DEF_MAX_CWND); ++ return 0; ++} ++ ++static int cnic_cm_open(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ int err; ++ ++ err = cnic_cm_alloc_mem(dev); ++ if (err) ++ return err; ++ ++ err = cp->start_cm(dev); ++ ++ if (err) ++ goto err_out; ++ ++ spin_lock_init(&cp->wr_lock); ++ ++ tasklet_init(&cp->cnic_task, &cnic_task, (unsigned long) cp); ++ ++#ifdef HAVE_NETEVENT ++ cp->cm_nb.notifier_call = cnic_net_callback; ++ register_netevent_notifier(&cp->cm_nb); ++#else ++#ifndef __VMKLNX__ ++ init_timer(&cp->cnic_timer); ++ cp->cnic_timer_off = 2 * HZ; ++ cp->cnic_timer.expires = jiffies + cp->cnic_timer_off; ++ cp->cnic_timer.data = (unsigned long) cp; ++ cp->cnic_timer.function = cnic_timer; ++ add_timer(&cp->cnic_timer); ++#endif ++#endif ++ ++ dev->cm_create = cnic_cm_create; ++ dev->cm_destroy = cnic_cm_destroy; ++ dev->cm_connect = cnic_cm_connect; ++ dev->cm_abort = cnic_cm_abort; ++ dev->cm_close = cnic_cm_close; ++ dev->cm_select_dev = cnic_cm_select_dev; ++ ++ cp->ulp_handle[CNIC_ULP_L4] = dev; ++ rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops); ++ return 0; ++ ++err_out: ++ cnic_cm_free_mem(dev); ++ return err; ++} ++ ++static int cnic_cm_shutdown(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ int i; ++ ++ cp->stop_cm(dev); ++ ++#ifdef HAVE_NETEVENT ++ unregister_netevent_notifier(&cp->cm_nb); ++#else ++#ifndef __VMKLNX__ ++ del_timer_sync(&cp->cnic_timer); ++#endif ++#endif ++ ++ tasklet_kill(&cp->cnic_task); ++ ++ if (!cp->csk_tbl) ++ return 0; ++ ++ for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) { ++ struct cnic_sock *csk = &cp->csk_tbl[i]; ++ ++ clear_bit(SK_F_INUSE, &csk->flags); ++ cnic_cm_cleanup(csk); ++ } ++ cnic_cm_free_mem(dev); ++ ++ return 0; ++} ++ ++static void cnic_init_context(struct cnic_dev *dev, u32 cid) ++{ ++ u32 cid_addr; ++ int i; ++ ++ cid_addr = GET_CID_ADDR(cid); ++ ++ for (i = 0; i < CTX_SIZE; i += 4) ++ cnic_ctx_wr(dev, cid_addr, i, 0); ++} ++ ++static int cnic_setup_5709_context(struct cnic_dev *dev, int valid) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ int ret = 0, i; ++ u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0; ++ ++ if (CHIP_NUM(cp) != CHIP_NUM_5709) ++ return 0; ++ ++ for (i = 0; i < cp->ctx_blks; i++) { ++ int j; ++ u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk; ++ u32 val; ++ ++ memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE); ++ ++ CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0, ++ (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit); ++ CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1, ++ (u64) cp->ctx_arr[i].mapping >> 32); ++ CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx | ++ BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); ++ for (j = 0; j < 10; j++) { ++ ++ val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL); ++ if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) ++ break; ++ udelay(5); ++ } ++ if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) { ++ ret = -EBUSY; ++ break; ++ } ++ } ++ return ret; ++} ++ ++static void cnic_free_irq(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ ++ if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) { ++ cp->disable_int_sync(dev); ++ tasklet_kill(&cp->cnic_irq_task); ++ free_irq(ethdev->irq_arr[0].vector, dev); ++ } ++} ++ ++static int cnic_init_bnx2_irq(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ ++ if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) { ++ int err, i = 0; ++ int sblk_num = cp->status_blk_num; ++ u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) + ++ BNX2_HC_SB_CONFIG_1; ++ ++ CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT); ++ ++ CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8); ++ CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220); ++ CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220); ++ ++ cp->bnx2_status_blk = cp->status_blk; ++ cp->last_status_idx = cp->bnx2_status_blk->status_idx; ++ tasklet_init(&cp->cnic_irq_task, &cnic_service_bnx2_msix, ++ (unsigned long) dev); ++ err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, ++ "cnic", dev); ++ if (err) { ++ tasklet_disable(&cp->cnic_irq_task); ++ return err; ++ } ++ while (cp->bnx2_status_blk->status_completion_producer_index && ++ i < 10) { ++ CNIC_WR(dev, BNX2_HC_COALESCE_NOW, ++ 1 << (11 + sblk_num)); ++ udelay(10); ++ i++; ++ barrier(); ++ } ++ if (cp->bnx2_status_blk->status_completion_producer_index) { ++ cnic_free_irq(dev); ++ goto failed; ++ } ++ ++ } else { ++ struct status_block *sblk = cp->status_blk; ++ u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND); ++ int i = 0; ++ ++ while (sblk->status_completion_producer_index && i < 10) { ++ CNIC_WR(dev, BNX2_HC_COMMAND, ++ hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); ++ udelay(10); ++ i++; ++ barrier(); ++ } ++ if (sblk->status_completion_producer_index) ++ goto failed; ++ ++ } ++ return 0; ++ ++failed: ++ printk(KERN_ERR PFX "%s: " "KCQ index not resetting to 0.\n", ++ dev->netdev->name); ++ return -EBUSY; ++} ++ ++static void cnic_enable_bnx2_int(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ ++ if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)) ++ return; ++ ++ CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num | ++ BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx); ++} ++ ++static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ ++ if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)) ++ return; ++ ++ CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num | ++ BNX2_PCICFG_INT_ACK_CMD_MASK_INT); ++ CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD); ++ synchronize_irq(ethdev->irq_arr[0].vector); ++} ++ ++static void cnic_get_bnx2_iscsi_info(struct cnic_dev *dev) ++{ ++ u32 max_conn; ++ ++ max_conn = cnic_reg_rd_ind(dev, BNX2_FW_MAX_ISCSI_CONN); ++ dev->max_iscsi_conn = max_conn; ++} ++ ++static int cnic_start_bnx2_hw(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ struct status_block *sblk = cp->status_blk; ++ u32 val; ++ int err; ++ ++ val = CNIC_RD(dev, BNX2_MQ_CONFIG); ++ val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; ++ if (BCM_PAGE_BITS > 12) ++ val |= (12 - 8) << 4; ++ else ++ val |= (BCM_PAGE_BITS - 8) << 4; ++ ++ CNIC_WR(dev, BNX2_MQ_CONFIG, val); ++ ++ CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8); ++ CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220); ++ CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220); ++ ++ err = cnic_setup_5709_context(dev, 1); ++ if (err) ++ return err; ++ ++ cnic_init_context(dev, KWQ_CID); ++ cnic_init_context(dev, KCQ_CID); ++ ++ cp->kwq_cid_addr = GET_CID_ADDR(KWQ_CID); ++ cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX; ++ ++ cp->max_kwq_idx = MAX_KWQ_IDX; ++ cp->kwq_prod_idx = 0; ++ cp->kwq_con_idx = 0; ++ cp->cnic_local_flags |= CNIC_LCL_FL_KWQ_INIT; ++ ++ if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708) ++ cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15; ++ else ++ cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index; ++ ++ /* Initialize the kernel work queue context. */ ++ val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE | ++ (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ; ++ cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_TYPE, val); ++ ++ val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16; ++ cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val); ++ ++ val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT; ++ cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val); ++ ++ val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32); ++ cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val); ++ ++ val = (u32) cp->kwq_info.pgtbl_map; ++ cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val); ++ ++ cp->kcq_cid_addr = GET_CID_ADDR(KCQ_CID); ++ cp->kcq_io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX; ++ ++ cp->kcq_prod_idx = 0; ++ ++ /* Initialize the kernel complete queue context. */ ++ val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE | ++ (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ; ++ cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_TYPE, val); ++ ++ val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16; ++ cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val); ++ ++ val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT; ++ cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val); ++ ++ val = (u32) ((u64) cp->kcq_info.pgtbl_map >> 32); ++ cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val); ++ ++ val = (u32) cp->kcq_info.pgtbl_map; ++ cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val); ++ ++ if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) { ++ u32 sb_id = cp->status_blk_num; ++ u32 sb = BNX2_L2CTX_STATUSB_NUM(sb_id); ++ ++ cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT; ++ cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb); ++ cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb); ++ } ++ ++ /* Enable Commnad Scheduler notification when we write to the ++ * host producer index of the kernel contexts. */ ++ CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2); ++ ++ /* Enable Command Scheduler notification when we write to either ++ * the Send Queue or Receive Queue producer indexes of the kernel ++ * bypass contexts. */ ++ CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7); ++ CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7); ++ ++ /* Notify COM when the driver post an application buffer. */ ++ CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000); ++ ++ /* Set the CP and COM doorbells. These two processors polls the ++ * doorbell for a non zero value before running. This must be done ++ * after setting up the kernel queue contexts. */ ++ val = cnic_reg_rd_ind(dev, BNX2_CP_SCRATCH + 0x20); ++ cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, val | 1); ++ ++ val = cnic_reg_rd_ind(dev, BNX2_COM_SCRATCH + 0x20); ++ cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, val | 1); ++ ++ err = cnic_init_bnx2_irq(dev); ++ if (err) { ++ printk(KERN_ERR PFX "%s: cnic_init_irq failed\n", ++ dev->netdev->name); ++ ++ val = cnic_reg_rd_ind(dev, BNX2_CP_SCRATCH + 0x20); ++ cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, val & ~0x1); ++ ++ val = cnic_reg_rd_ind(dev, BNX2_COM_SCRATCH + 0x20); ++ cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, val & ~0x1); ++ ++ return err; ++ } ++ ++ cnic_get_bnx2_iscsi_info(dev); ++ ++ return 0; ++} ++ ++static void cnic_setup_bnx2x_context(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ u32 start_offset = ethdev->ctx_tbl_offset; ++ int i; ++ ++ for (i = 0; i < cp->ctx_blks; i++) { ++ struct cnic_ctx *ctx = &cp->ctx_arr[i]; ++ dma_addr_t map = ctx->mapping; ++ ++ if (cp->ctx_align) { ++ unsigned long mask = cp->ctx_align - 1; ++ ++ map = (map + mask) & ~mask; ++ } ++ ++ cnic_ctx_tbl_wr(dev, start_offset + i, map); ++ } ++} ++ ++static int cnic_init_bnx2x_irq(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ int err = 0; ++ ++ cp->bnx2x_status_blk = cp->status_blk; ++ ++ tasklet_init(&cp->cnic_irq_task, &cnic_service_bnx2x_bh, ++ (unsigned long) dev); ++ if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) { ++ err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, ++ "cnic", dev); ++ if (err) ++ tasklet_disable(&cp->cnic_irq_task); ++ } ++ return err; ++} ++ ++static void cnic_enable_bnx2x_int(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ u8 sb_id = cp->status_blk_num; ++ int port = CNIC_PORT(cp); ++ ++#ifdef NEW_BNX2X_HSI ++ CNIC_WR8(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id, ++ HC_INDEX_C_ISCSI_EQ_CONS), ++ 64 / 12); ++ CNIC_WR16(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id, ++ HC_INDEX_C_ISCSI_EQ_CONS), 0); ++#else ++ CNIC_WR8(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id, ++ HC_INDEX_C_ISCSI_EQ_CONS), ++ 64 / 12); ++ CNIC_WR16(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, ++ HC_INDEX_C_ISCSI_EQ_CONS), 0); ++#endif ++} ++ ++static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev) ++{ ++} ++ ++static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ u32 base, addr, val; ++ int port = CNIC_PORT(cp); ++ ++ dev->max_iscsi_conn = 0; ++ base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR); ++ if (base < 0xa0000 || base >= 0xc0000) ++ return; ++ ++ addr = BNX2X_SHMEM_ADDR(base, validity_map[port]); ++ val = CNIC_RD(dev, addr); ++ ++ if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) { ++ u16 val16; ++ ++ addr = BNX2X_SHMEM_ADDR(base, ++ drv_lic_key[port].max_iscsi_init_conn); ++ val16 = CNIC_RD16(dev, addr); ++ ++ if (val16) ++ val16 ^= 0x1e1e; ++ dev->max_iscsi_conn = val16; ++ } ++ if (BNX2X_CHIP_IS_E1H(cp->chip_id)) { ++ int func = CNIC_FUNC(cp); ++ ++ addr = BNX2X_SHMEM_ADDR(base, ++ mf_cfg.func_mf_config[func].e1hov_tag); ++ val = CNIC_RD(dev, addr); ++ val &= FUNC_MF_CFG_E1HOV_TAG_MASK; ++ if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { ++ addr = BNX2X_SHMEM_ADDR(base, ++ mf_cfg.func_mf_config[func].config); ++ val = CNIC_RD(dev, addr); ++ val &= FUNC_MF_CFG_PROTOCOL_MASK; ++ if (val != FUNC_MF_CFG_PROTOCOL_ISCSI) ++ dev->max_iscsi_conn = 0; ++ } ++ } ++} ++ ++static int cnic_start_bnx2x_hw(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ int func = CNIC_FUNC(cp), ret, i; ++ int port = CNIC_PORT(cp); ++ u32 start_cid = ethdev->starting_cid; ++ u16 eq_idx; ++ u8 sb_id = cp->status_blk_num; ++ ++ ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ, start_cid, 0); ++ ++ if (ret) ++ return -ENOMEM; ++ ++ cp->kcq_io_addr = BAR_CSTRORM_INTMEM + ++ CSTORM_ISCSI_EQ_PROD_OFFSET(func, 0); ++ cp->kcq_prod_idx = 0; ++ ++ cnic_get_bnx2x_iscsi_info(dev); ++ ++ /* Only 1 EQ */ ++ CNIC_WR16(dev, cp->kcq_io_addr, MAX_KCQ_IDX); ++ CNIC_WR(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_ISCSI_EQ_CONS_OFFSET(func, 0), 0); ++ CNIC_WR(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0), ++ cp->kcq_info.pg_map_arr[1] & 0xffffffff); ++ CNIC_WR(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0) + 4, ++ (u64) cp->kcq_info.pg_map_arr[1] >> 32); ++ CNIC_WR(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0), ++ cp->kcq_info.pg_map_arr[0] & 0xffffffff); ++ CNIC_WR(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0) + 4, ++ (u64) cp->kcq_info.pg_map_arr[0] >> 32); ++ CNIC_WR8(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(func, 0), 1); ++ CNIC_WR16(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_ISCSI_EQ_SB_NUM_OFFSET(func, 0), cp->status_blk_num); ++ CNIC_WR8(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(func, 0), ++ HC_INDEX_C_ISCSI_EQ_CONS); ++ ++ for (i = 0; i < cp->conn_buf_info.num_pages; i++) { ++ CNIC_WR(dev, BAR_TSTRORM_INTMEM + ++ TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i), ++ cp->conn_buf_info.pgtbl[2 * i]); ++ CNIC_WR(dev, BAR_TSTRORM_INTMEM + ++ TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i) + 4, ++ cp->conn_buf_info.pgtbl[(2 * i) + 1]); ++ } ++ ++ CNIC_WR(dev, BAR_USTRORM_INTMEM + ++ USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func), ++ cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff); ++ CNIC_WR(dev, BAR_USTRORM_INTMEM + ++ USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func) + 4, ++ (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32); ++ ++ cnic_setup_bnx2x_context(dev); ++ ++#ifdef NEW_BNX2X_HSI ++ eq_idx = CNIC_RD16(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) + ++ offsetof(struct cstorm_status_block_c, ++ index_values[HC_INDEX_C_ISCSI_EQ_CONS])); ++#else ++ eq_idx = CNIC_RD16(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id) + ++ offsetof(struct cstorm_status_block, ++ index_values[HC_INDEX_C_ISCSI_EQ_CONS])); ++#endif ++ if (eq_idx != 0) { ++ printk(KERN_ERR PFX "%s: EQ cons index %x != 0\n", ++ dev->netdev->name, eq_idx); ++ return -EBUSY; ++ } ++ ret = cnic_init_bnx2x_irq(dev); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int cnic_start_hw(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ int err; ++ ++ if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) ++ return -EALREADY; ++ ++#ifndef __VMKLNX__ ++ if (!try_module_get(ethdev->drv_owner)) ++ return -EBUSY; ++#endif ++ err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev); ++ if (err) { ++ printk(KERN_ERR PFX "%s: register_cnic failed\n", ++ dev->netdev->name); ++ goto err2; ++ } ++ ++ dev->regview = ethdev->io_base; ++ cp->chip_id = ethdev->chip_id; ++ pci_dev_get(dev->pcidev); ++ cp->func = PCI_FUNC(dev->pcidev->devfn); ++ cp->status_blk = ethdev->irq_arr[0].status_blk; ++ cp->status_blk_num = ethdev->irq_arr[0].status_blk_num; ++ ++ err = cp->alloc_resc(dev); ++ if (err) { ++ printk(KERN_ERR PFX "%s: allocate resource failure\n", ++ dev->netdev->name); ++ goto err1; ++ } ++ ++ err = cp->start_hw(dev); ++ if (err) ++ goto err1; ++ ++ err = cnic_cm_open(dev); ++ if (err) ++ goto err1; ++ ++ set_bit(CNIC_F_CNIC_UP, &dev->flags); ++ ++ cp->enable_int(dev); ++ ++ return 0; ++ ++err1: ++ ethdev->drv_unregister_cnic(dev->netdev); ++ cp->free_resc(dev); ++ pci_dev_put(dev->pcidev); ++err2: ++#ifndef __VMKLNX__ ++ module_put(ethdev->drv_owner); ++#endif ++ return err; ++} ++ ++static void cnic_stop_bnx2_hw(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ u32 val; ++ ++ cnic_disable_bnx2_int_sync(dev); ++ ++ val = cnic_reg_rd_ind(dev, BNX2_CP_SCRATCH + 0x20); ++ cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, val & ~0x1); ++ ++ val = cnic_reg_rd_ind(dev, BNX2_COM_SCRATCH + 0x20); ++ cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, val & ~0x1); ++ ++ cnic_init_context(dev, KWQ_CID); ++ cnic_init_context(dev, KCQ_CID); ++ ++ cnic_setup_5709_context(dev, 0); ++ cnic_free_irq(dev); ++ ++ ethdev->drv_unregister_cnic(dev->netdev); ++ ++ cnic_free_resc(dev); ++} ++ ++static void cnic_stop_bnx2x_hw(struct cnic_dev *dev) ++{ ++ struct cnic_local *cp = dev->cnic_priv; ++ struct cnic_eth_dev *ethdev = cp->ethdev; ++ u8 sb_id = cp->status_blk_num; ++ int port = CNIC_PORT(cp); ++ ++ cnic_free_irq(dev); ++ ethdev->drv_unregister_cnic(dev->netdev); ++#ifdef NEW_BNX2X_HSI ++ CNIC_WR16(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) + ++ offsetof(struct cstorm_status_block_c, ++ index_values[HC_INDEX_C_ISCSI_EQ_CONS]), ++ 0); ++#else ++ CNIC_WR16(dev, BAR_CSTRORM_INTMEM + ++ CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id) + ++ offsetof(struct cstorm_status_block, ++ index_values[HC_INDEX_C_ISCSI_EQ_CONS]), ++ 0); ++#endif ++ cnic_free_resc(dev); ++} ++ ++static void cnic_stop_hw(struct cnic_dev *dev) ++{ ++ if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) { ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ clear_bit(CNIC_F_CNIC_UP, &dev->flags); ++ rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL); ++#ifndef __VMKLNX__ ++ synchronize_rcu(); ++#endif ++ cnic_cm_shutdown(dev); ++ cp->stop_hw(dev); ++ pci_dev_put(dev->pcidev); ++#ifndef __VMKLNX__ ++ module_put(cp->ethdev->drv_owner); ++#endif ++ } ++} ++ ++static struct cnic_dev *alloc_cnic(struct net_device *dev) ++{ ++ struct cnic_dev *cdev; ++ struct cnic_local *cp; ++ int alloc_size; ++ ++ alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local); ++ ++ cdev = kmalloc(alloc_size , GFP_KERNEL); ++ if (cdev == NULL) { ++ printk(KERN_ERR PFX "%s: allocate dev struct failure\n", ++ dev->name); ++ return NULL; ++ } ++ memset(cdev, 0, alloc_size); ++ ++ cdev->netdev = dev; ++ cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev); ++ cdev->register_device = cnic_register_device; ++ cdev->unregister_device = cnic_unregister_device; ++ cp = cdev->cnic_priv; ++ cp->dev = cdev; ++ ++ spin_lock_init(&cp->cnic_ulp_lock); ++ printk(KERN_INFO PFX "Added CNIC device: %s\n", dev->name); ++ ++ return cdev; ++} ++ ++static struct cnic_dev *init_bnx2_cnic(struct net_device *dev) ++{ ++ struct pci_dev *pdev; ++ struct cnic_dev *cdev; ++ struct cnic_local *cp; ++ struct cnic_eth_dev *ethdev = NULL; ++#ifdef __VMKLNX__ ++ vmk_IscsiNetDriverData iscsinet_drv_data; ++ struct cnic_eth_dev *(*bnx2_cnic_probe)(struct net_device *); ++ VMK_ReturnStatus vm_err; ++ ++ vm_err = vmk_IscsiNetDriverRegistered(vmk_ModuleGetID("bnx2"), &iscsinet_drv_data); ++ if (vm_err != VMK_OK) ++ return NULL; ++ ++ bnx2_cnic_probe = iscsinet_drv_data.drvData; ++ ++ if (!bnx2_cnic_probe) ++ return NULL; ++ ++ ethdev = bnx2_cnic_probe(dev); ++#else ++ struct cnic_eth_dev *(*probe)(void *) = NULL; ++ ++ probe = __symbol_get("bnx2_cnic_probe"); ++ if (probe) { ++ ethdev = (*probe)(dev); ++#if (LINUX_VERSION_CODE > 0x020610) ++ symbol_put_addr(probe); ++#else ++ __symbol_put("bnx2_cnic_probe"); ++#endif ++ } ++#endif ++ if (!ethdev) ++ return NULL; ++ ++ pdev = ethdev->pdev; ++ if (!pdev) ++ return NULL; ++ ++ dev_hold(dev); ++ pci_dev_get(pdev); ++ if (pdev->device == PCI_DEVICE_ID_NX2_5709 || ++ pdev->device == PCI_DEVICE_ID_NX2_5709S) { ++ u8 rev; ++ ++ pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); ++ if (rev < 0x10) { ++ pci_dev_put(pdev); ++ goto cnic_err; ++ } ++ } ++ pci_dev_put(pdev); ++ ++ cdev = alloc_cnic(dev); ++ if (cdev == NULL) ++ goto cnic_err; ++ ++ set_bit(CNIC_F_BNX2_CLASS, &cdev->flags); ++ cdev->submit_kwqes = cnic_submit_bnx2_kwqes; ++ ++ cp = cdev->cnic_priv; ++ cp->ethdev = ethdev; ++ cdev->pcidev = pdev; ++ ++ cp->cnic_ops = &cnic_bnx2_ops; ++ cp->start_hw = cnic_start_bnx2_hw; ++ cp->stop_hw = cnic_stop_bnx2_hw; ++ cp->setup_pgtbl = cnic_setup_page_tbl; ++ cp->alloc_resc = cnic_alloc_bnx2_resc; ++ cp->free_resc = cnic_free_resc; ++ cp->start_cm = cnic_cm_init_bnx2_hw; ++ cp->stop_cm = cnic_cm_stop_bnx2_hw; ++ cp->enable_int = cnic_enable_bnx2_int; ++ cp->disable_int_sync = cnic_disable_bnx2_int_sync; ++ cp->close_conn = cnic_close_bnx2_conn; ++ cp->next_idx = cnic_bnx2_next_idx; ++ cp->hw_idx = cnic_bnx2_hw_idx; ++ return cdev; ++ ++cnic_err: ++ dev_put(dev); ++ return NULL; ++} ++ ++static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev) ++{ ++ struct pci_dev *pdev; ++ struct cnic_dev *cdev; ++ struct cnic_local *cp; ++ struct cnic_eth_dev *ethdev = NULL; ++#ifdef __VMKLNX__ ++ vmk_IscsiNetDriverData iscsinet_drv_data; ++ struct cnic_eth_dev *(*bnx2x_cnic_probe)(struct net_device *); ++ VMK_ReturnStatus vm_err; ++ ++ vm_err = vmk_IscsiNetDriverRegistered(vmk_ModuleGetID("bnx2x"), &iscsinet_drv_data); ++ if (vm_err != VMK_OK) ++ return NULL; ++ ++ bnx2x_cnic_probe = iscsinet_drv_data.drvData; ++ ++ if (!bnx2x_cnic_probe) ++ return NULL; ++ ++ ethdev = bnx2x_cnic_probe(dev); ++#else ++ struct cnic_eth_dev *(*probe)(void *) = NULL; ++ ++ probe = __symbol_get("bnx2x_cnic_probe"); ++ if (probe) { ++ ethdev = (*probe)(dev); ++#if (LINUX_VERSION_CODE > 0x020610) ++ symbol_put_addr(probe); ++#else ++ __symbol_put("bnx2x_cnic_probe"); ++#endif ++ } ++#endif ++ if (!ethdev) ++ return NULL; ++ ++ pdev = ethdev->pdev; ++ if (!pdev) ++ return NULL; ++ ++ dev_hold(dev); ++ cdev = alloc_cnic(dev); ++ if (cdev == NULL) { ++ dev_put(dev); ++ return NULL; ++ } ++ ++ set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags); ++ cdev->submit_kwqes = cnic_submit_bnx2x_kwqes; ++ ++ cp = cdev->cnic_priv; ++ cp->ethdev = ethdev; ++ cdev->pcidev = pdev; ++ ++ cp->cnic_ops = &cnic_bnx2x_ops; ++ cp->start_hw = cnic_start_bnx2x_hw; ++ cp->stop_hw = cnic_stop_bnx2x_hw; ++ cp->setup_pgtbl = cnic_setup_page_tbl_le; ++ cp->alloc_resc = cnic_alloc_bnx2x_resc; ++ cp->free_resc = cnic_free_resc; ++ cp->start_cm = cnic_cm_init_bnx2x_hw; ++ cp->stop_cm = cnic_cm_stop_bnx2x_hw; ++ cp->enable_int = cnic_enable_bnx2x_int; ++ cp->disable_int_sync = cnic_disable_bnx2x_int_sync; ++ cp->ack_int = cnic_ack_bnx2x_msix; ++ cp->close_conn = cnic_close_bnx2x_conn; ++ cp->next_idx = cnic_bnx2x_next_idx; ++ cp->hw_idx = cnic_bnx2x_hw_idx; ++ return cdev; ++} ++ ++static struct cnic_dev *is_cnic_dev(struct net_device *dev) ++{ ++ struct ethtool_drvinfo drvinfo; ++ struct cnic_dev *cdev = NULL; ++ ++ if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) { ++ memset(&drvinfo, 0, sizeof(drvinfo)); ++ dev->ethtool_ops->get_drvinfo(dev, &drvinfo); ++ ++ if (!strcmp(drvinfo.driver, "bnx2")) ++ cdev = init_bnx2_cnic(dev); ++ if (!strcmp(drvinfo.driver, "bnx2x")) ++ cdev = init_bnx2x_cnic(dev); ++ if (cdev) { ++#ifndef __VMKLNX__ ++ write_lock(&cnic_dev_lock); ++#endif ++ list_add(&cdev->list, &cnic_dev_list); ++#ifndef __VMKLNX__ ++ write_unlock(&cnic_dev_lock); ++#endif ++ } ++ } ++ return cdev; ++} ++ ++/** ++ * IP event handler ++ */ ++#ifndef __VMKLNX__ ++static int cnic_ip_event(struct notifier_block *this, unsigned long event, ++ void *ptr) ++{ ++ struct in_ifaddr *ifa = (struct in_ifaddr *) ptr; ++ struct net_device *netdev = (struct net_device *) ifa->ifa_dev->dev; ++ struct cnic_dev *dev; ++ int if_type; ++ u32 my_dev = 0; ++ ++ read_lock(&cnic_dev_lock); ++ list_for_each_entry(dev, &cnic_dev_list, list) { ++ if (netdev == dev->netdev) { ++ my_dev = 1; ++ cnic_hold(dev); ++ break; ++ } ++ } ++ read_unlock(&cnic_dev_lock); ++ ++ if (my_dev) { ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ rcu_read_lock(); ++ for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) { ++ struct cnic_ulp_ops *ulp_ops; ++ ++ ulp_ops = rcu_dereference(cp->ulp_ops[if_type]); ++ if (ulp_ops) { ++ void *ctx = cp->ulp_handle[if_type]; ++ ++ ulp_ops->indicate_inetevent(ctx, event); ++ } ++ } ++ rcu_read_unlock(); ++ ++ cnic_put(dev); ++ } ++ ++ return NOTIFY_DONE; ++} ++ ++/** ++ * netdev event handler ++ */ ++static int cnic_netdev_event(struct notifier_block *this, unsigned long event, ++ void *ptr) ++{ ++ struct net_device *netdev = ptr; ++ struct cnic_dev *dev; ++ int if_type; ++ int my_dev = 0, new_dev = 0; ++ ++ read_lock(&cnic_dev_lock); ++ list_for_each_entry(dev, &cnic_dev_list, list) { ++ if (netdev == dev->netdev) { ++ my_dev = 1; ++ cnic_hold(dev); ++ break; ++ } ++ } ++ read_unlock(&cnic_dev_lock); ++ ++ if (!my_dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) { ++ /* Check for the hot-plug device */ ++ dev = is_cnic_dev(netdev); ++ if (dev) { ++ my_dev = 1; ++ new_dev = 1; ++ cnic_hold(dev); ++ } ++ } ++ if (my_dev) { ++ struct cnic_local *cp = dev->cnic_priv; ++ ++ if (new_dev) ++ cnic_ulp_init(dev); ++ if (event == NETDEV_UNREGISTER) ++ cnic_ulp_exit(dev); ++ else if (event == NETDEV_UP) { ++ mutex_lock(&cnic_lock); ++ set_bit(CNIC_F_IF_UP, &dev->flags); ++ if (dev->use_count) { ++ if (!cnic_start_hw(dev)) ++ cnic_ulp_start(dev); ++ } ++ mutex_unlock(&cnic_lock); ++ } ++ ++ rcu_read_lock(); ++ for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) { ++ struct cnic_ulp_ops *ulp_ops; ++ void *ctx; ++ ++ ulp_ops = rcu_dereference(cp->ulp_ops[if_type]); ++ if (!ulp_ops) ++ continue; ++ ++ ctx = cp->ulp_handle[if_type]; ++ ++ ulp_ops->indicate_netevent(ctx, event); ++ } ++ rcu_read_unlock(); ++ ++ if (event == NETDEV_GOING_DOWN) { ++ mutex_lock(&cnic_lock); ++ clear_bit(CNIC_F_IF_UP, &dev->flags); ++ set_bit(CNIC_F_IF_GOING_DOWN, &dev->flags); ++ cnic_ulp_stop(dev); ++ cnic_stop_hw(dev); ++ mutex_unlock(&cnic_lock); ++ } else if (event == NETDEV_DOWN) { ++ mutex_lock(&cnic_lock); ++ clear_bit(CNIC_F_IF_GOING_DOWN, &dev->flags); ++ mutex_unlock(&cnic_lock); ++ } else if (event == NETDEV_UNREGISTER) { ++ write_lock(&cnic_dev_lock); ++ list_del_init(&dev->list); ++ write_unlock(&cnic_dev_lock); ++ ++ cnic_put(dev); ++ cnic_free_dev(dev); ++ goto done; ++ } ++ cnic_put(dev); ++ } ++done: ++ return NOTIFY_DONE; ++} ++ ++static struct notifier_block cnic_ip_notifier = { ++ cnic_ip_event, ++ 0 ++}; ++ ++static struct notifier_block cnic_netdev_notifier = { ++ cnic_netdev_event, ++ 0 ++}; ++#endif ++ ++static void cnic_release(void) ++{ ++ struct cnic_dev *dev; ++ ++ while (!list_empty(&cnic_dev_list)) { ++ dev = list_entry(cnic_dev_list.next, struct cnic_dev, list); ++ if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) ++ cnic_stop_hw(dev); ++ ++ list_del_init(&dev->list); ++ cnic_free_dev(dev); ++ } ++} ++ ++static int __init cnic_init(void) ++{ ++ int rc = 0; ++#ifdef __VMKLNX__ ++ struct net_device *dev; ++#endif ++ ++ printk(KERN_INFO "%s", version); ++ ++#ifdef __VMKLNX__ ++ /* Find Teton devices */ ++#if (LINUX_VERSION_CODE >= 0x020618) ++ for_each_netdev(&init_net, dev) ++#elif (LINUX_VERSION_CODE >= 0x20616) ++ for_each_netdev(dev) ++#else ++ for (dev = dev_base; dev; dev = dev->next) ++#endif ++ is_cnic_dev(dev); ++ ++#else ++ ++ rc = register_inetaddr_notifier(&cnic_ip_notifier); ++ if (rc) ++ cnic_release(); ++ rc = register_netdevice_notifier(&cnic_netdev_notifier); ++ if (rc) { ++ unregister_inetaddr_notifier(&cnic_ip_notifier); ++ cnic_release(); ++ } ++#endif ++ return rc; ++} ++ ++static void __exit cnic_exit(void) ++{ ++#ifndef __VMKLNX__ ++ unregister_inetaddr_notifier(&cnic_ip_notifier); ++ unregister_netdevice_notifier(&cnic_netdev_notifier); ++#endif ++ cnic_release(); ++ return; ++} ++ ++module_init(cnic_init); ++module_exit(cnic_exit); +diff -r 5f108bc568be drivers/net/cnic.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cnic.h Tue Sep 01 13:50:09 2009 +0100 +@@ -0,0 +1,418 @@ ++/* cnic.h: Broadcom CNIC core network driver. ++ * ++ * Copyright (c) 2006 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ * ++ * Written by: John(Zongxi) Chen (zongxic@broadcom.com) ++ */ ++ ++ ++#ifndef CNIC_H ++#define CNIC_H ++ ++#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) ++ #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." ++#endif ++ ++#ifndef DIV_ROUND_UP ++#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) ++#endif ++ ++#ifndef ISCSI_DEF_FIRST_BURST_LEN ++#define ISCSI_DEF_FIRST_BURST_LEN 65536 ++#endif ++ ++#ifndef ISCSI_DEF_MAX_RECV_SEG_LEN ++#define ISCSI_DEF_MAX_RECV_SEG_LEN 8192 ++#endif ++ ++#ifndef ISCSI_DEF_MAX_BURST_LEN ++#define ISCSI_DEF_MAX_BURST_LEN 262144 ++#endif ++ ++#define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1) ++ ++#define KWQ_PAGE_CNT 4 ++#define KCQ_PAGE_CNT 16 ++ ++#define KWQ_CID 24 ++#define KCQ_CID 25 ++ ++/* ++ * krnlq_context definition ++ */ ++#define L5_KRNLQ_FLAGS 0x00000000 ++#define L5_KRNLQ_SIZE 0x00000000 ++#define L5_KRNLQ_TYPE 0x00000000 ++#define KRNLQ_FLAGS_PG_SZ (0xf<<0) ++#define KRNLQ_FLAGS_PG_SZ_256 (0<<0) ++#define KRNLQ_FLAGS_PG_SZ_512 (1<<0) ++#define KRNLQ_FLAGS_PG_SZ_1K (2<<0) ++#define KRNLQ_FLAGS_PG_SZ_2K (3<<0) ++#define KRNLQ_FLAGS_PG_SZ_4K (4<<0) ++#define KRNLQ_FLAGS_PG_SZ_8K (5<<0) ++#define KRNLQ_FLAGS_PG_SZ_16K (6<<0) ++#define KRNLQ_FLAGS_PG_SZ_32K (7<<0) ++#define KRNLQ_FLAGS_PG_SZ_64K (8<<0) ++#define KRNLQ_FLAGS_PG_SZ_128K (9<<0) ++#define KRNLQ_FLAGS_PG_SZ_256K (10<<0) ++#define KRNLQ_FLAGS_PG_SZ_512K (11<<0) ++#define KRNLQ_FLAGS_PG_SZ_1M (12<<0) ++#define KRNLQ_FLAGS_PG_SZ_2M (13<<0) ++#define KRNLQ_FLAGS_QE_SELF_SEQ (1<<15) ++#define KRNLQ_SIZE_TYPE_SIZE ((((0x28 + 0x1f) & ~0x1f) / 0x20) << 16) ++#define KRNLQ_TYPE_TYPE (0xf<<28) ++#define KRNLQ_TYPE_TYPE_EMPTY (0<<28) ++#define KRNLQ_TYPE_TYPE_KRNLQ (6<<28) ++ ++#define L5_KRNLQ_HOST_QIDX 0x00000004 ++#define L5_KRNLQ_HOST_FW_QIDX 0x00000008 ++#define L5_KRNLQ_NX_QE_SELF_SEQ 0x0000000c ++#define L5_KRNLQ_QE_SELF_SEQ_MAX 0x0000000c ++#define L5_KRNLQ_NX_QE_HADDR_HI 0x00000010 ++#define L5_KRNLQ_NX_QE_HADDR_LO 0x00000014 ++#define L5_KRNLQ_PGTBL_PGIDX 0x00000018 ++#define L5_KRNLQ_NX_PG_QIDX 0x00000018 ++#define L5_KRNLQ_PGTBL_NPAGES 0x0000001c ++#define L5_KRNLQ_QIDX_INCR 0x0000001c ++#define L5_KRNLQ_PGTBL_HADDR_HI 0x00000020 ++#define L5_KRNLQ_PGTBL_HADDR_LO 0x00000024 ++ ++#define BNX2_PG_CTX_MAP 0x1a0034 ++#define BNX2_ISCSI_CTX_MAP 0x1a0074 ++ ++struct cnic_redirect_entry { ++ struct dst_entry *old_dst; ++ struct dst_entry *new_dst; ++}; ++ ++struct cnic_work_node { ++ u32 work_type; ++#define WORK_TYPE_KCQE 1 ++#define WORK_TYPE_NEIGH_UPDATE 2 ++#define WORK_TYPE_REDIRECT 3 ++ union { ++ struct kcqe kcqe; ++ struct neighbour *neigh; ++ struct cnic_redirect_entry cnic_redir; ++ } work_data; ++}; ++ ++#define MAX_CNIC_L5_CONTEXT 256 ++ ++#define WORK_RING_SIZE 256 ++#define WORK_RING_SIZE_MASK 255 ++#define MAX_CM_SK_TBL_SZ MAX_CNIC_L5_CONTEXT ++#define MAX_COMPLETED_KCQE 64 ++ ++#define MAX_ISCSI_TBL_SZ 256 ++ ++#define KWQE_CNT (BCM_PAGE_SIZE / sizeof(struct kwqe)) ++#define KCQE_CNT (BCM_PAGE_SIZE / sizeof(struct kcqe)) ++#define MAX_KWQE_CNT (KWQE_CNT - 1) ++#define MAX_KCQE_CNT (KCQE_CNT - 1) ++ ++#define MAX_KWQ_IDX ((KWQ_PAGE_CNT * KWQE_CNT) - 1) ++#define MAX_KCQ_IDX ((KCQ_PAGE_CNT * KCQE_CNT) - 1) ++ ++#define KWQ_PG(x) (((x) & ~MAX_KWQE_CNT) >> (BCM_PAGE_BITS - 5)) ++#define KWQ_IDX(x) ((x) & MAX_KWQE_CNT) ++ ++#define KCQ_PG(x) (((x) & ~MAX_KCQE_CNT) >> (BCM_PAGE_BITS - 5)) ++#define KCQ_IDX(x) ((x) & MAX_KCQE_CNT) ++ ++#define BNX2X_NEXT_KCQE(x) (((x) & (MAX_KCQE_CNT - 1)) == \ ++ (MAX_KCQE_CNT - 1)) ? \ ++ (x) + 2 : (x) + 1 ++ ++#define BNX2X_KWQ_DATA_PG(cp, x) ((x) / (cp)->kwq_16_data_pp) ++#define BNX2X_KWQ_DATA_IDX(cp, x) ((x) % (cp)->kwq_16_data_pp) ++#define BNX2X_KWQ_DATA(cp, x) \ ++ &(cp)->kwq_16_data[BNX2X_KWQ_DATA_PG(cp, x)][BNX2X_KWQ_DATA_IDX(cp, x)] ++ ++#define DEF_IPID_COUNT 0xc001 ++ ++#define DEF_KA_TIMEOUT 10000 ++#define DEF_KA_INTERVAL 300000 ++#define DEF_KA_MAX_PROBE_COUNT 3 ++#define DEF_TOS 0 ++#define DEF_TTL 0xfe ++#define DEF_SND_SEQ_SCALE 0 ++#define DEF_RCV_BUF 0xffff ++#define DEF_SND_BUF 0xffff ++#define DEF_SEED 0 ++#define DEF_MAX_RT_TIME 500 ++#define DEF_MAX_DA_COUNT 2 ++#define DEF_SWS_TIMER 1000 ++#define DEF_MAX_CWND 0xffff ++ ++struct cnic_ctx { ++ u32 cid; ++ void *ctx; ++ dma_addr_t mapping; ++}; ++ ++#define BNX2_MAX_CID 0x2000 ++ ++struct cnic_dma { ++ int num_pages; ++ void **pg_arr; ++ dma_addr_t *pg_map_arr; ++ int pgtbl_size; ++ u32 *pgtbl; ++ dma_addr_t pgtbl_map; ++}; ++ ++struct cnic_id_tbl { ++ spinlock_t lock; ++ u32 start; ++ u32 max; ++ u32 next; ++ unsigned long *table; ++}; ++ ++#define CNIC_KWQ16_DATA_SIZE 128 ++ ++struct kwqe_16_data { ++ u8 data[CNIC_KWQ16_DATA_SIZE]; ++}; ++ ++struct cnic_iscsi { ++ struct cnic_dma task_array_info; ++ struct cnic_dma r2tq_info; ++ struct cnic_dma hq_info; ++}; ++ ++struct cnic_context { ++ u32 cid; ++ struct kwqe_16_data *kwqe_data; ++ dma_addr_t kwqe_data_mapping; ++ wait_queue_head_t waitq; ++ int wait_cond; ++ unsigned long timestamp; ++ u32 ctx_flags; ++#define CTX_FL_OFFLD_START 0x00000001 ++ u8 ulp_proto_id; ++ union { ++ struct cnic_iscsi *iscsi; ++ } proto; ++}; ++ ++struct l5cm_spe; ++ ++struct cnic_local { ++ ++ spinlock_t cnic_ulp_lock; ++ void *ulp_handle[MAX_CNIC_ULP_TYPE]; ++ unsigned long ulp_flags[MAX_CNIC_ULP_TYPE]; ++#define ULP_F_INIT 0 ++#define ULP_F_START 1 ++ struct cnic_ulp_ops *ulp_ops[MAX_CNIC_ULP_TYPE]; ++ ++ /* protected by ulp_lock */ ++ u32 cnic_local_flags; ++#define CNIC_LCL_FL_KWQ_INIT 0x00000001 ++ ++ struct cnic_dev *dev; ++ ++ struct cnic_eth_dev *ethdev; ++ ++ u32 kwq_cid_addr; ++ u32 kcq_cid_addr; ++ ++ struct cnic_dma kwq_info; ++ struct kwqe **kwq; ++ ++ struct cnic_dma kwq_16_data_info; ++ ++ u16 max_kwq_idx; ++ ++ u16 kwq_prod_idx; ++ u32 kwq_io_addr; ++ ++ volatile u16 *kwq_con_idx_ptr; ++ u16 kwq_con_idx; ++ ++ struct cnic_dma kcq_info; ++ struct kcqe **kcq; ++ ++ u16 kcq_prod_idx; ++ u32 kcq_io_addr; ++ ++ void *status_blk; ++ struct status_block_msix *bnx2_status_blk; ++ struct host_status_block *bnx2x_status_blk; ++ ++ u32 status_blk_num; ++ u32 int_num; ++ u32 last_status_idx; ++ struct tasklet_struct cnic_irq_task; ++ ++ struct kcqe *completed_kcq[MAX_COMPLETED_KCQE]; ++ ++ struct cnic_sock *csk_tbl; ++ struct cnic_id_tbl csk_port_tbl; ++ u32 next_tcp_port; ++ ++ struct cnic_dma conn_buf_info; ++ struct cnic_dma gbl_buf_info; ++ ++ struct cnic_iscsi *iscsi_tbl; ++ struct cnic_context *ctx_tbl; ++ struct cnic_id_tbl cid_tbl; ++ atomic_t iscsi_conn; ++ ++ /* per connection parameters */ ++ int num_iscsi_tasks; ++ int num_ccells; ++ int task_array_size; ++ int r2tq_size; ++ int hq_size; ++ int num_cqs; ++ ++ struct notifier_block cm_nb; ++ ++ struct cnic_work_node cnic_work_ring[WORK_RING_SIZE]; ++ int cnic_wr_cons; ++ int cnic_wr_prod; ++ spinlock_t wr_lock; ++ ++ struct tasklet_struct cnic_task; ++ ++#ifndef HAVE_NETEVENT ++ struct timer_list cnic_timer; ++ u32 cnic_timer_off; ++#endif ++ struct cnic_ctx *ctx_arr; ++ int ctx_blks; ++ int ctx_blk_size; ++ unsigned long ctx_align; ++ int cids_per_blk; ++ ++ u32 chip_id; ++ int func; ++#ifdef __VMKLNX__ ++ uint8_t vmknic[VMK_VMKNIC_NAME_MAX]; ++ vmk_IscsiNetHandle iscsiNetHandle; ++ ++ /* For TCP port alloc/free. */ ++ uint8_t first_vmknic[VMK_VMKNIC_NAME_MAX]; ++ vmk_IscsiNetHandle first_iscsiNetHandle; ++ ++ vmk_uint32 cnic_local_port_min; ++ vmk_uint32 cnic_local_port_nr; ++#endif ++ ++ struct cnic_ops *cnic_ops; ++ int (*start_hw)(struct cnic_dev *); ++ void (*stop_hw)(struct cnic_dev *); ++ void (*setup_pgtbl)(struct cnic_dev *, ++ struct cnic_dma *); ++ int (*alloc_resc)(struct cnic_dev *); ++ void (*free_resc)(struct cnic_dev *); ++ int (*start_cm)(struct cnic_dev *); ++ void (*stop_cm)(struct cnic_dev *); ++ void (*enable_int)(struct cnic_dev *); ++ void (*disable_int_sync)(struct cnic_dev *); ++ void (*ack_int)(struct cnic_dev *); ++ void (*close_conn)(struct cnic_sock *, u32 opcode); ++ u16 (*next_idx)(u16); ++ u16 (*hw_idx)(u16); ++}; ++ ++struct bnx2x_bd_chain_next { ++ u32 addr_lo; ++ u32 addr_hi; ++ u8 reserved[8]; ++}; ++ ++#define ISCSI_RAMROD_CMD_ID_UPDATE_CONN (ISCSI_KCQE_OPCODE_UPDATE_CONN) ++#define ISCSI_RAMROD_CMD_ID_INIT (ISCSI_KCQE_OPCODE_INIT) ++ ++#define CDU_REGION_NUMBER_XCM_AG 2 ++#define CDU_REGION_NUMBER_UCM_AG 4 ++ ++#ifndef NEW_BNX2X_HSI ++static u8 calc_crc8( u32 data, u8 crc) ++{ ++ u8 D[32]; ++ u8 NewCRC[8]; ++ u8 C[8]; ++ u8 crc_res; ++ u8 i; ++ ++ /* split the data into 31 bits */ ++ for (i = 0; i < 32; i++) { ++ D[i] = (u8)(data & 1); ++ data = data >> 1; ++ } ++ ++ /* split the crc into 8 bits */ ++ for (i = 0; i < 8; i++ ) { ++ C[i] = crc & 1; ++ crc = crc >> 1; ++ } ++ ++ NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ C[6] ^ C[7]; ++ NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^ D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6]; ++ NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^ D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[0] ^ C[1] ^ C[4] ^ C[5]; ++ NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ C[1] ^ C[2] ^ C[5] ^ C[6]; ++ NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^ D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; ++ NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^ D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ C[3] ^ C[4] ^ C[7]; ++ NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^ D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ C[5]; ++ NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^ D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ C[6]; ++ ++ crc_res = 0; ++ for (i = 0; i < 8; i++) { ++ crc_res |= (NewCRC[i] << i); ++ } ++ ++ return crc_res; ++} ++#endif ++ ++#define CDU_VALID_DATA(_cid, _region, _type) \ ++ (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf))) ++ ++#define CDU_CRC8(_cid, _region, _type) \ ++ (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)) ++ ++#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \ ++ (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f)) ++ ++#define BNX2X_ISCSI_NUM_CONNECTIONS 128 ++#define BNX2X_ISCSI_TASK_CONTEXT_SIZE 128 ++#define BNX2X_ISCSI_CONTEXT_MEM_SIZE 1024 ++#define BNX2X_ISCSI_MAX_PENDING_R2TS 4 ++#define BNX2X_ISCSI_R2TQE_SIZE 8 ++#define BNX2X_ISCSI_HQ_BD_SIZE 64 ++#define BNX2X_ISCSI_CONN_BUF_SIZE 64 ++#define BNX2X_ISCSI_GLB_BUF_SIZE 64 ++#define BNX2X_ISCSI_PBL_NOT_CACHED 0xff ++#define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED 0xff ++#define BNX2X_HW_CID(x, func) ((x) | (((func) % PORT_MAX) << 23) | \ ++ (((func) >> 1) << 17)) ++#define BNX2X_SW_CID(x) (x & 0x1ffff) ++#define BNX2X_CHIP_NUM_57711 0x164f ++#define BNX2X_CHIP_NUM_57711E 0x1650 ++#define BNX2X_CHIP_NUM(x) (x >> 16) ++#define BNX2X_CHIP_IS_57711(x) \ ++ (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57711) ++#define BNX2X_CHIP_IS_57711E(x) \ ++ (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57711E) ++#define BNX2X_CHIP_IS_E1H(x) \ ++ (BNX2X_CHIP_IS_57711(x) || BNX2X_CHIP_IS_57711E(x)) ++#define IS_E1H_OFFSET BNX2X_CHIP_IS_E1H(cp->chip_id) ++ ++#define BNX2X_SHMEM_ADDR(base, field) (base + \ ++ offsetof(struct shmem_region, field)) ++ ++#define CNIC_PORT(cp) ((cp)->func % PORT_MAX) ++#define CNIC_FUNC(cp) ((cp)->func) ++#define CNIC_E1HVN(cp) ((cp)->func >> 1) ++ ++#endif ++ +diff -r 5f108bc568be drivers/net/cnic_cm.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cnic_cm.h Tue Sep 01 13:50:09 2009 +0100 +@@ -0,0 +1,552 @@ ++#ifndef __57XX_L5CM_HSI_LINUX_LE__ ++#define __57XX_L5CM_HSI_LINUX_LE__ ++ ++/* KWQ (kernel work queue) request op codes */ ++#define L4_KWQE_OPCODE_VALUE_CONNECT1 (50) ++#define L4_KWQE_OPCODE_VALUE_CONNECT2 (51) ++#define L4_KWQE_OPCODE_VALUE_CONNECT3 (52) ++#define L4_KWQE_OPCODE_VALUE_RESET (53) ++#define L4_KWQE_OPCODE_VALUE_CLOSE (54) ++#define L4_KWQE_OPCODE_VALUE_UPDATE_SECRET (60) ++#define L4_KWQE_OPCODE_VALUE_INIT_ULP (61) ++ ++#define L4_KWQE_OPCODE_VALUE_OFFLOAD_PG (1) ++#define L4_KWQE_OPCODE_VALUE_UPDATE_PG (9) ++#define L4_KWQE_OPCODE_VALUE_UPLOAD_PG (14) ++ ++/* KCQ (kernel completion queue) response op codes */ ++#define L4_KCQE_OPCODE_VALUE_CLOSE_COMP (53) ++#define L4_KCQE_OPCODE_VALUE_RESET_COMP (54) ++#define L4_KCQE_OPCODE_VALUE_FW_TCP_UPDATE (55) ++#define L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE (56) ++#define L4_KCQE_OPCODE_VALUE_RESET_RECEIVED (57) ++#define L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED (58) ++#define L4_KCQE_OPCODE_VALUE_INIT_ULP (61) ++ ++#define L4_KCQE_OPCODE_VALUE_OFFLOAD_PG (1) ++#define L4_KCQE_OPCODE_VALUE_UPLOAD_PG (14) ++ ++/* KCQ (kernel completion queue) completion status */ ++#define L4_KCQE_COMPLETION_STATUS_SUCCESS (0) ++#define L4_KCQE_COMPLETION_STATUS_TIMEOUT (0x93) ++ ++#define L4_LAYER_CODE (4) ++ ++/* ++ * L4 KCQ CQE ++ */ ++struct l4_kcq { ++ u32 cid; ++ u32 pg_cid; ++ u32 conn_id; ++ u32 pg_host_opaque; ++#if defined(__BIG_ENDIAN) ++ u16 status; ++ u16 reserved1; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved1; ++ u16 status; ++#endif ++ u32 reserved2[2]; ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KCQ_RESERVED3 (0xF<<0) ++#define L4_KCQ_RESERVED3_SHIFT 0 ++#define L4_KCQ_LAYER_CODE (0x7<<4) ++#define L4_KCQ_LAYER_CODE_SHIFT 4 ++#define L4_KCQ_RESERVED4 (0x1<<7) ++#define L4_KCQ_RESERVED4_SHIFT 7 ++ u8 op_code; ++ u16 qe_self_seq; ++#elif defined(__LITTLE_ENDIAN) ++ u16 qe_self_seq; ++ u8 op_code; ++ u8 flags; ++#define L4_KCQ_RESERVED3 (0xF<<0) ++#define L4_KCQ_RESERVED3_SHIFT 0 ++#define L4_KCQ_LAYER_CODE (0x7<<4) ++#define L4_KCQ_LAYER_CODE_SHIFT 4 ++#define L4_KCQ_RESERVED4 (0x1<<7) ++#define L4_KCQ_RESERVED4_SHIFT 7 ++#endif ++}; ++ ++ ++/* ++ * L4 KCQ CQE PG upload ++ */ ++struct l4_kcq_upload_pg { ++ u32 pg_cid; ++#if defined(__BIG_ENDIAN) ++ u16 pg_status; ++ u16 pg_ipid_count; ++#elif defined(__LITTLE_ENDIAN) ++ u16 pg_ipid_count; ++ u16 pg_status; ++#endif ++ u32 reserved1[5]; ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0) ++#define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0 ++#define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4) ++#define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4 ++#define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7) ++#define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7 ++ u8 op_code; ++ u16 qe_self_seq; ++#elif defined(__LITTLE_ENDIAN) ++ u16 qe_self_seq; ++ u8 op_code; ++ u8 flags; ++#define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0) ++#define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0 ++#define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4) ++#define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4 ++#define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7) ++#define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7 ++#endif ++}; ++ ++ ++/* ++ * Gracefully close the connection request ++ */ ++struct l4_kwq_close_req { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0) ++#define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0 ++#define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7 ++ u8 op_code; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 op_code; ++ u8 flags; ++#define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0) ++#define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0 ++#define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 cid; ++ u32 reserved2[6]; ++}; ++ ++ ++/* ++ * The first request to be passed in order to establish connection in option2 ++ */ ++struct l4_kwq_connect_req1 { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0) ++#define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7 ++ u8 op_code; ++ u8 reserved0; ++ u8 conn_flags; ++#define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0) ++#define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1) ++#define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1 ++#define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2) ++#define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2 ++#define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3) ++#define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3 ++#elif defined(__LITTLE_ENDIAN) ++ u8 conn_flags; ++#define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0) ++#define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1) ++#define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1 ++#define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2) ++#define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2 ++#define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3) ++#define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3 ++ u8 reserved0; ++ u8 op_code; ++ u8 flags; ++#define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0) ++#define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 cid; ++ u32 pg_cid; ++ u32 src_ip; ++ u32 dst_ip; ++#if defined(__BIG_ENDIAN) ++ u16 dst_port; ++ u16 src_port; ++#elif defined(__LITTLE_ENDIAN) ++ u16 src_port; ++ u16 dst_port; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 rsrv1[3]; ++ u8 tcp_flags; ++#define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0) ++#define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1) ++#define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1 ++#define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2) ++#define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2 ++#define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3) ++#define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3 ++#define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4) ++#define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5) ++#define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5 ++#define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) ++#define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6 ++#elif defined(__LITTLE_ENDIAN) ++ u8 tcp_flags; ++#define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0) ++#define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1) ++#define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1 ++#define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2) ++#define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2 ++#define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3) ++#define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3 ++#define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4) ++#define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5) ++#define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5 ++#define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) ++#define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6 ++ u8 rsrv1[3]; ++#endif ++ u32 rsrv2; ++}; ++ ++ ++/* ++ * The second ( optional )request to be passed in order to establish connection in option2 - for IPv6 only ++ */ ++struct l4_kwq_connect_req2 { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0) ++#define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7 ++ u8 op_code; ++ u8 reserved0; ++ u8 rsrv; ++#elif defined(__LITTLE_ENDIAN) ++ u8 rsrv; ++ u8 reserved0; ++ u8 op_code; ++ u8 flags; ++#define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0) ++#define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 reserved2; ++ u32 src_ip_v6_2; ++ u32 src_ip_v6_3; ++ u32 src_ip_v6_4; ++ u32 dst_ip_v6_2; ++ u32 dst_ip_v6_3; ++ u32 dst_ip_v6_4; ++}; ++ ++ ++/* ++ * The third ( and last )request to be passed in order to establish connection in option2 ++ */ ++struct l4_kwq_connect_req3 { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0) ++#define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7 ++ u8 op_code; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 op_code; ++ u8 flags; ++#define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0) ++#define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 ka_timeout; ++ u32 ka_interval ; ++#if defined(__BIG_ENDIAN) ++ u8 snd_seq_scale; ++ u8 ttl; ++ u8 tos; ++ u8 ka_max_probe_count; ++#elif defined(__LITTLE_ENDIAN) ++ u8 ka_max_probe_count; ++ u8 tos; ++ u8 ttl; ++ u8 snd_seq_scale; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 pmtu; ++ u16 mss; ++#elif defined(__LITTLE_ENDIAN) ++ u16 mss; ++ u16 pmtu; ++#endif ++ u32 rcv_buf; ++ u32 snd_buf; ++ u32 seed; ++}; ++ ++ ++/* ++ * a KWQE request to offload a PG connection ++ */ ++struct l4_kwq_offload_pg { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0) ++#define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0 ++#define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4) ++#define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7 ++ u8 op_code; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 op_code; ++ u8 flags; ++#define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0) ++#define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0 ++#define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4) ++#define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 l2hdr_nbytes; ++ u8 pg_flags; ++#define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0) ++#define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0 ++#define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1) ++#define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1 ++#define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2) ++#define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2 ++ u8 da0; ++ u8 da1; ++#elif defined(__LITTLE_ENDIAN) ++ u8 da1; ++ u8 da0; ++ u8 pg_flags; ++#define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0) ++#define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0 ++#define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1) ++#define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1 ++#define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2) ++#define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2 ++ u8 l2hdr_nbytes; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 da2; ++ u8 da3; ++ u8 da4; ++ u8 da5; ++#elif defined(__LITTLE_ENDIAN) ++ u8 da5; ++ u8 da4; ++ u8 da3; ++ u8 da2; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 sa0; ++ u8 sa1; ++ u8 sa2; ++ u8 sa3; ++#elif defined(__LITTLE_ENDIAN) ++ u8 sa3; ++ u8 sa2; ++ u8 sa1; ++ u8 sa0; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 sa4; ++ u8 sa5; ++ u16 etype; ++#elif defined(__LITTLE_ENDIAN) ++ u16 etype; ++ u8 sa5; ++ u8 sa4; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 vlan_tag; ++ u16 ipid_start; ++#elif defined(__LITTLE_ENDIAN) ++ u16 ipid_start; ++ u16 vlan_tag; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 ipid_count; ++ u16 reserved3; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved3; ++ u16 ipid_count; ++#endif ++ u32 host_opaque; ++}; ++ ++ ++/* ++ * Abortively close the connection request ++ */ ++struct l4_kwq_reset_req { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0) ++#define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0 ++#define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4) ++#define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7 ++ u8 op_code; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 op_code; ++ u8 flags; ++#define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0) ++#define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0 ++#define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4) ++#define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 cid; ++ u32 reserved2[6]; ++}; ++ ++ ++/* ++ * a KWQE request to update a PG connection ++ */ ++struct l4_kwq_update_pg { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0) ++#define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0 ++#define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4) ++#define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7 ++ u8 opcode; ++ u16 oper16; ++#elif defined(__LITTLE_ENDIAN) ++ u16 oper16; ++ u8 opcode; ++ u8 flags; ++#define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0) ++#define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0 ++#define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4) ++#define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 pg_cid; ++ u32 pg_host_opaque; ++#if defined(__BIG_ENDIAN) ++ u8 pg_valids; ++#define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0) ++#define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0 ++#define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1) ++#define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1 ++#define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2) ++#define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2 ++ u8 pg_unused_a; ++ u16 pg_ipid_count; ++#elif defined(__LITTLE_ENDIAN) ++ u16 pg_ipid_count; ++ u8 pg_unused_a; ++ u8 pg_valids; ++#define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0) ++#define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0 ++#define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1) ++#define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1 ++#define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2) ++#define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2 ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 reserverd3; ++ u8 da0; ++ u8 da1; ++#elif defined(__LITTLE_ENDIAN) ++ u8 da1; ++ u8 da0; ++ u16 reserverd3; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 da2; ++ u8 da3; ++ u8 da4; ++ u8 da5; ++#elif defined(__LITTLE_ENDIAN) ++ u8 da5; ++ u8 da4; ++ u8 da3; ++ u8 da2; ++#endif ++ u32 reserved4; ++ u32 reserved5; ++}; ++ ++ ++/* ++ * a KWQE request to upload a PG or L4 context ++ */ ++struct l4_kwq_upload { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0) ++#define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0 ++#define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4) ++#define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7 ++ u8 opcode; ++ u16 oper16; ++#elif defined(__LITTLE_ENDIAN) ++ u16 oper16; ++ u8 opcode; ++ u8 flags; ++#define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0) ++#define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0 ++#define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4) ++#define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 cid; ++ u32 reserved2[6]; ++}; ++ ++#endif /* __57XX_L5CM_HSI_LINUX_LE__ */ +diff -r 5f108bc568be drivers/net/cnic_defs.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cnic_defs.h Tue Sep 01 13:50:09 2009 +0100 +@@ -0,0 +1,570 @@ ++#ifndef __57XX_L5CM_HSI_LINUX_LE__ ++#define __57XX_L5CM_HSI_LINUX_LE__ ++ ++/* KWQ (kernel work queue) request op codes */ ++#define L2_KWQE_OPCODE_VALUE_FLUSH (4) ++ ++#define L4_KWQE_OPCODE_VALUE_CONNECT1 (50) ++#define L4_KWQE_OPCODE_VALUE_CONNECT2 (51) ++#define L4_KWQE_OPCODE_VALUE_CONNECT3 (52) ++#define L4_KWQE_OPCODE_VALUE_RESET (53) ++#define L4_KWQE_OPCODE_VALUE_CLOSE (54) ++#define L4_KWQE_OPCODE_VALUE_UPDATE_SECRET (60) ++#define L4_KWQE_OPCODE_VALUE_INIT_ULP (61) ++ ++#define L4_KWQE_OPCODE_VALUE_OFFLOAD_PG (1) ++#define L4_KWQE_OPCODE_VALUE_UPDATE_PG (9) ++#define L4_KWQE_OPCODE_VALUE_UPLOAD_PG (14) ++ ++#define L5CM_RAMROD_CMD_ID_BASE (0x80) ++#define L5CM_RAMROD_CMD_ID_TCP_CONNECT (L5CM_RAMROD_CMD_ID_BASE + 3) ++#define L5CM_RAMROD_CMD_ID_CLOSE (L5CM_RAMROD_CMD_ID_BASE + 12) ++#define L5CM_RAMROD_CMD_ID_ABORT (L5CM_RAMROD_CMD_ID_BASE + 13) ++#define L5CM_RAMROD_CMD_ID_SEARCHER_DELETE (L5CM_RAMROD_CMD_ID_BASE + 14) ++#define L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD (L5CM_RAMROD_CMD_ID_BASE + 15) ++ ++/* KCQ (kernel completion queue) response op codes */ ++#define L4_KCQE_OPCODE_VALUE_CLOSE_COMP (53) ++#define L4_KCQE_OPCODE_VALUE_RESET_COMP (54) ++#define L4_KCQE_OPCODE_VALUE_FW_TCP_UPDATE (55) ++#define L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE (56) ++#define L4_KCQE_OPCODE_VALUE_RESET_RECEIVED (57) ++#define L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED (58) ++#define L4_KCQE_OPCODE_VALUE_INIT_ULP (61) ++ ++#define L4_KCQE_OPCODE_VALUE_OFFLOAD_PG (1) ++#define L4_KCQE_OPCODE_VALUE_UPDATE_PG (9) ++#define L4_KCQE_OPCODE_VALUE_UPLOAD_PG (14) ++ ++/* KCQ (kernel completion queue) completion status */ ++#define L4_KCQE_COMPLETION_STATUS_SUCCESS (0) ++#define L4_KCQE_COMPLETION_STATUS_TIMEOUT (0x93) ++ ++#define L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL (0x83) ++#define L4_KCQE_COMPLETION_STATUS_OFFLOADED_PG (0x89) ++ ++#define L4_LAYER_CODE (4) ++#define L2_LAYER_CODE (2) ++ ++/* ++ * L4 KCQ CQE ++ */ ++struct l4_kcq { ++ u32 cid; ++ u32 pg_cid; ++ u32 conn_id; ++ u32 pg_host_opaque; ++#if defined(__BIG_ENDIAN) ++ u16 status; ++ u16 reserved1; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved1; ++ u16 status; ++#endif ++ u32 reserved2[2]; ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KCQ_RESERVED3 (0x7<<0) ++#define L4_KCQ_RESERVED3_SHIFT 0 ++#define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */ ++#define L4_KCQ_RAMROD_COMPLETION_SHIFT 3 ++#define L4_KCQ_LAYER_CODE (0x7<<4) ++#define L4_KCQ_LAYER_CODE_SHIFT 4 ++#define L4_KCQ_RESERVED4 (0x1<<7) ++#define L4_KCQ_RESERVED4_SHIFT 7 ++ u8 op_code; ++ u16 qe_self_seq; ++#elif defined(__LITTLE_ENDIAN) ++ u16 qe_self_seq; ++ u8 op_code; ++ u8 flags; ++#define L4_KCQ_RESERVED3 (0xF<<0) ++#define L4_KCQ_RESERVED3_SHIFT 0 ++#define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */ ++#define L4_KCQ_RAMROD_COMPLETION_SHIFT 3 ++#define L4_KCQ_LAYER_CODE (0x7<<4) ++#define L4_KCQ_LAYER_CODE_SHIFT 4 ++#define L4_KCQ_RESERVED4 (0x1<<7) ++#define L4_KCQ_RESERVED4_SHIFT 7 ++#endif ++}; ++ ++ ++/* ++ * L4 KCQ CQE PG upload ++ */ ++struct l4_kcq_upload_pg { ++ u32 pg_cid; ++#if defined(__BIG_ENDIAN) ++ u16 pg_status; ++ u16 pg_ipid_count; ++#elif defined(__LITTLE_ENDIAN) ++ u16 pg_ipid_count; ++ u16 pg_status; ++#endif ++ u32 reserved1[5]; ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0) ++#define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0 ++#define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4) ++#define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4 ++#define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7) ++#define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7 ++ u8 op_code; ++ u16 qe_self_seq; ++#elif defined(__LITTLE_ENDIAN) ++ u16 qe_self_seq; ++ u8 op_code; ++ u8 flags; ++#define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0) ++#define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0 ++#define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4) ++#define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4 ++#define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7) ++#define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7 ++#endif ++}; ++ ++ ++/* ++ * Gracefully close the connection request ++ */ ++struct l4_kwq_close_req { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0) ++#define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0 ++#define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7 ++ u8 op_code; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 op_code; ++ u8 flags; ++#define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0) ++#define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0 ++#define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 cid; ++ u32 reserved2[6]; ++}; ++ ++ ++/* ++ * The first request to be passed in order to establish connection in option2 ++ */ ++struct l4_kwq_connect_req1 { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0) ++#define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7 ++ u8 op_code; ++ u8 reserved0; ++ u8 conn_flags; ++#define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0) ++#define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1) ++#define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1 ++#define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2) ++#define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2 ++#define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3) ++#define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3 ++#elif defined(__LITTLE_ENDIAN) ++ u8 conn_flags; ++#define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0) ++#define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1) ++#define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1 ++#define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2) ++#define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2 ++#define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3) ++#define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3 ++ u8 reserved0; ++ u8 op_code; ++ u8 flags; ++#define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0) ++#define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 cid; ++ u32 pg_cid; ++ u32 src_ip; ++ u32 dst_ip; ++#if defined(__BIG_ENDIAN) ++ u16 dst_port; ++ u16 src_port; ++#elif defined(__LITTLE_ENDIAN) ++ u16 src_port; ++ u16 dst_port; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 rsrv1[3]; ++ u8 tcp_flags; ++#define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0) ++#define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1) ++#define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1 ++#define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2) ++#define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2 ++#define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3) ++#define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3 ++#define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4) ++#define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5) ++#define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5 ++#define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) ++#define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6 ++#elif defined(__LITTLE_ENDIAN) ++ u8 tcp_flags; ++#define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0) ++#define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1) ++#define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1 ++#define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2) ++#define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2 ++#define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3) ++#define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3 ++#define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4) ++#define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5) ++#define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5 ++#define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) ++#define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6 ++ u8 rsrv1[3]; ++#endif ++ u32 rsrv2; ++}; ++ ++ ++/* ++ * The second ( optional )request to be passed in order to establish connection in option2 - for IPv6 only ++ */ ++struct l4_kwq_connect_req2 { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0) ++#define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7 ++ u8 op_code; ++ u8 reserved0; ++ u8 rsrv; ++#elif defined(__LITTLE_ENDIAN) ++ u8 rsrv; ++ u8 reserved0; ++ u8 op_code; ++ u8 flags; ++#define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0) ++#define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 reserved2; ++ u32 src_ip_v6_2; ++ u32 src_ip_v6_3; ++ u32 src_ip_v6_4; ++ u32 dst_ip_v6_2; ++ u32 dst_ip_v6_3; ++ u32 dst_ip_v6_4; ++}; ++ ++ ++/* ++ * The third ( and last )request to be passed in order to establish connection in option2 ++ */ ++struct l4_kwq_connect_req3 { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0) ++#define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7 ++ u8 op_code; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 op_code; ++ u8 flags; ++#define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0) ++#define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0 ++#define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4) ++#define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 ka_timeout; ++ u32 ka_interval ; ++#if defined(__BIG_ENDIAN) ++ u8 snd_seq_scale; ++ u8 ttl; ++ u8 tos; ++ u8 ka_max_probe_count; ++#elif defined(__LITTLE_ENDIAN) ++ u8 ka_max_probe_count; ++ u8 tos; ++ u8 ttl; ++ u8 snd_seq_scale; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 pmtu; ++ u16 mss; ++#elif defined(__LITTLE_ENDIAN) ++ u16 mss; ++ u16 pmtu; ++#endif ++ u32 rcv_buf; ++ u32 snd_buf; ++ u32 seed; ++}; ++ ++ ++/* ++ * a KWQE request to offload a PG connection ++ */ ++struct l4_kwq_offload_pg { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0) ++#define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0 ++#define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4) ++#define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7 ++ u8 op_code; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 op_code; ++ u8 flags; ++#define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0) ++#define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0 ++#define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4) ++#define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 l2hdr_nbytes; ++ u8 pg_flags; ++#define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0) ++#define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0 ++#define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1) ++#define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1 ++#define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2) ++#define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2 ++ u8 da0; ++ u8 da1; ++#elif defined(__LITTLE_ENDIAN) ++ u8 da1; ++ u8 da0; ++ u8 pg_flags; ++#define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0) ++#define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0 ++#define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1) ++#define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1 ++#define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2) ++#define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2 ++ u8 l2hdr_nbytes; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 da2; ++ u8 da3; ++ u8 da4; ++ u8 da5; ++#elif defined(__LITTLE_ENDIAN) ++ u8 da5; ++ u8 da4; ++ u8 da3; ++ u8 da2; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 sa0; ++ u8 sa1; ++ u8 sa2; ++ u8 sa3; ++#elif defined(__LITTLE_ENDIAN) ++ u8 sa3; ++ u8 sa2; ++ u8 sa1; ++ u8 sa0; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 sa4; ++ u8 sa5; ++ u16 etype; ++#elif defined(__LITTLE_ENDIAN) ++ u16 etype; ++ u8 sa5; ++ u8 sa4; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 vlan_tag; ++ u16 ipid_start; ++#elif defined(__LITTLE_ENDIAN) ++ u16 ipid_start; ++ u16 vlan_tag; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 ipid_count; ++ u16 reserved3; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved3; ++ u16 ipid_count; ++#endif ++ u32 host_opaque; ++}; ++ ++ ++/* ++ * Abortively close the connection request ++ */ ++struct l4_kwq_reset_req { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0) ++#define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0 ++#define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4) ++#define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7 ++ u8 op_code; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 op_code; ++ u8 flags; ++#define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0) ++#define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0 ++#define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4) ++#define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 cid; ++ u32 reserved2[6]; ++}; ++ ++ ++/* ++ * a KWQE request to update a PG connection ++ */ ++struct l4_kwq_update_pg { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0) ++#define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0 ++#define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4) ++#define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7 ++ u8 opcode; ++ u16 oper16; ++#elif defined(__LITTLE_ENDIAN) ++ u16 oper16; ++ u8 opcode; ++ u8 flags; ++#define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0) ++#define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0 ++#define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4) ++#define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 pg_cid; ++ u32 pg_host_opaque; ++#if defined(__BIG_ENDIAN) ++ u8 pg_valids; ++#define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0) ++#define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0 ++#define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1) ++#define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1 ++#define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2) ++#define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2 ++ u8 pg_unused_a; ++ u16 pg_ipid_count; ++#elif defined(__LITTLE_ENDIAN) ++ u16 pg_ipid_count; ++ u8 pg_unused_a; ++ u8 pg_valids; ++#define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0) ++#define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0 ++#define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1) ++#define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1 ++#define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2) ++#define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2 ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 reserverd3; ++ u8 da0; ++ u8 da1; ++#elif defined(__LITTLE_ENDIAN) ++ u8 da1; ++ u8 da0; ++ u16 reserverd3; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 da2; ++ u8 da3; ++ u8 da4; ++ u8 da5; ++#elif defined(__LITTLE_ENDIAN) ++ u8 da5; ++ u8 da4; ++ u8 da3; ++ u8 da2; ++#endif ++ u32 reserved4; ++ u32 reserved5; ++}; ++ ++ ++/* ++ * a KWQE request to upload a PG or L4 context ++ */ ++struct l4_kwq_upload { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0) ++#define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0 ++#define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4) ++#define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7 ++ u8 opcode; ++ u16 oper16; ++#elif defined(__LITTLE_ENDIAN) ++ u16 oper16; ++ u8 opcode; ++ u8 flags; ++#define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0) ++#define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0 ++#define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4) ++#define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4 ++#define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7) ++#define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7 ++#endif ++ u32 cid; ++ u32 reserved2[6]; ++}; ++ ++#endif /* __57XX_L5CM_HSI_LINUX_LE__ */ +diff -r 5f108bc568be drivers/net/cnic_drv.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cnic_drv.h Tue Sep 01 13:50:09 2009 +0100 +@@ -0,0 +1,125 @@ ++/* cnic_drv.h: Broadcom CNIC core network driver. ++ * ++ * Copyright (c) 2008 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ * ++ */ ++ ++ ++#ifndef CNIC_DRV_H ++#define CNIC_DRV_H ++ ++#if !defined(__iomem) ++#define __iomem ++#endif ++ ++struct kwqe; ++struct kcqe; ++struct kwqe_16; ++ ++#define MAX_CNIC_CTL_DATA 64 ++#define MAX_DRV_CTL_DATA 64 ++ ++#define CNIC_CTL_STOP_CMD 1 ++#define CNIC_CTL_START_CMD 2 ++#define CNIC_CTL_COMPLETION_CMD 3 ++ ++#define DRV_CTL_IO_WR_CMD 0x101 ++#define DRV_CTL_IO_RD_CMD 0x102 ++#define DRV_CTL_CTX_WR_CMD 0x103 ++#define DRV_CTL_CTXTBL_WR_CMD 0x104 ++#define DRV_CTL_COMPLETION_CMD 0x105 ++ ++struct cnic_ctl_completion { ++ u32 cid; ++}; ++ ++struct drv_ctl_completion { ++ u32 comp_count; ++}; ++ ++struct cnic_ctl_info { ++ int cmd; ++ union { ++ struct cnic_ctl_completion comp; ++ char bytes[MAX_CNIC_CTL_DATA]; ++ } data; ++}; ++ ++struct drv_ctl_io { ++ u32 cid_addr; ++ u32 offset; ++ u32 data; ++ dma_addr_t dma_addr; ++}; ++ ++struct drv_ctl_info { ++ int cmd; ++ union { ++ struct drv_ctl_completion comp; ++ struct drv_ctl_io io; ++ char bytes[MAX_DRV_CTL_DATA]; ++ } data; ++}; ++ ++struct cnic_ops { ++ struct module *cnic_owner; ++ /* Calls to these functions are protected by RCU. When ++ * unregistering, we wait for any calls to complete before ++ * continuing. ++ */ ++ int (*cnic_handler)(void *, void *); ++ int (*cnic_ctl)(void *, struct cnic_ctl_info *); ++ unsigned long reserved[2]; ++}; ++ ++#define MAX_CNIC_VEC 8 ++ ++struct cnic_irq { ++ unsigned int vector; ++ void *status_blk; ++ u32 status_blk_num; ++ u32 irq_flags; ++#define CNIC_IRQ_FL_MSIX 0x00000001 ++}; ++ ++struct cnic_eth_dev { ++ struct module *drv_owner; ++ u32 drv_state; ++#define CNIC_DRV_STATE_REGD 0x00000001 ++#define CNIC_DRV_STATE_USING_MSIX 0x00000002 ++ u32 chip_id; ++ u32 max_kwqe_pending; ++ struct pci_dev *pdev; ++ void __iomem *io_base; ++ ++ u32 ctx_tbl_offset; ++ u32 ctx_tbl_len; ++ int ctx_blk_size; ++ u32 starting_cid; ++ u32 max_iscsi_conn; ++ u32 max_fcoe_conn; ++ u32 max_rdma_conn; ++ u32 reserved0[2]; ++ ++ int num_irq; ++ struct cnic_irq irq_arr[MAX_CNIC_VEC]; ++ int (*drv_register_cnic)(struct net_device *, ++ struct cnic_ops *, void *); ++ int (*drv_unregister_cnic)(struct net_device *); ++ int (*drv_submit_kwqes_32)(struct net_device *, ++ struct kwqe *[], u32); ++ int (*drv_submit_kwqes_16)(struct net_device *, ++ struct kwqe_16 *[], u32); ++ int (*drv_ctl)(struct net_device *, struct drv_ctl_info *); ++ unsigned long reserved1[2]; ++}; ++ ++#ifdef __VMKLNX__ ++extern struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *); ++#endif ++ ++#endif +diff -r 5f108bc568be drivers/net/cnic_if.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cnic_if.h Tue Sep 01 13:50:09 2009 +0100 +@@ -0,0 +1,209 @@ ++/* cnic_if.h: Broadcom CNIC core network driver. ++ * ++ * Copyright (c) 2006 - 2009 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ * ++ * Written by: John(Zongxi) Chen (zongxic@broadcom.com) ++ */ ++ ++ ++#ifndef CNIC_IF_H ++#define CNIC_IF_H ++ ++#define CNIC_MODULE_VERSION "1.9.3" ++#define CNIC_MODULE_RELDATE "July 9, 2009" ++ ++#define CNIC_ULP_RDMA 0 ++#define CNIC_ULP_ISCSI 1 ++#define CNIC_ULP_L4 2 ++#define MAX_CNIC_ULP_TYPE_EXT 2 ++#define MAX_CNIC_ULP_TYPE 3 ++ ++struct kwqe { ++ u32 kwqe_op_flag; ++ ++#define KWQE_OPCODE_MASK 0x00ff0000 ++#define KWQE_OPCODE_SHIFT 16 ++#define KWQE_OPCODE(x) ((x & KWQE_OPCODE_MASK) >> KWQE_OPCODE_SHIFT) ++ ++ u32 kwqe_info0; ++ u32 kwqe_info1; ++ u32 kwqe_info2; ++ u32 kwqe_info3; ++ u32 kwqe_info4; ++ u32 kwqe_info5; ++ u32 kwqe_info6; ++}; ++ ++struct kwqe_16 { ++ u32 kwqe_info0; ++ u32 kwqe_info1; ++ u32 kwqe_info2; ++ u32 kwqe_info3; ++}; ++ ++struct kcqe { ++ u32 kcqe_info0; ++ u32 kcqe_info1; ++ u32 kcqe_info2; ++ u32 kcqe_info3; ++ u32 kcqe_info4; ++ u32 kcqe_info5; ++ u32 kcqe_info6; ++ u32 kcqe_op_flag; ++ #define KCQE_RAMROD_COMPLETION (0x1<<27) /* Everest */ ++ #define KCQE_FLAGS_LAYER_MASK (0x7<<28) ++ #define KCQE_FLAGS_LAYER_MASK_MISC (0<<28) ++ #define KCQE_FLAGS_LAYER_MASK_L2 (2<<28) ++ #define KCQE_FLAGS_LAYER_MASK_L3 (3<<28) ++ #define KCQE_FLAGS_LAYER_MASK_L4 (4<<28) ++ #define KCQE_FLAGS_LAYER_MASK_L5_RDMA (5<<28) ++ #define KCQE_FLAGS_LAYER_MASK_L5_ISCSI (6<<28) ++ #define KCQE_FLAGS_NEXT (1<<31) ++ #define KCQE_FLAGS_OPCODE_MASK (0xff<<16) ++ #define KCQE_FLAGS_OPCODE_SHIFT (16) ++ #define KCQE_OPCODE(op) \ ++ (((op) & KCQE_FLAGS_OPCODE_MASK) >> KCQE_FLAGS_OPCODE_SHIFT) ++}; ++ ++struct cnic_sockaddr { ++ union { ++ struct sockaddr_in v4; ++ struct sockaddr_in6 v6; ++ } local; ++ union { ++ struct sockaddr_in v4; ++ struct sockaddr_in6 v6; ++ } remote; ++}; ++ ++struct cnic_sock { ++ struct cnic_dev *dev; ++ void *context; ++ u32 src_ip[4]; ++ u32 dst_ip[4]; ++ u16 src_port; ++ u16 dst_port; ++ u16 vlan_id; ++ unsigned char old_ha[6]; ++#ifdef __VMKLNX__ ++ unsigned char ha[6]; ++#endif ++ u16 pmtu; ++ struct dst_entry *dst; ++ u32 cid; ++ u32 l5_cid; ++ u32 pg_cid; ++ int ulp_type; ++ ++ u32 ka_timeout; ++ u32 ka_interval; ++ u8 ka_max_probe_count; ++ u8 tos; ++ u8 ttl; ++ u8 snd_seq_scale; ++ u32 rcv_buf; ++ u32 snd_buf; ++ u32 seed; ++ ++ unsigned long tcp_flags; ++#define SK_TCP_NO_DELAY_ACK 0x1 ++#define SK_TCP_KEEP_ALIVE 0x2 ++#define SK_TCP_NAGLE 0x4 ++#define SK_TCP_TIMESTAMP 0x8 ++#define SK_TCP_SACK 0x10 ++#define SK_TCP_SEG_SCALING 0x20 ++ ++ unsigned long flags; ++#define SK_F_INUSE 0 ++#define SK_F_OFFLD_COMPLETE 1 ++#define SK_F_OFFLD_SCHED 2 ++#define SK_F_PG_OFFLD_COMPLETE 3 ++#define SK_F_CONNECT_START 4 ++#define SK_F_IPV6 5 ++#define SK_F_NDISC_WAITING 6 ++#define SK_F_CLOSING 7 ++ ++ atomic_t ref_count; ++ u32 state; ++ struct kwqe kwqe1; ++ struct kwqe kwqe2; ++ struct kwqe kwqe3; ++}; ++ ++struct cnic_dev { ++ struct net_device *netdev; ++ struct pci_dev *pcidev; ++ void __iomem *regview; ++ struct list_head list; ++ ++ int (*register_device)(struct cnic_dev *dev, int ulp_type, ++ void *ulp_ctx); ++ int (*unregister_device)(struct cnic_dev *dev, int ulp_type); ++ int (*submit_kwqes)(struct cnic_dev *dev, struct kwqe *wqes[], ++ u32 num_wqes); ++ ++ int (*cm_create)(struct cnic_dev *, int, u32, u32, struct cnic_sock **, ++ void *); ++ int (*cm_destroy)(struct cnic_sock *); ++ int (*cm_connect)(struct cnic_sock *, struct cnic_sockaddr *); ++ int (*cm_abort)(struct cnic_sock *); ++ int (*cm_close)(struct cnic_sock *); ++#ifdef __VMKLNX__ ++ struct cnic_dev *(*cm_select_dev)(vmk_IscsiNetHandle iscsiNetHandle, ++ struct sockaddr_in *, int ulp_type); ++#else ++ struct cnic_dev *(*cm_select_dev)(struct sockaddr_in *, int ulp_type); ++#endif ++ unsigned long flags; ++#define CNIC_F_IF_UP 0 ++#define CNIC_F_CNIC_UP 1 ++#define CNIC_F_IF_GOING_DOWN 2 ++#define CNIC_F_BNX2_CLASS 3 ++#define CNIC_F_BNX2X_CLASS 4 ++ atomic_t ref_count; ++ int use_count; ++ ++ int max_iscsi_conn; ++ int max_fcoe_conn; ++ int max_rdma_conn; ++ ++ void *cnic_priv; ++}; ++ ++#define CNIC_WR(dev, off, val) writel(val, dev->regview + off) ++#define CNIC_WR16(dev, off, val) writew(val, dev->regview + off) ++#define CNIC_WR8(dev, off, val) writeb(val, dev->regview + off) ++#define CNIC_RD(dev, off) readl(dev->regview + off) ++#define CNIC_RD16(dev, off) readw(dev->regview + off) ++ ++struct cnic_ulp_ops { ++ /* Calls to these functions are protected by RCU. When ++ * unregistering, we wait for any calls to complete before ++ * continuing. ++ */ ++ ++ void (*cnic_init)(struct cnic_dev *dev); ++ void (*cnic_exit)(struct cnic_dev *dev); ++ void (*cnic_start)(void *ulp_ctx); ++ void (*cnic_stop)(void *ulp_ctx); ++ void (*indicate_kcqes)(void *ulp_ctx, struct kcqe *cqes[], ++ u32 num_cqes); ++ void (*indicate_netevent)(void *ulp_ctx, unsigned long event); ++ void (*indicate_inetevent)(void *ulp_ctx, unsigned long event); ++ void (*cm_connect_complete)(struct cnic_sock *); ++ void (*cm_close_complete)(struct cnic_sock *); ++ void (*cm_abort_complete)(struct cnic_sock *); ++ void (*cm_remote_close)(struct cnic_sock *); ++ void (*cm_remote_abort)(struct cnic_sock *); ++ struct module *owner; ++}; ++ ++extern int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops); ++ ++extern int cnic_unregister_driver(int ulp_type); ++ ++#endif diff --git a/master/bnx2i-1.8.9n.patch b/master/bnx2i-1.8.9n.patch new file mode 100644 index 0000000..dc65296 --- /dev/null +++ b/master/bnx2i-1.8.9n.patch @@ -0,0 +1,12981 @@ +diff -r ffba7e1f063a drivers/scsi/Kconfig +--- a/drivers/scsi/Kconfig Wed Aug 05 10:51:16 2009 +0100 ++++ b/drivers/scsi/Kconfig Wed Aug 05 10:51:49 2009 +0100 +@@ -1812,4 +1812,6 @@ + + source "drivers/scsi/device_handler/Kconfig" + ++source "drivers/scsi/bnx2i/Kconfig" ++ + endmenu +diff -r ffba7e1f063a drivers/scsi/Makefile +--- a/drivers/scsi/Makefile Wed Aug 05 10:51:16 2009 +0100 ++++ b/drivers/scsi/Makefile Wed Aug 05 10:51:49 2009 +0100 +@@ -128,6 +128,7 @@ + obj-$(CONFIG_SCSI_STEX) += stex.o + obj-$(CONFIG_SCSI_MVSAS) += mvsas.o + obj-$(CONFIG_PS3_ROM) += ps3rom.o ++obj-$(CONFIG_SCSI_BNX2_ISCSI) += bnx2i/ + + obj-$(CONFIG_ARM) += arm/ + +diff -r ffba7e1f063a drivers/scsi/bnx2i/57xx_iscsi_constants.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/bnx2i/57xx_iscsi_constants.h Wed Aug 05 10:51:49 2009 +0100 +@@ -0,0 +1,153 @@ ++/* 57xx_iscsi_constants.h: Broadcom NetXtreme II iSCSI driver. ++ * ++ * Copyright (c) 2006 - 2009 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ */ ++#ifndef __57XX_ISCSI_CONSTANTS_H_ ++#define __57XX_ISCSI_CONSTANTS_H_ ++ ++/** ++* This file defines HSI constants for the iSCSI flows ++*/ ++ ++/* iSCSI request op codes */ ++#define ISCSI_OPCODE_CLEANUP_REQUEST (7) ++ ++/* iSCSI response/messages op codes */ ++#define ISCSI_OPCODE_CLEANUP_RESPONSE (0x27) ++#define ISCSI_OPCODE_NOPOUT_LOCAL_COMPLETION (0) ++ ++/* iSCSI task types */ ++#define ISCSI_TASK_TYPE_READ (0) ++#define ISCSI_TASK_TYPE_WRITE (1) ++#define ISCSI_TASK_TYPE_MPATH (2) ++ ++/* initial CQ sequence numbers */ ++#define ISCSI_INITIAL_SN (1) ++ ++/* KWQ (kernel work queue) layer codes */ ++#define ISCSI_KWQE_LAYER_CODE (6) ++ ++/* KWQ (kernel work queue) request op codes */ ++#define ISCSI_KWQE_OPCODE_OFFLOAD_CONN1 (0) ++#define ISCSI_KWQE_OPCODE_OFFLOAD_CONN2 (1) ++#define ISCSI_KWQE_OPCODE_UPDATE_CONN (2) ++#define ISCSI_KWQE_OPCODE_DESTROY_CONN (3) ++#define ISCSI_KWQE_OPCODE_INIT1 (4) ++#define ISCSI_KWQE_OPCODE_INIT2 (5) ++ ++/* KCQ (kernel completion queue) response op codes */ ++#define ISCSI_KCQE_OPCODE_OFFLOAD_CONN (0x10) ++#define ISCSI_KCQE_OPCODE_UPDATE_CONN (0x12) ++#define ISCSI_KCQE_OPCODE_DESTROY_CONN (0x13) ++#define ISCSI_KCQE_OPCODE_INIT (0x14) ++#define ISCSI_KCQE_OPCODE_FW_CLEAN_TASK (0x15) ++#define ISCSI_KCQE_OPCODE_TCP_RESET (0x16) ++#define ISCSI_KCQE_OPCODE_TCP_SYN (0x17) ++#define ISCSI_KCQE_OPCODE_TCP_FIN (0X18) ++#define ISCSI_KCQE_OPCODE_TCP_ERROR (0x19) ++#define ISCSI_KCQE_OPCODE_CQ_EVENT_NOTIFICATION (0x20) ++#define ISCSI_KCQE_OPCODE_ISCSI_ERROR (0x21) ++ ++/* KCQ (kernel completion queue) completion status */ ++#define ISCSI_KCQE_COMPLETION_STATUS_SUCCESS (0x0) ++#define ISCSI_KCQE_COMPLETION_STATUS_INVALID_OPCODE (0x1) ++#define ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE (0x2) ++#define ISCSI_KCQE_COMPLETION_STATUS_CTX_FREE_FAILURE (0x3) ++#define ISCSI_KCQE_COMPLETION_STATUS_NIC_ERROR (0x4) ++ ++#define ISCSI_KCQE_COMPLETION_STATUS_HDR_DIG_ERR (0x5) ++#define ISCSI_KCQE_COMPLETION_STATUS_DATA_DIG_ERR (0x6) ++ ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_UNEXPECTED_OPCODE (0xa) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_OPCODE (0xb) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_AHS_LEN (0xc) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_ITT (0xd) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_STATSN (0xe) ++ ++/* Response */ ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_EXP_DATASN (0xf) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T (0x10) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATA_SEG_LEN_IS_ZERO (0x2c) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATA_SEG_LEN_TOO_BIG (0x2d) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_0 (0x11) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_1 (0x12) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_2 (0x13) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_3 (0x14) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_4 (0x15) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_5 (0x16) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_6 (0x17) ++ ++/* Data-In */ ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REMAIN_RCV_LEN (0x18) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_MAX_RCV_PDU_LEN (0x19) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_F_BIT_ZERO (0x1a) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_TTT_NOT_RSRV (0x1b) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATASN (0x1c) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REMAIN_BURST_LEN (0x1d) ++ ++/* R2T */ ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_BUFFER_OFF (0x1f) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_LUN (0x20) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_R2TSN (0x21) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_0 (0x22) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_1 (0x23) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T_EXCEED (0x24) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_TTT_IS_RSRV (0x25) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_MAX_BURST_LEN (0x26) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATA_SEG_LEN_NOT_ZERO (0x27) ++ ++/* TMF */ ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REJECT_PDU_LEN (0x28) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_ASYNC_PDU_LEN (0x29) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_NOPIN_PDU_LEN (0x2a) ++#define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T_IN_CLEANUP (0x2b) ++ ++/* IP/TCP processing errors: */ ++#define ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_IP_FRAGMENT (0x40) ++#define ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_IP_OPTIONS (0x41) ++#define ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_URGENT_FLAG (0x42) ++#define ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_MAX_RTRANS (0x43) ++ ++/* iSCSI licensing errors */ ++/* general iSCSI license not installed */ ++#define ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED (0x50) ++/* additional LOM specific iSCSI license not installed */ ++#define ISCSI_KCQE_COMPLETION_STATUS_LOM_ISCSI_NOT_ENABLED (0x51) ++ ++/* SQ/RQ/CQ DB structure sizes */ ++#define ISCSI_SQ_DB_SIZE (16) ++#define ISCSI_RQ_DB_SIZE (16) ++#define ISCSI_CQ_DB_SIZE (80) ++ ++#define ISCSI_SQN_TO_NOTIFY_NOT_VALID 0xFFFF ++ ++/* Page size codes (for flags field in connection offload request) */ ++#define ISCSI_PAGE_SIZE_256 (0) ++#define ISCSI_PAGE_SIZE_512 (1) ++#define ISCSI_PAGE_SIZE_1K (2) ++#define ISCSI_PAGE_SIZE_2K (3) ++#define ISCSI_PAGE_SIZE_4K (4) ++#define ISCSI_PAGE_SIZE_8K (5) ++#define ISCSI_PAGE_SIZE_16K (6) ++#define ISCSI_PAGE_SIZE_32K (7) ++#define ISCSI_PAGE_SIZE_64K (8) ++#define ISCSI_PAGE_SIZE_128K (9) ++#define ISCSI_PAGE_SIZE_256K (10) ++#define ISCSI_PAGE_SIZE_512K (11) ++#define ISCSI_PAGE_SIZE_1M (12) ++#define ISCSI_PAGE_SIZE_2M (13) ++#define ISCSI_PAGE_SIZE_4M (14) ++#define ISCSI_PAGE_SIZE_8M (15) ++ ++/* Iscsi PDU related defines */ ++#define ISCSI_HEADER_SIZE (48) ++#define ISCSI_DIGEST_SHIFT (2) ++#define ISCSI_DIGEST_SIZE (4) ++ ++#define B577XX_ISCSI_CONNECTION_TYPE 3 ++ ++#endif /*__57XX_ISCSI_CONSTANTS_H_ */ +diff -r ffba7e1f063a drivers/scsi/bnx2i/57xx_iscsi_hsi.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/bnx2i/57xx_iscsi_hsi.h Wed Aug 05 10:51:49 2009 +0100 +@@ -0,0 +1,1524 @@ ++/* 57xx_iscsi_hsi.h: Broadcom NetXtreme II iSCSI driver. ++ * ++ * Copyright (c) 2006 - 2009 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ */ ++#ifndef __57XX_ISCSI_HSI_LINUX_LE__ ++#define __57XX_ISCSI_HSI_LINUX_LE__ ++ ++/* ++ * iSCSI Async CQE ++ */ ++struct iscsi_async_msg { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 reserved1; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 reserved1; ++ u8 op_code; ++#endif ++ u32 reserved2; ++ u32 exp_cmd_sn; ++ u32 max_cmd_sn; ++ u32 reserved3[2]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved5; ++ u8 err_code; ++ u8 reserved4; ++#elif defined(__LITTLE_ENDIAN) ++ u8 reserved4; ++ u8 err_code; ++ u16 reserved5; ++#endif ++ u32 reserved6; ++ u32 lun[2]; ++#if defined(__BIG_ENDIAN) ++ u8 async_event; ++ u8 async_vcode; ++ u16 param1; ++#elif defined(__LITTLE_ENDIAN) ++ u16 param1; ++ u8 async_vcode; ++ u8 async_event; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 param2; ++ u16 param3; ++#elif defined(__LITTLE_ENDIAN) ++ u16 param3; ++ u16 param2; ++#endif ++ u32 reserved7[3]; ++ u32 cq_req_sn; ++}; ++ ++ ++/* ++ * iSCSI Buffer Descriptor (BD) ++ */ ++struct iscsi_bd { ++ u32 buffer_addr_hi; ++ u32 buffer_addr_lo; ++#if defined(__BIG_ENDIAN) ++ u16 reserved0; ++ u16 buffer_length; ++#elif defined(__LITTLE_ENDIAN) ++ u16 buffer_length; ++ u16 reserved0; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 reserved3; ++ u16 flags; ++#define ISCSI_BD_RESERVED1 (0x3F<<0) ++#define ISCSI_BD_RESERVED1_SHIFT 0 ++#define ISCSI_BD_LAST_IN_BD_CHAIN (0x1<<6) ++#define ISCSI_BD_LAST_IN_BD_CHAIN_SHIFT 6 ++#define ISCSI_BD_FIRST_IN_BD_CHAIN (0x1<<7) ++#define ISCSI_BD_FIRST_IN_BD_CHAIN_SHIFT 7 ++#define ISCSI_BD_RESERVED2 (0xFF<<8) ++#define ISCSI_BD_RESERVED2_SHIFT 8 ++#elif defined(__LITTLE_ENDIAN) ++ u16 flags; ++#define ISCSI_BD_RESERVED1 (0x3F<<0) ++#define ISCSI_BD_RESERVED1_SHIFT 0 ++#define ISCSI_BD_LAST_IN_BD_CHAIN (0x1<<6) ++#define ISCSI_BD_LAST_IN_BD_CHAIN_SHIFT 6 ++#define ISCSI_BD_FIRST_IN_BD_CHAIN (0x1<<7) ++#define ISCSI_BD_FIRST_IN_BD_CHAIN_SHIFT 7 ++#define ISCSI_BD_RESERVED2 (0xFF<<8) ++#define ISCSI_BD_RESERVED2_SHIFT 8 ++ u16 reserved3; ++#endif ++}; ++ ++ ++/* ++ * iSCSI Cleanup SQ WQE ++ */ ++struct iscsi_cleanup_request { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 reserved1; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 reserved1; ++ u8 op_code; ++#endif ++ u32 reserved2[3]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved3; ++ u16 itt; ++#define ISCSI_CLEANUP_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_CLEANUP_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_CLEANUP_REQUEST_TYPE (0x3<<14) ++#define ISCSI_CLEANUP_REQUEST_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_CLEANUP_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_CLEANUP_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_CLEANUP_REQUEST_TYPE (0x3<<14) ++#define ISCSI_CLEANUP_REQUEST_TYPE_SHIFT 14 ++ u16 reserved3; ++#endif ++ u32 reserved4[10]; ++#if defined(__BIG_ENDIAN) ++ u8 cq_index; ++ u8 reserved6; ++ u16 reserved5; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved5; ++ u8 reserved6; ++ u8 cq_index; ++#endif ++}; ++ ++ ++/* ++ * iSCSI Cleanup CQE ++ */ ++struct iscsi_cleanup_response { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 status; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 status; ++ u8 op_code; ++#endif ++ u32 reserved1[3]; ++ u32 reserved2[2]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved4; ++ u8 err_code; ++ u8 reserved3; ++#elif defined(__LITTLE_ENDIAN) ++ u8 reserved3; ++ u8 err_code; ++ u16 reserved4; ++#endif ++ u32 reserved5[7]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved6; ++ u16 itt; ++#define ISCSI_CLEANUP_RESPONSE_INDEX (0x3FFF<<0) ++#define ISCSI_CLEANUP_RESPONSE_INDEX_SHIFT 0 ++#define ISCSI_CLEANUP_RESPONSE_TYPE (0x3<<14) ++#define ISCSI_CLEANUP_RESPONSE_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_CLEANUP_RESPONSE_INDEX (0x3FFF<<0) ++#define ISCSI_CLEANUP_RESPONSE_INDEX_SHIFT 0 ++#define ISCSI_CLEANUP_RESPONSE_TYPE (0x3<<14) ++#define ISCSI_CLEANUP_RESPONSE_TYPE_SHIFT 14 ++ u16 reserved6; ++#endif ++ u32 cq_req_sn; ++}; ++ ++ ++/* ++ * SCSI read/write SQ WQE ++ */ ++struct iscsi_cmd_request { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 op_attr; ++#define ISCSI_CMD_REQUEST_TASK_ATTR (0x7<<0) ++#define ISCSI_CMD_REQUEST_TASK_ATTR_SHIFT 0 ++#define ISCSI_CMD_REQUEST_RESERVED1 (0x3<<3) ++#define ISCSI_CMD_REQUEST_RESERVED1_SHIFT 3 ++#define ISCSI_CMD_REQUEST_WRITE (0x1<<5) ++#define ISCSI_CMD_REQUEST_WRITE_SHIFT 5 ++#define ISCSI_CMD_REQUEST_READ (0x1<<6) ++#define ISCSI_CMD_REQUEST_READ_SHIFT 6 ++#define ISCSI_CMD_REQUEST_FINAL (0x1<<7) ++#define ISCSI_CMD_REQUEST_FINAL_SHIFT 7 ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 op_attr; ++#define ISCSI_CMD_REQUEST_TASK_ATTR (0x7<<0) ++#define ISCSI_CMD_REQUEST_TASK_ATTR_SHIFT 0 ++#define ISCSI_CMD_REQUEST_RESERVED1 (0x3<<3) ++#define ISCSI_CMD_REQUEST_RESERVED1_SHIFT 3 ++#define ISCSI_CMD_REQUEST_WRITE (0x1<<5) ++#define ISCSI_CMD_REQUEST_WRITE_SHIFT 5 ++#define ISCSI_CMD_REQUEST_READ (0x1<<6) ++#define ISCSI_CMD_REQUEST_READ_SHIFT 6 ++#define ISCSI_CMD_REQUEST_FINAL (0x1<<7) ++#define ISCSI_CMD_REQUEST_FINAL_SHIFT 7 ++ u8 op_code; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 ud_buffer_offset; ++ u16 sd_buffer_offset; ++#elif defined(__LITTLE_ENDIAN) ++ u16 sd_buffer_offset; ++ u16 ud_buffer_offset; ++#endif ++ u32 lun[2]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved2; ++ u16 itt; ++#define ISCSI_CMD_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_CMD_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_CMD_REQUEST_TYPE (0x3<<14) ++#define ISCSI_CMD_REQUEST_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_CMD_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_CMD_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_CMD_REQUEST_TYPE (0x3<<14) ++#define ISCSI_CMD_REQUEST_TYPE_SHIFT 14 ++ u16 reserved2; ++#endif ++ u32 total_data_transfer_length; ++ u32 cmd_sn; ++ u32 reserved3; ++ u32 cdb[4]; ++ u32 zero_fill; ++ u32 bd_list_addr_lo; ++ u32 bd_list_addr_hi; ++#if defined(__BIG_ENDIAN) ++ u8 cq_index; ++ u8 sd_start_bd_index; ++ u8 ud_start_bd_index; ++ u8 num_bds; ++#elif defined(__LITTLE_ENDIAN) ++ u8 num_bds; ++ u8 ud_start_bd_index; ++ u8 sd_start_bd_index; ++ u8 cq_index; ++#endif ++}; ++ ++ ++/* ++ * task statistics for write response ++ */ ++struct iscsi_write_resp_task_stat { ++ u32 num_data_ins; ++}; ++ ++/* ++ * task statistics for read response ++ */ ++struct iscsi_read_resp_task_stat { ++#if defined(__BIG_ENDIAN) ++ u16 num_data_outs; ++ u16 num_r2ts; ++#elif defined(__LITTLE_ENDIAN) ++ u16 num_r2ts; ++ u16 num_data_outs; ++#endif ++}; ++ ++/* ++ * task statistics for iSCSI cmd response ++ */ ++union iscsi_cmd_resp_task_stat { ++ struct iscsi_write_resp_task_stat write_stat; ++ struct iscsi_read_resp_task_stat read_stat; ++}; ++ ++/* ++ * SCSI Command CQE ++ */ ++struct iscsi_cmd_response { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 response_flags; ++#define ISCSI_CMD_RESPONSE_RESERVED0 (0x1<<0) ++#define ISCSI_CMD_RESPONSE_RESERVED0_SHIFT 0 ++#define ISCSI_CMD_RESPONSE_RESIDUAL_UNDERFLOW (0x1<<1) ++#define ISCSI_CMD_RESPONSE_RESIDUAL_UNDERFLOW_SHIFT 1 ++#define ISCSI_CMD_RESPONSE_RESIDUAL_OVERFLOW (0x1<<2) ++#define ISCSI_CMD_RESPONSE_RESIDUAL_OVERFLOW_SHIFT 2 ++#define ISCSI_CMD_RESPONSE_BR_RESIDUAL_UNDERFLOW (0x1<<3) ++#define ISCSI_CMD_RESPONSE_BR_RESIDUAL_UNDERFLOW_SHIFT 3 ++#define ISCSI_CMD_RESPONSE_BR_RESIDUAL_OVERFLOW (0x1<<4) ++#define ISCSI_CMD_RESPONSE_BR_RESIDUAL_OVERFLOW_SHIFT 4 ++#define ISCSI_CMD_RESPONSE_RESERVED1 (0x7<<5) ++#define ISCSI_CMD_RESPONSE_RESERVED1_SHIFT 5 ++ u8 response; ++ u8 status; ++#elif defined(__LITTLE_ENDIAN) ++ u8 status; ++ u8 response; ++ u8 response_flags; ++#define ISCSI_CMD_RESPONSE_RESERVED0 (0x1<<0) ++#define ISCSI_CMD_RESPONSE_RESERVED0_SHIFT 0 ++#define ISCSI_CMD_RESPONSE_RESIDUAL_UNDERFLOW (0x1<<1) ++#define ISCSI_CMD_RESPONSE_RESIDUAL_UNDERFLOW_SHIFT 1 ++#define ISCSI_CMD_RESPONSE_RESIDUAL_OVERFLOW (0x1<<2) ++#define ISCSI_CMD_RESPONSE_RESIDUAL_OVERFLOW_SHIFT 2 ++#define ISCSI_CMD_RESPONSE_BR_RESIDUAL_UNDERFLOW (0x1<<3) ++#define ISCSI_CMD_RESPONSE_BR_RESIDUAL_UNDERFLOW_SHIFT 3 ++#define ISCSI_CMD_RESPONSE_BR_RESIDUAL_OVERFLOW (0x1<<4) ++#define ISCSI_CMD_RESPONSE_BR_RESIDUAL_OVERFLOW_SHIFT 4 ++#define ISCSI_CMD_RESPONSE_RESERVED1 (0x7<<5) ++#define ISCSI_CMD_RESPONSE_RESERVED1_SHIFT 5 ++ u8 op_code; ++#endif ++ u32 data_length; ++ u32 exp_cmd_sn; ++ u32 max_cmd_sn; ++ u32 reserved2; ++ u32 residual_count; ++#if defined(__BIG_ENDIAN) ++ u16 reserved4; ++ u8 err_code; ++ u8 reserved3; ++#elif defined(__LITTLE_ENDIAN) ++ u8 reserved3; ++ u8 err_code; ++ u16 reserved4; ++#endif ++ u32 reserved5[5]; ++ union iscsi_cmd_resp_task_stat task_stat; ++ u32 reserved6; ++#if defined(__BIG_ENDIAN) ++ u16 reserved7; ++ u16 itt; ++#define ISCSI_CMD_RESPONSE_INDEX (0x3FFF<<0) ++#define ISCSI_CMD_RESPONSE_INDEX_SHIFT 0 ++#define ISCSI_CMD_RESPONSE_TYPE (0x3<<14) ++#define ISCSI_CMD_RESPONSE_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_CMD_RESPONSE_INDEX (0x3FFF<<0) ++#define ISCSI_CMD_RESPONSE_INDEX_SHIFT 0 ++#define ISCSI_CMD_RESPONSE_TYPE (0x3<<14) ++#define ISCSI_CMD_RESPONSE_TYPE_SHIFT 14 ++ u16 reserved7; ++#endif ++ u32 cq_req_sn; ++}; ++ ++ ++ ++/* ++ * firmware middle-path request SQ WQE ++ */ ++struct iscsi_fw_mp_request { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 op_attr; ++ u16 hdr_opaque1; ++#elif defined(__LITTLE_ENDIAN) ++ u16 hdr_opaque1; ++ u8 op_attr; ++ u8 op_code; ++#endif ++ u32 data_length; ++ u32 hdr_opaque2[2]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved0; ++ u16 itt; ++#define ISCSI_FW_MP_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_FW_MP_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_FW_MP_REQUEST_TYPE (0x3<<14) ++#define ISCSI_FW_MP_REQUEST_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_FW_MP_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_FW_MP_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_FW_MP_REQUEST_TYPE (0x3<<14) ++#define ISCSI_FW_MP_REQUEST_TYPE_SHIFT 14 ++ u16 reserved0; ++#endif ++ u32 hdr_opaque3[4]; ++ u32 resp_bd_list_addr_lo; ++ u32 resp_bd_list_addr_hi; ++ u32 resp_buffer; ++#define ISCSI_FW_MP_REQUEST_RESP_BUFFER_LENGTH (0xFFFFFF<<0) ++#define ISCSI_FW_MP_REQUEST_RESP_BUFFER_LENGTH_SHIFT 0 ++#define ISCSI_FW_MP_REQUEST_NUM_RESP_BDS (0xFF<<24) ++#define ISCSI_FW_MP_REQUEST_NUM_RESP_BDS_SHIFT 24 ++#if defined(__BIG_ENDIAN) ++ u16 reserved4; ++ u8 reserved3; ++ u8 flags; ++#define ISCSI_FW_MP_REQUEST_RESERVED1 (0x1<<0) ++#define ISCSI_FW_MP_REQUEST_RESERVED1_SHIFT 0 ++#define ISCSI_FW_MP_REQUEST_LOCAL_COMPLETION (0x1<<1) ++#define ISCSI_FW_MP_REQUEST_LOCAL_COMPLETION_SHIFT 1 ++#define ISCSI_FW_MP_REQUEST_UPDATE_EXP_STAT_SN (0x1<<2) ++#define ISCSI_FW_MP_REQUEST_UPDATE_EXP_STAT_SN_SHIFT 2 ++#define ISCSI_FW_MP_REQUEST_RESERVED2 (0x1F<<3) ++#define ISCSI_FW_MP_REQUEST_RESERVED2_SHIFT 3 ++#elif defined(__LITTLE_ENDIAN) ++ u8 flags; ++#define ISCSI_FW_MP_REQUEST_RESERVED1 (0x1<<0) ++#define ISCSI_FW_MP_REQUEST_RESERVED1_SHIFT 0 ++#define ISCSI_FW_MP_REQUEST_LOCAL_COMPLETION (0x1<<1) ++#define ISCSI_FW_MP_REQUEST_LOCAL_COMPLETION_SHIFT 1 ++#define ISCSI_FW_MP_REQUEST_UPDATE_EXP_STAT_SN (0x1<<2) ++#define ISCSI_FW_MP_REQUEST_UPDATE_EXP_STAT_SN_SHIFT 2 ++#define ISCSI_FW_MP_REQUEST_RESERVED2 (0x1F<<3) ++#define ISCSI_FW_MP_REQUEST_RESERVED2_SHIFT 3 ++ u8 reserved3; ++ u16 reserved4; ++#endif ++ u32 bd_list_addr_lo; ++ u32 bd_list_addr_hi; ++#if defined(__BIG_ENDIAN) ++ u8 cq_index; ++ u8 reserved6; ++ u8 reserved5; ++ u8 num_bds; ++#elif defined(__LITTLE_ENDIAN) ++ u8 num_bds; ++ u8 reserved5; ++ u8 reserved6; ++ u8 cq_index; ++#endif ++}; ++ ++ ++/* ++ * firmware response - CQE: used only by firmware ++ */ ++struct iscsi_fw_response { ++ u32 hdr_dword1[2]; ++ u32 hdr_exp_cmd_sn; ++ u32 hdr_max_cmd_sn; ++ u32 hdr_ttt; ++ u32 hdr_res_cnt; ++ u32 cqe_flags; ++#define ISCSI_FW_RESPONSE_RESERVED2 (0xFF<<0) ++#define ISCSI_FW_RESPONSE_RESERVED2_SHIFT 0 ++#define ISCSI_FW_RESPONSE_ERR_CODE (0xFF<<8) ++#define ISCSI_FW_RESPONSE_ERR_CODE_SHIFT 8 ++#define ISCSI_FW_RESPONSE_RESERVED3 (0xFFFF<<16) ++#define ISCSI_FW_RESPONSE_RESERVED3_SHIFT 16 ++ u32 stat_sn; ++ u32 hdr_dword2[2]; ++ u32 hdr_dword3[2]; ++ u32 task_stat; ++ u32 reserved0; ++ u32 hdr_itt; ++ u32 cq_req_sn; ++}; ++ ++ ++/* ++ * iSCSI KCQ CQE parameters ++ */ ++union iscsi_kcqe_params { ++ u32 reserved0[4]; ++}; ++ ++/* ++ * iSCSI KCQ CQE ++ */ ++struct iscsi_kcqe { ++ u32 iscsi_conn_id; ++ u32 completion_status; ++ u32 iscsi_conn_context_id; ++ union iscsi_kcqe_params params; ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define ISCSI_KCQE_RESERVED0 (0xF<<0) ++#define ISCSI_KCQE_RESERVED0_SHIFT 0 ++#define ISCSI_KCQE_LAYER_CODE (0x7<<4) ++#define ISCSI_KCQE_LAYER_CODE_SHIFT 4 ++#define ISCSI_KCQE_RESERVED1 (0x1<<7) ++#define ISCSI_KCQE_RESERVED1_SHIFT 7 ++ u8 op_code; ++ u16 qe_self_seq; ++#elif defined(__LITTLE_ENDIAN) ++ u16 qe_self_seq; ++ u8 op_code; ++ u8 flags; ++#define ISCSI_KCQE_RESERVED0 (0xF<<0) ++#define ISCSI_KCQE_RESERVED0_SHIFT 0 ++#define ISCSI_KCQE_LAYER_CODE (0x7<<4) ++#define ISCSI_KCQE_LAYER_CODE_SHIFT 4 ++#define ISCSI_KCQE_RESERVED1 (0x1<<7) ++#define ISCSI_KCQE_RESERVED1_SHIFT 7 ++#endif ++}; ++ ++ ++ ++/* ++ * iSCSI KWQE header ++ */ ++struct iscsi_kwqe_header { ++#if defined(__BIG_ENDIAN) ++ u8 flags; ++#define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0) ++#define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0 ++#define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4) ++#define ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT 4 ++#define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7) ++#define ISCSI_KWQE_HEADER_RESERVED1_SHIFT 7 ++ u8 op_code; ++#elif defined(__LITTLE_ENDIAN) ++ u8 op_code; ++ u8 flags; ++#define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0) ++#define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0 ++#define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4) ++#define ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT 4 ++#define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7) ++#define ISCSI_KWQE_HEADER_RESERVED1_SHIFT 7 ++#endif ++}; ++ ++/* ++ * iSCSI firmware init request 1 ++ */ ++struct iscsi_kwqe_init1 { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u8 reserved0; ++ u8 num_cqs; ++#elif defined(__LITTLE_ENDIAN) ++ u8 num_cqs; ++ u8 reserved0; ++ struct iscsi_kwqe_header hdr; ++#endif ++ u32 dummy_buffer_addr_lo; ++ u32 dummy_buffer_addr_hi; ++#if defined(__BIG_ENDIAN) ++ u16 num_ccells_per_conn; ++ u16 num_tasks_per_conn; ++#elif defined(__LITTLE_ENDIAN) ++ u16 num_tasks_per_conn; ++ u16 num_ccells_per_conn; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 sq_wqes_per_page; ++ u16 sq_num_wqes; ++#elif defined(__LITTLE_ENDIAN) ++ u16 sq_num_wqes; ++ u16 sq_wqes_per_page; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 cq_log_wqes_per_page; ++ u8 flags; ++#define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0) ++#define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0 ++#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4) ++#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE_SHIFT 4 ++#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5) ++#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE_SHIFT 5 ++#define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6) ++#define ISCSI_KWQE_INIT1_RESERVED1_SHIFT 6 ++ u16 cq_num_wqes; ++#elif defined(__LITTLE_ENDIAN) ++ u16 cq_num_wqes; ++ u8 flags; ++#define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0) ++#define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0 ++#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4) ++#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE_SHIFT 4 ++#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5) ++#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE_SHIFT 5 ++#define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6) ++#define ISCSI_KWQE_INIT1_RESERVED1_SHIFT 6 ++ u8 cq_log_wqes_per_page; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 cq_num_pages; ++ u16 sq_num_pages; ++#elif defined(__LITTLE_ENDIAN) ++ u16 sq_num_pages; ++ u16 cq_num_pages; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 rq_buffer_size; ++ u16 rq_num_wqes; ++#elif defined(__LITTLE_ENDIAN) ++ u16 rq_num_wqes; ++ u16 rq_buffer_size; ++#endif ++}; ++ ++/* ++ * iSCSI firmware init request 2 ++ */ ++struct iscsi_kwqe_init2 { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u16 max_cq_sqn; ++#elif defined(__LITTLE_ENDIAN) ++ u16 max_cq_sqn; ++ struct iscsi_kwqe_header hdr; ++#endif ++ u32 error_bit_map[2]; ++ u32 reserved1[5]; ++}; ++ ++/* ++ * Initial iSCSI connection offload request 1 ++ */ ++struct iscsi_kwqe_conn_offload1 { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u16 iscsi_conn_id; ++#elif defined(__LITTLE_ENDIAN) ++ u16 iscsi_conn_id; ++ struct iscsi_kwqe_header hdr; ++#endif ++ u32 sq_page_table_addr_lo; ++ u32 sq_page_table_addr_hi; ++ u32 cq_page_table_addr_lo; ++ u32 cq_page_table_addr_hi; ++ u32 reserved0[3]; ++}; ++ ++/* ++ * iSCSI Page Table Entry (PTE) ++ */ ++struct iscsi_pte { ++ u32 hi; ++ u32 lo; ++}; ++ ++/* ++ * Initial iSCSI connection offload request 2 ++ */ ++struct iscsi_kwqe_conn_offload2 { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ struct iscsi_kwqe_header hdr; ++#endif ++ u32 rq_page_table_addr_lo; ++ u32 rq_page_table_addr_hi; ++ struct iscsi_pte sq_first_pte; ++ struct iscsi_pte cq_first_pte; ++ u32 num_additional_wqes; ++}; ++ ++ ++/* ++ * Initial iSCSI connection offload request 3 ++ */ ++struct iscsi_kwqe_conn_offload3 { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ struct iscsi_kwqe_header hdr; ++#endif ++ u32 reserved1; ++ struct iscsi_pte qp_first_pte[3]; ++}; ++ ++ ++/* ++ * iSCSI connection update request ++ */ ++struct iscsi_kwqe_conn_update { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ struct iscsi_kwqe_header hdr; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 session_error_recovery_level; ++ u8 max_outstanding_r2ts; ++ u8 reserved2; ++ u8 conn_flags; ++#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0) ++#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0 ++#define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST (0x1<<1) ++#define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST_SHIFT 1 ++#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T (0x1<<2) ++#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2 ++#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3) ++#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3 ++#define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0xF<<4) ++#define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 4 ++#elif defined(__LITTLE_ENDIAN) ++ u8 conn_flags; ++#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0) ++#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0 ++#define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST (0x1<<1) ++#define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST_SHIFT 1 ++#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T (0x1<<2) ++#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2 ++#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3) ++#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3 ++#define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0xF<<4) ++#define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 4 ++ u8 reserved2; ++ u8 max_outstanding_r2ts; ++ u8 session_error_recovery_level; ++#endif ++ u32 context_id; ++ u32 max_send_pdu_length; ++ u32 max_recv_pdu_length; ++ u32 first_burst_length; ++ u32 max_burst_length; ++ u32 exp_stat_sn; ++}; ++ ++/* ++ * iSCSI destroy connection request ++ */ ++struct iscsi_kwqe_conn_destroy { ++#if defined(__BIG_ENDIAN) ++ struct iscsi_kwqe_header hdr; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ struct iscsi_kwqe_header hdr; ++#endif ++ u32 context_id; ++ u32 reserved1[6]; ++}; ++ ++/* ++ * iSCSI KWQ WQE ++ */ ++union iscsi_kwqe { ++ struct iscsi_kwqe_init1 init1; ++ struct iscsi_kwqe_init2 init2; ++ struct iscsi_kwqe_conn_offload1 conn_offload1; ++ struct iscsi_kwqe_conn_offload2 conn_offload2; ++ struct iscsi_kwqe_conn_update conn_update; ++ struct iscsi_kwqe_conn_destroy conn_destroy; ++}; ++ ++ ++ ++ ++ ++ ++ ++ ++ ++/* ++ * iSCSI Login SQ WQE ++ */ ++struct iscsi_login_request { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 op_attr; ++#define ISCSI_LOGIN_REQUEST_NEXT_STAGE (0x3<<0) ++#define ISCSI_LOGIN_REQUEST_NEXT_STAGE_SHIFT 0 ++#define ISCSI_LOGIN_REQUEST_CURRENT_STAGE (0x3<<2) ++#define ISCSI_LOGIN_REQUEST_CURRENT_STAGE_SHIFT 2 ++#define ISCSI_LOGIN_REQUEST_RESERVED0 (0x3<<4) ++#define ISCSI_LOGIN_REQUEST_RESERVED0_SHIFT 4 ++#define ISCSI_LOGIN_REQUEST_CONT (0x1<<6) ++#define ISCSI_LOGIN_REQUEST_CONT_SHIFT 6 ++#define ISCSI_LOGIN_REQUEST_TRANSIT (0x1<<7) ++#define ISCSI_LOGIN_REQUEST_TRANSIT_SHIFT 7 ++ u8 version_max; ++ u8 version_min; ++#elif defined(__LITTLE_ENDIAN) ++ u8 version_min; ++ u8 version_max; ++ u8 op_attr; ++#define ISCSI_LOGIN_REQUEST_NEXT_STAGE (0x3<<0) ++#define ISCSI_LOGIN_REQUEST_NEXT_STAGE_SHIFT 0 ++#define ISCSI_LOGIN_REQUEST_CURRENT_STAGE (0x3<<2) ++#define ISCSI_LOGIN_REQUEST_CURRENT_STAGE_SHIFT 2 ++#define ISCSI_LOGIN_REQUEST_RESERVED0 (0x3<<4) ++#define ISCSI_LOGIN_REQUEST_RESERVED0_SHIFT 4 ++#define ISCSI_LOGIN_REQUEST_CONT (0x1<<6) ++#define ISCSI_LOGIN_REQUEST_CONT_SHIFT 6 ++#define ISCSI_LOGIN_REQUEST_TRANSIT (0x1<<7) ++#define ISCSI_LOGIN_REQUEST_TRANSIT_SHIFT 7 ++ u8 op_code; ++#endif ++ u32 data_length; ++ u32 isid_lo; ++#if defined(__BIG_ENDIAN) ++ u16 isid_hi; ++ u16 tsih; ++#elif defined(__LITTLE_ENDIAN) ++ u16 tsih; ++ u16 isid_hi; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 reserved2; ++ u16 itt; ++#define ISCSI_LOGIN_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_LOGIN_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_LOGIN_REQUEST_TYPE (0x3<<14) ++#define ISCSI_LOGIN_REQUEST_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_LOGIN_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_LOGIN_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_LOGIN_REQUEST_TYPE (0x3<<14) ++#define ISCSI_LOGIN_REQUEST_TYPE_SHIFT 14 ++ u16 reserved2; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 cid; ++ u16 reserved3; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved3; ++ u16 cid; ++#endif ++ u32 cmd_sn; ++ u32 exp_stat_sn; ++ u32 reserved4; ++ u32 resp_bd_list_addr_lo; ++ u32 resp_bd_list_addr_hi; ++ u32 resp_buffer; ++#define ISCSI_LOGIN_REQUEST_RESP_BUFFER_LENGTH (0xFFFFFF<<0) ++#define ISCSI_LOGIN_REQUEST_RESP_BUFFER_LENGTH_SHIFT 0 ++#define ISCSI_LOGIN_REQUEST_NUM_RESP_BDS (0xFF<<24) ++#define ISCSI_LOGIN_REQUEST_NUM_RESP_BDS_SHIFT 24 ++#if defined(__BIG_ENDIAN) ++ u16 reserved8; ++ u8 reserved7; ++ u8 flags; ++#define ISCSI_LOGIN_REQUEST_RESERVED5 (0x3<<0) ++#define ISCSI_LOGIN_REQUEST_RESERVED5_SHIFT 0 ++#define ISCSI_LOGIN_REQUEST_UPDATE_EXP_STAT_SN (0x1<<2) ++#define ISCSI_LOGIN_REQUEST_UPDATE_EXP_STAT_SN_SHIFT 2 ++#define ISCSI_LOGIN_REQUEST_RESERVED6 (0x1F<<3) ++#define ISCSI_LOGIN_REQUEST_RESERVED6_SHIFT 3 ++#elif defined(__LITTLE_ENDIAN) ++ u8 flags; ++#define ISCSI_LOGIN_REQUEST_RESERVED5 (0x3<<0) ++#define ISCSI_LOGIN_REQUEST_RESERVED5_SHIFT 0 ++#define ISCSI_LOGIN_REQUEST_UPDATE_EXP_STAT_SN (0x1<<2) ++#define ISCSI_LOGIN_REQUEST_UPDATE_EXP_STAT_SN_SHIFT 2 ++#define ISCSI_LOGIN_REQUEST_RESERVED6 (0x1F<<3) ++#define ISCSI_LOGIN_REQUEST_RESERVED6_SHIFT 3 ++ u8 reserved7; ++ u16 reserved8; ++#endif ++ u32 bd_list_addr_lo; ++ u32 bd_list_addr_hi; ++#if defined(__BIG_ENDIAN) ++ u8 cq_index; ++ u8 reserved10; ++ u8 reserved9; ++ u8 num_bds; ++#elif defined(__LITTLE_ENDIAN) ++ u8 num_bds; ++ u8 reserved9; ++ u8 reserved10; ++ u8 cq_index; ++#endif ++}; ++ ++ ++/* ++ * iSCSI Login CQE ++ */ ++struct iscsi_login_response { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 response_flags; ++#define ISCSI_LOGIN_RESPONSE_NEXT_STAGE (0x3<<0) ++#define ISCSI_LOGIN_RESPONSE_NEXT_STAGE_SHIFT 0 ++#define ISCSI_LOGIN_RESPONSE_CURRENT_STAGE (0x3<<2) ++#define ISCSI_LOGIN_RESPONSE_CURRENT_STAGE_SHIFT 2 ++#define ISCSI_LOGIN_RESPONSE_RESERVED0 (0x3<<4) ++#define ISCSI_LOGIN_RESPONSE_RESERVED0_SHIFT 4 ++#define ISCSI_LOGIN_RESPONSE_CONT (0x1<<6) ++#define ISCSI_LOGIN_RESPONSE_CONT_SHIFT 6 ++#define ISCSI_LOGIN_RESPONSE_TRANSIT (0x1<<7) ++#define ISCSI_LOGIN_RESPONSE_TRANSIT_SHIFT 7 ++ u8 version_max; ++ u8 version_active; ++#elif defined(__LITTLE_ENDIAN) ++ u8 version_active; ++ u8 version_max; ++ u8 response_flags; ++#define ISCSI_LOGIN_RESPONSE_NEXT_STAGE (0x3<<0) ++#define ISCSI_LOGIN_RESPONSE_NEXT_STAGE_SHIFT 0 ++#define ISCSI_LOGIN_RESPONSE_CURRENT_STAGE (0x3<<2) ++#define ISCSI_LOGIN_RESPONSE_CURRENT_STAGE_SHIFT 2 ++#define ISCSI_LOGIN_RESPONSE_RESERVED0 (0x3<<4) ++#define ISCSI_LOGIN_RESPONSE_RESERVED0_SHIFT 4 ++#define ISCSI_LOGIN_RESPONSE_CONT (0x1<<6) ++#define ISCSI_LOGIN_RESPONSE_CONT_SHIFT 6 ++#define ISCSI_LOGIN_RESPONSE_TRANSIT (0x1<<7) ++#define ISCSI_LOGIN_RESPONSE_TRANSIT_SHIFT 7 ++ u8 op_code; ++#endif ++ u32 data_length; ++ u32 exp_cmd_sn; ++ u32 max_cmd_sn; ++ u32 reserved1[2]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved3; ++ u8 err_code; ++ u8 reserved2; ++#elif defined(__LITTLE_ENDIAN) ++ u8 reserved2; ++ u8 err_code; ++ u16 reserved3; ++#endif ++ u32 stat_sn; ++ u32 isid_lo; ++#if defined(__BIG_ENDIAN) ++ u16 isid_hi; ++ u16 tsih; ++#elif defined(__LITTLE_ENDIAN) ++ u16 tsih; ++ u16 isid_hi; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 status_class; ++ u8 status_detail; ++ u16 reserved4; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved4; ++ u8 status_detail; ++ u8 status_class; ++#endif ++ u32 reserved5[3]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved6; ++ u16 itt; ++#define ISCSI_LOGIN_RESPONSE_INDEX (0x3FFF<<0) ++#define ISCSI_LOGIN_RESPONSE_INDEX_SHIFT 0 ++#define ISCSI_LOGIN_RESPONSE_TYPE (0x3<<14) ++#define ISCSI_LOGIN_RESPONSE_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_LOGIN_RESPONSE_INDEX (0x3FFF<<0) ++#define ISCSI_LOGIN_RESPONSE_INDEX_SHIFT 0 ++#define ISCSI_LOGIN_RESPONSE_TYPE (0x3<<14) ++#define ISCSI_LOGIN_RESPONSE_TYPE_SHIFT 14 ++ u16 reserved6; ++#endif ++ u32 cq_req_sn; ++}; ++ ++ ++/* ++ * iSCSI Logout SQ WQE ++ */ ++struct iscsi_logout_request { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 op_attr; ++#define ISCSI_LOGOUT_REQUEST_REASON (0x7F<<0) ++#define ISCSI_LOGOUT_REQUEST_REASON_SHIFT 0 ++#define ISCSI_LOGOUT_REQUEST_ALWAYS_ONE (0x1<<7) ++#define ISCSI_LOGOUT_REQUEST_ALWAYS_ONE_SHIFT 7 ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 op_attr; ++#define ISCSI_LOGOUT_REQUEST_REASON (0x7F<<0) ++#define ISCSI_LOGOUT_REQUEST_REASON_SHIFT 0 ++#define ISCSI_LOGOUT_REQUEST_ALWAYS_ONE (0x1<<7) ++#define ISCSI_LOGOUT_REQUEST_ALWAYS_ONE_SHIFT 7 ++ u8 op_code; ++#endif ++ u32 data_length; ++ u32 reserved1[2]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved2; ++ u16 itt; ++#define ISCSI_LOGOUT_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_LOGOUT_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_LOGOUT_REQUEST_TYPE (0x3<<14) ++#define ISCSI_LOGOUT_REQUEST_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_LOGOUT_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_LOGOUT_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_LOGOUT_REQUEST_TYPE (0x3<<14) ++#define ISCSI_LOGOUT_REQUEST_TYPE_SHIFT 14 ++ u16 reserved2; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 cid; ++ u16 reserved3; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved3; ++ u16 cid; ++#endif ++ u32 cmd_sn; ++ u32 reserved4[5]; ++ u32 zero_fill; ++ u32 bd_list_addr_lo; ++ u32 bd_list_addr_hi; ++#if defined(__BIG_ENDIAN) ++ u8 cq_index; ++ u8 reserved6; ++ u8 reserved5; ++ u8 num_bds; ++#elif defined(__LITTLE_ENDIAN) ++ u8 num_bds; ++ u8 reserved5; ++ u8 reserved6; ++ u8 cq_index; ++#endif ++}; ++ ++ ++/* ++ * iSCSI Logout CQE ++ */ ++struct iscsi_logout_response { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 reserved1; ++ u8 response; ++ u8 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u8 reserved0; ++ u8 response; ++ u8 reserved1; ++ u8 op_code; ++#endif ++ u32 reserved2; ++ u32 exp_cmd_sn; ++ u32 max_cmd_sn; ++ u32 reserved3[2]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved5; ++ u8 err_code; ++ u8 reserved4; ++#elif defined(__LITTLE_ENDIAN) ++ u8 reserved4; ++ u8 err_code; ++ u16 reserved5; ++#endif ++ u32 reserved6[3]; ++#if defined(__BIG_ENDIAN) ++ u16 time_to_wait; ++ u16 time_to_retain; ++#elif defined(__LITTLE_ENDIAN) ++ u16 time_to_retain; ++ u16 time_to_wait; ++#endif ++ u32 reserved7[3]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved8; ++ u16 itt; ++#define ISCSI_LOGOUT_RESPONSE_INDEX (0x3FFF<<0) ++#define ISCSI_LOGOUT_RESPONSE_INDEX_SHIFT 0 ++#define ISCSI_LOGOUT_RESPONSE_TYPE (0x3<<14) ++#define ISCSI_LOGOUT_RESPONSE_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_LOGOUT_RESPONSE_INDEX (0x3FFF<<0) ++#define ISCSI_LOGOUT_RESPONSE_INDEX_SHIFT 0 ++#define ISCSI_LOGOUT_RESPONSE_TYPE (0x3<<14) ++#define ISCSI_LOGOUT_RESPONSE_TYPE_SHIFT 14 ++ u16 reserved8; ++#endif ++ u32 cq_req_sn; ++}; ++ ++ ++/* ++ * iSCSI Nop-In CQE ++ */ ++struct iscsi_nop_in_msg { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 reserved1; ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 reserved1; ++ u8 op_code; ++#endif ++ u32 data_length; ++ u32 exp_cmd_sn; ++ u32 max_cmd_sn; ++ u32 ttt; ++ u32 reserved2; ++#if defined(__BIG_ENDIAN) ++ u16 reserved4; ++ u8 err_code; ++ u8 reserved3; ++#elif defined(__LITTLE_ENDIAN) ++ u8 reserved3; ++ u8 err_code; ++ u16 reserved4; ++#endif ++ u32 reserved5; ++ u32 lun[2]; ++ u32 reserved6[4]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved7; ++ u16 itt; ++#define ISCSI_NOP_IN_MSG_INDEX (0x3FFF<<0) ++#define ISCSI_NOP_IN_MSG_INDEX_SHIFT 0 ++#define ISCSI_NOP_IN_MSG_TYPE (0x3<<14) ++#define ISCSI_NOP_IN_MSG_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_NOP_IN_MSG_INDEX (0x3FFF<<0) ++#define ISCSI_NOP_IN_MSG_INDEX_SHIFT 0 ++#define ISCSI_NOP_IN_MSG_TYPE (0x3<<14) ++#define ISCSI_NOP_IN_MSG_TYPE_SHIFT 14 ++ u16 reserved7; ++#endif ++ u32 cq_req_sn; ++}; ++ ++ ++/* ++ * iSCSI NOP-OUT SQ WQE ++ */ ++struct iscsi_nop_out_request { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 op_attr; ++#define ISCSI_NOP_OUT_REQUEST_RESERVED1 (0x7F<<0) ++#define ISCSI_NOP_OUT_REQUEST_RESERVED1_SHIFT 0 ++#define ISCSI_NOP_OUT_REQUEST_ALWAYS_ONE (0x1<<7) ++#define ISCSI_NOP_OUT_REQUEST_ALWAYS_ONE_SHIFT 7 ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 op_attr; ++#define ISCSI_NOP_OUT_REQUEST_RESERVED1 (0x7F<<0) ++#define ISCSI_NOP_OUT_REQUEST_RESERVED1_SHIFT 0 ++#define ISCSI_NOP_OUT_REQUEST_ALWAYS_ONE (0x1<<7) ++#define ISCSI_NOP_OUT_REQUEST_ALWAYS_ONE_SHIFT 7 ++ u8 op_code; ++#endif ++ u32 data_length; ++ u32 lun[2]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved2; ++ u16 itt; ++#define ISCSI_NOP_OUT_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_NOP_OUT_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_NOP_OUT_REQUEST_TYPE (0x3<<14) ++#define ISCSI_NOP_OUT_REQUEST_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_NOP_OUT_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_NOP_OUT_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_NOP_OUT_REQUEST_TYPE (0x3<<14) ++#define ISCSI_NOP_OUT_REQUEST_TYPE_SHIFT 14 ++ u16 reserved2; ++#endif ++ u32 ttt; ++ u32 cmd_sn; ++ u32 reserved3[2]; ++ u32 resp_bd_list_addr_lo; ++ u32 resp_bd_list_addr_hi; ++ u32 resp_buffer; ++#define ISCSI_NOP_OUT_REQUEST_RESP_BUFFER_LENGTH (0xFFFFFF<<0) ++#define ISCSI_NOP_OUT_REQUEST_RESP_BUFFER_LENGTH_SHIFT 0 ++#define ISCSI_NOP_OUT_REQUEST_NUM_RESP_BDS (0xFF<<24) ++#define ISCSI_NOP_OUT_REQUEST_NUM_RESP_BDS_SHIFT 24 ++#if defined(__BIG_ENDIAN) ++ u16 reserved7; ++ u8 reserved6; ++ u8 flags; ++#define ISCSI_NOP_OUT_REQUEST_RESERVED4 (0x1<<0) ++#define ISCSI_NOP_OUT_REQUEST_RESERVED4_SHIFT 0 ++#define ISCSI_NOP_OUT_REQUEST_LOCAL_COMPLETION (0x1<<1) ++#define ISCSI_NOP_OUT_REQUEST_LOCAL_COMPLETION_SHIFT 1 ++#define ISCSI_NOP_OUT_REQUEST_ZERO_FILL (0x3F<<2) ++#define ISCSI_NOP_OUT_REQUEST_ZERO_FILL_SHIFT 2 ++#elif defined(__LITTLE_ENDIAN) ++ u8 flags; ++#define ISCSI_NOP_OUT_REQUEST_RESERVED4 (0x1<<0) ++#define ISCSI_NOP_OUT_REQUEST_RESERVED4_SHIFT 0 ++#define ISCSI_NOP_OUT_REQUEST_LOCAL_COMPLETION (0x1<<1) ++#define ISCSI_NOP_OUT_REQUEST_LOCAL_COMPLETION_SHIFT 1 ++#define ISCSI_NOP_OUT_REQUEST_ZERO_FILL (0x3F<<2) ++#define ISCSI_NOP_OUT_REQUEST_ZERO_FILL_SHIFT 2 ++ u8 reserved6; ++ u16 reserved7; ++#endif ++ u32 bd_list_addr_lo; ++ u32 bd_list_addr_hi; ++#if defined(__BIG_ENDIAN) ++ u8 cq_index; ++ u8 reserved9; ++ u8 reserved8; ++ u8 num_bds; ++#elif defined(__LITTLE_ENDIAN) ++ u8 num_bds; ++ u8 reserved8; ++ u8 reserved9; ++ u8 cq_index; ++#endif ++}; ++ ++ ++ ++ ++/* ++ * iSCSI Reject CQE ++ */ ++struct iscsi_reject_msg { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 reserved1; ++ u8 reason; ++ u8 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u8 reserved0; ++ u8 reason; ++ u8 reserved1; ++ u8 op_code; ++#endif ++ u32 data_length; ++ u32 exp_cmd_sn; ++ u32 max_cmd_sn; ++ u32 reserved2[2]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved4; ++ u8 err_code; ++ u8 reserved3; ++#elif defined(__LITTLE_ENDIAN) ++ u8 reserved3; ++ u8 err_code; ++ u16 reserved4; ++#endif ++ u32 reserved5[8]; ++ u32 cq_req_sn; ++}; ++ ++ ++/* ++ * iSCSI TMF SQ WQE ++ */ ++struct iscsi_tmf_request { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 op_attr; ++#define ISCSI_TMF_REQUEST_FUNCTION (0x7F<<0) ++#define ISCSI_TMF_REQUEST_FUNCTION_SHIFT 0 ++#define ISCSI_TMF_REQUEST_ALWAYS_ONE (0x1<<7) ++#define ISCSI_TMF_REQUEST_ALWAYS_ONE_SHIFT 7 ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 op_attr; ++#define ISCSI_TMF_REQUEST_FUNCTION (0x7F<<0) ++#define ISCSI_TMF_REQUEST_FUNCTION_SHIFT 0 ++#define ISCSI_TMF_REQUEST_ALWAYS_ONE (0x1<<7) ++#define ISCSI_TMF_REQUEST_ALWAYS_ONE_SHIFT 7 ++ u8 op_code; ++#endif ++ u32 data_length; ++ u32 lun[2]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved1; ++ u16 itt; ++#define ISCSI_TMF_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_TMF_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_TMF_REQUEST_TYPE (0x3<<14) ++#define ISCSI_TMF_REQUEST_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_TMF_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_TMF_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_TMF_REQUEST_TYPE (0x3<<14) ++#define ISCSI_TMF_REQUEST_TYPE_SHIFT 14 ++ u16 reserved1; ++#endif ++ u32 ref_itt; ++ u32 cmd_sn; ++ u32 reserved2; ++ u32 ref_cmd_sn; ++ u32 reserved3[3]; ++ u32 zero_fill; ++ u32 bd_list_addr_lo; ++ u32 bd_list_addr_hi; ++#if defined(__BIG_ENDIAN) ++ u8 cq_index; ++ u8 reserved5; ++ u8 reserved4; ++ u8 num_bds; ++#elif defined(__LITTLE_ENDIAN) ++ u8 num_bds; ++ u8 reserved4; ++ u8 reserved5; ++ u8 cq_index; ++#endif ++}; ++ ++/* ++ * iSCSI Text SQ WQE ++ */ ++struct iscsi_text_request { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 op_attr; ++#define ISCSI_TEXT_REQUEST_RESERVED1 (0x3F<<0) ++#define ISCSI_TEXT_REQUEST_RESERVED1_SHIFT 0 ++#define ISCSI_TEXT_REQUEST_CONT (0x1<<6) ++#define ISCSI_TEXT_REQUEST_CONT_SHIFT 6 ++#define ISCSI_TEXT_REQUEST_FINAL (0x1<<7) ++#define ISCSI_TEXT_REQUEST_FINAL_SHIFT 7 ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 op_attr; ++#define ISCSI_TEXT_REQUEST_RESERVED1 (0x3F<<0) ++#define ISCSI_TEXT_REQUEST_RESERVED1_SHIFT 0 ++#define ISCSI_TEXT_REQUEST_CONT (0x1<<6) ++#define ISCSI_TEXT_REQUEST_CONT_SHIFT 6 ++#define ISCSI_TEXT_REQUEST_FINAL (0x1<<7) ++#define ISCSI_TEXT_REQUEST_FINAL_SHIFT 7 ++ u8 op_code; ++#endif ++ u32 data_length; ++ u32 lun[2]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved3; ++ u16 itt; ++#define ISCSI_TEXT_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_TEXT_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_TEXT_REQUEST_TYPE (0x3<<14) ++#define ISCSI_TEXT_REQUEST_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_TEXT_REQUEST_INDEX (0x3FFF<<0) ++#define ISCSI_TEXT_REQUEST_INDEX_SHIFT 0 ++#define ISCSI_TEXT_REQUEST_TYPE (0x3<<14) ++#define ISCSI_TEXT_REQUEST_TYPE_SHIFT 14 ++ u16 reserved3; ++#endif ++ u32 ttt; ++ u32 cmd_sn; ++ u32 reserved4[2]; ++ u32 resp_bd_list_addr_lo; ++ u32 resp_bd_list_addr_hi; ++ u32 resp_buffer; ++#define ISCSI_TEXT_REQUEST_RESP_BUFFER_LENGTH (0xFFFFFF<<0) ++#define ISCSI_TEXT_REQUEST_RESP_BUFFER_LENGTH_SHIFT 0 ++#define ISCSI_TEXT_REQUEST_NUM_RESP_BDS (0xFF<<24) ++#define ISCSI_TEXT_REQUEST_NUM_RESP_BDS_SHIFT 24 ++ u32 zero_fill; ++ u32 bd_list_addr_lo; ++ u32 bd_list_addr_hi; ++#if defined(__BIG_ENDIAN) ++ u8 cq_index; ++ u8 reserved7; ++ u8 reserved6; ++ u8 num_bds; ++#elif defined(__LITTLE_ENDIAN) ++ u8 num_bds; ++ u8 reserved6; ++ u8 reserved7; ++ u8 cq_index; ++#endif ++}; ++ ++/* ++ * iSCSI SQ WQE ++ */ ++union iscsi_request { ++ struct iscsi_cmd_request cmd; ++ struct iscsi_tmf_request tmf; ++ struct iscsi_nop_out_request nop_out; ++ struct iscsi_login_request login_req; ++ struct iscsi_text_request text; ++ struct iscsi_logout_request logout_req; ++ struct iscsi_cleanup_request cleanup; ++}; ++ ++ ++/* ++ * iSCSI TMF CQE ++ */ ++struct iscsi_tmf_response { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 reserved1; ++ u8 response; ++ u8 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u8 reserved0; ++ u8 response; ++ u8 reserved1; ++ u8 op_code; ++#endif ++ u32 reserved2; ++ u32 exp_cmd_sn; ++ u32 max_cmd_sn; ++ u32 reserved3[2]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved5; ++ u8 err_code; ++ u8 reserved4; ++#elif defined(__LITTLE_ENDIAN) ++ u8 reserved4; ++ u8 err_code; ++ u16 reserved5; ++#endif ++ u32 reserved6[7]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved7; ++ u16 itt; ++#define ISCSI_TMF_RESPONSE_INDEX (0x3FFF<<0) ++#define ISCSI_TMF_RESPONSE_INDEX_SHIFT 0 ++#define ISCSI_TMF_RESPONSE_TYPE (0x3<<14) ++#define ISCSI_TMF_RESPONSE_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_TMF_RESPONSE_INDEX (0x3FFF<<0) ++#define ISCSI_TMF_RESPONSE_INDEX_SHIFT 0 ++#define ISCSI_TMF_RESPONSE_TYPE (0x3<<14) ++#define ISCSI_TMF_RESPONSE_TYPE_SHIFT 14 ++ u16 reserved7; ++#endif ++ u32 cq_req_sn; ++}; ++ ++/* ++ * iSCSI Text CQE ++ */ ++struct iscsi_text_response { ++#if defined(__BIG_ENDIAN) ++ u8 op_code; ++ u8 response_flags; ++#define ISCSI_TEXT_RESPONSE_RESERVED1 (0x3F<<0) ++#define ISCSI_TEXT_RESPONSE_RESERVED1_SHIFT 0 ++#define ISCSI_TEXT_RESPONSE_CONT (0x1<<6) ++#define ISCSI_TEXT_RESPONSE_CONT_SHIFT 6 ++#define ISCSI_TEXT_RESPONSE_FINAL (0x1<<7) ++#define ISCSI_TEXT_RESPONSE_FINAL_SHIFT 7 ++ u16 reserved0; ++#elif defined(__LITTLE_ENDIAN) ++ u16 reserved0; ++ u8 response_flags; ++#define ISCSI_TEXT_RESPONSE_RESERVED1 (0x3F<<0) ++#define ISCSI_TEXT_RESPONSE_RESERVED1_SHIFT 0 ++#define ISCSI_TEXT_RESPONSE_CONT (0x1<<6) ++#define ISCSI_TEXT_RESPONSE_CONT_SHIFT 6 ++#define ISCSI_TEXT_RESPONSE_FINAL (0x1<<7) ++#define ISCSI_TEXT_RESPONSE_FINAL_SHIFT 7 ++ u8 op_code; ++#endif ++ u32 data_length; ++ u32 exp_cmd_sn; ++ u32 max_cmd_sn; ++ u32 ttt; ++ u32 reserved2; ++#if defined(__BIG_ENDIAN) ++ u16 reserved4; ++ u8 err_code; ++ u8 reserved3; ++#elif defined(__LITTLE_ENDIAN) ++ u8 reserved3; ++ u8 err_code; ++ u16 reserved4; ++#endif ++ u32 reserved5; ++ u32 lun[2]; ++ u32 reserved6[4]; ++#if defined(__BIG_ENDIAN) ++ u16 reserved7; ++ u16 itt; ++#define ISCSI_TEXT_RESPONSE_INDEX (0x3FFF<<0) ++#define ISCSI_TEXT_RESPONSE_INDEX_SHIFT 0 ++#define ISCSI_TEXT_RESPONSE_TYPE (0x3<<14) ++#define ISCSI_TEXT_RESPONSE_TYPE_SHIFT 14 ++#elif defined(__LITTLE_ENDIAN) ++ u16 itt; ++#define ISCSI_TEXT_RESPONSE_INDEX (0x3FFF<<0) ++#define ISCSI_TEXT_RESPONSE_INDEX_SHIFT 0 ++#define ISCSI_TEXT_RESPONSE_TYPE (0x3<<14) ++#define ISCSI_TEXT_RESPONSE_TYPE_SHIFT 14 ++ u16 reserved7; ++#endif ++ u32 cq_req_sn; ++}; ++ ++/* ++ * iSCSI CQE ++ */ ++union iscsi_response { ++ struct iscsi_cmd_response cmd; ++ struct iscsi_tmf_response tmf; ++ struct iscsi_login_response login_resp; ++ struct iscsi_text_response text; ++ struct iscsi_logout_response logout_resp; ++ struct iscsi_cleanup_response cleanup; ++ struct iscsi_reject_msg reject; ++ struct iscsi_async_msg async; ++ struct iscsi_nop_in_msg nop_in; ++}; ++ ++ ++ ++ ++ ++ ++#endif /* __57XX_ISCSI_HSI_LINUX_LE__ */ +diff -r ffba7e1f063a drivers/scsi/bnx2i/Kconfig +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/bnx2i/Kconfig Wed Aug 05 10:51:49 2009 +0100 +@@ -0,0 +1,7 @@ ++config SCSI_BNX2_ISCSI ++ tristate "Broadcom NetXtreme II iSCSI support" ++ select CNIC ++ select SCSI_ISCSI_ATTRS ++ ---help--- ++ This driver supports iSCSI offload for the Broadcom NetXtreme II ++ devices. +diff -r ffba7e1f063a drivers/scsi/bnx2i/Makefile +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/bnx2i/Makefile Wed Aug 05 10:51:49 2009 +0100 +@@ -0,0 +1,8 @@ ++bnx2i-y := bnx2i_init.o bnx2i_hwi.o bnx2i_iscsi.o bnx2i_sysfs.o ++ ++obj-$(CONFIG_SCSI_BNX2_ISCSI) += bnx2i.o ++ ++EXTRA_CFLAGS += -I$(srctree)/drivers/net ++EXTRA_CFLAGS += -D_SYSFS_INCL_ ++EXTRA_CFLAGS += -D__BNX2I_CONN_WORKER__ ++EXTRA_CFLAGS += -D_CREATE_SESS_NEW_ +diff -r ffba7e1f063a drivers/scsi/bnx2i/bnx2i.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/bnx2i/bnx2i.h Wed Aug 05 10:51:49 2009 +0100 +@@ -0,0 +1,1381 @@ ++/* bnx2i.h: Broadcom NetXtreme II iSCSI driver. ++ * ++ * Copyright (c) 2006 - 2009 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ * ++ * Written by: Anil Veerabhadrappa (anilgv@broadcom.com) ++ */ ++ ++#ifndef _BNX2I_H_ ++#define _BNX2I_H_ ++ ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifndef __VMKLNX__ ++#include ++#include ++#endif ++ ++#include ++#include ++#include ++#ifdef __VMKLNX__ ++#include ++#endif ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23) ++#include ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++#include "../../net/cnic_if.h" ++#else ++#include ++#endif ++#include "57xx_iscsi_hsi.h" ++#include "57xx_iscsi_constants.h" ++#include "bnx2i_ioctl.h" ++ ++#define BNX2_ISCSI_DRIVER_NAME "bnx2i" ++ ++#ifndef PCI_DEVICE_ID_NX2_5709 ++#define PCI_DEVICE_ID_NX2_5709 0x1639 ++#endif ++ ++#ifndef PCI_DEVICE_ID_NX2_5709S ++#define PCI_DEVICE_ID_NX2_5709S 0x163a ++#endif ++ ++#ifndef PCI_DEVICE_ID_NX2_57710 ++#define PCI_DEVICE_ID_NX2_57710 0x164e ++#endif ++ ++#ifndef PCI_DEVICE_ID_NX2_57711 ++#define PCI_DEVICE_ID_NX2_57711 0x164f ++#endif ++ ++#ifndef PCI_DEVICE_ID_NX2_57711E ++#define PCI_DEVICE_ID_NX2_57711E 0x1650 ++#endif ++ ++#define BNX2I_REGISTER_HBA_SUPPORTED 0 ++#define BNX2I_REGISTER_HBA_FORCED 1 ++ ++#define ISCSI_MAX_ADAPTERS 8 ++#define ISCSI_MAX_CONNS_PER_HBA 128 ++#define ISCSI_MAX_SESS_PER_HBA ISCSI_MAX_CONNS_PER_HBA ++#define ISCSI_MAX_CMDS_PER_SESS 128 ++ ++#define ISCSI_MAX_BDS_PER_CMD 32 ++ ++#define MAX_PAGES_PER_CTRL_STRUCT_POOL 16 ++#define BNX2I_RESERVED_SLOW_PATH_CMD_SLOTS 4 ++ ++/* 5706/08 hardware has limit on maximum buffer size per BD it can handle */ ++#define MAX_BD_LENGTH 65535 ++#define BD_SPLIT_SIZE 32768 ++ ++/* min, max & default values for SQ/RQ/CQ size, configurable via' modparam */ ++#define BNX2I_SQ_WQES_MIN 16 ++#define BNX2I_570X_SQ_WQES_MAX 128 ++#define BNX2I_5770X_SQ_WQES_MAX 512 ++#ifdef __VMKLNX__ ++#define BNX2I_570X_SQ_WQES_DEFAULT 32 ++#define BNX2I_5709_SQ_WQES_DEFAULT 64 ++#define BNX2I_5770X_SQ_WQES_DEFAULT 128 ++#else ++#define BNX2I_570X_SQ_WQES_DEFAULT 128 ++#define BNX2I_5770X_SQ_WQES_DEFAULT 256 ++#endif ++#define BNX2I_5770X_SQ_WQES_DEFAULT_X86 64 ++ ++#define BNX2I_CQ_WQES_MIN 16 ++#define BNX2I_CQ_WQES_MAX 256 ++#define BNX2I_CQ_WQES_DEFAULT 128 ++ ++#define BNX2I_RQ_WQES_MIN 16 ++#define BNX2I_RQ_WQES_MAX 32 ++#define BNX2I_RQ_WQES_DEFAULT 16 ++ ++/* CCELLs per conn */ ++#define BNX2I_CCELLS_MIN 16 ++#define BNX2I_CCELLS_MAX 96 ++#define BNX2I_CCELLS_DEFAULT 64 ++ ++#define ISCSI_CONN_LOGIN_BUF_SIZE 16384 ++#define ITT_INVALID_SIGNATURE 0xFFFF ++ ++#define ISCSI_CMD_CLEANUP_TIMEOUT 100 ++ ++#define BNX2I_CONN_CTX_BUF_SIZE 16384 ++ ++#define BNX2I_SQ_WQE_SIZE 64 ++#define BNX2I_RQ_WQE_SIZE 256 ++#define BNX2I_CQE_SIZE 64 ++ ++#define MB_KERNEL_CTX_SHIFT 8 ++#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) ++ ++#define CTX_SHIFT 7 ++#define GET_CID_NUM(cid_addr) ((cid_addr) >> CTX_SHIFT) ++ ++#define CTX_OFFSET 0x10000 ++#define MAX_CID_CNT 0x4000 ++ ++#define BNX2_TXP_SCRATCH 0x00060000 ++#define BNX2_TPAT_SCRATCH 0x000a0000 ++#define BNX2_RXP_SCRATCH 0x000e0000 ++#define BNX2_COM_SCRATCH 0x00120000 ++#define BNX2_CP_SCRATCH 0x001a0000 ++ ++#define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078 ++#define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL (0xfffffL<<2) ++#define BNX2_PCICFG_REG_WINDOW 0x00000080 ++ ++/* 5709 context registers */ ++#define BNX2_MQ_CONFIG2 0x00003d00 ++#define BNX2_MQ_CONFIG2_CONT_SZ (0x7L<<4) ++#define BNX2_MQ_CONFIG2_FIRST_L4L5 (0x1fL<<8) ++ ++/* 57710's BAR2 is mapped to doorbell registers */ ++#define BNX2X_DOORBELL_PCI_BAR 2 ++#define BNX2X_MAX_CQS 8 ++ ++#ifndef DMA_64BIT_MASK ++#define DMA_64BIT_MASK ((u64) 0xffffffffffffffffULL) ++#define DMA_32BIT_MASK ((u64) 0x00000000ffffffffULL) ++#endif ++ ++#ifndef DMA_40BIT_MASK ++#define DMA_40BIT_MASK ((u64) 0x000000ffffffffffULL) ++#endif ++ ++#define CNIC_ARM_CQE 1 ++#define CNIC_DISARM_CQE 0 ++ ++#define BNX2I_TBL_TYPE_NONE 0 ++#define BNX2I_TBL_TYPE_PG 1 ++#define BNX2I_TBL_TYPE_BD 2 ++#define REG_RD(__hba, offset) \ ++ readl(__hba->regview + offset) ++#define REG_WR(__hba, offset, val) \ ++ writel(val, __hba->regview + offset) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ ++#define scsi_sg_count(cmd) ((cmd)->use_sg) ++#define scsi_sglist(cmd) ((struct scatterlist *)(cmd)->request_buffer) ++#define scsi_bufflen(cmd) ((cmd)->request_bufflen) ++ ++#ifdef __VMKLNX__ ++#undef _DEFINE_SCSI_SET_RESID ++#define _DEFINE_SCSI_GET_RESID 1 ++#endif ++ ++struct bnx2i_hba; ++struct bnx2i_sess; ++struct bnx2i_conn; ++ ++#ifdef _DEFINE_SCSI_SET_RESID ++static inline void scsi_set_resid(struct scsi_cmnd *cmd, int resid) ++{ ++ cmd->resid = resid; ++} ++#endif ++ ++#ifdef _DEFINE_SCSI_GET_RESID ++static inline int scsi_get_resid(struct scsi_cmnd *cmd) ++{ ++ return cmd->resid; ++} ++#endif ++ ++#define scsi_for_each_sg(cmd, sg, nseg, __i) \ ++ for (__i = 0, sg = scsi_sglist(cmd); __i < (nseg); __i++, (sg)++) ++ ++#endif ++ ++struct bnx2i_dma { ++ struct list_head link; ++ int size; ++ char *mem; ++ dma_addr_t mapping; ++ int pgtbl_type; ++ int pgtbl_size; ++ char *pgtbl; ++ dma_addr_t pgtbl_map; ++}; ++ ++/** ++ * struct bd_resc_page - tracks DMA'able memory allocated for BD tables ++ * ++ * @link: list head to link elements ++ * @max_ptrs: maximun pointers that can be stored in this page ++ * @num_valid: number of pointer valid in this page ++ * @page: base addess for page pointer array ++ * ++ * structure to track DMA'able memory allocated for command BD tables ++ */ ++struct bd_resc_page { ++ struct list_head link; ++ u32 max_ptrs; ++ u32 num_valid; ++ void *page[1]; ++}; ++ ++/** ++ * struct io_bdt - I/O buffer destricptor table ++ * ++ * @link: list head to link elements ++ * @bd_tbl: BD table's virtual address ++ * @bd_tbl_dma: BD table's dma address ++ * @cmdp: command structure this BD is allocated ++ * @max_bd_cnt: max BD entries in this table ++ * @bd_valid: num valid BD entries ++ * ++ * IO BD table ++ */ ++struct io_bdt { ++ struct list_head link; ++ struct iscsi_bd *bd_tbl; ++ dma_addr_t bd_tbl_dma; ++ struct bnx2i_cmd *cmdp; ++ u16 max_bd_cnt; ++ u16 bd_valid; ++}; ++ ++/** ++ * struct generic_pdu_resc - login pdu resource structure ++ * ++ * @pdu_hdr: buffer to copy iscsi header prepared by 'iscsid' ++ * @cmd: iSCSI command pointer ++ * @login_itt: iSCSI ITT to be used with login exchanges ++ * @req_buf: driver buffer used to stage payload associated with ++ * the login request ++ * @req_dma_addr: dma address for iscsi login request payload buffer ++ * @req_buf_size: actual login request payload length ++ * @req_wr_ptr: pointer into login request buffer when next data is ++ * to be written ++ * @resp_hdr: iscsi header where iscsi login response header is to ++ * be recreated ++ * @resp_buf: buffer to stage login response payload ++ * @resp_dma_addr: login response payload buffer dma address ++ * @resp_buf_size: login response paylod length ++ * @resp_wr_ptr: pointer into login response buffer when next data is ++ * to be written ++ * @req_bd_tbl: BD table to indicate login request payload buffer details ++ * @req_bd_dma: login request BD table dma address ++ * @resp_bd_tbl: BD table to indicate login response payload buffer details ++ * @resp_bd_dma: login request BD table dma address ++ * ++ * following structure defines buffer info for generic pdus such as iSCSI Login, ++ * Logout and NOP ++ */ ++struct generic_pdu_resc { ++ struct iscsi_hdr pdu_hdr; ++ u32 login_itt; ++ struct bnx2i_dma login_req; ++#define req_buf login_req.mem ++ u32 req_buf_size; ++ char *req_wr_ptr; ++ struct iscsi_hdr resp_hdr; ++ struct bnx2i_dma login_resp; ++#define resp_buf login_resp.mem ++ u32 resp_buf_size; ++ char *resp_wr_ptr; ++ struct iscsi_hdr nopout_hdr; ++ struct iscsi_hdr nopin_hdr; ++ struct iscsi_hdr async_hdr; ++}; ++ ++ ++/** ++ * bnx2i_cmd - iscsi command structure ++ * ++ * @link: list head to link elements ++ * @iscsi_opcode: iscsi command opcode, NOPIN, LOGIN, SCSICMD, etc' ++ * @cmd_state: command state tracking flag ++ * @scsi_status_rcvd: flag determines whether SCSI response is received ++ * for this task or not ++ * @scsi_cmd: SCSI-ML task pointer corresponding to this iscsi cmd ++ * @tmf_ref_itt: reference ITT of the command being aborted ++ * @tmf_ref_cmd: pointer of the command being aborted by this command ++ * @tmf_ref_sc: SCSI-ML's task pointer of aborted command ++ * @sg: SG list ++ * @bd_tbl: buffer descriptor (BD) table ++ * @bd_tbl_dma: buffer descriptor (BD) table's dma address ++ */ ++struct bnx2i_cmd { ++ struct list_head link; ++ u8 iscsi_opcode; ++ u8 rsvd1; ++ u16 itt; ++ atomic_t cmd_state; ++ #define ISCSI_CMD_STATE_FREED 0x000 ++ #define ISCSI_CMD_STATE_INITIATED 0x001 ++ #define ISCSI_CMD_STATE_ABORT_REQ 0x002 ++ #define ISCSI_CMD_STATE_ABORT_PEND 0x004 ++ #define ISCSI_CMD_STATE_ABORT_COMPL 0x008 ++ #define ISCSI_CMD_STATE_CLEANUP_START 0x010 ++ #define ISCSI_CMD_STATE_CLEANUP_PEND 0x020 ++ #define ISCSI_CMD_STATE_CLEANUP_CMPL 0x040 ++ #define ISCSI_CMD_STATE_FAILED 0x100 ++ #define ISCSI_CMD_STATE_TMF_TIMEOUT 0x200 ++ #define ISCSI_CMD_STATE_CMPL_RCVD 0x400 ++ #define ISCSI_CMD_STATE_COMPLETED 0x800 ++ int scsi_status_rcvd; ++ ++ struct bnx2i_conn *conn; ++ struct scsi_cmnd *scsi_cmd; ++ struct scatterlist *sg; ++ struct io_bdt *bd_tbl; ++ dma_addr_t bd_tbl_dma; ++ u32 reserved0; ++ ++ struct iscsi_cmd_request req; ++ /* TMF RELATED */ ++ u8 tmf_func; ++ u8 tmf_response; ++ int tmf_lun; ++ u32 tmf_ref_itt; ++ struct bnx2i_cmd *tmf_ref_cmd; ++ struct scsi_cmnd *tmf_ref_sc; ++ int failed_reason; ++ /* useful for nop-in processing */ ++ u32 ttt; ++ ++}; ++ ++ ++/* ++ * TCP port manager ++ */ ++struct tcp_port_mngt { ++ int num_required; ++ u32 port_tbl_size; ++ u32 num_free_ports; ++ u32 prod_idx; ++ u32 cons_idx; ++ u32 max_idx; ++ u16 *free_q; ++}; ++ ++struct bnx2i_scsi_task { ++ struct list_head link; ++ struct scsi_cmnd *scsi_cmd; ++}; ++ ++/** ++ * struct bnx2i_conn - iscsi connection structure ++ * ++ * @link: list head to link elements ++ * @sess: iscsi session pointer ++ * @cls_conn: pointer to iscsi cls conn ++ * @state: flag to trace command state ++ * @stop_state: stop state request by open-iscsi ++ * @stage: iscsi login state ++ * @in_shutdown: flags to indicate connection is in shutdown mode ++ * @lead_conn: lead iscsi connection of session ++ * @conn_cid: iscsi cid per rfc ++ * @exp_statsn: iscsi expected statsn ++ * @header_digest_en: header digest parameter ++ * @data_digest_en: data digest parameter ++ * @max_data_seg_len_xmit: iscsi initiator's mrdsl ++ * @max_data_seg_len_recv: iscsi target's mrdsl ++ * @ifmarker_enable: ifmarker parameter ++ * @ofmarker_enable: ofmarker parameter ++ * @persist_port: iscsi target side TCP port number ++ * @persist_address: iscsi target's IP address ++ * @iscsi_conn_cid: iscsi conn id ++ * @fw_cid: firmware iscsi context id ++ * @lock: lock to synchronize access ++ * @ep: endpoint structure pointer ++ * @gen_pdu: login/nopout/logout pdu resources ++ * @nopout_num_scsi_cmds: scsi cmds issue counter to detect idle link ++ * @total_data_octets_sent:conn stats - data bytes sent on this conn ++ * @total_data_octets_rcvd:conn stats - data bytes received on this conn ++ * @num_login_req_pdus: conn stats - num login pdus sent ++ * @num_login_resp_pdus: conn stats - num login pdus received ++ * @num_scsi_cmd_pdus: conn stats - num scsicmd pdus sent ++ * @num_scsi_resp_pdus: conn stats - num scsicmd pdus received ++ * @num_nopout_pdus: conn stats - num nopout pdus sent ++ * @num_nopin_pdus conn stats - num nopout pdus received: ++ * @num_reject_pdus: conn stats - num reject pdus received ++ * @num_async_pdus: conn stats - num async pdus received ++ * @num_dataout_pdus: conn stats - num dout pdus sent ++ * @num_r2t_pdus: conn stats - num r2t pdus received ++ * @num_datain_pdus: conn stats - num din pdus received ++ * @num_snack_pdus: conn stats - num snack pdus received ++ * @num_text_req_pdus: conn stats - num text pdus sent ++ * @num_text_resp_pdus: conn stats - num text pdus received ++ * @num_tmf_req_pdus: conn stats - num tmf pdus sent ++ * @num_tmf_resp_pdus: conn stats - num tmf pdus received ++ * @num_logout_req_pdus: conn stats - num logout pdus sent ++ * @num_logout_resp_pdus: conn stats - num logout pdus received ++ * ++ * iSCSI connection structure ++ */ ++struct bnx2i_conn { ++ struct list_head link; ++ struct bnx2i_sess *sess; ++ struct iscsi_cls_conn *cls_conn; ++ ++ u32 state; ++ #define CONN_STATE_IDLE 0x00 ++ #define CONN_STATE_XPORT_READY 0x01 ++ #define CONN_STATE_IN_LOGIN 0x02 ++ #define CONN_STATE_FFP_STATE 0x04 ++ #define CONN_STATE_IN_LOGOUT 0x08 ++ #define CONN_STATE_IN_CLEANUP 0x10 ++ #define CONN_STATE_XPORT_FREEZE 0x20 ++ #define CONN_STATE_STOPPED 0x80 ++ atomic_t stop_state; ++ u32 stage; ++ u32 in_shutdown; ++ ++ u32 lead_conn; ++ u32 conn_cid; ++ ++ int poll_timer_enabled; ++ struct timer_list poll_timer; ++ void (*ring_doorbell)(struct bnx2i_conn *); ++ /* ++ * Following are iSCSI sequencing & operational parameters ++ */ ++ u32 exp_statsn; ++ #define STATSN_UPDATE_SIGNATURE 0xFABCAFE ++ u32 header_digest_en; ++ u32 data_digest_en; ++ u32 max_data_seg_len_xmit; /* Target */ ++ u32 max_data_seg_len_recv; /* Initiator */ ++ int ifmarker_enable; ++ int ofmarker_enable; ++ int persist_port; ++ char *persist_address; ++ ++ u32 iscsi_conn_cid; ++ #define BNX2I_CID_RESERVED 0x5AFF ++ u32 fw_cid; ++ ++ /* ++ * Queue Pair (QP) related structure elements. ++ */ ++ struct bnx2i_endpoint *ep; ++ ++ atomic_t worker_running; ++ atomic_t worker_enabled; ++ atomic_t worker_enabled_cnt; ++ atomic_t worker_disabled_cnt; ++#ifdef __VMKLNX__ ++ struct tasklet_struct conn_tasklet; ++ char isid[13]; ++#else ++ struct work_struct conn_worker; ++#endif ++/* DEBUG ONLY */ ++ u32 tasklet_freeze; ++ int tasklet_state; ++ int tasklet_tmf_exit; ++ int tasklet_timeslice_exit; ++ int tasklet_reschedule; ++ int tasklet_entry; ++ int cqe_process_state; ++ unsigned long cqe_process_jiffies; ++ int tasklet_loop; ++ unsigned long que_jiff; ++ unsigned long cqe_jiff; ++ unsigned long task_jiff; ++ ++ /* ++ * Buffer for login negotiation process ++ */ ++ struct generic_pdu_resc gen_pdu; ++ ++ u32 nopout_num_scsi_cmds; ++ /* ++ * Connection Statistics ++ */ ++ u64 total_data_octets_sent; ++ u64 total_data_octets_rcvd; ++ u32 num_login_req_pdus; ++ u32 num_login_resp_pdus; ++ u32 num_scsi_cmd_pdus; ++ u32 num_scsi_resp_pdus; ++ u32 num_nopout_pdus; ++ u32 num_nopin_pdus; ++ u32 num_reject_pdus; ++ u32 num_async_pdus; ++ u32 num_dataout_pdus; ++ u32 num_r2t_pdus; ++ u32 num_datain_pdus; ++ u32 num_snack_pdus; ++ u32 num_text_req_pdus; ++ u32 num_text_resp_pdus; ++ u32 num_tmf_req_pdus; ++ u32 num_tmf_resp_pdus; ++ u32 num_logout_req_pdus; ++ u32 num_logout_resp_pdus; ++}; ++ ++ ++ ++/** ++ * struct bnx2i_sess - iscsi session structure ++ * ++ * @link: list head to link elements ++ * @hba: adapter structure pointer ++ * @shost: scsi host pointer ++ * @state: flag to track session state ++ * @recovery_state: recovery state identifier ++ * @old_recovery_state: old recovery state identifier ++ * @tmf_active: TMF is active on this session ++ * @lock: session lock to synchronize access ++ * @abort_timer: TMF timer ++ * @er_wait: wait queue for recovery process ++ * @cmd_pages: table to track pages allocated for cmd struct ++ * @pend_cmds: pend command list ++ * @num_pend_cmds: number of pend command ++ * @free_cmds: free command list ++ * @num_free_cmds: num free commands ++ * @allocated_cmds: total number of allocated commands ++ * @sq_size: SQ size ++ * @itt_q: ITT queue ++ * @bd_resc_page: table to track BD resource page memory ++ * @bd_tbl_list: BD table list ++ * @bd_tbl_active: active BD table list ++ * @active_cmds: active command list ++ * @num_active_cmds: num active commands ++ * @cmdsn: iscsi command sequence number ++ * @exp_cmdsn: iscsi expected command sequence number ++ * @max_cmdsn: iscsi max command sequence number ++ * @initial_r2t: intial R2T is enabled/disable ++ * @max_r2t: maximun outstanding T2T ++ * @imm_data: indicates if immediate data is enabled ++ * @first_burst_len: negotiated first burst length ++ * @max_burst_len: negotiated max burst length ++ * @time2wait: time 2 wait value ++ * @time2retain: time 2 retain value ++ * @pdu_inorder: indicated if PDU order needs to be maintained ++ * @dataseq_inorder: indicated if data sequence order needs to be ++ * maintained ++ * @erl: supported error recovery level ++ * @tgt_prtl_grp: target portal group tag ++ * @target_name: target name ++ * @isid: isid for this session ++ * @tsih: target returned TSIH ++ * @lead_conn: points to lead connection pointer ++ * @conn_list: list of connection belonging to this session ++ * @num_active_conn: num active connections ++ * @max_conns: maximun connection per session ++ * @violation_notified: bit mask used to track iscsi error/warning messages ++ * already printed out ++ * iSCSI Session Structure ++ */ ++struct bnx2i_sess { ++ struct list_head link; ++ struct bnx2i_hba *hba; ++#ifdef __VMKLNX__ ++ struct iscsi_cls_session *cls_sess; ++#else ++ struct Scsi_Host *shost; ++#endif ++ unsigned long timestamp; ++ unsigned long worker_time_slice; ++ u32 state; ++ #define BNX2I_SESS_INITIAL 0x01 ++ #define BNX2I_SESS_IN_FFP 0x02 ++ #define BNX2I_SESS_IN_RECOVERY 0x04 ++ #define BNX2I_SESS_IN_SHUTDOWN 0x08 ++ #define BNX2I_SESS_IN_LOGOUT 0x40 ++#ifdef __VMKLNX__ ++ /* Do not notify device offline to vmkernel to until ++ * iscsi transport calls destroy_session() ++ */ ++ #define BNX2I_SESS_DESTROYED 0x80 ++ /* if session encounters an error before transitioning ++ * to FFP, target_destroy() will be called before ++ * session_destroy() and this requires another flag ++ * to identify this to make adjustments as to how ++ * resources will be freed ++ */ ++ #define BNX2I_SESS_TARGET_DESTROYED 0x100 ++#endif ++ #define is_sess_active(_sess) \ ++ (((_sess)->state & BNX2I_SESS_IN_FFP)) ++ unsigned long recovery_state; ++ #define ISCSI_SESS_RECOVERY_START 0x01 ++ #define ISCSI_SESS_RECOVERY_OPEN_ISCSI 0x02 ++ #define ISCSI_SESS_RECOVERY_COMPLETE 0x04 ++ #define ISCSI_SESS_RECOVERY_FAILED 0x08 ++ unsigned long old_recovery_state; ++ atomic_t tmf_active; ++ ++#ifndef _USE_ITT_QUE ++ struct bnx2i_cmd **itt_cmd; ++ #define get_cmnd(sess, itt) sess->itt_cmd[itt] ++#endif ++ ++ spinlock_t lock; /* protects session structure */ ++ struct mutex tmf_mutex; ++ ++ /* Command abort timer */ ++ struct timer_list abort_timer; ++ /* event wait queue used during error recovery */ ++ wait_queue_head_t er_wait; ++ ++ /* ++ * Per session command (task) structure management ++ */ ++ void *cmd_pages[MAX_PAGES_PER_CTRL_STRUCT_POOL]; ++ struct list_head free_cmds; ++ int num_free_cmds; ++ int allocated_cmds; ++ ++ int sq_size; ++#ifdef _USE_ITT_QUEUE ++ struct itt_queue itt_q; ++ #define MAX_BD_RESOURCE_PAGES 8 ++#endif ++ ++ struct list_head bd_resc_page; ++ void *bdt_dma_info; ++ struct list_head bdt_dma_resc; ++ struct list_head bd_tbl_list; ++ struct list_head bd_tbl_active; ++ ++ /* ++ * command queue management ++ */ ++ atomic_t login_noop_pending; ++ atomic_t tmf_pending; ++ atomic_t logout_pending; ++ atomic_t nop_resp_pending; ++ struct bnx2i_cmd *login_nopout_cmd; ++ struct bnx2i_cmd *scsi_tmf_cmd; ++ struct bnx2i_cmd *nopout_resp_cmd; ++ ++ void *task_list_mem; ++ struct list_head scsi_task_list; ++ struct list_head pend_cmd_list; ++ u32 pend_cmd_count; ++ struct list_head active_cmd_list; ++ u32 active_cmd_count; ++ int cmd_cleanup_req; ++ int cmd_cleanup_cmpl; ++ ++ /* ++ * iSCSI session related sequencing parameters. ++ */ ++ unsigned int cmdsn; ++ unsigned int exp_cmdsn; ++ unsigned int max_cmdsn; ++ ++ /* ++ * Following pointers are linked to corresponding entry in ++ * operational parameter table associated with this session. ++ * These are to be filled when session becomes operational (FFP). ++ */ ++ int initial_r2t; ++ int max_r2t; ++ int imm_data; ++ u32 first_burst_len; ++ u32 max_burst_len; ++ int time2wait; ++ int time2retain; ++ int pdu_inorder; ++ int dataseq_inorder; ++ int erl; ++ int tgt_prtl_grp; ++ char *target_name; ++ ++ unsigned char isid[13]; ++ unsigned short tsih; ++ ++ struct bnx2i_conn *lead_conn; ++ struct list_head conn_list; ++ u32 num_active_conn; ++ u32 max_conns; ++ ++ /* Driver private statistics */ ++ u64 violation_notified; ++ ++ unsigned long last_nooput_requested; ++ unsigned long last_nooput_posted; ++ unsigned long last_noopin_indicated; ++ unsigned long last_noopin_processed; ++ u32 last_nooput_sn; ++ u32 noopout_resp_count; ++ u32 unsol_noopout_count; ++ int noopout_requested_count; ++ int noopout_posted_count; ++ int noopin_indicated_count; ++ int noopin_processed_count; ++ int tgt_noopin_count; ++}; ++ ++ ++ ++/** ++ * struct iscsi_cid_queue - Per adapter iscsi cid queue ++ * ++ * @cid_que_base: queue base memory ++ * @cid_que: queue memory pointer ++ * @cid_q_prod_idx: produce index ++ * @cid_q_cons_idx: consumer index ++ * @cid_q_max_idx: max index. used to detect wrap around condition ++ * @cid_free_cnt: queue size ++ * @conn_cid_tbl: iscsi cid to conn structure mapping table ++ * ++ * Per adapter iSCSI CID Queue ++ */ ++struct iscsi_cid_queue { ++ void *cid_que_base; ++ u32 *cid_que; ++ u32 cid_q_prod_idx; ++ u32 cid_q_cons_idx; ++ u32 cid_q_max_idx; ++ u32 cid_free_cnt; ++ struct bnx2i_conn **conn_cid_tbl; ++}; ++ ++ ++/** ++ * struct bnx2i_hba - bnx2i adapter structure ++ * ++ * @link: list head to link elements ++ * @cnic: pointer to cnic device ++ * @pcidev: pointer to pci dev ++ * @netdev: pointer to netdev structure ++ * @regview: mapped PCI register space ++ * @class_dev: class dev to operate sysfs node ++ * @age: age, incremented by every recovery ++ * @cnic_dev_type: cnic device type, 5706/5708/5709/57710 ++ * @mail_queue_access: mailbox queue access mode, applicable to 5709 only ++ * @reg_with_cnic: indicates whether the device is register with CNIC ++ * @adapter_state: adapter state, UP, GOING_DOWN, LINK_DOWN ++ * @mtu_supported: Ethernet MTU supported ++ * @scsi_template: pointer to scsi host template ++ * @iscsi_transport: pointer to iscsi transport template ++ * @shost_template: pointer to shost template ++ * @max_sqes: SQ size ++ * @max_rqes: RQ size ++ * @max_cqes: CQ size ++ * @num_ccell: number of command cells per connection ++ * @active_sess: active session list head ++ * @num_active_sess: number of active connections ++ * @ofld_conns_active: active connection list ++ * @max_active_conns: max offload connections supported by this device ++ * @cid_que: iscsi cid queue ++ * @ep_rdwr_lock: read / write lock to synchronize various ep lists ++ * @ep_ofld_list: connection list for pending offload completion ++ * @ep_destroy_list: connection list for pending offload completion ++ * @mp_bd_tbl: BD table to be used with middle path requests ++ * @mp_bd_dma: DMA address of 'mp_bd_tbl' memory buffer ++ * @dummy_buffer: Dummy buffer to be used with zero length scsicmd reqs ++ * @dummy_buf_dma: DMA address of 'dummy_buffer' memory buffer ++ * @lock: lock to synchonize access to hba structure ++ * @hba_timer: timer block ++ * @eh_wait: wait queue to be used during error handling ++ * @err_rec_task: error handling worker ++ * @sess_recov_list: session list which are queued for recovery ++ * @sess_recov_prod_idx: producer index to manage session recovery list ++ * @sess_recov_cons_idx: producer index to manage session recovery list ++ * @sess_recov_max_idx: max index to manage session recovery list ++ * @mac_addr: MAC address ++ * @conn_teardown_tmo: connection teardown timeout ++ * @conn_ctx_destroy_tmo: connection context destroy timeout ++ * @hba_shutdown_tmo: hba shutdown cleanup timeout ++ * @pci_did: PCI device ID ++ * @pci_vid: PCI vendor ID ++ * @pci_sdid: PCI subsystem device ID ++ * @pci_svid: PCI subsystem vendor ID ++ * @pci_func: PCI function number in system pci tree ++ * @pci_devno: PCI device number in system pci tree ++ * @num_wqe_sent: statistic counter, total wqe's sent ++ * @num_cqe_rcvd: statistic counter, total cqe's received ++ * @num_intr_claimed: statistic counter, total interrupts claimed ++ * @link_changed_count: statistic counter, num of link change notifications ++ * received ++ * @ipaddr_changed_count: statistic counter, num times IP address changed while ++ * at least one connection is offloaded ++ * @num_sess_opened: statistic counter, total num sessions opened ++ * @num_conn_opened: statistic counter, total num conns opened on this hba ++ * ++ * Adapter Data Structure ++ */ ++struct bnx2i_hba { ++ struct list_head link; ++ struct cnic_dev *cnic; ++ struct pci_dev *pcidev; ++ struct net_device *netdev; ++ void __iomem *regview; ++ struct class_device class_dev; ++ u32 age; ++ unsigned long cnic_dev_type; ++ #define BNX2I_NX2_DEV_5706 0x0 ++ #define BNX2I_NX2_DEV_5708 0x1 ++ #define BNX2I_NX2_DEV_5709 0x2 ++ #define BNX2I_NX2_DEV_57710 0x3 ++ u32 mail_queue_access; ++ #define BNX2I_MQ_KERNEL_MODE 0x0 ++ #define BNX2I_MQ_KERNEL_BYPASS_MODE 0x1 ++ #define BNX2I_MQ_BIN_MODE 0x2 ++ unsigned long reg_with_cnic; ++ #define BNX2I_CNIC_REGISTERED 1 ++ ++ unsigned long adapter_state; ++ #define ADAPTER_STATE_UP 0 ++ #define ADAPTER_STATE_GOING_DOWN 1 ++ #define ADAPTER_STATE_LINK_DOWN 2 ++ #define ADAPTER_STATE_INIT_FAILED 31 ++ unsigned int mtu_supported; ++ #define BNX2I_MAX_MTU_SUPPORTED 9000 ++ ++ struct scsi_host_template *scsi_template; ++ struct iscsi_transport *iscsi_transport; ++#ifdef __VMKLNX__ ++ #define BRCM_ISCSI_XPORT_NAME_PREFIX "bnx2i" ++#else ++ #define BRCM_ISCSI_XPORT_NAME_PREFIX "bcm570x" ++#endif ++ #define BRCM_ISCSI_XPORT_NAME_SIZE_MAX 128 ++ struct scsi_transport_template *shost_template; ++ ++#ifdef __VMKLNX__ ++ struct Scsi_Host *shost; ++ u32 target_id; ++ u32 channel_id; ++ struct device vm_pcidev; ++#endif ++ ++ u32 max_sqes; ++ u32 max_rqes; ++ u32 max_cqes; ++ u32 num_ccell; ++ ++#ifdef __VMKLNX__ ++ struct timer_list hba_poll_timer; ++#endif ++ ++ /* different page table setup requirments for 5771x and 570x */ ++ void (*setup_pgtbl)(struct bnx2i_hba *hba, ++ struct bnx2i_dma *dma, ++ int pgtbl_off); ++ ++ struct list_head active_sess; ++ int num_active_sess; ++ int ofld_conns_active; ++ ++ int max_active_conns; ++ struct iscsi_cid_queue cid_que; ++ ++#ifndef __VMKLNX__ ++ rwlock_t ep_rdwr_lock; ++#endif ++ struct list_head ep_ofld_list; ++ struct list_head ep_destroy_list; ++ ++ /* ++ * BD table to be used with MP (Middle Path requests. ++ */ ++ struct bnx2i_dma mp_dma_buf; ++ ++ spinlock_t lock; /* protects hba structure access */ ++ struct mutex net_dev_lock;/* sync net device access */ ++ ++ /* Error handling */ ++ struct timer_list hba_timer; ++ wait_queue_head_t eh_wait; ++ struct work_struct err_rec_task; ++ struct bnx2i_sess **sess_recov_list; ++ int sess_recov_prod_idx; ++ int sess_recov_cons_idx; ++ int sess_recov_max_idx; ++ ++ unsigned char mac_addr[MAX_ADDR_LEN]; ++ ++ int conn_teardown_tmo; ++ int conn_ctx_destroy_tmo; ++ int hba_shutdown_tmo; ++ unsigned int ctx_ccell_tasks; ++ /* ++ * PCI related info. ++ */ ++ u16 pci_did; ++ u16 pci_vid; ++ u16 pci_sdid; ++ u16 pci_svid; ++ u16 pci_func; ++ u16 pci_devno; ++ ++ /* ++ * Following are a bunch of statistics useful during development ++ * and later stage for score boarding. ++ */ ++ u32 num_wqe_sent; ++ u32 num_cqe_rcvd; ++ u32 num_intr_claimed; ++ u32 link_changed_count; ++ u32 ipaddr_changed_count; ++ u32 num_sess_opened; ++ u32 num_conn_opened; ++}; ++ ++ ++/******************************************************************************* ++ * QP [ SQ / RQ / CQ ] info. ++ ******************************************************************************/ ++ ++/* ++ * SQ/RQ/CQ generic structure definition ++ */ ++struct sqe { ++ u8 sqe_byte[BNX2I_SQ_WQE_SIZE]; ++}; ++ ++struct rqe { ++ u8 rqe_byte[BNX2I_RQ_WQE_SIZE]; ++}; ++ ++struct cqe { ++ u8 cqe_byte[BNX2I_CQE_SIZE]; ++}; ++ ++ ++enum { ++#if defined(__LITTLE_ENDIAN) ++ CNIC_EVENT_COAL_INDEX = 0x0, ++ CNIC_SEND_DOORBELL = 0x4, ++ CNIC_EVENT_CQ_ARM = 0x7, ++ CNIC_RECV_DOORBELL = 0x8 ++#elif defined(__BIG_ENDIAN) ++ CNIC_EVENT_COAL_INDEX = 0x2, ++ CNIC_SEND_DOORBELL = 0x6, ++ CNIC_EVENT_CQ_ARM = 0x4, ++ CNIC_RECV_DOORBELL = 0xa ++#endif ++}; ++ ++ ++ ++/* ++ * CQ DB ++ */ ++struct bnx2x_iscsi_cq_pend_cmpl { ++ /* CQ producer, updated by Ustorm */ ++ u16 ustrom_prod; ++ /* CQ pending completion counter */ ++ u16 pend_cntr; ++}; ++ ++ ++struct bnx2i_5771x_cq_db { ++ struct bnx2x_iscsi_cq_pend_cmpl qp_pend_cmpl[BNX2X_MAX_CQS]; ++ /* CQ pending completion ITT array */ ++ u16 itt[BNX2X_MAX_CQS]; ++ /* Cstorm CQ sequence to notify array, updated by driver */; ++ u16 sqn[BNX2X_MAX_CQS]; ++ u32 reserved[4] /* 16 byte allignment */; ++}; ++ ++ ++struct bnx2i_5771x_sq_rq_db { ++ u16 prod_idx; ++ u8 reserved0[14]; /* Pad structure size to 16 bytes */ ++}; ++ ++ ++struct bnx2i_5771x_dbell_hdr { ++ u8 header; ++ /* 1 for rx doorbell, 0 for tx doorbell */ ++#define B577XX_DOORBELL_HDR_RX (0x1<<0) ++#define B577XX_DOORBELL_HDR_RX_SHIFT 0 ++ /* 0 for normal doorbell, 1 for advertise wnd doorbell */ ++#define B577XX_DOORBELL_HDR_DB_TYPE (0x1<<1) ++#define B577XX_DOORBELL_HDR_DB_TYPE_SHIFT 1 ++ /* rdma tx only: DPM transaction size specifier (64/128/256/512B) */ ++#define B577XX_DOORBELL_HDR_DPM_SIZE (0x3<<2) ++#define B577XX_DOORBELL_HDR_DPM_SIZE_SHIFT 2 ++ /* connection type */ ++#define B577XX_DOORBELL_HDR_CONN_TYPE (0xF<<4) ++#define B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT 4 ++}; ++ ++struct bnx2i_5771x_dbell { ++ struct bnx2i_5771x_dbell_hdr dbell; ++ u8 pad[3]; ++ ++}; ++ ++ ++/** ++ * struct qp_info - QP (share queue region) atrributes structure ++ * ++ * @ctx_base: ioremapped pci register base to access doorbell register ++ * pertaining to this offloaded connection ++ * @sq_virt: virtual address of send queue (SQ) region ++ * @sq_phys: DMA address of SQ memory region ++ * @sq_mem_size: SQ size ++ * @sq_prod_qe: SQ producer entry pointer ++ * @sq_cons_qe: SQ consumer entry pointer ++ * @sq_first_qe: virtaul address of first entry in SQ ++ * @sq_last_qe: virtaul address of last entry in SQ ++ * @sq_prod_idx: SQ producer index ++ * @sq_cons_idx: SQ consumer index ++ * @sqe_left: number sq entry left ++ * @sq_pgtbl_virt: page table describing buffer consituting SQ region ++ * @sq_pgtbl_phys: dma address of 'sq_pgtbl_virt' ++ * @sq_pgtbl_size: SQ page table size ++ * @cq_virt: virtual address of completion queue (CQ) region ++ * @cq_phys: DMA address of RQ memory region ++ * @cq_mem_size: CQ size ++ * @cq_prod_qe: CQ producer entry pointer ++ * @cq_cons_qe: CQ consumer entry pointer ++ * @cq_first_qe: virtaul address of first entry in CQ ++ * @cq_last_qe: virtaul address of last entry in CQ ++ * @cq_prod_idx: CQ producer index ++ * @cq_cons_idx: CQ consumer index ++ * @cqe_left: number cq entry left ++ * @cqe_size: size of each CQ entry ++ * @cqe_exp_seq_sn: next expected CQE sequence number ++ * @cq_pgtbl_virt: page table describing buffer consituting CQ region ++ * @cq_pgtbl_phys: dma address of 'cq_pgtbl_virt' ++ * @cq_pgtbl_size: CQ page table size ++ * @rq_virt: virtual address of receive queue (RQ) region ++ * @rq_phys: DMA address of RQ memory region ++ * @rq_mem_size: RQ size ++ * @rq_prod_qe: RQ producer entry pointer ++ * @rq_cons_qe: RQ consumer entry pointer ++ * @rq_first_qe: virtaul address of first entry in RQ ++ * @rq_last_qe: virtaul address of last entry in RQ ++ * @rq_prod_idx: RQ producer index ++ * @rq_cons_idx: RQ consumer index ++ * @rqe_left: number rq entry left ++ * @rq_pgtbl_virt: page table describing buffer consituting RQ region ++ * @rq_pgtbl_phys: dma address of 'rq_pgtbl_virt' ++ * @rq_pgtbl_size: RQ page table size ++ * ++ * queue pair (QP) is a per connection shared data structure which is used ++ * to send work requests (SQ), receive completion notifications (CQ) ++ * and receive asynchoronous / scsi sense info (RQ). 'qp_info' structure ++ * below holds queue memory, consumer/producer indexes and page table ++ * information ++ */ ++struct qp_info { ++ void __iomem *ctx_base; ++#define DPM_TRIGER_TYPE 0x40 ++ ++#define BNX2I_570x_QUE_DB_SIZE 0 ++#define BNX2I_5771x_QUE_DB_SIZE 16 ++ struct bnx2i_dma sq_dma; ++#define sq_virt sq_dma.mem ++ struct sqe *sq_prod_qe; ++ struct sqe *sq_first_qe; ++ struct sqe *sq_last_qe; ++ u16 sq_prod_idx; ++ ++ struct bnx2i_dma cq_dma; ++#define cq_virt cq_dma.mem ++ struct cqe *cq_cons_qe; ++ struct cqe *cq_first_qe; ++ struct cqe *cq_last_qe; ++ u16 cq_cons_idx; ++ u32 cqe_left; ++ u32 cqe_size; ++ u32 cqe_exp_seq_sn; ++ ++ struct bnx2i_dma rq_dma; ++#define rq_virt rq_dma.mem ++ ++ struct rqe *rq_prod_qe; ++ struct rqe *rq_cons_qe; ++ struct rqe *rq_first_qe; ++ struct rqe *rq_last_qe; ++ u16 rq_prod_idx; ++ u16 rq_cons_idx; ++ u32 rqe_left; ++}; ++ ++ ++ ++/* ++ * CID handles ++ */ ++struct ep_handles { ++ u32 fw_cid; ++ u32 drv_iscsi_cid; ++ u16 pg_cid; ++ u16 rsvd; ++}; ++ ++ ++/** ++ * struct bnx2i_endpoint - representation of tcp connection in NX2 world ++ * ++ * @link: list head to link elements ++ * @hba: adapter to which this connection belongs ++ * @conn: iscsi connection this EP is linked to ++ * @sess: iscsi session this EP is linked to ++ * @cm_sk: cnic sock struct ++ * @hba_age: age to detect if 'iscsid' issues ep_disconnect() ++ * after HBA reset is completed by bnx2i/cnic/bnx2 ++ * modules ++ * @state: tracks offload connection state machine ++ * @tcp_port: Local TCP port number used in this connection ++ * @qp: QP information ++ * @ids: contains chip allocated *context id* & driver assigned ++ * *iscsi cid* ++ * @ofld_timer: offload timer to detect timeout ++ * @ofld_wait: wait queue ++ * ++ * Endpoint Structure - equivalent of tcp socket structure ++ */ ++struct bnx2i_endpoint { ++ struct list_head link; ++ struct bnx2i_hba *hba; ++ struct bnx2i_conn *conn; ++ struct bnx2i_sess *sess; ++ struct cnic_sock *cm_sk; ++ u32 hba_age; ++ u32 state; ++ #define EP_STATE_IDLE 0x00000000 ++ #define EP_STATE_PG_OFLD_START 0x00000001 ++ #define EP_STATE_PG_OFLD_COMPL 0x00000002 ++ #define EP_STATE_OFLD_START 0x00000004 ++ #define EP_STATE_OFLD_COMPL 0x00000008 ++ #define EP_STATE_CONNECT_START 0x00000010 ++ #define EP_STATE_CONNECT_COMPL 0x00000020 ++ #define EP_STATE_ULP_UPDATE_START 0x00000040 ++ #define EP_STATE_ULP_UPDATE_COMPL 0x00000080 ++ #define EP_STATE_DISCONN_START 0x00000100 ++ #define EP_STATE_DISCONN_COMPL 0x00000200 ++ #define EP_STATE_CLEANUP_START 0x00000400 ++ #define EP_STATE_CLEANUP_CMPL 0x00000800 ++ #define EP_STATE_TCP_FIN_RCVD 0x00001000 ++ #define EP_STATE_TCP_RST_RCVD 0x00002000 ++ #define EP_STATE_PG_OFLD_FAILED 0x01000000 ++ #define EP_STATE_ULP_UPDATE_FAILED 0x02000000 ++ #define EP_STATE_CLEANUP_FAILED 0x04000000 ++ #define EP_STATE_OFLD_FAILED 0x08000000 ++ #define EP_STATE_CONNECT_FAILED 0x10000000 ++ #define EP_STATE_DISCONN_TIMEDOUT 0x20000000 ++ ++ unsigned long timestamp; ++ int teardown_mode; ++#define BNX2I_ABORTIVE_SHUTDOWN 0 ++#define BNX2I_GRACEFUL_SHUTDOWN 1 ++ u16 tcp_port; ++ ++ struct qp_info qp; ++ struct ep_handles ids; ++ #define ep_iscsi_cid ids.drv_iscsi_cid ++ #define ep_cid ids.fw_cid ++ #define ep_pg_cid ids.pg_cid ++ struct timer_list ofld_timer; ++ wait_queue_head_t ofld_wait; ++}; ++ ++ ++static inline struct Scsi_Host *bnx2i_conn_get_shost(struct bnx2i_conn *conn) ++{ ++ struct Scsi_Host *shost; ++ ++#if defined(__VMKLNX__) ++ shost = conn->sess->hba->shost; ++#else ++ shost = conn->sess->shost; ++#endif ++ return shost; ++} ++ ++static inline struct Scsi_Host *bnx2i_sess_get_shost(struct bnx2i_sess *sess) ++{ ++ struct Scsi_Host *shost; ++ ++#if defined(__VMKLNX__) ++ shost = sess->hba->shost; ++#else ++ shost = sess->shost; ++#endif ++ return shost; ++} ++ ++extern unsigned int cmd_cmpl_per_work; ++ ++/* ++ * Function Prototypes ++ */ ++extern int bnx2i_reg_device; ++void bnx2i_identify_device(struct bnx2i_hba *hba); ++void bnx2i_register_device(struct bnx2i_hba *hba, int force); ++void bnx2i_check_nx2_dev_busy(void); ++#ifdef __VMKLNX__ ++void bnx2i_ep_disconnect(vmk_int64 ep_handle); ++#else ++void bnx2i_ep_disconnect(uint64_t ep_handle); ++#endif ++ ++void bnx2i_ulp_init(struct cnic_dev *dev); ++void bnx2i_ulp_exit(struct cnic_dev *dev); ++void bnx2i_start(void *handle); ++void bnx2i_stop(void *handle); ++void bnx2i_reg_dev_all(void); ++void bnx2i_unreg_dev_all(void); ++struct bnx2i_hba *get_adapter_list_head(void); ++ ++int bnx2i_ioctl_init(void); ++void bnx2i_ioctl_cleanup(void); ++ ++struct bnx2i_conn *bnx2i_get_conn_from_id(struct bnx2i_hba *hba, ++ u16 iscsi_cid); ++ ++int bnx2i_alloc_ep_pool(void); ++void bnx2i_release_ep_pool(void); ++struct bnx2i_endpoint *bnx2i_ep_ofld_list_next(struct bnx2i_hba *hba); ++struct bnx2i_endpoint *bnx2i_ep_destroy_list_next(struct bnx2i_hba *hba); ++ ++struct bnx2i_cmd *bnx2i_alloc_cmd(struct bnx2i_sess *sess); ++void bnx2i_free_cmd(struct bnx2i_sess *sess, struct bnx2i_cmd *cmd); ++int bnx2i_tcp_conn_active(struct bnx2i_conn *conn); ++ ++struct bnx2i_hba *bnx2i_find_hba_for_cnic(struct cnic_dev *cnic); ++struct bnx2i_hba *bnx2i_get_hba_from_template( ++ struct scsi_transport_template *scsit); ++ ++struct bnx2i_hba *bnx2i_alloc_hba(struct cnic_dev *cnic); ++void bnx2i_free_hba(struct bnx2i_hba *hba); ++int bnx2i_process_new_cqes(struct bnx2i_conn *conn, int soft_irq, int num_cqes); ++void bnx2i_process_scsi_resp(struct bnx2i_cmd *cmd, ++ struct iscsi_cmd_response *resp_cqe); ++int bnx2i_process_nopin(struct bnx2i_conn *conn, ++ struct bnx2i_cmd *cmnd, char *data_buf, int data_len); ++ ++ ++void bnx2i_update_cmd_sequence(struct bnx2i_sess *sess, u32 expsn, u32 maxsn); ++ ++void bnx2i_get_rq_buf(struct bnx2i_conn *conn, char *ptr, int len); ++void bnx2i_put_rq_buf(struct bnx2i_conn *conn, int count); ++ ++int bnx2i_indicate_login_resp(struct bnx2i_conn *conn); ++int bnx2i_indicate_logout_resp(struct bnx2i_conn *conn); ++int bnx2i_indicate_async_mesg(struct bnx2i_conn *conn); ++ ++void bnx2i_iscsi_unmap_sg_list(struct bnx2i_hba *hba, struct bnx2i_cmd *cmd); ++ ++void bnx2i_start_iscsi_hba_shutdown(struct bnx2i_hba *hba); ++void bnx2i_iscsi_handle_ip_event(struct bnx2i_hba *hba); ++int bnx2i_do_iscsi_sess_recovery(struct bnx2i_sess *sess, int err_code); ++void bnx2i_return_failed_command(struct bnx2i_sess *sess, ++ struct scsi_cmnd *cmd, int resid, int err_code); ++void bnx2i_fail_cmd(struct bnx2i_sess *sess, struct bnx2i_cmd *cmd); ++int bnx2i_complete_cmd(struct bnx2i_sess *sess, struct bnx2i_cmd *cmd); ++ ++void bnx2i_cleanup_tcp_port_mngr(void); ++int bnx2i_init_tcp_port_mngr(void); ++ ++int bnx2i_alloc_dma(struct bnx2i_hba *hba, struct bnx2i_dma *dma, ++ int size, int pgtbl_type, int pgtbl_off); ++void bnx2i_free_dma(struct bnx2i_hba *hba, struct bnx2i_dma *dma); ++int bnx2i_setup_mp_bdt(struct bnx2i_hba *hba); ++void bnx2i_free_mp_bdt(struct bnx2i_hba *hba); ++void bnx2i_init_ctx_dump_mem(struct bnx2i_hba *hba); ++void bnx2i_free_ctx_dump_mem(struct bnx2i_hba *hba); ++ ++extern int bnx2i_send_fw_iscsi_init_msg(struct bnx2i_hba *hba); ++extern int bnx2i_send_iscsi_login(struct bnx2i_conn *conn, ++ struct bnx2i_cmd *cmnd); ++extern int bnx2i_send_iscsi_text(struct bnx2i_conn *conn, ++ struct bnx2i_cmd *cmnd); ++extern int bnx2i_send_iscsi_tmf(struct bnx2i_conn *conn, ++ struct bnx2i_cmd *cmnd); ++extern int bnx2i_send_iscsi_scsicmd(struct bnx2i_conn *conn, ++ struct bnx2i_cmd *cmnd); ++extern int bnx2i_send_iscsi_nopout(struct bnx2i_conn *conn, ++ struct bnx2i_cmd *cmnd, ++ char *datap, int data_len); ++extern int bnx2i_send_iscsi_logout(struct bnx2i_conn *conn, ++ struct bnx2i_cmd *cmnd); ++extern void bnx2i_send_cmd_cleanup_req(struct bnx2i_hba *hba, ++ struct bnx2i_cmd *cmd); ++extern int bnx2i_send_conn_ofld_req(struct bnx2i_hba *hba, ++ struct bnx2i_endpoint *ep); ++extern int bnx2i_update_iscsi_conn(struct bnx2i_conn *conn); ++extern int bnx2i_send_conn_destroy(struct bnx2i_hba *hba, ++ struct bnx2i_endpoint *ep); ++extern int bnx2i_alloc_qp_resc(struct bnx2i_hba *hba, ++ struct bnx2i_endpoint *ep); ++extern void bnx2i_free_qp_resc(struct bnx2i_hba *hba, ++ struct bnx2i_endpoint *ep); ++extern void bnx2i_ep_ofld_timer(unsigned long data); ++struct bnx2i_endpoint *bnx2i_find_ep_in_ofld_list(struct bnx2i_hba *hba, ++ u32 iscsi_cid); ++struct bnx2i_endpoint *bnx2i_find_ep_in_destroy_list(struct bnx2i_hba *hba, ++ u32 iscsi_cid); ++void bnx2i_ring_sq_dbell_bnx2(struct bnx2i_conn *conn); ++void bnx2i_ring_sq_dbell_bnx2x(struct bnx2i_conn *conn); ++int bnx2i_map_ep_dbell_regs(struct bnx2i_endpoint *ep); ++ ++void bnx2i_arm_cq_event_coalescing(struct bnx2i_endpoint *ep, u8 action); ++ ++int bnx2i_register_xport(struct bnx2i_hba *hba); ++int bnx2i_deregister_xport(struct bnx2i_hba *hba); ++int bnx2i_free_iscsi_scsi_template(struct bnx2i_hba *hba); ++ ++/* Debug related function prototypes */ ++extern void bnx2i_print_pend_cmd_queue(struct bnx2i_conn *conn); ++extern void bnx2i_print_active_cmd_queue(struct bnx2i_conn *conn); ++extern void bnx2i_print_xmit_pdu_queue(struct bnx2i_conn *conn); ++extern void bnx2i_print_recv_state(struct bnx2i_conn *conn); ++ ++#ifndef _SYSFS_INCL_ ++#define bnx2i_setup_ictx_dump(__hba, __conn) do { } while (0) ++#define bnx2i_sysfs_setup() do { } while (0) ++#define bnx2i_sysfs_cleanup() do { } while (0) ++#define bnx2i_register_sysfs(__hba) 0 ++#define bnx2i_unregister_sysfs(__hba) do { } while (0) ++#define bnx2i_init_mips_idle_counters(__hba) do { } while (0) ++#else ++extern void bnx2i_setup_ictx_dump(struct bnx2i_hba *hba, ++ struct bnx2i_conn *conn); ++extern int bnx2i_sysfs_setup(void); ++extern void bnx2i_sysfs_cleanup(void); ++extern int bnx2i_register_sysfs(struct bnx2i_hba *hba); ++extern void bnx2i_unregister_sysfs(struct bnx2i_hba *hba); ++void bnx2i_init_mips_idle_counters(struct bnx2i_hba *hba); ++void bnx2i_tcp_port_new_entry(u16 tcp_port); ++ ++#endif ++ ++#endif +diff -r ffba7e1f063a drivers/scsi/bnx2i/bnx2i_hwi.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/bnx2i/bnx2i_hwi.c Wed Aug 05 10:51:49 2009 +0100 +@@ -0,0 +1,2643 @@ ++/* bnx2i_hwi.c: Broadcom NetXtreme II iSCSI driver. ++ * ++ * Copyright (c) 2006 - 2009 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ * ++ * Written by: Anil Veerabhadrappa (anilgv@broadcom.com) ++ */ ++ ++#include "bnx2i.h" ++ ++extern unsigned int event_coal_min; ++static void bnx2i_recovery_que_add_sess(struct bnx2i_hba *hba, ++ struct bnx2i_sess *sess); ++ ++/** ++ * bnx2i_get_cid_num - ++ * @ep: endpoint pointer ++ * ++ * Only applicable to 57710 family of devices ++ **/ ++static u32 bnx2i_get_cid_num(struct bnx2i_endpoint *ep) ++{ ++ u32 cid; ++ ++ if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) ++ cid = ep->ep_cid; ++ else ++ cid = GET_CID_NUM(ep->ep_cid); ++ return cid; ++} ++ ++ ++/** ++ * bnx2i_adjust_qp_size - Adjust SQ/RQ/CQ size for 57710 device type ++ * @hba: Adapter for which adjustments is to be made ++ * ++ * Only applicable to 57710 family of devices ++ **/ ++static void bnx2i_adjust_qp_size(struct bnx2i_hba *hba) ++{ ++ u32 num_elements_per_pg; ++ ++ /* Only 5771x family requires SQ/CQ to be integral number of pages */ ++ if (test_bit(BNX2I_NX2_DEV_5706, &hba->cnic_dev_type) || ++ test_bit(BNX2I_NX2_DEV_5708, &hba->cnic_dev_type) || ++ test_bit(BNX2I_NX2_DEV_5709, &hba->cnic_dev_type)) ++ return; ++ ++ /* Adjust each queue size if the user selection does not ++ * yield integral num of page buffers ++ */ ++ /* adjust SQ */ ++ num_elements_per_pg = PAGE_SIZE / BNX2I_SQ_WQE_SIZE; ++ if (hba->max_sqes < num_elements_per_pg) ++ hba->max_sqes = num_elements_per_pg; ++ else if (hba->max_sqes % num_elements_per_pg) ++ hba->max_sqes = (hba->max_sqes + num_elements_per_pg - 1) & ++ ~(num_elements_per_pg - 1); ++ ++ /* adjust CQ */ ++ num_elements_per_pg = PAGE_SIZE / BNX2I_CQE_SIZE; ++ if (hba->max_cqes < num_elements_per_pg) ++ hba->max_cqes = num_elements_per_pg; ++ else if (hba->max_cqes % num_elements_per_pg) ++ hba->max_cqes = (hba->max_cqes + num_elements_per_pg - 1) & ++ ~(num_elements_per_pg - 1); ++ ++ /* adjust RQ */ ++ num_elements_per_pg = PAGE_SIZE / BNX2I_RQ_WQE_SIZE; ++ if (hba->max_rqes < num_elements_per_pg) ++ hba->max_rqes = num_elements_per_pg; ++ else if (hba->max_rqes % num_elements_per_pg) ++ hba->max_rqes = (hba->max_rqes + num_elements_per_pg - 1) & ++ ~(num_elements_per_pg - 1); ++} ++ ++ ++/** ++ * bnx2i_get_link_state - get network interface link state ++ * @hba: adapter instance pointer ++ * ++ * updates adapter structure flag based on netdev state ++ **/ ++static void bnx2i_get_link_state(struct bnx2i_hba *hba) ++{ ++ if (test_bit(__LINK_STATE_NOCARRIER, &hba->netdev->state)) { ++ set_bit(ADAPTER_STATE_LINK_DOWN, &hba->adapter_state); ++ } else { ++ clear_bit(ADAPTER_STATE_LINK_DOWN, &hba->adapter_state); ++ } ++} ++ ++ ++/** ++ * bnx2i_iscsi_license_error - displays iscsi license related error message ++ * ++ * @hba: adapter instance pointer ++ * @error_code: error classification ++ * ++ * Puts out an error log when driver is unable to offload iscsi connection ++ * due to license restrictions ++ **/ ++static void bnx2i_iscsi_license_error(struct bnx2i_hba *hba, u32 error_code) ++{ ++ if (error_code == ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED) ++ /* iSCSI offload not supported on this device */ ++ printk(KERN_ERR "bnx2i: iSCSI not supported, dev=%s\n", ++ hba->netdev->name); ++ else if (error_code == ++ ISCSI_KCQE_COMPLETION_STATUS_LOM_ISCSI_NOT_ENABLED) ++ /* iSCSI offload not supported on this LOM device */ ++ printk(KERN_ERR "bnx2i: LOM is not enable to " ++ "offload iSCSI connections, dev=%s\n", ++ hba->netdev->name); ++ set_bit(ADAPTER_STATE_INIT_FAILED, &hba->adapter_state); ++} ++ ++ ++extern unsigned int event_coal_div; ++ ++/** ++ * bnx2i_arm_cq_event_coalescing - arms CQ to enable EQ notification ++ * ++ * @ep: endpoint (transport indentifier) structure ++ * @action: action, ARM or DISARM. For now only ARM_CQE is used ++ * ++ * Arm'ing CQ will enable chip to generate global EQ events inorder to interrupt ++ * the driver. EQ event is generated CQ index is hit or at least 1 CQ is ++ * outstanding and on chip timer expires ++ **/ ++void bnx2i_arm_cq_event_coalescing(struct bnx2i_endpoint *ep, u8 action) ++{ ++ struct bnx2i_5771x_cq_db *cq_db; ++ u16 cq_index; ++ u16 next_index; ++ u32 num_active_cmds; ++ ++#ifndef _570X_ENABLE_EC_ ++ if (!test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) ++ return; ++#endif ++ ++ if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) { ++ cq_db = (struct bnx2i_5771x_cq_db*)ep->qp.cq_dma.pgtbl; ++ if (cq_db->sqn[0] && cq_db->sqn[0] != 0xFFFF) { ++ return; ++ } ++ } ++ ++ if ((action == CNIC_ARM_CQE) && ep->sess) { ++ num_active_cmds = ep->sess->active_cmd_count; ++ if (num_active_cmds <= event_coal_min) ++ next_index = 1; ++ else ++ next_index = event_coal_min + (num_active_cmds - event_coal_min) / event_coal_div ; ++ if (!next_index) ++ next_index = 1; ++ cq_index = ep->qp.cqe_exp_seq_sn + next_index - 1; ++ if (cq_index > ep->qp.cqe_size * 2) ++ cq_index -= ep->qp.cqe_size * 2; ++ if (!cq_index) ++ cq_index = 1; ++ ++#ifdef _570X_ENABLE_EC_ ++ if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) { ++#endif ++ cq_db = (struct bnx2i_5771x_cq_db*)ep->qp.cq_dma.pgtbl; ++ cq_db->sqn[0] = cq_index; ++#ifdef _570X_ENABLE_EC_ ++ return; ++ } ++ writew(cq_index, ep->qp.ctx_base + CNIC_EVENT_COAL_INDEX); ++#endif ++ } ++#ifdef _570X_ENABLE_EC_ ++ writeb(action, ep->qp.ctx_base + CNIC_EVENT_CQ_ARM); ++#endif ++} ++ ++ ++/** ++ * bnx2i_iscsi_license_error - copy RQ buffer contents to driver buffer ++ * ++ * @conn: iscsi connection on which RQ event occured ++ * @ptr: driver buffer to which RQ buffer contents is to ++ * be copied ++ * @len: length of valid data inside RQ buf ++ * ++ * Copies RQ buffer contents from shared (DMA'able) memory region to ++ * driver buffer. RQ is used to DMA unsolicitated iscsi pdu's and ++ * scsi sense info ++ **/ ++void bnx2i_get_rq_buf(struct bnx2i_conn *conn, char *ptr, int len) ++{ ++ if (conn->ep->qp.rqe_left) { ++ conn->ep->qp.rqe_left--; ++ memcpy(ptr, (u8 *) conn->ep->qp.rq_cons_qe, len); ++ ++ if (conn->ep->qp.rq_cons_qe == conn->ep->qp.rq_last_qe) { ++ conn->ep->qp.rq_cons_qe = conn->ep->qp.rq_first_qe; ++ conn->ep->qp.rq_cons_idx = 0; ++ } else { ++ conn->ep->qp.rq_cons_qe++; ++ conn->ep->qp.rq_cons_idx++; ++ } ++ } ++} ++ ++/** ++ * bnx2i_ring_577xx_doorbell - ring doorbell register to wake-up the ++ * processing engine ++ * @conn: iscsi connection ++ * ++ * Only applicable to 57710 family of devices ++ **/ ++void bnx2i_ring_577xx_doorbell(void __iomem *ctx_addr) ++{ ++ struct bnx2i_5771x_dbell dbell; ++ u32 msg; ++ ++ memset(&dbell, 0, sizeof(dbell)); ++ dbell.dbell.header = (B577XX_ISCSI_CONNECTION_TYPE << ++ B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT); ++ msg = *((u32 *)&dbell); ++ /* TODO : get doorbell register mapping */ ++ writel(cpu_to_le32(msg), ctx_addr); ++} ++ ++ ++/** ++ * bnx2i_put_rq_buf - Replenish RQ buffer, if required ring on chip doorbell ++ * @conn: iscsi connection on which event to post ++ * @count: number of RQ buffer being posted to chip ++ * ++ * No need to ring hardware doorbell for 57710 family of devices ++ **/ ++void bnx2i_put_rq_buf(struct bnx2i_conn *conn, int count) ++{ ++ struct bnx2i_5771x_sq_rq_db *rq_db; ++ u16 hi_bit = (conn->ep->qp.rq_prod_idx & 0x8000); ++ ++ conn->ep->qp.rqe_left += count; ++ conn->ep->qp.rq_prod_idx &= 0x7FFF; ++ conn->ep->qp.rq_prod_idx += count; ++ ++ if (conn->ep->qp.rq_prod_idx > conn->sess->hba->max_rqes) { ++ conn->ep->qp.rq_prod_idx %= conn->sess->hba->max_rqes; ++ if (!hi_bit) ++ conn->ep->qp.rq_prod_idx |= 0x8000; ++ } else ++ conn->ep->qp.rq_prod_idx |= hi_bit; ++ ++ if (test_bit(BNX2I_NX2_DEV_57710, &conn->ep->hba->cnic_dev_type)) { ++ rq_db = (struct bnx2i_5771x_sq_rq_db *) ++ conn->ep->qp.rq_dma.pgtbl; ++ rq_db->prod_idx = conn->ep->qp.rq_prod_idx; ++ /* no need to ring hardware doorbell for 57710 */ ++ } else { ++ writew(conn->ep->qp.rq_prod_idx, ++ conn->ep->qp.ctx_base + CNIC_RECV_DOORBELL); ++ } ++ mmiowb(); ++} ++ ++ ++void bnx2i_ring_sq_dbell_bnx2(struct bnx2i_conn *conn) ++{ ++ struct qp_info *qp = &conn->ep->qp; ++ ++ wmb(); /* flush SQ WQE memory before the doorbell is rung */ ++ writew(qp->sq_prod_idx, qp->ctx_base + CNIC_SEND_DOORBELL); ++ mmiowb(); /* flush posted PCI writes */ ++} ++ ++ ++void bnx2i_ring_sq_dbell_bnx2x(struct bnx2i_conn *conn) ++{ ++ struct bnx2i_5771x_sq_rq_db *sq_db; ++ struct qp_info *qp = &conn->ep->qp; ++ ++ wmb(); /* flush SQ WQE memory before the doorbell is rung */ ++ sq_db = (struct bnx2i_5771x_sq_rq_db *) qp->sq_dma.pgtbl; ++ sq_db->prod_idx = qp->sq_prod_idx; ++ bnx2i_ring_577xx_doorbell(conn->ep->qp.ctx_base); ++ mmiowb(); /* flush posted PCI writes */ ++} ++ ++ ++/** ++ * bnx2i_ring_dbell_update_sq_params - update SQ driver parameters ++ * ++ * @conn: iscsi connection to which new SQ entries belong ++ * @count: number of SQ WQEs to post ++ * ++ * this routine will update SQ driver parameters and ring the doorbell ++ **/ ++void bnx2i_ring_dbell_update_sq_params(struct bnx2i_conn *conn, int count) ++{ ++ int tmp_cnt; ++ struct qp_info *qp = &conn->ep->qp; ++ ++ if (count == 1) { ++ if (qp->sq_prod_qe == qp->sq_last_qe) ++ qp->sq_prod_qe = qp->sq_first_qe; ++ else ++ qp->sq_prod_qe++; ++ } else { ++ if ((qp->sq_prod_qe + count) <= qp->sq_last_qe) ++ qp->sq_prod_qe += count; ++ else { ++ tmp_cnt = qp->sq_last_qe - qp->sq_prod_qe; ++ qp->sq_prod_qe = ++ &qp->sq_first_qe[count - (tmp_cnt + 1)]; ++ } ++ } ++ qp->sq_prod_idx += count; ++ /* Ring the doorbell */ ++ conn->ring_doorbell(conn); ++} ++ ++ ++/** ++ * bnx2i_send_iscsi_login - post iSCSI login request MP WQE to hardware ++ * ++ * @conn: iscsi connection ++ * @cmd: driver command structure which is requesting ++ * a WQE to sent to chip for further processing ++ * ++ * prepare and post an iSCSI Login request WQE to CNIC firmware ++ */ ++int bnx2i_send_iscsi_login(struct bnx2i_conn *conn, struct bnx2i_cmd *cmd) ++{ ++ struct iscsi_login_request *login_wqe; ++ struct iscsi_login *login_hdr; ++ u32 dword; ++ ++ if (!conn->gen_pdu.req_buf || !conn->gen_pdu.resp_buf) ++ return -EINVAL; ++ ++ login_hdr = (struct iscsi_login *) &conn->gen_pdu.pdu_hdr; ++ login_wqe = (struct iscsi_login_request *) conn->ep->qp.sq_prod_qe; ++ ++ login_wqe->op_code = ISCSI_OP_LOGIN | ISCSI_OP_IMMEDIATE; ++ login_wqe->op_attr = login_hdr->flags; ++ login_wqe->version_max = login_hdr->max_version; ++ login_wqe->version_min = login_hdr->min_version; ++ login_wqe->data_length = ((login_hdr->dlength[0] << 16) | ++ (login_hdr->dlength[1] << 8) | ++ login_hdr->dlength[2]); ++ ++ login_wqe->isid_lo = *((u32 *) login_hdr->isid); ++ login_wqe->isid_hi = *((u16 *) login_hdr->isid + 2); ++ login_wqe->tsih = login_hdr->tsih; ++ login_wqe->itt = (cmd->req.itt | ++ (ISCSI_TASK_TYPE_MPATH << ++ ISCSI_LOGIN_REQUEST_TYPE_SHIFT)); ++ login_wqe->cid = login_hdr->cid; ++ ++ login_wqe->cmd_sn = ntohl(login_hdr->cmdsn); ++ login_wqe->exp_stat_sn = ntohl(login_hdr->exp_statsn); ++ ++ login_wqe->resp_bd_list_addr_lo = ++ (u32) conn->gen_pdu.login_resp.pgtbl_map; ++ login_wqe->resp_bd_list_addr_hi = ++ (u32) ((u64) conn->gen_pdu.login_resp.pgtbl_map >> 32); ++ ++ dword = ((1 << ISCSI_LOGIN_REQUEST_NUM_RESP_BDS_SHIFT) | ++ (conn->gen_pdu.resp_buf_size << ++ ISCSI_LOGIN_REQUEST_RESP_BUFFER_LENGTH_SHIFT)); ++ login_wqe->resp_buffer = dword; ++ login_wqe->flags = 0; ++ login_wqe->bd_list_addr_lo = (u32) conn->gen_pdu.login_req.pgtbl_map; ++ login_wqe->bd_list_addr_hi = ++ (u32) ((u64) conn->gen_pdu.login_req.pgtbl_map >> 32); ++ login_wqe->num_bds = 1; ++ login_wqe->cq_index = 0; /* CQ# used for completion, 5771x only */ ++ conn->num_login_req_pdus++; ++ ++ bnx2i_ring_dbell_update_sq_params(conn, 1); ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_send_iscsi_text - post iSCSI text request MP WQE to hardware ++ * ++ * @conn: iscsi connection ++ * @cmd: driver command structure which is requesting ++ * a WQE to sent to chip for further processing ++ * ++ * prepare and post an iSCSI Text request WQE to CNIC firmware ++ */ ++int bnx2i_send_iscsi_text(struct bnx2i_conn *conn, struct bnx2i_cmd *cmd) ++{ ++ conn->num_text_req_pdus++; ++ return 0; ++} ++ ++ ++ ++/** ++ * bnx2i_send_iscsi_tmf - post iSCSI task management request MP WQE to hardware ++ * ++ * @conn: iscsi connection ++ * @cmd: driver command structure which is requesting ++ * a WQE to sent to chip for further processing ++ * ++ * prepare and post an iSCSI Login request WQE to CNIC firmware ++ */ ++int bnx2i_send_iscsi_tmf(struct bnx2i_conn *conn, struct bnx2i_cmd *cmd) ++{ ++ struct bnx2i_hba *hba = conn->sess->hba; ++ u32 dword; ++ u32 scsi_lun[2]; ++ struct iscsi_tmf_request *tmfabort_wqe; ++ tmfabort_wqe = (struct iscsi_tmf_request *) conn->ep->qp.sq_prod_qe; ++ ++ memset(tmfabort_wqe, 0x00, sizeof(struct iscsi_tmf_request)); ++ tmfabort_wqe->op_code = cmd->iscsi_opcode; ++ tmfabort_wqe->op_attr = ++ ISCSI_TMF_REQUEST_ALWAYS_ONE | cmd->tmf_func; ++ ++ int_to_scsilun(cmd->tmf_lun, (struct scsi_lun *) scsi_lun); ++ tmfabort_wqe->lun[0] = ntohl(scsi_lun[0]); ++ tmfabort_wqe->lun[1] = ntohl(scsi_lun[1]); ++ ++ tmfabort_wqe->itt = (cmd->req.itt | (ISCSI_TASK_TYPE_MPATH << 14)); ++ tmfabort_wqe->reserved2 = 0; ++ tmfabort_wqe->cmd_sn = conn->sess->cmdsn; ++ ++ if (cmd->tmf_func == ISCSI_TM_FUNC_ABORT_TASK) { ++ if (cmd->tmf_ref_cmd->req.op_attr & ISCSI_CMD_REQUEST_READ) ++ dword = (ISCSI_TASK_TYPE_READ << ISCSI_CMD_REQUEST_TYPE_SHIFT); ++ else ++ dword = (ISCSI_TASK_TYPE_WRITE << ISCSI_CMD_REQUEST_TYPE_SHIFT); ++ tmfabort_wqe->ref_itt = (dword |= cmd->tmf_ref_itt); ++ tmfabort_wqe->ref_cmd_sn = cmd->tmf_ref_cmd->req.cmd_sn; ++ } else { ++ tmfabort_wqe->ref_itt = ISCSI_RESERVED_TAG; ++ } ++ ++ tmfabort_wqe->bd_list_addr_lo = (u32) hba->mp_dma_buf.pgtbl_map; ++ tmfabort_wqe->bd_list_addr_hi = ++ (u32) ((u64) hba->mp_dma_buf.pgtbl_map >> 32); ++ tmfabort_wqe->num_bds = 1; ++ tmfabort_wqe->cq_index = 0; /* CQ# used for completion, 5771x only */ ++ conn->num_tmf_req_pdus++; ++ ++ bnx2i_ring_dbell_update_sq_params(conn, 1); ++ return 0; ++} ++ ++/** ++ * bnx2i_send_iscsi_scsicmd - post iSCSI scsicmd request WQE to hardware ++ * ++ * @conn: iscsi connection ++ * @cmd: driver command structure which is requesting ++ * a WQE to sent to chip for further processing ++ * ++ * prepare and post an iSCSI SCSI-CMD request WQE to CNIC firmware ++ */ ++int bnx2i_send_iscsi_scsicmd(struct bnx2i_conn *conn, struct bnx2i_cmd *cmd) ++{ ++ struct iscsi_cmd_request *scsi_cmd_wqe; ++ ++ if (!conn->ep) ++ return -1; ++ ++ scsi_cmd_wqe = (struct iscsi_cmd_request *) conn->ep->qp.sq_prod_qe; ++ memcpy(scsi_cmd_wqe, &cmd->req, sizeof(struct iscsi_cmd_request)); ++ scsi_cmd_wqe->cq_index = 0; /* CQ# used for completion, 5771x only */ ++ ++ conn->num_scsi_cmd_pdus++; ++ bnx2i_ring_dbell_update_sq_params(conn, 1); ++ return 0; ++} ++ ++/** ++ * bnx2i_send_iscsi_nopout - post iSCSI NOPOUT request WQE to hardware ++ * ++ * @conn: iscsi connection ++ * @cmd: driver command structure which is requesting ++ * a WQE to sent to chip for further processing ++ * @ttt: TTT to be used when building pdu header ++ * @datap: payload buffer pointer ++ * @data_len: payload data length ++ * @unsol: indicated whether nopout pdu is unsolicited pdu or ++ * in response to target's NOPIN w/ TTT != FFFFFFFF ++ * ++ * prepare and post a nopout request WQE to CNIC firmware ++ */ ++/* ++ */ ++int bnx2i_send_iscsi_nopout(struct bnx2i_conn *conn, struct bnx2i_cmd *cmd, ++ char *datap, int data_len) ++{ ++ u8 wqe_flags; ++ int unsol; ++ struct iscsi_nop_out_request *nopout_wqe; ++ struct iscsi_nopout *nop_hdr; ++ ++ if (!conn->ep) ++ return -EINVAL; ++ ++ /* Check if it's an unsolicited pdu or a response to target's nopin */ ++ if (cmd->ttt == ISCSI_RESERVED_TAG) { ++conn->sess->unsol_noopout_count++; ++ nop_hdr = (struct iscsi_nopout *) &conn->gen_pdu.nopout_hdr; ++ unsol = 1; ++ wqe_flags = 0; ++ } else { ++conn->sess->noopout_resp_count++; ++ nop_hdr = (struct iscsi_nopout *) &conn->gen_pdu.nopin_hdr; ++ unsol = 0; ++ wqe_flags = ISCSI_NOP_OUT_REQUEST_LOCAL_COMPLETION; ++ } ++ ++ nopout_wqe = (struct iscsi_nop_out_request *) conn->ep->qp.sq_prod_qe; ++ memset(nopout_wqe, 0, sizeof(struct iscsi_nop_out_request)); ++ nopout_wqe->op_code = (ISCSI_OP_NOOP_OUT | ISCSI_OP_IMMEDIATE); ++ nopout_wqe->op_attr = ISCSI_FLAG_CMD_FINAL; ++ memcpy(nopout_wqe->lun, nop_hdr->lun, 8); ++ ++ if (test_bit(BNX2I_NX2_DEV_57710, &conn->ep->hba->cnic_dev_type)) { ++ u32 tmp = nopout_wqe->lun[0]; ++ /* 57710 requires LUN field to be swapped */ ++ nopout_wqe->lun[0] = nopout_wqe->lun[1]; ++ nopout_wqe->lun[1] = tmp; ++ } ++ nopout_wqe->ttt = cmd->ttt; ++ nopout_wqe->itt = ((u16) cmd->req.itt | ++ (ISCSI_TASK_TYPE_MPATH << ++ ISCSI_TMF_REQUEST_TYPE_SHIFT)); ++ nopout_wqe->flags = wqe_flags; ++ nopout_wqe->cmd_sn = conn->sess->cmdsn; ++ nopout_wqe->data_length = data_len; ++ if (data_len) { ++ /* handle payload data, not required in first release */ ++ printk(KERN_ALERT "NOPOUT: WARNING!! payload len != 0\n"); ++ } else { ++ nopout_wqe->bd_list_addr_lo = ++ (u32) conn->sess->hba->mp_dma_buf.pgtbl_map; ++ nopout_wqe->bd_list_addr_hi = ++ (u32) ((u64) conn->sess->hba->mp_dma_buf.pgtbl_map >> 32); ++ nopout_wqe->num_bds = 1; ++ } ++ nopout_wqe->cq_index = 0; /* CQ# used for completion, 5771x only */ ++ ++ conn->num_nopout_pdus++; ++ bnx2i_ring_dbell_update_sq_params(conn, 1); ++ ++ conn->sess->last_nooput_sn = conn->sess->cmdsn; ++ conn->sess->last_nooput_posted = jiffies; ++ conn->sess->noopout_posted_count++; ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_send_iscsi_logout - post iSCSI logout request WQE to hardware ++ * ++ * @conn: iscsi connection ++ * @cmd: driver command structure which is requesting ++ * a WQE to sent to chip for further processing ++ * ++ * prepare and post logout request WQE to CNIC firmware ++ */ ++int bnx2i_send_iscsi_logout(struct bnx2i_conn *conn, struct bnx2i_cmd *cmd) ++{ ++ struct iscsi_logout_request *logout_wqe; ++ struct iscsi_logout *logout_hdr; ++ struct bnx2i_hba *hba = conn->sess->hba; ++ struct Scsi_Host *shost; ++ ++ if (!conn->ep) ++ return -EINVAL; ++ ++ shost = bnx2i_conn_get_shost(conn); ++ ++ conn->sess->state = BNX2I_SESS_IN_LOGOUT; ++ ++ logout_hdr = (struct iscsi_logout *) &conn->gen_pdu.pdu_hdr; ++ ++ logout_wqe = (struct iscsi_logout_request *) conn->ep->qp.sq_prod_qe; ++ memset(logout_wqe, 0x00, sizeof(struct iscsi_logout_request)); ++ ++ logout_wqe->op_code = (logout_hdr->opcode | ISCSI_OP_IMMEDIATE); ++ logout_wqe->op_attr = ++ logout_hdr->flags | ISCSI_LOGOUT_REQUEST_ALWAYS_ONE; ++ logout_wqe->itt = ((u16) cmd->req.itt | ++ (ISCSI_TASK_TYPE_MPATH << ++ ISCSI_LOGOUT_REQUEST_TYPE_SHIFT)); ++ logout_wqe->data_length = 0; ++ logout_wqe->cmd_sn = conn->sess->cmdsn; ++ logout_wqe->cid = conn->conn_cid; ++ ++ logout_wqe->bd_list_addr_lo = (u32) hba->mp_dma_buf.pgtbl_map; ++ logout_wqe->bd_list_addr_hi = ++ (u32) ((u64) hba->mp_dma_buf.pgtbl_map >> 32); ++ logout_wqe->num_bds = 1; ++ logout_wqe->cq_index = 0; /* CQ# used for completion, 5771x only */ ++ ++ conn->num_logout_req_pdus++; ++ bnx2i_ring_dbell_update_sq_params(conn, 1); ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_update_iscsi_conn - post iSCSI logout request WQE to hardware ++ * ++ * @conn: iscsi connection which requires iscsi parameter update ++ * ++ * sends down iSCSI Conn Update request to move iSCSI conn to FFP ++ */ ++int bnx2i_update_iscsi_conn(struct bnx2i_conn *conn) ++{ ++ struct bnx2i_hba *hba = conn->sess->hba; ++ struct kwqe *kwqe_arr[2]; ++ struct iscsi_kwqe_conn_update *update_wqe; ++ struct iscsi_kwqe_conn_update conn_update_kwqe; ++ int rc = -EINVAL; ++ ++ update_wqe = &conn_update_kwqe; ++ ++ update_wqe->hdr.op_code = ISCSI_KWQE_OPCODE_UPDATE_CONN; ++ update_wqe->hdr.flags = ++ (ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT); ++ ++ /* 57710 requires conn context id to be passed as is */ ++ if (test_bit(BNX2I_NX2_DEV_57710, &conn->ep->hba->cnic_dev_type)) ++ update_wqe->context_id = conn->ep->ep_cid; ++ else ++ update_wqe->context_id = (conn->ep->ep_cid >> 7); ++ update_wqe->conn_flags = 0; ++ if (conn->header_digest_en) ++ update_wqe->conn_flags |= ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST; ++ if (conn->data_digest_en) ++ update_wqe->conn_flags |= ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST; ++ if (conn->sess->initial_r2t) ++ update_wqe->conn_flags |= ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T; ++ if (conn->sess->imm_data) ++ update_wqe->conn_flags |= ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA; ++ ++ update_wqe->max_send_pdu_length = conn->max_data_seg_len_xmit; ++ update_wqe->max_recv_pdu_length = conn->max_data_seg_len_recv; ++ update_wqe->first_burst_length = conn->sess->first_burst_len; ++ update_wqe->max_burst_length = conn->sess->max_burst_len; ++ update_wqe->exp_stat_sn = conn->exp_statsn; ++ update_wqe->max_outstanding_r2ts = conn->sess->max_r2t; ++ update_wqe->session_error_recovery_level = conn->sess->erl; ++ printk(KERN_ALERT "bnx2i: conn update - MBL 0x%x FBL 0x%x" ++ "MRDSL_I 0x%x MRDSL_T 0x%x \n", ++ update_wqe->max_burst_length, ++ update_wqe->first_burst_length, ++ update_wqe->max_recv_pdu_length, ++ update_wqe->max_send_pdu_length); ++ ++ kwqe_arr[0] = (struct kwqe *) update_wqe; ++ if (hba->cnic && hba->cnic->submit_kwqes) ++ rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, 1); ++ ++ return rc; ++} ++ ++ ++/** ++ * bnx2i_ep_ofld_timer - post iSCSI logout request WQE to hardware ++ * ++ * @data: endpoint (transport handle) structure pointer ++ * ++ * routine to handle connection offload/destroy request timeout ++ */ ++void bnx2i_ep_ofld_timer(unsigned long data) ++{ ++ struct bnx2i_endpoint *ep = (struct bnx2i_endpoint *) data; ++ ++ if (ep->state == EP_STATE_OFLD_START) { ++ printk(KERN_ALERT "bnx2i: ofld_timer: CONN_OFLD timeout\n"); ++ ep->state = EP_STATE_OFLD_FAILED; ++ } else if (ep->state == EP_STATE_DISCONN_START) { ++ printk(KERN_ALERT "bnx2i: ofld_timer: cid %d CONN_DISCON timeout\n", ep->ep_iscsi_cid); ++ ep->state = EP_STATE_DISCONN_TIMEDOUT; ++ } else if (ep->state == EP_STATE_CLEANUP_START) { ++ printk(KERN_ALERT "bnx2i: ofld_timer: cid %d CONN_CLEANUP timeout\n", ep->ep_iscsi_cid); ++ ep->state = EP_STATE_CLEANUP_FAILED; ++ } ++ ++ wake_up_interruptible(&ep->ofld_wait); ++} ++ ++ ++static int bnx2i_power_of2(u32 val) ++{ ++ u32 power = 0; ++ if (val & (val - 1)) ++ return power; ++ val--; ++ while (val) { ++ val = val >> 1; ++ power++; ++ } ++ return power; ++} ++ ++ ++/** ++ * bnx2i_send_cmd_cleanup_req - send iscsi cmd context clean-up request ++ * ++ * @hba: adapter structure pointer ++ * @cmd: driver command structure which is requesting ++ * a WQE to sent to chip for further processing ++ * ++ * prepares and posts CONN_OFLD_REQ1/2 KWQE ++ */ ++void bnx2i_send_cmd_cleanup_req(struct bnx2i_hba *hba, struct bnx2i_cmd *cmd) ++{ ++ struct iscsi_cleanup_request *cmd_cleanup; ++ u32 dword; ++ ++ cmd_cleanup = ++ (struct iscsi_cleanup_request *) cmd->conn->ep->qp.sq_prod_qe; ++ memset(cmd_cleanup, 0x00, sizeof(struct iscsi_cleanup_request)); ++ ++ cmd_cleanup->op_code = ISCSI_OPCODE_CLEANUP_REQUEST; ++ ++ if (cmd->req.op_attr & ISCSI_CMD_REQUEST_READ) ++ dword = (ISCSI_TASK_TYPE_READ << ISCSI_CMD_REQUEST_TYPE_SHIFT); ++ else ++ dword = (ISCSI_TASK_TYPE_WRITE << ISCSI_CMD_REQUEST_TYPE_SHIFT); ++ cmd_cleanup->itt = (dword | cmd->req.itt); ++ cmd_cleanup->cq_index = 0; /* CQ# used for completion, 5771x only */ ++ ++ bnx2i_ring_dbell_update_sq_params(cmd->conn, 1); ++} ++ ++ ++/** ++ * bnx2i_send_conn_destroy - initiates iscsi connection teardown process ++ * ++ * @hba: adapter structure pointer ++ * @ep: endpoint (transport indentifier) structure ++ * ++ * this routine prepares and posts CONN_OFLD_REQ1/2 KWQE to initiate ++ * iscsi connection context clean-up process ++ */ ++int bnx2i_send_conn_destroy(struct bnx2i_hba *hba, struct bnx2i_endpoint *ep) ++{ ++ struct kwqe *kwqe_arr[2]; ++ struct iscsi_kwqe_conn_destroy conn_cleanup; ++ int rc = -EINVAL; ++ ++ memset(&conn_cleanup, 0x00, sizeof(struct iscsi_kwqe_conn_destroy)); ++ ++ conn_cleanup.hdr.op_code = ISCSI_KWQE_OPCODE_DESTROY_CONN; ++ conn_cleanup.hdr.flags = ++ (ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT); ++ /* 57710 requires conn context id to be passed as is */ ++ if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) ++ conn_cleanup.context_id = ep->ep_cid; ++ else ++ conn_cleanup.context_id = (ep->ep_cid >> 7); ++ ++ conn_cleanup.reserved0 = (u16)ep->ep_iscsi_cid; ++ ++ kwqe_arr[0] = (struct kwqe *) &conn_cleanup; ++ if (hba->cnic && hba->cnic->submit_kwqes) ++ rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, 1); ++ ++ return rc; ++} ++ ++ ++/** ++ * bnx2i_570x_send_conn_ofld_req - initiates iscsi connection context setup process ++ * ++ * @hba: adapter structure pointer ++ * @ep: endpoint (transport indentifier) structure ++ * ++ * 5706/5708/5709 specific - prepares and posts CONN_OFLD_REQ1/2 KWQE ++ */ ++static int bnx2i_570x_send_conn_ofld_req(struct bnx2i_hba *hba, ++ struct bnx2i_endpoint *ep) ++{ ++ struct kwqe *kwqe_arr[2]; ++ struct iscsi_kwqe_conn_offload1 ofld_req1; ++ struct iscsi_kwqe_conn_offload2 ofld_req2; ++ dma_addr_t dma_addr; ++ int num_kwqes = 2; ++ int rc = -EINVAL; ++ u32 *ptbl; ++ ++ ofld_req1.hdr.op_code = ISCSI_KWQE_OPCODE_OFFLOAD_CONN1; ++ ofld_req1.hdr.flags = ++ (ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT); ++ ++ ofld_req1.iscsi_conn_id = (u16) ep->ep_iscsi_cid; ++ ++ dma_addr = ep->qp.sq_dma.pgtbl_map; ++ ofld_req1.sq_page_table_addr_lo = (u32) dma_addr; ++ ofld_req1.sq_page_table_addr_hi = (u32) ((u64) dma_addr >> 32); ++ ++ dma_addr = ep->qp.cq_dma.pgtbl_map; ++ ofld_req1.cq_page_table_addr_lo = (u32) dma_addr; ++ ofld_req1.cq_page_table_addr_hi = (u32) ((u64) dma_addr >> 32); ++ ++ ofld_req2.hdr.op_code = ISCSI_KWQE_OPCODE_OFFLOAD_CONN2; ++ ofld_req2.hdr.flags = ++ (ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT); ++ ++ dma_addr = ep->qp.rq_dma.pgtbl_map; ++ ofld_req2.rq_page_table_addr_lo = (u32) dma_addr; ++ ofld_req2.rq_page_table_addr_hi = (u32) ((u64) dma_addr >> 32); ++ ++ ptbl = (u32 *) ep->qp.sq_dma.pgtbl; ++ ++ ofld_req2.sq_first_pte.hi = *ptbl++; ++ ofld_req2.sq_first_pte.lo = *ptbl; ++ ++ ptbl = (u32 *) ep->qp.cq_dma.pgtbl; ++ ofld_req2.cq_first_pte.hi = *ptbl++; ++ ofld_req2.cq_first_pte.lo = *ptbl; ++ ++ kwqe_arr[0] = (struct kwqe *) &ofld_req1; ++ kwqe_arr[1] = (struct kwqe *) &ofld_req2; ++ ofld_req2.num_additional_wqes = 0; ++ ++ if (hba->cnic && hba->cnic->submit_kwqes) ++ rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); ++ ++ return rc; ++} ++ ++ ++/** ++ * bnx2i_5771x_send_conn_ofld_req - initiates iscsi connection context setup process ++ * ++ * @hba: adapter structure pointer ++ * @ep: endpoint (transport indentifier) structure ++ * ++ * 57710 specific - prepares and posts CONN_OFLD_REQ1/2 KWQE ++ */ ++static int bnx2i_5771x_send_conn_ofld_req(struct bnx2i_hba *hba, ++ struct bnx2i_endpoint *ep) ++{ ++ struct kwqe *kwqe_arr[5]; ++ struct iscsi_kwqe_conn_offload1 ofld_req1; ++ struct iscsi_kwqe_conn_offload2 ofld_req2; ++ struct iscsi_kwqe_conn_offload3 ofld_req3[1]; ++ dma_addr_t dma_addr; ++ int num_kwqes = 2; ++ int rc = -EINVAL; ++ u32 *ptbl; ++ ++ ofld_req1.hdr.op_code = ISCSI_KWQE_OPCODE_OFFLOAD_CONN1; ++ ofld_req1.hdr.flags = ++ (ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT); ++ ++ ofld_req1.iscsi_conn_id = (u16) ep->ep_iscsi_cid; ++ ++ dma_addr = ep->qp.sq_dma.pgtbl_map + ISCSI_SQ_DB_SIZE; ++ ofld_req1.sq_page_table_addr_lo = (u32) dma_addr; ++ ofld_req1.sq_page_table_addr_hi = (u32) ((u64) dma_addr >> 32); ++ ++ dma_addr = ep->qp.cq_dma.pgtbl_map + ISCSI_CQ_DB_SIZE; ++ ofld_req1.cq_page_table_addr_lo = (u32) dma_addr; ++ ofld_req1.cq_page_table_addr_hi = (u32) ((u64) dma_addr >> 32); ++ ++ ofld_req2.hdr.op_code = ISCSI_KWQE_OPCODE_OFFLOAD_CONN2; ++ ofld_req2.hdr.flags = ++ (ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT); ++ ++ dma_addr = ep->qp.rq_dma.pgtbl_map + ISCSI_RQ_DB_SIZE; ++ ofld_req2.rq_page_table_addr_lo = (u32) dma_addr; ++ ofld_req2.rq_page_table_addr_hi = (u32) ((u64) dma_addr >> 32); ++ ++ ptbl = (u32 *)((u8 *)ep->qp.sq_dma.pgtbl + ISCSI_SQ_DB_SIZE); ++ ofld_req2.sq_first_pte.hi = *ptbl++; ++ ofld_req2.sq_first_pte.lo = *ptbl; ++ ++ ptbl = (u32 *)((u8 *)ep->qp.cq_dma.pgtbl + ISCSI_CQ_DB_SIZE); ++ ofld_req2.cq_first_pte.hi = *ptbl++; ++ ofld_req2.cq_first_pte.lo = *ptbl; ++ ++ kwqe_arr[0] = (struct kwqe *) &ofld_req1; ++ kwqe_arr[1] = (struct kwqe *) &ofld_req2; ++ ++ ofld_req2.num_additional_wqes = 1; ++ memset(ofld_req3, 0x00, sizeof(ofld_req3[0])); ++ ptbl = (u32 *)((u8 *)ep->qp.rq_dma.pgtbl + ISCSI_RQ_DB_SIZE); ++ ofld_req3[0].qp_first_pte[0].hi = *ptbl++; ++ ofld_req3[0].qp_first_pte[0].lo = *ptbl; ++ ++ kwqe_arr[2] = (struct kwqe *) ofld_req3; ++ /* need if we decide to go with multiple KCQE's per conn */ ++ num_kwqes += 1; ++ ++ if (hba->cnic && hba->cnic->submit_kwqes) ++ rc =hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); ++ ++ return rc; ++} ++ ++/** ++ * bnx2i_send_conn_ofld_req - initiates iscsi connection context setup process ++ * ++ * @hba: adapter structure pointer ++ * @ep: endpoint (transport indentifier) structure ++ * ++ * this routine prepares and posts CONN_OFLD_REQ1/2 KWQE ++ */ ++int bnx2i_send_conn_ofld_req(struct bnx2i_hba *hba, struct bnx2i_endpoint *ep) ++{ ++ int rc; ++ ++ if (test_bit(BNX2I_NX2_DEV_57710, &hba->cnic_dev_type)) ++ rc = bnx2i_5771x_send_conn_ofld_req(hba, ep); ++ else ++ rc = bnx2i_570x_send_conn_ofld_req(hba, ep); ++ ++ return rc; ++} ++ ++ ++/** ++ * bnx2i_alloc_qp_resc - allocates requires resources for QP (transport layer ++ * for iSCSI connection) ++ * ++ * @hba: adapter structure pointer ++ * @ep: endpoint (transport indentifier) structure ++ * ++ * Allocate QP resources, DMA'able memory for SQ/RQ/CQ and page tables. ++ * EP structure elements such as producer/consumer indexes/pointers, ++ * queue sizes and page table contents are setup ++ */ ++int bnx2i_alloc_qp_resc(struct bnx2i_hba *hba, struct bnx2i_endpoint *ep) ++{ ++ struct bnx2i_5771x_cq_db *cq_db; ++ u32 num_que_elements; ++ int mem_size; ++ int sq_pgtbl_off = 0; ++ int cq_pgtbl_off = 0; ++ int rq_pgtbl_off = 0; ++ ++ if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) { ++ sq_pgtbl_off = ISCSI_SQ_DB_SIZE; ++ cq_pgtbl_off = ISCSI_CQ_DB_SIZE; ++ rq_pgtbl_off = ISCSI_RQ_DB_SIZE; ++ } ++ ++ ep->hba = hba; ++ ep->conn = NULL; ++ ep->ep_cid = ep->ep_iscsi_cid = ep->ep_pg_cid = 0; ++ ++ /* Allocate page table memory for SQ which is page aligned */ ++ mem_size = hba->max_sqes * BNX2I_SQ_WQE_SIZE; ++ mem_size = (mem_size + (PAGE_SIZE - 1)) & PAGE_MASK; ++ num_que_elements = hba->max_sqes; ++ ++ if (bnx2i_alloc_dma(hba, &ep->qp.sq_dma, mem_size, ++ BNX2I_TBL_TYPE_PG, sq_pgtbl_off)) ++ goto error; ++ ++ memset(ep->qp.sq_virt, 0x00, mem_size); ++ ++ ep->qp.sq_first_qe = (struct sqe *) ep->qp.sq_virt; ++ ep->qp.sq_prod_qe = ep->qp.sq_first_qe; ++ ep->qp.sq_last_qe = &ep->qp.sq_first_qe[num_que_elements - 1]; ++ ep->qp.sq_prod_idx = 0; ++ ++ /* Allocate page table memory for CQ which is page aligned */ ++ mem_size = hba->max_cqes * BNX2I_CQE_SIZE; ++ mem_size = (mem_size + (PAGE_SIZE - 1)) & PAGE_MASK; ++ num_que_elements = hba->max_cqes; ++ ++ if (bnx2i_alloc_dma(hba, &ep->qp.cq_dma, mem_size, ++ BNX2I_TBL_TYPE_PG, cq_pgtbl_off)) ++ goto error; ++ ++ memset (ep->qp.cq_virt, 0x00, mem_size); ++ ++ ep->qp.cq_first_qe = (struct cqe *) ep->qp.cq_virt; ++ ep->qp.cq_cons_qe = ep->qp.cq_first_qe; ++ ep->qp.cq_last_qe = &ep->qp.cq_first_qe[num_que_elements - 1]; ++ ep->qp.cq_cons_idx = 0; ++ ep->qp.cqe_left = num_que_elements; ++ ep->qp.cqe_exp_seq_sn = ISCSI_INITIAL_SN; ++ ep->qp.cqe_size = hba->max_cqes; ++ ++ /* Invalidate all EQ CQE index, req only for 57710 */ ++ cq_db = (struct bnx2i_5771x_cq_db *) ep->qp.cq_dma.pgtbl; ++ memset(cq_db->sqn, 0xFF, sizeof(cq_db->sqn[0]) * BNX2X_MAX_CQS); ++ ++ /* Allocate page table memory for RQ which is page aligned */ ++ mem_size = hba->max_rqes * BNX2I_RQ_WQE_SIZE; ++ mem_size = (mem_size + (PAGE_SIZE - 1)) & PAGE_MASK; ++ num_que_elements = hba->max_rqes; ++ ++ if (bnx2i_alloc_dma(hba, &ep->qp.rq_dma, mem_size, ++ BNX2I_TBL_TYPE_PG, rq_pgtbl_off)) ++ goto error; ++ ++ ep->qp.rq_first_qe = (struct rqe *) ep->qp.rq_virt; ++ ep->qp.rq_prod_qe = ep->qp.rq_first_qe; ++ ep->qp.rq_cons_qe = ep->qp.rq_first_qe; ++ ep->qp.rq_last_qe = &ep->qp.rq_first_qe[num_que_elements - 1]; ++ ep->qp.rq_prod_idx = 0x8000; ++ ep->qp.rq_cons_idx = 0; ++ ep->qp.rqe_left = num_que_elements; ++ ++ return 0; ++ ++error: ++ bnx2i_free_qp_resc(hba, ep); ++ return -ENOMEM; ++} ++ ++ ++ ++/** ++ * bnx2i_free_qp_resc - free memory resources held by QP ++ * ++ * @hba: adapter structure pointer ++ * @ep: endpoint (transport indentifier) structure ++ * ++ * Free QP resources - SQ/RQ/CQ memory and page tables. ++ */ ++void bnx2i_free_qp_resc(struct bnx2i_hba *hba, struct bnx2i_endpoint *ep) ++{ ++ if (ep->qp.ctx_base) { ++ iounmap(ep->qp.ctx_base); ++ ep->qp.ctx_base = NULL; ++ } ++ ++ bnx2i_free_dma(hba, &ep->qp.sq_dma); ++ bnx2i_free_dma(hba, &ep->qp.cq_dma); ++ bnx2i_free_dma(hba, &ep->qp.rq_dma); ++} ++ ++extern unsigned int error_mask1, error_mask2; ++extern unsigned int en_tcp_dack; ++extern u64 iscsi_error_mask; ++ ++/** ++ * bnx2i_send_fw_iscsi_init_msg - initiates initial handshake with iscsi f/w ++ * ++ * @hba: adapter structure pointer ++ * ++ * Send down iscsi_init KWQEs which initiates the initial handshake with the f/w ++ * This results in iSCSi support validation and on-chip context manager ++ * initialization. Firmware completes this handshake with a CQE carrying ++ * the result of iscsi support validation. Parameter carried by ++ * iscsi init request determines the number of offloaded connection and ++ * tolerance level for iscsi protocol violation this hba/chip can support ++ */ ++int bnx2i_send_fw_iscsi_init_msg(struct bnx2i_hba *hba) ++{ ++ struct kwqe *kwqe_arr[3]; ++ struct iscsi_kwqe_init1 iscsi_init; ++ struct iscsi_kwqe_init2 iscsi_init2; ++ int rc = 0; ++ u64 mask64; ++ ++ bnx2i_adjust_qp_size(hba); ++ ++ iscsi_init.flags = ++ ISCSI_PAGE_SIZE_4K << ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT; ++ if (en_tcp_dack) ++ iscsi_init.flags |= ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE; ++ iscsi_init.reserved0 = 0; ++ iscsi_init.num_cqs = 1; ++ iscsi_init.hdr.op_code = ISCSI_KWQE_OPCODE_INIT1; ++ iscsi_init.hdr.flags = ++ (ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT); ++ ++ iscsi_init.dummy_buffer_addr_lo = (u32) hba->mp_dma_buf.mapping; ++ iscsi_init.dummy_buffer_addr_hi = ++ (u32) ((u64) hba->mp_dma_buf.mapping >> 32); ++ ++ hba->ctx_ccell_tasks = ++ ((hba->num_ccell & 0xFFFF) | (hba->max_sqes << 16)); ++ iscsi_init.num_ccells_per_conn = hba->num_ccell; ++ iscsi_init.num_tasks_per_conn = hba->max_sqes; ++ iscsi_init.sq_wqes_per_page = PAGE_SIZE / BNX2I_SQ_WQE_SIZE; ++ iscsi_init.sq_num_wqes = hba->max_sqes; ++ iscsi_init.cq_log_wqes_per_page = ++ (u8) bnx2i_power_of2(PAGE_SIZE / BNX2I_CQE_SIZE); ++ iscsi_init.cq_num_wqes = hba->max_cqes; ++ iscsi_init.cq_num_pages = (hba->max_cqes * BNX2I_CQE_SIZE + ++ (PAGE_SIZE - 1)) / PAGE_SIZE; ++ iscsi_init.sq_num_pages = (hba->max_sqes * BNX2I_SQ_WQE_SIZE + ++ (PAGE_SIZE - 1)) / PAGE_SIZE; ++ iscsi_init.rq_buffer_size = BNX2I_RQ_WQE_SIZE; ++ iscsi_init.rq_num_wqes = hba->max_rqes; ++ ++ ++ iscsi_init2.hdr.op_code = ISCSI_KWQE_OPCODE_INIT2; ++ iscsi_init2.hdr.flags = ++ (ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT); ++ iscsi_init2.max_cq_sqn = hba->max_cqes * 2 + 1; ++ mask64 = 0x0ULL; ++ mask64 |= ( ++ /* CISCO MDS */ ++ (1UL << ++ ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_TTT_NOT_RSRV) | ++ /* HP MSA1510i */ ++ (1UL << ++ ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_EXP_DATASN) | ++ /* EMC */ ++ (1ULL << ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_LUN)); ++ if (error_mask1) ++ iscsi_init2.error_bit_map[0] = error_mask1; ++ else { ++ iscsi_init2.error_bit_map[0] = (u32) mask64; ++ } ++ if (error_mask2) ++ iscsi_init2.error_bit_map[1] = error_mask2; ++ else ++ iscsi_init2.error_bit_map[1] = (u32) (mask64 >> 32); ++ ++ iscsi_error_mask = mask64; ++ ++ kwqe_arr[0] = (struct kwqe *) &iscsi_init; ++ kwqe_arr[1] = (struct kwqe *) &iscsi_init2; ++ ++ if (hba->cnic && hba->cnic->submit_kwqes) { ++ rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, 2); ++ } ++ return rc; ++} ++ ++ ++/** ++ * bnx2i_complete_cmd - completion CQE processing ++ * ++ * @sess: iscsi sess pointer ++ * @cmd: command pointer ++ * ++ * process SCSI CMD Response CQE & complete the request to SCSI-ML ++ */ ++int bnx2i_complete_cmd(struct bnx2i_sess *sess, struct bnx2i_cmd *cmd) ++{ ++ struct scsi_cmnd *sc; ++ struct Scsi_Host *shost; ++ ++ spin_lock_bh(&sess->lock); ++ sc = cmd->scsi_cmd; ++ if (!sc) { ++ spin_unlock_bh(&sess->lock); ++ printk(KERN_ALERT "bnx2i: command already completed\n"); ++ return -EINVAL; ++ } ++ ++ if ((sc->result & (DID_OK << 16)) != (DID_OK << 16)) ++ printk("bnx2i: completing sc %p with bad status\n", sc); ++ ++ cmd->scsi_cmd = NULL; ++ sess->active_cmd_count--; ++ sc->SCp.ptr = NULL; ++ bnx2i_free_cmd(sess, cmd); ++ spin_unlock_bh(&sess->lock); ++ ++ shost = bnx2i_sess_get_shost(sess); ++ spin_lock_bh(shost->host_lock); ++ sc->scsi_done(sc); ++ spin_unlock_bh(shost->host_lock); ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_process_scsi_cmd_resp - this function handles scsi command ++ * completion CQE processing ++ * ++ * @conn: iscsi connection ++ * @cqe: pointer to newly DMA'ed CQE entry for processing ++ * ++ * process SCSI CMD Response CQE & complete the request to SCSI-ML ++ */ ++static int bnx2i_process_scsi_cmd_resp(struct bnx2i_conn *conn, ++ struct cqe *cqe) ++{ ++ struct iscsi_cmd_response *resp_cqe; ++ struct bnx2i_cmd *cmd; ++ struct scsi_cmnd *sc; ++ u32 itt; ++ ++ resp_cqe = (struct iscsi_cmd_response *) cqe; ++ ++ bnx2i_update_cmd_sequence(conn->sess, resp_cqe->exp_cmd_sn, ++ resp_cqe->max_cmd_sn); ++ ++ itt = (resp_cqe->itt & ISCSI_CMD_RESPONSE_INDEX); ++ cmd = get_cmnd(conn->sess, itt); ++ spin_lock(&conn->sess->lock); ++ if (!cmd || !cmd->scsi_cmd) { ++ /* Driver might have failed due to LUN/TARGET RESET and target ++ * might me completing the command with check condition, it's ok ++ * to drop this completion ++ */ ++ printk(KERN_ALERT "bnx2i: scsi rsp ITT=%x not active\n", itt); ++ spin_unlock(&conn->sess->lock); ++ return 0; ++ } ++ ++ if (atomic_read(&cmd->cmd_state) == ISCSI_CMD_STATE_INITIATED) { ++ /* remove command from the active list because it is ++ * gauranteed this command will be completed to SCSI-ML ++ */ ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_CMPL_RCVD); ++ list_del_init(&cmd->link); ++ } else { ++ printk(KERN_ALERT "%s: WaTcH: ITT=%x is being aborted\n", ++ __FUNCTION__, itt); ++ /* Driver will hold on to CMD till it TMF completes */ ++ } ++ spin_unlock(&conn->sess->lock); ++ ++ if (cmd->req.op_attr & ISCSI_CMD_REQUEST_READ) { ++ conn->num_datain_pdus += ++ resp_cqe->task_stat.read_stat.num_data_outs; ++ conn->total_data_octets_rcvd += ++ cmd->req.total_data_transfer_length; ++ } else { ++ conn->num_dataout_pdus += ++ resp_cqe->task_stat.read_stat.num_data_outs; ++ conn->num_r2t_pdus += ++ resp_cqe->task_stat.read_stat.num_r2ts; ++ conn->total_data_octets_sent += ++ cmd->req.total_data_transfer_length; ++ } ++ ++ sc = cmd->scsi_cmd; ++ cmd->scsi_status_rcvd = 1; ++ cmd->req.itt &= ISCSI_CMD_RESPONSE_INDEX; ++ ++ bnx2i_process_scsi_resp(cmd, resp_cqe); ++ ++ bnx2i_iscsi_unmap_sg_list(conn->sess->hba, cmd); ++ ++ if (atomic_read(&cmd->cmd_state) == ISCSI_CMD_STATE_CMPL_RCVD) { ++ bnx2i_complete_cmd(conn->sess, cmd); ++ } else if (atomic_read(&cmd->cmd_state)){ ++ /* cmd->cmd_state could be ABORT_PEND, ABORT_REQ ABORT_PEND ++ * ABORT_COMPL, CLEANUP_START, CLEANUP_PEND, CLEANUP_CMPL ++ * hold on to the command till Wait for TMF response ++ * is received ++ */ ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_COMPLETED); ++ } ++ ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_process_login_resp - this function handles iscsi login response ++ * CQE processing ++ * ++ * @conn: iscsi connection ++ * @cqe: pointer to newly DMA'ed CQE entry for processing ++ * ++ * process Login Response CQE & complete it to open-iscsi user daemon ++ */ ++static int bnx2i_process_login_resp(struct bnx2i_conn *conn, struct cqe *cqe) ++{ ++ struct bnx2i_cmd *cmd; ++ struct iscsi_login_response *login; ++ struct iscsi_login_rsp *login_resp; ++ u32 itt; ++ u32 dword; ++ int pld_len; ++ int pad_len; ++ ++ login = (struct iscsi_login_response *) cqe; ++ login_resp = (struct iscsi_login_rsp *) &conn->gen_pdu.resp_hdr; ++ itt = (login->itt & ISCSI_LOGIN_RESPONSE_INDEX); ++ ++ cmd = get_cmnd(conn->sess, itt); ++ if (!cmd) { ++ printk(KERN_WARNING "bnx2i - itt=%x not valid\n", itt); ++ return -EINVAL; ++ } ++ ++ login_resp->opcode = login->op_code; ++ login_resp->flags = login->response_flags; ++ login_resp->max_version = login->version_max; ++ login_resp->active_version = login->version_active; ++ login_resp->hlength = 0; ++ ++ dword = login->data_length; ++ login_resp->dlength[2] = (u8) dword; ++ login_resp->dlength[1] = (u8) (dword >> 8); ++ login_resp->dlength[0] = (u8) (dword >> 16); ++ ++ memcpy(login_resp->isid, &login->isid_lo, 6); ++ login_resp->tsih = htons(login->tsih); ++ login_resp->itt = conn->gen_pdu.pdu_hdr.itt; ++ login_resp->statsn = htonl(login->stat_sn); ++ ++ conn->sess->cmdsn = login->exp_cmd_sn; ++ login_resp->exp_cmdsn = htonl(login->exp_cmd_sn); ++ login_resp->max_cmdsn = htonl(login->max_cmd_sn); ++ login_resp->status_class = login->status_class; ++ login_resp->status_detail = login->status_detail; ++ pld_len = login->data_length; ++ conn->gen_pdu.resp_wr_ptr = conn->gen_pdu.resp_buf + pld_len; ++ ++ pad_len = 0; ++ if (pld_len & 0x3) ++ pad_len = 4 - (pld_len % 4); ++ ++ if (pad_len) { ++ int i = 0; ++ for (i = 0; i < pad_len; i++) { ++ conn->gen_pdu.resp_wr_ptr[0] = 0; ++ conn->gen_pdu.resp_wr_ptr++; ++ } ++ } ++ cmd->iscsi_opcode = 0; ++ ++ bnx2i_indicate_login_resp(conn); ++ return 0; ++} ++ ++/** ++ * bnx2i_process_tmf_resp - this function handles iscsi TMF response ++ * CQE processing ++ * ++ * @conn: iscsi connection ++ * @cqe: pointer to newly DMA'ed CQE entry for processing ++ * ++ * process iSCSI TMF Response CQE and wake up the driver eh thread. ++ */ ++static int bnx2i_process_tmf_resp(struct bnx2i_conn *conn, struct cqe *cqe) ++{ ++ u32 itt; ++ struct bnx2i_cmd *cmd; ++ struct bnx2i_cmd *aborted_cmd; ++ struct iscsi_tmf_response *tmf_cqe; ++ ++ tmf_cqe = (struct iscsi_tmf_response *) cqe; ++ printk("%s: ITT %x\n", __FUNCTION__, tmf_cqe->itt); ++ itt = (tmf_cqe->itt & ISCSI_TMF_RESPONSE_INDEX); ++ cmd = get_cmnd(conn->sess, itt); ++ if (!cmd) { ++ printk(KERN_ALERT "tmf_resp: ITT 0x%x is not active\n", ++ tmf_cqe->itt); ++ return -EINVAL; ++ } ++ ++ bnx2i_update_cmd_sequence(conn->sess, tmf_cqe->exp_cmd_sn, ++ tmf_cqe->max_cmd_sn); ++ ++ if (conn->sess->recovery_state) { ++ printk("%s: ignore TMF resp as sess is already in recovery mode\n", __FUNCTION__); ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_FAILED); ++ wake_up(&cmd->conn->sess->er_wait); ++ return -1; ++ } ++ ++ cmd->tmf_response = tmf_cqe->response; ++ if (cmd->tmf_func == ISCSI_TM_FUNC_LOGICAL_UNIT_RESET || ++ cmd->tmf_func == ISCSI_TM_FUNC_TARGET_WARM_RESET) { ++ if (tmf_cqe->response == ISCSI_TMF_RSP_COMPLETE) ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_COMPLETED); ++ else ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_FAILED); ++ printk("%s : LUN/TGT RESET TMF RESP, status %x\n", ++ __FUNCTION__, tmf_cqe->response); ++ goto reset_done; ++ } ++ ++ aborted_cmd = cmd->tmf_ref_cmd; ++ ++ if (tmf_cqe->response == ISCSI_TMF_RSP_COMPLETE) { ++ if (aborted_cmd->scsi_cmd) { ++ if (atomic_read(&aborted_cmd->cmd_state) == ++ ISCSI_CMD_STATE_COMPLETED) { ++ printk(KERN_ALERT "TMF: WaTcH - completed " ++ "ITT=0x%x & the TMF request to abort it\n", ++ aborted_cmd->req.itt); ++ /* scsi_cmd->result is already set will wait ++ * for CMD_CLEANUP to complete before calling ++ * scsi_done() ++ */ ++ } else { ++ aborted_cmd->scsi_cmd->result = DID_ABORT << 16; ++ aborted_cmd->scsi_cmd->resid = ++ aborted_cmd->scsi_cmd->request_bufflen; ++ } ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_COMPLETED); ++ } ++ } else if (tmf_cqe->response == ISCSI_TMF_RSP_NO_TASK) { ++ if (atomic_read(&aborted_cmd->cmd_state) == ++ ISCSI_CMD_STATE_COMPLETED) { ++ printk(KERN_ALERT "TMF: tgt completed ITT=0x%x while\n" ++ "abort is pending\n", aborted_cmd->req.itt); ++ /* Target did the right thing, so need to complete the ++ * command and return SUCCESS to SCSI-ML ++ */ ++ } ++ if ((atomic_read(&aborted_cmd->cmd_state) == ++ ISCSI_CMD_STATE_INITIATED) && ++ (aborted_cmd->scsi_cmd == cmd->tmf_ref_sc)) { ++ /* Something is messed up enter session recovery. */ ++ printk(KERN_ALERT "bnx2i: WaTcH - TMF_RESP: task still allegiant\n"); ++ } ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_COMPLETED); ++ } else { ++ printk(KERN_ALERT "TMF_RESP: failed, ITT 0x%x REF ITT 0x%x\n", ++ cmd->req.itt, aborted_cmd->req.itt); ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_FAILED); ++ } ++ ++reset_done: ++ cmd->iscsi_opcode = 0; ++ ++ if (cmd->conn && cmd->conn->sess ) ++ wake_up(&cmd->conn->sess->er_wait); ++ ++ return SUCCESS; ++} ++ ++/** ++ * bnx2i_process_logout_resp - this function handles iscsi logout response ++ * CQE processing ++ * ++ * @conn: iscsi connection ++ * @cqe: pointer to newly DMA'ed CQE entry for processing ++ * ++ * process iSCSI Logout Response CQE & make function call to ++ * notify the user daemon. ++ */ ++static int bnx2i_process_logout_resp(struct bnx2i_conn *conn, struct cqe *cqe) ++{ ++ struct bnx2i_cmd *cmd; ++ struct iscsi_logout_response *logout; ++ struct iscsi_logout_rsp *logout_resp; ++ u32 itt; ++ ++ logout = (struct iscsi_logout_response *) cqe; ++ logout_resp = (struct iscsi_logout_rsp *) &conn->gen_pdu.resp_hdr; ++ itt = (logout->itt & ISCSI_LOGOUT_RESPONSE_INDEX); ++ ++ cmd = get_cmnd(conn->sess, itt); ++ if (!cmd || cmd != conn->sess->login_nopout_cmd) ++ return -EINVAL; ++ ++ logout_resp->opcode = logout->op_code; ++ logout_resp->flags = logout->response; ++ logout_resp->hlength = 0; ++ ++ logout_resp->itt = conn->gen_pdu.pdu_hdr.itt; ++ logout_resp->statsn = conn->gen_pdu.pdu_hdr.exp_statsn; ++ logout_resp->exp_cmdsn = htonl(logout->exp_cmd_sn); ++ logout_resp->max_cmdsn = htonl(logout->max_cmd_sn); ++ ++ logout_resp->t2wait = htonl(logout->time_to_wait); ++ logout_resp->t2retain = htonl(logout->time_to_retain); ++ ++ conn->ep->teardown_mode = BNX2I_GRACEFUL_SHUTDOWN; ++ cmd->iscsi_opcode = 0; ++ ++ bnx2i_indicate_logout_resp(conn); ++ return 0; ++} ++ ++/** ++ * bnx2i_process_nopin_local_cmpl - this function handles iscsi nopin CQE ++ * processing ++ * ++ * @conn: iscsi connection ++ * @cqe: pointer to newly DMA'ed CQE entry for processing ++ * ++ * process iSCSI NOPIN local completion CQE, frees IIT and command structures ++ */ ++void bnx2i_process_nopin_local_cmpl(struct bnx2i_conn *conn, struct cqe *cqe) ++{ ++ u32 itt; ++ struct Scsi_Host *shost; ++ struct bnx2i_cmd *cmd; ++ struct iscsi_nop_in_msg *nop_in; ++ ++ nop_in = (struct iscsi_nop_in_msg *) cqe; ++ shost = bnx2i_conn_get_shost(conn); ++ ++ itt = (nop_in->itt & ISCSI_NOP_IN_MSG_INDEX); ++ cmd = get_cmnd(conn->sess, itt); ++ if (!cmd || cmd != conn->sess->nopout_resp_cmd) { ++ printk(KERN_ALERT "nop_in_local: ITT %x not active\n", itt); ++ return; ++ } ++ cmd->iscsi_opcode = 0; ++} ++ ++/** ++ * bnx2i_process_tgt_noop_resp - this function handles iscsi nopout CQE ++ * processing ++ * ++ * @conn: iscsi connection ++ * @cqe: pointer to newly DMA'ed CQE entry for processing ++ * ++ * Process iSCSI target's nopin response to initiator's proactive nopout ++ */ ++static int bnx2i_process_tgt_noop_resp(struct bnx2i_conn *conn, struct cqe *cqe) ++{ ++ struct iscsi_nopin *nopin_hdr; ++ u32 itt; ++ struct bnx2i_cmd *cmd; ++ struct iscsi_nop_in_msg *nop_in; ++ ++ nop_in = (struct iscsi_nop_in_msg *) cqe; ++ itt = (nop_in->itt & ISCSI_NOP_IN_MSG_INDEX); ++ nopin_hdr = (struct iscsi_nopin *) &conn->gen_pdu.nopin_hdr; ++ ++ cmd = get_cmnd(conn->sess, itt); ++ if (!cmd || cmd != conn->sess->login_nopout_cmd) { ++ printk(KERN_ALERT"bnx2i: nopout resp, invalid ITT, got %x" ++ " expected %x\n", itt, cmd->itt); ++ return -EINVAL; ++ } ++ ++ nopin_hdr->opcode = nop_in->op_code; ++ nopin_hdr->flags = ISCSI_FLAG_CMD_FINAL; ++ nopin_hdr->rsvd2 = nopin_hdr->rsvd3 = 0; ++ nopin_hdr->itt = conn->gen_pdu.nopout_hdr.itt; ++ nopin_hdr->ttt = ISCSI_RESERVED_TAG; ++ ++ memcpy(nopin_hdr->lun, conn->gen_pdu.nopout_hdr.lun, 8); ++ nopin_hdr->statsn = conn->gen_pdu.nopout_hdr.exp_statsn; ++ nopin_hdr->exp_cmdsn = htonl(nop_in->exp_cmd_sn); ++ nopin_hdr->max_cmdsn = htonl(nop_in->max_cmd_sn); ++ memset(nopin_hdr->rsvd4, 0x00, 12); ++ ++ bnx2i_process_nopin(conn, cmd, NULL, 0); ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_unsol_pdu_adjust_rq - makes adjustments to RQ after unsolicited pdu ++ * is received ++ * ++ * @conn: iscsi connection ++ * ++ * Firmware advances RQ producer index for every unsolicited PDU even if ++ * payload data length is '0'. This function makes corresponding ++ * adjustments on the driver side to match this f/w behavior ++ */ ++static void bnx2i_unsol_pdu_adjust_rq(struct bnx2i_conn *conn) ++{ ++ char dummy_rq_data[2]; ++ bnx2i_get_rq_buf(conn, dummy_rq_data, 1); ++ bnx2i_put_rq_buf(conn, 1); ++} ++ ++ ++/** ++ * bnx2i_process_nopin_mesg - this function handles iscsi nopin CQE ++ * processing ++ * ++ * @conn: iscsi connection ++ * @cqe: pointer to newly DMA'ed CQE entry for processing ++ * ++ * process iSCSI target's proactive iSCSI NOPIN request ++ */ ++static void bnx2i_process_nopin_mesg(struct bnx2i_conn *conn, struct cqe *cqe) ++{ ++ u32 itt; ++ u32 ttt; ++#ifndef __VMKLNX__ ++ struct Scsi_Host *shost; ++#endif ++ struct iscsi_nop_in_msg *nop_in; ++ ++ nop_in = (struct iscsi_nop_in_msg *) cqe; ++ itt = nop_in->itt; ++ ttt = nop_in->ttt; ++ ++ bnx2i_update_cmd_sequence(conn->sess, ++ nop_in->exp_cmd_sn, nop_in->max_cmd_sn); ++ ++ conn->sess->last_noopin_processed = jiffies; ++ conn->sess->noopin_processed_count++; ++ ++ if (itt == (u16) ISCSI_RESERVED_TAG) { ++ struct bnx2i_cmd *cmd; ++ ++ bnx2i_unsol_pdu_adjust_rq(conn); ++ if (ttt == ISCSI_RESERVED_TAG) ++ return; ++conn->sess->tgt_noopin_count++; ++ ++ cmd = conn->sess->nopout_resp_cmd; ++ if (!cmd) { ++ /* should not happen as nopout-resp command is reserved ++ * during conn_bind() ++ */ ++ return; ++ } ++ cmd->conn = conn; ++ cmd->scsi_cmd = NULL; ++ cmd->req.total_data_transfer_length = 0; ++ cmd->iscsi_opcode = ISCSI_OP_NOOP_OUT; ++ cmd->ttt = ttt; ++ ++ /* requires reply in the form of Nop-Out */ ++ if (nop_in->data_length) ++ printk(KERN_ALERT "Tgt NOPIN with dlen > 0\n"); ++ ++ atomic_set(&conn->sess->nop_resp_pending, 1); ++ ++ if (atomic_read(&conn->worker_enabled)) { ++#ifdef __VMKLNX__ ++ printk("%s: tasklet scheduled , cid %d\n", ++ __FUNCTION__, conn->ep->ep_iscsi_cid); ++ tasklet_schedule(&conn->conn_tasklet); ++#else ++ shost = bnx2i_conn_get_shost(conn); ++ scsi_queue_work(shost, &conn->conn_worker); ++#endif /* __VMKLNX__ */ ++ } ++ } else /* target's reply to initiator's Nop-Out */ ++ bnx2i_process_tgt_noop_resp(conn, cqe); ++} ++ ++ ++/** ++ * bnx2i_process_async_mesg - this function handles iscsi async message ++ * processing ++ * ++ * @conn: iscsi connection ++ * @cqe: pointer to newly DMA'ed CQE entry for processing ++ * ++ * process iSCSI ASYNC Message ++ */ ++static void bnx2i_process_async_mesg(struct bnx2i_conn *conn, struct cqe *cqe) ++{ ++ struct iscsi_async_msg *async_cqe; ++ struct iscsi_async *async_hdr; ++ u8 async_event; ++ ++ bnx2i_unsol_pdu_adjust_rq(conn); ++ ++ async_cqe = (struct iscsi_async_msg *) cqe; ++ async_event = async_cqe->async_event; ++ ++ if (async_event == ISCSI_ASYNC_MSG_SCSI_EVENT) { ++ printk(KERN_ALERT "async: scsi events not supported\n"); ++ return; ++ } ++ ++ async_hdr = (struct iscsi_async *) &conn->gen_pdu.async_hdr; ++ async_hdr->opcode = async_cqe->op_code; ++ async_hdr->flags = 0x80; ++ async_hdr->rsvd2[0] = async_hdr->rsvd2[1] = async_hdr->rsvd3 = 0; ++ async_hdr->dlength[0] = async_hdr->dlength[1] = async_hdr->dlength[2] = 0; ++ ++ memcpy(async_hdr->lun, async_cqe->lun, 8); ++ async_hdr->statsn = htonl(0); ++ async_hdr->exp_cmdsn = htonl(async_cqe->exp_cmd_sn); ++ async_hdr->max_cmdsn = htonl(async_cqe->max_cmd_sn); ++ ++ async_hdr->async_event = async_cqe->async_event; ++ async_hdr->async_vcode = async_cqe->async_vcode; ++ ++ async_hdr->param1 = htons(async_cqe->param1); ++ async_hdr->param2 = htons(async_cqe->param2); ++ async_hdr->param3 = htons(async_cqe->param3); ++ async_hdr->rsvd5[0] = async_hdr->rsvd5[1] = 0; ++ async_hdr->rsvd5[2] = async_hdr->rsvd5[3] = 0; ++ ++ bnx2i_indicate_async_mesg(conn); ++} ++ ++ ++/** ++ * bnx2i_process_reject_mesg - process iscsi reject pdu ++ * ++ * @conn: iscsi connection ++ * @cqe: pointer to newly DMA'ed CQE entry for processing ++ * ++ * process iSCSI REJECT message ++ */ ++static void bnx2i_process_reject_mesg(struct bnx2i_conn *conn, struct cqe *cqe) ++{ ++ struct iscsi_reject_msg *reject; ++ char rej_pdu[BNX2I_RQ_WQE_SIZE]; ++ int rej_data_len, idx; ++ ++ reject = (struct iscsi_reject_msg *) cqe; ++ rej_data_len = reject->data_length; ++ if (rej_data_len) { ++ bnx2i_get_rq_buf(conn, rej_pdu, rej_data_len); ++ bnx2i_put_rq_buf(conn, 1); ++ printk(KERN_ALERT "bnx2i - printing rejected PDU contents"); ++ idx = 0; ++ printk(KERN_ALERT "\n[%x]: ", idx); ++ while (idx <= rej_data_len) { ++ printk(KERN_ALERT "%x ", rej_pdu[idx++]); ++ if (!(idx % 8)) ++ printk(KERN_ALERT "\n[%x]: ", idx); ++ } ++ } else ++ bnx2i_unsol_pdu_adjust_rq(conn); ++ ++ bnx2i_recovery_que_add_sess(conn->sess->hba, conn->sess); ++} ++ ++/** ++ * bnx2i_process_cmd_cleanup_resp - process scsi command clean-up completion ++ * ++ * @conn: iscsi connection ++ * @cqe: pointer to newly DMA'ed CQE entry for processing ++ * ++ * process command cleanup response CQE during conn shutdown or error recovery ++ */ ++static void bnx2i_process_cmd_cleanup_resp(struct bnx2i_conn *conn, ++ struct cqe *cqe) ++{ ++ u32 itt; ++ struct bnx2i_cmd *cmd; ++ struct iscsi_cleanup_response *cmd_clean_rsp; ++ ++ cmd_clean_rsp = (struct iscsi_cleanup_response *) cqe; ++ itt = (cmd_clean_rsp->itt & ISCSI_CLEANUP_RESPONSE_INDEX); ++ cmd = get_cmnd(conn->sess, itt); ++ /* there is not be any synchronization issue here, 'Cuz only TMF process ++ * should be waiting on this response. There cannot be race b/w this & ++ * SCSI completion because completion is either processed by now and if ++ * SCSI_RESP arrives after CMD_CLEANUP, F/W will deem it as a protocol ++ * violation and forces session recovery ++ */ ++ if (!cmd || !cmd->scsi_cmd) { ++ printk(KERN_ALERT "bnx2i: cmd clean, ITT %x not active\n", itt); ++ /* may be completion came before cleanup response */ ++ } else { ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_CLEANUP_CMPL); ++ if (cmd->scsi_status_rcvd) { ++ /** cmd completed while CMD_CLEANUP was pending ++ */ ++ bnx2i_complete_cmd(conn->sess, cmd); ++ } else { ++ bnx2i_fail_cmd(conn->sess, cmd); ++ } ++ } ++ conn->sess->cmd_cleanup_cmpl++; ++ barrier(); ++ wake_up(&conn->sess->er_wait); ++} ++ ++void bnx2i_print_sqe(struct bnx2i_conn *conn) ++{ ++ struct qp_info *qp = &conn->ep->qp; ++ struct iscsi_nop_out_request *nopout_wqe; ++ int count = conn->sess->sq_size; ++ ++ printk(KERN_ALERT "bnx2i: dump SQE conn %p, sn %x, max_sn %x\n", ++ conn, conn->sess->cmdsn, conn->sess->exp_cmdsn); ++ printk(KERN_ALERT "\t: OPCODE, ATTR, DLEN, ITT, TTT, SN, flags\n"); ++ ++ nopout_wqe = (struct iscsi_nop_out_request *) conn->ep->qp.sq_prod_qe; ++ while (count--) { ++ printk(KERN_ALERT "\t: %.2x, %.4x, %.4x, %.2x, %.4x, %.4x, %.2x\n", ++ nopout_wqe->op_code, nopout_wqe->op_attr, ++ nopout_wqe->data_length, nopout_wqe->itt, ++ nopout_wqe->ttt, nopout_wqe->cmd_sn, nopout_wqe->flags); ++ if (qp->sq_first_qe == (struct sqe *)nopout_wqe) ++ nopout_wqe = (struct iscsi_nop_out_request *) qp->sq_last_qe; ++ else ++ nopout_wqe--; ++ } ++} ++ ++void bnx2i_print_cqe(struct bnx2i_conn *conn) ++{ ++ struct qp_info *qp = &conn->ep->qp; ++ volatile struct iscsi_nop_in_msg *nopin; ++ struct cqe *cq_cons; ++ int count = qp->cqe_size; ++ ++ printk(KERN_ALERT "bnx2i: dump CQE conn %p, exp_seq_sn %x\n", ++ conn, qp->cqe_exp_seq_sn); ++ printk(KERN_ALERT "\t: OPCODE, EXP_SN, MAX_SN, ITT, TTT, CQSN\n"); ++ ++ cq_cons = qp->cq_cons_qe; ++ while (count--) { ++ nopin = (struct iscsi_nop_in_msg *) cq_cons; ++ printk(KERN_ALERT "\t: %.2x, %.4x, %.4x, %.2x, %.4x, %.4x\n", ++ nopin->op_code, nopin->exp_cmd_sn, nopin->max_cmd_sn, ++ nopin->itt, nopin->ttt, nopin->cq_req_sn); ++ if (qp->cq_first_qe == cq_cons) ++ cq_cons = qp->cq_last_qe; ++ else ++ cq_cons--; ++ } ++} ++ ++ ++/** ++ * bnx2i_process_new_cqes - process newly DMA'ed CQE's ++ * ++ * @conn: iscsi connection ++ * @soft_irq: initial though was iscsi logout and command cleanup reponse will ++ * be directly processed in softirq. But I guess driver still needs ++ * flush the complete queue and cannot be picky ++ * @cqes_per_work: number of cqes to process per call ++ * ++ * this function is called by generic KCQ handler to process all pending CQE's ++ */ ++int bnx2i_process_new_cqes(struct bnx2i_conn *conn, int soft_irq, ++ int cqes_per_work) ++{ ++ struct qp_info *qp; ++ volatile struct iscsi_nop_in_msg *nopin; ++ volatile u32 *sess_state = &conn->sess->state; ++ struct cqe *cq_cons; ++ int num_cqe = 0; ++ int keep_processing = 1; ++ ++ if (!conn->ep) ++ return 0; ++ ++ qp = &conn->ep->qp; ++ while (keep_processing > 0) { ++ cq_cons = qp->cq_cons_qe; ++ barrier(); ++ nopin = (struct iscsi_nop_in_msg *) qp->cq_cons_qe; ++ if ((nopin->cq_req_sn != qp->cqe_exp_seq_sn) || ++ (*sess_state == BNX2I_SESS_IN_SHUTDOWN)) { ++ keep_processing = 0; ++ break; ++ } ++ if (num_cqe >= cqes_per_work) { ++ break; ++ } ++ ++ num_cqe++; ++ if (nopin->op_code == ISCSI_OP_SCSI_CMD_RSP) { ++ conn->num_scsi_resp_pdus++; ++ bnx2i_process_scsi_cmd_resp(conn, cq_cons); ++ } else if (nopin->op_code == ISCSI_OP_SCSI_DATA_IN) { ++ bnx2i_process_scsi_cmd_resp(conn, cq_cons); ++ } else if (nopin->op_code == ISCSI_OP_LOGIN_RSP) { ++ conn->num_login_resp_pdus++; ++ bnx2i_process_login_resp(conn, cq_cons); ++ } else if (nopin->op_code == ISCSI_OP_LOGOUT_RSP) { ++ conn->num_logout_resp_pdus++; ++ bnx2i_process_logout_resp(conn, cq_cons); ++ keep_processing = -EAGAIN; ++ } else if (nopin->op_code == ISCSI_OP_SCSI_TMFUNC_RSP) { ++ conn->num_tmf_resp_pdus++; ++ bnx2i_process_tmf_resp(conn, cq_cons); ++ /* exit out of completion processing inorder to ++ * TMF condition asap ++ ++ keep_processing = -EAGAIN; ++ */ ++ } else if (nopin->op_code == ISCSI_OP_NOOP_IN) { ++ conn->num_nopin_pdus++; ++ bnx2i_process_nopin_mesg(conn, cq_cons); ++ } else if (nopin->op_code == ++ ISCSI_OPCODE_NOPOUT_LOCAL_COMPLETION) { ++ bnx2i_process_nopin_local_cmpl(conn, cq_cons); ++ } else if (nopin->op_code == ISCSI_OP_ASYNC_EVENT) { ++ ++ conn->num_async_pdus++; ++ bnx2i_process_async_mesg(conn, cq_cons); ++ } else if (nopin->op_code == ISCSI_OP_REJECT) { ++ printk("%s: WaTcH: ISCSI REJECT CQE, cid %d\n", ++ __FUNCTION__, conn->ep->ep_iscsi_cid); ++ conn->num_reject_pdus++; ++ bnx2i_process_reject_mesg(conn, cq_cons); ++ } else if (nopin->op_code == ISCSI_OPCODE_CLEANUP_RESPONSE) { ++ bnx2i_process_cmd_cleanup_resp(conn, cq_cons); ++ } else ++ printk(KERN_ALERT "bnx2i: WaTcH: unknown opcode 0x%x\n", ++ nopin->op_code); ++ ++ /* clear out in production version only, till beta keep opcode ++ * field intact, will be helpful in debugging (context dump) ++ nopin->op_code = 0; ++ */ ++ qp->cqe_exp_seq_sn++; ++ if (qp->cqe_exp_seq_sn == (qp->cqe_size * 2 + 1)) ++ qp->cqe_exp_seq_sn = ISCSI_INITIAL_SN; ++ ++ if (qp->cq_cons_qe == qp->cq_last_qe) { ++ qp->cq_cons_qe = qp->cq_first_qe; ++ qp->cq_cons_idx = 0; ++ } else { ++ qp->cq_cons_qe++; ++ qp->cq_cons_idx++; ++ } ++ } ++ return keep_processing; ++} ++ ++/** ++ * bnx2i_fastpath_notification - process global event queue (KCQ) ++ * ++ * @hba: adapter structure pointer ++ * @new_cqe_kcqe: pointer to newly DMA'ed KCQE entry ++ * ++ * Fast path event notification handler, KCQ entry carries context id ++ * of the connection that has 1 or more pending CQ entries ++ */ ++static void bnx2i_fastpath_notification(struct bnx2i_hba *hba, ++ struct iscsi_kcqe *new_cqe_kcqe) ++{ ++ u32 iscsi_cid; ++ struct bnx2i_conn *conn; ++#ifndef __VMKLNX__ ++ struct Scsi_Host *shost; ++#endif ++ ++ iscsi_cid = new_cqe_kcqe->iscsi_conn_id; ++ conn = bnx2i_get_conn_from_id(hba, iscsi_cid); ++ ++ if (!conn) { ++ printk(KERN_ALERT "bnx2i: WaTcH: cid #%x not valid\n", ++ iscsi_cid); ++ return; ++ } ++ if (!conn->ep) { ++ printk(KERN_ALERT "bnx2i: WaTcH: cid #%x - ep not bound\n", ++ iscsi_cid); ++ return; ++ } ++ ++ if (atomic_read(&conn->worker_enabled)) { ++#ifdef __VMKLNX__ ++ tasklet_schedule(&conn->conn_tasklet); ++#else ++ shost = bnx2i_conn_get_shost(conn); ++ scsi_queue_work(shost, &conn->conn_worker); ++#endif /* __VMKLNX__ */ ++ } else { ++ /* command cleanup completions needs to be completed for ++ * flush command queue to drain out all active commands else ++ * this could lead to deadlock and PCPU lockup in ESX ++ */ ++ /* no that tasklet will run till ep_disconnect() is called, ++ * this may not be required - Anil ++ */ ++ bnx2i_process_new_cqes(conn, 1, conn->ep->qp.cqe_size); ++ bnx2i_arm_cq_event_coalescing(conn->ep, CNIC_ARM_CQE); ++ } ++} ++ ++ ++/** ++ * bnx2i_process_update_conn_cmpl - process iscsi conn update completion KCQE ++ * ++ * @hba: adapter structure pointer ++ * @update_kcqe: kcqe pointer ++ * ++ * CONN_UPDATE completion handler, this completes iSCSI connection FFP migration ++ */ ++static void bnx2i_process_update_conn_cmpl(struct bnx2i_hba *hba, ++ struct iscsi_kcqe *update_kcqe) ++{ ++ struct bnx2i_conn *conn; ++ u32 iscsi_cid; ++ ++ iscsi_cid = update_kcqe->iscsi_conn_id; ++ conn = bnx2i_get_conn_from_id(hba, iscsi_cid); ++ ++ if (!conn) { ++ printk(KERN_ALERT "conn_update: cid %x not valid\n", iscsi_cid); ++ return; ++ } ++ if (!conn->ep) { ++ printk(KERN_ALERT "cid %x does not have ep bound\n", iscsi_cid); ++ return; ++ } ++ ++ if (update_kcqe->completion_status) { ++ printk(KERN_ALERT "request failed cid %x\n", iscsi_cid); ++ conn->ep->state = EP_STATE_ULP_UPDATE_FAILED; ++ } else ++ conn->ep->state = EP_STATE_ULP_UPDATE_COMPL; ++ ++ wake_up_interruptible(&conn->ep->ofld_wait); ++} ++ ++ ++/** ++ * bnx2i_recovery_que_add_conn - add connection to recovery queue ++ * ++ * @hba: adapter structure pointer ++ * @conn: iscsi connection ++ * ++ * Add connection to recovery queue and schedule adapter eh worker ++ */ ++static void bnx2i_recovery_que_add_sess(struct bnx2i_hba *hba, ++ struct bnx2i_sess *sess) ++{ ++ int prod_idx = hba->sess_recov_prod_idx; ++ ++ if (sess->recovery_state || ++ atomic_read(&sess->tmf_active)) ++ return; ++ ++ spin_lock(&hba->lock); ++ sess->recovery_state = ISCSI_SESS_RECOVERY_START; ++ hba->sess_recov_list[prod_idx] = sess; ++ if (hba->sess_recov_max_idx == hba->sess_recov_prod_idx) ++ hba->sess_recov_prod_idx = 0; ++ else ++ hba->sess_recov_prod_idx++; ++ spin_unlock(&hba->lock); ++ ++ schedule_work(&hba->err_rec_task); ++} ++ ++ ++/** ++ * bnx2i_process_tcp_error - process error notification on a given connection ++ * ++ * @hba: adapter structure pointer ++ * @tcp_err: tcp error kcqe pointer ++ * ++ * handles tcp level error notifications from FW. ++ */ ++static void bnx2i_process_tcp_error(struct bnx2i_hba *hba, ++ struct iscsi_kcqe *tcp_err) ++{ ++ struct bnx2i_conn *conn; ++ u32 iscsi_cid; ++ ++ iscsi_cid = tcp_err->iscsi_conn_id; ++ conn = bnx2i_get_conn_from_id(hba, iscsi_cid); ++ ++ if (!conn) { ++ printk(KERN_ALERT "bnx2i - cid 0x%x not valid\n", iscsi_cid); ++ return; ++ } ++ ++ printk(KERN_ALERT "bnx2i - cid 0x%x had TCP errors, error code 0x%x\n", ++ iscsi_cid, tcp_err->completion_status); ++ bnx2i_recovery_que_add_sess(conn->sess->hba, conn->sess); ++} ++ ++ ++/** ++ * bnx2i_process_iscsi_error - process error notification on a given connection ++ * ++ * @hba: adapter structure pointer ++ * @iscsi_err: iscsi error kcqe pointer ++ * ++ * handles iscsi error notifications from the FW. Firmware based in initial ++ * handshake classifies iscsi protocol / TCP rfc violation into either ++ * warning or error indications. If indication is of "Error" type, driver ++ * will initiate session recovery for that connection/session. For ++ * "Warning" type indication, driver will put out a system log message ++ * (there will be only one message for each type for the life of the ++ * session, this is to avoid un-necessarily overloading the system) ++ */ ++static void bnx2i_process_iscsi_error(struct bnx2i_hba *hba, ++ struct iscsi_kcqe *iscsi_err) ++{ ++ struct bnx2i_conn *conn; ++ u32 iscsi_cid; ++ char warn_notice[] = "iscsi_warning"; ++ char error_notice[] = "iscsi_error"; ++ char additional_notice[64]; ++ char *message; ++ int need_recovery; ++ u64 err_mask64; ++ struct Scsi_Host *shost; ++ ++ iscsi_cid = iscsi_err->iscsi_conn_id; ++ conn = bnx2i_get_conn_from_id(hba, iscsi_cid); ++ ++ if (!conn) { ++ printk(KERN_ALERT "bnx2i - cid 0x%x not valid\n", iscsi_cid); ++ return; ++ } ++ ++ err_mask64 = (0x1ULL << iscsi_err->completion_status); ++ ++ if (err_mask64 & iscsi_error_mask) { ++ need_recovery = 0; ++ message = warn_notice; ++ } else { ++ need_recovery = 1; ++ message = error_notice; ++ } ++ ++ switch (iscsi_err->completion_status) { ++ case ISCSI_KCQE_COMPLETION_STATUS_HDR_DIG_ERR: ++ strcpy(additional_notice, "hdr digest err"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_DATA_DIG_ERR: ++ strcpy(additional_notice, "data digest err"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_OPCODE: ++ strcpy(additional_notice, "wrong opcode rcvd"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_AHS_LEN: ++ strcpy(additional_notice, "AHS len > 0 rcvd"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_ITT: ++ strcpy(additional_notice, "invalid ITT rcvd"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_STATSN: ++ strcpy(additional_notice, "wrong StatSN rcvd"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_EXP_DATASN: ++ strcpy(additional_notice, "wrong DataSN rcvd"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T : ++ strcpy(additional_notice, "pend R2T violation"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_0: ++ strcpy(additional_notice, "ERL0, UO"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_1: ++ strcpy(additional_notice, "ERL0, U1"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_2: ++ strcpy(additional_notice, "ERL0, U2"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_3: ++ strcpy(additional_notice, "ERL0, U3"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_4: ++ strcpy(additional_notice, "ERL0, U4"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_5: ++ strcpy(additional_notice, "ERL0, U5"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_6: ++ strcpy(additional_notice, "ERL0, U6"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REMAIN_RCV_LEN: ++ strcpy(additional_notice, "invalid resi len"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_MAX_RCV_PDU_LEN: ++ strcpy(additional_notice, "MRDSL violation"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_F_BIT_ZERO: ++ strcpy(additional_notice, "F-bit not set"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_TTT_NOT_RSRV: ++ strcpy(additional_notice, "invalid TTT"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATASN: ++ strcpy(additional_notice, "invalid DataSN"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REMAIN_BURST_LEN: ++ strcpy(additional_notice, "burst len violation"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_BUFFER_OFF: ++ strcpy(additional_notice, "buf offset violation"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_LUN: ++ strcpy(additional_notice, "invalid LUN field"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_R2TSN: ++ strcpy(additional_notice, "invalid R2TSN field"); ++ break; ++#define BNX2I_ERR_DESIRED_DATA_TRNS_LEN_0 \ ++ ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_0 ++ case BNX2I_ERR_DESIRED_DATA_TRNS_LEN_0: ++ strcpy(additional_notice, "invalid cmd len1"); ++ break; ++#define BNX2I_ERR_DESIRED_DATA_TRNS_LEN_1 \ ++ ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_1 ++ case BNX2I_ERR_DESIRED_DATA_TRNS_LEN_1: ++ strcpy(additional_notice, "invalid cmd len2"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T_EXCEED: ++ strcpy(additional_notice, ++ "pend r2t exceeds MaxOutstandingR2T value"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_TTT_IS_RSRV: ++ strcpy(additional_notice, "TTT is rsvd"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_MAX_BURST_LEN: ++ strcpy(additional_notice, "MBL violation"); ++ break; ++#define BNX2I_ERR_DATA_SEG_LEN_NOT_ZERO \ ++ ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATA_SEG_LEN_NOT_ZERO ++ case BNX2I_ERR_DATA_SEG_LEN_NOT_ZERO: ++ strcpy(additional_notice, "data seg len != 0"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REJECT_PDU_LEN: ++ strcpy(additional_notice, "reject pdu len error"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_ASYNC_PDU_LEN: ++ strcpy(additional_notice, "async pdu len error"); ++ break; ++ case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_NOPIN_PDU_LEN: ++ strcpy(additional_notice, "nopin pdu len error"); ++ break; ++#define BNX2_ERR_PEND_R2T_IN_CLEANUP \ ++ ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T_IN_CLEANUP ++ case BNX2_ERR_PEND_R2T_IN_CLEANUP: ++ strcpy(additional_notice, "pend r2t in cleanup"); ++ break; ++ ++ case ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_IP_FRAGMENT: ++ strcpy(additional_notice, "IP fragments rcvd"); ++ break; ++ case ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_IP_OPTIONS: ++ strcpy(additional_notice, "IP options error"); ++ break; ++ case ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_URGENT_FLAG: ++ strcpy(additional_notice, "urgent flag error"); ++ break; ++ default: ++ printk(KERN_ALERT "iscsi_err - unknown err %x\n", ++ iscsi_err->completion_status); ++ } ++ ++ if (need_recovery) { ++ shost = bnx2i_conn_get_shost(conn); ++ printk(KERN_ALERT "bnx2i: WaTcH: %s - %s\n", ++ message, additional_notice); ++ ++ printk(KERN_ALERT "conn_err - WaTcH: hostno %d conn %p, " ++ "iscsi_cid %x cid %x\n", ++ shost->host_no, conn, ++ conn->ep->ep_iscsi_cid, ++ conn->ep->ep_cid); ++ bnx2i_recovery_que_add_sess(conn->sess->hba, conn->sess); ++ } else ++ if (!test_and_set_bit(iscsi_err->completion_status, ++ (void *) &conn->sess->violation_notified)) ++ printk(KERN_ALERT "bnx2i: WaTcH: %s - %s\n", ++ message, additional_notice); ++} ++ ++ ++/** ++ * bnx2i_process_conn_destroy_cmpl - process iscsi conn destroy completion ++ * ++ * @hba: adapter structure pointer ++ * @conn_destroy: conn destroy kcqe pointer ++ * ++ * handles connection destroy completion request. ++ */ ++static void bnx2i_process_conn_destroy_cmpl(struct bnx2i_hba *hba, ++ struct iscsi_kcqe *conn_destroy) ++{ ++ struct bnx2i_endpoint *ep; ++ ++ ep = bnx2i_find_ep_in_destroy_list(hba, conn_destroy->iscsi_conn_id); ++ if (!ep) { ++ printk(KERN_ALERT "bnx2i_conn_destroy_cmpl: no pending " ++ "offload request, unexpected complection\n"); ++ return; ++ } ++ ++ if (hba != ep->hba) { ++ printk(KERN_ALERT "conn destroy- error hba mis-match\n"); ++ return; ++ } ++ ++ if (conn_destroy->completion_status) { ++ printk(KERN_ALERT "conn_destroy_cmpl: op failed\n"); ++ ep->state = EP_STATE_CLEANUP_FAILED; ++ } else ++ ep->state = EP_STATE_CLEANUP_CMPL; ++ wake_up_interruptible(&ep->ofld_wait); ++ ++ if (test_bit(ADAPTER_STATE_GOING_DOWN, &hba->adapter_state)) ++ wake_up_interruptible(&hba->eh_wait); ++} ++ ++ ++/** ++ * bnx2i_process_ofld_cmpl - process initial iscsi conn offload completion ++ * ++ * @hba: adapter structure pointer ++ * @ofld_kcqe: conn offload kcqe pointer ++ * ++ * handles initial connection offload completion, ep_connect() thread is ++ * woken-up to continue with LLP connect process ++ */ ++static void bnx2i_process_ofld_cmpl(struct bnx2i_hba *hba, ++ struct iscsi_kcqe *ofld_kcqe) ++{ ++ u32 cid_addr; ++ struct bnx2i_endpoint *ep; ++ u32 cid_num; ++ ++ ep = bnx2i_find_ep_in_ofld_list(hba, ofld_kcqe->iscsi_conn_id); ++ if (!ep) { ++ printk(KERN_ALERT "ofld_cmpl: no pend offload request\n"); ++ return; ++ } ++ ++ if (hba != ep->hba) { ++ printk(KERN_ALERT "ofld_cmpl: error hba mis-match\n"); ++ return; ++ } ++ ++ if (ofld_kcqe->completion_status) { ++ if (ofld_kcqe->completion_status == ++ ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) ++ printk(KERN_ALERT "bnx2i: unable to allocate" ++ " iSCSI context resources\n"); ++ ep->state = EP_STATE_OFLD_FAILED; ++ } else { ++ ep->state = EP_STATE_OFLD_COMPL; ++ cid_addr = ofld_kcqe->iscsi_conn_context_id; ++ cid_num = bnx2i_get_cid_num(ep); ++ ep->ep_cid = cid_addr; ++ ep->qp.ctx_base = NULL; ++ } ++ wake_up_interruptible(&ep->ofld_wait); ++} ++ ++/** ++ * bnx2i_indicate_kcqe - process iscsi conn update completion KCQE ++ * ++ * @hba: adapter structure pointer ++ * @update_kcqe: kcqe pointer ++ * ++ * Generic KCQ event handler/dispatcher ++ */ ++static void bnx2i_indicate_kcqe(void *context, struct kcqe *kcqe[], ++ u32 num_cqe) ++{ ++ struct bnx2i_hba *hba = (struct bnx2i_hba *) context; ++ int i = 0; ++ struct iscsi_kcqe *ikcqe = NULL; ++ ++ while (i < num_cqe) { ++ ikcqe = (struct iscsi_kcqe *) kcqe[i++]; ++ ++ if (ikcqe->op_code == ++ ISCSI_KCQE_OPCODE_CQ_EVENT_NOTIFICATION) ++ bnx2i_fastpath_notification(hba, ikcqe); ++ else if (ikcqe->op_code == ISCSI_KCQE_OPCODE_OFFLOAD_CONN) ++ bnx2i_process_ofld_cmpl(hba, ikcqe); ++ else if (ikcqe->op_code == ISCSI_KCQE_OPCODE_UPDATE_CONN) ++ bnx2i_process_update_conn_cmpl(hba, ikcqe); ++ else if (ikcqe->op_code == ISCSI_KCQE_OPCODE_INIT) { ++ if (ikcqe->completion_status != ++ ISCSI_KCQE_COMPLETION_STATUS_SUCCESS) ++ bnx2i_iscsi_license_error(hba, ikcqe->\ ++ completion_status); ++ else { ++ set_bit(ADAPTER_STATE_UP, &hba->adapter_state); ++ bnx2i_get_link_state(hba); ++ printk(KERN_INFO "bnx2i [%.2x:%.2x.%.2x]: " ++ "ISCSI_INIT passed\n", ++ (u8)hba->pcidev->bus->number, ++ hba->pci_devno, ++ (u8)hba->pci_func); ++ } ++ } else if (ikcqe->op_code == ISCSI_KCQE_OPCODE_DESTROY_CONN) ++ bnx2i_process_conn_destroy_cmpl(hba, ikcqe); ++ else if (ikcqe->op_code == ISCSI_KCQE_OPCODE_ISCSI_ERROR) ++ bnx2i_process_iscsi_error(hba, ikcqe); ++ else if (ikcqe->op_code == ISCSI_KCQE_OPCODE_TCP_ERROR) ++ bnx2i_process_tcp_error(hba, ikcqe); ++ else ++ printk(KERN_ALERT "bnx2i: unknown opcode 0x%x\n", ++ ikcqe->op_code); ++ } ++} ++ ++ ++/** ++ * bnx2i_indicate_inetevent - Generic netstack event handler ++ * ++ * @context: adapter structure pointer ++ * @event: event type ++ * ++ * Only required to handle NETDEV_UP event at this time ++ */ ++static void bnx2i_indicate_inetevent(void *context, unsigned long event) ++{ ++ struct bnx2i_hba *hba = (struct bnx2i_hba *) context; ++ ++ switch (event) { ++ case NETDEV_UP: ++ bnx2i_iscsi_handle_ip_event(hba); ++ break; ++ default: ++ ; ++ } ++} ++ ++/** ++ * bnx2i_indicate_netevent - Generic netdev event handler ++ * ++ * @context: adapter structure pointer ++ * @event: event type ++ * ++ * Handles four netdev events, NETDEV_UP, NETDEV_DOWN, ++ * NETDEV_GOING_DOWN and NETDEV_CHANGE ++ */ ++static void bnx2i_indicate_netevent(void *context, unsigned long event) ++{ ++ struct bnx2i_hba *hba = (struct bnx2i_hba *) context; ++ ++ switch (event) { ++ case NETDEV_UP: ++ if (!test_bit(ADAPTER_STATE_UP, &hba->adapter_state)) ++ bnx2i_send_fw_iscsi_init_msg(hba); ++ break; ++ case NETDEV_DOWN: ++ mutex_lock(&hba->net_dev_lock); ++ clear_bit(ADAPTER_STATE_GOING_DOWN, &hba->adapter_state); ++ clear_bit(ADAPTER_STATE_UP, &hba->adapter_state); ++ mutex_unlock(&hba->net_dev_lock); ++ break; ++ case NETDEV_GOING_DOWN: ++ mutex_lock(&hba->net_dev_lock); ++ set_bit(ADAPTER_STATE_GOING_DOWN, &hba->adapter_state); ++ mutex_unlock(&hba->net_dev_lock); ++ bnx2i_start_iscsi_hba_shutdown(hba); ++ break; ++ case NETDEV_CHANGE: ++ bnx2i_get_link_state(hba); ++ break; ++ default: ++ ; ++ } ++} ++ ++ ++/** ++ * bnx2i_cm_connect_cmpl - process iscsi conn establishment completion ++ * ++ * @cm_sk: cnic sock structure pointer ++ * ++ * function callback exported via bnx2i - cnic driver interface to ++ * indicate completion of option-2 TCP connect request. ++ */ ++static void bnx2i_cm_connect_cmpl(struct cnic_sock *cm_sk) ++{ ++ struct bnx2i_endpoint *ep = (struct bnx2i_endpoint *) cm_sk->context; ++ ++ if (test_bit(ADAPTER_STATE_GOING_DOWN, &ep->hba->adapter_state)) ++ ep->state = EP_STATE_CONNECT_FAILED; ++ else if (test_bit(SK_F_OFFLD_COMPLETE, &cm_sk->flags)) ++ ep->state = EP_STATE_CONNECT_COMPL; ++ else { ++ ep->state = EP_STATE_CONNECT_FAILED; ++ printk("%s: WaTcH: cid %d failed to connect %x\n", ++ __FUNCTION__, ep->ep_iscsi_cid, ep->state); ++ } ++ ++ wake_up_interruptible(&ep->ofld_wait); ++} ++ ++ ++/** ++ * bnx2i_cm_close_cmpl - process tcp conn close completion ++ * ++ * @cm_sk: cnic sock structure pointer ++ * ++ * function callback exported via bnx2i - cnic driver interface to ++ * indicate completion of option-2 graceful TCP connect shutdown ++ */ ++static void bnx2i_cm_close_cmpl(struct cnic_sock *cm_sk) ++{ ++ struct bnx2i_endpoint *ep = (struct bnx2i_endpoint *) cm_sk->context; ++ ++ ep->state = EP_STATE_DISCONN_COMPL; ++ ++ wake_up_interruptible(&ep->ofld_wait); ++} ++ ++ ++/** ++ * bnx2i_cm_abort_cmpl - process abortive tcp conn teardown completion ++ * ++ * @cm_sk: cnic sock structure pointer ++ * ++ * function callback exported via bnx2i - cnic driver interface to ++ * indicate completion of option-2 abortive TCP connect termination ++ */ ++static void bnx2i_cm_abort_cmpl(struct cnic_sock *cm_sk) ++{ ++ struct bnx2i_endpoint *ep = (struct bnx2i_endpoint *) cm_sk->context; ++ ++ ep->state = EP_STATE_DISCONN_COMPL; ++ ++ wake_up_interruptible(&ep->ofld_wait); ++} ++ ++ ++/** ++ * bnx2i_cm_remote_close - process received TCP FIN ++ * ++ * @hba: adapter structure pointer ++ * @update_kcqe: kcqe pointer ++ * ++ * function callback exported via bnx2i - cnic driver interface to indicate ++ * async TCP events such as FIN ++ */ ++static void bnx2i_cm_remote_close(struct cnic_sock *cm_sk) ++{ ++ struct bnx2i_endpoint *ep = (struct bnx2i_endpoint *) cm_sk->context; ++ struct bnx2i_sess *sess; ++ ++ if (!ep || !ep->sess) ++ return; ++ ++ sess = ep->sess; ++ spin_lock_bh(&sess->lock); ++ ep->state = EP_STATE_TCP_FIN_RCVD; ++ if (!ep->conn) { ++ /* Conn destroyed before TCP FIN received */ ++ spin_unlock_bh(&sess->lock); ++ return; ++ } ++ ++ if (sess->state == BNX2I_SESS_IN_FFP) ++ bnx2i_recovery_que_add_sess(ep->hba, sess); ++ ++ spin_unlock_bh(&sess->lock); ++} ++ ++ ++/** ++ * bnx2i_cm_remote_abort - process TCP RST and start conn cleanup ++ * ++ * @hba: adapter structure pointer ++ * @update_kcqe: kcqe pointer ++ * ++ * function callback exported via bnx2i - cnic driver interface to ++ * indicate async TCP events (RST) sent by the peer. ++ */ ++static void bnx2i_cm_remote_abort(struct cnic_sock *cm_sk) ++{ ++ struct bnx2i_endpoint *ep = (struct bnx2i_endpoint *) cm_sk->context; ++ struct bnx2i_sess *sess; ++ ++ if (!ep || !ep->sess) ++ return; ++ ++ sess = ep->sess; ++ spin_lock_bh(&sess->lock); ++ ep->state = EP_STATE_TCP_RST_RCVD; ++ if (!ep->conn) { ++ /* Conn destroyed before TCP RST received */ ++ spin_unlock_bh(&sess->lock); ++ return; ++ } ++ ++ if (sess->state == BNX2I_SESS_IN_FFP) ++ bnx2i_recovery_que_add_sess(ep->hba, sess); ++ ++ spin_unlock_bh(&sess->lock); ++} ++ ++ ++/** ++ * bnx2i_cnic_cb - global template of bnx2i - cnic driver interface structure ++ * carrying callback function pointers ++ * ++ */ ++struct cnic_ulp_ops bnx2i_cnic_cb = { ++ .cnic_init = bnx2i_ulp_init, ++ .cnic_exit = bnx2i_ulp_exit, ++ .cnic_start = bnx2i_start, ++ .cnic_stop = bnx2i_stop, ++ .indicate_kcqes = bnx2i_indicate_kcqe, ++ .indicate_netevent = bnx2i_indicate_netevent, ++ .indicate_inetevent = bnx2i_indicate_inetevent, ++ .cm_connect_complete = bnx2i_cm_connect_cmpl, ++ .cm_close_complete = bnx2i_cm_close_cmpl, ++ .cm_abort_complete = bnx2i_cm_abort_cmpl, ++ .cm_remote_close = bnx2i_cm_remote_close, ++ .cm_remote_abort = bnx2i_cm_remote_abort, ++ .owner = THIS_MODULE ++}; ++ ++ ++/** ++ * bnx2i_map_ep_dbell_regs - map connection doorbell registers ++ * ++ * maps connection's SQ and RQ doorbell registers, 5706/5708/5709 hosts these ++ * register in BAR #0. Whereas in 57710 these register are accessed by ++ * mapping BAR #1 ++ */ ++int bnx2i_map_ep_dbell_regs(struct bnx2i_endpoint *ep) ++{ ++ u32 cid_num; ++ u32 reg_off; ++ u32 first_l4l5; ++ u32 ctx_sz; ++ u32 config2; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) ++ resource_size_t reg_base; ++#else ++ unsigned long reg_base; ++#endif ++ ++ cid_num = bnx2i_get_cid_num(ep); ++ ++ if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) { ++ reg_base = pci_resource_start(ep->hba->pcidev, ++ BNX2X_DOORBELL_PCI_BAR); ++ reg_off = PAGE_SIZE * (cid_num & 0x1FFFF) + DPM_TRIGER_TYPE; ++ ep->qp.ctx_base = ioremap_nocache(reg_base + reg_off, 4); ++ if (ep->qp.ctx_base == NULL) ++ goto iomap_err; ++ else ++ goto arm_cq; ++ } ++ ++ reg_base = ep->hba->netdev->base_addr; ++ if ((test_bit(BNX2I_NX2_DEV_5709, &ep->hba->cnic_dev_type)) && ++ (ep->hba->mail_queue_access == BNX2I_MQ_BIN_MODE)) { ++ config2 = REG_RD(ep->hba, BNX2_MQ_CONFIG2); ++ first_l4l5 = config2 & BNX2_MQ_CONFIG2_FIRST_L4L5; ++ ctx_sz = (config2 & BNX2_MQ_CONFIG2_CONT_SZ) >> 3; ++ if (ctx_sz) ++ reg_off = CTX_OFFSET + MAX_CID_CNT * MB_KERNEL_CTX_SIZE ++ + PAGE_SIZE * ++ (((cid_num - first_l4l5) / ctx_sz) + 256); ++ else ++ reg_off = CTX_OFFSET + (MB_KERNEL_CTX_SIZE * cid_num); ++ } else ++ /* 5709 device in normal node and 5706/5708 devices */ ++ reg_off = CTX_OFFSET + (MB_KERNEL_CTX_SIZE * cid_num); ++ ++ ep->qp.ctx_base = ioremap_nocache(reg_base + reg_off, ++ MB_KERNEL_CTX_SIZE); ++ if (ep->qp.ctx_base == NULL) ++ goto iomap_err; ++arm_cq: ++ bnx2i_arm_cq_event_coalescing(ep, CNIC_ARM_CQE); ++ ++ return 0; ++ ++iomap_err: ++ return -ENOMEM; ++} +diff -r ffba7e1f063a drivers/scsi/bnx2i/bnx2i_init.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/bnx2i/bnx2i_init.c Wed Aug 05 10:51:49 2009 +0100 +@@ -0,0 +1,742 @@ ++/* bnx2i.c: Broadcom NetXtreme II iSCSI driver. ++ * ++ * Copyright (c) 2006 - 2009 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ * ++ * Written by: Anil Veerabhadrappa (anilgv@broadcom.com) ++ */ ++ ++#include "bnx2i.h" ++#ifdef __VMKLNX__ ++#include ++#include ++#endif ++ ++static struct list_head adapter_list; ++static u32 adapter_count; ++int bnx2i_reg_device = 0; ++ ++#define DRV_MODULE_NAME "bnx2i" ++#define DRV_MODULE_VERSION "1.8.9n" ++#define DRV_MODULE_RELDATE "Jul 22, 2009" ++ ++static char version[] __devinitdata = ++ "Broadcom NetXtreme II iSCSI Driver " DRV_MODULE_NAME \ ++ " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; ++ ++ ++MODULE_AUTHOR("Anil Veerabhadrappa "); ++MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/57710 iSCSI Driver"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_MODULE_VERSION); ++ ++static DEFINE_MUTEX(bnx2i_dev_lock); ++ ++unsigned int event_coal_div = 1; ++module_param(event_coal_div, int, 0664); ++MODULE_PARM_DESC(event_coal_div, "Event Coalescing Divide Factor"); ++ ++unsigned int bnx2i_nopout_when_cmds_active = 1; ++module_param(bnx2i_nopout_when_cmds_active, int, 0664); ++MODULE_PARM_DESC(bnx2i_nopout_when_cmds_active, ++ "iSCSI NOOP even when connection is not idle"); ++ ++unsigned int en_tcp_dack = 1; ++module_param(en_tcp_dack, int, 0664); ++MODULE_PARM_DESC(en_tcp_dack, "Enable TCP Delayed ACK"); ++ ++unsigned int time_stamps = 0; ++module_param(time_stamps, int, 0664); ++MODULE_PARM_DESC(time_stamps, "Enable TCP TimeStamps"); ++ ++unsigned int error_mask1 = 0x00; ++module_param(error_mask1, int, 0664); ++MODULE_PARM_DESC(error_mask1, "Config FW iSCSI Error Mask #1"); ++ ++unsigned int error_mask2 = 0x00; ++module_param(error_mask2, int, 0664); ++MODULE_PARM_DESC(error_mask2, "Config FW iSCSI Error Mask #2"); ++ ++unsigned int sq_size = 0; ++module_param(sq_size, int, 0664); ++MODULE_PARM_DESC(sq_size, "Configure SQ size"); ++ ++unsigned int rq_size = BNX2I_RQ_WQES_DEFAULT; ++module_param(rq_size, int, 0664); ++MODULE_PARM_DESC(rq_size, "Configure RQ size"); ++ ++unsigned int tcp_buf_size = 65536; ++module_param(tcp_buf_size, int, 0664); ++MODULE_PARM_DESC(tcp_buf_size, "TCP send/receive buffer size"); ++ ++unsigned int event_coal_min = 24; ++module_param(event_coal_min, int, 0664); ++MODULE_PARM_DESC(event_coal_min, "Event Coalescing Minimum Commands"); ++ ++unsigned int cmd_cmpl_per_work = 24; ++module_param(cmd_cmpl_per_work, int, 0664); ++MODULE_PARM_DESC(cmd_cmpl_per_work, "Number of CQE's processed per work"); ++ ++u64 iscsi_error_mask = 0x00; ++ ++extern struct cnic_ulp_ops bnx2i_cnic_cb; ++extern spinlock_t bnx2i_resc_lock; /* protects global data structures */ ++extern struct tcp_port_mngt bnx2i_tcp_port_tbl; ++ ++static void bnx2i_unreg_one_device(struct bnx2i_hba *hba) ; ++#ifndef __VMKLNX__ ++static int bnx2i_bind_adapter_devices(struct bnx2i_hba *hba); ++static void bnx2i_unbind_adapter_devices(struct bnx2i_hba *hba); ++#else ++void bnx2i_unbind_adapter_devices(struct bnx2i_hba *hba); ++#endif ++ ++ ++/** ++ * bnx2i_identify_device - identifies NetXtreme II device type ++ * ++ * @hba: Adapter structure pointer ++ * ++ * This function identifies the NX2 device type and sets appropriate ++ * queue mailbox register access method, 5709 requires driver to ++ * access MBOX regs using *bin* mode ++ **/ ++void bnx2i_identify_device(struct bnx2i_hba *hba) ++{ ++ hba->cnic_dev_type = 0; ++ if ((hba->pci_did == PCI_DEVICE_ID_NX2_5706) || ++ (hba->pci_did == PCI_DEVICE_ID_NX2_5706S)) ++ set_bit(BNX2I_NX2_DEV_5706, &hba->cnic_dev_type); ++ else if ((hba->pci_did == PCI_DEVICE_ID_NX2_5708) || ++ (hba->pci_did == PCI_DEVICE_ID_NX2_5708S)) ++ set_bit(BNX2I_NX2_DEV_5708, &hba->cnic_dev_type); ++ else if ((hba->pci_did == PCI_DEVICE_ID_NX2_5709) || ++ (hba->pci_did == PCI_DEVICE_ID_NX2_5709S)) { ++ set_bit(BNX2I_NX2_DEV_5709, &hba->cnic_dev_type); ++ hba->mail_queue_access = 0| BNX2I_MQ_BIN_MODE; ++ } else if (hba->pci_did == PCI_DEVICE_ID_NX2_57710 || ++ hba->pci_did == PCI_DEVICE_ID_NX2_57711 || ++ hba->pci_did == PCI_DEVICE_ID_NX2_57711E) ++ set_bit(BNX2I_NX2_DEV_57710, &hba->cnic_dev_type); ++ else ++ printk(KERN_ERR "bnx2i- unknown device, 0x%x\n", hba->pci_did); ++} ++ ++/** ++ * get_adapter_list_head - returns head of adapter list ++ * ++ **/ ++struct bnx2i_hba *get_adapter_list_head(void) ++{ ++ struct bnx2i_hba *hba = NULL; ++ struct bnx2i_hba *tmp_hba; ++ ++ if (!adapter_count) ++ goto hba_not_found; ++ ++ mutex_lock(&bnx2i_dev_lock); ++ list_for_each_entry(tmp_hba, &adapter_list, link) { ++ if (tmp_hba->cnic && tmp_hba->cnic->cm_select_dev) { ++ hba = tmp_hba; ++ break; ++ } ++ } ++ mutex_unlock(&bnx2i_dev_lock); ++hba_not_found: ++ return hba; ++} ++ ++/** ++ * bnx2i_get_hba_from_template - maps scsi_transport_template to ++ * bnx2i adapter pointer ++ * @scsit: scsi transport template pointer ++ * ++ **/ ++struct bnx2i_hba *bnx2i_get_hba_from_template( ++ struct scsi_transport_template *scsit) ++{ ++ struct list_head *list; ++ struct bnx2i_hba *hba = NULL; ++ int match_found = 0; ++ ++ mutex_lock(&bnx2i_dev_lock); ++ list_for_each(list, &adapter_list) { ++ hba = (struct bnx2i_hba *) list; ++ if (hba->shost_template == scsit) { ++ match_found = 1; ++ break; ++ } ++ } ++ mutex_unlock(&bnx2i_dev_lock); ++ ++ if (match_found == 0) ++ hba = NULL; ++ return hba; ++} ++ ++ ++/** ++ * bnx2i_find_hba_for_cnic - maps cnic device instance to bnx2i adapter instance ++ * ++ * @cnic: pointer to cnic device instance ++ * ++ **/ ++struct bnx2i_hba *bnx2i_find_hba_for_cnic(struct cnic_dev *cnic) ++{ ++ struct bnx2i_hba *hba, *temp; ++ ++ mutex_lock(&bnx2i_dev_lock); ++ list_for_each_entry_safe(hba, temp, &adapter_list, link) { ++ if (hba->cnic == cnic) { ++ mutex_unlock(&bnx2i_dev_lock); ++ return hba; ++ } ++ } ++ mutex_unlock(&bnx2i_dev_lock); ++ return NULL; ++} ++ ++ ++#ifdef __VMKLNX__ ++static void bnx2i_check_iscsi_support(struct bnx2i_hba *hba) ++{ ++ if (!hba->shost_template) ++ return; ++ ++ /* unless you register the device cnic can't get information ++ * to determine iscsi is supported or not ++ */ ++ bnx2i_register_device(hba, BNX2I_REGISTER_HBA_FORCED); ++ bnx2i_register_xport(hba); ++ bnx2i_unreg_one_device(hba); ++} ++ ++void bnx2i_lookup_iscsi_hba_vm(void) ++{ ++ struct list_head *list; ++ struct bnx2i_hba *hba = NULL; ++ ++ if (!adapter_count) ++ return; ++ ++ list_for_each(list, &adapter_list) { ++ hba = (struct bnx2i_hba *) list; ++ ++ bnx2i_check_iscsi_support(hba); ++ } ++} ++#endif /* __VMKLNX__ */ ++ ++/** ++ * bnx2i_start - cnic callback to initialize & start adapter instance ++ * ++ * @handle: transparent handle pointing to adapter structure ++ * ++ * This function maps adapter structure to pcidev structure and initiates ++ * firmware handshake to enable/initialize on chip iscsi components ++ * This bnx2i - cnic interface api callback is issued after following ++ * 2 conditions are met - ++ * a) underlying network interface is up (marked by event 'NETDEV_UP' ++ * from netdev ++ * b) bnx2i adapter instance is registered ++ **/ ++void bnx2i_start(void *handle) ++{ ++#define BNX2I_INIT_POLL_TIME (1000 / HZ) ++ struct bnx2i_hba *hba = handle; ++ int i = HZ; ++ ++#ifndef __VMKLNX__ ++ bnx2i_bind_adapter_devices(hba); ++#endif ++ bnx2i_send_fw_iscsi_init_msg(hba); ++ do { ++ if (test_bit(ADAPTER_STATE_UP, &hba->adapter_state) || ++ test_bit(ADAPTER_STATE_INIT_FAILED, &hba->adapter_state)) ++ break; ++ msleep(BNX2I_INIT_POLL_TIME); ++ } while (i--); ++} ++ ++ ++/** ++ * bnx2i_stop - cnic callback to shutdown adapter instance ++ * ++ * @handle: transparent handle pointing to adapter structure ++ * ++ * driver checks if adapter is already in shutdown mode, if not start ++ * the shutdown process ++ **/ ++void bnx2i_stop(void *handle) ++{ ++ struct bnx2i_hba *hba = handle; ++ ++ /* check if cleanup happened in GOING_DOWN context */ ++ if (!test_bit(ADAPTER_STATE_GOING_DOWN, &hba->adapter_state)) { ++ mutex_lock(&hba->net_dev_lock); ++ set_bit(ADAPTER_STATE_GOING_DOWN, &hba->adapter_state); ++ mutex_unlock(&hba->net_dev_lock); ++ bnx2i_start_iscsi_hba_shutdown(hba); ++ } ++ clear_bit(ADAPTER_STATE_GOING_DOWN, &hba->adapter_state); ++ clear_bit(ADAPTER_STATE_UP, &hba->adapter_state); ++ ++} ++ ++/** ++ * bnx2i_register_device - register bnx2i adapter instance with the cnic driver ++ * ++ * @hba: Adapter instance to register ++ * @reg_mode: 0 -> register only licensed hba, 1 -> all ++ * ++ * registers bnx2i adapter instance with the cnic driver while holding the ++ * adapter structure lock ++ **/ ++void bnx2i_register_device(struct bnx2i_hba *hba, int reg_mode) ++{ ++ if (test_bit(ADAPTER_STATE_GOING_DOWN, &hba->adapter_state) || ++ test_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic) || ++ ((reg_mode == BNX2I_REGISTER_HBA_SUPPORTED) && ++ (!hba->cnic->max_iscsi_conn))) ++ return; ++ ++ hba->cnic->register_device(hba->cnic, CNIC_ULP_ISCSI, (void *) hba); ++ ++ bnx2i_reg_device++; ++ set_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic); ++} ++ ++ ++/** ++ * bnx2i_reg_dev_all - registers all bnx2i adapter instances with the ++ * cnic driver ++ * ++ * registers all bnx2i adapter instances with the cnic driver while holding ++ * the global resource lock ++ **/ ++void bnx2i_reg_dev_all(void) ++{ ++ struct bnx2i_hba *hba, *temp; ++ ++ mutex_lock(&bnx2i_dev_lock); ++ list_for_each_entry_safe(hba, temp, &adapter_list, link) { ++#ifdef __VMKLNX__ ++ bnx2i_register_device(hba, BNX2I_REGISTER_HBA_SUPPORTED); ++#else ++ bnx2i_register_device(hba, BNX2I_REGISTER_HBA_FORCED); ++#endif ++ } ++ mutex_unlock(&bnx2i_dev_lock); ++} ++ ++ ++/** ++ * bnx2i_unreg_one_device - unregister bnx2i adapter instance with ++ * the cnic driver ++ * ++ * @hba: Adapter instance to unregister ++ * ++ * registers bnx2i adapter instance with the cnic driver while holding ++ * the adapter structure lock ++ **/ ++static void bnx2i_unreg_one_device(struct bnx2i_hba *hba) ++{ ++ if (hba->ofld_conns_active || ++ !test_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic) || ++ test_bit(ADAPTER_STATE_GOING_DOWN, &hba->adapter_state)) { ++ return; ++ } ++ ++ hba->cnic->unregister_device(hba->cnic, CNIC_ULP_ISCSI); ++ barrier(); ++ bnx2i_reg_device--; ++ /* ep_disconnect could come before NETDEV_DOWN, driver won't ++ * see NETDEV_DOWN as it already unregistered itself. ++ */ ++ hba->adapter_state = 0; ++ clear_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic); ++#ifndef __VMKLNX__ ++ bnx2i_unbind_adapter_devices(hba); ++#endif ++} ++ ++/** ++ * bnx2i_unreg_dev_all - unregisters all bnx2i adapter instances with the ++ * cnic driver ++ * ++ * unregisters all bnx2i adapter instances with the cnic driver while holding ++ * the global resource lock ++ **/ ++void bnx2i_unreg_dev_all(void) ++{ ++ struct bnx2i_hba *hba, *temp; ++ ++ mutex_lock(&bnx2i_dev_lock); ++ list_for_each_entry_safe(hba, temp, &adapter_list, link) ++ bnx2i_unreg_one_device(hba); ++ mutex_unlock(&bnx2i_dev_lock); ++} ++ ++ ++/** ++ * bnx2i_bind_adapter_devices - binds bnx2i adapter with the associated ++ * pcidev structure ++ * ++ * @hba: Adapter instance ++ * ++ * With newly introduced changes to bnx2i - cnic interface, cnic_dev's 'pcidev' ++ * field will be valid only after bnx2i registers the device instance. ++ * Earlier this field was valid right during device enumeration process ++ **/ ++#ifndef __VMKLNX__ ++static ++#endif ++int bnx2i_bind_adapter_devices(struct bnx2i_hba *hba) ++{ ++ struct cnic_dev *cnic; ++ int nx2_10g_dev = 0; ++ ++ if (!hba->cnic) ++ return -ENODEV; ++ ++ cnic = hba->cnic; ++ hba->pcidev = cnic->pcidev; ++ if (hba->pcidev) { ++ pci_dev_get(hba->pcidev); ++ hba->pci_did = hba->pcidev->device; ++ hba->pci_vid = hba->pcidev->vendor; ++ hba->pci_sdid = hba->pcidev->subsystem_device; ++ hba->pci_svid = hba->pcidev->subsystem_vendor; ++ hba->pci_func = PCI_FUNC(hba->pcidev->devfn); ++ hba->pci_devno = PCI_SLOT(hba->pcidev->devfn); ++ } ++ ++ bnx2i_identify_device(hba); ++ ++ if (test_bit(BNX2I_NX2_DEV_5709, &hba->cnic_dev_type)) { ++ hba->regview = ioremap_nocache(hba->netdev->base_addr, ++ BNX2_MQ_CONFIG2); ++ if (!hba->regview) ++ goto mem_err; ++ } else if (test_bit(BNX2I_NX2_DEV_57710, &hba->cnic_dev_type)) { ++ nx2_10g_dev = 1; ++ hba->regview = ioremap_nocache(hba->netdev->base_addr, 4096); ++ if (!hba->regview) ++ goto mem_err; ++ } ++ ++ if (nx2_10g_dev) { ++ hba->conn_teardown_tmo = 15 * HZ; ++ hba->conn_ctx_destroy_tmo = 6 * HZ; ++ hba->hba_shutdown_tmo = 240 * HZ; ++ } else { ++ hba->conn_teardown_tmo = 6 * HZ; ++ hba->conn_ctx_destroy_tmo = 2 * HZ; ++ hba->hba_shutdown_tmo = 30 * HZ; ++ } ++ ++ if (bnx2i_setup_mp_bdt(hba)) ++ goto mem_err; ++ ++ return 0; ++ ++mem_err: ++ bnx2i_unbind_adapter_devices(hba); ++ return -ENOMEM; ++} ++ ++ ++/** ++ * bnx2i_unbind_adapter_devices - removes bnx2i adapter to pcidev mapping ++ * ++ * @hba: Adapter instance ++ * ++ **/ ++void bnx2i_unbind_adapter_devices(struct bnx2i_hba *hba) ++{ ++ if (hba->regview) { ++ iounmap(hba->regview); ++ hba->regview = NULL; ++ } ++ ++ bnx2i_free_mp_bdt(hba); ++ ++ if (hba->pcidev) ++ pci_dev_put(hba->pcidev); ++ hba->pcidev = NULL; ++#ifdef __VMKLNX__ ++ scsi_remove_host(hba->shost); ++#endif ++} ++ ++ ++/** ++ * bnx2i_init_one - initialize an adapter instance and allocate necessary ++ * memory resources ++ * ++ * @hba: bnx2i adapter instance ++ * @cnic: cnic device handle ++ * ++ * Global resource lock and host adapter lock is held during critical sections ++ * below. This routine is called from cnic_register_driver() context and ++ * work horse thread which does majority of device specific initialization ++ **/ ++static int bnx2i_init_one(struct bnx2i_hba *hba, struct cnic_dev *cnic) ++{ ++ int rc; ++ ++ mutex_lock(&bnx2i_dev_lock); ++ hba->netdev = cnic->netdev; ++ if (bnx2i_reg_device && ++ !test_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic)) { ++ rc = cnic->register_device(cnic, CNIC_ULP_ISCSI, ++ (void *) hba); ++ if (!rc) { ++ bnx2i_reg_device++; ++ hba->age++; ++ set_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic); ++ } else if (rc == -EBUSY) /* duplicate registration */ ++ printk(KERN_ALERT "bnx2i, duplicate registration" ++ "hba=%p, cnic=%p\n", hba, cnic); ++ else if (rc == -EAGAIN) ++ printk(KERN_ERR "bnx2i, driver not registered\n"); ++ else if (rc == -EINVAL) ++ printk(KERN_ERR "bnx2i, invalid type %d\n", CNIC_ULP_ISCSI); ++ else ++ printk(KERN_ERR "bnx2i dev reg, unknown error, %d\n", rc); ++ ++ if (rc) ++ goto ret_err; ++ } ++ ++ if (cnic->netdev) ++ memcpy(hba->mac_addr, cnic->netdev->dev_addr, MAX_ADDR_LEN); ++ ++ /* Allocate memory & initialize the SCSI/iSCSI host templates */ ++ rc = bnx2i_register_xport(hba); ++#ifndef __VMKLNX__ ++ if (rc) ++ goto failed_xport_reg; ++ ++ /* create 'sysfs' device objects */ ++ rc = bnx2i_register_sysfs(hba); ++ if (rc) ++ goto failed_sysfs_reg; ++ ++ bnx2i_tcp_port_tbl.num_required += hba->max_active_conns; ++#endif ++ list_add_tail(&hba->link, &adapter_list); ++ adapter_count++; ++ mutex_unlock(&bnx2i_dev_lock); ++ ++ return 0; ++ ++#ifndef __VMKLNX__ ++failed_sysfs_reg: ++ bnx2i_deregister_xport(hba); ++ bnx2i_free_iscsi_scsi_template(hba); ++ ++failed_xport_reg: ++ bnx2i_unbind_adapter_devices(hba); ++#endif ++ cnic->unregister_device(cnic, CNIC_ULP_ISCSI); ++ bnx2i_reg_device--; ++ clear_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic); ++ret_err: ++ mutex_unlock(&bnx2i_dev_lock); ++ return rc; ++} ++ ++ ++/** ++ * bnx2i_ulp_init - initialize an adapter instance ++ * ++ * @dev: cnic device handle ++ * ++ * Called from cnic_register_driver() context to initialize all enumerated ++ * cnic devices. This routine allocate adapter structure and other ++ * device specific resources. ++ **/ ++void bnx2i_ulp_init(struct cnic_dev *dev) ++{ ++ struct bnx2i_hba *hba; ++ ++ /* Allocate a HBA structure for this device */ ++ hba = bnx2i_alloc_hba(dev); ++ if (!hba) { ++ printk(KERN_ERR "bnx2i init: hba initialization failed\n"); ++ return; ++ } ++ ++ /* Get PCI related information and update hba struct members */ ++ clear_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic); ++ if (bnx2i_init_one(hba, dev)) { ++ printk(KERN_ERR "bnx2i - hba %p init failed\n", hba); ++ bnx2i_free_hba(hba); ++ } else ++ hba->cnic = dev; ++} ++ ++ ++/** ++ * bnx2i_ulp_exit - shuts down adapter instance and frees all resources ++ * ++ * @dev: cnic device handle ++ * ++ **/ ++void bnx2i_ulp_exit(struct cnic_dev *dev) ++{ ++ struct bnx2i_hba *hba; ++ ++ hba = bnx2i_find_hba_for_cnic(dev); ++ if (!hba) { ++ printk(KERN_INFO "bnx2i_ulp_exit: hba not " ++ "found, dev 0x%p\n", dev); ++ return; ++ } ++ mutex_lock(&bnx2i_dev_lock); ++ list_del_init(&hba->link); ++ bnx2i_tcp_port_tbl.num_required -= hba->max_active_conns; ++ adapter_count--; ++ ++ /* cleanup 'sysfs' devices and classes */ ++ bnx2i_unregister_sysfs(hba); ++ ++ if (test_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic)) { ++ hba->cnic->unregister_device(hba->cnic, CNIC_ULP_ISCSI); ++ clear_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic); ++ bnx2i_reg_device--; ++#ifndef __VMKLNX__ ++ bnx2i_unbind_adapter_devices(hba); ++#endif ++ } ++ mutex_unlock(&bnx2i_dev_lock); ++ ++ if (hba->pcidev) ++ pci_dev_put(hba->pcidev); ++ ++ bnx2i_deregister_xport(hba); ++ bnx2i_free_iscsi_scsi_template(hba); ++ bnx2i_free_hba(hba); ++} ++ ++ ++/** ++ * bnx2i_mod_init - module init entry point ++ * ++ * initialize any driver wide global data structures such as endpoint pool, ++ * tcp port manager/queue, sysfs. finally driver will register itself ++ * with the cnic module ++ **/ ++static int __init bnx2i_mod_init(void) ++{ ++ int rc; ++ ++ printk(KERN_INFO "%s", version); ++ ++ INIT_LIST_HEAD(&adapter_list); ++ adapter_count = 0; ++ ++ mutex_init(&bnx2i_dev_lock); ++ rc = bnx2i_alloc_ep_pool(); ++ if (rc) { ++ printk(KERN_ERR "bnx2i: unable to alloc ep pool\n"); ++ goto out; ++ } ++ ++#ifndef __VMKLNX__ ++ rc = bnx2i_init_tcp_port_mngr(); ++ if (rc) { ++ printk(KERN_ERR "bnx2i: unable init TCP port manager\n"); ++ goto tcp_mgr_err; ++ } ++ ++ /* create 'sysfs' class object */ ++ rc = bnx2i_sysfs_setup(); ++ if (rc) ++ goto sysfs_err; ++#endif ++ ++ rc = cnic_register_driver(CNIC_ULP_ISCSI, &bnx2i_cnic_cb); ++ if (rc) { ++ printk(KERN_ERR "bnx2i: unable to register driver with cnic module\n"); ++ goto drv_reg_failed; ++ } ++ ++#ifdef __VMKLNX__ ++ bnx2i_lookup_iscsi_hba_vm(); ++#else ++ bnx2i_ioctl_init(); ++#endif ++ return 0; ++ ++drv_reg_failed: ++#ifndef __VMKLNX__ ++ bnx2i_sysfs_cleanup(); ++sysfs_err: ++ bnx2i_cleanup_tcp_port_mngr(); ++tcp_mgr_err: ++#endif ++ bnx2i_release_ep_pool(); ++out: ++ return rc; ++} ++ ++ ++/** ++ * bnx2i_mod_exit - module cleanup/exit entry point ++ * ++ * Global resource lock and host adapter lock is held during critical sections ++ * in this function. Driver will browse through the adapter list, cleans-up ++ * each instance, unregisters iscsi transport name and finally driver will ++ * unregister itself with the cnic module ++ **/ ++static void __exit bnx2i_mod_exit(void) ++{ ++ struct bnx2i_hba *hba; ++ ++ mutex_lock(&bnx2i_dev_lock); ++ while (!list_empty(&adapter_list)) { ++ hba = list_entry(adapter_list.next, struct bnx2i_hba, link); ++ list_del(&hba->link); ++ adapter_count--; ++ ++#ifndef __VMKLNX__ ++ /* cleanup 'sysfs' devices and classes */ ++ bnx2i_unregister_sysfs(hba); ++#endif ++ ++ if (test_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic)) { ++ hba->cnic->unregister_device(hba->cnic, CNIC_ULP_ISCSI); ++ clear_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic); ++ bnx2i_reg_device--; ++#ifndef __VMKLNX__ ++ bnx2i_unbind_adapter_devices(hba); ++#endif ++ } ++ ++ if (hba->pcidev) ++ pci_dev_put(hba->pcidev); ++ bnx2i_deregister_xport(hba); ++ bnx2i_free_iscsi_scsi_template(hba); ++ bnx2i_free_hba(hba); ++ } ++ mutex_unlock(&bnx2i_dev_lock); ++ ++#ifndef __VMKLNX__ ++ bnx2i_ioctl_cleanup(); ++#endif ++ cnic_unregister_driver(CNIC_ULP_ISCSI); ++ ++#ifndef __VMKLNX__ ++ bnx2i_sysfs_cleanup(); ++ bnx2i_cleanup_tcp_port_mngr(); ++#endif ++ bnx2i_release_ep_pool(); ++} ++ ++module_init(bnx2i_mod_init); ++module_exit(bnx2i_mod_exit); +diff -r ffba7e1f063a drivers/scsi/bnx2i/bnx2i_ioctl.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/bnx2i/bnx2i_ioctl.h Wed Aug 05 10:51:49 2009 +0100 +@@ -0,0 +1,46 @@ ++/* bnx2i_ioctl.h: Broadcom NetXtreme II iSCSI driver. ++ * ++ * Copyright (c) 2006 - 2009 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ * ++ * Written by: Anil Veerabhadrappa (anilgv@broadcom.com) ++ */ ++#ifndef _BNX2I_IOCTL_H ++#define _BNX2I_IOCTL_H ++ ++#define MAX_SIG_SIZE 32 ++#define MAX_XPORT_NAME 16 ++#define MAX_DEV_NAME_SIZE 16 ++ ++#define BNX2I_MGMT_SIGNATURE "bnx2i-mgmt:1.0" ++ ++ ++ ++struct bnx2i_ioctl_header { ++ char signature[MAX_SIG_SIZE]; ++ char xport_name[MAX_XPORT_NAME]; ++ char dev_name[MAX_DEV_NAME_SIZE]; ++}; ++ ++ ++struct bnx2i_get_port_count { ++ struct bnx2i_ioctl_header hdr; ++ unsigned int port_count; ++}; ++ ++struct bnx2i_set_port_num { ++ struct bnx2i_ioctl_header hdr; ++ unsigned int num_ports; ++ unsigned short tcp_port[1]; ++}; ++ ++ ++#define BNX2I_IOCTL_GET_PORT_REQ \ ++ _IOWR('I', 101, struct bnx2i_get_port_count) ++#define BNX2I_IOCTL_SET_TCP_PORT \ ++ _IOWR('I', 102, struct bnx2i_set_port_num) ++ ++#endif +diff -r ffba7e1f063a drivers/scsi/bnx2i/bnx2i_iscsi.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/bnx2i/bnx2i_iscsi.c Wed Aug 05 10:51:49 2009 +0100 +@@ -0,0 +1,6202 @@ ++/* bnx2i_iscsi.c: Broadcom NetXtreme II iSCSI driver. ++ * ++ * Copyright (c) 2006 - 2009 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ * ++ * Written by: Anil Veerabhadrappa (anilgv@broadcom.com) ++ */ ++ ++#include "bnx2i.h" ++#include ++#ifdef __VMKLNX__ ++#include ++#include ++#endif ++#include ++#include ++ ++struct scsi_host_template bnx2i_host_template; ++struct iscsi_transport bnx2i_iscsi_transport; ++struct file_operations bnx2i_mgmt_fops; ++extern unsigned int bnx2i_nopout_when_cmds_active; ++extern unsigned int tcp_buf_size; ++extern unsigned int en_tcp_dack; ++extern unsigned int time_stamps; ++ ++/* ++ * Global endpoint resource info ++ */ ++static void *bnx2i_ep_pages[MAX_PAGES_PER_CTRL_STRUCT_POOL]; ++static struct list_head bnx2i_free_ep_list; ++static struct list_head bnx2i_unbound_ep; ++static u32 bnx2i_num_free_ep; ++static u32 bnx2i_max_free_ep; ++static DEFINE_SPINLOCK(bnx2i_resc_lock); /* protects global resources */ ++struct tcp_port_mngt bnx2i_tcp_port_tbl; ++ ++extern unsigned int sq_size; ++extern unsigned int rq_size; ++ ++ ++int use_poll_timer = 1; ++ ++/* Char device major number */ ++static int bnx2i_major_no; ++ ++static struct io_bdt *bnx2i_alloc_bd_table(struct bnx2i_sess *sess, ++ struct bnx2i_cmd *); ++ ++static struct scsi_host_template * ++bnx2i_alloc_scsi_host_template(struct bnx2i_hba *hba, struct cnic_dev *cnic); ++static void ++bnx2i_free_scsi_host_template(struct scsi_host_template *scsi_template); ++static struct iscsi_transport * ++bnx2i_alloc_iscsi_transport(struct bnx2i_hba *hba, struct cnic_dev *cnic, struct scsi_host_template *); ++static void bnx2i_free_iscsi_transport(struct iscsi_transport *iscsi_transport); ++static void bnx2i_release_session_resc(struct iscsi_cls_session *cls_session); ++ ++#ifdef __VMKLNX__ ++static void bnx2i_conn_main_worker(unsigned long data); ++vmk_int32 bnx2i_get_570x_limit(enum iscsi_param param, ++ TransportParamLimit *limit, vmk_int32 maxListLen); ++vmk_int32 bnx2i_get_5771x_limit(enum iscsi_param param, ++ TransportParamLimit *limit, ++ vmk_int32 maxListLen); ++extern int bnx2i_cqe_work_pending(struct bnx2i_conn *conn); ++#else ++#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) ++static void bnx2i_conn_main_worker(struct work_struct *work); ++#else ++static void bnx2i_conn_main_worker(void *data); ++extern int bnx2i_cqe_work_pending(struct bnx2i_conn *conn); ++#endif ++#endif /*__VMKLNX__ */ ++static void bnx2i_xmit_work_send_cmd(struct bnx2i_conn *conn, struct bnx2i_cmd *cmd); ++static void bnx2i_cleanup_task_context(struct bnx2i_sess *sess, ++ struct bnx2i_cmd *cmd, int reason); ++ ++ ++#ifdef __VMKLNX__ ++extern int bnx2i_bind_adapter_devices(struct bnx2i_hba *hba); ++#endif ++void bnx2i_unbind_adapter_devices(struct bnx2i_hba *hba); ++static void bnx2i_conn_poll(unsigned long data); ++ ++/* ++ * iSCSI Session's hostdata organization: ++ * ++ * *------------------* <== hostdata_session(host->hostdata) ++ * | ptr to class sess| ++ * |------------------| <== iscsi_hostdata(host->hostdata) ++ * | iscsi_session | ++ * *------------------* ++ */ ++ ++#define hostdata_privsize(_sz) (sizeof(unsigned long) + _sz + \ ++ _sz % sizeof(unsigned long)) ++#define hostdata_session(_hostdata) (iscsi_ptr(*(unsigned long *)_hostdata)) ++ ++#define session_to_cls(_sess) hostdata_session(_sess->shost->hostdata) ++ ++/** ++ * bnx2i_alloc_tcp_port - allocates a tcp port from the free list ++ * ++ * assumes this function is called with 'bnx2i_resc_lock' held ++ **/ ++#ifndef __VMKLNX__ ++static u16 bnx2i_alloc_tcp_port(void) ++{ ++ u16 tcp_port; ++ ++ if (!bnx2i_tcp_port_tbl.num_free_ports || !bnx2i_tcp_port_tbl.free_q) ++ return 0; ++ ++ tcp_port = bnx2i_tcp_port_tbl.free_q[bnx2i_tcp_port_tbl.cons_idx]; ++ bnx2i_tcp_port_tbl.cons_idx++; ++ bnx2i_tcp_port_tbl.cons_idx %= bnx2i_tcp_port_tbl.max_idx; ++ bnx2i_tcp_port_tbl.num_free_ports--; ++ ++ return tcp_port; ++} ++#endif ++ ++ ++/** ++ * bnx2i_free_tcp_port - Frees the given tcp port back to free pool ++ * ++ * @port: tcp port number being freed ++ * ++ * assumes this function is called with 'bnx2i_resc_lock' held ++ **/ ++static void bnx2i_free_tcp_port(u16 port) ++{ ++ if (!bnx2i_tcp_port_tbl.free_q) ++ return; ++ ++ bnx2i_tcp_port_tbl.free_q[bnx2i_tcp_port_tbl.prod_idx] = port; ++ bnx2i_tcp_port_tbl.prod_idx++; ++ bnx2i_tcp_port_tbl.prod_idx %= bnx2i_tcp_port_tbl.max_idx; ++ bnx2i_tcp_port_tbl.num_free_ports++; ++} ++ ++/** ++ * bnx2i_tcp_port_new_entry - place 'bnx2id' allocated tcp port number ++ * to free list ++ * ++ * @port: tcp port number being added to free pool ++ * ++ * 'bnx2i_resc_lock' is held while operating on global tcp port table ++ **/ ++void bnx2i_tcp_port_new_entry(u16 tcp_port) ++{ ++ u32 idx = bnx2i_tcp_port_tbl.prod_idx; ++ ++ spin_lock(&bnx2i_resc_lock); ++ bnx2i_tcp_port_tbl.free_q[idx] = tcp_port; ++ bnx2i_tcp_port_tbl.prod_idx++; ++ bnx2i_tcp_port_tbl.prod_idx %= bnx2i_tcp_port_tbl.max_idx; ++ bnx2i_tcp_port_tbl.num_free_ports++; ++ bnx2i_tcp_port_tbl.num_required--; ++ spin_unlock(&bnx2i_resc_lock); ++} ++ ++/** ++ * bnx2i_init_tcp_port_mngr - initializes tcp port manager ++ * ++ */ ++int bnx2i_init_tcp_port_mngr(void) ++{ ++ int mem_size; ++ int rc = 0; ++ ++ bnx2i_tcp_port_tbl.num_free_ports = 0; ++ bnx2i_tcp_port_tbl.prod_idx = 0; ++ bnx2i_tcp_port_tbl.cons_idx = 0; ++ bnx2i_tcp_port_tbl.max_idx = 0; ++ bnx2i_tcp_port_tbl.num_required = 0; ++ ++#define BNX2I_MAX_TCP_PORTS 1024 ++ ++ bnx2i_tcp_port_tbl.port_tbl_size = BNX2I_MAX_TCP_PORTS; ++ ++ mem_size = sizeof(u16) * bnx2i_tcp_port_tbl.port_tbl_size; ++ if (bnx2i_tcp_port_tbl.port_tbl_size) { ++ bnx2i_tcp_port_tbl.free_q = kmalloc(mem_size, GFP_KERNEL); ++ ++ if (bnx2i_tcp_port_tbl.free_q) ++ bnx2i_tcp_port_tbl.max_idx = ++ bnx2i_tcp_port_tbl.port_tbl_size; ++ else ++ rc = -ENOMEM; ++ } ++ ++ return rc; ++} ++ ++ ++/** ++ * bnx2i_cleanup_tcp_port_mngr - frees memory held by global tcp port table ++ * ++ */ ++void bnx2i_cleanup_tcp_port_mngr(void) ++{ ++ kfree(bnx2i_tcp_port_tbl.free_q); ++ bnx2i_tcp_port_tbl.free_q = NULL; ++ bnx2i_tcp_port_tbl.num_free_ports = 0; ++} ++ ++static int bnx2i_adapter_ready(struct bnx2i_hba *hba) ++{ ++ int retval = 0; ++ ++ if (!hba || !test_bit(ADAPTER_STATE_UP, &hba->adapter_state) || ++ test_bit(ADAPTER_STATE_GOING_DOWN, &hba->adapter_state) || ++ test_bit(ADAPTER_STATE_LINK_DOWN, &hba->adapter_state)) ++ retval = -EPERM; ++ return retval; ++} ++ ++ ++/** ++ * bnx2i_get_write_cmd_bd_idx - identifies various BD bookmarks for a ++ * scsi write command ++ * ++ * @cmd: iscsi cmd struct pointer ++ * @buf_off: absolute buffer offset ++ * @start_bd_off: u32 pointer to return the offset within the BD ++ * indicated by 'start_bd_idx' on which 'buf_off' falls ++ * @start_bd_idx: index of the BD on which 'buf_off' falls ++ * ++ * identifies & marks various bd info for imm data, unsolicited data ++ * and the first solicited data seq. ++ */ ++static void bnx2i_get_write_cmd_bd_idx(struct bnx2i_cmd *cmd, u32 buf_off, ++ u32 *start_bd_off, u32 *start_bd_idx) ++{ ++ u32 cur_offset = 0; ++ u32 cur_bd_idx = 0; ++ struct iscsi_bd *bd_tbl; ++ ++ if (!cmd->bd_tbl || !cmd->bd_tbl->bd_tbl) ++ return; ++ ++ bd_tbl = cmd->bd_tbl->bd_tbl; ++ if (buf_off) { ++ while (buf_off >= (cur_offset + bd_tbl->buffer_length)) { ++ cur_offset += bd_tbl->buffer_length; ++ cur_bd_idx++; ++ bd_tbl++; ++ } ++ } ++ ++ *start_bd_off = buf_off - cur_offset; ++ *start_bd_idx = cur_bd_idx; ++} ++ ++/** ++ * bnx2i_setup_write_cmd_bd_info - sets up BD various information for ++ * scsi write command ++ * ++ * @cmd: iscsi cmd struct pointer ++ * ++ * identifies & marks various bd info for immediate data, unsolicited data ++ * and first solicited data seq which includes BD start index & BD buf off ++ * This function takes into account iscsi parameter such as immediate data ++ * and unsolicited data is support on this connection ++ * ++ */ ++static void bnx2i_setup_write_cmd_bd_info(struct bnx2i_cmd *cmd) ++{ ++ struct bnx2i_sess *sess; ++ u32 start_bd_offset; ++ u32 start_bd_idx; ++ u32 buffer_offset = 0; ++ u32 seq_len = 0; ++ u32 fbl, mrdsl; ++ u32 cmd_len = cmd->req.total_data_transfer_length; ++ ++ sess = cmd->conn->sess; ++ ++ /* if ImmediateData is turned off & IntialR2T is turned on, ++ * there will be no immediate or unsolicited data, just return. ++ */ ++ if (sess->initial_r2t && !sess->imm_data) ++ return; ++ ++ fbl = sess->first_burst_len; ++ mrdsl = cmd->conn->max_data_seg_len_xmit; ++ ++ /* Immediate data */ ++ if (sess->imm_data) { ++ seq_len = min(mrdsl, fbl); ++ seq_len = min(cmd_len, seq_len); ++ buffer_offset += seq_len; ++ } ++ ++ if (seq_len == cmd_len) ++ return; ++ ++ if (!sess->initial_r2t) { ++ if (seq_len >= fbl) ++ goto r2t_data; ++ seq_len = min(fbl, cmd_len) - seq_len; ++ bnx2i_get_write_cmd_bd_idx(cmd, buffer_offset, ++ &start_bd_offset, &start_bd_idx); ++ cmd->req.ud_buffer_offset = start_bd_offset; ++ cmd->req.ud_start_bd_index = start_bd_idx; ++ buffer_offset += seq_len; ++ } ++r2t_data: ++ if (buffer_offset != cmd_len) { ++ bnx2i_get_write_cmd_bd_idx(cmd, buffer_offset, ++ &start_bd_offset, &start_bd_idx); ++ if ((start_bd_offset > fbl) || ++ (start_bd_idx > scsi_sg_count(cmd->scsi_cmd))) { ++ int i = 0; ++ ++ printk(KERN_ALERT "bnx2i- error, buf offset 0x%x " ++ "bd_valid %d use_sg %d\n", ++ buffer_offset, cmd->bd_tbl->bd_valid, ++ scsi_sg_count(cmd->scsi_cmd)); ++ for (i = 0; i < cmd->bd_tbl->bd_valid; i++) ++ printk(KERN_ALERT "bnx2i err, bd[%d]: len %x\n", ++ i, cmd->bd_tbl->bd_tbl[i].\ ++ buffer_length); ++ } ++ cmd->req.sd_buffer_offset = start_bd_offset; ++ cmd->req.sd_start_bd_index = start_bd_idx; ++ } ++} ++ ++ ++/** ++ * bnx2i_split_bd - splits buffer > 64KB into 32KB chunks ++ * ++ * @cmd: iscsi cmd struct pointer ++ * @addr: base address of the buffer ++ * @sg_len: buffer length ++ * @bd_index: starting index into BD table ++ * ++ * This is not required as driver limits max buffer size of less than 64K by ++ * advertising 'max_sectors' within this limit. 5706/5708 hardware limits ++ * BD length to less than or equal to 0xFFFF ++ **/ ++static int bnx2i_split_bd(struct bnx2i_cmd *cmd, u64 addr, int sg_len, ++ int bd_index) ++{ ++ struct iscsi_bd *bd = cmd->bd_tbl->bd_tbl; ++ int frag_size, sg_frags; ++ ++ sg_frags = 0; ++ while (sg_len) { ++ if (sg_len >= BD_SPLIT_SIZE) ++ frag_size = BD_SPLIT_SIZE; ++ else ++ frag_size = sg_len; ++ bd[bd_index + sg_frags].buffer_addr_lo = (u32) addr; ++ bd[bd_index + sg_frags].buffer_addr_hi = addr >> 32; ++ bd[bd_index + sg_frags].buffer_length = frag_size; ++ bd[bd_index + sg_frags].flags = 0; ++ if ((bd_index + sg_frags) == 0) ++ bd[0].flags = ISCSI_BD_FIRST_IN_BD_CHAIN; ++ addr += (u64) frag_size; ++ sg_frags++; ++ sg_len -= frag_size; ++ } ++ return sg_frags; ++} ++ ++ ++/** ++ * bnx2i_map_single_buf - maps a single buffer and updates the BD table ++ * ++ * @hba: adapter instance ++ * @cmd: iscsi cmd struct pointer ++ * ++ */ ++static int bnx2i_map_single_buf(struct bnx2i_hba *hba, ++ struct bnx2i_cmd *cmd) ++{ ++ struct scsi_cmnd *sc = cmd->scsi_cmd; ++ struct iscsi_bd *bd = cmd->bd_tbl->bd_tbl; ++ int byte_count; ++ int bd_count; ++ u64 addr; ++ ++ byte_count = scsi_bufflen(sc); ++ sc->SCp.dma_handle = ++ pci_map_single(hba->pcidev, scsi_sglist(sc), ++ scsi_bufflen(sc), sc->sc_data_direction); ++ addr = sc->SCp.dma_handle; ++ ++ if (byte_count > MAX_BD_LENGTH) { ++ bd_count = bnx2i_split_bd(cmd, addr, byte_count, 0); ++ } else { ++ bd_count = 1; ++ bd[0].buffer_addr_lo = addr & 0xffffffff; ++ bd[0].buffer_addr_hi = addr >> 32; ++ bd[0].buffer_length = scsi_bufflen(sc); ++ bd[0].flags = ISCSI_BD_FIRST_IN_BD_CHAIN | ++ ISCSI_BD_LAST_IN_BD_CHAIN; ++ } ++ bd[bd_count - 1].flags |= ISCSI_BD_LAST_IN_BD_CHAIN; ++ ++ return bd_count; ++} ++ ++ ++/** ++ * bnx2i_map_sg - maps IO buffer and prepares the BD table ++ * ++ * @hba: adapter instance ++ * @cmd: iscsi cmd struct pointer ++ * ++ * map SG list ++ */ ++static int bnx2i_map_sg(struct bnx2i_hba *hba, struct bnx2i_cmd *cmd) ++{ ++ struct scsi_cmnd *sc = cmd->scsi_cmd; ++ struct iscsi_bd *bd = cmd->bd_tbl->bd_tbl; ++ struct scatterlist *sg; ++ int byte_count = 0; ++ int sg_frags; ++ int bd_count = 0; ++ int sg_count; ++ int sg_len; ++ u64 addr; ++ int i; ++ ++ sg = scsi_sglist(sc); ++#ifdef __VMKLNX__ ++ sg_count = scsi_sg_count(sc); ++#else ++ sg_count = pci_map_sg(hba->pcidev, sg, scsi_sg_count(sc), ++ sc->sc_data_direction); ++#endif ++ ++ for (i = 0; i < sg_count; i++) { ++ sg_len = sg_dma_len(sg); ++ addr = sg_dma_address(sg); ++ if (sg_len > MAX_BD_LENGTH) ++ sg_frags = bnx2i_split_bd(cmd, addr, sg_len, ++ bd_count); ++ else { ++ sg_frags = 1; ++ bd[bd_count].buffer_addr_lo = addr & 0xffffffff; ++ bd[bd_count].buffer_addr_hi = addr >> 32; ++ bd[bd_count].buffer_length = sg_len; ++ bd[bd_count].flags = 0; ++ if (bd_count == 0) ++ bd[bd_count].flags = ++ ISCSI_BD_FIRST_IN_BD_CHAIN; ++ } ++ byte_count += sg_len; ++ sg++; ++ bd_count += sg_frags; ++ } ++ bd[bd_count - 1].flags |= ISCSI_BD_LAST_IN_BD_CHAIN; ++ ++ BUG_ON(byte_count != scsi_bufflen(sc)); ++ return bd_count; ++} ++ ++/** ++ * bnx2i_iscsi_map_sg_list - maps SG list ++ * ++ * @cmd: iscsi cmd struct pointer ++ * ++ * creates BD list table for the command ++ */ ++static void bnx2i_iscsi_map_sg_list(struct bnx2i_hba *hba, struct bnx2i_cmd *cmd) ++{ ++ struct scsi_cmnd *sc = cmd->scsi_cmd; ++ int bd_count; ++ ++ if (scsi_sg_count(sc)) ++ bd_count = bnx2i_map_sg(hba, cmd); ++ else if (scsi_bufflen(sc)) ++ bd_count = bnx2i_map_single_buf(hba, cmd); ++ else { ++ struct iscsi_bd *bd = cmd->bd_tbl->bd_tbl; ++ bd_count = 0; ++ bd[0].buffer_addr_lo = bd[0].buffer_addr_hi = 0; ++ bd[0].buffer_length = bd[0].flags = 0; ++ } ++ cmd->bd_tbl->bd_valid = bd_count; ++} ++ ++ ++/** ++ * bnx2i_iscsi_unmap_sg_list - unmaps SG list ++ * ++ * @cmd: iscsi cmd struct pointer ++ * ++ * unmap IO buffers and invalidate the BD table ++ */ ++void bnx2i_iscsi_unmap_sg_list(struct bnx2i_hba *hba, struct bnx2i_cmd *cmd) ++{ ++ struct scsi_cmnd *sc = cmd->scsi_cmd; ++#ifndef __VMKLNX__ ++ struct scatterlist *sg; ++#endif ++ ++ if (cmd->bd_tbl->bd_valid && sc) { ++#ifndef __VMKLNX__ ++ if (scsi_sg_count(sc)) { ++ sg = scsi_sglist(sc); ++ pci_unmap_sg(hba->pcidev, sg, scsi_sg_count(sc), ++ sc->sc_data_direction); ++ } else { ++ pci_unmap_single(hba->pcidev, sc->SCp.dma_handle, ++ scsi_bufflen(sc), ++ sc->sc_data_direction); ++ } ++#endif ++ cmd->bd_tbl->bd_valid = 0; ++ } ++} ++ ++ ++ ++static void bnx2i_setup_cmd_wqe_template(struct bnx2i_cmd *cmd) ++{ ++ memset(&cmd->req, 0x00, sizeof(cmd->req)); ++ cmd->req.op_code = 0xFF; ++ cmd->req.bd_list_addr_lo = (u32) cmd->bd_tbl->bd_tbl_dma; ++ cmd->req.bd_list_addr_hi = ++ (u32) ((u64) cmd->bd_tbl->bd_tbl_dma >> 32); ++ ++} ++ ++ ++/** ++ * bnx2i_bind_conn_to_iscsi_cid - bind conn structure to 'iscsi_cid' ++ * ++ * @conn: pointer to iscsi connection ++ * @iscsi_cid: iscsi context ID, range 0 - (MAX_CONN - 1) ++ * ++ * update iscsi cid table entry with connection pointer. This enables ++ * driver to quickly get hold of connection structure pointer in ++ * completion/interrupt thread using iscsi context ID ++ */ ++static int bnx2i_bind_conn_to_iscsi_cid(struct bnx2i_conn *conn, ++ u32 iscsi_cid) ++{ ++ struct bnx2i_hba *hba; ++ ++ if (!conn || !conn->sess) ++ return -EINVAL; ++ ++ hba = conn->sess->hba; ++ ++ if (hba && hba->cid_que.conn_cid_tbl[iscsi_cid]) { ++ printk(KERN_ERR "bnx2i: conn bind - entry #%d not free\n", ++ iscsi_cid); ++ return -EBUSY; ++ } ++ ++ hba->cid_que.conn_cid_tbl[iscsi_cid] = conn; ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_get_conn_from_id - maps an iscsi cid to corresponding conn ptr ++ * ++ * @hba: pointer to adapter instance ++ * @iscsi_cid: iscsi context ID, range 0 - (MAX_CONN - 1) ++ */ ++struct bnx2i_conn *bnx2i_get_conn_from_id(struct bnx2i_hba *hba, ++ u16 iscsi_cid) ++{ ++ if (!hba->cid_que.conn_cid_tbl) { ++ printk(KERN_ERR "bnx2i: ERROR - missing conn<->cid table\n"); ++ return NULL; ++ ++ } else if (iscsi_cid >= hba->max_active_conns) { ++ printk(KERN_ERR "bnx2i: wrong cid #%d\n", iscsi_cid); ++ return NULL; ++ } ++ return hba->cid_que.conn_cid_tbl[iscsi_cid]; ++} ++ ++ ++/** ++ * bnx2i_alloc_iscsi_cid - allocates a iscsi_cid from free pool ++ * ++ * @hba: pointer to adapter instance ++ */ ++static u32 bnx2i_alloc_iscsi_cid(struct bnx2i_hba *hba) ++{ ++ int idx; ++ ++ if (!hba->cid_que.cid_free_cnt) ++ return ISCSI_RESERVED_TAG; ++ ++ idx = hba->cid_que.cid_q_cons_idx; ++ hba->cid_que.cid_q_cons_idx++; ++ if (hba->cid_que.cid_q_cons_idx == hba->cid_que.cid_q_max_idx) ++ hba->cid_que.cid_q_cons_idx = 0; ++ ++ hba->cid_que.cid_free_cnt--; ++ return hba->cid_que.cid_que[idx]; ++} ++ ++ ++/** ++ * bnx2i_free_iscsi_cid - returns tcp port to free list ++ * ++ * @hba: pointer to adapter instance ++ * @iscsi_cid: iscsi context ID to free ++ */ ++static void bnx2i_free_iscsi_cid(struct bnx2i_hba *hba, u16 iscsi_cid) ++{ ++ int idx; ++ ++ if (iscsi_cid == (u16)ISCSI_RESERVED_TAG) ++ return; ++ ++ hba->cid_que.cid_free_cnt++; ++ ++ idx = hba->cid_que.cid_q_prod_idx; ++ hba->cid_que.cid_que[idx] = iscsi_cid; ++ hba->cid_que.conn_cid_tbl[iscsi_cid] = NULL; ++ hba->cid_que.cid_q_prod_idx++; ++ if (hba->cid_que.cid_q_prod_idx == hba->cid_que.cid_q_max_idx) ++ hba->cid_que.cid_q_prod_idx = 0; ++} ++ ++ ++/** ++ * bnx2i_setup_free_cid_que - sets up free iscsi cid queue ++ * ++ * @hba: pointer to adapter instance ++ * ++ * allocates memory for iscsi cid queue & 'cid - conn ptr' mapping table, ++ * and initialize table attributes ++ */ ++static int bnx2i_setup_free_cid_que(struct bnx2i_hba *hba) ++{ ++ int mem_size; ++ int i; ++ ++ mem_size = hba->max_active_conns * sizeof(u32); ++ mem_size = (mem_size + (PAGE_SIZE - 1)) & PAGE_MASK; ++ ++ hba->cid_que.cid_que_base = kmalloc(mem_size, GFP_KERNEL); ++ if (!hba->cid_que.cid_que_base) ++ return -ENOMEM; ++ ++ mem_size = hba->max_active_conns * sizeof(struct bnx2i_conn *); ++ mem_size = (mem_size + (PAGE_SIZE - 1)) & PAGE_MASK; ++ hba->cid_que.conn_cid_tbl = kmalloc(mem_size, GFP_KERNEL); ++ if (!hba->cid_que.conn_cid_tbl) { ++ kfree(hba->cid_que.cid_que_base); ++ hba->cid_que.cid_que_base = NULL; ++ return -ENOMEM; ++ } ++ ++ hba->cid_que.cid_que = (u32 *)hba->cid_que.cid_que_base; ++ hba->cid_que.cid_q_prod_idx = 0; ++ hba->cid_que.cid_q_cons_idx = 0; ++ hba->cid_que.cid_q_max_idx = hba->max_active_conns; ++ hba->cid_que.cid_free_cnt = hba->max_active_conns; ++ ++ for (i = 0; i < hba->max_active_conns; i++) { ++ hba->cid_que.cid_que[i] = i; ++ hba->cid_que.conn_cid_tbl[i] = NULL; ++ } ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_release_free_cid_que - releases 'iscsi_cid' queue resources ++ * ++ * @hba: pointer to adapter instance ++ */ ++static void bnx2i_release_free_cid_que(struct bnx2i_hba *hba) ++{ ++ kfree(hba->cid_que.cid_que_base); ++ hba->cid_que.cid_que_base = NULL; ++ ++ kfree(hba->cid_que.conn_cid_tbl); ++ hba->cid_que.conn_cid_tbl = NULL; ++} ++ ++static void bnx2i_setup_bd_tbl(struct bnx2i_hba *hba, struct bnx2i_dma *dma) ++{ ++ struct iscsi_bd *mp_bdt; ++ int pages = dma->size / PAGE_SIZE; ++ u64 addr; ++ ++ mp_bdt = (struct iscsi_bd *) dma->pgtbl; ++ addr = (unsigned long) dma->mem; ++ mp_bdt->flags = ISCSI_BD_FIRST_IN_BD_CHAIN; ++ do { ++ mp_bdt->buffer_addr_lo = addr & 0xffffffff; ++ mp_bdt->buffer_addr_hi = addr >> 32; ++ mp_bdt->buffer_length = PAGE_SIZE; ++ ++ pages--; ++ if (!pages) ++ break; ++ ++ addr += PAGE_SIZE; ++ mp_bdt++; ++ mp_bdt->flags = 0; ++ } while (1); ++ mp_bdt->flags |= ISCSI_BD_LAST_IN_BD_CHAIN; ++} ++ ++ ++/** ++ * bnx2i_setup_570x_pgtbl - iscsi QP page table setup function ++ * ++ * @ep: endpoint (transport indentifier) structure ++ * ++ * Sets up page tables for SQ/RQ/CQ, 1G/sec (5706/5708/5709) devices requires ++ * 64-bit address in big endian format. Whereas 10G/sec (57710) requires ++ * PT in little endian format ++ */ ++void bnx2i_setup_570x_pgtbl(struct bnx2i_hba *hba, struct bnx2i_dma *dma, int pgtbl_off) ++{ ++ int num_pages; ++ u32 *ptbl; ++ dma_addr_t page; ++ char *pgtbl_virt; ++ ++ /* SQ page table */ ++ pgtbl_virt = dma->pgtbl; ++ memset(pgtbl_virt, 0, dma->pgtbl_size); ++ num_pages = dma->size / PAGE_SIZE; ++ page = dma->mapping; ++ ++ ptbl = (u32 *) ((u8 *) dma->pgtbl + pgtbl_off); ++ while (num_pages--) { ++ /* PTE is written in big endian format for ++ * 5706/5708/5709 devices */ ++ *ptbl = (u32) ((u64) page >> 32); ++ ptbl++; ++ *ptbl = (u32) page; ++ ptbl++; ++ page += PAGE_SIZE; ++ } ++} ++ ++/** ++ * bnx2i_setup_5771x_pgtbl - iscsi QP page table setup function ++ * ++ * @ep: endpoint (transport indentifier) structure ++ * ++ * Sets up page tables for SQ/RQ/CQ, 1G/sec (5706/5708/5709) devices requires ++ * 64-bit address in big endian format. Whereas 10G/sec (57710) requires ++ * PT in little endian format ++ */ ++void bnx2i_setup_5771x_pgtbl(struct bnx2i_hba *hba, struct bnx2i_dma *dma, int pgtbl_off) ++{ ++ int num_pages; ++ u32 *ptbl; ++ dma_addr_t page; ++ char *pgtbl_virt; ++ ++ /* SQ page table */ ++ pgtbl_virt = dma->pgtbl; ++ memset(pgtbl_virt, 0, dma->pgtbl_size); ++ num_pages = dma->size / PAGE_SIZE; ++ page = dma->mapping; ++ ++ ptbl = (u32 *) ((u8 *) dma->pgtbl + pgtbl_off); ++ while (num_pages--) { ++ /* PTE is written in little endian format for 57710 */ ++ *ptbl = (u32) page; ++ ptbl++; ++ *ptbl = (u32) ((u64) page >> 32); ++ ptbl++; ++ page += PAGE_SIZE; ++ } ++} ++ ++ ++void bnx2i_free_dma(struct bnx2i_hba *hba, struct bnx2i_dma *dma) ++{ ++ if (dma->mem) { ++ pci_free_consistent(hba->pcidev, dma->size, dma->mem, dma->mapping); ++ dma->mem = NULL; ++ } ++ if (dma->pgtbl && dma->pgtbl_type) { ++ pci_free_consistent(hba->pcidev, dma->pgtbl_size, ++ dma->pgtbl, dma->pgtbl_map); ++ dma->pgtbl = NULL; ++ } ++} ++ ++ ++int bnx2i_alloc_dma(struct bnx2i_hba *hba, struct bnx2i_dma *dma, ++ int size, int pgtbl_type, int pgtbl_off) ++{ ++ int pages = (size + PAGE_SIZE - 1) / PAGE_SIZE; ++ ++ dma->size = size; ++ dma->pgtbl_type = pgtbl_type; ++ ++ dma->mem = pci_alloc_consistent(hba->pcidev, size, &dma->mapping); ++ if (dma->mem == NULL) ++ goto mem_err; ++ ++ if (!pgtbl_type) ++ return 0; ++ ++ dma->pgtbl_size = ((pages * 8) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1); ++ dma->pgtbl = pci_alloc_consistent(hba->pcidev, dma->pgtbl_size, ++ &dma->pgtbl_map); ++ if (dma->pgtbl == NULL) ++ goto mem_err; ++ ++ if (pgtbl_type == BNX2I_TBL_TYPE_PG) ++ hba->setup_pgtbl(hba, dma, pgtbl_off); ++ if (pgtbl_type == BNX2I_TBL_TYPE_BD) ++ bnx2i_setup_bd_tbl(hba, dma); ++ ++ return 0; ++ ++mem_err: ++ bnx2i_free_dma(hba, dma); ++ return -ENOMEM; ++} ++ ++ ++ ++/** ++ * bnx2i_alloc_ep - allocates ep structure from global pool ++ * ++ * @hba: pointer to adapter instance ++ * ++ * routine allocates a free endpoint structure from global pool and ++ * a tcp port to be used for this connection. Global resource lock, ++ * 'bnx2i_resc_lock' is held while accessing shared global data structures ++ */ ++static struct bnx2i_endpoint *bnx2i_alloc_ep(struct bnx2i_hba *hba) ++{ ++ struct bnx2i_endpoint *endpoint; ++ struct list_head *listp; ++ u16 tcp_port; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&bnx2i_resc_lock, flags); ++ ++#ifdef __VMKLNX__ ++ tcp_port = 0; ++#else ++ tcp_port = bnx2i_alloc_tcp_port(); ++ if (!tcp_port) { ++ printk(KERN_ERR "bnx2i: unable to allocate tcp ports, " ++ "make sure 'bnx2id' is running\n"); ++ spin_unlock_irqrestore(&bnx2i_resc_lock, flags); ++ return NULL; ++ } ++#endif ++ if (list_empty(&bnx2i_free_ep_list)) { ++ spin_unlock_irqrestore(&bnx2i_resc_lock, flags); ++ printk(KERN_ERR "bnx2i: ep struct pool empty\n"); ++ return NULL; ++ } ++ listp = (struct list_head *) bnx2i_free_ep_list.next; ++ list_del_init(listp); ++ bnx2i_num_free_ep--; ++ ++ endpoint = (struct bnx2i_endpoint *) listp; ++ endpoint->state = EP_STATE_IDLE; ++ endpoint->hba = hba; ++ endpoint->hba_age = hba->age; ++ hba->ofld_conns_active++; ++ endpoint->tcp_port = tcp_port; ++ init_waitqueue_head(&endpoint->ofld_wait); ++ ++ spin_unlock_irqrestore(&bnx2i_resc_lock, flags); ++ return endpoint; ++} ++ ++ ++/** ++ * bnx2i_free_ep - returns endpoint struct and tcp port to free pool ++ * ++ * @endpoint: pointer to endpoint structure ++ * ++ */ ++static void bnx2i_free_ep(struct bnx2i_endpoint *endpoint) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&bnx2i_resc_lock, flags); ++ endpoint->state = EP_STATE_IDLE; ++ endpoint->hba->ofld_conns_active--; ++ ++ bnx2i_free_iscsi_cid(endpoint->hba, endpoint->ep_iscsi_cid); ++ if (endpoint->conn) { ++ endpoint->conn->ep = NULL; ++ endpoint->conn = NULL; ++ } ++ endpoint->sess = NULL; ++ ++ if (endpoint->tcp_port) ++ bnx2i_free_tcp_port(endpoint->tcp_port); ++ ++ endpoint->hba = NULL; ++ list_add_tail(&endpoint->link, &bnx2i_free_ep_list); ++ bnx2i_num_free_ep++; ++ spin_unlock_irqrestore(&bnx2i_resc_lock, flags); ++} ++ ++ ++/** ++ * bnx2i_alloc_ep_pool - alloccates a pool of endpoint structures ++ * ++ * allocates free pool of endpoint structures, which is used to store ++ * QP related control & PT info and other option-2 information ++ */ ++int bnx2i_alloc_ep_pool(void) ++{ ++ struct bnx2i_endpoint *endpoint; ++ int index; ++ int ret_val = 0; ++ int total_endpoints; ++ int page_count = 0; ++ void *mem_ptr; ++ int mem_size; ++ ++ spin_lock_init(&bnx2i_resc_lock); ++ INIT_LIST_HEAD(&bnx2i_free_ep_list); ++ INIT_LIST_HEAD(&bnx2i_unbound_ep); ++ ++ for (index = 0; index < MAX_PAGES_PER_CTRL_STRUCT_POOL; index++) { ++ bnx2i_ep_pages[index] = NULL; ++ } ++ ++ total_endpoints = ISCSI_MAX_CONNS_PER_HBA * ISCSI_MAX_ADAPTERS; ++ bnx2i_num_free_ep = 0; ++ mem_size = total_endpoints * sizeof(struct bnx2i_endpoint); ++ mem_ptr = vmalloc(mem_size); ++ if (!mem_ptr) { ++ printk(KERN_ERR "ep_pool: mem alloc failed\n"); ++ goto mem_alloc_err; ++ } ++ memset(mem_ptr, 0, mem_size); ++ ++ bnx2i_ep_pages[page_count++] = mem_ptr; ++ endpoint = mem_ptr; ++ ++ for (index = 0; index < total_endpoints; index++) { ++ INIT_LIST_HEAD(&endpoint->link); ++ list_add_tail(&endpoint->link, &bnx2i_free_ep_list); ++ endpoint++; ++ bnx2i_num_free_ep++; ++ } ++mem_alloc_err: ++ if (bnx2i_num_free_ep == 0) ++ ret_val = -ENOMEM; ++ ++ bnx2i_max_free_ep = bnx2i_num_free_ep; ++ return ret_val; ++} ++ ++ ++/** ++ * bnx2i_release_ep_pool - releases memory resources held by endpoint structs ++ */ ++void bnx2i_release_ep_pool(void) ++{ ++ int index; ++ void *mem_ptr; ++ ++ for (index = 0; index < MAX_PAGES_PER_CTRL_STRUCT_POOL; index++) { ++ mem_ptr = bnx2i_ep_pages[index]; ++ vfree(mem_ptr); ++ bnx2i_ep_pages[index] = NULL; ++ } ++ bnx2i_num_free_ep = 0; ++ return; ++} ++ ++/** ++ * bnx2i_alloc_cmd - allocates a command structure from free pool ++ * ++ * @sess: iscsi session pointer ++ * ++ * allocates a command structures and ITT from free pool ++ */ ++struct bnx2i_cmd *bnx2i_alloc_cmd(struct bnx2i_sess *sess) ++{ ++ struct bnx2i_cmd *cmd; ++ struct list_head *listp; ++ ++ if (unlikely(!sess || (sess->num_free_cmds == 0))) { ++ return NULL; ++ } ++ ++ if (list_empty(&sess->free_cmds) && sess->num_free_cmds) { ++ /* this is wrong */ ++ printk("%s: WaTcH - num_free %d\n", __FUNCTION__, sess->num_free_cmds); ++ return NULL; ++ } ++ ++ listp = (struct list_head *) sess->free_cmds.next; ++ list_del_init(listp); ++ sess->num_free_cmds--; ++ cmd = (struct bnx2i_cmd *) listp; ++ cmd->scsi_status_rcvd = 0; ++ ++ INIT_LIST_HEAD(&cmd->link); ++ bnx2i_setup_cmd_wqe_template(cmd); ++ ++ cmd->req.itt = cmd->itt; ++ ++ return cmd; ++} ++ ++ ++/** ++ * bnx2i_free_cmd - releases iscsi cmd struct & ITT to respective free pool ++ * ++ * @sess: iscsi session pointer ++ * @cmd: iscsi cmd pointer ++ * ++ * return command structure and ITT back to free pool. ++ */ ++void bnx2i_free_cmd(struct bnx2i_sess *sess, struct bnx2i_cmd *cmd) ++{ ++ if (atomic_read(&cmd->cmd_state) == ISCSI_CMD_STATE_FREED) { ++ printk(KERN_ALERT "bnx2i: double freeing cmd %p\n", cmd); ++ return; ++ } ++ list_del_init(&cmd->link); ++ list_add_tail(&cmd->link, &sess->free_cmds); ++ sess->num_free_cmds++; ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_FREED); ++} ++ ++ ++/** ++ * bnx2i_alloc_cmd_pool - allocates and initializes iscsi command pool ++ * ++ * @sess: iscsi session pointer ++ * ++ * Allocate command structure pool for a given iSCSI session. Return 'ENOMEM' ++ * if memory allocation fails ++ */ ++int bnx2i_alloc_cmd_pool(struct bnx2i_sess *sess) ++{ ++ struct bnx2i_cmd *cmdp; ++ int index, count; ++ int ret_val = 0; ++ int total_cmds; ++ int num_cmds; ++ int page_count; ++ int num_cmds_per_page; ++ void *mem_ptr; ++ u32 mem_size; ++ int cmd_i; ++ ++ INIT_LIST_HEAD(&sess->free_cmds); ++ for (index = 0; index < MAX_PAGES_PER_CTRL_STRUCT_POOL; index++) ++ sess->cmd_pages[index] = NULL; ++ ++ num_cmds_per_page = PAGE_SIZE / sizeof(struct bnx2i_cmd); ++ ++ total_cmds = sess->sq_size; ++ mem_size = sess->sq_size * sizeof(struct bnx2i_cmd *); ++ mem_size = (mem_size + (PAGE_SIZE - 1)) & PAGE_MASK; ++ sess->itt_cmd = kmalloc(mem_size, GFP_KERNEL); ++ if (!sess->itt_cmd) ++ return -ENOMEM; ++ ++ memset(sess->itt_cmd, 0x00, mem_size); ++ ++ cmd_i = 0; ++ page_count = 0; ++ for (index = 0; index < total_cmds;) { ++ mem_ptr = kmalloc(PAGE_SIZE, GFP_KERNEL); ++ if (mem_ptr == NULL) ++ break; ++ ++ sess->cmd_pages[page_count++] = mem_ptr; ++ num_cmds = num_cmds_per_page; ++ if ((total_cmds - index) < num_cmds_per_page) ++ num_cmds = (total_cmds - index); ++ ++ memset(mem_ptr, 0, PAGE_SIZE); ++ cmdp = mem_ptr; ++ for (count = 0; count < num_cmds; count++) { ++ cmdp->req.itt = ITT_INVALID_SIGNATURE; ++ INIT_LIST_HEAD(&cmdp->link); ++ cmdp->itt = cmd_i; ++ sess->itt_cmd[cmd_i] = cmdp; ++ cmd_i++; ++ ++ /* Allocate BD table */ ++ cmdp->bd_tbl = bnx2i_alloc_bd_table(sess, cmdp); ++ if (!cmdp->bd_tbl) { ++ /* should never fail, as it's guaranteed to have ++ * (ISCSI_MAX_CMDS_PER_SESS + 1) BD tables ++ * allocated before calling this function. ++ */ ++ printk(KERN_ERR "no BD table cmd %p\n", cmdp); ++ goto bd_table_failed; ++ } ++ list_add_tail(&cmdp->link, &sess->free_cmds); ++ cmdp++; ++ } ++ ++ sess->num_free_cmds += num_cmds; ++ index += num_cmds; ++ } ++ sess->allocated_cmds = sess->num_free_cmds; ++ ++ if (sess->num_free_cmds == 0) ++ ret_val = -ENOMEM; ++ return ret_val; ++ ++bd_table_failed: ++ return -ENOMEM; ++} ++ ++ ++/** ++ * bnx2i_free_cmd_pool - releases memory held by free iscsi cmd pool ++ * ++ * @sess: iscsi session pointer ++ * ++ * Release memory held by command struct pool. ++ */ ++void bnx2i_free_cmd_pool(struct bnx2i_sess *sess) ++{ ++ int index; ++ void *mem_ptr; ++ ++ if (sess->num_free_cmds != sess->allocated_cmds) { ++ /* ++ * WARN: either there is some command struct leak or ++ * still some SCSI commands are pending. ++ */ ++ printk(KERN_ERR "bnx2i: missing cmd structs - %d, %d\n", ++ sess->num_free_cmds, sess->allocated_cmds); ++ } ++ for (index = 0; index < MAX_PAGES_PER_CTRL_STRUCT_POOL; index++) { ++ mem_ptr = sess->cmd_pages[index]; ++ kfree(mem_ptr); ++ sess->cmd_pages[index] = NULL; ++ } ++ sess->num_free_cmds = sess->allocated_cmds = 0; ++ ++ kfree(sess->itt_cmd); ++ sess->itt_cmd = NULL; ++ ++ return; ++} ++ ++static struct bnx2i_scsi_task *bnx2i_alloc_scsi_task(struct bnx2i_sess *sess) ++{ ++ struct list_head *listp; ++ if (list_empty(&sess->scsi_task_list)) { ++ return NULL; ++ } ++ listp = (struct list_head *) sess->scsi_task_list.next; ++ list_del_init(listp); ++ return (struct bnx2i_scsi_task *)listp; ++} ++ ++static void bnx2i_free_scsi_task(struct bnx2i_sess *sess, ++ struct bnx2i_scsi_task *scsi_task) ++{ ++ list_del_init((struct list_head *)scsi_task); ++ scsi_task->scsi_cmd = NULL; ++ list_add_tail(&scsi_task->link, &sess->scsi_task_list); ++} ++ ++static int bnx2i_alloc_scsi_task_pool(struct bnx2i_sess *sess) ++{ ++ struct bnx2i_scsi_task *scsi_task; ++ int mem_size = 2 * PAGE_SIZE; ++ int task_count; ++ int i; ++ ++ INIT_LIST_HEAD(&sess->scsi_task_list); ++ sess->task_list_mem = kmalloc(mem_size, GFP_KERNEL); ++ if (!sess->task_list_mem) ++ return -ENOMEM; ++ ++ scsi_task = (struct bnx2i_scsi_task *)sess->task_list_mem; ++ task_count = mem_size / sizeof(struct bnx2i_scsi_task); ++ for (i = 0; i < task_count; i++, scsi_task++) { ++ INIT_LIST_HEAD(&scsi_task->link); ++ scsi_task->scsi_cmd = NULL; ++ list_add_tail(&scsi_task->link, &sess->scsi_task_list); ++ } ++ return 0; ++} ++ ++static void bnx2i_free_scsi_task_pool(struct bnx2i_sess *sess) ++{ ++ kfree(sess->task_list_mem); ++ sess->task_list_mem = NULL; ++ INIT_LIST_HEAD(&sess->scsi_task_list); ++/*TODO - clear pend list too */ ++} ++ ++/** ++ * bnx2i_alloc_bd_table - Alloc BD table to associate with this iscsi cmd ++ * ++ * @sess: iscsi session pointer ++ * @cmd: iscsi cmd pointer ++ * ++ * allocates a BD table and assigns it to given command structure. There is ++ * no synchronization issue as this code is executed in initialization ++ * thread ++ */ ++static struct io_bdt *bnx2i_alloc_bd_table(struct bnx2i_sess *sess, ++ struct bnx2i_cmd *cmd) ++{ ++ struct io_bdt *bd_tbl; ++ ++ if (list_empty(&sess->bd_tbl_list)) ++ return NULL; ++ ++ bd_tbl = (struct io_bdt *)sess->bd_tbl_list.next; ++ list_del(&bd_tbl->link); ++ list_add_tail(&bd_tbl->link, &sess->bd_tbl_active); ++ bd_tbl->bd_valid = 0; ++ bd_tbl->cmdp = cmd; ++ ++ return bd_tbl; ++} ++ ++ ++/** ++ * bnx2i_free_all_bdt_resc_pages - releases memory held by BD memory tracker tbl ++ * ++ * @sess: iscsi session pointer ++ * ++ * Free up memory pages allocated held by BD resources ++ */ ++static void bnx2i_free_all_bdt_resc_pages(struct bnx2i_sess *sess) ++{ ++ int i; ++ struct bd_resc_page *resc_page; ++ ++ spin_lock_bh(&sess->lock); ++ while (!list_empty(&sess->bd_resc_page)) { ++ resc_page = (struct bd_resc_page *)sess->bd_resc_page.prev; ++ list_del(sess->bd_resc_page.prev); ++ for(i = 0; i < resc_page->num_valid; i++) ++ kfree(resc_page->page[i]); ++ kfree(resc_page); ++ } ++ spin_unlock_bh(&sess->lock); ++} ++ ++ ++ ++/** ++ * bnx2i_alloc_bdt_resc_page - allocated a page to track BD table memory ++ * ++ * @sess: iscsi session pointer ++ * ++ * allocated a page to track BD table memory ++ */ ++struct bd_resc_page *bnx2i_alloc_bdt_resc_page(struct bnx2i_sess *sess) ++{ ++ void *mem_ptr; ++ struct bd_resc_page *resc_page; ++ ++ mem_ptr = kmalloc(PAGE_SIZE, GFP_KERNEL); ++ if (!mem_ptr) ++ return NULL; ++ ++ resc_page = mem_ptr; ++ list_add_tail(&resc_page->link, &sess->bd_resc_page); ++ resc_page->max_ptrs = (PAGE_SIZE - ++ (u32) &((struct bd_resc_page *) 0)->page[0]) / sizeof(void *); ++ resc_page->num_valid = 0; ++ ++ return resc_page; ++} ++ ++ ++/** ++ * bnx2i_add_bdt_resc_page - add newly allocated memory page to list ++ * ++ * @sess: iscsi session pointer ++ * @bd_page: pointer to page memory ++ * ++ * link newly allocated memory page to tracker list ++ */ ++int bnx2i_add_bdt_resc_page(struct bnx2i_sess *sess, void *bd_page) ++{ ++ struct bd_resc_page *resc_page; ++ ++#define is_resc_page_full(_resc_pg) (_resc_pg->num_valid == _resc_pg->max_ptrs) ++#define active_resc_page(_resc_list) \ ++ (list_empty(_resc_list) ? NULL : (_resc_list)->prev) ++ if (list_empty(&sess->bd_resc_page)) { ++ resc_page = bnx2i_alloc_bdt_resc_page(sess); ++ } else { ++ resc_page = (struct bd_resc_page *) ++ active_resc_page(&sess->bd_resc_page); ++ } ++ ++ if (!resc_page) ++ return -ENOMEM; ++ ++ resc_page->page[resc_page->num_valid++] = bd_page; ++ if (is_resc_page_full(resc_page)) { ++ resc_page = bnx2i_alloc_bdt_resc_page(sess); ++ } ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_alloc_bd_table_pool - Allocates buffer descriptor (BD) pool ++ * ++ * @sess: iscsi session pointer ++ * ++ * Allocate a pool of buffer descriptor tables and associated DMA'able memory ++ * to be used with the session. ++ */ ++static int bnx2i_alloc_bd_table_pool(struct bnx2i_sess *sess) ++{ ++ int index, count; ++ int ret_val = 0; ++ int num_elem_per_page; ++ int num_pages; ++ struct io_bdt *bdt_info; ++ void *mem_ptr; ++ int bd_tbl_size; ++ u32 mem_size; ++ int total_bd_tbl; ++ struct bnx2i_dma *dma; ++ ++ INIT_LIST_HEAD(&sess->bd_resc_page); ++ INIT_LIST_HEAD(&sess->bd_tbl_list); ++ INIT_LIST_HEAD(&sess->bd_tbl_active); ++ ++ total_bd_tbl = sess->sq_size; ++ mem_size = total_bd_tbl * sizeof(struct io_bdt); ++ num_elem_per_page = PAGE_SIZE / sizeof(struct io_bdt); ++ ++ for (index = 0; index < total_bd_tbl; index += num_elem_per_page) { ++ if (((total_bd_tbl - index) * sizeof(struct io_bdt)) ++ >= PAGE_SIZE) { ++ mem_size = PAGE_SIZE; ++ num_elem_per_page = PAGE_SIZE / sizeof(struct io_bdt); ++ } else { ++ mem_size = ++ (total_bd_tbl - index) * sizeof(struct io_bdt); ++ num_elem_per_page = (total_bd_tbl - index); ++ } ++ mem_ptr = kmalloc(mem_size, GFP_KERNEL); ++ if (mem_ptr == NULL) { ++ printk(KERN_ERR "alloc_bd_tbl: mem alloc failed\n"); ++ ret_val = -ENOMEM; ++ goto resc_alloc_failed; ++ } ++ bnx2i_add_bdt_resc_page(sess, mem_ptr); ++ ++ memset(mem_ptr, 0, mem_size); ++ bdt_info = mem_ptr; ++ for (count = 0; count < num_elem_per_page; count++) { ++ INIT_LIST_HEAD(&bdt_info->link); ++ list_add_tail(&bdt_info->link, &sess->bd_tbl_list); ++ bdt_info++; ++ } ++ } ++ ++ ++ INIT_LIST_HEAD(&sess->bdt_dma_resc); ++ ++ bd_tbl_size = ISCSI_MAX_BDS_PER_CMD * sizeof(struct iscsi_bd); ++ bdt_info = (struct io_bdt *)sess->bd_tbl_list.next; ++ num_elem_per_page = PAGE_SIZE / bd_tbl_size; ++ ++ num_pages = ((sess->sq_size * bd_tbl_size) + PAGE_SIZE - 1) & ++ ~(PAGE_SIZE - 1); ++ num_pages /= PAGE_SIZE; ++ sess->bdt_dma_info = kmalloc(sizeof(*dma) * num_pages, GFP_KERNEL); ++ if (sess->bdt_dma_info == NULL) ++ goto resc_alloc_failed; ++ ++ memset(sess->bdt_dma_info, 0, num_pages * sizeof(*dma)); ++ dma = (struct bnx2i_dma *)sess->bdt_dma_info; ++ while (bdt_info && (bdt_info != (struct io_bdt *)&sess->bd_tbl_list)) { ++ if (bnx2i_alloc_dma(sess->hba, dma, PAGE_SIZE, 0, 0)) { ++ printk(KERN_ERR "bd_tbl: DMA mem alloc failed\n"); ++ ret_val = -ENOMEM; ++ goto dma_alloc_failed; ++ } ++ list_add_tail(&dma->link, &sess->bdt_dma_resc); ++ ++ for (count = 0; count < num_elem_per_page; count++) { ++ bdt_info->bd_tbl = (struct iscsi_bd *)(dma->mem + ++ (count * bd_tbl_size)); ++ bdt_info->bd_tbl_dma = dma->mapping + count * bd_tbl_size; ++ bdt_info->max_bd_cnt = ISCSI_MAX_BDS_PER_CMD; ++ bdt_info->bd_valid = 0; ++ bdt_info->cmdp = NULL; ++ bdt_info = (struct io_bdt *)bdt_info->link.next; ++ if (bdt_info == (struct io_bdt *)&sess->bd_tbl_list) ++ break; ++ } ++ dma++; ++ } ++ return ret_val; ++ ++resc_alloc_failed: ++dma_alloc_failed: ++ return ret_val; ++} ++ ++ ++/** ++ * bnx2i_free_bd_table_pool - releases resources held by BD table pool ++ * ++ * @sess: iscsi session pointer ++ * ++ * releases BD table pool memory ++ */ ++void bnx2i_free_bd_table_pool(struct bnx2i_sess *sess) ++{ ++ struct list_head *list; ++ struct bnx2i_dma *dma; ++ ++ list_for_each(list, &sess->bdt_dma_resc) { ++ dma = list_entry(list, struct bnx2i_dma, link); ++ bnx2i_free_dma(sess->hba, dma); ++ } ++ ++ kfree(sess->bdt_dma_info); ++} ++ ++ ++/** ++ * bnx2i_setup_mp_bdt - allocated BD table resources to be used as ++ * the dummy buffer for '0' payload length iscsi requests ++ * ++ * @hba: pointer to adapter structure ++ * ++ * allocate memory for dummy buffer and associated BD table to be used by ++ * middle path (MP) requests ++ */ ++int bnx2i_setup_mp_bdt(struct bnx2i_hba *hba) ++{ ++ int rc = 0; ++ ++ if (bnx2i_alloc_dma(hba, &hba->mp_dma_buf, PAGE_SIZE, BNX2I_TBL_TYPE_BD, 0)) { ++ printk(KERN_ERR "unable to allocate Middle Path BDT\n"); ++ rc = -1; ++ } ++ return rc; ++} ++ ++ ++/** ++ * bnx2i_free_mp_bdt - releases ITT back to free pool ++ * ++ * @hba: pointer to adapter instance ++ * ++ * free MP dummy buffer and associated BD table ++ */ ++void bnx2i_free_mp_bdt(struct bnx2i_hba *hba) ++{ ++ bnx2i_free_dma(hba, &hba->mp_dma_buf); ++} ++ ++ ++/** ++ * bnx2i_start_iscsi_hba_shutdown - start hba shutdown by cleaning up ++ * all active sessions ++ * ++ * @hba: pointer to adapter instance ++ * ++ * interface is being brought down by the user, fail all active iSCSI sessions ++ * belonging to this adapter ++ */ ++void bnx2i_start_iscsi_hba_shutdown(struct bnx2i_hba *hba) ++{ ++ struct list_head *list; ++ struct list_head *tmp; ++ struct bnx2i_sess *sess; ++ int timeout_secs = hba->hba_shutdown_tmo; ++ unsigned long flags; ++ int lpcnt; ++ int rc; ++ ++ spin_lock_irqsave(&hba->lock, flags); ++ list_for_each_safe(list, tmp, &hba->active_sess) { ++ sess = (struct bnx2i_sess *)list; ++ spin_unlock_irqrestore(&hba->lock, flags); ++ lpcnt = 4; ++ rc = bnx2i_do_iscsi_sess_recovery(sess, DID_NO_CONNECT); ++ while ((rc != SUCCESS) && lpcnt--) { ++ msleep(1000); ++ rc = bnx2i_do_iscsi_sess_recovery(sess, DID_NO_CONNECT); ++ } ++ spin_lock_irqsave(&hba->lock, flags); ++ } ++ spin_unlock_irqrestore(&hba->lock, flags); ++ ++ wait_event_interruptible_timeout(hba->eh_wait, ++ (hba->ofld_conns_active == 0), ++ timeout_secs); ++} ++ ++ ++/** ++ * bnx2i_iscsi_handle_ip_event - inetdev callback to handle ip address change ++ * ++ * @hba: pointer to adapter instance ++ * ++ * IP address change indication, fail all iSCSI connections on this adapter ++ * and let 'iscsid' reinstate the connections ++ */ ++void bnx2i_iscsi_handle_ip_event(struct bnx2i_hba *hba) ++{ ++ struct list_head *list; ++ struct list_head *tmp; ++ struct bnx2i_sess *sess; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hba->lock, flags); ++ list_for_each_safe(list, tmp, &hba->active_sess) { ++ sess = (struct bnx2i_sess *)list; ++ spin_unlock_irqrestore(&hba->lock, flags); ++ bnx2i_do_iscsi_sess_recovery(sess, DID_RESET); ++ spin_lock_irqsave(&hba->lock, flags); ++ } ++ spin_unlock_irqrestore(&hba->lock, flags); ++} ++ ++ ++static void bnx2i_withdraw_sess_recovery(struct bnx2i_sess *sess) ++{ ++ struct bnx2i_hba *hba = sess->hba; ++ int cons_idx = hba->sess_recov_cons_idx; ++ unsigned int long flags; ++ ++ spin_lock_irqsave(&hba->lock, flags); ++ while (hba->sess_recov_prod_idx != cons_idx) { ++ if (sess == hba->sess_recov_list[cons_idx]) { ++ hba->sess_recov_list[cons_idx] = NULL; ++ break; ++ } ++ if (cons_idx == hba->sess_recov_max_idx) ++ cons_idx = 0; ++ else ++ cons_idx++; ++ } ++ spin_unlock_irqrestore(&hba->lock, flags); ++} ++ ++/** ++ * conn_err_recovery_task - does recovery on all queued sessions ++ * ++ * @work: pointer to work struct ++ * ++ * iSCSI Session recovery queue manager ++ */ ++static void ++#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) ++conn_err_recovery_task(struct work_struct *work) ++#else ++conn_err_recovery_task(void *data) ++#endif ++{ ++#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) ++ struct bnx2i_hba *hba = container_of(work, struct bnx2i_hba, ++ err_rec_task); ++#else ++ struct bnx2i_hba *hba = data; ++#endif ++ struct bnx2i_sess *sess; ++ int cons_idx = hba->sess_recov_cons_idx; ++ unsigned int long flags; ++ ++ spin_lock_irqsave(&hba->lock, flags); ++ while (hba->sess_recov_prod_idx != cons_idx) { ++ sess = hba->sess_recov_list[cons_idx]; ++ if (cons_idx == hba->sess_recov_max_idx) ++ cons_idx = 0; ++ else ++ cons_idx++; ++ spin_unlock_irqrestore(&hba->lock, flags); ++ if (sess) { ++ if (sess->state == BNX2I_SESS_IN_LOGOUT) ++ bnx2i_do_iscsi_sess_recovery(sess, DID_NO_CONNECT); ++ else ++ bnx2i_do_iscsi_sess_recovery(sess, DID_RESET); ++ } ++ spin_lock_irqsave(&hba->lock, flags); ++ } ++ hba->sess_recov_cons_idx = cons_idx; ++ spin_unlock_irqrestore(&hba->lock, flags); ++} ++ ++/** ++ * bnx2i_ep_destroy_list_add - add an entry to EP destroy list ++ * ++ * @hba: pointer to adapter instance ++ * @ep: pointer to endpoint (transport indentifier) structure ++ * ++ * EP destroy queue manager ++ */ ++static int bnx2i_ep_destroy_list_add(struct bnx2i_hba *hba, ++ struct bnx2i_endpoint *ep) ++{ ++#ifdef __VMKLNX__ ++ spin_lock(&hba->lock); ++#else ++ write_lock(&hba->ep_rdwr_lock); ++#endif ++ list_add_tail(&ep->link, &hba->ep_destroy_list); ++#ifdef __VMKLNX__ ++ spin_unlock(&hba->lock); ++#else ++ write_unlock(&hba->ep_rdwr_lock); ++#endif ++ return 0; ++} ++ ++/** ++ * bnx2i_ep_destroy_list_del - add an entry to EP destroy list ++ * ++ * @hba: pointer to adapter instance ++ * @ep: pointer to endpoint (transport indentifier) structure ++ * ++ * EP destroy queue manager ++ */ ++static int bnx2i_ep_destroy_list_del(struct bnx2i_hba *hba, ++ struct bnx2i_endpoint *ep) ++{ ++#ifdef __VMKLNX__ ++ spin_lock(&hba->lock); ++#else ++ write_lock(&hba->ep_rdwr_lock); ++#endif ++ list_del_init(&ep->link); ++#ifdef __VMKLNX__ ++ spin_unlock(&hba->lock); ++#else ++ write_unlock(&hba->ep_rdwr_lock); ++#endif ++ ++ return 0; ++} ++ ++/** ++ * bnx2i_ep_ofld_list_add - add an entry to ep offload pending list ++ * ++ * @hba: pointer to adapter instance ++ * @ep: pointer to endpoint (transport indentifier) structure ++ * ++ * pending conn offload completion queue manager ++ */ ++static int bnx2i_ep_ofld_list_add(struct bnx2i_hba *hba, ++ struct bnx2i_endpoint *ep) ++{ ++#ifdef __VMKLNX__ ++ spin_lock(&hba->lock); ++#else ++ write_lock(&hba->ep_rdwr_lock); ++#endif ++ list_add_tail(&ep->link, &hba->ep_ofld_list); ++#ifdef __VMKLNX__ ++ spin_unlock(&hba->lock); ++#else ++ write_unlock(&hba->ep_rdwr_lock); ++#endif ++ return 0; ++} ++ ++/** ++ * bnx2i_ep_ofld_list_del - add an entry to ep offload pending list ++ * ++ * @hba: pointer to adapter instance ++ * @ep: pointer to endpoint (transport indentifier) structure ++ * ++ * pending conn offload completion queue manager ++ */ ++static int bnx2i_ep_ofld_list_del(struct bnx2i_hba *hba, ++ struct bnx2i_endpoint *ep) ++{ ++#ifdef __VMKLNX__ ++ spin_lock(&hba->lock); ++#else ++ write_lock(&hba->ep_rdwr_lock); ++#endif ++ list_del_init(&ep->link); ++#ifdef __VMKLNX__ ++ spin_unlock(&hba->lock); ++#else ++ write_unlock(&hba->ep_rdwr_lock); ++#endif ++ ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_find_ep_in_ofld_list - find iscsi_cid in pending list of endpoints ++ * ++ * @hba: pointer to adapter instance ++ * @iscsi_cid: iscsi context ID to find ++ * ++ */ ++struct bnx2i_endpoint * ++bnx2i_find_ep_in_ofld_list(struct bnx2i_hba *hba, u32 iscsi_cid) ++{ ++ struct list_head *list; ++ struct list_head *tmp; ++ struct bnx2i_endpoint *ep; ++ ++#ifdef __VMKLNX__ ++ spin_lock(&hba->lock); ++#else ++ read_lock(&hba->ep_rdwr_lock); ++#endif ++ list_for_each_safe(list, tmp, &hba->ep_ofld_list) { ++ ep = (struct bnx2i_endpoint *)list; ++ ++ if (ep->ep_iscsi_cid == iscsi_cid) ++ break; ++ ep = NULL; ++ } ++#ifdef __VMKLNX__ ++ spin_unlock(&hba->lock); ++#else ++ read_unlock(&hba->ep_rdwr_lock); ++#endif ++ ++ if (!ep) ++ printk("bnx2i: ofld_list - icid %d not found\n", iscsi_cid); ++ return ep; ++} ++ ++ ++/** ++ * bnx2i_find_ep_in_destroy_list - find iscsi_cid in destroy list ++ * ++ * @hba: pointer to adapter instance ++ * @iscsi_cid: iscsi context ID to find ++ * ++ */ ++struct bnx2i_endpoint * ++bnx2i_find_ep_in_destroy_list(struct bnx2i_hba *hba, u32 iscsi_cid) ++{ ++ struct list_head *list; ++ struct list_head *tmp; ++ struct bnx2i_endpoint *ep; ++ ++#ifdef __VMKLNX__ ++ spin_lock(&hba->lock); ++#else ++ read_lock(&hba->ep_rdwr_lock); ++#endif ++ list_for_each_safe(list, tmp, &hba->ep_destroy_list) { ++ ep = (struct bnx2i_endpoint *)list; ++ ++ if (ep->ep_iscsi_cid == iscsi_cid) ++ break; ++ ep = NULL; ++ } ++#ifdef __VMKLNX__ ++ spin_unlock(&hba->lock); ++#else ++ read_unlock(&hba->ep_rdwr_lock); ++#endif ++ ++ if (!ep) ++ printk("bnx2i: destroy_list - icid %d not found\n", iscsi_cid); ++ ++ return ep; ++} ++ ++ ++#ifdef __VMKLNX__ ++struct Scsi_Host *bnx2i_alloc_shost(int priv_sz) ++{ ++ struct Scsi_Host *shost; ++ ++ shost = scsi_host_alloc(&bnx2i_host_template, priv_sz); ++ if (!shost) ++ return NULL; ++ ++ /* Vmware suggested values */ ++ shost->max_id = 256; ++ shost->max_channel = 64; ++ shost->max_lun = bnx2i_iscsi_transport.max_lun; ++ ++ return shost; ++} ++#endif ++ ++ ++/** ++ * bnx2i_alloc_hba - allocate and init adapter instance ++ * ++ * @cnic: cnic device pointer ++ * ++ * allocate & initialize adapter structure and call other ++ * support routines to do per adapter initialization ++ */ ++struct bnx2i_hba *bnx2i_alloc_hba(struct cnic_dev *cnic) ++{ ++ struct bnx2i_hba *hba; ++ struct scsi_host_template *scsi_template; ++ struct iscsi_transport *iscsi_transport; ++ ++#ifdef __VMKLNX__ ++ struct Scsi_Host *shost; ++ shost = bnx2i_alloc_shost(hostdata_privsize(sizeof(*hba))); ++ if (!shost) ++ return NULL; ++ hba = shost_priv(shost); ++ hba->shost = shost; ++#else ++ hba = kmalloc(sizeof(struct bnx2i_hba), GFP_KERNEL); ++ if (!hba) ++ return NULL; ++ ++ memset(hba, 0, sizeof(struct bnx2i_hba)); ++#endif ++ /* Get PCI related information and update hba struct members */ ++ hba->cnic = cnic; ++ hba->netdev = cnic->netdev; ++ ++ INIT_LIST_HEAD(&hba->active_sess); ++ INIT_LIST_HEAD(&hba->ep_ofld_list); ++ INIT_LIST_HEAD(&hba->ep_destroy_list); ++#ifndef __VMKLNX__ ++ rwlock_init(&hba->ep_rdwr_lock); ++#endif ++ ++ hba->mtu_supported = BNX2I_MAX_MTU_SUPPORTED; ++ ++ hba->max_active_conns = ISCSI_MAX_CONNS_PER_HBA; ++ ++ /* Get device type required to determine default SQ size */ ++ if (cnic->pcidev) { ++ hba->pci_did = cnic->pcidev->device; ++ bnx2i_identify_device(hba); ++ } ++ ++ /* SQ/RQ/CQ size can be changed via sysfs interface */ ++ if (test_bit(BNX2I_NX2_DEV_57710, &hba->cnic_dev_type)) { ++ hba->setup_pgtbl = bnx2i_setup_5771x_pgtbl; ++ if (sq_size && sq_size <= BNX2I_5770X_SQ_WQES_MAX) ++ hba->max_sqes = sq_size; ++ else ++ hba->max_sqes = BNX2I_5770X_SQ_WQES_DEFAULT; ++ ++#ifndef CONFIG_X86_64 ++ if (hba->max_sqes > BNX2I_5770X_SQ_WQES_DEFAULT_X86) ++ hba->max_sqes = BNX2I_5770X_SQ_WQES_DEFAULT_X86; ++#endif ++ } else { /* 5706/5708/5709 */ ++ hba->setup_pgtbl = bnx2i_setup_570x_pgtbl; ++ if (sq_size && sq_size <= BNX2I_570X_SQ_WQES_MAX) ++ hba->max_sqes = sq_size; ++ else { ++#ifdef __VMKLNX__ ++ if (test_bit(BNX2I_NX2_DEV_5709, &hba->cnic_dev_type)) ++ hba->max_sqes = BNX2I_5709_SQ_WQES_DEFAULT; ++ else ++ hba->max_sqes = BNX2I_570X_SQ_WQES_DEFAULT; ++#else ++ hba->max_sqes = BNX2I_570X_SQ_WQES_DEFAULT; ++#endif ++ } ++ } ++ ++ hba->max_rqes = rq_size; ++ hba->max_cqes = hba->max_sqes + rq_size; ++ hba->num_ccell = hba->max_sqes / 2; ++ ++ scsi_template = bnx2i_alloc_scsi_host_template(hba, cnic); ++ if (!scsi_template) ++ return NULL; ++ ++ iscsi_transport = bnx2i_alloc_iscsi_transport(hba, cnic, scsi_template); ++ if (!iscsi_transport) ++ goto iscsi_transport_err; ++ ++ /* Get PCI related information and update hba struct members */ ++ hba->cnic = cnic; ++ hba->netdev = cnic->netdev; ++ ++ ++ if (bnx2i_setup_free_cid_que(hba)) ++ goto cid_que_err; ++ ++ hba->scsi_template = scsi_template; ++ hba->iscsi_transport = iscsi_transport; ++ ++ spin_lock_init(&hba->lock); ++ mutex_init(&hba->net_dev_lock); ++ ++ /* initialize timer and wait queue used for resource cleanup when ++ * interface is brought down */ ++ init_timer(&hba->hba_timer); ++ init_waitqueue_head(&hba->eh_wait); ++ ++#ifdef __VMKLNX__ ++ init_timer(&hba->hba_poll_timer); ++ hba->hba_poll_timer.expires = jiffies + 2 * HZ; ++ hba->hba_poll_timer.function = bnx2i_hba_poll_timer; ++ hba->hba_poll_timer.data = (unsigned long) hba; ++ add_timer(&hba->hba_poll_timer); ++#endif ++ ++ ++#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) ++ INIT_WORK(&hba->err_rec_task, conn_err_recovery_task); ++#else ++ INIT_WORK(&hba->err_rec_task, conn_err_recovery_task, hba); ++#endif ++ hba->sess_recov_prod_idx = 0; ++ hba->sess_recov_cons_idx = 0; ++ hba->sess_recov_max_idx = 0; ++ hba->sess_recov_list = kmalloc(PAGE_SIZE, GFP_KERNEL); ++ if (!hba->sess_recov_list) ++ goto rec_que_err; ++ hba->sess_recov_max_idx = PAGE_SIZE / sizeof (struct bnx2i_sess *) - 1; ++#ifdef __VMKLNX__ ++ if (bnx2i_bind_adapter_devices(hba)) ++ goto pcidev_bind_err; ++#endif ++ ++ return hba; ++ ++#ifdef __VMKLNX__ ++pcidev_bind_err: ++#endif ++rec_que_err: ++ bnx2i_release_free_cid_que(hba); ++cid_que_err: ++ bnx2i_free_iscsi_transport(iscsi_transport); ++iscsi_transport_err: ++ bnx2i_free_scsi_host_template(scsi_template); ++#ifdef __VMKLNX__ ++ scsi_host_put(shost); ++#else ++ bnx2i_free_hba(hba); ++#endif ++ ++ return NULL; ++} ++ ++ ++/** ++ * bnx2i_free_hba- releases hba structure and resources held by the adapter ++ * ++ * @hba: pointer to adapter instance ++ * ++ * free adapter structure and call various cleanup routines. ++ */ ++void bnx2i_free_hba(struct bnx2i_hba *hba) ++{ ++ bnx2i_release_free_cid_que(hba); ++ INIT_LIST_HEAD(&hba->ep_ofld_list); ++ INIT_LIST_HEAD(&hba->ep_destroy_list); ++ ++#ifdef __VMKLNX__ ++ del_timer_sync(&hba->hba_poll_timer); ++#endif ++ ++ INIT_LIST_HEAD(&hba->active_sess); ++#ifdef __VMKLNX__ ++ bnx2i_unbind_adapter_devices(hba); ++ scsi_host_put(hba->shost); ++#else ++ kfree(hba); ++#endif ++} ++ ++ ++static int bnx2i_flush_pend_queue(struct bnx2i_sess *sess, ++ struct scsi_cmnd *sc, int reason) ++{ ++ int num_pend_cmds_returned = 0; ++ struct list_head *list; ++ struct list_head *tmp; ++ struct bnx2i_scsi_task *scsi_task; ++ ++ spin_lock_bh(&sess->lock); ++ list_for_each_safe(list, tmp, &sess->pend_cmd_list) { ++ scsi_task = (struct bnx2i_scsi_task *) list; ++ ++ /* cmd queue flush request could be due to LUN RESET or ++ * the session recovery. In former case just fail only the ++ * command belonging that particular LUN. ++ */ ++ if (sc) { ++ if (sc == scsi_task->scsi_cmd) { ++ list_del_init(&scsi_task->link); ++ scsi_task->scsi_cmd = NULL; ++ list_add_tail(&scsi_task->link, ++ &sess->scsi_task_list); ++ } else if (scsi_task->scsi_cmd->device->lun ++ != sc->device->lun) ++ continue; ++ } ++ ++ num_pend_cmds_returned++; ++ list_del_init(&scsi_task->link); ++ bnx2i_return_failed_command(sess, scsi_task->scsi_cmd, ++ scsi_bufflen(scsi_task->scsi_cmd), ++ reason); ++ scsi_task->scsi_cmd = NULL; ++ list_add_tail(&scsi_task->link, &sess->scsi_task_list); ++ } ++ sess->pend_cmd_count -= num_pend_cmds_returned; ++ spin_unlock_bh(&sess->lock); ++ return num_pend_cmds_returned; ++} ++ ++/** ++ * bnx2i_flush_cmd_queue - flush active command queue ++ * ++ * @sess: iscsi session pointer ++ * @reason: SCSI ML error code, DID_BUS_BUSY ++ * ++ * return all commands in active queue which should already have been ++ * cleaned up by the cnic device. ++ */ ++static int bnx2i_flush_cmd_queue(struct bnx2i_sess *sess, ++ struct scsi_cmnd *scsi_cmd, ++ int reason, int clear_ctx) ++{ ++ struct list_head *list; ++ struct list_head *tmp; ++ struct bnx2i_cmd *cmd; ++ unsigned long flags; ++ int cmd_diff_lun = 0; ++ struct Scsi_Host *shost; ++ struct list_head failed_cmds; ++ int total_sess_active_cmds = 0; ++ int cmd_cnt = 0; ++ ++ shost = bnx2i_sess_get_shost(sess); ++ ++ INIT_LIST_HEAD(&failed_cmds); ++ spin_lock_irqsave(&sess->lock, flags); ++ list_for_each_safe(list, tmp, &sess->active_cmd_list) { ++ cmd = (struct bnx2i_cmd *) list; ++ total_sess_active_cmds++; ++ ++ if (!cmd->scsi_cmd) { ++ printk(KERN_ALERT "bnx2i: WaTcH - cid %d, flush que," ++ " cmd %p is not associated with any" ++ " scsi cmd\n", ++ sess->lead_conn->ep->ep_iscsi_cid, ++ cmd); ++ continue; ++ } ++ /* cmd queue flush request could be due to LUN RESET or ++ * the session recovery. In former case just fail only the ++ * command belonging that particular LUN. ++ */ ++ if (scsi_cmd) { ++ if (cmd->scsi_cmd->device->lun != ++ scsi_cmd->device->lun) { ++ cmd_diff_lun++; ++ continue; ++ } ++ } ++ if (atomic_read(&cmd->cmd_state) == ISCSI_CMD_STATE_CMPL_RCVD){ ++ /* completion pdu is being processed and we will let ++ * it run to completion, fail the request here ++ */ ++ printk(KERN_ALERT "bnx2i: WaTcH - cid %d, completion & " ++ "TMF cleanup are running in parallel," ++ " cmd %p\n", ++ sess->lead_conn->ep->ep_iscsi_cid, cmd); ++ continue; ++ } ++ cmd->scsi_cmd->result = (reason << 16); ++ /* Now that bnx2i_cleanup_task_context() does not sleep waiting ++ * for completion it is safe to hold sess lock and this will ++ * avoid race between LUN/TARGET RESET TMF completion followed ++ * by command completion with check condition ++ */ ++ ++ if (clear_ctx) { ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_CLEANUP_START); ++ bnx2i_cleanup_task_context(sess, cmd, reason); ++ } else { ++ list_del_init(&cmd->link); ++ list_add_tail(&cmd->link, &failed_cmds); ++ } ++ cmd_cnt++; ++ } ++ spin_unlock_irqrestore(&sess->lock, flags); ++ ++ list_for_each_safe(list, tmp, &failed_cmds) { ++ cmd = (struct bnx2i_cmd *) list; ++ cmd->failed_reason = reason; ++ bnx2i_fail_cmd(sess, cmd); ++ } ++ return cmd_cnt; ++} ++ ++ ++/** ++ * bnx2i_session_recovery_start - start recovery process on given session ++ * ++ * @sess: iscsi session pointer ++ * @reason: SCSI ML error code, DID_BUS_BUSY ++ * ++ * initiate cleanup of outstanding commands for sess recovery ++ */ ++static int bnx2i_session_recovery_start(struct bnx2i_sess *sess, int reason) ++{ ++ if (sess->state == BNX2I_SESS_IN_LOGOUT || ++ sess->state == BNX2I_SESS_INITIAL) ++ return 0; ++ ++ if (!is_sess_active(sess) && ++ !sess->state & BNX2I_SESS_INITIAL) { ++ if (sess->recovery_state) ++ return -EPERM; ++ wait_event_interruptible_timeout(sess->er_wait, ++ (sess->state == ++ BNX2I_SESS_IN_FFP), 20 * HZ); ++ if (signal_pending(current)) ++ flush_signals(current); ++ if (!is_sess_active(sess) && ++ !sess->state & BNX2I_SESS_INITIAL) { ++ printk(KERN_ALERT "sess_reco: sess still not active\n"); ++ sess->lead_conn->state = CONN_STATE_XPORT_FREEZE; ++ return -EPERM; ++ } ++ } ++ ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_do_iscsi_sess_recovery - implements session recovery code ++ * ++ * @sess: iscsi session pointer ++ * @reason: SCSI ML error code, DID_BUS_BUSY, DID_NO_CONNECT, ++ * DID_RESET ++ * ++ * SCSI host reset handler, which is translates to iSCSI session ++ * recovery. This routine starts internal driver session recovery, ++ * indicates connection error to 'iscsid' which does session reinstatement ++ * This is an synchronous call which waits for completion and returns ++ * the ultimate result of session recovery process to caller ++ */ ++int bnx2i_do_iscsi_sess_recovery(struct bnx2i_sess *sess, int reason) ++{ ++ struct bnx2i_hba *hba; ++ struct bnx2i_conn *conn = sess->lead_conn; ++ ++ if (!conn) ++ return FAILED; ++ ++ /* block scsi host to avoid any further command queuing */ ++#ifdef __VMKLNX__ ++ iscsi_block_session(sess->cls_sess); ++#else ++ iscsi_block_session(session_to_cls(sess)); ++#endif ++ ++ if (bnx2i_session_recovery_start(sess, reason)) { ++ printk(KERN_INFO "bnx2i: sess rec start returned error\n"); ++ return FAILED; ++ } ++ hba = sess->hba; ++ ++ sess->recovery_state = ISCSI_SESS_RECOVERY_OPEN_ISCSI; ++ iscsi_conn_error(conn->cls_conn, ISCSI_ERR_CONN_FAILED); ++ ++ /* if session teardown is because of net interface down, ++ * no need to wait for complete recovery */ ++ if (reason == DID_NO_CONNECT || ++ test_bit(ADAPTER_STATE_LINK_DOWN, &sess->hba->adapter_state)) ++ wait_event_interruptible_timeout(sess->er_wait, ++ !conn->ep, ++ msecs_to_jiffies(3000)); ++ else ++ wait_event_interruptible(sess->er_wait, ++ ((sess->recovery_state & ++ ISCSI_SESS_RECOVERY_COMPLETE) || ++ (sess->recovery_state & ++ ISCSI_SESS_RECOVERY_FAILED) || ++ sess->recovery_state == 0)); ++ ++ if (signal_pending(current)) ++ flush_signals(current); ++ ++ if (reason == DID_NO_CONNECT) ++ goto ret_success; ++ ++ if (sess->recovery_state & ISCSI_SESS_RECOVERY_COMPLETE) { ++ printk(KERN_INFO "bnx2i: sess recovery %p complete\n", sess); ++ sess->state = BNX2I_SESS_IN_FFP; ++ } else ++ return FAILED; ++ ++ret_success: ++ sess->recovery_state = 0; ++ return SUCCESS; ++} ++ ++ ++/** ++ * bnx2i_iscsi_sess_release - cleanup iscsi session & reclaim all resources ++ * ++ * @hba: pointer to adapter instance ++ * @sess: iscsi session pointer ++ * ++ * free up resources held by this session including ITT queue, cmd struct pool, ++ * BD table pool. HBA lock is held while manipulating active session list ++ */ ++void bnx2i_iscsi_sess_release(struct bnx2i_hba *hba, struct bnx2i_sess *sess) ++{ ++ unsigned long flags; ++ ++ if (sess->login_nopout_cmd) { ++ /* set cmd state so that free_cmd() accepts it */ ++ atomic_set(&sess->login_nopout_cmd->cmd_state, ++ ISCSI_CMD_STATE_COMPLETED); ++ bnx2i_free_cmd(sess, sess->login_nopout_cmd); ++ } ++ if (sess->scsi_tmf_cmd) { ++ atomic_set(&sess->scsi_tmf_cmd->cmd_state, ++ ISCSI_CMD_STATE_COMPLETED); ++ bnx2i_free_cmd(sess, sess->scsi_tmf_cmd); ++ } ++ if (sess->nopout_resp_cmd) { ++ atomic_set(&sess->nopout_resp_cmd->cmd_state, ++ ISCSI_CMD_STATE_COMPLETED); ++ bnx2i_free_cmd(sess, sess->nopout_resp_cmd); ++ } ++ ++ sess->login_nopout_cmd = NULL; ++ sess->scsi_tmf_cmd = NULL; ++ sess->nopout_resp_cmd = NULL; ++ ++ bnx2i_free_bd_table_pool(sess); ++ bnx2i_free_all_bdt_resc_pages(sess); ++ bnx2i_free_cmd_pool(sess); ++ bnx2i_free_scsi_task_pool(sess); ++ ++ spin_lock_irqsave(&hba->lock, flags); ++ list_del_init(&sess->link); ++ hba->num_active_sess--; ++ spin_unlock_irqrestore(&hba->lock, flags); ++} ++ ++ ++/** ++ * bnx2i_iscsi_sess_new - initialize newly allocated session structure ++ * ++ * @hba: pointer to adapter instance ++ * @sess: iscsi session pointer ++ * ++ * initialize session structure elements and allocate per sess resources. ++ * Some of the per session resources allocated are command struct pool, ++ * BD table pool and ITT queue region ++ */ ++int bnx2i_iscsi_sess_new(struct bnx2i_hba *hba, struct bnx2i_sess *sess) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hba->lock, flags); ++ list_add_tail(&sess->link, &hba->active_sess); ++ hba->num_active_sess++; ++ spin_unlock_irqrestore(&hba->lock, flags); ++ ++ sess->sq_size = hba->max_sqes; ++ sess->tsih = 0; ++ sess->lead_conn = NULL; ++ sess->worker_time_slice = 2; ++ ++ spin_lock_init(&sess->lock); ++ mutex_init(&sess->tmf_mutex); ++ ++ /* initialize active connection list */ ++ INIT_LIST_HEAD(&sess->conn_list); ++ INIT_LIST_HEAD(&sess->free_cmds); ++ ++ INIT_LIST_HEAD(&sess->pend_cmd_list); ++ sess->pend_cmd_count = 0; ++ INIT_LIST_HEAD(&sess->active_cmd_list); ++ sess->active_cmd_count = 0; ++ ++ atomic_set(&sess->login_noop_pending, 0); ++ atomic_set(&sess->logout_pending, 0); ++ atomic_set(&sess->tmf_pending, 0); ++ ++ sess->login_nopout_cmd = NULL; ++ sess->scsi_tmf_cmd = NULL; ++ sess->nopout_resp_cmd = NULL; ++ ++ sess->num_active_conn = 0; ++ sess->max_conns = 1; ++ sess->target_name = NULL; ++ ++ sess->state = BNX2I_SESS_INITIAL; ++ sess->recovery_state = 0; ++ atomic_set(&sess->tmf_active, 0); ++ ++ if (bnx2i_alloc_bd_table_pool(sess) != 0) { ++ printk(KERN_ERR "sess_new: unable to alloc bd table pool\n"); ++ goto err_bd_pool; ++ } ++ ++ if (bnx2i_alloc_cmd_pool(sess) != 0) { ++ printk(KERN_ERR "sess_new: alloc cmd pool failed\n"); ++ goto err_cmd_pool; ++ } ++ ++ if (bnx2i_alloc_scsi_task_pool(sess) != 0) { ++ printk(KERN_ERR "sess_new: alloc scsi_task pool failed\n"); ++ goto err_sc_pool; ++ } ++ init_timer(&sess->abort_timer); ++ init_waitqueue_head(&sess->er_wait); ++ ++ return 0; ++ ++err_sc_pool: ++ bnx2i_free_cmd_pool(sess); ++err_cmd_pool: ++ bnx2i_free_bd_table_pool(sess); ++err_bd_pool: ++ return -ENOMEM; ++} ++ ++/** ++ * bnx2i_conn_free_login_resources - free DMA resources used for login process ++ * ++ * @hba: pointer to adapter instance ++ * @conn: iscsi connection pointer ++ * ++ * Login related resources, mostly BDT & payload DMA memory is freed ++ */ ++void bnx2i_conn_free_login_resources(struct bnx2i_hba *hba, ++ struct bnx2i_conn *conn) ++{ ++ bnx2i_free_dma(hba, &conn->gen_pdu.login_req); ++ bnx2i_free_dma(hba, &conn->gen_pdu.login_resp); ++} ++ ++/** ++ * bnx2i_conn_alloc_login_resources - alloc DMA resources used for ++ * login / nopout pdus ++ * ++ * @hba: pointer to adapter instance ++ * @conn: iscsi connection pointer ++ * ++ * Login & nop-in related resources is allocated in this routine. ++ */ ++static int bnx2i_conn_alloc_login_resources(struct bnx2i_hba *hba, ++ struct bnx2i_conn *conn) ++{ ++ /* Allocate memory for login request/response buffers */ ++ if (bnx2i_alloc_dma(hba, &conn->gen_pdu.login_req, ++ ISCSI_CONN_LOGIN_BUF_SIZE, BNX2I_TBL_TYPE_BD, 0)) ++ goto error; ++ ++ conn->gen_pdu.req_buf_size = 0; ++ conn->gen_pdu.req_wr_ptr = conn->gen_pdu.login_req.mem; ++ ++ if (bnx2i_alloc_dma(hba, &conn->gen_pdu.login_resp, ++ ISCSI_CONN_LOGIN_BUF_SIZE, BNX2I_TBL_TYPE_BD, 0)) ++ goto error; ++ ++ conn->gen_pdu.resp_buf_size = ISCSI_CONN_LOGIN_BUF_SIZE; ++ conn->gen_pdu.resp_wr_ptr = conn->gen_pdu.login_resp.mem; ++ ++ return 0; ++ ++error: ++ printk(KERN_ERR "bnx2i:a conn login resource alloc failed!!\n"); ++ bnx2i_conn_free_login_resources(hba, conn); ++ return -ENOMEM; ++ ++} ++ ++ ++/** ++ * bnx2i_iscsi_conn_new - initialize newly created connection structure ++ * ++ * @sess: iscsi session pointer ++ * @conn: iscsi connection pointer ++ * ++ * connection structure is initialized which mainly includes allocation of ++ * login resources and lock/time initialization ++ */ ++int bnx2i_iscsi_conn_new(struct bnx2i_sess *sess, struct bnx2i_conn *conn) ++{ ++ struct bnx2i_hba *hba = sess->hba; ++ ++ conn->sess = sess; ++ conn->header_digest_en = 0; ++ conn->data_digest_en = 0; ++ ++ INIT_LIST_HEAD(&conn->link); ++ ++ /* 'ep' ptr will be assigned in bind() call */ ++ conn->ep = NULL; ++ ++ if (test_bit(BNX2I_NX2_DEV_57710, &hba->cnic_dev_type)) ++ conn->ring_doorbell = bnx2i_ring_sq_dbell_bnx2x; ++ else ++ conn->ring_doorbell = bnx2i_ring_sq_dbell_bnx2; ++ ++ if (bnx2i_conn_alloc_login_resources(hba, conn)) { ++ printk(KERN_ALERT "conn_new: login resc alloc failed!!\n"); ++ return -ENOMEM; ++ } ++ ++ ++ atomic_set(&conn->stop_state, 0); ++ atomic_set(&conn->worker_running, 0); ++#ifdef __VMKLNX__ ++ tasklet_init(&conn->conn_tasklet, &bnx2i_conn_main_worker, ++ (unsigned long) conn); ++ atomic_set(&conn->worker_enabled, 0); ++#else ++#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) ++ INIT_WORK(&conn->conn_worker, bnx2i_conn_main_worker); ++#else ++ INIT_WORK(&conn->conn_worker, bnx2i_conn_main_worker, conn); ++#endif ++ atomic_set(&conn->worker_enabled, 1); ++#endif /* __VMKLNX__ */ ++ ++ init_timer(&conn->poll_timer); ++ conn->poll_timer.expires = HZ + jiffies; /* 200 msec */ ++ conn->poll_timer.function = bnx2i_conn_poll; ++ conn->poll_timer.data = (unsigned long) conn; ++ conn->poll_timer_enabled = 0; ++ ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_login_resp_update_cmdsn - extracts SN & MAX_SN from login response header & ++ * updates driver 'cmdsn' with ++ * ++ * @conn: iscsi connection pointer ++ * ++ * extract & update SN counters from login response ++ */ ++static int bnx2i_login_resp_update_cmdsn(struct bnx2i_conn *conn) ++{ ++ u32 max_cmdsn; ++ u32 exp_cmdsn; ++ u32 stat_sn; ++ struct bnx2i_sess *sess = conn->sess; ++ struct iscsi_nopin *hdr; ++ ++ hdr = (struct iscsi_nopin *) &conn->gen_pdu.resp_hdr; ++ ++ max_cmdsn = ntohl(hdr->max_cmdsn); ++ exp_cmdsn = ntohl(hdr->exp_cmdsn); ++ stat_sn = ntohl(hdr->statsn); ++#define SN_DELTA_ISLAND 0xffff ++ if (max_cmdsn < exp_cmdsn -1 && ++ max_cmdsn > exp_cmdsn - SN_DELTA_ISLAND) ++ return -EINVAL; ++ ++ if (max_cmdsn > sess->max_cmdsn || ++ max_cmdsn < sess->max_cmdsn - SN_DELTA_ISLAND) ++ sess->max_cmdsn = max_cmdsn; ++ ++ if (exp_cmdsn > sess->exp_cmdsn || ++ exp_cmdsn < sess->exp_cmdsn - SN_DELTA_ISLAND) ++ sess->exp_cmdsn = exp_cmdsn; ++ ++ if (stat_sn == conn->exp_statsn) ++ conn->exp_statsn++; ++ ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_update_cmd_sequence - update session sequencing parameter ++ * ++ * @sess: iscsi session pointer ++ * @exp_sn: iscsi expected command seq num ++ * @max_sn: iscsi max command seq num ++ * ++ * update iSCSI SN counters for the given session ++ */ ++void bnx2i_update_cmd_sequence(struct bnx2i_sess *sess, ++ u32 exp_sn, u32 max_sn) ++{ ++ u32 exp_cmdsn = exp_sn; ++ u32 max_cmdsn = max_sn; ++ ++ if (max_cmdsn < exp_cmdsn -1 && ++ max_cmdsn > exp_cmdsn - SN_DELTA_ISLAND) { ++ printk(KERN_ALERT "cmd_sequence: error, exp 0x%x, max 0x%x\n", ++ exp_cmdsn, max_cmdsn); ++ BUG_ON(1); ++ } ++ if (max_cmdsn > sess->max_cmdsn || ++ max_cmdsn < sess->max_cmdsn - SN_DELTA_ISLAND) ++ sess->max_cmdsn = max_cmdsn; ++ if (exp_cmdsn > sess->exp_cmdsn || ++ exp_cmdsn < sess->exp_cmdsn - SN_DELTA_ISLAND) ++ sess->exp_cmdsn = exp_cmdsn; ++} ++ ++ ++/** ++ * bnx2i_process_scsi_resp - complete SCSI command processing by calling ++ * 'scsi_done', free iscsi cmd structure to free list ++ * ++ * @cmd: iscsi cmd pointer ++ * @resp_cqe: scsi response cqe pointer ++ * ++ * validates scsi response indication for normal completion, sense data if any ++ * underflow/overflow condition and propogates SCSI response to SCSI-ML by ++ * calling scsi_done() and also returns command struct back to free pool ++ */ ++void bnx2i_process_scsi_resp(struct bnx2i_cmd *cmd, ++ struct iscsi_cmd_response *resp_cqe) ++{ ++ struct scsi_cmnd *sc = cmd->scsi_cmd; ++ u16 sense_data[128]; ++ int data_len; ++ u16 sense_len; ++ int res_count; ++ u8 flags; ++ ++ sc->result = (DID_OK << 16) | resp_cqe->status; ++ ++ if (resp_cqe->response != ISCSI_STATUS_CMD_COMPLETED) { ++ sc->result = (DID_ERROR << 16); ++ goto out; ++ } ++ ++ if (resp_cqe->status == SAM_STAT_CHECK_CONDITION) { ++ data_len = resp_cqe->data_length; ++ if (data_len < 2) { ++invalid_len: ++ printk(KERN_ERR "bnx2i: CHK_CONDITION - invalid " ++ "data length %d\n", data_len); ++ sc->result = (DID_BAD_TARGET << 16); ++ goto out; ++ } ++ ++ if (data_len > BNX2I_RQ_WQE_SIZE) { ++ printk(KERN_ALERT "bnx2i: sense data len %d > RQ sz\n", ++ data_len); ++ data_len = BNX2I_RQ_WQE_SIZE; ++ } ++ if (data_len) { ++ memset(sc->sense_buffer, 0, sizeof(sc->sense_buffer)); ++ bnx2i_get_rq_buf(cmd->conn, (char *)sense_data, data_len); ++ bnx2i_put_rq_buf(cmd->conn, 1); ++ cmd->conn->total_data_octets_rcvd += data_len; ++ sense_len = be16_to_cpu(*((__be16 *) sense_data)); ++ ++ if (data_len < sense_len) ++ goto invalid_len; ++ ++ if (sense_len > SCSI_SENSE_BUFFERSIZE) ++ sense_len = SCSI_SENSE_BUFFERSIZE; ++ ++ memcpy(sc->sense_buffer, &sense_data[1], ++ (int) sense_len); ++ } ++ } ++ ++ flags = resp_cqe->response_flags; ++ if (flags & (ISCSI_CMD_RESPONSE_RESIDUAL_UNDERFLOW | ++ ISCSI_CMD_RESPONSE_RESIDUAL_OVERFLOW)) { ++ res_count = resp_cqe->residual_count; ++ ++ if (res_count > 0 && (flags & ++ ISCSI_CMD_RESPONSE_RESIDUAL_OVERFLOW || ++ res_count <= scsi_bufflen(sc))) { ++ scsi_set_resid(sc, res_count); ++ cmd->conn->total_data_octets_rcvd -= res_count; ++ } else ++ sc->result = (DID_BAD_TARGET << 16) | resp_cqe->status; ++ } ++out: ++ return; ++ ++} ++ ++/** ++ * bnx2i_indicate_login_resp - process iscsi login response ++ * ++ * @conn: iscsi connection pointer ++ * ++ * pushes login response PDU to application daemon, 'iscsid' by ++ * calling iscsi_recv_pdu() ++ */ ++int bnx2i_indicate_login_resp(struct bnx2i_conn *conn) ++{ ++ int data_len; ++ struct iscsi_login_rsp *login_resp = ++ (struct iscsi_login_rsp *) &conn->gen_pdu.resp_hdr; ++ ++ /* check if this is the first login response for this connection. ++ * If yes, we need to copy initial StatSN to connection structure. ++ */ ++ if (conn->exp_statsn == STATSN_UPDATE_SIGNATURE) { ++ conn->exp_statsn = ntohl(login_resp->statsn) + 1; ++ } ++ ++ if (bnx2i_login_resp_update_cmdsn(conn)) ++ return -EINVAL; ++ ++ data_len = conn->gen_pdu.resp_wr_ptr - conn->gen_pdu.resp_buf; ++ iscsi_recv_pdu(conn->cls_conn, (struct iscsi_hdr *) login_resp, ++ (char *) conn->gen_pdu.resp_buf, data_len); ++ ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_indicate_logout_resp - process iscsi logout response ++ * ++ * @conn: iscsi connection pointer ++ * ++ * pushes logout response PDU to application daemon, 'iscsid' by ++ * calling iscsi_recv_pdu() ++ */ ++int bnx2i_indicate_logout_resp(struct bnx2i_conn *conn) ++{ ++ struct iscsi_logout_rsp *logout_resp = ++ (struct iscsi_logout_rsp *) &conn->gen_pdu.resp_hdr; ++ ++ iscsi_recv_pdu(conn->cls_conn, (struct iscsi_hdr *) logout_resp, ++ (char *) NULL, 0); ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_indicate_async_mesg - process iscsi ASYNC message indication ++ * ++ * @conn: iscsi connection pointer ++ * ++ * pushes iSCSI async PDU to application daemon, 'iscsid' by calling ++ * iscsi_recv_pdu() ++ */ ++int bnx2i_indicate_async_mesg(struct bnx2i_conn *conn) ++{ ++ struct iscsi_async *async_msg = ++ (struct iscsi_async *) &conn->gen_pdu.async_hdr; ++ ++ printk("%s: indicating async message on cid %d\n", __FUNCTION__, conn->ep->ep_iscsi_cid); ++ ++ iscsi_recv_pdu(conn->cls_conn, (struct iscsi_hdr *) async_msg, ++ (char *) NULL, 0); ++ return 0; ++} ++ ++ ++ ++/** ++ * bnx2i_process_nopin - process iscsi nopin pdu ++ * ++ * @conn: iscsi connection pointer ++ * @cmd: iscsi cmd pointer ++ * @data_buf: payload buffer pointer ++ * @data_len: payload length ++ * ++ * pushes nopin pdu to application daemon, 'iscsid' by calling iscsi_recv_pdu ++ */ ++int bnx2i_process_nopin(struct bnx2i_conn *conn, struct bnx2i_cmd *cmd, ++ char *data_buf, int data_len) ++{ ++ struct iscsi_nopin *nopin_msg = ++ (struct iscsi_nopin *) &conn->gen_pdu.nopin_hdr; ++ ++ iscsi_recv_pdu(conn->cls_conn, (struct iscsi_hdr *) nopin_msg, ++ (char *) data_buf, data_len); ++ ++ conn->sess->last_noopin_indicated = jiffies; ++ conn->sess->noopin_indicated_count++; ++ ++ cmd->iscsi_opcode = 0; ++ return 0; ++} ++ ++ ++ ++/** ++ * bnx2i_iscsi_prep_generic_pdu_bd - prepares BD table to be used with ++ * generic iscsi pdus ++ * ++ * @conn: iscsi connection pointer ++ * ++ * Allocates buffers and BD tables before shipping requests to cnic ++ * for PDUs prepared by 'iscsid' daemon ++ */ ++static void bnx2i_iscsi_prep_generic_pdu_bd(struct bnx2i_conn *conn) ++{ ++ struct iscsi_bd *bd_tbl; ++ ++ bd_tbl = (struct iscsi_bd *) conn->gen_pdu.login_req.pgtbl; ++ ++ bd_tbl->buffer_addr_hi = ++ (u32) ((u64) conn->gen_pdu.login_req.mapping >> 32); ++ bd_tbl->buffer_addr_lo = (u32) conn->gen_pdu.login_req.mapping; ++ bd_tbl->buffer_length = conn->gen_pdu.req_wr_ptr - ++ conn->gen_pdu.req_buf; ++ bd_tbl->reserved0 = 0; ++ bd_tbl->flags = ISCSI_BD_LAST_IN_BD_CHAIN | ++ ISCSI_BD_FIRST_IN_BD_CHAIN; ++ ++ bd_tbl = (struct iscsi_bd *) conn->gen_pdu.login_resp.pgtbl; ++ bd_tbl->buffer_addr_hi = (u64) conn->gen_pdu.login_resp.mapping >> 32; ++ bd_tbl->buffer_addr_lo = (u32) conn->gen_pdu.login_resp.mapping; ++ bd_tbl->buffer_length = ISCSI_CONN_LOGIN_BUF_SIZE; ++ bd_tbl->reserved0 = 0; ++ bd_tbl->flags = ISCSI_BD_LAST_IN_BD_CHAIN | ++ ISCSI_BD_FIRST_IN_BD_CHAIN; ++} ++ ++ ++/** ++ * bnx2i_nopout_check_active_cmds - checks if iscsi link is idle ++ * ++ * @hba: pointer to adapter instance ++ * ++ * called to check if iscsi connection is idle or not. Pro-active nopout ++ * is sent only if the link is idle ++ */ ++static int bnx2i_nopout_check_active_cmds(struct bnx2i_conn *conn, ++ struct bnx2i_cmd *cmnd) ++{ ++ struct iscsi_nopin *nopin_msg = ++ (struct iscsi_nopin *) &conn->gen_pdu.resp_hdr; ++ ++ if ((conn->nopout_num_scsi_cmds == conn->num_scsi_cmd_pdus) && ++ !conn->sess->active_cmd_count) { ++ return -1; ++ } ++ ++ memset(nopin_msg, 0x00, sizeof(struct iscsi_nopin)); ++ nopin_msg->opcode = ISCSI_OP_NOOP_IN; ++ nopin_msg->flags = ISCSI_FLAG_CMD_FINAL; ++ memcpy(nopin_msg->lun, conn->gen_pdu.nopout_hdr.lun, 8); ++ nopin_msg->itt = conn->gen_pdu.nopout_hdr.itt; ++ nopin_msg->ttt = ISCSI_RESERVED_TAG; ++ nopin_msg->statsn = conn->gen_pdu.nopout_hdr.exp_statsn; ++ nopin_msg->exp_cmdsn = htonl(conn->sess->exp_cmdsn); ++ nopin_msg->max_cmdsn = htonl(conn->sess->max_cmdsn); ++ ++ iscsi_recv_pdu(conn->cls_conn, (struct iscsi_hdr *) nopin_msg, ++ (char *) NULL, 0); ++ ++ conn->nopout_num_scsi_cmds = conn->num_scsi_cmd_pdus; ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_iscsi_send_generic_request - called to send iscsi login/nopout/logout ++ * pdus ++ * ++ * @hba: pointer to adapter instance ++ * ++ * called to transmit PDUs prepared by the 'iscsid' daemon. iSCSI login, ++ * Nop-out and Logout requests flow through this path. ++ */ ++static int bnx2i_iscsi_send_generic_request(struct bnx2i_cmd *cmnd) ++{ ++ int rc = 0; ++ struct bnx2i_conn *conn = cmnd->conn; ++ ++ bnx2i_iscsi_prep_generic_pdu_bd(conn); ++ switch (cmnd->iscsi_opcode & ISCSI_OPCODE_MASK) { ++ case ISCSI_OP_LOGIN: ++ bnx2i_send_iscsi_login(conn, cmnd); ++ break; ++ ++ case ISCSI_OP_NOOP_OUT: ++ if (!bnx2i_nopout_when_cmds_active) ++ if (!bnx2i_nopout_check_active_cmds(conn, cmnd)) { ++ return 0; ++ } ++ ++ conn->nopout_num_scsi_cmds = conn->num_scsi_cmd_pdus; ++ rc = bnx2i_send_iscsi_nopout(conn, cmnd, NULL, 0); ++ break; ++ ++ case ISCSI_OP_LOGOUT: ++ rc = bnx2i_send_iscsi_logout(conn, cmnd); ++ break; ++ ++ default: ++ printk(KERN_ALERT "send_gen: unsupported op 0x%x\n", ++ cmnd->iscsi_opcode); ++ } ++ return rc; ++} ++ ++ ++/********************************************************************** ++ * SCSI-ML Interface ++ **********************************************************************/ ++ ++/** ++ * bnx2i_cpy_scsi_cdb - copies LUN & CDB fields in required format to sq wqe ++ * ++ * @sc: SCSI-ML command pointer ++ * @cmd: iscsi cmd pointer ++ * ++ */ ++static void bnx2i_cpy_scsi_cdb(struct scsi_cmnd *sc, ++ struct bnx2i_cmd *cmd) ++{ ++ u32 dword; ++ int lpcnt; ++ u8 *srcp; ++ u32 *dstp; ++ u32 scsi_lun[2]; ++ ++ int_to_scsilun(sc->device->lun, (struct scsi_lun *) scsi_lun); ++ cmd->req.lun[0] = ntohl(scsi_lun[0]); ++ cmd->req.lun[1] = ntohl(scsi_lun[1]); ++ ++ lpcnt = cmd->scsi_cmd->cmd_len / sizeof(dword); ++ srcp = (u8 *) sc->cmnd; ++ dstp = (u32 *) cmd->req.cdb; ++ while (lpcnt--) { ++ memcpy(&dword, (const void *) srcp, 4); ++ *dstp = cpu_to_be32(dword); ++ srcp += 4; ++ dstp++; ++ } ++ if (sc->cmd_len & 0x3) { ++ dword = (u32) srcp[0] | ((u32) srcp[1] << 8); ++ *dstp = cpu_to_be32(dword); ++ } ++} ++ ++ ++#ifdef __VMKLNX__ ++static int bnx2i_slave_configure(struct scsi_device *sdev) ++{ ++ return 0; ++} ++ ++static int bnx2i_slave_alloc(struct scsi_device *sdev) ++{ ++ struct iscsi_cls_session *cls_sess; ++ ++ cls_sess = vmk_iscsi_getSessionFromTarget(sdev->host->host_no, ++ sdev->channel, sdev->id); ++ if (!cls_sess) ++ return FAILED; ++ ++ sdev->hostdata = cls_sess->dd_data; ++ return 0; ++} ++ ++static int bnx2i_target_alloc(struct scsi_target *starget) ++{ ++ struct iscsi_cls_session *cls_sess; ++ struct Scsi_Host *shost = dev_to_shost(starget->dev.parent); ++ ++ cls_sess = vmk_iscsi_getSessionFromTarget(shost->host_no, ++ starget->channel, starget->id); ++ if (!cls_sess) ++ return FAILED; ++ ++ starget->hostdata = cls_sess->dd_data; ++ return 0; ++} ++ ++static void bnx2i_target_destroy(struct scsi_target *starget) ++{ ++ struct bnx2i_sess *sess = starget->hostdata; ++ ++ if (!sess) ++ return; ++ ++ if (sess->state == BNX2I_SESS_DESTROYED) ++ bnx2i_release_session_resc(sess->cls_sess); ++ else ++ sess->state = BNX2I_SESS_TARGET_DESTROYED; ++} ++#endif ++ ++ ++#define BNX2I_SERIAL_32 2147483648UL ++ ++static int iscsi_cmd_win_closed(struct bnx2i_sess *sess) ++{ ++ u32 cmdsn = sess->cmdsn; ++ u32 maxsn = sess->max_cmdsn; ++ ++ return ((cmdsn < maxsn && (maxsn - cmdsn > BNX2I_SERIAL_32)) || ++ (cmdsn > maxsn && (cmdsn - maxsn < BNX2I_SERIAL_32))); ++ ++} ++ ++ ++/** ++ * bnx2i_queuecommand - SCSI ML - bnx2i interface function to issue new commands ++* to be shipped to iscsi target ++ * ++ * @sc: SCSI-ML command pointer ++ * @done: callback function pointer to complete the task ++ * ++ * handles SCSI command queued by SCSI-ML, allocates a command structure, ++ * assigning CMDSN, mapping SG buffers and delivers it to CNIC for further ++ * processing. This routine also takes care of iSCSI command window full ++ * condition, if session is in recovery process and other error conditions ++ */ ++int bnx2i_queuecommand(struct scsi_cmnd *sc, ++ void (*done) (struct scsi_cmnd *)) ++{ ++ struct bnx2i_scsi_task *scsi_task; ++ unsigned long flags; ++ struct bnx2i_sess *sess; ++ struct bnx2i_conn *conn; ++#if !defined(__VMKLNX__) ++ struct Scsi_Host *shost; ++#endif ++ ++#ifdef __VMKLNX__ ++ if (sc->device && sc->device->hostdata) ++ sess = (struct bnx2i_sess *)sc->device->hostdata; ++ else ++ goto dev_not_found; ++#else ++ sess = iscsi_hostdata(sc->device->host->hostdata); ++#endif ++ sc->scsi_done = done; ++ sc->result = 0; ++ ++ if (!sess) ++ goto dev_not_found; ++ ++#ifdef __VMKLNX__ ++ if (sess->state == BNX2I_SESS_DESTROYED) ++ goto dev_offline; ++#endif ++ if (sess->state == BNX2I_SESS_IN_SHUTDOWN || ++ sess->state == BNX2I_SESS_IN_LOGOUT || !sess->lead_conn) ++#ifdef __VMKLNX__ ++ /* delay offline indication till session is destroyed */ ++ goto cmd_not_accepted; ++#else ++ goto dev_not_found; ++#endif ++ ++ if (sess->recovery_state) { ++ if (sess->recovery_state & ISCSI_SESS_RECOVERY_START) ++ goto cmd_not_accepted; ++ else if (sess->recovery_state & ISCSI_SESS_RECOVERY_COMPLETE) ++ sess->recovery_state = 0; ++ else ++ goto dev_not_found; ++ } ++ ++ conn = sess->lead_conn; ++ /* Is connection stopped because of nopout timeout?. Don't accept scsi_cmds ++ * if connection is in stopped state because we don't know if it's going ++ * come online or taken offline after session recovery timeout */ ++ if (!atomic_read(&conn->worker_enabled)) ++ goto cmd_not_accepted; ++ ++ spin_lock_irqsave(&sess->lock, flags); ++ scsi_task = bnx2i_alloc_scsi_task(sess); ++ if (!scsi_task) { ++ spin_unlock_irqrestore(&sess->lock, flags); ++ goto cmd_not_accepted; ++ } ++ ++ scsi_task->scsi_cmd = sc; ++ list_add_tail(&scsi_task->link, &sess->pend_cmd_list); ++ sess->pend_cmd_count++; ++ spin_unlock_irqrestore(&sess->lock, flags); ++ ++ if (atomic_read(&conn->worker_enabled)) { ++#ifdef __VMKLNX__ ++ tasklet_schedule(&conn->conn_tasklet); ++#else ++ shost = bnx2i_conn_get_shost(conn); ++ scsi_queue_work(shost, &conn->conn_worker); ++#endif /* __VMKLNX__ */ ++ } ++ return 0; ++ ++cmd_not_accepted: ++ return SCSI_MLQUEUE_HOST_BUSY; ++ ++#ifdef __VMKLNX__ ++dev_offline: ++#endif ++dev_not_found: ++ sc->result = (DID_NO_CONNECT << 16); ++ scsi_set_resid(sc, scsi_bufflen(sc)); ++ sc->scsi_done(sc); ++ return 0; ++} ++ ++static void bnx2i_conn_poll(unsigned long data) ++{ ++ struct bnx2i_conn *conn = (struct bnx2i_conn *) data; ++#if !defined(__VMKLNX__) ++ struct Scsi_Host *shost; ++#endif ++ ++ if (!atomic_read(&conn->worker_enabled)) ++ goto exit; ++ if (bnx2i_cqe_work_pending(conn) || ++ !list_empty(&conn->sess->pend_cmd_list)) { ++#ifdef __VMKLNX__ ++ tasklet_schedule(&conn->conn_tasklet); ++#else ++ shost = bnx2i_conn_get_shost(conn); ++ scsi_queue_work(shost, &conn->conn_worker); ++#endif ++ } ++exit: ++ conn->poll_timer.expires = 50 + jiffies; /* 500 msec */ ++ add_timer(&conn->poll_timer); ++} ++ ++ ++/** ++ * bnx2i_fail_cmd - fail the command back to SCSI-ML ++ * ++ * @sess: iscsi sess pointer ++ * @cmd: command pointer ++ * ++ * Return failed command to SCSI-ML. ++ */ ++void bnx2i_fail_cmd(struct bnx2i_sess *sess, struct bnx2i_cmd *cmd) ++{ ++ struct scsi_cmnd *sc; ++ int reason; ++ ++ bnx2i_iscsi_unmap_sg_list(sess->hba, cmd); ++ ++ spin_lock_bh(&sess->lock); ++ sc = cmd->scsi_cmd; ++ reason = cmd->failed_reason; ++ cmd->req.itt &= ISCSI_CMD_RESPONSE_INDEX; ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_COMPLETED); ++ sess->active_cmd_count--; ++ cmd->scsi_cmd = NULL; ++ bnx2i_free_cmd(sess, cmd); ++ spin_unlock_bh(&sess->lock); ++ ++ bnx2i_return_failed_command(sess, sc, scsi_bufflen(sc), reason); ++} ++ ++struct bnx2i_scsi_task *bnx2i_scsi_cmd_in_pend_list(struct bnx2i_sess *sess, ++ struct scsi_cmnd *sc) ++{ ++ struct bnx2i_scsi_task *scsi_task; ++ struct list_head *list; ++ struct list_head *tmp; ++ ++ list_for_each_safe(list, tmp, &sess->pend_cmd_list) { ++ scsi_task = (struct bnx2i_scsi_task *) list; ++ if (scsi_task->scsi_cmd == sc) ++ return scsi_task; ++ } ++ return NULL; ++} ++ ++/** ++ * bnx2i_send_tmf_wait_cmpl - executes scsi command abort process ++ * ++ * @sc: SCSI-ML command pointer ++ * ++ * initiate command abort process by requesting CNIC to send ++ * an iSCSI TMF request to target ++ */ ++static int bnx2i_send_tmf_wait_cmpl(struct bnx2i_sess *sess) ++{ ++ int rc = 0; ++ struct bnx2i_cmd *tmf_cmd = sess->scsi_tmf_cmd; ++ struct bnx2i_conn *conn = sess->lead_conn; ++#ifndef __VMKLNX__ ++ struct Scsi_Host *shost = bnx2i_conn_get_shost(conn); ++#endif ++ ++ tmf_cmd->tmf_response = ISCSI_TMF_RSP_REJECTED; ++ ++ /* Schedule the tasklet to send out the TMF pdu */ ++ atomic_set(&sess->tmf_pending, 1); ++ if (atomic_read(&conn->worker_enabled)) { ++#ifdef __VMKLNX__ ++ printk("bnx2i: scheduling TMF for cid %d\n", conn->ep->ep_iscsi_cid); ++ tasklet_schedule(&conn->conn_tasklet); ++#else ++ scsi_queue_work(shost, &conn->conn_worker); ++#endif ++ } ++ ++#define BNX2I_TMF_TIMEOUT 10 * HZ ++ /* Now we wait here */ ++ rc = wait_event_timeout(sess->er_wait, ++ ((sess->recovery_state != 0) || ++ (atomic_read(&tmf_cmd->cmd_state) != ++ ISCSI_CMD_STATE_INITIATED)), ++ BNX2I_TMF_TIMEOUT); ++ ++ if (signal_pending(current)) ++ flush_signals(current); ++ ++ if (!rc) { ++ atomic_set(&tmf_cmd->cmd_state, ISCSI_CMD_STATE_TMF_TIMEOUT); ++ sess->recovery_state = ISCSI_SESS_RECOVERY_OPEN_ISCSI; ++ iscsi_conn_error(conn->cls_conn, ISCSI_ERR_CONN_FAILED); ++ /* set conn->stop_state to non-zero so that further TMF will not ++ * be allowed to seek in, this halt is only required untill ++ * 'vmkiscsid' issues conn_stop() ++ */ ++ atomic_set(&conn->stop_state, 0xFF); ++ atomic_set(&sess->tmf_pending, 0); ++ atomic_set(&sess->tmf_active, 0); ++ return -1; ++ } ++ ++ ++ ++ if (atomic_read(&sess->tmf_pending)) ++ printk("%s:: WaTcH: is tmf still pending \n", __FUNCTION__); ++ ++ if (tmf_cmd->tmf_response == ISCSI_TMF_RSP_COMPLETE) { ++ /* normal successs case */ ++ return 0; ++ } else if (tmf_cmd->tmf_response == ISCSI_TMF_RSP_NO_TASK) { ++ if (tmf_cmd->tmf_ref_cmd->scsi_cmd == tmf_cmd->tmf_ref_sc) { ++ if (atomic_read(&tmf_cmd->tmf_ref_cmd->cmd_state) == ISCSI_CMD_STATE_COMPLETED) { ++ /* task completed while tmf request is pending, driver is ++ * holding on to the completion ++ */ ++ return 0; ++ } else { ++ /* missing command, do session recovery */ ++ goto do_recovery; ++ } ++ } else { ++ return 0; /* command already completed */ ++ } ++ } ++ ++do_recovery: ++ printk(KERN_ALERT "%s: tmf failed, cmd 0x%p\n", __FUNCTION__, tmf_cmd); ++#ifdef __VMKLNX__ ++ bnx2i_do_iscsi_sess_recovery(sess, DID_RESET); ++#endif ++ return -1; ++} ++ ++static void bnx2i_cleanup_task_context(struct bnx2i_sess *sess, ++ struct bnx2i_cmd *cmd, int reason) ++{ ++ if (!cmd->scsi_cmd) ++ return; ++ ++ /* cleanup on chip task context for command affected by ++ * ABORT_TASK/LUN_RESET ++ */ ++ cmd->failed_reason = reason; ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_CLEANUP_PEND); ++ sess->cmd_cleanup_req++; ++ bnx2i_send_cmd_cleanup_req(sess->hba, cmd); ++} ++ ++/** ++ * bnx2i_initiate_target_reset- executes scsi command target reset ++ * ++ * @sc: SCSI-ML command pointer ++ * ++ * initiate command abort process by requesting CNIC to send ++ * an iSCSI TMF request to target ++ */ ++static int bnx2i_initiate_target_reset(struct bnx2i_sess *sess) ++{ ++ struct bnx2i_cmd *tmf_cmd; ++ struct bnx2i_hba *hba; ++ ++ hba = sess->hba; ++ tmf_cmd = sess->scsi_tmf_cmd; ++ atomic_set(&sess->tmf_active, 1); ++ tmf_cmd->conn = sess->lead_conn; ++ tmf_cmd->scsi_cmd = NULL; ++ tmf_cmd->iscsi_opcode = ISCSI_OP_SCSI_TMFUNC | ISCSI_OP_IMMEDIATE; ++ tmf_cmd->tmf_func = ISCSI_TM_FUNC_TARGET_WARM_RESET; ++ tmf_cmd->tmf_lun = 0; ++ tmf_cmd->tmf_ref_itt = ISCSI_RESERVED_TAG; ++ tmf_cmd->tmf_ref_cmd = NULL; ++ tmf_cmd->tmf_ref_sc = NULL; ++ atomic_set(&tmf_cmd->cmd_state, ISCSI_CMD_STATE_INITIATED); ++ ++ printk("%s: sess %p, conn %p\n", __FUNCTION__, sess, sess->lead_conn); ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_initiate_lun_reset- executes scsi command abort process ++ * ++ * @sc: SCSI-ML command pointer ++ * ++ * initiate command abort process by requesting CNIC to send ++ * an iSCSI TMF request to target ++ */ ++static int bnx2i_initiate_lun_reset(struct bnx2i_sess *sess, struct scsi_cmnd *sc) ++{ ++ struct bnx2i_cmd *tmf_cmd; ++ struct bnx2i_conn *conn; ++ struct bnx2i_hba *hba; ++ ++ hba = sess->hba; ++ tmf_cmd = sess->scsi_tmf_cmd; ++ atomic_set(&sess->tmf_active, 1); ++ tmf_cmd->conn = conn = sess->lead_conn; ++ tmf_cmd->scsi_cmd = NULL; ++ tmf_cmd->iscsi_opcode = ISCSI_OP_SCSI_TMFUNC | ISCSI_OP_IMMEDIATE; ++ tmf_cmd->tmf_func = ISCSI_TM_FUNC_LOGICAL_UNIT_RESET; ++ tmf_cmd->tmf_lun = sc->device->lun; ++ tmf_cmd->tmf_ref_itt = ISCSI_RESERVED_TAG; ++ tmf_cmd->tmf_ref_cmd = NULL; ++ tmf_cmd->tmf_ref_sc = NULL; ++ atomic_set(&tmf_cmd->cmd_state, ISCSI_CMD_STATE_INITIATED); ++ ++ return 0; ++} ++ ++/** ++ * bnx2i_initiate_abort_cmd - executes scsi command abort process ++ * ++ * @sc: SCSI-ML command pointer ++ * ++ * initiate command abort process by requesting CNIC to send ++ * an iSCSI TMF request to target ++ */ ++static int bnx2i_initiate_abort_cmd(struct bnx2i_sess *sess, struct scsi_cmnd *sc, ++ struct bnx2i_cmd **aborted_cmd) ++{ ++ struct bnx2i_cmd *cmd; ++ struct bnx2i_cmd *tmf_cmd; ++ struct bnx2i_conn *conn; ++ struct bnx2i_hba *hba; ++ ++ *aborted_cmd = NULL; ++ hba = sess->hba; ++ cmd = (struct bnx2i_cmd *) sc->SCp.ptr; ++ ++ if (!cmd || !cmd->scsi_cmd || cmd->scsi_cmd != sc) { ++ /* command already completed to scsi mid-layer */ ++ printk("%s: WaTcH: sc %p on lun %x, already completed\n", ++ __FUNCTION__, sc, sc->device->lun); ++ return -ENOENT; ++ } ++ ++ *aborted_cmd = cmd; ++ tmf_cmd = sess->scsi_tmf_cmd; ++ atomic_set(&sess->tmf_active, 1); ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_ABORT_PEND); ++ atomic_set(&tmf_cmd->cmd_state, ISCSI_CMD_STATE_INITIATED); ++ tmf_cmd->conn = conn = sess->lead_conn; ++ tmf_cmd->scsi_cmd = NULL; ++ tmf_cmd->iscsi_opcode = ISCSI_OP_SCSI_TMFUNC | ISCSI_OP_IMMEDIATE; ++ tmf_cmd->tmf_func = ISCSI_TM_FUNC_ABORT_TASK; ++ tmf_cmd->tmf_lun = sc->device->lun; ++ tmf_cmd->tmf_ref_itt = cmd->req.itt; ++ tmf_cmd->tmf_ref_cmd = cmd; ++ tmf_cmd->tmf_ref_sc = cmd->scsi_cmd; ++ printk("%s [ %lx ] : aborting active cmd sc %p, lun %x" ++ " ref_cmd %p, ref_scsi_cmd %p \n", __FUNCTION__, ++ jiffies, sc, sc->device->lun, tmf_cmd->tmf_ref_cmd, ++ tmf_cmd->tmf_ref_sc); ++ ++ return -EINPROGRESS; ++} ++ ++ ++static void bnx2i_tmf_wait_dev_offlined(struct bnx2i_sess *sess) ++{ ++ /* Still some clarification on this subject is going on with Vmware team ++ * Code will be added later ++ */ ++} ++ ++ ++/** ++ * bnx2i_execute_tmf_cmd - executes scsi tmf ++ * ++ * @sc: SCSI-ML command pointer ++ * ++ * initiate scsi tmf, support ABORT_TASK and LUN_RESET ++ */ ++static int bnx2i_execute_tmf_cmd(struct scsi_cmnd *sc, int tmf_func) ++{ ++ int active_cmds_failed = 0; ++ int pend_cmds_failed = 0; ++ struct bnx2i_cmd *cmd = NULL; ++#ifndef __VMKLNX__ ++ struct Scsi_Host *shost; ++#endif ++ struct bnx2i_sess *sess = NULL; ++ int rc = FAILED; ++ int wait_rc; ++ ++#ifdef __VMKLNX__ ++ if (sc->device && sc->device->hostdata) ++ sess = (struct bnx2i_sess *)sc->device->hostdata; ++#else ++ shost = sc->device->host; ++ sess = iscsi_hostdata(shost->hostdata); ++ BUG_ON(shost != sess->shost); ++#endif ++ if (sess == NULL) { ++ printk("%s: TMF session=NULL\n", __FUNCTION__); ++ return FAILED; ++ } ++ ++ mutex_lock(&sess->tmf_mutex); ++ ++ if (test_bit(ADAPTER_STATE_GOING_DOWN, &sess->hba->adapter_state) || ++ test_bit(ADAPTER_STATE_LINK_DOWN, &sess->hba->adapter_state)) { ++ printk("%s: TMF session LINK\n", __FUNCTION__); ++ mutex_unlock(&sess->tmf_mutex); ++ return FAILED; ++ } ++ ++ spin_lock_bh(&sess->lock); ++ if (!sess || atomic_read(&sess->lead_conn->stop_state) || ++ !is_sess_active(sess)) { ++ printk("%s: TMF session stoped\n", __FUNCTION__); ++ /* better to wait till device is offlined to avoid ABORT storm ++ */ ++ spin_unlock_bh(&sess->lock); ++ bnx2i_tmf_wait_dev_offlined(sess); ++ mutex_unlock(&sess->tmf_mutex); ++ return FAILED; ++ } ++ ++ atomic_set(&sess->tmf_active, 1); ++ if (tmf_func == ISCSI_TM_FUNC_ABORT_TASK) { ++ rc = bnx2i_initiate_abort_cmd(sess, sc, &cmd); ++ if (rc == -ENOENT) { ++ /* cmd not active */ ++ rc = FAILED; ++ spin_unlock_bh(&sess->lock); ++ goto done; ++ } ++ rc = SUCCESS; ++ } else if (tmf_func == ISCSI_TM_FUNC_LOGICAL_UNIT_RESET) { ++ bnx2i_initiate_lun_reset(sess, sc); ++ } else if (tmf_func == ISCSI_TM_FUNC_TARGET_WARM_RESET) { ++ printk("%s: tmf TGT_RESET, sess %p\n", __FUNCTION__, sess); ++ bnx2i_initiate_target_reset(sess); ++ } else { ++ printk(KERN_ALERT "bnx2i: unknown Task Mgmt Command %x\n", ++ tmf_func); ++ rc = FAILED; ++ spin_unlock_bh(&sess->lock); ++ goto done; ++ } ++ spin_unlock_bh(&sess->lock); ++ ++ printk("%s: tmf wait......., sess %p\n", __FUNCTION__, sess); ++ if (bnx2i_send_tmf_wait_cmpl(sess)) { ++ /* TMF request timeout */ ++ rc = FAILED; ++ goto done; ++ } ++ ++ sess->cmd_cleanup_req = 0; ++ sess->cmd_cleanup_cmpl = 0; ++ ++ if (sess->scsi_tmf_cmd->tmf_response == ISCSI_TMF_RSP_COMPLETE) { ++ if (tmf_func == ISCSI_TM_FUNC_ABORT_TASK) { ++ if (cmd->scsi_status_rcvd) { ++ /* cmd completed while TMF was active. ++ * Now it's safe to complete command ++ * to SCSI-ML ++ */ ++ bnx2i_complete_cmd(sess, cmd); ++ } else { ++ bnx2i_cleanup_task_context(sess, cmd, DID_ABORT); ++ } ++ active_cmds_failed = 1; ++ } else if (tmf_func == ISCSI_TM_FUNC_LOGICAL_UNIT_RESET) { ++ /* Pend queue is already flushed before issuing send TMF ++ * request on wire. This is just a redundant flush which ++ * should do allow us to detect any command queued while ++ * TMF is active ++ */ ++ pend_cmds_failed = bnx2i_flush_pend_queue(sess, sc, DID_RESET); ++ active_cmds_failed = bnx2i_flush_cmd_queue(sess, sc, DID_RESET, 1); ++ } else if (tmf_func == ISCSI_TM_FUNC_TARGET_WARM_RESET) { ++ /* pend queue- Same comments as LUN RESET holds good here */ ++ pend_cmds_failed = bnx2i_flush_pend_queue(sess, NULL, DID_RESET); ++ active_cmds_failed = bnx2i_flush_cmd_queue(sess, NULL, DID_RESET, 1); ++ } ++ rc = SUCCESS; ++ } else if ((sess->scsi_tmf_cmd->tmf_response == ISCSI_TMF_RSP_NO_TASK) && ++ (tmf_func == ISCSI_TM_FUNC_ABORT_TASK)) { ++ if (!cmd->scsi_cmd || ++ (cmd->scsi_cmd != sess->scsi_tmf_cmd->tmf_ref_sc)) { ++ /* command already completed, later case cmd is being ++ * reused for a different I/O ++ */ ++ rc = FAILED; ++ } else if (cmd->scsi_status_rcvd) { ++ /* cmd completed while TMF was active. Now it's safe ++ * to complete the command back to SCSI-ML ++ */ ++ bnx2i_complete_cmd(sess, cmd); ++ rc = FAILED; ++ } else { ++ /* we should never step into this code path as missing command ++ * will trigger session recovery in bnx2i_send_tmf_wait_cmpl() ++ */ ++ BUG_ON(1); ++ } ++ } else ++ rc = FAILED; ++ ++ wait_rc = wait_event_interruptible_timeout(sess->er_wait, ++ !is_sess_active(sess) || ++ (sess->cmd_cleanup_req == sess->cmd_cleanup_cmpl), ++ 30 * HZ); ++ ++ if (!is_sess_active(sess)) { ++ /* session went into recovery due to protocol error, there won't ++ * be any CQ completions, active command cleanup will continue ++ * in ep_disconnect() ++ */ ++ printk("%s: session in recovery\n", __FUNCTION__); ++ rc = FAILED; ++ } else if (!wait_rc) { ++ printk("%s: WaTcH - cleanup did not complete in 30 seconds\n", ++ __FUNCTION__); ++ /* If TCP layer is working fine, CMD_CLEANUP should complete ++ * 'Cuz all CMD before TMF REQ would have been TCP ACK'ed. ++ * If there is a problem with the TCP layer, TMF request should ++ * have timed out triggering session recovery ++ */ ++ BUG_ON(1); ++ } ++ ++ if (signal_pending(current)) ++ flush_signals(current); ++ printk("%s: WaTcH - async cmd cleanup - requested %d, completed %d\n", ++ __FUNCTION__, sess->cmd_cleanup_req, sess->cmd_cleanup_cmpl); ++ ++done: ++ barrier(); ++ atomic_set(&sess->tmf_active, 0); ++ mutex_unlock(&sess->tmf_mutex); ++ ++ return rc; ++} ++ ++static void bnx2i_wait_for_tmf_completion(struct bnx2i_sess *sess) ++{ ++ int lpcnt = 200; ++ ++ while (lpcnt-- && atomic_read(&sess->tmf_active)) ++ msleep(100); ++} ++ ++/** ++ * bnx2i_abort - 'eh_abort_handler' api function to abort an oustanding ++ * scsi command ++ * ++ * @sc: SCSI-ML command pointer ++ * ++ * SCSI abort request handler. ++ */ ++int bnx2i_abort(struct scsi_cmnd *sc) ++{ ++ int reason; ++ struct bnx2i_hba *hba; ++ struct bnx2i_cmd *cmd = (struct bnx2i_cmd *) sc->SCp.ptr; ++ struct bnx2i_sess *sess; ++ ++#ifdef __VMKLNX__ ++ if (sc->device && sc->device->hostdata) ++ sess = (struct bnx2i_sess *)sc->device->hostdata; ++#else ++ struct Scsi_Host *shost = sc->device->host; ++ sess = iscsi_hostdata(shost->hostdata); ++#endif ++ ++ ++ /** ++ * we can ALWAYS abort from the pending queue ++ * since it has not made it to the chip yet ++ * NOTE: the queue has to be protected via spin lock ++ */ ++ spin_lock_bh(&sess->lock); ++ if (sc->device && sc->device->hostdata) { ++ struct bnx2i_scsi_task *scsi_task; ++ hba = sess->hba; ++ scsi_task = bnx2i_scsi_cmd_in_pend_list(sess, sc); ++ if (scsi_task) { ++ sc->result = (DID_ABORT << 16); ++ list_del_init(&scsi_task->link); ++ bnx2i_free_scsi_task(sess, scsi_task); ++ spin_unlock_bh(&sess->lock); ++ bnx2i_return_failed_command(sess, sc, ++ scsi_bufflen(sc), DID_ABORT); ++ printk(KERN_INFO "%s: aborted from pending queue\n", ++ __FUNCTION__); ++ return SUCCESS; ++ } ++ } ++ ++ /** It wasn't in the pending queue... and it still has no cmd object ++ * it must have completed out. ++ */ ++ if (unlikely(!cmd) || cmd->scsi_cmd != sc) { ++ /* command already completed to scsi mid-layer */ ++ printk(KERN_INFO "bnx2i_abort: sc 0x%p, lun %d is not active\n", ++ sc, sc->device->lun); ++ spin_unlock_bh(&sess->lock); ++ return FAILED; ++ } ++ ++ if ((atomic_read(&cmd->cmd_state) != ISCSI_CMD_STATE_INITIATED) || ++ !cmd->conn->ep) { ++ /* Command completion is being processed, fail the abort request ++ * Second condition should never be true unless SCSI layer is ++ * out of sync ++ */ ++ spin_unlock_bh(&sess->lock); ++ return FAILED; ++ } ++ /* Set cmd_state so that command will not be completed to SCSI-ML ++ * if SCSI_RESP is rcvd for this command ++ */ ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_ABORT_REQ); ++ spin_unlock_bh(&sess->lock); ++ ++ reason = bnx2i_execute_tmf_cmd(sc, ISCSI_TM_FUNC_ABORT_TASK); ++ return reason; ++} ++ ++ ++ ++/** ++ * bnx2i_return_failed_command - return failed command back to SCSI-ML ++ * ++ * @sess: iscsi session pointer ++ * @cmd: iscsi cmd pointer ++ * @reason: SCSI-ML error code, DID_ABORT, DID_BUS_BUSY ++ * ++ * completes scsi command with appropriate error code to SCSI-ML ++ */ ++void bnx2i_return_failed_command(struct bnx2i_sess *sess, struct scsi_cmnd *sc, ++ int resid, int reason) ++{ ++ sc->result = reason << 16; ++ scsi_set_resid(sc, resid); ++ sc->SCp.ptr = NULL; ++ sc->scsi_done(sc); ++} ++ ++ ++#ifdef __VMKLNX__ ++/** ++ * bnx2i_host_reset - 'eh_host_reset_handler' entry point ++ * ++ * @sc: SCSI-ML command pointer ++ * ++ * SCSI host reset handler - Do iSCSI session recovery on all active sessions ++ */ ++int bnx2i_host_reset(struct scsi_cmnd *sc) ++{ ++ struct Scsi_Host *shost; ++ struct bnx2i_sess *sess; ++ struct bnx2i_conn *conn; ++ struct bnx2i_hba *hba; ++ int i = 0; ++ ++ shost = sc->device->host; ++ sess = (struct bnx2i_sess *)sc->device->hostdata; ++ hba = sess->hba; ++ ++ printk(KERN_INFO "bnx2i: reseting host %d\n", shost->host_no); ++ ++ for (i = 0; i < hba->max_active_conns; i++) { ++ conn = bnx2i_get_conn_from_id(hba, i); ++ if (!conn) continue; ++ ++ printk(KERN_INFO "bnx2i: reseting sess %d\n", conn->ep->ep_iscsi_cid); ++ bnx2i_do_iscsi_sess_recovery(conn->sess, DID_RESET); ++ } ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_device_reset - 'eh_device_reset_handler' entry point ++ * ++ * @sc: SCSI-ML command pointer ++ * ++ * SCSI host reset handler - iSCSI session recovery ++ */ ++int bnx2i_device_reset (struct scsi_cmnd *sc) ++{ ++ struct bnx2i_sess *sess; ++ int rc = 0; ++ ++ sess = (struct bnx2i_sess *)sc->device->hostdata; ++ if (!sess || !sess->lead_conn || !sess->lead_conn->ep || ++ atomic_read(&sess->lead_conn->stop_state)) ++ return FAILED; ++ ++ printk(KERN_INFO "bnx2i: device reset, iscsi cid %d, lun %x\n", ++ sess->lead_conn->ep->ep_iscsi_cid, sc->device->lun); ++ ++ if (sc->vmkflags & VMK_FLAGS_USE_LUNRESET) { ++ /* LUN reset */ ++ printk("%s : LUN RESET request, sc %p\n", __FUNCTION__, sc); ++ rc = bnx2i_execute_tmf_cmd(sc, ISCSI_TM_FUNC_LOGICAL_UNIT_RESET); ++ } else { ++ /* TARGET reset */ ++ printk("%s : Target Reset Request, sc %p, lun %x, sess %p\n", ++ __FUNCTION__, sc, sc->device->lun, sess); ++ rc = bnx2i_execute_tmf_cmd(sc, ISCSI_TM_FUNC_TARGET_WARM_RESET); ++ } ++ return rc; ++} ++ ++#else ++/** ++ * bnx2i_host_reset - 'eh_host_reset_handler' entry point ++ * ++ * @sc: SCSI-ML command pointer ++ * ++ * SCSI host reset handler - iSCSI session recovery ++ */ ++int bnx2i_host_reset(struct scsi_cmnd *sc) ++{ ++ struct Scsi_Host *shost; ++ struct bnx2i_sess *sess; ++ int rc = 0; ++ ++ shost = sc->device->host; ++ sess = iscsi_hostdata(shost->hostdata); ++ printk(KERN_INFO "bnx2i: attempting to reset host, #%d\n", ++ sess->shost->host_no); ++ ++ BUG_ON(shost != sess->shost); ++ rc = bnx2i_do_iscsi_sess_recovery(sess, DID_RESET); ++ ++ ++ return rc; ++} ++#endif ++ ++int bnx2i_cqe_work_pending(struct bnx2i_conn *conn) ++{ ++ struct qp_info *qp; ++ volatile struct iscsi_nop_in_msg *nopin; ++ int exp_seq_no; ++ ++ qp = &conn->ep->qp; ++ nopin = (struct iscsi_nop_in_msg *)qp->cq_cons_qe; ++ ++ exp_seq_no = conn->ep->qp.cqe_exp_seq_sn; ++ if (exp_seq_no > qp->cqe_size * 2) ++ exp_seq_no -= qp->cqe_size * 2; ++ ++ if (nopin->cq_req_sn == exp_seq_no) { ++ return 1; ++ } else ++ return 0; ++} ++ ++ ++ ++static void bnx2i_process_control_pdu(struct bnx2i_sess *sess) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sess->lock, flags); ++ if (atomic_read(&sess->tmf_pending)) { ++ bnx2i_send_iscsi_tmf(sess->lead_conn, sess->scsi_tmf_cmd); ++ atomic_set(&sess->tmf_pending, 0); ++ } ++ if (atomic_read(&sess->nop_resp_pending)) { ++ bnx2i_iscsi_send_generic_request(sess->nopout_resp_cmd); ++ atomic_set(&sess->nop_resp_pending, 0); ++ } ++ if (atomic_read(&sess->login_noop_pending)) { ++ bnx2i_iscsi_send_generic_request(sess->login_nopout_cmd); ++ atomic_set(&sess->login_noop_pending, 0); ++ } ++ /* flush pending SCSI cmds before transmitting logout request */ ++ if (atomic_read(&sess->logout_pending) && ++ list_empty(&sess->pend_cmd_list)) { ++ bnx2i_iscsi_send_generic_request(sess->login_nopout_cmd); ++ atomic_set(&sess->logout_pending, 0); ++ } ++ spin_unlock_irqrestore(&sess->lock, flags); ++} ++ ++static int bnx2i_conn_transmits_pending(struct bnx2i_conn *conn) ++{ ++ struct bnx2i_sess *sess = conn->sess; ++ ++ /* If TCP connection is not active or in FFP (connection parameters updated) ++ * then do not transmit anything ++ */ ++ if (conn->ep && !(conn->ep->state & (EP_STATE_ULP_UPDATE_COMPL | ++ EP_STATE_CONNECT_COMPL))) ++ return 0; ++ ++ if ((sess->recovery_state && ++ sess->recovery_state != ISCSI_SESS_RECOVERY_COMPLETE) || ++ test_bit(ADAPTER_STATE_LINK_DOWN, &sess->hba->adapter_state) || ++ list_empty(&sess->pend_cmd_list)) ++ return 0; ++ ++ return 8; ++} ++ ++static int bnx2i_process_pend_queue(struct bnx2i_sess *sess) ++{ ++ struct bnx2i_cmd *cmd; ++ struct bnx2i_conn *conn; ++ struct bnx2i_scsi_task *scsi_task; ++ struct list_head *list; ++ struct list_head *tmp; ++ unsigned long flags; ++ int xmits_per_work; ++ int cmds_sent = 0; ++ int rc = 0; ++ ++ xmits_per_work = bnx2i_conn_transmits_pending(sess->lead_conn); ++ if (!xmits_per_work) ++ return -EAGAIN; ++ ++ if (use_poll_timer) ++ xmits_per_work = sess->sq_size; /* flush all commands in pending Q */ ++ ++ conn = sess->lead_conn; ++ spin_lock_irqsave(&sess->lock, flags); ++ list_for_each_safe(list, tmp, &sess->pend_cmd_list) { ++ /* do not post any SCSI CMDS while TMF is active */ ++ if (iscsi_cmd_win_closed(sess)) { ++ rc = -EAGAIN; ++ break; ++ } ++ ++ if (conn->ep && ((conn->ep->state == EP_STATE_TCP_FIN_RCVD) || ++ (conn->ep->state == EP_STATE_TCP_RST_RCVD))) { ++ rc = -EAGAIN; ++ break; ++ } ++ ++ scsi_task = (struct bnx2i_scsi_task *) list; ++ cmd = bnx2i_alloc_cmd(sess); ++ if (cmd == NULL) { ++ rc = -EAGAIN; ++ break; ++ } ++ ++ cmd->scsi_cmd = scsi_task->scsi_cmd; ++ sess->pend_cmd_count--; ++ list_del_init(&scsi_task->link); ++ list_add_tail(&scsi_task->link, &sess->scsi_task_list); ++ ++ cmd->conn = sess->lead_conn; ++ bnx2i_xmit_work_send_cmd(sess->lead_conn, cmd); ++ cmds_sent++; ++ if (cmds_sent >= xmits_per_work) ++ break; ++ } ++ spin_unlock_irqrestore(&sess->lock, flags); ++ ++ return rc; ++} ++ ++ ++#ifdef __VMKLNX__ ++static void bnx2i_conn_main_worker(unsigned long data) ++#else ++static void ++#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) ++bnx2i_conn_main_worker(struct work_struct *work) ++#else ++bnx2i_conn_main_worker(void *data) ++#endif /* INIT_DELAYED_WORK_DEFERRABLE && INIT_WORK_NAR */ ++#endif /* __VMKLNX__*/ ++{ ++ struct bnx2i_sess *sess; ++ int cqe_pending; ++ int defer_pendq; ++#ifndef __VMKLNX__ ++ struct Scsi_Host *shost; ++#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) ++ struct bnx2i_conn *conn = ++ container_of(work, struct bnx2i_conn, conn_worker); ++#else ++ struct bnx2i_conn *conn = (struct bnx2i_conn *)data; ++#endif ++#else /* __VMKLNX__ */ ++ struct bnx2i_conn *conn = (struct bnx2i_conn *)data; ++#endif ++ ++ if (!atomic_read(&conn->worker_enabled)) { ++ printk("WaTcH: working scheduled while disabled\n"); ++ return; ++ } ++ ++ conn->tasklet_entry++; ++ ++ sess = conn->sess; ++ ++ ++ sess->timestamp = jiffies; ++ conn->tasklet_loop = 0; ++ do { ++ ++ bnx2i_process_control_pdu(sess); ++ ++ defer_pendq = bnx2i_process_pend_queue(sess); ++ ++ if (use_poll_timer) ++ cqe_pending = bnx2i_process_new_cqes(conn, 0, ++ conn->ep->qp.cqe_size); ++ else ++ cqe_pending = bnx2i_process_new_cqes(conn, 0, ++ cmd_cmpl_per_work); ++ ++ ++ defer_pendq = bnx2i_process_pend_queue(sess); ++ ++ if (time_after(jiffies, sess->timestamp + ++ sess->worker_time_slice)) { ++ conn->tasklet_timeslice_exit++; ++ break; ++ } ++ } while (cqe_pending && !defer_pendq); ++ ++ ++ if (defer_pendq == -EAGAIN) { ++ goto tasklet_exit; ++ } ++ ++ if (bnx2i_cqe_work_pending(conn) || ++ !list_empty(&sess->pend_cmd_list)) { ++ if (atomic_read(&conn->worker_enabled)) { ++ conn->tasklet_reschedule++; ++#ifdef __VMKLNX__ ++ tasklet_schedule(&conn->conn_tasklet); ++#else ++ shost = bnx2i_conn_get_shost(conn); ++ scsi_queue_work(shost, &conn->conn_worker); ++#endif ++ } ++ } ++tasklet_exit: ++ bnx2i_arm_cq_event_coalescing(conn->ep, CNIC_ARM_CQE); ++} ++ ++static void bnx2i_xmit_work_send_cmd(struct bnx2i_conn *conn, struct bnx2i_cmd *cmd) ++{ ++ struct scsi_cmnd *sc = cmd->scsi_cmd; ++ struct bnx2i_hba *hba = conn->ep->hba; ++ struct bnx2i_sess *sess = conn->sess; ++ struct iscsi_cmd_request *req = &cmd->req; ++ ++ cmd->req.total_data_transfer_length = scsi_bufflen(sc); ++ cmd->iscsi_opcode = cmd->req.op_code = ISCSI_OP_SCSI_CMD; ++ cmd->req.cmd_sn = sess->cmdsn++; ++ ++ bnx2i_iscsi_map_sg_list(hba, cmd); ++ bnx2i_cpy_scsi_cdb(sc, cmd); ++ ++ req->op_attr = ISCSI_ATTR_SIMPLE; ++ if (sc->sc_data_direction == DMA_TO_DEVICE) { ++ req->op_attr |= ISCSI_CMD_REQUEST_WRITE; ++ req->itt |= (ISCSI_TASK_TYPE_WRITE << ++ ISCSI_CMD_REQUEST_TYPE_SHIFT); ++ bnx2i_setup_write_cmd_bd_info(cmd); ++ } else { ++ if (scsi_bufflen(sc)) ++ req->op_attr |= ISCSI_CMD_REQUEST_READ; ++ req->itt |= (ISCSI_TASK_TYPE_READ << ++ ISCSI_CMD_REQUEST_TYPE_SHIFT); ++ } ++ req->num_bds = cmd->bd_tbl->bd_valid; ++ if (!cmd->bd_tbl->bd_valid) { ++ req->bd_list_addr_lo = ++ (u32) sess->hba->mp_dma_buf.pgtbl_map; ++ req->bd_list_addr_hi = ++ (u32) ((u64) sess->hba->mp_dma_buf.pgtbl_map >> 32); ++ req->num_bds = 1; ++ } ++ ++ atomic_set(&cmd->cmd_state, ISCSI_CMD_STATE_INITIATED); ++ sc->SCp.ptr = (char *) cmd; ++ ++ if (req->itt != ITT_INVALID_SIGNATURE) { ++ list_add_tail(&cmd->link, &sess->active_cmd_list); ++ sess->active_cmd_count++; ++ bnx2i_send_iscsi_scsicmd(conn, cmd); ++ } ++} ++ ++/********************************************************************** ++ * open-iscsi interface ++ **********************************************************************/ ++ ++/** ++ * bnx2i_alloc_scsi_host_template - ++ * ++ * allocates memory for SCSI host template, iSCSI template and registers ++ * this instance of NX2 device with iSCSI transport kernel module. ++ */ ++static struct scsi_host_template * ++bnx2i_alloc_scsi_host_template(struct bnx2i_hba *hba, struct cnic_dev *cnic) ++{ ++ void *mem_ptr; ++#ifndef __VMKLNX__ ++ u32 pci_bus_no; ++ u32 pci_dev_no; ++ u32 pci_func_no; ++ u32 extra; ++ struct ethtool_drvinfo drv_info; ++#endif ++ struct scsi_host_template *scsi_template; ++ int mem_size; ++ ++ mem_size = sizeof(struct scsi_host_template); ++ scsi_template = kmalloc(sizeof(struct scsi_host_template), GFP_KERNEL); ++ if (!scsi_template) { ++ printk(KERN_ALERT "bnx2i: failed to alloc memory for sht\n"); ++ return NULL; ++ } ++ ++ mem_ptr = kmalloc(BRCM_ISCSI_XPORT_NAME_SIZE_MAX, GFP_KERNEL); ++ if (mem_ptr == NULL) { ++ printk(KERN_ALERT "failed to alloc memory for xport name\n"); ++ goto scsi_name_mem_err; ++ } ++ ++ memcpy(scsi_template, (const void *) &bnx2i_host_template, ++ sizeof(struct scsi_host_template)); ++ scsi_template->name = mem_ptr; ++ memcpy((void *) scsi_template->name, ++ (const void *) bnx2i_host_template.name, ++ strlen(bnx2i_host_template.name) + 1); ++ ++ mem_ptr = kmalloc(BRCM_ISCSI_XPORT_NAME_SIZE_MAX, GFP_KERNEL); ++ if (mem_ptr == NULL) { ++ printk(KERN_ALERT "failed to alloc proc name mem\n"); ++ goto scsi_proc_name_mem_err; ++ } ++ ++ scsi_template->proc_name = mem_ptr; ++ /* Can't determine device type, 5706/5708 has 40-bit dma addr limit */ ++ if (test_bit(BNX2I_NX2_DEV_5706, &hba->cnic_dev_type) || ++ test_bit(BNX2I_NX2_DEV_5708, &hba->cnic_dev_type)) ++ scsi_template->dma_boundary = DMA_40BIT_MASK; ++ else ++ scsi_template->dma_boundary = DMA_64BIT_MASK; ++ ++ scsi_template->can_queue = hba->max_sqes; ++ scsi_template->cmd_per_lun = scsi_template->can_queue / 2; ++ ++ if (cnic && cnic->netdev) { ++#ifndef __VMKLNX__ ++ cnic->netdev->ethtool_ops->get_drvinfo(cnic->netdev, ++ &drv_info); ++ sscanf(drv_info.bus_info, "%x:%x:%x.%d", &extra, ++ &pci_bus_no, &pci_dev_no, &pci_func_no); ++ ++ sprintf(mem_ptr, "%s-%.2x%.2x%.2x", BRCM_ISCSI_XPORT_NAME_PREFIX, ++ (u8)pci_bus_no, (u8)pci_dev_no, (u8)pci_func_no); ++#else ++ sprintf(mem_ptr, "%s-%s", BRCM_ISCSI_XPORT_NAME_PREFIX, cnic->netdev->name); ++#endif ++ } ++ ++ return scsi_template; ++ ++scsi_proc_name_mem_err: ++ kfree(scsi_template->name); ++scsi_name_mem_err: ++ kfree(scsi_template); ++ printk(KERN_ALERT "bnx2i: failed to allocate scsi host template\n"); ++ return NULL; ++} ++ ++ ++ ++static void bnx2i_free_scsi_host_template(struct scsi_host_template *scsi_template) ++{ ++ kfree(scsi_template->proc_name); ++ kfree(scsi_template->name); ++ kfree(scsi_template); ++} ++ ++ ++/** ++ * bnx2i_alloc_iscsi_transport - ++ * ++ * allocates memory for SCSI host template, iSCSI template and registers ++ * this instance of NX2 device with iSCSI transport kernel module. ++ */ ++static struct iscsi_transport * ++bnx2i_alloc_iscsi_transport(struct bnx2i_hba *hba, struct cnic_dev *cnic, ++ struct scsi_host_template *scsi_template) ++{ ++ void *mem_ptr; ++ struct iscsi_transport *iscsi_transport; ++ int mem_size; ++ ++ mem_size = sizeof(struct iscsi_transport); ++ iscsi_transport = kmalloc(sizeof(struct iscsi_transport), GFP_KERNEL); ++ if (!iscsi_transport) { ++ printk(KERN_ALERT "mem error for iscsi_transport template\n"); ++ goto iscsi_xport_err; ++ } ++ ++ memcpy((void *) iscsi_transport, (const void *) &bnx2i_iscsi_transport, ++ sizeof(struct iscsi_transport)); ++ ++ iscsi_transport->host_template = scsi_template; ++ ++ mem_ptr = kmalloc(BRCM_ISCSI_XPORT_NAME_SIZE_MAX, GFP_KERNEL); ++ if (mem_ptr == NULL) { ++ printk(KERN_ALERT "mem alloc error, iscsi xport name\n"); ++ goto xport_name_mem_err; ++ } ++ ++ iscsi_transport->name = mem_ptr; ++ ++ memcpy((void *) mem_ptr, (const void *) scsi_template->proc_name, ++ strlen(scsi_template->proc_name) + 1); ++ ++#ifdef __VMKLNX__ ++ if (test_bit(BNX2I_NX2_DEV_57710, &hba->cnic_dev_type)) ++ iscsi_transport->get_transport_limit = bnx2i_get_5771x_limit; ++ else ++ iscsi_transport->get_transport_limit = bnx2i_get_570x_limit; ++#endif ++ return iscsi_transport; ++ ++xport_name_mem_err: ++ kfree(iscsi_transport); ++iscsi_xport_err: ++ printk(KERN_ALERT "bnx2i : unable to allocate iscsi transport\n"); ++ return NULL; ++} ++ ++ ++ ++static void bnx2i_free_iscsi_transport(struct iscsi_transport *iscsi_transport) ++{ ++ kfree(iscsi_transport->name); ++ kfree(iscsi_transport); ++} ++ ++ ++/** ++ * bnx2i_register_xport - register a bnx2i device transport name with ++ * the iscsi transport module ++ * ++ * @hba: pointer to adapter instance ++ * ++ * allocates memory for SCSI host template, iSCSI template and registers ++ * this instance of NX2 device with iSCSI transport kernel module. ++ */ ++int bnx2i_register_xport(struct bnx2i_hba *hba) ++{ ++#ifdef __VMKLNX__ ++ struct vmk_ScsiAdapter *vmk_adapter; ++ struct vmklnx_ScsiAdapter *vmklnx_adapter; ++ ++ if (hba->shost_template) ++ return -EEXIST; ++ ++ if (!test_bit(CNIC_F_IF_UP, &hba->cnic->flags) || ++ !hba->cnic->max_iscsi_conn) ++ return -EINVAL; ++#endif ++ ++ hba->shost_template = iscsi_register_transport(hba->iscsi_transport); ++ if (!hba->shost_template) { ++ printk(KERN_ALERT "bnx2i: xport reg failed, hba 0x%p\n", hba); ++ goto failed_registration; ++ } ++ printk(KERN_ALERT "bnx2i: netif=%s, iscsi=%s\n", ++ hba->cnic->netdev->name, hba->scsi_template->proc_name); ++ ++#ifdef __VMKLNX__ ++ hba->shost->transportt = hba->shost_template; ++ device_initialize(&hba->vm_pcidev); ++ if (scsi_add_host(hba->shost, &hba->vm_pcidev)) ++ goto host_add_err; ++ ++ vmklnx_adapter = (struct vmklnx_ScsiAdapter *)hba->shost->adapter; ++ vmk_adapter = (struct vmk_ScsiAdapter *)vmklnx_adapter->vmkAdapter; ++ vmk_adapter->paeCapable = TRUE; ++ ++ iscsi_register_host(hba->shost, hba->iscsi_transport); ++#endif ++ ++ return 0; ++ ++#ifdef __VMKLNX__ ++host_add_err: ++#endif ++ iscsi_unregister_transport(hba->iscsi_transport); ++failed_registration: ++ return -ENOMEM; ++} ++ ++/** ++ * bnx2i_deregister_xport - unregisters bnx2i adapter's iscsi transport name ++ * ++ * @hba: pointer to adapter instance ++ * ++ * de-allocates memory for SCSI host template, iSCSI template and de-registers ++ * a NX2 device instance ++ */ ++int bnx2i_deregister_xport(struct bnx2i_hba *hba) ++{ ++#ifdef __VMKLNX__ ++ if (hba->shost_template) { ++#endif /* __VMKLNX__ */ ++ iscsi_unregister_transport(hba->iscsi_transport); ++ hba->shost_template = NULL; ++#ifdef __VMKLNX__ ++ } ++#endif /* __VMKLNX__ */ ++ return 0; ++} ++ ++ ++int bnx2i_free_iscsi_scsi_template(struct bnx2i_hba *hba) ++{ ++ kfree(hba->scsi_template->proc_name); ++ kfree(hba->scsi_template->name); ++ hba->scsi_template->name = NULL; ++ ++ kfree(hba->scsi_template); ++ hba->scsi_template = NULL; ++ ++ kfree(hba->iscsi_transport->name); ++ hba->iscsi_transport->name = NULL; ++ ++ kfree(hba->iscsi_transport); ++ hba->iscsi_transport = NULL; ++ ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_session_create - create a new iscsi session ++ * ++ * @it: iscsi transport pointer ++ * @scsit: scsi transport template pointer ++ * @cmds_max: max commands supported ++ * @qdepth: scsi queue depth to support ++ * @initial_cmdsn: initial iscsi CMDSN to be used for this session ++ * @host_no: pointer to u32 to return host no ++ * ++ * Creates a new iSCSI session instance on given device. ++ */ ++#ifdef __VMKLNX__ ++#define _CREATE_SESS_NEW_ 1 ++#endif ++ ++struct iscsi_cls_session * ++ bnx2i_session_create(struct iscsi_transport *it, ++ struct scsi_transport_template *scsit, ++#ifdef _CREATE_SESS_NEW_ ++ uint16_t cmds_max, uint16_t qdepth, ++#endif ++ uint32_t initial_cmdsn, ++#ifdef __VMKLNX__ ++ uint32_t target_id, uint32_t channel_id, ++#endif ++ uint32_t *host_no) ++{ ++ struct bnx2i_hba *hba; ++ struct bnx2i_sess *sess; ++ struct Scsi_Host *shost; ++ struct iscsi_cls_session *cls_session; ++ int ret_code; ++ ++#ifdef __VMKLNX__ ++ printk("%s: tgt id %d, ch id %d, cmds_max %d\n", ++ __FUNCTION__, target_id, channel_id, cmds_max); ++#endif ++ hba = bnx2i_get_hba_from_template(scsit); ++ if (bnx2i_adapter_ready(hba)) ++ return NULL; ++ ++#ifdef __VMKLNX__ ++ shost = hba->shost; ++ if (!shost) ++ return NULL; ++ ++ cls_session = iscsi_create_session(shost, it, target_id, channel_id); ++ if (!cls_session) ++ return NULL; ++ ++ sess = cls_session->dd_data; ++#else ++ shost = scsi_host_alloc(hba->iscsi_transport->host_template, ++ hostdata_privsize(sizeof(struct bnx2i_sess))); ++ if (!shost) ++ return NULL; ++ ++ shost->max_id = 1; ++ shost->max_channel = 1; ++ shost->max_lun = hba->iscsi_transport->max_lun; ++ shost->max_cmd_len = hba->iscsi_transport->max_cmd_len; ++#ifdef _NEW_CREATE_SESSION_ ++ if (cmds_max) ++ shost->can_queue = cmds_max; ++ if (qdepth) ++ shost->cmd_per_lun = qdepth; ++#endif /* _NEW_CREATE_SESSION_ */ ++ shost->transportt = scsit; ++ shost->transportt->create_work_queue = 1; ++ sess = iscsi_hostdata(shost->hostdata); ++#endif /* __VMKLNX__ */ ++ *host_no = shost->host_no; ++ ++ if (!sess) ++ goto sess_resc_fail; ++ ++ memset(sess, 0, sizeof(struct bnx2i_sess)); ++ sess->hba = hba; ++#ifdef __VMKLNX__ ++ sess->cls_sess = cls_session; ++#else ++ sess->shost = shost; ++#endif ++ ++ /* ++ * For Open-iSCSI, only normal sessions go through bnx2i. ++ * Discovery session goes through host stack TCP/IP stack. ++ */ ++ ret_code = bnx2i_iscsi_sess_new(hba, sess); ++ if (ret_code) { ++ /* failed to allocate memory */ ++ printk(KERN_ALERT "bnx2i_sess_create: unable to alloc sess\n"); ++ goto sess_resc_fail; ++ } ++ ++ /* Update CmdSN related parameters */ ++ sess->cmdsn = initial_cmdsn; ++ sess->exp_cmdsn = initial_cmdsn + 1; ++ sess->max_cmdsn = initial_cmdsn + 1; ++ ++#ifndef __VMKLNX__ ++ if (scsi_add_host(shost, NULL)) ++ goto add_sh_fail; ++ ++ if (!try_module_get(it->owner)) ++ goto cls_sess_falied; ++ ++ cls_session = iscsi_create_session(shost, it, 0); ++ if (!cls_session) ++ goto module_put; ++ *(unsigned long *)shost->hostdata = (unsigned long)cls_session; ++ ++ return hostdata_session(shost->hostdata); ++#else ++ return cls_session; ++#endif ++ ++#ifndef __VMKLNX__ ++module_put: ++ module_put(it->owner); ++cls_sess_falied: ++ scsi_remove_host(shost); ++add_sh_fail: ++ bnx2i_iscsi_sess_release(hba, sess); ++#endif ++sess_resc_fail: ++#ifndef __VMKLNX__ ++ scsi_host_put(shost); ++#endif ++ return NULL; ++} ++ ++ ++#ifdef __VMKLNX__ ++struct iscsi_cls_session * ++bnx2i_session_create_vmp(struct iscsi_transport *it, ++ void *scsi_templ, ++#ifdef _CREATE_SESS_NEW_ ++ uint16_t cmds_max, uint16_t qdepth, ++#endif ++ uint32_t initial_cmdsn, ++ uint32_t target_id, uint32_t channel_id, ++ uint32_t *host_no) ++{ ++ struct scsi_transport_template *scsit = scsi_templ; ++ ++ return bnx2i_session_create(it, scsit, ++#ifdef _CREATE_SESS_NEW_ ++ cmds_max, qdepth, ++#endif ++ initial_cmdsn, target_id, channel_id, host_no); ++} ++ ++ ++struct iscsi_cls_session * ++ bnx2i_session_create_vm(struct iscsi_transport *it, ++ struct scsi_transport_template *scsit, ++#ifdef _CREATE_SESS_NEW_ ++ uint16_t cmds_max, uint16_t qdepth, ++#endif ++ uint32_t initial_cmdsn, ++ uint32_t *host_no) ++{ ++ struct bnx2i_hba *hba = bnx2i_get_hba_from_template(scsit); ++ ++ if (!hba) ++ return NULL; ++ return bnx2i_session_create(it, scsit, ++#ifdef _CREATE_SESS_NEW_ ++ cmds_max, qdepth, ++#endif ++ initial_cmdsn, hba->target_id++, hba->channel_id, host_no); ++} ++#endif ++ ++ ++static void bnx2i_release_session_resc(struct iscsi_cls_session *cls_session) ++{ ++#ifdef __VMKLNX__ ++ struct bnx2i_sess *sess = cls_session->dd_data; ++#else ++ struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); ++ struct bnx2i_sess *sess = iscsi_hostdata(shost->hostdata); ++ struct module *owner = cls_session->transport->owner; ++#endif ++ ++ bnx2i_iscsi_sess_release(sess->hba, sess); ++ ++ kfree(sess->target_name); ++ sess->target_name = NULL; ++ ++ iscsi_free_session(cls_session); ++#ifndef __VMKLNX__ ++ scsi_host_put(shost); ++ module_put(owner); ++#endif ++} ++ ++/** ++ * bnx2i_session_destroy - destroys iscsi session ++ * ++ * @cls_session: pointer to iscsi cls session ++ * ++ * Destroys previously created iSCSI session instance and releases ++ * all resources held by it ++ */ ++ ++void bnx2i_session_destroy(struct iscsi_cls_session *cls_session) ++{ ++#ifdef __VMKLNX__ ++ struct bnx2i_sess *sess = cls_session->dd_data; ++#else ++ struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); ++ struct bnx2i_sess *sess = iscsi_hostdata(shost->hostdata); ++#endif ++ ++ bnx2i_withdraw_sess_recovery(sess); ++ ++ iscsi_remove_session(cls_session); ++#ifndef __VMKLNX__ ++ scsi_remove_host(shost); ++ bnx2i_release_session_resc(cls_session); ++#else ++ if (sess->state == BNX2I_SESS_TARGET_DESTROYED) ++ bnx2i_release_session_resc(cls_session); ++ else ++ sess->state = BNX2I_SESS_DESTROYED; ++#endif ++} ++ ++/** ++ * bnx2i_sess_recovery_timeo - session recovery timeout handler ++ * ++ * @cls_session: pointer to iscsi cls session ++ * ++ * session recovery timeout handling routine ++ */ ++void bnx2i_sess_recovery_timeo(struct iscsi_cls_session *cls_session) ++{ ++#ifdef __VMKLNX__ ++ struct bnx2i_sess *sess = cls_session->dd_data; ++#else ++ struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); ++ struct bnx2i_sess *sess = iscsi_hostdata(shost->hostdata); ++#endif ++ ++ printk("%s: sess %p recovery timed out\n", __FUNCTION__, sess); ++#ifdef __VMKLNX__ ++ iscsi_offline_session(sess->cls_sess); ++#else ++ spin_lock_bh(&sess->lock); ++ sess->recovery_state |= ISCSI_SESS_RECOVERY_FAILED; ++ spin_unlock_bh(&sess->lock); ++ wake_up(&sess->er_wait); ++#endif ++} ++ ++ ++/** ++ * bnx2i_conn_create - create iscsi connection instance ++ * ++ * @cls_session: pointer to iscsi cls session ++ * @cid: iscsi cid as per rfc (not NX2's CID terminology) ++ * ++ * Creates a new iSCSI connection instance for a given session ++ */ ++struct iscsi_cls_conn *bnx2i_conn_create(struct iscsi_cls_session *cls_session, ++ uint32_t cid) ++{ ++#ifdef __VMKLNX__ ++ struct bnx2i_sess *sess = cls_session->dd_data; ++#else ++ struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); ++ struct bnx2i_sess *sess = iscsi_hostdata(shost->hostdata); ++#endif ++ struct bnx2i_conn *conn; ++ struct iscsi_cls_conn *cls_conn; ++ ++ cls_conn = iscsi_create_conn(cls_session, cid); ++ if (!cls_conn) ++ return NULL; ++ ++ conn = cls_conn->dd_data; ++ memset(conn, 0, sizeof(struct bnx2i_conn)); ++ conn->cls_conn = cls_conn; ++ conn->exp_statsn = STATSN_UPDATE_SIGNATURE; ++ conn->state = CONN_STATE_IDLE; ++ /* Initialize the connection structure */ ++ if (bnx2i_iscsi_conn_new(sess, conn)) ++ goto mem_err; ++ ++ conn->conn_cid = cid; ++ return cls_conn; ++ ++mem_err: ++ iscsi_destroy_conn(cls_conn); ++ return NULL; ++} ++ ++ ++/** ++ * bnx2i_conn_bind - binds iscsi sess, conn and ep objects together ++ * ++ * @cls_session: pointer to iscsi cls session ++ * @cls_conn: pointer to iscsi cls conn ++ * @transport_fd: 64-bit EP handle ++ * @is_leading: leading connection on this session? ++ * ++ * Binds together iSCSI session instance, iSCSI connection instance ++ * and the TCP connection. This routine returns error code if ++ * TCP connection does not belong on the device iSCSI sess/conn ++ * is bound ++ */ ++#ifdef __VMKLNX__ ++vmk_int32 bnx2i_conn_bind(struct iscsi_cls_session *cls_session, ++ struct iscsi_cls_conn *cls_conn, ++ vmk_uint64 transport_fd, vmk_int32 is_leading) ++#else ++int bnx2i_conn_bind(struct iscsi_cls_session *cls_session, ++ struct iscsi_cls_conn *cls_conn, ++ uint64_t transport_fd, int is_leading) ++#endif ++{ ++#ifdef __VMKLNX__ ++ struct bnx2i_sess *sess; ++ struct Scsi_Host *shost; ++ unsigned long flags; ++#else ++ struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); ++ struct bnx2i_sess *sess = iscsi_hostdata(shost->hostdata); ++#endif ++ struct bnx2i_conn *tmp; ++ struct bnx2i_conn *conn; ++ int ret_code; ++ struct bnx2i_endpoint *ep; ++ ++#ifdef __VMKLNX__ ++ sess = cls_session->dd_data; ++ shost = bnx2i_sess_get_shost(sess); ++#endif ++ conn = cls_conn->dd_data; ++ ep = (struct bnx2i_endpoint *) (unsigned long) transport_fd; ++ ++ if ((ep->state == EP_STATE_TCP_FIN_RCVD) || ++ (ep->state == EP_STATE_TCP_RST_RCVD)) ++ /* Peer disconnect via' FIN or RST */ ++ return -EINVAL; ++ ++ if (ep->hba != sess->hba) { ++ /* Error - TCP connection does not belong to this device ++ */ ++ printk(KERN_ALERT "bnx2i: conn bind, ep=0x%p (%s) does not", ++ ep, ep->hba->netdev->name); ++ printk(KERN_ALERT "belong to hba (%s)\n", ++ sess->hba->netdev->name); ++ return -EEXIST; ++ } ++ ++#ifdef __VMKLNX__ ++ spin_lock_irqsave(ep->hba->shost->host_lock, flags); ++#endif ++ if (!sess->login_nopout_cmd) ++ sess->login_nopout_cmd = bnx2i_alloc_cmd(sess); ++ if (!sess->scsi_tmf_cmd) ++ sess->scsi_tmf_cmd = bnx2i_alloc_cmd(sess); ++ if (!sess->nopout_resp_cmd) ++ sess->nopout_resp_cmd = bnx2i_alloc_cmd(sess); ++#ifdef __VMKLNX__ ++ spin_unlock_irqrestore(ep->hba->shost->host_lock, flags); ++#endif ++ ++ /* adjust dma boundary limit which was set to lower bound of 40-bit ++ * address as required by 5706/5708. 5709/57710 does not have any ++ * address limitation requirements. 'dma_mask' parameter is set ++ * by bnx2 module based on device requirements, we just use whatever ++ * is set. ++ */ ++ shost->dma_boundary = ep->hba->pcidev->dma_mask; ++ ++ /* look-up for existing connection, MC/S is not currently supported */ ++ spin_lock_bh(&sess->lock); ++ tmp = NULL; ++ if (!list_empty(&sess->conn_list)) { ++ list_for_each_entry(tmp, &sess->conn_list, link) { ++ if (tmp == conn) ++ break; ++ } ++ } ++ if ((tmp != conn) && (conn->sess == sess)) { ++ /* bind iSCSI connection to this session */ ++ list_add(&conn->link, &sess->conn_list); ++ if (is_leading) ++ sess->lead_conn = conn; ++ } ++ ++ if (conn->ep) { ++ /* This happens when 'iscsid' is killed and restarted. Daemon ++ * has no clue of tranport handle, but knows active conn/sess ++ * and tried to rebind a new tranport (EP) to already active ++ * iSCSI session/connection ++ */ ++ spin_unlock_bh(&sess->lock); ++ bnx2i_ep_disconnect((uint64_t) (unsigned long) conn->ep); ++ spin_lock_bh(&sess->lock); ++ } ++ ++ conn->ep = (struct bnx2i_endpoint *) (unsigned long) transport_fd; ++ conn->ep->conn = conn; ++ conn->ep->sess = sess; ++ conn->state = CONN_STATE_XPORT_READY; ++ conn->iscsi_conn_cid = conn->ep->ep_iscsi_cid; ++ conn->fw_cid = conn->ep->ep_cid; ++ ++ ret_code = bnx2i_bind_conn_to_iscsi_cid(conn, ep->ep_iscsi_cid); ++ spin_unlock_bh(&sess->lock); ++ ++ /* 5706/5708/5709 FW takes RQ as full when initiated, but for 57710 ++ * driver needs to explicitly replenish RQ index during setup. ++ */ ++ if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) ++ bnx2i_put_rq_buf(conn, 0); ++ ++ atomic_set(&conn->worker_enabled, 1); ++ bnx2i_arm_cq_event_coalescing(conn->ep, CNIC_ARM_CQE); ++ return ret_code; ++} ++ ++ ++/** ++ * bnx2i_conn_destroy - destroy iscsi connection instance & release resources ++ * ++ * @cls_conn: pointer to iscsi cls conn ++ * ++ * Destroy an iSCSI connection instance and release memory resources held by ++ * this connection ++ */ ++void bnx2i_conn_destroy(struct iscsi_cls_conn *cls_conn) ++{ ++ struct bnx2i_conn *conn = cls_conn->dd_data; ++ struct bnx2i_sess *sess = conn->sess; ++ struct Scsi_Host *shost; ++ shost = bnx2i_conn_get_shost(conn); ++ ++ bnx2i_conn_free_login_resources(conn->sess->hba, conn); ++ ++ spin_lock_bh(&sess->lock); ++ list_del_init(&conn->link); ++ if (sess->lead_conn == conn) ++ sess->lead_conn = NULL; ++ ++ if (conn->ep) { ++ printk("bnx2i: conn_destroy - conn %p, ep %p\n", conn, conn->ep); ++ conn->ep->conn = NULL; ++ conn->ep = NULL; ++ } ++ ++ atomic_set(&conn->worker_enabled, 0); ++ spin_unlock_bh(&sess->lock); ++#ifdef __VMKLNX__ ++ tasklet_disable(&conn->conn_tasklet); ++#else ++ scsi_flush_work(shost); ++#endif /* __VMKLNX__ */ ++ ++ kfree(conn->persist_address); ++ conn->persist_address = NULL; ++ iscsi_destroy_conn(cls_conn); ++} ++ ++ ++/** ++ * bnx2i_conn_set_param - set iscsi connection parameter ++ * ++ * @cls_conn: pointer to iscsi cls conn ++ * @param: parameter type identifier ++ * @buf: buffer pointer ++ * @buflen: buffer length ++ * ++ * During FFP migration, user daemon will issue this call to ++ * update negotiated iSCSI parameters to driver. ++ */ ++#ifdef __VMKLNX__ ++vmk_int32 bnx2i_conn_set_param(struct iscsi_cls_conn *cls_conn, ++ enum iscsi_param param, vmk_int8 *buf, ++ vmk_int32 buflen) ++#else ++int bnx2i_conn_set_param(struct iscsi_cls_conn *cls_conn, ++ enum iscsi_param param, char *buf, int buflen) ++#endif ++{ ++ struct bnx2i_conn *conn = cls_conn->dd_data; ++ struct bnx2i_sess *sess = conn->sess; ++ int ret_val = 0; ++ ++ spin_lock_bh(&sess->lock); ++ if (conn->state != CONN_STATE_IN_LOGIN) { ++ printk(KERN_ERR "bnx2i: can't change param [%d]\n", param); ++ spin_unlock_bh(&sess->lock); ++ return -1; ++ } ++ spin_unlock_bh(&sess->lock); ++ switch (param) { ++ case ISCSI_PARAM_MAX_RECV_DLENGTH: ++ sscanf(buf, "%d", &conn->max_data_seg_len_recv); ++ break; ++ case ISCSI_PARAM_MAX_XMIT_DLENGTH: ++ sscanf(buf, "%d", &conn->max_data_seg_len_xmit); ++ break; ++ case ISCSI_PARAM_HDRDGST_EN: ++ sscanf(buf, "%d", &conn->header_digest_en); ++ break; ++ case ISCSI_PARAM_DATADGST_EN: ++ sscanf(buf, "%d", &conn->data_digest_en); ++ break; ++ case ISCSI_PARAM_INITIAL_R2T_EN: ++ if (conn == sess->lead_conn) ++ sscanf(buf, "%d", &sess->initial_r2t); ++ break; ++ case ISCSI_PARAM_MAX_R2T: ++ if (conn == sess->lead_conn) ++ sscanf(buf, "%d", &sess->max_r2t); ++ break; ++ case ISCSI_PARAM_IMM_DATA_EN: ++ if (conn == sess->lead_conn) ++ sscanf(buf, "%d", &sess->imm_data); ++ break; ++ case ISCSI_PARAM_FIRST_BURST: ++ if (conn == sess->lead_conn) ++ sscanf(buf, "%d", &sess->first_burst_len); ++ break; ++ case ISCSI_PARAM_MAX_BURST: ++ if (conn == sess->lead_conn) ++ sscanf(buf, "%d", &sess->max_burst_len); ++ break; ++ case ISCSI_PARAM_PDU_INORDER_EN: ++ if (conn == sess->lead_conn) ++ sscanf(buf, "%d", &sess->pdu_inorder); ++ break; ++ case ISCSI_PARAM_DATASEQ_INORDER_EN: ++ if (conn == sess->lead_conn) ++ sscanf(buf, "%d", &sess->dataseq_inorder); ++ break; ++ case ISCSI_PARAM_ERL: ++ if (conn == sess->lead_conn) ++ sscanf(buf, "%d", &sess->erl); ++ break; ++ case ISCSI_PARAM_IFMARKER_EN: ++ sscanf(buf, "%d", &conn->ifmarker_enable); ++ BUG_ON(conn->ifmarker_enable); ++ break; ++ case ISCSI_PARAM_OFMARKER_EN: ++ sscanf(buf, "%d", &conn->ofmarker_enable); ++ BUG_ON(conn->ofmarker_enable); ++ break; ++ case ISCSI_PARAM_EXP_STATSN: ++ sscanf(buf, "%u", &conn->exp_statsn); ++ break; ++ case ISCSI_PARAM_TARGET_NAME: ++ if (sess->target_name) ++ break; ++ sess->target_name = kstrdup(buf, GFP_KERNEL); ++ if (!sess->target_name) ++ ret_val = -ENOMEM; ++ break; ++ case ISCSI_PARAM_TPGT: ++ sscanf(buf, "%d", &sess->tgt_prtl_grp); ++ break; ++ case ISCSI_PARAM_PERSISTENT_PORT: ++ sscanf(buf, "%d", &conn->persist_port); ++ break; ++ case ISCSI_PARAM_PERSISTENT_ADDRESS: ++ if (conn->persist_address) ++ break; ++ conn->persist_address = kstrdup(buf, GFP_KERNEL); ++ if (!conn->persist_address) ++ ret_val = -ENOMEM; ++ break; ++#ifdef __VMKLNX__ ++ case ISCSI_PARAM_ISID: ++ snprintf(sess->isid, sizeof(sess->isid), "%s", buf); ++ break; ++#endif ++ default: ++ printk(KERN_ALERT "PARAM_UNKNOWN: 0x%x\n", param); ++ ret_val = -ENOSYS; ++ break; ++ } ++ ++ return ret_val; ++} ++ ++ ++/** ++ * bnx2i_conn_get_param - return iscsi connection parameter to caller ++ * ++ * @cls_conn: pointer to iscsi cls conn ++ * @param: parameter type identifier ++ * @buf: buffer pointer ++ * ++ * returns iSCSI connection parameters ++ */ ++#ifdef __VMKLNX__ ++vmk_int32 bnx2i_conn_get_param(struct iscsi_cls_conn *cls_conn, ++ enum iscsi_param param, vmk_int8 *buf) ++#else ++int bnx2i_conn_get_param(struct iscsi_cls_conn *cls_conn, ++ enum iscsi_param param, char *buf) ++#endif ++{ ++ struct bnx2i_conn *conn; ++ int len; ++ ++ conn = (struct bnx2i_conn *)cls_conn->dd_data; ++ if (!conn) ++ return -EINVAL; ++#ifndef __VMKLNX__ ++ if (!conn->ep || (conn->ep->state != EP_STATE_ULP_UPDATE_COMPL)) ++ return -EINVAL; ++#endif ++ ++ len = 0; ++ switch (param) { ++ case ISCSI_PARAM_MAX_RECV_DLENGTH: ++ len = sprintf(buf, "%u\n", conn->max_data_seg_len_recv); ++ break; ++ case ISCSI_PARAM_MAX_XMIT_DLENGTH: ++ len = sprintf(buf, "%u\n", conn->max_data_seg_len_xmit); ++ break; ++ case ISCSI_PARAM_HDRDGST_EN: ++ len = sprintf(buf, "%d\n", conn->header_digest_en); ++ break; ++ case ISCSI_PARAM_DATADGST_EN: ++ len = sprintf(buf, "%d\n", conn->data_digest_en); ++ break; ++ case ISCSI_PARAM_IFMARKER_EN: ++ len = sprintf(buf, "%u\n", conn->ifmarker_enable); ++ break; ++ case ISCSI_PARAM_OFMARKER_EN: ++ len = sprintf(buf, "%u\n", conn->ofmarker_enable); ++ break; ++ case ISCSI_PARAM_EXP_STATSN: ++ len = sprintf(buf, "%u\n", conn->exp_statsn); ++ break; ++ case ISCSI_PARAM_PERSISTENT_PORT: ++ len = sprintf(buf, "%d\n", conn->persist_port); ++ break; ++ case ISCSI_PARAM_PERSISTENT_ADDRESS: ++ if (conn->persist_address) ++ len = sprintf(buf, "%s\n", conn->persist_address); ++ break; ++ case ISCSI_PARAM_CONN_PORT: ++ if (conn->ep) ++ len = sprintf(buf, "%u\n", ++ (uint32_t)(be16_to_cpu((__be32)conn->ep->cm_sk->dst_port))); ++ else ++ len = sprintf(buf, "0\n"); ++ break; ++ case ISCSI_PARAM_CONN_ADDRESS: ++ if (conn->ep) ++ len = sprintf(buf, NIPQUAD_FMT "\n", ++ NIPQUAD(conn->ep->cm_sk->dst_ip)); ++ else ++ len = sprintf(buf, "0.0.0.0\n"); ++ break; ++ default: ++ printk(KERN_ALERT "get_param: conn 0x%p param %d not found\n", ++ conn, (u32)param); ++ len = -ENOSYS; ++ } ++#ifdef __VMKLNX__ ++ if (len > 0) ++ buf[len - 1] = '\0'; ++#endif ++ ++ return len; ++} ++ ++ ++/** ++ * bnx2i_session_get_param - returns iscsi session parameter ++ * ++ * @cls_session: pointer to iscsi cls session ++ * @param: parameter type identifier ++ * @buf: buffer pointer ++ * ++ * returns iSCSI session parameters ++ */ ++#ifdef __VMKLNX__ ++vmk_int32 bnx2i_session_get_param(struct iscsi_cls_session *cls_session, ++ enum iscsi_param param, vmk_int8 *buf) ++#else ++int bnx2i_session_get_param(struct iscsi_cls_session *cls_session, ++ enum iscsi_param param, char *buf) ++#endif ++{ ++#ifdef __VMKLNX__ ++ struct bnx2i_sess *sess = cls_session->dd_data; ++#else ++ struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); ++ struct bnx2i_sess *sess = iscsi_hostdata(shost->hostdata); ++#endif ++ int len = 0; ++ ++ switch (param) { ++ case ISCSI_PARAM_INITIAL_R2T_EN: ++ len = sprintf(buf, "%d\n", sess->initial_r2t); ++ break; ++ case ISCSI_PARAM_MAX_R2T: ++ len = sprintf(buf, "%hu\n", sess->max_r2t); ++ break; ++ case ISCSI_PARAM_IMM_DATA_EN: ++ len = sprintf(buf, "%d\n", sess->imm_data); ++ break; ++ case ISCSI_PARAM_FIRST_BURST: ++ len = sprintf(buf, "%u\n", sess->first_burst_len); ++ break; ++ case ISCSI_PARAM_MAX_BURST: ++ len = sprintf(buf, "%u\n", sess->max_burst_len); ++ break; ++ case ISCSI_PARAM_PDU_INORDER_EN: ++ len = sprintf(buf, "%d\n", sess->pdu_inorder); ++ break; ++ case ISCSI_PARAM_DATASEQ_INORDER_EN: ++ len = sprintf(buf, "%d\n", sess->dataseq_inorder); ++ break; ++ case ISCSI_PARAM_ERL: ++ len = sprintf(buf, "%d\n", sess->erl); ++ break; ++ case ISCSI_PARAM_TARGET_NAME: ++ if (sess->target_name) ++ len = sprintf(buf, "%s\n", sess->target_name); ++ break; ++ case ISCSI_PARAM_TPGT: ++ len = sprintf(buf, "%d\n", sess->tgt_prtl_grp); ++ break; ++#ifdef __VMKLNX__ ++ case ISCSI_PARAM_ISID: ++ len = sprintf(buf,"%s\n", sess->isid); ++ break; ++#endif ++ default: ++ printk(KERN_ALERT "sess_get_param: sess 0x%p", sess); ++ printk(KERN_ALERT "param (0x%x) not found\n", (u32) param); ++ return -ENOSYS; ++ } ++ ++#ifdef __VMKLNX__ ++ if (len > 0) ++ buf[len - 1] = '\0'; ++#endif ++ ++ return len; ++} ++ ++ ++/** ++ * bnx2i_conn_start - completes iscsi connection migration to FFP ++ * ++ * @cls_conn: pointer to iscsi cls conn ++ * ++ * last call in FFP migration to handover iscsi conn to the driver ++ */ ++#ifdef __VMKLNX__ ++vmk_int32 bnx2i_conn_start(struct iscsi_cls_conn *cls_conn) ++#else ++int bnx2i_conn_start(struct iscsi_cls_conn *cls_conn) ++#endif ++{ ++ struct bnx2i_conn *conn = (struct bnx2i_conn *) cls_conn->dd_data; ++ struct bnx2i_sess *sess; ++ ++ if (conn->state != CONN_STATE_IN_LOGIN) { ++ printk(KERN_ALERT "conn_start: conn 0x%p state 0x%x err!!\n", ++ conn, conn->state); ++ return -EINVAL; ++ } ++ sess = conn->sess; ++ ++ if ((sess->imm_data || !sess->initial_r2t) && ++ sess->first_burst_len > sess->max_burst_len) { ++ printk(KERN_ALERT "bnx2i: invalid params, FBL > MBL\n"); ++ return -EINVAL; ++ } ++ ++ conn->state = CONN_STATE_FFP_STATE; ++ if (sess->lead_conn == conn) ++ sess->state = BNX2I_SESS_IN_FFP; ++ ++ conn->ep->state = EP_STATE_ULP_UPDATE_START; ++ ++ if (bnx2i_update_iscsi_conn(conn)) { ++ printk(KERN_ERR "bnx2i: unable to send conn update kwqe\n"); ++ return -ENOSPC; ++ } ++ ++ conn->ep->ofld_timer.expires = 10*HZ + jiffies; ++ conn->ep->ofld_timer.function = bnx2i_ep_ofld_timer; ++ conn->ep->ofld_timer.data = (unsigned long) conn->ep; ++ add_timer(&conn->ep->ofld_timer); ++ /* update iSCSI context for this conn, wait for CNIC to complete */ ++ wait_event_interruptible(conn->ep->ofld_wait, ++ conn->ep->state != EP_STATE_ULP_UPDATE_START); ++ ++ if (signal_pending(current)) ++ flush_signals(current); ++ del_timer_sync(&conn->ep->ofld_timer); ++ ++ switch (atomic_read(&conn->stop_state)) { ++ case STOP_CONN_RECOVER: ++ sess->recovery_state = ISCSI_SESS_RECOVERY_COMPLETE; ++ sess->state = BNX2I_SESS_IN_FFP; ++ atomic_set(&conn->stop_state, 0); ++#ifdef __VMKLNX__ ++ iscsi_unblock_session(cls_conn->session); ++#else ++ iscsi_unblock_session(session_to_cls(sess)); ++#endif ++ wake_up(&sess->er_wait); ++ break; ++ case STOP_CONN_TERM: ++ break; ++ default: ++ ; ++ } ++ ++ if (use_poll_timer) { ++ add_timer(&conn->poll_timer); ++ conn->poll_timer_enabled = 1; ++ } ++ ++ return 0; ++} ++ ++/* TOOD - debug only */ ++extern void bnx2i_print_cqe(struct bnx2i_conn *conn); ++extern void bnx2i_print_sqe(struct bnx2i_conn *conn); ++/* TOOD - debug only */ ++ ++/** ++ * bnx2i_conn_stop - stop any further processing on this connection ++ * ++ * @cls_conn: pointer to iscsi cls conn ++ * @flags: reason for freezing this connection ++ * ++ * call to take control of iscsi conn from the driver. Could be called ++ * when login failed, when recovery is to be attempted or during ++ * connection teardown ++ */ ++#ifdef __VMKLNX__ ++vmk_int32 bnx2i_conn_stop(struct iscsi_cls_conn *cls_conn, vmk_int32 flag) ++#else ++void bnx2i_conn_stop(struct iscsi_cls_conn *cls_conn, int flag) ++#endif ++{ ++ struct bnx2i_conn *conn = (struct bnx2i_conn *)cls_conn->dd_data; ++ struct Scsi_Host *shost = bnx2i_conn_get_shost(conn); ++ unsigned long flags; ++ ++ atomic_set(&conn->stop_state, flag); ++ conn->state = CONN_STATE_XPORT_FREEZE; ++#ifdef __VMKLNX__ ++ iscsi_block_session(cls_conn->session); ++#else ++ iscsi_block_session(session_to_cls(conn->sess)); ++#endif ++ ++ ++#ifndef __VMKLNX__ ++ atomic_set(&conn->worker_enabled, 0); ++ scsi_flush_work(shost); ++#endif ++ ++ switch (flag) { ++ case STOP_CONN_RECOVER: ++ conn->sess->state = BNX2I_SESS_IN_RECOVERY; ++ if (!conn->sess->recovery_state) { /* nopout timeout */ ++ ++ spin_lock_irqsave(shost->host_lock, flags); ++ conn->sess->recovery_state = ++ ISCSI_SESS_RECOVERY_OPEN_ISCSI; ++ spin_unlock_irqrestore(shost->host_lock, flags); ++ } ++ break; ++ case STOP_CONN_TERM: ++ if (conn->sess && (conn->sess->state & BNX2I_SESS_IN_FFP)) { ++ conn->sess->state = BNX2I_SESS_IN_SHUTDOWN; ++ } ++ break; ++ default: ++ printk(KERN_ERR "bnx2i: invalid conn stop req %d\n", flag); ++ } ++ ++ if (use_poll_timer && conn->poll_timer_enabled ) { ++ del_timer_sync(&conn->poll_timer); ++ conn->poll_timer_enabled = 0; ++ } ++ ++ /* Wait for TMF code to exit before returning to daemon */ ++ bnx2i_wait_for_tmf_completion(conn->sess); ++ ++#ifdef __VMKLNX__ ++ return 0; ++#else ++ return; ++#endif ++} ++ ++ ++/** ++ * bnx2i_conn_send_pdu - iscsi transport callback entry point to send ++ * iscsi slow path pdus, such as LOGIN/LOGOUT/NOPOUT, etc ++ * ++ * @hba: pointer to adapter instance ++ * ++ * sends iSCSI PDUs prepared by user daemon, only login, logout, nop-out pdu ++ * will flow this path. ++ */ ++#ifdef __VMKLNX__ ++vmk_int32 bnx2i_conn_send_pdu(struct iscsi_cls_conn *cls_conn, ++ struct iscsi_hdr *hdr, vmk_int8 *data, ++ vmk_uint32 data_size) ++#else ++int bnx2i_conn_send_pdu(struct iscsi_cls_conn *cls_conn, ++ struct iscsi_hdr *hdr, char *data, ++ uint32_t data_size) ++#endif ++{ ++ struct bnx2i_conn *conn; ++ struct bnx2i_cmd *cmnd; ++ uint32_t payload_size; ++ int count; ++#ifndef __VMKLNX__ ++ struct Scsi_Host *shost; ++#endif ++ ++ if (!cls_conn) { ++ printk(KERN_ALERT "bnx2i_conn_send_pdu: NULL conn ptr. \n"); ++ return -EIO; ++ } ++ conn = (struct bnx2i_conn *)cls_conn->dd_data; ++ if (!conn->gen_pdu.req_buf) { ++ printk(KERN_ALERT "send_pdu: login buf not allocated\n"); ++ /* ERR - buffer not allocated, should not happen */ ++ goto error; ++ } ++ ++ if (conn->state != CONN_STATE_XPORT_READY && ++ conn->state != CONN_STATE_IN_LOGIN && ++ (hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) { ++ /* login pdu request is valid in transport ready state */ ++ printk(KERN_ALERT "send_pdu: %d != XPORT_READY\n", ++ conn->state); ++ goto error; ++ } ++ ++ if (conn->sess->login_nopout_cmd) { ++ cmnd = conn->sess->login_nopout_cmd; ++ } else /* should not happen ever... */ ++ goto error; ++ ++ memset(conn->gen_pdu.req_buf, 0, ISCSI_CONN_LOGIN_BUF_SIZE); ++ conn->gen_pdu.req_buf_size = data_size; ++ ++ cmnd->conn = conn; ++ cmnd->scsi_cmd = NULL; ++ ++ switch (hdr->opcode & ISCSI_OPCODE_MASK) { ++ case ISCSI_OP_LOGIN: ++ /* Login request, copy hdr & data to buffer in conn struct */ ++ memcpy(&conn->gen_pdu.pdu_hdr, (const void *) hdr, ++ sizeof(struct iscsi_hdr)); ++ if (conn->state == CONN_STATE_XPORT_READY) ++ conn->state = CONN_STATE_IN_LOGIN; ++ payload_size = (hdr->dlength[0] << 16) | (hdr->dlength[1] << 8) | ++ hdr->dlength[2]; ++ ++ if (data_size) { ++ memcpy(conn->gen_pdu.login_req.mem, (const void *)data, ++ data_size); ++ conn->gen_pdu.req_wr_ptr = ++ conn->gen_pdu.req_buf + payload_size; ++ } ++ cmnd->iscsi_opcode = hdr->opcode; ++ smp_mb(); ++ atomic_set(&conn->sess->login_noop_pending, 1); ++ break; ++ case ISCSI_OP_LOGOUT: ++ /* Logout request, copy header only */ ++ memcpy(&conn->gen_pdu.pdu_hdr, (const void *) hdr, ++ sizeof(struct iscsi_hdr)); ++ conn->gen_pdu.req_wr_ptr = conn->gen_pdu.req_buf; ++ conn->state = CONN_STATE_IN_LOGOUT; ++ conn->sess->state = BNX2I_SESS_IN_LOGOUT; ++ if (atomic_read(&conn->sess->tmf_active)) ++ bnx2i_wait_for_tmf_completion(conn->sess); ++ ++ /* Wait for any outstanding iscsi nopout to complete */ ++ count = 10; ++ while (count-- && cmnd->iscsi_opcode) ++ msleep(100); ++ if (cmnd->iscsi_opcode) ++ goto error; ++ ++ cmnd->iscsi_opcode = hdr->opcode; ++ smp_mb(); ++ atomic_set(&conn->sess->logout_pending, 1); ++ break; ++ case ISCSI_OP_NOOP_OUT: ++ conn->sess->last_nooput_requested = jiffies; ++ conn->sess->noopout_requested_count++; ++ /* connection is being logged out, do not allow NOOP */ ++ if (conn->state == CONN_STATE_IN_LOGOUT) ++ goto error; ++ ++ /* unsolicited iSCSI NOOP copy hdr into conn struct */ ++ memcpy(&conn->gen_pdu.nopout_hdr, (const void *) hdr, ++ sizeof(struct iscsi_hdr)); ++ cmnd->iscsi_opcode = hdr->opcode; ++ cmnd->ttt = ISCSI_RESERVED_TAG; ++ smp_mb(); ++ atomic_set(&conn->sess->login_noop_pending, 1); ++ break; ++ default: ++ ; ++ } ++ ++ if (atomic_read(&conn->worker_enabled)) { ++#ifdef __VMKLNX__ ++ tasklet_schedule(&conn->conn_tasklet); ++#else ++ shost = bnx2i_conn_get_shost(conn); ++ scsi_queue_work(shost, &conn->conn_worker); ++#endif ++ } ++ return 0; ++error: ++ return -EIO; ++} ++ ++ ++/** ++ * bnx2i_conn_get_stats - returns iSCSI stats ++ * ++ * @cls_conn: pointer to iscsi cls conn ++ * @stats: pointer to iscsi statistic struct ++ */ ++void bnx2i_conn_get_stats(struct iscsi_cls_conn *cls_conn, ++ struct iscsi_stats *stats) ++{ ++ struct bnx2i_conn *conn = (struct bnx2i_conn *) cls_conn->dd_data; ++ ++ stats->txdata_octets = conn->total_data_octets_sent; ++ stats->rxdata_octets = conn->total_data_octets_rcvd; ++ ++ stats->noptx_pdus = conn->num_nopin_pdus; ++ stats->scsicmd_pdus = conn->num_scsi_cmd_pdus; ++ stats->tmfcmd_pdus = conn->num_tmf_req_pdus; ++ stats->login_pdus = conn->num_login_req_pdus; ++ stats->text_pdus = 0; ++ stats->dataout_pdus = conn->num_dataout_pdus; ++ stats->logout_pdus = conn->num_logout_req_pdus; ++ stats->snack_pdus = 0; ++ ++ stats->noprx_pdus = conn->num_nopout_pdus; ++ stats->scsirsp_pdus = conn->num_scsi_resp_pdus; ++ stats->tmfrsp_pdus = conn->num_tmf_resp_pdus; ++ stats->textrsp_pdus = 0; ++ stats->datain_pdus = conn->num_datain_pdus; ++ stats->logoutrsp_pdus = conn->num_logout_resp_pdus; ++ stats->r2t_pdus = conn->num_r2t_pdus; ++ stats->async_pdus = conn->num_async_pdus; ++ stats->rjt_pdus = conn->num_reject_pdus; ++ ++ stats->digest_err = 0; ++ stats->timeout_err = 0; ++ stats->custom_length = 0; ++} ++ ++#ifdef __VMKLNX__ ++vmk_int32 bnx2i_get_570x_limit(enum iscsi_param param, ++ TransportParamLimit *limit, vmk_int32 maxListLen) ++{ ++ limit->param = param; ++ switch(param) { ++ case ISCSI_PARAM_MAX_SESSIONS: ++ limit->type = TRANPORT_LIMIT_TYPE_LIST; ++ limit->hasPreferred = VMK_TRUE; ++ limit->preferred = 64; ++ limit->limit.list.count = 1; ++ limit->limit.list.value[0] = 64; ++ break; ++ default: ++ limit->type = TRANPORT_LIMIT_TYPE_UNSUPPORTED; ++ break; ++ } ++ return 0; ++} ++ ++vmk_int32 bnx2i_get_5771x_limit(enum iscsi_param param, ++ TransportParamLimit *limit, ++ vmk_int32 maxListLen) ++{ ++ limit->param = param; ++ switch(param) { ++ case ISCSI_PARAM_MAX_SESSIONS: ++ limit->type = TRANPORT_LIMIT_TYPE_LIST; ++ limit->hasPreferred = VMK_TRUE; ++ limit->preferred = 64; ++ limit->limit.list.count = 1; ++ limit->limit.list.value[0] = 128; ++ break; ++ default: ++ limit->type = TRANPORT_LIMIT_TYPE_UNSUPPORTED; ++ break; ++ } ++ return 0; ++} ++#endif ++ ++ ++ ++/** ++ * bnx2i_check_nx2_dev_busy - this routine unregister devices if ++ * there are no active conns ++ */ ++void bnx2i_check_nx2_dev_busy(void) ++{ ++ bnx2i_unreg_dev_all(); ++} ++ ++ ++/** ++ * bnx2i_check_route - checks if target IP route belongs to one of ++ * NX2 devices ++ * ++ * @dst_addr: target IP address ++ * ++ * check if route resolves to BNX2 device ++ */ ++#ifdef __VMKLNX__ ++static struct bnx2i_hba *bnx2i_check_route(struct sockaddr *dst_addr, ++ vmk_IscsiNetHandle iscsiNetHandle) ++#else ++static struct bnx2i_hba *bnx2i_check_route(struct sockaddr *dst_addr) ++#endif ++{ ++ struct sockaddr_in *desti = (struct sockaddr_in *) dst_addr; ++ struct bnx2i_hba *hba; ++ struct cnic_dev *cnic = NULL; ++ ++ bnx2i_reg_dev_all(); ++ ++ hba = get_adapter_list_head(); ++ if (hba && hba->cnic) ++#ifdef __VMKLNX__ ++ cnic = hba->cnic->cm_select_dev(iscsiNetHandle, desti, CNIC_ULP_ISCSI); ++#else ++ cnic = hba->cnic->cm_select_dev(desti, CNIC_ULP_ISCSI); ++#endif ++ ++ if (!cnic) { ++ printk(KERN_ALERT "bnx2i: check route, can't connect using cnic\n"); ++ goto no_nx2_route; ++ } ++ hba = bnx2i_find_hba_for_cnic(cnic); ++ if (!hba) { ++ goto no_nx2_route; ++ } ++ ++ if (bnx2i_adapter_ready(hba)) { ++ printk(KERN_ALERT "bnx2i: check route, hba not found\n"); ++ goto no_nx2_route; ++ } ++ if (hba->netdev->mtu > hba->mtu_supported) { ++ printk(KERN_ALERT "bnx2i: %s network i/f mtu is set to %d\n", ++ hba->netdev->name, hba->netdev->mtu); ++ printk(KERN_ALERT "bnx2i: iSCSI HBA can support mtu of %d\n", ++ hba->mtu_supported); ++ goto no_nx2_route; ++ } ++ return hba; ++no_nx2_route: ++ return NULL; ++} ++ ++ ++/** ++ * bnx2i_tear_down_conn - tear down iscsi/tcp connection and free resources ++ * ++ * @hba: pointer to adapter instance ++ * @ep: endpoint (transport indentifier) structure ++ * ++ * destroys cm_sock structure and on chip iscsi context ++ */ ++static int bnx2i_tear_down_conn(struct bnx2i_hba *hba, ++ struct bnx2i_endpoint *ep) ++{ ++ if (test_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic)) ++ hba->cnic->cm_destroy(ep->cm_sk); ++ ++ if (test_bit(ADAPTER_STATE_GOING_DOWN, &ep->hba->adapter_state)) ++ ep->state = EP_STATE_DISCONN_COMPL; ++ ++ if (test_bit(BNX2I_NX2_DEV_57710, &hba->cnic_dev_type) && ++ ep->state == EP_STATE_DISCONN_TIMEDOUT) { ++ printk(KERN_ALERT "bnx2i - WaTcH - please submit GRC Dump," ++ " NW/PCIe trace, driver msgs to developers" ++ " for analysis\n"); ++ return 1; ++ } ++ ++ ep->state = EP_STATE_CLEANUP_START; ++ init_timer(&ep->ofld_timer); ++ ep->ofld_timer.expires = hba->conn_ctx_destroy_tmo + jiffies; ++ ep->ofld_timer.function = bnx2i_ep_ofld_timer; ++ ep->ofld_timer.data = (unsigned long) ep; ++ add_timer(&ep->ofld_timer); ++ ++ bnx2i_ep_destroy_list_add(hba, ep); ++ ++ /* destroy iSCSI context, wait for it to complete */ ++ bnx2i_send_conn_destroy(hba, ep); ++ wait_event_interruptible(ep->ofld_wait, ++ (ep->state != EP_STATE_CLEANUP_START)); ++ ++ if (signal_pending(current)) ++ flush_signals(current); ++ del_timer_sync(&ep->ofld_timer); ++ bnx2i_ep_destroy_list_del(hba, ep); ++ ++ if (ep->state != EP_STATE_CLEANUP_CMPL) ++ /* should never happen */ ++ printk(KERN_ALERT "bnx2i - WaTcH: conn destroy failed\n"); ++ return 0; ++} ++ ++ ++/** ++ * bnx2i_ep_connect - establish TCP connection to target portal ++ * ++ * @dst_addr: target IP address ++ * @non_blocking: blocking or non-blocking call ++ * @ep_handle: placeholder to return new created endpoint handle ++ * ++ * this routine initiates the TCP/IP connection by invoking Option-2 i/f ++ * with l5_core and the CNIC. This is a multi-step process of resolving ++ * route to target, create a iscsi connection context, handshaking with ++ * CNIC module to create/initialize the socket struct and finally ++ * sending down option-2 request to complete TCP 3-way handshake ++ */ ++#ifdef __VMKLNX__ ++vmk_int32 bnx2i_ep_connect(struct sockaddr *dst_addr, vmk_int32 non_blocking, ++ vmk_uint64 *ep_handle, vmk_IscsiNetHandle iscsiNetHandle) ++#else ++int bnx2i_ep_connect(struct sockaddr *dst_addr, int non_blocking, ++ uint64_t *ep_handle) ++#endif ++{ ++ u32 iscsi_cid = BNX2I_CID_RESERVED; ++ struct sockaddr_in *desti; ++ struct sockaddr_in6 *desti6; ++ struct bnx2i_endpoint *endpoint; ++ struct bnx2i_hba *hba; ++ struct cnic_dev *cnic; ++ struct cnic_sockaddr saddr; ++ int rc = 0; ++ ++ /* check if the given destination can be reached through NX2 device */ ++#ifdef __VMKLNX__ ++ hba = bnx2i_check_route(dst_addr, iscsiNetHandle); ++#else ++ hba = bnx2i_check_route(dst_addr); ++#endif ++ if (!hba) { ++ rc = -ENOMEM; ++ goto check_busy; ++ } ++ ++ cnic = hba->cnic; ++ endpoint = bnx2i_alloc_ep(hba); ++ if (!endpoint) { ++ *ep_handle = (uint64_t) 0; ++ rc = -ENOMEM; ++ goto check_busy; ++ } ++ ++ mutex_lock(&hba->net_dev_lock); ++ ++ if (bnx2i_adapter_ready(hba)) { ++ rc = -EPERM; ++ goto net_if_down; ++ } ++ ++ endpoint->state = EP_STATE_IDLE; ++ endpoint->teardown_mode = BNX2I_ABORTIVE_SHUTDOWN; ++ endpoint->ep_iscsi_cid = (u16)ISCSI_RESERVED_TAG; ++ iscsi_cid = bnx2i_alloc_iscsi_cid(hba); ++ if (iscsi_cid == ISCSI_RESERVED_TAG) { ++ printk(KERN_ALERT "alloc_ep: unable to allocate iscsi cid\n"); ++ rc = -ENOMEM; ++ goto iscsi_cid_err; ++ } ++ endpoint->hba_age = hba->age; ++ ++ rc = bnx2i_alloc_qp_resc(hba, endpoint); ++ if (rc != 0) { ++ printk(KERN_ALERT "bnx2i: ep_conn, alloc QP resc error\n"); ++ rc = -ENOMEM; ++ goto qp_resc_err; ++ } ++ ++ endpoint->ep_iscsi_cid = iscsi_cid & 0xFFFF; ++ endpoint->state = EP_STATE_OFLD_START; ++ bnx2i_ep_ofld_list_add(hba, endpoint); ++ ++ init_timer(&endpoint->ofld_timer); ++ endpoint->ofld_timer.expires = 2 * HZ + jiffies; ++ endpoint->ofld_timer.function = bnx2i_ep_ofld_timer; ++ endpoint->ofld_timer.data = (unsigned long) endpoint; ++ add_timer(&endpoint->ofld_timer); ++ ++ if (bnx2i_send_conn_ofld_req(hba, endpoint)) { ++ printk(KERN_ERR "bnx2i: unable to send conn offld kwqe\n"); ++ rc = -ENOSPC; ++ goto conn_failed; ++ } ++ ++ /* Wait for CNIC hardware to setup conn context and return 'cid' */ ++ wait_event_interruptible(endpoint->ofld_wait, ++ endpoint->state != EP_STATE_OFLD_START); ++ ++ if (signal_pending(current)) ++ flush_signals(current); ++ del_timer_sync(&endpoint->ofld_timer); ++ bnx2i_ep_ofld_list_del(hba, endpoint); ++ ++ if (endpoint->state != EP_STATE_OFLD_COMPL) { ++ rc = -ENOSPC; ++ goto conn_failed; ++ } ++ ++ if (!test_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic)) { ++ rc = -EINVAL; ++ goto conn_failed; ++ } else ++ rc = cnic->cm_create(cnic, CNIC_ULP_ISCSI, endpoint->ep_cid, ++ iscsi_cid, &endpoint->cm_sk, endpoint); ++ if (rc) { ++ rc = -EINVAL; ++ goto conn_failed; ++ } ++ ++ endpoint->cm_sk->rcv_buf = tcp_buf_size * 1024; ++ endpoint->cm_sk->snd_buf = tcp_buf_size * 1024; ++ if (!en_tcp_dack) ++ endpoint->cm_sk->tcp_flags |= SK_TCP_NO_DELAY_ACK; ++ if (time_stamps) ++ endpoint->cm_sk->tcp_flags |= SK_TCP_TIMESTAMP; ++ ++ memset(&saddr, 0, sizeof(saddr)); ++ ++ if (dst_addr->sa_family == AF_INET) { ++ desti = (struct sockaddr_in *) dst_addr; ++ saddr.remote.v4 = *desti; ++ saddr.local.v4.sin_port = htons(endpoint->tcp_port); ++ saddr.local.v4.sin_family = desti->sin_family; ++ } else if (dst_addr->sa_family == AF_INET6) { ++ desti6 = (struct sockaddr_in6 *) dst_addr; ++ saddr.remote.v6 = *desti6; ++ saddr.local.v6.sin6_port = htons(endpoint->tcp_port); ++ saddr.local.v6.sin6_family = desti6->sin6_family; ++ } ++ ++ endpoint->timestamp = jiffies; ++ endpoint->state = EP_STATE_CONNECT_START; ++ if (!test_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic)) { ++ rc = -EINVAL; ++ goto conn_failed; ++ } else ++ rc = cnic->cm_connect(endpoint->cm_sk, &saddr); ++ ++ if (rc) ++ goto release_ep; ++ ++ rc = bnx2i_map_ep_dbell_regs(endpoint); ++ if (rc) ++ goto release_ep; ++ ++ *ep_handle = (uint64_t) (unsigned long) endpoint; ++ mutex_unlock(&hba->net_dev_lock); ++ ++ /* ++ * unregister idle devices, without this user can't uninstall ++ * unused bnx2/bnx2x driver because registration will increment ++ * the usage count ++ */ ++ bnx2i_check_nx2_dev_busy(); ++ ++ return 0; ++ ++release_ep: ++ bnx2i_tear_down_conn(hba, endpoint); ++conn_failed: ++net_if_down: ++iscsi_cid_err: ++ bnx2i_free_qp_resc(hba, endpoint); ++qp_resc_err: ++ bnx2i_free_ep(endpoint); ++ mutex_unlock(&hba->net_dev_lock); ++check_busy: ++ *ep_handle = (uint64_t) 0; ++ bnx2i_check_nx2_dev_busy(); ++ return rc; ++} ++ ++ ++/** ++ * bnx2i_ep_poll - polls for TCP connection establishement ++ * ++ * @ep_handle: TCP connection (endpoint) handle ++ * @timeout_ms: timeout value in milli secs ++ * ++ * polls for TCP connect request to complete ++ */ ++#ifdef __VMKLNX__ ++vmk_int32 bnx2i_ep_poll(vmk_uint64 ep_handle, vmk_int32 timeout_ms) ++#else ++int bnx2i_ep_poll(uint64_t ep_handle, int timeout_ms) ++#endif ++{ ++ struct bnx2i_endpoint *ep; ++ int rc = 0; ++ ++ ep = (struct bnx2i_endpoint *) (unsigned long) ep_handle; ++ if (!ep || (ep_handle == -1)) ++ return -EINVAL; ++ ++ if ((ep->state == EP_STATE_IDLE) || ++ (ep->state == EP_STATE_CONNECT_FAILED) || ++ (ep->state == EP_STATE_OFLD_FAILED)) ++ return -1; ++ ++ if (ep->state == EP_STATE_CONNECT_COMPL) ++ return 1; ++ ++ rc = wait_event_interruptible_timeout(ep->ofld_wait, ++ ((ep->state == ++ EP_STATE_OFLD_FAILED) || ++ (ep->state == ++ EP_STATE_CONNECT_FAILED) || ++ (ep->state == ++ EP_STATE_CONNECT_COMPL)), ++ msecs_to_jiffies(timeout_ms)); ++ if (ep->state == EP_STATE_OFLD_FAILED) ++ rc = -1; ++ ++ if (rc > 0) ++ return 1; ++ else if (!rc) ++ return 0; /* timeout */ ++ else ++ return rc; ++} ++ ++/** ++ * bnx2i_ep_tcp_conn_active - check EP state transition to check ++ * if underlying TCP connection is active ++ * ++ * @ep: endpoint pointer ++ * ++ */ ++static int bnx2i_ep_tcp_conn_active(struct bnx2i_endpoint *ep) ++{ ++ int ret; ++ ++ switch (ep->state) { ++ case EP_STATE_CLEANUP_FAILED: ++ case EP_STATE_OFLD_FAILED: ++ case EP_STATE_DISCONN_TIMEDOUT: ++ ret = 0; ++ break; ++ case EP_STATE_CONNECT_COMPL: ++ case EP_STATE_ULP_UPDATE_START: ++ case EP_STATE_ULP_UPDATE_COMPL: ++ case EP_STATE_TCP_FIN_RCVD: ++ case EP_STATE_ULP_UPDATE_FAILED: ++ case EP_STATE_CONNECT_FAILED: ++ /* cnic need to upload PG for 570x chipsets and there is ++ * an understanding it is safe to call cm_abort() even if ++ * cm_connect() failed for all chip types ++ */ ++ ret = 1; ++ break; ++ case EP_STATE_TCP_RST_RCVD: ++ case EP_STATE_CONNECT_START: ++ /* bnx2i will not know whether PG needs to be uploaded or not. ++ * bnx2i will call cm_abort() and let cnic decide the clean-up ++ * action that needs to be taken ++ */ ++ if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) ++ ret = 0; ++ else ++ ret = 1; ++ break; ++ default: ++ ret = 0; ++ } ++ ++ return ret; ++} ++ ++/** ++ * bnx2i_ep_disconnect - executes TCP connection teardown process ++ * ++ * @ep_handle: TCP connection (endpoint) handle ++ * ++ * executes TCP connection teardown process ++ */ ++#ifdef __VMKLNX__ ++void bnx2i_ep_disconnect(vmk_int64 ep_handle) ++#else ++void bnx2i_ep_disconnect(uint64_t ep_handle) ++#endif ++{ ++ struct bnx2i_endpoint *ep; ++ struct cnic_dev *cnic; ++ struct bnx2i_hba *hba; ++ struct bnx2i_sess *sess; ++ ++ ep = (struct bnx2i_endpoint *) (unsigned long) ep_handle; ++ if (!ep || (ep_handle == -1)) ++ return; ++ ++ while ((ep->state == EP_STATE_CONNECT_START) && ++ !time_after(jiffies, ep->timestamp + (12 * HZ))) ++ msleep(250); ++ ++#ifdef __VMKLNX__ ++ /** This could be a bug, we always disable here, but we enable in BIND ++ * so we should ONLY ever disable if the ep was assigned a conn ( AKA BIND was run ) ++ * Another case is that conn_destroy got called, which sets the ep->conn to NULL ++ * which is ok since destroy stops the tasklet ++ */ ++ if (ep->conn) { ++ atomic_set(&ep->conn->worker_enabled, 0); ++ tasklet_kill(&ep->conn->conn_tasklet); ++ } ++#endif ++ ++ hba = ep->hba; ++ if (ep->state == EP_STATE_IDLE) ++ goto return_ep; ++ cnic = hba->cnic; ++ ++ printk("%s: disconnecting ep %p, cid %d, hba %p\n", __FUNCTION__, ep, ep->ep_iscsi_cid, hba); ++ ++ mutex_lock(&hba->net_dev_lock); ++ if (!test_bit(ADAPTER_STATE_UP, &hba->adapter_state)) ++ goto free_resc; ++ if (ep->hba_age != hba->age) ++ goto dev_reset; ++ ++ if (!bnx2i_ep_tcp_conn_active(ep)) ++ goto destory_conn; ++ ++ ep->state = EP_STATE_DISCONN_START; ++ ++ init_timer(&ep->ofld_timer); ++ ep->ofld_timer.expires = hba->conn_teardown_tmo + jiffies; ++ ep->ofld_timer.function = bnx2i_ep_ofld_timer; ++ ep->ofld_timer.data = (unsigned long) ep; ++ add_timer(&ep->ofld_timer); ++ ++ if (test_bit(BNX2I_CNIC_REGISTERED, &hba->reg_with_cnic)) { ++ if (ep->teardown_mode == BNX2I_GRACEFUL_SHUTDOWN) ++ cnic->cm_close(ep->cm_sk); ++ else ++ cnic->cm_abort(ep->cm_sk); ++ } else ++ goto free_resc; ++ ++ /* wait for option-2 conn teardown */ ++ wait_event_interruptible(ep->ofld_wait, ++ ep->state != EP_STATE_DISCONN_START); ++ ++ if (signal_pending(current)) ++ flush_signals(current); ++ del_timer_sync(&ep->ofld_timer); ++ ++destory_conn: ++ if (bnx2i_tear_down_conn(hba, ep)) { ++ mutex_unlock(&hba->net_dev_lock); ++ return; ++ } ++ ++dev_reset: ++free_resc: ++ /* in case of 3-way handshake failure, there won't be any binding ++ * between EP and SESS ++ */ ++ if (ep->sess) { ++ int cmds_a = 0, cmds_p = 0; ++ cmds_p = bnx2i_flush_pend_queue(ep->sess, NULL, DID_RESET); ++ cmds_a = bnx2i_flush_cmd_queue(ep->sess, NULL, DID_RESET, 0); ++ //printk(KERN_ALERT "%s: CMDS FLUSHED, pend=%d, active=%d\n", __FUNCTION__, cmds_p, cmds_a); ++ } ++ ++ mutex_unlock(&hba->net_dev_lock); ++ bnx2i_free_qp_resc(hba, ep); ++return_ep: ++ /* check if session recovery in progress */ ++ sess = ep->sess; ++ ++ bnx2i_free_ep(ep); ++ if (sess) { ++ sess->state = BNX2I_SESS_INITIAL; ++ wake_up(&sess->er_wait); ++ } ++ wake_up_interruptible(&hba->eh_wait); ++ ++ if (!hba->ofld_conns_active) ++ bnx2i_check_nx2_dev_busy(); ++ ++ return; ++} ++ ++ ++int bnx2i_check_ioctl_signature(struct bnx2i_ioctl_header *ioc_hdr) ++{ ++ if (strcmp(ioc_hdr->signature, BNX2I_MGMT_SIGNATURE)) ++ return -EPERM; ++ return 0; ++} ++ ++static int bnx2i_tcp_port_count_ioctl(struct file *file, unsigned long arg) ++{ ++ struct bnx2i_get_port_count __user *user_ioc = ++ (struct bnx2i_get_port_count __user *)arg; ++ struct bnx2i_get_port_count ioc_req; ++ int error = 0; ++ unsigned int count = 0; ++ ++ if (copy_from_user(&ioc_req, user_ioc, sizeof(ioc_req))) { ++ error = -EFAULT; ++ goto out; ++ } ++ ++ error = bnx2i_check_ioctl_signature(&ioc_req.hdr); ++ if (error) ++ goto out; ++ ++ if (bnx2i_tcp_port_tbl.num_free_ports < 10 && ++ bnx2i_tcp_port_tbl.num_required) { ++ if (bnx2i_tcp_port_tbl.num_required < 32) ++ count = bnx2i_tcp_port_tbl.num_required; ++ else ++ count = 32; ++ } ++ ++ ioc_req.port_count = count; ++ ++ if (copy_to_user(&user_ioc->port_count, &ioc_req.port_count, ++ sizeof(ioc_req.port_count))) { ++ error = -EFAULT; ++ goto out; ++ } ++ ++out: ++ return error; ++} ++ ++ ++static int bnx2i_tcp_port_ioctl(struct file *file, unsigned long arg) ++{ ++ struct bnx2i_set_port_num __user *user_ioc = ++ (struct bnx2i_set_port_num __user *)arg; ++ struct bnx2i_set_port_num ioc_req; ++ struct bnx2i_set_port_num *ioc_req_mp = NULL; ++ int ioc_msg_size = sizeof(ioc_req); ++ int error; ++ int i; ++ ++ if (copy_from_user(&ioc_req, user_ioc, ioc_msg_size)) { ++ error = -EFAULT; ++ goto out; ++ } ++ ++ error = bnx2i_check_ioctl_signature(&ioc_req.hdr); ++ if (error) ++ goto out; ++ ++ if (ioc_req.num_ports > 1) { ++ ioc_msg_size += (ioc_req.num_ports - 1) * ++ sizeof(ioc_req.tcp_port[0]); ++ ++ ioc_req_mp = kmalloc(ioc_msg_size, GFP_KERNEL); ++ if (!ioc_req_mp) ++ goto out; ++ ++ if (copy_from_user(ioc_req_mp, user_ioc, ioc_msg_size)) { ++ error = -EFAULT; ++ goto out_kfree; ++ } ++ } ++ ++ if (ioc_req.num_ports) ++ bnx2i_tcp_port_new_entry(ioc_req.tcp_port[0]); ++ ++ i = 1; ++ while (i < ioc_req_mp->num_ports) ++ bnx2i_tcp_port_new_entry(ioc_req_mp->tcp_port[i++]); ++ ++ return 0; ++ ++out_kfree: ++ kfree(ioc_req_mp); ++out: ++ return error; ++} ++ ++ ++/* ++ * bnx2i_ioctl_init: initialization routine, registers char driver ++ */ ++int bnx2i_ioctl_init(void) ++{ ++ int ret; ++ ++ /* Register char device node */ ++ ret = register_chrdev(0, "bnx2i", &bnx2i_mgmt_fops); ++ ++ if (ret < 0) { ++ printk(KERN_ERR "bnx2i: failed to register device node\n"); ++ return ret; ++ } ++ ++ bnx2i_major_no = ret; ++ ++ return 0; ++} ++ ++void bnx2i_ioctl_cleanup(void) ++{ ++ if (bnx2i_major_no) { ++ unregister_chrdev(bnx2i_major_no, "bnx2i"); ++ } ++} ++ ++/* ++ * bnx2i_mgmt_open - "open" entry point ++ */ ++static int bnx2i_mgmt_open(struct inode *inode, struct file *filep) ++{ ++ /* only allow access to admin user */ ++ if (!capable(CAP_SYS_ADMIN)) { ++ return -EACCES; ++ } ++ ++ return 0; ++} ++ ++/* ++ * bnx2i_mgmt_release- "release" entry point ++ */ ++static int bnx2i_mgmt_release(struct inode *inode, struct file *filep) ++{ ++ return 0; ++} ++ ++ ++ ++/* ++ * bnx2i_mgmt_ioctl - char driver ioctl entry point ++ */ ++static int bnx2i_mgmt_ioctl(struct inode *node, struct file *file, ++ unsigned int cmd, unsigned long arg) ++{ ++ long rc = 0; ++ switch (cmd) { ++ case BNX2I_IOCTL_GET_PORT_REQ: ++ rc = bnx2i_tcp_port_count_ioctl(file, arg); ++ break; ++ case BNX2I_IOCTL_SET_TCP_PORT: ++ rc = bnx2i_tcp_port_ioctl(file, arg); ++ break; ++ default: ++ printk(KERN_ERR "bnx2i: unknown ioctl cmd %x\n", cmd); ++ return -ENOTTY; ++ } ++ ++ return rc; ++} ++ ++ ++#ifdef CONFIG_COMPAT ++ ++static int bnx2i_tcp_port_count_compat_ioctl(struct file *file, unsigned long arg) ++{ ++ struct bnx2i_get_port_count __user *user_ioc = ++ (struct bnx2i_get_port_count __user *)arg; ++ struct bnx2i_get_port_count *ioc_req = ++ compat_alloc_user_space(sizeof(struct bnx2i_get_port_count)); ++ int error; ++ unsigned int count = 0; ++ ++ if (clear_user(ioc_req, sizeof(*ioc_req))) ++ return -EFAULT; ++ ++ if (copy_in_user(ioc_req, user_ioc, sizeof(*ioc_req))) { ++ error = -EFAULT; ++ goto out; ++ } ++ ++ error = bnx2i_check_ioctl_signature(&ioc_req->hdr); ++ if (error) ++ goto out; ++ ++ if (bnx2i_tcp_port_tbl.num_free_ports < 10 && ++ bnx2i_tcp_port_tbl.num_required) { ++ if (bnx2i_tcp_port_tbl.num_required < 32) ++ count = bnx2i_tcp_port_tbl.num_required; ++ else ++ count = 32; ++ } ++ ++ if (copy_to_user(&ioc_req->port_count, &count, ++ sizeof(ioc_req->port_count))) { ++ error = -EFAULT; ++ goto out; ++ } ++ ++ if (copy_in_user(&user_ioc->port_count, &ioc_req->port_count, ++ sizeof(u32))) { ++ error = -EFAULT; ++ goto out; ++ } ++ return 0; ++ ++out: ++ return error; ++} ++ ++static int bnx2i_tcp_port_compat_ioctl(struct file *file, unsigned long arg) ++{ ++ struct bnx2i_set_port_num __user *user_ioc = ++ (struct bnx2i_set_port_num __user *)arg; ++ struct bnx2i_set_port_num *ioc_req = ++ compat_alloc_user_space(sizeof(struct bnx2i_set_port_num)); ++ struct bnx2i_set_port_num *ioc_req_mp = NULL; ++ int ioc_msg_size = sizeof(*ioc_req); ++ int error; ++ int i; ++ ++ if (clear_user(ioc_req, sizeof(*ioc_req))) ++ return -EFAULT; ++ ++ if (copy_in_user(ioc_req, user_ioc, ioc_msg_size)) { ++ error = -EFAULT; ++ goto out; ++ } ++ ++ error = bnx2i_check_ioctl_signature(&ioc_req->hdr); ++ if (error) ++ goto out; ++ ++ if (ioc_req->num_ports > 1) { ++ ioc_msg_size += (ioc_req->num_ports - 1) * ++ sizeof(ioc_req->tcp_port[0]); ++ ++ ioc_req_mp = compat_alloc_user_space(ioc_msg_size); ++ if (!ioc_req_mp) ++ goto out; ++ ++ if (copy_in_user(ioc_req_mp, user_ioc, ioc_msg_size)) { ++ error = -EFAULT; ++ goto out; ++ } ++ ++ i = 0; ++ while ((i < ioc_req_mp->num_ports) && ioc_req_mp) ++ bnx2i_tcp_port_new_entry(ioc_req_mp->tcp_port[i++]); ++ ++ } else if (ioc_req->num_ports == 1) ++ bnx2i_tcp_port_new_entry(ioc_req->tcp_port[0]); ++ ++out: ++ return error; ++ ++ ++} ++ ++ ++/* ++ * bnx2i_mgmt_compat_ioctl - char node ioctl entry point ++ */ ++static long bnx2i_mgmt_compat_ioctl(struct file *file, ++ unsigned int cmd, unsigned long arg) ++{ ++ int rc = -ENOTTY; ++ ++ switch (cmd) { ++ case BNX2I_IOCTL_GET_PORT_REQ: ++ rc = bnx2i_tcp_port_count_compat_ioctl(file, arg); ++ break; ++ case BNX2I_IOCTL_SET_TCP_PORT: ++ rc = bnx2i_tcp_port_compat_ioctl(file, arg); ++ break; ++ } ++ ++ return rc; ++} ++ ++#endif ++ ++/* ++ * File operations structure - management interface ++ */ ++struct file_operations bnx2i_mgmt_fops = { ++ .owner = THIS_MODULE, ++ .open = bnx2i_mgmt_open, ++ .release = bnx2i_mgmt_release, ++ .ioctl = bnx2i_mgmt_ioctl, ++#ifdef CONFIG_COMPAT ++ .compat_ioctl = bnx2i_mgmt_compat_ioctl, ++#endif ++}; ++ ++ ++/* ++ * 'Scsi_Host_Template' structure and 'iscsi_tranport' structure template ++ * used while registering with the iSCSI trnaport module. ++ */ ++struct scsi_host_template bnx2i_host_template = { ++ .module = THIS_MODULE, ++ .name = "Broadcom Offload iSCSI Initiator", ++ .queuecommand = bnx2i_queuecommand, ++ .eh_abort_handler = bnx2i_abort, ++ .eh_host_reset_handler = bnx2i_host_reset, ++ .bios_param = NULL, ++#ifdef __VMKLNX__ ++ .eh_device_reset_handler = bnx2i_device_reset, ++ .slave_configure = bnx2i_slave_configure, ++ .slave_alloc = bnx2i_slave_alloc, ++ .target_alloc = bnx2i_target_alloc, ++ .target_destroy = bnx2i_target_destroy, ++ .can_queue = 1024, ++#else ++ .can_queue = 128, ++#endif ++ .max_sectors = 127, ++ .this_id = -1, ++ .cmd_per_lun = 64, ++ .use_clustering = ENABLE_CLUSTERING, ++ .sg_tablesize = ISCSI_MAX_BDS_PER_CMD, ++ .proc_name = NULL ++ }; ++ ++ ++ ++struct iscsi_transport bnx2i_iscsi_transport = { ++ .owner = THIS_MODULE, ++ .name = "bnx2i", ++ .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_MULTI_R2T ++#ifdef __VMKLNX__ ++ | CAP_KERNEL_POLL | CAP_SESSION_PERSISTENT ++#endif ++ | CAP_DATADGST, ++ .param_mask = ISCSI_MAX_RECV_DLENGTH | ++ ISCSI_MAX_XMIT_DLENGTH | ++ ISCSI_HDRDGST_EN | ++ ISCSI_DATADGST_EN | ++ ISCSI_INITIAL_R2T_EN | ++ ISCSI_MAX_R2T | ++ ISCSI_IMM_DATA_EN | ++ ISCSI_FIRST_BURST | ++ ISCSI_MAX_BURST | ++ ISCSI_PDU_INORDER_EN | ++ ISCSI_DATASEQ_INORDER_EN | ++ ISCSI_ERL | ++ ISCSI_CONN_PORT | ++ ISCSI_CONN_ADDRESS | ++ ISCSI_EXP_STATSN | ++ ISCSI_PERSISTENT_PORT | ++ ISCSI_PERSISTENT_ADDRESS | ++ ISCSI_TARGET_NAME | ++ ISCSI_TPGT, ++ .host_template = &bnx2i_host_template, ++ .sessiondata_size = sizeof(struct bnx2i_sess), ++ .conndata_size = sizeof(struct bnx2i_conn), ++ .max_conn = 1, ++ .max_cmd_len = 16, ++ .max_lun = 512, ++#ifdef __VMKLNX__ ++ .create_session_persistent = bnx2i_session_create_vmp, ++ .create_session = bnx2i_session_create_vm, ++#else ++ .create_session = bnx2i_session_create, ++#endif ++ .destroy_session = bnx2i_session_destroy, ++ .create_conn = bnx2i_conn_create, ++ .bind_conn = bnx2i_conn_bind, ++ .destroy_conn = bnx2i_conn_destroy, ++ .set_param = bnx2i_conn_set_param, ++ .get_conn_param = bnx2i_conn_get_param, ++ .get_session_param = bnx2i_session_get_param, ++ .start_conn = bnx2i_conn_start, ++ .stop_conn = bnx2i_conn_stop, ++ .send_pdu = bnx2i_conn_send_pdu, ++ .get_stats = bnx2i_conn_get_stats, ++#ifdef __VMKLNX__ ++ /* TCP connect - disconnect - option-2 interface calls */ ++ .ep_connect = NULL, ++ .ep_connect_extended = bnx2i_ep_connect, ++#else ++ .ep_connect = bnx2i_ep_connect, ++#endif ++ .ep_poll = bnx2i_ep_poll, ++ .ep_disconnect = bnx2i_ep_disconnect, ++ /* Error recovery timeout call */ ++ .session_recovery_timedout = bnx2i_sess_recovery_timeo ++}; +diff -r ffba7e1f063a drivers/scsi/bnx2i/bnx2i_sysfs.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/bnx2i/bnx2i_sysfs.c Wed Aug 05 10:51:49 2009 +0100 +@@ -0,0 +1,214 @@ ++/* bnx2i_sysfs.c: Broadcom NetXtreme II iSCSI driver. ++ * ++ * Copyright (c) 2006 - 2009 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ * ++ * Written by: Anil Veerabhadrappa (anilgv@broadcom.com) ++ */ ++ ++#include "bnx2i.h" ++#include ++ ++#ifdef _SYSFS_INCL_ ++ ++#define BNX2I_SYSFS_VERSION 0x2 ++ ++ ++static ssize_t bnx2i_show_net_if_name(struct class_device *cdev, char *buf) ++{ ++ struct bnx2i_hba *hba = ++ container_of(cdev, struct bnx2i_hba, class_dev); ++ ++ return sprintf(buf, "%s\n", hba->netdev->name); ++} ++ ++static ssize_t bnx2i_show_sq_info(struct class_device *cdev, char *buf) ++{ ++ struct bnx2i_hba *hba = ++ container_of(cdev, struct bnx2i_hba, class_dev); ++ ++ return sprintf(buf, "0x%x\n", hba->max_sqes); ++} ++ ++static ssize_t bnx2i_set_sq_info(struct class_device *cdev, ++ const char *buf, size_t count) ++{ ++ struct bnx2i_hba *hba = ++ container_of(cdev, struct bnx2i_hba, class_dev); ++ u32 val; ++ int max_sq_size; ++ ++ if (test_bit(BNX2I_NX2_DEV_57710, &hba->cnic_dev_type)) ++ max_sq_size = BNX2I_5770X_SQ_WQES_MAX; ++ else ++ max_sq_size = BNX2I_570X_SQ_WQES_MAX; ++ ++ if (sscanf(buf, " 0x%x ", &val) > 0) { ++ if ((val >= BNX2I_SQ_WQES_MIN) && (val <= max_sq_size )) ++ hba->max_sqes = val; ++ } ++ return count; ++} ++ ++static ssize_t bnx2i_show_rq_info(struct class_device *cdev, char *buf) ++{ ++ struct bnx2i_hba *hba = ++ container_of(cdev, struct bnx2i_hba, class_dev); ++ ++ return sprintf(buf, "0x%x\n", hba->max_rqes); ++} ++ ++static ssize_t bnx2i_set_rq_info(struct class_device *cdev, const char *buf, ++ size_t count) ++{ ++ u32 val; ++ struct bnx2i_hba *hba = ++ container_of(cdev, struct bnx2i_hba, class_dev); ++ ++ if (sscanf(buf, " 0x%x ", &val) > 0) { ++ if ((val >= BNX2I_RQ_WQES_MIN) && ++ (val <= BNX2I_RQ_WQES_MAX)) { ++ hba->max_rqes = val; ++ } ++ } ++ return count; ++} ++ ++ ++static ssize_t bnx2i_show_ccell_info(struct class_device *cdev, char *buf) ++{ ++ struct bnx2i_hba *hba = ++ container_of(cdev, struct bnx2i_hba, class_dev); ++ ++ return sprintf(buf, "0x%x\n", hba->num_ccell); ++} ++ ++static ssize_t bnx2i_set_ccell_info(struct class_device *cdev, ++ const char *buf, size_t count) ++{ ++ u32 val; ++ struct bnx2i_hba *hba = ++ container_of(cdev, struct bnx2i_hba, class_dev); ++ ++ if (sscanf(buf, " 0x%x ", &val) > 0) { ++ if ((val >= BNX2I_CCELLS_MIN) && ++ (val <= BNX2I_CCELLS_MAX)) { ++ hba->num_ccell = val; ++ } ++ } ++ return count; ++} ++ ++ ++static ssize_t bnx2i_read_pci_trigger_reg(struct class_device *cdev, ++ char *buf) ++{ ++ u32 reg_val; ++ struct bnx2i_hba *hba = ++ container_of(cdev, struct bnx2i_hba, class_dev); ++ ++ if (!hba->regview) ++ return 0; ++ ++#define PCI_EVENT_TRIGGER_REG 0xCAC /* DMA WCHAN STAT10 REG */ ++ reg_val = readl(hba->regview + PCI_EVENT_TRIGGER_REG); ++ return sprintf(buf, "0x%x\n", reg_val); ++} ++ ++ ++static CLASS_DEVICE_ATTR (net_if_name, S_IRUGO, ++ bnx2i_show_net_if_name, NULL); ++static CLASS_DEVICE_ATTR (sq_size, S_IRUGO | S_IWUSR, ++ bnx2i_show_sq_info, bnx2i_set_sq_info); ++static CLASS_DEVICE_ATTR (rq_size, S_IRUGO | S_IWUSR, ++ bnx2i_show_rq_info, bnx2i_set_rq_info); ++static CLASS_DEVICE_ATTR (num_ccell, S_IRUGO | S_IWUSR, ++ bnx2i_show_ccell_info, bnx2i_set_ccell_info); ++static CLASS_DEVICE_ATTR (pci_trigger, S_IRUGO, ++ bnx2i_read_pci_trigger_reg, NULL); ++ ++ ++static struct class_device_attribute *bnx2i_class_attributes[] = { ++ &class_device_attr_net_if_name, ++ &class_device_attr_sq_size, ++ &class_device_attr_rq_size, ++ &class_device_attr_num_ccell, ++ &class_device_attr_pci_trigger, ++}; ++ ++static void bnx2i_sysfs_release(struct class_device *class_dev) ++{ ++} ++ ++struct class_device port_class_dev; ++ ++ ++static struct class bnx2i_class = { ++ .name = "bnx2i", ++ .release = bnx2i_sysfs_release, ++}; ++ ++int bnx2i_register_sysfs(struct bnx2i_hba *hba) ++{ ++ struct class_device *class_dev = &hba->class_dev; ++ char dev_name[BUS_ID_SIZE]; ++ struct ethtool_drvinfo drv_info; ++ u32 bus_no; ++ u32 dev_no; ++ u32 func_no; ++ u32 extra; ++ int ret; ++ int i; ++ ++ if (hba->cnic && hba->cnic->netdev) { ++ hba->cnic->netdev->ethtool_ops->get_drvinfo(hba->cnic->netdev, ++ &drv_info); ++ sscanf(drv_info.bus_info, "%x:%x:%x.%d", ++ &extra, &bus_no, &dev_no, &func_no); ++ } ++ class_dev->class = &bnx2i_class; ++ class_dev->class_data = hba; ++ snprintf(dev_name, BUS_ID_SIZE, "%.2x:%.2x.%.1x", ++ bus_no, dev_no, func_no); ++ strlcpy(class_dev->class_id, dev_name, BUS_ID_SIZE); ++ ++ ret = class_device_register(class_dev); ++ if (ret) ++ goto err; ++ ++ for (i = 0; i < ARRAY_SIZE(bnx2i_class_attributes); ++i) { ++ ret = class_device_create_file(class_dev, ++ bnx2i_class_attributes[i]); ++ if (ret) ++ goto err_unregister; ++ } ++ ++ return 0; ++ ++err_unregister: ++ class_device_unregister(class_dev); ++err: ++ return ret; ++} ++ ++void bnx2i_unregister_sysfs(struct bnx2i_hba *hba) ++{ ++ class_device_unregister(&hba->class_dev); ++} ++ ++int bnx2i_sysfs_setup(void) ++{ ++ int ret; ++ ret = class_register(&bnx2i_class); ++ return ret; ++} ++ ++void bnx2i_sysfs_cleanup(void) ++{ ++ class_unregister(&bnx2i_class); ++} ++ ++#endif diff --git a/master/bnx2x-1.50.13.patch b/master/bnx2x-1.50.13.patch new file mode 100644 index 0000000..8bff290 --- /dev/null +++ b/master/bnx2x-1.50.13.patch @@ -0,0 +1,84269 @@ +diff -r e67cb9a8e847 drivers/net/Makefile +--- a/drivers/net/Makefile Wed Aug 05 10:50:39 2009 +0100 ++++ b/drivers/net/Makefile Wed Aug 05 10:51:02 2009 +0100 +@@ -71,7 +71,7 @@ + obj-$(CONFIG_CNIC) += cnic.o + CFLAGS_cnic.o += -DHAVE_LE32 -DHAVE_IP_HDR -DNEW_SKB + obj-$(CONFIG_BNX2X) += bnx2x.o +-bnx2x-objs := bnx2x_main.o bnx2x_link.o ++bnx2x-objs := bnx2x_main.o bnx2x_link.o bnx2x_init_values_e1.o bnx2x_init_values_e1h.o + spidernet-y += spider_net.o spider_net_ethtool.o + obj-$(CONFIG_SPIDER_NET) += spidernet.o sungem_phy.o + obj-$(CONFIG_GELIC_NET) += ps3_gelic.o +diff -r e67cb9a8e847 drivers/net/bnx2x.h +--- a/drivers/net/bnx2x.h Wed Aug 05 10:50:39 2009 +0100 ++++ b/drivers/net/bnx2x.h Wed Aug 05 10:51:02 2009 +0100 +@@ -24,6 +24,45 @@ + #define BCM_VLAN 1 + #endif + ++#if (LINUX_VERSION_CODE >= 0x020610) /* ! BNX2X_UPSTREAM */ ++#define BCM_CNIC ++#endif ++ ++#if ((LINUX_VERSION_CODE >= 0x020617) && !defined(NETIF_F_MULTI_QUEUE)) /* BNX2X_UPSTREAM */ ++#define BNX2X_MULTI_QUEUE ++#endif ++ ++#if (LINUX_VERSION_CODE >= 0x020618) || defined(__VMKLNX__) /* BNX2X_UPSTREAM */ ++#define BNX2X_NEW_NAPI ++#endif ++ ++#if defined(BNX2X_MULTI_QUEUE) && !defined(__VMKLNX__) /* ! BNX2X_UPSTREAM */ ++#define BNX2X_SAFC ++#endif ++ ++#ifdef __VMKLNX__ /* ! BNX2X_UPSTREAM */ ++#if (VMWARE_ESX_DDK_VERSION < 40000) ++#define __NO_TPA__ 1 ++#else ++#define BCM_CNIC ++#define BNX2X_MULTI_QUEUE ++#endif ++#define KERN_CONT KERN_INFO ++#endif ++ ++#if (LINUX_VERSION_CODE > 0x02061e) /* BNX2X_UPSTREAM */ ++#include ++#endif ++#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ ++#include "bnx2x_compat.h" ++#endif ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++#include "../../bnx2/src/cnic_drv.h" ++#endif ++#include "bnx2x_reg.h" ++#include "bnx2x_fw_defs.h" ++#include "bnx2x_hsi.h" ++#include "bnx2x_link.h" + + /* error/debug prints */ + +@@ -61,6 +100,10 @@ + bp->dev ? (bp->dev->name) : "?", ##__args); \ + } while (0) + ++#define BNX2X_ERROR(__fmt, __args...) do { \ ++ printk(KERN_ERR "[%s:%d]" __fmt, __func__, __LINE__, ##__args); \ ++ } while (0) ++ + /* before we have a dev->name use dev_info() */ + #define BNX2X_DEV_INFO(__fmt, __args...) do { \ + if (bp->msglevel & NETIF_MSG_PROBE) \ +@@ -77,6 +120,7 @@ + } while (0) + #else + #define bnx2x_panic() do { \ ++ bp->panic = 1; \ + BNX2X_ERR("driver assert\n"); \ + bnx2x_panic_dump(bp); \ + } while (0) +@@ -92,12 +136,10 @@ + + #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) + #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) +-#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset)) + + #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) + #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) + #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) +-#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val) + + #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) + #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) +@@ -105,20 +147,31 @@ + #define REG_RD_DMAE(bp, offset, valp, len32) \ + do { \ + bnx2x_read_dmae(bp, offset, len32);\ +- memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \ ++ memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ + } while (0) + + #define REG_WR_DMAE(bp, offset, valp, len32) \ + do { \ +- memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \ ++ memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ + bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ + offset, len32); \ ++ } while (0) ++ ++#define VIRT_WR_DMAE_LEN(bp, data, addr, len32) \ ++ do { \ ++ memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ ++ bnx2x_write_big_buf_wb(bp, addr, len32); \ + } while (0) + + #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ + offsetof(struct shmem_region, field)) + #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) + #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) ++ ++#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ ++ offsetof(struct shmem2_region, field)) ++#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) ++#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) + + #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) + #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) +@@ -134,11 +187,19 @@ + struct sw_tx_bd { + struct sk_buff *skb; + u16 first_bd; ++ u8 flags; ++/* Set on the first BD descriptor when there is a split BD */ ++#define BNX2X_TSO_SPLIT_BD (1<<0) + }; + + struct sw_rx_page { + struct page *page; + DECLARE_PCI_UNMAP_ADDR(mapping) ++}; ++ ++union db_prod { ++ struct doorbell_set_prod data; ++ u32 raw; + }; + + +@@ -152,9 +213,7 @@ + #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) + #define SGE_PAGE_SIZE PAGE_SIZE + #define SGE_PAGE_SHIFT PAGE_SHIFT +-#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))addr) +- +-#define BCM_RX_ETH_PAYLOAD_ALIGN 64 ++#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) + + /* SGE ring related macros */ + #define NUM_RX_SGE_PAGES 2 +@@ -187,19 +246,57 @@ + #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) + + ++struct bnx2x_eth_q_stats { ++ u32 total_bytes_received_hi; ++ u32 total_bytes_received_lo; ++ u32 total_bytes_transmitted_hi; ++ u32 total_bytes_transmitted_lo; ++ u32 total_unicast_packets_received_hi; ++ u32 total_unicast_packets_received_lo; ++ u32 total_multicast_packets_received_hi; ++ u32 total_multicast_packets_received_lo; ++ u32 total_broadcast_packets_received_hi; ++ u32 total_broadcast_packets_received_lo; ++ u32 total_unicast_packets_transmitted_hi; ++ u32 total_unicast_packets_transmitted_lo; ++ u32 total_multicast_packets_transmitted_hi; ++ u32 total_multicast_packets_transmitted_lo; ++ u32 total_broadcast_packets_transmitted_hi; ++ u32 total_broadcast_packets_transmitted_lo; ++ u32 valid_bytes_received_hi; ++ u32 valid_bytes_received_lo; ++ ++ u32 error_bytes_received_hi; ++ u32 error_bytes_received_lo; ++ u32 etherstatsoverrsizepkts_hi; ++ u32 etherstatsoverrsizepkts_lo; ++ u32 no_buff_discard_hi; ++ u32 no_buff_discard_lo; ++ ++ u32 driver_xoff; ++ u32 rx_err_discard_pkt; ++ u32 rx_skb_alloc_failed; ++ u32 hw_csum_err; ++}; ++ ++#define BNX2X_NUM_Q_STATS 11 ++#define Q_STATS_OFFSET32(stat_name) \ ++ (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) ++ + struct bnx2x_fastpath { + ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ + struct napi_struct napi; ++#endif ++ ++ u8 is_rx_queue; + + struct host_status_block *status_blk; + dma_addr_t status_blk_mapping; + +- struct eth_tx_db_data *hw_tx_prods; +- dma_addr_t tx_prods_mapping; +- + struct sw_tx_bd *tx_buf_ring; + +- struct eth_tx_bd *tx_desc_ring; ++ union eth_tx_bd_types *tx_desc_ring; + dma_addr_t tx_desc_mapping; + + struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ +@@ -228,20 +325,20 @@ + u8 index; /* number in fp array */ + u8 cl_id; /* eth client id */ + u8 sb_id; /* status block number in HW */ +-#define FP_IDX(fp) (fp->index) +-#define FP_CL_ID(fp) (fp->cl_id) +-#define BP_CL_ID(bp) (bp->fp[0].cl_id) +-#define FP_SB_ID(fp) (fp->sb_id) +-#define CNIC_SB_ID 0 ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ u8 cos; ++#endif ++ ++ union db_prod tx_db; + + u16 tx_pkt_prod; + u16 tx_pkt_cons; + u16 tx_bd_prod; + u16 tx_bd_cons; +- u16 *tx_cons_sb; ++ __le16 *tx_cons_sb; + +- u16 fp_c_idx; +- u16 fp_u_idx; ++ __le16 fp_c_idx; ++ __le16 fp_u_idx; + + u16 rx_bd_prod; + u16 rx_bd_cons; +@@ -250,12 +347,36 @@ + u16 rx_sge_prod; + /* The last maximal completed SGE */ + u16 last_max_sge; +- u16 *rx_cons_sb; +- u16 *rx_bd_cons_sb; ++ __le16 *rx_cons_sb; ++ __le16 *rx_bd_cons_sb; ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */ ++ u16 netq_flags; ++#define BNX2X_NETQ_RX_QUEUE_ALLOCATED 0x0001 ++#define BNX2X_NETQ_TX_QUEUE_ALLOCATED 0x0002 ++#define BNX2X_NETQ_RX_QUEUE_ACTIVE 0x0004 ++#define BNX2X_NETQ_TX_QUEUE_ACTIVE 0x0008 ++ ++#define BNX2X_IS_NETQ_RX_QUEUE_ALLOCATED(fp) \ ++ ((fp->netq_flags & BNX2X_NETQ_RX_QUEUE_ALLOCATED) == \ ++ BNX2X_NETQ_RX_QUEUE_ALLOCATED) ++#define BNX2X_IS_NETQ_TX_QUEUE_ALLOCATED(fp) \ ++ ((fp->netq_flags & BNX2X_NETQ_TX_QUEUE_ALLOCATED) == \ ++ BNX2X_NETQ_TX_QUEUE_ALLOCATED) ++#define BNX2X_IS_NETQ_RX_QUEUE_ACTIVE(fp) \ ++ ((fp->netq_flags & BNX2X_NETQ_RX_QUEUE_ACTIVE) == \ ++ BNX2X_NETQ_RX_QUEUE_ACTIVE) ++#define BNX2X_IS_NETQ_TX_QUEUE_ACTIVE(fp) \ ++ ((fp->netq_flags & BNX2X_NETQ_TX_QUEUE_ACTIVE) == \ ++ BNX2X_NETQ_TX_QUEUE_ACTIVE) ++ ++ u8 mac_filter_addr[6]; ++#endif + + unsigned long tx_pkt, + rx_pkt, + rx_calls; ++ + /* TPA related */ + struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H]; + u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H]; +@@ -266,12 +387,21 @@ + u64 tpa_queue_used; + #endif + ++ struct tstorm_per_client_stats old_tclient; ++ struct ustorm_per_client_stats old_uclient; ++ struct xstorm_per_client_stats old_xclient; ++ struct bnx2x_eth_q_stats eth_q_stats; ++ ++ /* The size is calculated using the following: ++ sizeof name field from netdev structure + ++ 4 ('-Xx-' string) + ++ 4 (for the digits and to make it DWORD aligned) */ ++#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) ++ char name[FP_NAME_SIZE]; + struct bnx2x *bp; /* parent */ + }; + + #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) +- +-#define BNX2X_HAS_WORK(fp) (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)) + + + /* MC hsi */ +@@ -279,7 +409,7 @@ + #define RX_COPY_THRESH 92 + + #define NUM_TX_RINGS 16 +-#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd)) ++#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) + #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) + #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) + #define MAX_TX_BD (NUM_TX_BD - 1) +@@ -290,7 +420,11 @@ + #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) + + /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ ++#if !defined(__VMKLNX__) /* BNX2X_UPSTREAM */ + #define NUM_RX_RINGS 8 ++#else ++#define NUM_RX_RINGS 1 ++#endif + #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) + #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) + #define RX_DESC_MASK (RX_DESC_CNT - 1) +@@ -351,16 +485,21 @@ + #define DPM_TRIGER_TYPE 0x40 + #define DOORBELL(bp, cid, val) \ + do { \ +- writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \ ++ writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \ + DPM_TRIGER_TYPE); \ + } while (0) + + + /* TX CSUM helpers */ ++#if (LINUX_VERSION_CODE >= 0x020616) && !defined(__VMKLNX__) /* BNX2X_UPSTREAM */ + #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ + skb->csum_offset) + #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ + skb->csum_offset)) ++#else ++#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - skb->csum) ++#define SKB_CS(skb) (*(u16 *)(skb->h.raw + skb->csum)) ++#endif + + #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) + +@@ -401,10 +540,13 @@ + #define BNX2X_RX_CSUM_OK(cqe) \ + (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) + ++#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ ++ (((le16_to_cpu(flags) & \ ++ PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ ++ PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ ++ == PRS_FLAG_OVERETH_IPV4) + #define BNX2X_RX_SUM_FIX(cqe) \ +- ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \ +- PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \ +- (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT)) ++ BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) + + + #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES) +@@ -446,12 +588,24 @@ + #define CHIP_NUM_57710 0x164e + #define CHIP_NUM_57711 0x164f + #define CHIP_NUM_57711E 0x1650 ++#define CHIP_NUM_57712 0x1662 ++#define CHIP_NUM_57712E 0x1663 ++#define CHIP_NUM_57713 0x1651 ++#define CHIP_NUM_57713E 0x1652 + #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) + #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) + #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) ++#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) ++#define CHIP_IS_57712E(bp) (CHIP_NUM(bp) == CHIP_NUM_57712E) ++#define CHIP_IS_57713(bp) (CHIP_NUM(bp) == CHIP_NUM_57713) ++#define CHIP_IS_57713E(bp) (CHIP_NUM(bp) == CHIP_NUM_57713E) + #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ + CHIP_IS_57711E(bp)) + #define IS_E1H_OFFSET CHIP_IS_E1H(bp) ++#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ ++ CHIP_IS_57712E(bp) || \ ++ CHIP_IS_57713(bp) || \ ++ CHIP_IS_57713E(bp)) + + #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000) + #define CHIP_REV_Ax 0x00000000 +@@ -476,13 +630,11 @@ + #define NVRAM_PAGE_SIZE 256 + + u32 shmem_base; ++ u32 shmem2_base; + + u32 hw_config; +- u32 board; + + u32 bc_ver; +- +- char *name; + }; + + +@@ -528,6 +680,7 @@ + + /* used to synchronize phy accesses */ + struct mutex phy_mutex; ++ int need_hw_lock; + + u32 port_stx; + +@@ -573,6 +726,10 @@ + + u32 error_bytes_received_hi; + u32 error_bytes_received_lo; ++ u32 etherstatsoverrsizepkts_hi; ++ u32 etherstatsoverrsizepkts_lo; ++ u32 no_buff_discard_hi; ++ u32 no_buff_discard_lo; + + u32 rx_stat_ifhcinbadoctets_hi; + u32 rx_stat_ifhcinbadoctets_lo; +@@ -651,19 +808,20 @@ + u32 tx_stat_bmac_ufl_hi; + u32 tx_stat_bmac_ufl_lo; + +- u32 brb_drop_hi; +- u32 brb_drop_lo; +- u32 brb_truncate_hi; +- u32 brb_truncate_lo; +- +- u32 jabber_packets_received; ++ u32 pause_frames_received_hi; ++ u32 pause_frames_received_lo; ++ u32 pause_frames_sent_hi; ++ u32 pause_frames_sent_lo; + + u32 etherstatspkts1024octetsto1522octets_hi; + u32 etherstatspkts1024octetsto1522octets_lo; + u32 etherstatspktsover1522octets_hi; + u32 etherstatspktsover1522octets_lo; + +- u32 no_buff_discard; ++ u32 brb_drop_hi; ++ u32 brb_drop_lo; ++ u32 brb_truncate_hi; ++ u32 brb_truncate_lo; + + u32 mac_filter_discard; + u32 xxoverflow_discard; +@@ -674,16 +832,23 @@ + u32 rx_err_discard_pkt; + u32 rx_skb_alloc_failed; + u32 hw_csum_err; ++ ++ u32 nig_timer_max; + }; + ++#define BNX2X_NUM_STATS 41 + #define STATS_OFFSET32(stat_name) \ + (offsetof(struct bnx2x_eth_stats, stat_name) / 4) + + +-#ifdef BNX2X_MULTI ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ ++#ifdef BCM_CNIC ++#define MAX_CONTEXT 15 ++#else /* BNX2X_UPSTREAM */ + #define MAX_CONTEXT 16 ++#endif + #else +-#define MAX_CONTEXT 1 ++#define MAX_CONTEXT 2 + #endif + + union cdu_context { +@@ -708,6 +873,7 @@ + struct nig_stats nig_stats; + struct host_port_stats port_stats; + struct host_func_stats func_stats; ++ struct host_func_stats func_stats_base; + + u32 wb_comp; + u32 wb_data[4]; +@@ -738,7 +904,16 @@ + struct pci_dev *pdev; + + atomic_t intr_sem; ++#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */ ++#ifdef BCM_CNIC ++ struct msix_entry msix_table[MAX_CONTEXT+2]; ++#else /* BNX2X_UPSTREAM */ + struct msix_entry msix_table[MAX_CONTEXT+1]; ++#endif ++#endif ++#define INT_MODE_INTx 1 ++#define INT_MODE_MSI 2 ++#define INT_MODE_MSIX 3 + + int tx_ring_size; + +@@ -747,23 +922,26 @@ + #endif + + u32 rx_csum; +- u32 rx_offset; + u32 rx_buf_size; + #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */ + #define ETH_MIN_PACKET_SIZE 60 + #define ETH_MAX_PACKET_SIZE 1500 + #define ETH_MAX_JUMBO_PACKET_SIZE 9600 + ++ /* Max supported alignment is 256 (8 shift) */ ++#define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \ ++ L1_CACHE_SHIFT : 8) ++#define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT) ++ + struct host_def_status_block *def_status_blk; + #define DEF_SB_ID 16 +- u16 def_c_idx; +- u16 def_u_idx; +- u16 def_x_idx; +- u16 def_t_idx; +- u16 def_att_idx; ++ __le16 def_c_idx; ++ __le16 def_u_idx; ++ __le16 def_x_idx; ++ __le16 def_t_idx; ++ __le16 def_att_idx; + u32 attn_state; + struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; +- u32 nig_mask; + + /* slow path ring */ + struct eth_spe *spq; +@@ -771,10 +949,17 @@ + u16 spq_prod_idx; + struct eth_spe *spq_prod_bd; + struct eth_spe *spq_last_bd; +- u16 *dsb_sp_prod; ++ __le16 *dsb_sp_prod; + u16 spq_left; /* serialize spq */ + /* used to synchronize spq accesses */ + spinlock_t spq_lock; ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */ ++ /* n queues allocated */ ++ u16 n_rx_queues_allocated; ++ u16 n_tx_queues_allocated; ++ u8 netq_enabled; ++#endif + + /* Flags for marking that there is a STAT_QUERY or + SET_MAC ramrod pending */ +@@ -789,14 +974,17 @@ + u32 flags; + #define PCIX_FLAG 1 + #define PCI_32BIT_FLAG 2 +-#define ONE_TDMA_FLAG 4 /* no longer used */ ++#define ONE_PORT_FLAG 4 + #define NO_WOL_FLAG 8 + #define USING_DAC_FLAG 0x10 + #define USING_MSIX_FLAG 0x20 +-#define ASF_ENABLE_FLAG 0x40 ++#define USING_MSI_FLAG 0x40 + #define TPA_ENABLE_FLAG 0x80 + #define NO_MCP_FLAG 0x100 + #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++#define SAFC_TX_FLAG 0x200 ++#endif + #define HW_VLAN_TX_FLAG 0x400 + #define HW_VLAN_RX_FLAG 0x800 + +@@ -808,12 +996,19 @@ + + int pm_cap; + int pcie_cap; ++ int mrrs; + ++#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */ + struct delayed_work sp_task; ++#else ++ struct work_struct sp_task; ++#endif + struct work_struct reset_task; ++#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */ ++ u16 sp_running; ++#endif + + struct timer_list timer; +- int timer_interval; + int current_interval; + + u16 fw_seq; +@@ -822,9 +1017,16 @@ + + struct link_params link_params; + struct link_vars link_vars; ++ struct mdio_if_info mdio; + + struct bnx2x_common common; + struct bnx2x_port port; ++ ++ struct cmng_struct_per_port cmng; ++ u32 vn_weight_sum; ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ u32 cos_weight_sum; ++#endif + + u32 mf_config; + u16 e1hov; +@@ -848,7 +1050,7 @@ + u32 lin_cnt; + + int state; +-#define BNX2X_STATE_CLOSED 0x0 ++#define BNX2X_STATE_CLOSED 0 + #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 + #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 + #define BNX2X_STATE_OPEN 0x3000 +@@ -859,8 +1061,27 @@ + #define BNX2X_STATE_DIAG 0xe000 + #define BNX2X_STATE_ERROR 0xf000 + +- int num_queues; +-#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16) ++ int multi_mode; ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++#define BNX2X_MAX_PRIORITY 8 ++#define BNX2X_MAX_ENTRIES_PER_PRI 16 ++#define BNX2X_MAX_COS 3 ++#define BNX2X_MAX_TX_COS 2 ++ /* priority to cos mapping */ ++ u8 pri_map[BNX2X_MAX_PRIORITY]; ++ /* number of queues per cos */ ++ u8 qs_per_cos[BNX2X_MAX_COS]; ++ /* min rate per cos */ ++ u16 cos_min_rate[BNX2X_MAX_COS]; ++ /* cos to queue mapping */ ++ u8 cos_map[BNX2X_MAX_COS]; ++#endif ++ int num_rx_queues; ++ int num_tx_queues; ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++#define BNX2X_COS_QUEUES(cos) ((qs_per_cos & (0xff << cos*8)) >> cos*8) ++#define BNX2X_COS_RATE(cos) ((cos_min_rate & (0xff << cos*8)) >> cos*8) ++#endif + + u32 rx_mode; + #define BNX2X_RX_MODE_NONE 0 +@@ -875,21 +1096,35 @@ + struct bnx2x_slowpath *slowpath; + dma_addr_t slowpath_mapping; + +-#ifdef BCM_ISCSI +- void *t1; +- dma_addr_t t1_mapping; +- void *t2; +- dma_addr_t t2_mapping; +- void *timers; +- dma_addr_t timers_mapping; +- void *qm; +- dma_addr_t qm_mapping; ++ int dropless_fc; ++ ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ void *t1; ++ dma_addr_t t1_mapping; ++ void *t2; ++ dma_addr_t t2_mapping; ++ void *timers; ++ dma_addr_t timers_mapping; ++ void *qm; ++ dma_addr_t qm_mapping; ++ struct cnic_ops *cnic_ops; ++ void *cnic_data; ++ u32 cnic_tag; ++ struct cnic_eth_dev cnic_eth_dev; ++ struct host_status_block *cnic_sb; ++ dma_addr_t cnic_sb_mapping; ++#define CNIC_SB_ID(bp) BP_L_ID(bp) ++ struct eth_spe *cnic_kwq; ++ struct eth_spe *cnic_kwq_prod; ++ struct eth_spe *cnic_kwq_cons; ++ struct eth_spe *cnic_kwq_last; ++ u16 cnic_kwq_pending; ++ u16 cnic_spq_pending; + #endif + + int dmae_ready; + /* used to synchronize dmae accesses */ + struct mutex dmae_mutex; +- struct dmae_command init_dmae; + + /* used to synchronize stats collecting */ + int stats_state; +@@ -898,8 +1133,9 @@ + int executer_idx; + + u16 stats_counter; +- struct tstorm_per_client_stats old_tclient; +- struct xstorm_per_client_stats old_xclient; ++#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */ ++ struct net_device_stats net_stats; ++#endif + struct bnx2x_eth_stats eth_stats; + + struct z_stream_s *strm; +@@ -907,21 +1143,71 @@ + dma_addr_t gunzip_mapping; + int gunzip_outlen; + #define FW_BUF_SIZE 0x8000 ++#define GUNZIP_BUF(bp) bp->gunzip_buf ++#define GUNZIP_PHYS(bp) bp->gunzip_mapping ++#define GUNZIP_OUTLEN(bp) bp->gunzip_outlen + ++#if (LINUX_VERSION_CODE < 0x02060b) /* ! BNX2X_UPSTREAM */ ++ u32 pci_state[16]; ++#endif ++ struct raw_op *init_ops; ++ /* Init blocks offsets inside init_ops */ ++ u16 *init_ops_offsets; ++ /* Data blob - has 32 bit granularity */ ++ u32 *init_data; ++ /* Zipped PRAM blobs - raw data */ ++ const u8 *tsem_int_table_data; ++ const u8 *tsem_pram_data; ++ const u8 *usem_int_table_data; ++ const u8 *usem_pram_data; ++ const u8 *xsem_int_table_data; ++ const u8 *xsem_pram_data; ++ const u8 *csem_int_table_data; ++ const u8 *csem_pram_data; ++#define INIT_OPS(bp) bp->init_ops ++#define INIT_OPS_OFFSETS(bp) bp->init_ops_offsets ++#define INIT_DATA(bp) bp->init_data ++#define INIT_TSEM_INT_TABLE_DATA(bp) bp->tsem_int_table_data ++#define INIT_TSEM_PRAM_DATA(bp) bp->tsem_pram_data ++#define INIT_USEM_INT_TABLE_DATA(bp) bp->usem_int_table_data ++#define INIT_USEM_PRAM_DATA(bp) bp->usem_pram_data ++#define INIT_XSEM_INT_TABLE_DATA(bp) bp->xsem_int_table_data ++#define INIT_XSEM_PRAM_DATA(bp) bp->xsem_pram_data ++#define INIT_CSEM_INT_TABLE_DATA(bp) bp->csem_int_table_data ++#define INIT_CSEM_PRAM_DATA(bp) bp->csem_pram_data ++ ++#if defined(BNX2X_UPSTREAM) && !defined(BNX2X_USE_INIT_VALUES) /* BNX2X_UPSTREAM */ ++ const struct firmware *firmware; ++#endif + }; + + +-#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++) ++#define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT/(2 * E1HVN_MAX)) \ ++ : (MAX_CONTEXT/2)) ++#define BNX2X_NUM_QUEUES(bp) (bp->num_rx_queues + bp->num_tx_queues) ++#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 2) + ++#define for_each_rx_queue(bp, var) \ ++ for (var = 0; var < bp->num_rx_queues; var++) ++#define for_each_tx_queue(bp, var) \ ++ for (var = bp->num_rx_queues; \ ++ var < BNX2X_NUM_QUEUES(bp); var++) ++#define for_each_queue(bp, var) \ ++ for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) + #define for_each_nondefault_queue(bp, var) \ +- for (var = 1; var < bp->num_queues; var++) +-#define is_multi(bp) (bp->num_queues > 1) ++ for (var = 1; var < bp->num_rx_queues; var++) + + + void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); + void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, + u32 len32); ++int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); + int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); ++int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); ++u32 bnx2x_fw_command(struct bnx2x *bp, u32 command); ++void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val); ++void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, ++ u32 addr, u32 len); + + static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, + int wait) +@@ -979,9 +1265,9 @@ + #define DMAE_COMP_VAL 0xe0d0d0ae + + #define MAX_DMAE_C_PER_PORT 8 +-#define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \ ++#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ + BP_E1HVN(bp)) +-#define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \ ++#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ + E1HVN_MAX) + + +@@ -992,13 +1278,12 @@ + #define PCICFG_LINK_SPEED_SHIFT 16 + + +-#define BNX2X_NUM_STATS 42 +-#define BNX2X_NUM_TESTS 8 ++#define BNX2X_NUM_TESTS 7 + +-#define BNX2X_MAC_LOOPBACK 0 +-#define BNX2X_PHY_LOOPBACK 1 +-#define BNX2X_MAC_LOOPBACK_FAILED 1 +-#define BNX2X_PHY_LOOPBACK_FAILED 2 ++#define BNX2X_PHY_LOOPBACK 0 ++#define BNX2X_MAC_LOOPBACK 1 ++#define BNX2X_PHY_LOOPBACK_FAILED 1 ++#define BNX2X_MAC_LOOPBACK_FAILED 2 + #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ + BNX2X_PHY_LOOPBACK_FAILED) + +@@ -1007,7 +1292,8 @@ + + + /* must be used on a CID before placing it on a HW ring */ +-#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x) ++#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ ++ (BP_E1HVN(bp) << 17) | (x)) + + #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) + #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) +@@ -1060,9 +1346,6 @@ + + #define BNX2X_MCP_ASSERT \ + GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) +- +-#define BNX2X_DOORQ_ASSERT \ +- AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT + + #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) + #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ +@@ -1098,8 +1381,8 @@ + AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ +- AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ +- AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ ++ AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ ++ AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ +@@ -1120,13 +1403,13 @@ + AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) + + +-#define MULTI_FLAGS \ ++#define MULTI_FLAGS(bp) \ + (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ + TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ + TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ + TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ +- TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE) +- ++ (bp->multi_mode << \ ++ TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT)) + #define MULTI_MASK 0x7f + + +diff -r e67cb9a8e847 drivers/net/bnx2x_compat.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/bnx2x_compat.h Wed Aug 05 10:51:02 2009 +0100 +@@ -0,0 +1,568 @@ ++#ifndef __BNX2X_COMPAT_H__ ++#define __BNX2X_COMPAT_H__ ++ ++#ifndef __VMKLNX__ ++#define VMWARE_ESX_DDK_VERSION 0 ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x02061e) ++#define skb_record_rx_queue(skb, index) ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x020618) && (VMWARE_ESX_DDK_VERSION < 40000) ++#define napi_complete(napi) netif_rx_complete(dev) ++#define napi_schedule(napi) netif_rx_schedule(bp->dev) ++#endif ++ ++#ifndef BNX2X_MULTI_QUEUE ++#define netif_tx_wake_all_queues netif_wake_queue ++#define netif_tx_start_all_queues netif_start_queue ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x020616) ++#define skb_copy_from_linear_data_offset(skb, pad, new_skb_data, len) \ ++ memcpy(new_skb_data, skb->data + pad, len) ++ ++/* skb_buff accessors */ ++#define ip_hdr(skb) (skb)->nh.iph ++#define ipv6_hdr(skb) (skb)->nh.ipv6h ++#define ip_hdrlen(skb) (ip_hdr(skb)->ihl * 4) ++#define tcp_hdr(skb) (skb)->h.th ++#define tcp_hdrlen(skb) (tcp_hdr(skb)->doff * 4) ++#define udp_hdr(skb) (skb)->h.uh ++#define skb_mac_header(skb) ((skb)->mac.raw) ++#define skb_network_header(skb) ((skb)->nh.raw) ++#define skb_transport_header(skb) ((skb)->h.raw) ++#endif ++ ++ ++#ifndef CHECKSUM_PARTIAL ++#define CHECKSUM_PARTIAL CHECKSUM_HW ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < 0x020600) ++#define might_sleep() ++ ++#define num_online_cpus() 1 ++ ++#define dev_info(dev, format, args...) \ ++ printk(KERN_INFO "bnx2x: " format, ##args) ++ ++#define dev_err(dev, format, args...) \ ++ printk(KERN_ERR "bnx2x: " format, ##args) ++ ++static inline int dma_mapping_error(dma_addr_t mapping) ++{ ++ return 0; ++} ++ ++#define synchronize_irq(X) synchronize_irq() ++#define flush_scheduled_work() ++#endif ++ ++ ++#ifndef SET_MODULE_OWNER ++#define SET_MODULE_OWNER(dev) ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < 0x020604) ++#define MODULE_VERSION(version) ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < 0x020605) ++static inline void pci_dma_sync_single_for_device(struct pci_dev *dev, ++ dma_addr_t map, size_t size, ++ int dir) ++{ ++} ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < 0x020547) ++#define pci_set_consistent_dma_mask(X, Y) (0) ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < 0x020607) ++#define msleep(x) \ ++ do { \ ++ current->state = TASK_UNINTERRUPTIBLE; \ ++ schedule_timeout((HZ * (x)) / 1000); \ ++ } while (0) ++ ++#ifndef ADVERTISE_1000XPAUSE ++static inline struct mii_ioctl_data *if_mii(struct ifreq *rq) ++{ ++ return (struct mii_ioctl_data *)&rq->ifr_ifru; ++} ++#endif ++ ++#define pci_enable_msix(X, Y, Z) (-1) ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < 0x020609) ++#define msleep_interruptible(x) \ ++ do{ \ ++ current->state = TASK_INTERRUPTIBLE; \ ++ schedule_timeout((HZ * (x)) / 1000); \ ++ } while (0) ++ ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < 0x02060b) ++#define pm_message_t u32 ++#define pci_power_t u32 ++#define PCI_D0 0 ++#define PCI_D3hot 3 ++#define pci_choose_state(pdev, state) state ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < 0x02060e) ++#define touch_softlockup_watchdog() ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < 0x020612) ++static inline struct sk_buff *netdev_alloc_skb(struct net_device *dev, ++ unsigned int length) ++{ ++ struct sk_buff *skb = dev_alloc_skb(length); ++ ++ if (skb) ++ skb->dev = dev; ++ return skb; ++} ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < 0x020614) ++#define PCI_VDEVICE(vendor, device) \ ++ PCI_VENDOR_ID_##vendor, (device), \ ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0 ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x020615) ++#define vlan_group_set_device(vg, vlan_id, dev) vg->vlan_devices[vlan_id] = dev ++#endif ++ ++ ++#ifndef IRQ_RETVAL ++typedef void irqreturn_t; ++#define IRQ_HANDLED ++#define IRQ_NONE ++#endif ++ ++ ++#ifndef IRQF_SHARED ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++ ++#ifndef NETIF_F_GSO ++static inline void netif_tx_lock(struct net_device *dev) ++{ ++ spin_lock(&dev->xmit_lock); ++ dev->xmit_lock_owner = smp_processor_id(); ++} ++ ++static inline void netif_tx_unlock(struct net_device *dev) ++{ ++ dev->xmit_lock_owner = -1; ++ spin_unlock(&dev->xmit_lock); ++} ++#endif ++ ++ ++#ifndef skb_shinfo ++#define skb_shinfo(SKB) ((struct skb_shared_info *)(skb_end_pointer(SKB))) ++#endif ++ ++ ++#ifdef NETIF_F_TSO ++#ifndef NETIF_F_GSO ++ ++static inline int skb_is_gso(const struct sk_buff *skb) ++{ ++ return skb_shinfo(skb)->tso_size; ++} ++ ++#define gso_size tso_size ++ ++#endif /* NETIF_F_GSO */ ++ ++#ifndef NETIF_F_GSO_SOFTWARE ++#define NETIF_F_GSO_SOFTWARE (NETIF_F_TSO) ++#endif ++ ++#endif /* NETIF_F_TSO */ ++ ++#ifndef NETIF_F_TSO_ECN ++#define NETIF_F_TSO_ECN 0 ++#endif ++ ++ ++#if !defined(mmiowb) ++#define mmiowb() ++#endif ++ ++#if !defined(__iomem) ++#define __iomem ++#endif ++ ++#ifndef noinline ++#define noinline ++#endif ++ ++#if !defined(INIT_WORK) ++#define INIT_WORK INIT_TQUEUE ++#define schedule_work schedule_task ++#define work_struct tq_struct ++#endif ++ ++#if !defined(HAVE_NETDEV_PRIV) && (LINUX_VERSION_CODE != 0x020603) && (LINUX_VERSION_CODE != 0x020604) && (LINUX_VERSION_CODE != 0x020605) ++#define netdev_priv(dev) (dev)->priv ++#endif ++ ++/* Missing defines */ ++#ifndef SPEED_2500 ++#define SPEED_2500 2500 ++#endif ++ ++#ifndef SUPPORTED_Pause ++#define SUPPORTED_Pause (1 << 13) ++#endif ++#ifndef SUPPORTED_Asym_Pause ++#define SUPPORTED_Asym_Pause (1 << 14) ++#endif ++ ++#ifndef ADVERTISED_Pause ++#define ADVERTISED_Pause (1 << 13) ++#endif ++ ++#ifndef ADVERTISED_Asym_Pause ++#define ADVERTISED_Asym_Pause (1 << 14) ++#endif ++ ++#ifndef NETDEV_TX_BUSY ++#define NETDEV_TX_BUSY 1 /* driver tx path was busy */ ++#endif ++ ++#ifndef NETDEV_TX_OK ++#define NETDEV_TX_OK 0 /* driver took care of packet */ ++#endif ++ ++#ifndef DMA_BIT_MASK ++#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) ++#endif ++ ++#ifndef PCI_CAP_ID_EXP ++#define PCI_CAP_ID_EXP 0x10 ++#endif ++ ++#ifndef PCI_EXP_DEVCTL ++#define PCI_EXP_DEVCTL 8 /* Device Control */ ++#endif ++ ++#ifndef PCI_EXP_DEVCTL_PAYLOAD ++#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ ++#endif ++ ++#ifndef PCI_EXP_DEVCTL_READRQ ++#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < 0x020618) ++ ++#ifndef NETIF_F_HW_CSUM ++#define NETIF_F_HW_CSUM 8 ++#endif ++ ++static inline int bnx2x_set_tx_hw_csum(struct net_device *dev, u32 data) ++{ ++ if (data) ++ dev->features |= NETIF_F_HW_CSUM; ++ else ++ dev->features &= ~NETIF_F_HW_CSUM; ++ return 0; ++} ++#endif ++ ++ ++/* If mutex is not available, use semaphore */ ++#ifndef __LINUX_MUTEX_H ++#define mutex semaphore ++#define mutex_lock(x) down(x) ++#define mutex_unlock(x) up(x) ++#define mutex_init(x) sema_init(x,1) ++#endif ++ ++ ++#ifndef KERN_CONT ++#define KERN_CONT "" ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < 0x020619) ++#define le16_add_cpu(var, val) *var = cpu_to_le16(le16_to_cpup(var) + val) ++#define le32_add_cpu(var, val) *var = cpu_to_le32(le32_to_cpup(var) + val) ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < 0x02061b) || defined(BNX2X_DRIVER_DISK) || defined(__VMKLNX__) ++ ++/* ++ * This is the CRC-32C table ++ * Generated with: ++ * width = 32 bits ++ * poly = 0x1EDC6F41 ++ * reflect input bytes = true ++ * reflect output bytes = true ++ */ ++ ++static u32 crc32c_table[256] = { ++ 0x00000000L, 0xF26B8303L, 0xE13B70F7L, 0x1350F3F4L, ++ 0xC79A971FL, 0x35F1141CL, 0x26A1E7E8L, 0xD4CA64EBL, ++ 0x8AD958CFL, 0x78B2DBCCL, 0x6BE22838L, 0x9989AB3BL, ++ 0x4D43CFD0L, 0xBF284CD3L, 0xAC78BF27L, 0x5E133C24L, ++ 0x105EC76FL, 0xE235446CL, 0xF165B798L, 0x030E349BL, ++ 0xD7C45070L, 0x25AFD373L, 0x36FF2087L, 0xC494A384L, ++ 0x9A879FA0L, 0x68EC1CA3L, 0x7BBCEF57L, 0x89D76C54L, ++ 0x5D1D08BFL, 0xAF768BBCL, 0xBC267848L, 0x4E4DFB4BL, ++ 0x20BD8EDEL, 0xD2D60DDDL, 0xC186FE29L, 0x33ED7D2AL, ++ 0xE72719C1L, 0x154C9AC2L, 0x061C6936L, 0xF477EA35L, ++ 0xAA64D611L, 0x580F5512L, 0x4B5FA6E6L, 0xB93425E5L, ++ 0x6DFE410EL, 0x9F95C20DL, 0x8CC531F9L, 0x7EAEB2FAL, ++ 0x30E349B1L, 0xC288CAB2L, 0xD1D83946L, 0x23B3BA45L, ++ 0xF779DEAEL, 0x05125DADL, 0x1642AE59L, 0xE4292D5AL, ++ 0xBA3A117EL, 0x4851927DL, 0x5B016189L, 0xA96AE28AL, ++ 0x7DA08661L, 0x8FCB0562L, 0x9C9BF696L, 0x6EF07595L, ++ 0x417B1DBCL, 0xB3109EBFL, 0xA0406D4BL, 0x522BEE48L, ++ 0x86E18AA3L, 0x748A09A0L, 0x67DAFA54L, 0x95B17957L, ++ 0xCBA24573L, 0x39C9C670L, 0x2A993584L, 0xD8F2B687L, ++ 0x0C38D26CL, 0xFE53516FL, 0xED03A29BL, 0x1F682198L, ++ 0x5125DAD3L, 0xA34E59D0L, 0xB01EAA24L, 0x42752927L, ++ 0x96BF4DCCL, 0x64D4CECFL, 0x77843D3BL, 0x85EFBE38L, ++ 0xDBFC821CL, 0x2997011FL, 0x3AC7F2EBL, 0xC8AC71E8L, ++ 0x1C661503L, 0xEE0D9600L, 0xFD5D65F4L, 0x0F36E6F7L, ++ 0x61C69362L, 0x93AD1061L, 0x80FDE395L, 0x72966096L, ++ 0xA65C047DL, 0x5437877EL, 0x4767748AL, 0xB50CF789L, ++ 0xEB1FCBADL, 0x197448AEL, 0x0A24BB5AL, 0xF84F3859L, ++ 0x2C855CB2L, 0xDEEEDFB1L, 0xCDBE2C45L, 0x3FD5AF46L, ++ 0x7198540DL, 0x83F3D70EL, 0x90A324FAL, 0x62C8A7F9L, ++ 0xB602C312L, 0x44694011L, 0x5739B3E5L, 0xA55230E6L, ++ 0xFB410CC2L, 0x092A8FC1L, 0x1A7A7C35L, 0xE811FF36L, ++ 0x3CDB9BDDL, 0xCEB018DEL, 0xDDE0EB2AL, 0x2F8B6829L, ++ 0x82F63B78L, 0x709DB87BL, 0x63CD4B8FL, 0x91A6C88CL, ++ 0x456CAC67L, 0xB7072F64L, 0xA457DC90L, 0x563C5F93L, ++ 0x082F63B7L, 0xFA44E0B4L, 0xE9141340L, 0x1B7F9043L, ++ 0xCFB5F4A8L, 0x3DDE77ABL, 0x2E8E845FL, 0xDCE5075CL, ++ 0x92A8FC17L, 0x60C37F14L, 0x73938CE0L, 0x81F80FE3L, ++ 0x55326B08L, 0xA759E80BL, 0xB4091BFFL, 0x466298FCL, ++ 0x1871A4D8L, 0xEA1A27DBL, 0xF94AD42FL, 0x0B21572CL, ++ 0xDFEB33C7L, 0x2D80B0C4L, 0x3ED04330L, 0xCCBBC033L, ++ 0xA24BB5A6L, 0x502036A5L, 0x4370C551L, 0xB11B4652L, ++ 0x65D122B9L, 0x97BAA1BAL, 0x84EA524EL, 0x7681D14DL, ++ 0x2892ED69L, 0xDAF96E6AL, 0xC9A99D9EL, 0x3BC21E9DL, ++ 0xEF087A76L, 0x1D63F975L, 0x0E330A81L, 0xFC588982L, ++ 0xB21572C9L, 0x407EF1CAL, 0x532E023EL, 0xA145813DL, ++ 0x758FE5D6L, 0x87E466D5L, 0x94B49521L, 0x66DF1622L, ++ 0x38CC2A06L, 0xCAA7A905L, 0xD9F75AF1L, 0x2B9CD9F2L, ++ 0xFF56BD19L, 0x0D3D3E1AL, 0x1E6DCDEEL, 0xEC064EEDL, ++ 0xC38D26C4L, 0x31E6A5C7L, 0x22B65633L, 0xD0DDD530L, ++ 0x0417B1DBL, 0xF67C32D8L, 0xE52CC12CL, 0x1747422FL, ++ 0x49547E0BL, 0xBB3FFD08L, 0xA86F0EFCL, 0x5A048DFFL, ++ 0x8ECEE914L, 0x7CA56A17L, 0x6FF599E3L, 0x9D9E1AE0L, ++ 0xD3D3E1ABL, 0x21B862A8L, 0x32E8915CL, 0xC083125FL, ++ 0x144976B4L, 0xE622F5B7L, 0xF5720643L, 0x07198540L, ++ 0x590AB964L, 0xAB613A67L, 0xB831C993L, 0x4A5A4A90L, ++ 0x9E902E7BL, 0x6CFBAD78L, 0x7FAB5E8CL, 0x8DC0DD8FL, ++ 0xE330A81AL, 0x115B2B19L, 0x020BD8EDL, 0xF0605BEEL, ++ 0x24AA3F05L, 0xD6C1BC06L, 0xC5914FF2L, 0x37FACCF1L, ++ 0x69E9F0D5L, 0x9B8273D6L, 0x88D28022L, 0x7AB90321L, ++ 0xAE7367CAL, 0x5C18E4C9L, 0x4F48173DL, 0xBD23943EL, ++ 0xF36E6F75L, 0x0105EC76L, 0x12551F82L, 0xE03E9C81L, ++ 0x34F4F86AL, 0xC69F7B69L, 0xD5CF889DL, 0x27A40B9EL, ++ 0x79B737BAL, 0x8BDCB4B9L, 0x988C474DL, 0x6AE7C44EL, ++ 0xBE2DA0A5L, 0x4C4623A6L, 0x5F16D052L, 0xAD7D5351L ++}; ++ ++/* ++ * Steps through buffer one byte at at time, calculates reflected ++ * crc using table. ++ */ ++ ++static inline u32 /*__attribute_pure__*/ ++crc32c_le(u32 seed, unsigned char const *data, size_t length) ++{ ++ __le32 crc = __cpu_to_le32(seed); ++ ++ while (length--) ++ crc = crc32c_table[(crc ^ *data++) & 0xFFL] ^ (crc >> 8); ++ ++ return __le32_to_cpu(crc); ++} ++#endif ++ ++/* Taken from drivers/net/mdio.c */ ++#if (LINUX_VERSION_CODE < 0x02061f) ++#include ++ ++/* MDIO Manageable Devices (MMDs). */ ++#define MDIO_MMD_AN 7 /* Auto-Negotiation */ ++ ++/* Generic MDIO registers. */ ++#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */ ++#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */ ++ ++/* Device present registers. */ ++#define MDIO_DEVS_PRESENT(devad) (1 << (devad)) ++#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN) ++ ++/** ++ * struct mdio_if_info - Ethernet controller MDIO interface ++ * @prtad: PRTAD of the PHY (%MDIO_PRTAD_NONE if not present/unknown) ++ * @mmds: Mask of MMDs expected to be present in the PHY. This must be ++ * non-zero unless @prtad = %MDIO_PRTAD_NONE. ++ * @mode_support: MDIO modes supported. If %MDIO_SUPPORTS_C22 is set then ++ * MII register access will be passed through with @devad = ++ * %MDIO_DEVAD_NONE. If %MDIO_EMULATE_C22 is set then access to ++ * commonly used clause 22 registers will be translated into ++ * clause 45 registers. ++ * @dev: Net device structure ++ * @mdio_read: Register read function; returns value or negative error code ++ * @mdio_write: Register write function; returns 0 or negative error code ++ */ ++struct mdio_if_info { ++ int prtad; ++ u32 __bitwise mmds; ++ unsigned mode_support; ++ ++ struct net_device *dev; ++ int (*mdio_read)(struct net_device *dev, int prtad, int devad, ++ u16 addr); ++ int (*mdio_write)(struct net_device *dev, int prtad, int devad, ++ u16 addr, u16 val); ++}; ++ ++#define MDIO_PRTAD_NONE (-1) ++#define MDIO_DEVAD_NONE (-1) ++#define MDIO_EMULATE_C22 4 ++ ++/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */ ++ ++#define MDIO_PHY_ID_C45 0x8000 ++#define MDIO_PHY_ID_PRTAD 0x03e0 ++#define MDIO_PHY_ID_DEVAD 0x001f ++#define MDIO_PHY_ID_C45_MASK \ ++ (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD) ++ ++static inline int mdio_phy_id_is_c45(int phy_id) ++{ ++ return (phy_id & MDIO_PHY_ID_C45) && !(phy_id & ~MDIO_PHY_ID_C45_MASK); ++} ++ ++static inline __u16 mdio_phy_id_prtad(int phy_id) ++{ ++ return (phy_id & MDIO_PHY_ID_PRTAD) >> 5; ++} ++ ++static inline __u16 mdio_phy_id_devad(int phy_id) ++{ ++ return phy_id & MDIO_PHY_ID_DEVAD; ++} ++ ++#define MDIO_SUPPORTS_C22 1 ++#define MDIO_SUPPORTS_C45 2 ++ ++/** ++ * mdio_mii_ioctl - MII ioctl interface for MDIO (clause 22 or 45) PHYs ++ * @mdio: MDIO interface ++ * @mii_data: MII ioctl data structure ++ * @cmd: MII ioctl command ++ * ++ * Returns 0 on success, negative on error. ++ */ ++static inline int mdio_mii_ioctl(const struct mdio_if_info *mdio, ++ struct mii_ioctl_data *mii_data, int cmd) ++{ ++ int prtad, devad; ++ u16 addr = mii_data->reg_num; ++ ++ /* Validate/convert cmd to one of SIOC{G,S}MIIREG */ ++ switch (cmd) { ++ case SIOCGMIIPHY: ++ if (mdio->prtad == MDIO_PRTAD_NONE) ++ return -EOPNOTSUPP; ++ mii_data->phy_id = mdio->prtad; ++ cmd = SIOCGMIIREG; ++ break; ++ case SIOCGMIIREG: ++ break; ++ case SIOCSMIIREG: ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ /* Validate/convert phy_id */ ++ if ((mdio->mode_support & MDIO_SUPPORTS_C45) && ++ mdio_phy_id_is_c45(mii_data->phy_id)) { ++ prtad = mdio_phy_id_prtad(mii_data->phy_id); ++ devad = mdio_phy_id_devad(mii_data->phy_id); ++ } else if ((mdio->mode_support & MDIO_SUPPORTS_C22) && ++ mii_data->phy_id < 0x20) { ++ prtad = mii_data->phy_id; ++ devad = MDIO_DEVAD_NONE; ++ addr &= 0x1f; ++ } else if ((mdio->mode_support & MDIO_EMULATE_C22) && ++ mdio->prtad != MDIO_PRTAD_NONE && ++ mii_data->phy_id == mdio->prtad) { ++ /* Remap commonly-used MII registers. */ ++ prtad = mdio->prtad; ++ switch (addr) { ++ case MII_BMCR: ++ case MII_BMSR: ++ case MII_PHYSID1: ++ case MII_PHYSID2: ++ devad = __ffs(mdio->mmds); ++ break; ++ case MII_ADVERTISE: ++ case MII_LPA: ++ if (!(mdio->mmds & MDIO_DEVS_AN)) ++ return -EINVAL; ++ devad = MDIO_MMD_AN; ++ if (addr == MII_ADVERTISE) ++ addr = MDIO_AN_ADVERTISE; ++ else ++ addr = MDIO_AN_LPA; ++ break; ++ default: ++ return -EINVAL; ++ } ++ } else { ++ return -EINVAL; ++ } ++ ++ if (cmd == SIOCGMIIREG) { ++ int rc = mdio->mdio_read(mdio->dev, prtad, devad, addr); ++ if (rc < 0) ++ return rc; ++ mii_data->val_out = rc; ++ return 0; ++ } else { ++ return mdio->mdio_write(mdio->dev, prtad, devad, addr, ++ mii_data->val_in); ++ } ++} ++#endif ++ ++#endif /* __BNX2X_COMPAT_H__ */ +diff -r e67cb9a8e847 drivers/net/bnx2x_dump.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/bnx2x_dump.h Wed Aug 05 10:51:02 2009 +0100 +@@ -0,0 +1,542 @@ ++/* bnx2x_dump.h: Broadcom Everest network driver. ++ * ++ * Copyright (c) 2009 Broadcom Corporation ++ * ++ * Unless you and Broadcom execute a separate written software license ++ * agreement governing use of this software, this software is licensed to you ++ * under the terms of the GNU General Public License version 2, available ++ * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). ++ * ++ * Notwithstanding the above, under no circumstances may you combine this ++ * software in any way with any other Broadcom software provided under a ++ * license other than the GPL, without Broadcom's express prior written ++ * consent. ++ * ++ * Written by: Yitchak Gertner ++ */ ++ ++ ++/* This struct holds a signature to ensure the dump returned from the driver ++ * match the meta data file inserted to grc_dump.tcl ++ * The signature is time stamp, diag version and grc_dump version ++ */ ++ ++#ifndef BNX2X_DUMP_H ++#define BNX2X_DUMP_H ++ ++ ++struct dump_sign { ++ u32 time_stamp; ++ u32 diag_ver; ++ u32 grc_dump_ver; ++}; ++ ++#define TSTORM_WAITP_ADDR 0x1b8a80 ++#define CSTORM_WAITP_ADDR 0x238a80 ++#define XSTORM_WAITP_ADDR 0x2b8a80 ++#define USTORM_WAITP_ADDR 0x338a80 ++#define TSTORM_CAM_MODE 0x1b1440 ++ ++#define RI_E1 0x1 ++#define RI_E1H 0x2 ++#define RI_ONLINE 0x100 ++ ++#define RI_E1_OFFLINE (RI_E1) ++#define RI_E1_ONLINE (RI_E1 | RI_ONLINE) ++#define RI_E1H_OFFLINE (RI_E1H) ++#define RI_E1H_ONLINE (RI_E1H | RI_ONLINE) ++#define RI_ALL_OFFLINE (RI_E1 | RI_E1H) ++#define RI_ALL_ONLINE (RI_E1 | RI_E1H | RI_ONLINE) ++ ++#define MAX_TIMER_PENDING 200 ++#define TIMER_SCAN_DONT_CARE 0xFF ++ ++ ++struct dump_hdr { ++ u32 hdr_size; /* in dwords, excluding this field */ ++ struct dump_sign dump_sign; ++ u32 xstorm_waitp; ++ u32 tstorm_waitp; ++ u32 ustorm_waitp; ++ u32 cstorm_waitp; ++ u16 info; ++ u8 idle_chk; ++ u8 reserved; ++}; ++ ++struct reg_addr { ++ u32 addr; ++ u32 size; ++ u16 info; ++}; ++ ++struct wreg_addr { ++ u32 addr; ++ u32 size; ++ u32 read_regs_count; ++ const u32 *read_regs; ++ u16 info; ++}; ++ ++ ++#define REGS_COUNT 558 ++static const struct reg_addr reg_addrs[REGS_COUNT] = { ++ { 0x2000, 341, RI_ALL_ONLINE }, { 0x2800, 103, RI_ALL_ONLINE }, ++ { 0x3000, 287, RI_ALL_ONLINE }, { 0x3800, 331, RI_ALL_ONLINE }, ++ { 0x8800, 6, RI_E1_ONLINE }, { 0xa000, 223, RI_ALL_ONLINE }, ++ { 0xa388, 1, RI_ALL_ONLINE }, { 0xa398, 1, RI_ALL_ONLINE }, ++ { 0xa39c, 7, RI_E1H_ONLINE }, { 0xa3c0, 3, RI_E1H_ONLINE }, ++ { 0xa3d0, 1, RI_E1H_ONLINE }, { 0xa3d8, 1, RI_E1H_ONLINE }, ++ { 0xa3e0, 1, RI_E1H_ONLINE }, { 0xa3e8, 1, RI_E1H_ONLINE }, ++ { 0xa3f0, 1, RI_E1H_ONLINE }, { 0xa3f8, 1, RI_E1H_ONLINE }, ++ { 0xa400, 69, RI_ALL_ONLINE }, { 0xa518, 1, RI_ALL_ONLINE }, ++ { 0xa520, 1, RI_ALL_ONLINE }, { 0xa528, 1, RI_ALL_ONLINE }, ++ { 0xa530, 1, RI_ALL_ONLINE }, { 0xa538, 1, RI_ALL_ONLINE }, ++ { 0xa540, 1, RI_ALL_ONLINE }, { 0xa548, 1, RI_ALL_ONLINE }, ++ { 0xa550, 1, RI_ALL_ONLINE }, { 0xa558, 1, RI_ALL_ONLINE }, ++ { 0xa560, 1, RI_ALL_ONLINE }, { 0xa568, 1, RI_ALL_ONLINE }, ++ { 0xa570, 1, RI_ALL_ONLINE }, { 0xa580, 1, RI_ALL_ONLINE }, ++ { 0xa590, 1, RI_ALL_ONLINE }, { 0xa5a0, 1, RI_ALL_ONLINE }, ++ { 0xa5c0, 1, RI_ALL_ONLINE }, { 0xa5e0, 1, RI_E1H_ONLINE }, ++ { 0xa5e8, 1, RI_E1H_ONLINE }, { 0xa5f0, 1, RI_E1H_ONLINE }, ++ { 0xa5f8, 10, RI_E1H_ONLINE }, { 0x10000, 236, RI_ALL_ONLINE }, ++ { 0x103bc, 1, RI_ALL_ONLINE }, { 0x103cc, 1, RI_ALL_ONLINE }, ++ { 0x103dc, 1, RI_ALL_ONLINE }, { 0x10400, 57, RI_ALL_ONLINE }, ++ { 0x104e8, 2, RI_ALL_ONLINE }, { 0x104f4, 2, RI_ALL_ONLINE }, ++ { 0x10500, 146, RI_ALL_ONLINE }, { 0x10750, 2, RI_ALL_ONLINE }, ++ { 0x10760, 2, RI_ALL_ONLINE }, { 0x10770, 2, RI_ALL_ONLINE }, ++ { 0x10780, 2, RI_ALL_ONLINE }, { 0x10790, 2, RI_ALL_ONLINE }, ++ { 0x107a0, 2, RI_ALL_ONLINE }, { 0x107b0, 2, RI_ALL_ONLINE }, ++ { 0x107c0, 2, RI_ALL_ONLINE }, { 0x107d0, 2, RI_ALL_ONLINE }, ++ { 0x107e0, 2, RI_ALL_ONLINE }, { 0x10880, 2, RI_ALL_ONLINE }, ++ { 0x10900, 2, RI_ALL_ONLINE }, { 0x12000, 1, RI_ALL_ONLINE }, ++ { 0x14000, 1, RI_ALL_ONLINE }, { 0x16000, 26, RI_E1H_ONLINE }, ++ { 0x16070, 18, RI_E1H_ONLINE }, { 0x160c0, 27, RI_E1H_ONLINE }, ++ { 0x16140, 1, RI_E1H_ONLINE }, { 0x16160, 1, RI_E1H_ONLINE }, ++ { 0x16180, 2, RI_E1H_ONLINE }, { 0x161c0, 2, RI_E1H_ONLINE }, ++ { 0x16204, 5, RI_E1H_ONLINE }, { 0x18000, 1, RI_E1H_ONLINE }, ++ { 0x18008, 1, RI_E1H_ONLINE }, { 0x20000, 24, RI_ALL_ONLINE }, ++ { 0x20060, 8, RI_ALL_ONLINE }, { 0x20080, 138, RI_ALL_ONLINE }, ++ { 0x202b4, 1, RI_ALL_ONLINE }, { 0x202c4, 1, RI_ALL_ONLINE }, ++ { 0x20400, 2, RI_ALL_ONLINE }, { 0x2040c, 8, RI_ALL_ONLINE }, ++ { 0x2042c, 18, RI_E1H_ONLINE }, { 0x20480, 1, RI_ALL_ONLINE }, ++ { 0x20500, 1, RI_ALL_ONLINE }, { 0x20600, 1, RI_ALL_ONLINE }, ++ { 0x28000, 1, RI_ALL_ONLINE }, { 0x28004, 8191, RI_ALL_OFFLINE }, ++ { 0x30000, 1, RI_ALL_ONLINE }, { 0x30004, 16383, RI_ALL_OFFLINE }, ++ { 0x40000, 98, RI_ALL_ONLINE }, { 0x40194, 1, RI_ALL_ONLINE }, ++ { 0x401a4, 1, RI_ALL_ONLINE }, { 0x401a8, 11, RI_E1H_ONLINE }, ++ { 0x40200, 4, RI_ALL_ONLINE }, { 0x40400, 43, RI_ALL_ONLINE }, ++ { 0x404b8, 1, RI_ALL_ONLINE }, { 0x404c8, 1, RI_ALL_ONLINE }, ++ { 0x404cc, 3, RI_E1H_ONLINE }, { 0x40500, 2, RI_ALL_ONLINE }, ++ { 0x40510, 2, RI_ALL_ONLINE }, { 0x40520, 2, RI_ALL_ONLINE }, ++ { 0x40530, 2, RI_ALL_ONLINE }, { 0x40540, 2, RI_ALL_ONLINE }, ++ { 0x42000, 164, RI_ALL_ONLINE }, { 0x4229c, 1, RI_ALL_ONLINE }, ++ { 0x422ac, 1, RI_ALL_ONLINE }, { 0x422bc, 1, RI_ALL_ONLINE }, ++ { 0x422d4, 5, RI_E1H_ONLINE }, { 0x42400, 49, RI_ALL_ONLINE }, ++ { 0x424c8, 38, RI_ALL_ONLINE }, { 0x42568, 2, RI_ALL_ONLINE }, ++ { 0x42800, 1, RI_ALL_ONLINE }, { 0x50000, 20, RI_ALL_ONLINE }, ++ { 0x50050, 8, RI_ALL_ONLINE }, { 0x50070, 88, RI_ALL_ONLINE }, ++ { 0x501dc, 1, RI_ALL_ONLINE }, { 0x501ec, 1, RI_ALL_ONLINE }, ++ { 0x501f0, 4, RI_E1H_ONLINE }, { 0x50200, 2, RI_ALL_ONLINE }, ++ { 0x5020c, 7, RI_ALL_ONLINE }, { 0x50228, 6, RI_E1H_ONLINE }, ++ { 0x50240, 1, RI_ALL_ONLINE }, { 0x50280, 1, RI_ALL_ONLINE }, ++ { 0x52000, 1, RI_ALL_ONLINE }, { 0x54000, 1, RI_ALL_ONLINE }, ++ { 0x54004, 3327, RI_ALL_OFFLINE }, { 0x58000, 1, RI_ALL_ONLINE }, ++ { 0x58004, 8191, RI_ALL_OFFLINE }, { 0x60000, 71, RI_ALL_ONLINE }, ++ { 0x60128, 1, RI_ALL_ONLINE }, { 0x60138, 1, RI_ALL_ONLINE }, ++ { 0x6013c, 24, RI_E1H_ONLINE }, { 0x60200, 1, RI_ALL_ONLINE }, ++ { 0x61000, 1, RI_ALL_ONLINE }, { 0x61004, 511, RI_ALL_OFFLINE }, ++ { 0x70000, 8, RI_ALL_ONLINE }, { 0x70020, 21496, RI_ALL_OFFLINE }, ++ { 0x85000, 3, RI_ALL_ONLINE }, { 0x8500c, 4, RI_ALL_OFFLINE }, ++ { 0x8501c, 7, RI_ALL_ONLINE }, { 0x85038, 4, RI_ALL_OFFLINE }, ++ { 0x85048, 1, RI_ALL_ONLINE }, { 0x8504c, 109, RI_ALL_OFFLINE }, ++ { 0x85200, 32, RI_ALL_ONLINE }, { 0x85280, 11104, RI_ALL_OFFLINE }, ++ { 0xa0000, 16384, RI_ALL_ONLINE }, { 0xb0000, 16384, RI_E1H_ONLINE }, ++ { 0xc1000, 7, RI_ALL_ONLINE }, { 0xc1028, 1, RI_ALL_ONLINE }, ++ { 0xc1038, 1, RI_ALL_ONLINE }, { 0xc1800, 2, RI_ALL_ONLINE }, ++ { 0xc2000, 164, RI_ALL_ONLINE }, { 0xc229c, 1, RI_ALL_ONLINE }, ++ { 0xc22ac, 1, RI_ALL_ONLINE }, { 0xc22bc, 1, RI_ALL_ONLINE }, ++ { 0xc2400, 49, RI_ALL_ONLINE }, { 0xc24c8, 38, RI_ALL_ONLINE }, ++ { 0xc2568, 2, RI_ALL_ONLINE }, { 0xc2600, 1, RI_ALL_ONLINE }, ++ { 0xc4000, 165, RI_ALL_ONLINE }, { 0xc42a0, 1, RI_ALL_ONLINE }, ++ { 0xc42b0, 1, RI_ALL_ONLINE }, { 0xc42c0, 1, RI_ALL_ONLINE }, ++ { 0xc42e0, 7, RI_E1H_ONLINE }, { 0xc4400, 51, RI_ALL_ONLINE }, ++ { 0xc44d0, 38, RI_ALL_ONLINE }, { 0xc4570, 2, RI_ALL_ONLINE }, ++ { 0xc4600, 1, RI_ALL_ONLINE }, { 0xd0000, 19, RI_ALL_ONLINE }, ++ { 0xd004c, 8, RI_ALL_ONLINE }, { 0xd006c, 91, RI_ALL_ONLINE }, ++ { 0xd01e4, 1, RI_ALL_ONLINE }, { 0xd01f4, 1, RI_ALL_ONLINE }, ++ { 0xd0200, 2, RI_ALL_ONLINE }, { 0xd020c, 7, RI_ALL_ONLINE }, ++ { 0xd0228, 18, RI_E1H_ONLINE }, { 0xd0280, 1, RI_ALL_ONLINE }, ++ { 0xd0300, 1, RI_ALL_ONLINE }, { 0xd0400, 1, RI_ALL_ONLINE }, ++ { 0xd4000, 1, RI_ALL_ONLINE }, { 0xd4004, 2559, RI_ALL_OFFLINE }, ++ { 0xd8000, 1, RI_ALL_ONLINE }, { 0xd8004, 8191, RI_ALL_OFFLINE }, ++ { 0xe0000, 21, RI_ALL_ONLINE }, { 0xe0054, 8, RI_ALL_ONLINE }, ++ { 0xe0074, 85, RI_ALL_ONLINE }, { 0xe01d4, 1, RI_ALL_ONLINE }, ++ { 0xe01e4, 1, RI_ALL_ONLINE }, { 0xe0200, 2, RI_ALL_ONLINE }, ++ { 0xe020c, 8, RI_ALL_ONLINE }, { 0xe022c, 18, RI_E1H_ONLINE }, ++ { 0xe0280, 1, RI_ALL_ONLINE }, { 0xe0300, 1, RI_ALL_ONLINE }, ++ { 0xe1000, 1, RI_ALL_ONLINE }, { 0xe2000, 1, RI_ALL_ONLINE }, ++ { 0xe2004, 2047, RI_ALL_OFFLINE }, { 0xf0000, 1, RI_ALL_ONLINE }, ++ { 0xf0004, 16383, RI_ALL_OFFLINE }, { 0x101000, 12, RI_ALL_ONLINE }, ++ { 0x10103c, 1, RI_ALL_ONLINE }, { 0x10104c, 1, RI_ALL_ONLINE }, ++ { 0x101050, 1, RI_E1H_ONLINE }, { 0x101100, 1, RI_ALL_ONLINE }, ++ { 0x101800, 8, RI_ALL_ONLINE }, { 0x102000, 18, RI_ALL_ONLINE }, ++ { 0x102054, 1, RI_ALL_ONLINE }, { 0x102064, 1, RI_ALL_ONLINE }, ++ { 0x102080, 17, RI_ALL_ONLINE }, { 0x1020c8, 8, RI_E1H_ONLINE }, ++ { 0x102400, 1, RI_ALL_ONLINE }, { 0x103000, 26, RI_ALL_ONLINE }, ++ { 0x103074, 1, RI_ALL_ONLINE }, { 0x103084, 1, RI_ALL_ONLINE }, ++ { 0x103094, 1, RI_ALL_ONLINE }, { 0x103098, 5, RI_E1H_ONLINE }, ++ { 0x103800, 8, RI_ALL_ONLINE }, { 0x104000, 63, RI_ALL_ONLINE }, ++ { 0x104108, 1, RI_ALL_ONLINE }, { 0x104118, 1, RI_ALL_ONLINE }, ++ { 0x104200, 17, RI_ALL_ONLINE }, { 0x104400, 64, RI_ALL_ONLINE }, ++ { 0x104500, 192, RI_ALL_OFFLINE }, { 0x104800, 64, RI_ALL_ONLINE }, ++ { 0x104900, 192, RI_ALL_OFFLINE }, { 0x105000, 7, RI_ALL_ONLINE }, ++ { 0x10501c, 1, RI_ALL_OFFLINE }, { 0x105020, 3, RI_ALL_ONLINE }, ++ { 0x10502c, 1, RI_ALL_OFFLINE }, { 0x105030, 3, RI_ALL_ONLINE }, ++ { 0x10503c, 1, RI_ALL_OFFLINE }, { 0x105040, 3, RI_ALL_ONLINE }, ++ { 0x10504c, 1, RI_ALL_OFFLINE }, { 0x105050, 3, RI_ALL_ONLINE }, ++ { 0x10505c, 1, RI_ALL_OFFLINE }, { 0x105060, 3, RI_ALL_ONLINE }, ++ { 0x10506c, 1, RI_ALL_OFFLINE }, { 0x105070, 3, RI_ALL_ONLINE }, ++ { 0x10507c, 1, RI_ALL_OFFLINE }, { 0x105080, 3, RI_ALL_ONLINE }, ++ { 0x10508c, 1, RI_ALL_OFFLINE }, { 0x105090, 3, RI_ALL_ONLINE }, ++ { 0x10509c, 1, RI_ALL_OFFLINE }, { 0x1050a0, 3, RI_ALL_ONLINE }, ++ { 0x1050ac, 1, RI_ALL_OFFLINE }, { 0x1050b0, 3, RI_ALL_ONLINE }, ++ { 0x1050bc, 1, RI_ALL_OFFLINE }, { 0x1050c0, 3, RI_ALL_ONLINE }, ++ { 0x1050cc, 1, RI_ALL_OFFLINE }, { 0x1050d0, 3, RI_ALL_ONLINE }, ++ { 0x1050dc, 1, RI_ALL_OFFLINE }, { 0x1050e0, 3, RI_ALL_ONLINE }, ++ { 0x1050ec, 1, RI_ALL_OFFLINE }, { 0x1050f0, 3, RI_ALL_ONLINE }, ++ { 0x1050fc, 1, RI_ALL_OFFLINE }, { 0x105100, 3, RI_ALL_ONLINE }, ++ { 0x10510c, 1, RI_ALL_OFFLINE }, { 0x105110, 3, RI_ALL_ONLINE }, ++ { 0x10511c, 1, RI_ALL_OFFLINE }, { 0x105120, 3, RI_ALL_ONLINE }, ++ { 0x10512c, 1, RI_ALL_OFFLINE }, { 0x105130, 3, RI_ALL_ONLINE }, ++ { 0x10513c, 1, RI_ALL_OFFLINE }, { 0x105140, 3, RI_ALL_ONLINE }, ++ { 0x10514c, 1, RI_ALL_OFFLINE }, { 0x105150, 3, RI_ALL_ONLINE }, ++ { 0x10515c, 1, RI_ALL_OFFLINE }, { 0x105160, 3, RI_ALL_ONLINE }, ++ { 0x10516c, 1, RI_ALL_OFFLINE }, { 0x105170, 3, RI_ALL_ONLINE }, ++ { 0x10517c, 1, RI_ALL_OFFLINE }, { 0x105180, 3, RI_ALL_ONLINE }, ++ { 0x10518c, 1, RI_ALL_OFFLINE }, { 0x105190, 3, RI_ALL_ONLINE }, ++ { 0x10519c, 1, RI_ALL_OFFLINE }, { 0x1051a0, 3, RI_ALL_ONLINE }, ++ { 0x1051ac, 1, RI_ALL_OFFLINE }, { 0x1051b0, 3, RI_ALL_ONLINE }, ++ { 0x1051bc, 1, RI_ALL_OFFLINE }, { 0x1051c0, 3, RI_ALL_ONLINE }, ++ { 0x1051cc, 1, RI_ALL_OFFLINE }, { 0x1051d0, 3, RI_ALL_ONLINE }, ++ { 0x1051dc, 1, RI_ALL_OFFLINE }, { 0x1051e0, 3, RI_ALL_ONLINE }, ++ { 0x1051ec, 1, RI_ALL_OFFLINE }, { 0x1051f0, 3, RI_ALL_ONLINE }, ++ { 0x1051fc, 1, RI_ALL_OFFLINE }, { 0x105200, 3, RI_ALL_ONLINE }, ++ { 0x10520c, 1, RI_ALL_OFFLINE }, { 0x105210, 3, RI_ALL_ONLINE }, ++ { 0x10521c, 1, RI_ALL_OFFLINE }, { 0x105220, 3, RI_ALL_ONLINE }, ++ { 0x10522c, 1, RI_ALL_OFFLINE }, { 0x105230, 3, RI_ALL_ONLINE }, ++ { 0x10523c, 1, RI_ALL_OFFLINE }, { 0x105240, 3, RI_ALL_ONLINE }, ++ { 0x10524c, 1, RI_ALL_OFFLINE }, { 0x105250, 3, RI_ALL_ONLINE }, ++ { 0x10525c, 1, RI_ALL_OFFLINE }, { 0x105260, 3, RI_ALL_ONLINE }, ++ { 0x10526c, 1, RI_ALL_OFFLINE }, { 0x105270, 3, RI_ALL_ONLINE }, ++ { 0x10527c, 1, RI_ALL_OFFLINE }, { 0x105280, 3, RI_ALL_ONLINE }, ++ { 0x10528c, 1, RI_ALL_OFFLINE }, { 0x105290, 3, RI_ALL_ONLINE }, ++ { 0x10529c, 1, RI_ALL_OFFLINE }, { 0x1052a0, 3, RI_ALL_ONLINE }, ++ { 0x1052ac, 1, RI_ALL_OFFLINE }, { 0x1052b0, 3, RI_ALL_ONLINE }, ++ { 0x1052bc, 1, RI_ALL_OFFLINE }, { 0x1052c0, 3, RI_ALL_ONLINE }, ++ { 0x1052cc, 1, RI_ALL_OFFLINE }, { 0x1052d0, 3, RI_ALL_ONLINE }, ++ { 0x1052dc, 1, RI_ALL_OFFLINE }, { 0x1052e0, 3, RI_ALL_ONLINE }, ++ { 0x1052ec, 1, RI_ALL_OFFLINE }, { 0x1052f0, 3, RI_ALL_ONLINE }, ++ { 0x1052fc, 1, RI_ALL_OFFLINE }, { 0x105300, 3, RI_ALL_ONLINE }, ++ { 0x10530c, 1, RI_ALL_OFFLINE }, { 0x105310, 3, RI_ALL_ONLINE }, ++ { 0x10531c, 1, RI_ALL_OFFLINE }, { 0x105320, 3, RI_ALL_ONLINE }, ++ { 0x10532c, 1, RI_ALL_OFFLINE }, { 0x105330, 3, RI_ALL_ONLINE }, ++ { 0x10533c, 1, RI_ALL_OFFLINE }, { 0x105340, 3, RI_ALL_ONLINE }, ++ { 0x10534c, 1, RI_ALL_OFFLINE }, { 0x105350, 3, RI_ALL_ONLINE }, ++ { 0x10535c, 1, RI_ALL_OFFLINE }, { 0x105360, 3, RI_ALL_ONLINE }, ++ { 0x10536c, 1, RI_ALL_OFFLINE }, { 0x105370, 3, RI_ALL_ONLINE }, ++ { 0x10537c, 1, RI_ALL_OFFLINE }, { 0x105380, 3, RI_ALL_ONLINE }, ++ { 0x10538c, 1, RI_ALL_OFFLINE }, { 0x105390, 3, RI_ALL_ONLINE }, ++ { 0x10539c, 1, RI_ALL_OFFLINE }, { 0x1053a0, 3, RI_ALL_ONLINE }, ++ { 0x1053ac, 1, RI_ALL_OFFLINE }, { 0x1053b0, 3, RI_ALL_ONLINE }, ++ { 0x1053bc, 1, RI_ALL_OFFLINE }, { 0x1053c0, 3, RI_ALL_ONLINE }, ++ { 0x1053cc, 1, RI_ALL_OFFLINE }, { 0x1053d0, 3, RI_ALL_ONLINE }, ++ { 0x1053dc, 1, RI_ALL_OFFLINE }, { 0x1053e0, 3, RI_ALL_ONLINE }, ++ { 0x1053ec, 1, RI_ALL_OFFLINE }, { 0x1053f0, 3, RI_ALL_ONLINE }, ++ { 0x1053fc, 769, RI_ALL_OFFLINE }, { 0x108000, 33, RI_ALL_ONLINE }, ++ { 0x108090, 1, RI_ALL_ONLINE }, { 0x1080a0, 1, RI_ALL_ONLINE }, ++ { 0x1080ac, 5, RI_E1H_ONLINE }, { 0x108100, 5, RI_ALL_ONLINE }, ++ { 0x108120, 5, RI_ALL_ONLINE }, { 0x108200, 74, RI_ALL_ONLINE }, ++ { 0x108400, 74, RI_ALL_ONLINE }, { 0x108800, 152, RI_ALL_ONLINE }, ++ { 0x109000, 1, RI_ALL_ONLINE }, { 0x120000, 347, RI_ALL_ONLINE }, ++ { 0x120578, 1, RI_ALL_ONLINE }, { 0x120588, 1, RI_ALL_ONLINE }, ++ { 0x120598, 1, RI_ALL_ONLINE }, { 0x12059c, 23, RI_E1H_ONLINE }, ++ { 0x120614, 1, RI_E1H_ONLINE }, { 0x12061c, 30, RI_E1H_ONLINE }, ++ { 0x12080c, 65, RI_ALL_ONLINE }, { 0x120a00, 2, RI_ALL_ONLINE }, ++ { 0x122000, 2, RI_ALL_ONLINE }, { 0x128000, 2, RI_E1H_ONLINE }, ++ { 0x140000, 114, RI_ALL_ONLINE }, { 0x1401d4, 1, RI_ALL_ONLINE }, ++ { 0x1401e4, 1, RI_ALL_ONLINE }, { 0x140200, 6, RI_ALL_ONLINE }, ++ { 0x144000, 4, RI_ALL_ONLINE }, { 0x148000, 4, RI_ALL_ONLINE }, ++ { 0x14c000, 4, RI_ALL_ONLINE }, { 0x150000, 4, RI_ALL_ONLINE }, ++ { 0x154000, 4, RI_ALL_ONLINE }, { 0x158000, 4, RI_ALL_ONLINE }, ++ { 0x15c000, 7, RI_E1H_ONLINE }, { 0x161000, 7, RI_ALL_ONLINE }, ++ { 0x161028, 1, RI_ALL_ONLINE }, { 0x161038, 1, RI_ALL_ONLINE }, ++ { 0x161800, 2, RI_ALL_ONLINE }, { 0x164000, 60, RI_ALL_ONLINE }, ++ { 0x1640fc, 1, RI_ALL_ONLINE }, { 0x16410c, 1, RI_ALL_ONLINE }, ++ { 0x164110, 2, RI_E1H_ONLINE }, { 0x164200, 1, RI_ALL_ONLINE }, ++ { 0x164208, 1, RI_ALL_ONLINE }, { 0x164210, 1, RI_ALL_ONLINE }, ++ { 0x164218, 1, RI_ALL_ONLINE }, { 0x164220, 1, RI_ALL_ONLINE }, ++ { 0x164228, 1, RI_ALL_ONLINE }, { 0x164230, 1, RI_ALL_ONLINE }, ++ { 0x164238, 1, RI_ALL_ONLINE }, { 0x164240, 1, RI_ALL_ONLINE }, ++ { 0x164248, 1, RI_ALL_ONLINE }, { 0x164250, 1, RI_ALL_ONLINE }, ++ { 0x164258, 1, RI_ALL_ONLINE }, { 0x164260, 1, RI_ALL_ONLINE }, ++ { 0x164270, 2, RI_ALL_ONLINE }, { 0x164280, 2, RI_ALL_ONLINE }, ++ { 0x164800, 2, RI_ALL_ONLINE }, { 0x165000, 2, RI_ALL_ONLINE }, ++ { 0x166000, 164, RI_ALL_ONLINE }, { 0x16629c, 1, RI_ALL_ONLINE }, ++ { 0x1662ac, 1, RI_ALL_ONLINE }, { 0x1662bc, 1, RI_ALL_ONLINE }, ++ { 0x166400, 49, RI_ALL_ONLINE }, { 0x1664c8, 38, RI_ALL_ONLINE }, ++ { 0x166568, 2, RI_ALL_ONLINE }, { 0x166800, 1, RI_ALL_ONLINE }, ++ { 0x168000, 270, RI_ALL_ONLINE }, { 0x168444, 1, RI_ALL_ONLINE }, ++ { 0x168454, 1, RI_ALL_ONLINE }, { 0x168800, 19, RI_ALL_ONLINE }, ++ { 0x168900, 1, RI_ALL_ONLINE }, { 0x168a00, 128, RI_ALL_ONLINE }, ++ { 0x16a000, 1, RI_ALL_ONLINE }, { 0x16a004, 1535, RI_ALL_OFFLINE }, ++ { 0x16c000, 1, RI_ALL_ONLINE }, { 0x16c004, 1535, RI_ALL_OFFLINE }, ++ { 0x16e000, 16, RI_E1H_ONLINE }, { 0x16e100, 1, RI_E1H_ONLINE }, ++ { 0x16e200, 2, RI_E1H_ONLINE }, { 0x16e400, 183, RI_E1H_ONLINE }, ++ { 0x170000, 93, RI_ALL_ONLINE }, { 0x170180, 1, RI_ALL_ONLINE }, ++ { 0x170190, 1, RI_ALL_ONLINE }, { 0x170200, 4, RI_ALL_ONLINE }, ++ { 0x170214, 1, RI_ALL_ONLINE }, { 0x178000, 1, RI_ALL_ONLINE }, ++ { 0x180000, 61, RI_ALL_ONLINE }, { 0x180100, 1, RI_ALL_ONLINE }, ++ { 0x180110, 1, RI_ALL_ONLINE }, { 0x180120, 1, RI_ALL_ONLINE }, ++ { 0x180130, 1, RI_ALL_ONLINE }, { 0x18013c, 2, RI_E1H_ONLINE }, ++ { 0x180200, 58, RI_ALL_ONLINE }, { 0x180340, 4, RI_ALL_ONLINE }, ++ { 0x180400, 1, RI_ALL_ONLINE }, { 0x180404, 255, RI_ALL_OFFLINE }, ++ { 0x181000, 4, RI_ALL_ONLINE }, { 0x181010, 1020, RI_ALL_OFFLINE }, ++ { 0x1a0000, 1, RI_ALL_ONLINE }, { 0x1a0004, 1023, RI_ALL_OFFLINE }, ++ { 0x1a1000, 1, RI_ALL_ONLINE }, { 0x1a1004, 4607, RI_ALL_OFFLINE }, ++ { 0x1a5800, 2560, RI_E1H_OFFLINE }, { 0x1a8000, 64, RI_ALL_OFFLINE }, ++ { 0x1a8100, 1984, RI_E1H_OFFLINE }, { 0x1aa000, 1, RI_E1H_ONLINE }, ++ { 0x1aa004, 6655, RI_E1H_OFFLINE }, { 0x1b1800, 128, RI_ALL_OFFLINE }, ++ { 0x1b1c00, 128, RI_ALL_OFFLINE }, { 0x1b2000, 1, RI_ALL_OFFLINE }, ++ { 0x1b2400, 64, RI_E1H_OFFLINE }, { 0x1b8200, 1, RI_ALL_ONLINE }, ++ { 0x1b8240, 1, RI_ALL_ONLINE }, { 0x1b8280, 1, RI_ALL_ONLINE }, ++ { 0x1b82c0, 1, RI_ALL_ONLINE }, { 0x1b8a00, 1, RI_ALL_ONLINE }, ++ { 0x1b8a80, 1, RI_ALL_ONLINE }, { 0x1c0000, 2, RI_ALL_ONLINE }, ++ { 0x200000, 65, RI_ALL_ONLINE }, { 0x200110, 1, RI_ALL_ONLINE }, ++ { 0x200120, 1, RI_ALL_ONLINE }, { 0x200130, 1, RI_ALL_ONLINE }, ++ { 0x200140, 1, RI_ALL_ONLINE }, { 0x20014c, 2, RI_E1H_ONLINE }, ++ { 0x200200, 58, RI_ALL_ONLINE }, { 0x200340, 4, RI_ALL_ONLINE }, ++ { 0x200400, 1, RI_ALL_ONLINE }, { 0x200404, 255, RI_ALL_OFFLINE }, ++ { 0x202000, 4, RI_ALL_ONLINE }, { 0x202010, 2044, RI_ALL_OFFLINE }, ++ { 0x220000, 1, RI_ALL_ONLINE }, { 0x220004, 1023, RI_ALL_OFFLINE }, ++ { 0x221000, 1, RI_ALL_ONLINE }, { 0x221004, 4607, RI_ALL_OFFLINE }, ++ { 0x225800, 1536, RI_E1H_OFFLINE }, { 0x227000, 1, RI_E1H_ONLINE }, ++ { 0x227004, 1023, RI_E1H_OFFLINE }, { 0x228000, 64, RI_ALL_OFFLINE }, ++ { 0x228100, 8640, RI_E1H_OFFLINE }, { 0x231800, 128, RI_ALL_OFFLINE }, ++ { 0x231c00, 128, RI_ALL_OFFLINE }, { 0x232000, 1, RI_ALL_OFFLINE }, ++ { 0x232400, 64, RI_E1H_OFFLINE }, { 0x238200, 1, RI_ALL_ONLINE }, ++ { 0x238240, 1, RI_ALL_ONLINE }, { 0x238280, 1, RI_ALL_ONLINE }, ++ { 0x2382c0, 1, RI_ALL_ONLINE }, { 0x238a00, 1, RI_ALL_ONLINE }, ++ { 0x238a80, 1, RI_ALL_ONLINE }, { 0x240000, 2, RI_ALL_ONLINE }, ++ { 0x280000, 65, RI_ALL_ONLINE }, { 0x280110, 1, RI_ALL_ONLINE }, ++ { 0x280120, 1, RI_ALL_ONLINE }, { 0x280130, 1, RI_ALL_ONLINE }, ++ { 0x280140, 1, RI_ALL_ONLINE }, { 0x28014c, 2, RI_E1H_ONLINE }, ++ { 0x280200, 58, RI_ALL_ONLINE }, { 0x280340, 4, RI_ALL_ONLINE }, ++ { 0x280400, 1, RI_ALL_ONLINE }, { 0x280404, 255, RI_ALL_OFFLINE }, ++ { 0x282000, 4, RI_ALL_ONLINE }, { 0x282010, 2044, RI_ALL_OFFLINE }, ++ { 0x2a0000, 1, RI_ALL_ONLINE }, { 0x2a0004, 1023, RI_ALL_OFFLINE }, ++ { 0x2a1000, 1, RI_ALL_ONLINE }, { 0x2a1004, 4607, RI_ALL_OFFLINE }, ++ { 0x2a5800, 2560, RI_E1H_OFFLINE }, { 0x2a8000, 64, RI_ALL_OFFLINE }, ++ { 0x2a8100, 960, RI_E1H_OFFLINE }, { 0x2a9000, 1, RI_E1H_ONLINE }, ++ { 0x2a9004, 7679, RI_E1H_OFFLINE }, { 0x2b1800, 128, RI_ALL_OFFLINE }, ++ { 0x2b1c00, 128, RI_ALL_OFFLINE }, { 0x2b2000, 1, RI_ALL_OFFLINE }, ++ { 0x2b2400, 64, RI_E1H_OFFLINE }, { 0x2b8200, 1, RI_ALL_ONLINE }, ++ { 0x2b8240, 1, RI_ALL_ONLINE }, { 0x2b8280, 1, RI_ALL_ONLINE }, ++ { 0x2b82c0, 1, RI_ALL_ONLINE }, { 0x2b8a00, 1, RI_ALL_ONLINE }, ++ { 0x2b8a80, 1, RI_ALL_ONLINE }, { 0x2c0000, 2, RI_ALL_ONLINE }, ++ { 0x300000, 65, RI_ALL_ONLINE }, { 0x300110, 1, RI_ALL_ONLINE }, ++ { 0x300120, 1, RI_ALL_ONLINE }, { 0x300130, 1, RI_ALL_ONLINE }, ++ { 0x300140, 1, RI_ALL_ONLINE }, { 0x30014c, 2, RI_E1H_ONLINE }, ++ { 0x300200, 58, RI_ALL_ONLINE }, { 0x300340, 4, RI_ALL_ONLINE }, ++ { 0x300400, 1, RI_ALL_ONLINE }, { 0x300404, 255, RI_ALL_OFFLINE }, ++ { 0x302000, 4, RI_ALL_ONLINE }, { 0x302010, 2044, RI_ALL_OFFLINE }, ++ { 0x320000, 1, RI_ALL_ONLINE }, { 0x320004, 1023, RI_ALL_OFFLINE }, ++ { 0x321000, 1, RI_ALL_ONLINE }, { 0x321004, 4607, RI_ALL_OFFLINE }, ++ { 0x325800, 2560, RI_E1H_OFFLINE }, { 0x328000, 64, RI_ALL_OFFLINE }, ++ { 0x328100, 536, RI_E1H_OFFLINE }, { 0x328960, 1, RI_E1H_ONLINE }, ++ { 0x328964, 8103, RI_E1H_OFFLINE }, { 0x331800, 128, RI_ALL_OFFLINE }, ++ { 0x331c00, 128, RI_ALL_OFFLINE }, { 0x332000, 1, RI_ALL_OFFLINE }, ++ { 0x332400, 64, RI_E1H_OFFLINE }, { 0x338200, 1, RI_ALL_ONLINE }, ++ { 0x338240, 1, RI_ALL_ONLINE }, { 0x338280, 1, RI_ALL_ONLINE }, ++ { 0x3382c0, 1, RI_ALL_ONLINE }, { 0x338a00, 1, RI_ALL_ONLINE }, ++ { 0x338a80, 1, RI_ALL_ONLINE }, { 0x340000, 2, RI_ALL_ONLINE } ++}; ++ ++ ++#define IDLE_REGS_COUNT 277 ++static const struct reg_addr idle_addrs[IDLE_REGS_COUNT] = { ++ { 0x2114, 1, RI_ALL_ONLINE }, { 0x2120, 1, RI_ALL_ONLINE }, ++ { 0x212c, 4, RI_ALL_ONLINE }, { 0x2814, 1, RI_ALL_ONLINE }, ++ { 0x281c, 2, RI_ALL_ONLINE }, { 0xa38c, 1, RI_ALL_ONLINE }, ++ { 0xa408, 1, RI_ALL_ONLINE }, { 0xa42c, 12, RI_ALL_ONLINE }, ++ { 0xa600, 5, RI_E1H_ONLINE }, { 0xa618, 1, RI_E1H_ONLINE }, ++ { 0xc09c, 1, RI_ALL_ONLINE }, { 0x103b0, 1, RI_ALL_ONLINE }, ++ { 0x103c0, 1, RI_ALL_ONLINE }, { 0x103d0, 1, RI_E1H_ONLINE }, ++ { 0x2021c, 11, RI_ALL_ONLINE }, { 0x202a8, 1, RI_ALL_ONLINE }, ++ { 0x202b8, 1, RI_ALL_ONLINE }, { 0x20404, 1, RI_ALL_ONLINE }, ++ { 0x2040c, 2, RI_ALL_ONLINE }, { 0x2041c, 2, RI_ALL_ONLINE }, ++ { 0x40154, 14, RI_ALL_ONLINE }, { 0x40198, 1, RI_ALL_ONLINE }, ++ { 0x404ac, 1, RI_ALL_ONLINE }, { 0x404bc, 1, RI_ALL_ONLINE }, ++ { 0x42290, 1, RI_ALL_ONLINE }, { 0x422a0, 1, RI_ALL_ONLINE }, ++ { 0x422b0, 1, RI_ALL_ONLINE }, { 0x42548, 1, RI_ALL_ONLINE }, ++ { 0x42550, 1, RI_ALL_ONLINE }, { 0x42558, 1, RI_ALL_ONLINE }, ++ { 0x50160, 8, RI_ALL_ONLINE }, { 0x501d0, 1, RI_ALL_ONLINE }, ++ { 0x501e0, 1, RI_ALL_ONLINE }, { 0x50204, 1, RI_ALL_ONLINE }, ++ { 0x5020c, 2, RI_ALL_ONLINE }, { 0x5021c, 1, RI_ALL_ONLINE }, ++ { 0x60090, 1, RI_ALL_ONLINE }, { 0x6011c, 1, RI_ALL_ONLINE }, ++ { 0x6012c, 1, RI_ALL_ONLINE }, { 0xc101c, 1, RI_ALL_ONLINE }, ++ { 0xc102c, 1, RI_ALL_ONLINE }, { 0xc2290, 1, RI_ALL_ONLINE }, ++ { 0xc22a0, 1, RI_ALL_ONLINE }, { 0xc22b0, 1, RI_ALL_ONLINE }, ++ { 0xc2548, 1, RI_ALL_ONLINE }, { 0xc2550, 1, RI_ALL_ONLINE }, ++ { 0xc2558, 1, RI_ALL_ONLINE }, { 0xc4294, 1, RI_ALL_ONLINE }, ++ { 0xc42a4, 1, RI_ALL_ONLINE }, { 0xc42b4, 1, RI_ALL_ONLINE }, ++ { 0xc4550, 1, RI_ALL_ONLINE }, { 0xc4558, 1, RI_ALL_ONLINE }, ++ { 0xc4560, 1, RI_ALL_ONLINE }, { 0xd016c, 8, RI_ALL_ONLINE }, ++ { 0xd01d8, 1, RI_ALL_ONLINE }, { 0xd01e8, 1, RI_ALL_ONLINE }, ++ { 0xd0204, 1, RI_ALL_ONLINE }, { 0xd020c, 3, RI_ALL_ONLINE }, ++ { 0xe0154, 8, RI_ALL_ONLINE }, { 0xe01c8, 1, RI_ALL_ONLINE }, ++ { 0xe01d8, 1, RI_ALL_ONLINE }, { 0xe0204, 1, RI_ALL_ONLINE }, ++ { 0xe020c, 2, RI_ALL_ONLINE }, { 0xe021c, 2, RI_ALL_ONLINE }, ++ { 0x101014, 1, RI_ALL_ONLINE }, { 0x101030, 1, RI_ALL_ONLINE }, ++ { 0x101040, 1, RI_ALL_ONLINE }, { 0x102058, 1, RI_ALL_ONLINE }, ++ { 0x102080, 16, RI_ALL_ONLINE }, { 0x103004, 2, RI_ALL_ONLINE }, ++ { 0x103068, 1, RI_ALL_ONLINE }, { 0x103078, 1, RI_ALL_ONLINE }, ++ { 0x103088, 1, RI_ALL_ONLINE }, { 0x10309c, 2, RI_E1H_ONLINE }, ++ { 0x104004, 1, RI_ALL_ONLINE }, { 0x104018, 1, RI_ALL_ONLINE }, ++ { 0x104020, 1, RI_ALL_ONLINE }, { 0x10403c, 1, RI_ALL_ONLINE }, ++ { 0x1040fc, 1, RI_ALL_ONLINE }, { 0x10410c, 1, RI_ALL_ONLINE }, ++ { 0x104400, 64, RI_ALL_ONLINE }, { 0x104800, 64, RI_ALL_ONLINE }, ++ { 0x105000, 3, RI_ALL_ONLINE }, { 0x105010, 3, RI_ALL_ONLINE }, ++ { 0x105020, 3, RI_ALL_ONLINE }, { 0x105030, 3, RI_ALL_ONLINE }, ++ { 0x105040, 3, RI_ALL_ONLINE }, { 0x105050, 3, RI_ALL_ONLINE }, ++ { 0x105060, 3, RI_ALL_ONLINE }, { 0x105070, 3, RI_ALL_ONLINE }, ++ { 0x105080, 3, RI_ALL_ONLINE }, { 0x105090, 3, RI_ALL_ONLINE }, ++ { 0x1050a0, 3, RI_ALL_ONLINE }, { 0x1050b0, 3, RI_ALL_ONLINE }, ++ { 0x1050c0, 3, RI_ALL_ONLINE }, { 0x1050d0, 3, RI_ALL_ONLINE }, ++ { 0x1050e0, 3, RI_ALL_ONLINE }, { 0x1050f0, 3, RI_ALL_ONLINE }, ++ { 0x105100, 3, RI_ALL_ONLINE }, { 0x105110, 3, RI_ALL_ONLINE }, ++ { 0x105120, 3, RI_ALL_ONLINE }, { 0x105130, 3, RI_ALL_ONLINE }, ++ { 0x105140, 3, RI_ALL_ONLINE }, { 0x105150, 3, RI_ALL_ONLINE }, ++ { 0x105160, 3, RI_ALL_ONLINE }, { 0x105170, 3, RI_ALL_ONLINE }, ++ { 0x105180, 3, RI_ALL_ONLINE }, { 0x105190, 3, RI_ALL_ONLINE }, ++ { 0x1051a0, 3, RI_ALL_ONLINE }, { 0x1051b0, 3, RI_ALL_ONLINE }, ++ { 0x1051c0, 3, RI_ALL_ONLINE }, { 0x1051d0, 3, RI_ALL_ONLINE }, ++ { 0x1051e0, 3, RI_ALL_ONLINE }, { 0x1051f0, 3, RI_ALL_ONLINE }, ++ { 0x105200, 3, RI_ALL_ONLINE }, { 0x105210, 3, RI_ALL_ONLINE }, ++ { 0x105220, 3, RI_ALL_ONLINE }, { 0x105230, 3, RI_ALL_ONLINE }, ++ { 0x105240, 3, RI_ALL_ONLINE }, { 0x105250, 3, RI_ALL_ONLINE }, ++ { 0x105260, 3, RI_ALL_ONLINE }, { 0x105270, 3, RI_ALL_ONLINE }, ++ { 0x105280, 3, RI_ALL_ONLINE }, { 0x105290, 3, RI_ALL_ONLINE }, ++ { 0x1052a0, 3, RI_ALL_ONLINE }, { 0x1052b0, 3, RI_ALL_ONLINE }, ++ { 0x1052c0, 3, RI_ALL_ONLINE }, { 0x1052d0, 3, RI_ALL_ONLINE }, ++ { 0x1052e0, 3, RI_ALL_ONLINE }, { 0x1052f0, 3, RI_ALL_ONLINE }, ++ { 0x105300, 3, RI_ALL_ONLINE }, { 0x105310, 3, RI_ALL_ONLINE }, ++ { 0x105320, 3, RI_ALL_ONLINE }, { 0x105330, 3, RI_ALL_ONLINE }, ++ { 0x105340, 3, RI_ALL_ONLINE }, { 0x105350, 3, RI_ALL_ONLINE }, ++ { 0x105360, 3, RI_ALL_ONLINE }, { 0x105370, 3, RI_ALL_ONLINE }, ++ { 0x105380, 3, RI_ALL_ONLINE }, { 0x105390, 3, RI_ALL_ONLINE }, ++ { 0x1053a0, 3, RI_ALL_ONLINE }, { 0x1053b0, 3, RI_ALL_ONLINE }, ++ { 0x1053c0, 3, RI_ALL_ONLINE }, { 0x1053d0, 3, RI_ALL_ONLINE }, ++ { 0x1053e0, 3, RI_ALL_ONLINE }, { 0x1053f0, 3, RI_ALL_ONLINE }, ++ { 0x108094, 1, RI_ALL_ONLINE }, { 0x1201b0, 2, RI_ALL_ONLINE }, ++ { 0x12032c, 1, RI_ALL_ONLINE }, { 0x12036c, 3, RI_ALL_ONLINE }, ++ { 0x120408, 2, RI_ALL_ONLINE }, { 0x120414, 15, RI_ALL_ONLINE }, ++ { 0x120478, 2, RI_ALL_ONLINE }, { 0x12052c, 1, RI_ALL_ONLINE }, ++ { 0x120564, 3, RI_ALL_ONLINE }, { 0x12057c, 1, RI_ALL_ONLINE }, ++ { 0x12058c, 1, RI_ALL_ONLINE }, { 0x120608, 1, RI_E1H_ONLINE }, ++ { 0x120808, 1, RI_E1_ONLINE }, { 0x12080c, 2, RI_ALL_ONLINE }, ++ { 0x120818, 1, RI_ALL_ONLINE }, { 0x120820, 1, RI_ALL_ONLINE }, ++ { 0x120828, 1, RI_ALL_ONLINE }, { 0x120830, 1, RI_ALL_ONLINE }, ++ { 0x120838, 1, RI_ALL_ONLINE }, { 0x120840, 1, RI_ALL_ONLINE }, ++ { 0x120848, 1, RI_ALL_ONLINE }, { 0x120850, 1, RI_ALL_ONLINE }, ++ { 0x120858, 1, RI_ALL_ONLINE }, { 0x120860, 1, RI_ALL_ONLINE }, ++ { 0x120868, 1, RI_ALL_ONLINE }, { 0x120870, 1, RI_ALL_ONLINE }, ++ { 0x120878, 1, RI_ALL_ONLINE }, { 0x120880, 1, RI_ALL_ONLINE }, ++ { 0x120888, 1, RI_ALL_ONLINE }, { 0x120890, 1, RI_ALL_ONLINE }, ++ { 0x120898, 1, RI_ALL_ONLINE }, { 0x1208a0, 1, RI_ALL_ONLINE }, ++ { 0x1208a8, 1, RI_ALL_ONLINE }, { 0x1208b0, 1, RI_ALL_ONLINE }, ++ { 0x1208b8, 1, RI_ALL_ONLINE }, { 0x1208c0, 1, RI_ALL_ONLINE }, ++ { 0x1208c8, 1, RI_ALL_ONLINE }, { 0x1208d0, 1, RI_ALL_ONLINE }, ++ { 0x1208d8, 1, RI_ALL_ONLINE }, { 0x1208e0, 1, RI_ALL_ONLINE }, ++ { 0x1208e8, 1, RI_ALL_ONLINE }, { 0x1208f0, 1, RI_ALL_ONLINE }, ++ { 0x1208f8, 1, RI_ALL_ONLINE }, { 0x120900, 1, RI_ALL_ONLINE }, ++ { 0x120908, 1, RI_ALL_ONLINE }, { 0x14005c, 2, RI_ALL_ONLINE }, ++ { 0x1400d0, 2, RI_ALL_ONLINE }, { 0x1400e0, 1, RI_ALL_ONLINE }, ++ { 0x1401c8, 1, RI_ALL_ONLINE }, { 0x140200, 6, RI_ALL_ONLINE }, ++ { 0x16101c, 1, RI_ALL_ONLINE }, { 0x16102c, 1, RI_ALL_ONLINE }, ++ { 0x164014, 2, RI_ALL_ONLINE }, { 0x1640f0, 1, RI_ALL_ONLINE }, ++ { 0x166290, 1, RI_ALL_ONLINE }, { 0x1662a0, 1, RI_ALL_ONLINE }, ++ { 0x1662b0, 1, RI_ALL_ONLINE }, { 0x166548, 1, RI_ALL_ONLINE }, ++ { 0x166550, 1, RI_ALL_ONLINE }, { 0x166558, 1, RI_ALL_ONLINE }, ++ { 0x168000, 1, RI_ALL_ONLINE }, { 0x168008, 1, RI_ALL_ONLINE }, ++ { 0x168010, 1, RI_ALL_ONLINE }, { 0x168018, 1, RI_ALL_ONLINE }, ++ { 0x168028, 2, RI_ALL_ONLINE }, { 0x168058, 4, RI_ALL_ONLINE }, ++ { 0x168070, 1, RI_ALL_ONLINE }, { 0x168238, 1, RI_ALL_ONLINE }, ++ { 0x1682d0, 2, RI_ALL_ONLINE }, { 0x1682e0, 1, RI_ALL_ONLINE }, ++ { 0x168300, 67, RI_ALL_ONLINE }, { 0x168410, 2, RI_ALL_ONLINE }, ++ { 0x168438, 1, RI_ALL_ONLINE }, { 0x168448, 1, RI_ALL_ONLINE }, ++ { 0x168a00, 128, RI_ALL_ONLINE }, { 0x16e200, 128, RI_E1H_ONLINE }, ++ { 0x16e404, 2, RI_E1H_ONLINE }, { 0x16e584, 70, RI_E1H_ONLINE }, ++ { 0x1700a4, 1, RI_ALL_ONLINE }, { 0x1700ac, 2, RI_ALL_ONLINE }, ++ { 0x1700c0, 1, RI_ALL_ONLINE }, { 0x170174, 1, RI_ALL_ONLINE }, ++ { 0x170184, 1, RI_ALL_ONLINE }, { 0x1800f4, 1, RI_ALL_ONLINE }, ++ { 0x180104, 1, RI_ALL_ONLINE }, { 0x180114, 1, RI_ALL_ONLINE }, ++ { 0x180124, 1, RI_ALL_ONLINE }, { 0x18026c, 1, RI_ALL_ONLINE }, ++ { 0x1802a0, 1, RI_ALL_ONLINE }, { 0x1a1000, 1, RI_ALL_ONLINE }, ++ { 0x1aa000, 1, RI_E1H_ONLINE }, { 0x1b8000, 1, RI_ALL_ONLINE }, ++ { 0x1b8040, 1, RI_ALL_ONLINE }, { 0x1b8080, 1, RI_ALL_ONLINE }, ++ { 0x1b80c0, 1, RI_ALL_ONLINE }, { 0x200104, 1, RI_ALL_ONLINE }, ++ { 0x200114, 1, RI_ALL_ONLINE }, { 0x200124, 1, RI_ALL_ONLINE }, ++ { 0x200134, 1, RI_ALL_ONLINE }, { 0x20026c, 1, RI_ALL_ONLINE }, ++ { 0x2002a0, 1, RI_ALL_ONLINE }, { 0x221000, 1, RI_ALL_ONLINE }, ++ { 0x227000, 1, RI_E1H_ONLINE }, { 0x238000, 1, RI_ALL_ONLINE }, ++ { 0x238040, 1, RI_ALL_ONLINE }, { 0x238080, 1, RI_ALL_ONLINE }, ++ { 0x2380c0, 1, RI_ALL_ONLINE }, { 0x280104, 1, RI_ALL_ONLINE }, ++ { 0x280114, 1, RI_ALL_ONLINE }, { 0x280124, 1, RI_ALL_ONLINE }, ++ { 0x280134, 1, RI_ALL_ONLINE }, { 0x28026c, 1, RI_ALL_ONLINE }, ++ { 0x2802a0, 1, RI_ALL_ONLINE }, { 0x2a1000, 1, RI_ALL_ONLINE }, ++ { 0x2a9000, 1, RI_E1H_ONLINE }, { 0x2b8000, 1, RI_ALL_ONLINE }, ++ { 0x2b8040, 1, RI_ALL_ONLINE }, { 0x2b8080, 1, RI_ALL_ONLINE }, ++ { 0x2b80c0, 1, RI_ALL_ONLINE }, { 0x300104, 1, RI_ALL_ONLINE }, ++ { 0x300114, 1, RI_ALL_ONLINE }, { 0x300124, 1, RI_ALL_ONLINE }, ++ { 0x300134, 1, RI_ALL_ONLINE }, { 0x30026c, 1, RI_ALL_ONLINE }, ++ { 0x3002a0, 1, RI_ALL_ONLINE }, { 0x321000, 1, RI_ALL_ONLINE }, ++ { 0x328960, 1, RI_E1H_ONLINE }, { 0x338000, 1, RI_ALL_ONLINE }, ++ { 0x338040, 1, RI_ALL_ONLINE }, { 0x338080, 1, RI_ALL_ONLINE }, ++ { 0x3380c0, 1, RI_ALL_ONLINE } ++}; ++ ++#define WREGS_COUNT_E1 1 ++static const u32 read_reg_e1_0[] = { 0x1b1000 }; ++ ++static const struct wreg_addr wreg_addrs_e1[WREGS_COUNT_E1] = { ++ { 0x1b0c00, 192, 1, read_reg_e1_0, RI_E1_OFFLINE } ++}; ++ ++ ++#define WREGS_COUNT_E1H 1 ++static const u32 read_reg_e1h_0[] = { 0x1b1040, 0x1b1000 }; ++ ++static const struct wreg_addr wreg_addrs_e1h[WREGS_COUNT_E1H] = { ++ { 0x1b0c00, 256, 2, read_reg_e1h_0, RI_E1H_OFFLINE } ++}; ++ ++ ++static const struct dump_sign dump_sign_all = { 0x49aa93ee, 0x40835, 0x22 }; ++ ++ ++#define TIMER_REGS_COUNT_E1 2 ++static const u32 timer_status_regs_e1[TIMER_REGS_COUNT_E1] = ++ { 0x164014, 0x164018 }; ++static const u32 timer_scan_regs_e1[TIMER_REGS_COUNT_E1] = ++ { 0x1640d0, 0x1640d4 }; ++ ++ ++#define TIMER_REGS_COUNT_E1H 2 ++static const u32 timer_status_regs_e1h[TIMER_REGS_COUNT_E1H] = ++ { 0x164014, 0x164018 }; ++static const u32 timer_scan_regs_e1h[TIMER_REGS_COUNT_E1H] = ++ { 0x1640d0, 0x1640d4 }; ++ ++ ++#endif /* BNX2X_DUMP_H */ +diff -r e67cb9a8e847 drivers/net/bnx2x_fw_defs.h +--- a/drivers/net/bnx2x_fw_defs.h Wed Aug 05 10:50:39 2009 +0100 ++++ b/drivers/net/bnx2x_fw_defs.h Wed Aug 05 10:51:02 2009 +0100 +@@ -1,6 +1,6 @@ + /* bnx2x_fw_defs.h: Broadcom Everest network driver. + * +- * Copyright (c) 2007-2008 Broadcom Corporation ++ * Copyright (c) 2007-2009 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -12,46 +12,117 @@ + (IS_E1H_OFFSET ? 0x7000 : 0x1000) + #define CSTORM_ASSERT_LIST_OFFSET(idx) \ + (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) +-#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ +- (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \ +- ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \ ++#define CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(function, index) \ ++ (IS_E1H_OFFSET ? (0x8622 + ((function>>1) * 0x40) + \ ++ ((function&1) * 0x100) + (index * 0x4)) : (0x3562 + (function * \ + 0x40) + (index * 0x4))) +-#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \ +- ((function&1) * 0x100)) : (0x1900 + (function * 0x40))) +-#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \ +- ((function&1) * 0x100)) : (0x1908 + (function * 0x40))) ++#define CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(function, index) \ ++ (IS_E1H_OFFSET ? (0x8822 + ((function>>1) * 0x80) + \ ++ ((function&1) * 0x200) + (index * 0x4)) : (0x35e2 + (function * \ ++ 0x80) + (index * 0x4))) ++#define CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8600 + ((function>>1) * 0x40) + \ ++ ((function&1) * 0x100)) : (0x3540 + (function * 0x40))) ++#define CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8800 + ((function>>1) * 0x80) + \ ++ ((function&1) * 0x200)) : (0x35c0 + (function * 0x80))) ++#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8608 + ((function>>1) * 0x40) + \ ++ ((function&1) * 0x100)) : (0x3548 + (function * 0x40))) ++#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8808 + ((function>>1) * 0x80) + \ ++ ((function&1) * 0x200)) : (0x35c8 + (function * 0x80))) + #define CSTORM_FUNCTION_MODE_OFFSET \ + (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff) +-#define CSTORM_HC_BTR_OFFSET(port) \ +- (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) +-#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ +- (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \ +- (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ ++#define CSTORM_HC_BTR_C_OFFSET(port) \ ++ (IS_E1H_OFFSET ? (0x8c04 + (port * 0xf0)) : (0x36c4 + (port * 0xc0))) ++#define CSTORM_HC_BTR_U_OFFSET(port) \ ++ (IS_E1H_OFFSET ? (0x8de4 + (port * 0xf0)) : (0x3844 + (port * 0xc0))) ++#define CSTORM_ISCSI_CQ_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x6680 + (function * 0x8)) : (0x25a0 + \ ++ (function * 0x8))) ++#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x66c0 + (function * 0x8)) : (0x25b0 + \ ++ (function * 0x8))) ++#define CSTORM_ISCSI_EQ_CONS_OFFSET(function, eqIdx) \ ++ (IS_E1H_OFFSET ? (0x6040 + (function * 0xc0) + (eqIdx * 0x18)) : \ ++ (0x2410 + (function * 0xc0) + (eqIdx * 0x18))) ++#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(function, eqIdx) \ ++ (IS_E1H_OFFSET ? (0x6044 + (function * 0xc0) + (eqIdx * 0x18)) : \ ++ (0x2414 + (function * 0xc0) + (eqIdx * 0x18))) ++#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(function, eqIdx) \ ++ (IS_E1H_OFFSET ? (0x604c + (function * 0xc0) + (eqIdx * 0x18)) : \ ++ (0x241c + (function * 0xc0) + (eqIdx * 0x18))) ++#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(function, eqIdx) \ ++ (IS_E1H_OFFSET ? (0x6057 + (function * 0xc0) + (eqIdx * 0x18)) : \ ++ (0x2427 + (function * 0xc0) + (eqIdx * 0x18))) ++#define CSTORM_ISCSI_EQ_PROD_OFFSET(function, eqIdx) \ ++ (IS_E1H_OFFSET ? (0x6042 + (function * 0xc0) + (eqIdx * 0x18)) : \ ++ (0x2412 + (function * 0xc0) + (eqIdx * 0x18))) ++#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(function, eqIdx) \ ++ (IS_E1H_OFFSET ? (0x6056 + (function * 0xc0) + (eqIdx * 0x18)) : \ ++ (0x2426 + (function * 0xc0) + (eqIdx * 0x18))) ++#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(function, eqIdx) \ ++ (IS_E1H_OFFSET ? (0x6054 + (function * 0xc0) + (eqIdx * 0x18)) : \ ++ (0x2424 + (function * 0xc0) + (eqIdx * 0x18))) ++#define CSTORM_ISCSI_HQ_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x6640 + (function * 0x8)) : (0x2590 + \ ++ (function * 0x8))) ++#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x2404 + \ ++ (function * 0x8))) ++#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x2402 + \ ++ (function * 0x8))) ++#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x2400 + \ ++ (function * 0x8))) ++#define CSTORM_SB_HC_DISABLE_C_OFFSET(port, cpu_id, index) \ ++ (IS_E1H_OFFSET ? (0x811a + (port * 0x280) + (cpu_id * 0x28) + \ ++ (index * 0x4)) : (0x305a + (port * 0x280) + (cpu_id * 0x28) + \ + (index * 0x4))) +-#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ +- (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \ +- (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ ++#define CSTORM_SB_HC_DISABLE_U_OFFSET(port, cpu_id, index) \ ++ (IS_E1H_OFFSET ? (0xb01a + (port * 0x800) + (cpu_id * 0x80) + \ ++ (index * 0x4)) : (0x401a + (port * 0x800) + (cpu_id * 0x80) + \ + (index * 0x4))) +-#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ +- (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \ +- (0x1400 + (port * 0x280) + (cpu_id * 0x28))) +-#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ +- (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \ +- (0x1408 + (port * 0x280) + (cpu_id * 0x28))) ++#define CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, cpu_id, index) \ ++ (IS_E1H_OFFSET ? (0x8118 + (port * 0x280) + (cpu_id * 0x28) + \ ++ (index * 0x4)) : (0x3058 + (port * 0x280) + (cpu_id * 0x28) + \ ++ (index * 0x4))) ++#define CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, cpu_id, index) \ ++ (IS_E1H_OFFSET ? (0xb018 + (port * 0x800) + (cpu_id * 0x80) + \ ++ (index * 0x4)) : (0x4018 + (port * 0x800) + (cpu_id * 0x80) + \ ++ (index * 0x4))) ++#define CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, cpu_id) \ ++ (IS_E1H_OFFSET ? (0x8100 + (port * 0x280) + (cpu_id * 0x28)) : \ ++ (0x3040 + (port * 0x280) + (cpu_id * 0x28))) ++#define CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, cpu_id) \ ++ (IS_E1H_OFFSET ? (0xb000 + (port * 0x800) + (cpu_id * 0x80)) : \ ++ (0x4000 + (port * 0x800) + (cpu_id * 0x80))) ++#define CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, cpu_id) \ ++ (IS_E1H_OFFSET ? (0x8108 + (port * 0x280) + (cpu_id * 0x28)) : \ ++ (0x3048 + (port * 0x280) + (cpu_id * 0x28))) ++#define CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, cpu_id) \ ++ (IS_E1H_OFFSET ? (0xb008 + (port * 0x800) + (cpu_id * 0x80)) : \ ++ (0x4008 + (port * 0x800) + (cpu_id * 0x80))) ++#define CSTORM_SB_STATUS_BLOCK_C_SIZE 0x10 ++#define CSTORM_SB_STATUS_BLOCK_U_SIZE 0x60 + #define CSTORM_STATS_FLAGS_OFFSET(function) \ + (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \ + (function * 0x8))) + #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff) ++ (IS_E1H_OFFSET ? (0x3200 + (function * 0x20)) : 0xffffffff) + #define TSTORM_ASSERT_LIST_INDEX_OFFSET \ + (IS_E1H_OFFSET ? 0xa000 : 0x1000) + #define TSTORM_ASSERT_LIST_OFFSET(idx) \ + (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) + #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \ +- (IS_E1H_OFFSET ? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) \ +- : (0x9c8 + (port * 0x2f8) + (client_id * 0x28))) ++ (IS_E1H_OFFSET ? (0x33a0 + (port * 0x1a0) + (client_id * 0x10)) \ ++ : (0x9c0 + (port * 0x120) + (client_id * 0x10))) ++#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \ ++ (IS_E1H_OFFSET ? 0x1ed8 : 0xffffffff) ++#define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \ ++ (IS_E1H_OFFSET ? 0x1eda : 0xffffffff) + #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ + (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \ + ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ +@@ -63,81 +134,133 @@ + (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \ + ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) + #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \ ++ (IS_E1H_OFFSET ? (0x2940 + (function * 0x8)) : (0x4928 + \ + (function * 0x8))) + #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \ +- (function * 0x38))) ++ (IS_E1H_OFFSET ? (0x3000 + (function * 0x40)) : (0x1500 + \ ++ (function * 0x40))) + #define TSTORM_FUNCTION_MODE_OFFSET \ +- (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff) ++ (IS_E1H_OFFSET ? 0x1ed0 : 0xffffffff) + #define TSTORM_HC_BTR_OFFSET(port) \ + (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18))) + #define TSTORM_INDIRECTION_TABLE_OFFSET(function) \ + (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \ + (function * 0x80))) + #define TSTORM_INDIRECTION_TABLE_SIZE 0x80 ++#define TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(function, pblEntry) \ ++ (IS_E1H_OFFSET ? (0x60c0 + (function * 0x40) + (pblEntry * 0x8)) \ ++ : (0x4c30 + (function * 0x40) + (pblEntry * 0x8))) ++#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x6340 + (function * 0x8)) : (0x4cd0 + \ ++ (function * 0x8))) ++#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x4c04 + \ ++ (function * 0x8))) ++#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x4c02 + \ ++ (function * 0x8))) ++#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x4c00 + \ ++ (function * 0x8))) ++#define TSTORM_ISCSI_RQ_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x6080 + (function * 0x8)) : (0x4c20 + \ ++ (function * 0x8))) ++#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x6040 + (function * 0x8)) : (0x4c10 + \ ++ (function * 0x8))) ++#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x6042 + (function * 0x8)) : (0x4c12 + \ ++ (function * 0x8))) ++#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x6044 + (function * 0x8)) : (0x4c14 + \ ++ (function * 0x8))) + #define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \ +- (function * 0x38))) ++ (IS_E1H_OFFSET ? (0x3008 + (function * 0x40)) : (0x1508 + \ ++ (function * 0x40))) + #define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ +- (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \ +- 0x50)) : (0x4000 + (port * 0x3f0) + (stats_counter_id * 0x38))) +-#define TSTORM_RX_PRODS_OFFSET(port, client_id) \ +- (IS_E1H_OFFSET ? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) \ +- : (0x9c0 + (port * 0x2f8) + (client_id * 0x28))) ++ (IS_E1H_OFFSET ? (0x2010 + (port * 0x490) + (stats_counter_id * \ ++ 0x40)) : (0x4010 + (port * 0x490) + (stats_counter_id * 0x40))) + #define TSTORM_STATS_FLAGS_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \ ++ (IS_E1H_OFFSET ? (0x29c0 + (function * 0x8)) : (0x4948 + \ + (function * 0x8))) +-#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3b30 : 0x1c20) +-#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10) +-#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200) ++#define TSTORM_TCP_MAX_CWND_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x4004 + (function * 0x8)) : (0x1fb4 + \ ++ (function * 0x8))) ++#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa000 : 0x3000) ++#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2000 : 0x1000) + #define USTORM_ASSERT_LIST_INDEX_OFFSET \ + (IS_E1H_OFFSET ? 0x8000 : 0x1000) + #define USTORM_ASSERT_LIST_OFFSET(idx) \ + (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) + #define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \ +- (IS_E1H_OFFSET ? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \ +- (0x5450 + (port * 0x1c8) + (clientId * 0x18))) +-#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ +- (IS_E1H_OFFSET ? (0x951a + ((function>>1) * 0x28) + \ +- ((function&1) * 0xa0) + (index * 0x4)) : (0x191a + (function * \ +- 0x28) + (index * 0x4))) +-#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x28) + \ +- ((function&1) * 0xa0)) : (0x1900 + (function * 0x28))) +-#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x28) + \ +- ((function&1) * 0xa0)) : (0x1908 + (function * 0x28))) ++ (IS_E1H_OFFSET ? (0x1010 + (port * 0x680) + (clientId * 0x40)) : \ ++ (0x4010 + (port * 0x360) + (clientId * 0x30))) ++#define USTORM_CQE_PAGE_NEXT_OFFSET(port, clientId) \ ++ (IS_E1H_OFFSET ? (0x1028 + (port * 0x680) + (clientId * 0x40)) : \ ++ (0x4028 + (port * 0x360) + (clientId * 0x30))) ++#define USTORM_ETH_PAUSE_ENABLED_OFFSET(port) \ ++ (IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff) ++#define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \ ++ (IS_E1H_OFFSET ? (0x1030 + (port * 0x680) + (clientId * 0x40)) : \ ++ 0xffffffff) ++#define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1dd0 + \ ++ (function * 0x8))) + #define USTORM_FUNCTION_MODE_OFFSET \ + (IS_E1H_OFFSET ? 0x2448 : 0xffffffff) +-#define USTORM_HC_BTR_OFFSET(port) \ +- (IS_E1H_OFFSET ? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8))) ++#define USTORM_ISCSI_CQ_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x7044 + (function * 0x8)) : (0x2414 + \ ++ (function * 0x8))) ++#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x7046 + (function * 0x8)) : (0x2416 + \ ++ (function * 0x8))) ++#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x7688 + (function * 0x8)) : (0x29c8 + \ ++ (function * 0x8))) ++#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x7648 + (function * 0x8)) : (0x29b8 + \ ++ (function * 0x8))) ++#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x7004 + (function * 0x8)) : (0x2404 + \ ++ (function * 0x8))) ++#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x7002 + (function * 0x8)) : (0x2402 + \ ++ (function * 0x8))) ++#define USTORM_ISCSI_PAGE_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x7000 + (function * 0x8)) : (0x2400 + \ ++ (function * 0x8))) ++#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x7040 + (function * 0x8)) : (0x2410 + \ ++ (function * 0x8))) ++#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x7080 + (function * 0x8)) : (0x2420 + \ ++ (function * 0x8))) ++#define USTORM_ISCSI_RQ_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x7084 + (function * 0x8)) : (0x2424 + \ ++ (function * 0x8))) + #define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \ +- (IS_E1H_OFFSET ? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \ +- (0x5448 + (port * 0x1c8) + (clientId * 0x18))) ++ (IS_E1H_OFFSET ? (0x1018 + (port * 0x680) + (clientId * 0x40)) : \ ++ (0x4018 + (port * 0x360) + (clientId * 0x30))) + #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5408 + \ ++ (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x1da8 + \ + (function * 0x8))) +-#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ +- (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \ +- (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ +- (index * 0x4))) +-#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ +- (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \ +- (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ +- (index * 0x4))) +-#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ +- (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \ +- (0x1400 + (port * 0x280) + (cpu_id * 0x28))) +-#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ +- (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \ +- (0x1408 + (port * 0x280) + (cpu_id * 0x28))) ++#define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ ++ (IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \ ++ 0x28)) : (0x1500 + (port * 0x2d0) + (stats_counter_id * 0x28))) ++#define USTORM_RX_PRODS_OFFSET(port, client_id) \ ++ (IS_E1H_OFFSET ? (0x1000 + (port * 0x680) + (client_id * 0x40)) \ ++ : (0x4000 + (port * 0x360) + (client_id * 0x30))) ++#define USTORM_STATS_FLAGS_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1db8 + \ ++ (function * 0x8))) ++#define USTORM_TPA_BTR_OFFSET (IS_E1H_OFFSET ? 0x3da5 : 0x5095) ++#define USTORM_TPA_BTR_SIZE 0x1 + #define XSTORM_ASSERT_LIST_INDEX_OFFSET \ + (IS_E1H_OFFSET ? 0x9000 : 0x1000) + #define XSTORM_ASSERT_LIST_OFFSET(idx) \ + (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) + #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \ +- (IS_E1H_OFFSET ? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40))) ++ (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3a80 + (port * 0x50))) + #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ + (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \ + ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ +@@ -149,23 +272,74 @@ + (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \ + ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) + #define XSTORM_E1HOV_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x2ab8 + (function * 0x2)) : 0xffffffff) ++ (IS_E1H_OFFSET ? (0x2c10 + (function * 0x8)) : 0xffffffff) + #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \ ++ (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3a50 + \ + (function * 0x8))) + #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x2568 + (function * 0x70)) : (0x3c60 + \ +- (function * 0x70))) ++ (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3b60 + \ ++ (function * 0x90))) + #define XSTORM_FUNCTION_MODE_OFFSET \ +- (IS_E1H_OFFSET ? 0x2ac8 : 0xffffffff) ++ (IS_E1H_OFFSET ? 0x2c50 : 0xffffffff) + #define XSTORM_HC_BTR_OFFSET(port) \ + (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18))) ++#define XSTORM_ISCSI_HQ_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x80c0 + (function * 0x8)) : (0x1c30 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8080 + (function * 0x8)) : (0x1c20 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8081 + (function * 0x8)) : (0x1c21 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8082 + (function * 0x8)) : (0x1c22 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8083 + (function * 0x8)) : (0x1c23 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8084 + (function * 0x8)) : (0x1c24 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8085 + (function * 0x8)) : (0x1c25 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8086 + (function * 0x8)) : (0x1c26 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8004 + (function * 0x8)) : (0x1c04 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8002 + (function * 0x8)) : (0x1c02 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8000 + (function * 0x8)) : (0x1c00 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x80c4 + (function * 0x8)) : (0x1c34 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_SQ_SIZE_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x80c2 + (function * 0x8)) : (0x1c32 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8043 + (function * 0x8)) : (0x1c13 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8042 + (function * 0x8)) : (0x1c12 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8041 + (function * 0x8)) : (0x1c11 + \ ++ (function * 0x8))) ++#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x8040 + (function * 0x8)) : (0x1c10 + \ ++ (function * 0x8))) + #define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ +- (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \ +- 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38))) ++ (IS_E1H_OFFSET ? (0xc000 + (port * 0x360) + (stats_counter_id * \ ++ 0x30)) : (0x3378 + (port * 0x360) + (stats_counter_id * 0x30))) + #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x2528 + (function * 0x70)) : (0x3c20 + \ +- (function * 0x70))) ++ (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3b20 + \ ++ (function * 0x90))) + #define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \ + (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \ + (function * 0x10))) +@@ -173,12 +347,19 @@ + (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \ + (function * 0x10))) + #define XSTORM_STATS_FLAGS_OFFSET(function) \ +- (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \ ++ (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3a40 + \ + (function * 0x8))) ++#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port) \ ++ (IS_E1H_OFFSET ? (0x4000 + (port * 0x8)) : (0x1960 + (port * 0x8))) ++#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port) \ ++ (IS_E1H_OFFSET ? (0x4001 + (port * 0x8)) : (0x1961 + (port * 0x8))) ++#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(function) \ ++ (IS_E1H_OFFSET ? (0x4060 + ((function>>1) * 0x8) + ((function&1) \ ++ * 0x4)) : (0x1978 + (function * 0x4))) + #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 + + /** +-* This file defines HSI constatnts for the ETH flow ++* This file defines HSI constants for the ETH flow + */ + #ifdef _EVEREST_MICROCODE + #include "microcode_constants.h" +@@ -195,49 +376,48 @@ + #define TCP_IPV4_HASH_TYPE 2 + #define IPV6_HASH_TYPE 3 + #define TCP_IPV6_HASH_TYPE 4 ++#define VLAN_PRI_HASH_TYPE 5 ++#define E1HOV_PRI_HASH_TYPE 6 ++#define DSCP_HASH_TYPE 7 + +-/* Ethernet Ring parmaters */ ++ ++/* Ethernet Ring parameters */ + #define X_ETH_LOCAL_RING_SIZE 13 + #define FIRST_BD_IN_PKT 0 + #define PARSE_BD_INDEX 1 +-#define NUM_OF_ETH_BDS_IN_PAGE \ +- ((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8)) +- ++#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8)) ++#define U_ETH_NUM_OF_SGES_TO_FETCH 8 ++#define U_ETH_MAX_SGES_FOR_PACKET 3 + + /* Rx ring params */ +-#define U_ETH_LOCAL_BD_RING_SIZE (16) +-#define U_ETH_LOCAL_SGE_RING_SIZE (12) +-#define U_ETH_SGL_SIZE (8) ++#define U_ETH_LOCAL_BD_RING_SIZE 8 ++#define U_ETH_LOCAL_SGE_RING_SIZE 10 ++#define U_ETH_SGL_SIZE 8 + +- +-#define U_ETH_BDS_PER_PAGE_MASK \ +- ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1) +-#define U_ETH_CQE_PER_PAGE_MASK \ +- ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1) +-#define U_ETH_SGES_PER_PAGE_MASK \ +- ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1) + + #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \ + (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) + +- +-#define TU_ETH_CQES_PER_PAGE \ +- (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8)) ++#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8)) + #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8)) + #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8)) ++ ++#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1) ++#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1) ++#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1) + + #define U_ETH_UNDEFINED_Q 0xFF + + /* values of command IDs in the ramrod message */ +-#define RAMROD_CMD_ID_ETH_PORT_SETUP (80) +-#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85) +-#define RAMROD_CMD_ID_ETH_STAT_QUERY (90) +-#define RAMROD_CMD_ID_ETH_UPDATE (100) +-#define RAMROD_CMD_ID_ETH_HALT (105) +-#define RAMROD_CMD_ID_ETH_SET_MAC (110) +-#define RAMROD_CMD_ID_ETH_CFC_DEL (115) +-#define RAMROD_CMD_ID_ETH_PORT_DEL (120) +-#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125) ++#define RAMROD_CMD_ID_ETH_PORT_SETUP 80 ++#define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85 ++#define RAMROD_CMD_ID_ETH_STAT_QUERY 90 ++#define RAMROD_CMD_ID_ETH_UPDATE 100 ++#define RAMROD_CMD_ID_ETH_HALT 105 ++#define RAMROD_CMD_ID_ETH_SET_MAC 110 ++#define RAMROD_CMD_ID_ETH_CFC_DEL 115 ++#define RAMROD_CMD_ID_ETH_PORT_DEL 120 ++#define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125 + + + /* command values for set mac command */ +@@ -250,16 +430,23 @@ + #define T_ETH_CRC32_HASH_SEED 0x00000000 + + /* Maximal L2 clients supported */ +-#define ETH_MAX_RX_CLIENTS_E1 19 +-#define ETH_MAX_RX_CLIENTS_E1H 25 ++#define ETH_MAX_RX_CLIENTS_E1 18 ++#define ETH_MAX_RX_CLIENTS_E1H 26 + + /* Maximal aggregation queues supported */ +-#define ETH_MAX_AGGREGATION_QUEUES_E1 (32) +-#define ETH_MAX_AGGREGATION_QUEUES_E1H (64) ++#define ETH_MAX_AGGREGATION_QUEUES_E1 32 ++#define ETH_MAX_AGGREGATION_QUEUES_E1H 64 ++ ++/* ETH RSS modes */ ++#define ETH_RSS_MODE_DISABLED 0 ++#define ETH_RSS_MODE_REGULAR 1 ++#define ETH_RSS_MODE_VLAN_PRI 2 ++#define ETH_RSS_MODE_E1HOV_PRI 3 ++#define ETH_RSS_MODE_IP_DSCP 4 + + + /** +-* This file defines HSI constatnts common to all microcode flows ++* This file defines HSI constants common to all microcode flows + */ + + /* Connection types */ +@@ -278,25 +465,22 @@ + #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) + #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) + #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) +-#define ISCSI_STATE \ +- (ISCSI_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) +-#define FCOE_STATE (FCOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) + + /* microcode fixed page page size 4K (chains and ring segments) */ +-#define MC_PAGE_SIZE (4096) ++#define MC_PAGE_SIZE 4096 + + + /* Host coalescing constants */ + + /* index numbers */ +-#define HC_USTORM_DEF_SB_NUM_INDICES 4 ++#define HC_USTORM_DEF_SB_NUM_INDICES 8 + #define HC_CSTORM_DEF_SB_NUM_INDICES 8 + #define HC_XSTORM_DEF_SB_NUM_INDICES 4 + #define HC_TSTORM_DEF_SB_NUM_INDICES 4 + #define HC_USTORM_SB_NUM_INDICES 4 + #define HC_CSTORM_SB_NUM_INDICES 4 + +-/* index values - which counterto update */ ++/* index values - which counter to update */ + + #define HC_INDEX_U_TOE_RX_CQ_CONS 0 + #define HC_INDEX_U_ETH_RX_CQ_CONS 1 +@@ -315,12 +499,14 @@ + #define HC_INDEX_DEF_C_ETH_SLOW_PATH 3 + #define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4 + #define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5 ++#define HC_INDEX_DEF_C_ETH_FCOE_CQ_CONS 6 + + #define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0 + #define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1 + #define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2 + #define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3 +- ++#define HC_INDEX_DEF_U_ETH_FCOE_RX_CQ_CONS 4 ++#define HC_INDEX_DEF_U_ETH_FCOE_RX_BD_CONS 5 + + /* used by the driver to get the SB offset */ + #define USTORM_ID 0 +@@ -330,16 +516,16 @@ + #define ATTENTION_ID 4 + + /* max number of slow path commands per port */ +-#define MAX_RAMRODS_PER_PORT (8) ++#define MAX_RAMRODS_PER_PORT 8 + + /* values for RX ETH CQE type field */ +-#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0) +-#define RX_ETH_CQE_TYPE_ETH_RAMROD (1) ++#define RX_ETH_CQE_TYPE_ETH_FASTPATH 0 ++#define RX_ETH_CQE_TYPE_ETH_RAMROD 1 + + + /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ +-#define EMULATION_FREQUENCY_FACTOR (1600) +-#define FPGA_FREQUENCY_FACTOR (100) ++#define EMULATION_FREQUENCY_FACTOR 1600 ++#define FPGA_FREQUENCY_FACTOR 100 + + #define TIMERS_TICK_SIZE_CHIP (1e-3) + #define TIMERS_TICK_SIZE_EMUL \ +@@ -353,12 +539,9 @@ + #define TSEMI_CLK1_RESUL_FPGA \ + ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) + +-#define USEMI_CLK1_RESUL_CHIP \ +- (TIMERS_TICK_SIZE_CHIP) +-#define USEMI_CLK1_RESUL_EMUL \ +- (TIMERS_TICK_SIZE_EMUL) +-#define USEMI_CLK1_RESUL_FPGA \ +- (TIMERS_TICK_SIZE_FPGA) ++#define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP) ++#define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL) ++#define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA) + + #define XSEMI_CLK1_RESUL_CHIP (1e-3) + #define XSEMI_CLK1_RESUL_EMUL \ +@@ -383,12 +566,15 @@ + #define XSTORM_IP_ID_ROLL_HALF 0x8000 + #define XSTORM_IP_ID_ROLL_ALL 0 + +-#define FW_LOG_LIST_SIZE (50) ++#define FW_LOG_LIST_SIZE 50 + + #define NUM_OF_PROTOCOLS 4 +-#define MAX_COS_NUMBER 16 ++#define NUM_OF_SAFC_BITS 16 ++#define MAX_COS_NUMBER 4 + #define MAX_T_STAT_COUNTER_ID 18 + #define MAX_X_STAT_COUNTER_ID 18 ++#define MAX_U_STAT_COUNTER_ID 18 ++ + + #define UNKNOWN_ADDRESS 0 + #define UNICAST_ADDRESS 1 +diff -r e67cb9a8e847 drivers/net/bnx2x_fw_file_hdr.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/bnx2x_fw_file_hdr.h Wed Aug 05 10:51:02 2009 +0100 +@@ -0,0 +1,37 @@ ++/* bnx2x_fw_file_hdr.h: FW binary file header structure. ++ * ++ * Copyright (c) 2007-2009 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ * ++ * Maintained by: Eilon Greenstein ++ * Written by: Vladislav Zolotarov ++ * Based on the original idea of John Wright . ++ */ ++ ++#ifndef BNX2X_INIT_FILE_HDR_H ++#define BNX2X_INIT_FILE_HDR_H ++ ++struct bnx2x_fw_file_section { ++ __be32 len; ++ __be32 offset; ++}; ++ ++struct bnx2x_fw_file_hdr { ++ struct bnx2x_fw_file_section init_ops; ++ struct bnx2x_fw_file_section init_ops_offsets; ++ struct bnx2x_fw_file_section init_data; ++ struct bnx2x_fw_file_section tsem_int_table_data; ++ struct bnx2x_fw_file_section tsem_pram_data; ++ struct bnx2x_fw_file_section usem_int_table_data; ++ struct bnx2x_fw_file_section usem_pram_data; ++ struct bnx2x_fw_file_section csem_int_table_data; ++ struct bnx2x_fw_file_section csem_pram_data; ++ struct bnx2x_fw_file_section xsem_int_table_data; ++ struct bnx2x_fw_file_section xsem_pram_data; ++ struct bnx2x_fw_file_section fw_version; ++}; ++ ++#endif /* BNX2X_INIT_FILE_HDR_H */ +diff -r e67cb9a8e847 drivers/net/bnx2x_hsi.h +--- a/drivers/net/bnx2x_hsi.h Wed Aug 05 10:50:39 2009 +0100 ++++ b/drivers/net/bnx2x_hsi.h Wed Aug 05 10:51:02 2009 +0100 +@@ -1,11 +1,25 @@ + /* bnx2x_hsi.h: Broadcom Everest network driver. + * +- * Copyright (c) 2007-2008 Broadcom Corporation ++ * Copyright (c) 2007-2009 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation. + */ ++ ++struct license_key { ++ u32 reserved[6]; ++ ++#if defined(__BIG_ENDIAN) ++ u16 max_iscsi_init_conn; ++ u16 max_iscsi_trgt_conn; ++#elif defined(__LITTLE_ENDIAN) ++ u16 max_iscsi_trgt_conn; ++ u16 max_iscsi_init_conn; ++#endif ++ ++ u32 reserved_a[6]; ++}; + + + #define PORT_0 0 +@@ -91,6 +105,49 @@ + + #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 + ++#define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 ++#define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 ++ ++ /* Output low when PERST is asserted */ ++#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 ++#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 ++ ++#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 ++#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 ++#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 ++#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 /* 0dB */ ++#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 /* -3.5dB */ ++#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 /* -6.0dB */ ++ ++ /* The fan failure mechanism is usually related to the PHY type ++ since the power consumption of the board is determined by the PHY. ++ Currently, fan is required for most designs with SFX7101, BCM8727 ++ and BCM8481. If a fan is not required for a board which uses one ++ of those PHYs, this field should be set to "Disabled". If a fan is ++ required for a different PHY type, this option should be set to ++ "Enabled". ++ The fan failure indication is expected on ++ SPIO5 */ ++#define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 ++#define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 ++#define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 ++#define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 ++#define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 ++ ++ /* ASPM Power Management support */ ++#define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 ++#define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 ++#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 ++#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 ++#define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 ++#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 ++ ++ /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register ++ tl_control_0 (register 0x2800) */ ++#define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 ++#define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 ++ ++ + u32 power_dissipated; /* 0x11c */ + #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 + #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 +@@ -119,34 +176,14 @@ + #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 + + u32 board; /* 0x124 */ +-#define SHARED_HW_CFG_BOARD_TYPE_MASK 0x0000ffff +-#define SHARED_HW_CFG_BOARD_TYPE_SHIFT 0 +-#define SHARED_HW_CFG_BOARD_TYPE_NONE 0x00000000 +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1000 0x00000001 +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1001 0x00000002 +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G 0x00000003 +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1004G 0x00000004 +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1007G 0x00000005 +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006 +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007 +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008 +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009 +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1023G 0x0000000b +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1033G 0x0000000c +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957711T1101 0x0000000d +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957711ET1201 0x0000000e +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957711A1133G 0x0000000f +-#define SHARED_HW_CFG_BOARD_TYPE_BCM957711EA1233G 0x00000010 +- +-#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000 +-#define SHARED_HW_CFG_BOARD_VER_SHIFT 16 +-#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0xf0000000 +-#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 28 +-#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0x0f000000 +-#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 24 + #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 + #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 ++ ++#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 ++#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 ++ ++#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 ++#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 + + u32 reserved; /* 0x128 */ + +@@ -198,36 +235,24 @@ + u32 rdma_mac_lower; + + u32 serdes_config; +- /* for external PHY, or forced mode or during AN */ +-#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000 +-#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16 ++#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff ++#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 + +-#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff +-#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0 ++#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 ++#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 + +- u16 serdes_tx_driver_pre_emphasis[16]; +- u16 serdes_rx_driver_equalizer[16]; + +- u32 xgxs_config_lane0; +- u32 xgxs_config_lane1; +- u32 xgxs_config_lane2; +- u32 xgxs_config_lane3; +- /* for external PHY, or forced mode or during AN */ +-#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000 +-#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16 ++ u32 reserved0[16]; /* 0x158 */ + +-#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff +-#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0 ++ /* 4 times 16 bits for all 4 lanes. In case external PHY is present ++ (not direct mode), those values will not take effect on the 4 XGXS ++ lanes. For some external PHYs (such as 8706 and 8726) the values ++ will be used to configure the external PHY – in those cases, not ++ all 4 values are needed. */ ++ u16 xgxs_config_rx[4]; /* 0x198 */ ++ u16 xgxs_config_tx[4]; /* 0x1A0 */ + +- u16 xgxs_tx_driver_pre_emphasis_lane0[16]; +- u16 xgxs_tx_driver_pre_emphasis_lane1[16]; +- u16 xgxs_tx_driver_pre_emphasis_lane2[16]; +- u16 xgxs_tx_driver_pre_emphasis_lane3[16]; +- +- u16 xgxs_rx_driver_equalizer_lane0[16]; +- u16 xgxs_rx_driver_equalizer_lane1[16]; +- u16 xgxs_rx_driver_equalizer_lane2[16]; +- u16 xgxs_rx_driver_equalizer_lane3[16]; ++ u32 reserved1[64]; /* 0x1A8 */ + + u32 lane_config; + #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff +@@ -265,9 +290,11 @@ + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 +-#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600 ++#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 ++#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 ++#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 + +@@ -307,7 +334,9 @@ + #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800 + #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 + +- u32 reserved[2]; ++ /* A place to hold the original MAC address as a backup */ ++ u32 backup_mac_upper; /* 0x2B4 */ ++ u32 backup_mac_lower; /* 0x2B8 */ + + }; + +@@ -319,7 +348,24 @@ + + u32 config; /* 0x450 */ + #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 +-#define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100 ++ ++ /* Use NVRAM values instead of HW default values */ ++#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000 ++#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002 ++ ++#define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 ++#define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 ++ ++#define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 ++#define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 ++ ++ /* Override the OTP back to single function mode. When using GPIO, ++ high means only SF, 0 is according to CLP configuration */ ++#define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 ++#define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 ++#define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 ++#define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 ++#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 + + }; + +@@ -372,6 +418,21 @@ + #define PORT_FEATURE_MBA_ENABLED 0x02000000 + #define PORT_FEATURE_MFW_ENABLED 0x04000000 + ++ /* Advertise expansion ROM even if MBA is disabled */ ++#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 ++#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 ++ ++ /* Reserved bits: 28-29 */ ++ /* Check the optic vendor via i2c against a list of approved modules ++ in a separate nvram image */ ++#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 ++#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 ++#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT 0x00000000 ++#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER 0x20000000 ++#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 ++#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 ++ ++ + u32 wol_config; + /* Default is used when driver sets to "auto" mode */ + #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 +@@ -385,12 +446,13 @@ + #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 + + u32 mba_config; +-#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003 ++#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 + #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 + #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 + #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 + #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 + #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 ++#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 + #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 + #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 + #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 +@@ -512,7 +574,7 @@ + /**************************************************************************** + * Device Information * + ****************************************************************************/ +-struct dev_info { /* size */ ++struct shm_dev_info { /* size */ + + u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ + +@@ -641,7 +703,10 @@ + + u32 port_stx; + +- u32 reserved[2]; ++ u32 stat_nig_timer; ++ ++ /* MCP firmware does not use this field */ ++ u32 ext_phy_fw_version; + + }; + +@@ -656,6 +721,8 @@ + #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 + #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 + #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 ++#define DRV_MSG_CODE_DCC_OK 0x30000000 ++#define DRV_MSG_CODE_DCC_FAILURE 0x31000000 + #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 + #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 + #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 +@@ -663,6 +730,12 @@ + #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 + #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 + #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 ++ /* ++ * The optic module verification commands requris bootcode ++ * v5.0.6 or later ++ */ ++#define DRV_MSG_CODE_VRFY_OPT_MDL 0xa0000000 ++#define REQ_BC_VER_4_VRFY_OPT_MDL 0x00050006 + + #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 + #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 +@@ -684,6 +757,7 @@ + #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 + #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 + #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 ++#define FW_MSG_CODE_DCC_DONE 0x30100000 + #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 + #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 + #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 +@@ -697,6 +771,9 @@ + #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 + #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 + #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 ++#define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 ++#define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 ++#define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 + + #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 + #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 +@@ -731,6 +808,14 @@ + u32 drv_status; + #define DRV_STATUS_PMF 0x00000001 + ++#define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 ++#define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 ++#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 ++#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 ++#define DRV_STATUS_DCC_RESERVED1 0x00000800 ++#define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 ++#define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 ++ + u32 virt_mac_upper; + #define VIRT_MAC_SIGN_MASK 0xffff0000 + #define VIRT_MAC_SIGNATURE 0x564d0000 +@@ -767,10 +852,9 @@ + struct port_mf_cfg { + + u32 dynamic_cfg; /* device control channel */ +-#define PORT_MF_CFG_OUTER_VLAN_TAG_MASK 0x0000ffff +-#define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT 0 +-#define PORT_MF_CFG_DYNAMIC_CFG_ENABLED 0x00010000 +-#define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT 0x00000000 ++#define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff ++#define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 ++#define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK + + u32 reserved[3]; + +@@ -827,11 +911,7 @@ + + struct shared_mf_cfg shared_mf_config; + struct port_mf_cfg port_mf_config[PORT_MAX]; +-#if defined(b710) +- struct func_mf_cfg func_mf_config[E1_FUNC_MAX]; +-#else + struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; +-#endif + + }; + +@@ -862,20 +942,42 @@ + #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 + #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 + +- struct dev_info dev_info; /* 0x8 (0x438) */ ++ struct shm_dev_info dev_info; /* 0x8 (0x438) */ + +- u8 reserved[52*PORT_MAX]; ++struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ + + /* FW information (for internal FW use) */ + u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ + struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ + + struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ ++#if !defined(b710) /* BNX2X_UPSTREAM */ + struct drv_func_mb func_mb[E1H_FUNC_MAX]; ++#else ++ struct drv_func_mb func_mb[E1_FUNC_MAX]; /* 0x684 (44*2=0x58) */ ++#endif + ++#if !defined(b710) /* BNX2X_UPSTREAM */ + struct mf_cfg mf_cfg; ++#endif + + }; /* 0x6dc */ ++ ++ ++struct shmem2_region { ++ ++ u32 size; ++ ++ u32 dcc_support; ++#define SHMEM_DCC_SUPPORT_NONE 0x00000000 ++#define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 ++#define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 ++#define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 ++#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 ++#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 ++#define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE ++ ++}; + + + struct emac_stats { +@@ -1211,9 +1313,10 @@ + }; + + +-#define BCM_5710_FW_MAJOR_VERSION 4 +-#define BCM_5710_FW_MINOR_VERSION 5 +-#define BCM_5710_FW_REVISION_VERSION 1 ++#define BCM_5710_FW_MAJOR_VERSION 5 ++#define BCM_5710_FW_MINOR_VERSION 0 ++#define BCM_5710_FW_REVISION_VERSION 21 ++#define BCM_5710_FW_ENGINEERING_VERSION 0 + #define BCM_5710_FW_COMPILE_FLAGS 1 + + +@@ -1221,18 +1324,12 @@ + * attention bits + */ + struct atten_def_status_block { +- u32 attn_bits; +- u32 attn_bits_ack; +-#if defined(__BIG_ENDIAN) +- u16 attn_bits_index; +- u8 reserved0; +- u8 status_block_id; +-#elif defined(__LITTLE_ENDIAN) ++ __le32 attn_bits; ++ __le32 attn_bits_ack; + u8 status_block_id; + u8 reserved0; +- u16 attn_bits_index; +-#endif +- u32 reserved1; ++ __le16 attn_bits_index; ++ __le32 reserved1; + }; + + +@@ -1263,6 +1360,22 @@ + struct doorbell_hdr header; + u8 zero_fill1; + u16 zero_fill2; ++#endif ++}; ++ ++ ++/* ++ * doorbell message sent to the chip ++ */ ++struct doorbell_set_prod { ++#if defined(__BIG_ENDIAN) ++ u16 prod; ++ u8 zero_fill1; ++ struct doorbell_hdr header; ++#elif defined(__LITTLE_ENDIAN) ++ struct doorbell_hdr header; ++ u8 zero_fill1; ++ u16 prod; + #endif + }; + +@@ -1302,10 +1415,66 @@ + + + /* ++ * IGU driver acknowledgement register ++ */ ++struct igu_backward_compatible { ++ u32 sb_id_and_flags; ++#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) ++#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 ++#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) ++#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 ++#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) ++#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 ++#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) ++#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 ++#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) ++#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 ++#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) ++#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 ++ u32 reserved_2; ++}; ++ ++ ++/* ++ * IGU driver acknowledgement register ++ */ ++struct igu_regular { ++ u32 sb_id_and_flags; ++#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) ++#define IGU_REGULAR_SB_INDEX_SHIFT 0 ++#define IGU_REGULAR_RESERVED0 (0x1<<20) ++#define IGU_REGULAR_RESERVED0_SHIFT 20 ++#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) ++#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 ++#define IGU_REGULAR_BUPDATE (0x1<<24) ++#define IGU_REGULAR_BUPDATE_SHIFT 24 ++#define IGU_REGULAR_ENABLE_INT (0x3<<25) ++#define IGU_REGULAR_ENABLE_INT_SHIFT 25 ++#define IGU_REGULAR_RESERVED_1 (0x1<<27) ++#define IGU_REGULAR_RESERVED_1_SHIFT 27 ++#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) ++#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 ++#define IGU_REGULAR_CLEANUP_SET (0x1<<30) ++#define IGU_REGULAR_CLEANUP_SET_SHIFT 30 ++#define IGU_REGULAR_BCLEANUP (0x1<<31) ++#define IGU_REGULAR_BCLEANUP_SHIFT 31 ++ u32 reserved_2; ++}; ++ ++/* ++ * IGU driver acknowledgement register ++ */ ++union igu_consprod_reg { ++ struct igu_regular regular; ++ struct igu_backward_compatible backward_compatible; ++}; ++ ++ ++/* + * Parser parsing flags field + */ + struct parsing_flags { +- u16 flags; ++ __le16 flags; + #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) + #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 + #define PARSING_FLAGS_VLAN (0x1<<1) +@@ -1336,8 +1505,8 @@ + + + struct regpair { +- u32 lo; +- u32 hi; ++ __le32 lo; ++ __le32 hi; + }; + + +@@ -1432,8 +1601,8 @@ + #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1 + #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2) + #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2 +-#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3) +-#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3 ++#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3) ++#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3 + #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4) + #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4 + u8 status_block_id; +@@ -1458,16 +1627,18 @@ + #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1 + #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2) + #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2 +-#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3) +-#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3 ++#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3) ++#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3 + #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4) + #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4 + #endif + #if defined(__BIG_ENDIAN) + u16 bd_buff_size; +- u16 mc_alignment_size; ++ u8 statistics_counter_id; ++ u8 mc_alignment_log_size; + #elif defined(__LITTLE_ENDIAN) +- u16 mc_alignment_size; ++ u8 mc_alignment_log_size; ++ u8 statistics_counter_id; + u16 bd_buff_size; + #endif + #if defined(__BIG_ENDIAN) +@@ -1480,40 +1651,59 @@ + u8 __local_sge_prod; + #endif + #if defined(__BIG_ENDIAN) +- u16 __bd_cons; +- u16 __sge_cons; ++ u16 __sdm_bd_expected_counter; ++ u8 cstorm_agg_int; ++ u8 __expected_bds_on_ram; + #elif defined(__LITTLE_ENDIAN) +- u16 __sge_cons; +- u16 __bd_cons; ++ u8 __expected_bds_on_ram; ++ u8 cstorm_agg_int; ++ u16 __sdm_bd_expected_counter; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 __ring_data_ram_addr; ++ u16 __hc_cstorm_ram_addr; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __hc_cstorm_ram_addr; ++ u16 __ring_data_ram_addr; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 reserved1; ++ u8 max_sges_for_packet; ++ u16 __bd_ring_ram_addr; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __bd_ring_ram_addr; ++ u8 max_sges_for_packet; ++ u8 reserved1; + #endif + u32 bd_page_base_lo; + u32 bd_page_base_hi; + u32 sge_page_base_lo; + u32 sge_page_base_hi; ++ struct regpair reserved2; + }; + + /* + * The eth Rx Buffer Descriptor + */ + struct eth_rx_bd { +- u32 addr_lo; +- u32 addr_hi; ++ __le32 addr_lo; ++ __le32 addr_hi; + }; + + /* + * The eth Rx SGE Descriptor + */ + struct eth_rx_sge { +- u32 addr_lo; +- u32 addr_hi; ++ __le32 addr_lo; ++ __le32 addr_hi; + }; + + /* + * Local BDs and SGEs rings (in ETH) + */ + struct eth_local_rx_rings { +- struct eth_rx_bd __local_bd_ring[16]; +- struct eth_rx_sge __local_sge_ring[12]; ++ struct eth_rx_bd __local_bd_ring[8]; ++ struct eth_rx_sge __local_sge_ring[10]; + }; + + /* +@@ -1605,13 +1795,13 @@ + */ + struct xstorm_eth_ag_context { + #if defined(__BIG_ENDIAN) +- u16 __bd_prod; ++ u16 agg_val1; + u8 __agg_vars1; + u8 __state; + #elif defined(__LITTLE_ENDIAN) + u8 __state; + u8 __agg_vars1; +- u16 __bd_prod; ++ u16 agg_val1; + #endif + #if defined(__BIG_ENDIAN) + u8 cdu_reserved; +@@ -1624,7 +1814,7 @@ + u8 __agg_vars4; + u8 cdu_reserved; + #endif +- u32 __more_packets_to_send; ++ u32 __bd_prod; + #if defined(__BIG_ENDIAN) + u16 __agg_vars5; + u16 __agg_val4_th; +@@ -1697,7 +1887,7 @@ + }; + + /* +- * The eth aggregative context section of Tstorm ++ * The eth extra aggregative context section of Tstorm + */ + struct tstorm_eth_extra_ag_context_section { + u32 __agg_val1; +@@ -1890,8 +2080,8 @@ + #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0 + #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1) + #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1 +-#define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2) +-#define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2 ++#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<2) ++#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 2 + #define ETH_TX_BD_FLAGS_END_BD (0x1<<3) + #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3 + #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) +@@ -1907,18 +2097,29 @@ + /* + * The eth Tx Buffer Descriptor + */ ++struct eth_tx_start_bd { ++ __le32 addr_lo; ++ __le32 addr_hi; ++ __le16 nbd; ++ __le16 nbytes; ++ __le16 vlan; ++ struct eth_tx_bd_flags bd_flags; ++ u8 general_data; ++#define ETH_TX_START_BD_HDR_NBDS (0x3F<<0) ++#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 ++#define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6) ++#define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6 ++}; ++ ++/* ++ * Tx regular BD structure ++ */ + struct eth_tx_bd { + u32 addr_lo; + u32 addr_hi; +- u16 nbd; ++ u16 total_pkt_bytes; + u16 nbytes; +- u16 vlan; +- struct eth_tx_bd_flags bd_flags; +- u8 general_data; +-#define ETH_TX_BD_HDR_NBDS (0x3F<<0) +-#define ETH_TX_BD_HDR_NBDS_SHIFT 0 +-#define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6) +-#define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6 ++ u8 reserved[4]; + }; + + /* +@@ -1928,8 +2129,8 @@ + u8 global_data; + #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0) + #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0 +-#define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4) +-#define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4 ++#define ETH_TX_PARSE_BD_UDP_CS_FLG (0x1<<4) ++#define ETH_TX_PARSE_BD_UDP_CS_FLG_SHIFT 4 + #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5) + #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5 + #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6) +@@ -1954,27 +2155,28 @@ + #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7) + #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7 + u8 ip_hlen; +- s8 cs_offset; +- u16 total_hlen; +- u16 lso_mss; +- u16 tcp_pseudo_csum; +- u16 ip_id; +- u32 tcp_send_seq; ++ s8 reserved; ++ __le16 total_hlen; ++ __le16 tcp_pseudo_csum; ++ __le16 lso_mss; ++ __le16 ip_id; ++ __le32 tcp_send_seq; + }; + + /* + * The last BD in the BD memory will hold a pointer to the next BD memory + */ + struct eth_tx_next_bd { +- u32 addr_lo; +- u32 addr_hi; ++ __le32 addr_lo; ++ __le32 addr_hi; + u8 reserved[8]; + }; + + /* +- * union for 3 Bd types ++ * union for 4 Bd types + */ + union eth_tx_bd_types { ++ struct eth_tx_start_bd start_bd; + struct eth_tx_bd reg_bd; + struct eth_tx_parse_bd parse_bd; + struct eth_tx_next_bd next_bd; +@@ -2003,11 +2205,35 @@ + #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7 + u16 tx_bd_cons; + #endif +- u32 db_data_addr_lo; +- u32 db_data_addr_hi; +- u32 __pkt_cons; +- u32 __gso_next; +- u32 is_eth_conn_1b; ++ u32 __reserved1; ++ u32 __reserved2; ++#if defined(__BIG_ENDIAN) ++ u8 __ram_cache_index; ++ u8 __double_buffer_client; ++ u16 __pkt_cons; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __pkt_cons; ++ u8 __double_buffer_client; ++ u8 __ram_cache_index; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 __statistics_address; ++ u16 __gso_next; ++#elif defined(__LITTLE_ENDIAN) ++ u16 __gso_next; ++ u16 __statistics_address; ++#endif ++#if defined(__BIG_ENDIAN) ++ u8 __local_tx_bd_cons; ++ u8 safc_group_num; ++ u8 safc_group_en; ++ u8 __is_eth_conn; ++#elif defined(__LITTLE_ENDIAN) ++ u8 __is_eth_conn; ++ u8 safc_group_en; ++ u8 safc_group_num; ++ u8 __local_tx_bd_cons; ++#endif + union eth_tx_bd_types __bds[13]; + }; + +@@ -2072,47 +2298,47 @@ + + + /* +- * ustorm status block ++ * cstorm default status block, generated by ustorm + */ +-struct ustorm_def_status_block { +- u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES]; +- u16 status_block_index; ++struct cstorm_def_status_block_u { ++ __le16 index_values[HC_USTORM_DEF_SB_NUM_INDICES]; ++ __le16 status_block_index; + u8 func; + u8 status_block_id; +- u32 __flags; ++ __le32 __flags; + }; + + /* +- * cstorm status block ++ * cstorm default status block, generated by cstorm + */ +-struct cstorm_def_status_block { +- u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES]; +- u16 status_block_index; ++struct cstorm_def_status_block_c { ++ __le16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES]; ++ __le16 status_block_index; + u8 func; + u8 status_block_id; +- u32 __flags; ++ __le32 __flags; + }; + + /* + * xstorm status block + */ + struct xstorm_def_status_block { +- u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES]; +- u16 status_block_index; ++ __le16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES]; ++ __le16 status_block_index; + u8 func; + u8 status_block_id; +- u32 __flags; ++ __le32 __flags; + }; + + /* + * tstorm status block + */ + struct tstorm_def_status_block { +- u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES]; +- u16 status_block_index; ++ __le16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES]; ++ __le16 status_block_index; + u8 func; + u8 status_block_id; +- u32 __flags; ++ __le32 __flags; + }; + + /* +@@ -2120,41 +2346,41 @@ + */ + struct host_def_status_block { + struct atten_def_status_block atten_status_block; +- struct ustorm_def_status_block u_def_status_block; +- struct cstorm_def_status_block c_def_status_block; ++ struct cstorm_def_status_block_u u_def_status_block; ++ struct cstorm_def_status_block_c c_def_status_block; + struct xstorm_def_status_block x_def_status_block; + struct tstorm_def_status_block t_def_status_block; + }; + + + /* +- * ustorm status block ++ * cstorm status block, generated by ustorm + */ +-struct ustorm_status_block { +- u16 index_values[HC_USTORM_SB_NUM_INDICES]; +- u16 status_block_index; ++struct cstorm_status_block_u { ++ __le16 index_values[HC_USTORM_SB_NUM_INDICES]; ++ __le16 status_block_index; + u8 func; + u8 status_block_id; +- u32 __flags; ++ __le32 __flags; + }; + + /* +- * cstorm status block ++ * cstorm status block, generated by cstorm + */ +-struct cstorm_status_block { +- u16 index_values[HC_CSTORM_SB_NUM_INDICES]; +- u16 status_block_index; ++struct cstorm_status_block_c { ++ __le16 index_values[HC_CSTORM_SB_NUM_INDICES]; ++ __le16 status_block_index; + u8 func; + u8 status_block_id; +- u32 __flags; ++ __le32 __flags; + }; + + /* + * host status block + */ + struct host_status_block { +- struct ustorm_status_block u_status_block; +- struct cstorm_status_block c_status_block; ++ struct cstorm_status_block_u u_status_block; ++ struct cstorm_status_block_c c_status_block; + }; + + +@@ -2162,19 +2388,10 @@ + * The data for RSS setup ramrod + */ + struct eth_client_setup_ramrod_data { +- u32 client_id_5b; +- u8 is_rdma_1b; +- u8 reserved0; ++ u32 client_id; ++ u8 is_rdma; ++ u8 is_fcoe; + u16 reserved1; +-}; +- +- +-/* +- * L2 dynamic host coalescing init parameters +- */ +-struct eth_dynamic_hc_config { +- u32 threshold[3]; +- u8 hc_timeout[4]; + }; + + +@@ -2212,12 +2429,12 @@ + #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 + u8 placement_offset; + u8 queue_index; +- u32 rss_hash_result; +- u16 vlan_tag; +- u16 pkt_len; +- u16 len_on_bd; ++ __le32 rss_hash_result; ++ __le16 vlan_tag; ++ __le16 pkt_len; ++ __le16 len_on_bd; + struct parsing_flags pars_flags; +- u16 sgl[8]; ++ __le16 sgl[8]; + }; + + +@@ -2225,7 +2442,7 @@ + * The data for RSS setup ramrod + */ + struct eth_halt_ramrod_data { +- u32 client_id_5b; ++ u32 client_id; + u32 reserved0; + }; + +@@ -2236,11 +2453,11 @@ + struct eth_query_ramrod_data { + #if defined(__BIG_ENDIAN) + u8 reserved0; +- u8 collect_port_1b; ++ u8 collect_port; + u16 drv_counter; + #elif defined(__LITTLE_ENDIAN) + u16 drv_counter; +- u8 collect_port_1b; ++ u8 collect_port; + u8 reserved0; + #endif + u32 ctr_id_vector; +@@ -2251,8 +2468,8 @@ + * Place holder for ramrods protocol specific data + */ + struct ramrod_data { +- u32 data_lo; +- u32 data_hi; ++ __le32 data_lo; ++ __le32 data_hi; + }; + + /* +@@ -2260,16 +2477,6 @@ + */ + union eth_ramrod_data { + struct ramrod_data general; +-}; +- +- +-/* +- * Rx Last BD in page (in ETH) +- */ +-struct eth_rx_bd_next_page { +- u32 addr_lo; +- u32 addr_hi; +- u8 reserved[8]; + }; + + +@@ -2282,24 +2489,24 @@ + #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 + #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1) + #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1 +- u8 conn_type_3b; +- u16 reserved1; +- u32 conn_and_cmd_data; ++ u8 conn_type; ++ __le16 reserved1; ++ __le32 conn_and_cmd_data; + #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) + #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 + #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) + #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 + struct ramrod_data protocol_data; +- u32 reserved2[4]; ++ __le32 reserved2[4]; + }; + + /* + * Rx Last CQE in page (in ETH) + */ + struct eth_rx_cqe_next_page { +- u32 addr_lo; +- u32 addr_hi; +- u32 reserved[6]; ++ __le32 addr_lo; ++ __le32 addr_hi; ++ __le32 reserved[6]; + }; + + /* +@@ -2316,17 +2523,17 @@ + * common data for all protocols + */ + struct spe_hdr { +- u32 conn_and_cmd_data; ++ __le32 conn_and_cmd_data; + #define SPE_HDR_CID (0xFFFFFF<<0) + #define SPE_HDR_CID_SHIFT 0 + #define SPE_HDR_CMD_ID (0xFF<<24) + #define SPE_HDR_CMD_ID_SHIFT 24 +- u16 type; ++ __le16 type; + #define SPE_HDR_CONN_TYPE (0xFF<<0) + #define SPE_HDR_CONN_TYPE_SHIFT 0 + #define SPE_HDR_COMMON_RAMROD (0xFF<<8) + #define SPE_HDR_COMMON_RAMROD_SHIFT 8 +- u16 reserved; ++ __le16 reserved; + }; + + /* +@@ -2352,12 +2559,10 @@ + + + /* +- * doorbell data in host memory ++ * array of 13 bds as appears in the eth xstorm context + */ +-struct eth_tx_db_data { +- u32 packets_prod; +- u16 bds_prod; +- u16 reserved; ++struct eth_tx_bds_array { ++ union eth_tx_bd_types bds[13]; + }; + + +@@ -2377,14 +2582,18 @@ + #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 + #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) + #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 +-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4) +-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4 +-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5) +-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5 +-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6) +-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6 +-#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7) +-#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7 ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7) ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7 ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8) ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8 ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9) ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9 ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10) ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10 ++#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11) ++#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11 + #elif defined(__LITTLE_ENDIAN) + u16 config_flags; + #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) +@@ -2395,18 +2604,48 @@ + #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 + #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) + #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 +-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4) +-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4 +-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5) +-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5 +-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6) +-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6 +-#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7) +-#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7 ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7) ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7 ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8) ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8 ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9) ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9 ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10) ++#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10 ++#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11) ++#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11 + u8 rss_result_mask; + u8 leading_client_id; + #endif + u16 vlan_id[2]; ++}; ++ ++/* ++ * RSS idirection table update configuration ++ */ ++struct rss_update_config { ++#if defined(__BIG_ENDIAN) ++ u16 toe_rss_bitmap; ++ u16 flags; ++#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0) ++#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0 ++#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1) ++#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1 ++#define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2) ++#define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2 ++#elif defined(__LITTLE_ENDIAN) ++ u16 flags; ++#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0) ++#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0 ++#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1) ++#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1 ++#define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2) ++#define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2 ++ u16 toe_rss_bitmap; ++#endif ++ u32 reserved1; + }; + + /* +@@ -2415,6 +2654,7 @@ + struct eth_update_ramrod_data { + struct tstorm_eth_function_common_config func_config; + u8 indirectionTable[128]; ++ struct rss_update_config rss_config; + }; + + +@@ -2422,7 +2662,7 @@ + * MAC filtering configuration command header + */ + struct mac_configuration_hdr { +- u8 length_6b; ++ u8 length; + u8 offset; + u16 client_id; + u32 reserved1; +@@ -2432,10 +2672,10 @@ + * MAC address in list for ramrod + */ + struct tstorm_cam_entry { +- u16 lsb_mac_addr; +- u16 middle_mac_addr; +- u16 msb_mac_addr; +- u16 flags; ++ __le16 lsb_mac_addr; ++ __le16 middle_mac_addr; ++ __le16 msb_mac_addr; ++ __le16 flags; + #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0) + #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0 + #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1) +@@ -2459,8 +2699,9 @@ + #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3 + #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4) + #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4 +- u8 client_id; ++ u8 reserved1; + u16 vlan_id; ++ u32 clients_bit_vector; + }; + + /* +@@ -2484,12 +2725,12 @@ + * MAC address in list for ramrod + */ + struct mac_configuration_entry_e1h { +- u16 lsb_mac_addr; +- u16 middle_mac_addr; +- u16 msb_mac_addr; +- u16 vlan_id; +- u16 e1hov_id; +- u8 client_id; ++ __le16 lsb_mac_addr; ++ __le16 middle_mac_addr; ++ __le16 msb_mac_addr; ++ __le16 vlan_id; ++ __le16 e1hov_id; ++ u8 reserved0; + u8 flags; + #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0) + #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0 +@@ -2497,8 +2738,9 @@ + #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1 + #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2) + #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2 +-#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3) +-#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3 ++#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1 (0x1F<<3) ++#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1_SHIFT 3 ++ u32 clients_bit_vector; + }; + + /* +@@ -2523,13 +2765,13 @@ + */ + struct tstorm_eth_client_config { + #if defined(__BIG_ENDIAN) +- u8 max_sges_for_packet; ++ u8 reserved0; + u8 statistics_counter_id; + u16 mtu; + #elif defined(__LITTLE_ENDIAN) + u16 mtu; + u8 statistics_counter_id; +- u8 max_sges_for_packet; ++ u8 reserved0; + #endif + #if defined(__BIG_ENDIAN) + u16 drop_flags; +@@ -2541,27 +2783,27 @@ + #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2 + #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3) + #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3 +-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4) +-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4 ++#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4) ++#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4 + u16 config_flags; +-#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0) +-#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0 +-#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1) +-#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1 +-#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2) +-#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2 +-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3) +-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3 ++#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0) ++#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0 ++#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1) ++#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1 ++#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2) ++#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2 ++#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3) ++#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3 + #elif defined(__LITTLE_ENDIAN) + u16 config_flags; +-#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0) +-#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0 +-#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1) +-#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1 +-#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2) +-#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2 +-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3) +-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3 ++#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0) ++#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0 ++#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1) ++#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1 ++#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2) ++#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2 ++#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3) ++#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3 + u16 drop_flags; + #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0) + #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0 +@@ -2571,8 +2813,8 @@ + #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2 + #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3) + #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3 +-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4) +-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4 ++#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4) ++#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4 + #endif + }; + +@@ -2594,9 +2836,61 @@ + + + /* ++ * common flag to indicate existance of TPA. ++ */ ++struct tstorm_eth_tpa_exist { ++#if defined(__BIG_ENDIAN) ++ u16 reserved1; ++ u8 reserved0; ++ u8 tpa_exist; ++#elif defined(__LITTLE_ENDIAN) ++ u8 tpa_exist; ++ u8 reserved0; ++ u16 reserved1; ++#endif ++ u32 reserved2; ++}; ++ ++ ++/* ++ * rx rings pause data for E1h only ++ */ ++struct ustorm_eth_rx_pause_data_e1h { ++#if defined(__BIG_ENDIAN) ++ u16 bd_thr_low; ++ u16 cqe_thr_low; ++#elif defined(__LITTLE_ENDIAN) ++ u16 cqe_thr_low; ++ u16 bd_thr_low; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 cos; ++ u16 sge_thr_low; ++#elif defined(__LITTLE_ENDIAN) ++ u16 sge_thr_low; ++ u16 cos; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 bd_thr_high; ++ u16 cqe_thr_high; ++#elif defined(__LITTLE_ENDIAN) ++ u16 cqe_thr_high; ++ u16 bd_thr_high; ++#endif ++#if defined(__BIG_ENDIAN) ++ u16 reserved0; ++ u16 sge_thr_high; ++#elif defined(__LITTLE_ENDIAN) ++ u16 sge_thr_high; ++ u16 reserved0; ++#endif ++}; ++ ++ ++/* + * Three RX producers for ETH + */ +-struct tstorm_eth_rx_producers { ++struct ustorm_eth_rx_producers { + #if defined(__BIG_ENDIAN) + u16 bd_prod; + u16 cqe_prod; +@@ -2615,38 +2909,23 @@ + + + /* +- * common flag to indicate existence of TPA. +- */ +-struct tstorm_eth_tpa_exist { +-#if defined(__BIG_ENDIAN) +- u16 reserved1; +- u8 reserved0; +- u8 tpa_exist; +-#elif defined(__LITTLE_ENDIAN) +- u8 tpa_exist; +- u8 reserved0; +- u16 reserved1; +-#endif +- u32 reserved2; +-}; +- +- +-/* + * per-port SAFC demo variables + */ + struct cmng_flags_per_port { + u8 con_number[NUM_OF_PROTOCOLS]; +-#if defined(__BIG_ENDIAN) +- u8 fairness_enable; +- u8 rate_shaping_enable; +- u8 cmng_protocol_enable; +- u8 cmng_vn_enable; +-#elif defined(__LITTLE_ENDIAN) +- u8 cmng_vn_enable; +- u8 cmng_protocol_enable; +- u8 rate_shaping_enable; +- u8 fairness_enable; +-#endif ++ u32 cmng_enables; ++#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) ++#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 ++#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) ++#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 ++#define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2) ++#define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2 ++#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3) ++#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3 ++#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4) ++#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4 ++#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x7FFFFFF<<5) ++#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 5 + }; + + +@@ -2657,7 +2936,6 @@ + u32 rs_periodic_timeout; + u32 rs_threshold; + }; +- + + /* + * per-port fairness variables +@@ -2668,23 +2946,21 @@ + u32 fairness_timeout; + }; + +- + /* + * per-port SAFC variables + */ + struct safc_struct_per_port { + #if defined(__BIG_ENDIAN) +- u16 __reserved0; +- u8 cur_cos_types; ++ u16 __reserved1; ++ u8 __reserved0; + u8 safc_timeout_usec; + #elif defined(__LITTLE_ENDIAN) + u8 safc_timeout_usec; +- u8 cur_cos_types; +- u16 __reserved0; ++ u8 __reserved0; ++ u16 __reserved1; + #endif +- u8 cos_to_protocol[MAX_COS_NUMBER]; ++ u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; + }; +- + + /* + * Per-port congestion management variables +@@ -2698,22 +2974,33 @@ + + + /* ++ * Dynamic host coalescing init parameters ++ */ ++struct dynamic_hc_config { ++ u32 threshold[3]; ++ u8 shift_per_protocol[HC_USTORM_SB_NUM_INDICES]; ++ u8 hc_timeout0[HC_USTORM_SB_NUM_INDICES]; ++ u8 hc_timeout1[HC_USTORM_SB_NUM_INDICES]; ++ u8 hc_timeout2[HC_USTORM_SB_NUM_INDICES]; ++ u8 hc_timeout3[HC_USTORM_SB_NUM_INDICES]; ++}; ++ ++ ++/* + * Protocol-common statistics collected by the Xstorm (per client) + */ + struct xstorm_per_client_stats { +- struct regpair total_sent_bytes; +- u32 total_sent_pkts; +- u32 unicast_pkts_sent; ++ __le32 reserved0; ++ __le32 unicast_pkts_sent; + struct regpair unicast_bytes_sent; + struct regpair multicast_bytes_sent; +- u32 multicast_pkts_sent; +- u32 broadcast_pkts_sent; ++ __le32 multicast_pkts_sent; ++ __le32 broadcast_pkts_sent; + struct regpair broadcast_bytes_sent; +- u16 stats_counter; +- u16 reserved0; +- u32 reserved1; ++ __le16 stats_counter; ++ __le16 reserved1; ++ __le32 reserved2; + }; +- + + /* + * Common statistics collected by the Xstorm (per port) +@@ -2722,38 +3009,33 @@ + struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID]; + }; + +- + /* + * Protocol-common statistics collected by the Tstorm (per port) + */ + struct tstorm_per_port_stats { +- u32 mac_filter_discard; +- u32 xxoverflow_discard; +- u32 brb_truncate_discard; +- u32 mac_discard; ++ __le32 mac_filter_discard; ++ __le32 xxoverflow_discard; ++ __le32 brb_truncate_discard; ++ __le32 mac_discard; + }; +- + + /* + * Protocol-common statistics collected by the Tstorm (per client) + */ + struct tstorm_per_client_stats { +- struct regpair total_rcv_bytes; + struct regpair rcv_unicast_bytes; + struct regpair rcv_broadcast_bytes; + struct regpair rcv_multicast_bytes; + struct regpair rcv_error_bytes; +- u32 checksum_discard; +- u32 packets_too_big_discard; +- u32 total_rcv_pkts; +- u32 rcv_unicast_pkts; +- u32 rcv_broadcast_pkts; +- u32 rcv_multicast_pkts; +- u32 no_buff_discard; +- u32 ttl0_discard; +- u16 stats_counter; +- u16 reserved0; +- u32 reserved1; ++ __le32 checksum_discard; ++ __le32 packets_too_big_discard; ++ __le32 rcv_unicast_pkts; ++ __le32 rcv_broadcast_pkts; ++ __le32 rcv_multicast_pkts; ++ __le32 no_buff_discard; ++ __le32 ttl0_discard; ++ __le16 stats_counter; ++ __le16 reserved0; + }; + + /* +@@ -2765,11 +3047,33 @@ + }; + + /* ++ * Protocol-common statistics collected by the Ustorm (per client) ++ */ ++struct ustorm_per_client_stats { ++ struct regpair ucast_no_buff_bytes; ++ struct regpair mcast_no_buff_bytes; ++ struct regpair bcast_no_buff_bytes; ++ __le32 ucast_no_buff_pkts; ++ __le32 mcast_no_buff_pkts; ++ __le32 bcast_no_buff_pkts; ++ __le16 stats_counter; ++ __le16 reserved0; ++}; ++ ++/* ++ * Protocol-common statistics collected by the Ustorm ++ */ ++struct ustorm_common_stats { ++ struct ustorm_per_client_stats client_statistics[MAX_U_STAT_COUNTER_ID]; ++}; ++ ++/* + * Eth statistics query structure for the eth_stats_query ramrod + */ + struct eth_stats_query { + struct xstorm_common_stats xstorm_common; + struct tstorm_common_stats tstorm_common; ++ struct ustorm_common_stats ustorm_common; + }; + + +@@ -2777,6 +3081,7 @@ + * per-vnic fairness variables + */ + struct fairness_vars_per_vn { ++ u32 cos_credit_delta[MAX_COS_NUMBER]; + u32 protocol_credit_delta[NUM_OF_PROTOCOLS]; + u32 vn_credit_delta; + u32 __reserved0; +@@ -2788,13 +3093,15 @@ + */ + struct fw_version { + #if defined(__BIG_ENDIAN) +- u16 patch; +- u8 primary; +- u8 client; ++ u8 engineering; ++ u8 revision; ++ u8 minor; ++ u8 major; + #elif defined(__LITTLE_ENDIAN) +- u8 client; +- u8 primary; +- u16 patch; ++ u8 major; ++ u8 minor; ++ u8 revision; ++ u8 engineering; + #endif + u32 flags; + #define FW_VERSION_OPTIMIZED (0x1<<0) +@@ -2812,9 +3119,10 @@ + * FW version stored in first line of pram + */ + struct pram_fw_version { +- u8 client; +- u8 primary; +- u16 patch; ++ u8 major; ++ u8 minor; ++ u8 revision; ++ u8 engineering; + u8 flags; + #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) + #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 +@@ -2826,6 +3134,15 @@ + #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 + #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) + #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 ++}; ++ ++ ++/* ++ * The send queue element ++ */ ++struct protocol_common_spe { ++ struct spe_hdr hdr; ++ struct regpair phy_address; + }; + + +diff -r e67cb9a8e847 drivers/net/bnx2x_init.h +--- a/drivers/net/bnx2x_init.h Wed Aug 05 10:50:39 2009 +0100 ++++ b/drivers/net/bnx2x_init.h Wed Aug 05 10:51:02 2009 +0100 +@@ -1,6 +1,7 @@ + /* bnx2x_init.h: Broadcom Everest network driver. ++ * Structures and macroes needed during the initialization. + * +- * Copyright (c) 2007-2008 Broadcom Corporation ++ * Copyright (c) 2007-2009 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -8,26 +9,17 @@ + * + * Maintained by: Eilon Greenstein + * Written by: Eliezer Tamir ++ * Modified by: Vladislav Zolotarov + */ + + #ifndef BNX2X_INIT_H + #define BNX2X_INIT_H + +-#define COMMON 0x1 +-#define PORT0 0x2 +-#define PORT1 0x4 +- +-#define INIT_EMULATION 0x1 +-#define INIT_FPGA 0x2 +-#define INIT_ASIC 0x4 +-#define INIT_HARDWARE 0x7 +- +-#define STORM_INTMEM_SIZE_E1 (0x5800 / 4) +-#define STORM_INTMEM_SIZE_E1H (0x10000 / 4) +-#define TSTORM_INTMEM_ADDR 0x1a0000 +-#define CSTORM_INTMEM_ADDR 0x220000 +-#define XSTORM_INTMEM_ADDR 0x2a0000 +-#define USTORM_INTMEM_ADDR 0x320000 ++/* RAM0 size in bytes */ ++#define STORM_INTMEM_SIZE_E1 0x5800 ++#define STORM_INTMEM_SIZE_E1H 0x10000 ++#define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1(bp) ? STORM_INTMEM_SIZE_E1 : \ ++ STORM_INTMEM_SIZE_E1H) / 4) + + + /* Init operation types and structures */ +@@ -42,33 +34,74 @@ + #define OP_WR_64 0x8 /* write 64 bit pattern */ + #define OP_WB 0x9 /* copy a string using DMAE */ + +-/* Operation specific for E1 */ +-#define OP_RD_E1 0xa /* read single register */ +-#define OP_WR_E1 0xb /* write single register */ +-#define OP_IW_E1 0xc /* write single register using mailbox */ +-#define OP_SW_E1 0xd /* copy a string to the device */ +-#define OP_SI_E1 0xe /* copy a string using mailbox */ +-#define OP_ZR_E1 0xf /* clear memory */ +-#define OP_ZP_E1 0x10 /* unzip then copy with DMAE */ +-#define OP_WR_64_E1 0x11 /* write 64 bit pattern on E1 */ +-#define OP_WB_E1 0x12 /* copy a string using DMAE */ ++/* FPGA and EMUL specific operations */ ++#define OP_WR_EMUL 0xa /* write single register on Emulation */ ++#define OP_WR_FPGA 0xb /* write single register on FPGA */ ++#define OP_WR_ASIC 0xc /* write single register on ASIC */ + +-/* Operation specific for E1H */ +-#define OP_RD_E1H 0x13 /* read single register */ +-#define OP_WR_E1H 0x14 /* write single register */ +-#define OP_IW_E1H 0x15 /* write single register using mailbox */ +-#define OP_SW_E1H 0x16 /* copy a string to the device */ +-#define OP_SI_E1H 0x17 /* copy a string using mailbox */ +-#define OP_ZR_E1H 0x18 /* clear memory */ +-#define OP_ZP_E1H 0x19 /* unzip then copy with DMAE */ +-#define OP_WR_64_E1H 0x1a /* write 64 bit pattern on E1H */ +-#define OP_WB_E1H 0x1b /* copy a string using DMAE */ ++/* Init stages */ ++/* Never reorder stages !!! */ ++#define COMMON_STAGE 0 ++#define PORT0_STAGE 1 ++#define PORT1_STAGE 2 ++#define FUNC0_STAGE 3 ++#define FUNC1_STAGE 4 ++#define FUNC2_STAGE 5 ++#define FUNC3_STAGE 6 ++#define FUNC4_STAGE 7 ++#define FUNC5_STAGE 8 ++#define FUNC6_STAGE 9 ++#define FUNC7_STAGE 10 ++#define STAGE_IDX_MAX 11 + +-/* FPGA and EMUL specific operations */ +-#define OP_WR_EMUL_E1H 0x1c /* write single register on E1H Emul */ +-#define OP_WR_EMUL 0x1d /* write single register on Emulation */ +-#define OP_WR_FPGA 0x1e /* write single register on FPGA */ +-#define OP_WR_ASIC 0x1f /* write single register on ASIC */ ++#define STAGE_START 0 ++#define STAGE_END 1 ++ ++ ++/* Indices of blocks */ ++#define PRS_BLOCK 0 ++#define SRCH_BLOCK 1 ++#define TSDM_BLOCK 2 ++#define TCM_BLOCK 3 ++#define BRB1_BLOCK 4 ++#define TSEM_BLOCK 5 ++#define PXPCS_BLOCK 6 ++#define EMAC0_BLOCK 7 ++#define EMAC1_BLOCK 8 ++#define DBU_BLOCK 9 ++#define MISC_BLOCK 10 ++#define DBG_BLOCK 11 ++#define NIG_BLOCK 12 ++#define MCP_BLOCK 13 ++#define UPB_BLOCK 14 ++#define CSDM_BLOCK 15 ++#define USDM_BLOCK 16 ++#define CCM_BLOCK 17 ++#define UCM_BLOCK 18 ++#define USEM_BLOCK 19 ++#define CSEM_BLOCK 20 ++#define XPB_BLOCK 21 ++#define DQ_BLOCK 22 ++#define TIMERS_BLOCK 23 ++#define XSDM_BLOCK 24 ++#define QM_BLOCK 25 ++#define PBF_BLOCK 26 ++#define XCM_BLOCK 27 ++#define XSEM_BLOCK 28 ++#define CDU_BLOCK 29 ++#define DMAE_BLOCK 30 ++#define PXP_BLOCK 31 ++#define CFC_BLOCK 32 ++#define HC_BLOCK 33 ++#define PXP2_BLOCK 34 ++#define MISC_AEU_BLOCK 35 ++#define PGLUE_B_BLOCK 36 ++#define IGU_BLOCK 37 ++ ++ ++/* Returns the index of start or end of a specific block stage in ops array*/ ++#define BLOCK_OPS_IDX(block, stage, end) \ ++ (2*(((block)*STAGE_IDX_MAX) + (stage)) + (end)) + + + struct raw_op { +@@ -115,694 +148,5 @@ + struct raw_op raw; + }; + +-#include "bnx2x_init_values.h" +- +-static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val); +-static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len); +- +-static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data, +- u32 len) +-{ +- int i; +- +- for (i = 0; i < len; i++) { +- REG_WR(bp, addr + i*4, data[i]); +- if (!(i % 10000)) { +- touch_softlockup_watchdog(); +- cpu_relax(); +- } +- } +-} +- +-static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data, +- u16 len) +-{ +- int i; +- +- for (i = 0; i < len; i++) { +- REG_WR_IND(bp, addr + i*4, data[i]); +- if (!(i % 10000)) { +- touch_softlockup_watchdog(); +- cpu_relax(); +- } +- } +-} +- +-static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len) +-{ +- int offset = 0; +- +- if (bp->dmae_ready) { +- while (len > DMAE_LEN32_WR_MAX) { +- bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, +- addr + offset, DMAE_LEN32_WR_MAX); +- offset += DMAE_LEN32_WR_MAX * 4; +- len -= DMAE_LEN32_WR_MAX; +- } +- bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, +- addr + offset, len); +- } else +- bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len); +-} +- +-static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) +-{ +- if ((len * 4) > FW_BUF_SIZE) { +- BNX2X_ERR("LARGE DMAE OPERATION ! addr 0x%x len 0x%x\n", +- addr, len*4); +- return; +- } +- memset(bp->gunzip_buf, fill, len * 4); +- +- bnx2x_write_big_buf(bp, addr, len); +-} +- +-static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data, +- u32 len64) +-{ +- u32 buf_len32 = FW_BUF_SIZE/4; +- u32 len = len64*2; +- u64 data64 = 0; +- int i; +- +- /* 64 bit value is in a blob: first low DWORD, then high DWORD */ +- data64 = HILO_U64((*(data + 1)), (*data)); +- len64 = min((u32)(FW_BUF_SIZE/8), len64); +- for (i = 0; i < len64; i++) { +- u64 *pdata = ((u64 *)(bp->gunzip_buf)) + i; +- +- *pdata = data64; +- } +- +- for (i = 0; i < len; i += buf_len32) { +- u32 cur_len = min(buf_len32, len - i); +- +- bnx2x_write_big_buf(bp, addr + i * 4, cur_len); +- } +-} +- +-/********************************************************* +- There are different blobs for each PRAM section. +- In addition, each blob write operation is divided into a few operations +- in order to decrease the amount of phys. contiguous buffer needed. +- Thus, when we select a blob the address may be with some offset +- from the beginning of PRAM section. +- The same holds for the INT_TABLE sections. +-**********************************************************/ +-#define IF_IS_INT_TABLE_ADDR(base, addr) \ +- if (((base) <= (addr)) && ((base) + 0x400 >= (addr))) +- +-#define IF_IS_PRAM_ADDR(base, addr) \ +- if (((base) <= (addr)) && ((base) + 0x40000 >= (addr))) +- +-static const u32 *bnx2x_sel_blob(u32 addr, const u32 *data, int is_e1) +-{ +- IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr) +- data = is_e1 ? tsem_int_table_data_e1 : +- tsem_int_table_data_e1h; +- else +- IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr) +- data = is_e1 ? csem_int_table_data_e1 : +- csem_int_table_data_e1h; +- else +- IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr) +- data = is_e1 ? usem_int_table_data_e1 : +- usem_int_table_data_e1h; +- else +- IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr) +- data = is_e1 ? xsem_int_table_data_e1 : +- xsem_int_table_data_e1h; +- else +- IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr) +- data = is_e1 ? tsem_pram_data_e1 : tsem_pram_data_e1h; +- else +- IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr) +- data = is_e1 ? csem_pram_data_e1 : csem_pram_data_e1h; +- else +- IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr) +- data = is_e1 ? usem_pram_data_e1 : usem_pram_data_e1h; +- else +- IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr) +- data = is_e1 ? xsem_pram_data_e1 : xsem_pram_data_e1h; +- +- return data; +-} +- +-static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data, +- u32 len, int gunzip, int is_e1, u32 blob_off) +-{ +- int offset = 0; +- +- data = bnx2x_sel_blob(addr, data, is_e1) + blob_off; +- +- if (gunzip) { +- int rc; +-#ifdef __BIG_ENDIAN +- int i, size; +- u32 *temp; +- +- temp = kmalloc(len, GFP_KERNEL); +- size = (len / 4) + ((len % 4) ? 1 : 0); +- for (i = 0; i < size; i++) +- temp[i] = swab32(data[i]); +- data = temp; +-#endif +- rc = bnx2x_gunzip(bp, (u8 *)data, len); +- if (rc) { +- BNX2X_ERR("gunzip failed ! rc %d\n", rc); +- return; +- } +- len = bp->gunzip_outlen; +-#ifdef __BIG_ENDIAN +- kfree(temp); +- for (i = 0; i < len; i++) +- ((u32 *)bp->gunzip_buf)[i] = +- swab32(((u32 *)bp->gunzip_buf)[i]); +-#endif +- } else { +- if ((len * 4) > FW_BUF_SIZE) { +- BNX2X_ERR("LARGE DMAE OPERATION ! " +- "addr 0x%x len 0x%x\n", addr, len*4); +- return; +- } +- memcpy(bp->gunzip_buf, data, len * 4); +- } +- +- if (bp->dmae_ready) { +- while (len > DMAE_LEN32_WR_MAX) { +- bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, +- addr + offset, DMAE_LEN32_WR_MAX); +- offset += DMAE_LEN32_WR_MAX * 4; +- len -= DMAE_LEN32_WR_MAX; +- } +- bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, +- addr + offset, len); +- } else +- bnx2x_init_ind_wr(bp, addr, bp->gunzip_buf, len); +-} +- +-static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end) +-{ +- int is_e1 = CHIP_IS_E1(bp); +- int is_e1h = CHIP_IS_E1H(bp); +- int is_emul_e1h = (CHIP_REV_IS_EMUL(bp) && is_e1h); +- int hw_wr, i; +- union init_op *op; +- u32 op_type, addr, len; +- const u32 *data, *data_base; +- +- if (CHIP_REV_IS_FPGA(bp)) +- hw_wr = OP_WR_FPGA; +- else if (CHIP_REV_IS_EMUL(bp)) +- hw_wr = OP_WR_EMUL; +- else +- hw_wr = OP_WR_ASIC; +- +- if (is_e1) +- data_base = init_data_e1; +- else /* CHIP_IS_E1H(bp) */ +- data_base = init_data_e1h; +- +- for (i = op_start; i < op_end; i++) { +- +- op = (union init_op *)&(init_ops[i]); +- +- op_type = op->str_wr.op; +- addr = op->str_wr.offset; +- len = op->str_wr.data_len; +- data = data_base + op->str_wr.data_off; +- +- /* careful! it must be in order */ +- if (unlikely(op_type > OP_WB)) { +- +- /* If E1 only */ +- if (op_type <= OP_WB_E1) { +- if (is_e1) +- op_type -= (OP_RD_E1 - OP_RD); +- +- /* If E1H only */ +- } else if (op_type <= OP_WB_E1H) { +- if (is_e1h) +- op_type -= (OP_RD_E1H - OP_RD); +- } +- +- /* HW/EMUL specific */ +- if (op_type == hw_wr) +- op_type = OP_WR; +- +- /* EMUL on E1H is special */ +- if ((op_type == OP_WR_EMUL_E1H) && is_emul_e1h) +- op_type = OP_WR; +- } +- +- switch (op_type) { +- case OP_RD: +- REG_RD(bp, addr); +- break; +- case OP_WR: +- REG_WR(bp, addr, op->write.val); +- break; +- case OP_SW: +- bnx2x_init_str_wr(bp, addr, data, len); +- break; +- case OP_WB: +- bnx2x_init_wr_wb(bp, addr, data, len, 0, is_e1, 0); +- break; +- case OP_SI: +- bnx2x_init_ind_wr(bp, addr, data, len); +- break; +- case OP_ZR: +- bnx2x_init_fill(bp, addr, 0, op->zero.len); +- break; +- case OP_ZP: +- bnx2x_init_wr_wb(bp, addr, data, len, 1, is_e1, +- op->str_wr.data_off); +- break; +- case OP_WR_64: +- bnx2x_init_wr_64(bp, addr, data, len); +- break; +- default: +- /* happens whenever an op is of a diff HW */ +-#if 0 +- DP(NETIF_MSG_HW, "skipping init operation " +- "index %d[%d:%d]: type %d addr 0x%x " +- "len %d(0x%x)\n", +- i, op_start, op_end, op_type, addr, len, len); +-#endif +- break; +- } +- } +-} +- +- +-/**************************************************************************** +-* PXP +-****************************************************************************/ +-/* +- * This code configures the PCI read/write arbiter +- * which implements a weighted round robin +- * between the virtual queues in the chip. +- * +- * The values were derived for each PCI max payload and max request size. +- * since max payload and max request size are only known at run time, +- * this is done as a separate init stage. +- */ +- +-#define NUM_WR_Q 13 +-#define NUM_RD_Q 29 +-#define MAX_RD_ORD 3 +-#define MAX_WR_ORD 2 +- +-/* configuration for one arbiter queue */ +-struct arb_line { +- int l; +- int add; +- int ubound; +-}; +- +-/* derived configuration for each read queue for each max request size */ +-static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = { +- {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} }, +- {{4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4} }, +- {{4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {16 , 3 , 11}, {16 , 3 , 11} }, +- {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, +- {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81}, {64 , 64 , 120} } +-}; +- +-/* derived configuration for each write queue for each max request size */ +-static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = { +- {{4 , 6 , 3}, {4 , 6 , 3}, {4 , 6 , 3} }, +- {{4 , 2 , 3}, {4 , 2 , 3}, {4 , 2 , 3} }, +- {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} }, +- {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} }, +- {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} }, +- {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} }, +- {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25} }, +- {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} }, +- {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} }, +- {{8 , 9 , 6}, {16 , 9 , 11}, {32 , 9 , 21} }, +- {{8 , 47 , 19}, {16 , 47 , 19}, {32 , 47 , 21} }, +- {{8 , 9 , 6}, {16 , 9 , 11}, {16 , 9 , 11} }, +- {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} } +-}; +- +-/* register addresses for read queues */ +-static const struct arb_line read_arb_addr[NUM_RD_Q-1] = { +- {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0, +- PXP2_REG_RQ_BW_RD_UBOUND0}, +- {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, +- PXP2_REG_PSWRQ_BW_UB1}, +- {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, +- PXP2_REG_PSWRQ_BW_UB2}, +- {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, +- PXP2_REG_PSWRQ_BW_UB3}, +- {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4, +- PXP2_REG_RQ_BW_RD_UBOUND4}, +- {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5, +- PXP2_REG_RQ_BW_RD_UBOUND5}, +- {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, +- PXP2_REG_PSWRQ_BW_UB6}, +- {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, +- PXP2_REG_PSWRQ_BW_UB7}, +- {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, +- PXP2_REG_PSWRQ_BW_UB8}, +- {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, +- PXP2_REG_PSWRQ_BW_UB9}, +- {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, +- PXP2_REG_PSWRQ_BW_UB10}, +- {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, +- PXP2_REG_PSWRQ_BW_UB11}, +- {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12, +- PXP2_REG_RQ_BW_RD_UBOUND12}, +- {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13, +- PXP2_REG_RQ_BW_RD_UBOUND13}, +- {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14, +- PXP2_REG_RQ_BW_RD_UBOUND14}, +- {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15, +- PXP2_REG_RQ_BW_RD_UBOUND15}, +- {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16, +- PXP2_REG_RQ_BW_RD_UBOUND16}, +- {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17, +- PXP2_REG_RQ_BW_RD_UBOUND17}, +- {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18, +- PXP2_REG_RQ_BW_RD_UBOUND18}, +- {PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19, +- PXP2_REG_RQ_BW_RD_UBOUND19}, +- {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20, +- PXP2_REG_RQ_BW_RD_UBOUND20}, +- {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22, +- PXP2_REG_RQ_BW_RD_UBOUND22}, +- {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23, +- PXP2_REG_RQ_BW_RD_UBOUND23}, +- {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24, +- PXP2_REG_RQ_BW_RD_UBOUND24}, +- {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25, +- PXP2_REG_RQ_BW_RD_UBOUND25}, +- {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26, +- PXP2_REG_RQ_BW_RD_UBOUND26}, +- {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27, +- PXP2_REG_RQ_BW_RD_UBOUND27}, +- {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, +- PXP2_REG_PSWRQ_BW_UB28} +-}; +- +-/* register addresses for write queues */ +-static const struct arb_line write_arb_addr[NUM_WR_Q-1] = { +- {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, +- PXP2_REG_PSWRQ_BW_UB1}, +- {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, +- PXP2_REG_PSWRQ_BW_UB2}, +- {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, +- PXP2_REG_PSWRQ_BW_UB3}, +- {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, +- PXP2_REG_PSWRQ_BW_UB6}, +- {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, +- PXP2_REG_PSWRQ_BW_UB7}, +- {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, +- PXP2_REG_PSWRQ_BW_UB8}, +- {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, +- PXP2_REG_PSWRQ_BW_UB9}, +- {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, +- PXP2_REG_PSWRQ_BW_UB10}, +- {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, +- PXP2_REG_PSWRQ_BW_UB11}, +- {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, +- PXP2_REG_PSWRQ_BW_UB28}, +- {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29, +- PXP2_REG_RQ_BW_WR_UBOUND29}, +- {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30, +- PXP2_REG_RQ_BW_WR_UBOUND30} +-}; +- +-static void bnx2x_init_pxp(struct bnx2x *bp) +-{ +- u16 devctl; +- int r_order, w_order; +- u32 val, i; +- +- pci_read_config_word(bp->pdev, +- bp->pcie_cap + PCI_EXP_DEVCTL, &devctl); +- DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); +- w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); +- r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); +- +- if (r_order > MAX_RD_ORD) { +- DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n", +- r_order, MAX_RD_ORD); +- r_order = MAX_RD_ORD; +- } +- if (w_order > MAX_WR_ORD) { +- DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n", +- w_order, MAX_WR_ORD); +- w_order = MAX_WR_ORD; +- } +- if (CHIP_REV_IS_FPGA(bp)) { +- DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n"); +- w_order = 0; +- } +- DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order); +- +- for (i = 0; i < NUM_RD_Q-1; i++) { +- REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l); +- REG_WR(bp, read_arb_addr[i].add, +- read_arb_data[i][r_order].add); +- REG_WR(bp, read_arb_addr[i].ubound, +- read_arb_data[i][r_order].ubound); +- } +- +- for (i = 0; i < NUM_WR_Q-1; i++) { +- if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) || +- (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) { +- +- REG_WR(bp, write_arb_addr[i].l, +- write_arb_data[i][w_order].l); +- +- REG_WR(bp, write_arb_addr[i].add, +- write_arb_data[i][w_order].add); +- +- REG_WR(bp, write_arb_addr[i].ubound, +- write_arb_data[i][w_order].ubound); +- } else { +- +- val = REG_RD(bp, write_arb_addr[i].l); +- REG_WR(bp, write_arb_addr[i].l, +- val | (write_arb_data[i][w_order].l << 10)); +- +- val = REG_RD(bp, write_arb_addr[i].add); +- REG_WR(bp, write_arb_addr[i].add, +- val | (write_arb_data[i][w_order].add << 10)); +- +- val = REG_RD(bp, write_arb_addr[i].ubound); +- REG_WR(bp, write_arb_addr[i].ubound, +- val | (write_arb_data[i][w_order].ubound << 7)); +- } +- } +- +- val = write_arb_data[NUM_WR_Q-1][w_order].add; +- val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10; +- val += write_arb_data[NUM_WR_Q-1][w_order].l << 17; +- REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val); +- +- val = read_arb_data[NUM_RD_Q-1][r_order].add; +- val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10; +- val += read_arb_data[NUM_RD_Q-1][r_order].l << 17; +- REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val); +- +- REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order); +- REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order); +- REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order); +- REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order); +- +- if (r_order == MAX_RD_ORD) +- REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00); +- +- REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); +- +- if (CHIP_IS_E1H(bp)) { +- REG_WR(bp, PXP2_REG_WR_HC_MPS, w_order+1); +- REG_WR(bp, PXP2_REG_WR_USDM_MPS, w_order+1); +- REG_WR(bp, PXP2_REG_WR_CSDM_MPS, w_order+1); +- REG_WR(bp, PXP2_REG_WR_TSDM_MPS, w_order+1); +- REG_WR(bp, PXP2_REG_WR_XSDM_MPS, w_order+1); +- REG_WR(bp, PXP2_REG_WR_QM_MPS, w_order+1); +- REG_WR(bp, PXP2_REG_WR_TM_MPS, w_order+1); +- REG_WR(bp, PXP2_REG_WR_SRC_MPS, w_order+1); +- REG_WR(bp, PXP2_REG_WR_DBG_MPS, w_order+1); +- REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */ +- REG_WR(bp, PXP2_REG_WR_CDU_MPS, w_order+1); +- } +-} +- +- +-/**************************************************************************** +-* CDU +-****************************************************************************/ +- +-#define CDU_REGION_NUMBER_XCM_AG 2 +-#define CDU_REGION_NUMBER_UCM_AG 4 +- +-/** +- * String-to-compress [31:8] = CID (all 24 bits) +- * String-to-compress [7:4] = Region +- * String-to-compress [3:0] = Type +- */ +-#define CDU_VALID_DATA(_cid, _region, _type) \ +- (((_cid) << 8) | (((_region) & 0xf) << 4) | (((_type) & 0xf))) +-#define CDU_CRC8(_cid, _region, _type) \ +- calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff) +-#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \ +- (0x80 | (CDU_CRC8(_cid, _region, _type) & 0x7f)) +-#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \ +- (0x80 | ((_type) & 0xf << 3) | (CDU_CRC8(_cid, _region, _type) & 0x7)) +-#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) +- +-/***************************************************************************** +- * Description: +- * Calculates crc 8 on a word value: polynomial 0-1-2-8 +- * Code was translated from Verilog. +- ****************************************************************************/ +-static u8 calc_crc8(u32 data, u8 crc) +-{ +- u8 D[32]; +- u8 NewCRC[8]; +- u8 C[8]; +- u8 crc_res; +- u8 i; +- +- /* split the data into 31 bits */ +- for (i = 0; i < 32; i++) { +- D[i] = data & 1; +- data = data >> 1; +- } +- +- /* split the crc into 8 bits */ +- for (i = 0; i < 8; i++) { +- C[i] = crc & 1; +- crc = crc >> 1; +- } +- +- NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ +- D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ +- C[6] ^ C[7]; +- NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^ +- D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ +- D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6]; +- NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^ +- D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ +- C[0] ^ C[1] ^ C[4] ^ C[5]; +- NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ +- D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ +- C[1] ^ C[2] ^ C[5] ^ C[6]; +- NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^ +- D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ +- C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; +- NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^ +- D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ +- C[3] ^ C[4] ^ C[7]; +- NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^ +- D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ +- C[5]; +- NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^ +- D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ +- C[6]; +- +- crc_res = 0; +- for (i = 0; i < 8; i++) +- crc_res |= (NewCRC[i] << i); +- +- return crc_res; +-} +- +-/* registers addresses are not in order +- so these arrays help simplify the code */ +-static const int cm_start[E1H_FUNC_MAX][9] = { +- {MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START, +- XCM_FUNC0_START, TSEM_FUNC0_START, USEM_FUNC0_START, CSEM_FUNC0_START, +- XSEM_FUNC0_START}, +- {MISC_FUNC1_START, TCM_FUNC1_START, UCM_FUNC1_START, CCM_FUNC1_START, +- XCM_FUNC1_START, TSEM_FUNC1_START, USEM_FUNC1_START, CSEM_FUNC1_START, +- XSEM_FUNC1_START}, +- {MISC_FUNC2_START, TCM_FUNC2_START, UCM_FUNC2_START, CCM_FUNC2_START, +- XCM_FUNC2_START, TSEM_FUNC2_START, USEM_FUNC2_START, CSEM_FUNC2_START, +- XSEM_FUNC2_START}, +- {MISC_FUNC3_START, TCM_FUNC3_START, UCM_FUNC3_START, CCM_FUNC3_START, +- XCM_FUNC3_START, TSEM_FUNC3_START, USEM_FUNC3_START, CSEM_FUNC3_START, +- XSEM_FUNC3_START}, +- {MISC_FUNC4_START, TCM_FUNC4_START, UCM_FUNC4_START, CCM_FUNC4_START, +- XCM_FUNC4_START, TSEM_FUNC4_START, USEM_FUNC4_START, CSEM_FUNC4_START, +- XSEM_FUNC4_START}, +- {MISC_FUNC5_START, TCM_FUNC5_START, UCM_FUNC5_START, CCM_FUNC5_START, +- XCM_FUNC5_START, TSEM_FUNC5_START, USEM_FUNC5_START, CSEM_FUNC5_START, +- XSEM_FUNC5_START}, +- {MISC_FUNC6_START, TCM_FUNC6_START, UCM_FUNC6_START, CCM_FUNC6_START, +- XCM_FUNC6_START, TSEM_FUNC6_START, USEM_FUNC6_START, CSEM_FUNC6_START, +- XSEM_FUNC6_START}, +- {MISC_FUNC7_START, TCM_FUNC7_START, UCM_FUNC7_START, CCM_FUNC7_START, +- XCM_FUNC7_START, TSEM_FUNC7_START, USEM_FUNC7_START, CSEM_FUNC7_START, +- XSEM_FUNC7_START} +-}; +- +-static const int cm_end[E1H_FUNC_MAX][9] = { +- {MISC_FUNC0_END, TCM_FUNC0_END, UCM_FUNC0_END, CCM_FUNC0_END, +- XCM_FUNC0_END, TSEM_FUNC0_END, USEM_FUNC0_END, CSEM_FUNC0_END, +- XSEM_FUNC0_END}, +- {MISC_FUNC1_END, TCM_FUNC1_END, UCM_FUNC1_END, CCM_FUNC1_END, +- XCM_FUNC1_END, TSEM_FUNC1_END, USEM_FUNC1_END, CSEM_FUNC1_END, +- XSEM_FUNC1_END}, +- {MISC_FUNC2_END, TCM_FUNC2_END, UCM_FUNC2_END, CCM_FUNC2_END, +- XCM_FUNC2_END, TSEM_FUNC2_END, USEM_FUNC2_END, CSEM_FUNC2_END, +- XSEM_FUNC2_END}, +- {MISC_FUNC3_END, TCM_FUNC3_END, UCM_FUNC3_END, CCM_FUNC3_END, +- XCM_FUNC3_END, TSEM_FUNC3_END, USEM_FUNC3_END, CSEM_FUNC3_END, +- XSEM_FUNC3_END}, +- {MISC_FUNC4_END, TCM_FUNC4_END, UCM_FUNC4_END, CCM_FUNC4_END, +- XCM_FUNC4_END, TSEM_FUNC4_END, USEM_FUNC4_END, CSEM_FUNC4_END, +- XSEM_FUNC4_END}, +- {MISC_FUNC5_END, TCM_FUNC5_END, UCM_FUNC5_END, CCM_FUNC5_END, +- XCM_FUNC5_END, TSEM_FUNC5_END, USEM_FUNC5_END, CSEM_FUNC5_END, +- XSEM_FUNC5_END}, +- {MISC_FUNC6_END, TCM_FUNC6_END, UCM_FUNC6_END, CCM_FUNC6_END, +- XCM_FUNC6_END, TSEM_FUNC6_END, USEM_FUNC6_END, CSEM_FUNC6_END, +- XSEM_FUNC6_END}, +- {MISC_FUNC7_END, TCM_FUNC7_END, UCM_FUNC7_END, CCM_FUNC7_END, +- XCM_FUNC7_END, TSEM_FUNC7_END, USEM_FUNC7_END, CSEM_FUNC7_END, +- XSEM_FUNC7_END}, +-}; +- +-static const int hc_limits[E1H_FUNC_MAX][2] = { +- {HC_FUNC0_START, HC_FUNC0_END}, +- {HC_FUNC1_START, HC_FUNC1_END}, +- {HC_FUNC2_START, HC_FUNC2_END}, +- {HC_FUNC3_START, HC_FUNC3_END}, +- {HC_FUNC4_START, HC_FUNC4_END}, +- {HC_FUNC5_START, HC_FUNC5_END}, +- {HC_FUNC6_START, HC_FUNC6_END}, +- {HC_FUNC7_START, HC_FUNC7_END} +-}; +- + #endif /* BNX2X_INIT_H */ + +diff -r e67cb9a8e847 drivers/net/bnx2x_init_ops.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/bnx2x_init_ops.h Wed Aug 05 10:51:02 2009 +0100 +@@ -0,0 +1,501 @@ ++/* bnx2x_init_ops.h: Broadcom Everest network driver. ++ * Static functions needed during the initialization. ++ * This file is "included" in bnx2x_main.c. ++ * ++ * Copyright (c) 2007-2009 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ * ++ * Maintained by: Eilon Greenstein ++ * Written by: Vladislav Zolotarov ++ */ ++ ++#ifndef BNX2X_INIT_OPS_H ++#define BNX2X_INIT_OPS_H ++ ++static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len); ++ ++ ++static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data, ++ u32 len) ++{ ++ u32 i; ++ ++ for (i = 0; i < len; i++) ++ REG_WR(bp, addr + i*4, data[i]); ++} ++ ++static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data, ++ u32 len) ++{ ++ u32 i; ++ ++ for (i = 0; i < len; i++) ++ REG_WR_IND(bp, addr + i*4, data[i]); ++} ++ ++static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len) ++{ ++ if (bp->dmae_ready) ++ bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len); ++ else ++ bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len); ++} ++ ++static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) ++{ ++ u32 buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4)); ++ u32 buf_len32 = buf_len/4; ++ u32 i; ++ ++ memset(GUNZIP_BUF(bp), (u8)fill, buf_len); ++ ++ for (i = 0; i < len; i += buf_len32) { ++ u32 cur_len = min(buf_len32, len - i); ++ ++ bnx2x_write_big_buf(bp, addr + i*4, cur_len); ++ } ++} ++ ++static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data, ++ u32 len64) ++{ ++ u32 buf_len32 = FW_BUF_SIZE/4; ++ u32 len = len64*2; ++ u64 data64 = 0; ++ u32 i; ++ ++ /* 64 bit value is in a blob: first low DWORD, then high DWORD */ ++ data64 = HILO_U64((*(data + 1)), (*data)); ++ ++ len64 = min((u32)(FW_BUF_SIZE/8), len64); ++ for (i = 0; i < len64; i++) { ++ u64 *pdata = ((u64 *)(GUNZIP_BUF(bp))) + i; ++ ++ *pdata = data64; ++ } ++ ++ for (i = 0; i < len; i += buf_len32) { ++ u32 cur_len = min(buf_len32, len - i); ++ ++ bnx2x_write_big_buf(bp, addr + i*4, cur_len); ++ } ++} ++ ++/********************************************************* ++ There are different blobs for each PRAM section. ++ In addition, each blob write operation is divided into a few operations ++ in order to decrease the amount of phys. contiguous buffer needed. ++ Thus, when we select a blob the address may be with some offset ++ from the beginning of PRAM section. ++ The same holds for the INT_TABLE sections. ++**********************************************************/ ++#define IF_IS_INT_TABLE_ADDR(base, addr) \ ++ if (((base) <= (addr)) && ((base) + 0x400 >= (addr))) ++ ++#define IF_IS_PRAM_ADDR(base, addr) \ ++ if (((base) <= (addr)) && ((base) + 0x40000 >= (addr))) ++ ++static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr, const u8 *data) ++{ ++ IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr) ++ data = INIT_TSEM_INT_TABLE_DATA(bp); ++ else ++ IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr) ++ data = INIT_CSEM_INT_TABLE_DATA(bp); ++ else ++ IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr) ++ data = INIT_USEM_INT_TABLE_DATA(bp); ++ else ++ IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr) ++ data = INIT_XSEM_INT_TABLE_DATA(bp); ++ else ++ IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr) ++ data = INIT_TSEM_PRAM_DATA(bp); ++ else ++ IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr) ++ data = INIT_CSEM_PRAM_DATA(bp); ++ else ++ IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr) ++ data = INIT_USEM_PRAM_DATA(bp); ++ else ++ IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr) ++ data = INIT_XSEM_PRAM_DATA(bp); ++ ++ return data; ++} ++ ++static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len) ++{ ++ if (bp->dmae_ready) ++ bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len); ++ else ++ bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len); ++} ++ ++static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data, ++ u32 len) ++{ ++ data = (const u32 *)bnx2x_sel_blob(bp, addr, (const u8 *)data); ++ ++ if (bp->dmae_ready) ++ VIRT_WR_DMAE_LEN(bp, data, addr, len); ++ else ++ bnx2x_init_ind_wr(bp, addr, data, len); ++} ++ ++static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr, u32 len, u32 blob_off) ++{ ++ const u8 *data = NULL; ++ int rc; ++ u32 i; ++ ++ data = bnx2x_sel_blob(bp, addr, data) + blob_off*4; ++ ++ rc = bnx2x_gunzip(bp, data, len); ++ if (rc) ++ return; ++ ++ /* gunzip_outlen is in dwords */ ++ len = GUNZIP_OUTLEN(bp); ++ for (i = 0; i < len; i++) ++ ((u32 *)GUNZIP_BUF(bp))[i] = ++ cpu_to_le32(((u32 *)GUNZIP_BUF(bp))[i]); ++ ++ bnx2x_write_big_buf_wb(bp, addr, len); ++} ++ ++static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage) ++{ ++ u16 op_start = ++ INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block,stage,STAGE_START)]; ++ u16 op_end = ++ INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block,stage,STAGE_END)]; ++ union init_op *op; ++ int hw_wr; ++ u32 i, op_type, addr, len; ++ const u32 *data, *data_base; ++ ++ /* If empty block */ ++ if (op_start == op_end) ++ return; ++ ++ if (CHIP_REV_IS_FPGA(bp)) ++ hw_wr = OP_WR_FPGA; ++ else if (CHIP_REV_IS_EMUL(bp)) ++ hw_wr = OP_WR_EMUL; ++ else ++ hw_wr = OP_WR_ASIC; ++ ++ data_base = INIT_DATA(bp); ++ ++ for (i = op_start; i < op_end; i++) { ++ ++ op = (union init_op *)&(INIT_OPS(bp)[i]); ++ ++ op_type = op->str_wr.op; ++ addr = op->str_wr.offset; ++ len = op->str_wr.data_len; ++ data = data_base + op->str_wr.data_off; ++ ++ /* HW/EMUL specific */ ++ if ((op_type > OP_WB) && (op_type == hw_wr)) ++ op_type = OP_WR; ++ ++ switch (op_type) { ++ case OP_RD: ++ REG_RD(bp, addr); ++ break; ++ case OP_WR: ++ REG_WR(bp, addr, op->write.val); ++ break; ++ case OP_SW: ++ bnx2x_init_str_wr(bp, addr, data, len); ++ break; ++ case OP_WB: ++ bnx2x_init_wr_wb(bp, addr, data, len); ++ break; ++ case OP_SI: ++ bnx2x_init_ind_wr(bp, addr, data, len); ++ break; ++ case OP_ZR: ++ bnx2x_init_fill(bp, addr, 0, op->zero.len); ++ break; ++ case OP_ZP: ++ bnx2x_init_wr_zp(bp, addr, len, ++ op->str_wr.data_off); ++ break; ++ case OP_WR_64: ++ bnx2x_init_wr_64(bp, addr, data, len); ++ break; ++ default: ++ /* happens whenever an op is of a diff HW */ ++ break; ++ } ++ } ++} ++ ++ ++/**************************************************************************** ++* PXP Arbiter ++****************************************************************************/ ++/* ++ * This code configures the PCI read/write arbiter ++ * which implements a weighted round robin ++ * between the virtual queues in the chip. ++ * ++ * The values were derived for each PCI max payload and max request size. ++ * since max payload and max request size are only known at run time, ++ * this is done as a separate init stage. ++ */ ++ ++#define NUM_WR_Q 13 ++#define NUM_RD_Q 29 ++#define MAX_RD_ORD 3 ++#define MAX_WR_ORD 2 ++ ++/* configuration for one arbiter queue */ ++struct arb_line { ++ int l; ++ int add; ++ int ubound; ++}; ++ ++/* derived configuration for each read queue for each max request size */ ++static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = { ++/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} }, ++ { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} }, ++ { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} }, ++ { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} }, ++ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, ++/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, ++ { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} } ++}; ++ ++/* derived configuration for each write queue for each max request size */ ++static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = { ++/* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} }, ++ { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} }, ++ { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, ++ { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, ++ { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, ++ { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, ++ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} }, ++ { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, ++ { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, ++/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} }, ++ { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} }, ++ { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} }, ++ { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} } ++}; ++ ++/* register addresses for read queues */ ++static const struct arb_line read_arb_addr[NUM_RD_Q-1] = { ++/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0, ++ PXP2_REG_RQ_BW_RD_UBOUND0}, ++ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, ++ PXP2_REG_PSWRQ_BW_UB1}, ++ {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, ++ PXP2_REG_PSWRQ_BW_UB2}, ++ {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, ++ PXP2_REG_PSWRQ_BW_UB3}, ++ {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4, ++ PXP2_REG_RQ_BW_RD_UBOUND4}, ++ {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5, ++ PXP2_REG_RQ_BW_RD_UBOUND5}, ++ {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, ++ PXP2_REG_PSWRQ_BW_UB6}, ++ {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, ++ PXP2_REG_PSWRQ_BW_UB7}, ++ {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, ++ PXP2_REG_PSWRQ_BW_UB8}, ++/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, ++ PXP2_REG_PSWRQ_BW_UB9}, ++ {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, ++ PXP2_REG_PSWRQ_BW_UB10}, ++ {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, ++ PXP2_REG_PSWRQ_BW_UB11}, ++ {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12, ++ PXP2_REG_RQ_BW_RD_UBOUND12}, ++ {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13, ++ PXP2_REG_RQ_BW_RD_UBOUND13}, ++ {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14, ++ PXP2_REG_RQ_BW_RD_UBOUND14}, ++ {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15, ++ PXP2_REG_RQ_BW_RD_UBOUND15}, ++ {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16, ++ PXP2_REG_RQ_BW_RD_UBOUND16}, ++ {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17, ++ PXP2_REG_RQ_BW_RD_UBOUND17}, ++ {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18, ++ PXP2_REG_RQ_BW_RD_UBOUND18}, ++/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19, ++ PXP2_REG_RQ_BW_RD_UBOUND19}, ++ {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20, ++ PXP2_REG_RQ_BW_RD_UBOUND20}, ++ {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22, ++ PXP2_REG_RQ_BW_RD_UBOUND22}, ++ {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23, ++ PXP2_REG_RQ_BW_RD_UBOUND23}, ++ {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24, ++ PXP2_REG_RQ_BW_RD_UBOUND24}, ++ {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25, ++ PXP2_REG_RQ_BW_RD_UBOUND25}, ++ {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26, ++ PXP2_REG_RQ_BW_RD_UBOUND26}, ++ {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27, ++ PXP2_REG_RQ_BW_RD_UBOUND27}, ++ {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, ++ PXP2_REG_PSWRQ_BW_UB28} ++}; ++ ++/* register addresses for write queues */ ++static const struct arb_line write_arb_addr[NUM_WR_Q-1] = { ++/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, ++ PXP2_REG_PSWRQ_BW_UB1}, ++ {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, ++ PXP2_REG_PSWRQ_BW_UB2}, ++ {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, ++ PXP2_REG_PSWRQ_BW_UB3}, ++ {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, ++ PXP2_REG_PSWRQ_BW_UB6}, ++ {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, ++ PXP2_REG_PSWRQ_BW_UB7}, ++ {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, ++ PXP2_REG_PSWRQ_BW_UB8}, ++ {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, ++ PXP2_REG_PSWRQ_BW_UB9}, ++ {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, ++ PXP2_REG_PSWRQ_BW_UB10}, ++ {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, ++ PXP2_REG_PSWRQ_BW_UB11}, ++/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, ++ PXP2_REG_PSWRQ_BW_UB28}, ++ {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29, ++ PXP2_REG_RQ_BW_WR_UBOUND29}, ++ {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30, ++ PXP2_REG_RQ_BW_WR_UBOUND30} ++}; ++ ++static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order, int w_order) ++{ ++ u32 val, i; ++ ++ if (r_order > MAX_RD_ORD) { ++ DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n", ++ r_order, MAX_RD_ORD); ++ r_order = MAX_RD_ORD; ++ } ++ if (w_order > MAX_WR_ORD) { ++ DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n", ++ w_order, MAX_WR_ORD); ++ w_order = MAX_WR_ORD; ++ } ++ if (CHIP_REV_IS_FPGA(bp)) { ++ DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n"); ++ w_order = 0; ++ } ++ DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order); ++ ++ for (i = 0; i < NUM_RD_Q-1; i++) { ++ REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l); ++ REG_WR(bp, read_arb_addr[i].add, ++ read_arb_data[i][r_order].add); ++ REG_WR(bp, read_arb_addr[i].ubound, ++ read_arb_data[i][r_order].ubound); ++ } ++ ++ for (i = 0; i < NUM_WR_Q-1; i++) { ++ if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) || ++ (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) { ++ ++ REG_WR(bp, write_arb_addr[i].l, ++ write_arb_data[i][w_order].l); ++ ++ REG_WR(bp, write_arb_addr[i].add, ++ write_arb_data[i][w_order].add); ++ ++ REG_WR(bp, write_arb_addr[i].ubound, ++ write_arb_data[i][w_order].ubound); ++ } else { ++ ++ val = REG_RD(bp, write_arb_addr[i].l); ++ REG_WR(bp, write_arb_addr[i].l, ++ val | (write_arb_data[i][w_order].l << 10)); ++ ++ val = REG_RD(bp, write_arb_addr[i].add); ++ REG_WR(bp, write_arb_addr[i].add, ++ val | (write_arb_data[i][w_order].add << 10)); ++ ++ val = REG_RD(bp, write_arb_addr[i].ubound); ++ REG_WR(bp, write_arb_addr[i].ubound, ++ val | (write_arb_data[i][w_order].ubound << 7)); ++ } ++ } ++ ++ val = write_arb_data[NUM_WR_Q-1][w_order].add; ++ val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10; ++ val += write_arb_data[NUM_WR_Q-1][w_order].l << 17; ++ REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val); ++ ++ val = read_arb_data[NUM_RD_Q-1][r_order].add; ++ val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10; ++ val += read_arb_data[NUM_RD_Q-1][r_order].l << 17; ++ REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val); ++ ++ REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order); ++ REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order); ++ REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order); ++ REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order); ++ ++ if (r_order == MAX_RD_ORD) ++ REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00); ++ ++ REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); ++ ++ if (CHIP_IS_E1H(bp)) { ++ /* MPS w_order optimal TH presently TH ++ * 128 0 0 2 ++ * 256 1 1 3 ++ * >=512 2 2 3 ++ */ ++ val = ((w_order == 0) ? 2 : 3); ++ REG_WR(bp, PXP2_REG_WR_HC_MPS, val); ++ REG_WR(bp, PXP2_REG_WR_USDM_MPS, val); ++ REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val); ++ REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val); ++ REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val); ++ REG_WR(bp, PXP2_REG_WR_QM_MPS, val); ++ REG_WR(bp, PXP2_REG_WR_TM_MPS, val); ++ REG_WR(bp, PXP2_REG_WR_SRC_MPS, val); ++ REG_WR(bp, PXP2_REG_WR_DBG_MPS, val); ++ REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */ ++ REG_WR(bp, PXP2_REG_WR_CDU_MPS, val); ++ } ++} ++ ++#endif /* BNX2X_INIT_OPS_H */ +diff -r e67cb9a8e847 drivers/net/bnx2x_init_values.h +--- a/drivers/net/bnx2x_init_values.h Wed Aug 05 10:50:39 2009 +0100 ++++ b/drivers/net/bnx2x_init_values.h Wed Aug 05 10:51:02 2009 +0100 +@@ -47,12 +47,16 @@ + {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000}, + {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000}, + {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000}, +- {OP_ZR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x4}, ++ {OP_ZR_E1, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x4}, ++ {OP_WR_E1H, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x40100000}, ++ {OP_ZR_E1H, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5, 0x3}, + {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000}, + {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000}, + {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000}, + {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000}, +- {OP_ZR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x4}, ++ {OP_ZR_E1, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x4}, ++ {OP_WR_E1H, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x42140000}, ++ {OP_ZR_E1H, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5, 0x3}, + {OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0}, + {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0}, + {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0}, +@@ -71,15 +75,16 @@ + {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f}, + {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f}, + {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f}, +- {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_4, 0x0}, ++ {OP_WR_E1, PRS_REG_PACKET_REGIONS_TYPE_4, 0x0}, ++ {OP_WR_E1H, PRS_REG_PACKET_REGIONS_TYPE_4, 0x3f}, + {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f}, + {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f}, + {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f}, +-#define PRS_COMMON_END 47 +-#define SRCH_COMMON_START 47 ++#define PRS_COMMON_END 52 ++#define SRCH_COMMON_START 52 + {OP_WR_E1H, SRC_REG_E1HMF_ENABLE, 0x1}, +-#define SRCH_COMMON_END 48 +-#define TSDM_COMMON_START 48 ++#define SRCH_COMMON_END 53 ++#define TSDM_COMMON_START 53 + {OP_WR_E1, TSDM_REG_CFC_RSP_START_ADDR, 0x411}, + {OP_WR_E1H, TSDM_REG_CFC_RSP_START_ADDR, 0x211}, + {OP_WR_E1, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400}, +@@ -118,8 +123,8 @@ + {OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8}, + {OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1}, + {OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa}, +-#define TSDM_COMMON_END 86 +-#define TCM_COMMON_START 86 ++#define TSDM_COMMON_END 91 ++#define TCM_COMMON_START 91 + {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20}, + {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32}, + {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020}, +@@ -149,7 +154,9 @@ + {OP_WR, TCM_REG_N_SM_CTX_LD_1, 0x7}, + {OP_WR, TCM_REG_N_SM_CTX_LD_2, 0x8}, + {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8}, +- {OP_ZR, TCM_REG_N_SM_CTX_LD_4, 0x4}, ++ {OP_ZR_E1, TCM_REG_N_SM_CTX_LD_4, 0x4}, ++ {OP_WR_E1H, TCM_REG_N_SM_CTX_LD_4, 0x1}, ++ {OP_ZR_E1H, TCM_REG_N_SM_CTX_LD_5, 0x3}, + {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6}, + {OP_WR_E1, TCM_REG_PHYS_QNUM0_0, 0xd}, + {OP_WR_E1, TCM_REG_PHYS_QNUM0_1, 0x2d}, +@@ -175,75 +182,75 @@ + {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1}, + {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1}, + {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1}, +-#define TCM_COMMON_END 141 +-#define TCM_FUNC0_START 141 ++#define TCM_COMMON_END 148 ++#define TCM_FUNC0_START 148 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0xd}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x7}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x7}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x7}, +-#define TCM_FUNC0_END 145 +-#define TCM_FUNC1_START 145 ++#define TCM_FUNC0_END 152 ++#define TCM_FUNC1_START 152 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x2d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x27}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x27}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x27}, +-#define TCM_FUNC1_END 149 +-#define TCM_FUNC2_START 149 ++#define TCM_FUNC1_END 156 ++#define TCM_FUNC2_START 156 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x1d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x17}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x17}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x17}, +-#define TCM_FUNC2_END 153 +-#define TCM_FUNC3_START 153 ++#define TCM_FUNC2_END 160 ++#define TCM_FUNC3_START 160 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x3d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x37}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x37}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x37}, +-#define TCM_FUNC3_END 157 +-#define TCM_FUNC4_START 157 ++#define TCM_FUNC3_END 164 ++#define TCM_FUNC4_START 164 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x4d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x47}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x47}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x47}, +-#define TCM_FUNC4_END 161 +-#define TCM_FUNC5_START 161 ++#define TCM_FUNC4_END 168 ++#define TCM_FUNC5_START 168 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x6d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x67}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x67}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x67}, +-#define TCM_FUNC5_END 165 +-#define TCM_FUNC6_START 165 ++#define TCM_FUNC5_END 172 ++#define TCM_FUNC6_START 172 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x5d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x57}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x57}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x57}, +-#define TCM_FUNC6_END 169 +-#define TCM_FUNC7_START 169 ++#define TCM_FUNC6_END 176 ++#define TCM_FUNC7_START 176 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x7d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x77}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x77}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x77}, +-#define TCM_FUNC7_END 173 +-#define BRB1_COMMON_START 173 ++#define TCM_FUNC7_END 180 ++#define BRB1_COMMON_START 180 + {OP_SW, BRB1_REG_LL_RAM, 0x2000020}, + {OP_WR, BRB1_REG_SOFT_RESET, 0x1}, + {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0}, + {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220}, + {OP_WR, BRB1_REG_SOFT_RESET, 0x0}, +-#define BRB1_COMMON_END 178 +-#define BRB1_PORT0_START 178 ++#define BRB1_COMMON_END 185 ++#define BRB1_PORT0_START 185 + {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0xb8}, + {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 0x114}, + {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0}, + {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0}, +-#define BRB1_PORT0_END 182 +-#define BRB1_PORT1_START 182 ++#define BRB1_PORT0_END 189 ++#define BRB1_PORT1_START 189 + {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0xb8}, + {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 0x114}, + {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0}, + {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0}, +-#define BRB1_PORT1_END 186 +-#define TSEM_COMMON_START 186 ++#define BRB1_PORT1_END 193 ++#define TSEM_COMMON_START 193 + {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0}, + {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0}, + {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0}, +@@ -303,143 +310,165 @@ + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa020, 0xc8}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1c18, 0x4}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa000, 0x2}, ++ {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1c10, 0x2}, ++ {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x1ad0, 0x0}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, +- {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x1ad0, 0x0}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3678, 0x6}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, +- {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3b28, 0x6}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3670, 0x2}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x810, 0x4}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2}, + {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x40224}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5008, 0x4}, + {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x4cb0, 0x80228}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5018, 0x4}, +- {OP_ZP_E1, TSEM_REG_INT_TABLE, 0x940000}, ++ {OP_ZP_E1, TSEM_REG_INT_TABLE, 0x920000}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5028, 0x4}, + {OP_WR_64_E1, TSEM_REG_INT_TABLE + 0x360, 0x140230}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5038, 0x4}, +- {OP_ZP_E1, TSEM_REG_PRAM, 0x30b10000}, ++ {OP_ZP_E1, TSEM_REG_PRAM, 0x32bb0000}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5048, 0x4}, +- {OP_ZP_E1, TSEM_REG_PRAM + 0x8000, 0x33c50c2d}, ++ {OP_ZP_E1, TSEM_REG_PRAM + 0x8000, 0x32f50caf}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5058, 0x4}, +- {OP_ZP_E1, TSEM_REG_PRAM + 0x10000, 0xbc6191f}, ++ {OP_ZP_E1, TSEM_REG_PRAM + 0x10000, 0xd28196d}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5068, 0x4}, +- {OP_WR_64_E1, TSEM_REG_PRAM + 0x117f0, 0x5d020232}, ++ {OP_WR_64_E1, TSEM_REG_PRAM + 0x11b00, 0x5ca00232}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5078, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x6140, 0x200224}, +- {OP_ZP_E1H, TSEM_REG_INT_TABLE, 0x960000}, +- {OP_WR_64_E1H, TSEM_REG_INT_TABLE + 0x360, 0x140244}, +- {OP_ZP_E1H, TSEM_REG_PRAM, 0x30cc0000}, +- {OP_ZP_E1H, TSEM_REG_PRAM + 0x8000, 0x33df0c33}, +- {OP_ZP_E1H, TSEM_REG_PRAM + 0x10000, 0xdce192b}, +- {OP_WR_64_E1H, TSEM_REG_PRAM + 0x11c70, 0x5c720246}, +-#define TSEM_COMMON_END 276 +-#define TSEM_PORT0_START 276 ++ {OP_ZP_E1H, TSEM_REG_INT_TABLE, 0x980000}, ++ {OP_WR_64_E1H, TSEM_REG_INT_TABLE + 0x398, 0xd0244}, ++ {OP_ZP_E1H, TSEM_REG_PRAM, 0x310a0000}, ++ {OP_ZP_E1H, TSEM_REG_PRAM + 0x8000, 0x35590c43}, ++ {OP_ZP_E1H, TSEM_REG_PRAM + 0x10000, 0x1a3c199a}, ++ {OP_WR_64_E1H, TSEM_REG_PRAM + 0x14210, 0x57be0246}, ++#define TSEM_COMMON_END 285 ++#define TSEM_PORT0_START 285 + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x22c8, 0x20}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x2000, 0x16c}, +- {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x4000, 0xfc}, ++ {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x4000, 0x16c}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb000, 0x28}, + {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b60, 0x0}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb140, 0xc}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1400, 0xa}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32c0, 0x12}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1450, 0x6}, +- {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3350, 0xfa}, +- {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500, 0xe}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3350, 0x64}, ++ {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8108, 0x2}, ++ {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1500 + 0x8, 0x50234}, ++ {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500 + 0x1c, 0x7}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1570, 0x12}, +- {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x9c0, 0xbe}, ++ {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x9c0, 0x4c}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x820, 0xe}, +- {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x20234}, ++ {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x20239}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2908, 0x2}, +-#define TSEM_PORT0_END 294 +-#define TSEM_PORT1_START 294 ++#define TSEM_PORT0_END 305 ++#define TSEM_PORT1_START 305 + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2348, 0x20}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x25b0, 0x16c}, +- {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x43f0, 0xfc}, ++ {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x45b0, 0x16c}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb0a0, 0x28}, + {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b64, 0x0}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb170, 0xc}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1428, 0xa}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3308, 0x12}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1468, 0x6}, +- {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3738, 0xfa}, +- {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538, 0xe}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x34e0, 0x64}, ++ {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8110, 0x2}, ++ {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1538 + 0x8, 0x5023b}, ++ {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538 + 0x1c, 0x7}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x15b8, 0x12}, +- {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0xcb8, 0xbe}, ++ {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0xaf0, 0x4c}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x858, 0xe}, +- {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20236}, ++ {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20240}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2910, 0x2}, +-#define TSEM_PORT1_END 312 +-#define TSEM_FUNC0_START 312 ++#define TSEM_PORT1_END 325 ++#define TSEM_FUNC0_START 325 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b60, 0x0}, +- {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000, 0xe}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000, 0x2}, ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3000 + 0x8, 0x50248}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000 + 0x1c, 0x7}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31c0, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5080, 0x12}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2}, +-#define TSEM_FUNC0_END 318 +-#define TSEM_FUNC1_START 318 ++#define TSEM_FUNC0_END 333 ++#define TSEM_FUNC1_START 333 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b64, 0x0}, +- {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038, 0xe}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038, 0x2}, ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3038 + 0x8, 0x5024d}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038 + 0x1c, 0x7}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31e0, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5010, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x50c8, 0x12}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2}, +-#define TSEM_FUNC1_END 324 +-#define TSEM_FUNC2_START 324 ++#define TSEM_FUNC1_END 341 ++#define TSEM_FUNC2_START 341 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b68, 0x0}, +- {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070, 0xe}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070, 0x2}, ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3070 + 0x8, 0x50252}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070 + 0x1c, 0x7}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3200, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5020, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5110, 0x12}, +- {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4010, 0x20248}, +-#define TSEM_FUNC2_END 330 +-#define TSEM_FUNC3_START 330 ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4010, 0x20257}, ++#define TSEM_FUNC2_END 349 ++#define TSEM_FUNC3_START 349 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b6c, 0x0}, +- {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8, 0xe}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8, 0x2}, ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x30a8 + 0x8, 0x50259}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8 + 0x1c, 0x7}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3220, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5030, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5158, 0x12}, +- {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4018, 0x2024a}, +-#define TSEM_FUNC3_END 336 +-#define TSEM_FUNC4_START 336 ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4018, 0x2025e}, ++#define TSEM_FUNC3_END 357 ++#define TSEM_FUNC4_START 357 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b70, 0x0}, +- {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0, 0xe}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0, 0x2}, ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x30e0 + 0x8, 0x50260}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0 + 0x1c, 0x7}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3240, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5040, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51a0, 0x12}, +- {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4020, 0x2024c}, +-#define TSEM_FUNC4_END 342 +-#define TSEM_FUNC5_START 342 ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4020, 0x20265}, ++#define TSEM_FUNC4_END 365 ++#define TSEM_FUNC5_START 365 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b74, 0x0}, +- {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118, 0xe}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118, 0x2}, ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3118 + 0x8, 0x50267}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118 + 0x1c, 0x7}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3260, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5050, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51e8, 0x12}, +- {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4028, 0x2024e}, +-#define TSEM_FUNC5_END 348 +-#define TSEM_FUNC6_START 348 ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4028, 0x2026c}, ++#define TSEM_FUNC5_END 373 ++#define TSEM_FUNC6_START 373 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b78, 0x0}, +- {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150, 0xe}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150, 0x2}, ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3150 + 0x8, 0x5026e}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150 + 0x1c, 0x7}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3280, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5060, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5230, 0x12}, +- {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4030, 0x20250}, +-#define TSEM_FUNC6_END 354 +-#define TSEM_FUNC7_START 354 ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4030, 0x20273}, ++#define TSEM_FUNC6_END 381 ++#define TSEM_FUNC7_START 381 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b7c, 0x0}, +- {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188, 0xe}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188, 0x2}, ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3188 + 0x8, 0x50275}, ++ {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188 + 0x1c, 0x7}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32a0, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5070, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5278, 0x12}, +- {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4038, 0x20252}, +-#define TSEM_FUNC7_END 360 +-#define MISC_COMMON_START 360 ++ {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4038, 0x2027a}, ++#define TSEM_FUNC7_END 389 ++#define MISC_COMMON_START 389 + {OP_WR_E1, MISC_REG_GRC_TIMEOUT_EN, 0x1}, + {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911}, + {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0}, +@@ -447,39 +476,39 @@ + {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0}, + {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209}, + {OP_WR_E1, MISC_REG_SPIO, 0xff000000}, +-#define MISC_COMMON_END 367 +-#define MISC_FUNC0_START 367 ++#define MISC_COMMON_END 396 ++#define MISC_FUNC0_START 396 + {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0}, +-#define MISC_FUNC0_END 368 +-#define MISC_FUNC1_START 368 ++#define MISC_FUNC0_END 397 ++#define MISC_FUNC1_START 397 + {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0}, +-#define MISC_FUNC1_END 369 +-#define MISC_FUNC2_START 369 ++#define MISC_FUNC1_END 398 ++#define MISC_FUNC2_START 398 + {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0}, +-#define MISC_FUNC2_END 370 +-#define MISC_FUNC3_START 370 ++#define MISC_FUNC2_END 399 ++#define MISC_FUNC3_START 399 + {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0}, +-#define MISC_FUNC3_END 371 +-#define MISC_FUNC4_START 371 ++#define MISC_FUNC3_END 400 ++#define MISC_FUNC4_START 400 + {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0}, +-#define MISC_FUNC4_END 372 +-#define MISC_FUNC5_START 372 ++#define MISC_FUNC4_END 401 ++#define MISC_FUNC5_START 401 + {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0}, +-#define MISC_FUNC5_END 373 +-#define MISC_FUNC6_START 373 ++#define MISC_FUNC5_END 402 ++#define MISC_FUNC6_START 402 + {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0}, +-#define MISC_FUNC6_END 374 +-#define MISC_FUNC7_START 374 ++#define MISC_FUNC6_END 403 ++#define MISC_FUNC7_START 403 + {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0}, +-#define MISC_FUNC7_END 375 +-#define NIG_COMMON_START 375 ++#define MISC_FUNC7_END 404 ++#define NIG_COMMON_START 404 + {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1}, + {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1}, + {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1}, + {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1}, + {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1}, +-#define NIG_COMMON_END 380 +-#define NIG_PORT0_START 380 ++#define NIG_COMMON_END 409 ++#define NIG_PORT0_START 409 + {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000}, + {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28}, + {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0}, +@@ -492,8 +521,8 @@ + {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1}, + {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1}, + {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1}, +-#define NIG_PORT0_END 392 +-#define NIG_PORT1_START 392 ++#define NIG_PORT0_END 421 ++#define NIG_PORT1_START 421 + {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000}, + {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28}, + {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0}, +@@ -506,11 +535,11 @@ + {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1}, + {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1}, + {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1}, +-#define NIG_PORT1_END 404 +-#define UPB_COMMON_START 404 ++#define NIG_PORT1_END 433 ++#define UPB_COMMON_START 433 + {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20}, +-#define UPB_COMMON_END 405 +-#define CSDM_COMMON_START 405 ++#define UPB_COMMON_END 434 ++#define CSDM_COMMON_START 434 + {OP_WR_E1, CSDM_REG_CFC_RSP_START_ADDR, 0xa11}, + {OP_WR_E1H, CSDM_REG_CFC_RSP_START_ADDR, 0x211}, + {OP_WR_E1, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, +@@ -550,8 +579,8 @@ + {OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8}, + {OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1}, + {OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa}, +-#define CSDM_COMMON_END 444 +-#define USDM_COMMON_START 444 ++#define CSDM_COMMON_END 473 ++#define USDM_COMMON_START 473 + {OP_WR_E1, USDM_REG_CFC_RSP_START_ADDR, 0xa11}, + {OP_WR_E1H, USDM_REG_CFC_RSP_START_ADDR, 0x411}, + {OP_WR_E1, USDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, +@@ -568,9 +597,14 @@ + {OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5}, + {OP_WR, USDM_REG_AGG_INT_EVENT_2, 0x34}, + {OP_WR, USDM_REG_AGG_INT_EVENT_3, 0x35}, +- {OP_ZR, USDM_REG_AGG_INT_EVENT_4, 0x5c}, ++ {OP_ZR_E1, USDM_REG_AGG_INT_EVENT_4, 0x5c}, ++ {OP_WR_E1H, USDM_REG_AGG_INT_EVENT_4, 0x7}, ++ {OP_ZR_E1H, USDM_REG_AGG_INT_EVENT_5, 0x5b}, + {OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1}, +- {OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x1f}, ++ {OP_ZR_E1, USDM_REG_AGG_INT_MODE_1, 0x1f}, ++ {OP_ZR_E1H, USDM_REG_AGG_INT_MODE_1, 0x3}, ++ {OP_WR_E1H, USDM_REG_AGG_INT_MODE_4, 0x1}, ++ {OP_ZR_E1H, USDM_REG_AGG_INT_MODE_5, 0x1b}, + {OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff}, + {OP_WR, USDM_REG_ENABLE_IN2, 0x3f}, + {OP_WR, USDM_REG_ENABLE_OUT1, 0x7ffffff}, +@@ -594,8 +628,8 @@ + {OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8}, + {OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1}, + {OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa}, +-#define USDM_COMMON_END 486 +-#define CCM_COMMON_START 486 ++#define USDM_COMMON_END 520 ++#define CCM_COMMON_START 520 + {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32}, + {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020}, + {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020}, +@@ -620,8 +654,8 @@ + {OP_WR, CCM_REG_XX_INIT_CRD, 0x3}, + {OP_WR, CCM_REG_XX_MSG_NUM, 0x18}, + {OP_ZR, CCM_REG_XX_TABLE, 0x12}, +- {OP_SW_E1, CCM_REG_XX_DESCR_TABLE, 0x240238}, +- {OP_SW_E1H, CCM_REG_XX_DESCR_TABLE, 0x240254}, ++ {OP_SW_E1, CCM_REG_XX_DESCR_TABLE, 0x240242}, ++ {OP_SW_E1H, CCM_REG_XX_DESCR_TABLE, 0x24027c}, + {OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1}, + {OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2}, + {OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8}, +@@ -657,8 +691,8 @@ + {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1}, + {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1}, + {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1}, +-#define CCM_COMMON_END 547 +-#define CCM_FUNC0_START 547 ++#define CCM_COMMON_END 581 ++#define CCM_FUNC0_START 581 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x9}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0xa}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x7}, +@@ -666,8 +700,8 @@ + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0xc}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0xb}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x7}, +-#define CCM_FUNC0_END 554 +-#define CCM_FUNC1_START 554 ++#define CCM_FUNC0_END 588 ++#define CCM_FUNC1_START 588 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x29}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x27}, +@@ -675,8 +709,8 @@ + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x2c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x2b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x27}, +-#define CCM_FUNC1_END 561 +-#define CCM_FUNC2_START 561 ++#define CCM_FUNC1_END 595 ++#define CCM_FUNC2_START 595 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x19}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x1a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x17}, +@@ -684,8 +718,8 @@ + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x1c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x1b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x17}, +-#define CCM_FUNC2_END 568 +-#define CCM_FUNC3_START 568 ++#define CCM_FUNC2_END 602 ++#define CCM_FUNC3_START 602 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x39}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x3a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x37}, +@@ -693,8 +727,8 @@ + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x3c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x3b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x37}, +-#define CCM_FUNC3_END 575 +-#define CCM_FUNC4_START 575 ++#define CCM_FUNC3_END 609 ++#define CCM_FUNC4_START 609 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x49}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x4a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x47}, +@@ -702,8 +736,8 @@ + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x4c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x4b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x47}, +-#define CCM_FUNC4_END 582 +-#define CCM_FUNC5_START 582 ++#define CCM_FUNC4_END 616 ++#define CCM_FUNC5_START 616 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x69}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x6a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x67}, +@@ -711,8 +745,8 @@ + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x6c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x6b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x67}, +-#define CCM_FUNC5_END 589 +-#define CCM_FUNC6_START 589 ++#define CCM_FUNC5_END 623 ++#define CCM_FUNC6_START 623 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x59}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x5a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x57}, +@@ -720,8 +754,8 @@ + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x5c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x5b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x57}, +-#define CCM_FUNC6_END 596 +-#define CCM_FUNC7_START 596 ++#define CCM_FUNC6_END 630 ++#define CCM_FUNC7_START 630 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x79}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x7a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x77}, +@@ -729,8 +763,8 @@ + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x7c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x7b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x77}, +-#define CCM_FUNC7_END 603 +-#define UCM_COMMON_START 603 ++#define CCM_FUNC7_END 637 ++#define UCM_COMMON_START 637 + {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32}, + {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020}, + {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020}, +@@ -756,14 +790,14 @@ + {OP_WR, UCM_REG_XX_INIT_CRD, 0xe}, + {OP_WR, UCM_REG_XX_MSG_NUM, 0x1b}, + {OP_ZR, UCM_REG_XX_TABLE, 0x12}, +- {OP_SW_E1, UCM_REG_XX_DESCR_TABLE, 0x1b025c}, +- {OP_SW_E1H, UCM_REG_XX_DESCR_TABLE, 0x1b0278}, ++ {OP_SW_E1, UCM_REG_XX_DESCR_TABLE, 0x1b0266}, ++ {OP_SW_E1H, UCM_REG_XX_DESCR_TABLE, 0x1b02a0}, + {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0x10}, + {OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7}, + {OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf}, + {OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10}, + {OP_ZR_E1, UCM_REG_N_SM_CTX_LD_4, 0x4}, +- {OP_WR_E1H, UCM_REG_N_SM_CTX_LD_4, 0xd}, ++ {OP_WR_E1H, UCM_REG_N_SM_CTX_LD_4, 0xb}, + {OP_ZR_E1H, UCM_REG_N_SM_CTX_LD_5, 0x3}, + {OP_WR, UCM_REG_UCM_REG0_SZ, 0x3}, + {OP_WR_E1, UCM_REG_PHYS_QNUM0_0, 0xf}, +@@ -787,56 +821,56 @@ + {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1}, + {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1}, + {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1}, +-#define UCM_COMMON_END 659 +-#define UCM_FUNC0_START 659 ++#define UCM_COMMON_END 693 ++#define UCM_FUNC0_START 693 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0xf}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0xe}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0}, +-#define UCM_FUNC0_END 663 +-#define UCM_FUNC1_START 663 ++#define UCM_FUNC0_END 697 ++#define UCM_FUNC1_START 697 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x2f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x2e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0}, +-#define UCM_FUNC1_END 667 +-#define UCM_FUNC2_START 667 ++#define UCM_FUNC1_END 701 ++#define UCM_FUNC2_START 701 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x1f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x1e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0}, +-#define UCM_FUNC2_END 671 +-#define UCM_FUNC3_START 671 ++#define UCM_FUNC2_END 705 ++#define UCM_FUNC3_START 705 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x3f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x3e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0}, +-#define UCM_FUNC3_END 675 +-#define UCM_FUNC4_START 675 ++#define UCM_FUNC3_END 709 ++#define UCM_FUNC4_START 709 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x4f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x4e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0}, +-#define UCM_FUNC4_END 679 +-#define UCM_FUNC5_START 679 ++#define UCM_FUNC4_END 713 ++#define UCM_FUNC5_START 713 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x6f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x6e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0}, +-#define UCM_FUNC5_END 683 +-#define UCM_FUNC6_START 683 ++#define UCM_FUNC5_END 717 ++#define UCM_FUNC6_START 717 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x5f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x5e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0}, +-#define UCM_FUNC6_END 687 +-#define UCM_FUNC7_START 687 ++#define UCM_FUNC6_END 721 ++#define UCM_FUNC7_START 721 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x7f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x7e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0}, +-#define UCM_FUNC7_END 691 +-#define USEM_COMMON_START 691 ++#define UCM_FUNC7_END 725 ++#define USEM_COMMON_START 725 + {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0}, + {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0}, + {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0}, +@@ -887,69 +921,78 @@ + {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500}, + {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4}, + {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5000, 0x102}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5000, 0xc2}, + {OP_WR_EMUL_E1H, USEM_REG_FAST_MEMORY + 0x11480, 0x0}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1020, 0xc8}, + {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x11480, 0x1}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1000, 0x2}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2000, 0x102}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57e8, 0x4}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8020, 0xc8}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57d0, 0x5}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8000, 0x2}, +- {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x57d0 + 0x14, 0x10277}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3760, 0x4}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1e20, 0x42}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3738, 0x9}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4f00, 0x40}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8980, 0xc8}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57f0, 0x4}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8960, 0x2}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57d8, 0x5}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3228, 0x4}, ++ {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x57d8 + 0x14, 0x10281}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3200, 0x9}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1c60, 0x20}, ++ {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x3200 + 0x24, 0x102bb}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b68, 0x2}, +- {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x3738 + 0x24, 0x10293}, +- {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x20278}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3180, 0x42}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3180, 0x20}, ++ {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x20282}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x400}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b10, 0x2}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x400}, +- {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x2027a}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000, 0x2}, +- {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x20294}, ++ {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x20284}, ++ {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x102bc}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0xc, 0x3}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b68, 0x2}, +- {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x20296}, ++ {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x202bd}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b10, 0x2}, +- {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x74c0, 0x20298}, ++ {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x74c0, 0x202bf}, + {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, +- {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x10027c}, +- {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c00, 0x10029a}, ++ {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x100286}, ++ {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c00, 0x1002c1}, + {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0}, +- {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x10028c}, +- {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002aa}, +- {OP_ZP_E1, USEM_REG_INT_TABLE, 0xc20000}, +- {OP_ZP_E1H, USEM_REG_INT_TABLE, 0xc40000}, +- {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x13029c}, +- {OP_WR_64_E1H, USEM_REG_INT_TABLE + 0x368, 0x1302ba}, +- {OP_ZP_E1, USEM_REG_PRAM, 0x311c0000}, +- {OP_ZP_E1H, USEM_REG_PRAM, 0x31070000}, +- {OP_ZP_E1, USEM_REG_PRAM + 0x8000, 0x33450c47}, +- {OP_ZP_E1H, USEM_REG_PRAM + 0x8000, 0x330e0c42}, +- {OP_ZP_E1, USEM_REG_PRAM + 0x10000, 0x38561919}, +- {OP_ZP_E1H, USEM_REG_PRAM + 0x10000, 0x389b1906}, +- {OP_WR_64_E1, USEM_REG_PRAM + 0x17fe0, 0x5004029e}, +- {OP_ZP_E1H, USEM_REG_PRAM + 0x18000, 0x132272d}, +- {OP_WR_64_E1H, USEM_REG_PRAM + 0x18250, 0x4fb602bc}, +-#define USEM_COMMON_END 787 +-#define USEM_PORT0_START 787 ++ {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x100296}, ++ {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002d1}, ++ {OP_ZP_E1, USEM_REG_INT_TABLE, 0xc50000}, ++ {OP_ZP_E1H, USEM_REG_INT_TABLE, 0xcd0000}, ++ {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x1302a6}, ++ {OP_WR_64_E1H, USEM_REG_INT_TABLE + 0x3a8, 0xb02e1}, ++ {OP_ZP_E1, USEM_REG_PRAM, 0x31fb0000}, ++ {OP_ZP_E1H, USEM_REG_PRAM, 0x32200000}, ++ {OP_ZP_E1, USEM_REG_PRAM + 0x8000, 0x36490c7f}, ++ {OP_ZP_E1H, USEM_REG_PRAM + 0x8000, 0x36020c88}, ++ {OP_ZP_E1, USEM_REG_PRAM + 0x10000, 0x358d1a12}, ++ {OP_ZP_E1H, USEM_REG_PRAM + 0x10000, 0x33b61a09}, ++ {OP_ZP_E1, USEM_REG_PRAM + 0x18000, 0x4152776}, ++ {OP_ZP_E1H, USEM_REG_PRAM + 0x18000, 0x26a126f7}, ++ {OP_WR_64_E1, USEM_REG_PRAM + 0x188b0, 0x4eea02a8}, ++ {OP_ZP_E1H, USEM_REG_PRAM + 0x20000, 0x71230a0}, ++ {OP_WR_64_E1H, USEM_REG_PRAM + 0x20e70, 0x3e3202e3}, ++#define USEM_COMMON_END 825 ++#define USEM_PORT0_START 825 + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1400, 0xa0}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9000, 0xa0}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1900, 0xa}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9500, 0x28}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1950, 0x2e}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9640, 0x34}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1d00, 0x4}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1900, 0x10}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9500, 0x40}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1980, 0x30}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9700, 0x3c}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1d80, 0x48}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2450, 0x48}, ++ {OP_WR_E1, USEM_REG_FAST_MEMORY + 0x1fd0, 0x0}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2770, 0x2}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1b40, 0x4}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3080, 0x20}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1d20, 0x20}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3288, 0x96}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5440, 0x72}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1b60, 0x20}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8000, 0x12c}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5318, 0x98}, ++ {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x3238, 0x0}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x20}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5100, 0x20}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5200, 0x20}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5300, 0x20}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5400, 0x20}, +@@ -966,23 +1009,28 @@ + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f00, 0x20}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b78, 0x52}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e08, 0xc}, +-#define USEM_PORT0_END 818 +-#define USEM_PORT1_START 818 ++#define USEM_PORT0_END 861 ++#define USEM_PORT1_START 861 + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1680, 0xa0}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9280, 0xa0}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1928, 0xa}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x95a0, 0x28}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1a08, 0x2e}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9710, 0x34}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1d10, 0x4}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1940, 0x10}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9600, 0x40}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1a40, 0x30}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x97f0, 0x3c}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1ea0, 0x48}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2570, 0x48}, ++ {OP_WR_E1, USEM_REG_FAST_MEMORY + 0x1fd4, 0x0}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2778, 0x2}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1b50, 0x4}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3100, 0x20}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1da0, 0x20}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x34e0, 0x96}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5608, 0x72}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1be0, 0x20}, ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x84b0, 0x12c}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5578, 0x98}, ++ {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x323c, 0x0}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5080, 0x20}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52}, ++ {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5180, 0x20}, +- {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5280, 0x20}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5380, 0x20}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5480, 0x20}, +@@ -999,40 +1047,48 @@ + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f80, 0x20}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e38, 0xc}, +-#define USEM_PORT1_END 849 +-#define USEM_FUNC0_START 849 ++#define USEM_PORT1_END 897 ++#define USEM_FUNC0_START 897 ++ {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x26d0, 0x0}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3000, 0x4}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4010, 0x2}, +-#define USEM_FUNC0_END 851 +-#define USEM_FUNC1_START 851 ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4018, 0x2}, ++#define USEM_FUNC0_END 900 ++#define USEM_FUNC1_START 900 ++ {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x26d4, 0x0}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3010, 0x4}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4020, 0x2}, +-#define USEM_FUNC1_END 853 +-#define USEM_FUNC2_START 853 ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4028, 0x2}, ++#define USEM_FUNC1_END 903 ++#define USEM_FUNC2_START 903 ++ {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x26d8, 0x0}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3020, 0x4}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4030, 0x2}, +-#define USEM_FUNC2_END 855 +-#define USEM_FUNC3_START 855 ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4038, 0x2}, ++#define USEM_FUNC2_END 906 ++#define USEM_FUNC3_START 906 ++ {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x26dc, 0x0}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3030, 0x4}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4040, 0x2}, +-#define USEM_FUNC3_END 857 +-#define USEM_FUNC4_START 857 ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4048, 0x2}, ++#define USEM_FUNC3_END 909 ++#define USEM_FUNC4_START 909 ++ {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x26e0, 0x0}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3040, 0x4}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4050, 0x2}, +-#define USEM_FUNC4_END 859 +-#define USEM_FUNC5_START 859 ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4058, 0x2}, ++#define USEM_FUNC4_END 912 ++#define USEM_FUNC5_START 912 ++ {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x26e4, 0x0}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3050, 0x4}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4060, 0x2}, +-#define USEM_FUNC5_END 861 +-#define USEM_FUNC6_START 861 ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4068, 0x2}, ++#define USEM_FUNC5_END 915 ++#define USEM_FUNC6_START 915 ++ {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x26e8, 0x0}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3060, 0x4}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4070, 0x2}, +-#define USEM_FUNC6_END 863 +-#define USEM_FUNC7_START 863 ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4078, 0x2}, ++#define USEM_FUNC6_END 918 ++#define USEM_FUNC7_START 918 ++ {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x26ec, 0x0}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3070, 0x4}, +- {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4080, 0x2}, +-#define USEM_FUNC7_END 865 +-#define CSEM_COMMON_START 865 ++ {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4088, 0x2}, ++#define USEM_FUNC7_END 921 ++#define CSEM_COMMON_START 921 + {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0}, + {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0}, + {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0}, +@@ -1091,29 +1147,29 @@ + {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0}, + {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0}, +- {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802a0}, ++ {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802aa}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4070, 0x80}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x5280, 0x4}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6280, 0x240}, +- {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x6b88, 0x2002be}, ++ {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x6b88, 0x2002e5}, + {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff}, +- {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002a8}, +- {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002de}, ++ {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002b2}, ++ {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c00, 0x100305}, + {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0}, +- {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002b8}, +- {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ee}, +- {OP_ZP_E1, CSEM_REG_INT_TABLE, 0x6e0000}, +- {OP_ZP_E1H, CSEM_REG_INT_TABLE, 0x6f0000}, +- {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002c8}, +- {OP_WR_64_E1H, CSEM_REG_INT_TABLE + 0x380, 0x1002fe}, +- {OP_ZP_E1, CSEM_REG_PRAM, 0x32580000}, +- {OP_ZP_E1H, CSEM_REG_PRAM, 0x31fa0000}, +- {OP_ZP_E1, CSEM_REG_PRAM + 0x8000, 0x18270c96}, +- {OP_ZP_E1H, CSEM_REG_PRAM + 0x8000, 0x19040c7f}, +- {OP_WR_64_E1, CSEM_REG_PRAM + 0xb210, 0x682402ca}, +- {OP_WR_64_E1H, CSEM_REG_PRAM + 0xb430, 0x67e00300}, +-#define CSEM_COMMON_END 944 +-#define CSEM_PORT0_START 944 ++ {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002c2}, ++ {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c40, 0x100315}, ++ {OP_ZP_E1, CSEM_REG_INT_TABLE, 0x710000}, ++ {OP_ZP_E1H, CSEM_REG_INT_TABLE, 0x740000}, ++ {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002d2}, ++ {OP_WR_64_E1H, CSEM_REG_INT_TABLE + 0x380, 0x100325}, ++ {OP_ZP_E1, CSEM_REG_PRAM, 0x32300000}, ++ {OP_ZP_E1H, CSEM_REG_PRAM, 0x321c0000}, ++ {OP_ZP_E1, CSEM_REG_PRAM + 0x8000, 0x229a0c8c}, ++ {OP_ZP_E1H, CSEM_REG_PRAM + 0x8000, 0x23960c87}, ++ {OP_WR_64_E1, CSEM_REG_PRAM + 0xc810, 0x656402d4}, ++ {OP_WR_64_E1H, CSEM_REG_PRAM + 0xca30, 0x65200327}, ++#define CSEM_COMMON_END 1000 ++#define CSEM_PORT0_START 1000 + {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8000, 0xa0}, + {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1900, 0x10}, +@@ -1126,8 +1182,8 @@ + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6040, 0x30}, + {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3040, 0x6}, + {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2410, 0x30}, +-#define CSEM_PORT0_END 956 +-#define CSEM_PORT1_START 956 ++#define CSEM_PORT0_END 1012 ++#define CSEM_PORT1_START 1012 + {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8280, 0xa0}, + {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1940, 0x10}, +@@ -1140,43 +1196,43 @@ + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6100, 0x30}, + {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3058, 0x6}, + {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30}, +-#define CSEM_PORT1_END 968 +-#define CSEM_FUNC0_START 968 ++#define CSEM_PORT1_END 1024 ++#define CSEM_FUNC0_START 1024 + {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1148, 0x0}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3300, 0x2}, +-#define CSEM_FUNC0_END 970 +-#define CSEM_FUNC1_START 970 ++#define CSEM_FUNC0_END 1026 ++#define CSEM_FUNC1_START 1026 + {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x114c, 0x0}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3308, 0x2}, +-#define CSEM_FUNC1_END 972 +-#define CSEM_FUNC2_START 972 ++#define CSEM_FUNC1_END 1028 ++#define CSEM_FUNC2_START 1028 + {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1150, 0x0}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3310, 0x2}, +-#define CSEM_FUNC2_END 974 +-#define CSEM_FUNC3_START 974 ++#define CSEM_FUNC2_END 1030 ++#define CSEM_FUNC3_START 1030 + {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1154, 0x0}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3318, 0x2}, +-#define CSEM_FUNC3_END 976 +-#define CSEM_FUNC4_START 976 ++#define CSEM_FUNC3_END 1032 ++#define CSEM_FUNC4_START 1032 + {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1158, 0x0}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3320, 0x2}, +-#define CSEM_FUNC4_END 978 +-#define CSEM_FUNC5_START 978 ++#define CSEM_FUNC4_END 1034 ++#define CSEM_FUNC5_START 1034 + {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x115c, 0x0}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3328, 0x2}, +-#define CSEM_FUNC5_END 980 +-#define CSEM_FUNC6_START 980 ++#define CSEM_FUNC5_END 1036 ++#define CSEM_FUNC6_START 1036 + {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1160, 0x0}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3330, 0x2}, +-#define CSEM_FUNC6_END 982 +-#define CSEM_FUNC7_START 982 ++#define CSEM_FUNC6_END 1038 ++#define CSEM_FUNC7_START 1038 + {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1164, 0x0}, + {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3338, 0x2}, +-#define CSEM_FUNC7_END 984 +-#define XPB_COMMON_START 984 ++#define CSEM_FUNC7_END 1040 ++#define XPB_COMMON_START 1040 + {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20}, +-#define XPB_COMMON_END 985 +-#define DQ_COMMON_START 985 ++#define XPB_COMMON_END 1041 ++#define DQ_COMMON_START 1041 + {OP_WR, DORQ_REG_MODE_ACT, 0x2}, + {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3}, + {OP_WR, DORQ_REG_OUTST_REQ, 0x4}, +@@ -1195,8 +1251,8 @@ + {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c}, + {OP_WR, DORQ_REG_REGN, 0x7c1004}, + {OP_WR, DORQ_REG_IF_EN, 0xf}, +-#define DQ_COMMON_END 1003 +-#define TIMERS_COMMON_START 1003 ++#define DQ_COMMON_END 1059 ++#define TIMERS_COMMON_START 1059 + {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2}, + {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c}, + {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1}, +@@ -1219,14 +1275,18 @@ + {OP_WR, TM_REG_EN_CL0_INPUT, 0x1}, + {OP_WR, TM_REG_EN_CL1_INPUT, 0x1}, + {OP_WR, TM_REG_EN_CL2_INPUT, 0x1}, +-#define TIMERS_COMMON_END 1025 +-#define TIMERS_PORT0_START 1025 ++#define TIMERS_COMMON_END 1081 ++#define TIMERS_PORT0_START 1081 ++ {OP_WR, TM_REG_LIN0_LOGIC_ADDR, 0x0}, ++ {OP_WR, TM_REG_LIN0_PHY_ADDR_VALID, 0x0}, + {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2}, +-#define TIMERS_PORT0_END 1026 +-#define TIMERS_PORT1_START 1026 ++#define TIMERS_PORT0_END 1084 ++#define TIMERS_PORT1_START 1084 ++ {OP_WR, TM_REG_LIN1_LOGIC_ADDR, 0x0}, ++ {OP_WR, TM_REG_LIN1_PHY_ADDR_VALID, 0x0}, + {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2}, +-#define TIMERS_PORT1_END 1027 +-#define XSDM_COMMON_START 1027 ++#define TIMERS_PORT1_END 1087 ++#define XSDM_COMMON_START 1087 + {OP_WR_E1, XSDM_REG_CFC_RSP_START_ADDR, 0x614}, + {OP_WR_E1H, XSDM_REG_CFC_RSP_START_ADDR, 0x424}, + {OP_WR_E1, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600}, +@@ -1274,8 +1334,8 @@ + {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8}, + {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1}, + {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa}, +-#define XSDM_COMMON_END 1074 +-#define QM_COMMON_START 1074 ++#define XSDM_COMMON_END 1134 ++#define QM_COMMON_START 1134 + {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6}, + {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5}, + {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa}, +@@ -1576,8 +1636,8 @@ + {OP_WR_E1H, QM_REG_PQ2PCIFUNC_6, 0x5}, + {OP_WR_E1H, QM_REG_PQ2PCIFUNC_7, 0x7}, + {OP_WR, QM_REG_CMINTEN, 0xff}, +-#define QM_COMMON_END 1374 +-#define PBF_COMMON_START 1374 ++#define QM_COMMON_END 1434 ++#define PBF_COMMON_START 1434 + {OP_WR, PBF_REG_INIT, 0x1}, + {OP_WR, PBF_REG_INIT_P4, 0x1}, + {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1}, +@@ -1585,20 +1645,20 @@ + {OP_WR, PBF_REG_INIT_P4, 0x0}, + {OP_WR, PBF_REG_INIT, 0x0}, + {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0}, +-#define PBF_COMMON_END 1381 +-#define PBF_PORT0_START 1381 ++#define PBF_COMMON_END 1441 ++#define PBF_PORT0_START 1441 + {OP_WR, PBF_REG_INIT_P0, 0x1}, + {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1}, + {OP_WR, PBF_REG_INIT_P0, 0x0}, + {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0}, +-#define PBF_PORT0_END 1385 +-#define PBF_PORT1_START 1385 ++#define PBF_PORT0_END 1445 ++#define PBF_PORT1_START 1445 + {OP_WR, PBF_REG_INIT_P1, 0x1}, + {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1}, + {OP_WR, PBF_REG_INIT_P1, 0x0}, + {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0}, +-#define PBF_PORT1_END 1389 +-#define XCM_COMMON_START 1389 ++#define PBF_PORT1_END 1449 ++#define XCM_COMMON_START 1449 + {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32}, + {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020}, + {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020}, +@@ -1633,14 +1693,14 @@ + {OP_WR_E1, XCM_REG_XX_MSG_NUM, 0x1f}, + {OP_WR_E1H, XCM_REG_XX_MSG_NUM, 0x20}, + {OP_ZR, XCM_REG_XX_TABLE, 0x12}, +- {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02cc}, +- {OP_SW_E1H, XCM_REG_XX_DESCR_TABLE, 0x1f0302}, ++ {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02d6}, ++ {OP_SW_E1H, XCM_REG_XX_DESCR_TABLE, 0x1f0329}, + {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf}, + {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7}, + {OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb}, + {OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe}, + {OP_ZR_E1, XCM_REG_N_SM_CTX_LD_4, 0x4}, +- {OP_WR_E1H, XCM_REG_N_SM_CTX_LD_4, 0xc}, ++ {OP_WR_E1H, XCM_REG_N_SM_CTX_LD_4, 0xe}, + {OP_ZR_E1H, XCM_REG_N_SM_CTX_LD_5, 0x3}, + {OP_WR, XCM_REG_XCM_REG0_SZ, 0x4}, + {OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1}, +@@ -1663,8 +1723,8 @@ + {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1}, + {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1}, + {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1}, +-#define XCM_COMMON_END 1453 +-#define XCM_PORT0_START 1453 ++#define XCM_COMMON_END 1513 ++#define XCM_PORT0_START 1513 + {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, + {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, + {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, +@@ -1673,8 +1733,8 @@ + {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD10, 0x2}, + {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, + {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, +-#define XCM_PORT0_END 1461 +-#define XCM_PORT1_START 1461 ++#define XCM_PORT0_END 1521 ++#define XCM_PORT1_START 1521 + {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, + {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, + {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, +@@ -1683,8 +1743,8 @@ + {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD11, 0x2}, + {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, + {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, +-#define XCM_PORT1_END 1469 +-#define XCM_FUNC0_START 1469 ++#define XCM_PORT1_END 1529 ++#define XCM_FUNC0_START 1529 + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, + {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, +@@ -1694,8 +1754,8 @@ + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, + {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, +-#define XCM_FUNC0_END 1478 +-#define XCM_FUNC1_START 1478 ++#define XCM_FUNC0_END 1538 ++#define XCM_FUNC1_START 1538 + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, + {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, +@@ -1705,8 +1765,8 @@ + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, + {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, +-#define XCM_FUNC1_END 1487 +-#define XCM_FUNC2_START 1487 ++#define XCM_FUNC1_END 1547 ++#define XCM_FUNC2_START 1547 + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, + {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, +@@ -1716,8 +1776,8 @@ + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, + {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, +-#define XCM_FUNC2_END 1496 +-#define XCM_FUNC3_START 1496 ++#define XCM_FUNC2_END 1556 ++#define XCM_FUNC3_START 1556 + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, + {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, +@@ -1727,8 +1787,8 @@ + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, + {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, +-#define XCM_FUNC3_END 1505 +-#define XCM_FUNC4_START 1505 ++#define XCM_FUNC3_END 1565 ++#define XCM_FUNC4_START 1565 + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, + {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, +@@ -1738,8 +1798,8 @@ + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, + {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, +-#define XCM_FUNC4_END 1514 +-#define XCM_FUNC5_START 1514 ++#define XCM_FUNC4_END 1574 ++#define XCM_FUNC5_START 1574 + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, + {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, +@@ -1749,8 +1809,8 @@ + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, + {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, +-#define XCM_FUNC5_END 1523 +-#define XCM_FUNC6_START 1523 ++#define XCM_FUNC5_END 1583 ++#define XCM_FUNC6_START 1583 + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, + {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, +@@ -1760,8 +1820,8 @@ + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, + {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, +-#define XCM_FUNC6_END 1532 +-#define XCM_FUNC7_START 1532 ++#define XCM_FUNC6_END 1592 ++#define XCM_FUNC7_START 1592 + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, + {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, + {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, +@@ -1771,8 +1831,8 @@ + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, + {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, + {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, +-#define XCM_FUNC7_END 1541 +-#define XSEM_COMMON_START 1541 ++#define XCM_FUNC7_END 1601 ++#define XSEM_COMMON_START 1601 + {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0}, + {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0}, + {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0}, +@@ -1827,10 +1887,10 @@ + {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500}, + {OP_WR_EMUL_E1H, XSEM_REG_FAST_MEMORY + 0x11480, 0x0}, + {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40}, +- {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3d00, 0x4}, ++ {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3d20, 0x4}, + {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x11480, 0x1}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3000, 0x48}, +- {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x28a8, 0x4}, ++ {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x28c8, 0x4}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1020, 0xc8}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2080, 0x48}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1000, 0x2}, +@@ -1839,65 +1899,66 @@ + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9000, 0x2}, + {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3368, 0x0}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86}, +- {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202eb}, ++ {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202f5}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2000, 0x20}, +- {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402ed}, ++ {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402f7}, + {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0}, + {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1518, 0x1}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x23d0, 0x20321}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x23d0, 0x20348}, + {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1830, 0x0}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2498, 0x40323}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2498, 0x4034a}, + {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1838, 0x0}, +- {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ac8, 0x0}, +- {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202f1}, +- {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ab8, 0x0}, ++ {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ae8, 0x0}, ++ {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202fb}, ++ {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ad8, 0x0}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2}, + {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3010, 0x1}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x4040, 0x10}, +- {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f50, 0x202f3}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x4000, 0x100327}, ++ {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f48, 0x202fd}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x4000, 0x10034e}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x83b0, 0x20337}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x83a8, 0x2035e}, + {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0}, +- {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x1002f5}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100339}, ++ {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x1002ff}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100360}, + {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, +- {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80305}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80349}, ++ {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x8030f}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80370}, + {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000}, +- {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8030d}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80351}, +- {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xa90000}, +- {OP_ZP_E1H, XSEM_REG_INT_TABLE, 0xac0000}, +- {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130315}, +- {OP_WR_64_E1H, XSEM_REG_INT_TABLE + 0x368, 0x130359}, +- {OP_ZP_E1, XSEM_REG_PRAM, 0x344e0000}, +- {OP_ZP_E1H, XSEM_REG_PRAM, 0x34620000}, +- {OP_ZP_E1, XSEM_REG_PRAM + 0x8000, 0x38840d14}, +- {OP_ZP_E1H, XSEM_REG_PRAM + 0x8000, 0x38240d19}, +- {OP_ZP_E1, XSEM_REG_PRAM + 0x10000, 0x3e711b35}, +- {OP_ZP_E1H, XSEM_REG_PRAM + 0x10000, 0x3e971b22}, +- {OP_ZP_E1, XSEM_REG_PRAM + 0x18000, 0x1dd02ad2}, +- {OP_ZP_E1H, XSEM_REG_PRAM + 0x18000, 0x21542ac8}, +- {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0d0, 0x47e60317}, +- {OP_WR_64_E1H, XSEM_REG_PRAM + 0x1c8d0, 0x46e6035b}, +-#define XSEM_COMMON_END 1651 +-#define XSEM_PORT0_START 1651 +- {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3ba0, 0x10}, ++ {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80317}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80378}, ++ {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xae0000}, ++ {OP_ZP_E1H, XSEM_REG_INT_TABLE, 0xbb0000}, ++ {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x13031f}, ++ {OP_WR_64_E1H, XSEM_REG_INT_TABLE + 0x3a8, 0xb0380}, ++ {OP_ZP_E1, XSEM_REG_PRAM, 0x342d0000}, ++ {OP_ZP_E1H, XSEM_REG_PRAM, 0x34530000}, ++ {OP_ZP_E1, XSEM_REG_PRAM + 0x8000, 0x38640d0c}, ++ {OP_ZP_E1H, XSEM_REG_PRAM + 0x8000, 0x37e90d15}, ++ {OP_ZP_E1, XSEM_REG_PRAM + 0x10000, 0x3c161b25}, ++ {OP_ZP_E1H, XSEM_REG_PRAM + 0x10000, 0x3be21b10}, ++ {OP_ZP_E1, XSEM_REG_PRAM + 0x18000, 0x249b2a2b}, ++ {OP_ZP_E1H, XSEM_REG_PRAM + 0x18000, 0x33ed2a09}, ++ {OP_WR_64_E1, XSEM_REG_PRAM + 0x1cbc0, 0x46880321}, ++ {OP_ZP_E1H, XSEM_REG_PRAM + 0x20000, 0x13903705}, ++ {OP_WR_64_E1H, XSEM_REG_PRAM + 0x224f0, 0x3b620382}, ++#define XSEM_COMMON_END 1712 ++#define XSEM_PORT0_START 1712 ++ {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3ba0, 0x14}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc000, 0xfc}, +- {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c20, 0x1c}, +- {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x24a8, 0x10}, ++ {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c40, 0x1c}, ++ {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x24a8, 0x14}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1400, 0xa}, +- {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2528, 0x1c}, ++ {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2548, 0x1c}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1450, 0x6}, +- {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2608, 0x1c}, ++ {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2628, 0x1c}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3378, 0xfc}, +- {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x26e8, 0x1c}, ++ {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2708, 0x1c}, + {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b58, 0x0}, +- {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x27c8, 0x1c}, +- {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d10, 0x100319}, ++ {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x27e8, 0x1c}, ++ {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d30, 0x100323}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa000, 0x28}, + {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1500, 0x0}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa140, 0xc}, +@@ -1910,28 +1971,28 @@ + {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x5040, 0x0}, + {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x5208, 0x1}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x5048, 0xe}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x2035d}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x20384}, + {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42}, +- {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x20329}, ++ {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x20333}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4}, +-#define XSEM_PORT0_END 1683 +-#define XSEM_PORT1_START 1683 +- {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3be0, 0x10}, ++#define XSEM_PORT0_END 1744 ++#define XSEM_PORT1_START 1744 ++ {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3bf0, 0x14}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc3f0, 0xfc}, +- {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c90, 0x1c}, +- {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x24e8, 0x10}, ++ {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3cb0, 0x1c}, ++ {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x24f8, 0x14}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1428, 0xa}, +- {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2598, 0x1c}, ++ {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x25b8, 0x1c}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1468, 0x6}, +- {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2678, 0x1c}, ++ {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2698, 0x1c}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3768, 0xfc}, +- {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2758, 0x1c}, ++ {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2778, 0x1c}, + {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b5c, 0x0}, +- {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2838, 0x1c}, +- {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d50, 0x10032b}, ++ {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2858, 0x1c}, ++ {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d70, 0x100335}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28}, + {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1504, 0x0}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa170, 0xc}, +@@ -1944,68 +2005,68 @@ + {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x5044, 0x0}, + {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x520c, 0x1}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x5080, 0xe}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x2035f}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x20386}, + {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42}, +- {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2033b}, ++ {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x20345}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42}, + {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4}, +-#define XSEM_PORT1_END 1715 +-#define XSEM_FUNC0_START 1715 ++#define XSEM_PORT1_END 1776 ++#define XSEM_FUNC0_START 1776 + {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e0, 0x0}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28b8, 0x100361}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28d8, 0x100388}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5048, 0xe}, +-#define XSEM_FUNC0_END 1718 +-#define XSEM_FUNC1_START 1718 ++#define XSEM_FUNC0_END 1779 ++#define XSEM_FUNC1_START 1779 + {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e4, 0x0}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28f8, 0x100371}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2918, 0x100398}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5080, 0xe}, +-#define XSEM_FUNC1_END 1721 +-#define XSEM_FUNC2_START 1721 ++#define XSEM_FUNC1_END 1782 ++#define XSEM_FUNC2_START 1782 + {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e8, 0x0}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2938, 0x100381}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2958, 0x1003a8}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe}, +-#define XSEM_FUNC2_END 1724 +-#define XSEM_FUNC3_START 1724 ++#define XSEM_FUNC2_END 1785 ++#define XSEM_FUNC3_START 1785 + {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7ec, 0x0}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2978, 0x100391}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2998, 0x1003b8}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe}, +-#define XSEM_FUNC3_END 1727 +-#define XSEM_FUNC4_START 1727 ++#define XSEM_FUNC3_END 1788 ++#define XSEM_FUNC4_START 1788 + {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f0, 0x0}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29b8, 0x1003a1}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29d8, 0x1003c8}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5128, 0xe}, +-#define XSEM_FUNC4_END 1730 +-#define XSEM_FUNC5_START 1730 ++#define XSEM_FUNC4_END 1791 ++#define XSEM_FUNC5_START 1791 + {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f4, 0x0}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29f8, 0x1003b1}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a18, 0x1003d8}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5160, 0xe}, +-#define XSEM_FUNC5_END 1733 +-#define XSEM_FUNC6_START 1733 ++#define XSEM_FUNC5_END 1794 ++#define XSEM_FUNC6_START 1794 + {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f8, 0x0}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a38, 0x1003c1}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a58, 0x1003e8}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5198, 0xe}, +-#define XSEM_FUNC6_END 1736 +-#define XSEM_FUNC7_START 1736 ++#define XSEM_FUNC6_END 1797 ++#define XSEM_FUNC7_START 1797 + {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7fc, 0x0}, +- {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a78, 0x1003d1}, ++ {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a98, 0x1003f8}, + {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe}, +-#define XSEM_FUNC7_END 1739 +-#define CDU_COMMON_START 1739 ++#define XSEM_FUNC7_END 1800 ++#define CDU_COMMON_START 1800 + {OP_WR, CDU_REG_CDU_CONTROL0, 0x1}, + {OP_WR_E1H, CDU_REG_MF_MODE, 0x1}, + {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000}, + {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d}, +- {OP_WB_E1, CDU_REG_L1TT, 0x200033d}, +- {OP_WB_E1H, CDU_REG_L1TT, 0x20003e1}, +- {OP_WB_E1, CDU_REG_MATT, 0x20053d}, +- {OP_WB_E1H, CDU_REG_MATT, 0x2805e1}, ++ {OP_WB_E1, CDU_REG_L1TT, 0x2000347}, ++ {OP_WB_E1H, CDU_REG_L1TT, 0x2000408}, ++ {OP_WB_E1, CDU_REG_MATT, 0x200547}, ++ {OP_WB_E1H, CDU_REG_MATT, 0x280608}, + {OP_ZR_E1, CDU_REG_MATT + 0x80, 0x2}, +- {OP_WB_E1, CDU_REG_MATT + 0x88, 0x6055d}, ++ {OP_WB_E1, CDU_REG_MATT + 0x88, 0x60567}, + {OP_ZR, CDU_REG_MATT + 0xa0, 0x18}, +-#define CDU_COMMON_END 1750 +-#define DMAE_COMMON_START 1750 ++#define CDU_COMMON_END 1811 ++#define DMAE_COMMON_START 1811 + {OP_ZR, DMAE_REG_CMD_MEM, 0xe0}, + {OP_WR, DMAE_REG_CRC16C_INIT, 0x0}, + {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1}, +@@ -2013,24 +2074,25 @@ + {OP_WR_E1H, DMAE_REG_PXP_REQ_INIT_CRD, 0x2}, + {OP_WR, DMAE_REG_PCI_IFEN, 0x1}, + {OP_WR, DMAE_REG_GRC_IFEN, 0x1}, +-#define DMAE_COMMON_END 1757 +-#define PXP_COMMON_START 1757 +- {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x50563}, +- {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x400, 0x50609}, +- {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x50568}, +- {OP_WB_E1H, PXP_REG_HST_INBOUND_INT, 0x5060e}, +- {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x5056d}, +-#define PXP_COMMON_END 1762 +-#define CFC_COMMON_START 1762 ++#define DMAE_COMMON_END 1818 ++#define PXP_COMMON_START 1818 ++ {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x5056d}, ++ {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x400, 0x50630}, ++ {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x50572}, ++ {OP_WB_E1H, PXP_REG_HST_INBOUND_INT, 0x50635}, ++ {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x50577}, ++ {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x20, 0x5063a}, ++#define PXP_COMMON_END 1824 ++#define CFC_COMMON_START 1824 + {OP_ZR_E1H, CFC_REG_LINK_LIST, 0x100}, + {OP_WR, CFC_REG_CONTROL0, 0x10}, + {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff}, + {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a}, +-#define CFC_COMMON_END 1766 +-#define HC_COMMON_START 1766 ++#define CFC_COMMON_END 1828 ++#define HC_COMMON_START 1828 + {OP_ZR_E1, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4}, +-#define HC_COMMON_END 1767 +-#define HC_PORT0_START 1767 ++#define HC_COMMON_END 1829 ++#define HC_PORT0_START 1829 + {OP_WR_E1, HC_REG_CONFIG_0, 0x1080}, + {OP_ZR_E1, HC_REG_UC_RAM_ADDR_0, 0x2}, + {OP_WR_E1, HC_REG_ATTN_NUM_P0, 0x10}, +@@ -2049,8 +2111,8 @@ + {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, + {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, + {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, +-#define HC_PORT0_END 1785 +-#define HC_PORT1_START 1785 ++#define HC_PORT0_END 1847 ++#define HC_PORT1_START 1847 + {OP_WR_E1, HC_REG_CONFIG_1, 0x1080}, + {OP_ZR_E1, HC_REG_UC_RAM_ADDR_1, 0x2}, + {OP_WR_E1, HC_REG_ATTN_NUM_P1, 0x10}, +@@ -2069,8 +2131,8 @@ + {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, + {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, + {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, +-#define HC_PORT1_END 1803 +-#define HC_FUNC0_START 1803 ++#define HC_PORT1_END 1865 ++#define HC_FUNC0_START 1865 + {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, + {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x0}, + {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, +@@ -2086,8 +2148,8 @@ + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, +-#define HC_FUNC0_END 1818 +-#define HC_FUNC1_START 1818 ++#define HC_FUNC0_END 1880 ++#define HC_FUNC1_START 1880 + {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, + {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x1}, + {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, +@@ -2103,8 +2165,8 @@ + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, +-#define HC_FUNC1_END 1833 +-#define HC_FUNC2_START 1833 ++#define HC_FUNC1_END 1895 ++#define HC_FUNC2_START 1895 + {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, + {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x2}, + {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, +@@ -2120,8 +2182,8 @@ + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, +-#define HC_FUNC2_END 1848 +-#define HC_FUNC3_START 1848 ++#define HC_FUNC2_END 1910 ++#define HC_FUNC3_START 1910 + {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, + {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x3}, + {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, +@@ -2137,8 +2199,8 @@ + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, +-#define HC_FUNC3_END 1863 +-#define HC_FUNC4_START 1863 ++#define HC_FUNC3_END 1925 ++#define HC_FUNC4_START 1925 + {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, + {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x4}, + {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, +@@ -2154,8 +2216,8 @@ + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, +-#define HC_FUNC4_END 1878 +-#define HC_FUNC5_START 1878 ++#define HC_FUNC4_END 1940 ++#define HC_FUNC5_START 1940 + {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, + {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x5}, + {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, +@@ -2171,8 +2233,8 @@ + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, +-#define HC_FUNC5_END 1893 +-#define HC_FUNC6_START 1893 ++#define HC_FUNC5_END 1955 ++#define HC_FUNC6_START 1955 + {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, + {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x6}, + {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, +@@ -2188,8 +2250,8 @@ + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, +-#define HC_FUNC6_END 1908 +-#define HC_FUNC7_START 1908 ++#define HC_FUNC6_END 1970 ++#define HC_FUNC7_START 1970 + {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, + {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x7}, + {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, +@@ -2205,10 +2267,10 @@ + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, + {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, +-#define HC_FUNC7_END 1923 +-#define PXP2_COMMON_START 1923 +- {OP_WR_E1, PXP2_REG_PGL_CONTROL0, 0xe38340}, ++#define HC_FUNC7_END 1985 ++#define PXP2_COMMON_START 1985 + {OP_WR_E1H, PXP2_REG_RQ_DRAM_ALIGN, 0x1}, ++ {OP_WR, PXP2_REG_PGL_CONTROL0, 0xe38340}, + {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10}, + {OP_WR_E1H, PXP2_REG_RQ_ELT_DISABLE, 0x1}, + {OP_WR_E1H, PXP2_REG_WR_REV_MODE, 0x0}, +@@ -2220,7 +2282,7 @@ + {OP_WR, PXP2_REG_PGL_INT_TSDM_5, 0xffffffff}, + {OP_WR, PXP2_REG_PGL_INT_TSDM_6, 0xffffffff}, + {OP_WR, PXP2_REG_PGL_INT_TSDM_7, 0xffffffff}, +- {OP_WR, PXP2_REG_PGL_INT_USDM_1, 0xffffffff}, ++ {OP_WR_E1, PXP2_REG_PGL_INT_USDM_1, 0xffffffff}, + {OP_WR, PXP2_REG_PGL_INT_USDM_2, 0xffffffff}, + {OP_WR, PXP2_REG_PGL_INT_USDM_3, 0xffffffff}, + {OP_WR, PXP2_REG_PGL_INT_USDM_4, 0xffffffff}, +@@ -2247,6 +2309,7 @@ + {OP_WR_E1, PXP2_REG_PGL_INT_XSDM_1, 0xffff3340}, + {OP_WR_E1H, PXP2_REG_PGL_INT_USDM_0, 0xf0005000}, + {OP_WR_E1, PXP2_REG_PGL_INT_USDM_0, 0xf0003000}, ++ {OP_WR_E1H, PXP2_REG_PGL_INT_USDM_1, 0xf0008000}, + {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8}, + {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8}, + {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x8}, +@@ -2323,9 +2386,8 @@ + {OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440}, + {OP_WR_E1H, PXP2_REG_RQ_ILT_MODE, 0x1}, + {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1}, +- {OP_WR_E1H, PXP2_REG_PGL_CONTROL0, 0xe38340}, +-#define PXP2_COMMON_END 2040 +-#define MISC_AEU_COMMON_START 2040 ++#define PXP2_COMMON_END 2102 ++#define MISC_AEU_COMMON_START 2102 + {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16}, + {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000}, + {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555}, +@@ -2345,8 +2407,8 @@ + {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_1, 0x0}, + {OP_WR_E1H, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00}, + {OP_WR_E1H, MISC_REG_AEU_GENERAL_MASK, 0x3}, +-#define MISC_AEU_COMMON_END 2059 +-#define MISC_AEU_PORT0_START 2059 ++#define MISC_AEU_COMMON_END 2121 ++#define MISC_AEU_PORT0_START 2121 + {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000}, + {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000}, + {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef}, +@@ -2379,8 +2441,8 @@ + {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0}, + {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3}, + {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7}, +-#define MISC_AEU_PORT0_END 2091 +-#define MISC_AEU_PORT1_START 2091 ++#define MISC_AEU_PORT0_END 2153 ++#define MISC_AEU_PORT1_START 2153 + {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000}, + {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000}, + {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef}, +@@ -2413,7 +2475,7 @@ + {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0}, + {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3}, + {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7}, +-#define MISC_AEU_PORT1_END 2123 ++#define MISC_AEU_PORT1_END 2185 + + }; + +@@ -2512,72 +2574,63 @@ + 0x00000200, 0x00000001, 0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0x00000000, 0x00007ff8, 0x00000000, 0x00003500, +- 0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20, 0x00002000, 0x000040c0, +- 0x00006180, 0x00008240, 0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, +- 0x00012600, 0x000146c0, 0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, +- 0x0001ea80, 0x00020b40, 0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, +- 0x0002af00, 0x0002cfc0, 0x0002f080, 0x00031140, 0x00033200, 0x000352c0, +- 0x00037380, 0x00039440, 0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, +- 0x00043800, 0x000458c0, 0x00047980, 0x00049a40, 0x00008000, 0x00010380, +- 0x00018700, 0x00020a80, 0x00028e00, 0x00031180, 0x00039500, 0x00041880, +- 0x00049c00, 0x00051f80, 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, +- 0x0007b100, 0x00083480, 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, +- 0x000ac600, 0x000b4980, 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, +- 0x000ddb00, 0x00001900, 0x00100000, 0x00000000, 0x00000000, 0xffffffff, ++ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003, ++ 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, ++ 0x00000003, 0x00bebc20, 0x00002000, 0x000040c0, 0x00006180, 0x00008240, ++ 0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, 0x00012600, 0x000146c0, ++ 0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, 0x0001ea80, 0x00020b40, ++ 0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, 0x0002af00, 0x0002cfc0, ++ 0x0002f080, 0x00031140, 0x00033200, 0x000352c0, 0x00037380, 0x00039440, ++ 0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, 0x00043800, 0x000458c0, ++ 0x00047980, 0x00049a40, 0x00008000, 0x00010380, 0x00018700, 0x00020a80, ++ 0x00028e00, 0x00031180, 0x00039500, 0x00041880, 0x00049c00, 0x00051f80, ++ 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 0x0007b100, 0x00083480, ++ 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 0x000ac600, 0x000b4980, ++ 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, 0x000ddb00, 0x00001900, ++ 0x00100000, 0x00000000, 0x00000000, 0xffffffff, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x00000000, 0x00007ff8, 0x00000000, 0x00003500, 0xffffffff, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, + 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, + 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, + 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, + 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, + 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000, 0x00001500, +- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, +- 0xffffffff, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, +- 0x00000000, 0x00003500, 0x00001000, 0x00002080, 0x00003100, 0x00004180, +- 0x00005200, 0x00006280, 0x00007300, 0x00008380, 0x00009400, 0x0000a480, +- 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680, 0x0000f700, 0x00010780, +- 0x00011800, 0x00012880, 0x00013900, 0x00014980, 0x00015a00, 0x00016a80, +- 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80, 0x0001bd00, 0x0001cd80, +- 0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000, 0x00010001, 0x00000604, +- 0xccccccc1, 0xffffffff, 0xffffffff, 0xcccc0201, 0xcccccccc, 0x00000000, +- 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000, +- 0x00003500, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, ++ 0x00001000, 0x00002080, 0x00003100, 0x00004180, 0x00005200, 0x00006280, ++ 0x00007300, 0x00008380, 0x00009400, 0x0000a480, 0x0000b500, 0x0000c580, ++ 0x0000d600, 0x0000e680, 0x0000f700, 0x00010780, 0x00011800, 0x00012880, ++ 0x00013900, 0x00014980, 0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80, ++ 0x00019c00, 0x0001ac80, 0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80, ++ 0x0001ff00, 0x00000000, 0x00010001, 0x00150604, 0xccccccc1, 0xffffffff, ++ 0xffffffff, 0xcccc0201, 0xcccccccc, 0x00000000, 0xffffffff, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x00000000, 0x00007ff8, 0x00000000, 0x00003500, 0x0000ffff, + 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x00100000, + 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, ++ 0x00000000, 0x0000ffff, 0x00000000, 0x00100000, 0x00000000, 0x0000ffff, + 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x00100000, +- 0x00000000, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x30efffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, +- 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, +- 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, +- 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, +- 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, +- 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x302fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, +- 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, +- 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, ++ 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, ++ 0x00000000, 0x0000ffff, 0x00000000, 0x00100000, 0x00000000, 0xfffffff3, ++ 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, ++ 0xcdcdcdcd, 0xfffffff1, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, + 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, + 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, + 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, + 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, + 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, + 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, +- 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, +- 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x31efffff, 0x0c30c30c, ++ 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, ++ 0xcdcdcdcd, 0xfffffff5, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, ++ 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x310fffff, 0x0c30c30c, + 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, + 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, + 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +@@ -2585,41 +2638,41 @@ + 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, + 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, + 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x056fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, +- 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, +- 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, ++ 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x30efffff, 0x0c30c30c, ++ 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, ++ 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, ++ 0xcdcdcdcd, 0xfffffff3, 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, + 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, + 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, + 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, + 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, + 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffff8a, +- 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0010cf3c, +- 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, ++ 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, ++ 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, ++ 0xcdcdcdcd, 0xffffff97, 0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, + 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, + 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, +- 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, +- 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, ++ 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, ++ 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, + 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, + 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, + 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, + 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, +- 0x040fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, +- 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, +- 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, +- 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, +- 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, +- 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, +- 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, +- 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, +- 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, ++ 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffff8a, 0x042fffff, 0x0c30c30c, ++ 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, ++ 0x05cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, ++ 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, ++ 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x300fffff, 0x0c30c30c, ++ 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, ++ 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, ++ 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, ++ 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, ++ 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, ++ 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, ++ 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, ++ 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x040fffff, 0x0c30c30c, ++ 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, ++ 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, + 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, + 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, + 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, +@@ -2641,16 +2694,26 @@ + 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, + 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, + 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, +- 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x00100000, 0x00070100, 0x00028170, +- 0x000b8198, 0x00020250, 0x00010270, 0x000f0280, 0x00010370, 0x00080000, +- 0x00080080, 0x00028100, 0x000b8128, 0x000201e0, 0x00010200, 0x00070210, +- 0x00020280, 0x000f0000, 0x000800f0, 0x00028170, 0x000b8198, 0x00020250, +- 0x00010270, 0x000b8280, 0x00080338, 0x00100000, 0x00080100, 0x00028180, +- 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298, 0x00080380, 0x00028000, +- 0x000b8028, 0x000200e0, 0x00010100, 0x00008110, 0x00000118, 0xcccccccc, +- 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, +- 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, +- 0xcccccccc, 0x00002000 ++ 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, ++ 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, ++ 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, ++ 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, ++ 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, ++ 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, ++ 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, ++ 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, ++ 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, ++ 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, ++ 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, ++ 0xcdcdcdcd, 0x00100000, 0x00070100, 0x00028170, 0x000b8198, 0x00020250, ++ 0x00010270, 0x000f0280, 0x00010370, 0x00080000, 0x00080080, 0x00028100, ++ 0x000b8128, 0x000201e0, 0x00010200, 0x00070210, 0x00020280, 0x000f0000, ++ 0x000800f0, 0x00028170, 0x000b8198, 0x00020250, 0x00010270, 0x000b8280, ++ 0x00080338, 0x00100000, 0x00080100, 0x00028180, 0x000b81a8, 0x00020260, ++ 0x00018280, 0x000e8298, 0x00080380, 0x00028000, 0x000b8028, 0x000200e0, ++ 0x00010100, 0x00008110, 0x00000118, 0xcccccccc, 0xcccccccc, 0xcccccccc, ++ 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, ++ 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000 + }; + + static const u32 init_data_e1h[] = { +@@ -2751,11973 +2814,13327 @@ + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0x00007ff8, +- 0x00000000, 0x00003500, 0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20, +- 0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20, +- 0x00000003, 0x00bebc20, 0x00002000, 0x000040c0, 0x00006180, 0x00008240, +- 0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, 0x00012600, 0x000146c0, +- 0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, 0x0001ea80, 0x00020b40, +- 0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, 0x0002af00, 0x0002cfc0, +- 0x0002f080, 0x00031140, 0x00033200, 0x000352c0, 0x00037380, 0x00039440, +- 0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, 0x00043800, 0x000458c0, +- 0x00047980, 0x00049a40, 0x00008000, 0x00010380, 0x00018700, 0x00020a80, +- 0x00028e00, 0x00031180, 0x00039500, 0x00041880, 0x00049c00, 0x00051f80, +- 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 0x0007b100, 0x00083480, +- 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 0x000ac600, 0x000b4980, +- 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, 0x000ddb00, 0x00001900, +- 0x00000028, 0x00000000, 0x00100000, 0x00000000, 0x00000000, 0xffffffff, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000, 0x00001500, ++ 0x00000000, 0x00001500, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, ++ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, ++ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003, ++ 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, ++ 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, ++ 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, ++ 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000, ++ 0xffffffff, 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, ++ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, ++ 0x00002000, 0x000040c0, 0x00006180, 0x00008240, 0x0000a300, 0x0000c3c0, ++ 0x0000e480, 0x00010540, 0x00012600, 0x000146c0, 0x00016780, 0x00018840, ++ 0x0001a900, 0x0001c9c0, 0x0001ea80, 0x00020b40, 0x00022c00, 0x00024cc0, ++ 0x00026d80, 0x00028e40, 0x0002af00, 0x0002cfc0, 0x0002f080, 0x00031140, ++ 0x00033200, 0x000352c0, 0x00037380, 0x00039440, 0x0003b500, 0x0003d5c0, ++ 0x0003f680, 0x00041740, 0x00043800, 0x000458c0, 0x00047980, 0x00049a40, ++ 0x00008000, 0x00010380, 0x00018700, 0x00020a80, 0x00028e00, 0x00031180, ++ 0x00039500, 0x00041880, 0x00049c00, 0x00051f80, 0x0005a300, 0x00062680, ++ 0x0006aa00, 0x00072d80, 0x0007b100, 0x00083480, 0x0008b800, 0x00093b80, ++ 0x0009bf00, 0x000a4280, 0x000ac600, 0x000b4980, 0x000bcd00, 0x000c5080, ++ 0x000cd400, 0x000d5780, 0x000ddb00, 0x00001900, 0x00000028, 0x00100000, ++ 0x00000000, 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, ++ 0x00007ff8, 0x00000000, 0x00001500, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, +- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, +- 0xffffffff, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, +- 0x00000000, 0x00003500, 0x00001000, 0x00002080, 0x00003100, 0x00004180, +- 0x00005200, 0x00006280, 0x00007300, 0x00008380, 0x00009400, 0x0000a480, +- 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680, 0x0000f700, 0x00010780, +- 0x00011800, 0x00012880, 0x00013900, 0x00014980, 0x00015a00, 0x00016a80, +- 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80, 0x0001bd00, 0x0001cd80, +- 0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000, 0x00010001, 0x00000604, +- 0xccccccc5, 0xffffffff, 0xffffffff, 0xcccc0201, 0xcccccccc, 0xcccc0201, +- 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, +- 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, +- 0xcccccccc, 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, +- 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, +- 0x00007ff8, 0x00000000, 0x00003500, 0x00100000, 0x00000000, 0x00100000, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, +- 0x00000000, 0x0000ffff, 0x00000000, 0xfffffff3, 0x320fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, +- 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, +- 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, +- 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, +- 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, +- 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, +- 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, +- 0xcdcdcdcd, 0xfffffff3, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, +- 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, +- 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, +- 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, +- 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, +- 0xcdcdcdcd, 0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, +- 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, +- 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, +- 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, +- 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, +- 0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, +- 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, +- 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, +- 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, +- 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, +- 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, +- 0xcdcdcdcd, 0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, +- 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, +- 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, +- 0xcdcdcdcd, 0xfffffff3, 0x31afffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, +- 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, +- 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, +- 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, +- 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, +- 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, +- 0xcdcdcdcd, 0xffffff97, 0x058fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, +- 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, +- 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, +- 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, +- 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, +- 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, +- 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, +- 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, +- 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, +- 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, +- 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, +- 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, +- 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, +- 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, +- 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, +- 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, +- 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, +- 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, +- 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, +- 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, +- 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, +- 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, +- 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, +- 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, +- 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, +- 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, +- 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x00100000, +- 0x00070100, 0x00028170, 0x000b8198, 0x00020250, 0x00010270, 0x000f0280, +- 0x00010370, 0x00080000, 0x00080080, 0x00028100, 0x000b8128, 0x000201e0, +- 0x00010200, 0x00070210, 0x00020280, 0x000f0000, 0x000800f0, 0x00028170, +- 0x000b8198, 0x00020250, 0x00010270, 0x000b8280, 0x00080338, 0x00100000, +- 0x00080100, 0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298, +- 0x00080380, 0x000d0000, 0x000000d0, 0x000280d0, 0x000b80f8, 0x000201b0, +- 0x000101d0, 0x000c81e0, 0x000002a8, 0xcccccccc, 0xcccccccc, 0xcccccccc, +- 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, +- 0x00002000 ++ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x00000000, 0x00007ff8, 0x00000000, 0x00001500, 0x00001000, ++ 0x00002080, 0x00003100, 0x00004180, 0x00005200, 0x00006280, 0x00007300, ++ 0x00008380, 0x00009400, 0x0000a480, 0x0000b500, 0x0000c580, 0x0000d600, ++ 0x0000e680, 0x0000f700, 0x00010780, 0x00011800, 0x00012880, 0x00013900, ++ 0x00014980, 0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80, 0x00019c00, ++ 0x0001ac80, 0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80, 0x0001ff00, ++ 0x00000000, 0x00010001, 0x00150604, 0xccccccc5, 0xffffffff, 0xffffffff, ++ 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, ++ 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, ++ 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0x00000000, 0xffffffff, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000, 0x00003500, ++ 0x00100000, 0x00000000, 0x00100000, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x30efffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, ++ 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, ++ 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, ++ 0xfffffff7, 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x302fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x310fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, ++ 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, ++ 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, ++ 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x30efffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, ++ 0xfffffff5, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x31efffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, ++ 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, ++ 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, ++ 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x056fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, ++ 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, ++ 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, ++ 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffff8a, 0x042fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, ++ 0xffffff97, 0x05cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, ++ 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x316fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, ++ 0xfffffff1, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffffff6, 0x30bfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf314, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, ++ 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, ++ 0xfffffff0, 0x307fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0040cf3c, 0xcdcdcdcd, 0x00100000, 0x00070100, 0x00028170, 0x000b8198, ++ 0x00020250, 0x00010270, 0x000f0280, 0x00010370, 0x00080000, 0x00080080, ++ 0x00028100, 0x000b8128, 0x000201e0, 0x00010200, 0x00070210, 0x00020280, ++ 0x000f0000, 0x000800f0, 0x00028170, 0x000b8198, 0x00020250, 0x00010270, ++ 0x000b8280, 0x00080338, 0x00100000, 0x00080100, 0x00028180, 0x000b81a8, ++ 0x00020260, 0x00018280, 0x000e8298, 0x00080380, 0x000b0000, 0x000100b0, ++ 0x000280c0, 0x000580e8, 0x00020140, 0x00010160, 0x000e0170, 0x00038250, ++ 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, ++ 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, ++ 0xcccccccc, 0xcccccccc, 0x04002000 + }; + + static const u32 tsem_int_table_data_e1[] = { +- 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x19d9b38a, 0x22717618, +- 0xa70143f8, 0xa4303332, 0x10267103, 0x97e204af, 0xaf0c0c8c, 0x2fd78918, +- 0xcf608621, 0x38606610, 0x4206c402, 0x22450c0c, 0xa07af108, 0xfe407b9a, +- 0xb698a842, 0x76c30328, 0x3bf781d1, 0x34957035, 0x24a458a6, 0x458d5d82, +- 0xa0d7191e, 0x4494efc9, 0xd012d7e5, 0x4538d03f, 0x513f9509, 0x547f4201, +- 0x342fa684, 0xf95049f9, 0xa57f5039, 0x77376129, 0x001e542e, 0x61aa8a92, ++ 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x19d8c58a, 0x1138fc18, ++ 0x5980a1fc, 0xd8181998, 0x88039880, 0x81b8803d, 0x91a18191, 0x57fd7891, ++ 0x6f6c1144, 0x72860661, 0xc82d3e20, 0x8229a0c0, 0x6313b710, 0xe40a9860, ++ 0x1ec54047, 0x517ce903, 0xa07fb8ea, 0xa6349471, 0x8224a598, 0x1e458d1d, ++ 0xc9a0c719, 0xe54494cf, 0x3fd012c7, 0x12af78d0, 0x02a1ff2a, 0x8a84f684, ++ 0x7f9343ef, 0x81af9504, 0x12bf6bfa, 0xa16b7376, 0xc73200f2, 0x0360ecb6, + 0x00000360 + }; + + static const u32 tsem_pram_data_e1[] = { +- 0x00088b1f, 0x00000000, 0x7dedff00, 0xd554780b, 0x733ef0b5, 0x49999cce, +- 0x204e4cce, 0x30840909, 0x43511879, 0x7c061e1c, 0x201276f4, 0x06bf2ae5, +- 0x0ea2a17c, 0x2de42108, 0xebf8fea5, 0x092132fd, 0xf636c544, 0xda2f45a2, +- 0x05a855e1, 0xa180d03b, 0x4a00ee05, 0x7836daa1, 0xf5ab15bd, 0x62a2968e, +- 0x96ad2248, 0xbfcb17fe, 0x24fbdad6, 0x00664e73, 0xbbf7bdcb, 0x9fa7efd7, +- 0xece7d9dd, 0xebdaf7b3, 0x7b5ad7b5, 0x5d8a3ded, 0x19d7ea62, 0xa0ff873b, +- 0xc631b3ec, 0x9f2c19ae, 0x23a57cc8, 0x6ad8cbd7, 0x3127d43b, 0x0f623c16, +- 0x5b18926d, 0xb59fda32, 0x71ca0d30, 0xbc20be69, 0xebe16767, 0xc654c612, +- 0x9b4aadff, 0xe8f2c994, 0xf073b9f9, 0xf30f81dc, 0x58564b19, 0x63026530, +- 0xafcc6c2b, 0x8fba830f, 0xfc9c0fb1, 0x7ff8739b, 0xf61b24c1, 0xbf874233, +- 0xaf3edfa1, 0x814f682d, 0xedcdb37e, 0x1215494e, 0xd5db1993, 0x140bd2c4, +- 0x9c9abac6, 0x49b4fe54, 0x60282f4f, 0x26534f6c, 0x7935f7d5, 0x8d348ca9, +- 0x9a07e7a5, 0xb34f547c, 0xf7e3d7f5, 0x2b7c8e23, 0xce0d1595, 0x68ae5adf, +- 0x060b7182, 0x64cc7feb, 0xf9e00541, 0xafeec2a3, 0x5f9aef80, 0x8512989f, +- 0x802c99f2, 0xf7e86536, 0x45fb2ecf, 0x8ce1b4fe, 0x387c3d65, 0x6844da7f, +- 0xe139b127, 0x87459c22, 0xe25c6b34, 0x77b19f71, 0xcdc032a4, 0x6991802d, +- 0xb9b58c99, 0x4f2e6ffa, 0x44f5cc65, 0x0b9a7fb6, 0x5d0cdde6, 0x2eec648c, +- 0xde0c1056, 0xf81ffd00, 0xe80525b8, 0x614976a1, 0x4b26cd78, 0xd012cd15, +- 0x7ccedd8b, 0xa538709b, 0xd41479a2, 0xde60eefb, 0xe383bdc7, 0x9880c5dc, +- 0x46ccd8e9, 0x32a864e5, 0xa5dd87e8, 0xe2e53686, 0x15c5fd87, 0x2fb712e3, +- 0xd517f839, 0xf6f1a6eb, 0x078d328f, 0x7f13b9df, 0xcbe07597, 0xaef7d77d, +- 0x78842332, 0xe11f9853, 0xc657753b, 0xde25c7ba, 0x7d8f163e, 0xc70aab2a, +- 0x8e1567a1, 0x66dcfc0b, 0x367b74e7, 0xb18d4a17, 0x16663835, 0x9c62b563, +- 0x03d95a29, 0x3000b258, 0xb58cb5e7, 0xdda0bd20, 0x3abf6894, 0xdf4ae00f, +- 0x852a4b33, 0x0af1fa7a, 0xf2115e69, 0x10cf41a1, 0xb1259ff5, 0x9ef81d8a, +- 0x70ca92cd, 0xe71f3b1c, 0x8b50fe86, 0xe86ee007, 0xec9eddca, 0x6194fde5, +- 0x48553fbb, 0x3858b5f3, 0x7a4fd4bd, 0xdf038c17, 0x38c0f7a7, 0xa56b3ef0, +- 0xfe69bac4, 0xe1a614de, 0x32c67e78, 0x70a6a440, 0xa8d99099, 0x7867e424, +- 0xfc8165ae, 0x3f2e3364, 0x8be635a7, 0x9f737e00, 0xd0d47cd4, 0x783579ab, +- 0x69c85a3f, 0x266aa076, 0x01b630f3, 0x530593d0, 0x7ca8dd1e, 0xb3918d10, +- 0xcda37331, 0x9663fa28, 0x997b9f99, 0x9cf286d7, 0xcf3f341b, 0xbfd7376f, +- 0x2769dccd, 0xdc3f82ae, 0x8e4e7dcc, 0xc0e38f33, 0x12cf00d4, 0x6fc0ef21, +- 0xadbf2c6a, 0x5a19626d, 0x91396241, 0x5dce1c96, 0xb7687a89, 0xf7c073e4, +- 0x907b602f, 0x6ef890ef, 0x05d7a8bd, 0x0d5d8555, 0x1e282025, 0x958afc7f, +- 0x1fba406e, 0x101b6567, 0xbf4a0dff, 0x0d7c03aa, 0xa43faa8d, 0x17bf6d0d, +- 0xd7db1118, 0x4e03be2b, 0x99bfbf18, 0xf8c3d6f9, 0x197aec4b, 0xec3c97d6, +- 0xd798bd25, 0x7e472d1e, 0xea05d31d, 0xfbf0772a, 0x2767808b, 0xecf001c2, +- 0x97f4e3e4, 0xdfedfea3, 0xb9f5b12b, 0x77ef0e38, 0x165ceec9, 0xe70c4dcc, +- 0xfc4ecc73, 0xbc0b40b4, 0x267ee582, 0x02c62729, 0x83cc3d9a, 0xcaa968f4, +- 0x54394efb, 0xe9f7c69f, 0xf9ccf583, 0x00033233, 0x6618d657, 0xb3a557a2, +- 0x7af50731, 0x1cb84575, 0x25c3e2f9, 0x12c0acaf, 0x00ae9cf0, 0x2a388fbe, +- 0xea7ec75e, 0xa21636e6, 0xe870edc8, 0x7b1afe34, 0x7237d647, 0x1fa50f11, +- 0xd06fc02b, 0x1865306d, 0xff4595f2, 0xc60fbfc3, 0x989cba8a, 0x172a17ee, +- 0xe20a3f60, 0xf59fcb8d, 0x0f4207fd, 0xf8261e81, 0x957ecbbc, 0xb63c305f, +- 0xc17e7afe, 0x09500144, 0x13f0cbc1, 0x4552a2c6, 0x663dbd1c, 0xa561e977, +- 0xff3c3138, 0x7404f3d9, 0x001a7cd2, 0x7527c8b7, 0x1cb4356e, 0xa7753df0, +- 0xe075f23d, 0x5275ba93, 0xdb7501c8, 0xefbd173e, 0x11ebcb5d, 0xe9f5cab7, +- 0x0a83a846, 0x7f74706c, 0xb3e47afb, 0x8f5b329d, 0xf5858edd, 0x09ccf418, +- 0xc49b3b01, 0x174ae7d7, 0xdbadd6af, 0x5f7e1f7f, 0x2e60e5d5, 0xf76eafe8, +- 0x87af9ba2, 0x76c3a2fa, 0x36ea4d86, 0xa123ab35, 0xd7c438be, 0x0e32bea5, +- 0x4c97705f, 0xa79f4beb, 0xa076e33b, 0x2726c9cf, 0xd0f182f3, 0xb8ceeee2, +- 0x3aadf80d, 0xbf1cbdb4, 0xf92adeab, 0x7753ed10, 0x85943a6e, 0x9721faf3, +- 0xc92d9af3, 0x0fe06bcc, 0x29d13bfe, 0xef0ebe47, 0x193cc097, 0x7588bbf4, +- 0xac3ea394, 0xad14f4db, 0x4ebe0633, 0xce34e936, 0x10fe1c80, 0xeaef81c6, +- 0x387c925f, 0x0b1b7ac5, 0xeef63ca0, 0xa0d9cd76, 0xd59afce1, 0x6bce3742, +- 0x16ed8aa5, 0x72ede685, 0x75be1179, 0xafbc396a, 0xad4ebb5e, 0x9adf918c, +- 0x70cdc32d, 0x111fc9ad, 0x717d8f38, 0x6f0bec12, 0x1abd60e1, 0x45ea01f5, +- 0xaec6a425, 0xa9496f6b, 0x2d9adf44, 0xf89af332, 0xf83dd388, 0xedd68caf, +- 0x5f375ee0, 0x06dd05b7, 0xdba0aaf4, 0x51d05d69, 0x67892fe9, 0xe91b7c7f, +- 0x2074f000, 0x255ca09e, 0xc0dcf3e0, 0xdfe8154a, 0x2e3a67e3, 0xcbe217bb, +- 0xc79b3b0e, 0xcd39ac60, 0xac0afd9b, 0x7b2a1da3, 0xef99ed10, 0xd3fd86b6, +- 0x966dbd60, 0x8025b302, 0xaa05b65b, 0xce15baf8, 0x857f75c4, 0x946f6f58, +- 0x15af34bc, 0x809fc059, 0x25e98ef7, 0xc049641b, 0xcaf5869e, 0x4b9e3c1f, +- 0xfd43dcfd, 0xfe4fd0a8, 0xcbd1fb85, 0xd1fa98a7, 0x7e8cabcb, 0x493f5016, +- 0x474fd717, 0x786675f9, 0x7e8dabca, 0xcf1fa8ea, 0xff4bcdc5, 0x78660dc6, +- 0xfd4b51be, 0xb1f34ea4, 0xbaeb8680, 0xedd607e0, 0xb6bde197, 0xe3c27535, +- 0xca2f962c, 0xdcf1c61e, 0x7cb12520, 0xc9253291, 0xfea987c4, 0xf43aa661, +- 0x2cbad3a4, 0xe3df8ff4, 0x4754b924, 0x4a17a4aa, 0x9e093a47, 0xa46a4687, +- 0x2eba1e17, 0x87ae3970, 0x4bda3638, 0xab81a90f, 0x0d7c38f5, 0x132c4a70, +- 0x320fb04b, 0x695fbe87, 0x1b2878e7, 0x7df0b675, 0xd6c1bef8, 0xf50a985f, +- 0x3fe95b36, 0x959e3ce2, 0x24969db8, 0x976c46b3, 0xdef6e0e4, 0x0d92dcca, +- 0xb53c18c1, 0x4bfa068f, 0xdbb6fd83, 0x5fc89903, 0x0ebf4bcf, 0x18adbf22, +- 0xfc7d92ad, 0x22aff342, 0x2b8fd041, 0x22665747, 0xc82a1d3e, 0x2af8ec77, +- 0xe3445f8c, 0x7ff1c06f, 0x477c6098, 0xf8d314de, 0xd32a9cce, 0xc6154ef8, +- 0x26df7e07, 0x07c625bd, 0xd8c75dfc, 0xa1bfcd4b, 0x55391df1, 0xb44afe34, +- 0x4fc7634f, 0x27ff181a, 0x5bbb8c12, 0x90d2ebe2, 0x675de7f9, 0xb54e7f9e, +- 0x9f2afe79, 0xdfe95eff, 0x3449f8c4, 0xefcd7dff, 0x54e7f9f1, 0x783bf9f3, +- 0x7be303bf, 0x107ff006, 0xd1247fe7, 0x306ff3fc, 0xad4c7fcf, 0x3e0efe79, +- 0x0fa52ffe, 0x8d1af8c5, 0x13e6abff, 0x6a63fe7c, 0x11d57c69, 0xa91f21f0, +- 0xc91a92a3, 0xed06cf9e, 0x94748234, 0xdcb1ca9f, 0xf2976eee, 0x250f0f08, +- 0x3cfbbe71, 0x1b4df809, 0x042c77d4, 0xacfa0512, 0xcd7cf05e, 0x503552d6, +- 0xde83de24, 0x5d40285b, 0x5f1325d0, 0xd08ed5b3, 0x6f6f0065, 0xfac41c97, +- 0x0b5fd582, 0x71deb4c9, 0xb9cc007f, 0xc3ff3e08, 0xc7d6e3d3, 0x2e5acbce, +- 0x889fb0ec, 0xc388e49a, 0x63632c13, 0x6bbe011b, 0x67f09d25, 0x1e804fd4, +- 0x3f3fa065, 0xe58a3d00, 0x381fc287, 0xa9967a0e, 0x4cd372b1, 0x6f7741df, +- 0xeebcc116, 0x509ff010, 0x2c4fbe38, 0xff884295, 0x507a9fcf, 0xb0b4fd45, +- 0x3e901923, 0xa0834708, 0x476eff53, 0xf844bd68, 0xee7e22f4, 0xec645124, +- 0x5fbec277, 0xe9b866b4, 0xd42cb9bb, 0x1fed0996, 0xb46f3558, 0x67bff30e, +- 0x4c82638e, 0x947f9f7e, 0x8d98e48d, 0x318f81b2, 0xfb29f3a7, 0x39dca828, +- 0xefb26ec7, 0xeb980aef, 0xeb9954f7, 0xdd90f6bd, 0x62c6f686, 0x7e83ad89, +- 0xbf346def, 0xdbb1c637, 0x8c7b0986, 0x0647778f, 0x2c5ef787, 0x9d63e027, +- 0xce9f7ae8, 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0x1f137dc3, 0xaeb8c1e0, 0xd394a031, +- 0x56bc5db9, 0xf87a8954, 0x0779da69, 0x4fb4dfe9, 0x0772950e, 0x4327dbca, +- 0xbeecc1d4, 0xaf2577c1, 0x77da4e2a, 0x0fdc5ee2, 0x870aa871, 0x5c38ed9b, +- 0x493916d3, 0x6fe956b4, 0xa73a11c6, 0x12e9f89e, 0xbe91d6a6, 0x38cf3327, +- 0x37fe603e, 0x2333b75f, 0x313f1d2e, 0xde8170fc, 0x7f8a430c, 0xf8b89d75, +- 0x1e303ff9, 0x247b4d76, 0xec7f5e9a, 0x26f06e99, 0x3ab30afd, 0xfd30dc4b, +- 0x19c86eac, 0x85bcd813, 0xc6fcd2f7, 0x14c52333, 0xd1186f6f, 0x42dc30fa, +- 0x02d9f8e2, 0x7b8ddedd, 0xfb82fe41, 0x8b42f73a, 0xb8c74a80, 0x1088f9bf, +- 0x9b5ca275, 0xda304f29, 0x743fb62a, 0xd0649da1, 0x8f93d97c, 0xe437ad72, +- 0x83fe1cea, 0x6d3a8303, 0x1bbc92a3, 0xefd7fe0c, 0xca66fbb9, 0xed4436fb, +- 0xdf8ef8c9, 0x36e891f6, 0x90fdbbe2, 0x21229fb5, 0xac65dfc9, 0xabbca0ef, +- 0xeb37f298, 0xfc782ebc, 0xba97145f, 0x9bfdac86, 0x4c39e902, 0x063dc60f, +- 0x9f78be46, 0xa3e48731, 0x71f379bc, 0xb289d447, 0x2ddbde6d, 0xe85da8f9, +- 0xdd1c5891, 0x5bb328f3, 0xc9ec3e73, 0xfa623666, 0xc01d86e7, 0xc71360f2, +- 0x329c07a5, 0x81e963e9, 0x62df963c, 0x0af2ce5e, 0xcecc138c, 0x1c262297, +- 0x990bddda, 0xcf1e4153, 0x9978e179, 0xcbf37944, 0x6f78655b, 0x333f9241, +- 0x0e116f6f, 0x3ed03b37, 0x1f01efa6, 0x50357de5, 0xae0374f6, 0x87653eab, +- 0x834f8e28, 0x0be98fae, 0xebbfcb3c, 0x64fd2b86, 0x231cc207, 0x4f31f86e, +- 0x2dc3c14f, 0x253101ce, 0x75f135cf, 0x2b4b7a1a, 0xa78cb2cb, 0xeb2cf34b, +- 0xd6836a33, 0x0f1caaf5, 0xd69c50d5, 0x8bca67d7, 0xc341f32c, 0x306f1c3f, +- 0x5deedbe0, 0xb7ec8a71, 0x66feb3d1, 0x657b29c2, 0x53be6585, 0xff102638, +- 0x2cda9f0d, 0x8426fc7a, 0xce51d39b, 0x0f31b7da, 0xc6ea73c1, 0x4d6ee3ad, +- 0x7ee75a05, 0xa01f253b, 0x7b6b44fd, 0xf987b4c0, 0x1ed53f30, 0xae7b7892, +- 0x50f649e0, 0x782c0b03, 0x0aebc4cf, 0xf3071efe, 0x6ee1ba87, 0xd86e5fc6, +- 0x9b5e7b8a, 0xc57cf715, 0x7ac1738a, 0x1185ce2b, 0xf5d7ce2b, 0xa80d7158, +- 0x778adc56, 0x5fe659d4, 0x6964dfdf, 0x655aee97, 0xba30bf99, 0x7c5ed2da, +- 0xfccb76e8, 0x59770325, 0x6d0e97c6, 0xf69b8cb4, 0xdfff5335, 0x619e6d88, +- 0x5ff03c5f, 0x53caffa2, 0x99ce590f, 0x888077a9, 0x6bd6f840, 0x5703bb00, +- 0xedfabdeb, 0x578af07e, 0x0f029deb, 0xf5339de5, 0xa7fa453f, 0xffe86f38, +- 0xc629d233, 0x17bd37b9, 0xfd37271e, 0xcf1e9a6e, 0xb886845a, 0xb06d7a4c, +- 0xcfeb7ab3, 0x3a737662, 0x1ee303c5, 0x18f71b0b, 0xecc1dfac, 0xdbd3ec21, +- 0x493a5c52, 0x5ce2ac71, 0xaaf899b8, 0x512722d2, 0xd0b9a84c, 0xf3419cdf, +- 0x387d1065, 0xfaf0339f, 0x36072d5e, 0x7b613f8b, 0x5bcf126e, 0x03215ed4, +- 0x8a5fd727, 0x4b30b1f6, 0xbf9e0ec5, 0x6ae718da, 0x55a27bf5, 0x052d8376, +- 0xf35ac697, 0xfe3108fe, 0x316ffc4c, 0xe7cc08ea, 0x3cf941c1, 0x05f68aef, +- 0xa45fcb66, 0xafcb025d, 0xbd6f9614, 0xa27629ce, 0x22f15c6b, 0x9e4aeb8a, +- 0xb8882f32, 0xc892f24d, 0xeb4e33f2, 0x2412a123, 0x6a565d18, 0x754cab66, +- 0x30a39618, 0xd19f290f, 0xfb187aaa, 0x2f46ad3e, 0x1253e97b, 0x18838a54, +- 0xdf394717, 0xfb5c4ab6, 0x45c7dd66, 0xca2d6f74, 0xff501790, 0x3c8ef795, +- 0xabe30b94, 0x412a8bc6, 0xb1c43ea0, 0xda63e1fa, 0xdf8a5964, 0x7bb3b0ee, +- 0x6a7a8c0a, 0x599381ad, 0x9c61dd4f, 0xac5b8a3b, 0x76bdf8c7, 0x478675e8, +- 0xd59c7fbb, 0x926f689f, 0x7bbff70f, 0xea82a7be, 0x252b9049, 0xeb370ebd, +- 0x7fe102ab, 0x7acd47b9, 0xdbf35af4, 0x752c17fd, 0xefd61c2e, 0xafef6b97, +- 0xca4d7b32, 0xfa3fefad, 0x77bb1a58, 0x6c2b1f46, 0x7fdc9a22, 0x36bfed92, +- 0x3ec596f2, 0xbbf9ecee, 0xa47eeec5, 0xd7196bbe, 0x05eca672, 0x3476bf28, +- 0x100fc57f, 0xce2389bf, 0x5133aa1a, 0xa60fdf5f, 0x13dac1d4, 0xbce9cba5, +- 0x3fe72eff, 0x5b23be19, 0x905b60e3, 0xd6fcf394, 0x6dadac73, 0x299d18d5, +- 0x9a9759a7, 0x287bf1d4, 0xa67ea1b3, 0x6cd239b8, 0x41232cef, 0xb91f6f3d, +- 0xdd136e71, 0x0e8523bf, 0xf44b4e9b, 0x4bad7e76, 0x4958af6f, 0xecf76134, +- 0x8474baa0, 0x7b439903, 0xf9f79d18, 0x516e0701, 0x403ca797, 0xa69a2672, +- 0x2977a73e, 0x288ad1c8, 0x2a664c9e, 0x873f520f, 0x167e5fc9, 0xf284b3e3, +- 0xfabc0bff, 0x7018c06b, 0xad6ddf60, 0x7a4fd794, 0x647fbb75, 0x2aad2ddf, +- 0x199952e2, 0x40eb4ade, 0x917bd8d6, 0x8ef9afc9, 0xd52f7542, 0x4eb70921, +- 0x263907b7, 0x74198eff, 0x28d4d537, 0x1d064bdf, 0x384afbe5, 0x4edd87f2, +- 0x7e601fd8, 0x315e5320, 0xfba9cc7d, 0x8bc00d81, 0x711defe3, 0x3cf6473e, +- 0xbca67917, 0x9633b305, 0xcefc57ff, 0x6138a319, 0x14e4bfbe, 0xe10b3f8b, +- 0xec979cfa, 0x4c9fceac, 0xbfc86b17, 0xb2afbd3b, 0xa0a6ebbc, 0x40e4c032, +- 0x8c7e2849, 0xdbee751e, 0x2a4dfcc9, 0x7ffe9d5a, 0x103b677d, 0xa68c7564, +- 0x3bc691e7, 0x8b77299b, 0x7b9338f0, 0x4813977a, 0xe37b89ce, 0xbbd8854f, +- 0x7c445492, 0xdf3af28e, 0x7ca6bf26, 0x7dc91ca6, 0xcd6edcbe, 0x7be4a2f7, +- 0xf212f6d6, 0x7f51c403, 0x3bb813c7, 0xfeb2cf57, 0x9aabe90c, 0xa09da7bd, +- 0xa231b638, 0xf525a7bf, 0x3bc0ffde, 0x0f61b7a4, 0x5ad7638b, 0xcece533f, +- 0x0f0cc313, 0x2487f394, 0xa79c8a5f, 0x7eef2983, 0x3ecfc713, 0xbebf1215, +- 0x38c2897c, 0x3c4cdf7b, 0xc448b177, 0x5ec79df5, 0xd276473f, 0x33ffd469, +- 0x739da9df, 0x9acc7eb0, 0x6f1a7ded, 0xc97c9485, 0x6f9fae69, 0x04c7aeb3, +- 0x886cfc99, 0x0af291fc, 0x5e2927bc, 0x8be4f79b, 0x69c19d46, 0x4d78b1af, +- 0x6efd91e7, 0x5f7654e3, 0x7d05ef99, 0x5447de1c, 0x2cdd2b97, 0x79d70b8e, +- 0x17cfb224, 0x74e306d1, 0x34e4d8ff, 0xa33c2ef6, 0x54e79d8e, 0xd93b253e, +- 0x1e5356f2, 0x6f83b9d5, 0x27ea32ac, 0x36a91efd, 0xce9ab2ec, 0x1943fe27, +- 0x32a93eec, 0x4571abf8, 0x0cbade58, 0x177f4154, 0x1e19de30, 0x7752cd7b, +- 0xa2bf07fd, 0x17f0846b, 0x000017f0 ++ 0x00088b1f, 0x00000000, 0x7dedff00, 0xd5547c0f, 0xf37df095, 0x4999bcde, ++ 0x425e4cde, 0x60109212, 0x85444092, 0xa88bfc30, 0x10909db8, 0xc075b569, ++ 0x1daad07f, 0xff908420, 0xa5ba5522, 0x8126265f, 0x1761a888, 0x03a8ba2d, ++ 0x358a8b42, 0x168681d0, 0xb88200ec, 0xbac1bbb5, 0x46ebab16, 0x921888a5, ++ 0x57f15588, 0xe739dfad, 0x379997de, 0x6ed40199, 0xbf7efd7f, 0x737b5d8f, ++ 0xdeefbbdf, 0x7bbfcf73, 0xdee7b9ce, 0xa60cd451, 0x2fb1837e, 0xff941ff0, ++ 0x4d8c6162, 0x5b0f948b, 0x1a7df7d9, 0x0c9c5763, 0xc674aec8, 0x76f2ba1a, ++ 0xcb19bb24, 0x9a473bd8, 0x7a33cf09, 0x2d42d27d, 0x0e4bfdf2, 0xdfff097c, ++ 0x192a4735, 0x9f71e50f, 0xecca00b4, 0x86eb12d5, 0x14ee2992, 0xf319ed06, ++ 0x58c99632, 0xff4674c1, 0x09223664, 0x6b9f07fe, 0xe58cc5d9, 0xd5d09fe2, ++ 0xc2798d19, 0xbbcb1953, 0x4350f34f, 0xe0d6e6b7, 0x19fe48fd, 0x5d57f5cb, ++ 0x3d8c5ccb, 0xa766f001, 0xe546f3c1, 0x7f3b1eed, 0x37fc05f7, 0x669e96fa, ++ 0xcc2b962b, 0x6dccddcf, 0x6fd00561, 0xa0bcfcc0, 0x642f5cdd, 0xc913f4ce, ++ 0x399387f0, 0xcce390bf, 0x632a78e3, 0x9d32cf00, 0x80d8cbc3, 0xc1109bea, ++ 0x9626c6c7, 0xd4898da9, 0xd9694b63, 0x80d5bc91, 0x247b65d7, 0x7fbe0d8f, ++ 0x8c2bdb0c, 0x9b77c505, 0xa02ebd45, 0x94226c2a, 0xf1cea080, 0xcc59fb43, ++ 0xbc44ae4a, 0xa4cd88ff, 0x501941b2, 0xa1af8075, 0xb506f551, 0x646feda1, ++ 0x5ea9d10a, 0xc3b01cf1, 0xcccd03f8, 0x5fc619b3, 0x6267d566, 0xdd0fd97d, ++ 0xf3d4009e, 0x19ca7bdb, 0x497747d4, 0x7c8bce4c, 0x7cf0017f, 0xe007f91b, ++ 0x195eb2a1, 0xc7406728, 0xdb127d81, 0xf0e3879c, 0xc9ed977e, 0xc4bc8163, ++ 0x56664e70, 0x933e7382, 0x17481394, 0x1d217317, 0x1ff2aa5a, 0xb66a8728, ++ 0xfb05bde6, 0x53f35abf, 0x5acf3c69, 0x1f9c7d38, 0xcd1ecbfa, 0xb4aaf44c, ++ 0xf9628e37, 0x3afb558c, 0xde2f91cb, 0x2afcf65d, 0x19cf012c, 0xa17be00a, ++ 0xe38157cd, 0x58d2ddd5, 0x6ea780c8, 0x183971b5, 0x9ef255dd, 0xdd067c02, ++ 0x90d25205, 0x3b7b189f, 0xdff04f8a, 0x5d44e3db, 0xf3ef4c4e, 0x8fd81595, ++ 0x72e2f882, 0x87fefb17, 0x1c34d408, 0xf74a83a5, 0x1828ff8a, 0xfeba2c33, ++ 0x2998c152, 0x8262a002, 0x8c27e197, 0x7cd148f5, 0xf7a39469, 0x8a511c94, ++ 0xbff3c312, 0x27404f3d, 0x7001b7d1, 0xe751fc8b, 0x03778354, 0xb2ee943f, ++ 0xfc01bf86, 0x0a49b751, 0x796ea0da, 0xfbef41ce, 0xd87af236, 0x7f917aa9, ++ 0xba816f4e, 0xbadbdf04, 0xf912bfef, 0x36cc976b, 0x92e3b763, 0x4e5fa82c, ++ 0x54d9d808, 0x2a3e03a8, 0xb75abc1d, 0xf86dff69, 0x8d97557d, 0xbabfa039, ++ 0x73be4b3d, 0x1c97d425, 0x526c32b1, 0xcd59b5b7, 0xa0d2fa81, 0xfef589d4, ++ 0xc0be1c99, 0x15b8396e, 0xbabbf7da, 0xfa046f33, 0x33b26a9c, 0xe77c0ab7, ++ 0x01bcceec, 0xb83aacf8, 0xabbf1ca3, 0x10792ede, 0xb6bba5ed, 0x79c6ce1e, ++ 0xbbe5c93d, 0x73325b66, 0xff83f81b, 0xf0e4844e, 0x32fde037, 0x7e832798, ++ 0x728eb097, 0x5b7583d4, 0x676ea9d7, 0x9aa75f04, 0x50671a74, 0x71849efe, ++ 0x9ffabbe0, 0x629c1e4b, 0x51f985bd, 0x38f6fb0e, 0xe1a13de6, 0x42d59afc, ++ 0xb56bce27, 0x0496ed8a, 0xd546ec17, 0xa4dc1d5c, 0xeafbc396, 0xcad49b8d, ++ 0xd9adb928, 0xd70ccc36, 0xfee18286, 0x811d7238, 0x30ad7807, 0x3d46af52, ++ 0x0950fa80, 0xf8a273aa, 0x254a5eac, 0x26d9acbe, 0x8f89b733, 0xff03dd38, ++ 0xbe027f05, 0x849cfb02, 0x836e8357, 0xedd054fa, 0xa8e82e8c, 0x89cf140c, ++ 0x23f7c7c3, 0x0e9e001d, 0x6b9413c4, 0x19ae7c05, 0xfe8144ac, 0x4ba65e5d, ++ 0xd97cfcec, 0x180b6561, 0xeecfd58c, 0x43972af0, 0x33b7655d, 0xca87ac0f, ++ 0xd4196f4a, 0x7bff24b3, 0xc9569f38, 0xabd7c55f, 0xe01f2cce, 0xe6c49579, ++ 0x42dffce1, 0xab5e61a0, 0x013f81b2, 0x8ab31def, 0x0125909f, 0x2bd63a7b, ++ 0x8f26ba7f, 0xfd4339fa, 0x829fa158, 0x97a3f7f3, 0xa3f5374f, 0xfd195797, ++ 0x71fa85fc, 0x1d3f585c, 0xe19857e5, 0xfa36af29, 0xd7682451, 0x79b0bcea, ++ 0x30cf57e9, 0x2d7573c3, 0xe65a93f5, 0x6577a861, 0xb7581f83, 0xdaf78657, ++ 0x6bc9d4f6, 0xcc5f3458, 0xdb8025d4, 0xcd125209, 0x93d32917, 0xea987c4c, ++ 0xa1d5334d, 0xa5c4fd27, 0x4e13fd11, 0x357c6955, 0x50bd2547, 0xfaa76392, ++ 0xe91a399d, 0xf0af3b85, 0x20eb845f, 0xa1b2cd8e, 0xea27faae, 0xe01af871, ++ 0x96165894, 0x0d641760, 0xcadabf7d, 0xc47330f1, 0xc16f8567, 0x81960df7, ++ 0x5fa854c2, 0x04b92964, 0xb891e6f1, 0x59924e5e, 0xb24bb623, 0xab4fd231, ++ 0x089f8af3, 0x7da9e144, 0x8a5fd024, 0xf56edbf4, 0x4d7f2167, 0xa0247e6d, ++ 0x46ab7c00, 0xa0727cc2, 0x7091e92b, 0xd5a3d600, 0x10b32b23, 0xe415369f, ++ 0x157c7a3b, 0xe34f1fc6, 0xf478815f, 0x4319f8e2, 0x4fe5b7c7, 0x1f6f8d37, ++ 0xdf1a6555, 0xc0f8c2ae, 0x9bcd65ef, 0xbf80f8c5, 0x259b182b, 0x6df1a66d, ++ 0xfc68aaa3, 0x32ab2ad5, 0x38349f8d, 0xfe70b7fe, 0xcff344be, 0xff3cc2bf, ++ 0xf9e6d551, 0x37fe7cab, 0xc6253f34, 0xdff9a24f, 0xe7c53d28, 0xcf9aaa3f, ++ 0x1dfbc6df, 0x8835df1c, 0xfce2efff, 0xb7c609fd, 0xcf30cc15, 0x79ad747f, ++ 0x7e3e36fe, 0x314ef345, 0x2fe346be, 0xf9f27696, 0xf1a5ae8f, 0x83df9b55, ++ 0x488ea47c, 0x3da20c6a, 0x31020b91, 0x9794749c, 0x146071ca, 0x2d187e80, ++ 0x771c13e5, 0xfbbe7126, 0x4df80938, 0x163be88b, 0x7d028904, 0xbe782f56, ++ 0x8a897b66, 0x67de967a, 0xffc4dda2, 0xb4c97455, 0xb6f5b0de, 0xb78058e0, ++ 0x600e4baf, 0x55fd62bd, 0x3bd69941, 0xaec80fb0, 0xfe7c6161, 0x6c2707a7, ++ 0x6c579e8e, 0x7ac3b8b9, 0x4724c7a2, 0x4cc09e1c, 0xe011ae36, 0x982646eb, ++ 0x009fa916, 0x2fc60a3d, 0x28f41b7b, 0x3f0aef96, 0x59e838e0, 0x4dcb46a6, ++ 0x0247b733, 0x30f195ec, 0xfc049baf, 0xef8e1427, 0x20a5cb13, 0x75e3ffe2, ++ 0x9fa8abb7, 0x31807716, 0x0def251d, 0x7b034e82, 0x12cdc16c, 0xf88dd3e1, ++ 0x914499b9, 0x7616ffb1, 0xc30d92fd, 0xc2dddf4c, 0xd0596d82, 0x05dad17e, ++ 0xff987523, 0x26d9e6f7, 0x920a7da3, 0x7242c230, 0xc05846cc, 0x5a1798b7, ++ 0x95011d67, 0x4d59e79b, 0xbf7cfd76, 0x2abdfeb9, 0x1acfbd73, 0xded05ab4, ++ 0x4db12a58, 0x8dadefd0, 0x38c6f7e6, 0x4e34a51b, 0x4dde3157, 0x5bde1c99, ++ 0x8f8c9cb1, 0x6deba275, 0x80d6ff3a, 0x5647e1a7, 0xb2f5a616, 0x1d218327, ++ 0xaf641903, 0xef3e75f9, 0xb36f7858, 0x803ebdda, 0xca1fb6e7, 0xf858cf84, ++ 0xf64b9e7b, 0xeb8ec05a, 0x15a1f0d9, 0xf9d8dbed, 0xfdffc2c4, 0xd1f3b115, ++ 0x0bf7d455, 0x39cfb102, 0x53f2c49f, 0xb0c95743, 0xeaed51e3, 0xec39bf3a, ++ 0xd57f1478, 0xaa639b6c, 0x37ce0d2f, 0x61b25fb5, 0xe2fde981, 0xf7a6a58e, ++ 0x376fda8b, 0x7e0417d5, 0xfdff6a68, 0xf7a6cd15, 0x63de36b7, 0xaabdff7a, ++ 0x7cfaa675, 0xf6a6c3ff, 0x64dbcf37, 0xee796f7a, 0x8e50ebe2, 0x664bfe5a, ++ 0xa47c6eb8, 0xed1fb89d, 0xc5348fc1, 0xd938f483, 0x70724594, 0x654dc9aa, ++ 0xbb14d75f, 0x4ac1eb9f, 0x80ce2606, 0x7da071f4, 0x4665ea06, 0xd2cff3fa, ++ 0xd4008167, 0x09b922ff, 0x9506f27f, 0x25858185, 0xc7c83696, 0xfbd47203, ++ 0xdfbcf39e, 0x653e8200, 0x27b97be8, 0xcd86f3fe, 0x71eb460b, 0xdc8887fc, ++ 0xceb811b2, 0x3df58bf5, 0xc4ad7df6, 0x19cfd17c, 0xbce49bbb, 0xb533ac45, ++ 0xb507d72a, 0xa267b33b, 0x86ab5dff, 0x35cf1b0b, 0x1520275e, 0xe75a24f5, ++ 0x200fc819, 0x297e2605, 0xef77c930, 0xaae0997e, 0x7a009d47, 0x0df31d75, ++ 0x099ea0b7, 0xfd751c1f, 0x9bc38404, 0x0caef545, 0x9b7bd75a, 0xae3b0f66, ++ 0x547c7d20, 0x479a6c9e, 0x3f2689e5, 0xaa9bc795, 0xa9bb7ca8, 0xa69eca91, ++ 0xd9be5415, 0x8df2a014, 0xff2a76a6, 0xe541d4d8, 0x540da6b1, 0xa414dabe, ++ 0x4bc9afb2, 0x62bfa0e5, 0x6174dfe8, 0x02bf0aaf, 0x9faa1e56, 0x85697311, ++ 0xe724ddb6, 0xf3942c9e, 0x85c7da33, 0x399f8f68, 0x5e658e06, 0xf2c57c62, ++ 0x7a3a625b, 0x0ca95ec9, 0x0ca7fd02, 0xe248ef7d, 0xd8587274, 0xd9a6706c, ++ 0xea7f633d, 0xea9e3859, 0x2c0cb20a, 0xce399e48, 0xdac2fd38, 0x1f3af487, ++ 0xa077989d, 0xe3d02e68, 0x297f23c4, 0xc45b7ec6, 0x507497fa, 0x859875a6, ++ 0xbd20f09f, 0xeb46f0a2, 0xa12ec0da, 0xbf83cfef, 0xebf883d3, 0xfbfe851e, ++ 0xfea74921, 0x4c6c84cf, 0x4dee3c41, 0xb3f3020e, 0x709e4733, 0xcb2e3ca1, ++ 0xe3c7e8b2, 0xeb28c1e0, 0x2d74f33a, 0x32e9fd7a, 0x4874cfd7, 0x3d693bb3, ++ 0x30dca776, 0xd74af901, 0xfa418f8f, 0xf4695167, 0xd54b2cb3, 0x9ebc838f, ++ 0xc29056da, 0x5f20efd7, 0x12a7b707, 0x485f82bf, 0xf0d6ffed, 0x80c7ea24, ++ 0x7b10b187, 0x00fa8ec7, 0x797c15de, 0x7f299cbf, 0xdb15f8a6, 0xed18fd6b, ++ 0xf7fc1b05, 0x140fc505, 0x36fd1baa, 0xdb01ca74, 0xddbe7c44, 0xe77c1e34, ++ 0x2fee7c36, 0xb7c5cff2, 0x15113b0a, 0xe2275847, 0x1cdb358d, 0x495d79ba, ++ 0xba1bd535, 0x3ad375b2, 0xfc807f83, 0x414946b3, 0x5c15a9be, 0xed68afd4, ++ 0x6b57c012, 0x0dbf5371, 0x67576f12, 0xf0fd51ef, 0xd38874e8, 0xa77c112d, ++ 0x15b88e9a, 0x3b2af790, 0x5f008078, 0x65c5e755, 0x874ee7a8, 0x1ed1325a, ++ 0xdccf91ac, 0xfdf38be9, 0xe3448b4e, 0x075a0d2d, 0xe0a8ebcc, 0x1afd060f, ++ 0x62cfc9cf, 0x7aa889da, 0xd9db85af, 0x141efdb1, 0x3f0f9efd, 0x968fdbf5, ++ 0x8a1ee95f, 0x0faefaa7, 0x11c93f54, 0x04715ffc, 0x6afe064f, 0xa883be2d, ++ 0xbdb7ab4f, 0x49e8f645, 0x47f0a06b, 0x434fd0e7, 0x5165a7e7, 0x5798d49c, ++ 0x184a4c00, 0xef88a167, 0xfcdeff02, 0xefa7ac3a, 0xd6cad6fd, 0x33ec7c00, ++ 0x07051568, 0x502ca906, 0x0b6a245f, 0xd7143543, 0xedc2cf7d, 0x73e60aa8, ++ 0x47581d11, 0xa791da31, 0xe2366599, 0xd97b34e9, 0x0e8a2535, 0xd2545aef, ++ 0xcdda8b33, 0xbfd80c76, 0x0d92faa6, 0x9b257ae6, 0xa4fa899b, 0x0595bd72, ++ 0xe99f9a25, 0x3a2c1ffd, 0x6b097fe1, 0x6aeb855c, 0x3083fa0b, 0x299d42ee, ++ 0xbabe0023, 0x8c5a3e5f, 0x0b3eee71, 0xf88c43f7, 0x0e34d2c8, 0x26e7757f, ++ 0xdfef0bd5, 0xe9b94d09, 0x07df864a, 0x103ae157, 0xb67925d8, 0xf7e287ba, ++ 0x0b1fc2cb, 0x0f5eb1af, 0x3808d389, 0x7149b6ea, 0x099fade3, 0xf5f4333e, ++ 0xe4dd64b7, 0xf584dc17, 0x4521bf28, 0x99597116, 0xd3f748c9, 0x49603dba, ++ 0xb714f7a1, 0x79b4ec0f, 0x8f7e605a, 0xe4c37c5b, 0x14276469, 0x8f76a8b1, ++ 0xbcf4fc5b, 0x12a97a57, 0x84a656ed, 0x850ed08b, 0x54f88635, 0x2720fc15, ++ 0xde308ab9, 0x8eb064ec, 0x086dfd02, 0xcab3f41f, 0x2b2d7559, 0xc83778c2, ++ 0x9f77f43b, 0x0488fcab, 0x62168775, 0xcb2d9fd8, 0xb877cf1c, 0xfc06f5cd, ++ 0xd612f803, 0x253f8a38, 0xf062538f, 0x0fa86618, 0xf3f31e9d, 0x9184e809, ++ 0x3e261fdd, 0x438b1176, 0x32c2d769, 0x2ba6cf8c, 0x56fe83bd, 0x1c7bfa3e, ++ 0x402f8a7e, 0x6f3ae5fb, 0xe7e22f5f, 0x399b5fcb, 0xfa1ced3c, 0x682ce1a8, ++ 0x75516190, 0x567fbe23, 0x5f29c161, 0x61ba6f43, 0x9bd28d55, 0x59fe2df3, ++ 0x93d40f48, 0xe3049f08, 0x60764df8, 0xe72d1eae, 0xe3f8630b, 0xce91c32b, ++ 0xd6bbfa4c, 0xce49bfe2, 0x57c70a18, 0x486b3fee, 0xcde30bff, 0x3ff72bf3, ++ 0xf5ff4866, 0xfbaffaf1, 0x03bb33e5, 0xcfd54fc0, 0x6602e83e, 0x1d29ef66, ++ 0x7ba01e99, 0x1736d6ed, 0x2549e5ca, 0xbeba42e0, 0x07679417, 0x16c3f0e3, ++ 0xaf4f90d9, 0xff131526, 0x7a9d1f10, 0xa0efdeea, 0x56f1f55d, 0x81f14eab, ++ 0x0db0b66d, 0xb43eb298, 0x36c7cb94, 0xbebc5bdb, 0xcfe403fa, 0xbeb32e86, ++ 0x83d9fea8, 0x066f1899, 0x39ff0a4a, 0xfd41fe4c, 0xa3953f96, 0x06c0d5dd, ++ 0x7ec5ef48, 0x4d9fe387, 0x81607b23, 0xbdf4329a, 0x20d7cfb1, 0xba10d2f0, ++ 0x849903f7, 0xcdfc87a5, 0xc255f6d8, 0x76507fde, 0xef9c53a6, 0xf2197632, ++ 0x160f8199, 0xcb7ef6e4, 0x7a293f93, 0xdde9e00b, 0x34975bf2, 0xb93f9a3e, ++ 0xb9d33bde, 0xb95ff1e8, 0x1f53cb13, 0xbb68c5e8, 0xdd9f58da, 0xd94fc25d, ++ 0x6b5acbcb, 0x607e85d8, 0x27ab26ed, 0xe67d7480, 0x823e9f89, 0x6cd79971, ++ 0x7fd0b19e, 0x5e8733cd, 0x35ea02bd, 0xd7e9ac3b, 0x526869f2, 0x0d2e8466, ++ 0xc98adff0, 0xff543a11, 0x9eea90e2, 0x4caf9fc0, 0x66a3d08b, 0x4d957ec7, ++ 0xd28f8a18, 0x8f6afdce, 0x9d2e8716, 0x3fa3956f, 0x27e4f2d1, 0xf7afea2a, ++ 0xf0d8939e, 0xdcf838bc, 0x62ec8874, 0x51d113c4, 0x6e9069d0, 0x801bed31, ++ 0x0d5fa82e, 0xbfbec53a, 0xec7fe84b, 0xf89e3dcf, 0xc2bfe7f9, 0xda3f947d, ++ 0xaaff383c, 0xc2e1df9f, 0x34abbc79, 0xb47ebe72, 0xe30bd32d, 0x99035956, ++ 0x79fc953a, 0x203f63d5, 0xf4725b7e, 0xff149907, 0x0b6cde60, 0x6c810ad9, ++ 0x8de2df9c, 0x2afcd237, 0xaef89f99, 0x87d951ea, 0x0a47d5eb, 0x8e23bd9b, ++ 0x5c28e45c, 0x19bbbf1f, 0xdf980c1c, 0xe070b8bb, 0x72cbc2be, 0xffc52b70, ++ 0xcaf8a76e, 0x20fd8c0f, 0x1fea8cb6, 0x3e9d39d9, 0x357d8d90, 0xf9a27958, ++ 0x6eeacb75, 0x91a9cfa4, 0x3718e1de, 0x404a606e, 0x02fa43e0, 0xce8f95fa, ++ 0xc3e9ce1a, 0xf8b14adc, 0x297df40e, 0xddf6c73e, 0xc8a3af56, 0x22fb1df4, ++ 0x72fe322f, 0x9dc03e31, 0xbbeaf684, 0xc5ff6099, 0x62b95f99, 0x576037ac, ++ 0x9457f145, 0xdf79737c, 0x6f970f72, 0x7383de43, 0x3ffbe366, 0x07e5c2bf, ++ 0x057b43bf, 0xa70f0ae0, 0x906ffbf7, 0x58d81f48, 0x6f5c9e38, 0x36b90ab1, ++ 0x04f837bf, 0xdd7056e0, 0xec17e41d, 0x4ff08d3f, 0x7ae56c76, 0x5f4a2ef8, ++ 0xae78e036, 0x7219fda1, 0x7fc844bb, 0x7f966286, 0x7dcb91b6, 0xc0227f62, ++ 0xe0d612e3, 0x79411f4f, 0xfdc4f905, 0xac67daeb, 0xfbf79c3e, 0xfabe0fdb, ++ 0xf7d3905d, 0x35390d3b, 0x3958cfeb, 0x8d39daad, 0xf7d393c5, 0x9e210d31, ++ 0xb8f3c29c, 0x10f5aa72, 0xf4bdff1f, 0xabbf81a7, 0xe867f062, 0x8c7844c3, ++ 0x947f87d5, 0x21f571dd, 0x15857bfc, 0x833fe50f, 0xab7e0cef, 0x346eba7e, ++ 0xbe0cc7c5, 0x906ef834, 0x1bbe0d2f, 0xe1346f12, 0x0dbdf62f, 0x97003063, ++ 0xe2958f6f, 0xf97bb508, 0x777c2ffe, 0xc254c478, 0x31969793, 0x447871d6, ++ 0x183d747a, 0x698cef53, 0xfba98def, 0x63fbda62, 0xf6a68dea, 0x55075db5, ++ 0x3612d79e, 0x3c5793b5, 0x1619dec2, 0xdc835f8f, 0xa07d0d2f, 0xb42f9006, ++ 0x7adefa01, 0x31380b37, 0xa64fbe1e, 0xe03f48f8, 0xd38c1578, 0x882f3dbf, ++ 0x0e6d1279, 0xc81a771e, 0x9ea15750, 0x5c07d7eb, 0x380e3768, 0xdfaf1c78, ++ 0x8d4ae037, 0xdaded7b2, 0xee9e932b, 0xf1d9b209, 0x41584afc, 0x587a6e48, ++ 0xbe3cf7a2, 0x46d64b3f, 0x4b78c0ad, 0x10c1ec87, 0xcdf3454e, 0xe82bcc2e, ++ 0xdd705bdf, 0xf8be783c, 0x0db69945, 0x4f4ed1fb, 0x95787241, 0xee7f28ec, ++ 0x343c0b24, 0x7bf5e303, 0xb1575fb9, 0x60fec636, 0x2a7f896b, 0xea2ae5b5, ++ 0xdec3f04f, 0x7057ef36, 0xfd16a839, 0xbf346d55, 0x1dc7be37, 0xabd7b45b, ++ 0xfbdf98b7, 0x541fff85, 0x24cf3e44, 0xdff84936, 0xf424fe3c, 0xfc792cf0, ++ 0xff00f375, 0x866447fd, 0xf667f5fb, 0x33ff84ca, 0x3cfef9db, 0x472fe9c5, ++ 0xfd201e7e, 0x17a9e067, 0xac4d47e5, 0xfd777a9f, 0x908ff177, 0x5ebf764f, ++ 0xf6506ff4, 0xf0ad7eee, 0xe5ff58d7, 0xcebd461f, 0x7d2fb686, 0x22fb41ce, ++ 0x8939cffd, 0xfdf7fbbf, 0xb08fd46e, 0xf146c7be, 0x3ee7fee8, 0xe97e4229, ++ 0x8556dbbf, 0x247fadfa, 0xf65b47f7, 0x43d4527d, 0xd12b69eb, 0xca8ab7ed, ++ 0x7fbda1ed, 0xc74a5379, 0x76856612, 0x24c973c2, 0x72bf0d3f, 0x7facfc50, ++ 0xd1c527df, 0x9dd7fe76, 0xafd8bd4f, 0x79b277ec, 0x54be113b, 0xf0d3cfbe, ++ 0x689fcbeb, 0xd08b7cc6, 0xbc11757e, 0xe7cdfd2f, 0xfb37a845, 0xa7fb7277, ++ 0x18f3dacf, 0xdabdc7ee, 0x2b6eef3a, 0x850fb9e0, 0xd3e80728, 0x944cf0f6, ++ 0xf978a193, 0x1782e29c, 0x0ad38f8a, 0xe3fc0f8f, 0x72f243e3, 0xda0ce6fd, ++ 0xa7f79c25, 0x7a8ebe6f, 0xf11b39e0, 0xf7df31a5, 0x3ec99b3b, 0x35bcdf39, ++ 0x7c2bffeb, 0x96f3a170, 0xef3217c2, 0xe7c1ff4b, 0x137143bd, 0x3072b17c, ++ 0xddf7cf94, 0x9c67f549, 0x02f7821e, 0x7f9afdf9, 0x697ff9f0, 0xba04efba, ++ 0xef3fcebb, 0x79f07fea, 0x8bfba627, 0xebba09b7, 0xf0d2cf98, 0xbe09cf9b, ++ 0xd6e7ab2f, 0xf5b1ff58, 0x1bf9a25c, 0x8b1afc76, 0xe31f23a7, 0xc025e871, ++ 0xe739ad3a, 0x707863b6, 0x3ab9b8cd, 0xcc7295da, 0xfe51a4fe, 0x24fdcada, ++ 0x3129f719, 0xc79237ae, 0x9bf098f5, 0x860f0b68, 0xb24ab456, 0x156d155b, ++ 0x4f15a7b7, 0xb2f017b7, 0x1e8592e6, 0x936215ca, 0x9eb1f98f, 0xf143c33b, ++ 0xb1ff18ea, 0x095e6255, 0x92e559ec, 0x7f411d6f, 0x12ce3ac6, 0xf95115b6, ++ 0x45ab9616, 0xabaad21c, 0x1b473f26, 0xdc3bae6f, 0xf44dbae6, 0x7e1c6767, ++ 0x620b167b, 0xf8be5a3c, 0x6c798e80, 0x498524f2, 0x8eb07750, 0xb613fa00, ++ 0x3ff7f32c, 0x8cd664c1, 0x35731e08, 0xb0be432f, 0x0cb43b0a, 0xe7ac14fd, ++ 0x5fed18fa, 0x49543b0a, 0xe200b2f7, 0xc430f755, 0x6103fa2f, 0xd85e07f0, ++ 0x1fc504fe, 0xd6f53f4e, 0x9a9e1077, 0x0ecccb5f, 0xeedbecf8, 0x5efc6164, ++ 0xdfe8aa09, 0x2f648754, 0x709467c5, 0xfb51f5f1, 0x597d8689, 0xe693acf3, ++ 0x16d3bd53, 0xafbe16bc, 0x114efdde, 0x0f77f7ad, 0x781cbd90, 0x256cf24a, ++ 0x708a7bb0, 0xe15ab0bf, 0x7d2c6e76, 0x3f72b0df, 0xf24f77bd, 0x48078c3c, ++ 0x671e78db, 0x56cde775, 0xcbfe545b, 0x6f3cadef, 0xff11da18, 0x28949e05, ++ 0x8be1068f, 0xec341fce, 0x2527dedb, 0x35975f0e, 0xd5a0f988, 0x61f476db, ++ 0x98faa35c, 0x62e683cd, 0x280fb6c3, 0xecfa5e6e, 0xf21eae33, 0x5f9364e3, ++ 0xdc9fc43b, 0xd43f1326, 0xdec8ea87, 0x45f13a85, 0xb8fc677d, 0x9efcf9ca, ++ 0xedf7679a, 0x6b0a000e, 0x1733f17e, 0x754e4dc6, 0x5f91756f, 0xf1dcedb9, ++ 0x63fe219c, 0xf4e73de7, 0x1fe14f1f, 0xd55b2760, 0xdb7bff18, 0x017bb230, ++ 0x7978e2be, 0xd5bf06c4, 0x63d1f33c, 0xddecdf18, 0x0863fef9, 0x3f5fed6f, ++ 0x56ed0c7c, 0xc7439cf6, 0xa7868e7d, 0x43e28bfe, 0x55a377c6, 0x7beccf1e, ++ 0x571467f2, 0x1dbf03eb, 0xf7dbeb7b, 0x5bf428ee, 0x9a7c76fa, 0xf2f87e89, ++ 0xe386b37d, 0x2aef977c, 0xc8e2ce1d, 0xdf2251bd, 0xae202f06, 0x83af4b17, ++ 0x5f6483a1, 0xa37a069f, 0x0f18337f, 0xf1e3ace8, 0x0388b715, 0x3f1f8f6c, ++ 0x87f7e21d, 0xaaeebfae, 0x3d5a58a9, 0xebce3ea8, 0x7402bfff, 0xf401789c, ++ 0xf08f7edb, 0xefd3e273, 0xfe81fe34, 0x1cfc2abf, 0x428fbf41, 0x047f1f8b, ++ 0x258685df, 0x17c3fff4, 0x3e233780, 0x677aa49b, 0x3b5f28ab, 0x0b78a69f, ++ 0x985aedd2, 0x1f33df68, 0xf6b8c28d, 0x6dc0eb49, 0xa6dfdf3c, 0xbd5b1fa3, ++ 0x3f240fef, 0x528ebb7d, 0x388993fc, 0xfc1b1f69, 0x225ae3c7, 0x8b61af57, ++ 0x040dc793, 0xe0ae31fe, 0x1173d176, 0x6c7ce03f, 0xc51215c4, 0x7cd49a13, ++ 0xe3c77791, 0x5e5b751e, 0x847a7e17, 0xa474d25e, 0x8ce75bd3, 0xd0781b73, ++ 0x45970f11, 0xc7e2c7c7, 0xa8e3066d, 0x5c465e82, 0x05fe306c, 0x878c5cf5, ++ 0xb03fa504, 0x6fa0fa38, 0xf5ab8f13, 0xe7e7e359, 0x7fb2f118, 0x31b3a18e, ++ 0x61f244cf, 0xe0f9e9c8, 0xa9f8b2ff, 0x7e26dd51, 0xfbd4f031, 0xfe3d7c59, ++ 0xfb617aa8, 0x5bf709d9, 0x3ed3256a, 0xbfc5ad76, 0x2eb1f911, 0xcfca96f4, ++ 0x3873f03b, 0x457b7cc6, 0x53ef623e, 0x5651c532, 0x3d241e75, 0x8c2fab1e, ++ 0x7858b8fd, 0x5db9559f, 0xd7c5df51, 0xce9dde89, 0xf4fd06a0, 0xfc43d81e, ++ 0x2dfdbf5c, 0xde1ce38a, 0x27b50bf6, 0x75c55d6a, 0x7f051822, 0x17f7cfef, ++ 0xcf2078f1, 0x671d8e8f, 0x61a7189f, 0x1a71fc6f, 0x1a607fb6, 0xa9d026a7, ++ 0x73d2fcf2, 0xf14a778f, 0x9dfd8cde, 0xcc32b6ea, 0x29d53c1f, 0xffb78ecf, ++ 0xa6ad541b, 0x5eb825f3, 0x51f81e52, 0xea62de7e, 0x679449cb, 0xece8fcbd, ++ 0xb1d253d7, 0x7f43c204, 0xa7ce66a1, 0x477b1fa1, 0x4743bd20, 0x3ae32bbf, ++ 0x1bf11bb5, 0xbf164f65, 0x04ea58d2, 0x86fc50bd, 0x6bb22a6f, 0xecb9beac, ++ 0x3f04c598, 0xd71c338c, 0x07e85681, 0x1e603fcf, 0xbb23c215, 0x3c2367ca, ++ 0x1dd16eb2, 0xad5ef271, 0xd0f28f9a, 0xbaad7e8d, 0x7d9ccf39, 0xfd8dc536, ++ 0xe46c5df4, 0x1052f917, 0xdf751f4f, 0x2fbb4bc8, 0x73f95ce5, 0xecbe8527, ++ 0xb0b0f26d, 0x6081cfca, 0x1fe441bd, 0x483ded57, 0x3aaa9de7, 0x7c06e625, ++ 0x241d652d, 0xa9aa9f37, 0x6cc43f22, 0xfdef543f, 0x0eafb53d, 0xac35f6f1, ++ 0x79e3da93, 0x3e49b091, 0x1dd8c4a6, 0x45fbbf9c, 0xd9ed48de, 0x3423ca62, ++ 0xb8d874e0, 0xe936f59c, 0x8b5efd26, 0x7e7869f0, 0xa9c69bab, 0x1a661ceb, ++ 0x775768c7, 0x2fca0af6, 0xdd2bac1c, 0x67756fc4, 0x19c689ff, 0x2ca6af94, ++ 0xfee243c2, 0x8ee09847, 0x04dd3ff4, 0x19ffa46f, 0xfe6c6e34, 0x1e5cd669, ++ 0x9ebecc5f, 0x5ce30197, 0xb052654e, 0xfdf70f25, 0xd06d23fd, 0x3eb9cb3e, ++ 0x73a310ef, 0x3dbf9460, 0x942926c6, 0x8fce246f, 0x80b5d69d, 0x47dbd605, ++ 0x66ebcdb4, 0x1843ca30, 0x43ce8b67, 0xd422e160, 0x21bb461f, 0x14f263ef, ++ 0x5013f172, 0xaf80b281, 0x8c29e440, 0xfa123d64, 0xfc9d1b2f, 0x2d68e29c, ++ 0x3fdf82dd, 0xe303fc21, 0x7390e21c, 0x15e7318b, 0x314e77cf, 0xf6e4b4bd, ++ 0x1ac61ed1, 0xf14afb6d, 0xcdfa4adc, 0xe8463b25, 0x7f03398c, 0xf6bcc52c, ++ 0x4c959ff4, 0x9ffa86ca, 0x4651df56, 0x992cfff5, 0x9fea0a34, 0x329fffb7, ++ 0x51235f6a, 0xcda96ade, 0xc07e8653, 0x37cbd657, 0x7acc4600, 0xc7a43af9, ++ 0x371bdf69, 0x1e63762d, 0xf1ca80c4, 0x6ed87ccb, 0xb78e74e4, 0x1d8ded5c, ++ 0x96d1a788, 0x27d4669e, 0x24fbef8f, 0x9bb8f515, 0x9d1f84e9, 0x6798eab5, ++ 0x7fa68f02, 0xba7c8e71, 0x8332bcd8, 0xbf34aa7f, 0x7ab7e91f, 0xca07b8c1, ++ 0xaa47bc61, 0xde79db26, 0x819f399e, 0xcf44e9e9, 0x844f410a, 0x97951ed3, ++ 0xa80e44bf, 0x874c7cfc, 0x74ca5f58, 0xd40a4f1c, 0xfa5c5fca, 0x6e5ae1e5, ++ 0x5f38a5f0, 0xf1ae751a, 0xd5dbc42e, 0xd8ca9f9a, 0xd9d78d73, 0xf9c43f7c, ++ 0x1d9e5764, 0x9ce37585, 0x4779ec62, 0xe2580ca6, 0xc59bebd9, 0xf044c779, ++ 0x57fbb1ce, 0xbff9b8e3, 0x023cef71, 0x42b135f2, 0xe68a60f5, 0x335315c4, ++ 0x90be7e14, 0x041a1df2, 0x5c2cb2fd, 0x8c9dd90e, 0x6dfb5bf6, 0xe9fd1792, ++ 0x5a743bfe, 0xae2b736f, 0x3fb6bf25, 0xf313af39, 0xc47ffa82, 0xe66297cf, ++ 0xc8d1ca34, 0x876129bd, 0xe3e0e48b, 0xd8f83918, 0xc798976c, 0xddc2ffed, ++ 0xe9fd43d5, 0x98303fa2, 0x83e72333, 0x8ebe65fb, 0x09b937f6, 0xb02c918e, ++ 0x0bb1ed1f, 0x36a7ef1d, 0xc05ff9f3, 0xbc68b6fb, 0xbf4c4f6f, 0x9efd0567, ++ 0xd8bf478d, 0x6d0ba873, 0x7bb610fe, 0x2af0f2b7, 0xf9e87bab, 0x36ba58d3, ++ 0x630f1d28, 0xef7323a8, 0x18176407, 0xc2b89b74, 0x330ca193, 0x0837f1d1, ++ 0x1fbdc4ef, 0x835c7058, 0x90493f7e, 0x1b5bfdf7, 0xc7623fb7, 0x93d79ccb, ++ 0xfed38fe3, 0x45ce0c55, 0x7b22e7e9, 0xdc3f8d31, 0x4340e3c2, 0x3fec27db, ++ 0x98f95cff, 0x17ef3a45, 0xf10c7ff0, 0x0dffe064, 0x1b3fc89b, 0xc1ffff8a, ++ 0xa9fe0379, 0x1ffc00bc, 0x0dfe173f, 0xe846ac3f, 0x6fdc1a85, 0x93f9fe02, ++ 0x3e666e7b, 0x6b2e5b8c, 0xb74bffc4, 0xd23f62ca, 0x66766d7b, 0xbd2c8f44, ++ 0x15bf71bc, 0xa3e970f8, 0x8569f112, 0xbefeb738, 0x9b12df38, 0x2f3957df, ++ 0xfcf27a40, 0xd2417e79, 0xccdb3543, 0x09b73fcf, 0x46c9ddff, 0x806e5e51, ++ 0x8594a39f, 0xffe2c45c, 0x45f4268c, 0x5da9aa45, 0x36461d2c, 0xe0f94c5a, ++ 0xfd83a5d9, 0x659e5f90, 0xe281ff71, 0x656eff6e, 0x2af1cf18, 0x88c353e9, ++ 0x1952a98f, 0xe4225bf6, 0xf46fe8d6, 0x965db30a, 0xff9f3017, 0x9f37682b, ++ 0x91db1bff, 0xd17f6a63, 0xfbd37c86, 0x9897838b, 0x6dba5fde, 0xa13ea9b2, ++ 0xfb530af3, 0x4d335d89, 0x6fe149f5, 0x394fda99, 0x9f54d732, 0x535dfdd6, ++ 0x2d8ecbfb, 0xbcbfbd34, 0xfef4daa7, 0x4ccb93ca, 0xfe06abf5, 0xbc3ed4d9, ++ 0x03c5eb98, 0x78b9594d, 0xcbc0c0be, 0x8b55db81, 0x2f6fcf8e, 0xd145e8b4, ++ 0xeebd33cf, 0xbd8b2c22, 0x92270fe8, 0x767b5297, 0x5cfaf46e, 0xbd26acc2, ++ 0xad8f6a56, 0x05197e0b, 0x9fc402fc, 0xb5eb376d, 0xda338d11, 0x39647cc1, ++ 0xde50c74b, 0x35d7c834, 0xa8dfae76, 0xf2f900bc, 0xeb77bb61, 0x3ede74c3, ++ 0x9464be56, 0x032a02af, 0x3ccacfb4, 0xb0f97794, 0x59a7ccc3, 0xadcaf409, ++ 0x7b888b76, 0xf4fef076, 0x24c50e23, 0xb3f3c627, 0xa5cfd149, 0xfe52d725, ++ 0xad7ea24e, 0xd9af0b59, 0x9ad2fa02, 0x78d2a7ed, 0x12cf36de, 0x2eef3f37, ++ 0x6bf4d7fb, 0x9fb10c37, 0xbee3b2ee, 0x0fcbfa65, 0xfd59be61, 0xdfe4032d, ++ 0x78ccdb66, 0xc33dd489, 0x9b953e79, 0xf9d4279f, 0xda9b1b9f, 0xdef5c1af, ++ 0xd7e2e798, 0xde6266e6, 0x7f026e40, 0xeb9d9777, 0xaa9ac7e9, 0xb3c0a9ae, ++ 0x15876820, 0x8f65ce47, 0xa394370a, 0xe45a3e9d, 0x89643f43, 0xaff4b79f, ++ 0x51c31f02, 0xa07da281, 0x3f8f14a9, 0x4b86f95d, 0xd6fc7981, 0xe457ffe2, ++ 0xbb13858b, 0x65f9f98b, 0x4a5cd64f, 0x7e09d0b0, 0xd28d0f43, 0x5ea10f7c, ++ 0x99e60519, 0x3c286f3b, 0xcdf16fc3, 0xadf783ce, 0x468f1669, 0xc70901f5, ++ 0x36325753, 0xfeb7da0c, 0x5af82655, 0x794e5c0f, 0xa7e6aa3d, 0x4f31b778, ++ 0x8c00f226, 0xe947fef8, 0xd81f9037, 0xf9e0c97a, 0xa17e461d, 0x7ec6ebe6, ++ 0xa56f5a3f, 0x4a675b71, 0xb4a3f7a6, 0x030fdb8e, 0x64a1951c, 0x1b29fb8a, ++ 0x8c7e43be, 0x69e1c59a, 0xb9624c7d, 0xe3c3c112, 0x0f8e2ed2, 0x44a3c3c0, ++ 0xc7de6f67, 0xf0d26316, 0xa5452ebe, 0x13239d73, 0x125e0bc4, 0x0dfa65f8, ++ 0x65476899, 0x5786645f, 0xede0ff5e, 0x633f3187, 0xbb07b257, 0x10ad360c, ++ 0xb7cf34f4, 0x75ee7d2d, 0xcb5da1f3, 0xd4c3322b, 0x630f771f, 0x390f3469, ++ 0x6f838c18, 0xf7005e83, 0x793f484b, 0x33cd3943, 0x0979d04f, 0x7ef519d0, ++ 0x9b37c596, 0x61699ee8, 0xf858cf38, 0xf6e42f7f, 0xfdcebb15, 0x6bcaacf4, ++ 0xb2c30cb6, 0x98ede482, 0xf57da13d, 0xaf3fd0ba, 0xe73fd3c7, 0x76a3f7bb, ++ 0x2c61f75e, 0xd845af65, 0xd1858db3, 0xabe83276, 0xa30f4813, 0x2caca72e, ++ 0xd897bd42, 0x17b4f31e, 0x1edf9de6, 0xf90c3b43, 0xfec3b0ce, 0x2fdb376c, ++ 0x13f5fa51, 0xa85fb73b, 0xfafd00bc, 0xefd7e919, 0x2fdae386, 0xfd7c6a19, ++ 0xf1c1c536, 0x8caba0df, 0xec12f8f2, 0xa43a14bb, 0xb44ef3b8, 0xbfcf9cfe, ++ 0xf8364fc8, 0xdcebd0d4, 0x2a9560cf, 0xd99d03ed, 0x10a7bc10, 0x7cb52df7, ++ 0xd44dbbca, 0xff1588cf, 0x1afc40ee, 0x30e91b78, 0xe8f013e3, 0xa13e7076, ++ 0x6b1e0872, 0x13168f01, 0xce3ac71e, 0x657e0761, 0x3e655ebd, 0xf027d377, ++ 0xc55dfa0d, 0xff5f4ef1, 0x2bc63166, 0x98fc6fea, 0x1e57fbf4, 0xfd799e67, ++ 0x186efc30, 0x3ee07247, 0x157ff5cb, 0x8a1ed1f1, 0xbaecb5eb, 0x88e30528, ++ 0xf5073375, 0x83db9d86, 0x4effa4f9, 0x1179b6ef, 0x3c69d3ce, 0xf77a74be, ++ 0xbe318765, 0x91d37ef1, 0x5eca257c, 0xa3f3fd39, 0xefe856c5, 0xc5a3cef4, ++ 0x20efe90a, 0x5f78cbe1, 0x8befc5f7, 0x9ce45a7d, 0xd9bf20c0, 0xdeb3faf9, ++ 0x3f26e3c1, 0x89b6bcc1, 0xcc9f3d8c, 0x33c364e3, 0xf3e3f72d, 0xc0102916, ++ 0xd48b6838, 0xc7718a5d, 0x9d19b7c0, 0xbebac99b, 0xacd6cc92, 0x0f2e3602, ++ 0xdf3db3be, 0x527ac611, 0xdfe52777, 0xc3bac769, 0x067aba58, 0xa5edb8bc, ++ 0x63f7d49f, 0x0bfcd0e9, 0x0369ef11, 0x31e26f9e, 0x8a73f5ed, 0x94a44e29, ++ 0xb03bbd72, 0xf7882920, 0xbc5a6514, 0x39bd7147, 0x2a516473, 0xcc993fbe, ++ 0x66d71ff7, 0x0791d2bd, 0x4032e3e3, 0xad17a7f1, 0x1b2ef7e4, 0x0c5ecde9, ++ 0x949b2fdf, 0x3ecb7c4e, 0x9d47d983, 0x3d2fb963, 0x8ff14594, 0xc52f00cf, ++ 0xc8cdbfb8, 0x7e14d1ee, 0x0b2ad0af, 0x6a50eaf3, 0xddee6353, 0x70fbf611, ++ 0xddfb7fa1, 0xf0158096, 0xb7378ea2, 0xa77110cb, 0x98dfc810, 0xb57f1831, ++ 0xa4d5d953, 0x7a018c67, 0x8b29aafd, 0x6e4dbdca, 0xd35cfe7a, 0x4dc32a38, ++ 0x2dd32a1e, 0xd168a3dd, 0xddd71a55, 0x6df57e82, 0xb7be8b0a, 0xb7bcb623, ++ 0x63e3df89, 0xcf1c3fd4, 0xe1d00a02, 0x9a47a143, 0xfc429a5f, 0x8004d0f5, ++ 0xefd0e27a, 0xeff15e1f, 0x25b86505, 0x0523c3f5, 0x1f0fa065, 0x033e7892, ++ 0xbc526bd8, 0xf28c5e7b, 0x2a476b21, 0xc2fd89e6, 0x596502c1, 0xf0391798, ++ 0x1960729d, 0x51ffbdc7, 0xcc317656, 0xaffff71f, 0xe39f6c60, 0x873c56d5, ++ 0x45e07d9d, 0xed46f919, 0x4cf9f7e2, 0x98cd7c93, 0x646ec117, 0xf159df7c, ++ 0x673e6335, 0x8dcc4dff, 0x38c6fdfb, 0x3edc1cfb, 0x74e0e3d8, 0x7a71269f, ++ 0xc8aaf9b3, 0x8a28182b, 0xdb62375e, 0x29f83d4f, 0xde3007ad, 0xf1a611fe, ++ 0x987e2806, 0x03ecbbe8, 0x3ffdd29f, 0xff5dfa17, 0xf3c50a2b, 0x7bf0cb41, ++ 0x6e67e691, 0xf6f1235a, 0x57ec78d1, 0x2f69dbe3, 0xcda07589, 0x70f6e9ca, ++ 0xbc373f1e, 0x8515e841, 0xb3fffd71, 0xa02f99e4, 0x1a7f30dc, 0x88b603ed, ++ 0xb1f14238, 0x93817501, 0x02570bdf, 0x7c378cf5, 0x17d402d2, 0x12d99e82, ++ 0xe7c4edf3, 0x4cd27d67, 0xbe1d7ba8, 0xac9fb197, 0x33d91b45, 0xddbacf80, ++ 0x9db23736, 0xa396af81, 0xe1f31daa, 0x45bef633, 0x522d86fb, 0xe1268a8f, ++ 0x4a7cf787, 0x6b16caf1, 0x7faf3663, 0xccf186d4, 0x1f1b389f, 0x7c0b3ac6, ++ 0xf03cf65a, 0x0e7170c3, 0x1ea09f1f, 0x3d44390b, 0x17ab71f0, 0xe56421f8, ++ 0xf89ef875, 0x5c6d6423, 0xb1f8e780, 0x85fd0ade, 0x2c23bd52, 0x3f9ad750, ++ 0x15723d6c, 0x1ff68dd6, 0x873efb52, 0xcd46edce, 0x1ff4879f, 0x7750ebac, ++ 0x5e15d546, 0x1a5e7667, 0xf83babf3, 0xd70fe529, 0x88fce5ef, 0xe279c378, ++ 0x8eb879bd, 0xb98fd19d, 0x6f14dd9a, 0x3afae42e, 0xe333e26c, 0x8b16ea7c, ++ 0xe945259f, 0xf58ccfd9, 0xf45a634f, 0xb1c7bc79, 0x7f54465d, 0x8b9d7e22, ++ 0xa014def7, 0xa54037db, 0x67cd6f11, 0x6cc72a1e, 0x0720739b, 0x15bb2f9a, ++ 0xa4a616f4, 0x47dfa914, 0xe311983d, 0xe64cac37, 0x5c9cd3fc, 0x94325572, ++ 0x47ae25eb, 0x27214e03, 0x9bd90a3d, 0xbd5742bd, 0xe00961df, 0x615b23be, ++ 0xe2b5e7a5, 0xeef5b7fc, 0xdc65fbce, 0x4ac67e37, 0x7935c6fb, 0xd42b12be, ++ 0x79e4f66b, 0xff24599a, 0x33b526b9, 0x3916b273, 0x49f58987, 0xaeff645a, ++ 0x28dd6bbe, 0x6f783fcc, 0xef846bff, 0x08f292d7, 0x51d0babe, 0xfda4efd5, ++ 0xed0bd54c, 0xae0c73df, 0xb5deb47b, 0x78293c39, 0x77e067de, 0x2db11efc, ++ 0x89be671d, 0x4afefef2, 0x3bfee98b, 0xfa003ca3, 0xf18e0bcf, 0x90b04df3, ++ 0x041dcf01, 0xfd0b99f9, 0xba77afbc, 0x5e2dbe10, 0x8a6825df, 0x988d2597, ++ 0xda3e00e5, 0x2dd5ef9a, 0x6dbb1893, 0x3b36b8cd, 0x555bf518, 0xbbe462fd, ++ 0xb62692db, 0x38d75f21, 0x0577ca64, 0x7790f10b, 0x804fc88c, 0xda9ace7a, ++ 0xf7efb859, 0x0a82ed95, 0xb0d1fdb3, 0x806bef9e, 0xfc8a505d, 0x80f48f53, ++ 0x4ddec5ba, 0x4b6f7fe7, 0x322fc262, 0xa41c579f, 0xce3c8deb, 0x8b73be7b, ++ 0xe8936755, 0x7f51a27c, 0x7a4dc92d, 0xd0094aa4, 0x59d54f3e, 0xfc6b9d17, ++ 0x4dd8e3fa, 0x8e8723e7, 0xc61c11a3, 0x7191b538, 0xbed57f48, 0xe1fc8076, ++ 0xf6189703, 0x59e297ad, 0xbc8877cb, 0x38778713, 0x55f943f6, 0xb3d01f44, ++ 0x6f257780, 0x40501eb0, 0xd41c1cef, 0xcadb333b, 0x51be9172, 0x49ba687a, ++ 0xa015792f, 0x4324c1d3, 0x7e2b7d2f, 0xf698a4fb, 0x7afd46f9, 0xcf0b1f6a, ++ 0xba911c4f, 0x9f2bda1d, 0x08eb06db, 0x8fb39d1f, 0x18cd2fee, 0x9fd47bff, ++ 0x49397fc1, 0xa0028715, 0xfaa60e5f, 0x19fd704a, 0x51b991b8, 0x06571e1e, ++ 0x3a289e1c, 0x75f124e4, 0x25eceaa1, 0xf047fc26, 0xffa2645e, 0xd36e4dbb, ++ 0xed92f07e, 0x98f9d077, 0x2c5e831c, 0x6d7bcfc0, 0x03ed302c, 0xbe387fff, ++ 0x04de1c2a, 0x9dfd9470, 0x1a6718e1, 0x78c7022f, 0x155f7c13, 0x86f5390e, ++ 0xbf6879d9, 0x9ee85b35, 0xc04b4cc5, 0xd3768f9e, 0x9bb2169d, 0xf984b430, ++ 0x9358605b, 0x8091241e, 0xb6bdee76, 0xe45f9805, 0x2511d856, 0xebc9e50d, ++ 0xfe7b466e, 0x17f90a07, 0x9d6edcf0, 0xc3b0aa8c, 0xb141f78b, 0x730edc15, ++ 0xf8ebf857, 0x3fbe6fa1, 0xd5e84238, 0xe0959d02, 0x27f7a13d, 0x192ab82f, ++ 0xbbcf75e0, 0x6ddb01b3, 0x6a9fd2d2, 0x25792663, 0xba4da4bb, 0xf583017d, ++ 0x95a4d3e0, 0x4f0cc764, 0xc48c76e2, 0xb91db656, 0x2e7bde3c, 0xacd767af, ++ 0x8471859c, 0x12ecdde0, 0x8e82a7f4, 0xa401e760, 0x41e69b43, 0x1bdde43a, ++ 0xcbf9c76c, 0xdd6858f7, 0xdb835394, 0xbefd6336, 0x15da0f42, 0x5fae54c1, ++ 0x3a359a07, 0xc9aab467, 0x95f78b9d, 0x75f074b4, 0x0ceb7360, 0x9578c25d, ++ 0xf7c15806, 0x68f9c6d6, 0xf7bb4f6f, 0xe5fb3691, 0xed3cc7a8, 0xcf5e74c3, ++ 0x8d75c6ca, 0x8927dbe5, 0x05aeb0f7, 0x9e8e599b, 0x7c17a91a, 0xe908d60e, ++ 0xbcda4799, 0xdcefd8b9, 0x3fbfc66a, 0xad8b7184, 0xbf887a83, 0x3c09a777, ++ 0xe9f31d41, 0xfbc8e6e4, 0x13ef9832, 0x953d728f, 0x7207fd0d, 0xb2013e69, ++ 0x342ac61b, 0xed8c071f, 0xe2e3ba82, 0x0bf7da7c, 0xe07d783a, 0xd8defe62, ++ 0x5ac751af, 0x21c6bf68, 0xe6c8e1f0, 0x2ff055ed, 0x382fe8c3, 0x29c7ee35, ++ 0x57cc32de, 0xcff198d3, 0x6293e3cb, 0xef09233f, 0x47e28807, 0xda32eb7b, ++ 0x318fb6ac, 0xb9abd3ef, 0x3cc2bae6, 0x92dfd10b, 0xabf3f375, 0x3e3c4592, ++ 0xfee3658d, 0x4fc5814d, 0x2c45d8f6, 0x17f6c160, 0x979520b3, 0x9f3d30b2, ++ 0x3ea87ac0, 0x05a64311, 0xcdc9bc78, 0x8f31640f, 0xe663768c, 0xe4ae237c, ++ 0xd9f6859f, 0x571164cc, 0xa1fe86cb, 0xa99cfa5d, 0x357e1fb4, 0x9378c7be, ++ 0xb303cc6f, 0x8f17e4dc, 0x8cf7b68b, 0xe7b0d2f5, 0x3dcc042a, 0x7b5c52c9, ++ 0x2aefb0c1, 0x5fdebc1c, 0x0d9012a9, 0xfd8210b8, 0xb0b1dfd7, 0xc62ce31c, ++ 0xe2295efa, 0x4a1b959c, 0xab7ed132, 0xfc9f3fd8, 0xb992bba0, 0xfd78b6fd, ++ 0x013fd51c, 0x202d87cf, 0x8e22a0bf, 0xd4f976fd, 0xc896fd88, 0xdbb5885e, ++ 0xe88bae82, 0xaac02b1e, 0x3a45ef17, 0xf5af7568, 0x33dc7ca0, 0x9829e486, ++ 0xa15255e4, 0xf6e65c1e, 0x97dc30b4, 0xf1ba8770, 0xe8938ffd, 0xb8a0e4de, ++ 0x1f30695f, 0xd2affbc0, 0xc789c917, 0x3807cd8f, 0x2dfdca98, 0x9207fe63, ++ 0xf4851fde, 0xdaf02b98, 0x85dc96a3, 0xbd51e974, 0xd2acb173, 0x748cfffc, ++ 0xf0a73d5c, 0x422c5981, 0x867cd8bf, 0x1afb04f4, 0xaf7e8957, 0x86d3b6c2, ++ 0x73a0cdd2, 0x5cb5ddac, 0x13a0e7e2, 0xace1abcd, 0x23e7a4c5, 0xa4a854f7, ++ 0x3f84fbe7, 0xbfcb3872, 0xe9204afe, 0x215bacd5, 0x7bf717fe, 0xaa0148b4, ++ 0x73159d5f, 0xb3c88cbf, 0xfb7a1729, 0xe33f9877, 0x9e3befc2, 0xd73f42f7, ++ 0x7c82a0b0, 0xd9e4587f, 0x44a4bf80, 0x0946c9fb, 0xece49afd, 0xfd736e9b, ++ 0xfae6719a, 0xeff13db7, 0x49b7bbc3, 0xddd7ed37, 0xe327e78b, 0xf08f65e0, ++ 0xbdfabe8b, 0xcf362c46, 0xbdd20f71, 0x494bf30e, 0x639e79be, 0x879f83b2, ++ 0xf077ef08, 0xba9a16f3, 0x0d034309, 0x1fa257e0, 0xf784ec9e, 0x899fb9e3, ++ 0x5b24d4f7, 0xbdc8fb79, 0x9f6e3c44, 0x7112cbe1, 0x9cd64f03, 0x6e1e5f09, ++ 0x4f2857f4, 0x230f615a, 0x9af9227d, 0x4e31fbe6, 0x8c59bf27, 0x73e611fa, ++ 0x8c01c623, 0x9f31a878, 0x739f97bf, 0xc44f88af, 0x64aeedd2, 0x20b4b76e, ++ 0xd8e2a39d, 0x77ce82ad, 0xdc00dca1, 0xeefb8a1f, 0x947c921f, 0x016995e7, ++ 0x59882c6e, 0xf2eda3e7, 0x65ada7c0, 0x7870cf18, 0x42bc518e, 0xa92de5d8, ++ 0xf787fdfc, 0xe7e8e548, 0xffd60db5, 0x86f186da, 0xff518736, 0xf25bd50b, ++ 0x47c60e58, 0x1f7f0ebc, 0xe779efe2, 0x67bc6143, 0xcd9765b7, 0xe907f94d, ++ 0xf9e26fdd, 0x36ddcc95, 0x8cb5df8a, 0xacfb4f3c, 0x2c79f698, 0xb09a7284, ++ 0x4fb42e7d, 0x5d67b48f, 0xb473a649, 0x667e5f86, 0x35253b8c, 0x4a31fe8e, ++ 0x74c5836d, 0x255add6f, 0xb17d476c, 0xb3f3c3d6, 0x6832fa22, 0x1b6b278a, ++ 0xd9476940, 0x33df788d, 0xb1555906, 0xe29f7c8f, 0x94f5a3d1, 0xd8e9f566, ++ 0xb939d5af, 0xec61eddb, 0xca7ad69f, 0xc16b77d1, 0x2bb060bc, 0x55acb5f2, ++ 0xd5a75788, 0xe9e70473, 0x98dc5a74, 0x59acdb27, 0x745a9e48, 0xb6bde53b, ++ 0xc8ead74a, 0xcebf46b7, 0x30e0851e, 0xe689e5e2, 0xcb9f80a9, 0xdf35cfc8, ++ 0x37bff593, 0x1d78469e, 0xc1d72f72, 0xd1b88fcb, 0xa16a99ae, 0x4b252e7c, ++ 0xc9c4ef63, 0x6f1c1ccb, 0xee171283, 0xfe0676d8, 0xdad9d213, 0xf47a42e3, ++ 0xcdf7f169, 0xf5f49afd, 0x312de4f4, 0xc7f9c5fa, 0x61f030c2, 0x9df3d49d, ++ 0x7f923c82, 0xd7fd06bf, 0x2ae33a4f, 0xa19e9375, 0x9f4352fd, 0xdb2f68b7, ++ 0xf9b0be79, 0xfc44b63e, 0xfac5e067, 0xf3c622e2, 0xfb0cbd19, 0x9c1e1f3b, ++ 0xf947d852, 0xb8949331, 0x29e0a1fb, 0xf0a9f298, 0x7ce8ec7e, 0x6be4169b, ++ 0xcabe5380, 0xa17b476f, 0x1dae6b39, 0x14abebe3, 0xffb875f7, 0xd822f03d, ++ 0xcfdc6e3d, 0x518fcb35, 0x7bfb8bb6, 0x712cd3ef, 0x8bb575ef, 0x9f63e47b, ++ 0xda7d0487, 0xe74e5ff7, 0x0ff112e4, 0x5c3e6358, 0x8ac5ec47, 0xcb81f78e, ++ 0x23af0e56, 0xf4621d81, 0xf75f089b, 0xfbf077ec, 0x83d8c7bd, 0x8ec59eb8, ++ 0xf6e786d7, 0xc01b7de0, 0x2e7ac013, 0xaa6dbf1f, 0x8743f142, 0xa3d9893b, ++ 0xa6335bda, 0x68cffe12, 0x908678e9, 0xc63f21b5, 0x53c0cb81, 0xbd7cb340, ++ 0x0c7f3f7d, 0xb57c8e5f, 0x8a25f910, 0x4da17f2f, 0xb897ca1b, 0x105e2006, ++ 0x36fbe8fe, 0xe26319ad, 0x84385bde, 0xa6f8633f, 0xf3a30678, 0xdca1c379, ++ 0xc4877d04, 0xa8753a3d, 0xab9fc1cb, 0x3a6359bd, 0xae25fbe8, 0x4f088392, ++ 0x7e01f771, 0xc194264e, 0xdf1407ef, 0x71eb8ec7, 0xe3d275f2, 0x394ca9d4, ++ 0x7f1a7de6, 0x9dd421b7, 0x8a73c6e4, 0xbff8b4a1, 0x66a1f163, 0xe21d0bf8, ++ 0xc50f419c, 0xc5f68db7, 0x66ef30b7, 0xb1250f28, 0xd5d83b76, 0xcf22686f, ++ 0x888bfd81, 0xc2e083ab, 0xfafdd738, 0x308fca52, 0x68087fe6, 0x3333ed86, ++ 0xf9248a7b, 0x1b6dd06b, 0x568bdd33, 0xba21ef67, 0xdff8b7cd, 0x1c34fc43, ++ 0x7ac4c9eb, 0x6453e5e8, 0x70b467a7, 0x4f6069fb, 0x4397f932, 0xf04cd3e9, ++ 0x61cd9ed5, 0xe9436181, 0xc984ab56, 0x3b3dae4e, 0xd0a6058a, 0xb4f603bc, ++ 0x6cebfbc8, 0xff474d8c, 0x84f1cec2, 0x8f4789f8, 0x1b5c8497, 0x74bd00f4, ++ 0x03d053a9, 0x6f4834f1, 0xaf487f71, 0x6dee97b8, 0x9d337f61, 0xbdc675fb, ++ 0x0e176f44, 0x3dd3d3ee, 0xef0eb54d, 0x07df7803, 0x7e532a3b, 0x7e52a2df, ++ 0x9b22deef, 0x05e30537, 0x4b2f7e8b, 0xc62fb4cd, 0xc0b17ef9, 0xd0f32f5f, ++ 0x5ac0f5f9, 0x63efce87, 0x791bfb32, 0xf94c950f, 0x74a9e61d, 0x1657a4c9, ++ 0xec016a96, 0xe67bb8b7, 0xa45e78d3, 0xce993db2, 0x86fa2f2f, 0xf9fa04e7, ++ 0xb8701e8b, 0x964277f1, 0x925f96bf, 0x7f2efd0d, 0xf9474f30, 0xcbe15e4f, ++ 0xbb187bb2, 0x472c19d6, 0x5a4da93f, 0xc49a40b0, 0x6cff3740, 0x95d7c615, ++ 0x77df4bcf, 0xb3ae7d40, 0x25c6156b, 0x50f18d7e, 0x94f6d3b2, 0x14f93fa3, ++ 0x5fc469fe, 0x1d4f0701, 0xc3b888b1, 0x40caab0b, 0x11925fe5, 0xf30068b2, ++ 0xb0bdf703, 0x66c1cf0a, 0x592779a6, 0xbb7fbc60, 0xfb72a5ef, 0x03f70055, ++ 0x00de3e13, 0xdf737fef, 0x017d90ff, 0x1fdf1274, 0xef852f2f, 0xf518672b, ++ 0xa7ac54f7, 0x9d88b327, 0x3be41d38, 0xda3e323f, 0xb8c1a185, 0x32f2e9c8, ++ 0x99edf6f8, 0xf40aa58d, 0x0fbef27f, 0x44078d57, 0x44beb65d, 0xa7f8c2f7, ++ 0xe688fbef, 0xc7e2321b, 0xd1564f81, 0x1ff3173e, 0xc57bc2b4, 0x476d5d25, ++ 0x37cc3a55, 0x0ff98749, 0x3d5c2f6b, 0x90d7e47b, 0xce43718f, 0xcceb5d5f, ++ 0x8c393920, 0x82b51d28, 0x283777df, 0x6f9cb9df, 0x7ae3eb07, 0xa309f9f8, ++ 0xa1ebc59e, 0x0bebe3bb, 0xc3d70a57, 0xeff8a4a1, 0x043d0a97, 0x9c530ef8, ++ 0x38392bae, 0x3fa22f36, 0xd3ec7e40, 0x71d69e49, 0x847201fd, 0xb7206679, ++ 0xb2fbfb71, 0xf7121af2, 0x6f148761, 0x86cbfa32, 0x4bf9031e, 0x4edc71c6, ++ 0x2b9d69b7, 0xfa485eee, 0xce9703f5, 0xfc7371e1, 0xf59a9464, 0x1777b308, ++ 0xabb1fb46, 0xe66f5c9c, 0x53ec6a5d, 0xfde8d584, 0x4a3be589, 0xb63e79ce, ++ 0x51c1e316, 0x1e6476f6, 0x0f9fe465, 0x73fa17e9, 0xe33dfe8b, 0xfa5f042f, ++ 0x4e95f079, 0x3cdf3af8, 0xe399fd23, 0x53fb4309, 0x8751fec5, 0xe3511d79, ++ 0xc08cf9c3, 0x12dfe21f, 0x852b3fa5, 0xcff6353e, 0xbc5f76fb, 0xf45e4d79, ++ 0x25bcfcb8, 0xfc69f7d0, 0xe8009ebd, 0xc563d453, 0x6c1af78a, 0xa69ddc5f, ++ 0xfc0efda3, 0x4df82ad6, 0xe8337e41, 0x2c6b4a1c, 0x93aef9a1, 0xec71cdf4, ++ 0xbfc190be, 0xd65efc1d, 0xe5f8b7e1, 0x19f05105, 0x0ffa1efa, 0x72a7fe89, ++ 0x90747e7e, 0xf9456f9f, 0xf329fe11, 0xdcbdd0f4, 0x825ff0b1, 0x6a2d3732, ++ 0xa0e5dabd, 0x6f03173c, 0x0dff955f, 0xe136a17b, 0x3822e4ba, 0xbb0b1f87, ++ 0x08aed0dc, 0xd9f101e5, 0xafdd0ef9, 0x1992ea18, 0xf38f755e, 0x6c51bd46, ++ 0x795649e8, 0xb218e678, 0xd97a225b, 0xa18bf64d, 0x7b76c337, 0xad3efda4, ++ 0xf515bcb2, 0x3d9fb8aa, 0x3e2d065d, 0x3bc70239, 0x4e3ebe4e, 0xf7b8b3f7, ++ 0x39a87edf, 0x79887f39, 0x2662bc3c, 0x2c509bdd, 0x3de9d3d6, 0xbc9f8a01, ++ 0xbeb131ac, 0xeb187c72, 0x9eb675f5, 0x41f38b9f, 0xea347e26, 0x5bd49760, ++ 0xe3fd220a, 0x7c51b9fb, 0xcfe0b9ff, 0x5d7cfa58, 0x087804fd, 0x08661e20, ++ 0x1d4067bc, 0x0a60afef, 0x2f985fac, 0xacf34732, 0x5b828bc9, 0x4338fae3, ++ 0x763d70b6, 0x1f48b91e, 0x78efc4c6, 0x239e4938, 0x4b76e0f8, 0x7de38ba1, ++ 0x78a73893, 0x427202c8, 0x9e7c31fb, 0xa9b3bb7d, 0xeed15cdf, 0x3797a56f, ++ 0xc3177c89, 0xd5fbac5e, 0xf8664d88, 0x763f7f79, 0x1f14bc71, 0x3b424ef3, ++ 0xf34fac66, 0xdc507fa0, 0xe600f73d, 0xc5ee141f, 0x7c23e78b, 0xe5c9d85e, ++ 0xe04bb814, 0xd1edc5e5, 0x39734efd, 0x9bfb390d, 0x18f0a3cc, 0x3971e313, ++ 0xbb97da37, 0xcc0e3e34, 0x54f886cf, 0x28d47acc, 0xf87076ff, 0x9639e00e, ++ 0xaa07c05a, 0xa16f036d, 0x3b7705ce, 0x318f8e50, 0x5f71ca0f, 0x04cb02e7, ++ 0x10262ba4, 0xc3f4a3b9, 0xc30f3e7a, 0xecbe050e, 0xe79cbe44, 0x8cfd491a, ++ 0x1e4de63d, 0xa2c7ef0f, 0xef1534dd, 0xd10670ab, 0xf2e2588f, 0x7c85d8ff, ++ 0x2940c371, 0x93eb77c6, 0x511d9b1b, 0x77db07cf, 0x63e27b41, 0xe1013cbf, ++ 0xf7e33efc, 0x40f98b8d, 0xc60d80d3, 0x4e4153ab, 0x461ea80b, 0xde5485bc, ++ 0xfa56e07e, 0x2f560a85, 0x60ddfbf3, 0xf886befd, 0x1a4b65f3, 0x24fd17d2, ++ 0x656b93b4, 0x8fe52e5f, 0x7079b70d, 0x83bf001d, 0x8390fdf8, 0xffe80e29, ++ 0x4f512805, 0xa76f92cf, 0x0ab33f73, 0x3037da24, 0x5bd47bfc, 0xf75d27e8, ++ 0x47e2648d, 0x631dd9f6, 0x919ade30, 0xfd04e9cc, 0x763f45d8, 0xfc88e4fb, ++ 0x8ba8e7fd, 0xd631dfc9, 0x449243b7, 0xeaba1cfd, 0x512dcdd2, 0x87f6107e, ++ 0x3490fffa, 0xe476f727, 0x91c7e17f, 0x591e987d, 0x995ed177, 0x3dd345ac, ++ 0x19ebe020, 0x6d147c85, 0x3a7da28f, 0x59b2cf68, 0x3d06afab, 0xceecd97b, ++ 0xde8d5e30, 0xeafab81c, 0x59bfa0bb, 0x003acf60, 0x2f82ed0f, 0xdff1e50e, ++ 0x56343d0d, 0x0fc07ba2, 0x37c7f927, 0x3271916a, 0x5321bc45, 0x266727e4, ++ 0x853f32f1, 0xa29dc1eb, 0xf6c36e24, 0x89f1f8ae, 0x5ffef15c, 0xac7f5c2c, ++ 0xc79f8929, 0x6bebb4fc, 0x4bc699c6, 0x3f3cf7b1, 0xf710caed, 0x169e533c, ++ 0x109f5f8f, 0x21cec1ed, 0x2aec453a, 0xb0dcce7e, 0xe6f38d43, 0x07be4975, ++ 0x2af42e28, 0xfc7155f8, 0xb8b83fc7, 0x135ef07d, 0xefd673a3, 0x42f3b9e2, ++ 0x584c7bfe, 0x41f2ba5f, 0xcd5d6f3a, 0x5e3fb482, 0x9d3645bd, 0xd958aee7, ++ 0x59b7bf46, 0x5b989411, 0xc7ccbf42, 0xfc0b65cf, 0x551a512f, 0xfc2f3dfc, ++ 0xefe8a67d, 0x894e36aa, 0xeb95a7b9, 0x7f6eaf8b, 0xf7ed34ce, 0x394bf447, ++ 0xfdb179d9, 0x6b1cfc1a, 0xe4ddbe87, 0x5f379d36, 0x396c72b8, 0xede59cdf, ++ 0xcd0f3117, 0x817b516f, 0x1dfc7e19, 0xc313cba9, 0x2c8f7837, 0xb8819dd8, ++ 0x07a4aa70, 0x036fe78d, 0xe75103fe, 0x1c9e17ea, 0x776c7043, 0x2f91fbf9, ++ 0xb3247022, 0x364e2980, 0x9d8eff83, 0x8119c783, 0x5ae7024f, 0x5f29adef, ++ 0x24bfeed7, 0xf45fdd81, 0x8bfbb577, 0x967ae16f, 0x2c6c4875, 0x662de5f2, ++ 0x45332c3b, 0x929e72e3, 0x850f731c, 0xe0cc7b88, 0xdfe182f6, 0x2d67850d, ++ 0x19597f7d, 0x90ec17ef, 0x1e5ec2ed, 0x7fe5edcf, 0xbf97b41b, 0xa27fe517, ++ 0xa015265d, 0x19dfe33e, 0x77943bbf, 0x1fca65ea, 0xb70a7efc, 0xdeebe75f, ++ 0xfda0528b, 0x3eaf915a, 0x7bf17c64, 0x83ad6b44, 0x3f94d2fb, 0x3bf3e9b6, ++ 0x25f7f05a, 0xfd807606, 0xe4b07a0f, 0x1ee9e7d1, 0x6fbbe32e, 0x5d1ce8af, ++ 0x269bf801, 0xe1eb5ce8, 0x27ad61f6, 0x7e818eac, 0x5c396a72, 0x25fb9db9, ++ 0xdcbbea25, 0x1beede2a, 0xfc535629, 0x4bd44caf, 0x1efcdc52, 0x34b0aab0, ++ 0x6ce5da06, 0xd82922dc, 0x131efe1f, 0xc8d393c0, 0x43bfd182, 0xdb953394, ++ 0xba9edf35, 0x3e345a49, 0xcb768782, 0xd03af19c, 0xd9333dad, 0x13cceb83, ++ 0x885bffba, 0xc237da87, 0xd97f5f94, 0xda0add1b, 0xef74bbed, 0x11192935, ++ 0x3d65b83c, 0xe4d1d707, 0x1d9c3837, 0x5f317e83, 0x94e7685f, 0xdb99bce8, ++ 0xc23b327d, 0xeb485db8, 0xe3dde654, 0x976bbf4c, 0x89d62699, 0x7ca7e64c, ++ 0xd3b59962, 0x38ca3bbe, 0x5ddd5fee, 0xb1db99b8, 0x1566ff9c, 0xf3e0b6f8, ++ 0x9e2fc359, 0x1443f78c, 0xf82b0dac, 0xdabfd57b, 0xbbee3f18, 0xe61fe054, ++ 0x33f38151, 0x7d3e71e6, 0x26b3b461, 0x72184f88, 0xbe3b3c92, 0xfdd8c1df, ++ 0xa68f5e9c, 0x41ee977f, 0x77e9556c, 0xeffc0cc8, 0x21777dd2, 0x9b9d393c, ++ 0x188dc224, 0xe1db88cf, 0xb7d79473, 0xc039f355, 0xc560fa84, 0xd115d1ce, ++ 0x2555a0fa, 0xc98a6cfa, 0xfbec370f, 0x72fe2275, 0x23b5f75c, 0xd6bbeb7d, ++ 0xe9677c51, 0x317bfe16, 0x8173f109, 0xb8aa93f8, 0xb3ced75c, 0xc94e3e53, ++ 0xbfd10aa3, 0xaeff95a6, 0x1df6ed67, 0x92b3ae3c, 0xd46f5079, 0x2a90ee76, ++ 0x27efe3c6, 0x471690ee, 0x6d4473e1, 0x2fa7f290, 0xc7f21a72, 0xbf2c59f5, ++ 0xed189c63, 0x6e0ec394, 0x6896f5b7, 0xed1fdc01, 0xb16bfab5, 0xb2766f5d, ++ 0x0c80f307, 0xe3b0bffc, 0x7037ca6a, 0xb185b4ee, 0xce6cb76c, 0xf6bb43b2, ++ 0xf20f544b, 0xffdd2ed5, 0x4d25e20c, 0xfbf085f1, 0xa7a774d4, 0xdb75be19, ++ 0xbb5d64d8, 0x165c3c70, 0xad971fc3, 0x3ff372e4, 0x4e487fa8, 0x9b9464d8, ++ 0x7fb85217, 0xf913f601, 0x7cad8757, 0x87193b1e, 0xbbc53f37, 0x48f7f897, ++ 0x539b8d1a, 0x5e30961b, 0xa76a779d, 0x845a7ce9, 0xbe07bcbf, 0xdd83bf0c, ++ 0xd5bf22a7, 0xf253fd08, 0x9de916e8, 0xa68fb828, 0xce5f04c8, 0x8d4be076, ++ 0x66ffefde, 0xfba7b53a, 0x4bb6733c, 0xbc0d5df4, 0x67a51c5f, 0xd1c4798c, ++ 0xbf10c737, 0xcfdd1bda, 0xe6137d73, 0x6f0145f1, 0x0b8f3d2c, 0xcb0e57bd, ++ 0x03573d35, 0xf3df70e3, 0xf5127e70, 0xac7fc867, 0xe14f1ebc, 0x49ea23f6, ++ 0x59f1468b, 0xf80d23b2, 0xf5f3768c, 0x08532799, 0x8784dd0f, 0xcd0a8dba, ++ 0x1bea9667, 0x3c947b73, 0x3bfa2c7c, 0x749bf370, 0x5ffad35f, 0xac7e251e, ++ 0xeff890eb, 0x551c76e3, 0x40f8c46f, 0xed1949e0, 0x89b86bca, 0xf7121ec0, ++ 0xe2135da4, 0xb42eb8fa, 0x337bc143, 0x3bcd3e0d, 0x57ee8075, 0x31b4ebab, ++ 0xff8083f4, 0xc5fa433e, 0x1f81a9f2, 0xd2c6df43, 0xcf02fff3, 0x0085c0de, ++ 0x000085c0, 0x00088b1f, 0x00000000, 0x7dd5ff00, 0xd5947809, 0x677df0d5, ++ 0x2613324f, 0x930842fb, 0x840a2584, 0x10424849, 0x58424994, 0x28027164, ++ 0x0b61b641, 0xb4a9b201, 0xcff6ac7f, 0xbf229060, 0xdd6d1bfd, 0xad101dad, ++ 0xc1410bad, 0x08380c06, 0x236d5622, 0xda2b15a5, 0x27b22951, 0xfe2d7e8d, ++ 0x9cff95fa, 0xcccdef73, 0xc58666fb, 0x17cf3ed2, 0x7dcb9f1f, 0xb9ce7eef, ++ 0xce7b9ce7, 0xf31877b9, 0x58c49632, 0x58c664cc, 0x35effc21, 0x416706f9, ++ 0x33593cca, 0xc6b58c6d, 0x2b6e45b3, 0x74fdd963, 0xf9598f54, 0xcf3b34f7, ++ 0x6df02bd7, 0xec3b630c, 0x117b589e, 0xee391563, 0x454fd82d, 0x05b3944a, ++ 0x553ac9fa, 0x912586f0, 0xe2a73ab1, 0x89aa828c, 0x70dfd0e5, 0x343b47f8, ++ 0x0271c34e, 0x18239599, 0xe37f80bb, 0x6b632983, 0x92fe8319, 0xccf8f812, ++ 0x71c4c810, 0xeff1f319, 0x1581b67a, 0xd867db04, 0xf81f341d, 0x59dfe7ee, ++ 0x70447bb6, 0xb29e72fe, 0x8576c9ff, 0xaba0d9fa, 0xf9876e1c, 0x718e486d, ++ 0xa7a7c0b6, 0x76c19eed, 0xa8f6a7e8, 0x8dc38fdf, 0xf069da3e, 0x871d7158, ++ 0x6fe80e4c, 0xc9ba93d7, 0xf2ffc83e, 0xb2a50349, 0x89bb42bf, 0x1bb42bfa, ++ 0x970f1e68, 0x3f4abd5a, 0x68b88d48, 0x7c5ad748, 0x5bc7805e, 0x541e2773, ++ 0xddb318f2, 0xfa63f26a, 0x2d496ea6, 0xce99bf96, 0xd3a0dfc7, 0x0df98edd, ++ 0xe61958f7, 0x455dd877, 0xe637d708, 0x6a7e12c4, 0x333e4cab, 0x57b3f3f4, ++ 0x5af79e14, 0x59fe0c7d, 0x0cbd99eb, 0x28c4b1db, 0x3f8833e7, 0xcdd37ecf, ++ 0xafef00b8, 0xb1992cf4, 0x39ff8ca9, 0x726bde5e, 0x6da9f7c0, 0x8217cb8a, ++ 0x6db6da87, 0x1eb0a586, 0xb780b463, 0x9e106b80, 0x4d13ee1c, 0x1f151bcc, ++ 0x3f7647c4, 0xa00ba73b, 0xeaf78417, 0xc7eca2e7, 0x0bac7c2c, 0x5b5d7ff0, ++ 0xd0df2a9c, 0x963f669e, 0xc6afcc1b, 0x6c1d207f, 0x679c5661, 0x5ce798ad, ++ 0x5c16e79d, 0x70259d77, 0x2da808c0, 0xf26dd23e, 0x09d1c358, 0x4dd5dfa7, ++ 0x6c721dbf, 0x52ab6314, 0x189a520f, 0x98cce9c3, 0xeb23d7cd, 0xbf78152f, ++ 0xb7685311, 0xf206e90a, 0x4cdb0bab, 0x3eafea0c, 0x407268d6, 0x08cc9d6a, ++ 0x90a3d63e, 0xfbc7435a, 0xec67d531, 0x115f6a7e, 0x0f5136d3, 0x85f8af70, ++ 0x7d616f62, 0x15d327e7, 0x41b7730a, 0xb93c5f7f, 0xc231762f, 0x7a0bdbf7, ++ 0x8deb0c56, 0x0bbdebe2, 0x7bf413f7, 0x380039e6, 0x89a37bd1, 0xe5ef5985, ++ 0x87fcc7f6, 0x6ae78415, 0x2f33fb01, 0x2bf98f94, 0xb9f78bd0, 0xb0c1ce7e, ++ 0xcc2fd3e4, 0x30aff3ba, 0xc65b33ef, 0x3648f53b, 0x9fa26e2d, 0xe728a4ee, ++ 0x449fa066, 0x00ac9b3d, 0xedb6d7de, 0xed0b1d8b, 0xb23f3e4e, 0x1eed0cc0, ++ 0xd4fefb14, 0x8426fa2b, 0xdcbf3dcb, 0xaf96037a, 0x660929f6, 0x5fb9e71c, ++ 0xfa1d33fc, 0x80d2d9a9, 0xcf2d6610, 0x400a6ebf, 0x136f9d3d, 0x3f5cfeff, ++ 0xf93bd63b, 0x203703f4, 0x5ada5bbc, 0xd3d4fca8, 0xc6ff289b, 0xf9eeb72f, ++ 0xd6af507f, 0x7ac4eb1d, 0x4bd95ea7, 0x18f5a978, 0x48deb85c, 0xb6f0fd74, ++ 0x813fb4bd, 0xb1bf69ae, 0x24c7ce2a, 0x3dfa4b5d, 0x6345cbf9, 0xfc828e90, ++ 0x00df7f87, 0xba016d74, 0x18cd10de, 0xb169f7d2, 0x5997577f, 0xfa7a6037, ++ 0x5c2aa8c5, 0x3029bd6f, 0x33e70e24, 0x4f85d39c, 0xedb6ade0, 0x95bd6336, ++ 0x7f3f53da, 0xe98f7d82, 0xe3cfa008, 0x6b50ef40, 0x385185cb, 0x3f044bde, ++ 0x051257a8, 0xff339df0, 0x13e70553, 0xb8d1bc33, 0x3cf9e69a, 0x8755872f, ++ 0xe1af1796, 0x83a5a8f4, 0xa0ab765d, 0xd20fbe47, 0x386657b7, 0x9d980f88, ++ 0xf5f38f9c, 0x5a78d7a5, 0xc6fdf06c, 0x1ea71e35, 0xc4ebb8f0, 0x21fd89a1, ++ 0x655ccbff, 0xaf5fe114, 0xf7a97ed0, 0xba9c695a, 0x39f632a6, 0xb16df7cc, ++ 0xcced925f, 0x81f11d70, 0x0dee9c4d, 0xbcc560cc, 0x44f89ba1, 0xda4e86dd, ++ 0xf85b7537, 0x3ba5993c, 0xda8d9673, 0x0f8baf59, 0x59da03ce, 0xceef94ad, ++ 0xca0465bc, 0xc9156f1d, 0xe689871d, 0x03f24a7b, 0x305bcde6, 0x92dfb822, ++ 0xf883cc75, 0x6a41364f, 0x12a6fce5, 0x2f663ffa, 0x6bf20bfd, 0xf3472699, ++ 0xd29c2d72, 0xf4f978e2, 0xeca51738, 0x3c9504b9, 0xea57c488, 0x561ffe05, ++ 0x5748d502, 0xf6519dde, 0xf5240067, 0x84860437, 0x38a495f2, 0x8273a70e, ++ 0xe4edce6e, 0x4ea6f2f4, 0xbdf5c5e7, 0x26d879b9, 0xf95ae7e4, 0x09b8d4a6, ++ 0x2f80f55f, 0xfe979433, 0x29a1cd7c, 0x986b2f28, 0xfd5bf713, 0x8dcf4176, ++ 0xbeb9e88c, 0xf61972bd, 0x8a713fd7, 0x5ca0af53, 0x7f6264f8, 0xb2d7d7c8, ++ 0xe92fdc22, 0x44ed964f, 0x8576b2bc, 0x8d7cc60d, 0xbfb63b7b, 0xa9ceb131, ++ 0xb5b942cf, 0xf502d539, 0xa62dcc6f, 0x700f0ff6, 0xde7f6294, 0x7aeb460a, ++ 0x7921e8d8, 0x30da70f4, 0x7aabca27, 0xa25cbacf, 0x13b44727, 0x70c799cb, ++ 0xf7afd63b, 0x951b67ce, 0xa770fb30, 0x5f72a2e2, 0xda0a2f8c, 0x68576d4f, ++ 0xf3b7d49f, 0xc256787d, 0xcec6a647, 0xb9de3885, 0x55e6661d, 0xd6f27482, ++ 0x4e5c49ce, 0x39266abe, 0xc5d9ba79, 0x7ad1073e, 0x0979c84a, 0x642fd5c7, ++ 0xb33f68e9, 0xc79c6659, 0x568f3152, 0x71fbe723, 0xdce78f82, 0x2391e7cf, ++ 0xa71394f0, 0xc849a913, 0x8fbe56af, 0x943cdeec, 0x78c56763, 0x1648e7f8, ++ 0xae860a72, 0x3a27e65b, 0xf7817daf, 0xe5766897, 0x074211df, 0xd2d1bf52, ++ 0x971c5953, 0xee4fe937, 0xa4199057, 0xb553393f, 0x61ac6f4f, 0xe75806fe, ++ 0xfcea4f8d, 0xef48f3e3, 0xf1f895b9, 0xacdb135a, 0xa26fedf4, 0x82457f98, ++ 0xf9415f3b, 0xfa4ac733, 0x8b3eef43, 0x50a2e976, 0x9c502b0f, 0x770ab42d, ++ 0x9dea0ea1, 0x1139b648, 0x1ce3d36f, 0xdea5f561, 0x6e3d1af6, 0x8f37ab5a, ++ 0xdae94365, 0xe7842ae8, 0x2c9d209b, 0xed0eced8, 0xe6f25ea1, 0x246f4fb1, ++ 0xfd42d37e, 0xe5d9c496, 0x011b0afc, 0xee39493e, 0xd8be5c35, 0x73d6e19c, ++ 0x37d1f04c, 0xd7cc2ce6, 0xb6ccfd21, 0xd9f87ed2, 0x4e12ca6b, 0x70c8206f, ++ 0xfef879df, 0x9e3fb060, 0x923d1071, 0xe8df541e, 0x47a785f6, 0x41ea5fbe, ++ 0xfa528a2f, 0x64cc63d2, 0xdf91c7ce, 0x72a1ea84, 0x8ffdca7f, 0x3c39df7c, ++ 0xff72b748, 0x3f3eee5f, 0xf0fbe467, 0xe91fac1c, 0x77be97bc, 0xb8defa71, ++ 0x9421f616, 0xd87d846f, 0x0fb7c212, 0xffb4bc98, 0x1347640e, 0xc9b81d7e, ++ 0x3a78ef21, 0x48fd87c6, 0xddb4f97e, 0xf21c577d, 0xaf6fcdab, 0xfc15b227, ++ 0x7dd77ead, 0x37a62e43, 0x3fbc0c59, 0x50d7ec0b, 0xb800b1fa, 0x7a94056d, ++ 0x34c7cf91, 0x9920f5a9, 0xe5c7143e, 0xfbd677cf, 0xe9031572, 0xb55f022d, ++ 0xb843cf3a, 0x80fbd40e, 0x13665822, 0x5192fbd7, 0xd89ca066, 0xfd43e31c, ++ 0x79993936, 0x1f330e5e, 0x12dfd8af, 0x4fff52af, 0xb7f5e58e, 0x65fd71c5, ++ 0x4bb7a88b, 0x0ae721a4, 0x9d0e0fda, 0x8fa653e7, 0x3b644f2c, 0xcb951798, ++ 0x4b9ef4f9, 0xc9be7c2c, 0xbcd90cf7, 0xc19f0431, 0x014d757d, 0x7ee739e2, ++ 0x358961bf, 0x6b948e38, 0xf9c1fa5a, 0xf5c3fca3, 0x5c8f0e54, 0x38af75af, ++ 0xb9e8695f, 0x4d6de853, 0x33d78c71, 0xf68bfffa, 0x86366de3, 0x83901efa, ++ 0xd5e6012b, 0xdf2867b0, 0x43ddb947, 0x04a0fdb0, 0xb43c7c4f, 0xec413d1b, ++ 0x133ef813, 0xf3037cf5, 0xef11e39a, 0x04205f46, 0x4f109bcf, 0x66cbbf50, ++ 0x9f61eaf1, 0x3a782714, 0x6f3c60e3, 0x51fa7319, 0xf800fcce, 0xe65bee09, ++ 0xd37e422f, 0x08b102c0, 0x3d5a7fe7, 0xf57e8987, 0x0e58439d, 0x90255ff0, ++ 0x891fdf87, 0xee9ee7e1, 0xa1bef5b7, 0x4b1ecf30, 0x858effe0, 0xc9acf779, ++ 0x9fa17a71, 0xb47d778f, 0xede823e3, 0x85e61d93, 0x7ae0b04f, 0x8b3a2deb, ++ 0x3f982121, 0xb6aab0a7, 0xb8f97c30, 0xf9c363c0, 0xfa85e674, 0xdd32c0cc, ++ 0xe3e7d700, 0xa1bbfc1d, 0x562a84db, 0xe64cf9c3, 0x63e87d05, 0xd709ab1d, ++ 0xce78c4cf, 0xd1c3b6bf, 0xd4f95c32, 0xb7ffce78, 0xd6fdf367, 0x21f149bd, ++ 0x5a69ac1f, 0xec3d37fb, 0x36359aff, 0x8c50a53f, 0xdd8d567a, 0x21e5d7eb, ++ 0x33fe00df, 0xdb3bc092, 0x6f941c52, 0x0e30cf50, 0x0385ed61, 0x25bbf027, ++ 0x6d2d3e42, 0xe46beb7f, 0x66063527, 0x2cfd0719, 0xf40fb8b3, 0xac2fa287, ++ 0xbd9162cb, 0x8eef7f57, 0x293f9464, 0x5c4d5bf3, 0xa3b04e6e, 0xa6b8aa7e, ++ 0x5cc42fe9, 0x90321f4c, 0x06784b1e, 0x778d6cbc, 0x7ac3c747, 0x2463f7e7, ++ 0xc1dfe7ef, 0xffac91f9, 0x5a4f9096, 0x0224f8fa, 0x6509ec1e, 0x5bfe23af, ++ 0xd489dd62, 0x55671def, 0x129ceb7c, 0xa409f678, 0xce6cdb9f, 0x99777867, ++ 0xcefa10ee, 0x7d5ff017, 0xea78475e, 0xd21cefca, 0xda748594, 0xc001f99d, ++ 0xd987757b, 0xfab2f48e, 0x2cf089bc, 0x0cd67ddb, 0x30486e0c, 0xa0c4e4bf, ++ 0x5aee7889, 0x11eb9cca, 0xc4374bef, 0xdf086f30, 0xe9154542, 0xa33cfea3, ++ 0xbc74967e, 0x5de10475, 0x9d10086f, 0x0958b12c, 0x0de7f58f, 0xc1b60f34, ++ 0xdb202678, 0x889fee03, 0xf5c48d75, 0x2e347f79, 0xf830f8ee, 0x69df0298, ++ 0xfc229efd, 0x4aeef48e, 0x4777a50c, 0x578078bf, 0x0e97a983, 0x3d1096dc, ++ 0xd4d86587, 0x9b78eff8, 0xe2ccbff0, 0x5ebca131, 0xa47382ee, 0x2fe4f11e, ++ 0xc50f0fb2, 0x85fd38f7, 0xef8f9761, 0x3fafb174, 0x87fd0136, 0xe35387e1, ++ 0x5e797f39, 0xfbe74bd6, 0x564ce3e4, 0xd7a632f3, 0x3eed0a42, 0x02f916ce, ++ 0xea221f91, 0x47bcf325, 0xf38f93ec, 0x38ed3d78, 0xdb3c0b77, 0x08555c13, ++ 0x37e7682f, 0x89ec5d21, 0x5a7e91f2, 0xf90d7c08, 0x4803edd8, 0xe5fe053f, ++ 0xe305fe41, 0x9ea8e3f8, 0x6b07e499, 0x7806fe04, 0x10722aec, 0x0296367c, ++ 0xd99f209d, 0x766fb66d, 0xf12af104, 0x1ae3c5a9, 0x2cefcf31, 0x862b86f7, ++ 0xc8077b50, 0x5cf135bd, 0x7f7099ee, 0x5c4c4cc2, 0xf8441b1f, 0x5fd13a22, ++ 0x8a6ebe3e, 0x7d8078e2, 0x49e3bffa, 0x8447f9be, 0x085f97ee, 0xf67e497c, ++ 0xaf1ab471, 0x2f9cf1b1, 0x4bd448fe, 0x3973b78f, 0x7da6ece9, 0xaf3c71f7, ++ 0xe5c3989f, 0x1fb7d48d, 0x05e2ed11, 0xe52a647c, 0x6ac9e8c7, 0xf45e223d, ++ 0x4b1f1f1f, 0xa7f5e029, 0x77290708, 0xe3f8bf80, 0x7fcc3f60, 0x85fc4cdd, ++ 0x821eebad, 0x3dea0ffb, 0xdcc27c4a, 0xe40130bd, 0xc7a02dc5, 0x5da80a98, ++ 0x73ef7e3a, 0xe92e1eee, 0x1e50c6c2, 0x29eb966f, 0x0f7e26ec, 0xb5d68d72, ++ 0x50df0184, 0xb5ff8d2e, 0x680d2750, 0x0758f3fd, 0xc3d15bcd, 0xb9fb4880, ++ 0x01fd81cc, 0x4f8c5fdc, 0x3b5dc20a, 0x074151de, 0x0c5789bf, 0xf25e91c7, ++ 0x6de23e59, 0xda5ffbe1, 0x67974016, 0x0eaf16ed, 0x742fe7e4, 0x9fb0d79e, ++ 0x4dbe7733, 0x9351f7fa, 0x35ab487f, 0xffc9b94c, 0xb04a23d4, 0xf4afd17c, ++ 0x8bf0135e, 0x1e679ded, 0x5eeb039a, 0xe277a9d2, 0xfeee4b90, 0xa346f7af, ++ 0x7469dcfe, 0xe410f9e2, 0x9c06fdf8, 0x17d72377, 0x74d4ea8f, 0xeafbfa70, ++ 0x8111ccf3, 0x486fd02f, 0xe77c936f, 0x1e6c5468, 0x64acf983, 0xbf28c1fe, ++ 0x09973297, 0x5b6ecfd3, 0xfc018d31, 0x10d75b96, 0xfb793a3f, 0xab7bd214, ++ 0x97ca9799, 0x167e306e, 0xb7961f2a, 0x1e2bf3aa, 0xfa57e755, 0x3b5ef9d4, ++ 0xcedab971, 0x02735327, 0xc0d3bfa7, 0x588f49f6, 0xbea1f66b, 0x23d7ada3, ++ 0x780b36e8, 0x49f22762, 0x7768fb90, 0x4ae5135a, 0x66bebe41, 0xc5ca6977, ++ 0xe70d71ec, 0x51be65af, 0xbd5ef921, 0x12f98f21, 0x217bf6fa, 0xf60dd39e, ++ 0xe0e310eb, 0x5974e2f9, 0x137c75f8, 0x6894f52f, 0x5cb7afea, 0x2f1c13f4, ++ 0x70d1e696, 0x3e6112de, 0xba7f6a56, 0x5138fc3a, 0xbb1c7209, 0xdb064e4a, ++ 0x26b97227, 0x3e92cbce, 0xd2a7ce1a, 0xfa979977, 0x065db06e, 0x8658afd7, ++ 0x904c78fd, 0xb37b494f, 0x2b9f0fdc, 0xf64692cc, 0xb9c407a1, 0x768799dc, ++ 0x0f51cfe6, 0xc938fdc2, 0x530027b1, 0x98d77a5c, 0xe0ec8621, 0x03aed17e, ++ 0x2054eae8, 0x4c0eef84, 0xbc9225b0, 0x8e273275, 0xe17de92b, 0x3cfd159d, ++ 0xdcbfdf30, 0x09e29e5d, 0xfb5ef3a1, 0xff9f898f, 0xe4aab318, 0xe1c8d32c, ++ 0x7720eda5, 0x1adf4963, 0xafe74c82, 0x7a24efbb, 0x64ee66af, 0xddaef3a4, ++ 0xff3d3343, 0xf395fc82, 0x6c5de599, 0x4d879464, 0xa66ffb0c, 0x8eaccf98, ++ 0x9d7c68b7, 0x71a465c5, 0x4f61cc5c, 0x9f3323a6, 0x034f302f, 0x9defafe4, ++ 0x18d31a3f, 0xafe6271b, 0xf1bd7074, 0x25b2917a, 0xb79c549e, 0xf185c719, ++ 0x152f98a2, 0x4e3196d3, 0x15e3a607, 0x83cf81b7, 0x6b2279e3, 0x3afac0cc, ++ 0xd7cf404b, 0xc6483309, 0xa2f0bdf6, 0xd7e44dbc, 0xb859eecd, 0x6d5bbf1c, ++ 0x624c47c4, 0xe0049e1e, 0x5fc4b987, 0xb36eb82c, 0xd7127fd5, 0xb7a91365, ++ 0xd8fb41cc, 0xaec8cd9b, 0x18dacd11, 0x9eb56b8e, 0xed62e2f5, 0x3e60aecc, ++ 0xbfe3deca, 0xb49f218b, 0x8923757a, 0x404b2e4f, 0x5bbca93e, 0xbe01788d, ++ 0x913cedcc, 0x6e500dca, 0x2e7cbd63, 0x45afcc5e, 0xc634b9f0, 0x5cc090e1, ++ 0xb683de34, 0x450c69ea, 0x828d7598, 0x9d8b1fed, 0x9be7107c, 0xf287808c, ++ 0x1506c984, 0xab724adf, 0xea5529f3, 0x9d479a7c, 0x76a3b0b7, 0xefc55fa4, ++ 0x4090bd4e, 0xb45ca9e7, 0xbf0518ab, 0xe7cd1398, 0x098dd325, 0x3f4d7fba, ++ 0xe5cfaa71, 0x4626f1f5, 0x8b64baf6, 0x7d248d85, 0xd7026365, 0x62f13e57, ++ 0xf89bbeb9, 0xc778fe79, 0x67e0035a, 0xbce2a57d, 0xdebbf007, 0x8b579f66, ++ 0x3105d376, 0x70635edc, 0x7ca158b4, 0x739c7553, 0x768f8e23, 0xfacf5866, ++ 0x17eafb28, 0x6c0baf10, 0x5eeb1ebc, 0x4dc37e8f, 0x8df6ed1b, 0x75abb40e, ++ 0x5ea1344f, 0x37d99cbc, 0xfdf430b3, 0x981bec2d, 0x0798d3ef, 0x5e8228bc, ++ 0xf82df7e4, 0xc7e7873d, 0x93b9e317, 0xc474e5ff, 0xd97ce295, 0x22fc856c, ++ 0xfcdb1d0d, 0xa9cb2768, 0xf93b27ca, 0xc3dec207, 0xad1f7ec4, 0x83634fd9, ++ 0xf9e54df4, 0x5d69df22, 0xd215a6f7, 0x7ec21d41, 0x7e16689b, 0x817d90d5, ++ 0x87c3b793, 0xa02e6e62, 0x7ef9127e, 0xc7f93270, 0x2c75e9f7, 0x94e387f8, ++ 0xbe25c707, 0x8d944134, 0xe2f7f836, 0xd22b1dfe, 0xb9be917c, 0x63d11260, ++ 0x30eacea7, 0xb67ef8e9, 0xdad1e0e4, 0x14b847ad, 0xc16befdb, 0xf8af5cf9, ++ 0x3f74cd29, 0x5bf647a0, 0x803e0160, 0x55c4a1fb, 0x65aefb81, 0x5ea3b302, ++ 0xdf2cb31d, 0x1fef8769, 0x00e6fc2c, 0xb5479bda, 0xcc23f232, 0x71dae131, ++ 0x287eae56, 0x2957672f, 0xf846ffde, 0x06fbd04e, 0x26afbb43, 0x8677d394, ++ 0xbbcc19aa, 0xfca2d052, 0xeabe591e, 0x9d68f2d4, 0x490fe549, 0xbb72b44b, ++ 0xa3c4c270, 0x72efa409, 0x9267e47f, 0x5cb2e49f, 0xfb2127e4, 0xf7ed38fd, ++ 0xf12277d2, 0xe0b97503, 0x46bb3707, 0x173f4919, 0x5ff2417c, 0x683bee37, ++ 0x01b19737, 0x59b37f48, 0x43e9f123, 0x2f892ba5, 0x46bcc2dc, 0x6587f384, ++ 0xde720f1c, 0xf5ab26b3, 0xeadd9b99, 0xad2a9cfc, 0x26e1c3be, 0x51eb9dc7, ++ 0xfa94cf97, 0xbeb564ea, 0x7d7fff3a, 0x3772471b, 0x0bbad9e5, 0xc0efd103, ++ 0x550dedcf, 0x3bf71f16, 0xeb4e8818, 0x72ff71d7, 0x7be2fb43, 0x776f1093, ++ 0x6113d233, 0x86cb285f, 0x5954dd93, 0xfea7821e, 0xf9053eb5, 0xc49b50fd, ++ 0x3e6fd73b, 0xa2f6fa30, 0x9583e25f, 0x9e6055b0, 0xafdc4cfb, 0x798a3fb6, ++ 0xe92c6ed1, 0xdb90b6d1, 0xd417613f, 0xec327ce2, 0xcfd44e31, 0xc80ae837, ++ 0xd621ba5e, 0x6f6bb2a6, 0x50e9cb5c, 0x661d49da, 0xc5fa8056, 0x6c6b331c, ++ 0xfdb7f6e3, 0xdcadacc4, 0xf613e63e, 0x0f42a386, 0x6475f284, 0x81f0d39f, ++ 0x1fae04a4, 0x25cbcd26, 0x4755683b, 0xa1da217e, 0x7d913e41, 0x838268fe, ++ 0xf27957da, 0xa3777ec9, 0x4ff92e75, 0x19363a1a, 0x74835996, 0xfa144ce3, ++ 0x418b0c7c, 0x7bb5eb7a, 0xbb266cbd, 0xee742fd7, 0x17f444c2, 0xdf64fc9a, ++ 0xfa37a10a, 0xacfe491e, 0x9636f810, 0x072ee7b9, 0x67bd74b8, 0x9539e272, ++ 0x1f64632d, 0x1c67657b, 0x330cedd9, 0x75fff119, 0xd9f08ca5, 0x98267685, ++ 0x357117ff, 0x53af87a4, 0x9f4f895a, 0xf0489f8b, 0x4fdd655f, 0x279acde7, ++ 0xe4428e81, 0xea2daac0, 0x49d66afc, 0x17dae4e7, 0xf123d0fa, 0xeaf7c933, ++ 0xb1dbabb7, 0x967e6a41, 0x8172f82f, 0x02ab39db, 0xcce55ea7, 0x385de7e1, ++ 0x8a3ac030, 0x7b0935de, 0xf1fb7ce9, 0xcf916428, 0x93d3172a, 0xf4276cba, ++ 0xfe72ff7c, 0xd1c6245b, 0xa12287ca, 0x8060dd1f, 0xfa820a71, 0xf9e3114e, ++ 0x7d0ebafd, 0xdf382eaa, 0xea4ed142, 0x4aff9259, 0x0096957c, 0xbb3a044b, ++ 0x97f05133, 0xf88d966c, 0xce89fe86, 0x89a48c15, 0x78bdfea7, 0xc62b1abe, ++ 0x22f07a03, 0x1675795d, 0x7aefd21f, 0x92e491a5, 0x4869f505, 0xe21e2a37, ++ 0xf1a9bfbf, 0x63de11ea, 0x69ace358, 0xa59c6f50, 0x04e10633, 0xc4c3f274, ++ 0xb4fd20a4, 0x36e67f30, 0x54474545, 0x9dee267e, 0xe52474b0, 0xae43ff84, ++ 0x15854c27, 0xe8153f63, 0xbf748148, 0x936bcfc2, 0x60333fac, 0x537477fb, ++ 0x33264e88, 0x57e7019f, 0x7fe35761, 0x3f3aaa52, 0x3e87d1c5, 0x25c12e28, ++ 0x573539e0, 0xfc92ee5d, 0x55f9a98a, 0xf496fb16, 0x81df761d, 0x3df9e1ef, ++ 0x1ae589a6, 0x68b28e50, 0xfe30e0e7, 0xaf1367a3, 0xd9e21fba, 0x887e30c4, ++ 0x0f3f232e, 0xd502c75c, 0xe97d282f, 0x4d9bdcec, 0x7a10d4fa, 0x9762fb94, ++ 0x2803c791, 0x4fbf73af, 0xf70d8589, 0x72157d23, 0x1fdc9dfb, 0xc67d21d7, ++ 0x58aee907, 0xd24b7f7c, 0x103640d9, 0xf6faece9, 0xf01ebf28, 0xbbfa2f92, ++ 0x20aee90e, 0xfea5ff28, 0x87d252de, 0x1c94b2be, 0xdf7ceb94, 0x4a3ff949, ++ 0x64316b69, 0x51f91f21, 0x8437ce0b, 0x7ce1de9e, 0xf689e809, 0xa9391f69, ++ 0x9bd0d72e, 0x28e1fbc4, 0x594b1f2e, 0x6cd9d123, 0x7f52839d, 0x8f920ae5, ++ 0x06d9d6e5, 0x4cd6ff6c, 0x90136f4e, 0xbeb0731e, 0x2dca5e9a, 0x1e96bcea, ++ 0xe85d4461, 0x8cfa5ab8, 0x91036f44, 0x4c7ca4de, 0x7dbd34b8, 0xab8df425, ++ 0x215f6f48, 0x9bd1231c, 0xff24ce96, 0x2f6516da, 0x1b3cc2b7, 0x0792146a, ++ 0xd41bdea3, 0x75a1f982, 0x6ebfa459, 0xa3ee738b, 0x5e5e46f2, 0x63d2e9d8, ++ 0x1ace481c, 0x2ee59e51, 0x13437cc7, 0x45d74394, 0xc89c7987, 0x7979bba0, ++ 0xfb8d3dfe, 0x7827a86c, 0x275dfb79, 0xa163ebd7, 0xb45eb7dc, 0xc72d6d2f, ++ 0xde06c37c, 0xfbf40bfe, 0x2d78c48c, 0xbf7e0b5f, 0x272cfee6, 0x7d72be3f, ++ 0xef58bc79, 0x7de5e536, 0xb795aed4, 0x12c0715b, 0xe6cf48cd, 0x620deefa, ++ 0xe49fe39d, 0xfcfc4ceb, 0xa00ec9c6, 0x5edde58b, 0xeb8ebfd2, 0xbf898b6a, ++ 0x96a73845, 0x9819ad2a, 0x8bf6024e, 0xdce2cba9, 0x7ee6cfa0, 0x8430cdc1, ++ 0x39db8933, 0xfd0d3fa4, 0x7a2195f6, 0xdb89338d, 0xe4bd6599, 0xd200c078, ++ 0xb236e3c3, 0x9f7f4b33, 0xa0a611ff, 0x5235c7bc, 0xff04481c, 0x469ca4df, ++ 0x0d261bd2, 0x80bf7e94, 0x9b8c0961, 0x89cbe17f, 0xa330ece1, 0x72beb893, ++ 0xc821c442, 0x1e3e35ef, 0x890db0ef, 0xbae11d24, 0x4794b7f9, 0x52171ebf, ++ 0x7882565e, 0x878af9e5, 0x21b8da9e, 0x6babe003, 0xa8517834, 0xc7142a65, ++ 0xf993a331, 0x9df6c5fb, 0xf30324ff, 0x87ae289b, 0x05babfcf, 0x1d1131e4, ++ 0x0b3767e7, 0x8371b1fc, 0x0b677e89, 0x124ccd3c, 0x3628cf7a, 0xcdd3f90a, ++ 0x58b76f02, 0x7e260f40, 0xf0d46ad8, 0x90925b8d, 0x51163c6f, 0x6b9756ff, ++ 0x188d4af8, 0xdde85ab7, 0xe937592b, 0x1f15c727, 0xe31e27a5, 0xeb6af77a, ++ 0xba6fd261, 0x66fae71e, 0xfe900b2d, 0xae23b5a3, 0xaf9d4e7e, 0x1be7536b, ++ 0xaef9d5da, 0xa71a5e11, 0x62bab1eb, 0x3cd5dfb4, 0x8bd91efa, 0xf17f246b, ++ 0x280bf9a9, 0x3cbf9cd2, 0x7dd92d72, 0x78df33be, 0xc5494e01, 0xbbc938aa, ++ 0xec429293, 0x78f2af22, 0xcfc67a8f, 0xa6b65de3, 0x10475aba, 0x691e527f, ++ 0xe0be49f9, 0x207ed227, 0xe33e4bf9, 0x8dce08f2, 0xaeb0b9ef, 0x547b9f46, ++ 0xaf9c5de2, 0xfd0bdb7a, 0x1ff51f27, 0xc36ba7a4, 0x439053ef, 0x43b398ef, ++ 0x42dcd0e4, 0x6f5be10b, 0xaab1e11d, 0xa249e1e8, 0x35e7c887, 0x5e86b975, ++ 0x56e979e4, 0xd0b32f41, 0xffe30163, 0xb9d17159, 0x4e4ad0ec, 0xd75b372f, ++ 0xb87ebd10, 0x3c8bd38a, 0x39f95db7, 0x2effa5cd, 0x3a5eb4e7, 0x17bd0289, ++ 0xf29939d2, 0xf3a0e55c, 0xe9c28371, 0x87e16ea0, 0x8238554f, 0x3350e17c, ++ 0xf084324b, 0x66299689, 0x5b0bfa0b, 0x33fcfc8c, 0xc5c7ea73, 0x8cf8424b, ++ 0x8fd4aa2b, 0x491d62f0, 0x8bad0764, 0x3e69f691, 0xe75d1cce, 0x7e423ff7, ++ 0xf90c54f7, 0x651e7b5b, 0x3cf492a4, 0x98e29439, 0xb4bf0b4f, 0x038acf9c, ++ 0xe009edcf, 0x6dfa6c7e, 0x57ddfa14, 0xefbfbe2b, 0xd98a3f40, 0xcfa47bf3, ++ 0x89bf3ad5, 0xc93b0bdb, 0x8dc72a7f, 0x12f4ff6c, 0xc1bd33ff, 0x12b770e5, ++ 0xf0a9714d, 0x1fa8487d, 0x6e64c3eb, 0xf27292e7, 0xd73ec28f, 0xedaa9bd2, ++ 0xae09c511, 0xffbae0bf, 0x78f5f0a8, 0x3f1237df, 0xfa3bfb47, 0xb32a4159, ++ 0xe77df1fe, 0x5b04f183, 0xe09e232e, 0xb9dbe08c, 0xef4c7b80, 0xc59d738d, ++ 0x7e109ff5, 0xcfc213d3, 0xfb962276, 0xd6f7cedd, 0x5a2672e7, 0x5f8427a4, ++ 0xdabc44ee, 0x59eb231f, 0xd9ac7a45, 0x40675962, 0xacb3363f, 0xf6a4041b, ++ 0xe291b988, 0xf5f3e634, 0xdb8ced75, 0xdfc431b4, 0x9a5c9291, 0xf6ed0c9b, ++ 0xa60addda, 0x353f5acb, 0xbbbdda85, 0x77a45d70, 0x4575f5f0, 0x9b8e54f1, ++ 0x9b995c92, 0x1b9ef08c, 0xe6f67c20, 0x9bbcc8c7, 0x9ebaeffa, 0xfcded9f3, ++ 0x099e78f7, 0xa3b485fb, 0x69aff247, 0x702069fd, 0x8a2079f8, 0xfeb5c3db, ++ 0xaf9205f0, 0x7cf87f09, 0x74169fc1, 0x42fcbb70, 0x1fdf5b0b, 0xa47517ca, ++ 0xac6ef3f0, 0x1fca8877, 0xa2b98dee, 0x9f4907f8, 0x7b3a035d, 0x878fc7fd, ++ 0x84eb8ff8, 0xae4eb0ff, 0x7d7abb6f, 0xaf3c04e3, 0x5c78ffa2, 0xff5f5172, ++ 0xe0ce36b1, 0x0627d455, 0xbb70f105, 0x42adc39d, 0xf68e5b5f, 0x8c659ed5, ++ 0x7f6fb3e2, 0xda0b697b, 0x0fbf6f5f, 0xcfc4942d, 0x13aeaf48, 0xaeb48e70, ++ 0x398eb724, 0x68ed7654, 0x7f9908e6, 0x955e279a, 0x243d4d27, 0x4d7fb2be, ++ 0x80fdaaba, 0xfd556cc6, 0xaad74d81, 0x05bcb3ca, 0x86ce7caa, 0x07f554eb, ++ 0xf2a996b7, 0x51bd1f43, 0x659f3f55, 0xd83b23f7, 0x8ada3d41, 0x99be35d8, ++ 0xcf61f2aa, 0xff6aaadd, 0x787c6b05, 0x2edbd41c, 0xebcc33ce, 0xcc5e1cea, ++ 0xff3830cd, 0x544b6d11, 0xb6945bed, 0x1af23f62, 0xa057e2bf, 0xaf8172de, ++ 0x5fdc9d65, 0x957db230, 0xb1d3ffaa, 0xd6887efc, 0xeb9d0a0f, 0x576b1f49, ++ 0x5f4ae3d8, 0xc74d68bf, 0xce31eb03, 0x147fafa7, 0x5bb427f8, 0xd418e705, ++ 0xce7ab4e3, 0x44b6c93d, 0x2ce93792, 0x96b5d39d, 0x07a4ac2e, 0x27a93cf6, ++ 0x1b3e60bb, 0x8238c8f2, 0x1cf99197, 0xc3d7f17d, 0xe7abbdb8, 0x67c51b05, ++ 0x297b78ad, 0x5539a3d1, 0x0e51174d, 0xe4c45d35, 0xe6c2e9aa, 0xbf41d354, ++ 0x681d3512, 0x52e71ee1, 0xc00b05d3, 0x96f0217f, 0x4f709570, 0x1ba6ac98, ++ 0x580bbc2d, 0xab8a01f7, 0x3f4e29f6, 0x6e87e30b, 0xbaeb44df, 0x52f91e94, ++ 0x0a3bf0b2, 0xefda8ef8, 0xdc12b16a, 0xd4973c78, 0xff42ccc7, 0xa5ffdad1, ++ 0x5927b37e, 0x3f45ff9c, 0x5ebfaed2, 0xbeb9d2f1, 0xe2573fd7, 0xa167f4cf, ++ 0xb8c8d55e, 0x46fdc8bd, 0x7b585272, 0x648f7d23, 0x9d70946f, 0xd5b9f42d, ++ 0xed7645cc, 0xfc43cce5, 0x4ae558ee, 0xb0ad13b2, 0x9cfc8cfe, 0x7d7267a7, ++ 0x88f986a9, 0x1fb15fcf, 0x1651f41f, 0xc2d58f62, 0xfc50e951, 0x4237e436, ++ 0x0eb3a41e, 0x143c0f29, 0x686401df, 0x49f95629, 0xfa2efad4, 0x97f842e9, ++ 0x78e57fd4, 0xaf929e12, 0xacccf1c9, 0xfb8a9f51, 0x58e7c342, 0xa34fd6ae, ++ 0x7b48d7b6, 0xe2160d0f, 0x67dad1ef, 0x38197682, 0xfa38c29f, 0x0c2d5981, ++ 0xeeca37f0, 0x115ffb22, 0xdf879ceb, 0x2d6d2c4b, 0x53b08706, 0xed7ac35c, ++ 0xd5e51114, 0xb3bffc25, 0x89e04abc, 0x5f7ebeac, 0xe58647e9, 0x3411fe7f, ++ 0x0838a71e, 0x0d7733ef, 0xea7a424d, 0x1e74af6b, 0xd1fa0d79, 0x4213baeb, ++ 0x71bd88ed, 0xd6804afc, 0xdd730b73, 0x90f442cb, 0x7136d67a, 0x8bda165e, ++ 0x62c64e41, 0xac59edca, 0x1b0fab5d, 0x83ac9ec8, 0xafdd2095, 0xd17e2166, ++ 0xe53960ac, 0x32f37df5, 0xfa52e74e, 0xec53afc4, 0xc780de22, 0x07c13117, ++ 0xd23339e5, 0x2dc64eb9, 0x980269bc, 0x72e30414, 0x5ce2299c, 0xb0f2c794, ++ 0xa7efb47f, 0xf6011d90, 0x1fba12a7, 0xa878e37b, 0xd47ecfbc, 0x2dc65fac, ++ 0x64856de8, 0xba1a5a1f, 0x8780cbde, 0x04ee5bd4, 0xd8d3007d, 0xa9e10714, ++ 0x9fe8fa2e, 0xd85c585c, 0x6cab8aa9, 0x0641c130, 0x8aaf06ed, 0xb536b9b8, ++ 0x45373ede, 0xf38903c4, 0x15e0a5ce, 0xce221f19, 0x72e3e04d, 0xe71930f5, ++ 0xa8b8e126, 0xa697dc2f, 0xf7fbf584, 0x2e5d5dc2, 0x72e12ee0, 0x59f3a8b6, ++ 0x76de97c4, 0xdde11938, 0xc1aeeb12, 0x048e03fa, 0xe0ba2b8e, 0x67f42abc, ++ 0xa7b53e28, 0xd6f74f5d, 0xf1e7afea, 0xf53bf54d, 0x75ce1ac4, 0xf40a7d98, ++ 0x8fbed353, 0xcd33c2f4, 0x0f4168c0, 0x430cd53b, 0x37622e1a, 0xd23bc0d0, ++ 0xc7ae4939, 0x84e4229b, 0x8f8cbf58, 0xbbae7581, 0x85d61c04, 0x7e854383, ++ 0xf0c0bf78, 0x431eb890, 0x10cce677, 0xc3aed0fa, 0x66edc295, 0x3fdc1bb7, ++ 0xed3efec6, 0xfb1878cc, 0x1c77d0ab, 0xacf84748, 0xd35ee851, 0x47bf3378, ++ 0xefca969a, 0x1a049599, 0x370f789d, 0x7e4ac335, 0xfbdfa1b5, 0x482194e9, ++ 0xf919cb77, 0x735e3fe5, 0xe1d2fc47, 0x2a8671c1, 0xc8ffba3a, 0xfc9fcbd8, ++ 0x8ffd10a0, 0x609e29f3, 0x43c79981, 0xc63f7d64, 0xe4fc039f, 0xe0b31375, ++ 0x376634be, 0xee91bdd2, 0x31d93d38, 0x026cf513, 0xbf9c9fd2, 0xbf2a2fbc, ++ 0x8b7cfe97, 0xe512f782, 0xdd2df1f7, 0xb4876ea3, 0x2922e91a, 0xe5f1feb8, ++ 0xad1aa3dd, 0x27d43c41, 0x5ea3d699, 0xe5c2ce78, 0x638b8ca6, 0x93f10376, ++ 0x3fbe1635, 0xe7960e8e, 0xcf0dbf6d, 0xae51f5a5, 0xbd71a37e, 0x9e19ebef, ++ 0xbbb2bfb7, 0xfad1c5fa, 0xaf77a41c, 0xe776f3b1, 0x9af97c44, 0xbce8cb0f, ++ 0x3e12d49a, 0x14adeb8e, 0xd5a8be7e, 0x0d6bcdf8, 0xaac78a7e, 0x51e838c5, ++ 0x1a57efc1, 0xdce32d07, 0x2e50f4b5, 0x671f5ff0, 0x74918660, 0xb17ddaef, ++ 0x53fdaf7a, 0xd4bef61f, 0x527944df, 0xc353f739, 0xdc6c2ab9, 0x7e1489de, ++ 0xd7c60e7e, 0x6cdee805, 0xcededc6f, 0xa61614d2, 0x74395eff, 0xa78aa5de, ++ 0xf5dc7193, 0xfc5027e7, 0xa17e9f5c, 0x1835873f, 0xfe0917af, 0xf5fe02e5, ++ 0x2a374718, 0x2be73bf4, 0x451271c1, 0x16205c5c, 0xdbafe3f7, 0xfcaf74f5, ++ 0x937507d7, 0x77998737, 0xcb872a72, 0x370649b5, 0xf30c3fc6, 0x30a6d733, ++ 0xf27acbe3, 0xa7bc8a7e, 0xf6df9da9, 0x9c42c0b2, 0x86e7c63f, 0x952a2f1b, ++ 0x7bce57c3, 0x47c73c7b, 0xdd331efd, 0x297e805f, 0x7c7b7a8e, 0x83f89aa0, ++ 0x1ce78d5d, 0x37edc781, 0xbee93206, 0x4f6e14d4, 0x2b0f4488, 0x51e33d62, ++ 0x81ced60e, 0xc53f40ca, 0x1ec54686, 0x452ebfb2, 0xebb8410f, 0x0bed7854, ++ 0x57e11377, 0x39cf2bf6, 0x53d51f27, 0x43c9c43c, 0x9732df62, 0x8b6dcf15, ++ 0xc93b5c85, 0x64e43fb8, 0x9be742ab, 0x9ac61e25, 0xde2cbf80, 0xe1f49ab2, ++ 0xad4667ea, 0xdf867147, 0xb23e06ef, 0x1bb19538, 0x4eb25d20, 0x765f17ed, ++ 0x217b1f7f, 0xcb9f950b, 0x8fc92359, 0xdba99fea, 0xfffbb0d5, 0xd6927a86, ++ 0x5f368f5f, 0xa5c643d4, 0x3146f38a, 0x7ffe462b, 0x9a5f33fb, 0x12394430, ++ 0x7e009ffd, 0x7c80c83a, 0x99e942d5, 0xeea53b66, 0x5484d754, 0x54a2cb80, ++ 0xb454a4cf, 0xe1cfbcdf, 0xc3db53d1, 0xe25e03e5, 0xd664b905, 0xf326f8f3, ++ 0xfecfee3c, 0x000fbe11, 0xb99b30f0, 0x77efa43e, 0x3419ccf7, 0x7fc11f4b, ++ 0x30bec074, 0x338fe48e, 0xf13de915, 0x299349f9, 0x18f9ee6e, 0x636fc217, ++ 0xed1f2ba9, 0xf92b1b0e, 0x998b467d, 0xbf7dd3fb, 0xba06f31e, 0x3db5063b, ++ 0x5ce78650, 0x3f5ec77b, 0xe83673da, 0x47f146fe, 0xf1e06e1b, 0xc0bac980, ++ 0xc159fede, 0x7c6292f1, 0x4f6fe8a9, 0x7ba2661a, 0xd2fa898c, 0xf890c6fc, ++ 0x83817aa3, 0x13f1c52e, 0x7deec7bc, 0xf42ff81b, 0xf7e063db, 0x1c65ae2e, ++ 0x0c8e32bf, 0x63d50ec7, 0x30fc00cf, 0xafe65178, 0x46fc536d, 0xf6dd4f58, ++ 0xa9a7e46d, 0x3c9fc7bd, 0xafcee50f, 0x92e7e40c, 0x3d7c4af3, 0x59fd0cad, ++ 0x53ccde52, 0x263edcec, 0x4cb9f4f4, 0x587f71fe, 0xb98ba095, 0x179f3f42, ++ 0x84bce1c3, 0xddb13339, 0xab1616ad, 0xaf342d83, 0xd688adbc, 0x8718dab7, ++ 0xebf4807a, 0xc21fd644, 0x9feab5db, 0xb9fbf1b5, 0xec10f74a, 0x679c14e4, ++ 0x1eefb62e, 0x7ea27c12, 0xc6a7bf08, 0xfa173106, 0x0cf7eb11, 0x077684dd, ++ 0x4ff73473, 0x94b23f03, 0x6cbe9014, 0xcad1f3c1, 0x14fca2d7, 0xc2e027a7, ++ 0x8c7caeec, 0x99986bbf, 0x20714051, 0x9de9ba47, 0x40c67389, 0xe05bed26, ++ 0xc2c80a33, 0xd395a9ad, 0xf5ef400c, 0x4187a0e9, 0x45d4e3fe, 0xdf780cd3, ++ 0xad503b31, 0xed29bc83, 0x36bf9e4e, 0xf6f31c70, 0x5f3c75b4, 0x43d6a810, ++ 0x83da587e, 0x46078f3c, 0xb492ac20, 0xa179a6c7, 0x427153ff, 0xe80671cf, ++ 0xaefd725e, 0xfb50baa1, 0xce34a0e9, 0xf1454ea7, 0xd8b2a77a, 0xef0899a2, ++ 0x2df5f0dc, 0x6e3f5269, 0xbd7276a5, 0x0d4b3db2, 0x2a4f6edf, 0xdc52b76f, ++ 0xc31f1e27, 0xbf714436, 0xf016379c, 0x2863bfb0, 0xa73715f9, 0xedfef3c6, ++ 0xb0614fd0, 0xd94f091f, 0x15771c9f, 0xc3e463ca, 0x95e76e46, 0x72a4efe5, ++ 0xace309be, 0xb90671a3, 0x99dc3df8, 0x3f88f919, 0xe0419bc0, 0xb5cfc0cd, ++ 0xa0fcf89b, 0xe23cb8df, 0x4ed0a3fb, 0xa85bffbf, 0xb79c159f, 0x088e4e96, ++ 0xc2d9593a, 0x71dda9fd, 0xe34f4439, 0x22bbc463, 0x0c75ea85, 0x941ef013, ++ 0xd9d7c716, 0x8514978b, 0x701169c6, 0xbdd008cc, 0xf75d2bc4, 0xbad37fa9, ++ 0xc2e5f043, 0xb7f641f7, 0xaf99b35f, 0xe90be387, 0xbbf49e39, 0x9dfd5407, ++ 0x5f69ab5a, 0xd7121b02, 0xed439f1b, 0x2cc5147f, 0xee6d9df4, 0xc795976d, ++ 0x4fd450f5, 0xcc0dbbe5, 0xf50b037b, 0xcfbef613, 0x3fefc6d0, 0xad39d707, ++ 0x2ed3ac50, 0xebe769d6, 0x95e8a9f4, 0x9cceee1d, 0xc74beb6d, 0xedeff0bd, ++ 0xe881786f, 0xc3cfb54f, 0x3afb87f5, 0xa4065e12, 0xc8bc655d, 0xd9e06a79, ++ 0xfccd670b, 0x7f713c24, 0x6ae1bb53, 0xb4f394ba, 0x59dfda47, 0x52bc71df, ++ 0x4eeeaede, 0x1ccd171e, 0xdbaeba6a, 0xb8c3a59e, 0x16aed901, 0x4149fd6d, ++ 0x4d2b9ebb, 0x58337f9c, 0xc3f88446, 0x61456909, 0x5df481ed, 0x8aebfe7b, ++ 0x5adf71e3, 0x9257443b, 0x29ef13b3, 0x7bf2cf7a, 0x763563f8, 0xbd1ff419, ++ 0x0bb60d6c, 0xfe7517ca, 0xbebf0141, 0x4ceea576, 0xb9a15f9c, 0x138715ec, ++ 0x5b69b1ce, 0xf6175f89, 0x0b23bb2b, 0xdb1ecbf2, 0xb0bffc46, 0x5997d97f, ++ 0x1fabcfc0, 0x0f97997b, 0x1b32fb2b, 0xf0af69f3, 0x2bd778fc, 0x7b19efc8, ++ 0x3184da65, 0x45627d41, 0xd5c6839a, 0xd218eb97, 0xf31eaf51, 0x18f499ba, ++ 0x6948d709, 0x18d759a1, 0xd8d7ffce, 0x5fdc0f4b, 0x74ff8252, 0x9c4efda0, ++ 0xd50603ef, 0x962bbef9, 0xdaee93df, 0x37ba0ffd, 0xe79a5772, 0xbed0697b, ++ 0xc2cce621, 0x13dfc82c, 0xe7f909f3, 0x21e81714, 0xd8713768, 0xaf987cd9, ++ 0x1ba36672, 0xcab626f5, 0x5c103169, 0x600b3d85, 0xf7e00172, 0xdd5f9eda, ++ 0xe30f9fd5, 0x118c79c6, 0xcf61a07c, 0xbf477fd7, 0xab29c36e, 0x63fecd13, ++ 0x03bb1e3a, 0x1d31aef5, 0xe5cd7cef, 0x22e7bf30, 0xed063de7, 0xa4bdf095, ++ 0x1ff34cdd, 0x72cd71d3, 0x0ff63fac, 0x2748391d, 0xb7f51fd7, 0xdae85b20, ++ 0xaafe9bfd, 0x8bec2dfb, 0x466dc68b, 0x7849a7f4, 0xaa9415fc, 0x478f047e, ++ 0xa5be3c38, 0x4973b2f8, 0xc807d687, 0x47bea9a8, 0xf93bfa04, 0xb4587b89, ++ 0xf214fd13, 0x0ed6b9fe, 0xd612a47a, 0xefafdf07, 0xe8841986, 0x5bcfe3cf, ++ 0xf3049180, 0x954e2ca5, 0xa9a4b72f, 0xb3d857ea, 0x5293e554, 0x4f9551af, ++ 0xf2abe471, 0xa8c77353, 0x96774fea, 0x9537f2aa, 0xafd5514c, 0xf2aa5574, ++ 0x5536fef9, 0xdb0751fd, 0x9987e5d5, 0x7050f11e, 0xd30fb9c4, 0x322e63a2, ++ 0x689f16a7, 0x98e987dc, 0xb43838af, 0xceebe076, 0xefc3edb7, 0xbdac0ed2, ++ 0xc2ed2417, 0x9f56f473, 0x37fdbc29, 0xbc1390d5, 0xf1d7afaf, 0xb4ff417b, ++ 0x78877e7a, 0xc682f793, 0x90181da3, 0x2ce8b150, 0x9f3fbfbf, 0x208ec9db, ++ 0xcd3f9062, 0xf17d91b5, 0xc5f1b188, 0x7f9fb88f, 0xebbdf200, 0xeb54abbb, ++ 0xa3de7f1e, 0x5b29775a, 0x6dd3c1a9, 0xfd857caa, 0x49fd554e, 0xe5556ba9, ++ 0x69f71c53, 0x2a80f4f0, 0x98f9dd3f, 0x349b4f06, 0xaa95fa78, 0x8777d25c, ++ 0x41ed53b0, 0xe3a412fb, 0x88e59d02, 0x744e1b87, 0x3a4a3e13, 0x4f11cb5b, ++ 0x23691dd7, 0xddfa157c, 0x8b2ec8e5, 0xc3ee360f, 0x30e70fd4, 0x7346f76c, ++ 0x9bfba52a, 0x3aa7641d, 0xe94b9cd0, 0x7d2766c1, 0x09736dff, 0xbb36efa5, ++ 0xf35dfd28, 0x9b3b4a64, 0x35b694dd, 0x97fd51b7, 0x9db9db9b, 0x7df7a12b, ++ 0x0f680188, 0xd40ba738, 0x90d787a3, 0xfc8e986e, 0xe0745cf2, 0xf1efe61c, ++ 0xbf23a6ea, 0x01132134, 0xd22650b9, 0x0f5dfd21, 0x135e03a5, 0xc65e79d2, ++ 0x5ce9b45d, 0x0f87a8f9, 0x8fdfbc7c, 0xbb18030d, 0xd53bad77, 0x16f3c71e, ++ 0x29b213c8, 0x8fdfad5e, 0x2f5c405d, 0x8eb928a2, 0xdf31d3f2, 0x13cbc515, ++ 0x1d37ef1e, 0xeceff0f5, 0xf1f57717, 0xf9c40f8b, 0x2fe2fd6a, 0xd0d8709e, ++ 0xdbe8738e, 0xc78436a1, 0x72cf6121, 0x62e37cb1, 0xf90d4b48, 0x47b39446, ++ 0x4c897a34, 0xe695d41f, 0x3a6dbf62, 0xcf14cde7, 0x2191a37d, 0xf854cefd, ++ 0x33d657b9, 0x29f117f6, 0x9e74cdd3, 0x2d73ac3a, 0xa531b8a7, 0xf38429fb, ++ 0x0873c7a4, 0xeeb65dee, 0xc55f844c, 0x9f3cd9e3, 0xe294fdd4, 0x391bc90c, ++ 0x9e3f467c, 0x53e1b575, 0x933e0e1e, 0x3cfcedd3, 0x400d77e6, 0x0fe6403d, ++ 0x70eaba57, 0x752e1f3f, 0x2dfba60d, 0xbfdf336e, 0xefdd1b6e, 0xd1570661, ++ 0x9d7621cd, 0x6a46e9fd, 0xf82f1b37, 0x56f37da1, 0x2d73ed3d, 0xe74b3f3c, ++ 0x09d11efa, 0xc6e7339e, 0xb0e0b9d0, 0xa00bbf8e, 0xe7f4afad, 0xd1d382e7, ++ 0x3a6fede1, 0xab365e51, 0xd01dc5ee, 0x289ad75f, 0x3dcbbaea, 0xaeb1f494, ++ 0x03ae8046, 0x678d13d2, 0x29d9b979, 0xd97e4240, 0x282ff879, 0x8ee3b17f, ++ 0xd423faff, 0x8c4d64ff, 0xfd886493, 0xaddf825a, 0x0482f2a2, 0x0b4fe90b, ++ 0x43280e66, 0xf84f38b9, 0x0cda16f7, 0x33e6e4c9, 0xc9f099c4, 0xfcd665aa, ++ 0x564100f5, 0xc269589d, 0x326a97a7, 0xe98f5b6e, 0x980f41aa, 0xed6f0af0, ++ 0x51eb6df0, 0x2d83ad8d, 0x2ffc445c, 0xcc335ef0, 0xde93516b, 0xf273cfc1, ++ 0x2beae8de, 0xf491538a, 0x13c4587b, 0xbce81001, 0xa8afefaa, 0x417ad8ec, ++ 0x85d21ba7, 0x1b0460ff, 0x9fed4171, 0xe4e91fba, 0x86f782cc, 0xa81ff044, ++ 0xf8fe85cb, 0x571f1327, 0x1c880efb, 0xe39fd0d7, 0x2809b0fd, 0x5bc9f513, ++ 0xabc81cb9, 0x229ef2fa, 0x875e7f58, 0x0871475d, 0x2076ea8b, 0x05da7a1e, ++ 0x1dac8d1e, 0xef2cd3f7, 0x96284fe2, 0xf61f734b, 0xd9d2f252, 0x950f2f69, ++ 0x77018597, 0x2cbca879, 0x472d6ee9, 0xa3e528b9, 0x9bfa8bf4, 0x6e5f046b, ++ 0xbfba7e24, 0x07f289b9, 0x1e94bd9a, 0xf820de6c, 0xbf952b72, 0xe0a8fcdb, ++ 0x97c13ecb, 0x1defa39f, 0xee9455cd, 0xda50f669, 0x257eeb12, 0xc589f71d, ++ 0x6f87f143, 0xe866663e, 0x30e9eb77, 0xec05dc53, 0x489ea788, 0x3322b8c4, ++ 0xc6d487dd, 0x7cf96917, 0xef6c3d2f, 0xebc8fef3, 0xb8dea788, 0x0717d420, ++ 0x43a7a646, 0xbe4361cc, 0xcd7a41f4, 0x0fb7d474, 0xd4361c39, 0x5e3c8fa7, ++ 0x90e97c43, 0x423361cb, 0x95f4c3fe, 0xb0e3dcbc, 0xe7ff2199, 0x72f257c7, ++ 0x0516c3af, 0x57d28ff9, 0x918fbcf1, 0xde903e93, 0x7c8bdd30, 0x71fb2996, ++ 0xb25b947f, 0x00b88026, 0x1fba5d79, 0xd4a4c5f7, 0x5f7013c5, 0x10774f4c, ++ 0xac714c7d, 0xa9f98fdd, 0x780c9bb9, 0xcd65cb15, 0xcaed875f, 0xd80d2b12, ++ 0x6dc6426e, 0xc4ddb0eb, 0x42180f41, 0xbe1e4ddb, 0xa7e61d6d, 0x50193739, ++ 0xf82e9d3f, 0xe647ec98, 0xd3e4b965, 0x646dfe32, 0x41e49b87, 0xe49bbb5e, ++ 0xd94b8481, 0xd17bcaec, 0xaed0d55f, 0xc79c15d8, 0xf837a56c, 0xeb086300, ++ 0x74ce3df1, 0xa1fe3b8c, 0xb7ec2d6d, 0x475fcc06, 0x1daf1ff9, 0xf7f9557e, ++ 0xf7f8e137, 0xa3bf6207, 0xf6b8c7bc, 0x3dfc4c0f, 0x17089995, 0x163ba7d4, ++ 0x50dde8db, 0x9ea1b1e6, 0xf9e42555, 0xfca14c7c, 0x407f917e, 0x5cea0fa4, ++ 0xddf0fec6, 0x2f9c5fda, 0x7b07f2fb, 0xffda22ff, 0x11227b9a, 0x887f05ca, ++ 0xe7e76fef, 0x462ef125, 0xd3f7e31d, 0xa73f152e, 0xc6d7038d, 0x6d62ac93, ++ 0x7d595c07, 0xf16a48e3, 0xdf4e5b1e, 0x2f196ef8, 0xeef38dad, 0x7345573d, ++ 0xbc855a7e, 0x4478e806, 0x5fe43864, 0xe1f90e02, 0x3d67d0e0, 0xf7b1c78c, ++ 0xf1122f89, 0x3175daec, 0xc77f124f, 0x6bb7c457, 0xa2e927d7, 0xb95afaef, ++ 0xf870379c, 0x8e577e83, 0x6458ae78, 0x0ab76863, 0xbc7f3fe5, 0xf2d1ff08, ++ 0x27c5abb3, 0xcbaa2ce7, 0xfaaa77a4, 0x842ab1f2, 0xc98f96a3, 0x54daf17b, ++ 0xff78a9ea, 0xf11ce30e, 0xe73c20bd, 0x59ec937f, 0x9574fd8a, 0x875dff75, ++ 0x00c4d0e7, 0x38dee1c1, 0x41c2354f, 0x0578f131, 0x427c7719, 0xf5097de7, ++ 0xeffa3bb6, 0x0e777e22, 0x91ec0585, 0xbd479055, 0x5dddaf6c, 0xdcb1fd8b, ++ 0x4b39c500, 0xae29117e, 0xc3908d76, 0xefbe537d, 0xd7697c64, 0xc933afa6, ++ 0x7d89777e, 0x151e0911, 0xbc0171fa, 0x1253d1ff, 0x8cf3f243, 0xbef8fcc2, ++ 0x64d299ef, 0x0cce5bd2, 0xbd301930, 0x33e2e7da, 0xff508603, 0x99f1f3da, ++ 0x1f0b12b4, 0x4c64e277, 0xbc76977f, 0xefdee510, 0xbb655c45, 0x77ea3bc9, ++ 0x131e1f68, 0x9bfafe45, 0xc2214094, 0x3eae7b41, 0x32fcf6f3, 0xf3df5e47, ++ 0x026fac35, 0x53f6afae, 0xedf8bddd, 0xb5dbcf4a, 0x18677f4d, 0xe9b63ec7, ++ 0xf518665b, 0x9ddfce5d, 0xd40e79f1, 0x482d3c2b, 0x80cfa322, 0x4bf9013e, ++ 0x559d65c5, 0x159e9ce0, 0x792f2e72, 0x8967c787, 0xef3e7b54, 0x2adeaef3, ++ 0xb01e3aaf, 0x71445fd4, 0x2c40fa28, 0xf1d5fbdd, 0x9c642b77, 0x3ce25bd6, ++ 0xfdf5e70f, 0x95ebb748, 0x79d54cce, 0x2e1f07fd, 0x40f88bbc, 0xbc6dc514, ++ 0x1279fed8, 0x9d2ff5ce, 0xe6bd0f49, 0x8377d208, 0x2704effd, 0xea6daf99, ++ 0xaccfe551, 0x8513be0d, 0xff6aadf7, 0x04b927a9, 0xe1036c72, 0xba61bd89, ++ 0xb2be443d, 0xc2f5bfb6, 0xbbf0247b, 0x9d18044a, 0x70cce717, 0x714abd41, ++ 0xa3de621e, 0x8fce2f3c, 0x70cdb9a0, 0x4995bf41, 0xe36b3ea2, 0x7cb201f9, ++ 0x583faf1b, 0xe5e567f6, 0xfa2f3269, 0x4fe646bb, 0xd92cf2f0, 0xca26fa3e, ++ 0xc9f978db, 0x40cdeffe, 0xf7f2463d, 0x7f42feae, 0x0139ef16, 0xf912ffbf, ++ 0x6ee245c8, 0x1e42e5d4, 0x2a9bf7c8, 0xe625307e, 0x6db7dc3d, 0xd610c50a, ++ 0xfb246dde, 0xb6f8e9fd, 0x6777d0bc, 0xbb8e7c65, 0x5af146dc, 0xdd0eaf75, ++ 0x4b7117ac, 0x0ac4b7a8, 0xde857aff, 0x9e977e4a, 0x8f5f39fb, 0x3755f7a4, ++ 0xafe152ed, 0x2f78b94f, 0x30931c9a, 0xa71fd9de, 0x36033dd0, 0x01e293a8, ++ 0x191432e2, 0xa4f7407f, 0x625c7c65, 0x79e1730e, 0x5137f139, 0x63d1bdfc, ++ 0xab6fc49d, 0xd9edc37f, 0x23ed8f75, 0xef44b6f9, 0x2f927b20, 0x819293db, ++ 0x7f1b12fe, 0x69bab217, 0x52cbed0f, 0x0bf85d87, 0xc28787bb, 0xfa866073, ++ 0x6f802d3d, 0xe1c5c64e, 0x37ff2eaf, 0x476b5fc3, 0x57eff797, 0xdf1c615d, ++ 0xfbf71b39, 0x3e9e053a, 0x058a39d3, 0x80cfaebc, 0xef2ece71, 0xc7a7121c, ++ 0x8a4eec60, 0xbfd0ab5b, 0xabe7845b, 0x431b469e, 0x3a539fbc, 0x83083ef3, ++ 0xe239ed7f, 0x8aa64c89, 0xd19a9b2f, 0xba6fbe87, 0xfa6f7c04, 0xc537c24f, ++ 0xd1393010, 0xbf847c4f, 0xf9dc5733, 0xfe342999, 0x65d041a7, 0x07ee76bf, ++ 0xc16df193, 0x93c71b72, 0xcdd537f0, 0xfa1c777c, 0x187ee49b, 0xd0dac31f, ++ 0xed74007f, 0x44ed7414, 0x1bf496ba, 0xbb413bf4, 0xd20df030, 0xdfae1aaf, ++ 0x3fb74bef, 0x7f5c04b8, 0xeb849ff0, 0xc97fd076, 0x8a23bb5f, 0x385a32ec, ++ 0xeb833cff, 0x2fde122d, 0x38247c89, 0x4e7084bf, 0x7e70faba, 0xb2a1c329, ++ 0x4778486b, 0xfc5a4792, 0xd98779c8, 0x65df45a7, 0x299f5e9f, 0x402194f8, ++ 0xbc5ab571, 0xf78be8ef, 0xfbc0979d, 0xde24ffce, 0xa6d370b5, 0xab7fc2b5, ++ 0x4641fefd, 0x55777e44, 0xcd3ff8e0, 0x71a0b02f, 0x517caaaf, 0xf2aadbd3, ++ 0x2ff7dec5, 0xed208fcb, 0x7f29fffb, 0xcc23f482, 0x0e856578, 0xf95a8dfd, ++ 0x3ba64cf0, 0xe3d0007f, 0x7bfebb4d, 0xf93807f8, 0x5714219a, 0xcb588775, ++ 0xf1fee397, 0x5f405dc9, 0xfb72365f, 0x27bdd1ea, 0x7d118e8d, 0x79c165e9, ++ 0xd085731d, 0xf7a682d9, 0x2d67a88d, 0x9c398d00, 0x0078b59f, 0x5c5257b7, ++ 0x2a85f014, 0x0226330b, 0xe2aaa83f, 0xd0ab9ff7, 0xa94f18a1, 0x33e503df, ++ 0xef8fcc0c, 0x0d5a5755, 0x39f9337e, 0xcdd9f7d5, 0x966b3de2, 0xd7baa098, ++ 0x29e977ae, 0x12e6ef7e, 0xd5bd1fee, 0x81f746da, 0xe7bc1ee7, 0x97b85dec, ++ 0x788b79d7, 0x47bcbafc, 0x95dd67f8, 0x518b3df8, 0x9e73c52f, 0xb7e9fc22, ++ 0xae9fc919, 0xd62d176d, 0xf0af433b, 0x3c9d99b8, 0x4fee52fe, 0x7341df58, ++ 0x82cfbf01, 0xd951b7bf, 0xcd0ff468, 0x2f7abd43, 0x250dd5e9, 0x7f10f36b, ++ 0x4f94130d, 0xf3c179cd, 0x57d3434d, 0x9fcb5ed4, 0xdae5e9b5, 0x3e693f53, ++ 0xcf22f448, 0xfd9b4741, 0x57dad794, 0x3fff8fe7, 0xf31c8fe4, 0xd305af95, ++ 0x3ebadfb1, 0x0eeb0d18, 0x4bfe7734, 0x376903f6, 0xad047690, 0x11f2425d, ++ 0xd2e3eef9, 0x9ef17601, 0x39f92969, 0x92a78198, 0xd01caedf, 0x0dd73f87, ++ 0x7f28ba28, 0x9bff9756, 0xd2e5f3f9, 0x972a6d7f, 0x3fba5aab, 0x6497f332, ++ 0xadf4966f, 0x18f9ffa5, 0xcfe30283, 0xdee8506f, 0x568ad577, 0xbbe558e3, ++ 0xeb2afbd3, 0x370e4cb1, 0x62b85c8d, 0xf5a0e079, 0x74f5cbeb, 0x6feb30be, ++ 0x439da273, 0x17d7c1e2, 0x812e5b6f, 0x49ff2db7, 0x8b95f5bc, 0x377e16c7, ++ 0xfa54c8b9, 0xfa03ebc4, 0x06fbe7e8, 0x509f5c5c, 0xd79bff97, 0x68df721d, ++ 0xbc175ea1, 0xd7f18357, 0xe5d9f718, 0x6b4cf7e3, 0x77e95ab2, 0x77495801, ++ 0x95bbf22c, 0xf7fcf5bb, 0x432e0c66, 0x687bc85a, 0x4fff9867, 0xc62b8f48, ++ 0xb48477f1, 0x22f5d171, 0x75957a5e, 0xd453dd3b, 0xe3266bbe, 0x7f45ebae, ++ 0x64cdf7da, 0x816ef97b, 0x53b37df6, 0xd9fdc403, 0xe3c05602, 0x47ce2e50, ++ 0x0f3ca1cf, 0xfb9ccff1, 0x0aec99b6, 0x7fa2033d, 0xe208cde2, 0x3c5f7ce5, ++ 0x3c097b7e, 0xc49ffb7e, 0xf57e96a3, 0x1f742db6, 0xf7e94aed, 0x2e2b871d, ++ 0x97c82933, 0x6bcdf97b, 0xf237e266, 0xdbaef67d, 0x84f7a45e, 0xe466beba, ++ 0xfbd4bd87, 0xf0cfe3dc, 0x1fd784eb, 0x00d8b5f3, 0x7a8f63af, 0xe6373ec9, ++ 0xdfee87b0, 0x85d77e8e, 0x7f2cff11, 0xf38f5bbf, 0xd48cfa96, 0x4bfc826f, ++ 0x71134bdc, 0xe7cb9755, 0xf8bfd4ae, 0xca2bf2ef, 0x8ce771fb, 0x1dfc22fe, ++ 0x28ceef04, 0x3b43cf7a, 0xba99c9ff, 0xdc2fbe8b, 0x9c99eb12, 0x2599f809, ++ 0x677c84e4, 0xdfcf42b8, 0xd4e9ef17, 0xcd707d93, 0xd2f0ff0f, 0xdb4b8e13, ++ 0x3dec1a15, 0x3265cf61, 0x7bf1d06d, 0x0ee5052b, 0xf3c48b8a, 0xa50bda1a, ++ 0xff5b50fd, 0xadd9473e, 0x1adf6499, 0xf9c2e9d7, 0x13e7ca3c, 0x4d0d5f09, ++ 0xf7f42cdd, 0xdf8d2241, 0x1ec8bbb0, 0x13ca6efa, 0x7fa48a99, 0x104b71fb, ++ 0x174b97df, 0x2dced3ff, 0xabccf433, 0xa11d7c80, 0xcbdeb8f8, 0x9f3bfeb8, ++ 0x90ba5275, 0x61ea5375, 0x12c2fefc, 0x1974a4e6, 0xe49a5373, 0xf704fcf0, ++ 0x3bb19777, 0x5f4de299, 0xd23866fd, 0xc61bd9cd, 0xe24c62b6, 0x691bf2d5, ++ 0x7caebef5, 0x68ff7f07, 0x447f37c7, 0xa1faecfa, 0xc6f8b2f1, 0xa7aeb113, ++ 0xc7f8c333, 0xe7aa577f, 0xaff696f7, 0x69517921, 0x04d86de7, 0x4d8b77ee, ++ 0x13fda2c9, 0x9b299be4, 0xff44df24, 0x754f88f1, 0xa565fe3c, 0xb700ef42, ++ 0xc5b47407, 0xf2cf2c46, 0xb5b2efe1, 0x23e5e76f, 0x0a7ce2ea, 0x898c47e4, ++ 0xc5b7e5e2, 0xc9bef0f9, 0x7da01602, 0x9b6f08b9, 0x123ef1e8, 0x9df28be7, ++ 0x6411387d, 0x797ed02b, 0x9bdf8587, 0xc8418160, 0xfcf0f3ff, 0x7e7ce614, ++ 0x91f7ec41, 0x8fdf9cd9, 0x43db532c, 0x05e514de, 0x81acb28e, 0xe81b0e90, ++ 0x6bfb803a, 0xc6e77c64, 0x1da2169f, 0x2fd0c748, 0x3b98c5f3, 0xdb298fc9, ++ 0xbd9475cd, 0x2ab6f583, 0xbbdfbe3c, 0x661bdc5b, 0xfea1c9dd, 0xf94724b0, ++ 0x23e708fb, 0x4514bfa8, 0x4efe2b86, 0x79cc3ba0, 0x8e8bc651, 0xd91b33c4, ++ 0x7bbd19e5, 0xf9e155b6, 0x37f59993, 0xbe4e1bad, 0xc7ea2f03, 0xcf9e1d73, ++ 0x2691bc70, 0xe9fdf0c6, 0xfb8b9fee, 0x1331ac6b, 0x9e2ba2ed, 0xbf50eb32, ++ 0x31c410f8, 0x08f9e7de, 0x7e98dbce, 0x4c66e70c, 0x66e702ff, 0x73853f4c, ++ 0xc39fa633, 0xe5d319b9, 0x08f89de7, 0xd03f5b38, 0x5bae0df5, 0xf3b4f7fa, ++ 0xcb932afd, 0x77f1decd, 0x02fc689b, 0xdbe08787, 0x8c9def8b, 0x6b75cf7e, ++ 0xfc7a775c, 0x6bade845, 0x3d323ff7, 0x1bdaf061, 0x8f84ab47, 0xe6253b5b, ++ 0x40ddb791, 0x3daf3ff2, 0x521d5b10, 0x89a06a2f, 0x71d88fda, 0x3ffb162c, ++ 0xaf85ef67, 0xcf25814b, 0xd47cf1d0, 0xad3775c0, 0x70ecfe43, 0xa22c0d65, ++ 0x34c36e7d, 0x0f0ffdaf, 0xe82a3de2, 0xba22e29f, 0xe987ee94, 0x8759a0bc, ++ 0x5d720e16, 0x373ae35b, 0x3badfb62, 0xc02571b2, 0x37df1877, 0xb84a4748, ++ 0xf5a5aef5, 0x2eee64dc, 0x3741fbc4, 0x8d87d05d, 0x94702ecb, 0x843b9c12, ++ 0xf7ebdcbe, 0xf125f416, 0xb7f75df6, 0xdf263fb6, 0xea5e4151, 0x6df4b940, ++ 0x9585ea2c, 0x7da07e22, 0xd3dfa0fb, 0x7a83b37d, 0x479bf786, 0xdff7abc6, ++ 0xff7c81ec, 0x6ec474c9, 0xb5f11b93, 0x41f1f775, 0xe030def8, 0xa872d067, ++ 0x60e0613f, 0x11977dd5, 0xfc7ebe63, 0x9f5489a7, 0x2e757f7e, 0x718154db, ++ 0x7b2cf332, 0x2d25c4df, 0x815a7fb0, 0x528b3271, 0x2e980395, 0xc44d6476, ++ 0xbf7918f8, 0xe96e6960, 0xd352dc01, 0xcfa4959c, 0x09932295, 0x96e50f91, ++ 0xb958f118, 0xaa094794, 0xfed4a4fc, 0x1c53faaa, 0xa9f2aa39, 0xe554c3b9, ++ 0xce69dc72, 0x237aaa51, 0xf1b3bbe3, 0xe0eb073c, 0xc33fa7ef, 0xb11f0fdf, ++ 0xc38df0e3, 0xd9e33f20, 0xc95de99b, 0xc67ca2ad, 0xc43ee5cb, 0xd3c01747, ++ 0x89d50a04, 0xfe1efb92, 0x39a67629, 0x7eeed42f, 0x71cb80fa, 0x4b85e719, ++ 0xbd22139c, 0x6bdb2c87, 0x37c009cf, 0x39be441f, 0x76d9d5f2, 0x1d6ed3f4, ++ 0xc63a75f3, 0x503ede9f, 0x44887e7d, 0x43fbbd37, 0xf43efc71, 0x6e96a29e, ++ 0xd047bb18, 0x1c674f21, 0xaef1f7e2, 0x15fdaf94, 0x0bd91af9, 0x88bf62bc, ++ 0x1bdf6354, 0xfefe7269, 0xbd47b40e, 0x491bc7a7, 0xab24f7bd, 0x20fadff1, ++ 0x9b65b3bd, 0xa44b4dee, 0x87d45eef, 0xefbd85eb, 0xdec281c5, 0xdef7bb5e, ++ 0x3960c2b4, 0xaaa9f35b, 0x595bbb3e, 0xcbafcaaf, 0x2fefe752, 0x3eda1f5d, ++ 0xfd563e92, 0x679362e8, 0x55abde04, 0x6e9efec2, 0x05127cef, 0x82bdd85f, ++ 0xbdf1ecf8, 0xb377e92b, 0xa1ebf5b5, 0x5653b43f, 0x92b39047, 0xf3d5cd3f, ++ 0xe5b5c9f7, 0x54540daf, 0xb574abbf, 0x6010fbc6, 0xbf94f14f, 0xc3f7f2e1, ++ 0x28531e7e, 0xe3101c9d, 0x81ec7d9e, 0xe01dfe1f, 0x3f277676, 0xe38d9d57, ++ 0xfb6f2372, 0xa41d3a17, 0x7d39a323, 0x3a03d9e5, 0x355d4794, 0x3fbc5e31, ++ 0x46d2b0d1, 0xb323af71, 0xc964ffbb, 0xe068fd07, 0x00589fd9, 0x4bc67fcf, ++ 0xb8f221a8, 0x90590f0b, 0xce2ff3ff, 0xc3663c90, 0xd5d19c79, 0x419fe75a, ++ 0x5ab92337, 0x42c5f9c6, 0xaf213fa4, 0x86abec18, 0xfcaf597b, 0x7082fe42, ++ 0x477338a1, 0x867feff7, 0x39b7d176, 0xc23b40bf, 0x5c07d23c, 0xa17db556, ++ 0xe85bbf8d, 0xd513efe0, 0xf891ef88, 0xadfdaac7, 0x5e5f3c26, 0x8ff1fe6d, ++ 0x775ee281, 0x68713e64, 0x61b1e02a, 0xd157bf27, 0x1fb831d3, 0x5a1be10b, ++ 0xaa3c35f8, 0xfffdfda3, 0x8dc7d501, 0x00800021, 0x00000000, 0x00088b1f, ++ 0x00000000, 0x58b5ff00, 0xd554700d, 0xdf6f3e15, 0x926c85fe, 0x23640fcd, ++ 0xd5ddbc24, 0xaf242110, 0x12489bf9, 0xa942125d, 0x48a0dd5a, 0x513ea2c6, ++ 0x9adfc811, 0xcda28da0, 0x83bf2ba3, 0xf8aad535, 0x945a2e37, 0x234d6819, ++ 0xb824193a, 0x3ac15194, 0xd420feba, 0xd5359866, 0x4d924a18, 0x9d4e2b51, ++ 0xfbdce7a1, 0x042fbb1e, 0x861b4eab, 0xef7b9c9c, 0xef9cf7bb, 0xee73dcfc, ++ 0x73f83399, 0x3ed8c019, 0x10a85171, 0x79e3cc00, 0xce01730d, 0xeb00e368, ++ 0x3891ca00, 0x0d304df3, 0x7f89dda0, 0xbe6b484b, 0x48650c5e, 0x0200cdfb, ++ 0x0a982d8e, 0x4eff1390, 0x4c9b6da7, 0xf9c69520, 0x56dbf717, 0x2fb41c86, ++ 0x4e62fdb0, 0xf71437f6, 0xbf31957f, 0x2475d390, 0x73f37407, 0x8fcf3c61, ++ 0xc015ccf2, 0x41e78592, 0x40ef2083, 0xbb3fa472, 0x0a915216, 0xd84a9610, ++ 0x2bdad716, 0xdbe1ae00, 0x3203b8d1, 0x81570ff0, 0x0c59ce99, 0x2a6bee5c, ++ 0x808df2ff, 0x5fe92ddf, 0x004a1172, 0x7e59ed1f, 0xb35387c4, 0xaa002f25, ++ 0x0b5414b0, 0xba7df888, 0xe503b73f, 0x6e144abc, 0x3f1217f2, 0xf9e0223e, ++ 0x85926a47, 0xbff6c0a0, 0xf5d7f69f, 0xe7f1623a, 0x0b5e9806, 0x0805439c, ++ 0x78b66f89, 0x3c5cf926, 0x819ab8e2, 0x19cfd1d6, 0xecab7e91, 0xdef17afc, ++ 0x016457f9, 0x4e065a9c, 0xb57bca1b, 0x1e403e08, 0x7685b35e, 0xfc7d49b8, ++ 0x55c412fb, 0x9c906488, 0xd5c5a553, 0xdd94e212, 0x67301bf9, 0x7686e026, ++ 0xedc4a7f4, 0xae78e3a2, 0xd5b9fa1c, 0x77ea1f11, 0xdb20a76a, 0x9655b470, ++ 0x6b7fb4ac, 0x9647c9f5, 0x11adf9e2, 0x9e501651, 0x8e077de5, 0x5d3d7e11, ++ 0x10be603d, 0x8fabb7a0, 0x4776e5d1, 0x7a622c58, 0xc80b460d, 0x6bd302b8, ++ 0x3d33c6b5, 0xb8f9f1dd, 0x4df813de, 0xbcb39196, 0x54c9e007, 0xca1275ff, ++ 0x2fbee6b7, 0x69252c8e, 0x0fa75637, 0x6bee01cd, 0x17f2e333, 0x281c015b, ++ 0xe48ef8ff, 0x1cecb3d0, 0xb88ad7f4, 0x9fd89ebf, 0xe703b47f, 0x6165bc4f, ++ 0xe6b07aee, 0x91bbb1b1, 0x9923b35f, 0x03227ce1, 0x7f9a1cd4, 0xc5485676, ++ 0xc69bb705, 0xf7083a07, 0x077914de, 0xf4fe7fce, 0x91bb5dac, 0x22ebb55f, ++ 0xdb6cc499, 0x788d7e86, 0x0c8b9e7f, 0xc394bf8d, 0x3f1703be, 0x9f9d8577, ++ 0xf730be2b, 0x7f9a6ac1, 0x73a65321, 0x3f0dfb74, 0xc403e49d, 0x17082beb, ++ 0x4ef5d139, 0x0990ea0a, 0xed326e37, 0x5fa02e3e, 0xbf2ab42e, 0x7eaebb24, ++ 0x551f4fe2, 0x2f753ea1, 0x4bb1fcfc, 0x1f55be50, 0x27da054c, 0x471e576e, ++ 0xf579daed, 0x51a9b7e2, 0xfb53d7f4, 0x185069bc, 0x6769a7c7, 0xbb53f392, ++ 0x6ffe2b86, 0xf03749e9, 0xce397d6d, 0x7ce20b4f, 0xa18c7013, 0x3e933059, ++ 0x355c5acd, 0x48fb949b, 0x328816ae, 0xadc440ff, 0xa22557e4, 0x307ca3e0, ++ 0xe18d80fe, 0x1ecfd13f, 0x2fcc4c91, 0xf4a04d9b, 0x64949c60, 0x7145dd82, ++ 0x62fc70ab, 0x767acc0f, 0x07f3620b, 0xfb8f4329, 0x1373c5fc, 0xf5a073fd, ++ 0x6dcff255, 0x239fe636, 0x72e2c049, 0xa5db39e2, 0x0afdf674, 0x1e2c97fb, ++ 0xced6f1f4, 0x10be46d3, 0x4aef947c, 0x1de95282, 0xbb343b48, 0xdffe5d04, ++ 0xeeadbf93, 0x6f2bedf9, 0xba9f3c33, 0xf73a63eb, 0x0fd98390, 0xc7b8e6de, ++ 0x3d246804, 0xd856fdf4, 0x4a5cc1c7, 0xf2676ef2, 0x8f43e3ea, 0x70522d1f, ++ 0xe797a1ff, 0xf3fa0114, 0xf4323172, 0x9633e224, 0x16be3912, 0xf7a1ef69, ++ 0x738e29a7, 0x3cee6de5, 0xf9d3f6c5, 0xa1e78111, 0xc703d266, 0x5eff1e43, ++ 0xcf39c589, 0xe65b830f, 0xc5eafc32, 0x7fb234c2, 0xbe5184ec, 0xfbea7289, ++ 0xfbe9f2eb, 0x910eebeb, 0x518f50bd, 0x0328a46b, 0x93cfafc7, 0xa68d7a0c, ++ 0x1dd28a46, 0xebe4ee34, 0xf04f9032, 0x13fa46b7, 0xc768dbed, 0x35f28dbc, ++ 0x10720a36, 0x794ab8d8, 0xc1586913, 0x5ed766f9, 0xdbf0370d, 0x68978fd1, ++ 0x9959067e, 0x05aeefcc, 0xb44bd7ee, 0xf43d7dbc, 0xe5e30058, 0x9ddd6998, ++ 0x91bff456, 0x4a2d879e, 0x3f55de62, 0xf3999d36, 0x5aaef3c3, 0xbf94050b, ++ 0xd50e9d47, 0x40798c54, 0x1443cc12, 0x4b90b91f, 0x0e5e70eb, 0xbda81fa3, ++ 0xf2883936, 0x8ff2633c, 0xd6cdfe12, 0x81c51170, 0x2633ddfe, 0x088f8d85, ++ 0x7b20af6f, 0x445c3983, 0x6e963879, 0xe90d2105, 0x43e23954, 0x80afd43c, ++ 0x059895e5, 0xdcf17b1a, 0xa0533ab2, 0x87cf11d7, 0x9b2cfe7a, 0x6b88e383, ++ 0xf1eb8d0d, 0x56537e8a, 0xd71f5c6c, 0x716fc8c7, 0xcb2bb8f3, 0x267a0534, ++ 0xda999789, 0x447a107c, 0x1efccf1e, 0x0770d2ad, 0x5f9489f0, 0x55be355a, ++ 0x54b1f3cb, 0x3ea22abb, 0x2ed0fb55, 0xc39957c8, 0x16628807, 0xefb44e80, ++ 0xfdf3083c, 0x9cf98cfa, 0xec6590ee, 0xeec39e5e, 0xb99a79e5, 0x20010837, ++ 0xfee9dabb, 0x8845ba42, 0x852f4488, 0xe07d4671, 0x33451334, 0xfc00ba30, ++ 0x00842e8c, 0x9ba08ba3, 0x87a1cbd1, 0xc2212bd1, 0x070ecc28, 0xf707dd81, ++ 0x3ef0873a, 0x6edd9f86, 0x6cb97ba2, 0x8b260429, 0xf7375a8f, 0x81e3f3fb, ++ 0xc7e2be59, 0x1410b1e3, 0x7ceb9317, 0x6028ccb8, 0x62e3af7e, 0xefc4ff23, ++ 0x22e42092, 0xb651035a, 0xc8e465cf, 0x907ccfb8, 0x81d7c4cc, 0xdff5f18f, ++ 0xa8ca8f13, 0x270a5662, 0x726ea5c1, 0xc342b93f, 0x596118e5, 0xea97b71e, ++ 0xdbaf1896, 0x8b93330d, 0xed7383ee, 0x67247909, 0x17ed7259, 0x958ca612, ++ 0x337e5dee, 0xd2b2d1e6, 0xf22f0eda, 0x957f6f77, 0x2fb555f3, 0xeb5f9079, ++ 0x717ce7ee, 0xc645a96d, 0xefd8542a, 0x1dbc805f, 0xe2127f93, 0xa8457a24, ++ 0xa524aa44, 0x9dc60116, 0x33af744d, 0xd6d95c63, 0x4a33cb02, 0xd5844012, ++ 0x1465e8b3, 0x7ebc8d27, 0x76e4e35d, 0x96556adb, 0xb31ee9bb, 0xc4255387, ++ 0xfabacd7f, 0x372fba6c, 0x9ffef95a, 0xbce6954c, 0xf0daba8a, 0x5c497b3c, ++ 0x93579c4f, 0x520a8f90, 0x7e3ba747, 0x2f38f7fe, 0xb9e75df0, 0x6e9dca5d, ++ 0xf9ec17c4, 0xae9ff640, 0xbdbde7dd, 0xa26cb255, 0xfcec9df3, 0x477e4a68, ++ 0xe1dd4e27, 0x3eb4abf2, 0x4efdc296, 0x3d4cbb25, 0xf6e5dd3f, 0x9fce8afd, ++ 0xf75b1e38, 0xca612bf5, 0x20a19f43, 0xdcefcfb8, 0xd75a7aca, 0x95e68a66, ++ 0x9d7ebda2, 0x7e4adc7c, 0x80b1fba2, 0xfa865bc6, 0xb2107d07, 0x76a8f8b2, ++ 0xbcc7ad9e, 0xdd8838f1, 0x2e21fb86, 0x9d7f7e65, 0x1a2ba705, 0x56890703, ++ 0x3875dd2a, 0xc43ce743, 0x57c711ce, 0xa58c5f90, 0x8cfd607f, 0xee0ce9c5, ++ 0xeafe5a8f, 0xed787fdf, 0x21face74, 0xf6db0e21, 0xbfaff37f, 0x4edbbda1, ++ 0x5e5a6439, 0x0ef1efb5, 0xf8f407ea, 0x90d06ac3, 0x9c78f45f, 0x8b0b67d7, ++ 0xb7c5dd6c, 0x0f9afad1, 0xa794bc06, 0x06881b2f, 0xf58e5ca9, 0xe3ce9d1f, ++ 0xbfe3af42, 0x7dcc7e16, 0x52522f52, 0x65ecbac7, 0xbd436431, 0xd0bea9da, ++ 0x73fec278, 0x1a4dfa3b, 0x7239f7ad, 0x9a95af50, 0x5f872d5e, 0x825f52b7, ++ 0xefa4a8db, 0x95fe4d2a, 0x2572dd4f, 0x42ab8bd5, 0x803df896, 0x42069bff, ++ 0xa6ee481b, 0xca71c69d, 0x9b7fa498, 0xd5337df6, 0xfbaa5e6b, 0x60daeb8c, ++ 0x7f293feb, 0xc719f5b5, 0x64a7775f, 0xf76abb31, 0xe675681f, 0xd21adaed, ++ 0x3ffac1cf, 0xba86c86b, 0x21dd3fb5, 0x75cf893b, 0x9edf2cc8, 0x58fccf5e, ++ 0x654f0f5f, 0xe3d11f32, 0x6026d576, 0x638eb3f5, 0x1f36f3f1, 0xf9f8a3d9, ++ 0x6317566c, 0x11eacf3d, 0xefcc27cc, 0x0113118b, 0xf4c5eefd, 0xcf098f71, ++ 0x40bfb179, 0x6f7b7aa6, 0x7efe0f97, 0xbd3e5c61, 0x7717afde, 0x8fa959d7, ++ 0x28fb15ba, 0xfc3f6a1c, 0x7c8ed05c, 0x15a066fb, 0x1a415a28, 0x87e54dd5, ++ 0x3ed10844, 0x1ab87a10, 0xcb4538a9, 0xefac2e27, 0x9248f013, 0x509480a6, ++ 0xdaf8eb1f, 0x1725bb34, 0x53e61864, 0xdf0c0be4, 0x8c7a55a7, 0x48beabdf, ++ 0x73e50561, 0x6fba7dfe, 0x507d61b6, 0xf261c808, 0xc3fe2899, 0x8c1ad575, ++ 0x57958e35, 0x8b994e12, 0x37eb0c4a, 0x443c2ea6, 0xa5fd5dfe, 0x041f8279, ++ 0xaabbf244, 0x6813c028, 0xc6237997, 0xbb0ff2f9, 0x4fcf1521, 0x6ea130fa, ++ 0xa055bf60, 0x1926c5ba, 0xf41eedc7, 0x19b80a0b, 0x2fd12330, 0xbf73b8e2, ++ 0x626c353f, 0x1701517e, 0x465d563e, 0x24205b38, 0x29db8b9d, 0x61deb4a2, ++ 0xef317165, 0xf94c8770, 0x88dfaa68, 0x11a3767f, 0x88c51cff, 0x4695f4f7, ++ 0x460373bc, 0x1a7667bc, 0x46ab75f1, 0xe69bbcfc, 0xd45fd619, 0x67e06b5d, ++ 0xb0dcbb6d, 0x62d0e2fe, 0xe7673f03, 0x73f586f5, 0xe61b967b, 0x1b56fb8b, ++ 0x9b3f75e6, 0x093f07e8, 0x33f04fb7, 0xec129813, 0xf759dbaf, 0xf743d283, ++ 0x7ff9ce18, 0x47917fdb, 0xfd9a0bcb, 0x03d5aa7f, 0x6f0ea4ef, 0x2abd70a5, ++ 0xb3b5e799, 0x16d509ef, 0x2bbdafd6, 0xd0a5d665, 0xf37eed5a, 0x1c1bf76b, ++ 0x2779ccda, 0x7c88e5e7, 0xc959f290, 0xc91d7f31, 0x1c0d1655, 0x62a13544, ++ 0x8d2ebbb8, 0x7240fbd6, 0x4e4fe34e, 0x4aeafeb4, 0xb886cc01, 0x1c5a7e42, ++ 0x75d46bcf, 0xae2e1a62, 0x641436fa, 0xbe8296e9, 0x241efe22, 0xa2fbf254, ++ 0xe60497c1, 0x2a6a5c04, 0x90a47bf5, 0xbf8eabf9, 0xfd847efe, 0x1fa95800, ++ 0x4143d930, 0x8ef564f7, 0xf5644dbc, 0xb3eac298, 0xbd850537, 0x8f6b5d2b, ++ 0x777e51e4, 0x1eed2b67, 0x24cc6dc4, 0x139eac4b, 0x2a5241a2, 0x4bb18a46, ++ 0x1f06d2eb, 0xced871f5, 0x0f0005c2, 0xd41aaa99, 0x33be2642, 0x66dbc15a, ++ 0x28f2e9fa, 0xdf783d6b, 0x0dce0a0c, 0x3bedf8a5, 0xd1e64ef3, 0x111365fd, ++ 0x3f7a1289, 0xf347ddf1, 0xb24ddf67, 0xb7cc3f51, 0x12a49351, 0x023dea14, ++ 0xd24e43eb, 0xc4249766, 0xbb0b26ef, 0xcbeb40b7, 0xd2f0d06e, 0xda65b2fb, ++ 0xc5b883f9, 0x37e7cc4a, 0x70c9bdf4, 0x688d7269, 0xd90150ef, 0x32dffb89, ++ 0x7d4251c3, 0x654af829, 0x7debcfde, 0x87f174da, 0x5f7aabdc, 0x4df5be7b, ++ 0xbf4361ae, 0x2733bb0c, 0xf89c8f7d, 0x9bd715ee, 0x39b83fef, 0x8343dd99, ++ 0xfbd9739b, 0x31ff7c62, 0x810dffb6, 0x727e0cf7, 0x0d5fe753, 0xfab377fe, ++ 0x9a3e6189, 0x8e996e35, 0xc95f47fa, 0xc40bf859, 0x5b65f46f, 0x68abf505, ++ 0x424f5eb7, 0x607d1d3f, 0xef3a02d6, 0x0ff9ebbf, 0x5740ef86, 0xe9bbbd84, ++ 0x3aef1e7a, 0x5768f8c6, 0x7a89d194, 0x4eadfdea, 0x02867fad, 0x85c797aa, ++ 0xef64f229, 0x797a9735, 0x7f303fbd, 0xc7dd2d5a, 0x3356b903, 0xcf9cf9a7, ++ 0x7e73b4a9, 0x31a222e1, 0xf513638b, 0xf80203b7, 0x6587f404, 0x9bc7f482, ++ 0x4f7fdf71, 0x3f25de53, 0x5e3d5b6f, 0x6878c664, 0x28de8e2b, 0xa7d73da0, ++ 0xfe93ef2b, 0x39831602, 0x7cce4c19, 0x4d861bea, 0xb980916a, 0x4db9fd20, ++ 0x277a660d, 0xd18ea29b, 0xbde49d8d, 0x81fa81bf, 0x8f8f2b61, 0x83736f1c, ++ 0x701c7a8a, 0xffcc032a, 0xfc98624d, 0x842bdd56, 0x8b7f3076, 0xc4a7175a, ++ 0x6bdfd1f5, 0xfea6dfa8, 0xe9c49626, 0xe9811ea7, 0xf2d119f9, 0xc3d6fd38, ++ 0x978e5af3, 0x6b717ad3, 0xdec590be, 0x02e2809f, 0x1d51f3cf, 0xefe7eea2, ++ 0x0750d3b2, 0x7ab06baa, 0xc942fd63, 0xe530b66b, 0xe75dfd0f, 0xcecdc7b4, ++ 0xf7f2f2c9, 0x6d07ac9a, 0xdfbb20a1, 0x280d7923, 0xeb05b767, 0x3e1bea1d, ++ 0x368ef604, 0x0961ef4a, 0xe1ed3976, 0x0adc3a7d, 0xb7b3e7c0, 0xe1cb7cd3, ++ 0x4f94e3c1, 0xc3251e42, 0x2a9070cb, 0xa4b49f28, 0xdef5601e, 0xcfddf0ff, ++ 0xd8b7fb4e, 0xd53ebca3, 0x87cefdde, 0x916de8cf, 0x3bd90b47, 0x72479c97, ++ 0x72e972e8, 0x72e8b8ea, 0x6ef9f7c6, 0xafdfd7ff, 0xf1e87e74, 0x4f14f98d, ++ 0x577f3f88, 0x169b8514, 0xb97df24f, 0xe835db97, 0xfe744bf2, 0xdf7f00ea, ++ 0xf747fb8b, 0x3e531f5d, 0xf960ec3c, 0x4fdf7cf0, 0xff65b3d4, 0xea078661, ++ 0x97e92379, 0xa25167a0, 0x47fda39e, 0x7e942d1f, 0xdcb17ebc, 0x8d6f7b08, ++ 0x4f26ff6d, 0xf65befc2, 0xfc8c79bd, 0x777f45ab, 0x4f7c63df, 0x3ec14db0, ++ 0xf7b26335, 0x1265bc72, 0xfe9b2fea, 0xf1b30cfd, 0xde81547b, 0xae28fba3, ++ 0x7bc14ea9, 0xbf41fc97, 0xfd68f777, 0x837d108b, 0x8f3a7de5, 0xa0837efc, ++ 0x7f4ffbb2, 0x780a08af, 0x956d91bf, 0x881f760e, 0xf9321d33, 0xc1f41eed, ++ 0xd9bbf908, 0xa9decc97, 0xafcbf427, 0x08eb955b, 0xd5ef35bf, 0xdd3f5366, ++ 0x5ae5d6fb, 0xa3efc65f, 0xcb2fcd72, 0xbf927ce9, 0x6bf98d30, 0x855f2699, ++ 0x0f1eeb1d, 0xe45576a5, 0x3bda12ef, 0x0c37e6c7, 0x007fdcfd, 0x9e7336ce, ++ 0x00001b00 + }; + + static const u32 usem_int_table_data_e1[] = { +- 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x33ab678a, 0x32ea7830, +- 0x31e9c830, 0x43d24c30, 0xb712d388, 0x9fa65173, 0x8181859d, 0x81b98813, +- 0x5f881798, 0xbc303231, 0xff5e2466, 0x3b046147, 0xe181804b, 0x0b6f9013, +- 0x32089fa4, 0xb2075c30, 0x0371033f, 0x88073f90, 0x35b10057, 0x480fbf90, +- 0xa3e204df, 0x1845fc40, 0x095ff9bf, 0x42156fc8, 0xe3443fe5, 0xafc4159f, +- 0xf980825f, 0xb1e40472, 0xe42269e1, 0x0a6dc7c7, 0xde040ef4, 0x67ca86a6, +- 0xe0606553, 0xaac58a07, 0x91dbf843, 0x6281f3e4, 0xf610aaec, 0x8606396b, +- 0x1db9405f, 0x7dcdd86a, 0x0dff9403, 0x9a86ab94, 0xf1b90003, 0x03685054, +- 0x00000368 ++ 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x18140b8a, 0x18d57c18, ++ 0x19d57218, 0x23aa1e18, 0x0f8969c4, 0xdfa65173, 0xc181859c, 0x81ad8812, ++ 0xdf8816d8, 0xbc303231, 0x7f5e2467, 0xbd8208a3, 0xa181805f, 0x076fc809, ++ 0x0c4229d2, 0x7640e90c, 0x055f1033, 0xf1023ff2, 0x2d3e205f, 0x2a20c0cc, ++ 0x0c60c0c8, 0xdc4032c4, 0xfcdf8222, 0xa6f20256, 0x44fca8c2, 0x10afbe34, ++ 0x840bfd7e, 0x23afcbf1, 0xfb0d8f20, 0x1f1f926a, 0x3bd02893, 0x1e43b810, ++ 0x964b7f95, 0x1cb9e181, 0x02818303, 0x2489df84, 0xbb1404ef, 0x6f610b2d, ++ 0x38606714, 0x92eb9403, 0x26ee6ec7, 0xa059fca0, 0x1cd41f9c, 0xc9488100, ++ 0x00036836, 0x00000000 + }; + + static const u32 usem_pram_data_e1[] = { +- 0x00088b1f, 0x00000000, 0x7dedff00, 0x45547809, 0xbedd70b6, 0xe9d3bb7d, +- 0x84849d25, 0x1674b090, 0x26c43510, 0x630a0840, 0x944c2127, 0x615151a8, +- 0x8408ec44, 0xf9707d90, 0x37d7d470, 0xdf95012c, 0x3e30eb89, 0x0e0c1a74, +- 0x1036a0c3, 0xc6c06a30, 0x680e8300, 0x8cc08378, 0x364584cb, 0x5c710921, +- 0x7f9e6466, 0xbb75539d, 0x48e9bdef, 0x9bdffc74, 0x3f6fef37, 0x556ea2bf, +- 0x5b3aaa9d, 0xaa753a9d, 0x42049462, 0x1be426ae, 0x71f4d1f8, 0x10921091, +- 0x69f2bb4e, 0xb910963a, 0x96bfca27, 0xff6e0d56, 0x401904fa, 0x5be6b9c8, +- 0x4254e65c, 0xc1513d3c, 0x39f969ab, 0x4cdf9e7f, 0xbcb60bcb, 0x7cd230ef, +- 0x08d116f5, 0x16ed86e5, 0x4ab9df6c, 0xd6be43f0, 0x55d8fedc, 0x45bddf34, +- 0x68286b24, 0x2066ceb2, 0x889c8439, 0xb467ec22, 0x2122481b, 0xad961665, +- 0x1663bd5e, 0x62de57f4, 0xfeda1626, 0x81e8b344, 0x82b582fc, 0xaafed09f, +- 0x4a665b5f, 0xf9e6f0a6, 0x45c58085, 0x371f6bf3, 0x2c84ecb9, 0xa381feda, +- 0x19c846c3, 0x9971145f, 0x81e51e70, 0xfc2a424c, 0xd324a71b, 0x041b15f6, +- 0xafc281b7, 0x13be7558, 0x2cd157c6, 0xbc29170d, 0xe25675ca, 0xfefac91a, +- 0x6d7f4086, 0x2dbfb0c7, 0x57f40652, 0x136ee17e, 0x929e6111, 0xd355da07, +- 0x95bcc071, 0x1af8cf7e, 0x18446b89, 0xa1bfd59f, 0x357ad1fd, 0x986e0b2f, +- 0x78818d62, 0xaf9d1c61, 0x60bfa659, 0x9bd5f983, 0xf3d5d846, 0xf30add28, +- 0x36aff0a8, 0xf8c1b14d, 0x32ca9b56, 0xd72af0c3, 0x515c493d, 0x4cadf1aa, +- 0x9555e81f, 0x3e33d3eb, 0x054f19a2, 0x06c05925, 0x6e9bf678, 0x7efe151c, +- 0x7a458858, 0x3513ae57, 0xf1e529f0, 0xfd3efcbb, 0xbc83c527, 0x9b5feecd, +- 0x02dba61a, 0x2bb7fd27, 0xa71eb74c, 0x1ceec742, 0x7d257c35, 0xc741e80c, +- 0x6273e8d3, 0x092f84fa, 0x2e7ca7d3, 0xbe33d3a4, 0xf4ae9891, 0xb3fbf1b9, +- 0x574c5cbe, 0x3e983cf9, 0xd4c22bef, 0x7ac12bef, 0x31d37c6b, 0xf179f26d, +- 0x72be8bfb, 0xeaf9d74c, 0xdf7afbf0, 0xf8374c42, 0xb2fefc64, 0x01a6396f, +- 0xbe4da74e, 0xfb369895, 0xab6f58fc, 0x2da61d6f, 0x5f7e00be, 0x98e7f1c1, +- 0x748cf248, 0x710f0efe, 0xb8937252, 0x449e4f62, 0x2c2571f3, 0xce53389f, +- 0xa27cd133, 0x3e29e697, 0x7982ab92, 0xae4f9a66, 0x1f43e563, 0x3451f924, +- 0xe566543f, 0xf93c2b69, 0x6b4f9a16, 0x5623e564, 0x34d1f9c9, 0xcacfc23f, +- 0xcc10db2f, 0x65fcd2b7, 0xd59e5601, 0x346c0a4a, 0xf964159f, 0x029ebdec, +- 0xb767cd3b, 0x87ce7cb3, 0xe6838172, 0x7b583a73, 0x1203de3d, 0x6d284d99, +- 0x3c8b959e, 0x6f3441c6, 0x37137722, 0xa37c8bc5, 0xe28138c7, 0xf9617241, +- 0x5827f976, 0xc2e4c9be, 0x367976f2, 0x1e4b3796, 0x572a3f2c, 0xc9b37961, +- 0x917fe583, 0x56fcc5ef, 0xa6e58bc9, 0xfac37ffa, 0x2c5e4d5b, 0x865faa4f, +- 0xc64916f9, 0x1beacbf2, 0x498b7eb1, 0x9627f2c6, 0x9933d2fc, 0xef04fb96, +- 0x8b67c053, 0x49396f05, 0x2409fe07, 0x69fe5095, 0xe074c810, 0xc98107d7, +- 0x20fcd1c6, 0x605dca13, 0x200bce57, 0x001bf8af, 0x1f17b2f9, 0xcf384549, +- 0xc2891c21, 0xc70e2f11, 0x03573bbd, 0x5cbbbdc7, 0xd422f381, 0x1fe96c5b, +- 0x2beec09c, 0x5dd9e3b5, 0x0579c0a1, 0x37fbd8e1, 0x26eff72f, 0xbbf3c76a, +- 0x0b4e052a, 0xdfed89c2, 0xd3ed3678, 0xbed367e2, 0x20767e10, 0x37fa127e, +- 0xb577ec9e, 0x377ec9f8, 0x70779f84, 0x07fa833c, 0x5abbd367, 0x377a6cfc, +- 0xe03f9f84, 0x6ff48678, 0x69efd95e, 0x5efd93f1, 0x221f3f08, 0xc1fed49c, +- 0x8b5f7e69, 0x43f7e69f, 0xe104f9f8, 0xbcdfef0c, 0xe2d41ec6, 0x10c1ec67, +- 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0xd77fc5a2, +- 0x49303d09, 0xddb039f2, 0x9a3f6367, 0xde6c4155, 0x7fdf4595, 0x88dff114, +- 0xbb44fd76, 0xaca26ed3, 0xc03efa2e, 0x45e8e515, 0x83f68b9f, 0xf1a21af2, +- 0xf912fb89, 0x72698bff, 0x8b3bf502, 0xe123b3b2, 0x949d89ed, 0xa9e9af6f, +- 0xcdf23ea6, 0xf2130db6, 0x714fe351, 0x7cc7109e, 0x6493c456, 0xf37b72f0, +- 0x3f4fd3c8, 0x37b1eced, 0xa43d0877, 0xd05093f5, 0x2209954a, 0x78a0c4ef, +- 0x2564fe88, 0x75801e90, 0xfb197d36, 0x61dcf89e, 0x716d8e5c, 0xf6c74b6f, +- 0x3a6ab915, 0x79d14bfa, 0x51eef5de, 0xf57fc8e9, 0xaafd3553, 0xaff9235a, +- 0x7bff9ddd, 0x75b42f3c, 0xb9e45898, 0xc669747c, 0xe41bb573, 0xfdc59bed, +- 0xc7476dc8, 0xbcbe3158, 0xc61256cd, 0xb66dd9f3, 0xbb721294, 0x478f3c6c, +- 0xf1b36f6b, 0xca9b3abc, 0x1b36d5e3, 0xf2d37bcf, 0x27ddda6f, 0xbb5a0f08, +- 0xfef8c3e1, 0xff7e54d9, 0x520d5e21, 0x1bd938bb, 0xb8acbcc0, 0x66f64614, +- 0xc77f959c, 0xc8c0a12f, 0xf9fc31ac, 0xea266182, 0x49665b67, 0x9b54ec98, +- 0xd87642ec, 0x4e925e96, 0x0df11272, 0xbbdbd6e3, 0x19f745f1, 0x6b7c0856, +- 0xf3b7d4fd, 0xa9bede75, 0x08c56e72, 0x8bbd13b4, 0xd9b74e90, 0xbf315896, +- 0xde97b254, 0xc3f5bfb0, 0xca7cba0c, 0x7994fe9e, 0xd815bfa2, 0x512f649f, +- 0x8b133fb0, 0xfa0cfffd, 0xbbfebcc5, 0x819815e7, 0x60e3df46, 0x9e4fbb4c, +- 0x68cf4b1e, 0x439c55a5, 0x0ff7bf44, 0xfacd95db, 0x93d82578, 0x75830d0f, +- 0x3b9e66d5, 0x709e9131, 0x5e31b27b, 0xd849177c, 0xdbc2b285, 0x3df91a37, +- 0x637bed4d, 0x27289d9a, 0x73d0f1e9, 0xc3ef8a7f, 0x31c78555, 0xc518daae, +- 0xf9f9a257, 0xba63a9ea, 0x67a8107b, 0xc6dec23d, 0x8f48ed12, 0x3895cf19, +- 0x8efc6b5f, 0x3f28ba77, 0xf77f9aaa, 0x2918a6c4, 0xf400c25f, 0xddad744b, +- 0x8a4af9df, 0x115d7f69, 0xab486afb, 0x6dbf8951, 0xa32c42a1, 0xf3bf7bf9, +- 0xf3f22154, 0xfadd69fe, 0x6d75c156, 0xf7e5ca48, 0x564e4f17, 0x5fc3d962, +- 0x71c25f77, 0xa4ddc76e, 0xcf5c9d67, 0x3fbebffe, 0xaf34e8d1, 0x66debd44, +- 0x97f7fbd0, 0x50fddc85, 0x9afd8ff0, 0xdbbcf74c, 0x22ef7c8b, 0xde8c98bd, +- 0xfb07d46a, 0xbf9366eb, 0x501e0324, 0x30dfeeef, 0xc0af2a2d, 0x08b0fef7, +- 0x326b2e7e, 0x1aa677d3, 0xbf208fc0, 0xa31f6a2e, 0xb7eda7f1, 0xf9abdb06, +- 0xbfb69a39, 0x216cd313, 0x764bb791, 0xb9653387, 0xb398e501, 0xd9f067da, +- 0xec987db1, 0xfddabe8d, 0xad3bc84c, 0xb7fb0dbd, 0x3c4afce1, 0x8c4c7bfc, +- 0x6b24aef2, 0xec7fffec, 0x810f0a30, 0xcbac2b1f, 0x82aa7471, 0xeec24afd, +- 0xe8f9146d, 0xd5a94af5, 0x94bef113, 0x149d6a54, 0x7df52f41, 0x874a87c4, +- 0x942bdb77, 0xfce5a7e7, 0x60af684b, 0xbe4d9f5e, 0x20471ddc, 0x675e20ff, +- 0x47e36a2f, 0x9cf7bb9f, 0xbe3a73b3, 0xbd9294aa, 0xbb018f28, 0x4307ec00, +- 0x489bd2d2, 0x3f7c9a3f, 0x743c034e, 0xfca167bd, 0x3f05f7db, 0xec7e0a76, +- 0xd8056e4b, 0xb7dcba51, 0x4bc71d95, 0x2527401e, 0xf5274889, 0x39dd4699, +- 0x8b16568c, 0x5fb0c675, 0xfc8f87f2, 0x90cbf646, 0x17ec31e1, 0xcf224fb4, +- 0xf12ed1cf, 0xb445c844, 0xec313c4b, 0xf0a36697, 0xe779c4df, 0xadab9369, +- 0xfa70f013, 0xcefa44e6, 0xdbb469cd, 0xfb3ec04a, 0xdc5cd9e9, 0xee865994, +- 0x3b0853ef, 0x760c1191, 0x5e7077da, 0x1abbcc55, 0x1cd6ffff, 0x883f1bc9, +- 0xffd197e7, 0xfb75f2ab, 0x40b80719, 0xfbc76cbc, 0x1f744570, 0xf9d632ae, +- 0xe9baf7da, 0x88974504, 0x601e11c3, 0x5be22217, 0x5176e2bd, 0xa30c3a71, +- 0xe6fde774, 0xfdbf6ef4, 0xdae281ba, 0x882c7d3b, 0xb5bfb9df, 0x7b571f4c, +- 0xed99e443, 0xcf88ca5c, 0x86b41676, 0x53495fd0, 0xabc9c519, 0x73f6fa3c, +- 0xe3bfa32a, 0xddbf8fac, 0xcf4535e6, 0xd6ebbe97, 0xc06fac5f, 0x9714d5ee, +- 0x8b8f15eb, 0xfad1c38a, 0xf2943f50, 0x46adbc78, 0x6f655f9f, 0x7ddf419e, +- 0x12aeac66, 0x34cce7d7, 0xda8f8c32, 0xcff3a3ab, 0x1ecf0202, 0x9e1a5a12, +- 0xd878efb5, 0x7bfc8d8a, 0x540981a4, 0xe1c1e5af, 0x3a2705f7, 0x5b65d67b, +- 0x2c53e62f, 0xd881ace2, 0xf189daeb, 0x2e57cc46, 0x83c4830a, 0x302e70fe, +- 0xa30d464e, 0xbac299ef, 0x8705e775, 0xd0356f77, 0x03e147ff, 0x3c26ed71, +- 0x9813cfe8, 0x5afb40cf, 0x807f3fa3, 0x68e0ea75, 0xecebfebb, 0xb3bbc3f9, +- 0x58ff7e63, 0x5038b52b, 0x7610f8af, 0x383a4800, 0x6ca77c5c, 0xf68a1b28, +- 0x2378ad8d, 0x4c95c3ed, 0x0acaf79e, 0xa1bb9f62, 0x0ddf8f9d, 0x327c8a9a, +- 0xa679fd12, 0xf302cefb, 0x6f9f94c8, 0x3573e328, 0xa672f3f4, 0xd7c4622b, +- 0xb1307896, 0xbcfff04a, 0x1fa0f78a, 0x8c00b167, 0xdf1063df, 0xbdc4969f, +- 0x26062da4, 0xd514cc23, 0xb5e4f3ca, 0xe9043cef, 0x8d7d0f3b, 0x8b077da3, +- 0xda7bf805, 0x37dfd138, 0x74fbd1ba, 0x7e894d1f, 0x3ae282bf, 0xe17df8da, +- 0x17efafbd, 0x9dfcb1fd, 0x953e3c91, 0xc35a7449, 0xeba71fb4, 0x2b74ddc5, +- 0x53b83c93, 0x0f0f4eab, 0x773e7e45, 0xf74a824f, 0x0475b56f, 0x8eb44ba6, +- 0xf75fd96f, 0x595dd23c, 0x5881defc, 0xdbefe897, 0x117e8bae, 0x9301acf2, +- 0x1a8e816f, 0xcf91ef81, 0x2e93296c, 0xa10e74c9, 0xbf8bcfbf, 0x35fd1173, +- 0xf9493d1c, 0xbdc47b3b, 0xa75c6d70, 0x8a0433ea, 0x3c107ef0, 0xd08f118f, +- 0xdf8ca5ca, 0xf5e6d28f, 0x3504017f, 0x7fe05f6a, 0x00007fe0 ++ 0x00088b1f, 0x00000000, 0x7de5ff00, 0xd554780b, 0xb3dae8b9, 0x24999ef7, ++ 0x42499333, 0x49af0842, 0x701a8802, 0xb15e1008, 0x9441024c, 0x420a03a8, ++ 0x84089c45, 0xd112f210, 0x03b39f43, 0x4f6950f2, 0x0f52d62c, 0x89e0a0ea, ++ 0x0201b41e, 0x60e8188d, 0xda2d43c0, 0x3eb01160, 0xd5e4013a, 0xd1500c90, ++ 0xd77af4b6, 0x67b5afff, 0x4899def6, 0xedce78f4, 0xfcfc77bd, 0xf7af6b16, ++ 0xfaff5eff, 0x4e648ad7, 0x21226425, 0xa68fc25f, 0xc8424407, 0x59da68e8, ++ 0x8451d348, 0x81ac9728, 0xc121022d, 0x4d3f7fbd, 0xa172117a, 0x92cba671, ++ 0x25c14849, 0xe422706b, 0x0b010503, 0xf3b49f2d, 0xeb44877d, 0x2514ee57, ++ 0x8ded3728, 0x1b1df6c3, 0xabe40085, 0x9d3fad2d, 0x9de1f340, 0x76817922, ++ 0x1336824d, 0xb4e42349, 0xcb9fb095, 0x38d2f98e, 0xb4dcad96, 0x578c1e6f, ++ 0x712164d6, 0x46e9fdb4, 0xa5f903d1, 0xa100845b, 0xbebe55e3, 0xfb419cc6, ++ 0x1a10145b, 0xbf345ce2, 0xcbb349e5, 0xbd8ac84e, 0x36423a1f, 0xadfbce42, ++ 0x75c665c4, 0x10e43594, 0x36d81e52, 0x2fb68325, 0x4db82adf, 0x8df2ffb4, ++ 0x7e603b17, 0x60f28de5, 0xa4b7f691, 0x86b8813e, 0x24bfb1b2, 0x49cb5e30, ++ 0x3ca76f1c, 0xbb2bc608, 0x889990fa, 0x03d94eb0, 0x3ce92aed, 0xb8eadd60, ++ 0x701bfde7, 0x959e153c, 0x68f1d32f, 0x04d7aabd, 0xcab12c37, 0x8f307c44, ++ 0x66e3d78e, 0xf58368bf, 0xd8879ad5, 0xd928ebb5, 0x0f28eb05, 0xb14f326c, ++ 0x9936fcc1, 0xfda2734b, 0x37ffa92d, 0x6436fcfd, 0xca69f6f7, 0x3f79e98d, ++ 0x6890e905, 0x4f109cbe, 0x4897ed03, 0x61f4f301, 0x091fefd1, 0x25ef8849, ++ 0x597122f5, 0xcc53fda3, 0x44494213, 0x93fe9f79, 0x63d941c2, 0x8cc96c0f, ++ 0x13a96de2, 0xdbc51670, 0xa3c72725, 0xf6d3ce14, 0x053fa6af, 0xd4f9d07c, ++ 0xfe989df9, 0xe98e9fcc, 0xc2177e53, 0x50ff69ed, 0xddf8374c, 0xff19fdf8, ++ 0xfa374c58, 0xe73e983d, 0xc0698a9f, 0x2f7ac5ef, 0xba6367f8, 0xefc3efd9, ++ 0x30cbf92f, 0xe0d7f7ad, 0xcbfc57f7, 0x57eadd31, 0xfe6bfbf0, 0xf83698b5, ++ 0x0edd30eb, 0xa369a2f8, 0x76f5803f, 0x6d31ebf9, 0xf7e037f2, 0x4c26fedd, ++ 0x3a3871d7, 0x448149f2, 0x10f0e0e1, 0x493b4527, 0xc814f62e, 0x65ec9f34, ++ 0x4ab9b4f9, 0xd3e69981, 0xe14f347c, 0x2c115192, 0x467cd0b0, 0xf01f2b0d, ++ 0xa5685243, 0x2b0a01f9, 0x29e75acf, 0xacf9a38c, 0x643e563a, 0x4f1852a3, ++ 0xac0243f3, 0xc1ad86fc, 0xbf9a04c2, 0x0f9581a1, 0x6c93266f, 0xc83c3f34, ++ 0x3c87b9f2, 0x9f34ec93, 0x79f2cadb, 0x1c93291f, 0x62179f34, 0x07b7c7ed, ++ 0x2bad9744, 0xaecbb61e, 0x6ae284f9, 0x47ab72a3, 0x66f3471a, 0x4dc443d7, ++ 0xf0cca3e1, 0x3c287d48, 0x07960f64, 0xbcb17b95, 0xf2c1ecd1, 0x980594f7, ++ 0xb0fb25df, 0xc95294fc, 0x961f66f2, 0xc11e515f, 0x60ac937c, 0xcfd6b5b9, ++ 0xcb0566f2, 0x62d76a33, 0x00e5bbff, 0x3ed4e796, 0xcdbbe589, 0xd9ff2c01, ++ 0x2678cfa3, 0xc14afcd3, 0x23d034f7, 0x3648cb4d, 0xba4353d0, 0x6ad3d297, ++ 0xfa06cc81, 0x1d1031fd, 0x7dd5cba5, 0xdb87c8cc, 0x117bc9df, 0xbd7f17f8, ++ 0xd2fa5f20, 0xfed899e3, 0xa647ec79, 0xeed788fd, 0xb1ddf727, 0xdf727eba, ++ 0xa9fb532d, 0xe32b7a87, 0xf6cfd67a, 0xe7ebc777, 0xdab96ef3, 0x8f9c36cf, ++ 0xcaeb67bd, 0x7ebe7dfd, 0x50afbf3e, 0xf38dd9fb, 0x7cd9ea49, 0xc3d7df1a, ++ 0x08fdf1a7, 0x3e705a7c, 0xcf9b3da9, 0xf87aa3a8, 0x811a3a8c, 0xa7ec21cf, ++ 0x69facf4f, 0x4f87aa3c, 0x7c08d1e3, 0xf575c7de, 0x46bad9ef, 0x67c3d31d, ++ 0x7c08b1d4, 0x64f9c13e, 0x5d9facf6, 0xb3e1eb1f, 0x7c08e3eb, 0x833f60ce, ++ 0xbcaeb67b, 0xc9f0f44f, 0x9f0224fb, 0x7d73f630, 0xf5d9facf, 0xbb3e1e89, ++ 0xe7c0893e, 0xb0cfd8af, 0xef2bad9e, 0xe4f87a4f, 0x1f0229fd, 0x8cfd0093, ++ 0x9a7cd9e8, 0xa7c3d53e, 0x7c08d3e9, 0xd19fb012, 0xd8cf9b3d, 0x8cf87ad3, ++ 0x4f811d3d, 0x3ef0012f, 0x34fd67ae, 0xa7c3d69d, 0x3e0474e9, 0x9b9fb1fd, ++ 0xb1aeb67b, 0x19f0f467, 0x9f02267b, 0x02aeb821, 0x1f30f7ca, 0x77b1fb42, ++ 0x0beecfdf, 0xbeecf87a, 0x4dcf8110, 0xed114fd8, 0xfddafb27, 0xc3d0ef8c, ++ 0x04477c67, 0x9fb1633e, 0xcfd67b5b, 0x7c3d0eee, 0xe0447776, 0xb9f08053, ++ 0x1aeb67bd, 0xcf87a9df, 0x9f064ef8, 0x266a4791, 0xd5396839, 0x36916e85, ++ 0xf1eed099, 0x3a2f3408, 0xba745e59, 0xa225d809, 0x56906f6a, 0xdbdb488f, ++ 0x3ee526b6, 0x4776b44e, 0x975874e1, 0x5a635a9d, 0x6c7123bb, 0x49cecebc, ++ 0xf2eb24f2, 0x74335329, 0x59bd53f5, 0xb3def2ba, 0xf795d06f, 0xf2eae5f1, ++ 0xebc6cb7d, 0x29aff7ea, 0x2e07e5d4, 0x3f574dbf, 0xcba19953, 0xaefdaf67, ++ 0xbae0feae, 0xd7e57407, 0x95d7286d, 0xaa581f5f, 0xff58dfcb, 0x61fd5d7d, ++ 0xe5742b0d, 0xae3d3537, 0xfc111f2b, 0xf23f2e99, 0xfaba33e0, 0xd05f5ba3, ++ 0xfe398f95, 0x5c7cae8a, 0x3f2ebb68, 0x836eece1, 0x9e73679d, 0x45e791be, ++ 0xecc27ba0, 0xb4663efe, 0x337682f7, 0x3619cde6, 0xd9f7e3b4, 0x28a75d4b, ++ 0xce6fcd7e, 0xf8a2f577, 0xaa129c05, 0xca320bd7, 0xefd10bae, 0x5df78c8f, ++ 0x1fdfa4e7, 0x726efb31, 0x294fb0c6, 0x1d24083d, 0x52099752, 0x991af963, ++ 0xdf6163d1, 0x68da43ab, 0x78536afb, 0xf7cd1248, 0x00360b13, 0x98273efd, ++ 0x45e34e90, 0xe2f50352, 0x05f7042d, 0x5ef3326b, 0xbaf43454, 0x43e53fb6, ++ 0x5aefda21, 0x760e97d9, 0x87b50bc6, 0x5643b015, 0xcaeba7f7, 0xe145e420, ++ 0x44195070, 0x4d2ff7db, 0x2cfed1f7, 0x6ba76a66, 0xf1d337c7, 0x7afc7073, ++ 0x6eb5ff18, 0x8d64b7c6, 0x1d6f8dd5, 0xdf1ba650, 0x3be3a66a, 0xfb503da9, ++ 0x229f1f01, 0x3b213c61, 0x7c700f84, 0x1c3280cb, 0xee998d7f, 0xc7e3b457, ++ 0x026fc647, 0xe30bd97e, 0xfeb18e8f, 0xf5faf1ac, 0xafd7280f, 0xffd6ccdf, ++ 0x1f1b6d66, 0xdfd71e3f, 0xf5b1b422, 0xeb67280f, 0x237eb0b7, 0xf0223be3, ++ 0x7feb083f, 0x67f5bbb7, 0x3fd7ebe7, 0x7ebf42b0, 0xbdff1b0b, 0x7c7c73da, ++ 0x07ff8e1b, 0xff5b1ce1, 0xdf1c0ac0, 0x81b9f16c, 0xe37dcc7e, 0x7c74026b, ++ 0xa60a8fd2, 0x742e40de, 0x2687481c, 0xe426a253, 0xce164227, 0x467891e3, ++ 0x29e2576f, 0x51bca1bd, 0x50093bf0, 0xf74796c9, 0x97d69c5d, 0x83302d6c, ++ 0xba72c25c, 0xa7c8595f, 0x4449a0ba, 0x594f26fa, 0x7ce98302, 0x05449a3b, ++ 0xba9e0bf2, 0xaff20039, 0xf7ee42da, 0x04893b42, 0x3fa7fbe1, 0x7682f61f, ++ 0x6174c65d, 0xa43a7c9d, 0x3ec8b7e1, 0xad0c90aa, 0x022bf3a1, 0xcd1d1822, ++ 0x20fba09f, 0x1f17f742, 0xa1067dd1, 0x66527924, 0xf7427de3, 0xd10f904b, ++ 0x139412fd, 0x88ed8b52, 0x107f79e2, 0xa897bf9d, 0xf3ae0f3f, 0xda29641e, ++ 0xf7f8c49f, 0x00213ac4, 0x797fb8f8, 0x747e0502, 0x8a4a253e, 0x87d74f2e, ++ 0x0ab7c3f5, 0xec041781, 0x99f007c3, 0x3023fbce, 0xed9f9a5f, 0x518e6d64, ++ 0x28a1f7f4, 0x2fb6bf98, 0x9fb445c5, 0xee4788bb, 0x5ccfdb4d, 0x13132256, ++ 0x7fd0b970, 0x7ccfd029, 0x01196e99, 0xc92a4a7e, 0xe741c4e1, 0xeb275dfb, ++ 0x3e47ba7f, 0x67ccd215, 0x78f56cb6, 0x97667ce9, 0xbbff3888, 0xffcbeaa6, ++ 0x63c137b8, 0xb5d34e1a, 0x999c71eb, 0x3df97d5e, 0x39f9f5b3, 0xea9e7d3e, ++ 0xdef4193d, 0xefc665bd, 0x9d742c14, 0xa5702373, 0xbcf3a513, 0xbee1c38f, ++ 0xe1d1591a, 0x6aadb615, 0x7c143839, 0xed85d704, 0xeff5aec5, 0x97cfae5f, ++ 0xfcfcfa28, 0x39fe86b5, 0xf8e69cdd, 0x41f4013f, 0x1f4033d3, 0x38a79e14, ++ 0xaae5447d, 0x45663e9e, 0x43e8c196, 0x8969c75d, 0x46f4e0a1, 0xeb0b1f46, ++ 0x43d36212, 0x3c1e8449, 0xe952fa5a, 0x87a71e61, 0x2c3d398f, 0xaba7a0da, ++ 0x2ab02439, 0x77bfb69d, 0xd3c43edd, 0xd184a151, 0x7a540fc3, 0xc1e8e908, ++ 0x88c1e9c7, 0x1e9c79bf, 0xd18f7de6, 0x219f1183, 0x0da10f4e, 0xd5926597, ++ 0x0f14af15, 0x83c53cba, 0x334eef01, 0x47c503d0, 0x20787a4c, 0x70ba6eb2, ++ 0xcbcf9f9a, 0xd38be0ba, 0x01679603, 0x09c209d8, 0xad7767db, 0x2e84e54f, ++ 0x6c4368bf, 0x153757fc, 0xccd29ca4, 0xd6e1b2ab, 0x7a9a5394, 0xeba7ea4b, ++ 0x73038bf2, 0x6d17f574, 0x2f95d128, 0x2bac5bac, 0x41f6bf9f, 0xf944be5d, ++ 0xfdfeae9e, 0xe5756bcb, 0xa63cd5f7, 0xecb7bf2b, 0x8e7e5d49, 0xfaba97ef, ++ 0xa4deccf7, 0x7de99f2b, 0xd77e5759, 0xfcba6dd4, 0xbaebcf74, 0xd7bda6fa, ++ 0x98f409df, 0x6024547f, 0xbbf29c7f, 0xfb4fee90, 0xd67a6287, 0x38be46ef, ++ 0xe98b1fef, 0xf596a6a1, 0xcf956813, 0x0913b3c2, 0x24a59fd3, 0x2b2d9089, ++ 0xf36bb5bc, 0xd4139f41, 0x98af2fbb, 0xa3f4ab55, 0x42e4c0d2, 0x306f1738, ++ 0x4248e093, 0x7c4a5004, 0x2d18b0fc, 0xf2d10fcf, 0x8bcbee94, 0xcb314837, ++ 0xcc5243f3, 0x567fab7e, 0xc319d032, 0x67e5133f, 0xa3ec17d2, 0x1b9f6e4e, ++ 0xe2042bcb, 0x64277ed5, 0x45fff205, 0xcc2b9fae, 0x6c544e4c, 0x1c4853ef, ++ 0xa90e0f90, 0x1af1aaf9, 0x06f57328, 0xf1d6c8fa, 0x370da2f1, 0x013ce4ea, ++ 0xd02a6def, 0xf7dd48d9, 0x7413f525, 0x89f7daed, 0x902aef38, 0x7d40e321, ++ 0xa04d5b7a, 0x032d8397, 0xf3061aee, 0x81361cf4, 0x454a6abc, 0x3fddb1fb, ++ 0x0494e535, 0x7a62f478, 0xd31b3fd6, 0xa61f7ed3, 0x9865fca7, 0x60d7f09e, ++ 0xc72ff21a, 0x82bf13f4, 0xb5fe47e9, 0x5fd1fe98, 0xff71e987, 0xfa8f4c06, ++ 0xf11e9803, 0x9efa63d7, 0x56d301bf, 0x1da6137f, 0x2aa60f7e, 0x30f0a9bf, ++ 0xae59ddd2, 0xfd03cfa7, 0x5d9d057d, 0xed4bfd36, 0x3a517eda, 0x8fc57cfb, ++ 0x68fc956a, 0x2c1bc5bf, 0x74d24e9c, 0x40bff0f4, 0x7a068c87, 0x897a70b1, ++ 0x41bc5e5d, 0xfcf2cafe, 0xffb31c90, 0x7bfe17ea, 0x89b46de8, 0x94dfa3d9, ++ 0xd4f4a2de, 0xd94f40d7, 0x0ca7a2d7, 0x9e947471, 0x4c9c9b46, 0x7a7a71ff, ++ 0x6311d602, 0x180b71ff, 0xbb1aa975, 0xfcc093ce, 0x81dcfcd9, 0x9fccb45a, ++ 0x495ec7cd, 0xfda2b6eb, 0x780a1817, 0x6ff434be, 0x7f5fc043, 0x945538e9, ++ 0xcfafdd99, 0xc3dd2f48, 0xa0fb83dd, 0xa25500d2, 0xc796bb23, 0xc6b833c5, ++ 0x9254c899, 0x8363c84b, 0x903f725f, 0x24897983, 0x7b80fb43, 0xbf463dba, ++ 0xf806a6d4, 0x2bae0b5e, 0x438657ed, 0xf99fa77f, 0xa3a41e7b, 0x8eaecc4d, ++ 0xbed1116f, 0xdd17c127, 0x3e88df00, 0xc1d3b8b2, 0x6c1e1e0f, 0x107da276, ++ 0xa7e1e9b0, 0x145e7cd0, 0x18518f7e, 0xafbea2b5, 0x0df8474b, 0x4fa432ba, ++ 0x2d77e00f, 0x782d7f39, 0xf8c8103e, 0xb5e7816f, 0xe4b5e3e4, 0x5eb8f122, ++ 0xefeba26b, 0xf72c3bdc, 0xc1c81771, 0xeb9fb62c, 0xf9eade06, 0x2b3e7195, ++ 0xd16be944, 0x4a9a6771, 0x0803adc7, 0xf024e71d, 0xa97f6d0b, 0xbf263af1, ++ 0xa76fbb54, 0xbc13d025, 0xf7d4c85e, 0xbfa1b0f7, 0x745f074b, 0x696b7ec0, ++ 0x2a79c9ba, 0xb4d41e06, 0x69d321b2, 0x4d9fdad3, 0x3aa5fcfa, 0xda036a61, ++ 0xbbc4ae89, 0x709e8187, 0x020d4f3a, 0xa98e9db9, 0x74d2cfda, 0x9514f3b3, ++ 0xb3ebe77b, 0x2f3ed913, 0xd6c1e4c0, 0xe7179424, 0xffac56fd, 0xbba7cf6d, ++ 0x10f9d47e, 0x5a4e48d2, 0xb2d31e41, 0x77ebeeec, 0x5fd2cf4b, 0x24c7e0cc, ++ 0xb015f2cd, 0xfff4ad0f, 0x13d6412f, 0xbf6af309, 0x62a20dd5, 0x6fbe09b9, ++ 0xdb478dd5, 0xd633d4b9, 0x8abeb32f, 0x5a72246f, 0x2faa5ba5, 0x308f83f6, ++ 0xce37e815, 0x933fb7a9, 0xa6eaf974, 0x3d9d4e3e, 0xf2a0ff0a, 0x1208d497, ++ 0x27054fd0, 0xb6c94e9f, 0x7bf3a056, 0x40849c1e, 0x57ab02b7, 0x7d990d69, ++ 0x6657382e, 0x7e6eeb78, 0x25d37f14, 0xd665f24a, 0x2d873c3a, 0x327eb86b, ++ 0x8d0b99e8, 0x6fc0d32b, 0xf4bc44b0, 0xfb463788, 0x8fde414f, 0xc394be06, ++ 0xd39efb7a, 0xaafda107, 0x4a2fd1df, 0xf935a76c, 0xc7f31376, 0xc2bdfb18, ++ 0xe0b5c8f5, 0xf0f5b553, 0x8c13b014, 0xba6aaa70, 0x5ca1f668, 0x45e5ffa4, ++ 0xefc2a4e1, 0x057bd179, 0x7d795bf4, 0xce2dfa1b, 0x1f90caca, 0xecbc857c, ++ 0xfa5b3eba, 0xbacd04e9, 0xe30ad214, 0x0f96303c, 0x7cf75c44, 0xb9f8e548, ++ 0xe404c9df, 0x6b4ab910, 0x9b01e669, 0x745e535a, 0xe340f3bf, 0xf7806292, ++ 0x51efd839, 0x7880b9b9, 0x5207881d, 0x9bfb0797, 0x1534c40b, 0xbc8174e0, ++ 0xc1a918e7, 0x46648643, 0xcffdd338, 0xe8fced09, 0xa79747fe, 0xbe5d1ffb, ++ 0x8348cc94, 0xa7d28278, 0x70101264, 0x78f2ba7d, 0x2efd89c9, 0xc1ab3522, ++ 0x86fd51ae, 0xd489380f, 0xf2afce97, 0x95e6cfd7, 0x4a6479d0, 0xcf513ecc, ++ 0xb32717c3, 0x6c3797f9, 0xf9687b32, 0xb391c6c9, 0xeda684a8, 0x3e21ab03, ++ 0xb829d940, 0xc2bab8b7, 0xdfceebf7, 0x5ed55f38, 0xcf2e72ea, 0x2f5951e7, ++ 0xe8310278, 0xd18926ec, 0x260faa99, 0xfeab75f2, 0xfc8669a3, 0xf8d7903d, ++ 0xca1be69b, 0xf73f31bf, 0x7e7e3a22, 0x934df45e, 0xc2ff1952, 0xc29058fe, ++ 0xb8dfcf48, 0xfd2ef4ff, 0xfe8d23df, 0xa7effb16, 0xffda33e7, 0xfe756ffc, ++ 0xbfccba83, 0x95ff563a, 0x97757ebf, 0xf979e542, 0x20ee7eaf, 0x2738ced4, ++ 0x29b9a5d5, 0xacb62bfe, 0x9c1d0072, 0xd0071495, 0x3880b9f3, 0x9e431035, ++ 0x2e04916d, 0x01363cb7, 0x4ff09bfc, 0x57f9ffda, 0xf403b89e, 0xb22d95f7, ++ 0xf596fd13, 0xf285a096, 0xe2e3556b, 0xf31c3262, 0xe6bf2c6d, 0x26f908a2, ++ 0xff967d3d, 0x20d3cffb, 0x4a52858e, 0xe7fa135f, 0xa81fb883, 0x14e9fcda, ++ 0x24d5efd0, 0x6c667c8c, 0x917fe307, 0xc4a7fa8c, 0x1cb5d89c, 0xd069211d, ++ 0x1baafd9e, 0x3a28b89f, 0xf4215fe0, 0x97eb18bb, 0x69fefb71, 0xe50bdec9, ++ 0x063218d7, 0x0f0a97e4, 0xfdf66012, 0x317f97ca, 0xa7ce8dbc, 0x1ceff37d, ++ 0x2a4e0682, 0x986a5d9f, 0x576efcff, 0x83b2f2f7, 0x8ed6a1f2, 0xab81f554, ++ 0x9a4bef89, 0x07215a59, 0x5ca8131d, 0xbb24d8a8, 0xe2b9fa15, 0x7a5f17d5, ++ 0x1fc5fc06, 0x6983dc58, 0x3d5e4bff, 0xcd3c7470, 0xf726d92f, 0xb0cb662a, ++ 0xbc516909, 0x97ffd354, 0x50f146e7, 0xd980e3be, 0xff7d8c35, 0x1f147261, ++ 0x33edb64b, 0xe15d6193, 0x9f61a931, 0x818b6439, 0x29b68697, 0x7cad6760, ++ 0xb83373f9, 0x15edced0, 0x18ccef48, 0x0074dcf0, 0x138030ed, 0x29e391e2, ++ 0xfd433782, 0x90178a6a, 0x8c9e2ae7, 0x3cb9cbe5, 0x395cfe81, 0xedafcf48, ++ 0xfd97e3a6, 0xf586e2d1, 0x90f6bd97, 0x4671d603, 0xfd7461aa, 0x0f34aaec, ++ 0x564cb71d, 0xb2989cd2, 0x3dcf65ef, 0xe8b6f48c, 0xcc69c3f0, 0x63e9e80f, ++ 0xf4a4dd42, 0xdc2df581, 0x57d71338, 0x77487c4a, 0x5e8acf65, 0x499f8f90, ++ 0x18b6ea64, 0x6657d17c, 0x0bccf272, 0xeba590d4, 0x6ffb033b, 0x89efe790, ++ 0xc846bf18, 0x7c67e883, 0x5a85af98, 0xccff9868, 0x4974f0ca, 0x4b397132, ++ 0xbd2d75ad, 0x0ad35e6e, 0xdfdf39f8, 0xb3ce1bd3, 0x70a489aa, 0xd25f0878, ++ 0x45c3c57e, 0x887e19bd, 0xede3ca4b, 0x09359da8, 0x56fd43be, 0x5c3713d9, ++ 0x997c8ed7, 0x197f1d19, 0x3bce9f1f, 0x33a3ec1e, 0xfdedb169, 0x0f55645b, ++ 0xa1ae3d50, 0x337f0d2f, 0x18fcdf7e, 0xdf956fe3, 0x42a7d303, 0x308e5ff9, ++ 0xa07681fe, 0x82bce91f, 0xdf7cb1bd, 0x03ca02dd, 0xe2c6090b, 0xe732cdeb, ++ 0x4ab97d6b, 0x92de7427, 0x17a1a890, 0xe1193fe8, 0xe953768f, 0x469db453, ++ 0x78c3565e, 0xa9fdae8e, 0xf388bb7c, 0xe7ac9a7f, 0xf191b27f, 0xabf6f77d, ++ 0x725efcc2, 0x8067a5e0, 0x2a7f295f, 0xd957e02e, 0xf3feeb0b, 0xdfa396d6, ++ 0xe7fa7ca5, 0xf54f9506, 0xa7c8d3f2, 0x261fdb65, 0x3e469f40, 0x1abf73fd, ++ 0xe94f9312, 0xda7c98f7, 0x2a3ff42f, 0x7df8553f, 0x553f00c7, 0x4707761e, ++ 0x50fc3ca3, 0x8794c572, 0xe48477f4, 0x953fa575, 0x2b7a54ee, 0x81ca8fff, ++ 0x74227720, 0x845dd2a9, 0x33ba552e, 0x3f0f57ae, 0x2655b963, 0xebef6788, ++ 0x2b57ee32, 0x261c599a, 0xdf56f76d, 0x0f270851, 0xf75231aa, 0xda5edf56, ++ 0x6f90c07c, 0x18f7d430, 0x7d435ef2, 0xa35f219f, 0xd4d15fab, 0xff882662, ++ 0xb89eaea0, 0x327219fc, 0x06bd1625, 0x8dd5be10, 0xd00acd17, 0xed8c2d85, ++ 0x814415e5, 0x1ef0beb8, 0x9de1f711, 0xc1abc614, 0x3335b05f, 0xb1b950a0, ++ 0xf7ed8e2a, 0xd5e6a9c3, 0x9d3ae720, 0xe4324761, 0xdbfd98e3, 0x923b0de9, ++ 0x5b647634, 0x3a7288b3, 0x63532014, 0x06a863ed, 0x48867841, 0x5cece577, ++ 0x0db448a9, 0x9b7e0e58, 0xae0dd13a, 0xf7b50582, 0xa75ce038, 0xcefb39b3, ++ 0xc2fbf4d9, 0x56188adf, 0x18ef19d2, 0x8a22f30e, 0xd9a3ea47, 0xca259c3f, ++ 0x3d74f9d3, 0x3ed99bf3, 0x833ac162, 0x21d641fd, 0x96da94fd, 0x527e4199, ++ 0xfe84ffbb, 0x41f1843c, 0x6cafef39, 0x6d5cbea3, 0xfb8ef14f, 0xfacdf2e5, ++ 0x6fdf1f72, 0x62f9526e, 0xf7c11904, 0xc1cfcc7b, 0x989170e5, 0x0a6ce773, ++ 0x2283ceff, 0xa5fcd0b1, 0x7fe11166, 0x0010ab69, 0x5251157f, 0x48aabf91, ++ 0x0a9fe518, 0x1fe076a7, 0xa9f2f773, 0x79c7e77d, 0xd93a003f, 0x7ff0e1f5, ++ 0xaefb69a3, 0x01bc860f, 0x1b1f5ff9, 0x5ae921f0, 0x38ded27f, 0xdcef573c, ++ 0xeefa476b, 0x80cef3dc, 0x75fe401f, 0xd9e61b8b, 0xe1f3f7b9, 0x2b9d2f40, ++ 0xdf20652c, 0x7f33fb3a, 0x9f3dcae7, 0x3ea10f0f, 0x76f1147d, 0xaffb6648, ++ 0xff7fcd4b, 0x2905e844, 0x09d8155d, 0x7f90137b, 0x61c777aa, 0x9ee7753c, ++ 0xb67cf3cf, 0x553d6f6f, 0xd3a28e3c, 0x876f664e, 0x38b125f9, 0xc637ea81, ++ 0xc74b58bd, 0x67dc6caf, 0x27cb4f9e, 0xc31fe6fd, 0x6e766e41, 0x874ff667, ++ 0xe20e7a1c, 0x1fc98e04, 0xbe2990ac, 0x3289803a, 0x9cc87908, 0xa4f80931, ++ 0x81fe5c2b, 0xc29ea7fe, 0x1affe3a3, 0x261e0878, 0xab01ecdf, 0xebfeeb00, ++ 0xdfa21f27, 0xa97482d0, 0x0dcff7ae, 0x5c9f68b5, 0xb376dd6b, 0xfee7f999, ++ 0x10b7599f, 0x73bac9ec, 0xbdd7c9fe, 0xfce1765d, 0x95d07c8c, 0x823cf7ce, ++ 0x6eed57f9, 0xe90f6f9c, 0x7c9ff8bd, 0xef1b5ffd, 0x1dde29db, 0x92f75ed7, ++ 0x7775f27f, 0xcedff78f, 0xe27778e3, 0xfcdf99bd, 0x75f7e703, 0xe613dce5, ++ 0xd7396e7f, 0x3b55fadd, 0xb6f262de, 0xcdf9d016, 0x30767526, 0x5ea4e62c, ++ 0x89a1043a, 0xe97ffe96, 0x0d95f305, 0xda6a91e7, 0x11fe666c, 0xe9c1ce19, ++ 0xc0a664b8, 0xdf6c7ff7, 0x1fb70774, 0x8a57e8ee, 0x1e1deb76, 0xc913d766, ++ 0x05182deb, 0xdc0b7871, 0xb9250fe8, 0x9f907dc7, 0xebcf3379, 0x0aef8ff7, ++ 0xbb5023c4, 0x53018efd, 0x7b1d820f, 0x68293f67, 0xa41b6961, 0xf7f83bef, ++ 0xce7dfab1, 0x7f3e9f1c, 0x7e7d6ccf, 0x166fef26, 0xfc745718, 0x00215e59, ++ 0xffb94ffe, 0x0fe0a953, 0x44ca1795, 0xa71e2010, 0x27ec1566, 0xedf57a66, ++ 0x57bec037, 0x67ec2fe3, 0x0ba010f3, 0x93a1db99, 0xef966e6d, 0x6e7825e7, ++ 0xa950edc4, 0x39288797, 0xc5ddf8d1, 0x3834df56, 0x150eb0bf, 0xae778e10, ++ 0x590e5113, 0x979c0473, 0xf18cac77, 0xbc9a9fa0, 0xe29f8079, 0xbeaa6391, ++ 0x06e1a6cf, 0x70e62d38, 0x6835252e, 0x5fab9127, 0x079f997e, 0x768262fe, ++ 0x210f62d6, 0x40fdd3b7, 0x8c10be69, 0x48bcfca7, 0x2e624a22, 0x720551f8, ++ 0xd547e742, 0x9df7e1e7, 0xd73f68b4, 0x1d1ddfaa, 0x9fe9db7f, 0x189cdf28, ++ 0x3f6ded44, 0xcc23c18f, 0xdbeea81f, 0x70666fee, 0x0210aeac, 0x418f4859, ++ 0x3f39abd9, 0xfb61631a, 0x70fd3ffb, 0xc163f224, 0x644b0ebf, 0x6841c9fb, ++ 0x7eab569f, 0x0895c50a, 0xcd4b93fe, 0x6d9cfcd9, 0x8317c392, 0xfdf30e0f, ++ 0x4e201fdc, 0x939da68c, 0xf6113a85, 0x7e8c240b, 0x1c726542, 0x8e2312d9, ++ 0xc4c5b7b1, 0xb8358bfd, 0x989f84bf, 0xbf647807, 0x6269b445, 0xeb6f06b2, ++ 0x0d273f6e, 0xf8078aef, 0x279cd09d, 0x0be157fd, 0xeb8047fb, 0x14d0b8e1, ++ 0x5ef58c6f, 0xfc57e1cf, 0x3ef15fe6, 0x4ce68cde, 0x6332e019, 0x7f3ba8b2, ++ 0xfb70b4cd, 0x0919247f, 0xf37e2af3, 0xc038c756, 0x0dd141cb, 0x9baaeff7, ++ 0x317d9a2f, 0xf08cf5ce, 0xfcf1fe84, 0x02977640, 0x24fe4f3c, 0xecfec08e, ++ 0x945e7e1d, 0x39eff103, 0x80f02ae8, 0xc2d72abf, 0x2c6b4bfc, 0x5def844e, ++ 0x2a7205c5, 0xd1a7371d, 0xc48e0239, 0x35fd7832, 0x4346eca0, 0xa76b0630, ++ 0x60a8cbd6, 0xceccdaf5, 0xdfeb58aa, 0x79f8156b, 0xb191fb88, 0xde1f3fc2, ++ 0x1ed5fe0a, 0x343d042c, 0x1bafdd59, 0x7f209ae9, 0x042a9a5c, 0xbec04f40, ++ 0xecc5f30b, 0x263be7be, 0x60ccae56, 0x7ba55cf2, 0xe7ef9c23, 0xef8eabf4, ++ 0xc05f70e7, 0xb38543e9, 0x7ce35f0a, 0x5e54fad5, 0x39fad44d, 0xf11a6cee, ++ 0xaad1e81a, 0xa269c166, 0x2149555d, 0x7561f033, 0xf83293d3, 0x58b8e7f1, ++ 0x0c8f54bf, 0xaf0b9ed7, 0x9f3848b1, 0xf309dc96, 0xaf2e4e80, 0x6d0cf6a3, ++ 0xd17059ef, 0x1df87201, 0x70f7fb93, 0x5779562f, 0x42be5b24, 0x77e87d5e, ++ 0xd25936de, 0xf3899bf6, 0x40a2abbc, 0xbdccb706, 0xdee4fb15, 0x635a7a1a, ++ 0xf572c649, 0x2b85467b, 0xf1d3be17, 0x4fca1e70, 0xfbe2042d, 0xf15a1a73, ++ 0x35bde19e, 0xcb0e8c49, 0x3199f61a, 0xd5f5899f, 0x8c71d4f1, 0xb17774fc, ++ 0xfe747e3e, 0x803f50a4, 0xb825b14b, 0x4e831dcc, 0xfc46b06f, 0x4f4f5f98, ++ 0x0edd2878, 0x4f48ffff, 0x44f5532c, 0xd595e308, 0xeaba97f6, 0xf4b1de89, ++ 0x575ad2c4, 0xd2c3c06f, 0x81bdd93d, 0xb6fe9649, 0x9e962d28, 0xcecfdf78, ++ 0xfbf18f23, 0x53779db9, 0x4693713d, 0x871ddc4f, 0xf76c6274, 0xd727ca91, ++ 0xde2a13d2, 0xcde587fe, 0x6227a0fb, 0x41a777f0, 0x2e6acc4f, 0xeb313d41, ++ 0xbf7f516e, 0xdc04f41a, 0x4f56e98b, 0xc1cda414, 0x884eecbc, 0x73ef3f41, ++ 0x8f18fa3b, 0x407186d3, 0x3ab60c5f, 0xdea37c71, 0xbfae4ee8, 0xfeb953dd, ++ 0xaace087f, 0x933a5f5c, 0x4aeff3dd, 0x79e90487, 0xd72a1ce9, 0x2647a005, ++ 0xc7de97d7, 0x390669fd, 0x3b3905eb, 0x59672b4a, 0xd31f2afb, 0x994dd50b, ++ 0xcb4b98bf, 0xbb275bbf, 0x77feb4ad, 0x4f3772a3, 0x5b07772b, 0x17547c59, ++ 0xe4c65bb9, 0x91e6e5ee, 0xb7753f68, 0xbcb98fbe, 0x906cf2a5, 0xcc7d063b, ++ 0xbba09b9e, 0xc4727547, 0x00ece67f, 0xc447797e, 0xb94fc173, 0xc468701d, ++ 0x7b028e7f, 0xe995857a, 0x3e383b81, 0xb6e4fc3b, 0x4c0e54c9, 0xe9ecc05a, ++ 0xc222adca, 0xf191aaaf, 0xf8a0d57f, 0xa7e68b80, 0xcf15fee4, 0x61ec96f7, ++ 0x05747be7, 0xfc1a05c5, 0xb427792f, 0x4bcdfc1a, 0x3e780936, 0x00e87109, ++ 0x9e1c45cf, 0xb825eea5, 0x27c631cf, 0x4ad4fea8, 0xf3716f5e, 0x1abbf426, ++ 0x072a16e3, 0xf60e76dd, 0x8616c523, 0x421de287, 0x9c265360, 0xb9ea1b93, ++ 0x8973c31f, 0x79c306ca, 0x42ef5f22, 0x03b39831, 0x17bf63f6, 0x5cf4b1dd, ++ 0x652e11b5, 0x1cb845ff, 0xf51970a6, 0xee970fdf, 0x7bed40e0, 0xe11b43f4, ++ 0xdb95a0f1, 0x1464b99f, 0x26a7e1f0, 0xe515ca0f, 0x4ee3116d, 0x58393c16, ++ 0x9f83aef7, 0x4c77cbeb, 0xa07dd5be, 0x4f8b155e, 0xdb71b459, 0x9f9a3481, ++ 0x804640db, 0x06d17b1b, 0xe88e1ebd, 0xea1746fd, 0xdb35b9f5, 0x5c738804, ++ 0x956defc8, 0xf7c49e05, 0x4e5bee30, 0x3fad3cf5, 0x83e2d73f, 0x71c3d5f3, ++ 0x2a9b9461, 0xf9c6bedd, 0xcfc72b68, 0x64f08cc9, 0x824d4fd4, 0x1831f913, ++ 0xc515f4c7, 0xd1d3bc13, 0x29f3ee32, 0x7fcc2f1c, 0x58f0c4d1, 0xfc06f14d, ++ 0xe799a53c, 0x781d99eb, 0x106f9aaf, 0xe4012e02, 0xbd993eea, 0x149021fb, ++ 0xa3412381, 0xaedce11f, 0xe7834d20, 0xfe8c6d3d, 0xfc6e08b7, 0x7dffa010, ++ 0x4b773c13, 0xe98eccf7, 0x70abbd29, 0xf5cacd7a, 0xe1f3c707, 0x91e2d6b8, ++ 0xb823ae78, 0xe693fdf1, 0x388f3c24, 0xf1dec755, 0x3678e668, 0x3bec05f2, ++ 0x4c8aefb4, 0x9c438987, 0x8c38d4ea, 0xb371c3f3, 0x95a65d98, 0x707b914f, ++ 0x71bafd3c, 0x15a4d52d, 0x3c68b1ed, 0x05826f9a, 0x055385f6, 0x16271f49, ++ 0x16ff3a46, 0x4962bffa, 0x927fbeed, 0xd3f8c4ee, 0x77ea9c87, 0xc35fbb27, ++ 0xf3fd2df3, 0xf0a5cd8e, 0x7456bcbd, 0x1eea16c3, 0x3e68eb93, 0x65c79bc8, ++ 0xf972fc02, 0x7a61ec90, 0x4ef50120, 0xf1273bc9, 0x8b09525e, 0x3f25226d, ++ 0x24e5fa62, 0xa91fcf9f, 0x2f80f6de, 0x868c3485, 0x76ee4cf7, 0x81722bef, ++ 0xe1d465bf, 0x769e7055, 0xd1e724d7, 0xc7cf80a3, 0x27367bd8, 0x7dc24ed6, ++ 0x0a0f43da, 0x29c76fc8, 0xccfda0de, 0x1e8f33bb, 0xb7dee3a5, 0xc7cf1536, ++ 0x67527ae6, 0xdcd979c1, 0x45dba243, 0xd3bfcdeb, 0xb2f3836e, 0xe2454369, ++ 0x3ee7c0d3, 0x9dfe8ad2, 0xce0f35b9, 0x51977984, 0x4266287d, 0x37a8b87a, ++ 0xd80a37e4, 0x99f15abe, 0xeb5ddee1, 0x51e68b86, 0x5a52fc74, 0xbd5ec00f, ++ 0xdeabd591, 0x8421b82c, 0x49f9b4b7, 0x9ba59794, 0xa4307c05, 0x56bfda95, ++ 0x4ac06fd6, 0x48dd6dfb, 0x22fcd3db, 0x6efd0f68, 0xe7059a4e, 0x9e74d560, ++ 0x2d6c7ed8, 0xd296779e, 0xb498b476, 0xfb107e6e, 0x2051bc5b, 0x6cabcf70, ++ 0xc74fe66c, 0x64877f42, 0xdb1f9437, 0xcc334bf7, 0xaf1d1e7b, 0xbe7fed0f, ++ 0x7f422a18, 0x27040fdc, 0x1b6323be, 0x84ebf88c, 0x23834305, 0x05cf8cd9, ++ 0x92b7dea2, 0xb30e71b4, 0x749c58e2, 0xd5daf2e9, 0x9290aeb0, 0xba42699a, ++ 0x3d0668ba, 0xdbc28a7e, 0x93d7ed47, 0xd13f1666, 0x87349ca2, 0xa1f47234, ++ 0xbf6c6cb8, 0xcf00a9a0, 0x2f1217e3, 0x6afbc79e, 0xb6d23d99, 0x80202e2a, ++ 0x073b261d, 0x5596f7c0, 0xf1defc16, 0x1d3fd32a, 0x47e843fd, 0x2651b33d, ++ 0xe56d0f70, 0x01a7ecc6, 0xcab6678f, 0xb3e26f48, 0xd17a3cec, 0xd64fccab, ++ 0x7bf591b2, 0xbd999966, 0x34e5048f, 0x7565e8bf, 0x6397abff, 0x9472aea5, ++ 0xd4b94653, 0xa9f0ae25, 0x6c90335a, 0x6cb57917, 0x72abca0a, 0xd08077aa, ++ 0x7eabc8ba, 0xd9cfd1ab, 0x9b133f45, 0x21728faa, 0xb2a4a52e, 0x400dbcff, ++ 0xc0b1f7c7, 0xebe0d6ef, 0xf41cfd9f, 0xc09d856e, 0xf9c92a97, 0x82e8c0b4, ++ 0x6dccbf00, 0xf019f6de, 0x38dcd941, 0x34e9577c, 0x66f801e0, 0x939e0a5d, ++ 0x104a0696, 0xe69c6ade, 0x3a7a0da2, 0x738ffd57, 0x68f1227c, 0x025957f5, ++ 0x1dea68f1, 0x57a511fb, 0x4dfdce3a, 0x804e2042, 0x0f5bdb7c, 0x13bcc28f, ++ 0xdb9cb5e7, 0x48eceb07, 0x77bec7cf, 0xebd01571, 0x040a1fbc, 0xf8a275ec, ++ 0xac3e8356, 0xc0b820da, 0x87e8bb9f, 0xda22fdac, 0xec7de61e, 0x28ae8c97, ++ 0xfe80bb7d, 0xf93e36ab, 0x2cdfd616, 0x63ffa0b8, 0x9ed04a9b, 0x82445328, ++ 0x70db9be5, 0x14f540ff, 0x28b52fc6, 0x7fd01a62, 0x2716a3d5, 0x1d2a4a98, ++ 0xc6d974a9, 0xd58953e3, 0xda2efc3d, 0x9526132e, 0xc51e95da, 0x9f4442d9, ++ 0x2b549d02, 0x5edace8c, 0x3640dd95, 0x764ba6d7, 0xd70cf99f, 0x33b3e2af, ++ 0x8b7dc0a7, 0x023f5445, 0x9c6cb69d, 0xe23b0664, 0x73c0404c, 0x4974aefc, ++ 0x4a3b5a6c, 0x0567cba5, 0x15afaf26, 0xee85dae7, 0xf4aa5d38, 0xf71a8947, ++ 0x64871595, 0x8da8f702, 0x1b93e8f4, 0x419c4166, 0x3d746bc9, 0x5693be74, ++ 0x75ed0f7f, 0x9f348e15, 0x8952f906, 0xfca893c5, 0xb8b12950, 0x3f3dafa3, ++ 0xe293f8c3, 0x107e51ec, 0x904c5c59, 0x5b9ffb8e, 0xbc38c45f, 0xddb4af0b, ++ 0x1bcdf681, 0xfe000e94, 0x8824ed5b, 0xca008ffb, 0xd146f2a1, 0x528a7183, ++ 0xcd2eef30, 0xb38d5dbe, 0x3b2bf258, 0xbb7cbbc2, 0xdb4c5025, 0x393aef97, ++ 0x57bdcf1c, 0x446e3184, 0xfb404579, 0xe1a12898, 0x5ca40f70, 0x461ef162, ++ 0x1c6f60bb, 0xbfb77fdb, 0xec1b309e, 0xbd9ea136, 0x70de5697, 0xf8d16c8f, ++ 0xc9c67775, 0x873c3d6a, 0xe19e2851, 0x4fcc3b9e, 0x1a974efb, 0x32fed1e7, ++ 0x26f2bfa3, 0xf2b9ed19, 0x101d6dfa, 0xdc7e57df, 0xeadcfb82, 0xaf188bfa, ++ 0xaf57e93c, 0xd56b3be2, 0xbe2ea24d, 0x555c4bab, 0x22e788bd, 0x18958d55, ++ 0x78f341f7, 0x10d5523e, 0x5af0be3b, 0x7e4b3ff1, 0x429767b5, 0xc764b841, ++ 0xddf03bbf, 0x0e2dd6b5, 0xff52bfbc, 0x5d8d71d5, 0x1e1aa8e2, 0xaa38cafb, ++ 0x4a0ff0f3, 0xb8e26758, 0xa1c6a71d, 0x46b933d5, 0x8de797e7, 0xd88e27e1, ++ 0xf67eaf5b, 0xb6f9c41c, 0x73f3ff6f, 0xff8adf30, 0x8839f975, 0x7388a0df, ++ 0xfd523d82, 0x2718fbca, 0xe213b6a9, 0xe5e7fef9, 0xd2f8c77f, 0x6e2c0f8e, ++ 0xcf63ade8, 0x6f600199, 0x6bfb6c74, 0x2e8dc41a, 0xfe8453db, 0x273b659c, ++ 0xfc3126f5, 0x740a6a05, 0x7c41e81b, 0x2d5f11ab, 0x67182d8d, 0x1be28172, ++ 0x2e2443e4, 0xc592a1ae, 0x3c78ba19, 0x71d8d6dc, 0xdfe25dc4, 0xf3baef1a, ++ 0x8d8b9066, 0x66b82ecc, 0x8a11dc1c, 0x807a9bc7, 0x718fadbf, 0x7f1b1279, ++ 0x141fe017, 0xf5e3034f, 0x359f7071, 0x19fe7c2e, 0xe94c6b28, 0xd82e0e36, ++ 0x71a9b803, 0x9e71edca, 0xbf81e21b, 0xc607ffb6, 0x8ade021d, 0x3f9f205d, ++ 0xe17e001b, 0xfd1872b3, 0x163de10f, 0xbe572fbc, 0x4ff218e7, 0x18c3cec7, ++ 0xbc784c07, 0xfc890770, 0xf7277c58, 0xb66f54f5, 0x0e39f8b3, 0x73af887f, ++ 0x8f3bf039, 0xac7463a3, 0x1775d7c6, 0x9f125757, 0x60c5dfc5, 0x9b957ff1, ++ 0x6af1e43f, 0x63097c51, 0x5f6d4f01, 0xc2a8af19, 0x187009c1, 0x8d138da3, ++ 0x8918bf1d, 0x02f8e627, 0x8e9c81fc, 0x7cd281c4, 0x0c0b883f, 0x0c48c708, ++ 0x89b1d079, 0xc87697c5, 0xaaa5efb1, 0xe373a371, 0xe81a7c0d, 0xb5e8bc59, ++ 0xe175ffe6, 0x0bbc7b73, 0xa9c235fb, 0x396c6afd, 0xff7ce7ee, 0x541def8d, ++ 0x0d7bc608, 0x7b878e3f, 0x666d8d13, 0xdd42977c, 0xb6f5f13f, 0xfb5a7f73, ++ 0x13c6222b, 0x41686eae, 0x17946e39, 0xc49cfc55, 0xf927df38, 0x989aab7c, ++ 0x6edf689e, 0x3f68d80f, 0x8ebe6fed, 0xb5b55cf4, 0xdf19e30d, 0x0e61dfaa, ++ 0x4197ce69, 0xf334044f, 0xdf6d7f6f, 0xfcdb9470, 0x38e3289d, 0xfdb3c7cf, ++ 0xec737570, 0x5eb7aa71, 0x44b38dd4, 0x6d3b3069, 0xbcef1ed7, 0xfa07b9e4, ++ 0xeccadf3b, 0xe20df3a5, 0x6ef758d4, 0xfccbc456, 0xa58eb41c, 0x7be25f54, ++ 0x3ef67659, 0x4788e896, 0x7d996bfb, 0x5ec4f1ec, 0xbe319a90, 0x8f2d6562, ++ 0x3b91f8c7, 0xd2bdf01d, 0xf9811b7e, 0x6af802ae, 0xd3b2f1f6, 0x936ec047, ++ 0xb4a3bdd3, 0xfcea2ce7, 0x244cbdcd, 0x32ffc1a0, 0xb0ded4fb, 0xd29224ff, ++ 0x4771e60f, 0xe812e7d6, 0xf33f56bf, 0x27ab93df, 0x56f7c107, 0x852079c9, ++ 0x593adbf6, 0xb5eb8370, 0x7407dd2b, 0x3dd363e7, 0x213f77fa, 0x77d61f56, ++ 0x7b426dc9, 0x3a0a6ed0, 0x8f621569, 0x0dc74d6b, 0xa4b88bac, 0xc7b10c34, ++ 0xfdc7f738, 0x41a4bbd6, 0x352eb284, 0x5b9ea14f, 0x9163bdd2, 0xbc325638, ++ 0x0c8e416b, 0xe36af4a2, 0xe5faaaf4, 0xb4dfecec, 0x97be10df, 0x6a439491, ++ 0xd9d77c81, 0xac37687d, 0xd08cefe7, 0x838850df, 0x6ef12648, 0x743c3bed, ++ 0x1dfbdd5c, 0x3e5d5c74, 0xa7cfa3c9, 0xc54e954c, 0x7c292fd2, 0x1b44531e, ++ 0xc8a921c2, 0x8ad7eea4, 0xe745a707, 0xdc4a949d, 0xddbf2841, 0x94e67186, ++ 0x3aed14bd, 0xbcfd366c, 0x7274fce9, 0xa4273122, 0x753cd898, 0x25c49ddf, ++ 0xfa3dfae0, 0xbabe74ef, 0x7954dffc, 0xe4091127, 0x4adacd9d, 0xe92ffc38, ++ 0x74a8fde0, 0xe01a7fa8, 0xb57df087, 0x429ee042, 0x1d075f22, 0x09df575f, ++ 0xbe3601de, 0xcfd21fbe, 0x784fbda9, 0x2d7fd713, 0x0484de09, 0x0379a7ca, ++ 0x3800306b, 0xe0e49d3f, 0x5ee6d7bd, 0x96b29f28, 0x89dc6217, 0x6ae8c750, ++ 0x7c823ad0, 0xe2cc2833, 0xf1a3c85b, 0xac5a8f68, 0x85cb8944, 0x9144527b, ++ 0x00946173, 0x0ad73fe7, 0x5a4aed13, 0xb68d694b, 0x9a170e6b, 0x34245216, ++ 0xdfed1140, 0x80c9e09a, 0xf74f57f1, 0xc0469ba5, 0xed56a7c7, 0x7b5c87ef, ++ 0x4d04783d, 0x0703fac2, 0x40a1666f, 0xc5031ef0, 0xbfd001c8, 0x093c9175, ++ 0xbaed7dc2, 0x63de48f8, 0x2ebef2a5, 0x2687e58b, 0xef055fac, 0x7a24b486, ++ 0xc438c287, 0xcf01bcea, 0xb8c982bb, 0x17e96bfe, 0x37439e75, 0x8fc4a687, ++ 0x78537e62, 0x3db0759f, 0xf51a7f72, 0x9a9b16f0, 0xc23ee20f, 0xe51878db, ++ 0x61c3655a, 0x9e41372c, 0x425303a6, 0x1126fa53, 0x2f13cb72, 0x0f5fa516, ++ 0xe925e3f1, 0xef4eba26, 0x901e2f13, 0xd7a87074, 0xbd3241c1, 0x4bc38064, ++ 0xde0e0b5f, 0x0e109784, 0xa5375d3d, 0x5e013b8b, 0xf84c0ad3, 0xe398d66e, ++ 0xd0aff436, 0x23ea1c5f, 0x6ea6cfde, 0xfbaad7ee, 0x3dcfda11, 0xdb52fa5a, ++ 0x1dd574a9, 0xe71364dd, 0x44bdec0d, 0x4dacfd3d, 0xbfa0f8f0, 0xdd8f0492, ++ 0xc7eb8a9e, 0x7cd3dcfb, 0x91e4f73e, 0x3626ba51, 0x7619c8df, 0xc581ff18, ++ 0xecbf1a09, 0x62a582b4, 0x396f9d16, 0x746a42f0, 0x95cba93d, 0x9d7421b8, ++ 0xc6131ea9, 0xf824b767, 0x3ce813aa, 0x41c3b31c, 0x8630b2b8, 0x620a46f8, ++ 0xf1d42f94, 0xfb61ef56, 0xa625d5f5, 0xde760ac0, 0x517f402b, 0xe81908fa, ++ 0xa3e8cc23, 0xa3e90da9, 0xd18db9aa, 0x216d5347, 0x9b9c17d0, 0x8ebf3ec1, ++ 0xde004784, 0x66f13d57, 0xd29fd491, 0x7578424d, 0x32174a5f, 0xc7151609, ++ 0xc6575c21, 0x9f9f0fc4, 0xf0eeaeba, 0xeb30775b, 0x4fd81c89, 0x79e1321e, ++ 0xb5370a97, 0x2c092bde, 0xdd8e72fe, 0xa8700757, 0x0b7a1b1e, 0xe0fdbf96, ++ 0xe1b7187b, 0x1f633438, 0x4ddc77b4, 0x8e8ae431, 0x0568775b, 0x475c83be, ++ 0x265d01d7, 0x7a02b092, 0x30787bbd, 0x03c089fe, 0x801c9eec, 0xcbf21b47, ++ 0x121efc2b, 0x5fbc3be5, 0xbd81303b, 0x0262f0ff, 0x75f9138b, 0xfcf38882, ++ 0x6bb30275, 0x325d0f52, 0xfaab7ec3, 0x4fd61351, 0xbb473485, 0x3b7947fe, ++ 0x0627cb89, 0x2a9f150f, 0x9a49513d, 0xfc48ef00, 0x90d7c938, 0x3f4b5a30, ++ 0x9a5909c9, 0x3f76d4fe, 0x02f713f5, 0xecc747aa, 0xd021e07f, 0x7e7e94ab, ++ 0x4c376ba2, 0xa9b8038e, 0x633e81f5, 0xdbb687e1, 0x1c60ed0b, 0xedb617b0, ++ 0x7be22a5f, 0x6bc43d08, 0x47ffbc1e, 0x9025e7eb, 0x7db4ed9a, 0x214d225e, ++ 0xbdf3c29f, 0x4b2fbe79, 0x9b723fb3, 0x137dfa04, 0x4d1ebbf7, 0x920171e0, ++ 0xc31986f3, 0xb8eccf20, 0xd478f4fc, 0xc2df2a0b, 0xb7387e5d, 0x75f9f896, ++ 0x04cb3856, 0x58f95378, 0x76829b0a, 0x24b2b4aa, 0x18e20997, 0x75d3f6de, ++ 0x9dcbdd4b, 0xf767aedb, 0xcfdf8d03, 0x637cf9f3, 0x5d2ffafb, 0x079f0dee, ++ 0x435a56f8, 0xf3419d3f, 0xc65fd755, 0x0915c1f3, 0xeabe1355, 0xfce302fd, ++ 0xc67abedf, 0xc761f601, 0xb1a99617, 0x3681ecec, 0xfd078f46, 0x1e5db1b3, ++ 0xf4839f7f, 0x3559e356, 0x8ca110f7, 0xca8865db, 0x768efc2c, 0x045077d6, ++ 0x29153e02, 0x6427da19, 0x44e1f9e2, 0xefc47dc3, 0x2f9f9904, 0x50030c0f, ++ 0xc0ddd712, 0xd982f9c6, 0x1ffa5649, 0xf115339c, 0x25b7b173, 0xed3b4adf, ++ 0xcec26def, 0x6a52f357, 0x2c4f205a, 0xa202ffac, 0xaf2d4f7f, 0x64e4dd77, ++ 0x133137e8, 0xac935bfd, 0x456cf286, 0xb24d3902, 0xb12e3133, 0x33ec6888, ++ 0xeed037a6, 0x02f3a38e, 0x686d3e39, 0x2f327b89, 0x1fff4cbf, 0x4ff72168, ++ 0x6e37ecd7, 0x4f71cd75, 0x752fd9d6, 0xefcbaef8, 0x1fde21fe, 0x5fe2ce2b, ++ 0x0f4e8c6c, 0x386ebdfa, 0xb3c2367f, 0x6a3c25d0, 0xbb857577, 0xb8468e11, ++ 0xc23570ab, 0xf723e0b1, 0x7018e4e4, 0x88a5c232, 0x3d050dd4, 0x08ddc2a6, ++ 0x8cadb797, 0xb1cede2e, 0x6f78fbe0, 0x6f8e0c4b, 0xbd923353, 0xbb41e9c7, ++ 0x03a548b6, 0x495bb30b, 0x49e23b6f, 0xd92773b5, 0x08d9bf99, 0xf470aed7, ++ 0x45a51714, 0xc016f7d7, 0xc133e80b, 0xfd0cc47d, 0xfc460e26, 0xa244e091, ++ 0xd3a0eb8d, 0x270477c0, 0xd2baaeb2, 0xe0866fdb, 0xbf13b37b, 0x45b9dbd0, ++ 0x81ce53cd, 0x7e96e09f, 0x7f828f25, 0x6dd080b4, 0x11e50b86, 0x4c8487e3, ++ 0xc70a53a4, 0xe37a7a13, 0x72b0a6fd, 0x797d570a, 0xe968f136, 0xdc69c8bc, ++ 0x41b9d7f7, 0xafd71bff, 0xe0afd9d2, 0xf0aeb8c3, 0xcaace952, 0x194efdc6, ++ 0xcbd81fa4, 0x951f5fc3, 0x349bf208, 0x4bf4c727, 0x8dee398c, 0x47c7c3f4, ++ 0x2f88163a, 0xfd99ddf2, 0x8763905f, 0xc8d496a8, 0x6fa275b1, 0x1c862da5, ++ 0x66e5e953, 0x899bb78e, 0x4bfc0fb2, 0x2fe91337, 0x6640fd91, 0xd84ffd74, ++ 0x2fa43ef8, 0xfceb0be9, 0xe98b8273, 0xc8cebe45, 0x0979a9ba, 0xf1f3e7e3, ++ 0xbc36adf3, 0x52c241c7, 0x59ee047b, 0x628d6ef8, 0x43ce8e4e, 0x80c9f5e6, ++ 0xb9ecc21a, 0x315ef8b9, 0x32f90b85, 0x808f3a21, 0xddf0904d, 0x0b8f3e16, ++ 0xe20556f5, 0x7d13ded8, 0xf7e06d9b, 0xc70d0e10, 0x21c149f5, 0xe58cffa0, ++ 0x57f69b97, 0x57ad3941, 0xfcf8f58a, 0xffcc8897, 0x0963de10, 0xbdd990bc, ++ 0x1ad94a9d, 0x17ca84f5, 0xf20f70f9, 0x60bbe026, 0x44f7985f, 0xdd347550, ++ 0xf70cb17b, 0xb94d0585, 0xe0738c12, 0xf78c14d2, 0x091e242f, 0xfd235bec, ++ 0x48dae91b, 0x96e831c7, 0x03c22bfb, 0x75f29f60, 0xe3b545e9, 0x44737422, ++ 0xbd2a374f, 0x1df9fa50, 0xa8e74fd0, 0xb3069f4f, 0x97519dfb, 0xa9ff40d3, ++ 0x1ed47a76, 0xf00bbcf1, 0x575eceed, 0x6d0ff4ed, 0x9ea1f7be, 0xa0f3c244, ++ 0x9750d67d, 0xc7dbee09, 0xe1473dd9, 0x5cbf6abb, 0xf641df6b, 0xa5310dd3, ++ 0x0f1c799b, 0xef82260d, 0x054b2af9, 0x91f72f94, 0xdde30cb0, 0xf6eb2357, ++ 0xc2e2f3b7, 0xce00fc9f, 0x43af6b0b, 0x2883e67d, 0xb3db1136, 0x5cd5e3b8, ++ 0x0f0d0eef, 0xbfdeb801, 0xd89edf5c, 0xa2ef74d2, 0x7db0227e, 0x50b8bcff, ++ 0x2dcfdc2a, 0x8df5f451, 0x30ebabe3, 0x576c6bf6, 0x6bf7626d, 0xb76a5de0, ++ 0xdcf86ec6, 0xc8d9ecc6, 0xefe6df7c, 0x9b78501e, 0x7cd39fc0, 0xeecdea3d, ++ 0x66b3e7e0, 0x779a48e4, 0x2c7b42b1, 0x3fbd63b3, 0xc2a38ea2, 0x55692e7b, ++ 0x8337f9e1, 0x7dd994df, 0x300fe63e, 0x9dd4153d, 0xa0e9abc7, 0xfbb464f0, ++ 0x68083506, 0x14345767, 0xecebe698, 0xee1fb67d, 0xbbc3ef62, 0x71bf5018, ++ 0x1bf7b31f, 0x50df716a, 0x3ff6c8d1, 0x3a0ce09b, 0x07244f83, 0x7d9101f7, ++ 0x5549c42d, 0xac83fbc2, 0xdd57083c, 0xfd58ebb3, 0xe60df609, 0xbec106c7, ++ 0xbb2e97d4, 0xcf27fe69, 0xfdd2b6ae, 0x124cead3, 0x69fee847, 0x9d9e4fdc, ++ 0xe52c6eb2, 0x008f64b2, 0xfcd23def, 0x9eb8db6a, 0xfc27a3ef, 0xf46ae364, ++ 0x73782427, 0x6d7d9aed, 0x0831fc77, 0xd8af8e8c, 0x7a24b6cf, 0xfe51d827, ++ 0x1184bf30, 0xaeac97ff, 0xc7bfa044, 0xb6fb3ef8, 0xfee00fe5, 0xabbaee21, ++ 0x2c1e2003, 0x16fde39f, 0xab37b33b, 0xedfdd813, 0x2ddf4587, 0x9be76fd0, ++ 0x1f808757, 0x27a1edf9, 0xccd6df71, 0xe43c87df, 0x493b432f, 0x3b0ce3c5, ++ 0xbb6fb3b3, 0xfb01c5be, 0xff47db8e, 0x5f9def01, 0x697bd890, 0x3acd63ed, ++ 0xad8f773b, 0x5fac0668, 0x44d8294d, 0xa3f9cb90, 0x7d071ff6, 0x887e9ddf, ++ 0x008f7fca, 0x3d5c9ff2, 0x3fe7869c, 0xe01c078d, 0xf7e76cbb, 0xb6342fd8, ++ 0xd3403da4, 0x707f6dca, 0x3e6b7ec0, 0xa905df5f, 0xa9d7df15, 0xbbe229d8, ++ 0xb4dc7410, 0xdcbfc17b, 0x71ef3f38, 0xab558c36, 0xd1ff72ff, 0x9ccbd7d2, ++ 0x87bef87e, 0x6cde0f6a, 0xbf300255, 0xfd115ae6, 0x889337bd, 0x05df139f, ++ 0x7a28d899, 0xed5d1ce2, 0x55d9efc3, 0xc61a72bf, 0xb2732d33, 0xcbe3ba71, ++ 0x49922ffc, 0x407ef340, 0x611414be, 0xa45ff9fe, 0xf06a7811, 0xf5acc1c2, ++ 0x226f80c5, 0xb74307bb, 0xf68fd912, 0xa23f3f27, 0x1ef0fdbf, 0xf99e5ef4, ++ 0xbbe5e34d, 0x3a912026, 0x0051bd1f, 0x8bd7cc3b, 0x9c990739, 0x89c4ed57, ++ 0xa3fde85f, 0xb0b53b46, 0x7da3c479, 0xfd9bc209, 0x59b080bd, 0xf6f4b3b5, ++ 0x4c4a786b, 0x279095bb, 0x77725e91, 0xf7834f66, 0x6b7f7275, 0x73b8c272, ++ 0x3757bd38, 0x5ff7c65e, 0x167048aa, 0x8a355794, 0x788120ce, 0x023751a1, ++ 0x5f7aa8bf, 0xd5d34b85, 0xf070eb16, 0x3a2ebdaf, 0xe6bd4057, 0x470e90cf, ++ 0xea2afefe, 0x19668ea5, 0xdea93fdf, 0xbe63a9f3, 0x68effec6, 0x74a2ef66, ++ 0x7fd49f36, 0x11b94a6f, 0xb1336dda, 0xb7feed7d, 0xf20096fe, 0x2f5737e6, ++ 0x5a7ee0a5, 0xfb06fbd5, 0x1b4f68da, 0xe62265ed, 0xabb8811f, 0x889944a2, ++ 0xee0ed442, 0x223ff7a2, 0x5749da8f, 0xf6085ffd, 0x0ec31884, 0xe3a670e0, ++ 0x4647c049, 0xe76820bb, 0x927f68f6, 0x3602ef0b, 0x82594d5d, 0x139b4cf7, ++ 0xefd02b9c, 0xce9decc3, 0x367fe7fd, 0x121fbe0d, 0x57033bd9, 0x37a7e445, ++ 0x18192ef7, 0x4a87c0d2, 0x95dfc444, 0xde3b173e, 0x1caff5a0, 0x707e6788, ++ 0xf6a37dc9, 0x7eb442be, 0x982bc380, 0x94d3cec1, 0xe7ef780c, 0xedb3db1b, ++ 0x1fe5f65d, 0xb4a91c83, 0x5880a786, 0xcdb1b21f, 0x639ff80c, 0xc989fef7, ++ 0x80048697, 0xfb0a428b, 0x596e3a12, 0xba04293c, 0x2712d70a, 0x3cedefc4, ++ 0x5e013268, 0xc4c96d46, 0xf8579b38, 0x86e2e379, 0x46a6733a, 0xe7e62d6e, ++ 0x65656755, 0xfbe6b240, 0x2f930742, 0x3f940f67, 0x03f7f28f, 0x431c190b, ++ 0x983916df, 0x5661dc9c, 0x7a856da6, 0xef784c27, 0xbb5bff67, 0x657782df, ++ 0x8d771f17, 0xd035fd00, 0x4d7ac2e1, 0x77c15e87, 0x223e9ae9, 0xdbcdd5e8, ++ 0xe89a225c, 0x17106fb8, 0x311dbff3, 0xe23a7ee1, 0x149e24b7, 0x073f6758, ++ 0x71becfdb, 0xdf3ba4d0, 0x7fbf837a, 0x3930776a, 0xff983a24, 0xc2c1fb6b, ++ 0x7307d014, 0x03b33eec, 0x6854eff8, 0xf5414c35, 0xd7f6a9d7, 0xa7db23b8, ++ 0x1cffa30d, 0x02726ed7, 0x5e475dba, 0xaebd6110, 0x092484b3, 0x463d8ba4, ++ 0x523a73fb, 0xd1bdfda3, 0xf3a3face, 0x55f81378, 0xb0783f85, 0x8dfe6873, ++ 0xe2192956, 0xabf854b3, 0x77c750eb, 0x26cf1035, 0x6792b21b, 0x8df857fb, ++ 0x91d0f8d5, 0x5bbea24e, 0x0bf9748f, 0x40e5c7bb, 0x3ed0507a, 0x1e207b3e, ++ 0x5c1d9ced, 0x92f4923f, 0x1c3fc881, 0x660e054f, 0xe9f3a8ef, 0x8e7cfc6e, ++ 0xbafd357f, 0xec8afd74, 0xf86e9052, 0x252e83fb, 0x3886cd68, 0xfc6ca6b0, ++ 0x389a3abb, 0xff9c7cd9, 0x737bfd59, 0x0993214d, 0xed5571ee, 0x59f09211, ++ 0xcbda1e93, 0x1a933a11, 0x8e9afe90, 0xf2e3e413, 0xdf9907fa, 0xfe1bca90, ++ 0x839e172e, 0xf3f0ff03, 0x4d023ef0, 0x5a6f35c7, 0x1be117d9, 0x455f0074, ++ 0x06f944e1, 0x333a9ad2, 0x65e2ebd0, 0xcfc45d2c, 0xf06f1795, 0x6e967f21, ++ 0xb381f164, 0x8f38991c, 0x895e9c0b, 0xe2033e29, 0x4ddb0e47, 0x8fcaf3ba, ++ 0xe99e2ced, 0x16fae35c, 0xd7d29718, 0xf1d7a05c, 0x0d3e4f4d, 0xf5e955d3, ++ 0xfb1966dc, 0x9fd78b29, 0xbc7097bb, 0xe8c23cee, 0xb966dc7d, 0x1a85de10, ++ 0xf82710a7, 0xbcd8dfa1, 0xfdf90445, 0x2673d006, 0xb7d073e3, 0x9e3c0f67, ++ 0x73d07df0, 0xfe02266d, 0x52661dee, 0x17c34db6, 0x5afd37fb, 0xf5e5bfc7, ++ 0xafd0d3b5, 0x40164a1e, 0xab7cabce, 0xd9877dc2, 0xfff22b7d, 0x9ffe061d, ++ 0x0d3fdacc, 0x5aeba178, 0xfd7ff9cf, 0xf4ffca54, 0x24e6d253, 0x61d9fa01, ++ 0xd84efd8e, 0x7f486fda, 0xea1ab911, 0x3ad75722, 0x1c86ae50, 0xaafc74d9, ++ 0x9fa12fdb, 0x4e3f3220, 0xab27eb37, 0x00299374, 0x0628ebfc, 0x28bc0107, ++ 0xa99e815c, 0x8cff7c3d, 0x83cae41c, 0xf0d39e12, 0xbf1e2073, 0xabf9c6a1, ++ 0x67951afc, 0x7efadf2a, 0x9bc8f309, 0xec12b35c, 0x056294f5, 0xe09cf3e9, ++ 0xf54c981b, 0xe3e039d9, 0x3960f218, 0xd915c787, 0xcff7ad77, 0xcb9e8033, ++ 0xd60fcee8, 0x4e0a3643, 0xee5a8bc0, 0x27f6c8da, 0x523cb8bb, 0x6ff9abbf, ++ 0x9770ef0c, 0x39772377, 0x36132fd0, 0x90e99c43, 0x4463d300, 0x207e4428, ++ 0x8032dba6, 0xfd5316cf, 0xfe8d5df5, 0x21d7273a, 0x0870aa9d, 0x2575b972, ++ 0x86bbad89, 0xb039f3cf, 0xe06b46f5, 0xc092482f, 0x181459f8, 0xffd08b9f, ++ 0x6fe303b9, 0x3dbf7a45, 0x613bbd36, 0x7f0c94df, 0xd2136757, 0x2754d267, ++ 0x2f5943de, 0x7492e3b9, 0xd30051f6, 0x817e5bfd, 0x5fa035fb, 0xe8eef7e0, ++ 0x9fe80cbf, 0x00fba0c4, 0xfe0d7ba5, 0x74a03a54, 0x234391f1, 0xa1748c1f, ++ 0x70aa179e, 0x6f3861d9, 0xc9912ebc, 0xb970bf83, 0xee26eae0, 0x37cf5d45, ++ 0x2ed9f3c6, 0xe46cbe78, 0x2ab7c02b, 0x835f8e1f, 0x3a2566bf, 0xfb6bdfd9, ++ 0x99c63e78, 0xa773f1d4, 0x3a9e3e06, 0xd051396f, 0xcf194f9d, 0x7c125a8d, ++ 0x7ceea252, 0xcae8a96a, 0x1147d289, 0x6e9767b7, 0xfdb9e0b1, 0xbc012836, ++ 0x680f8fed, 0x253a85ef, 0x5052786a, 0xc4cc4af7, 0xe1f4ab79, 0x83266e5a, ++ 0x4ae5fee8, 0x887ec966, 0x55a5b9df, 0xd7461e29, 0xdcaccdb1, 0x03ee3b7d, ++ 0xff42b7dc, 0x9c9b16b7, 0xe491cf10, 0xd7e00a71, 0x7c0d1540, 0x338d8878, ++ 0x237ddb32, 0xee5d7fee, 0x060f2091, 0xf8a9bc70, 0x9dd0e155, 0xaf0eeb9e, ++ 0x527c38b3, 0x8e51b979, 0xa6f9c17c, 0x96d7a795, 0xfc088a23, 0x15be20e4, ++ 0x9f3fcc22, 0x1c88bfc9, 0xae7827c9, 0x2f513138, 0xb7fcd447, 0x26264728, ++ 0xd8c8e56a, 0x42394c50, 0x3ff9317f, 0xb442f375, 0xd8f1c963, 0x899dec76, ++ 0x82a70f4c, 0x52f5a4fe, 0x6e77fe15, 0x791c5d13, 0x58f71875, 0x7182d9b7, ++ 0x721caade, 0xe10a4ddc, 0x403ae6ef, 0xbbad42df, 0x866fc77d, 0xb374def3, ++ 0xcf9fce0b, 0xfbc461c9, 0xaf01ba39, 0x0af0fa43, 0xf218ef80, 0x441f8088, ++ 0xe63f63f9, 0x919b17bf, 0x1116964f, 0xb7fb9fd4, 0x2aba418c, 0x8012ce2b, ++ 0x93ebcb6e, 0x9e4f2804, 0x9c8134ec, 0x6631d752, 0x1a0c89b9, 0x30b07c89, ++ 0x318f8351, 0xfdfe0d4a, 0xbe2981dc, 0xee893974, 0xdf7713d3, 0x3d03f5a2, ++ 0xd2ebf348, 0x9a207ea3, 0xd3eb635f, 0xb2d03f73, 0x035a6d7f, 0x9d64277f, ++ 0xc614b3c3, 0x2ef0496d, 0x77af3483, 0x7234488d, 0xdbf65aeb, 0x6a97a537, ++ 0xad226fee, 0xe9a71a54, 0xeaf3bbfc, 0x5ddfe85d, 0xcaa9f303, 0x7434fd38, ++ 0xc462ef87, 0x3cd9b7b4, 0x40b9717a, 0x8f88223e, 0x111ade5e, 0xdcaa2ffc, ++ 0xbc870f59, 0xc02cbf6c, 0x6fca8ab9, 0x8ec0b720, 0xc02ae356, 0xff4765ff, ++ 0x43eb007f, 0x2f63513e, 0xc5362bac, 0xe5f9177c, 0x2ab7db44, 0xdff3499f, ++ 0x8f3f7d77, 0xc88b1bc7, 0x7e332f4f, 0x7d7af262, 0x763489f1, 0x0fdec1ae, ++ 0xf18f887c, 0xeff70afc, 0x7d15ebaf, 0xc58461cf, 0x2afc40ac, 0x539710f1, ++ 0x342cbf13, 0xc43b410b, 0x760dfec3, 0xfd9f746c, 0xcfa61337, 0x353bd8ff, ++ 0x26f8ec13, 0x18fc1b93, 0xa47efc55, 0x7bc1207b, 0x7dfc0d2d, 0x9b1682c5, ++ 0x7f051e47, 0xefcac5af, 0xe7f47b5d, 0x03c36325, 0x95f2d2b6, 0x1bfc16cd, ++ 0xea059d8d, 0xe370e1df, 0xbe1567bd, 0x3f59dfc3, 0xa544e314, 0xd9f0373a, ++ 0xffac710b, 0xfad4e217, 0xd7d044ae, 0xe7db9ddd, 0xff42cf2f, 0xccafeaa1, ++ 0x8045070f, 0x65d8564b, 0x6c72c162, 0x704c291c, 0x7e79eabd, 0x8efb8703, ++ 0xd045db83, 0xeb9379e3, 0xe73ec256, 0x28efbb0b, 0x7cf8ddd0, 0x4a379dbd, ++ 0x778169a8, 0x04adc931, 0x7f2a47f7, 0x3ec884a4, 0x8e926930, 0x32a03c87, ++ 0xecf59fc7, 0xa2647d83, 0x9fd00897, 0x0da88e26, 0x3cbd25fa, 0xe0bdedc2, ++ 0xbff2e1ef, 0xd9fbc95d, 0x0050b071, 0x3ad5ef7e, 0x74e57059, 0xb00defa5, ++ 0xe2c51edf, 0xeaaf005d, 0x7fe0703e, 0x877f80dc, 0xc9df5220, 0x3e09cdec, ++ 0x397024df, 0x8184f5d3, 0x0ecdc66e, 0x5793c0b4, 0x1694ca63, 0x9eb34bb3, ++ 0xebfb04c5, 0x1d70521b, 0x0afb8e7d, 0x93dbb520, 0x67f19fb0, 0xd3271883, ++ 0xf86086bb, 0x23d6ff50, 0xaff53f68, 0x8f001569, 0x89be0e3b, 0xbad7edf3, ++ 0xaf9ca59f, 0x407b73b6, 0xfb9d979d, 0xa676ed67, 0x7737fe67, 0x006a4c28, ++ 0x00006a4c, 0x00088b1f, 0x00000000, 0x7dd5ff00, 0xd5547c09, 0xf37df8d5, ++ 0x9932cb66, 0x93b264c9, 0x01476130, 0x5bb09027, 0x0a300427, 0xa02901c1, ++ 0x48049c46, 0xd881b258, 0x0cd7eb62, 0xa4623004, 0x054552b1, 0x51f8281d, ++ 0x8d361a8a, 0x9004e835, 0x558d0506, 0x2f96ac5b, 0x225d8608, 0x62d8bf58, ++ 0xf739cef9, 0x97bcccbe, 0xffe97004, 0x1f87fbf7, 0xeef39bbf, 0x7b9df77d, ++ 0x92ee7bf6, 0x2567e795, 0xa6300678, 0x962d79b7, 0xffbac64c, 0x2cb186e1, ++ 0x5995b18a, 0x48f284de, 0xf636d6c6, 0x06407478, 0x3a43be63, 0x63276f57, ++ 0xb18c4937, 0xc15d8c11, 0x8b185b9f, 0x831919b1, 0x78b2eef7, 0x96506d23, ++ 0x603e68cd, 0x1a3b2680, 0x85e51cff, 0x83bd59f7, 0xe2c644b1, 0x80d67d0e, ++ 0x612dc4fd, 0x6b61ba0c, 0x18922d0f, 0x63cdad54, 0xf60a5a2c, 0x2c625f07, ++ 0x5e09b196, 0x10ec6baf, 0xa72c67a8, 0xb661fb16, 0xc616c988, 0x4ded157e, ++ 0xed28efc4, 0x23dbe427, 0xc086447a, 0x2b27bde2, 0x2f766b98, 0x2fed86c6, ++ 0x307ac9d8, 0x1bc22fb6, 0xe06f7aa6, 0x8c2f308a, 0x7748e9fb, 0x20bf3e1a, ++ 0x9df819b1, 0xf3c258ad, 0x5b0e06ad, 0x67c23a2c, 0x52a24d81, 0xb16c9b6f, ++ 0xd93a72c4, 0x30bb4106, 0x57e94ede, 0xe9b3ef29, 0xe64e2e88, 0x26b1fa24, ++ 0xe3336b9d, 0x0c0cf0e3, 0xfa2f1bb6, 0x66f6e51d, 0xcdb6a1eb, 0x01b4cde2, ++ 0x7fb8623c, 0x1a840c9f, 0xa7dbe396, 0x95853287, 0xbd00b3ef, 0x7ea30e58, ++ 0x03599a62, 0x1f4589b0, 0x41477669, 0x9d9b54fd, 0x54f237be, 0x67ba432b, ++ 0xe383cc48, 0x2395e2d0, 0x8d3472f0, 0xd2245891, 0xc70633c5, 0x5cb9343f, ++ 0x0e2a0036, 0x7ac09b66, 0xcd8f7632, 0x190d7849, 0x2327deee, 0x8c8f6ed6, ++ 0x6117defd, 0xa657f7a3, 0xf780f971, 0xccfbe027, 0x017296e1, 0xc3ffa1bf, ++ 0x77002ad8, 0x9c918e35, 0x633bf003, 0x1b98c979, 0xf903b4e9, 0xdb978219, ++ 0x8f7be9c6, 0xfec743a0, 0x1e9033bd, 0x5b9d268e, 0x1d864e82, 0x6833f489, ++ 0xb9716c3a, 0x583bf88c, 0x4100c493, 0x165b5cfb, 0x2e4b2248, 0xd7c84976, ++ 0x4ccf08fc, 0x0f03f51b, 0x759e5033, 0xef784afe, 0x926e519f, 0xc25b05f3, ++ 0xc4cc276c, 0xfe057610, 0xab46d497, 0x44bab2e0, 0x417e89db, 0x02fe0178, ++ 0x33f6cc72, 0x58ca1b33, 0xcf62af31, 0xf805decb, 0xf373129d, 0x4b807cea, ++ 0x91b5ff7f, 0xddc648e9, 0x8d1dce38, 0x420a2383, 0x8e3963e4, 0xefc55333, ++ 0x2d7df1fb, 0xc12433bf, 0xdf80dbef, 0xb6fc8ece, 0xbf05a258, 0x5657a4dd, ++ 0x7df0930f, 0x717fd7a0, 0xa087787e, 0x169a399c, 0xd8f00ccb, 0xbc88fc89, ++ 0x79143f36, 0x3f3858b7, 0x45543e14, 0xbf6257b8, 0xfc41d016, 0xeb0c6fae, ++ 0x27abcf87, 0x9dfc72ea, 0xb633d9c8, 0xdf37ae48, 0x98a7ce97, 0xe905c59e, ++ 0xf5ffeacc, 0xee802fca, 0x4cbbf865, 0xe5067f74, 0xd51ee802, 0xc4fdc613, ++ 0x50e2cfc4, 0xd6e6753e, 0xa3d01283, 0xca765ea4, 0x87ca8430, 0xffe46eec, ++ 0xcb92b5f3, 0x97a9f484, 0x5f9e1e49, 0xa537ee19, 0x62fdf105, 0xbb1075b7, ++ 0xffa14a09, 0x2197d02c, 0xc5a2cb9f, 0x03007df7, 0x1c6c173e, 0xddeaca7c, ++ 0x9e4f6a1a, 0x1847ffaf, 0x04c6f9d2, 0x0c44e036, 0x7b5370b6, 0xb1ff6b03, ++ 0x099fd049, 0xae90937f, 0x2a3255e9, 0x4eef34d6, 0xdb7c4c93, 0x630dfd85, ++ 0x0d1e7fcd, 0xdb61fd78, 0x44379d18, 0x7dd52e6e, 0xe02f7335, 0x3511165f, ++ 0x8f015988, 0xa0fb97bd, 0xb7f5299c, 0xbb20292f, 0xddec80f7, 0xdbd78a13, ++ 0x3b738efd, 0x2d6cf2cc, 0xdda7e237, 0x200895d2, 0x9fb99461, 0x92e0e81e, ++ 0x7c325dc3, 0xf79c36af, 0x948fb59b, 0x06f6558a, 0x1afd20fa, 0x957e89c2, ++ 0xd2ef41bd, 0xb1b7cf08, 0x2316fdff, 0x97e7844b, 0x9db11f40, 0xc0f7f782, ++ 0x63e403f7, 0xd9bb7c47, 0x5c84225a, 0xdafc41c8, 0x807c82f9, 0x9e8b65fe, ++ 0x858171c6, 0xb59f90bb, 0xfe433746, 0xbd728efb, 0x2a56f851, 0x7d42ee64, ++ 0x8c2f11e6, 0xdd23f9ef, 0x85fef85c, 0x3a614bba, 0xadefdef8, 0x878813de, ++ 0x851ad29c, 0xfd5f70fe, 0x03cdfea5, 0xe0b5bec8, 0x8e874bf3, 0xbe03bddb, ++ 0x5c2ef8d7, 0xf4caf8cf, 0x95925591, 0x8b69c6c4, 0x8ee11123, 0x52472352, ++ 0xd237c37d, 0x863fd220, 0xca97d0f6, 0xee3095fc, 0x3c850395, 0xd44e654d, ++ 0x9fbf2d7b, 0xd8ae7ab2, 0x9576f442, 0x674523d5, 0x0f24eff2, 0xd1ca71a6, ++ 0xc3a0e780, 0x741886b3, 0x0cb1be38, 0x258f66fd, 0x9071d863, 0xf9999367, ++ 0xa49da0c2, 0xe0c33e67, 0xc7daf8e0, 0xa0f2fbdf, 0x1bc68c43, 0xf202fd85, ++ 0x5f8074cb, 0x55833819, 0x0ee3a169, 0xc44aff10, 0x91cc4af8, 0xc3c61901, ++ 0x35ce1976, 0x47a0762b, 0x3f81fc47, 0x6f9f8889, 0x1788eb8c, 0x48b7fbf9, ++ 0x47d22557, 0x58f364df, 0x58c93c68, 0x27e786cf, 0x45f7f8e0, 0x9da147b8, ++ 0x9194badf, 0x91785f3c, 0x60c237f9, 0x91d7efb7, 0x37606cbc, 0xa0dfdc90, ++ 0x13d338bb, 0x1bdcfa49, 0xaa68cef1, 0xeddda1d1, 0xd0ea77ed, 0xaa6ff69e, ++ 0x0e48e9d5, 0x7d04fdbc, 0xbf01e92e, 0xcb95b71b, 0xd21e53df, 0x3f43afa3, ++ 0x7c995f81, 0x0a5f9cbc, 0x390b46dd, 0x43748d18, 0x3faad087, 0xd20e6cd7, ++ 0x92c3f80d, 0x63fb1ded, 0xe91539ac, 0xc9daf0d4, 0x5fd0cd3e, 0x67271be9, ++ 0xff4a5d22, 0x18212268, 0x56fec7fb, 0xb22ff794, 0xce678f3a, 0xf4bb9455, ++ 0x24fd4f10, 0xf5d907ba, 0xc464d662, 0x76a4a138, 0x621f4ba1, 0xedf895cf, ++ 0x2269a190, 0x53287ff6, 0xce814b66, 0xe2c35c97, 0x427e2759, 0x78c5df29, ++ 0x418f700d, 0xafce91dc, 0xfc795865, 0xa07f2768, 0x62a87f6d, 0xaf6c6bae, ++ 0x943bfbae, 0x0fc3361e, 0xc4d44fef, 0xdcd16541, 0xcd123daf, 0x641830fd, ++ 0xfe79e237, 0x07df8b15, 0xfe0fce8f, 0x9d018a28, 0x60faefce, 0xe8e40f88, ++ 0xffba6b3c, 0xafb3d475, 0x5dc61922, 0x1a3fd313, 0xd412d4b2, 0xf3879bcb, ++ 0xeafcdfb1, 0xb42728e1, 0x9f7db89f, 0xbf4217c3, 0xabfe999b, 0xc34eb976, ++ 0x31f1f2ef, 0xe41f737d, 0x74fd7b07, 0x89ca139c, 0xe0e5bdaf, 0x43a71072, ++ 0xf6162f3e, 0x147c65ed, 0x5c4f6f12, 0xa4724a52, 0x666d25c0, 0x81098fe6, ++ 0x74464df5, 0x916d25bd, 0xeeed0fcc, 0x5038b68c, 0x4b12580e, 0x25d33b42, ++ 0x9e93aebd, 0x3d0ae7da, 0x4e9fa50f, 0x8be2b8c5, 0x3ae1e22e, 0xee5daed1, ++ 0xd74e202b, 0xbe77e107, 0x74f3ef95, 0xf13adef2, 0x88d725de, 0x26f78c78, ++ 0x6cbd031a, 0xcc63b49d, 0xd2d4fc4f, 0x45cbede9, 0x2befd811, 0xce9ca66d, ++ 0xb46dfaf0, 0x29c587ee, 0x90ab0087, 0xf65ab078, 0xe22d18be, 0x970029c1, ++ 0x1e34bff6, 0xbcbb40ed, 0x3377bb08, 0xfea035f3, 0xe143e56a, 0x1be46ef7, ++ 0x4b326dea, 0x2afdbe46, 0x46e5c9da, 0x1fa283e8, 0xcb6a3a5a, 0xede64609, ++ 0xbab01e6c, 0xcc61ae9d, 0xfef0f607, 0xeff2060d, 0x75ff2f87, 0xf79010ea, ++ 0xb60ceb93, 0xb9c9f065, 0x7b75f7eb, 0xa6e7ea02, 0xc0126c9b, 0x5e819d27, ++ 0xeb45f7a8, 0xc3ca0f65, 0xc7f775c9, 0x2cf282cd, 0xe0316fe8, 0x40c1b451, ++ 0x786ee7cf, 0x169f9e80, 0x3eb45d7a, 0x97b446f6, 0x8aaff787, 0xfdce3e43, ++ 0xc869e1f6, 0xdb46ed97, 0x1650e98d, 0x635c936f, 0x7f3de843, 0xde0a9853, ++ 0x717363ae, 0x995f0a1c, 0x77af6de4, 0xd12d3e02, 0xbdf35e7c, 0xc75018f9, ++ 0xb65f109b, 0x72f8f344, 0xee309dd2, 0x144bccd2, 0x103befd7, 0xcde4fe4e, ++ 0xc7e29948, 0xbefffa40, 0xd9c01373, 0x145deadf, 0x8f3e09db, 0x2c667c13, ++ 0xa176ec81, 0xafd9c399, 0xccfe29e9, 0x6f44c8b6, 0x0e391f68, 0xda227fea, ++ 0xa2cec007, 0xf479321e, 0x6ed0119a, 0xd0c0d59c, 0x3024fd0f, 0x3f03227f, ++ 0xfe9b4b79, 0xf190e6b3, 0xfd35618c, 0x62ce1e30, 0xb773cd06, 0x9b679f1e, ++ 0xf5c7cfd5, 0xc634fdba, 0xea6ce30f, 0xe9dc8ae7, 0x84ee42ed, 0xe077d8bd, ++ 0xc0266fcc, 0xc90f0af8, 0xcb5f3f14, 0xf88bbf1e, 0x6fcf91eb, 0xf7836de7, ++ 0x1caa0b0e, 0x79727cbe, 0x70d5ca22, 0xf8032d89, 0xf5cee5e4, 0x4b908271, ++ 0xfdbf80c6, 0x75cdfc82, 0x51876bcd, 0xbe18efdd, 0xfc461db0, 0x5d8edfaf, ++ 0xa2054edd, 0xeb433e79, 0xf37ab437, 0x131bf29f, 0xf54adfd3, 0x017ca859, ++ 0xb9db73cb, 0x09dad5dd, 0xad589fad, 0xff41afb1, 0x87f953a0, 0x048ec2d5, ++ 0xfc9184fd, 0x1f388fc4, 0x3277b5ce, 0x8638861f, 0xaa1be5e8, 0xc43879a7, ++ 0xddb0535b, 0x4c674880, 0xc5e71396, 0x9ed0223d, 0xfde91d3d, 0x0f243da9, ++ 0x1ab6e375, 0xf68dda1d, 0x9d418cfc, 0xabe651a7, 0xfe3e7679, 0x61873b2c, ++ 0xfcf34abe, 0xa557e2ae, 0xb5ef257f, 0x3cf18b32, 0xa78f3441, 0xea73f47b, ++ 0xec0f386c, 0x7e43a097, 0xf1682fdd, 0x80c24548, 0x8fdf2013, 0xc4a93856, ++ 0xf3df1c38, 0x71a70ded, 0x06792e7d, 0x223ddea1, 0x1b5f2e75, 0x60ee22ed, ++ 0xcafff21e, 0xba6339f3, 0x3d76d3b0, 0x7793d71f, 0xf67c62a5, 0xa9ddc379, ++ 0x073f3f68, 0x5e309b7c, 0x57acbbd0, 0x171eab8b, 0xf098f8fa, 0xde62d113, ++ 0x13d46bff, 0xdd9b4180, 0xb8e007db, 0x8f37a43c, 0xf2a0cc56, 0x54258a89, ++ 0xa34f6e5f, 0xfeb2dbef, 0xfc09e9ec, 0x932d513b, 0xf463981f, 0xf78689f4, ++ 0x9475984e, 0x1e5e383f, 0x122bb399, 0x2f9a339f, 0xc27279ce, 0x5e485f66, ++ 0x91c71caf, 0x3738f5d9, 0xfd9fbfda, 0x51cd612e, 0xe5da8fe8, 0x7f0748f1, ++ 0x163dbcfc, 0x71cd87e7, 0x6a4caed8, 0x268db3ea, 0xa1a9ad57, 0x224fb879, ++ 0xee511bdd, 0x46ec8d6a, 0x70da8bd4, 0x78b46fee, 0xf672156e, 0x213f4548, ++ 0x2701ae07, 0x440b5e80, 0xfa39fadc, 0xfef84ea9, 0xcc2f78b2, 0x4ed97ee2, ++ 0xf8a48ffc, 0xf201c69c, 0xdee51d52, 0x3cc27881, 0x4396176c, 0xce3e79e3, ++ 0x7b09b162, 0xbcf896e8, 0xbd9af3c6, 0x575b7c93, 0x1e2d1df9, 0x3a70c677, ++ 0x4a3ef36b, 0xf67de4a9, 0x63dcf18b, 0x71f2a9b7, 0xeee65ace, 0x1693df2c, ++ 0x09f6a463, 0xe11cb76e, 0x32ef5aec, 0x64f99fbc, 0x60cd6bcc, 0xc450deae, ++ 0xc06dae8f, 0x58e2577c, 0x87cc52ff, 0xead68cad, 0xe70c2fa1, 0xbabc3d63, ++ 0x8bb41f38, 0x1966f26b, 0x6b168f01, 0xcf15e11c, 0xbf2297ca, 0x1a3abc32, ++ 0x70fec674, 0x9e4ca4bf, 0x6110c9a1, 0xc343411f, 0xb29edf50, 0xfd218f78, ++ 0xaf2ece86, 0x5f313a34, 0xdc79a3e8, 0xdddbc969, 0xfa71f20e, 0xe34ef0ad, ++ 0xde8a8bdc, 0xd092634a, 0x326c67a5, 0x36321d10, 0xe22676fd, 0x56e9b19b, ++ 0xff9214bd, 0x50318a88, 0xcd6fd3fb, 0x88f94eef, 0x77ac4d8f, 0x8d7ec75a, ++ 0x16dfbc31, 0xc69def41, 0x174ee5ce, 0x38b0fd23, 0x1be219b5, 0xc5d69db5, ++ 0x67f30664, 0xc91725a5, 0x73b51f4e, 0xbeacf0ff, 0xd01240f6, 0xccd9d9f3, ++ 0xbf9f7485, 0x55e50365, 0x6f6b1a77, 0x29e386db, 0xafcc31d5, 0xc7f03fec, ++ 0x1f184903, 0x63a676ce, 0xfefed07c, 0xf12bada1, 0x5973b3f9, 0xd13fd23a, ++ 0x7984b8ff, 0x6ac3af96, 0x6f5f5e88, 0x30a5b136, 0xd7ef79a4, 0x800bf6de, ++ 0x18eb16d7, 0xb8ed15da, 0x5d064be1, 0x83019602, 0x3fe7386e, 0xef853fda, ++ 0xe4465820, 0xa437c287, 0xf72876df, 0xf0957e6f, 0xb16af057, 0xf3ce893a, ++ 0x0dbf6cb7, 0xd8a924e5, 0x5ffce12e, 0xfa87ebc1, 0x7fd11f89, 0x5ec4c666, ++ 0x191cff97, 0xd4ff89d3, 0x23a7cdfa, 0x7f6337dd, 0x079ff2d7, 0x1fea7d84, ++ 0x75f6e1c3, 0xca3a438b, 0xb2f969a3, 0x8f21dedf, 0x7be6313d, 0xb15fb1e4, ++ 0xda7be9db, 0x2356f63c, 0x7635a3b7, 0x4ee4df76, 0xc0bb61f4, 0xd5a6b757, ++ 0x51d17e88, 0x976a752f, 0xcf1e162c, 0x2fbcdd81, 0x439d6426, 0xa13b576b, ++ 0xefb6216f, 0x17b02dbf, 0xee8e0d5b, 0xd7618115, 0x9e60570d, 0x4a77c9da, ++ 0x173a7e85, 0x4ed0b703, 0x47b23396, 0x3279fb00, 0xfda1202f, 0x61947e01, ++ 0x6f5ad7bf, 0xd166b26a, 0xbeb2933a, 0x549562d4, 0x3135dbf3, 0x83f73b4a, ++ 0x174a5fd8, 0xb0a97ef6, 0x1f7e302f, 0x316381ca, 0x28a3ad53, 0x728e27eb, ++ 0x40cc649f, 0x2f28c2b7, 0xbbc63dda, 0x5aed00d4, 0x46d73047, 0xb679ad80, ++ 0xf697b42c, 0x5c06aeb9, 0x9e795967, 0x2e57d1e7, 0xd465fe64, 0xf32f1f0f, ++ 0x4e6ff0f6, 0x9d0b7ce3, 0x457e2bcf, 0xbbf81f19, 0xd78e189a, 0xe2ae626f, ++ 0xbd447eef, 0x5ea75ff2, 0x7c2efe6d, 0xf93af17f, 0x896184ee, 0xf7ed1375, ++ 0xda5e2276, 0xec9c81ef, 0x59391eba, 0x25d75df1, 0x361fa423, 0xd748ee4f, ++ 0x893a6277, 0xea27abf7, 0x9c71e9fa, 0x99d5dc2c, 0x131a3bdf, 0x1f5e9ff9, ++ 0xadf82a3a, 0x1f821f5a, 0xfcff3c55, 0x7d7bd732, 0x6577cf11, 0xff3da79a, ++ 0xf22366ab, 0x506f5959, 0x27fb2df0, 0x87f82448, 0x51d4ff0b, 0xf5f7aed9, ++ 0xf79c10d2, 0x4cbbed65, 0x8685f9f1, 0x7e7c527f, 0x2b9f1341, 0x72845ddf, ++ 0x938cf800, 0x2e7f4923, 0x0479e3ae, 0x1a9f3999, 0x46f2f98d, 0x493bf303, ++ 0xa17e29fe, 0x117c02f1, 0xc5bf6c4b, 0xa2cdf348, 0x06873b83, 0xb87591e0, ++ 0xe843398e, 0x670eed15, 0xc57a10ce, 0x7055d8e4, 0xd54927ac, 0x0f467e3e, ++ 0xf7a27d55, 0xf27d5506, 0x382ac1dc, 0xaaa47ca5, 0x9bf0777d, 0xef9a70a1, ++ 0x9efb5576, 0x70545355, 0x55bb9aef, 0xddcf99ed, 0x39c60bd4, 0xefb38c5b, ++ 0x7b5502da, 0xae009f50, 0x6c11cd9b, 0x7c75bb3e, 0x640e04a3, 0xf487c8b6, ++ 0xf557cff7, 0x9d46a737, 0x023a20d7, 0x24eb0add, 0x6dd20cf6, 0x6e7ebaad, ++ 0x932be3fd, 0x57e79ca1, 0xeb8f9f3f, 0xa7ca1259, 0x9d6ef9fa, 0x479c7ee7, ++ 0xf3a877f4, 0xafe4d724, 0xf8b5efaf, 0xfb600aeb, 0xb78a166d, 0x22ce0e8a, ++ 0xa825323d, 0x0ce61bf9, 0x22fd2abf, 0xf535d9fa, 0xf42aeff0, 0xf2d4b8b3, ++ 0x9e9fa5a0, 0x06481eb5, 0x92fd4abc, 0xd23ac02b, 0x06dd5e6f, 0x3f4b53c2, ++ 0xd0eedd2d, 0x845f6bd0, 0x13238a77, 0xcb164dd7, 0x72c4ceb8, 0xa5f57af8, ++ 0x1d06afba, 0x95d6aa72, 0xb9475aba, 0xbac9d1db, 0x475c05da, 0xc75d89bb, ++ 0x6fbeda3a, 0xf0260e90, 0x27e00658, 0xb732ee1b, 0x05859baf, 0x76b44dd7, ++ 0x6ec1294b, 0x3d90702f, 0x5637ae0f, 0xad43dbc2, 0x9e50f17f, 0x293fac50, ++ 0x7d9451fb, 0x8f922c33, 0xe807e953, 0x33f63f70, 0x811ecb21, 0xfbedb7f3, ++ 0x447cd117, 0x2c8337d9, 0x121f6d0f, 0xacfd9317, 0xc9135fc5, 0xc1c2fe9f, ++ 0x5843e9fd, 0x0594fe2a, 0xc2bbfcec, 0x8fd5769f, 0x55d4ceb2, 0x6995ed29, ++ 0x0a55acdd, 0xc4ec6d77, 0xf8e93f9e, 0x5393f381, 0x4faff21d, 0x27e7423a, ++ 0x803a5c0f, 0xfee81d76, 0x08e283b4, 0xd05297f0, 0x11153e5f, 0x7ad6fa45, ++ 0x85f7f650, 0x4ecd1707, 0x70407dab, 0xef8b4c3d, 0x00d27368, 0x4a3ac87d, ++ 0xb35f26bd, 0x5f8f3072, 0x5ae3105e, 0xedfdc91d, 0x6997011e, 0x55650be6, ++ 0xda0c5e7c, 0x243eb730, 0xb0e3d84e, 0x447179f0, 0x7bc41ed6, 0xac2bc883, ++ 0x7be8934c, 0xfc89252b, 0x31d683fa, 0xc8ec5f54, 0xb772c7aa, 0x3de9fb83, ++ 0x59415318, 0xe3e383d3, 0x944afb14, 0xf68897fe, 0xa8631c4b, 0x89b0e3dc, ++ 0x0376c9f8, 0xe11cdbf2, 0x728d7ea6, 0x7b2bebe7, 0xd01f3c1d, 0xb193730b, ++ 0xf2513d41, 0x1d85e3d7, 0x89b57cc3, 0x713dc994, 0x5f305c5c, 0x1fd1e4cd, ++ 0x4f221d1a, 0x6eebd12d, 0x08b737b4, 0xb795763e, 0xedb3f776, 0x8e9165c7, ++ 0x4240eb79, 0xd76b79a7, 0xc35bca78, 0x971c7a9b, 0x7c8d7f36, 0xf507b088, ++ 0xf68eefe1, 0x686eaf75, 0xde8cea6f, 0xb4879c4a, 0x167886ee, 0x37f3f71e, ++ 0xe07b5e53, 0x9c2e9ea1, 0x634cac6f, 0x3f282d7b, 0x78c3194b, 0xb759aeb7, ++ 0xabea0c2c, 0xf586cc7d, 0x79f1d623, 0xa75ad14c, 0x8069870b, 0x7065a1f9, ++ 0xedffbf50, 0xd5fa2688, 0xc0694f35, 0x54f5773c, 0x50b74766, 0xa3b26ac3, ++ 0xc758be30, 0x7d479d3a, 0x4269e423, 0xf5195ed6, 0xe415b63f, 0x7d3e13a8, ++ 0x07f2e0e3, 0x7a86ddfa, 0x7bd5ac31, 0x712baf89, 0x0e2640fb, 0x75fb6be7, ++ 0xdf6b7f14, 0xf65467ff, 0x060e51bf, 0xdfcf3bfa, 0x7970b2f4, 0xd1e1181b, ++ 0x5dbb62c7, 0x43b446cd, 0x9d3d8a45, 0xe07a63ad, 0xaf829dfb, 0xfbe3ae77, ++ 0x2be5d810, 0xee256457, 0x433fd462, 0xd534513b, 0x487cc7e2, 0x8f9a7d51, ++ 0x9448f2f0, 0x7fab29ef, 0x517083df, 0xe70d8646, 0x31bfeedf, 0x851fa5a9, ++ 0x23db8c6c, 0xec516b3d, 0x0755f903, 0x114c9fad, 0xe2cbd6f2, 0x6ec13c24, ++ 0xfd004757, 0xdd2dd68b, 0x3e50fb8b, 0x75a31dfa, 0xeb722392, 0xa7ecec50, ++ 0x83259c40, 0xbcb3d4b1, 0x5f32f8c1, 0xfa2a9987, 0xbe13fdf1, 0xf77e0e6b, ++ 0x6907f5a7, 0xcc0c473c, 0xba390667, 0x13ba67b0, 0xb195d7e3, 0xb5c91766, ++ 0x2a3c5f58, 0x5390577b, 0x2296b7d1, 0x47d5776a, 0xc37f70d8, 0x7bb908ff, ++ 0x303bd634, 0x9779da16, 0x7e8a56dd, 0x29a979ad, 0x7792fd15, 0x00eca259, ++ 0x25abbd3c, 0x6598f71a, 0x875c4689, 0x7d3cb59f, 0x838bc63c, 0xe6257b99, ++ 0x618dee33, 0x4fe9ea9d, 0x169eb963, 0xd1981b94, 0xe230834a, 0x55f38afe, ++ 0xc0afed12, 0xe05ca475, 0xbe315ccf, 0x8fde4792, 0x8980f922, 0x9e7b8e3c, ++ 0xf2dccfe0, 0xad47d222, 0xb5662ebf, 0x67e844c6, 0xef4c357e, 0xdff4747a, ++ 0xf8505d8a, 0xaeab525c, 0x5fd5632f, 0x060e3ed2, 0xed05b3f1, 0xc7ffc6bc, ++ 0x31747d0a, 0xfbd5f217, 0xf7198b33, 0x74118cbb, 0x6c96afc9, 0x2d665f68, ++ 0x0e9d886f, 0xd946acf0, 0xd0ad3285, 0xaf887585, 0x857ed006, 0x29bd8d8b, ++ 0x74e8bebe, 0x6f3b63c6, 0x25bb8f14, 0x3e1877bd, 0x3bc637bf, 0xadb5e70c, ++ 0xee185b1f, 0x06d638ff, 0xcfee14f1, 0xb441b332, 0x83636efe, 0xc5f88726, ++ 0x0e2d837c, 0xb63edaf3, 0x35f18128, 0xb8e8731a, 0x4dd5cccb, 0xc65b6eb8, ++ 0x3e313ef4, 0x7c448ae9, 0x7d6d5123, 0x267da24d, 0xc3e0ceac, 0x33331af5, ++ 0x197dc52f, 0x71359da7, 0xcf328210, 0x69e9030a, 0x8a68b6c1, 0x67960b0b, ++ 0x0b7e511b, 0x1d934576, 0xc3ee7882, 0x7c83435e, 0xc87cb63c, 0xb7e80481, ++ 0x25cd36a0, 0x4277f9ab, 0x1d56af15, 0xe276f853, 0xd13b7c1a, 0x5f80df19, ++ 0x342be7aa, 0xc50f62fc, 0xb7911c50, 0x66deadf0, 0x7962e7c0, 0xe99fed18, ++ 0xdd609e2a, 0xa53eb41c, 0x9272b3cc, 0xb443e7da, 0x3aa97bfe, 0xe5a6f893, ++ 0x67bfce57, 0xc27f430d, 0x686166fe, 0xc9edeec7, 0xcf029bee, 0x7eb893ef, ++ 0x5b795bdd, 0x73e9ea0e, 0xbe6edcb1, 0x34230157, 0x857ef632, 0x30fbb999, ++ 0x8d8541f6, 0x122a8fe0, 0x856bfe08, 0x2b8fca93, 0x427951fa, 0x3d1495e4, ++ 0x79200103, 0xedcb14dd, 0x6558a6eb, 0x027171fd, 0x7f9c8c9a, 0xb3a9907f, ++ 0x6e0fa3e1, 0x7202971f, 0x846206ec, 0xa6332fc4, 0xdb932046, 0x6d8366e1, ++ 0x83c6027c, 0xef64488f, 0x54a33c0b, 0x69de99ed, 0xaccc7dc4, 0x73e090df, ++ 0x34e4efda, 0xbc39014e, 0xaa8c626b, 0x64aab4fd, 0xeb1f5c15, 0xe726fc24, ++ 0xbf3d54f4, 0x1546ef3b, 0x4406df9c, 0xb37275c0, 0x8a13af9d, 0xecc667f5, ++ 0xe36bfe7c, 0x1f2abf6d, 0xc073ff16, 0x0643abf7, 0x43f2d7aa, 0xb5ecebe1, ++ 0xd405e63a, 0xb185ad66, 0x6a27bf41, 0x9d5e9166, 0xbf21623d, 0x90db72bf, ++ 0x7c038777, 0xd6819b6c, 0x8f2d8f89, 0xa0eb8d59, 0x46c5b6c7, 0x2bbd2831, ++ 0xb8c01665, 0xb2336f56, 0xbd96fb10, 0x43ed297c, 0x5c9bf7ca, 0xfbf9ffa8, ++ 0xb029cf7d, 0x443be313, 0x43e3f512, 0x88901fd9, 0xefa26e7f, 0x66ff30d6, ++ 0xbd814f80, 0xb3cfadc6, 0xa75e399a, 0xe11cb624, 0xf69f61d3, 0x71e039f9, ++ 0x50a6b73e, 0x7cbdf187, 0xe5ec9628, 0xdca1990e, 0xd0342de6, 0x8fbcd53a, ++ 0x33080de4, 0xe7327069, 0xeafb4cb7, 0xf51356d8, 0x42415acf, 0xdfe2dda0, ++ 0x92ae369b, 0xde08cd38, 0x4abfd03d, 0xd1ca27c8, 0x8ee668a9, 0xc2256426, ++ 0xb1fbccf7, 0x483eb01b, 0x1c20ff4f, 0xa7bd41f7, 0x99c3fd15, 0xb220ff42, ++ 0x92c50f6b, 0x7ee9695e, 0x96edc8c2, 0x0a40f50f, 0x9ea0cbda, 0x307f232d, ++ 0x738ae0cb, 0x48cabd91, 0xa2757b44, 0x71fb40da, 0x351dde99, 0x3b33e699, ++ 0xef958e48, 0xc73bd09c, 0xaa277e23, 0x11e618d2, 0x8a65aa0a, 0x78fe5007, ++ 0xe75f3f7b, 0xb2f65c78, 0x956fd061, 0x1df165e4, 0x85fee6e5, 0xce3f68c3, ++ 0xd1af314c, 0x402f81da, 0x827dbd57, 0x7c3dfcf0, 0x68cb08bf, 0x181d4fd6, ++ 0xfce58e3a, 0x7fbc097b, 0xb8bb3d65, 0x628e9fc7, 0xb1b17dc8, 0xf0fd15a7, ++ 0x92650fe9, 0x6a3dd3b3, 0x3f002686, 0x0ef6e9cf, 0x67c039fd, 0x7a2d7d73, ++ 0x6f708554, 0x3fce1c4a, 0x52a9d574, 0x79e7dc0f, 0x7828f57c, 0x068bccef, ++ 0x92f9a917, 0xf31fb258, 0x1eebceb7, 0xa3af6fba, 0xf1240afd, 0xa27706f5, ++ 0xe05cf404, 0xf98f1dac, 0x23cc39fd, 0x8fa710fc, 0x81111713, 0x1235b62e, ++ 0xc7657e6e, 0x70ab2d33, 0x502cf0ff, 0xc479d093, 0xdbcf0371, 0x7c78e2b9, ++ 0x0f09c4a5, 0x333b71c4, 0x9be5c74b, 0xdc5124bd, 0xfb2a3f06, 0xd9f6265f, ++ 0xb15f7629, 0x86acc5d7, 0xc4c73dd6, 0xf378fdf1, 0x2bb53f24, 0x304c15c5, ++ 0x9e368551, 0x62de2d94, 0xa8d3fbf2, 0x1c685b2f, 0xc9ce3cb0, 0x2f8c43d7, ++ 0x5b62893e, 0xf8f89ac4, 0x18ceed34, 0x694d85fc, 0xa14dfd1d, 0x3b72c36d, ++ 0x61706ff5, 0xe848a33e, 0xe48d4969, 0x9071f00f, 0x0ef254df, 0xd4df8473, ++ 0xfe0ea7fa, 0xe687e348, 0xab2cfc68, 0xc055fb51, 0xa3bf1237, 0xd3c5abe0, ++ 0x3a216113, 0xd0bc07cc, 0xfd7a16df, 0xde112607, 0xd9380b92, 0xe6229f01, ++ 0xe38d1b19, 0xb380fa80, 0x71da7e23, 0x8c57c075, 0xa1778b53, 0x9c80cbeb, ++ 0x5139f7c1, 0x0e3347fe, 0x78da1f85, 0xa14be14d, 0xb0b7d38f, 0x7e7e225e, ++ 0x32071ede, 0xf228ffca, 0x5aa01302, 0x499efbf5, 0xd68acf68, 0x0b4dfd80, ++ 0x4f228fca, 0x146d59f3, 0x0b294bca, 0xfd444cac, 0x1b4ed40a, 0xbafb7181, ++ 0xcffe29f7, 0xeb7a07b3, 0xd98491a2, 0x1cdce68f, 0x9d2d6b94, 0xefd7c5af, ++ 0x951c374b, 0x015fc95e, 0x926ce69d, 0x548361dd, 0x187ec4ed, 0x5cc1e91f, ++ 0xf988cf9f, 0xde62b98a, 0xcb3c2d7f, 0xf3ff7cf4, 0x22edf135, 0x78a1fa4e, ++ 0x791388ef, 0x56710eb1, 0x76676b6f, 0xa7e7194a, 0xd35caec2, 0xd35debbf, ++ 0x58f7f919, 0xb5d697c9, 0x7e142ebd, 0x79fa0e7d, 0xeed65b28, 0xe7da7ca4, ++ 0xde52766b, 0x9ce2f8dc, 0x5bb78c28, 0x8d5aced6, 0xb65a92fb, 0x5ebf22cd, ++ 0xd7e28cf4, 0x78d0c6bd, 0xfe6d7b21, 0xf285fff3, 0x768c25ba, 0xf7ee1580, ++ 0xd80e798a, 0x5ce76851, 0x5b26edcb, 0x1168edc3, 0xd7ca3ffa, 0xbb62fb78, ++ 0xfb7a159f, 0x3c87dca2, 0xb3f8bf27, 0xf797de59, 0xfb3fbf40, 0x47cb8443, ++ 0x7405b643, 0x02dba714, 0x164affe8, 0xee28f5fd, 0xff7f06cf, 0xbf8a83d1, ++ 0x9b7b3e27, 0x7e283fd1, 0x90de44be, 0x40b8c36a, 0xd7ff85f8, 0x7a402ef4, ++ 0xe9c53c53, 0xa71559fd, 0x4e6af1f3, 0x7adb95f7, 0xf0fce146, 0x149eaab3, ++ 0xadb67d47, 0xf67bd137, 0xc537a02a, 0x1c754ed1, 0xc6f40555, 0x1bd20279, ++ 0xefd82af0, 0x7176f414, 0x3a71577a, 0xce5e6ab3, 0x1f5740ee, 0xecffcbad, ++ 0xc6172677, 0x02c2a705, 0xda9d2f14, 0x90cab32e, 0x73894b38, 0x9e6ac1fe, ++ 0xa14c78c3, 0x4d3ebcf7, 0xe4bed083, 0x28a7fe3d, 0xedbcfba4, 0x81de293c, ++ 0x8f1dccde, 0xfbf076f1, 0x4c5171ed, 0x745c687c, 0x65297c9d, 0xaf7e461e, ++ 0x70474ffe, 0xe1b9205e, 0xf79e3b55, 0xea0ae710, 0x700ae7d4, 0x1d9e418f, ++ 0xb32e07f3, 0xa6e9f119, 0x65e12f3d, 0xbafdf798, 0x173397f7, 0xaab71e91, ++ 0x624d69f6, 0xc63c4301, 0x9d12b587, 0x9c592bc3, 0x30c59515, 0x784e5caf, ++ 0xaa4bc6e4, 0xb225787d, 0x62c3e28e, 0x95138f23, 0x788cbcf5, 0xc4640f1e, ++ 0x667d79f3, 0xbbde8dbc, 0xcec8c610, 0xfd18b05f, 0xe61e6fb8, 0x7df8094b, ++ 0xf1131edf, 0x04e228ed, 0x228d97f4, 0x0e2e032f, 0xc61ef1e5, 0xc89ef1e5, ++ 0xc36bca46, 0xfa3d644c, 0x98977bbd, 0x3ab7145c, 0xbd5f94ac, 0x7bb3d85b, ++ 0xd07a5722, 0x691bdffe, 0xfd096374, 0x983370fa, 0x1e7c0c61, 0x32486fbe, ++ 0x3c86fed2, 0x388bf373, 0xe12fbdb5, 0x406603f8, 0xaf0826f5, 0xbf026f31, ++ 0xd312baee, 0xfe412f91, 0x6538f3a8, 0x35e79de1, 0x497a09a6, 0x6be5376e, ++ 0x3877d04c, 0xbc5771e0, 0xda773f93, 0x1d66fe78, 0xe412c9f0, 0xf339f6af, ++ 0x317dfcf1, 0xc91bc7ee, 0x270c80b8, 0x62e0abfa, 0x8f2faf23, 0xa6b09daf, ++ 0x667f631b, 0xb7c881ce, 0x3819b462, 0xfab7cf7f, 0x077dbf31, 0x58ec8fe6, ++ 0xa65e49ea, 0xc74f99e8, 0xdc48aacb, 0x49f223ab, 0x7f3d0493, 0xac059c3a, ++ 0x41c0f740, 0x7a6b3e75, 0x0be81740, 0x1f43bdf4, 0xd4f94068, 0x1b069d99, ++ 0x2393c77c, 0x4779c60d, 0xc3ebb2f1, 0xf5fe32b7, 0x03466b09, 0x9cfbe3ac, ++ 0x79e41f5a, 0x59407b86, 0xf5336e91, 0x983cbf6c, 0xa5d201cb, 0x51f4eecc, ++ 0xe51285bb, 0x9a3c953b, 0xe874ffc2, 0xf78f943e, 0x9fa0fc08, 0xdf7c28aa, ++ 0x7ebf39d8, 0x7716e42d, 0x17dd21ca, 0xa05bbd08, 0xb536dbe8, 0xf0acbdbe, ++ 0xa05ce311, 0xeca23ddb, 0x09b62f4a, 0xcf16d879, 0xc4cfe3e7, 0xebf1f32b, ++ 0xe48b1efb, 0x7d14fafb, 0xfef13129, 0x21dfef95, 0x76f1adca, 0x0f82871a, ++ 0xd867ebc8, 0x002c0e8f, 0x9a89ebca, 0xe67f8a4a, 0x75bc90b2, 0x229db05a, ++ 0x76e11dd7, 0x82bba23b, 0x3675b1a5, 0x49fa5e92, 0xe8ed0b98, 0xdedac63d, ++ 0xba8f3cfc, 0x92ceb29d, 0x8c0c9ac7, 0x77c8a4ec, 0x4e333f09, 0xf4f5a48e, ++ 0x739f893c, 0xf16590bb, 0x8798ace9, 0xf36b1031, 0x6fda25a2, 0x5f1869f0, ++ 0xfad7bb37, 0xd7a849b3, 0x3d465179, 0x2b593396, 0x5b77fbf5, 0x8674eb0f, ++ 0xcc6498fb, 0xcf87c38d, 0x77c3704e, 0x70eed12b, 0x68f751f8, 0xb8091aca, ++ 0xd0371df5, 0xe065ea61, 0x4e5fc13f, 0xb9dd8370, 0x67a896f0, 0x0bfde917, ++ 0xfb1c842b, 0x6ff0e6be, 0x717ffa95, 0xfea511f8, 0x531f870a, 0xe3f017fa, ++ 0x9aa5fa9a, 0xfc39a7fa, 0x265753e9, 0x1d2e30f8, 0x6f3a45c3, 0xaa7644a4, ++ 0xf019ca27, 0x80596f33, 0xdba79be8, 0x2c31cbcb, 0x76b8cba0, 0xa782733b, ++ 0xd91ffa27, 0xfe82c272, 0xeee491d7, 0x67720f19, 0xc49ef388, 0xc964fe72, ++ 0xfb7b4467, 0xc1fc9fa1, 0xdbf62ea4, 0xdcf614f4, 0xf7a1e89c, 0xfd05ff15, ++ 0x7e9f7eb4, 0xd0e84c9e, 0xa7df37cf, 0xf11dd99f, 0x7e6425d1, 0x4ede7ef7, ++ 0xfa5274e4, 0xa29be251, 0xf60a7764, 0x54384ec7, 0xfc162bfb, 0xfcc565ca, ++ 0x15fdc312, 0xcb05fa40, 0x4087536a, 0x7a5e0bff, 0xe310b52d, 0x4be7e129, ++ 0x8dcc74db, 0x18db09e7, 0x3e1b6795, 0xa8b9e236, 0xc60d5dd2, 0x0caed0f1, ++ 0xbc10ecca, 0xe09e058a, 0x4253f4e7, 0x048f73fc, 0x8f17b09d, 0x97c8f5f3, ++ 0x9f91eb4e, 0x2db5740b, 0x1edfa0cf, 0x0eba7529, 0x3bde2e13, 0xd8bec5da, ++ 0x0edc097e, 0xf77148cd, 0x618671c5, 0xecca008e, 0xd5d7ceca, 0xf2fe8a16, ++ 0x359bdf84, 0x027662d4, 0xe43f339d, 0xeb8550eb, 0xf9d306d2, 0xe931b8c2, ++ 0x97cd5709, 0x697cf2b6, 0xe697cf3d, 0x83169bd9, 0x09c566f1, 0x30cdabdd, ++ 0x94f09b1f, 0xb2a067a2, 0x498e6ef0, 0x1c4e8781, 0xb3e78ddb, 0xed63be10, ++ 0x37a8d54d, 0xe60f888d, 0x0c0d87c5, 0x9cd0bb47, 0x81b3a116, 0x9b1fe8bd, ++ 0xdc788c5f, 0xf1e6ec3b, 0x64cb3cf8, 0xf3cf93e9, 0xfd1724ee, 0xe2b73d63, ++ 0xe63db1b8, 0x40c6bc39, 0x871874ec, 0xf6996df7, 0x4507782b, 0x575b3b78, ++ 0xe5c0971a, 0x46c138a6, 0x360468f4, 0xe0a2fc63, 0xe21f7ca1, 0xd04dc5f7, ++ 0x896589df, 0xb89cabe9, 0x80b5928e, 0xff7c49e4, 0x8cef58d1, 0xd09fefd0, ++ 0x85383eb1, 0x7e3c5eb8, 0x00b1f82a, 0x67a506f9, 0x21dcccb4, 0x6329b8f3, ++ 0xd4f05423, 0x1dcc3189, 0x9a9d879a, 0xe46782ac, 0xbfb554f5, 0xaa8df67b, ++ 0x53535cfa, 0x1c487946, 0xe49c75db, 0x16c9ebe3, 0x73c6384b, 0xc7ffaf7f, ++ 0xf8c1ee5f, 0xc2ec936f, 0x9ede7558, 0xc5197fcd, 0x3b887f68, 0x4e8bf286, ++ 0x699d87ca, 0x75c51994, 0x743eb77a, 0x6b3ce7dd, 0xadf7127a, 0xa3ceb574, ++ 0xd81763cc, 0x8dbed3f6, 0xa79d7b1f, 0x67cc413a, 0xe8c1b307, 0x7f962f0f, ++ 0xd2b8f944, 0xf3be3e48, 0xe2331daf, 0x1bae273a, 0xbf79015e, 0xf8c45f15, ++ 0xf947cdb0, 0x63baecea, 0x20362eb4, 0xd2e9db81, 0x78f50b6e, 0x4a0ca63e, ++ 0xc1e343f4, 0x5e41595e, 0xc0d81a9a, 0x9aaeb85d, 0x7871e166, 0x62c614db, ++ 0xfe78ae50, 0x9a2e31a6, 0xa82f07ce, 0xa5e7a1ca, 0xffd4e16d, 0x78d3727b, ++ 0xaaf77fda, 0xb90beb44, 0xc32ef7c9, 0xe18db2fd, 0xc3f701be, 0xbe5f7377, ++ 0x56e90735, 0x27ef8bba, 0x9cff95cd, 0xe2ca10b1, 0x3f7a1c9a, 0x128d6657, ++ 0xb2130bc4, 0x45cdffb9, 0x3cb00f9f, 0xfd0ab2d4, 0xf40c6cae, 0x8ced1679, ++ 0xc67642d1, 0x7d3776da, 0x4ccdacbf, 0xe04eefef, 0x99a193f1, 0xcdae35e3, ++ 0x7915cf43, 0x87a13d78, 0x21a79f6a, 0xef1e9376, 0x3334308f, 0xdb7b7f6a, ++ 0xe32a540d, 0xefdfbb7d, 0x21a8dce8, 0xb8f1abf6, 0x876de74f, 0x4430a364, ++ 0x952f8763, 0x4eb2b30f, 0x77fb54ec, 0x36bef8da, 0xe7df1b53, 0xfdc937b6, ++ 0x4983da3e, 0x71eb350f, 0x9a4587bd, 0x49af486d, 0x859dd3c3, 0xef25fa21, ++ 0xfc88cbbd, 0xdf79ac31, 0x04da7e88, 0x7d487665, 0xa0afd889, 0x6d7fd3b5, ++ 0x694bd3b7, 0x61df8abc, 0x7f2479d5, 0x00426d33, 0x17ecfe85, 0xbf794476, ++ 0xc034e689, 0x4f3cddc7, 0xf79249ff, 0xa687da0c, 0x0763362c, 0x54a6cdd9, ++ 0xb1f9675c, 0x9b3e07f0, 0x9b138a25, 0xa4e6ff69, 0xe61d4ee1, 0xbc082ff7, ++ 0xd6be3d14, 0xed153e38, 0x12d993df, 0x5bbdf7ec, 0x4372696e, 0x1cbf0d7f, ++ 0x41fd0432, 0xe4485dbb, 0xad9829e7, 0x07ce32f5, 0x7088decb, 0xe2e7bea2, ++ 0x33d70c64, 0x9e6898f7, 0xbd69cf02, 0xd30deca2, 0x50f73c46, 0x55f30516, ++ 0x9bf67ef8, 0xe3940161, 0xf4c33786, 0x4d1e37e8, 0x58c4b2f1, 0x2c77de7c, ++ 0xf5dd0fce, 0xb8a33d26, 0x66252dc7, 0xb5ef8d76, 0xce5696ec, 0x56f4fd14, ++ 0x17c97d71, 0xf4205a72, 0xe8f42bcf, 0xe93c7952, 0x0087a5e1, 0x7d075c69, ++ 0x0bb81a48, 0x85a704e3, 0xf45219ee, 0x43e71732, 0xc6f73cf0, 0xab2fda68, ++ 0x3d5a1bc4, 0x51b36e2c, 0x4e6d25bf, 0x8276efa1, 0x102bbd15, 0x7112637a, ++ 0xe7216cc6, 0x74dec9c9, 0x256e7f1c, 0xad147de8, 0x3ea067d3, 0x68c6e505, ++ 0xb902f943, 0xd10c2849, 0xbb86ca9f, 0x2627c618, 0x66e48787, 0xf1a19436, ++ 0xf8f69cc9, 0x0e3e36c4, 0x3cb49ff0, 0x74e7874d, 0x89a1fa94, 0x9f5cdc8a, ++ 0xe44cf7fc, 0x191052fa, 0xacf18de8, 0x85cc3ca1, 0x3a2faefb, 0xa2ce7af8, ++ 0x171d3847, 0x18d93c19, 0x5a7a2c5f, 0xc618fca2, 0x8697681d, 0x8637291e, ++ 0x6aee51e6, 0x409cc41b, 0x7adb3b87, 0xce3fd951, 0x23e5163b, 0xa09a6dbf, ++ 0xb5efa0d7, 0xe6e9987e, 0xdf832479, 0x8690dae4, 0x8caf2479, 0xc2953e7c, ++ 0xae844f6c, 0x51d5add7, 0x57594bfe, 0x264af254, 0xe212e7dc, 0xafa1ff47, ++ 0x067ba549, 0x2ca679b4, 0x6dcff7ee, 0x2fdf9032, 0x50f3f86e, 0x919fd41b, ++ 0x9fd1e2b2, 0x677bd41c, 0x4fe678e2, 0x0064bff1, 0x3b63c178, 0x833846a3, ++ 0x07d5acf4, 0xad1fa37a, 0xbe623a05, 0xce5ab6ab, 0x2778f3f1, 0x7183af82, ++ 0x59e456f9, 0xdbf3e72b, 0x5d3c907a, 0x1f91372a, 0xcb7204ba, 0xe290fc42, ++ 0xaf3b1477, 0xae451ff8, 0x7edcf44b, 0xfd5a4495, 0xfa0c2798, 0x2c9ec99d, ++ 0x7c7ebb94, 0xefd04cbf, 0x123d5c6c, 0x8382e0f5, 0x7e2a19f6, 0xaf07ab43, ++ 0xd3804056, 0x51dfa3a7, 0xe762baec, 0xe635bf15, 0xf9daff0f, 0x924efc37, ++ 0xaf4837f7, 0x7fdcf5db, 0x90b7aedd, 0x4c738cfc, 0x5cdca3d6, 0x263d1dbf, ++ 0x9531e8ec, 0xc2ed2d1d, 0xf8953c0f, 0x0ac0fcdd, 0xc4c73ed1, 0xf3b447e3, ++ 0x927dfda1, 0xea2b6634, 0xdc89cbf3, 0x7858fecf, 0x5fff6577, 0xf66efc4e, ++ 0xf5e25d7f, 0x89bdffd9, 0xd68adcfc, 0xbf1b33de, 0x9ec2e5f7, 0x07f47efe, ++ 0x07f81947, 0x11f583f4, 0x1fc2cdce, 0xb708bf90, 0x0fe6affa, 0xdacca466, ++ 0xd83f85db, 0xafbfcf87, 0x50e4503f, 0x4f451bd1, 0xead0bd14, 0x1317a291, ++ 0x2279851e, 0xbe3de9f2, 0xef44bf0f, 0x89eb46db, 0xd47488ce, 0x6e38f6cf, ++ 0xd6fa4497, 0xfd084fc1, 0xda8bea09, 0xa17a286f, 0x3fa28be8, 0xe62f4225, ++ 0x9f62f468, 0x48c4fb5c, 0x248eef78, 0x4f2857ef, 0x43b27aed, 0x94ba1feb, ++ 0xb22ccc2b, 0x86728e39, 0x65025572, 0xba995ca8, 0xbe6f87d0, 0x79385fa3, ++ 0x9914f29d, 0xff89e3c4, 0x26453ca0, 0x4f2a7665, 0x311fa496, 0xfe54b8be, ++ 0xe0270cd7, 0xec032973, 0xde505a6d, 0x78c3bc26, 0xcf93d0fc, 0x497e6007, ++ 0x531a3778, 0xe133ef28, 0x3a472b0a, 0xf0a9722a, 0xe6078959, 0xa4c3bc88, ++ 0xe23a4f64, 0x8581f38b, 0x88f767d7, 0x934726cf, 0x7327e711, 0x038d0ca0, ++ 0x877f8aba, 0x3e377d26, 0x3eba4af7, 0xf49adf3e, 0xb78dc7a3, 0x276e7526, ++ 0x807e9272, 0x66cdc89d, 0xcae7bf22, 0x84e37cc5, 0x65980b5f, 0x4cbea2e4, ++ 0xa7d4ae1b, 0xa3d6e63f, 0x5e4a607d, 0xef1cf29c, 0x0df602c9, 0xf0163c3e, ++ 0x0b04f09c, 0x7ea1cde6, 0x7b6b68dc, 0xc162445e, 0xdccf45f6, 0xfc9ab874, ++ 0xbfa70d7c, 0xd7cf59b7, 0x019c047f, 0x1e0425b0, 0xf1d781ae, 0x66fa51f6, ++ 0x041fba16, 0xcc1a49e5, 0x8909ecf9, 0xfbf3e01f, 0xb0bfa12f, 0x1af30c49, ++ 0x6f0d8e65, 0x56bb425d, 0x545ad127, 0x28d81d3b, 0xbd6943a2, 0x0e5be024, ++ 0x76317bbb, 0xaf0e2ef7, 0xcc7eca4e, 0x86fd17a7, 0xd43793ec, 0x57da6e4a, ++ 0xf7f25c30, 0xef48eb48, 0xff6a49d5, 0xf57a3f84, 0xdbf70cfb, 0xdbf7977d, ++ 0xa0f57fcf, 0xefa603f7, 0xa3e9fdf0, 0xbcdfdf3b, 0xf5fb8929, 0x4ed619b1, ++ 0xc925b7eb, 0x6f22fbfc, 0x4787df40, 0x7e76d677, 0xf89773ee, 0x97ae136e, ++ 0x7bef3d10, 0xe18dddcc, 0xcf011a6e, 0x3de90c7c, 0xfe55318e, 0xf04fbe0c, ++ 0x7333499b, 0xb87cf4ab, 0xaebd0d6e, 0x24dfde36, 0x904cf129, 0xbf0d3e5e, ++ 0xf7a1574c, 0xdbd09d93, 0x703f7ea9, 0xebad7e35, 0xdb90bef0, 0xbb1c8ab9, ++ 0xd56ef255, 0xad3e487b, 0x7186c90e, 0xac27a974, 0x410be71a, 0x72479cfd, ++ 0x0faca4d9, 0xf9bfd074, 0xa57fa8b9, 0xc57d1d0a, 0x7afea18f, 0xb9eded74, ++ 0x35cbb63e, 0xba03f773, 0xde0fca52, 0x0599f8ff, 0x125e618f, 0x09ea82e4, ++ 0xade087d6, 0x0d5ac7d5, 0xbfa35a3c, 0x7ec8ff42, 0x3a003fa0, 0xe6fb46f5, ++ 0x86746638, 0xe09b49c8, 0xae7179d3, 0x8f0c69b2, 0xf07a9b27, 0xac592132, ++ 0x76f3253b, 0x4f2164e6, 0xe87421e1, 0x009f92a6, 0xc6425bce, 0xcbba744d, ++ 0x3abb8ca1, 0x73e82277, 0xdbd79d93, 0xf31eab93, 0xdac20b75, 0xd5c91cfe, ++ 0xd0c8beb9, 0x461d57fe, 0xa09772ff, 0xa3f2425b, 0x82917d87, 0xfbc171cf, ++ 0x7c3e40f4, 0x504a0f68, 0xf28ea43e, 0x3e51dcd1, 0xddf79a7d, 0xdfbcab86, ++ 0xb77df1d2, 0xe7867de6, 0x7dffaf86, 0x1a89b7c1, 0xf868e6be, 0xe703563a, ++ 0x655fb029, 0x5cbb157f, 0x8af8f750, 0x37e60738, 0x1faeda25, 0x4867e794, ++ 0x14d8179e, 0x30f67df9, 0x9e506bca, 0xa79d11d7, 0xf9be0ad4, 0x99ff93d6, ++ 0x6478768c, 0xed13be10, 0xe5cfc110, 0xd0587ae2, 0x18ff3d5f, 0x55e9edda, ++ 0xc13f7b4a, 0xfa572f77, 0x2bef40db, 0x8dbe647c, 0x6157c4b9, 0x77ef9877, ++ 0x7e7eb187, 0xc27f7f3d, 0xfb0e9bb3, 0x1f455d7a, 0x5974346a, 0x9a7d81a7, ++ 0xe1ae6bf6, 0xde6b96df, 0x5f53487f, 0x6ad781ad, 0xfbf52ae0, 0xd225b3f9, ++ 0x7ce1fcc3, 0x97ab527d, 0x27b8f95a, 0x69ce3db9, 0x2452e7f7, 0xbd2a77c5, ++ 0xe1c9509a, 0xcf6ecf39, 0x02101aad, 0xe5ccef27, 0x0b5f017a, 0x3607ef39, ++ 0x311dee97, 0xef376174, 0x2e42ee4c, 0x3dfd69fb, 0xfc1fffaf, 0x8bd69135, ++ 0x3ec97154, 0xc8370d59, 0x870dde0a, 0xac864717, 0x2e40b2ab, 0x5eba23ce, ++ 0x772379bf, 0xe45c686c, 0x917143db, 0xfda54e32, 0xc8af6ff8, 0x265fbdf8, ++ 0x34ddc9ef, 0xc53bd700, 0x979da6ba, 0xba652fe0, 0x6fe4552f, 0x5c3ee3c6, ++ 0xe81e176c, 0xc84068bd, 0x1f6d5938, 0x2fc3671c, 0x519f7e65, 0xe807f025, ++ 0xb49ccf94, 0xee16749f, 0xf509efaa, 0x1792eb56, 0xbf7dbde0, 0x9fa09794, ++ 0x8624ba3e, 0x2dfd2df6, 0xfb9dc799, 0xe6e3ddac, 0x7110dc00, 0x86dbd91f, ++ 0xb951c787, 0x6caf7657, 0x4cf631b5, 0xc8dce1f2, 0x256f58fe, 0x6cf93d3a, ++ 0x9052ee63, 0x9d93a7ef, 0x6ed7bef4, 0x78c3ab8b, 0xd681957b, 0x3d73190b, ++ 0x98f3f247, 0xdbe71d29, 0xa46f4bf9, 0xdf82b0f5, 0xe78f1e4e, 0x18560aac, ++ 0x59a49d68, 0x913ca367, 0xda38d577, 0xb97b3517, 0x52b77d28, 0x7fbfe6f9, ++ 0xb0e78957, 0x744bd75a, 0x5fcdc19f, 0x0833bed5, 0x9eaaa2e0, 0x0de2ae74, ++ 0xbee00798, 0xf6d6cfee, 0xe33ee3f5, 0xb4e561e3, 0xd3da144f, 0xcba2b079, ++ 0x652777ce, 0xb6d97b60, 0xc0b7da0c, 0x5b9f8c73, 0xe237911e, 0x28fca739, ++ 0xcfee384b, 0x5196f96e, 0x8565a75e, 0xf845ee89, 0x733bd22c, 0xcdce83ad, ++ 0x5acfa462, 0x04946724, 0xd9f57874, 0x1213724f, 0xf049b9f1, 0x3e4b13f7, ++ 0xaebe7de8, 0x9fc87e5d, 0xf8734614, 0x724fe4d5, 0x5a38c337, 0xfb4bee9e, ++ 0xe6ea6ec3, 0x7a064bae, 0xfb9babfd, 0xc44ce4b5, 0x37adfb97, 0x23d7cdff, ++ 0x10573f5f, 0x7d9b7987, 0x68dfae42, 0xbd0b882b, 0xbcf0ba87, 0x4de0e49e, ++ 0xdd3173a3, 0x229e1767, 0xe41b3ce1, 0xe6f30620, 0x05bcc5b3, 0xcec979e4, ++ 0xf5abe24e, 0x6b1e3cc9, 0x34763478, 0xd72837f2, 0xd27ec867, 0x0fe0037c, ++ 0x3f216d9f, 0x84b4c277, 0x263b471d, 0x7db237f6, 0xc3274461, 0x587f30b6, ++ 0xdd4fe61a, 0x59be51e3, 0x299f6d42, 0x143d1096, 0xe3eeffed, 0x0eff78fb, ++ 0xf7de71ed, 0xe857a077, 0xbed2867a, 0xc3e2ca28, 0xc5a4e2e0, 0x1c7e47a2, ++ 0xe0b457d5, 0xf5c2b47e, 0x8503f206, 0x6a1f63eb, 0x7203fb45, 0xed35f983, ++ 0x19bad2b8, 0x2ba31e78, 0xaffdf4bd, 0xffd92f5a, 0xbf2f555e, 0xdcebf678, ++ 0xeb5d914d, 0xdb8d9165, 0xf9ebf1a7, 0x994589bd, 0x6fae3d16, 0xd6ff598e, ++ 0xb7273a66, 0x9e306c30, 0x6f5a288b, 0x5b357e22, 0x4ddb3e2c, 0xa2c05e78, ++ 0xb2f2868f, 0x376a6fe0, 0x968f5f27, 0x983cde99, 0xa1073a4a, 0x5e9e1bac, ++ 0xb893c4f2, 0xf30cf2dd, 0xf4061b4f, 0x72e6e8bb, 0x4c97717a, 0x3aed47f9, ++ 0x9dc1c962, 0x1d762cc6, 0x58d788eb, 0xcd662c3f, 0xced89ee2, 0x1faed7df, ++ 0xd769ba3a, 0xfe740d0f, 0x1fac48bb, 0x0893af66, 0xfc25a2ef, 0x0c767d5c, ++ 0xa89f1bcf, 0x691bfe00, 0x60db3edc, 0xfdccefdc, 0xfc93114e, 0xd6f5f866, ++ 0x8f290b75, 0x33b0a8f9, 0xbf7ee2f9, 0x54ae61e3, 0xae17e79c, 0x16fa230f, ++ 0x2fef373d, 0xb9e0674f, 0xe8475cbd, 0x9406fabc, 0x865f4e0b, 0x7e9503e7, ++ 0x2ffd2e4e, 0xfb304fba, 0xc31f9879, 0xd9a28a78, 0x21a5774b, 0x715312bf, ++ 0x5769539d, 0x7d97ecb4, 0x5f983b78, 0xff3a3cc3, 0x97df9911, 0x7e44dbb2, ++ 0x813d7410, 0x9ca39c85, 0xd1a0fcbd, 0x9eff8038, 0xd7c45430, 0xb3f9e0ce, ++ 0x8f1ea0cf, 0x738996e6, 0x94fd0a66, 0x3af95273, 0x9e5acf7e, 0x53f3a24e, ++ 0xdce8c960, 0x3c6ef4d1, 0xca289dae, 0x9d1754fc, 0x6d5929bf, 0xe34b2d72, ++ 0xe79fb4fd, 0x895df984, 0xd690a9ae, 0x51315f33, 0x796ca55e, 0x8a2c3b98, ++ 0x31d8bfef, 0xeb4ff680, 0x97ec768d, 0xc9d8b38f, 0x3f3c06ed, 0x25e787a2, ++ 0x4b176e16, 0xdcde81a2, 0x4375bb2f, 0x46363ef1, 0xbfb125fb, 0xdf2141c4, ++ 0xe773c495, 0x519d5be4, 0x751b7ec1, 0x35f30aac, 0x20ffbed8, 0xb4cc5fa4, ++ 0x8bd78819, 0x1031e932, 0x8c70f567, 0x87945ef7, 0xff3b3ce0, 0xd1e37d91, ++ 0x9ed82eee, 0x5821278e, 0x901f4bfe, 0xf82058df, 0x9bf62cde, 0xf78c0015, ++ 0xe3779545, 0x7995e47a, 0xd05ca89e, 0x52bfe147, 0x8188f25f, 0xbec1ede7, ++ 0x592941a3, 0xb7ea57fa, 0x8714d2c4, 0xb764b776, 0xe7da2861, 0x05de05fb, ++ 0x1f46534b, 0x302a7901, 0xbcdee958, 0x11ae5f62, 0x891ae2e1, 0xb17be0e0, ++ 0x679f28a9, 0x851abf97, 0x2c3c7372, 0x51fd1bd0, 0x1730c2eb, 0xf1b4279d, ++ 0xe5d9dd3c, 0xd21ce9bd, 0x05935b6c, 0xbd981def, 0xed1da7b8, 0xc05b51f6, ++ 0x6b47f588, 0xbb0874d3, 0x08d1b66d, 0x1137f5bb, 0x6bec567c, 0x27941fa1, ++ 0x78b7f389, 0xfe233edb, 0xc4a78cfd, 0xf8bfcf78, 0xfbcc1f41, 0xf536a494, ++ 0xfc027f41, 0x748c93ef, 0x3f912ade, 0xf7c6dd2e, 0x2ffc2bb1, 0xbe83fe45, ++ 0x2f7c17cd, 0xcfeaf5dd, 0x914a0f51, 0xca3b83ff, 0x7ef1c80f, 0xc363be7a, ++ 0xdfdfc678, 0xf8a2728f, 0x1b97802f, 0xe3b798ec, 0x47415af0, 0x3f963e78, ++ 0xfbe00df7, 0x1ff7dae7, 0x2bbfe4a8, 0xfc16eefe, 0x226a582b, 0x8c5bbb3b, ++ 0xdd91f9b7, 0xf3bfc851, 0x803bee2f, 0x3b252beb, 0x3b3b3bc0, 0x8f4103d1, ++ 0x147f1c32, 0x45714fe1, 0x2a378e19, 0xb976fe38, 0xc657fa17, 0xf194f8f8, ++ 0xf8c5e996, 0xfef17a95, 0x30fe8a2b, 0x7d5daf41, 0xfd09beb9, 0xfba5fd42, ++ 0xbcf8c490, 0x8a3df576, 0xbdf18a9f, 0xffcc4dd5, 0x4851b56d, 0xda2fe41f, ++ 0x22c7861d, 0x4d023b15, 0x40df6fce, 0x7e15f5fb, 0x0f9ff829, 0xb47711fa, ++ 0xe6c7c83d, 0xfc35ee2e, 0xd8f1d048, 0x3ad4f88a, 0x2dd9dfa0, 0xc9149d74, ++ 0x7be43eab, 0xdf28dc8a, 0xe4c3fecb, 0xd0dc71db, 0x57fb007f, 0x17d47bbe, ++ 0x8e7ec7a1, 0x0a1fae32, 0x665e8afe, 0x7b7bde57, 0x3bb6147a, 0x0039e96f, ++ 0xb6e42dc7, 0x77de8d9b, 0xef009c63, 0xca24ebbb, 0xf3131f57, 0x5e2b63fb, ++ 0x10182a8d, 0xddb3f794, 0xf2f71124, 0x4f16987c, 0x7c14fe45, 0x1f3ced1b, ++ 0xfd9be0ac, 0xf1dbf4f0, 0xae3782b9, 0xa7ca8513, 0x4e453f42, 0x5a77f395, ++ 0x53592579, 0xb5dca5fc, 0x3b75975c, 0x3a75fb46, 0x27f6d73c, 0x62e3a0e2, ++ 0x2c6b791f, 0xe5fe79e3, 0xe755fb09, 0x0c8b1884, 0xdf8a37f5, 0x7d6a9f80, ++ 0x3f69bf88, 0x9f70e677, 0x52797e46, 0xcf78d07a, 0x16635ab0, 0xaa7c5bf4, ++ 0xe3de3c69, 0x379dc4a6, 0xad90157f, 0xc5da9f98, 0x7229b7f7, 0x3f6e7c52, ++ 0x38897fc9, 0xc8ff94cf, 0x50c3b907, 0xa06f7fce, 0x15fc9c75, 0xcf188ce3, ++ 0x6b3cdbcf, 0xcf019228, 0x3f3da03d, 0x087329bd, 0x8b60493f, 0x1fe7869b, ++ 0xed313d36, 0xbb3e786e, 0x187ba64e, 0xdbd41fb0, 0x508607fc, 0x5878f53e, ++ 0x8c48ee73, 0x6d941fdb, 0xda8fb718, 0xb610f99c, 0x1ee9651f, 0x6c67974d, ++ 0xadd8218a, 0x505f92b7, 0xdf655ce2, 0xf381a55f, 0xd70a647d, 0xae14f4a7, ++ 0x9229e94f, 0xd957efd8, 0x5bdfd707, 0x3dd18437, 0x67467928, 0xb7bf006d, ++ 0x15e69e27, 0xca3c4665, 0x2950e748, 0x646b9b0e, 0xf4c1c4e6, 0xcf089cdc, ++ 0x1e9a1a0f, 0xf071ff40, 0xde3a4b01, 0xcbe4c87f, 0xfc780b43, 0x6319d7cc, ++ 0x319eea98, 0x29118f05, 0xfdb5ce5c, 0xe237ef29, 0xe74ec1bc, 0xd3fde90d, ++ 0x0d3f7fcb, 0x2de9dffd, 0xee38edbd, 0xe8c27b93, 0x8349c0bc, 0xef939efa, ++ 0x7b4b8e7a, 0x873949fe, 0x9c45213a, 0x9b711717, 0x3ad7ef22, 0x553ec1bf, ++ 0xd6bc7bef, 0x1573a53e, 0x5b71ce8c, 0x777d1853, 0x3bb7c46c, 0x6160df71, ++ 0xe786c98d, 0xdca04e5e, 0x6ed5fae3, 0x34a79f99, 0xb1383d73, 0xd79d087b, ++ 0xc394fc2d, 0x1f92b585, 0x7fef17cf, 0x9fda61fc, 0x4ae20730, 0x1ede6adc, ++ 0x7c79af2f, 0x45c3aa1a, 0x9e257797, 0x85b8bfcf, 0x70e8a7ef, 0x9dc1c2cf, ++ 0x5d9d1207, 0x763fc9c7, 0x1de4ac7c, 0x9f514c1e, 0xace8531b, 0x04de97cc, ++ 0x383e1879, 0x2a2fb748, 0x7c7c52e6, 0xe54bc2ae, 0xead8e905, 0x16c72851, ++ 0x780f9d2b, 0x1909eebd, 0xd92ac1ef, 0xe7197e95, 0xad2323bd, 0x17c9ef74, ++ 0xdd684b15, 0x39455cf4, 0x95bf0a95, 0xbbcddbbc, 0x2fbde81a, 0xe3d486ea, ++ 0x2237db79, 0xdbfec2ad, 0x576be53b, 0x719588e7, 0xf390799d, 0xccfbc157, ++ 0x38515996, 0x636786ae, 0x5f2047ea, 0x8c36ac23, 0xbec48af7, 0x3cb59691, ++ 0xb6653e8e, 0xf81130be, 0x9ddd6a7b, 0xdb1f7871, 0xd3a9869c, 0x1ee179f0, ++ 0xbff186c9, 0x28e4cf6b, 0xae7e979c, 0xf3c28e6f, 0x55af9f50, 0xe9f951ce, ++ 0xcc8d23ef, 0xfb627761, 0x733d0191, 0x6aa5f1a6, 0xe7119394, 0xf59e74f4, ++ 0xbca73c2c, 0xca70e5c8, 0x0c4fc08b, 0xf39913ee, 0xb4a7cf1a, 0xbcc56bcf, ++ 0xf718946e, 0x657629c7, 0x679e82dd, 0x4fcfe70f, 0x0939dbae, 0xc9bd3bfb, ++ 0xbfbc4360, 0xfea064d8, 0x4c7cc3e7, 0xda9ef807, 0x0839e7c2, 0xf4f8fce3, ++ 0x999f3e16, 0x33e7cb5f, 0x6e0d0b25, 0x2d53fe7e, 0xed21d98f, 0x2e9ebee8, ++ 0xef98ffee, 0x0f9be3e6, 0xabc7127e, 0x5668db95, 0xbec6e74b, 0xad50feef, ++ 0xb1a7bedc, 0xdaf2ed0f, 0x7a089c95, 0xbca3bea2, 0x7f30f22a, 0xb7a75f2d, ++ 0xa167a6d7, 0xa1f229dc, 0xd2aac7bd, 0x83fdf8c8, 0xda1770ba, 0x4e91c981, ++ 0x3b87fa03, 0x9163cd1d, 0xb953232c, 0x75b3953d, 0xc6e73c6e, 0xde9d4d2a, ++ 0xd84a739b, 0xc654d2df, 0xb54c59ef, 0xe29bfdf1, 0xc25297bc, 0x6fd05240, ++ 0xffb08e4f, 0xfc7aef03, 0x9337ca47, 0x93cf20f4, 0xe81fd947, 0xdbec62e9, ++ 0xf4932b94, 0x43c99e30, 0x007bbbec, 0xb7fd657c, 0x7b26febc, 0xf06001a6, ++ 0x858c7705, 0xeea96efa, 0xc199294b, 0x1cde9cef, 0x83e3829f, 0xf3e35fe7, ++ 0x37ef58a4, 0xf3899658, 0xd6a4175f, 0x82d24b41, 0x63dfdfed, 0x33bafa39, ++ 0x581b3708, 0xa00fde2a, 0xf3bfc76f, 0xadd53b32, 0x79e4ed4b, 0x682b6301, ++ 0x9f8f9e7f, 0x8f1f81bb, 0x45cf0e39, 0x502b7971, 0x6954e1ce, 0xf8b8e1ce, ++ 0x7ce53379, 0xa9fe7294, 0xd8fcf07f, 0x7e72efba, 0xff8182ec, 0xadc9247d, ++ 0xd525ff3e, 0xedee89ff, 0xe6b1f4a9, 0xfa83e230, 0xde094d5c, 0x72740723, ++ 0x44096abf, 0xbd179f02, 0x317a4118, 0xd077894f, 0xde0d0f59, 0xf812c03b, ++ 0x8407837e, 0x60ac9e3c, 0x71e97abd, 0x2fdef55f, 0xe6c780f4, 0x480def30, ++ 0xa1dd62a7, 0xd44e45d4, 0x8c28cae3, 0x24bfce37, 0xfb4226bb, 0xb2a71162, ++ 0x1ec2b14d, 0xa05b81c8, 0xffad31be, 0x193ff446, 0x389e3ca9, 0xfd481697, ++ 0x3493da25, 0x76822f3e, 0x672e6fb4, 0xd8b1add9, 0x87f6dcee, 0xbe01cd7b, ++ 0x78dbe099, 0xe836eb1e, 0xee9db873, 0xad32629d, 0x3df9fb33, 0x8be67a48, ++ 0x55fde3b2, 0x738aa44f, 0x501e7443, 0xf7428fe1, 0x4f80fc0e, 0x33ab1c63, ++ 0x57ce0333, 0xf475b3fb, 0xbe14a8f7, 0x2e17f728, 0x2cf3cdda, 0xc0521674, ++ 0x693a2f98, 0xab8f7f16, 0x8b7c3f83, 0x475054e2, 0xaceeca9f, 0x7fb9d59b, ++ 0x88c1be1c, 0x7ed8ff5d, 0xe154def2, 0x7a59d31f, 0x458cfde8, 0x3938cda2, ++ 0x54f789cf, 0xd3358a2d, 0xd68b23bd, 0xc43f24f7, 0x68584bcc, 0x862eb63b, ++ 0x9a6564e4, 0x579ff44c, 0xa0fee8c7, 0xda24badc, 0xceb13937, 0x5b54654e, ++ 0xfd3f3d02, 0xdc193bc2, 0xe4fe711e, 0x18fc77fe, 0xdff49fda, 0x5d64a97d, ++ 0x11e913dd, 0xfdc83e74, 0x918b22d9, 0x5f7a0bf2, 0xa7ed2b7f, 0x1f99946c, ++ 0xef07a9e0, 0xe57d2034, 0xdad72e70, 0xba1521fb, 0xba3f0499, 0xba722fba, ++ 0xbeeaefa8, 0xf86269c8, 0x4ee723d3, 0xf7b5bc44, 0x351c3e44, 0x4ae491be, ++ 0x7c47a73e, 0x0c48b74d, 0x969dc2af, 0xd4c3e6a7, 0x30d86aa9, 0xbfb24bfa, ++ 0x7e5ad186, 0x6fce0333, 0xf3f56e4d, 0xdf855327, 0x5ffacfe8, 0x48cd9ef5, ++ 0x1eb5e933, 0x780551ef, 0x1367b89a, 0xd78c39e3, 0x244dba2f, 0x09870fb7, ++ 0x091949ba, 0xfff97e78, 0xb553fbf7, 0xef6aa5f7, 0xcb71bd43, 0xb03c1522, ++ 0xf6aa17f6, 0x532dd537, 0x5607a7d5, 0x3487eaa9, 0x670546fe, 0x6aa33d36, ++ 0x46c8ec3f, 0xe688fd55, 0x51faaaad, 0xe0a876a7, 0xa8ff5b9b, 0xdb4b7f6a, ++ 0xc59c155e, 0xcfb551de, 0x82a07f36, 0x513ed9c7, 0xe135bfb5, 0x36feaab8, ++ 0xfd5559e7, 0x54977e84, 0xf7a31af0, 0xa5ea2a78, 0xf7aa5feb, 0xafe73126, ++ 0xe9d67ef1, 0x002b9d0e, 0xfd8ae7f0, 0x92d77210, 0x6f71e362, 0x4be7462f, ++ 0x03a3c9c7, 0xfc757724, 0xfd6a4aef, 0xc7acfe93, 0xf639f98d, 0x666f3f2a, ++ 0x1f4fb885, 0xb768bdf2, 0xddfe8599, 0x9b1c98b4, 0x24f58e0a, 0xcfc7daa8, ++ 0x13eaaa70, 0xf554fdbd, 0x2a5d73c9, 0xb87ca538, 0x25f77daa, 0xe69c156e, ++ 0xefb551cb, 0xc151e559, 0xa8666bbd, 0xeb5df7da, 0xf7f7d555, 0xdfd555cf, ++ 0x055ca5b8, 0xa25dac0f, 0x9d537f6a, 0x1e9f554f, 0x0fd552a8, 0xc151ac69, ++ 0x556b4d99, 0xf11d87ed, 0x3447eaab, 0x8fd5516f, 0x82ab553a, 0x53ad6e6f, ++ 0x2da5bfb5, 0xd8b382a0, 0x6cfb5541, 0x782afbf3, 0x5563ed9c, 0x8e135bfb, ++ 0x736feaa9, 0x2bd5569e, 0x7e84c8f1, 0x8b9faa5f, 0xf5d724f8, 0xf6fdea8d, ++ 0x4877637b, 0xbb294e74, 0x5ee50f7b, 0x1930e6c3, 0xe50f19e3, 0x41b8ec83, ++ 0x1596ec10, 0xf9db79cf, 0xca3c99be, 0x6e28392b, 0xc4e29721, 0xe7e03c7d, ++ 0x957670a3, 0x6ff18696, 0xeace3044, 0xf5c86576, 0xbb9359c7, 0x4963c233, ++ 0xeef8ef77, 0xd88f38b1, 0x47ee9e3e, 0x8895be66, 0xdeef7287, 0xd3ac61bb, ++ 0x336fd0fb, 0x90fa629f, 0x5860eeb8, 0x57c1b74d, 0x66dfcf99, 0x1ef0c73e, ++ 0x457ef6d6, 0x38ff02fe, 0xfe90a2f4, 0x003cc357, 0x4d60feff, 0xc40de805, ++ 0xb0a9bf40, 0x22a6bc11, 0x2b27e081, 0xadae549c, 0x33e547e8, 0x5faa2e15, ++ 0xe09c3157, 0x04dc2ae7, 0xa8722bfb, 0xa1e158dc, 0x662a9be7, 0xcc02fc10, ++ 0x02dcb18b, 0xb72c64f3, 0xeb177cc2, 0x17fcc1b7, 0x7c2a97e1, 0x5456d654, ++ 0x151df3d1, 0xaaef0435, 0x2bf04b58, 0xeb2a7e15, 0xf950b62a, 0xaa5a8ac7, ++ 0x23a8afaf, 0x008a8df8, 0x468a81c1, 0x3456f782, 0xe2bfbc11, 0x2a07c108, ++ 0xac6ca99a, 0xdbe54538, 0x7f54ad15, 0xe08da2a8, 0xf1d4bf20, 0x5ef1132d, ++ 0xe5039091, 0xce42879e, 0xe4467652, 0x1c848b6d, 0xe877ef06, 0xc5f711b3, ++ 0xf49ca266, 0xf4393923, 0xed71e25d, 0xe9294b7c, 0xf5ca395c, 0xacfbf6c2, ++ 0xa9d8e7b4, 0x3e01ef3e, 0xe217bd3f, 0x503f5c57, 0x2c5fadce, 0xc33dd037, ++ 0xe31dce78, 0x9fe58b9f, 0x70c3bc53, 0xfe441c3d, 0xdd137abe, 0x95e0a6ab, ++ 0xc032f787, 0x69f109fb, 0x6b375cfc, 0xab3ad034, 0x3b65b99e, 0xbe7e739d, ++ 0x9f9f3c3b, 0x7cd1f3a2, 0x739f9239, 0xdde71fee, 0x962fcf88, 0x9d8039cf, ++ 0xb45cd917, 0x0a6b98ce, 0xad93fdd0, 0xe7ca6507, 0x328f4575, 0xcbbccfb1, ++ 0x774e37fa, 0xe73ab8c3, 0x07dd32df, 0x32c1aef6, 0xbb04f303, 0xe779f3bb, ++ 0x553aeeee, 0x779c6af9, 0xb5f3e217, 0x0ea67ca5, 0x4ff5f848, 0x7f70be16, ++ 0x7c9e705a, 0x21354e07, 0x9ccc9dfe, 0xc8f7da06, 0x49a56fdc, 0x97a9bf78, ++ 0x47cce9e0, 0xef58ff65, 0xbbdbd41e, 0xef609f98, 0x676a5348, 0xd5e2d2e3, ++ 0x146af028, 0xe7e528f8, 0x713fde71, 0xd784dcbc, 0xed6e23bb, 0xf052e383, ++ 0xd3ce2dea, 0xcfad624f, 0xef5f7e21, 0xea45b2f9, 0xfe3e51d9, 0x89117203, ++ 0xc7681569, 0x12a47d70, 0x7d40fa37, 0x9cfc83e5, 0x791722bf, 0xf7c40098, ++ 0x1ce8921e, 0x404e5040, 0xe51e703e, 0x8273a568, 0x48272720, 0x74c8464e, ++ 0x9d5dfe1e, 0xeb448fbf, 0x988c73cf, 0x80722837, 0x5ae8f47c, 0xf9c54a0e, ++ 0xc839e504, 0x87c817d7, 0xd61b5e2f, 0xf655e90f, 0xd22708c6, 0xcfc752ab, ++ 0x96def92d, 0x1627dff9, 0xc51e5ca6, 0x7a6413ef, 0x4af30b97, 0x4b7ce2b9, ++ 0x6c96cc83, 0x5acec4ef, 0xfd1f3c9d, 0xefbf026e, 0x3eb352af, 0xfe727263, ++ 0xaf9c9c99, 0x2c9e168b, 0x77ff0196, 0xf3a69ef7, 0xffbb4a2e, 0x9f947d03, ++ 0x008000f2, 0x00000000, 0x00088b1f, 0x00000000, 0x7dedff00, 0xd554780b, ++ 0x333ef0b5, 0x4c991e67, 0x3335e4c2, 0x4c933279, 0x49309e42, 0x3ac40680, ++ 0xd3c30109, 0x248255e1, 0x51a0d832, 0x5a403302, 0x99deaf63, 0xd2091e10, ++ 0x042d60db, 0x7c509d45, 0x37bdaf5c, 0x46c1a45a, 0xc140826f, 0x1f50314b, ++ 0x80dadbd8, 0x10ab6ad6, 0x2da7f684, 0x6b5affad, 0x99cc939f, 0xedad404c, ++ 0xfdfffdff, 0x9b7c7df3, 0xfb3ef67d, 0xaf7af6b1, 0xfa7ccfb5, 0xc4ddfc29, ++ 0xd5e9b798, 0x6302473c, 0xeef5ca9f, 0xc65d33b3, 0xe65cbae1, 0x92c604db, ++ 0xabfaab18, 0xed05d3da, 0xa78c6d6a, 0x18dfa433, 0x49b18a9b, 0xecc8fd8c, ++ 0xbf41b589, 0x6ef9c43f, 0xf9416553, 0x07ef75d5, 0x3af9d5e0, 0x50a598db, ++ 0xbe76300e, 0xe3cf4a17, 0xf6832d26, 0xca9399db, 0xf2a6e63a, 0x32d0164e, ++ 0xc0ee6335, 0x64cb2d0e, 0x45d66eec, 0x7d96d7cf, 0x8a60ccdd, 0x0c9e543b, ++ 0x7eb037ac, 0x8365ee7a, 0x633b5695, 0x8f9b5a4b, 0x8b631958, 0x48cc77da, ++ 0x30b631b6, 0x9608f2b8, 0xef09f60b, 0x4bcca007, 0x5d71d8f2, 0x736f8203, ++ 0xeb7fcc0a, 0x539be5b3, 0x757cf9e1, 0x44d2d26f, 0xd4bff178, 0x5ea027ce, ++ 0x3a973223, 0x7fbee47e, 0xd9e4f66d, 0x5cbee126, 0x6c752fb4, 0xf6078e55, ++ 0x7b2eb35f, 0xca10a78c, 0xc025cc8d, 0xe92f8338, 0x3d617b82, 0xc11b16d9, ++ 0xead97e63, 0xbac2a55f, 0x1b783899, 0xcbef7683, 0x766df8ba, 0xe19b97dc, ++ 0x6317053e, 0x809f304d, 0x7f094373, 0xc644e2b9, 0x13833356, 0x0356fdfb, ++ 0xdbfea04f, 0xc16c1674, 0xac5cc0ba, 0x1a0bb184, 0x0630ab63, 0xd63c32da, ++ 0x5dcf5812, 0x4185b02c, 0xecf557bb, 0xd3538478, 0xf70b8f58, 0x5dbbf77b, ++ 0xb9e18a5b, 0x219822a6, 0x679a38c0, 0x071c4e74, 0x5fbd3366, 0x0f32f300, ++ 0x9e1a34fb, 0x78431f33, 0x3b8e0bfe, 0x84bae461, 0x147fa3b2, 0x69d31962, ++ 0xf30f4059, 0x9b182a07, 0x5205e30c, 0x0016c1b4, 0x36820b51, 0xdb71e70b, ++ 0xe391c67c, 0x7bd6949f, 0x69b02fec, 0xf6004380, 0x691084f3, 0x51fc9f9e, ++ 0x18f30f18, 0xfdc1e786, 0xe68ccc07, 0xd3b36159, 0x31f3c879, 0xbb9a40e3, ++ 0xe0cef008, 0x87cf0db9, 0xcc551359, 0x137ad8cc, 0x3cc61ffc, 0x038dff66, ++ 0xd4fe67cf, 0x2f3c34b6, 0x8f1a5fc0, 0x3e08557d, 0xd975c761, 0x593f5802, ++ 0xe006776e, 0xd36602f1, 0x52dcb9e0, 0xb83393f6, 0xc6f45b8e, 0x6c94355e, ++ 0x81a3e69a, 0xf61f3a5c, 0x6e152669, 0x19da1936, 0x1b4d879f, 0xf3bce223, ++ 0x8b761779, 0xef87dbd8, 0xe0d4e633, 0x2fd8f2fa, 0xf9ec7864, 0x95f68134, ++ 0x67408beb, 0x847eb1b8, 0x30b3689f, 0x7c0bd728, 0x0dd3ebff, 0xb623a441, ++ 0xa7f68f3d, 0xc379f3d5, 0x3354b7df, 0xeb4bd0e6, 0x1ec97f84, 0x0ee4733d, ++ 0x4deb53d7, 0xcfba7a8a, 0xb63fe8aa, 0xb768a6c9, 0xed157207, 0x454ead59, ++ 0x4cbdbb3d, 0x875c7fd1, 0x0bcf514b, 0x17fa2956, 0xd456ed3c, 0x15aaba8b, ++ 0x7b7427fd, 0xbdc5ed14, 0xd2f68af5, 0x7d453e63, 0xa2937f52, 0x04ce57ff, ++ 0x0653ed14, 0x37ed155a, 0xa8aed07c, 0xa1d838df, 0x95d37fe8, 0x9cbda2a0, ++ 0x7da2abfd, 0x4539feba, 0xa0e9867d, 0x51e3ffa2, 0xd019e3b1, 0x3ed6cdcf, ++ 0xb659f3c5, 0xe6f78ae3, 0xd4529ee4, 0x39ce971f, 0x7440ccb0, 0x1d4ab3b1, ++ 0xf338c2d0, 0xc62b6f9c, 0xfcf93d61, 0xb3f8a3fc, 0xbafd8ec7, 0x63e4f918, ++ 0xe23b41aa, 0x4a6d4dad, 0x94763a41, 0x6804382d, 0xeb5c72c6, 0xe5bd902a, ++ 0x8438ed56, 0xb9fbbe65, 0x561f200a, 0x10ea7d58, 0x173de396, 0xe638602b, ++ 0x057b8fac, 0xf15f12cb, 0xa52e0b74, 0x582bc169, 0x9bac0e4e, 0xf1f57c8e, ++ 0x48f9b5fb, 0x32f1b147, 0x3f08ba7e, 0x4455931b, 0x8ccb8dcf, 0xe63fe441, ++ 0x03228c1b, 0xaefe613e, 0x8f1b1379, 0x962b4965, 0x0b3d7ead, 0xe2db196a, ++ 0xf36e5467, 0x0730589b, 0xa56fd9d0, 0x55a9e37a, 0xce309955, 0x04d15ad8, ++ 0x71a660db, 0x60db25f7, 0xda0fcb7c, 0x1939f773, 0x97eda5fb, 0xe7b0350b, ++ 0xb2df2cd8, 0x33ac38ce, 0x8b8062d7, 0xa6c46019, 0x7edfb632, 0x38503b8f, ++ 0xe1d73eb2, 0x41f215fe, 0xb9e57626, 0x6dc78663, 0x53adf8ab, 0x36084265, ++ 0xdc030fba, 0xe8192577, 0x3b97ac3d, 0xaeb8cb3e, 0xc0df910f, 0x04575f73, ++ 0x728f3e3a, 0x57f61263, 0x2dc2bf11, 0xf859b9e1, 0xc88b31b1, 0x96006302, ++ 0x9d34a6bb, 0x679713bd, 0x9fc8080a, 0x1f7855d8, 0x760a4af8, 0x4dfaa2ca, ++ 0x6327a806, 0x2198c6dd, 0xe71573db, 0x3b1878b5, 0xc93f8217, 0x2efacaf5, ++ 0xc739f380, 0x2b347af0, 0xf6110154, 0xdbbef9a0, 0xf67984e9, 0xa17ec2d4, ++ 0x56cb4bbe, 0xfb870bb8, 0x9231538d, 0xb9d8b7ef, 0x1757673c, 0x60c41739, ++ 0x61e7ef9d, 0xf7d2e0ff, 0xff0edc60, 0xea532a15, 0xf807827d, 0xedc6a59b, ++ 0x4d3f400c, 0x70a3c00b, 0xed123c24, 0xf341c122, 0x0d82bdca, 0x36ecb9fa, ++ 0x26a52f1a, 0xad4efb48, 0xd6437187, 0x8203156f, 0xef5b9e09, 0x3eb8080b, ++ 0x64edc9ab, 0x9bd31ef0, 0x4837ff09, 0xfa6d6134, 0x4af7d2eb, 0xdbbf5c61, ++ 0x7334fd89, 0x110b3f00, 0x83133ea0, 0xc4da52f2, 0xf9c22c31, 0x406ea5c8, ++ 0xa3a55cc5, 0x7c66c7b7, 0xe2f247cb, 0x1b2da356, 0x65f1fbf0, 0x08ceeac6, ++ 0xf824b9e3, 0xce578d6c, 0x7873566f, 0x92fb7cc8, 0x4ca39f89, 0x98e21bc7, ++ 0x486f8f82, 0xd6b9689f, 0x7a1d2d7a, 0xef5909e6, 0x04c7982e, 0xb2feebe3, ++ 0xd7fb84ce, 0xf34dcc09, 0x749f9c89, 0x89db9a3e, 0x39f8447a, 0x6047c08e, ++ 0x104a633d, 0x2d82063f, 0x5aba8740, 0x26f513ad, 0x116f3fcb, 0xb0a73650, ++ 0x8bf90176, 0x98f2bd25, 0xf44d7288, 0x1b5ca1e4, 0xe0ebbeb1, 0xb27e7ca5, ++ 0x2f3f0e7c, 0x6f59a7cd, 0xffbc2395, 0x1f50c34b, 0x293c7f5b, 0x4f8213de, ++ 0x2cbc25ab, 0xa46aed63, 0x8baca98f, 0x9fac69ca, 0x41b2afca, 0x24cc5d2a, ++ 0x9cc15962, 0x37325654, 0x8f993395, 0x4ed62aca, 0x45d66ce5, 0x4fd65ce5, ++ 0x48367ce5, 0x34999ba5, 0xf9042e58, 0xe662e58d, 0xcc6bf2a6, 0x88fde547, ++ 0xd5cf80bf, 0xb7ea9dac, 0xbb2a2eb2, 0xc06cee81, 0x7e045ecf, 0xf00f6587, ++ 0x065f2c39, 0xaf65873e, 0xc06cc6df, 0x73f90ef7, 0x77ec3ca9, 0x5fd47952, ++ 0xbf31e546, 0xeabdfa8b, 0x84f2a2af, 0x49e54ddf, 0xfd95357f, 0x3bf50f7e, ++ 0xf2a7afed, 0xca8fbf75, 0x544dfd37, 0xa807f19e, 0x95bfb9fc, 0xa05a71ca, ++ 0xee6f8467, 0x3842f140, 0xb5778cff, 0xe7f01b2e, 0x7a5f12e3, 0x5efaa5c5, ++ 0x373c44de, 0x1e21d315, 0x10106e54, 0x2ab92cff, 0x6dca1057, 0xaf85ebb9, ++ 0x24f5b943, 0x9674dfd7, 0x2d0fd218, 0x0d828d1d, 0x0616edc6, 0x9670d1d4, ++ 0xeabe778f, 0x2e7f03d6, 0xa29b61ef, 0xad7f589d, 0xd7780f5d, 0x760df1a9, ++ 0xf6c3fb42, 0xd4fb529f, 0x7bbfd398, 0x7da9d786, 0x62d661ca, 0x9d13fa82, ++ 0x0513dba7, 0x7e640ebe, 0xc37f61ff, 0x3ae22cdd, 0xb29f9c39, 0x99ca00b3, ++ 0xa48d7bc1, 0x9c77175f, 0x7d41562b, 0x04b1934a, 0x7ed0aa94, 0xa3f788bd, ++ 0x976f0bf5, 0xceb3dbdf, 0xd87082dc, 0xe5a83efa, 0x6b2328f0, 0xa17d78a0, ++ 0x67d55c72, 0xafa99f9b, 0x3f687f31, 0x19e31ae1, 0xd82f5db2, 0xe3cffe93, ++ 0x6b7e3879, 0x39f77d3e, 0x47d89a95, 0x7dd3ca3c, 0x0ccf9c71, 0x17ba7e82, ++ 0x5e2fbdd6, 0x6839b7aa, 0xf10fc85f, 0xcb6eb6dc, 0xbea0060c, 0xfebdca2f, ++ 0x5b7fb638, 0x4d0bdce5, 0x6d9e0cfb, 0x38775479, 0xbfb0daf7, 0xe01e372f, ++ 0xe5cd119e, 0x6fb4ced2, 0xe842d945, 0xdb9dacff, 0x5da6bb63, 0x3b44efee, ++ 0xb2c555a2, 0xadbdbde1, 0xc2e5b7b7, 0x0edfdf38, 0xc7d403fa, 0x96d758dc, ++ 0x6d99ed0d, 0x896ac9aa, 0xbe3ae1c7, 0xc9eebdbf, 0xa55fa86d, 0xc0e7c7e5, ++ 0xbf1259b8, 0x281848cc, 0xbe7800de, 0x23eacb53, 0x240ff3c9, 0x6183a97a, ++ 0x665e01ce, 0x3afaf8e8, 0x543aac35, 0x3933e9de, 0xe6c9cd7f, 0x04dcd4eb, ++ 0x74fc86f8, 0x11b821ac, 0xd63e5ff6, 0x6f31f048, 0x578107d2, 0x9fda7333, ++ 0xed0cdd4e, 0x272a3de6, 0xa5a274aa, 0xfa8359a1, 0x85d632fe, 0xf029d8f4, ++ 0x5ce903f7, 0x2145042f, 0x10f8f913, 0x599ff7ff, 0xeb8710ea, 0x8080ead6, ++ 0xd8f97bf6, 0xe5006106, 0x82ddda4f, 0xb9b4f80d, 0x627823da, 0x51f03ed0, ++ 0x47b6457b, 0x5a7584cc, 0x50fde06b, 0x927992fd, 0xde615cf1, 0xf3d22eea, ++ 0x7ce84958, 0x0e1cd9c5, 0x264ec19b, 0x9693757d, 0xaf0e15d6, 0x988a9ce8, ++ 0x73e1a4cc, 0x97ef6f0c, 0x236fb4e0, 0x3074814c, 0x27cddb85, 0xfd21489f, ++ 0x834efe71, 0x93a7ed0b, 0xa92bf23b, 0x1754e0fe, 0x9f2791ea, 0xcb133a98, ++ 0xa6ce0ff9, 0x7605277e, 0xf9e1ed0c, 0xe22ade0f, 0x582c8cf3, 0x56778e17, ++ 0xff38f84b, 0xf7a5bbc1, 0xed8955bf, 0xbfc0aa65, 0xd6591da1, 0xda344cf2, ++ 0x9e6353c9, 0xa4f2c54f, 0x0fb1a06a, 0xc4c5bfe6, 0xd9e28a7e, 0xedf896dd, ++ 0x82cff82a, 0xd41a991d, 0x33334baf, 0x988bbd69, 0x7a00e88b, 0xed375d90, ++ 0x4057fee9, 0xed5f6293, 0x660e9c1a, 0x9b75732e, 0xd159630e, 0xf044aceb, ++ 0x1f731e55, 0xbf6672c6, 0x97d512af, 0x87ed33aa, 0xd7287cb1, 0x79f08a53, ++ 0xf6bf9fea, 0x1f5053fc, 0x09a37f7b, 0xc6c720f5, 0x917b5981, 0x186b8e1e, ++ 0x32eec3d2, 0x111abb5f, 0x851edf58, 0x957921fc, 0x5cf2854a, 0xc38f6f67, ++ 0x43956eba, 0xbee17685, 0xda7af6b8, 0x2181b677, 0x39055f1c, 0xdbb17884, ++ 0xf4851ed4, 0xe7497404, 0xf1c99e50, 0x33e71752, 0x28f3e1c5, 0x9fa87cfe, ++ 0x1e6fd781, 0x271ed7ea, 0x02893cd0, 0x36a09fd9, 0xc920de90, 0x2f805def, ++ 0x639817a8, 0xd7e89d3c, 0xf4e2edd9, 0xbc72301f, 0x405beec0, 0x021b457f, ++ 0xf76d68e1, 0xa0fb21cd, 0x840c0c46, 0x062005ea, 0x41b45c71, 0xcea03cf0, ++ 0x29debed0, 0x19f03af0, 0xa1fe175a, 0x346ac31f, 0xcb1d2277, 0x947b37eb, ++ 0x163ee1e3, 0x93df871a, 0xda41aef1, 0x7f84bd57, 0x3c7c3dbb, 0x326bbd79, ++ 0x023f5c6d, 0x9332adb1, 0x03d7c6fe, 0xac8550fb, 0xed1fa427, 0xccdd686f, ++ 0x00bc4569, 0x8e90123a, 0xe8624a10, 0x5744ebfe, 0xffae2c54, 0xdf883dc0, ++ 0x6047c8b1, 0x9be9df9d, 0x0d3a27a2, 0xa67347db, 0x1169e69d, 0xedea027d, ++ 0x823c6bb3, 0x02d3f60b, 0x8c768cf4, 0xd39baa59, 0x66d79244, 0x2682ede3, ++ 0xb4e6bf64, 0xb3d3923a, 0x1acd3dab, 0x65d9c738, 0xefc44ed1, 0x936bac39, ++ 0x61f7d389, 0x1c6fac07, 0x3233fa1b, 0x71d03f79, 0xe9c55d5f, 0x3a6ff872, ++ 0x43cf2deb, 0x1dff79f9, 0x768e9173, 0x31f66b7e, 0x6e6a7f5c, 0x78b21f67, ++ 0xee7e45f7, 0x75fb96ac, 0xf7c47b1c, 0xd691f742, 0x3e10f508, 0xaca0d293, ++ 0xea283e03, 0x84595e32, 0xb7f438fa, 0x670ba2a9, 0x8cdf20e7, 0x3f389955, ++ 0x638b080f, 0x1195f246, 0x5fc12578, 0x33a79f3e, 0x66fe741d, 0x81ce8aa3, ++ 0x4bf53a0d, 0xcb9da462, 0xb41304e7, 0x018f9900, 0xaa54b578, 0xcf1d8283, ++ 0xdea3fa0b, 0xf092c83b, 0xa9cfc35c, 0x9d9b6353, 0x877a7c83, 0x1b04f4ca, ++ 0x33905709, 0xbb5e906f, 0xe1da9123, 0x7f27a8b9, 0xef238c1f, 0xaea91d5b, ++ 0xf5eb8f3c, 0x2ff5947f, 0x7c8fb1c8, 0x78b69a9e, 0x2fac1e76, 0xfce8c7d5, ++ 0xddc7dbc3, 0xb2573ca7, 0x7da2273f, 0x5fbd82c6, 0xa7673ce0, 0xfb24abed, ++ 0x655cec27, 0x8848cbbc, 0xb36a172c, 0x44667d38, 0x91574f3b, 0x9e92215e, ++ 0x93174ee0, 0x81a2ed42, 0xdc076e4c, 0xc92323f4, 0x3eaef621, 0xd9d72288, ++ 0xee00ffdb, 0x0ab2e2b3, 0x391d918f, 0xb3bbe871, 0xd3f19ca1, 0x17ffd7d7, ++ 0x17f19bf4, 0x7f3e2963, 0x42cc0d91, 0x18e04887, 0x6f5019d8, 0x76c9f8fe, ++ 0xd4b49474, 0xddca2730, 0x726575a1, 0x4d63f779, 0x35fc4dd0, 0x897b644f, ++ 0x2e65820f, 0xd3b70b9f, 0xbc4e74d5, 0xda6bb98d, 0x38b46ec9, 0xa357810a, ++ 0x396baf5b, 0xb48fc5f1, 0x0b8efd0c, 0x729a6dab, 0x1ac2ffd8, 0xd225669b, ++ 0x50aac8b3, 0xed54588f, 0x6a8be7a4, 0x9eb9fc9c, 0xed5c5f3f, 0x6b8be7a2, ++ 0x11b9fc5c, 0x963c039e, 0xfdfb0754, 0x6312ee30, 0x7e854dbc, 0x6f371af0, ++ 0xf6a3a2bf, 0x380f6013, 0x510de500, 0xedf7e241, 0x5ce8a81f, 0x840c1a5b, ++ 0x9298bad7, 0xdf843663, 0xf513954a, 0xc8ba5d28, 0xa8ef504c, 0xd0d50776, ++ 0x4f6b30fe, 0xe8bdfdc6, 0xfa426f59, 0x344d317b, 0x745efee1, 0xf08cdd81, ++ 0xd98317ab, 0xa1c90976, 0x5a5d62fe, 0xfde91b70, 0xab027f1c, 0x0567e4f4, ++ 0xacfc875d, 0xa48a556c, 0xfd3970c7, 0x4189edc8, 0x3ab1e3e4, 0x08b9abe7, ++ 0x79f827df, 0x8a2fa77f, 0xcbef33c6, 0xd1d9460c, 0x57c10c8e, 0x7b77f486, ++ 0x1ab3b639, 0xe7f9c266, 0xa367b8d6, 0x87b2d91e, 0x030d9139, 0x70fbd37d, ++ 0x0ecfb49e, 0x04cae9cf, 0x9d3bb7ac, 0x0a004e6a, 0xd9e2d0be, 0xfb86dc78, ++ 0xb2995069, 0xde97f619, 0x87d8a86f, 0x39e99070, 0x9943a25f, 0x37e48c7f, ++ 0x8e3863ce, 0x73855975, 0x07cbf41b, 0xec7e8c19, 0x824eb447, 0xd156e073, ++ 0xef96f889, 0xb14d7b11, 0x269df4c3, 0x748f9b8d, 0xad3ee388, 0xfb71b7a4, ++ 0x47b47494, 0x5847d3a2, 0xe38098af, 0xd71a3076, 0x07eca1d1, 0xf280969a, ++ 0xa75e9c28, 0x01f90f66, 0x01187014, 0xfbc886e7, 0xd757de1c, 0x97da1cf1, ++ 0xf90bef8a, 0x31cf3c1a, 0xf91c7f3e, 0x48b54e61, 0xdac1c6fc, 0x1dfee34f, ++ 0x685044fb, 0x253cbce1, 0xee6f7c06, 0xb5b11576, 0xf89fac79, 0x2df6f5c2, ++ 0xf7c237fb, 0x81bfbe19, 0x23e7354c, 0x59b83eb2, 0xcee0fa4f, 0xc631017b, ++ 0x4065be90, 0x764542bf, 0x00b3d7c5, 0xdf12f50e, 0xe6aa7cd1, 0x48c5a4fc, ++ 0xdcb1aa78, 0x7fea1b97, 0x51579a98, 0x12fd459f, 0xdc515616, 0xa3714348, ++ 0x43b63e70, 0x00ca6f1a, 0x7fe14fec, 0xc85b3036, 0x8c1c6efe, 0xba6fd457, ++ 0x5fe8a292, 0xda17c40e, 0xa05f5d3e, 0x2a619f68, 0xb66fd455, 0x3fe8a0de, ++ 0x515d36cb, 0x473b939f, 0x739e7fd1, 0x4b7ea291, 0xff4572d9, 0x2bafae05, ++ 0xad5517da, 0x712fb456, 0x97d4506f, 0xa293ff56, 0x8b4f32ff, 0xfd797da2, ++ 0x70f68a03, 0x1f2e49fb, 0x777ce2c9, 0xca77d597, 0xeb953c45, 0xfde41153, ++ 0xc7b9e860, 0x2a7d7346, 0xa42fdfbc, 0xe05c78f3, 0x18c1b1f3, 0xec9dd215, ++ 0x315d637f, 0xef5cff0a, 0x01faa9d4, 0x9c72fa23, 0xb33d216f, 0xc51fdc93, ++ 0xd93dfc82, 0x11b7d57f, 0xeb78c1fa, 0x282d3263, 0xeaefd0ef, 0x04fa02d1, ++ 0xb7bfe455, 0xf80a36b4, 0x91bdb2dc, 0x68ae55fb, 0x64212799, 0xe7c0cc1d, ++ 0xf239e295, 0x9a2b993a, 0xf8a307fb, 0x5f923df3, 0x2bf461e9, 0x2ff630e5, ++ 0xef0fd966, 0xcb9371a1, 0xcff401b4, 0x413e7508, 0xc3cb7c8b, 0xd71b3a4c, ++ 0x5a0fc907, 0x22c31ced, 0x772e59c0, 0x05ccadfa, 0x031b5be3, 0xdbd85acd, ++ 0xebffbe4f, 0x7de1bb1d, 0x32918fab, 0xffefb3f0, 0xc8334766, 0x6cb2b791, ++ 0x459237c4, 0xd647e70e, 0x93e1f8be, 0x5acedf30, 0xd5f20973, 0x6f54f6f0, ++ 0xd7a3c5cf, 0xcd647f68, 0xb8efb781, 0xbb6bfbd6, 0x69096ecf, 0x5a2fd51f, ++ 0x215cc29d, 0x45d36078, 0x26ffcbf6, 0xde0deb8b, 0x63f25aa9, 0x79ed437d, ++ 0xc2ffe90f, 0x7e4d3fd4, 0xfedfa19a, 0x07c86df2, 0xb26ff9e1, 0xeb823f78, ++ 0x1927c779, 0x00a33cf8, 0xb7187bf4, 0xde322a25, 0x7c7c1d9a, 0x883352d1, ++ 0x31f5a07e, 0xf9da1b5a, 0xc80ffaa9, 0xe1addd4f, 0xfdb87576, 0xbd90c8fe, ++ 0xb7f645dd, 0xfff1c1c1, 0xa81d12af, 0xa67dfc4d, 0x2cd1300f, 0xe01167e9, ++ 0x10ed8ea1, 0xd4a55f90, 0xd287ef89, 0x968c5f45, 0xa36608fc, 0xd63077e4, ++ 0xb202fc2b, 0xe62fa0df, 0xdef1010e, 0xf9177bdc, 0x805fd1e9, 0xfc1d99e3, ++ 0x05fdc25c, 0x968ffaa9, 0xad7097be, 0xf3d0d9f1, 0x3cc22168, 0xfd90eb61, ++ 0x04f3e113, 0xf9409f51, 0xfa40c6bc, 0xe7bef844, 0x1d53ca3a, 0x83234849, ++ 0xfe466ea7, 0xf2435a7d, 0x897c3468, 0x305819b2, 0x473cfc64, 0x3a39c126, ++ 0x3cf15e37, 0x82c299c6, 0x669ef90a, 0xaa5a3f7a, 0xab198883, 0x871b681d, ++ 0xe7cabdf3, 0x5a71a93b, 0xb1041f49, 0x82777287, 0x3fd9cb83, 0x909318e1, ++ 0xde5db8ce, 0xe58c7401, 0xe9137ec3, 0xfe807b67, 0xdf98feb0, 0x9fd06546, ++ 0xbf5ee54b, 0xf9f7da93, 0xa4fea8cb, 0xa7f545df, 0x3e5455fd, 0xf3d377e3, ++ 0x54d5fd67, 0x87bf77ff, 0x3d7f2eca, 0xefde7f3d, 0x7f7efaa3, 0xa00fd513, ++ 0x9fa2283e, 0x17ca95ba, 0xded4edfd, 0xfaa0efe3, 0x9520fecb, 0xe9a7febd, ++ 0x177f21f9, 0xbbfb0fd5, 0xdfd47ea9, 0xfe63f54b, 0xeabe5463, 0x27e7a7ef, ++ 0x1ea867fc, 0x78a4c795, 0x3fbf6b57, 0xd16bed11, 0x6eddfa86, 0xf5099d4f, ++ 0x954aeb6b, 0xe839d909, 0x9fa17757, 0x8f0d4f63, 0xa9d759f7, 0x56c40fc8, ++ 0xb49f48a9, 0xf8e87cae, 0x4c5f6a0c, 0xc870bbed, 0x758fc064, 0x6b657f5c, ++ 0x52cfd4b4, 0xec5e122b, 0x7d21a869, 0x40c73db5, 0x227596ed, 0xa88f7de9, ++ 0x9764717c, 0xff1226dd, 0xfeb868b6, 0x9d41e320, 0xb8753e74, 0xcc5f2878, ++ 0x9b14e7e6, 0xdc8e5915, 0xa6f590e7, 0x3fb863d6, 0x0fec2d6b, 0xa8db5bd7, ++ 0x65a5f8c7, 0xe60fec15, 0x5aa75dd9, 0x91d60877, 0xabdb92b6, 0x0bf21eb0, ++ 0xd92295b3, 0x4dda9629, 0x95b4aeb4, 0x6778e50b, 0x1de9da1c, 0xb405c6be, ++ 0xfc911ade, 0x439e1d9a, 0x4f90ab71, 0xd25fb8aa, 0x07706492, 0xe7ae470b, ++ 0xeff5b0be, 0x486edc61, 0xb9e97d03, 0x8b00fb08, 0xfdc7ee47, 0x23e9f778, ++ 0xebbef1fa, 0x4d28f2e0, 0xbec7f4e0, 0x3dfd1221, 0x10a37ac6, 0x11ae1fef, ++ 0xb5226f29, 0xe87599e2, 0xc399faaf, 0x8c071df3, 0xe26da8fb, 0xf1ea1121, ++ 0xccfc7c55, 0xb549f146, 0xe1fde740, 0x76de7816, 0xda3776f7, 0x6ddb09c6, ++ 0x1d6e48cd, 0xa3240f2b, 0x504d2bff, 0x765c8f9e, 0xcc7cfb4a, 0xb87bc7c5, ++ 0xb27f2451, 0xfb7edd65, 0xa3ef3e61, 0xb8ca6f38, 0x7a61445f, 0x9b62d646, ++ 0x5a46590a, 0xe71178ad, 0xbdbd5a8b, 0xda4be70a, 0x2be792ee, 0x2b3ef9c6, ++ 0x5fdec69c, 0x5844f169, 0xe4fc68d7, 0x79e47c7a, 0xe6224c47, 0x9654b083, ++ 0x11e47c8a, 0x815be70d, 0xa49f5c53, 0x23299864, 0xe7e391e7, 0x3c3d3c72, ++ 0xc127de8e, 0x39175529, 0x74aafb0e, 0x9513309e, 0xb9b6b98f, 0xe304bf29, ++ 0x5eb4d0b3, 0x73c2eec3, 0x306e5f5e, 0x07c04735, 0xf9107cb9, 0x070df218, ++ 0x5ed9c693, 0xf151c7c5, 0xeb646e71, 0x346e5ea8, 0x6bf02205, 0x1a487cb9, ++ 0xf1c1d7a7, 0x67eef536, 0xf9e28edb, 0x9ca1aabe, 0xc15587a0, 0x4e2fb236, ++ 0xa6bf89aa, 0x9f3abba8, 0x59d7590c, 0x6b0f3f69, 0xa44e7983, 0x10af181f, ++ 0x4bd22af9, 0x80bfe621, 0xbb81086c, 0x25cfdefc, 0xd5e8fd39, 0x5f1471ad, ++ 0x8514ddae, 0xd30751fa, 0x34583e13, 0x10e2b8be, 0x5e20b07c, 0x750fc046, ++ 0xef8e56b6, 0x6327cb1b, 0xe5cb865c, 0x6097c8e9, 0xc5d52fdd, 0xbe9c3c92, ++ 0x1339f5f2, 0xb2ed3ea0, 0xecbd44e8, 0xb53d06e1, 0x8ab5f94f, 0xbe5e26f2, ++ 0x5f7ddb9f, 0xd92566fd, 0xb952c975, 0xa6f3b25b, 0x2f6732b5, 0x3ab4cb9c, ++ 0x3753d923, 0x85cf115e, 0x92e449da, 0x05f6889e, 0x30dcd7f7, 0xf821ed08, ++ 0x6503e537, 0x1aa8807f, 0x01e48cf5, 0xed6b73e5, 0x6033b3fe, 0xfe068e9e, ++ 0xb7d5c772, 0xd03d638e, 0x093f22a8, 0xffc49f60, 0xe7e4c902, 0x0bc90314, ++ 0x33d36ca0, 0x9596e7e2, 0x83f2137a, 0xf881b33e, 0x2332c75f, 0x1d5ba1e9, ++ 0x4f50a3eb, 0xc636d5d6, 0x1b563961, 0x69df44e8, 0x85f6f64a, 0x6fc429d6, ++ 0x400bfca5, 0x07d032cc, 0x9495aebe, 0x383f6f9c, 0x52fc81c3, 0xd969ed45, ++ 0x880c1fdb, 0xd69dbcf8, 0x14b15361, 0xfaa1f9be, 0xc86fdcad, 0xcce805e5, ++ 0xcb8f5829, 0x51b3d8f3, 0xf40c4caf, 0xe32ed361, 0xd7f21ab9, 0x9d1224d6, ++ 0x4c7cea69, 0x4a6bcf8b, 0x2e74a1f4, 0xa5e7c9d3, 0x38a58fff, 0xc0f8f5df, ++ 0x1ebdc6f5, 0x3933ebbd, 0x4f668dfd, 0xa7e146eb, 0x9b5c7db2, 0xc90ee9c5, ++ 0x39eae496, 0xaafd446d, 0x95678a43, 0xc87e7969, 0x5599eafc, 0x0c098714, ++ 0xd6c79888, 0xa9e9cd9c, 0x71431cc3, 0xd64c8ee2, 0xc083718b, 0xefee2aed, ++ 0x3affe449, 0x3fc9326a, 0xc5f053b4, 0xbfd0b205, 0xf9e3b1ee, 0x628c0075, ++ 0x199dfe60, 0xa0b3af9c, 0x6af184cf, 0x743ea718, 0xbbfc11fd, 0x1e530fa4, ++ 0xcf689a83, 0x67f10da6, 0x88c4d258, 0x071b8bfe, 0xae9bf595, 0x4ce5eb28, ++ 0xd74fa8a3, 0x4c33eb2b, 0xda57baca, 0xe556cdff, 0x653659f3, 0x70fd2d3d, ++ 0x04e28a94, 0xf65d7ee1, 0xd297fa3a, 0x556d3da5, 0x97080975, 0xee0681f4, ++ 0x3e00cd97, 0xefc11b10, 0xe39bdaca, 0x57fe9185, 0x413ae16b, 0xd35c378a, ++ 0x67839ecf, 0x51e28533, 0x1e31b39b, 0x3c763e35, 0xd5b247fa, 0x3c3cfebe, ++ 0xa2448e87, 0x1794bb23, 0x3e3e5234, 0x8f217848, 0x08107483, 0x7fe22fd9, ++ 0xcf3f3d68, 0x079c5df3, 0x2a1020e9, 0x34070b2f, 0x7cf20748, 0x4c83d1a3, ++ 0xdc52658f, 0xb9abce44, 0xe7258d2c, 0xf94a34d5, 0xf961dd71, 0x2ad39738, ++ 0x72e81f29, 0x244306ff, 0x0b3a43ba, 0xc3ba70e4, 0xafca4db2, 0x680bba41, ++ 0x73e1dd39, 0xb9d65fdd, 0x3787e923, 0xfab0784b, 0x7bd328e9, 0xd35bfb21, ++ 0x7ba8a715, 0xa14d93bb, 0xf1ab4ef9, 0xd5e4983f, 0xb48f28ca, 0xc7ceda41, ++ 0x64fe7f67, 0xab8f940b, 0x7f91073d, 0x473ec9ad, 0x0d8cd179, 0xdeff916a, ++ 0xc01efa8c, 0x647a7623, 0xec84f57d, 0x558debe7, 0xff642df8, 0x361dfac3, ++ 0x37bc3c4b, 0xc9c320c6, 0x53bca7a9, 0xda319fc9, 0x18aee839, 0x6f242d98, ++ 0x18fa275c, 0xb12b9bf1, 0x99fa56cc, 0x10a7c3e2, 0xfff3460f, 0x338a56fc, ++ 0xfafab56f, 0x61a3ffd1, 0x1c515760, 0x1933e014, 0xa7fe26d5, 0x4b7cf036, ++ 0x0fd29a4d, 0xa24161a4, 0xea62479f, 0x59927e89, 0x6657e280, 0x9be7a3e6, ++ 0x3d126763, 0xeb9ba08d, 0x3e630bd0, 0xe6137286, 0x7f5f3c53, 0x2d27972f, ++ 0xeb83d382, 0xffcfdf0c, 0x154fbb14, 0xf49fb133, 0x4d8374c7, 0x6fbd0d77, ++ 0x8693dfa7, 0xf8356fef, 0x9bd631ea, 0x6121a4f5, 0xadfdc833, 0x58d4c4b1, ++ 0x176393f1, 0x4ee59e61, 0x27374f09, 0xcc9f08aa, 0xd53b9ab7, 0xd664f821, ++ 0xf7a8ec7a, 0x9e525599, 0xbfa1fe13, 0xef79b368, 0xcbf308b6, 0x5e90cbfa, ++ 0x08eb0d57, 0x929dc3a1, 0xdf3438de, 0x754e94f2, 0x9d6638c8, 0x93e698a7, ++ 0xf9e4faf3, 0xf9b17cb6, 0x1f7e4976, 0x6dcb3e79, 0xb459fdca, 0x459fda3e, ++ 0x7cf2bfe2, 0x117f70bb, 0xf3baeae8, 0xd0e47649, 0xfb942b7c, 0xb47ce8b3, ++ 0xfb9a8b3f, 0xdbe686cf, 0xdbe6c5f2, 0x89e5c51c, 0xd1d3a246, 0x865bdef2, ++ 0x26dd8af2, 0x659b3fe4, 0xdfc4987f, 0xefe3093f, 0x2efe25eb, 0xa249ffbf, ++ 0x9f9bfc83, 0x8a645b1c, 0x9f91d7c4, 0x628f4933, 0x24c51e92, 0xf3eb0a3d, ++ 0x4c6d9fa7, 0x3bbc3c02, 0x1122d267, 0xd5fcd8e4, 0x40662767, 0xb7ce637d, ++ 0xb3a9fd79, 0x95e153fb, 0xf36673f7, 0x5ecf77fa, 0x10a2734e, 0x12a8b0df, ++ 0x026c76f8, 0xbaf2bfe7, 0xc9ef79e5, 0xdbd7fce1, 0xbfee5bf4, 0x7c893e03, ++ 0xc7c325bb, 0x2176bfd0, 0x2576306d, 0x0fa6f7f4, 0x008f6f9a, 0x36f4b917, ++ 0x1b3f279d, 0x7fe43cb2, 0xe3e7190b, 0x09fbe50b, 0x09fbca55, 0x48dbb1b1, ++ 0x416289ff, 0x68bbf213, 0xf5834bbd, 0xa236392b, 0x59cc25d3, 0x5b66f5cd, ++ 0xe057cf36, 0x951619f7, 0xa69ae349, 0x4bed80bd, 0x68cdae54, 0xa531bdcf, ++ 0x43d50936, 0x80ac2f39, 0x9fbd326d, 0x3e3353cb, 0x2cfe46bd, 0x97dece06, ++ 0x717c05d7, 0xd702bbfe, 0x7f70c705, 0xf9729fc3, 0x66fd427a, 0x068df7a8, ++ 0xc04627cf, 0x19e1c5d3, 0x34f0e2ef, 0xc336c60d, 0x06e37bf9, 0x3e891bcd, ++ 0x6bc2237b, 0xe0c35c04, 0x0dc003f7, 0x2351cec9, 0xde0f5dbe, 0xfce55c32, ++ 0x96c116b9, 0xa3eaf24d, 0x65dc8502, 0x148b69cc, 0xe7ead8c7, 0x7921fdfe, ++ 0xe861e69a, 0x9d5ad09f, 0xdd5798b9, 0xc47557f2, 0x2477b4bc, 0x1ac73478, ++ 0x25b1af28, 0x66f64b56, 0x866cec5f, 0x38d155fe, 0x1952e093, 0x86f9455b, ++ 0x85d604ea, 0x1e7858f6, 0xddcc7ab5, 0x4ea30794, 0xca1a0d45, 0x975cbca1, ++ 0xa607e29e, 0x51e66b92, 0xa3cbd78b, 0xf3cd9f8e, 0x36b563a8, 0xc7364954, ++ 0x51e62368, 0xe5c390bf, 0x27ee1f7e, 0xfb0fd711, 0x43ef0fb1, 0x3238f134, ++ 0xb8c68f3e, 0xc8c7c9b2, 0xf7ed2c9f, 0xe41ce905, 0x228d68fe, 0x9d6b503f, ++ 0xd44fd436, 0xf4272e06, 0x1b962a69, 0xf9e5bf22, 0xdc3472bb, 0xe26793df, ++ 0xf5cf4cf2, 0x09aff9d2, 0x1729fd11, 0x4a7f6472, 0x0d1b3c64, 0x78aa164f, ++ 0x874c991e, 0xca5a8d8b, 0xb46c5b6f, 0x601fa056, 0x07de2031, 0xbffd21f1, ++ 0x17e894ba, 0xf88ac3e8, 0x6e1bb3f3, 0x0c67e17a, 0x3f9cdcdd, 0xa1a59e9f, ++ 0x05a761fb, 0x8fc672e6, 0xbb74dfcc, 0x32e066e3, 0x767b996f, 0x53df9213, ++ 0xe095afe6, 0xd3e3ba78, 0xe91b6635, 0xc8719aff, 0x9becea17, 0xb4bea093, ++ 0xf88358a6, 0xbc49c727, 0x7f8f9cd1, 0x6031ed43, 0x7f530bbf, 0x78815b1b, ++ 0xe0660e24, 0x4938e47a, 0x5231bf48, 0xbafcf9bf, 0x422bf414, 0x2fdefd3e, ++ 0xc3ce8c3c, 0x424f491a, 0x9c8581fb, 0xd01fcc8b, 0x8e7d088e, 0x910b03f6, ++ 0xccb98233, 0x5f811032, 0x7ad9a5c8, 0xd01d6c7a, 0x9fb939b9, 0x4ef9f94a, ++ 0x182aba97, 0xc78b5ce1, 0x1e9b7f09, 0x9dab01df, 0x83c7ac3c, 0xf08c5efe, ++ 0xb4fab8f8, 0x696c2279, 0xd245e56d, 0x995a35e3, 0x5f446cce, 0xbc6575c3, ++ 0x77bf976e, 0xfda0e8ac, 0xaf508fb1, 0x7c79124e, 0x84db877a, 0xbfd83bfa, ++ 0x8777dc2e, 0x4ad8ccff, 0x15bdf871, 0x44fc24e3, 0xa3d605a3, 0x9ad3f093, ++ 0x9ecb69e6, 0x524d7948, 0x22ae503e, 0x65417f2f, 0xd4448cdc, 0x4e636e6b, ++ 0xd4b70da3, 0xb3f48cde, 0xea10f913, 0x25ee8765, 0xf9a4b2fa, 0x64318084, ++ 0x6809141e, 0xccf1497f, 0xb49589cb, 0xf6439d8f, 0xfd918f85, 0x47eee695, ++ 0x21f9747e, 0xb3b4bd0d, 0x4d6ed942, 0x619a7b73, 0xe7ec777d, 0x9a966af9, ++ 0x7ee90176, 0xf90263e7, 0x141d61a2, 0x70640fd7, 0x61dd42fb, 0x3fe00164, ++ 0x6e7b557f, 0x6cbb3826, 0x89c954df, 0xcd6fd0bf, 0x67e92d58, 0x2ccf059b, ++ 0xc54acf7e, 0xee39f922, 0xcff9c718, 0x744ce39d, 0x9beb66fe, 0xb14aeb63, ++ 0xe6f09d7c, 0x46f9d2b3, 0xbf681f94, 0xe960f98c, 0xdeb0e27b, 0x8c89aad3, ++ 0x938c6f9f, 0xf2c8dbee, 0x145f8242, 0x7e91e8f3, 0x3b9b82d5, 0xe67e9ef9, ++ 0x04cc6799, 0xdc27ca22, 0xf235e926, 0x5db9d138, 0x74ed18d4, 0x140bcc31, ++ 0x072e2e4c, 0x006b014c, 0x2ff5afe8, 0xd6f688ea, 0x6bf3a5f7, 0x62b16fb6, ++ 0xd3874aff, 0xf0ba7e8a, 0xf62d1afb, 0xcf3c56c9, 0x7b4a5996, 0xcfa71e51, ++ 0xe616f39e, 0x698f1879, 0x2a8f2298, 0x5e62d4ac, 0xda35c244, 0x2deafca5, ++ 0xe45e7887, 0x3f496316, 0x18b7e1c6, 0x58e84b13, 0x52cf3c8d, 0x1e346fee, ++ 0x3a347c25, 0x88d1bc79, 0xe5c041f2, 0xd9f43871, 0xe41c128f, 0x8e3cff7e, ++ 0xb3a315f3, 0x25fde197, 0xfd483383, 0x407744a2, 0x4a8feb05, 0x25ff7464, ++ 0x55740f4a, 0x31557088, 0x7179047d, 0x2f2e38cf, 0xf495a4b6, 0x44fad397, ++ 0xb6cd09bc, 0x24ac4b58, 0x30de11b7, 0xac9c4b6f, 0x3eba72df, 0x7917f120, ++ 0xff29169c, 0xdca6b6f3, 0xe8099545, 0x3b3f7127, 0xde35c70e, 0x52fa47ae, ++ 0xe6bc4cc7, 0xf9d2bd78, 0x75af1c8d, 0x01de3489, 0x4c750ba4, 0xd3c70989, ++ 0x1c22fc48, 0x75a527ee, 0x66f1adfd, 0x77dd2c80, 0x581d3aa5, 0xef491ac0, ++ 0xc63d4b91, 0xbe474b91, 0xeff985f7, 0x051fa526, 0x8459eff8, 0x73b49ae7, ++ 0x09e9cb47, 0x263c9ff7, 0x9db227d9, 0x06c69661, 0xb0f74336, 0x89c18203, ++ 0x3bb6427c, 0x384a51cc, 0xe487df0c, 0x9aa970e7, 0x4a5d8de7, 0x0fd7e464, ++ 0x274be7a7, 0xb50b8dde, 0x712ed04f, 0x04bb70e5, 0x5c4bb44b, 0xeb099f92, ++ 0x3b4037e8, 0x21fba645, 0xedb566bf, 0x7d60d33b, 0x2adfe03a, 0xf3485718, ++ 0xd2eb7e11, 0xe748ec06, 0xfd3dd219, 0xe4573870, 0xbe113c72, 0xe91d81f5, ++ 0x307132bb, 0xa70bdf19, 0xbdefc7f3, 0x79fb8c92, 0x9e50d67c, 0xd647c509, ++ 0xf7e4cb2f, 0x3eff8f92, 0xfc6113ce, 0x8a7fddeb, 0x036db73d, 0x73b781e9, ++ 0x7d1ff03d, 0x95b1ea1f, 0x16ecef5c, 0x69a77e94, 0x7fef9cb9, 0xbfe39725, ++ 0xed300ae5, 0x9127ba52, 0x7e849b9b, 0xc8edd308, 0xe5ee337f, 0xefeb6379, ++ 0xcee0fc6f, 0x3530f408, 0x373e33cf, 0x5acb0e84, 0x6b0fe4b5, 0xb98e6631, ++ 0xf47f9f96, 0x3e71f673, 0xf96f9d2e, 0x9f3cf4b7, 0x62f5c3c2, 0xca0ee7b3, ++ 0x9fcf08d3, 0x9fdfad18, 0x1a4def91, 0xe6abafee, 0x718b73fa, 0x3e03f921, ++ 0xf5011b41, 0x85ef890a, 0xc8f7f3af, 0x7c389244, 0x6257c0f4, 0x8515dd0f, ++ 0x7b246ae3, 0x9fd931ec, 0x77a25d51, 0x59afbc85, 0x08afa256, 0xc61697c1, ++ 0xc7c357f3, 0xa43b94df, 0xa2be934f, 0x8357e891, 0x437d1672, 0x4347e289, ++ 0x4b14867c, 0x918ec283, 0x9fcf0fe7, 0x8a97c90a, 0xedca74e2, 0x37989d99, ++ 0x736dfa05, 0x1163edf5, 0xcf453bbe, 0xc38016e3, 0xca3adbe0, 0xa2477df3, ++ 0x2e8901cb, 0x00bf3b47, 0xe3c9443b, 0xbc61d91b, 0x327805b4, 0x47d20c71, ++ 0x1555438b, 0x66cfb08c, 0xf4119f69, 0x4ee66feb, 0xf5fa4cfa, 0xd046e53f, ++ 0x767f51af, 0x43dff985, 0xbb37a8eb, 0x27d7e822, 0x201fc905, 0xd49cade5, ++ 0x0007bad8, 0x1c6f270e, 0xd1b16ce3, 0xb3971b3d, 0xa787ec04, 0x6f503ace, ++ 0xeff02f9f, 0x61f7c824, 0xa951e096, 0x17f88ec9, 0xe602d75c, 0x814ee67b, ++ 0x37ed08e2, 0x013a69db, 0xe77ae3cf, 0x93ca4cb9, 0x42738369, 0xabcefbbf, ++ 0xf245672b, 0xc21d1f6b, 0xc35d6413, 0x9e1958f7, 0x655c4842, 0x2c28bc44, ++ 0x04e1843e, 0xe3957fcc, 0x6ffde147, 0x6fc65329, 0xff72aeda, 0x162eee85, ++ 0x7e6028dc, 0x517db2a4, 0x3e3c2695, 0x2ceb88a5, 0xd7c26b71, 0xffcd0813, ++ 0x3773df4d, 0xa46781c5, 0x359e7c8b, 0xf0f9ec8c, 0xb8ae8fb8, 0x50c6a5df, ++ 0xda733549, 0xd8fd236c, 0xfe492f98, 0x1ec66abd, 0x9d77bf46, 0xf2d6af32, ++ 0xf90fdcd0, 0xabda29f7, 0x43ab1e70, 0xb63f50c5, 0xe4fd9478, 0x89a60b78, ++ 0x9e17de84, 0x7bf236a1, 0xb454cb6c, 0x89b8163e, 0x3cbf65da, 0x9b9637f4, ++ 0x5e6df787, 0xd3fa86c7, 0xe440a23d, 0x39daef7d, 0x983fdf97, 0x85ee2be8, ++ 0x232754a6, 0xb1d6a438, 0x03fa7e20, 0x6b88a0e0, 0xd1f7d2eb, 0x67a93f3e, ++ 0xc1c7812c, 0x20c9ed14, 0x613f11c1, 0x37388aff, 0x0f5153ec, 0x67af3bb7, ++ 0x1dd2ea6f, 0xd7e7e4d7, 0xa4ea37f3, 0x5ca5d978, 0x88a40f29, 0x63bea115, ++ 0x9d10f65e, 0x1e7027c7, 0x169e7794, 0x1db61e39, 0x450117c6, 0xd2f44b76, ++ 0xe558c522, 0x9730aaef, 0x84a9f748, 0x2166be32, 0xa3e3cdc1, 0x5be88c85, ++ 0x0b950067, 0xaa9859e8, 0x75dc2173, 0x96c3a83a, 0x27d32d05, 0xe4b573c3, ++ 0x98166e6f, 0x72667588, 0x509fb9ea, 0x904baefe, 0xda32ebbe, 0x0ffba03c, ++ 0x017ce144, 0x4f3c9efe, 0x546177c8, 0xfb5c169f, 0x23f7bc7d, 0x7efc3bcf, ++ 0xe51df925, 0x7f8347f9, 0xc651dfb8, 0x7f4e5fe3, 0x7bf7127d, 0xd6be11a6, ++ 0xd52be30c, 0x88f84a57, 0xf85f23ef, 0xed6cdcba, 0x76fbc22f, 0xed11bee7, ++ 0xd0f83f44, 0xd473023e, 0x39cf8fb4, 0xac3ad0de, 0x4f7e0cb6, 0x3497da4c, ++ 0x17dde7de, 0xb5f085fd, 0x028978ad, 0x186a2ff3, 0x9ecdd3c5, 0x8a450f8a, ++ 0x141ec383, 0x7ee4227c, 0xf5b78c3e, 0xdcfbcf10, 0x0879df85, 0x5ea023f1, ++ 0xb5837681, 0xb0479e06, 0x8eb2e483, 0xf2b1fbf1, 0xa0b45aba, 0xaa5e2347, ++ 0xcf3d1eb8, 0x5e622038, 0x5071268f, 0xcb69fa44, 0x087c7ce3, 0xe518937f, ++ 0xa553a81f, 0x36b1bf3c, 0x970733aa, 0x6b3cf26f, 0xbed254f3, 0x3ffbe9fb, ++ 0x374fa2f3, 0x7f309cda, 0xd18bf3de, 0xcc6f3f3f, 0xd43b46e9, 0xe1fbccef, ++ 0x67e81162, 0xcbe9ea5e, 0x77631376, 0xf5e7ede5, 0x3397d382, 0xef3abea1, ++ 0x81bf5e05, 0x26b39191, 0x8c62c0ef, 0xfc95ad3b, 0x8ff8f27f, 0x7d27ac23, ++ 0x53ad52f1, 0xbe47cc45, 0x27ce4f27, 0xd49f7464, 0x3393f3dd, 0xcb749718, ++ 0x09a5d1f2, 0xc9a077d3, 0xa4a8f78c, 0x8a58c4bf, 0xf096ce87, 0x777e0e6c, ++ 0x96fd1628, 0x71df04bd, 0x87fa7ec3, 0x5e9f8f3e, 0x65dfc970, 0xa01ab132, ++ 0xe62696ff, 0xc10aca89, 0x7d52e67b, 0x2960f3ca, 0x47af206e, 0xbac47f9e, ++ 0xf8c568e0, 0xa1ed75d0, 0x5d75e471, 0x1e91d628, 0xba1f1e16, 0x863e0c20, ++ 0xe3954279, 0xb9e29733, 0xcc19885e, 0xfd3ea010, 0xaa12fb19, 0x263e0d27, ++ 0x1aea4338, 0xe68f8e7e, 0xf118b6bd, 0xf5da88f5, 0x7e125e68, 0xbf7f8ab7, ++ 0x438a55a0, 0x09e4903d, 0x78067da0, 0x81557947, 0xdde52d74, 0x5c144e55, ++ 0xa7c0fea1, 0xc82b3c24, 0x1999fee7, 0x29df76ba, 0x7eef4bc0, 0x7f433581, ++ 0x5a4bd5ef, 0xf5e64fd4, 0x1ea2d59c, 0x59ff76bd, 0x5ccbde2d, 0xa3c4758b, ++ 0x24575a3d, 0xf92beffd, 0x15dcf96a, 0xf491d776, 0x77e8cd9c, 0xd0275b5b, ++ 0x07f5b43d, 0xfd6e1fb9, 0x6325dc4a, 0x8e7b4eb7, 0xeeb5b8fc, 0xae58cdbe, ++ 0xf0470360, 0x3ccb09bb, 0x8abdc56a, 0x8ad1f5e5, 0xbeb5177b, 0x457d4504, ++ 0xc80e9c3b, 0xa94d15d9, 0x4a18f78a, 0x32cf583d, 0xf687fc36, 0x8e74b57f, ++ 0xfbdbaccb, 0xccb5dfd1, 0xe663d4a3, 0xf18b34f5, 0x409f6eb8, 0xfc80aff7, ++ 0x72def86d, 0x432843be, 0xfb802af4, 0x47ae6e8c, 0x93d6adad, 0x7583527d, ++ 0x834d6b80, 0xce9f883a, 0xa5ae9239, 0x40b76f76, 0xdda95eed, 0xbb702f5b, ++ 0x2bafe25a, 0x7f2e35a4, 0xba0cd4e9, 0xf570194e, 0xbbd6423b, 0x43eabaa2, ++ 0xdf4947c2, 0x6d55f790, 0xd6c6fae3, 0x383537f4, 0x047b8aee, 0x7da76096, ++ 0xe5a8f429, 0xad7acaf5, 0x67a6134f, 0x7f90680d, 0x3e5268af, 0x72079f3f, ++ 0x80a3e91d, 0x5d3d2015, 0xa24413ca, 0x51fea92f, 0x7b279bfa, 0xd5a77d61, ++ 0x7e203fee, 0xc77b6836, 0xad3bdca3, 0x6e5d50f6, 0xb96be787, 0x8afae2bc, ++ 0xdf0f280a, 0x4cb8d16f, 0xb0349f78, 0x5dbc2046, 0x1ef442ce, 0xaa7f70fb, ++ 0xf3d647ab, 0x1bbe25f2, 0x7f246ee5, 0x09824be8, 0xd14a86f5, 0xf03de225, ++ 0xe8fc5196, 0x1e9cf9f9, 0x4281b24e, 0x220e575c, 0xce539c29, 0x672431a2, ++ 0x6573fe72, 0x3948e300, 0x25f902a5, 0x9b8ac0e6, 0x8914b04a, 0x5cc7cc8f, ++ 0xa61fbc01, 0xfe26aaee, 0x226b413e, 0x53c68efe, 0xfd70bf08, 0xd7de132b, ++ 0xe7059573, 0x8c76939d, 0xbf373fbe, 0xe445fb63, 0x572c8e8b, 0xdf580ec9, ++ 0xfe7c5103, 0xc10a0e07, 0x6d671866, 0x9fe251e1, 0x9c0f4016, 0xe255ad77, ++ 0xff4adda3, 0x1af905ac, 0x42dccc22, 0x8e59379a, 0x915e032f, 0x20adee1c, ++ 0xcd22c4fd, 0xd0bd1a7b, 0xddf36fb0, 0x0b165e52, 0x797e6334, 0x9c085e32, ++ 0x617e5c34, 0x20a5557f, 0x9e0bc586, 0x957f43ca, 0xef914075, 0xff8e25f3, ++ 0xf859e21c, 0x457db0f8, 0xfa8672bc, 0x6fdd2c6a, 0x9aeb297a, 0xbd6a40f9, ++ 0xc69b9ef2, 0x77bb0864, 0xf33fe4a6, 0xf761a99c, 0xeec2b2ce, 0xdd84159d, ++ 0x73de533b, 0x21bee25b, 0xf299deec, 0x3ace9b9e, 0xca3fd15b, 0x8f5150b6, ++ 0xd155bdce, 0xbb79c63f, 0xfc775da2, 0x13216a85, 0x1817b3bf, 0x5a1c00f0, ++ 0xe2ca3681, 0x4148e587, 0xd286742c, 0xc4651a50, 0xd758b5b2, 0x9ad2788b, ++ 0xdd73edc2, 0x7b586ff1, 0x98fd1c61, 0x6fe8f567, 0x582137fc, 0x5e89f681, ++ 0xbfc953ca, 0xcce4298f, 0x2ba71160, 0xdf27bcb9, 0xce00a5b3, 0x5b69f0bf, ++ 0x40aeff2a, 0x8f9e3e7f, 0x81363f1e, 0xdf807374, 0xd9209dab, 0xaf38f211, ++ 0xcbefcb3b, 0x73eef7c7, 0x7b38a2cd, 0xbb1fbf37, 0xbc78cb57, 0xefcf00e4, ++ 0x501eec2c, 0xdbe842b9, 0xc1f9c050, 0x1415dcf7, 0x03db591f, 0xa9e91652, ++ 0xef169ce3, 0xe9edac25, 0x3679458b, 0x8b4e7dde, 0xe7e1937e, 0x07139c92, ++ 0xffaf680d, 0x78e45747, 0x5af98bda, 0x12a38fa2, 0x86fdaf5f, 0xcc8ddb9a, ++ 0xa6f31735, 0xfb5d7e65, 0xed5fdf1c, 0x03cf2d12, 0x047468c5, 0xfa7c0dbe, ++ 0xbb0f929c, 0x5a60f294, 0x0ef23370, 0x7e8adfe0, 0x24cf162b, 0xf806b7bb, ++ 0xf031d236, 0xda7b6573, 0xc02fe216, 0x9fcf15cf, 0xb4ec97ce, 0x29f85602, ++ 0xadc677bc, 0xabcfb88a, 0xf1c12245, 0xc13a678c, 0x47007bff, 0x6f7da7f4, ++ 0x3c38dc04, 0x1faf07af, 0x9c87d9e0, 0xfd3f785b, 0xfe3fae78, 0x6d7e1460, ++ 0x7bede02a, 0x6412fe85, 0x81b75ea6, 0xdeb976f0, 0x75fd0733, 0xb0ffd347, ++ 0xb570e305, 0x4f74082f, 0x8efbbffd, 0xd7ff519b, 0x8cc4773e, 0xd76f30fe, ++ 0xa6d83311, 0x6b6341ac, 0xf01e3d46, 0xcf7a89c2, 0x5a5eeeda, 0xd2ae9aff, ++ 0xa6be7c3e, 0xd7efa05b, 0x9c5ff778, 0x0364fb49, 0xb85e305b, 0xbd759477, ++ 0xb391c929, 0xcf9e36f9, 0x513981e1, 0x05d7efde, 0x01e20283, 0xd75c25f0, ++ 0x3cbf0141, 0xe9b6f6c6, 0x51e923ab, 0xbc39e389, 0x1969b70f, 0xe01bebfa, ++ 0xd1c7dc7d, 0x3d5aa3f4, 0x0273d1e2, 0xaededad9, 0x71a24b53, 0x430d46fc, ++ 0xdf5e42fd, 0xeffde9c7, 0xaedffee0, 0x80a7a0d3, 0x09a9d4b5, 0xaa376fde, ++ 0x2af51c69, 0xdd97d50d, 0x5e2af3c5, 0x4b777ba9, 0x76fb8c2a, 0xfc794083, ++ 0xfefd57d3, 0xdd97d628, 0x70b5f5c5, 0x35f1967c, 0xf1c33f1c, 0xd69e0477, ++ 0xfd3c317f, 0x8e9e30cb, 0xe70f3947, 0xf882c33e, 0x1fbf2f73, 0x15f57d5e, ++ 0x3337fa0d, 0x1b9c98b7, 0x0ea45ea1, 0x9f23366e, 0x17b78578, 0x9c0a7437, ++ 0x456ed8df, 0xd56d4c3a, 0x4d77b432, 0x35ff5c05, 0xb2f3f015, 0xe30141b1, ++ 0xcfec4c6b, 0x9764be44, 0x6bcf49e2, 0x1473f558, 0xa6fce417, 0xced647e8, ++ 0xffb8bcd0, 0x990ef494, 0x9968160f, 0xcbf239e7, 0x3de0a576, 0xf9481f82, ++ 0x78d219a0, 0x338359d9, 0x2c594017, 0x95229fcd, 0xc250bd72, 0x9678167f, ++ 0x8a4f3be0, 0xea6eccb3, 0xc3cc7ca5, 0xf90d8f5a, 0x378cdce8, 0xb5ce501b, ++ 0x485abe66, 0x5378c679, 0x3f7e3260, 0x32bdff98, 0x367b37e5, 0xcf2fdc60, ++ 0xf518e740, 0x43ca0ed2, 0x689eca8b, 0x90e71489, 0x1b15ef4b, 0xed6f8f7d, ++ 0xe52a4c95, 0x1f4382fa, 0x0ec8076a, 0xe89338b8, 0xf1558ae4, 0xb49b3edd, ++ 0xfbf922ee, 0xcfdc3d6c, 0x2c5a7c03, 0x27ee192b, 0xcb3d01c3, 0x7b2a3fd8, ++ 0x86d79d1f, 0x8798ac75, 0x3c1077b7, 0x129c3797, 0x4b0fbbf0, 0x118d2e35, ++ 0x98e6fde0, 0x7df839ea, 0x900efc46, 0x26e30727, 0x7c97ba7a, 0x7aa26fd2, ++ 0xf54adfbf, 0x951b7ed3, 0x95ddea6f, 0x8725a708, 0xb708d97d, 0xba77d257, ++ 0x85debef1, 0xaf091a13, 0xb4befc4d, 0x7a976b84, 0x718f4cd4, 0x8fa0fdae, ++ 0xbfebc30b, 0xdd0a4aed, 0xce39fe6f, 0x69acf307, 0x3bf119fa, 0x99c5fd67, ++ 0x37151768, 0x7582dd9c, 0x67efd36f, 0x0ef13ea2, 0xebd20fc8, 0x0ab7bf41, ++ 0x694e47c8, 0x73596e31, 0xf9c69e25, 0x26706a81, 0x65e057d2, 0xbc9fee81, ++ 0x6b517dd3, 0xdc89f2e1, 0x1a2f7873, 0x0b9bf2fd, 0xbd3fb8e2, 0xcfc558a7, ++ 0x2aedc1d7, 0xf2fa1f09, 0xe78b14ff, 0xbdb26fa1, 0x7fbe0376, 0x7e90cd4c, ++ 0xc60c55b7, 0xdff0229a, 0xcbbfe833, 0x32c0fbe1, 0x1b5abdbc, 0xc93cc6c8, ++ 0xc38f096a, 0x860b9bdb, 0xe91a13fc, 0x084c403b, 0x32d50ff1, 0xb04ffdfe, ++ 0x400d7a7b, 0xd33db5c7, 0xeb533fc9, 0x9fe9ae13, 0x3f0f0d19, 0x7196b96b, ++ 0x475c8cff, 0xafd431bb, 0x53237689, 0xdfe01fcc, 0x5c774a81, 0x778a9ef3, ++ 0xf9e28520, 0xc5195b6b, 0xc95cd6bb, 0xc1fcf2a7, 0x1fa436ad, 0x277061bd, ++ 0x51ccefdd, 0x26b19d91, 0x1a7fd4a0, 0x685f388b, 0xdd9ff494, 0xe92f6005, ++ 0x04bd90d9, 0xc41ed176, 0x628bb04f, 0xbd85310f, 0xec9cfe14, 0x4f74bd25, ++ 0xf3c18e05, 0x0775847c, 0xf13a2a8a, 0x4ed60cbd, 0xf04ece78, 0xfbe1bbfb, ++ 0x8bd2567c, 0x865eba64, 0xdbf88d74, 0x7c3ae9cd, 0xca8a07dc, 0xdb71c59f, ++ 0x356f8946, 0xd35cfb4b, 0xde5e08c1, 0xd382788e, 0x5dc3acc7, 0x31f97801, ++ 0x51ef03ac, 0xa3bb705e, 0x0bfde0e3, 0xe634771e, 0x607cc8f7, 0xbbcf076d, ++ 0x4c2c736f, 0x3ed1bcc0, 0x77cfef09, 0x9c23d74f, 0xf4e0eb6f, 0x4ef7cf27, ++ 0xa404b2ef, 0x419a49a7, 0xd3da13ad, 0xa2c6ce7a, 0xe0e937de, 0xc3a404a2, ++ 0xbfb9d6d1, 0x35a7f390, 0x48e7eb4d, 0x3d4ca779, 0x6027b259, 0xbd8dde7d, ++ 0xd5f69df4, 0xb7f08c4d, 0xaf7fc0ef, 0xdf3e3a45, 0xb9426d13, 0xd14bf1f9, ++ 0x0bc6bdf4, 0x2a82eb2f, 0xfa0eec81, 0x9ac7e8be, 0x5fa4f981, 0xbdd3541e, ++ 0xbfcbef40, 0xe8f489db, 0xbca3a03d, 0x5b3dd5c3, 0x6bdca22f, 0x21f599e8, ++ 0xe1b4677e, 0x3d2c7fd9, 0x26fa69ac, 0xfd7245e9, 0x1bbd7e77, 0x9179e8f9, ++ 0xddd589f3, 0x777d243f, 0xe34bd5f5, 0xe3e53f31, 0x193cfe97, 0x3ff79af9, ++ 0x7e464d2f, 0xa5f1fde6, 0xfdeed8c9, 0x922fb451, 0x5e3652be, 0xcb25e74d, ++ 0xa2ebfb4b, 0xb7b43fc2, 0xbeddc388, 0x87be9da9, 0x62d4e93c, 0x0f77e867, ++ 0xdcab6526, 0x1bd27fd8, 0x42ab0995, 0x2fd4dbde, 0xe2719c52, 0xbae8caa9, ++ 0x55dcbc10, 0xc3fd91a4, 0xc3afc85f, 0x0cc3efa4, 0xf9fa71f9, 0xfadab077, ++ 0x9f7dfe45, 0x61ee817a, 0xe232fe83, 0xff9d165e, 0x7df4095d, 0xe7ba261f, ++ 0x7ac44d14, 0x87177d36, 0x1c47f405, 0xb2d27a21, 0x0eaf557e, 0x47baa8f0, ++ 0x7dfa4bd7, 0xea9678bf, 0xdb74fe92, 0xd8c4dfc5, 0x99fe0885, 0x9033d3dc, ++ 0x69fb878f, 0xd7062fe0, 0x355beb2d, 0xae3a4f3e, 0xb37fdc3f, 0xf266faa2, ++ 0x6ffb850f, 0x6aa2fdec, 0xfefc44de, 0x85675d39, 0x47a43efd, 0x50f5917a, ++ 0x11fdbf3c, 0x8959ffe8, 0xdaba646e, 0xbfe3cfd4, 0xf42bfa9b, 0x909f280e, ++ 0x3883f7da, 0x9bf8c00d, 0x813d167a, 0x574d847e, 0x01174697, 0xbebd36bc, ++ 0xfa446d90, 0xb3e85537, 0x37abbdf1, 0x0e1497eb, 0x7cf84be3, 0x0f5c858d, ++ 0x2213d61a, 0xd255bdcb, 0xf928ffbc, 0xfff0b2b7, 0x7607f90d, 0x12617d78, ++ 0xb9cbe1d9, 0xe1db849f, 0xe64372e1, 0xbbb8f2c7, 0xe48f7825, 0x7e921fc7, ++ 0xf132f603, 0x3685dde3, 0xb3d697ea, 0xe8ec8120, 0xd82717d7, 0xcfc7238c, ++ 0xf8aa9d12, 0xcbe391c2, 0xe0379c7a, 0x3b47a23a, 0x7ee6a5c7, 0x5042c5d2, ++ 0x3ef58610, 0x7d205baf, 0x09a35bdc, 0x5d793f62, 0x5fb98bfd, 0x134b8975, ++ 0xf586128c, 0x1c7f5943, 0xd40a776a, 0xb293eb2e, 0xe6efd8de, 0x13c5dc7e, ++ 0x7a9bfb79, 0xebc23b4f, 0xfdfe5e9d, 0xf85349ae, 0x47dcc673, 0xf4bea152, ++ 0xfa23026b, 0x1949f497, 0xcdf5c34f, 0xaeb27a4f, 0x3d9abdf9, 0x74ca7e12, ++ 0x1f461196, 0x93eafcb2, 0x28b5dfec, 0x7e5013bf, 0x97a151ff, 0xf20b8f87, ++ 0xbd215f7b, 0x277f08c7, 0x23ba21be, 0x6593e7d9, 0xafcf963a, 0xae3970ff, ++ 0x53f59d37, 0x7268ec9e, 0x9522a9f5, 0xb7843f82, 0x367c15f7, 0xa155fe7a, ++ 0x83fd4764, 0x25bff9e8, 0x3b7ff33e, 0x85e90f3d, 0x0cfbc8da, 0x87bf9514, ++ 0xfb506fe7, 0xb4739f28, 0x50fd7bef, 0xe760d392, 0x48f8f02a, 0x768556ba, ++ 0xfb9eb791, 0x6ce35a07, 0x72fd91af, 0x1fdf4d5c, 0x20760d59, 0x5f776fea, ++ 0x80d95131, 0xcb94327a, 0xdf453e9f, 0xaf5e5d99, 0xfa2b7f5c, 0x75fdf16e, ++ 0xd7eb8a76, 0x2bf24ab2, 0x99c4f6d5, 0x35bfdf30, 0xd228eba9, 0xb509e055, ++ 0xfed089ed, 0x7f52f96d, 0xd5b7f73d, 0xa7efd1c7, 0xa03d30b0, 0xefae17d6, ++ 0x1b82f52b, 0x68d13f24, 0xfb8fc1fa, 0x395f38a2, 0x5f3a26a6, 0x2bbfe6eb, ++ 0x7ce1eda0, 0x4514dbc1, 0xd7b4137e, 0x341f5d70, 0xeefc4109, 0xdfa91af7, ++ 0xf93f6207, 0x069e289f, 0xd9ec3e5d, 0x64ba4661, 0x68fc652e, 0x8837becd, ++ 0x91c7866f, 0x714bf7e2, 0xd1b8a1a1, 0x5907ca64, 0x05a4f603, 0xed9b4bf5, ++ 0xac3f8416, 0xef89058f, 0x987e14b8, 0x4bbd8e4f, 0x83f2e7f6, 0x2233fe3c, ++ 0x9b3ad47e, 0xbbf08fc7, 0x90fc1123, 0x3d1ec62b, 0x7423bf82, 0xdad1b8bd, ++ 0x8f7453ee, 0x11fe8464, 0x2a4c77a6, 0xc719fa52, 0x3b8fdc8a, 0xa13047b6, ++ 0x04ac6a7f, 0x19b4afc7, 0xf99eaf48, 0xe404bacb, 0x9d39f207, 0x7ae1c05f, ++ 0xf4cbedfe, 0xbfc9c47d, 0xfdf84d14, 0xddbf1fc4, 0x5e54b3f8, 0xf86de9b7, ++ 0xda34635e, 0xb97fe731, 0xfae11a3e, 0xf7f12863, 0x46747e15, 0xec8fe88c, ++ 0xcf4bf61e, 0xb2ff222e, 0x411697e4, 0xfb0cc61e, 0x7bdfc273, 0x15af7a4b, ++ 0x63f214cc, 0xfdf1e41e, 0x6ccf64d6, 0x64ceefaa, 0x2e907bfc, 0x10ff3bf2, ++ 0x45fd1af0, 0x8c59b005, 0x81bbff3f, 0x5178c26d, 0x55e7926b, 0x2adda3a2, ++ 0xbc11d21b, 0xc0a6714f, 0x8f923673, 0xe78c3208, 0xeff2d78c, 0x9364d212, ++ 0x98d7bf87, 0xda2c760c, 0xc59ab093, 0x902e6f18, 0x0de33ae2, 0x1ff1c44c, ++ 0xe1b678d0, 0xe81f4377, 0x44cd9d13, 0xfc04ce04, 0x7c7875ee, 0xb8f17049, ++ 0x92671cb8, 0xc5a3e3e3, 0x679c0499, 0x9e3bc73c, 0x3012e2b7, 0x93c72e6e, ++ 0xfcdcd7d8, 0x3e65b37b, 0xe93fefca, 0x4bfcf464, 0x543cf38c, 0xd3ce2110, ++ 0xf0b7c929, 0xdcb6e2b8, 0x3f4f09e7, 0x57f13c6f, 0x6a5fb348, 0x27c38bfc, ++ 0xe313dd7c, 0xbd93313e, 0x15ff97f5, 0xe7b6724b, 0x0bc3c912, 0x3ee93a83, ++ 0xb3f700c2, 0xbfc868f7, 0xb6ec0170, 0xfb3910a4, 0x797fc957, 0xe13a67a8, ++ 0xcafefeff, 0x4e3fec68, 0xaf6de392, 0x0f345e2f, 0x745fb2f1, 0xb84ad366, ++ 0x5fbfb61d, 0xcb7a849c, 0x5d2e7897, 0x7be21185, 0xefe4437a, 0xe892ac2c, ++ 0x87115568, 0xb9b7f4f3, 0xe46de5fd, 0xc4931471, 0x5a55bc17, 0xd34783e2, ++ 0x3fec82cd, 0xb38a44b7, 0xb9241c1c, 0x40977b51, 0x70be1cf7, 0x4fbba59c, ++ 0xfe615b92, 0xc499aae9, 0x5bf34737, 0x15cdc487, 0x49146fed, 0xee22f371, ++ 0xc8b9bebf, 0xf78efb44, 0xee639715, 0x2fffbca1, 0x8d361cf1, 0x59c6fbff, ++ 0x01109c9f, 0xf1c4bf8f, 0xbefff31b, 0x77fb3fe3, 0xfcc5ff1e, 0x7ffc2fbf, ++ 0xbf1e77fe, 0xfd7f1238, 0xf94fc712, 0x583f8f3b, 0xff3e0110, 0xc200f353, ++ 0x79e1fce3, 0x7ef1e101, 0x0155f1dd, 0x6c2adb6c, 0x5285ec1f, 0x5aa07b1f, ++ 0xc62d5600, 0x48efa3ed, 0xe3c29dcd, 0xfa956d60, 0x9c30a760, 0xabc3201f, ++ 0x08edc9c3, 0x40c5e153, 0xc339c002, 0xdf895fd5, 0x8530be73, 0x82fc877f, ++ 0x26519df4, 0x5b3be89a, 0xef1933d0, 0x4546b7c7, 0x3856ab8e, 0x1470bb25, ++ 0xb3baf239, 0x893e303c, 0xe220b67e, 0x92338efd, 0xcdd4da7f, 0x44c92fc8, ++ 0x9a42f25b, 0xfa8c96d7, 0xfcc398d0, 0x732f6c79, 0x6cbad275, 0x0f6485f6, ++ 0xbeb8ecda, 0x6f78a507, 0x3b1cecfc, 0x41e3a3fa, 0xe078c42f, 0x920b8c0e, ++ 0x7ea26b3d, 0x13f17cf2, 0xd41ffef8, 0x5bee8130, 0x267cf1e5, 0x22a2f0d6, ++ 0xd342779e, 0x814adefb, 0x208f79e2, 0xaaa9febf, 0x5daf70b7, 0x6f806242, ++ 0xc5137ee1, 0x794e4f19, 0xf343d72a, 0x06def8f0, 0x0af2ef13, 0x8eb0cdda, ++ 0x12952f0d, 0x343f2efe, 0xf4fc2de5, 0x3a21d797, 0x9453dd23, 0x246705fd, ++ 0x2fec877f, 0xbf5ae390, 0xef24fc90, 0xee85ffa0, 0xeca8d887, 0xb2faaf1e, ++ 0x48eeb7f5, 0x8141e9f2, 0x3f0287fb, 0x52a1fee5, 0x342b33ad, 0x78c8f26f, ++ 0x7b2b8e7e, 0xf642dc79, 0xed233cf7, 0x755ef4a7, 0xd2f40eaf, 0x5a452dd2, ++ 0x5ba5f394, 0x8e580dd2, 0x78550577, 0xdd597c1f, 0xfcf92a73, 0x6bd1e122, ++ 0x8edb3ed2, 0xef5c520d, 0xfe716187, 0x6a5a09f8, 0xc7c2407f, 0xb049b078, ++ 0xb62d90dc, 0x6638faa0, 0x291d499a, 0x760b549e, 0x6573ae31, 0x0cb75f2b, ++ 0xdb5edaef, 0xece79c74, 0x582dc191, 0xa7dbd496, 0xe1bdbf93, 0xdfd416e2, ++ 0x1d2f57bc, 0x65fc89bd, 0x13da1b5a, 0xfd280db7, 0x7938cf6e, 0x050fe5be, ++ 0x81ad3bfe, 0x74fefc59, 0xf0912ce9, 0x8a36be27, 0x0d78d7ec, 0xbeb11b53, ++ 0x2545eb80, 0xb1d38955, 0x91c716ce, 0xcc72583e, 0x70aab716, 0x3f160fd8, ++ 0xe10931ab, 0xaaf8dd74, 0x537b4fe4, 0xfa441aef, 0xd5f1bcfb, 0xa75e2735, ++ 0x5f7952bc, 0x38e45c32, 0x55f168e9, 0x5bc1cf39, 0x97915975, 0x670715e1, ++ 0xf4b1ffa2, 0x295ab3a5, 0xbf84d2cf, 0x5fc72ba3, 0xa45e0f4b, 0x671cabb8, ++ 0x922efaf5, 0x69ef0d5e, 0x3852fdf1, 0xfc78e4fe, 0xbf8f10be, 0x527bc01e, ++ 0x67ffbc5a, 0x2f52fba2, 0x7b17f74a, 0xfcf8ff60, 0x952e7f65, 0x95277ebd, ++ 0x5465fc87, 0x522e7b7a, 0x6132d6bc, 0xc5247e44, 0xddab4ef3, 0x29261329, ++ 0x0f547de2, 0x0da9f78f, 0x3de35fdc, 0x0fdfa1a6, 0x13d09ef0, 0x59ef2eff, ++ 0xfebaf749, 0x1633ca70, 0xe316bdd7, 0x7178216d, 0xc28ce5de, 0xef3845df, ++ 0x9c614676, 0x43efb4ad, 0xacbfe62d, 0xe8b5fb15, 0xa715830f, 0x77a26a62, ++ 0xdf9e45ff, 0xbf4e53db, 0xb8dd7547, 0x8ffff758, 0xb89e7d8b, 0x8f2701d8, ++ 0xa47cc98b, 0xe172adc4, 0x6392cd3d, 0x2155a8ae, 0xcdcda27c, 0x8e6d29e3, ++ 0x87c3a24c, 0x757199dc, 0xaa6de321, 0xf88bfee2, 0xd0a88e59, 0x3cc551e7, ++ 0xca3f160e, 0x13bd3c77, 0x5db65f54, 0xf7a48de1, 0x9ea9ff9f, 0x1df5fbee, ++ 0xdd2c73bc, 0xc7f30faf, 0x8dd555b5, 0x74fe418d, 0xb9b2c746, 0x8fe14ebf, ++ 0xb8f16163, 0xcb72fcd1, 0xb7dfa4ab, 0x28198361, 0x66fdc3b7, 0xcb90af78, ++ 0xcaaa5775, 0x1520658a, 0xc7862def, 0x82ce7ee5, 0xffa0386f, 0xc9152ab2, ++ 0x573e390b, 0xfc322552, 0x269291dd, 0x72e2904d, 0x6a59e255, 0x4dc6ec97, ++ 0xc45492a6, 0x684e77f3, 0xaaf2914d, 0x5afb559d, 0x677de133, 0x77df4083, ++ 0xaefc5eb8, 0x466fbbb6, 0xa4dfed2a, 0x47647ba6, 0x91b6bdf9, 0xef9e3cf1, ++ 0x5bdac25d, 0x731fa12b, 0x09e3dff0, 0x9e21b3f7, 0xee125ea1, 0xc2527f87, ++ 0xbd252783, 0xdec93de4, 0x25f4912c, 0xfc70bdf9, 0x2e04f3f9, 0xebf346e7, ++ 0x6f1a4eff, 0x9b495553, 0xae77cf03, 0xd93ca18a, 0x77a15554, 0x70778c84, ++ 0x7b67cf02, 0x8983e310, 0x1e41f1a1, 0x0b8f0c07, 0xb4ae7cca, 0x11338fef, ++ 0xbf010fde, 0xb5e63946, 0xe941f8f2, 0x9f74e5cb, 0x5c9d786e, 0x1d643f6e, ++ 0xc71eb7ba, 0xe618bef8, 0xe25e05cb, 0x325d8bbf, 0x68a1f2f7, 0x8e3b9f84, ++ 0x7bc6177e, 0x4462d1c2, 0x9c57347e, 0xbc77f784, 0xce28616e, 0x45a4f184, ++ 0xc6cfd5af, 0x4ba504fb, 0xdc214f8a, 0x2868d497, 0x6bd1701f, 0x6d7bf4d5, ++ 0x5d2bfcb2, 0x80d1b9d2, 0x3382b9ed, 0x55ed86ca, 0xe73ed815, 0xa4f45ed9, ++ 0x3ab879b3, 0x27fde7e0, 0x6e9113de, 0xde7bd4de, 0xba5f7e46, 0xd5338a40, ++ 0xa4bd3970, 0x71868167, 0x3721527d, 0x03ff495f, 0xf52e83f9, 0x28fc5294, ++ 0x0a1ef301, 0xe955e587, 0x62c7204b, 0xdfd8e586, 0x3cfebf2a, 0x9cf044c1, ++ 0xd70c7200, 0xc780bf13, 0xffcfc3e7, 0xa31f84a0, 0xf8d1a5c9, 0x551fca30, ++ 0xc14fa719, 0xdb8e523a, 0x15f3efd0, 0xba05d7d4, 0xfe1a399c, 0x1d784ae5, ++ 0xff73e927, 0x2340861b, 0x008000b6, 0x00000000, 0x00088b1f, 0x00000000, ++ 0x55b5ff00, 0x655b685f, 0xb97dff14, 0xb649b7b9, 0x76dabbc6, 0xa6f06bad, ++ 0x34d7529d, 0xe2accbbd, 0xc6dd2c86, 0xd4687590, 0x366e8c97, 0x4d714be2, ++ 0x1f486452, 0x25a8a584, 0x28226f6e, 0x95979882, 0x0f6516f9, 0x15918419, ++ 0xd68bea5a, 0x8bd9683e, 0x70e28e31, 0x3fe0a8b0, 0x77ce78d0, 0x6db935ef, ++ 0xe179845e, 0xfbefee72, 0xf9ce77ce, 0x6bf73f9d, 0x0a39e834, 0x31196c34, ++ 0x7a0e3005, 0x0bd07bf6, 0x4fa3e6bc, 0xe079b803, 0x377560cf, 0x5f192be0, ++ 0xc81c791e, 0xa0e829ac, 0xeac74bf5, 0x3cd23d41, 0x8bcdc8ef, 0xe051ee74, ++ 0x949f45d6, 0x5a93f7db, 0xce9311ee, 0x15483d25, 0x361f9cdb, 0xc70f403d, ++ 0x3a26aeb1, 0xf1411f21, 0x713eb59c, 0xd03dc80e, 0x2a24b845, 0xf2e12081, ++ 0x965e3bf1, 0x9f350273, 0x75b0d3a5, 0x5636c36b, 0xaff9fa76, 0xbcf6c332, ++ 0x45267c4d, 0xfe9b8746, 0x517666a6, 0x17d89a92, 0x379c7e20, 0x3f7992cd, ++ 0xb6df2c92, 0x45c8ecf3, 0xd3f65e5b, 0xd7926ea1, 0x4c216145, 0x9bab22fe, ++ 0x8ded7882, 0xc231f303, 0x0a2bbb7d, 0xbbd49461, 0x20efc755, 0xce3a1bed, ++ 0xa7103e52, 0xf4013e64, 0x02d031db, 0x544f48b6, 0x118d3cba, 0xfb581bd2, ++ 0x986ded83, 0xef6fcc86, 0xa201454b, 0x416e4210, 0x0d15bf90, 0xff929f13, ++ 0x0b026bd9, 0x242d92a4, 0xeb483c60, 0xfc5ade1f, 0xd733d684, 0x22914e84, ++ 0x634afc5d, 0xbaef6957, 0x4c9f13a6, 0x2c0d47f9, 0xeb59df8b, 0xb42f1125, ++ 0xa9b2eba9, 0x8827bf48, 0xd28fa80f, 0x07429417, 0xfe493df9, 0xae367798, ++ 0xabc20c15, 0x8cbdd7a1, 0xd8175dcf, 0x63595b4b, 0xef1767bd, 0x0851505f, ++ 0x27a75e4b, 0x56126788, 0x306bd27f, 0xeb3633ef, 0x69eaf1a4, 0xf55eb904, ++ 0xafdc7dd5, 0x18acc233, 0x56b52f5c, 0x0507f575, 0x6d357d42, 0xdd2a9b9f, ++ 0x75c83154, 0xc74deb74, 0x5111de4f, 0xeb6dafee, 0xc93f8b03, 0xfb2aa07a, ++ 0xbdde7a74, 0xbb3b319f, 0x3025a8b7, 0x08634882, 0xcbaa2378, 0x4253273a, ++ 0x3e3f28a4, 0x7996624f, 0xafd086e2, 0xebe67784, 0x260e7b2d, 0x54f30273, ++ 0xeacd25df, 0xa2c3a58f, 0x49fd2390, 0xa5f75c82, 0x04e72f1b, 0x098a5cf1, ++ 0x60f9c3d3, 0x29c7ca25, 0x218f3f3b, 0x8b8a2d87, 0x38d7bdac, 0x3d4b3c04, ++ 0x9a7ea7ec, 0x2801fbb4, 0xff9eb8c8, 0x88515020, 0xd8b565e7, 0x6349f3c7, ++ 0x4cc7fd26, 0xc0e81948, 0x9d79bb5c, 0xe6622733, 0xa479eb38, 0xfd57f39d, ++ 0x3c96edfa, 0x5c7b8ba4, 0xd7ea5b38, 0xcdccb76f, 0xa7e8fe79, 0x72f084f7, ++ 0x3d76b3dc, 0xef52563e, 0xdd37e49b, 0x2eb8d557, 0x8c4b5d40, 0xad445f02, ++ 0x85323e78, 0xf29bfb97, 0x7df3c23b, 0x7075f437, 0x9286e099, 0xb33c7028, ++ 0xfdca255a, 0x24a4a1bd, 0x3d69f676, 0xe7b62183, 0x791cf1ad, 0xe1ffe420, ++ 0x2a67f0d2, 0xd78a65d7, 0x4dc3789d, 0x9d95893d, 0x73f39478, 0x1b7f797f, ++ 0x3efbc36d, 0xec717fda, 0x5cffb5ff, 0xc9bdbabb, 0xfd36bfff, 0xb9d07dd3, ++ 0x39740677, 0x19e6ff2f, 0x43a43dd6, 0xe84af1f6, 0xe50f7957, 0xdf0df185, ++ 0x55cfb943, 0xff9a315c, 0x65a77cd5, 0x7ffb7bff, 0x6dbfc8ea, 0xbd2d5799, ++ 0xb6fdfeed, 0x5e2515ff, 0xae47b8e3, 0xf0b4607a, 0x60062d1e, 0x2b1ef0b4, ++ 0xc1f0b975, 0xfd2e43ca, 0xae836b43, 0x03f5f1fd, 0x3727fdae, 0x54fc2e63, ++ 0xff4bb0f5, 0x5cc70fc8, 0x29fae9f8, 0xdfd1fe97, 0x6761705f, 0x73a8277e, ++ 0xf71dcf5b, 0xdbd2e2bd, 0x15e6e337, 0x7af3739a, 0xcbcdde78, 0xb9ce1bb1, ++ 0xdde50df9, 0xfcf6bafc, 0xde506bdc, 0x16fd7fb3, 0x9de0fbe4, 0x4eb22ff2, ++ 0x581deaf7, 0xb788ffe7, 0x650fdd6a, 0xf70bde55, 0x4f60f5bc, 0xc7a61d4b, ++ 0xb967e90c, 0x73e7e43c, 0xdfb33eef, 0x11f7088f, 0xf7a3bae4, 0xadd07b0f, ++ 0x0008b02f, 0x00000000 + }; + + static const u32 csem_int_table_data_e1[] = { +- 0x00088b1f, 0x00000000, 0xe733ff00, 0x51f86062, 0x39fbc10f, 0x716e1819, +- 0x0143f822, 0xd9433117, 0x1017fa40, 0x606463bf, 0xbc48cf78, 0x040e357e, +- 0x033b2f7b, 0x3e200ac3, 0xfef03ec0, 0xc95c481a, 0x4ebb3f4d, 0x622ed1d0, +- 0x067e2ef0, 0x0c023d86, 0x1082590c, 0x54417ffe, 0x08fcddf9, 0x651898b6, +- 0xf5012976, 0x93320003, 0x038009d3, 0x00000380 ++ 0x00088b1f, 0x00000000, 0xe3e3ff00, 0x51f86066, 0xb8d3c10f, 0x72361818, ++ 0x0143f821, 0x684333b7, 0x0606163e, 0xc77e2001, 0x9ef0c0c8, 0x38330491, ++ 0x207eec10, 0x27880abb, 0x7dcf5071, 0xe62f1143, 0x9f5d9fa1, 0x163d76a0, ++ 0x837f7818, 0x03109db0, 0x03308b83, 0x84089883, 0x55045abf, 0xc1085ede, ++ 0x9941243e, 0xfa80e75d, 0xa5c3d401, 0x0003804b, 0x00000000 + }; + + static const u32 csem_pram_data_e1[] = { +- 0x00088b1f, 0x00000000, 0x7dd5ff00, 0xc5547c0b, 0xbddcf8d5, 0xeecddd8f, +- 0x21079b26, 0x086e3c21, 0x4bc60a22, 0x9bade102, 0x88b46204, 0x7d608a89, +- 0x8420182d, 0x96d22247, 0xedf7ed7e, 0x5ab11062, 0x68db151b, 0x34105db1, +- 0x060b28da, 0x2df0980c, 0xaa5694a0, 0xd1f58df1, 0x90cbc8a0, 0xf87e8784, +- 0xce7feb69, 0x7bbbb999, 0x7c486eef, 0xfefdfbf4, 0x730ecfe9, 0x3399dee7, +- 0x9ce735e7, 0xc92b3339, 0x210cb102, 0xbbf81be4, 0x22ad909c, 0xa46c6421, +- 0xe5a22aec, 0x79fc4218, 0x8126c08e, 0xafaed090, 0x4234908e, 0x54cd364e, +- 0xec84d9ad, 0x2e8473ce, 0x0327eda7, 0x6d2b0185, 0x76f6de2f, 0x4beb44a2, +- 0xb41289b6, 0xf1d9765b, 0x4275cefb, 0xd6d5ea00, 0xd12607b6, 0x9136f77a, +- 0x935da06c, 0xd242d390, 0x23623909, 0x61754fec, 0x559dbe7d, 0x7ddfac97, +- 0xd9578c2b, 0xfa76256c, 0xd12691fd, 0x9b65f503, 0xe3a10084, 0x8f71d92d, +- 0xb7f68032, 0xed042020, 0x7a6fad2a, 0x845d5150, 0xfdebb5dc, 0x212776c4, +- 0xa2367c27, 0xca8f382a, 0xaa4228e0, 0x064a5b02, 0x1aabefd0, 0xfb42cd05, +- 0xaa775aaf, 0x6aabe013, 0x69102f92, 0x1c1a8b7f, 0xc6c11d44, 0x78c086fe, +- 0xbc703b7b, 0x1830f26d, 0x3bebf2af, 0x3cc22215, 0xb77c0f65, 0xf301c284, +- 0xe13dc7d6, 0x74f1c7ab, 0x9a792e7c, 0x5bdf478e, 0xc1a09cfa, 0x885a9714, +- 0xdce8e017, 0x84fd9f61, 0x52b7e613, 0x9e8aee19, 0x30ed9cc7, 0x7ac0aa8f, +- 0xf009c4a5, 0x8fe657ad, 0xa8b7f48a, 0xf846f7e1, 0x7bfa73ea, 0xe5cddaa3, +- 0xe9451f09, 0x8abd48f0, 0xf6904f10, 0x5280a44b, 0xf9e4497e, 0xd2324207, +- 0x4883517b, 0x7fa45b54, 0xfa42794a, 0x9b7fffd1, 0xc1e293fe, 0x6c0aeadf, +- 0x6dd08eca, 0x16681b99, 0x3769dba1, 0x5dd4a3a7, 0x5ebfdd10, 0xa0f4003e, +- 0xdcf9d4f0, 0xcbe43e58, 0x4fad72c0, 0xd6fdbc45, 0x7acb0237, 0x1fcf869f, +- 0x72c78df3, 0xe583cf9d, 0x58a57c1f, 0xf8657c06, 0x6cdf06de, 0xbcfa372c, +- 0x5f49fcf8, 0xbe0d9625, 0x8cfe7c1a, 0x8d96056f, 0x7f3e3f3e, 0xcb06b7ce, +- 0xcb0eafa0, 0x5a2f40ad, 0xf802f936, 0x035f76de, 0x20becd96, 0x6be9df3e, +- 0x8e7ef2c6, 0xa4c9c4c7, 0x4878a250, 0x253710f4, 0xee99493b, 0x3d699429, +- 0xd3d58ca5, 0x2a17f66f, 0xa5ee9eb4, 0x01978a75, 0x5685438b, 0xc3501f5a, +- 0x92ff07da, 0x7d68d914, 0x0fb59fb0, 0x6453dfbd, 0x75a1f5a7, 0x3af87dac, +- 0xad02517f, 0xf6b00f0f, 0x45431b8b, 0x38bf5a0e, 0x5b73dac8, 0xd693b148, +- 0x9eac4373, 0xec53c077, 0x36bcf5a2, 0xc0f82f56, 0xeb489c5f, 0xfbeced05, +- 0x51011d89, 0x61d2c675, 0x4edeacab, 0xf9d6ad28, 0x1348f4af, 0xef515d68, +- 0x8fc51a24, 0x948f5aff, 0x7b21f149, 0xbfe43db0, 0x149bdb09, 0xe1bfb60f, +- 0x76fac0af, 0x87ed8bd9, 0x5d584bfd, 0x17fb62f1, 0xbd629ffe, 0xbb63f659, +- 0xd58fa56d, 0x0fb63f15, 0xfb06b958, 0xb00729df, 0x07cad47d, 0x12a77db1, +- 0x5687f6c0, 0x4a99e63d, 0xf782b5eb, 0xb48fc0b7, 0xc03924ac, 0x328cc14f, +- 0x05ab4fca, 0xf7f81b32, 0x28e980bf, 0x54ceae5f, 0xfeb70e50, 0x9009e0ad, +- 0x834bfc5f, 0x7f27fcfa, 0xffdf8d95, 0x6991fb11, 0xfdef623f, 0xde3abde4, +- 0xabde4fd0, 0x0d3f7a95, 0xbdad5ef0, 0x7d6cfd6f, 0x9e11a275, 0x7ef4ab57, +- 0xae3c20b6, 0xef2bcdbe, 0x7846c9b5, 0xf7ac5b5e, 0x49e113b3, 0x4d3c1bee, +- 0xd3f11b6f, 0x3f1876f4, 0x7e9e117b, 0xcc67837d, 0x8cfc463b, 0x9f8c2779, +- 0x664fd803, 0x7a69fadf, 0xa69f88c7, 0x79f8c277, 0xa835e71b, 0xf31af36f, +- 0x633f11ae, 0xe7e30dde, 0xbb278423, 0xff6cfd6f, 0xed9f88d0, 0x73f1861f, +- 0xa0b9fb14, 0xf82af36f, 0x829f88c8, 0xe9f8c28f, 0xea2e7ec6, 0x3fdb3f5b, +- 0xfb67e232, 0x7cfc6147, 0xd25cfd89, 0xfc1579b7, 0x829f88c3, 0x63f1847f, +- 0xd19fa011, 0xf9a7837d, 0x9a7e2353, 0xc7e30d3f, 0xed8cfd81, 0x8fe33c1b, +- 0xfe33f118, 0x693f1848, 0x427dd002, 0x3e69fadf, 0xf34fc462, 0x067e3091, +- 0xfa533f61, 0x47f1af36, 0x7f19f88d, 0xe19f8c34, 0x2a42af38, 0xa10f00f7, +- 0xee7ab8fd, 0x2349e767, 0x0c9e767e, 0xec52e7e3, 0x27ed1a67, 0x267ef7a7, +- 0x33f11a76, 0x9f8c33b1, 0x95cfd8f1, 0x6767eb7d, 0x3b3f11a7, 0x29f8c33b, +- 0xdd5cfc44, 0xec4d79b7, 0x6267e232, 0xfe4fc317, 0x89c5355b, 0x85ae9db4, +- 0x993f489a, 0x08f1e1d4, 0x59ba2eb4, 0x046b745d, 0xb75112ec, 0x479b4837, +- 0x1b3bdfa4, 0x457ef393, 0xa28eeda2, 0x8b979872, 0x76d1635a, 0x04f8d247, +- 0xec939d83, 0x53d43149, 0xde18074b, 0xd43657ef, 0xf67fded0, 0x4cf686c5, +- 0x9ea19e6f, 0xf0d13955, 0x229aa0fe, 0x8ac87d43, 0x67ef0cab, 0xd435affb, +- 0xd8fcd673, 0x7505fef0, 0x17ed0d73, 0xda1957d6, 0x332c0a2f, 0xfc3647d4, +- 0x4bfde187, 0xda197782, 0x95fe6d2f, 0xe8747da1, 0x7f3d4321, 0xf78663ff, +- 0x306db6c7, 0xf83b8fb4, 0x427da18c, 0x7d4356fb, 0x269db1d2, 0x3ee9cf3b, +- 0x45d79232, 0xecc27be0, 0xed054cfe, 0xc14b90bd, 0x89c032ba, 0xd76efc76, +- 0xa530f57c, 0x76e7b2af, 0x17d28d35, 0xbae84a68, 0xf2a0385e, 0xfcfa76c2, +- 0x17bd13a7, 0x9ff3e9ba, 0xdd4bde2a, 0xca53ec71, 0x80c9020f, 0x6940b552, +- 0x6647bf6e, 0xf59458fc, 0xf443f0f5, 0xf74b6afb, 0xb75a64f0, 0xc0f58588, +- 0x2c107fbf, 0x2209a7c8, 0x12f781a9, 0x82fd04ac, 0x9e0bb27b, 0xebf147f0, +- 0x0e54419a, 0x6bbf4885, 0xd8066f64, 0xbe561b19, 0x643b07ee, 0xaf3a20f5, +- 0x213c8401, 0x0ff21ebc, 0x9a0fdfa3, 0xfda5e19f, 0xa76a1559, 0xd0af8f47, +- 0xf8e147f1, 0x73fe300d, 0x1d6f8c3d, 0xbe30de3a, 0x61a5706d, 0xc7429b7c, +- 0x607b5377, 0x7c7c7be5, 0x8489844a, 0x87bc2f3c, 0x57075be3, 0x28f7f8e2, +- 0x1e895fd4, 0x7e3c213f, 0x2ecbc833, 0x9c6c7f18, 0x689d0ff9, 0x2ae0ff9c, +- 0x3615fce3, 0x0f2b3dff, 0x7013f1f1, 0x43857bfe, 0xab83fe6c, 0xacadfcd8, +- 0x89f8f0df, 0x87effc61, 0xd3dabff9, 0x1b2673fc, 0xb1643fe7, 0x3656fe71, +- 0x8f2b1bfe, 0x389df1f3, 0x71c29bfe, 0x8b21ff36, 0xeac57c71, 0x947f80d5, +- 0x009a84ac, 0xa40c9f1d, 0xb03fa98a, 0xca071d0b, 0xa9942911, 0x30b5f909, +- 0x69f8e114, 0x2fb7e302, 0xa1bf2812, 0x73e3f1be, 0xad9aa012, 0x9c5dfa80, +- 0x163517d7, 0xb097a02a, 0xf32bfa9d, 0xcd15a838, 0x5937f222, 0x405c0d6b, +- 0x166cede1, 0x58af50fd, 0xfa00253b, 0x6e4adaaf, 0x24ef832b, 0x9fe78212, +- 0x86c9723e, 0xcb9979e8, 0x91f27579, 0x0b7928f6, 0x644551fb, 0x6f850d44, +- 0xd8c1301a, 0xea63fd48, 0x5fea1107, 0x0cfd407c, 0x13f25942, 0x11f78d99, +- 0xdea097f5, 0x6825fd4e, 0x7e256427, 0x2b7bbb47, 0xc65fc283, 0x6258ffe1, +- 0xcdf1faf2, 0xe54fc042, 0x8f9f8bf3, 0xb6f53f46, 0xf48a0e15, 0xfc731c08, +- 0x9d3a86a9, 0xd4e81f97, 0xd81ac3bd, 0x557e2020, 0x8a3957c0, 0xafb72126, +- 0x8eb8a2c9, 0x252effbc, 0xfd45267b, 0xf723c40d, 0xb2dfefa7, 0xa6e4185c, +- 0x58f4cee3, 0xe13ad8f3, 0x5ca0b2c9, 0x78cb2c93, 0x1a6dae42, 0x481ed32d, +- 0xb8fe47b9, 0xebdc6a3d, 0x99f58d4a, 0xa77ac665, 0x142d91ec, 0x8172ceae, +- 0xcefda7ac, 0xd76c6d9a, 0x525a71c7, 0x78f99d18, 0xbe0ce965, 0xc1e65059, +- 0x79d23763, 0xab7d9bb6, 0xbb7d53c3, 0xa0585d4c, 0x011fbfa7, 0xf0d3faba, +- 0xd9bb1fbd, 0xcef0cdbc, 0x329e6d96, 0x73d9cf3a, 0xb7f000c4, 0xefbffe19, +- 0xb92c7872, 0xb0f35cb4, 0xf3b12c4c, 0xa37fc331, 0xa09f3cd7, 0x4df0eb0c, +- 0x8ce7e695, 0xfa708e6f, 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0xac2d846d, 0x3225fca5, 0xf1a0db9f, 0x131e4aef, 0x4ffa8ef1, 0xc31fae21, +- 0x8d2b5fb9, 0x5b7c17e7, 0xfa374b67, 0xd4afc303, 0x1757bc0a, 0x294ad9ef, +- 0x539e6c57, 0x3308ec2b, 0x62df1678, 0x0e9d9bf3, 0x9c08bf91, 0x644a9c36, +- 0x71e0eaf9, 0x5d33a359, 0x474feb94, 0x7986fe53, 0x739c5e7a, 0x2e04cfcc, +- 0x65fdc5fb, 0xe4ccb943, 0x5bc99a66, 0xf9421f23, 0x9e0cbc31, 0xbe53f64c, +- 0x8df8745f, 0xf57fd23c, 0x69179c5e, 0x0f3fa877, 0xcfc7aefb, 0x481b5c70, +- 0xc6327762, 0x6fc3bef8, 0x359c264c, 0x9f32fa9c, 0xbe5ae5eb, 0x7d39b8ea, +- 0xbc492b46, 0xbc49358e, 0x8730ed8e, 0xf27ea952, 0xfedd941e, 0x7a1a7d08, +- 0x476117fe, 0xfaf5e660, 0xface871e, 0x171c5d0d, 0xe2de6ea6, 0x79f82bfe, +- 0xbff6c28d, 0xe21e7c61, 0x1ae22be5, 0x7ba85d10, 0xb86612af, 0x31349ef3, +- 0x8727bc7a, 0xbbe32332, 0x451dd68f, 0x06a1af7e, 0x02491f98, 0xc7e8b3f2, +- 0xdef7547c, 0xe5812e77, 0x76f2c74b, 0x95bf3054, 0xadf90327, 0x4d554e27, +- 0xf90f8c8a, 0x27e7990e, 0xca2c8724, 0xfbe59e56, 0xc234390b, 0x73ef5172, +- 0xce92bf1c, 0x527580e5, 0x6c71d937, 0xf9ab749d, 0x05b7436e, 0x7bd81ce8, +- 0x13bec2c1, 0x81bddab9, 0x85f0e1d5, 0x19f91267, 0xa76e78f0, 0x1bc389f6, +- 0xabf3d126, 0xcede3787, 0xc6a52fce, 0x23e5f8a8, 0x2f28b2fa, 0xe3a9933a, +- 0x99f76d78, 0xc2ad604c, 0x647ea7e8, 0xc1d77afc, 0x4f60d7e3, 0x90a73b02, +- 0x00e38f20, 0x5bad4426, 0xcb16fed3, 0x653a6a23, 0x8c1e2457, 0xf0703ef7, +- 0xc223eafc, 0x9013f101, 0x6dcf4c5c, 0x7ce9adbc, 0xad53d19d, 0x1b1e9804, +- 0xde3e145a, 0x2fcc5bca, 0xb03e1d19, 0x36fe88fb, 0xf7e6bf3a, 0x02bcec1a, +- 0x18fb3267, 0x6ff4282a, 0xe8affec7, 0xc875ca11, 0xdcfe026f, 0x9b83eec2, +- 0x11a7c77a, 0x5f7a87ee, 0x178bc477, 0x083dd0ef, 0x97227a92, 0xe3b117d7, +- 0x39f8327b, 0xdcf389c2, 0xeb989d8f, 0x9fcf1499, 0xaf1e60f9, 0xef2125b7, +- 0xbc516576, 0x3217b4fb, 0xdecf39f8, 0xe209df6c, 0x812dbfa7, 0xdbf5a7dd, +- 0xfce8b9f8, 0xe9cdc7fd, 0xa5db7714, 0xaa3f1469, 0x405fde0b, 0x2fd8f8f7, +- 0x782b7e63, 0xd61bdd90, 0x742db4b6, 0x2ea3a1c5, 0xc5f1fb83, 0xc8fbfc6a, +- 0x7bf8c5db, 0xf510cce0, 0xee130ed1, 0xa2855ef7, 0x8679676d, 0xf436f92b, +- 0xff0bf7bf, 0x8512c0fb, 0x81ef25e5, 0x077bf0ae, 0x54b03f7e, 0x85fbd1f8, +- 0x1e5a5e5f, 0xed9727ed, 0x7ee9a786, 0xbe2b9960, 0xac487e1f, 0x6c5c1cbf, +- 0x451607dd, 0xe4487bcf, 0xa3b90f77, 0x10ca4f9f, 0xf21f37fe, 0x3006ffc9, +- 0xebbe901e, 0x5c58130b, 0xc4ca6fbd, 0xb1c179b8, 0xfdeec0cd, 0xbffdc57b, +- 0xc286f7a1, 0x3abc59f7, 0x35fe73d1, 0x09dbf31b, 0x5ee71790, 0x195e246b, +- 0xd720fef6, 0xa82fb8b7, 0x868d38d5, 0xe560afde, 0x652e7913, 0x90b17de8, +- 0x04def57f, 0xaf9ef22d, 0xea8b6036, 0xd36f3b7b, 0xf9f8462e, 0xf46f816a, +- 0x73c8e6fd, 0x67b29d8a, 0x0bdd0671, 0x3e59fb58, 0xb8b01c8d, 0x08e57c85, +- 0x112c72be, 0x6dcae8f1, 0x77e2e26b, 0x8fbb3f84, 0x6b077dfb, 0xcc2d0a7b, +- 0x92036aee, 0x6aa3ee9f, 0xac9ebc83, 0xc9ebc05d, 0x579e76fc, 0xf25078ae, +- 0xbee624bb, 0x067d134e, 0x795a967e, 0x327036fc, 0x1f812f2c, 0x7e78a71a, +- 0xb1e788bf, 0x7d049a38, 0x779ce90b, 0xd2724ba5, 0x78b171f7, 0xea6abe5a, +- 0x6f9ee45b, 0x9bc41f86, 0x16327e42, 0xf0cf3f47, 0x1a632b7c, 0x4c570bab, +- 0x144f75c1, 0xb8439a7e, 0xdd89bba9, 0xdb7a14ec, 0x413bec9b, 0xbf66bef1, +- 0x5fdf07b8, 0x792219d8, 0xf7cb02f4, 0x5b7d6dfa, 0xcc1e79eb, 0x836bc1ee, +- 0xdefa4e09, 0xc92bb6b5, 0xf6fd4099, 0x54c9c486, 0xcec9761f, 0xb457ec24, +- 0xf2405c9f, 0xdfe328ac, 0x61a9d465, 0xb4ae6f96, 0x5e92b679, 0xa27b3897, +- 0x3a0dbfee, 0x58f3866f, 0x0902f6bf, 0xe76fe327, 0xe0c85e6f, 0xf8feaef1, +- 0x719399e7, 0xcf36e9ab, 0xf07ba26e, 0xba5557ad, 0x7e4ef326, 0x4eba6163, +- 0x6f3674f3, 0x16cf4b49, 0xe8357e3a, 0xee343b0f, 0x367f155f, 0x6f8b23cb, +- 0x86907bed, 0x50976f83, 0x73d03cde, 0xc08d44bc, 0xfa3d7f77, 0x6bfa38e7, +- 0x5bb09300, 0x69256b33, 0xb86fc8b9, 0x8fbb7b1d, 0x41b9d266, 0x316fd93f, +- 0x295267b5, 0xbdb6d62e, 0xf2913a97, 0x1ade0e8c, 0x92e95deb, 0x87303cd9, +- 0x894a1ff2, 0x4669efa4, 0x5f0095df, 0xff942007, 0xf1c894c0, 0xfb6fffa6, +- 0xae38413f, 0xeca286b5, 0x561390df, 0x47563eed, 0x7bb0b61e, 0x8927ba75, +- 0x92ea9efc, 0x2c0cf5c0, 0x674ec86e, 0x78f0bdd2, 0xf0ccc54a, 0x10cdf508, +- 0x9ee9db34, 0xeff32836, 0xff99b2cc, 0x9ff62e9e, 0xd0f60e61, 0xc53396f7, +- 0xe82ce2bd, 0x06bef363, 0x40bad661, 0x0f3b5333, 0xb72dac9c, 0x32a3ef06, +- 0x901038af, 0x4cc1ff49, 0x9592edb3, 0xf1007f7d, 0x37223df4, 0xe4325c33, +- 0x13fdd321, 0x962f5eff, 0x8f02eb9f, 0xefdc5c33, 0xdf412a50, 0x80439659, +- 0x09df77dd, 0x1def7121, 0x58d98f9f, 0xd77dd1a7, 0x893b689d, 0x367e1e4c, +- 0x23f10e7f, 0x7427e3c7, 0x2c33531f, 0x293e88d0, 0x9eba6998, 0x0c7ceb74, +- 0x375b0266, 0xe0785d75, 0xfb91b2c9, 0xdbd76742, 0x50bbe8e7, 0xdf62e5c9, +- 0xc9ad3a8d, 0x04975641, 0x7ec3fdcd, 0x39200f2c, 0x66626d73, 0xf777c8c6, +- 0x3df601e0, 0xf777ec45, 0xcce5eec4, 0x8cb4ef91, 0xfaf73fef, 0xc426eb97, +- 0xd5872ac7, 0x4a3e2329, 0xd07739ad, 0xcd39e0f9, 0x8d399893, 0x996d03be, +- 0xfb3116c8, 0x53bcb1a7, 0x5c092ae0, 0xe4bfc4e5, 0x07fbbe32, 0x389f1786, +- 0x8265f6bf, 0x9252ae9f, 0x91587c30, 0x43881dae, 0x5fa19dab, 0xe159efa7, +- 0xe53af9a9, 0x566d5bb7, 0x166fe527, 0x846937a2, 0xff2b26de, 0x7ef8c1ee, +- 0x4d8e562b, 0x663e8328, 0xcb2b4e7f, 0x628fd78b, 0x6b8f34f7, 0xb27fbf9c, +- 0xfd10a678, 0x1bcca78f, 0xd16ef945, 0xb164e62f, 0x30e51bfc, 0xe98390c7, +- 0x80e7ffc6, 0x3c91977c, 0x817fff63, 0x802a2fc1, 0x72134681, 0x48d7f834, +- 0x5c6f143f, 0xbf431fa8, 0xd9722379, 0x57f9c891, 0xf18f4be8, 0xec9d5dec, +- 0x836f9634, 0xcf05ffbf, 0x10785073, 0x00107850 ++ 0x00088b1f, 0x00000000, 0x7de5ff00, 0xd5547c0b, 0x733ef7b5, 0x9993331e, ++ 0xf20f264c, 0x04278020, 0x21842a28, 0x38880840, 0x8d069009, 0x8808889a, ++ 0x420100ca, 0xb9113248, 0x9db57a5e, 0x5688a189, 0x8db4b46d, 0x04076c5e, ++ 0xc075168d, 0x740d0340, 0x6af10530, 0xad282a35, 0xf0c5068f, 0xd0f09210, ++ 0x77adad8b, 0x49f7b5af, 0x90999ce6, 0xbf77eda8, 0x9fc5f7ef, 0xfb3ecdbf, ++ 0x5ed7bd9c, 0x5ed6bfeb, 0x48c7ed7b, 0xba6200ca, 0xe1af908c, 0x0e421aef, ++ 0x0190848a, 0x3e67693d, 0xe213c74d, 0xb60736cf, 0xf6848408, 0x249dadfe, ++ 0x71a67211, 0x20ce6ab6, 0x7358df64, 0x7e5a1ae8, 0x30179026, 0x3b69f2d3, ++ 0x9a243b0e, 0x4a21dcaf, 0x6bda6e50, 0x363befc5, 0x7bc80108, 0x5c8fadcd, ++ 0x3b5df345, 0x5689b244, 0x1376424d, 0xdda42649, 0x1a9fd842, 0x56a5f98b, ++ 0xb8dcad96, 0xaf680eef, 0xac4cc9ac, 0x46f6fbf4, 0x95f90dd1, 0xa100845b, ++ 0xbaee55ed, 0xeb48195f, 0x8210165b, 0xb7e69556, 0xb1a8aa3c, 0xf7b7dc84, ++ 0x9d9b477d, 0x0b3e5390, 0x47ec1551, 0x21147059, 0x056d81e5, 0xe5f7e903, ++ 0x8997055b, 0xe1be5fd6, 0x57d0076c, 0x170f28de, 0x1a2b7d69, 0xc91d446c, ++ 0x409afeda, 0x601f2d7b, 0x61e43b7b, 0x57d95ed0, 0x84442977, 0xf86eca7e, ++ 0x01d292ae, 0x3ddad6fd, 0xf6c7abe5, 0x3e567e34, 0xefa3db4b, 0xb820bd55, ++ 0x26558ba0, 0x3a3a01e2, 0x3ee75976, 0xd5fe8765, 0xc3622328, 0x2770b1fb, ++ 0xb03ca3f4, 0x03b02951, 0xa5951b7d, 0x5bea7aa3, 0x7a9ff0d1, 0x5333eafa, ++ 0xc6e5613c, 0xb28f94f4, 0xbe4f4474, 0x9077109c, 0x80a44bd6, 0xe7ba3252, ++ 0x3c4207f9, 0x7ea01321, 0x9e96a891, 0x11e4a9fa, 0xf4c3fe07, 0xfe0f949f, ++ 0x2d81b13d, 0x5b723d19, 0xf59904e9, 0x939cedc8, 0xcaea51cb, 0x4b5faf09, ++ 0x5079011f, 0x4e7cea7a, 0xa5f31f4c, 0xa7deba62, 0xe17edf22, 0xbd69891b, ++ 0x9fcf85cf, 0xba62e5f0, 0xf4c6e7c1, 0x4c42be57, 0x7c62be03, 0x2e6f936f, ++ 0x1e7d9ba6, 0xafb4fe7c, 0x5f06d30c, 0xce7f3e35, 0xadd31ab7, 0x7f3e3f3e, ++ 0xd30eb7c1, 0xd30eafa0, 0x9a2f20ed, 0xf802fa36, 0x035f4ede, 0x20be4da6, ++ 0x6beddf3e, 0xce21f4c2, 0x9214c747, 0x383e5127, 0xc549c4dc, 0xdc8a124e, ++ 0x27cd3279, 0xf27cb314, 0x853cfe6d, 0x343d93e6, 0xb032f94f, 0xa6679422, ++ 0xacd581f9, 0x24bdc87c, 0x43f342df, 0xe87cacfc, 0x2b7cee43, 0x63ad0fcd, ++ 0xf83623e5, 0x7e6863f3, 0x5f958044, 0x6f9435b1, 0x822bf9a3, 0x99ab3cac, ++ 0x7cd3b34c, 0xb3e58856, 0x8b4f775f, 0x56ecf9a5, 0xc0f9cf96, 0xf341cd3f, ++ 0xfbec6d39, 0xa203a7c9, 0xc3948f6a, 0x4c5d5976, 0xf836aca8, 0x49a5ba67, ++ 0x77a8af34, 0x8fe51711, 0x94b726ff, 0xbb21f946, 0x9fe43cb1, 0x8a8de58f, ++ 0xf6dfcb1b, 0xa77e6297, 0x63f2c1ec, 0x57964afe, 0x85fe583c, 0x37cc6eff, ++ 0xb72c7ec9, 0x5e58f8d4, 0xc0f963f1, 0xff58759a, 0xe580396e, 0xc51e6aa3, ++ 0x004addf2, 0xf35b1fcb, 0xcd3a7b84, 0x5f9e0ad7, 0x5a691e00, 0x4f013246, ++ 0x8a62d4c1, 0x9902b5a7, 0x11fdf80b, 0x72e28e80, 0x7a829a6d, 0x398ffdb8, ++ 0xe2fe814f, 0x97e4125f, 0x0660fd3e, 0xac6bff7e, 0x88f5a647, 0xfd93d77d, ++ 0x9eaeae46, 0xb4ca37ec, 0xbde01a7a, 0xeaff6b5a, 0x64c6fed9, 0x946f3d3d, ++ 0x436cf56b, 0xd7fb627a, 0xa737ecaf, 0xb379e9e8, 0x3767ab42, 0x3fdf13d2, ++ 0xeb0f1a7a, 0xb878d3f9, 0x482d3f9b, 0xd1fe80cf, 0x3d5dfe33, 0xdbbfc67f, ++ 0xb1d79fcd, 0xd5feb49e, 0x9eaef8d3, 0x76ef8d3f, 0xf630e7f3, 0xfaff706b, ++ 0x3d3dfe35, 0xd7bfc67f, 0x908f9fcd, 0xd5fe8c9e, 0x3d43f3b3, 0xd87e767f, ++ 0x58e39fcd, 0xf5fef0cf, 0x3d23e72b, 0xea3e727f, 0xd6174fe6, 0xeaff7973, ++ 0x9e91f9d9, 0xea3f3b3f, 0x5897cfe6, 0xf5fee8cf, 0x7a2fe72b, 0xa5fce4fe, ++ 0x01263f9b, 0x3fdb19ea, 0xd53e9a7a, 0xd3e9a7f3, 0xb0d8fe6e, 0xa3fd099e, ++ 0xcf5db727, 0x6ef6dc9f, 0x200924fe, 0xabfd49f7, 0xcf5da9a7, 0x6ef6a69f, ++ 0x7ac60cfe, 0xbf5feeae, 0xf9eb8f72, 0x9bbc7b93, 0x5fb0233f, 0x81ef5479, ++ 0x89eb421e, 0xdd9ebded, 0xd9fcf467, 0x3f9ba67d, 0x199eb063, 0xbecc9eb4, ++ 0xa1dc99eb, 0x8ee4cfe7, 0x62e4fe6e, 0x57fb333d, 0x3d0eeecf, 0x7477767f, ++ 0xf90f27f3, 0xfaff7d73, 0xcf53b935, 0x8c9dc99f, 0x550ee33f, 0x72d0734f, ++ 0x44ba163a, 0xa755c9fa, 0xe6816edd, 0x8bcb2745, 0xbf01174e, 0x0dfcd444, ++ 0xe916ead2, 0xf1adf6f7, 0x70920fd9, 0x04bf23bf, 0xbd4b15fa, 0x23bf70b1, ++ 0xe746372e, 0x13bbc4e7, 0xc2c4f974, 0x07f7ba81, 0x95d50f14, 0x42bdcca7, ++ 0xc9e69e57, 0xcbd3e5d6, 0x1fdeeb26, 0xcbaf9d5c, 0x5afab65f, 0xfe19fbdd, ++ 0xccf9749b, 0xdeeab775, 0x48b75e1f, 0xfabdfe57, 0xe5f95d72, 0xfcba9581, ++ 0xa1ff0d95, 0xf0747f7b, 0x98f95d3e, 0xe57507a6, 0xe98f4363, 0x3e0ee3f2, ++ 0x427f7ba1, 0xf95d26eb, 0xe9cf23c4, 0x6db527ca, 0x3aafe5d7, 0xe7e0dbb1, ++ 0x57ed9dd9, 0xb808bcf2, 0x4fefcc27, 0x0bdfd053, 0x57982ac5, 0x8fd1da06, ++ 0x54bb17df, 0xabe5463d, 0x4d58bcbc, 0x9905f2a2, 0xe7ae3a12, 0x5efb2c0d, ++ 0xf77e7d1b, 0x9cf7cf64, 0x8addf9f4, 0x8a338c67, 0x20f14a7f, 0x55485490, ++ 0xf2c6a413, 0xc78665fb, 0x46aff4fc, 0x7bdfa51c, 0xe2235d4d, 0xcc453e69, ++ 0xfcbc07ab, 0x4e21304a, 0x0d524463, 0x0998c5ef, 0xcfee0bce, 0x1fca79c8, ++ 0x8375d786, 0x3d0a1ea9, 0x3d93aef5, 0x6c67e0a9, 0x0fcb79aa, 0xc1dac87e, ++ 0x09035fb4, 0x2b784a79, 0xbf461fe4, 0xd534bc1f, 0x2b33eb43, 0x6f0f4fd4, ++ 0x8feda15f, 0xa01bf6c2, 0x697a17fd, 0x57343cdf, 0x4865bed7, 0x8b7dae99, ++ 0x5277db42, 0x4fe6a07f, 0x842a7dbc, 0x24bc84c9, 0x37db09fc, 0xf6c3290f, ++ 0x7ce857ef, 0x98fdbc25, 0x409bf6ee, 0xfb42f77f, 0x7ff4a213, 0xff7d64e8, ++ 0xfbeb9487, 0xbffeb0af, 0xb794735c, 0x6ffd831f, 0xfeb28e11, 0xfd67290f, ++ 0xbb7ab337, 0xf37477db, 0xfff420ff, 0x9ffade8d, 0xffdf4539, 0xfdf42acb, ++ 0xdff6b337, 0xdbc939ae, 0xeffb63b7, 0xff592708, 0xf6c0ab2f, 0x05c7b315, ++ 0x63d251f8, 0x7db403aa, 0xa61a8832, 0x6d0b8014, 0x0991d207, 0x3c84d414, ++ 0x3a450c2c, 0x78618eee, 0xe28622fb, 0x1f8ded0d, 0xb500939f, 0xde74396c, ++ 0x62beb1c5, 0x76029e6b, 0x7ce9cb09, 0xb5270965, 0x7c4449b4, 0xc0e6f593, ++ 0x476f4a70, 0x7c87e893, 0x03abfae9, 0x66bcff60, 0xbe18a0b2, 0x9e084893, ++ 0xd1f3fa7f, 0x65fbc29b, 0xc9d4974c, 0xfa616ded, 0xca8f3dd6, 0x29ab2327, ++ 0x0400337d, 0x1ff27a13, 0xa11079d3, 0xe80f8bf3, 0x4850833c, 0xf6b3227e, ++ 0x25f3a23e, 0xf9d1b7c8, 0x52139412, 0xead1df83, 0xfa52a50e, 0x1ffd398b, ++ 0x3f5f4c4b, 0xf8084dbe, 0xf17e7ea9, 0x4f38b183, 0x46dab05d, 0xc743de99, ++ 0x2ea27f42, 0x07e5fb4f, 0x32ed7539, 0xc8093607, 0x55f8155f, 0xc849aa82, ++ 0x94e975e2, 0xbfef3dd7, 0x469ec547, 0x710b7f59, 0xfdf429cb, 0x830957db, ++ 0xd9ddb49d, 0x1b36736e, 0x26e9dc27, 0x6e926bd4, 0xa6e425ca, 0xad32b1c6, ++ 0xe5b89481, 0xdac2db8f, 0xcfa8559d, 0xe7d62ecf, 0x6cb7643b, 0x947574a2, ++ 0xad236408, 0x7d5cce77, 0xdd8ed6b9, 0xcce4c094, 0x664e2bdb, 0x3481cdf4, ++ 0x513b1e1b, 0xec9d73ce, 0xef1e8d5b, 0x614e9962, 0x01fe9e41, 0x4feae404, ++ 0x756ef7c2, 0xe91b7eb2, 0xdc5b2b9d, 0x739fb4c5, 0xc0018a17, 0x3ffe91b7, ++ 0x4db9b5ef, 0xf75d3459, 0x22989933, 0x7fa463fb, 0x9fd8c79e, 0xf0e30ca0, ++ 0x73e332fc, 0x2e769b86, 0x1f018fff, 0xf80e3d34, 0xe31ff4a0, 0xabb1e8f8, ++ 0xb35e1f0c, 0x43c006e7, 0x4122e3d7, 0xdcbc72b9, 0xa4b2f1c2, 0x420b8f4e, ++ 0x71c8323c, 0xfb215cd9, 0xcc1c30c1, 0x565838e1, 0xedcdc7af, 0x45a72fc4, ++ 0xf5bccb91, 0xaa9c7f1b, 0x43eff646, 0x0ff99b8e, 0x44fe43ed, 0xe9c993f6, ++ 0xdba72e0e, 0xb7e5f5ab, 0xcedeb970, 0xfeb73ae5, 0x7cd4fdd1, 0x80d55b90, ++ 0xbdeefa0c, 0x9b679347, 0x2e1e9e4e, 0x779d234f, 0xf1de7970, 0x234f2603, ++ 0x9e5c6dbd, 0x65e7f56d, 0x5e923432, 0x560b7d23, 0x0147f447, 0x47f42e79, ++ 0x29b7a797, 0xd858f12f, 0xcce0caf3, 0x7a6163c4, 0x44a1a2b6, 0x981e5f97, ++ 0x597f7ba7, 0xf95d42fd, 0xbae5ba92, 0xeeebc5f2, 0xfa17e5d4, 0x7f7ba07f, ++ 0x5d1aeac1, 0x0fd5edf9, 0x97e7cae8, 0xcfcbaa3d, 0x7bae3cf3, 0x8ddcce7f, ++ 0xc5d9f2ba, 0x67caeacf, 0xe5d36e15, 0x74bbdc4b, 0x5ef69bef, 0xf3e0237e, ++ 0x0122c3f5, 0xd773e27f, 0x7e0b8c71, 0xf05d92ee, 0x8a9f31ce, 0x8df76eb8, ++ 0xcf84f4c4, 0xe53fb885, 0xa3b4c5cb, 0xe30ec5a9, 0x97171d04, 0xe66a7892, ++ 0xacd4374d, 0x34e3041b, 0xb374f1c1, 0xff1ae6e9, 0x637e4214, 0x45df9152, ++ 0x8d090af5, 0xc1804423, 0x25d1d386, 0xf5b79586, 0x0d4f5e51, 0x7964627f, ++ 0xe7f45b51, 0x5e16c7de, 0x77128ce6, 0x9253d1e9, 0x274f7e0e, 0xe58dbbf7, ++ 0x0e290215, 0x7dc84e7f, 0xf967d7a8, 0x30a15bb8, 0x9ed8affd, 0x901c4f96, ++ 0xbea88d0f, 0x0a417b54, 0x49c014f2, 0x978f4ea6, 0xb3a95fd5, 0xb2a204ef, ++ 0xe36f0003, 0x3457cf74, 0xeefba55c, 0xe9113ef4, 0x315b02ae, 0xe2c58609, ++ 0x87604cd7, 0x66432d43, 0xdd3a068d, 0x9c609baf, 0x7e801a6a, 0x615f69e1, ++ 0xe40931e2, 0x09e98c57, 0xdb4c5cdf, 0x8f4c1e7d, 0xfd30caf9, 0x698d57d8, ++ 0xa6356f9b, 0x98fcf91f, 0x875be07e, 0x757d9fe9, 0xd5f11e98, 0x2faefa63, ++ 0x5f21e980, 0xfb6fa603, 0xfab69882, 0xf0ed309a, 0xf4d531b9, 0x9ddc2fae, ++ 0x29f0e3e0, 0x9c145fc0, 0xaab7dc75, 0x1e94dd66, 0xdd339d9c, 0xd41fe353, ++ 0x7aa2e7c3, 0xb243c733, 0x425f0f0e, 0xd67119b0, 0xccbd7947, 0xf7dbd871, ++ 0x9bbdcbd1, 0x9b7835fe, 0xe67e6260, 0x0f5bc5b7, 0x780dd29e, 0x4f0becca, ++ 0x3d09c403, 0x72609a78, 0xe387bf32, 0x8fd027e9, 0x7c8af328, 0x84064270, ++ 0x1b6e6bf9, 0xf5f3538b, 0xb2a9ea04, 0xbb6f3538, 0x8adbbe96, 0x24605d7e, ++ 0x46e71b8c, 0xc40475fe, 0x311dcfe1, 0xef5f49d3, 0xa4e233fd, 0x71bbbe77, ++ 0x4034b37e, 0x9171af07, 0xc618d6e5, 0x1489ab57, 0x3dae3a12, 0xd769fc30, ++ 0x979851a2, 0x1f7c0248, 0x46c49570, 0xcafa97a9, 0xf8bedfc0, 0x45fb1b5a, ++ 0xfed7d416, 0x2072dfc4, 0xfe62609d, 0x888b4c72, 0x3d093b7e, 0x76fe02e5, ++ 0x57664b8f, 0xbbb7c42a, 0xf44e2b86, 0x3d76021b, 0x9f34fcff, 0x07bfc3d3, ++ 0x715a8f28, 0x454baddc, 0x62fb0dfe, 0xf83f5a44, 0xef7d97d7, 0x028b9f8b, ++ 0xfc25ff03, 0xf63ecbec, 0x5b891765, 0xf689a17d, 0xe8ef73bf, 0xb05507ec, ++ 0x3cd94383, 0x6b7e17ad, 0x7a4652eb, 0x710df87e, 0xe1ac99dc, 0xa10875b8, ++ 0xf5c47ced, 0xf7e35ce5, 0xb42e40e2, 0x741f9c1e, 0x7e7ee0ed, 0x933d721f, ++ 0x6bcfafa1, 0x214e2fac, 0x6eda18c2, 0x3890a2ac, 0xcf45aa42, 0x6fce22c3, ++ 0x887e6d5c, 0xb9b5ec1b, 0x3798556a, 0xa4237a9e, 0xf8fa8d42, 0x4f83b9c2, ++ 0xb61e6039, 0x3ce4d532, 0x5a8e4516, 0x70cc195a, 0x2be7c3da, 0xb9fcfa4d, ++ 0x8830a13a, 0xee3539f3, 0xce30d1e6, 0x86c79d38, 0xc54fdd81, 0x6567ab54, ++ 0x463ce2aa, 0x86a9eeed, 0xff3638cc, 0xb27b300b, 0xcded1e35, 0xdf059f29, ++ 0xd3d367ff, 0x3d1a3d5b, 0x4f923484, 0x69cf602c, 0xefef6659, 0xd20faaf7, ++ 0x9be20505, 0x02fe59a4, 0xfa569be6, 0xa143d7ff, 0x5af3095e, 0xe8a0debd, ++ 0xe7818f37, 0xd1ed755b, 0xed6d54ef, 0x5debbe15, 0xaed224ef, 0xefca9ee1, ++ 0xbc3ebe15, 0xd4eac1a2, 0xbaf1b1fb, 0xcd29b7bc, 0xe16bf3a9, 0x57b8e01f, ++ 0xafe0120b, 0x53afc382, 0x3c03afb2, 0x21e0826d, 0xf6045fcc, 0x4da5a55e, ++ 0x2ea8a8f1, 0x45cf80ad, 0xd5fe1ab9, 0x3b53ef39, 0x9935f275, 0xaf919e80, ++ 0x3d395528, 0x9e91d1f5, 0x317e6898, 0x5c6a2dcf, 0xd6e30451, 0x3f9b1349, ++ 0x07629294, 0x48cb8fcc, 0x53c40e5d, 0x215310cf, 0xf219e7e8, 0x985c63b6, ++ 0x15159e3e, 0x75e2e7ec, 0xce9e3f7a, 0x65f975ef, 0x52fcfaf5, 0xac325372, ++ 0x2f5d2f83, 0x76008093, 0x547e5f43, 0xcbbd6274, 0x185af548, 0x6ccbd7b7, ++ 0x24e45b3c, 0xafa53a52, 0xe64fb7f2, 0x8bf9a42c, 0xb57f1b22, 0x09e5dc75, ++ 0xe0f2fe8c, 0xcb4dc546, 0x771c693f, 0xf440b50b, 0x185ac0fb, 0x043bfcb7, ++ 0x523516d7, 0x7e94df7e, 0x3f9abd23, 0xcc9eb110, 0x106ca8e9, 0xfe2881dc, ++ 0x4c092280, 0xbbbdb8cf, 0xe2ea7242, 0x0f903920, 0x6b7c838b, 0x1d11253c, ++ 0x9e89369e, 0x8604d221, 0x09ff981f, 0xf9e29752, 0x46a7f52e, 0x34857fd4, ++ 0xff589fe0, 0x8e7f5a20, 0x7f9cfeae, 0x22c3fd2a, 0x568fcfe8, 0x9f6fe57f, ++ 0xf6a7e9df, 0x9fc5fca4, 0x271d083b, 0xc9754a4f, 0x8adf2a2e, 0x80763f2d, ++ 0x7e484f9c, 0x64f5e007, 0x440c2c40, 0x7756b719, 0x176ddbcb, 0xff06ee20, ++ 0x7a9ff5a4, 0x8f1827ee, 0xec8b62f8, 0x835a78c4, 0xfaa66439, 0xbcb8d558, ++ 0xfe616488, 0x7fdfcb28, 0x937c8456, 0xcfe57f1e, 0xf6193cfc, 0xf0a45057, ++ 0xfd0852f8, 0x9fcdaad9, 0x44f8e016, 0x8c8f50ba, 0x17fb41df, 0x2dfed013, ++ 0xcb22e254, 0x27189d29, 0x78be72f0, 0x56727f1b, 0xdabfc074, 0x7c6efe70, ++ 0xa7fb8cbf, 0xa4d8a5cb, 0xf7fd1b76, 0xec113244, 0x120fc6a1, 0xed69fe60, ++ 0x3accbfb3, 0xbd39e94a, 0x108735f9, 0x8f4d27c6, 0xff1705ce, 0xbbdab77a, ++ 0x7aa0edbd, 0x6907ee16, 0xc4da95e3, 0x9666eafd, 0xc721c856, 0x560ed455, ++ 0x7e5d946c, 0xf9e2b8fa, 0x027e9ea7, 0x327f98e2, 0xfad386bb, 0xffbf3c57, ++ 0xbf34c9dd, 0x549c9b62, 0x1761bac4, 0xe2e47b92, 0xceafffa5, 0xf94391ee, ++ 0x7515fb4b, 0x6f7e7b34, 0x563c8f42, 0x90a7db6c, 0x98fc91d1, 0xb4a7dc16, ++ 0x25c8a3d9, 0xfc00b478, 0xff67da84, 0xe2f8815b, 0x4902bdc9, 0xcfc288c9, ++ 0x0fd1fb8d, 0x1ca13e00, 0xe5ba9cb9, 0x4bdf7866, 0x5af602e5, 0xfcb19393, ++ 0xa04f6e3a, 0xe214753e, 0xb4dd85f9, 0x9b3fb2fd, 0xb2ffd05d, 0x4072ee17, ++ 0xd54b8e3f, 0xfe4fd70c, 0xdb4dd938, 0xc9fd932d, 0xf3d94c4e, 0x1bfd5fb2, ++ 0x5bd96de2, 0xf18c96ff, 0x334ee224, 0x4fe3d8e1, 0xd92dfe83, 0xb7fb1b30, ++ 0x77107894, 0xc58a4f65, 0x973eff60, 0x28b6e148, 0xf5c1d17a, 0xea26f8e2, ++ 0x1dfed188, 0xec23f987, 0xc45b79a7, 0xdc84557d, 0xffff4049, 0x7a85f78d, ++ 0xdcff9808, 0x5fb4e4c2, 0xa2bd7132, 0x5e3866de, 0x0adfdf37, 0xd83539f2, ++ 0x2ceb029d, 0x39f9225e, 0x69af843f, 0x335be2bd, 0x887c9852, 0xeff0e52a, ++ 0x0d3f38e8, 0xadfbc39e, 0xa59adbb2, 0x9d7c8efb, 0x2afed3d1, 0x3ba53ede, ++ 0xe3e7c606, 0xd5fdd1c9, 0xf7a6b281, 0xc30e9c74, 0x337e9857, 0x00fcdf7d, ++ 0xdf4d6fd3, 0x50852503, 0xd310e17e, 0xc60ef81f, 0x28574a3f, 0xddf7cb05, ++ 0xa03da02c, 0x7a68e6f3, 0x7ae659bd, 0x70d72fad, 0x8496e942, 0x40bc30b8, ++ 0x7fc809fd, 0xba595f5c, 0x66177e9e, 0x9ed0bd2f, 0x4d3eb223, 0xfd71976f, ++ 0x7ffa093f, 0x93fe8f65, 0x7bef4c0d, 0x2cfc9ff7, 0x9e07236e, 0x95f4027e, ++ 0x055fa7ea, 0xa18b957d, 0x6d6d9fdf, 0xaa56f779, 0x35059fa7, 0x4fdbd53d, ++ 0x6d969ea3, 0xe9a2409f, 0x177667e9, 0xf4a7aa89, 0xb53d5479, 0xff8e21b7, ++ 0x8d4fd94f, 0x9eb2f17f, 0xec3d9a7f, 0x7b468f8d, 0x22a482f8, 0x90f68d3f, ++ 0x39221dfe, 0x70d3f891, 0xfcade1a7, 0x81979537, 0xa5c6e9dd, 0x5c6ebb86, ++ 0x888bb86a, 0x67f8eadf, 0x621f7f2c, 0xf9ae944d, 0x30a9fa96, 0x1174b08f, ++ 0xdde5779c, 0xa9bae22c, 0xbd4102e5, 0xee3227cf, 0x54cf7c1b, 0xd0fc013d, ++ 0xe5bb7fa9, 0xde94ddcc, 0xb32fc4f9, 0x193af975, 0xbeaffafd, 0xed0a7afe, ++ 0xbf9cadcf, 0xafbb29f3, 0x2b98f2a7, 0x4a18a109, 0xf8893ce7, 0x3e2012e3, ++ 0xc38f902b, 0xa65f98e8, 0xd4dfc3cf, 0xfa7a9ee4, 0xce9bff7a, 0xfa6dbe43, ++ 0x5dad8f96, 0x30e903bd, 0xc70a5e6c, 0x95c80953, 0x5e3bcff2, 0xbb450c08, ++ 0x871526d4, 0xe31eabcd, 0xe9ade776, 0xff8026b3, 0x74673792, 0x10f9c31c, ++ 0xb97adf9c, 0x57e73afd, 0x9faec0e3, 0xf9c4ce6b, 0x8b83b9eb, 0x9beda363, ++ 0xdb38e16c, 0x3a55d7cf, 0x489d42ed, 0xba49df71, 0xdbf17fd0, 0x944b64ad, ++ 0xca1fbf75, 0xc50ebe26, 0x44ff46e5, 0x1cb9b72a, 0xa7e8f387, 0x7261d971, ++ 0x93faf9bb, 0x0e522392, 0xd871f7f0, 0xf2bbeb3c, 0xfc0d7017, 0x15b6b16d, ++ 0xcff14714, 0x37f9ca7f, 0x712fe5f5, 0xe6f4eaff, 0x38f8093c, 0xe2ea2edd, ++ 0xfa6bf71c, 0x028c8a3a, 0xbcbea6ba, 0x1409e1fc, 0xa283dec7, 0x7aabf60b, ++ 0x9e2acf9b, 0x235df328, 0xf07ea13f, 0x4ecbf723, 0xb961d7e4, 0xf5f00978, ++ 0x812b6cf0, 0x1477cb75, 0x3a346557, 0x3c599867, 0xfe291e64, 0x7ff0bc7c, ++ 0xe6f37f1f, 0x29f286c4, 0xd9d9ce3f, 0xfc48e07e, 0xe73fbd31, 0x02350214, ++ 0xf96450e0, 0x71002124, 0x79e202b2, 0xfa808a78, 0xfdb84d7e, 0x792a6bca, ++ 0x54d5f61e, 0x134e0b35, 0xda92af2d, 0xb7b1c014, 0xfe049b69, 0x712a75f9, ++ 0xaa41bc63, 0x58737d1e, 0x2cbf6b5c, 0xfe5abf21, 0xc0edeb7a, 0x9b37f3df, ++ 0x1ee5d009, 0xe301d675, 0x71e6f9fe, 0xf5bd07a8, 0x323e8feb, 0xf504ba75, ++ 0x1187c410, 0x3649050f, 0x34f67e5d, 0xe545c832, 0x76dcd536, 0xfc8a2b97, ++ 0x670c2996, 0x966fb6fd, 0xdbeccfff, 0x18df6a14, 0xfb70e5ae, 0xb0894636, ++ 0xecd1296f, 0x351acadb, 0x72b17005, 0xc80a664f, 0x4babe575, 0x6fb34406, ++ 0xfcd8f8af, 0x0fbe55fd, 0xb51073bb, 0xecc2636f, 0xdf6a20db, 0xd36dc4a2, ++ 0xecffcd14, 0xfe59bec3, 0x15eff477, 0xfa516fb0, 0xdbd14a3b, 0x1ae6c2b7, ++ 0x83856fb4, 0xa87edd44, 0xe7cf854c, 0x0b6fb57a, 0xf31b3e7f, 0x0516cbb2, ++ 0xb057c03f, 0x3b72af6f, 0x9d80ed07, 0xb138a45b, 0xb9dafefd, 0xb9dafe92, ++ 0x6b3e25ff, 0x60e56e76, 0x12239e76, 0xadcecc87, 0x6e7660cc, 0xe7661ee5, ++ 0x76670e56, 0xf2df68ce, 0xfb1bec23, 0xfd246abe, 0x198be71e, 0x968dbcbf, ++ 0x5d95cd17, 0x917efa16, 0xa85f9daa, 0xef6e109e, 0xf2122916, 0xb9dec239, ++ 0x9039e2ce, 0x9bddecbe, 0xa186ef60, 0x7a061b1d, 0xb5c7c464, 0xfdba6cc3, ++ 0x6cbf8772, 0xa08bcdff, 0x71147f2f, 0x899efd9e, 0x7ef68bcd, 0xf40e3ed9, ++ 0xe7a7176e, 0xb3c98561, 0x7b47e7c3, 0xd3146d3a, 0x3183caf7, 0x35544e38, ++ 0xf7bfac0a, 0xc615010a, 0xc45ebf81, 0x7bedf2f9, 0x8e797cd8, 0xfc83f199, ++ 0x5dcec8bb, 0x0c2c1650, 0x8bdcc3c3, 0x9cd718e5, 0xf80b112b, 0x5e0e0baf, ++ 0xd6fc127b, 0xa1d71705, 0x9e00bbbf, 0x6d89bec3, 0x69d36b6d, 0x172fb7bb, ++ 0xeda1de70, 0x6dd798ef, 0xec7ef52f, 0xfbe8e6fc, 0x7a72a634, 0x0423dea6, ++ 0x5f4e5f60, 0xe05e20fb, 0x6c4737fa, 0x37917e43, 0x2896d745, 0xd7bda3fa, ++ 0xe31727cd, 0xe62ae54b, 0x89f37737, 0x22154df2, 0x5d2544f9, 0x87b930b4, ++ 0xa0efb72f, 0xbdea4dfd, 0x22df1abf, 0x71b8e1f7, 0xbf80b33e, 0x341f1bd7, ++ 0x9ff4473e, 0xa9fa9df3, 0xc8c79fb8, 0x6766a08f, 0x41a324ae, 0x7933df2f, ++ 0x38009e1e, 0xe3112ffa, 0x1bccb7b6, 0xb3cf3bae, 0x7ae5f393, 0xc9e9d1cf, ++ 0x5491f02a, 0x2d6ece03, 0x993fb6db, 0x7746eff6, 0xcc843646, 0xf155ff67, ++ 0xc5a1fc40, 0x507685da, 0x99aa61c3, 0x8e33f0e1, 0x9d03c3c3, 0x69bc71d3, ++ 0x5fa89c12, 0xe39d8321, 0x94bcc8fb, 0xdebfa0cf, 0x513e3e26, 0x167e827c, ++ 0xc815e368, 0xfaf3fe85, 0x6f172666, 0xb97280b5, 0x001d7481, 0x092557be, ++ 0xaaad10ae, 0x8fdb69a0, 0x2bd5bf61, 0xf41cfa56, 0x6d704cbc, 0xa7b0ec62, ++ 0xb1c54725, 0xb8c70d14, 0xdc6c3049, 0x25ef005c, 0x3345bec0, 0x0ffb7fb6, ++ 0xfa323d98, 0xadcd5329, 0xa99e8187, 0x8d932eff, 0xff4030f0, 0xd181c30b, ++ 0x83d0898f, 0x27efb86f, 0x57efdb99, 0xe0760e40, 0xfe029777, 0xc6c43790, ++ 0x2bdcad1f, 0x6f91d3a9, 0xe89a1c9a, 0xc99e32f8, 0x8dfa9601, 0xcb51be7c, ++ 0xfde1fe03, 0xef864166, 0x24f95267, 0xa669a2d2, 0x78680f2f, 0xfc91ab37, ++ 0x5a427882, 0xfb00dd98, 0x596ebe16, 0xf216f4d5, 0xd455dae9, 0xf923533d, ++ 0xec07c9a4, 0x15f8a5e0, 0xfb4d3fa1, 0xfa9feea2, 0x6a93fab6, 0x5ecfebd6, ++ 0x636bd76b, 0x47b68e20, 0x9a42bb40, 0x83f175e3, 0x979b335c, 0x883d58b5, ++ 0x6557aef3, 0xd23526d7, 0xe5ce5cfe, 0xf095f302, 0xa0d37bf3, 0xec6eb043, ++ 0xb44f92b4, 0x38650f7e, 0x5e0f1f0b, 0x7e507ab1, 0x913fd5bd, 0x3f9bdfd7, ++ 0x0fbfe5a6, 0x45bec1ed, 0x719edf55, 0x49e2d23c, 0xba6bf57d, 0x6f8fd999, ++ 0x9dad2fdb, 0xe0eeba6f, 0x7f18ad25, 0x361fd6d3, 0xc85f9e89, 0x142e3f30, ++ 0x5d3afd24, 0xfe5fae17, 0xa71fea13, 0x887ea25c, 0x9f28851f, 0x14fad95f, ++ 0x3ccfabc6, 0xd006f477, 0x13bf159f, 0x53ea8589, 0x1258d6c7, 0x1440fb62, ++ 0x1bca13f0, 0xf3c63745, 0xacce50a5, 0x90833f30, 0x178fc65a, 0x94eed163, ++ 0x8a07376f, 0x3be5f7e8, 0xb882c93f, 0xcc7dc75b, 0xe39ff9fe, 0x65b7f478, ++ 0xb97f7ac1, 0x8df1d6c4, 0xe39bb9f2, 0xdb2ef4f3, 0x42dfb05c, 0x5aef3b03, ++ 0x9b239c1e, 0x950ce2c3, 0xb5c59966, 0x9f70d977, 0x0159ffb5, 0x7d0329f7, ++ 0xb52ce7e1, 0x9fa79ffd, 0xbcb97665, 0xb9c00e49, 0x6d86f2d9, 0x2f07101d, ++ 0xff46623f, 0x1670dbd5, 0xbda6edd7, 0x47fa3cf8, 0x175126de, 0x3f888d07, ++ 0x33218836, 0x2b1acfc4, 0xfcd00ed1, 0xa307cc51, 0x8afbe1c7, 0x7178ad93, ++ 0x653f4ecf, 0x9e978ae1, 0xd9b9e071, 0x8c0e2dd6, 0x3a5c3643, 0x6f111ffe, ++ 0xc9703e0c, 0x8e29e378, 0xf59b5f8f, 0x21a435eb, 0x9490e311, 0x28e29cbe, ++ 0xdc6e8b71, 0xaff9ff3f, 0xf4ec3d60, 0x057ecff6, 0xe3fc56f4, 0x01eeaffc, ++ 0xd5af6c7f, 0xf7b5e309, 0x9eb8c3b9, 0x8bb77da0, 0xb3c779eb, 0x4c3ae0cf, ++ 0x2ecc9fc7, 0xcf63ada8, 0x1eb021f1, 0xcbedb1d1, 0xaedb8864, 0xe70333da, ++ 0x4c76ab69, 0xe651214b, 0xb80a5a01, 0x1d63f40d, 0x96af28c8, 0x402196c6, ++ 0x6f2a19e7, 0xe3bad970, 0x164ac1c7, 0xdc79578f, 0xf5f46b78, 0x713888b6, ++ 0xaf1bace3, 0x51bbf186, 0x1fa4a976, 0x5443e2f1, 0x21fa638e, 0x680fadbf, ++ 0xfcaa3ef6, 0xa83fc0ce, 0xc833de9c, 0x25c6f3ef, 0xca027ebf, 0x8d7b131a, ++ 0xc1fa8717, 0x6f3d6d37, 0xb1fdd9b3, 0xfb66f419, 0x0f3e306f, 0x0d73a372, ++ 0xe7fcf1d2, 0x72ce2043, 0x03baee42, 0x31eccff7, 0xf2a8bee3, 0xfea1ef3d, ++ 0x0b78ec74, 0x5f08cbd7, 0xdd20eb57, 0x841d6c7f, 0x9bbce1cf, 0x999c5963, ++ 0xd0e21ff3, 0xf39f03aa, 0xb1c33378, 0x2dee8716, 0x61669cfe, 0x75b489fb, ++ 0xefcdcac6, 0xd710c42b, 0x4e417217, 0x2eb92f47, 0x09c1f1aa, 0xbe18987c, ++ 0xce3d129e, 0xc6eebddf, 0x03f205e5, 0xbd7babff, 0x4107e684, 0xbc203cfc, ++ 0x83d8a247, 0x1d6c8d8e, 0xbe8e43a6, 0x5f5b50ff, 0xf418b249, 0x75bfd034, ++ 0xffe8be95, 0x6191fca6, 0x922139b2, 0x8abfa74f, 0x5a27c76e, 0x1fb6ef84, ++ 0x588842a6, 0xfac0b7ff, 0x0551e37c, 0x38da1fe6, 0x34f7f5a6, 0x7e9f279f, ++ 0x1ef3c44e, 0x682d836b, 0xa2f68dc7, 0xa0f8b08a, 0x9c99de91, 0x3626aade, ++ 0x1ede9c4e, 0x7ad3b01b, 0x0bbcbf4e, 0xf5b55cf1, 0xf5a7e2a8, 0x4978681d, ++ 0x2fdb0b69, 0x2044e305, 0x2fd3fe8c, 0xeb62cbec, 0x6e5e6c47, 0x6f0e676c, ++ 0xbd1cdbc7, 0xb3d6ef1d, 0xf85676ba, 0xbf3b0a83, 0x4ef6e973, 0x5039ee49, ++ 0x9956a9df, 0x53fdfec0, 0xda30b141, 0x16c993fe, 0x33cb8b59, 0x25e3a1bd, ++ 0x658c779e, 0x04c51be7, 0x55ebfd05, 0xe247b9b1, 0x54552092, 0xd6d45388, ++ 0xb538fdb0, 0x82a5743f, 0x6fe36bbc, 0x3ab6f5c1, 0x499d7f03, 0x5f883cce, ++ 0x8f17a738, 0xed1ab807, 0xa4dbbc4d, 0x6c557fa3, 0xc79c0a61, 0x31fdc35f, ++ 0xfcf0b922, 0x2828e8a5, 0x4e88fe84, 0x651ad393, 0x17b6417d, 0x5f184f13, ++ 0xbcfea764, 0x9c6af924, 0xfb68f50a, 0xad2c2a68, 0xe9d0b007, 0x52c2adc6, ++ 0xef377b2e, 0xbbf62766, 0x279f2b73, 0x4cea89b8, 0x60c1fb66, 0x1edce8dc, ++ 0xe0c64597, 0xf14dc487, 0x85cfe368, 0x81f6fbad, 0x20e35a3d, 0x67aa78ee, ++ 0x98aaab94, 0xc746e709, 0xc04c845a, 0x7e37d9e9, 0x36b5eb47, 0xe87f388b, ++ 0x42fb6bb4, 0x67a0f1dd, 0xee10f236, 0x7f2803ff, 0xa743d89d, 0x81205f71, ++ 0xee7b9257, 0xda219895, 0x6e73de71, 0x88038b03, 0x4e5f8ae4, 0x12387161, ++ 0x78f9fa00, 0x79d382b2, 0xbf78520e, 0x1d73c154, 0x297d5ecb, 0x1c984427, ++ 0x5895f9c2, 0x5a5f3fa8, 0xc164756f, 0xbbf13cba, 0x4c9ce15b, 0x406faf29, ++ 0x29dcfeb1, 0xe83f3f55, 0xa7ae12e9, 0x382d2d9f, 0xd4aff608, 0x7aed14b3, ++ 0xb9fd5cca, 0x2b3ee354, 0x85f617a4, 0x427bbd51, 0x5577dc88, 0x5ae8fcd6, ++ 0xee472f98, 0x612322bf, 0x8939593f, 0x9cf9c171, 0xf2fa0d15, 0x2f3760bd, ++ 0xfb127607, 0x7d7de2a5, 0xc46db7f2, 0xbf8ca72f, 0x215d7f24, 0x2c6b7f78, ++ 0xbd9655c6, 0x93ed18ba, 0x5fcf5539, 0xafe7aaab, 0x8f91a46d, 0xbac73e7a, ++ 0xe6d37cf4, 0x39f1bd9f, 0xde7f572e, 0x8967c8d7, 0x804378f0, 0xf62221c5, ++ 0x446d35b7, 0x367c8dba, 0xc2ddb5f2, 0x5f38bdd7, 0x25b15fe9, 0xa06c9999, ++ 0xa10a4d3b, 0x28f5185e, 0xe0121edd, 0x029383df, 0x2b95f835, 0x2a7bed16, ++ 0xca508fef, 0x1e81b3be, 0x0baf4089, 0xf44e08f5, 0x91b79d81, 0x56ed9c0f, ++ 0xe427d610, 0x977b2beb, 0x7f255de7, 0x7e88ba38, 0x3bf001b5, 0x9d8af506, ++ 0x81204ddb, 0x53d00cda, 0xedc61397, 0x96a2cfa0, 0x09ff704a, 0xc1874b51, ++ 0x4c4e27bd, 0x50fbe11f, 0xdc11473a, 0x5d0c1c17, 0xf4fb0648, 0x0dd77648, ++ 0x4bbcf760, 0xc1d83148, 0x3cd8621b, 0xff4f3165, 0x5db85566, 0x35eafe9d, ++ 0xacb37df0, 0xcef0b9c2, 0xe1962de6, 0xf1126f90, 0x7c6f11fe, 0x7ed0e5dd, ++ 0xe8ccb347, 0x8604b52a, 0x8f62fc43, 0x9476ed8c, 0x95f3c14e, 0x335b7edd, ++ 0xd9d207db, 0x716389fc, 0x68ef3d98, 0x10e5d9fa, 0x14dc7acf, 0x08c9ff7d, ++ 0x5fdf89ab, 0xdfc72df3, 0xbbfec460, 0x3fb65611, 0xb4a191ee, 0xe725551f, ++ 0xf4cc38f8, 0xe72e2ae1, 0x16bd2c3f, 0x59a3bffb, 0x291c6150, 0x6ebb6f10, ++ 0xa4e7ed34, 0xc38f12c3, 0x78e4b8b0, 0xe22efefe, 0x4c7e054a, 0xa0089aba, ++ 0x44fe93cf, 0xf8d6df70, 0xaf38a5ea, 0xe2839dfa, 0x49d60b3c, 0xcec16e29, ++ 0xffa3b69d, 0xd255a13e, 0xba7e32e1, 0x99e605a7, 0xb4108f13, 0xe88f13b7, ++ 0x404973cb, 0xf4da76c4, 0xa13aafcf, 0x395be7cf, 0x19241dbe, 0x2bfebdf0, ++ 0xeceae911, 0x68fbae22, 0x03a59dbd, 0xce9bbef1, 0x976a700b, 0x85895fa6, ++ 0x59f9c6d1, 0xafca0780, 0xe38215c7, 0xed4be3cb, 0x797fbf18, 0x3065f969, ++ 0x03f17fae, 0xced165cf, 0xa5d98781, 0xcabfb638, 0xa789471d, 0x30235eb8, ++ 0x15a5d77e, 0xafafd947, 0xb5c358e1, 0xa5b4e786, 0xfb689e31, 0x32b43f12, ++ 0xe97f243f, 0x79814148, 0x00815ed9, 0xf3ee3b5f, 0x8cdcf25c, 0x0e97dc9f, ++ 0xce9b78f4, 0x696d9fa3, 0x75cfbe8e, 0xe6c1d595, 0x6bf9f77d, 0xddde3f60, ++ 0x3ec12954, 0x7aef5ef6, 0x0add579c, 0xcef85741, 0xcf10b752, 0x90b12ee1, ++ 0x96cf104d, 0x8a6ed2ea, 0x9b4fdc05, 0xfbd296b9, 0xe509b144, 0x42ecb8fc, ++ 0x8495fdfa, 0xc7817c60, 0x40dd076b, 0x479f8636, 0xef3591fe, 0xf7ad2b41, ++ 0xe513ab41, 0x0971e892, 0xefebbf40, 0xbd00edff, 0x4668bcee, 0xf3e40e39, ++ 0x2dbbed1f, 0x62634f9c, 0xff006bdc, 0xf5092ca4, 0xa871e5c3, 0x2f7089a5, ++ 0x947be501, 0x2fcd5475, 0xdb50f04d, 0xb049e946, 0x2e7ef09b, 0x4eab76e2, ++ 0xe119df6d, 0x03e985ef, 0xf6040909, 0x54f669a5, 0xb1421668, 0x2de3ff14, ++ 0x33cc10f6, 0xbf68ca12, 0x62560929, 0x4ab5f561, 0x55cfbba7, 0x8a773ee3, ++ 0xdc381ccb, 0x1b5f7044, 0xfa85a46c, 0xd9ab3b35, 0x04f135e7, 0x479acded, ++ 0xad2d40a5, 0x66d48367, 0x8649f885, 0xad87cd5b, 0x8a920944, 0x9707bde7, ++ 0x65b47d31, 0xeddf193e, 0x1f6550af, 0x41710ffb, 0x8fbaf5b4, 0x79e5f9bb, ++ 0x7595f81e, 0x7065ebb0, 0xd6565c6b, 0x05bf6b9e, 0xbb6ef3fd, 0x02b0fdc1, ++ 0xfa4eee3e, 0x0bf6c4d4, 0xfdc1ae84, 0x9a3ada76, 0x3d506ed1, 0xbd044778, ++ 0x782254fa, 0xff4dd73e, 0xdcb6d1cb, 0x3e0fd985, 0x5534e64e, 0x26efa0b7, ++ 0x3c016a8e, 0xde1af55e, 0x476111c5, 0xa9eebe26, 0xadbf7a05, 0x61e230fd, ++ 0x23ea886c, 0x1528cf97, 0x7670a9ee, 0xd5bca1e7, 0xdc77e7ca, 0x8c9524de, ++ 0x96bf414f, 0x5fc8cce3, 0xfa8daf4d, 0xd5dabd9e, 0x035ac662, 0x3b6304c8, ++ 0x43a1e844, 0xf47b04cd, 0x7dfe08ba, 0x0bc51e67, 0xd06eeba5, 0x2fcff03b, ++ 0x6e026604, 0xdf7f37d6, 0xadf1fa0a, 0xfa668fc7, 0xeafed875, 0x0e9e8a9f, ++ 0xee1fdb2b, 0xed543e00, 0x8fc7c0bb, 0x5bb9ca10, 0xc23f54ae, 0xee1a21e3, ++ 0xf4d7388d, 0xcc2e16a2, 0x71f3c4c8, 0x0a23e404, 0x99ac1441, 0x5f02706c, ++ 0xb6baff35, 0xc78d9fdb, 0x9cab3d73, 0x595abdac, 0x165dcbf3, 0xd8aaefe8, ++ 0xad4b94fc, 0xd22f7a8b, 0x79d84bf9, 0x85d4af18, 0x45ef33f3, 0xbf120485, ++ 0x689abf03, 0x7e3a39eb, 0xe144c525, 0xd1e80757, 0xfb27ff84, 0xcfec6593, ++ 0x7f4f6afd, 0xdf9e22ae, 0x90bb51b5, 0x1a7d5773, 0x943905c3, 0xbe0b8e1a, ++ 0x7e9bd95e, 0x06fd52e7, 0x9f422dd7, 0xa93c7a0d, 0x29b1ea99, 0x725d8f52, ++ 0xe75bde31, 0x7b4363da, 0x0bebd467, 0x1b5e5fbc, 0xe8b57be3, 0xf3031999, ++ 0x10d75371, 0x4a965dc0, 0xb1288b12, 0x5b224d59, 0xd44d6d5f, 0xe391238d, ++ 0xa4ed1fbb, 0x7e6a5fe6, 0x6ebdf1a5, 0x1b8f92bf, 0x68533c5a, 0xfda7f8a2, ++ 0x33c637be, 0xeb5af80f, 0x384ff364, 0xf2fe0a68, 0xdb9eac8f, 0xed1b3e80, ++ 0x6bac0c43, 0xb0650c8c, 0xa7484978, 0x97e9bd6f, 0xc13fa0cd, 0x98e38490, ++ 0xc3638e9f, 0x19e9de85, 0xe8cf1310, 0xfc0556a5, 0x84394194, 0x70455635, ++ 0x2ca0f75f, 0xa0cc8f76, 0xe3ef766c, 0xf5b0c47f, 0xd8627b98, 0x3fa5a1b8, ++ 0x05df16b2, 0xe22592fd, 0x7b7f6737, 0x885481ba, 0xe31bde1f, 0x61f813be, ++ 0x3f637429, 0x25c49dd2, 0x4ba5bc50, 0x37f60141, 0x02a85424, 0x36121b8b, ++ 0xeb4a40ee, 0xf3522f4b, 0xa74adc60, 0x20e216b6, 0x44efe0e9, 0x18fad391, ++ 0xbbc5bbf9, 0xa3ce231a, 0xfe618fac, 0xf68501f6, 0x9d88b137, 0xdb8ee947, ++ 0xbf81f250, 0x60b7b11d, 0x673e3b67, 0x78fea1eb, 0xfce367c6, 0xfd06040b, ++ 0xc7fe7892, 0x09ac910a, 0x9bf23f38, 0x05933be0, 0xe23647e7, 0x7cfd820a, ++ 0x55c58631, 0x75ae0ad7, 0xd4a9ff90, 0x76fb8165, 0x323ffc34, 0x449726e5, ++ 0x7d5c715f, 0xace60b2e, 0x039e1f54, 0x394c7579, 0xf60d6237, 0xc3086ba0, ++ 0xedd45b9b, 0xd6e4d77f, 0x66e4eb24, 0xb8487885, 0x70558ebd, 0xc421df7e, ++ 0xd43e60b8, 0x74605cb1, 0x3e7e160a, 0x69c7d240, 0xc6d43db8, 0x3263b781, ++ 0xf11b7e90, 0xc1fbc58f, 0xd00b2e2c, 0x7ddfd1a3, 0xce70d48e, 0x340e78d3, ++ 0x6e3bb335, 0x64fb8693, 0xe3b8158b, 0xb66b9c8b, 0x75e5ffa1, 0xe237fd30, ++ 0xc78c0521, 0x524dce25, 0x7c82b57e, 0x78eae453, 0xb729b7b0, 0x7c80731f, ++ 0x14e87c8d, 0xc00f63fc, 0xe51fd6fa, 0xb444fba8, 0x60753534, 0xa9a3f809, ++ 0x6a98a969, 0x52edebcf, 0x29e038d4, 0x1adf77ae, 0x62c4f5af, 0x829e1f98, ++ 0xbcf19cfe, 0xd51baefd, 0xe3e30bbd, 0xdf8c31f5, 0x47c68af5, 0xacf40e35, ++ 0x638aef27, 0xb3c493f7, 0x4c9c87fb, 0x967deb9e, 0x7f0a4912, 0xc8fe8dcf, ++ 0x399ee200, 0x7ac08c0f, 0x5c416c99, 0x768df8b3, 0x3a1a832e, 0x4678bf26, ++ 0x637c2fd7, 0x8cff604b, 0xe976636c, 0xd819fac2, 0xcfb9325e, 0x75f2823a, ++ 0x05c9b169, 0x8b339d71, 0xa380ecfe, 0x5bd28be0, 0x29ef0073, 0xbe910e70, ++ 0xc8f45877, 0xd7c38836, 0xc8944353, 0x477a0070, 0xd71332e5, 0xa29a171d, ++ 0xdbb67fee, 0x39bbfcd8, 0x6a6989c6, 0xd29290ea, 0x41f9e171, 0x8f0d2728, ++ 0x4ad30f54, 0x139cf7c7, 0x8248f8a6, 0xd4fa8d76, 0x58269329, 0x61ecd037, ++ 0x66bfe712, 0x487d358f, 0x75833d02, 0x1f6a62c0, 0xe50e7935, 0xbc6326af, ++ 0xe684ff12, 0xf984be57, 0x7ceae380, 0xff5477b4, 0x8cbea1d7, 0x0adbf664, ++ 0x4e2c34f6, 0xbde7b9d9, 0xf7feb0c1, 0xc7cf0fe1, 0x5fd03ac2, 0xb058aea4, ++ 0x7dee279f, 0x0dce1627, 0x8b2f787d, 0x9861dc57, 0x31b44d47, 0x5b13febb, ++ 0x6bf41671, 0x39efef81, 0x925c309e, 0x635d6cd5, 0x9c344079, 0xcbdfd727, ++ 0x344c1953, 0xc7e3d3dc, 0xe8a52b7a, 0x2e0af6f1, 0x375be587, 0xb42ae92a, ++ 0x06db71ef, 0x823db9c0, 0x2344f2f6, 0xa34a1fbb, 0xb1d6d167, 0xfe9dcc0a, ++ 0xebe66cd2, 0x1b32addf, 0xb045dc17, 0x7ce1e59e, 0x6079d233, 0x5beb0daf, ++ 0x3fb673f2, 0x6b6d2165, 0x9eafb535, 0xc2de7666, 0x1f258fd8, 0x542905aa, ++ 0x101e4b78, 0xef0c5e70, 0x29c74bdf, 0x71fbeacf, 0x4fd8cbdd, 0xc639bde3, ++ 0x7cdaabf3, 0x7f97196a, 0xfea0f129, 0x6d6b9c45, 0xc6d3eb66, 0x83b9dff8, ++ 0xbfec3699, 0x723fc78d, 0x0f3844c8, 0xd0e0fdbd, 0xa7dd4bb8, 0xc3df9a7c, ++ 0x434af704, 0x3047c27a, 0xeca9b2cd, 0xb7e68c9e, 0x5557000a, 0x9ef0db4d, ++ 0x6f6a6fb1, 0x3a4f9b2a, 0x66b30f60, 0xb91fa877, 0x4a43f01a, 0x597f9d05, ++ 0xc2bcf1b5, 0x0f8cbbe6, 0xb7e7f1b7, 0x60b37f41, 0x93fab59f, 0xb7ce5429, ++ 0xc217c855, 0xdbf321ef, 0xfa6ee7f4, 0x9fad5fdb, 0x493d7c95, 0xef11bfeb, ++ 0xa57f1c59, 0x0ed64b9b, 0xdda92ca4, 0x3f087c73, 0x72e7867f, 0xf1193c34, ++ 0x17148cb2, 0xb86109a4, 0xfb187e68, 0xb4afc9a1, 0xafef216e, 0xe3af953f, ++ 0xa8bc42a5, 0xf1189c2f, 0x0db721d0, 0xe235fd01, 0xfb97a3a1, 0x0db61e44, ++ 0xaa957ec5, 0x8fb002ee, 0xeb5d6dd4, 0x4e4bf30c, 0xee077548, 0xccdabd01, ++ 0xde361d70, 0x35ede732, 0x95efc719, 0xdc0a6ab1, 0x9a72879f, 0xcc00fb04, ++ 0x6b4f787e, 0x76e7dda7, 0xcf80930d, 0xf29e9885, 0x0d86bb15, 0xfa5f29eb, ++ 0xf80779f8, 0x09239dcd, 0x623a6dc6, 0xb1eef4f5, 0x1ee74889, 0x2ae71b1b, ++ 0xbc7fd6a4, 0x7369360f, 0x686fee2b, 0x7dc78aff, 0x461732be, 0xfe11e7eb, ++ 0x84f7e11d, 0x4af5c1dd, 0xe02c879b, 0x99a3bb72, 0xda2f5fad, 0x30f28250, ++ 0x5d7acfee, 0xd3a41670, 0xb1c13caa, 0x28dfc80a, 0xefae259f, 0x08afbee3, ++ 0xf8879139, 0xee0f003e, 0x17ad29cb, 0x9461ce31, 0x277635df, 0x56af373b, ++ 0x456dbce3, 0xb870762f, 0xfa8df4dd, 0xc2c7ec63, 0xa2ed0146, 0x9b65fe91, ++ 0x240ed66b, 0xbfd67fd0, 0x06847ec8, 0xfde21da1, 0x4a55fad4, 0x40df785c, ++ 0xdb507ac4, 0xff7c2435, 0xc5e6f2f4, 0x8abf0fb8, 0xb8b09ff6, 0x3481c611, ++ 0x8d7a35fa, 0x4f1028fd, 0xdb8816cb, 0x605c16ae, 0x23ef238f, 0x3beeeb73, ++ 0x6fb0d85c, 0x5dafc810, 0xdb64fb62, 0x03ce02fd, 0x6c203f3b, 0x809d603d, ++ 0xcabd67eb, 0xffed99af, 0xd58e5de9, 0x57dfdc0a, 0x2a8841ba, 0x79f565c7, ++ 0x766161ae, 0xa6607969, 0xde8e986b, 0x5907ee20, 0x7ba250d1, 0xdbd76a9e, ++ 0x8df4beeb, 0x8d47c754, 0xa5fa692b, 0x7fa69be9, 0x3655d8d7, 0x070291af, ++ 0x8ec033d2, 0x10f38a3f, 0xda47876a, 0x91fe7cd9, 0xaa95f479, 0xd6ebcfc7, ++ 0x32e49603, 0x8b112cf9, 0xf66f79f0, 0x6741f294, 0xfaedb38f, 0xb5df0efd, ++ 0x343f5a3f, 0x67fad0bd, 0xff230bd4, 0x519a38b5, 0x03fe460e, 0x781f305d, ++ 0x702d8f7d, 0xcefa009f, 0xb1eff4e8, 0xa91d9d22, 0xf7382ef9, 0x80f847f8, ++ 0x769559d2, 0xc5abe62b, 0x38ed1be2, 0xa4f3e38f, 0x178bfdf1, 0x6abf7364, ++ 0x8e3dd587, 0x4e2a1b9d, 0xad4c5c04, 0x71659b69, 0x943f9c52, 0x88f70055, ++ 0x6db47d4e, 0x17ba8416, 0xf962e43f, 0x58ef6d2d, 0xab8fd45c, 0x0e982ec9, ++ 0x1bb7167e, 0x0d995064, 0x4f35efbe, 0xabce973c, 0xe6f1fdec, 0x1eecf9e2, ++ 0x415e5666, 0xe3a16c79, 0x11a1c559, 0xacfd007f, 0x842a2d68, 0x44054d38, ++ 0x5678e9b8, 0x6c8476e9, 0x9efc6c59, 0xce7bdf4c, 0x788959e6, 0xc706b8ba, ++ 0x12438ab7, 0xc83913ea, 0xed12a0e2, 0xb77e95ab, 0xb9fa8626, 0x126bbf94, ++ 0xaf982e2c, 0x987ee7d2, 0x7049aec7, 0x73d86aab, 0x1df07e4d, 0xc4c6b1d0, ++ 0xbdf7e9d6, 0xedae223a, 0x3efbe312, 0xf302991f, 0x059f168e, 0x9e796353, ++ 0x10f3c4e2, 0xc7162679, 0xa93f9630, 0xa6a259d9, 0x0eaa2e03, 0x4d3e2c2a, ++ 0xac7fc0ff, 0xaa2f4c24, 0x55c73b08, 0xb9e08879, 0x0583aa95, 0xf6056e78, ++ 0xc3ac7ff5, 0xdce6bfe1, 0x18ae0f4a, 0x6125f29f, 0xeb86148a, 0x2eab76e9, ++ 0x4698a62f, 0x18887f42, 0x177382e3, 0x7aa9ba62, 0x78bfed3b, 0x3f294d19, ++ 0x844ba724, 0xa6ea59fb, 0x7ee1154d, 0x7f7e5aa9, 0x9d89ad4b, 0xdbdad72b, ++ 0xa5eb676e, 0x5ec27a5a, 0x9fb9041c, 0xc735b379, 0x702bd6c6, 0xb7f5abfe, ++ 0x01137056, 0x09fb59e6, 0x4ec8079e, 0x3fc02d22, 0x02e7711b, 0x13d90ede, ++ 0x3ad9bf38, 0x874bfd31, 0xbd3665d4, 0xefbc52a4, 0x0161687f, 0x2b829efc, ++ 0x065774ce, 0xbed1ffcd, 0x95c1f514, 0x419f3a6e, 0x7da6fc21, 0x695fcb19, ++ 0xe6943f3a, 0xb197b2df, 0xc2682c3c, 0xe5f6bc3d, 0xd051fe05, 0x56fbc70e, ++ 0x6f8095f7, 0x2de2c4c9, 0xae0acbd2, 0x40fb689f, 0x1589d0d6, 0xb710f1e0, ++ 0xf26b6b9b, 0xf883637f, 0x855bbe74, 0xf89b1dfd, 0x36df413d, 0xda2af8d5, ++ 0x167f784c, 0xf7ffc0a4, 0xb9353f39, 0x95f74690, 0x04960fb0, 0xbac257dd, ++ 0xe7bb09d9, 0xe337b023, 0x0a9d6f5e, 0xedf1bbf6, 0x7de0e73f, 0x7ab197e4, ++ 0xe74ebdc6, 0x673fb480, 0x63783b7e, 0x09f3faf8, 0x2027de7b, 0xf4062a1f, ++ 0x49d5054f, 0x587aa36e, 0x92aa26eb, 0xfd64f309, 0x3091b0fc, 0xad9cf4fb, ++ 0xda3b33f8, 0x5b8e1093, 0x33e2f605, 0x39ecd790, 0xd7e84d69, 0x6b25363e, ++ 0x72e308b5, 0x91d37a42, 0x7fff6045, 0x10f1eecf, 0xbfdc6edc, 0x3df762f9, ++ 0x883f6c66, 0x8083f60d, 0xaa48bbfe, 0xbbc7993f, 0x24993c58, 0x7bcd84e5, ++ 0xf7e83f79, 0xf97f61d3, 0x2fdb1b44, 0x8225fb40, 0x544b1d5d, 0xfc41c74c, ++ 0xe620132a, 0x126efcc1, 0xad0f723c, 0x8b2b31ff, 0x881a591f, 0x2a381e2e, ++ 0x25fdf996, 0x73dd990e, 0x026f0726, 0x2ce621ff, 0xd0ff8271, 0xe122a4f9, ++ 0x79c9227e, 0x1d87ae1d, 0xf7a01130, 0x84e03919, 0xcbae98f5, 0xe9137525, ++ 0xcb93afa9, 0x31f7ab5b, 0xe21cbd45, 0x9838b770, 0x1e4cfa7f, 0x5dcffdc1, ++ 0xac009527, 0x5ba42693, 0x3de3c3aa, 0xf777f9c3, 0x8b2ff33b, 0x9ef37885, ++ 0x4fed0218, 0x02631bdc, 0x6b66fc39, 0xf0f015b6, 0xf288f022, 0xbcecc121, ++ 0x384bea13, 0xc0cde94f, 0xbc5f6ce7, 0xa38d8ea4, 0xad7c9dfc, 0xa5fb855d, ++ 0xaf06b19e, 0xcf9ffdc5, 0xdd3ef09b, 0x09571517, 0xa73c5fe4, 0x3efec13a, ++ 0xc18c1193, 0xc26f3cfe, 0xd318bcfe, 0x4a4ac575, 0x592383f7, 0x11b24a3c, ++ 0x64b2ec09, 0xa4ef57ca, 0x32c7c7cf, 0x7a766afc, 0x9fd32c59, 0xfb8204c7, ++ 0x1e5325ff, 0x3fb68fea, 0xe08bb3a7, 0x37019cfe, 0xe3808ab7, 0x4e2d1298, ++ 0xbe211214, 0xa098a533, 0x2ec536df, 0xd81c39e3, 0xc4e70c0f, 0x3bfb72a6, ++ 0x5c0a83f5, 0x3812a03f, 0xb65df704, 0x59bdf9d8, 0x1af11d7c, 0x49ab938e, ++ 0xe47e089b, 0x2b8917d5, 0xe6bbdb44, 0x8fd514a2, 0x7debc19c, 0x1c52205a, ++ 0x82ef2f7d, 0xf2ee012a, 0x9bcfde88, 0x12705f51, 0x1669c1c6, 0x13f073c3, ++ 0x9e371e91, 0x34e19fe7, 0xcb1d07dc, 0x6421a2fd, 0x30bef848, 0x8667dd6d, ++ 0xf471ea38, 0x17150b53, 0xdd9b65f0, 0x73ac1efd, 0x72655bfa, 0xd3e1b8a9, ++ 0x6f7fb63e, 0x5c18c5e4, 0xb4f8a1ef, 0xa8ae2e03, 0x695bf3af, 0xc618afbf, ++ 0x821c07ea, 0x93def95d, 0xe7608949, 0xce3658e5, 0x3b86a969, 0x8e3397c0, ++ 0xa639cbe1, 0xc6573f47, 0x353ca066, 0x41dc037d, 0xc0e5bb3d, 0xc8eb68fc, ++ 0x632baf14, 0x083f4027, 0x927ecfce, 0x7a0b9966, 0x14d3b5a6, 0x4c6ff0cb, ++ 0xdcacd6d7, 0xfe38eb07, 0x3178d9cf, 0x2545e07d, 0xdf7fbc7c, 0xaaf5e8c9, ++ 0xa06eb375, 0x65daf3fd, 0xe649af5c, 0xf1c289e7, 0x17861692, 0x761d770d, ++ 0xf0d1df16, 0x3bd76d33, 0xf69f3c22, 0x0cce2139, 0xd10f3dd2, 0xcfd533f0, ++ 0x20f53870, 0xc2fa271b, 0x39cbbb8f, 0x0463cc1d, 0xdc320e6e, 0xe07c53e4, ++ 0x82f56def, 0x366e231f, 0xaf9b89f4, 0xaafbfcf0, 0xb92ed33d, 0xd3e4d84e, ++ 0xa634f3ef, 0xf7d16c93, 0x64ebbf01, 0xa94bbd7a, 0xec0b2ebb, 0x7626f5c5, ++ 0xe9224dde, 0xef9c5137, 0x91eed18a, 0xfc84ceaf, 0x9fd98936, 0xb466cd6d, ++ 0x1eecdb3f, 0x5359c60f, 0x9b0e782d, 0xd8369e48, 0x681aefc7, 0x377fc351, ++ 0x3f6e2ee3, 0xd2687282, 0x5fbff071, 0xbdcff265, 0xac6e1b3e, 0x4ca56923, ++ 0x284fe30e, 0xcf5a451b, 0xdfbc8ead, 0x0a3c3d83, 0xb8c16877, 0x7bc14c74, ++ 0x298eaa88, 0xbb7f1768, 0x8802adf7, 0x85fb6a67, 0xab7eee27, 0xbc147f20, ++ 0x0af670cf, 0x1e5aabb7, 0x9d804e8f, 0x3f43dc34, 0x92fcfba9, 0x62f91efe, ++ 0x4f564fc0, 0xf57ef1b9, 0x8ba27039, 0xb5373b8e, 0x598066b9, 0x3eafde30, ++ 0x8bcec427, 0x9ee23ecd, 0xe232a601, 0x878e757e, 0xceeb485b, 0xbef23118, ++ 0xff3e3a6f, 0xe67ffa05, 0x710290b5, 0x7d52a0ef, 0x544f9b25, 0xd1fd8267, ++ 0x28ff0ef4, 0x8e1f82df, 0x9fefddd4, 0x7ffd60e9, 0x7bb125c8, 0x5c14da9b, ++ 0xb0987c17, 0xdc7c82ef, 0x5b2c7bfa, 0xf55ec987, 0x87b07cc2, 0xb8dccae3, ++ 0xc9d2bb4e, 0x253f33e2, 0xc8264b21, 0xfae125cb, 0xa7565046, 0xde7a171d, ++ 0x48f15223, 0x3ddf2d3b, 0xb41c6620, 0x43c3ab7f, 0x49efe01c, 0xbbe1075d, ++ 0xc7b39389, 0x8fb6dd81, 0xe308935d, 0xa5374698, 0xbd8b70ab, 0xae8d0e87, ++ 0xdd5edc33, 0x1c4858ea, 0x6077d803, 0xb68e9a87, 0x0d7be05b, 0x673dc107, ++ 0xf0c3fc99, 0xc1eff200, 0xf200b083, 0x7cac1f1a, 0xfff2d63c, 0x06843c7c, ++ 0xc57a7c81, 0x1c21c403, 0x190f09df, 0x0f0d57c0, 0x1efb5fd4, 0x2d7f35e4, ++ 0x867db0a8, 0x41c35e5a, 0xdf0f3d81, 0xf7042973, 0x56bd910b, 0x13db2e76, ++ 0x2f13eb8f, 0x9d1b5939, 0xa10fb61f, 0xec99262e, 0xc6fa6048, 0x6c643f7f, ++ 0x72bf4048, 0xb708352c, 0x08371fa1, 0xf38ba1ed, 0x020bb48b, 0x7b89b3dc, ++ 0xbfc1d3c9, 0x5e82250c, 0x8517358c, 0x6ddbff00, 0x3fc1d353, 0xc94db6cc, ++ 0x1ced7c04, 0x1835eab9, 0x2c0e76b2, 0xdab3697b, 0x76693fe3, 0xab5785af, ++ 0xc1d33fb5, 0x6e35c6ec, 0xec081e76, 0x9a1d3876, 0x00b107fd, 0x8e68421d, ++ 0xda1b6be9, 0xb036e6eb, 0xe50740e7, 0x34813eeb, 0x67907f82, 0x034d2772, ++ 0x48406f3f, 0xf73b3a02, 0xe204397c, 0xafcd4594, 0x8b7a011c, 0x974ff5b4, ++ 0xe8d3fd7e, 0x8efe6b47, 0xfcd0af36, 0x0b3e6d21, 0x8f94137e, 0xf09dcfe2, ++ 0x7e30237b, 0x4e782c85, 0xea73b1f9, 0xbfae6ee5, 0x1147ed12, 0xa48dc7ef, ++ 0xeed2e915, 0xf381b919, 0x9d20e8a3, 0x39416687, 0x3e53d721, 0x19efcf5c, ++ 0xbfa5deb9, 0xdcc6e147, 0x688cf7e8, 0xbef5f4f5, 0xcab87c71, 0x5df44eb0, ++ 0x763e83d3, 0xf97fc8af, 0xf2773cd8, 0xc12fd150, 0xc69b9a80, 0x327065ee, ++ 0xa2541c3e, 0xe7bf578f, 0xd4d93bfa, 0x94e70596, 0x1bfeedf7, 0xef2f8f8e, ++ 0xe0bbdbfe, 0x293a4e27, 0x3ac7d811, 0x38f8e4f9, 0x4dcf8f5c, 0xad63f5c5, ++ 0x8da7ef5e, 0x239ec236, 0x59dfb47e, 0x71e94039, 0x059f402b, 0x7e9ddfd3, ++ 0xdf5067ec, 0x09126385, 0xa051273f, 0x1c418678, 0xdeff80b7, 0xf98101ce, ++ 0x01f95a4b, 0x0d173bfe, 0x01b0b71c, 0xc47fbb42, 0xebe7261c, 0x9a18bdf9, ++ 0x513faf5c, 0x8aca5278, 0xfdfc0f94, 0x5a0be233, 0xe737615c, 0x13f9691f, ++ 0x7ef9679e, 0xf8129de3, 0x154fdfe7, 0xddac3b89, 0xc19d2a99, 0xb639c587, ++ 0x4a7e0c39, 0xbb3fb3cb, 0xde2b8e81, 0x3adc45d7, 0xf6de6de8, 0x5be4165a, ++ 0x8df7a8c5, 0xfdfbf918, 0xbef13be6, 0x454e3511, 0xfb57dcbb, 0x38a0af93, ++ 0x27720319, 0x61cbcfcc, 0xe51875f7, 0xffeef2fb, 0xd51b6c4c, 0x937bbf3b, ++ 0xbf0e51bf, 0xeb8f9d3b, 0xc3c97d4c, 0xb4bddb88, 0xbfda7e9f, 0x9fa7ed10, ++ 0xfb2f63fa, 0x83ff989c, 0x1af3152f, 0x9e7bbd5e, 0x4e7f044a, 0x448ce9c3, ++ 0xbb499b86, 0xec48967e, 0xf232f23d, 0xdf9702ed, 0x7d9ae21c, 0x0ee7fd03, ++ 0xf68b15c1, 0x615a4fc2, 0xa731563f, 0x02a1ce71, 0x3f083ff4, 0xc71c61ff, ++ 0xf0a388e6, 0xbf9f7b9c, 0x4f2c3373, 0x1c6b7306, 0x57f7e0af, 0x71c6d700, ++ 0x3af5f0aa, 0x02b65c09, 0x63b31569, 0xe8d74fdc, 0x30f9ca32, 0xf47ec629, ++ 0x0711a746, 0xff357a46, 0x17ddfb5c, 0x09198fca, 0xd49bbeb4, 0xc45fec3c, ++ 0xd2f9cc38, 0x5bdbf8db, 0x78e3e2bf, 0xffe39f1c, 0x6fe989fc, 0xd37b7b02, ++ 0x8cdca337, 0x28fd9ae5, 0x31b20680, 0xa23f83f5, 0x3ea325c6, 0x88545c14, ++ 0x0c33f61b, 0x27779fd2, 0xde219745, 0x67b272ee, 0xeaade1bd, 0x127889a2, ++ 0x3727707b, 0xdc036a3d, 0x6cea92ed, 0xdabd1f10, 0xaa0b525e, 0xfcd3fd37, ++ 0x875ef19b, 0x90811336, 0xb3e68cd9, 0xf047102d, 0x1e78211e, 0xdf79bf20, ++ 0x1fe9c034, 0x479c56a4, 0xe4205e75, 0xb33f30d1, 0x06d6b9a9, 0x1253587e, ++ 0x2076cf3b, 0x1df6e89e, 0xcf8e3eff, 0xbb9d8eff, 0xfca51dc1, 0xe786388b, ++ 0x949dc459, 0x2c72e385, 0xd60a3fc6, 0xd3ffb099, 0x24fed705, 0xb1e65bf0, ++ 0xf73ba27b, 0x449fdc4c, 0x3db8ede9, 0x8ccced1e, 0x74effba6, 0xff044152, ++ 0x779f0e3e, 0x5ef0142d, 0x85d50281, 0x0cd282f9, 0xf131afdc, 0x8ab3891f, ++ 0x8ca67ca0, 0x62199bf3, 0xa8f10485, 0x3642a933, 0x0b7717cc, 0xbbf0356d, ++ 0xd612feb7, 0x13fa710e, 0x76f9fe61, 0xfc58e251, 0xcb5538ad, 0x03dfc70f, ++ 0xda798624, 0xf7e71daa, 0xaaf96999, 0xd7ee02d9, 0x274ce19d, 0x14fc30fe, ++ 0x1cf2a3ac, 0x9cd97147, 0x9eb80f92, 0x273fa855, 0x46d8bb38, 0x16ebe102, ++ 0x1def1382, 0x65f7c03b, 0x1efc0977, 0xd7e7ae7c, 0x99cfbc72, 0xaefba89b, ++ 0xd33f3084, 0xf76443bb, 0xdfb1e46f, 0xebf4d69d, 0xd787ae3a, 0x3cf1f9f2, ++ 0x8e8eba4f, 0xc0d28822, 0xf6c9d5fc, 0xa178dd97, 0x12e7870d, 0xf34383f1, ++ 0x8dd77b69, 0xc56bcc34, 0x8b88358a, 0x378eb654, 0x89bd761b, 0xeff53760, ++ 0xcfab98dd, 0x4be3d147, 0x1ecd09da, 0xe223decc, 0x3cece1ba, 0x448167ca, ++ 0xd4dfe9f8, 0xb9344c5e, 0xe83c43f6, 0xbc6e8ba6, 0x5ec22737, 0xadf8507c, ++ 0xa96fc5ec, 0xbd52e60e, 0xe3e38fae, 0x183260e6, 0x710cc6ec, 0x4700cfeb, ++ 0x34dc749d, 0x3691c147, 0xfdf368ee, 0x80c7aa02, 0xad9a721b, 0x98b8ccb3, ++ 0xb49cfb8a, 0x1db77ef9, 0x2b897ea1, 0x23b4bf8a, 0x3da3830e, 0x2bb34776, ++ 0x9c897e61, 0x92fdddf3, 0x551fd419, 0x41be81b2, 0xed0e3fc4, 0x0b25c619, ++ 0xc4142360, 0x62cf5307, 0xd12bc79c, 0xcf8e2bf9, 0x473b314f, 0xf42425ff, ++ 0x5fd187e8, 0x63cce2d1, 0xa53f9a9d, 0xbc7749c7, 0x3f7666f1, 0x029386a9, ++ 0xffe827e0, 0x75c622cd, 0xd68dc2fa, 0x09785f7e, 0x26047b51, 0x70bc57ab, ++ 0x78a6fbfd, 0x5f1b50f9, 0xfd619186, 0x0f8689c1, 0xf1c62f0d, 0xf10cbfe6, ++ 0x9bc6dea0, 0x066f180e, 0xecde3ef4, 0x5da3291f, 0xf9afcbef, 0xf8ecc9c4, ++ 0xca2738c4, 0x67cbdaf5, 0x8d10efe3, 0x1b4476e5, 0x5ae3bab7, 0xfb270cf5, ++ 0xb04916db, 0xfb05e47e, 0x0723d191, 0xe1ac1e2d, 0xc11d6ab2, 0x00ffe7f8, ++ 0x0251357d, 0x00008000, 0x00088b1f, 0x00000000, 0x7cbdff00, 0xd5547c0b, ++ 0x67b7efb9, 0x332479ef, 0x49926649, 0x9d804032, 0x20424210, 0x7860210e, ++ 0x200f3b88, 0x15019042, 0xf01d51f1, 0x28490201, 0xd6b4f5a7, 0xa4484cdb, ++ 0xd179fd14, 0xfd5bd6b6, 0x3d503b9d, 0x4320d687, 0x813c180c, 0xf0c50133, ++ 0x150106b0, 0x888da7ae, 0x31243688, 0xded80f54, 0xbefbf79f, 0x333277b5, ++ 0xee7a5a19, 0x1651373d, 0xf8f5ef6b, 0xbffdf7d6, 0x536b5ad7, 0x6abad1fd, ++ 0xdde80648, 0x0094012f, 0x41ca55d4, 0xa2b5fe1b, 0x899f99fd, 0x58ac19ba, ++ 0xa77f1507, 0xf1022c03, 0x2874a653, 0x62c03736, 0xb395e4af, 0xd176b401, ++ 0x962bd6ff, 0x45f58aa0, 0x6eb9f35e, 0x2dfb689b, 0x6401a9ff, 0xf7a6dc00, ++ 0x607f4c5f, 0x149ac5fb, 0xc5d7630c, 0x6fedd1a5, 0x73ef32bb, 0x896008a9, ++ 0x9e1cf316, 0xa22e52fa, 0x25f66a9a, 0xfa2abd61, 0xc933967d, 0xff10a17d, ++ 0x7ec61632, 0xbe5c032b, 0x352ef958, 0x6e7e96ff, 0xae1e5e1e, 0x002cca47, ++ 0x2e36f59d, 0xb3cfdf63, 0xc0e43f80, 0xe6282692, 0x00a90032, 0xcc5c4e85, ++ 0xb15fac34, 0x13469680, 0xf927c027, 0x43391d3a, 0xf8e00ffd, 0x8c371c01, ++ 0x00f207e3, 0xb93bd60e, 0x87bd66fe, 0xb052b3eb, 0x7ffe3a43, 0xc545aae8, ++ 0xff6fccf5, 0xf9c7e2ae, 0x78515fe6, 0x1eb4e9dc, 0x031fbe3b, 0x7f3d6863, ++ 0xeffe29ea, 0xfb50c2b7, 0x2d2ff6ba, 0x5ed7c9fe, 0xbf9adfcf, 0x75e54520, ++ 0xa4dabcd0, 0x281779a1, 0x9d70a300, 0xf9a3f30b, 0x2b13cc6b, 0x2df958df, ++ 0xcac7fbd1, 0x1eb317cf, 0x83d03e43, 0x87111a60, 0xa04c57ff, 0xfcb6bd4d, ++ 0xf163e506, 0x0d277ae7, 0x6bf00f7f, 0x78d0df5e, 0x4ba0bcba, 0x74164df1, ++ 0xd5d71199, 0x77c6290c, 0x5ce50520, 0x44e109dd, 0xc5d16c24, 0x2a15cfaa, ++ 0x8b9c12bd, 0x39c033c2, 0xd0f2de43, 0x20af73f8, 0xe686d35f, 0xbb20ab9d, ++ 0x1679e98b, 0xa3ace204, 0xa851c696, 0xb071807d, 0x79699b69, 0x9371d708, ++ 0x51f7ee05, 0x1fca2899, 0x2f1e253b, 0xbb7134e0, 0x266cafbe, 0xd76001b8, ++ 0x4072cc81, 0xe756bcfa, 0x10071831, 0xfff70332, 0xb72a49df, 0x0209227b, ++ 0x283f3809, 0x17d2365d, 0x1f201ca5, 0x69194ef5, 0x90e23609, 0x47d84acd, ++ 0x55e7d87a, 0xf6f501a0, 0x60efd18a, 0x91401ee0, 0xcf2e713c, 0xfd4d98d4, ++ 0xb0b35dc3, 0x8ac58ddd, 0xb89b05ba, 0xe977eaac, 0xab7eef7d, 0xedf5fa93, ++ 0x330ec7fb, 0x7815f38d, 0x73784291, 0xfde815bf, 0x4839876c, 0x7cae63f6, ++ 0xbd61365c, 0x8ac01faf, 0x0f2f67ed, 0xedca0057, 0x746ae826, 0xe4933962, ++ 0x077e4718, 0xaa22f5f5, 0x4e50231d, 0xcd397473, 0xc556edd1, 0x48ed997e, ++ 0x841c9245, 0x753b21ec, 0x39a32eb3, 0x63a256c8, 0x17ae1b4e, 0x457cdfdf, ++ 0xe6976b89, 0xfd96e3ea, 0xc9521409, 0xedc68832, 0x8f6136dc, 0x005341ca, ++ 0xc5b0aca7, 0x84bb27bc, 0x4675ccf4, 0xb6499f3f, 0xcbbd7113, 0x976ebdc0, ++ 0xf344c7f0, 0xe629cf7e, 0x25ff2b9d, 0xbfd71bb9, 0x307da2cb, 0x3fede90b, ++ 0xf8ed8661, 0x65622e1c, 0xb4be70c6, 0xf3075ea1, 0xfb17adae, 0x2a6a240e, ++ 0xf08bb3d2, 0x48faa0e3, 0x76ba2d4d, 0xfeeea2fb, 0xbb0e6c72, 0x902a979a, ++ 0xe53c70c3, 0xf7e218c9, 0xfceabe30, 0x8b67e58f, 0xe4764d04, 0xb7bb5973, ++ 0x30cb4c92, 0x1f22763e, 0xbf795fb1, 0x2f5cf3c6, 0xd8fd0d1f, 0x23512175, ++ 0x30baefbc, 0xdbf9a352, 0x86d3af08, 0xfcefbff0, 0x4fd92240, 0x20aaa3e4, ++ 0x365dfa2e, 0xafc676ef, 0x44687dc0, 0xd60b705e, 0x77ce3a43, 0x2d1ff625, ++ 0x322f7e24, 0x34d3b779, 0x4b71faca, 0xdcdd9327, 0xfb1e7e5c, 0x3f481a48, ++ 0x5491fd40, 0x658bdc27, 0xf087f500, 0xc6054816, 0x40421993, 0xf06a36f3, ++ 0x66739502, 0xefc429ab, 0xcbb31c01, 0x29a9e341, 0xcbf87384, 0xc9bee9e5, ++ 0x52def9c3, 0x79c2808f, 0x9a6deb5a, 0xb7b00b92, 0xb6f5c9de, 0x6f970f7a, ++ 0x6e5cabd4, 0x83fc963c, 0xa7538e20, 0x6d253459, 0xaa4a7fa8, 0x68398fd0, ++ 0x39ae8867, 0x88030520, 0xeb8f39b9, 0xe0a457b8, 0x84e48946, 0x27e089eb, ++ 0x3ba065ca, 0x4dbf823f, 0xe9f8d34a, 0xef2c0dac, 0xf71342e2, 0x7c1fe747, ++ 0x7b787b39, 0x7d547b94, 0x3a624b8c, 0xdd9a5cf2, 0x0ee3e585, 0x1a6b925f, ++ 0x43cee1e1, 0x29eb8097, 0xba45bcf4, 0xe384be4b, 0xc1970d4f, 0x4c3fd00f, ++ 0x5f10c145, 0xa21ee7f1, 0x05875a7f, 0x50e83e48, 0x758b2f59, 0x25afb47a, ++ 0x47ce02e9, 0x28edf3aa, 0x0ead67ec, 0x42f68e13, 0xbdf11a77, 0xa3b3e6c4, ++ 0x421d2146, 0x87749aae, 0x66f1c247, 0x32bc5ba4, 0xbe71ce99, 0x7f91eba9, ++ 0x2138e91d, 0xc8e8efb6, 0xdf5152c8, 0x0fede534, 0x9b35af49, 0x0ae22c23, ++ 0x84774f73, 0x1784cf1f, 0x904f149d, 0xf916fb4d, 0xe487f9de, 0x8c35db00, ++ 0x758ec873, 0x86f64c9e, 0xae9b9e71, 0xc256bcd8, 0x7d44753f, 0x5c98903d, ++ 0x3a19f644, 0x371d792b, 0x0a3ac4db, 0x1762fecd, 0xa1f0b3db, 0xbfdfb077, ++ 0x3d90000d, 0x23eba9bd, 0x0a9e9019, 0x37664153, 0x9a4879d2, 0x73e54290, ++ 0xc49e487f, 0x1ee4c9e5, 0x9301cfe2, 0x4f79a55d, 0xb925abd7, 0x5ded1788, ++ 0x60d00987, 0xa1d779cd, 0x3d4ef950, 0x5e22e494, 0x71b7adde, 0xc9dea279, ++ 0x0f7ac9e5, 0x3df08797, 0x7c2de9e1, 0x1b7b784f, 0x08fd53df, 0x18f2a7be, ++ 0xf1654b8e, 0x5e3c493d, 0x1649ddcb, 0x6481c75a, 0x27e63668, 0xc313853c, ++ 0xf805e0ad, 0x366f99ea, 0xbfa346db, 0x4b27fab4, 0xcf597053, 0x60a5537e, ++ 0x31fcd8fd, 0xdf0afc3f, 0x3f4acfcb, 0xb7bd21b5, 0x1eb4749f, 0xaa427ac7, ++ 0xe10753fc, 0x1a2258f3, 0xe56b5247, 0x98025a08, 0x2471b64a, 0x52835db3, ++ 0xf5e9a7ac, 0x254b7280, 0x45596142, 0x00b82177, 0x6e5972ee, 0x977f21b1, ++ 0xa7dffdd9, 0x5cd025ba, 0xd5137955, 0xbe9235d1, 0xeb20e64b, 0x5ee4967b, ++ 0x76eefe8a, 0xaecfff87, 0x49afff08, 0x7d91a69f, 0xe049ae98, 0x83bcb372, ++ 0xe7a1a5e3, 0x1ddbbb46, 0x724cff73, 0xb325c47a, 0x5b36997d, 0xe18e82d2, ++ 0x9bb46bfa, 0x24ad5e76, 0x38bf4df9, 0xc5ca89af, 0xfbae2e55, 0x44d8df96, ++ 0xb8e95ffa, 0xee0aff56, 0xcccba8ff, 0xb0572db8, 0x683f1c5d, 0x208a9bb4, ++ 0xffbbb8a3, 0x3b706248, 0xbf94fae1, 0x73eb0931, 0xb2c5d93d, 0xeb819b6e, ++ 0xe85b6dae, 0xad5bf57d, 0x24de57ac, 0xd3e5c52f, 0x0d32aba1, 0x243997df, ++ 0xe74c986f, 0xd29b8fec, 0xf253bde8, 0xb4cadb12, 0xd094ef29, 0x5bd95cfb, ++ 0x6a53f546, 0x93cb13a5, 0x4bacd94a, 0x7e7e6ed8, 0xfd86d78a, 0x787f864e, ++ 0x965bf099, 0x204de49f, 0x5f04af3b, 0xd7baa5a8, 0x69506dea, 0x2454cf1d, ++ 0xe4aa38d3, 0xe5bd6135, 0x46ff8ad6, 0x52fb9474, 0xbde89240, 0xf5f8a14b, ++ 0xb8fc3fb9, 0x5aed89d2, 0xfa4048c6, 0xf05c3273, 0xacbfa247, 0x404d5133, ++ 0xce2c5a82, 0x62d7ea4a, 0xb91b9c91, 0xf6a0abee, 0xfab33c81, 0xfc7b8e32, ++ 0x83fb3b6e, 0x712777ea, 0xeefc741c, 0xaa17ec51, 0x4e5d9ddf, 0x889371e5, ++ 0xaddfabd7, 0x26f7e2ae, 0xa9519308, 0xdc3be7be, 0x8fc56b6f, 0xfe38dd2b, ++ 0xb62eb1b1, 0x12a7282d, 0x624ec225, 0xffa8907b, 0xbedc353d, 0xe1fcca43, ++ 0x797f6c79, 0x15b14a52, 0x4ee79fe7, 0x955f6a88, 0x2faa8ae5, 0xa2511dc8, ++ 0xeac9d844, 0xf551d949, 0x92a44b5b, 0x78f8c8dc, 0x7d544276, 0x24aba569, ++ 0xedfda237, 0xeaa223d5, 0x8ecf6ecb, 0x669997aa, 0x0f51fb08, 0x9e852bb3, ++ 0x05ccaecf, 0x4f644ca1, 0xdbeda29d, 0xd241fef8, 0x7e2223f3, 0xfc61762a, ++ 0x3ca97284, 0xb97ec252, 0xafdbaec4, 0xa6797400, 0x3f17fd93, 0xea3c7047, ++ 0x9dfc4107, 0xf890f14e, 0x78c2eb29, 0x0523e280, 0x3d0476fd, 0x3f688e95, ++ 0x216a055e, 0xceaadfd9, 0xcd4f1c05, 0x44a92cf3, 0x463e4635, 0x1f92abf7, ++ 0x0c487117, 0xcc47c5dd, 0xcaade971, 0xc46fee8a, 0x7d3a5575, 0x537f262d, ++ 0x0162c52a, 0x1ae28bad, 0x1d063d63, 0x954f5ad7, 0x8a256f7c, 0x2bae6fff, ++ 0xf5807e96, 0xd2c45f9c, 0xf3d2efd5, 0x38a78c53, 0xe54cec0e, 0xdc7f10f8, ++ 0x2303e2f1, 0xfb46a9ee, 0x6fb48ae6, 0x64bdc90e, 0x9bedb5f2, 0xe2b5ee31, ++ 0xa35c633d, 0x3ccb343f, 0xf07fd1bf, 0x7fc52ab9, 0x27db03be, 0x96ee79c5, ++ 0x297f3fe2, 0x451cfdba, 0x1ea0746d, 0x1bc9051f, 0x571f7e20, 0x2ac90a15, ++ 0x544d694e, 0xafc8fdce, 0xff3a3c50, 0xca89a07c, 0xe3c13d59, 0x2dff5c56, ++ 0xfb4ab2f9, 0x143c460d, 0xa9a9aebb, 0x7a390e22, 0xf8abb545, 0xdaa025be, ++ 0x7968bf29, 0x1e53b55c, 0x1541a2d5, 0x38da8be5, 0x37ca7ad3, 0xb12c42b4, ++ 0xec2a9b9e, 0xbfbd04fc, 0xfd976e51, 0xacb15213, 0x4d3f75b1, 0xd5ed48b1, ++ 0x03050b7e, 0x9bce2947, 0x3bce3c34, 0x341d04aa, 0x83c7d1df, 0x1d845f0e, ++ 0x2f38debf, 0x8d36c093, 0x916929f0, 0x96c2a476, 0x8dda45a0, 0x54574eb9, ++ 0x1553aafd, 0x4467bc79, 0xd45bbf54, 0x1876a8ec, 0x1c53e6bf, 0x7c8168d4, ++ 0x29a8ec85, 0x5df14bd1, 0xd65f1f2c, 0x3875efd7, 0xb3027c29, 0x71fd955b, ++ 0x42b792fc, 0xb9f62ff0, 0xcf4b8f4f, 0x7cb07ad0, 0xb2e5553a, 0x2089f649, ++ 0xc266e30e, 0x731d6c43, 0x1e34e5d2, 0xdc21ec8e, 0xcba6ed79, 0x5d437a18, ++ 0x0a2dd16a, 0x54ef7dfa, 0xc38c3fd3, 0x2b534ffa, 0xdf10516f, 0xd7a659de, ++ 0x64feb072, 0xbf515cea, 0xecd534c1, 0x9867f805, 0xb6254b77, 0xf77dba77, ++ 0xfa5f22a5, 0x12cd8ecc, 0x498a33c6, 0x50f76282, 0x05a4fbfe, 0x160a29fd, ++ 0x90b9a641, 0xe455bb56, 0x6809b5cb, 0xb97da8ff, 0x6abf12a6, 0x77390c13, ++ 0x875f9067, 0x644d3307, 0xcdfc8c2f, 0xd87ec16e, 0xafe6cf3f, 0x27097811, ++ 0xbe9768ab, 0x266e6fb7, 0x54e9e2e1, 0xf0bfaf27, 0xb21e59b5, 0x77d74857, ++ 0x47ffdda9, 0xe8f102ba, 0x798b326a, 0x2b0a5a7a, 0x8e16efc8, 0x43487145, ++ 0x9f74c2f2, 0x1084279f, 0x6b971c2b, 0x8deb091e, 0xe2978b2e, 0xbc75a7f4, ++ 0xa8d96f5e, 0x76c84fef, 0xc5391b81, 0x96377eb4, 0xf2f1d0bf, 0x5a2f3e9c, ++ 0x104b31ba, 0x1fece00f, 0xa8b274b3, 0xb9641e13, 0xede29fb8, 0x7924effe, ++ 0xeace3f39, 0xb08ffdff, 0x85bdc1fe, 0xcfa38a5e, 0x2cfe0a26, 0x7634e60f, ++ 0x358a7d63, 0x748c3a38, 0x0fe69a3e, 0xb6ee0e12, 0xde33c706, 0x6893eb1c, ++ 0xce03497c, 0x0efc8c43, 0x32d538f3, 0x3fdc786e, 0x11b05e7c, 0x219cef9f, ++ 0x8bcc6cf8, 0xdf91b53c, 0x3c54a0f9, 0xf9c0e837, 0x837fc443, 0x203a419e, ++ 0x02fbc9cb, 0xe691f620, 0x0fb10eca, 0xf789a9fb, 0xf948ea4d, 0x79dafeb0, ++ 0xbd75e713, 0x9a015e46, 0x7e74c563, 0x78ccf3c5, 0xc4cca367, 0x3a77f006, ++ 0x4a7f9ab3, 0x9e72d6da, 0x3a2bad3e, 0xd3b1bf4f, 0x7ec0e15f, 0x7f187e37, ++ 0x3e96643f, 0x6504296e, 0xba33d7f2, 0xd2cddba3, 0x1759f4f3, 0x4f1f9fa3, ++ 0x48dbfdd5, 0xcfb91918, 0x7fcf41b1, 0xa4e78e06, 0xd6c94e10, 0x8b77c8c9, ++ 0xea69432a, 0xad68dd90, 0x647976c7, 0x4e5c6d1f, 0x807ce53e, 0x047afcf3, ++ 0xa4ec85b4, 0x9f434b87, 0xfb829f26, 0x1e6228a1, 0x1f06f71d, 0x7c143e07, ++ 0xff9dd29c, 0x3758d9cb, 0xa8219a77, 0xa673ad0e, 0x1001a7ce, 0x5a701e7c, ++ 0x8fd3cf98, 0x186a7afc, 0x263d591f, 0x97d62350, 0x1a8226a0, 0xf9ed4f61, ++ 0xd97551a9, 0x671e8f90, 0x4fc7d54c, 0x1a8c8ef2, 0x0c3788c7, 0x3a91bdf9, ++ 0x90e293af, 0x1cd58ea9, 0xe694a477, 0x725b8d44, 0xc84e563c, 0x91db8a38, ++ 0x5c515fc8, 0x8a894a7f, 0x07746e33, 0xfa500388, 0x97131291, 0x8f49956c, ++ 0x7e8f9e66, 0xfbe9a72e, 0xbb72b153, 0xe8a13f16, 0x7fddb397, 0x5a5d3f3f, ++ 0xaad33f34, 0xee99f9a2, 0xe667e68b, 0x8dbe68f2, 0x65f347f0, 0x5189ead4, ++ 0x2faf47ef, 0xfd8faa8e, 0xf6a8ccc1, 0x2300e8d9, 0x2f36e3eb, 0x7e3f6a88, ++ 0xfaa8d2eb, 0x8eefe784, 0x5c105f6a, 0x70bef519, 0x92eb9ac7, 0x86d0e4ff, ++ 0x5ec476a8, 0xff915fd3, 0x458f6d0d, 0x2d5ff3cd, 0x68b48aff, 0xdba45dbd, ++ 0xf686976b, 0x4fc878b1, 0xd90af6d1, 0xdbfb5749, 0x25ff6957, 0xbef2ae50, ++ 0x78016053, 0xcfddf11b, 0x76449f65, 0xdab2146d, 0xc9a37684, 0xdec9ab04, ++ 0xf1326d3f, 0xe7a1a43e, 0x7c44d2ab, 0x8f4d2ab1, 0x14dedc13, 0x1d865fb2, ++ 0xfada6b3d, 0x6c9b8f0e, 0xbf665f53, 0x4cdf0a63, 0xe5479779, 0xe48abbfd, ++ 0x4bf69552, 0xc5de91e5, 0x968711d3, 0x2ba032e3, 0x3fe3c684, 0x7df6877b, ++ 0x2a6c3b2e, 0xf54e54e1, 0xe15fc807, 0x632f42ba, 0x0eda02f1, 0x1d06a3f2, ++ 0xc787d41f, 0xd4647e53, 0x3fd67b97, 0xdf97ed41, 0xf29e365b, 0xf7e7c1d6, ++ 0x8caf8c76, 0xbae47fe0, 0x8b89c696, 0xa6bad036, 0x6ee7ad0d, 0x8dd8daab, ++ 0x85914f74, 0xb07f47dd, 0x7dd70d21, 0x2cdc7a56, 0x9980abe2, 0x8ff42be2, ++ 0xc2efdfbc, 0x96037a40, 0x487e4329, 0x74c116fd, 0xf97c12d6, 0x51cbe239, ++ 0xeff94bd9, 0xca2088ef, 0xeca96c1f, 0xec32eff7, 0xb8a6aaac, 0x701ae822, ++ 0x03a9c744, 0x3b638e0f, 0xcc3ee67c, 0x67af11ba, 0x463d622c, 0x1dba8bfb, ++ 0xc3b742fe, 0x237f643d, 0x6f579bf6, 0xc51259fb, 0x45f267d7, 0xff3c6d3c, ++ 0xa7389a55, 0xcc9a55f8, 0x23bb5d72, 0xefb919c1, 0x45721358, 0x46daebd5, ++ 0xe047cf38, 0x1eb1ad70, 0x7ad0a4bf, 0x53fae9d6, 0x7c9dd9d3, 0xfe3c7037, ++ 0xfc70d23f, 0xef976dda, 0x4dfd4bdb, 0x8fc219fd, 0x3bbe7806, 0xeb8e003f, ++ 0x4433fcef, 0x49bfa5c5, 0xbf2bfb13, 0x865ae9d1, 0xb0711385, 0x8bbb7d0c, ++ 0xcf67b7ca, 0xe7c3bd23, 0x8beb0961, 0x714cc13b, 0xb67f12da, 0x127f9899, ++ 0xe0f7a7bc, 0x54d35ad2, 0xe0eddf5e, 0x7c5f9333, 0x249abeff, 0x9e38376a, ++ 0x002a0e31, 0xb81f6dc5, 0xda0ce602, 0xe249b9af, 0xb3e701b8, 0xbddf73d1, ++ 0xff209ea3, 0x3ef7cc6b, 0x469d2ff8, 0x2f052c7c, 0x0f8c6b8f, 0x87651a90, ++ 0x4c205acf, 0xb38137fb, 0x48cbe0d6, 0xdf8a06cf, 0xf61b0f10, 0xed9db267, ++ 0x3b1ff35b, 0xf776c39f, 0x4d1eea8f, 0x35d9cc71, 0x5c23ce7f, 0xda3cf5dd, ++ 0xae6b5c5d, 0xb841dfdd, 0xe672f833, 0xf449cbc1, 0xc611e31e, 0xf562bc15, ++ 0x5d9c9e92, 0x645e4af3, 0xad2c7fbc, 0x83f530ec, 0xe7b8b4d2, 0xe579b111, ++ 0x9ff04b1a, 0x3bbd231e, 0x0cf1e66a, 0xe3a23e7c, 0x9ab64373, 0x0dcf8919, ++ 0xe4f88349, 0xcbc374b8, 0x0d95db32, 0x5cf813fb, 0x8b8eb4e7, 0xbeae57ba, ++ 0x154a98fa, 0x827e0f11, 0x97115538, 0x554e229f, 0x10cfedd4, 0x2f5f54a7, ++ 0x709dfefb, 0x9f53c9f2, 0x7c3e7324, 0xddd1f5fb, 0x7fbff527, 0x88f7f10f, ++ 0x1801afd0, 0x58fd9f78, 0xf14a816b, 0xabdec56f, 0xa87d93ef, 0x3ef2b56d, ++ 0xf75725ec, 0xfda817e1, 0x7da8093e, 0x8d81386d, 0x14ab6d7a, 0x35abfda4, ++ 0x8d37bb6d, 0xe69afac2, 0xd3042525, 0x3b6064ba, 0x0522db56, 0x42eb3f69, ++ 0x3ce8b87d, 0x378a9fda, 0x71a05eae, 0xe310df7b, 0xe70fac5e, 0xdbd48c51, ++ 0x34f7e2b2, 0x2b56bade, 0xe7fc5024, 0xd1465b0a, 0x10a5bb7c, 0xf43ab7cd, ++ 0x5fc6858c, 0x5c92d2fd, 0xeed6ff0a, 0xb91f18e8, 0xf7bbd41f, 0x3e454584, ++ 0x667d6ead, 0x44aede9e, 0xd460f7b8, 0xc123e8b9, 0xbcc8bc8e, 0x0858a311, ++ 0x420b7c50, 0xfce8ef5e, 0xae3ede5f, 0x7689d891, 0x120bcf6c, 0x9bbb31db, ++ 0x9d81d8ec, 0x34affeff, 0x197fbedf, 0x9281b84f, 0xf837e3eb, 0xd4371c02, ++ 0xc5c0f3ea, 0x03ca1693, 0x17cd5b6b, 0x3cff9de2, 0xdc79f6ec, 0xd8f286d3, ++ 0x3379f8d8, 0x2be503ea, 0xd644ec81, 0x6fd1d90f, 0xfcf48159, 0x3d201a84, ++ 0xb2dfb38a, 0x539beb12, 0xb63976f5, 0x77fcbc60, 0xfe615b85, 0xf9c472d8, ++ 0xfbfbec72, 0x7287f7f4, 0x7ed0b0be, 0xd17aad5b, 0x0dadb842, 0xe5ce2e7f, ++ 0xa79e3edb, 0xaf77e9c5, 0xb33df85b, 0x5b7ab7c9, 0x6c7e90c9, 0x93763690, ++ 0x6fb0dadf, 0xbe71ca82, 0xf4cdd02b, 0x695049ed, 0x3f7b151d, 0x311dde9f, ++ 0x1f111fde, 0xab7e11b9, 0x45c7d776, 0x6bdbe266, 0x4929171f, 0x337bcf43, ++ 0xede3ab1c, 0x16ebdc93, 0x6489f77e, 0xb79a45df, 0xdd55af66, 0xf04ef8c8, ++ 0xeddf0986, 0x40cf3e76, 0x96365b7c, 0x2efbe244, 0x5db6bba6, 0xadbf92f6, ++ 0x6fe25b6d, 0x5e49f6e0, 0x56dc8312, 0xc99c2016, 0x11e31f4e, 0x4df382fe, ++ 0xd071cfd7, 0xff6ec91e, 0xe28bc252, 0xc48f8f08, 0x7ba9ad5b, 0x6c2b9d0c, ++ 0x96b7fb36, 0xec9fe845, 0xdd1ba808, 0xaf34cfc4, 0xcfc90eac, 0xe972126c, ++ 0x5393bb55, 0x1fa26fc9, 0xde957da7, 0xc4c9e7f0, 0x0f6d4dff, 0x73ef48d8, ++ 0xa75e4edd, 0x695012cd, 0xd52c665f, 0x2d9b6e51, 0x57a4d5be, 0x4512339b, ++ 0x7d759b5e, 0xa4bd65fb, 0xfb9d0aaf, 0xa2df79f9, 0xef5bc757, 0xcbfb6068, ++ 0xd0666577, 0x6bd78d2b, 0xda93bf03, 0x1475b5d5, 0xdebdfa45, 0x897a777d, ++ 0xe8a2733e, 0xaf02190f, 0x493ef3b1, 0x99392338, 0x8b2d6e56, 0xedb1fbf0, ++ 0xd1e3aa7e, 0x012803e0, 0xa9c13fde, 0x1df878b5, 0x206f2ee9, 0xea913c39, ++ 0x4c3b27cb, 0x8c1cba5b, 0x74b896aa, 0x449ffb60, 0xcebeffb6, 0xefd98b47, ++ 0xd7aebe24, 0x8f8b66eb, 0xad8a8cf9, 0xae0f1e92, 0x5712c72f, 0xe9d25ecf, ++ 0x2d1d9cde, 0xdb76d8f7, 0x536676f5, 0xe892b3c0, 0xdeb3203c, 0x2cfda9f4, ++ 0x5f5da37f, 0x7f90aaf8, 0xe95be5fb, 0xece6cb3e, 0x2fcf8c65, 0x2c50537e, ++ 0x2c7b8c47, 0x76483cad, 0x0f0319e4, 0xe88780e6, 0x1d662a7e, 0x9fefb74e, ++ 0x34fb11dd, 0x2ebee590, 0x3f9e809c, 0x877f7579, 0xb7ef13f9, 0x97a241f5, ++ 0x3d6efbec, 0xc7c0504f, 0x5783b138, 0x834638e5, 0xa2cf7463, 0x5b04c3b1, ++ 0x9b4c9ab0, 0x62e71141, 0x48c9b2c9, 0xa61b34b2, 0x4b4c74c2, 0xaf70dfef, ++ 0xeb84d05e, 0x590107dd, 0xfbd143c4, 0x9a49a003, 0xf02fb914, 0xfbf89ae6, ++ 0x1bfa2f02, 0xd6ffaf49, 0xb08cc0be, 0xe5258569, 0xe81fdfef, 0x99e74772, ++ 0x2655bbef, 0xf02f942a, 0x06270a17, 0x4c133ec5, 0x4f3efc25, 0xfff7c4bc, ++ 0x45a511e8, 0xb9b7cdea, 0xd7b8dfd0, 0x1b3cd96c, 0xac572bf5, 0x048dea9f, ++ 0x67114ee2, 0xbc37ee0c, 0x5ce39139, 0xe73243b4, 0x969d4edb, 0x6095b918, ++ 0x6f7c047c, 0xbf6a3527, 0x9bf87c22, 0x3bbbb264, 0x4977d553, 0x6447fd2e, ++ 0xa09197be, 0x715c5b74, 0xc52f6af4, 0xa88718cd, 0xdabec2e9, 0x9e79c4da, ++ 0xfc80d54d, 0x39d3827b, 0xafd08e45, 0xa83fba53, 0x8c767c39, 0x4bc8e305, ++ 0x93c9e3a6, 0x7b75fc70, 0xdb69925a, 0xf799ed6b, 0x9815d3a6, 0x857fc572, ++ 0xb485faf0, 0x7146cf2d, 0x1160e6e1, 0xce1427f1, 0x3b7f2149, 0x52808159, ++ 0xba9e9c3c, 0x09398be7, 0x0f9e7dad, 0xfb7261db, 0x9f1455d4, 0x7ac585d6, ++ 0xbe330e69, 0xae03682a, 0xa635b6f7, 0xff7578d2, 0xd9247fb6, 0xc5d257a7, ++ 0xaf6fec7e, 0x15fd144c, 0x527da850, 0x53074bba, 0x73fb44d0, 0x7afbe8af, ++ 0xdc4c57bd, 0x727f98ce, 0x44ec995b, 0x6f0a4c1c, 0x88fbc83d, 0xa38e56ed, ++ 0xc1025e12, 0x3e04f68f, 0x303ba9c7, 0xf50fc81f, 0xe12bc0b9, 0xfd899dfb, ++ 0xeff4f71c, 0xce74aab7, 0x0adce099, 0xf53be7a4, 0x0805517b, 0xd0c716c8, ++ 0x84be6373, 0x1ed25ff6, 0xcf82e11c, 0xad94135b, 0x92239370, 0xefcc49df, ++ 0x3a55c222, 0xd13613cd, 0x78ff4439, 0xd74c31b4, 0xf3c09d10, 0xb016741a, ++ 0xe969df7d, 0x3723f0bf, 0x1c24e5d3, 0x13a08014, 0x9e7027da, 0x78d4e09a, ++ 0xd54e091d, 0xd386901b, 0x81845755, 0xd3cdea17, 0x8f50611b, 0x12ebaf49, ++ 0xd436ea87, 0xa0399d85, 0xb8bf7f9f, 0x447672a5, 0xe94c0c9d, 0xf48aff50, ++ 0x29a5b9ff, 0x02d3f78b, 0x8eda8a32, 0xad2a5265, 0xa1f5e553, 0xc5e9684a, ++ 0x3f740f82, 0xef136ece, 0xce23db07, 0x8877541d, 0xd3ab5e76, 0xf59b20be, ++ 0x078b0e85, 0x49efb2e3, 0xa3370be1, 0xe33cf6be, 0xeb84994b, 0x7c1d31ea, ++ 0xfddb19b4, 0x8f284571, 0x64be6fee, 0x8e9adff5, 0xd1febdf3, 0x932727ca, ++ 0xf669ddbd, 0xe9dd9356, 0xf1cb3c0e, 0xeacd6fef, 0x83bd0896, 0xbe0cfeac, ++ 0x4f33177f, 0xcf8d99dd, 0xb7db7c52, 0x9ce9524f, 0x3fdccfb9, 0x6daee886, ++ 0xf642ccff, 0xc7df6ebc, 0x4a5ecf1c, 0x8e9ddff7, 0x6b6d2bf8, 0x33647be0, ++ 0x23df2b60, 0x82e3d42b, 0x93d84790, 0xdb795381, 0x10e4221b, 0x06fa1748, ++ 0xe4b1fefd, 0x7d75da9f, 0x2e79403d, 0xee3a7b96, 0xefe3471a, 0xa370f3d1, ++ 0x1c1c035f, 0x08df7c45, 0xe839726f, 0x154a826f, 0x7df0ace1, 0x445afddb, ++ 0xfd74c7fb, 0xcf9f4c7f, 0x4f5fe199, 0x38edaef4, 0x75a64967, 0xa18d0f9e, ++ 0xf98432bc, 0x1d8e33b8, 0x18dfd419, 0xfa53aa7d, 0xeebed42d, 0x415db022, ++ 0xa0a53779, 0xbf795efc, 0x7c0ae26d, 0x926507be, 0x19c27142, 0x31ee1f91, ++ 0xfb5146fb, 0x175fd386, 0x495b1d91, 0xbeffc242, 0x2c76bfde, 0x5ff10df1, ++ 0xb67a489e, 0x19aed81b, 0xf4893a7a, 0x224ffb14, 0xbd5097fc, 0x4ef2ed80, ++ 0xd602d74b, 0x20263dcb, 0xb3fc44bd, 0x9dfe203e, 0x39278fe4, 0xffb81f51, ++ 0x9df3d604, 0xe38d265d, 0xe3ebb458, 0x1b7e5eb9, 0x557677d5, 0xe9cf593a, ++ 0xf498be7c, 0xc7907c35, 0x278c0109, 0x8be049d1, 0xe5388fdc, 0x0dba664e, ++ 0x0dce797b, 0x5350dfba, 0xbb0eb8bc, 0x47e9472c, 0x75149f84, 0xfcf68fdd, ++ 0x3f2ddde2, 0xa44722cf, 0xeea709fb, 0x76143f1f, 0x5f741fff, 0x99ade1b5, ++ 0x1e299b8b, 0xf7e6477f, 0x90fdf407, 0x83938eb0, 0xf9087efa, 0xb8aa750d, ++ 0xa7cf4b4f, 0xedef9d61, 0xc82beb6a, 0x6d56951d, 0x4ce5443d, 0x4282a85f, ++ 0xbbcbd9c5, 0x9a85990e, 0x5afe1217, 0x4852de0f, 0xcefad4f7, 0xf5aefc88, ++ 0xffdffe9b, 0xe8f6d716, 0x1c7fe401, 0x61cb853f, 0x357c61fc, 0xdfc33c0a, ++ 0x1d8649f7, 0xf280b739, 0x7956de8f, 0xb2be8ea8, 0xf54d8116, 0x2deef48e, ++ 0x3aac2401, 0x20937b43, 0xe7e99b51, 0x37c4efb2, 0x7b96a419, 0xbce39d4e, ++ 0x15a2d5b9, 0x735a7e12, 0x838cd530, 0x99ba50d3, 0x856250e5, 0x9f80e7b8, ++ 0xb07d8ba5, 0x293c00bc, 0x3b2c5e71, 0xb7379483, 0xe3059aca, 0x58108b9f, ++ 0x8dec8b36, 0x10fa5fbe, 0xfe1a3fe8, 0xd61e7ca2, 0xbc510fab, 0xe1eb7e82, ++ 0x673b0f9f, 0x569e1137, 0x2bf04bb5, 0x17eafb5c, 0x3003dfe3, 0x691e91f6, ++ 0x147876db, 0x4bcd73ca, 0x0dd6edd1, 0x710f2bde, 0x39aeb9fe, 0xb3ff7cfa, ++ 0x196e3d74, 0x6e28e307, 0x7db13c41, 0x69d02b30, 0xcd6efc45, 0x38a69ff4, ++ 0xe09315f1, 0xd655da13, 0xdd6ed3cb, 0x7b0b94cf, 0xf8097fd4, 0x8ec14ede, ++ 0x1fba21d0, 0xdb39b333, 0x54cc734b, 0x6d99fbc4, 0x4067ecd9, 0xbe74ca09, ++ 0xe7f9aa5f, 0xd01d3c71, 0x8c3dd14e, 0x049dbad5, 0x7ed2fe27, 0xd5aebe8a, ++ 0x48f73c7a, 0x19ee9a30, 0x79a46c10, 0xf710ed56, 0x88eed67d, 0x4ebf2f7f, ++ 0xf3dd671f, 0xf6d30e27, 0xba284d5b, 0x9fce9d5d, 0xe7e8b6ba, 0x7b377dc6, ++ 0xac7fbe86, 0xdebeebdf, 0x347f07fb, 0x3de2f88b, 0x7de31c7d, 0x4dc08661, ++ 0xf247922d, 0x8394175d, 0x52d59b84, 0xb7c45920, 0x748158e0, 0x45e0603f, ++ 0xa0fa9fbf, 0x74079fce, 0xb0baf0bc, 0x528bcd7f, 0x1eddce90, 0xfe9a2a7c, ++ 0xe62b4287, 0x71621e11, 0xccd9bab5, 0x581aedf1, 0x36f8a16f, 0x066b5716, ++ 0x42d5b2f1, 0x4f162c7e, 0x1ae97eb5, 0xfcb88b74, 0xb5ee96ff, 0xfbef30e6, ++ 0xe485fdac, 0xadfd100d, 0x3ed0b5df, 0x10fd70e4, 0xe0635df2, 0xdfd75f44, ++ 0x19f99ebb, 0xc227fe3a, 0x556f9644, 0x41e675da, 0x6ef4f1d1, 0x018fd08b, ++ 0x1b4fec45, 0x3fed89f8, 0xe7c78f4f, 0x5e5c0f3f, 0x4c9cbb6a, 0x5d7dcdfb, ++ 0xa5c0c903, 0x1ffc8aa9, 0xec2373d5, 0x22199dce, 0xf9e4de5f, 0xd78a69e4, ++ 0x7b36efe7, 0xbad69ee9, 0xf91f66d1, 0xdfa375e9, 0xf08dc8ca, 0xdbd1df2b, ++ 0xd0fddfcf, 0x67da04c6, 0x25e48df8, 0xff6bebf5, 0x07aa41fe, 0x78ef259a, ++ 0x6bb87fec, 0x2f7477e0, 0x9f63c6bb, 0xedd5e34e, 0x13b85b9f, 0x4fb787eb, ++ 0x95e646f5, 0xfac55387, 0xb3368fe6, 0x6919ecdf, 0xed3575ff, 0x58db6a03, ++ 0x78de7b8f, 0xedf7c2cd, 0xc1e04a77, 0x0e7b0e89, 0x7e401abd, 0x613decf7, ++ 0xa2bc60a1, 0xfba584f5, 0x9703c4af, 0xf30add30, 0x0b56e93e, 0xf3dc2fdf, ++ 0x41ce85a9, 0x98fa5f6a, 0xb4d69ff7, 0xd6476c49, 0x550728bc, 0xfda1ebfc, ++ 0x47085baf, 0x6412cdb5, 0x37be4766, 0x77b27bf3, 0x59acff54, 0x9f034fd8, ++ 0x1a3c752b, 0xbaf034f8, 0x0f33b752, 0xe3c68e6c, 0x1a6da0c3, 0x6a1ffd89, ++ 0x63f7c15e, 0xdf1ada1e, 0x6af618ce, 0x688fe515, 0x1f3d57ff, 0x4191eedd, ++ 0x0ed8061c, 0xe7b3dac7, 0x00533b0d, 0x81c38405, 0x0ab1caf0, 0x13ebfee2, ++ 0x9c42c66b, 0xbae39873, 0xe6fc36df, 0xdbdaf8b5, 0xfe42d976, 0xcccb2eae, ++ 0xd65d4379, 0x9c489657, 0x3271d76c, 0x964bfdaf, 0x077b754f, 0x045cefdf, ++ 0xdfc475fe, 0x2776ed45, 0xddd5c1c5, 0xb4176f42, 0x8941835b, 0x9fb133e8, ++ 0x26a1045b, 0x01df7f92, 0xe0445df1, 0x21e3890d, 0x2ad8edd0, 0x74abdf9d, ++ 0x3cc2aefe, 0xf7dd146b, 0x47e8f3d0, 0xa61db7f2, 0xfab511ab, 0x0e4775f3, ++ 0x179f1325, 0x0b33b080, 0x18cec242, 0xc4fc32f2, 0x7fd87f70, 0x6d7bc91f, ++ 0x59ef95bb, 0xccedd42f, 0x1df166c2, 0xf7deac56, 0xfb8bb08d, 0xbd047bee, ++ 0xb6b17eb1, 0xabfdba35, 0x1cbe2219, 0xdfdae3d0, 0xbaabc8c5, 0x7093ec1f, ++ 0xecaa05bc, 0x2eaf720d, 0x2cefe685, 0xb31cf892, 0x12971d53, 0x51919eef, ++ 0xd78f4efe, 0xda62fa8d, 0x21f6c2df, 0x644756e7, 0x299a5e3e, 0x199ac7fc, ++ 0x1ff88072, 0x2e2cbf91, 0xbf9b8ece, 0xed819a7c, 0xe07acedf, 0xf99129a9, ++ 0x8f2db68b, 0xcf13f870, 0x7ee9aacf, 0xb0b35d4e, 0x38a5bd27, 0xe3c50a6e, ++ 0x5d6df1c0, 0x794835b3, 0x88e21d46, 0x9c22a3bf, 0x4bb67e90, 0x18270973, ++ 0xe3497fff, 0x3ea3a12f, 0x3692ff5c, 0xfc38c7f4, 0x192fca92, 0xc5724777, ++ 0x996f91ba, 0x2301f2f1, 0x22bda80f, 0x79e34de2, 0xf9cdd2ad, 0xb8bb6d40, ++ 0xf07adc5f, 0xa46c98ea, 0x7fff6fb7, 0xe581598c, 0xad0f9d38, 0x7473a1e5, ++ 0x9debe64f, 0xe571b8b6, 0x9a96dda0, 0xcd6a4f58, 0x771c19dd, 0xeef8c3ec, ++ 0xde1fcc46, 0x87f382fb, 0xf70983d6, 0xd2b95c73, 0x57f9d63f, 0x1b00d4e4, ++ 0x08dd3e39, 0xfc525c4d, 0xadcf1912, 0x377b8a72, 0x8efeeb0f, 0xae238fea, ++ 0x73b6c61f, 0x85d9e38a, 0xd259a6c0, 0xd8607b70, 0xef1d1a95, 0xdb6d276b, ++ 0xb1fb5b44, 0xae8d4e71, 0xb3c11847, 0x6f8d8b7f, 0xff75334a, 0xe1b4e3a6, ++ 0x578e44bd, 0x4ec88efb, 0xbe45d3da, 0x8a48d3fe, 0xcf4e30df, 0xf98fb389, ++ 0x1ecb8e85, 0xa1b4bcfd, 0x99be6654, 0x88d28866, 0x8c7f9087, 0x8e13be97, ++ 0x85fbc520, 0x21cf5e07, 0x81ddaff9, 0x0ef522ed, 0x7be7e7e5, 0x5f96414f, ++ 0x67cec84d, 0x57fbc632, 0x913ebc0e, 0xdef0d670, 0x2e427937, 0xee2cf357, ++ 0x9467d36b, 0x58f22492, 0xd8f22493, 0x32774a3d, 0xfb754fe5, 0xbde45f64, ++ 0xb7ce4373, 0x4501f8e8, 0x328bebe4, 0x86efd655, 0xd30b8176, 0xfce2517e, ++ 0x8d7ec4cb, 0xf61fe799, 0xf2f11cbe, 0x101afc57, 0x3afb285d, 0xaee33f73, ++ 0xe98984ee, 0x90313ba9, 0x03dfe911, 0xd9266e34, 0xc07586bd, 0x640ec476, ++ 0x77d21767, 0xf85f587b, 0x4bc70261, 0xac9e7387, 0x2395bb66, 0x47add903, ++ 0x21335bdf, 0x97bc3fd2, 0x8181ce21, 0x68a1e0f8, 0x7e62e7e5, 0x611b0f9d, ++ 0x0bef9ea9, 0xc461df1c, 0x47fe99a3, 0x49e4e332, 0x36ef1bd7, 0xed02b7ec, ++ 0xb59dd703, 0xaf9a3df2, 0x3ce2aff7, 0x27f8ae1c, 0xbf019d90, 0x1f2a06ff, ++ 0x026ab03d, 0xc0faff3d, 0xfef03723, 0xca31b4a5, 0x3e88057f, 0xa745c50f, ++ 0x963be833, 0xf9a7fd9a, 0x7ecd5ffe, 0xf54fd333, 0x58f5ff48, 0xef3fd8a6, ++ 0x7de048eb, 0x0472090a, 0x6a37200e, 0x6fad75dc, 0xaeb11c71, 0x0efa8e4d, ++ 0x45b7e8c1, 0x0369e71f, 0x63492107, 0xe516ef39, 0x98d7b6ba, 0x10e6b59e, ++ 0xd9a1b1cb, 0x14efde2c, 0xe297c625, 0x0d48463b, 0x69bbfd10, 0x6b9c5aff, ++ 0xb6057ef0, 0xc818fd64, 0xf7d2082f, 0x11e8c70b, 0x682075f2, 0xcadcf102, ++ 0x9d8dc1e7, 0x98fbf8e3, 0xdcd7ce81, 0x71c5fcf1, 0x5241073a, 0xfc8b668f, ++ 0x22fdf622, 0x3847d88f, 0xb1d8467a, 0x09fe65a3, 0x0059ecf1, 0x2dbe45ca, ++ 0x356efce9, 0x4f3bc557, 0xb78fa85b, 0x94702b23, 0x3bb3d3d6, 0x7ad3cf81, ++ 0xb45f625c, 0x4288e5a2, 0x6dac59df, 0xff91a695, 0x01ff9b58, 0xf581877f, ++ 0xe15bb612, 0x586e7c7d, 0x9e7bbcd3, 0x918e8716, 0x05bf811e, 0x91e7f896, ++ 0xec532bff, 0x6f049d37, 0x3d1f9eba, 0x4ef9c269, 0xe29d9b56, 0xfdf12a7b, ++ 0xfdbaade4, 0x99916dbd, 0xa09392e3, 0x83b9c59a, 0xac581f38, 0x755bd1db, ++ 0xbbec3cbb, 0x09e117de, 0xfd881f3a, 0xc3b0d7ae, 0x2fe3e877, 0x8dc78d05, ++ 0x0efb3efd, 0xc3bbbe3d, 0xa4fcfd17, 0x20f37f61, 0x086fec8f, 0x7bc901fd, ++ 0xfb024143, 0xc79385d5, 0xe80b8dc7, 0xff55677b, 0x434a99de, 0x1f050dee, ++ 0xda3abfb0, 0xbe55e671, 0x01267f37, 0x6b9ce272, 0x432bf90d, 0xf2176fdf, ++ 0x6a0bcfd6, 0x4346829c, 0xf33097ee, 0x3297dc89, 0xceb5fee4, 0x7df4ffff, ++ 0x22507c97, 0xcbb629f7, 0xcec9affe, 0x387ad8d4, 0xb015c69e, 0x8d75c2df, ++ 0xc635d7d1, 0x2e8fe11a, 0x1711588d, 0x4beb43bf, 0xefbb080d, 0xc0a3b2e6, ++ 0x13577aca, 0xb63bf892, 0x27c8b09a, 0x3e452a6b, 0xe22ad799, 0x4bb765ca, ++ 0xf3624d41, 0x33e88a75, 0x26d8b3f0, 0x9381b7fc, 0xf8e97e41, 0xcfe4f7a1, ++ 0x79fdd56f, 0x40268e2c, 0xe7da3cd7, 0xbc9353bd, 0x16307f74, 0x4f974b4f, ++ 0xf3cc8b79, 0x7883f0b5, 0x63ffefe3, 0xe3d4b471, 0xe749ed1f, 0x64d970bc, ++ 0xc168f71c, 0x37086367, 0x9bd0d7b5, 0x76af5d52, 0xc9470238, 0xd16bafdf, ++ 0x0a5bc1cf, 0x1f89bada, 0x5ef1c09d, 0xd36bab8f, 0xf3071106, 0x384d7839, ++ 0xabfbbf81, 0xf7f3b769, 0x0dad354f, 0x3f291389, 0x76bd976c, 0x9eb757ac, ++ 0x567e24a8, 0x197b8897, 0x8e7e96b5, 0xbfb76537, 0xe45be898, 0xff3a88ed, ++ 0x16bce836, 0xdaed63ce, 0xec3cfd42, 0x2cdecabf, 0x6f3c08f4, 0x63397238, ++ 0x2e754e22, 0x7cc55fcd, 0x16b7eb7d, 0x9bab263a, 0xba3cfaf8, 0xa3d0b50a, ++ 0xcd45bb72, 0xfdb44d1d, 0x62ffd06a, 0x57d853a6, 0xe38b3073, 0x77d749c8, ++ 0xdf61a41f, 0x371445db, 0x291c76f7, 0xbbe044b2, 0xe7da0367, 0x006bf238, ++ 0x0ab7ae93, 0x54b49297, 0x1e846f8f, 0x943fedd7, 0x3d06fb41, 0xa893bfa4, ++ 0x7e4c9d3c, 0xc9f766b1, 0x6714f1e4, 0x31a511ec, 0x9976a5de, 0x9dd281db, ++ 0x24524777, 0x7d304f7d, 0x1c624297, 0xdbbcee80, 0x6fbe4726, 0xffad7ffc, ++ 0xf1a67a8f, 0xfa512777, 0xb309f06f, 0x350efe76, 0xe7cac070, 0x124e74ea, ++ 0x59ea9f79, 0x6237d71d, 0x3a7a4372, 0xc785ce83, 0xc0a62851, 0x205754bd, ++ 0x39d2a4ac, 0xf716586d, 0x7ed8b2cc, 0xbfe7d74f, 0xd0770951, 0xfa19d47d, ++ 0xe84ce2b9, 0xa07376e2, 0x9c0d4b9f, 0x396d1dfc, 0xb52cb978, 0x9a521785, ++ 0xe2142937, 0x19c244ef, 0x4d82eb8a, 0x8e375eff, 0xa6f887bc, 0x1f8305c0, ++ 0x893f9d32, 0xebb17bfb, 0x8f58c579, 0x850eec26, 0xb50f7412, 0xde7c4214, ++ 0xeb74137d, 0xd7f1dee7, 0x34f30b31, 0x09baef3a, 0xf9912775, 0xb3f6e411, ++ 0xbc723d69, 0x642f74f5, 0x93a54331, 0x19c293e8, 0xd7ed6fa6, 0xba3e8ebf, ++ 0xc4fb4895, 0xfef7f40f, 0xbce864a8, 0xf6fedbd0, 0x566f7487, 0x57be34d2, ++ 0x8eefa5eb, 0x2b092f29, 0x2c76833d, 0xb3cda007, 0xdfc92f72, 0xfc012ef8, ++ 0x6229f7c0, 0xe5a04bbf, 0xba18cc5e, 0x37dc65a7, 0xaa5c11dd, 0xb0b7bfd2, ++ 0x7fe36ddc, 0x36d8a59f, 0x0fed2a66, 0xdfe69a3e, 0x567c7a4b, 0x83cf1e6a, ++ 0x1c69c128, 0xb2b8ea77, 0xeb4a5683, 0xbbe33497, 0x0cbc6008, 0x019ef77e, ++ 0xdd8a7dfc, 0x791bbe2a, 0x4b687112, 0x74abf465, 0xaf1e17df, 0xddbe2950, ++ 0x2979b2e4, 0xbd12b37e, 0x1b7a21f6, 0x83dee26d, 0x962b7f71, 0x83c88d8f, ++ 0xaf3fd62e, 0x98e2e38d, 0xb7ee59ef, 0x5f10cff9, 0x9e5497be, 0xe16ef149, ++ 0x8a1ed9ae, 0xeff51bbf, 0x00a51a62, 0xcb80e1db, 0x821dee24, 0xa371c9d6, ++ 0x116ea2c3, 0xbfdf25f1, 0x1cab701b, 0xda4a1e5f, 0xeb113894, 0xbe242b8d, ++ 0xae98d4ef, 0xd09764a6, 0xc81976bd, 0x567637ae, 0xa05f9274, 0x37af14fe, ++ 0xd51a7cba, 0xf7c0e903, 0xb3ff88ef, 0x869bfe0d, 0xefd21ff8, 0x5edb14e1, ++ 0xeefb4d1d, 0x4150dc53, 0xb584a6fd, 0xe30bc4f1, 0xc7940ffb, 0x531e489f, ++ 0xa1f7d1c2, 0xfdf27140, 0x081e4307, 0x53b50610, 0x1f21b397, 0xbaddf1a7, ++ 0xb77d44a6, 0xc9edc86e, 0x331f2144, 0xc71944dd, 0x371a557d, 0xff062e56, ++ 0x62670fff, 0x48106171, 0x00004810 + }; + + static const u32 xsem_int_table_data_e1[] = { +- 0x00088b1f, 0x00000000, 0x94f3ff00, 0x51f86066, 0x257bc08f, 0x799c1819, +- 0x8968c550, 0x1819390b, 0x0bf1030e, 0xda005620, 0xc0c5caeb, 0xfdc406e0, +- 0x88013c40, 0x3eb100bf, 0x01830337, 0xd902a710, 0x736e6852, 0x17ba0264, +- 0xd8815d88, 0x32bf881d, 0x637c3030, 0x767ede20, 0x623da021, 0x2039fe08, +- 0xfd04b2fb, 0xf0d83ffc, 0xdafa655d, 0xc0c2a817, 0x2a83a310, 0x8fc68b16, +- 0x466fc1d3, 0x027c9a3c, 0x8f113f1a, 0x5473717e, 0x2a019d7e, 0x8188c93f, +- 0x9a920f61, 0x6efc037a, 0x81afc741, 0x3100df7a, 0x74769a00, 0x0003685d, +- 0x00000000 ++ 0x00088b1f, 0x00000000, 0x27dbff00, 0xa3f0c0cd, 0xa5f5811e, 0x798a1818, ++ 0x8968c550, 0x1819393b, 0x0331036e, 0x00430317, 0x2064ded0, 0x6bc4029d, ++ 0x101d7881, 0x3033708b, 0x08710304, 0xf9033710, 0xf36e685e, 0xf0606265, ++ 0x2040e207, 0xafe2060e, 0x31bea340, 0xae7f6f10, 0x43169010, 0x19c4cdf0, ++ 0xe9245c18, 0x86c1ffe7, 0xd7d3ebbf, 0x06032cbe, 0x044b7b06, 0x0305917f, ++ 0xaa258383, 0xfc4b471a, 0xc9a13866, 0x5df1a33b, 0x4097e8f0, 0x06b26ff3, ++ 0x8b543f2a, 0x92066181, 0xfc0d149a, 0xc7c7416e, 0x004f7a81, 0x54850031, ++ 0x0368f919, 0x00000368 + }; + + static const u32 xsem_pram_data_e1[] = { +- 0x00088b1f, 0x00000000, 0x7de5ff00, 0x45547809, 0xbedd70b6, 0x4e9def4b, +- 0x62585908, 0x81511007, 0x05e42ce9, 0x62d9b1c4, 0x970621f4, 0x66854611, +- 0x44749ecb, 0xf9d1c1c6, 0x153610d3, 0xc713309d, 0x60ec44e0, 0x81a0d050, +- 0x60241009, 0x3cc0ea03, 0x64ffe31d, 0xb83066dc, 0xc5a4c6b0, 0xfcb8df0d, +- 0x4dd54e75, 0x11d37bdf, 0x7fef999c, 0xca3fbff3, 0xfb5ba957, 0x539cead9, +- 0x2c922aa7, 0x4222e910, 0xab9f83be, 0x409bf908, 0x4d171908, 0x69e5a909, +- 0x24e05295, 0xbfa2e024, 0xe1521366, 0xd3cb4254, 0x43b29909, 0x48955f0e, +- 0xc8428df3, 0x7da6f34c, 0x6eef2c56, 0x53b0f960, 0xfe5a11f1, 0xd3cd1371, +- 0x8ee6033e, 0xe5a0ae87, 0xd9221d91, 0xb28edd08, 0x21124899, 0xfd842dc7, +- 0x0e7cd364, 0x96568521, 0x3fdc68ad, 0xb717da07, 0xf6958999, 0x68bbb157, +- 0x5f3415c6, 0x50264874, 0x32d362a5, 0x97cd1065, 0xc8168484, 0xf3664cf7, +- 0x4314ee0b, 0x1efd689b, 0xcdd24757, 0x574e420e, 0x2147885b, 0x91d9c6a4, +- 0x4268d374, 0xf2db434a, 0xb3695da0, 0x581135e0, 0x5397a6c7, 0x045b5d61, +- 0x4843d9af, 0xf13b66d9, 0xf873628c, 0xde3bfe8e, 0xa2af862a, 0x3ae98be5, +- 0x88b7ed09, 0x1111e6d4, 0x78a75fc6, 0x9df8519c, 0x38e376ae, 0x0b62be6a, +- 0xabb6871d, 0xc2f0567c, 0xc44d2b12, 0xefc742df, 0xf59d6dde, 0xb7d60384, +- 0x84e9194c, 0xa056ad75, 0xde68515e, 0xe607ab4e, 0xd1e4a8d7, 0x4686d2f2, +- 0xb47470a5, 0x03cdb2bf, 0x1faaf3f4, 0x94d7ec9e, 0xd5d3d31b, 0x46467884, +- 0xf884a5f3, 0x44bf685a, 0xc733290a, 0x407fbf44, 0x081909e2, 0x63c48bfd, +- 0x214ff689, 0x4783df89, 0x5e14afe8, 0x844ebdc1, 0xc5b78aab, 0x27bbfa6e, +- 0x6eb3b78a, 0x9229478e, 0x4d5feda3, 0xd03c021f, 0x9c02d4f9, 0xcf96ba68, +- 0x4c9135cf, 0x2eff6892, 0xe903711f, 0x351eb7f5, 0x3cc995ad, 0x185ac742, +- 0xc693e31c, 0xee42bcd3, 0x7e425e20, 0x37c722bd, 0x241fe695, 0x6f3039fe, +- 0x062fe4d1, 0x92d2113c, 0x4abbf402, 0xfd60b320, 0xd349813f, 0x94a955f2, +- 0x6bdc293e, 0x213ce5a7, 0x89ee7c0a, 0xf27c2f90, 0xa7ec74fe, 0x6851fb08, +- 0xdfcfc33f, 0x572f3b8f, 0xaf3b8fd7, 0x0aa7ed58, 0x585db1fb, 0x1379b53f, +- 0x2bc9f3f4, 0x1bb9fb55, 0xd85d71fb, 0x4f57dcba, 0xeae7cfd4, 0x7e27ec72, +- 0x69f897aa, 0x07a5517d, 0x6913e1d2, 0x3e39a3b9, 0xa5a27ef3, 0x812bc98b, +- 0x4b949dff, 0x971174b4, 0x61d1d36b, 0x97412fbc, 0x8fb93da7, 0x30f3ce5f, +- 0x7c82cb88, 0x50520ca9, 0x641a4c2e, 0x35dcf9c1, 0xe17281c8, 0x4bfe09ae, +- 0x301e74dc, 0x79a54936, 0x7723ffc5, 0xf3a6ba0c, 0xa40a4814, 0xc6a4131e, +- 0x8332d5f2, 0x5fc1e4c3, 0xdb463c8f, 0x91914c07, 0x4ebf34f1, 0xac38f498, +- 0x21311363, 0xa9226c7c, 0x33367a82, 0x3ab4f941, 0xa089e73d, 0x866b4e06, +- 0xd10bfc52, 0xfec8d77e, 0x2dafa014, 0xd020e6e4, 0x94a1aadb, 0xf21107c9, +- 0x70a6f074, 0x87eda250, 0x3c00a616, 0x6fe50acd, 0x1d0af8ed, 0xff8e347f, +- 0x03bf8c1c, 0x77d71fc6, 0x5cb0f37c, 0xb496f8dd, 0x16f8dd62, 0xe94f8e85, +- 0x9db9377d, 0x37e14f8f, 0x83e79081, 0xe6f8e1b7, 0x7f1c62b4, 0x758a42b5, +- 0xc77adbe3, 0xfdd6017f, 0x1feb7f52, 0xfebf4136, 0xfafd52b4, 0xc3feb615, +- 0xdf1f1164, 0x63ffeb86, 0x7f5b2170, 0xbf5b295a, 0x3bdbf599, 0xfe17abbe, +- 0x8fbac1af, 0xe1feb7f4, 0xbfebf513, 0x7ebf5ca8, 0x6dff1b33, 0x77c7c152, +- 0x04eff8e0, 0x2ffad9cb, 0x15f1c72a, 0x740bdfb3, 0x55b60ca4, 0x64f8e885, +- 0x64886508, 0x4c3e5194, 0x42102547, 0x6191d7db, 0x6cbb8708, 0xb0beee8c, +- 0x44737a51, 0x51091de5, 0xacf2a28e, 0x597cd392, 0xe40524f3, 0xb953962c, +- 0x754f88b7, 0x74889b61, 0xa1ccea4d, 0xbb7ce98b, 0xe420c4db, 0x195dd617, +- 0x23bf7112, 0x9da00b73, 0xfdf0c244, 0x6cc787a3, 0x98cbaed4, 0x8f95aa2e, +- 0x88f8ea77, 0x993827cd, 0xf3a2aa8c, 0x3044069b, 0x4e3f9a2e, 0xf2a128e5, +- 0x472a7df3, 0xd3213d21, 0x0ff7e8f1, 0x8a259ca9, 0xb1966f96, 0xde483c7d, +- 0x72049518, 0x971cfd82, 0x2f8fbc18, 0xff004211, 0xa1ddd62f, 0x545a7c80, +- 0x8f40a76b, 0xf1c023ce, 0x0e6dd914, 0x9e10146d, 0x2dcf801e, 0xfc848ac8, +- 0x9535a295, 0x7ea8b682, 0x6dddae80, 0x8532b424, 0x76b05fd6, 0x5d3750de, +- 0xccb3adff, 0x1fec2299, 0x84d837c4, 0x9b064c7c, 0xd5990972, 0x4c1e4eba, +- 0x92ccb733, 0xb4d4efdf, 0xe7d7ed9f, 0xe7d62d6f, 0x6c90e5bb, 0x44a37d02, +- 0xdfb48d20, 0xe5f4abdb, 0x42f138ea, 0x1f2bc302, 0x6c4927ef, 0x9a43b7be, +- 0x88dd9f09, 0xd66e39d7, 0xe04f9d56, 0x7184991e, 0x481cecbf, 0xb103ff10, +- 0xd6cddf9e, 0x1cef9c6d, 0xa02be2d9, 0xb77399f3, 0xce34f088, 0xdd9f73bf, +- 0xd34b1a67, 0x20654ffa, 0x8c7ae341, 0xd4bb9ff3, 0xea371eb8, 0xc682f361, +- 0x8c4e8cef, 0x9b6814f4, 0x4d43e034, 0x6b968abd, 0xa1a87c06, 0x33cdb2af, +- 0xd092f975, 0xa2fd5d6c, 0xf2ba79fa, 0xba25b545, 0xee6b05f2, 0x05e7e5d0, +- 0x9fd5d6ef, 0xae9974bb, 0xfbaaf6fc, 0x16b7e574, 0x67e5d3af, 0xeaebd7fb, +- 0x51ab32df, 0x2bec2e57, 0xe513a8b9, 0x54a2ffaa, 0x36df2bd0, 0x9547a013, +- 0x387e55de, 0xe9829d59, 0xa60f6ae9, 0x294f80cb, 0xb3769bff, 0xde71b034, +- 0x2aefc045, 0x55c84e9c, 0x464fc069, 0xd3c237ba, 0x67f4df48, 0x487dac70, +- 0x5205cb4d, 0x87ae7200, 0xf7eacfef, 0x120e5c73, 0x72d31cb2, 0xf96df185, +- 0xc4c9d4f6, 0xc8f0f905, 0xfdff472a, 0xd7011692, 0x1e8b4041, 0xd4a37808, +- 0x70ebc3aa, 0xf6bb3cdd, 0x257e388b, 0x0078eef0, 0x0132c155, 0x307c21f8, +- 0x3031c6ed, 0xcc72df1f, 0xfdc40db7, 0x7f3aabb7, 0xc01287c0, 0x93d300af, +- 0x3d30b3d5, 0xf4c7ed5e, 0x4c62eac3, 0xc2aeafdf, 0x297ab3b4, 0x83ab47a6, +- 0x7aa5fe98, 0x54efa60d, 0x56fa62d7, 0x7fa63d75, 0xda610eae, 0x54c3ed5d, +- 0x395edba5, 0x4af5c899, 0x1dd3ffae, 0xf967f302, 0x7bfa445a, 0x37a3f207, +- 0xacf1f805, 0xa0918be3, 0xcb7d9f37, 0xef2f404c, 0x7a465e0f, 0xc4ae17e8, +- 0x61457a87, 0xac870a88, 0x1b56e5be, 0x44d593c3, 0x1b9509f2, 0xa4fc5df7, +- 0xcc68fe77, 0xda01244b, 0x9d33bc87, 0x411dfa31, 0xc3e75f10, 0xc645f113, +- 0x71f140de, 0xe5bfd1fc, 0xf8e7bf40, 0x283b653e, 0xc2497ee2, 0x5f01784f, +- 0xfee1b81a, 0xe5c1d913, 0xf7e079f2, 0x7e1540f1, 0xa684691d, 0xd2370413, +- 0x3356d9df, 0xed8e0091, 0xfda110f6, 0x84f43d9c, 0xc5bbf60b, 0x87f72629, +- 0xa6a0e031, 0x6ee92d15, 0x689f7687, 0xd6cfe7d3, 0x282df90a, 0x37713d37, +- 0x72ba018d, 0x011c3fbb, 0x54c14ff8, 0x8a7167ed, 0x0070fee2, 0x45f18fc2, +- 0x29d23c73, 0xdeb0dbb5, 0xfd1e7b3f, 0x479d13f5, 0xb680f92b, 0xf8645b47, +- 0x3e91edf9, 0x533e96f8, 0xed4f000a, 0x9fb017f2, 0xefbfe8db, 0x12bf4186, +- 0x037ed5e6, 0xfcd0622d, 0xacdef823, 0xf3b68f1b, 0xb43136a8, 0x255e9feb, +- 0x27a55c72, 0x0bfeda2a, 0xce3b403a, 0xfdcbd6ea, 0xd03e5d78, 0xedd6ea96, +- 0xe50bf003, 0x482c527b, 0x9ce52f40, 0xc7247a7a, 0xefce811a, 0xf461e088, +- 0x157ab026, 0xefc54e96, 0x00ec3241, 0xae7e603d, 0x5b9e6f4a, 0xf972a5de, +- 0xe4c87fd4, 0x9aff287e, 0xda272ace, 0xc4c0951f, 0x780bf344, 0xd96b7e6e, +- 0xa7779074, 0x5e1f6c4c, 0x605c0a48, 0xda931494, 0x3e43d01c, 0xa07ca626, +- 0xffc98ffb, 0xec696576, 0x05261181, 0x8d60b3e7, 0xfaa41f7e, 0x545f2e93, +- 0x9217cfaf, 0xce80921b, 0x1264eb0b, 0xf51f8012, 0xc62689e5, 0x6aa4450f, +- 0x2b0fec15, 0xdf313db8, 0x74c1a44d, 0x1ebb157e, 0xe74799cb, 0xc989b971, +- 0x2ebed56f, 0x2ff36049, 0x7c54696d, 0xd683fcb4, 0x415c9fac, 0x15687da0, +- 0x3b8219f8, 0x4f26ef04, 0xd0fdfc5f, 0xabe71bf9, 0xec7d1fee, 0x8a8f3e7c, +- 0x142f82cd, 0x6f191f63, 0x13fef812, 0x035e3844, 0x99e8d6eb, 0xa8387337, +- 0xf28679f9, 0xeffe430a, 0xa244b7a6, 0x8223b7a3, 0x40d366ff, 0x5fa05f46, +- 0xf1445209, 0xa7fd23ff, 0x9e7fe9f4, 0xb13fdc69, 0xffb421ff, 0x15ff5d1c, +- 0x47fed4ff, 0xddff99f4, 0xd8affab1, 0x906775b5, 0xe7d29bca, 0xba11761e, +- 0x6a929cff, 0xff14bc93, 0xba569be5, 0x4a4e0e80, 0xf3d01741, 0x1f9890a9, +- 0x3f57618a, 0x3e0f4bd7, 0x0f760087, 0x3ffb4afc, 0x3303f4fd, 0x62f97f60, +- 0x7b46ec93, 0x6c39b366, 0xd95afca6, 0x8c9d325a, 0x9631fcc5, 0x0889fd5f, +- 0x7d3d36f9, 0x70f53e96, 0x28c7f812, 0x3f7d70a5, 0x6552fa8c, 0xb07947d3, +- 0x044804ff, 0x0ed8ccf9, 0x80973fc6, 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0x76ecb78b, +- 0xca73ff42, 0xe562dd25, 0x077f4ebd, 0xe715d06b, 0xf73a628f, 0x7bb0f68c, +- 0xf59e79fb, 0xf193e36b, 0x6798c6ae, 0xe394b95e, 0x34d4b6c6, 0xd6d8d7cc, +- 0xabdc03f0, 0xab1fbb0c, 0xa5e3a777, 0xf1e52c3e, 0xafa797a0, 0x15d77352, +- 0x332f9c5d, 0xc972ace0, 0x79311fb7, 0x3b258ef1, 0xe227e7b1, 0x049ac41d, +- 0x82e5f915, 0xf3084882, 0x6eb18e42, 0xbc45db17, 0x89682987, 0x14758a7c, +- 0x02ff7c90, 0xf3269498, 0xef8ce91f, 0x305765e1, 0xd84bb7cc, 0x2107d3a8, +- 0xe8d3d434, 0x1ff61948, 0xf246b76b, 0x34f90c2b, 0x53b589c6, 0xc96fed23, +- 0xe9dfdc77, 0x525e3d3c, 0x79bae6a8, 0x4e1ffade, 0xfa3f1152, 0x12ba7db6, +- 0x6869be64, 0x15ac2cbf, 0xb7ecc369, 0x4683de40, 0x55776fde, 0xbdfb30fa, +- 0xebac0f28, 0x7bd6f189, 0x25d23f28, 0x15a723f3, 0xdfb8b73e, 0xe2f1b5e9, +- 0x2fb199bd, 0x5dff3e23, 0x9477e7df, 0x8b71e9a7, 0xc9fc1248, 0xff5d04ba, +- 0xf94712c3, 0x71b95302, 0x46f49fde, 0xf64cd292, 0xfd36c3f9, 0x76c8a43c, +- 0x1f6f8311, 0x9c73884f, 0x649d3aec, 0xca7c822b, 0xd6fd19f5, 0xed93d53b, +- 0xe29b73b0, 0xf66efbc4, 0x8e23369b, 0x154c1cd4, 0xdadb99f1, 0xe0eccf4b, +- 0x98db6e71, 0x5ebf0aad, 0xe997f3f7, 0x7d712ff6, 0x6869e6c3, 0x0bcf23bf, +- 0x53d9be3f, 0x2dfc42e3, 0x2b817bb1, 0xf2bdf85f, 0xabe4601e, 0x03542bd6, +- 0xfb0e5bfd, 0xbdb2bd08, 0x66f38050, 0xffe90ef9, 0x16d1b7cf, 0x75c73be4, +- 0x82cbccd6, 0xa8a9d87d, 0x176927f0, 0x7ee351db, 0x6923b6c6, 0x72cecd4a, +- 0x962bebd0, 0x32ff1e3b, 0xec76b19c, 0x7b8027a7, 0x817fb127, 0xa03d60fd, +- 0xb4b9564b, 0x4fbb278f, 0xa28af925, 0xbf53fcf4, 0xc2e4317f, 0x23359bc8, +- 0xf20a33ee, 0xf90e9751, 0x63f3d268, 0x0ae7bb9b, 0x4df779bc, 0x4e973be2, +- 0x647be634, 0x0f5583d3, 0x733e5907, 0xb5347a75, 0x7e01bdce, 0x713d8ad1, +- 0xe35ee2a9, 0xfd9ae60c, 0xf7dda6d0, 0xce5eef8b, 0xdf178eee, 0x177a54bd, +- 0x3ef2a654, 0xf54aed97, 0xc2e74ddb, 0xddfeba2b, 0xf2d73ad1, 0x8f334afd, +- 0x7ff1e5e9, 0xde2893df, 0xa5df192f, 0x8ed6e55c, 0xfbe34ec1, 0xf93ee994, +- 0x68964a5d, 0x3e361bef, 0x1d33c06f, 0xd3073bf2, 0xd4373677, 0xd696ff72, +- 0x6718c903, 0x956f43d5, 0xd7108533, 0x1a7c037a, 0x8766cefa, 0xf9a6cefc, +- 0x77bfe1a1, 0x3e435c81, 0x4b211c57, 0x50b6f17e, 0xb543f08a, 0xef90b930, +- 0xfc24bcd6, 0x6a76b3dc, 0xf86eb9c7, 0x44794625, 0x94d9c3a7, 0x7ff05cae, +- 0x7247dee5, 0x9c7c6e71, 0xbdbaf124, 0x7612feb7, 0x4e327b48, 0x120edffa, +- 0x50636dfe, 0xf7c6cbfa, 0x1baa4453, 0xe573f0f7, 0x95bc6289, 0xc63877fa, +- 0x10bfd8ba, 0xa83b1fe5, 0xf7c0eb1a, 0x77e79035, 0xf066e11d, 0x47f65df3, +- 0x4578ef91, 0xbb77bf97, 0x7bc4f3ec, 0xf8045622, 0x1d76ef15, 0xd11e4248, +- 0xecaac3f0, 0xf0ec05ef, 0x7e290e97, 0x4589c39c, 0x863dc427, 0x6ac978f4, +- 0x75b794af, 0xcbce733f, 0x2afc2d1e, 0x08e2d251, 0xd7e386bb, 0x34dfba1d, +- 0x2fdc1f84, 0xfb2d65ee, 0xd2d05fa4, 0x05f84a73, 0x7c619f86, 0xdf6ab747, +- 0x1827e129, 0x941f56fd, 0x283d6974, 0x6d0a1bcb, 0xa025bc46, 0xacbee014, +- 0xd9727c08, 0x38364bfd, 0x25e6f8cc, 0xbd000a1b, 0x5fa43c7a, 0x0b5be5f8, +- 0x33ee257f, 0x71f51bad, 0xe69a7719, 0x4636994b, 0xe5c5c77e, 0xefe83de3, +- 0x5adfdcb3, 0x50fbca0f, 0x8b6135b8, 0xdabb1778, 0x6cec00e3, 0x7cf388f5, +- 0x10ad9b57, 0x4a03c9ef, 0x8ee7f082, 0xc6b9efea, 0x3c4dfaac, 0xd45904e2, +- 0x13cb6bdf, 0xa7f2b8ef, 0x14193cf1, 0x8cbaef14, 0xfc2e67ef, 0x18a547e3, +- 0xe45c767f, 0x97802200, 0x096c7b4e, 0x53b325f2, 0xf8a0a522, 0x951f87a5, +- 0x00e44678, 0x60de50e2, 0xe9ca92f7, 0x695c467f, 0xaf8962be, 0x6568adbf, +- 0xe0eb4120, 0x6b8c9779, 0xfe7c8bf4, 0x8e52698c, 0x7be31cc6, 0x5f51ee24, +- 0x303dc478, 0xf89b5463, 0x228a8bae, 0x147768a5, 0x823e587d, 0xf084265f, +- 0xc93c8c3e, 0x983ccf32, 0xa8ef121f, 0x30df32dc, 0xf02e9fd0, 0xb431ce30, +- 0xda2dd4ff, 0x5dd1cac7, 0xa0fde4d3, 0x63e64e26, 0x399c546f, 0x9b9300ff, +- 0xfa0b5da7, 0x8bdbe4d5, 0xdef1e3fd, 0xbf03be4e, 0x0d6de7a0, 0xbe8e797f, +- 0x9efd1caf, 0xd324bae7, 0x0253fd03, 0xe5ddf101, 0x1ac7457d, 0xfd03ff31, +- 0xd0fe426e, 0xa738c778, 0xabde413f, 0xe716a92e, 0x5073e2ab, 0x563fb71d, +- 0x1de30b64, 0x16e403ff, 0xc7726579, 0x78b6d9f8, 0x395b1ef1, 0x3817cafa, +- 0x9fedb267, 0xfef0a6f6, 0x5152ffb3, 0x07eb8361, 0x26f63cce, 0x3dc1bac3, +- 0x7d8fb1fb, 0xf6235ac9, 0xfaa07271, 0x7e24c694, 0x56e3dbc0, 0xe645f9e5, +- 0xfbbd1ff5, 0x5b34e48b, 0xfa175d74, 0x78733ccf, 0xc45ba02a, 0xb51ce7a5, +- 0xcc5638cb, 0xfa642e7a, 0x6e70bbc4, 0xc17ee827, 0x5ee10b63, 0xef68e738, +- 0x1cdf583b, 0x7dc677bc, 0x6f3cedc1, 0x97c8e73e, 0x1af78a93, 0x64df9d30, +- 0x1ac0ed47, 0xef4a3cfd, 0x0579bdf4, 0xed57c9ce, 0x73037884, 0x963ff052, +- 0x1fc16f7f, 0x699ce3c1, 0x2a36def2, 0x4d3826bf, 0x072863e8, 0x3ed338fa, +- 0xd0b53bfc, 0x638f4534, 0xfc1a7e49, 0xf063f832, 0xdd33a0c3, 0x14a5e270, +- 0xf8b7d045, 0x3fae9287, 0xe2fd7410, 0x4b5626f8, 0xd70fe4ba, 0x7ffefa0a, +- 0xfbc8eba3, 0x0d85df93, 0xde1eefed, 0x7f659e5f, 0xda5ffd3f, 0xeff7d09f, +- 0xd613bfbc, 0x8677a5fd, 0x4e4127e3, 0x7f09b21e, 0x28bdf62a, 0x97b09215, +- 0x1104f6f5, 0xe412d537, 0x276c06f7, 0x349d825f, 0xeab8e3ec, 0x8afc3148, +- 0x638f4493, 0x8f5b115d, 0x5a78ff28, 0xb19390be, 0x7c4b2274, 0x9488e137, +- 0x54ed6fc1, 0x76dd3b02, 0x8733c8c0, 0x7a565f61, 0x42edde44, 0xf27416c8, +- 0xa1a9ddf8, 0xde78cb9d, 0x448b9bee, 0xd102e51e, 0x1f382394, 0x7f082457, +- 0x84953bb4, 0x9daeeadd, 0xe796fc28, 0xc2e7b6bf, 0x4dafed5f, 0x6edbf910, +- 0xfc3b647f, 0x3e09eecf, 0x7f4dc835, 0xf844d0a1, 0x6e05c1ab, 0x02f74f31, +- 0xb7bb0769, 0x83f7c8e7, 0xf209fa14, 0x48ae8f48, 0xeec17910, 0xc42c81dd, +- 0xd24c3ecf, 0x2e1f434e, 0xb873cbb1, 0x19cb8f3b, 0xd4d4ac3e, 0x62bc6336, +- 0x6d48eeb9, 0x797bb3c2, 0x3602f894, 0xb27e5c99, 0x6be4493d, 0xe2317d0d, +- 0xa782e3d5, 0xc64e8276, 0xebefb677, 0x5dd065f2, 0x0eefc809, 0x721bfa0d, +- 0xbba75a36, 0xb794af72, 0xabc7f7a1, 0x1e3fbc49, 0x77c04bcb, 0xaa71f56a, +- 0x32be740f, 0xeb12fb45, 0x7ccb5cee, 0x92fd63b1, 0x1df127fe, 0x95fe30e1, +- 0xd38f42b3, 0xd45fdfe8, 0xf523b493, 0xed16f7c6, 0x282defd6, 0x79153632, +- 0xdc47213b, 0x9abef7ff, 0x8dd80ab8, 0xc125df82, 0x4fff1c6e, 0x80efb0fb, +- 0xbcf215bc, 0x296bc4f0, 0xfdfebda2, 0x1f5fe189, 0x83947ff7, 0xdde4e273, +- 0xfc058caf, 0xad26a92a, 0x70f5d782, 0x70f3e7ed, 0x159fbd74, 0xbccddf11, +- 0x8e65fb5f, 0xfbdfb788, 0xeff7908a, 0x02ffceba, 0xb38b7a5f, 0x000040d0 ++ 0x00088b1f, 0x00000000, 0x7de5ff00, 0xd5547c09, 0x73b9f8b9, 0x2cc99997, ++ 0x6cac8499, 0x1689b0de, 0x1a424270, 0x8b61db10, 0x5c18a3e8, 0x84c0b82a, ++ 0x01327b25, 0xf69e0fa9, 0x69b08197, 0x6b1b6351, 0x304ed1b0, 0xa0d06828, ++ 0x1c048201, 0x69f42d40, 0xb15a7d0d, 0xb22834b6, 0x0dc06486, 0xcefab3df, ++ 0x93739df7, 0x82266f7b, 0xd7ff7f6d, 0xcfe3fef7, 0xb3dce1df, 0xbef9db7f, ++ 0x44e77cef, 0x74891252, 0xc0df2105, 0x588487ef, 0x7190842d, 0xd521293d, ++ 0x7250ad3c, 0xdc04845d, 0x84999ff4, 0xd094b994, 0xa64234ca, 0x3fc3976c, ++ 0x7af9a04c, 0x79a56421, 0x963b5ecb, 0x7cb1d677, 0x08f8a5d8, 0x40d73f2d, ++ 0x6f6d02f3, 0x5af87b6d, 0x2ed91e5a, 0xedd08d92, 0x490b18c8, 0x8d84e422, ++ 0xcd265fb0, 0x6f921167, 0xfab2d967, 0x7da1737d, 0xd8958b61, 0xbb657f69, ++ 0x4b5e660a, 0x650705f3, 0x36ca5502, 0xd3fa50ad, 0x6848517c, 0x64d77c82, ++ 0x0ee0bf36, 0xd689b431, 0x25b772ef, 0xe424e6dd, 0xa88da54c, 0xae55210a, ++ 0x475ba4b6, 0xda1c5211, 0x8aed0396, 0x2c2f051b, 0x4df6ca75, 0xbac2a46f, ++ 0xab5e08b6, 0x66c9484a, 0xb2475107, 0xff437c39, 0x862cd13f, 0x97cb487f, ++ 0xda1275d0, 0xcea9016f, 0xff8c2221, 0x7abaa2a8, 0xd2a677e0, 0xf968e383, ++ 0x1c742db2, 0x05fcaeda, 0x2c4b0bc1, 0x137f10b7, 0x9773bf1d, 0x4ed3f67d, ++ 0x650adf58, 0xb5d60b84, 0x057a8156, 0x761dbca1, 0xaf57e615, 0xe2f2d0e4, ++ 0x7f257aba, 0x257f4f54, 0xe719fb9b, 0xd9343b55, 0xa7372baf, 0x51092a67, ++ 0x8be4f447, 0xd135f109, 0x5214897e, 0xf9ee8d66, 0x238911fe, 0x17fa1124, ++ 0xe9eb6a89, 0xbf12429f, 0xffa5df07, 0xee0af0a4, 0x355c2171, 0xd0f12dbc, ++ 0x783dab7f, 0x78e1e0bb, 0xfa592294, 0x61f4b5fe, 0x4f9d03c0, 0xa689c035, ++ 0xdcfcf9eb, 0x8924c913, 0x11f6eff6, 0x5efa408f, 0xcb56968f, 0xb1d08f24, ++ 0xfb470616, 0xaf34f1a4, 0x4bc4c590, 0x6557cfc8, 0xfcd2a6f9, 0x173fc443, ++ 0xf04abde6, 0x089e0217, 0xfa014a69, 0xd990235d, 0xc31ffeb0, 0x9af969a4, ++ 0x149f4a54, 0xb2d3d5ee, 0x3e05169e, 0xe7c804f7, 0x1a60f33f, 0xfd8053f6, ++ 0xa19fb4c8, 0x93c7ee97, 0xc7e86d93, 0xf5a85393, 0xd8fd8153, 0xea9faf2f, ++ 0xf9c6099c, 0xfd6b14e4, 0x5c7ec72c, 0xcf2eb797, 0xf38d13f5, 0xfb14beb9, ++ 0x25ea9b89, 0xd45f5a7e, 0xf9b481e8, 0x6cee5a44, 0x20fb1b8c, 0xe4c5d3d1, ++ 0x2effc0d5, 0xba7a25ca, 0x318ecd88, 0x2f9c61d0, 0x3da790de, 0x8f7c4e79, ++ 0xe120e9e7, 0x57c70538, 0x17282bfa, 0x61b7f526, 0x4efedefe, 0x4ef70b94, ++ 0xa1e95ff0, 0x49b180f3, 0xfe2bcd2a, 0xe8513c6b, 0x2053ce9a, 0x16aa9029, ++ 0x6be5cd48, 0xc9870665, 0x711abe03, 0x580fb68c, 0x68e22322, 0xf4984ebe, ++ 0x26cb806b, 0xc4f84162, 0xea02a488, 0xca0958c5, 0x5969b5a7, 0x7075074f, ++ 0xe288375a, 0x77e9e85f, 0x014fec9d, 0x6e42dafa, 0xadbd020b, 0xd3d74419, ++ 0x82e7909f, 0x128386b7, 0x3f283f6d, 0x5569e005, 0xc7eb7f28, 0xa3f8e857, ++ 0x6117fc70, 0xfe30eddc, 0x5be3deb8, 0xc61b6487, 0x342e0db7, 0xe8536f8c, ++ 0x77de94f8, 0xf8f9bb91, 0x08137e14, 0x17782579, 0x5c1d6f8e, 0x55afe388, ++ 0xfc61a148, 0x5ff1ee98, 0xef5f7185, 0x2643fd6b, 0xb83fd718, 0x857eb8d8, ++ 0x5910ffad, 0xc18fc7c4, 0xb836fff5, 0x707fad90, 0x95bf5b31, 0xbe3ddbf5, ++ 0x6ffe1bbb, 0xf6efb8c3, 0x13a1feb5, 0xa2bfeb8d, 0x2b7eb8d4, 0x527dff1b, ++ 0xe277c7c6, 0x960c7ff8, 0x515ff5b2, 0x562be38a, 0x48e817bf, 0x11531019, ++ 0x8193e3a2, 0x51922194, 0x1d30f946, 0x6d084f19, 0x2086435f, 0x618dee1c, ++ 0x0c79f774, 0x8f6737a5, 0xca2123bc, 0x959e5451, 0x692f9a73, 0x9c80a49c, ++ 0xf72a72c5, 0x2ea9f116, 0xbf71116c, 0xd0d63521, 0xcedf3a70, 0xf9083116, ++ 0x85d73585, 0xc8efdc44, 0x27685cbc, 0xff7c3091, 0x1bd1b1f8, 0xa732ebf5, ++ 0x13e5aa8b, 0x623e06ed, 0x264e09f3, 0xfce82b23, 0x8c1101a6, 0xa09fc9eb, ++ 0xf9509472, 0xa39521f9, 0xe9949e90, 0x71fbf478, 0xa289672a, 0x6c159be7, ++ 0x77920f1f, 0x9c812646, 0x1213bf60, 0xa589f783, 0xffe00842, 0x158ba3f9, ++ 0xaa8b4f90, 0x3de8141d, 0x3c7008f3, 0x43597645, 0xa784051b, 0x1db9f00a, ++ 0x3f909159, 0x52a6b453, 0xf6d416d0, 0x8bbbb433, 0xd0a75684, 0xe7d60bfa, ++ 0xf5d0f20d, 0x3adb39df, 0x83fd8456, 0x905806f8, 0x4b00c98f, 0x9bb32136, ++ 0xd007951f, 0xe5b3edcc, 0xed75db0f, 0xf98df8e7, 0xf98d0b3b, 0x5b24394e, ++ 0x1228df40, 0xf7ed3d48, 0xb9630aee, 0x109c4e36, 0xc7caf0cf, 0x9b1271fb, ++ 0x8e90ddef, 0xc41ecf85, 0x6b0f5ceb, 0x7027cdab, 0xb8c24c9f, 0x1227b65f, ++ 0xd6227fc4, 0xbad87bf3, 0x2b9df3cd, 0x74b97cdb, 0x8b97733e, 0xfcf34f08, ++ 0x7c3af7db, 0xad343196, 0x120644fd, 0x3cc7af34, 0xcccb79ff, 0x1ea0f1eb, ++ 0x7f341796, 0xa6627467, 0xa4cb40a7, 0xf575c77e, 0xe86e9aca, 0x5f475c77, ++ 0x19679b25, 0x39a145f2, 0xb505fa86, 0x45f28679, 0xf28645d5, 0x1b16eb05, ++ 0xe5c179f2, 0x96f3fa86, 0xdf9430ad, 0xa180f15d, 0x47c2cefc, 0xfe39f90d, ++ 0xb7fa860d, 0x9437aecf, 0x755ef65b, 0xd551f013, 0x7d8122bb, 0x89e733e3, ++ 0xfc1f4187, 0x017929cc, 0x532aa71f, 0x54ce0f90, 0xb67698aa, 0x4cfcd864, ++ 0x8a83e60e, 0x534568b3, 0x9044dd70, 0x67e504cb, 0xc11d8ad1, 0xddaa40e0, ++ 0x4fc22a0a, 0x984855ac, 0xe240b092, 0x2238e9bb, 0x2fdbcaea, 0x194b5e51, ++ 0xb977a33d, 0x7bfd1ed8, 0x15de6360, 0x92fa7720, 0x0037f407, 0xbe2eb9f6, ++ 0x4bcb9bbf, 0xffab9205, 0xe44ac84e, 0xce5c8bf3, 0x1e4c2a96, 0x3a94be94, ++ 0x1f21b899, 0x6df1511e, 0xa05135e3, 0xed049c82, 0x81e8113c, 0x5e818172, ++ 0xbbf81a86, 0xf3889f63, 0x3099072a, 0xee4e441e, 0x4ce4017a, 0x5be0c0f8, ++ 0x7c3cc346, 0x77c0090f, 0xafb8892d, 0xef4e5477, 0xfc025c77, 0xaa7a62e4, ++ 0x27a63672, 0x1e98fd2a, 0xf4c42caf, 0x4c0acac3, 0x61972bdb, 0x8832b47a, ++ 0xd72a9fe9, 0xcac7fa61, 0x548f4c6a, 0x87fa62d6, 0x9da610ca, 0x354c3e95, ++ 0xbf96e87e, 0xe55f5c09, 0x79dd0576, 0xaf817f30, 0xdbad1565, 0x4dee7c86, ++ 0xe0bf3e01, 0xe8047cfc, 0x588e17e3, 0x7dfbe809, 0x6f4ccbc1, 0x87d1e37d, ++ 0x887e4afa, 0x77a33fe2, 0xe1863db9, 0xd3216ec9, 0x0f479509, 0x3bc67f0c, ++ 0x25e6147f, 0x21ba1920, 0xa2b96779, 0x208c3bf4, 0x27852ebe, 0xb98c8be2, ++ 0xc4e3e299, 0x0595ff13, 0xfbe45efd, 0x1101cc5f, 0x7e1261f7, 0xd2f80bda, ++ 0xb5f70dc1, 0xef2e76c8, 0x73bf012f, 0x1b6bf0dd, 0x413a684c, 0x5dfd20f0, ++ 0x0912b668, 0x08ead8e0, 0x1727e251, 0x06ed3e0e, 0x62925c7e, 0x028f1cf1, ++ 0x6b2d2d07, 0xf538f34a, 0x318b4ffb, 0x985aa17f, 0x58f284de, 0x3475bd8d, ++ 0x73c795d0, 0x3fe0187c, 0x9fad5305, 0xe78a2925, 0x33d7e538, 0xb2c6879b, ++ 0xf6c43bfd, 0xa438c6c1, 0x62176a57, 0x7cf47ffd, 0x9b47eafa, 0xe4cd210f, ++ 0x03c81b23, 0xd2f4365a, 0xbc2f4ef6, 0xb92a9f4b, 0xf956af80, 0x6217d073, ++ 0x0cdfffe8, 0xcc257e81, 0x9a06fd6b, 0x1af5a0c4, 0x1868def8, 0x3553b68f, ++ 0xf5da1b9b, 0x3912b74d, 0x9515d1a1, 0xcb180a57, 0x3dda2768, 0xce257dc6, ++ 0xa4b40f90, 0x0cfb0c7a, 0x3ff283fc, 0xd0129415, 0xa2a7294d, 0x4eb9c92e, ++ 0x063bf3a0, 0x25e293f2, 0x657ab020, 0xafc576b6, 0x81b63922, 0x5b3f319e, ++ 0xf6f53ba3, 0x3fbca80f, 0x7932effd, 0xa2bfca10, 0xe9eacab3, 0xc410ee8f, ++ 0x780bf342, 0xc9737e6e, 0xa77b900c, 0x5f9f6c2d, 0x60dd7248, 0xea9214f4, ++ 0xce73d02c, 0xa074cb11, 0xf7e473ff, 0xbd9d0cee, 0xb828b5e1, 0x8ceb05ce, ++ 0xcfd52cfb, 0x5a82f90c, 0xdc9f3e63, 0x9ef4049c, 0x9093235f, 0x2c697c00, ++ 0xec1e2d57, 0xac5480b7, 0x8abfb901, 0x3df32bdb, 0xe7401a44, 0xc9f3b657, ++ 0x8f3a3cac, 0x9e985bef, 0x45efd9ae, 0xc5fe6cf1, 0x8f8af54d, 0x9cd47f96, ++ 0x096be3f1, 0x01ad0fb4, 0xbb70463f, 0xf6a4dde0, 0x9d77dfc6, 0xdabe79bf, ++ 0x8fcbd27e, 0xb651e7c0, 0xa285f059, 0x2cd327ec, 0x82b7d702, 0xeb06de98, ++ 0x79ade9d6, 0xbe5a0e1c, 0x6e5f94cc, 0xf4cdffca, 0xf40c4096, 0xe7f04c76, ++ 0x7d191259, 0x4820be81, 0xf7ffc511, 0xabd29ff4, 0x687fb2ff, 0xff6903ff, ++ 0x97fe8659, 0x1ffb43ff, 0xabfe6bd6, 0xb65ff5a3, 0x208eeb73, 0x2fc53795, ++ 0x7426e63e, 0x552d3a1f, 0xfe297927, 0x76ad374b, 0x929c1d03, 0xe7a06e82, ++ 0x7a7121d3, 0xbedd8a28, 0xfd01e81b, 0x00a73e88, 0x93fc1576, 0xb9e67ff6, ++ 0x7d84cd9f, 0xb24df3e6, 0xcda5ed07, 0xf295b0d6, 0xd173796b, 0xf306320c, ++ 0xed7e58c7, 0x2df21179, 0x7e2cfa46, 0xf024b1f6, 0xe14a51bf, 0xf51844f6, ++ 0x8f86f2a5, 0x0a1f6073, 0x99f20890, 0x7f8c1db9, 0x63e51e31, 0xbbdb129e, ++ 0xf513ce9c, 0x4b8700fc, 0xe767f9a0, 0x927df045, 0x3507e676, 0xfae42fd5, ++ 0x95c5a34f, 0x4e9a8270, 0xfbe4fbe4, 0x78352f20, 0x7fd31090, 0x3e3cb6aa, ++ 0x4f9d18e6, 0xbbbfc347, 0x349c1d05, 0xb4d0bb3e, 0xa8afd7e0, 0x4ee3cb7d, ++ 0xb4f5e76e, 0xb53b610b, 0xad6deb85, 0xc3952d2c, 0x4b8bd06e, 0x906f65eb, ++ 0xfadd2e7e, 0x804f33f4, 0xd5befa9d, 0x5ff69c3b, 0x3ff5f5b2, 0x92f9a04c, ++ 0x0cc2726d, 0x90a70cb6, 0x009783d4, 0xd8d97ffd, 0xbf143c1e, 0x8ea2bafc, ++ 0x8fefdf66, 0xc947c1ef, 0x190a7db6, 0x531e1bdd, 0xed29f69a, 0x697828ce, ++ 0xfa03963a, 0x2f96d555, 0x4f27b014, 0x724815ef, 0xd678145a, 0x027a8ebf, ++ 0xc8f109c0, 0x378dd4f1, 0xc500fd53, 0x0d73c80b, 0x87f2e64f, 0xfe81fcb9, ++ 0xcf4851d4, 0x7e02bc2f, 0xbd5a3fe5, 0x17c2feb0, 0x3ac371ee, 0x8c154a4e, ++ 0x9d5c9fae, 0x16e3a3e4, 0x0f24c1ca, 0xe17beca6, 0x7a413f53, 0x93fc382b, ++ 0xfa0f6624, 0x37b82d52, 0x7d615305, 0xc36eea8b, 0x3f13e5f5, 0x93e15dd2, ++ 0xc7c82e62, 0x7d3224cf, 0x48be145b, 0x9c5f1917, 0x2e1548dc, 0x6093beba, ++ 0xff3c8097, 0x84da18bd, 0x04c590fe, 0x9a27fff8, 0xc12c9c7f, 0x863667fc, ++ 0xe1689b27, 0x3db5457c, 0xac36bd3d, 0x9cfc036d, 0x064be419, 0x48805a3f, ++ 0xe10f0e41, 0x78afda1b, 0xc3325a78, 0x2ca5510f, 0x01ea8ede, 0xd43be053, ++ 0xf67d936f, 0xe4768631, 0xf19eb49b, 0xe9f1f297, 0xff6063bc, 0x0a44993e, ++ 0xefaca29b, 0x7be3516e, 0xe8eb8fba, 0x8cdfc74b, 0x601e1bdf, 0x7bf1adfc, ++ 0x2874d668, 0xc61df4ff, 0xf60ed03f, 0x70af3a47, 0xbbef9632, 0x60794055, ++ 0x7c68e125, 0xbe7320dd, 0x746b9636, 0x092de742, 0x817a3ab1, 0xfe11e3fe, ++ 0xafcb3fe8, 0xf274eda1, 0xb9e30032, 0xf1a7f77b, 0xffe7016d, 0xff91a251, ++ 0xfbe31d49, 0x20abf5be, 0x72a573ee, 0x802799e8, 0x067f295f, 0x3957e055, ++ 0xb67dd617, 0xee1fc0f1, 0xb67a7ca0, 0xa353e349, 0x69f334fc, 0x049b4be1, ++ 0x9f334fa0, 0xdaa42d9e, 0xa53e3448, 0x69f2a3df, 0x53fffb61, 0xefc1a9f9, ++ 0x34fc1356, 0x1c17d879, 0xbcf0f2cd, 0x9a784545, 0xbdfd21e5, 0xd37ab243, ++ 0x1a77469f, 0x5f3f15bd, 0x0bfa0576, 0xe8d4ba34, 0x352e9bae, 0x7fe5ebba, ++ 0x5ccfc031, 0x8168183e, 0x2eee49d2, 0xd2aaed19, 0x461e7656, 0x2031bddb, ++ 0xc3e4e113, 0xbf548c6d, 0x9f412031, 0x4df2990f, 0x533efaa6, 0xdf54d73e, ++ 0x1857ca6f, 0x1cb697ea, 0x3fe20850, 0x5d67a86c, 0x28f904f6, 0xeda43d8a, ++ 0xf3e68137, 0x62e8104a, 0x79014460, 0x4124af27, 0xf707f817, 0x762f6888, ++ 0xa1af1851, 0xa63574e3, 0x6e548285, 0x3b33b6ac, 0xaca8923c, 0xe5d73901, ++ 0x21e3b889, 0x6ffa676f, 0x1dc46e57, 0x8f23d3a7, 0xa7288ab5, 0x7a6443db, ++ 0xdd07bf34, 0xedcf1041, 0xe672afa4, 0x3a269cef, 0xfb032f07, 0x82f45ab3, ++ 0xc570bb49, 0x8d706eed, 0xbd0eb574, 0xbefd3669, 0xc78890e8, 0xee315d28, ++ 0x122f3031, 0x3aa949f4, 0x0914e1fb, 0xf82272fe, 0x1d995b2f, 0x49bd70b1, ++ 0x91eb20ff, 0x4b9df27e, 0x549f9015, 0xe8d0ffef, 0x507c65bf, 0xac2bfbcc, ++ 0xed6b9633, 0xec0b04e1, 0x6306e2b9, 0x43db9fb9, 0xe02f813b, 0xa49d253c, ++ 0x43015ca3, 0x2e71ec07, 0xa389a787, 0xe14d9a6e, 0x245075df, 0xa1797e70, ++ 0x5ff84455, 0x95e76468, 0xfc889824, 0x28224e55, 0x753834ff, 0x7d28ff00, ++ 0xed8ea7cb, 0x0fbace7f, 0x07c764e8, 0xd3457e63, 0x8fef1d8e, 0x9df90dd8, ++ 0x80fe0def, 0x653faef4, 0xc4fd1daf, 0x485d7b5d, 0xde7b5ddf, 0xe41f7c1a, ++ 0x3fd15977, 0x8bf7b5d7, 0x5d6f4031, 0x2085ad2b, 0x5106badf, 0xb03e83fc, ++ 0xed318be7, 0x42ae9fb8, 0x2a287dbc, 0xfd6a1f4c, 0x0242a3af, 0xa05574a4, ++ 0x2075ec27, 0xb15e04ff, 0x6ba13fa3, 0x7e5917cf, 0x3d6e3fe7, 0xa6fcfce5, ++ 0xbf6645cb, 0x638bf304, 0xeec0ef7e, 0x80af4ff1, 0x7de6e7f3, 0x3e5a02ca, ++ 0x8ebfd5e5, 0xf5d9b901, 0x3a7fd312, 0xe0a7f6e5, 0x789ce27c, 0xe14c857c, ++ 0xd44c09dc, 0xa407909f, 0x4f8193e1, 0xafe5c37a, 0x5cb927e8, 0xffd24878, ++ 0x3e087816, 0x215cdf26, 0xfeeb009b, 0x2007e8f2, 0x915af607, 0x9ef5b52e, ++ 0xfa815a6d, 0x3dd6a5c9, 0xbadcfff4, 0xace5f085, 0xfcc4b27b, 0xebacff0f, ++ 0x38aa283e, 0xf41f334f, 0xf73df3a6, 0xcbab7e62, 0x4cbdf38b, 0x7fff9f7a, ++ 0x512fef0d, 0xbd2fbbbc, 0x6bff15ee, 0x2e687ef1, 0xce07bbc7, 0xfeaf03f7, ++ 0x5df7e715, 0x3ffd5ce5, 0x5afbde39, 0xffc7a6bf, 0x93bea2c6, 0x274feb4e, ++ 0x2c504ed5, 0x7fdb286e, 0xfe969d28, 0x3881e066, 0xd364ef98, 0xfe968d79, ++ 0xd276625e, 0xf682c164, 0xb813891f, 0xa6ecc7fd, 0x187f5c01, 0xf51f34b0, ++ 0x1f030190, 0xa4837a62, 0xe379c0d6, 0xf02f066f, 0x1904ec62, 0x790fc47b, ++ 0x6f3c75cf, 0x257f1fb4, 0x851c1f10, 0x2ffc180e, 0x1d8f4107, 0x3d445038, ++ 0xdfa8a697, 0xce9ee6be, 0x062a97be, 0xd506e73b, 0x24e4f768, 0xa9a3ed18, ++ 0x8469bfbc, 0x539a7fcd, 0x1c288508, 0x45fa0f26, 0x2743f802, 0x4089970f, ++ 0xbfc439f3, 0xa989ec0a, 0x2f7f634e, 0xb8cd99c0, 0x740e381e, 0x2e80962e, ++ 0xda1e83a6, 0xb3a7ea0f, 0x84a0c0fc, 0x0f5c39e7, 0x2c5d5ebd, 0xca7e6905, ++ 0xe00974c0, 0xb96b605b, 0x36ebfc11, 0xb8f380af, 0x7282c3b2, 0x202996c8, ++ 0x95ac8cfd, 0xe2d87f30, 0x99f80719, 0xb3ceed79, 0x63f809cb, 0xa78b0a7d, ++ 0xf57e65c9, 0x66f9beaf, 0x71a1c422, 0xffd017b8, 0xe3fe047f, 0xa18e123a, ++ 0x91245a70, 0xf83c6c60, 0xa1f20553, 0xcc6a9fc1, 0x4907efc3, 0xaa5cfd3d, ++ 0xfbf45f7e, 0x52774e8f, 0xc290f97e, 0xc3a4177c, 0x6f497870, 0x95bf7daf, ++ 0x26f02bc1, 0xe7610d09, 0xeeae62f5, 0xcc9269fc, 0xff3bbbfc, 0xd80652f4, ++ 0x46ba934b, 0x1e3e32c5, 0x80697a86, 0x8817a5eb, 0x0275eb1a, 0xc58d0f1f, ++ 0xa283b573, 0xdabc5a2b, 0x3dc76e16, 0x340b710f, 0xd5206aed, 0x2409d822, ++ 0x60c1fe82, 0x8a6c8d83, 0x4a313712, 0x1c1ffcd6, 0x6627f46f, 0x8d9f9f81, ++ 0x8d3688bf, 0x63ade3d5, 0x4c6969c6, 0xefc03c6f, 0xc739dd43, 0xb05f0bdf, ++ 0x5bbe011b, 0xb939edec, 0x07fdf851, 0x99f7e332, 0xbf44bffb, 0xf5add5da, ++ 0xabdfa016, 0x73862c1b, 0xeb992cbb, 0x58c963fd, 0xfdccd798, 0xe0265776, ++ 0x85e8a0e5, 0xeb40c138, 0xe51fc579, 0x4f0cc9bc, 0xb4fc1fe8, 0xe20f654b, ++ 0xb4dcb76d, 0xfbbae000, 0x7d808d9c, 0x2ea94bb6, 0x13cf3689, 0x22e79b0a, ++ 0x98cf74d2, 0xf83e7fb4, 0x8672ea4e, 0xd39d8327, 0x6d3db840, 0x74823fa6, ++ 0x0933617c, 0xbb071c81, 0x85c2e408, 0x08fb8246, 0x6043c905, 0xff7e51df, ++ 0x703fdea1, 0xe7b6cb65, 0x6f29ff61, 0xbae03c15, 0x15da972e, 0x5a05fff0, ++ 0xf79044e2, 0x4716aae9, 0xab7d19e9, 0xca962f8e, 0xc0f7c212, 0xc277dd84, ++ 0x28749fb8, 0xdf43f604, 0xec37116b, 0x66b49f17, 0xb5f41f20, 0xc92b97ae, ++ 0xe825538d, 0x3343c987, 0x8c6a8c3d, 0x15afe431, 0xbf81fdfd, 0x97db5a66, ++ 0x2fe0a37a, 0xb2efe389, 0xffe85be5, 0x8ef6f933, 0x62fcdf26, 0x8e8f8eae, ++ 0xc96f96f6, 0x12dbe4d1, 0xb8064d41, 0x3433d92f, 0xe4baf019, 0x4d189c90, ++ 0x64ad6dbe, 0xf22f67e7, 0x66aed7f8, 0xd1aedf2a, 0x2a66b7c9, 0x19c4a2df, ++ 0xf95cbc1c, 0xe19ffa16, 0xdf20adbf, 0x03f7aca2, 0xbe4d3f0e, 0x863d698d, ++ 0xb34c6df2, 0xfa2710c5, 0x37ca4bfb, 0xd056f121, 0x5eca0ec3, 0xd9fa1447, ++ 0x17bef5ca, 0x8c1bbc79, 0x4e2e7203, 0xee726ef9, 0xb9cae5c2, 0x6b3821ff, ++ 0x76c96e72, 0xbdb3f182, 0xb9c990e9, 0x9ca8bb25, 0x991e8013, 0x87b25b9c, ++ 0x498fff30, 0x25ec8dbe, 0x2fd608df, 0x81f6b30f, 0xefc7b496, 0xf58dfda2, ++ 0xad1b5ec9, 0xde47b63f, 0xbbcbd38d, 0x790fa538, 0xe4f2f077, 0xef2e76dd, ++ 0x021b1ca8, 0x1f4cd5f2, 0x9c6356de, 0x27f1eef1, 0x7e065f1b, 0x73c44b79, ++ 0x7616c3ac, 0xf1bbf0ee, 0xbe813327, 0x143e610a, 0x4615138f, 0x41959d7f, ++ 0x6bca7fec, 0x4e657d6c, 0xde5c7f16, 0xf2c3f4cc, 0xd2a42146, 0xf84ce67f, ++ 0x17f98152, 0x324811ed, 0xb2b2cfcd, 0xed59e4fa, 0x48cc861c, 0xc2c3d1d7, ++ 0x1ff412ec, 0x0d88942f, 0xce25c3fc, 0xffa0d39c, 0x7f336496, 0x5eff0972, ++ 0x0d7da874, 0x368b55f8, 0xa70e7808, 0xf16a4dc5, 0xe3cebda3, 0x1fa0575b, ++ 0x3f2e7cd1, 0xcce3c793, 0xd5085e7c, 0x282b8947, 0x238a6cd9, 0x4b3cf4e4, ++ 0x9178476c, 0xa6ef45b7, 0xd5a3fc28, 0x41d386eb, 0x1106a70e, 0x386ed3f7, ++ 0x69a9b851, 0x3144e1bd, 0xa93d233d, 0x6f452e07, 0xf666f5d1, 0x6e0d5ebd, ++ 0x7e6b75e6, 0x4fde12d2, 0xe0d0705f, 0x1cfd6bdc, 0x402ed4ee, 0xc7866939, ++ 0x7fdba53c, 0x2ff1019a, 0xce506e94, 0x622b7f04, 0xa4ee44dc, 0x147b86e1, ++ 0x64fd388b, 0x029a4f54, 0x20b3e4c7, 0xe796995e, 0x237e2ed7, 0xdc63c295, ++ 0x6c2c7511, 0xb04ed7a7, 0x6f7ce1fa, 0x72823d8b, 0x5dc3a350, 0xc17f0e9c, ++ 0xbfddd9fb, 0x93da3262, 0xf407822d, 0x8ed84090, 0xb8500d70, 0x8096bdc2, ++ 0xa01bf0c4, 0x77fc08f4, 0x0ce7c360, 0x15047b8e, 0xda3908fc, 0xa178057e, ++ 0x195a33f5, 0x0121025e, 0x224992f1, 0xaf2fd7e8, 0x8061bc15, 0xc23d4b5f, ++ 0xf4cf934f, 0x49e3d4e7, 0x3452bf47, 0xba4ac5fa, 0xd784b2fd, 0xfead699b, ++ 0xccf3d003, 0x8f526567, 0x7dffa6e0, 0x225f3d1b, 0xa78cc4be, 0x5b5e1c9d, ++ 0x804e9e01, 0x5de9845b, 0x9ef12fe1, 0x901e568d, 0x4e780682, 0xb7e2e279, ++ 0x069c6bc2, 0x9063a02f, 0x2279ad6f, 0x045bf3e4, 0xf7ad2fd2, 0x4d9ce17a, ++ 0x7b45efcf, 0x9ffeb18e, 0xca24bc14, 0xae9b2fba, 0x42e7a0fb, 0x97e0b74a, ++ 0xcdae8bef, 0xf0a5da70, 0xcf4e3273, 0xde47b3bf, 0xde7a00cc, 0x939f2023, ++ 0x79c338d6, 0xd30afbd9, 0x29d8b623, 0x4775d3dd, 0x8ddec90e, 0xf0796f6a, ++ 0xb05f0e5b, 0x98f7f41f, 0x408582ae, 0x1b66e21c, 0x3ce191c6, 0x54fd3086, ++ 0xdab79f2f, 0x99ade249, 0x847ff77d, 0x7e97dff7, 0xc347e5a4, 0xdd971078, ++ 0xd91bc742, 0x7f799e33, 0x9705fcd0, 0x5cc7d75a, 0xebadfdce, 0xaef9c6d2, ++ 0xd2013671, 0xe2d57886, 0xfe098e6d, 0x73e83269, 0x18c905d3, 0x72e116b7, ++ 0xffeeefeb, 0xefb13943, 0x078a49fe, 0xe3dd69ef, 0x907bbed1, 0x843d733e, ++ 0x7c4d239f, 0x4ffdf60f, 0x2cbcec7c, 0x9dde42d3, 0x64c7fb08, 0x7d5d0099, ++ 0xfe8ca6f2, 0xb2a64fce, 0xde9bce78, 0xcb81203a, 0x6b1626e7, 0x271a6e45, ++ 0x18759da0, 0x7a0f1eba, 0x46f88db8, 0xe032fc20, 0x437a583e, 0xf29514f5, ++ 0xa1cdd8f5, 0x53bd482a, 0x03bf0922, 0x09124dbc, 0xd7cdade0, 0xe6938a6f, ++ 0xa498f9ef, 0xea8dab83, 0xec7ed807, 0xf5089241, 0xd112f826, 0xfcdf198c, ++ 0xd0b73be9, 0x537f8c79, 0xdeb4aaf4, 0x274e03ac, 0xc8f4faa1, 0xebf10b3a, ++ 0x848135e0, 0x34dfc0aa, 0x16efb8fe, 0xd5217798, 0x41fee077, 0x957d6b61, ++ 0x0275f21b, 0xfd040fb6, 0x9eba6e39, 0x73e7b5ad, 0x817207be, 0x026e83d6, ++ 0xa05eac75, 0xe842f041, 0xa3eb7e6b, 0xdf92b718, 0xb545e020, 0xd88121ad, ++ 0x1b21bf58, 0x1d6b77ed, 0xfb099f6d, 0xfd0f6d17, 0xe77f9c36, 0x743b9016, ++ 0x91bed89e, 0xd3e6f79d, 0x4bf02a76, 0xafec62c3, 0x70204ea8, 0x91b0a24f, ++ 0x6f854bed, 0x6f285eca, 0xf701b7de, 0xbc7419db, 0x87d834d4, 0xbef153c2, ++ 0xc1e08649, 0x838d787b, 0x45d7bfd0, 0xd2c8fe18, 0x098e4c81, 0x1eedcf3c, ++ 0xd67bef4d, 0x20f9043a, 0xe942bbdf, 0x5df9fb47, 0x059a6276, 0x9e3ceae9, ++ 0xf0a71ee3, 0x1f7853f6, 0x071071e6, 0xda523fb2, 0x6be2fb75, 0x07c8a1d6, ++ 0x61265b0b, 0x9222c07c, 0x3301f18b, 0xf37d33c7, 0x21ecebed, 0x2dbdf3f0, ++ 0xf7c20647, 0xf159d703, 0x2656e77b, 0xb5073b87, 0x64f75fa3, 0x7ee04c9d, ++ 0x889d5544, 0xa364e2f2, 0xc52ef78c, 0x78f9d927, 0x7fa656c1, 0xfd63a81c, ++ 0x0dbd049e, 0x4e50ebfc, 0xb45b05f3, 0xa72673f3, 0xdf33fb35, 0x35f5cec3, ++ 0xd7c65bb9, 0xaa1f6bdd, 0xc900a159, 0x196de59a, 0x24c5c797, 0x59b2f68c, ++ 0x79c196ee, 0xd2f81bad, 0x64e47f1c, 0x18ec18f2, 0x97f083a0, 0x6fe5d748, ++ 0x18ec04ca, 0x1c8ea3e1, 0x23da778c, 0x7c7c7fa0, 0xf383e0ab, 0xd623c2f2, ++ 0xa1dfea10, 0x06ff79bc, 0x56fbcbfb, 0x27b0a102, 0x4e540f00, 0x7f235b65, ++ 0x7efd05fa, 0x220db0fa, 0xe4dd284d, 0xf8b5dc21, 0x2c4dccd1, 0x70f3244e, ++ 0x13dc124d, 0xa1fb5325, 0x15a8281c, 0x27275f89, 0x5bbe0b4e, 0x83fb60ee, ++ 0x9a271f47, 0xc3e754a9, 0x95b9fafe, 0x937547c9, 0xe417b10c, 0xd3932b49, ++ 0xf8c03ed4, 0x8f5da2ce, 0x3a3a2926, 0x68f3da28, 0xafbf4892, 0x551671e1, ++ 0x76d2bfb0, 0xa71b0a45, 0xa9e0af68, 0xf5a38dd7, 0xecabf5a3, 0xee86ed62, ++ 0xfd5f6961, 0x70fcc117, 0x20299f9d, 0xf4fdcc2f, 0x7e8fbf1a, 0x62e3ffb2, ++ 0x95e7408d, 0x4188b6fd, 0xcd1fd9d0, 0x3f3faa18, 0xafcd52d0, 0x858ef59c, ++ 0xcbf074f8, 0xf10c53fe, 0x3cddf0e9, 0xc53df28e, 0x845a8fdf, 0xfc805d90, ++ 0x132ca531, 0xf3e01ef3, 0x2e7fee72, 0x85ceca9f, 0xaf0fd39a, 0x919fbe02, ++ 0x903d2029, 0x97e95fa0, 0x0a9afa80, 0x9905cc71, 0x6d017dac, 0xbcd8fc0f, ++ 0x9527f181, 0x91c82a13, 0x7347baf2, 0xa0837eb0, 0xf5cdff42, 0x148fa879, ++ 0xcb048b66, 0x7ea18e1b, 0x2c72d854, 0xf298f801, 0x03e80d6d, 0x1ead13e5, ++ 0x3f1ae390, 0x36fdfc6a, 0x36263b8f, 0xfb8868cf, 0x2f9801bf, 0x6f8b5f0a, ++ 0x681eb932, 0xc818fc64, 0xf6fafc66, 0x78561956, 0xfc8dfc39, 0xe333727c, ++ 0xdbc9f157, 0x759ee072, 0xcf7626c1, 0x14dd40fa, 0x93e9f405, 0x9bf70121, ++ 0xf4cdfcde, 0x577f3356, 0xfbdf6c09, 0xc6a5faae, 0xd31f1adf, 0xbc608fdf, ++ 0x70a7ca52, 0xd7cccf2f, 0x3fa6e533, 0x7be743dc, 0x3d740bd3, 0x7e53be74, ++ 0xaedddcb0, 0x9f349393, 0x897cf904, 0x726909c5, 0xf1624ca5, 0x7e79df64, ++ 0xac4bf1a6, 0x93c8ff46, 0x471638d6, 0xdd2320dd, 0x7b3f8a5f, 0xf265d9f1, ++ 0xd5f2e5e7, 0x1b53f8a5, 0xec63dc5f, 0x6f4e49e7, 0x293afee6, 0xae14c35c, ++ 0x1a7c69bf, 0x3dcf47e3, 0xe0266c77, 0xa53764a7, 0x46afa073, 0x9c830917, ++ 0x5fb84293, 0x3e8b3715, 0xc295af8c, 0xf4b8b759, 0x83e2cc7c, 0x21745e4a, ++ 0x64bf153d, 0xeda0cd0d, 0x347c778b, 0x5635e306, 0x29de3046, 0x97d71cf8, ++ 0x8063ed83, 0x16258a0f, 0x0b9664a7, 0xfd31b3df, 0x639763b9, 0xd84fac36, ++ 0x2825decc, 0xb65dba6e, 0x8625ceea, 0x971c64d8, 0xc3f3c3d6, 0xb863a520, ++ 0xd3f30a17, 0xe2d787df, 0x30b63a93, 0x22dc5139, 0xbc581da3, 0xc4275b79, ++ 0xb11f16a5, 0xb02bbfa2, 0xd9c63cf9, 0x2b71794f, 0x2d0253fa, 0xaddce1a2, ++ 0x66e03c57, 0x78856c31, 0x3c32e6b6, 0x63f9a427, 0x1e8a6f98, 0xb8a97b17, ++ 0xf71792b5, 0x105208ec, 0xacfcbc96, 0x99cbe41b, 0x806e4db6, 0x5bf7ed3b, ++ 0xc57b71e3, 0xf03d35ff, 0x677ff1ad, 0x71941fe0, 0x7a71b56e, 0x3727e2d7, ++ 0x923d43f7, 0x372b2fce, 0xb74739ca, 0xb3f5be5e, 0xbd3e20a7, 0x4fb3a5e3, ++ 0xbf4b7cc1, 0x8829e4fe, 0xed7b223b, 0x9e05dfb8, 0x7be3177b, 0xc6dde9bb, ++ 0x9e5b43fd, 0xcee8b8c5, 0xe85eadf7, 0xc9cf73ad, 0xd67710c1, 0x24cbedb9, ++ 0xdd2e5bf0, 0xbafd0d33, 0x494fb74b, 0x0bf65126, 0x0dba052d, 0xb65c465d, ++ 0x9a075f19, 0xd47c600f, 0x906f8a39, 0x9cf1dd7f, 0x3e2c654d, 0x9c71e556, ++ 0xdfe3d18d, 0x366dc57b, 0x75d372df, 0x999bf720, 0xf8c978fe, 0x1e2877cd, ++ 0xfc0cb9af, 0x817e6a35, 0x073bf8e8, 0x5a78a0ff, 0x67dfc26f, 0xfd7e8bcd, ++ 0xf7359404, 0x337e33eb, 0xd370197c, 0xd8e7ebe2, 0x80db8f7c, 0x1e7a5e6f, ++ 0x6f0165e3, 0x7fd85433, 0xf70c1b3e, 0x91c94e12, 0x6d6f78b9, 0x7103d58f, ++ 0xde7bc588, 0xdce9fe43, 0xd0fd187e, 0x77b9c784, 0x8b1fee92, 0x3af8164b, ++ 0xee2c5c1b, 0xe21fc393, 0x7e375542, 0x8c9ff1e7, 0xd0b8b58e, 0x7f41e2be, ++ 0xb67a6367, 0xd65ff716, 0xb38f01f0, 0x9097c1ec, 0xf63a780d, 0x1ab671ad, ++ 0x0e5c3c1c, 0x4737c4f7, 0x8eedbb8f, 0x02f8e783, 0xd43ec1fc, 0xf34cbf1d, ++ 0xdfa2c703, 0x45123de8, 0xb3d6741e, 0x394ee8b8, 0x2d537dfa, 0xcd90f9de, ++ 0xba1ce714, 0x4be738bc, 0xc2bbffcd, 0x7e5015e7, 0xa9c37b12, 0x72e8abe3, ++ 0xfdf383bc, 0xa65f7cdf, 0xc7df3054, 0x58f40b39, 0x014c7cd6, 0xcedbb83b, ++ 0xe0edebe6, 0xe78ef57e, 0x5d838c44, 0xe50074d3, 0x945e59b8, 0x511c3bc3, ++ 0x9f35fbe6, 0xdb0b796f, 0x725e3a27, 0x9fb49c85, 0x90bbfd8e, 0x8f1bcb9e, ++ 0x1bee1c61, 0xda565f9b, 0xb0117175, 0xf374844f, 0xdf6178ef, 0xfcdb9418, ++ 0x38f30fbd, 0xabf73b4e, 0x271f46b5, 0x30de78d0, 0x49b0494e, 0x3d2f38f1, ++ 0x77c919de, 0xa677f43b, 0x6783e98d, 0xd1e9c49a, 0xc1758bee, 0x5ce789be, ++ 0xfba52cd5, 0xe26bbe25, 0x8898ef62, 0x2fd418ee, 0x8fb2ba97, 0xaa4026c4, ++ 0xd5505c60, 0xf4471e0a, 0xe00a6f53, 0x2375cabb, 0x06aef981, 0x3cfceaf8, ++ 0x404fc7b2, 0x7253952f, 0x60afc133, 0x824a3796, 0xf8748485, 0x9e9aea5f, ++ 0x4779e2ac, 0xf3e02078, 0x1949fa68, 0xc98bfdfa, 0x8917f54f, 0xf3a649ac, ++ 0xf0504bfb, 0x92fda0ae, 0x941a3eaf, 0xbfddeaeb, 0x2fdff796, 0xe54afc1a, ++ 0xb051c8d6, 0x76abc84b, 0xf7106f8c, 0x88fdf1da, 0x5c7653c0, 0x5fed81ef, ++ 0xf5fa833c, 0x9d84adaf, 0x85eb50fb, 0x0f02abca, 0xf6e4e3eb, 0x2ffa9e2f, ++ 0x31a19fd0, 0x29e0bf1d, 0x86ec1f5a, 0x39da0746, 0x8ec52f5d, 0xc148bf01, ++ 0x04cdf7ab, 0x60e05679, 0x62f058f4, 0xf68aa872, 0xe5912277, 0x841d6c4f, ++ 0xbc9415ef, 0xc4f8c2e4, 0x9677db03, 0xf9d4bec3, 0xbec083a2, 0xd72af9d4, ++ 0xefe79ff3, 0xaacad51f, 0x88b94e3e, 0x9efeaa48, 0x59e40948, 0xc137de39, ++ 0x23e7165f, 0xc4b557f0, 0xaa12fde2, 0x39fa1aff, 0xf5ee4727, 0xfb071d22, ++ 0xe1357bb3, 0xcc0f20fe, 0xdbf2b4f5, 0x06ce4cec, 0xb39db4ac, 0x89407ea7, ++ 0x757cb3e4, 0xda4f267f, 0x3b7cfeb0, 0xf2b573b3, 0xfab2fdde, 0xeedfad7e, ++ 0x72fb587e, 0x9989befe, 0xbf78cb7e, 0x7aff9b25, 0x3bf7b465, 0xbf1fcca2, ++ 0x412044ff, 0xdb29e80b, 0x12aef8ec, 0xb887cfdc, 0x3b0a1df8, 0x87752ad7, ++ 0xdd94fdf1, 0xc6971e5c, 0x973df184, 0x501e7cfe, 0xd6c4f21f, 0xcbbe02fe, ++ 0xe04ed3b5, 0x57b29f7d, 0x77c03e5d, 0x4e2f8ed9, 0xe2132afc, 0x7f181cdf, ++ 0xbfeaf65d, 0x59941d22, 0x1f8173c3, 0x64acdb22, 0xb6f9f023, 0x5f818343, ++ 0xe0f0e43b, 0xaf396ff8, 0x1ab26b2b, 0x75f395ef, 0xbdaca99c, 0x6b51ee16, ++ 0xfb8b35f7, 0xd86f3390, 0x9fd6bdd9, 0x76d57ddb, 0x3be377e4, 0x672a6741, ++ 0x7dfdc067, 0x2db17ead, 0xb06c5cba, 0x1c9f7fcb, 0xf7baf677, 0x39f300d8, ++ 0xc092da47, 0xf54e53ef, 0xc5e7906e, 0x8206d39b, 0x5dbf609f, 0xc6aedfbb, ++ 0x5fb47ec2, 0x869ed156, 0x9ccfbf54, 0x4866f4aa, 0x337fc0c3, 0xeba24332, ++ 0x9f3faae8, 0xbc409fdf, 0x34767da2, 0xeec3b7b9, 0xb629ba40, 0xeed17d59, ++ 0x72e01e4d, 0xfd181379, 0xc078d8e3, 0xfbb8da1f, 0xe1ca10e5, 0xd62a3149, ++ 0x1176a62b, 0x3cd92f7c, 0xaef0c327, 0xf58d5487, 0x3c229f28, 0x928d488b, ++ 0xdadf93a9, 0x32cb4578, 0xf80ca433, 0x3767fd2e, 0x783d8abd, 0xd404c126, ++ 0x630e250b, 0xb86a9352, 0xb9c92087, 0x429f8036, 0x08923d72, 0xfc8d52a4, ++ 0x309a431e, 0x8b755275, 0x41557fbd, 0xe29e4e40, 0xefe0f6e7, 0x5e07b482, ++ 0x07ee51cb, 0x3c321107, 0x5019de0d, 0xf83a3d63, 0xecddd9b5, 0x82a93a9d, ++ 0xc3317930, 0x1088fa03, 0x286f93f4, 0x4e55553d, 0xa47a00cf, 0x6fdc1f3f, ++ 0xce83d343, 0xe379edcf, 0x2883d04b, 0xe277b29d, 0x5542407e, 0x7610c414, ++ 0xc9d57e8a, 0xb66fbd84, 0xdbd108ee, 0x3c719f1b, 0x943ee090, 0xf3d24e63, ++ 0x883cd08b, 0x55b79055, 0xc3675fb1, 0x43d3a239, 0x3a17a0c2, 0xa0ec249c, ++ 0x749473a9, 0xeeffcf46, 0xd1d79a4c, 0xb1a267a9, 0x5417ccdc, 0x6dc699ae, ++ 0x7ed1f842, 0xfbf5353f, 0x4fdfa9a9, 0x0d5fadbf, 0x46db014e, 0xb07fbc2f, ++ 0xc39732ba, 0xe3678d8d, 0x19f0a370, 0x11b3ef09, 0x9f978c4b, 0x635c2387, ++ 0x50ac6cf8, 0x3b35e29f, 0xf4e10d26, 0x11bdd8b3, 0x0925b788, 0xdeec04b5, ++ 0xa7db0255, 0xa9d72fe9, 0x363c476b, 0xf807c3e4, 0x4c31d938, 0xe2f76a8e, ++ 0xa3b7d77b, 0xbeabd5fe, 0x31faafbd, 0xfabbebd1, 0xfa238f9a, 0xe8fae27c, ++ 0xb511dabf, 0x972aefff, 0xef7d5fca, 0xdb6e7077, 0x143c9f2d, 0x333d46f4, ++ 0xccf4063b, 0xb75f13b8, 0x67a617e3, 0xf11a06da, 0x4df4031d, 0x98662de9, ++ 0x4e99bbf1, 0x3cafa2fa, 0x779a0ebe, 0xdc3852a6, 0xda9fc7c1, 0xefbdcec0, ++ 0x74fcca5a, 0x41f43cd4, 0xfd793bfd, 0xe8056c3b, 0xdfc6386f, 0x96abba81, ++ 0xdd7791e9, 0x74f9e22f, 0xe08e77af, 0xeedf941f, 0xc284265e, 0x6dded169, ++ 0x0f700d22, 0xdf1f1e6b, 0x9f920efc, 0xc4eb39a8, 0x3120ef68, 0x6feed4ba, ++ 0x583fdf99, 0xfbf97248, 0x7befc656, 0xf96e9eec, 0x67aa3d59, 0x4a3e0b1f, ++ 0x4ff41ee9, 0x2e70f74a, 0x3092d70f, 0xb0adc42e, 0x41b690b8, 0xc9a69e78, ++ 0xd5230bbf, 0x89afd858, 0xeefb306f, 0x8c97df61, 0x74e39357, 0x18ba5df2, ++ 0xa6077863, 0x80a6f64a, 0x5e2f937c, 0x2a6a544d, 0x5248d42b, 0x6f54e575, ++ 0xf087e645, 0x2953944d, 0xa2e40852, 0x0525c9e4, 0x8ccaf7a0, 0x4afab59e, ++ 0x7addd5c2, 0xfff4dbe6, 0xa444988a, 0xd58b25cb, 0x21e71864, 0xf80aee47, ++ 0xbdb3ba24, 0x7a6f677e, 0xeb656e08, 0xa77582ae, 0x954f5ef5, 0xbea2f5e2, ++ 0xddfba13d, 0x4fcc1b1c, 0xa9efaab4, 0x977fbf30, 0x7a5df809, 0x2a7bc7c3, ++ 0x842fcb44, 0x887c6006, 0x04633b18, 0x03bdaf8c, 0x0532aeb9, 0xf15767cf, ++ 0x555721f7, 0x83fcc48e, 0x35cefdfc, 0x1aa62a95, 0x6ade6cfc, 0x36d0b77c, ++ 0xf36ff58c, 0x5824fc70, 0xa8fc7c38, 0x2a52d95f, 0xeed0dcf0, 0x7bc308a9, ++ 0xdd206461, 0x9eda6057, 0xe29f846a, 0xa4b7e821, 0x856f31f5, 0xdae54d3c, ++ 0xc90f8851, 0x400a4153, 0x9ff872df, 0xabb43e07, 0x21ef0dfd, 0x7c86535a, ++ 0xdd87fbeb, 0xc981b4f4, 0x4f4e04d1, 0x2824f866, 0x8d507dec, 0xc3d2fa8e, ++ 0x6f5c78aa, 0xadff7f15, 0xa221de0a, 0xd2ac7970, 0x7f156987, 0xc28aa88f, ++ 0x98bde58f, 0xb33b7226, 0xcb1b32aa, 0x2efbe71f, 0x8d3007dd, 0x95f93077, ++ 0x27d8a960, 0x09e29c03, 0x04268ff3, 0xc22cc0c9, 0x97e14842, 0xe42a2412, ++ 0xd54673b5, 0x47a21f48, 0xa763bd32, 0xaa780e3e, 0xc05b2439, 0xbb2e2ecf, ++ 0x54bf70d1, 0x038bed9c, 0xf4e89bbf, 0xfe7fb00b, 0xe74cf00c, 0x279d28f7, ++ 0xe9cadbbe, 0x83a73563, 0x1e3e9cb5, 0xe9a17a00, 0x1e4e9c43, 0x7c84eba1, ++ 0x43dd9795, 0xc59d3f58, 0x5ba425cb, 0x616e3bf8, 0x8b478fa2, 0x851136f3, ++ 0x687513ae, 0xa77c5315, 0x22b11c8f, 0x114638fd, 0x47e5089f, 0x3bd88796, ++ 0xb0a9b99a, 0xef69c6ef, 0xe3544e66, 0xdac5e0e6, 0xb3dfc4b0, 0xd2dd9913, ++ 0xca7df516, 0x1b7eef2a, 0xcd7dffd8, 0xa5f5e1c7, 0x39e3a6ad, 0xafa85d6a, ++ 0xcee7f3f7, 0xcef34459, 0x13bfaa5a, 0xea746728, 0xd02ef3a4, 0x0fa387d1, ++ 0xe39d41ff, 0xcf81af86, 0x8b0d81bf, 0xb5e7f5e2, 0x5f00ed43, 0xfc156b0a, ++ 0xb9c98f24, 0x1e0f20a9, 0xefee8b8b, 0xf4c31d39, 0xd5e6776c, 0x91aefa06, ++ 0x33ced87d, 0x0f81ac71, 0x8a1cb86a, 0xf0c13a9f, 0xff3b935d, 0xc87bfbc1, ++ 0xd0778fe1, 0x9c5d24f9, 0x709c7c8a, 0x54397473, 0x78412b25, 0x346aa05f, ++ 0x3cc17b93, 0xbd67e985, 0x7f410ae4, 0x88ff05fb, 0xd167e08d, 0x61256be8, ++ 0x98482c72, 0xebada2de, 0x28ef4097, 0xf7483c6f, 0x680f80ab, 0x20a61c5e, ++ 0x65dd24dd, 0x0d773b41, 0x3907b3e7, 0x7ce7ad7f, 0xd5f030f5, 0xd6c77808, ++ 0x39cfe98b, 0xff00d53f, 0x48e7d4d1, 0xfe0c7e63, 0x2fa6913e, 0xc58db4af, ++ 0x9caae8f7, 0xd24b9416, 0x1390d6fb, 0xe37dcff4, 0x105fe03d, 0xbf1e995d, ++ 0x6d33ca0b, 0x8867383e, 0xbd00f4cb, 0x785aee7c, 0x51c5b7c5, 0x5df111d2, ++ 0x7e664954, 0x2e424f2f, 0x9e1470f9, 0x68fde082, 0x013373d9, 0x09e3e83f, ++ 0xf3807615, 0x87660e35, 0x2165e6d5, 0xa63e29dc, 0x31e77439, 0xec6fb3c9, ++ 0xba0c4f7e, 0x7b8fbc7f, 0x5c1cb3d6, 0x24181e2f, 0xa1f274c3, 0x4757bf96, ++ 0xa91920d4, 0x872b1393, 0x1ff010e7, 0x7d0f96f5, 0x4c4dcbc8, 0x7c09565e, ++ 0x5de1321f, 0x7934f7db, 0xfbde0129, 0xeae79ef5, 0xee1ba62b, 0xde5cc987, ++ 0x3b15eb9b, 0x86b63d98, 0xa17e2378, 0x53853977, 0x2f6743b1, 0x76370929, ++ 0x8c3fc3db, 0x5cb30eb2, 0x25fb053c, 0x8fc91ac8, 0x542c9aef, 0x83c7c7d4, ++ 0x8b2df9bc, 0x9f4be9af, 0xb82bc6d0, 0x417a8858, 0xdc6cc5fe, 0xa76b0a97, ++ 0xf010ff23, 0xb0ecebf6, 0x713f7593, 0xd64f5e03, 0x3ad7f3f2, 0x2f710439, ++ 0xf7de36fb, 0xcf0a1cf0, 0x78894f85, 0x00f70afe, 0x04fc5d44, 0x0f5154c9, ++ 0x3b75ded4, 0xadc7ba19, 0xffcf273f, 0xfa07dd85, 0x98745f65, 0x3fdd175f, ++ 0x04ff0550, 0x477896bd, 0xf54ade82, 0xf4184887, 0xf1db9f8b, 0x1f2d0bbd, ++ 0xfa88e8dc, 0x63a9558e, 0xf70023da, 0x71ef8752, 0x1e338948, 0xe6fa03cf, ++ 0x09ee3607, 0x39c2c9f0, 0x8e3c13dc, 0x967dc297, 0xcec73fc1, 0x7f704ee1, ++ 0x51f5b10b, 0xd5cbc31e, 0x2cddca3e, 0xa278865e, 0x7ecdff97, 0xecbd518a, ++ 0xa7c05d80, 0xd767b565, 0x8c5f8fbc, 0xdcd3e6fe, 0xd1b85d8e, 0x45195a11, ++ 0xefc858bf, 0xe7e42e39, 0x9d7d1a29, 0x18e3d6ee, 0x9dc3765d, 0x97d219d2, ++ 0x67858e89, 0x7edd2347, 0xff465072, 0x75ecf0a0, 0xf94c9ef8, 0xa5103a45, ++ 0xfbd152cb, 0x9191c408, 0xeba445b7, 0xc38d0e7b, 0xd30eb473, 0xb967963b, ++ 0xf9a5a1be, 0x7a0d8b17, 0x81687e6f, 0xfe417a02, 0x77a472c5, 0x7b84d788, ++ 0x7f9c84f5, 0xe9c4927d, 0x3fb40276, 0xed256d37, 0xf19da0b7, 0x2c189907, ++ 0xbd673f47, 0x30fe0bc3, 0x759c7d33, 0x47bf06a8, 0xf6297b41, 0x92419c4f, ++ 0x58378ba0, 0x2f6bdfc8, 0x6ddec8b8, 0x49209e24, 0xf2e17e01, 0x8dee87ac, ++ 0x5876f6ef, 0xd7983d18, 0xe75f15fb, 0x9debdd57, 0x7f7ac7d0, 0xf5cbd6c0, ++ 0x6cf6828c, 0x357ebad3, 0x7abada3e, 0xdb1133d6, 0x9677f297, 0xef0c2d4b, ++ 0x2770f95a, 0x4f4b5f1b, 0x1b86ce54, 0xbf88a442, 0xba1f9997, 0xa1f78147, ++ 0xe2e2ebf2, 0x0b3add05, 0xc434ef6a, 0xe6d7e4c5, 0x0560fbe1, 0x7cca7975, ++ 0x8dd4fedd, 0x0df3a0a7, 0xaf869e3d, 0x9e00e6b7, 0x71b91cea, 0x67cfe04e, ++ 0x857deeca, 0x6f0cbf40, 0x98e094a7, 0xf75b940a, 0xa3dda3b8, 0xe134ee19, ++ 0x6de396ad, 0xd28c9058, 0x5f0d31c9, 0x3627f6e6, 0xe70bdc95, 0xb03627eb, ++ 0x96fa50d7, 0x69f1d163, 0xc38fa386, 0xc70dd7cf, 0x75b71891, 0xcf7e3869, ++ 0x27d59f10, 0x35fe391c, 0xa9df6938, 0x89de375e, 0x9ef612e3, 0x65f66d60, ++ 0x7c67afc1, 0x14a71f46, 0x200d88df, 0x061ca91f, 0xccfd3d3e, 0xdbe8c6cf, ++ 0x4d263a95, 0xf5487183, 0xbdef9de5, 0x84cff0e2, 0xdec9c1fa, 0x73ca2a83, ++ 0xd7455bd1, 0x44fb145d, 0x6b571867, 0x57571fdc, 0xbf81d7aa, 0xd729da89, ++ 0xe657df81, 0x7d011afa, 0x4fbd8d2d, 0xacdded1f, 0x77a64ec5, 0x40acaeac, ++ 0x05b1317f, 0x92fc0789, 0x3925f184, 0x3bfe8195, 0x33d469c9, 0x01efd914, ++ 0xefc2a17f, 0x7f92cb61, 0xd8265a5d, 0x41e909d7, 0x4e037c1d, 0x4fad1fa6, ++ 0x3f01efd9, 0x0ff695b0, 0x40db037e, 0xdfc182e9, 0xb0b49af0, 0xed3ba51f, ++ 0xd218d459, 0xf40413e4, 0xf9305cbf, 0xe6182e5f, 0x6de74091, 0x708d27d8, ++ 0x3c6e6c91, 0xf70891b7, 0xd07871bb, 0xd787282f, 0xd2bc3972, 0x6dfdc6e1, ++ 0xb41615cd, 0x3fb86a4f, 0xc7e097ef, 0xe848b843, 0x21b0859f, 0xb2c4afa8, ++ 0xefc1d875, 0x10dd822b, 0x5e0bbcc6, 0x09f111d2, 0x71f20132, 0xdf201544, ++ 0x80d7848f, 0xa935dc1e, 0xeef85efd, 0x001ffbb5, 0xb53cfdbe, 0x7e00a8ed, ++ 0x95ff5cdc, 0x315ae700, 0xfad2ae98, 0xe92316bf, 0x2d306f50, 0xd2cf123a, ++ 0xdb8e202b, 0x621f3baf, 0xe4f694ef, 0x2bf9dec5, 0xf3a64996, 0xd4aeaf92, ++ 0xeedcff97, 0x547985ab, 0x3dbbd9d9, 0x28091f09, 0xfdbaaae7, 0xef78b9f4, ++ 0x8b2765e8, 0x00ba41db, 0xf4c83aba, 0x1a920b80, 0xbffe8f1b, 0x19af1991, ++ 0xe435e1e6, 0x35576e25, 0x74953a50, 0x24c312e7, 0x68e8059f, 0xaefd3578, ++ 0xfd14679f, 0xcf89de2d, 0x0f3d46f4, 0xc747e6d1, 0x2f157a45, 0xc67db0e6, ++ 0x05bb0f44, 0x9160ff36, 0x243fd995, 0xe75e0228, 0xad278468, 0xa238f962, ++ 0x78eed0fd, 0x93d3f35f, 0x61ef2c55, 0x767cc0b9, 0xcf9e682e, 0x6db5d69c, ++ 0xd39f1fe0, 0xce00ba9a, 0x5e14e689, 0xbba431f9, 0x077ec8e5, 0xb09f89c8, ++ 0x78ef4677, 0xb61935f7, 0x6cefedd0, 0x6fdcfbc4, 0x4b9c7e73, 0xdfe03222, ++ 0xf30a3c4f, 0x7bd887f3, 0xf3cbc41e, 0xcfd8324d, 0xb7438577, 0xeee688fd, ++ 0x23f42d7e, 0x1ee65f50, 0x680ebc8c, 0x727937f3, 0xb5ae97d0, 0xc1bef16b, ++ 0x375dacf2, 0xeffcec1c, 0x5c364890, 0x6dbacf57, 0x9d6d0708, 0xa3e226b4, ++ 0xddfc4e1b, 0xdd2e0d24, 0x79dc76eb, 0xfb2ff823, 0x6c736f92, 0x71663fa3, ++ 0x665e6cc5, 0x450a7d38, 0xc1fe3e54, 0xf20b3be9, 0xafa775ef, 0x5b52d203, ++ 0x0434b064, 0xf90226f9, 0x457fd172, 0xb9c38512, 0x132bfe41, 0xfd6d1e01, ++ 0x3d8f4b2e, 0xe0f2676a, 0x3f669a68, 0x6be8f7f0, 0x8f365e99, 0xed9adbd3, ++ 0x3efddf27, 0x621d13c4, 0x899540ef, 0xa1f74dea, 0xd1244e3f, 0x3d2d6af4, ++ 0x9b5fedca, 0x6ddfc2cb, 0x279ceb65, 0x6bcf7831, 0xa4bde076, 0xc344cb79, ++ 0x96f3d33b, 0x223f78b1, 0xd5b98db5, 0xe2aef7a0, 0x1fbbdd74, 0xfdcdcfb0, ++ 0x1936582c, 0x8a1db6ed, 0xebda1267, 0x5b3a314f, 0x4227d530, 0x7584f49c, ++ 0xc643fa02, 0xda5b571f, 0x28417e69, 0xbaec0bce, 0x0c92f960, 0xbca1ef78, ++ 0x92ebf98d, 0x3fe9c5c5, 0xfb63e9a5, 0xf90bfed9, 0xa72700c5, 0xfcea754f, ++ 0x45721ddb, 0xf9e807ba, 0xe40fa76e, 0xbeadde41, 0x9a9f01f7, 0x11e9aebd, ++ 0x0cbee93b, 0x77796f71, 0x1f40d9a9, 0x1f764d79, 0xc52236a6, 0x2796b950, ++ 0xc9a41b11, 0x90ec910a, 0xa41b10c6, 0x7bd92b59, 0xb3b5f9de, 0x67773f70, ++ 0xaef02ae7, 0xb3eb5e6f, 0x02fb419f, 0xd04fbc29, 0xeb5e53d1, 0xfef12fa1, ++ 0xe3172f90, 0x59b7bf1a, 0xa351d831, 0x6bf98c9b, 0xf4f98c5a, 0x719f31b0, ++ 0x0f5f98d0, 0x6f4e8eea, 0x9d87bfda, 0x659c97e7, 0xa15f21f7, 0x1e019030, ++ 0x1f28ad5b, 0x66b494a7, 0xd9f0f9c1, 0x28165c17, 0x6657fddf, 0xd8b64647, ++ 0x7db77df1, 0x31218c7f, 0xa2f8a710, 0x9f94237d, 0x02ca698d, 0x8fad193f, ++ 0x77741e71, 0xd076011d, 0x7a35ab8e, 0xc83c610d, 0x3c59af8e, 0x358b647f, ++ 0x67cee704, 0x02fb3d77, 0x2dd9e7d0, 0x7a3f5003, 0xa05a0845, 0x0c03e0df, ++ 0xdc6213ff, 0xb2553906, 0xce5f68d9, 0xabbd3171, 0x0f32b4eb, 0xd6571bfc, ++ 0x557dd71a, 0x73cf98c8, 0x9f353931, 0xc1a7bee8, 0x26baba79, 0xa7d9f605, ++ 0x927bd449, 0x9e2f9c85, 0xe8d14e7b, 0xb0efe456, 0xe7a93511, 0x9eeed77e, ++ 0x03a5ae73, 0x00951d28, 0x7cf4862c, 0xab8d312f, 0x62e19ff5, 0x3f0240fb, ++ 0x25bc885f, 0x54ce7c22, 0xc3ce1a16, 0x4ad8f5bb, 0x61d4ca6f, 0x76b13d3a, ++ 0xea1e525f, 0xe692fb8f, 0x2db7edeb, 0x84ee9207, 0x12cd9e78, 0xd2ab9dfe, ++ 0x3c3ccf39, 0x8bbe0121, 0x285f304d, 0xa3b21d07, 0xd43775e9, 0x58ea7aa3, ++ 0x414c7c7d, 0xa994b8ed, 0xaefd3e3a, 0x3efdd974, 0x67c187b7, 0x2dee7667, ++ 0x2ef8a23f, 0x50bd13a9, 0xb6e9a4ad, 0x700d197f, 0x3ef193af, 0x1936e96f, ++ 0xd40f8bdf, 0x8afe8b5f, 0x39c3c692, 0x86e12ef8, 0x2bcc2f3c, 0xe2b9224b, ++ 0xdc517458, 0xd6a9e90a, 0x5f9ef8ed, 0x146b9fc9, 0x1af98549, 0x1bd283e9, ++ 0x94d521f2, 0x1e066eb2, 0x38c0adf0, 0x19bbed5c, 0x632145ae, 0x5ebe337b, ++ 0x7f43f4e6, 0x3778f523, 0x2337ebd7, 0xa62f7f88, 0x4f951974, 0xf4a43b3a, ++ 0x01c63578, 0xe741c79a, 0x1dbcee94, 0xf91539f6, 0x7bf7ced1, 0x78b2d822, ++ 0x9650ec9c, 0x810577c7, 0x57fd60be, 0xdc2aa993, 0x4c99bce3, 0x2115f487, ++ 0x3228b0fc, 0xc7ff46be, 0x75f20756, 0x99fda787, 0x343d015f, 0x97f3c68e, ++ 0x6b5efcfe, 0xf7c61a87, 0x33bfb518, 0xf961e1d1, 0xc63b56e2, 0xa73d9c91, ++ 0x015bdca0, 0xff506bf1, 0x42c5bb05, 0xdbb3aef5, 0x78864dfa, 0xf6268ec8, ++ 0xa699ef4e, 0x6f95937e, 0xfccd47d9, 0xc76fedab, 0x1f749fe0, 0xfdf2e23c, ++ 0x8df60b87, 0x345e2c55, 0x7a455fb9, 0x693c1445, 0x8a9412ed, 0x2233b074, ++ 0x1bbd3b77, 0x26945e99, 0x05381fa1, 0xee3cfeed, 0x362cf8e7, 0x75fa1db7, ++ 0xfa3ebad1, 0x7141fc7f, 0x47d7d023, 0xcf5ef7a2, 0xc1739ed0, 0xbc7e9985, ++ 0x107f8b37, 0x40bf8e82, 0xea896122, 0x7f600bb1, 0x94798318, 0x04ea0b83, ++ 0xb85a9f8c, 0x781eb8de, 0xafbf5637, 0x265fc215, 0x30f10a1b, 0xd616984d, ++ 0x608bcb19, 0x9c63701f, 0x1409c60b, 0x09cb1837, 0xa77fa309, 0x6b1bf1b4, ++ 0x467db834, 0xfef9f5b4, 0x1f9065d3, 0x8f8fca32, 0x5f5c5cc5, 0x34a55809, ++ 0xb3ef83bd, 0x29d9e581, 0xb5da690b, 0xc2ca426c, 0xcbdfb80c, 0x156423f6, ++ 0xfef647e4, 0x1254c954, 0x03dec41e, 0x95cfb021, 0xd1e10ab4, 0xa091b790, ++ 0x0efb2c7b, 0xbac022ef, 0xb463f7f5, 0xf57ac375, 0x0c3bc9df, 0x2afddaaf, ++ 0xbcbeaf58, 0xb4a1c394, 0x33f06ad1, 0x8214684c, 0xdee06bae, 0x2bb63b46, ++ 0x6ac6fe6f, 0xa3ef97e8, 0x7625ff74, 0x8509af8a, 0xe62c22f5, 0x1c796eb1, ++ 0xfc5a2aba, 0xbf0e51fd, 0x4fcb6ec7, 0x047d7e05, 0x1cfec8f4, 0x3c84d9c0, ++ 0x02734208, 0x8e8d8443, 0x9dd19317, 0x95acf2c7, 0x773dff2c, 0x03b5f5e2, ++ 0xfb25dda9, 0x81645cf1, 0xdc06fb98, 0xf1ef5aeb, 0xe3a6e35f, 0x06f8b02c, ++ 0xbeb7c84b, 0x5bafe811, 0xf8f0e0c6, 0x2aab8ad8, 0x1ab7d8a2, 0x34297f7e, ++ 0x706579e1, 0x5d0fdb17, 0xef591199, 0xcdc1bd8f, 0xfeec51e4, 0x10cfbc76, ++ 0x3de02ed9, 0x31c20dca, 0xe1b867bc, 0xfd809506, 0x04f1429d, 0x408372f2, ++ 0x5ffbc156, 0x16b3cd99, 0xce780ebf, 0x39c2f18c, 0x24f35968, 0xeb89ccb1, ++ 0xa3937a67, 0x27ce1ea2, 0x1c8de792, 0xd74e740b, 0xfa66ef3d, 0x8ab726fd, ++ 0x193aa5e3, 0x065653de, 0x828c96d3, 0xbf1773f1, 0x3a387c0e, 0x26dfef06, ++ 0xe2b95853, 0xfa075d31, 0xdf490a50, 0x653d7207, 0x7c163a86, 0xd9b98fc1, ++ 0x71168938, 0xd7d02cde, 0xfc7cb2c6, 0x236f82fd, 0x38a3e112, 0x4c95b24e, ++ 0x77c2f987, 0xe06cefd0, 0xf0ea700f, 0x1d22a53d, 0xca1e4fc6, 0x8c2504d2, ++ 0x6a6f5171, 0xf1656f78, 0x043d4b49, 0x2fd2f4e5, 0x3d832527, 0x350766f6, ++ 0x7afca98c, 0x2f66a073, 0x4fa89d86, 0xeac91b0f, 0x697a7d73, 0x4ffb8b3a, ++ 0x31e9ac18, 0xec975eac, 0xb900cd8b, 0xd5e9987a, 0xe87d3a9f, 0x8956bd47, ++ 0x9cbc771e, 0x317029e3, 0xe7748486, 0x9fd98113, 0xb817bea3, 0xdd2126e8, ++ 0xd9ef013e, 0x4b57e3e9, 0xbbe3f70b, 0x0da465e2, 0x9acba0e3, 0xd7b6f18c, ++ 0x571f44c6, 0x45c0f3a3, 0x43f6090b, 0x76081e32, 0x64429bd4, 0xbc04a2cd, ++ 0xd9fe880f, 0x048545c0, 0x2e07e375, 0xddf31bc6, 0x7ec24cf3, 0x6311ea7a, ++ 0xb02f96bd, 0x776ec91e, 0x9e9d38c3, 0x0247dc76, 0xa76c2517, 0x215d37ed, ++ 0xfca6504b, 0xf2b2a9dc, 0xa4be7e2e, 0xebfad7d5, 0xfbf0ad9c, 0xe19dec3e, ++ 0x782a4a8e, 0x689e5c28, 0xd27e8f3d, 0x087dd6d2, 0x7a1e8d17, 0x4120e3e0, ++ 0xaa927c1d, 0xca16c2da, 0xfc3e2fdb, 0xaea3b5e3, 0xcfd8a8a2, 0x7b3838f9, ++ 0x40d28fad, 0xaea3bc12, 0x66476be3, 0x98a39f37, 0x7222cc79, 0xb59ce67f, ++ 0xf2ea0753, 0xfb777ebc, 0x43d71de0, 0xd628e679, 0x77c3d77e, 0x3a2566fe, ++ 0x5c79aa1f, 0xae706473, 0x99b7974b, 0x1f9a4ef2, 0x4c7bcbad, 0xf2a609e5, ++ 0x207e5314, 0x0ae1dfab, 0x84bd160f, 0xbcf0f6bc, 0xe5efe1eb, 0xe786a475, ++ 0xeb05cbc2, 0xc3d7f9c5, 0xcb2cc7df, 0xb1ef7f64, 0x0af055bc, 0xde59f93a, ++ 0xaedcbe7d, 0x7005182c, 0xe4037b68, 0xe08b6940, 0xd9dcfd01, 0x798c2db4, ++ 0xdaeaa768, 0xb03b3135, 0xb618e9b4, 0x91ffb3eb, 0x07e3e416, 0xf5887e47, ++ 0x422e752e, 0x5eff1866, 0x24e75f4c, 0x9fff04c7, 0xef3d89dc, 0x7b6c771b, ++ 0xf5efe7af, 0xa99defd1, 0x472803be, 0x035ff74d, 0x0f671f30, 0x7c70689f, ++ 0x7c05e470, 0xd183f1ef, 0x3a82efad, 0x7e7a58e0, 0x7f97e805, 0x0e393b2e, ++ 0x33782df4, 0x5f8df612, 0x60aba10a, 0xf8827a3f, 0xef7182af, 0x0fbe1b2e, ++ 0x2a3f209e, 0xef093fb7, 0xb91e3b01, 0xce897aef, 0x7daba8ef, 0x2449fc10, ++ 0x961aec57, 0x97c76c4f, 0xd7638a24, 0xf6a0fcb2, 0x8f9a1641, 0xf88edd8b, ++ 0xfdbc3a3a, 0x8f8fc849, 0x47e5927d, 0x3d120fb7, 0x753c4a60, 0x7f5a54fd, ++ 0xbf3a2793, 0x3d99625b, 0x31cfcda4, 0xd857f7cc, 0xdb29487f, 0xa57ae06f, ++ 0xb9d3ca8d, 0x6eb667c5, 0xfb98f0a2, 0x73940e6f, 0xb96e3a9b, 0xc1c9e991, ++ 0x4a9f885c, 0xfdc6f0e6, 0x84bae510, 0xec2a44fa, 0xf83df181, 0x536e0d74, ++ 0xbab8bf71, 0x0de81b62, 0xe14773c9, 0xe5d8717e, 0xec4d892b, 0x9a44a549, ++ 0xac5839c2, 0xd16dc987, 0xc9f5e782, 0x8f50b9f7, 0x0fbf847a, 0xe90ef94e, ++ 0x92f1c9c3, 0x66e4cb1c, 0xbfb32c72, 0x61a6ba2e, 0x7c147f3f, 0xa4226c1b, ++ 0xbf476824, 0x2bea0c58, 0xb953d677, 0x0d7ae542, 0xa3cd779f, 0xe1bfa157, ++ 0x8ef7f04e, 0xd4beef82, 0xfa3d51f8, 0xcd3a4d7f, 0xb3ec7b3b, 0x54be599a, ++ 0x4d6b79fd, 0xe4d72b3d, 0x6b1a4d56, 0xc957edaf, 0xe49c6c55, 0x08daae47, ++ 0x044870eb, 0xcd1756e3, 0x0571b11e, 0xe337ffee, 0x97cf897c, 0xf1f4f60a, ++ 0xd01621a2, 0x8cfc354b, 0x874be619, 0x39f83bf2, 0x6ea7868d, 0xd996397d, ++ 0xaa440b85, 0xe4be803f, 0x547f63f1, 0x0ec3189f, 0x513e99db, 0xf18cd742, ++ 0x44be1cd0, 0xdf071f6a, 0xe9c10fff, 0x7f4740c7, 0xd6fe9c37, 0x1c935873, ++ 0x18a6f2a2, 0xecb653e6, 0x0fdef1a4, 0x852ffb87, 0xa99c9cb0, 0x7e858f7b, ++ 0xd333fb07, 0xab1c5fed, 0xbdccc3f3, 0x4ef50caf, 0x7f8e3d6d, 0xfe1d39dd, ++ 0x3f99a6a6, 0xd1e17acd, 0xa3d6da3f, 0x4269503f, 0x46f47c79, 0x8e4ff782, ++ 0x34b0f7f2, 0xdfeb36bd, 0xfb04de4a, 0x22b1cfed, 0xc101e7c2, 0x78f00a97, ++ 0xdc03d280, 0x62ce0f5f, 0x7eda34f1, 0xda17135c, 0x70f40f90, 0x973c28db, ++ 0xae2c22ef, 0x81ccb826, 0xdae26af5, 0x19af3ed1, 0x4ce87aaf, 0x8f103e80, ++ 0xfa0a3991, 0x19d26a85, 0x5d14d59d, 0x2849f78d, 0xfdb104bd, 0x3577461c, ++ 0x17da08b3, 0x90527335, 0x6424ecde, 0x45f4f987, 0xcc55493f, 0xdf24468f, ++ 0x7ab9fd18, 0x8e07970b, 0xefedf6cc, 0xdebb1e81, 0xa02c7a8e, 0xaa4bcf12, ++ 0x94be7193, 0x2780420e, 0xbf6dd9a2, 0x883d0d48, 0xfd17a276, 0xbe5d6b01, ++ 0x4fff9c3c, 0xbfcc2a1d, 0xd9d64ece, 0x43f982c6, 0xe49ca156, 0x8fd521f3, ++ 0xe6857c63, 0xe14bfd67, 0x1fe81705, 0xfb76c62f, 0x9f607c03, 0x7cac27cf, ++ 0x638efdfe, 0xbfcd4f60, 0x4bafbd9f, 0x19f34dd6, 0x5ce83fcf, 0xce4fc093, ++ 0x1711b57f, 0xda1f8dd0, 0xffffa1b9, 0x23fdc174, 0x3eecfdff, 0xf6d2092f, ++ 0xefda7b23, 0x573efce7, 0x9527f364, 0xfbda350e, 0x7ef9fba8, 0xd3efe740, ++ 0x638da78f, 0x91da97ee, 0x145e0007, 0x67b861ee, 0xfb29f915, 0xf9e60e7b, ++ 0x87912826, 0x6e7cb4ec, 0x7f0718a5, 0xccbfde07, 0xe6d5eb85, 0x72392f3b, ++ 0x4c29fa1d, 0x94709ffd, 0x5c3f8167, 0xfdc87fb3, 0xe10ffb3a, 0x45e4f4a2, ++ 0x82208778, 0xefaf5476, 0xdb366edc, 0x6d7c849d, 0xbeebd7d5, 0xa60aa0b7, ++ 0x52ba73f9, 0xe6f00905, 0x8af9e7e7, 0xf20b9912, 0x0d6f3cca, 0x9cb9e79e, ++ 0x0cc2e8d1, 0xc07df3ef, 0x1f69413b, 0x97fafd04, 0xe64e1159, 0xf4fdb5fe, ++ 0x9fe53b71, 0x129f8878, 0x976b5e90, 0xec7f703b, 0xc19e47b2, 0xaf7b9d7b, ++ 0x16777c47, 0xdf70a8c5, 0xb6aa09e0, 0x5ec879e3, 0x35d21e76, 0xf0047da2, ++ 0xb35d2753, 0xf3a7e28f, 0x283eb12d, 0xfaa09368, 0x46e25bd1, 0x5dceffa0, ++ 0xff3f6037, 0x61bcd60d, 0x008000d0, 0x00000000, 0x00088b1f, 0x00000000, ++ 0x7dc5ff00, 0xd554780b, 0x733ef0b5, 0xcc923cce, 0x24c93324, 0x124fbc99, ++ 0x4e220108, 0xa07c0422, 0x35180843, 0xe2d101da, 0xf090e2e3, 0x44c93048, ++ 0xb578bd6d, 0x4844033f, 0x44683110, 0x8a1388a0, 0x06f6ad8a, 0xc134188b, ++ 0xb5b15141, 0xedaf42fd, 0x17e7ed15, 0x4ae3e221, 0x6c520232, 0xad6bfeb5, ++ 0x67324fbd, 0xbd2d2892, 0x3d3ef9bd, 0xd9f7b3ec, 0x5ed6b58f, 0x7fa7bdef, ++ 0x72ca9c65, 0xc633f319, 0x0cf0894c, 0x8b0575fc, 0xa198ec67, 0xa1f2c4c7, ++ 0x9e6669dc, 0xdf7f4642, 0xf0fd7fc2, 0x63094d5f, 0xc0434103, 0xb13c2178, ++ 0x81633262, 0x93e0b8ce, 0xd5f058b9, 0x0d632732, 0x75b2c4b7, 0x920d3c12, ++ 0x0df500c7, 0x570426cb, 0x858dd44b, 0xc75630a5, 0xd67a84bb, 0xe97f4124, ++ 0x28ec6b32, 0x82d1f2c2, 0x9d788b3b, 0xc76eed02, 0xeed4a87f, 0xabf304a0, ++ 0x91efacb3, 0x0ecc7e61, 0x32fd41ff, 0xbf7187ac, 0xa02bbfc5, 0xf9fffadd, ++ 0xb0dfe706, 0x196de607, 0xb3dd779a, 0x632c75fa, 0x9a7aa1a6, 0x64b18077, ++ 0xae60e2c6, 0xce567f38, 0xbe616382, 0xab8e5136, 0x08ca09e8, 0xec65e5a7, ++ 0x7d341258, 0xd7b677b5, 0xac1df58a, 0x4ffe9e0a, 0xf3082798, 0xfdaba4be, ++ 0xef680cb5, 0xc2c9e8a8, 0xdf97fae5, 0x45df5179, 0xb1907fd8, 0xbcf34329, ++ 0xcca36bb8, 0x7d1e34ac, 0xecf15307, 0xf1bb52b6, 0x7c882f73, 0x92efa2ae, ++ 0x386df20d, 0x4abe2f5e, 0xd278e043, 0x53671824, 0x1d619e6d, 0x814e2bcc, ++ 0xc5d73057, 0xac76e3ad, 0x0a7b3824, 0x7b18dae6, 0xe6dd9e34, 0x4bba7825, ++ 0x7adfd0bd, 0x3b6cd97b, 0x28ea97f4, 0xe64f619b, 0xb86d78e3, 0xc5d4587c, ++ 0x7e8bf343, 0xdad1f06a, 0x1637e6a5, 0x6f475a37, 0xb87134e7, 0x0424b785, ++ 0x147ce077, 0x7e4bca89, 0x475f6c63, 0x6e8853f3, 0x373c7cee, 0x61aff388, ++ 0x756f44ad, 0x3262682c, 0x40b0b3b4, 0x12c5d03c, 0xcf009668, 0x4ccd9ba5, ++ 0x6d5fc08d, 0x53ae5f50, 0x78a40742, 0xfa1e97a4, 0x515df6fe, 0x642ce5f5, ++ 0x0b7afa83, 0xb3e1c50b, 0xc0df5f43, 0xbfde82c2, 0x67be4735, 0xb7bd7c6d, ++ 0xca3bbc09, 0xd60fb283, 0xb18625bd, 0xd06c4498, 0xe4b9f84a, 0x67c276be, ++ 0xf7278942, 0xf857587e, 0x077ba32d, 0x0247edd0, 0xbe7c1a5f, 0x06bb284c, ++ 0x1b2b1ee1, 0x95e1fd68, 0xb01dc171, 0xab033efe, 0xe43ffc41, 0x85cdb760, ++ 0xd50aff67, 0x810c6635, 0x41d21269, 0xbdd79c34, 0x74835314, 0xa0ddaf73, ++ 0xddb72ba3, 0x35eff048, 0x4fdc1ab1, 0xbfa0aba5, 0x71fd88a2, 0xdf87d5a3, ++ 0xf44bb2ad, 0x7affe21d, 0x4d5b3fc4, 0xa47b61df, 0xf88bd8b3, 0x05aefb53, ++ 0x6cbd13db, 0xef854fe4, 0xb1b54dfb, 0x21bf88ed, 0xa230347a, 0x09af22c7, ++ 0xe092f4e1, 0x7c692f13, 0xf9ccc9a2, 0xb05f6284, 0x7d2fca1c, 0x075ee452, ++ 0x9e856270, 0x751f4885, 0x48aac59f, 0xfb3e871f, 0x83bf03f9, 0x989f93fa, ++ 0x2fd43354, 0x3c019a42, 0xfe7124bc, 0x9629b812, 0xeaef093d, 0xb8e31b60, ++ 0x05c77b75, 0x5eefd003, 0x7efd5328, 0x17538d1b, 0x18b2dbef, 0x3e7ba9fa, ++ 0xc9940dd9, 0x9f06365e, 0xbbeb0a79, 0x424fdc63, 0x9cb175bf, 0xca5eeb4e, ++ 0x89efefa0, 0xf88d3df1, 0x7f073749, 0x03e44bf1, 0x4fdd98af, 0x0b24e3c2, ++ 0x9ff9c12d, 0xb09188ec, 0x575c51dd, 0x4ea13c02, 0xc17575c2, 0xa5df7c78, ++ 0x8eef862d, 0x75f2a4b5, 0x7b1d3809, 0xf9d12270, 0x2f1f2326, 0xf6a24fb0, ++ 0xd9de8d47, 0xfa3e5069, 0x257bb142, 0x4d780d54, 0xa7d01321, 0xdfdba1ff, ++ 0xab189366, 0x11dba836, 0x1c7f6c4e, 0x87c357cd, 0x4ad2c37f, 0xbb2ff7ac, ++ 0x77e43aef, 0xe45beda3, 0x0f822cdf, 0x3670b3f6, 0x35ad8fee, 0x18211d79, ++ 0xbc6bbfb7, 0x175aa65b, 0xc3e81f20, 0x19f6dbce, 0xddc35c39, 0xe7bfda46, ++ 0x57ae3fda, 0x04f2e529, 0x9f03f1c7, 0x227eda65, 0x96511b3e, 0xfe032a47, ++ 0x97febd60, 0xd15e0952, 0x7cdb97f5, 0x357f9047, 0x0fe7fc3c, 0xc37c1396, ++ 0x6b58e7c4, 0x3eb3ed32, 0xd20167a3, 0x643ca3ad, 0xfba08aaa, 0x409f702f, ++ 0x97336a93, 0x4c858c33, 0x7d745df8, 0xee9e9969, 0xec5867b5, 0xe70f5b17, ++ 0x0debc3d7, 0x6f5d3f62, 0x0974b946, 0x41cb329f, 0xfec560b9, 0x92ffea55, ++ 0x6aa6424f, 0x17dce728, 0x4f112d32, 0xef0027dc, 0xddd60590, 0xfc46c5b7, ++ 0xfd80c100, 0x48c6992c, 0x59912dfe, 0xdf04a593, 0x80bd9dab, 0x382fe397, ++ 0x0d7d7d38, 0x2f780150, 0x999da264, 0x2f805b35, 0x8524d8bd, 0xe16ed02c, ++ 0x988ef366, 0x1ed7dc5c, 0x7cf886d9, 0xb4be225c, 0xc14669b0, 0xdb2f2816, ++ 0x3fe10173, 0xcba71a7e, 0xc9074165, 0xbf044bb9, 0x4d0736ab, 0x5f83ee0a, ++ 0x01f70c48, 0xfd84dff4, 0x6947c1d7, 0x80e1c325, 0x0f475a7c, 0x1e7288c1, ++ 0xf9c1dbf4, 0x3cfe0324, 0x21bcd788, 0x597c8dfe, 0x9bfb3df7, 0x011f4f59, ++ 0x9e10be4d, 0x73a9d160, 0xb3e2182e, 0x3378265f, 0xc6a7c41d, 0x017e22a4, ++ 0xed0e5c9f, 0xf5ae0896, 0x83e491ac, 0xc707d7c6, 0xb8e17215, 0xc7f2e01c, ++ 0xc59e91bc, 0x6f1a5c8e, 0xf920eb19, 0xd189c9a0, 0xf1d8a0e8, 0xe25074dd, ++ 0xeebea950, 0x0e9a1613, 0xc7ddd5e3, 0xf893f542, 0xe48936d3, 0x167b971d, ++ 0x19f0f72e, 0x2ff20e7b, 0xcb45de5a, 0x96b968b7, 0x4bf2e26a, 0x9fa6b3c3, ++ 0x72e4cea4, 0x82fb92fd, 0x9df58332, 0xc9bc79b5, 0x14f48653, 0x8b16bbff, ++ 0xbd96217a, 0x1dda0f2c, 0x2578cdb6, 0x57e3e005, 0x55f70798, 0x1da5c01c, ++ 0xc31e3fde, 0x2fffd802, 0xbbdd3852, 0x8d7e9c4c, 0x5b15978a, 0x213d2f11, ++ 0x9925e203, 0x351e91d9, 0x836e3e78, 0x3bf04aef, 0xbf066f2e, 0xd8a6b0b7, ++ 0x5ecbef88, 0x7abe218a, 0x682d9f66, 0x97c2fd26, 0x52fe80e3, 0xde9337de, ++ 0x8d92ffd9, 0x91bf63e4, 0xf680efcd, 0x892fd44e, 0x3e70d65e, 0x829d7880, ++ 0xc19654d4, 0xaba5f690, 0x6a059033, 0x83bd56fa, 0xf5c34deb, 0xdb9f511b, ++ 0x2ba72373, 0xf1fc8ab3, 0x6ef7a38c, 0x587cc32c, 0x08b7ca00, 0xccf7fb3c, ++ 0xde17be2c, 0x3756bdfb, 0x18afbe87, 0xff2cd5e9, 0xd00b46e8, 0xbef96cd7, ++ 0x8eb03df0, 0x1dab2cfa, 0xce795ce5, 0x1378fe9f, 0x63dd3f94, 0xf3c46664, ++ 0xb3e73393, 0x6ff9d1bc, 0xb478d06d, 0xdcbf6237, 0xae5f4bbe, 0xfd97d0ef, ++ 0x2af2fa9d, 0x7c79cd87, 0xf70ef122, 0x66d740b7, 0xed27e373, 0xcbf35f30, ++ 0x3f479266, 0xe2d6f874, 0x84306a7e, 0x9b3840df, 0xe49f3e73, 0xfae83a43, ++ 0x19a7c242, 0x88a7a768, 0xf5f71fc3, 0x39859899, 0x36e011f6, 0x31663f04, ++ 0xfb419c10, 0x73e24fe6, 0x9c4fb17e, 0x07a7cf26, 0xe64bfd60, 0xd157dac6, ++ 0x94e54f1b, 0x690fd452, 0xf9bfcc8e, 0x49a54faa, 0xf116aed4, 0xb40e7c7f, ++ 0x6cd57983, 0x8eb0f2e6, 0xbee3c4f5, 0xd23d006d, 0x223e2802, 0x537b70f0, ++ 0xff0434b8, 0x18ac4b6c, 0xbe54f38f, 0x1f48bc51, 0x08dfb16b, 0x1d3ff7bd, ++ 0xbedc0e5c, 0xa7dec62b, 0x5743a383, 0xd9a677f6, 0x9ff722fb, 0x532c3fe0, ++ 0x9bed2252, 0x7fdf250f, 0x2deafc22, 0x3019a6bd, 0x9cdf15fe, 0x74bf7e26, ++ 0x05d91579, 0x99b27a43, 0x7bd2d3f8, 0xb5fef47c, 0xa42e572d, 0x51896df5, ++ 0x1fc7ee11, 0x97de8897, 0x16835a66, 0x0e15e7f8, 0x852f3fae, 0x386924ef, ++ 0xf6e1a31c, 0x5d2bb6f1, 0x331f4748, 0x83a05e3e, 0xdb1f1feb, 0xbcf95e01, ++ 0x71f7f60d, 0x12e3e827, 0x4fcaf9c2, 0x7d2e2f91, 0x9ea3765c, 0xee6dbac0, ++ 0xb3cb0cb1, 0x62b62fc6, 0x6692a77f, 0xedb6fb40, 0xbd32ecb3, 0xdfc8bd97, ++ 0xb9ec0f40, 0xdb2bde02, 0x771e92a7, 0x9f3371f0, 0x14f2c3a7, 0x6f8ae3ae, ++ 0x8a57da64, 0xdf50f981, 0xc679336d, 0xb7567ee3, 0xf11b393d, 0x749cf1f2, ++ 0x4e7fb503, 0x87847662, 0xbe0a7963, 0x5e292a5f, 0x9b35bfdc, 0xf5232b6b, ++ 0x2643bf1d, 0xb9c8cefc, 0x4ad7a52f, 0x9446e9fb, 0xc38ff5a3, 0xe7f1c1fe, ++ 0x9bc7f7be, 0xe9fb919c, 0x886652ae, 0xb5db7ef8, 0x17f84f44, 0x152d7802, ++ 0x7ddf3af0, 0xf6d38e65, 0xf2016345, 0x1aaba5d1, 0xe823ec0b, 0x62fb8315, ++ 0xa787df1b, 0xd6fb121c, 0xa8947480, 0xb3461bb3, 0x0685acb3, 0x37162b92, ++ 0xcf093cf3, 0xd1733054, 0x2a25769e, 0x9a266f9c, 0x57ca3e08, 0x2dfaee77, ++ 0x8709ebac, 0xf7844a4f, 0x8c53cc39, 0xf6c35778, 0x11635032, 0xb177a4c4, ++ 0xc7ae666d, 0xde8f5c2a, 0x5a9ecc94, 0x3b5f6117, 0x17c07f45, 0xfe9fb162, ++ 0x81bf5f23, 0xfec86d70, 0x07ea127c, 0x4da7b3fe, 0xdad7ac2a, 0xb73f1125, ++ 0xe90cbdba, 0x8735dfc5, 0xe21a2a2d, 0x97377ec3, 0x5aebd113, 0x17edc898, ++ 0xfd4c33bf, 0xf7c4935c, 0xd3839b6f, 0xb1e5d6e7, 0x5bafe441, 0x9c18c19d, ++ 0x4fbbdff4, 0xd6a97d35, 0xd96cf1c2, 0x8c8f2bf9, 0xec941df4, 0xf2acb163, ++ 0xb35031fd, 0x38c32820, 0x0fccee9f, 0x0ccf7950, 0xd6750cb7, 0xce6b3f9d, ++ 0x1a753843, 0xeaded8dd, 0xf5c78dee, 0x58f3ba7d, 0x66afae3c, 0xaeeb4ca7, ++ 0xb2917e09, 0x2f8868b8, 0x15f24efc, 0x5d98bc23, 0x1af8e2b2, 0xe774f87f, ++ 0x564594a9, 0xfc93ff6e, 0x5c323c9c, 0x4a331d52, 0x570e0113, 0xf2f1ce5c, ++ 0x20e673d9, 0x62cfbdf2, 0xf045be40, 0x5c6ccfdb, 0x6a2455de, 0x36475af6, ++ 0xf2c19bca, 0xe40685ad, 0xf3b23f13, 0x1d4d3bf5, 0xff1fb8d9, 0xb3f7d247, ++ 0x82c0d9ac, 0x9b6bdbc0, 0x8fc03401, 0xc5e67b3e, 0x9ff7e46c, 0x7662f93e, ++ 0xa2fcc455, 0x739ed3bf, 0xd97d8513, 0x02c798fa, 0x6d3155e3, 0x8e2650bc, ++ 0x7f36e557, 0x3585fc88, 0xee0cf2cf, 0x8cfe3c9b, 0x7b36cf6c, 0xb80e0f88, ++ 0xa1d22acd, 0x4d40ddf6, 0xdbf507ac, 0xfe216601, 0x8725d557, 0xc79fd8cc, ++ 0x7689c633, 0x547df68c, 0x3d049bff, 0xf9129d49, 0xc28ae203, 0x61ff8fc4, ++ 0x7c04ef7e, 0xc07bf046, 0xf1225273, 0x191bf0fb, 0x84c3e88c, 0x58353370, ++ 0x294f9415, 0x857d39ab, 0xbb206c7f, 0xb2ee94ca, 0xa2bb3f22, 0x00c9b620, ++ 0x1b19d11b, 0x7e81893f, 0x485e9595, 0x9c6503ed, 0x8c2903ee, 0xac6967fc, ++ 0x6d7e2251, 0x4f7f25ef, 0x5f6634e6, 0x1217c507, 0x62ea9eb9, 0x3e72cdee, ++ 0x7f425de1, 0x4d0f068f, 0x20fd202e, 0xb24cfc7f, 0x5d48fd10, 0xb29de912, ++ 0xf60163a1, 0x3d3d1a3b, 0xd053e1ac, 0x5ff960d3, 0x34db4f44, 0x4f461dfa, ++ 0xc9e8953e, 0x9e991965, 0x5dfd8954, 0x8bc059ed, 0x80aa6bf6, 0xef8243d7, ++ 0xe16c7f84, 0x19002c7e, 0xf452b7ae, 0x86b16957, 0x6e1f9464, 0x11bde7e3, ++ 0xd036ccf6, 0x4a4ed17f, 0x9e1dfd43, 0xaa17ab19, 0xd3d63784, 0xb882fe8b, ++ 0x8f9216a9, 0x727a180f, 0x9d495f51, 0xe91bb8d0, 0x51417522, 0xffb26ac9, ++ 0x0f281d32, 0xdf92b650, 0xb7997966, 0x5f42292f, 0x4cf6e6e8, 0x7a1e3dc3, ++ 0xeb8bb33f, 0x2631fe07, 0x9dfd87d2, 0xdcf10052, 0x510535e0, 0xb8916a0f, ++ 0x60f0257f, 0x917e8a8c, 0x12ba8736, 0x27eda7e9, 0x46a03baa, 0xb77b73fa, ++ 0x56f48bdf, 0x47bf2563, 0x65b8239b, 0xa1bbb609, 0xfdedda88, 0x1fc7cc9b, ++ 0xb6fc68cb, 0xe3d20ee2, 0xb952aedb, 0xafe0457f, 0xcd278e6d, 0xb340fa81, ++ 0xb5b73f7e, 0xe112d27b, 0x000d80fd, 0xad55e303, 0xa43c218f, 0x2cce1ccb, ++ 0xcfe5c2c1, 0x7e40be70, 0x026994e3, 0x918fad31, 0xcfb833be, 0x39605381, ++ 0xe5b7d45d, 0x0f3038c2, 0x1737915b, 0x1b59ef35, 0x0b143e9f, 0x7e829af4, ++ 0x05946e37, 0x7f27ef50, 0x3b932f2f, 0x4c0351f8, 0x576b1d24, 0x2cbf2bae, ++ 0x0fda2ca2, 0xa6bf6f7d, 0xeee4933c, 0x1b4e3d60, 0xf656b1e4, 0xd6bcc0c4, ++ 0x15ea86da, 0x9d2d77d0, 0xb03eff12, 0x2059eaff, 0x6d2407a2, 0x1e2d95fc, ++ 0x30c5fff4, 0xf39178dd, 0x37faa253, 0x5556ff42, 0x62a3bf6b, 0x6f9818d6, ++ 0xbafe5689, 0x7bf303d9, 0x8fefa8c8, 0xc7be2a40, 0x1fde3682, 0xadd72b92, ++ 0x0bd21ccf, 0x25304f40, 0x07e90f25, 0x6cabdf6b, 0x8ac610bd, 0xa1329fb3, ++ 0xbce4d5dc, 0xfe9129df, 0x5d5fbd11, 0xfc3f9c49, 0x1d557cc3, 0x92bb47a6, ++ 0x3d1e90a6, 0xd824b71b, 0xfdb7c41f, 0xea1979f7, 0x648fa073, 0xf23e9126, ++ 0x5003f1f9, 0x2ff73fdf, 0xd8a8646f, 0xa8058eee, 0x2acffaf7, 0x5dfeb744, ++ 0xba025072, 0x02fd88b5, 0xfcfc9c72, 0xb32d3d1a, 0x04753a0b, 0xda2dc618, ++ 0x0129a5ba, 0xecc6afa2, 0x2b97001b, 0x68e33c93, 0x4657611c, 0xc493dbaf, ++ 0x617f07ed, 0xec0296d9, 0x50c4a77f, 0x7857584f, 0xd9116534, 0x2ca61f4d, ++ 0xb6aef88e, 0x678251f3, 0x88e32eed, 0x7124f470, 0xdf61b6fd, 0x1be41e0b, ++ 0xe225059f, 0xb04a3509, 0xd72812e5, 0x135018d4, 0x0b839364, 0xc5b8a26f, ++ 0x0b1b137c, 0x39402beb, 0x75d8f387, 0x5c12e07d, 0xc127fc37, 0x25deadab, ++ 0xceb74f24, 0xee2958b7, 0x07755853, 0xeb1ec1c1, 0x2bac3841, 0x71c34b2c, ++ 0xb6cce61a, 0xf403bc53, 0xb86fac38, 0x0bf266e7, 0xd75af369, 0x3d40ac69, ++ 0xb9f414a7, 0xb3bcc15f, 0x70aeaf12, 0x90ce3ec3, 0x05df1777, 0xf0a34de5, ++ 0x9c9df7f1, 0xde49378f, 0x93260fc0, 0xfa45941f, 0xb93a7335, 0xc93f38de, ++ 0xcf6bf3a4, 0xecfae24f, 0x999e8165, 0x95fb3e48, 0xa7d438de, 0x05f3ccfd, ++ 0x6bcccfda, 0x3c249f55, 0x5ce47e71, 0xcc7f92a1, 0xe07dece2, 0x4cbfac42, ++ 0x2985fb21, 0xb8e08fbd, 0xf74e2dfd, 0x01f6263a, 0x2229ef96, 0x24cde7bb, ++ 0x6fc462df, 0xfb53d0a9, 0x8c595df7, 0xef4d447e, 0x16d2796a, 0xd4fc855c, ++ 0x815c3ea6, 0x852bf4fc, 0x84b324f8, 0x3f42667b, 0xa44d7fb5, 0xf38a5f7e, ++ 0xb6bd2235, 0x905b04c4, 0x32ed020e, 0xb5ce73b5, 0x4f9fb084, 0xa3b5b29f, ++ 0xb674697e, 0x3063a432, 0x625fc857, 0x0a997a71, 0x858199e5, 0x22f2848a, ++ 0x89999f4a, 0x57b22afe, 0x2dafe49c, 0x2c63fb13, 0x0b71c150, 0x6fa6856d, ++ 0x9bf48693, 0x53cf5f43, 0xf7a6a5f0, 0x7fdc2c18, 0x963f3e5e, 0x4d6cf8e1, ++ 0xfa030df8, 0x0c3d9deb, 0x0efae0f5, 0x2fa9c689, 0x7684de7c, 0x7c1dedcb, ++ 0x9d85fb7f, 0x46cbf001, 0x2925a2bd, 0x4d97e84e, 0x7ac1cfdc, 0x3840c8de, ++ 0xc9f1cb3f, 0xf08bb418, 0xe1cec2af, 0x67f440fc, 0x7a867112, 0x490257e1, ++ 0x24fcf5c8, 0x255d6f4d, 0xfe568df4, 0x926ee314, 0xc2323c7a, 0xf9d258b3, ++ 0x2fe7b5c3, 0xaf09f7c4, 0xfee36786, 0xa17d030d, 0x348b697f, 0x61d78ee7, ++ 0x4ca65b7d, 0xe60aa370, 0x4b927202, 0x22903df0, 0xe7727dc0, 0x6e91b317, ++ 0xfda30558, 0x4339d0da, 0x78f2b7ae, 0xa90bea0c, 0x58ed8d71, 0x215b7a9f, ++ 0x8f8c67c9, 0xb7655c60, 0x959a6b80, 0xab5cebfb, 0xbf18b902, 0x7bd5784c, ++ 0xfe38ebc7, 0x6fe4b105, 0xd8dc054d, 0x8cd9e912, 0x2b172dfe, 0xd7f2803e, ++ 0xe096a955, 0x1d38b47c, 0x14e6f9c6, 0x72a71f11, 0xecf25ba2, 0x49cbe780, ++ 0xd8175a0e, 0x5f381577, 0x0eb41f7c, 0x6fd10dc5, 0x5c62e387, 0x69fd9f0e, ++ 0xfcfc8521, 0x449fcf20, 0xdb34ed3a, 0x9d955e11, 0xf28bbe6f, 0x3ac2d2b6, ++ 0xa51a8e28, 0x7f1cdcb7, 0xffa441fd, 0xb7c71381, 0xbaf38fdf, 0x47dbaf61, ++ 0x23ebd1f8, 0xf5ce5c57, 0x8c9ecff2, 0xdc8f5153, 0xe836f821, 0xf2fe3c8f, ++ 0xa323b71c, 0x93f7c8f5, 0x60e47af4, 0x47ae9ff9, 0x6005f9f2, 0xf0464f7e, ++ 0xfbb0bf77, 0xc64e6a06, 0x78fafca3, 0xff203e70, 0x94f4874b, 0x1f719daa, ++ 0xb41b3ee2, 0x11f4a22b, 0x7fc79da5, 0x7c49ac30, 0x711261d7, 0x216b8f2d, ++ 0x051c3ffa, 0x3d0e7fc4, 0xba401715, 0x4311d939, 0x30e2997a, 0x4d5e7085, ++ 0x0683982f, 0x80a0f909, 0x5788b757, 0x2c1c4499, 0x854540b1, 0x4bc9af62, ++ 0xbcf03f7c, 0xe2abc791, 0x053ccf83, 0x69fdbae5, 0xa8c59e22, 0x38bec0ff, ++ 0xac5d7782, 0xd7fd809a, 0x61893afd, 0xc6006a9c, 0x13df3c43, 0x539c93e3, ++ 0xfbc5ae30, 0x5598af67, 0x150b3f1e, 0xed0e0038, 0x1dffae41, 0x4c84342b, ++ 0xd476eeb0, 0xf5dfb017, 0xaf8b5c5a, 0x0cc1e073, 0x6541971e, 0x16b2ed04, ++ 0xd6aa2fee, 0xb9fb55e2, 0xc45aae1f, 0x5dcd8ea5, 0x468604f2, 0x0ac6a49a, ++ 0xacced3b4, 0xf3fe419b, 0x439e1fbb, 0xbd66eacf, 0xfa097fbf, 0xe287f3e7, ++ 0xbddf9ac1, 0x5c4db98a, 0x1ff21e7f, 0x519f401a, 0x9432959b, 0xbeccb99f, ++ 0x1a81e50a, 0x854dec00, 0x513c1367, 0xca009789, 0x71694ed0, 0xd7be22c6, ++ 0x6e481936, 0x1e0c9a05, 0xcbd1a76c, 0x672e4e05, 0x9d82a167, 0xc410244c, ++ 0x9367b471, 0x441bc451, 0x21992b7f, 0xc4834f84, 0x4aed6b9f, 0x5bf248c5, ++ 0xd8c9afeb, 0x7a819968, 0xfc819673, 0x9e4c67dd, 0x4e2fe4f9, 0x353c202c, ++ 0x2b9b1ad9, 0xa5ed3d78, 0x2f613133, 0xb8574fd5, 0x44d4c962, 0x4ef9a7e4, ++ 0x86885f1e, 0x7d56e2db, 0x530e3a39, 0xab97d41b, 0x5a5c6f99, 0x441b8f3e, ++ 0x7277cfbe, 0x5d66767e, 0xdbb780ae, 0x5b577c84, 0x0e4ccaff, 0x7f164337, ++ 0xcd9565e6, 0x73c83a47, 0x230f2898, 0xaafdc1cf, 0x7f9a12b0, 0x44a774de, ++ 0xdf3511f4, 0xa7a70726, 0x43f70b40, 0x8ff3bdfe, 0xceb5f79e, 0x3c372114, ++ 0x565b8c2e, 0x87144ddb, 0x497f573e, 0x97cf5383, 0x7cffcb06, 0xf3db96fb, ++ 0x97c8b22d, 0xaa5f13b1, 0x1cb5f3b2, 0x854fdc93, 0xf415bdf0, 0x8b475c06, ++ 0x647c825c, 0x5a56f5e6, 0xe07ec347, 0xbac71823, 0xe51b37af, 0x6f59437a, ++ 0xa26bc601, 0x55b38be1, 0xed067e34, 0x8f609caa, 0xacd0dea0, 0x8f0dc78f, ++ 0x23567aaf, 0x70d4789f, 0x289bf76c, 0x90c776bf, 0x1d7f82fc, 0xdffee330, ++ 0xcd7c4b97, 0xe03df361, 0x3632fd44, 0x5ce9fdb4, 0x1eb863d4, 0x6e65df55, ++ 0xaab13d47, 0x87be2229, 0x8faf5bff, 0x44e6b1f7, 0x36b3bbf2, 0x6d9afbfd, ++ 0x8b0ddf51, 0x5e12b5ff, 0xe37c9936, 0x1c83bf71, 0x1383bca2, 0xf88606b5, ++ 0x4bdd96ad, 0x889d4850, 0x27e7ebd1, 0x3f5f1c6c, 0x85fa6a77, 0x3cf100bb, ++ 0x67861e58, 0xb9e20177, 0x917cc0da, 0x9e23d4fd, 0x0275bf01, 0x985e27cf, ++ 0xfe78805a, 0x02d4f77c, 0x6326f3c4, 0xcdf707ab, 0x97efbb7a, 0x59be9f08, ++ 0x30afd25e, 0xd1f7071f, 0x6863d2b9, 0x1e9c9e70, 0xf3cea343, 0x196fe39f, ++ 0x3dbe3e4d, 0x7cbd0f38, 0x4cd49a74, 0x165507e4, 0x49ca77f3, 0x9fd11bfc, ++ 0xff933167, 0xa7d7ff63, 0x463e5036, 0x89fa4c97, 0xc57edfd6, 0xd1fa8f97, ++ 0xee5d77fe, 0xff7a3480, 0xc73b0977, 0xf4016165, 0x817668b3, 0xf3465fa6, ++ 0xafb15ee3, 0xfcf4ecff, 0xb01fe920, 0x71ff354f, 0x0963688d, 0xef7ae29e, ++ 0xfdcdc94e, 0x4fe41dc7, 0x685ee86e, 0x27f17f47, 0x6e3fee41, 0xfc98a178, ++ 0xd7c1b5c7, 0xc61f9842, 0xda3b24ba, 0x3f3bb523, 0x003cc78c, 0x3b05eecd, ++ 0xf2938cf7, 0xeff6f46b, 0xf163c127, 0xf3003798, 0xb3f506be, 0x84d86738, ++ 0xf600df74, 0x3525831f, 0xb037e128, 0x232706df, 0xa77260bd, 0xe2d41ede, ++ 0x26bd5bbb, 0xbb5bbbe2, 0xebf220a4, 0x372f9314, 0xcb1ae513, 0x1b8f1fb4, ++ 0xb24a67da, 0x39393f27, 0x31eeae32, 0xf3581c61, 0x496ef53f, 0x35edfa20, ++ 0xf91d8f32, 0xe09b16d9, 0xb7f10a67, 0x8239b72f, 0x86f422eb, 0x4f5c832f, ++ 0xbbf2d5a8, 0x00521614, 0x79e64b5f, 0x91be208e, 0xf8a287df, 0x8b59647d, ++ 0x42cedfd7, 0x31ea9724, 0x79e449c3, 0x8e8bb645, 0x5c1c63e7, 0x2c6b0fd7, ++ 0x764fd156, 0x714dd5ab, 0xcd6fceae, 0xb700fafa, 0x2c3f619b, 0x5fa2192f, ++ 0xfd1a0f0d, 0xb47f0836, 0x1ae8e6bf, 0xa77f5fa4, 0xbafb4764, 0xb7e9cdce, ++ 0xf32fec0e, 0x9dfbe1a4, 0x46fd0075, 0xf6d1bbf0, 0xbf5927bf, 0xffcb07ff, ++ 0x35eb7f22, 0x58bd7ac9, 0xbfe6bf5b, 0x97675c1f, 0xd465f7c4, 0xd6eda2ba, ++ 0x66bbbf68, 0x3f2b9e77, 0x47828aac, 0x3c32ffd5, 0x0d87e346, 0x43f1a3c9, ++ 0xefe35c7d, 0xcbff87e6, 0xba278df1, 0x00378b1f, 0x0dcda8ab, 0xe75eb8b8, ++ 0x678bc5d1, 0x8f0f56cb, 0x9f3cca9b, 0xaeee3a22, 0x777116ce, 0x7b5f9fbe, ++ 0xd57c2641, 0x7d70f88b, 0x4d8dcdb7, 0x294bac6b, 0x3f1d1b3e, 0xcf76c65d, ++ 0xc7451446, 0x1f70eb51, 0x3c7f7fe7, 0xc1e4b1f5, 0xcc5c853c, 0xd3ce8853, ++ 0x2a7acd7a, 0xef8117c9, 0x043022b2, 0x8b6ba046, 0x11896012, 0xe64c9fef, ++ 0x226bf4fa, 0x6265c89f, 0xf2a798cd, 0x83ce2d90, 0xc0cb8c76, 0x26569df3, ++ 0x7e469f79, 0x3c055168, 0x1990fdf7, 0x184f2e00, 0x049f883b, 0xe46eadea, ++ 0x471f9a7f, 0xfc20dfeb, 0xe74ae711, 0xf9d144af, 0x7de2ff2b, 0xefb696ff, ++ 0xddb8deff, 0x6e8d8066, 0xdfa2303f, 0x94ce31b7, 0x476e9c3b, 0xfa3467eb, ++ 0xf7b253fd, 0x7eb993bf, 0x95f2893f, 0xc4bf91cf, 0x431f0e4d, 0x63db117f, ++ 0x89bfd156, 0x8b9212fe, 0xbd84d3eb, 0x439d2eee, 0x52eed679, 0x00fb17cc, ++ 0xe8f179ff, 0x41c9e3fa, 0xf1fd70fc, 0xf9f8a8e4, 0x65c7f4c7, 0x5c69ef76, ++ 0x4f0cdf67, 0xb5b7ca01, 0xda3f9836, 0x3cf0cf85, 0x9c316da3, 0x9c49b73e, ++ 0xa4f2d92e, 0xc4bbf273, 0x9bede8a6, 0x98bff2c1, 0xfca4a67f, 0x5fe7f8ab, ++ 0x3a8fd1e2, 0x91013f7a, 0x11e3d9ef, 0x23b634f1, 0xefedbfc2, 0xe37af9e1, ++ 0xf7b49c04, 0x771fd8b2, 0x310a78a6, 0x23f3edef, 0x004b0b16, 0xe7326795, ++ 0x2b5e0d8b, 0x3a1a17c5, 0xc34bde78, 0x77f88c7d, 0x514ffa03, 0x61ce747e, ++ 0xe13defa8, 0x4ca495f0, 0x358ab8c1, 0xdfa02720, 0xfd432e7d, 0x2f08ffae, ++ 0x2be1d0ff, 0x7dff7ac5, 0x68cf14bd, 0xe519fb9b, 0x7b7e955d, 0x64c54d6a, ++ 0x11f92f9a, 0x559f229c, 0x14c2df9b, 0x9ed07f1e, 0xede1060b, 0xe7febf21, ++ 0xdb3f3c35, 0xd1d8f4ef, 0xc5f9a11f, 0xf21ed4e3, 0xe1ec3533, 0xcca95b4a, ++ 0xcdeec3d7, 0xd86a7a24, 0xfd18a333, 0xa623aca7, 0xd2dcf518, 0xef64adf7, ++ 0x3a4f7e7d, 0x99bc49e5, 0xe116bbe4, 0xbc1c9b61, 0x1cd2f50a, 0xddf50718, ++ 0x555f77cf, 0xf8d6f38c, 0x9ff426df, 0x364dfb43, 0x599c5fbd, 0xed7cde78, ++ 0xff9a19d3, 0x6fec46fc, 0xcc87d893, 0x673a5ada, 0xedaf7d84, 0x40d954f7, ++ 0x62dea7fd, 0xc6b938a1, 0x9919360f, 0xc43f92cf, 0x7c8ba647, 0xe453bf42, ++ 0xe1cd7633, 0x6ca229f9, 0x3af3ea75, 0x359cecff, 0x3d30f11d, 0xbcbf3945, ++ 0x3cb0eb30, 0xf317ea01, 0x073ed0c2, 0x259f928c, 0x9fd72cee, 0xa226ecf3, ++ 0x37ec1b23, 0x1d00cf8a, 0x597f1ea1, 0x026667b8, 0x5b4c73ac, 0xef8432e8, ++ 0xc206b3fe, 0x6de73293, 0x4824cf8a, 0xf5fcbc7c, 0xd0e32dbd, 0x677f62ff, ++ 0x6d52a23a, 0xa86197b5, 0x378709ef, 0xf4fe4290, 0xaf1c42c6, 0x9e460fec, ++ 0x471dd947, 0xecb6857e, 0xeca3ca3a, 0x3baccf7f, 0x0cfd1357, 0x379455b0, ++ 0x5ff9d799, 0xedb02714, 0x87cc4691, 0x958a69fd, 0x3d02afc7, 0xe6b729b3, ++ 0x57f12732, 0x8a7dfba5, 0x0a2d2b4f, 0x64d61e72, 0x906218f4, 0xe464ad7f, ++ 0x66db1ce7, 0x72be2037, 0xc0cc5e44, 0xf24ebffe, 0xc5a29d91, 0xaf3c8205, ++ 0x06bbd8c9, 0x65652fed, 0xc401e5ef, 0xa1871ec7, 0x0bfb08a1, 0xa59f9037, ++ 0x9f218e3b, 0x5fcce9cf, 0x73942975, 0x0714ed9a, 0xf6e9781b, 0xc2abf21c, ++ 0xb08ec73a, 0x9e14a6ce, 0xc774a487, 0x298e5019, 0x471b991b, 0x65291c55, ++ 0xa147ef34, 0xbffcfd0c, 0x5a674e14, 0x4ffd14dc, 0x4cee9f28, 0xfd2075f1, ++ 0x5a279e0e, 0x13cfcb1e, 0x624fdc29, 0x73defe5b, 0xbb674e78, 0xeaf1a738, ++ 0xc97389fe, 0x48a2d7df, 0x0e338788, 0x25d9479e, 0xf870f1f6, 0xaaf94abf, ++ 0xc5ffdd79, 0x01cc19e5, 0x9c8c57fb, 0x6716945e, 0x0f15fa3b, 0x9f947cdb, ++ 0x2429bd3b, 0xdeccdc53, 0x1a8548f7, 0xe66cdf61, 0x1761a5f2, 0xeda3c7b7, ++ 0x2b93ef99, 0x2fe4187f, 0x960cae5c, 0x4afa45ff, 0xf93c946f, 0xa614edbb, ++ 0xf5a2efb7, 0x6e7b6896, 0xd51dfe98, 0x8bfa68df, 0x36528796, 0xa3d70e34, ++ 0x147e9a6d, 0x94e9e5d0, 0xccb8f959, 0x477fefa2, 0x2ff79da2, 0x565276f2, ++ 0x3f312bab, 0x4613fc3f, 0x7f2d3a7e, 0xf3c65028, 0xe006027c, 0x6f18b987, ++ 0xa1bca56a, 0x2492160c, 0x32f5a3f2, 0xf3152efc, 0x13bbe087, 0xc7047929, ++ 0x59bb99c7, 0x4aa97e26, 0xcc18ef38, 0xd53ca13b, 0x382596e0, 0x1a560dce, ++ 0x4ef30627, 0x01d4c22e, 0xafe416cf, 0x5c786b33, 0x30e41d21, 0x18fa6fd2, ++ 0xf331874e, 0x9689fe79, 0x83e5a25f, 0x13287068, 0xb71f4df0, 0x60f91724, ++ 0x067be48b, 0x89169ef5, 0x20f027c3, 0x39b42bf7, 0x7286af40, 0xca04ed5b, ++ 0xbc601bff, 0x818d40ff, 0x0fcb52e8, 0xf2ab1b6c, 0xe37f4073, 0x8adae5e7, ++ 0xb0c9be79, 0xb82894bc, 0x9929796a, 0xa9b1bef1, 0x11e743c9, 0x8d123cb5, ++ 0x17f0224e, 0xb6f18188, 0xbe7d7376, 0xeb44c6ac, 0x9abda818, 0xb50391fc, ++ 0xbf728606, 0xe9cccbac, 0xadbc6a2e, 0x842c4df3, 0x18c12afd, 0xfe1a9fe4, ++ 0x059f4fbf, 0xbfa216bc, 0x1515d5f7, 0x8c01f517, 0xd2f0ae0f, 0xea462073, ++ 0x277f3190, 0x3880bc26, 0x35d76b95, 0x6798c5ca, 0x8096ce13, 0x1e5b6c64, ++ 0x2e4054a9, 0x3f87240c, 0xe6c672c0, 0x1b1e5e6e, 0xfb412ede, 0x25655762, ++ 0x4c5a47b5, 0x31fcac67, 0x7ac0654f, 0x6beef21e, 0xe1bf9d16, 0xb3d6b845, ++ 0xe43d35de, 0x6ef21227, 0xac87e732, 0x7ee41cdc, 0x65fc952a, 0x4972d387, ++ 0xe616b00f, 0xfac1e9ed, 0xd7f9334c, 0xfde89ea0, 0xbc19d8f0, 0x6778e55e, ++ 0xc79e3699, 0xc8037ac1, 0xcee70ecf, 0x3d753f20, 0xa7d007ee, 0x7cfab4be, ++ 0x13cf00a9, 0xb8ddcf52, 0xfacf0e0f, 0xefa422f7, 0x1def7b13, 0x4ae6fc83, ++ 0x23e9e813, 0x2e3397f0, 0x8c065fce, 0xfa0966d6, 0xabeac179, 0x1bbc75c5, ++ 0xa63660b7, 0x9a4fcf96, 0x04a3c261, 0xcc8cf02c, 0xbc0410b4, 0xfae3cc77, ++ 0x2bdca3a3, 0xeae81e61, 0x648f3e18, 0x7d21e29f, 0xba4f37c6, 0x5abfd601, ++ 0x530dfa12, 0x290ec813, 0xbcf01354, 0x37389d5f, 0x7cfd8b2a, 0x1946c771, ++ 0xafdfe7f5, 0x4552f778, 0x5f2e5d19, 0x686f651f, 0xbe54e6cf, 0x7ab2b98e, ++ 0x1ac7d201, 0xca9bf429, 0x4abdf18b, 0x2fc567ef, 0xd3f98c9f, 0x4e35c657, ++ 0xb0e9ff46, 0xbef009f7, 0xe66ca228, 0xe12ceaed, 0xd9e8056c, 0x8f5be31d, ++ 0xf0b33970, 0xff71bbc3, 0xf87e9dde, 0x385fcc03, 0x38fb146c, 0xc1fe124b, ++ 0x80f199b6, 0x1df237af, 0x42c2ff22, 0x1c637bf8, 0xe60e0ff7, 0x28978d97, ++ 0x1e72aedf, 0x0d79b73f, 0x85ea69eb, 0x0089c9ef, 0xe5a7b3f5, 0x29579e92, ++ 0xbf6621f2, 0x7b478deb, 0xc30ff67d, 0x3477e20a, 0x32e95cf8, 0xf411bdaa, ++ 0x2faa957a, 0x2fa8535f, 0x97d6eb5f, 0x9bed307f, 0x87e59171, 0x20cf3c63, ++ 0xf12cbd5d, 0xc5c0cc7c, 0xacfa4ecc, 0x7ea00a53, 0x74c5f131, 0xe795de71, ++ 0xd85cfe0d, 0x634e2f43, 0xcbb29f54, 0xf9f303b2, 0x2cb2bf35, 0x98ba27ea, ++ 0xe0912725, 0x2c28f241, 0x2743fc89, 0xded85ac5, 0xbfdcec3b, 0xd04d6d0a, ++ 0x2a85decf, 0xac5365c5, 0xee397606, 0xda16c987, 0x9619a50f, 0x579fa458, ++ 0xe769fd05, 0x2c7a3597, 0xf3179855, 0x79e86020, 0xb46c3cf8, 0x723f401f, ++ 0xe74653e0, 0xa19b18bd, 0x18a43e50, 0x5495b18b, 0xf9d04c7e, 0xfe9f1aab, ++ 0x7df84289, 0x7c2266dd, 0xdb96bfca, 0xec600e51, 0x27c3fd06, 0xf9a04fd7, ++ 0x7608fb69, 0xd90c18fd, 0x57eb4c49, 0x0a24e031, 0xd1acbced, 0x53a18539, ++ 0xd2316e50, 0x5978b547, 0x3bf06596, 0x26977e0f, 0xc0deb9fa, 0x54acd6e3, ++ 0x39c5e3c4, 0x2f5114ac, 0x15f9bd75, 0xd4e9cbd2, 0x9defa25c, 0xf48bd7cc, ++ 0x2adc9b2a, 0x3fb6b3d2, 0xdfc9caec, 0x7ae1a654, 0xeb4c7e0a, 0xc766dab9, ++ 0x9cc214f5, 0xd3d227e6, 0xfd825493, 0xe5a7c4a8, 0xf5fdfe58, 0x552e4715, ++ 0x7c23f822, 0x8fbfcf5f, 0x82ef7fd3, 0xbe2313ef, 0x8bef878f, 0x58cf7f86, ++ 0xb5739088, 0x22d5ff98, 0xcda774df, 0xc24c3212, 0x5ed54bfe, 0xe14e4ef8, ++ 0x87898fdf, 0x0a2f28f7, 0x6c1d79f5, 0xf942db9a, 0x1c7951c0, 0xa5f74a57, ++ 0xcab97ee1, 0x0bd5df52, 0xf029bffd, 0x77c1a573, 0xdfef0eda, 0x1070505c, ++ 0x258555f7, 0xdd1e60a8, 0x06b42c35, 0xc3303691, 0x9f2384f7, 0x0b9c7df6, ++ 0xfb20d8e0, 0xf94225c6, 0xcc75b184, 0x2fb4b91d, 0xc329aeac, 0x5fe1afe7, ++ 0x01d2075b, 0x1d20d3d2, 0xc35bcd44, 0x83aebb17, 0x071edf12, 0x9a9f05fd, ++ 0x2358c33e, 0xb35673cf, 0xc405d686, 0x38d2db32, 0x3789f506, 0x0fc4036b, ++ 0x423c74ae, 0xe9695079, 0xd79c5cbe, 0xc8bf0bfc, 0x6bb1b056, 0xd7d438e1, ++ 0xff79be61, 0xf4d5f397, 0xbe7961b6, 0x79749a9f, 0x1feda3be, 0xea3f5c6d, ++ 0x03e63263, 0xaede53b7, 0x8dd59e7f, 0x98fc33e7, 0xe2993a77, 0xbd8fa445, ++ 0x373d7124, 0xfe845920, 0xc0f9ae74, 0xf559eb8c, 0x2e967a83, 0x98adbd9f, ++ 0x0eedbbcf, 0x97b4f495, 0xb03ede25, 0x6e3d7190, 0x6c5fa88e, 0xef2d7aa7, ++ 0xfb9dadbd, 0x185edae9, 0xa0bf62a7, 0x671c917f, 0xcbbf4209, 0xedb5fce5, ++ 0xe01ed562, 0xca5266e0, 0x26f69e50, 0xb71bd723, 0x94a5dc1a, 0xbd026257, ++ 0x3981c78a, 0xc7cb1a7f, 0xd5e7f68f, 0xbcfef4b9, 0xc93ff2c1, 0xeedeb79f, ++ 0x2d5d23f3, 0x4b64f22e, 0xf7179c06, 0x6e7d01eb, 0x6e9861eb, 0xf50638d6, ++ 0xe358abed, 0xa27c863b, 0x7ee31fcf, 0xe8113f9a, 0x9f475f33, 0x3992bb77, ++ 0x4579c43f, 0x3a6883f3, 0xb7de39bc, 0x736dc702, 0x80dfbc74, 0xd9976a7a, ++ 0x7958f3cd, 0x1f345e5e, 0x22cf9888, 0x29c7cf85, 0xb59f34cb, 0xe6a25fb4, ++ 0x24fb2e73, 0x19533e92, 0xeda30fdf, 0x05855497, 0xfb43256c, 0xdf18e1e5, ++ 0xe0ef5c26, 0xedc359be, 0x96f36192, 0x375f44ad, 0x16e3c4de, 0xd72e38fe, ++ 0x06917e30, 0xe311cfe3, 0xe9c2d8df, 0x337fc6f0, 0xf4c2dd11, 0xb9ff3843, ++ 0x574e7ea2, 0xcd2de53d, 0x8d1e372d, 0x9c5aef94, 0x3768be64, 0xc46c59cf, ++ 0x52af302d, 0x7f989f1f, 0xdc8f8f2b, 0x388d1ac0, 0xe9e71bdf, 0xd6cf99fb, ++ 0x5879817f, 0xbfd56ff3, 0x1835de7f, 0x718718d7, 0x7ec2838d, 0x82fd801f, ++ 0xe4f5e9fb, 0x00eedba5, 0xd3f71dfa, 0xf7f412a2, 0xdda94acc, 0x4fca11b9, ++ 0xe5409d6f, 0xf96e53d7, 0xdfac61d1, 0x72e5405e, 0xfb432a4c, 0xca23f703, ++ 0xae9bd29b, 0x0f7185ce, 0xef7e88c6, 0xaefb79e0, 0x1cdb5f58, 0x949ae768, ++ 0xe587f947, 0x2c0cdf82, 0x5cd7f5e6, 0xa629e368, 0xdfe4a9b7, 0x2f0d8f2b, ++ 0xbb7ffa40, 0x304bbff8, 0x4f3cb61f, 0x9e5e4b94, 0xd283e580, 0xbeee7417, ++ 0x20aadebf, 0xb9d21bfc, 0xa162745f, 0x700f1a14, 0xfd144f29, 0x5575f3d7, ++ 0x8e933c96, 0x8cbca3fb, 0x3dd133f7, 0xdb1f25a3, 0xb9524e19, 0x8f12dd3f, ++ 0x67db50fc, 0x297db547, 0xd8af24f4, 0x3e7a2ff7, 0x7e824a6c, 0x8dc916bd, ++ 0xfb4ef44b, 0x665aec90, 0xbcb9e7e5, 0xfd055c9e, 0x3c3d33aa, 0xb2ccb25f, ++ 0xe2ed0d32, 0xc9a67ceb, 0xa5bb2eb8, 0x27ea20f8, 0x4c66d309, 0x0b5afca1, ++ 0x039ca233, 0xfb4e3fba, 0xd917ea70, 0x566c48f1, 0x746bdd3d, 0xf7a34735, ++ 0xc35d3d72, 0x95dcfd7e, 0x5afcfdfc, 0x4331d747, 0xfe9a3d74, 0x8afaf30a, ++ 0x7aa5e3f6, 0x4e3835f9, 0x1e8cbed4, 0x817e3477, 0x74fc917f, 0xb41d7e68, ++ 0x0b3132ff, 0x67f71f2d, 0x633fb6ab, 0x261e60d3, 0x6b9d0f43, 0x13dc91c9, ++ 0x28e820e8, 0xbf36867a, 0x9675f42c, 0xfe179f0c, 0xc79e9a29, 0x0f689cff, ++ 0xf87a8a67, 0x8712c3ce, 0xa7e305e6, 0xac3d21a7, 0x5c79f3e1, 0x45fce46a, ++ 0x1d9ad9e8, 0xb7ada0dd, 0xd2debf53, 0xdcce7e58, 0xf20efe85, 0x184f1775, ++ 0xe039f79c, 0x5f8f5b41, 0x1679edc8, 0x6b04cdaf, 0x4d51c1bb, 0x1643f3f4, ++ 0xa3f50178, 0x0bbead4f, 0x1aaf9e71, 0xbf68dd02, 0x8a1e662c, 0xb87d0277, ++ 0x5f02fe69, 0xe1a37cda, 0x3f0a30d4, 0x344f5e8d, 0xd6f0867c, 0x769dfa43, ++ 0xbd706c6e, 0x4d4eb8e7, 0xf49a712f, 0xe144a67e, 0x7e144a17, 0x9428a420, ++ 0xd62c95cf, 0x4cfe7a8d, 0x45fa44b7, 0x5f10b325, 0xf2e0acae, 0xf5cad13c, ++ 0x8fee4d0f, 0xb8ae3fb6, 0xaabf119c, 0x9ce263ac, 0x34575f1a, 0xdeb2a61d, ++ 0xd2b3e31f, 0x84596ea2, 0x14f51efb, 0x95fe6875, 0xae3fee56, 0xdf84934d, ++ 0xca0a77b8, 0x30f2c1f9, 0x053bdf39, 0x5902cff9, 0x3ca9571f, 0x8994fdcb, ++ 0x2b3d1967, 0x414e1fdd, 0xd1589f39, 0xd8f9053b, 0x967827bf, 0xc0f87ee1, ++ 0xd1b9fdc0, 0xcd3bbc70, 0xcf29f9a0, 0xf7a33e89, 0xfaaf168f, 0x07bbead2, ++ 0x1afcd1c7, 0x529ea427, 0xc929b46c, 0xcbe7d62e, 0xd8763a45, 0x7fa06773, ++ 0xe4059e62, 0x00e30191, 0x1df895be, 0xbf6fcff0, 0x9b0f6345, 0x286f1c02, ++ 0xf0afddf7, 0x770e0961, 0x12cc380a, 0x36e4f572, 0xe502e299, 0xd0c7c29e, ++ 0x643fef75, 0xafda4164, 0xda8b921e, 0x41275cfd, 0xfb610a81, 0x67a46d67, ++ 0x9aab7d2c, 0x36e31ae2, 0x211a981b, 0x6307c727, 0x4c52f775, 0x2ba895dc, ++ 0xae91d05f, 0x67617f6b, 0x38beae9e, 0x7f574134, 0x5d12a1d1, 0x25cf4a79, ++ 0xdf53f6ba, 0x2f95d32d, 0xd75abdee, 0xe64fd2fe, 0x3120caea, 0x53f75c14, ++ 0x15b624fb, 0x7c3d3dd6, 0xfffbeeb3, 0x10fb3ad9, 0x098f17c6, 0x3c0599fb, ++ 0x8700853d, 0x9edd1a45, 0x17f7d2ad, 0x29524292, 0xb7fe7bee, 0x8fcf3d68, ++ 0x8b90019e, 0xab7177ec, 0xba589f5e, 0xe9ae5f59, 0x7906b8da, 0x8abcf0e3, ++ 0x348732c6, 0xdca2af3c, 0xf480d0be, 0xf40d2079, 0x538c140b, 0xebcc54d9, ++ 0x7f9f6d1a, 0xd80bfe1f, 0x3fc3ef98, 0x44d9bf6f, 0xb7d2fd7a, 0x821a557e, ++ 0x1e976657, 0x1eaa31ff, 0x7a8571ff, 0x7adcdbfc, 0xd34c27fc, 0xd1e1dfe3, ++ 0x42a93fe3, 0xaf64ff8f, 0xf3a9ff1e, 0xf34ff8f5, 0x519ff1e9, 0x567fc7a3, ++ 0x39df1ea3, 0xccf8f5cb, 0xd5d32c0d, 0xe35fe347, 0x77cdf997, 0x7801dbea, ++ 0xa074110d, 0x6f22d1d1, 0x8ccbe50d, 0xdd0ffd6d, 0x00f4d138, 0xee81a376, ++ 0x6e3b034f, 0xf4ee74ab, 0xfc8adc01, 0x21f4d1ac, 0x53bd0ba5, 0x23c805d0, ++ 0xd214fa43, 0xa8e98c2f, 0xfa138cf7, 0xfd6477be, 0x915fe342, 0x2ed23cf2, ++ 0x0daf8d1e, 0x4ec25393, 0xa14e551e, 0x64331c9d, 0xbf468f27, 0x87db3047, ++ 0xe4f5a8f4, 0xcec9ba47, 0x5f0a71e7, 0xdafe8c5d, 0x3e5c925f, 0x069c1302, ++ 0xeb823df3, 0xc48ff181, 0xc6ff244e, 0x7a442c2d, 0x4661bffb, 0x1b760c23, ++ 0x78cb4626, 0xcf4a92af, 0x17b7216a, 0x3b87ff0b, 0xe10137c6, 0x72fb20d5, ++ 0xccdc7052, 0xc49f3a1e, 0xa73a4ede, 0xa28e1b7b, 0x6f181eff, 0xe1effa1f, ++ 0xe9c31fd9, 0x57c6b8e6, 0x46754c3c, 0xa66ab3c0, 0xad7a4854, 0x46794b1c, ++ 0x48943f55, 0x99fd553e, 0xb9d2cb3f, 0xae7e8b3c, 0xb3c1ae5e, 0x5c03e855, ++ 0xae98582f, 0xf30f788a, 0x6e6e0959, 0xfa19e23b, 0x9ff4fee3, 0x73d9ff71, ++ 0x25a65312, 0xc22eb1d2, 0xcf1be233, 0x3e16c91f, 0xcc8ce7cf, 0xc89cf082, ++ 0x3e07a47c, 0xe36b00a0, 0xfde04dfd, 0x7f43ce1d, 0xbb8f2c9a, 0x70f01cb6, ++ 0xf30b8e23, 0x3375659a, 0x2ecb23f4, 0xd5bf4337, 0x2e7bf7b0, 0x06294ba1, ++ 0xc3b78ccb, 0xe68b843f, 0xf414cc0f, 0xb8c6d3b2, 0x3fca2bdf, 0x07032198, ++ 0x23197cc6, 0x52ed8f3f, 0xf27b7336, 0x39b3770d, 0x198cdd62, 0xee7e781d, ++ 0xcc21f4fb, 0x911e3d6f, 0x69780e8f, 0x4fde491c, 0x6579e0cf, 0x4e1457ab, ++ 0xf88afc27, 0xd42bfdd3, 0x91af18e9, 0xa1e53715, 0x8e467de1, 0x4e4def88, ++ 0x1be08fa8, 0x5750b58a, 0x04bd5a36, 0x1a2b3597, 0xe28c6e89, 0x99b5a5de, ++ 0x117dda77, 0xe995897e, 0x09667c7c, 0x130a7b30, 0x7dfc31aa, 0x7ae19332, ++ 0x5c72bb65, 0xe9fee767, 0x5b8458db, 0x6d37a0bd, 0x8c1766be, 0x03eed113, ++ 0xf6f5a741, 0xffce131e, 0x9eed5c83, 0x8a64de93, 0x26ce6d63, 0xe026dff8, ++ 0x8523de6f, 0x5981dcf0, 0xd8a233c1, 0xa61fef4b, 0xf9ad7d02, 0x7c6191ad, ++ 0x573dcd66, 0x687dc21e, 0x83746c4a, 0xfaeecfe5, 0x6fbb62ed, 0x4f6a7804, ++ 0x13394bb3, 0x22b6c7c9, 0xe21b8b1f, 0x87cc2363, 0x765dc1f8, 0xf75dcdfe, ++ 0xbd0ec918, 0xe518dfeb, 0xf0e5b33f, 0x9f043a57, 0x7e26e664, 0x7a6160e4, ++ 0x6c057eb9, 0xd78db010, 0x5f30b0ad, 0xd62fc801, 0x0a537a48, 0xad1d10f3, ++ 0x37441f77, 0xf2707b29, 0xae7c5e3b, 0x8ad9dc2b, 0x4503dbea, 0x69f07a7b, ++ 0x938ed8c5, 0x78824af2, 0x6586cc56, 0x4057ff8c, 0x158fc619, 0x5e1eb1f5, ++ 0x71f5138e, 0xe8fb78d3, 0x7baa40b8, 0x9f1334ae, 0xe457dfd6, 0x64ad3ee3, ++ 0x38ab5cfc, 0xe5f9af1f, 0xf7bfad93, 0x517e44ce, 0x8cdc44ce, 0xd62a3fd7, ++ 0xd1dd6499, 0x97f5879c, 0x111febe9, 0x8eeb0ef5, 0x7fec32d6, 0xa37ebe8c, ++ 0xfac13fe8, 0x07ba21fc, 0xfe3f5325, 0xc63ea243, 0x194f7cfa, 0x7dd07dcf, ++ 0xcdea22df, 0x02b79e56, 0x3f7116ff, 0x8c56bf5e, 0x81ab729f, 0xcee822f9, ++ 0xf9962f39, 0x589ef022, 0x1b2ba899, 0xcf1c3fb1, 0xb56defc5, 0xbeeba797, ++ 0x5fbffad7, 0x597f1f8c, 0xcb7bee9e, 0xf6fa0998, 0x3744593d, 0x9bb80a77, ++ 0xf5744b32, 0xcb5c5afd, 0x38f9f8c1, 0xa699d395, 0x4bce293f, 0x2c9ffd74, ++ 0xee301354, 0x60781c7c, 0x7158e20f, 0xdf1f705b, 0x454bcb69, 0x98ae0d3a, ++ 0x56714746, 0xb2819d03, 0x78bb4f05, 0x557bc4ba, 0xd9450b94, 0xe15ccf4d, ++ 0xa2bd5c8f, 0x803bca82, 0xc4f9f15e, 0x1f3d0f0a, 0xdf0ab287, 0x05fa14fd, ++ 0x40b6c649, 0x0c7e58bf, 0xa3e7c5fa, 0x1f3e2fd0, 0x7eb17e81, 0xe58bf423, ++ 0x583e6087, 0xc1fa107e, 0x3fd003f2, 0x78565b96, 0xc576bca9, 0xbfde7a7c, ++ 0xd5cf47c2, 0x3ea86a2b, 0xbf3a4335, 0xc0c9a93c, 0x71754b60, 0xe48cd4e3, ++ 0x2d7f7ca1, 0x1a6edc6e, 0x989aced9, 0x1cacedc1, 0x7e803de6, 0x8a6fa01e, ++ 0xefad6563, 0x68f68038, 0x27e39792, 0xd5237d6d, 0x38f82a3b, 0x19cc77da, ++ 0xfca59960, 0x83e72378, 0xa3ca2aea, 0x9e78cf18, 0xd4c02b9a, 0x13ee7152, ++ 0xf93094ff, 0x3d4295f3, 0xca8dcd3f, 0x259ed3cb, 0x63c82e42, 0x1cb83d1a, ++ 0x086f34cb, 0x6ead88f3, 0xcf039d1f, 0x261b3b39, 0xecebfb09, 0x38c54ce5, ++ 0xdf5ea540, 0xd12f2c4d, 0xd9f295e9, 0xc9676a06, 0xced759bc, 0xb5d2ace4, ++ 0x773dbaab, 0x91e10b8d, 0x5e61d7c1, 0xc1a592bf, 0x36db8bb8, 0x0ab7b8d2, ++ 0x037ac1bc, 0x2ddfafe4, 0x7d0af5f1, 0x58bb69ea, 0xd93d65af, 0xbc1ce309, ++ 0x30109058, 0xfcfc1f20, 0x1fb40957, 0x40c27a9e, 0x2cf1c2fe, 0x4d7c4068, ++ 0xf58cb104, 0x2a5eb017, 0x155c885f, 0x954cc5ca, 0x0b117cb1, 0xfa099e93, ++ 0x1e0cbcd4, 0x06227a47, 0xbe5948e3, 0x4a9e79a7, 0x02cdf488, 0x4d028f81, ++ 0x44acdcaf, 0xce6edbfb, 0x7f57fb20, 0x738b458e, 0xa695b4ae, 0x3fd11ea2, ++ 0x9c511e4a, 0x174be6eb, 0xd2e31c01, 0x7b53d3e6, 0x186a80ff, 0x8fe75cf1, ++ 0x37ce97ce, 0xd3d23f03, 0xfd708ff9, 0x8f7e8a27, 0x61ac3899, 0xe7ec984c, ++ 0x5f8d46d5, 0x2fc809a8, 0x04eeca86, 0x695d6f92, 0xced91f04, 0x0ad4f3e1, ++ 0xb54dc51f, 0x155fca75, 0xa5af31db, 0xedd1e440, 0xa5c7715a, 0x03f911e5, ++ 0x428eb141, 0xe50871d6, 0xe0d3a141, 0x4b9df6e6, 0x8cc60f67, 0x39e0f569, ++ 0x73027963, 0x78c5ce63, 0x6de74ad6, 0xc4c9bfe5, 0xaf57e47f, 0x15e82a62, ++ 0xc320f6b1, 0x5fad11bc, 0x1fcaec26, 0xda7a3e09, 0x96f34e5a, 0xed3935b3, ++ 0xb4e67d21, 0xbcc76ddd, 0x466dd399, 0xaa3e48fa, 0xbbb42faf, 0x5d01f5df, ++ 0xe713d92e, 0x16c5e9c6, 0x713dd2b6, 0x658976f2, 0x9e0f344a, 0xf5c89707, ++ 0x52e6e356, 0x4808b816, 0x266be0d2, 0x7baaf6b8, 0x87909a0d, 0xa649f576, ++ 0x1aa7e81d, 0x78417087, 0x3824298e, 0xddeb162e, 0xc12562b5, 0xa10c85e9, ++ 0x70696747, 0x1e61f317, 0xb72bde0f, 0x87b34da4, 0xa07cebf5, 0x5807eca8, ++ 0x5323d4df, 0x3c346c1e, 0x31ffc44f, 0x5d101e3e, 0x6ffb9135, 0x202f9e60, ++ 0xef382afd, 0xa32f8424, 0x9bb52cf5, 0xb41e7882, 0x20a8ea5f, 0x81817379, ++ 0xb4b1c645, 0x2be09767, 0x7e761965, 0xc16bb98f, 0x8a2e8ba5, 0x744adf2c, ++ 0xaf169cfd, 0x6e5c29b7, 0xa46a3c79, 0x669d6ddf, 0xedfc887f, 0xc1df3158, ++ 0xf026a87b, 0xeb2b327c, 0x1df98cd9, 0xbf17d9a3, 0xf9a5c8cf, 0x8017d90c, ++ 0x299fa41a, 0x5887ca16, 0xa8bde5a7, 0xebca5587, 0xdfe62785, 0xae9d045b, ++ 0xdfefe9b5, 0x77d62d3c, 0xc063e05a, 0x8c50f5c2, 0x44a714f3, 0xaaefdb9c, ++ 0x8b5a7b26, 0xf1740d0b, 0x5fcd56bc, 0x60482b51, 0xc38720e0, 0xe29936c0, ++ 0xd75db541, 0xbb0efbf0, 0x227ba11f, 0xe9152fa1, 0xafb45aa1, 0xcfdbd66e, ++ 0xd77a768b, 0xedc3aac4, 0x402c25f4, 0x7db46276, 0x7f976d1e, 0x56f42191, ++ 0xb8c62b37, 0xf9f5b1cf, 0x7cc2c46f, 0xce8cb94d, 0xcfc8660d, 0xa0ac3dd3, ++ 0x3de2b675, 0xdf88ac8b, 0xf78d1233, 0xe1132ca2, 0xd7869777, 0xffa256b1, ++ 0xfef8535d, 0xe4e075df, 0x9fa16375, 0xba48e4df, 0xe4dfd23c, 0x058e0918, ++ 0x678760e8, 0x23156307, 0x65250de5, 0xcf8fce1a, 0xefbfa65d, 0xf7b3bebf, ++ 0xf895388d, 0xe226625d, 0xc4bf8df1, 0x08fed117, 0xd7f4fdd3, 0xf993bfe0, ++ 0x7f7f31bc, 0x058be1b7, 0x90507491, 0xc17d50a9, 0x5cabcef9, 0x4513af3f, ++ 0xcd5ca4ef, 0x133635e7, 0x68e860e5, 0xb65e644a, 0xa3ddaf36, 0xed3d0fdc, ++ 0x4d33e77c, 0xe0220f2f, 0x33e71534, 0x9b769c1a, 0xb5cf9e46, 0xfcbf7c99, ++ 0xefbf20e2, 0x74bd7860, 0xb533f77e, 0xe27be7e9, 0x911b9ed9, 0xaf7cc35d, ++ 0xbbf6bc45, 0x062852fa, 0x31d7e025, 0x64e7d059, 0x64dc77c1, 0x7bff3113, ++ 0xa98f2953, 0xfef5e143, 0x95c125c4, 0x03eebf40, 0x1e50728b, 0xe9988ed8, ++ 0x68ff1a9e, 0x1d626d79, 0x11a5d3bb, 0x933ab0e1, 0xb781fdd3, 0x07bfa8ab, ++ 0xe43335de, 0xfee24d07, 0x1dec07a6, 0x547fbc16, 0x4b962383, 0x8537e9e0, ++ 0x3cb1b897, 0xb545b4f9, 0x819e308e, 0xd450f78f, 0xd3c6d1be, 0x2cc93f9e, ++ 0x3a5072e4, 0xf6be6328, 0x43bd9743, 0x343d04f7, 0xfb9e2159, 0x7d7fc30f, ++ 0xef43fc14, 0xe9c75ca4, 0xff0827e5, 0xf8a3e906, 0x2fd9401f, 0x84577f85, ++ 0x68f933f0, 0xccf7fefd, 0x0e1a5dac, 0xbf411aa7, 0xf5b4fada, 0x4db6f36b, ++ 0xf2f9445f, 0xf89c0f88, 0x935ed16a, 0xee420913, 0x4e48bae1, 0x7cf0a65c, ++ 0xe10a29f7, 0x9769a1f5, 0xdd84f9d0, 0xbe1d3e22, 0xbde234d8, 0x7012bff2, ++ 0x7fece07b, 0x197da0f5, 0xb9d232e8, 0x5de7b070, 0xf91d03d7, 0x3dd0ab7f, ++ 0x154f40b3, 0x81cdef78, 0xa3c64fb7, 0xc991d75e, 0xa64759f9, 0xb387cb89, ++ 0x1b9d0572, 0x5db4fb78, 0xddffa08e, 0x4bd0b299, 0x3cf07a7a, 0x9e1286c0, ++ 0x7a156cff, 0xbeedf580, 0x75bf9c1a, 0xa5987fda, 0x9edb3908, 0x36efa669, ++ 0x6e29c298, 0x2ddfcfe8, 0x03e910b3, 0xd77f74bd, 0x3b2779e0, 0x64c34387, ++ 0x78453010, 0xd7bf2a0f, 0xcaa6776b, 0xdef307e7, 0xc763ef0b, 0x6357b69f, ++ 0x2f1864fd, 0x9b7be86f, 0x7633e39d, 0xe347bf0a, 0x6f7ecba1, 0x12c37bc7, ++ 0xdff74624, 0x75196516, 0xd546fc7c, 0xe9edfa20, 0x602dfd41, 0xb0ff2857, ++ 0x05a77423, 0x5f6d7af5, 0x6a657358, 0xebdc56b7, 0x615a76ba, 0x681fcf10, ++ 0xcb273c74, 0xcdd23af7, 0xcf17d806, 0xe3d5de93, 0xb1f0499d, 0xe69e6317, ++ 0xdd0f5273, 0x62981257, 0x297ca3b2, 0xfb741834, 0xd38b252d, 0xbd04f68d, ++ 0x1f9df494, 0xe4d65a0b, 0x616edcbd, 0xcbe9be78, 0x501273b3, 0x34b3952f, ++ 0x476dcf3d, 0x9d697e38, 0xc7e1fa47, 0x47d75baf, 0xe7b5ffc6, 0xe6f02b47, ++ 0x62f2a1fe, 0xb63677b7, 0x6b7cc25f, 0xd25d1f50, 0x7bceeb26, 0xf9f62c7f, ++ 0x2cb1b3e2, 0x2fd7a114, 0x9d33769e, 0x367c595b, 0x4f40859e, 0x339c58fa, ++ 0x05e458fa, 0xe0fb129d, 0xcb8cf15b, 0xe97e4f3a, 0x8f37928e, 0x5553f7ff, ++ 0x429e5f9c, 0xbd4bd7b8, 0x1b73e426, 0x9d0bf92e, 0xec08f817, 0x77c150f4, ++ 0x858933ad, 0x6c19c622, 0xeb42d677, 0xa70bc219, 0x5af5a1bb, 0x811f0e09, ++ 0x70ddfffd, 0x71c1d0cc, 0x1d3cffa8, 0x5ff7871c, 0xb47fe340, 0xfa7bf0a2, ++ 0xff4a389f, 0x43fe6eaa, 0x71a18efd, 0x7aad5ffb, 0xcbf60e3a, 0x5b55a1ab, ++ 0xb6fcc65f, 0x37ba66fd, 0x9476759d, 0xe7a639d1, 0xbb6f9d18, 0x1f57ff7b, ++ 0xdddade60, 0x1c6e4c3b, 0x5e18c063, 0x3e411ee0, 0x00f6618c, 0x3da423de, ++ 0x69f2b2b3, 0xb7bf457f, 0xe63b4128, 0x150a59a7, 0xf5154afb, 0x2ae09eb2, ++ 0x5b2637b4, 0xfe693f88, 0xafdfad71, 0x1ced6432, 0xed6bed2d, 0xe29788be, ++ 0xd059257c, 0x5ab1a7ff, 0x0360529e, 0x7f6ac9fa, 0x3e79db26, 0x10ec83b4, ++ 0x30ad7fcd, 0xcd1bf91f, 0xff30cbcc, 0x77c73dbf, 0xfbf41671, 0xe8036053, ++ 0xd82f96cf, 0x9dfcc3e9, 0xf7bd8507, 0xcb8f4c60, 0xaeefc11d, 0x8fce52ce, ++ 0xe8a35b6e, 0x9f1fca76, 0x7339710a, 0x5ea3ce35, 0x5565f9ee, 0xf61de62e, ++ 0x5482fb8a, 0x27fdf913, 0x8cf741bf, 0x7af66955, 0x3b7c7473, 0xaffa81cb, ++ 0xc78f6fe6, 0x11d423fc, 0xa6fbf036, 0xb978e3aa, 0x944937fa, 0x4b760de7, ++ 0x9ff2115c, 0xdf9bb2dd, 0xb827672f, 0x186b149e, 0x46c86cb0, 0xb8080e78, ++ 0x8d7aec9e, 0xd93bb3ee, 0x5ff0963c, 0x74bdcafd, 0x74eed51f, 0xba067f2e, ++ 0xaa7f246d, 0xbc52eecd, 0x3a776d2f, 0x943b33d7, 0x84497c50, 0xb336b9de, ++ 0xe7eaf88c, 0xa80d63cd, 0x5d706b97, 0xd4e5c596, 0x985fc106, 0xbcc52e12, ++ 0x8727cffd, 0x6ff2477e, 0x3efd0c4f, 0x57ef618d, 0xdeaf74a5, 0x47dd3306, ++ 0xfc77b65e, 0x5f50f9a6, 0xbca0605f, 0x18dec34c, 0x7589cf9a, 0xfc1f5efc, ++ 0xfd74e516, 0x5dfa0cde, 0x30b8ea9d, 0xc7d555e5, 0xfe300bba, 0x52f7bd51, ++ 0xd8fc4fba, 0x91b3e383, 0x564d1e5f, 0xd53ee9b3, 0xb0e80107, 0xe3dda3ee, ++ 0xa996fbf8, 0xb6ce5e74, 0x9237ce21, 0x239342ff, 0xed06f7d1, 0xefee2f4e, ++ 0xb78cf844, 0xf94077b8, 0xe3cdc923, 0x73c2875f, 0xb8af8a55, 0xb560dce9, ++ 0xe86fb3f5, 0x0fb6af9e, 0xdef4656f, 0xd9ab7449, 0x55e3d161, 0xdbb3390b, ++ 0xbf805e14, 0x5abd546f, 0xf3c4ddc0, 0xc50daabf, 0x1a5fbbf4, 0xdd4437dc, ++ 0xf82ed9af, 0xf63cf6af, 0x94f742b6, 0xc6cffc81, 0xfb63e7fc, 0xc76744cd, ++ 0x73a44c36, 0xd578dab2, 0xec3b1300, 0xea89a3cb, 0x2eebc424, 0x57aaafc1, ++ 0x7b52fb73, 0x58d86d5f, 0x770e7881, 0x32df94cb, 0x63c70f60, 0xa76b437c, ++ 0xd3d70795, 0xf4efd325, 0x403f4eec, 0x627a06f8, 0x57864f48, 0xfd5f246c, ++ 0x207798af, 0xcc9f3f3e, 0xb7487102, 0x3ddff2ef, 0x4cdbb57a, 0x11c0ef7a, ++ 0xbb0e976e, 0xce1ac9b7, 0xfd0b7bc6, 0x1f1064af, 0x6f0ac81b, 0x0c727ae7, ++ 0xb0edcfbf, 0x8388aa6f, 0xd07b89a5, 0x3b3f50d2, 0x42131dd3, 0x149e0cfd, ++ 0x9db008d7, 0x3fbf7a2e, 0x06dfa18e, 0x3852419e, 0xfa2e3da5, 0x2ad60bbd, ++ 0xefa1efbe, 0x8df6ceef, 0x777cbe43, 0xc56ff43e, 0xdda8fbef, 0x85df3c99, ++ 0x74bf8658, 0xf53a5e31, 0xa1cbe59b, 0x1769d2f7, 0x56871dff, 0xf543df51, ++ 0x2a6fb37e, 0x1b7de3ad, 0x9d611f6b, 0xd7df7be7, 0x4449598b, 0x01bcdabf, ++ 0x45efa4ce, 0x2ca3e5c3, 0x0f9df883, 0xba688f0e, 0xf7e7c41c, 0x26fd0fcc, ++ 0x9bb45e74, 0x78dd71e3, 0x2d23e713, 0x65af4913, 0x3cbab14d, 0xfcdd95a2, ++ 0x83ff77fc, 0x80f3c236, 0xca18f3d1, 0x2361f0a3, 0x8169f7e3, 0x85fe8046, ++ 0x97ef2369, 0x715e44cf, 0x37cf0b6d, 0x8f99ecfa, 0xf15a17b3, 0xbac7e45c, ++ 0x9f9a9173, 0x47893a0f, 0xadd58a3f, 0x711557c6, 0xf9a65b3d, 0xda13dff1, ++ 0xf7e95460, 0x8e0f029e, 0x31c23f27, 0x7e97ba93, 0x05dd6a97, 0x16aba406, ++ 0x813de737, 0xed3ebe56, 0xbeed1e9e, 0x8cf8689d, 0xbfe7cecd, 0xb77cc283, ++ 0x47cddde1, 0x82229a99, 0x58ef7468, 0x400bfe0d, 0xe0c6335f, 0xd0fe2189, ++ 0xf8617248, 0xefa65efd, 0xffa83df9, 0x1cf8f2db, 0x716ceb46, 0xae51e207, ++ 0xf6e7627e, 0x45fe9d1e, 0x75f32eb9, 0x69aa5dd2, 0x17bdaf28, 0x3d532764, ++ 0x244fc3f1, 0xb9f1af5e, 0x7a47eb61, 0x1db07ec1, 0x3b3d35f4, 0xb827db97, ++ 0x347ef1e9, 0xbe613016, 0xfc9f269a, 0x73c06292, 0x350e7dbb, 0xafb1e91e, ++ 0xed113f25, 0x9a872ae5, 0x17411252, 0xce8c83fe, 0xcf78aaab, 0x5dfc54f1, ++ 0xf424cf0b, 0xd44eedd7, 0xe7a20bfb, 0xde8cfcf3, 0x57f59105, 0x77397366, ++ 0xf7b73643, 0x61336456, 0x8dc3453f, 0xc0a97de3, 0x77db8b7b, 0x518fd939, ++ 0x4e6e96ed, 0xf510f410, 0x7fe5f5be, 0x6d907ca7, 0x5ce9fbfa, 0x4fbc7c39, ++ 0xd202990e, 0xa58cf885, 0x8d9adefc, 0xbcd5cf9c, 0x0f705955, 0xeeb9d32f, ++ 0xd3f7ed19, 0xda2c80ef, 0x7180ab31, 0xd07845be, 0xb65171e8, 0xb8f500a7, ++ 0x8ed916f0, 0xb366a2fb, 0x5169f34c, 0xe05b2d5a, 0x46cdf1fd, 0xc46aefd2, ++ 0xfa678e7c, 0x0a6f09e2, 0xf7004c53, 0x9e2f8ae3, 0xe22dd7f4, 0xd6a24ef7, ++ 0x51deed01, 0x8f80464a, 0xe099e385, 0x1d023f93, 0x9e10361c, 0xd1efe116, ++ 0x25da3ce1, 0xcf1e4bf2, 0xe586ddf2, 0xe9dbb03e, 0x5ad6e1de, 0x1a2347ba, ++ 0x3e2dc7de, 0x62a5cfa2, 0xa33c1a3d, 0x39e0d1c7, 0x7d44f080, 0x9256d0e9, ++ 0x6547fe7b, 0xa07658a4, 0xd3d914eb, 0x7d67ba33, 0xdfbe2970, 0x8a8b7a08, ++ 0x77ef3672, 0x6b9ca0b7, 0x5477e996, 0x53f3baaa, 0x46bc9458, 0xb7eab1bb, ++ 0x110de2f3, 0x4da5b272, 0xcb49f8a6, 0x8bf1b998, 0xebc9fda9, 0xaa8ebe90, ++ 0x889294ee, 0xc1ecc176, 0x5f0e8178, 0x1aff1bd5, 0xacd4e38f, 0x34bad237, ++ 0x9cc00cbc, 0xc6b6ff88, 0x2068bf91, 0x6afd4c33, 0x6fa41a78, 0x4f4683c4, ++ 0xb650eed0, 0x0649e45d, 0xe5f51f88, 0x23dd4afa, 0x4792c9d0, 0x6fec5c60, ++ 0x4dee8db3, 0x3571d73c, 0x5be20c78, 0x232a6bec, 0x92e7b71e, 0x5870dbff, ++ 0xa3eb64a1, 0x50c3b0ad, 0x817905cf, 0x296a86fe, 0x5fdd01fc, 0xfba66dd9, ++ 0xde37ab5f, 0x578e1b7e, 0xc06cc47d, 0x57fdbefa, 0x4579a24e, 0x94e015e1, ++ 0x0fbd123d, 0xddb386e4, 0x7d03f011, 0xb6b7f682, 0xd379889e, 0xa29ec03c, ++ 0x7206507b, 0x7c119f01, 0xae6ccde0, 0xbb7b4177, 0xdf9be889, 0x5eb833c3, ++ 0xed7ad47b, 0x877deb51, 0xb7337d11, 0xe8b3d68f, 0xdf01b33d, 0x9af87a2f, ++ 0xf5aff402, 0xeb499bad, 0x4cf44bea, 0x97d5fdc2, 0xc08ffd0d, 0x0c3d172f, ++ 0x8efa2ceb, 0x10c6b675, 0x675d46be, 0xfb3b7862, 0x09f6758e, 0xf9d6d43a, ++ 0x63c6a291, 0x9f7fb35e, 0xe25fd0cc, 0xb86ef2cf, 0xf7e99794, 0x0f22fca9, ++ 0x8e31bfc0, 0xbbfb1ef2, 0x1ae8bdf8, 0xcef1801f, 0x440c1e91, 0xea657d0f, ++ 0x5f4869a6, 0xcc76ca0f, 0x775beda3, 0xf7f0efd1, 0xc836fac3, 0xfa13d476, ++ 0x80fc38ca, 0xeedc901f, 0x475ef6cb, 0xfa46fde5, 0xad63ac1d, 0x9d23fd7f, ++ 0xd236ef3f, 0xe40efaef, 0xc7cc377a, 0xf917cc32, 0x46e5c01a, 0x691aafae, ++ 0x8fcd2dfd, 0x607d6336, 0x5e7485f3, 0xd67cb862, 0xbd66b9c3, 0x4c87dbac, ++ 0xff3c6951, 0x7f7419c3, 0xe0670684, 0x0f6805b0, 0xf2c0f069, 0xe0860bbc, ++ 0xade717e2, 0xf7e02f51, 0x867e092f, 0x72e3c9f0, 0x208dcf02, 0x2bf3c31f, ++ 0x68abc9a3, 0x47ad13fe, 0x2348e4e5, 0xa8daabca, 0x165ca5df, 0x8a3dbe55, ++ 0xd545d46f, 0x83d547d7, 0x246ebe7c, 0x3943f3ff, 0x2556be7a, 0x41f9a8e0, ++ 0xe7e41e07, 0xd514ab9c, 0xf3cff684, 0xae7cb833, 0x72e59856, 0x3cfc97da, ++ 0x9ac2954c, 0xdef825cc, 0x93b48a6d, 0x7326bfa0, 0x39639422, 0x1576821f, ++ 0xc6b288a6, 0x5cf9b56f, 0xb1f7c39b, 0xfd87fcf6, 0xc6a39502, 0x19cdae2b, ++ 0x2253ae21, 0x6deafde7, 0xc9f6afb4, 0xdffa5764, 0x7d87f2e2, 0xb3d36a7d, ++ 0x36d7bc4e, 0xb4c1f29f, 0x71c347f5, 0x3c54f3a0, 0xff60defe, 0x679d1321, ++ 0x2a4aeaae, 0x312bfb23, 0xabdc223c, 0xfeb4fac5, 0xf8de95fa, 0x337a9139, ++ 0xfc8f8deb, 0xceaadc5d, 0x9ed02b53, 0xe405f805, 0xac7e3e08, 0xed0cb93b, ++ 0xa75feaca, 0xdb79e197, 0xdd9a3935, 0x3d6cfeaf, 0x667d9bee, 0xbff447f2, ++ 0xdf80df35, 0x2355bff7, 0xfdd3779e, 0x1d1ffd71, 0xe3f1c6cb, 0x05fbfa0d, ++ 0x76e1cdee, 0xc3e1b549, 0xff91d3ed, 0xbb9a94bf, 0x5cdfc23a, 0x7b21286d, ++ 0x786359f8, 0xf41bce01, 0xbbcc66fc, 0x9359fad4, 0x8d7cf2a3, 0x476f1f7d, ++ 0x436c70fe, 0x95b20956, 0xc8e37dfe, 0x723fedfe, 0xec9d8151, 0xf237348f, ++ 0xea8d6785, 0xb15edcdd, 0x6bdf71b9, 0x1838e1fd, 0x37dfec67, 0x05fd14b5, ++ 0x7cf847fd, 0x03fe4ca1, 0xfcc01768, 0x78dfad49, 0xe610fa83, 0x1b5fb381, ++ 0xf3b88ec9, 0xcc54fc9b, 0x8d378a6b, 0xbb419f1c, 0xbd079f41, 0xddadd68a, ++ 0x576d1de7, 0x9e5e622c, 0x7f651b67, 0x4782f769, 0xac3589db, 0x34af4d75, ++ 0x45045edc, 0x114812dc, 0x7f4e0fbf, 0x6fef241d, 0x59adf5df, 0x40724f7f, ++ 0xf10b4fec, 0x8fd82ae3, 0x14dfc8eb, 0xa05eff24, 0xee311e45, 0xc787307a, ++ 0xfb8b1fb7, 0x08de82db, 0x30351ebc, 0x3d7005c5, 0x5716626a, 0xe37648c9, ++ 0xcfb46c99, 0x1f8bdb86, 0x3aa31f93, 0x36329ef2, 0x5a3c6edc, 0x832d6c16, ++ 0x275d1d79, 0x9c18efd3, 0xfd18ddaf, 0x0d3bf6bd, 0xf13d0baf, 0x26cce628, ++ 0xacdd977e, 0xcf06af9f, 0x19fbf118, 0x94ffedd1, 0xc288edc3, 0xc1e6646f, ++ 0xa46ddf7d, 0xed713df3, 0x82dd37a7, 0xb465d9f4, 0x5f14aae7, 0x6079dfa1, ++ 0x0fca64fb, 0x163ae81c, 0xcce50cbf, 0x98e88bbe, 0xb39da0d9, 0x4938a64f, ++ 0x14a9e77f, 0x3f40a78c, 0x77f63714, 0xfa46ea3f, 0xfd1e6d1d, 0xc5f9f239, ++ 0xf1513d6b, 0xee3f1137, 0x805e3f6f, 0x60f81dfc, 0xfec1f23f, 0xfdc5af82, ++ 0x48a5bd5e, 0xd23f307f, 0x678207df, 0x74b4bf48, 0x9bde23c9, 0xe774c945, ++ 0xbd0abf33, 0xc3e616df, 0xf34329d4, 0x26c3506c, 0x1fffb394, 0x97541322, ++ 0x00008000, 0x00088b1f, 0x00000000, 0x7dcdff00, 0xd5547c09, 0xb3b9ffbd, ++ 0x24992665, 0x21258493, 0x02564c24, 0x26c27124, 0x04b0ea2a, 0x55869151, ++ 0x243788d0, 0xb41d9081, 0x9b4b697d, 0x8b520081, 0x4146bc35, 0xa0503a8b, ++ 0x2a17d168, 0x1bec5628, 0x96eb1140, 0x6d6d6ad6, 0xb0b8a269, 0x68fad0c7, ++ 0xdfffabeb, 0x49ee77f7, 0x69410ee6, 0xcf9f7bdf, 0xc39fad3f, 0xb3dcf7b9, ++ 0xdbf3b6fc, 0xce7399ce, 0x857142b8, 0x8cff3fa0, 0x2c4241a2, 0x54bd3fc6, ++ 0x219f281e, 0xfa9884e2, 0xd76ae55c, 0xb5ce2158, 0x7a28be6a, 0x2ac0715e, ++ 0x319400c4, 0xbd066f41, 0x7ae6ee1f, 0x60d623f9, 0x59a7d514, 0x80b3be27, ++ 0xcfbd2fda, 0xaea28bea, 0xc6fd6e0e, 0x7f7a763b, 0xe05d8b6e, 0x04238d3d, ++ 0xc84cb38d, 0x6e0765bf, 0x38d1a13e, 0xebb85f4b, 0xfa59c610, 0x17e3e680, ++ 0xfa0752d6, 0x1349b65d, 0xbff51a49, 0xa77efede, 0x05f37e53, 0x6ad957fd, ++ 0x9d112fae, 0xb534ac8b, 0xcfcd9ba5, 0xaf4ce885, 0xf6ab7ea6, 0xc5ee7947, ++ 0xf7c8c178, 0xf348bc42, 0x9dfe3069, 0xb6e1b397, 0x6f3ed443, 0x70e183ab, ++ 0x474425d6, 0x75b0bd3e, 0x4328120e, 0xb125e99d, 0x0fb9fcf4, 0x6f54bdd3, ++ 0xe57ff9f8, 0xf817f9e2, 0x52e2febb, 0xf01d881c, 0x85108c51, 0x917c4d5e, ++ 0xf7fefd49, 0xfd2599f9, 0x5a86d7b4, 0xc4281884, 0x88607b2e, 0xda1fde8f, ++ 0x277a59fa, 0xd39ee795, 0x5fdc7987, 0xb808bfd2, 0x4328c92c, 0x6c72812e, ++ 0x8226e7bb, 0xec2fc35b, 0x6d86debc, 0xa36f66eb, 0x3b79ebba, 0x39ea80cd, ++ 0xe62092ee, 0xbe03c2fd, 0x5d7eb0ca, 0x4ed8d156, 0x589a5df5, 0x2a38e5c0, ++ 0x8d2f31f3, 0x30eaf5e7, 0xd83aee59, 0x9fa73333, 0xcc3abcf9, 0xb438c42e, ++ 0x1d6e5c17, 0x978b7256, 0x025b47da, 0x680b2271, 0x10077bf7, 0xbe83359c, ++ 0x351a9a5a, 0xad164f3c, 0xed150e5c, 0x84223e5c, 0xe17b46ee, 0x42ce00f3, ++ 0x7e0025a4, 0xe18be056, 0xfd016299, 0xe1c0dd7c, 0xd690e8bd, 0xc1104817, ++ 0xeb6ff41d, 0xc6b0a756, 0x9d10e10b, 0xb628f871, 0xc3fdf660, 0x37fdbde8, ++ 0xf4468b56, 0xf8534d67, 0xad0479f4, 0xb9ee2fe3, 0x3bf8e1f1, 0xe9e2daf8, ++ 0x9f6eafe8, 0x7f514455, 0x45daf667, 0xddf68dc8, 0xbfb3b40e, 0xc64767f6, ++ 0x1343cc58, 0x068eb439, 0xc379e3aa, 0x183f9b44, 0x5ee59706, 0xccabc33b, ++ 0x59e5cb9b, 0x0ce8ff9b, 0x67acf7ea, 0x45e023b1, 0x05d3153f, 0x5e4f63f5, ++ 0x0ebcc0ec, 0x99d936be, 0xd825bc01, 0x1dd66f98, 0x7876e350, 0xe59e7fd0, ++ 0xf4499ed7, 0x4d9c7bbe, 0x1fc7a36c, 0x00dee4bf, 0xfde355be, 0xf3f12bdc, ++ 0x82513361, 0xe579efa3, 0xf0d3b9d8, 0xafa112fd, 0x692d1d03, 0x18508ab3, ++ 0x976c7ffd, 0x10bcaef8, 0x6149422d, 0xe6cf25df, 0x885e5575, 0xd431a113, ++ 0x7ddb25ce, 0x62e92b1c, 0x8fde3193, 0xffbe1251, 0x766b28c3, 0xc3c73cb9, ++ 0x4f6baffa, 0xf61bd530, 0xe78e78a7, 0xf06bd5f5, 0x5ba0148f, 0x5ad78138, ++ 0x3ccf0f83, 0x909ddbf2, 0xbe9a5d45, 0xa7547409, 0x429b4e75, 0xee4bac43, ++ 0xac6ee871, 0xb94223d3, 0x24ceb65f, 0xa71b0a11, 0x2705ddb7, 0x6e0fa7af, ++ 0xdf475e5e, 0x870cdd7a, 0xbf939b0f, 0x26a98e02, 0x9ff5f638, 0xc5e38269, ++ 0xf8f2e7fd, 0x7de7361f, 0x2ea3ff45, 0x34d7bfd1, 0xb37ebeff, 0xf935dc79, ++ 0x74471116, 0xa8dde6b5, 0x939b3320, 0x885e37fe, 0xd6ef8328, 0xbd3aa684, ++ 0x406ff0fd, 0x13154d4c, 0xeb5efde8, 0x19f1d074, 0xf80f62cf, 0x72409edc, ++ 0xdefa4ae9, 0x0d7e9fee, 0x90951bf5, 0xfdfa0498, 0xaf166f4f, 0x4684b3eb, ++ 0xd2cfe3a6, 0x2c035b46, 0x504b1bdf, 0xc2b4335f, 0xbad9bcca, 0x837de589, ++ 0xfb1f8e53, 0xf8253102, 0x30672ae7, 0x3b9fda87, 0x9ca796f0, 0xa69599c6, ++ 0xae3bc6ff, 0xe3b13e6f, 0xb3c0145e, 0x830fafd8, 0x43c7b81c, 0x40fccb7c, ++ 0x75eb4d7c, 0xd763fa68, 0xdf883f10, 0x541d8945, 0x87d2e67c, 0xf8f8c27b, ++ 0xf3c1d7b8, 0x85486e23, 0x36880c5c, 0x9ff61b2e, 0x897b3867, 0xf52eb17f, ++ 0x337441be, 0x62d7c1dc, 0xe6d26830, 0xf5fbf7e5, 0x7d0525e1, 0x37fd50f3, ++ 0x580eecbc, 0x5ea2ff88, 0xc038eff8, 0x7bad9cf3, 0xf6ca8fa6, 0x7098d603, ++ 0xe0ddfef8, 0x7f69c993, 0xe7a4ec2e, 0xe48ef8f5, 0x517e37d3, 0xa7f21c33, ++ 0x10bbaa3e, 0x8bf43ef3, 0xde4217bf, 0xcd42f67f, 0x45df3c30, 0x9cbfb1ed, ++ 0xfbd77473, 0x16cbfac2, 0x4265809e, 0x0367f95f, 0x77cf910f, 0x0432d0bd, ++ 0x624dd8f3, 0x38d22448, 0x8e63d54d, 0xfc1c8127, 0x119c843f, 0x60765f24, ++ 0xc73fdb7f, 0xff52b90a, 0x543110b6, 0xdc9cfb1f, 0x89a6c7df, 0x53f085a0, ++ 0x0bdbc2ff, 0x71faaf80, 0x96858f0e, 0x11d45d12, 0xa3ef4d5c, 0x1a3d39c7, ++ 0xaa6bffb5, 0x7d81df1c, 0x17df0b3d, 0xf96f0127, 0xfcf16724, 0x5b07965f, ++ 0xe841e422, 0x69bbf5d7, 0xe76b3abc, 0x9201c84c, 0x8832430b, 0xff5fea5e, ++ 0x5ef91bf3, 0x041ee8b4, 0xa862fcfc, 0xa32df71c, 0xfa19199f, 0x9dd3b430, ++ 0x495df79d, 0x4fcde6ed, 0xae09d749, 0x43a11665, 0x0419898e, 0x5740ab94, ++ 0x0bb30525, 0x575fdbfa, 0x5e7b5cb3, 0x21c075d3, 0x61f4e290, 0x2a95199f, ++ 0x5704299c, 0x9ccc1c91, 0x6616e34d, 0x237a0c58, 0x8f79a3ae, 0xe4f8d634, ++ 0x0915f690, 0x13059fbc, 0xecff4741, 0xf86757b8, 0xec0c65c7, 0xfcf6ff6b, ++ 0x7ef40bdb, 0xce1417f8, 0x2fb47078, 0xebbb3cc7, 0x846dbedc, 0x15e0dfbf, ++ 0xf9e3f77d, 0xe92b2151, 0xeeece759, 0xdfd11af5, 0x8e8b31bb, 0xec78240c, ++ 0x0053eb73, 0xdeb7059f, 0xed750eb8, 0x05779250, 0x73acb9e8, 0x73e9f03c, ++ 0x7de037e9, 0x361f53ad, 0x26789688, 0x8f1e1f4d, 0x4924b8cd, 0x149449e2, ++ 0x7f3bf494, 0x4d329f39, 0xe9665f8e, 0x0d4af478, 0x0b3eadfb, 0x1d5ba9eb, ++ 0x5b4ef52f, 0xafe678c7, 0xbfb90335, 0xd5510e33, 0x24faefde, 0xeb198e3c, ++ 0xd7176839, 0x1e75a05d, 0x6bef18dc, 0xdc5779a1, 0x06a2eb73, 0x252d2b2a, ++ 0xd3564283, 0xf9e4effc, 0xa586ca07, 0xc675fe90, 0xc9bfcc6e, 0x93cdbf98, ++ 0x91d7ce1b, 0xfa516ff3, 0xe0b477c5, 0x18830c8e, 0x206cfea9, 0xd52f7821, ++ 0x7fe72ca3, 0x72fb0733, 0x7d87c581, 0xf1344b79, 0xde2168d8, 0x08f9e634, ++ 0x91339ff1, 0xf3c7af9f, 0x7df968e4, 0x609683f2, 0x325f7d0b, 0xd7c639f9, ++ 0x3eddeb8f, 0x26558d2b, 0xfcd17048, 0x81df85ca, 0xe9387ff9, 0xd2742fef, ++ 0xa193beba, 0x771d6137, 0x7fd25926, 0x47d0f3c3, 0x347e82cd, 0x4be3ae51, ++ 0xc75e43f4, 0xb3b1e16c, 0x58362512, 0xf6cc1fb0, 0x6a54a5c8, 0x08e64f92, ++ 0xcde31dbf, 0xfbb73a13, 0x1f8759f5, 0x09affffa, 0x7de682e7, 0xf3f008ab, ++ 0xe5c82285, 0xedc422ed, 0x5c9d10ef, 0x3a26f057, 0xa48073b9, 0x5b078f93, ++ 0x03f7fe19, 0x298abfdf, 0x75a26b4c, 0x3c34dacc, 0xb6cfa047, 0xaf9f0c81, ++ 0x832cf79a, 0x378f887e, 0x4b9e3e2b, 0x29beccfd, 0x0ea78f82, 0xf9ccf854, ++ 0xe8ea7e32, 0xdc77b5e9, 0x1b870429, 0xe0de940c, 0x477b61af, 0x57ef0f08, ++ 0xb7f8335f, 0x0316ead8, 0x5e1d3f08, 0x17306fb2, 0x18faf6bf, 0x649f4faa, ++ 0x3cd2f715, 0x78255e5e, 0xc8b97b3f, 0x315a641a, 0x46999bec, 0xcd2633bf, ++ 0xed4f1359, 0x39de7da6, 0xf4e54436, 0x847f64a1, 0x071bbbc9, 0x40935d6c, ++ 0xe6d94de5, 0x0e8b37e7, 0x233ae01b, 0xccaf6cdf, 0x776e6b1c, 0x0e426310, ++ 0xf82b5689, 0xb48640e8, 0x3148c437, 0xb7c60bf2, 0xa7af84b0, 0xc779c667, ++ 0xf9c79a39, 0xe030fd0c, 0x0f96e2b9, 0xc04c8917, 0x063ebc4d, 0x721bc0fb, ++ 0x1e93ef5d, 0x8e281449, 0x418ed337, 0xa447d67a, 0x09fea16f, 0x4f2845e9, ++ 0x3cb97b36, 0xde0c7a4d, 0x71f66d9f, 0xc966707d, 0xf177e86b, 0xc06d4ffa, ++ 0x092e3dcf, 0xd6f6aaef, 0xf5569869, 0x2823f6fe, 0xd325422b, 0x392eddb0, ++ 0xe50478da, 0x5676bd3d, 0x2ced93a3, 0x1977de63, 0xec577a74, 0x080b9bec, ++ 0x673d77ce, 0x6d3d71f5, 0x065b9cf6, 0xfae76ea0, 0xeea8e8a5, 0xe90cd102, ++ 0xff56f54b, 0x7fcbcc31, 0x1248eba0, 0xe6e3efad, 0x13ef3c09, 0xf79e7ecd, ++ 0x5ce9e6a9, 0x8e4b32fa, 0x29f13b73, 0xecb799eb, 0x52a5b2ee, 0xe6bf62fb, ++ 0xe75edf07, 0xf120c117, 0xdcbb66df, 0x7ed3360f, 0x549e3e00, 0xbb91fb30, ++ 0x7eb5e405, 0xbbcfdf16, 0xc6315969, 0xcca13999, 0x7eb77686, 0x4652442e, ++ 0x157e9d1f, 0xd7f5abdd, 0xf33b7819, 0x78e18d0b, 0x1afde2c6, 0x2fc09ef4, ++ 0xf77fbcad, 0xd4aa68d8, 0x23bbcf7f, 0x85a20183, 0x06b2fb15, 0x61587f43, ++ 0x0c4e0ef7, 0x114e87d3, 0xbe98453e, 0x7fc9ea7c, 0xdfc3d64b, 0xf67fb627, ++ 0x3fb1c87b, 0x9a46394a, 0x430f47cc, 0xf64d0dce, 0x6b3c8ec1, 0xdfa409d8, ++ 0xabbf60c5, 0x71df1077, 0xfa851f5d, 0x677168a9, 0x3fc7d509, 0x7c193a95, ++ 0x82a0f184, 0xfb953929, 0x6fcca6d4, 0xdbc6fb7b, 0xfbf95ed5, 0x267ea987, ++ 0x69d80968, 0xda233a3f, 0xeb1cfecf, 0x41f6eeda, 0x6cd3cb9f, 0xd74c4dd1, ++ 0x3cdbe641, 0x226b6bcd, 0x53f8f439, 0x91f90c8f, 0xc42c7ec0, 0xfcff7a04, ++ 0x539618c6, 0xc77ddbcf, 0x23fdf09a, 0xfc9ffbf2, 0xefef9be0, 0xdd5f7947, ++ 0xbfa26fe8, 0xa7ee44cc, 0x8d97dfe2, 0xff69bac4, 0xdfd42916, 0x42d59f4f, ++ 0x0a2142ae, 0x4eae0eda, 0xb15cf9a1, 0x8432cba5, 0x5aeda2ca, 0x6951ca0b, ++ 0xdf628fd3, 0x32f4cc2c, 0xceecc65e, 0xbd82a6b0, 0x7f7f0486, 0xe6ebef3d, ++ 0xedbf3efd, 0x4443c9d3, 0x523fbedf, 0x8ab93f6b, 0xda4f7ef0, 0x9f59a33b, ++ 0x8f3cad15, 0xbce6077d, 0x83af3b75, 0xbbcc0a34, 0xfde3e1cc, 0x0ad81825, ++ 0xe7a33b3a, 0x2e7f58f9, 0xfc043c09, 0xf907d19e, 0x433cdfb0, 0x68d5f4f6, ++ 0xebc6cc7f, 0xaffb767c, 0x895fe0e2, 0x45d53b27, 0xba8aebef, 0x5d7da1a7, ++ 0x1e80579a, 0x61bd1ed2, 0xbf53e03a, 0xee56df77, 0x83e9d6a7, 0xefb559bd, ++ 0xe85491fc, 0x5f0a3781, 0xaf6be80e, 0xaa7f7fac, 0xa5a567df, 0x8bfd6d56, ++ 0x709477ac, 0x7bb484bd, 0x4b97da1b, 0xb19367fd, 0x42ce89af, 0xb24c7796, ++ 0x7d7c3ede, 0xfde35e9f, 0x4a408ce6, 0x3f6fbba3, 0x566c7da4, 0x21c05826, ++ 0x7c98efbf, 0xe5c33a7b, 0x8731f732, 0xfea91fb1, 0xc0443936, 0xd1a4fd45, ++ 0xacfb0d73, 0x3bbfee43, 0x5e806e48, 0xe34bfed4, 0xefca6596, 0xa99790fd, ++ 0x2f60ad56, 0x537523c1, 0x970feb14, 0xf882fe3b, 0x2b1fbc75, 0x5a21aa3d, ++ 0x3416b7ca, 0x71dfefa1, 0xb49975eb, 0xff634afe, 0x3e6f3616, 0xdc978bf4, ++ 0xd64cfafe, 0xb1d3baa3, 0x5717da06, 0x256f5ea0, 0x4c2b2abd, 0x5e2772af, ++ 0xc278bed6, 0xf7c26fed, 0x727edb97, 0x1e33cd0c, 0xc8a3b2a5, 0xce57e8aa, ++ 0x876eee66, 0x4a207d9c, 0x31d8d9ca, 0xfad44f2c, 0x4c3ffb22, 0x5c93ae7c, ++ 0x09f68979, 0xc53f609d, 0xf8c6c93d, 0x7b52d17c, 0x62d7f684, 0xd9080239, ++ 0xeb963096, 0xdf8258fe, 0xe855b754, 0xaae7d8fd, 0x026d7c24, 0x880da6be, ++ 0x1e2bb531, 0xff00e090, 0xadbaee5e, 0xd1ac7e06, 0x0ef17f6a, 0xd6feee10, ++ 0x9779d72d, 0xc060dc6b, 0x7976b265, 0x56cb7deb, 0x30f004f2, 0xfbc45dc5, ++ 0xacf714dd, 0xf9e0ba63, 0x91fe63b7, 0x8f5c8ceb, 0x1e9e5e70, 0x044d75f4, ++ 0x4fbfe02c, 0x3ae7ec1d, 0xe9fcef60, 0x0f3c107f, 0xc1f7cb2c, 0xb2067f1e, ++ 0x9c49f616, 0x03d4f583, 0xb90022b1, 0xa0d66072, 0xe7f2ec20, 0x6e420761, ++ 0xbdf2140c, 0xb03fb64b, 0x1bef1070, 0x3ee4a243, 0x368f6e22, 0xf181a7fa, ++ 0xfcc1aafd, 0xf8d68b7d, 0x5fbe016a, 0xe772c315, 0xdb94a0dd, 0xdba1096d, ++ 0xedbcf4ad, 0x76815cd3, 0xfae08aef, 0x695bb44c, 0x3ef476e5, 0x6dfa81b5, ++ 0xce52365b, 0xde561ff3, 0xfc8ada27, 0x966e8929, 0x6a4fece3, 0x494fe59b, ++ 0xc0d92b80, 0xf956db57, 0x92fc087e, 0x75419f78, 0x976f7f2a, 0xda336fed, ++ 0x4ba0cefd, 0x039673e2, 0x1b18ccfa, 0x991ffce8, 0x7f314f8b, 0x468a7f08, ++ 0x915c3fe3, 0xdbc2bec3, 0x60cc6faa, 0x12fc31fa, 0xadb90c0b, 0xce07c3fa, ++ 0xe583d0f1, 0x1dcac2df, 0xbcf3d02e, 0xed17572a, 0xaadde2c0, 0xcbb0b1d5, ++ 0x50d6e9e7, 0xb9c5f414, 0x7d5efec5, 0xfae3132c, 0xca15b8e5, 0x03950bbe, ++ 0x76e8bfae, 0x6f597b8a, 0xb7098d0f, 0xeb7e1497, 0x852527da, 0xa2cbc5db, ++ 0x11397ca4, 0xe7f6f92d, 0xd15ffa31, 0x1bfec36f, 0xe5edc293, 0xe36b9585, ++ 0xf18cdf98, 0x93fb374e, 0x1f43678e, 0x1aa5ce9b, 0x7d338d4f, 0x11afd3b6, ++ 0x46f67a7e, 0xa77b3eb1, 0x510de741, 0x5790f9a1, 0x91dd2e8d, 0x4faa7185, ++ 0x076f8216, 0xc78bcecc, 0x62bdcffc, 0x8e4fb015, 0x1d877819, 0x1a06b806, ++ 0x845e9963, 0x9dbfd751, 0xe91176c4, 0xfa5f4c93, 0xaeb8a3fd, 0x9529fc3b, ++ 0x4415dfa0, 0xc707443f, 0xb1fdf23c, 0xbfa604da, 0x5e6bfbd2, 0x63df0413, ++ 0xd3a60e25, 0xecac0763, 0x9343fabf, 0x3820e435, 0xe17d9d9f, 0xeefa5cc1, ++ 0xc60fcaec, 0x73b2a66f, 0xffac7bf5, 0x9baeae97, 0xab4aef81, 0x3ec4ce57, ++ 0x2a3e2977, 0xf3828dad, 0x636e17a3, 0xacdefcb3, 0x85df5881, 0x6fea1623, ++ 0x43ed4d48, 0x96674095, 0xd7f5839e, 0x01eb3a3b, 0xffe7fa8f, 0xe5bb0e98, ++ 0xd93f73dc, 0xa7ca8473, 0xfc11f563, 0x190df57e, 0xad99d16b, 0xadf0173b, ++ 0x40be11b7, 0xd87ec63f, 0x2bcfd060, 0x1815fa59, 0xcbf576a7, 0xe4c767ac, ++ 0xb5f94877, 0xfef8f2f2, 0xcf1d81e4, 0x4d5df468, 0x2e7a81f4, 0xcc42c1ad, ++ 0x8a1694eb, 0x5700b2d3, 0xf69cff69, 0xa812e284, 0x2f522dd4, 0x5e65d9ab, ++ 0x90754f2f, 0xefa15fe1, 0x7eadda6a, 0x413bdb17, 0xd91fe607, 0x739e86be, ++ 0x5e7ccbbb, 0xf3e5da2d, 0xb83ffd84, 0x143fe246, 0x7c9efc22, 0xf01b673c, ++ 0x4fdf667f, 0x497f1772, 0xf9e2e31c, 0x069ff5ca, 0x4f5c11bd, 0xe83b13d3, ++ 0xc994776d, 0x78fb3f0e, 0xcede898a, 0x083c3e3e, 0x9efd573e, 0xf08be435, ++ 0x059f8fb5, 0x8fb7f03e, 0xe4aabe87, 0x17b6708a, 0xd79d1db2, 0x51bb085e, ++ 0xd25123c9, 0x83cfcb9e, 0xff68b9ed, 0x25fa458c, 0x3fd5b8d4, 0xaf7add4d, ++ 0x2c06aff4, 0xb51f5163, 0xefd5750d, 0xf86fad57, 0x3ea98766, 0x7fae6822, ++ 0x0dfa4b23, 0x9e82789f, 0x1ab77e4b, 0x2af09cf6, 0x1ea57a3c, 0x9df970cc, ++ 0xeee5c143, 0x355f9254, 0xcf265b98, 0x27fdca5b, 0x99e2ffa4, 0x72153d22, ++ 0x43d62cf5, 0x81267cf3, 0x43d0f9ea, 0x5d55bce4, 0xde7221c1, 0x24b77fab, ++ 0x6dcc7e15, 0xe5dfca59, 0x69fa0c1b, 0xd5394971, 0x203b2762, 0xd561f61f, ++ 0xd836e398, 0x0ae4be8d, 0x961c1f5b, 0x82722e6c, 0x296e97fe, 0x43d38672, ++ 0x4731aecb, 0xa7166769, 0x987cd977, 0xf82d8b72, 0x2db9e803, 0x01edacbb, ++ 0x7e9defc1, 0x7dda7f6a, 0x5bb40de8, 0x346125b2, 0xfdf552f4, 0x92e3cdd2, ++ 0x39e6c22b, 0x9e19976a, 0xfae6ed05, 0xf5cdfb15, 0x06d5d0dd, 0x15dff3fe, ++ 0x31f5cc85, 0x8ff5cd47, 0x7cf7737f, 0x35955d90, 0xf42b03f0, 0x1da6f7ee, ++ 0xc9f23ec5, 0x01c6cf33, 0xac7f353f, 0x627b0238, 0x9c3366e9, 0xf41a6f09, ++ 0x8d4ec0ed, 0xc165d1f7, 0x9fe8fe48, 0xc558856f, 0x3a2837fa, 0x45aa4e9c, ++ 0xe32d88e0, 0x44a7f6e2, 0xd13f7cfb, 0x8ad36d55, 0xf4c7c731, 0xfb557bf5, ++ 0xa1f40746, 0xc52f71c8, 0xf7edc2a7, 0x3654afc2, 0xbabbbe41, 0x80f8b269, ++ 0xe1b124b6, 0x7f40d357, 0x78d7df65, 0x7a7b2dff, 0xd3908bf8, 0xde167b5d, ++ 0xe9fce5c4, 0xefe50f0c, 0x0b407a5a, 0x33dd52c5, 0xe56dd241, 0x68282d66, ++ 0x44d78bde, 0x71e03e29, 0xe798362b, 0xfccda4b1, 0x83fee97e, 0xb95c457f, ++ 0x03a8f9ca, 0x16d558fb, 0xe75a7bf3, 0xd537d861, 0x77f6089f, 0x22ff6f54, ++ 0xae5efcca, 0x23ad52ab, 0xfac09d70, 0x7a4d96ae, 0xa8e394f5, 0x4bff1c90, ++ 0xc829c97c, 0xb6dbabf9, 0x3ab7015a, 0x93c37fa1, 0x287bf6c5, 0x24b1e686, ++ 0xd1b1f48a, 0xbaf2ffbc, 0xe78e6fce, 0x173d3978, 0x5e7e7a2e, 0xbec78c74, ++ 0xac6f7e7c, 0x3a51c64f, 0xbea87bc6, 0x5b80ea94, 0xf8656895, 0x5afe42d4, ++ 0xc3f8bd25, 0x853c0be6, 0xb4ab45d7, 0xa16d6a67, 0x8d438083, 0x80efe4e8, ++ 0xb576f0bf, 0x1377aeb4, 0x7c447fa1, 0xf7ec7c2f, 0x183b706f, 0xbffb0d6f, ++ 0xaf7f0a88, 0xef652aec, 0x63e7bf29, 0x8345b7d5, 0xfe6ad7ae, 0x94569c87, ++ 0x40473dc1, 0xbcdccbc7, 0x55b6dfef, 0x3836f3ca, 0x6e17a0bd, 0xe5fac11c, ++ 0x173f9a6d, 0x5d1b15eb, 0x25b65f6c, 0xe2d633f8, 0xa53cacfd, 0x1f900637, ++ 0x3a2cbdd0, 0x8bef0db8, 0xb6dabea4, 0x87f59730, 0x10f6b5e7, 0x01e070e4, ++ 0xb36d2fc9, 0xddb4fd24, 0x7fefc297, 0x40a6a98f, 0x4a7a94af, 0x52e1c6db, ++ 0x79cab5ef, 0x5963fb88, 0x1865b63e, 0xe5e81af3, 0x72bd2979, 0x911f4783, ++ 0x9d6fb03d, 0xaf49ab15, 0x77c41e44, 0x1ffe02ad, 0x59749551, 0x630ef9fb, ++ 0xe8deea9f, 0x7f3fc20a, 0x82392b5c, 0x776a8b38, 0xfb94b675, 0x77fb27e3, ++ 0x8fd8ed1a, 0x7599615f, 0xef18f5ef, 0x25b78b41, 0x7efe0c23, 0x82ec2e7f, ++ 0xa35d1be3, 0x93f1a781, 0x58e61fa5, 0x31df9491, 0xf11f8563, 0x32d929fe, ++ 0xdb253b3e, 0xa3932a62, 0x9fa92e89, 0x9fd2c5e3, 0x84b63b1b, 0xab845efd, ++ 0x53cbfb3b, 0x4fd19af8, 0x97e4a385, 0x1f33f6d7, 0x55311f05, 0x72f8e7e2, ++ 0x179c9b6d, 0xe3ea97e1, 0xfec5ddff, 0xfec6e3b2, 0x7442f0a2, 0x5bf78e34, ++ 0x346d7e43, 0x25e367e8, 0x1f4cc7e9, 0xe47d91b7, 0x7d10fd02, 0x04131e30, ++ 0x7d14ebfb, 0x3d30fd10, 0xcb17df74, 0x31fa2770, 0x418463e8, 0x0dfc423f, ++ 0xed2c53f4, 0xa88f6523, 0x1eca5f75, 0x01a8ba21, 0x4bb6f45d, 0x3c458ee8, ++ 0xb083d14f, 0x597dc705, 0x84f1617c, 0xa11af184, 0x0226d522, 0xec370451, ++ 0xefb70c89, 0x69ab82d9, 0x126d431e, 0x4936693f, 0x04bbb487, 0x7b7347a2, ++ 0x65ea83bf, 0xfc2a5c3f, 0x552cbed4, 0x9b275fb0, 0x44f891f4, 0x44a04efe, ++ 0x7f0ace18, 0xbef89507, 0x5ff65e2c, 0x57045836, 0xdf9fdc6b, 0xb5086892, ++ 0x0a1f88f1, 0x7df01bd6, 0x3efe68dc, 0xfbdf9160, 0xcb0e546d, 0xbdd3fc92, ++ 0xb0f98a36, 0x5cb49eec, 0xc98ccbd0, 0x96397a66, 0x5503f52d, 0x096488de, ++ 0x63242fa9, 0x66bc597f, 0x2d2fef04, 0x7dba92ae, 0xd293fb80, 0x775b282e, ++ 0x30e32dc7, 0x7c92a7bf, 0xce4e6150, 0x8571c3dc, 0x7e166bc5, 0x13d86dfd, ++ 0x7cfc5cbb, 0x30fe8e49, 0xf3527ee0, 0x0f47da2e, 0xec3bcf16, 0xf5efa648, ++ 0x7e6759f6, 0xc0cce54e, 0x3fa0379e, 0xe56b9ccc, 0xf48533f6, 0x72358a6f, ++ 0x9f025b9c, 0xbfa992da, 0x1c6a265b, 0x7972ef26, 0x9e2397d2, 0xa777e060, ++ 0x2e2d87c1, 0x6e67e0b1, 0x372d2bcc, 0x02df9e93, 0x3d1fb20d, 0x2f8303f6, ++ 0x5b69265a, 0x9b0d07a0, 0xb550f922, 0xf7e83f47, 0x7b77c184, 0x3aa8b80c, ++ 0x57db95c1, 0xcaea8fac, 0x0f69438a, 0xe072a70d, 0xb2fbc9f0, 0x4c8cfde9, ++ 0xe0336d31, 0xe72b4dfe, 0x44b9747f, 0x4779e988, 0x1741e301, 0x60f75ddd, ++ 0xf147db7d, 0x7926bafa, 0xd98457d2, 0xc11e95b9, 0x24d7407a, 0x3a783e43, ++ 0xffa51363, 0x72dded87, 0x6c3e0483, 0xe201f96a, 0x9d2be5a4, 0x2a37d85d, ++ 0xf1c3981f, 0xb236f2ed, 0x165f6977, 0x2ef6cc1b, 0x67afa5d9, 0x46bf63f7, ++ 0x11a0a9da, 0x06c54dd0, 0x586ee98d, 0xc291cf8b, 0x60f34df2, 0x50ee153d, ++ 0x857fe436, 0xfbc3e5cf, 0xcfd8ec8b, 0xe1e3ce09, 0x0c9c154f, 0xffa39dd4, ++ 0x6b29701e, 0x31bb632d, 0xb9675f26, 0x704acc35, 0xde807f01, 0x05f83700, ++ 0x9d6c8f21, 0xfbc3e029, 0xce1d25b2, 0xbae4f448, 0x025d8e99, 0xeecba0f2, ++ 0xbafcc5c9, 0x882cbad6, 0x2d58cce3, 0xccf899e9, 0xbfefa369, 0xe0d11367, ++ 0xef8c27ff, 0x4ad9574b, 0xa87d52b6, 0x1362d853, 0x4c454f41, 0xeb870bcf, ++ 0x4faf307b, 0x402623be, 0xb0df283f, 0xa0cbce51, 0x98eb6107, 0x7ce3449a, ++ 0x346323b2, 0x7e8aeafc, 0xdc9f0e16, 0xd2f63803, 0xf18d5cc1, 0x0a39eb4f, ++ 0xe1c0e57f, 0x3de02f8b, 0xfa083f3d, 0x94393198, 0x5b16fc0d, 0xf61f856b, ++ 0x41f0b27c, 0x9211e89f, 0xdbd67bbf, 0xb929ae58, 0xd107e4a2, 0xa839df83, ++ 0x8e4adf0f, 0xa9a66cec, 0x35779c11, 0xa27cb93b, 0x246c23d9, 0x27377603, ++ 0x66a9fd73, 0xcded972f, 0x67fcfc79, 0xefae3ecd, 0xf5c09e6d, 0x5cfd9a67, ++ 0x9d3cdfdf, 0x97379fcb, 0x0f8273f0, 0x672521cb, 0xf4523c94, 0x2452e4a5, ++ 0x30222d5d, 0xbf9a375f, 0xe4a7f967, 0x1961d61e, 0x148f27dd, 0x27ebed9e, ++ 0x68cfd859, 0x7ad8b9e0, 0x0167c9fa, 0xe7372a87, 0xc5c2f62d, 0xa4b864ed, ++ 0xd87ec43b, 0xfdcb2deb, 0xed84f75d, 0x6957b7bf, 0xb74616c2, 0x84ba3477, ++ 0xefae8c2d, 0xd5304a6c, 0x7ade9b4b, 0x7ff53069, 0xcfcf4e3c, 0xeefbbc81, ++ 0x96fc8f47, 0xddf63f9e, 0x3bc03993, 0x26c763cd, 0xda32bb8c, 0x9ca74798, ++ 0xef074ad7, 0xff0cc35b, 0x619cfe0e, 0x196597f9, 0x04fc6f09, 0x22700d72, ++ 0xf03dfefa, 0x83fcf043, 0x06639f81, 0xcad6ca7e, 0xa02bad7d, 0x5fb43505, ++ 0x7ae9f063, 0x279aa782, 0x14fdf3c1, 0xd90319d1, 0x710217ed, 0x93bff795, ++ 0xd6be0e9b, 0x852a98c8, 0xcbfd6cdf, 0xad1c62ef, 0xcdeb28e9, 0xf9cdd3ba, ++ 0x3f602202, 0xd68fde1d, 0x89db8474, 0xbca6a1ce, 0x7eb198bc, 0x4d03fa07, ++ 0xf38b5f03, 0xb7f0090e, 0x403cd568, 0xbcf18551, 0xfac6bd62, 0x9cf78288, ++ 0x53f32b1c, 0xcb8db66b, 0xb675e033, 0x3f795a5f, 0x724a7452, 0x2aebf383, ++ 0x4b1c8b5a, 0x62efe4c2, 0x9e7979e3, 0xd77f94c5, 0x7ee0ed9a, 0xe86980ce, ++ 0x65e6f7ff, 0xde592a3a, 0x0fa01d79, 0xde717ed5, 0x639975e8, 0x60b20fd1, ++ 0x33bfbefa, 0xb7dfc6c7, 0xbee47b66, 0x2b7da4e5, 0xfa51f396, 0x6f4aff95, ++ 0xbcff04f9, 0x76cfe78a, 0x3f53f554, 0xad710a7d, 0x78a2f7ea, 0xc2beaa1f, ++ 0x07e43bf0, 0x7d61cfc7, 0x68d6efc7, 0xde06f59d, 0x8ff4fea7, 0x6a03c871, ++ 0x8bfd2bd8, 0xaca17654, 0x7ec5595f, 0xf11f7aae, 0xabe42245, 0xe2fc2e39, ++ 0x75c5ef53, 0x90227fb2, 0x7283e46a, 0xdefd535e, 0x49df380f, 0x7e4537e5, ++ 0xce7da0d7, 0x7b8aa876, 0xf16378ab, 0x97e6760b, 0xf634e786, 0x3bec3613, ++ 0xadf2083f, 0x83b585e1, 0x893fcbfa, 0xc1c557ec, 0x41ac1f95, 0x0ad4f86c, ++ 0x043b21ba, 0xff6c8c70, 0x6e231cc3, 0x92b8a57d, 0xc1361cfd, 0x8c2b0a79, ++ 0x609eb1bc, 0x12f8bc4e, 0x66c351ff, 0x8831fe62, 0x91e37a87, 0x4c8e7b3f, ++ 0xf4f0fead, 0xa7dc8e6e, 0x213f10cf, 0xb76e7a1e, 0x73c4f595, 0x7f9963bb, ++ 0xf0ff77ea, 0xf5abe208, 0x670e35db, 0x860e89d5, 0xab5efd5b, 0x85c98670, ++ 0x926ff806, 0x9acf3d2e, 0x8236c69f, 0x6bb596be, 0x9f341dfe, 0x7e37a71e, ++ 0xf67cd860, 0xaf7a48e5, 0xcf1f6a89, 0xffe63178, 0x524f4353, 0xf81d96ed, ++ 0x51f7e721, 0xbfacb3bb, 0xc70c47fc, 0x7ae7697d, 0xb53cf303, 0xf60f8c65, ++ 0x3df6b2eb, 0xd88758f5, 0x12c1e31d, 0x727e1a4f, 0x6341cfd5, 0x523983bc, ++ 0x788538ef, 0xca7fbe01, 0xe60e76ca, 0x693cbe09, 0xefaaffe4, 0x7bbe365e, ++ 0x43ea4739, 0x0e1608b5, 0xacbf6bec, 0x9b2e2bbd, 0xffbc7fda, 0x657f2e2d, ++ 0x7732cdf0, 0xcff62147, 0x4cc6f78f, 0xa3f9720f, 0x78d3cf69, 0x0d27da67, ++ 0xecf8c2d0, 0xf25d8e78, 0x779916fd, 0xaf2a8228, 0x73d79da8, 0x06aa776a, ++ 0xe01d5eff, 0xb539f04d, 0x0b38e9f7, 0x7fe071f3, 0x40b65f96, 0x97e785b3, ++ 0x7ffa6975, 0xe31e848d, 0x78c874ec, 0x5fe1b755, 0xbfe9dff9, 0xa5de78de, ++ 0x74e31895, 0x19df243b, 0xc18f7e71, 0xc1fcd677, 0x5745ffe0, 0x1dbd6f78, ++ 0x9955f3f2, 0x7a8627a7, 0x5bcec137, 0xdb1266f4, 0xa3ef88e3, 0xecd7e7fe, ++ 0x3459771c, 0xc92b90c6, 0xe7e0e39d, 0x7a90caec, 0xe27aed44, 0x0d690244, ++ 0xe08057d1, 0x08b41b57, 0xb971ea9d, 0x53a78c99, 0x8e0eff44, 0xe172847b, ++ 0x10e63cff, 0xf1f42b01, 0xafd8b99f, 0xca199b5f, 0x14f95f85, 0xdaca89f8, ++ 0x126e50c4, 0x9d0670fc, 0xf7a6ced4, 0xbb52f461, 0x3d0b942d, 0xfa43b4e9, ++ 0xf61ef117, 0xd968ed50, 0x73c32bae, 0x7ddaed96, 0xab7a02b1, 0xa658d9e5, ++ 0xb89fbac3, 0xed8545b6, 0x52b9a9c3, 0xd87ea62f, 0x29d81abf, 0xae2cb3e7, ++ 0x6d39fb95, 0xe8b2f7d0, 0x31df9e56, 0x996c6f23, 0xecbbd643, 0xdd1ce382, ++ 0xbdb1478f, 0xe3a53277, 0xf2738c19, 0x171c11f1, 0x2e08caef, 0x49efcfd9, ++ 0x56f823ff, 0xc215113f, 0x1e3c4ebc, 0xe9a6fecb, 0x08bcdddf, 0x47b67bed, ++ 0x277f9069, 0x32470a06, 0x18ec4fd5, 0x09f6fbc8, 0x9171cbcd, 0x7124af13, ++ 0x4dcdd57f, 0x26a87f1c, 0x93fd0131, 0xdbd0e9ca, 0x2878ec4e, 0xf54bfc1d, ++ 0xa2eba8f5, 0xc0b7d175, 0x1c64bba7, 0x7f13e4ed, 0x879e111f, 0xedeacaa1, ++ 0xc2957f66, 0x4d7f7aa7, 0x6bc7e4ae, 0x5f3f2572, 0x7861eb9f, 0x3fb4c5d5, ++ 0x93ebc998, 0x66704dfc, 0x69f880fb, 0xc7d8fc10, 0xa41b9fda, 0xcfd53f51, ++ 0xcfb1fac6, 0xb943d977, 0xc438623f, 0x821f7918, 0x3b13c9ed, 0x4e8fd893, ++ 0x73f734da, 0xfb016762, 0xb6ee4fd9, 0x06663c73, 0x63c63674, 0xd8b7c301, ++ 0xfd90a5ba, 0x2c63db57, 0x3df563c0, 0x5fb05a57, 0xff59bad1, 0x7caa7eae, ++ 0x23f75186, 0xadfd5f4e, 0x05782b6f, 0xfda2ffe0, 0xad68e587, 0xeeeb4721, ++ 0xf91e26b9, 0x2b4de2c6, 0xb79fd9e7, 0x4e4306f9, 0x4365c246, 0x9f4721ae, ++ 0xb6f98479, 0xf91ce896, 0x3c46353e, 0x8d09e6b4, 0x759abdf5, 0xf9626cd7, ++ 0x205d86f8, 0xfb74f8ef, 0xe1c2e30f, 0x9fa30dfe, 0xdc7defbe, 0xcbda86be, ++ 0xe38d5fef, 0xfbb4ecf9, 0x7c489f30, 0x4ff7f65d, 0xefa5ff58, 0x0f49dbab, ++ 0xfd78bc28, 0x37c745e7, 0xd81c83de, 0xf805f2ed, 0x4f9f3b69, 0x5f6f6539, ++ 0x7a9ff582, 0xe1f2c5d2, 0xbf918254, 0xc05efb4f, 0x7cdcf981, 0x7ebdfb3f, ++ 0xb440473d, 0xfb9a0d2f, 0x76faf355, 0x75cf94ae, 0xf078be49, 0x03e11d61, ++ 0xbe7e11fd, 0x69bfdfc6, 0xd723efe7, 0xaef8d0b3, 0x8c9f0f97, 0x353c3a61, ++ 0xd4e5e244, 0xdf79c353, 0x74904ae9, 0x7b65f34d, 0x2c8254f5, 0xf4043271, ++ 0xf491ed50, 0x3b526a70, 0xb4a7e7db, 0xd9765c3d, 0x4dd577e5, 0xe8961c46, ++ 0x03f41934, 0xca1c459a, 0xfa03a1b9, 0xf8f1e406, 0xa2865cd1, 0x5ff62f12, ++ 0x9db31d13, 0x4fc196f7, 0x8f208350, 0x7ec27e39, 0xe40776d8, 0x7de86ea9, ++ 0x8e2fbbb5, 0xb54f01ab, 0x078e35bb, 0x53572cfd, 0xef3e77fe, 0xbc252352, ++ 0x7e6809a8, 0xacd519e4, 0x740cbe59, 0xf1b8d35f, 0x5a83f076, 0x4c4d8d47, ++ 0xa5d61d87, 0x643e7959, 0x3b39dfdf, 0x14f1e2ff, 0x1be85f7c, 0x3ed47847, ++ 0x1076bc43, 0xb281d241, 0xd5fd4ade, 0xf036d1ae, 0xfeca1938, 0x7053eb94, ++ 0xf81169c2, 0xe05f94dd, 0xf357eb52, 0xde7cd4bc, 0x5750e436, 0x89fef786, ++ 0x56ebf7c0, 0x3fe72796, 0xf89f131f, 0x671b7a25, 0x68feab8e, 0x4e93effe, ++ 0x43527ec6, 0x94e0d59e, 0x7733cd04, 0x92ae398b, 0x1f5cddb7, 0xcf5cdbb9, ++ 0x17ae6bdf, 0x7dd7301e, 0xbfeb9a2f, 0x7055c634, 0xfc8c3d82, 0x28c3d835, ++ 0x28e30f61, 0xd461ec0f, 0x84a30f61, 0xb0e78c3d, 0x3d875187, 0x61ec3a8c, ++ 0xa30f61d4, 0xe78c3d84, 0xbee5c349, 0x31f86b56, 0xabce0781, 0xe2a5ce7a, ++ 0xe72fcce8, 0xf2920e16, 0xc5ed26d7, 0x59f2cb73, 0x4972ebcf, 0x2cf74f3f, ++ 0x96fb0fa7, 0x2eb9cbca, 0xdcefff56, 0x76778871, 0xe0c94bac, 0xdc2fd8ef, ++ 0x17e973f0, 0x72ed1dae, 0xb9d11fc3, 0x5075e3f6, 0x7562124f, 0xc871f0cb, ++ 0x09deea63, 0x1d35d6f8, 0xe774f8e6, 0xd79bef2a, 0x5fb1fc4b, 0x94d9e544, ++ 0xdc835f61, 0xe3821c46, 0xb8673e90, 0x3e32335f, 0xd5843623, 0x99b4e7a1, ++ 0x18f191eb, 0x89bf35c8, 0x4e195aaf, 0x53bbd98f, 0x783ff720, 0x9de7c9dc, ++ 0x68fc303e, 0xf5878162, 0x2377a526, 0x6572174f, 0x36da7dc5, 0xc359d7ec, ++ 0x3d9f1913, 0xe74c7347, 0xf2cb22bb, 0xaf59a30b, 0xd06fadec, 0x9867182c, ++ 0xc58ffa43, 0x9789563b, 0x9fde38e4, 0x38e632ee, 0xd87afa1c, 0xa30447fc, ++ 0x6a34f44d, 0x1c446257, 0xfda98871, 0x2333fb15, 0xcd2388e2, 0xabb9adf1, ++ 0x9efec20e, 0xa98c61b3, 0xeff079dd, 0x32b3ec58, 0xe4a2a72f, 0x96b8889a, ++ 0x7c8f4f31, 0xe89d9776, 0xb5dfda85, 0x87f7852f, 0x7fb79a0a, 0x8249e20c, ++ 0xb5d2e8f3, 0xe3963ac0, 0x3fce355b, 0x1ff6372c, 0x8fde64d1, 0xe0226cab, ++ 0xc6809c41, 0xbb587e87, 0x9570706f, 0x557f47d6, 0xa04fe11e, 0xec8d96fe, ++ 0x9ec10c28, 0xe3c7e578, 0xd6754f41, 0x8388e9ad, 0x7705addd, 0x4e6e887a, ++ 0x7419ee26, 0x93ffbd15, 0xfa039f45, 0xdc747d3b, 0xce08131b, 0x7d5b77a7, ++ 0x1edd2718, 0xddda341a, 0x76e97747, 0xbff0344f, 0x76cad5b5, 0xd659fc04, ++ 0xd8fa3ec4, 0x9d149ada, 0xb75beeed, 0x8e6187a2, 0xb0bbd0d0, 0x58b99fae, ++ 0x9abd22cf, 0x47f3abf7, 0x55cfacad, 0xac02d24d, 0x5ceb1af7, 0xa9df91e1, ++ 0xec371cf5, 0xfb2d9143, 0x7f78dbbd, 0x42c1c47a, 0xcda5e22f, 0x90add3fb, ++ 0x3bdd96eb, 0xe85ca853, 0x9eb1ebd4, 0xbf39adaa, 0x54e3489d, 0x88156dbf, ++ 0x36d87f4f, 0xe82aee25, 0x7dda4f9d, 0x4f7ea833, 0xd01d8feb, 0x416dabef, ++ 0xaad4ec07, 0xfc3ab7c7, 0x6bb0de54, 0xb25f3f2b, 0xf5ed8cab, 0xed91a2a5, ++ 0xde544fce, 0xaa8f01ad, 0x0f16dac9, 0x436dfbcd, 0xcb45548e, 0xeb628f7c, ++ 0xa79097c4, 0x56977e7e, 0x735eb384, 0xca38f64b, 0xe1faf9e8, 0x823e9c46, ++ 0x9b5e7a5f, 0x7e103c53, 0xe18d76a8, 0x98fe297e, 0x44744387, 0x782e730f, ++ 0x617b9cb9, 0x6fbddb24, 0xb08eb20b, 0xd847e47f, 0xf3c9afbf, 0xdfc83d5d, ++ 0x39573c21, 0x00e60342, 0x33b0bf0f, 0x7e88ea1e, 0x5d868c26, 0x54d5c42d, ++ 0x9ab44c96, 0x6a61b7e8, 0x17de898c, 0xa23e3088, 0x218be6fe, 0x19dcfaa6, ++ 0xb7f6a659, 0xc1151dce, 0xdefba30f, 0xbabadcb3, 0xebd53def, 0x1abc0656, ++ 0x364cc1e7, 0x2572a73f, 0xa64dd9d3, 0xecc4ebef, 0xf3a076be, 0x3862bfed, ++ 0x80e1d10b, 0x9c6554fd, 0x77a05847, 0xf93bcf19, 0xc4c42d39, 0x7cb2c397, ++ 0xa4fb95bf, 0xcaf9fd9d, 0xff00bdbf, 0x9f6feace, 0x1bcdee8c, 0xfc289e44, ++ 0x0f59ba11, 0x523b60e9, 0x19d43c48, 0x3cbaa2fe, 0x0baa2fe9, 0x87903874, ++ 0xa5b7f04b, 0x5bea4812, 0x5203f635, 0xa26a677b, 0xf3c4afac, 0x05f3e6bd, ++ 0xde02efe8, 0x8196b51f, 0xd7df225f, 0x1fb1bad3, 0x03bfc3d4, 0xdfea953f, ++ 0x67d157e8, 0xc8ecb9e4, 0xbcf2527e, 0xbbd5cf4c, 0x42191cf6, 0x92539970, ++ 0xa9fe0450, 0x2f659f6d, 0xce98bfcb, 0x5f3fbc94, 0x54ff6165, 0x99876bcf, ++ 0x6caa7ace, 0xfc87993e, 0xf7a8f0e5, 0x24683f4b, 0xf5a12dfd, 0xc9726f20, ++ 0xd417cd5e, 0x65c03b64, 0x0232e808, 0xc0fda92e, 0x17a9c14b, 0x97ef116e, ++ 0x91631fe2, 0x2105a09f, 0x8b822f27, 0xffd1a382, 0x7eb05d12, 0xf209f349, ++ 0x13fa227c, 0xeff92213, 0xdf373e2e, 0x1e1345b3, 0x30e1abed, 0xabf482fb, ++ 0xeb92cb0c, 0xf9a7deee, 0xbfcfa7a0, 0xbde7e360, 0xf32252f4, 0x30cee7a9, ++ 0xfd2f67f3, 0x997e4894, 0x7f106177, 0x474dbff7, 0x2a3f455f, 0xa799126e, ++ 0x0cfdceac, 0x8bfc33cb, 0x2fb8c4e3, 0xeb3c89fe, 0x1ce7bd61, 0x04fb4ce2, ++ 0xec092ffc, 0x3bef316f, 0x84263ff0, 0xb4651be9, 0x80c77a9f, 0x820e875e, ++ 0xfc37567f, 0xeb1e4a7c, 0xd6eb7f46, 0x7f79f164, 0xd6be9df5, 0xf4d6fece, ++ 0x965c4955, 0xb0833cb9, 0xb2ad945f, 0xf7fdf9f2, 0xd07837bf, 0xf7a3a204, ++ 0xcc07dad7, 0xffde2ea0, 0x5174d8e6, 0x97317a80, 0x5a8c6c1f, 0x570fee10, ++ 0xb93cb4e5, 0xf77dd46f, 0xcebfde5d, 0x5b8b5e58, 0xbb5b3e00, 0x37290e2f, ++ 0x1adf6b35, 0x7b7da1ef, 0x979f45ad, 0xc0fe0e37, 0x0b6fbcad, 0xf842d6cf, ++ 0x50de94c3, 0x3078b6bd, 0x7fdaf7f6, 0xfb147e1c, 0x3ecabebb, 0x89e6fa08, ++ 0x513cc8df, 0x5f58b7da, 0xe925c4f8, 0x311d93f7, 0x13edde7c, 0xef11f84d, ++ 0x583d6659, 0xa3ed31e8, 0xfc63e607, 0x2e349c07, 0x3b8375c7, 0x2fae3193, ++ 0xfa95f9c0, 0xfef89caa, 0x6caa24fc, 0xb8f52cd8, 0x6bafca9d, 0xbfa17ff8, ++ 0x1dfd0ea3, 0xefe82441, 0x477f43a8, 0xcf1dfd09, 0x07e7e11b, 0x1774b49d, ++ 0x4c0cfec1, 0xbc8d7916, 0xa0f3baaf, 0x45a5df9f, 0xee6720fb, 0x39837cd2, ++ 0xde5dbfbe, 0x21e8a043, 0x76d73e72, 0x4615ae93, 0x705fd79f, 0xb4fcf08a, ++ 0x54c12249, 0x314ce29f, 0x64f62fb5, 0x90dfde98, 0xfef4c23c, 0xa9916f46, ++ 0x55de737e, 0xf8b7f6a6, 0x5fea9926, 0xa9a3709b, 0x2cff2cfd, 0xf4ce7d53, ++ 0xf3f6a685, 0xef4cca4a, 0xccb05d6f, 0xbea17ef4, 0xbdbf54dc, 0xf6a69bea, ++ 0x32ae3477, 0x8f0bf7bd, 0x01dafb0d, 0xf70455d8, 0xa2aec05f, 0x73d7aef2, ++ 0x9d78e1dc, 0xd8d2c538, 0x4b7edf9f, 0xde63d49e, 0x04dfe118, 0x0f79c4ba, ++ 0x719a61d0, 0xec09e39e, 0x1711031f, 0xaed2690c, 0xdd0148ed, 0x7c8bb644, ++ 0xd0e6313f, 0xe3482f79, 0x6d7365f1, 0x5e260f24, 0x164c6879, 0x1e3e27d5, ++ 0x0e6bf594, 0xf5499d3d, 0x49ff8f69, 0x7438afd6, 0x3e0fef1e, 0x8dae63be, ++ 0x39c4cce4, 0x928a5582, 0x06e6f311, 0xaf131d68, 0x93e0dccf, 0x77d6117e, ++ 0x80af452e, 0x0122f203, 0xa2219407, 0x8887944f, 0x48be513e, 0x2d9159f4, ++ 0x4fa211c4, 0xbec94794, 0x925ff3c4, 0x35f2897d, 0xbe512fb2, 0xca25f641, ++ 0x512fb20e, 0x0179bafe, 0xd669bf97, 0x9a77bbf9, 0xb77cb8ab, 0xff9f91b9, ++ 0xcb89b9be, 0x6407343f, 0x3a9a79ff, 0x16fecf27, 0x47aa8715, 0x9af10ffc, ++ 0xe1d3f6fd, 0x2fcd5971, 0x37154df7, 0x9d14696c, 0x4ed3e031, 0xce47c25b, ++ 0xa5e078be, 0x7c4daae5, 0xfd67a614, 0xabffcbbb, 0x0c63f63c, 0x367cb0f5, ++ 0x73131f9e, 0x9e1346d2, 0xdff43352, 0xd1bcfde2, 0x49e36be5, 0x79ff5c7e, ++ 0xf2f41da3, 0x73ffa5b6, 0x74184fc2, 0xff8473b2, 0x2a23900f, 0xcee2adee, ++ 0x612cf9bd, 0x93c47171, 0x8a8cde55, 0x585ff387, 0x538a8c3e, 0xeb9c7cab, ++ 0x54737b8c, 0xdbe55a1c, 0x2f8b7ea8, 0xd77b9608, 0x7eb1b7ae, 0x21136b12, ++ 0x6af2a38c, 0x17b675ae, 0xdae0df21, 0xfbe7375a, 0x8ee7a60d, 0x6fcedcd1, ++ 0x5ffb72a5, 0x5f617da8, 0xb1b07bdc, 0x5c9b588e, 0x9d05f147, 0x1ad7b4fd, ++ 0xef7c7f71, 0xf803ef94, 0xd059b91e, 0x7994a833, 0xb3f49a6c, 0xda3c38aa, ++ 0x21f6c8c7, 0x19fd97f4, 0xc7d7178d, 0xed896947, 0x4ad7c845, 0xbe7377ab, ++ 0x214996d6, 0x2735c73e, 0x3afbbae1, 0x8dc7c8ad, 0xa8f83aff, 0x198f432d, ++ 0xf57fed41, 0x47cd3782, 0x5989d9f5, 0x32ce5103, 0xc12fe0f4, 0xb8c4678f, ++ 0xb829783e, 0x78297c2b, 0x312fe587, 0x7f0abf9c, 0xc48b7891, 0xf153c297, ++ 0x03f83e85, 0xa7e3177e, 0xbff07f0f, 0x9f82fffe, 0x3e76b6b1, 0xeb55181f, ++ 0x5f5e61f4, 0xbb3baf85, 0x3f9c34c5, 0x3de0bb2e, 0x4c96f282, 0x53f009fd, ++ 0xcd3498b9, 0xac791803, 0x44e3f005, 0x997f9bb6, 0xd113beed, 0x98e250ee, ++ 0xbacb7ff5, 0x8896ddb8, 0x63092d76, 0xfa4dfc36, 0xfec56e91, 0xe76bd47a, ++ 0x2eabd6b8, 0x77e10f95, 0xa71e1117, 0xa8e8f218, 0x83fde468, 0xf000b2d4, ++ 0xf540d53b, 0xaca5fc94, 0x9b754ecf, 0x9f69c3f5, 0xd773c897, 0x65f42203, ++ 0x937d2e23, 0xa20defd1, 0x3c8dfb95, 0xa1937d97, 0xcb9e4687, 0x7a411aae, ++ 0x64989924, 0x4e4066db, 0x393e154d, 0xfd5ce32f, 0x37ec8f54, 0x2c97a0d5, ++ 0x044c55af, 0xcf9d083d, 0x7388bf73, 0x371885f5, 0x451bf5c0, 0x459bcb90, ++ 0x85b9fb88, 0x5fea2904, 0xcf2ec213, 0x82f3cbd3, 0x4ffd56f5, 0x39d4b3d0, ++ 0xff4b9f41, 0x70e7f816, 0xdc52cccc, 0xcc65307b, 0x777c6c94, 0xf597aa68, ++ 0x2cce4393, 0x57c097d6, 0xfe3ec4f6, 0x17f6857b, 0x1ce05aa4, 0x639c4a1b, ++ 0x796626cb, 0xd41ff699, 0x255bca6f, 0xaf34ddf0, 0x7d460f39, 0xb267b37f, ++ 0xb4b98db0, 0xf0b9bf7c, 0x0fc8a1b9, 0xf8613578, 0x5fb9f854, 0x2a72b84d, ++ 0xc26afbd6, 0xa32c8b60, 0x3c165c1c, 0x3e9fdd9b, 0x6fb9e8a7, 0x96c269bc, ++ 0x2b386974, 0x53c246b8, 0x805ff9c1, 0xb3c80eeb, 0x013eb848, 0x1c438c58, ++ 0xf87ae9ff, 0xa462ea7b, 0x1b3ff13c, 0x5c17102b, 0x7fde4fb1, 0x44530276, ++ 0xc253b5de, 0xf47fd229, 0x0a18b371, 0xf1ed8b78, 0x63dd5cfc, 0x3574d955, ++ 0xd34973af, 0xd12efe04, 0xfc0b3fa9, 0xca1d1e9e, 0x7c458d25, 0xcf85a5bc, ++ 0xca799efd, 0x5fbe83ea, 0xf06ef56b, 0x6abc8641, 0xf13f7ce5, 0xc474e1f9, ++ 0xfef6c4f7, 0x9d6b90f3, 0xaeca8e12, 0xc2599259, 0x633c28fc, 0x5b3de592, ++ 0xdab31cf2, 0xc94687ff, 0x9e755e3c, 0xc0fa52f6, 0xb72968f8, 0x39494686, ++ 0xdf47f0ab, 0xfa953d71, 0x29724f19, 0xd668fef5, 0xfe3d33ff, 0x425f0137, ++ 0x567f49a8, 0x00cf7cf6, 0x44ebc709, 0xd1f826ee, 0x8bb51ea6, 0x99efbd20, ++ 0x5bf94c2a, 0xdb94afc5, 0xb9d5df20, 0xb264a893, 0xdff8c2b3, 0xde168de5, ++ 0xc98dfa30, 0x63d5344b, 0xed4c437d, 0x9a6427e3, 0x47f827de, 0x4d27de9a, ++ 0x0faa6d1f, 0xd4dab92c, 0xc982f07e, 0x7e8a7aa6, 0x6a7da993, 0x5d536cd5, ++ 0xf954a1c9, 0xde35a448, 0x587efa66, 0xfb5362d3, 0xe9b5408c, 0x3bf808bd, ++ 0xe9fbe8f2, 0xeb59f7c6, 0x13df9857, 0xfbe32d78, 0x51f8b7ee, 0x31673c9c, ++ 0xef84bddd, 0xfd69c8b9, 0xd63e7996, 0x57d8adcf, 0xbe35e352, 0xaf06e0a7, ++ 0x2715ee59, 0x3d53eb9b, 0x75022f45, 0x79913c53, 0xf40d213f, 0x3368da94, ++ 0x691f8f3d, 0xa285dfd8, 0xafefed90, 0xd23ebfc2, 0x7848ff84, 0x4f0f4c5d, ++ 0x0d7ee117, 0xd7c3e5f8, 0x387cbf05, 0x0f97e05c, 0x1f2fc3af, 0xf97e1ede, ++ 0xcbf0f7f0, 0x731fbf87, 0xe3074cd4, 0x7074cc3a, 0x3a66bbe5, 0x8919f450, ++ 0xcd3aabaf, 0x4d7421f4, 0x5f04bed7, 0xa6627cd7, 0x08fc489f, 0x9bf8cdd1, ++ 0xc3c4d6e6, 0x7c73ff19, 0xf6348f15, 0xbd5f0339, 0x437821f8, 0x342ebd9f, ++ 0x8a1ff38a, 0xee055a8f, 0x58c478c3, 0x1aa30de7, 0x4f2499dd, 0x5fe9b09f, ++ 0xa28b9e43, 0x491496ab, 0x9f473d57, 0xcfee4176, 0x653fe88a, 0x24773e88, ++ 0x4905a3c9, 0xa01dd3e7, 0xef796e8f, 0x61ac26d6, 0x249e5f60, 0x9cf2e5d9, ++ 0x7de4b7f3, 0xad2cc72b, 0x23f3e41a, 0xc6297a71, 0x51bf33bb, 0x5935bc43, ++ 0x8259ec94, 0x8cff98bc, 0xd17d474a, 0xa1bf7930, 0x73e4efc8, 0x2e2e4a06, ++ 0x3379954a, 0x3b0d2315, 0x67f327c8, 0x7a948e96, 0xc3cfac6a, 0xf965bd79, ++ 0x99051cf2, 0x0a8be92f, 0x5cd78f00, 0x368f01c3, 0xd7d7df0b, 0xf3c6f769, ++ 0xac57bb39, 0xe822f102, 0xd327d0ad, 0xe5ae7d0c, 0xe6274e77, 0x30b37c3f, ++ 0x8223abed, 0xe93e534e, 0x531e5da8, 0xd93da0bd, 0xfd8afed4, 0xa2fbd35e, ++ 0xfde99e50, 0x533ea398, 0x04c75c7d, 0xdf2bfb53, 0x57ea9bf5, 0xb5374e75, ++ 0x1293e6bf, 0x74553d53, 0x0ef8043f, 0xfcdda4d3, 0x094cc8d8, 0x8f8caf27, ++ 0x4127ba2d, 0xec34839e, 0xab97a569, 0xa0dd633c, 0xdefd48e7, 0xc1344081, ++ 0x35fa41cf, 0x279505f6, 0x05e447ac, 0xf7bffd2b, 0x9cc0429c, 0x83f2ac27, ++ 0xc303ed7b, 0x273de81e, 0xd783f2a1, 0x1783f398, 0xfd7e8945, 0x948c4f0c, ++ 0xf9c8b1fe, 0x8e4579ab, 0x91e39a9f, 0x777e8ded, 0x373ffb38, 0x1948ecf3, ++ 0x559e3faf, 0x7d3a0ed2, 0x777beed4, 0x3f3fc669, 0x67ec4b4e, 0x87e73a29, ++ 0x5a97f9c9, 0xcace772c, 0x16aa7be7, 0xdc6c2cfc, 0xcf78c623, 0x7d741be5, ++ 0xc5167189, 0x6fce711b, 0x2f47e71b, 0x43b26e31, 0x701e81ac, 0xfbf686c7, ++ 0x4b481386, 0x7dc6ad1d, 0xf03b4152, 0xe932633e, 0xa3f04557, 0x49b9b625, ++ 0xc9b478ff, 0xd7917ec6, 0x479b2e47, 0x39ef599a, 0xcf646188, 0xc3a00e80, ++ 0x29ba0ec0, 0x31f32adf, 0xef3e4a47, 0xd04407db, 0xf9e767c8, 0xd83934f5, ++ 0xae87ea4e, 0x7ad4de98, 0xd8f3affe, 0x6bd3e123, 0x26741a8f, 0xecbe7c8c, ++ 0xe757ba08, 0xedcbbc09, 0x7cdcdb25, 0xf23a612e, 0x50e57aa2, 0xc33794be, ++ 0xa0384946, 0xa5cde41d, 0xf35b15da, 0xee2fe1e3, 0x4f78de11, 0xcaa6f43f, ++ 0x28782bff, 0x7cea5fb8, 0xfff8a5d2, 0x2293e752, 0x3e523ef9, 0xff9dc244, ++ 0x92bce32e, 0x1f928bc2, 0x10b9d176, 0x6d982c72, 0x3df278e1, 0x9d7e66b1, ++ 0xf7c24a39, 0x5d3fc1bc, 0x0b20cf5e, 0xc3c9bce8, 0x219547fa, 0x569d153b, ++ 0x0bdc603e, 0x357b2016, 0x5b95bd6c, 0x11efbdad, 0x7711d507, 0xa3fbe389, ++ 0xb8b0afd8, 0xa56e0b55, 0xe602caef, 0x645d98fd, 0xde9cbef4, 0xf8b8cc1f, ++ 0x07a563de, 0x7bc91c71, 0x4bc83df1, 0x3715bb0d, 0x232f8003, 0x51fe26e3, ++ 0x13e61e86, 0xbae42fbe, 0x5be90ed8, 0xc1574197, 0x8663ce2c, 0xfe956b1d, ++ 0x529fce19, 0x8e22f270, 0x2757d491, 0x61e74678, 0xeb635e5f, 0xc14dbf37, ++ 0xbd38e2f3, 0xcf104fcc, 0x518ed8b8, 0x88d3fa71, 0x2aef03d3, 0x3fb4624e, ++ 0xdc0ab01d, 0x6f7a7237, 0x8cf5c314, 0xb8f9b5e5, 0xae37a99a, 0x463c5172, ++ 0xa0bf21c4, 0xdbccb767, 0xe89f14bc, 0x1e53169d, 0x57ef45c8, 0x367be3ed, ++ 0xf1949f6a, 0x0f27da97, 0xdb0eca0f, 0xb28c963f, 0xb5acdd31, 0x06a375e8, ++ 0x543de5f6, 0x88582dff, 0x37e18672, 0xaf4f5c8a, 0xf3289bbc, 0x7d687bec, ++ 0xcba6ef2c, 0x2f24cf73, 0xc54cf805, 0xd08967db, 0xce2a9400, 0xc09fafa1, ++ 0x8e715078, 0x5e04d0b2, 0xa596bcc7, 0xd8355c76, 0xe2cad0f9, 0xfc5f6f68, ++ 0xe64d33a3, 0x0e2a5ccf, 0x8f82e732, 0xe17b9bfb, 0xc367ee6a, 0x97290ca8, ++ 0x1cb7dcd6, 0x5dc8e8fa, 0x74380ec2, 0xab97e446, 0x7f8373f2, 0x8d2ba052, ++ 0x59cbcb0b, 0x5f3cb1a5, 0xcb195e01, 0xcf2c3a79, 0xab7cfd55, 0xf5962f51, ++ 0x7acad6bb, 0xd2cf71a7, 0x815fc34e, 0x7ac4a275, 0x36ef4760, 0x075819fc, ++ 0xcf03ac4a, 0x8750c721, 0x721d431c, 0x31c8750c, 0x78639094, 0xa49458be, ++ 0xbc655917, 0x1f386a66, 0xa98a705e, 0xe2107a61, 0xc475e135, 0x23dbc26b, ++ 0x1efe135e, 0xf7f09af1, 0xd784d788, 0x6f09af11, 0x784d788f, 0xf09af11d, ++ 0x84d788f6, 0x09af11d7, 0x4d788f6f, 0x6bc47bf8, 0x5e23dfc2, 0xbc475e13, ++ 0xe23dbc26, 0xefefe135, 0xf14cd26c, 0xf38d3b9c, 0x139be5f9, 0x93be3e99, ++ 0x28caf251, 0x629fefc2, 0x7b75f1fe, 0x607cf026, 0x4576e819, 0xe24fb45d, ++ 0xc4ba75b9, 0x3c4845bb, 0x3c642f77, 0x7ac874af, 0x8de7ccb1, 0x45c41fa4, ++ 0xb8cb66a6, 0x45c44a08, 0x822e2250, 0xa9917112, 0x41171936, 0x9e08b889, ++ 0x12822e23, 0x88941171, 0x5c44a08b, 0x22e22504, 0xc1171128, 0xa08b8877, ++ 0xcf045c44, 0x89411711, 0x1f9e08b8, 0x3e2079a3, 0xbd05e6a2, 0x5764db3d, ++ 0xec9a1d12, 0x0ea98f4a, 0x3dbc3dbd, 0xf7f0f6f4, 0xdfc3dbd0, 0xaf0f6f43, ++ 0x6f0f6f43, 0xbc3dbd0f, 0xcbca351e, 0x3dfd05fc, 0xefe83bfc, 0xd682f5e1, ++ 0x49f04bc0, 0xece5b2dd, 0x633b288b, 0x8f3547b5, 0xdaf9d110, 0x3aafc47c, ++ 0x827a5a5d, 0x55c5f68f, 0x4953f98e, 0x7c8dd36f, 0x6dd142b8, 0x3e39be01, ++ 0x43d3784d, 0x0b77f382, 0xefcc9afe, 0xff94bc55, 0x7b45ef08, 0x8d01db05, ++ 0xea5e72d9, 0x58f09f7b, 0xa3215ef9, 0xffbd5f7d, 0xabe39176, 0xc32f2c76, ++ 0x620641e6, 0x8a15f211, 0x2347ba56, 0x45a77d2f, 0xab9b7993, 0x246cde65, ++ 0xe8675d5d, 0x7b2d3b4d, 0x77d3450e, 0xe71a65dd, 0xc4dae64f, 0xc068fb51, ++ 0xf43471a9, 0x04fcdc88, 0x578d5d63, 0xcd476f23, 0x490ff95b, 0xb1b9f04e, ++ 0x51c2dd89, 0xfb5ce341, 0x3dc0e167, 0x521c33fa, 0xb077c08f, 0x3405471f, ++ 0xfa30b6ff, 0xfdcbe5f6, 0xbf2c0f4f, 0x8f9e82ba, 0x3578ddda, 0x88cda3ce, ++ 0xe4fddf96, 0xe38638b1, 0x36da35cc, 0x713213dc, 0x7ce3f0b7, 0xd2f955e9, ++ 0xdbb5191e, 0x71e0a8e3, 0x4d8e7c3d, 0x25b65bf5, 0x95ddcf9d, 0xc9a9ce89, ++ 0xf8d0531c, 0x37056c3e, 0x588bdf5a, 0xa3f8891f, 0xcbff03f0, 0x3d4859e7, ++ 0x2cf39cbc, 0x284d8ed7, 0x389a1e46, 0xbc15ef20, 0xdad96c65, 0x3d2f3481, ++ 0xbc15ef28, 0x2f8dcff6, 0xbcbb7d71, 0x67c99057, 0xc3b54cbc, 0xa03c387e, ++ 0x33197df1, 0x032d5b03, 0xbb5738bc, 0xed083eca, 0xd41f0b77, 0x9e42e181, ++ 0xcaeb550b, 0x97161d17, 0x87117a06, 0x8fe8c293, 0xd05cc724, 0xcecf914b, ++ 0xb2cd6ef7, 0x3790ec79, 0x6446fa91, 0x1fe9075e, 0x413ccab7, 0x3af58dbb, ++ 0xf32a3f43, 0x5f9eb9c8, 0xa3fd6763, 0xbf719f6c, 0xa1be847a, 0xef483df2, ++ 0x8fb085f0, 0x17d9bdef, 0xcbb557a0, 0x8abce6df, 0x9dc11993, 0x64f217b8, ++ 0x13f99ee6, 0x5c9217a0, 0xbd253c81, 0x81fceee1, 0x12f9cf38, 0x0ce84b9f, ++ 0xc6facd3c, 0xc40f35f9, 0x3248f3c9, 0xc061521e, 0x2a8bf949, 0x18547c0d, ++ 0x37ef3d79, 0x695b7bcb, 0x1f210ddf, 0x7acbe683, 0x289ea445, 0xe41de784, ++ 0x7ad1559f, 0xe9736670, 0xc975b286, 0xcfdfbfa2, 0x707ccbf0, 0x6b65dc63, ++ 0x53bf9cec, 0x1503dc65, 0x351a7bf9, 0xb359fe86, 0xfefcfccb, 0xa3dfc37c, ++ 0xff754ef4, 0xeca6d19e, 0x58f3c3f5, 0x73b469ef, 0x2ae979de, 0x3d8907a9, ++ 0x05f38822, 0x58a6aba5, 0xe943bf70, 0xeb4fbf3e, 0x34de6e87, 0x1819a1f4, ++ 0xeb39e094, 0x91cb3442, 0x708617d9, 0x6485fe7d, 0x90bd6f2e, 0x17c39f27, ++ 0x2cee7844, 0xdfd1e796, 0x79a0f432, 0xfe046fc8, 0x8e998302, 0x318e887b, ++ 0x9f21a144, 0xc3b5fa46, 0xb0cfa370, 0x3f916beb, 0x60ab6339, 0xe816f2bd, ++ 0x0162f44b, 0xe031a7f4, 0xce628c83, 0xf1ae9dab, 0xc65b9379, 0x9ee8372e, ++ 0xdcb040f8, 0xf431fbe0, 0xc882b3a9, 0xefa05997, 0x8adf00b1, 0x1740f5fe, ++ 0x4b78a3df, 0xbee07340, 0x9fb0dd39, 0xf2477d15, 0xc318a2c1, 0xfe96e5bf, ++ 0x117b5eab, 0x6b4be593, 0xfee3e6ca, 0x45f045a4, 0x4b10310e, 0x97cd8aa0, ++ 0x2fc95fef, 0xc606bf9b, 0xf7e8bfd4, 0xe458b528, 0xf3d22379, 0x745c6f38, ++ 0x9f060f14, 0x2346d06c, 0x4ed7bd6f, 0xbe7c9c28, 0x5e4ecc20, 0x3a95f06c, ++ 0x7be2b6f7, 0xecbf8339, 0xc139679c, 0x28b5fc19, 0xf8ebf3be, 0xf34f98a5, ++ 0x04ea7f85, 0xd6ad4bdc, 0xd3c84229, 0x0fa8cdbb, 0x3bc1f82b, 0x1f0cddeb, ++ 0xddd99fae, 0x1a791f30, 0x2c1cb2ff, 0x179c6cd5, 0x4ba7c06d, 0x8fe54fd3, ++ 0xd38373e3, 0xfc98d780, 0x1fef3e6e, 0x37e51f09, 0xf1205619, 0x293fe917, ++ 0x8afb97cf, 0x6fd379b0, 0x978c78e7, 0xdd6a8cfd, 0xe7cddbef, 0xb8395532, ++ 0x9ad7d8c0, 0x2bce6fff, 0xe791683c, 0x04b61fe3, 0xb38b3cf7, 0x1775030a, ++ 0xf230f7f0, 0x3afe79af, 0x33dd4faf, 0x8c9f2bd1, 0x1d14257b, 0x60fa6e2d, ++ 0x8fb3259f, 0x7fd62a9e, 0xd80ed0fa, 0x820fa4c1, 0x9af5f59f, 0x097eb73c, ++ 0x3aac7b3a, 0xb1e5f99a, 0xee58396f, 0x5e3a3a96, 0xc1f46672, 0x7fa6bdf3, ++ 0x19394bb7, 0x60fdc1ca, 0xf8ba35b7, 0x6160dcbe, 0x1be63a49, 0xbc63ef93, ++ 0x2e2e479c, 0xd38f9fd5, 0x42060b33, 0x9238efff, 0xb7f13f0c, 0x687be75f, ++ 0xf0640e1b, 0xfb657cfd, 0x3ee1d68b, 0x3ea16091, 0xb997df1c, 0x17e80e3d, ++ 0x78126bf5, 0xd8345dbf, 0xba296f38, 0xf0a6ee39, 0xf4817d71, 0xb58a7db7, ++ 0x0af9c40c, 0x6882bce3, 0xb532cfb5, 0x97ebf4b3, 0x20dfbdeb, 0xe7d5afc2, ++ 0x1ebed95f, 0x031dd5e7, 0x36b7bc84, 0xff105e12, 0x26f2c3a3, 0xbd1ffc22, ++ 0x9f30eafc, 0x63655427, 0x1ba76181, 0xaf656a76, 0x6d3f9a9d, 0x8df9f430, ++ 0xeefe079a, 0xd6f7b70a, 0x715ea8ab, 0x4b0c8ed4, 0x2bd12331, 0x9ef8f3ef, ++ 0xf163cfbc, 0xb72c45dd, 0xd193814a, 0x81307738, 0x4822b6f9, 0xf9a5d265, ++ 0x878df6fb, 0xbac39ed3, 0x273e7e42, 0x3bf1e15e, 0x2eb1efc2, 0xe74cd56f, ++ 0x2f5d55fc, 0x52c47e90, 0xbf001f32, 0x70ceee3b, 0x529d2ee0, 0xcf907b52, ++ 0x89d068d7, 0x71da8efa, 0x4c8cc7be, 0xb3de4471, 0x90cef344, 0xeb0e8de3, ++ 0xf9ab717f, 0xcf6a02be, 0x41755afa, 0x037dfcac, 0x033bad0f, 0x49e787a5, ++ 0x75386070, 0x79fd47df, 0x7b861c79, 0xc7682879, 0x229478ef, 0xb7ea84cf, ++ 0x8c768279, 0xbc8d78b3, 0x20df4437, 0x27d7d1c7, 0xcfa00a38, 0xb48e3cd9, ++ 0x8d6f3d70, 0xd4b6f7bc, 0x9a00fdf8, 0x15c1eb2f, 0xaf9c2704, 0xec3639c2, ++ 0x2af09169, 0xd15fe633, 0x1bd6609a, 0x81da375b, 0xb897859f, 0x8351e0cf, ++ 0x99af160e, 0x2bcfe7c4, 0xaf3e7e6c, 0xfef01ba0, 0x5eebb970, 0xb61633c4, ++ 0x5067b26d, 0x3d0607fd, 0x79c06a3f, 0x87286646, 0xee5a09ef, 0x85e27ce2, ++ 0x6f5e569e, 0x201fbc2f, 0xf12f40f8, 0x89bc3094, 0xcfc8024e, 0xe33368ab, ++ 0xb13e6fb7, 0xb6a9def2, 0x25bfe632, 0x09e1dd36, 0x83e6c79f, 0xb5373839, ++ 0xf71ef890, 0xce8f0920, 0x7a3f20e7, 0x9dfe56e0, 0x7013cc2e, 0xa779f58e, ++ 0xa21fdee1, 0x456ba61b, 0xb4fcea3f, 0x815f6f1a, 0x5dd3de4d, 0xe03c7fd0, ++ 0x62b4f8ab, 0xcbdf1943, 0x7c2c9e52, 0x7cd5f69a, 0xf153f8aa, 0x4fc342eb, ++ 0x1661be59, 0xe4a39ddf, 0x8ddfed0d, 0x3e07eb3f, 0xdff80de7, 0xe093e066, ++ 0xf308a2f9, 0x90d1fdd7, 0x6699a54b, 0xe87f47be, 0xfdea97f7, 0xce0e50e4, ++ 0x6af6aa57, 0xf944d2dc, 0x741fe81d, 0x3c634bf6, 0xedc15fb4, 0x2673a62d, ++ 0x6372bde5, 0x9041daf7, 0x8e347b1b, 0x4fb8ad93, 0x9e2b75ea, 0x4face794, ++ 0x8df678ad, 0xe4eed4f9, 0x85175b83, 0x08a87b9f, 0x49513949, 0xc6e414fa, ++ 0x5fdf6312, 0xaeffa392, 0x2b8f8c20, 0x2e64f87e, 0xf6b6e2f8, 0x97708fa2, ++ 0xef9bad18, 0x93c3f9ff, 0xb57dbfcf, 0x557f6fb7, 0xfebc58eb, 0x7732f657, ++ 0xe334dc38, 0x9cc5907e, 0xc17c05af, 0xa35f2afe, 0x9348b8c9, 0x854ff583, ++ 0x283a48ef, 0x772dfe23, 0xcecf7c5f, 0x5ea6f4a5, 0x57f81b3c, 0x17bdeef8, ++ 0xc2b7c0c7, 0x4507ba93, 0xde6aabed, 0xbef31b9f, 0xf043c94d, 0x1955ea1d, ++ 0xefcc258e, 0xd0728e19, 0x617ef1bd, 0x2f79f985, 0xf2bd3c9e, 0x02f81d7d, ++ 0xa78081e7, 0xe9760d9e, 0x117ddc87, 0xefb1d29e, 0x352c79ab, 0x86958dfc, ++ 0xa18970df, 0xe29e1307, 0xb4f0c30a, 0xa78931f4, 0xff5ea7f2, 0x2ae7ee23, ++ 0xd8e434cd, 0xfe7cf27d, 0x8c3df6e2, 0x37eb85af, 0x5da833da, 0x4986617a, ++ 0x1637975e, 0xbf3fe079, 0x3b56fd6d, 0xd0bd3ff8, 0x97bd2fdb, 0x035f3caa, ++ 0xb47fd8ae, 0xb54f7db0, 0x43dbdc87, 0xdcbddce3, 0x3bfe1715, 0x4a14376a, ++ 0x4c6f2e3a, 0xe578c448, 0x803f658d, 0x7ee4a55d, 0xe07ddf24, 0x98b0fc92, ++ 0x7e5f03fa, 0xe7c7c930, 0xeb971197, 0xaebd7f6f, 0x1fd5ca50, 0x8fbde5d9, ++ 0x8fed31a9, 0x4345de73, 0xecf10fb4, 0x20ceecec, 0x631d05c6, 0xbc8b0ede, ++ 0xb6bb3237, 0x83cc53f3, 0xb7ce7454, 0xa77b8941, 0xa20fb2a0, 0x3c8b36fa, ++ 0x95699557, 0x5ca14565, 0x78685c3f, 0xf274062f, 0x7291743d, 0x857a52eb, ++ 0x4fd54fa2, 0xd4ba9ca4, 0x250b4afa, 0xfad57e5d, 0xfc30c83e, 0x74be7925, ++ 0xe8bb8d27, 0xcf7ce1fe, 0xd3ad57e5, 0xd857dc61, 0xf928debb, 0xad17103b, ++ 0x41da5b37, 0x5b6f5e97, 0xd67ea0f1, 0xd9bc517b, 0xcb9513e0, 0x691f1bde, ++ 0x0f91f195, 0xe8b7da34, 0xbb960fbb, 0xad4dbf38, 0x2fe7f94b, 0xa041fcf7, ++ 0xc3c8d130, 0x3e858cee, 0x9efc6a59, 0x3ac90886, 0x7b0acf9e, 0x757bf6ae, ++ 0xcf929b8f, 0xfd8d1bc7, 0x07de7450, 0x594d167e, 0xb1c87f7c, 0x71620fd6, ++ 0x9307ca6f, 0x77d4fce4, 0x9bbf1b77, 0x7146d621, 0x4de93abe, 0xaa47e0eb, ++ 0x7fb0240c, 0x31a68ee6, 0xb9dee11f, 0xcaa4d63b, 0x9e865573, 0x7f90c4bf, ++ 0xad977731, 0x37ed12bb, 0x81eff067, 0x1c4bba55, 0xb4c5bff0, 0xb26472cd, ++ 0x00ed2bde, 0x5bbaaf15, 0x1e7c2513, 0x6ad7b8cc, 0x3660e586, 0x9ba59bf6, ++ 0xc33ffea5, 0xde23d622, 0x64a5ac39, 0xc3e40a5a, 0x97bc9a43, 0x3ef98b62, ++ 0x929ceeab, 0xaf010b87, 0xeee17b88, 0x61fbb7b6, 0x2fd20a77, 0x07cc1eb0, ++ 0xd0621970, 0x2eb6b1c7, 0xc15dbfbe, 0xdf3d5ff3, 0xc542e8a3, 0xf7e12acd, ++ 0x947d0249, 0x547d020e, 0x75b1f118, 0x5eb8536d, 0x9f0e75b9, 0x634169e3, ++ 0x362b23b2, 0x28183f16, 0x095bf9c0, 0x29ba8a8f, 0x5517a133, 0x804a8b6d, ++ 0x0f6e935d, 0xa1eb87a4, 0xe1ef5b15, 0x6c9f3d73, 0x9eb9f175, 0x53599ea9, ++ 0x3df00613, 0xf7e145c8, 0xe4351f20, 0x14dd754b, 0x4a9cf9d3, 0xc1f913ea, ++ 0xe18f697f, 0xee75297c, 0x3f53a166, 0xfce2380c, 0x795e55cd, 0xdb8526ee, ++ 0xcff5fb7b, 0x66a3f2ab, 0xec238e79, 0x85ccd11c, 0xdd6d7df4, 0xa7e871d3, ++ 0xc6b781e6, 0xd7e08413, 0x40fb137a, 0xcda239ef, 0xe5511cf2, 0xe79ffd03, ++ 0x5431f751, 0xf8a617ed, 0x78c11de2, 0x90f543d6, 0xadde2070, 0xb9eb047b, ++ 0x1345589f, 0x97a575f6, 0x865de7a8, 0xbe24fa1c, 0x5ff81d35, 0xdf1373b6, ++ 0x56227677, 0xde774bd6, 0x21c84bfa, 0xd4947b7d, 0xf5826dbf, 0xd480f2db, ++ 0x30f9d597, 0x1d87739c, 0x4630aa7e, 0x9c647bde, 0x52f35233, 0xb09edff7, ++ 0x7071fbc9, 0xfcf4087e, 0x09542d9e, 0xfa47be7c, 0x471de228, 0xaf7bfa0d, ++ 0xcfbfcad5, 0x80462012, 0xeb5ef15e, 0x2388b1d3, 0xd8ac3d2a, 0xce3f07fa, ++ 0x27d8af57, 0xbee2f1cf, 0xd413be78, 0x7bd497f0, 0x78adbd24, 0xf70d3ece, ++ 0xc55e9317, 0x216d6a4f, 0xaaf87f47, 0xdea6f436, 0x6c3ddefa, 0x96eed597, ++ 0x7b6d417a, 0x4a05eb17, 0x04e750cf, 0xb177766b, 0xabbea09e, 0x52e12bdf, ++ 0x2f3e57b7, 0xf4bf1e43, 0x6cb5f8b7, 0xd71acbd8, 0xe7bc9ff3, 0xf0b655d6, ++ 0x575bbafa, 0x02fcfbd1, 0xe90fe18f, 0xdefcbd66, 0x3db35fbc, 0xe8c6b753, ++ 0xb0f6ea97, 0x0c573cf1, 0xd08ef794, 0xbe372cf3, 0x81f49af7, 0x1ed2bdba, ++ 0xaf45d50a, 0x7adc3ce7, 0x877f8db7, 0xfbcdcea5, 0x4b4696f9, 0x262c6d9e, ++ 0xdcfacd17, 0x6c7f2301, 0x2e3bcd60, 0x445209f8, 0xbbdc61f7, 0x9e9c48fb, ++ 0xfc38c575, 0xf38063e4, 0xa0f9d4c8, 0x3c7c2f73, 0x375ffd06, 0xee3cf3ac, ++ 0x3f6bb0c4, 0x91f115bc, 0xeb185751, 0xdfe4efc8, 0x48781855, 0xec47ddca, ++ 0x63df3d62, 0x88112b63, 0x48b01c1b, 0x37f026fd, 0xc21a7bf9, 0xbce3271d, ++ 0xbde53217, 0xefe94e0e, 0xf796e9ef, 0x8fb0843c, 0x4ea7fda0, 0xc7891f6e, ++ 0xbe485725, 0x177e312e, 0x3d9a6be2, 0x9ba83fed, 0x1afd0c8a, 0xd324aa80, ++ 0x8594505a, 0xf7993afc, 0x469f7ead, 0x0d93abe9, 0xd8669d79, 0xc9218e59, ++ 0xe6bfd06e, 0xceb9f3f7, 0xca87f9d5, 0xbbf7fe31, 0xcd3bfc9d, 0x72716f2a, ++ 0x6bb4b477, 0xfde74c86, 0x44daf34d, 0x943fb529, 0x6f21096f, 0xc9c2fbff, ++ 0x8ce15d71, 0x2e2d73d0, 0x0ed6bfce, 0xc857fcbc, 0xa7eb54f9, 0xfd69e387, ++ 0xf9a6ffa9, 0xf5170320, 0x9bc8f47c, 0xd85e9654, 0x38eb07b6, 0xc5cfa71e, ++ 0x4cf58e3a, 0xd509d2ef, 0x3bb4f7df, 0x10ff727d, 0xf03ff3e1, 0x25c6bfcd, ++ 0x75e6fa5a, 0x7923fbae, 0x93b7463f, 0x0f93c2fd, 0x461ff718, 0xb25ce7cc, ++ 0xa9c0f397, 0x9cfdc31d, 0xbdf7c2db, 0x98703e4d, 0xac9c33ef, 0x9a743bee, ++ 0xde143bef, 0xadf804b4, 0x48beba21, 0xf543e3ed, 0xc63da67b, 0x74f761ef, ++ 0x352fd9bb, 0xbf7fa5a8, 0x07d05bca, 0x2ebf9f68, 0xde676cde, 0x2fb4857d, ++ 0xbbf036ef, 0x2564b32f, 0xc16c20e0, 0xdb2f2334, 0x6a247bf4, 0xe31ab5ff, ++ 0x30e033cf, 0xeb916dcf, 0x123df88e, 0xcf0a0745, 0xfceaaf0a, 0xf88fc296, ++ 0x384bc756, 0x2978455f, 0x63e25fb8, 0xafe3e31d, 0x7625adaf, 0x7efe4312, ++ 0xffe5e313, 0x6f7c1f00, 0xa3e365f7, 0x418f8cc3, 0x70d7212d, 0xc80f09e8, ++ 0xcc8b2ddf, 0x827914bb, 0x6b22c0e5, 0x7503fb34, 0xe276dee3, 0xffc097ff, ++ 0x4d87ef8a, 0x7ec02cef, 0x47884c79, 0x4b4eaf31, 0xe97f3f3b, 0x43964c8a, ++ 0x8a474543, 0xcea73dfc, 0x5ac7d071, 0x5ba9fb8c, 0x9f27ceb4, 0x3f77d01d, ++ 0xbaa0b9f5, 0xd0f83a9f, 0x6db71a12, 0x9e7dfc9e, 0xee144273, 0x8aafdc87, ++ 0x47177e36, 0xcbfbf088, 0x3587f99f, 0xf7587a1d, 0x4b8e68c2, 0xde7515b6, ++ 0x2daabd07, 0x080bebc7, 0x173a9fbe, 0x9660587a, 0xbbe9c793, 0xe64d3cdf, ++ 0xe3e089c5, 0x5c3c8f88, 0x2ef1cd15, 0xd0f55f75, 0x213ffd38, 0xadef22df, ++ 0x592b507e, 0x0afe8958, 0x173bbce4, 0x93b53f46, 0x9365717a, 0xc7e7a228, ++ 0x0e39629a, 0xf954e8a9, 0xba058761, 0xd49c021e, 0x193fd8f9, 0xaee0a5f4, ++ 0x40f9e5f9, 0x67457f05, 0x6d7cbeea, 0xdeb7a4a5, 0xc17ade3c, 0x8543bc79, ++ 0x51749fbc, 0x380bcf94, 0xfebc5bff, 0xb2dde60e, 0xc562f09c, 0x8ffc25fc, ++ 0x115bbf19, 0x065d5fc9, 0x1ce3091f, 0xf92122c3, 0xb73a9163, 0xb73e64d0, ++ 0xe97f7910, 0x71fadc5f, 0xb45d7bd0, 0x9ecefe5b, 0xbc78d6f6, 0xadbfed7c, ++ 0x9cb9e6fd, 0xdb35f831, 0x3cc69fa5, 0xa50e79d5, 0xf456be3f, 0xf0e41a71, ++ 0x3cbe6fb1, 0xb8d8e514, 0xf7687392, 0xa6cfc2e0, 0x53f86b61, 0x439f274a, ++ 0xbfc2d3f9, 0x793fb1a5, 0xf57fbca5, 0xf17be772, 0x0f4964b9, 0xf3ca5577, ++ 0x91a2a964, 0xefb937e9, 0xf20babbc, 0xf25cf224, 0x3fc303ff, 0x80000177, ++ 0x00008000, 0x00088b1f, 0x00000000, 0x3cb5ff00, 0x6594580b, 0xff3fdfba, ++ 0x6018185c, 0x8a22e440, 0x86888a3f, 0xb880c034, 0x102a3b59, 0x93b4174a, ++ 0x98e9abab, 0x18665ca6, 0x939e2ed4, 0xaea18c3d, 0x4f47bb9a, 0x356b696e, ++ 0xee1598a8, 0x0c0d1219, 0xb324b46a, 0x44e710f2, 0xc1eace9e, 0x19b51532, ++ 0x39eb6cc4, 0xdf79eeed, 0xe67ffbf7, 0x7bbb6622, 0x9f3d3d0e, 0xdeff77ef, ++ 0xdf7efbfb, 0x2eff3f3f, 0x63092d8c, 0xf817f7f4, 0x098b0a7f, 0x2585a782, ++ 0x7e1925b1, 0x1a98c8b8, 0xe2777ed4, 0xe9f6a0b8, 0x5c107652, 0xa829319a, ++ 0x29a6bdff, 0x05fdf041, 0xcffa83d3, 0x820cccb4, 0x66a8cc2d, 0xab6b19a3, ++ 0x973dc92d, 0xb5dbd8c6, 0xd4e7b965, 0x3f7f86d0, 0x759397f7, 0x26480f47, ++ 0x31ddd2c6, 0x0093d473, 0x32ba3e8e, 0xa609e015, 0x24ea39f8, 0x5e8f9380, ++ 0x7632354b, 0xc38129bb, 0x36bd1db7, 0x536ce00a, 0x80ef8722, 0x963186c5, ++ 0xe39a4a6b, 0x67ec64cc, 0x69b356a9, 0xbfb36328, 0x0d1639ab, 0x99ae9f4d, ++ 0xc8aa48f5, 0x733619d8, 0x27ec0644, 0x1e3ad539, 0x7f8c1fdb, 0xc0b45d78, ++ 0xa87fcfd8, 0xdc6158d1, 0xd999534c, 0xef98c794, 0xbb16546a, 0xd0b3b19d, ++ 0xedfe86c6, 0xc61e6325, 0xca9b19f2, 0x86a6c251, 0x14623c19, 0x734c23fc, ++ 0xe3c147a5, 0x0b04c628, 0x1162ab63, 0x512d8c4f, 0xa8c29e23, 0xa91ad4f4, ++ 0x489b5a3c, 0x12b57be5, 0xec78025b, 0xf2a0cda8, 0xea89ad78, 0x5016d44f, ++ 0x85ad51f9, 0x25b593ca, 0x96d67654, 0x71482951, 0xcfcc3e6c, 0x68369af6, ++ 0xa9cc0f00, 0xeb0f398e, 0xe9033fe3, 0xa6325a10, 0x7a15e766, 0xd17fe742, ++ 0xd137ee5b, 0xcf1b86b9, 0x8febf847, 0xa9267fb5, 0xe60e80e2, 0xce0e9330, ++ 0x29d0d93e, 0xec399985, 0x55cf7804, 0xf14551e6, 0x7ec0ea7e, 0x236cee71, ++ 0xa819b3f6, 0xf43f5a5f, 0xef7ec2cb, 0xbeb1a927, 0xa5d26b46, 0x86bcf632, ++ 0xffb0f539, 0x1111d548, 0x67ec89d7, 0x0ffa0eac, 0x732a01d7, 0x32d04b18, ++ 0x8fd0ed86, 0xa7b94185, 0x2237af9f, 0x833966b6, 0x302c4679, 0x7152ea98, ++ 0x80c62eb7, 0x3c43c9be, 0xe4bfb849, 0x8faa5a95, 0x35497554, 0xb5bcc606, ++ 0xa7c8199e, 0xfe9ce185, 0x81965a85, 0x70aa60fb, 0x57ac0353, 0x91d0fe24, ++ 0x568af00c, 0x66961b21, 0x9db2ba85, 0x80d5dfc8, 0xff871663, 0xb80d5deb, ++ 0xe2b3ba8e, 0x15d7e815, 0x84da6c9f, 0xc43c4ad8, 0xbc6172d2, 0x019324a3, ++ 0x16d8bbbd, 0x18bdc701, 0xf88d5d65, 0x46b3207c, 0x49992a60, 0x92c49e60, ++ 0x609b5d88, 0xd8fb5f3d, 0x59cbe43c, 0x0320e93a, 0x4f73a879, 0x1598f921, ++ 0x4609e52d, 0x70e6ef84, 0x80507482, 0xca73a376, 0x8790429c, 0xe37a7daa, ++ 0xb53900b9, 0x608263bb, 0xf1924b47, 0x569c805c, 0x1c603fe1, 0xb35047bb, ++ 0xf26cc678, 0xd60ace56, 0xb079467f, 0xe5ad7c97, 0x96d3ebfb, 0x9b6c604d, ++ 0x0e3c2249, 0x86780a3d, 0x8f4df673, 0xfd82ed74, 0xc9a90c26, 0x65fb015e, ++ 0xf61e5299, 0x45f4d14b, 0xbeaf0119, 0x2e25d41f, 0xfa8f8d03, 0xfe7e0987, ++ 0xa44da97a, 0xfbbe50fa, 0xf240b645, 0x6c3348e3, 0x27543a46, 0xd9518586, ++ 0xe198b576, 0xb4b2ea3c, 0x458f3059, 0x659616cb, 0x7a7e38de, 0xa7c68ab6, ++ 0x5e92d7ae, 0x5b045520, 0x053384b6, 0xc602b276, 0x8a871fea, 0x4076f19f, ++ 0x518ed327, 0xdb23f0c9, 0xfd41d50b, 0xdfdfd82d, 0x4e882cce, 0xd331fc65, ++ 0xd56beddc, 0x2fc87af2, 0x0c6b994b, 0x0199211c, 0x123e415d, 0x1de88799, ++ 0x784b1395, 0x62fce853, 0xe91ebe9c, 0x7f02269c, 0x8cc950e7, 0xc0472650, ++ 0xfc9ed07a, 0xfc85de8e, 0xf9cf47b9, 0xcbc54d3f, 0x5fde2a3d, 0xc89cce1b, ++ 0x660023ef, 0xb1c84e50, 0xa3cec99e, 0x8f343c79, 0x7c8d94d8, 0xb4dcc49d, ++ 0xd273027e, 0xc37e947e, 0x949ea759, 0x1d2fba80, 0x545935e9, 0x474f8a0d, ++ 0xe45e94f6, 0x97e82f03, 0xb7f402af, 0x556a2237, 0x71aafd20, 0xdc7021bc, ++ 0x8ca71a54, 0xb152afb7, 0x5e9086af, 0xa7b23e24, 0x4cae2ca9, 0x13dec71c, ++ 0x53beb072, 0x1fe9165b, 0xf07a0dd7, 0xffc7902b, 0xe588bd00, 0xb887d029, ++ 0x0fa0e7fe, 0xe803fcb1, 0x033fac43, 0x1ecb10fa, 0xff5887d0, 0x2c43e805, ++ 0x348bcf67, 0x5a38fca3, 0x82afb0a6, 0xed6341e4, 0xa7bb8009, 0xd147ce0c, ++ 0x8fb847c8, 0x33dbc1d4, 0x38bbf694, 0x308f7d3d, 0xe254aed7, 0xd8c6b5cb, ++ 0xe70fe91b, 0x7cf9e3d3, 0x1b8e6c91, 0x8f2934f0, 0x892fb9f3, 0x0d6cfac3, ++ 0xdb1516c1, 0xe527e38e, 0xa3fcf969, 0x6ed8e554, 0x76f3e589, 0xfb0c03a7, ++ 0x45305d39, 0xe3fd8d97, 0x0fc73ea1, 0xede78f77, 0x5ebc6196, 0x7ed2afd9, ++ 0xf9c8db26, 0x4fbba650, 0x1267eb03, 0x4afcd3bf, 0xf91395ff, 0xbbfb42fe, ++ 0xae2554d2, 0x4361f041, 0xe593cdb9, 0x44e1f002, 0x900d4839, 0xe4896a8b, ++ 0x8543e142, 0xb872a2ff, 0x64e9a6bc, 0x42db073e, 0x831b43f8, 0xe4013a7a, ++ 0x58bc2040, 0x8f679c18, 0xa84bcb20, 0xf689403c, 0x45079140, 0x4f7e140e, ++ 0x62133906, 0x33b8e7fd, 0x32955f84, 0x9d3fd65b, 0x118f91f1, 0x4634db5d, ++ 0x207f6026, 0xd54bee24, 0xca1e727f, 0x54a47c67, 0xfd15d307, 0x983350ca, ++ 0x7bf8ab1e, 0x85e8a1f1, 0x06e3e09b, 0xf979683c, 0xf481e2d7, 0xe471ea1c, ++ 0xd6f441df, 0xd958ecec, 0xebfce19f, 0x2194b6c8, 0xbd04f91f, 0xcb07005a, ++ 0x13fce7a7, 0x7949fe7a, 0x1f0a1cfc, 0xe38ca145, 0xd1ce78fa, 0xe53dea37, ++ 0x5ce7033c, 0xa5ff48c6, 0x50faf385, 0x0ae72b3a, 0xf14b7fd0, 0x193e0a7c, ++ 0x70c5fee3, 0xa5362ff0, 0xbb731f22, 0x617a1be5, 0x3fe656c1, 0x9ed955ff, ++ 0x12254efd, 0x65f6283f, 0x17105ea0, 0xb20cccce, 0xf408cc3b, 0x91d76bec, ++ 0xac547bbc, 0xd7180dfc, 0xf24e7380, 0x6c8f7f9f, 0x8ce7fa87, 0xe77fa151, ++ 0x44e0d6fd, 0xd61de63b, 0xf1804677, 0xd8e0edde, 0xb9625f90, 0xfbbb0047, ++ 0xb418d808, 0xef405753, 0x2ec674b1, 0x8251a2d5, 0x67abee7e, 0x63873804, ++ 0x00c2c887, 0xeb8ee295, 0x969f91b3, 0xe88c6bb6, 0x7f6dd51f, 0xe3f238f6, ++ 0x424166f9, 0x0cdbc4bf, 0xf6fe87c7, 0x3d2e916d, 0x18062ff4, 0x68332ffb, ++ 0x8f5f125d, 0xd7979d91, 0x3d5f4afb, 0x35df818a, 0xf086876d, 0xd155f4be, ++ 0xbbd9fe85, 0x11aa57db, 0x5812ef3e, 0x162b8c02, 0x01247757, 0x60a2f95c, ++ 0x9b38c1d2, 0x0057b8a1, 0x55f2ab3f, 0xfcc0f266, 0x26914d95, 0x6dbf9a27, ++ 0x027a2f9a, 0xd7728bfc, 0x3dfa2d56, 0xeb833be5, 0xc304f72b, 0xffd22f40, ++ 0x0fa846b6, 0x672fcfd0, 0xbf91c647, 0xa3658e39, 0xc5b6c9bf, 0xe8a2bf92, ++ 0x56fd1bf7, 0x2ba3d727, 0xec66deb8, 0x3059f89b, 0x3d7ed8af, 0x87030be5, ++ 0x59f0ca67, 0xcebebf80, 0xa5e0a2e9, 0xebfb5e5a, 0xc3766624, 0xf5dbab79, ++ 0xb79c2746, 0x28cbf5ba, 0x8477f406, 0xf247dcf7, 0xa234587b, 0x45b1b7bf, ++ 0xed7e2274, 0x2addfa6d, 0xc1f55bc0, 0x2452b44f, 0xf9397de2, 0xe733772b, ++ 0xf226637a, 0x12758a89, 0xc96a751f, 0x2df4b18f, 0xadbc79c5, 0x01fa237a, ++ 0xeb3f87d5, 0x41f08798, 0x8e91e981, 0x4f887a23, 0x8140ee96, 0x23dd2da5, ++ 0x44f9fbe4, 0x9d22ba44, 0xaf44d1dd, 0xa4774865, 0xe91dd033, 0x713d222c, ++ 0xc5d6a47c, 0xf82444f9, 0x5f4e3efc, 0xe2c5ee85, 0x57d62d66, 0x4f3a73d6, ++ 0x5cf0d1db, 0x8681f138, 0x74407cc9, 0xd393bf3f, 0x4ebedb5d, 0xb7f90c3b, ++ 0x5a0f843e, 0x807c0375, 0x0f81bbfb, 0x015fe842, 0x103d46f4, 0xf4a107ca, ++ 0xeb9b2c7f, 0xcfbff00d, 0xeffd0eff, 0xd00b8848, 0xfa7ecae4, 0x63eeaad0, ++ 0x82deb071, 0xe5f6cbd8, 0xf1263f50, 0x7e06960d, 0xeb28b9c6, 0x6707d405, ++ 0x0ebc7fa6, 0xe335d5c9, 0x97e46cf5, 0xc34f4d3a, 0x8ce150f3, 0xcca13089, ++ 0xee6752fa, 0x5dce137c, 0x4a7dfb18, 0xf1dfec13, 0x6c88ceb6, 0xefb64d76, ++ 0x7c0617f8, 0xef1c6761, 0x78b3e740, 0xce9b7b5e, 0xb1fc03a3, 0x604b22e6, ++ 0xe24be73c, 0xf6d22ae7, 0x718e582d, 0xeb87cc01, 0xe71e1608, 0x7fbdb555, ++ 0xc7f2c84a, 0x17185565, 0x108d3ce2, 0xe7f86617, 0x531f8c11, 0x28ce433f, ++ 0x09d1e7e2, 0x87e84a77, 0xd665cdd7, 0x663fd1f0, 0x87d9181f, 0xe9b8e517, ++ 0x4de3fea6, 0x37e284ec, 0x18f0e732, 0x4e253b94, 0xb2d4f454, 0x63c7be02, ++ 0x0f509f8f, 0x7b7cf581, 0x4547a204, 0x3827e81b, 0xe34b856f, 0x79008492, ++ 0x405ffb92, 0x5dbc037e, 0x521cd674, 0x0677c889, 0xe64dafda, 0x23e46acf, ++ 0xf9a56f38, 0xd39e1448, 0x5b15eb26, 0xc015e82b, 0x52db257b, 0x09577c8c, ++ 0xe10679eb, 0x4d7dcaa7, 0x8adca714, 0xb33f149f, 0x5fb839ba, 0x99e80e66, ++ 0x4ccf48db, 0x77e00bf8, 0xe993017c, 0x9149f5cf, 0x03dd1998, 0xa4cfd3fc, ++ 0x01e79468, 0xff7027fb, 0x633fd14d, 0x078883b7, 0x15ce3bcc, 0xeb01d4c6, ++ 0x18cfb6df, 0x27704f04, 0xbdbff506, 0xcf6a0a45, 0xb50464f6, 0x05371ee7, ++ 0x059d79c1, 0x9e27fd41, 0x93c104b2, 0xfa824a7a, 0x2cb171df, 0x84cfee08, ++ 0xbfe20cf3, 0x89dde528, 0xe9ff5042, 0xfe683e92, 0x20988cd2, 0xe320dfb8, ++ 0x152bf647, 0x3997f77f, 0x2d0a1fdc, 0x6bdefc15, 0x89475e0a, 0x082fefd7, ++ 0x25a66f5e, 0x4a9fbd78, 0x4f60bd97, 0xec2710d5, 0xe58afb03, 0xa84f106b, ++ 0x84684e21, 0xdfe10278, 0xa5813c43, 0xac09e21b, 0x09e2037f, 0x9e219b84, ++ 0xc410f840, 0xd4b7083f, 0xb8795096, 0x6fea8cb6, 0x790ebf85, 0xbaf2e3dd, ++ 0xff75e427, 0x247d3c56, 0x9e5277cf, 0x4be713af, 0x4bdbb7f3, 0x03bea8c6, ++ 0xdb129e79, 0xb8c1edab, 0x314f4561, 0x3efa2de6, 0x902ed910, 0x1d756623, ++ 0x7b438daf, 0x5fa18436, 0x3efacac4, 0xf54abcc4, 0x4dc6d1c1, 0x7fb3da12, ++ 0xdeed893f, 0xb9425166, 0x65f2da3c, 0xe573ce14, 0x7314703b, 0xb0083b65, ++ 0xf0467bed, 0x00976826, 0x0a04de9e, 0x9b9bec84, 0x3495dbec, 0x19697605, ++ 0x4d8d6594, 0x1553a45a, 0x7fb429ca, 0xb704d6e0, 0x6a0fabef, 0x287f6237, ++ 0xca2ed4ab, 0x516a5c23, 0x7f50f3e6, 0x41609a5b, 0xbed2fbbf, 0x81dfd777, ++ 0xd169b7f6, 0x5ff61110, 0xfc49f8d5, 0xc7a11fe2, 0xcf5e87d7, 0x6f603b44, ++ 0xfe0cf985, 0x1aadecf9, 0xb7fbe619, 0xc71535a5, 0x1468e1a2, 0xae2818d8, ++ 0x156c2db0, 0x96aac7e8, 0xadea1b06, 0x1a798caa, 0xb9f1f806, 0x01bf3945, ++ 0x2afd07da, 0x9c7ee323, 0x62d45afb, 0xf71df798, 0x482cfbb1, 0xa377b6df, ++ 0xb35f5d70, 0x793f1418, 0x727afa64, 0x2bbf44b4, 0x4946efcd, 0xfdd1bed0, ++ 0xdabbc72e, 0x2a3fe743, 0x09283ec3, 0x9d222ddf, 0x153be2bf, 0xef9941d1, ++ 0xe6911cc3, 0x2632de9b, 0xe5d5cf12, 0x9a7debe6, 0xd3fcd123, 0xc12d16d3, ++ 0x9c489ffd, 0x3f92279b, 0xf51a8a08, 0x06d2f8f8, 0xdcaa43f4, 0xf8b065a2, ++ 0x0bce02ee, 0x9c343be3, 0x3b483f4f, 0xf8fa81d0, 0x6c90c944, 0xbf7211b2, ++ 0x97e396ff, 0x0d35ad62, 0x419748ed, 0x7f3e448a, 0x247464ba, 0x9628f7d2, ++ 0x5bb25f58, 0xb2b2856b, 0x65d7af99, 0xbe428cec, 0x15ce6aeb, 0xe651dfd1, ++ 0x3cf94ffb, 0x403dfc03, 0xa9d12737, 0xc06f55dc, 0xe3f4fc79, 0x18e69ff5, ++ 0xd709ffa9, 0xafd1b327, 0x2088caea, 0xcb43a4bf, 0x6aae9e28, 0x57717ee4, ++ 0xe23d725b, 0xd3ef5941, 0xcf2e391c, 0xbd5d1150, 0xdfb91a2d, 0xd41606bc, ++ 0xbafb434f, 0x3f7827b2, 0xdfd9d746, 0x7b6e3fa0, 0x17686451, 0x789a9a6d, ++ 0x9d85ff3c, 0x972bfbc1, 0x78d36cf1, 0xf803e3e2, 0x203ad6d5, 0xf3e20637, ++ 0x244e4556, 0xc742a7a2, 0xcfee0cae, 0x5cea2575, 0x9ada9f18, 0x6faf881a, ++ 0xa67527cc, 0xfc90fc62, 0x3be51844, 0x2b3f156f, 0x7c40437e, 0xd45e30c5, ++ 0x53ce8c94, 0x07fbf28d, 0x312c728b, 0xee3143b9, 0xb2b8a32a, 0x0b3f818b, ++ 0x9fd1da6b, 0xfcbd468e, 0xdd70e787, 0x23f066fe, 0x587b5d61, 0xe0738ccb, ++ 0x409bf597, 0xfddf6050, 0x392e353b, 0x5fa031fe, 0x6bf654bb, 0x7cd6482f, ++ 0x7dafec11, 0x67ce8a8d, 0x38a70ccb, 0xbdeb2bc6, 0xef529baf, 0xb8e1bf27, ++ 0x6878c468, 0xc1fb9b9a, 0xd7ee46b6, 0xff53bb56, 0xedfa3279, 0xe08c1a8d, ++ 0xd887e298, 0xbce43f65, 0x5f9ef7ec, 0xf8a5a7d3, 0xcf605da6, 0x5bca3ec2, ++ 0x432476b6, 0x06733dbb, 0xb176b3f9, 0x6589fc91, 0x07fd83db, 0xe0826ff0, ++ 0xfea17daa, 0x72df9c85, 0xf12bd707, 0x01dca4e1, 0xc61c633f, 0xe4e24533, ++ 0xfb879404, 0x955d3972, 0x04e566f8, 0xfdca0253, 0x4334b546, 0xbe2043c9, ++ 0x2a07ed1c, 0x5b2edf70, 0x8de289b8, 0xaf098755, 0x1c786fbe, 0x84644be3, ++ 0xf8e31f0f, 0x3e70b5f5, 0x57046877, 0xb6078e18, 0x04c2f9a5, 0x33cc1ad7, ++ 0x48a3fb3b, 0x8256313f, 0x2e62b172, 0x982d578f, 0x487285f3, 0xa14fd72e, ++ 0x752ef576, 0xa013188f, 0x72e5e627, 0xcb50b53f, 0x56cf68ac, 0xbec89a46, ++ 0x7ee30c8d, 0x776ad17a, 0x48c3f236, 0x0175c788, 0x8691f8f9, 0xedfb013e, ++ 0xffe78a79, 0x4cc27c95, 0x131351b5, 0x5b191f60, 0xf995fd43, 0xf1f0a341, ++ 0x08df9ab7, 0xf3fc1bf3, 0x11a3be03, 0x26ccd7df, 0x3329dbb2, 0x5c9286c1, ++ 0x2a5c90d6, 0xfc02b9e7, 0x86fc0856, 0x9ba41a39, 0x8a11e76d, 0x73acece7, ++ 0x8e2b8e3d, 0xc628fbe2, 0xce1c20fd, 0xb97227cb, 0xf05568fe, 0xbf6c1b96, ++ 0xab2d9a27, 0xcde26e50, 0x94b9d5d6, 0x7f123157, 0x057994ae, 0x9e8499fc, ++ 0x8aeff441, 0xeba2458f, 0x94079035, 0x046a87f7, 0x5fc82d29, 0xe0ee7ce2, ++ 0x7332ec55, 0x3c464f77, 0x199d2d38, 0xb8ce5f50, 0xa55c2d7c, 0xef02d297, ++ 0x31df9003, 0xff8328fe, 0xe32e31f2, 0x8ac6e57f, 0xb75fd07b, 0xf0978aae, ++ 0xf281c2fe, 0xfcd6ea30, 0xf0f7ca1f, 0xadf913b7, 0x684ce99a, 0xa12d1c5f, ++ 0xfa3526ed, 0xe4433be3, 0xd3e64522, 0x42e0ab7a, 0x83ff507b, 0xe6d1e79a, ++ 0x7b37940b, 0x4f912a10, 0x95fb0fe9, 0xfce1714f, 0xf748020f, 0xf8e2db5d, ++ 0xc23606bd, 0x3e41feb9, 0xcf6a83ff, 0x63ef9411, 0xe62a771a, 0xf9d98e71, ++ 0x065cd53d, 0x9de8090e, 0xca93acf9, 0x83ea88ee, 0x39dc9a1e, 0xcff0e302, ++ 0x23ca3aac, 0x15ddafd5, 0x8b367a89, 0xfde235ad, 0xbec98818, 0xdcdee4bf, ++ 0x47bd08df, 0xf047e063, 0x39d39678, 0x56f65cde, 0x8117c02e, 0x37398946, ++ 0xf4faaf8e, 0xfde21460, 0x6607a3f2, 0x1c6182ff, 0xe60b7a04, 0xca69aca9, ++ 0x27197ba0, 0xf7c8cceb, 0xa7a157d3, 0x93a83f42, 0x670ae882, 0x99f80e19, ++ 0x3df2fac3, 0xa9e9adc2, 0xd34539e0, 0x12a200f7, 0xa1e918ec, 0x782b3a50, ++ 0x1a3566af, 0x39ab7f9e, 0xfffa1739, 0x424aad72, 0xba06f2bf, 0x1e3e82df, ++ 0x44f26f3d, 0xdecf140a, 0x9d0a5e8c, 0x821e621e, 0x71f0c54f, 0x29121ea7, ++ 0x4d7ff87f, 0xeb6689af, 0x67925cb5, 0x1b72a0e3, 0x9337a72a, 0x42ab85cb, ++ 0x4e4437e4, 0x04d2e407, 0xcfd005ff, 0xe48a2aba, 0x4dafa151, 0xed193882, ++ 0xc9a45b5f, 0x27a46ec5, 0x9fb8bbc6, 0xbd8166ca, 0x7914fc20, 0x30f7e1ed, ++ 0x5e02f421, 0x883da0b1, 0xe3e40f31, 0x1c7cf1c6, 0xf4cde3a7, 0x4ef7a296, ++ 0xa331cf33, 0x5c19f740, 0xb9d71f8e, 0xb9555ef0, 0x2dee50cf, 0x7f5ccdb2, ++ 0xc1a79686, 0xa27bc16f, 0x435d194d, 0xd6ebdfd1, 0x7bf0f32a, 0x3a6bd3d7, ++ 0xf1872c47, 0xb2f0a7a7, 0x00bcfd1b, 0xf3ce12d8, 0x7493a781, 0x69dbc44e, ++ 0xf454dc61, 0x4f0b4e03, 0x04e1c7dc, 0xdcf084ad, 0x8046a984, 0xfe4a35bb, ++ 0x7f5969f0, 0x3d3ca8bb, 0xf5216277, 0x887bd813, 0x6560490f, 0xc4208eb4, ++ 0x4e7ec096, 0x0726363f, 0xf39405ef, 0x0fee664b, 0x1db998a7, 0xffb7c818, ++ 0xf6f940a3, 0x8c3a6085, 0xf5302f78, 0x505192f9, 0x469fe67f, 0xe57dd367, ++ 0xd1f5e08a, 0x9e52a6fe, 0x77cd2b72, 0x9a7d77d7, 0x7dfe9945, 0xc2cdd80d, ++ 0xc97ebcab, 0xca478a18, 0x625a1a65, 0xd938f1c7, 0xed1a3a35, 0xfad76298, ++ 0x04301f8f, 0xe57b51e6, 0x3c00f3bc, 0x8129d7ee, 0xdec8f176, 0x9e71d267, ++ 0xcb33ad72, 0xeb17f504, 0xfe82977f, 0x5fdef943, 0xbb5f93a5, 0xc63a6377, ++ 0x9ebbe527, 0x1c10b749, 0x48f8a561, 0x797dcfcd, 0x9bdda4ff, 0xdee8fc02, ++ 0xcc571e3c, 0x84523b0f, 0xdb8cedfe, 0x79875ebe, 0x24ff31fb, 0x21ee1e50, ++ 0xed0eb9d6, 0x2e0c82ed, 0x185b6c57, 0x8f987fe9, 0xc61b49ee, 0xf507bbdd, ++ 0x2f8c89fe, 0xfed04b35, 0x8f84d59a, 0x39b5cc05, 0x1b6ff301, 0xf9bfca04, ++ 0x7ba08ffb, 0x056b45d7, 0xda1c626d, 0x8c6c98d1, 0xc7309f1b, 0xde1e3ed0, ++ 0xf581dd90, 0xfaf3560b, 0x73573a19, 0xbcf3ce17, 0xe120d4d6, 0xcaa36544, ++ 0x9fb1ee02, 0x6db8f330, 0xfc8166e1, 0x319d6579, 0x07d7c5cf, 0x9909f39e, ++ 0x4f9becfe, 0x2fdc1f48, 0xd59ee5d3, 0x0897bc9f, 0xb6ae7ef3, 0x7986653e, ++ 0x7cf6fe4e, 0xc2b3ea1a, 0xe44cded8, 0xeb5a31f3, 0xee78150b, 0x57ca3a5d, ++ 0xc592b39a, 0xf39fe804, 0xb16794e8, 0xd17ab85c, 0xf798150b, 0x71461edd, ++ 0x15bfb298, 0x78c2a482, 0x5ffaddf5, 0xbb788c3c, 0xf230dbf8, 0x8fd457c3, ++ 0xc883604d, 0x02be52a9, 0x19d297f4, 0x8c36b57b, 0x8d6bd7ca, 0xee23824c, ++ 0xf8244daf, 0x2a256b5f, 0x5fce1cd9, 0x5f5c8c2b, 0xdcbe6cdd, 0x0499c2ef, ++ 0x01bccafa, 0xf53f03e6, 0x76cb5acf, 0xcc61e033, 0x8daefb78, 0xc0c6b9f2, ++ 0xea676cf8, 0x7983c434, 0x740ef2e3, 0xf99ad761, 0x5d87e87d, 0x0fc8521b, ++ 0xa5f67d5f, 0x37ff680a, 0xe23d5973, 0x55e76c29, 0xdbbc17ca, 0x8805abfa, ++ 0x3a5df2ef, 0xdcf93e7e, 0x9e9b7f17, 0x79e602f0, 0xfc50d03f, 0xf679d8ee, ++ 0x2e508da5, 0x1b5cbcde, 0xf53fefc8, 0xfbcb2fbc, 0xdd5c95b9, 0xbd7f0f0c, ++ 0x42933d5c, 0xe40bb3f2, 0x976ff32a, 0x35eac72b, 0xe6ebbf84, 0xb788e3b2, ++ 0x0a671a8b, 0x71c5d3ca, 0x3b9f1277, 0xbfc205db, 0xf195c7a2, 0xab79f21d, ++ 0xe4cdee54, 0xfc7aca47, 0x888e443a, 0x17ad23df, 0xbe8fd1d2, 0x47f732de, ++ 0x16a87dcf, 0x9bcc2223, 0xda195185, 0x8eb5af9e, 0xf2f9c136, 0x0e7fdc55, ++ 0x2b33ef6d, 0xb79e7879, 0xe0213fc5, 0x361d8a9d, 0xf68b1d16, 0x8384f04f, ++ 0xdcb7b65e, 0xf8c6abdd, 0x2fc2e20d, 0xf650fd82, 0xbf5d8045, 0x556f7ed9, ++ 0x6a3ce356, 0x789ddebf, 0x013cc54a, 0x4f527c76, 0xac04f338, 0x40af103b, ++ 0x7bee969d, 0x202f4892, 0x943df0dd, 0x2edc75b7, 0x9cb57b84, 0x1043de8e, ++ 0x0cbcf197, 0xe7fdf313, 0x9cbd6dec, 0xf4367a85, 0x2f87d5bc, 0x5ad87f13, ++ 0xa055757e, 0x55ef4ff3, 0xfcfadd67, 0xce5ef647, 0x6af5fa42, 0xfe31f27a, ++ 0xb27b6af2, 0x6fd50e90, 0xd7fe7d71, 0xafa941e2, 0x79e5a0d8, 0x7148c142, ++ 0x85789164, 0xe3de00f2, 0xdd500f3c, 0x69f49bba, 0xc7cf1b7f, 0xc59d5438, ++ 0xa8bf9809, 0xfa81db39, 0xc7913fac, 0x05bf3065, 0xb47936f1, 0x7dd5076c, ++ 0xaf413329, 0x657be499, 0x88bc1e25, 0x79c5abf2, 0x877a36dc, 0xd0c11595, ++ 0xf284b8af, 0x560bf50c, 0x3e47aea5, 0x8a1ae8bf, 0x61f62499, 0x5354ffd6, ++ 0x089deefe, 0x2c7e48a3, 0x6fd006d4, 0x912e1ce0, 0x8a61f43f, 0x2cc11c5f, ++ 0x5a1cfd01, 0xab8a7ee9, 0x39fbf04f, 0x4f2e78c7, 0x279730ec, 0xda23dafb, ++ 0x86f980c4, 0x43fac9e7, 0xbc6727f6, 0x97243ff3, 0x9f963959, 0x811c01e5, ++ 0x4be710ba, 0x8209768c, 0x7fdf2fdc, 0x9368691f, 0x9112f8e3, 0x222d1dda, ++ 0x96397bc3, 0x0aef4918, 0x7a16d84a, 0xb983396f, 0x3d77f327, 0x03b9bf3d, ++ 0x11df4bda, 0x1a1df173, 0xbf74d3f8, 0x4d6e1c5d, 0xdd5a77c3, 0xabc6412a, ++ 0xc0333cdb, 0xdf92ad9e, 0x05164ca5, 0x497d63b2, 0x4ca7e411, 0x8f9f639f, ++ 0xe9fa55fb, 0xcc1fbc54, 0x73167e43, 0xbde165f5, 0x65f4f32a, 0xd2ab7de1, ++ 0x113bf66f, 0x99176435, 0x603b3cdb, 0xdc798d9d, 0xfbc35e6e, 0x0e27d071, ++ 0x48b61ef9, 0x8c39e1fc, 0xf3b456b7, 0x556ec7fb, 0xcef867ea, 0x467809cc, ++ 0xba065eba, 0x58fed05a, 0xf282c599, 0x0ba86133, 0x5fb1c7e5, 0xaf5ef860, ++ 0x0bb755ba, 0x9ad542f3, 0xe7e4789e, 0x6a9f2d8d, 0x781d9f91, 0xc7013b2f, ++ 0x6e5f3933, 0x1d7e2154, 0xf5efc646, 0x867ec65a, 0x71fb3b79, 0xeaed456e, ++ 0x801f284f, 0xabd71b7a, 0xf8a26e6a, 0x143cc6df, 0x831adbff, 0x913fa6f9, ++ 0xe543f3e7, 0x149e6364, 0xb7d31f24, 0x2d98f973, 0x77d41ab2, 0x4ebfce4c, ++ 0xbf204c4f, 0xf64e3fc4, 0xebcbc517, 0x8df18fd0, 0x4c024c12, 0xae770be5, ++ 0x99c8ff45, 0xdf1afdce, 0x979bafdb, 0x99717e92, 0x3cf7c01f, 0x7d3bdfb2, ++ 0x18b556c3, 0x6de99fb0, 0x0be8df3c, 0x8887e567, 0x48e1d6ee, 0xb29cba8f, ++ 0x7cff9067, 0x7793beda, 0xc5483e60, 0xe7a1a3f3, 0xc6bce510, 0x6513cc09, ++ 0x9a5df7fa, 0x19f5cc9c, 0x751f1173, 0xcafaf8a8, 0x7c651d7b, 0x819e7c8f, ++ 0xf9e04938, 0x17e99bad, 0x77c1afbc, 0x835f78ae, 0x7bf26be5, 0x41afbc58, ++ 0x7bf2f7f8, 0xc1afbc58, 0x41afbc7a, 0x0f7e59b8, 0x0835f78b, 0x960d7de3, ++ 0xb0f7e587, 0xf8ab7027, 0xf9f9cf8e, 0x1d17c80b, 0xfcc36b28, 0x086c7770, ++ 0x7fb82c3c, 0x0c10ac77, 0xffa8130f, 0xbf9f8381, 0x3e6034e0, 0x2bdb28d4, ++ 0xb0fd1229, 0x16d611c3, 0xde2f6fc4, 0x1e834757, 0x10f6792a, 0xec6151ca, ++ 0x5f28f9dc, 0x863a71fd, 0x6797c87a, 0x1dfb077d, 0x6d2d3e3f, 0x3d47e92b, ++ 0xff77afdd, 0xca68b6f2, 0x32207de7, 0x929a9611, 0x0cd6bb91, 0x408314f0, ++ 0xe27a0b7c, 0xbe2532f6, 0xb5a67984, 0xb9ab322d, 0x9fa2305e, 0x96da245c, ++ 0x922b3ae0, 0x7fa8b9f4, 0x4f5ae597, 0xe3f50de4, 0xb2d878b9, 0x3a87f434, ++ 0x9867d234, 0xac7e7597, 0x294f1861, 0xdfa53bf9, 0x4e53b99d, 0x19e9b8e1, ++ 0xe0e6d7a3, 0xa86420fc, 0xd65a2ce7, 0xa8b3fb88, 0xd23a8422, 0xf51a925b, ++ 0x8f5929c0, 0x5fb8954c, 0xea4ad1ec, 0xc3e78c58, 0x7de1c4a7, 0xdf4c876e, ++ 0x4f7d32e3, 0xfbc5f4c8, 0x897f7c2d, 0xe2585bf7, 0xa19616fd, 0xf2e2d0ef, ++ 0x23c8beca, 0x04a5f73c, 0x819b63be, 0x4df5c572, 0x460bfa0a, 0xbcf6ff39, ++ 0xcd0a6fac, 0x9c7cbd65, 0x92a9e69b, 0x359777f3, 0xca85f7c1, 0x4678ff38, ++ 0xcedd67e3, 0xd68b34f5, 0xc3bef7f2, 0x13df1399, 0x89337acf, 0x975e4ff2, ++ 0x3a01a9ca, 0x471902cf, 0xe4dec63d, 0xe44b2e71, 0x40eb32f2, 0x93abf502, ++ 0xd8f6a8f3, 0xb458f4ce, 0x295cb2bf, 0xf33fa1f0, 0x1cf648f7, 0x4b7ca180, ++ 0xcfb3e7e0, 0x018f4cea, 0x55e82bd8, 0x5df64fc8, 0x964bbdbc, 0x7928fb3b, ++ 0x2c3cf93e, 0xf4829dcc, 0x99bfb5f0, 0x9bc030f2, 0x5ca59e0c, 0x49d27bef, ++ 0x3a4f335f, 0x2cba6bbe, 0x3be0cfb8, 0x2b43dee3, 0xfabbe1e7, 0x4bf71acb, ++ 0xe87d7f08, 0xcef879b1, 0x74d0b2f8, 0x3ed818c6, 0xef829dd4, 0x3d0f7b90, ++ 0x3687dbca, 0x0a6314bd, 0x9c6f3580, 0xd3ed76c1, 0x042bcd8f, 0x3ae754b8, ++ 0xf37c8b5e, 0xf4bf9caf, 0x479e0ffb, 0x72b554fc, 0xfeea7dbf, 0x40de5783, ++ 0x92307cbb, 0xcd8c13de, 0xd7bc254f, 0x19b2beb5, 0xa4dbcdf9, 0xd4d87921, ++ 0x4f4be9f8, 0xa51d3f52, 0x6e754a57, 0xfa62a633, 0x7da10d0f, 0xbfb84695, ++ 0xe89c5841, 0x0e947da4, 0x361cf2e1, 0x7e1e6eb1, 0xb83de01f, 0xbf9471ff, ++ 0x687068d2, 0xebaf3f71, 0x07953e89, 0x3e6215c6, 0xb9d91bc0, 0x7eafe700, ++ 0x1ddfc74d, 0x8a98481c, 0x3e7301f9, 0x8c576fcf, 0x768292df, 0xd5f87556, ++ 0x5e624fbd, 0xdd3d35f3, 0xb96238f3, 0xd629579f, 0xfa272fe7, 0xef8bdeed, ++ 0xeaafbc55, 0x02b5dee9, 0x57007173, 0x79431dec, 0xf4feb7f9, 0x43a402e5, ++ 0x2f73b891, 0x47b37fd6, 0x743c42af, 0x77d12d69, 0x69761ca2, 0x90acde28, ++ 0x21ee8ae1, 0x3d113f7c, 0xb8bf44c5, 0x6768292d, 0xe3fc872b, 0x52efb87d, ++ 0x184bcb71, 0x7457b0ef, 0xfbd0d774, 0xc60de02a, 0xf06836f5, 0x23ec1de5, ++ 0x72fc8d52, 0xe0b2d859, 0x81bf9c05, 0xdfacbbf7, 0x3674f842, 0x1eb8658c, ++ 0x876863f4, 0x835b0b2f, 0x5e1b7bea, 0xf478c2c9, 0x14a56bd2, 0xae7c2a97, ++ 0x1ee54bc8, 0x243d905d, 0xf98f104d, 0xe8cff94a, 0x3c808664, 0x3b43a5d6, ++ 0xff302fbc, 0x1a8d4bf8, 0x5470168f, 0xf16b63a1, 0x0f22b35d, 0x9777c995, ++ 0x552af9e0, 0xb7e8e9f5, 0x2cf6e454, 0xd5e8b940, 0xe844b0b3, 0xaf6ca1f7, ++ 0xccd79b2a, 0x66f7ff44, 0x9f2a79fb, 0xb2eba3eb, 0xd16f5e1c, 0x19ef02bb, ++ 0xd43fcb43, 0xb523e932, 0x46a87e1f, 0x32bc3e47, 0xb75a87df, 0xeab4e30d, ++ 0xce3fae58, 0xd046ff40, 0xebca4f63, 0xdc155c2c, 0xbf9f26bf, 0xf6d6aca3, ++ 0x53dda3a4, 0x2be7b7e6, 0x1d27ad7a, 0xb8e855f5, 0x37d65152, 0x6fa40baf, ++ 0xb3859b2a, 0xa2091df4, 0xcf8fde34, 0x0ba730ca, 0x460d11df, 0x997cc487, ++ 0x7e97300e, 0xa3ed2a62, 0xd16f51b2, 0xe1553cc3, 0x27e8513d, 0xa27b22d9, ++ 0x1ef1ffd0, 0x992ed916, 0xfcca717c, 0x29ebfca3, 0xb70ac9f9, 0x6c1fa2c6, ++ 0xc60e383d, 0xdff0cbc7, 0x89948a80, 0x5bca6e5c, 0x663d6822, 0xbe47c9ec, ++ 0x3c19df2d, 0x0c69cf0e, 0xcb6f4790, 0x38c0f8ee, 0xdf3e577d, 0x4b384fb7, ++ 0xd3fbe372, 0x07c82917, 0x16b62a95, 0x092f27ef, 0x80103bfc, 0x4b903be9, ++ 0xe5673df2, 0xe47086b7, 0x6dd74b9f, 0xa15ec724, 0xd95cf487, 0x5f495b9b, ++ 0xa43d3578, 0x3e268ae7, 0x9e98e1cf, 0xcab7a805, 0xfd23ee26, 0x59ea4de1, ++ 0x6527df80, 0x4608f029, 0x9bc17ff6, 0xf6879fbf, 0xefe454be, 0x8d6ed827, ++ 0x3887e791, 0x78c997be, 0x77436c62, 0x1a1fc52d, 0x85a4fd09, 0x20fb9513, ++ 0xa2fcffad, 0x4cbc9e5f, 0xf28cdfda, 0x7ca06e59, 0x8d55f80f, 0x37ffa06f, ++ 0x7984de37, 0x29bc50f4, 0xb1718af7, 0x3a452fdf, 0x7d6915dd, 0xc9ef1f3f, ++ 0xbe287b33, 0x3f276e00, 0x1d6dfabe, 0x4d3e99c5, 0x5fd45edf, 0x0fd69131, ++ 0x361f61f3, 0x4c7ae76d, 0xf4d15d4d, 0x3f4ba074, 0xf48df903, 0x6f37e708, ++ 0xfdfe6ee6, 0xf92f7c87, 0x065eb25f, 0x91eac67b, 0xe74e043f, 0x7c0e5b77, ++ 0xdbc6fa84, 0x74f49a39, 0xb6f53ca8, 0x7a851b3c, 0x77d814e3, 0xe01e4067, ++ 0xe857a2d4, 0x7c1cc01d, 0xc3e501ff, 0xd7cf836b, 0x1403c3ff, 0x01cdb20f, ++ 0xdb8fc8f5, 0xbc50e182, 0x827a5f20, 0xfc49c0e4, 0x5bcb2f13, 0x6aced4d5, ++ 0x3c00c3c4, 0x0031600b, 0x87021a3e, 0xdc6567f4, 0x5a07887f, 0x11b6bce3, ++ 0xdf8a6e9e, 0xbd77f3f7, 0x08d76075, 0xf741183e, 0x60fdaad2, 0xddb8e2b7, ++ 0x15517b42, 0x2b7949d5, 0xdd1d41ef, 0x7add3ca7, 0x0fcf0521, 0x99f948fc, ++ 0xe337d6aa, 0x9b1fae31, 0x6a3f712f, 0x7a78c1ff, 0x35b0730f, 0xa510e31e, ++ 0xa772a6de, 0x6417dfcb, 0xea50fea1, 0x1d27a2ed, 0x74255ff7, 0x58fb6166, ++ 0x07f537dc, 0xd1984458, 0x97026c39, 0x922ad67b, 0xdba50f9e, 0x36fdf930, ++ 0x7a2c87e8, 0xe79871c7, 0x507d140d, 0xa395eb21, 0xe5c99f58, 0x47dca8df, ++ 0xca12fde1, 0x627a20fd, 0x564782bb, 0xf89d7943, 0xcadf7c89, 0xe7979a78, ++ 0xbd7bf89d, 0x8d672eb7, 0xd271c4ca, 0x01ccbbc0, 0xafda347d, 0x240f505f, ++ 0x5a781e92, 0xaae70f13, 0xd530497c, 0xf98a90c1, 0x3ba18a6b, 0x5e5ea65b, ++ 0x7c34f94c, 0x71b86b97, 0xd47ca15f, 0x52a9e324, 0xcaefe3c5, 0x2bdd02bd, ++ 0xfbf0d25d, 0xf437d03a, 0xc2b2c05d, 0x7f28c535, 0xb5d9c48f, 0xadf27181, ++ 0x2dba5fe6, 0xb3565e18, 0x106138a6, 0xb55caf39, 0xbb2863b5, 0x6b0abe71, ++ 0x74bc717d, 0xefb2bd63, 0x9f657a4b, 0x03433553, 0x4d6731f1, 0x972850f1, ++ 0xf8adfd85, 0xd4bee7e0, 0xdda0f3aa, 0xfdd2fc05, 0xd5df5df0, 0x6f57e504, ++ 0x73055f35, 0xcdc7fdd1, 0xda5a1ff6, 0xe6374f04, 0x57c81893, 0xc819c903, ++ 0x877ac04d, 0x1d7eb9f3, 0x2f944bc8, 0x2971891a, 0x191a2eb3, 0x2d089798, ++ 0x15198bf1, 0x527111bd, 0xc0b87209, 0x943e0834, 0xf226cbfe, 0x65874977, ++ 0x5a561e3e, 0x460de3b5, 0x27479cf9, 0xf7f9bd0e, 0xfac94f25, 0x5f7f27ff, ++ 0xf7822d32, 0x311bd76b, 0xff6be3ef, 0xbec2f29e, 0xfc398675, 0x92c0c1be, ++ 0x7123bda0, 0xfcc0aec2, 0x2e02b0ef, 0xee6611b7, 0x343238ef, 0xca579e3f, ++ 0x2bc81c8c, 0x1991bf91, 0xde2cf741, 0xdf646b96, 0x46796d7c, 0x76f10fbc, ++ 0x6f280cba, 0x31fd3f8e, 0xb7b0ed1e, 0x8f7a2bed, 0x02e1fde6, 0x28db53bd, ++ 0xda3c17bf, 0xeaf3bf22, 0xdeb12294, 0x3165f257, 0x9724dbf6, 0x8682bcfe, ++ 0x4a94a1f0, 0x978940de, 0x21767e21, 0x1b8c1b3e, 0xf586637f, 0x7c96d859, ++ 0x3f1007d4, 0xf0dda2c7, 0x84a413e7, 0x812ff2c1, 0x353484f9, 0x896027cf, ++ 0x34b484f9, 0x18404f9e, 0x625809f3, 0x31eb013e, 0xe630809f, 0x7cc61013, ++ 0x4f98c202, 0x09f312c0, 0xfc8dff58, 0x140f877d, 0x1a77cf17, 0xc4afef48, ++ 0xbf80cd77, 0xdefced95, 0x4883656a, 0x7df8c1f7, 0x1bbfda07, 0xcb34ebde, ++ 0x5bdc75ef, 0x71d01ee9, 0x89213450, 0x67103bf0, 0xe9dbbe3a, 0x2079863b, ++ 0x5a609347, 0x1cfd6123, 0xb6c6c7da, 0x63e6cfbc, 0xa4c6837d, 0x389f8892, ++ 0x9705eb3d, 0xadaae51e, 0x8556f281, 0xcef4ed09, 0x3028d1df, 0xd6ceb7cc, ++ 0x2ed938f1, 0xdd0e6d42, 0x6d1f92a7, 0xfc5275d7, 0x904fb552, 0x76f7bf02, ++ 0x3d255c14, 0x2f53dca1, 0xeecc4de5, 0x824b4bd6, 0xbf85acec, 0xc27fc2b7, ++ 0xbbf2ec7e, 0x0243f26e, 0x78a5a2fc, 0xe2f58d7f, 0x899df40f, 0x21dc021d, ++ 0x5bdfadc2, 0xad35b655, 0x3f5a77c7, 0x85d5ddf5, 0x757df289, 0xa47eff36, ++ 0xf64bb7e4, 0xfaf5841f, 0x4fc8e8b7, 0xbd59e5f1, 0x7df0f313, 0x2ef28581, ++ 0x14f5dac7, 0x3adb9d67, 0x52ef2836, 0xbca70e24, 0x408d0ac7, 0xae597bf6, ++ 0xcbe41bf5, 0x298b2569, 0x312d32df, 0xe158e492, 0xcb733bc3, 0x5779c5be, ++ 0xcf28904c, 0x8f63a455, 0x3bf27cd1, 0x454e852e, 0x054b8275, 0xa26622f0, ++ 0x021606ef, 0xea1f30fa, 0xe03618d3, 0x8c85ab7b, 0xf850abbf, 0x8156c56a, ++ 0x0f130af8, 0x3205e788, 0xbdb6173e, 0x9bbe3dff, 0xfee3ac58, 0xdf8ab26f, ++ 0xe26f278f, 0x611e27ef, 0xb2377a56, 0x244fb90c, 0x0f76fafb, 0x86235bd4, ++ 0x5eff70a7, 0x17f9c04a, 0xbbd0d09d, 0x7b84a2e0, 0xe764add3, 0x84dde90b, ++ 0xfe2799e0, 0xd31fb6e5, 0x26efc19f, 0xdeb8698e, 0x9c527c01, 0x4afc81d5, ++ 0x952b1ef9, 0xa9cb6a27, 0x06cd933c, 0xd7cddefd, 0x8e1366fe, 0x4c18722f, ++ 0x7e9bff88, 0xe3fe17ff, 0xf119bddf, 0xe21e5d5d, 0x42572ba3, 0x306b7c7c, ++ 0x128a3e21, 0xb0fbe9da, 0x59fcf2d1, 0x05996539, 0x144b0fb0, 0x78fae273, ++ 0xf005b33f, 0x12078c5b, 0xb6ee7f30, 0x7d35f7e0, 0xde9182ed, 0x47a0df51, ++ 0xf7c3aeb7, 0xc1348e29, 0xe2da7988, 0xf1452df0, 0xa8f17f30, 0x71ea1354, ++ 0xbfcf0b47, 0x7ce4a17a, 0x144b8770, 0x3c7558f8, 0x1d39ede6, 0x3fac72eb, ++ 0xafea182f, 0xcce5952f, 0xbf8d76d7, 0x7e75be1f, 0xefce0f76, 0x6efa7a64, ++ 0x5f60fe9d, 0xa08db7a5, 0x47c2ad3c, 0xbb098dfd, 0x281e8f90, 0xfe68f6e0, ++ 0xe8344ffc, 0xad9a1447, 0xfde015f7, 0xebab92f9, 0x839ce9e2, 0x7794c9e7, ++ 0xb279a1f7, 0xfffb7d40, 0xa3fedef1, 0x4f2a1ada, 0xb2a2aed6, 0xdbc9d6b3, ++ 0x208fac23, 0x9e427ede, 0x483056d5, 0x4985959e, 0x416764d1, 0x3b3e79de, ++ 0x720aaf24, 0xf3900aae, 0x0f316d69, 0x643f406f, 0xf784d69b, 0x79def8cb, ++ 0xc2f481a5, 0xe68305e3, 0x19bc1557, 0xcfdb1f28, 0xff8839f4, 0xd5a319a9, ++ 0xca77682a, 0x6fc95af6, 0xf9e0bca2, 0x44b05e50, 0xfdab5179, 0x16a2f2f2, ++ 0xfdccda44, 0x05f92702, 0xfaeba27a, 0x004fa035, 0x418ccc5e, 0x884ae4fa, ++ 0xe600813e, 0x587df497, 0x126d8e9b, 0xa73deffc, 0xce5df142, 0xcdc5fa20, ++ 0x7088cbf5, 0xbbf4abf7, 0xf4e1d50a, 0x9ce4189e, 0x46d8ebf8, 0x096f4efe, ++ 0x0775a32b, 0x5df433d1, 0x7d21e2cf, 0xfd077e67, 0x20633f17, 0xd27d66ff, ++ 0x47bffcd2, 0xc0593ccf, 0xfe3cf1f1, 0xc7fa837e, 0xb361bf7e, 0x2baff780, ++ 0x48d9621e, 0x1bf7e56f, 0xc50c6012, 0xeffd7fbb, 0x9d233437, 0x0674c81f, ++ 0xc2437efd, 0xe1bf7e4d, 0xe68796ad, 0xc37efe07, 0xe78b2d5b, 0xffc1be63, ++ 0xcd0f0dfb, 0xfdfe3fff, 0x7f71f786, 0xf0dfbfa1, 0x93f48151, 0xfc01bf7e, ++ 0x4e518fd8, 0x9396d91c, 0xe7cb2658, 0xf95efd0e, 0xd8ef7c84, 0xc7ceb2a1, ++ 0xa9ca38b2, 0xcb957aa6, 0x2a87e58c, 0x0fc4a3f7, 0xc4ffd6b9, 0x9b3f14fd, ++ 0x877e9e3d, 0x77a6e745, 0x5ae677e4, 0x17f9c73e, 0x0bfe58e5, 0x7f3cd0cb, ++ 0xd83e7c9d, 0x7b637fcf, 0x85317be8, 0xf595be2f, 0x39651fd8, 0xf8375c9a, ++ 0x2c7ffb77, 0xf27ac950, 0xfb0df7c7, 0x957ee1f5, 0x8b2db3fd, 0x78ddf4cc, ++ 0xeb0fa5ae, 0x4957bf61, 0x83621b4f, 0x91bdfbbe, 0xdeb49d5f, 0xc9efe51f, ++ 0x9e962f40, 0x95287ee3, 0x0c576ae9, 0x9ec30bfa, 0x7ee0c572, 0xe9f7d587, ++ 0x978ffbf1, 0xf47a7d9d, 0xdd5e5e1b, 0x97fac7a7, 0x767dfc2d, 0x2693fce8, ++ 0x7d2438f1, 0x1f8d1f72, 0x52756b09, 0x8317d05c, 0xf97a5afe, 0x28e75a7b, ++ 0xf4ad2efa, 0x24bf905c, 0x948f7c91, 0xa53e46eb, 0x230fc862, 0x6efe3077, ++ 0xec8e30b1, 0xef18655b, 0xa3d4f95a, 0x71a3e42a, 0x0077d82e, 0xaedd8dff, ++ 0x8efe0fee, 0xaae343d7, 0x4fc025e4, 0x33b76a0b, 0x98749efe, 0x4fd08fac, ++ 0xc6fa0f9c, 0xf7defe5e, 0xadc17ef4, 0x7e8f9909, 0xfde060e3, 0xf5987564, ++ 0xde891eed, 0x5bf50627, 0xf5c9ef3a, 0xcf96cf18, 0x78a5aadf, 0x7ad34978, ++ 0x4fb66d2c, 0xfc8c09b4, 0xe0fea0ca, 0x37c10657, 0x1f6433ec, 0x5d5e8fd5, ++ 0xbac8309f, 0x933907c0, 0x707cfcf2, 0x871ee34c, 0x7b31e9f1, 0xdf7f89b8, ++ 0xa1dfa6e0, 0x877f25d9, 0xa65ffbbe, 0x58fbf99a, 0xfe3017ce, 0x127e9367, ++ 0x7f51d51f, 0x819654e7, 0x52ab7372, 0xbf0383d1, 0x4e65a36b, 0x88ce53ca, ++ 0x90e73d24, 0x25eabee3, 0x1443f246, 0xbb56aeb9, 0x7ec7aecf, 0xbdfc9171, ++ 0x68f41a9b, 0x0d2fde1c, 0xf4dbf7a3, 0xd18cf087, 0x5f158f74, 0xbce0f6e7, ++ 0x260af77d, 0x46171bcc, 0xa45abd70, 0x02bdb32a, 0xf8a9efed, 0x88bc08ef, ++ 0x77c443fa, 0x05f7fc13, 0xbcf364ce, 0x3efe2270, 0x9057bd09, 0xaf3e30f2, ++ 0xc23b2c13, 0x3ce52c44, 0xf6818568, 0x9ca973e1, 0xb6cf381a, 0xa58ed718, ++ 0x0f6dcf80, 0xee9f9266, 0xbfa0fdc3, 0xc7df8733, 0x9b298b6d, 0xe7db1cbf, ++ 0x43f6a78e, 0x6bfd1e7f, 0x22afee33, 0xdb7e84dc, 0xe7ee6cb6, 0x41999b6f, ++ 0xd2096fed, 0xce13b41a, 0xb3ad18a7, 0xdf3f266d, 0x908f5fb6, 0xe9714fbf, ++ 0xea6f77e9, 0xcf78492d, 0xbaca3c36, 0x4c3de902, 0x96dc67be, 0x3e50f50a, ++ 0x7dcd9427, 0xc099e704, 0xdefcabf7, 0xe3b9b1c0, 0xe397bd7f, 0x5df783d1, ++ 0x1491198e, 0x922fffa7, 0xc06a0a3a, 0x00c06a0a + }; + + static const u32 tsem_int_table_data_e1h[] = { +- 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x33b3af8a, 0x21716830, +- 0x9f0143f8, 0x38606664, 0x8167c40d, 0x81859798, 0x818997c1, 0x78898fc1, +- 0x10c533fd, 0x0611416c, 0x5e203b06, 0xf0c0c42e, 0xce21044e, 0x10c0ce28, +- 0x20c0ca2d, 0xafe10a2b, 0x6266d204, 0x40ff71d4, 0x4c194663, 0x089207b1, +- 0x79161336, 0x268ccc64, 0xca8520ef, 0x7fa02167, 0x2517f1a0, 0x22acbe54, +- 0x8a846e84, 0x9793457f, 0x432bca83, 0x094df5fd, 0x502ab9bb, 0x1aa00079, +- 0x03605f82, 0x00000360 ++ 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x3373f78a, 0x45e6fc30, ++ 0x5e0287f0, 0xb0c0ceca, 0x0257881c, 0x56204bf1, 0x50606364, 0xff5e2362, ++ 0x5b04290a, 0xc181825c, 0x8aa78805, 0x0812f901, 0x06696171, 0x06495486, ++ 0x08497506, 0x76900b7f, 0xeddca294, 0x2b1b0183, 0xc9098a60, 0x5826d821, ++ 0x29b191e4, 0x1c917c9a, 0x808cdf2a, 0xf3c681fe, 0xfbf951d4, 0x16b42155, ++ 0x9a3e7c54, 0x7ca801fc, 0x0b5fd428, 0x1b9bb1d4, 0x27bfa646, 0x006840b0, ++ 0xf4f4f7fd, 0x00000398 + }; + + static const u32 tsem_pram_data_e1h[] = { +- 0x00088b1f, 0x00000000, 0x7dedff00, 0xd554780d, 0x733ee8b5, 0x49999cce, +- 0x21264cce, 0x61021309, 0x40a02092, 0x200c7e18, 0xf7f09d78, 0x803aa568, +- 0x07515a56, 0x43f21081, 0xbd1f5202, 0x24266bed, 0x1bd568c1, 0xab45a8fa, +- 0x68a90076, 0x62348ed1, 0xa80740a8, 0x0db6a85c, 0xc7f42ad6, 0xc405ad1b, +- 0x96aa4490, 0x6bb94abe, 0xe64fbdad, 0x4019939c, 0x6f5fb7bd, 0x6fd697bf, +- 0x67d9cfb3, 0xdfd7b5ef, 0xb5ed6b5e, 0x897628f7, 0xec650ee5, 0xc75dfe02, +- 0x319902d8, 0xf4a27576, 0x0d0ebbc1, 0x07f8adfe, 0xccdd2832, 0x2862b12f, +- 0x2f6e2cfd, 0xfc707281, 0xd65e9618, 0xf37e18c9, 0x959905f1, 0x3271e632, +- 0xb09417f1, 0xdaf2f5ee, 0x6d87b2b7, 0xd5b28428, 0x6cc653f7, 0x67aaed8c, +- 0x44f66181, 0xff57873b, 0x91c17e2e, 0xfa4870cb, 0x877560cb, 0xbb87c187, +- 0xb6e2e7a4, 0x8ef58c89, 0x7e2d8161, 0x5dde0718, 0xcffd059b, 0x316dec61, +- 0x704605e6, 0x8a50b85c, 0x4b8231df, 0xe73af8fb, 0x0ee76842, 0x00c55fad, +- 0x7334cf5e, 0xb9a26d7b, 0xf50d18ee, 0xa5fa8991, 0x6ca603da, 0x881de00c, +- 0xed5c03f0, 0xd79a4ef5, 0x81bdeb8f, 0xb6305761, 0xf547dea7, 0x2a7ef57d, +- 0xe923f5e3, 0x00fa81f9, 0xb05873d5, 0xeac7f090, 0x66ca2c36, 0x8536f1ac, +- 0x7412c7dd, 0x8c3d66f9, 0xfea24577, 0x222cd1a7, 0xa4fee4c3, 0x00423bb0, +- 0x132bc36b, 0xbca13a32, 0x7f41db1f, 0x28018d0f, 0x3fda26c6, 0xdce5f6bc, +- 0xcb181399, 0xdc91eafb, 0xbde00399, 0x46c616c4, 0xd2ad78e3, 0x9df031bc, +- 0xdbd1fbca, 0xeb6325eb, 0xed9a0f88, 0x65afdfc9, 0xf2cf0212, 0x7e60ac0e, +- 0x0f6bf437, 0x07013be7, 0x04c644b7, 0xb8c3065b, 0x186bec48, 0x111b32fb, +- 0x370e0089, 0x8c799761, 0xf342d0ed, 0x5f1cbbf0, 0x91230a48, 0x299c40c3, +- 0x2cab658c, 0x470a4b1c, 0x2b71c103, 0x4b0733fe, 0x0f4bd53f, 0x7ef571f2, +- 0xe711b2f4, 0xcee4e507, 0xde2c5b30, 0x77fbe197, 0xe862d242, 0xe7c5d9bf, +- 0x736302f3, 0x1249bc70, 0x12b9610b, 0x2dfa1299, 0x312732c7, 0xe5c60aee, +- 0x6173bae1, 0x547e8416, 0xc785985f, 0xfc837ef0, 0x6c8ca6fb, 0x1b7f9b9a, +- 0xda9443f1, 0x474ddb1b, 0x88b6fcb8, 0xedc7033d, 0x23ed883d, 0xf6c3163e, +- 0x39b6682f, 0x3b44b45b, 0x6e499e1d, 0x968b685b, 0x16c82fe8, 0xe5d3fa9b, +- 0xbe72764d, 0x81def9d3, 0xda9c809f, 0xc228fbe1, 0x3705983b, 0xbdebc127, +- 0x07a5be62, 0x3c06415d, 0xa3542ead, 0xafa9242e, 0x39eb0cb5, 0x0640594b, +- 0xe5eb4e1a, 0x0703b8f3, 0x3bcc49c9, 0x37c003e7, 0xfec01d94, 0x08e3e60c, +- 0xda03a8b0, 0x826b79ab, 0x1f4f5065, 0x1b02d5cc, 0x3672631c, 0xcdc473c9, +- 0x97a1c3fa, 0xfc13c7da, 0x00df1748, 0x0604ef5d, 0x41dba832, 0x78020ca1, +- 0xa83b8f1a, 0xe5dc8fff, 0xfd33b143, 0xf1f553bb, 0x3e414b71, 0xa61fd74e, +- 0x83beabb2, 0x63faeeca, 0x0f1aa654, 0x26c6d124, 0x60df8c03, 0x5dca2741, +- 0x075d12a1, 0xffee37fd, 0x218ff32a, 0x878823f8, 0x2d16cd74, 0x4e665e42, +- 0xf815cd59, 0xe12b7c45, 0x8e6ef9bc, 0xbdb3c45f, 0x866d0950, 0x2ad9cf32, +- 0x786d1aad, 0xfc40740e, 0xb87c1e97, 0x2ea4f101, 0x855ce365, 0x4f9c2f28, +- 0x97c89f11, 0x5f381abb, 0x284efd62, 0x029539af, 0xef1c5def, 0x53a9dada, +- 0xc06099df, 0x5c82c29f, 0x28bf39ae, 0x78c77ff0, 0x7b343a80, 0xbde82645, +- 0xbc077fbc, 0x9e7d268e, 0x906b95c1, 0x9e2adea1, 0x30ddebac, 0xabd27e23, +- 0x5079edc0, 0x97cfac1f, 0xf8897ff9, 0xfa04dcd8, 0xd57eeb09, 0x21fbc2af, +- 0x70e0f5a2, 0xca545cc5, 0x1ee7cb5b, 0x62bc6092, 0xa8fde3f9, 0x29d487de, +- 0xf41a776f, 0x6042c165, 0x86c622bc, 0x2f3f35ae, 0x30eb988c, 0xf3042d80, +- 0x3f316e2f, 0xd9dcce3f, 0x2e19d227, 0x80906e48, 0xbd5af37e, 0x849a45ec, +- 0xf58dde95, 0x0dd9ae2c, 0xf427a175, 0xdc99e4ba, 0xadf98119, 0x900592be, +- 0x449269c6, 0xefc56c78, 0x141e8f80, 0x7e96fde5, 0xac9952f4, 0x02ef50d9, +- 0xf4c983de, 0xd654be58, 0x56bc748b, 0xfd8bde9a, 0xe6312ba6, 0x54bf90d5, +- 0xfb6b13e2, 0xf1a14934, 0xa08e94d3, 0x14deeb8c, 0xb6adeebe, 0x9e51c6f7, +- 0x03f99756, 0x028f5c11, 0x4cdf9251, 0x5e50b358, 0x363c013f, 0x9363c389, +- 0xf5189c68, 0xdb2beb03, 0xbc38e122, 0xfa57d5df, 0x0d4a4459, 0x2d191fe7, +- 0x1698ec62, 0x3cfec4ce, 0x709ca492, 0x58d3e826, 0xb36ff451, 0xc372eaa1, +- 0x7513abfb, 0x7c739ddf, 0x4379c7c8, 0x772bf4cd, 0x7f2015d6, 0xb3628654, +- 0x7a4e7f91, 0x0edeba7e, 0xf602def3, 0x9ff80282, 0x61e50ce4, 0xea8b353f, +- 0xf30aa386, 0xe303a2e3, 0x1eb7b26e, 0x39824b07, 0x5ff48859, 0x0175cccb, +- 0x67dbde05, 0xf03b712a, 0x01f27da5, 0xac5c57b2, 0xc9c7eb8e, 0x07b43291, +- 0xef83239c, 0x455ef0ca, 0xdee78079, 0x75c32b60, 0xbccc39c4, 0x9b3c83ce, +- 0xb9b64aea, 0x5ccf4a9e, 0xf8ca5caa, 0x84069efa, 0xb267fc22, 0x995fe228, +- 0xf841281c, 0xf3e6bc1e, 0xaa67847e, 0x84a5d7c4, 0xde72e2fe, 0xbfb5ef47, +- 0x00361dc8, 0xf972b79f, 0xee4afb5f, 0x8f8809b0, 0x73979a56, 0x0b926ac6, +- 0x7323f115, 0x13b90ff9, 0xf878ebdf, 0x961bcf7b, 0xf4979a05, 0x5027f393, +- 0x6f3e363f, 0x9f9ea3f7, 0x7e3dbcf1, 0x366bd41d, 0x6df7a44b, 0x9f845cfb, +- 0x3d7947ee, 0xd88356ee, 0x5013ccfe, 0x3ad57c07, 0x8a9c1e3a, 0x665e7bf8, +- 0x0b3d085b, 0x4ecfa86d, 0x3b68f6e8, 0x78bb97af, 0xfef366b5, 0x8afbf1db, +- 0x7d430776, 0xf97bb35c, 0xbea1530d, 0x619db0fc, 0x0d6d9a93, 0xafa820ea, +- 0xac314a88, 0xf4e74cf7, 0xa392ec89, 0x8f7da0db, 0x66f723a7, 0x271dd70d, +- 0xb8008ff3, 0x37b91ddd, 0x46571f01, 0xdf8d9b9f, 0x0290ee55, 0xc7983140, +- 0xf07943b6, 0x5253cd5d, 0x5c7c01c0, 0xf99d3db5, 0x89e5f60d, 0x1d7e3936, +- 0x93cc19ca, 0x59cbbf41, 0x4fa46ceb, 0xaa0db6cd, 0xd39f40df, 0xdf9923f5, +- 0x3cd7a891, 0x77c0e305, 0x02959f2b, 0x3695c538, 0xef753f6e, 0xaadc2d76, +- 0xd41afce1, 0xd79c6ee1, 0x5bb62a3d, 0xcbbc5d1e, 0x36f847e5, 0x7de1b3ab, +- 0xd59ba3e5, 0xa85e8372, 0x640a3eda, 0xa6d700c9, 0x24e181e2, 0x0f01237a, +- 0x8953c133, 0xedd6867a, 0xa5768aa8, 0x2daa7cfe, 0x6ab1f893, 0x5fea6cbb, +- 0xd7e47ba7, 0xc887ec8c, 0x55e1375e, 0x2f6adba7, 0xa08eebe3, 0xa0af59db, +- 0x6a5bd2a3, 0x1f2f5fec, 0x50383a44, 0xfca97b5f, 0xca8fbd56, 0xa27ef58d, +- 0xbf8843cf, 0xc64edc11, 0x97d760e7, 0x827b2f21, 0xc3ec0bcc, 0xcb06e6b2, +- 0x0acf50ec, 0xa2ee7af1, 0xc8bfe4b0, 0xec12f5fc, 0x04e0c5de, 0x7afdfac1, +- 0xf63b0150, 0x8abc3521, 0xa6fc6005, 0x04ce08ff, 0x528ff77b, 0x4afa8638, +- 0xb82b85b6, 0x287cc5dc, 0xfac5eb77, 0x13f25db3, 0xa9e7d61e, 0xba1f6fa4, +- 0x2cab74ad, 0x6366b989, 0xf7fbfcbd, 0xbb3f5215, 0xfa151fa9, 0x3f74be29, +- 0x364fb7b9, 0x7b7b93f5, 0x01cfde85, 0xf2ed27ea, 0xf6e879fa, 0xdcf0cc6b, +- 0xf3f7a95e, 0xb9e3f532, 0xdee579bc, 0xcf0ccd31, 0xcfd4d51d, 0xd20145c0, +- 0x3fceb2b7, 0xb43bd60c, 0x8e647717, 0x5341fa37, 0xc0dfd36d, 0x520dc5f5, +- 0x8ca3e465, 0x792669c9, 0x99660cca, 0x0ce603ea, 0x09cfb532, 0x0fde9915, +- 0x8595785c, 0x89ef352f, 0x408ea251, 0xf68b43a1, 0xf49520f1, 0x2720d94e, +- 0x20f77fc1, 0xddcef48d, 0xe04784d7, 0xa2b08e3a, 0x1ab7737f, 0xea4deb1e, +- 0xcc4874c7, 0x86dfa587, 0x3dfdf5a5, 0x9e9c1ec2, 0xb7f0f1ff, 0x5b5afbe0, +- 0xa84cf0ef, 0xfb2b6bbf, 0xbcf9e233, 0x3269ffd0, 0x6976c3ab, 0xeffa460e, +- 0xadd2c29e, 0x5b5e0311, 0x48bf0086, 0xec5b7e89, 0xa3f21f61, 0x901a9364, +- 0x510fd73f, 0xfa041b19, 0x1fdb1d74, 0x9ee73581, 0xc43ee521, 0x2ffd03bf, +- 0x8c2af8e3, 0x77c69a3f, 0xb77c60d8, 0x8ef8f92d, 0xf1a6c9a2, 0xa615059d, +- 0x8c2a9df1, 0x6991f20f, 0x9df18973, 0xad6617e4, 0x8ef8d273, 0xff1a0a82, +- 0x9855951e, 0x1beb4fc6, 0xc60da07f, 0xfee3621d, 0x17f9bf4a, 0x7f9e635d, +- 0xfe79a541, 0xa17f9f2a, 0x9f8c532d, 0x5a2ff346, 0x2ff3e5e7, 0x77f3e4a8, +- 0xc6fb7ef0, 0x7fe1f4f7, 0x263f8e04, 0xe28ef8c5, 0x0ff9e669, 0xdfcf36ad, +- 0x671fc7c1, 0x6be313cb, 0x75f8fe34, 0xa1ff3e3e, 0xeabe34d5, 0x8f900708, +- 0xbab4fcd4, 0x8343da28, 0x240dfb41, 0x72a4181d, 0xbb93f724, 0xe38222a4, +- 0x77ce34ee, 0xbf01a51f, 0xca7d0969, 0x9e29eba2, 0x74f052b2, 0x35328ed5, +- 0x07bc5a3c, 0x00997f7b, 0x4cbb6975, 0x3a36cd7c, 0xbc0057a2, 0xf932eddd, +- 0x5e374b3b, 0x3d69951b, 0x1808fee5, 0xfe7c7190, 0xd98f6fc7, 0xb5979c62, +- 0x3f6ad65c, 0xab9069d1, 0x9d3efd3e, 0xf803ac8d, 0x535e4836, 0x69e804fd, +- 0x06dea674, 0x49e58c7d, 0xf3c0338c, 0xb38f4077, 0x7ffdfd11, 0xd1b5eee8, +- 0x0a2faf30, 0x1c284ff8, 0x48d627df, 0x47ffc451, 0xa8a9561b, 0xa6b596cf, +- 0x07d3d1a3, 0x53a0ad47, 0xd9076eef, 0x3f4f8055, 0x1216e7e2, 0xbf7ec645, +- 0x24870bef, 0x6f967bb0, 0x6efa601a, 0xfb368b11, 0xfb92fda0, 0xc2f10f17, +- 0xe85d6ffc, 0x1f932f18, 0x91b7cc18, 0x1b7cb31c, 0xdb0b4ef8, 0xa1f3d836, +- 0xbb42cb72, 0x52f94fc9, 0xb5bf5cd8, 0xb6ef5cc2, 0xcf18ed47, 0xb1215eea, +- 0x6defd0cd, 0xff8b7675, 0x6159c7c3, 0x08f112cb, 0x8117de3e, 0xe8f07986, +- 0xe3c72c36, 0xf5d12f63, 0x56ff2f76, 0x6bf6a787, 0x90547076, 0xe8399d7e, +- 0x0e48b347, 0x2f6177f9, 0xde15b79f, 0x60ceeddb, 0xfdb9e008, 0xd3e132ab, +- 0xbee77f0a, 0xec0da0f4, 0x7f4dced1, 0x6e7da3b2, 0xfe158f9d, 0xe75ad63b, +- 0x7d7155e3, 0x3eb11c58, 0x5aec988f, 0x2f6dacbd, 0x818efadb, 0x9f626a9f, +- 0xe18efadb, 0xf3edaabb, 0xd115f54c, 0x2fda992f, 0xf4d8b4df, 0x0aeb597e, +- 0x2d25fbd3, 0xc5f54cab, 0xda9aaf91, 0xc1b6b1df, 0xbab6fef4, 0x6fef4d7b, +- 0xaa60d8ad, 0xb0fc297f, 0x0b2dfda9, 0x4bde9b37, 0xed0c56fb, 0x1e1abd24, +- 0xeb76879a, 0x59f90771, 0xf2ebbf3a, 0x16ec0a70, 0xdd834f2c, 0xca036582, +- 0x6dbfc829, 0xb76b2f37, 0x35ea1e2c, 0xed2761f8, 0x4f280575, 0xe2b7be56, +- 0xf0dfcad3, 0x1d6c9f97, 0x8c6acbd2, 0x3dbf4143, 0x24393f16, 0x1f1ea0f4, +- 0xdcb956ac, 0x9bccef56, 0xb57ffe8e, 0x975e1f1a, 0x93ec4fc4, 0xf34498e7, +- 0xe7a56860, 0x5b80dd20, 0xdaab780d, 0xb3826c5e, 0xe34cbf6b, 0x05d944af, +- 0x0a5f37fd, 0x88f5c71d, 0x2c160fc5, 0x04f08318, 0xf6f5437f, 0xbb7f5a1c, +- 0x7d6ce7ea, 0x0bf88ec7, 0x7eaa7951, 0xea279521, 0x53be54c3, 0xdbe5415f, +- 0x765475f5, 0xf2a5afd6, 0x9508facd, 0xa16fabbf, 0xadf537f2, 0xdfab1e54, +- 0xf5ebe544, 0xebbb2a51, 0x7cea5483, 0x4327a7db, 0xfe156ec2, 0xb7224805, +- 0xe45cc55b, 0x96b8bedc, 0xacf1e50f, 0xb470d1f6, 0x031ecfcb, 0xc6a61722, +- 0x521f9597, 0xc90595e2, 0x028f28ae, 0x7ff4079d, 0x74e34aef, 0x1cd8d972, +- 0xdee37a06, 0xc01fbe2b, 0x15d41338, 0x47df8596, 0x49dcf303, 0x107f05fa, +- 0x3a2975e9, 0xc96f60b1, 0x89c7a07c, 0x8a5afe47, 0x456c86fd, 0x28385edc, +- 0xe2c97ad3, 0xaf48035b, 0xe9378a4f, 0x402fbf27, 0xa39339b9, 0x00a3afe3, +- 0xb2df04e3, 0xb39fa979, 0x20a60e6d, 0x47a4f71e, 0xf67d2431, 0xae0f56f0, +- 0x727dab77, 0xb31f18d4, 0xc2b13596, 0x4f9866a8, 0x7eb9bb6d, 0xc39a55b6, +- 0x8cfe69e3, 0x5f20c69b, 0x50efa379, 0xa547d15c, 0x9f6acfde, 0xfee8e34a, +- 0x4991db38, 0x217e0a7c, 0x86affbb5, 0x093f5523, 0x1fd8da38, 0x2e287700, +- 0xb93f8a17, 0x0f94ce5f, 0xb1bb8c54, 0x708ff63d, 0x7fc0773d, 0x6591d017, +- 0x7ef5d50a, 0xc472636b, 0xef9f1631, 0xdf078d30, 0xfb9f75f9, 0xf8c5d142, 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0x0a4501e1, 0x8e284b7a, 0x48a4efab, 0x20f70c53, 0x5fb8ff84, +- 0x437189ae, 0x64c39cd2, 0x15ce15cf, 0x3690de6c, 0x9e78d0b7, 0x5f13cb5f, +- 0x87b833b6, 0x657f957c, 0xe675e836, 0x7e9e1180, 0x10921db4, 0x39a8e3af, +- 0x00a16e6e, 0xc13625d5, 0xd5ca5df8, 0x4c0262ec, 0x861bcc30, 0x961ceee5, +- 0x0945d92b, 0xf720c8fc, 0x1ea1b978, 0x3434dd58, 0x422a29c1, 0x7d630f54, +- 0xd467f946, 0x259fe518, 0x7e3de51b, 0xd9de5185, 0x5f79464d, 0xab9462dd, +- 0xcdca315b, 0xe1a671b3, 0x4af6c4fc, 0xf3793c03, 0xd7f3860d, 0xe01817f8, +- 0x376fdba9, 0x71d69f9c, 0xa0bf61af, 0x5f61956b, 0xd9cbb3b7, 0xd581b5c1, +- 0x0266f671, 0xa0ec15d3, 0x0643f0e8, 0xff7af17c, 0x12aaf831, 0x47a5ce51, +- 0x48c2de51, 0x1484703b, 0x6f1878a0, 0x57faf107, 0xaadff4e2, 0x93f793e5, +- 0xee4e3ece, 0x8f412f3a, 0xa0bcda7f, 0xb1fac2dc, 0x55690a7f, 0xcb567489, +- 0xaf2d3e6b, 0x644df6c1, 0xa973e024, 0x0f1418b0, 0x3c2b1c52, 0xbb22abe9, +- 0x1d350e2c, 0xe4a0f644, 0x32557b6c, 0x7040979d, 0x4b47538d, 0x5296fe74, +- 0x72b1cc0e, 0x8f366742, 0xa171ca8b, 0xe327cad2, 0xfd6fb2e1, 0x54ecc96d, +- 0xcfa7c33a, 0x3552b87d, 0x1c97cc6f, 0x47918e60, 0x4f9ea945, 0x5d5e8cbc, +- 0x089cfaee, 0x52b07deb, 0xfbb26fbd, 0xd5a3dcdb, 0x9e66e237, 0xab325fd5, +- 0x32710ec7, 0x6add1f9b, 0x7d90e60f, 0x5f90c99f, 0x317cc5c9, 0x56051268, +- 0x36a171bf, 0x8c4c2a62, 0x6e52f251, 0x9f512f9b, 0xcd2aed86, 0x8bf21727, +- 0x465e2be7, 0xa2542bbe, 0xb7f4c5b6, 0x99de5727, 0x739e794b, 0xbbc22fad, +- 0x973ccfef, 0x9fcc7943, 0xf7a2ed2c, 0x1921e787, 0xd9c617c8, 0x48504990, +- 0x1c43ca04, 0xd1ce2feb, 0xfc623323, 0xe585a376, 0xadfad02b, 0xe939353b, +- 0x0d12d6fd, 0xb13e2f6f, 0x9df8e302, 0x3c98875d, 0xb407336a, 0x7449ad3e, +- 0x4df7fbe1, 0xbf521670, 0xa8915209, 0xff7ae9f6, 0x3eff9e35, 0x57ef5579, +- 0x36be772f, 0x07d0dfb3, 0x51b48ec3, 0xf3f18de7, 0xeadf28ac, 0x258fbdfb, +- 0xfbd3fcb0, 0x1f9b3658, 0x641fdf46, 0x9b3b8173, 0xc7d8303e, 0x1b1f2ddd, +- 0xe51eeeec, 0x287ec313, 0x8f19623d, 0x64f687fc, 0xe503b9cd, 0xadb77e77, +- 0xd450fa84, 0x4c6e7f57, 0x627a1c9f, 0xf7c26cf2, 0xc73cf9bf, 0x1759e8e8, +- 0x9d34f364, 0x4eebd3cf, 0x2eb43832, 0x3e78d6c4, 0x5f55bef5, 0x3c837fad, +- 0xc227ea33, 0x9b47118d, 0xd479d4c3, 0xd667beba, 0xc3ca4ab8, 0xb356d93d, +- 0xe1524eba, 0x0abb52ac, 0x6b4b99cf, 0x48dce2d8, 0x070f6b7d, 0xd0f68712, +- 0x9785d57b, 0x7744f8ac, 0x50f56c86, 0xb9195a5d, 0x482b7340, 0xe379b10f, +- 0x41d954d2, 0x062c39df, 0x9d1952b3, 0x383fa893, 0x035e526b, 0x2f25018c, +- 0xf53e71fe, 0xaa498301, 0xf8be27dd, 0xe9057cdc, 0x97c5257e, 0x0a40f74c, +- 0x94e76359, 0xfa859cfa, 0xc253ea62, 0xf0cd750e, 0xcc8f8c70, 0x478a75b8, +- 0xd3d7578d, 0x9af5ef8a, 0xe47126da, 0x80dacf0f, 0x07e8a7e6, 0x4317d512, +- 0x1faa6cfb, 0x70920198, 0xdb6eccff, 0xe3cf640b, 0x5faa6690, 0x7d635ab0, +- 0xb65be141, 0x7d09c500, 0x11ee933e, 0xfbc5e57e, 0x6c2d7be9, 0x2898300e, +- 0xd77f9094, 0xf5601d27, 0x595c89d7, 0x15f9b0f2, 0x7a3f1448, 0x6eb6d8f7, +- 0x3991e752, 0xafff120b, 0x0f12b873, 0x6a4233eb, 0xe1cda95d, 0xf9abbe74, +- 0x43df19c7, 0x7c406d9b, 0x7c1a5f9e, 0x4ee6cbca, 0xd9d10e62, 0xd6e9526b, +- 0xd3f9d5e9, 0x73be88f9, 0xe7d5bb65, 0xd779d149, 0x07e44986, 0xce754728, +- 0x2f7773c7, 0x7dfee518, 0x7cb2beba, 0x558f88f3, 0x2dbcea4d, 0x07f6f7aa, +- 0x8ede914f, 0xbb1c5938, 0x3e78fddc, 0x611ff7eb, 0xef3e40f2, 0xf862fe22, +- 0x9989e25c, 0x3eef9e0b, 0xf85794f1, 0xb385fce1, 0xf878f9d5, 0x02398b85, +- 0x77dfafde, 0xc9d924e8, 0x6e3c1cf0, 0x831b6d8e, 0x68ea657d, 0x0acc6bf3, +- 0x4d92f531, 0x6cc13fbf, 0x9f218fbc, 0xfc8bacfc, 0x5d89eb11, 0xf9421f5a, +- 0x9eb6e292, 0xb1d9772f, 0xe2df454f, 0xb8b36f42, 0x8ec9784d, 0xcb0a73d7, +- 0xa15cfa5b, 0x44bcc38d, 0x599b963a, 0x76afe73c, 0xbba7648a, 0xd482f6d0, +- 0x04a59ad7, 0xeb8e3f36, 0xe4dbd76f, 0xd65ec947, 0x4199507c, 0x3be76ffd, +- 0x957d6837, 0x6ba64f9a, 0xf09d39f6, 0x64de1f13, 0x358a5796, 0x4dec4afa, +- 0x3321d53c, 0xf9d5e140, 0x788f3681, 0x8fd66dec, 0x775717fd, 0x1c70ea99, +- 0x00001c70 ++ 0x00088b1f, 0x00000000, 0x7dedff00, 0xd554780b, 0x733ef0b5, 0x7993331e, ++ 0x31e424e4, 0x09261081, 0x83086820, 0x3ac54440, 0xbde311e1, 0x1a5e1db4, ++ 0x15e18fad, 0xa0484842, 0xdeb787e8, 0x2409033f, 0x88b06220, 0xf0ed6bd8, ++ 0xed160b48, 0x16850348, 0xd22d00e9, 0xb15ab077, 0x5ac17eda, 0xa4490850, ++ 0xcb6ad457, 0xfbdad6bf, 0x13267324, 0x5fafdb40, 0x4fc5ef7b, 0xfd9f6b36, ++ 0xd6bdaf5c, 0xb4518fda, 0x84319674, 0xe7f84bb1, 0x5ac6c656, 0xbde96319, ++ 0x65166ce9, 0xc6d4864c, 0x8cd18e42, 0x7e9acca5, 0xc634a2f7, 0xdf35139c, ++ 0x7324506d, 0x6bb9f4d6, 0xd13d9e01, 0x8f2ac3e6, 0x6fb3fe6d, 0x0db19791, ++ 0xeef1df1b, 0x0bbd7802, 0xebef82fe, 0x578593ff, 0x1e1d8c49, 0xba7871a3, ++ 0x42e6b614, 0xe1cadb3a, 0xe0cc2cc1, 0xe59eabfb, 0xcea0598c, 0x229e3027, ++ 0x27f874c6, 0x061847cb, 0x10d8c199, 0x57f8bd84, 0x7df06325, 0xb3dd8096, ++ 0x2b3d5297, 0xde38480b, 0x63aa34de, 0x337426ca, 0x0bda8d25, 0x2d7ea8b9, ++ 0xa6fab80b, 0xef1f3f0e, 0xe3466cec, 0x38f08d9b, 0x3f082b0e, 0x601d61cc, ++ 0xb6778c0b, 0x77ea41ef, 0x94677436, 0xcc3079c3, 0x6def198d, 0xad8fc0fe, ++ 0x59aceed0, 0xc2e9e112, 0x1e6f182c, 0x95a9e3d6, 0x734707f9, 0x71a6ed31, ++ 0x85075e3f, 0xa571deb4, 0x5c6892ce, 0x37bed0a9, 0x877df317, 0x34eb3db1, ++ 0x68c6bec6, 0xbc03eabe, 0xc24561fe, 0xbc4767d4, 0x87dda6f5, 0xf9df52ad, ++ 0x97d678fe, 0x844eed6d, 0x973e1297, 0x5378f8d9, 0x906a034b, 0x2ccefdf2, ++ 0x989cffc8, 0x47c180c7, 0xe98ba726, 0x16ff2059, 0x5f39ff91, 0x085634f9, ++ 0xe83087f0, 0x5d805411, 0x44fdbfa2, 0x1b945d37, 0x6ddf0dd2, 0x40f5dfbd, ++ 0xd4327be3, 0x5ccb301b, 0x9c95f74f, 0x92a0f6c1, 0x70051814, 0xcd1eb9a9, ++ 0xeec646e5, 0xd3b4ae66, 0x07bfc1d7, 0x9097c1b3, 0x3e3f80ce, 0x4bd7f63f, ++ 0xac2cefd0, 0xb7f2f723, 0x787e1e91, 0x80bdab86, 0x3359c6b1, 0xf9e60c5d, ++ 0x0ba6606a, 0xaceafbe7, 0xf8ef3499, 0xe567b3f2, 0xfa0b0726, 0xe3e91be6, ++ 0x70d1d075, 0x16e82fa8, 0xcc807dff, 0x2805236a, 0x8e1fcc27, 0x4e196769, ++ 0x30fa100a, 0xc078cd32, 0xe92dd28f, 0x2f10ffd0, 0x8c1247f3, 0x6cc84be3, ++ 0x03658e50, 0x1ffab3f1, 0xb539b00f, 0x96099bfb, 0x718270d2, 0xe076c32f, ++ 0x1a34bbbb, 0xc69dfe20, 0x1a7b3be5, 0x8cdc3a8b, 0x6cd771dd, 0x3486c3c2, ++ 0x0dfd6125, 0x84625e38, 0xbef84ea8, 0xb3b8f1ca, 0x4f6c012c, 0xc2072d9b, ++ 0x126bf331, 0x165231e3, 0xdb3ff2e5, 0x7b97e9c3, 0x7f414bc7, 0x15ac7c02, ++ 0x1c8b5b78, 0x3c77be36, 0xf80d77c6, 0xd21ff91c, 0xd3097ee3, 0xa7b63b6e, ++ 0x155db6b1, 0x86414724, 0x27f905fc, 0xfe17a924, 0x1c554d67, 0x7e4c5663, ++ 0x41c91a5a, 0xa3c2f5bf, 0x81eb9415, 0x4320fe42, 0x6c0589e0, 0xf0831f20, ++ 0xf5b1b95f, 0xd3abff7c, 0x77e0667a, 0xf41a7e8a, 0xb2ffe491, 0xcbbae974, ++ 0x4ec2b5f1, 0xf50b7a1b, 0xe895338f, 0x48392571, 0xe89e9fc0, 0xfdff00bf, ++ 0x3140d2dd, 0x471a37ad, 0x43b2d31d, 0xfbe8126d, 0x3ee5c1c6, 0x403ceebe, ++ 0x1eb186eb, 0xa04f9fe1, 0xd87183bc, 0x94f5cb51, 0x56f416b5, 0x302fd432, ++ 0x298d0faf, 0xb4249bfb, 0xd30ad823, 0x472f16ba, 0xf4449f8d, 0xd2bd0240, ++ 0x76b89f43, 0xdeb04847, 0x166ea838, 0xd87e5bd1, 0xd7cbc7c6, 0x02cb0d1b, ++ 0xaca71b3d, 0x6f1ea1b0, 0xe1b32cf4, 0xbd98d1ba, 0xc86a618c, 0x35bed1ab, ++ 0x75d97bdb, 0x1d8f4d65, 0xedb92610, 0x363acfc9, 0x630deb06, 0xe8651bed, ++ 0xc4bd25af, 0xf81fedc2, 0xdd1eec9b, 0x4968e382, 0xd5f63d61, 0x52f39436, ++ 0xf60ce70e, 0xdc01d786, 0xcf7f3762, 0xb25be511, 0xd910e1bd, 0xb08b5e11, ++ 0x3ebb4423, 0x6d864fb2, 0x86476dea, 0xb1c6c372, 0xc7eb0690, 0x85cb15d0, ++ 0x7895e33d, 0xb0ec263d, 0x4b4bc26e, 0x91a4a4f3, 0x1b852760, 0x87a221a0, ++ 0x63b61d7f, 0xebe8b26d, 0x75b10f48, 0x0137840e, 0x33b7fd4c, 0xde31c761, ++ 0x46ddbb5e, 0xdbb76df9, 0xfd8a1d21, 0x7d356326, 0xc7af0a5d, 0xe41d91d6, ++ 0xb18b68db, 0x3e407677, 0xb02167da, 0xb025869f, 0xa78c4083, 0xf6b14548, ++ 0x4e10c4a5, 0x6952f017, 0x36f90128, 0x988d6fce, 0xd1dc740f, 0x0bc92934, ++ 0xf5e1de74, 0x1e80f927, 0x419c6c0f, 0x20764b70, 0xf3805029, 0x2ec4919d, ++ 0x3627df43, 0x0923a605, 0xfcf74876, 0x6bf53274, 0x6d8ec3b6, 0xc3f36a2c, ++ 0x989a5bb8, 0xca700acf, 0xda1240fa, 0x9f30f9b1, 0x76dea4db, 0xdb361fd2, ++ 0xf29adb4f, 0x61cbe424, 0xc5bf7c9b, 0xaa3f2779, 0xa94e9179, 0xbcfcccd3, ++ 0xd2f1c435, 0xaddb8d32, 0xbaef5e2d, 0x32970811, 0x9ef84adf, 0x779737ec, ++ 0x8bbff7ae, 0xeafcea72, 0x80f3a245, 0x1e56a027, 0x453fcfe2, 0xbdcfb58a, ++ 0xfe0c5ff0, 0xedcc139c, 0x9b7c4cb4, 0x78db1fea, 0x9fda1247, 0x9240c12d, ++ 0xfe77d05e, 0x14e8fd86, 0x3fe8c27a, 0x6fa889f9, 0xef3beb11, 0xf819f9f8, ++ 0xb88f33e9, 0xe4376cf1, 0x1ae4193a, 0x54ec8dfd, 0xa3be0fd2, 0x64498e6f, ++ 0x1c7a1a0f, 0x89d990f8, 0x7b7e22df, 0x5ffabe22, 0xe6eb1a92, 0x73f02904, ++ 0x5d92f109, 0x614efa4b, 0xe3495fc1, 0xf919cb7b, 0x1205894e, 0x97bfb7d9, ++ 0x34f73db8, 0x5cc6fe0b, 0x0e90c82f, 0x7af82cdd, 0xdd637ca2, 0x7fd80a65, ++ 0x97a7faa3, 0x0b286e51, 0x66cb5e90, 0x72a7a46d, 0x47caefd0, 0x337ae396, ++ 0x3e5df50f, 0x94b5f49a, 0x94cd608e, 0x9422cb5e, 0x4a36b016, 0xc85cbd0d, ++ 0x3a1e09ba, 0x02c4702e, 0x774b7b7c, 0x9e61f984, 0x0b08828e, 0x0bd338c2, ++ 0xafda1202, 0x3976a5e3, 0x8d97e419, 0x2816de62, 0xa5edceb7, 0x9b96c571, ++ 0xbdeaf504, 0x7a0a9096, 0x9b6b2f66, 0xab7a8c9c, 0xfcb04580, 0x74a5a75e, ++ 0xb96f415b, 0xe38f02f1, 0xe600965d, 0xee7ded1b, 0xe07b7343, 0x5728cb4f, ++ 0xc25721b2, 0x14f5a6bf, 0x7d42adc6, 0x02b5c7b4, 0x409adfe6, 0xdc2db95f, ++ 0xd4771f2e, 0xed7d47ee, 0xc8c2d328, 0xcd05e9f7, 0xcfa708c5, 0xe0193e67, ++ 0xfde1de9b, 0xc638e036, 0xbd3bcef7, 0xdd212023, 0x5a163cdb, 0xc0e31c37, ++ 0x3c7b46bf, 0x8c5fd5ab, 0x26f804f1, 0xa20ab8e3, 0x9760197e, 0xd3fbd3f0, ++ 0xc64fae9b, 0xf6dd717a, 0x9136800c, 0x132f8afe, 0xb6eaacf5, 0xaf8081b1, ++ 0xe4add7fa, 0x95745fbf, 0x7c31610f, 0x745d4ef6, 0x8c61fccc, 0x4e3bad9d, ++ 0x1b5d4769, 0x27759da5, 0x6edfed29, 0x7c085583, 0xf9fff911, 0xfd6fd83c, ++ 0x3bcc03e1, 0xc21dc68a, 0x969d38f9, 0xbfc91e70, 0x7a32d64d, 0x001014ed, ++ 0xb3c60dbf, 0xad1e4c79, 0xc45f88b7, 0x12c63ab3, 0xd9673c40, 0x05a5a59a, ++ 0x9e2ef931, 0x53e8ee3f, 0x3b2f512b, 0xa831b3e6, 0xacab3657, 0xf88ce90c, ++ 0xab69039c, 0x203fb964, 0x4e90b9e0, 0xef07ef68, 0x1d68076f, 0xf0097ac8, ++ 0x78a07c84, 0xf532b993, 0x9fcd5e93, 0x209fc4c0, 0x00d95de9, 0x6d9fdf85, ++ 0x7f7983cc, 0xdad9e385, 0x0875b0a0, 0x56af357b, 0xff376e84, 0x98ac1d93, ++ 0xdb1ec0c6, 0x18ed3e5e, 0xf97ce7ea, 0xe42ac393, 0xde55ae0f, 0xb3d18f6a, ++ 0x9f606539, 0xb21fde80, 0x1b9f9cc2, 0x81d0c332, 0xbf38e505, 0x665f9cc9, ++ 0x8bbefe11, 0x8afed0b9, 0x05b2d79f, 0xefe8483f, 0x5163aeaf, 0x4b031aa7, ++ 0x2c069f1c, 0x57059465, 0x8d96fcc2, 0x599f1464, 0x6dfee16b, 0xbe03d633, ++ 0xf5d220d8, 0xa918ed71, 0x8169c13c, 0x4ebb03b5, 0x653fb7e8, 0x00b1ae29, ++ 0x265a0e5d, 0xde5058d5, 0xfb430895, 0xf9a691d0, 0xafca09c3, 0x7fd428b5, ++ 0x97e6d292, 0x37dd5c61, 0xc036df32, 0x3bb532fb, 0xacb1f28a, 0xa10bebd8, ++ 0xfd85f33a, 0x58149748, 0x3efe5103, 0x8a5678c5, 0x50b4acf1, 0xa76a113f, ++ 0x4dbe701b, 0xbb787ec2, 0x197a46cb, 0x8dfd81da, 0x2545be73, 0x22d47b7e, ++ 0x0907e429, 0xc8a9acba, 0xc004ac7b, 0x8cdfdd76, 0x8253b8fd, 0x9ef91a94, ++ 0xd45e65b9, 0xcc435907, 0xd5b72bf4, 0x547f20e6, 0xc8252206, 0x7e32673f, ++ 0x798546b4, 0x3e63ab6f, 0x72eff005, 0x78e0b606, 0x1da9efab, 0x0daef68e, ++ 0x971d3979, 0xb64d3f72, 0x9f2aca69, 0x14caf902, 0x1f02aa25, 0x9c8e132a, ++ 0x8698dd54, 0xed3f918a, 0xec02dfc2, 0x29619286, 0xbff08db0, 0xc4d1bb2b, ++ 0x187d51f6, 0x3627ad2e, 0x8adef730, 0xdb2d3be1, 0x19bacb0c, 0x5c6f4fee, ++ 0x750f9d29, 0xf8861adf, 0x75876467, 0x2e1db8bb, 0xe215f04f, 0x74dc3778, ++ 0xfbe9e113, 0xeaf6ff42, 0x1fc9b0a3, 0x32fc5790, 0xcc58e863, 0x797ca66f, ++ 0x8633cfc5, 0x34bc400e, 0x936d7cd3, 0xf71e3197, 0xaa78f3f0, 0xfa8d77f0, ++ 0xd1fe1e06, 0x87f78ef3, 0x181f486d, 0xd9d84da7, 0x178e5e29, 0xb7c2ceab, ++ 0x05325e01, 0xfaf9d36c, 0x6968b0a1, 0x5c034f1e, 0xc49ed6ff, 0xe6b64aef, ++ 0x787b7d45, 0x1be546b0, 0xf8797853, 0x469b99ee, 0x298f49df, 0xfec36c2c, ++ 0xc47fd414, 0xf6910117, 0x5cb487e4, 0xd46a8fca, 0xf919844f, 0xbf01c112, ++ 0x166fca64, 0xfb0bf5f8, 0xca94efe8, 0xc4c13cd3, 0x69e931f6, 0x43700a2a, ++ 0xafb21aca, 0x0c437aa6, 0x76576aed, 0xe765e939, 0xabbdb338, 0x7376cc7a, ++ 0xce9b7793, 0xbad3f7db, 0xd9ed1360, 0x9f1435f4, 0x9c9765b5, 0xe29276c1, ++ 0x50db61fc, 0xb888ac33, 0xf6164bac, 0x06ec0df4, 0xabf593f2, 0x3f0a0f8c, ++ 0x7fd06dcf, 0x13b7a702, 0x77f405ec, 0x2eec0532, 0xf7c9e830, 0xdff98c01, ++ 0xfb718536, 0xcf47f042, 0xdc4a43fe, 0x8f0a43fe, 0x91bfafef, 0xe8c207f3, ++ 0x257db8ff, 0xc7b897e4, 0x686e7af1, 0x78c7c787, 0x27e8df3c, 0xddea3bf6, ++ 0x68da130b, 0xe05dc01f, 0x6911f4a7, 0xa0a3b51a, 0x1e7cc29c, 0xc2bc7e13, ++ 0x263f8a74, 0xeb24798b, 0x8baf9e3c, 0x318074f6, 0xe89ae94e, 0x28d1fee7, ++ 0x3a0dde3e, 0xa7b62f1f, 0x9bda78d0, 0x09f3e454, 0x7685dfdc, 0xf6e7e637, ++ 0x93992fd2, 0xfd61f204, 0x0b92f680, 0xaa6e8e80, 0x7d48b21f, 0xfe1148f9, ++ 0x75fc22ba, 0x165a6768, 0xf58033b4, 0x47e099f0, 0xec37f71e, 0xee22019b, ++ 0x4c777c6f, 0xc7ff1beb, 0xfe38a4fc, 0x4a53f233, 0x7d93e5cd, 0xef8ccf9c, ++ 0x035b7ef1, 0x9775fce3, 0x7480ec2c, 0x57f38c36, 0x57f155ea, 0xca13ce0a, ++ 0x59fb18a7, 0x27525f82, 0xe022fd0a, 0x7f06a194, 0x7bdbba71, 0xf3f9c9f0, ++ 0x8f57c171, 0xbb757c1b, 0x9d2303d6, 0xe1ca9f1e, 0xfd8c52c7, 0x29a7ce20, ++ 0x89d49da2, 0xa927c425, 0x2f3aff46, 0x17b43a97, 0x285dba46, 0x5b707ce5, ++ 0xf677cf1a, 0x925781f0, 0x417a5ea5, 0xedcd159a, 0x228f43d5, 0xbe270dbf, ++ 0x4ababa20, 0x90b9bf39, 0x7f5e24df, 0x2a9f943e, 0xfa3d1df2, 0x5ff42c34, ++ 0xccb24fd4, 0xf10afdda, 0xc267df19, 0x5fd41cf6, 0x6e5e78f8, 0x049a9d2f, ++ 0x3ae87a5d, 0x72e43825, 0xa2c62d71, 0x7443c592, 0x83642c91, 0x28ca45fa, ++ 0x552fb0ff, 0xc7dfa092, 0x2e563f01, 0xb35f147f, 0xe3daf88b, 0x0fc84705, ++ 0x3587dc79, 0xef5e2f00, 0x432879ed, 0xfa1f16a5, 0xf2978f49, 0xbf7c47f8, ++ 0x8f97a5a9, 0x71d969b7, 0x6dcd2cfa, 0x6447cfe2, 0x27113fb1, 0x73596b3f, ++ 0x213fad33, 0x26279b7f, 0x2f2f115e, 0x1f5c89ce, 0xe57d7c3b, 0x114cf901, ++ 0x7d6092e5, 0x47dafa41, 0xf143e598, 0x1d6c7d73, 0xe8be2017, 0x7c89de33, ++ 0x33494cdf, 0x5e30ffe7, 0x4eaf7b1f, 0x21f97a5e, 0x80b7d622, 0xe77f1fd0, ++ 0x2d9fedf5, 0x3ec9f90d, 0x9e201a42, 0xce04b65e, 0x9d0f88c8, 0xb60e87db, ++ 0x84cff09e, 0x36e8307e, 0xf0bc6295, 0x93cb9b3d, 0x7ad08f43, 0x3cb828ec, ++ 0xfb17addf, 0x74eb6b87, 0xadf11f4a, 0x25e79b2a, 0x0dd685bf, 0xc553515b, ++ 0x4367f876, 0x5bbe879d, 0xe76a8547, 0x6c38dc02, 0xf61b7045, 0xd279fc2d, ++ 0xb15f4853, 0x4b8c6e5f, 0xe5057b45, 0xb7e43b28, 0x10b951a4, 0xc11d534e, ++ 0x4f68e8e3, 0x041c5c52, 0xe1ac0adf, 0x04eb0a18, 0xdc1185ea, 0x8d0c721f, ++ 0xe6820c60, 0xaa657e83, 0x10524c1c, 0x51cd051f, 0xba28778c, 0x20d6f24e, ++ 0x1f239845, 0xf9257be7, 0xbcb8590f, 0xabfb4e27, 0xa8fb8497, 0x48bae409, ++ 0xdbdd91b1, 0x049846a0, 0xc5186bf3, 0xc8696fc8, 0x4679fb35, 0x1cb850ea, ++ 0x0f69de2f, 0x5f231dbf, 0x131491d5, 0x2b3fb35c, 0x1c8c76fc, 0x1f9c662d, ++ 0xf68972d8, 0x27f8aad5, 0x73dacd56, 0x0c2eef10, 0x4bbb42d2, 0x0819ed2c, ++ 0x3beeb177, 0x6794644a, 0xe6e51fbf, 0x0638393e, 0x223496f1, 0xe8a47c40, ++ 0x4abf1101, 0xa37daabb, 0x0bd5e12b, 0x484cb3dd, 0x3a8a45b3, 0xd34806f6, ++ 0x8e331a78, 0xcff8ca49, 0xee030e3e, 0x228397b5, 0x84f435ad, 0xa91ffa5f, ++ 0xf5e38a27, 0xd1e22542, 0xae4c0bd0, 0x883f6262, 0xc85582f4, 0x904f54df, ++ 0xe30d71ec, 0xf1ef1895, 0x1fd07d70, 0xfac51bbe, 0x85e846bd, 0x5a0bd406, ++ 0xd437fcaf, 0x0ab60979, 0xd0f1593b, 0xc94b3e36, 0x5cf0860e, 0x2d766643, ++ 0x27c04f6b, 0x8a415c6b, 0x2ace1d5f, 0x35f7e0f7, 0x8c3dcb83, 0x9f6e7eec, ++ 0x935de318, 0xd762ce55, 0x2f371c4f, 0xfc579e67, 0x9be3fa7c, 0xe0c8f5f8, ++ 0x46f91523, 0x5873d4a6, 0x52afd4c2, 0xc3cf123c, 0x046bfb70, 0x4b2a1fda, ++ 0xefa3adf2, 0x3e5e72d1, 0x9cd2285a, 0x405ca807, 0x6bfe2fec, 0x093e6ba4, ++ 0x860e90d8, 0x06b7eb3d, 0xd85ea3f7, 0x69ca48ab, 0xa75893c4, 0xecbda757, ++ 0xdf183a46, 0xf6bfa63b, 0x55e35405, 0xe209745a, 0x07739669, 0x8c6c875f, ++ 0x676191f4, 0xe3981524, 0x67817666, 0x54cbe05b, 0x1be0967e, 0x397350db, ++ 0x7dc54f3a, 0x2e4b7091, 0x2e3e37d2, 0x4940e5c7, 0xb8abe733, 0xf3e30aa1, ++ 0x83c7bbcc, 0x1b3d5de3, 0xc3f02ef4, 0xfd66e9ea, 0x40e58d9b, 0xf0af7e5e, ++ 0x7fa11ff4, 0xbe77b975, 0xea290139, 0x33c8fb00, 0xc21ed7d9, 0x92b4ce79, ++ 0xc18488bd, 0x3c4610f3, 0x2b273593, 0xfc46e7c8, 0xa5e07073, 0x39ae308f, ++ 0xb927de64, 0x0ade6828, 0xcb6e08fd, 0x319d15fe, 0xa437c798, 0x5fd891ee, ++ 0xe7a2638e, 0x06e78601, 0xeb015b18, 0xde71ee28, 0x77d62983, 0x3cfc0923, ++ 0x61e82ede, 0x91903945, 0x1d4a613e, 0x8970bfc2, 0xb464cf7d, 0xfd7bf36e, ++ 0xc2c7f016, 0x1ecff216, 0x5b9ec9d6, 0x84f9d32b, 0x607ff5ab, 0x4dfa3a34, ++ 0x97975812, 0xcf5f571c, 0xc62e6813, 0xb2c0dc78, 0xe375c508, 0xf32679cb, ++ 0xf9f14df3, 0xfe2f82b9, 0x9cde7401, 0xa57c8f96, 0x7a0c3d13, 0x0e0e48ff, ++ 0xf0c7c751, 0x7d27eead, 0x54ae5f15, 0xa1550e09, 0x628159bd, 0x4fd56fbe, ++ 0x7f87e939, 0x5df68d39, 0x8bd55efd, 0xbde4c97e, 0x8056f46a, 0xf3f2b7ab, ++ 0x7643968c, 0xa7ce9f92, 0x69751c39, 0xdf9ca7e4, 0x583d9121, 0x70db6d63, ++ 0xf6f9c633, 0xb6ec8cca, 0xe7059970, 0x9dcc5a77, 0xb970e7ed, 0xb7ab3870, ++ 0xeb0fbe1e, 0xd2b7ec57, 0x81f5633e, 0x19b85f85, 0x55c785e0, 0x5baaf5b2, ++ 0x01036a56, 0x2296145e, 0xe24d7708, 0x27da1bf2, 0xb976fc93, 0x3b6632db, ++ 0xc6c3bf71, 0xb8c0d7bc, 0xb3196d5d, 0xe1955e60, 0x5eb04a17, 0x87c96ee5, ++ 0xbde4c6eb, 0xa0b2c72d, 0x892ef55e, 0xef1799f6, 0x0c6f3074, 0xcab74e7d, ++ 0x1e315bd1, 0x78c4f30c, 0x5cd642c8, 0x6eaf7882, 0x5d79a8d9, 0x5b3ef4bd, ++ 0xad798237, 0x2ef570bd, 0x2dea07e8, 0xe1f25e79, 0x58589714, 0xf3a4f910, ++ 0xbb6cbd80, 0x52b7e713, 0x79c2ee1b, 0x6e586a35, 0x3ece7861, 0xb7c717bb, ++ 0xef812b55, 0xd56f4f95, 0x6af863ca, 0x98ebcef1, 0x4e4f8637, 0xbccfc96f, ++ 0x1673badc, 0xf1d8d1d6, 0x38788a54, 0xf4dac253, 0xb267f898, 0x91f42296, ++ 0xe0df6a6c, 0x8cabd0ff, 0x8bd0faec, 0x41abc22e, 0xd73a65b7, 0x2edd060f, ++ 0x4a8e82e8, 0xfb6c5177, 0xe901ba46, 0x057dc560, 0x61c7d29d, 0x1374c73d, ++ 0x9f48e7ac, 0x6bbf88cd, 0xf2819f68, 0x315913dd, 0xfdbbf7ee, 0xfee3c8e8, ++ 0xc558bfb6, 0xc38040f8, 0x2504f719, 0x6fe665ef, 0xe0d59ba4, 0xb7223c1c, ++ 0x9274756e, 0x59b57202, 0x90c52e0b, 0x3f0de3f7, 0xe0053499, 0x01b06a03, ++ 0x0a41bff9, 0x4ff8f056, 0xb2f283c4, 0x3c93ec46, 0x8c78418c, 0xb46967df, ++ 0xdef9b02f, 0x24b2eda2, 0x70869ae6, 0x0e3137f9, 0x4a3ced05, 0x4ed0a8ed, ++ 0xc9db95fe, 0xa9826fb8, 0x2afb8c9d, 0x5336768c, 0x6babf63b, 0x377df367, ++ 0x5f73c799, 0x37ced1a5, 0xd5d71da8, 0xfee32bcd, 0xdcf1e689, 0x64ed455f, ++ 0x7b23e3de, 0x614fd8c8, 0x78c35718, 0xeb94eecc, 0x3e58b1d7, 0xec6df49a, ++ 0x155205cf, 0x13c947cb, 0x94f24c92, 0xc1354fe2, 0x9a074a03, 0xf207a7ca, ++ 0xcb33df4c, 0x4be38dae, 0x8271e927, 0x14d15061, 0x06d26f1e, 0x8a77a46a, ++ 0x7e08da07, 0xf493a070, 0x053783ce, 0x26fdc1af, 0xd5ea2b1c, 0x68e0b507, ++ 0x30df013d, 0xb8a70fdc, 0x6982d78c, 0xec54bb1f, 0xf41a4e43, 0x5053f0c9, ++ 0x3dd2c6bf, 0xe3e0053c, 0x50cff15a, 0xb9509ecf, 0x69f8655f, 0xfa465649, ++ 0x68b731af, 0xaf06287b, 0x5f81834d, 0x9b76dea4, 0xf907a0d4, 0xdcf555f1, ++ 0xb446e52a, 0xb43a354b, 0x67d59bf8, 0x3a14848f, 0x85764617, 0x11fd0355, ++ 0xfd06bfdb, 0x6fff5017, 0xf54fde20, 0x6f35bfd3, 0x5b7fa982, 0x7fa9854e, ++ 0x83fd069b, 0xfd51fc7c, 0xf01fe893, 0x97e81377, 0x7fa817d5, 0xf5054e6b, ++ 0x0ab1a8df, 0x3d49ff53, 0xfec39ffd, 0xf9f953df, 0xcff33edc, 0xff3cc9bb, ++ 0xfcf34a9c, 0xf7ff3e35, 0xff458fd5, 0x8bff3449, 0xe7ccffab, 0xe7c9539f, ++ 0xf6ede56f, 0xc1eeeff4, 0x7f88c7ff, 0xbfdc4b49, 0x79a27f35, 0xccaa43fe, ++ 0xfef2b7f3, 0xe7ae4d55, 0x7fa93bfd, 0x28e58d6d, 0x15487fcd, 0x8359aff5, ++ 0x6d23e43e, 0x9e2d5250, 0xc90305e3, 0xfc267e8b, 0x0474a7ed, 0x55115f3f, ++ 0x0f1c68f3, 0xbbbe7126, 0xe6fc0498, 0x2ca7d5ec, 0xfa08120c, 0xe9e08972, ++ 0x358bbbc5, 0xa210ffbe, 0x3102c5b8, 0x65fbf9d4, 0xb26e8f6e, 0xceadb9d2, ++ 0xe10872fd, 0xa16e9bf9, 0x958d68f8, 0xfda01fdd, 0x209c3043, 0x8c4f8fff, ++ 0xaf3b16da, 0xb34174f8, 0x14ddba7a, 0x09e3e69f, 0x6a23624d, 0x540b7c61, ++ 0x469f04dd, 0xf0f40bbf, 0x418fe85b, 0xb465467a, 0xfa36feef, 0xcac4d765, ++ 0xae7e4acd, 0x295ec436, 0x21dd7980, 0xe15a7fc6, 0x5cbd3ef8, 0x1774f3a2, ++ 0x50d52e37, 0x76682d9f, 0x1aa1fc98, 0x03eea741, 0xbfee30d6, 0xeea7e71a, ++ 0xec645124, 0x7f3e8777, 0x85c7ed0c, 0xea98065b, 0xabc2c3dd, 0xde7e503d, ++ 0x718339fa, 0x654be10f, 0x3f71ebd6, 0x20d4d402, 0x83655f1e, 0xd6529e30, ++ 0xb3c551ba, 0xa99677be, 0xaefdbb26, 0x52fe19a0, 0x54ee1985, 0x81c62ac3, ++ 0x6c49173a, 0x6f7bb42b, 0x0fef1aad, 0x68b73f50, 0xe4bec2a9, 0x3401ddfd, ++ 0x7bac82cc, 0xb31ebd31, 0x7deba275, 0x8c6baf3a, 0xe02be6a7, 0xdc7ad1c1, ++ 0x65fe4e9e, 0xd0fc9d28, 0x1de7cea0, 0x54fbde3f, 0xe3003f9b, 0x9921efb9, ++ 0xfe3f19f0, 0xbf0e43f6, 0xf6f4ec05, 0xd1527f2d, 0x4f9f89cf, 0x5feff8fc, ++ 0x5d1f3f11, 0x4e61f5c3, 0x643f3e28, 0x69187b8a, 0xede2fecd, 0xf6f6bb66, ++ 0x763b26ed, 0xbc1374e7, 0xa9977c28, 0x732dc2fc, 0x3417df4c, 0x9f7d322f, ++ 0x04d4b4d7, 0x643d09cf, 0x8aff7f2a, 0xf7efa695, 0x7d35aed6, 0x46c552ff, ++ 0xf0577c13, 0x3bf95329, 0xbe9ab6cb, 0xfc8d0e5b, 0xfd51ca22, 0xb1dd32ab, ++ 0x7a79df78, 0xef9bda03, 0xd21f153b, 0x3f8c1de3, 0xf2aed158, 0x7fb9da52, ++ 0x056f9d2c, 0x9b8e583d, 0x94d71b1b, 0x444d37d4, 0x7f48ccbd, 0x5a66b13e, ++ 0xa7e0087d, 0x4fe12f35, 0xe8b1a2de, 0x526a7400, 0x5bb8f87b, 0x7edef98e, ++ 0x405bef85, 0xfdf6c7d0, 0xce27b72e, 0x6736d9af, 0xfe209e88, 0x6cb72bd7, ++ 0x5d73ae10, 0x6138e252, 0x3539dc55, 0x9c9156c6, 0x3af8d50f, 0x7d71a553, ++ 0x6b27b550, 0xc1f5c612, 0x7b5e1f2f, 0x1222feb9, 0x5a18e5c5, 0x0fc8e9ff, ++ 0xfdf14c83, 0x4df33bc5, 0x5871ddf2, 0x412d71a6, 0x757a009d, 0xafd81ab8, ++ 0xa388fdd1, 0xe1473339, 0x3407fc38, 0xd3fb3bd4, 0xa8ef5d69, 0xb6fedd2b, ++ 0x5009f48a, 0x195d4efa, 0x82eba7a5, 0x575dbe94, 0x755be941, 0xd7b694b5, ++ 0xf7f4a0ad, 0xdf4a2175, 0xf4a26bac, 0x94cd75b7, 0x42dbac9e, 0xc2ea6fe9, ++ 0xf9d67694, 0xa1e43529, 0x8406ff47, 0x946c6c3d, 0x8b0f6131, 0xf7a434b9, ++ 0x78a2d39c, 0xc5e705d3, 0x5fef68e1, 0xfba56938, 0x2be1fd07, 0xa7fadf9e, ++ 0x95ec9fa3, 0x7200f0f2, 0xdbbfe392, 0xec9d3893, 0x40ca5616, 0xf61dad1f, ++ 0x02dcdf4d, 0x19641582, 0xd37c9058, 0xc5da095d, 0x2bccb8fd, 0xbbf989d3, ++ 0x3d00670b, 0xe3ed7f4e, 0xa8776c22, 0xa4bfd7c6, 0xc3ad32a3, 0x37ddba2c, ++ 0xc7a7d473, 0xdfc3f49b, 0xee9c60e5, 0xdafe0f7c, 0x8c9ce872, 0x173b53a6, ++ 0xe30cad5a, 0x3a0e1763, 0xc2f0ff68, 0x946eedf1, 0x391e65c7, 0xfed8f6fc, ++ 0xc91d55f1, 0xfe4d3b0d, 0xd0be19b7, 0x6846952c, 0xcf26f63d, 0xa57c851a, ++ 0x73a6df87, 0x8d4a1e72, 0x34799676, 0xceece7ea, 0x34cf1e7c, 0x4eec97ee, ++ 0xbf057e21, 0xbdffca93, 0x3b5fd3c7, 0x6b1878c6, 0xd1b07f65, 0xf3c320d6, ++ 0xef95fdbc, 0xff949f97, 0x775e28d6, 0xf688bd50, 0xbffe1582, 0x1409f744, ++ 0x6b768d82, 0x3ac87222, 0x9b77f31a, 0x5e7a83fa, 0x94bfa7c3, 0x35be3977, ++ 0x1eb91fdf, 0x4b7fab03, 0xa256ac5c, 0x2f1195b8, 0x4d9c52e9, 0x78dee8d2, ++ 0x5b888d49, 0xb5dadb57, 0x6f9d6420, 0xdc6cbfcd, 0x71dd6cf6, 0x555dcf1d, ++ 0x74359ad8, 0x23222a7e, 0x3b9ea0a7, 0x819f5adf, 0xf962e0f6, 0x048183c2, ++ 0x795a67f5, 0x58516f7c, 0xa3af36ed, 0xb4183f82, 0x43f3e46b, 0x31d3ce87, ++ 0xdb858770, 0xceedf1d9, 0x3c5d5eb7, 0x13eec969, 0xfb7b3725, 0xfec969e2, ++ 0xcf8a34f7, 0x5714cc2b, 0xb2e7f032, 0x615be606, 0x4f3b957c, 0x8efa3d91, ++ 0x95fe1a1a, 0xbea7e8cb, 0x287a73f3, 0x2bcc672e, 0x9fb0dac4, 0x474413b9, ++ 0x1be77bcc, 0xfbbe9eb0, 0xa39f9533, 0x8d72e714, 0xc5fb1871, 0xb73404f3, ++ 0x17ed3175, 0xdfefbbbf, 0xcf9bfec9, 0x03a26e02, 0x3b422e6b, 0x94b33cf2, ++ 0xb3ce9e22, 0x6363dd97, 0x8e04d0e8, 0x5e69e212, 0x018ed993, 0x2f04d7fb, ++ 0xcb8662dc, 0xd40c8cd9, 0x549be527, 0x7e689616, 0xac2befa6, 0x216fd13a, ++ 0xeb835dab, 0xe3cabd6a, 0xa67573bc, 0x5abd020c, 0x17afbdfd, 0x31f801cd, ++ 0x8d1f5f2b, 0x54a2cbf8, 0x4656076e, 0x2e786ab6, 0x63ad0ffa, 0x6199b8ef, ++ 0x5c1af0fd, 0x257b4207, 0xe3c6c38a, 0x3f8ed3f7, 0x7ac6bc7e, 0x240e27dd, ++ 0x53bd51c6, 0xf1ae784a, 0x0ccf82eb, 0xcc4e7d7d, 0x3e0bf0db, 0x4fc63840, ++ 0xdc455888, 0xd232665e, 0x0b6ebcfd, 0xbbe99259, 0xdbf38a2f, 0x7bd5f563, ++ 0x681f8e31, 0xc0dd92b5, 0x728c2ff7, 0xf2906b7e, 0x979fa43b, 0xd114fbf3, ++ 0x126fda42, 0x9ee37d71, 0x2ee49c94, 0x62cf2864, 0xeedead9f, 0x1af086de, ++ 0xc39d0557, 0x877941a9, 0x97751ef6, 0xb578c71c, 0xfd47358d, 0x4f56bfc0, ++ 0xd7807edc, 0x3ec43b0c, 0xe0660d7f, 0xc78fa15e, 0xcc231dff, 0x333e5ce5, ++ 0x3c1ecbfc, 0x698f8945, 0xe78bd92b, 0x3c519cb7, 0x2826c0a7, 0x56fe3d1d, ++ 0x7c7bfa1e, 0xd9cf0cfc, 0x3ae5f943, 0xe304bf2f, 0xe58f402a, 0x4cca4faf, ++ 0xaa3e8cbd, 0xe16250f9, 0x46a47598, 0x0f90d6e9, 0x28543e6b, 0x4deb33ff, ++ 0x31aaac2f, 0x5acff37a, 0x01ea34f0, 0x3e3893d4, 0xdd89fa09, 0x57c7030f, ++ 0xd973958f, 0xcf8fe666, 0x66348e3c, 0x6b2edfd2, 0xe34483f0, 0x7bedccf8, ++ 0xdb2fb4fa, 0xed8effd2, 0x7ed3ed0f, 0xabf6a272, 0xbedcf7bf, 0x95afac10, ++ 0x8dc279df, 0x55deea87, 0xfef0339a, 0x6acb5554, 0x3be5ca37, 0x748dc84a, ++ 0x272c377d, 0x625c7fbc, 0xefcef833, 0x4b5a7bc4, 0x7d9ddf04, 0xa02f91f6, ++ 0x45b172ff, 0xb03e29d5, 0x02b51ad3, 0x5d692e53, 0xa763e5c4, 0xf98714f5, ++ 0xfd9af3bd, 0xf9517d66, 0xbc3227ad, 0x121bcfb4, 0xfc9473fe, 0xfe3b2583, ++ 0x57768258, 0xbd26eb0d, 0xfb0f5f17, 0xec9530ff, 0x1f783981, 0x71bbfe2d, ++ 0xe046a7be, 0x11f5a6a5, 0xd3578f3a, 0xef38bb7a, 0x677e4ed6, 0x610abd7c, ++ 0x1360dff7, 0xbec4dde7, 0x161781a0, 0xfd7f76e6, 0x4f0b27ae, 0x763ab8c1, ++ 0x152dccfc, 0xd729f2c4, 0xf322177f, 0x6f7df1be, 0x09d572ff, 0xbed631fa, ++ 0xef69d636, 0x1cafe17e, 0x1a9569e4, 0x583fa375, 0xf3a555b5, 0x6dcf55e7, ++ 0x30d7e6ff, 0xd5baf33e, 0x5fda0c37, 0x7f8fdcfc, 0x8bc01373, 0xa6d3505f, ++ 0xf13869f1, 0x9f41985e, 0xc57ff81a, 0xa8f4bdf5, 0x358feefc, 0xf98147bc, ++ 0xd2f6a70f, 0x870bf165, 0x2faa3635, 0x0e47263e, 0x82bdfc6b, 0x4e44fa38, ++ 0x515fa095, 0x0d03ebbf, 0x87bbd7f5, 0x9b999624, 0x7f5b9f00, 0xe231f64c, ++ 0xe829e889, 0xb8bf43d5, 0x174035f2, 0xf4718bd2, 0x11e72f8a, 0x62ed8ff2, ++ 0xfbf81e3c, 0xbee3eff9, 0x3ead6fcd, 0xf3c543c4, 0x7ce3765f, 0x9cb528ce, ++ 0x3abebfcf, 0x54d1cf03, 0x9d0ca1a8, 0xf15f9e52, 0x7fc403cc, 0x903c4f0b, ++ 0xfddbf7c1, 0x4c5ce259, 0xc173ce16, 0x9e69b3d3, 0x7c482ce5, 0x7e75f158, ++ 0x857dfe8f, 0x4090be95, 0xb8d90e4e, 0x9b66761d, 0xcf133695, 0xfb8242e0, ++ 0xe1cb2f18, 0x2e078a16, 0x03cb78a5, 0x5b13fec6, 0x36fbf046, 0x364daf4e, ++ 0x2c1bbce3, 0xbbfcb125, 0xe90db1a3, 0x3fb07674, 0x35c8e313, 0x7c09094c, ++ 0x5da09748, 0x4cd4c4f9, 0x55e6274e, 0xd03d448a, 0x1f3193ff, 0x7ea9b7cb, ++ 0x1ea9a17b, 0xdbdb94bb, 0x3fd172ff, 0xed093b8c, 0x601933d7, 0xdf98260f, ++ 0xf83f3139, 0xf862c6d3, 0xb9de462c, 0xcb58effc, 0xff90dde5, 0xfc52f4f0, ++ 0x70afdffe, 0x687ac239, 0xa2b8c0bf, 0xf0fdf499, 0x83f4892c, 0xc9134595, ++ 0xc8550ef9, 0x3c7bf9b9, 0x15f8c0bf, 0xf87b8f5c, 0x2549fb06, 0x5b7d903a, ++ 0xc7ea09be, 0xd7ec55ea, 0x435db7dd, 0x7d0a178e, 0x1f4e2070, 0xafd3a7b0, ++ 0x4ab71f6a, 0x6bf37f0d, 0xaf20bf28, 0xafca2f21, 0x9c31ef4a, 0x37f47ddb, ++ 0x9edc8377, 0x6b72188b, 0x72f1abd6, 0x3c67b15b, 0xe7b7244b, 0x50963e9c, ++ 0xa13f216e, 0x89db3adc, 0x7ad1ff9f, 0x5be3c0d5, 0x48b9f336, 0x87f64f43, ++ 0xf93d78cf, 0x426f369f, 0x5e7f093d, 0xf97d4561, 0x8343e0d1, 0x5dbf2aff, ++ 0x7ab9e74d, 0xc3e0d4f8, 0xf8353e1e, 0xd23c4fb0, 0xeff8c784, 0x61bfe2cf, ++ 0x2a03810a, 0x0eabcfc5, 0x733ce24a, 0x71a0d8e8, 0x2d3f2f84, 0xd8f9ac73, ++ 0x3858b4a0, 0xe247071c, 0xe0e3fbca, 0x60f95c40, 0x2a6b5c1c, 0xa8ffb55f, ++ 0x46c70fc6, 0x15e4e54d, 0x90fec5ff, 0xac603e20, 0xefad3543, 0x0fe42169, ++ 0x57d53767, 0x0b90b157, 0xca2fe5e3, 0x02ef2f14, 0x7e81af1c, 0x86e776ba, ++ 0x5647a043, 0xa57c79db, 0x835b5d3b, 0xef4baf7a, 0xd95da376, 0xbe71e76d, ++ 0x3bb740ae, 0x3b9ec625, 0xbd265075, 0xa5661edd, 0xba4efc89, 0x6cf80ae1, ++ 0xe77dfd67, 0xb42efff1, 0xa9bfa1cf, 0x056733b2, 0x659a65c6, 0x7f393f3a, ++ 0x3c6e9de5, 0x3075d237, 0x90658bff, 0x3227e0bf, 0xf90c8edf, 0x7f18ac95, ++ 0xda161def, 0x7dc2513c, 0x27c4f5ea, 0xff720ef3, 0xc4fafe6f, 0xea295f7c, ++ 0x6b973b95, 0x6fc15fa8, 0x7f762b7b, 0xe2a768c3, 0x83fcb8e9, 0xa3e42eff, ++ 0x951ce299, 0x83dfcc3b, 0x62504e22, 0x8631f217, 0xba7e118d, 0x865df625, ++ 0x17c172a9, 0x5d0e80cb, 0x218665c7, 0x65070b86, 0xdd85c3a2, 0xc5009cfc, ++ 0xbe446ff3, 0x68bd26ee, 0xe503abe0, 0xf5fe9ae8, 0xdfdec755, 0xf9057d15, ++ 0x851bdf65, 0xc76905ff, 0xff87d7be, 0xbdefe100, 0xeb06f396, 0x21f27e5b, ++ 0x749fed3b, 0x9f11721d, 0x8bf8bd77, 0x7c20af9c, 0xeb714ac0, 0x141f43ae, ++ 0xad74df22, 0xbea056b2, 0xfdcc1aeb, 0x3f17fad6, 0x75a76c28, 0xb7e881b6, ++ 0x7b71aed4, 0xbfc7e0e9, 0x17a473c7, 0xd0acc20e, 0x20e4388e, 0xbef9aa39, ++ 0x5d6ce29d, 0x14507e2f, 0xadfc0feb, 0xf62259f3, 0xac5cbb35, 0x2f8e0f6c, ++ 0xd507ef85, 0xedc6e0fc, 0x47dcf12b, 0x1e6d61eb, 0xc3fc9f7c, 0x1ea214bf, ++ 0xedc3daed, 0xfdb54ea3, 0x7bb7dc19, 0x1bb7ed78, 0x2757a054, 0xb040d30a, ++ 0x4c75d647, 0x7dbaf3c1, 0x8a17f2f1, 0x3e2d5e1f, 0x832ffabe, 0xf5cfc90f, ++ 0x268c2b9c, 0x1f43e4c1, 0xd40dfefd, 0xc4ac8707, 0xcf7cc697, 0xdd925645, ++ 0xef79a572, 0x6f371ff9, 0xf3357a29, 0x3e4ff13e, 0x70f13bef, 0x72bef8d0, ++ 0x5fcf97d0, 0xe7e0907c, 0xef1a3e5c, 0x7bfbf255, 0xfb371e76, 0xa7ff9d67, ++ 0xa01efba6, 0xf3cafbbb, 0xb9fe93d6, 0xdd3fdde7, 0xa09f727f, 0x5ee78ebb, ++ 0x17f87e6a, 0xd5a7df1a, 0x7fa4be73, 0xec37be4d, 0x5f1675fa, 0x72c7de33, ++ 0xeb00d7a0, 0xa335d3b4, 0xeb88c309, 0x7ba0cc46, 0xef3f729d, 0xe249cc6d, ++ 0xf12c93fe, 0x60d81977, 0xc263f71e, 0x0be3c29f, 0xc9d03f74, 0x4e29f9ef, ++ 0x29908f7e, 0x66977a3e, 0x7d73b5dd, 0x5d88a674, 0x7088327f, 0xc51f44f6, ++ 0xcafce3b5, 0x25f98906, 0x6b956bb0, 0xfa38edff, 0x4b08ea37, 0xe9485ad4, ++ 0x451b4c29, 0x35d552bc, 0x2ce3df93, 0xaf76c330, 0xf68ab619, 0xdf8f8c6c, ++ 0x8c6161e6, 0x8f23cb5b, 0x4e6e78e8, 0xbc30a31e, 0xcd676087, 0xac2ff421, ++ 0x5bfd731e, 0xce299892, 0xd3f4ed9b, 0xd85579b9, 0x6fd053a3, 0xc03b3841, ++ 0xd84ebf68, 0x9f9a4aa3, 0xbac8c3ee, 0xa289ce8f, 0x4305105f, 0xdbdda5ef, ++ 0xfe713e29, 0xc05f53d9, 0x81fe2cf1, 0xcf806ccc, 0x162eddce, 0x584afac5, ++ 0xb2a77f43, 0x0077a655, 0x9a2d1299, 0x68efb319, 0xbf8b99d8, 0x54f9a2e3, ++ 0xa786b1ee, 0x7dcafd41, 0xf5a4287f, 0xd937557e, 0x2567a1cd, 0xbb0d0b5f, ++ 0x15f710bd, 0xef6e152b, 0x5577d3c6, 0x3bdff712, 0x30ca380e, 0xe4ed204e, ++ 0x232b49e7, 0x98d6aa77, 0x250f3273, 0xe23946a9, 0x892ed0bf, 0xe30493bf, ++ 0x68c73d8b, 0xbb1db9d8, 0xfdbe3e24, 0x5203bd2a, 0x4e85f3b9, 0x9e54778c, ++ 0x5cd0fab4, 0x1ef9d9ac, 0x7f27d7c5, 0x3b7739e7, 0xc9b275f9, 0x5fe3edcf, ++ 0x1f8994ee, 0x9356b496, 0xf1300bbd, 0xf08892c5, 0xffa53ee7, 0x2f3bf8b3, ++ 0x4e0bc3ee, 0x2dfbbf8b, 0xce53c637, 0xc9b8b5b6, 0xf979dccf, 0x7f1f4f78, ++ 0xf856b232, 0xef179f93, 0x27f62651, 0xc03fe2cf, 0x149ddafe, 0x1cef97e7, ++ 0x4645ee20, 0x2ef72e8b, 0xdee7e2cd, 0xa1e3067f, 0x3dce7b1d, 0xfaaee383, ++ 0x419e9feb, 0xb21d95fb, 0x522fb8eb, 0x14abecf3, 0x1dea323f, 0xcff1e24b, ++ 0xa2df5dce, 0xf8275bf8, 0xe75ad8f3, 0xd072678b, 0xe17ce98f, 0xcff40ca3, ++ 0x9538bf97, 0xbe5945de, 0x4b267277, 0x8a46ff20, 0x8abe1bfc, 0xdd3c5ff8, ++ 0x251eb68e, 0xd03cfb3b, 0x9e9cfd1d, 0x9aa44138, 0x22bc5fc7, 0x713bb03e, ++ 0x3c4fb5bc, 0x17e675a0, 0xc2f3c16f, 0xd50faaad, 0x02e315c8, 0x473d00af, ++ 0x771d055f, 0xe44ff88b, 0x0b8d97f3, 0x007fc79c, 0x6498febd, 0xdfbc0b8e, ++ 0x781be0ba, 0x0eb595ff, 0x102e37e8, 0x19fc0abd, 0x9217dcf1, 0x2849ddfc, ++ 0x4dbe7b6f, 0xdfa418f1, 0xe7709834, 0x60e7ef73, 0xb51dfc3c, 0x0f7a3efb, ++ 0x8eab45e2, 0x8be56dfe, 0x753c91af, 0xf1413dee, 0xaae22652, 0x0fe7ac9d, ++ 0x33897f8f, 0x5c3b357e, 0xe8209e3c, 0xaf06f180, 0x5c45f29b, 0x11b5f381, ++ 0xce2fe86f, 0x2791c230, 0x78f1ebce, 0x378ef548, 0x4bdeff84, 0xd2026937, ++ 0xe365d4eb, 0x741e06e3, 0xb10dc3c4, 0x71c4b471, 0x5a389e9d, 0xf88cdd1c, ++ 0x0c9c4f59, 0x978c6ce0, 0x12d7a584, 0xb73b65c5, 0xa75bf8f2, 0x8f7cf89a, ++ 0x77cb5711, 0xf86dc9c4, 0x5769e2ea, 0xc5a7c79a, 0x978700d3, 0x57c78dda, ++ 0xf58927c7, 0xeae3897b, 0xddfbc3f6, 0xdf32a9af, 0x835970af, 0xdfb81d53, ++ 0xa34a7ad4, 0xb7e0650b, 0x8cec6207, 0xb19e710e, 0xe29959e3, 0x47226b2c, ++ 0xebc7bf49, 0x2f3f630f, 0x6265bc7e, 0xf3f64bbc, 0x8f63a3f5, 0x7684ec2b, ++ 0x201c8e3a, 0xfbb25ebe, 0x8e79c514, 0xd6aefced, 0xe2deb31e, 0x998e11fa, ++ 0x87f3c74f, 0x30dc790b, 0xe536fbf1, 0xd4d76e0e, 0x4fdc4c1c, 0x4cf7eecd, ++ 0x450e2cfd, 0xf53e7e34, 0x559dfdf2, 0x7b6277fc, 0xba54db67, 0x22367a5f, ++ 0x3fda2697, 0x8aa1ddbe, 0x4f3374b8, 0x73a51d61, 0x7df827e7, 0x272f7190, ++ 0xe5ed39d1, 0xc0df4a27, 0x8396c0f7, 0xd97da358, 0x69f392ba, 0x07fa7feb, ++ 0x4f5bbd21, 0xfae32ddc, 0x1bf10fb5, 0xbd166763, 0x05d93b52, 0xcde8a1fa, ++ 0xd76438c0, 0xc373bd78, 0xfc698b49, 0xae264fd0, 0x0ed00d0b, 0x73c02fde, ++ 0xd91e3858, 0xe38a525d, 0x6e8b7591, 0x566e704f, 0xa17b8a75, 0x37555da2, ++ 0xf8676b9f, 0xd3b4170e, 0x9f38d239, 0x3c464814, 0x9b36dfbd, 0xf240b6a7, ++ 0xbddfcee5, 0x4766f423, 0xaf458f9d, 0x1054f7e1, 0x97e711ae, 0x2d1e0e2b, ++ 0x11583d41, 0x93be1891, 0x933588b1, 0xa4736cdc, 0x6625f388, 0xe0f2a2bb, ++ 0x657ca9af, 0x98bf2f2b, 0xde3ca845, 0xfbb58967, 0xe36323aa, 0xdfce11ec, ++ 0x49dce25d, 0x744587d5, 0xe718d10e, 0x1d4fc11e, 0xcf49ba75, 0x9cf8e157, ++ 0x8da92f78, 0x0c8ea9fa, 0x9463f530, 0x66f0feab, 0x4ad57b53, 0xf55bf11b, ++ 0xfca39f87, 0xf3aaf91e, 0x6ffa1e10, 0xdc69907f, 0x48dfedbd, 0xb6fb1fe7, ++ 0xe3f2913f, 0x667aafcf, 0xd66538f0, 0x09cd234c, 0x190cfea3, 0x93ca87f7, ++ 0xbf80f5c2, 0x12f83d36, 0x6b8f03ea, 0x198fee53, 0x8134dbbe, 0xd2ff81ce, ++ 0xb83bce21, 0x779f9b99, 0xb02c8670, 0xb7cd7f0e, 0x4644e36d, 0x765e19e7, ++ 0x60679ec4, 0x23d442d1, 0xdf3eb946, 0x643bcee3, 0x85501563, 0xbe6718b2, ++ 0x7eafa778, 0xc21b7bba, 0x7bf8bb4f, 0xfbac3963, 0xd86f9e30, 0x5c87fc2e, ++ 0xf7e64f8c, 0xb3ec777d, 0x369637be, 0x10e978b9, 0xeb39ac1f, 0xdef04b53, ++ 0xc59dda4c, 0xc1d20c2f, 0x4af8b06f, 0xda7c9cf0, 0x64c78ab7, 0xfcecdc01, ++ 0x557f8729, 0xe007263c, 0x72af5d67, 0xe744b178, 0x591f3b60, 0xc2fe825d, ++ 0xb3d3d667, 0x3d663300, 0xdfc467fd, 0x779bc0f9, 0xb9e2f02c, 0xbc4d6e8a, ++ 0x72c01047, 0xfc702783, 0x7cdf3b65, 0x21c1fd01, 0xa895f696, 0xe2f1be5f, ++ 0x7f742907, 0xa873bc51, 0xe91d06b3, 0x2e135908, 0x5e7ce65d, 0x058e779f, ++ 0x094e8d3f, 0x1fc09c3a, 0xa08ce76b, 0x56bebd77, 0xcfc6c331, 0x47cf9a01, ++ 0xe88d3d30, 0x95d05f3a, 0x0b96fb89, 0xca167cc4, 0xc4078d21, 0x237ac59b, ++ 0x550e5fde, 0xfdea9fc9, 0x21ae3165, 0x23df7ece, 0xd3a673cb, 0xc694647b, ++ 0x67f647bf, 0xe6286047, 0x987f9567, 0xbc6e7c83, 0x4eff162f, 0x2dba5319, ++ 0x6df9ec89, 0xfeb29de2, 0x3389fbc6, 0x9fb63d78, 0x9eef43f7, 0xa36720e3, ++ 0x3c3e6be7, 0xc57a39fa, 0x7a429f38, 0xa89f9f80, 0xe7c3f411, 0xc3fee912, ++ 0x6bf68c83, 0x1f92acbb, 0x2faeeefd, 0x66feb4eb, 0xfe469fcf, 0x3723976f, ++ 0xba8ce782, 0x7da5e2be, 0xfc1de33d, 0xa39307c1, 0xc3c93776, 0xb87938c5, ++ 0x737fe668, 0xbc975dbf, 0x3da9dbfb, 0x0607b45d, 0xd8fdcc75, 0xabaf992e, ++ 0x1a5e755d, 0x3a1660c7, 0xd5da768c, 0x29dd37f6, 0x1f416bec, 0x58ccfbc0, ++ 0x3fd9dfbc, 0xf416eefd, 0xfd113bbb, 0x738fdfe2, 0x63f78339, 0xc7e533b9, ++ 0xf8b91de8, 0xe9e2e377, 0x3f34a35a, 0x33565785, 0x7647be0e, 0xd1b74182, ++ 0x7d10c62b, 0x8958e862, 0xe0fa3f7c, 0xaf1c167b, 0xfb27bf41, 0xa0fe4739, ++ 0xf11faf93, 0xb59465fd, 0x28260c0f, 0x35e9d2bf, 0x5b42ebe9, 0xf9014f91, ++ 0x78f0b4cc, 0x52f2df51, 0xfb40f9c2, 0xdf3b9779, 0x76f3a859, 0x38f5ff01, ++ 0x8dff031f, 0xfbdfa14e, 0x961d7fe2, 0x7a53fc03, 0x0c7ff815, 0x7f87f5cb, ++ 0x2c5b4fc3, 0xdc62c2f4, 0xf9fe02af, 0x464677a3, 0x225bf41e, 0x17ff893b, ++ 0xff62c8b5, 0x654bbf92, 0x374591e8, 0xfbc61ed6, 0x2ebe8b90, 0x17ce9f11, ++ 0x139e50ef, 0x9fc650ef, 0x0b2f2c17, 0xf2bc9e91, 0xe930c1b9, 0xcd3bc5a1, ++ 0xf97b3bf9, 0xf9ce8736, 0xf46684a2, 0x8f199bbe, 0xa14e0bff, 0x2ddbe62f, ++ 0xc66befb1, 0xad7061d3, 0x3cbe74c5, 0x3b4f726b, 0x2c7bb7e4, 0x3e28d7de, ++ 0x619553f7, 0xa4afc7dc, 0x11f7a38d, 0xb05349c6, 0xb72162dd, 0x56437b46, ++ 0xdcb4ed98, 0x61fef990, 0xfef9937e, 0xf366b0e1, 0xb66bc3fd, 0x8e1fef98, ++ 0x1fef9b0c, 0x7af3b75e, 0x722a3c13, 0xe8fca993, 0xf04c93fd, 0x99bfe898, ++ 0x3e3d8fca, 0x6f8f04c3, 0xfe54dbbb, 0x4d739386, 0xaf6c6fdf, 0xf9bf7d34, ++ 0xf826659d, 0x30ffee96, 0xe02e8f95, 0xdd48f17a, 0xafbc228a, 0xc8e5e060, ++ 0x63a2cd52, 0x16e1d2fe, 0x3f3630bd, 0xc42defc3, 0x7e8fc8b4, 0x32f27f72, ++ 0x5150f6d9, 0xcc5cfaec, 0x9b5e9354, 0x9dc3336c, 0xe657e14e, 0xf100bf00, ++ 0x572714ff, 0x9aab6a83, 0x70380386, 0x873a50d1, 0x5175f20d, 0x578bb7e8, ++ 0x263edfa9, 0x5d125af9, 0x7cbc7083, 0x400def19, 0xd8efe21a, 0x9f1f77f1, ++ 0xd4f99bb2, 0xb15e8fd3, 0x3ff38cb9, 0xac4e3ccd, 0x4c558d97, 0xbfe46272, ++ 0x5f362e33, 0xce8d385a, 0xaed7f4ff, 0xdd7799ea, 0x6a97d00e, 0x8d4a1cd6, ++ 0x8965d5fc, 0xcf24af7f, 0xe76dfd25, 0xb1f4b7e2, 0x685cf29f, 0xbcbda53f, ++ 0x2dadcf19, 0xfc9ba7b9, 0x19ab2cdd, 0x7f30bd2f, 0xcf18d85f, 0x00ac75d3, ++ 0x5ee379d7, 0xc44802db, 0x5df34d7a, 0x0c8cfaf0, 0xdd906f3c, 0xc73c1f8f, ++ 0x33f5f5c5, 0xe6eba175, 0xcd98e123, 0x273c9f74, 0xf682535a, 0xce7110fb, ++ 0xf125b37a, 0x055ba7f9, 0x9151325e, 0xd4e09da2, 0xbe7f7e28, 0x3e374dfc, ++ 0x0d655471, 0xef82eade, 0x15b74773, 0x3d3f7789, 0xe3bd5c33, 0x8e51f436, ++ 0xde99b033, 0x8d3307f3, 0x7990beff, 0x04f7993c, 0x7be1734a, 0xe7c5aa43, ++ 0xc25bb824, 0x1987b4fe, 0x1be5001b, 0xf8d32afe, 0x48dc8e1a, 0x673482e7, ++ 0xc6e3e290, 0x3738993c, 0xbc07ec60, 0xfc8b369f, 0x7b6b86c3, 0xfbd105ee, ++ 0x033bef32, 0xfbeed86d, 0x9efe549b, 0xf4c924e5, 0xbcd9c73d, 0xa38c18f4, ++ 0xf141d5bc, 0x17cb6541, 0x3cd1bfc8, 0xcf0d3c7c, 0xa25b2c48, 0xb638f0f1, ++ 0xf003e39b, 0xdbd13b70, 0x62d17b9f, 0x57be1a4c, 0x5f746b27, 0x713f7074, ++ 0xf18c8784, 0xe89847fb, 0x798d759c, 0x27a6f2dc, 0x73c31e96, 0x3e1d7b1d, ++ 0x175c3a6c, 0xcf357415, 0x8cda757b, 0xf785de2f, 0xe9915eeb, 0x3b6f6bbd, ++ 0x1f34a963, 0x804e1c39, 0x306e8377, 0xfc7087fe, 0x9a1296f2, 0xf7a0ae6f, ++ 0xae37a042, 0xa04b1e03, 0x619fe894, 0xf8df3861, 0x1c848479, 0xdce974af, ++ 0x7394f78f, 0xbfccf3f9, 0xb7b4076e, 0x7aefd5da, 0xebe2e4df, 0xf69fa53d, ++ 0xb2aadefd, 0xca9863b6, 0x0cec997e, 0xc7876ac6, 0xbfa0cdda, 0x1aed8abe, ++ 0x70fc9cb0, 0xbfdbb621, 0x1a6c167d, 0xfb657b9e, 0xe432ed0c, 0xdb2ec33f, ++ 0x18bf371a, 0xc5c3bb7d, 0x57a52df5, 0xe1776fa1, 0x1ddccf78, 0xa4cf684d, ++ 0x5df5896b, 0x8d7fc0bb, 0x0f3a31ae, 0xcd7ecfd8, 0xed895daf, 0xa3d6feb8, ++ 0x791bf92b, 0x0d4f830e, 0x0efdcf3d, 0xfed1ae56, 0xe1e385d1, 0xbf71c3b5, ++ 0xe74793d3, 0x676bfb79, 0x8d2f8ad0, 0x7819fa45, 0x6ccba9fb, 0x7f1e039f, ++ 0x8bf8f021, 0x02ac7884, 0x784c5a3c, 0x1975d97c, 0xeb33f0bb, 0xbdf30af9, ++ 0x6f814e9e, 0xc5dff7d0, 0xfccfcefe, 0x31c6117d, 0x48becc96, 0xf733fefa, ++ 0x4f5e6653, 0xfa1c3f0c, 0xe9fb1e79, 0x1157f99c, 0xb8a76d3f, 0x6bdefd5f, ++ 0x58ce3192, 0x6f47a93d, 0x987db8d8, 0xfcf07a47, 0xc71fab3e, 0xc7953e79, ++ 0xbbefce9f, 0x39c618e1, 0x4f1dd5ce, 0xf9efa58d, 0xa9144fe7, 0x3df9ded0, ++ 0xd2148a27, 0x3bd361e3, 0x7e97d5d0, 0xf670145d, 0xe1e843de, 0x875f1b37, ++ 0x3c79d936, 0x173c49e5, 0x55b19a37, 0x3be10a7a, 0x81b2c333, 0xfdb70bde, ++ 0x78dbe07a, 0xafb8fcc5, 0x2f564018, 0xa016b3f9, 0x24e39d1e, 0xb3e4f17e, ++ 0x4f50b911, 0xf1e2d68b, 0x79ff6665, 0xfd3be198, 0xf4a2578e, 0xcdebbf5e, ++ 0x495eda76, 0xc4ad9b7e, 0xf4dbe8a7, 0xda1bb260, 0x4af0e94f, 0x757f00c9, ++ 0xfa0f58e8, 0xae64cafc, 0xb2efbb7f, 0xd2d77bd1, 0xf2db9fbc, 0xccb72f81, ++ 0xe3eff850, 0x82979f1d, 0x9d2ec87e, 0x19e067bf, 0x64c7c3d2, 0xf02acf0f, ++ 0x984c5ede, 0x023bd3f7, 0x90e9ceba, 0x5b59659a, 0x82b4fd0c, 0xbc050c5c, ++ 0x3f16bcb9, 0xe8987dff, 0x78866b25, 0xadee5397, 0x5cf510e7, 0xf893d1d9, ++ 0xcd38f85e, 0xb8a193f7, 0xe2ca32ef, 0xc479f7a3, 0x46c98abb, 0xcb5f713d, ++ 0x97a2e7b8, 0x76c3df9a, 0xc52cd605, 0x27e716fd, 0x52cadab7, 0xf316fde9, ++ 0xb8eef177, 0xdf399c73, 0x5bd89011, 0x5f177c31, 0xe1bcbe2f, 0x7cea6477, ++ 0x6ceafb1c, 0x75fddf34, 0x08286fba, 0x3cebf7d8, 0xf3ac1e94, 0xbaa1fe52, ++ 0xeb469411, 0x83a6947c, 0x81edc01d, 0x00f78dda, 0xe3eed21d, 0x7c1bfaef, ++ 0x7f1d48f4, 0x5607bb9f, 0xddf12723, 0xc85feeec, 0x3f959784, 0xbcfc4b1f, ++ 0x3ef41479, 0xf357bf9a, 0xfd9d8c56, 0x659f8ad4, 0x917d014c, 0x324fd0f5, ++ 0x6d3f00a6, 0x0bb9f896, 0xd8a517b0, 0x5af5e4fd, 0xc14bebc0, 0xda98addf, ++ 0x78458368, 0x8bbc1ab5, 0xa162818d, 0xe47ffabf, 0x7839dfc1, 0xdf02cb3c, ++ 0x1a9b944b, 0x71c39f6d, 0xf9ec9ad5, 0x663ce2f5, 0xbf7e24cb, 0xd7bfc8d7, ++ 0x4eedf5cd, 0x775ef8a9, 0x37c1fe02, 0x9a9fc9fc, 0x30779c6d, 0x802993e3, ++ 0x23f9c017, 0x24bc72f7, 0xf87d63eb, 0xdc8ffa9e, 0xdfc33d86, 0xfbfa3191, ++ 0x8dddf891, 0xb88b23e4, 0xbfe1e3fd, 0xf1a69177, 0x30588ef7, 0xdfcef4d5, ++ 0x084ed13a, 0xff7c6919, 0xda24377a, 0x00f4771d, 0xfc007dc3, 0x7f58875d, ++ 0xff08eb3e, 0x422d8a1d, 0x03d02d2f, 0xa35f3855, 0xbe3df19c, 0x4bd6919e, ++ 0x473c7ac1, 0x22c51a1b, 0xae58df28, 0xbfa5ca18, 0xc2677fc9, 0x57bb4738, ++ 0xbdf8d9e0, 0x5c493f91, 0xb489cf2e, 0x5de7a453, 0xdf094781, 0xcf669ef3, ++ 0xf7aafe01, 0x3628bd59, 0x447e8ee3, 0x09fd75eb, 0xf9e786cd, 0xa29e0fd3, ++ 0xa97accfd, 0xf453435d, 0xb79df779, 0x5eb4bc61, 0xf0e2cdad, 0x6f184d5d, ++ 0xfb55d27d, 0xc8f1ff14, 0x7e436f3b, 0x0aef14c8, 0xdea08720, 0xf01bb56c, ++ 0xc83f46ac, 0xe1caab4c, 0x1b33dde7, 0xd708d943, 0x0977c1ce, 0xf6806e10, ++ 0x83fc535b, 0xd29c9f90, 0xb7e3c6f4, 0x9f946c20, 0x14ef88de, 0x7ceb72ec, ++ 0xcc19c6bf, 0x07a53b45, 0xc57601d6, 0x99870ac0, 0xfcc6a78d, 0x447e8faa, ++ 0x1c979de7, 0xa571efe4, 0xe12e9c1f, 0x4ff7d33c, 0xd05ffc27, 0x7a57ba4f, ++ 0x9c3dee29, 0x2e3c0faf, 0xb8c3d06e, 0x1ad53b6f, 0x263b81fc, 0xb73df3fe, ++ 0xcc9d6f58, 0xd0bf7b19, 0xb4f5ca2f, 0xaae8e227, 0xd29bbf85, 0xf9d194bd, ++ 0x9dacc1e8, 0x221b8fde, 0x172c1f7e, 0xd191f7df, 0x1aaff435, 0x70efdf08, ++ 0x61de7df3, 0x9b5f73bb, 0x3bf97aca, 0x1fbb50ad, 0x9c7a70f5, 0xd093731f, ++ 0xc5eab7cb, 0xba43271f, 0xbbd00a49, 0xfc03a154, 0x99db271e, 0x21d4f245, ++ 0x66b9d674, 0xae9dff0b, 0x5f9481da, 0xabbbee25, 0xe81b22ab, 0x539e2df7, ++ 0x717b9f69, 0x7ae3246e, 0x643aef67, 0x14e2dff0, 0x37dc6f9e, 0xb38c7845, ++ 0xc9719f77, 0x78398dfe, 0xc3dde26e, 0x9e1d13af, 0x41a5ce4c, 0xd09eb757, ++ 0x77da2e82, 0x7ac170d5, 0xfeb3ded7, 0xdabbbad2, 0x99be4bee, 0x8f7a35eb, ++ 0x85f3476d, 0xe76f11db, 0x7e98b61e, 0x8f48c34f, 0x41ce21d4, 0x4160ebde, ++ 0xa8e01f05, 0x019feeca, 0x23d39ced, 0x0edf1c6e, 0x745ae07f, 0xffc92c09, ++ 0xf41d9b71, 0x5f9e4b59, 0xcb3e80b7, 0xd1b1ac7e, 0xa2d6fc06, 0x1f9123e9, ++ 0x343793b3, 0xb62fbf22, 0x19c7e2cb, 0x1fe4bc37, 0x0055ce2a, 0xcfc3727c, ++ 0xc9fdc36e, 0xcc9f6ccf, 0x3541db37, 0x0bbef89b, 0x325227d8, 0xd20965e0, ++ 0xad8b6003, 0x6739ee8d, 0xaf486d23, 0x6e65ef99, 0x0c9eb892, 0xe7f1e6cd, ++ 0xaccfdd2b, 0xc2c1d0f8, 0x93f87631, 0x7f03e8b8, 0xda212854, 0xd0f8aa8f, ++ 0xf6ffdf4d, 0x7ba6ec7e, 0x71fb7da0, 0x9fa377d2, 0x287edeaa, 0xfaf55b3e, ++ 0x8fcff211, 0xd9d86b5c, 0x96175a7e, 0xcbce20bf, 0xd899fdd8, 0x132a93ce, ++ 0x0b7f01f4, 0xef6f4cf0, 0x80a43873, 0xa3da3a3e, 0x4e36b68f, 0xc6fa46c9, ++ 0x2609a7e8, 0x8057e57d, 0x0493476e, 0xb895da1c, 0xf95c527c, 0xd3de033c, ++ 0xdf626538, 0xef693cf1, 0x5e506d85, 0x07b58bf9, 0xb46df1c6, 0x6a97b5c4, ++ 0x6a7dfff4, 0x93bfe0cf, 0xe12fa3ee, 0x53474f3b, 0xbe78c502, 0xf3367bac, ++ 0x437c3ca2, 0x62fbb6e9, 0xcdd270e8, 0x1f150de3, 0x7fc2675e, 0x4d0bde2f, ++ 0xbcea67f9, 0x85eb7da6, 0xf74cbfbb, 0xdf8a4e7d, 0x2160aa29, 0xe9ed8f7e, ++ 0xf57ed37c, 0xb3e38dff, 0x9fb8a38e, 0x07f94c71, 0x49a4638f, 0xa38ef40f, ++ 0x59ff94c0, 0xcca721c7, 0xfdc5cd2a, 0x7a1695a9, 0x12c332af, 0x3da1e5b2, ++ 0xfc85a0f7, 0xf16d3414, 0xce1819dc, 0xf5bfdfa6, 0x41ceb41e, 0xb0abdcfb, ++ 0xca2a4ae3, 0xbf8bdf93, 0x407a14fb, 0xf20b75a1, 0xa8f5ea6d, 0xf8fd9b0a, ++ 0xc15b15ee, 0xfcef3da8, 0xfa373560, 0x17377e63, 0xb159d1fb, 0xf4d3f902, ++ 0x7a0eb439, 0xc1ac1ecb, 0x699d5b72, 0x2666aecf, 0x657b2579, 0x0e74b4b5, ++ 0x4bdfb7da, 0xed11a37e, 0x6e24cc9b, 0x8dec48df, 0x2637e3c6, 0x75e5cefa, ++ 0xdc6f63df, 0xf08cf186, 0xfa2d762a, 0x387b6175, 0xb0e90472, 0x78f649da, ++ 0x26e123ee, 0xd6bcbf9c, 0x28dbbf42, 0x6e7784a7, 0xe1d1f843, 0xc237b43e, ++ 0x76bf5c29, 0x3d9274af, 0x542ea6b0, 0xd4b2ef84, 0x6075f337, 0x1d44c35b, ++ 0xc1a16f7f, 0xefc15809, 0x785ded6a, 0x8f4fe4af, 0xbb68d47d, 0xaf98f511, ++ 0x61ce8069, 0x6bae164f, 0x4636cf2c, 0x2e75877c, 0x440d92bc, 0xf380d257, ++ 0x0a5602ff, 0xc88f99e9, 0xce706b2e, 0xfebc64a8, 0xbc1f784b, 0xf10f47a5, ++ 0x0473f8ef, 0x51802784, 0x7b2bca0f, 0x79814fbf, 0xd73aff6f, 0xfb41af53, ++ 0x7cc1a768, 0x0c376442, 0xf63e6853, 0x2c9bfe14, 0xb47991f6, 0x73b6191f, ++ 0xff247bb8, 0x6923ec6e, 0x8fb42cc3, 0xb0f81764, 0xdaf2f167, 0x0a2f99e7, ++ 0x5272e6b0, 0x3df8c41c, 0xfe33274b, 0x54bc79f8, 0xe124b3ec, 0xfc31083b, ++ 0x46586b68, 0xeff1e89b, 0x9fbfc729, 0x5cdf30ac, 0xdd64bbb4, 0xb271ff9c, ++ 0xe54a57d8, 0x6f993fbf, 0xfcfed209, 0x76442c35, 0xa513481a, 0xe528b1d7, ++ 0x04ed628f, 0x34af468f, 0x7967af1f, 0x9f3285c5, 0xc664f68c, 0x2b7c465d, ++ 0xaeb8eb28, 0x147ec2eb, 0x369b5bbf, 0xd3ed3e7d, 0x22587fff, 0x80000e1f, ++ 0x00008000, 0x00088b1f, 0x00000000, 0x7dbdff00, 0x55547809, 0xb57df096, ++ 0x542aaa57, 0x646caa92, 0x280810a9, 0x89212b01, 0x849520a0, 0x152da8b0, ++ 0xb16406c4, 0x4d900d58, 0x65ba6da5, 0xe90414be, 0xba1b4c80, 0xe9569719, ++ 0x5b1bb102, 0x9d1a09da, 0x558b51a8, 0x8ffa1dfc, 0x88f4ad0c, 0xb20bb576, ++ 0x3dd38327, 0x7fcb8cf4, 0xa6f7b9ce, 0x8154bdea, 0xe5e9fcdb, 0xefbbdf72, ++ 0xe7bf672e, 0x392b7b9c, 0x9677a025, 0x3fc1b633, 0x0f1ac1f4, 0x7f6b5b63, ++ 0x331409e8, 0xd7cc66e6, 0x8556e501, 0x33b0eecd, 0xe96576c6, 0x4b633a58, ++ 0xb6fe8c2c, 0xc46a1539, 0x2ac75398, 0x84e55b18, 0xacf7c27f, 0xb3b79b39, ++ 0x32ef7af2, 0x30d76313, 0xe50194d6, 0x2fb7a820, 0xe7846c9a, 0x9554feab, ++ 0x2ffd0a91, 0xffa071c3, 0xa6548f65, 0xddf01d07, 0x0f2639de, 0x02cee594, ++ 0xd6e97fea, 0x1460535a, 0xd0badfbc, 0xfde62be4, 0x0c7ce0f6, 0xea0c41de, ++ 0x83bd5bf7, 0xd63195c6, 0x76cf4477, 0xf0afe3c0, 0x72c0e26f, 0x640c0b5f, ++ 0x8b40ec66, 0x3386f985, 0x5e1e4a16, 0xd4a192c5, 0x654b1f31, 0xb3d1bf6c, ++ 0x7e82ebd9, 0x62f50e36, 0x9f24a13f, 0xa1ea0521, 0x56de3dbb, 0xf56a3fa8, ++ 0xfbe0f674, 0xeef2487f, 0x5377d0f0, 0x7fae2959, 0x08e4f392, 0x2fdf14c6, ++ 0x896caf95, 0x330987c7, 0x5f7f876c, 0x14bc61e9, 0x1edf8776, 0xa4beff5d, ++ 0x770879b3, 0x46eb80a7, 0x93b9655b, 0xcb139f4a, 0x6302526b, 0x445b5ea9, ++ 0xced57278, 0xc67b60b4, 0x6d279c72, 0x3a5d7ed1, 0xb4fec016, 0x20cfffe3, ++ 0x4b1cb7e8, 0x126f1716, 0xf22f12cf, 0x2f8a55bb, 0x789c59c3, 0xf4974d5d, ++ 0x5316942c, 0x9c99f437, 0xa26e7c76, 0x969c17e7, 0x3cc60ea0, 0x7ad81994, ++ 0x0a74a03d, 0x983031eb, 0x79293ea7, 0xab45d234, 0x96077935, 0x7d8d3253, ++ 0x5f5b4111, 0x0059ffe1, 0xc9bf3060, 0x48efcf8c, 0x4ac3e4f2, 0xa41f7e32, ++ 0x3bd9a7ef, 0xf4086c0d, 0x19bba8eb, 0x0b2378f1, 0xfced73d3, 0x630fdfa0, ++ 0x51e69dfb, 0xa11a6fd7, 0xabc0ffae, 0x241633ae, 0xd2d03d78, 0x31b1f15c, ++ 0x8c03efda, 0x0388ed4d, 0x58031f97, 0x772bce11, 0x8f1f4359, 0xd0d3f688, ++ 0x37aaa291, 0x3e856575, 0x2567198e, 0xf90b23fe, 0x9ebbaf87, 0x730e62bf, ++ 0xf788c7e0, 0xe1311606, 0x4d0280fa, 0x9b07e07e, 0x5f11f995, 0x1f56bde1, ++ 0xb26cba03, 0x015bb69b, 0xb5dd4dc5, 0x6e7842ca, 0xe47bc073, 0x6943ac63, ++ 0x40f6f233, 0xf83f34b9, 0x1be031f3, 0xfb733fb7, 0x29f88526, 0x37d476b3, ++ 0xfc23779f, 0x4ff00d6f, 0x8a3d81a3, 0x475fe9f8, 0x3d23ac3d, 0xb6f38eba, ++ 0x8e982a0f, 0x2e4ba3d6, 0x3130ba47, 0x3d745065, 0x4b5e1adf, 0xda6af0d4, ++ 0xaeea0f6a, 0x419471a1, 0x76c6b700, 0x7504d05d, 0x84c7a59d, 0xd200f2fc, ++ 0x95bc1c79, 0x687f393b, 0xf119bcf1, 0xf69f871c, 0x885dcab1, 0xe7277297, ++ 0x07eafb27, 0x831e3e2a, 0x494373f2, 0x0ddbda00, 0xe01a7e5c, 0x139066bf, ++ 0xe5e4ff16, 0x69a1a329, 0x67efe732, 0x3e543d93, 0xc415f8a4, 0x57ceba6b, ++ 0x7b190ac0, 0xd966c618, 0xbd60f082, 0x7d655b0f, 0x1526cfd6, 0x8f78bf23, ++ 0x9fc72733, 0x29ea1321, 0xc9b3fdfc, 0x5106a74b, 0x17d7f61e, 0xa3c705b5, ++ 0x3bf5947c, 0xd03982da, 0x2b6580be, 0x8ef38f00, 0x8788d3c0, 0xc2878e03, ++ 0xd69fa07a, 0x331ecc17, 0xe7ab81d2, 0x45d00083, 0xb6668bfa, 0xb9adaa09, ++ 0xa99f6857, 0x3ac05f69, 0xb613df91, 0xaef681cf, 0xc8167b68, 0x37743922, ++ 0xd24016e2, 0xb9f8e46a, 0x2833d438, 0x65dc0e25, 0x80047fa9, 0x5a772316, ++ 0xca0b5e0d, 0x3efb569d, 0xb9518b92, 0xfa3de9cb, 0x1dfd499d, 0x1c3605e8, ++ 0x43334dc5, 0x7ec7ac3c, 0x1bd7be62, 0x57ec4ebd, 0x56da559f, 0x98cc65e0, ++ 0x01aa75b2, 0x4006d8e4, 0xb18ebb2c, 0x11f7edd3, 0xf78c379c, 0x5b0f91f9, ++ 0x0eb6069d, 0x0ed6b9d6, 0x69700ec4, 0x708434cd, 0x205326dd, 0xed105c33, ++ 0xd03110d7, 0x87da2e3c, 0xb44b1e90, 0x6025d34e, 0x0eb831aa, 0x9cac667b, ++ 0xcf1bdfff, 0xe3b4ed4e, 0xdbcbfdb1, 0x8b3c600a, 0x02b5e753, 0x3b1ecc9e, ++ 0x1f8628fb, 0x1e18fdb5, 0x47edc431, 0x3fc24edb, 0x918d9e21, 0x85c7c464, ++ 0x50d4dd4c, 0x4f0f799c, 0xadf4fce1, 0x8d3cc7e5, 0x2f1f729c, 0x4af7e30a, ++ 0x80a0b924, 0x14f0c8e4, 0xc7469fa0, 0x3cf83fc5, 0xfdd2af24, 0x389ece0e, ++ 0x2acc86ee, 0x2ae4804b, 0xfd949fb3, 0x9fd313eb, 0x4de98b84, 0xf8742ab0, ++ 0x7f6199be, 0x41838257, 0x99be12f1, 0x2a9ec0c3, 0xb19ef818, 0xfe9f34ed, ++ 0x310f48f6, 0xe0dfbfeb, 0x4e363a27, 0x00fc5a08, 0x459eb5c7, 0xdbd40896, ++ 0x0b079e0c, 0x137a7ed0, 0xae0f27ec, 0x7f8a8667, 0xec09b964, 0xd3f60626, ++ 0x6a9d14cc, 0x4a4cb23d, 0x27dc7760, 0xef69b3f0, 0x65e57f1c, 0x99c407e8, ++ 0x2937e91f, 0x7d44e0d5, 0xf9f23464, 0x38dfb0da, 0x26fd91f3, 0x7b03d782, ++ 0x960fc4ad, 0xf5084b62, 0x0dbc76a2, 0x67cd3f06, 0x8827cc03, 0xfe3e1cf5, ++ 0xb9c1a706, 0x46dbda03, 0x0c4b3124, 0x33594cfc, 0x5d17fe09, 0xf787a62e, ++ 0x8f405c1b, 0xe12bd671, 0xf4e10534, 0xa032e85d, 0xef61cba1, 0xc4bd2114, ++ 0x534fe5d0, 0x72e903dc, 0x72ffca0a, 0x89667f3e, 0x41d0ff9d, 0x803af0f1, ++ 0x5374353e, 0x90f99e31, 0xdca032ef, 0xab05eb0e, 0x629eea6b, 0x1cbc079c, ++ 0x659bf307, 0xf7904e67, 0x4dcab4de, 0x3d1527c8, 0xf90c4cfb, 0xeb4dd3a1, ++ 0x6bdf17a8, 0xc0bbfdc7, 0x9c53dfdf, 0xee3a0e54, 0xc022667b, 0xc927b3b7, ++ 0xceabc0a3, 0x6b1f6e54, 0x45397bbf, 0x3b4bf611, 0xd1910d2f, 0xf6c83f68, ++ 0x6f98f315, 0x93079407, 0xf4059b58, 0x722993ee, 0x5e0bf29f, 0x6171801a, ++ 0x8cafe99c, 0x8f7641dc, 0x5041ff58, 0x3d3ed80b, 0xd15a323d, 0xedbc077f, ++ 0xe0c7d582, 0x2912c1ad, 0xbff53b42, 0xc40e814d, 0x48f1d357, 0x8f3bd63a, ++ 0xdf7b219e, 0xb0edcadd, 0x216c97be, 0xf881bba4, 0xabf34b59, 0x059834bf, ++ 0x5bc40cc7, 0xf64c21bd, 0x3ca5fd76, 0x0eeb0f7a, 0xefa3525a, 0x8e2d03a7, ++ 0x858a7dc5, 0x13e109c3, 0x14bf1f0f, 0x01f12af4, 0x21d238fc, 0xfa7081f0, ++ 0xfdebd850, 0x369b7778, 0x9cee7ee0, 0xbe673f85, 0x213f7c11, 0x4987f8f4, ++ 0xf6062179, 0x724587ce, 0x8f49e6bf, 0x56f53bd5, 0x61b383df, 0x3d6decdd, ++ 0xc58a0a7b, 0xb436f6d5, 0x7d9b1707, 0xbe781483, 0xcaf4dff8, 0x210202da, ++ 0x0152c1f1, 0x7bcc73cf, 0xb82fe22f, 0x8a7cead9, 0xc7dea7f0, 0x39543c14, ++ 0xbf7c08e6, 0x45ef4bb4, 0xb55167d3, 0x56fd883d, 0xe33d54f4, 0xdacbe780, ++ 0xfd061e6c, 0x3de89e2e, 0x1e71c7a9, 0x15d67ab4, 0x4867bee0, 0xbbf41665, ++ 0x9c0a9fea, 0xab6c0f28, 0x2f1699fd, 0x8617e280, 0xc7803669, 0x85c2cafd, ++ 0xf8a0094a, 0x068db617, 0x8be1b3c0, 0xa856b3ea, 0xce45fe0f, 0x632e4b46, ++ 0x472ca0af, 0x3b982d3b, 0xbfa9f70d, 0x475da9c3, 0xee3b2653, 0xa2758777, ++ 0xd271bc5e, 0x76aec650, 0x30ecea77, 0xc5a9d9e7, 0x7e302d1b, 0x44afaa7a, ++ 0x492de307, 0xfd86992d, 0xd4707a2d, 0xf7811edf, 0xa693a96d, 0x7801bda1, ++ 0x9b4fdf13, 0x642a0d56, 0xbf5978d9, 0x97758ac5, 0xc6ed458d, 0x873f20b1, ++ 0x3b47c744, 0xd65533b1, 0x049b4c67, 0xd5587edf, 0xfe806d5c, 0xdecea4f7, ++ 0x63157c58, 0x74ad6ed7, 0x17fc60fa, 0xf5a76f53, 0xfb649a76, 0xd07d1b79, ++ 0xf60593be, 0x91fde11b, 0x669d2c5f, 0xd2bac001, 0x584e25fc, 0x81e59a7f, ++ 0x7c27538d, 0xa1197e07, 0xee3bf768, 0xcdf13754, 0xde690421, 0xd7133eea, ++ 0x73df82af, 0xd7f71d38, 0x11dd4047, 0xf5e4cf53, 0xe5f175ce, 0x5c69bbc7, ++ 0xc526757f, 0xca9a5f7f, 0x3bc00be5, 0xecfa43ac, 0x158685b2, 0xf009e544, ++ 0xf12c6593, 0x27ce16d7, 0x1c3357c0, 0xfb71c7c4, 0x0bfca6fb, 0x3a7ea770, ++ 0xee1b3e0d, 0x035ca5c3, 0x38e1b306, 0x2a3c53a7, 0xb3d15d79, 0xcbede488, ++ 0x3d6f8269, 0x6aee3e1c, 0x96615cb5, 0x8b84229e, 0x58ba6efc, 0xe048c167, ++ 0xc023f44f, 0x573f903c, 0x8fbf6159, 0x953d807e, 0xf632ec19, 0x4aa5fd77, ++ 0xba3fbed5, 0x7cf4498e, 0x9fd0bf40, 0x2deff447, 0x4af03afe, 0x5cbc02b9, ++ 0xeb4afef4, 0xf6a7f68c, 0x8fec0c53, 0xe8062bfb, 0x79fc5315, 0x04e92bde, ++ 0x918bafe0, 0x7c84cb6b, 0xfb45a905, 0x5e2f0bf2, 0x415363b5, 0x38ebb8ec, ++ 0xdf4019fd, 0x2083bcc1, 0x558e515f, 0x61377c18, 0x549e8afb, 0x7a215067, ++ 0xcde82f5b, 0xf126f480, 0x5cda99dc, 0xa2ddeb49, 0xb1c47738, 0x9521ff03, ++ 0x768abbeb, 0x49f687c5, 0x7e80bcc6, 0xa4fccc61, 0x3bfe87fc, 0x9c65ff45, ++ 0xa7e89f9e, 0x3fc8f9e7, 0xbcc1bfc2, 0x06a3df40, 0x6133ffce, 0xafebf467, ++ 0x9c21ac17, 0xb7db848f, 0x3f697fa5, 0x53d427d4, 0x8ccf34c9, 0x3064e1e3, ++ 0x097fd8e9, 0xf8ece87e, 0xd47af928, 0xa67a5d57, 0x51baf878, 0x3948546e, ++ 0x70f37c19, 0x63b250d5, 0x43d972a2, 0x9b948cf6, 0xda258b61, 0x3796fd7e, ++ 0xb947aea7, 0xc3fc066a, 0x907a5c3c, 0x79d1a5e2, 0xfae54eec, 0xf9806c72, ++ 0x2f81d9e2, 0x1ca438a7, 0xba3c75a1, 0x847d9aba, 0x75fa17eb, 0x7e48246c, ++ 0x1c054799, 0xa110edfb, 0x239ba7bf, 0x8f7f72cf, 0x1d651e9a, 0x5d4694ec, ++ 0x7c7fb461, 0xee86233f, 0xd03a090f, 0xcabbe7e2, 0x10438027, 0xf54c60e1, ++ 0xaea1fef0, 0x00617da0, 0x3ff005fd, 0x6ef76b5f, 0xb799882a, 0xb763cb9d, ++ 0xd8e5c75e, 0x95c2f815, 0xbdf7dfc6, 0x8e7e20e4, 0x31db83c2, 0x7e5ca9bd, ++ 0x3ab1d76f, 0xd41c6fdc, 0xfd209f01, 0x2f3af9da, 0xfd4598bc, 0x7dda227e, ++ 0xbb79725f, 0x7ce3c609, 0xc363f64d, 0xabb783cb, 0x9bfbcfe7, 0x52e1c69c, ++ 0x8257dc71, 0xbf30cc76, 0x85fb8bdd, 0xfb199e8a, 0xea2f508c, 0x5ad89c56, ++ 0x075179d2, 0x2ea053e7, 0x77379701, 0x65fbf6c7, 0x5d7be3aa, 0x2671d147, ++ 0x2e7ce3c6, 0xb34a0fdb, 0xfac27c73, 0x834f08cc, 0xf2ca8e5a, 0x7f879bfb, ++ 0x5bd6119f, 0xb140f00f, 0xd9d6e12d, 0x159d70b1, 0xf338f8f9, 0xe85f1f22, ++ 0x851ba858, 0x91847d78, 0x1f2fd77d, 0x4875f2b6, 0xb2e8147b, 0x20b2e903, ++ 0x19fa972d, 0x2b67dc76, 0xd0c3f786, 0x9bef826e, 0xdc211c3a, 0x02d37857, ++ 0x9d70d393, 0xd1aafb33, 0x6b68dc6f, 0x798d6b5e, 0x0bbedfde, 0x071d13da, ++ 0x9e70a3f4, 0xcedec077, 0x340f5d13, 0xaf5fa20d, 0x5a7c04c1, 0xc230f548, ++ 0xdbc4d3ad, 0x1467cdf7, 0xf7d4688f, 0xe83df099, 0x3e889bef, 0x1152ea8f, ++ 0x426fb8bf, 0xef5eb9bb, 0x5f7051cf, 0xa2f6619f, 0x087d801e, 0x2b41fbd1, ++ 0xffa15833, 0x3944a037, 0x6bbfa35d, 0xa6abc22f, 0x8478a150, 0xdca3efdc, ++ 0xf4d37dc2, 0x47a23689, 0x433df9f6, 0xb6eb8fd1, 0x3f413c71, 0xc58fd116, ++ 0xbfe51a52, 0x15779bff, 0x7ea47fed, 0xd428a83b, 0x2309c1cf, 0xecc6b477, ++ 0x943fb08b, 0xda9507ff, 0xfe90bb9c, 0xec8ebec5, 0xef545743, 0x6a52bda2, ++ 0x507bc58f, 0x87922fcc, 0x8f6b1474, 0x6fda7da2, 0xde9f06cf, 0xf2e40538, ++ 0xc23b53b5, 0xd152273a, 0x863f69ee, 0x9ec06afe, 0x6a1c02b5, 0x2c1c5d05, ++ 0x7193ea08, 0xfd60c37e, 0x5250e8f0, 0x1ed9b8a0, 0xf85d271d, 0xdc4dd209, ++ 0xc49e910f, 0x5c69b3cb, 0xf171af4f, 0xa6512df2, 0x2bf7c727, 0xc7ef149c, ++ 0xd8fcb998, 0xbfe5c954, 0xd12addb6, 0x7bb6b7ef, 0xfed5158b, 0x55deec1e, ++ 0x35eedc69, 0xf710bf71, 0xed149f8b, 0x3c21cec1, 0x3f2aed45, 0x1da4f1f9, ++ 0xdb9ed7fa, 0xe490dea8, 0x44fc907f, 0x2abec0ef, 0x24327ece, 0x05ba7de6, ++ 0x63386708, 0x8178b69f, 0xb8fb1970, 0xe5f542c5, 0x3269fe6b, 0x160ad7f2, ++ 0xbafc80da, 0x141ea762, 0x4bfe7463, 0x193fdcd6, 0x52125ffb, 0x7dc14798, ++ 0x35da9f99, 0x69dff808, 0x40a53668, 0xa6ddb4b9, 0xf1eeaefa, 0x94baaa31, ++ 0xfededf17, 0x18a166ac, 0x2f951339, 0xb6b9e993, 0x5acf495f, 0x16c3f43b, ++ 0xf65bad0f, 0x30cd68b3, 0xbf6cbf5a, 0x7d697998, 0xd50adb8b, 0x8d247ff3, ++ 0xf9a24ee4, 0xbb44ba49, 0x9e771833, 0x0ff3d526, 0x7341fe01, 0x0d4e3ccc, ++ 0x28fc79a5, 0x7485d02d, 0x8d879d11, 0xc2c44705, 0x24f3bc71, 0x9ec195ac, ++ 0x408efd0c, 0xe9cbc127, 0x71a43ffb, 0xc3dbe0bb, 0xbb02647d, 0x57fff47f, ++ 0x1e62bfbb, 0x5dacb397, 0x2e90c361, 0xb0eda9e7, 0x2b3ea33f, 0xe426d2c7, ++ 0x8ecabb50, 0x8b16bf42, 0x9c0ddfd9, 0xeefa66cf, 0x5fbc49da, 0x0b7643b0, ++ 0xdb98b97b, 0xdbf58fcb, 0xf66373cb, 0x2997689f, 0xf8cf2885, 0x3f428d77, ++ 0x6a399c15, 0x23b8c0f2, 0x2d7edc5c, 0xd2fafb74, 0x6b66fda0, 0xa3f468f2, ++ 0x85e6b66c, 0x8ff51f50, 0xece5c5df, 0xbc7f6366, 0xb9e1033b, 0x5a7b8bfd, ++ 0x3ddf880d, 0x1c83ff60, 0x00e27cac, 0xa7c8c48b, 0x7c56ac1f, 0x5f0f004b, ++ 0x7bd73c0a, 0xef587db9, 0x42869b0d, 0x7cf5d93f, 0x7b1d395e, 0x77cc4315, ++ 0x9dbc7539, 0xf95465c5, 0x9ea21d55, 0x3872e2e4, 0x0cac2ea7, 0x8fd97685, ++ 0xd80c54ef, 0xfa42875f, 0x1019bb32, 0xecc70315, 0xfcd76e32, 0xb2bb6ca0, ++ 0x870a38b8, 0xb16d5d36, 0x96d6f013, 0x9ea2f36e, 0xd2077069, 0x13cf385c, ++ 0xf18230e1, 0x063d13da, 0xdc5bdbb4, 0x973e173e, 0x9de8f070, 0x6d47a8d9, ++ 0xdb3cf827, 0x5cc5f7fb, 0x964450bf, 0xd21de8ec, 0xb8cc3d2e, 0x2a7a485d, ++ 0xd208dd7d, 0xe97e7277, 0xa44f42a9, 0x7673c0b3, 0xf146df6a, 0x8c71e47c, ++ 0xda2bad67, 0x4e58edc1, 0xfe85357f, 0x26bcf89d, 0x56d2aae3, 0x39b85e78, ++ 0xfb84586c, 0xfbe3c7ee, 0x1e854b81, 0x8a8c7581, 0xe495c75d, 0x4c676c85, ++ 0x7c909fe0, 0x7f1a9b62, 0xcfd8c1df, 0x13e57de9, 0xbe71dbae, 0x0c4debf5, ++ 0xfe1241e3, 0x0fbf6e2d, 0xb1dd93e7, 0x48d8415d, 0x571c9ebf, 0x3df0edfa, ++ 0x2687edf2, 0xfe9ccfc9, 0xd585ca12, 0x5892df7a, 0x44deb739, 0x73769278, ++ 0xcedc7e74, 0xfae2eb9f, 0x7fb759f5, 0xb1a7ce06, 0x79f90b6b, 0x8bfcef96, ++ 0x5a9f9e29, 0x825717cb, 0xf9c752a3, 0x85b67ebb, 0x4f9561e2, 0x560e8818, ++ 0xcc8537ae, 0xdeed7f68, 0x6b3bfdc3, 0x47e51798, 0x651ec77d, 0x72bb8c09, ++ 0x69651ef7, 0xd7075c0c, 0xcf9c1487, 0x43e48770, 0x74b4d72e, 0xb463fe8f, ++ 0xb9590e57, 0xd2ae76fd, 0xe9b8c41e, 0x1ea06339, 0xb2cb9ddb, 0x51058379, ++ 0x67b1bc3c, 0x3833e50a, 0xb187339e, 0xc8edd36c, 0xb6bb40b4, 0xa45e4dab, ++ 0xe07716af, 0x4f802ec7, 0x89dfc1aa, 0x1cb8a7df, 0xadf0b5de, 0x514accc7, ++ 0x385d7e0e, 0x93a1ab5c, 0xfe70d76b, 0x21c85a79, 0xfe452bf8, 0xfbe2e2d9, ++ 0x68a3b00c, 0xc8c8759f, 0xe31cf1d7, 0xe69b3df3, 0x7c7440db, 0xcdc69538, ++ 0xe82b0fae, 0xf3382ec7, 0xd935c91c, 0x7cce947f, 0x5ffe719b, 0x261d9e7f, ++ 0x4295b7a4, 0xb13e550e, 0x6628f953, 0xf4b98fde, 0x377b2ed4, 0xde9da5d0, ++ 0xa2e69def, 0xc1ecccf6, 0xb77d0ae7, 0x8d2fde12, 0x1d723791, 0x0ecee471, ++ 0x44fd8f5c, 0x772e01cf, 0x28cfdcc2, 0xe7c5abe6, 0x70ff28b3, 0x9b6a077f, ++ 0x23829b9e, 0xa1dfd03c, 0x9fd44921, 0xbe5a0394, 0x39d0567d, 0x9d9d4bca, ++ 0x4f64b4fc, 0x76c9f9ca, 0xe7aaee85, 0x4ed75e10, 0x343821ed, 0xf5a06e3c, ++ 0x43fc98d4, 0x87e18aef, 0x1dfb8bb0, 0xc0facdf6, 0xeb7f7284, 0xf44dbcbf, ++ 0x50aed0d8, 0x7f6b111e, 0xfa1b74db, 0xeb4f8209, 0x89bcbed1, 0xa1ec0a9b, ++ 0x3c26de17, 0xe5c9d4dd, 0x1ee74372, 0x947b62c3, 0xecce0b4e, 0xd674805b, ++ 0xb86661d0, 0x3bfa021f, 0xd2d1f384, 0x948f84a9, 0x09f089bb, 0x83f889f2, ++ 0x5fa44d05, 0x80551f61, 0xb72909fe, 0x2c3f0acf, 0x1fe7f3b3, 0xe9453809, ++ 0xa5dc7027, 0xe256bb92, 0xa533828b, 0xffb82cfb, 0xdfe42af6, 0x78735577, ++ 0x76abcec6, 0xe9b96254, 0xc37a134e, 0xe19bc910, 0x7ef7ca88, 0x3fbe2ff9, ++ 0xcf0df029, 0x1b39fcc3, 0x9c837682, 0xa97f16bf, 0xe3ef2e6e, 0x3c6f59d0, ++ 0x01ed26fd, 0x7dbf3749, 0x23d2a0dc, 0x044cba5f, 0x065d2fc7, 0x4aa1f7ea, ++ 0xc878c71e, 0x43d9f5c8, 0x94212d6b, 0x99cc6f27, 0x7901587c, 0x14ddb8ed, ++ 0x6ea0f2c6, 0x3fbe3d51, 0x6fc7cd98, 0xc6eee9d3, 0x3b3adb7a, 0xfabc256b, ++ 0xfd1172be, 0x1f2e3324, 0xfadc3cb9, 0xf567973c, 0xc1887b41, 0x3303eb3f, ++ 0xc23ed097, 0xbc62f565, 0x980e0599, 0xa40c736e, 0x7b73cf2b, 0xa6ef5f29, ++ 0x127fce0e, 0x894f200f, 0x483f24be, 0x19e146b8, 0xc493f152, 0x63f459c7, ++ 0xf97a7397, 0x3b41794e, 0xffb871d5, 0xee3c0536, 0xc0571e72, 0xe38ac3fc, ++ 0x8890ae3c, 0x7eae577e, 0xb063fb2b, 0xbe6456a3, 0x5be4a549, 0xf8aac7d8, ++ 0xbbc0947b, 0x6e65944b, 0xacbeff0f, 0xe572f883, 0xcfc4cdc7, 0xae5ca9f6, ++ 0xe5a84fd9, 0x28ff6331, 0xcdedcbd6, 0x64c75b1a, 0xf9a997cc, 0x7dc4e2b5, ++ 0x79b9227e, 0xbbf3c2a7, 0x7f7c7d3e, 0xb17be632, 0xc7fac1cf, 0xaf958a38, ++ 0xe5cdc6b7, 0x005db9c4, 0x66f7a270, 0xfaece5d3, 0xc2c7f52b, 0xe78414c7, ++ 0x73eb014a, 0x7dc7abbb, 0x5debfe82, 0x60c3bc83, 0xdf7767c9, 0x604f93fa, ++ 0x4e76e7de, 0xd2dba2f4, 0xfa27ead5, 0xbd5b73e9, 0xf1010fb8, 0x84fd153d, ++ 0x27f63b6b, 0x9ddf0f5f, 0x529ae67e, 0xdcf3db94, 0x3ccfef9c, 0x708d5faf, ++ 0x7fdbf759, 0xafdf01be, 0x6669290c, 0xafd7671c, 0x7e86ccbf, 0x913676ea, ++ 0x99f5a89f, 0xb7984dd7, 0xe76d0ba0, 0x720d77cf, 0x4fd3bb62, 0xe101b96e, ++ 0x4ad1dadd, 0xb93ccfef, 0x7efbea9d, 0xfdafcffb, 0xfc6ffa37, 0x776c5ec9, ++ 0x84bdf9e6, 0x8180fa97, 0xd112b3f2, 0xf67b43f5, 0x7a897972, 0x3660f91e, ++ 0xae926397, 0xfe9efd25, 0x62e31ded, 0xde7c86f5, 0x6d38fc26, 0x9c8f5c49, ++ 0xb2bbfc15, 0xcf39c78a, 0x9b3adefe, 0x48a607f6, 0xeb97ee11, 0xac5d398b, ++ 0xefa8f010, 0x68d8cbb8, 0x9fa9efa7, 0xb1ef8077, 0x89f4051c, 0x6ad0a479, ++ 0x179457e7, 0x19e12cf4, 0x3f458dda, 0x7f79accf, 0xb63e7051, 0x4ae366e2, ++ 0xfc33e79a, 0xf63aac3d, 0xf8aac57d, 0x6ef5f5fe, 0x380bb0bb, 0xd677641f, ++ 0x0e4878e6, 0x62c3bd98, 0xbaece1ec, 0x87c62b40, 0xf0155c6f, 0x2f8f01ea, ++ 0x793a3a9f, 0x3b7fd430, 0xf8431942, 0xcf5c2bd7, 0x4e34ed05, 0x81bffa03, ++ 0xf8297e8f, 0x0cc9dd24, 0xe01c91d7, 0x031aac7e, 0x3fc9d833, 0xa27247d5, ++ 0xc1e84da1, 0x6dbfc29d, 0xd5bbcbe9, 0xafd9df41, 0xc36f898b, 0xd53b7677, ++ 0x887ef2fb, 0x83539179, 0x78ef49b3, 0x33df344c, 0xe0b01e52, 0xa2a3f9e8, ++ 0x17f5a6fc, 0x75a9bca1, 0xf95a3da0, 0x2d1ddbb4, 0x0b491fa5, 0xfbc48fa7, ++ 0x951f748c, 0xf3d7d76c, 0xfc0a3407, 0x9644a43f, 0x25fb1c51, 0xbc6ec71e, ++ 0x2b145221, 0xe6ecfe57, 0x820bb7fb, 0xc4bc2e6e, 0x4ea0e5e9, 0x83fbfb47, ++ 0x6f6e463b, 0x37ea0655, 0xf84fcea5, 0x717c046a, 0x51d577bb, 0xea1a93b4, ++ 0xadf91798, 0x33d053b1, 0x9f08add8, 0x25daaec6, 0xd760dfd8, 0x8353f234, ++ 0x3079315d, 0x59eb1bd4, 0xf64bf239, 0x212f55e3, 0xdf17595e, 0x81d76767, ++ 0x77788a3d, 0x05f57835, 0xddb8b7a8, 0x0a88e37a, 0x5ca1fefa, 0x82a7c50f, ++ 0xf5d68c35, 0xa8bfda10, 0x7246b2af, 0x9eb037fb, 0x49e626ec, 0x0b277f22, ++ 0xf6c6ee18, 0x8c79c18d, 0x7cb431f2, 0x764292f8, 0x16c8637c, 0x37f7c2b2, ++ 0xa5fb7175, 0xe1f38bb1, 0x591f0979, 0x90167b1a, 0x3305fd1f, 0x31f8c60b, ++ 0x0a6978df, 0x9a2f93d7, 0x6d9e4f49, 0x868fb1f1, 0xa3d33ba1, 0xdcaea78a, ++ 0xf1e3a05d, 0x38cd5be6, 0x1e62c58f, 0xf72e46ed, 0x2f1c8453, 0x71e7ccdc, ++ 0x79f3d05e, 0xdde7b7c1, 0xc1bfb526, 0xc37f2419, 0xfe1e3179, 0x9e85d279, ++ 0x961ba182, 0xebce8984, 0x5cfef377, 0x3dc95f66, 0xed207431, 0xd93d2d1b, ++ 0x576115d3, 0x1850501e, 0x433e3f64, 0xd637a7c5, 0xac1370b1, 0x75c7c6f3, ++ 0xc9a389e1, 0xe49db9ee, 0x8b135af1, 0x4ce26797, 0x26a2fae7, 0xfe825fcd, ++ 0x76599ae8, 0xb81fac6f, 0xb3a7c926, 0x2a561da2, 0x32fecffd, 0x4a9cf78c, ++ 0x6f117877, 0xb89ee919, 0xfdc0d2f6, 0x6ee3b733, 0xc68e0f6e, 0x6d6843fd, ++ 0x478a6cd2, 0xff227682, 0xc7be13b4, 0xeb8ef7fd, 0xeffbe49f, 0x0e979a56, ++ 0xafcc5f18, 0xeebefd0c, 0xae2aff42, 0x78de1c5f, 0x2dd679eb, 0x2505e4ed, ++ 0x9c6bcfb8, 0xd87e2769, 0x88b28afa, 0x32281bd3, 0xe700bbe4, 0xf1fc060f, ++ 0x91e88794, 0x66c6a0ec, 0x3d3e287f, 0x04697e72, 0x64ed08bb, 0x7dca3d2d, ++ 0x589bca39, 0xa7f2543b, 0xfb947fe4, 0x74930fe8, 0xebfff92b, 0x2305f9f2, ++ 0xb00bc3e7, 0x7ef3a47e, 0xd3997efa, 0xc0b5a6f7, 0x137ef087, 0x8c6b61f0, ++ 0x5beed6dc, 0x50e4c83c, 0x0b693cf7, 0x5e523f61, 0x35fdb836, 0x1ddf38e9, ++ 0xabaa526f, 0x2f8d6f94, 0x9cba2c6f, 0xf03164dd, 0xafc02cfe, 0xb183f4b1, ++ 0x95294755, 0xb6f39441, 0x17fdf1d5, 0xbfdba477, 0xc0dcde5b, 0xd23b927c, ++ 0x49f303dd, 0xa06751d2, 0x0b61d89e, 0xfd2b7da1, 0xdcf9da40, 0xfdc8ae98, ++ 0xda57cd0c, 0xc03f18ff, 0x8ba5f7f6, 0xb7688b7d, 0xcc65f05e, 0xc1f882be, ++ 0x85fc0ba3, 0xe813bcf2, 0xf7ddf913, 0xe39297e5, 0xa5a6bd48, 0xc0ff191f, ++ 0x2716d4f5, 0x57bed76e, 0xf434afec, 0xef212bfc, 0x703780aa, 0xf0c6eddd, ++ 0xef1f895f, 0x03ca3072, 0x1a5f3208, 0x1b5ed1c6, 0x4468f9ce, 0xdf7e115f, ++ 0x81381197, 0xaafd2574, 0x4be31cf8, 0x71dc452b, 0x28632ee5, 0x7d45fcf6, ++ 0x7a71a306, 0x1ea0961d, 0x199744f8, 0x1f7e15f8, 0x30de62ac, 0x5a9f99ea, ++ 0x06041e29, 0x9bca396a, 0x46491626, 0x094c1f38, 0xd5fa236c, 0xdfa114f7, ++ 0x1912bcf0, 0xb61fcf8d, 0xdf4f7df1, 0x70d0fa9b, 0x4b45e798, 0x3798e7e4, ++ 0xa1557170, 0xbcfd0837, 0x2f7bf2ff, 0x7dbd07bc, 0xc17982f0, 0xafc62c63, ++ 0x0dfbd161, 0x0bef7e31, 0x7411ce09, 0x12683a08, 0x60665071, 0x37be4fb4, ++ 0xe8c7cb83, 0x071e18f9, 0xf6a75f7d, 0x2532c98f, 0xceafcb83, 0xd24ce704, ++ 0x74bd3833, 0xd6fce10e, 0x38a15db7, 0xb5eadd5c, 0xfe07a1ff, 0x08e55baf, ++ 0xd1af0953, 0x0673aace, 0x28d1bac3, 0x5cfe4037, 0x699de043, 0x37ea88a9, ++ 0x8f186768, 0x5274113c, 0xd0916a5c, 0xdebb8b4f, 0x93ca3bf8, 0x8cb3033a, ++ 0x5ff3c52f, 0xe18343fe, 0x25f6a7d5, 0x97de28c9, 0x749ee8fd, 0xf3193fd4, ++ 0x969e45da, 0xb3750f3c, 0x879c9bfe, 0xff8669fa, 0xde6be218, 0x9bb7ee20, ++ 0x47970f77, 0xa116fdb2, 0xf1f4b49f, 0x9c3c0241, 0x88daa8c8, 0x9a737f7c, ++ 0xe72c03ff, 0x255e73dd, 0x91282eb7, 0xf4863cdf, 0xfbc39773, 0x2f2eef14, ++ 0x7fe56f36, 0xbf1878e4, 0x96f7bc01, 0x2ead14f4, 0xcbed3a40, 0x4efd177b, ++ 0xd22766dd, 0xe38c4acb, 0xa245d0c4, 0xf8e24e38, 0xf484c78d, 0x214978d1, ++ 0xfdd4587a, 0x778471c6, 0x744221a3, 0x2762c8b2, 0x325e363c, 0x336a7a70, ++ 0xefc88b9e, 0xd24bf701, 0x7e277f7c, 0x14f8d9f8, 0xbf01038a, 0xa342f870, ++ 0x27157398, 0xc32c0232, 0x077ff44d, 0x5a2e8fee, 0xbf30833c, 0x4fd4c9ac, ++ 0x8c4b7e0f, 0x1c72c3bd, 0x7ee83a6a, 0x8960e893, 0xbd426025, 0x4cd7d4bd, ++ 0x0de691e7, 0x8b3b970a, 0x5e3ef163, 0xafc8d5ff, 0x858ff78f, 0xc4df78fc, ++ 0xd20639f3, 0xf7339739, 0xd9768866, 0xcfde5f9c, 0x61cf7563, 0xf0943579, ++ 0x4443fbdd, 0x8bd454bd, 0x5e74bb44, 0xf9c1991f, 0xbcd1fdf2, 0x299c769d, ++ 0x644edf82, 0x4e110af8, 0x84d85df0, 0x359af1f4, 0x196a7644, 0x679437c8, ++ 0x9d92e777, 0x646c720a, 0x138d3946, 0x6676a14e, 0x19ac23d2, 0xb3e01ce4, ++ 0xf043dcb7, 0xf40954d9, 0x55e6f282, 0x246bc533, 0xb55e257e, 0xe6289cf8, ++ 0x95c63df9, 0x0f946627, 0x36332b8c, 0xf445f094, 0x465ce712, 0xee7d7c22, ++ 0x7e0078e0, 0x7a41969d, 0x962a3c2e, 0x3808566f, 0x7ef6b94a, 0xc7af1a92, ++ 0x219b9e85, 0xda31faf0, 0xb78fd875, 0xfdeff88f, 0x55dede54, 0xb48ef5c8, ++ 0x790917bb, 0x57c84277, 0xa23d4a59, 0x109f73f5, 0x3d227bfc, 0x0175e259, ++ 0x1fea55e2, 0x3c613390, 0x75ef39df, 0xb619c933, 0x5df28fbe, 0x5c62dda0, ++ 0xdf733cd7, 0x1bd03482, 0xc67b043f, 0x7ddf4a54, 0xc064728c, 0xd258bbfe, ++ 0x5ea18385, 0xeb10c86e, 0x71e3eb29, 0x5d7c11a9, 0x0fc8188b, 0x47f8cae5, ++ 0xc8167f1f, 0xf798dde1, 0xcc39fb80, 0x76254ab7, 0x007f60f6, 0xee19d5f7, ++ 0xe3b5dc28, 0xb074109d, 0xd031432e, 0x56129479, 0xf05b7882, 0xf98e67f6, ++ 0x7179e5d0, 0x0e67d31e, 0xce7ec06c, 0xb24de4fd, 0xc2984fc3, 0x38f6ed45, ++ 0x6de14def, 0xf7d12b0f, 0xa7ad3c77, 0x3d9d74f3, 0x1669fee7, 0x8f517bac, ++ 0x2e438bde, 0x23d7f35a, 0xdd1da2d7, 0x0a78a463, 0x06cdf3e8, 0xb733779c, ++ 0xd4e84f1b, 0x5ef67074, 0xa766bef5, 0xee7907a0, 0x139dca53, 0x9cba3e22, ++ 0x49bcb979, 0xf581de4a, 0xf3baef0f, 0x2d538c66, 0x3e43fe61, 0xbbe9fb80, ++ 0x7bfd91a7, 0xbe500b27, 0xf536e2cd, 0xeda5ce39, 0x8f9dfaea, 0x49e7380c, ++ 0x48797872, 0x8df85cfb, 0xe3c7e3ab, 0xe5d04dfe, 0xbb889359, 0x8dc735af, ++ 0xf826bfbb, 0xef1f1a3a, 0x5fddc753, 0xbddc7cbd, 0x8f771349, 0xb8da11da, ++ 0x2df7ef3b, 0xbf606f61, 0xb3f7f1b1, 0xf1d7f155, 0xd3475886, 0xaf2a9b25, ++ 0x7601ade2, 0x6fbd324b, 0x304d64ba, 0x3f3d3b1f, 0x38fe2cbb, 0x471fec7f, ++ 0x7e8fe71d, 0x72fbe3cf, 0xa4e92cff, 0xe91652e9, 0xf6975959, 0x1cbbf46f, ++ 0x0f3daf7a, 0x92cffd2d, 0x98523e2f, 0x45fc8b25, 0xdd3ec45b, 0x1f93794b, ++ 0x7c845da1, 0x5af3c539, 0xf8b8a604, 0x864571be, 0xd1be5121, 0xebe803ae, ++ 0x1e46244c, 0xb870cd9f, 0x997aff48, 0x09cbce97, 0x93f05fba, 0xf3773a1a, ++ 0x19d535e7, 0x418973ea, 0xf1320fee, 0x189d20fd, 0x4cb7d18d, 0x77178fa3, ++ 0x264dfe81, 0x01ce8bfb, 0x4feaf27d, 0x632f0f48, 0xf7a474fe, 0xe78757de, ++ 0x1e83be05, 0x35b9f396, 0xf3c8d0b8, 0x3f645d4e, 0xb9f310cc, 0x1a0dfbb5, ++ 0x19f1675f, 0xf31f1c69, 0x0b69d338, 0x420be7cd, 0x09f500d4, 0xe747f3fd, ++ 0xc5e3631a, 0x6e6e95fc, 0x25104e47, 0xc4c8145b, 0x5c719b79, 0x84afa63d, ++ 0x1d6cb132, 0x3960f5e7, 0xf81bf151, 0x279e383c, 0x6c1ce6b3, 0xf444b3af, ++ 0x83309d7c, 0x256a3a74, 0x877545e1, 0x799fafa8, 0x7c52c171, 0x3c90776e, ++ 0x14798931, 0xc45c8267, 0x05985b75, 0x87b66dd7, 0x4b7c534f, 0x0f2ac194, ++ 0x087071f1, 0x12473f23, 0xae3860eb, 0x883e7edd, 0xa732758b, 0xf3ab7582, ++ 0x863ef862, 0x379f92f2, 0xcde97906, 0x539e7984, 0xe21975fe, 0xf733e405, ++ 0x6f7a24fb, 0x0b73f308, 0x8aa5de42, 0x790ab5f9, 0x8abcc597, 0xf24f2738, ++ 0x658e17ee, 0xc5ddce74, 0xde517bfc, 0x953c9a3d, 0x2c1972e2, 0x9b49f340, ++ 0x2dc9506a, 0xcf5d5fb7, 0xcad06d98, 0x97e7053b, 0xb73f5015, 0x4f9413b0, ++ 0x99fd84a4, 0x3ed1a55f, 0x5bfa046b, 0x79f12566, 0x90fc8519, 0x3c4959f5, ++ 0xa676656f, 0xc3e5bbee, 0xf6fbd579, 0x3e7e54c6, 0xc5ba42fc, 0x6009f982, ++ 0xe4ceccc7, 0x820ff8fb, 0x59579a2c, 0x16b3d132, 0xd43661f3, 0x8075de2a, ++ 0xe70e0def, 0xabf47adc, 0x7f71b7ce, 0x6ad3c18e, 0x97dbf787, 0xbcf178a5, ++ 0xc3c89371, 0xae7560de, 0x9e788ddc, 0x58ede0ef, 0x2b8c06df, 0x74e4df6e, ++ 0xaba79e62, 0x09b26fba, 0x994b55f7, 0x438b0773, 0x1f039fef, 0xc49f7cc1, ++ 0x1149e03a, 0xef9f23f4, 0xbc85e7c4, 0xf702b13e, 0xb0affca5, 0xe712a53b, ++ 0x142a66cb, 0xdeea6937, 0x5a3f4613, 0xf212ece1, 0xfc2bbfa3, 0xfff04c41, ++ 0xc13c72b5, 0xe947d75f, 0x8897de9d, 0xfd7d8f7a, 0x43943b41, 0xd77f85bb, ++ 0xd7711665, 0xc9c13e18, 0x8541e13b, 0xfd881a38, 0x787f38b8, 0x7ce3fc99, ++ 0xfe8b1d7b, 0xd1d538e1, 0x4d4e4971, 0x35aeef12, 0x3f22f784, 0x12ca2f5f, ++ 0xcf9c1e51, 0x3a3dc6e3, 0xe3a4c7bb, 0xc4296dfc, 0x8f5fb7ad, 0x6e70a970, ++ 0x4cf9c56c, 0xe654c250, 0x51e8b7f9, 0x405a971c, 0x8c7f202e, 0x79d0d5f5, ++ 0xce8c49e6, 0x9496da83, 0xfcf09d78, 0x73ff05dd, 0x63d1fd08, 0x19c519da, ++ 0x5e649966, 0xcf106f86, 0xfcd0f3db, 0xcd8d056b, 0xbd395d9c, 0x3d12ec8c, ++ 0x5d57ee13, 0x9cfffbec, 0xf2e83d54, 0xbf9d577a, 0x5af224d7, 0xa654fd64, ++ 0x0ffee89d, 0xc99f9399, 0xe3c27d24, 0x85327b96, 0x8d8235fd, 0x23133940, ++ 0x76c05e07, 0x4adf2ae7, 0xefd42724, 0xcdb89c85, 0xf648c637, 0x521790bb, ++ 0xfe45fb2e, 0x33e61cce, 0xc47b5c22, 0x2b471a7d, 0x98bc9397, 0xfcf402c5, ++ 0x1f1c554f, 0xec464840, 0x6aa9d6ef, 0xbf36e73b, 0xb66b3eba, 0x70e20ed6, ++ 0x09cee393, 0x90cfdfa8, 0xb554ecf6, 0xc7ef3b3d, 0x3e90a79f, 0xc34df8ce, ++ 0xbcd1f957, 0x5e4d269c, 0xcbc8a34e, 0x785aea69, 0x2f263bbf, 0xf283f807, ++ 0xaebb1a72, 0xedc39794, 0xa18d779e, 0x78bf18bd, 0x14ac3977, 0xe45fb9e6, ++ 0x3cc01c71, 0x5d28d28e, 0x3f70163a, 0xf29c4029, 0x369c7273, 0xa6d0b73a, ++ 0x6abf252b, 0xe543b25b, 0x96b4deff, 0xa7f4a3d3, 0x599c3cca, 0xc1dcd666, ++ 0x780774fd, 0xa3f719be, 0xe25f8485, 0xfa454c99, 0x1f93d701, 0xdc0f234f, ++ 0x746edc69, 0xfe411dcf, 0x25ddd9d2, 0x64979465, 0xff1f9077, 0x7d0f4c99, ++ 0x42503b3f, 0xed1bbe7e, 0xd2ce2873, 0xb0ddbdd4, 0x9ba51ec4, 0xd9bd24af, ++ 0xade90d98, 0x9cf63fdf, 0x3e63fc99, 0x059f5fb3, 0x0a6f5574, 0x862c1f93, ++ 0x2279e8de, 0xc0a774bd, 0x3fcab1b7, 0xa5c02967, 0xee8988f7, 0x9bc301bf, ++ 0xbfcf68fc, 0x3dfe4294, 0xfa460cc3, 0x23257d60, 0x3fa2f67c, 0x69ffe60a, ++ 0xe9d91d4a, 0xe9196beb, 0xfca90bb1, 0x2ce5971e, 0xfe87c874, 0x8e81c7aa, ++ 0x8ac3f462, 0x3d7aea9d, 0x5f3920eb, 0x3d007bbf, 0xf2935c92, 0xf47981af, ++ 0x752f8c46, 0x4367bfaa, 0x44adf2d5, 0xb731e9c8, 0x3cc56a4d, 0x2e3a3180, ++ 0xef12d88f, 0x2fb419e0, 0x693ce79e, 0x1bf95145, 0x53f672e5, 0x9e94e3af, ++ 0xc3972ff3, 0xad7fa2e5, 0x7617289e, 0xe6060dd3, 0xb4a47dc3, 0xd53da083, ++ 0xf5bae80f, 0x3ce53aa8, 0xd277c4cb, 0x587292fe, 0x2c72abe2, 0xb3a04688, ++ 0x8ec259a9, 0x2086c219, 0xa27fa1be, 0x32370573, 0x107fd4a9, 0x8bd75ff7, ++ 0x821e80f1, 0x9d415748, 0xbbf48425, 0xfd266941, 0x1b3b4164, 0x804a4dca, ++ 0xd4bff0e4, 0x1f48f505, 0xadf358e3, 0xf1bb4337, 0xca1b1e96, 0x9b93a01d, ++ 0xf4a3cab3, 0x79c2cad3, 0x1d15147b, 0x2973fbd1, 0x23a5c56f, 0x7fc22fa9, ++ 0x4dc376e2, 0x183bec0c, 0xdceff7d7, 0xf0a039be, 0x79d81cfd, 0x79bed007, ++ 0xe88d374b, 0xf7de1a64, 0x9c6aed03, 0xe95ffc6a, 0x5a861f5e, 0x21d102b9, ++ 0xe03219e1, 0xfdf7b47c, 0x62dca4f8, 0xc055b96a, 0xd579e73e, 0x08fd0f1b, ++ 0xd5b6f9f7, 0xf501846c, 0x0ef24b08, 0xba6f138b, 0xddfecb37, 0x71819fec, ++ 0xcab37b8b, 0x7a2dc607, 0x70bf7c8d, 0xdb2c8b1d, 0xb7a40cad, 0xeb57070b, ++ 0x52e86333, 0x46cbc7f2, 0xbca03f9e, 0x6344e3ce, 0x8c38ac2d, 0x7ee32970, ++ 0xd71fc93e, 0x46a69d21, 0x3c42afe9, 0xc84b387f, 0x8f967c97, 0xcba136f4, ++ 0x7e03d61a, 0xd77f444a, 0x4695fd21, 0xdf6901ed, 0x401d8eb7, 0x1f980567, ++ 0x16f16a5d, 0x7b495d22, 0xd1d28c60, 0x9f9ce78a, 0xad67e97f, 0xba18df38, ++ 0x4ae88c7a, 0xff22ba01, 0xa97d00d5, 0x3ba1af7e, 0x5663ff89, 0x592b27ae, ++ 0x662bed33, 0x193d7126, 0xf493bdae, 0xa24b8824, 0x706637bb, 0x3e61abba, ++ 0xa64abba2, 0x8b6a97a6, 0x4ba5aeba, 0xa6a75118, 0x9dd100bb, 0xd1135e96, ++ 0x9dd23e5d, 0x576997d4, 0x5983bba6, 0xecbc7bdf, 0x789c5660, 0x2d3ba499, ++ 0xb67949bd, 0xb6aceac7, 0xea9b3cc3, 0x630fd214, 0xc56d0c8e, 0x0286f0fa, ++ 0xa4f76bb2, 0xfbd3f778, 0xacbefe66, 0xfcc7a7c7, 0xe255c291, 0x1abf817d, ++ 0x15ab4deb, 0xfcad7fba, 0x192fcf18, 0x2fbf86ba, 0x1fbcd759, 0x0537efcf, ++ 0x9f2ff7f9, 0x81e740de, 0xf7c41b42, 0x58d5ed95, 0xdfe36a6f, 0xa2f18a7f, ++ 0x2bcf306b, 0xafcf8ad4, 0xe5e05cda, 0x476e5cdb, 0xddeb144f, 0x9fb73ca3, ++ 0xdfe76bbe, 0x92c879dd, 0xe6fec8c4, 0x620df076, 0xe71f139d, 0x747d74eb, ++ 0xd00f54e3, 0x20bed2c7, 0x752763d9, 0xef2415f5, 0x2b67ec12, 0x2c1cf695, ++ 0x3e65bde5, 0x3f4db78b, 0x7713c784, 0x364a10c0, 0x38c90bf7, 0x6bfbc61c, ++ 0x251cec63, 0x6531fb9b, 0x4654f4bb, 0xafd8b7e7, 0x9697e41c, 0xc3f0c271, ++ 0xc4fe414c, 0x8977e235, 0x0a5386e2, 0x988ec99b, 0x85e32f92, 0x1822c311, ++ 0xcfabe4b7, 0xd7f3c726, 0xa7b8c458, 0x7c82fe44, 0x79e2175e, 0x48907b12, ++ 0xedacfce8, 0x9853d508, 0x9ed79cea, 0xcf4f5e02, 0x5b63ff36, 0xd757c00e, ++ 0x92a2086c, 0xff2853cb, 0x161e96e3, 0x703c941e, 0x2c0c53fe, 0x207ca26c, ++ 0xad65ff3e, 0x075f7126, 0x09b76b97, 0xc3f1b1fc, 0x0a677e88, 0x0b66153c, ++ 0x8d863539, 0x9b753941, 0x2d0fdbc0, 0xafae46cd, 0xf91a8ddb, 0xed1b3c31, ++ 0xda13479f, 0x1af7eae3, 0xc62752f9, 0xf0ec265d, 0xfc8face5, 0x1d852794, ++ 0x6e51ea7e, 0x1d60af87, 0xfdeca7e4, 0x1b3fb715, 0x2f487960, 0xcae37f5a, ++ 0x437aea5d, 0x08deba87, 0x6ffb1dea, 0x9dc8d2ea, 0xedffee62, 0x02a1b47d, ++ 0x8f757dfd, 0x733f211c, 0x2133949d, 0x03019cb5, 0x8799cb9b, 0xd13f26af, ++ 0xbb1f96b7, 0xa154f761, 0x05bcb3ca, 0x47efd5e1, 0x8be79179, 0x5fbe3234, ++ 0x6eac75ef, 0xf144f7a8, 0xf493f528, 0x4be56827, 0xf22f9089, 0x253794bd, ++ 0xd829eb8c, 0x61f11e5f, 0xb79d8d5b, 0xffbd5b32, 0x690a7e92, 0x7da0951f, ++ 0x7575f484, 0xfd05be7c, 0x487996f4, 0x539a7e8c, 0xebfc2166, 0x7602a3ed, ++ 0x65347d15, 0xa73f7e5f, 0x1fa1af7e, 0x5dba9fb9, 0x18adcfd0, 0xfff180f1, ++ 0x96e3ee5d, 0xc999fa73, 0x7e9107fc, 0xd382b4fe, 0x7dd7dc8f, 0x4f9c7df3, ++ 0x938fbb1f, 0xbbafc1fb, 0x1ba7eb9f, 0xbee86feb, 0xfd7959cb, 0x3ed0bbf7, ++ 0x74e149ba, 0x4fe0b0d1, 0x4a9ef0db, 0xb68e2f29, 0x18c1af30, 0x334eb7ad, ++ 0x28ee305b, 0x719b7bef, 0x8b15fbd3, 0x79cfe462, 0x8456e547, 0x9376eb1b, ++ 0x26c1b51f, 0x9c7cdbfd, 0x7b9eba59, 0xb83943df, 0xdbf146cd, 0x9919878b, ++ 0x1f1f172c, 0x67d1794e, 0xce5b9c45, 0xbb43cee7, 0x7cc08b5e, 0x3b9ead96, ++ 0xdcf600c6, 0xb7f4254a, 0xfbf41417, 0x46cc9e05, 0x16174dbb, 0x50f62bf7, ++ 0x9b8e401c, 0x241a7fd8, 0xc7da68b9, 0x929f73f5, 0xf0ae7944, 0x1e3628bc, ++ 0xee60ecf6, 0x3d7e9317, 0x28ff47a9, 0xdce2adea, 0xed55ab57, 0xfa65d0c7, ++ 0x7ffd713a, 0x82baf854, 0xde491b6f, 0xe31f1fa3, 0xd9b5a0b6, 0xf381d4e0, ++ 0x9d853cc2, 0x614f235f, 0x5feb90af, 0xf986eca0, 0xedf74f4d, 0x894ef1c3, ++ 0x1129ec38, 0xcc953bb7, 0xfa4778e3, 0xcff2f3db, 0x38882f52, 0x7554a9df, ++ 0xfbb6477c, 0xffdf364b, 0xf162dc7e, 0x7c6237af, 0x83d7f99c, 0x6c3cf11e, ++ 0x8ffca66e, 0xbd7d7c79, 0xcea8a52f, 0xaecb9fd3, 0xf2f102fc, 0x0effdb80, ++ 0xbb496bce, 0xaf505cfa, 0x57b4afb8, 0x95af4fd0, 0x73dc7297, 0xe05fb5d9, ++ 0xf873bd77, 0xf5fd99bd, 0xa7eeb271, 0x44277bfe, 0xd7f52e48, 0xe711147f, ++ 0x43bfb9b5, 0xc513e3fa, 0x39f1b4eb, 0x6d4c79ed, 0xe4be7d7c, 0x9f5f113b, ++ 0xfcd5e427, 0x5fdfee6e, 0x061b6160, 0xba3bfbc3, 0x5b5e2833, 0x522c1c97, ++ 0xb683d7c5, 0x2157946f, 0xb737b4e9, 0xfd1e3fa7, 0x747898ab, 0x36478883, ++ 0xaa75f5c8, 0xf83297d7, 0xa7478f7b, 0x8f138e0c, 0xbc2fe6d6, 0x3186f688, ++ 0x9dbb878a, 0xfa356e1c, 0xcbf46afa, 0x28c25c5e, 0x37eefbef, 0xdfa2b717, ++ 0xe28deef6, 0x7f614c56, 0x27380837, 0xafdb975a, 0x7f951e63, 0x6279893c, ++ 0x481593d6, 0xa2c9d555, 0x1cdbc98f, 0xfaad975c, 0x8879b73e, 0xeafe7daa, ++ 0x0bef55ab, 0x7aaaa582, 0xaa75db61, 0xabdac3f6, 0x8fe1f554, 0x5f6aa8dc, ++ 0x220c86c2, 0x3d61d9bf, 0x55d896fa, 0xf7aa19a1, 0xaedd7723, 0xd653fefa, ++ 0x6878d0fc, 0xdf5569d7, 0xbe82cbb3, 0xee0ae29e, 0x8c75c1be, 0xeaa458ea, ++ 0xb0958587, 0x6fbd1152, 0x3f326ceb, 0x87a4b25f, 0xe9ae1fc7, 0x671aa15a, ++ 0xf09ebea5, 0x96af8da8, 0x9443beb2, 0xbc521c47, 0xde303661, 0x3b6bbcba, ++ 0xfb25777d, 0x30fe3fa7, 0xc93ae1d8, 0xe6cab8ef, 0x0ba5ad74, 0x1789d93b, ++ 0x1f93d71f, 0x3d1584b1, 0x65e09e3c, 0x40cf2164, 0xdc645dfc, 0xb771763f, ++ 0xeebef283, 0xcd31737c, 0xa6a99cc7, 0x4d47ab0b, 0x6a11b617, 0xd57870ba, ++ 0xac683074, 0xf0b40e9a, 0xe9a9f14e, 0x3fe04582, 0xda778197, 0xfcdd3554, ++ 0x55b9c16f, 0x0731df03, 0x8276ad7c, 0x9313cf1b, 0xd8599a76, 0x81b8da43, ++ 0x397e77b4, 0xa25dd858, 0xd80f191f, 0xff6904a0, 0x1be71fdf, 0xfbc3ce1b, ++ 0xcd2d4b49, 0xfc97fb8c, 0xef8e0f0f, 0x89e7a49f, 0xae1293fc, 0xb87d8533, ++ 0x7e49f992, 0xbf72b31f, 0xcbb5c7d2, 0x8cb4afc9, 0x7dfd9335, 0xe114c676, ++ 0xbb520c7f, 0x0c05e52b, 0xfb0007c8, 0x6ff8c594, 0xe055e057, 0xa9e10385, ++ 0x07612b74, 0xdd65a39e, 0x28041f52, 0xd0c8045f, 0xaf8aa152, 0x6860eca8, ++ 0x2fcac4a0, 0xf1cb0f69, 0x5ca53c24, 0x5998e393, 0xf9133eb3, 0xd8e72342, ++ 0x477c6d08, 0x7e91d7ed, 0x91371921, 0x1fad2271, 0x81bfea27, 0x25c62bfd, ++ 0xf15a0bf3, 0xa718ebdc, 0xe585fc8f, 0x3e2e67ac, 0x68e96b1f, 0x1f847835, ++ 0xefd62ae3, 0xafa848c7, 0xbe4710ae, 0x1e44a835, 0x3f18182b, 0x5868f196, ++ 0xc1ef47fe, 0x4f15e3c7, 0xc663ce2e, 0x48ddc3cb, 0x9bfd034f, 0x40afe3de, ++ 0x5f5d7a3f, 0xc1abb61a, 0xf898ef44, 0x844a1bf2, 0xe643f3d6, 0x1cf63fbb, ++ 0x98eb237b, 0xcafc973c, 0xbef127a0, 0xf7ee4e98, 0xbb5a5d62, 0x677e40d8, ++ 0xe904ac1d, 0x898b257e, 0xdf4416ab, 0xb03f5d53, 0xae7ef32e, 0xe4b44f64, ++ 0x02de4538, 0x426257cf, 0x687dca0e, 0xcc9efda2, 0x5cf7907f, 0x631f3cca, ++ 0x8f23f08e, 0x7fb1a366, 0x0e6b37e0, 0x3f8019f9, 0xec7e5895, 0xf7a20bcf, ++ 0xb351f803, 0xa0ff997e, 0xff919477, 0x7aec7168, 0xa43c06bf, 0x0e4b72dd, ++ 0x3423f2a3, 0x486ed08a, 0x0f8ef13a, 0xa8f5975f, 0x4c9b35f2, 0xbf41b1b0, ++ 0x0f228bc2, 0xbf6d43af, 0xf911ce8f, 0x73ff6245, 0xc6257825, 0x139bc887, ++ 0x76baf8f8, 0x939bcc98, 0x11cb2c70, 0xf70a3272, 0xf37139b1, 0xaee1fa07, ++ 0x2ee02f7e, 0xbcbe72e1, 0x2f8837e7, 0x3a58e3bd, 0x34e6fbc2, 0x9f6c04ff, ++ 0x52723c7b, 0x55e745d1, 0x79473fa3, 0xf4bb17af, 0x71ae1e74, 0x8d839702, ++ 0x3449e92f, 0xd336e85c, 0x5d75493d, 0x3c2ec9fb, 0x168202d7, 0x1699c464, ++ 0x65d87218, 0x781a09fc, 0xc92fda27, 0xa1a6dcf5, 0x0367993b, 0xa2a39ceb, ++ 0x987081af, 0x6afe8f13, 0xf083c5f4, 0x7e7f743c, 0x2f2fa190, 0xed3adef6, ++ 0xdc39dc3a, 0xf56196af, 0xfd38422f, 0x21e727a5, 0xdf46afec, 0xe11b287d, ++ 0xf3a14ab3, 0xfccd1352, 0x26566a7c, 0x3636bf3f, 0xf3c5ecd2, 0xfc3999bd, ++ 0x3fe1af5e, 0x22b4e5fa, 0x8ca5bba4, 0xafeff9e2, 0xef1527ba, 0x0ce390bb, ++ 0xae747457, 0x3ee7b192, 0xc61969f8, 0x1e51e72b, 0xb8b37cc2, 0x5b5ee7cf, ++ 0xc9e410b8, 0x3f7e26eb, 0x33487193, 0x4be9479d, 0xd39f93d1, 0x909367a5, ++ 0xe5fce4fe, 0x1cf95439, 0x3e63c9cf, 0xb13e7caf, 0xddcc6fb5, 0xe39f5e50, ++ 0x31e3dd51, 0x4c6fbab1, 0x078a3db3, 0x88d75799, 0x9e82b8f7, 0xfe9160bd, ++ 0xae3df517, 0xf4fec427, 0x7bfeb0c4, 0xf1b11c5d, 0x6fab46f2, 0x7eb8b5d0, ++ 0x7feb8f71, 0x52837d3a, 0x7beabd68, 0x3c882f59, 0x12fbf976, 0xd981ee89, ++ 0x2f7ca396, 0xca24e6f7, 0xf4f996b7, 0x14c8fa5a, 0xc531a1f2, 0xd0d70cc0, ++ 0xe5ff6ef9, 0xa5f2bdda, 0xacb9ee3e, 0xfaae82c3, 0x357ca5ef, 0xebe03e7e, ++ 0xc07cda39, 0xedcf9d08, 0xa97c07cf, 0x6df7b2f2, 0x9bfde234, 0xf9907031, ++ 0xff788de2, 0xfd3898e6, 0xfb1e7f42, 0xc9e1ef95, 0xf5fbe1cc, 0x4bcfcc46, ++ 0xe5ce7d8b, 0x971c744c, 0x248bb7c8, 0xaefe7f23, 0xd7e74f4b, 0x3758777f, ++ 0x799c4775, 0xbb70179f, 0x63f06dda, 0x30c8c4fe, 0x513a4fbf, 0x460e793b, ++ 0xced5079e, 0xb22ab3af, 0xf98fe700, 0x8bc6f1bf, 0x79caf808, 0x7c72a677, ++ 0xe666be34, 0x781a84f7, 0x6a67769e, 0x0bc91964, 0x97cf1aa7, 0xf3a6df84, ++ 0x9d1e48c6, 0xfdc69acb, 0xc1e8890b, 0xa170169b, 0xbaf7911c, 0x159a1855, ++ 0x5dbf0c67, 0x70a21e89, 0x3af0abd7, 0x7a26ee10, 0x7d3dfb2f, 0xe9edf394, ++ 0xe54f9ca3, 0x23f4e83e, 0x00afca7a, 0x7ee3b686, 0x77d0a16e, 0xa38f19a7, ++ 0x68576e9c, 0xc028b3df, 0x3b906ad8, 0xe4ae770b, 0x6353f276, 0xc2aaa036, ++ 0x1ebbf8e7, 0xbb19330b, 0xeb45ca01, 0xb1757135, 0x747a929f, 0xfdb566c9, ++ 0xff36c75b, 0x4b49da07, 0x97e93359, 0xdfd55b65, 0xe9bcedd7, 0x1b4f1c53, ++ 0x315f47ff, 0x2b9677dd, 0xac1523f6, 0xddc3f502, 0xc2667d4f, 0xc448cc9f, ++ 0xde40a70f, 0x72861d0e, 0xb9e542d7, 0x57952716, 0x7372fae5, 0x73637e01, ++ 0x7b2c1e03, 0xbaf0e6df, 0xeb917f58, 0x0c3c3c0f, 0xe7accb7a, 0xb9e65379, ++ 0x33fe3e3c, 0xe00097bc, 0x7b733662, 0xcd683f49, 0x96685b8c, 0xb5c7c221, ++ 0x1482e711, 0x4cde4fd2, 0x33d77fa4, 0xfc22a653, 0x7cd8cfdd, 0x954daeb8, ++ 0x4bf412be, 0xe7e5aa6c, 0x1e662d28, 0x6efd0f9f, 0xb9743edc, 0x52d8ed0d, ++ 0x9c68e785, 0xa8c37bdd, 0xff74dbc2, 0x6d4d7941, 0xc3bcf037, 0xef645d74, ++ 0x78e882e0, 0x13285b6e, 0x91eef7e3, 0x97187efc, 0xcb84b2be, 0x35ff6e73, ++ 0x2af7d80a, 0xfcf1079e, 0x904df07c, 0x45efd0c7, 0x71e73f03, 0x9678e335, ++ 0x763869f9, 0x0e7b9dac, 0xfbfb17e0, 0x28775703, 0xdd326361, 0x9e714213, ++ 0xf4e175fa, 0x9e97a8b9, 0x4c9c5036, 0x7af5cbce, 0xc3c61556, 0xab9a3ea4, ++ 0x4cffb938, 0x9873f1d8, 0xb4f1e3fc, 0xe65e82d9, 0xae7dfb08, 0x1179c38d, ++ 0x77e1e6f3, 0xb2585bb7, 0x6e6a580e, 0xad394775, 0x0531a56f, 0x171904ed, ++ 0xc45f6c4a, 0xfe357bf7, 0x05cfc1c6, 0xd8457d2b, 0x29f419c9, 0x1b0f865d, ++ 0x161f0573, 0x6c71f3f1, 0x1c61f328, 0xe1b5f1b2, 0xe6393bf4, 0x06e71e24, ++ 0x7bc164f9, 0xdea20e72, 0x7f2f7586, 0x47efcac5, 0x3a26f791, 0x4da87df9, ++ 0xe94a7233, 0x3ef1debc, 0x82e2dfba, 0x7c479231, 0x6f07720c, 0xe27b6d02, ++ 0x780c5bd5, 0xec1b32ae, 0xf8bfa834, 0x3ebc5bc4, 0xef0cb224, 0x13f3fc43, ++ 0xd5faf09f, 0x3f589391, 0x2ddf44fd, 0x6378ff78, 0x1e996469, 0x5f6d86ea, ++ 0xa1b8f7f2, 0xd94ac204, 0x441e9c66, 0xd84523fb, 0x9d08de41, 0x797c6e87, ++ 0xbfd62eb8, 0x972e45fa, 0xbcac675b, 0x760299dd, 0xf7840cc7, 0xffedf888, ++ 0x9d53ab92, 0x95eb966b, 0xf8ccb3df, 0xc62c3ddf, 0x31ce2e59, 0x36b1b44f, ++ 0x05eb8f2b, 0x070f0193, 0x5c5387ba, 0x54dcbef2, 0xdd08b701, 0xd1fb2343, ++ 0x1c813efe, 0x7fc28577, 0x9182e8cf, 0xfbe581fb, 0x307f029d, 0x671a7ace, ++ 0xff9f8fa8, 0x8253919d, 0x19bc03f8, 0x7c0cde04, 0xd69dbbdf, 0xefe2fd85, ++ 0x181e80f3, 0x03fcfe83, 0x82fb439f, 0x74b5bce8, 0xeb9727b2, 0x3cade597, ++ 0x5297db1e, 0xd134f448, 0x2933ee26, 0x90c3af53, 0x45f0e1c7, 0x63870a6e, ++ 0x14325e3f, 0xc055a71a, 0x34522731, 0x5f37d463, 0x9f317ef7, 0x31dd7bef, ++ 0xbde1f2f8, 0xf8ba0724, 0xbc86bdbd, 0x013f7e54, 0xd92a73d0, 0xfd545b7b, ++ 0xf9ab599d, 0x7ba32c7e, 0x0b531b73, 0x899ffbe9, 0x7de5497b, 0xc15df86d, ++ 0xa2a76e68, 0x8bef2afd, 0x581bc160, 0xffb17c6c, 0x710e885e, 0x3aff6e6f, ++ 0xeb132e6f, 0x3a758a74, 0xa1077f63, 0xf58f3f9f, 0xb98ccde5, 0xef3e4faf, ++ 0x7f7f7f87, 0x3fa2a5c5, 0xebc79f15, 0x113af90f, 0x7df6fe5e, 0x53ce45e3, ++ 0x387ecf03, 0xe127e66b, 0xdf4dfc89, 0x52e9ab15, 0xae74f3ce, 0xf86b1fdc, ++ 0x8e5be0bb, 0x6d4dee27, 0xb7cf09f8, 0x5d351e66, 0xe8167437, 0x7e40ef30, ++ 0x68cdc0e7, 0x97efd479, 0x87f62795, 0x41272c39, 0x5e6e633e, 0x217f5c79, ++ 0x0feed73d, 0xefe4537b, 0x14fda98d, 0x8f6f6ebd, 0xe76be30f, 0xebfff9f9, ++ 0x8c1b7e35, 0x8f673d2f, 0x2fd5177e, 0xc14afaea, 0x4efd03df, 0xbf38797d, ++ 0xf3d57332, 0x0dd82f1e, 0x474f06db, 0xa8365d79, 0x3dfc1eea, 0x797909a9, ++ 0x979e51d3, 0xacfaae0d, 0xc4f9e400, 0x1f5e7cbc, 0x10d9f559, 0xe7cb6fac, ++ 0x9efa27ed, 0x82cf7947, 0x6527d3f9, 0x5f09ed45, 0xd5c6879e, 0xdee8eb57, ++ 0xe63b7eb6, 0x31d93375, 0xca89ae12, 0x39aeb332, 0x5a707c5e, 0x84bfbf5e, ++ 0xf16371f6, 0xeff41e9f, 0xc47ffd89, 0xf7ffdaa0, 0xd9f3f326, 0x17feafbd, ++ 0x99994f9d, 0x0f25b817, 0x76c9b8e8, 0xd401416e, 0xa03ed9d7, 0x03e29df8, ++ 0x2afd043b, 0x079b271e, 0x6dce55f3, 0xc4dda3f2, 0x062d7856, 0x77f0ab82, ++ 0x00719de1, 0x7b5e57bf, 0x7cc1befa, 0x63ce3f18, 0x4d03909c, 0x6ffdfdaf, ++ 0x3a6dff18, 0x99a2f763, 0xd1fbae38, 0x1aeed07b, 0xdfd6fdd7, 0xe7e61eb9, ++ 0xc7bce469, 0x9e133fa1, 0xd332ed8f, 0x5f75c7fc, 0x5fdb14b5, 0x85dd6fff, ++ 0x4e132748, 0x2c515b84, 0x2ffabef4, 0x68e75583, 0xcd97a7d8, 0x6f184d03, ++ 0xc4f8f093, 0x097bbf44, 0xba4668f0, 0x4e7db26c, 0xdc176a79, 0xc8443747, ++ 0x579f573e, 0xe29dfb02, 0x925917c9, 0xf218e317, 0x4fd6bbdc, 0xd616bc7a, ++ 0xf427cf07, 0xec620cc1, 0x2c9789e7, 0xf5a24820, 0xaaa2964a, 0x54b25b57, ++ 0x059c6bed, 0x3253f7aa, 0x9fbd52af, 0xd55129e6, 0x4e311a6f, 0xde07fed5, ++ 0xfa7d554a, 0xf6aa69d8, 0x555abeb5, 0xa1dc24bd, 0x70e63f6a, 0x31fdfa97, ++ 0x943c47a6, 0xc7eef71e, 0x1f63fcb2, 0x4e2b5bb9, 0x72c7ef35, 0x70727fdc, ++ 0xd7c4fd68, 0x8fd8ea5d, 0x589fa5cf, 0xfa48fe7b, 0xede9678d, 0xff7c5321, ++ 0x30a1a670, 0x5e804f7a, 0x1d1fcfc7, 0x16fc094c, 0x3f9e58e9, 0x627e889a, ++ 0x1dcd4240, 0x01bdf9e7, 0xed1fb8f3, 0xe5062238, 0xf9071cd3, 0x9b1b8f1f, ++ 0xcf1eff7f, 0xb945c807, 0xb66fa137, 0x2f13dd6a, 0xaeeb5405, 0x7835cb64, ++ 0xaf554bba, 0xd544fe71, 0x5ae64a7e, 0x9e69fbd5, 0x6d3c1a8d, 0xe07fd551, ++ 0xa783547d, 0x3d3c1aed, 0xe92f7aad, 0xb1f85bbb, 0x13ff435e, 0x3d23e394, ++ 0x1b8788d5, 0x3e11f54e, 0x57b4f6c6, 0x3bae9e23, 0x2af841de, 0x51abfb0b, ++ 0x6e1c565c, 0x18658fde, 0xddf861f6, 0x2a4c96be, 0xc878b40f, 0x65a8758f, ++ 0x5b879504, 0xfffcf4bc, 0xf2a58cb4, 0x547c5b5f, 0x2a65a1fe, 0x7e2d3d95, ++ 0x3a5a3b2a, 0x2d73fda8, 0x960fdc5d, 0x452f7fd6, 0x2e07fa2e, 0x188d22e8, ++ 0x5b7f7e01, 0x0bcbc933, 0x580b9149, 0x489ac75f, 0x9f39fe5e, 0xbdc33c91, ++ 0xf2c5f916, 0xa8f98d7d, 0x5d78f227, 0xe87465e6, 0x8768257c, 0xf35bca5f, ++ 0xb19721a0, 0x33fad7fb, 0x8ebc299d, 0xc843cbbf, 0x35b77ca6, 0x1872fa0f, ++ 0x12aa3dfb, 0x99ace60a, 0xf15ef58e, 0xf2e78b7b, 0xda0f4cd6, 0xdcdc43bf, ++ 0x7e6e2037, 0x1b50e909, 0x29fdff37, 0x3afd038f, 0xee1f3f47, 0x151c7840, ++ 0x2b1f2dfe, 0x4befe231, 0x8c4a1a54, 0x6b8f67a8, 0x8e5912ec, 0xf92a5731, ++ 0xf7b75c6e, 0xbf0fca36, 0x2fbf48d1, 0xfbe14337, 0x83eed95e, 0x7a0fae7c, ++ 0xfda6607f, 0x6f9d31d4, 0xaf47f229, 0xe10db7d2, 0x276fc9ec, 0xfa3af7b8, ++ 0x797e10f2, 0xbaf20ff9, 0xe29b6fbb, 0x391ba98d, 0x3ff99c7c, 0x93e1beff, ++ 0xc2d4f883, 0xc9df20a7, 0x97d858f5, 0xac80768b, 0x35f5ab1f, 0xd2b09c50, ++ 0x71d70c37, 0xfce66fd4, 0x868477eb, 0x57c87f91, 0x9f8c5b7e, 0x237c89e7, ++ 0x0f13377d, 0xf3bfa212, 0xde287d76, 0x92bdf0ef, 0x441ff7cf, 0x9ccfb827, ++ 0xc17da363, 0x87bf1d31, 0xdffedb40, 0xeabef9f3, 0x7efb826c, 0xaf7013df, ++ 0xf7e1b5ba, 0xbd7f402f, 0x75d4acab, 0xd9387faf, 0x00cdbd63, 0xdee9a05d, ++ 0xf9e7cd53, 0x8057b37b, 0x73b6e284, 0xfef05ff1, 0xfcf7ddf7, 0xfed08ff5, ++ 0x2f365583, 0xd5e710e9, 0x45dbbf04, 0x1669f9e3, 0xcfe69fb2, 0xbd42adc8, ++ 0xffc45738, 0xe90c3816, 0xa4340614, 0xcfd09c98, 0x06c97b12, 0xe65b2080, ++ 0x4fe135aa, 0xdce5d4af, 0x15cb01b5, 0xf098b743, 0x8bea4127, 0x33406cf7, ++ 0xb85801b6, 0xe45fe49c, 0xebcc0b48, 0x0f7ad58e, 0xf3c9cfdf, 0x51bf2ba9, ++ 0xdfa48b1e, 0x08df2263, 0xd5fb4080, 0xca8af913, 0xc0427dcf, 0x88be6173, ++ 0xa3628caf, 0xafc752be, 0x9fbd2296, 0x28a47f9b, 0xfd417c41, 0xef8fd85e, ++ 0xb58c7b88, 0x71c88ff7, 0x3f7817df, 0x44ca0266, 0xae76f27b, 0xfecf4607, ++ 0xac395d6c, 0x53b7747f, 0x770a7947, 0x7880bc34, 0xf025d8b8, 0xc85d6468, ++ 0x1706b74f, 0x5eb9407e, 0x57b7739a, 0x1ede97d2, 0xbeac7567, 0xabf88b2c, ++ 0xd8e5f563, 0xd46af6be, 0x863f528b, 0x3c84ea5b, 0x7a39266e, 0xd53565a0, ++ 0xa904b50f, 0x26d2dc3c, 0xbd3b71e4, 0x4796d7ff, 0x090e3c84, 0x9e8bbc79, ++ 0xa6ccb777, 0x0096b5f2, 0x05a73795, 0xc9ff2336, 0x4b4cecb8, 0x0f6df280, ++ 0x18666a3e, 0x6dd8bb97, 0xe00cbca6, 0xb98f6d88, 0x4cc8ef30, 0xf9b52ce7, ++ 0xdf395a47, 0x039d0f4f, 0x04793dee, 0x379fd4f1, 0x7e62f684, 0xca3a7a62, ++ 0x4b940e3c, 0x463ebf1d, 0x8f51f5f6, 0xf4f681c7, 0x923ffc9e, 0xf3ea3a5c, ++ 0x7f508c38, 0xe47fd7ee, 0x871e03ef, 0xe7cfea19, 0x41ebc3bf, 0xf50ac38f, ++ 0x7a8b5fce, 0xff105188, 0x47bf5fa5, 0xa64a96fe, 0xa8fe401c, 0x024c14b6, ++ 0xbafa0175, 0xc5f200f2, 0x9385cc94, 0xf28a2f90, 0xd397443d, 0x600f6b3c, ++ 0xdb11a6fd, 0x83c5780d, 0x1eb25ecf, 0xd572abbf, 0x49bbf01a, 0xc7ad7739, ++ 0xdd0f26ef, 0x6efd8862, 0xf59ef16a, 0xbbd9bf58, 0x69f680dd, 0x7731ca11, ++ 0x97591fb4, 0x969ca5ef, 0x74d771f9, 0x8c1f49fb, 0x3e93f2ee, 0x9aa97090, ++ 0xc63f7b59, 0x14ba9ab3, 0x4adefe27, 0x3fa54cd5, 0x0c730139, 0x501ef11b, ++ 0xf387d790, 0x0b5a0ccf, 0xfd6135df, 0xb83faa3a, 0xdf95fbf6, 0xe8e3f2c7, ++ 0xbf0577b7, 0xbcc7bea3, 0xfc4d77f8, 0x089196fe, 0xbba7b417, 0xbee83a17, ++ 0xa0701652, 0xf422559d, 0xd096397c, 0xae5152df, 0xb318e510, 0xe71c03ef, ++ 0xe1f2c493, 0xf305d934, 0x9bce688f, 0xe42f7824, 0x67a959c3, 0x0d1c3dc4, ++ 0xa0fc9dac, 0xd3afca57, 0xf36b91e6, 0xb8de644d, 0x9ea4bf36, 0x07fef0f5, ++ 0x3cf387e4, 0xe1f901eb, 0xc4955f72, 0x946ce9e5, 0xfff74035, 0x20d9c80f, ++ 0x008000d8, 0x00000000, 0x00088b1f, 0x00000000, 0x3bd5ff00, 0xd554740b, ++ 0x9dcefbb5, 0x9924c85f, 0x10827c24, 0xc947f9bc, 0x03108067, 0x04243209, ++ 0x20271115, 0x067cac4f, 0x027e7f94, 0xd7628daf, 0xa02ac60c, 0x2d6ac6be, ++ 0xa81beab4, 0xc95a5da8, 0x0958d443, 0x5822aa1d, 0x010553aa, 0x1101d29b, ++ 0x08cf91e1, 0xfac5a556, 0xdee7def6, 0x0249dccc, 0x5eb5d548, 0xdce76158, ++ 0xbdffdff3, 0x456639cf, 0x05cf1e32, 0xffc87c80, 0xb0e8065a, 0x0486bd5b, ++ 0xddc5a700, 0xd000194f, 0x0b4ffb3e, 0xe0f580c1, 0x9fe5702f, 0xf588dea7, ++ 0x60ad0871, 0xc5806284, 0x580145d4, 0xe0333e02, 0xa67c4bb8, 0xf02b41a3, ++ 0xbbf8d7cf, 0x4ccfb6cc, 0xab3d96fd, 0x1c6e0eff, 0x35403074, 0x0190cd04, ++ 0x551cd350, 0xad33210f, 0xfa25aea3, 0x68c0137b, 0x1868475a, 0xcbebe3ad, ++ 0x2c15439d, 0x038dce57, 0xe9c03fb9, 0x259f16ed, 0xb93ffb8d, 0xdb35cb1f, ++ 0x0a75f62d, 0x4a0eb7c1, 0x36ad0805, 0xbb708cbf, 0x4d182667, 0x6e3c3b00, ++ 0x62cf7e86, 0xfc016630, 0xe5cf53c1, 0x5c0d3c37, 0x32f1e5de, 0xc359eddc, ++ 0x134f6df0, 0xacf5efd7, 0x1e3bf2e7, 0xe780c31f, 0xf37efe59, 0x6e619adc, ++ 0xcdbf4e1b, 0x55cc1ed4, 0x700e9dd7, 0x0473b27b, 0x7f7bd1e1, 0xe1f1e259, ++ 0xfaff7bc0, 0x43972c72, 0x27adbd6e, 0xd6d932ec, 0xf65c0948, 0xde1f719a, ++ 0x46be311d, 0x886057dc, 0xdbf68cbb, 0xdcfa1e55, 0xfe86f880, 0x8dc3c641, ++ 0x69e3dd03, 0x438cc97c, 0xdeacd127, 0x09dfc26c, 0xb005f783, 0x65f14c03, ++ 0x67388cbb, 0x5d563c67, 0x65815006, 0x03c01e6f, 0xd4955c03, 0x6683720f, ++ 0x8cfd27c6, 0x9825f1c7, 0x40ebccd9, 0x62baed88, 0x9141bc04, 0x213dff18, ++ 0x74e3818e, 0x0f9806a5, 0x1d9e36ba, 0xc4f5e4a6, 0xfa5e347b, 0x5ca547c2, ++ 0x2116f416, 0x1d624b3d, 0x976eac16, 0x448d2fc0, 0x39606138, 0xa9ed38e0, ++ 0x71c12366, 0x6d056421, 0xff1dfc3c, 0x04663225, 0x44804cbf, 0x3ac2b95d, ++ 0xd2bed758, 0x6faba69e, 0xf1e6cd4f, 0x42b949af, 0x707daed7, 0x3bcc5589, ++ 0x2d825ae9, 0x79faf766, 0x18d09748, 0xd613638b, 0x5f131bbf, 0x53008500, ++ 0x1137e363, 0x9866377c, 0x3d4dda8f, 0xe03fae7a, 0xfecaa73e, 0xaa880581, ++ 0xfa1194eb, 0x2accf771, 0xf5ddb057, 0xebf463b9, 0xed226090, 0x04c706f7, ++ 0x4b1bf7dd, 0x77f5d3ae, 0x84490359, 0x95672ad6, 0xc3757bee, 0x064c60e7, ++ 0x07386d28, 0x230051c6, 0x71bacdfc, 0xd16eed46, 0x0fb11fb5, 0x91eb1264, ++ 0x13af1d07, 0x29cc7d1c, 0x9f14ab13, 0xe09d7fa8, 0xc302cf98, 0x04e01f68, ++ 0xf9103ec5, 0xf07b954c, 0xf2c4604a, 0x125cb538, 0x102635f2, 0xae41ce1d, ++ 0x0a57e911, 0x36321cfd, 0x78fe4a96, 0x9c60f896, 0x3990010a, 0x58995fb0, ++ 0xd831cc02, 0x5274e67c, 0xa8df282b, 0x8e49d60f, 0x59c22314, 0xca98b072, ++ 0x202c109d, 0x465c1b28, 0x5049afe2, 0x16ca943f, 0x7c10a770, 0xdffdd133, ++ 0x521dc7c4, 0x2e2c51b0, 0x5cfc4c94, 0x39a1d779, 0xc42f58ab, 0xbeb82c38, ++ 0x347cb6df, 0xb7fad680, 0xbf9f80c0, 0xbdf984a6, 0xe339fece, 0x37572b49, ++ 0x69fc619c, 0x30d5f6e5, 0x6e4b85d7, 0x2adcc132, 0x92ffd584, 0x48d956e7, ++ 0xa21ac17f, 0xc1fc3553, 0xdc2f3cbc, 0xed3f9a1e, 0xea2177c6, 0xd35a2abf, ++ 0xe9bd2a58, 0x2abb6272, 0x80439093, 0x8e5c55c9, 0xcddecb51, 0x5b8e272e, ++ 0xef6d4035, 0xa9f5154d, 0x5130fd5a, 0xbbc6d2ce, 0xac1fb44b, 0xaef1d595, ++ 0x51ffcad0, 0xda69f5c5, 0x1ca20d7c, 0xf0dfea27, 0x3d22ad8d, 0xb7fbe9a0, ++ 0x02313b35, 0x409d9046, 0xe90efffd, 0xef69769b, 0x4f7fa642, 0x57afa0fb, ++ 0xdfdcc3ed, 0x21735ec8, 0xd8baffe1, 0x371c913f, 0x5c72404b, 0xe9c9b77d, ++ 0x254ff9c3, 0xb0ac1735, 0xea75f185, 0xaebf0287, 0x8ca7388a, 0xce5e6bed, ++ 0x237c44d9, 0x381bedc7, 0x347fbf1f, 0xa67ac0c4, 0x8139b652, 0xd0a0f9e8, ++ 0x68ff5af3, 0x35e1b0b8, 0xd47afd1d, 0x07cf12cb, 0xe717f133, 0xd06878eb, ++ 0xa38475c6, 0xe13640cc, 0x1af49da6, 0xea2060d2, 0x7dfc12d2, 0x15aaf513, ++ 0x033fdce9, 0xdf6c069c, 0xc7d415ff, 0x0163d344, 0x5f0bbfd6, 0x284bf189, ++ 0x5e1b3528, 0x5f377b67, 0xfc46a946, 0x9f71cead, 0xc674fc26, 0x4f89b205, ++ 0xe0ec3617, 0x659e5d75, 0x1ec1f1e7, 0xe7c48bca, 0xffe27a3f, 0xffc0175f, ++ 0xfc4fbebf, 0x494704e3, 0xc8501b7f, 0x6d4b7d68, 0x977ef06f, 0x9f59dfaa, ++ 0x71db85a4, 0xee59ee59, 0x230c738c, 0x3a54387c, 0xc528351d, 0xd252be2a, ++ 0x058e9e70, 0x2c44ec81, 0x8181fc3b, 0x7b07b66e, 0xf7444b47, 0xba2038fa, ++ 0x82814a77, 0xbfd0bd03, 0x76ccd3d9, 0x85a7ab78, 0x0e708fe1, 0xaf86b3c2, ++ 0xf81eb4ec, 0xc06d32bd, 0xafabf179, 0x3bf18eff, 0x3b3418c8, 0x41ed5fb0, ++ 0x038a71e0, 0xa110cd47, 0x09a72657, 0x22d09b7b, 0x9ca57d71, 0xd5d41097, ++ 0x653a09c7, 0x9f10473a, 0x5bdb4cd6, 0xcb0a4eb6, 0x6858f8c3, 0xbe62498e, ++ 0xed7ca876, 0xf8d6be20, 0x9471f917, 0xc6fcf111, 0x0bd7ec39, 0x0bfcc37e, ++ 0xa7868f3c, 0x9d789eaa, 0xbe7e7691, 0xc77fd7d5, 0x0fd6dd78, 0xfd7b2107, ++ 0x536f8c52, 0x373c4f5a, 0xd77909a4, 0x02f6bdf0, 0x1dfb5e78, 0x9a6d79e1, ++ 0xe346e3c2, 0x147b2fbb, 0xdd6d1f4d, 0xe8e9c8bd, 0xc1d3914b, 0x329eaa19, ++ 0xdf999fa2, 0x444dee93, 0xee8eab77, 0x9e405e8f, 0xe53efd1e, 0xd16f1a29, ++ 0x57025ab0, 0xf7e7adb3, 0xb10669ad, 0x8f08efef, 0x753342e3, 0x2ff8d8fe, ++ 0x6c7f3add, 0x7a544602, 0x5d0ef5bf, 0xa77ed2b9, 0x2935fdae, 0xd7f575ab, ++ 0xf5756b29, 0xac3ee7d7, 0xd8e0df2b, 0x6e57e510, 0x3957d5d4, 0x9faba37f, ++ 0x5753bf5d, 0x8f61b73f, 0xf79e7eae, 0x86b2bacf, 0xe01eedc7, 0xc78768f8, ++ 0xd74bc6aa, 0x060b2c32, 0xae0c482a, 0xff62113e, 0x54d024b2, 0xc1c92ec1, ++ 0x8b3ff666, 0x0a0aaefc, 0xd7778aa3, 0xefd04ebf, 0x59f1abb1, 0x3c37c30a, ++ 0x5df7eb0a, 0xbb865c9e, 0x3e350e3d, 0xd7b8612b, 0x32e354e3, 0xbb68c317, ++ 0x6dc33ab0, 0x4c7a474b, 0x0191717d, 0xfe370170, 0x03bcabee, 0xc3a0f8b4, ++ 0x0aed7140, 0xca672f75, 0x0abc38be, 0xbd4cebf9, 0xb6e541c5, 0x4a4d279d, ++ 0x997e4f7e, 0xce0ca5fd, 0xdd9b3e08, 0xf91367f0, 0xe591b359, 0xd3917b9b, ++ 0x5fc174c4, 0xea007ee4, 0x30569985, 0x307d47f5, 0x68e4a673, 0x85eefe04, ++ 0x377e8624, 0x82354fd6, 0x2ae582df, 0x896fd19b, 0xacb9a5e7, 0x10cf3fe8, ++ 0x118b04cb, 0xfd0f54bc, 0xbf2e3993, 0x282a3e89, 0xae194e0f, 0xc833efc6, ++ 0x3f7ec6ef, 0xc89b35b0, 0xfbb2deee, 0x58558e9e, 0x477af70f, 0x130f3c73, ++ 0x25bfa4ed, 0xaf8687ef, 0x2f2df787, 0x1e384d48, 0x2489d7c1, 0x4a8f14c3, ++ 0xe293808e, 0x8e4c3bd4, 0x7ecf4acd, 0x7909a71f, 0xec4b2a9c, 0xb55e85bf, ++ 0x614936f8, 0xedfdc4f9, 0xeb3ee0b6, 0x9f680788, 0x4e7f26f5, 0x3bd5f901, ++ 0x2baeafd9, 0x74405d59, 0x1d289baa, 0xe38414b1, 0xcf86ba9b, 0xd68f6fd8, ++ 0x42f0d1cf, 0x60238ff1, 0xec3bfe67, 0xa2fccdd9, 0x1e6d41c5, 0x828b973f, ++ 0x78c88aae, 0x07f8d668, 0xc6738a64, 0x9de2267c, 0x03ce73d2, 0x83bee157, ++ 0x95bfc09e, 0x08f2d04f, 0x3a215e5a, 0x91e9a14f, 0x26567739, 0x57bf71b8, ++ 0xbe85dba7, 0x65484eb7, 0xd4051a3a, 0xf4c4edf4, 0xdaf9fa1e, 0x65dbf3f4, ++ 0xac77fd7d, 0xff962f9f, 0x5d8453ab, 0x83fbe68d, 0xd1319ed3, 0x8efe353a, ++ 0xd459ffe6, 0x559fe707, 0xa8bcf927, 0x6a2e67a7, 0x974a9532, 0x6d4befce, ++ 0x1c1c44c7, 0xb1be176d, 0x8e98503d, 0xf1cc8572, 0xc3be4585, 0x8d0f7941, ++ 0xd27aab0e, 0x7e7e93cd, 0xffafaabb, 0x6380e3de, 0x2ecd2e73, 0xf89fce82, ++ 0x3f7dcf65, 0x3f7d8179, 0xfbee7df9, 0xc30a21a3, 0x736d7e9a, 0x17a88364, ++ 0x0c0d89f1, 0x3e5dbfc8, 0xc5d2e399, 0x14f14d69, 0x284940cf, 0x92ddf49e, ++ 0x3fc81956, 0x38d3a304, 0x9173f918, 0xe0ed9fca, 0xb1f880ff, 0x94fc1e16, ++ 0xca8b2e12, 0x3d214d16, 0x5371f8b7, 0xbffc4f18, 0xb525f393, 0xb6a5bf6a, ++ 0xefda666d, 0xedf4a7d2, 0x9faa71b4, 0x6b4de7d7, 0x04f9aecb, 0x38046ed8, ++ 0x4dbb57cf, 0x7a576fdf, 0xc3ce7f5c, 0x8491848d, 0xd3e90bf7, 0xa6ebb24e, ++ 0x0f39f288, 0x49de17e7, 0x3bd8786f, 0x7d9f4c34, 0xf079e93d, 0xe0e7fa02, ++ 0xa27fa9f7, 0x7b8e58f9, 0xfcf44cca, 0x9bfc7ca6, 0xad07672c, 0xddcfd35b, ++ 0x0b35e77a, 0xd1ae9deb, 0xde8bc88a, 0x78c6dbf1, 0xe0b393e2, 0xaf987620, ++ 0x6be747e6, 0xfa35d1f9, 0x76f8e8fc, 0xc6e1e73f, 0xc635f31d, 0xdb4bdd21, ++ 0x1ba79cbc, 0x68ddcfb3, 0x7b55f2c3, 0x47f9329d, 0xc970de23, 0xbfcd6eb4, ++ 0xb09dfcd1, 0x7d64cb1e, 0x8cd679c7, 0x9a77d78b, 0x61ecd45d, 0x092c1db4, ++ 0xfd905535, 0xf365fb1b, 0xadbf04eb, 0xddb47a3c, 0x2393473b, 0xfe4d3b5e, ++ 0xcfc807d1, 0xb1c63578, 0x3fae7a19, 0x75d04333, 0x899e77ba, 0x0f848fe5, ++ 0x2a9a6de5, 0xdd925337, 0xce381999, 0x185ed574, 0xd9134eac, 0xfdb94ad1, ++ 0x5f1337e7, 0x13ce6405, 0xfbf1fcae, 0xb94afc2f, 0xcea17e70, 0x8ffd867e, ++ 0x3a8ce2be, 0xbe29b803, 0x8ca15918, 0xe2863f22, 0x6a1bca36, 0xf6e8c479, ++ 0x8bcab28b, 0x72957d69, 0xeb49c059, 0xd3d62f59, 0x1aeabd17, 0x2de5d53e, ++ 0xaebf9afb, 0x7e7db475, 0x28fc7c84, 0xb44e3ba3, 0xe986b71f, 0xf17cb17d, ++ 0x997e2dff, 0x4257832a, 0xf92f9b3b, 0xc20bff84, 0x01059e0f, 0xc4207386, ++ 0x3e760dd0, 0x0e0f9a8f, 0x8b83b786, 0xf74c99e1, 0x73f20cb2, 0xc481a14d, ++ 0xff2f1d57, 0xa6f88f33, 0xa6d2eae3, 0x9dedf031, 0x7ffb4527, 0x9e14235d, ++ 0x7fa5ebbf, 0xecfe27ee, 0xa2e9b1fa, 0xc9edc6f4, 0x51f10f4e, 0x3bcaf9f4, ++ 0xc73e6413, 0x961ac701, 0xe8bb2a8b, 0x70071303, 0xa4868f9b, 0xf5859cb1, ++ 0x9a8da0e6, 0xfd879cde, 0x58188ff2, 0xc912c1af, 0x5b4d8597, 0xb1160682, ++ 0x3e6905fc, 0x44dbca99, 0xa24d7e7d, 0xfe72c24f, 0x7f511898, 0xd20fa247, ++ 0xb20a1e28, 0x6005ce5c, 0x840f387d, 0x9c0dbc5e, 0x0c8c4fbc, 0xbfec25d2, ++ 0x2475bb60, 0x982163e7, 0x80bffa49, 0xe25ea8e2, 0xf2a8bff4, 0xf42e985e, ++ 0x3eb9617d, 0x4331b22f, 0xacf659c4, 0x7e88aff2, 0x26e74c96, 0x81498582, ++ 0x51148f75, 0x9b00c83e, 0x193ebe50, 0x6f9f2773, 0xcaaefd6a, 0xda867f2a, ++ 0xe380916d, 0xc5ab6f15, 0x2b9c59b7, 0x273c8c0e, 0xf159933b, 0x36f3c25b, ++ 0x17d8cf35, 0xc71fb15e, 0xcae53dfd, 0x290afdcb, 0x3cfce376, 0x79e1287e, ++ 0x4666fcb9, 0x79bdd55b, 0x25e0867c, 0x2caaf93f, 0xaf9a0ef7, 0xa3600cd0, ++ 0xe2213ff5, 0x61fa8028, 0xf45d1f94, 0x7e40c5a4, 0xc73421c6, 0xc1f88390, ++ 0x5fe09bb8, 0xf8267e31, 0x099f8c37, 0x99f8c11e, 0x3f1847e0, 0xe5f05c13, ++ 0x908a0c08, 0x03ce990e, 0x79c5cf82, 0x037af45f, 0xe7bb3e2a, 0xfcf3356f, ++ 0xe3372cf6, 0xafde9bb7, 0x61ce8f82, 0x2e8624b6, 0xbf0f3a4b, 0xc17eb575, ++ 0xe17da5e7, 0x8c873b45, 0xd2a5dfae, 0x919b60bd, 0x4b417fed, 0x44617e30, ++ 0xcc338fbb, 0xd2ff9f5c, 0xbf1a78b1, 0x5f8dded3, 0x9e5b84a7, 0x8fe5106a, ++ 0xdd574e33, 0x3bf5a36b, 0xa2bc22bf, 0x7da49f9c, 0xffbcb414, 0x1e22d2b3, ++ 0xb4292edf, 0x1c63d08e, 0x23ed4437, 0xbeda0f1a, 0xd60624b6, 0x2f2dff51, ++ 0x504ed3a5, 0x1b9080ef, 0xb7a923e2, 0xf5e6aefd, 0x150968de, 0x373d71d9, ++ 0xf7d72d7e, 0xd67b7f86, 0x7af3c604, 0x3eee6fd5, 0x4bf9570f, 0xcaa5dba3, ++ 0x4078f477, 0x9dfa11ae, 0x2a9749cb, 0xc5ce9764, 0xe7c85f93, 0xde486359, ++ 0x7da5df33, 0x90cb777a, 0xeb1f30a5, 0x2991cfe4, 0xf98345f8, 0xd11766ad, ++ 0xf1eb4b6b, 0x4c6ddbcc, 0xd805cc9f, 0xd2ccc95e, 0xc7f33de5, 0x23e5fd9c, ++ 0x9dbdb9fd, 0x3605baa6, 0xfc71da56, 0xdf3bad5b, 0xb6cd2da4, 0xc44ca91f, ++ 0x6914dcf2, 0x4a79c117, 0x8524a4da, 0x71e3eb96, 0xb09dcb6e, 0x8a6a448b, ++ 0xb9fd8aa3, 0x2264a409, 0x358543ec, 0xbb1b0e96, 0x64f695cb, 0x949af95d, ++ 0xd7f6ba21, 0xfaba1929, 0xeb8773eb, 0xa779b5ea, 0xdae94638, 0xd2852615, ++ 0x7dc3ae29, 0x66c05cb0, 0xd12597d9, 0x1e4df7be, 0x4fa9e58e, 0x9b9070cf, ++ 0x9fad45b2, 0x47c2b5ba, 0x7c42e8f4, 0x3aa1d19a, 0xb1f6b251, 0xa8b06847, ++ 0xf5baa1b8, 0xca9cbbd7, 0x7d0dc425, 0x40cb0bc4, 0x15f7db9c, 0x0bc74437, ++ 0x467f3fa8, 0xe5f0b3fa, 0x388dec9b, 0x673196ee, 0x6f88532f, 0x408e3133, ++ 0x44716ad4, 0x2dd3fc5f, 0xf8229227, 0x9b0c8f67, 0x801fe17b, 0x147e547b, ++ 0xe87bea70, 0x737de4cf, 0xe931f6fd, 0x781fce37, 0x0aaebcd5, 0x857df2a3, ++ 0x2bbbc766, 0x27f53f28, 0x1f5ce819, 0xb03ae1ce, 0x2dfd217e, 0x6e1ef987, ++ 0xc193f8df, 0x97bbf9fd, 0x355ad35c, 0x532eb7ff, 0x77aaabf5, 0x517064fe, ++ 0x1e561eb8, 0xbb87b5d1, 0xe574fba5, 0xe5f4d37b, 0x17dc2707, 0xbf2fbfd9, ++ 0x79fae16c, 0xe9ca3766, 0xa72547c2, 0xd17d17af, 0xaafe9ebd, 0xc45d687e, ++ 0xcef8f6fa, 0xae256625, 0x1c5afb67, 0x0b96f28f, 0x9ab7b0fb, 0x8645ba9e, ++ 0xd7eadefa, 0xbe39f36b, 0x210ef9dd, 0x79bec9ee, 0xf876115f, 0x1cdb8250, ++ 0xcebf27c9, 0x1d37e714, 0xf1fe1e1b, 0xfb9e74e7, 0x3aaf88aa, 0x28fd8512, ++ 0xc189f6d8, 0x9fb0b080, 0x7b02afe0, 0xa97640d0, 0x17ac716b, 0x96eace50, ++ 0x850d79c4, 0x3e8447e4, 0x3cab22b0, 0x3fadd4f7, 0x7e7f22b3, 0xece83068, ++ 0x5b051772, 0xf3257e58, 0x376469d6, 0x43dc4f20, 0xf9f6b6fa, 0x7f08264a, ++ 0x8de85ca6, 0xaa7fc439, 0xab9402dd, 0xb7409fba, 0x433d231d, 0xa7f2a178, ++ 0xef79cd4f, 0xf7f3f251, 0x7941bd08, 0x2fd95b85, 0xf9f4da70, 0x73966686, ++ 0xbc895bfc, 0xfad175bf, 0xb3268de3, 0x23d45bed, 0x2fac2ffb, 0xe91ebbde, ++ 0xccaaf759, 0x6f4e80f7, 0x08804acf, 0xc78d11fd, 0xcb32f5ba, 0xdcee56b9, ++ 0x724b5f2e, 0xaac5f741, 0x1be27bf2, 0x97fe429c, 0xcb7cc5db, 0x8d317dc7, ++ 0x56f2f4ec, 0xd2e4b8a3, 0x646b3cd7, 0xd9e62250, 0x98b2c3b2, 0xfeb69aec, ++ 0x4faabb2e, 0x349eff5a, 0xd5c04f21, 0xf457d8bd, 0xc9fd4c0b, 0x3892a82f, ++ 0x3adfdd9e, 0xb4f09ca8, 0x32bf025f, 0xc9b88792, 0x2e9beb8a, 0x36efa386, ++ 0x4a428bca, 0xd1e691ae, 0x9e2d5ae2, 0x233ad19d, 0x0fd8fc8b, 0x8fdfcdb6, ++ 0x566b0394, 0xcdc5cb06, 0x7bbf65e0, 0x952ba27f, 0xd55324f2, 0x13fb0ffb, ++ 0x6fe4ed43, 0x2b171fef, 0x1c067dd1, 0x5f1a5eff, 0x937ed7db, 0xf79eb52b, ++ 0x9d4be6a5, 0xc75fca57, 0xa89c7c5e, 0xf94ad9e9, 0xd3d709ee, 0xb02cfdf9, ++ 0xa37b3c53, 0xf86afc2c, 0x4d6790bd, 0x8149d6af, 0x99e75a24, 0x659769cc, ++ 0x0d41bf61, 0x7de6a5ff, 0xfef7749b, 0xeeafd62e, 0x959fa38e, 0x1d6a7f98, ++ 0x2da8de22, 0x9bf3f53b, 0x8c5afe71, 0x9bbfc9f7, 0x20f3b2df, 0xbe3a2fe1, ++ 0xfeaf8eef, 0xcf6f7ccd, 0x9455ccf8, 0x0cf29a35, 0x0cdff667, 0xeeb4e33d, ++ 0x2ff340b8, 0xb9f2c737, 0x21562a35, 0x9ebf2a1f, 0x607d91dc, 0x7c9fd605, ++ 0xfaecc4db, 0x745fb8fa, 0x95e589de, 0xcf19639b, 0x4bc09327, 0xa6e4e476, ++ 0x1b179f1c, 0xda84322c, 0xd6c1bec8, 0xf9a73e38, 0xe79c89e4, 0xe4fca79e, ++ 0x87ec5973, 0xe828fc90, 0xf7427cc2, 0x8bfbe88d, 0xb81fb983, 0x550bbcc5, ++ 0xc99f94b9, 0xd51969ff, 0xf9cc933f, 0x277e8d09, 0x5271889e, 0xf077f6b0, ++ 0xf591d817, 0xe3de494e, 0x99714f74, 0x12c3f9e1, 0x3f6765f2, 0xeba20cf7, ++ 0xcffe5fd2, 0x9fb8a507, 0xf86e678a, 0xdf5c18c5, 0x0007f792, 0x6ba6138d, ++ 0xe9c37eef, 0xfe4219ed, 0x7b2cfc55, 0x2c77c636, 0x34d49f42, 0x75caea27, ++ 0xc77d832d, 0x32d0f422, 0x6a863810, 0xaa09cf89, 0xb38ab955, 0x7a256fb8, ++ 0x547dd0d4, 0x7fb89fa6, 0xabce923a, 0x590fff08, 0x7cd1ff18, 0xf84b22b6, ++ 0x9e5ad5b5, 0x29ac1927, 0x816eb724, 0x7287aebf, 0xf63c5136, 0xea925640, ++ 0xa7b28477, 0x67f247e5, 0x9c6bed5b, 0x7b88b1e7, 0x9fbd318e, 0x12b27beb, ++ 0x5a17ff99, 0x99e5d33f, 0xeace1b6a, 0x79b53ff2, 0xc8c07ec0, 0x1dd46546, ++ 0x74a85708, 0xbaea9599, 0xfcdef187, 0x197bcbf0, 0xf0ff8f9f, 0xb7779a43, ++ 0x7b07e98d, 0x2a2c78d5, 0xfd685ade, 0x8dbf9554, 0xfbed5ebc, 0x0a070df1, ++ 0xfc71ff28, 0x9405e1a5, 0x072f9da7, 0x8d2aff8e, 0x5e1d39ef, 0xeeeb7085, ++ 0x1e2f38f7, 0xf71edebd, 0x87a12418, 0xc91f69aa, 0xb5c7ff74, 0x5ce58b3e, ++ 0xeba387e8, 0x5a7f19f2, 0x64ebba3e, 0xb6a0f1ef, 0x6d7c6d4e, 0x5af8da7d, ++ 0x44b3a7bb, 0x0e61d8dc, 0x2ffd9014, 0x889873a6, 0x3e23a3b8, 0xa3689050, ++ 0x2ed176ef, 0xfc11cb09, 0x579eeff6, 0x754f9f45, 0xf9aacb9f, 0xd58683a8, ++ 0xfe4669ff, 0xc47e6f6b, 0xbbd48ee4, 0x4a9cf0df, 0x9f76af5b, 0x636ec3b6, ++ 0x2cade6ff, 0x0a9f1f35, 0xeb0ed4a9, 0xbff27e1d, 0xe41c5ab7, 0xae2d3bc7, ++ 0xabfe123f, 0xbfbe7ecd, 0x5a73f5a6, 0x3a3dfcdc, 0x6895df2f, 0xdca7ba06, ++ 0xff3d4035, 0x5eb03bfd, 0x2b7438a1, 0x61545bce, 0x0b6adfa8, 0x7f4d43eb, ++ 0xefc70d16, 0xd46f7479, 0x9013f618, 0xf50a8a6f, 0xd1fbc3ed, 0x0b669797, ++ 0x1b25163a, 0xbf938d7a, 0x11b2e552, 0xcf21659a, 0xaa968ec2, 0xc91dc778, ++ 0xad4d7e91, 0xe2bbe7aa, 0xd83a5ead, 0xee2edd2d, 0xfd1a96a9, 0x16a2093b, ++ 0xba248680, 0xe317e932, 0x39f5e8b5, 0x6c5990d9, 0x5db38797, 0xfb92ab1e, ++ 0xef9ea93e, 0xb5ef86b3, 0x57826406, 0x13a18843, 0x488246ec, 0xc1138606, ++ 0xd41270c5, 0x9a16bc33, 0x66864e18, 0xc0205386, 0x37f4ae10, 0xbb83db02, ++ 0x5d3feced, 0x7640c8b7, 0xdee6e8b9, 0xfb2572fd, 0x2d40f842, 0xf8e97c5f, ++ 0xc3dea498, 0x432f13ed, 0x35ef9973, 0x3f8858bc, 0xf80c5fb1, 0x838e0852, ++ 0x9e338f20, 0xe2833918, 0xf9ef8575, 0xcb938056, 0x8f891795, 0xe8dba092, ++ 0x2f05ebce, 0xc9f3bd15, 0x5e5e2a15, 0x27e606cd, 0x6cee5e8d, 0xba3417a1, ++ 0x429f7c61, 0x3d27a0f6, 0xb3ad1861, 0x8cfcb628, 0x9ae32a82, 0xd3a6cbec, ++ 0x51a2fb3d, 0x85482be5, 0x70f4f2dc, 0x7f2d2e51, 0x6fea8e91, 0xe517cecd, ++ 0x2651f2c2, 0xa93bea07, 0x2c44fa60, 0xe3fbd5bb, 0x74023456, 0x10ce4c6f, ++ 0xf56ec2e7, 0x4e45b91e, 0xc5f74d5b, 0xf580ab2c, 0x20063b8d, 0x722d7ec0, ++ 0x4f8bc91b, 0x7695e7d8, 0xb1d1bf41, 0x64d909ee, 0x78feaccf, 0x72b0e905, ++ 0xb220e575, 0xc59bf79b, 0x280647f8, 0x7c435fc3, 0x5ee22c59, 0xac5fb6ab, ++ 0x3960c6f7, 0x1a2b2928, 0xd2ebc2d2, 0xf31171d6, 0xef37ceba, 0x33dd4397, ++ 0x2a0ec9b2, 0x862b8e0e, 0xeb7df6a8, 0x8e0752d6, 0xf3b0eb84, 0xd971823a, ++ 0x6ab01a2b, 0x4dcbaa72, 0x09c575e3, 0x9d13743e, 0x1f0df406, 0xa1ce76c8, ++ 0xbbdfd1f6, 0xb2f17f56, 0xc7d2f49f, 0x671c10b8, 0x017bb665, 0x0433abb5, ++ 0xfa428d87, 0xd87b13dd, 0xf1a37c4c, 0x9cc484b5, 0x74687885, 0xf2cccf82, ++ 0xf6ef6652, 0x72c232cf, 0xc700b5d1, 0xb914fc43, 0x2ee8155c, 0xfaccf142, ++ 0xb89609d7, 0x86b02a9b, 0xf3ce59e6, 0xc485a1c8, 0xef899d27, 0xb9663f9b, ++ 0x53f82a1d, 0x3bad67d5, 0x221aacf6, 0x90882e8a, 0x671dbacb, 0xd20bff3f, ++ 0xcdb4eebd, 0xb74bcd41, 0xf141586f, 0xe88f2681, 0x8df4ea1d, 0x5b639f26, ++ 0x58707c2c, 0x058afdba, 0xfbdc7ed4, 0xb7a4196d, 0x1b05b7c7, 0x6aee7dc9, ++ 0xc844303d, 0x7fd7e689, 0x7d8a5d21, 0xfc8ac4f9, 0xbfce2091, 0x497a6e39, ++ 0x572f7f9c, 0xf6549df3, 0x1c457ef2, 0x359bc5aa, 0x7be4de7b, 0x978c38c3, ++ 0x5d44bbf6, 0x6fc7e2ff, 0x167c429b, 0x8b488efd, 0x76d4eb43, 0xf77cdacb, ++ 0xdfa23ed1, 0x1c51d515, 0xbbf7d05a, 0x2bc7baa2, 0x7e8d0e38, 0xb674f457, ++ 0x76aa871a, 0x73ff5411, 0xf686da91, 0xd0b8e367, 0xdee0b3ec, 0xc2b13f96, ++ 0xaa72a761, 0xb87ac1cd, 0x5be70361, 0x78f0f6b5, 0x268af332, 0x48d64bc7, ++ 0xf86b57ec, 0xe2da7c2c, 0x3e1475a4, 0x65fd883d, 0x7dc5f3f4, 0x488f3574, ++ 0x5de8066f, 0x50c496c1, 0xdd2fdd3a, 0x20eb9ad2, 0x1e77fc3f, 0x0a647c27, ++ 0x038b4faf, 0x2be7e52a, 0xe9d09de8, 0xc2be31db, 0xfcf7cb4f, 0xe58ad1ba, ++ 0xf5e96be5, 0x372d2d0f, 0xd1a9fc81, 0xd1f065bb, 0xa47be038, 0xfdbef28c, ++ 0x525b7c84, 0xe044a00c, 0x07e94623, 0x00792f4a, 0xd8bf4a8b, 0x7d5d24dc, ++ 0x5d32e39c, 0x749284ff, 0x8c637d5d, 0x5e031778, 0x38af2067, 0xd1245efc, ++ 0x1faea579, 0x715ff104, 0xfdc85df8, 0xf37693f1, 0x62db11bb, 0x5f244fce, ++ 0xded7523b, 0x89976f22, 0x333ecbaf, 0x1579e8ea, 0x6f11b865, 0xbfd0fb25, ++ 0xb6c679c1, 0x8263ebeb, 0x317ea05e, 0x7cba8cfb, 0x97d14584, 0xf7ab664f, ++ 0x50c28622, 0x1ba27e5d, 0x4fef82ef, 0x5f30309f, 0x2fe64314, 0xcf088aca, ++ 0x3d29f026, 0x841a76f1, 0xa87a75bf, 0x75a5e1cd, 0x265179ed, 0xd2e01839, ++ 0x4cd07fe3, 0xbb07fe3d, 0xb21ef8f5, 0xd4ef8f58, 0x2fbe3d7a, 0x35e3d06f, ++ 0x5bc7abcd, 0xbab19ac6, 0xe54d59f6, 0xface72ba, 0x57f6bac9, 0xcae9a6f8, ++ 0x81fd9fc3, 0xf37e7dae, 0x617d5d7c, 0xbd5d52cb, 0xf17d67c6, 0xf2ff08c1, ++ 0x80337e28, 0x307c3ce1, 0xba5df76a, 0xfa2bbef9, 0xeaa3915f, 0x59fe9505, ++ 0x4ef09faa, 0x490789fc, 0x6ac6a75c, 0x33cd4ffa, 0x8e389994, 0xae49577b, ++ 0xa0bd2388, 0x6a9739da, 0x13ca60e7, 0x765c27ac, 0xc4047651, 0x07918abd, ++ 0x0af1155d, 0xf710afdd, 0x344f8a2a, 0xfb502455, 0x3756f7a8, 0x73ba4896, ++ 0x57f7e8ee, 0xe5abbdd3, 0x23ee8904, 0xd1897b8a, 0x77b41ff7, 0x18ce5558, ++ 0x5f78f9dd, 0xbcb4b2ef, 0x6009c612, 0x60c138a6, 0x3d8877e5, 0x7ac720fd, ++ 0x3734fd99, 0x496f6dfb, 0xdd37ce6e, 0x230c0d64, 0x887cfefe, 0xe20e7a7b, ++ 0x50e0d3ad, 0xdf53cfd8, 0xc6d17569, 0x0bd39df8, 0x52dde9d3, 0x94b98617, ++ 0xff751ccf, 0x36bdd373, 0x583dbe5e, 0xfa69c22c, 0x67b8e771, 0x254738d1, ++ 0xb0a37dfb, 0x4f633bef, 0x663b230d, 0x91fdf3a1, 0x873dee7c, 0x29f3bbea, ++ 0xa87f7083, 0xc506836f, 0x77b8e7cb, 0x9c9f1c49, 0x44c6c1a2, 0x931aefc8, ++ 0xc4546efa, 0x7c55b36b, 0x2cdaf169, 0x38a3fe75, 0xe7d462c4, 0x62de5bb3, ++ 0x694b2cbc, 0x7abce357, 0xbfc71d87, 0x246da86d, 0x8e72f3df, 0x5f388872, ++ 0xc886df8b, 0x5ebec4df, 0xb2d5fee8, 0x38ba9394, 0xee4f9e1a, 0x9d194f35, ++ 0x5bef0b0f, 0x6d747f8c, 0xa3a1db2c, 0xef39536b, 0x93bf1e18, 0xebb30af3, ++ 0xe7baf7f5, 0xf1d21c36, 0x11ef3cdf, 0x7fb07d5d, 0xf70434c8, 0xf0797c1f, ++ 0x7f115ba4, 0x8a592f1d, 0xba458e29, 0x1113923d, 0xca1f0767, 0x5df34899, ++ 0x78a79f78, 0xbdea6d1d, 0x879f6d5a, 0x1cb9073d, 0xeea304f4, 0x71757939, ++ 0x7fcd06af, 0x9ff25c80, 0x473f5243, 0xcb9c796f, 0xd93c4573, 0x6d2fbea6, ++ 0xb697df53, 0xdb41efa9, 0x6d9ff7d4, 0xed4ffbea, 0x049b6e7d, 0x3257ba4e, ++ 0x985e524b, 0x73efc697, 0x759f699b, 0xf405434b, 0x30aeb17e, 0xf9924738, ++ 0x398bee7d, 0x9f7d7a03, 0x2ea1205b, 0x76739d38, 0x67f291ba, 0x649dbcfd, ++ 0x99f7ffb1, 0x2cd944cf, 0xcf1fe3e4, 0xef174db4, 0x34addd75, 0xec8351ce, ++ 0xfef5be27, 0x64f3e24e, 0xd3cd0670, 0xeefde22e, 0x9ce2399b, 0xfc145764, ++ 0x6bd08e6b, 0xa56150ff, 0xbf3660fc, 0xe16f5ab7, 0x1f3856f7, 0xeef37bbf, ++ 0xe8daf910, 0x7f237177, 0xfe93f16f, 0x873df2d0, 0x3339c472, 0xb92397bd, ++ 0x8b53ffeb, 0x0c172f78, 0x75f7a30c, 0x45c9ff74, 0x9c0fbdf2, 0xce5dfde2, ++ 0x3077c8a6, 0xfbd47287, 0xee83b779, 0x9ecd5e7d, 0x9f4987a3, 0x9f71ceac, ++ 0xbea03d61, 0xdf89ab1b, 0xb7defec9, 0x493c0f98, 0x06b1ae78, 0xe6aa9f85, ++ 0x4fc2fb03, 0x63c082c7, 0x77e16979, 0xd9ef116d, 0x5e1a9d78, 0xc78675b4, ++ 0x6bff3f39, 0x7cad2d79, 0xd9fdc37c, 0x7f884f24, 0xa5946f91, 0xe97ad3b9, ++ 0x9c57303f, 0x754acdc3, 0xf794b949, 0xbf7917ab, 0xfd347f30, 0x87d243f0, ++ 0xdebd6c7b, 0x47fad7d7, 0xc766b3ef, 0xee07c61e, 0x2fed0e73, 0xb9099f62, ++ 0x68ecfb11, 0x9e58f03d, 0xfbfbe972, 0x2dc8efa6, 0x4d6e30fd, 0x8e8f2dea, ++ 0xffc22656, 0x87fd68b2, 0xd1fdf51a, 0x753ca6f1, 0xfa35c90b, 0xb8d4db27, ++ 0xf12fec86, 0xb77f6685, 0x460e3159, 0x770525bd, 0x79a7feb1, 0x93efff89, ++ 0xb5076cbc, 0x84a3467c, 0x06f28e76, 0x176c15ee, 0x0e6dcbe4, 0xc86ddfe2, ++ 0x7be2017b, 0xf39633a3, 0x73f151d8, 0x84bbac6d, 0xcff2b5e8, 0xbe2883e5, ++ 0x64f6fade, 0x76134e35, 0x9fcab469, 0xda7e69a3, 0xf3025e47, 0xbeba916d, ++ 0xfb3d6b62, 0x2bc063c3, 0x9a85bc8b, 0x4bbb5907, 0x1ffddf17, 0x0f9284da, ++ 0x00004210 + }; + + static const u32 usem_int_table_data_e1h[] = { +- 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x33a98f8a, 0x32e8f430, +- 0x31e8a430, 0x43d4dc30, 0xcf12d388, 0xbf4ca2e1, 0x83030b30, 0x038b1028, +- 0x7f1024b1, 0xf8606463, 0x7ebc48ce, 0xbb04115e, 0x81818045, 0x070fc80f, +- 0x1905ffd2, 0x330b3e18, 0xf903f030, 0x6dfc80b3, 0x88087c40, 0x376280c3, +- 0x2067f480, 0x02c40fbe, 0x17cdf822, 0x417f2024, 0x07ff9508, 0x1042ff8d, +- 0x61637ebf, 0x0496f2fc, 0x4de1b1e4, 0x0f8cdc04, 0xef40a77f, 0x6a87e040, +- 0x557d7ca8, 0xa02b0606, 0x843a8758, 0x7e4908ff, 0x40cc5016, 0x93e6c215, +- 0x05506067, 0x61ab1ff2, 0x281f9737, 0x5f9406af, 0x00073506, 0x15e5ac6f, +- 0x00000368 ++ 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x022aa78a, 0xc3033ab1, ++ 0x06060d6e, 0x06064d03, 0x1c840631, 0x373fb0ad, 0xb177fa65, 0x01ec3030, ++ 0x7c407de2, 0x980b8800, 0x990a1818, 0x242fd788, 0x0afb608a, 0x03083032, ++ 0xfa40a2f9, 0x4c50108b, 0x04418184, 0xf2064fc8, 0x1bb881eb, 0x6281a388, ++ 0x21f4804b, 0xc40d5e20, 0xcdf8a2a2, 0x7f202317, 0xff951854, 0x577f8d11, ++ 0x037ebf08, 0x76f2fc11, 0x61b1e404, 0xe3f22b66, 0xbd0283c3, 0x2ad78103, ++ 0xcafff2a0, 0x00f03031, 0x211542c5, 0xf24875fc, 0x7fb140e9, 0x39f61072, ++ 0x015c6009, 0x602bd6e5, 0x503cf737, 0xae5013fe, 0xf7349158, 0xf2a0e914, ++ 0x34208c5b, 0x711dda00, 0x0003a8d3, 0x00000000 + }; + + static const u32 usem_pram_data_e1h[] = { +- 0x00088b1f, 0x00000000, 0x7dedff00, 0x45147809, 0xf4f570da, 0x73264cf4, +- 0x10909264, 0xa70930ae, 0xe15c380a, 0x1084ca30, 0xa8ea2416, 0x1388a888, +- 0x2e421081, 0xf57175d1, 0x11c3a7fb, 0x9e375941, 0x1d47facb, 0xa22cdc10, +- 0x60188806, 0xb200c1c0, 0x1761bb8a, 0xc363d715, 0x01921a0d, 0xe5c58f15, +- 0xeaadf7ab, 0x44ceee99, 0xeff3eba2, 0xe3fdfb7e, 0x575453e3, 0xef555bf5, +- 0x5dbd6f5d, 0x71024a31, 0x02e426f6, 0xf211c6fc, 0x4908488c, 0xe36d9689, +- 0x1749c7c3, 0x92cde442, 0x8840ad6b, 0x343dbaf0, 0xfb21046e, 0x33010956, +- 0x587687ad, 0xd3f5a109, 0xcc07d735, 0xd43eb419, 0x9afac1ec, 0xbee7ac1c, +- 0x48c3aefa, 0x8aafa5eb, 0x761ba846, 0xdb34729c, 0x37372908, 0x7d05723d, +- 0x24557e1e, 0xc450e9ab, 0xb240c535, 0x471e3908, 0xad196fd8, 0x685212a7, +- 0x55d2d561, 0x3cc2673b, 0xc4cc1a8a, 0x6e94e142, 0x15ed7b99, 0xaf773eb4, +- 0xe94ba044, 0x77534ada, 0x10179f5a, 0x68bea0ea, 0x4e3887c7, 0x545278db, +- 0x4f908837, 0x35c471fd, 0x4d1dd680, 0xe7d137a9, 0x130d81c5, 0x7af17fa1, +- 0xfda06dc1, 0x7e766b8b, 0xeb8bf004, 0x8522bea5, 0x4ad6bf3f, 0xd8d9035c, +- 0x63ac0817, 0xdf30b5ce, 0xc4483fd2, 0xe745eb4c, 0xc01136ef, 0xe4dab191, +- 0x8ff8c3b5, 0x18765c9a, 0x51c716a7, 0x7bfa59f0, 0xaf7d0e3a, 0x0dc165ec, +- 0x10332b4b, 0x75a7cc1f, 0xf3fa658b, 0xa5575836, 0xbfbc3fa9, 0xf41341e5, +- 0xd8281b9b, 0xfcc1716c, 0xc2269956, 0x99566b3c, 0xe145070a, 0x517dafcd, +- 0x2be3af33, 0xa9f574fb, 0xa7e5f5da, 0x735a8a7e, 0x884c5eb4, 0xf306cea7, +- 0x1fae980e, 0x547e7d1c, 0xcf7a4448, 0x2b8915af, 0x529f0a2e, 0xefcb9f1e, +- 0x1f027fd2, 0xd607b76c, 0xb5e94466, 0x8eff09c0, 0x93acebd2, 0xce18cfd3, +- 0xca57c352, 0x740e8047, 0x277ed53e, 0xd3f98f96, 0xefc27cb0, 0xe53dbc42, +- 0x4ae5881f, 0x3f9f1bbf, 0x658d1fed, 0xe583df8d, 0x5849feb3, 0xec5efc06, +- 0x1d3fdab7, 0x1f7e35cb, 0x5fc17f3e, 0xbfad6584, 0xf3af9f02, 0xbd72c42f, +- 0x2fe7c65f, 0x596197fb, 0x72c6afe7, 0x96257fa3, 0xf600fef5, 0xd7e9ccdb, +- 0xe7c3afe0, 0x580dfd5b, 0x2c21fd06, 0x62f7f877, 0xd5e382b9, 0x8c724d91, +- 0x0f0e2f14, 0x20715271, 0x1c9ef949, 0xbc93d689, 0x433a9eac, 0x7ad131ce, +- 0x29d68faa, 0x8497ba9e, 0xdeb4cc72, 0xa7b582bd, 0xc7c6403f, 0xccba7ad1, +- 0x785733da, 0x3d685bc6, 0xf7b59ab3, 0xc7c791af, 0x00ff7ad3, 0x7d74bf6b, +- 0xd695bc68, 0xed63ad2f, 0xd7248243, 0x4243eb46, 0x9f6c3eac, 0xeb4ed727, +- 0x3d589ac3, 0xd73923eb, 0xcd59eb41, 0x2db1fdec, 0x5a04dca1, 0xed661b1f, +- 0x166f9d57, 0x67f8315d, 0x459be4b3, 0xf2032d28, 0x1bb18f14, 0x777c9bad, +- 0x97c53713, 0x1c63d53c, 0xc923f143, 0xbe4bbed8, 0x4c1bdb1d, 0x27bfb632, +- 0x56fb6217, 0x27ed8029, 0xdf6c72e5, 0xfb600a6a, 0xac42f2b7, 0xb610a507, +- 0xb12b2adb, 0xc214d07f, 0x87caf4f6, 0xd4877db0, 0xcaeeed8c, 0x877db1c7, +- 0x1fdb19a9, 0x99e3525b, 0x0b0feb40, 0x2f81a7be, 0x22be0b17, 0xadf807d2, +- 0xf94bcd2e, 0xd3204aad, 0x0117bf81, 0xaaf6d253, 0x47d4266e, 0x7ace3f9b, +- 0x6f38145e, 0xe17a8176, 0x20650f0b, 0x8e11e79c, 0x1788e144, 0xc9f59387, +- 0xac9c0d68, 0x38148a4f, 0xa58e11eb, 0x7f367073, 0x9f3b5632, 0x38158a4f, +- 0x149192af, 0xeb73bd8e, 0xb65bfaca, 0x2b7f3e76, 0xc0ece051, 0x6e7624f9, +- 0xb4c70d3e, 0x163869f8, 0x389bcfc1, 0xcdce949f, 0x2d71f467, 0x8f1f467e, +- 0xe109a7e0, 0x9c1ceb74, 0xfc5ae386, 0xe08f1c34, 0xd38403e7, 0x1aeb73ab, +- 0x9f8b427d, 0xf82227d1, 0xc9f88c39, 0xad9c1ce8, 0xd9f8b5a7, 0x9f823a7a, +- 0xbf4e10cf, 0x6c6badce, 0x633f16ab, 0xf9f8235b, 0x4975d702, 0x6d6ce0e7, +- 0x6b67e2d5, 0xdf3f046b, 0x9dc19c21, 0x36d8d75b, 0xb6c67e2d, 0x1263f045, +- 0xced0ce00, 0xa5f827cd, 0x2fc13f16, 0x4049f823, 0x373b2338, 0x5a73ec9f, +- 0x8b9f64fc, 0xe10d27e0, 0x9c1ce98c, 0x7e2d39e0, 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0x1de3edc6, 0xa2d6ce33, 0x620c6638, 0xb0e43f74, +- 0x78e762b3, 0xccc3fe46, 0xae60d061, 0xde326caf, 0x9e5d98c7, 0xafb616ff, +- 0x8f407612, 0x49f55717, 0x91fe520d, 0x6c339be4, 0x3f8dc624, 0x6242559d, +- 0xdf4a91df, 0x4f6aecbd, 0xf6b0e371, 0xd3fb45f3, 0x1d71c469, 0x2b83ddf4, +- 0x3e8bb1ea, 0xf287d137, 0x8bf12221, 0x9dff0a74, 0xa07f5d35, 0xfe1167dd, +- 0x48fc3879, 0x13dd394c, 0xbd57edd0, 0xf578e7a5, 0xbd0986af, 0x38adcba9, +- 0x1f33b087, 0x4c91345d, 0x1ea7ee5e, 0x67d9f67d, 0xea7e5d5d, 0xf49f610e, +- 0x8333a27e, 0xf98d1954, 0x549a502a, 0xaca3f10f, 0x60052756, 0xdaffdb9d, +- 0x27f7fdf3, 0xf01e7975, 0x2fb61260, 0xb072fb71, 0xdf17cc8c, 0x072cba96, +- 0x34db72e5, 0x946aeedd, 0x9cedbe37, 0xbe7437fb, 0x1bcf0efa, 0x9d90196f, +- 0x4a517988, 0x59be45ab, 0xe415a65e, 0x3d137dd5, 0x3ff7156e, 0x631b1db7, +- 0x36f4f8c7, 0xcf0da0a5, 0xf129b777, 0x536db405, 0xde901e78, 0x5e78515e, +- 0x78f1a29e, 0xbcf0a2b7, 0xa77f3d39, 0x84dbc065, 0x03ddbd0f, 0x8d15af82, +- 0xd288e3df, 0x5d9da81a, 0xb2f7d2f6, 0xe28cf1ec, 0xff957652, 0xa67450ee, +- 0x907bd999, 0x2cc3b5d7, 0xe5b61f64, 0xa24db415, 0x146ec9f9, 0x05496d93, +- 0x1147a449, 0x8d7ef0ef, 0x316f13a3, 0x0a9fc788, 0xd4fdebbc, 0xde75f0b4, +- 0x417771bb, 0x23f45f49, 0x5f9087bd, 0xec8b29b7, 0x7246ef78, 0xbfb4de14, +- 0x432661e6, 0x7f57663e, 0x7f450a97, 0x24fec53f, 0xfd8a8147, 0xbfcf5859, +- 0xe8b6f8bb, 0xef3defe7, 0xfa360cc0, 0x226308de, 0xd494268f, 0x2761f9d3, +- 0x631cf0fd, 0xfef7f744, 0xbd677edb, 0xfe09de31, 0xbf516fe6, 0x7b9de654, +- 0xe13d127b, 0x68d6e6fe, 0xbf742fae, 0xfb795651, 0x0f7e66ad, 0x9abeff55, +- 0xb1ca47ee, 0xdd743c46, 0xb874e303, 0xc838f2aa, 0x7c518555, 0xafae5226, +- 0xb86e3a9e, 0xd8768147, 0x2c71fc23, 0x0cf4cfd1, 0x2e2973c2, 0xa3dcbadf, +- 0xebfd444e, 0x1f7f7728, 0xa8a4abbf, 0x30b7ca66, 0x5f12ff01, 0x9243de77, +- 0xc6cff47a, 0x3574e70d, 0x24685625, 0xb7284ae7, 0xe03f3927, 0x728b953a, +- 0x1ecba07d, 0x03aeb8ab, 0x1389dce7, 0xbf5ce4c3, 0xbff7a21f, 0x3564e4fe, +- 0x74df5d7c, 0x6e79c2ff, 0x8f64fde7, 0xff1edc5d, 0xd8c7df6f, 0x40aeb2ea, +- 0x326cdffb, 0xc391e5ea, 0x86d63eb9, 0x75e0f88b, 0xb3b7ee99, 0xe1b4bea1, +- 0xd98b3f80, 0xf97a8e5b, 0xdfdf3540, 0x1499b1ca, 0x7eb03987, 0x829e445a, +- 0x30f0d06f, 0xb3aa2c79, 0x85abbe92, 0x03ed077d, 0x491ae823, 0x3afe9d2f, +- 0xe7e728ec, 0x27bd3a72, 0x91212a26, 0x89fe4c07, 0x09997e2b, 0xdcab9af5, +- 0xb039f267, 0x81d91b7d, 0x115ddade, 0xaf6f4ffa, 0xce0aff60, 0x73e280af, +- 0xa0e75057, 0xfcf6a49f, 0x51976cfb, 0xec7e0498, 0xb1e72eb0, 0x2bf62aa9, +- 0xab793f09, 0x51af6fc8, 0xb09eed0b, 0x42d8a5f7, 0x3e30a4fb, 0xde25e9a9, +- 0xc7ae1fe4, 0xefb4439b, 0x4810efd7, 0x9e60d7e8, 0xee5f22a0, 0x7ed0478c, +- 0x9df0d4a2, 0xdefc7d45, 0x5f39edcf, 0x690b555f, 0x018f281f, 0x0bfc017f, +- 0x8192ec53, 0xbe2d3764, 0xfcc44e7f, 0x28dadf95, 0x2123f79f, 0x3e42ed9f, +- 0x0163d37b, 0x2d2e8c76, 0xf027616e, 0x49f008d2, 0x49f20c41, 0x70d98a4d, +- 0x9b97a3ae, 0xe26f3ac4, 0xbf0f54e7, 0xc1e73f35, 0x39f83de1, 0x9f84c7e8, +- 0xe2ffa3cf, 0xe89bd309, 0xf07a78bf, 0x62cdea73, 0x53ce27ff, 0xcddc5b4f, +- 0xd39780ed, 0x3be86213, 0xf87d193f, 0xe8d3df3d, 0x7f8015f7, 0x4cd9ccf7, +- 0x532cd624, 0x843a77e7, 0x0608c99f, 0xca276f3f, 0xaef31945, 0xd5bddfc2, +- 0xdf8988e5, 0x3a26f9a3, 0xe0dc06cf, 0x3de3b6bc, 0x87ba3cbc, 0x39d3da57, +- 0xfe4eb1de, 0xc7a61301, 0x401f08fb, 0x5a38b09d, 0x4460f8b7, 0x31c3103c, +- 0x19c5f99d, 0xbf6fdbdd, 0xf9f8a261, 0xe20b1f2e, 0x51dc02ef, 0xbddf8c64, +- 0x76d9f225, 0x7f24612d, 0x429a72bb, 0x6a245fe8, 0x65f1e28c, 0x39fb631e, +- 0xbddf91a5, 0xeef9c636, 0xe7225af4, 0xebb5df4b, 0x7fd7d627, 0xff8a2acf, +- 0x22fdc645, 0x3eb47de3, 0x3c8523b4, 0x1854afee, 0xf51cb8f3, 0xd8bbe833, +- 0x714af860, 0x3314ae7d, 0xa3ac38c3, 0x2dcf323c, 0x21ecf020, 0x59e3a665, +- 0x92899eff, 0x6bdfe66f, 0xf546dc0d, 0x7e1dbe7a, 0xaba27177, 0x3aca5d6b, +- 0x117c9f31, 0xbcf40dcf, 0xd7185dae, 0xbce8bcc4, 0xd084d036, 0xc605ce1f, +- 0xf460ae49, 0xb75857bd, 0xf0e25ce1, 0xfa262d9e, 0xa31f0f1d, 0x1e01a1ef, +- 0xcc16e78c, 0x5850f147, 0x039ce1bf, 0x238069d6, 0xe4df01f7, 0x93de1fff, +- 0xa277e3de, 0x278f52f5, 0x61338b75, 0x2fa48007, 0xbdf38b86, 0xfa286ca1, +- 0x06fe4a41, 0x1495c3a2, 0x72cb5f9e, 0xdbdf3e7a, 0xf7e1fd09, 0x72887e93, +- 0x01718092, 0x04def866, 0x0f74c8f3, 0xe7c454c0, 0xe5ebea6a, 0x48c79742, +- 0xccd16dbe, 0xa684798e, 0xea0f6882, 0x600d9b13, 0xf8852efc, 0xee24b74e, +- 0x283ffd3f, 0x00812bd4, 0x0000812b, 0x00088b1f, 0x00000000, 0x9095ff00, +- 0x50c34b31, 0x97bf8514, 0x4a36ac46, 0x1056dac1, 0xa8508a09, 0x755a5095, +- 0x97375433, 0x221d0e8c, 0x38ba383a, 0xfc5d251b, 0x09f9ce01, 0xe6e284fe, +- 0x482ae0e6, 0x22bf8290, 0x26a697de, 0xcbbd0820, 0x77dde779, 0xddf73dce, +- 0x2e8dcc2b, 0x5eca7550, 0x75619047, 0x444506d2, 0x9aea1152, 0x47e17536, +- 0x3cd6a5a4, 0x7c22c128, 0x4c12092e, 0xecbbaa75, 0xfbd45ab2, 0x5ffed246, +- 0x73e4ec6f, 0x7569fd73, 0x27e7cad2, 0x22ff8eba, 0xba77e898, 0x00839d12, +- 0xe4e3e1d6, 0x65f68fbd, 0xc8773d13, 0x5f94dcac, 0xd53da3e8, 0x3970079b, +- 0x3adf376b, 0xdbe20d46, 0x0aa8f38a, 0xa567047b, 0xfd398f74, 0xed34737e, +- 0xb0a56f2d, 0xef37e657, 0xbf89695e, 0xc21b71a5, 0xc1ec8481, 0xc81447a8, +- 0xbe0daad1, 0xb9417dcd, 0x3e99cb8b, 0xbf05c593, 0x67eb81f0, 0xf3ba7931, +- 0x8416bf0f, 0xcb62bcbf, 0x5f1dd7ff, 0x7f74f68d, 0x6b7d238c, 0xbb92f72c, +- 0x50a8dce1, 0xd9f695f8, 0xf4112ed5, 0x738dbcf3, 0xf3e569f1, 0x742b007e, +- 0x02505747, 0x00000250 ++ 0x00088b1f, 0x00000000, 0x7de5ff00, 0x45547c09, 0xbedd77b6, 0xee92774b, ++ 0x1090274e, 0x5849d0b6, 0x05b36035, 0x2aced050, 0x4056904a, 0x2c3b1151, ++ 0x19176421, 0xbaf2ce1f, 0xd14112c3, 0x8be33b89, 0x1330a363, 0x5180d419, ++ 0x206c06a3, 0x13383a20, 0x19705066, 0x9b6459a7, 0x36e09a40, 0x757c3833, ++ 0xdcedd54e, 0xb898e9db, 0xfbcdefbc, 0x4ac3f8be, 0xcb5baadd, 0xea73ff39, ++ 0x2b73a9d4, 0x6c409292, 0x04b90883, 0x3210d73f, 0x24842255, 0x7603a474, ++ 0x8fb28dae, 0xebbac424, 0xbda1a8de, 0xd737e909, 0x45a288e0, 0xc7133deb, ++ 0x7909971c, 0xea732046, 0x2a4909d3, 0xc652a9aa, 0x6da174d1, 0xa427688c, ++ 0xc33dd24f, 0xd212c79a, 0x99eb4dd7, 0xa25cfe08, 0xab657eff, 0x90692389, ++ 0x91ae0af3, 0x69aafd1d, 0x1fe942d2, 0xf9fd4d01, 0x4a9d15c4, 0x2fccf1c7, ++ 0xcdbafbaa, 0xfd003c84, 0xa752810e, 0x71d06481, 0x2cdebaf1, 0xbfda3ffa, ++ 0x56f8aad7, 0x0688840a, 0x09112c7b, 0x120f4989, 0x9fbc2f78, 0xc3953d27, ++ 0xacde1924, 0xe859728c, 0xeb94e87c, 0x21cbd423, 0xcd41d202, 0x26764ec7, ++ 0x57b8e979, 0xbce2237d, 0xa425f557, 0x2447be85, 0xf4d08d87, 0xc847125a, ++ 0x321e4278, 0xf903ee0f, 0x243f3b55, 0xec7eda76, 0x6af120b8, 0x21eb5fda, ++ 0xe4246ec4, 0xd3098f3e, 0x4f1b1e55, 0x187d8893, 0x763dab21, 0x8679574c, ++ 0x80ff7a63, 0x29325a47, 0x06bec5fd, 0x59111d1b, 0x66c9bf6b, 0x4f68ef4f, ++ 0xca6f9b8e, 0xc5321074, 0x484cec9b, 0x0c12f5a1, 0xa9495c84, 0x9455f344, ++ 0x1d884397, 0xbceca5c7, 0xa4f3c70e, 0x9dca32ad, 0x345cf1de, 0x3fcc3710, ++ 0x29df9c66, 0x38c63a52, 0xbd92596c, 0xf4fe39e3, 0xdecfe7c6, 0x717c029f, ++ 0x3cba034f, 0x2f011c49, 0x38adddd0, 0x2bfad136, 0x52d24765, 0xd0a8aeda, ++ 0x0e19d2f7, 0xe31db1a4, 0xa4f4059c, 0x593991fd, 0x840dfe3a, 0x7bc02471, ++ 0x37c019f6, 0x6df183b3, 0x022be025, 0x76f1e65f, 0x369cd956, 0x89072786, ++ 0xa6d12784, 0x5d3993c7, 0xc4fa478f, 0x9e72e276, 0x17aefda7, 0xa5c9df2a, ++ 0x312ef4f3, 0x67d13638, 0x011a84fd, 0x2bdb57da, 0x57ec0621, 0x922df7cd, ++ 0xdae181fc, 0x0f38bcf6, 0x6025bcfa, 0x2dbcfcea, 0xe802782b, 0xb6557de8, ++ 0x1053a26f, 0xaff8b2de, 0xbfdbf4a1, 0x6919f041, 0x0623bfde, 0xf6b67c71, ++ 0xd2919f46, 0xa368e779, 0xdd9fea13, 0xecf98998, 0x4ab7de57, 0x15ecbcb4, ++ 0x61bc8251, 0x806b69c7, 0xd8c2a7d2, 0xf455d0f2, 0x9115f079, 0x4ddd8b3c, ++ 0xe09efa43, 0xb35f2063, 0xcb14617c, 0x39d86d96, 0x6a2dda0f, 0xda289234, ++ 0x8bebd94e, 0xe68ab86f, 0x0993ef17, 0x54db2954, 0xf9a3f4a5, 0x1ea13e25, ++ 0x7c762bf2, 0x65b4fd8c, 0xebe02291, 0xc52dc019, 0x25b59b65, 0x5e7d3671, ++ 0x079adbec, 0x08b78bf5, 0x52214a0e, 0x13f3bb5c, 0x41b8bf68, 0xf6d22c1e, ++ 0x8862ea4b, 0xeca7435d, 0x00dd1657, 0x477b2de3, 0xa4f61426, 0x0adde2e8, ++ 0x35489df0, 0xd963c80a, 0xc01587a6, 0x3ecf19e9, 0x77a547ec, 0x1fb4f3d9, ++ 0x8bf95efa, 0x56a60382, 0x3b38606e, 0x9cd47af7, 0xaf30cce7, 0xbc28652a, ++ 0x0a7dfaff, 0x2bec5bd4, 0x0eca3578, 0xe4a0dbe3, 0x376b38c1, 0xb91a8528, ++ 0xbdfba929, 0xd6275c6e, 0xa771f5a7, 0x9a91c677, 0xab72e19e, 0x88a98be6, ++ 0x3e487ca1, 0xfe0d46e5, 0x1e9819e6, 0x8913a928, 0xbc0e023d, 0xf27933ef, ++ 0x36f8b76e, 0x6bf074a5, 0x6efe8da9, 0xbb57e0ef, 0x0a4ff38d, 0x0118dc66, ++ 0xfd710fdf, 0xc7f5c351, 0x683fa023, 0x1fd718fa, 0xb1fd704f, 0xe7c0e3de, ++ 0x6226794f, 0x6271eb5a, 0x54cf6bfa, 0x171e7d4c, 0x33d67bd6, 0x1e8dd307, ++ 0x8dff3e37, 0x3ad308a7, 0xdf3e254f, 0xe98e59ec, 0x9f178f16, 0x8359e8bf, ++ 0x06a7bd69, 0xf59e6dd3, 0x7c783698, 0x4f55ef58, 0x9e8da61d, 0x86fe7c7a, ++ 0x26d311a7, 0x1dd31f8f, 0xfa9a5fc0, 0xee982d3d, 0xb4c61cf2, 0xf7c013d9, ++ 0x614e7af6, 0xddd38eba, 0x4a64993a, 0x27566e94, 0x9f183d41, 0x6994ccef, ++ 0xf2c5de3e, 0x99bd7389, 0xba27cd0a, 0xb1d29e69, 0xd33fa95f, 0x2556eb08, ++ 0x39fe4f2b, 0x7cd132c9, 0xa79597b2, 0x456673ae, 0x0d6a7cd1, 0xeb5a1f2b, ++ 0xf9a68acd, 0x7e563ea1, 0x567f16d9, 0x565fcd0c, 0x3547cacf, 0xcd336c91, ++ 0xfcb3f28f, 0x6ccefd98, 0x698fcd0b, 0x4f8cf961, 0x9a56d9bc, 0xf7b008cf, ++ 0x67f56caf, 0x95fcd2c7, 0xf57e5641, 0xa3639245, 0x8089abf9, 0x66732cf9, ++ 0x67cd1c4e, 0x6f3e58d9, 0x8f648140, 0x721dbf80, 0x58a10160, 0xe55aaf88, ++ 0xbcd12694, 0xaa9bb812, 0xeab8323c, 0x65fbcc41, 0x33ca10b2, 0x79609eaa, ++ 0xf2832c85, 0x60cf55a9, 0xc76c977e, 0xeaaadbf2, 0xb35d129c, 0x2c762976, ++ 0x8adaad2f, 0x13b2cde5, 0xeab3ffcb, 0x566f2c0d, 0x535e589c, 0xf7cb1bb5, ++ 0x7f2c6eca, 0x963f6ab6, 0x58dc55ef, 0xf7aac8fe, 0x2f34399d, 0x6166dc1b, ++ 0x776be83c, 0xa963ea11, 0x71f4093e, 0x9fdfd735, 0xbaa675f3, 0xfd04e2af, ++ 0x8c9be3b6, 0x63a144e7, 0x4df1d95d, 0x5d606fe1, 0x0824eda1, 0xd08eb009, ++ 0xdbeec476, 0x135ffab9, 0xfd5ced75, 0x9db522af, 0x544f1c64, 0xf1d9dacf, ++ 0xe3f52baf, 0xdab157f9, 0xc76c30ce, 0x5d79b3d2, 0x7eb2697d, 0xd54a973c, ++ 0x4ed81c76, 0xe3c6cf5c, 0xdae82797, 0xd58bcbf1, 0x3b612676, 0x8f1b3d09, ++ 0x6ba49953, 0x512ca9c7, 0x76c2c9db, 0x1dacf6fa, 0x7e9572bf, 0xda894a3c, ++ 0x676c34ce, 0xe5e6cf60, 0x8fd14e34, 0xb6a658c7, 0x9ef90b33, 0x7676b3d2, ++ 0xd9f4f459, 0xe7d10965, 0x48676c0e, 0x6595e6cf, 0xcb27d3d5, 0x214fa21a, ++ 0xcf446bce, 0xd565d9da, 0x359767d3, 0x6c0a9f44, 0xe6cf6467, 0xa7ab1595, ++ 0x886c564f, 0x9db1cb3e, 0x4f1b3dd1, 0x3e9e8273, 0xfa2109cd, 0xe33b6154, ++ 0x9c9e367b, 0x727d3d44, 0xb9f44312, 0xa93ce91f, 0x2734ed67, 0x9cd3e9ea, ++ 0xa3cfa218, 0x3d299e38, 0x1f4e579b, 0xfa727d3d, 0x8b53e884, 0xebba64ed, ++ 0xb6843c70, 0x9dbae963, 0xf4f503bd, 0x44303bd9, 0x4ed84d9f, 0xad276d2e, ++ 0x92f276fb, 0x4bc9f4f5, 0x45e7d10e, 0x3d75cfa4, 0xb26f676b, 0x937b3e9e, ++ 0x0d79f443, 0x67bd33c7, 0xa41bcaf3, 0x20de4fa7, 0xa46b9f46, 0xd0ceb8d1, ++ 0xfb01d3b5, 0x64076bb3, 0x6071853a, 0x68bcb31f, 0x7bb01073, 0x219ed544, ++ 0xd6914e2d, 0x1b896f37, 0xdad13f73, 0xc36f5935, 0xcad42c78, 0xb135dad3, ++ 0x7675a313, 0x5e339c54, 0xb535ef97, 0x827eae9f, 0xde57552b, 0xba65ce67, ++ 0x31eebef2, 0xa2ff7cba, 0x07f5752b, 0xf2e96656, 0xaf5f9683, 0xbde29fab, ++ 0x5b4f9749, 0xfeae9b73, 0xbaf99a90, 0x8beb61f2, 0x7c23e575, 0xcbf9754b, ++ 0xabaa7eeb, 0x857eb23f, 0xc68afcae, 0xa3e575fb, 0xf2e88ffd, 0xa53df763, ++ 0xe5be3fab, 0x84f95d59, 0xe5759bc3, 0x74db0293, 0xbd4eabf9, 0x253faba1, ++ 0xbf974bb8, 0x7577ebe6, 0x9fc933f5, 0xe9b6f6f5, 0x5cfd5d63, 0xf95d31db, ++ 0x0b7f49b5, 0xfbf553b3, 0x849995a2, 0x2afbafed, 0x2dfaaf68, 0x7e95e60a, ++ 0xb14fb666, 0x538fda14, 0x16bb28fc, 0xfc537bd8, 0xb5086600, 0x15fb320b, ++ 0xe7d00b0d, 0x1ee95cf7, 0xefcfa366, 0xd857dc51, 0x1437d822, 0x8249026f, ++ 0x34806ed4, 0x993efcbc, 0xffab3de1, 0xe847a1c5, 0xe08615fb, 0x7f9a38d0, ++ 0x67eccc46, 0x196f0f18, 0x168eaed0, 0x8bd42549, 0x37dc1236, 0xf19297dd, ++ 0x0f23579c, 0x3b52066b, 0x7768e843, 0x424eec8d, 0x7c456a3b, 0xd535d815, ++ 0xfabce903, 0xe2187c51, 0xd3077a77, 0x261607f7, 0xa8d43ec1, 0xa8707db0, ++ 0x9ff6857f, 0x065ffd8e, 0x6c0c3bfd, 0xbfde185f, 0xaea27531, 0x9172537f, ++ 0x42937fae, 0x5251b7fb, 0xfbc7e8ae, 0x7dbee137, 0xf61fa1bc, 0xc22e4c6f, ++ 0xe853effe, 0x7fdb4bbe, 0x2bffa874, 0x0de0090d, 0xa9fe62e9, 0x9fe7ea57, ++ 0xbf9fac5c, 0xb39fe6c2, 0x1ff79522, 0x35cff38d, 0x27f9b2a4, 0x1bf9b317, ++ 0xfea1bb59, 0x5ffa21ad, 0x7577f30f, 0xc9b4ff35, 0x2a0ff9fa, 0xc8dfcfd5, ++ 0xe2b59ffa, 0x19bfde32, 0xb86d9ffb, 0x507fcd8c, 0x18aff629, 0x8fc00edd, ++ 0xd2ba3fd2, 0x0327fb47, 0x03ebe2a8, 0x40fda170, 0x0a9e3c3a, 0x8643d50d, ++ 0x3dc3a454, 0x5f6f0cd1, 0xa1bc5346, 0x73e2f33e, 0x939aa3e2, 0x39caabee, ++ 0x64b64bd6, 0xb0f7a02a, 0x4590913c, 0x1b0ba87c, 0x7937c445, 0x421be8cc, ++ 0x51ae7bc7, 0xe17e42f4, 0xa07c5363, 0xe48c2b5f, 0x27bc174e, 0xff3c3f11, ++ 0xcf91f1ec, 0x9e15e76a, 0x4f91aa2e, 0x7813f244, 0x4af0c8b3, 0x0097be3a, ++ 0x51fc9a04, 0x8d838fba, 0xdf7427f1, 0xe7fee843, 0xfbfacc98, 0x20f7ee94, ++ 0x3dfba01f, 0x2a9338dc, 0x3af14fe6, 0xc74c1fdf, 0x8fea22ef, 0x0b79e713, ++ 0x4f6d148a, 0x747bf262, 0x7e03e09d, 0x863cb9dc, 0x3c63bf12, 0xba5ede05, ++ 0xd591857c, 0xf8275e0f, 0x0db0159e, 0x46e7d037, 0xf1811ede, 0x1b1cfcd2, ++ 0x8ed0e77b, 0x2b057be9, 0xf4d60b21, 0x68e8bca7, 0xca712667, 0xb3fbe87d, ++ 0xe0c81597, 0x8411693a, 0xaa1fe081, 0x3f132058, 0x09bd9bee, 0x83839d24, ++ 0x1b36f78e, 0xa746ff6b, 0x3feb5c7c, 0x9c9b2399, 0x399e3a2e, 0x7f8e2205, ++ 0xf97d54e6, 0x9c623b47, 0x5d345186, 0x33f628f3, 0xbf2fa5db, 0x7f3e8e65, ++ 0xa79f5bab, 0xeb0caaeb, 0xe145edea, 0xe85929cf, 0xe886e73c, 0xc74a074a, ++ 0xc3a70779, 0x57b2951d, 0xedba57c7, 0x7072d456, 0xce09b884, 0x3b17df0b, ++ 0xb973bfd7, 0xd5e05f3e, 0x09ac17e7, 0xe6e39f6b, 0x51ffe704, 0x4f4d07c0, ++ 0x3d283e02, 0x747c738f, 0x3e3d55e8, 0x834d0e6e, 0xc79d43e1, 0xe0b18909, ++ 0xc7c32d44, 0xc8989aa2, 0xe1082878, 0x97c5a9c1, 0x1c79878a, 0x78e17f0f, ++ 0x8f5ebc58, 0x6f895bab, 0xff7d1275, 0x913b75f6, 0x05081f4f, 0x533f0f0c, ++ 0xe1d010f1, 0x10f1cdc1, 0x1c79bfce, 0x65eef30f, 0x67e70878, 0xb021e380, ++ 0x524c82fe, 0xf295f33b, 0x7ca79741, 0x0dbbe308, 0x1f9450fd, 0x3f30f111, ++ 0x713a6f34, 0xcbc05f9a, 0xe38bf13a, 0x8153cb01, 0x84e904ec, 0xae75a7ef, ++ 0x2e84f54f, 0x647d78bf, 0x6e3457fe, 0xf35c7758, 0xf9feacbc, 0x66bf5a75, ++ 0x5d56dd49, 0x75ef897e, 0xebc5fd5d, 0x8bf2ea77, 0xd5d1de6a, 0x80e6b05f, ++ 0xfde05f2e, 0xceff5750, 0xe57447e5, 0xd69e5477, 0x745edf95, 0xd5bf975e, ++ 0xfd5d77fd, 0x0f08e65b, 0x5db3f36a, 0xeb6a0f51, 0xa71a9ccf, 0xece8dfcb, ++ 0xd86fabab, 0xe0066231, 0x22fbff71, 0x0be3fb01, 0x7ff449c7, 0x1d90e17e, ++ 0xc7b8e750, 0xc270728e, 0x53d31c33, 0xc9ca071e, 0x4c44cf19, 0x36ee35cf, ++ 0xd742bac3, 0xd97042d1, 0xa91f170f, 0xd600335a, 0x6feb8275, 0xcabeb8ba, ++ 0xc163f34b, 0xcef4a638, 0xff10af5f, 0x58044258, 0x82b8f89c, 0xd03ca6a2, ++ 0xba7af94d, 0x5ceaf450, 0xfc881f9e, 0x8291e2bc, 0x7e08b641, 0x26b90eef, ++ 0x6a4ec1fd, 0x5e3fc2eb, 0xf697102a, 0x502b2139, 0xedcddc0f, 0xe9855284, ++ 0x7d6dd28b, 0xf21588b3, 0xdf95a1fe, 0x153d5fd6, 0x93803eb2, 0x2f3c9d34, ++ 0x4eb97f5e, 0x3ef013df, 0xc6de0027, 0xd4979eea, 0xaf7ba55d, 0xe388a775, ++ 0x425d072e, 0xe272edd7, 0xfac2299a, 0x3c9ddfec, 0xd38c2473, 0xbd044b39, ++ 0x768098d5, 0x6ea7ab64, 0x9d379c1d, 0x7a63d4f1, 0xe988d3ca, 0x1d7f8f09, ++ 0xf71d079c, 0xa8f4c3ec, 0x80d305a7, 0x9fa630e7, 0x7e98027a, 0xe98539e2, ++ 0xa6209e47, 0x635f3d87, 0x3c8781fa, 0xf41ced08, 0x93fd3098, 0x8b6986c7, ++ 0x73d30927, 0xa3f61f1e, 0xb8775dca, 0xedd7c53b, 0x08bf8033, 0x6567bb38, ++ 0xc99ad563, 0xa9fb381d, 0x4ce216f8, 0x7afe73a5, 0xa243c723, 0xb0550f0e, ++ 0x780f1bf7, 0xbd7ca6e9, 0xd5d871cc, 0x2bcb91fb, 0xc1effd9e, 0x2edc6bdb, ++ 0xeb78befc, 0x30ff53c0, 0x8775a53c, 0x3f11a7a7, 0x19af4f1c, 0xe41d6c6c, ++ 0x9f807a78, 0xfbf7865b, 0xfbcec8ae, 0xf39df642, 0x6a90033a, 0x21373f29, ++ 0xdbe62a64, 0x692bdf79, 0x03b416dd, 0xdd61c37d, 0x8ffe1f6a, 0xd0ee70a1, ++ 0x3f32987e, 0x85f9eba5, 0xba6ba4e3, 0x543f713b, 0xef4ca3e8, 0x2a3cb9d5, ++ 0xca35d19a, 0x3192a640, 0xf21dac84, 0x74fcc71b, 0x1e244bcc, 0x6e39f7de, ++ 0x976844b4, 0xdf40d6da, 0xd2bae8ee, 0x6828e5f2, 0xff53c4ef, 0x35f480cc, ++ 0xef475f6e, 0x27ced116, 0x401ce7fe, 0x64bad0df, 0x7f812474, 0xb144383e, ++ 0xa6409da1, 0xbde7e9e9, 0xb5bf475e, 0x69f9ea29, 0x6fd2124d, 0xfb4397f0, ++ 0xdd7e80f6, 0xe8eef7e9, 0xfde61f39, 0xeecf40df, 0x7a7763f4, 0x2fed3891, ++ 0xb7f9d236, 0xe63918ed, 0xc1e83b7e, 0xeaafb654, 0x79eade82, 0x6478f85c, ++ 0x7af7c249, 0x44b6e38a, 0xc92dc715, 0x285d6e70, 0xf6fdb0da, 0xc0b16186, ++ 0xdd3b5097, 0xeb7853f0, 0xdfb0c92f, 0x6fa29b3f, 0xbe832bef, 0xcf7df6bd, ++ 0xb5df6159, 0xdac16934, 0xa0f811e3, 0x55f565a6, 0x3b5acd6b, 0x6f9f51b4, ++ 0xd6a611af, 0xb1ecb8e3, 0x3ac246b3, 0xe996b951, 0xaa98e5ed, 0x2a4d2ced, ++ 0xd4ce7ec4, 0xfdb2c5a5, 0x83e98f9e, 0x2fa8712d, 0xb08a78ce, 0x9e3d8ffe, ++ 0xc751daae, 0x39034843, 0x4c7d0266, 0xaebad2cb, 0xa59e25df, 0x97f015cf, ++ 0x4bf92692, 0xf44d13b0, 0x77d825df, 0x6af30910, 0xa2f515bb, 0x3c0578d7, ++ 0x8feba2df, 0xcf5767be, 0x7ea52f88, 0xe448dc9b, 0xba5b8a84, 0xe3cb5c5e, ++ 0x96ea4a43, 0x65dad5ac, 0xe977f565, 0xf78d15f2, 0x71dad5ae, 0xd50bf025, ++ 0x9052a4bf, 0x1ca53700, 0x79926d46, 0x97c7408d, 0x8007410a, 0x2bd5815b, ++ 0x37140533, 0x81b6747d, 0xf1abadf1, 0x5298f19d, 0xc8a39e20, 0xc8e78354, ++ 0x7223f545, 0xdb399d60, 0xd61132b0, 0xfdb112df, 0xf784571e, 0xaf81248b, ++ 0x6f50722f, 0x107c73e7, 0xde66aeda, 0xa21cc7f4, 0x1ab7cd17, 0xbc265f98, ++ 0xbb797bdd, 0x7ca7d1dd, 0xabbc81cb, 0x54e99dec, 0x715e78de, 0xffa45ea3, ++ 0x49d07465, 0xe4aa5fa5, 0xeda257ba, 0x411dd717, 0xd929c5ff, 0xdf67f43b, ++ 0xcf3b2fa2, 0x22749ccf, 0x2f2f3346, 0xe67e8169, 0x111de44f, 0x531f2dfb, ++ 0xf7fa7e3d, 0x443d0132, 0x9a5ad22e, 0xd6e6c071, 0xefb1d190, 0x9250df99, ++ 0xfd3ef40f, 0xf7dc34ea, 0x2b2e242d, 0x64d481f2, 0x2ce73ec0, 0xcd7c6031, ++ 0xeb27f259, 0x9e1f0d58, 0x33a41496, 0xd51d07dd, 0x83ee8f8e, 0x0fba7974, ++ 0xc90be5d2, 0x0710894d, 0x4c98f851, 0x4fce027c, 0x64a0fe57, 0x931776c3, ++ 0x6bb06aca, 0x7ce1ff54, 0x53fa911b, 0xdaf65ebd, 0x740519d3, 0x66251b1c, ++ 0xfae7ab0f, 0xef8ea84b, 0xeb8bcb4b, 0x5a4e2837, 0xec61ac7e, 0xd34354cd, ++ 0x10d57df7, 0x457de0df, 0x709738c0, 0xf1d77efa, 0xb5578f87, 0x17c53a97, ++ 0xd59471f0, 0x045f4e09, 0x78936d9c, 0x0f5f0d3c, 0x35bcc176, 0x843fa47e, ++ 0xcb0a3fe5, 0x7fcb089f, 0x4dee796f, 0x2a9cf274, 0xf800ffb9, 0x7d85f904, ++ 0x110520b2, 0xfdbbdfcf, 0x7fed4ea4, 0x3fb6a3f4, 0xb4672f40, 0x6a3f13fd, ++ 0x8d3b83fb, 0xfb523dbf, 0xf0bdaf65, 0x1597c42a, 0x95b8f4bf, 0xb4e33b50, ++ 0xa0e89354, 0xb4dd2ffc, 0x38380ada, 0x80ad7925, 0x713ed3e7, 0x3e822faa, ++ 0x78ab211b, 0xf0059a70, 0xb4afc273, 0x1f9b33fd, 0x2df601b8, 0x6d926e5f, ++ 0x33acbfe8, 0x4e548dfa, 0xe4961bcb, 0x3f985193, 0x9df7f2c2, 0xa8df2117, ++ 0x6ff167c7, 0x78844f1f, 0xfe948a1c, 0xfbd3f406, 0xbe503f71, 0x583cb3f1, ++ 0x10482bdf, 0x3dfc2ce5, 0x78ebffe8, 0x940a7f5c, 0xe8e5ced8, 0xf7844910, ++ 0xc3454fd9, 0x2b45e703, 0x049dd7a4, 0x7277427d, 0x7f0987e8, 0xf9db88af, ++ 0x6f4b64fd, 0xc81363d4, 0x2a63d004, 0xd98f885d, 0x7f9f2bf9, 0x3a11d472, ++ 0xbf8dd6ae, 0x7a1a0ab7, 0x5ed6f2a9, 0x3799e0bf, 0xcdeb5dec, 0xb51e5473, ++ 0x2ebaa4f6, 0xfef91bd8, 0xa5a589a4, 0xf10adfb2, 0x641ba553, 0x2e3e9787, ++ 0xdfb9e17d, 0xe3fe053c, 0x218e8d0f, 0x1792fdb4, 0x25707cf6, 0x956c97cd, ++ 0x69b3e77b, 0x0ec48598, 0x7fd054fe, 0xf074c7cb, 0x3de5f8a3, 0xc25dc40a, ++ 0x77c79ff3, 0xeb64a5f0, 0xec8c854e, 0xfaec8f4c, 0x1cc04a9d, 0x47f53f81, ++ 0x5adec0f2, 0x0a57fcf9, 0xef4ed4b8, 0x949f4810, 0xb0dcf408, 0xa031ed07, ++ 0xf393f213, 0xb0bfc42b, 0x2f9415fa, 0xf9c3d7a0, 0x9fef5e15, 0xbb40bf5c, ++ 0xf142d710, 0x101be2fd, 0xd191f677, 0x7a287401, 0xcc2b6ef1, 0xc954a4e7, ++ 0xeaf4fe70, 0xbfed2744, 0xda26f648, 0x8bcf6530, 0xc413fd7e, 0x3f03e2df, ++ 0x41fe6449, 0xae035f67, 0x30bede55, 0xb3b545cf, 0xc4859e71, 0x7a2c388d, ++ 0xbe81745a, 0x532242fc, 0x939046b7, 0x4e4e5c0d, 0x4b994b3e, 0xf61279e7, ++ 0xffdfa0e3, 0xe136fa24, 0xf42ee5be, 0xcf84fe3f, 0x986c5a85, 0xf8c4c2ff, ++ 0x5b321ff5, 0xef580837, 0xbc6efc5a, 0x74f805af, 0x0fb3a066, 0x1055739c, ++ 0x21e9cbc9, 0x8aeda25c, 0x30fb7207, 0x94bb113e, 0x76a3dfc1, 0x873c3657, ++ 0x33b22dfa, 0x3dee946a, 0xa3a52972, 0x7fbc65ff, 0xb068ee3a, 0x46264e97, ++ 0x10ffffb6, 0x5d7403d2, 0x234ce0d7, 0x37fe4cef, 0xaef265ae, 0xc6efbfca, ++ 0xf9fe50a9, 0xf0472641, 0x7497ac1e, 0x583efe5c, 0x809673be, 0xfc48c1fa, ++ 0xa37ce491, 0x5f5ce5cc, 0x3a178e1e, 0xd588497e, 0x89fa06e0, 0x3da03e47, ++ 0x7d18f855, 0x2b47a35f, 0xe76b5fa0, 0x5e395576, 0x2d41f5cc, 0x3bcb83e8, ++ 0x65a901f4, 0xbb6ba07a, 0x61fccbd6, 0x4f37efb2, 0x7952fc81, 0x7e41daf5, ++ 0xffcc1765, 0x7f765b6f, 0xdb951b70, 0x72abd5bf, 0xe1abd7ab, 0xedb45b72, ++ 0x1b5f1827, 0x1b7fb72e, 0xca224950, 0x511e7d2d, 0xfe04076e, 0x4aaaf447, ++ 0x74613dc7, 0x5764f554, 0x93d70cf4, 0x748ed96e, 0xf493d70d, 0xe8c920e7, ++ 0x8715478c, 0x7f8afe2a, 0xf4083657, 0x2aa70851, 0x5538430e, 0x6f3e1871, ++ 0xcbc31d3d, 0x1e5f041f, 0x2ebe579c, 0x694679e3, 0xa5bb8b13, 0x3fededef, ++ 0xc4e5e90e, 0xecd48e65, 0x9b5bdfed, 0xebe585f7, 0xc33beac3, 0xfab0aef2, ++ 0xa57cb0ee, 0xe3697eae, 0x0e20856e, 0xe27abafc, 0xc722fff2, 0xadc246c6, ++ 0x1a93ed8f, 0x57102bce, 0xe20e615e, 0xe20af2fb, 0xe0c47885, 0x69cf1176, ++ 0xab8d28da, 0x25b09fc1, 0x7aa5e7c5, 0xdb147564, 0x941307c7, 0x6d7bd06a, ++ 0x1e35a0b6, 0x3ecc51f2, 0xad05736e, 0xf33b1a71, 0x7a889348, 0x1c8be03b, ++ 0x16574f1f, 0x8ba073e4, 0xfcf579f8, 0x3ada2da9, 0x15cbfa0a, 0xc1cbc9cd, ++ 0x3a2353bf, 0x616948e0, 0x38562dd5, 0x4a6b6a07, 0x3e87319b, 0xc88ef45f, ++ 0x4ebc5cc2, 0x7f66afa9, 0x9f788a71, 0xbc402c98, 0xc9c43aed, 0xdfb62682, ++ 0x322eb858, 0x7bf98bee, 0x0a65e685, 0x4fba57e8, 0x473daa38, 0xaa29db51, ++ 0x34de7b0d, 0x0d47cb8d, 0x378babee, 0x7cddcbea, 0xe1423a5f, 0x3268c776, ++ 0x990bef9a, 0xe7eb845f, 0xc67d315c, 0xb687ca1c, 0xd231227d, 0x88937b7c, ++ 0x22df687c, 0x45afc0f8, 0x4fdc09bc, 0xf1b45419, 0x4720ade5, 0x57d6bac3, ++ 0x25fcafad, 0x978067e3, 0xf51e3f57, 0x7d6d345f, 0x6fa1c3f5, 0x43b5fe42, ++ 0xce931fc9, 0x4477b3f5, 0xdb7c39e1, 0xbce20b0e, 0xc97bfb6d, 0xebfc833f, ++ 0xb38c0746, 0xa357c76d, 0x2b6d3700, 0xefa0458c, 0xbf3206da, 0x5fedcae8, ++ 0x3ae00a8d, 0x37f90abb, 0xff98514b, 0x9f9fe9a6, 0xa521bd0a, 0x823b02b3, ++ 0xbc57abc7, 0xd823e511, 0xda1957fe, 0xe87e2def, 0xdc79ca7c, 0xcc859b45, ++ 0x8be306d9, 0x15057163, 0xae7a4e6f, 0xd65ff68a, 0x405953b0, 0xfadfb3cb, ++ 0xa7c61466, 0xd1f6636f, 0x6bf03939, 0x53b82b88, 0xa652b819, 0xc2073afc, ++ 0x23da8fd4, 0x906cbcca, 0xf974ce97, 0x3d54fd06, 0xff3dc7a5, 0x3821e86b, ++ 0xf8b39e99, 0xfbcc024c, 0x8c7e9fef, 0xe22345fe, 0xdfef9d52, 0x6ed0abea, ++ 0x8fde6ee9, 0xfebf6c2b, 0x05bcceff, 0xdde64f7f, 0xef3e6ff0, 0xe23b152b, ++ 0x3a0e5c31, 0x3dfb7ce3, 0xe2c17f98, 0x10f6f1c0, 0xcdff07ef, 0xf99dffe7, ++ 0xddf28dbe, 0x2fbcfdda, 0xbbcf9bfc, 0x33bfbe6b, 0x06ddf38f, 0x6f1594e7, ++ 0xfbe3837d, 0x97ae7aae, 0xfce77ff1, 0x68debb55, 0xd264b570, 0x3521cdf1, ++ 0x6e2c3016, 0x0fdf684d, 0x81c68ca1, 0xf186f79f, 0x96e761ca, 0x64639a6a, ++ 0x305927fb, 0xcc90bee0, 0x90bef816, 0xe06ea7ed, 0x030dc5f6, 0xbd7ed10a, ++ 0x7cecc9c1, 0x995cb922, 0x6f6e20e3, 0xa6fd03a1, 0x3761cc64, 0xe14f67e4, ++ 0xf2befd79, 0x0a71020f, 0x21bf8ed4, 0xb03eea79, 0x900c6767, 0x1e9646fc, ++ 0x2b7df481, 0xbf513e7f, 0xadd5b9ef, 0x4732dfcf, 0xdbcd9f9f, 0x2b8c19bb, ++ 0x2ecdffda, 0x527e07c1, 0x0963e079, 0x179537e0, 0x201044c9, 0x3572a77e, ++ 0xbb662fec, 0x0f83eff4, 0x1c57eb52, 0xc0127660, 0xd1edcc85, 0xe583b31c, ++ 0x3b08b807, 0x7d61f217, 0x7893b7a9, 0x89e23bd3, 0x4a0a9897, 0x34c39ce0, ++ 0xce3a405c, 0x1ea22758, 0x380ba532, 0x1944d72e, 0x333f47e3, 0x3f8032b8, ++ 0x942763f9, 0xc30d94ff, 0xc25a7401, 0x2a485ce9, 0x17224ed1, 0x9c9a5d2f, ++ 0x82657e01, 0x2712d676, 0xbee9d321, 0xe0b270a0, 0x2378868f, 0xc7637889, ++ 0x2055bf80, 0x56fe7547, 0xae7e1e7d, 0xa768ec4e, 0xe15dfabb, 0xff4ec7f8, ++ 0x28e6e54a, 0x811c9add, 0x2f760874, 0x7771f769, 0x563a3136, 0x54be0a94, ++ 0xd65fa3c4, 0x96f8f77e, 0xfc3b9d91, 0x5163e7f5, 0x397f331e, 0x2fed9632, ++ 0x64f7e1c7, 0x6d3edc15, 0xc163daf7, 0x94ded2af, 0xb2e3cfc6, 0x7208eead, ++ 0xebef8070, 0x65710cfe, 0x11cb6d34, 0x37d8446a, 0x13fa2090, 0x645139bd, ++ 0xc7b88453, 0x8e068c67, 0x67dc4a9f, 0xdf088fc2, 0x2c79f21f, 0xc6c6afa6, ++ 0x6eb6f86b, 0x546969fa, 0xcfc03e67, 0xcbf9cd51, 0xec2fa50f, 0x07ae8123, ++ 0xae7902a2, 0xcaddf308, 0xd77f3ee5, 0xc3fbf1df, 0x64529a9b, 0x394dcba0, ++ 0xf69ceea2, 0xffb72379, 0x30b192c7, 0xd75dfcae, 0x5f012759, 0xf80e89f6, ++ 0xe9a2b0de, 0x708ee2bc, 0x4f4e17fe, 0x19cf1f68, 0xd0214764, 0x5183d8f3, ++ 0xef69f604, 0x74a573f1, 0x474fc788, 0xfc1381d7, 0x99186f58, 0x64d629df, ++ 0xccce71c3, 0x681394cf, 0xb60de9bf, 0xd46a10d1, 0x358fd78f, 0x3fbcb1d9, ++ 0xd7ad4f7f, 0x3bd594af, 0x23cad8a2, 0x28daffcd, 0xc4c59f86, 0xe144cf71, ++ 0x996f8fdf, 0xb3f8b4bf, 0x51ca1d60, 0xb8e1edf7, 0xed1f2826, 0xac1f0553, ++ 0xc2efb013, 0xeb80be7c, 0x56067bd4, 0xe989bdee, 0xe1f71573, 0xd4693e74, ++ 0x346be77f, 0x72b7ba31, 0xace952f9, 0xbc7c37d2, 0xafaa7d6a, 0x3bfad1ae, ++ 0x7e8e3466, 0xf2d1d611, 0xa066c126, 0x014b954d, 0xa2b0e405, 0xfc1961f1, ++ 0x59dab7fd, 0x191d74bb, 0x8e3f3da5, 0xfcf3b135, 0x9aae63dd, 0xb0b93807, ++ 0xf433da8e, 0xf3c2e77d, 0xefc3d056, 0x847f1c19, 0x1fef2438, 0x5be9b244, ++ 0x1ec7d5f4, 0xac8e715b, 0xc705376d, 0x5334b339, 0xedccf706, 0x3ee53ba5, ++ 0x9ac53c1a, 0x7d5cb1e2, 0x8ed4afde, 0xfed3f7df, 0x87de1c70, 0x07be048c, ++ 0xc16faf48, 0xaf6f24ef, 0x2c38638c, 0x60a9dfaa, 0xabeb053e, 0x84fda9fd, ++ 0x7cacd3cb, 0x82e9bc7d, 0xa000c0ec, 0xbfd1be4b, 0xa70111cc, 0xff214cdb, ++ 0x275b77e6, 0xa3b7149c, 0x275a3ffe, 0x44eba996, 0xd59be300, 0xea6a7ff7, ++ 0x89f44eb4, 0xad2c4eb4, 0x3e01f7b2, 0xd69edd2c, 0xe9648407, 0x9189b93b, ++ 0x3df789d6, 0xc43866cc, 0x9b6e47bf, 0x2b89d745, 0xacc4eb34, 0xf849c428, ++ 0x39550b7b, 0x509d6ee9, 0x597ff6f9, 0xeb0fbcdf, 0xfef90444, 0x9d7e930f, ++ 0x00a9b9b8, 0x679b89d7, 0x6aefba89, 0x8fdc4dca, 0x913ae5da, 0xe62b7899, ++ 0x044c4765, 0xedcfbcfc, 0xae3c43e8, 0xf581fa1b, 0xffd005e2, 0x8dd79d09, ++ 0xccfaf4ae, 0xfff5ea9e, 0x7aab3a21, 0xb3b5297d, 0x7091298d, 0x4bcf1048, ++ 0x5d7aa56f, 0xbd323c00, 0xee0ef4be, 0xb3d30b4f, 0xe3b3d02e, 0xbd967ab4, ++ 0xeb66ee5f, 0xca634542, 0xf9697393, 0x03b2356d, 0x3adbca96, 0x56866ef4, ++ 0x7a00beef, 0xde822137, 0xf77a622d, 0xb458d342, 0xdf9aba9f, 0xa5beb85f, ++ 0x23b06cfa, 0xcce63e02, 0x777dd18d, 0xdbf46c75, 0xbc832fe9, 0xb9e227bc, ++ 0x0edc67e1, 0xedfa3fd8, 0xc74f6071, 0xe075b144, 0x39dfc710, 0xa1ce290f, ++ 0xc85ecbf4, 0x2db2e9ec, 0xbcafd222, 0x797fc981, 0xd3b3e09d, 0xbf98de7c, ++ 0xc95ff9e3, 0x47fe7676, 0xa99f9067, 0x7bc97fe1, 0x3bf06a81, 0xf0106c97, ++ 0xd6e212fc, 0x398b9e81, 0x251d0b3d, 0x8f09cfb8, 0x6d1b5863, 0x815c967d, ++ 0xb5dfa1ed, 0x37cfd78c, 0x9d8fd106, 0xb1c15bff, 0x778e7481, 0xfd7c1b28, ++ 0x949fd869, 0x773d85d4, 0x0a73c5ac, 0xec18c2f8, 0x7d7ab2da, 0x6f5cd7f9, ++ 0xe9fd122d, 0xecbec32f, 0xd223a28f, 0x0bd6a77a, 0x07e8a7d1, 0xa500e7d2, ++ 0x8f1fb8cf, 0x769a4b3e, 0xbbfa5fa2, 0x1e9c25d2, 0x3b7130ff, 0x07190c74, ++ 0xc199f8f2, 0xfbc5fa89, 0x2a7188ae, 0xa21e1f0b, 0x14c2cfbb, 0x9ef370c5, ++ 0x17dd5dc1, 0x78b395ea, 0x5bb5c596, 0xfcd224f7, 0x1a327adc, 0xd78bd9dc, ++ 0xd0e3d7eb, 0xc760dffa, 0xe56e7df5, 0x22e20156, 0xbdeff117, 0xe30f7c8a, ++ 0x2c771ffd, 0xad3deba7, 0xd18c60bf, 0x07afe70d, 0x3fa882a2, 0xe04efc55, ++ 0xf5cf1df8, 0xc17eb1d1, 0x1aa75c1c, 0xa5ca1b05, 0x5bad8a3f, 0x2f704f94, ++ 0x5f49eec9, 0x30be71e5, 0xe323463f, 0x1be50563, 0x135e75c8, 0x7b33d7cf, ++ 0xf3a6f6f0, 0x69acdcec, 0x37eecca7, 0xd42f4811, 0x77dc0e77, 0x9c23ebab, ++ 0x6a2665e3, 0x08fdbbf8, 0xc126ffc3, 0xf47c0f81, 0xdfc21fbf, 0xdaaaf82e, ++ 0xafe53d33, 0x5109a74a, 0x881f3e7a, 0x8b1fc96a, 0x03823ce7, 0x8a697bef, ++ 0xe38973c3, 0x92feec35, 0x70e7ce5c, 0x87fd80b9, 0x1b953ef6, 0xd710e061, ++ 0xe30a353a, 0x54dfb102, 0xf5699f66, 0x39fbe854, 0x38d77e9e, 0x82d20a98, ++ 0xfc475976, 0x11b77b9a, 0x82a9b7ec, 0x0b2b8fa4, 0x08ffdca2, 0xe9a7ffed, ++ 0x4927da5b, 0xee5f5c26, 0xbba7b1b6, 0xee042a07, 0x46b0ba31, 0x62dd1c46, ++ 0x19307fb0, 0x32fdcbf4, 0xb0b8f901, 0xb9a1fc7f, 0x445ca1bd, 0x37bc147c, ++ 0x2b5c1cb6, 0x89f62c05, 0xd6cbdc14, 0xffbc63a5, 0xed7ae88f, 0x04bbc61c, ++ 0xe713d83b, 0x6703ef83, 0xdae67639, 0xee32dfc1, 0x57386ac0, 0xfb6d999b, ++ 0xe3e003e0, 0xcf6f765a, 0xb8d935d1, 0x2efbbb4f, 0x30ece501, 0x33b417e5, ++ 0x07ca567b, 0xddf1d01f, 0xcf0126b1, 0x133ae6c7, 0xb2f3866e, 0x8745fbb9, ++ 0x305bd69d, 0xf38662c3, 0x45c369b5, 0xe5d0d6e2, 0xfe82d20e, 0x7795b99d, ++ 0x293906cd, 0xdc21eba2, 0x74d453c7, 0xe40fb720, 0xbf7c056b, 0xe056ebc2, ++ 0xf596bd3b, 0xb47195e7, 0x0f5a42ff, 0xcb515dc8, 0x146c55ea, 0xc2afdef0, ++ 0x4f5187a6, 0xf0146e16, 0x6a169342, 0xbb589aff, 0xb44ad83e, 0x69f7d2d4, ++ 0x0fbc317e, 0xbb8c6eed, 0x2ac1ce19, 0xfdf138e8, 0xee785589, 0xa3df4859, ++ 0xe365a4c5, 0x92ded85d, 0x77c0815a, 0x53134561, 0xed089a1e, 0x501d97ed, ++ 0xafe7687e, 0x3cf71814, 0xda5f5fda, 0x903102fe, 0x9fb8fe8b, 0x37bc3609, ++ 0xe50c31c7, 0x1dcb8dba, 0x93087cf9, 0xdfa88173, 0xf8da4967, 0xb146bf87, ++ 0xe5c2f5f8, 0xaf30d555, 0xc5213780, 0xaf3a7880, 0x9c7e3ac0, 0xed4ddbd2, ++ 0x8b0a63d7, 0x3dedd8ab, 0xfa3404a6, 0x1a5462f3, 0x31b0bfbe, 0x22ccf513, ++ 0x79f3c2e2, 0x47b31577, 0xf28eac8e, 0xc9876009, 0xbe7864b6, 0x9f11b57b, ++ 0xad817b9f, 0x0606e73b, 0xb27a8fd0, 0xddf02656, 0xb4dacada, 0x278f8027, ++ 0xf00ec8b7, 0xb34f8b4f, 0x2fc5e973, 0xeed93f30, 0xc9eed65a, 0xb2dfa63a, ++ 0x079d9e9f, 0xd5317b7a, 0x9f9c4653, 0xda158f5e, 0x3d4f518b, 0x52f4c51d, ++ 0xd70abeb8, 0x1b354553, 0xcb43af22, 0x43af22f2, 0x9f99aa03, 0xb9f58bb3, ++ 0x3d559882, 0x56e20635, 0xce06ca0a, 0xbe780f5b, 0xb78c0583, 0xe2ff5ff8, ++ 0x4b775871, 0x54cf782d, 0x427b64b9, 0xa020f860, 0x6d36e7ff, 0xa1e402fd, ++ 0xde146e68, 0xf8027523, 0xaeb47201, 0x16979e17, 0xee900afa, 0xe2e75c6a, ++ 0xabbc7af5, 0xdd5bc87e, 0xd76a7122, 0xe218a2af, 0xf43bd4d4, 0xda5b8a0b, ++ 0x828d9dcf, 0xa1e5540f, 0xfbd91c5f, 0xb7987193, 0x7396b8e1, 0x059d60fb, ++ 0xdee87d71, 0xb701abf3, 0x102e7ef3, 0xd789dbb0, 0x61eb0d5d, 0x0ec17af9, ++ 0x3fc5dd7e, 0xa62fef67, 0x0fb8c3ef, 0x8be18afd, 0x720edce2, 0xf0fb5e50, ++ 0x51bfac5e, 0x87fb43b0, 0x3da01436, 0x0915e451, 0x823c6f96, 0x5eba08fb, ++ 0x6ed37c61, 0x720898af, 0x68cabe50, 0x8aac5703, 0x479f1527, 0x312b3c78, ++ 0xa4cd4639, 0x830f3def, 0x714b808a, 0x4f5a108e, 0x5e153f01, 0x2f23b786, ++ 0x91100ec8, 0xbec9f1ee, 0x27f15683, 0x75c6fe02, 0x6d776fe0, 0x3c7802b6, ++ 0x3cf013e9, 0x0bf01b3f, 0xf55e7cf8, 0xd6b310cf, 0x9f0eea8e, 0x84ec38e1, ++ 0x28d9b83f, 0x2a9f03ad, 0x7871c31e, 0xc3372254, 0x1d5eefb8, 0xaec8f385, ++ 0xe5e6fd7e, 0x1cf0ce4c, 0xdefabb28, 0x42eb9044, 0xa895c589, 0x58932d74, ++ 0x71a7521c, 0xf4a5563d, 0xc2f8c9ed, 0x8a3fb1c6, 0x1e40ffef, 0xe3271644, ++ 0xbdbcfda7, 0xd78c39e5, 0xc8f9bb3b, 0xbcdf680d, 0xf4007149, 0x7e2162df, ++ 0x50f887dc, 0x8837151f, 0x94678c4e, 0x353319fc, 0xee3577fb, 0x0b25e4a2, ++ 0x9b78bbd2, 0xdf4f97d1, 0xd8f57e2f, 0x5eff3c28, 0xef6fecc1, 0x63ed0166, ++ 0x828c0de2, 0x258a46ef, 0x6e11ff16, 0xcd1b5c17, 0xc7af5bfd, 0x4dbb01cc, ++ 0xc3f763a8, 0x22dfd715, 0xddfe351b, 0xb565a3ab, 0x78c79e1e, 0xfbe19f29, ++ 0xf69f1878, 0xee35327e, 0x8679f5a3, 0x1946e2bf, 0xbae2b9ed, 0xfe20e7ad, ++ 0x11b0f8af, 0x7515bbf7, 0x39be31e7, 0xd817a5fb, 0xa28d763d, 0x53abee2e, ++ 0x889d55bc, 0x0de523e7, 0x41ff1865, 0x524e78f3, 0x9be3cf5e, 0x503c63be, ++ 0x5fdb4bc9, 0x961252f5, 0x2b5bfcbc, 0xb2d737de, 0xbbdf8ac9, 0xfc7b7dd4, ++ 0xaaf8a763, 0xbe3cb5fa, 0x8249fa6a, 0x7c7231fa, 0x85f819d5, 0xe8aee902, ++ 0x3ab538b0, 0x38e8dfa6, 0x63dd2233, 0x5ebbb218, 0x10d7e2f8, 0xedbadc1f, ++ 0x7186bf6f, 0xc2ebfe97, 0x839e21af, 0x81b288ec, 0xf9b1529d, 0x54a78c7d, ++ 0x9a207bdf, 0xff9e83ef, 0x9ea3c62d, 0x80e8d0fb, 0x3f6dced6, 0xc7f60c99, ++ 0x4f7fadb9, 0x65d33884, 0xbfd173db, 0x6c95ecb3, 0xabb2b7bc, 0xd7e02cfd, ++ 0xd87883d7, 0x6eedbe70, 0x27718dd8, 0x41df2967, 0xe6e2844f, 0x3c58cbea, ++ 0xcbc79da2, 0x7f1c896d, 0xae3e29dc, 0x298ce661, 0x981b1fa0, 0x9c6dd09d, ++ 0xcfca41dc, 0xc7c07a2b, 0xb21e3c2d, 0xc6b7fa7e, 0x5f859dc9, 0x8736bf28, ++ 0x868bf1f1, 0x053ccf45, 0xbabd0d65, 0xf7f3938c, 0x7c6a7e80, 0xced13df3, ++ 0xde41a257, 0xe30efdb6, 0xf97f8113, 0x5fd7d076, 0xf8bf8324, 0xbf441c94, ++ 0x11bb7044, 0xde2bb7bf, 0xe9e5087e, 0x30072bdc, 0x38f0987e, 0xf42473e3, ++ 0xb941e2c3, 0xa362a80f, 0x71d7c585, 0x9dfc403e, 0x79cf8add, 0xb5c31d9c, ++ 0x55d77f1a, 0x68d9dddc, 0x1a9a9df6, 0xf1b65d77, 0xd6cf1e63, 0x226137c1, ++ 0xb7c8ebf0, 0x74aa35c6, 0x261d01b0, 0x234ae368, 0xe28639c7, 0x06f8c34a, ++ 0x1e3d04fc, 0xf9a51b8a, 0xe83f1001, 0x8a450e13, 0x81b73e53, 0x939ea3c5, ++ 0xaadf7f23, 0x0a9e99c6, 0xcf5f5b97, 0x9bbb4be2, 0xd3a577c7, 0x2ebb68e1, ++ 0x57a552be, 0xfac8c5eb, 0xf846263d, 0x956bdf61, 0x47dfe10a, 0x878cc744, ++ 0x0a23f873, 0xeea173de, 0x5b7cf8ab, 0x75adbfb9, 0x877188b3, 0x51bbf5d5, ++ 0x8feb87bf, 0x128e7e72, 0x3181de3e, 0xde5aff6c, 0xd68fd6c8, 0x999f166d, ++ 0xebbad3b6, 0xf975c475, 0xf7182396, 0x65eeb7b8, 0x7f39a025, 0xa7c3f586, ++ 0x8beb7f19, 0x3ea1473b, 0x855af7e7, 0xef3973f7, 0x7229a2a7, 0xce5b153f, ++ 0xf129faeb, 0x73362bd6, 0x919dfdf7, 0x7b40b79c, 0x1d985a67, 0x9c5ea675, ++ 0x1dfbe91a, 0xcfcc8c6b, 0x4a586a31, 0xdfbc51d7, 0xf3eec2cb, 0x68d1ad12, ++ 0x4cb32d97, 0x48f70c3c, 0x1828b32e, 0x8ab2b17f, 0xc2fc6bc7, 0x5efc0491, ++ 0xc09eb969, 0x7d035778, 0xd97bfb35, 0xcf6026e6, 0x71ae49c9, 0x751873da, ++ 0x036f4afc, 0xbff869f1, 0x0fb532cc, 0xe4894fec, 0xb8e3001d, 0x092bf521, ++ 0x0f16c5d6, 0x78b8098f, 0x6f3c306c, 0x7a7b6c91, 0x725b76d1, 0x66b80704, ++ 0xa7dee33b, 0xe8dc3ff3, 0x0a83dfd4, 0xbf30fe31, 0xed018776, 0x6fc18b44, ++ 0x258855a3, 0x370925aa, 0x976276b8, 0x1f343112, 0xf7efe3e3, 0xf7c30698, ++ 0xcd42567d, 0x90e7a856, 0xc462f774, 0xeec2944e, 0x070720c9, 0x399abc53, ++ 0x9d7f555e, 0xdb4efd85, 0x1bfde00d, 0x0aa4e971, 0xe2cebbe0, 0x51e27b46, ++ 0x5fbf13ab, 0x21c33fa3, 0x449e224e, 0xfaf7b43b, 0xf7757ed0, 0x757ed081, ++ 0x3ea738f9, 0x74aa6bdf, 0xd37ad23c, 0x4f238f8b, 0xe21d2334, 0x5edc0d72, ++ 0x490fe676, 0x5c7718ec, 0xa1f87102, 0xe319ba7c, 0x7978a9d2, 0x9b30f3b5, ++ 0xe3a6e3f5, 0xd889e9d3, 0xc0d780f4, 0x6e7ba9c6, 0xd7bc7623, 0x68f78e98, ++ 0xf97578d8, 0xefae18ea, 0xbe812224, 0x085a9b33, 0x8ebb7fa7, 0x5724abde, ++ 0x4b61227c, 0x0e938c26, 0x886fbe13, 0xfda0f3e5, 0xc0dbeaeb, 0xd7fac07b, ++ 0xd80643b7, 0x5e25dfb4, 0x19c1d7c1, 0x3193d766, 0x0c64af54, 0xe100c4aa, ++ 0xf38249c9, 0xd65a58f8, 0x7bf99bd4, 0x5c636796, 0x70c3508a, 0x411d7835, ++ 0x641c19b9, 0x55642ff1, 0x46a9da34, 0x8d46f113, 0x88adef81, 0xbd031e57, ++ 0xd9fcb8f8, 0x53681857, 0x358a1ad2, 0x30535efa, 0x3288b0cb, 0x688a1ea1, ++ 0x38c58ffb, 0xaefa037f, 0x927746fa, 0xfc3c3461, 0x00f37568, 0xe011da94, ++ 0x1f083431, 0x9037d9ee, 0xbdc10a85, 0xb87c840e, 0x135e3007, 0x7c3f13ca, ++ 0x1d135df7, 0x544d3bca, 0xb2a4d7df, 0x87cc437c, 0x11fee1ab, 0x00d5cd97, ++ 0xed9310fd, 0xf30f3c32, 0xbaad7bb3, 0x71d45f5b, 0xc818df0e, 0xfcc71e8b, ++ 0xecff70a9, 0x3be84b10, 0x378f5c6c, 0x1fbcd599, 0x86ae17f7, 0xcad7a803, ++ 0xb9600fea, 0x1d34f201, 0xd7902bd4, 0x3f908e3f, 0x373a703f, 0xb5d80469, ++ 0x3a064905, 0x381e4fcf, 0x5bbe07bd, 0xb9c3a0eb, 0x3b93cdd5, 0x5a1920e8, ++ 0xfad0e8c3, 0x49f0e89d, 0xb86aeb4c, 0xf3a7a31f, 0x18f8b8a6, 0xd32d35e8, ++ 0x4d70f780, 0xff466c38, 0xc289fd0b, 0xb3b788f5, 0x74ef8ba1, 0x6d0a7dd5, ++ 0x5f1698e7, 0xae2a7bea, 0x1a4dc2ba, 0xeec65db1, 0xa7e3d477, 0x0ad9d9b7, ++ 0x718d9ded, 0x8092cafe, 0xc2efc7f3, 0x5c0bb9a7, 0x703abd39, 0xb1eecc4d, ++ 0xffa05937, 0x7d405ff9, 0x32d35c75, 0x74a98a97, 0x2c825fbc, 0x27cc7424, ++ 0x6a37b961, 0x82679d28, 0xdbf180d3, 0x7feecc33, 0x39d67bc2, 0x8f553f41, ++ 0x8f7004d4, 0x7e8ec415, 0xdea8f954, 0xd5f1f6ce, 0x0adf0605, 0xf78c1e76, ++ 0x23e077ef, 0x208f8610, 0x11e347c3, 0xd37947c4, 0xc68f8611, 0x7e68acaa, ++ 0xe8fb06ae, 0x0d1c121a, 0x675b8f7c, 0xdf2893ca, 0xab04c507, 0xc85c53fb, ++ 0x8fcbc944, 0x9ac6ba42, 0x87f02213, 0x579d4b8f, 0xd9adfc57, 0x3a40fa97, ++ 0x1bf733ec, 0xa54c3cf0, 0xc32f5a9b, 0x4f13e2cc, 0xa003dc58, 0x81898a9f, ++ 0x6dbec0bd, 0x7184fefb, 0x37fdd61d, 0xadf784ed, 0xec8728b3, 0xecd6fd1d, ++ 0x3cf7815f, 0x7bb134d7, 0xd0496397, 0xd77aeb0b, 0x13f260f4, 0x3dd807a2, ++ 0x238f40e9, 0xf99b2f28, 0xee544b77, 0x41dd3bf0, 0x891eec31, 0x8e2ccc2b, ++ 0xb22cdb24, 0xb3334538, 0xb7f61237, 0xaaffb02b, 0xfac06558, 0x6ba69009, ++ 0xbf8abfe7, 0xf0e2e927, 0x78aabe54, 0x06349aa2, 0xc4b0a3ee, 0x759b27bb, ++ 0x498f89f8, 0xbea7b4d5, 0xb88790f7, 0x4ca05216, 0x377f9e68, 0x3f14abac, ++ 0x759acd7d, 0x3948da7a, 0xc216e80a, 0x2467c50f, 0xaef7d0fe, 0xfd678f37, ++ 0xb5b0bd80, 0xf788a979, 0xaf90f42a, 0x209f7019, 0x43119fad, 0xf7d1b72a, ++ 0x0a696233, 0xdf3c5ef9, 0xb3fbe787, 0x8713ed34, 0x37cfa041, 0x7cecbf70, ++ 0xd922574e, 0x2469bb2e, 0x275d19e4, 0xbae0c527, 0x5c2dcaa0, 0xdae70183, ++ 0x4edf3f12, 0x801aa60d, 0x4b1caa6f, 0x62df8341, 0x0c077bc5, 0xaef0e710, ++ 0xf382edc7, 0xcef4aec2, 0x77d823f5, 0xefcfe185, 0xdef9e3e1, 0x9de7f5f6, ++ 0x07be3fbe, 0x0a665be8, 0xcd13743c, 0x80b88f97, 0x3115da7e, 0xdb7d57e5, ++ 0xe3e1083d, 0x49e2f77f, 0xe787d82b, 0x8d4e36be, 0x366f6764, 0x3ec17db3, ++ 0x2f7c1ccf, 0x46f3df83, 0xaef1a8fa, 0xa117ef9a, 0xc865db8c, 0x8e7c54ca, ++ 0xa8d5d676, 0x5e9f8102, 0x8fde1e29, 0xc573c149, 0x63bec26b, 0xaecbcf54, ++ 0x603f33f6, 0x1f2fac46, 0x0d3cbbfb, 0xd7c908e3, 0xd1325ecc, 0x2a1ce0ff, ++ 0x399b9f97, 0x619adb0f, 0x55e8cc39, 0xc7ed8393, 0x2b5fa0a6, 0x67efe893, ++ 0x95e3e8cb, 0x969e500c, 0x9b65ed82, 0x08d3cac2, 0xb0c8adfa, 0xb97e70cb, ++ 0xe19f6344, 0x00e351ba, 0x386d3c7d, 0x7e7f3fc5, 0x641bfe81, 0xa8de7724, ++ 0x675c67d9, 0xa395d5bf, 0xf06a5bb3, 0x7fdf985e, 0x2919de23, 0x30b442fe, ++ 0xb8f3ee7c, 0x100f105c, 0xbb2cc74e, 0xef62cab0, 0xfa70ef4c, 0xa55bd385, ++ 0x32dd3863, 0xc4e4713f, 0x27d33bdb, 0xe71d1e9c, 0xc075be97, 0x22e1dc87, ++ 0xdd2a5fae, 0xf187d33b, 0x6823f7eb, 0x42f0013d, 0x4cf40de9, 0x47be3013, ++ 0xf9736fb5, 0x8b7da8f8, 0x82766bf6, 0xe13efd05, 0x474ced74, 0x626e7e67, ++ 0x02f6fcc7, 0x9ea086bd, 0x4d8cb860, 0xc465be43, 0x7c420e3a, 0xc21d8919, ++ 0x86bfe370, 0x5e3fe368, 0x2c72ff02, 0x29ef070e, 0x117586bc, 0x5f35d7a2, ++ 0xdcdcedeb, 0x60d3bca6, 0xaaf4673f, 0x7e838e6c, 0x79bf0c8c, 0x34e9ff7c, ++ 0x4a41f8b1, 0xbc7aa3cf, 0xf4ec6611, 0xbc71f14a, 0xbc56fd1d, 0xfdf7c2d9, ++ 0x74e16f0c, 0x12f6f150, 0x99d4983c, 0xfede2a6e, 0x79f6e661, 0xec00323f, ++ 0x8faf51e5, 0x4dfd058b, 0xfa23e29a, 0x761c2625, 0xfde1da85, 0xe2052e23, ++ 0xa5b73d0e, 0xb63d00fd, 0x1a92ae9f, 0xb92b163d, 0xf4112d63, 0x29938a98, ++ 0x88535f9c, 0x99f82777, 0xf3e910a6, 0xa5207ed0, 0x2c7dfe63, 0x3fbbfcfc, ++ 0xfcf30fe9, 0xd99db30f, 0xa19e7c45, 0x12f35379, 0xfbcc9ffa, 0xe3326c9f, ++ 0x28241e77, 0x9ee886b5, 0x78dff78a, 0x718ef895, 0x493ebcc8, 0x9ecc24ae, ++ 0x1ff78b9b, 0x4b90ba53, 0x48e31d31, 0xde1208b7, 0x71c7c2ff, 0x85e4ceb6, ++ 0x92d9b738, 0x6cf301db, 0xc28ff615, 0xa1fe49f9, 0x9785feb0, 0x2e6c685f, ++ 0xaf5a7287, 0xf1f1eb10, 0x670c8897, 0xdf46edc1, 0xdb5d29b3, 0x71bc54a9, ++ 0x63e5509d, 0x79577c32, 0x505bc805, 0xf1377184, 0xe71d9573, 0xe85f708b, ++ 0x9755b624, 0xb4f6f6d3, 0x00f7e1e7, 0x40ed54d9, 0x87fc70bd, 0xc71c3ae3, ++ 0x0f382439, 0x5f8cebde, 0x2bf2f7ef, 0x085c76a9, 0xb8f50737, 0xf142f151, ++ 0xcfd80b73, 0x7b3ee36d, 0xf7eecc02, 0x84485dc6, 0xd3b54ff5, 0xe711ec3b, ++ 0x2baf506d, 0xd3b55d7b, 0x05dc5b17, 0xe60907c0, 0x1d4fdf43, 0x77c0376e, ++ 0x9c5b8ffa, 0x6ab9e1f3, 0xefb774bf, 0x1912cd20, 0x877f019e, 0xdea1f188, ++ 0x607ef040, 0xef0152ef, 0x0483bec7, 0x8eefe865, 0xbfb7594a, 0xfc15179d, ++ 0x8e7067f4, 0xe30c3558, 0xd5f0dc88, 0xb3ef88a8, 0xbe6ae4b8, 0x0e0f0eee, ++ 0x9ddffd85, 0x13eff5cb, 0xc7627dc0, 0xd29fab3d, 0xa1e37dba, 0x7c0240dd, ++ 0xd5e05bc7, 0x5fef0fd7, 0xbb78479d, 0xf055efe1, 0xf704fbbf, 0x76343b5c, ++ 0x3b0b4ac3, 0xf78d0a27, 0x025f7e5d, 0xbbac37a5, 0x7c234ded, 0xafc047f7, ++ 0xfd4dba9a, 0x7ee6929d, 0xe376c0ad, 0x98f7489c, 0xf4a8fda8, 0x545a4b9e, ++ 0x1223fe7a, 0x99bb26fe, 0x98f0c03f, 0xaf5e775f, 0x398383a6, 0xae0df768, ++ 0x2eced017, 0x2c34cfad, 0x6cfbd9d0, 0xdec9dc3f, 0xa0357b87, 0x664ec37e, ++ 0xe157d7ef, 0x81b4a1be, 0xc0367fed, 0xf8fd11bd, 0x1f71d240, 0x42d7da10, ++ 0xdc1954fc, 0xfdcac863, 0x5a55b570, 0xb6ffab0d, 0xad6553e5, 0x7752fb04, ++ 0xf91cdc12, 0xaac783f6, 0x54ff744d, 0x08a2429d, 0x79ed3fdd, 0xbade58f0, ++ 0xc73b5489, 0x37b8053b, 0xcdabe692, 0x8fbe7a93, 0xa3c1fb7e, 0xa68fb0d5, ++ 0x801daffb, 0xba5e556b, 0x307a8f92, 0xdeba123e, 0xae6cbacf, 0x54be41b7, ++ 0xff3844bf, 0x58f64ddb, 0xbe5adfc0, 0xf97ebecf, 0x443fdc02, 0x0c98bb0d, ++ 0x39936271, 0x3b720fdf, 0x7d8622a8, 0x93115e0f, 0xf53d03ec, 0x083ee8b5, ++ 0x75db6ce3, 0x93f82871, 0x0c7e1ddf, 0xfc4d6ff7, 0x9efdc9be, 0x6e369722, ++ 0x1f1caffd, 0x6dd88fd7, 0xf4c7fd85, 0xefc67ff1, 0xec4acfd4, 0x89d6b5fe, ++ 0xbddece8a, 0x57fb92ce, 0x529abf18, 0x9fa089f2, 0x3e6b8f27, 0x577eeb0c, ++ 0x3ac744eb, 0x1d6014e0, 0x240f1720, 0xc35079e2, 0x35f82b1e, 0xef77f95a, ++ 0x27761b67, 0xd969a7ce, 0x615b3fd6, 0xf3e415df, 0xe0b52b3c, 0xafa53d7d, ++ 0x049f7888, 0x76f137ed, 0x2c3733f0, 0x759fb8c8, 0x83aed263, 0xddd9be63, ++ 0x7f9cc5df, 0x6a883f78, 0x79314e1f, 0xa6be307d, 0xe777f62a, 0xbf9090a6, ++ 0xb915ef13, 0x467441a6, 0x8bdb3b59, 0x72e6558a, 0xa778c764, 0x4fd63665, ++ 0xf939f257, 0xa7c45eeb, 0xb2606fb9, 0xfc6117e4, 0xc44ebf93, 0xa5f767e7, ++ 0x7c0f9a3e, 0x0863b227, 0x66912b34, 0x79f947b4, 0x8669fd12, 0xf077a67b, ++ 0x170d5bcc, 0x60855e66, 0x0090eba5, 0x37bb97f6, 0x7d321273, 0xd789daaf, ++ 0x93f7ad7c, 0xeaaddb86, 0x34d596ba, 0x027f557a, 0xc4cfb774, 0x49f61def, ++ 0x6e159f18, 0xf306e6d7, 0x1f5fb0ba, 0x6b6c7a46, 0xbc018b48, 0xafb8e09c, ++ 0xf780b868, 0xff1394c7, 0x4f8f70cd, 0xf3688379, 0x1a2b8813, 0x8dc83977, ++ 0x74abfeba, 0xdbb8bc69, 0x6cfc0a34, 0x15b68baf, 0x0be9af50, 0x3fd8e1c4, ++ 0xe9f5c45e, 0xf78c935c, 0xff6c54a7, 0xb340bacc, 0xc4d7381f, 0x6b6955ee, ++ 0xde7fa63a, 0x7872ebd8, 0xed81ab6f, 0xfef79b6f, 0xcef40623, 0x7bdb175b, ++ 0x5d5abee1, 0xd7db3bff, 0x5b671768, 0x58ff90c4, 0x71133f6b, 0xcf8841f2, ++ 0x89958dca, 0xff6d7428, 0x56427e66, 0x3b674859, 0xe2774420, 0xe10e8094, ++ 0xce884176, 0x74c17661, 0x06d7b72b, 0xcf703192, 0x5ec5e360, 0x6a3df825, ++ 0x056d8c53, 0xdd987ffa, 0xe67cd6d3, 0x7cf06991, 0x23eec8bf, 0x3ca228b8, ++ 0x3251daed, 0x0fa1a028, 0xa7c88cd5, 0x3f9efb2f, 0xffad26f7, 0xe6689ee5, ++ 0x971c970f, 0xe86bbf6b, 0xf4e3efa8, 0xe763f7f2, 0x707ede6a, 0xb6f7d05f, ++ 0xed3b5b6b, 0x68ad8bcf, 0x40f306d7, 0x3dad0fbd, 0x4fff00a2, 0x56a55c58, ++ 0x18fab794, 0x925e2fd0, 0x7ed09fd5, 0x1649a28b, 0x45582ae0, 0xf7e7106c, ++ 0x01833eca, 0x536e32f8, 0x6ce1c60a, 0x4b8ee7e6, 0x14946bea, 0xc25ade8d, ++ 0xc94eadcf, 0xcd78e4de, 0xdb2b76f3, 0x53da9fb7, 0xe1ea0cfc, 0x48648d0f, ++ 0x4ff77584, 0x7897e656, 0xdb4ef159, 0x1a8ef502, 0xe6a0fbf0, 0x85ec6fbd, ++ 0x1c976a7b, 0x75868fb6, 0x8ed58b6c, 0x6ff71af5, 0x1aee7bc6, 0xdde8213f, ++ 0x2058d8cd, 0x6fbf681a, 0xc3f33b12, 0x177f641d, 0x24bfe431, 0xcf305ece, ++ 0xdf4cade7, 0xa0cfb9bd, 0x937ae73b, 0x14faa7df, 0x563543d7, 0xb6db07e6, ++ 0xde17ab2f, 0x3f716b2b, 0x38aaf40a, 0x2186a81e, 0xd53b7ea8, 0x70749b0e, ++ 0xf491b4db, 0x06ad49d7, 0x7edbb01b, 0xe61159f0, 0x48453f6b, 0xd93a409c, ++ 0xa7bdb465, 0x7b6a2f81, 0xf6b2b66f, 0x817638e8, 0xa7f4aabc, 0xe903da2b, ++ 0x8b66ff34, 0x5bf10f14, 0x79d5fd2a, 0xebdbfda8, 0x19837389, 0xedb9c945, ++ 0xeac7fc5b, 0x6d63f7fd, 0x1f0fbd44, 0xead83971, 0xfccac17c, 0x3f90c977, ++ 0xed1a27b5, 0x3af9979d, 0x060a9249, 0x3e54fd01, 0xd6cac1fd, 0x5d3c7535, ++ 0x1f0efff5, 0x577e9aa7, 0xed966f5c, 0xbf0dc45e, 0xf5eed0cf, 0x4e20d29b, ++ 0xff0d31ac, 0x8e26901e, 0xff1c1df6, 0x75fdfd29, 0x0183018d, 0xdf2af7be, ++ 0xf5e1c42e, 0x9bb43d27, 0xea933843, 0x878d7f11, 0x7171ca09, 0x7fcc5ddd, ++ 0xf9fdfc48, 0x1e785ebd, 0xcfc3f20e, 0x340afbc5, 0x61b4d49d, 0xafa47f65, ++ 0xd5720adf, 0x372a2741, 0x28d65690, 0xcb25d780, 0x9f98ba58, 0xef592f2f, ++ 0xac2cf946, 0xc783f165, 0x7d6c29ac, 0x862578e6, 0x57107ee8, 0x5fd38f32, ++ 0xc731771d, 0x4786e9ed, 0x14bf4377, 0x1e81a75f, 0xfc3e3657, 0xc5570c04, ++ 0x328de9eb, 0xad1453b6, 0xc73f7f3f, 0x41cafaf9, 0x1b49f786, 0x4fb82ce5, ++ 0xd897926a, 0xe6fd1fc0, 0xe8224dc6, 0xcf0137ef, 0x61ce4c29, 0xe7b53dbd, ++ 0xc29f98fe, 0x40c476fa, 0xb2fdefc0, 0x6ab68a42, 0xc379a2e4, 0x2df93a6b, ++ 0x869aabae, 0xbc40f5fe, 0x955e7a00, 0x2fee955b, 0x50eb8e2b, 0x93086ffe, ++ 0x7ef61cff, 0xcbe32c5a, 0x1ffe5ca3, 0x9fe54a9d, 0x18db8a3e, 0x2f3b4027, ++ 0x19ef912b, 0x7efd884b, 0xd5e90bf8, 0x9abd2740, 0x05fccb10, 0x7fda34d6, ++ 0xf476f4f9, 0xc7c68417, 0x8e68f371, 0x01149b8a, 0x39435fe8, 0x45e81838, ++ 0xa6780ae9, 0x379df176, 0xee54a3a5, 0x86bcf093, 0x38f1079f, 0x8d28940e, ++ 0x33e876bc, 0x43dd6e55, 0x39191c61, 0x6ec12b95, 0x45ef95ef, 0xdc169e7c, ++ 0x7ae9e283, 0x38e41a76, 0x63903e82, 0x52fe5e99, 0x9f777776, 0x73c03f7a, ++ 0xc201dd11, 0x60ad487c, 0xe5a8be03, 0x4fb65af6, 0x55f4e6c9, 0x50ff679f, ++ 0xdd3b077a, 0xe8cd9943, 0x0e20541d, 0xad8fa875, 0x42c84463, 0xeb862079, ++ 0x2d9c81fb, 0x6dd7eba1, 0xb4ebf59a, 0x5538835c, 0x963d30e9, 0x7197cdc9, ++ 0xf0dfde6c, 0xf072e9f5, 0xd0d78dc1, 0x8124905f, 0x3028b3c9, 0xfda11739, ++ 0xbcae7bd3, 0x3d3ef10e, 0xb06dde32, 0xbf878a7f, 0xf101b3d7, 0x86d53719, ++ 0x2a3ca9df, 0x74e2a239, 0xd30f91f6, 0xe24f4de6, 0x0bf00dbe, 0xfe15def2, ++ 0x24ff008b, 0x147dee02, 0xa9fe1af7, 0x58b8a038, 0x0fd1ab12, 0xcf50b8e1, ++ 0xbcba550d, 0xd8ee761c, 0xc554e9c0, 0xf1177b53, 0xbe7cea2f, 0x754f9f37, ++ 0x5c37b3e2, 0xaadf80ae, 0xf204587e, 0x7cb5d095, 0xb1b58b1d, 0x97f733bf, ++ 0x526f1805, 0xea9fcfc3, 0xb8ea7f79, 0xecf8e11f, 0x8668fcea, 0xac70fdd9, ++ 0x7329bcf6, 0xef4f68a9, 0xb72e47c0, 0x326e9767, 0x56fdf9e2, 0x35be0128, ++ 0xdfb4fb47, 0x6a24da8f, 0x6f525290, 0x71c14d88, 0x2fb0f8ab, 0xda60c857, ++ 0x052997ef, 0x73c710cd, 0x7f378b6d, 0x56c79d24, 0x3a6b3bc5, 0xeb8effda, ++ 0xf2ebfda0, 0x5ff0360d, 0x026d39c7, 0x64d037f8, 0xcfdc3903, 0xe69b19fa, ++ 0xc1f71cb8, 0xd058c776, 0xe58bbf07, 0xbf9c4de7, 0x5aba1d2a, 0xebe2bae7, ++ 0x049f4e31, 0x47ae1e5e, 0x3bf2f356, 0x1ebdda78, 0x4f208af1, 0x015ee256, ++ 0x4c9bb77f, 0xa42ffa66, 0x3c132647, 0xf5cfdc5f, 0xcd5cfa92, 0x647a88ff, ++ 0x4845c83f, 0x440c4c8f, 0x27f423d4, 0x6c27fca2, 0x2c76845c, 0x8ed91c39, ++ 0xad9624fd, 0x7eb009c3, 0x5e097ad2, 0x7f74f7f6, 0x8a05d7c7, 0xac838c48, ++ 0x73c468d9, 0x590f5509, 0xf82c9167, 0x5856c0fb, 0x2cd6a16f, 0x7029e1f7, ++ 0xd8a49bee, 0xb4fa1ce1, 0x9fbe441c, 0x1af01ba6, 0x004b87c4, 0x47d0477e, ++ 0xde21fc04, 0x3f30068f, 0x7284d8be, 0xe09734b2, 0x69bcd9fa, 0x28aae202, ++ 0xdc00553f, 0x09c5d716, 0x639f1e50, 0x529e8033, 0xb96131e7, 0x72a4f888, ++ 0x8395aed0, 0x114ade09, 0x97a835e8, 0xc38e493b, 0x5aa99638, 0x7ebfd07f, ++ 0xfd6aa649, 0xe6bf3441, 0x0483f8bb, 0xc0fba5db, 0xd637d41f, 0x9dfa0979, ++ 0x36097661, 0x03ffcf4a, 0x1cc8bafb, 0x00008000, 0x00088b1f, 0x00000000, ++ 0x7dd5ff00, 0xc5547c0b, 0xbddcf0f5, 0x936bc8fb, 0x21213bcd, 0x21e1026c, ++ 0x10084b88, 0x83cdeb11, 0x05849288, 0x6ea2be29, 0xf23c2402, 0x6b62d102, ++ 0x023042cb, 0x2d47c622, 0x858bac56, 0x0da229fe, 0xa8d63502, 0x8a8b401b, ++ 0x9fb4df1a, 0x8790f0d2, 0xfb60a482, 0x77cb16a5, 0xec9999ce, 0x808d9bde, ++ 0xf7efffda, 0xe64e9f85, 0x67b999de, 0x9cce7bce, 0x6e4d8c99, 0xc640d950, ++ 0xb18e3f98, 0x873b19cb, 0x2ef5573f, 0x9632f319, 0x4dfcd8c8, 0x0e1e5773, ++ 0x0e73f463, 0x596dabfe, 0xb7d7aba0, 0xf0f2b5de, 0x3e7d40d0, 0xcf0a92fe, ++ 0x43b21717, 0x0ef7e1a3, 0x1892c516, 0x584de1ab, 0xade7586d, 0xc58c9c9b, ++ 0x8e093d98, 0xf5d58c31, 0x0e28f23b, 0x77f6df57, 0x6faa27ab, 0x57f01238, ++ 0xcc27dffc, 0x5f8151b7, 0x256a0ddd, 0xa9ec9fb4, 0x33c51770, 0x7cc074e6, ++ 0x4d2360c6, 0x2ea76699, 0xc608cb5a, 0xf49b199a, 0x5fcbb61c, 0x694166a8, ++ 0x7b5e630b, 0x51f3b61c, 0xe4c7ac7b, 0xeee16810, 0x5d5b194b, 0x1be49a62, ++ 0xb18e1bd1, 0x85efa88e, 0x998c760f, 0xdac0f183, 0x9fc7fdfe, 0xf8f6858e, ++ 0x9658cabb, 0xf11633d9, 0x1e89f801, 0xb879f808, 0xe21260e4, 0xd84c7e03, ++ 0x8df176ef, 0xdeb99727, 0xf0780219, 0x8db2adbe, 0xb3651f50, 0x9c18957a, ++ 0x4920a036, 0x4a3f078c, 0x8fb7e29b, 0x0ad7fa84, 0xa70e80d3, 0x7ca956be, ++ 0x49ee17f2, 0xaebfd099, 0x065ae4d5, 0x00daeaed, 0xb98cb999, 0x585f3006, ++ 0x112d6326, 0x8c1923d1, 0x4a2bbf97, 0x53f3c0b3, 0x96cf984a, 0x08657849, ++ 0x9fc24587, 0x05b195d7, 0xd9b637de, 0x9ea82ad8, 0x235207ca, 0x0c5766bc, ++ 0xefc0111b, 0x1e1eb7c8, 0xe780330a, 0xd0372ecd, 0x3e70a9e5, 0x19e153fe, ++ 0xa58d163e, 0x018ce7ec, 0x8259614e, 0xe066cc6f, 0x1413a011, 0x2c272c5e, ++ 0x8199a81e, 0x79998ace, 0x09af402d, 0xf1157e5d, 0x34e5d593, 0xf7c0a8b1, ++ 0xe68c5dcc, 0x9a76659d, 0x8b47005c, 0x3db6ffc0, 0xc066a9cf, 0xe6a2d8eb, ++ 0x7bca1546, 0x10b33da2, 0x3427e3df, 0xf8f3e234, 0x81eaaf12, 0xc34ab9f6, ++ 0xd9f23b2e, 0xd1b5cc35, 0xf8939019, 0xe00ed64e, 0x9d7dd8b2, 0x1f3c345a, ++ 0x1f6b4c7f, 0x718ff301, 0x63c70533, 0x7f7d296c, 0x1ebb944a, 0x9a0965c7, ++ 0x8ce30a52, 0xfc231bfd, 0xedb671c8, 0x009c5029, 0x9147426f, 0x9bd11ce2, ++ 0xe732d7cf, 0x77ae387d, 0xf485c9af, 0x6d30b675, 0xf01fb43d, 0x884525f4, ++ 0x8d7ed92f, 0x5defa143, 0x5a14f1e1, 0x17e7cd19, 0xf97fe80e, 0x165dbe0d, ++ 0x1cdc6780, 0x33ab2eef, 0x19733e68, 0xe9d6978d, 0xeea479a5, 0xf963e4f3, ++ 0xbe963d98, 0xbf98fe3b, 0x4bb4047d, 0xc0f9806e, 0x1f1dfef3, 0xfed78828, ++ 0xd20a1d0d, 0x9d9edb73, 0xc77a6f04, 0xf90a5e6e, 0xabe40e7a, 0x8f1e6825, ++ 0xd7044dd9, 0x5f0e7663, 0x2999c9d3, 0x90ff786e, 0x3d98f3c3, 0xa68f3031, ++ 0x034a4f7c, 0x4f76bf8c, 0xb37ccf56, 0xa0cbde01, 0x5a5eb05b, 0x38d2b0ef, ++ 0x5f9eec47, 0x6feafce3, 0x790d7ce8, 0xef3db9f0, 0xb47c9345, 0x937d1025, ++ 0x7a241ef6, 0x9c062d24, 0x7bb5e3c1, 0x2fa82a17, 0xcd0396d6, 0x9678de94, ++ 0xc22d637a, 0x88e3fc4f, 0x69fc0a9c, 0x0ffcf38f, 0x9fb6477e, 0x9917115c, ++ 0x6497a415, 0x309747bf, 0x64002cf7, 0x6dcaeedc, 0xeee90b2c, 0xdfae95f9, ++ 0x2384f7a5, 0xb5db653f, 0x9c3f203f, 0xf80dd852, 0xc258cd9d, 0x5e16cdf3, ++ 0x97faf897, 0x8e43e7a0, 0xc7d98fa9, 0x80393c70, 0xf387378f, 0x747d4676, ++ 0x39fbc1d2, 0x0eb0bf05, 0x0f382fce, 0xddb263d4, 0x344f9207, 0xf399a14f, ++ 0x93e22ec9, 0xe42edf3c, 0xbc9371db, 0xfbff90bb, 0x9327c133, 0xf9189f38, ++ 0x57ea20fd, 0x862e93e2, 0x9855cf78, 0xb2ee983b, 0x42e108fc, 0x4051dd7d, ++ 0xd0f203fc, 0x9b1bdf81, 0x505aa0d6, 0x64c7336f, 0x1dc73fb4, 0x3a376a4e, ++ 0xfc85db4f, 0x24dcd0e6, 0x3a445fcf, 0x7264df38, 0x7ffe80fe, 0x7946fec1, ++ 0x34728eda, 0x09472022, 0xbd518fc8, 0x016df1f9, 0x43c471cf, 0x3df1a862, ++ 0xaf041c47, 0x90605349, 0x7ca2fb71, 0x5b8e9a0c, 0xe5127604, 0x03ff0194, ++ 0x1c737180, 0x696728f9, 0xe9052e35, 0x7dd2327a, 0xa135fb02, 0x7e45cc6e, ++ 0xa11af936, 0x1a31bddf, 0xdb3befd1, 0x8c2cdd89, 0x09d80d8d, 0x12ff0bb0, ++ 0x054d6176, 0xffdfebea, 0xd4fa8ad3, 0x4f6fe529, 0x1065644e, 0xf2c5c47f, ++ 0x5bd10679, 0x6f410d89, 0xd2339ea3, 0xf417a03b, 0x15f00e7a, 0xcdfa4b19, ++ 0x2cf91a33, 0xca9163a1, 0xaf5e83f5, 0x5e8f45f5, 0x21d041fa, 0x404b4a21, ++ 0x19031f38, 0x0b7aefc4, 0xde7c50d8, 0x1a1e3d97, 0xfffd451b, 0x2878f68b, ++ 0xc7b463c2, 0xd7aeb0a6, 0x6d47c015, 0x6154ea9b, 0xc7778d0a, 0x27ff4869, ++ 0x0d97145b, 0x536aedda, 0x6c9e1f89, 0x29bb208a, 0x4772fde1, 0x197648cc, ++ 0xd9fe4294, 0xa7b258ee, 0xfbe2b1f5, 0xf817e1cb, 0xaf0729fe, 0xf278720e, ++ 0xffb2cf10, 0x08ff6d93, 0x4f0f3c47, 0xe8c3b451, 0x31ed1957, 0xfd029088, ++ 0x829bf86d, 0x42b51d78, 0xe19ac145, 0x895366d9, 0x9f38056e, 0xbdf3ac71, ++ 0xd3d70009, 0xc14c0a5b, 0xd699d6fe, 0x09dd6eaf, 0x7247d7f0, 0xc91f5cfb, ++ 0x9da9f3ed, 0xbf230767, 0x2678bb5d, 0xd56ebde9, 0x48363933, 0xf431bdcf, ++ 0xacc3d710, 0x386471dc, 0xce535a7e, 0xa30a0245, 0xd19a86c3, 0x5c2350af, ++ 0x20afdeaa, 0x06cc68e6, 0xdafe20fc, 0x8d7f0823, 0x997720d9, 0x380de704, ++ 0x2b76ddef, 0x67e7854b, 0x9db11e40, 0xc03bfb84, 0xc78c115b, 0x8ee9bc00, ++ 0x2f829123, 0x3d7c00d4, 0xc03a4174, 0x4cddaaf8, 0x22c538f3, 0x16cf485c, ++ 0xfe90c6ab, 0x3fc2fdde, 0x13ab7410, 0x6daa773c, 0xcc0f3ecc, 0xe97dc9ef, ++ 0xaa7fec2e, 0x29b84cf5, 0xcf47fd0a, 0xda9bc442, 0xed1a2bbf, 0x33b6aee1, ++ 0x90473ac3, 0xcf845b7e, 0x143deccf, 0x9df119e7, 0xd0f3f7e6, 0xafcfd0f4, ++ 0x22b51cde, 0x33444fd8, 0xc0d2864b, 0xfb5b4a47, 0x249194bf, 0xa1f50c7f, ++ 0x1af98337, 0x974dde61, 0xce9a7e0a, 0x46f7289c, 0xb8720f7a, 0x920d8fef, ++ 0xfb8764db, 0x7e3bc401, 0xe6872d27, 0xf92c60f9, 0x5b473383, 0x22bf384c, ++ 0xfa537686, 0xe89e727b, 0x04e7878f, 0xbdfd27e6, 0x9f67f99e, 0xd197b91d, ++ 0x3d209fbc, 0x4ccb9cc4, 0x183d6700, 0xc1995585, 0x5d13f7f3, 0x6b3cc56a, ++ 0x2afca2c3, 0xb76d8bcc, 0xfa94e89c, 0x3cf7ab20, 0x709b4e80, 0x6b816f5c, ++ 0xfce9079f, 0x235728d7, 0xe1dcc9e2, 0xe615ff40, 0xc9e719b5, 0x10522af2, ++ 0xb4a2530f, 0xdfbea33f, 0x5f1194bc, 0xf9867a9f, 0x6f49829e, 0xbe226ddd, ++ 0x212ecf59, 0x74c4bffe, 0x147756fa, 0xec76f5c9, 0x6cd1db9f, 0xed9bfd42, ++ 0xaf509a73, 0x3168eb0e, 0x3c1f8899, 0xc07be3cf, 0xc03319d3, 0x834b7c37, ++ 0xc2f91dfa, 0x0a72217f, 0xe7cddb74, 0xf126e9cb, 0xc3f04136, 0x1a1bc404, ++ 0x89f32e86, 0xde00b0ce, 0x2d2c2e80, 0x8c78f7ae, 0x9e206675, 0x3a385fda, ++ 0xabc613b8, 0xade8f97b, 0x3fba9788, 0x8a1988d9, 0x062c34fe, 0xfccbfef9, ++ 0x89cd7ed0, 0x336e0d25, 0xb15be330, 0x6a076459, 0xfd158758, 0x6eebd005, ++ 0x975e9073, 0x4b5edc7e, 0xbf8e0947, 0x96ca8c77, 0xb8cf9e02, 0x10b325c6, ++ 0x1fc7a2f6, 0x9b2dbf40, 0xec22dfb1, 0xe42f8fc8, 0x323f70c6, 0xb182ec8e, ++ 0x7325defd, 0xbe9645dc, 0x2a3bdbc7, 0xf41f06fc, 0x43f8312f, 0xf6e589ff, ++ 0xdb8e252d, 0x1acc5063, 0x8ff279c2, 0x1e179f76, 0x30f9cc9d, 0x4e9e019a, ++ 0xb47f7f6e, 0x24e8f817, 0x45fdb8eb, 0xa2afb794, 0x32575d68, 0x4bd1c3ea, ++ 0xbcf901ed, 0xfdcf8f32, 0x8adfe7ca, 0x92fb4276, 0xbc12bbad, 0x92bbf841, ++ 0xe1eabf99, 0x2efc4ceb, 0x77331f9f, 0xb07a460e, 0x39278f17, 0xe1792ca1, ++ 0x07ce04d5, 0x3a026eb0, 0xee7a122f, 0xc828f80f, 0x5c592eef, 0x1d1a2ee7, ++ 0x8776d7a8, 0xdd705f33, 0x25c561dc, 0x14776d71, 0x6b183f3d, 0x603e404f, ++ 0xd43f58fd, 0xebe27d37, 0x7c69f102, 0x77b9f12e, 0xf40cf1d4, 0xc3ecbe2f, ++ 0xe05abe2f, 0x97ef87bb, 0xd945dc78, 0xdf9bfa81, 0x43b9b7a8, 0xfa2e1bf4, ++ 0x9e5d719d, 0x895f7e8c, 0x11c83fd5, 0x23e11e32, 0x7a788c38, 0x24756ce3, ++ 0x6ec7fb8e, 0x7050a4db, 0x7d338a0d, 0x5ec1f8bf, 0x2fc82a80, 0x267b318c, ++ 0x64ff71c4, 0xd7a834cd, 0x4c533b0d, 0x2fc96ceb, 0xc95def42, 0xbf28edbc, ++ 0xf490fe46, 0x74138a2e, 0x4869634b, 0x939c7b37, 0x07908df3, 0x3c461f29, ++ 0x56c9cb1a, 0x1eb509e6, 0xd783dfe8, 0x7d05e670, 0x0b7afb78, 0xceb7f9d9, ++ 0x347d3c7e, 0x75d1fbf0, 0xf832c716, 0x76279ce4, 0xef0c3fa5, 0x39b28ce7, ++ 0x751fa814, 0xdca107fa, 0xbaa13f57, 0xae8e1f91, 0x26693dbb, 0x7e400fae, ++ 0xea8e006b, 0x3e7a16f5, 0xf41dfd67, 0xeb90b8fc, 0x871227ea, 0x6b7cbea3, ++ 0xa424aaf7, 0xee6f9ce3, 0xd974819d, 0x1f0c756a, 0x16cd6505, 0x84145dc5, ++ 0xc21b79ef, 0x26adf575, 0x21e70736, 0x4f14cae9, 0xc0277bcf, 0xe99c4773, ++ 0x7e9df9fb, 0x7e09dfbd, 0xdc711de6, 0x0ebb2fbf, 0xe6375de6, 0xbbf7f90c, ++ 0x7b208b5e, 0x4a944af2, 0xd47fa47e, 0x32f37dff, 0x637e17a8, 0x278f9176, ++ 0xd0513ce8, 0xd2623c19, 0xbc6155db, 0x9982f85e, 0xbb42d0fc, 0x83f6f84a, ++ 0x23222d5e, 0x844d45af, 0xfd923f76, 0x5c8f09d4, 0xc626ed0e, 0xa1da1858, ++ 0x95e7f91f, 0x5793b030, 0x760f9b75, 0x80a7cd06, 0x8bf46669, 0xf74599f3, ++ 0xf444657c, 0xc2d7e853, 0x87b46660, 0xf7fa6185, 0x7b5d0713, 0x8989fd1c, ++ 0xc973fd0e, 0xff208f7f, 0xc6f40645, 0x7f3ed7ae, 0xb3cc3268, 0xfe4aaf6a, ++ 0xf2f4f9f4, 0x6caf38db, 0xe51bf7a4, 0x5bdfa05b, 0x9d6f3b02, 0x153cba3d, ++ 0x614f2bf9, 0x7a3ae718, 0xfe5cb436, 0xc615e855, 0x0343ce80, 0xcd752e74, ++ 0xd8a3a9ed, 0xd05bc94f, 0x2ff84753, 0xbb7d9f5c, 0x67129abe, 0xda30f925, ++ 0xfcfca30f, 0xc947ecb7, 0xbc3357a8, 0x877f2a76, 0x5cad89e5, 0x85f51aff, ++ 0x37f45ed1, 0x9d80d9e8, 0xa2767550, 0xc493ea3f, 0xa5617b60, 0xfae03ff7, ++ 0x07a953f8, 0xe0c7d783, 0xbcbe10cf, 0x2eb4cd63, 0x20ebbf07, 0xe5111bb6, ++ 0x9007cf8c, 0x22b23b96, 0xdb65af51, 0x05c59f3d, 0x6f86a5c5, 0xfea13669, ++ 0x58d789e8, 0xb91b71f4, 0xc7113d7e, 0xa15de6f9, 0x4afd61d7, 0xcfe97eeb, ++ 0xfa563f4a, 0x197c72af, 0x67ca6b07, 0xcb106e3c, 0xa1acebfd, 0xc603934e, ++ 0x4524b95f, 0x7cfc0c3b, 0x952712df, 0x5d50e86c, 0x72fd17fc, 0x19dde7ec, ++ 0x4cfaf341, 0xb9448f71, 0xe684a95c, 0xc1789caf, 0x7e4dcc3f, 0xbb3e7c80, ++ 0xcebeb420, 0xbcd33788, 0x31bd1ff2, 0xcfb4fd03, 0x40ca6fda, 0x2199fa3d, ++ 0xbf17dbbe, 0xf1e4283f, 0x622f617e, 0x01e01c45, 0x83a81394, 0x695b6b34, ++ 0x9b926e9e, 0x40dc96fb, 0x164bc3e5, 0x9f167bd3, 0xf23af049, 0x040f73df, ++ 0xad5e1dfa, 0x6d983d92, 0x858e0f75, 0x4cc3877e, 0xd4384f14, 0x7b693510, ++ 0xb4673e14, 0xe8fd9c7e, 0xe0de8de4, 0x47989f38, 0x89ccf35f, 0xb8f66eff, ++ 0xa3467596, 0xc7e1ea5d, 0xf2ecbd7d, 0xb889f165, 0xc24cec5e, 0xc74af576, ++ 0xd8b42de0, 0x8e08caea, 0xb5db55cb, 0x62d76c1c, 0x2e51c365, 0xddb8225a, ++ 0x3e39c231, 0xcad9f39e, 0x5f054325, 0x80c3b4b8, 0x7fa37faf, 0x433ffd07, ++ 0xee82157b, 0xbf7e8957, 0xc5576bb4, 0xc8a3fd13, 0x0079a74f, 0x68c6a4bf, ++ 0xd61cf805, 0xd0f14565, 0x8f326c6e, 0x77663dcf, 0xf0a3ecf4, 0x9afb8df5, ++ 0xb7f110f8, 0x463de2be, 0x3c090e38, 0xb240e31b, 0xe9a07194, 0xf2c166b0, ++ 0xb507388b, 0x8c217197, 0xff8a877f, 0x7ae78d6c, 0xd4d34533, 0x72df6748, ++ 0xe839eb97, 0x75ce3155, 0x7b217303, 0x69684f25, 0x6a57f8c7, 0xc6296f91, ++ 0x8d629ac7, 0xc70de872, 0xc7965975, 0x7685e494, 0x7c9e1d49, 0xbdea146b, ++ 0x992f8224, 0x7a452c35, 0x344c7ae5, 0x11dddce9, 0xa62e453e, 0xa168c9a1, ++ 0xc342411f, 0x4506de51, 0x7e10167b, 0x62343567, 0x86ad3e3c, 0x571c33ef, ++ 0x30e2033c, 0x446afa0e, 0x99777f48, 0x0a531fa0, 0xf814b1fa, 0xe10b06ce, ++ 0x2fc37721, 0x7378456f, 0x566d5c37, 0xbf21e282, 0xfb50b789, 0x1bceafe3, ++ 0xbf89f140, 0x667658d8, 0x151f71ef, 0xf029dee3, 0x9a1acdbd, 0x7a121eef, ++ 0xe9eb3be3, 0xf473f04e, 0xf8a1fa7a, 0x5d5a78a0, 0xd3d269ed, 0x3edcf175, ++ 0x796e6e3c, 0xf3e01fad, 0x85cc59f1, 0x69b79f78, 0xb759c53d, 0xc1ae5b59, ++ 0x9d6f267d, 0x65bc6189, 0x7a7f6bf7, 0x89fa1fad, 0xd0a39cb3, 0xbfe9e83f, ++ 0x3e137377, 0x1b0e7c7f, 0xf54ff885, 0xdc60a83d, 0xcde19fe5, 0x6e7faf84, ++ 0x30a5b1b4, 0xb6efb9a5, 0xa853f35c, 0x3131adaf, 0x79c62bd4, 0xa62c97c3, ++ 0x16fd2c14, 0x3fa71e53, 0x77493fea, 0xd22b2c60, 0xf10dd243, 0xddca15b7, ++ 0xf8279f1b, 0x308b5c25, 0xe7063dbe, 0xe41af5b1, 0x71357e93, 0x2401c60a, ++ 0x4ed7df5c, 0xf3f680fc, 0xf110f8d5, 0xf3f610e5, 0xb4676c0d, 0x99bb469f, ++ 0x22ded76d, 0xfb1e77fd, 0xe1f04339, 0xf43f420b, 0xbee063ec, 0x4cba0857, ++ 0xd715ef8f, 0xb9e104fe, 0x7176b8d8, 0x3627df3c, 0x5b37b5c6, 0x8e6d1eb9, ++ 0x0d4db763, 0x02f90f21, 0x5d23d35e, 0x098bb456, 0xbd484a6d, 0xeb9d98f4, ++ 0xa79bd025, 0xdf720f10, 0x4357a8c3, 0x389ff7e0, 0xfc5b619f, 0x4e55b13b, ++ 0x7448a0ec, 0x07392ebb, 0xdf10d5eb, 0x87c08ff9, 0xfda31173, 0x2303674f, ++ 0x1f75047d, 0x15f9ee0f, 0x8f403fd4, 0xf9ee3873, 0x756e9ff6, 0xc9bf13e4, ++ 0x6245a6fd, 0x6f7e48df, 0xd3a70250, 0x3c2d0ead, 0x8bf71121, 0xd8fbeb42, ++ 0xdfce4504, 0x13fd0091, 0xbedd3116, 0x494fdc8a, 0xd62af068, 0x8c2b345c, ++ 0xe203a4e2, 0xd02d4b3d, 0xe672ebae, 0x31ea0a7a, 0xd47c8ee5, 0x5c737197, ++ 0xd2efb8ed, 0xd5c79274, 0xdf30169b, 0x1f282532, 0xdbe593c0, 0x16e9c998, ++ 0x7697aebc, 0xec0fce45, 0xc381339d, 0x5f658595, 0x9407eef6, 0x85c2572b, ++ 0xb063a5f9, 0xfdd285dd, 0xaf3e04ca, 0x59fdd1f3, 0x21efd707, 0x109857be, ++ 0x4f80cf82, 0xcf12128a, 0xb1f127cf, 0xf94fb717, 0xfdf2a445, 0xf1bdcbd6, ++ 0x0842737a, 0xc4bab57d, 0xf38cd434, 0x50ae1164, 0x212eaf76, 0xbf9dbfea, ++ 0xbae02751, 0x278dfca8, 0x4569d17f, 0x07fdcb3a, 0x6f31af09, 0x6d1e67a3, ++ 0xf75c68ca, 0x4b3aefe5, 0xf6a9f9fe, 0xef3fc9af, 0xbfc17f9d, 0x00f910bb, ++ 0x46a899e0, 0x5e9cfc91, 0x2a09e3c7, 0x026afe73, 0x58f7cdc6, 0xfc49cf98, ++ 0xcd0bfe4f, 0x19a7ea17, 0xfdb1f973, 0xe3d93b16, 0x1267d7ea, 0x4cf2639e, ++ 0xaf8419cc, 0x39822d58, 0x3f15f083, 0x4f574e29, 0xb5d3f774, 0x4b21be4f, ++ 0x73d53ef7, 0xda7dee89, 0xbd5d1c9c, 0x5d78c37f, 0x0b8b01fb, 0xef4cf574, ++ 0x03f6bab5, 0xd5d34c57, 0xd26f9bb3, 0x1e1cdfb5, 0xf3ed14fd, 0x418eb578, ++ 0x6259df30, 0x56d643be, 0x1881faea, 0x6d3f71f9, 0x17f720b6, 0x28f78b9b, ++ 0x89664860, 0xdf30c8f8, 0xb3b8dd3c, 0x0df1f59b, 0x2d7aeb33, 0xe757f00d, ++ 0xa87e5c53, 0xbfd5af57, 0x9ebadb9f, 0xa7d739f0, 0x937f3e7f, 0xadf23ebe, ++ 0xfcf386eb, 0x9468f719, 0xe8253feb, 0xa5e725e3, 0x77c877b3, 0x452db3a2, ++ 0xa770e74f, 0xfc46ce9e, 0x338d0e45, 0xdf7f87bc, 0x4bbb3f82, 0x2dff17cf, ++ 0xf01a75fc, 0x73ca2535, 0x4cf4e508, 0xf71522eb, 0xbe24d89f, 0xf5a67d8f, ++ 0x9d7b91ab, 0xb255f621, 0x7cabed7b, 0x5f1c1091, 0xa72afb16, 0x32ed7f70, ++ 0x6bfb0176, 0x7885febb, 0xb2e581b0, 0x9e5e1e60, 0x3f67ac2b, 0x8fb03c2d, ++ 0x3d5fd462, 0x39e1d876, 0x16f7df8b, 0x1b21f604, 0x98d8f7a1, 0xa708dc8f, ++ 0x79928fdc, 0x869f322a, 0xca79f145, 0xe60f0071, 0x8bcc44c4, 0x75c48b8b, ++ 0x0bddd6dc, 0xf3225d69, 0x87c89869, 0x931fe10b, 0x5fc16d1e, 0x46aec953, ++ 0xbb218e26, 0xb20c4f6a, 0x49df32ab, 0xc6bed5da, 0x7d4efb91, 0x954eca95, ++ 0x94bad1f6, 0x2153d708, 0xc490faf4, 0x8e5f69ef, 0x0ec78af5, 0xe3d20c49, ++ 0x799c7775, 0xe03bf50d, 0x9f9c12fd, 0x53760edd, 0x5fcdd809, 0xbc934645, ++ 0xfaaebd75, 0xd383c086, 0xb898ce61, 0x31fd8111, 0xc213bc23, 0x4d8f28d2, ++ 0x710cdbd6, 0xee1ca69b, 0xe44b8cc7, 0x3b3f547e, 0xc4cabbf7, 0xeb0deb3c, ++ 0x7c15fa86, 0x30d20c7d, 0x5fc82da7, 0x53b44b28, 0xf9910dfb, 0x7af70865, ++ 0xca685f11, 0x4d7be854, 0xddf6428a, 0xc32828ea, 0x90937ef9, 0xb1658a5f, ++ 0xae196ef8, 0xe6bfe1f9, 0x538f0e2c, 0xf1c89be4, 0xfb7913c3, 0x2a02c4f0, ++ 0xc21d12cb, 0x825c728f, 0x52247ef4, 0x6aad71a3, 0xeb96fde8, 0xd13fb912, ++ 0x31ca3182, 0x28993901, 0xe858a6e4, 0xdb5f8c31, 0x92b49848, 0xb8ba4989, ++ 0x04d607f5, 0xa856b711, 0xe6fa86bb, 0xbec7412a, 0x50dad8e2, 0xa7546ec7, ++ 0xeaf638c6, 0x96c71e70, 0x715eee71, 0xc871576c, 0x21d23638, 0x0f202e32, ++ 0xfb3d8975, 0x6fa8e960, 0x469ead5a, 0xed748f5c, 0x1e16bf00, 0x5275f50f, ++ 0xbdd2fb7c, 0xeeb85d03, 0x3b64ca68, 0x4b3fc8ed, 0xb7bf4319, 0x2cb4d3b5, ++ 0xf6afde1c, 0xbfbe0732, 0xcf5f1d7c, 0xba75af54, 0xae529a70, 0x24cc481f, ++ 0xdd6059bc, 0x7ec1cf68, 0xde31dad3, 0x8b3a7abd, 0xccd0b343, 0xd1a30b9a, ++ 0x42c758cf, 0x0956a7ae, 0xdfce4f3a, 0x27fca2a9, 0x851f0176, 0x44aad3a0, ++ 0x57e7f493, 0xeb8d1f22, 0xfbe19cf2, 0x903f5c4c, 0xdb75c38a, 0xe1f9136e, ++ 0xc6f7fec6, 0xfd803e14, 0x8e85f52e, 0x39d8b4e3, 0xba442f1c, 0xb6ed497f, ++ 0x0f515a77, 0x3a7d4b55, 0x40ccc4cb, 0x5d04ebf7, 0xf3c75baf, 0x73d9d813, ++ 0x7fe954e7, 0xa19f1a31, 0x6e9ea89e, 0xa45c61f7, 0x4bd32dba, 0x8a15b970, ++ 0xbdb7d4fb, 0x757ac6eb, 0xd703ae6e, 0x995fdae1, 0xb9286472, 0x23eb8c6e, ++ 0xf5223b33, 0x04d5d903, 0x26994fda, 0xeec5adf8, 0x6f413824, 0x7c048eaf, ++ 0xba5baf57, 0x3e53f313, 0x7da32dfc, 0xd76a7d93, 0xc7ec1c58, 0x39c59c80, ++ 0x39599a58, 0xd0a715e5, 0x38c5d338, 0xbbe1afde, 0xfeef8161, 0x9a75edb8, ++ 0xf30b3ecf, 0x9d1f0186, 0x277ae97a, 0x894db1fa, 0x6be22e61, 0x5fb8dfb1, ++ 0x4643dcf5, 0x8755dcc5, 0x16d8dda0, 0x877cc0e9, 0xdc7d2f53, 0x9fffe31f, ++ 0x1d8cfcfe, 0x99bfc2fd, 0xf798ecbb, 0xf7eeec7a, 0xf3d01aed, 0xca55bbd3, ++ 0xd855ba9f, 0xb7f78901, 0x92b3fd04, 0xef11bbdc, 0x66f92db7, 0x103e706c, ++ 0xfc489c5b, 0xd2a7d73c, 0xde8f52d6, 0x49c604dc, 0x75e367a7, 0x6bd7a975, ++ 0x87d7a1cd, 0xfb97126a, 0x5bd65bb9, 0x7df89cd3, 0xfdf847cf, 0x47ce6663, ++ 0x3e2bb6c7, 0x9e00666f, 0xaca32dca, 0x6feaf069, 0x47e6366d, 0xb0ee64fb, ++ 0xad5f7cf0, 0xf0be0144, 0xe11bfa08, 0x48e5ed7c, 0x2ff66f1a, 0x80a8feb9, ++ 0xfc062d6f, 0x92e6da7a, 0x63ce305e, 0xe2cea7f6, 0xecebc064, 0x3f430a95, ++ 0x0ddfdb08, 0xbe2cf3f4, 0x7fb8eff7, 0x85679c6a, 0xa407af57, 0x7416aafe, ++ 0xff42b99e, 0x3eedbabe, 0xf316671a, 0xd1833e50, 0xbb6ea9df, 0x1bfa28e6, ++ 0xf4e73f46, 0x2861d19e, 0x144aff0f, 0x3658cc7e, 0x6ff41cee, 0xf18aca8c, ++ 0x59279084, 0x20e2589e, 0x497cfd66, 0x96c79518, 0x27772a30, 0x69ae3e72, ++ 0xfd18b77b, 0xadd6ba9f, 0x1d176f24, 0x1e3b6f07, 0xd80b137d, 0x27b318d1, ++ 0xf8f50926, 0x0f17451c, 0xc67f5baf, 0xc0967e4a, 0x5e78b94f, 0x3a00f88e, ++ 0x2b5cccdc, 0xca7d0026, 0xfd812c6b, 0x392ff826, 0x1c77cc49, 0xf0bd57cc, ++ 0xd679caf9, 0xe7257b0a, 0xddfbe46f, 0xdacdaf42, 0x1fa9b530, 0xa5f1a4a0, ++ 0x7c9d19a3, 0xc201f6bd, 0x9aaaf92f, 0x43538bb9, 0x67a48ff0, 0xddb49f0f, ++ 0x7491f34f, 0x215cd59c, 0x114dede6, 0x8c14c4f1, 0xc6f91a27, 0xbe4627c8, ++ 0x99d2d2f8, 0xe46cf281, 0xd847990b, 0xe24c3fcb, 0x9cb33379, 0x09c6315a, ++ 0x13773367, 0x24f12dc5, 0xb39418c4, 0x867ed7e6, 0xf381b672, 0xfd04dff9, ++ 0x29e4977e, 0x9e7e824e, 0x21d4d765, 0x6d4b9ddc, 0x9e7f2819, 0x026aa965, ++ 0x51acf7b4, 0x2c166f48, 0x9e22b54b, 0x551f2e66, 0xc398728c, 0x96ff1a34, ++ 0xced21678, 0xaf790bd7, 0x6b30b06c, 0x1587090c, 0xae4eb5f3, 0x0b5f2850, ++ 0x814ba3f7, 0xb908e62f, 0x6ef95da9, 0x2717d934, 0x698b1bfc, 0x4e67fceb, ++ 0xdde13543, 0xbe4befe8, 0x86a07692, 0x615358b5, 0xdbab79dc, 0xf5c6ff09, ++ 0x4d5b3d40, 0x316daa74, 0x9ab86f3c, 0xb73306e8, 0xbeab3ae2, 0x90deb0d5, ++ 0x2e62e8fc, 0x9dcf47e4, 0xa7cc30f6, 0xa9f8102b, 0x5038ad58, 0xde5ccccf, ++ 0xd43d789e, 0x5d51ee67, 0xfc1e9d30, 0xb4eb5eb0, 0x75079411, 0xad364f7a, ++ 0x9d3b4fd7, 0x13ced8c9, 0x8af1d7cd, 0x9f0e33d9, 0x19ef12df, 0xaeb27187, ++ 0xe619d8bf, 0x86e81d95, 0x25e63b95, 0x9491b184, 0x2360e3d7, 0xd7f906a7, ++ 0x12471615, 0xd97993ee, 0xf7c614c2, 0xf182c37c, 0xbab61f53, 0x9eb6f903, ++ 0x7e62bd99, 0xe88539ca, 0xebaf2647, 0xd7f28505, 0x8bc5ab58, 0xc2c618f2, ++ 0xd7be6296, 0x52736771, 0xdf773c2b, 0x5abd2163, 0xd69625b9, 0x0bcb9597, ++ 0x2b0768ad, 0x3f92c7b7, 0x0fc2eb03, 0xd00d8d06, 0xd1f2c0f3, 0xb8c0a5af, ++ 0x2e992d95, 0xc3c74f55, 0x79c746df, 0xfa480e2b, 0x7e83ee1d, 0x0fd14387, ++ 0xee7ba6e8, 0xdd8dd033, 0xb0764f1d, 0xd9abc17c, 0xe9d70061, 0xcfca7086, ++ 0xc27d6beb, 0x7da78d66, 0x99bf196f, 0xce27afd4, 0x6725f942, 0xfa218f56, ++ 0xe936e919, 0xa1c7333f, 0x6afeca7f, 0xdd17e867, 0x36dd9032, 0xa6df9e0d, ++ 0xa5bb7970, 0x68499af1, 0xe2485ff7, 0xd01de8fa, 0xc610da5b, 0xa57d05de, ++ 0x1f7abe81, 0x3fd619f4, 0xf542925c, 0xa938978f, 0xa192cbfc, 0xf1161e54, ++ 0xc077296a, 0xafb7c408, 0xf6bd7124, 0xf7dc924a, 0x2e82945d, 0xbcffa4c8, ++ 0xbc04c63f, 0x4cf5e897, 0xf825789e, 0x5ede9a73, 0x6f5d30de, 0x8e2d3b0f, ++ 0x5f5c14e2, 0x7fc854ae, 0xa15f74ac, 0x4ecccf6b, 0x60979e2b, 0x9e074743, ++ 0x5a73be93, 0xde3f01a7, 0x6baf1258, 0x9a45633f, 0x9271feae, 0xd4c2f493, ++ 0xcf750349, 0xae1f2a6f, 0x5b7457ab, 0x777e4319, 0x2cfc91e6, 0xb02df912, ++ 0x7174e670, 0x355fb6f0, 0x09fe4b8c, 0x5ed5fbc0, 0xd237bd0b, 0xd675d243, ++ 0x6079955a, 0x416b99bc, 0x878801ff, 0x7c92679b, 0x4ecfb17d, 0x2da688eb, ++ 0x83cedfa3, 0x162d81fa, 0xb0393fca, 0xfa0d7e3c, 0x24b60757, 0x3d283346, ++ 0x43f0aa4d, 0xa416561c, 0x2f970aef, 0x0ac73ca5, 0xfe45cd9f, 0x6fef6ec6, ++ 0xeb89dd64, 0xe5120445, 0xe7d503e4, 0x1a7e8857, 0x387377e1, 0x063b679d, ++ 0xb11e1ffe, 0xe1c9d998, 0xe5b0a63a, 0xfe1e3f58, 0x009fe0c9, 0x9b4b271c, ++ 0x2f184cab, 0x9226f750, 0x654e7cfe, 0x0be5b7c8, 0x3dffb42c, 0x3d7543f7, ++ 0x939299d6, 0x52ade9c6, 0x6cdb2efe, 0x1759f1a3, 0x5bb40870, 0x53db7bf4, ++ 0x338e14ab, 0xd4b8efaa, 0x27f04ab7, 0x58b1d1f2, 0xb012c5a6, 0xf9fbc10a, ++ 0xf1eb89bb, 0xbe9f007d, 0x32ef3891, 0x19323b8b, 0x2af3ebf8, 0x6fd248df, ++ 0x5c922777, 0xd87ef119, 0x1797f5ca, 0xe80940e5, 0x2d9c80cd, 0x69983e23, ++ 0x48b92571, 0xa2a6e56f, 0xdabc3ade, 0x332b7e42, 0x2953d16b, 0xf11cf23e, ++ 0x61cefcb1, 0xe118b3b3, 0x9322bc3b, 0xe57fbee1, 0x17d6956a, 0xbdbc7fc8, ++ 0x1f2baf8f, 0x43e03d54, 0xc50aef30, 0xf37b92c3, 0xc60bedcd, 0xd19fbe51, ++ 0x97e5963f, 0x209eab20, 0x4bde61ff, 0xe58d1f3c, 0x5fa79a76, 0xe58f3c1a, ++ 0x3c9e7bfc, 0x4d4c9e5d, 0x47f79fd6, 0x0fcf5099, 0xfebf418c, 0xf12a07f8, ++ 0xe6acf1d9, 0xcf4029b1, 0x639da613, 0x2ff5027f, 0xcc47bd4a, 0xe116df50, ++ 0x78c64bc9, 0x86756986, 0xe4f98592, 0x015cd687, 0xc67f3efd, 0x173122e2, ++ 0xcdbcf97e, 0x9b7c0773, 0x46fe043f, 0x6877ee3f, 0x73e00aa9, 0xe0c5b3be, ++ 0x38fc700f, 0xf0013931, 0x414478e2, 0x1a1d8b5f, 0xeb855f63, 0xe62699e0, ++ 0x0fdff609, 0x31bfb859, 0x15eb9939, 0x983c37e9, 0x3312e3cc, 0xd9bf9c4d, ++ 0x37e70acb, 0xed82a3f0, 0xf3dbd480, 0x0d579f31, 0xb7a901d8, 0xe533586b, ++ 0xcc9adc55, 0x8ab997fd, 0x3ae4fc8f, 0xf68090cc, 0xe9be0e55, 0xe6c9b353, ++ 0x98d265f3, 0x60ff608e, 0x27d7327d, 0x3ccfacf3, 0xcd5bec8a, 0x0d3cf83a, ++ 0xf8b73eed, 0x7b323aaa, 0xc72a9fdb, 0x3471e5fa, 0x7185c5be, 0xaf216ad2, ++ 0xcf8acdb5, 0xb70a7e4f, 0x399e32a3, 0xa351d85b, 0x9765ea7d, 0xb668f60c, ++ 0x66b2eec1, 0x78059dbd, 0x84acbce9, 0x3ba708d7, 0x98784ed2, 0xfda17007, ++ 0x5ef8f2ad, 0x15b8232b, 0x17b45017, 0x16bfe03c, 0xe03ce2c5, 0x1bd9dfbd, ++ 0x7abce33e, 0x69e62bc1, 0xf5cabb84, 0x4b9abf77, 0x2f8494f9, 0x3d243ce3, ++ 0xa49c7e8c, 0xe397954b, 0x214daab7, 0xe3d67e7a, 0x2b8a321f, 0x2d61be4b, ++ 0xbfa82ff0, 0x579823e4, 0xeab7ea19, 0x671f4047, 0x79a7e6f6, 0xf91a25ac, ++ 0x9bf98ea6, 0xee3f7fd0, 0x3971996f, 0xbdd605c6, 0xf29deb4b, 0x29b67f38, ++ 0x7de95016, 0x5749bef7, 0x88dcf806, 0xf7d1f3ef, 0x670fe2bb, 0x71f19667, ++ 0x0decd7c0, 0x523e16aa, 0xdde44ed7, 0xe61e4979, 0x8c56bd78, 0x7111ce87, ++ 0x59c1f3c5, 0x2ee7e66f, 0xc0af0bce, 0xf70d0fe7, 0x0e22c93b, 0xcaefcbd6, ++ 0x938eb90e, 0xe844fcf3, 0x7bdaf399, 0x467aebb3, 0xc1513ef6, 0xfa5f4178, ++ 0xf9d84abb, 0xa1f768d9, 0x1b76b23c, 0x7b3febc5, 0xcfed1b64, 0x1d999f59, ++ 0x91f87e8d, 0x60d733b5, 0x2d91e3fe, 0x57cec933, 0x79da5aff, 0xc107af58, ++ 0xe2b6b85b, 0xdf239fc9, 0x4ca70a6e, 0x1eddaad3, 0xbd020eb1, 0x6b9ced0a, ++ 0x8f651eb9, 0x8d5abd70, 0xc1e290f6, 0xeed8219e, 0x10cf2ace, 0xe7a0ffe4, ++ 0x9cef2764, 0x4bc3f9e9, 0x4f9dee30, 0x34bcba47, 0x44df8765, 0x8fc3bbfe, ++ 0xe176b0f6, 0x3cf1fbc7, 0x0fffd808, 0x1ff692ef, 0x9ecda7aa, 0x4b0ed06f, ++ 0xaeab5fbb, 0x9fa070cf, 0xffc4ec20, 0x112bbe36, 0x715fe4df, 0xc15c1f7c, ++ 0x35687cf1, 0x96d37bc7, 0x7eb8d181, 0x2062b83c, 0xb70755f9, 0x67be1364, ++ 0x937c02ad, 0xfbd4ed5f, 0xdf002b55, 0x7c407eb8, 0xbb955c03, 0x2edf029d, ++ 0x1c15ef8e, 0x2f356ccf, 0xabc2f567, 0xee7ff297, 0x85cdadfc, 0x70b1c27e, ++ 0xc74ff93f, 0x31acaab6, 0x7e92efc8, 0xf3583fcf, 0x933fd06f, 0xb83b9ef8, ++ 0x97ea2463, 0x1cff07f2, 0xbb9f788d, 0xf5ba6f95, 0x92d337c2, 0x7c0effd1, ++ 0x724fc7bf, 0xf2098ca5, 0x2e902e93, 0xc8cdcc75, 0x79fdb5fe, 0x1413ae1f, ++ 0xea1fc78d, 0x56a639e4, 0xcc2639fd, 0xc38f2a65, 0x2c2b8750, 0x3749e10c, ++ 0x30f2d39e, 0x67fa57dc, 0x5d6fdff6, 0xa5dc7248, 0x632d07cb, 0xbfc60b7e, ++ 0xe7428b58, 0xe5176b7f, 0xdc33e747, 0x38206ab7, 0xba28a5e6, 0xd55adf7c, ++ 0x8d62fe44, 0x328dfb95, 0x0a6a606f, 0xa6a607f7, 0xb4ff75f0, 0xa7950714, ++ 0xfbe919c2, 0x0fab7653, 0xfac0e9cf, 0xefbf0529, 0x7446c97d, 0x01308fdb, ++ 0x88ab55fe, 0x43a982fb, 0x7199bbfe, 0x6a39bc7e, 0xc19bed0f, 0xb409e4ca, ++ 0xb62cb77f, 0x4d8fc8b9, 0x9bfda188, 0xbb3e849b, 0x8dc9aa39, 0x2896e076, ++ 0x8c2586ab, 0x53a4c5eb, 0x1e7c014b, 0x67e96fbe, 0xf2aa3ca5, 0x7067ceb0, ++ 0xca5b7bc9, 0x00c23ba1, 0xddc0cbd4, 0xfc2cb8c6, 0x7c5cfdba, 0xe804ba6f, ++ 0xd7138fa3, 0x7b8e8447, 0xa0f02edc, 0x83c51a68, 0x0476306d, 0x8a6771c0, ++ 0x3a773f93, 0x1d787c78, 0xa01ec9d0, 0xf339f1af, 0x1ac1fdf2, 0xcf1dfbcc, ++ 0x11e48338, 0x1af575fe, 0xff7f7f2b, 0x3c951fda, 0xf7b18132, 0xa452f398, ++ 0x0cea0d5b, 0xc457d75c, 0x6cff70f8, 0xe3a7c60a, 0xbf1334b0, 0xaf33334c, ++ 0xa22b9789, 0xc454a730, 0x3e04cbab, 0xfcc79c7f, 0xff778031, 0xf978faeb, ++ 0x7f937ef5, 0x8a77e008, 0xfc8edfd9, 0x5a730a69, 0xf71df01c, 0xd7072524, ++ 0x2ecb3521, 0xdadf5e0c, 0x1ade086b, 0xeca7cf13, 0x1fc78bba, 0x4561066e, ++ 0x666addbc, 0xce1cd5bb, 0xfa978807, 0xda97a738, 0x3f68502d, 0x25e9c645, ++ 0xf0c147fd, 0x59bc74c1, 0xace307c0, 0xd6fec688, 0x92daf4d0, 0x2dcbd722, ++ 0x2f9e8eb4, 0x94be6ee4, 0x797a2db7, 0x84748bdb, 0xbdfa0af6, 0x459bb780, ++ 0xbc5c97d9, 0x3d7fc62e, 0x9fcfaf85, 0xb1efc8bf, 0x2c3f9e28, 0xc6d6a5e5, ++ 0x9fdf97c7, 0xe33fca22, 0x00c4afc1, 0x07afc03c, 0x68131c71, 0xc3d7e400, ++ 0xffe48dcd, 0xfb4161cc, 0x76819962, 0xd77baf92, 0xe988f47b, 0xaed6961c, ++ 0xe57a8859, 0xd42ee147, 0x5b5b37a3, 0x7aa21bb2, 0xb8fb93b7, 0x42c3ace5, ++ 0x38c8cef7, 0x1333b098, 0xdbca28d5, 0xf9f85729, 0x76f953da, 0xc0fc09af, ++ 0x213dc44f, 0xc42fc1a7, 0x2ac794ef, 0x4b74df94, 0x28659dcc, 0x56d1e5d7, ++ 0x889f9633, 0x656e447b, 0xa7fe345d, 0xeb98ac8e, 0xaa4de619, 0x000707b8, ++ 0xf704b4fc, 0xff511a41, 0x6d6afaf0, 0x449b4502, 0x0d5ec97d, 0x2cfd31f0, ++ 0xbdd501f0, 0xf77c1a25, 0x3de2abd4, 0x4ffd4a5b, 0xd9f823dd, 0xffaf0f7b, ++ 0x555fbe52, 0xad4ffd82, 0xf0d7ef94, 0x7c72fdfa, 0xf0d07f51, 0xfde1a97e, ++ 0xf5febc63, 0x5e2535da, 0x380b4ff4, 0x578f976b, 0x42695f48, 0xf32f946f, ++ 0x4dcb9e13, 0xc059793b, 0xf3dca6fc, 0xea9c1bb7, 0xf11252d6, 0x3b61f33c, ++ 0x69d1e1da, 0xc976869a, 0xa4b1ec99, 0xaa69bae2, 0xdea2b5e2, 0x7647c0fd, ++ 0xfc8faca1, 0xf5e84d3e, 0xd4dcfd21, 0x1831da5f, 0xf1353a27, 0x21d9c7e2, ++ 0x271a0ae0, 0xd3c0bbf9, 0x38d7afd8, 0xcf02efce, 0xd238c371, 0xd74a69cf, ++ 0x58f1c0ae, 0x78ba15d1, 0xb85ffce0, 0xc4ee3062, 0x500b9f30, 0x4b597f3f, ++ 0x7f1868c6, 0x642fb3fe, 0x255fa154, 0xb75d7dec, 0x47d034ca, 0x950addf5, ++ 0xc5ffb45f, 0xeb31e78a, 0x8b5bb7b6, 0x943d5da1, 0xd5704185, 0xdec13808, ++ 0xd905a799, 0x24d52d69, 0x3c83c6f4, 0xe3d9ed9f, 0x7ce7a466, 0x5f91cb53, ++ 0xaf1efda3, 0x1defdc84, 0xb7e7ca9a, 0x7c3c8fbf, 0xf180e4da, 0x26d0caee, ++ 0x6087fe22, 0x0bd4046e, 0xdfef431b, 0x28e0203f, 0xe66ff617, 0x13987b58, ++ 0x03e63cf0, 0xb55ddfbe, 0xe307332e, 0x05c945c1, 0xbebc7053, 0x3c5da8e3, ++ 0xe3c6da8e, 0x1d71e5a8, 0xb389408b, 0xaecfa955, 0xd975830e, 0x39495fe4, ++ 0xbe859103, 0xfeb26c93, 0x3a51496a, 0xbd61738f, 0x5797b1f6, 0x41ecdca3, ++ 0x3e6e3078, 0xd408d2ee, 0x91999d0f, 0xe9c60726, 0x21562a93, 0xbb8cb71c, ++ 0xe79f18b2, 0x2b83ecdb, 0xf89e5c78, 0x3dc920a2, 0x7b63df1b, 0xac787f8c, ++ 0x61ebc4fe, 0x54379e1e, 0x8cf28bca, 0xda84f48c, 0xf0299ebf, 0x41d52aba, ++ 0x0263d8f8, 0x70027338, 0x1f83efc8, 0xc603a8bf, 0x752cbc3b, 0xee272ad4, ++ 0x24afe4b7, 0xffdf127e, 0x4ee7925d, 0x1fefcbac, 0xb8c1b136, 0x3850b894, ++ 0x58f4176e, 0x78037489, 0xdf8013dc, 0xd373d682, 0xf575228a, 0x4cf125e9, ++ 0x4ecf8e0b, 0x6fd5d34f, 0x6ba81f28, 0xe1acd37f, 0xb6a5f7ba, 0x2086dc8e, ++ 0x7f6fb67f, 0xd5704bc9, 0xe811eddb, 0xf6da7dd7, 0x466e8f8f, 0xea83703f, ++ 0xee759f42, 0xba3f1b4b, 0x9a1e5182, 0x47714f16, 0x3ec9c527, 0xf232a3df, ++ 0x399accef, 0x24e87f78, 0xf71478eb, 0xf5bae50b, 0xe685f742, 0xbe53763b, ++ 0x1fb50fd8, 0x58aa74f4, 0x1cb0e6df, 0x1ba78fb4, 0x5d78a43e, 0xe79f145d, ++ 0x580e17c9, 0xf302af31, 0xdf01ce14, 0xd11d8d5f, 0xc506ec5f, 0xd85ff20f, ++ 0xd1f6807a, 0x72754dae, 0x817d3f7f, 0xd5e5cf19, 0xa0f68943, 0x0c56f418, ++ 0x3b474df0, 0xe63b74bb, 0xb9da6471, 0x1d7dde5f, 0x44f7c3c5, 0x9eceb8f0, ++ 0x9fba58a4, 0x6b8afe60, 0x775d79e8, 0x8eff8d24, 0x794c51da, 0xb42bcfbf, ++ 0x769a50ff, 0xcf9c32cb, 0x88ef089e, 0xa5bbe1db, 0x127ab87f, 0x3b6eade2, ++ 0x552f63cf, 0x005dcbdf, 0x35f34d65, 0x6554bfd4, 0x1ff0147b, 0xa66fba62, ++ 0x07d14b71, 0xd63aba80, 0xb2ed0abe, 0x7e0ff56a, 0xd58df51c, 0xbea6fa4e, ++ 0x4dfa9c3b, 0xfbf6e42e, 0xffee5483, 0x5c393a5a, 0xd2a7bb13, 0x7f17c97b, ++ 0xe5d2cd4d, 0x37125b97, 0x1b1ef198, 0xed42a74b, 0x4e1eedaf, 0x1bef9ca5, ++ 0xe74b7f43, 0x5f892dd6, 0xe05e6315, 0x838a091b, 0x3e8312dc, 0x2e30d33e, ++ 0x57d08586, 0xe6e9df3d, 0x6eb6b4f9, 0x207b5f9e, 0xb942eb4d, 0xd3bbbb2f, ++ 0x2c41fb8c, 0xf881cc2a, 0xe51bcb2a, 0x33920aac, 0x568de775, 0x91e58fa4, ++ 0xff68ad77, 0x0616506d, 0xcdfb97bd, 0x4ffd7d46, 0xfde41fa1, 0x7a3d6560, ++ 0xf3f882bd, 0x50608756, 0x84874721, 0x1dfecb1c, 0x3a01c6b4, 0xfc71e0ee, ++ 0xe13cd3af, 0x477de0fd, 0x39e1bb3e, 0x191d9fd2, 0x43f30fb8, 0x0e740fc1, ++ 0xec6fc853, 0xb2f1bca4, 0xe309a73c, 0xa4fdd1ff, 0x7cf2e1dd, 0x5bfc79be, ++ 0x951de3cc, 0xdf71c62d, 0x0eaaeab9, 0xff6bc60d, 0x68d1e8d9, 0x0777e417, ++ 0x7bf7e3f4, 0x59d74731, 0xbfd61f5c, 0xb944e91c, 0x19c5c52f, 0x64be7bee, ++ 0x3c0b75a3, 0xfa8cfda7, 0xe14f6d97, 0x68faab79, 0xf7c2bf58, 0xf7095f0b, ++ 0xbfb71f23, 0xfb466e12, 0x67864cf1, 0xf0a7e200, 0xb8452195, 0x6cdad45e, ++ 0x8ffe4666, 0xd897ece6, 0xd3e7bc37, 0x933e465f, 0xc159e9f2, 0xf042a5e5, ++ 0x3f90a569, 0x33a3908f, 0x8724c90d, 0xa006ee67, 0x6ef4bf71, 0xe8edd2e5, ++ 0x74ed382f, 0xcb9499df, 0xc11f5c52, 0xb1e1d2f3, 0xd35fa794, 0xc393ab1d, ++ 0x214ceeda, 0x5cf4f1df, 0x90a55bca, 0x2ff09b13, 0x96be0966, 0xc7948b7e, ++ 0x771ee9f1, 0x6973c03f, 0x347dc823, 0xa2e7ebed, 0xc6f8053c, 0x02fe40ea, ++ 0x0aa949be, 0xf6c69f92, 0x29fa191b, 0xf13704b6, 0x83282ccd, 0x3dd994fd, ++ 0x4e28e07c, 0x96cbf802, 0x7cf09a67, 0xe3ff7ca0, 0xffc7177e, 0x657da205, ++ 0xfd1b3f94, 0xb8434b5a, 0x9c7bcf0b, 0x3dfbe04e, 0x3c72570b, 0x0bb8b42e, ++ 0xf858cfd1, 0x32f14298, 0x2f503ff4, 0x60d7dd8d, 0xdcab8e0d, 0xf6923dd8, ++ 0x1eebafcb, 0xb2516544, 0x41f22667, 0x410cf745, 0x69df91af, 0xc68c717f, ++ 0x9f164ae3, 0x133eb5cd, 0x151e4ae3, 0x3fac7ce9, 0xbc1c3c73, 0xa556b79f, ++ 0x77dc9878, 0x1b267194, 0xb209a79e, 0x3730ffa7, 0x273dd067, 0x3e53b8c6, ++ 0x3627ffb7, 0xd7fec858, 0xd637bfb4, 0x573fef01, 0x9ed193f2, 0x3f3c5994, ++ 0x9bccf9c7, 0x02d67be6, 0x6ff7f9f5, 0x19dcbe8b, 0xd98b67c0, 0xb4f68d9f, ++ 0xf188f005, 0xead596af, 0x7bf71f24, 0x193ef922, 0xcfc96fe7, 0xd79f3e46, ++ 0x73f0903d, 0x7646c1a6, 0x2df00ce8, 0xd243b20b, 0x2f3d48ee, 0xebe48fed, ++ 0x5fd7335a, 0x943151b5, 0x3bb015d7, 0xc8f9dd53, 0x7e794377, 0x3ceec05e, ++ 0xca3c66b5, 0xca04a9c1, 0x4376966b, 0x4bf3c1ca, 0x479f2852, 0x072925da, ++ 0xfd4b9f52, 0xda5ef92e, 0xffa782ad, 0xf0afedbd, 0x9e697deb, 0x6baf88ad, ++ 0x5d7edccd, 0xff13b66b, 0x6a984c4c, 0x70b9be46, 0xe8407a3d, 0x3d3a03d1, ++ 0x1d87d75a, 0xfe8f63f8, 0xd83930bc, 0xb24fda20, 0xf5123f71, 0x5f78f07c, ++ 0x8ebc15a7, 0x1fbb78f3, 0x287fdbf7, 0xffd2fbb8, 0xfea45f6f, 0xf1c8517f, ++ 0x81fff4f9, 0x9cbcfc7e, 0x0733df51, 0xd4ea7fbf, 0x687cc34b, 0xb033f60f, ++ 0xdb07680f, 0x851b9d22, 0x117b203d, 0x36fbe311, 0xc657707b, 0xf7a803cc, ++ 0x8383d842, 0x777cc6fd, 0x4bf9207b, 0x13948dca, 0x39461729, 0xf9317292, ++ 0x222f583e, 0xe7e1de9d, 0xdecd6a7f, 0xe8cfb42d, 0xf2851c8c, 0x6dc7e3d9, ++ 0x7ade4857, 0x3f2109d9, 0xdbd17901, 0x521f290d, 0xd4fca45e, 0x2d98f90a, ++ 0xc5ca43e4, 0xe1e5b52e, 0x2eafd0f1, 0x369f13cd, 0x35272026, 0x43ed19cf, ++ 0x91857c9f, 0xa13b3646, 0xd55f2181, 0x57cc1942, 0x21e43eb6, 0xe4e2ed25, ++ 0x61769ac1, 0x34f0c4fe, 0x17fc4fee, 0x5a7869f9, 0x4462ff68, 0xa7e0f7da, ++ 0xc7ec7ede, 0xe7804eb9, 0xdbe82e4c, 0x4dbf00cc, 0xff71937e, 0x0f5f2061, ++ 0xe0933ac0, 0x4fed63de, 0xe7c99ff1, 0x51e20358, 0x45b303fa, 0x69f241bc, ++ 0x0801f82d, 0xae3fa4a7, 0x985c1607, 0xdb3a23de, 0xb8ac3a12, 0x650d993e, ++ 0x97d01fb0, 0x8be3fbff, 0xda6173a4, 0xaa8de985, 0x6fdc1fb4, 0xae83eaac, ++ 0xae87dfd5, 0xc44c85a5, 0x5aa5fc2b, 0x01e7d03a, 0x2aeef751, 0x91997945, ++ 0xdfb7df27, 0xfd420daf, 0x9c9c64c0, 0xa8ef1de2, 0xadf3beb2, 0xf93f6822, ++ 0xa3881661, 0x1389fbc3, 0x23e27a62, 0x6fb40b0a, 0xade57b4a, 0x66e784d5, ++ 0x69d29791, 0xa241fbe6, 0x7b750b9e, 0x50cf3d50, 0x47dbc75f, 0x70593b9b, ++ 0x8df208be, 0xece9c392, 0xe01ff20e, 0xa0cfbbf3, 0x0c2870bd, 0x09f51be3, ++ 0x833d5feb, 0xa155ad7a, 0x3c1ea9bd, 0xc528df78, 0x3bdd2bf8, 0xdfb7f54d, ++ 0xb4df79c2, 0x799fd79d, 0xbdfbbdfc, 0xd06e3166, 0x8b4b1cb9, 0x41be51a2, ++ 0xcacbe29e, 0x67ef8dec, 0x299fa4d2, 0x6e7461e1, 0xc33fa820, 0xe98bbc7c, ++ 0x9cc793df, 0xb6fdfd45, 0xf5fef88b, 0xa79f4213, 0xa1e425d8, 0xe4263728, ++ 0x54d337fb, 0x37117dfe, 0xa3c3efa0, 0x9f425aeb, 0x7c5f7f37, 0x4ff703b7, ++ 0xde5f9f08, 0xb0edf88f, 0xa49f7c4a, 0x74c644fa, 0x3ef83471, 0x7e3ff7d5, ++ 0x998574b2, 0xe033574f, 0xbbe6dbeb, 0x0fef4d35, 0x7a066fd0, 0xdf05bed9, ++ 0xdbe0423b, 0xffefefa9, 0xd8bd7a36, 0x6f82fbeb, 0xd63e48e7, 0x631efc74, ++ 0xc67f1376, 0xf40e2824, 0xe1dceba3, 0x10bd71ab, 0x917fcf90, 0x7dc8767c, ++ 0xf7f25e82, 0x5fca2975, 0xcf1e0f5d, 0xd07a8fde, 0xcf69ea6d, 0x35f251e5, ++ 0xbc02351e, 0xfa0fe852, 0xfbfda777, 0x024f8c7e, 0xaa7bd05f, 0x36e0839b, ++ 0xa18b63ca, 0xbf20c13e, 0x7f48fe42, 0x3c003da0, 0x4b7ea365, 0x06756038, ++ 0x3a7249f1, 0x9149f3c7, 0xc051de2f, 0x2c8ec9fd, 0xe74b8e5e, 0x7480e3fe, ++ 0xa221cf8e, 0x1044477d, 0xfc75d21e, 0x4b75c7e3, 0x4f09bcd0, 0x79482637, ++ 0x012b2b4e, 0xe388ee79, 0x4bad47ef, 0x109de35e, 0x1bc71ba8, 0x0cad2ebd, ++ 0xbe33d2f1, 0xd46df537, 0xbc0a378b, 0xefd75b8d, 0xa0946f6d, 0x3ee05273, ++ 0x2f0fe04f, 0xe45a83ea, 0x1e84250f, 0x5e9fcdee, 0xdfba7f43, 0x96feafbe, ++ 0xa9fc5ef4, 0xbc33fa19, 0xfbc2e0af, 0x1895ba0b, 0x40c93ae8, 0xbd4322d7, ++ 0x3a7dd65c, 0x72f52bfd, 0xf783eb65, 0x5c602524, 0x41e3a153, 0xa4be7e01, ++ 0xbe7ee50c, 0x70eff243, 0x9f806bc2, 0xfc8dbc47, 0xf245ad3b, 0x346ba5eb, ++ 0xa8a9c7e0, 0xea07c787, 0xa21ea1d7, 0xed32c8fa, 0x757b60b2, 0xdbd41ad9, ++ 0xed90afd7, 0xa6fed45d, 0x51bc72e5, 0x91d25ef4, 0xa2329cb1, 0x57b4ae6b, ++ 0xf7c6dfa3, 0xff78daf3, 0x6fb9e979, 0x8b7d077b, 0xf01b343c, 0xf750ceb2, ++ 0x723fda1a, 0xdcb6fb1e, 0xc36effd0, 0xfa86d5fb, 0x857d435a, 0x2cc57fbe, ++ 0x22b0e485, 0x1a53ef8f, 0x1fc8d2e5, 0xf1ef4d3f, 0xb9ec7b67, 0x9dfe4512, ++ 0x3726ae4e, 0xf4f2faf2, 0x2315b2fc, 0x0aebea82, 0x6e186e48, 0x2f9d06b5, ++ 0xf74b9d06, 0xd0fa591d, 0xe2fb0b9b, 0x7b46a1cb, 0x79e5d5ef, 0x23a1efee, ++ 0xaa976b87, 0x02abb7af, 0xedfbaf6e, 0xfbc15145, 0x70ca53ab, 0x3ee7d11d, ++ 0xacb4b78e, 0x622fd828, 0xd05a65a5, 0xe2fb653c, 0xf8a9ce6f, 0x2baf5fbd, ++ 0x8510db29, 0x7f629efb, 0x60978e33, 0xd7b4552f, 0x537e22f5, 0xb8ba798c, ++ 0xcfe1149f, 0x6822385e, 0x3065ac9e, 0x67fdb3ce, 0xad47bf2a, 0x8993e811, ++ 0xf2939dde, 0x8d32674c, 0x63db4ef2, 0x0eff1662, 0x99faedfa, 0xf4ed18ba, ++ 0x94f1c5fe, 0x74aff4c7, 0x15dd5ebe, 0x36692033, 0x6f23dbd4, 0x7edb7d23, ++ 0x772a44ef, 0x97535aaa, 0xd617b183, 0x0d459795, 0x8431f7c3, 0x37e91da7, ++ 0x5385e194, 0x824ee9ad, 0x48e713c3, 0x7b7f456a, 0x0df68595, 0x437e7e41, ++ 0x6dbf73fc, 0x2bb7ae14, 0x7da70e96, 0x4e5fcab1, 0x9d73c62d, 0x6858f795, ++ 0xe4d3a4bf, 0x679138a0, 0x93ca44d5, 0x945cb59a, 0x7ca9abde, 0x6dbf3fe5, ++ 0x5d9f73c4, 0x8f74284f, 0xb55f95ca, 0xea1239bc, 0xd2062bd5, 0xbb978bf9, ++ 0x7df7944d, 0x1f10ed70, 0x0a1f21e6, 0x51fca06f, 0x4fe74f68, 0xdf3acfab, ++ 0xf6c5cb2e, 0x385303aa, 0xf473c08e, 0x54ac8f9f, 0x9573c29f, 0x08f6d115, ++ 0xf23edfcc, 0xceb8a30d, 0x746c7b91, 0x28c1cb1f, 0x136badcf, 0x7a129ce8, ++ 0xe288ecfa, 0x0f00568c, 0x2fcfa51f, 0xe7c5494b, 0xf9cf4136, 0x878015d1, ++ 0xff0f530a, 0x8aa93d90, 0xd68ff5e5, 0x08db2bcd, 0xd8f23c78, 0x9b17ca10, ++ 0x38fb5fd2, 0x969df01d, 0x1f4beda1, 0xbb72f083, 0xf87fcaf5, 0x278be4be, ++ 0x6e30932a, 0xf5f05073, 0x4995ddcb, 0x57e1f7c1, 0x1f13349d, 0x2e7562bc, ++ 0x2334fba2, 0xceb82bfa, 0xc7883e06, 0xb12cf9b8, 0x5e7e016e, 0x7f842dbc, ++ 0xd2ae96d5, 0x25f7edb8, 0x06fa404e, 0xd22efaf8, 0x80deb4a7, 0x3bf499fa, ++ 0x8f8178d7, 0x6316db0f, 0xbe4f74ae, 0x4e15db23, 0x096cb278, 0x626785f7, ++ 0xc62b54fc, 0x65a52c7e, 0x907b34f0, 0x9ff68a1c, 0xef7e797a, 0xd71ed0a7, ++ 0xff7a9f7d, 0x3f783d8f, 0x8eafb643, 0xb9d17bb6, 0x9bb76a38, 0xcdfb1e91, ++ 0x7e608e4b, 0x1613d55a, 0x4f5503b2, 0x85ddde24, 0x06f807fa, 0x79c66be3, ++ 0xd0b7f7e5, 0x5fdefabc, 0x68acb7bd, 0xa57af042, 0xd2e55be9, 0x6ca9bfde, ++ 0xe5be88c3, 0xf5c1dab2, 0xfc13f153, 0x31ead6de, 0xb79d3376, 0x8dd5e27e, ++ 0x41772e74, 0x9b9e0e78, 0x46c27ea8, 0xdbb4eaf4, 0xf0cb8ebd, 0x1cdd813c, ++ 0x7f5a650b, 0xd47f2fae, 0xa14fcb9f, 0x3961ccca, 0x0939d254, 0x7c787fb9, ++ 0x628fc3f1, 0xcce7e5fa, 0xe01c6337, 0xf9c6b4ef, 0x9576f4f4, 0xfdc68fe2, ++ 0xb7d7dac4, 0x77d9f359, 0x63ec4fd8, 0x7586b11f, 0x43aafb8a, 0xf71a27ef, ++ 0x8bfb7311, 0xfb3d49f3, 0x6fba1688, 0x23ec5aa2, 0x0853ae16, 0xfcc5eafe, ++ 0x78c28f3e, 0xbc3e3f1e, 0x0860f804, 0xc8ebdfcd, 0x6e683cc1, 0xe299aa7f, ++ 0xaf5f830b, 0xe280b75e, 0xbe859b99, 0x8bf710a9, 0x65770a1e, 0xeabf7ae0, ++ 0x73c27089, 0x7ee66ff5, 0x9e2e58f4, 0x084d2bf7, 0x8b5f5f5e, 0xe34891fc, ++ 0x2c973c33, 0xf4ba39c7, 0x699f74e7, 0x4eb093e1, 0x58ec3cc6, 0x998decf6, ++ 0x0cd4b748, 0xed94efdc, 0x6cfd97aa, 0xeb076f30, 0xb9273c6c, 0x35f7e552, ++ 0x3d91b0ed, 0x614f9904, 0x67b7e741, 0x6add7f2d, 0xa58cf6e5, 0xb67e158c, ++ 0xed5e7033, 0x2bc7bc20, 0xb9c5ea01, 0x793f8934, 0xc4c2aa9e, 0x372c79ef, ++ 0x0ace7429, 0x4f9d1a34, 0xee7f49fa, 0xb288d6df, 0xe745c322, 0xd8d76a74, ++ 0xf932cb5c, 0xc8e73d38, 0x6b579d61, 0x7da2a8ea, 0x28da3fcd, 0x3cbf52be, ++ 0xe68f0b5c, 0x8dcf18f9, 0xb36abca0, 0x75c70e35, 0x5c9d71f2, 0x7df3c07f, ++ 0xb1a7dc66, 0x1b58fd73, 0xe28ef80b, 0x8b1a638c, 0xca3241f7, 0x52f1c4a3, ++ 0x577d0647, 0x539dcf11, 0x074676af, 0x6263ddc6, 0x833e302b, 0x448d87ed, ++ 0xb8cfc5fc, 0x467ae101, 0xe4067925, 0xbf43c9ac, 0x347519ef, 0x562bb7ae, ++ 0xfd462aee, 0x28eb7f3b, 0x2ac1293c, 0xec9f7d9e, 0xf7417cc7, 0x5687914e, ++ 0xafbc7509, 0x93c859ae, 0xa2f1e547, 0x491f8166, 0x76bef97f, 0xefc785a5, ++ 0x62a3cf41, 0x31fa5da9, 0xef6b5b8d, 0x5bfd4248, 0xe742c3bb, 0x70161fb4, ++ 0x3fed2e57, 0x53f01f61, 0xee8625a5, 0x96f1aced, 0xd35eb15a, 0xd03d50ac, ++ 0xf903312f, 0xcfe58bf3, 0x1cdf2347, 0xa367f70a, 0x105aea5d, 0x87f3a2ee, ++ 0xfbaf1e0e, 0x9d367962, 0xe8e59a57, 0x277de3b0, 0x8c0d16b3, 0xdfbdfd43, ++ 0xfbe2b7e1, 0x26992dfd, 0xc70e6bac, 0xe66bac04, 0x85fea8cb, 0x1fa173c8, ++ 0xd38527e4, 0x2ecb66b7, 0x9f3dfe2b, 0x4f7cc5e7, 0x60fef33e, 0x66d4ff8c, ++ 0xbb460c74, 0x9c1ff402, 0xacde7886, 0xdbae5d90, 0x25dbf3c2, 0xfe90ebfd, ++ 0x04f36f20, 0x3fb6ebdd, 0x839413ff, 0x4e7fa43a, 0x3e01fe6f, 0x9fcf4dde, ++ 0x78cc5f5b, 0x27c8ddff, 0x7d418ed2, 0x70e305b9, 0x156f5e56, 0x45e78478, ++ 0x0477b9fc, 0xc9ebabcf, 0x7ff1d043, 0xb0fdf45f, 0x5b47d8bf, 0xfb7d236a, ++ 0xea17ce21, 0x44772b9d, 0x3e4efd23, 0xdc35ebb3, 0x0e7da967, 0x8433b4ac, ++ 0xd47c081c, 0x09a3fce3, 0xea2ff27e, 0x81d1be71, 0xbdf0f7f9, 0xc67abf90, ++ 0x5be727e7, 0x97f3166f, 0x8fff45ef, 0x61af1e84, 0x87db5f02, 0xf2137970, ++ 0xf74bf285, 0x79f989b1, 0xb8f7f4e2, 0xf9fc159e, 0x73279899, 0x7e2344b4, ++ 0x77a8be90, 0xab347f80, 0xe4d023d4, 0x94f5d6e4, 0x25e92fc7, 0x3867b7e1, ++ 0x62d13da5, 0xec7402e3, 0xd55ee3ec, 0x39be087f, 0x46724f70, 0x8befe02b, ++ 0x1d9d744d, 0xe839abf1, 0xe46f927b, 0x9e9f0af7, 0x1bce2d7a, 0xf8e3f7c6, ++ 0xbdfbbbf2, 0x671c6691, 0x21f2e33f, 0x597297e1, 0xb5cb78d8, 0xddb1a2a3, ++ 0x11c0fb49, 0x7dfe6f38, 0xfa83867b, 0x402fe86b, 0xa155ad7f, 0xb101f5b8, ++ 0xcf703fce, 0x2395d1f3, 0x991efc02, 0x97ff08a1, 0x708cc5c7, 0xf093fe4a, ++ 0x71e389ee, 0xe16f0961, 0x8b5fd7bd, 0xb8dc25cf, 0x9fcc145f, 0x4f927f12, ++ 0x233d39e5, 0x49af12bf, 0xcdf6aa3b, 0x07e9f5d7, 0xd7a75f28, 0xc278e373, ++ 0xf2243a1f, 0xaf7ebbcb, 0xcbcbf3f2, 0xceeb7653, 0x15163111, 0x2e966f6c, ++ 0x8f91dab8, 0x145bb7fb, 0xed21c73a, 0x36acfc08, 0xe91fd907, 0xe0c82c0f, ++ 0x09f52af9, 0x63a471da, 0x628eb1cd, 0xfa524fbc, 0xe57e57a1, 0x5e306357, ++ 0xbde79db5, 0x39a97e49, 0xa0e49bb1, 0xaa7b9c56, 0xe97ef958, 0xdff7e438, ++ 0xa75f685b, 0x56899ee2, 0x6ee7eff4, 0xd116399c, 0x5022e781, 0x30df1faf, ++ 0x87a13466, 0xe0669239, 0x0f0d88f9, 0x9e09b8cf, 0xe9556acf, 0x071c181e, ++ 0x8ee2b7e5, 0x3d5f14d1, 0x3a59de14, 0xbbf8fd1e, 0xf1fa0754, 0x731c6c57, ++ 0xc2bfb637, 0x2e96203e, 0x4f10d9ef, 0x431ccd75, 0xbdfa41f6, 0xd1b01f32, ++ 0x737fe9c2, 0x69a79706, 0x9be7253d, 0xc1c6c6c2, 0xb5df1fb8, 0x61ee9c3e, ++ 0x5b3ab72a, 0x97bdf8fc, 0x519d6992, 0x737fe56f, 0xfdc298e2, 0x165639b2, ++ 0xcf439a96, 0xf9e152c3, 0x3b8e96eb, 0x7ebc8ed0, 0xde147d87, 0xb3d4cac3, ++ 0x3fb92b63, 0xe31df7cd, 0x43beee99, 0x194dc709, 0xe38ddf9c, 0x707bfec9, ++ 0xe747111d, 0xf1ffa913, 0x819fbfe5, 0xa6f8f076, 0xf79c38ec, 0xe9c297d1, ++ 0x8b51c13c, 0x8ba59efe, 0x3c65e73d, 0xadcf251f, 0xf3e864d6, 0x9fdf24c0, ++ 0x1b077cef, 0x4b797174, 0x3a309627, 0x60caedf7, 0xc8a2ddf4, 0x3e61b66f, ++ 0xcdb35561, 0x0e62e781, 0x7ee3ff23, 0xee950ed6, 0xdcb3a1e1, 0x3bc3af40, ++ 0xdef9d346, 0xbd784faa, 0xe1f145aa, 0x0fdde479, 0x0af94bde, 0xc4bfc1b3, ++ 0xfe3d9c23, 0xce0f23f3, 0xed383140, 0xb9e134f2, 0x789bd3fe, 0x7baf457e, ++ 0xf6df5e1a, 0x7ff3aa5a, 0xf1965fdf, 0xf433c788, 0xbe25fae7, 0x15ea3ae5, ++ 0x9cbc8be0, 0x5cbefe00, 0xe5fc8732, 0x543c4b13, 0xac0e529e, 0xd9f902b9, ++ 0x08e7431e, 0x587d6c5e, 0x6a667bc5, 0x8b3a8fb7, 0x51f1e1eb, 0xd2ff7431, ++ 0xd3164b97, 0x2589e626, 0x6b8fe20d, 0xd47a132d, 0xdb95e547, 0x97dfa9db, ++ 0xf0dba3ad, 0x51cbee9c, 0x69ad5c31, 0x1f7bba79, 0x3afb7d25, 0xf5e72c7f, ++ 0xce9c5df9, 0x37cfee12, 0x79c68ccd, 0xdf1e3fb5, 0x37d23976, 0xfe81c632, ++ 0x27c8b55f, 0xfb96b239, 0x62c2c7d5, 0x7402577e, 0xbaeeb63e, 0x6807bc24, ++ 0x19f4fb76, 0x25eabcf8, 0x01eb81c5, 0xa3534bd7, 0x99f6fd71, 0xcf1a33b9, ++ 0x56b67d4d, 0xd1f2b79e, 0x3f1b6fdf, 0xed875d89, 0xcccdfbc7, 0xc65b4999, ++ 0x9f972fc4, 0xd7f9d330, 0xc539e02f, 0x5046ce4b, 0xe27e04bc, 0xf6647f31, ++ 0xd2ce3c0b, 0xeb15deb3, 0xbcc42bbd, 0x71c466cf, 0x85e7897c, 0xd1f9fc79, ++ 0x70cadb75, 0x2c1be3bc, 0xcbfb840e, 0x7f1a160d, 0x4cd3ac1e, 0x4db1ef00, ++ 0x7583dd7c, 0xdf1f375c, 0xf337d7c4, 0xa6faf85a, 0xe3458176, 0x7cf545e7, ++ 0x8ed41859, 0xe3eb0dee, 0x1a79911e, 0xb03cdf9f, 0xf3df389b, 0x6b2c6ff1, ++ 0x1766f3a1, 0xe46a3f9b, 0xfa19d3df, 0xdf0f5ef5, 0x022fc5f6, 0xc8ff28af, ++ 0xe62f92b7, 0xf8fbe5ad, 0xf2a32d71, 0x9f24ff91, 0x6bd5ef18, 0x2f7e32b4, ++ 0x85c229aa, 0x946a617a, 0xe2f682d3, 0x22ce84ba, 0x032dcf44, 0x0b557eb8, ++ 0x8b9e1a4d, 0x90b68d63, 0x0e4578f7, 0x43d6fee0, 0xffcf1803, 0xf9e0e01f, ++ 0x987ce29d, 0xf55ec12c, 0x353e7b47, 0x4e1fee32, 0xe4f29268, 0xe06629aa, ++ 0xc457a9eb, 0x05d031dd, 0x99b278e4, 0xedc747d7, 0xd67a82c8, 0x98a60780, ++ 0x2f537e61, 0x81631b8b, 0x0fa5d2fa, 0xfa82294e, 0xa4b40355, 0x39df4101, ++ 0x3fb931be, 0xa79e0fce, 0x13a7f3e2, 0xd658e93d, 0xa762f38b, 0x8b91ae94, ++ 0xdfed0333, 0xffbec97d, 0xdea06745, 0x8f746169, 0x3f8410ce, 0x6ab2efb1, ++ 0xbfcd9680, 0xc95e7fab, 0xbf943dd8, 0x74e7e5e7, 0x961dc7e0, 0x38a8e784, ++ 0x73ca55df, 0xe70c2b3b, 0x7cfc5c76, 0x254f3c9a, 0x0b0d4bcf, 0x775b379c, ++ 0x4ecde731, 0x71dff859, 0x79fd3453, 0xcfeda531, 0xa3588f74, 0x13867597, ++ 0x70e7f41d, 0x4b5ef16a, 0xbcf693c0, 0x74051fdd, 0x244cf85e, 0xe95cc7c9, ++ 0x88f278f7, 0x05bde5df, 0xf89e33cc, 0x8fc10ef1, 0x86b09747, 0xbfcc1641, ++ 0x19a5f9de, 0xe11918e0, 0xeb801d29, 0x8cded35f, 0xe7944e85, 0x3ff468c6, ++ 0xbaab3e4e, 0x8d7da04a, 0x86d95ff0, 0x5417a144, 0x7ef055ff, 0xa7b0e64f, ++ 0x2f5d1ed0, 0xa644e9f8, 0x23ef033f, 0xf5f266f2, 0xbca3b412, 0xaecb49ba, ++ 0x2776c44e, 0x683bdeb6, 0x06cdd036, 0x6fcf07ea, 0xe663035d, 0x77bdd1c5, ++ 0x687da54c, 0xde17d11f, 0xf0e3a37b, 0x3387bd3e, 0x3a2339c4, 0x23e9283f, ++ 0x1e8bdef1, 0x6ff469f0, 0x82cc614d, 0x6c61d8eb, 0x3cddfd1d, 0x61a39749, ++ 0xbc921cfc, 0x0ee17557, 0x33a1871e, 0x714ea294, 0xf1f65ea5, 0x995ff255, ++ 0x47b507b8, 0x799bacff, 0x6f32f661, 0x713f15bd, 0x5d7376d1, 0xb3bd4861, ++ 0x3bd08074, 0xe0a8d8a3, 0x45ab637b, 0xb96a899b, 0x5bcfef13, 0xf7461898, ++ 0x627c2c97, 0xf625d920, 0x7eb4ddc8, 0xbad8ed96, 0xa697e278, 0x30e8954c, ++ 0xbca155b7, 0x34d6d2ca, 0x255784e6, 0x4654f1ad, 0xf3d2a777, 0x337bbfe3, ++ 0x4e25eb97, 0x49ffd2a7, 0xa63ca02e, 0xc05219ff, 0xf78debf3, 0x9f3c7122, ++ 0x9b3c7376, 0xfee8c3bd, 0xbfb88b5a, 0x78e334f6, 0xdf9d3d3f, 0xcf7a7713, ++ 0x89da3321, 0xf42a57e9, 0x08d443a7, 0xfbc6e7ce, 0x6d7e256b, 0xfbc63e82, ++ 0xfdc51b6c, 0xdb5ef28f, 0xbebb45eb, 0x219db5ee, 0xd47d71d0, 0xc79c129c, ++ 0x7bc5d1bd, 0xb8647d68, 0x46a6d6d7, 0x660f9059, 0x31e9eb94, 0x6ebeba7d, ++ 0xd277f099, 0x860996c7, 0x7d3525fb, 0x84034ffd, 0x0d8c39bf, 0x5ffee3eb, ++ 0xd3f4fd0d, 0x0fe38d9a, 0xfa8679ef, 0x61fc208c, 0x74e9cd3e, 0xdeefe133, ++ 0x352f8e70, 0xfc8bdf82, 0xcefdfbff, 0x8d9c7bc6, 0xdf0f34f7, 0xbf5750b4, ++ 0xbaa7e5b4, 0x2eb597f6, 0xe51fbdd3, 0x3f7ba55f, 0xba43cf7a, 0x5f8e98fa, ++ 0xdb8fdaeb, 0xfdee94f7, 0x759b9de5, 0xf638afef, 0x657eae9c, 0xed749fd7, ++ 0xa9deeaaf, 0x37b3e7ab, 0xc30bed75, 0x27d5d7de, 0xae8ffe3a, 0x8729d5fd, ++ 0x71afef74, 0xff7ba17e, 0x57f600ff, 0x80004ec1, 0x00008000, 0x00088b1f, ++ 0x00000000, 0x7de5ff00, 0xd554780d, 0x333ee8b5, 0x4c927e67, 0x66109392, ++ 0x9c24c926, 0x06091fc9, 0x80d22219, 0x603f2641, 0x820c29f8, 0x03b06d1a, ++ 0x9942a2a2, 0xd9f05a00, 0x13f0c4ce, 0x7a836d28, 0x80ea0221, 0x9f5f5ca8, ++ 0xcbd6b45f, 0x2009bfc5, 0x446977f2, 0xdf5f4feb, 0x16bd01bd, 0xa40758bd, ++ 0xeb4bda3e, 0x7ded6b5d, 0x13267392, 0xded7ef40, 0x7df2fbbe, 0xf7b59b7c, ++ 0xbdaf7b3e, 0xaf6b5af6, 0x673af6b5, 0xc17f95a6, 0xbfa33b54, 0xb7dfe0af, ++ 0xd4ceff7d, 0x63d87ef2, 0xabd5da0b, 0xd3e63fe1, 0xac61cb32, 0x86c4ae6d, ++ 0x7b3b1978, 0x583db670, 0x9aaa58c9, 0x1a71f39e, 0x8ab057b4, 0xa58cccaf, ++ 0xc318530c, 0x30ac25fe, 0x49b19230, 0x1b189ae6, 0x4b77fd03, 0xd8ca9b3e, ++ 0xbb4716e7, 0xe498c994, 0x36456c67, 0x05bff263, 0xb3b412fc, 0x4f7c907f, ++ 0x35667b41, 0xcfe6e9d4, 0xac99dbf2, 0xa3486fc3, 0x06878062, 0xaefe86dc, ++ 0x9ed0d526, 0xb4372c1b, 0x19f42fe7, 0xb55082e0, 0x15b0ffa1, 0x8dec037e, ++ 0x17fa1a34, 0x700c07b7, 0xa1934769, 0xa0cef0ff, 0xba22bda1, 0xc57ed0d0, ++ 0x1e0190ae, 0xd0c2b5d9, 0x88eed47f, 0xac747da1, 0xd57ed0dd, 0x7c030ec1, ++ 0xa1a74f75, 0x8fdeb7ff, 0xf5c7da1a, 0x5fb432ee, 0x00cbaa73, 0x36ef884f, ++ 0x3e789ff4, 0xd96b8066, 0x7aff4321, 0x78065bfb, 0xa181f292, 0x13ee75ff, ++ 0xea29f686, 0x49768627, 0x15735855, 0xcfcad363, 0x795feb18, 0x95d20ff3, ++ 0x307f7fc8, 0xf3a91f3c, 0xc88fe433, 0x4daf920b, 0x5aa16c65, 0x6365fc44, ++ 0xf80537ac, 0x00122dad, 0x580c64de, 0x5f0195a9, 0xe2244666, 0xd631602b, ++ 0x00a38d9c, 0x2c658ed3, 0xcf0bff03, 0x6eb1ca67, 0x936c8009, 0x30721bd7, ++ 0x2956c696, 0x267cc31f, 0xaeaff560, 0x6ff13982, 0xb812c0e2, 0xe1ac7d92, ++ 0xa7ddf30b, 0x31e3c232, 0xca0f7835, 0xcf5dddc7, 0xaa87ce4f, 0x0d6458bb, ++ 0x5cc931e2, 0xf20bd999, 0x7d852c71, 0x70395037, 0xa07629bc, 0x43be6e8b, ++ 0x2a9e1d29, 0x4ff3e0c7, 0xfea69fb1, 0xf85ae37d, 0x6fac12b8, 0x9ffc6ea9, ++ 0x0b530184, 0x90611d63, 0x1ec6529b, 0x3f042b0a, 0xbc137612, 0xd952ac29, ++ 0x72a72e19, 0xed47d84b, 0x04d5c2db, 0x13f61e3f, 0x52370d1c, 0xa01c23b9, ++ 0x26e19dfa, 0x070e9f82, 0x5e15dca9, 0xe1b3e548, 0x2cffb510, 0xe7e082bc, ++ 0xbb2a11c2, 0xff54edc2, 0xe083b842, 0x049dc317, 0x528e14bf, 0x8bbc3bb9, ++ 0x2ee13dca, 0xbc257f6a, 0xc2d7e09b, 0xe1638231, 0x0def0483, 0x3fbc10f7, ++ 0x07c13efc, 0x1e54bdc2, 0xf2a29f0c, 0xed4e3870, 0x09e7c347, 0x66afdfee, ++ 0x902be3e5, 0x57d3413e, 0x05b6d057, 0x14ee0f90, 0x3272c07c, 0xec64e665, ++ 0xeca5be0e, 0xd85b1353, 0x53bff405, 0x8ea5a1f0, 0x77c031b1, 0x1db2bc96, ++ 0x6adc5e6d, 0xe27293e0, 0x0d5fa393, 0x013e7cb9, 0x852505ce, 0x91cacc7c, ++ 0x4d72b4df, 0x5f22342d, 0xa7d148b7, 0x84ddd4bc, 0x73b52cf8, 0x1d9926fc, ++ 0xaf7cded4, 0x8c49b514, 0xc45995cd, 0x9bf3720a, 0x912b8c94, 0x2c86cfb9, ++ 0x4bb632e5, 0x24583ea9, 0x416affc0, 0x862fe0e4, 0x57ddff2c, 0x7bd7db6c, ++ 0x866af1fb, 0xfcf04de7, 0x0c5a6ed5, 0x2d07666b, 0xfbd40788, 0xaa2720cd, ++ 0x055fb82b, 0x302eef3c, 0x3c28ac45, 0x2059688e, 0x5706b19d, 0xefe44df0, ++ 0x0fdba1b3, 0x2a77e0e0, 0xe79c32be, 0xd0d8b6db, 0xf8fe609b, 0x876fb321, ++ 0x963d383a, 0xa5014c74, 0xd7f6917d, 0x0104f13e, 0x9b3fc68f, 0x63ff4883, ++ 0x28a6f496, 0x55aff3f0, 0x6bf6e889, 0xdf2864d5, 0x403f0571, 0x0f4cbe7c, ++ 0x12026add, 0xcb6d797e, 0x4960cbd3, 0x99a52dcd, 0x84cd1e78, 0x8cc5632d, ++ 0x05aa62cd, 0xe66cc2f5, 0x430bc37f, 0x0482c0dd, 0x5422c4df, 0x278339d6, ++ 0x599b9c71, 0x78e0e094, 0x75b2615b, 0x19f5e225, 0x963575e2, 0x72694326, ++ 0xfd234f07, 0x13f74cbe, 0x5dc6c75e, 0xd2eb8657, 0xab73aaf0, 0x160cff84, ++ 0xfbf11c7f, 0x1f33d5f2, 0xf903c54b, 0x17c02fe3, 0xfb1e180e, 0x73ec2b31, ++ 0x3e0ac81b, 0x8a52b6df, 0x7c6b5f22, 0x7cecccd1, 0x5ea007dc, 0xf009f3d2, ++ 0x4bca1547, 0x3a5670bc, 0x178a49f1, 0x399c64f9, 0xeb051d62, 0x24cb4534, ++ 0x5587f133, 0xcceefc02, 0x1a28fe01, 0xd7be0f9c, 0xef4ea50e, 0xc10d7f01, ++ 0x8ff77ef1, 0x7a472adf, 0x9c6d792d, 0x336af48a, 0x1f003ec1, 0xc99b0e47, ++ 0x9542602e, 0x1919af9b, 0xb266be45, 0x246b37cf, 0x83d717ee, 0xe2b666dd, ++ 0x767a24f9, 0xd7ef978c, 0x31a5b731, 0x3972e34a, 0xbd2bdad7, 0x452aff7c, ++ 0xbf2da5bf, 0xfc06645d, 0xc4fded8f, 0xb24c8eaa, 0xba3f158e, 0xcfc744af, ++ 0x989f764b, 0xb7a24fec, 0x34f18a67, 0xd35b31fe, 0x7a1ddb83, 0xc0bcf8bc, ++ 0x917957cf, 0x9f80b39f, 0x3f9f898b, 0xcd8c2386, 0x3799a9b0, 0xa40bd941, ++ 0x7c194189, 0xdf22b142, 0x2a3e67cc, 0x9500b017, 0x23f6c277, 0x1b2206ff, ++ 0xbbf748ad, 0x7fd51759, 0x2736faaf, 0xa61df3f2, 0x8bc22160, 0x2fd50f58, ++ 0xdc06f161, 0x5bda1bda, 0x190370df, 0x9c6c7767, 0xbdf40b94, 0x0def3a3e, ++ 0x94ed672c, 0x24a88e3e, 0xaf11931f, 0x3ab4295e, 0xe5bfe60f, 0xf3abb567, ++ 0x99867ea1, 0xc23b0bef, 0x1fd345f7, 0x7906eb89, 0xfafb8198, 0xd69f9665, ++ 0x3468ce65, 0x83f343c8, 0x38c12fcc, 0xd16d57f1, 0x7c9d5e1d, 0x2ff3df54, ++ 0xe4c7a8f9, 0xdfb8adf8, 0x65b35e4b, 0xcddf7ee3, 0xf92f39f8, 0xbc88ddb9, ++ 0x4677cfc6, 0x4b0f7efc, 0x4fbf61f5, 0x5a7f7f05, 0x3fbf88c0, 0x559f9895, ++ 0xac9ddbf5, 0x2aaee830, 0x97a73fee, 0x25767e98, 0xf1ce09d2, 0x77bd71db, ++ 0x66b5d87f, 0x7ff517b4, 0x0eed10b4, 0x5f36b3cb, 0x9e70d79b, 0x50d2afb0, ++ 0xd21884c9, 0xee3827f3, 0x497881a8, 0x80fe07d5, 0xcacd8676, 0x922af622, ++ 0xe516366f, 0xf24acf3a, 0x2da486d5, 0x2a0279c6, 0xf8e27dca, 0x07be04c7, ++ 0xbe2664ff, 0x9e7ac08f, 0xc3cd9292, 0x6a5b2bcf, 0x3fa43cff, 0x59e68c9c, ++ 0xac72e5e5, 0xbd1cc7cd, 0xebcbb41e, 0xb86d82d3, 0xb8f8a03f, 0x7eb8517e, ++ 0x6dfde839, 0x8ccfee09, 0xbd34ebf1, 0x6bb1e34c, 0x663a3eb9, 0x1f082351, ++ 0x40faf5ab, 0xd9e9f573, 0xbe6fd599, 0xb4cc788f, 0x2866623b, 0x74e58d59, ++ 0x160e76af, 0x33bf9ff5, 0x86b7f3b5, 0x8433bf9f, 0xbb44cf68, 0x3e639f0c, ++ 0xc157e20b, 0x63d1a37e, 0x9ab79e1b, 0xde701c7e, 0x907ac2c2, 0x62eab27e, ++ 0xf8952e50, 0xcafe97fa, 0xbed08d1c, 0xaf384df9, 0xc64fe855, 0xae78e542, ++ 0x9abbcf69, 0xf83155c0, 0x6256760b, 0x031417f0, 0x1b72105c, 0xa15b0ffa, ++ 0x91bdda1a, 0x717b4372, 0x9700cfbb, 0xfa1b5476, 0x1bf4ef0f, 0xa3688ae0, ++ 0xbb15ffa1, 0x64780602, 0xffa19357, 0x4341dda8, 0x42d8e8fb, 0x0755fb43, ++ 0xeaf80643, 0xfe86159e, 0x623f7adf, 0xdbd71f68, 0xe6bf686e, 0x9e018754, ++ 0xf434ef10, 0x6a3e789f, 0x7f65af68, 0xb7af686f, 0x9f806f3f, 0x146a73c0, ++ 0x68ff0dfa, 0x773aee78, 0x3c7e01b7, 0xf6076335, 0x321ea29b, 0x37f62f3e, ++ 0xc92a7372, 0xb7f2b4c3, 0xf7dded0c, 0x0cdcd88f, 0xdfbd12f2, 0xa6e6fe44, ++ 0xb14e7e46, 0x07ce3aa6, 0xb7efbc29, 0xe6181f7d, 0xbdc7342b, 0x59aac7c8, ++ 0x2eb943c9, 0x17b59ea9, 0xf9958ed8, 0xdd50ea5b, 0xdc6e3795, 0xc088e58b, ++ 0x362875f3, 0xed6f4d95, 0xe0caf2c5, 0x63603a99, 0xb5985be6, 0xd0aacb0f, ++ 0xa2177ae8, 0x3ed662b8, 0x5a46c72c, 0x82cf51ea, 0x9de9f859, 0x23eff780, ++ 0xc07ad823, 0xf80f232b, 0xfdeb12b6, 0x73cbb7c4, 0xcbe7244d, 0x5144766f, ++ 0x71af392f, 0x6cb4e8c8, 0xef86870e, 0x7ce69d07, 0x818ab9d8, 0x5d83b47c, ++ 0x760e1d1f, 0x58f9d802, 0x7c760a3e, 0xf5a19c14, 0xb963e760, 0xac7cec01, ++ 0x3e760adf, 0xab87cec2, 0xe5b9f1da, 0x58dedd6f, 0xbb0fe304, 0x2cd05657, ++ 0x5a9aab5d, 0xee3e02f6, 0xea0aad7b, 0x91f7ab12, 0x28f01514, 0x8c780c58, ++ 0x91f8b227, 0x022e8fd4, 0xc38f21c3, 0xddcfd029, 0x9dc03262, 0x4d823ff8, ++ 0x7e7c0691, 0x9df2c6e4, 0x8aaff03e, 0x805b675a, 0x3dc519d6, 0x42cf6f37, ++ 0xc0e7f998, 0x2f71393e, 0xee3ffc60, 0xa9159ac8, 0x543f081c, 0xc229c81a, ++ 0x55dc81f8, 0x0caa7281, 0xe22e4dff, 0x53eeaeb5, 0xfa81499f, 0xfdacc648, ++ 0x86c78eb0, 0x013c72a6, 0x672f95ae, 0xd1617f5c, 0x750faa50, 0xc523d125, ++ 0xfadcfc45, 0x33b71163, 0xfd414fe1, 0xc22ce2e4, 0x6527605c, 0x3cddbe82, ++ 0xf409c56e, 0x22256421, 0x17647ea1, 0x82b1f9e0, 0x4f04c504, 0x1738054c, ++ 0xa04fa061, 0xd71a382c, 0x76320ae3, 0xb9a7c752, 0x66f08d0b, 0x9693cfd8, ++ 0xdf2c7c7e, 0x58644535, 0x80c9e583, 0x6cf307cf, 0x05eb0b9b, 0xe8d5b378, ++ 0x31370e4f, 0xd61e2fb2, 0xdb30bef0, 0xc3da7687, 0xde7edc45, 0xfaaf2e12, ++ 0x9efe82c8, 0xf023eaaf, 0x8616f28f, 0x57e820a4, 0x17c07357, 0xaf967e81, ++ 0x456dde7e, 0xeb2efec6, 0xeb1cf3c2, 0xcf76755b, 0xcb5c6275, 0x9ba26657, ++ 0xcbe02da5, 0x316fcdd6, 0x24aea14b, 0x458dd776, 0x8dae7f32, 0xdf65bb51, ++ 0xf985494a, 0xd2a39af2, 0x484e34ed, 0x2bbd41f2, 0x9bf3ebc6, 0x0005a4bb, ++ 0xe9522aaf, 0xfc9c6d39, 0x8ebf8085, 0x22396e4e, 0xfbbcf029, 0x74848881, ++ 0x1f012b70, 0x075a474b, 0x0997be48, 0x18af7699, 0x10d1f55b, 0x0be03bc4, ++ 0x34d37ce0, 0x0c290b79, 0xf7d0f9f1, 0xd73c5acb, 0x4f66697e, 0xea85f141, ++ 0xb249cccb, 0xf5b4ad0e, 0x22ff999a, 0xe1464c7e, 0x273a21fd, 0xa5a8716f, ++ 0xdc4fbf20, 0x9eda68ec, 0x8956cf84, 0xa79b597d, 0x1f1c5b9d, 0x49d399a7, ++ 0x50beaf3b, 0x7a68ff38, 0x8716596b, 0x159671b5, 0x31bd218c, 0xceae3e18, ++ 0xe1d41614, 0x51e619bb, 0x9fdb7c60, 0x1ba4145a, 0x9a010ef8, 0x74fae64f, ++ 0xe4e563fb, 0xcff2262f, 0x89003900, 0xbe42accb, 0x01b68dec, 0x5ae6d8df, ++ 0xba2f687d, 0x4246b87e, 0x3ac7923d, 0xaea3d424, 0x32838682, 0xb072e79e, ++ 0x8ec49022, 0x683c94be, 0x25d9a9fb, 0x7d4ff703, 0x50ec96af, 0x5dbe430b, ++ 0xb85d55ea, 0x2e9f1a7f, 0x3b34343d, 0xe7cfdba8, 0xb3571f05, 0xe9ca330e, ++ 0x6545d678, 0xf2a1eb0d, 0xd2a7165a, 0xcb1914cf, 0xb2a3e63a, 0x9ca80581, ++ 0x365442cc, 0xa72a0eb2, 0xa72a2eb2, 0xc12a1eb3, 0xc032a3af, 0xaf3ff214, ++ 0xcb063b07, 0xe5402c39, 0xe5442c8d, 0x4ddfc13e, 0x5be083ac, 0xbb951758, ++ 0xe1d5fe41, 0x53b10f18, 0x73e80af9, 0x7d035f2c, 0xf40c658e, 0x78c36ab9, ++ 0xfb953948, 0x0f2a3ec3, 0x3ca9ab84, 0xbf53f618, 0x2a46e1c3, 0x5403868f, ++ 0x51370b1e, 0x520e13d9, 0x85e1e3bf, 0x0e13be54, 0x786ef951, 0x87ef9505, ++ 0x3afe5423, 0x70e54edc, 0xa415e82b, 0xe8ef7977, 0x0a1f81eb, 0x55fab43f, ++ 0x8b328f38, 0xcfb2dfb9, 0x8abbfa6f, 0x268fb831, 0x5731c58c, 0xf90932c3, ++ 0xf26e55d1, 0x5f5ca147, 0x0dba54be, 0xb8c7b5ca, 0xa5736b1d, 0xeaec9d93, ++ 0x30a92e5c, 0xd7a96eee, 0xfb7b069c, 0xcf163baf, 0xdd8057b2, 0x955b0af0, ++ 0xe97843e6, 0xe1f03b46, 0xbe284b76, 0x8b7bda1d, 0x70ecb342, 0x3f4f8c8e, ++ 0x72cf6ffe, 0xedc7da98, 0xc00a6d67, 0xdee3b6ff, 0xc712398d, 0xeff09503, ++ 0x6acc568b, 0x954f1195, 0x0bc67cf0, 0x19fa360e, 0x67e41d2b, 0x393cee8c, ++ 0xb8f004da, 0xf42a8e15, 0x28fd758f, 0xbf583d4e, 0xb9ed76c4, 0x36ce2d6d, ++ 0x8fdac3a4, 0xaa813dc1, 0xd1dee2c2, 0x8fd38f18, 0xf9bcba6b, 0xf322f999, ++ 0x1749fbeb, 0xe6502f19, 0xbfa2f7ff, 0xe44f3e01, 0x1f57cb6f, 0x78a26f3e, ++ 0xe78d9298, 0xae2ccefa, 0xa905e277, 0xf7801dd1, 0xaf016cce, 0xad75a12b, ++ 0xb5d61845, 0xd9117d76, 0x02533bf1, 0xfb610f4b, 0x1dbe4d8f, 0x3533b4d0, ++ 0xe082beb8, 0xacd38a12, 0xe3950ecd, 0xc69854b9, 0x9e4dc7cf, 0xfd5453fb, ++ 0xcfcc5939, 0xe735cdf7, 0x3fa3b67a, 0xa5626ed5, 0xf68edcf0, 0x61caebf9, ++ 0x8037279c, 0xe670045d, 0x4aeb0584, 0x9d68bda1, 0xe859ac69, 0xc9e3c43c, ++ 0x5e9e0b0d, 0x23b8e12f, 0xdc60cbb2, 0x0b3fa162, 0x5e8ef487, 0xc9be7c06, ++ 0x682b8c6a, 0x5e4295e5, 0x2730c016, 0x142dfce1, 0x16ed8af1, 0x373fa4d6, ++ 0x16fc0867, 0x32d2f195, 0x6cf1c791, 0x0fa352c3, 0x876bfac2, 0x738fb8f1, ++ 0x3ee29d95, 0xdf1fcf4e, 0x9dda0eba, 0x343e4cdb, 0xa2d76569, 0x3dfa0b56, ++ 0x942eb337, 0x7f12edc7, 0xedc0523e, 0x8a583064, 0x1efce966, 0x4aaa37b0, ++ 0x7752f174, 0x38c24453, 0x45b0ed46, 0x9d97c612, 0x8c25bb9e, 0x829b387f, ++ 0xfd1d3052, 0xb7b510a4, 0x16a70597, 0x9bb97f03, 0xfd9d79e1, 0x2e648e0c, ++ 0xdbcc2bee, 0x1ae745d4, 0xf7cfd2ab, 0x874e32fd, 0x1eb032d5, 0xacabefda, ++ 0xbd225784, 0x9baf0f66, 0xfb6be38d, 0x2ceed898, 0xf9d9f4e1, 0x72814c20, ++ 0x0fc78e30, 0x47953d8e, 0x4d8cf2f6, 0x23f47ea9, 0xd11c6d8f, 0xe343f040, ++ 0x1eff68fd, 0x64fc6a7b, 0x343c672c, 0x931dfa95, 0x0b8c41d8, 0x16e878cc, ++ 0x8b0beb19, 0xef1c2f01, 0x71f89584, 0x8b7743c6, 0xc06fefe7, 0xe4536af6, ++ 0x5d3fa27f, 0x1a6cf6dd, 0xa7c60bc6, 0xe58f90bf, 0xf2ef5331, 0xa67f986e, ++ 0x8f09fec2, 0x9cbac0eb, 0x7fc2371f, 0xb22c6d66, 0x65663c60, 0x98afbf31, ++ 0x0724fccd, 0xdbfc83d0, 0xfb3d5d9a, 0xd763a2c0, 0xf1ebc576, 0x5bbfccfa, ++ 0x5d658fd9, 0x346687cc, 0xd818386b, 0x9ee4e58f, 0x379a0350, 0xec77ef8d, ++ 0x4554f2c7, 0xe7d22570, 0xf8de1f99, 0x0f0033c2, 0x0572c1fb, 0x0792d0ed, ++ 0xa0eca77b, 0xa185a5b8, 0x1d5a3c3c, 0x032330ea, 0x50523bdb, 0x6edee43f, ++ 0x6ef9e132, 0x216476f3, 0xc4bdbb6c, 0x9da67184, 0x690b1d59, 0x0ca9a5dd, ++ 0xce1878e9, 0x478be421, 0x94148e95, 0xda4b9027, 0x3f82b587, 0x2521596d, ++ 0xbdc5eb0b, 0x54bf5f46, 0xafb8ff0e, 0x4496475f, 0x3848e4f3, 0x64119a0f, ++ 0x7cf38847, 0xda0bf033, 0xe0f4ce09, 0x3d6f8c76, 0x1ff2e7ea, 0xc0be7071, ++ 0xfce06bee, 0x4809df27, 0x4d08eee8, 0x3670fdc3, 0xbd5e91cb, 0x20c7009d, ++ 0x17be8b8e, 0x0ce1bfc5, 0x9361bb41, 0x33d061c4, 0x61fe1784, 0x70edc73c, ++ 0xd639476e, 0x8d0677f0, 0xae3ae1e3, 0xa73ff477, 0x620bddf1, 0x7315cf5d, ++ 0x20d1e8bb, 0xf7c34f1f, 0x5cfcc5e7, 0x9355bc07, 0x8e39ec93, 0xa4c3ac0f, ++ 0x8fd747c3, 0x3787d7d6, 0x2f91b9f3, 0x94248e40, 0xac92a423, 0xd902ff5f, ++ 0xf881929f, 0xe47df4bf, 0x23d40cef, 0xbb4fe780, 0x4e49d9c7, 0x66f1d613, ++ 0xc8fb88b1, 0xbf436760, 0xc941cda9, 0x904ff18f, 0x9ca7f467, 0x647a7602, ++ 0x8e9daf3a, 0xb74592f9, 0x0167a75e, 0x9b53d39d, 0xd816ad82, 0x69d5a9c7, ++ 0x69efe43e, 0xc2956bac, 0x097f7be5, 0xf59c37e0, 0xb69839fd, 0x73b8e81e, ++ 0x5af1dd41, 0x8b016ff8, 0xf9e056d5, 0xa63b83f9, 0xba6d1ca3, 0xc441ea7f, ++ 0x7b7cbf3f, 0xc0f8aa37, 0x6cefbe19, 0x956f8f2e, 0xd23f936c, 0x1cb3c3af, ++ 0xc99e9d60, 0x8184645b, 0xc6b00c1f, 0x61692e57, 0x4d1dc616, 0xcb539569, ++ 0x98666f50, 0x23cfae14, 0x24f49cd2, 0xaf91257a, 0xfdb5fd04, 0x09715df9, ++ 0x61d39bed, 0x71607da2, 0x7486fd9f, 0x9f6d72b1, 0xc4123ef0, 0xc9ef133c, ++ 0xc951cc1b, 0xfd05fb8b, 0xb38e0ed1, 0x89afb8a1, 0xa2ddb4fb, 0x3d432d4e, ++ 0xa0a4d1bd, 0x5748921f, 0x915fb760, 0x8731b29f, 0xb65ea1da, 0xc613dc53, ++ 0x4e6dd6d1, 0xe3f71b06, 0x631ffd52, 0xbccab33d, 0x3df3eb03, 0x0056a673, ++ 0x4621f97e, 0x3ed89ffb, 0xbee301fc, 0x063c1f92, 0x8d163cfd, 0x9cfd837d, ++ 0x40d9d9ea, 0xbec250fe, 0x38577c6a, 0xf0b9f924, 0xcb970964, 0xf1df34c2, ++ 0x642bb246, 0x050213b2, 0x9fbd50f2, 0xcfc25654, 0xe0ff89a1, 0x7d8873a0, ++ 0xc2968f68, 0xcf58bea3, 0x759d708f, 0x8db84ce7, 0x7ba38dec, 0xe50a9e1f, ++ 0x677a7fa4, 0x37e811e9, 0xab8e4fe9, 0xeb0f7eb0, 0xa081829d, 0xf90b41c8, ++ 0x3d9fad8d, 0xa20181dd, 0xc3e666b6, 0x679b5773, 0x65e79892, 0xfa40344b, ++ 0x3b6642b5, 0x0bb20f48, 0xc2fb695f, 0xda6605e3, 0x02c6de27, 0x47e41dcd, ++ 0x412a4aba, 0xb3786357, 0x17a43beb, 0xc6195b4f, 0x526faf5f, 0xfeb0b52d, ++ 0xcb559beb, 0x9967943c, 0x311da235, 0xf547c9bb, 0xbc7d9bb3, 0xe7ebcede, ++ 0x7ea9f934, 0xd79fb34e, 0xe81ea03b, 0xb4534371, 0xdee30c27, 0x4d56c8e0, ++ 0x1cd01f78, 0x6de7ede0, 0xfc147ed4, 0x630b1281, 0xd25129a9, 0x4ca71df7, ++ 0x5168defc, 0x2db5f12a, 0x8aa0eabd, 0xf2679bf4, 0x2b651da1, 0x70029990, ++ 0x6a205367, 0xac2df686, 0xb7d71723, 0x4154b827, 0x91e3dbf9, 0x1edf5c15, ++ 0x48fd6f70, 0xb47285bf, 0x1c982bd4, 0x3c0b3de0, 0x5db3af74, 0xb723efc4, ++ 0x0cde29db, 0x9bc50eb6, 0xc279edd9, 0xf4e7e18e, 0x5139f9d6, 0x3619e3d4, ++ 0xa472e1df, 0xbf7c53ef, 0x429dda7f, 0x167739e3, 0xe8bc5345, 0x95f8ea57, ++ 0xafcdfca1, 0xccd676c5, 0x7a7f9c14, 0xda2a6073, 0x98db6d91, 0xc830d50f, ++ 0xfb0f3d37, 0x0ceceb49, 0x82186f1e, 0x67cf8770, 0xd06002e6, 0x07c16d0b, ++ 0x9eb8a90f, 0x8e052645, 0x9e2fe84d, 0xd3b7545f, 0xe797edec, 0x350e4211, ++ 0xdf5031fd, 0x38e20ef8, 0x7ceb9bee, 0x011c1f18, 0xf3c60c3e, 0x447d5ab7, ++ 0xb22dc8e7, 0x446df90f, 0x19298e50, 0x11edf2fd, 0x39408ee3, 0x197771c4, ++ 0x4ef86de5, 0x136d1ca3, 0xc595ba72, 0x6e3821e4, 0x4b71a327, 0xc0fd8d3a, ++ 0x3cf09463, 0x48d7944a, 0xc05c5f59, 0x74018740, 0x9d7c945e, 0x3aeaebfd, ++ 0x32eb4654, 0x5ea175f1, 0xc732fa83, 0x1f50870b, 0xa4c93596, 0xc7584a6f, ++ 0xc97f5c71, 0x5a0c194e, 0x5560afd8, 0x7d373e2a, 0xdad48983, 0xe90f59b7, ++ 0x5bad4b85, 0xae24778b, 0x657d7133, 0x47ae6625, 0xb5707b34, 0x4dc1ec9d, ++ 0x3231812b, 0xc54adec9, 0x597b42b8, 0x4097dfdd, 0x3d84e7bf, 0xcccaf96a, ++ 0x839b49f5, 0x7ae2d4f8, 0x7f1f5ca0, 0xba88c9f8, 0xdfa84ae7, 0x791beb90, ++ 0xcfee82dc, 0x7bd8f512, 0xeb8d8f42, 0xb2f21935, 0x6a9539ae, 0x109acbc8, ++ 0x13c036cf, 0xfa19e7cf, 0xe9f082d7, 0x57edebdb, 0x2927da18, 0xebe01957, ++ 0xfa18d7dc, 0x0deb514f, 0x69f2b4f0, 0xb3627909, 0xeaccf00d, 0xcffa18ef, ++ 0x6866dff2, 0x8f78dd9f, 0xc086fda1, 0x537c0332, 0xf430ffd3, 0x66d839bf, ++ 0xc2ceff68, 0x13da191f, 0x3cad27fd, 0x3ce3c251, 0xb7a1dd9b, 0xec2d8028, ++ 0x7de724a9, 0x19efbf5c, 0x4a9edc69, 0xca5457ec, 0x8909f7f7, 0x6e22c7cf, ++ 0xf98e3c43, 0x5d7886dd, 0x7b78fc6c, 0x5aa38c2f, 0x3ca1ef7d, 0xbf0ea263, ++ 0xee1b76bf, 0x841fbad9, 0xd2de307e, 0x9e1722f4, 0x0dff1877, 0x16dee1c2, ++ 0x857dd135, 0x84b97dab, 0xcb0daef5, 0xbce55c79, 0x7d79e295, 0x1a46b078, ++ 0xaf710bef, 0x4db9e1a5, 0x60b691c4, 0x240f091c, 0xb7ea14ff, 0xfbf7852c, ++ 0x3b8b5389, 0xdcdc6906, 0xf2846b6a, 0x248416f1, 0x05b7038c, 0x26f78299, ++ 0xfce20f68, 0x32f9345f, 0xa2e245d9, 0xe66ec29b, 0xcbdcf987, 0x5856ad23, ++ 0xed53fa5b, 0xab8a3d0f, 0x0632310d, 0xff5a9f72, 0x0a63c610, 0xfc0090f0, ++ 0xe74e6572, 0xf3dbdfad, 0xdf30d3c9, 0x2aceb9a6, 0xed89abd4, 0x395e4bf9, ++ 0xed22e073, 0xf4bf175b, 0x7b171dc1, 0x4fbb7bfe, 0x0fb5d1ac, 0xca6d271a, ++ 0x1f1d7e63, 0xde92cd00, 0xe52c8c0f, 0xf192f9e7, 0x9d638a56, 0x94470737, ++ 0x3e7d9f02, 0x77638ffe, 0x53bf73c1, 0x7a8addcf, 0x9647ea10, 0xd7447ef2, ++ 0xa59c95df, 0x2bc292bc, 0x7187bec0, 0xf39252db, 0x5f18b36d, 0x31c73576, ++ 0xdd34b40e, 0x9f9fa2aa, 0x7d56f76f, 0xbb631574, 0x4eafdc2d, 0xf6b7dff4, ++ 0xe45ddbf9, 0x38c4077f, 0x2b34a20d, 0x8f6679fc, 0xec29d930, 0x30f424b3, ++ 0xa84a7467, 0xc816f2af, 0xa2e5eb1f, 0x714add3b, 0xc443a704, 0x0d0b1c1d, ++ 0x6e2d0171, 0x877e9dd0, 0x8cef7c84, 0x7cf145dd, 0x3dd0178c, 0xc497d8bf, ++ 0xbdbe4178, 0x7c1af084, 0x9f57d67c, 0x27992526, 0x3e2d0f01, 0x144f3891, ++ 0x9f3c09ed, 0x3d92a717, 0x87eeb891, 0xe1e76b4a, 0xf8d6a97e, 0xfea1d75b, ++ 0xf3a16e3e, 0x497e3068, 0x54595351, 0xd292fe37, 0x6937d222, 0xfa86d9e5, ++ 0x8b1e5f74, 0x8f77ce1a, 0x8cb27942, 0xacc3cddb, 0xe386ebbd, 0x7cf9877c, ++ 0x373e2cc7, 0xec7083d9, 0x6f7bb9e1, 0x66073f29, 0x1430e1a0, 0xe5fb8ce5, ++ 0x58d7209d, 0x642b096e, 0xf9036d9f, 0xb0f1f843, 0x5c34654a, 0xb08ee54e, ++ 0x8677da8f, 0x3a7e09ab, 0x577827ec, 0x67ca91b8, 0xffaa01c3, 0xe089b859, ++ 0x2a41c2e7, 0xa90bc2bb, 0x887085fe, 0x2bc317e0, 0xed097e08, 0x538c52c1, ++ 0x27b953b7, 0xafed41dc, 0x7e093b84, 0x32a51c2d, 0xf545de16, 0x045dc37b, ++ 0x26ef0fef, 0x463840f8, 0x41f0c1f0, 0x7b870f2a, 0xf868fea8, 0xe2e7827d, ++ 0x8fdef13a, 0x7384f7b5, 0x5596bfd0, 0x0d1eefb4, 0xbed0502e, 0x2933cf76, ++ 0xbec1cea8, 0x1ce30bba, 0x3df99adb, 0x6247de26, 0x6edd881c, 0x3dd27b22, ++ 0x934391ef, 0xb50e7da8, 0x7321c66f, 0xb85a3f81, 0x5b16cafd, 0x130b9fa9, ++ 0x6db9e0a2, 0x5ec99a8b, 0xa54b28ed, 0x4c8b5776, 0x5356df76, 0xb2fc8b28, ++ 0xdfd2655b, 0x1fb70b2e, 0x56783e34, 0x4b67dbe8, 0x32ef9e65, 0x4653ef9c, ++ 0x6473f271, 0x3766a96f, 0xf5c41fb5, 0xfac2e7b9, 0xcbb9df10, 0xeb2f78ed, ++ 0xf744ddba, 0xe02e8fb0, 0x799eb2f7, 0x7c055fdc, 0xe6cc2e28, 0xb8a7e4c9, ++ 0xbc22aee6, 0xa7aef33c, 0x03f86576, 0x77a7e859, 0x22cf9686, 0x8a659b7c, ++ 0xf706766b, 0xdb3de166, 0xe4ef9156, 0x881a9a1a, 0x67c40e56, 0xa7bf296f, ++ 0xc6dff0d3, 0x01e0dfb8, 0x24f9e97b, 0x5b34c0eb, 0x8898673a, 0x4f603de3, ++ 0x40fbc71a, 0xb891ef8c, 0x657bb1fc, 0x59c7bf92, 0x7ef9052c, 0xf94cb34b, ++ 0xcf75f923, 0x2abc60b6, 0x2bf82cb7, 0xd4c7c394, 0x80657b31, 0xf8f91bb3, ++ 0xa7e5cb45, 0xf7ed12cd, 0x7ea06b27, 0x021bdddd, 0x0d90ea88, 0x5b8a2b6a, ++ 0x7297bce7, 0x91e5fe31, 0x95a3fb8c, 0xf4fb15bf, 0xb78f9fb8, 0xf14cb965, ++ 0x8bcb5764, 0xde7cfdde, 0xbcde710f, 0xc149bfe1, 0x39e29534, 0x865509aa, ++ 0x067cae67, 0x67b94be7, 0x66912343, 0x6f9b5f83, 0xb977ce34, 0x83f61a74, ++ 0x09305706, 0x93e9835e, 0xf391e94b, 0x9839e9a5, 0x59f2c317, 0xad91ea3e, ++ 0x22b7ae16, 0x927b716f, 0x0dc68292, 0x17cb479c, 0x1207f2d0, 0xc26c05f3, ++ 0xb1b7cfae, 0x4ab9f7a4, 0xa11fdd9f, 0xfaff71f2, 0x78d9e500, 0x61d24c65, ++ 0x2eec2d4b, 0xb5a5e7dc, 0x126b4aa9, 0xb7d3e87e, 0xc080c7a8, 0xf62632a6, ++ 0x1f234365, 0x99c7c4c7, 0xae085ac0, 0x24912875, 0x1f2b5afa, 0xcb58e311, ++ 0xdfe6df38, 0x0775b3fd, 0x5b0f7f70, 0x8b6a3728, 0xfc8eba29, 0xd266638b, ++ 0xaee679af, 0xf0eb4fed, 0xece22e1a, 0x0ad1ac5b, 0x84ee87bc, 0xaf512af1, ++ 0x6254bca2, 0x18f8101e, 0xcf6bba3a, 0xbedc65a9, 0xdac2ec7c, 0x9e7fba2c, ++ 0xed052abb, 0x27664ea3, 0x4259707e, 0xfc75a359, 0x4cbe42e0, 0xca531fc2, ++ 0x31df42ac, 0xbc58ed47, 0x72e7e197, 0xc025ea3d, 0x1905d5fb, 0xcfd61e74, ++ 0x28da677b, 0xc9ce6b80, 0x65b2cf94, 0x1cd3cf11, 0xca26aff7, 0x07ed7913, ++ 0xf6bbefdc, 0xebf206be, 0xa8f94572, 0xda6af3f0, 0xfb062f99, 0x41c0b352, ++ 0xf384d4fe, 0x9fbd49f2, 0x31e92144, 0x78f05fe8, 0x687135cd, 0xb8dff1d7, ++ 0x40fec653, 0x19da3351, 0x7ac6bdb9, 0x4f17dcf7, 0x3a79824c, 0x3b87f117, ++ 0x0877bc2f, 0x1372c8e1, 0xfb8049c5, 0xb9237ac4, 0x2394e714, 0xb9bf98b9, ++ 0x9f48cece, 0x15d9e6bb, 0xcedd07d4, 0x9d7fd254, 0x0ec83b37, 0x34b25b5d, ++ 0xdb64ed05, 0x5859e5dc, 0xb646b30e, 0x5834ec63, 0x7bb66a36, 0x2d5be91c, ++ 0xaac2255f, 0xcdb81ec1, 0xdf1c8c2a, 0xd46493c3, 0x659f3c97, 0x87a8d97e, ++ 0xdf582523, 0x26a87841, 0xdf17c796, 0xe3c2df07, 0x50bcfc86, 0xf00ed0ad, ++ 0x778223ed, 0xe77ec196, 0xb1ba44e6, 0x64e3b369, 0x316bc533, 0xb7e608c9, ++ 0x2b31082c, 0xd95737d6, 0xc9ae72f5, 0xff95d7c9, 0xdf3dc4ab, 0xa5c0f4a5, ++ 0xbc94bdc6, 0x72e628cf, 0x6d3f9833, 0x6a9f441b, 0x2593f1fe, 0x6c517e5c, ++ 0x693d5ce9, 0xf55f6a4d, 0x6d51bd0a, 0x332a79e5, 0xd237269a, 0x57a44c3d, ++ 0x83be7cc6, 0x9d3a9e42, 0xdc4f74e9, 0x7862c459, 0x6f99106f, 0x1c9ef1e2, ++ 0xb9b3affe, 0x9b43e288, 0xa45650a4, 0x41ebe318, 0x275fee2f, 0xe61d28d0, ++ 0xf5c854df, 0x14868b3a, 0x7186afbc, 0x4ff1ea16, 0x7b25df12, 0xcc1af298, ++ 0x55aa7b24, 0x7970cf17, 0x8bf1a4e4, 0x3c237109, 0xae11bcf1, 0x5c031665, ++ 0x93c2376f, 0x0bfc2314, 0xdcebfeb1, 0xaa29fac6, 0xec14f611, 0xfcf1314f, ++ 0x2eb884fe, 0x4be3077b, 0x6b4d6205, 0x81d8ccaf, 0xde828a71, 0x5b2e3c45, ++ 0x63207a08, 0x9f239c60, 0x5fa42545, 0xb735fc62, 0xf2e295bc, 0xf18905ee, ++ 0x83c510a0, 0xb8b2e312, 0xcf0728bd, 0xcff3c95c, 0xff04554f, 0x74a5e509, ++ 0x99e3c714, 0x7ee94b6d, 0x90e6758a, 0xbe45795c, 0xf2f3c0d2, 0x3683a221, ++ 0x4445ca1e, 0x07947eb7, 0x11c3fc3d, 0x765dffc1, 0x888b9735, 0xecacfcfe, ++ 0x685ca0b5, 0x1f260df3, 0x8b567c9a, 0xef2d147b, 0x4b189ce6, 0x2e59bbcb, ++ 0x277705f2, 0xf39cebe4, 0xffa26434, 0x5967ae7c, 0x4439326a, 0xb8d88bb9, ++ 0x4eb9621c, 0x1ca0dfe4, 0x39738646, 0x9fdb7ac4, 0xecc9025a, 0xfb8b1fc5, ++ 0xdd767bd2, 0xdd23eeb5, 0xb57716fa, 0xbb25e018, 0xe7d3ae57, 0xff83dd47, ++ 0x76b3e4c1, 0x8bb5f946, 0x3b3e72c4, 0xdba7ebf1, 0xbf022ca0, 0xbb8c387f, ++ 0xe524f4b8, 0xb716338b, 0x58febee2, 0xf519a39c, 0x9cd7edc9, 0x2ffce2e1, ++ 0x31c436cf, 0xd2c478b4, 0x1b2baa8d, 0xd54ccb9e, 0x767c74f2, 0xf115c7ca, ++ 0xc1f6c18d, 0xa98d3e76, 0x6c01f7ba, 0xfe918872, 0xf5419f39, 0x9c5f7197, ++ 0xe0e87c3b, 0xe1aaa0f1, 0xdd6b8e9c, 0x078c1ea1, 0x33df0459, 0x2c67d03b, ++ 0x33ff01ca, 0x54bcf2a7, 0x1718c78b, 0x133e60b2, 0xbe9adff4, 0x2da9e490, ++ 0xbaa5e785, 0xa12f991f, 0x319d589e, 0x512be499, 0xc7e5128e, 0x13c5f225, ++ 0x33e607e5, 0xf2574bc0, 0xf24da5f3, 0x252f5105, 0x17ffe7ae, 0x3e94d03f, ++ 0xc9ec87a6, 0x76d55482, 0x53703b11, 0x9f1a3238, 0x5a1a9b5b, 0xf7bf7788, ++ 0x90dcf33c, 0xac0760d5, 0xc83918c5, 0xf667caec, 0xcffcc6cd, 0x574f824d, ++ 0x9f8898e7, 0xb738b79c, 0xe4fc759b, 0x68bd06b4, 0x224d3a07, 0x30ff09ef, ++ 0xb9dab47e, 0xf9927d63, 0xcfa67b35, 0x3c026bce, 0x49b8fb74, 0xf37d91d8, ++ 0xbb6f277d, 0xd38e3759, 0xf34d1c16, 0x89fde5f5, 0xb37cd6f9, 0x388b36f9, ++ 0xeb9f3690, 0x5cfae356, 0xcfad10d6, 0x36aff425, 0x5f5c66df, 0xe4bab912, ++ 0xecafc27c, 0xc6bbef9b, 0x216cb9f5, 0xcccb9f5a, 0xf37d69e3, 0xf366f9ad, ++ 0xae7c8459, 0x5939ef16, 0x28a30b52, 0x17bd838f, 0x5f97d6d0, 0x0f50501d, ++ 0x64e2d6ad, 0x4d9fcf42, 0x854bf3d0, 0x3f9ed79e, 0x7142539b, 0x6707b3cf, ++ 0x3bf4c92b, 0xec2675ea, 0x2bec262b, 0x842bec26, 0x589fd467, 0xf1f8143e, ++ 0x307ccfe7, 0x6cf3865b, 0xc6273dc6, 0xe47c0214, 0x10e6ab99, 0x1789ccfc, ++ 0xd191e1f3, 0x5b377ebb, 0xe33d7d06, 0x3ce713e1, 0xb888eed0, 0x5da034e7, ++ 0x61eb843b, 0xde6d6f0d, 0x4bc3d098, 0xb8f31456, 0xd44be81e, 0x21856ddf, ++ 0xcfb77186, 0x798cf13d, 0x41497fd0, 0x093f39dc, 0xc972b45d, 0x3cfe328a, ++ 0x31633f5a, 0xf3eb8b8f, 0x37f7b5eb, 0x6fef8d1a, 0x27ac6464, 0x458528bb, ++ 0x6963d415, 0x6fbd3f76, 0xd2ae5f58, 0x7cc0ddbe, 0x569edc4d, 0x031e794b, ++ 0x7663df7f, 0xa95718b5, 0xdfb605f9, 0x46aff260, 0xe357ef3f, 0xb3450ee6, ++ 0xbb17cb51, 0xcafdffa2, 0x3de75f9d, 0x4a1f19dc, 0xe4cc46dc, 0x23198871, ++ 0x78fa3e38, 0x8383da1a, 0x0377f3d1, 0xf4e7e9e8, 0x7a73f6cc, 0x568cf12a, ++ 0x5925ffd8, 0x2483e771, 0xf4a4b1a7, 0x04d7401a, 0x9c397dfa, 0x198ffe69, ++ 0xd14bcfcf, 0x96aba35b, 0xa926d757, 0xb2a764a5, 0x2c5e435c, 0xb26a39f8, ++ 0x61b58dfb, 0x77d00f7e, 0x0c827aae, 0xdbab30ed, 0xdf798e57, 0x27367f6d, ++ 0x28ab57cd, 0x6b717ee7, 0x3be52a46, 0xc95865b6, 0x98ceed0f, 0x2aee30ca, ++ 0x5d13263b, 0x291a321a, 0x843cd10f, 0x969fa175, 0xce6d7f98, 0x63f29bbc, ++ 0x5968f9cc, 0xbf97d943, 0x5ca3b7eb, 0x65f43f99, 0x2e01917a, 0xbe5aff33, ++ 0xf675fe54, 0x9d7f9e54, 0xe4315561, 0x9add3ab3, 0xcffaff34, 0xc6e81ec2, ++ 0x7ae0e5f5, 0xfede7d60, 0xbf0ac975, 0x34fac66f, 0x42567fbc, 0x62cee28c, ++ 0xce1e7ffd, 0x8feb45f7, 0x07ea2b5e, 0xa2a7d5b3, 0xe6ce62dd, 0x63dd87e7, ++ 0xfd3ae562, 0x87ffcda5, 0x7e7a16e1, 0xc78508d9, 0x5edcecdd, 0xe4cbf19d, ++ 0xcbe3f479, 0x724bb8b5, 0x6f8c1bbe, 0x7cf137ae, 0xe72e4d33, 0x0794ac38, ++ 0xaee1c737, 0x1cc178c3, 0xd953c460, 0xded7feba, 0x961fdfc4, 0xa7e46e7d, ++ 0xf899afb7, 0x8619b78b, 0x3edeb9c3, 0xef42c53e, 0x98971dd3, 0x303d97df, ++ 0xc81033cf, 0xce68849a, 0x15627e9c, 0x28e9638a, 0x33d27646, 0x6a3afbce, ++ 0x020bf254, 0x4e61d0e5, 0xf424d670, 0x1a6fae5d, 0x5ff606fd, 0xb9f5c692, ++ 0x24b2af76, 0x067af40d, 0x88dca3dd, 0xff1f3ffd, 0xf21d4669, 0x442f1c97, ++ 0xe9fd74bc, 0xbfd7457e, 0xc19ff459, 0xd38b375f, 0xe6ce27f7, 0x209bf47c, ++ 0x2771fda3, 0xcfd0a7b3, 0xd27dba60, 0x1bfa07f4, 0x33f47afa, 0x96cece98, ++ 0xdeaed59c, 0x2b44fa24, 0xcbb7ee9d, 0x701e8016, 0xa545bee6, 0x6fc9bf56, ++ 0xd9268c6e, 0x7d8a1fe7, 0x7ef6c6fe, 0xb63b6027, 0x3b07dedf, 0x8f4887ff, ++ 0x3b8e9acf, 0xbe92c0c7, 0xec8670d7, 0x93558b7d, 0x97fc9543, 0xcf78d87e, ++ 0x51dc39b7, 0x33d5ef86, 0x6b8c03a4, 0x5b46fa11, 0x406365af, 0xfc1f7b41, ++ 0x9dc23f67, 0x435978e1, 0xfff3ff69, 0x1611e84b, 0x6de7a329, 0x9edd6f82, ++ 0x31d2bae0, 0xf2251794, 0x3e831489, 0x3590d59b, 0xa0ed0729, 0xa1cf995b, ++ 0x5a3ad2e2, 0xa136ae51, 0x6e3b42be, 0x3b924aef, 0x45242797, 0xc479ba1c, ++ 0xc5cbd27b, 0x9cb9e87d, 0xa6cf5a06, 0xc4247f3e, 0x04f35fc8, 0x9d6f507a, ++ 0x0f42c47b, 0xb633aa6d, 0x60813dbb, 0xc777e02b, 0xcddf3c8b, 0x3ff60cd5, ++ 0x971e17c6, 0x780d9628, 0xa4405e50, 0xe623fb90, 0xc08b074e, 0xc1cab6fe, ++ 0xfb7a23bf, 0x5a4cfbd5, 0x5bf430e2, 0xf64acc3c, 0x38296adc, 0x66b7bf85, ++ 0x24e2c962, 0x38f3962f, 0x15ca2fc0, 0xfdd38f5a, 0xf71fe72e, 0x860b653b, ++ 0x1ffcbe5c, 0x1ffc7111, 0xdef4aa65, 0x6d1f668f, 0x2a3fc418, 0xfa0930a9, ++ 0xd0457389, 0x7682cecf, 0x14b31794, 0x5dc241e0, 0xacfb3ecf, 0xf9444893, ++ 0xfd84eb88, 0x5a938da3, 0x54c6a512, 0xa5f49f9f, 0x79f9f8a4, 0x11dc84a1, ++ 0x7fb5c390, 0xff9d2732, 0x14de76ac, 0xfec6e7dc, 0x1cb06a0d, 0x3ff7c4cb, ++ 0x51de14d6, 0x66b9fb8e, 0x5cbfd1aa, 0x8f7d5273, 0xf30e63f2, 0x82eef67b, ++ 0x60099732, 0x6c8b41c7, 0xda1c48bb, 0x7a89e70a, 0x2ac33b11, 0xecd7b4f2, ++ 0x6b95f9e5, 0x783d551c, 0x91c6bf9f, 0xebdb4553, 0x5a9af9e0, 0x00e3877f, ++ 0xc7c3a5f1, 0x781d2def, 0x2688487e, 0xf112a3d0, 0xd0f4403a, 0xbd451dfa, ++ 0xc7fb143b, 0x958fbe18, 0x7ea0ebe2, 0xc7e03976, 0x0e7b5cfc, 0xbb11fba3, ++ 0xb52be5c2, 0x49ecc4c4, 0x946fd1e2, 0x4d64f3f3, 0x1d4f5565, 0x17e327e1, ++ 0x771ad809, 0x79ce9b95, 0xdf3c3ba4, 0x73946b96, 0xb064854b, 0x1e44dbb7, ++ 0xb22bade9, 0x61570d22, 0xeff0257c, 0x63ae38e5, 0xcce51dbe, 0xa2e63e9c, ++ 0x3a0e65e3, 0x312af75e, 0x6ae2a59e, 0xc14aa71c, 0x6f422cf1, 0x40bdd224, ++ 0xbd9ff38c, 0xd2ca06b7, 0xd304c3fb, 0xc9dcc586, 0xdbea43de, 0x9d1f713f, ++ 0xd637dcf8, 0xf18cabc7, 0x3ec7d017, 0xcae2ff5c, 0xa8ea0793, 0x1e5dc786, ++ 0xe68cfe17, 0xd8c53897, 0xbde86ea0, 0xea9488f6, 0x0840efa3, 0x6299c53f, ++ 0x7bff43a4, 0xbe1f7ca4, 0x67f9e268, 0xba30e45f, 0xeb94481f, 0x987e8e2f, ++ 0xd067f7a5, 0xb8dbf18f, 0xef17e31f, 0x7c45fa91, 0x378c610a, 0xf216f290, ++ 0x6d1f17df, 0x035a7f52, 0x8f40d9f8, 0xc95c609b, 0xb6fe2213, 0x28bd7a79, ++ 0xbbe285ef, 0x7e748907, 0x74afec58, 0xc62f29ff, 0xe2721bf3, 0xfde4c9b9, ++ 0x73e79589, 0x4c4f3d71, 0xa157cbe9, 0x4e27967b, 0xfcf19ba8, 0xbe321c88, ++ 0xbf8da5f7, 0xb3efd0f4, 0x2f79ba82, 0xc6555ef5, 0xc8cbf5c9, 0xedcf9c6e, ++ 0x7bf6bfc6, 0xe3cf8f56, 0xc96eea76, 0x2c7f9fa8, 0xa0bb72f4, 0x4cbceb97, ++ 0x2f68cddf, 0x18acae0b, 0x650cf18a, 0xc2e5ea3e, 0x6d1f3c95, 0x9f960fe9, ++ 0x7c8933ba, 0x304464fc, 0xb835fd8c, 0x7a4addba, 0x9451cdaf, 0x83fbb179, ++ 0x443df7c1, 0xefdb4a7a, 0x3cedfbda, 0xedc8234f, 0x0ef06768, 0xcc48ffca, ++ 0xdfac18cb, 0x07ae0ad4, 0x26b6feb5, 0x39b76f6e, 0xc2b8a7ae, 0x2431f459, ++ 0xc9fc3fb2, 0x5c068fce, 0x1d8fa09c, 0xbd8cc9ce, 0xb8e0a577, 0x3dcfe116, ++ 0x9a45c5ae, 0xdd7eecaa, 0xab9b96f3, 0x3e3a75ec, 0x2f3c6369, 0xf7fc7136, ++ 0x22fb342a, 0x2120edc6, 0x7f3c16cf, 0x2394c631, 0x3bd3ee9f, 0xbcf27864, ++ 0x72fd65ac, 0x830ee3cc, 0x70a561e7, 0x7b22adb9, 0x63e6136c, 0xdadc1d81, ++ 0xd2187f34, 0x7c1c9377, 0x887405c2, 0xfca3607f, 0x72167fe1, 0x74e42bda, ++ 0xb08bfdb0, 0xfe9494bd, 0x2f8fdb20, 0x8c9f0183, 0x68b944c9, 0x4635312b, ++ 0x1df3ac93, 0xd88bceb1, 0xbe2b07e3, 0xac7e3d9e, 0x8e3d8922, 0x213fb6f6, ++ 0xd187afae, 0xb127f6ce, 0x22498fc7, 0x63f220be, 0xddd4598e, 0x639740bd, ++ 0xbbe93213, 0xfc69a560, 0xfa18e1be, 0x87e05527, 0x04a2733c, 0x521997ed, ++ 0x848077df, 0x0608c43f, 0xea24e47f, 0xf42c59e3, 0xc9129dec, 0xc0a7bf11, ++ 0xa5e7685b, 0x0ad9f9f7, 0x0ebb7c46, 0xfae30ff6, 0x9bcc2e9b, 0x9e6e2c92, ++ 0x5f2fa237, 0xef75d996, 0x1ddc32d1, 0x80ce3ddd, 0xfb84a9fb, 0xc0aebc28, ++ 0xbeed5b7c, 0xccffb12a, 0xd17de36a, 0x2e3c0bba, 0x458bbb62, 0x1f30941f, ++ 0xbb3ed8d3, 0x1f7892d1, 0xba47b866, 0xc4496021, 0x37cfa227, 0x3776d82e, ++ 0x2a4f3bdd, 0xb63479e0, 0x04e28cc5, 0xb64cf789, 0x337e3dd1, 0x3134c55e, ++ 0x8c0eaa9f, 0x267e6393, 0x189b0fc5, 0x5ff982db, 0xbc798c0b, 0x7fa647ae, ++ 0xd20bbfc2, 0xb8f388d1, 0x7b420ec1, 0xf63415da, 0x3073eed3, 0xbeff452d, ++ 0x24bdf6b2, 0xc226cde7, 0x5226458f, 0x87f716bb, 0x675a8efe, 0x2d9dbaff, ++ 0xbd3fafac, 0xbe4914b7, 0xa69bcdee, 0xc61df7f3, 0xa0c74684, 0x88c7df29, ++ 0x580bf90e, 0x1d12f554, 0xb6e8f70c, 0xceb49d82, 0x1b190bb3, 0x0c1d1122, ++ 0xd270b9ed, 0x02c0fdd3, 0xac3abde3, 0xfa2700d3, 0x53f297ab, 0x1725056d, ++ 0x8a97f3d5, 0x7dc4da63, 0xc42375dc, 0xb2471e77, 0x39176891, 0xf6847e6f, ++ 0x07ec2ce3, 0x927bb9e5, 0x806db7df, 0x6cbbf1f1, 0x6979099f, 0xdaba7713, ++ 0x5f986cf7, 0xa4b7f7a6, 0x34b38e6a, 0x63efc024, 0xb9c9192b, 0x31d9952d, ++ 0x6f1a5c2f, 0x6ddd23f3, 0xc9618036, 0x73d99592, 0xe22cdea1, 0x9312add9, ++ 0xcf8a6611, 0xda8fe3ce, 0xf4a274f7, 0xe6c19d3d, 0xc823bed1, 0x6d39fc22, ++ 0x8fdf019e, 0xf8f3c8bb, 0x6f36919e, 0x140df3ff, 0x1fe6d4cf, 0x7d83fe8c, ++ 0xd4ffee2f, 0x8f3573bf, 0x5f887aa7, 0x95f9fb9b, 0x1f8279e0, 0x0bd479f1, ++ 0xeecd69b7, 0x3fe8919e, 0xcd37bc9c, 0xadd25eb7, 0xcccd3223, 0xf5f783bf, ++ 0xc3c3ebc6, 0xf7f216ad, 0xc4bac4d2, 0x5d775f78, 0x6bd3a7f4, 0x0da5f16b, ++ 0x6668f7cc, 0x0cef7f74, 0xd3227dd6, 0xc1ac3bbd, 0xdf7427a0, 0xd6f18007, ++ 0x1fefc83e, 0x2df7e336, 0x6f67fef0, 0x6ae9de7f, 0xe907b607, 0x3e5a12fb, ++ 0xae8fe62a, 0x0f7fecaa, 0xc1bef137, 0x24e30cdd, 0xc04dd789, 0x137cc085, ++ 0x06922cec, 0x39d64be7, 0xc3dfaf8e, 0x1ea1d7a2, 0x0f04f012, 0xf1367fd7, ++ 0xf994357e, 0xfb3fa231, 0x98dbb60d, 0xbafdf28d, 0x8ff51b25, 0xb8fef015, ++ 0xa8724b41, 0x630bbe9d, 0x96fb3d63, 0x3849bf40, 0xdc7e8e6e, 0xe7b71898, ++ 0x13a4fc61, 0x0e1ef4c2, 0x7c4ddfbe, 0xe1cf55d8, 0x3317e8a8, 0x5d73d267, ++ 0xfea432fb, 0x8c42c67a, 0xae7fe3ef, 0x3c1efdb4, 0x5f07380a, 0x79494375, ++ 0xef4c2d09, 0x9d5ea067, 0xba6bcba2, 0x9d39dd96, 0x37e705cb, 0x384fd459, ++ 0xabe8356f, 0x8356e26b, 0xac2f933e, 0xafe78339, 0x3d4254ed, 0x7cb7eebb, ++ 0xebc520bc, 0x7db1b765, 0xf9e3c8a2, 0x7d6f4d67, 0xf88b7d8b, 0xd24e42f0, ++ 0xbe7eb8fc, 0x3fbe188d, 0xaaf58562, 0x44632c66, 0x9f78ab67, 0x34f48ade, ++ 0xdfffcff7, 0xf9bab4a5, 0x0ae6013d, 0x8e76fd20, 0xb8af5808, 0xa0feffba, ++ 0xec00e506, 0x2f78acc2, 0x58de6373, 0x1c91f335, 0xdee663c4, 0xcbcce724, ++ 0x68f95de9, 0xf67f7517, 0xbfb63e52, 0x7ca5e67c, 0xfe5f73b4, 0x8e3369ec, ++ 0x3f8a7b57, 0x0f250357, 0xfe242d2e, 0xfa5d29e0, 0xd3df1e7a, 0x713e13d7, ++ 0xdbe7a2f5, 0xb37cf14f, 0xcc0739e2, 0xbf049651, 0x23160e09, 0x0d2bb9ff, ++ 0xe41670ed, 0x3e08d7f3, 0xca6e397e, 0xbe75806a, 0x13e4ca7c, 0xfe7f36f9, ++ 0xc62f6b4a, 0x70d217f6, 0xef4f97fe, 0x78750735, 0xfbf8235e, 0x50f03c6c, ++ 0x3e673e06, 0x9093ed4a, 0x69f7884e, 0xe792bfc0, 0xda7e2243, 0xe783983a, ++ 0xd4fb666f, 0x0e7b8c5a, 0x7f8a3e61, 0xb15cf7e2, 0x7cf14fdf, 0xb8f5c32e, ++ 0x0d3f2609, 0x0f3c57e0, 0x6cde62d6, 0x1ba3bf9e, 0x77c877df, 0x79847f47, ++ 0x613adac0, 0xfb13f27c, 0x65b688f1, 0x35615e60, 0x51ac2bcf, 0x87456662, ++ 0x893e1f57, 0x5fbcab78, 0xc3579887, 0x4fc09b67, 0x91c60bc3, 0x337e386c, ++ 0x9c98a1f3, 0xb1bbc78d, 0x6b7bf8f4, 0x702cadd1, 0xfedf0907, 0x758bb27d, ++ 0x5c65fb69, 0xa3c4e667, 0x5ac788f9, 0xfd348ecf, 0x5f735b7e, 0x8cfac34c, ++ 0x8dfba338, 0x84d5b89a, 0xf1830ef7, 0x49dc4643, 0x0d4d73e7, 0x5451e168, ++ 0x01bf458e, 0x8f016aca, 0x960d7017, 0xd30f0b6b, 0xaa35197c, 0xa8cfc70f, ++ 0xf9f0f9f1, 0x80bf1a8c, 0x5e349543, 0xfde1495c, 0xe2bf0422, 0x7d70c0b9, ++ 0xc6d9a71d, 0x5faf550c, 0x077386a2, 0x63c4339e, 0x1c3be2ac, 0xa5141656, ++ 0x077ae65f, 0x52b04ea8, 0xfd224f39, 0xd5ef56d3, 0x511ea3eb, 0x2e328af6, ++ 0xc6d315f4, 0xd783227b, 0x3979da17, 0xefc7b792, 0xfbd95135, 0x57fc5c98, ++ 0x1e9a33d4, 0x18230771, 0x07149f8f, 0x7274023d, 0x7d41fe81, 0x0681e9a0, ++ 0xb0b28721, 0x0f48df43, 0x0c9f4878, 0xfd83c9bd, 0xd1bdc8de, 0x9ac1fa83, ++ 0x68ef7ff3, 0xeeb57e81, 0x89714ca0, 0xcd8d895e, 0x07ffb81e, 0x281df3dc, ++ 0xdb9407e7, 0x90af42ec, 0x7908373c, 0xb8f5035e, 0xf3dc6b1f, 0xd48e3e99, ++ 0x8bee3fb7, 0xcf4d1beb, 0xa622e8b0, 0x36a0eeff, 0xdfc15eef, 0x2fb31407, ++ 0xadeb0636, 0xf5dc3e5c, 0xe30c7cab, 0x873e5faa, 0xb8e258b6, 0x7dbc84a7, ++ 0x2d3fc62a, 0xd0cf63e4, 0xe02b9ec0, 0xa517fabc, 0x51a3a7f8, 0xa0bfb8df, ++ 0x875a8df7, 0x02dcd4de, 0x6af03d74, 0xbc97bd3a, 0x5cfe2324, 0xf1f0778b, ++ 0xa36f454e, 0x6ae36af5, 0x7f8fc0fd, 0xbf1d0af3, 0xcc9f71ae, 0x5ca73d20, ++ 0x559d7e5e, 0xa9613de4, 0xf053f3f0, 0x65f05473, 0xa2432887, 0x8d7be35e, ++ 0xdff2237f, 0xe49b39c2, 0xe904fc5c, 0xd38b9dae, 0xba464398, 0xc894aa4f, ++ 0xe9869bbe, 0xf3fedeb6, 0x0f38aa60, 0x5a5eb266, 0x8c59b7df, 0xb79523ca, ++ 0xb4c97e51, 0x2a65e7f2, 0x5fc4bd2b, 0x0c7c84d3, 0x6fb15fe0, 0xab2d9559, ++ 0x175fcf90, 0x585af7fb, 0x5572be25, 0x1a30dbce, 0x5b9a66b6, 0x729f7da2, ++ 0x1c617581, 0xe0f4cde7, 0x7fa82caa, 0xf7d98273, 0x88fbc320, 0xbcfc93ef, ++ 0xea4ef239, 0x448566ff, 0xe575dbe7, 0x02979b1b, 0xf92b53fe, 0x5834d3f3, ++ 0x0235f549, 0x6dabf13c, 0x708f921e, 0x9173e735, 0xf05fb27f, 0xe89a94cd, ++ 0xed3fec36, 0xd9e69dbc, 0x2bf7f42b, 0xf72a72e1, 0x4e547d84, 0x7ee9f8f3, ++ 0x9b0acde0, 0x9f417f38, 0x5c8e7ac2, 0xe51fb1d8, 0xfa3e56d8, 0xf3072fa8, ++ 0x7df4cd60, 0x19cac99b, 0x1ac0cc33, 0xda3f6c58, 0xa52ac7b5, 0xafd05955, ++ 0xa1b8dd51, 0x2ccdfa0a, 0xd098e615, 0xee428d1b, 0xd76fa90e, 0x473e0267, ++ 0xf3864976, 0xbbc851bb, 0x07dbe475, 0x511cb550, 0xbbf199f7, 0x4a76470d, ++ 0xb4f79ef4, 0x01a3b6ca, 0x54e7bfa8, 0x75f70324, 0xd910e9d1, 0x5b2b67b9, ++ 0xbe723ca8, 0xc33e8721, 0xae72e410, 0xdf9da7cd, 0x5da31533, 0x4ceaedfb, ++ 0xf7ea7d83, 0xfef00cb9, 0x7b46494a, 0xe1fab0fa, 0x2f8825d6, 0x0d61afc3, ++ 0xfa88f7c4, 0x13c23ec5, 0xf3c725f4, 0x73e23349, 0x59bb7b8d, 0x8d65ddff, ++ 0x1164588f, 0xc09a63d1, 0x93e570ef, 0xab0e87a4, 0xfdb03a4f, 0x65cff970, ++ 0x62bf5fe4, 0xf7d3e033, 0x5363d0bc, 0xf2a1db45, 0x30bddadb, 0xb34aa1ff, ++ 0xdeb7d38f, 0xeb063dd7, 0xeac7a4cd, 0xf4e38c72, 0xc4ead3e3, 0xf0950e79, ++ 0x17c6faf9, 0x9f8696f6, 0x73c35fd6, 0x1d15f9da, 0x57d7d6e8, 0x8550df6e, ++ 0x8996e57c, 0x1a8aef2f, 0x5767b9e7, 0x8bde81a6, 0xf8065cbb, 0xc1fd6550, ++ 0x7e8c822a, 0x6f25abca, 0xccf5e6cf, 0xf3a9c531, 0x52773c57, 0x6911e7be, ++ 0x97a9f93a, 0xd72a53f4, 0x3c53f726, 0xfc50a7e0, 0x929fb92a, 0xa1b46fe8, ++ 0x91f1852f, 0xf4f9463c, 0xc4cef9da, 0xf8ad8e77, 0x7fa9639d, 0xe56effbc, ++ 0xf6af4a9e, 0x11f162bd, 0x8dff5e4d, 0x4b96e1ef, 0x622f3eb2, 0x442deb31, ++ 0xc6845145, 0x3df3cc19, 0xe113af53, 0x537c59cf, 0x1af9d02a, 0x7e36ed99, ++ 0x5eff99cf, 0xd05b7005, 0xaa3efd06, 0x257dfe0c, 0x169d5fde, 0xf8f677df, ++ 0x3d4ffe79, 0xdfc4e3cf, 0xd9d16863, 0xecaf3f07, 0xf831dfcb, 0x57b4a62f, ++ 0xf1b9f1f2, 0xbe3cada7, 0x1ef12a7c, 0xc53f8b41, 0x38db8a24, 0x95d7bf92, ++ 0x339ade78, 0xcf2fb8f9, 0x2f49f7e2, 0x1fefc0df, 0xe5e5ae5e, 0x9c792b2f, ++ 0x5e045fff, 0xaff809ef, 0xff3c5f41, 0x43cca077, 0x822347fd, 0x5ee92bc7, ++ 0xc413c445, 0xfd836a39, 0x2c3ec0b6, 0x6ef822bd, 0xf4fdd5e5, 0xa979bab5, ++ 0x8af47f3d, 0x7b07afe0, 0xf3d3365e, 0x74395cff, 0x9fa1e7f0, 0x7dfbc2df, ++ 0x6479b178, 0x7c476be6, 0x51971864, 0x49f1e219, 0x3c783770, 0xf2edffe4, ++ 0x9c77fe00, 0x443ddeae, 0x2d871dc8, 0x6d95f178, 0xfd2aa584, 0xfdfe5138, ++ 0xa2dfa80b, 0xa5f1a7eb, 0x584ee22c, 0x843e61d6, 0x2b656388, 0x0724ec8c, ++ 0xaa5149d8, 0x8fde0e67, 0xe625723d, 0x13ef89e3, 0xb8a3e632, 0x2dbeea39, ++ 0x9b371f54, 0x3d6f7fa9, 0x7fcc7b2f, 0xcfc1fbdb, 0x1b4dfa6f, 0x7bfb338a, ++ 0xc7ae004a, 0x29611516, 0xefc58d22, 0x3dbff230, 0x1e34deca, 0xcf73a8d7, ++ 0xe57af687, 0xacdc430e, 0xefd1fe2f, 0x3c5f939f, 0x0ce6be3e, 0x578d03e6, ++ 0x3379d326, 0x7cf1ba67, 0xd18e71bc, 0x366a68fe, 0x2cb71fda, 0xdf386618, ++ 0x370d179a, 0x1f2eb7c0, 0x0f838065, 0xcf00cb7c, 0x30d1355f, 0xd70d82de, ++ 0x78efda19, 0x5e01a664, 0x0326edb8, 0xefcef77c, 0xc68b9c26, 0x0f3b5a73, ++ 0x9d5ef512, 0xbf4eb8c3, 0xbdaf846c, 0xc76f3c60, 0xf3c2339f, 0xa0f88a47, ++ 0x0f8a54ca, 0xed9ea65e, 0xf9abff87, 0x465d2feb, 0xeeb884a4, 0x106ffb45, ++ 0x4f332dfe, 0xc72a3d27, 0x5abcf0a6, 0xef1eac5f, 0x5762d7df, 0x185f7d1d, ++ 0x1edef3c9, 0x6bde291e, 0x4d5d9abe, 0x309350fb, 0xda78c26f, 0x7d7cdaf3, ++ 0xc3cc46fa, 0xd897553c, 0xd6bfd6c7, 0x81bce7b9, 0x97d95f02, 0x7b332fe5, ++ 0xdeffd244, 0x4eeb60cb, 0x91d825f7, 0x6c1af409, 0x95e8c19e, 0xf62a2fd8, ++ 0xd6f172e5, 0x29ea2b60, 0xea6ab71e, 0x7ffdfa91, 0x855b8ecd, 0xb7da313e, ++ 0xbefc4cb9, 0xdd86dfcd, 0xf3cb4df9, 0xbec2bd23, 0xc11af0e3, 0xbe497f1f, ++ 0xe7dff8c2, 0xc5ddfc6a, 0x2d373f50, 0x64902cb6, 0x34ae52ff, 0x89f2e7fd, ++ 0xb75d86bf, 0x9d77f604, 0xc60f7635, 0xea39f6e5, 0xf12bf3ed, 0x6ecc8e73, ++ 0xa7c7eaab, 0x0322caec, 0xef4ac89f, 0xcfb7ec50, 0xfbf88cb1, 0xd89395d6, ++ 0x6b6ae2c5, 0x2b79e495, 0xc5fe5765, 0xf177d7ed, 0xe573edbe, 0x614bbbec, ++ 0x2607b609, 0x2f1087d1, 0x57732785, 0xfe6e425d, 0xc347fae2, 0xe87dd37b, ++ 0xef2fb84f, 0x5becd35c, 0x7abceb2c, 0x8ee837bb, 0x4f15bd91, 0xb7f1ede3, ++ 0xfb7edebd, 0xfaebb34b, 0x36cc7bdb, 0xf3d5ef6e, 0xf6f32fd2, 0x614cfa9e, ++ 0xea1a6607, 0x762aff7b, 0xb277bb5c, 0x81a6ec9b, 0x5f6495f7, 0x78ea7969, ++ 0xed0a597f, 0x736c0493, 0x49c87bf3, 0xa1b31ec2, 0x6d41959d, 0xdda38e2a, ++ 0xff18ca67, 0x4d57edd0, 0x5131bd82, 0x12dbb631, 0x89560ae2, 0x57bdefef, ++ 0x3b44bb0a, 0x9dee130f, 0xd38e67ec, 0xe7abc4bd, 0x0d7dd38e, 0x35ef1b73, ++ 0x78bb9c27, 0xa7427a9c, 0x5c3bf0d9, 0x35107cfd, 0x38c04fdc, 0x659bf786, ++ 0xfdf125d6, 0x2f9daaea, 0x2a23f9e9, 0xfa0f7df1, 0xd117c4ad, 0xe46bc956, ++ 0x4f1f5e27, 0x193e7133, 0x349ecbc2, 0x057b2866, 0xf81af53f, 0xef65afea, ++ 0x099698c8, 0xe2be6ea6, 0xb474b08f, 0xfb1e79bf, 0x9ef12830, 0xbf116f22, ++ 0x44f7c8a7, 0x60c7f3dc, 0x27bd2b3f, 0x6ceef760, 0x6c9df7c5, 0x26a3df98, ++ 0x0fba2fe5, 0xdaf2106f, 0xa6eff0a0, 0xa178284e, 0xbca5cd1b, 0x495f2085, ++ 0x2f9123f8, 0x5b4517f3, 0x2322ffa9, 0x99fc695f, 0xf8d2a718, 0xaf1096d4, ++ 0x9f38c3da, 0xcf841ded, 0x62bf84f2, 0xba05ebbf, 0xe8badad7, 0x277bfe05, ++ 0x247a8ca7, 0xf9c5d17f, 0x1bda0b6c, 0xfa162718, 0x0fb0a265, 0xf91652b4, ++ 0xaf4e5015, 0x7503e830, 0xa5f88595, 0xd7265f77, 0xf654a233, 0xd8feb85b, ++ 0x9747f5c7, 0x380a8fa8, 0x3070e314, 0x189f61c6, 0xa29f6bbf, 0xcbafd7e3, ++ 0x8a4c0d17, 0x39be3359, 0xa1b93d5f, 0x7f37ce8e, 0x7bc54b35, 0xabe45ac5, ++ 0x8cdf7a4a, 0xec75fee2, 0x538c3ecc, 0x3bfc29d7, 0xf817b5bb, 0x996a5b77, ++ 0x629407cd, 0x6e9f7baf, 0xd5f39253, 0xb7174c3b, 0x71e7609c, 0xd17c06ab, ++ 0x1ffd0ab0, 0xff9a67ce, 0x400fed84, 0x7c75437d, 0x5b5fd60e, 0x07b2ff02, ++ 0x77c68df2, 0xfcd35e9a, 0xc5a51aa2, 0x880c788f, 0xe4b5b27f, 0x7f880e7f, ++ 0xe8fee05e, 0x81cf7160, 0x7c141ef2, 0x89e71711, 0x76a56b06, 0xf19884ce, ++ 0x3ed189dc, 0xaa8fc3af, 0xc95f1d03, 0xf85df466, 0x4ba9f3fe, 0xfa9455f0, ++ 0xf04bbac1, 0x62e017be, 0xa1549fa1, 0xf77fa887, 0xce34ac1f, 0x3dda59eb, ++ 0xc52b7c4e, 0xca0edc21, 0x7efc043f, 0x32913f84, 0x5d611ea8, 0x17bd3347, ++ 0xb5a40be1, 0xfa986e76, 0xabedade9, 0x56f4ed29, 0x3b313f7a, 0xa79ff295, ++ 0xa9bbfccb, 0xde1e3e5a, 0x0d57e527, 0xa8f76ba4, 0xd3dfd22c, 0xd94a7b45, ++ 0x5e273a79, 0xe782fcaf, 0x28e7e037, 0xca26f374, 0x5d0bc4eb, 0xcf002f74, ++ 0x7cbfbdd1, 0xabf7d181, 0x4eb5d053, 0x95aa9f72, 0xfdb9b2eb, 0xe8ff5897, ++ 0xad9f6e28, 0xa9f7e72f, 0x92296513, 0x4d7e7eec, 0x8fbe8841, 0xbd0a56b8, ++ 0x9150f98f, 0x77f95bdf, 0xfbd0e533, 0xe3ee80f3, 0xd7a3dd0b, 0x73fefeb3, ++ 0x9fe05c71, 0xa7ddcfd7, 0xebc7bde2, 0xe2bf230a, 0xca7653f5, 0xe55d7cdb, ++ 0xe782e7df, 0xde811bd5, 0xb77bdd13, 0x899384fe, 0xa2ee4e49, 0x5c5673e2, ++ 0x35b5c81f, 0x1f45a6be, 0xe1f6d167, 0x6dea1288, 0xf3cf71c5, 0x4ee9b9df, ++ 0xed077d8f, 0xe62fa46d, 0x8fcf5a21, 0x7f1933bd, 0xe702054f, 0x51befb43, ++ 0x2e9deedc, 0x89be8d60, 0x058530f3, 0x7dfecead, 0x3bfc3d91, 0x1bdd83ef, ++ 0x0459574c, 0x23c04c4d, 0xdc78c5e6, 0x6f1a12fe, 0x4cfbc2ba, 0xae87f714, ++ 0x132e9c0b, 0x57fcf3cf, 0xc0269be4, 0x2085fa63, 0xbdd785e9, 0xc2d7d6ef, ++ 0xdc1d53fc, 0x8c8c03d5, 0x75e445fa, 0xa7e0bd4e, 0xcbd7dc3c, 0x41898c77, ++ 0xcc4c75bd, 0x6c87bfcc, 0xfac1f78c, 0xa97d7072, 0x7f88e715, 0x1de85e26, ++ 0x9f47bfa2, 0x67c633e6, 0x4b385c8e, 0x7fa8997c, 0x3c2371ac, 0x4fd44955, ++ 0xde3bfc1d, 0xa70aa217, 0xba2d5327, 0x7e589d7d, 0x41a77e92, 0xa7cbdfdb, ++ 0xbf802057, 0x1cf1342b, 0x40f79eff, 0x75a01d7a, 0x612bd3f7, 0xd7a1071f, ++ 0xa467fd40, 0x9f8c75b3, 0x445ffde3, 0x94a3c9bf, 0xdc69fcbe, 0xd390ab4f, ++ 0xff380b57, 0xfe07fabc, 0x4f2018bb, 0xe47ef8bd, 0xf49c676b, 0x33fc6a9d, ++ 0xebc9f4eb, 0x5c9fa7ee, 0x8df5eaa2, 0xe9833e91, 0x5fb9359b, 0x7c8df41a, ++ 0x90a3c85e, 0xe55f6d0b, 0xeb379738, 0x8c8f9039, 0xa449397e, 0x7701f7ef, ++ 0xfa81fe43, 0xd68fdd12, 0x6c7af9ba, 0xb75eb8a7, 0x9b768c21, 0xc52fbda2, ++ 0x7cad23ef, 0xfced24a8, 0x3b593f3e, 0xf59f41e6, 0x79f4fbf8, 0x97dfbd32, ++ 0x8dee221f, 0x2751c6fb, 0x9a9773d3, 0x7cdf8b4f, 0x68f779dd, 0xfa84b971, ++ 0xb9af00ff, 0x80005f58, 0x00008000, 0x00088b1f, 0x00000000, 0x7dedff00, ++ 0x5554740b, 0x55b9e896, 0x92556eb7, 0x4849524a, 0x370f90a8, 0x00946084, ++ 0x07e47e45, 0x301084a9, 0x68205d82, 0x882a6210, 0x01521288, 0xae59c6d1, ++ 0x08626149, 0xa5d0bda8, 0x339e663c, 0xc0e03053, 0x1a44f68c, 0x29c120e9, ++ 0xdab433e4, 0x79a681dd, 0xc1addd3a, 0x9af0ec66, 0x0fb4214f, 0xede3e0df, ++ 0xa4bdcfbd, 0x4456e56e, 0x9c7baa5b, 0xe1ed5ea9, 0x67dff3dc, 0x2739f7ff, ++ 0x2b99398c, 0xe7fdb196, 0x303318eb, 0xcb573e66, 0x63147f53, 0x36498c85, ++ 0x18128be6, 0x2d03fcfc, 0x4ac71790, 0xe6328db6, 0x7d353b79, 0xed4d5ec7, ++ 0xc7485ca4, 0xa33b7b40, 0x3f6866f6, 0x7d686b2b, 0xca59f627, 0xdae8d458, ++ 0xbfa09a0f, 0x318f2c77, 0x17d41e77, 0x5303995b, 0x13ba7fbb, 0x26d30ed2, ++ 0xb195a247, 0x57fb4f0d, 0xba8d20b8, 0x12fb29ed, 0xafe3af48, 0x40fa6872, ++ 0x2b36a3ba, 0x5d6db18e, 0x2349d7db, 0x983af318, 0x4a860723, 0xfea3ee6b, ++ 0x1c6b7ad5, 0x18648130, 0x45deec67, 0xef5c30ef, 0x79864c93, 0x364c5d49, ++ 0x77ed0fc7, 0xc769c9bd, 0xd6a47579, 0xeb5e71da, 0x934d5e13, 0x7ceb7d21, ++ 0xd609bdad, 0xe3e04de9, 0xc770bfec, 0x4ae3066c, 0x8c23d5e9, 0xa2ffe602, ++ 0x31c20c6b, 0x2358de7d, 0x6c894794, 0x70889893, 0x824ffdf5, 0x08a939e7, ++ 0x1c637d20, 0xb2cfba73, 0xd6f7d614, 0x43d827d9, 0x67ced879, 0x8d7981c9, ++ 0x409939b6, 0x4cc732fd, 0x926d9780, 0xc451c2bb, 0xc39d3598, 0x96700ad9, ++ 0x76b1ce01, 0x58f907a8, 0xa138731b, 0x33d7199e, 0x9977f709, 0x6afd7825, ++ 0xdabe99da, 0xbb3be0c2, 0x29605d76, 0xfe05bfd0, 0xdbd6ed0d, 0x309c5b57, ++ 0x4bb3b28f, 0xde075b99, 0x9359d263, 0x1bdb0e39, 0x78f2f966, 0xecc371fd, ++ 0x387fd60b, 0xcd33e68e, 0x1bdf03ad, 0xc278ce70, 0xb8762cbe, 0xee6d027e, ++ 0xb39eb089, 0x674fbd52, 0xbeca65bc, 0xc27c5d46, 0x5eb3fb8e, 0xf680fd68, ++ 0xd8eac727, 0x4fd686c1, 0x3ea81873, 0xfc3527fd, 0x5503d0b8, 0xe0a890d9, ++ 0xa62cc8a1, 0x45f2c1c4, 0x47ec0fd8, 0x4af744e7, 0xcf1517dc, 0x8437d845, ++ 0x4f9dd7fb, 0xa94f8393, 0xfbfba27a, 0xeb6dfd7a, 0xf6f4cd5a, 0xbb1c06f3, ++ 0xd097da44, 0xcf32b2ef, 0xd91f3b15, 0x1af70670, 0x5fff00e7, 0x934abdd9, ++ 0xb93cf4f7, 0x60ee4ce1, 0x03fe057e, 0x08d6c3e0, 0xac662b22, 0x95b11799, ++ 0x01933fac, 0x65118f62, 0xd0c5b7ea, 0xf00b2a7f, 0x67fa62f0, 0xfe1a2f29, ++ 0x4ed7d353, 0xd37ff247, 0x8ab96857, 0x3f10cbe7, 0x9f333521, 0x666ffb88, ++ 0xfa9e467d, 0xa60225c4, 0xc6cb237e, 0x6530cdd4, 0xffe155ac, 0x2f52c9ff, ++ 0xdbec3a60, 0xadf7c654, 0x80a40aee, 0x92e97527, 0x035c918f, 0x9729a7a9, ++ 0x6e54fdbb, 0x9f311871, 0x788f159b, 0x26dd6ed1, 0x502cca62, 0x22e498bf, ++ 0x7ddceafd, 0x7f7c1b46, 0x12320dae, 0x6fec73a7, 0xf82782b5, 0x42be40b3, ++ 0xffc7b7a1, 0xd23a6af0, 0x7e4574c5, 0xf612039a, 0xdf4e8379, 0x722ff0cd, ++ 0x25ef7941, 0xdb7889c9, 0xadc8fb79, 0xfeea2748, 0xb40b2719, 0x1c09bd6f, ++ 0x92a9bdaf, 0x075f076f, 0x55377fd5, 0xcf23757a, 0xb8298d7b, 0x03eb8c7f, ++ 0x0a339857, 0xfd772bf1, 0x9d69062a, 0xe2637985, 0xf0f396b1, 0xa957a858, ++ 0xae646fcc, 0x9c02fd40, 0x67f8667c, 0x6cd36e65, 0xded4f806, 0x804667ea, ++ 0x8f20bbcb, 0x365d7cbd, 0x0534e75c, 0xf17b666e, 0xbe0f58c3, 0x0562c5ba, ++ 0x7e106314, 0x3e9063a7, 0xefdec0a4, 0x962e500b, 0x38555cba, 0x4fda80cf, ++ 0x9cacbc08, 0x7216c78f, 0x7b97593e, 0x9bdb093c, 0xca7021ed, 0x05d6827a, ++ 0xc7ee192d, 0x2a81bc20, 0xd9f19453, 0xdca4dc20, 0x3e38b3aa, 0xb03b3633, ++ 0xb4d769bf, 0xd15c55fd, 0x368745e6, 0xf36ba52f, 0x83293caa, 0x981f48aa, ++ 0x4e5e01fa, 0x0e72ef45, 0x8cabbd70, 0xcaae8805, 0xd791b758, 0x6df52873, ++ 0xf98c7744, 0xb709ae8c, 0x5a0af532, 0xff5f0cf8, 0xb8f1e200, 0xa153bcc1, ++ 0xcf580a97, 0xf5a1ac98, 0x244e4d2f, 0x3f0b7c7c, 0x9fcdbec1, 0xd3e23b1c, ++ 0x7c9634f1, 0x3077d61d, 0x9ab1af6b, 0xb34ab5e0, 0x5f84874f, 0x73fdf0c7, ++ 0x7be0735a, 0x535fb2b5, 0x41889fcf, 0xa2f151bc, 0x72afc15c, 0x464bfaeb, ++ 0xf16abfd8, 0xbf88d9e1, 0xdfcce2e5, 0xe139be11, 0x4abed07f, 0x86b95f69, ++ 0x55f38889, 0x906ff816, 0x02c69bfc, 0x7f71e287, 0x8e2369d8, 0x1194895b, ++ 0xaf539fb4, 0xa0fa9a4a, 0xcafad32f, 0x35b3e843, 0xd58c7d64, 0x76853ed8, ++ 0xd70bf302, 0x7fa70fc7, 0xb553ec88, 0xfec76a7f, 0x3ba475df, 0xc1f01bec, ++ 0x8ac1a5f2, 0x26540ef8, 0x2721c9ea, 0x5c287ce3, 0xff0aedff, 0xd0b36f69, ++ 0x17e0ddfe, 0xf01bb4d0, 0x7fe40d9d, 0x8eb47e85, 0x7c0ad1f6, 0x2e93e713, ++ 0xdab77df3, 0xfb07cf99, 0x09f4756e, 0xdc04af98, 0xb3bc824e, 0x2f1fd5b0, ++ 0xe90990e3, 0xf2ee104b, 0xaac7a266, 0x3b0e5c6b, 0x198731cf, 0x18d79dca, ++ 0xa63c87a7, 0xb4e5dbf0, 0x71bf2aaf, 0x143eeb5e, 0x9963e587, 0x0697e143, ++ 0xded2b96d, 0x0c27080a, 0xc32023c5, 0xaadf5893, 0x6f818fd4, 0xad25016b, ++ 0xfe609e0a, 0x75ba5829, 0xa400e02c, 0x020c30d1, 0xbe842625, 0xd1af090f, ++ 0x45cc8dfc, 0x5ab951e5, 0xfe22307c, 0x03e50dc5, 0xf843c446, 0x473a026e, ++ 0xa11c69b9, 0xdb19f76d, 0xae7c426a, 0x2fb5e6ba, 0x5a48b821, 0x0e04b8b8, ++ 0xad335f17, 0xd75952ab, 0xe9fb2133, 0x566f36bf, 0x5bf7d416, 0x1a4e1505, ++ 0x335ff1fc, 0x7afe7f50, 0xc2cc67c1, 0xf9a72f71, 0x5faf3d79, 0x7df03f95, ++ 0xd07df201, 0x300fee77, 0x7bcc3c67, 0xfff7a140, 0xae738cad, 0x7de946cd, ++ 0x38426bcc, 0x678e642c, 0xcfbb43a6, 0xb4ca5ce7, 0x4363fe40, 0xa40371e0, ++ 0xf819dd1f, 0xfbd605b4, 0x17fbb256, 0xda6f0193, 0x82fcfcbf, 0xd8faba07, ++ 0x20ef1d9a, 0x933cf87c, 0x34a003e3, 0x8a37bbae, 0x5bac09e4, 0x590acda4, ++ 0xc23e286f, 0x77a4ac7a, 0xd1275d0d, 0xf10fae09, 0xeebfad4e, 0xe57fcfcb, ++ 0x3feff581, 0xfa40eb10, 0xf3fe7fdf, 0x43e7c889, 0xe3e037d7, 0x53aea5f4, ++ 0xe8d57f6d, 0x3939373e, 0xdbf67c68, 0x4dd13738, 0xf0e9c922, 0xf6e5e374, ++ 0x042bc587, 0xef9531cb, 0x4dae121d, 0x683ed337, 0x2bb4dcf9, 0xe4193c5a, ++ 0xe542ab7b, 0xc1f14dd9, 0xcc60c003, 0x3f086c59, 0x9583e50c, 0xff89fad7, ++ 0x307cb1fd, 0x60f81f21, 0xf2cefb0c, 0x19938dc1, 0x63eb22a5, 0xf7bb4e5c, ++ 0x2c7801bc, 0x8db64a16, 0x927e8ab4, 0x1fa2a2eb, 0xe9cb1f3f, 0xdf1cec19, ++ 0x6fbf010e, 0x1660f25a, 0x71ea57b5, 0x687f1a7d, 0x2ddb887f, 0xc751bf7f, ++ 0x9067f2af, 0x17bf705a, 0xfad367e4, 0x52a7e3f7, 0x40f7498e, 0x5f42f3f9, ++ 0xceb883fd, 0xff640c2f, 0xdcf973b2, 0xc3b2240f, 0xf0f3fc22, 0xbf4b6ad5, ++ 0x253c2875, 0x12da70f9, 0x1b0edfc0, 0xf9e03660, 0x2776d93f, 0x8b553572, ++ 0xd5d4e6ef, 0xa82f5516, 0x53c8bc02, 0xb02f3ef0, 0xd8d0f48c, 0x098da711, ++ 0x1ddf1f90, 0x3a718faa, 0x07fa9511, 0x9f89f784, 0x9efa16c7, 0x76373546, ++ 0xc5af16a7, 0x47449d2b, 0xb43fdc56, 0x81e4427b, 0xba25a818, 0xcef44312, ++ 0xfe457cd6, 0x60a2b117, 0x3ac58dfc, 0x7d14b790, 0xdbeefa42, 0x92313f57, ++ 0x512e70bd, 0xaed36f83, 0xefe2c3ca, 0xeafc2a3f, 0x185fc435, 0x9f0a87fa, ++ 0x53b36eea, 0x4c9b777e, 0x5cb69ee9, 0xcdb7befa, 0xb69ef941, 0xf5e94512, ++ 0xa1ba3f12, 0xc4d882f7, 0x5c8a4979, 0xe45f9897, 0xf0544fa9, 0xfb445731, ++ 0x363b459b, 0xfb7a980a, 0x859f7d79, 0xd719bb97, 0xd33cfef7, 0xa99e4532, ++ 0xb70184f9, 0x246ff117, 0xf47efa30, 0x0bf82847, 0x0b1ce9f8, 0xeb19d15b, ++ 0xe7ffa3b6, 0x3b32ea60, 0xed9e7796, 0x199213b4, 0xfc76359b, 0x86d7bb0c, ++ 0x6ea588fd, 0xfd986d8b, 0x9b3eec92, 0xae07fb9b, 0xc7bb475f, 0x98c0f1ce, ++ 0xdda2b526, 0xe5b037ef, 0xbbed41dd, 0x76fdb80b, 0xd5b85f24, 0xcc149c7e, ++ 0x5381645f, 0x078fb039, 0xfe3a1e71, 0x51f95380, 0xbdc79a91, 0x103da3b7, ++ 0xd0dbedcb, 0x815efc79, 0xdc31c1c7, 0xfcb4373f, 0x6ebdfb96, 0xc03c73cc, ++ 0x55eb2bab, 0xd543e223, 0x9e219b80, 0x25729048, 0x65afeb93, 0xdf833f4a, ++ 0xf64adeb9, 0xa27a8cb6, 0xe90ba4e3, 0x9039806a, 0xe1f6484d, 0x9157bee9, ++ 0x7229cf5b, 0x062badeb, 0xd6dfff5d, 0x1be69102, 0x80c77dfa, 0x051cfd7e, ++ 0x7d337adf, 0x7767a8ed, 0x00706cbe, 0xf6756647, 0x1fc851ce, 0x42581adf, ++ 0x7cdccf78, 0x5815b35d, 0x5eddd9d6, 0xf9c67446, 0x9f22995b, 0x44bbfceb, ++ 0x89d603f4, 0x7dfd113e, 0xeccb6915, 0xd4cefeb8, 0xc733fe30, 0x1f2a1683, ++ 0x92e54258, 0x1de91b7d, 0xc388e943, 0x7c4bc767, 0x9f76753e, 0x99c47e88, ++ 0x84455bb9, 0x7c0a8bff, 0xa89b72ea, 0x7fcb3cdc, 0xbb382458, 0x997fd89d, ++ 0xa63b6b63, 0x09d60392, 0x36713a72, 0xb264f873, 0xc8d9d7b7, 0x3a5afb6f, ++ 0x4e551fca, 0xa842f6a8, 0x219a39fc, 0x19d3dd91, 0x0abe9030, 0x80cf67f5, ++ 0xb52977fa, 0x649de9ad, 0x776e7407, 0x9eb1141c, 0xc63f2043, 0x930fb95d, ++ 0x72e6b27c, 0x7522ac7d, 0x22c93b5b, 0xa013e09f, 0x2f053aff, 0xfab4f2ea, ++ 0x74e39956, 0x57a61c7b, 0xaa6672b5, 0xfa8477a2, 0xda85ac25, 0x2281757c, ++ 0x3cb9728f, 0x1ffb306a, 0xd692fa43, 0x040c2508, 0x211ad45f, 0x2ee3e715, ++ 0x08e97ee0, 0x49e6cfd0, 0x95667690, 0x68c7ff90, 0x0081fa3f, 0xbcc4340b, ++ 0x66fb8696, 0x28fc901c, 0x3b40c177, 0x4b8eafd7, 0x8dba6f7a, 0xe8a649f4, ++ 0x9bc4b685, 0xc89fe7f2, 0xd3bcfce0, 0x75bbeac4, 0x80b6aff0, 0x328f8df3, ++ 0xf8f5eb5a, 0xb65e5a8a, 0x22392046, 0xcca4f229, 0xf47a9cce, 0x20dfd6a4, ++ 0x76553e71, 0x9308f58d, 0xf1cb2fd0, 0xd6536766, 0x8153b436, 0xf37a9c5e, ++ 0xf4e428c9, 0x59816ef8, 0xf5391ff5, 0x95cff2f8, 0xfebcaafd, 0xbe387d94, ++ 0xb900ae61, 0x823dfb87, 0xf3a523f7, 0xa7912571, 0x3c790a53, 0x4f117ae5, ++ 0x27228a1b, 0x4764a677, 0x81220f0e, 0x5e9031d7, 0xf7d1b7cf, 0x483bb1e9, ++ 0x8e02443e, 0x638411d9, 0xa6f1cc99, 0x4bc5a1cc, 0x67b782a3, 0x3f86220b, ++ 0x904796f7, 0x7f02448f, 0xf45bbeca, 0xbbf4aa70, 0x91293fb5, 0x8731cf5c, ++ 0xe510acbb, 0xe44f80ce, 0xd7ae0e71, 0x3dc13bbc, 0x8abdfb55, 0x6fed20e2, ++ 0x77efebe9, 0x123d7c29, 0xf80558f4, 0xffd32f3b, 0xdefe9ea0, 0xbe311858, ++ 0xe61d3290, 0xf5c490d1, 0xb479d09c, 0x1e0c4616, 0x1e606b9b, 0x8780258b, ++ 0x8bacbece, 0xd7363c1c, 0x0a2ebda2, 0x7b979e3c, 0xc8318cec, 0x58df810e, ++ 0x4af5ea03, 0xf465f41e, 0x2c9e83a5, 0xc3e2f538, 0xbf08225b, 0x1ea0e33a, ++ 0x8e8f3a15, 0x337e1c29, 0xf51ebe98, 0x79e6e47a, 0x7a36546f, 0x4a7d3937, ++ 0x7f35f461, 0xd3ecc461, 0xd06336cd, 0x9134467c, 0x2d9a4c93, 0x27abeae8, ++ 0x90885ed0, 0x3806483c, 0x2cd83bb5, 0x36fcf83d, 0x6295fb72, 0x04f97487, ++ 0xc985a7f7, 0x4cf97768, 0xa2f43009, 0xe05e5511, 0x0907eccc, 0x41dbbaae, ++ 0x6b3def4f, 0x9ea36c70, 0xbe280b02, 0xd0183769, 0xee7e65ff, 0xf5fd17b0, ++ 0x8381e955, 0x8dfe7e66, 0x031535e2, 0xfe4669cc, 0x8c5edccf, 0x653d956f, ++ 0xe8e7e7ca, 0x98d9bdb8, 0xfcc0e090, 0x7b4081f4, 0x4f9da41c, 0x5da074e5, ++ 0x47d03557, 0x3f40e779, 0xf6a179d9, 0x8fbdbf66, 0x02548de4, 0x1fda2926, ++ 0xcc467de9, 0x4e7ded5b, 0x455bb78c, 0x3d4321c1, 0x5f6bc071, 0x48fe4852, ++ 0xe0839387, 0xa353f624, 0x85ba63c0, 0xec6abdc7, 0x502e28cb, 0x87981251, ++ 0xc77e1f76, 0x128d57f8, 0xf9b4aaff, 0xdd342e28, 0xab43b5a6, 0xf3c44c03, ++ 0x82f1a10e, 0xdedc03a9, 0xb027121d, 0x9d68ff73, 0x8d0f07e2, 0xb827581b, ++ 0xded08a53, 0x2e283b00, 0x658e5071, 0xc9f9189b, 0xe7cc033b, 0x25f482cd, ++ 0x6dcdfb91, 0x0b272f82, 0x5a061ce3, 0xd9133947, 0x53b34862, 0x4b9d225d, ++ 0xe2d8f804, 0x5c02c595, 0xf04f6fb2, 0xdcfb246d, 0xfd54f04e, 0x3b9feb31, ++ 0xce85fe49, 0xff8ec554, 0xc18be6c2, 0x4c6dd3b8, 0x5dc2d4f8, 0x358f88f9, ++ 0xf25af322, 0x7e48ce29, 0x7bbb38d0, 0xec8e2db6, 0x1e211ea6, 0xc53227e3, ++ 0xb733a7e7, 0xbaf7a712, 0x65339e71, 0xf6fd0d8b, 0x5fa3f6e5, 0xb50279e0, ++ 0xf0e4e0be, 0x5b1b6417, 0x27b2fd0c, 0x6f18edfc, 0x9ee7933b, 0x29f80452, ++ 0xdcc5f528, 0x840befb9, 0x5e2cdf37, 0xc4fd2912, 0xeab42318, 0x91ddf1d1, ++ 0x6fa46b93, 0xc7300ddc, 0x7d33b4f9, 0x229af2be, 0x9c06ea27, 0xdaa828e2, ++ 0x087eea5c, 0x7b633de1, 0x55e60753, 0xc610dbbc, 0x6ffdf8af, 0x79da7f59, ++ 0xf88494f6, 0x1fe84177, 0x63757887, 0x8e20425d, 0x2f63e9fc, 0x1a9fa0a5, ++ 0x28bfbcf4, 0x3e8b73a2, 0xea2ee311, 0xba65e73c, 0x84d7a8ed, 0x173c67f3, ++ 0x737dfb39, 0x9ebc318a, 0x9b9137f5, 0x1bf3f107, 0xec7c8dfa, 0x9f5831b0, ++ 0x3e913471, 0x0436ff83, 0x764901f1, 0xf92b56b3, 0xe2e5755f, 0x83f4119b, ++ 0x8c5ca3a4, 0x748ed47b, 0xf60fb9da, 0x790fd315, 0x7ba7ceaa, 0x27c3c70a, ++ 0x2727224b, 0x229c63c7, 0x2bcf99be, 0x32f3e04a, 0xcd799a09, 0x3a70e129, ++ 0xf072253d, 0xd7f4862a, 0x8a8fee25, 0x96acdce8, 0x9fae403e, 0x769ba3d6, ++ 0x247284fc, 0x70f3a057, 0xb0067f20, 0x6e6d8d7d, 0x81c8024d, 0xf2b3dbe5, ++ 0xdad5be51, 0x422476b7, 0x4c9b51fe, 0xa569f97e, 0xf5ebdfee, 0x9fcee7f7, ++ 0x715faddb, 0xfc0dd87e, 0x35dca752, 0x9fdaa8c5, 0xbac9c5d1, 0xb16c67f6, ++ 0xd8c37c1e, 0x2253c99f, 0xb3856f6b, 0xb98a0b3f, 0xbf1c34bf, 0xdc8e282a, ++ 0x6b1ed13c, 0xd617630c, 0xb31e7044, 0xe17635b2, 0x7f106376, 0x8e0dc424, ++ 0xf1b80d57, 0x86fe168c, 0xb7148bd8, 0x8bdbe871, 0x4e47140f, 0x38c1cd1e, ++ 0x1cbeb566, 0x2c4714f7, 0xf7ef71be, 0x7d2fbd20, 0x5011a1eb, 0x7e30bcc4, ++ 0xb7dc60ca, 0x434abdde, 0x3a8df797, 0x0753a0fa, 0x1c899f1f, 0x1b454edc, ++ 0xd12c5f91, 0xa6aea73d, 0xf5f58b9d, 0x2453a5ab, 0xe6666fea, 0x6e7843ae, ++ 0xb32cf3a5, 0xcced1f21, 0xdbd22ff2, 0x7e14f787, 0xe39b3f50, 0xdfca2d4b, ++ 0x8a5b7aa0, 0x47b2fc79, 0xc3332b91, 0x22b949d0, 0xfe296707, 0xe63659e8, ++ 0xef53addc, 0xb311c587, 0x848d4fbb, 0xfeb46674, 0xe6576f7c, 0x7f18677b, ++ 0xe1c8a1c5, 0xa034e6e7, 0xfad59993, 0x39193cf3, 0x266f73fe, 0xfb5ee3cc, ++ 0xeed0330b, 0x33af259e, 0xc3fbf229, 0x5eb91d62, 0x50a3bcc7, 0x250c5e3f, ++ 0x1a9fb006, 0x49f29520, 0xf28c7f8e, 0x1b4001e8, 0x3e907e5b, 0xdc0f861f, ++ 0xc3e38536, 0x3fba26cf, 0xb9871bd5, 0xa2f6359b, 0xf22abf24, 0xf1217773, ++ 0xf1f7b47b, 0xf8b3093e, 0x4cf74098, 0x7df9123a, 0xa017ba3a, 0x5effabc6, ++ 0xf21f3fd4, 0x67231b56, 0x44776491, 0xf1857e93, 0xb1d92b79, 0x758edcd1, ++ 0xb9d5cf44, 0xba99d1c7, 0xcc34decc, 0xbb388efd, 0x4ed82eab, 0xbb5a9c15, ++ 0xd34dec13, 0x01f3a094, 0x98e9ddaa, 0xd14cb6ec, 0x14adf5c8, 0xdb53fabf, ++ 0x94119993, 0x643fa887, 0x9ee55d42, 0x785a1dd7, 0xbc00fc70, 0xbfe53099, ++ 0x46ccde26, 0xcde0e878, 0xc6f0f4f7, 0xf1c38532, 0x90ffd37d, 0xc68663ad, ++ 0xde7ed42b, 0xa82dbab7, 0x2fb7ad8f, 0x97bde0b1, 0xe2dbb74e, 0x58f3f2b0, ++ 0x7eeff7c1, 0x38bdc93d, 0xeec97c78, 0xa022f3a3, 0xedea368f, 0x347d3853, ++ 0xc9b3e141, 0x6666fcca, 0xe17f7e32, 0x0db7c17e, 0xb67a82ec, 0x467c84c9, ++ 0x125d1fad, 0x8ef63b39, 0x4f7fe26c, 0x1867adea, 0xf886d7fe, 0xeffcb378, ++ 0x715e8ab7, 0xc61fae1b, 0xf5ccd459, 0xa67619fa, 0x75fdbfab, 0x14baece4, ++ 0x4633a42b, 0x87af0d34, 0x161f3984, 0xa9ff7f41, 0x8f1c6cd8, 0x49d80fe3, ++ 0x27453cff, 0x22fdf74e, 0xcf4e1e5e, 0xbb39183f, 0x9868d4e8, 0x62bb236f, ++ 0xd3877f42, 0x1e8665f8, 0xc04d1b7c, 0x1fbe746f, 0xe735922b, 0xd9531ac9, ++ 0xdaadd00f, 0xdfafa099, 0x45e850ed, 0xcb42efd5, 0x1ed044b7, 0xf1c6c848, ++ 0x3b879e38, 0x08abf837, 0xb90b47c6, 0x7a0fe2df, 0x7f740df4, 0xe18f9755, ++ 0xe2dfad27, 0x09bbd63a, 0xe4a185bf, 0x7c5bf45b, 0xd8e1c456, 0x737e2619, ++ 0x4afb722a, 0x5e012fe7, 0x4f5f2599, 0xf25b1c4f, 0x50c4f435, 0x6f5e193e, ++ 0x2e3f9c8f, 0x31e388c3, 0x4c2b3efa, 0x1187f19c, 0x235487dc, 0xafa5a78e, ++ 0xeaee0546, 0x89281e7c, 0x6a735d98, 0x77e311a2, 0xef79e48c, 0x039e5ced, ++ 0x78e52dbd, 0xae37bfc2, 0x718ada4b, 0x7bba20a1, 0x744e8f58, 0xe4a5aee8, ++ 0xab85fce6, 0x8ff2f0f4, 0x7270bba5, 0x6fc29d64, 0x7562163f, 0x20ff73ef, ++ 0xbdcbfa72, 0x4ad7e839, 0xdfe79fd4, 0x9b1e6e45, 0xfafecb6f, 0x673d4cf2, ++ 0xd682aff9, 0x32aefeef, 0xf3912def, 0x308ca423, 0x70adca0e, 0x72923672, ++ 0x8e483e34, 0x83e186d6, 0x724f9c91, 0x3baa7c10, 0x6653a204, 0x561f1463, ++ 0x78895bef, 0x9838c59f, 0x37b833ff, 0x51a547f5, 0x070459a5, 0x5bdeaf35, ++ 0x4e3e0489, 0x3c44de30, 0xd0edc9c1, 0xa599efd0, 0x6ffcc452, 0x4d3bffc8, ++ 0xc967f7df, 0x5929e7e1, 0xc9e90cdd, 0x68656f6c, 0x563b9a6f, 0xf318f9d1, ++ 0xf47e55ec, 0x810eb25f, 0xb66121de, 0x92fe3413, 0xe411ef74, 0x74f9430f, ++ 0x7ee4c467, 0x4defe221, 0xbd4051fa, 0x7f8d9b71, 0x53fd7c7a, 0xcfc8a2a5, ++ 0xad4e0bdb, 0x7f7d42ff, 0xfd1db040, 0x6758fd02, 0x4acbdcf2, 0xd9da8393, ++ 0x37127bf8, 0x06f79f7b, 0x7e7b413e, 0xdf59ce5f, 0x13b2880a, 0xa5df0591, ++ 0x37a4654a, 0x0ebbca48, 0x183afdea, 0x6fbd18ef, 0x6f20ce73, 0x72af72a4, ++ 0x6c71c47e, 0xa77d2162, 0x5f50a3fb, 0x36ecf7e4, 0xf3b512c9, 0xdb147a8e, ++ 0xe326976d, 0xf7e82239, 0x6f9d1c58, 0x99373f71, 0x237937f7, 0x9967ae0b, ++ 0xb4c3f4ac, 0x0fbaf4f7, 0xa8b951c5, 0xf7b5bfd4, 0x7c2876ef, 0xf0e04cab, ++ 0xdaefbf57, 0x3fee97b1, 0xa6eb9f56, 0x3be5787b, 0xaf288dbb, 0x47b9cfcb, ++ 0xe067c70f, 0xc1286897, 0xa4a09fc4, 0xeb4ec182, 0x843f3016, 0x13df6d2f, ++ 0x5fd30f23, 0x1b6eb9f9, 0x76bbc3da, 0xa7f57458, 0xefd72940, 0xfd87eda5, ++ 0xcac65aa8, 0x8d0fe455, 0xc346b099, 0xbbed3b0f, 0x73d63d69, 0xf46fba7e, ++ 0x7a09de6c, 0xdf1ca0e7, 0x1c719043, 0xa7fdee9f, 0xbf76e7f5, 0xc5f11137, ++ 0x50391cc6, 0xbf1cf3af, 0xaf3fbfa7, 0x0f9e3b7a, 0xc23bdf52, 0xca1e8d77, ++ 0xa6f79e0b, 0x37e8a5c4, 0x198eedb3, 0x04bf8c3b, 0x3af587d7, 0x97840dd2, ++ 0xefe6f3fb, 0x78a18410, 0x3ee49b6f, 0x69ac9a56, 0x8ac87967, 0x9619aceb, ++ 0xfd3077ef, 0xa5a7f238, 0x65da5f5c, 0x46b25a72, 0x07457c20, 0xdb2dce50, ++ 0x8c271af7, 0xdbe78853, 0x7c1f0e8c, 0x44b92a3d, 0x14d1e384, 0x38026d81, ++ 0x1ddf4fae, 0x495f9c33, 0xc36783c5, 0x294767ac, 0xb63a63b7, 0xf74fdc77, ++ 0xe846078f, 0x7a1109f2, 0x0a72fba1, 0x77cbc89f, 0x1a2d2e5f, 0x630def0a, ++ 0xc58fc9ba, 0x057fe606, 0xbf9a7f5f, 0xe9bdd4c3, 0x37205adf, 0xe1eb676b, ++ 0xf1e6f968, 0xaca9577c, 0x3aea57e1, 0x8b9625db, 0x86bcd3f7, 0xa9f20768, ++ 0x117ed639, 0x46999dcf, 0x558fc804, 0xbef1c659, 0xc967e55d, 0xd3199f9c, ++ 0xd1b27e38, 0x68577f32, 0xe913206c, 0x6c7fed59, 0x6f794199, 0xbf1d2fad, ++ 0xb13989cf, 0x36307646, 0x41b62caa, 0x89cd7804, 0x0b26b13f, 0x716519f2, ++ 0x7bac220d, 0x2b89da4e, 0xaee83659, 0xc7e79e2c, 0x0632b89f, 0x366559f2, ++ 0x0d87c79e, 0x2b0b0146, 0xe6f0684b, 0x4d36ff61, 0x12f063ff, 0x4f37f25d, ++ 0x6e83668d, 0xb28261dc, 0x7099f87e, 0xbfef571c, 0x65c3fc52, 0xbcf1fab1, ++ 0x429a7323, 0x14501ee2, 0x8d900f74, 0xaef92388, 0x4bbbebde, 0xf8a41ff4, ++ 0xf04fc589, 0x90758dbd, 0x7ad0083d, 0xcdc17ae9, 0x538283db, 0xd7dad72b, ++ 0xf1147732, 0xbc36c5f7, 0xa73027e7, 0xbf8f3ae1, 0x757c70b8, 0x43f8ea3e, ++ 0x8b5b05e6, 0x5e7065fc, 0xea3f50af, 0x364e2ebc, 0x7a9e517b, 0x6b6e59ab, ++ 0x0a2e9c10, 0x9d05bf81, 0xf6f97d9b, 0xbee2365f, 0x640d8c5e, 0xe2ff900a, ++ 0x9f68a7ad, 0xfe07262f, 0xe5047056, 0xef1f7c4d, 0xf683bb29, 0xbce89671, ++ 0x5af10ca7, 0xbc6176b2, 0x6e3a2ba1, 0x7d6f9e22, 0x45edd936, 0xe77807be, ++ 0xbcb677c0, 0x07639219, 0x50a6b3cc, 0xa1b97e7b, 0xd397f38c, 0x30cdbe0a, ++ 0x0e3d6a6f, 0x23d9e978, 0xdf5075b0, 0x84b2ed73, 0xde9cde7a, 0xff9e12d3, ++ 0x5a73d96a, 0x3cc53192, 0x8af2d3f4, 0x3c9feba4, 0xf454665f, 0x59b71e6c, ++ 0x3a70e36d, 0x99ee3192, 0x969f3011, 0x1fbd02a5, 0xc25f7ab2, 0x6eafcc0c, ++ 0x763255c2, 0x331bc57f, 0x5c1a5d10, 0xb4c19f07, 0x191ff591, 0xd0b42801, ++ 0x9072646d, 0x7968b83e, 0xf483930c, 0x24d686c1, 0x1371be4d, 0x4844ceec, ++ 0xda69a6d7, 0x9b5d3c31, 0x0cadef82, 0x8c14c4fe, 0x2df9f057, 0x87d73fb4, ++ 0x6e85b8f1, 0xa83fb793, 0xebbd39bf, 0xb44ff444, 0x7a0e0ab4, 0x64cbc136, ++ 0xaf88b76c, 0xb0715210, 0x467dc03e, 0xdef4408f, 0xe1f46cd2, 0x7b8b217b, ++ 0x78b57db8, 0x0593e0b9, 0x373f0384, 0xa811e9eb, 0x42f3d3dc, 0x3cafc60d, ++ 0x33bbf86b, 0xb6e2a329, 0xf552bde1, 0x32a36d1e, 0x71ef4f57, 0xe8b3f613, ++ 0x07de8171, 0xdf675e62, 0x37f9a0d8, 0x4b3acfd6, 0xff85e9f8, 0xb3ae0f15, ++ 0xce947e5e, 0xfe8e372b, 0x81c9de94, 0xd7e99df5, 0x6f9b53c0, 0x1be6d568, ++ 0xdbf36ad7, 0x497794cb, 0x48f1b3c6, 0x04cabb4f, 0xaafdcf11, 0xa71973f9, ++ 0x9fe7867e, 0xd7ae8817, 0x9b2360ca, 0xd444ff25, 0x6e8816c3, 0xf0e5abca, ++ 0x55eb85bd, 0x44fd27e2, 0x67d102c7, 0xc369c9bb, 0x2bbccbf7, 0x45dbc205, ++ 0x9f8eae58, 0xf29f5835, 0x8ff9a1c6, 0xdd1db8cb, 0x435ae51e, 0x8203a7fe, ++ 0xa90bdf0d, 0x62629d11, 0xbd45d11e, 0x57eabf1e, 0x7867e1e8, 0x35e61d1b, ++ 0xf614910e, 0xf13ddc69, 0xdc7a8e74, 0xd17934bf, 0x005719be, 0xdd232078, ++ 0x7cdad81b, 0x23e2454c, 0x8c3f0377, 0xb19c7482, 0xfbf89ebb, 0xdfc6c924, ++ 0x60b3b38d, 0xa5dce17e, 0x577d273d, 0xa7d231fa, 0x1cf2deef, 0x9b1f039d, ++ 0x017fcced, 0x1f1468e5, 0x827dd9ff, 0xd3f41d6f, 0xc7e3c792, 0x702d0123, ++ 0xc2bb16dc, 0x8f807b47, 0xfd87ebaa, 0x0d7c891d, 0xcecc040f, 0x2d5371a3, ++ 0x893bb62a, 0x6afe0a0f, 0x46cffa03, 0x5b3ee32a, 0xa7fd1325, 0xe02dda3c, ++ 0x779833ba, 0xfde3009d, 0x45b1031c, 0xb637e983, 0x76b46ad3, 0xddd118da, ++ 0xa56b7c80, 0xf1e25fbd, 0xf28480dd, 0xffec5be1, 0x61febd61, 0xa0aef4f9, ++ 0x18668fca, 0xfea1c5af, 0xf640fab4, 0xde8c3648, 0x3418b464, 0x8b64c47c, ++ 0xbb9bf0d6, 0x67fcb572, 0x77cb438e, 0xad9257be, 0x1ceb9f29, 0x67bf29af, ++ 0xbf268156, 0xa9ae55c0, 0x74fd5f7f, 0xaf6cde4d, 0x928fd4d3, 0x31f269e7, ++ 0xea6bf7b9, 0x68963ac7, 0x793fcdca, 0xfbc05eb3, 0xbf6f1610, 0x05d0e01b, ++ 0x389251b4, 0xc7c64728, 0xa3486541, 0x98aca20b, 0xfb364d76, 0x46ba4f11, ++ 0xc7897c81, 0xfddb8ff6, 0xfe258fd0, 0xf2680b35, 0x5f049fec, 0x01f41275, ++ 0xdea37260, 0xda53c777, 0xa6bbc0f3, 0x92ac7a29, 0x4f77284e, 0x6f3480ab, ++ 0xdfc69ca7, 0x03bbe9a1, 0xcd12c7f7, 0xd7b45eb8, 0x24d17a42, 0xf4829bd4, ++ 0xaaabe7c3, 0xddb1cbf2, 0x913bce53, 0xb30f582e, 0x1b6abfa1, 0xe728901a, ++ 0x1a77f2f6, 0x0dfa7af3, 0x7efa20ce, 0x21eb9ca7, 0xefaabb2f, 0x7a5bfec4, ++ 0x3d22ca41, 0x4244f96d, 0xf7a5af7d, 0xb3ca1c60, 0x244fae89, 0xbf063bb4, ++ 0x0c4e722b, 0x8239e344, 0xea36ee7f, 0xaab0ffbe, 0x51ffdf9c, 0x786835df, ++ 0x5de378dc, 0x41e2aa83, 0x46f0dcfe, 0xf1846fc0, 0x79af801b, 0x8f5937f9, ++ 0xfe7f034f, 0xbedf9824, 0x60f20a9c, 0x91a7f512, 0xf897f707, 0x967f244d, ++ 0xce37eb6b, 0x1877a5af, 0xbf6b8f81, 0x002aef2b, 0x1ea133a7, 0x5b5d7c0d, ++ 0xaf837e5e, 0x3e075de7, 0xff4b81f0, 0xa7378bbd, 0x0fdeb489, 0x1f69d3dc, ++ 0xe278065e, 0x8797fc7d, 0xf5c38fc0, 0x3af6e0ab, 0xfed040e2, 0x383bd685, ++ 0xebdfef8d, 0x31f6f861, 0x09b77f65, 0x54c8f97d, 0xc268ae3d, 0xa69645df, ++ 0x700a6715, 0x44ef3e5f, 0x4de1b23b, 0xfdbca181, 0xa49fc1d5, 0x6fbb3bd0, ++ 0xf7c1491c, 0x47dd3c67, 0x8e1df052, 0x0ebc9366, 0x0fc079f5, 0x2d3fea07, ++ 0xff9a7e3d, 0x7a02eeca, 0x8f656287, 0xec9640e0, 0x96a973d9, 0x3bfac9d6, ++ 0x16daeed1, 0x97cf5e66, 0x52df7c73, 0x3cfcd32e, 0x00437a6e, 0x3e7d9bda, ++ 0xf801f101, 0x1f6bce13, 0xdf9057d8, 0x7edf41b6, 0xef02a9fe, 0x86241bc3, ++ 0x433508ef, 0xd1c75c7b, 0x0592a38c, 0x580de9f1, 0x38eb8097, 0xfb0620be, ++ 0xa862635f, 0x3bf3a867, 0x11f7d19f, 0xa5c3ffae, 0x92a97c26, 0x12352fb5, ++ 0xc35c3fbc, 0x43e313f5, 0x0699deff, 0x978085f9, 0xd0eb0f78, 0xd347cbd2, ++ 0x970fdfa0, 0xfa6d3d73, 0xcba22643, 0xbeb8ab85, 0x2ad78a12, 0x82b5fede, ++ 0x1bf8a1a7, 0xf043b78a, 0xc337f975, 0x95cb37d7, 0xb3c63977, 0x61f72889, ++ 0x448c67ff, 0xd1927a3c, 0xd7f559bb, 0xc246990e, 0xda74c7bc, 0xb201601c, ++ 0x33df4609, 0x0e37c829, 0xcdc9f2f1, 0x7fce055b, 0x7d71fbe4, 0xc3125d69, ++ 0x72b1d6b8, 0x531f0fae, 0x01664df6, 0x3137ef01, 0xf20c6fb1, 0xce252ca9, ++ 0xeac4dbb1, 0x53fb40df, 0xc267fce4, 0x375bed8f, 0x13efe106, 0x7caa5e0a, ++ 0xdcc4bc71, 0x2b5da06f, 0x0b9a8f76, 0xdcaebcfd, 0xfa54c93f, 0xd40ec9cb, ++ 0xacf485ce, 0x0509fe32, 0xbffcd47f, 0xdcc0742b, 0x739e0917, 0x75fe1c2c, ++ 0x718bfd6b, 0xeecdb31d, 0x7ca1ca0f, 0x66a9e676, 0x635d7b94, 0x71e3cdde, ++ 0xe1e90733, 0x87fe051e, 0xcaf77f4a, 0xa8deb063, 0x7f69a3db, 0x60bc0ea3, ++ 0xca8e7c43, 0x9c391c29, 0x9ab9ef7d, 0x8049dcc5, 0x29b35757, 0xdf73f355, ++ 0x93f52b39, 0x96a9705d, 0x2a6ae5e8, 0x7ddb577d, 0x827bcca8, 0x7ac0e1c4, ++ 0x06dc9047, 0x04962dbe, 0x385539c5, 0x547af6a8, 0xafda76ce, 0xc9b156c7, ++ 0x17b1e6a4, 0xc736f394, 0xe7e82685, 0x64d3933e, 0x8a9f7805, 0x26715faf, ++ 0xdb77b187, 0xd8cb71d0, 0xe6166dfb, 0xb8f40dbe, 0xfbe51b36, 0x3f94ecda, ++ 0xda5326d1, 0x86bae518, 0xb8705a70, 0x76e10735, 0xabb36328, 0xf8b9c61a, ++ 0x41e089be, 0xfdf8063b, 0x976b8298, 0x02cc8d7b, 0x08f797e5, 0x9d4cde74, ++ 0xd35703ff, 0xcbf81b98, 0xd078e1bf, 0x5fdae570, 0x2c73df10, 0x768b54bf, ++ 0xd3e6e4d2, 0xacf7989d, 0xea2d43fd, 0x3c811f17, 0xbd033c41, 0xe405d99f, ++ 0x1925c727, 0xd5f160f0, 0x75e7ea24, 0xe916a043, 0xc0b6fbce, 0xea3f3f10, ++ 0xe48d24b9, 0x05ae8af2, 0x7746d2be, 0x8ad4d8ec, 0x7a4fce04, 0xfef81b27, ++ 0xef821a16, 0xe3bc1e3b, 0x7ee1c6ff, 0x3fcad658, 0xcb59df47, 0xba432331, ++ 0x881d58de, 0xf70f3bd3, 0x878bf401, 0x981d70eb, 0x4bd79686, 0xb4071cde, ++ 0x38f057ab, 0xe2b4bcb4, 0xc4c2bf86, 0x63a0c8fd, 0x03f3f0a6, 0x25806bf8, ++ 0x1d9227c5, 0x7a068fe4, 0x7e9de86e, 0x55b4c456, 0xed689f60, 0x9049f633, ++ 0x0f0e1f1e, 0x5f45366f, 0x833927cf, 0x8323b479, 0x1da24fef, 0xb0def7a9, ++ 0xc8ec6339, 0x9e68fce1, 0x60efd07e, 0x71405abf, 0xdf109392, 0x617a53c7, ++ 0xce997adf, 0x360745ed, 0xe360bca3, 0xac77640c, 0xa1f56af4, 0x7db8d309, ++ 0x87d14132, 0xfd8056e6, 0xd86ecb94, 0xcd27604f, 0xec08fd47, 0x9877b8a4, ++ 0xfd0a7ec6, 0x0593f64e, 0x1dc60ae9, 0x5bb3fb0f, 0x55a67f6f, 0x4648ac2f, ++ 0x7844dafa, 0x11cf00ce, 0xb9d742bf, 0x4bcf82b4, 0x4885eba5, 0x3dbf88d7, ++ 0xfb43ae9c, 0xb55699ad, 0x21b3e714, 0x32c1bdcc, 0xb72b9d65, 0xcf2f0408, ++ 0xd3822496, 0x55c5b679, 0x1e79780d, 0xf00db1e6, 0x15cba2f2, 0x2fed0093, ++ 0xf8315dba, 0x3e542c77, 0x8625b2d0, 0x3b186dda, 0xf209a92f, 0x7f782a4f, ++ 0x05ba67a1, 0x16c0fce1, 0x78ea7f4e, 0x2617f91f, 0x99153d21, 0x7f9e1202, ++ 0x1d3def4c, 0xd1607a87, 0x90927bbe, 0x73cdc30e, 0x9fce54e5, 0x6c7dae56, ++ 0x8e2499c5, 0x638f780f, 0x3cdf2285, 0x8425fb4f, 0x8cb58aff, 0xdee0f7f0, ++ 0x1d20b55f, 0xb18de85f, 0x7f3c3ca1, 0xfc8bc620, 0x66dbe2ff, 0x3b20419f, ++ 0x7c0f1bc4, 0xffa9bced, 0xf737d26e, 0x3f686d19, 0xfdfede7a, 0xcf47a466, ++ 0x7e6a335e, 0xfaef456c, 0x9af7284b, 0x2b3cef7b, 0x645afa62, 0xdae561e9, ++ 0x6abd6827, 0x166df7fe, 0x05e8f919, 0x1589f391, 0xfd223f3d, 0xcbb5c577, ++ 0x7acfd113, 0x147fc0fe, 0xfcf35f23, 0xe462e5cb, 0x97fd9e67, 0xf3dcb18b, ++ 0x3d5698e3, 0x34d2e5bd, 0xe55207ee, 0x5149d665, 0xa45a2fe3, 0x8eac85c8, ++ 0x00c6b34d, 0xcf8e8afc, 0x6abbf3a7, 0xc18e5179, 0x7e8bf585, 0x50f49359, ++ 0x3e8ebb50, 0x85a4e291, 0x96626bc7, 0x6ba5e106, 0x37f5499a, 0x0f3f237e, ++ 0xeabbe296, 0x7d3afc37, 0xd4146706, 0xdca7d0db, 0xefce5e9f, 0x12fe834f, ++ 0xa9f48eda, 0xf1248f8b, 0xeba2d2fb, 0x988509ae, 0xeafba1cf, 0x32396bcc, ++ 0x5a5f4836, 0xe3f067d8, 0xefa82ddf, 0xdf49fb35, 0x534f13ef, 0x1ea3d15e, ++ 0xd8bbf4b8, 0x4fc7412c, 0x06627b93, 0x7f50f1f2, 0x7162fc0d, 0x757eaade, ++ 0x8ffb952a, 0x866d5bd2, 0xc5af3039, 0xc93efc1d, 0xfd4ebf10, 0x8517f24c, ++ 0xbee477fa, 0x4ed82c97, 0xe1b06b1e, 0x14bd557c, 0x0e8f71f7, 0x2a68781f, ++ 0xbe9573a7, 0x1c78fa3a, 0xdaafa3bb, 0x07957182, 0x63dafa14, 0xc02f3033, ++ 0x9ef7a3a5, 0xe85fe81d, 0xcc5f76b8, 0xe3a71804, 0x34f63ce4, 0xb55b01f2, ++ 0x5ddb0725, 0x9059699b, 0xa1378837, 0xca984de3, 0xbea0e6f9, 0x32ff2fa0, ++ 0x4a457995, 0xfa9a8e0e, 0x608390dd, 0xe54d679f, 0xee22f9f6, 0x79f6e13f, ++ 0xf950fca8, 0x3cefdab2, 0xf2879f65, 0xe7a4b3e5, 0x7c4d1d80, 0x9954de79, ++ 0xcef7a5ea, 0xfafb224d, 0xd924fce4, 0x6cffb43a, 0xcc4861d1, 0xaabfda1b, ++ 0xcebc79cf, 0x7bb41623, 0x4fa2469c, 0x87c17ccf, 0xff553971, 0xd204b8f3, ++ 0x4d8b3dcb, 0xcea7ac3e, 0xf73e6fab, 0x9a702ec7, 0xa807efe8, 0x47aaa27a, ++ 0x087728de, 0x95eaae54, 0xe7d8feaa, 0xf9ddfee2, 0x31bcbc85, 0xc2277dca, ++ 0xbbfc23eb, 0x4ac7c804, 0x41efe505, 0x5da08eb9, 0x02bddf75, 0x5858efe3, ++ 0xaa1a7834, 0x9bd67e77, 0x1f9c3f1d, 0x3f0515ea, 0x0ccb3a55, 0x8e550fa1, ++ 0xf1c8a93d, 0x05e39416, 0xd0bfc728, 0xfda1e7e8, 0x986f1c82, 0xb518ed4a, ++ 0xe8a5fc2f, 0x2fd7b3d2, 0x54aefd2a, 0x70efaff7, 0x8337ce15, 0x3b43adf5, ++ 0x757c9c33, 0xb84e7a2b, 0x6e2b27f2, 0x28b79e8e, 0x3d148beb, 0xa11df4bf, ++ 0xa1fa1be7, 0x9f7f4614, 0xb837f556, 0xd6c6d1ff, 0xbfa42abe, 0x77e44cf7, ++ 0xacd7ad0f, 0x644c73e8, 0x9239fd9a, 0x3ed01921, 0xfee72cf2, 0xf904ae83, ++ 0xfcc764e7, 0x9fb0c8c4, 0xa20f6015, 0xd5e8f71e, 0x519b4a04, 0xd174865f, ++ 0x8f14e3ce, 0x3b5cb458, 0xe9f42eff, 0x5955fb62, 0x0377cef4, 0x533f21ab, ++ 0xad826f43, 0x5742841d, 0xa451f772, 0xa30eef2b, 0xfeb823bc, 0x0b7d6a23, ++ 0x4dadc3f7, 0x35ec51f5, 0x68681f44, 0xb5fbd50d, 0xe2b941fa, 0x27a70a37, ++ 0xc5183fec, 0x2331caf9, 0xfa0b79d1, 0x2631269b, 0xe0be72f5, 0x24fdcb59, ++ 0xe2ebbd2d, 0x4acde018, 0xec407ca5, 0xc5143f23, 0xd9eaa0d7, 0xe85217de, ++ 0x1b53b03e, 0xfdb95a4f, 0x432fc497, 0x7b894ae3, 0x34f25f38, 0x5238951b, ++ 0x95f980b1, 0x448e4f60, 0xbf9652fd, 0x79877087, 0x1bf11f31, 0xb2efc6a7, ++ 0x7d2b894d, 0x64b7ec76, 0x17da2e87, 0x55d48e26, 0x4e48e3c7, 0x238fd4e6, ++ 0x26923d1d, 0xa91c757f, 0xdd38e7a5, 0x78aafc47, 0x5aa985d2, 0x9168e3bf, ++ 0xf74777fb, 0x57f4360a, 0xebe5ee8d, 0x9a21b29e, 0xdfdaebf4, 0x7e424d2c, ++ 0x85d3eea0, 0x17be1cb9, 0x8552bc3e, 0x237f8aed, 0x5d60a2da, 0xf35c3ffb, ++ 0x979e348b, 0x5bb6322d, 0xccf68313, 0x8eacdf85, 0x87eef841, 0xc7e7f714, ++ 0x1dffe81f, 0xfe8355b0, 0xf234e36a, 0x6afe2b3b, 0xec61e411, 0xb4275fa0, ++ 0x5da526dd, 0xe42b9817, 0xe3c7dcd7, 0xeea95dfe, 0xd5ffca3a, 0xf483b618, ++ 0xa3f92744, 0x8d78047f, 0xb0f1a37e, 0xff4b8c58, 0x60759a30, 0xd92ba91c, ++ 0xd1d12efd, 0xa464195f, 0xf14f6823, 0x321bef27, 0x7d7447c9, 0xa2679c61, ++ 0xf7c17304, 0x8cf16870, 0x63eca1dd, 0x18b3d82a, 0xccd98267, 0x78f438c7, ++ 0x3133de25, 0xffd8899a, 0x46f726b3, 0xd9e9a77c, 0x57bd2283, 0x124744cc, ++ 0x8d0b7bde, 0x1e4e093b, 0x4fe3572f, 0x5c3cdc6a, 0x71c049fc, 0xe3fc7226, ++ 0x029db5e7, 0x38d5d3c6, 0x45d7bb13, 0x92f6afc1, 0xb5573a56, 0xdf08831e, ++ 0x76697c6e, 0x67fc4e85, 0xe2530561, 0xe378dad2, 0x84dddcc6, 0xce375fa7, ++ 0xb7ea65b8, 0xcb996f3d, 0x177990d7, 0x42967c26, 0xff97d776, 0x6ce48e27, ++ 0x879265ef, 0xd6660317, 0x7ec7fe47, 0x35ef77ee, 0x22e19f91, 0x41c96fd8, ++ 0x056f7672, 0xde9df7ef, 0x7bff84e9, 0xb0626afa, 0x7df2bf7e, 0xf7f9c9c3, ++ 0xedefbea0, 0x4db9f913, 0x3db1edc6, 0xea11627d, 0xbee2df2d, 0x6755323c, ++ 0x2e68967d, 0x28e9429f, 0x4ca3a153, 0x805803fc, 0xe43fd337, 0x0d679876, ++ 0x14d8af8f, 0xe569e0be, 0x19a3f571, 0x4fea8229, 0x7f17a91f, 0xb92017d9, ++ 0x7f08f0d1, 0xe366fa4f, 0xeaa62f2f, 0xf517e3c7, 0xbf8fd69c, 0xfe25aacc, ++ 0x1d9fce19, 0xc1fec7ea, 0x4dff8534, 0x366c7ee0, 0x4eeb46cd, 0x355c9d6c, ++ 0xffae0d92, 0xa987dc5b, 0xfe36b795, 0xb5bce8da, 0xfe81dffd, 0xffd85bdb, ++ 0x76b7e583, 0x716eabfe, 0x62dc2fff, 0xc5bd9cf8, 0xc5b89ffd, 0x27a9d9f0, ++ 0x9eabfe1f, 0xff8d080f, 0x08179e87, 0xfe60073d, 0x2c5e43c9, 0x173c2f5b, ++ 0x896a43f0, 0x002f5bdb, 0xb613141f, 0xd9dcf9d3, 0xb61e3ca5, 0xdbe2c6a1, ++ 0x1b9e0c2a, 0xb735e150, 0xb611db8a, 0x3c5e4bbc, 0xece99bd7, 0x7f4249ab, ++ 0x3b232959, 0x8f1462f8, 0x96d1318b, 0x41ce973a, 0x81e752db, 0xa515d25e, ++ 0x0ffd671f, 0x861762a7, 0x57cf2391, 0xbf229555, 0x77b985b3, 0x87e282f3, ++ 0xfbf0f5b4, 0x53944cdb, 0x72b8d1e7, 0xf143ea2a, 0x38f7f987, 0xa56e733f, ++ 0xf359c979, 0xb3941ec8, 0x2a2f7e70, 0xbac4dff1, 0x97e85971, 0x10bd044e, ++ 0x602f82e3, 0x59ec907c, 0xc753d51b, 0xaf92af7b, 0x131345ff, 0xbdeb9e30, ++ 0x62739f9d, 0x71352fae, 0xfe4df7bd, 0xc5024d33, 0xc257e6f5, 0xf06a7efc, ++ 0x52cb6de7, 0x9be01890, 0xf146c7b7, 0xfe959fc6, 0x2f3f2e43, 0x8f7ce3cb, ++ 0x439578d9, 0x3cc33768, 0x40503b1e, 0x9de8bbf8, 0x18b5ffd2, 0x22b18fed, ++ 0x5d8879c1, 0x3e0bf8a9, 0xaa1dfc50, 0x6f8d40bf, 0x93f15afd, 0x17fe847c, ++ 0x1fd1fb48, 0xcaaae902, 0xa27ef23f, 0xd4ac7f0e, 0x0a2f2fe1, 0xfde43fdc, ++ 0x150ff729, 0xe0ec8e48, 0x597f94f3, 0xc9b1f7c9, 0xaa17e3cf, 0x951fe7bf, ++ 0x693c14f5, 0xa2fbe3f4, 0x24139d05, 0x9d05f394, 0x4e98d119, 0x290cfa74, ++ 0x4b85ef00, 0xfba830df, 0x5d4787a7, 0x1c373aca, 0xef7c500b, 0xff712147, ++ 0x79f92af7, 0x3e2a9a86, 0x1be0f78f, 0x88e58fa6, 0xe3d628ed, 0xbd466c2b, ++ 0xd80352b8, 0xa6cf38c5, 0x156f3e2e, 0x797e0dde, 0xfa738e3a, 0xd313a048, ++ 0xd359e5fc, 0x7cdeefc9, 0x37f513a9, 0x47cbb5cf, 0x265fc92b, 0x3c4f68c9, ++ 0xbbf5afd0, 0xfdc5583d, 0x05423fef, 0xa776e11c, 0xc171f648, 0x4fe1229d, ++ 0xd9144362, 0x662689af, 0x2e7e62b4, 0x67f28bd7, 0x798e988d, 0xf4813f36, ++ 0x7263fcc1, 0x579b9e02, 0x778960fd, 0x384649ae, 0x559c557d, 0x4635a7f5, ++ 0x7ee17739, 0xeb38dd7e, 0xd24ff7ca, 0x5d755379, 0x78d45c2a, 0xab38b869, ++ 0x33c1ee7a, 0x9ce68aeb, 0xd40c4786, 0xe0b1ffa2, 0x394969c0, 0x67b3697f, ++ 0x0b61c60d, 0xf8a25df6, 0xf56f1aab, 0xbd225eb4, 0xd849da1a, 0x8f1b4f7e, ++ 0x7985eebf, 0xeb03da60, 0x3df19a76, 0xbda53b11, 0xfefc6eb0, 0xa52e5b76, ++ 0xa50736fe, 0x5095b4ef, 0x226e7f8a, 0xb6e31135, 0xdb6e2897, 0xfb8da957, ++ 0x05bd71a9, 0xc817eba2, 0x7ee282af, 0xfb8d0f94, 0xbfb9a319, 0x44cc73c6, ++ 0xde7aecef, 0xaeff10b7, 0x8d1a6dea, 0xc7e7c1f6, 0xde71a3dd, 0x0b77182d, ++ 0x4e0b8bc2, 0xda025447, 0x14472ec1, 0x0e0adbc6, 0x3cf0959e, 0x27d88b4c, ++ 0x660c3fa1, 0x1647869e, 0xf12e7b3d, 0x55bdbf73, 0xafdf0851, 0x7cf58f8c, ++ 0xff63e337, 0xc340d61f, 0x00800092, 0x00000000, 0x00088b1f, 0x00000000, ++ 0x17adff00, 0x67534c5d, 0xdb977cf4, 0x179fcb72, 0x71914414, 0x505112c1, ++ 0x1a744c2b, 0xac745ee5, 0x9514b653, 0x351804a5, 0xd09b1973, 0x96166732, ++ 0xe34eb43d, 0x0c60f740, 0x493f660f, 0x64b8d45d, 0x5992750f, 0x8b2aeab7, ++ 0xf11a2586, 0xb0f88e61, 0x06646180, 0x37187137, 0xce761737, 0x2f6d6f77, ++ 0x920f64d6, 0x9f9ee734, 0xfcef9cef, 0xe34f4c7f, 0x84c00d5f, 0x4ac6525f, ++ 0x27177e01, 0x800ae4b3, 0x56d3e19d, 0xa9c3e095, 0xbf842e65, 0x5aa7fb9d, ++ 0x7df000c9, 0x880d5537, 0xaa9dbefb, 0x4cefbe26, 0xe910577a, 0x189e86d3, ++ 0x002969f4, 0x334e012b, 0x5f908770, 0xa3d412e9, 0xdb550704, 0xb97115eb, ++ 0xa4e0975e, 0x92f6bdf3, 0xb9f7a26c, 0x2477b24a, 0x14e7dbe8, 0xe7a4419d, ++ 0x25b768bc, 0x0b3407d2, 0x19d22e40, 0xec4942b8, 0xb702a997, 0x9be4f3bf, ++ 0xf01263bd, 0x75fc69bf, 0xe136de86, 0xbd7bf0be, 0x7c716563, 0xc3cc7d27, ++ 0x422646df, 0xce874035, 0x53d11282, 0xcebea2a6, 0x942b11fc, 0xead26510, ++ 0xbaf18a5a, 0xe5b0f522, 0xbece1700, 0xc1523451, 0x03c82545, 0xf5ce3268, ++ 0x6514773a, 0x0c0801ce, 0xd32942a7, 0xddf22269, 0x5470a1f4, 0x334ed111, ++ 0x9b95e17d, 0x4a1a3ff2, 0x63d08659, 0xdc248c09, 0xa829d9ab, 0xf76e2cb6, ++ 0x924c8699, 0x62fce317, 0xccf93a52, 0xa984a596, 0xc13e4205, 0x26ac0140, ++ 0x57b45d20, 0x80ddedc7, 0x94768fe0, 0xd10a726f, 0x8ee3b454, 0xf50146a4, ++ 0xf0453a56, 0xdbb08b3f, 0xc4662c12, 0x5f394717, 0xf89eab79, 0x02cae4fb, ++ 0xbe7e3f40, 0x1767956c, 0x8d8dfbf3, 0xe1d1c424, 0x8253d63c, 0xcc1d1de7, ++ 0xb7356e41, 0x97f8f99b, 0x19b67e49, 0x9f9bc971, 0x02cc39f5, 0x785f0d68, ++ 0xac0f00be, 0x1b3d4380, 0xbb0afcf1, 0x6f114720, 0x6f9f32ed, 0x316f3b73, ++ 0x183a27ba, 0x75b738c2, 0x6754f99b, 0x0bde90a7, 0x87ac4ce0, 0xda0ea336, ++ 0x67e1c654, 0x98c381eb, 0x99b9d89e, 0xc86fd3f5, 0x8317d4cf, 0x4b9f88c7, ++ 0x6bd959f5, 0x0bd6fca7, 0x7883ed80, 0xd04f64ad, 0xb9154bb7, 0x00b2c39e, ++ 0x17db9401, 0x619c7ad9, 0x7c3df6fc, 0xb9446a41, 0x54ad723b, 0x7dc7119a, ++ 0x309eb197, 0x1e17552e, 0xfbbc51d4, 0x686c0c22, 0xf78f97ca, 0xf3aab945, ++ 0x965b20da, 0xbfdd4f78, 0x50f9cc3e, 0x2381d506, 0x40bf741b, 0xce0678c2, ++ 0xb471e0b1, 0x6f7f5957, 0x70711d20, 0x154a3b65, 0x9bdf63b2, 0x5eafb881, ++ 0x7708c95c, 0xb7c201e1, 0x9f84a0b1, 0x6fb6af5b, 0xd553b402, 0xe51ae2b8, ++ 0xe2c5b1a5, 0xebf1e1b0, 0x693bdcb3, 0xeabd6c4e, 0x47f9d3ae, 0x7e23483f, ++ 0x14d87319, 0x896b3ba2, 0xa8cbf9be, 0x12fcf548, 0xde216945, 0x4898f2ed, ++ 0xf366d37d, 0xaa3ea61c, 0xe823406a, 0x5b16b6df, 0x8c6bfc90, 0x83205834, ++ 0x7d408fb7, 0xdb918ef7, 0x67ef0bef, 0x2a7d208d, 0xfc8b3552, 0xb4996d9a, ++ 0xa156103a, 0x083979ee, 0x02b5ddcf, 0x9c4f83f6, 0xd728cab4, 0x2ec4c7ef, ++ 0x2fdaf802, 0xcbf61871, 0x7c02a6a0, 0x30e7cfe3, 0xfd3857e2, 0xc38cbfbc, ++ 0xe1c1dfa8, 0x87357f80, 0xe3ccaafd, 0x57723cb9, 0x34e4fba0, 0xf364ae08, ++ 0x1f51976d, 0x91697cb1, 0xcf7445ed, 0x453cd7fb, 0x18f91272, 0xc2058b44, ++ 0x193fbd6a, 0xbce7cce6, 0xbc764757, 0xce9fb230, 0x586f9829, 0x11872005, ++ 0xfd727dce, 0xbc08d68d, 0xf005b2fe, 0x62ffe324, 0x952627d4, 0xa49773c7, ++ 0x2585fff7, 0x4a78f37f, 0x5aeae561, 0x30779bcc, 0x7e915205, 0xfb9f56a0, ++ 0x630cf533, 0x76e3013c, 0x7049e303, 0x0d6ddf26, 0xdc3e5294, 0xe7248f74, ++ 0xc4fa8d47, 0x32b8b00a, 0x9c329cf5, 0x1cc62d7f, 0xcc40c568, 0x84b63cc2, ++ 0xfb0d3459, 0xe1b235bb, 0x8bb04896, 0xfcf34dc1, 0x79b19b80, 0xf8e4f297, ++ 0x25e85ffe, 0xbc71a57d, 0x134a83c9, 0x3a7b6de7, 0xb847f24d, 0x59c7a694, ++ 0xc7b0eab2, 0xf5b5efa6, 0x31075e9a, 0x71e9a358, 0x82cd483f, 0x2cf07df5, ++ 0xfec1ee0b, 0x1a5c56f3, 0x5735f9a6, 0xe1c6e805, 0x88cfcde3, 0x0f3cd0a6, ++ 0x9a3f6e5b, 0x731fd8e3, 0x725a1915, 0x30638c68, 0x8cf36f31, 0xc601203b, ++ 0x73458e51, 0x9472e984, 0x80f8305b, 0x14d41df4, 0xd5ef2f6e, 0xa1740310, ++ 0x687b0210, 0x82b45cbe, 0x77ed0a76, 0x43d833f4, 0x006c1dfd, 0x1fe90aa5, ++ 0x05ffd8df, 0x4cfdbdd2, 0x19d475a6, 0x7cf7c6ba, 0xfbc438a7, 0xb0991bc7, ++ 0x8d0c7af2, 0x5330f4ea, 0xfaf24983, 0x37dfb1be, 0x46e7c0aa, 0x6094eee7, ++ 0xebadda2a, 0xd7dafbd7, 0x7e0a82c5, 0x577c2a5e, 0x2cf5bc24, 0xc734b983, ++ 0x74dca194, 0x40b6efe2, 0x55fb98b0, 0x27ec25af, 0x77e429fc, 0xf6c67f6c, ++ 0x2f26178f, 0xb6bd5015, 0x07ed0733, 0xcd373fdc, 0x922f05fb, 0x872fdf17, ++ 0xc17ee1e6, 0x1e1cdcbd, 0xc21cd0b5, 0x6f92647d, 0xd16eeb53, 0x633dc51c, ++ 0x7fd82fa6, 0xfb82f297, 0xa45f44c5, 0xc719ce65, 0x543943b8, 0x5b3ce34c, ++ 0xb8f32359, 0x798c3dbb, 0xb96a682a, 0x384fc83a, 0xb79a64cf, 0x4eb5e333, ++ 0x7360fbd3, 0xe6374180, 0xaf5584f7, 0x586b138f, 0x9bf28030, 0x9fbca511, ++ 0xc03dbf38, 0x9513cfd0, 0x3c5021cc, 0xb1e30848, 0x62cf88c9, 0xc4b8c008, ++ 0xd37d0a9f, 0x7197cf98, 0x9eb0d8bd, 0x00f51b36, 0x1a76e410, 0xe945a48e, ++ 0x12d0711d, 0x77f077ca, 0x77df8049, 0x3085f282, 0x92ba152d, 0x4d62ebf5, ++ 0x3cf9a09b, 0x4fdff4f1, 0xf1f72d2e, 0x3487d3f7, 0x2bced113, 0x2fc9131a, ++ 0xf5396f8c, 0xebc2edf7, 0x36880359, 0x3a26ae8a, 0x2e8d61d7, 0x146efaa3, ++ 0xf18f1c3d, 0xfda5ee91, 0x26ef8b82, 0x8c0091f5, 0x650387cf, 0x2f28595f, ++ 0xdd8f44cd, 0xc72e38b7, 0xf1c794f1, 0xb69e1571, 0x926a47df, 0xa29f1bbc, ++ 0xef648cfe, 0x5fa8a7d2, 0xdfe892d2, 0x492ff34b, 0xe6315cfd, 0x7902c020, ++ 0xce313d3c, 0xcfec1a98, 0x3af0325d, 0xf5ec68be, 0x44fca61e, 0x83f0287b, ++ 0xf12b8e05, 0xa993dab9, 0x98d4ffeb, 0xc67831a7, 0x5d163d80, 0x01fda66e, ++ 0x5453bec3, 0x293aa13f, 0x9280293f, 0x50d2f7e0, 0x7e09281a, 0x98e70f2f, ++ 0xf9d115f0, 0xc1aaf926, 0xe57f1312, 0x7f1312d0, 0x09a570d5, 0x8d646e7f, ++ 0xafed7e49, 0xdd7c26b5, 0x7c9326e4, 0x4c5b5fcd, 0x357fac78, 0x73c4dcac, ++ 0x4cd7a41b, 0x66ed0572, 0xccbb0abf, 0x9b75157e, 0x2de98afd, 0x5bfd980e, ++ 0x2ff663d8, 0x3c8ffb27, 0xffa1de85, 0xfb4599fe, 0xc53237a0, 0x326774f3, ++ 0x8e688615, 0x7efa2388, 0x5ef85888, 0x2fff83b8, 0x21e426e6, 0x9db8555f, ++ 0x1b42c881, 0xb4ec3b9d, 0x56dde8db, 0xf28a7382, 0xdbb01ff6, 0x0e70044a, ++ 0x00000e70 + }; + + static const u32 csem_int_table_data_e1h[] = { +- 0x00088b1f, 0x00000000, 0xe24bff00, 0x51f86062, 0x38cfc10f, 0x90981819, +- 0x770143f8, 0x01684331, 0x21060616, 0x62636620, 0x22676060, 0x072bbf5e, +- 0x9d877d82, 0x1038e181, 0x781f67df, 0x5e240d7f, 0xbb3f4dcd, 0x2ed1d37e, +- 0x7e27f062, 0x02af8606, 0x058b0c0c, 0x210b7c21, 0xfccff954, 0x18a47608, +- 0x02a57665, 0x150003f5, 0x8051b77b, 0x008051b7 ++ 0x00088b1f, 0x00000000, 0xe4b3ff00, 0x51f86066, 0xb97bc10f, 0x726e1818, ++ 0x0143f821, 0xd08667cf, 0x0c0c2c6a, 0xc6cc401a, 0xcec0c0c4, 0x717ebc44, ++ 0x1d7b044e, 0x4cc30307, 0x31c8de20, 0x481afef0, 0x7e87957c, 0x42f2a976, ++ 0x81c16968, 0x970837f7, 0xd430310b, 0x04303309, 0x4ff84088, 0x2be55045, ++ 0x366c1084, 0x12ecca49, 0x0007ea02, 0x0fb3beda, 0x00000380 + }; + + static const u32 csem_pram_data_e1h[] = { +- 0x00088b1f, 0x00000000, 0x7dddff00, 0x45547c79, 0xbedd70b6, 0x97a7774b, +- 0x42c84274, 0x4010dc20, 0x804d8854, 0x024de3b0, 0x10602a31, 0x66b71c11, +- 0x04484b0f, 0xd3ce7cde, 0x0831baf9, 0x544e38e8, 0x387c0666, 0xa8d041af, +- 0x1a0c1a51, 0x166bc3b0, 0x26665419, 0xb8c38e3a, 0x6c8a89bc, 0xfd011242, +- 0x5f283798, 0x3b75539d, 0x4dba6f7d, 0xe3fbe65c, 0x45a7efcb, 0xeab7badd, +- 0x9cead9d4, 0x25aaa753, 0xd7a92059, 0xfe197212, 0x48a6f968, 0x51d11908, +- 0x1fb715b6, 0x04846927, 0x6dd5915e, 0x7fc22102, 0x0ed722b9, 0x16c8e427, +- 0xf5a56821, 0x21075ec8, 0xd3767eb4, 0x9735a0b4, 0x0e057d90, 0xbb3fde0d, +- 0x25eb08b5, 0x96e2febb, 0x2ee57b68, 0x65ba8251, 0x8b7729ef, 0x6b2a9093, +- 0xe963a3f3, 0x225df6f3, 0x228742d9, 0x490b1281, 0x8db8e427, 0xac8bbfb0, +- 0xaacec0be, 0xddf79b95, 0x3456fd05, 0xf69d895a, 0xe17bb953, 0xbeb4b1d4, +- 0xe04cb0f0, 0xab6dca95, 0xbeb45e94, 0xa0842828, 0x0fdec0fe, 0x62b69c70, +- 0x4c1a1152, 0x8dbf69c8, 0xbad057a8, 0x067d39bb, 0xb838be7d, 0x5fde14a3, +- 0x2d782f5c, 0x9bc5fdf4, 0xfe819df6, 0xfdc83717, 0x92ffda45, 0x0751073a, +- 0x132fb1b1, 0xa9fcc798, 0x1be56f00, 0x7ad2b132, 0x0a15a5c5, 0xb5491c01, +- 0xc60bb94a, 0x5d514c7f, 0x1c61ce30, 0xe567c747, 0xfa1c7473, 0x0497b2dd, +- 0x996d4c2f, 0x9e00f885, 0x59f6ddd6, 0x5e613b4f, 0xf08194ab, 0x0ab5eefd, +- 0x3830b7bc, 0x0abb15fb, 0x4a566df0, 0x9b4dce01, 0x3b830595, 0xf7525bfa, +- 0xe3ae0196, 0x7c32f21b, 0xf2e6ed31, 0xd5109fb4, 0x4c5f51da, 0x02721688, +- 0xda6541dc, 0x17e78e90, 0xf7a41484, 0xa8913a92, 0x29fe8eb6, 0x49e90861, +- 0xfa17ffff, 0x2683e04f, 0x6e5b7057, 0x7b96bd07, 0x0ed5bfe8, 0x70f39d7a, +- 0x85ed49fa, 0xe5ebfdb1, 0x0a0740a3, 0x83dfad4f, 0x4cfee3e5, 0x55fbd72c, +- 0xfc6fdbc4, 0xe0dcb083, 0x27f3e2f7, 0xdcb0a3fd, 0xfcb0d7e4, 0xcb0cbf9d, +- 0xdf1cbfa0, 0x859fe2db, 0x0fbf56e5, 0xafe33f9f, 0x5fceb2c0, 0xf79fcf8d, +- 0xbd658bdf, 0x5fcf803f, 0x32c3aff2, 0x72c5afe4, 0x96037fa7, 0xbe20fe0d, +- 0x0ebf8af7, 0x087f46cb, 0x37f1ef9f, 0x47f61962, 0xf40bdcb0, 0xdfc465a5, +- 0xff7ee58c, 0xfa0f2c51, 0x43bbf05b, 0x3e5893fe, 0x1eeef1c2, 0x8a248a47, +- 0x3c46b737, 0xea485c54, 0xa648ad64, 0x5672d4f5, 0x5023bf4f, 0xba7ad0a4, +- 0x1e29d68f, 0x148d2d7b, 0x57bd6959, 0xb9cf6b35, 0x68db149f, 0xdac0273d, +- 0x15a23dfb, 0x5fbd69db, 0xb81f6b2d, 0x449c5029, 0xac8303eb, 0x48faaafd, +- 0xafd683b1, 0xfcf6b10a, 0xd2712930, 0xd5847e7a, 0x25688e0b, 0x682f5a2e, +- 0x0fc2f566, 0x5a6e2503, 0xdf616c2f, 0x2913398f, 0x31f5a649, 0xc27daced, +- 0x43d13225, 0x808813eb, 0xd16762f5, 0x2f5a14c4, 0x697ab0f6, 0x1a92d9ef, +- 0xcaf6ff87, 0xe509732d, 0x4dc0ba85, 0xeb45949a, 0xe20acb4a, 0xcc0cf8a5, +- 0x26447ac2, 0x48fda0f3, 0x8d26b660, 0xac8575a6, 0x0efff684, 0xfdf6c62c, +- 0xeded8ab2, 0xbed81581, 0xddb1515f, 0xac7eeab2, 0x6c35941f, 0x20f55b4f, +- 0xd1507fbe, 0xaae07db0, 0x487eb147, 0xa8fb61f6, 0xf7c5bf55, 0x6c3e290f, +- 0x50757c7f, 0xffeb489b, 0x00b6f821, 0xbe08d75f, 0xfc07920a, 0xa72cca1a, +- 0x2046bafc, 0x1e3e40b3, 0xf2a6a606, 0xd14b26b0, 0xfdedbf40, 0x5169f0ba, +- 0x069dbce0, 0x3ccf05f5, 0xbcfd8b9c, 0xb4c8fd80, 0x7eebb11f, 0xca337c26, +- 0x6f84cfd0, 0x1a7ef42a, 0x7b1abde0, 0xfbd9faf7, 0x3c2318cd, 0xfbd62cdf, +- 0x5c7ec269, 0x84d79bdd, 0xf08ce3cb, 0xf7aa5e5c, 0x49fb0873, 0x113c1ee9, +- 0x9fa1a479, 0xef50bc88, 0x4fd84fe7, 0xa3c1eecf, 0xfd0da329, 0xbd22ca68, +- 0x4fd8a39f, 0x89faf756, 0xf08d6328, 0x7ef44b28, 0xfa7ec63e, 0x9a5e6f74, +- 0x1e11bc75, 0xcfdea56b, 0x6e7ba469, 0xefd9faf7, 0xbf67e232, 0xf39f8a2b, +- 0xee80cf08, 0x6dd8abcd, 0x3bb14fc4, 0xd84b9f8a, 0xebdd95cf, 0x88dbbf67, +- 0x28eefd9f, 0xe601647e, 0xf37ba435, 0xe2364e2a, 0x8a3938a7, 0xf000b71f, +- 0x3c1eed0c, 0xf11a7b07, 0x1467b073, 0xcf08193f, 0x33c1ee88, 0x9f88dd31, +- 0xfc51e989, 0xe8cf08a8, 0x3073f5ee, 0x839f88dd, 0x5cfc51e9, 0xef8cfd89, +- 0x6626bcde, 0x3133f118, 0x029f8a23, 0x57c8a7ec, 0xda10f087, 0x3f712b8f, +- 0xf118fa87, 0x144fa873, 0x9fb1633f, 0xbc9fb449, 0xcd29fbae, 0x34a7e231, +- 0x899f8a27, 0xbbebe788, 0x1ca1cfd7, 0xe50e7e23, 0x0533f144, 0xbdd299fb, +- 0x35f69579, 0x2fb4a7e2, 0xd2b5cfc3, 0xe8675c50, 0xe915e9da, 0x2ef5d727, +- 0xbefa04d2, 0xd17561e8, 0xf76025e3, 0x433dba88, 0xbe91359a, 0x294facef, +- 0xdac49878, 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+- 0x2d547080, 0xf79e76e9, 0xdc7ada42, 0x060306df, 0xb941fe1a, 0xb4e42c3c, +- 0xed87e041, 0x7fafdf1f, 0xbdd00a4e, 0xc74fc3d3, 0x5e035ff3, 0xdf3e3475, +- 0x952df9d8, 0xf112f5ce, 0xb0a6dd56, 0xc846b7fc, 0x355f1127, 0x5569f843, +- 0xe225be29, 0xdd27c1ab, 0xb79e7f84, 0x37f96fff, 0xa6235cf4, 0xec2255a9, +- 0x1ff6a89c, 0xddaeb724, 0xfb435f7c, 0x4bfbfb11, 0xd0de75f7, 0xcc9864f7, +- 0xf334bdf4, 0xf8a5eb16, 0xe543bb7c, 0xe6683376, 0x9e06cae7, 0x2c5fdf12, +- 0xbb25f5f2, 0x357ade79, 0xe74ecd74, 0x833dfdc4, 0x69ad6076, 0xa247c529, +- 0xa5f8c7c7, 0x5d79324f, 0xa3f73dbd, 0xbf3e501f, 0x637143a4, 0x637507a6, +- 0xf1c52f15, 0xe7afb1ba, 0x2bad8f8c, 0x1d25f8c5, 0xe8db348f, 0x9297e23c, +- 0x3fb2cc9b, 0x894777fc, 0xf724dbd6, 0x78ff7c04, 0xe66fe0cf, 0x53725e91, +- 0xfe7cd167, 0xda4b3bee, 0xfcfe3e91, 0xfd6c770c, 0xf7c5dc79, 0xc2ac64b7, +- 0xa8ef6ae2, 0x415a7fd4, 0x3d9e85e7, 0x5f7bbecc, 0xfb25597d, 0x20976fef, +- 0x9e3a1717, 0x1d25ec7b, 0xf07bdde5, 0xfac94ab4, 0x6ad3cec2, 0x85f26bf4, +- 0x458e58ab, 0xab6a79d8, 0xb78f754a, 0x946af7eb, 0x3e17a7f2, 0x3554e764, +- 0x3e53e794, 0xd01c9cf6, 0xbac79ff0, 0x4f09515f, 0x8c126d0d, 0x57ed8fc8, +- 0x41f93f58, 0xe36e3fa2, 0x69c0d4fe, 0x81a5c095, 0x55b70353, 0xd86cffc2, +- 0x86971c91, 0x9e08da9f, 0xbe70a3ed, 0xabd6da47, 0xd23d0794, 0x137e3f1a, +- 0x68d399d5, 0xa6e5c73c, 0x9bfdf1dd, 0x33a8f087, 0xefe89d3f, 0x1e04b24a, +- 0xf098a18b, 0x1aa91838, 0x7fdc4667, 0x1c66ba7e, 0x7947b924, 0x2377c453, +- 0xbe4cdebe, 0x2a6ba17d, 0x18ff45c5, 0xfe17d585, 0xc6a1ff31, 0x166665e2, +- 0xf0e2cbc7, 0x569e981f, 0xa22c8f84, 0xaf8256f5, 0x32bce48e, 0x7ca0ea9c, +- 0xdb944579, 0x25b0b2f1, 0x3f889010, 0x2b878b13, 0x708db821, 0xc2d87fd0, +- 0x955f29cf, 0xc204de58, 0x72126dbf, 0xbce424df, 0xd1b1eb09, 0xa883ddf4, +- 0xdd441bc7, 0x9ed279bd, 0x340254e3, 0x93bafe88, 0xe724ecc7, 0xcffdc065, +- 0x3ff720b2, 0x788cfe86, 0x18f76892, 0xfd241ea9, 0x402d86d7, 0x172c33df, +- 0x1b7967fe, 0x46e91ffa, 0x323fd03f, 0xef47e195, 0xc6277ce2, 0xf8ce86cf, +- 0x78b20bf1, 0xf2283a3e, 0x712caae0, 0xb6f4203e, 0x4b520062, 0x9a65be71, +- 0xb7b00eec, 0xfeb4cc7a, 0x4788a989, 0x5684ff9c, 0xa24be198, 0x8dfda34f, +- 0x7a0defc8, 0xe18b9d15, 0x35a3a0f8, 0x7f7eb62d, 0xebd78b2b, 0x9d647335, +- 0xef5310f4, 0x4fcb2aac, 0x377cef5a, 0x31bfc70b, 0xd3d3c366, 0xcf1deb63, +- 0xe3c2229e, 0xbc7f73f7, 0xf157be82, 0xd2ff71b7, 0x66f38157, 0x2c0efe50, +- 0x59b7f61f, 0xf8975402, 0x37544f11, 0x90bc212c, 0x3ba586bd, 0x2f582f09, +- 0xaff3493c, 0xdc3b2ba6, 0xc610eaff, 0xf57e9c69, 0xfc303fa2, 0xf7cf1c9d, +- 0x911b728d, 0xea307eac, 0x782f8686, 0x6f3c6a7e, 0xfd594730, 0x189610d0, +- 0x5e8f3b7e, 0x7e47cbcf, 0x98ffbbfb, 0x50db1eb7, 0x9db38f16, 0xf48bc195, +- 0xede7c91d, 0xe879a4d6, 0xb6971f90, 0x50697b31, 0x3f2c39a2, 0xe0f98439, +- 0xde37ac6c, 0x1bd594fe, 0x0f6d479d, 0xcab43cb1, 0x35f1ce37, 0x66826a7a, +- 0xc336cf96, 0x9e52d636, 0x6dff9b13, 0x52eff072, 0x48388a36, 0xeb8813f4, +- 0xf6f6388d, 0x83fd1bb2, 0x05ea6fe1, 0xbe8337ae, 0xa3749e7d, 0x7617a89f, +- 0x67ba5b53, 0x8968a53b, 0xb0bd5079, 0x59fccc27, 0x83cc4bdc, 0x6bc04ade, +- 0x2c29dbd3, 0x293fedcf, 0x184ce83b, 0x51f3fbe5, 0x7e61ef94, 0x1ce4905f, +- 0xcf8153f4, 0xd9ff715e, 0xf9332154, 0xd6f0e699, 0x8e509bc8, 0xa7fd370c, +- 0x275402d3, 0xa57e1c94, 0xbb507080, 0xdac5c70f, 0xc7d1ea1f, 0xf00a0fbe, +- 0x2a60a573, 0xfa31d3bb, 0x657e1ff7, 0xe9ade132, 0xb88b2fed, 0xa917ae7e, +- 0xcfe73759, 0xd7892568, 0xd78926bf, 0xa8e65dbf, 0xff2eea9d, 0x881bd921, +- 0xefa1abd1, 0xc08e040f, 0x8bfcebcc, 0x9ba31a59, 0xa61f1cc2, 0xfae2de6e, +- 0x8f39f96b, 0xa1bfd6c2, 0xf37112bf, 0x880ef135, 0x5f80c42f, 0xf3f86019, +- 0x7e31369f, 0x7307a7fc, 0x4ebee362, 0xff208ef3, 0xcc0754d7, 0xf902a49f, +- 0x3a67f45d, 0xdfcbcbd5, 0xea7cb1b3, 0x15aec178, 0xc8157fcc, 0xb1ebfe40, +- 0xc6266bb7, 0x598d8bc6, 0x254c3f32, 0x1652e439, 0x5f5f0cf3, 0xd619a1c8, +- 0x8e027388, 0xb9338fe7, 0xeafac15f, 0x89cf64cf, 0xe6add5f5, 0x16dd4dc5, +- 0xff6473a0, 0xcefb0b05, 0x4deef3e4, 0x2f877eac, 0xdfc9137c, 0x8d37cf80, +- 0x6f0ec7da, 0x3fcf489a, 0x1a79bc3f, 0x9a94f73b, 0x4e99e2e3, 0xbe52e5fc, +- 0xc3473674, 0xb3eefafe, 0xfab8bbec, 0x4ff1856e, 0xcb3c6c74, 0xefe7e6c8, +- 0xec6c47fd, 0x0282437c, 0x1f18038e, 0xe75d6f37, 0xa8bf2ceb, 0x589ec90b, +- 0x8def183c, 0xb171e6cb, 0x20e05b30, 0x9e987928, 0x175b783b, 0x53f1997a, +- 0x1e9904ab, 0xde14da9b, 0xcc5bcedf, 0x3a1f193b, 0xbfe274b8, 0xf9bfce83, +- 0xe73b08bd, 0x3ecc91c0, 0x07152706, 0x6bfd2276, 0x1d72847a, 0x3f80980c, +- 0xe4fbb0b7, 0x19851396, 0x13c1fb84, 0x8b25672f, 0x3dd26f1b, 0x54e5420a, +- 0x1243af3e, 0xf3652ffb, 0xe75387f3, 0xb53b3fb9, 0x993137c0, 0x92a1d35f, +- 0x9092e9d7, 0x34b2a777, 0x45dc7dd9, 0x31bedf31, 0x4fda29fa, 0xdd8d876f, +- 0xf93af5c7, 0x03c2ea79, 0x1499cd27, 0x99a53b7f, 0x276a4714, 0xbe88bbbd, +- 0x9cba4003, 0xe46d5afc, 0xac77bb10, 0xec58eb6f, 0x4747c249, 0x32dfc736, +- 0xe67df935, 0x3bff44b7, 0x7516cee0, 0xae132ed4, 0xc50acef7, 0x1de593b1, +- 0xe891b49e, 0x7e12ef87, 0x0a95eef8, 0x01de53cb, 0x16f7e14d, 0x95617efc, +- 0x0977b3f0, 0x22aabcff, 0x57be3fb9, 0x39fab3cc, 0x17ee9278, 0xc7e27b56, +- 0xbdf22bdd, 0xf361e035, 0xa134bddf, 0xf77de45f, 0xc1f2137a, 0x8b87e16c, +- 0x70fc88a0, 0xe903e310, 0xc6d8b1bd, 0x29f2ece2, 0x09e69213, 0xd2ffd1c7, +- 0xc42703f7, 0xfe860477, 0x65df8a9b, 0x91d4ebf1, 0x99392ff3, 0x4141b6ff, +- 0xe1b1fb92, 0xfdd865f8, 0xe2ef5c3d, 0xc1dea1be, 0x7ff43479, 0xd8a32b15, +- 0xff432d73, 0x7f73674f, 0xb6cfbb59, 0xb0bef625, 0xa38ce83e, 0x5b91a1fd, +- 0xfbf8c52e, 0x8c73815a, 0x73d8e601, 0xdf641790, 0xf4d9d9d3, 0xcb2f6b3d, +- 0x2c0771af, 0xf2bee17e, 0x2cf2bec4, 0xeae97131, 0x7149f5c8, 0x973fbc3c, +- 0x167ffdce, 0x5b148f6b, 0x07d5fd98, 0x6bdd00a5, 0x3db847d5, 0xb123dfd6, +- 0xcea2c273, 0x857bec23, 0xb7248bb5, 0x33b1bb87, 0xa3819fc4, 0xcf1e5655, +- 0xc90cbc0d, 0xfa88e04b, 0x25dfbe29, 0x9e227be2, 0x62cf4226, 0x8f3eff9a, +- 0xecefa6e4, 0x75a38a6e, 0x30a75fd3, 0x211c3374, 0x9bf2152e, 0x24fa7889, +- 0xf249d7db, 0xed71fac3, 0x54ff9c14, 0x8479c7f1, 0xd89b869f, 0x1d856fd1, +- 0x4fd34bed, 0x3baffc51, 0x0fd5ee20, 0x24a28714, 0xf2c01397, 0xcf675ec0, +- 0x1f9e46f6, 0xfaf57bb3, 0x0f7d8d88, 0x754e1f58, 0x6cee88db, 0x754c994a, +- 0xa7765864, 0xf3a2bd22, 0xdfaa22f4, 0xeff39457, 0x01d41a3c, 0x3ab68796, +- 0xbf89277d, 0xb8a6ee95, 0xcf8374fb, 0xd13de19b, 0xe1245dcf, 0xfcf5ff64, +- 0x972145cf, 0x72d793c6, 0x9d7e1326, 0x5365dfbe, 0x45fd793c, 0xfcf6ae95, +- 0x9c595f93, 0x8d38d1a9, 0x76d95b8d, 0xe31d1b64, 0xcf4ffc1a, 0x4efe3076, +- 0x2c318129, 0xb5bd2cbf, 0x0e9a4bef, 0xf29531bd, 0x2723bee9, 0x3831aaa7, +- 0x7f446def, 0x4d7f449d, 0x6bf61260, 0xad24ad66, 0xb70ef911, 0xb1f77f67, +- 0xe85f3a1c, 0xa52e3b25, 0xe29dacf6, 0x3bc77d64, 0x779409f6, 0x98d6f174, +- 0x66586aef, 0x2d1cc0e3, 0x963d37ba, 0x7f1927bf, 0x1e7c8357, 0xddd16880, +- 0x5bfb6253, 0x40fdaffe, 0x03f30e7a, 0x603f38d1, 0x7bab09c8, 0x8799d59d, +- 0x9e9eec2d, 0xbf625bee, 0xe1ce2acf, 0x1636697e, 0x73af643d, 0x90b99ee8, +- 0x3c333352, 0x2219b440, 0x07dd1766, 0xddfe6447, 0xe7e618da, 0x67f58967, +- 0xe847239b, 0xe239cdbb, 0xf42e727e, 0xc3b771b0, 0xe03d6b00, 0x095b5330, +- 0x5856d66e, 0x6ca9cb23, 0x65060d2f, 0xc7247fd2, 0xe56cbcec, 0x4c90f2bf, +- 0x3372c3df, 0x1e4365c3, 0xf163dd32, 0xf712ffef, 0xf1c39953, 0xfdc3db38, +- 0xf416a50f, 0x040566dd, 0x6df9fdd9, 0xe8f71510, 0x0f31f7c9, 0x37ba37eb, +- 0x99d30dbb, 0x008f2614, 0xf69f3f1b, 0x4fdb2723, 0x33533974, 0x7f10722c, +- 0xf4c72452, 0xefadea55, 0xd8073fa3, 0x030df6bc, 0x0f978f7d, 0xc3ba3bdf, +- 0xdf47bc6f, 0x0f1e4a99, 0x6dd50efb, 0x1d508b4d, 0x1de8da83, 0xe80563f2, +- 0x56aa7337, 0xfe1ccce6, 0xc07c1f9e, 0xfc48cfbe, 0x7bb69f9e, 0xbbf86725, +- 0xd27be32f, 0x9a35817d, 0x2eb1f109, 0x1196eacb, 0xbcd6651f, 0x657bec19, +- 0xe1256fa7, 0x36d482ea, 0x0e624d81, 0xa87964cc, 0x782a55c0, 0x92ff682a, +- 0x027df8c7, 0xc5d17860, 0x039eb7f9, 0x5238f7ec, 0x2bf7fc2d, 0xad0e2176, +- 0x8d7e862e, 0x27858fbe, 0xef946a16, 0xdd5a776e, 0x8859cf94, 0x7e61d4df, +- 0x3bfcac5b, 0x5e6b168a, 0xf1b8fc80, 0x3ca2585d, 0x3d16505b, 0x56dd0ecc, +- 0xfc272f96, 0xc59b47fe, 0xcf922df7, 0x472bd3b7, 0xf25c1e50, 0x2cb9f9ab, +- 0xcc79472f, 0xba61e437, 0x7028f7f1, 0xfda1dfff, 0x82fefe27, 0x04546fb1, +- 0xc8438f03, 0x838390d3, 0xc77144f4, 0xf4327a83, 0x9f2c305c, 0x0e5c295d, +- 0x52417d0a, 0xc8d5dec8, 0x6ff7135e, 0x01bfefec, 0x8f1a3ec3, 0x00003430 ++ 0x00088b1f, 0x00000000, 0x7de5ff00, 0xd554780b, 0x733ef0b5, 0x7993331e, ++ 0x0f20f264, 0x0084f102, 0x010e02a2, 0x93c443c2, 0x80d06210, 0x2a5e4041, ++ 0x24863bc3, 0xa7f68113, 0x84cef7ad, 0x36b5a220, 0x97836c5a, 0x8d04077a, ++ 0x68d03a8a, 0x00e84e03, 0x6bdab11a, 0xeada5454, 0x8088a0ed, 0xc5978490, ++ 0xd7bfca96, 0x7324e7da, 0x6a24264e, 0xffffdffb, 0x6df9f8fe, 0xece7d9f6, ++ 0xed7af6bd, 0x7b5ed6b5, 0x21f5208f, 0x72113789, 0x1968fe19, 0x7d2109e1, ++ 0xfcb6cb3a, 0x992463f6, 0xa22bff10, 0x84239dbc, 0x7c239dfb, 0xde4228d3, ++ 0xcc05c2de, 0x6bde1eb4, 0x4fd68423, 0x301e9e6f, 0x6fb21167, 0xf7815984, ++ 0xc3cb6f4f, 0x3f97a4fa, 0xbdb40a70, 0x805e65e2, 0x09ef69ba, 0x884ec467, ++ 0xc8f2dcd7, 0xfb79f40d, 0x4ad93ccb, 0x49fe2287, 0xc8429226, 0x7f610b31, ++ 0x997d5917, 0xb62b5595, 0xfa1bbbec, 0x13346d2d, 0x62a7ed2b, 0x3769f2f7, ++ 0x83f2fad0, 0x2a578122, 0x7d4b57b6, 0x009efd69, 0xdafa8417, 0x71c67fbd, ++ 0x6949f2da, 0x27212870, 0x5f22167d, 0x96ceeb4d, 0x79f45994, 0x21676059, ++ 0x83b65fbc, 0xfbe89b73, 0x7df79b65, 0x3597fd0c, 0xda790388, 0x1b7a8aff, ++ 0xb1b08791, 0xc798132f, 0x6f0069d2, 0x31229bc5, 0xa5e97ad3, 0x1c011255, ++ 0x8952b509, 0x547fc603, 0xce301d92, 0xc3471c41, 0x74b3c567, 0xe55dfa1c, ++ 0xa61b9c8b, 0x1e226956, 0xb775a780, 0x7653ce75, 0x34b55798, 0xfddfbe18, ++ 0x2def0480, 0xc57c2c0f, 0x5b7c032a, 0x738042a4, 0xd96916f3, 0x56feced0, ++ 0x83a5bfd4, 0x765d58eb, 0xddaa27aa, 0x11f49e58, 0xeb3b9b22, 0x41288465, ++ 0x901dc03b, 0x7ceb0fa6, 0x204b9e7e, 0xcff43464, 0xd9d2d913, 0xf20c253f, ++ 0xfa03ff81, 0x2683e04f, 0x567b6047, 0xba56bd27, 0x4ee5bfe8, 0xa9759d7a, ++ 0x73da13f4, 0xcad7fba3, 0x140e8047, 0x0b9f5a9e, 0x697cc7cb, 0xc9f46e58, ++ 0xfa5fb788, 0xe7596086, 0x27f3e373, 0xdcb1637c, 0x7cb053ec, 0x658457d2, ++ 0xef8257c0, 0xc1cdf56d, 0x83cf9b72, 0x95f69fcf, 0xabef5962, 0xf9cfe7c2, ++ 0xc3b960d6, 0x2fe7c7e7, 0x196036fa, 0xb962d5f4, 0x658757cb, 0xef802f83, ++ 0xc7abe2bd, 0xc417d1b2, 0x8d7c7be7, 0x617c8658, 0x7d02f72c, 0xb5f61969, ++ 0x77dfb960, 0x7cd7cb18, 0xd9aefc11, 0x87cb1c77, 0x273bbc55, 0xe2813c90, ++ 0x1710a9cd, 0x58921715, 0xb489e4ac, 0xeac2589e, 0xf3fa7729, 0xf14f5a24, ++ 0x63c53ad0, 0x9e70f2df, 0x56fbd699, 0xfbccf6b1, 0xd685be48, 0x7dacfd33, ++ 0xbe4ac3c0, 0xd407d695, 0x9bc1f6b2, 0xb471f9fd, 0xdac0383e, 0xce11ddaf, ++ 0xb5fad1b7, 0x3c3ed641, 0x69d92644, 0xd598787d, 0x2656de73, 0xa73d6839, ++ 0x3f73d585, 0xd2724ff6, 0x7d846e7a, 0x7854fe3f, 0x8fad3c52, 0x13ed676f, ++ 0x1702912f, 0x1c244fad, 0x79edf3d6, 0x9eb40905, 0xc2f562ef, 0x39050b7e, ++ 0x15edff06, 0xe5098b23, 0x6dff7a85, 0xeb4e908a, 0x71156452, 0xe7fa7c53, ++ 0x922c3d60, 0xb6fed025, 0x8c22a17f, 0xac8975a3, 0xf6fff686, 0x7efb6197, ++ 0x76f6c651, 0xdf6c2aff, 0x6ed8c92f, 0xeb0fbeaa, 0xb60a89af, 0x8fdf5727, ++ 0x2926bfef, 0xfab83ed8, 0x8b37ac11, 0x5b1f6c1e, 0xbf7c2bfd, 0xfb60f259, ++ 0x4a02eb63, 0x07ffad01, 0x7c0ad9e7, 0x4a79c35d, 0x6bf03649, 0xf284ad30, ++ 0xcc8e7aeb, 0x0878f901, 0xc3ca9a98, 0x014974fa, 0x1ff7b6fd, 0x9cf14fb9, ++ 0x50c9dbca, 0x43f4f65f, 0xf3cfd859, 0xfb488fd8, 0x67ee7be1, 0x756337e2, ++ 0xa6fc4cfd, 0x01a7eb54, 0xf6b1abde, 0xdfbd9fae, 0xf3c3d78c, 0x4fd6994d, ++ 0xe8e3f613, 0x5e26bcdd, 0xe787a09e, 0x4fd6b972, 0xd093f633, 0xe2c2783b, ++ 0x613f5d18, 0xcfd6b971, 0x9f4fd83b, 0x48a3c1de, 0x28fd74e3, 0x3f5a3dd2, ++ 0xf49fb187, 0x9613f5de, 0x23c3d06e, 0x39fad0ad, 0xeff4fd82, 0xf314bcdd, ++ 0xcc787a8d, 0x273f5a15, 0xbd59ee91, 0x43bf67eb, 0x8efd9f8f, 0x439cfc0e, ++ 0x6ef50678, 0x3d4ef95e, 0x1d9df27e, 0xfd84b9f8, 0x7ebbd35c, 0xf8f53bf6, ++ 0xc0ecefd9, 0xbcc1c88f, 0x5e6ef586, 0xfc7af1f9, 0xe077c7e4, 0x3c01c9c7, ++ 0xcf077a23, 0xf8f47d6b, 0x074fad79, 0x9e11527e, 0xa783bdd1, 0x9f8f4520, ++ 0xfc0e9482, 0xb8cf08c8, 0x5af3f5de, 0xaf3f1e8a, 0xe7e074a5, 0xc6e7ec1a, ++ 0x20abcdde, 0x829f8f55, 0xe4fc0ed4, 0x9e793f60, 0xd087847a, 0xf7dd1c7e, ++ 0x8f5fdcd3, 0x1dfee69f, 0xfb01b9f8, 0xc9fb4c99, 0xc29fb9ee, 0x0a7e3d4c, ++ 0x53f03b33, 0xd29e7880, 0x339a7ebb, 0xce69f8f5, 0x54cfc0ec, 0xef6a67ec, ++ 0x957855e6, 0x57853f1e, 0x24dcfc31, 0x8675c08c, 0x9e6e9dae, 0xbf73727e, ++ 0xefa3853c, 0xe7562ef3, 0x76026e5d, 0x33d9af0f, 0xe9e145a4, 0x091df6fb, ++ 0x68910f39, 0x2eff26bb, 0x5a838fc0, 0x4d76d179, 0x9d38d8fc, 0x24a0951d, ++ 0x4549eaea, 0xf7ef757d, 0x6ba01929, 0xad739d4f, 0x93dd3dae, 0x9467aba3, ++ 0xdfbdd78e, 0x575f2abf, 0x2dcd6abf, 0xfcb3f7ba, 0xd9eaebb7, 0xdee9e61b, ++ 0x48bb541f, 0x5d757ed7, 0x9afdae99, 0xfd5d4ac0, 0xeb1ffaba, 0x5c161fde, ++ 0xbebf6bab, 0xfb5d21f1, 0xba63f088, 0x4f83c8fa, 0xdd1fdee8, 0x3ed755b2, ++ 0xba73f0e6, 0x5d9171f6, 0xc70dfaba, 0xbfdee8f7, 0xaebf7db1, 0xdfc5d37e, ++ 0x23cfdeeb, 0x6dedebef, 0xef759fcb, 0xa67d764f, 0xed39bf6b, 0x6a9d834b, ++ 0x4ebb1d77, 0x5720f3ad, 0x7f12fd04, 0x6af684ba, 0x5d6121d8, 0x7e676bea, ++ 0x7c99638a, 0xb48ff294, 0x8c9cb17f, 0xa8ff497c, 0xb7d790dd, 0x7d08eaf4, ++ 0x9ef1c3fe, 0xf9f45dab, 0xf5cf250f, 0x0df618ae, 0xa48e37e5, 0xa09b2941, ++ 0x203fb634, 0xcfcf7e32, 0x08f834b8, 0x6a6bdefd, 0xeb409c1f, 0x4179f3d7, ++ 0x38578f90, 0x71d5da13, 0xf782a93c, 0xfd04cce2, 0x72b207a6, 0xc947f29f, ++ 0xd4fe86c3, 0xfb3ae0ce, 0xd27a20dd, 0xfeaa8ed0, 0xce760fc4, 0x5e74fefa, ++ 0x9579097d, 0x1fec24fb, 0xbfefbf48, 0xfb43cd2c, 0xcfd44b33, 0xa25f1e88, ++ 0xf1c50fe3, 0xcd0f20c3, 0xaee8fe30, 0x8c079be3, 0xc96f8dd5, 0x6f8dd52c, ++ 0x2ef8e891, 0xfd5f7e42, 0x253e3ab9, 0xde4278c2, 0xf1c73ee2, 0x38a599cd, ++ 0xf51203fe, 0x8fc7a2bb, 0x05bf18eb, 0x7761ffe6, 0x5e301ff3, 0x32ccff3f, ++ 0x3625fcfd, 0x9f553fff, 0xc38fc756, 0x3b99fff9, 0x599fe6cd, 0x666fe6c6, ++ 0xef8c76fd, 0x047fc0ec, 0xcdd63fc6, 0x09ece6f8, 0x555ff9fa, 0x99bf9fae, ++ 0xfab27f8d, 0x1dbe3a82, 0xbb92ffc7, 0x557fe6c0, 0x992f8e39, 0x1fe06e3d, ++ 0x2aae2329, 0xfd27c740, 0x054be2a8, 0x40e3a176, 0x0a912439, 0xb9db210d, ++ 0x0fc70801, 0x7dbf18e3, 0x0df94715, 0x9f1f99f5, 0x9cd50093, 0x546fd4b9, ++ 0x8ec57d79, 0x1ef4093c, 0x6b7f53b6, 0x92ea0aa9, 0x9bf91e46, 0x0607346c, ++ 0x1b5b7851, 0x97d43f79, 0x0031bc6c, 0x266bd5fa, 0x3be04a0b, 0xf9e18481, ++ 0xdb0f8fe7, 0x632f3d1a, 0x3c56b4b9, 0xb7928916, 0x9f303f0e, 0xf0a2a90c, ++ 0x1826064d, 0x94ff59dd, 0x18e071fa, 0x1efd4c7f, 0xcf9ffd42, 0x7fde3644, ++ 0xea0f7f53, 0xa1efea11, 0xf1aa4ce3, 0xa1ddda3b, 0x897f0a34, 0x02a7ff0a, ++ 0xef4fd793, 0x2a7e02e4, 0x68fd5f9f, 0x0bd7fa04, 0xd228d8d6, 0xe858e13b, ++ 0xe9d5d24f, 0xa740fcbc, 0xc0e6ddf6, 0x2bf10e56, 0xa3a6be03, 0x78b21268, ++ 0x75c50643, 0xed1ffbe7, 0x39ccda9d, 0x2883b909, 0xff7d2a62, 0x7f5cd5ae, ++ 0x96771d17, 0xeb61ce62, 0x42619290, 0xa61926b9, 0xdedc84b1, 0x3da44230, ++ 0xf88ae990, 0xdc6a2469, 0xfafa4519, 0xbd7d12ac, 0x13445455, 0x3a75ab85, ++ 0x7ed0b647, 0xb7d1cf67, 0x340ce36b, 0xab3a3225, 0x9c5095e3, 0xb347d3a4, ++ 0xc781cca1, 0x1cf3a42e, 0x8356fb17, 0x2458bbc7, 0xfde3f461, 0xd5d0087d, ++ 0xcdef8c9f, 0x1b79b173, 0x5a239de1, 0xcf3a1294, 0x00f90b39, 0xfe11b7f0, ++ 0x29b5ed3f, 0xdcb4e1a6, 0x98910bf0, 0x08c7ceba, 0x718f5cff, 0xd611413e, ++ 0xc6a5f9f9, 0x8e6f8ce7, 0x14fff4a9, 0x5f9683f8, 0xf8507f00, 0xd1fcaa8f, ++ 0x7f1957a9, 0x699ecd78, 0x9bed0fc0, 0x55748278, 0x950ee5f9, 0xead6965f, ++ 0x8f1082f9, 0x3e5c7408, 0x2879cb87, 0xab660f8a, 0x4ebcb07c, 0x117737cf, ++ 0x831e98bf, 0x6e37732e, 0xee4d3fb9, 0x544fbf3a, 0xf0ff99be, 0xd74fc43e, ++ 0xdd3a3279, 0xaee9d2ad, 0x1dfb7d2a, 0x52ef5d2a, 0xeea73ae9, 0xfaa9d7d1, ++ 0x80e4f320, 0xfdeef208, 0x88cf4689, 0x951e9e8e, 0xef38469e, 0xf779e956, ++ 0x8d3d188f, 0x7a5446f0, 0x89ceea46, 0x78574064, 0x582df08d, 0x183e65d3, ++ 0x8fe85ad7, 0x636f4f4d, 0x51a3aade, 0x53822bcf, 0x928d1d56, 0xd3f515b3, ++ 0x027bf575, 0x2fef7573, 0x6ba85baf, 0x8f7b5a5f, 0x86f17dae, 0x85f5757b, ++ 0xdee91ffe, 0x5aa6b05f, 0xd5577ed7, 0xf9f6ba83, 0xeaea8fa5, 0x749b3d73, ++ 0xb39ecfef, 0xab3ed745, 0xfb5d59e4, 0xba9da28c, 0xb76574fa, 0xded37dee, ++ 0xfe036e6b, 0x9e03fb7c, 0xc1713d80, 0x33c605fd, 0x3745b82f, 0x27d473bc, ++ 0xf31f5f23, 0xb8f2c10d, 0x7f7c8dcf, 0xcb1637d2, 0x7603c6d6, 0xbae82758, ++ 0x10248cb8, 0x579a68d2, 0xac1fa1bd, 0xd3d704d3, 0xed53c990, 0x2603f5a7, ++ 0xb8a1e519, 0x91e1224e, 0xd8b07084, 0xf3b470a8, 0x1e91ed51, 0xe2a8ebda, ++ 0x5edaea4f, 0xdcfd891c, 0xabc2d8fb, 0x5bbb2f80, 0x065fe81f, 0xaa6d3dd8, ++ 0x2f6c6f5d, 0xf44948e7, 0x22d64273, 0xb313561c, 0x2625ca3b, 0xd2bbe5ff, ++ 0xea1389f3, 0x5755c1e1, 0x99482f1a, 0x24f8153c, 0xcbc7275b, 0xe9d3aeeb, ++ 0xe4d10277, 0x236fc03e, 0xd457cf75, 0xeefba0df, 0xe11e3ed4, 0x315d04ae, ++ 0x92c5960e, 0x87a04ccf, 0x673207c3, 0x9538030c, 0xec6f58a3, 0x29e17683, ++ 0xa3aad15f, 0x257e8083, 0xcdf71e58, 0xcf98f2c1, 0x5f51e583, 0xfa9f9629, ++ 0xf88cb0aa, 0xdff960d6, 0x1f963f3e, 0xf96036fb, 0x962d5f27, 0x58757d87, ++ 0x600be87e, 0x8f57c879, 0x20be7be5, 0x46be2d96, 0x0a7d5b2c, 0xf5dc9a96, ++ 0xd5c777c4, 0xf024f875, 0x933e0c5f, 0x1bd5fc6a, 0x59f27426, 0xf200ff1c, ++ 0xe2e78699, 0x0fcab33a, 0x487e3a29, 0xf90e5f00, 0x3af687ac, 0xeec3e551, ++ 0xeedd8fbe, 0xe1affadd, 0x93dfa9b7, 0x29f93adf, 0xd94fc0c3, 0x30d3f13d, ++ 0xa69f8a3e, 0xeecc5c9a, 0xa7e9f951, 0x7e188f30, 0x42303cc5, 0x6bd944fa, ++ 0xd6099e4a, 0x3eea95b1, 0xf5807d08, 0x35d8eab3, 0xb416ddf4, 0x604302eb, ++ 0xe43b38dd, 0x1f61836f, 0x4a61ece1, 0xe7eeacfc, 0xee93e467, 0x7fa0aef1, ++ 0x89402cb3, 0xddb5d49e, 0x6af0c71a, 0x42229135, 0x0707b5d7, 0x345eed3d, ++ 0x4902eb14, 0xee03ef84, 0xfd188ee9, 0xf0195b52, 0x6b5e13db, 0x870d5f1c, ++ 0xf13d8efe, 0xa7285cf7, 0x1cbd989a, 0xbb478077, 0x729f849d, 0xd63b7e03, ++ 0x0d3bb325, 0x83edede2, 0x0dda1724, 0x7f1e9264, 0xfe1d7cfe, 0x6a38a41e, ++ 0x36b775c1, 0xf037f10d, 0xbde9c1ab, 0xfa4f5fc0, 0x2e7c27bd, 0x0bff7982, ++ 0x7e93d9f0, 0x122f49ec, 0x91b17e45, 0xef6dbfce, 0x64879cb0, 0xf8caf718, ++ 0x8cd7f6d6, 0x2dfe3cf0, 0x452db8f9, 0x4c96e3e3, 0x2a907e02, 0xae1b672f, ++ 0x74ba078e, 0x3d03d3f4, 0x927ddfb9, 0xe9fbfe09, 0x0f7f7d2c, 0x978bfb18, ++ 0x1d3d7708, 0x244921d7, 0xbc95fa9e, 0xfe8f3b67, 0x87e23b8c, 0x9b5ec1b8, ++ 0xbf0646bb, 0x857fe4f1, 0x1f59e865, 0xf07b385f, 0x61f82729, 0xaaf8d32b, ++ 0xa8e831a3, 0xacc11595, 0xbfb47b2a, 0x9fafa8d2, 0x828ae5ad, 0x7e392f38, ++ 0x675830e6, 0x4547555c, 0x5869fbd0, 0x4cacfd6a, 0x939c7093, 0xccf1d9f5, ++ 0x7d300bff, 0xf50123b2, 0x059f49cd, 0xc367ffdf, 0x1a3f5dd3, 0x9034843c, ++ 0xcfa02ccf, 0xf7765b69, 0x0f2b77ef, 0xe20979c2, 0x7e2424a7, 0x95a6fe05, ++ 0x00797ffe, 0x5d602bf4, 0xe41bd7eb, 0xe1ebe6fd, 0x78dd0ef9, 0xdb593bf4, ++ 0xbaef8633, 0x1c813b97, 0xd29ef8d3, 0xfeea2fef, 0x6b7a8af6, 0x4d8ede95, ++ 0x8dbdd5d0, 0xbb3a55e9, 0x8601fe16, 0xc027157b, 0xb2ae5612, 0xdf609b61, ++ 0x07b4fc00, 0xbfe09382, 0x0abdec70, 0xc8f2444b, 0xc02d2e28, 0x6ac68ba7, ++ 0xfecf2ffc, 0x2753d533, 0xc80912de, 0xa144b919, 0x8fecedca, 0x44c4f4ae, ++ 0xdad58beb, 0xc51586a2, 0x789d6eb0, 0x43f456e5, 0x27129096, 0xa4a5c7f8, ++ 0xb5e21736, 0x08a989a7, 0x7934f3e4, 0x4a3239cf, 0x8482ad1e, 0x41bc5cf3, ++ 0xff53c76f, 0x5e5f575e, 0x232fafa7, 0xbec0a7b7, 0x228db2fd, 0x37a07009, ++ 0xf35fedf4, 0x3977ec2e, 0xeb0f5aa9, 0xad9146f6, 0x445c8b67, 0xab7aa0c8, ++ 0xcebfb7e2, 0x2eeb485d, 0xb459c581, 0x127be87d, 0x1653ff99, 0xb42922dc, ++ 0x9186b3fd, 0x440d5077, 0x87ac0fbf, 0x32ffcb75, 0x772edee7, 0x85b7dfa5, ++ 0x66af08df, 0x0fd9740f, 0xa8a8e157, 0x0c4094e7, 0xe053207b, 0xfaa99c98, ++ 0xe9705f2e, 0x0cd31ee2, 0x4fcceff5, 0x4fc744c9, 0xae4f787b, 0x0ff19a30, ++ 0xd09c7ff8, 0x4fbe792e, 0xfa5d69ff, 0xf6a7ffcf, 0x9ff68fdf, 0xda7febab, ++ 0x81ffb53f, 0x179fe05d, 0xdf8affab, 0x9f8af0be, 0x97b293ea, 0xba12771e, ++ 0x6a109e4e, 0xbe94dc53, 0x77efdbe5, 0x0b8f9d02, 0xebf0277e, 0x145f0089, ++ 0x3d6eb188, 0x3c6a702a, 0x1073b146, 0xd27f8377, 0xf73e4ffe, 0x7c478c53, ++ 0x61745db5, 0x1cdead3c, 0xac395336, 0x98a7b86c, 0x11fac70c, 0x0ce07f56, ++ 0x3d46f50f, 0xf33d95ff, 0x87e40a78, 0xe3514e50, 0x67b4614b, 0x5e7db72b, ++ 0x9793eb08, 0x191ca3b4, 0x2ff183bf, 0x5bfea226, 0x6d77c528, 0x9c6270a7, ++ 0xc5e2abc0, 0x33d3f0db, 0x29ca13bc, 0xa0be805f, 0xf1fa089e, 0x554aefc6, ++ 0xe0ad753b, 0xa3663e48, 0xc6431eff, 0xf0d45e80, 0x4ecc0242, 0x57f679ad, ++ 0xb8508fc3, 0xcb7b6d4e, 0x4be145c9, 0xc1b3a793, 0x47b9ffc5, 0xb6ef5eee, ++ 0xb68b7952, 0x4b75b487, 0xebed546e, 0xc5cb2b10, 0x79f213b0, 0x6e88b7ca, ++ 0xfe5c7d3f, 0x3f4f53c2, 0x3fccf101, 0x6883dd9a, 0x785e2bff, 0xb4f1c3fd, ++ 0x98a762be, 0x61a6cc5c, 0xe93a52e7, 0xafffa5e3, 0x47a4e9c9, 0x975e6fd9, ++ 0xf9ec61e4, 0x749d897d, 0x9f73b159, 0xc5758644, 0x3ee0a4c7, 0x418f6229, ++ 0x4291e09f, 0x9e6a17b0, 0x7104abfd, 0x397b13c6, 0x03159a92, 0x475e5b9f, ++ 0x84f0007b, 0xd5e954f4, 0xfbc33f41, 0xd0174a5e, 0x197a46db, 0xeaac5bdf, ++ 0xf217e817, 0xbf7f282c, 0xa0f207b8, 0x037664fe, 0x5c5f4a1e, 0x7cf984e5, ++ 0x3e315421, 0x29fdf5ff, 0x54bf1d0a, 0xb0b8a7f4, 0x9f4bcf64, 0xdff201fc, ++ 0x907f77f2, 0xa225f182, 0x2d709ba4, 0x3cc3a7f2, 0x859e6e97, 0x3c465cf3, ++ 0xbfa587c8, 0x1f404be6, 0xd148105e, 0x627218ce, 0x7c9c9915, 0x971295b1, ++ 0xf00bf3ce, 0xe83f2127, 0x1db03e3d, 0x097beeed, 0xa81f83e8, 0x0316a173, ++ 0x18582fd6, 0xaea2febd, 0xcfac040b, 0xf6ddfe68, 0xe9d00b40, 0x15257f64, ++ 0x44bc5df6, 0xe0f8abf0, 0xf97ed32e, 0x32a72777, 0xc859113a, 0xeba3bf55, ++ 0x0e7824fe, 0x8a88b7ef, 0x3beeb875, 0x73ab3972, 0xf8ead5fc, 0x5838ee14, ++ 0x8948bfaf, 0x8ae6bf6d, 0xeba01e9a, 0x459f1476, 0xff933bc9, 0x79320f6d, ++ 0x303fe4d7, 0xcfda08bd, 0x0472621f, 0x487ac1df, 0x62a70ae1, 0x1c99befb, ++ 0x47ea07ea, 0x6df392c7, 0xfae72aa2, 0x50bf2376, 0x3e2e05f8, 0x9c606f8a, ++ 0xee03a444, 0x48db2cbb, 0xa3d28fbf, 0xd9d7185e, 0x8e4d5fb5, 0xab7e6b97, ++ 0x6407d7a8, 0xdd03d333, 0xc47e55db, 0x7818b953, 0x5f9009fa, 0x197eaf2a, ++ 0x812c57e4, 0xe3b97ff9, 0xa8f387c0, 0xd4197edc, 0x57af56e4, 0xba5b728d, ++ 0x2589346b, 0xddda5fb7, 0xd2dca624, 0xd6e531e7, 0xfe7e411e, 0x3557ad3f, ++ 0x3c030e3c, 0x4789d75e, 0x87764f4d, 0x3c9ea34f, 0x5788c828, 0x7fa49ea3, ++ 0x576e4887, 0x50f8d47e, 0xe7b2bfe3, 0x7d02ae2b, 0x1aa7c1d4, 0xa9f0761f, ++ 0xe25d87c6, 0x1a3c3abb, 0x3ec02fdb, 0xbe6b850d, 0xa3b4d365, 0xb4b495d4, ++ 0xc9b7dc13, 0xbee3c99b, 0x613ce5aa, 0xc4442079, 0x4c8fd0fc, 0x4ec1a355, ++ 0x3bf7f89d, 0xc290ff4e, 0x45f89f3b, 0x2b501796, 0xe97fdda2, 0x7409e5f2, ++ 0x3c54f33e, 0x9f68a7cf, 0x4732e94a, 0x1471c2e0, 0xf102b9ce, 0xfc4227c7, ++ 0x469f2396, 0x54bf31c1, 0x89bf875f, 0xf4fd9d29, 0xf5b7fef4, 0xf96bbe53, ++ 0xa7eba52e, 0x1f790883, 0x1787114a, 0x3a6af9a2, 0xcfe295d0, 0x0c0b8a3b, ++ 0x11153d40, 0xaefca24a, 0x7f664517, 0x63305bbe, 0x7937d834, 0x33c587b3, ++ 0x7e8c1f7e, 0x67d557af, 0x3c72fd67, 0xa1b3f9e8, 0xcf6ff46c, 0x88ec5c1e, ++ 0x407a1795, 0xd5d7b3e5, 0x3b36977d, 0xfe53cb57, 0x68ed236f, 0x56edf8df, ++ 0xbec63db2, 0xd35126e0, 0xe8dd2ad7, 0x9fc74f1f, 0x5ce1f2a3, 0x4e7c69fa, ++ 0x4e66dd14, 0xbb38213d, 0x3efe01d2, 0xbec3f28d, 0xaf817e2f, 0xac07bf01, ++ 0x1892c291, 0x2af3fbf6, 0xffee26fe, 0x0b73f31a, 0xe0027942, 0xebcec0b1, ++ 0x694f20e2, 0x0c943af2, 0xee26b805, 0xa367e7bf, 0x0f7b1f29, 0xc7c86ef2, ++ 0x48ce86f5, 0xb0fe189e, 0x3fd09f11, 0x444799d8, 0x03ebe217, 0xe02964b1, ++ 0x565983f5, 0xef9afb02, 0x588aee4b, 0xb3342e70, 0x292e66f5, 0xfb8a30b9, ++ 0x79bf0fbf, 0x7ce11db3, 0x76b38f8a, 0x95ddf796, 0x9fdc98ff, 0x6a817175, ++ 0x6790f80e, 0x002e64f5, 0xe242b471, 0x0e04d9f9, 0x68a6fde5, 0x38d795fd, ++ 0xebc805fd, 0x2e710ca9, 0x14af6d13, 0xb1f01222, 0x00a771b7, 0x32adfbf6, ++ 0x211e3051, 0x199b0d54, 0x223af715, 0x03af880a, 0x17779b7f, 0x4cdcf7e0, ++ 0x94b80133, 0x609c67a1, 0x8d0b9c07, 0x6ee83944, 0x91f07f5e, 0xf4220569, ++ 0x8c3f9043, 0x6c9850fc, 0x4d67d5d3, 0x94dcfd22, 0x91cd136e, 0xf418ee55, ++ 0x9f1891ab, 0x59bf5af5, 0x6fd33ffe, 0x637ea813, 0xeb462d7c, 0xc6255bb7, ++ 0x2dfa51f7, 0x5b7e9635, 0x02a72d59, 0xca6cac5f, 0xaeba054e, 0x9f69737c, ++ 0x0dedfa58, 0xdfeff31f, 0xdbccf354, 0x76fd51fa, 0xeb7e947d, 0x8c5bf547, ++ 0xa968eeb8, 0xf2cdfa97, 0x6f7f233f, 0x318b7e80, 0x7f1522df, 0x0a2b7e9a, ++ 0x2b7ea355, 0xf2ebc7ea, 0x7a926ea5, 0x1f0b6fd2, 0xd175859f, 0x3fc18b6d, ++ 0x6fd05780, 0x0e7aaa6f, 0xf73d01c6, 0x5beb92ef, 0xde8ab9e9, 0x21ffb9ea, ++ 0x6e7a6b3c, 0xed0e7f65, 0xc87cae99, 0x2ccadcf4, 0x3656e7a6, 0x72b73d31, ++ 0x4673d310, 0x45df96fd, 0x2befb1bf, 0xd1efd087, 0xd5facc8f, 0x78bdb49d, ++ 0xd0b6e88e, 0xed658bf7, 0xe8d5467c, 0xeff77d68, 0xcefa3752, 0xb9cf067d, ++ 0xdeefa4f4, 0x08377d01, 0x9040d8f5, 0xdc7f2323, 0xcba6d032, 0xebe0fba7, ++ 0x04bfcf63, 0x1e07f2f2, 0x4c8feffd, 0xfbda4fcc, 0x2091b1f5, 0x3c001f77, ++ 0xab3ddf54, 0xcfab5ff2, 0xd274fa8f, 0x15ef2650, 0x55fc31f7, 0xbe6c7036, ++ 0x0c80f9ab, 0x2edfc0eb, 0x577d1fa2, 0x67a3f313, 0xd8fa5b9b, 0x5fffcfc0, ++ 0xfd25ca22, 0xc5185e2b, 0x962e730f, 0x5773dc61, 0xf82b739c, 0x62047399, ++ 0xc1763b01, 0x804e5bc1, 0xe2e0bafd, 0x177bb406, 0xd244f3c0, 0xb731f791, ++ 0xedea4f43, 0x3b8d79d7, 0x5d20cf5f, 0x9a2621f3, 0xae265d19, 0xb25b02e2, ++ 0x5047e6ba, 0x5bf30cbb, 0xbf12798c, 0x9b3fe757, 0xc8be208f, 0x7b7bbc3b, ++ 0xbdf9f90c, 0x866e4f11, 0xbcd58a97, 0x5c554f1e, 0x4a513c4c, 0xe94c2f17, ++ 0x2f5dcbc4, 0x4067d647, 0xfa1c3dfb, 0x6b79c65b, 0x5fce3378, 0xdfe6a3c3, ++ 0x9fdf502c, 0x33123a1f, 0x73c3444f, 0x0d117c97, 0xbc7c06ef, 0xeb99e9ad, ++ 0xcb9030c8, 0x9f9e4c8f, 0xfa3e068d, 0xdd718f3d, 0xd20ee63b, 0x4f7a579d, ++ 0xcf54cbc5, 0x19148291, 0x80aa48f0, 0xee95e6cf, 0xce853d7c, 0x2b2536ef, ++ 0xb3ea4207, 0x207926fe, 0xdac0711e, 0xe3507a8e, 0x266651c3, 0xaf556617, ++ 0x55d7d07c, 0x234deb80, 0x0af942e7, 0x9a9cf41b, 0x8fbde667, 0xee01dfc9, ++ 0x4633ebaf, 0xb9619e21, 0x7ada8520, 0xffa17405, 0x74621a9c, 0xe85d02f1, ++ 0xf691a73f, 0x657bc066, 0xc30ee732, 0xef3b8dfb, 0xc37a7e07, 0x9c839f4a, ++ 0xadee7297, 0xf4f61d0c, 0xb1f22b94, 0x318f8b10, 0xb9db9198, 0xf7802e7e, ++ 0x27dabb12, 0x1f2dcd13, 0xa9131c00, 0x87816cdc, 0x145ffa01, 0x8bf68dfd, ++ 0xca7a0f91, 0xdf8eea07, 0xbf3c5473, 0x03b07401, 0xb025dbbe, 0xb661bc87, ++ 0x5eed68fe, 0xbc402e41, 0xa4687469, 0x4628cbeb, 0x3c0c5307, 0x55d5a6df, ++ 0x9c437b3c, 0xa14fdf08, 0x07126ffe, 0x375f7ebb, 0x966efc6b, 0xe209e2bb, ++ 0x7a51e90a, 0xf45bf403, 0xe36566be, 0x5baf88bb, 0x4cf35356, 0x8d2f8aee, ++ 0xaf07a03e, 0xe56eb784, 0xcc48f1a7, 0x2b6fb0bc, 0x7acca33f, 0x6d6bd9f9, ++ 0x887aeb7f, 0xa87135ab, 0x41284857, 0x69983f17, 0x01cb7666, 0xbcf907ab, ++ 0xbdd14dfd, 0x7faaee55, 0x0174ab26, 0x7cfa257f, 0x089824e2, 0x95974de8, ++ 0x7bcda67c, 0xe8b7e300, 0xab0de0f5, 0x5dd7e907, 0xcccc33ff, 0x1eceedfe, ++ 0xc337ead3, 0x28d79078, 0xae33c7eb, 0xa95c5a47, 0xd47979a7, 0xbcebbf71, ++ 0xedbe71b4, 0xb49784be, 0xdb4e3c60, 0x7bc3d89f, 0x3f608976, 0x7e827116, ++ 0xf71daf1f, 0xfd09ff37, 0xee8d26df, 0x1f887fbe, 0xdf9e2985, 0xc614f1d8, ++ 0x773f4fb1, 0xcfc81a64, 0x6279578a, 0xbad7f2a1, 0x2cc241c3, 0x3b02444f, ++ 0x5781aca1, 0x842fce30, 0xd9446773, 0x6193d419, 0x81c978f8, 0x976caf7a, ++ 0xbf4c5039, 0xb3e57b2f, 0x6b7f10e1, 0x9ff4cb5d, 0x1f9539ff, 0x90e191fd, ++ 0xb026500f, 0x7d2379fd, 0xf3f9531e, 0x1cdb6ed4, 0x3d5cdfd0, 0x165bc73b, ++ 0xa39a2d9c, 0x9a0f0ce2, 0xdee71645, 0x6c3cc36d, 0xe61cb3ff, 0xd17c0331, ++ 0xfcb548e7, 0x32cf53d0, 0x28d65cbd, 0x703ce006, 0x56cefd59, 0x1d978b88, ++ 0xeafda336, 0xfb833fad, 0x7a5e937a, 0x6e379d81, 0xd0f175e4, 0x7ac8712e, ++ 0xf8866c3e, 0xea054359, 0x823f5a01, 0xf71aa0f5, 0xb27196fb, 0xbd352f15, ++ 0x5c28a7e2, 0x9c679bf1, 0x65b82e78, 0x91e313bb, 0x17de57f5, 0x0c7712e8, ++ 0x1dc6a83e, 0x70417ea7, 0x771d887d, 0x49f2a93c, 0x3b8facc8, 0x8c24fa92, ++ 0x73385247, 0x2fc4624b, 0x85fff83a, 0xbec24f0b, 0x5f5da9d9, 0x9770093e, ++ 0xc9ee737f, 0x527c509f, 0x7582e405, 0x07dcfbdb, 0x7da0cfb8, 0x4faaa1f7, ++ 0x067d9f5a, 0xff5a69f7, 0x6f437668, 0x645f4dad, 0xeb453ec2, 0x2053afce, ++ 0x69babb8e, 0xab6bfa32, 0x4a949e5f, 0x5a03f862, 0xe81bfc09, 0x91913ec5, ++ 0x0e1a076e, 0xa79c0264, 0xfd61dd29, 0x072788ee, 0x5e9c582b, 0x3bc8e356, ++ 0x75cbef62, 0xcc371b89, 0x5846edb8, 0xb7441bc7, 0x3f117a4c, 0x79e9443e, ++ 0xb8e82f7d, 0x0827dd43, 0xfc62bd4e, 0x83fc34f8, 0x5982ebd2, 0xd0bf871f, ++ 0x9f3ff4b0, 0xa486b680, 0xe1c7e36e, 0xdb4fe05e, 0x5667dbf7, 0x68e40588, ++ 0xb718f3d7, 0xdf51fa07, 0x70beb483, 0x2ee21321, 0xbbf6c5c7, 0xc9baff31, ++ 0x6554798c, 0x3ca11f4d, 0x2efcbeb5, 0x7511abee, 0x7495adff, 0x127db1fc, ++ 0x6ef3a7d5, 0xb3b8b073, 0x4b88074a, 0xae7c4ecb, 0x5f199fc6, 0xeee9716b, ++ 0x2d63d1e2, 0xbbfed803, 0xb1591fba, 0x3112cfed, 0xb1b9fbc4, 0x5723af40, ++ 0xf0d547dc, 0x8c3c02e0, 0x896fde89, 0xd8efff1d, 0x0dd0316f, 0x58f609e8, ++ 0xad0a7ec7, 0x7ab883f7, 0xd628fb80, 0x16eb5dfe, 0x2ad34fb6, 0xd45bcec6, ++ 0x5a465ff6, 0x812efb0c, 0xf4bbedde, 0x8b6f8f34, 0x42706ca7, 0xd7c574fb, ++ 0xf5b14ba9, 0x4e161dfb, 0x3be037bd, 0x7397ebee, 0x5981bcc6, 0x0d1597c0, ++ 0xa7b02447, 0x9b4df5b4, 0x7fd529ef, 0x8f1cf53e, 0x07d644e7, 0x377ea00f, ++ 0xc24a8fea, 0x784686e2, 0x6f4c2d4b, 0xf5b23655, 0x472ed4e3, 0x39fb4ec0, ++ 0xf2377fb5, 0x238ee575, 0xd7f69f92, 0x291bff5c, 0x05679512, 0x0a2047eb, ++ 0xee2f53fe, 0x97f6ce1b, 0x1c6ebf98, 0x38ea87e7, 0x71ec50de, 0xe8ce3bbc, ++ 0x0fe159c6, 0xcfdcec4a, 0x293bc795, 0xbfa1b328, 0x81222d93, 0x4193ffbc, ++ 0xde5628be, 0xa88b5cca, 0xfc98b3c5, 0xcf1475d0, 0xb9d83a61, 0x42513e4b, ++ 0x63b57bbb, 0xef3861ec, 0xc921dabf, 0xa9a8bf10, 0x353c7966, 0x034ee6ff, ++ 0xdc24d77a, 0xb571fb81, 0x92bafc06, 0xd710795d, 0x8c941570, 0xea357602, ++ 0xa4c5049d, 0xa3b57f83, 0x70a65528, 0x34ed53ae, 0x5cf1b822, 0x2c2cef28, ++ 0x2ef0f982, 0x631acb93, 0x97b441df, 0x5e144f10, 0x1cfe9744, 0x5234b927, ++ 0xfcb47e86, 0x4b4b729b, 0x14ba3633, 0xc616314c, 0x66f377b2, 0x6dde70ba, ++ 0x41ff543b, 0x852bb221, 0x3ac191e5, 0x7e2bb6d2, 0x3f1eb938, 0x47e50a24, ++ 0xdb9cfa9b, 0xe81f6fb1, 0xa24e75a5, 0xa3395024, 0x6cf99558, 0xc23acf38, ++ 0x9f0365c2, 0x57aff99e, 0x10d6bf69, 0x9b457e8f, 0x5527cb5d, 0x6cce4012, ++ 0x1bcc61e4, 0x9cbe5604, 0x31a709d4, 0x2bc0909f, 0x4c69f751, 0x0fe8ede6, ++ 0xe2ccdd9d, 0xf6b93c03, 0x7c581357, 0x7e00048e, 0xa1597d75, 0x109679c2, ++ 0xdfde1877, 0xc078c0e1, 0xa31737f2, 0xa21d00fc, 0xa45495f1, 0x675af73f, ++ 0x7f070e75, 0xf5559366, 0x0b4afc6b, 0xa259b39c, 0x44a7dbf6, 0x8a962e7f, ++ 0x75e41fa1, 0x5faf2aa9, 0x883c2b2e, 0x659e68f9, 0xe753e7a8, 0x1acdcfe8, ++ 0xa204b4f3, 0xe601c9fa, 0xdbc9773f, 0x7082dc6a, 0x56b7f31b, 0x1aebebd4, ++ 0xbd013f1e, 0x93a00d79, 0x0714afd8, 0x91bf11ec, 0x309abfc1, 0xd7e3dbea, ++ 0xafc7a69c, 0xd7e3d655, 0x3f88c436, 0x6e1d7e3d, 0xbf34be3d, 0xc6fc3bb4, ++ 0x439fd58f, 0x57e157fe, 0xa476aab4, 0x57fa578a, 0x2a614962, 0x174ee01b, ++ 0x461728c2, 0x87b0ca39, 0xff77f839, 0x7e3540e4, 0x7ea076e5, 0xc3e7534f, ++ 0xd9df612d, 0x80788e40, 0x04728dd7, 0xcf410127, 0xaec7c8db, 0xd6205663, ++ 0x75f2e467, 0xd573d3dd, 0x2c8ed7f4, 0x066d5fa2, 0xf91ebdfe, 0x4df79d81, ++ 0x2c9a8124, 0x0bb75390, 0xcfa0efd6, 0xc2225ee2, 0xbdc42fbd, 0xf7dc1064, ++ 0x11f2c2e2, 0x6da55f35, 0x8373c128, 0x14f9f0c1, 0xe48f4fd0, 0xbd034fb4, ++ 0x4a4a5de7, 0x20fe0f40, 0x781f9d8e, 0xc5fb2d48, 0x2d5eaa49, 0xf826f378, ++ 0x70ca243e, 0xb42dbd5e, 0xea0832dd, 0xa3de3c8d, 0xbda84de2, 0x0d6fc606, ++ 0x25ae0c89, 0x8820c096, 0x38893483, 0x0992eb6e, 0xc3b32e78, 0x7cb10b7e, ++ 0x67d0b691, 0xfa51c5ce, 0x17f1b5bc, 0x6b9c40d7, 0x9e762993, 0xe9ab64ca, ++ 0xc1bfadfb, 0x937b792e, 0xeeaf2cad, 0x1e740191, 0xaacfd395, 0x879330eb, ++ 0xbf3a541b, 0x9c16ecb6, 0x4e21cbff, 0x90a47586, 0x61d6f3bf, 0x3ee39e74, ++ 0x0cf8d410, 0x528e578b, 0xfd01afdf, 0xf6b5fa82, 0xdc3e9e7d, 0x7020547d, ++ 0xd5546f4e, 0x5eb7f432, 0xa73e5275, 0x04ab917c, 0x16df0247, 0xdef01284, ++ 0x04c7ef1c, 0x2dd1faed, 0x733f8e82, 0x373575d5, 0x4c05e542, 0xf6fac394, ++ 0x60c11171, 0xe0780507, 0xeb8e1baf, 0xaab22f9f, 0xa4939776, 0xbc6f9f00, ++ 0xf79073c4, 0xdc4ed6da, 0x6ddc296b, 0x1c22fa4b, 0xd4e1e76d, 0xf12f2d2f, ++ 0xfbd6b145, 0x17c65655, 0xeb82249b, 0x7665a6cc, 0x5fee2f8c, 0xac157656, ++ 0xc8fd5fef, 0x73ac5573, 0x29fa51e4, 0x2963e59e, 0xf02c64f1, 0xe18e3af7, ++ 0x24bd36bd, 0xc6bfbe46, 0x6b7f1acf, 0x2cbe9d7c, 0xaf2b13ce, 0xb32b1bf1, ++ 0x0d97f2d3, 0xd7f024e1, 0x1c7872f6, 0xe7ad75b7, 0xfc6ee78a, 0xc0066d64, ++ 0x873c6de3, 0x1425b776, 0xa3764f3b, 0xb7fd89d5, 0x4357f5ae, 0xa90fdf1e, ++ 0xec9e8270, 0xe88ddfbe, 0x8218fd6f, 0xa59df0b2, 0xe39e2176, 0x5b216a5d, ++ 0xd42dde21, 0x00eedfa6, 0x65349ffe, 0x89f7853d, 0xafae1312, 0xc237449b, ++ 0x0420afef, 0x3c6a0fe3, 0xb234dfb7, 0xf33cfa25, 0xe7bcd693, 0xcf1e94ac, ++ 0x97485d59, 0x039b8f24, 0xf8ffddf8, 0xbbe413ab, 0xe919a2ed, 0x87f557d8, ++ 0xb75eefb4, 0x666dbb32, 0xbe0db29c, 0x28c9a527, 0xd38f6e27, 0xdc2464bd, ++ 0x1ef1409b, 0xf49d4725, 0x8977e3f3, 0x28e3aa1e, 0x1376893c, 0x145125f2, ++ 0x538ba5d9, 0x348e51fa, 0x8e6120b9, 0xa69b1e40, 0x1710b957, 0x18395076, ++ 0xc187b165, 0xa52c48ef, 0x5820a6f3, 0xd7f58589, 0x38ea9c22, 0xf2798d97, ++ 0xe1732f94, 0x90c11470, 0x42e22428, 0xd5be9aff, 0x04baf4f4, 0xeeb2f282, ++ 0x43502151, 0x442cd9fb, 0xc95f10ac, 0x487ce452, 0x64144a35, 0xbfde2f3c, ++ 0xa5fe6094, 0x09d7fb2d, 0x150b761d, 0xf0df11fa, 0xe7ed620b, 0xbe1a71f1, ++ 0xbd007f3c, 0xfb60fc31, 0xdc6f307e, 0xfb9e3656, 0xe9da0b75, 0xb543fa1d, ++ 0xf5d50ac7, 0x26e7dc77, 0xbe104f96, 0xb3ef4489, 0x6687f519, 0x31bb8c9f, ++ 0x8bf616b2, 0xc191fdc6, 0xe055bb49, 0x7cead1bb, 0xba89f43b, 0x51098e6e, ++ 0xcfbf427d, 0x003c8d09, 0x7ce560f7, 0x8bb8e4cc, 0xe7e8393e, 0x55df7f01, ++ 0x62f9188f, 0xa5ca9844, 0x86543eda, 0x1d5c34fb, 0x633f6875, 0xd3c93bd0, ++ 0x9da2a547, 0x119bf2ab, 0x1b7c9acf, 0x8d673ee5, 0xc19980fb, 0xc348fcc5, ++ 0x84eb8438, 0xbd06ce43, 0xf60f36f4, 0xc51e5b7e, 0x97eb8503, 0x7e947f20, ++ 0x5303e709, 0x431bfe60, 0x4e415b37, 0x127af3be, 0xe5475fa2, 0x7bc33f69, ++ 0xe0fae3e2, 0x3c04e27a, 0xaf3bee54, 0xa46127ae, 0x501c8777, 0x978e8939, ++ 0xe46ffc68, 0x6a3e4d77, 0x6c8de2e0, 0x6047673c, 0x20b9e59d, 0x2663065e, ++ 0x57805d9b, 0x51aedecd, 0x4fe25bed, 0xb56ffb47, 0x51eba88b, 0xa4f80066, ++ 0x75ecd446, 0x3e3a25b7, 0x9f91dab5, 0x54fda57a, 0x9fea45ef, 0xf1b39d45, ++ 0xbfe8ed0a, 0xf84a2f79, 0xafe33bfc, 0xab914291, 0xb898dfc3, 0x17f15dd1, ++ 0xbb08471f, 0xf9ffec2f, 0xf230cdf9, 0xe77203c7, 0x9e206efc, 0x7f542357, ++ 0x50daaee4, 0x93f19363, 0x5db96943, 0xffb682f5, 0x301e9dd9, 0xf298fbca, ++ 0x6e1803da, 0xbdde41e9, 0x84bf1536, 0x367d00cc, 0x96ed4c3e, 0x7ff2aeac, ++ 0xd79f9d5e, 0x76def0c6, 0x9060fb47, 0xa7bc0da7, 0xc5ed0e2a, 0x7604c988, ++ 0x76826ec5, 0x51df7b8f, 0x4b7bca27, 0xe9fd6e92, 0x51f8176a, 0x54fb353e, ++ 0xef8d4bb3, 0xeaa5d875, 0x47c5a37a, 0x2f2a46b9, 0xe2a79e14, 0xa3807e3c, ++ 0x57fcc5c6, 0x7a0ae038, 0xa7ab49ec, 0x46cbf806, 0xfb0712e7, 0x59c24325, ++ 0xd612de2c, 0xf27767c9, 0x5bc83368, 0xd607e290, 0xff5d3f3f, 0xc3dd7106, ++ 0x812e3633, 0x10b54bc1, 0x72fd37d8, 0x92ac1b09, 0xbf78fe60, 0x9afeece1, ++ 0xbeec397e, 0xcc712dcc, 0x286ad97e, 0x3c96b49f, 0x0512f301, 0x7ce737e2, ++ 0x5401b877, 0x153e4388, 0x3e01d4a7, 0xce0a452c, 0xdc45c323, 0x8677a51c, ++ 0x6f20e410, 0xe65cb122, 0x7491fc58, 0xfed23fee, 0x3ce58a32, 0x818c8fe0, ++ 0x668dcf04, 0x83149d80, 0x89c6af4e, 0x6f5ecfdf, 0xe60e72e8, 0x9a7e5555, ++ 0xa4df3a25, 0xa60e7662, 0xc143ee23, 0x3ab6fc07, 0xb6c9c0ee, 0xacfb605e, ++ 0x678604fe, 0x0406ffa3, 0x6a097983, 0x08897efd, 0xaff444d6, 0x7ebfc0fc, ++ 0x2bfd0593, 0x4107711b, 0xc7147edf, 0x39ebb3e2, 0xffa806f7, 0xc0b7685c, ++ 0xdc9a3f3d, 0xc8f0f268, 0x02dddb84, 0xe379d57d, 0xfbe0e1d9, 0x0f78b952, ++ 0xe13adcf0, 0x3875e0ec, 0xc64cf693, 0xcbaf0a77, 0xd7e8d7b7, 0x67e8ea28, ++ 0xb44ab885, 0x4348779e, 0xe56f6ec0, 0x57e0dce2, 0x31c3deb5, 0x7a8b3978, ++ 0xcdd0411e, 0xfcc6cd33, 0x7f553691, 0x0b2e3dfe, 0x4f5b51f9, 0x6036fce8, ++ 0x8f30d7fc, 0x86a8738e, 0x73c6a773, 0x1dd969a9, 0xcc74a071, 0xe0912dc7, ++ 0x3672332e, 0xce3b4364, 0x24cf6ceb, 0xa64bce31, 0xcf31ac46, 0xc5256b05, ++ 0xb780d7db, 0x012ab154, 0x5dea71f4, 0xf1188f4c, 0x47f9c6d1, 0xda3ec334, ++ 0xf998c41f, 0x96995a28, 0x12c26b76, 0xfa5a7efa, 0xe7b52c14, 0x66217675, ++ 0xc6c9315c, 0x9373bf7d, 0xf062c475, 0xb46c9337, 0xf79ed3bf, 0xfc50543e, ++ 0x5eee31db, 0x5ef0c717, 0x5ef0c717, 0x94f86927, 0x3afe41e3, 0xde5d6eeb, ++ 0x259f46d3, 0x443c8041, 0xe7ca3a7f, 0x77a31752, 0xda0afbe7, 0x32887d37, ++ 0x89282e65, 0x8ed9228d, 0x43e2cf7c, 0x5f90f9da, 0x804d9efa, 0x2db7297c, ++ 0x2df7f54b, 0x0c09be8c, 0x271bf3ee, 0x6429b8e3, 0xc53075ad, 0x9312b2f3, ++ 0xa746e21b, 0x09c9fd17, 0x6517a647, 0x3c82e4b4, 0x48f9c2a4, 0xde69defa, ++ 0x267986e3, 0x954551d7, 0xe402f8c4, 0x0a69d292, 0x342e77ee, 0x1ebbccc5, ++ 0xa7fb6363, 0x585ce347, 0x434da5a6, 0x8bd6753a, 0x312fc013, 0xd79529f2, ++ 0x3aa325f4, 0xbe5331cf, 0xe4316c51, 0x8d244dad, 0x616fae1c, 0xc6b257c4, ++ 0xd6deaace, 0xe41925e4, 0x4aadf610, 0xe8d51ea8, 0x357d403c, 0xf8a2e305, ++ 0xf8de85c7, 0xe70dfc1a, 0x17a8f98d, 0x43223935, 0x82b79e98, 0x878a8dde, ++ 0xd47d35b6, 0x3f1df61f, 0x0e73b7f9, 0x8bfa77d8, 0x3d00eed0, 0xf7befc7b, ++ 0xe98e701d, 0x5c58fb93, 0x9f836ee4, 0xf4c6d8b6, 0x64ada37f, 0x816bcc1e, ++ 0x9eb91fef, 0x6b257e28, 0x3dc9fed8, 0xde70de01, 0x506f7f5d, 0x70c93045, ++ 0xf11f908f, 0x8ec4215a, 0xb1b26feb, 0x3b3dcb78, 0x321948b6, 0x8729ef8c, ++ 0x7eab8ff1, 0x7606f1e8, 0xcf06957f, 0x24231da2, 0x12fecdf0, 0xeffbab32, ++ 0x3f5b222d, 0x3fd86294, 0x3378a8f3, 0xdeacd9c2, 0x71f4bdab, 0x90b31f96, ++ 0xea86b58e, 0x9d884f61, 0x63ce30f7, 0x617227e9, 0xd2de252a, 0xbbf43907, ++ 0xe8fbfde1, 0xf359e67a, 0x19b3ee00, 0x5ef5d9e7, 0xb3fd051f, 0x8dbd2ae5, ++ 0x87976de7, 0x12f83ed8, 0xecf941e2, 0xc436fe72, 0xe318c5ce, 0x660f678d, ++ 0x3f0f00db, 0xc4f1a9b7, 0xce06325c, 0x383aef6d, 0xf74afe20, 0xef529f56, ++ 0xbb7b828b, 0x23ee3ca1, 0x2303ce58, 0x3cbbe290, 0xf0216ef4, 0x4ee36557, ++ 0xdbed0fbc, 0xd08aa3ea, 0x52e42709, 0xda897a6b, 0x8e81dba1, 0xb3a70964, ++ 0x9cb72b4f, 0xcd5f9893, 0xfaa773f0, 0xc7c04efc, 0x96f7c870, 0xd2813a7f, ++ 0xf172cefb, 0x697df47c, 0xfbf4d82f, 0xaf9dbdf0, 0x750acf36, 0xbf9b4aff, ++ 0xa9e7ef91, 0xdb64b87c, 0x297df5f4, 0xbe9a6a4a, 0xc5cf54c8, 0x8d20f9e1, ++ 0x929396af, 0xfc18f4c2, 0x83b3d1a3, 0xc33f424f, 0x5c7468f9, 0x9d50bb52, ++ 0xdd4d3fb7, 0xf8834c3f, 0x7a6f9194, 0x2add973a, 0x9e413246, 0xdad17c8d, ++ 0x7b27fdcd, 0x589ecc6c, 0xa0852b22, 0xbbb9a937, 0xcf6515de, 0x9b6a171c, ++ 0xb672027f, 0x8779f18d, 0x182703de, 0x225bf9f4, 0x1d2bf7ae, 0xf7dc2a72, ++ 0x071af487, 0x3f6608f9, 0x738da7bc, 0x0328a7cc, 0x1177c045, 0x257d2796, ++ 0x9d41c0ca, 0x9d36cbed, 0xddbd8273, 0x9c608436, 0x87a1d5a8, 0x8f1b4bf7, ++ 0x954be27a, 0xcb42e51e, 0x1d067f37, 0xf305adb5, 0x525d8e2c, 0xcc974ce3, ++ 0x29e6b145, 0x4a3ad9d9, 0xeecd7bd4, 0xf34ee556, 0xf4a81663, 0xf6c43bbb, ++ 0x9e6d17cf, 0x92e8f48e, 0x3ffaa96f, 0xd4381b0b, 0x2cfa4633, 0xf98cdf75, ++ 0x79038b67, 0x7a177df8, 0xee918791, 0xed79ba46, 0x9b6f762e, 0x3dc12550, ++ 0x7336c776, 0xa2b8dfb8, 0xcb38bd1b, 0xf356fa6e, 0x3ba3ce31, 0xab6f97f8, ++ 0xc097df5e, 0xc04847fc, 0xb5f846e7, 0x0a252ff9, 0x7cea4bd3, 0x89179bbb, ++ 0x32f2c4dc, 0x1efe75d4, 0xfb02a738, 0x2cf30f25, 0x3b8d5b7f, 0xf06bf069, ++ 0xc851e71a, 0x8279e397, 0xf31e3ab6, 0x07f6efb0, 0x09efc3d6, 0xc38ebddc, ++ 0x3a3bb6f5, 0xdb447a69, 0x5c6ca9df, 0x1e5a7988, 0xadd80fda, 0xb6131f6d, ++ 0xc381b12f, 0xa5badd7b, 0x27e58867, 0x424f4775, 0x5096dd18, 0xd9bf81ba, ++ 0x3c84bef5, 0xbef46065, 0x328a6050, 0x8a9f7a30, 0x653f3104, 0xdd74fd45, ++ 0x5ebb22f3, 0x7f24f78f, 0x66212aa4, 0x37934b3c, 0x7934fe4d, 0x6665daf4, ++ 0xe6810a5f, 0xcfc02c8c, 0x50cfe8a3, 0xaec73cfd, 0xa5cc4bee, 0x3a6e54af, ++ 0x5897dba7, 0x6bd1963a, 0xcf8c5f29, 0x14b3d3bb, 0xbd3d3a0f, 0xbbcfaec8, ++ 0xd1f3bef8, 0x89c9a1e6, 0x9ca33f36, 0xd237bf18, 0x19e78b43, 0x07a462e9, ++ 0xc57e09c0, 0xc0b64ddb, 0xdbe70a5a, 0xdfdb831c, 0x5bb84564, 0x702926d3, ++ 0x7d32b34e, 0x807f963e, 0x1ec1d30f, 0xa3b6a92c, 0x5dfaa87f, 0x87177aa3, ++ 0xb0ed51c8, 0x48caad97, 0x24a9ce76, 0x6264f809, 0xc5866475, 0x0fa3c845, ++ 0xf7085cdf, 0x347c4fed, 0xef420332, 0x853c3f8f, 0xde47b7d5, 0xfee1b8b7, ++ 0xf10b5bfe, 0x2fd07dfe, 0x52bf7e30, 0x6ddf7c1b, 0x5cae789d, 0xa3fbd997, ++ 0xd9f325cc, 0xbdacd5bd, 0x1663da9c, 0x1f95deba, 0xc81afc1a, 0x714b796f, ++ 0xca81c411, 0xd74ee221, 0x19c50abb, 0xeb670db6, 0xdefa78fc, 0x1b679b61, ++ 0x75c5d7f2, 0x1f962eb8, 0xc8be5012, 0x158f1641, 0xf4ad5ce8, 0xd47175bb, ++ 0x5df8a62e, 0x83716897, 0xfb9f4c1f, 0x975e3fc1, 0xd472c8a8, 0xf07e8d73, ++ 0xceb1c01d, 0xf607f2c4, 0x3e3839bd, 0x603b0572, 0x83148f9f, 0x67c072ff, ++ 0x9ed8d2c1, 0xfcf0b927, 0xc5899e46, 0xefed8c47, 0xc8987a68, 0x9517c019, ++ 0x7f942507, 0xb37b03f8, 0xa9393082, 0x59dcec24, 0xe78221c5, 0x160f2a6c, ++ 0x381b39e2, 0x4ea9f087, 0xce6bfc0f, 0x15f274d9, 0xc0be53c3, 0xe3510b15, ++ 0xbaadd816, 0x1a6a9f3a, 0x7c21f302, 0x89ce1b9c, 0xaaa619f0, 0xfcfe745d, ++ 0xf8a4b455, 0x1e6e5c10, 0x9da99bee, 0xfb879134, 0xfbd46ab2, 0xec4c6a68, ++ 0xde36bc3c, 0x5a3f1551, 0xf251d7d9, 0xf4fdd029, 0x36b92d3b, 0x7e827fb6, ++ 0x1adf36b4, 0xf81c214e, 0x3c13af67, 0x4c9390bf, 0x6cfe000e, 0xfc0b1944, ++ 0x55123926, 0x6bfdb37c, 0xa50197fa, 0x8dfa6cdb, 0xaffdf94c, 0x10b8ff0f, ++ 0xc77609ee, 0xd165569b, 0x8fbb65fa, 0xe74c33d5, 0x730b28b2, 0x5fab3f0e, ++ 0x80373a67, 0x354779d6, 0x2b46c3ab, 0xc744f85d, 0x50ff42da, 0xf7e54718, ++ 0xc075ca1d, 0xc58982df, 0x12fd8471, 0xf968e7ee, 0xcf28eb29, 0x0e4a3f00, ++ 0xaa65c599, 0x41b79ff3, 0x915f3c9c, 0x8f625f21, 0x77d1ef7a, 0xf2bc352d, ++ 0x07de1336, 0xdfe02506, 0xd4f860e1, 0x941a42e8, 0x976f20eb, 0x60eb9504, ++ 0xc3afaf1f, 0xfec072e3, 0x132ddbc4, 0xbc379f41, 0xbc5ca7f7, 0xd62afdbf, ++ 0xa9b7c8cf, 0x73e748cf, 0xb7fdb7fa, 0xf78bef44, 0x81f5e475, 0xd01928ef, ++ 0x1764e57e, 0x61ca93b9, 0x2964428d, 0xbd6bfc1b, 0x9840d93f, 0x2b6c3a7e, ++ 0x7d40efe9, 0x6c75c612, 0x4323dd8d, 0x9327e8dd, 0xe55ec496, 0xd7c349d9, ++ 0x6250fee0, 0x45e1e346, 0x8efc2eb0, 0x29c24bdd, 0xbe9be60a, 0x1b3f71d4, ++ 0x8d9438c1, 0x4e21b9c4, 0xcd24dc4c, 0xd3c6a29f, 0x92af8c4c, 0x65fca373, ++ 0xfbf43e75, 0x1f8bc802, 0x0cf96363, 0xe83c7e74, 0xc64411d7, 0xc5c42472, ++ 0x1ea481b2, 0xc121efac, 0xfda13fc3, 0xf165663f, 0xd13d4b28, 0x38171bc5, ++ 0xc1ba5d98, 0xdbfbb229, 0x60ede0c4, 0x219dc457, 0xda2bb02e, 0xb8092d7e, ++ 0x6eb82f1f, 0x66ba7dc5, 0x9fb5c613, 0xd82e0311, 0x46bf6a1f, 0xce92b790, ++ 0xba54dafe, 0x263efd6b, 0x9c40d7c9, 0x564e67ef, 0x608f267f, 0x09fb76de, ++ 0xb7fb0029, 0xaa961989, 0x1cd1f8e8, 0x9b77b307, 0x3bb7f95c, 0x14dd9e20, ++ 0x31fc6047, 0x404ce37b, 0xe477e78f, 0x5e2f8158, 0x3c511c02, 0xf75d9a24, ++ 0xe7897f42, 0xf859bc28, 0x0bf3e59c, 0x8a7888f2, 0xd8b7f1df, 0xeb37b865, ++ 0x16f06b19, 0xc17d53cc, 0xbf04f784, 0x43a7b924, 0xb2b3a5fd, 0x33f0f40b, ++ 0x9c38c159, 0x9c260bcf, 0xed714bcf, 0x70a4aed7, 0xc584343f, 0x111b04b7, ++ 0xa60b3f40, 0xf05ef97c, 0xd63e5453, 0xaa13f5f4, 0x11c63d1c, 0x9820b73c, ++ 0xb48e50f2, 0x76b6a1fc, 0x7d43f982, 0xc0f0b666, 0xb5d371cf, 0x87985338, ++ 0x1284d0f8, 0x04dcf682, 0x5ae788bb, 0xce197f20, 0xf5544db7, 0xcb8fc4f0, ++ 0xb03e598b, 0xe3dc10fb, 0xdeaec079, 0x6beea607, 0xc9f2a4de, 0x5bc2248d, ++ 0x178dfb68, 0x059c3b89, 0xf7ebe7f7, 0xd8369e1f, 0xfed59397, 0x01577695, ++ 0x7a23ce3c, 0x5d726ffb, 0x0f5809e1, 0x002289f3, 0x18b24d3f, 0x748ec1da, ++ 0xfafbbdc2, 0xaa1c1be7, 0x324994bd, 0xb4d6f3a3, 0xfcc9a77d, 0xbf684dd0, ++ 0xc06e4916, 0xf2bb4ecb, 0xf803e411, 0xa572445b, 0x3ed3e438, 0xe4385f96, ++ 0x15c08da2, 0xed3f9485, 0xeb6b9f30, 0x3a56fd6a, 0xb2076bef, 0x410f81fe, ++ 0xebfd5cbf, 0xf7d024e4, 0x697a5563, 0xc077c6a5, 0xc678ae5f, 0x3bebae5f, ++ 0x83bb73e5, 0x7934f3c5, 0x7e83be03, 0xf98188f6, 0x29b7f6b1, 0xbd076ebf, ++ 0xd04ed3b1, 0xba69fb8f, 0x99c80e65, 0x9529ce36, 0xfae58daf, 0xe0fb95ea, ++ 0x17fc9e77, 0xd051bad8, 0xbd14a2f7, 0x302527ee, 0xd72bddff, 0x790698ce, ++ 0xf3117667, 0x73d452ca, 0x92fcd150, 0x1a2fc51e, 0x59dab5df, 0x9fe3485c, ++ 0xe7dfbb49, 0x0ba4f9e1, 0x48b2b884, 0xf1a2bf87, 0x187f44cf, 0x12277df7, ++ 0xf9189fe6, 0xfc375767, 0x165e7793, 0xe1756f40, 0x7f8c839f, 0xda1be3ba, ++ 0x6163de0f, 0x87169fe4, 0xcb743fea, 0xfcf0973f, 0x49a6eafe, 0x6c9fdc57, ++ 0x51f3e9f4, 0x5b38e58d, 0xa7657cec, 0x52ddf78a, 0x41c3aded, 0xb1354c6f, ++ 0xc9027af3, 0xbbc29db8, 0x27bb4e3b, 0xea1b2abf, 0x87a6053b, 0xa8cc8676, ++ 0x3dda7687, 0xa6d78c1e, 0x5579d859, 0xf38113c1, 0x16beee07, 0x4777fa39, ++ 0x71b0769e, 0xdc786282, 0xbf8f6017, 0xec60f8c9, 0x521e1cd4, 0x3097d2cf, ++ 0xb8ea30bd, 0x6f7e05b4, 0xde6751ee, 0x298bd039, 0x8be03b80, 0xabde12a3, ++ 0x42547954, 0xbddbf8fd, 0x3c4216ef, 0x1e6bcb54, 0xc2dde7b3, 0x3b3f887c, ++ 0x5dfdbf19, 0x8ead3be5, 0x5f403e47, 0x1fd9ee1a, 0x4afe71d7, 0x097e4f7f, ++ 0xcef0d1f0, 0xf1fde376, 0x5fb638c1, 0x22c89b32, 0x68e3310c, 0x9d70fdc9, ++ 0xf91ef199, 0xde7661d9, 0x4f21e66d, 0x55e47bec, 0x67de30fe, 0x64efed4e, ++ 0xcfdfd827, 0xd085ecb7, 0xbad99108, 0xaeaa941d, 0x55467e63, 0x2693f036, ++ 0xf147f887, 0x8864fc17, 0xe60c77ee, 0xc3d1eba9, 0x47dd816e, 0x1f709115, ++ 0x7d8467f2, 0xb1d75417, 0xbe16671c, 0xc5fab397, 0xc8e700f9, 0xd000e552, ++ 0xe3c5dea5, 0xb0939ff3, 0xe6e81b25, 0x24ff7016, 0xbe93ca28, 0x23df3ae0, ++ 0x3b10c942, 0x27d3df6d, 0xff8c246e, 0xda33d3a8, 0xd0a07609, 0x1bbe107e, ++ 0x24673e33, 0x88fb71e8, 0xaeb04975, 0xb8537069, 0x3bdbb68a, 0x1ae0d0e1, ++ 0xf2fc64e0, 0x68e173a8, 0x077c03c0, 0xc8f1a97a, 0xaf7c0b31, 0xe9b043f1, ++ 0x2883e30c, 0xe83e00be, 0x016e0be4, 0x4c3c35d4, 0xab41f954, 0x42f9b3ff, ++ 0xc8f46b8b, 0x70b71017, 0x98be277e, 0xf235780d, 0xeee7b505, 0xe7b0c676, ++ 0x93cb1282, 0x635f3e34, 0xddf7c3cf, 0x273cc112, 0x7ecad7b2, 0x8093d0c7, ++ 0x71bf1efb, 0x3edb31b1, 0x4d499639, 0x93af7251, 0xefdaf5d9, 0x73088ca6, ++ 0xa08e7f68, 0xb44ee28a, 0x9ea1faf3, 0x23f8ab74, 0xee0e38c7, 0xf85cc517, ++ 0xc343b00c, 0x8daf6049, 0x41871730, 0x26d9761e, 0x98fd8066, 0x0d909b63, ++ 0xc8657ff3, 0x4960b7ea, 0xe96fa57b, 0x9dc9b66f, 0x0fa695f6, 0x6adda80f, ++ 0x6c9dfbe3, 0x6149bb7d, 0xaf409be7, 0xada1c347, 0x8026400f, 0x36cf0b83, ++ 0x1ea1b65d, 0xde28450f, 0x2838026e, 0xa471f61e, 0x3c87ec01, 0x093c9293, ++ 0x613ec0ec, 0x6b6ce001, 0xe2133afa, 0x37a1c59d, 0xc5bc030e, 0x5babbeda, ++ 0xb46aefbf, 0x487b35b7, 0x7b343ff3, 0xc17bf349, 0x05f682ae, 0xfc1773ea, ++ 0x6fac0ace, 0x9fde0b61, 0xf959d8f0, 0x6795451a, 0x58a3ce81, 0xa46dc79d, ++ 0xeed2e105, 0xe2a6994f, 0xf520f8a3, 0x3b438757, 0x1e295321, 0xa7f7aaa6, ++ 0xefeb754c, 0x6c6db887, 0xb453fbec, 0xdf7a7a7e, 0x60dc6eb8, 0xbefa7fd8, ++ 0xbb1f41e5, 0x3ef7e52f, 0x1f8f0fe6, 0x5805fbc0, 0xb166c77f, 0x0c5c26fb, ++ 0xd8a5070f, 0xaa57d8eb, 0x45378f3c, 0xebf9c386, 0x8efe7b7d, 0x3dfee6eb, ++ 0xec10ff7f, 0x042771c8, 0xe3b87902, 0xc78a8c4f, 0x32b1807c, 0xafd695f2, ++ 0x1b06f3f7, 0xf449cf61, 0x5334cbef, 0x01ab9478, 0xaf960b3e, 0x17ec7a9e, ++ 0xa3f9dfd0, 0xe73e8902, 0x06792851, 0x50be5c42, 0x66a19dfd, 0x5a53d98e, ++ 0xfbfab37b, 0x6a717f1e, 0x411688f1, 0x1cc557bb, 0xeaa9e745, 0x5d1a1f7d, ++ 0x3a2f1ea7, 0x4aef0c21, 0x67fbf81f, 0xf8b421c4, 0x2f5519c3, 0xc47f0392, ++ 0x373738f3, 0xfd802bdc, 0x4f1a737e, 0xa771a894, 0x8fd3d4c8, 0x771c438a, ++ 0x03dfec1a, 0x1a62fecf, 0xcdbf29e4, 0x37a3ca63, 0xe1adf3b4, 0x63e16f50, ++ 0xc462a3de, 0x7ba1cdef, 0xd9951ef1, 0x7a3e4cf1, 0xb5fc7f1a, 0x07ae4f94, ++ 0x076613ba, 0x487bb2e6, 0xbfddf48c, 0x22923fe7, 0x77c7bb43, 0xd237f477, ++ 0xf953d5e1, 0x13d56fb8, 0xbb7c8c3d, 0x7fd3ce97, 0xaa4efc35, 0x77f1f885, ++ 0x7f585d52, 0x758697cd, 0x4dbd5f8d, 0x9d81254f, 0xe4e9f1a7, 0xe337c624, ++ 0x8922ff76, 0x65e93bd8, 0xf175dbc4, 0x5b2f7e8c, 0x3dc4bb35, 0xf47d1a6b, ++ 0x90875d3e, 0x05a4fd51, 0x544ac4f2, 0x2a1f6758, 0xa884bb44, 0xeb8c57e7, ++ 0xcefe6cdb, 0x7b4ea0c9, 0x999f9dfa, 0xfd5ec2f2, 0xdbd14e3e, 0x83ac02b5, ++ 0xa66ac285, 0x5e3b54c7, 0xe748c783, 0xc209480f, 0x467c1ddf, 0xf9c2303e, ++ 0xbd7e4772, 0xf681eb82, 0x063337bb, 0x31898966, 0x63e1a1e6, 0x71eba126, ++ 0xe3d7ef76, 0xfdbd78a2, 0xc178ee7e, 0xeed6803b, 0x3748cde4, 0x3fa6bb63, ++ 0x1c80610a, 0x9f60fd2c, 0x414f8ecc, 0x28bc2879, 0x25f20511, 0xf1cfe9fa, ++ 0x91abe293, 0xd8b956df, 0xadf8eeb3, 0x3c4f22f2, 0x4ef93b23, 0x06d47c6c, ++ 0xa85bb77c, 0xf51c41b5, 0x1af4fb46, 0xcf82bd10, 0x7de267f3, 0x81131115, ++ 0xd0e4dad0, 0x67100399, 0x78261ef0, 0xb43f219e, 0xe9f0126f, 0xfa0b426b, ++ 0xa9e76d59, 0x776516ad, 0x6c6a8636, 0x26359760, 0xcd78f3b3, 0x2f974409, ++ 0xafca95fd, 0x4ecf478d, 0x0fb46253, 0x3e7d3173, 0xc3c92883, 0x370b3fe9, ++ 0x3f00fe50, 0xe3038fb8, 0xfb9c0524, 0x5bb064f5, 0xb1fbb2e6, 0xbcc69adb, ++ 0x6de14c9e, 0xf5012bbd, 0x07c6e4cc, 0x425175ee, 0x1231ff04, 0xe42fb79f, ++ 0x4284bef0, 0xc2f58dd9, 0xf7e85925, 0x6926f98d, 0x4fb43146, 0x99efd111, ++ 0x100b97cc, 0xc69d3aaf, 0x7b1dd5e1, 0xfc3548b8, 0x3a7fb0fe, 0xfcb8871b, ++ 0xbe9fe049, 0x02349c57, 0xd64f237f, 0x77f083ea, 0x7fc18916, 0xb9f2fd5b, ++ 0xbeda667d, 0xf987167a, 0x195d93c5, 0x3fc51fc4, 0x9c241b85, 0xd4a1edd7, ++ 0x19ebe07c, 0x8e73fa45, 0x9c9ed561, 0x81236255, 0xce48fde8, 0x6cdd7285, ++ 0x7f03bf6d, 0x2449bc37, 0xce4d3f30, 0x7df9516f, 0xdd249cf6, 0xb309d377, ++ 0xbab9353b, 0x5bbf9555, 0xae79bf54, 0x7e374327, 0xd0f66109, 0x017b481f, ++ 0x2ec7ec90, 0xad3d1fb6, 0x7cd0e5bd, 0x37ef8978, 0xade1f41a, 0x2f7e0c43, ++ 0xf90ebe5f, 0xe3738d22, 0x7d6e31bd, 0xf5636dfb, 0x1afca375, 0xc82cc3f5, ++ 0xeabbe3da, 0xcc1f4d09, 0x8845e26a, 0xa3cacd07, 0x58bb4678, 0xa4f7b76f, ++ 0x75c4c62f, 0xc92e2fa3, 0xd21983f7, 0x5c7c5f45, 0xc5f49df4, 0x32dba96f, ++ 0x3bf5ca96, 0x4fe8de9a, 0x98de83fa, 0x05f8efcc, 0x5d1b51f0, 0xf831cd37, ++ 0xb4775b48, 0x95214038, 0xa703d463, 0xe4cc7ed8, 0x3fc4e98b, 0xd00e33b2, ++ 0x5da847a1, 0x2f618ee2, 0xd6cf8a9d, 0xa1d24fdd, 0x12eca257, 0xdbfbf731, ++ 0x3da99325, 0x7c00e52a, 0x42be10fd, 0x42921ef5, 0xf882b048, 0x8c19da61, ++ 0xea057903, 0xfcfae2cf, 0xf473d314, 0xa7625c5f, 0x15ed187c, 0xea5d0e2d, ++ 0x3d29ecd2, 0x23c474bf, 0x577bb267, 0x04293e35, 0xcffc827c, 0xc09f71e4, ++ 0x1bff37c8, 0xfa32ca23, 0x00008000, 0x00088b1f, 0x00000000, 0x7cbdff00, ++ 0x55547809, 0x753eeeb6, 0x2a490d4e, 0x62c65549, 0x4a61270a, 0x0843c048, ++ 0x91602018, 0x520c6201, 0xad0e2280, 0x210c0e05, 0xfaf5cd09, 0xe76f6dba, ++ 0xd11a0484, 0xfdb1c5af, 0x15fbbe9e, 0x2b8fbd5e, 0x30188a41, 0x015b9260, ++ 0x06d88081, 0x9f3e01c1, 0xa88d2a5d, 0x6e874921, 0x3efdd82f, 0xef6b5ade, ++ 0x8a555493, 0x77befa6e, 0x66f6d25f, 0xf5af3d9f, 0x610f69af, 0x4cd9532a, ++ 0xf83096c6, 0xb05b1951, 0xd3dcc2d5, 0x7f36ef21, 0xfa31b415, 0x05ff06b9, ++ 0x635e1262, 0x33739889, 0x5dd8c696, 0xbfb2fea2, 0xf3f19ba8, 0xfaf0f2b2, ++ 0xdf85b177, 0xdd8c094a, 0x3666bcc1, 0x3d3bb18e, 0xff4fe591, 0xbbf28641, ++ 0x4f7f8456, 0x5ca7c471, 0x8c7f8388, 0xc9afe367, 0x4dc9958c, 0xc05edfcf, ++ 0x5949df58, 0x266af2b3, 0x0751ff1c, 0xf6d1ff1f, 0xc7967492, 0xc53dbbd8, ++ 0x8f485e89, 0x270cc1d6, 0x6755d631, 0xe404f4a3, 0x1af0d07d, 0xeb02dcfe, ++ 0xdfaf30b3, 0x94f6290e, 0x92cea94f, 0x80e09b18, 0x7f21534e, 0x0c9fd605, ++ 0xd863a365, 0x5e62d9d7, 0xc91d8c59, 0xa0fb9736, 0xa7f4075d, 0xe801bf43, ++ 0x0f7e875f, 0xff2839d5, 0xf28b9d5e, 0xf5129ca3, 0x13089353, 0x4558c19c, ++ 0x2f769dce, 0xc8e35bb4, 0x9cab3ca2, 0x1b7a4264, 0x797b2ff3, 0xde81d334, ++ 0x14ab8247, 0x5ab18529, 0x3359a497, 0xab00f887, 0xfa84afb1, 0x35de8295, ++ 0x83e6255b, 0xaf9f95ef, 0xbf4064af, 0x0f1876de, 0x2a5b53e8, 0xcff06cfb, ++ 0x9f67b692, 0xb33379e7, 0xf886d44a, 0x852f88bb, 0x153a57cd, 0x58b38c1b, ++ 0xc6193493, 0xf6f1b771, 0x9f25bbb7, 0xa45cff0a, 0x23a3f385, 0x44cbef82, ++ 0xfff18b3f, 0x72e2dda0, 0x7e8017c9, 0xb7861716, 0xc165765b, 0xe1d4d2b7, ++ 0x7c865a38, 0x2f1c3a9f, 0x8fbe0ccb, 0xef916365, 0x7e962f97, 0xf10d9538, ++ 0xe48d322d, 0xf5f96473, 0x6feabcf8, 0xff68d9f0, 0x11bcf8b7, 0x3cfc8269, ++ 0xc6a2d57c, 0xedb0b633, 0x79f20aa7, 0xfa8515e1, 0xe4f5c6ad, 0xcb067942, ++ 0xb1fcf5c0, 0xdb99ff27, 0xdafd50d9, 0xbc583fb6, 0x9ebfae53, 0x37be35bf, ++ 0xe075a551, 0xa1bceeb8, 0xc0142b71, 0xb6f3ac20, 0x46fa70ec, 0x5f9235f2, ++ 0x48bb444b, 0x58896d7e, 0xd617c187, 0x111a2003, 0x6457ee85, 0xf8f5c79a, ++ 0x8b17c836, 0x3796bc77, 0x7fb19cbc, 0xf50eba21, 0xbac4f827, 0x3e14cf15, ++ 0x3c88732f, 0x44f5ae00, 0x17656fe0, 0xc4c2c40b, 0xff2c5d16, 0x9354c156, ++ 0xeb2157d8, 0x0caf9fc0, 0xfd43cb3e, 0x41195d97, 0x5b8c67f2, 0x92dd30a6, ++ 0x5cb9df8f, 0x06afce46, 0xf58099fb, 0x96ffa275, 0x7e15a61d, 0x0b5cc758, ++ 0x6983c07b, 0x1c5b4f2c, 0xdfb7f512, 0x7d7aa261, 0xd899b27f, 0xe9ed8c4d, ++ 0x30662f48, 0x78eacd3f, 0xdfa2f51f, 0x7e7da8cc, 0xe6e7e702, 0xc0c7a678, ++ 0xb6e94cf8, 0x4a270079, 0x20d96331, 0x8b48ca67, 0x6cba01af, 0x941e0252, ++ 0x614d3ebb, 0x537720f5, 0xb38c1db0, 0x2f7e90f9, 0xfe6c9603, 0x21a9a26a, ++ 0xba07db13, 0x9bbd40e7, 0x1b7515f3, 0xd55a7154, 0x6f79629f, 0xed81d5bb, ++ 0xb7fc0efa, 0xf3f6334e, 0x0cc1a627, 0x00ed7bd9, 0xb22f282a, 0x37a87d9b, ++ 0xb293e4ca, 0xfd7df209, 0x2a3ea18c, 0x6128115a, 0xacb9b7c0, 0xe901c1bb, ++ 0x1463e46c, 0xf5c55dfe, 0x6b7ae0ce, 0x9e69f004, 0xa13cd3e0, 0x65da4aaf, ++ 0xf1251bd2, 0x0e658fb2, 0x045ba7e9, 0xdde9e68f, 0xee308925, 0x1ad2453c, ++ 0x15cb7f20, 0x6f8f0c25, 0x69ba3ea1, 0x89951f48, 0xaafdddfe, 0xcd819602, ++ 0x2df8e167, 0xa87ae56b, 0x5df116c4, 0x49681fd8, 0x84732ab8, 0xdd46cf97, ++ 0x60bef809, 0x25e85fe0, 0xca7f6116, 0x0424bfe4, 0x2c7b0e81, 0xc0e74fee, ++ 0x994ffbbc, 0x9df06bd9, 0xaccc845d, 0x8d69f4e1, 0xe99147b0, 0xb7588e81, ++ 0x83daf30a, 0x7e63b238, 0x7a9d5ba4, 0x8353fafd, 0x8cb8c5fd, 0x154b4d3d, ++ 0x3cb04596, 0xa21b4ae3, 0x0afa30fb, 0xb5d2443e, 0x7779e859, 0x543de3ab, ++ 0xd8e8c3c3, 0x79ec80b5, 0x05551fc9, 0x4bdfdf55, 0xf65e434f, 0x2375885c, ++ 0x185cf7fe, 0xf479c6e9, 0x1bdc73c4, 0xfce070f2, 0x51ea2c40, 0x00aaa7a0, ++ 0x369dfa4e, 0x33c235ed, 0x88ff0397, 0x906dbe89, 0x71cf1f3f, 0xffb627bf, ++ 0x7dd22e44, 0x0d7b4991, 0x8c365187, 0xf5053a5b, 0xe7a5d6e7, 0x6e498ccd, ++ 0xe40cfd26, 0xec1d5249, 0x9075483e, 0x9e9fc427, 0x27287cc4, 0x3867e666, ++ 0xbd9b836e, 0x22bce982, 0x3ee91135, 0xdb767d00, 0x11353fb1, 0x72fecf71, ++ 0xca67a679, 0xd737fa70, 0xe3028f31, 0x3cd9d4b4, 0xfd85e80a, 0xb7ca0e75, ++ 0x3d28b9d6, 0xba52a758, 0x9f84fde9, 0xeb50ffa1, 0x109478b6, 0xc49e52bd, ++ 0xd03cc3f5, 0x79af383b, 0x80e9f24c, 0x304f79bd, 0x03904792, 0xf90926df, ++ 0x1ec9eb05, 0x67f027a2, 0x67921820, 0x8ce34a8d, 0xe20a9234, 0x89ae7e7b, ++ 0xe01383da, 0x7873237b, 0x587fe07d, 0x5bf0b97e, 0x4bba77ee, 0x65be909c, ++ 0x813994f7, 0x5dd2cdbe, 0xca312f87, 0xcdefc42f, 0x25f2ddd2, 0x607a7fe8, ++ 0xd819fb3e, 0x18c0e98b, 0xdcfc2ba4, 0xd19ff38b, 0x1fc86169, 0x9f24ac30, ++ 0xfe7c86f9, 0x60174920, 0x6ba1143c, 0xb59da0a3, 0xda788032, 0x48c982cf, ++ 0x279b02f7, 0xb977e50e, 0x2dc1e393, 0xa092e9dd, 0x16a959bf, 0x3a55464d, ++ 0x037d33ce, 0x1533afd0, 0x9dfa8406, 0xd5a3699d, 0xb1db443c, 0xddbe50cf, ++ 0x26407b36, 0x09ee64c3, 0x74f3d886, 0xe503aaf6, 0x35dc7517, 0xbf5d23b0, ++ 0xcf49d04b, 0x50f8b15d, 0x4e9d75af, 0xce3002d0, 0xf2362bdc, 0x21b19b2f, ++ 0x6c476dc8, 0x33d254c2, 0xa0c3413b, 0x3af8d8fc, 0xebbd9a16, 0x02dfa49c, ++ 0x76803f87, 0x18c03eff, 0xddb9d7ea, 0x87e8cb9f, 0xd2729896, 0xc3cf3083, ++ 0x4c44a4d2, 0x425dfa5f, 0x13a7a51e, 0x1d3e907a, 0xc71538a6, 0x2d4eb8fd, ++ 0xf9780f1d, 0x8e958ea0, 0x587c7c07, 0x54f4a367, 0xd3d2839d, 0x0f4a2e75, ++ 0xe7e23943, 0xbe239408, 0xe639418e, 0xa639438f, 0x983f43ef, 0x9bb43fba, ++ 0x7de77e50, 0xcd305768, 0xd29e37bf, 0x2de27be6, 0x048e8eb8, 0x8f8c64d6, ++ 0x06c40a78, 0xfa06985a, 0x49fd2923, 0x9fb018db, 0x6914ef56, 0x293d2c1a, ++ 0xf20556fd, 0xf8cc2fef, 0xbca09ff9, 0x49e32928, 0x8ef7cc1b, 0x9396f6d3, ++ 0x6e7e2f90, 0xc47693ec, 0xa0b1fbe7, 0x990e9124, 0x9b20ddc7, 0x8c6951d3, ++ 0x59bbb224, 0x8d93e421, 0xa5ade67c, 0x25e58500, 0x64e65cc1, 0xb367d9ec, ++ 0x7d01b56e, 0xff79c797, 0xbd16f311, 0x0c74bcab, 0x40ee99e6, 0x3ecc9779, ++ 0x52d1f792, 0x7fb052ca, 0x82deec5b, 0xc07f10a4, 0x193efd2d, 0xb74cc3f5, ++ 0xc4299cc4, 0x6904df6f, 0x6f51bbe8, 0x20acbd8b, 0xc3b47009, 0x669e1329, ++ 0x9f6e4914, 0x1afcb87d, 0x579c66f5, 0x337f914b, 0xc4682e2f, 0x93b97174, ++ 0x37159ef2, 0x97fca237, 0xbed7afda, 0xe5bfda84, 0xc538d334, 0x628bd40a, ++ 0xd37a8d17, 0x7fe86401, 0xf58f1ff7, 0x3eb886bd, 0x87886de3, 0x332b997c, ++ 0x9a3a165f, 0x63b9de51, 0x1e57961b, 0xd2b92169, 0x133535e2, 0x9a5dd8a1, ++ 0xedf3e50c, 0x15401692, 0x6365f458, 0x243b9632, 0xdf36c90d, 0x0283ed3d, ++ 0x6b2f1f2c, 0x467f31f3, 0x7a40752d, 0xe73f995a, 0x985bd412, 0xa0d9a89d, ++ 0xcfc0e9dd, 0xe77e232f, 0x316bc767, 0xbe05c62a, 0xaf306a57, 0x157ab559, ++ 0x496cf1d7, 0x4aa3f602, 0xcdf2099a, 0x13fc97b7, 0x93d8a3ce, 0xcb0924c8, ++ 0xb1fa0a9d, 0x97eefd2f, 0xd7a80ea5, 0x9431219c, 0x9c81d39f, 0xf3fe71ef, ++ 0x18d562bb, 0xc5b35098, 0x9aed8a51, 0x1363922d, 0x58253de5, 0x56689f5f, ++ 0x4f7e80df, 0xf64713de, 0x3cc3f2a0, 0xde4e8bf2, 0x42ec8a33, 0xc54587e5, ++ 0x71349e98, 0xc3f2bdbf, 0x372a72ca, 0x952a00b1, 0x427f7bca, 0xfc97b6ed, ++ 0xfa0534b2, 0x93ac7f7f, 0xa9f00b74, 0x6bd10954, 0xd8499f50, 0xaa6adefe, ++ 0xffa529df, 0xbfd43cfc, 0x6f98979c, 0xa417f185, 0x2fd584c4, 0xcb0ced1f, ++ 0x511f8c57, 0xb1d884aa, 0xb0ccbcca, 0x5205edfc, 0xfa90f8e9, 0xb098a29e, ++ 0x6752d2fc, 0xfa90f8e9, 0x088e5477, 0x23bf2fcb, 0xdf3f2c33, 0x8feb8b34, ++ 0xca59563a, 0x94b2bee5, 0xd22ccdfc, 0x5e0ef943, 0x3f9418f7, 0xc7f9e504, ++ 0xef953fb9, 0xf80a7f04, 0x80bc7a52, 0xd0e380fc, 0xe20bcb0e, 0x59d31e84, ++ 0xda266bb7, 0x83e3f101, 0x8b17c85f, 0xf06efcec, 0x5f22a60b, 0xcc876ec1, ++ 0x6e1ed4bf, 0xb9639bc7, 0xbcce509f, 0x67e04e8d, 0xf9055779, 0xf5296557, ++ 0xf4860105, 0x391f6f0c, 0xcfa2506f, 0xec3887df, 0x966f4852, 0xef188e8f, ++ 0xfc9da978, 0x95dfe118, 0xb8c6568b, 0xa377774c, 0xc3ac637f, 0xeb7aff18, ++ 0xc88b9729, 0xeb5bfc2f, 0xa4bd905a, 0xfcea2934, 0x133f9037, 0x249ccf39, ++ 0x7f82af11, 0x57617e45, 0xf08bf912, 0x4fcd1293, 0x4a9ffc30, 0x50ce73d0, ++ 0x5297673d, 0xbeb94c96, 0xbdfa339e, 0x1837ff9e, 0xacf68887, 0x8df1a649, ++ 0x55df83f6, 0x9df7fa29, 0xca3e3f50, 0xfa2914f7, 0xebc3d7f7, 0x06d453cf, ++ 0x09f3c83b, 0xd23a6926, 0xa0aaa4fd, 0xc672566b, 0xd96988dd, 0xdd055ee7, ++ 0xf5e785c2, 0xf4e74c46, 0x615a4ef8, 0xcb66b7fd, 0x183fee2a, 0xbae4517e, ++ 0x7f7127d6, 0x3515c4e4, 0x66f2854e, 0xb8c38d5d, 0x3509f9a3, 0x66abe30e, ++ 0x38c72b37, 0xb4ce3dd2, 0x7710e301, 0xff90a42e, 0xf7d71249, 0x48ded15e, ++ 0x2f5eca0f, 0x5b6adfea, 0x93e8d7f0, 0xb7ed5cd4, 0xa04e2e20, 0xdc3797bf, ++ 0xf8a13bdf, 0x89de38ec, 0x4f767c27, 0x51bf3e88, 0x6083cf7f, 0x9538819a, ++ 0xa4faa13c, 0x09e316c4, 0x0e651fd5, 0x1a7e5867, 0x6ed03ffa, 0x58446ba1, ++ 0xccd55bbb, 0xc7e07ab0, 0xd43fa366, 0x0ad96160, 0xac5353ea, 0x245e7e86, ++ 0xeb10bf1d, 0x740eecd7, 0x453998a3, 0xec51bd95, 0xe9c25693, 0xc9fdf917, ++ 0x25cf1e24, 0x1cf5f327, 0x6bf3e24b, 0x99dc3d94, 0xf119ff03, 0x58879910, ++ 0x07f60575, 0x7710bb3d, 0x32e99c5a, 0xe76ce0b8, 0x2ab71573, 0xba6d6780, ++ 0x41c61fe9, 0xde73d0fe, 0x07f0155b, 0xb7a639b4, 0xdeff20b3, 0xf9792b73, ++ 0x66e9a64d, 0xd57fb18d, 0x0a5add57, 0xcf148af9, 0x7d7f106f, 0x0956fb66, ++ 0x926280f4, 0x50ca7e58, 0x0594fc5c, 0x16302aec, 0x0276e640, 0x3cace3ed, ++ 0x0189ae8e, 0x8bf587fd, 0xabd22add, 0x73e0c626, 0x3bed0d30, 0xd8466f7b, ++ 0x059c5c7e, 0x32fb41da, 0x715ff79b, 0x205b6abc, 0xf47d0541, 0x74b281e8, ++ 0x24b1c5c4, 0xf73fad07, 0xd42e39ed, 0x37af3053, 0x1fff5711, 0xe38075e7, ++ 0x8d5e7c38, 0x4f4e3e66, 0xda096e73, 0xc0b1dcdf, 0x5f88690e, 0xdf4a8af9, ++ 0x1580fc63, 0x2eddcff2, 0x706c6fdc, 0xd7f4345a, 0x535e218f, 0x106d3c6f, ++ 0x1c7216fb, 0x689c8dc7, 0xd217b0da, 0x7cbc0adf, 0xe2a6e388, 0x4b19fd38, ++ 0xd1cc0f00, 0x0a74b19f, 0x641e23cf, 0xfd1fbf39, 0xc49ffeee, 0x8f2f146b, ++ 0x17e2ffee, 0xbef4ff90, 0xc2ed0d5c, 0x9f4e58b9, 0x86acbe15, 0x59a7e420, ++ 0x9f70637d, 0x3dec9fd1, 0xc7bfeb8b, 0x78409bea, 0xc7886fb3, 0xa33725fe, ++ 0xf388c478, 0x2d539e20, 0xfffb86e3, 0x3665c7c3, 0xb35df3a4, 0x718d9d38, ++ 0xb436a681, 0xf2169f3f, 0x603cc6ef, 0x7c716ffc, 0xf3833e63, 0x641da360, ++ 0x5fdf180f, 0x43f115ea, 0xfbe76c99, 0xd137bfb3, 0x0a2d4abe, 0x3edfe421, ++ 0xcf38a26f, 0x602ddfd8, 0x1f599c7c, 0xb269926c, 0x14cefc3a, 0xa4d8295b, ++ 0xf6e28ab5, 0x444add19, 0x3b26ed5c, 0xbfb44739, 0x625bcbb9, 0xf0b3f4c7, ++ 0x7c44737a, 0x327cc85e, 0x82b34fc6, 0xb7ade511, 0xcffd837d, 0xddfe18b9, ++ 0xdcec2c92, 0x74323648, 0x88a363ff, 0x664e0687, 0x155e2225, 0xa0640188, ++ 0x599545bf, 0xfe90d261, 0x7a83a968, 0x3693d456, 0x719ca74a, 0xb4e3883c, ++ 0x27b001d6, 0x5174bea1, 0x94d5c86a, 0x3601ec33, 0x811c6435, 0x038e837f, ++ 0x4e3a719f, 0xa6ff660b, 0x2ee6f208, 0x43a9f333, 0xe82d9874, 0xc5196105, ++ 0xed170375, 0x1e669764, 0xbca3265f, 0xa6265d5a, 0x462fac86, 0x886a658d, ++ 0x4ecb8d9e, 0x82cbcb0a, 0xe1318d8f, 0x3174c7fe, 0x3236bc4e, 0x0fc33fac, ++ 0x3079f831, 0xfa174169, 0x6bedd327, 0x2c491fc8, 0xbfeb0acc, 0xbd3864e0, ++ 0x8dc799f3, 0x39f6af71, 0xe67eff23, 0xefcc2519, 0x276c0c28, 0x1e7e147c, ++ 0xf9f67dfe, 0x64dcfcf0, 0xc9156fb1, 0x93d1ebb7, 0x514dfd4d, 0x4f4fdfca, ++ 0x9e9c3ba7, 0xf4e1e5c9, 0xd384f54c, 0x38457d33, 0xc37846bd, 0xcd6a31e9, ++ 0x31f2b0e4, 0xf2c3f21b, 0x3b367f63, 0x18267eac, 0xb8fcd0c2, 0xf56115ad, ++ 0x1a5f6c27, 0xf2f49f96, 0x73f5613d, 0xcac2ab7c, 0xfbae7773, 0xc53ff8bb, ++ 0x3eac31bf, 0x57f4d992, 0xeb537ff8, 0xfde361e3, 0x9ffff157, 0x8b76e422, ++ 0x604edbd0, 0x1987ee2b, 0x0ddd0af6, 0xb6ce97d4, 0x3f715763, 0x69562f46, ++ 0x60af4a1f, 0xbd94035a, 0xd4247b20, 0xd480a36f, 0x8d1bd026, 0xf506b626, ++ 0x264daffe, 0xe4349fda, 0xf732477c, 0xf3247633, 0x29b3acfd, 0xd3ce225a, ++ 0x4ce7a7d0, 0x7ea03fdb, 0x1bea6c13, 0x814c7f64, 0x730e305b, 0x579fb4a9, ++ 0xe2a85092, 0x523caa3e, 0x70133c5b, 0x33293968, 0xe1ac8930, 0x201ff3e4, ++ 0x6ddb2e3d, 0x4e54e22a, 0xb768eaf2, 0x37fe5d60, 0xec057920, 0x6353da2b, ++ 0xe9d69f1e, 0x325e30ab, 0x1b5c2bf2, 0x15fd6336, 0x809fcdf7, 0xf7e0ec71, ++ 0x9557eafb, 0x742bd086, 0xf8a34b5d, 0xdcc94d47, 0xb9eb19ae, 0x0436aac7, ++ 0x64d3de61, 0x2ec1ffae, 0xbac32534, 0x984f49cf, 0x9ba59fb9, 0x3b02cfd1, ++ 0x4e01e749, 0x4237a870, 0x8f64389a, 0xa2006bd4, 0x1bdf1673, 0x4e5d212f, ++ 0xc3c61ac8, 0x6109c5bf, 0x646aa11c, 0xf436efff, 0x3a26aaac, 0x6035e643, ++ 0x0757f70f, 0x7a471a1e, 0xa0fdecf8, 0x67af0164, 0x463d7c2d, 0x0f428bfd, ++ 0x70f4277f, 0x90dfea0f, 0x3b35e87d, 0x3f478f9e, 0xf7366cfb, 0x67ef8dab, ++ 0xc639f992, 0x57ee6499, 0xd98ced57, 0xaf043e70, 0x58677ed5, 0xc475b6be, ++ 0xca7dd086, 0x5e3d632a, 0xacf5c149, 0xdd537217, 0x87b84c15, 0x1a7e5f91, ++ 0xe3b356e9, 0xb1fbfdf2, 0x8d3fa9bd, 0xc69d53db, 0x4653ebbb, 0x7f5dfdfe, ++ 0xe9fe6166, 0x9a66c9d7, 0x2f38d7d7, 0xe2439748, 0x072c1c00, 0xf4c4ef1b, ++ 0x9402d158, 0x901ef837, 0x8bb8bf20, 0x2d5f5199, 0x919a66f1, 0xf699a7f8, ++ 0x5a583ef1, 0xed4ab26f, 0x3a1e60ef, 0xfee4fea7, 0x37ac78ea, 0x0fd19fd8, ++ 0x6ffa0008, 0x73753a9f, 0xccdfee1a, 0x807fc895, 0xddf86cf1, 0xcda8df73, ++ 0xf18d7768, 0x4bde613e, 0x963e031f, 0x35fa8d32, 0xdc7867fa, 0xcf87a212, ++ 0xf7005859, 0x5673f473, 0x9f301bdf, 0x01c7e88d, 0xa7b6361e, 0xb7d07f93, ++ 0xbf763fee, 0x181ef504, 0xfe831c15, 0x7f75b9cc, 0xbab8889e, 0xa99965fb, ++ 0x9c4f1f80, 0x3f48cff7, 0x1f672e83, 0xe58f1cba, 0xae1097e0, 0x86ab2ed8, ++ 0xdd6e7272, 0x7ea189ae, 0x3e6539bf, 0xa2e7414b, 0x39ea3930, 0xb97c6445, ++ 0xe7fbe2ce, 0x4eee51c7, 0x033fa998, 0x3e056b9f, 0xe9aa6637, 0x18dcf8a1, ++ 0xf24f883f, 0x21be374f, 0xd8d95e93, 0x3ee7431e, 0xd45c0b1f, 0xd6fabaee, ++ 0xb8662ae3, 0xe035f85f, 0xfe5c0554, 0x82aa701e, 0xe00df05f, 0x655bf314, ++ 0xf7ce3a4f, 0x4ebfa7eb, 0x8ef8b8a0, 0x9f779b1b, 0xbdc9ffd4, 0x5ce3df48, ++ 0xc0d806be, 0x5af76427, 0x83f45472, 0xfd5ff64b, 0x4d43f504, 0x65f6958b, ++ 0x4783392f, 0x07fac15f, 0x6bf58624, 0xcca43102, 0x1f245a6b, 0x6bad67ee, ++ 0x1465bbdd, 0x2d35d7e4, 0xd6984029, 0x63d23026, 0x0f92cd35, 0xd42eb7f7, ++ 0xee7855e9, 0xeaf07250, 0xf7b7ec05, 0x62f7ef20, 0xc620fe9d, 0x2bcdbd8b, ++ 0xd6fec0bf, 0x0c5958b7, 0xb019cfe2, 0xf6f1c28c, 0x6f1c7e4a, 0x0b59ff8d, ++ 0xf5e6bff6, 0x0dd1e325, 0xbf59daac, 0xa87f742a, 0x8b29ff77, 0xd35a740a, ++ 0x5102ecf2, 0x779b80af, 0xe9b9d85f, 0x83fd5f5a, 0x7822f1a1, 0x399f4cb3, ++ 0x03e36f74, 0x6d15ff41, 0x9c901ae3, 0xbdf6c7a0, 0x2b1e9122, 0xd63d414b, ++ 0xbd7ffbb1, 0xf81de38b, 0x3710139f, 0xe8c6e0ac, 0xf93a3ccd, 0x1c62350d, ++ 0x05b4f176, 0x169ac1e3, 0xe76885f3, 0xcf14be41, 0x88cf1c52, 0xe8fd2367, ++ 0x8c4b40ad, 0x58ccf45b, 0xded90f92, 0xf309596f, 0x805615f9, 0x7e8e28f9, ++ 0x6fc82acb, 0xb2f5124d, 0x7168be6c, 0x0a292bf0, 0xc596c7d1, 0xcb239fcf, ++ 0x87e5165f, 0xe0b3beb3, 0x7a8d5bfe, 0xadb882d1, 0xcfcb7c09, 0x5cbf5beb, ++ 0xeed28ee0, 0xf76e14a5, 0x9acf26cc, 0xf243051d, 0x14da51b1, 0xf1b5bb44, ++ 0x275524c0, 0x9a41eb3e, 0x1518bedf, 0xffb251d7, 0x90c199db, 0x7c07befe, ++ 0x91bf7ee0, 0xe5f3d9af, 0xedd23354, 0x2aa72fed, 0x7bdf43f1, 0xa26becd3, ++ 0x94bc97ed, 0xe6eeedc2, 0x1c45cf04, 0x55bf7ab7, 0x8ef844dd, 0xef8802d1, ++ 0xdf3a38b6, 0x365b7c00, 0xfbe28415, 0x4d779a6e, 0xbda1ac9b, 0xe25d69ad, ++ 0xf1faa7ad, 0x6e41b21a, 0xce23af9d, 0xf0878764, 0xe302fec8, 0x3ae714cd, ++ 0xa6e68fa0, 0xb9469f78, 0xaafaec54, 0x1a8afdd0, 0xcf033053, 0xbd9ab619, ++ 0xc887e7db, 0xd5d76c9f, 0xa5cf784d, 0xd5935935, 0x4d99fe21, 0x6abd2f9c, ++ 0xed092130, 0x9271d826, 0x09b7c097, 0xad2dff48, 0xee50da0f, 0x70714fef, ++ 0x15745a3e, 0xc6ee67f7, 0xab7bac3c, 0xe506b3c5, 0x2c5a6b6a, 0xdf476f8f, ++ 0x2f59bed8, 0x3c04ebca, 0xfed2f407, 0x5bc0af45, 0xfa4618ef, 0xccd0ee97, ++ 0xad3722c2, 0x0ebcc6d7, 0x5adb57ac, 0xf76a155f, 0xa5dc0f7a, 0xb1ccfce1, ++ 0xe34b3dbc, 0xf71c8d78, 0xf90ce208, 0x7db55a64, 0x8fdd887e, 0xd45877ac, ++ 0x14c0e833, 0x6051f69d, 0xfc347768, 0xfc5291de, 0xe6d1ca2e, 0xea364f24, ++ 0x86270561, 0x512d5478, 0x3bf501e7, 0xfd466f91, 0x168e823d, 0x7481d7b3, ++ 0xcde4537d, 0x19d10f16, 0x39455b04, 0x965f5c1e, 0x7d9caa25, 0x35bde621, ++ 0x91ef9c33, 0xf2173ef5, 0xaee93666, 0x0ecf3855, 0x4fa6e499, 0x1bfe27ed, ++ 0x5702faf5, 0x2edbff39, 0x5cf78edf, 0x272e66b6, 0x6ff77e7c, 0x4872f939, ++ 0xe294e6bf, 0xf7feb873, 0x9ab63e05, 0xfbce1775, 0x2a3ac468, 0x94c13c52, ++ 0x36247d90, 0x7086e53a, 0xa4fc44c2, 0xf1077b09, 0xf5bbed13, 0xafba58b1, ++ 0x09c457b5, 0x4e10f30a, 0x92a698e2, 0xef66e31f, 0x868c3de3, 0x06db134e, ++ 0x14dc04d9, 0x4b27390a, 0x90464d90, 0x2841b6e5, 0x58b6c78c, 0x3617c7fe, ++ 0xf9e23457, 0xee65d33f, 0x13ef850f, 0x96e4b730, 0xde07f742, 0xfb63775b, ++ 0x1b7aaf03, 0xf723ce50, 0x4c056607, 0x37892d2b, 0x5ef04fb0, 0x827dd445, ++ 0x78f0d4b8, 0xd2aa99d3, 0x1cd9fce4, 0xac40fe87, 0xb13bef8f, 0xd3e388e9, ++ 0x7f285348, 0x8b53c5d7, 0x736d9bd4, 0xfc5fa902, 0x45adb6d5, 0x39e36720, ++ 0x80df301d, 0x7f720e60, 0xe1df7063, 0xefe4c9bd, 0x29923e82, 0xb98876de, ++ 0x00aff044, 0xac1e24fc, 0x16fb6169, 0x263fa381, 0x9dddfea0, 0xfc887ea4, ++ 0xd32e3fe9, 0x25188dbd, 0x91467168, 0x3fe8fdaf, 0x6f723f83, 0xb6b3d72a, ++ 0x67ce7e56, 0xed0cdd53, 0x31c38c7c, 0xb3910e4d, 0x37ee54c4, 0x973d1f57, ++ 0xf27f0161, 0x4264e992, 0x7ebff41e, 0x6e02735f, 0xfd9d5583, 0x955e2668, ++ 0x4ef147b9, 0xdf7a854f, 0xda263b49, 0xeadc3fd0, 0xf1f48a9b, 0x3ee8b207, ++ 0xe98514e3, 0xf9f0fe4a, 0x8b0cbed4, 0xf35c9302, 0x53a53272, 0x46afa6da, ++ 0xc036b53f, 0x98638bd7, 0xb4e60541, 0x6def944a, 0xfec2486d, 0x7dbdff6a, ++ 0x5da9ea24, 0xf67f7ca9, 0xbcb92bcd, 0xac14c2bd, 0x14ea9e5f, 0x7099f778, ++ 0xd8976ebf, 0x22bdebe7, 0xfc633d53, 0x65f3ad29, 0x2f20e007, 0xed10fdb0, ++ 0xc959b62b, 0x9d798a9f, 0xc5b47a71, 0x6d5479d0, 0xf68642c7, 0x34c9cfa8, ++ 0xc777ca09, 0xd3ff93f6, 0xf1556edf, 0xb1c633fc, 0xefbca19d, 0x72a7f716, ++ 0xf6cdb000, 0x78c6efa1, 0xc1bf6d31, 0x05c4393d, 0x28c6c39d, 0x7b5cd9db, ++ 0x89e3bd28, 0xee716bde, 0xc04e38a9, 0xfd12e784, 0xa35f3ba0, 0x93cd0d79, ++ 0x3cc6b8d1, 0xefcf4873, 0xf85ff4b6, 0xcbcd0a45, 0x61c83881, 0x6dac9e7c, ++ 0x31abc512, 0x23ad370e, 0xba6aa1c6, 0xb55e7c34, 0x0301c153, 0x26f5f9f9, ++ 0x28cf2836, 0x43b1b5df, 0xc2c81b79, 0xe4262cee, 0xd2b6e0ff, 0x283cd0a2, ++ 0xf6a1c29a, 0x6db17cbf, 0xed11635b, 0xf032e9ab, 0xf8d20e3f, 0x97275c24, ++ 0x7709102b, 0x03a73e6a, 0xb38ba3de, 0xfac1f2f1, 0xe63b7380, 0x669ebced, ++ 0x6455c475, 0x79d0bc92, 0x3d9fe19c, 0xdc2e052a, 0x79edac02, 0x079893d6, ++ 0x1d31eaeb, 0xea09ac7a, 0x3fd2bf7d, 0x4ef90031, 0xc449f7ab, 0xaf9f3be7, ++ 0xea0a6a7a, 0xad66dddd, 0x504ff512, 0xe0fc8e7f, 0xb6eacd37, 0xa363b910, ++ 0x9ee8d3fb, 0xb538c45e, 0x873d3767, 0x01df6e7e, 0xe7f3c549, 0x067f733e, ++ 0xeda6bbce, 0xf5ea0b1b, 0x925f03da, 0xe6939b5f, 0xf815317d, 0x4f5ad857, ++ 0xb166cdf7, 0x2cdf74ed, 0x7e07f857, 0x0327d717, 0x56be2667, 0x7787c21f, ++ 0x7eb1bc85, 0x53b458ef, 0x3b5e426d, 0x7485de30, 0xe3dde75f, 0x227dffb0, ++ 0xd5da371e, 0x90a343b3, 0x7bd89bee, 0x1dda0e94, 0x7df7429f, 0x3db13f73, ++ 0xbfa90ee0, 0xbeffc84f, 0x2df7ee54, 0xc2eef34a, 0x7e7556f9, 0x78abc165, ++ 0x19fde7b5, 0x21fa5f18, 0xd144772e, 0x1bf28323, 0x4ab54f21, 0xd7eb05bf, ++ 0x57a4645e, 0x898ddf80, 0x9f5dbfc0, 0x095e4eb4, 0x4f01f7df, 0x385fd112, ++ 0x7dc4e3cb, 0xac28cf66, 0x0ff1ff5f, 0xfd8f5153, 0xfc049c0f, 0xaaf687ef, ++ 0xc03748b1, 0xca2c717f, 0x7a465ed9, 0x3cd390cd, 0x9f685394, 0xc02ff887, ++ 0xe5e90e7c, 0x0aee96dd, 0x267dcb92, 0xf8097286, 0xfc007927, 0xe72ed03b, ++ 0xa81e4039, 0xf39224fd, 0x3726dddd, 0xd7a0b3f9, 0x78be5027, 0x7777e619, ++ 0xce483a97, 0x1f3edcf1, 0x887035e5, 0x8633f1fa, 0xc4814c6e, 0x12fba13c, ++ 0xc409a989, 0x8e5f4337, 0xcfebf211, 0x58351356, 0x872c9c47, 0xbd8847c9, ++ 0x4f6179e4, 0x6d2ed3b3, 0x7e34617b, 0x84edc69e, 0x7549d843, 0x7ffde91a, ++ 0xe36ab610, 0x9b8bd991, 0x40ff2fd0, 0xb10ef2a6, 0x3810122f, 0x45f62439, ++ 0xc9a86ed0, 0x7e2dbefc, 0xbc79019f, 0xbdd33d8f, 0x51cd04a1, 0xc3f6f961, ++ 0xf8f6ce98, 0x2c65d04b, 0xd87dd15a, 0x173cc5cc, 0xe872d7f1, 0xbfbc5cd6, ++ 0xc79677d6, 0xf63f2d79, 0xd026f17f, 0xa00eb1e1, 0x053b147f, 0x81fc21cb, ++ 0xb98a359f, 0x49f79786, 0xd7e88f42, 0xbd8f102a, 0x1e50f22d, 0xc0035226, ++ 0x5e5ffcc6, 0x74dbdffc, 0xe6953fc8, 0xf09086be, 0xa1af7ba7, 0xfa9df6fc, ++ 0x72c50d31, 0x28af99df, 0xb8b16e7e, 0x2d3f1173, 0x46721059, 0xa9f7e9c1, ++ 0x8143e266, 0x173d4595, 0xe5c6971c, 0x9ecea260, 0x963e2892, 0x9f8c3e1d, ++ 0x05b7645b, 0x4c8ba0fc, 0xf5073e5f, 0x7d2fd88d, 0x371f8998, 0x1e7f02fc, ++ 0xd187d911, 0xf5bb016f, 0xe7910bc8, 0x5bf26eee, 0xc622fd8c, 0x5f109836, ++ 0xf624dbab, 0x6b1681df, 0xbfaf0d5e, 0x5f2bdc5e, 0xe8e3badb, 0xbaebe028, ++ 0xd1ca23d7, 0x0573a16f, 0xeba3c53f, 0xffcfc29b, 0xff09a5c7, 0x871b1c65, ++ 0x8ae00bfe, 0x615984f4, 0xf1c0565d, 0x075ee947, 0x899771d2, 0x2bf40bd3, ++ 0xf843a7c9, 0xb98bbb31, 0xc4bfea5e, 0xce4f5ee8, 0xbc61ff4e, 0x29bb333f, ++ 0x6631c353, 0x767cbc2b, 0xf73f266b, 0x9e327c51, 0xbdba17fb, 0xd6bfc80b, ++ 0x7ef067dd, 0x2fa11ac6, 0x717e0399, 0x7eac457f, 0xd6eff08d, 0x55ef22fa, ++ 0x8ad53a72, 0xaf98b37a, 0xbd5dc701, 0xaa0fdf93, 0xbf5e19da, 0xfd69d056, ++ 0xe28ea7cb, 0x3fb55cb6, 0xa9d05ca2, 0xdee235b6, 0x959cef07, 0x657d89a7, ++ 0x46fc1f71, 0x6f7c27ef, 0x47c6fee6, 0x7ca31fa2, 0x57df1a6d, 0x206581ad, ++ 0x64fbd77f, 0x8d68e21f, 0xbf7027a4, 0xc257d997, 0x60341efa, 0x3eb3ee20, ++ 0xa0f4e824, 0x1fad0fc0, 0xcabf57da, 0xf43c23df, 0xd7fcf874, 0x14658f31, ++ 0xe5a47f7c, 0xdfdc16a7, 0x9adbc48b, 0xbff93326, 0x227d04eb, 0x106eb5f1, ++ 0x682ddb3f, 0x55f122df, 0x33ae95e3, 0xffb7ee7f, 0xe0dfcedf, 0x4dd13af3, ++ 0xfb403995, 0x4a2f5544, 0x7f5eae9a, 0x11eb835d, 0xd77bfbeb, 0x8b90c5b5, ++ 0xf1326cc9, 0x06f93cbb, 0x7f70a5e3, 0xcb85af7b, 0xf7c280cd, 0x453c0db1, ++ 0xfc205fb6, 0x732f85f5, 0xeb52f5bf, 0x97dc04e5, 0x481eebee, 0xca9a9460, ++ 0x7e623ed1, 0x7a5e887c, 0x93c78d29, 0xff5f5c5b, 0x85f9fd1a, 0xde1acd7b, ++ 0xc63f5aef, 0xbe3b41ec, 0xb491cc7e, 0xe77621f1, 0xe17f5155, 0xc53787de, ++ 0xbfc47ee0, 0x658a1a49, 0x1e3fdb5f, 0x24debcc2, 0xfda01369, 0xdf81eed1, ++ 0x6aeebde2, 0xec4cdc57, 0x2cbdb6af, 0x8fe43777, 0x0b5d36be, 0x268f3f8d, ++ 0x1c2df5f1, 0xdabb2663, 0x5fee3233, 0xd0bf712a, 0xbbe483bd, 0x16dbe0e7, ++ 0x5bbfb7ba, 0xe8182e62, 0x5bf0eba8, 0x67bbd03a, 0x3a0b29ff, 0xa72d25eb, ++ 0xe2bfc12c, 0x70825c2f, 0xa9fb402c, 0x2f742ddb, 0x2defdf71, 0xf3525e78, ++ 0x4fb497fa, 0x7cfd0eb5, 0x955ec7f4, 0xe1cf1de9, 0x882c77f6, 0x89269aa7, ++ 0x968667a5, 0xf51ca99b, 0x69bfe620, 0xc0d4fae2, 0x4b812ae9, 0x6e06a703, ++ 0xf3fd0957, 0xb8e8d6e0, 0x23d4f434, 0x2465bdcc, 0xd370f7f4, 0xf35fba4a, ++ 0xfaf0f6f0, 0xbcce31ab, 0x5c73eb09, 0xbc397eae, 0x1e20ed7c, 0x91d3d275, ++ 0x4333eefa, 0x1cb0e4ff, 0x6040e3c4, 0x700558d5, 0x75a9c3ff, 0x73945963, ++ 0xbec2939b, 0x7af5f61b, 0xbd6dedf4, 0x58bb416c, 0xf14cda3b, 0x3fe8ed45, ++ 0xf2f14259, 0x82cbc095, 0x9f103fb6, 0xe93adb2a, 0xe622e87e, 0x5e748f5d, ++ 0x40e716d4, 0xc832b97f, 0xcda2b8e5, 0x3849f3ea, 0xc3d9133f, 0x88dfcc45, ++ 0xe0ebe838, 0x83f42cef, 0x4c4df912, 0x82d5b7e8, 0x9d05abee, 0x363c4357, ++ 0x8889ef0a, 0xc446bc78, 0x77b36bdd, 0x15abc51c, 0xfd7ca235, 0x4809c3f1, ++ 0xf5c60ae7, 0xeb9f854f, 0x867f831f, 0x7b94893d, 0x23f754b0, 0xacdaabff, ++ 0x36fb5f74, 0x6b6e7fa1, 0x0d23fd02, 0x237d03d7, 0xf9bdf8e2, 0x91de7c7d, ++ 0x25a6b3f6, 0x5a6f7ebc, 0x406bd12a, 0xe989c1f8, 0xbe088f42, 0xb8b3f655, ++ 0x42afe83c, 0xb51f3595, 0xfc7056ea, 0x4780a9ae, 0x1d4bbfe8, 0x9eed1897, ++ 0x56fe9192, 0x7e46f7f8, 0x418bee31, 0xbb63bf7d, 0x7f7e343d, 0x97db9d3c, ++ 0x1d64b375, 0xef1210f9, 0x8ccfce2c, 0x4c4cef1a, 0xa32e7bc7, 0x5a7a7c1f, ++ 0xdee3bc68, 0xf8f11131, 0x95f3d72b, 0xb6a7bf78, 0xde97eb89, 0x1137e842, ++ 0xfe4677fd, 0xd5936d70, 0x2d497187, 0x65de89e0, 0x5e505e21, 0xc232a4db, ++ 0x3f379a4b, 0xb7bd067d, 0xd5bde334, 0xa760ad25, 0xa525fba1, 0x1dfc207f, ++ 0x0dd7cf1f, 0x168f4b74, 0x4371183f, 0x9fee15cd, 0x946bdf1a, 0x350fc520, ++ 0x729efc6d, 0x19aba1cb, 0xbedf3099, 0x58c8fff6, 0xe9c3e909, 0x296b5fdc, ++ 0xf7857ff6, 0x6dd87e6c, 0x0e87ea8b, 0x91a971ea, 0x1cc6a5e4, 0xe4ff234c, ++ 0x3783f800, 0xd1f1bc43, 0xb46f1477, 0x00798a1c, 0x577bc3f7, 0xfe3ac779, ++ 0xd9ea9f0a, 0x3767f226, 0xd14a46b1, 0xfff509cf, 0xbdf83b56, 0x1d84479d, ++ 0x8013fcc4, 0xeea047eb, 0xfae1fcbc, 0xd537d0c1, 0x996bd702, 0x348e65be, ++ 0x0b544f5c, 0xdbcaa9b9, 0x91df4741, 0x90b5507e, 0xc9fcf027, 0x41fa45ee, ++ 0xeb87a78f, 0x628ffa99, 0x3bedcfc9, 0x4f703b2e, 0xcffbe818, 0x03dfd123, ++ 0xca2b3eff, 0x0277e83e, 0xbce23d9f, 0x2650beb5, 0xf16699fa, 0x809bf0d4, ++ 0xbe9b848e, 0xc61f7653, 0xef1db909, 0xaa0e2164, 0x50bd4276, 0x7a3e03f9, ++ 0x8f94fee9, 0xe3f92bef, 0x28c74ce8, 0xcef1d5df, 0xfd5bc464, 0xe44e3f47, ++ 0xd13ab9fc, 0xf9fd7292, 0xf124a919, 0xf124d7f8, 0x129f77f8, 0xabb8c04c, ++ 0x09ec80f6, 0xf06ec7bd, 0x238129fb, 0xff38f0a6, 0xe6957499, 0xf1c6df53, ++ 0x29e76a61, 0xef9cbf8c, 0xfc6998f3, 0x80c5e561, 0xef62bf9b, 0x300bce18, ++ 0x27ee6b50, 0x329ed5fc, 0x4f6a7cd1, 0xda85a40d, 0x4dfb1d7d, 0xbf57fd47, ++ 0x893e919e, 0x6f77a863, 0x908177c3, 0x18b3edbf, 0x668ea7f2, 0xfa49553d, ++ 0xa8664b2b, 0x68fb1ebf, 0x7b50a4dd, 0xcfce9c91, 0xc1d219b7, 0x0bcc5e85, ++ 0x87417c7c, 0xd8a96c4d, 0x7e78e027, 0x103fc441, 0x8f4aed5f, 0xa8dd5f12, ++ 0x6edf5c5f, 0x5c8fb865, 0xf74ace7b, 0x5f687e70, 0xbb3bf14d, 0xfa849de2, ++ 0x37bd7986, 0xc758fa61, 0xfdf849ea, 0x37b58e87, 0xb4a7bed1, 0xe99ecc29, ++ 0xfa173f38, 0xe1a71f4b, 0xf6ea98bb, 0x611ee98f, 0xe699bb75, 0x7b50f98f, ++ 0xedce96d6, 0x0c675f59, 0x2c486fed, 0x8d80e38b, 0x7d77eb0f, 0x2ff211cb, ++ 0x61cab7d6, 0x768c1aef, 0x7ef9d327, 0x0381b77f, 0x3e26e4bf, 0xfae9e5ef, ++ 0x3e69b7d6, 0xf13f6655, 0xccc9beb1, 0x14f377cb, 0xa76a4efc, 0xe71d24b3, ++ 0xbff717bf, 0xed08b9f9, 0x924d4073, 0x1cec818f, 0x7887be1f, 0x5d013f1f, ++ 0xc6267c07, 0x3ce95bbf, 0x1c6ba1b9, 0xe819b7bd, 0x9a253b7a, 0xe78938dd, ++ 0x13950028, 0x890e3c99, 0xc5d67f2c, 0x9c4e1ff7, 0xc4ecfae5, 0x68a4ef7c, ++ 0xc5674d7a, 0x04974e3c, 0xbbf85bbd, 0xcf7ac8f0, 0x8e76fe88, 0x7ae04fd6, ++ 0xd0c6f67a, 0x938f5c79, 0x3496a7ef, 0xddf0571f, 0x348b5546, 0x5548ed03, ++ 0xaef4a7f6, 0xa805f203, 0x0702aad7, 0xbab1dce8, 0x7702ef69, 0xefdc7994, ++ 0xc2ad76e2, 0x333cfd12, 0x79f1c5c3, 0x22a9699a, 0x04ca7a8e, 0x34ae9de3, ++ 0x2cfbf83b, 0x76f33efe, 0x2d9787a1, 0x729f9332, 0x7e66a99a, 0x17cfc16e, ++ 0x7b3d0b16, 0x91cfd0bb, 0x7d0d86ef, 0x67e8a77c, 0x336cabc9, 0xbe442f9e, ++ 0xf853be23, 0x9b994b7b, 0xff7c8ffa, 0xfbf0a77d, 0x404eff22, 0xe1e84b9a, ++ 0xea226c89, 0x07d83f61, 0x9cc6fbe4, 0xb7b3b218, 0xd510994d, 0xd4f7c04f, ++ 0x8d4f78aa, 0xfaffc1a9, 0x7ec94f9c, 0xfb3ce89d, 0x3fc3dd16, 0xa2b2c31b, ++ 0xd90d8f9c, 0xefee432f, 0xe7177ce0, 0x3e0ed50d, 0x97ff8347, 0xdd0a3220, ++ 0x3ff832d7, 0x3fe1f04b, 0x9b266f7d, 0x20fba129, 0x2cef6507, 0xffde2a57, ++ 0x1aff21ed, 0x0bf64056, 0xd62195d6, 0xb10d6195, 0xac46974b, 0xa1e38a8c, ++ 0x5ce925f5, 0xda50a7ff, 0xf9256399, 0xf44bf6ab, 0xc03aae3e, 0x0efab1e5, ++ 0x2709f689, 0x7dd274b6, 0x92a5e585, 0xec6ae6e6, 0xc0cfce0c, 0xb71b62d1, ++ 0x065e06e7, 0x847025e9, 0x6fdf68e5, 0x123df617, 0xf758934f, 0x2effec02, ++ 0x3de1a4b7, 0x68e2ebc4, 0xa823b4c5, 0x2387afae, 0xf519a5c0, 0x5e9e2466, ++ 0x22577972, 0x5c7e20fd, 0x3ffa053e, 0x064df391, 0x3ae6a7e2, 0x9084f472, ++ 0xfd769db3, 0xf5ffda04, 0xbd5ce2cd, 0x8835a739, 0xe462e974, 0xbb38f607, ++ 0xfee46cb7, 0x57ab9d31, 0xbee86207, 0x1c5b7564, 0x6eaaafbd, 0x8c9d8fa9, ++ 0xac9b6471, 0xb2be41c5, 0xc62954e5, 0xfc0595ef, 0xa58d479e, 0xb9d0fc9f, ++ 0x5cc7de29, 0x7afdf033, 0xba79d87d, 0xe1ebcf31, 0x3dcf523d, 0xea56be83, ++ 0x79fe9d7f, 0xe365d046, 0x9369cbf1, 0x7aa31e19, 0xf779c69f, 0x82d3791d, ++ 0x276a054f, 0xaf00b3bf, 0x52e33d56, 0xa6a2dea9, 0xc6dc46ce, 0x45ffe635, ++ 0xefbf83ba, 0x9346fb30, 0x6377997f, 0x0fea4bf7, 0xfe8a9b1c, 0xf1e76f74, ++ 0x9c1096a9, 0x7d046cf7, 0xf57f851d, 0x57e424cc, 0x969254a1, 0xcb877f0a, ++ 0xe1fb6d73, 0xe85fdc34, 0xc3ce3941, 0xb404e3f4, 0x4f7bd593, 0xbf404c27, ++ 0x8d4f1f63, 0xc9b52efe, 0xc1298f54, 0x87c67789, 0xcd336fce, 0xf79f92ef, ++ 0xe27058c3, 0xe5a129b2, 0xf5afff0d, 0x77a441c0, 0xa6182db5, 0x413a0c07, ++ 0x5cef4f74, 0x9d2b0ef5, 0x4b79e3d3, 0x4facfde8, 0x866eff04, 0x75e507a0, ++ 0x8f339e16, 0x614cd743, 0x615e61f7, 0xcf092501, 0xbf320383, 0xf49a36b7, ++ 0xfe314cfc, 0x13a04acd, 0x12ceb5ef, 0x59b393e7, 0xc79bd537, 0x337529fa, ++ 0x2dd3bd07, 0x85a51a66, 0x186dc0b6, 0xfdf9e5fe, 0x9024fef4, 0xd82f38a6, ++ 0x28e07bc4, 0x9ba21efc, 0xf4182ec2, 0x8b1cf190, 0x5c8c07df, 0x1eb19f4f, ++ 0xe83fd737, 0xd6bde05a, 0xf3a7e642, 0x282cb9f3, 0xafa3d1ce, 0x6fc40e63, ++ 0x17366e78, 0xa25899dc, 0x17ea8f87, 0x68e47ae1, 0x46de09eb, 0x0ea5666c, ++ 0x48149f9c, 0xbb8b5d33, 0xe1f475f1, 0x67dc472d, 0xf7bfb07e, 0xe7430517, ++ 0xb1db5a8e, 0xae1ef0cf, 0x3dd376e4, 0x35df0d5d, 0x50129c63, 0x58f5067a, ++ 0xd755a816, 0x8f511faa, 0x981def19, 0x8cfdd197, 0xb80ef7c8, 0x7f218bdc, ++ 0xbfb8c7af, 0x54b7d3ba, 0xb0efbfc5, 0x7f46c522, 0x96df2607, 0x0ff71d31, ++ 0x1fdec9fd, 0xa4e75711, 0x89d409a6, 0x7e419be2, 0x1c55c0a8, 0xfae21773, ++ 0xdef1b725, 0x065e1182, 0x31a7d5df, 0x6712f77a, 0x9e51efe5, 0x92da1c02, ++ 0xde2afd08, 0x944f661f, 0x6eefe8a8, 0xf434da71, 0xdf38ace7, 0x36f9a1b8, ++ 0x8a3df8d8, 0x0f865b06, 0x2f71b8f5, 0x0d9e922c, 0x926e8b40, 0xfe46cd43, ++ 0x997bc472, 0x19bcda5f, 0x8f1d6023, 0xdfd317c6, 0x53ddca07, 0xbcbf42e4, ++ 0x69bbbc41, 0xc7d27490, 0xefc4d3ba, 0x17773233, 0x8b7693f9, 0x9dfb8dba, ++ 0x206faf74, 0xf3bf2545, 0xd896fc70, 0x586f90c9, 0xaa3dd129, 0x31355486, ++ 0xcbef00b3, 0x7bf50ccb, 0x17495743, 0x8f6c07da, 0x93837c7e, 0x53d6e3df, ++ 0x43ebdd19, 0x7c19143e, 0xc1f10d30, 0xe4f7ee2f, 0x831adedb, 0x52d3f5fb, ++ 0x9bb60958, 0x404f7016, 0x4bef189a, 0x46b32f80, 0xf0f7e2a4, 0x714c567b, ++ 0x830a7dd0, 0x0214002f, 0xdbf043b7, 0x78c393e0, 0xc256ef1f, 0xfc1bc7de, ++ 0xf3962a7b, 0x5c378cc9, 0x155b51c6, 0xcfe48dfb, 0xec3501ff, 0x4a307ca6, ++ 0x00004a30 + }; + + static const u32 xsem_int_table_data_e1h[] = { +- 0x00088b1f, 0x00000000, 0x277bff00, 0xa3f0c0cd, 0xa5fd811e, 0x79ba1818, +- 0x8968c550, 0x30327137, 0x303170b0, 0x06710268, 0x2036ded0, 0x17c40edd, +- 0x1022f880, 0x3033719b, 0x11710214, 0xf2032f10, 0x56dcd093, 0x50c0c4c1, +- 0x4035c405, 0x3ac4075c, 0xba0c0c8c, 0x1fdbc48c, 0xf0c0c42f, 0xd7c10c42, +- 0x48606710, 0xff9fa491, 0x54ee1b07, 0xc27dafa1, 0x860c0caa, 0x4662a8ba, +- 0x5d637c68, 0xa09866fc, 0xf1a29bc9, 0x17e8f0cd, 0x87e540b4, 0xe3f2a219, +- 0x7618198c, 0x3709a922, 0x7416efc4, 0xf7a802fc, 0x00031025, 0x22037beb, +- 0x00000368 ++ 0x00088b1f, 0x00000000, 0x92cbff00, 0x51f86061, 0xa507c08f, 0xf3761818, ++ 0x12d18aa0, 0x6064e29f, 0x6062e190, 0x19e20470, 0x00977b40, 0xfc40a5e9, ++ 0x03df880e, 0x03371871, 0x9e2054c3, 0x8047c406, 0x6e6849fc, 0x6062616b, ++ 0x0ee20368, 0x6202ee20, 0x0606461d, 0xede2465d, 0xc0c42a3f, 0xe08e2010, ++ 0xafb2004f, 0xffcfd24a, 0xb67f0d83, 0x357dafa2, 0x290c0cd6, 0x71fe082e, ++ 0x54860667, 0x69355417, 0x48cdf82e, 0x40cf9347, 0xd1e267e3, 0x951f5dff, ++ 0xca89a32f, 0x6066d337, 0xf04034a8, 0xbbf13565, 0x00af1d05, 0x40695dea, ++ 0x232efabc, 0x3195be54, 0xe8000684, 0xa8f9d363, 0x00a8f9d3 + }; + + static const u32 xsem_pram_data_e1h[] = { +- 0x00088b1f, 0x00000000, 0x7de5ff00, 0xd5547c09, 0x73b9f8b9, 0xc999dee7, +- 0xac84992c, 0x5d86f12c, 0x48409c04, 0x5876c443, 0x0622b4a4, 0x30a20a97, +- 0x9037d96c, 0xff69f0fa, 0xa5ab0819, 0x68d06a1a, 0x68304ec1, 0x1a0741b0, +- 0x01c04830, 0x6a2be2d4, 0x6d8ad3ec, 0x2c3480c5, 0x0dc46486, 0x3ff2d3de, +- 0xcdce77df, 0x11337bdc, 0xbffbfb6c, 0x4f169fe5, 0xb7fb3dce, 0xe77cef9d, +- 0x92cc5f3b, 0x407e1240, 0xa1f865c8, 0x211318e9, 0x5d245c64, 0x88fdfd6c, +- 0xe5227d53, 0xacc8957f, 0x465a48e0, 0x46dbe42a, 0xb213be45, 0xb16feb12, +- 0x589346b9, 0xc402d348, 0x93df3f45, 0x84592268, 0xf826e7dc, 0x9bce25b3, +- 0x12126426, 0x6f7168de, 0x25dfa74d, 0xd02425c5, 0xb720fd74, 0x4a76805f, +- 0xebc3e412, 0x9a56f725, 0x165f5f27, 0xcad9bda1, 0x27e813da, 0xf87c9089, +- 0xd221107d, 0xe8f89145, 0x024ba4fc, 0x32245ba6, 0x4fce972f, 0x2646df72, +- 0x73f3223a, 0x9392e427, 0x994efbf4, 0x52efd396, 0x37d5ae42, 0x2d7e5232, +- 0xe4fe7011, 0x5fec4aeb, 0xfbb56f1d, 0xd717ab36, 0xdfb517eb, 0x5c17dcbb, +- 0xcb757df0, 0x2d0fd8ed, 0xc39675c1, 0x9e5a14fc, 0xa6265270, 0x3811ff48, +- 0x351c7005, 0x71d0b4af, 0xf08847bf, 0x84ed37ca, 0xb76abbae, 0x5c2858a4, +- 0x4296ef26, 0xd2f9a03f, 0x7900213a, 0x211b01d3, 0x9b9d6e14, 0x94e43e59, +- 0x7cff50bd, 0x2ed3cd3d, 0x8fad2dca, 0xdd7000dc, 0x38ad922d, 0xe609ae4c, +- 0xadc2aedb, 0x6cf3e599, 0x775a5b2c, 0x2fb42e70, 0x1b10b668, 0x6f74afed, +- 0x681b8cfe, 0x4488ff3e, 0xb6e94aa0, 0x9a5f7215, 0x41080c2f, 0x224d77c8, +- 0x8f7fbe38, 0xeb46d818, 0x935ab977, 0x3c70a4ee, 0xca256957, 0x676f3a30, +- 0x141dd26b, 0x9d81450e, 0x515da153, 0x1201e0a3, 0xdb7bbc9a, 0x5db4a9eb, +- 0x63c176e9, 0x6e2970a1, 0x386513b0, 0xfa65c39b, 0x0c49bdaf, 0x2f9680fd, +- 0xe924eba5, 0xa9ead780, 0x37f18444, 0x02338aca, 0xc39573a7, 0xe4896289, +- 0x71d3b74b, 0x17b2bb68, 0xb12c0f04, 0x407c44cc, 0x6d7b9d97, 0xc0719eb3, +- 0x43c856fa, 0xb5aeb09d, 0x0fcbd432, 0x5363dfcc, 0xf2757e60, 0xb45e5a54, +- 0xd3ce4eb9, 0xe1b8bfe0, 0x3558a23a, 0x941daaf3, 0x630fa5ac, 0x89928e7a, +- 0x84453e76, 0x200e8378, 0x533c8083, 0x857d17c3, 0x7177c438, 0x9feba883, +- 0x44909242, 0xe8f7dffa, 0xfe5e14af, 0xab844efd, 0x9ca5b78a, 0x5dbc548e, +- 0xcc43fce0, 0xff6d2ce1, 0xe008fa6a, 0xbaa7ce81, 0x2fe98dd2, 0xad30532b, +- 0x3f1054a9, 0x68fc038f, 0xdbcf81ba, 0x344c8135, 0x5e5d71d3, 0x8b3606e2, +- 0x289dee9f, 0x2e7c7cd1, 0xe3dd27cb, 0x596f9413, 0x2e3e9abf, 0x4f03e6f9, +- 0xbd53226e, 0x979a54e6, 0x87884b7d, 0xd5be6f8e, 0x213c653b, 0xa3df12af, +- 0xe4d17eb0, 0x12bc002b, 0xa5c94c12, 0x50235978, 0xb5e14239, 0xe1491616, +- 0xd29526b0, 0xe3d3c533, 0x233d66f7, 0x09ad7c0a, 0xf67bcf90, 0xa7ec74e1, +- 0x6991fb16, 0xdcae833f, 0x6cdcd24f, 0x73493f5d, 0xea7ed40b, 0xab989fb0, +- 0xb9f1e7eb, 0xccf9fa39, 0x79fb522d, 0xae89ea1e, 0xd2575bab, 0xf9fa09bc, +- 0x7ec12bcc, 0x10f1ef92, 0xaa2fad1f, 0xbd5a43f4, 0x34772d22, 0x98798dc6, +- 0xd268e968, 0x49cfe81e, 0x474b4ab9, 0x3a31d9b1, 0xc6f38a7e, 0xa67df2eb, +- 0x4fd5d5f5, 0x2ba81dcc, 0xc2359e4f, 0x770e9740, 0x0f3c75fb, 0x91597293, +- 0x32bee5ef, 0x7d899dca, 0xfbff38ad, 0xee503afb, 0x1be39fdc, 0x86f3a6e6, +- 0xff8a12b9, 0xf5df65fb, 0x437428ee, 0x149025d7, 0xa4131548, 0x12b5f2c6, +- 0x7ea4db83, 0x413d0f5f, 0xc29b97db, 0xfe68e343, 0x8ff13088, 0x80bfeeb0, +- 0x8b78a530, 0xd4054911, 0x9410b18b, 0xb3d36b7f, 0xe06bf19e, 0xa5006eba, +- 0xefd22117, 0x0297c93a, 0xafe6d8f4, 0xae7d03f0, 0x60532019, 0x54827212, +- 0x6983fc84, 0x297901fb, 0x4c8b7f00, 0x7c7687e5, 0x123f8e99, 0xf1876fc7, +- 0xdf197a3b, 0x375b3032, 0x40ad35be, 0xa655be37, 0x08fe53e3, 0xf1f397fb, +- 0x0872fc29, 0xc72c94f9, 0x05692df1, 0x995afe38, 0x8fc6e814, 0x4bff1ee9, +- 0x186bf718, 0xfaca313f, 0xd7e8e607, 0x5fa4569f, 0x4fd6ccbf, 0xf8f9f856, +- 0x417eb831, 0xa7f5b3f0, 0x5bf5b115, 0xe3ddbf58, 0x2fe1babb, 0x875c740b, +- 0x07facbd0, 0xffafd04d, 0xfafd129a, 0xf77c6c2d, 0x7c7c758a, 0x271f8e07, +- 0xbfeb63ac, 0x97c704a6, 0xd00f3e2d, 0xa62fdc91, 0x69fb0022, 0xc940ca7f, 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0xd78a89fb, 0x1f52efcb, 0x8ad93c2a, 0xc4737f75, 0x1620efce, 0x73c9c48e, +- 0xb63a8cd5, 0xd9b17daf, 0x2e283fec, 0xfea2688b, 0x214d0b27, 0xa6ffdfdc, +- 0x599e73b0, 0x6dfca3d8, 0xc3df2c53, 0xf1bf8e56, 0x964dec39, 0x92a7f7f9, +- 0xff599f68, 0x8ba078a0, 0xfe2f479b, 0x6ca84fe3, 0x187fdb1a, 0xfe4911fb, +- 0xb9c3f066, 0x7ef3bad1, 0x9d37f542, 0xb48f7643, 0x8fbf4263, 0x9e7e0fe3, +- 0xac8a6298, 0xc5c8caef, 0x879d5f17, 0xe9f1ced2, 0x32cdc785, 0x9eb5159e, +- 0xbe2e192b, 0x98fd4e0f, 0xa61c573e, 0x0b87ce20, 0x0f7a9f8f, 0x7b885beb, +- 0xd83738ce, 0xf6f597ad, 0x2566b84e, 0x150e7e23, 0x88ac97fa, 0xb540783e, +- 0xae7d694b, 0x7b08dc9f, 0x2059a6f9, 0x651440ee, 0x07d6883e, 0x425f833f, +- 0xaa37c6fe, 0x07ed79e4, 0x546fbe39, 0x67065cb1, 0x9be72e41, 0xb69fbf27, +- 0xe3514aaf, 0xd1ae9259, 0x8ba68b74, 0xe7716f86, 0x8524e9f0, 0xa8f45cf1, +- 0xc62eefc4, 0xb767e7ef, 0x198a9893, 0xc636fbff, 0xf86ffff3, 0xca7de2fd, +- 0xfbe373f7, 0xd3ed3afc, 0x77e7d86d, 0x93ed1ffe, 0xbcdfc0f5, 0x3ee361cf, +- 0xb142fad3, 0x8f37c073, 0x8acfd89b, 0x0a2a37be, 0x66d1eb04, 0x53c71c73, +- 0xddf271fd, 0xd3cfe901, 0xde9a9fd0, 0x2e175d9c, 0x4e71bf82, 0xaeb16788, +- 0xeb8869b0, 0x30e5562f, 0xc314ccdf, 0xc27efc99, 0x3f872e12, 0x35bfb66b, +- 0x4bb223f7, 0x0f048f03, 0xf4e34abf, 0x56a7c129, 0xeddd5f41, 0x95dcfce0, +- 0xa56029a0, 0x45920679, 0x7f9a31f1, 0xce5ccd60, 0xaa115cb3, 0xb1b06a9e, +- 0xecf6a29e, 0xca37b41e, 0xf9fdeff6, 0xa3f81ec2, 0xf782f923, 0xae225033, +- 0xc0f04bd9, 0xff6e0292, 0xf6e7a6a1, 0x97efc824, 0x8193e608, 0xef7c2935, +- 0x83a7e9e4, 0x0e8ec2d7, 0x11337a0c, 0xf44cab57, 0x19c74187, 0x079f6966, +- 0xe54f54dc, 0xb1af8a13, 0xc914e31d, 0xe31b86f5, 0x43403a5e, 0x2a91e6c5, +- 0x3d73faa5, 0xd5cf9c09, 0x638b47e4, 0x7f9c0ecf, 0xded2780a, 0xf2a07f23, +- 0xc5778699, 0xa667df2b, 0xe8d678aa, 0x6a5bf1a0, 0xa6cf7c9c, 0x377c916c, +- 0xbd791f7e, 0x33c8fbe0, 0x27782969, 0x71e31cd7, 0x4adfdf01, 0xfd618ff2, +- 0x3e881b7d, 0xd243ec66, 0x5bde1ce1, 0x997fe24e, 0x7e5a4dab, 0x3463df9f, +- 0x9a5fa90b, 0x3d17f7b5, 0x2217f7c6, 0xef19333c, 0xe89f9891, 0x3edd67fb, +- 0x5fbe355b, 0xd2fb65ee, 0xd9def2ac, 0x7a4f34ff, 0x5aa9286f, 0x623b95da, +- 0x9dfc89fd, 0xf3450efa, 0x7c96cfc3, 0xe4f60b3c, 0xcc6f83dc, 0xa2577944, +- 0xf69ab92f, 0x1fe344f3, 0x7dc4c316, 0xf7e61990, 0xfe341f34, 0xe5c71671, +- 0xfcc1bcb7, 0x57aeb7ff, 0x01ffc75b, 0x0934e170, 0x000048d0 ++ 0x00088b1f, 0x00000000, 0x7de5ff00, 0xd5547c09, 0x73b9f8b9, 0x2cc99997, ++ 0x2cac8499, 0x04455871, 0x0310849c, 0x11161da2, 0xb4a0e22d, 0x044c0b82, ++ 0xf5206fb2, 0x032fb541, 0x1ad2d361, 0xd1a0c06a, 0xb068304e, 0x301b0701, ++ 0xd4018048, 0xa1ad2be2, 0x18b6adc5, 0x9316c314, 0xdabe1b80, 0x77df3ff2, ++ 0xbdee4dce, 0xfdb60899, 0xfbdefafd, 0x387b3fa7, 0xb7cb3dcb, 0xe77cef9d, ++ 0x4a48df3b, 0x1efb893c, 0x8fe09721, 0x089937a6, 0xd3bb6321, 0x23739685, ++ 0xaee98e4e, 0xb32644ff, 0x1d692343, 0x1cee5529, 0xc84e5dd5, 0x8cff6c0a, ++ 0x449a39d5, 0x24129a43, 0x185c5a4e, 0x8419226f, 0xf822e83c, 0x378c4cf7, ++ 0xa4274845, 0xb5d9bd73, 0x972d2079, 0x8e214edd, 0x760e8fa6, 0xcef80405, ++ 0xcef9009d, 0x66d76547, 0x5cdf279a, 0xc97be112, 0xd027bec2, 0x3921024f, ++ 0x84c1eff0, 0xe24517c8, 0xafd343ef, 0x919f4c05, 0x9d1f3cc9, 0x93baec9f, ++ 0xcf77b44c, 0x23e715cf, 0x1df2d11f, 0xe5a7ad0a, 0xe2cf9c72, 0x7f5dd91f, ++ 0xfe70110d, 0xec329be4, 0x956f1d5f, 0x178b4eeb, 0xb5101bd7, 0x0bae1de5, ++ 0xd55f284e, 0x43f61774, 0x259d706b, 0xad373f30, 0x2148fb8f, 0xbbfeeea6, ++ 0x71c414e1, 0x89bbbcd4, 0x213d7b8e, 0xb5bffec2, 0xf2eeba12, 0x4cdbb29d, ++ 0xa77932e1, 0xcd1efe1c, 0x4108d517, 0x59f69bc8, 0x6b70a109, 0xb0f966af, ++ 0xfb42f143, 0x9e696b4f, 0x6e625176, 0x000df9fe, 0xd9229dd7, 0x4cf8c38c, ++ 0x1556df30, 0x9f2c8d6e, 0xa2d9656d, 0xe173039a, 0x3346dcfb, 0x8afed2b1, ++ 0xb8cce776, 0x0e73e681, 0x149a04cb, 0xf4ae596d, 0xa0bcf9a5, 0xc77c8210, ++ 0x07e38224, 0x2dc18976, 0xb3877db4, 0x1407e139, 0x2ccb678e, 0x9d357dc4, ++ 0x6139a3b7, 0x7e438516, 0xf854c770, 0xf05ebf2e, 0xde4d0900, 0x648de5b9, ++ 0x56d15dfa, 0x70a663c1, 0x11b3a829, 0x873670f7, 0xd6bff44b, 0x3dfc3106, ++ 0xae98bf5a, 0xbc040c93, 0x22254c56, 0x715ebf8c, 0x74e1ba3b, 0x71386cb6, ++ 0x45f3bb9b, 0xf438e95b, 0x82ede2bb, 0x6c589607, 0xcba07e22, 0xd9d6ddf6, ++ 0x7d61d9cf, 0x0e6195cb, 0x051ad758, 0xb304e5da, 0x30dd5976, 0x2a651abf, ++ 0xaeafcfad, 0xf835b251, 0x96bba82f, 0x799a2db8, 0xd44e0d55, 0x3d3187d2, ++ 0x3b44c94b, 0xbc427c9f, 0x41903b21, 0xe1a99950, 0x0c42be8b, 0x4ea0bbe2, ++ 0x214ff5d4, 0xfd3c4849, 0x3fe9b7ff, 0x7b02bc29, 0x1557081d, 0x1d398b6f, ++ 0xc0bb78a9, 0x9d4887f9, 0xd5feda19, 0x0780e7f4, 0x328a9f3a, 0x28bfa617, ++ 0xb2b4c24b, 0xd9f88dcc, 0xe9a3f008, 0xe76f3e3a, 0xa2513204, 0xc4bd3ae3, ++ 0x3b166c05, 0xa6513bdd, 0xcb1f58f9, 0x17e7dc27, 0x7eb2dfdc, 0xfb28dd35, ++ 0x372780b3, 0x295ea990, 0xff15e699, 0xe3a1e222, 0xa778774b, 0x35e4238c, ++ 0xd61c7fe2, 0xe7f052bf, 0x09095e02, 0x5e28f925, 0x8e540b56, 0x81ad7850, ++ 0xac385245, 0x4cf4a64e, 0xfef1b4f1, 0x8144e78c, 0xf20e35af, 0x363fcfd9, ++ 0xc2a9fb10, 0xcfda647e, 0x93f7cbe0, 0xd7533730, 0x5cdcc24f, 0xec1a9fb5, ++ 0xfd657ac7, 0x5e3b9c6c, 0xf9b99f3f, 0x422f3f6a, 0x2b8e95bb, 0xbcc2575b, ++ 0xccf9fa09, 0x127ec42b, 0x3f10f3ef, 0xf4aa2f6d, 0x22bd9a43, 0xc7d7b7ad, ++ 0xb4463da4, 0x17693474, 0x5ca0e7f4, 0xe8a3a5a5, 0x3f1d28cc, 0x756378c5, ++ 0xfad33ef9, 0xfbc7daea, 0x13eae906, 0xd0308f67, 0x7ad5dda5, 0x49d3cf2d, ++ 0x9c146385, 0x4157d2af, 0xafb133b9, 0xf50ff305, 0x79dca3b5, 0x6affbc68, ++ 0xcc379d17, 0x3ffc5095, 0x73aff8a4, 0xba1ba045, 0x4124812e, 0x6a4136ea, ++ 0x33235fac, 0xf7ea4db8, 0xf413b0cd, 0xe75312fb, 0xff9a18b0, 0x1df130a3, ++ 0x419ff758, 0x45bc5298, 0xda14a489, 0xca099945, 0x330335bf, 0xe0680b9e, ++ 0xa50076ba, 0xdfbba117, 0x093fb2b5, 0x5025b1e8, 0x5cfa001a, 0xa7ae803d, ++ 0x4827212f, 0x84303869, 0x3b203f7e, 0x566fe009, 0x8ed0fca8, 0x47f1d0af, ++ 0x30adf8e2, 0xe32f5b7e, 0xea65079b, 0xe4a4b7c6, 0x28b7c6ea, 0x1fca7c74, ++ 0x7ca5819d, 0xf1bf0a7c, 0x4b279c84, 0x4a737c71, 0x46bf8e2e, 0xf1bab921, ++ 0xffc6baa3, 0x06fdc612, 0xb08f8fc6, 0xf5e341fe, 0xd7c94feb, 0xeb615faf, ++ 0x7c03cb27, 0xbf5c28fc, 0xfad80420, 0xfad9f253, 0xaedfaccd, 0xf05d9df1, ++ 0xae3a0457, 0xfd65e85d, 0xd7e82783, 0x7ea1557f, 0xbe3666fd, 0x3e5af96b, ++ 0x8fc71dbe, 0xf5b2d611, 0xe388555f, 0x07bf662b, 0x17e948e8, 0xfd841a55, ++ 0xa0653fb4, 0x5e819444, 0x12c7874c, 0x6fc9e542, 0xc38420c9, 0xee8c5143, ++ 0xf4a28cbe, 0xa796ef66, 0x90394824, 0x9cc5c3ee, 0x27ea0ba6, 0x0e7f6c2a, ++ 0x90bebee0, 0xa341754f, 0xa919fb88, 0xd2870734, 0x8a37b6f9, 0xa82fc801, ++ 0xe22831bc, 0x08f4ca7e, 0x94309122, 0xd461b27f, 0x8cbaed66, 0xb90ac2e9, ++ 0x57c345b5, 0x127df25d, 0xe74a5e19, 0x30440a57, 0x4adf3bb6, 0x72a134e5, ++ 0x8f2a23f8, 0x33253d21, 0x9524e4bd, 0x2d6ae4e3, 0x7a672cdf, 0x1b1c8049, ++ 0x43ffe74e, 0x8956ff3e, 0x8975bbc1, 0x7ff80410, 0x02917eb9, 0x85616cf2, ++ 0x7bbd028d, 0x4f1c251e, 0x41cdbb9d, 0x76e8a7d4, 0x1bb9f000, 0xbf909159, ++ 0x0dfdbbec, 0x3969ea81, 0xdf747d55, 0xab8247dd, 0xf9fb6892, 0xb806b2eb, ++ 0x9deffae8, 0x61134e6d, 0x7ede227f, 0xd263e426, 0xc84994cf, 0x72f586ec, ++ 0x7bb99a3f, 0x8b51fcb6, 0x7e39fbe6, 0x5cdefe7d, 0x0e5dbe7d, 0x67d026ca, ++ 0x435204f2, 0x54bfbdfb, 0x338eaf5f, 0x7865884d, 0x90fde3e5, 0x169920c2, ++ 0x1a690fdd, 0xaf10bb14, 0x5bec5d73, 0x0f253e75, 0xfb8c24cb, 0x413c4b71, ++ 0x3b63c7fc, 0xdbad8bbf, 0xb2b9df38, 0xf3a3ebc5, 0x444cbb99, 0xdfe71a78, ++ 0x35e6cfb2, 0xd569a68d, 0xa0903267, 0xf9c63d71, 0x5c6a5bcf, 0xfd814b8f, ++ 0x2c602b21, 0xa4627467, 0x89c692a7, 0xd0d49c4f, 0xd6e85153, 0xbe6a4e27, ++ 0xa99ba82b, 0xe705e7cb, 0x54e7dae8, 0x17eae965, 0xeae9e456, 0xa45dafe7, ++ 0x960567cb, 0x5bcfdae9, 0x7f575cba, 0xbaa3e97f, 0xd7737bfa, 0xfc73f2eb, ++ 0xefed749b, 0xaba35d9e, 0xe6bbed37, 0xf2a3e00e, 0xfb0245b7, 0xd6f617c6, ++ 0xf9be839f, 0x00f25d85, 0x7d534e3e, 0x2ce0f805, 0x6d2057d5, 0x7a831c6f, ++ 0xd9839535, 0xd550aa84, 0xdac091c2, 0x09972009, 0xf0a0cfca, 0x3fa04087, ++ 0x6e082f21, 0xa5589f84, 0x61253090, 0xd176c481, 0xa9a8a771, 0x7d4cb96f, ++ 0x31f46515, 0x96c5eb3d, 0x9b25e5c8, 0xd972aeb3, 0xf407977b, 0x73ec1faf, ++ 0x301f5c1d, 0xc40a17d6, 0xcf572da7, 0x4c09d74f, 0x73f217ce, 0xc9cbe14a, ++ 0x551ce093, 0x958784a8, 0x2178db7e, 0x9390540a, 0x03c7fda0, 0xd02e503d, ++ 0x6ea0a3e0, 0xdbbf8eb0, 0xaf38880e, 0x54099062, 0xdf12a6ae, 0x4ce40121, ++ 0x5dca50f8, 0xde1e60a3, 0x93ee40d7, 0xd7dc78c6, 0x3da6cadb, 0xfc065271, ++ 0x5d3d30f8, 0xd6d31b36, 0x27a63f32, 0xfd3172cb, 0xd314aca8, 0x98a5b296, ++ 0x600b2f1e, 0xb5b2e7fa, 0xaca9fe98, 0xcaf7d302, 0xa77d30aa, 0x7b69882c, ++ 0x95531799, 0xafe4ba1f, 0xfcc3eb8f, 0x980b42dc, 0xb2d7cc3e, 0x466db692, ++ 0x0124f73e, 0x7fb05f9f, 0xfdf40c39, 0x2251ef0b, 0xbc3bd81a, 0x3bd6f48c, ++ 0xafa8bd1e, 0xf1290764, 0x6f59e9f4, 0xb278628d, 0x4234c89a, 0x43a3d1e5, ++ 0x303cf79f, 0x9012f312, 0xcf54a50c, 0x7e84474c, 0xf807dee9, 0x889e1cba, ++ 0x9c3473b7, 0xfa9f5bb3, 0x7bf4066b, 0xed88309d, 0xdc4487c3, 0x39f84987, ++ 0xbbebe00f, 0xffd84dc2, 0xda169497, 0xf82ed3ee, 0x9a10a735, 0xd85c122e, ++ 0x330685ff, 0x4d8e0091, 0x8d1c20b6, 0xce7e1c2f, 0x38b8fc09, 0xdad0ac49, ++ 0x51698c03, 0x5d856068, 0x46929eb3, 0x8542fe7d, 0x0fd98d30, 0x46b3d1dc, ++ 0x2ab95d01, 0xfc050e4e, 0xf6aa6127, 0xc14938b3, 0x0dd6ce71, 0x77fb668e, ++ 0xf583ed90, 0xf4af4831, 0xffed89dc, 0xade9f3d5, 0x843e751f, 0x2d8f9034, ++ 0xdd680f20, 0x8f9fcbe0, 0xfa5de07a, 0xbe01f15c, 0x412fe49a, 0xffa2885f, ++ 0xfd041a5d, 0xfb57984a, 0x0189092d, 0x5e5075f3, 0x7e8f1baf, 0xf4cf56e7, ++ 0x74ef5df0, 0x7556912b, 0xdd5e549d, 0x0539edc8, 0xfd0ad675, 0xcba312be, ++ 0x57263497, 0xf819f6e8, 0x527fe507, 0x3f40482a, 0x3a9a9c85, 0x815afb24, ++ 0xe4c92fce, 0x044b7ec6, 0xd2c8aed6, 0x48ddf8a2, 0x67a0cd8e, 0xd2a9903c, ++ 0x0feefb9f, 0xf33fbca8, 0x063c995b, 0xa3aedcf5, 0x087747f6, 0xf9f9a262, ++ 0x4340f73c, 0x7b9074c1, 0x1f7d7667, 0xc40593f5, 0x524384e7, 0x00c8a92e, ++ 0x6253e73d, 0xfff4069a, 0x7383f929, 0x91bce68c, 0x3e705263, 0xf7ead7f3, ++ 0xe99faa59, 0xfa5539f2, 0x33b9367c, 0xbb3de801, 0x0b7ba652, 0xfebea5f0, ++ 0xf90b936e, 0xae94872b, 0x92bfb906, 0x701e579f, 0xe51fa911, 0x9e57a2fb, ++ 0x091ac8c9, 0xbf260876, 0x5e40fb55, 0xf253d32c, 0xd80a3543, 0x186e3e8b, ++ 0x081bc3f3, 0x0d5c1f7c, 0x4ec09276, 0xddc5b3c1, 0x75df7f13, 0xaaf9c6fe, ++ 0x3b0f49fb, 0x51479f05, 0x460de09d, 0x311e4fd8, 0x0adf5c09, 0xaf8eba60, ++ 0xab5bd55b, 0x435af90c, 0xffc8643e, 0x4716f4c3, 0x6496f474, 0xe29957f2, ++ 0xbe817d19, 0x8a9d4820, 0x3fe99fff, 0xb5ff47a9, 0xfbfed2ff, 0x7433fed3, ++ 0xa5fe87fd, 0x31e90ffd, 0xfd48a6ff, 0x6db2bd17, 0x9bca8057, 0x383697fc, ++ 0xce87dd09, 0x1e091548, 0x2dc2ff8a, 0x797ed0ab, 0x81380a5a, 0xc504cf9e, ++ 0xe708c169, 0xdc4ccff6, 0x76bc4a2e, 0xf055ce01, 0xd9ffda4f, 0x033a7f17, ++ 0xb72fb9f4, 0x2f3c2ec8, 0x66c399d5, 0x0dc5a7ca, 0x68c9d379, 0xf9609fcc, ++ 0xc845e735, 0x33e9ea37, 0x090d85ff, 0x94a3df60, 0x6113cfc2, 0x6b8a97d4, ++ 0xfb0a993f, 0x44e90950, 0x077e333e, 0x458c5fe3, 0x44a598f9, 0xf3a7acf7, ++ 0x84bf3d44, 0xe1a4a5c3, 0x2745e7a7, 0x429eb7a4, 0x4169347b, 0x5df8dc3d, ++ 0x4e83d72e, 0xad711c9a, 0xae4508f4, 0xdc83d727, 0x8242e154, 0xdf2a0f4c, ++ 0x13e8e4fa, 0xb56d5e74, 0x1a0a75bf, 0x76fca978, 0x97ff3421, 0x977bbaaf, ++ 0xbcfcedcb, 0x105dfdd7, 0x723773bf, 0xa589adfd, 0x09d87285, 0x8d6171fa, ++ 0xe2d009ec, 0x3dcf6dc2, 0x579c14ff, 0x867b37df, 0xb60bfed2, 0x78cefebd, ++ 0x21d82f9a, 0xcb674dc7, 0xdd090bb0, 0xffa129f8, 0xc6eb4d2d, 0x5faffe47, ++ 0x58a3dc57, 0xddb123f9, 0x71d82978, 0x7aa32140, 0xe87263c2, 0x8f62d280, ++ 0x89d09f80, 0x9567a0a9, 0x814afd6f, 0x7d99e573, 0x181c4902, 0xaf359e01, ++ 0x7000bea3, 0x7c727c42, 0xd0cfe175, 0x05e284be, 0x5f11bae4, 0x83af76c6, ++ 0xfacb197c, 0xa524fb05, 0x82afedef, 0x664ffb1d, 0x7721c00f, 0x584e83fb, ++ 0x94a929cf, 0xab33f9d1, 0xfc74bc12, 0xe090395c, 0xe79594c2, 0xa423fb3e, ++ 0x3fa39cbf, 0x43e7604a, 0xf709b26f, 0xac3240aa, 0x0ff56173, 0xc4d99d70, ++ 0xfb98748f, 0x7903e88c, 0xa64485f9, 0x27c088ed, 0x93e32205, 0x72299b53, ++ 0xc14f3ae9, 0xfbe40539, 0x16e0c41f, 0x222c8fb4, 0xa47e0f20, 0x62c9e3da, ++ 0x61617fcc, 0x9a289af8, 0x45ae73d4, 0x6bb5bf47, 0x674f019a, 0xc1137807, ++ 0xa44256ae, 0x70878700, 0x1e2bf689, 0xe19139bd, 0x0ca5b889, 0x0bd51dfe, ++ 0xb4394326, 0xd6bd966f, 0xc8efbad1, 0xe3dd81a5, 0xd3e3e12f, 0x7ec14779, ++ 0xe4812a7e, 0xafac2286, 0x00e5544a, 0x7435d7dd, 0xc677e1a6, 0x328fb5ff, ++ 0x3ff9577e, 0xd41a7338, 0xf18c7e7f, 0xfb077c11, 0x38579d25, 0xcc0feb11, ++ 0x983e5012, 0x9f123849, 0xcf9ccad7, 0x7a46f5f5, 0x8497f3a1, 0xc0dd0d68, ++ 0x0788b138, 0x5765abb4, 0x72b5efd2, 0xf675c615, 0xe3e557ec, 0xb20f2e1c, ++ 0xae0f2a45, 0xa40796ed, 0xde81c99a, 0x3b00aef5, 0xe7c1c9bf, 0xa5fe029f, ++ 0x03701afc, 0x583ecaff, 0x43fab9ff, 0xf943dcef, 0xe5485cf6, 0x355cbd5b, ++ 0xcbee6df2, 0x53a0045b, 0xcb9edf23, 0x244a5aa5, 0x11e5a5be, 0xe5b736f9, ++ 0x555722df, 0xea2e3e38, 0x272aaae5, 0x51a7837b, 0xdd108e4e, 0xfd24e511, ++ 0x7a32463b, 0x874aa3d2, 0xffe5fd2a, 0xb42ae8aa, 0xaa74a827, 0x9d1761d2, ++ 0xc3d874aa, 0xa383a33e, 0xa06efeb1, 0xdf04ba09, 0x89ed196e, 0x3eec4d85, ++ 0x46f77e8e, 0x978474bf, 0x5239b717, 0x38bf46f1, 0xc8683e6d, 0xbded0c87, ++ 0xd0cfbc86, 0x97c86fde, 0x3617daea, 0xd208521e, 0xced75841, 0xf269f4bc, ++ 0xac738471, 0x34950fba, 0x4002579c, 0x153bfd1f, 0x0af27f90, 0xfd807012, ++ 0xf688af70, 0xe30a0ec3, 0x8e9c74d5, 0x00c181fa, 0xacab2395, 0x19d9bcec, ++ 0xb906acaf, 0x74eae1d7, 0xcade42c6, 0x5f0ee3f4, 0xa34633a7, 0x12689e67, ++ 0x04b76e51, 0x7648b4c9, 0x20b3ba11, 0x6f485b3c, 0xda1eccf5, 0x99eec511, ++ 0x29ed166f, 0x5a9ce14b, 0xb9287a21, 0xefcb0590, 0xbca98276, 0x1df069a3, ++ 0xc2f969b3, 0x3d764537, 0xc94af013, 0x69c5f39a, 0x4138d812, 0x75bb7b80, ++ 0x9bf32748, 0xc16379d8, 0x9f74c8ba, 0xb6cbbfcf, 0xbe40512f, 0x47c273d2, ++ 0xdaaf7b5a, 0xa1b56e4f, 0x9cfbe9bc, 0xdcf02a3f, 0xafab5f97, 0xd373f3f7, ++ 0x499caa67, 0x6728a925, 0xe70440e0, 0x6f9f2e77, 0x31de4716, 0xe3a1e29b, ++ 0x1ee048b0, 0x889342f5, 0xcf50b878, 0x20494dee, 0x98acf91e, 0x545ca274, ++ 0x7c06d5e1, 0xf2ef7574, 0x5fe76daa, 0x7a061e32, 0xe8c1f5d9, 0xb6da69a7, ++ 0x7b61fdeb, 0xbbcaff20, 0x9e901f29, 0xb3ef27ed, 0x63b93da2, 0xbce9039f, ++ 0x52efef63, 0x6efc861e, 0x3af1da33, 0x1a357df6, 0x8563aee8, 0x5de41739, ++ 0x2fe600c7, 0xabf7be50, 0xcfb82dd1, 0xa5fc44ae, 0xf9e20a48, 0x8f5fd342, ++ 0x85ff7dc3, 0xd02aba26, 0x90d9f623, 0xb55e4a8f, 0x63a1dda2, 0x7e1957ef, ++ 0x3d6ebffb, 0xa79efcc5, 0xbf6641c3, 0x618bf30c, 0x3d92f1f6, 0x0e5b9ee3, ++ 0x070de0f7, 0x7eb4f994, 0x8dbffef2, 0xf1da3906, 0xda8fd332, 0xe16796e5, ++ 0xc91ae31e, 0xf8a642b4, 0xea66076a, 0x6911f54b, 0xc8c0a4f2, 0x1bf97048, ++ 0x14ae53da, 0x9d895e1e, 0xc3e7ff5b, 0x3932f043, 0x045a08e7, 0xc7d7f758, ++ 0xb079003f, 0xa9748ccf, 0x685cf7ae, 0x972dea39, 0xffbcf75b, 0xa5707435, ++ 0x57c216eb, 0xfcffeeb2, 0x496ebe1f, 0x8cfce372, 0xce93d07c, 0xf9843ef7, ++ 0xce0f0e6d, 0xfde90af7, 0xf46bffd9, 0xbbc532fe, 0xdeebf2f3, 0xef16bffb, ++ 0x78e5ce6f, 0x401f8177, 0xe1bffec9, 0x9cabbefc, 0xd2ffcbfb, 0xfd7aabf5, ++ 0x63ee4c6f, 0x34fdb4a9, 0xc5076152, 0x83a2d6e2, 0xdad2a66f, 0x143ff4df, ++ 0x649df303, 0x5351d7b8, 0x4fcecca7, 0x877ee093, 0x04624b8e, 0xe7642e7e, ++ 0xbf5c7ea9, 0x1b24b7e8, 0xfd7e90f5, 0x04fa867f, 0x7095dc91, 0x949bf92f, ++ 0xb1f41ef9, 0xf9ef6920, 0x91baef21, 0xcae7f5e7, 0x85e205a7, 0x297ed32b, ++ 0xfa0c3fdf, 0x22feff6c, 0x4534bbea, 0xe735f73d, 0xa85e5634, 0xb73dcee8, ++ 0xa0e7f5ba, 0xf3fa71a9, 0xdfde14d2, 0xffcd84cd, 0x0c10bb66, 0x1a4c3852, ++ 0xd81c44f0, 0x950d274d, 0x53f34089, 0x9c257f89, 0xf5d8a62f, 0xfb859dfd, ++ 0x70ddb1ea, 0x245f6fec, 0x034c5d01, 0xb40c747d, 0xfef9654f, 0x2fef0901, ++ 0x8b7a3eb8, 0xfb84917b, 0x0954ff6b, 0xd9639be0, 0xae127f9d, 0xce023daa, ++ 0x1336eae3, 0xba4b21ca, 0xbc33f480, 0x51fcc24a, 0xe02c6b93, 0xaf0dc667, ++ 0xc0465b9c, 0x9855eb6e, 0xf663e822, 0x5d2e6ff7, 0xe701909a, 0xfe07f67b, ++ 0xf3d3b784, 0x126a82c0, 0x5a70a28e, 0x74409128, 0x055dd82c, 0xeece91f2, ++ 0xdfc3cfaa, 0xfddd094d, 0x6f7dae5c, 0x4eaffbf4, 0xf2fca15f, 0x764250d1, ++ 0x6af78a43, 0x9ea85ecc, 0x626faedf, 0x42392af0, 0xbdd88382, 0xdcd3e8be, ++ 0x6644fd53, 0xfe57e076, 0x3818f2fc, 0x18ec4d37, 0x38f8cd19, 0x7239f99d, ++ 0x7102f4bd, 0xc0ec7b47, 0xf1a383c7, 0xe8b0edfe, 0xb737e488, 0x7ee79f95, ++ 0x340dfe05, 0x1525a8ed, 0x48179c22, 0x0311da27, 0x25b216b5, 0xae457f82, ++ 0xc374e26c, 0xc4ff46f1, 0x600fb80c, 0x9fa42fe3, 0xd6f16b46, 0x348cfd36, ++ 0xe01e27ba, 0x7dcd23ef, 0x5f0b3fc8, 0x7c023f38, 0xa65b5ab7, 0xfbf022fa, ++ 0xcfbf398f, 0xda35f838, 0xd53446dd, 0x477e8098, 0xf7749ad4, 0xae658b7b, ++ 0x3491a7f7, 0x838cd798, 0xe03a4756, 0x01e8b0e5, 0xa692c57f, 0xc23f8af3, ++ 0x9e1194bd, 0x73d83fd0, 0xc70bb243, 0xe68723dd, 0x7cf75c03, 0x4e70216a, ++ 0x1454addb, 0x10e79a44, 0x42e79b33, 0xf4707a12, 0xf079ffc0, 0x0f61d89d, ++ 0x4e73824f, 0x6ae7e12d, 0xa411fd23, 0x24750be3, 0xce1c7208, 0x2e172045, ++ 0x47dc13d4, 0x067e4828, 0xefca3ce7, 0x09dad3df, 0xf1dc6eae, 0x8a7fd82b, ++ 0x9817049b, 0x16a58bb8, 0x2582ec05, 0xc822318d, 0xeab754fb, 0x351ae9cf, ++ 0x2117c34b, 0x1d784259, 0x5ee7bf1a, 0x36b3f718, 0xe87ec085, 0x09d3ad7d, ++ 0x4d67c5fb, 0x7a0f9063, 0xcbafd75b, 0x1914fe48, 0x5fc821fa, 0x59187a46, ++ 0xdfcba51f, 0x02fbfa20, 0xb730cd7f, 0xc044f12c, 0xc30a9ddf, 0xb7cb15df, ++ 0xf267ffe0, 0xdf2a98ed, 0xeb4fa2fc, 0xa6e1cb97, 0x91896f91, 0xc162dbe4, ++ 0x5f70089d, 0x227077bc, 0x9bf175e0, 0xf9247c72, 0xdd8cadb6, 0xfdc4bdb3, ++ 0xa81a3b70, 0x234ebb7c, 0x7ca81adf, 0x208fe08b, 0xdf285729, 0xfe1eff82, ++ 0x2df206db, 0x15137ac2, 0xf2a83fb6, 0x09d3746d, 0x1ba36f94, 0x52ff3a4c, ++ 0x7eedc2a7, 0x2137cabd, 0x61e8167e, 0x2d8f6587, 0xe36cfd02, 0xdc4bdf7a, ++ 0x01c60e2f, 0xe2bb7739, 0x54aff1c2, 0x54ae79ce, 0xe09bfdce, 0xc5b9caac, ++ 0xd9fa093b, 0x2643a4f6, 0xa6ef16e7, 0x7a004e72, 0xf16e7264, 0x3fecc25e, ++ 0xbc36f906, 0xd8237c87, 0xbecc38be, 0xf81c692f, 0xbfb47de4, 0xb1ecaf34, ++ 0xdd69f6d0, 0x56ac6ef2, 0x48aeddde, 0xf21ee708, 0xc995f0ee, 0xde5c9dbb, ++ 0x08363951, 0x3e91abe4, 0xff7a4d3c, 0x4ee33de5, 0xf81affd5, 0xde2277e5, ++ 0xb1351d73, 0x8fdf88fb, 0xf40e953b, 0xf930ab55, 0x5fd394bb, 0xfb00597b, ++ 0x5b1afc9f, 0xb33d515f, 0x303716bf, 0x56b8b0fd, 0x3fe9ba0c, 0x5aff8ea7, ++ 0xede7f981, 0xcd224815, 0x6c5734cf, 0xfe1e83b4, 0x1eb84c82, 0x43553d3e, ++ 0x0b320b0f, 0x6e5c8ed0, 0x94266e75, 0xc448178f, 0x02e2f602, 0xa033d4fb, ++ 0x32641707, 0x2f0172fb, 0x552afd57, 0x7de352ff, 0xa2e3767d, 0x9e91fa37, ++ 0xcc33f6f7, 0x9e33af0c, 0x07e08213, 0x3f1ef3d9, 0xa0a17288, 0x89be5f4e, ++ 0xd8a67faf, 0x6f22f082, 0x112d9e89, 0x119367f8, 0x9c39874e, 0x70745c28, ++ 0xe1110a0a, 0x3d3d3144, 0x2e1ba135, 0x596bbf79, 0xbce6760d, 0x4bde024d, ++ 0xc2add71a, 0x157eb8cd, 0xb53daa8e, 0xd397f780, 0x64ef8354, 0xe151708c, ++ 0x1747846c, 0x78f00ddc, 0xa933955a, 0xc9f80c64, 0x3941ba50, 0x112ff813, ++ 0x137c2bfd, 0x73deea87, 0x3ff970d4, 0x64e262a6, 0x099f4eb8, 0x3eb4cd7e, ++ 0x1bd16abb, 0x631e14c9, 0xc1a773df, 0x78c37a76, 0xfdee1fb3, 0x513b5ab6, ++ 0xf874aa0e, 0x66c3a715, 0xbe9ecfde, 0x3cf093a5, 0x40b828d9, 0x5b09290f, ++ 0x9425ae11, 0xc9b4ad1e, 0x4e5f4da1, 0xe17570e5, 0xbe469d7b, 0x983c513f, ++ 0xeea4dce0, 0xbef64157, 0xc3134c67, 0xc31d494b, 0x44e93a4b, 0x95717efb, ++ 0xf5d309e0, 0x422e3714, 0x3e5566bf, 0x16bb3fd3, 0x57e8114f, 0x04bf448a, ++ 0xdd199a8c, 0x6f0166fb, 0xf15cc337, 0xcc1bdc0e, 0x8351fca0, 0xf7ff4864, ++ 0x397df42d, 0xbe23147f, 0xb974e0be, 0x076ae00d, 0xfd3275f8, 0xbe35fc2b, ++ 0x4beb51fb, 0xae0e80a4, 0xc8ba9f93, 0xe0af6fe8, 0x174bfb06, 0x699e80dc, ++ 0x6e1558fd, 0x8780cf40, 0xf2112ca6, 0x7dde14d9, 0x2f5cf606, 0xf969bfdc, ++ 0x09ef6f3e, 0x8233ffd6, 0xf7584487, 0xefefa677, 0xf1bdd748, 0xfa0657fb, ++ 0xf3b5bdfe, 0xefa018c8, 0x3df202bd, 0xddd18a69, 0x999a25a3, 0x4ad5b15e, ++ 0x6fee00f9, 0x9b3d94de, 0x83e53ddd, 0x0ce0ccc5, 0xc6b709e7, 0x2c0d72be, ++ 0xeb17fc04, 0x867fe82c, 0xf4c418f3, 0xdebcad55, 0xb3f12566, 0x3fef7bd2, ++ 0x9bdff781, 0x47e6a4be, 0x472078c1, 0xc378e91b, 0xee33c7bb, 0xe0fdaa17, ++ 0xfc1aeb72, 0x1d4bae4f, 0xe7fabbe7, 0x00895094, 0x9faa2ff7, 0xbfc9924e, ++ 0xfd7b865c, 0xf7a48269, 0x78e4eb77, 0x4ffba7fe, 0x7fa5be51, 0xbdd16492, ++ 0xb459bcbf, 0xdb850093, 0xf9195e67, 0x6f196a85, 0x63fd804f, 0x6907dd12, ++ 0xb191d9f2, 0xf587deef, 0xdce7de22, 0x453ebbf1, 0x0775df70, 0x7722c9f3, ++ 0x3fa80aa4, 0xc6ce851c, 0x216e1e81, 0x921f335e, 0x1f5e67d6, 0x12778413, ++ 0x9315b5a9, 0xd3af94dd, 0x90e582ea, 0xc677267a, 0x35f01efd, 0xaf802451, ++ 0xc99f6f66, 0xf83effb0, 0xab854909, 0x6027aa5d, 0x4987693f, 0xef1bb43c, ++ 0xcce3c78d, 0x8fcf86b8, 0x37e745dd, 0x71e888ee, 0x0f3376d3, 0x67c0edd9, ++ 0xc44dabc3, 0x78cb81af, 0xbb072c12, 0xde93b8d3, 0xe41e40bb, 0xde07bd52, ++ 0xd536e42b, 0x5f213b94, 0x25f7e02d, 0x2754ff01, 0xaab6df9d, 0x05af53f3, ++ 0x41db40b9, 0xacd52537, 0xe0ad495d, 0xecd99701, 0xdfe8f5a6, 0xe02b5d92, ++ 0x416db883, 0xbf585881, 0x77ed0b41, 0x3efd355b, 0xfa2ff61d, 0x7b5bf43d, ++ 0x205dd8fe, 0xf13ce877, 0xff767afb, 0x73bf4d9b, 0x2ed49f03, 0xaaf2fec2, ++ 0x2aef0205, 0xfed9eb72, 0xf6447b94, 0x81c37d40, 0x4eefb84d, 0x0f25e3a7, ++ 0x3c28fd84, 0x8ca7df05, 0x2ef85c11, 0xe50536b0, 0x182c074a, 0xc01dc83e, ++ 0x9e05e3ee, 0x551fe7e7, 0xccc4fbff, 0x3db384fc, 0xb43e95cb, 0xc667df9f, ++ 0x3d21340f, 0xdd7bc79d, 0x7ede1493, 0xdca3ef0a, 0xe650e23f, 0x668b4ac7, ++ 0x0659347f, 0x682ffd23, 0x037e889c, 0xfd0f890b, 0x638c6606, 0x375be77a, ++ 0xef60835a, 0xecee4b7b, 0x6e87e50f, 0xfb796334, 0xdb872636, 0x7da0b407, ++ 0x4cb554f7, 0x79453de0, 0xe27288b5, 0xef8cbd54, 0xd867c540, 0x36ce797d, ++ 0xaa1c87a6, 0xaa9efd66, 0xe4dbfa63, 0x15307e67, 0x2d9ce1f6, 0x2aa8ddec, ++ 0x6873d5a7, 0xb74f2bb6, 0xace519bf, 0x388b872a, 0x6a2b723c, 0x28d6def0, ++ 0xfdd48b77, 0x8b6f20d0, 0xef173ee0, 0x47c8c36d, 0xbfa32145, 0x5cfbbd92, ++ 0xfe10f403, 0xf8bbe91a, 0x5ce04c88, 0x36dc7c23, 0x60a3fd15, 0xe3f5a7bf, ++ 0xdc2f049a, 0x67bee7a3, 0x1e3ea20e, 0x63f79acc, 0x37de67d8, 0xd0827813, ++ 0x72a0f80a, 0xf9dcd32a, 0xf96827e7, 0xf016a399, 0x93f4a144, 0xfd57f085, ++ 0x30b7d34e, 0xa3f4923f, 0x7ef00995, 0x83e94c95, 0x4aa72072, 0xdc8d7e24, ++ 0xef782338, 0x0fed87ba, 0x697fad2e, 0x0d9152ba, 0x85ba6cfb, 0x16f747c9, ++ 0x7f1fdf19, 0xf447cfc0, 0xa17e80bc, 0x27d7bb79, 0xc87a1a28, 0x813ebbdb, ++ 0x9ab20e8a, 0xf3945ffb, 0x0a79cb77, 0x9f6f271b, 0x8cd1aae0, 0xf6a3f6a3, ++ 0xdf66ecab, 0xd2cbde0d, 0x83cffade, 0xbf3ae1f9, 0x186e4050, 0x7e31e9fb, ++ 0xfe64fd2f, 0xbc2562f1, 0x4b7ccf33, 0xcce9e744, 0xd60fa78f, 0xa9a827de, ++ 0x38ce676a, 0x0d5e2266, 0x1cff32fc, 0x7c1abc45, 0xfca58c37, 0x7b77f14f, ++ 0x1ae7d323, 0x8a509ec6, 0x02ef31d2, 0xf6e62f7e, 0xec29e2e8, 0xf521a89e, ++ 0xffe04ae8, 0xd202e9e9, 0x95f80903, 0xbfa8713e, 0x39ffc1b9, 0x9f7d9d27, ++ 0xbe07bf43, 0xf8c4d86c, 0x370bca94, 0xeae293c8, 0x7db153f5, 0xfe86e0ad, ++ 0x50b26a1b, 0x14cdc92f, 0x9ed7d609, 0xb7293d40, 0xf01c44f1, 0x4adfe533, ++ 0x278a07d0, 0x8e205d98, 0xf954be55, 0xafee2dfc, 0x51ae2c4c, 0x35605ef0, ++ 0xfe045530, 0xae108f16, 0x2cbe32b7, 0xfb7c64c9, 0x561936d6, 0x8e7c2578, ++ 0xb1f2ad7c, 0xde9c7c08, 0xaa87c7cd, 0xd7c02b27, 0xfa0282a7, 0x39064c6b, ++ 0x55be7c00, 0x7a619bf5, 0xf9f295ec, 0x22ccf4e5, 0x5fb0bfca, 0xf2ae7caa, ++ 0x9b9f91b5, 0x305996a5, 0xb46f078f, 0xdf263ae2, 0x079dfbb4, 0x7bc2bc99, ++ 0x2d37c9be, 0x98f9004b, 0x21bf312d, 0x1245ae15, 0x31eb33f3, 0x4ae5caaf, ++ 0xcfcc95f2, 0x66ad8f30, 0x03e4bdbd, 0xa7f30c73, 0xee9195ae, 0x3d9fc72f, ++ 0xf90aecf8, 0xeaf94af3, 0x8ea9fc72, 0xf7d5ee2f, 0x710001f3, 0xdafecf6c, ++ 0x14c31c29, 0x7fa9bf8e, 0x3f4dfd0e, 0x0cc4f17d, 0x1ec143c0, 0x5f40e74a, ++ 0x06120ef5, 0x71052739, 0x106fcadf, 0x2b8fe8bd, 0x72ee3385, 0xf998f968, ++ 0xe4bc150d, 0x7fca7a40, 0x4e9c1cd9, 0xf5dfcfbf, 0xdff468f1, 0x7e89d158, ++ 0xb9178150, 0x19681cbe, 0x2f907c0d, 0xa325ff31, 0x30b3c85c, 0xb76db9fd, ++ 0x4fac366d, 0x12f163a8, 0xcb7743f2, 0x853dcd66, 0xb8e322df, 0x27de1db4, ++ 0xc31d2806, 0x9f98527b, 0xeabe9df6, 0x95b6d4b7, 0x46fc89c9, 0x17710839, ++ 0xb476ebf2, 0xfe6aff83, 0x7fb4667b, 0x479dd495, 0x2fc9fcff, 0x4afb436d, ++ 0xbba8a349, 0x2fe1eb87, 0xcd862758, 0x50d6e7e0, 0x3486f784, 0x21f3027f, ++ 0x1df79fee, 0x5e0ad9fd, 0x402bbbda, 0xebf05841, 0x5f209c17, 0x716f36ce, ++ 0xbf69dc02, 0xdbbfeadf, 0xf4303fc3, 0xbc0ff728, 0x73c114fd, 0xc0ff644d, ++ 0xca0ff0b3, 0xf4584f28, 0xaea481fe, 0x7497ea0f, 0x08be199e, 0xfa5d1ff7, ++ 0x9e2fb6f9, 0xb6f6ff05, 0x0b3dcf97, 0xfbfc2ef3, 0x3f82cf67, 0xc567d912, ++ 0xc5e4af7d, 0xb81fd1b7, 0xf7c1dceb, 0x2fadf6bd, 0xfb753fa0, 0xf40f66fb, ++ 0x54f7bed6, 0xb5a5f80a, 0x013af8ef, 0xf64b99ec, 0xdef68cde, 0x27273b25, ++ 0x86fb0892, 0x06fd029a, 0xdb9fc0af, 0x0d43b788, 0xea6fd087, 0x90778a53, ++ 0x9f7e5d83, 0x4fe622a1, 0x9efee6eb, 0xe7fd91f5, 0x3677f87b, 0x8dc775dc, ++ 0x981bff20, 0x3f59793e, 0x9f1463cf, 0x1e015dd7, 0x6f3fb9eb, 0xf56ff6e8, ++ 0xfe14fcf3, 0xc475f141, 0x1a2fc780, 0x29f2fe16, 0xd3e86ba8, 0xf8679fab, ++ 0xfaa7e00a, 0xbc5957e7, 0x8f805aef, 0xfa15fe5e, 0xa6fe02d7, 0xfa3f61bb, ++ 0x37de0522, 0xe73b969c, 0xb9d3fec2, 0x63f18cd7, 0x8bbef7f2, 0xf3bed4fc, ++ 0x09a9da28, 0x276f93f7, 0x9fcc7f5d, 0xadebe059, 0x50ff3075, 0x1ff0078e, ++ 0x9cb13b75, 0xba3289fb, 0x7b47fd56, 0xb68d1bf3, 0x7d5bfd32, 0xfb545037, ++ 0xecc7f701, 0x09909bc6, 0xadf13af8, 0x1c2ab97e, 0x772e5c5c, 0xf64745fb, ++ 0x8bf2edd3, 0xf00de036, 0x9754fb09, 0xf7cd33df, 0xc93b434f, 0xecfc91bb, ++ 0x3f986bdb, 0xf91cbb75, 0x27eaaafd, 0xf835651d, 0xccaf0747, 0xeb72fa3f, ++ 0xfa70aef8, 0xc68a506f, 0xdb5784f6, 0xfbe59137, 0x0ff0ab28, 0xdebbef9d, ++ 0xc60a14df, 0xad233df7, 0xe48fc163, 0xbb33da04, 0xbd7cdfce, 0xdefedc6d, ++ 0x7e88a2f6, 0x8743abb3, 0xe51bbe50, 0x01c43147, 0xefdf3089, 0x3716f9f1, ++ 0xeda3fdb2, 0x4ed04765, 0xb83b69fb, 0xb8bae91b, 0xedfa04fe, 0x6bf751be, ++ 0x3fe345a5, 0x5047fb01, 0xedb69eb3, 0x3ca34607, 0x8c46f1e7, 0xc7cedce3, ++ 0x3c8a6929, 0x79fd494e, 0x810538dd, 0x5fb2e290, 0x92b3bc7e, 0xefe86ef7, ++ 0x13d3336c, 0x69c486cf, 0x799fde91, 0x0fbf32ac, 0xdd2960ab, 0x8aae3147, ++ 0x1151c583, 0x77a8519d, 0xbe64712e, 0xa9071d17, 0xe543fe82, 0xd1bfb9cb, ++ 0x80493c4f, 0x6dc772ef, 0x0abbe604, 0xffb1abe0, 0x013f2ec8, 0xf24e557d, ++ 0xc1dd83a5, 0x38947728, 0xf06a0913, 0x2d31c4bd, 0x22f78dd1, 0xcf80fee1, ++ 0x64a7a9e3, 0x8343f7e8, 0x8943eafd, 0xf3a44eac, 0x782030fb, 0xc97ed396, ++ 0xf00f1f37, 0xdff67a39, 0x223c37a5, 0xc54decea, 0x70e3cee6, 0xadfb215e, ++ 0xee211f78, 0x8a3c62b3, 0xb8ad6792, 0xbf3b43de, 0xeef51e7a, 0xbb099a5f, ++ 0x1aa7a21f, 0x62e58388, 0xf9da9c7d, 0x057fb3d5, 0xa63e1abd, 0x4b3ce7e3, ++ 0xa279c3db, 0x9fe786de, 0x47a3978e, 0xffbcfea3, 0xd72019e1, 0x1e8c6c72, ++ 0x0c4a5e73, 0x5afed396, 0x75be59e3, 0x7f8c00db, 0x03b2f050, 0xed0f18fd, ++ 0xf618a57c, 0x6c97f6a9, 0xda4066e0, 0xfffd73f7, 0x535e3c57, 0xfad6ec95, ++ 0xc911e733, 0x52677dad, 0x8f567900, 0x2ff055ef, 0xd811f383, 0xf1a31ab1, ++ 0x8bd50a7d, 0x2a7cfd75, 0x41e43e77, 0x65f40e3a, 0x7dc272ef, 0xdb181e41, ++ 0xb91bf5a9, 0xd3312dbc, 0xedddecef, 0x6cce944b, 0xcbe8af96, 0xb63349e4, ++ 0x73a54e7f, 0x5fb3df5e, 0x3ac6bed6, 0xfd4ed748, 0x4bc798be, 0x76efd231, ++ 0xd9dfc0ab, 0x48eaedfe, 0xcc2240f1, 0x247fcb1f, 0xf4098090, 0x8c561d96, ++ 0xfdef0503, 0x977e8fc1, 0x0abfeec2, 0xc78c619d, 0xe3cb87b2, 0xc630a8c2, ++ 0xe7cbe987, 0x4f21ed01, 0x01db2d2c, 0x58af45ef, 0x2a17c409, 0x02f0efda, ++ 0x7d768bbe, 0x3a74fad5, 0xd0d9c9f8, 0xffb457ae, 0x8a0e903f, 0x18b9e1cc, ++ 0x99876d6f, 0xb6b63c40, 0x00a66f1d, 0xe1c9b6bf, 0xb96fd894, 0x990a2bd7, ++ 0xf9d4eff5, 0x0596ce3a, 0x7e3bc087, 0x7e67fdf5, 0x1cc6722f, 0x3febf4c5, ++ 0xad47bd5a, 0xb8faefc8, 0x1acb6743, 0x83df6b07, 0xcb23bbe7, 0xf2ac4fc5, ++ 0xedc7273f, 0x7e51de3d, 0x94f9f302, 0x01802734, 0xe3ea98b2, 0xebf3cf20, ++ 0xfb028fce, 0xea5187c1, 0x3477797b, 0x2a1f47ec, 0xfe40a39d, 0x39d2987d, ++ 0x9ccfbb4a, 0x25b8b32e, 0x983aed19, 0xcf9cd476, 0xafc04bee, 0x923b3ad1, ++ 0x6acafbdc, 0x3fe47843, 0x7a46f362, 0x31452987, 0x63056aba, 0x171b3c40, ++ 0xf71d43f8, 0x72882543, 0x1b944578, 0x07fbf3eb, 0xa82f2815, 0x0b583ddb, ++ 0x02a93c87, 0x453e51db, 0x4a91e678, 0xbf235d25, 0x96f2f1d5, 0xbe12ddda, ++ 0xbbfe9777, 0x6ec55e8b, 0x5911a33c, 0xee8f0f13, 0x566768b8, 0xb2482bdf, ++ 0x53f002cf, 0x8925cf88, 0xc8152a40, 0x842451ef, 0x5daa9da9, 0x2956fe2c, ++ 0x9a793901, 0x1d83efdf, 0x786ed20c, 0x1fb9432d, 0xd0c84018, 0xc0bf1081, ++ 0xc0d2ed1d, 0xeb2e062f, 0x52cc7ce9, 0x62f26129, 0x4ff40bba, 0x9727e021, ++ 0x97953d28, 0x71660dd5, 0xde178825, 0x4b0aa1c7, 0xbd74e7e7, 0x41e835f1, ++ 0x5c594e94, 0xb0489bbb, 0x0c7f005c, 0x08932796, 0xf6b6c78b, 0x7f3da23d, ++ 0x7c094464, 0x8e5007fd, 0x5ff749d9, 0x5883cd27, 0x1e5b7905, 0xb84cf7fd, ++ 0x48bbb39f, 0x9b43f418, 0x346d849d, 0xce948fb5, 0x99dff96a, 0xba1af34e, ++ 0xd7d04d74, 0xca82f91b, 0x21b8c335, 0xf7ed1f84, 0x9fbf4373, 0xfcfdfa1b, ++ 0xe155fadb, 0x3c196254, 0xac1ce210, 0xb8710b2a, 0x1c2cf1b1, 0xc33e146e, ++ 0x311c6e21, 0xbdf87945, 0x8a35c239, 0xed0cc6cf, 0x45975e29, 0xfd38440d, ++ 0x275f7a34, 0xb892e5f8, 0xe1e7022a, 0x3f1a8295, 0x9aecf892, 0x82cb88ef, ++ 0x1f28f87c, 0x77a71967, 0xcf7d9df5, 0xbfd456f6, 0xf6b7b47a, 0x722a3ed6, ++ 0xf36f477b, 0x4f9e45b1, 0x57fd2f4c, 0xfff622d8, 0xf152e55d, 0x0f7f77fe, ++ 0xf25dbbf7, 0xaf4145c9, 0x459733d7, 0xd3199e81, 0x2c16f7fa, 0xa5a67a61, ++ 0x51df1ebf, 0xde94df40, 0xcbe886a2, 0x8112748d, 0x74c9ecbe, 0xf1f0f7dd, ++ 0xbd8479ee, 0x20e9528b, 0x4a6faf8b, 0xbf27bb2d, 0xe3b3096f, 0x17a363d1, ++ 0xf5e5efea, 0xfd3155f7, 0x4447bef1, 0xc63587bc, 0x9ff13a4b, 0xfdc3ae2c, ++ 0xedf94050, 0x3042a5fe, 0x1c52303c, 0x862c7228, 0xcf8f3bf6, 0xc95718c7, ++ 0xd753dc4f, 0x2ae2918a, 0xdf54ba31, 0x29e3197b, 0x1e3e202c, 0xfe5f4b2f, ++ 0xc98bab77, 0x54a82961, 0xc7deec8c, 0xdd29eb02, 0xe949fe83, 0x44bfee1e, ++ 0x3897befe, 0x3dc7e615, 0xff27562b, 0x47770c2e, 0x5e4d7ec3, 0x562ee5e3, ++ 0x3b9c78be, 0xdf234631, 0x5d368ba5, 0xd972995c, 0x4df20493, 0x712d78be, ++ 0x2e543e53, 0x4d6e21f6, 0x915bd53d, 0x13cdc1f9, 0x149254e5, 0xb928b904, ++ 0xf407247c, 0xcf4618de, 0x6e257b6a, 0xf99e9744, 0x476ffd16, 0xe5f23c54, ++ 0x44ee45e2, 0xcd98e718, 0x49e81077, 0xfc7a6674, 0x10f49ef6, 0x5dd6c6d8, ++ 0xd81eeb0e, 0x8ae53d73, 0xf6fa83c7, 0x3c38aef8, 0x689f9816, 0x86ebbf76, ++ 0x2656fdf9, 0x09e98760, 0x20e9cf1f, 0xec10bfad, 0x62247e87, 0x3061f4f4, ++ 0x729f1abe, 0xa4afc42d, 0x1e4ac0fb, 0x8f2572cf, 0x8f18f95f, 0xc79aba37, ++ 0x67e154b5, 0xdc6054f1, 0xd610cb44, 0xf1c5c5bf, 0xf0e26713, 0x657ea3f1, ++ 0x7bc52a49, 0x34abab45, 0x48c7f10c, 0xc0afba7f, 0x08155db4, 0xd045c53f, ++ 0x63db499e, 0x9a790cde, 0x112355ca, 0x94ab920f, 0xedfad0e4, 0x801b7f36, ++ 0xc7d6ead2, 0x0d273457, 0x1b23dc32, 0xd3d2a9e0, 0xe3472626, 0xe1193d38, ++ 0x78b0a713, 0xf51d2aa6, 0x739587a6, 0x1e72dfff, 0xe21cae4f, 0x6cb8511a, ++ 0x5a62f328, 0x951be3ce, 0xbcb1f853, 0x7e78d307, 0xcb2f2cce, 0xf927fac4, ++ 0x365e5bbe, 0x3659d30d, 0x99c5cfb6, 0x00c80f4a, 0xecc258a7, 0xd20171a6, ++ 0x5730833f, 0x0a4bf853, 0xd5e43710, 0x3d5ac87b, 0xc92e887d, 0xfdcf1710, ++ 0xf2a9e024, 0xf704d94d, 0xefd2e2c4, 0x8aa3deeb, 0x6031bdb3, 0x7eed1387, ++ 0x9fcff601, 0xfce99e02, 0x6279d3d6, 0x1f4e599c, 0xac1d38ab, 0x28f1f4e1, ++ 0x33fa778f, 0xd38f274e, 0xdcbe4275, 0xac2bdec3, 0xeafcc69b, 0x3c4d52e2, ++ 0x68985c2e, 0x3c62d6fd, 0x75d0a221, 0xc6ed0ea2, 0x91fee314, 0x3f48ccf7, ++ 0x2bc491b6, 0xcb7bfd42, 0xa78e2c82, 0xddf6192f, 0xe76e3518, 0x1ccc7704, ++ 0x961b887c, 0x913c7c78, 0x239a5b9d, 0xf72cbbc6, 0xf9c0b41c, 0x1cf9b7bf, ++ 0xc08bb998, 0x21d7d978, 0xbf1f487a, 0x9a42ce6f, 0xfd5157b7, 0x3cd9fe9d, ++ 0x40558cfe, 0x020e55df, 0x3a76727e, 0x9d0d1cff, 0x23b17ad8, 0xeaddb49c, ++ 0x9f7e51b5, 0xc50a8a08, 0x06aa2fef, 0x14ce015b, 0x97b06ee6, 0xc97d906c, ++ 0xc4361720, 0x8cfbb644, 0xb9f3b1b0, 0x8e847d33, 0x2f652bce, 0x909ae77e, ++ 0x4a87e3a6, 0xa7628f2e, 0xab95d78c, 0xc6ce27f2, 0x3663f7f4, 0x4d1b2cff, ++ 0x214e2e13, 0xb8bdca84, 0xa3cb233b, 0x40095972, 0x51f2829c, 0xb205fe4c, ++ 0xf5a7a614, 0xed042f90, 0xc3fc17f1, 0x45bd8336, 0x8415b3a5, 0x6100b3c9, ++ 0xaeba8bfa, 0x28f7408d, 0xff485c77, 0x681f812b, 0xb0a21c5e, 0x99f7ad78, ++ 0x9abbbcf0, 0x9c63dbf3, 0xfe71d6cf, 0x97f039fa, 0x7aefe219, 0xe705fd30, ++ 0x43e04aab, 0x31b0ae9a, 0xcf18c87d, 0x0d25857a, 0xdb95dce3, 0xa49f284d, ++ 0x3b41cdf7, 0xc607a1e8, 0x20cec0b9, 0x7e5dd23a, 0x5ba7d407, 0x110f70bc, ++ 0xba02ee93, 0xe0b1d2f9, 0xbbf36faa, 0x78c7e8a4, 0x878f12ab, 0x2ebfc6ad, ++ 0x21aaefe7, 0x45d8363e, 0xb52b8c9f, 0xd9179c02, 0x2aac79d8, 0x4ee1032b, ++ 0xa6c6b1f1, 0xce240f39, 0x4e2badbe, 0x64ff7419, 0x9fb3ef2f, 0x87bd31b0, ++ 0x21900ff4, 0xc551391a, 0x7711e0e3, 0xc8d70c80, 0xa743158b, 0xf523b012, ++ 0xc8bd1394, 0x6e4c2dcd, 0x3f7c0b96, 0x9cbde032, 0xe55727c7, 0x8f7804a6, ++ 0xd56c1f10, 0xef74d355, 0xf72e64c9, 0x6deaed8d, 0x9ab65cec, 0x42fd3a78, ++ 0xa70a7acf, 0x949c2d7a, 0xcebadbb8, 0xb08bdfc5, 0x3c7ca30e, 0xc826fb0d, ++ 0x718fc91c, 0xee281652, 0xdc81c727, 0x8fe62ff9, 0xa15e9bd3, 0x3173978e, ++ 0xeca5f70f, 0x5f50e38b, 0x15baadc8, 0xb70243f7, 0xe3f79a00, 0xe47faaa7, ++ 0xaa9ebc04, 0xd5b3f7e2, 0x63fc1072, 0x2aad554e, 0xd5857cc6, 0xf899380d, ++ 0x884e658b, 0x59e0b32b, 0x4f6bef11, 0xd0520547, 0x4b9bf0bf, 0xff8d4497, ++ 0x359af2c5, 0x0b874029, 0xf7c1af36, 0xbd63a77f, 0x3c9a7cc3, 0xbea37749, ++ 0xcb9bc6a8, 0x05ecce7e, 0x7a37af7d, 0x6c8eaecd, 0x7f87284f, 0x3c4c1e82, ++ 0x3dcf41c3, 0x19df1ce0, 0xfd3ff8a6, 0x9dea2b0b, 0x1da04ae5, 0x6d9be5f2, ++ 0x8f2905f0, 0x64bf1c8d, 0x77e6edbb, 0xb76cbe40, 0x94843f79, 0x3ef163d8, ++ 0x61fe77a1, 0x2d82b7e3, 0x9ef5ee17, 0x285c71e2, 0xecea669e, 0xaf5eec7a, ++ 0x8869db95, 0x28fa97a5, 0xa5eeef5e, 0x70fcc9de, 0xfd722b88, 0x18df6c3f, ++ 0x20fce3d9, 0x50fce1d8, 0xfbf56e75, 0x53b7a258, 0xdfe7e19f, 0xc16d9b05, ++ 0x92f41115, 0xe51dfc05, 0xa31f7e02, 0x2e99e3d2, 0xb1d18ffd, 0x4a42ff3a, ++ 0x068f4897, 0x185e17ba, 0xd9fe7485, 0x37f71961, 0x311b85e1, 0x45f14d8e, ++ 0x42ffca2b, 0xf838f3d1, 0x44b793a7, 0xdf0783e4, 0x71f78b1c, 0x9a78866d, ++ 0x4f4cec63, 0x8becd351, 0x397d3a05, 0x015f383b, 0x62fb227d, 0xb013e331, ++ 0x8161839f, 0x5131bfc4, 0x1e3cf4e2, 0xba998fbe, 0x69cbb682, 0x2644fc61, ++ 0x3ed18a04, 0x80f3635a, 0x1f48cd1d, 0x9d6eec63, 0x4b4e635f, 0x1ecefb21, ++ 0xff1a7120, 0x2e3c0585, 0x1645ce7d, 0x02b8923f, 0x88f80924, 0xfa6ebfcb, ++ 0x6e0fc7d7, 0x307a3133, 0x5f0a77ae, 0xf5ae94e7, 0x7acbd0de, 0xe5eb626f, ++ 0xcb4e49fa, 0x9ebac338, 0x5d69171e, 0x8099ebdd, 0xbc790bed, 0xc31342e7, ++ 0x645f5abb, 0x4d5e7267, 0x1366cb5b, 0x79a7952f, 0x7664fe3c, 0xe40541f0, ++ 0x4c757648, 0x6759a0ac, 0x3abdd54e, 0xaaec9b3f, 0x96538c2c, 0x3ca59d53, ++ 0x2edbe1a0, 0x3a3c053c, 0xbbad153c, 0xd274f116, 0x07639be6, 0xe8be7cfe, ++ 0xf40957a1, 0x5a76f0cb, 0x452e8c09, 0x33a0f739, 0x229d3bd2, 0xed58dbc0, ++ 0x86de387c, 0xed48c804, 0x918ba97b, 0x6eb67de3, 0xee087829, 0xb1375beb, ++ 0xcbbd2ba8, 0x34f8c8b3, 0xc72d71c2, 0x52b69aa3, 0x457fc23d, 0xe756bc70, ++ 0x1c2bd5ef, 0x3855fe39, 0x0f54e5a9, 0x60720e5c, 0x58ecf02d, 0x15dc6fe8, ++ 0xfc7bafc1, 0x77bdbc09, 0x8f9026d8, 0x9f031e54, 0xa7fe799e, 0x6ddfb5a3, ++ 0x19fc4db7, 0xae2a438c, 0x64d05eec, 0xbc046ff7, 0x0e792606, 0xb031f9c3, ++ 0xd394f459, 0x3f45e775, 0xd5c61ed5, 0x55d3f7ea, 0x83878765, 0xacbcb89d, ++ 0xeb995319, 0xbbf40477, 0x7eae2c81, 0xbb5d78a4, 0x2aaedd39, 0x2e76666b, ++ 0xc0b8804b, 0x5f18499e, 0xd063d392, 0xf5d927ee, 0xfb22897a, 0x5467605d, ++ 0x596f3bf8, 0x981daff2, 0xb8f2e70e, 0xbe0680d4, 0x3c59d8af, 0x074975af, ++ 0x363f605d, 0xdec1fed3, 0x5d2fe960, 0x5e29d9d0, 0x28381693, 0x5a61a9dd, ++ 0x2bc848a3, 0xb9b76808, 0x5cdbb060, 0xae23cdd0, 0x35d76759, 0x38b245c2, ++ 0x2247bef1, 0xe1c75edc, 0xc94efea1, 0x2b872e1a, 0x236fddb9, 0x8286fbd8, ++ 0xfdc4ea9e, 0x2655f56e, 0x48b1ce76, 0xdc068718, 0x12bda090, 0x0561d6cd, ++ 0xe708b17b, 0x1de6308c, 0xc447b110, 0xe40267d0, 0x805b8863, 0x5e121f7c, ++ 0xc7737a0d, 0xa08796c4, 0x7fd5917c, 0xcbe1e814, 0x02e3e6e4, 0xfe7d7fd8, ++ 0x55ce01ab, 0x4dd52062, 0xec52ffdb, 0x2976854c, 0x58bdeab4, 0x7e055e96, ++ 0xbdcd7ee1, 0xda978b12, 0xe67b179d, 0x192a5aaf, 0xb9be59ee, 0x47ff5b5a, ++ 0xe805b7ab, 0x357bf8cc, 0x280b1f71, 0xaab19eef, 0xdf0f99fb, 0xf1c37d37, ++ 0xf401f489, 0x03e99875, 0x74772417, 0xba1fb32c, 0xc9d9d35f, 0x34d7ee2d, ++ 0x3cfc49e3, 0x15e94b56, 0x3a5403ee, 0x4d792219, 0x2b434f40, 0x2e96b968, ++ 0xb17de822, 0x1c1b0c76, 0x9d453ef1, 0x006fbc1f, 0xa7178a78, 0xa46a3ee2, ++ 0xf65d3d8b, 0x367bf657, 0x93c25473, 0x0c7cb256, 0x9cf0ff51, 0x7d977ef2, ++ 0xbbcb257f, 0x01e4ae58, 0xa7f89f76, 0xcbf468ac, 0xa731e753, 0xe8334d69, ++ 0x929a7379, 0xd2fdc3e7, 0x3fabdc9c, 0xdc8f7481, 0x7206d079, 0xde2c47e2, ++ 0xbf6f3de9, 0xba68db26, 0x7c66d8f3, 0x60e89e2f, 0x749738fc, 0x3f7f80ca, ++ 0x7eec2971, 0x0fe58820, 0x87cf0f10, 0xdf773864, 0xe0fe0e17, 0xffbb9a76, ++ 0xa0ede0b5, 0xdc3dccbe, 0xcba03af9, 0x454d721f, 0x5dfabc1b, 0x960de7a3, ++ 0xad75df67, 0x7ae0b25f, 0xc16bd7ba, 0xa3ebabf5, 0x77f84533, 0x63c787c1, ++ 0x6931e152, 0x1cf75b3e, 0x91b7bddb, 0xe76bd16f, 0xc27d4658, 0x7cd89ffc, ++ 0x1cf9f08c, 0x4c5ca8aa, 0x1cd37871, 0xf0e1deb4, 0xd0b4818e, 0x0d2299d2, ++ 0x1eb97e42, 0xffa2c5f2, 0xfeba04aa, 0xaff8074f, 0x3438078e, 0xfd22b9f7, ++ 0xc995b8f5, 0xdf40e381, 0x03e3bc74, 0x8f06f3d5, 0x87185f8b, 0xe9c79aeb, ++ 0x53cef56c, 0x7e0f5f6f, 0x38b26f49, 0xfba24553, 0x8ed1878e, 0x71489227, ++ 0x38f4d56a, 0x1cfb2f3f, 0x20d67bea, 0xf8c3ef8f, 0x0d835e65, 0x5bcc0ddf, ++ 0x5de2ea2a, 0xfcca5bcf, 0x3cd48907, 0xef4e967a, 0x3f6bd95d, 0xf6379e70, ++ 0x64e97f33, 0x52ede73c, 0x7cf1135c, 0xb3a32cff, 0x22bc53f9, 0x5f8f5df8, ++ 0xe7bde02b, 0xc6ee93b8, 0x1f9f9a16, 0x9b00f18c, 0xc7f65fce, 0xa24f10c1, ++ 0xf9d999b8, 0xa945c512, 0x86e9a13f, 0x85ff6c83, 0x938022fc, 0x6bb6ebdd, ++ 0x726ddfec, 0xe80baa69, 0x17bb7ef9, 0x2cd640e4, 0x5780fbef, 0xeaaf7cf5, ++ 0x7dd0af11, 0xb2e8fc19, 0x026773ee, 0xac85649d, 0x442d4c5e, 0x2d72a28a, ++ 0x4816224b, 0x59221513, 0x16228d21, 0xb0563348, 0x55d9e2b8, 0x773f7133, ++ 0x8814fa66, 0xf4d59c2f, 0x7df017c2, 0x203e148e, 0xab2ae868, 0xf1afcde9, ++ 0x87d7925d, 0xd6d7927e, 0xd4f3ba29, 0x7f3e90a8, 0x9f3ea35d, 0xc7e7d61a, ++ 0x8fe7d61c, 0xe943ba83, 0x3dff3c69, 0xcd7b83b0, 0xa82f7e04, 0xfa3325e0, ++ 0x7b0abeed, 0x5a3ffa05, 0x2e4e2e51, 0x7b80ca68, 0x1ddb73e5, 0xedbbb026, ++ 0xf1afdbf9, 0x9b73ba5e, 0xd65f808d, 0x91453f81, 0x7c7bf028, 0xea19bac9, ++ 0x609f680b, 0xc9782c67, 0x07fe035a, 0x74a846bb, 0x91ff441a, 0xef677f5d, ++ 0x9ab73a03, 0x7d4f7083, 0xdb0bf76e, 0x6dcf2e81, 0xd17a87ed, 0x04c042ab, ++ 0x651e05fd, 0xc51f1f78, 0x147c7ee8, 0x3a82fba3, 0x57f2f9fd, 0x7adf550e, ++ 0x7bec046f, 0xbc1963e3, 0xb04ecb5b, 0xaeeb8f3c, 0x79e353ea, 0xc5177e3c, ++ 0xbb2347e7, 0xf39c3cf1, 0x01f0764d, 0x5af88bc5, 0xacf2051e, 0x0f328ce3, ++ 0x57572bec, 0xd2a8e1e9, 0x7d4135f7, 0x7f970379, 0xf94d100f, 0x77dfb840, ++ 0xfd824eaf, 0xf11239fb, 0xce1ee77d, 0xa8be2f6f, 0xf220fca8, 0xadc471f8, ++ 0x2dd68779, 0x7e92c9f7, 0xf8017fe0, 0x5e5dd41a, 0xed571860, 0xffde61ff, ++ 0x7fe61667, 0x70e1c71d, 0xea30ecb6, 0x717a5d0d, 0x453bd799, 0x3aaecf93, ++ 0xf0859090, 0x80f0903b, 0xf5b83cf6, 0xe0bdc250, 0xe1275457, 0xce1583ef, ++ 0xe3e7fe79, 0x0c5ca0e3, 0x1ea13cc1, 0x7a16d8e0, 0xa8ed09dd, 0xf5a69bde, ++ 0xbaa9c9d3, 0xc3453bd9, 0xce95dff7, 0xbb8ee2bb, 0xc95e5c18, 0x3b75ddf4, ++ 0xe8b55dd0, 0xa1056681, 0x147f7c1f, 0xc65abbc0, 0x3b85c7f7, 0x5f838c64, ++ 0xda037352, 0x8fea0a4b, 0x8a78c54e, 0x303cb29b, 0xf8890caf, 0x753434c4, ++ 0x74f482cc, 0x3f8c4ed3, 0x4a97f058, 0xe5094205, 0x8ee9e954, 0x8fc231d2, ++ 0x77195a6a, 0x97794f02, 0x5ab09fa3, 0x5e6fc46e, 0x11bdff50, 0x5053b24f, ++ 0xd70eb2e3, 0xaed8dbe2, 0xbe00f4cf, 0x4a5c2d17, 0x1ec69de5, 0x02b27856, ++ 0xe38d12fd, 0x977dcdc0, 0x037a657c, 0x6d7f0371, 0xf429fe63, 0x7064b04f, ++ 0x2cc1ddff, 0x8112718f, 0x23fd60ae, 0xbc3714c8, 0x4c93bd37, 0x1b955483, ++ 0xd1a1996d, 0xa155fed0, 0xb1a7f9e5, 0x6bf2073f, 0x718c2b9b, 0x77f2fb23, ++ 0x966e6db8, 0x433f7f57, 0xb26fcfad, 0xb9cb3fa2, 0xa394154f, 0x0e8fc1cb, ++ 0x9ab76fda, 0x3b8f544c, 0x24cfa3b7, 0x0b6ccff0, 0x67c3b8b1, 0x29267d43, ++ 0x1b3fb2df, 0x6fba82e5, 0xd27f809e, 0xd38475fd, 0x7a09d43b, 0xbfe64ad5, ++ 0x34a7d89a, 0x9e0234b5, 0x94e2efd4, 0xb73854d2, 0xf76fde74, 0x0538466c, ++ 0x87684a06, 0x423b424e, 0xdc9bb716, 0x39a5f2e6, 0x6da7bf61, 0xd8bff4bd, ++ 0xa066e2c3, 0xcf458faf, 0xddc1ae43, 0xd20b93f7, 0x096ef8fd, 0x8e82e87f, ++ 0x61225f3f, 0xf3c5ea89, 0x8d19bf61, 0xe717dc79, 0xc7e80b57, 0x7e9d60b5, ++ 0x56f7103d, 0x92e64fbb, 0x9f37ec0a, 0xadcd3084, 0xc1e7d7d6, 0x95e142be, ++ 0x0afe616f, 0x7afab5f9, 0x61543df5, 0x247325fd, 0xd4417db8, 0x03a779f5, ++ 0x2d3b84dc, 0x3707bf38, 0x17fbb344, 0xdf617885, 0x40e0dcec, 0xfc405e39, ++ 0xf87b8f38, 0x2cb25dfe, 0xa680bbcb, 0x7be74b1d, 0xf781f417, 0x439f6cc8, ++ 0x64be4196, 0xa60ab371, 0x1600f090, 0xfec084c7, 0x8424d059, 0x42de4147, ++ 0x5634ce02, 0x601cf10e, 0x3c77dafd, 0xdd61faea, 0x8c7272da, 0xde1f37e1, ++ 0xdd6c888b, 0x0e42fada, 0xb37ac28f, 0xbe317ece, 0xae38085e, 0x2d257783, ++ 0xc3715df8, 0x5faeb325, 0x7dd33fbe, 0xde29589d, 0x88d6e7c6, 0x5d0d98b0, ++ 0x4d7838f2, 0xc70277a4, 0xfc371c39, 0xf8193b20, 0x53d071f6, 0x674072fb, ++ 0x0818f212, 0x210cf1cf, 0xd45e3a16, 0xd63cae98, 0xf960ac67, 0x4df9fcff, ++ 0x3aa3d0b7, 0xde1f4efc, 0x7d17cccf, 0xb3fbc06f, 0x15fe5c8f, 0x4df37f40, ++ 0xf90914de, 0xed0c3bd7, 0x1c194b80, 0xbd2b4c9e, 0xb9c234a6, 0x46f3c559, ++ 0xa7f78421, 0xbf6cdd81, 0xca77a475, 0xd555f7da, 0x1f452e5c, 0x1777c16c, ++ 0x7c053b9d, 0x3849b9f7, 0x3722ef81, 0x7026eadd, 0x78a24fae, 0x49b9b902, ++ 0x6e212b20, 0xccc37a59, 0x9e03af45, 0x703ca3d3, 0x30d45b2f, 0xe3b22c51, ++ 0x663e99fa, 0x7b81ad2b, 0xc379c492, 0xe9de80d3, 0x49dde7ba, 0xdd3b37cb, ++ 0x3b64af38, 0x8ad27bc3, 0x23c5c0c0, 0xa2df7c61, 0x471f81d7, 0xe13be145, ++ 0x472b0a44, 0x416ba62c, 0xa9224acf, 0x27be4007, 0x81a7774d, 0x938379ad, ++ 0x126f138d, 0x3d04cde7, 0x63e58d30, 0x9bbc111f, 0xe3d70891, 0xf6668938, ++ 0x0e5054d3, 0xec05a37a, 0xbe0d760c, 0xc2a69727, 0x598389f8, 0xfb84a71a, ++ 0xba473f43, 0xbd47eef0, 0xa08b897b, 0xf5f25ebc, 0xdf3844c4, 0x07a3691d, ++ 0x8ec72a6e, 0x9fcf57f4, 0xe9ea3b61, 0xf6b38643, 0x9258df5c, 0xc425deca, ++ 0x127aa8a5, 0x7b21d76b, 0x5c80c7a3, 0xf5f4ca3d, 0xb45eedcf, 0x44a0decf, ++ 0xc23e83f6, 0xd17254f1, 0x7d9a8246, 0x97f664a1, 0x5c9647a8, 0x21caea74, ++ 0x9fd69f0e, 0x20f730b6, 0x222f49c6, 0x5d97e8cd, 0xfffbd214, 0x791510de, ++ 0x4bce955c, 0x10248a2e, 0x5f455c71, 0x090fb17e, 0x2ed489f4, 0x517e5f41, ++ 0xbf1be7d0, 0x2c24ede2, 0x4e2d9927, 0x874e0738, 0x3be688fd, 0x7c80a682, ++ 0xda5e375d, 0x7dba2d5d, 0xf2cddda8, 0x4bbefc1d, 0x6ffb57ad, 0xf7f0ad9f, ++ 0x725e2c49, 0x4015195b, 0x354f3e14, 0x6c3b479d, 0x8401d361, 0xdd174a8f, ++ 0x8091b270, 0xe5094e06, 0xe51361cd, 0xc0f1f171, 0x50d7919a, 0xf9c83b12, ++ 0x8d62b039, 0x026ff297, 0xf0d787c4, 0x8bbd2db7, 0x6cdc51df, 0x5edc8930, ++ 0xca66be5a, 0xb79e4d04, 0xb03efaef, 0x942996f2, 0xb247d2b6, 0xaf8f1def, ++ 0xf00acdfa, 0xb7f2e899, 0x39f14cee, 0x218b7934, 0x51f9a76f, 0x50cbbc9a, ++ 0x4fa8671f, 0xb3fbe432, 0x708e6df6, 0xd5a1e88a, 0x0b7a3f8f, 0x5b602efc, ++ 0x442e7872, 0xae27585c, 0x377e05bb, 0xfd9d28b4, 0x9371660e, 0x723411e0, ++ 0xeec3d8b4, 0x169eece9, 0x8048fe65, 0x201bf343, 0x051b0a0f, 0xec039c17, ++ 0xcc611da1, 0xcd6e77c3, 0xce762177, 0xc09d0c2c, 0x7fed7aef, 0xf9f909b8, ++ 0x611fe1b1, 0xbbddcbbb, 0xdffae990, 0x1eede9c5, 0xf7e4c926, 0xc777c744, ++ 0xf1db6e67, 0x12eff76e, 0x64f6f2d2, 0xa79421ef, 0x25baf786, 0x377b1f30, ++ 0x7c70a8bf, 0x8c05f86c, 0xa8c1f957, 0x3d41b7a6, 0xbf392db0, 0xbfcdf41c, ++ 0x0b1a9d14, 0xbcc417fa, 0xa363fd84, 0xf606bc10, 0xff88a7a5, 0xfef7181a, ++ 0xe007a1a2, 0xcb8e7b27, 0x2840cf2d, 0x6f8f798c, 0x071a45b9, 0x0196bbe7, ++ 0x594fd3f0, 0xc7c421d1, 0x8c16f8f1, 0x7a2fb180, 0x680fcb07, 0xf9a26019, ++ 0xb21fd185, 0x9e5b43f6, 0xa2cffc81, 0xa3f2c37f, 0x2e88065a, 0xbe1c5238, ++ 0xbf6d0a65, 0xef9915c5, 0xcecd187f, 0x0efcea5d, 0x04cef10c, 0xb64290b8, ++ 0x5073c0ef, 0x73ab950b, 0xdb6ecff3, 0xf731e142, 0x779436c7, 0xbaeeda5b, ++ 0x01cde98d, 0x2575f81f, 0xbee37872, 0x425df288, 0xf619227d, 0x7c6ed8c2, ++ 0xdd9a523a, 0x288c6fb8, 0x43fa01dd, 0xb891dce2, 0x7a760c6f, 0xed8f47f7, ++ 0x678def4e, 0x1768fee9, 0x09a2df93, 0x1f1207fd, 0xf55ea076, 0x4e738f38, ++ 0xc3e90ef9, 0x1052f1ce, 0xa2fcfdcd, 0x36e939d9, 0xcfd8cde7, 0xaddf5c3d, ++ 0xd5b8347c, 0x27ffe14a, 0x9ebc7cf5, 0xd6f7cfe9, 0x0d13b950, 0x64de11fe, ++ 0x82f72790, 0x7764793d, 0x540f3d5e, 0xbdbcd2a6, 0x39569cfb, 0xbdac9bd3, ++ 0x61acadff, 0xaabcaaf5, 0x57bec81c, 0x72c4adf7, 0xc7c49f06, 0xeb0cd9af, ++ 0xfd0449b0, 0x1ece1769, 0xea3979b6, 0x47ee7701, 0xc9bd7bf8, 0x993f5e70, ++ 0x7a04c837, 0x939f8aaa, 0x70abbc43, 0x481efc3d, 0xfe3a93c5, 0xf9eebe7e, ++ 0xe823d522, 0x3f2ec33a, 0x15ea9fae, 0x3fe5d9a3, 0xd3f62bd3, 0x55de02b5, ++ 0x65a912f8, 0x1fff942c, 0x508bd382, 0xe9c2cfff, 0x35e7be1f, 0x6f2a21c8, ++ 0x8a7cc1f6, 0xbfd29e96, 0xdf70e247, 0xc4e58428, 0x18fc4d74, 0xd1e70e5a, ++ 0xebff4e35, 0xcd7b9ad1, 0xa1170fb9, 0xc7aea9fe, 0x4caf1ff6, 0xe4f49bbb, ++ 0x787ea34f, 0x75964ffc, 0x42547768, 0xdf8f8f28, 0xcc5df046, 0x4bcf1e71, ++ 0x7e336fd5, 0xce04705c, 0x112e6973, 0xe95563e1, 0xc8edf041, 0x947df0a6, ++ 0xeef0e76e, 0xf993303e, 0x75fba8f9, 0x5bdf8f25, 0x7c5aecb9, 0x5a41d2af, ++ 0xc81e9cf0, 0xbb3f2824, 0xc30ce7ea, 0x01274a7a, 0xbc89c82b, 0x831dfc28, ++ 0xef8254ca, 0x8ce72a6b, 0xdf387ac0, 0x1cd13fa2, 0x39538e0b, 0x6561d193, ++ 0x1bda2c5e, 0xdc02ee41, 0x84a3a37a, 0x21176672, 0xf6b47792, 0x62e1defe, ++ 0x7a5b7976, 0x4177cecb, 0x45675daf, 0x885016bd, 0x891532f7, 0x87a51e38, ++ 0xd4be902f, 0xc913dcf3, 0x5c70c7c1, 0xd609da0f, 0x2859bc38, 0x73627ee7, ++ 0xadabfcc3, 0x0d25ad64, 0x2564438e, 0x1f3e4bca, 0xd124f152, 0xcc3f73da, ++ 0x3d00e0bd, 0xea097244, 0xe178cbef, 0x6100fedc, 0x210ffff5, 0x0004212a, ++ 0x00000421, 0x00088b1f, 0x00000000, 0x7dc5ff00, 0xd554780b, 0x733ef0b5, ++ 0x9267bcce, 0x9924c933, 0x124e3c84, 0x0c020108, 0x51680869, 0x62311087, ++ 0x16a4076a, 0xe121c5ad, 0x44c92891, 0xe96c5adb, 0x08149065, 0x791a8622, ++ 0x0b84e915, 0x1fed6d8a, 0x40d4522c, 0x6f4a4407, 0xb6a87fb5, 0x6f7f6d57, ++ 0x151f1484, 0x6b4b3e32, 0x6b5affad, 0x99cc93ef, 0xedaa9524, 0xd87b3f4d, ++ 0x1fb3ef67, 0x5ad7bdeb, 0x4add4f7b, 0x24d22be7, 0xca56eac6, 0x630a6b31, ++ 0x8195fd6c, 0xbfa31b5e, 0xd3f88a8f, 0x8858c996, 0x716dbf89, 0x94227077, ++ 0xff683bf1, 0x757f0d3f, 0xc32c2e6b, 0x8b0fd0f7, 0x83a5f7c0, 0xf0a967df, ++ 0x16c60c8f, 0xac4581ca, 0xcabdfe02, 0xa095eda9, 0x18aeff0e, 0xf0a9667c, ++ 0xb7d42a72, 0x8e240d6f, 0xdc938fa7, 0xe0351cef, 0xe67da153, 0xf54b161a, ++ 0x8eff1632, 0x0d2ddd1c, 0x12d7af9d, 0xf50ec7bf, 0x9ec9570b, 0xfde10abb, ++ 0x57ad370a, 0x59cdef9f, 0xf158cbf1, 0x3acffed0, 0x5c152b9b, 0xc6748aff, ++ 0xd2b9e1b2, 0xb80602ca, 0x32cb0658, 0xfc584b63, 0xe61a4984, 0x8a3b12bd, ++ 0x91da5ff3, 0xfffd3df0, 0xed89addf, 0x27040260, 0xf34949a6, 0x5d073767, ++ 0x55b15ef4, 0x431c7bc2, 0xf12c5183, 0xa1b2c185, 0x39e1d6f3, 0xb809355b, ++ 0xb2ae96b3, 0x8d9ef0a1, 0x0a18cef0, 0x37a5af6f, 0xad0dfb0f, 0x929c12b0, ++ 0x4a2c67fb, 0x676ada78, 0x901a7b11, 0x00fd0483, 0xe9ddb75e, 0xf801ae8c, ++ 0x0fe3dbf6, 0x47c33c22, 0x9f7c22ae, 0x0c68746f, 0xc0b0ec9a, 0x391ca102, ++ 0xc5ee8ee2, 0x25bd2576, 0x1e7dd60c, 0xfc0010e6, 0xee567f9c, 0x24fa488c, ++ 0x567e6b18, 0xda01bdde, 0x6afc7f9d, 0xa76acfde, 0x461ca0c6, 0xe1b8c308, ++ 0x18ab07c8, 0x679a55c0, 0x1ccff1a3, 0xac56a294, 0xd670043f, 0x9dff0be7, ++ 0xca1aff87, 0x29a8bc61, 0x4f0c9e62, 0x1c79c0ac, 0x603cd272, 0xde348da5, ++ 0x036c1c57, 0x926cdf8c, 0x6fa82602, 0x747c65be, 0x8d8f9f0d, 0x8b967c01, ++ 0x589b35a9, 0xe5fd04ab, 0x9b36b808, 0x5edc974e, 0x6814ebc6, 0xf8e32b77, ++ 0x25c77681, 0xdb72e798, 0xe9191ec6, 0xea00f917, 0xc2fac16f, 0x6f343c41, ++ 0xb887d3fc, 0x4603e68e, 0x63fe58fa, 0x496e3ae3, 0x41c2aba4, 0x7056717a, ++ 0x166ab178, 0x75f3031d, 0xa6b3b28b, 0x3c232a27, 0x6762cc56, 0x8f4d073e, ++ 0x3a46cef5, 0xb1745772, 0x5f86783a, 0xcc288163, 0xceeed2fb, 0x7b4146a7, ++ 0x1e4f4d4f, 0xe2bc372e, 0xcfbee2b9, 0x9f59e20d, 0x9bdd25e7, 0xf1a2e665, ++ 0x4a983be8, 0xda8bbf60, 0x31379b8d, 0x7d1779f1, 0x89926197, 0x15f17b6e, ++ 0xc8128ff2, 0x2d9c6096, 0xc426458d, 0x578153ab, 0xed25d730, 0x26af7763, ++ 0xe64a0738, 0x3fbb19b9, 0xe09de805, 0x3944afe9, 0xdaad5a73, 0xe4de7c89, ++ 0x66aadaa9, 0x6e8271f0, 0xe5f03e5c, 0x5ae94325, 0x93f00e7f, 0xdc559768, ++ 0x35c5a532, 0x33e03b72, 0x7b7c5b82, 0x8a23972a, 0xbfa5e544, 0xa06e7732, ++ 0x374429f9, 0x18503fb7, 0xb037f9c5, 0xf9d20b76, 0x20b51672, 0xb1b52f1d, ++ 0xc5d00a48, 0x0a966852, 0xacdb65cf, 0x5fc04b4c, 0x5e58d463, 0xadc2e42e, ++ 0xbfbe87ac, 0x7d525f75, 0xa1b98b35, 0x62c6c9be, 0x19767c4e, 0x9c599beb, ++ 0xfa1f0fc6, 0x9ef89ac8, 0xdef5f075, 0xa9eef02c, 0x5821ca8e, 0x633b76f7, ++ 0xf0c0afc8, 0x574b9f84, 0x533e1276, 0xdf8503cb, 0x7fc57585, 0x06eff669, ++ 0xc0a3fdba, 0x399f0e97, 0xc227556a, 0x689b21df, 0xced5f1fd, 0x7f586ee8, ++ 0x2035899f, 0xb0f5effe, 0xf3c1e79b, 0x18162afc, 0x4d30266d, 0x86483a42, ++ 0xec2786f3, 0xa737480d, 0xd0252e50, 0x4cd55ad5, 0x6b0b5ee5, 0xbcaa7e40, ++ 0x904bfa0b, 0xbbd7cd57, 0x0bddf842, 0xfc007eba, 0x67f8875f, 0xd86f086b, ++ 0xf1cce91e, 0xbfd4fe39, 0xbe5d1ffb, 0xa9fccdb1, 0xd2dfbe70, 0xfc44e8e8, ++ 0x89a3d20d, 0x05963d11, 0x27a7082d, 0x64589c84, 0x3ef8d3fb, 0x4013e500, ++ 0x220f2820, 0x2f2e765d, 0x0ae17514, 0x5af13f28, 0x86837f99, 0xc7e5c374, ++ 0xd83a3713, 0xc9e4305d, 0xf7787e37, 0xedfea1af, 0x159a2cd7, 0xed2317ea, ++ 0x909e3e00, 0x8bc70058, 0xa28d663c, 0xec0e5bfe, 0x7e59f38c, 0xe5146264, ++ 0x684b41de, 0xe71c12fb, 0x2f7fb351, 0x253cb77c, 0x5483f0fa, 0x0a07ed9f, ++ 0x399a4f65, 0x771e467d, 0xd11deff2, 0x8bc4fd1f, 0x08fe59f5, 0x1ec27fb4, ++ 0x23f910fa, 0x92a5aac7, 0xcc95fd9e, 0x12b138f8, 0x34efc00f, 0x9e152bae, ++ 0x38e12550, 0x07ea6edd, 0x097b2ef8, 0x2da673f4, 0xf203d68b, 0x9ce38034, ++ 0x8ddd64d9, 0xc0cb74f2, 0x3fb512b8, 0xcece0e6d, 0xc7e9f286, 0x4357f8a6, ++ 0x12d07f55, 0x867d00b3, 0x19f5bdef, 0xdea2fa06, 0xf842eda4, 0x5a4e23b0, ++ 0xf08f8e87, 0x58b565a6, 0xe565be1f, 0x46ef28b5, 0xdf945be2, 0x9e0e412c, ++ 0xe47cf167, 0x450d1d8f, 0x13d4315d, 0xa4fce3dd, 0x900f992e, 0xf2a1f40f, ++ 0x0e667db6, 0x3361f8df, 0xf6c5eff1, 0x54a1748f, 0xe382bd72, 0x32ce4184, ++ 0xce489f9d, 0xe1e59426, 0xe18f1cca, 0x2e48b227, 0x75afd724, 0x007b2687, ++ 0xfbdfcd2f, 0x342bcbf3, 0x724e2f1c, 0x1067b58e, 0x0399f59f, 0x3d6e910b, ++ 0x5d4b31d5, 0xe55fdd02, 0xdebbfae1, 0x630cf5ca, 0x977e0b31, 0x65595f5c, ++ 0xfd01fba4, 0xe2fce1ee, 0x7af2e1ee, 0xf049bd68, 0xd45675d3, 0x29f2974b, ++ 0x0bd402b3, 0xa35fec2e, 0x2d7d2ffe, 0x7287a966, 0x6598cac1, 0x9f2278a9, ++ 0x3663bc00, 0x76df7758, 0x0403c937, 0x74b3f603, 0xb7fd233a, 0xb6ad6654, ++ 0x1daf7c72, 0x9cbc05ea, 0xf443cc7d, 0x5006fec5, 0x622f7801, 0xad959da2, ++ 0xfa5c81b7, 0xb314ab59, 0xdb45bb41, 0x85edbbac, 0xd901d7c8, 0x407cf88d, ++ 0xa8b4b922, 0x76c96675, 0x6072df28, 0x653fe122, 0x5bcba73a, 0x73d21ea2, ++ 0x57790a97, 0x145a8d6f, 0x923f87d4, 0xfd465ed8, 0xcbff62b7, 0xf2eca3e1, ++ 0x394070a1, 0x6887a06d, 0x9dec1942, 0x9cb8bb4b, 0x599f2064, 0xcba41d82, ++ 0x2ccb946f, 0xd233aec9, 0x2fd74447, 0x5a638edc, 0x8389dcd6, 0x1a8e7672, ++ 0x7843ddbc, 0xf8859d18, 0x3d727c05, 0xb8225fb4, 0xd216b136, 0x1f5cba0f, ++ 0x85e85718, 0xeb8472b3, 0x7a66eb1f, 0x1214f3ae, 0x5d616f5e, 0x3d741fa4, ++ 0xac1d1231, 0x12347413, 0x7417ac1d, 0x1635fcb0, 0x5bc60cbb, 0x9ac592be, ++ 0x7ba7f126, 0xae3be912, 0xef5c6cf7, 0x1171d3e1, 0xdf592ffa, 0x64b7eb25, ++ 0xe16596bd, 0xb3c74bfa, 0xcd649f6e, 0xd2fd7ae2, 0xc1995195, 0x04a4e6fa, ++ 0x18c8ca1e, 0x2fc253b4, 0x64da6cd8, 0x1159072c, 0x994e2bb4, 0xdf059599, ++ 0x40161585, 0x5c0272be, 0x03fde13a, 0xb3959ec2, 0x167d7af8, 0x2566bf4e, ++ 0x10b8a6c8, 0x13313d2f, 0xa98325e2, 0x3c3a8f48, 0x77c3701f, 0xd71df8e5, ++ 0xdbdf0337, 0xe123ab58, 0xec27aafb, 0x7fde7fa4, 0x92b51ddc, 0xf02a117d, ++ 0xbf997f40, 0x79dd92b7, 0xe93709fe, 0xb666f3c7, 0x7bda0ba0, 0x7a24bed1, ++ 0x3dfd4b59, 0x40cd788e, 0xc51aaa6a, 0x39a5f690, 0xea0450a3, 0x879356f6, ++ 0xed434ddb, 0xd85f511b, 0x2ba73d73, 0xf1f286ab, 0x1def4f7d, 0x30f98658, ++ 0x05fb3fd4, 0x6607c39e, 0xbc36f94d, 0x7e5d070f, 0x14d0fd0e, 0xfcab57a4, ++ 0x406debf5, 0x95e5b35f, 0x1d613bf1, 0x152e794d, 0xc1755bf5, 0x03777e1f, ++ 0x603f5f94, 0xf3c45666, 0x580b59de, 0xb7f2c8d1, 0xdd3e6a31, 0xb72fc09b, ++ 0x9b9633ee, 0xf0e58cba, 0x05f96321, 0x767bdb8f, 0xff0ec902, 0x56d74047, ++ 0x9d6bcb6b, 0x93eb5f30, 0x8f47d256, 0x8fff4278, 0x7e29ade4, 0x2d6ce102, ++ 0x08527378, 0x2dfba0e9, 0x60569f09, 0x0e329ea3, 0xf7ebe47f, 0xd40a8bed, ++ 0x0836e061, 0x1133663f, 0xe6fac19c, 0x6173924f, 0x4b5e27c1, 0xb0a3f5e0, ++ 0x1cf3a5fe, 0x26f45dea, 0x12b53b50, 0x239a43ed, 0xfabb6f0b, 0x4147dc75, ++ 0xffc446bb, 0x0ed0b9d9, 0x8db0d5e6, 0xace5c3eb, 0xb6f90527, 0x1b48ec19, ++ 0xc69fd8a0, 0x6b6b70f1, 0xff0632bc, 0x19ab48ec, 0x3e54f387, 0x1f488254, ++ 0x04dfb0eb, 0xc69cd7bb, 0x7dd6f7f9, 0x033ef6f6, 0xe50c793f, 0xf6eca1f0, ++ 0x0bb844be, 0x2572c3f9, 0xe37f7125, 0x69cc8533, 0x7a5f2819, 0xfc61332d, ++ 0x977c3e2b, 0x15b2fde4, 0x00bed14f, 0xdb88b1d6, 0xe50d76c9, 0x8f3bb2d3, ++ 0x1f7d7bd2, 0x45cf3676, 0xb6a7b0fb, 0x63d9795b, 0x07d9f2a1, 0x59713ef8, ++ 0x75c51497, 0xa42ef34a, 0xf0bd44cf, 0xb2b55980, 0x864d70a1, 0xff3babe3, ++ 0x52c1853b, 0xe3a0255f, 0xf6e24dfe, 0x4292da98, 0x25ad01fb, 0xf0ceed05, ++ 0x475eabb6, 0x01ecb8f9, 0x02f68fd9, 0x8ff6ec3b, 0x72be5861, 0xf61712dc, ++ 0x4cfa4ef3, 0xaec74798, 0xde99552b, 0x739441cb, 0x5cf60f60, 0x5d95ef01, ++ 0xc7e434d3, 0xf9f00fe3, 0x1ed8f32f, 0xe2ba3a44, 0x4bf89943, 0xda10b131, ++ 0xc0961dbd, 0x6d6be438, 0x88d9dee7, 0xe6e7579f, 0x23fda898, 0x2e115312, ++ 0xf899159e, 0x04a4997e, 0xb61b8f91, 0xda26d635, 0x647b4f3d, 0x0599cbe2, ++ 0x5d7b332b, 0xa3d757c4, 0x007a6d3e, 0x9fc708f8, 0x6eefd2f7, 0x95f20ef0, ++ 0xb5db6f34, 0x0fff6297, 0x77c8fd99, 0xceccf603, 0xe17d102f, 0xb5e00c5f, ++ 0xd3ebc04c, 0xa9d599f2, 0x094b49f3, 0x7765d5ca, 0xc3a894b5, 0x7c0319d8, ++ 0xe5f393b2, 0xfb126935, 0x957484c8, 0x8c47d866, 0x9572efb4, 0xd8cf489a, ++ 0x17b02cfc, 0xedb0599e, 0x4b75fdc5, 0x69f0429a, 0x3b50b349, 0xefb72fe5, ++ 0xf5d6167b, 0x4374279e, 0x602fbc1a, 0xd7a82981, 0x055ab8b4, 0x9a822d66, ++ 0x93b630ec, 0xd760d7db, 0x25bb1d91, 0x21b83d83, 0x1cbdbf61, 0x724a9bfb, ++ 0x39fb0ea2, 0x4edfe2ff, 0xf39b7c20, 0xf6849cdf, 0xbbc2f842, 0xebd60d16, ++ 0xbe4896ea, 0x8641fcbb, 0x9eee1374, 0x0d9716cb, 0x9fb0e5ca, 0x75e48deb, ++ 0xe6669e3d, 0xa71bd472, 0x73a4f67e, 0x30f0ee7e, 0x2b1da7a2, 0xefef641c, ++ 0x38ed46f0, 0x6f967fe9, 0xd1a9fb75, 0xdb6cf1c6, 0x8c80d3f3, 0xd4951e74, ++ 0x38d65831, 0x2c37f47f, 0xce30ca8c, 0x238a7beb, 0xd3303e54, 0x6b9d432f, ++ 0x2fae7fcf, 0x321d3842, 0xcbbdb1fb, 0xeb829bdf, 0x99cf7d7b, 0xc35f5c14, ++ 0xddd6991e, 0x732b7d10, 0x9ca0d949, 0x6d429b30, 0x4aa62f08, 0x975f1c2e, ++ 0x79efaf17, 0x8bb17327, 0x9f4803fb, 0x970f0c56, 0x4dcccf26, 0xb8ae5728, ++ 0x8de5e39c, 0x9451ac47, 0x41d86f83, 0xdfc825df, 0xff5cdc37, 0xfdf4d345, ++ 0xea3e575b, 0x32b2819f, 0xe27284ce, 0xbf5f2aeb, 0x8f95d2d7, 0xc927f97c, ++ 0xeb2dcfd8, 0xb9051665, 0x625eb8d4, 0x6ff99051, 0x7cb3fc3c, 0xefafff94, ++ 0x5d7e59fd, 0xbf92fcc2, 0xd43f9fd3, 0xb1fe13c7, 0x178fa63a, 0xeaf1c5cb, ++ 0x97ee56fc, 0xaa5fc11c, 0xb8db67b7, 0xb81fb3df, 0xff50e916, 0x11c1bfae, ++ 0x9fb77b40, 0x42e8a2d9, 0xfe16ebab, 0xb46040d7, 0xfa35f717, 0xf7fd49f7, ++ 0x0e927a0b, 0x701fe449, 0x3e49c596, 0xeff9627f, 0xc8267c05, 0xadf3c07f, ++ 0x5b26e788, 0x4628c4fc, 0xb84161f4, 0x0a5d9a59, 0x35ccabea, 0xdfe2be9c, ++ 0xcb3ed130, 0xc49948eb, 0xe4b2bec0, 0xdf285cf8, 0xb47128ae, 0x7df1529a, ++ 0xe7db147e, 0x77d294e5, 0xff4e2a91, 0x7e464c91, 0x22d66cb5, 0xed55df91, ++ 0xee503f25, 0x806ea674, 0xb73a4a62, 0xbfcc7d5f, 0xfc262e4d, 0xd207e84b, ++ 0x07eba2e1, 0x979423a4, 0xa236486f, 0x225ba923, 0x7536547b, 0x477ec42d, ++ 0x253faba2, 0xfe9fd5d1, 0xdef574cd, 0xd2157488, 0xb67cae88, 0xf84ae9e1, ++ 0x3dba2f85, 0x5f71048b, 0x75e0259b, 0xf13f90af, 0x3f74d86f, 0xadeb84b9, ++ 0xdad5fd15, 0xf519315c, 0x66fcdf88, 0x2777bfa2, 0x7fb8c5d8, 0x1ebb46ca, ++ 0x2cd6a39e, 0xac6f08d2, 0x08fd17a7, 0xd23669ce, 0x7a9b7797, 0xc98ed10a, ++ 0x1fb2df1a, 0x616b23e9, 0xda1af959, 0x507ae617, 0x25aea02f, 0x598ace7f, ++ 0x40476e41, 0x734748bf, 0x69cfb42d, 0x906673be, 0xc43511db, 0x768de12f, ++ 0xace0f50d, 0x48d5c2ee, 0xcc95e11f, 0xee3a256f, 0xfd14bedc, 0x7e5df3b3, ++ 0xf4767594, 0x607ee0d3, 0xdaef91bd, 0xd7b22ea4, 0x3f335723, 0xffdd75ca, ++ 0xdde9e1db, 0xffd46df5, 0x37e4658d, 0x8f07f019, 0x3a37a466, 0x34ec813c, ++ 0xbfc1eb80, 0xc765ff73, 0xf3c32814, 0x8ecf8149, 0x0f6c81b9, 0xda36eb94, ++ 0x9d1dee09, 0x0ddfbebc, 0x7e4c9a00, 0xa58fea61, 0x1a1eb8da, 0x9fc81f2a, ++ 0xe99d399c, 0x9cb0db7f, 0xb7db97a3, 0xf3a41d92, 0x9f21477f, 0x582cbb8f, ++ 0xf7f91688, 0xa4e6ff37, 0x1327e803, 0xb37c71fd, 0x00fdc116, 0x997981f9, ++ 0x9bf7c4dc, 0x58392260, 0xf543647c, 0x6f32c48c, 0x8cfdf83f, 0xf41eb06b, ++ 0x4e3d40ef, 0x5eb2f41b, 0x1e61d80e, 0xf583dceb, 0xb6c1d80a, 0xfef89243, ++ 0x8257398d, 0xc497eeaa, 0xda4791f8, 0xb417e802, 0x8978c333, 0xfa9253f3, ++ 0x2eff4337, 0x6cff6f4d, 0x61a395cd, 0xb97ae5be, 0xf3002db4, 0xec6cd7bb, ++ 0xbe2a408f, 0xde3e82c7, 0xdcdf2dc4, 0xa0c671b0, 0xc2f6007d, 0x8319e9cd, ++ 0x97bac276, 0xc327db6a, 0x1df54e58, 0x5d5fea0b, 0x12bd87df, 0xfcc921d9, ++ 0xf73a5b7a, 0xf9627ca3, 0xafb10daa, 0xf9274b6f, 0x591b3bda, 0x2425f612, ++ 0x832bc3bf, 0xb05bed0c, 0xf381be4b, 0x9be2ff3d, 0xfd428f67, 0x3d7f79f9, ++ 0x76c34a31, 0x7dc42db7, 0x4282f855, 0x4fbc37f2, 0x37c04a8e, 0x576e6eb6, ++ 0xff273e83, 0xb73f4ebf, 0x3c7e82a8, 0xcbfe8611, 0x54d2c38e, 0xa8b077a4, ++ 0xb804bff2, 0x103d297c, 0x7ec471a1, 0xdbdd7933, 0x287fb9d3, 0xbdb55a5c, ++ 0x23dffb04, 0x3617b431, 0x5cce9e94, 0x57a9fb4c, 0x7c249732, 0x7ee878d7, ++ 0x3ee36782, 0xdc70b0f3, 0xdc932e9e, 0xb1fc7e6b, 0x378dca00, 0x84c912a2, ++ 0x86da2506, 0x83436d76, 0x56422d09, 0x03745d11, 0x581633c5, 0xdf5818d8, ++ 0xc2efa12a, 0x5c8baefb, 0xff86eb8a, 0x23b57824, 0xc4e494b8, 0x1736058e, ++ 0xeb4a85c5, 0xa838236e, 0x61c2008e, 0x36556943, 0x773cd38e, 0x10714ab6, ++ 0xbeb0e7b0, 0xc91bcef9, 0x6bcfa45f, 0x0d7321c3, 0x60953bda, 0xe614fdd7, ++ 0xa736979d, 0x3d7c0fc6, 0xe53fde4a, 0x32de506b, 0xcf2f1c82, 0x55bc72e0, ++ 0x58be460a, 0x9651fe41, 0x382cefe8, 0xfdc7edc4, 0xd57edce9, 0xe74fefdf, ++ 0x488ced76, 0x97242ccf, 0x13af4a23, 0x0b30eaed, 0x6afb85bc, 0x7b697416, ++ 0x7e5c4f09, 0xe4695779, 0x7b79b337, 0xf58c9eef, 0xcfda1433, 0x3ef7a530, ++ 0x9b7cf71c, 0x0981bfd7, 0x9df2c03e, 0xc7945165, 0x0474379a, 0xd852ace9, ++ 0xbf1fe7ab, 0x17fa0a6a, 0x6dabfb75, 0xf18a3baf, 0xf6b736d0, 0x93941abd, ++ 0x4e48517f, 0x67bc5b32, 0xf8d3f416, 0x6bf51a41, 0x897e8572, 0xa3d9b4fd, ++ 0x9107486d, 0x79da994e, 0xd862d9e7, 0xba0febcf, 0x34ced13b, 0xd219db7b, ++ 0xc85f6c31, 0x06f3628f, 0x6785c619, 0x12291645, 0xbb248bea, 0xb1fa1666, ++ 0x25e2df68, 0xe0956e3f, 0x0540318f, 0x0ac46d67, 0x0fa51fad, 0xff2739da, ++ 0x97c15f36, 0xb263fdba, 0xf57bbf71, 0xf1c30702, 0x09f8dad9, 0xbdf1fa13, ++ 0xe1ed0c3d, 0xc6892ea6, 0xd47d2a69, 0x5b97fb82, 0x877f38bb, 0xe0037ec5, ++ 0xa5f14f97, 0x83f0a774, 0x677a72b6, 0x2146273d, 0xf1cc7f9c, 0x4bb418c9, ++ 0xb632bbf0, 0xd103cb9a, 0x1fc4459f, 0x09bf849a, 0x9fd52134, 0x15e3d74b, ++ 0x3b678977, 0xb7718a7f, 0x19013d48, 0x324539e1, 0xa7f5c9f8, 0xa7dfe5e2, ++ 0x46cf8b1e, 0x7d038dfe, 0xbb69dfa1, 0xa7b6f734, 0xa7db7d61, 0x29a3f78e, ++ 0x927203e6, 0x903df1cb, 0xe2bdc022, 0x91b35bd0, 0x230d586e, 0x343e6d7e, ++ 0xf1726e53, 0x0bda0d38, 0x4e96ce59, 0xb9bacfac, 0xc633f494, 0xe2de304d, ++ 0x66b872f0, 0xcf1fb8bb, 0x10a45777, 0xc7a99ae3, 0x8d3db782, 0x90744fe3, ++ 0x700b361f, 0xe7a34ee3, 0xf97bf47a, 0xa8a394d8, 0x5ab57d9f, 0x8f47ce39, ++ 0x6ffc61df, 0x71c9196e, 0xa5f9a72a, 0x3fdc6ec0, 0x6fdc3d79, 0x38356567, ++ 0x751f7c5f, 0xd113c60d, 0x62e3879f, 0xe79f0ebc, 0xf90a63b3, 0xaeef59ff, ++ 0xb7efb4bd, 0xdaaf08aa, 0x0178bf43, 0x8dad6ff5, 0x357c5175, 0x24796ec9, ++ 0x2f3cbae5, 0xee7fd38c, 0xe2efaeec, 0xd074bebc, 0x18fc221f, 0x2e2b91ed, ++ 0x1bf9f6e7, 0xda1a9d7b, 0xdc85bb91, 0xf891fb06, 0xdf08f224, 0x91db264f, ++ 0xbf1d5e15, 0x281c8edc, 0x2476e67f, 0x2f645f9f, 0xe5d09bcf, 0xffec587b, ++ 0x4ede1bfa, 0x1815fd41, 0xffe80f98, 0xa83b41ca, 0xefc88f6e, 0xbf3e1ee8, ++ 0xce83e4e3, 0xdbc3d208, 0x4bf2765d, 0x75ee222a, 0x03bf1dce, 0x39ead481, ++ 0xdbca3d71, 0xfc6f2df0, 0xa7fc04c4, 0x9238f274, 0xd3388922, 0xe3c6652f, ++ 0x31350162, 0x6678a7ee, 0x286502fb, 0x97baf91f, 0xf2d1bf0b, 0xc78d12b4, ++ 0x6fbc78bb, 0x04ac4a79, 0x8527a9ed, 0xe0ee5a1e, 0x8f7eaaf1, 0x7d788625, ++ 0x805a1ec2, 0xf2b1cc78, 0xadcfd9ef, 0xab5c625a, 0xbaedca33, 0x98a6a533, ++ 0x89d9d605, 0x6de201f6, 0x0d6f8f23, 0xb11c07e4, 0x9e695a76, 0x6dfdca8c, ++ 0xeb272485, 0x11d5b8f5, 0x17ab8fee, 0xf333a9f1, 0x4300fe96, 0x4b52ad95, ++ 0xdecfee0d, 0xfc9330df, 0x6f7c77e8, 0xd7eb3d2e, 0x4bfefd1b, 0x3c5f4fd1, ++ 0xfdd61718, 0x6fcc75ef, 0xa0f2f6e1, 0xf604d11f, 0xa95eb68b, 0xc8597d42, ++ 0xfe50bbd4, 0xd6c0116b, 0xc2b67834, 0xc9768d13, 0xa39da124, 0x881d79b4, ++ 0x26ad75df, 0x569153d2, 0xe9db0053, 0x72f56e70, 0x2f4ed23f, 0xaa006bf7, ++ 0xfe8e38a2, 0xb88b356c, 0x356fe883, 0x69f0c533, 0x9d73f892, 0xa70cd4aa, ++ 0x5afef5af, 0xf4362dcd, 0x4cf3c5d3, 0xdf7ef7e4, 0x7e405812, 0x1612b4e3, ++ 0xbab67801, 0xf0d7d65b, 0xf79de27a, 0xd520f1ed, 0x4370a65f, 0x28696992, ++ 0xe5e5bf3f, 0xdc3244f6, 0xcb1bb496, 0xc698f1c9, 0xcf5cb1a8, 0x8bb36342, ++ 0xf120fc79, 0x7e50b7fd, 0x153c454d, 0x2dfb780a, 0xf5f56728, 0x70e5ceaf, ++ 0x67f1e533, 0x02d55e51, 0x8f2283a4, 0x8a31f285, 0x0abfdc3c, 0x17f9a12b, ++ 0x8895e65d, 0xdbe6923e, 0xd21b468a, 0x878f1b57, 0x4ff3b3fe, 0x6f1ef79e, ++ 0x80dbe0a6, 0xf597e30f, 0xd1e285aa, 0x7927eb17, 0xcfdc6bda, 0xfb3f940e, ++ 0x27df2cfd, 0x6f22c9b5, 0x54392546, 0x9cb5f2a7, 0xc60ffc91, 0xec0bbdf0, ++ 0x9b475c04, 0xcb768e5c, 0xb45cebac, 0x7623e68e, 0xad3703f2, 0x3d47cdec, ++ 0x5bd55cde, 0x649b7182, 0x156ce2f8, 0xbb417e5d, 0x3fec2f3a, 0x6c484ed0, ++ 0x8caff227, 0x4bc0d671, 0x37ee2728, 0x0bffd99d, 0xedfb57d4, 0x5fe0afa4, ++ 0x67e8ad47, 0xec90bc79, 0xa1dc1ba8, 0x27b45ed3, 0x0f5db11d, 0xc2dda215, ++ 0x6ea6a6ed, 0x85da276b, 0x7109ad75, 0x8dbffc3e, 0x5b1fb8c6, 0x77fe469f, ++ 0xdf7c61d6, 0xbbe933b0, 0x76c07121, 0x4b16f3c2, 0x3bf21c68, 0x3fca1de8, ++ 0xa268d738, 0xd97a81bc, 0xede514bf, 0x1ed1bb39, 0xf8e6e73f, 0x3c743292, ++ 0xcf104bfb, 0x7821e503, 0x9e2097f6, 0x942c4deb, 0xe2134fd8, 0x5cbbf019, ++ 0x63dcf9e0, 0xcf104ad3, 0x569fee6f, 0x62de7882, 0xdf200f6e, 0xe643569c, ++ 0xdf67980c, 0xa7b24195, 0xf9072f30, 0x31e962e8, 0x17a8c32b, 0x22ffca07, ++ 0xfa48caff, 0x5e0078b0, 0xb5e87d46, 0x0f28b968, 0x7fd66cea, 0x6ff117a8, ++ 0xcd9e3f58, 0x238efe4a, 0xd3677b7f, 0xba072883, 0xf447b265, 0xa1288efe, ++ 0x8e87b462, 0x47f3e0bc, 0x7ffb91a4, 0xa9d8ed06, 0xa08c2714, 0x07df455f, ++ 0xb264f6e8, 0xd6269e3c, 0x60466d73, 0xd827fa5f, 0xe37eea8f, 0x16cef106, ++ 0xb9db877d, 0xf73f247b, 0x1f91771b, 0x22f0f9b9, 0xafc4fd15, 0xb8dfb945, ++ 0xe429b1f9, 0x3e8c6e37, 0x313cc315, 0xb8a92dd6, 0xf3dc68ff, 0x03e60a4a, ++ 0xd85cfbe8, 0x83217ed7, 0xefdc6cf0, 0x933d16be, 0x3003f982, 0x6f383def, ++ 0x416e37a7, 0xfd866fba, 0x3605e61e, 0xd813f12b, 0x5197b36f, 0x21c54b9e, ++ 0x8f4ffee3, 0x5a08eef3, 0xe8eeee48, 0xaf28a296, 0xc2a12d33, 0x2c6bd45c, ++ 0x1ceb3d57, 0x64afb3e4, 0xf185be04, 0x7af8c1df, 0x1919abe0, 0xbd5df983, ++ 0x7e8953db, 0xa02ccd7b, 0xeedb3ca2, 0x214cf216, 0x4edef6f9, 0x7be7944f, ++ 0x45eff6f1, 0xa8d09db9, 0x2c2979e7, 0x96be00a6, 0x88bc0fce, 0x1f7946f8, ++ 0x89f7924b, 0x7f6e3d65, 0x5e918b2b, 0x274cc26a, 0xd895ef91, 0x8fae392e, ++ 0x3f4370f1, 0x868a65ac, 0x5c9bb07e, 0xc60f9c7e, 0x11f58dc7, 0x7e064fbe, ++ 0x483e5158, 0x741e3abf, 0x7e166dfa, 0xe9c370e8, 0xe1bf48b5, 0xf68a9243, ++ 0xa73f72dd, 0xdfb0e5df, 0x64d8bcc2, 0xc65d677e, 0xf891d03c, 0xdf00eb7f, ++ 0x3adffe71, 0xd7fa9ca2, 0x277757f8, 0x7ebebdf1, 0xb03f6fdd, 0xf3896ece, ++ 0x92bad265, 0xfec9a9f7, 0x799f7d76, 0xf1f0f2b1, 0xfe3c7824, 0x48c7862f, ++ 0x01e9f0f2, 0x0f2c9cb9, 0x7f8cf18d, 0x8bfe1e5a, 0x383f1ae3, 0xf70535bc, ++ 0xe3c7681d, 0x5efd653e, 0x009fcf33, 0x8bc627f0, 0x00aecb67, 0x7aca9f8f, ++ 0xaf0e31bd, 0x787116cd, 0x3d4fd7ce, 0x9ade1326, 0xe9b89c44, 0x4d8fdbb0, ++ 0x28cb5c1b, 0x3f1c9b4e, 0x9fed85bd, 0x8e4aa88d, 0x7e472ea3, 0x78f8fe2e, ++ 0x40c67f6a, 0xe62142de, 0x6de7242d, 0x277ae53d, 0xf780943d, 0x10d832aa, ++ 0x36df430c, 0x12d2c225, 0xc1987fde, 0x894fffe3, 0x859f22fc, 0x95bcc7ad, ++ 0x00cedd7b, 0x267c67ee, 0x52f4ff9e, 0x9423f07a, 0xc04d3683, 0x332ff1f5, ++ 0x07e5c013, 0x2b922ee6, 0x1f972691, 0xbfeea0e5, 0x4afffbd1, 0x8bd7a73a, ++ 0x4999ffd6, 0xff2f5ffa, 0x50bff89b, 0x8d9fef1f, 0xd8036ddb, 0x1182f818, ++ 0xf1833f1d, 0xf4a1c2a5, 0x233f523b, 0x664571d1, 0xb7267270, 0xbe5127f3, ++ 0x19ca45c2, 0x0cfc4567, 0x01d889fa, 0x4d7e86ab, 0x7e9093f4, 0xf22d98dc, ++ 0x7395fd51, 0x5fdaef29, 0x2f63f989, 0x192f3fe3, 0x939c8ed9, 0x0723b469, ++ 0x1d919fca, 0xb5835319, 0xdf5fd099, 0xf7e500cc, 0xfcc373af, 0x30f87f71, ++ 0x69da3bcf, 0x53b9f4e7, 0x9fa974e2, 0x7f38f8af, 0x51a65d4b, 0x388dd68e, ++ 0x1cad7fef, 0x4694ce6d, 0x6b3f2bb0, 0x14d7fa39, 0xdc8e9ff4, 0x7fe4444f, ++ 0xe2dc10f6, 0x3bb62587, 0xee1dafc1, 0xab7bf9e1, 0xf7f57cc4, 0xf03d0a37, ++ 0x0881995f, 0x2f9be3d2, 0x152c6cda, 0xcb82b3e8, 0x8ba0e6c5, 0x5dcd0ae2, ++ 0x79a5ff3c, 0xde392325, 0x5c537e8c, 0x0cb9a1ff, 0x3cf7beed, 0xfdf80da1, ++ 0x115c97ba, 0xedfd1539, 0x79da18f3, 0xe5e45fe7, 0x4da13c47, 0xd95e1f58, ++ 0x8e8c714b, 0x1e506f79, 0xef47e556, 0xa0a9adac, 0xc13f92f9, 0x4f9e356b, ++ 0xcb933c79, 0x7079fd33, 0xf201de00, 0xc0d9bfe7, 0xdec3b5f3, 0x097e8a80, ++ 0xd4ee1fdd, 0xd0ae287a, 0x6f1b807c, 0x0f5f3295, 0xd12e76fb, 0x9981f353, ++ 0xca6fd053, 0xd053ecba, 0xbdfcadde, 0x6f7df68b, 0x794399de, 0xb4379a12, ++ 0xaeebe717, 0xf68d5e88, 0x838c0169, 0xfb9bef76, 0xf3829eaf, 0x16dfe5d6, ++ 0xfb439bf4, 0x3fa36e2d, 0x1e78d99c, 0xa343e37d, 0x4ff9bf74, 0x08b60f90, ++ 0xf6ae643e, 0xf0c3b9ca, 0x59efcebd, 0xcffa89b2, 0xe28d8afa, 0xd83cbae3, ++ 0x5b216662, 0xb91ca0f1, 0x7ee3533f, 0x6fc8af6a, 0xf3cb9eec, 0xe5d94453, ++ 0x5e79e635, 0xfde5719b, 0x33fb8f38, 0xc7174f95, 0x13c90d72, 0xc7933fb8, ++ 0x4fb82cb1, 0xbf928c07, 0xdb8179c5, 0x85aa45d1, 0x9ebdc8e8, 0xd014f8f1, ++ 0x33f3da11, 0xf0b33de2, 0x8ee8d6bc, 0xef840cd8, 0xc2260b91, 0x19f73293, ++ 0x4aa4cb8a, 0x8de2bc7c, 0xd1636dbd, 0x7f3ea30f, 0x6b52a219, 0xc430ab57, ++ 0xf8279ef7, 0x7df12642, 0x578e294b, 0xcf335bf5, 0x24ec3cab, 0xfe4742ff, ++ 0x3cabca72, 0x70d592ff, 0x19f926ce, 0x1e517761, 0xe7a1d165, 0x3ee03e28, ++ 0x1f9b0d20, 0x8ba64efb, 0x3d22adc7, 0x66b729b3, 0xabe49786, 0x11f7f872, ++ 0x369437b4, 0x6b0f2505, 0x784c0735, 0x9ab22cce, 0x4c7f3f91, 0x7c426a87, ++ 0x98bc8815, 0x4c1f23fe, 0x457ed10a, 0xe944078f, 0xd77b98a9, 0x594c3ee2, ++ 0x04797bdd, 0x63c071f1, 0xa9bf466a, 0xfe4cde39, 0xf24ec396, 0x2a1c16af, ++ 0x50f3ebbe, 0x52af582e, 0x89ffabfc, 0x8f280b5b, 0x6639d61f, 0x21fe7598, ++ 0x3ffbccd3, 0x1ea134ec, 0x3f333653, 0x3278aa8e, 0xf7de68ab, 0xf9fa1943, ++ 0x33a7265d, 0x7e8a5e3d, 0xff4fd428, 0x61b21995, 0xf9c0ec9e, 0x7e0e15a2, ++ 0xfee148be, 0x978af712, 0x3b73c11e, 0xf71f84bb, 0xf30991d8, 0xa6d7efc8, ++ 0xf7878848, 0xd2af3c3d, 0xc832659b, 0x1ff8419f, 0xa2d5fca3, 0x7d71cfc3, ++ 0xff616306, 0x8bd3998a, 0x44ede6d2, 0x4a7162ff, 0x2f75f288, 0x14c98d6b, ++ 0xeefb532f, 0xf612d1ab, 0x7eb8db39, 0xf7c7de69, 0x9afbc9e5, 0x132bd38f, ++ 0x657a8cb3, 0xb26ffca0, 0x1967a657, 0x7a7ff2ed, 0xfb8cc2bf, 0x25bb64bc, ++ 0xc4375f79, 0x6fea4f0e, 0xcf45fb24, 0x1c1aa93f, 0x6ed1db87, 0x188a3edd, ++ 0x5caa73f2, 0xcda0fce2, 0x6907ffd8, 0xcf57ad2a, 0xa35cc9d7, 0xfd7cc6ad, ++ 0xf91877f8, 0x227cf4eb, 0x52287f3d, 0x227cf3c5, 0x2f9d1b26, 0xca76b1f4, ++ 0x62c51a1b, 0xb57e4492, 0x67df865e, 0x7c10fe61, 0x1156657f, 0xe601ffcd, ++ 0xdc932f5f, 0xbf9c24d4, 0xd24ef31d, 0xedd1de71, 0x2fbc714b, 0x3b3c68b9, ++ 0xd3a49de6, 0x39f882fe, 0x55f3c827, 0x78f03567, 0x65e80e43, 0xe68ce72c, ++ 0x605f6974, 0x3d55fca1, 0x3bcf449f, 0x2552e1d1, 0x76339de0, 0x45ca2169, ++ 0x8b653f3d, 0xf6895fc3, 0xf6049b50, 0xd1a7ae35, 0x784df221, 0x458d1dbf, ++ 0x4ff7a451, 0x0c928f9a, 0x252f3d67, 0x855a129c, 0x579fa3fc, 0x7449f3d4, ++ 0x27c049ba, 0x61c76bcd, 0x3557df6e, 0xfd1d6858, 0x4fc8738d, 0x6268dfd9, ++ 0x75540768, 0x261d395b, 0x8163b78d, 0x5fb0c585, 0x79476a25, 0xc7c3d3aa, ++ 0xdf80b7d9, 0x1f03f452, 0xb8afb55b, 0xf8ff780f, 0xf67a2eaa, 0x792ea5db, ++ 0x5d279d32, 0x1eeb9288, 0x51af6fdf, 0x9b3cc12e, 0x2404be78, 0x0ffb2bb4, ++ 0xee364ab5, 0x632fe2ab, 0x966de1f9, 0x98fd502f, 0xda092ef8, 0x51d7dcff, ++ 0xcda4654b, 0x75bf681c, 0xf5c46d7d, 0xdfdff429, 0xc71e7258, 0xc832b30f, ++ 0x87b6b39f, 0xff4247fc, 0xc8f97055, 0xee51adaa, 0x8fc8d2bf, 0x90bb2a76, ++ 0x695702ec, 0xac1e81d1, 0xdf92b5cf, 0xfe89ea0d, 0xc9998d4f, 0x7f8e35eb, ++ 0xf9e6eb96, 0x8237ac1c, 0xe154edf2, 0x375ff24c, 0x7d807f21, 0x7a1dc335, ++ 0x4e7af102, 0xf903b9ea, 0xdf95d4e1, 0x3f3a432c, 0xa3dbf077, 0x655cfe51, ++ 0x187dbb01, 0x9b2eb379, 0xb37e9bcb, 0xfd04bd6b, 0x7a15ddfc, 0x82f1d70a, ++ 0x3c6ce173, 0x7d20b002, 0x1a8f05a6, 0x32c3c8b0, 0xe04337ae, 0xdb9f33cf, ++ 0xa0ea9e93, 0x6ba17984, 0x191e7cec, 0xf6402521, 0xf4be684d, 0x1aff5825, ++ 0x4c3bd849, 0x497da54b, 0x718a96a9, 0x5ce2e5c1, 0x5bf82ca9, 0x9bfdfc16, ++ 0x15a3bd55, 0xe92ee030, 0xb70f2cda, 0x692ebddf, 0xff3fa1ff, 0x3ce6e42c, ++ 0xf4889b59, 0xfb9f35e1, 0x5be02d55, 0x08a3f8b6, 0x6e7935ef, 0x751ee78a, ++ 0xa17afa57, 0x3be0a95f, 0xbd679815, 0x153bef26, 0xd3937718, 0x4260befc, ++ 0x6e78cff9, 0x679e2a63, 0x3f087680, 0xfa054b67, 0xfeb33f63, 0xb2bfa152, ++ 0x40dfde4f, 0xaf3e563f, 0x3e78b6e5, 0xcdbf4f9e, 0xf100fa1e, 0x57a2fef7, ++ 0x477b5e28, 0x3197a9ce, 0x9994e2df, 0x9e48e7cb, 0x1d6793c8, 0xae8052b3, ++ 0x447b144e, 0x8b8f08be, 0xfdcb189e, 0x785f209b, 0x8938e75e, 0xe76b03f2, ++ 0xd7a7f3f3, 0xded69eb0, 0xce2f3c42, 0xbd3d9bfb, 0x5ad3ec90, 0xfb31bf91, ++ 0xe20a6085, 0xe397f671, 0x48e1d20a, 0x3e55d6f6, 0xc09bd6b3, 0xc66b5767, ++ 0xc6a535f2, 0xc6fc17f2, 0x7fa717f2, 0xfcb13638, 0xf3e03d9c, 0xc839454d, ++ 0x972347f3, 0x70ec9530, 0xbb4114af, 0x72cfc268, 0x9e5db9c4, 0xb143f8e7, ++ 0x74d9fb8f, 0xfb99f546, 0x586dbb6c, 0xb2e2fc2f, 0x63e09fa8, 0x823482b6, ++ 0xb8d1e907, 0xbd25f224, 0x07622b14, 0x7fb9536f, 0xa05ada18, 0x348b839f, ++ 0xe997f73a, 0x91cbb132, 0xc46c2b6f, 0xac7f3ab7, 0x039d03b1, 0xd9472b1c, ++ 0x6bf7481c, 0xd86dfecc, 0x6ab0ec97, 0xa66737a8, 0xf96fa8d8, 0x3bd2143f, ++ 0xa656edab, 0x3dd8f942, 0x3b432a0e, 0xa6c71f92, 0x2fe8a25a, 0x85f4235f, ++ 0xe9133dfc, 0x05854add, 0xda03ff31, 0xb1fdf0c5, 0x83b51b6c, 0xf7c7cd25, ++ 0x3f3acca7, 0x1f2854ce, 0xe75dcc54, 0xde911843, 0x2e7c156f, 0x0e3b7e0b, ++ 0x7f71a0f3, 0x3f927729, 0x09bb54ad, 0x36db7ffb, 0x852bce96, 0x2961ce07, ++ 0x54ac1c26, 0x9ba27215, 0xf9d3979f, 0x2033975a, 0xa8634715, 0x50e31253, ++ 0xf5133e98, 0x5d3b2338, 0xae3d73e7, 0xdbd36798, 0x3fec0129, 0x2df77c5b, ++ 0xbce1a15f, 0x2f78a65a, 0x2fe2ff75, 0x3cba8f48, 0xf49d65d8, 0x70f66d4c, ++ 0x06fd2ef0, 0x55b8e795, 0xb9b1ef0e, 0x63b277c8, 0xadea2e6c, 0x16bf1e35, ++ 0xc297284c, 0x1a416676, 0x41da03c2, 0x579abaf9, 0x71892b46, 0x73e71f67, ++ 0x07481768, 0x6bb31f78, 0xc39fc8b9, 0xc7c4db8c, 0xe3b67e75, 0x685c60fa, ++ 0xe30dcc77, 0x763dbb42, 0x3294cc6b, 0x35d3f8dc, 0xc6e3ef1c, 0xc4462c65, ++ 0x15c04733, 0xfe8220e8, 0x136e63a7, 0x911ce3d1, 0x832c7c27, 0x8d4ac78f, ++ 0x81a33779, 0xd7944d0e, 0xb9b3cc65, 0x8ad9da4a, 0x3dab727a, 0xddd23765, ++ 0x9c5d042f, 0x68c7fe70, 0xb17e93b4, 0xc938e4b0, 0xadd5d491, 0x58732448, ++ 0x5d13c917, 0xfd9fbdce, 0x4196254a, 0xbe476dde, 0xd4e8a3bf, 0xb8fcec42, ++ 0xd468eb67, 0x760f207b, 0x9d0ea6f8, 0xfa7f4ebf, 0x910e91bc, 0x30e807de, ++ 0x1d3afe69, 0x28bb6bb1, 0xb001f141, 0xdba9f133, 0xf0b58c9d, 0x6f2d747c, ++ 0xc4407d70, 0x7c2d6db3, 0x9a118d1d, 0xfb9e55f7, 0x47ed5f28, 0x83ffa139, ++ 0xf9305af3, 0x1b057cad, 0xc58d16fb, 0xb7cc15fd, 0xbff197cb, 0x3b64df37, ++ 0xb2f2e3fb, 0x7d63e247, 0x3ede697c, 0xcf0ecbca, 0xf69e5177, 0x1a97912c, ++ 0x3f91306e, 0x6463f61e, 0x5b3337c7, 0xa5eee514, 0xcfd62ec2, 0x71213c0b, ++ 0x31e4673f, 0xc137b6ab, 0xaf9a1ebe, 0x783e51ad, 0xebcf2564, 0x9b9fb01e, ++ 0x079fb234, 0x9f3898f4, 0xcb8531d0, 0x34db8eee, 0xa4f3773a, 0x1647dbc4, ++ 0x1d8bd231, 0x12fd4573, 0x3fdfaa35, 0xe60e6522, 0x327477cd, 0x770effa2, ++ 0xc8e7d511, 0xcfb0df5c, 0x51d37d73, 0x1d97f7c8, 0xfd509437, 0x1c744716, ++ 0x788907e5, 0xfb8c0efe, 0xfeb883ff, 0x7f467cdf, 0x33f940ec, 0x569ec7f2, ++ 0x9d211f43, 0xe40b292d, 0xf58f404b, 0x0597ee16, 0xc3d9dd7a, 0x65b04d30, ++ 0xae93ee34, 0x9bcf2d66, 0xcd5e898a, 0xc17ed0d9, 0x62d7a004, 0xb25abd03, ++ 0xc6dcb833, 0x3af4e979, 0xc9a5a740, 0x54a177f9, 0xe9e1df6c, 0xee337dfa, ++ 0x7eadba2b, 0xf3cc7f9e, 0x43e59329, 0x2b167cc2, 0x595e3e7c, 0x0d64f9a6, ++ 0xe18b9f37, 0xcd3a449b, 0x463f9c62, 0x852c9fe2, 0x83e5dc45, 0x3d9cf3fc, ++ 0x0ee38254, 0xbe5ad1f0, 0x6f321c9f, 0x74f445d9, 0xee3c0dfd, 0xbd727614, ++ 0x6ca7f18f, 0x18ae7f18, 0x60b6faff, 0xcddb07b5, 0x621c3895, 0xff983ff0, ++ 0xb73f513c, 0xcff289bb, 0x4f9b55e6, 0xba39da27, 0x5de3d4bc, 0xebfb440b, ++ 0xcc66b9d4, 0x6b5f9f07, 0xb82d338c, 0xaeb9c789, 0x67ec6f9f, 0x16f8db01, ++ 0x16b249e5, 0xc16fc233, 0x59fac64d, 0xa9f103d9, 0x3a9f18b1, 0xfd30fc2e, ++ 0x47c827c0, 0xdb2c674f, 0xf9d01b79, 0x9597efd8, 0xcaeedfa3, 0x9b3dc6cc, ++ 0x8ed0fca1, 0x3a7e54f1, 0x3f5f2bf3, 0x4abbf585, 0x978d5ca8, 0x11bee121, ++ 0xacf810f9, 0x3986f2b4, 0x4fa82985, 0x31b7bf44, 0x8473ef7a, 0x3b42e63a, ++ 0xca22a4df, 0x7e16ad1f, 0xbc25fe85, 0x6ec99afe, 0xb37c229e, 0x6ada7e46, ++ 0xe8f7bf07, 0x5dff2999, 0xd5ccf98e, 0xfe5ca245, 0x1f2c78e4, 0xfba2de97, ++ 0xb937ce14, 0x7343c414, 0x4f6ff70e, 0xe3629528, 0x69d52e00, 0xbe26ffa2, ++ 0x87f2daae, 0xaa4f9073, 0x133f78ab, 0x8adb33fc, 0x6de99db1, 0xb1cf9f2a, ++ 0x75fc20a5, 0xb65afb7e, 0x37614fe0, 0xf89c8506, 0xd695e059, 0x6837e874, ++ 0xc4b8fc93, 0xc857f4e0, 0xfc5cc12f, 0x50305e5c, 0x7c7fa0a8, 0xbbe78056, ++ 0x6756d956, 0x36bc3ca3, 0x75c0a964, 0xc729b6a9, 0x75211f31, 0x94a9ccfa, ++ 0x84636d1f, 0x6fffa05f, 0x7b4ffd12, 0x89053f2b, 0x7fa465ce, 0xeae6be9d, ++ 0xa46d5f74, 0xefdbe06f, 0x271ff7e0, 0x6df40dbf, 0x91efa41f, 0xd79879ec, ++ 0x6bd46c86, 0xb5ea379f, 0xf8927181, 0x91dc7933, 0x25fe06e4, 0xf9c1dfca, ++ 0xe61f1175, 0x31615662, 0xcebb69f2, 0xf5c7dfa7, 0x743d4c59, 0xf240a92e, ++ 0xbd83a78f, 0xd236fdd3, 0xaafc497b, 0x7d0f2fcf, 0xe743e5d6, 0x6e8a7f85, ++ 0x2f3ff297, 0x457231fa, 0x60177c3d, 0x82f38369, 0x72447ff1, 0xcf9f2d71, ++ 0x970b5203, 0xa1df6233, 0xf59a3ffb, 0xae321ef5, 0xefc1d2b7, 0xbfa1f00f, ++ 0x5316628a, 0xfbcc0fc6, 0xafa0f022, 0xf9f42c27, 0x6dd05b7c, 0xc97db581, ++ 0xf3f44f53, 0x1ea8d065, 0x1ddf8b80, 0x8ebe218a, 0x71872299, 0x0584b73f, ++ 0xf40d6e28, 0xc13b3471, 0xd7f01a6e, 0x79a9c124, 0xbc9ab904, 0x0cf8649e, ++ 0x1b27ade2, 0xbfb9fa9f, 0xe45ef581, 0x15ed933a, 0x37e8c5af, 0xbdfe134c, ++ 0x5e7f41b4, 0x32d7d629, 0x79fc9f87, 0x73f6897e, 0xa07f60b5, 0x61adae9c, ++ 0x734957e4, 0xa79fc899, 0xf12321db, 0x739715c9, 0x9cbb55b9, 0x7c86f389, ++ 0x98f4c97d, 0x81bf7ac5, 0xb69b5acf, 0x7ff2317d, 0xdf90cb83, 0xf1e2eb5f, ++ 0x39740f80, 0xa2a77ac2, 0x0f281fde, 0x53bdfbd1, 0xdf250e51, 0x817b56e3, ++ 0x2ed39dfb, 0xf5acf448, 0xf51532bf, 0xef4d5a7e, 0xbf679454, 0x0dfc0d4a, ++ 0x1365f2e9, 0xc327cff7, 0xd26396d3, 0x451798e3, 0xa47cc9a7, 0xb8671fc7, ++ 0x8c9cce43, 0x39d4bf41, 0x9cfc87a9, 0xe8aae9fd, 0xf488543f, 0x670b51ec, ++ 0xbe697fa2, 0x768cc5ad, 0x94350af1, 0xe8e5c39e, 0x66e11f47, 0x1c029b15, ++ 0xfa1d54bf, 0x2587c2ae, 0xe02edc38, 0xb3d0a570, 0x6994ef6f, 0x281d521f, ++ 0x98a18add, 0x8b3349f0, 0x4806df12, 0xaff7ea3f, 0x1f240dbd, 0x763ff6c3, ++ 0xf65dbe93, 0x538a7acb, 0x6266dd8d, 0x1cbe825a, 0xee187517, 0x2fb0991d, ++ 0xd89e50cd, 0x3f686395, 0xa19150f9, 0xbc6c4a7e, 0x2773fea1, 0xa9e50dcb, ++ 0xda1a973d, 0xcaa17b4f, 0x77a4be50, 0x83fda18e, 0x8e01efa8, 0x9e6d7f9f, ++ 0x769ffde1, 0x71893ecc, 0x37e2cbe1, 0x233fbe1a, 0x122c0cfc, 0xf58529e8, ++ 0xf5e9d62f, 0x7be19d42, 0x52626b30, 0xff3df225, 0xe791bc5b, 0x8804cfbb, ++ 0xa4b7f625, 0x5c4f68dd, 0x2794e2c9, 0xfc951cd8, 0x6ef98631, 0x43c6fac6, ++ 0x8fd7049d, 0xac606fbb, 0x4d099177, 0xc072ebf5, 0x808718ce, 0x5f30d360, ++ 0xff7e246f, 0xb097fc38, 0xff089fd1, 0xff119f56, 0x7f88cd76, 0xff11a967, ++ 0xff11bf6e, 0xf88dd3a9, 0xf88c04f7, 0xe231af4f, 0xc468233f, 0x2302d67f, ++ 0x4643b3fe, 0x306a8ffc, 0xc5af3de2, 0x1582ef88, 0x4616bc46, 0x27d4316e, ++ 0x4f4e81d3, 0x5e2cfcba, 0x3db1bb7f, 0x4094c500, 0x2d9d3a17, 0x1e50360e, ++ 0x6ff698d4, 0xa64bc619, 0xe44cb18f, 0xfa4a7e6f, 0xc2e90fb8, 0xa0174839, ++ 0xa6723a97, 0x15b19d92, 0x0ac60b9f, 0xbc383ffb, 0xafcba19d, 0xb89ebd44, ++ 0xae491e6f, 0x6257d10d, 0xbea23d1f, 0x7db47dc2, 0x123d1f70, 0x40c8befd, ++ 0x1be0d2cf, 0x83763fc9, 0xcc71e7ca, 0x77f9edc1, 0x6812eab0, 0xc3a66d07, ++ 0xf5c45f7c, 0x3a2ff8c0, 0xe41f9026, 0xc665d646, 0x3d626f71, 0xe2c85cf4, ++ 0xd5310cf4, 0x3164ae70, 0x5f845a0b, 0xb4e11ba4, 0x895bd6dc, 0x45fdff7a, ++ 0xf8a65ea7, 0x17e933d8, 0x69c70f75, 0x618cbf8c, 0x2790acec, 0x8187187d, ++ 0xf0bb79f2, 0xe6980613, 0x59e7804d, 0x9bacd7e1, 0x659e9125, 0xc7f283b2, ++ 0x912cbeea, 0x33fbaa9e, 0x8736fe7f, 0xe7e4b5eb, 0x5c3a159a, 0xc07d85db, ++ 0x1e0704ed, 0x1df8a576, 0x1ec8b90b, 0x6f88abf5, 0x45c78fe8, 0xfb42d3fe, ++ 0xcf8d9f76, 0x298911f3, 0xb8e8d3d3, 0xf11de11e, 0x7ccae78f, 0x47bf3e36, ++ 0xf086cccc, 0x6442c09d, 0x80adde1f, 0x8efde3c8, 0x2a9efde7, 0xc3a17f42, ++ 0xaa17db71, 0x74f3c12f, 0x9fe4d591, 0xfa332aff, 0x916a6fe7, 0x55ff3fc8, ++ 0x7d3c3798, 0x7a87dfaa, 0x947f2f59, 0x3f7f71a3, 0x59f783b6, 0xfd0916be, ++ 0x7f599f63, 0xdbc5be07, 0x06fec27d, 0x5e7c61fa, 0xd4f887f8, 0x40b9affd, ++ 0x97a056df, 0xe4655f3d, 0xc3f64c3f, 0x8341928e, 0x9996de60, 0x53e007df, ++ 0xf17df1b6, 0xf06abf09, 0x07b33133, 0x9c7e6fcf, 0xd6f9873d, 0x47ce1367, ++ 0x7b0d1d00, 0xa3abed4f, 0x66b29db8, 0xd1294f55, 0x7e7b88a3, 0x2a49d577, ++ 0xf29f8acb, 0x2d9ef121, 0x16f7c24f, 0xc827d42f, 0xdf05c517, 0xb33dc827, ++ 0xc697482b, 0x43d55dac, 0xb8b346f1, 0xee5d6c0f, 0xc1286aed, 0x147e32bf, ++ 0x6cc4b73f, 0x3266a611, 0xdfc3da61, 0xd218b36b, 0x672aac8f, 0xecd1f713, ++ 0xb844e4a4, 0x793e0935, 0x3e8ff059, 0xc60fab6f, 0xcbd7984b, 0x36cf6e76, ++ 0x5c163da9, 0xfa85cbc7, 0x19bd3bbd, 0xee5d8fe4, 0xb376f925, 0x80f583c0, ++ 0x30f3c314, 0x2acf0556, 0xbfbd2f63, 0xb17c069d, 0xc33359f6, 0x3bdae0f8, ++ 0x72893aaf, 0xe2d692c4, 0x7c7d018f, 0x6a25d9ed, 0xeab81868, 0x794fab4f, ++ 0x570e513f, 0x007e128f, 0x99878721, 0xafe5e90f, 0xaf9bfca9, 0xfda669dd, ++ 0xcabed7f4, 0xad9f2f28, 0x41cabf80, 0x3f306538, 0x8b0f53c9, 0xab8dcbd3, ++ 0x32c7b180, 0x8d9561b6, 0x7fa0ac85, 0x7dd90b59, 0xf4402c99, 0x5c7fd1b4, ++ 0xa7ba7245, 0x3e20f9e2, 0x69ee9437, 0xeef3f347, 0xf83d03b2, 0xc08c6174, ++ 0x514e794b, 0x8dd5a2bc, 0xa947cc65, 0xef8c3281, 0x008ef510, 0xbd453b2f, ++ 0x9f6f3a73, 0xf2c9ef1c, 0xe16693cf, 0x9a9bf5d3, 0xb52f9462, 0x16af9f8c, ++ 0x71e834f7, 0x6fd70c91, 0xce50b382, 0xb7113355, 0x8bf7f5e5, 0x76bba675, ++ 0xfac22faf, 0xfbfac619, 0xb5c7bd44, 0xfb0abdbb, 0xdfac6d1f, 0x754ffa2c, ++ 0xee927a3d, 0x8e35c9e5, 0xb7a8af7f, 0xa1ed1ebb, 0xefc6bdef, 0xd5bd44db, ++ 0xe0a8f3c5, 0xccee22df, 0xf189d7eb, 0xb1326f33, 0x7a9d0250, 0x28583be7, ++ 0xb569ef01, 0x19b28669, 0x7cf1c3fb, 0xb5615efc, 0xbdf0c73a, 0xc577ffde, ++ 0x8a3329f8, 0x46dbdf0c, 0x9fb6378f, 0xf07a469f, 0x4b770176, 0xfea1b96e, ++ 0xf4af1ebc, 0xb607bcf0, 0x7957b447, 0xa97bc57b, 0x4bb7ffa1, 0x7bcc54b5, ++ 0xbb320b38, 0xf8ac7107, 0xb7cfc86d, 0x90b28bbb, 0xa6aba34e, 0x720271a3, ++ 0xe2b23e03, 0x9f4f1553, 0x7289af78, 0xe9fb28a9, 0xabfc2859, 0x50d5566b, ++ 0x2bd03779, 0x2ab07f3e, 0xa007cf40, 0xdf77c1ac, 0x28357e87, 0xb17e876f, ++ 0xc5fa15bc, 0x2fd0fde7, 0x7e83ef3e, 0xf4337eb1, 0x617be58b, 0x07be583e, ++ 0xddf2c1fa, 0xdb963fd0, 0xbca90556, 0x7a02d56e, 0x8855777e, 0x35566b9e, ++ 0x51d1fd50, 0xdbcba7d2, 0x5b4100ab, 0x385bc869, 0xe0ea6a3a, 0x6f3d1439, ++ 0xfc32d3a1, 0x42b7f13e, 0xe0b015fe, 0x0157f451, 0x9abdd37d, 0x8ebb1b79, ++ 0x3d3a7ee2, 0xbd93f1c8, 0x3dea85b1, 0xfd1c7c35, 0xb08de63b, 0xec7e4adc, ++ 0x979ddb16, 0x9f28bbb4, 0xdff71c67, 0x69845f33, 0x65bafc95, 0xa4e253fa, ++ 0xa3529447, 0x0eb42d5c, 0x1ff98f7f, 0xe8f238c4, 0xc72e0096, 0xc3183d36, ++ 0x3f9776bc, 0x1411f744, 0x930d985c, 0x70bafe04, 0xe9e0d339, 0xebda35ad, ++ 0x06e5d569, 0xd0be587b, 0xb96ced4c, 0x59da1a37, 0x768675bc, 0xae16b775, ++ 0x463c21f5, 0x375875f1, 0x30d966ae, 0xcd8e92ee, 0x9725ae34, 0xcbd60de3, ++ 0x2fdf3def, 0x7b0af5f1, 0xac5521f0, 0xe491b6d7, 0x2f0f58e9, 0x4c46a496, ++ 0xfcdf0728, 0xc3f12a69, 0x91303f83, 0x8b1c73df, 0x135f109a, 0xfd633d40, ++ 0xe54bd644, 0xa15528c9, 0x3269853c, 0xe2c73f96, 0x3d832764, 0x9851f7f8, ++ 0x7e8728b7, 0xb9f28760, 0x3c43d0bc, 0xfa462a5f, 0xa3e044a4, 0xb78bb744, ++ 0x437ec929, 0x42fc9725, 0xc955f3c6, 0xeed5ed71, 0x3bb42cca, 0xdf908fce, ++ 0xf99df4e6, 0xc1cfe2c5, 0x7a15fb33, 0xd6efefea, 0x3b9ec34c, 0x3e95c82e, ++ 0xdb867ddd, 0xe9192e40, 0xfa1720bd, 0x9bf6573b, 0xcd1fd44c, 0x1fb4e3a3, ++ 0xe5d66359, 0x5cca9686, 0x2a7f6589, 0x83c7584b, 0x56285eab, 0x08872048, ++ 0xd3aab26e, 0xfcaf5f31, 0xe62a2997, 0x3c889559, 0xb2ab7dcf, 0x498f5747, ++ 0xf588d3f0, 0x93aeb294, 0xbd4a1fa8, 0x57ed3f26, 0x7f61aa03, 0x1edd1f6b, ++ 0xf22df3c0, 0x1cc7e678, 0x9dac71a0, 0x7fcb85ce, 0xc91e4997, 0x1a66aec7, ++ 0x350e1bd8, 0x498f30ca, 0x7d8997ef, 0x5c85d7f2, 0x4d55d77d, 0x75f397f3, ++ 0x3b201dbd, 0xafd55de7, 0xbbd71e62, 0x48fa661d, 0x2fac6d3e, 0x842ffd55, ++ 0x1e974e80, 0x7a71fa70, 0xba76d28e, 0x25de50cf, 0xe60a1c31, 0xd334f3c1, ++ 0xde6dfdb8, 0x8022c956, 0xa14c6bcf, 0xaf6f820a, 0x2ba4d076, 0x94d7687d, ++ 0xfbfba16e, 0x5c5c22c7, 0x461b9708, 0xa3d0e357, 0x4b8e094b, 0x8917bac4, ++ 0xd3c9ac75, 0xc3e62fe1, 0xffbc0102, 0xbe876970, 0xf3ae37bf, 0x2faab2ee, ++ 0x8f6b7d62, 0xc9da794c, 0xf2973cf0, 0x401494bb, 0xee04dd78, 0x2e79828f, ++ 0x382a79c2, 0x2f8474ef, 0x532ddb8f, 0xb73c512d, 0xaaea5e7c, 0xd133fd21, ++ 0xc9b6f944, 0xcb90d974, 0x4737d0ed, 0x4ed7c4a9, 0xe7a259df, 0x2fdf72c1, ++ 0x7ed3a716, 0xb731eb84, 0x2058f5c2, 0x11fa25a0, 0x1afee837, 0x21c0be71, ++ 0x3f703be6, 0xe79e78da, 0xdb3d62e8, 0xa4678f30, 0xe47fd27d, 0x93ed2616, ++ 0x3f483500, 0xf7946d53, 0xc3cf41b2, 0x94694ed2, 0x3c4f0e77, 0x7413621f, ++ 0xbc6dceba, 0xac53b62f, 0xa3e053af, 0x87e7a6df, 0x24a76a04, 0xeba8579c, ++ 0x80bf27ae, 0x17eaf71e, 0x877e98fe, 0x28d54e31, 0x78ffa148, 0xe303957b, ++ 0xee3ced2d, 0x0d7dd8d5, 0xf0f39fbf, 0x29bf747d, 0x3d21a9f4, 0xf5f68bd4, ++ 0x817e8deb, 0xc442fb25, 0x877ec9af, 0x40033f64, 0x78f682ce, 0x57619fb2, ++ 0xfd67b0ae, 0xb5c60a6c, 0x3e2c6cce, 0x5b7980e1, 0x739d190a, 0x4a3f251d, ++ 0x358307f7, 0x82f78eda, 0x0f7e32b2, 0x7cfd90ce, 0xb2e0859e, 0x18efc74f, ++ 0xbec1f117, 0xec0e5ca9, 0xb5f6fa3b, 0x6f9fa063, 0x7ee1926b, 0x666b6ffb, ++ 0x0c39eefa, 0x2efbc020, 0xcb866ac6, 0x9ae58b67, 0x9f9e9d3e, 0x8a9dfc61, ++ 0x27bd43a6, 0xbfc91a9c, 0xf7dd239f, 0x4a6bf89f, 0x9c51f119, 0x03e1577e, ++ 0xe707cf8d, 0xf64ce78d, 0x985ade9b, 0xe5cf0f48, 0xa6de622a, 0xab8f274f, ++ 0x573af38d, 0x1ce67cf6, 0xa0dfaf3e, 0x3b1f397e, 0x7e78999d, 0xfed79f40, ++ 0xff35ee11, 0xcf9da7e3, 0x487ea374, 0xce1f5380, 0xed382467, 0x9f3f0cb7, ++ 0xfdbc0abf, 0x9fbf38e8, 0xa7fd6863, 0x8c3adfb4, 0xe3f73df3, 0x6c51eb9e, ++ 0x4aff7cc3, 0x65f5f3f0, 0xc04d8c52, 0xd042abaf, 0x3f908567, 0xb12bda7e, ++ 0x28d34bf0, 0x614bad6f, 0xae58b5e9, 0xad5fec5c, 0x12f7de0d, 0x79893d06, ++ 0xeb25ec71, 0x6a6ff2b0, 0xfb0b971e, 0xe161a473, 0x47f517e0, 0x402ba99f, ++ 0x0bf7733d, 0xa1728656, 0xdd9fe455, 0xf0d976ad, 0x8e1d5cbe, 0x67872e58, ++ 0xea5f12d8, 0xbbc572c7, 0xcc35cd36, 0xde3e2678, 0xa37c49bd, 0xc73fa78f, ++ 0x7d7295e7, 0xf1971d28, 0x33bdc15c, 0xac7ba79e, 0x4850adee, 0xf8627ef6, ++ 0x7f824c6f, 0x6bccf9ec, 0xcf8cbd39, 0x4b37f803, 0x22f94c7f, 0xfc52c394, ++ 0xff1865d7, 0xfd6884b7, 0xa7638061, 0x194e1434, 0xf45e9c79, 0xd7ebe9f5, ++ 0x6cbeede7, 0xfdc1e131, 0x869495a2, 0xdfa4cf3f, 0x35724917, 0x5c3fe855, ++ 0x198be917, 0x31973f0a, 0xdfbc2155, 0x3a52fd3b, 0xc45fb347, 0x5897e3df, ++ 0x843dfd86, 0xeeff1890, 0xe0f5cf0b, 0x6dd233be, 0x600c7ba6, 0x0ebbef9f, ++ 0x567e51ef, 0x81917ba1, 0x5ef06a9e, 0xbccfa3a6, 0xde76829d, 0x3cb8f357, ++ 0x8790aafb, 0x1ae417fd, 0xccf2df3a, 0x409caabb, 0x64f30bff, 0xf4f49f61, ++ 0x4d95b9e0, 0xdf3f3ce5, 0xd701ec25, 0x380d7d33, 0x6ff4d77f, 0x7a04a559, ++ 0x4acf36bb, 0xc4b26ddf, 0x5fd0fd33, 0x62ccb0f8, 0xd2f41764, 0xe70372fd, ++ 0x870e54f2, 0x0ce38ae6, 0x37571ded, 0x616e77bf, 0x2ce5c69e, 0xbc20fbcc, ++ 0x577b8c77, 0x0afac7ad, 0xf068af18, 0xf1cab77b, 0xefca98e9, 0xc677b97d, ++ 0xd7bc546f, 0x7462552e, 0x628bf35f, 0x2cbcfa9d, 0x5d0f1c85, 0x683d3d15, ++ 0x855445c7, 0x62ba7ff2, 0xded0dbb7, 0xbba2f9d7, 0x9d7baf90, 0xdd787fb8, ++ 0x9e28d2f4, 0xf8e9d193, 0xedd0bca3, 0x809b3748, 0xfb251e2f, 0x8b3827ab, ++ 0xc14ea3e0, 0xa447dcbc, 0x275fba1e, 0x22a2d532, 0x4c9a961f, 0x02c273c6, ++ 0x3013fa6f, 0x37cf7649, 0x7aeaed04, 0x31b4ee5f, 0xdef7873c, 0x68a9b985, ++ 0xba79ca9f, 0x1157e7bd, 0xe6b9ef8e, 0xeaf89d93, 0x898daed3, 0x72030df9, ++ 0xb1b9f616, 0x25e583b1, 0x6c6ce0fe, 0xd68594bf, 0xb4ba5da2, 0x4fdc3643, ++ 0xf3e0aaf0, 0x2c9c1725, 0x2fe76096, 0x9d237e99, 0x21725aaf, 0x2abfde85, ++ 0x155ea0f2, 0xb1514ff9, 0xe78b1f8e, 0x694fbca1, 0xf493fbff, 0xfdff03cd, ++ 0x97971d60, 0x538c3cd1, 0xdc16bd4a, 0xf4ba6d4f, 0xe5ae74af, 0x8f7fb08f, ++ 0x3ad1ff59, 0x612c59d3, 0x177681dc, 0x9e962cec, 0xe68d1788, 0x175eb83d, ++ 0x9571ffd5, 0x38e063ef, 0xc1c700ca, 0x700d8bfe, 0x097fda1c, 0x5571ffd5, ++ 0x3ff4c7e9, 0x0bfe8461, 0xec1ff30d, 0x3fbd3477, 0x21eeac7f, 0xb1cbf027, ++ 0x9e3b5dd8, 0x23be3cc4, 0x9fefba56, 0xa2aaea1d, 0x308f76f3, 0xc779873a, ++ 0x8cbcbf91, 0xec7779f9, 0x8c71f8b6, 0xa17c737e, 0x30fd187f, 0xbc11a99a, ++ 0xfe7f4af7, 0xad315e57, 0x4dbdf927, 0x6f98aa89, 0x54552b67, 0xd6364fd4, ++ 0xf70bbd13, 0x9236151d, 0x5f9fba4f, 0x5cc1f7ef, 0xf51f20d9, 0x175e4dfb, ++ 0x2b9368f1, 0xf6fc8bd4, 0x57ef83ba, 0xa136b381, 0x3ff1ad1f, 0xc1e79565, ++ 0xa23f687b, 0xdc15b9fb, 0x6ba315e7, 0x7cf0c828, 0xf42d5cca, 0x7dff7e2a, ++ 0xf7e80710, 0x09ee2796, 0x3dd29e61, 0x8f77ff62, 0x4fe7c7bd, 0xf2177b90, ++ 0xefa74f94, 0x77e893db, 0x8c1eefea, 0x01737d71, 0xf724d1e7, 0x10aea4fc, ++ 0x8af559cf, 0xb234ae7b, 0x4e2aeb7b, 0x75787dd0, 0x7d7e7efa, 0xcf3efc72, ++ 0xdd78fb83, 0x79829f2f, 0x37efa856, 0xead27bf1, 0xff5cbc9d, 0xefca74ab, ++ 0xb38c7d87, 0x7ed0e50c, 0x41efcfd9, 0x6fbe0954, 0xdbf7398b, 0x7c23e536, ++ 0xdf9c05fb, 0xee8a7eee, 0xfd7b7c5d, 0xfa83a218, 0xee9b7f9f, 0x239fdb51, ++ 0xbb0ec0f2, 0x5bd50f49, 0xaf7895fd, 0x6e1cfedf, 0xb129766f, 0xfb04f294, ++ 0x156e5d73, 0xd737d7c9, 0x7da1318f, 0x97d5c3ae, 0x26c2e5cf, 0x895d9f3d, ++ 0x92b9e257, 0xbf622b37, 0xc0783d26, 0x6477bf4e, 0x4a97f83a, 0x9371ffba, ++ 0xafd1ee95, 0xcb6e383a, 0x2a6fa802, 0xaa5e5131, 0xe69da0e9, 0xbf036e73, ++ 0x45bf0a8f, 0x7074dd7d, 0x542efd14, 0xf94e33bd, 0x7f0e4d63, 0xea49c609, ++ 0xee9e7e0f, 0xcf733fbf, 0x9b947cb8, 0x7cb433a7, 0x1ef7efba, 0xfbac3a00, ++ 0xfcb1e1f4, 0x3a34db7d, 0xe4dee9df, 0xd7e70d0c, 0xf249f5d0, 0x73fb577d, ++ 0x843f9ca6, 0xf36719f0, 0x12f286ef, 0x71633efd, 0xc9fd597f, 0xf30d3cf8, ++ 0xaafec5b9, 0x87c6f5de, 0xc75d4f74, 0x7a71372b, 0x7d01f1e6, 0x6e3c967f, ++ 0xfb3bd0bd, 0xf885f12d, 0x6bf55d3b, 0xefc5fc04, 0xa69bd607, 0xe9d7efd0, ++ 0x7494dff0, 0xc0506c1f, 0x799e7f5d, 0xf67ba146, 0xc7c81ec0, 0x2399d278, ++ 0x33b7a256, 0xf9d0269b, 0x7abc7d6e, 0x7c0a8d80, 0x9b4d3a7a, 0x72fdf884, ++ 0x7fefc6be, 0x9df7c35b, 0xd37afbfa, 0x77c41ae6, 0x794cb0fc, 0x3c6afd3c, ++ 0x7a20e305, 0xb03cbd3b, 0x7e996e9e, 0xce7f6a6f, 0xd03bc251, 0x32ba4315, ++ 0xfa4ddcfd, 0xfe73fc36, 0x566f55bb, 0xe91388b0, 0xed2b05f7, 0xb61d8ed3, ++ 0xffdc1d92, 0x3c273f22, 0x5731dee4, 0xd9ef1f3c, 0x147cff0c, 0xbcfeb5c9, ++ 0x376e2ef8, 0xbb9ee9db, 0x69a153fe, 0x2d966e22, 0x46cbf1ee, 0xc3fded7b, ++ 0x6bda18f6, 0x47f8a4f0, 0xd1f1ed84, 0xba4e23fb, 0x749e04af, 0x0749831e, ++ 0x2dbbf47c, 0xdf7c5dac, 0x91dfdf43, 0x728b1a1f, 0xe8628efa, 0xf7df85df, ++ 0x8bf7bb51, 0x0cb19342, 0xbc62397f, 0x2f37ea1c, 0xa5ef4054, 0xf7fc7d77, ++ 0x7d45da48, 0xad87d50f, 0x8eb469a1, 0xe759bbdf, 0xb4fceb30, 0xcd2dd5f7, ++ 0xd03a274f, 0x26700de7, 0x2e192ffb, 0xcedcf91d, 0x4c91e1d5, 0xfcf80397, ++ 0x3fa1f998, 0x1f39ce85, 0x30dc78e6, 0x49e5c2ce, 0x73b204db, 0x849386e9, ++ 0x87d5a97c, 0xecba255f, 0xa2b60737, 0x329f8a5e, 0x1c0f7e33, 0x67e80658, ++ 0xd5dbce98, 0xe93f393b, 0xe44378f3, 0xf1b63751, 0x1e37aa7c, 0x917f357e, ++ 0xbef1cf0b, 0xabc7386a, 0x93a0fdfb, 0xb8abf414, 0x5d4a5afc, 0x65b7b719, ++ 0x3dff179a, 0x8d664dac, 0x722caf7e, 0x27f238cf, 0x0768b19c, 0x0dca1ee9, ++ 0x4f484d13, 0x7b2e7e6d, 0x5d7ced22, 0xfa52fdfa, 0x70c9513d, 0x98bf2e79, ++ 0x0b0f8eff, 0x8c778cdd, 0xa65a669f, 0x7dd1b208, 0x2ff80d79, 0x68c37900, ++ 0xf3cec053, 0x0c2f497c, 0xf2ce97bd, 0xf667bf31, 0xb17e5bbf, 0xdb3ad180, ++ 0xd41491fc, 0x7ca9afab, 0xd5a747df, 0x7ccbbf51, 0x6fe7749d, 0xe0ebea36, ++ 0xa833f3ef, 0x6be0e49e, 0xa64faf12, 0x0dde5d33, 0x0dd20781, 0x41df8bf6, ++ 0x0bf2e7df, 0x9902dc79, 0x63f9ef1f, 0xe7e60b11, 0x2c2afae9, 0x773c2629, ++ 0x52d1e7de, 0xdafb2e90, 0x6356d38a, 0xcb4783de, 0x93a04f2c, 0xe74671f0, ++ 0x073c35ad, 0x977f0d31, 0xfd093025, 0x8cd3fb79, 0xf9e4847e, 0x77b33a3c, ++ 0x9ffd6261, 0xc0ffb9f3, 0x69f9c05c, 0x30cf80b2, 0x744743bf, 0x41d04cb0, ++ 0x39743f9b, 0xda932bed, 0x2a96db2d, 0x7de923e8, 0xa4df93fb, 0xc69d97fc, ++ 0x8a4f167b, 0x693b5ef1, 0xf1934889, 0xe6bca0e9, 0xde5ccd86, 0xb6b2fc35, ++ 0xa65e4ee4, 0x7666097b, 0xcf7e977e, 0x2beef166, 0x5f97184b, 0x3e9d1784, ++ 0x4a07e717, 0x6f8bbed0, 0x93e45597, 0xcd326d86, 0xb7694da7, 0x67f7876d, ++ 0xeec999b7, 0x39f3106b, 0x214a1b9b, 0xb14c29bc, 0x2acfdc00, 0x6bb214a1, ++ 0xeddf8bb7, 0xb4075a49, 0x1f295e7b, 0x8e363e06, 0xf14f8267, 0xca707430, ++ 0xec5a7844, 0x8b77fc60, 0x4f3a253a, 0x742f3672, 0x60fb9633, 0x65f74f3f, ++ 0x3dd237b7, 0x3ef0c930, 0xbd110b6b, 0xd1eb132e, 0x8e3c99e1, 0x847ecf0e, ++ 0x274fda27, 0x0bfe9077, 0x05232fdf, 0xefdda3b3, 0xe67b3ed0, 0xfe5f2be1, ++ 0x0cdfbe3c, 0xfa868c76, 0x5fd7e8b6, 0x72077d41, 0xba98ed0a, 0x2c99c5c3, ++ 0x7ee36f49, 0xf9d9eeb2, 0x7d04a629, 0x5321d6d9, 0xf46da59c, 0xd42594bc, ++ 0x916bedfe, 0xfe6b4ebe, 0x7684f2cc, 0xbf4902c1, 0xaf80c087, 0xa41fcdfa, ++ 0x1b0d38e0, 0x1d2eb4cd, 0x2730fd2f, 0xceedc392, 0x7f7fd228, 0xd5fa9c6e, ++ 0xdf4034f1, 0x9e9d0788, 0x028adda0, 0xfdc38c55, 0xa1857db5, 0x7430ff4a, ++ 0x183ef4b2, 0xe6dbfb17, 0x2f3ffba6, 0x1e1d5c76, 0x7c16f803, 0xe3c4654d, ++ 0x8ff242ae, 0x94294e9b, 0xfdba7e64, 0xe3e47caa, 0xd00fb07a, 0xc52f510f, ++ 0x587ba65f, 0x9ee95b0f, 0xb7cdfae2, 0xd5e38cde, 0x613568bf, 0xab91df7d, ++ 0x92bcd126, 0xca700af0, 0xfbde8e1f, 0xfef9e30b, 0x5d81f804, 0xafadfc41, ++ 0x34de6127, 0xd167d80f, 0x85fd3e3d, 0x3904cf80, 0x1f814df0, 0x885aaf68, ++ 0x523df9be, 0x9355eb03, 0xad26abd6, 0xf44679f7, 0x5a21fccd, 0xac97e2cf, ++ 0xf8bf7c26, 0xa094d77b, 0xc36faddf, 0x5f575a2c, 0xf212605a, 0xf43e5f57, ++ 0x5cbc8c3f, 0x67583dfc, 0x67583fd9, 0x35f09dbb, 0xe2d33ae2, 0x583fd8bb, ++ 0xb7014767, 0xfe75f533, 0xe852d151, 0x971e3ff7, 0xc251fa19, 0x9f4dc179, ++ 0xbdfa65e7, 0x1bc8b0b5, 0xd2766f08, 0xddf3abf9, 0x5d7f3efc, 0x1778c00e, ++ 0xa2260f49, 0x6d2abe87, 0xafa474cb, 0xe315647b, 0x3e1b7d15, 0x3dfc6bf7, ++ 0xb24dbebc, 0x5f43768a, 0xc81f8715, 0x7de3d203, 0xa96bc1f9, 0xbf4cc47c, ++ 0xfda676eb, 0x7dd1df83, 0xf4cd8709, 0x85fdd57b, 0xb00b4dc1, 0xb945f30c, ++ 0x9eb97006, 0x5a66addb, 0xfbfadb7f, 0x647d63d7, 0x273a64db, 0x1b5f5432, ++ 0x51b0dce1, 0x5321f036, 0xfc2f1a34, 0xff7451bd, 0x90670e89, 0x3fb825b0, ++ 0xe581e1d2, 0xe10713f9, 0x03f71612, 0xefc09da0, 0x0cf2130f, 0xf5c453e1, ++ 0x41979e04, 0x76e78639, 0xc957d246, 0xef5927f2, 0xb901dffe, 0x8dc79462, ++ 0x7ab3bf49, 0xd6f9524b, 0x3cb1b924, 0xa929bea9, 0xb5f3f41e, 0xafa5f9c3, ++ 0xad728cd0, 0xf751c04e, 0xc3dff68f, 0x29d7bbcf, 0x41f7059a, 0xfae4ce8f, ++ 0xb6615eb9, 0xf92f89cb, 0x853aa039, 0xf1cb5ab5, 0xb892dfbd, 0x5afe825f, ++ 0x765069ad, 0xed043970, 0x65092c6a, 0xf3eade5d, 0xb7d050f9, 0x7ec4fcfe, ++ 0xe311da82, 0x0c161f18, 0x9729ef13, 0x0cfa7e8b, 0x971eb3ee, 0xfe199f69, ++ 0xff3fd725, 0xb89ea81f, 0x008000ee, 0x00000000, 0x00088b1f, 0x00000000, ++ 0x7db5ff00, 0xd5547c09, 0xb3b9ffbd, 0x84eb2665, 0x08109084, 0x2481d933, ++ 0x2a22c24c, 0xa20900ea, 0x088b0d22, 0x8059388a, 0xda808d90, 0x066d5697, ++ 0xda2d1612, 0x2d8a8cf0, 0x510140ea, 0x50542f23, 0xe0ffd1a8, 0x8da97142, ++ 0x9a56b16b, 0x46b20a80, 0xd3df4b50, 0x7f7dfffa, 0xdee4dee7, 0x7beb5121, ++ 0x87a3e7cd, 0x67b9ef73, 0xe77efdf9, 0xe2339fb7, 0xb40f73eb, 0xfb510bc6, ++ 0xdbb89a42, 0x26efc425, 0x238b9b8a, 0x7f16f885, 0x6796f457, 0x4e8b9cf6, ++ 0x0fa7e7a5, 0x28c5c2d8, 0xe3db4a21, 0x85a2d926, 0x7ba039d8, 0xe3ed5f7a, ++ 0x03108a5c, 0x6d3bfb7b, 0xa19e8ce9, 0x745a776b, 0xe9cccf46, 0x39ee97ad, ++ 0xa8f220d7, 0xb9bf08b4, 0x7d35fa80, 0xde98a0be, 0xe07e791f, 0x2f3d3324, ++ 0x24f06d7b, 0xd0e39513, 0xee2158ef, 0xbb7ebab5, 0xdfede68e, 0x4ad9e61b, ++ 0xeafd3ef3, 0x3fbe135c, 0x5a856afd, 0xe5cbd4fe, 0x30524727, 0xf849b47e, ++ 0x8de374da, 0x9fb89974, 0x23d75332, 0xf2a18d97, 0x8ddc83f7, 0x65f7deee, ++ 0xe5cc82a6, 0xdad5bed4, 0x3ef300bd, 0xcab588ad, 0xc67ede80, 0xfdfc5cb9, ++ 0x1f47bde9, 0x71e69db9, 0x05a1dee4, 0x567a8166, 0x9fde8f9e, 0xa67460fe, ++ 0x7d3dfa93, 0xa567924f, 0x3f5c7e82, 0xcceed415, 0xcd9e515d, 0x30fedeee, ++ 0xdffa1d4e, 0x1f38d17b, 0x7ce40fca, 0x93e79ea9, 0x8295fae3, 0x4da37ede, ++ 0xa04d5fae, 0x566bc47e, 0x962a56cf, 0x2836937f, 0xd1b3eb16, 0x43c0fabc, ++ 0xe130dad9, 0xf7fc16ca, 0x257fff2d, 0x7854bbcf, 0xbe4d226c, 0xf7def617, ++ 0x9f98a2e5, 0x3e366c2f, 0xf8ea245f, 0xc60de2f9, 0x79a215e7, 0x6fad2775, ++ 0x5cf8c049, 0x9fdd8458, 0xd0a54420, 0xc56cdafe, 0x6d544251, 0xd0cc36ff, ++ 0x4e99f84e, 0x578263f8, 0xe04a3de9, 0x29efea6e, 0x09581025, 0xe665defc, ++ 0xebae8675, 0xbf9b9756, 0x9fe2307b, 0x78753a0b, 0x96126c3d, 0x61eb8244, ++ 0x1627b09b, 0x14211fa0, 0x7cffd7ea, 0x7d2b6058, 0xaff0f772, 0x30734a52, ++ 0xd049a25e, 0xd2756efc, 0x2b95093f, 0x829a3f9e, 0x16d6ca7e, 0xf3753b79, ++ 0x3ef5633b, 0xdf7d3b78, 0x6c5596fd, 0x278776a6, 0xd1279a05, 0x6ddf0ebc, ++ 0x31f634f6, 0xcd6be3af, 0xf0471022, 0x81114bb8, 0xfc7f54d1, 0xe1094a68, ++ 0x47adb3e5, 0xf4f54a53, 0x7ab988af, 0x9a4ad47a, 0x36e7e309, 0x61e50b1a, ++ 0x13d60b5a, 0xbf17aeda, 0xf06af9c6, 0x5d459874, 0x0eb0f45f, 0xb3ef4f74, ++ 0x2f0b31bf, 0xd6f3fdf6, 0x6233e800, 0xdc0f17d3, 0xb76cfa08, 0xf634dd3a, ++ 0x5ecde7d2, 0xec5bad33, 0xdc320735, 0xba247e78, 0xdd2fde92, 0xd669da3b, ++ 0x5ee97bad, 0xf4007173, 0x425ce7be, 0x33f70e59, 0xef8915dd, 0x7e80f7ef, ++ 0x23c79bfb, 0xafaf332e, 0xf9a3bb6a, 0xd67d1d63, 0xea1ac5b4, 0x3524f74b, ++ 0x5f5bac7f, 0x4491fe15, 0x608979ff, 0xad5109c6, 0x9ca9d752, 0x06ae1377, ++ 0x69f4d81f, 0xbb0130a6, 0xb45c47be, 0x5f99d3ce, 0xa21750db, 0x8fe81c73, ++ 0xa2ed17e6, 0x7c099e79, 0x5e682d15, 0x37b376f6, 0xda1e07d0, 0xddffb65c, ++ 0xfcd2a6fc, 0x47e77a12, 0x7cc369f3, 0xbad679b4, 0x95226dba, 0xce8f61e6, ++ 0x05a53f03, 0xc04fcb4d, 0x58f494be, 0x4d365eda, 0xdc2d7f10, 0x83a570bb, ++ 0x59a670f0, 0xf3d184f1, 0x1b8276f2, 0xa37ca1e1, 0x502d8039, 0x8bc77598, ++ 0xdd97aa0e, 0xd3e9ef4f, 0xef09e629, 0x8bf6a5cf, 0x7d7331ef, 0xbe9fa6df, ++ 0x375e056f, 0xf018455a, 0x59bd1e18, 0x7e604f1d, 0x2df9d44b, 0x33e6bf69, ++ 0xfc5bc685, 0xc413d9bc, 0x3ca35bf7, 0xd6b65e78, 0x5f4f587a, 0xea0ff10b, ++ 0x2506e16f, 0x4f837410, 0x1e9fdf18, 0x44f957eb, 0xab4df3c8, 0x8f18be67, ++ 0x171422d2, 0x3df185f8, 0xf9a65efe, 0xbdff552c, 0x60dd633d, 0x43b4e7e0, ++ 0x57ec0e88, 0x4082674b, 0x014cec19, 0xfdef4f1e, 0x5c780524, 0x67bffbfa, ++ 0xd7f03e8a, 0xa3da9fb3, 0x108d3fe2, 0x8dc910e2, 0xf741536f, 0xf717a6e7, ++ 0x10c77ed1, 0x5bb62fb9, 0xf43d83fd, 0x5f4dc5fe, 0xb3383f31, 0xd9cc37d7, ++ 0xeef6fd07, 0x94c3bf57, 0x10e83288, 0x39b4c728, 0x793ec6af, 0x1bbceac1, ++ 0xf579b1f4, 0x7754cdcc, 0xe485673c, 0x22334b12, 0x7f60bf79, 0xabf5d42c, ++ 0xe0ed93ed, 0x4ac7280b, 0x8863b0fe, 0xabb7a394, 0xbefb6f72, 0xfa33d3b3, ++ 0x2eedcf98, 0x31dbb72b, 0x198df244, 0x5c6fe2ae, 0xfc9b8654, 0xf087c0d1, ++ 0x04f15d7a, 0xafa5455f, 0x053afac6, 0x334513cf, 0x1b444397, 0xe10b0f97, ++ 0xe17b448b, 0x42ce0271, 0xfc058d0c, 0x7af3cf78, 0x6f37cc7d, 0x5e077153, ++ 0xc7f07a0d, 0xfa56c08a, 0x5d9379b7, 0xb0846398, 0x47c77c91, 0x7f33b951, ++ 0x5bde8c35, 0x149b35df, 0x50f317a2, 0x271e9f0d, 0xe465fbf0, 0xfe3d18ec, ++ 0x3a51bdf6, 0xecd5fd15, 0xea308b36, 0xab2ed4ef, 0x3da24608, 0x676a17ed, ++ 0x9b0be37d, 0x5da97c1b, 0x8eb41911, 0xf3c754a5, 0xde2c13a5, 0x6e2e0e80, ++ 0x10e195b7, 0xb864ceeb, 0x0f78b69c, 0x39fd034c, 0x177e6d4b, 0x0a9f29fa, ++ 0x2c4d6379, 0xfb5e61b5, 0x776498de, 0x16b16f03, 0xdbab37de, 0x9c3b71b5, ++ 0xf4db3fe8, 0xbd2273b6, 0x116b1eef, 0xd1f1e99b, 0x61d72257, 0x55e3691f, ++ 0x3e9e25ba, 0xc84a2069, 0x70be7dea, 0xf829eccc, 0xadf0917e, 0x6a2d1d06, ++ 0x8ea08b31, 0x255a8fee, 0x8f9e17be, 0xbad1c110, 0xf26712ef, 0x8f9e16ba, ++ 0x1d47e7e6, 0x28d1ddb2, 0xaa571749, 0xcb52cde3, 0x47f2d59b, 0x918f2bf3, ++ 0xf87a9d5f, 0x254adbcf, 0x4dd2badf, 0x9d28d6fd, 0x10d32653, 0xdacf13ab, ++ 0x693fd7c0, 0xd8608a70, 0x4e33ad77, 0xf6e37504, 0x10ef3bb4, 0xdc3d38c1, ++ 0xdeef3c5c, 0xfbf246f5, 0xbf121a4f, 0x06c98e07, 0x9ff6f638, 0x85e38066, ++ 0xfbf267fd, 0xbfb21a4f, 0xfd91ffa7, 0xcc36eff4, 0x74dfb7bf, 0x6394de7e, ++ 0x5744d112, 0x02c3074d, 0x52ecd9bc, 0xfba9854e, 0x685829ae, 0x7fb1f577, ++ 0x5930a2fd, 0xbbf7a78c, 0xc74153cc, 0x4ea59ca7, 0x2c6b73ec, 0xe88ba5f1, ++ 0xea77ab7b, 0x586fd4a5, 0xd03880ec, 0x1a7752ef, 0xd8abebaf, 0xafe3a63a, ++ 0xbbf4fd48, 0x315d4831, 0xca434dea, 0x9b37bccd, 0xbf3e641f, 0x8fc72ed4, ++ 0x7accde7a, 0xaed8b896, 0x9c77f5ca, 0x50cf9865, 0x6c7b935f, 0xc6a27cef, ++ 0x67802cbe, 0x0c37c7b1, 0x938d607c, 0x07ef2df6, 0x5eb4d7da, 0xf47be29b, ++ 0x1fa1e852, 0x67e80984, 0x597c395f, 0x6e3edd4e, 0xbd54db71, 0xbe0c982e, ++ 0x5c2d17e8, 0x8e73dd2e, 0xfda2ece1, 0xef69758b, 0x866e8a97, 0x18b5f63b, ++ 0xb8b49a04, 0x5f1efdf8, 0xef6e7156, 0x8ef47a3c, 0x4dfa443f, 0x9ec2ffb4, ++ 0xf01a26ff, 0x9ee9633c, 0xadb2a1ee, 0x87a11cdd, 0xc96e93ef, 0xfd0d2737, ++ 0x9e93af22, 0xe23be2d7, 0xa17d3f4f, 0xa7fc0b2a, 0x0f3bac36, 0x85f17ef3, ++ 0xbf03c9ff, 0xaaf9eaff, 0x9dbe7861, 0x609eb3da, 0xe8f5aeeb, 0x4e174bfa, ++ 0x6f7c69bf, 0x187805b9, 0xedf3e17b, 0xc60e37cf, 0x0d895a3c, 0x6adfd209, ++ 0xfb4f5feb, 0xe0e40e38, 0x467c0fbd, 0xbb617f10, 0x332ccf65, 0x7bed4af8, ++ 0x7d509ba4, 0xdf295ecc, 0x01150cc7, 0xd9fa1b93, 0xaf81737b, 0xa736b1da, ++ 0x9e129689, 0x717ac1df, 0x13bb58f8, 0x10db7472, 0xf20dbe39, 0x17df0d3c, ++ 0x1f6f01c5, 0x5ffd9f10, 0x218d83f1, 0x76f820fc, 0x578d2b6d, 0x0e9cee63, ++ 0xe17c403e, 0xda85f035, 0x66f17e3f, 0xba2d0b8e, 0x57bf5813, 0xed477dc7, ++ 0xefb76be7, 0x9f2ba04f, 0x8b9ef3bd, 0x7375dda8, 0xc7605292, 0x9476a894, ++ 0xb9404698, 0x9c557418, 0x2fb7333b, 0x95ed2af9, 0x0f9f14e7, 0xd927f070, ++ 0x2333903d, 0x693d8593, 0x20541800, 0x7b8d2675, 0xe9526dc8, 0xcd1d768d, ++ 0xa6ba847b, 0x2db706a7, 0x1679658f, 0xfa3a0018, 0xee3dc757, 0x75827ef6, ++ 0x9bdfed6a, 0xafae6373, 0xe9abfd8f, 0xdb5b36dd, 0xbbb3cc32, 0xbced9226, ++ 0xbe8af177, 0xb09cedfb, 0xf61a39a0, 0x855ae444, 0xc460efe8, 0x0903fd82, ++ 0xf48cff1e, 0x73ff439d, 0x356abfaf, 0x718bcaea, 0xe7a0e5ae, 0xc071ce92, ++ 0xef8732e7, 0x6d5f78ef, 0xa04b0df7, 0xea1a9e25, 0x30818acb, 0x78938e2e, ++ 0xc5b9c512, 0xce5fce7d, 0xe39144a7, 0x1e3a9897, 0x3dfe88b9, 0xa4a7ca21, ++ 0x566abad2, 0xd3bd48c6, 0xf78e31d2, 0xee40d357, 0x544d94ef, 0x6bafa5f4, ++ 0xaea438f0, 0x5c559f67, 0xb9d69e7e, 0xa78c7d6f, 0xbe5de691, 0x4b05fae6, ++ 0x2a685ca9, 0x0d9a084e, 0x78c18ff3, 0x6192fed5, 0x9d7fa449, 0xaff3aab2, ++ 0x716fe757, 0x75f7ea66, 0x351bfce8, 0x854ee2fd, 0xa3fe37ed, 0xd8feb3fa, ++ 0x0f54ddc0, 0x777b9d33, 0xae72e416, 0xbcb903c9, 0x18f69c31, 0x527f7dd9, ++ 0xed30f9e7, 0x7e00fb3f, 0x13cf16be, 0x89f7e5c3, 0xb002980f, 0xed278bf7, ++ 0xb6fd7c65, 0xa663d236, 0x29044ab1, 0x32bf34fe, 0xf63d65e1, 0xf3ff8993, ++ 0x2bad277c, 0x8d97d537, 0x671cdc75, 0xe797794a, 0x03391be1, 0xb904d1fa, ++ 0x0fd0ef8e, 0x85331d79, 0x944acad3, 0x3c826758, 0x4b94e998, 0x7dc8a859, ++ 0xad784b32, 0xe13aef18, 0x9f6f76e3, 0xffa179b6, 0x85db0dbf, 0xf0bd7de6, ++ 0x2279f3f3, 0x228de5c0, 0x126fedc8, 0xe0d75c9d, 0x7372744d, 0xa393a4bc, ++ 0xff0ccc83, 0xb7ef302b, 0xd686f222, 0x3c663ad3, 0xf6c19598, 0x8640cb50, ++ 0x7bcdf7cf, 0xb43f4a86, 0xaaa6a78f, 0xf53678fb, 0x90eaf333, 0x50385c7d, ++ 0x77c667c3, 0xb38ea7ed, 0x644ef63d, 0x4ae1c112, 0x7a57a515, 0x29ded8ab, ++ 0x3f0a4732, 0x8263a7e1, 0xe57b0039, 0x7c457780, 0x2ceb99bc, 0x663c3ab7, ++ 0x587fab96, 0x50c6a221, 0x56f90ffd, 0x9ecd3fa6, 0x57f6ae99, 0x72f7de74, ++ 0x6e9f3d0c, 0xa58a6d6e, 0x6421d4fa, 0xdef8e86f, 0x2d3bf155, 0x4eaebfb0, ++ 0x969f3e37, 0xae4bb463, 0xc066cd15, 0x6318fa77, 0x0b807dbb, 0x2a6555d1, ++ 0xe92317d9, 0x88c423df, 0x82bf196f, 0xa89fe3f5, 0x769d9c7d, 0xe68676ce, ++ 0xb7d539b1, 0xb440952c, 0x164fdafc, 0x11615c60, 0xbe0d1c7f, 0xfd99a6ff, ++ 0x6f49876e, 0xf23e92f4, 0x08490371, 0x253e1652, 0x63f50afd, 0x3ca107a4, ++ 0xf2e2e0de, 0x782de924, 0xc3c1ba7f, 0xc5a9fdf5, 0xa5bf473f, 0x00b73f6b, ++ 0x121c6b1f, 0x291c6bbe, 0x2abff801, 0x90a79ada, 0xf72a2efa, 0x5947edb4, ++ 0x029e2c1e, 0x40e8bb31, 0x6b947edd, 0x3aabec7a, 0xea57db3b, 0xe9516ffc, ++ 0x99a896f3, 0x9c12e4d7, 0xf66bd96f, 0xcce87d70, 0xa3c6d759, 0x7f7ae56e, ++ 0x5e7353f4, 0x1ada3e11, 0xf7bd9b8f, 0xf6de7e60, 0xb471fdae, 0xe30da3ce, ++ 0x359ffe79, 0x27fe7978, 0xf972a61a, 0xfbe2d4b7, 0x9cf89db8, 0x5b6bcbf5, ++ 0xd4c92cbb, 0x78abc8be, 0xf72f5fb1, 0xe880408a, 0xca558361, 0x07240d81, ++ 0xe6277fb0, 0x56f87cce, 0x7bed3e01, 0xdd79f418, 0x308a4bd5, 0x25f1f4ce, ++ 0xfebbb416, 0xdce2216b, 0x7df9f4bd, 0xbfadaef4, 0xa9dfc546, 0xe7861417, ++ 0x27eb9329, 0xaffc77d0, 0x9f6e5999, 0xa954d0b5, 0x4707b3ff, 0x0b44fc04, ++ 0x0da777cb, 0xdcb0de82, 0x40341aea, 0x209d07a7, 0x9e9d0abc, 0xffa9e27c, ++ 0xdfe9f448, 0xeafb680f, 0x1f5fe02f, 0x1a45fe49, 0x06bfa7cc, 0xe8921b7f, ++ 0x5a78fd81, 0xaf480fb5, 0xab9c808b, 0xe07cfd55, 0x089fa83f, 0x71d5fe97, ++ 0x6127923b, 0x573c60ff, 0xca7f2f56, 0xea60f1dc, 0xf1deaeed, 0xfc2db7b6, ++ 0x7ea9afcb, 0x5bf2602a, 0x129d0e49, 0x8f7fa76d, 0x64896d75, 0x62b65b3f, ++ 0x5c87af09, 0xafde0115, 0x52cb8ad9, 0xf1e7fc4f, 0xfe0f0f1d, 0x161c808d, ++ 0x7fbd3c62, 0xf3047d6e, 0x9eace7a7, 0xfef8f543, 0x63fdf961, 0xf0ecfef7, ++ 0xd4f7941e, 0xca8cfc14, 0xe00ea73f, 0x73ffca7e, 0x9bac08c9, 0xa248b6e4, ++ 0x567c9efe, 0x3e883a09, 0xadf65b73, 0x8cf9a24c, 0x1a65d8da, 0x16fe654c, ++ 0xc8e511a5, 0x400f53a1, 0xea947e5e, 0x6e8cbc62, 0xb1939b75, 0xfe0706cd, ++ 0x73cb0572, 0x69cf9ca3, 0x60d27cf9, 0x47ef2bd1, 0x57c76d28, 0x0cd7de10, ++ 0xf580bf7d, 0xf3ccd158, 0xeb3eddd8, 0x1d791b9d, 0xde6049a4, 0xcb0f3625, ++ 0x137f8095, 0x2f94ece8, 0x737ac3db, 0xe021ffb1, 0xc12f94f7, 0x0cf33903, ++ 0xa097d1d9, 0xaf0b21fd, 0x6f2dd9f3, 0x12afc345, 0x83a9f643, 0x77e4d7de, ++ 0x9afb414f, 0x7a012ea1, 0x95c8fa18, 0xda9f0153, 0x7137bb5d, 0x0f76d53f, ++ 0xdd8accec, 0x4327f6e7, 0x784abbff, 0xbb5f4032, 0x8597fd64, 0x96998f5e, ++ 0x4be9b15a, 0xe628ef59, 0xf569317a, 0x932fb416, 0xaa83cf7a, 0x799d133c, ++ 0x6498efcc, 0xfaf8bd5d, 0xfbc6bd25, 0x127f6e0d, 0x1c9acafc, 0xd225f924, ++ 0xf26c05b0, 0x37498efb, 0x7e5c30a6, 0xa9b2fca0, 0xefeb4872, 0x3bf09b41, ++ 0xf4a19fa8, 0x8dec7e1c, 0xb7772936, 0xbd00df12, 0xc6977268, 0xe58da675, ++ 0x97e0bdef, 0x772566c9, 0xf923c117, 0xb7c930c1, 0x73f8e07f, 0x1cb35663, ++ 0xa5a7f4d6, 0xc1cf92e1, 0x53ef8b07, 0xb0437ca2, 0xdcaa85be, 0x0e571616, ++ 0x28a88af4, 0x5f8c50ef, 0xc14eef6d, 0xba1e481a, 0x4cd6aed1, 0x4e9a54fa, ++ 0xf01c8a9f, 0x27a1e483, 0xef859bca, 0x49fb687f, 0x18cf3411, 0xa38fc494, ++ 0x14766a51, 0xf27d1559, 0x36d6d4db, 0xc3fbdbf0, 0x1a8dbf24, 0x5b457ccd, ++ 0x2f38e867, 0x11f77ed1, 0xe485797f, 0xfdf68f86, 0x1689c8e4, 0xa6cbebc6, ++ 0x5f24fdea, 0x2008e48b, 0x18ec4b68, 0x08a37bae, 0x6691858e, 0x3ec3ebe1, ++ 0xdbc24ad7, 0x94e75895, 0xbb4308f8, 0x1b58f8a2, 0x5d0ff1f6, 0x93c559bf, ++ 0x23ca5c39, 0x6f26b873, 0xb222f15c, 0xf5cbf5af, 0x3b18e2de, 0xa499f008, ++ 0xc775b0fc, 0x046f8b58, 0xe647279e, 0x1c9c1cb3, 0x4f90e339, 0xf04a3af0, ++ 0xa1bd743c, 0x1ff612eb, 0xa6dd0fa6, 0xfb09bf08, 0xfb1b73f1, 0x9daddabb, ++ 0xc117fe4f, 0x8e497db5, 0x33f97607, 0xb0ec2fb4, 0x58da6653, 0x8e876d5f, ++ 0x07dbed48, 0xcfb0033a, 0xbacab39f, 0xbdfa9e7f, 0x6b7cb043, 0xe598379f, ++ 0x1a30e0c8, 0xa379f608, 0x5bb4578c, 0xfc875eeb, 0xec915f6d, 0xb30819a1, ++ 0x8f88c4fd, 0x10fd9347, 0x51bbfc90, 0x3f08de09, 0x9b73ffbd, 0xd896fb40, ++ 0xaa54dac0, 0xc699dcb7, 0xf64839f3, 0x578c52f5, 0xab7cce11, 0x049bd625, ++ 0x3fccf4f9, 0x5a372ccd, 0xc91ea9f2, 0x4afd9d7c, 0x49bc332d, 0xabc52788, ++ 0x24d96b78, 0x7f860fdf, 0xf2ddef12, 0x6558bffb, 0x76d41bfb, 0x3f7e2af1, ++ 0xf694e950, 0xdf07f33f, 0xe80b08f4, 0xe95a677f, 0x9103c0c3, 0x31e2125f, ++ 0x60cf2ebf, 0x950de1df, 0x9e99b957, 0x5cc53f54, 0xfd6b9f95, 0x38fb03e2, ++ 0x6ff2c5e8, 0x0eadc2de, 0x1575f7d0, 0xcc922e8e, 0xcac560e2, 0xd7e9d828, ++ 0x30c1ccf9, 0x76625fda, 0x4f47b791, 0x5eb8c54b, 0x66b96e39, 0x00cb05ef, ++ 0xedba17df, 0xe3d66ee2, 0xf6f5a383, 0xcfe78693, 0xadbee5c2, 0x9f789b69, ++ 0x125e5ede, 0x67cff926, 0x9b3f72e1, 0xe8ad7d22, 0xab9ee97f, 0xd1dbd3ee, ++ 0x8aae16f3, 0x8ea87de6, 0x7bc1b27b, 0xd019c7df, 0xa972a6db, 0x378dab8d, ++ 0xabdda675, 0xeece9e10, 0xefc00b0a, 0xf74ab379, 0x7382c34b, 0x3a76cfc0, ++ 0x9c797b7c, 0xd879e3ca, 0xb333f1cf, 0x338eb063, 0x4a7a92af, 0xf4a90f6d, ++ 0xe38cfb00, 0x4c51755d, 0xfbad425f, 0x7b638f6e, 0x4071a149, 0x4656476f, ++ 0xed7e866d, 0x169379b3, 0x47979e82, 0x10f51c70, 0x3fb521f6, 0xf4cb1d54, ++ 0x5557ff38, 0x87af006f, 0xb74c6d8a, 0xfea5da87, 0x737ad7fd, 0xd3dff110, ++ 0x903fcf33, 0xbe9ddf49, 0x0db8c8e3, 0xfcae7654, 0xf982ed90, 0xe1a66b2b, ++ 0x7795f9bb, 0xfa9c074c, 0xabf357db, 0xa3c3718d, 0xb077de69, 0xe799f8ce, ++ 0xbfa89bf7, 0x0fd555c1, 0x9610e621, 0xe7883bee, 0x5aceb6b5, 0xb9f6a3c0, ++ 0xcf60528f, 0xd8fbd99c, 0x5a54fdce, 0x657f7da3, 0x4af2bebe, 0x66742af7, ++ 0x7c04cee9, 0x2f842d6b, 0x2f2a91d0, 0xf474aa97, 0x61df748b, 0xf95eafb4, ++ 0x23c7d607, 0x5f243a72, 0xf187e3bb, 0x5bede381, 0xbbe8519f, 0x5af6f0aa, ++ 0x3c81cd2e, 0x1284ebcc, 0x00d2568c, 0x9d176957, 0x63a30674, 0xce6bd873, ++ 0xf6d55b7a, 0xa6293890, 0x5dfaa09a, 0x36aabbe8, 0x3a01d7b3, 0xe61b0116, ++ 0x8abeda1f, 0x1fbb739e, 0xb452bcf8, 0x7bb1e7c9, 0xf414bdee, 0xc441116e, ++ 0x9e3f8e77, 0x70f419b1, 0x9963f76a, 0x6864b8fa, 0xe57ce179, 0xde824ffa, ++ 0xe927ae08, 0xd6f41589, 0xcfb0661a, 0xc49e3f4f, 0x31e346f4, 0x3c7e9d3d, ++ 0x5abae38b, 0x53fc5abf, 0xcdc6da78, 0xb6f03ec0, 0xab3e838d, 0x6f6119f1, ++ 0x3afb63cb, 0xf60f2dbb, 0x449fc6a4, 0x3f265b71, 0xa265b40f, 0xe92633fd, ++ 0xadc6d0af, 0xd379327c, 0xeaefd2dd, 0x7d418d37, 0xb5d466e4, 0x7d6fbf7e, ++ 0x866c1b59, 0x4840f0fa, 0x13fa5d3d, 0x9e82789f, 0x5660be4b, 0xd2e13eed, ++ 0x7a92e8f0, 0x03e5c332, 0x5b97069b, 0x558f8993, 0x3ca96e61, 0x9e07296f, ++ 0x678d7e90, 0xe0c97df2, 0x1eb1a7b3, 0xaa58e7f0, 0x914f40e7, 0x1aead6f3, ++ 0xbde7421c, 0xc94583f2, 0x9f5e6ff0, 0x1a1af32e, 0x357f921d, 0x5a9f243a, ++ 0x106e3511, 0xc95a37de, 0x3d81c85e, 0x63ed2079, 0x3e1c2f6b, 0x897af06d, ++ 0x17d4f725, 0x63b7c86d, 0x98de2c3f, 0x47d3d76f, 0x07d1f6e3, 0x938b7248, ++ 0x2c1e2ddb, 0xb812d1a1, 0xe3717a17, 0x5f9b7376, 0x97bb7bf0, 0x7c8c9fda, ++ 0x5bb44df1, 0x00b631b4, 0xfdf6ac7a, 0xde450de2, 0x47bcdd72, 0x37c2376e, ++ 0x1f58cdb7, 0x2f58c7b5, 0x7f4c1749, 0xf977eaff, 0xf47d6341, 0xe8fd6301, ++ 0x01ceb7bb, 0xfd985619, 0xa7a19af7, 0x00e5387f, 0x67b1cbe4, 0xbe068d9e, ++ 0xdf2a3eaa, 0x3423fb0f, 0xa8f081ff, 0x6ff73f40, 0x5ebe5853, 0xcfd10790, ++ 0xfce2d63e, 0xdd3d70a0, 0x7eff0a54, 0xf6c2fb8b, 0x1cdb4427, 0x7559d12f, ++ 0x90693bfd, 0x17bf5aff, 0x41b7adb7, 0xb71d0a5f, 0x222b7dbf, 0x9ff82ebd, ++ 0x77cbc64a, 0x164fd497, 0xbadfd047, 0x1e80a6b7, 0xb0a97e4b, 0x3a792e5c, ++ 0x4dd065eb, 0x5779ced7, 0x2a673973, 0x8bf343c3, 0x82576e2d, 0x8e775451, ++ 0x60f13d17, 0x6d2ef341, 0x85f6d30a, 0x175927cc, 0x62d24792, 0xcf78bf7c, ++ 0xee207fbe, 0x847f615c, 0x1b15f4e3, 0x9d69ef8d, 0xaa1ec12f, 0x4fd8263c, ++ 0xdbe5b952, 0xb97be330, 0x3aea85ae, 0xf845bd34, 0xe758172f, 0xf8a9b225, ++ 0xbe23ff18, 0xb7d3b57e, 0xaf607d29, 0xcb4972be, 0x57e03326, 0x753f7c23, ++ 0x1fddb1a6, 0x2cf9a08c, 0xf60c3d22, 0x5e65c90c, 0x310db9df, 0xe7a28fec, ++ 0xcfcf41c2, 0x90718e89, 0x4576e7d7, 0xa5dc6479, 0xea939c63, 0xf80ea98b, ++ 0x86668855, 0xb2f83553, 0x578dd259, 0x8c0447af, 0xed2cd175, 0x704b6aa0, ++ 0x2551e01f, 0xe03bf93a, 0x9aaedf51, 0x007075d6, 0xef9092f4, 0x04e38785, ++ 0x8c6d234b, 0xbe7ba5bf, 0xd7bfd30d, 0x4ecd31ec, 0x8fa4fcd4, 0x0e10de56, ++ 0x7aaab6fa, 0x815dcb65, 0x3d69fb9d, 0xebbf34ab, 0xa7f3077a, 0x7e49361b, ++ 0x2663fa4f, 0x7eb2d9d6, 0x06fbaf38, 0x055eebc5, 0x5d86757d, 0xef492fd5, ++ 0xd225fbc3, 0x267a422f, 0x49ba49fb, 0x40acdddf, 0x420b6cdf, 0xdfb96e7f, ++ 0xf82cfacd, 0xeff5fb24, 0xd2beb071, 0x2bea4332, 0xf107eb2d, 0x94c17ff7, ++ 0xca87a093, 0x93dcb4f9, 0x60f47acb, 0x0c4efcb3, 0xd23f3c12, 0xbaed334b, ++ 0xe7fa6979, 0x6fefa761, 0xb6f5bae9, 0x214776c4, 0xe22a23de, 0xdf9c907e, ++ 0x6eafcaaa, 0xf9fc0382, 0xfbc52b1f, 0xdad19711, 0xb8cba775, 0xde49b8eb, ++ 0xf63b6a6d, 0x669b97fb, 0xf2057ddc, 0xb9301e34, 0xf83add1a, 0x5899bd7b, ++ 0x1debc7ff, 0xb8d3c005, 0x737fd249, 0xf5f25f28, 0xf3823188, 0xf6a1fe51, ++ 0x93748ffb, 0x270c4ca1, 0x3e7ea4ba, 0xdffe922e, 0xecc531a8, 0xeddd232f, ++ 0x1af2bee6, 0x5e5219ac, 0x5f8adb95, 0xf98facbb, 0x85117068, 0xf1f59fd2, ++ 0x9cb36532, 0xd7f39797, 0x83a7fdc6, 0xab1f6cfd, 0x07c34772, 0x9658d1d1, ++ 0x8b1f2ac3, 0xf59fa10d, 0x0fd00ba0, 0xa7a5c2e8, 0xdc7d231f, 0x47fb48a0, ++ 0xb27293cc, 0x5bc25625, 0x0fd133c3, 0xe89bbde3, 0x108fd243, 0x8bef8dff, ++ 0x0a9ed25c, 0x75b45bb1, 0x10b767f7, 0x7433b83d, 0x7a50ce71, 0xd8c09610, ++ 0x94478aef, 0xa71d8f8e, 0x2d922a10, 0x70461fc2, 0xb8646c83, 0xac0965dd, ++ 0xb10cf9a4, 0xb50cfc48, 0x2923fa48, 0xe02f0fe3, 0xd51b5ef6, 0x2c5bee4b, ++ 0x24bed4bc, 0x283fb059, 0x9894f49d, 0x409dfc01, 0x1999f089, 0xf12a127e, ++ 0xec8c497d, 0x1ce884bf, 0x9fd45a79, 0x654034d7, 0x6f10e36a, 0xe04fac14, ++ 0xfe02e8fb, 0xdf926fde, 0x0e542d7b, 0xa9fb934b, 0xc318557b, 0xd0cd64af, ++ 0xb4cbd04c, 0x697a4649, 0xa5f490c9, 0xb922df95, 0x2793e582, 0xb4a67211, ++ 0x99cb3869, 0xcd714746, 0xa7d7ec6e, 0xb250bda4, 0xc76ba6fa, 0xe23b7e62, ++ 0xc7cad83c, 0x38e4efa7, 0xbcd36944, 0xdd83dedb, 0xcfc1ddb1, 0x8afa6487, ++ 0x2b37a033, 0xe9bb05ae, 0x2f75e941, 0x7be912d9, 0x538cdb5f, 0xba72a7bf, ++ 0xd09be77f, 0x36cfa623, 0x42e9fb73, 0x934545fa, 0xff5ae71c, 0xea4496e7, ++ 0x0a09daef, 0x1cbbd587, 0x886594ce, 0x9df8a83f, 0xa379d2af, 0x5dfdcc43, ++ 0x3435e624, 0xfe073533, 0xfb2cd27b, 0xd21f6fd0, 0x36544fda, 0x361a4f42, ++ 0xad43ee59, 0xbf41fa3d, 0x7d48668f, 0x170ab16a, 0xe5704ead, 0xc36be5f6, ++ 0x51a2d2ba, 0x5459835a, 0xa9359ebe, 0x969ceb0a, 0x006ca62a, 0xe6667fdc, ++ 0x872e917c, 0x6f1d3208, 0xf83c65cd, 0x1ad77744, 0x48cb6fac, 0x44d75f5e, ++ 0x9d72ca67, 0x29d0bc1d, 0x52e81f58, 0x390f67f3, 0x4806a33b, 0xc3db117f, ++ 0x7c092a65, 0x2f78df52, 0x7765aae2, 0x3720bbd8, 0x8b3fde16, 0x2d65e1e3, ++ 0x7c930f64, 0xf68ceb13, 0x8dabd930, 0x5da85f98, 0x82bf6a1b, 0xe5374046, ++ 0xbba614eb, 0x5b1e8d61, 0xc537f312, 0x4794f589, 0x0721d306, 0xce0e3dca, ++ 0xbec0bd6f, 0x3ce09afd, 0xc1587e0e, 0x32db43c9, 0x77d8cd7d, 0x6c25cd25, ++ 0xf8e4464f, 0x330d6f98, 0x6e885c13, 0x6de952df, 0xe089fc1a, 0x24ce9647, ++ 0x78c9c3ec, 0x700e780e, 0x1d324666, 0x6bf8043b, 0x8999d597, 0x72ad75f9, ++ 0x9c231098, 0x33d252b6, 0x85bb33ed, 0x22cbbfbe, 0x7dffb1c2, 0x57f3bf6a, ++ 0x51378a58, 0x585d887d, 0x9e8006a2, 0x639e99f2, 0x318b7db2, 0x8a7763af, ++ 0xca1bd0f1, 0xf397add6, 0x5841e952, 0x68e30a3a, 0xdd5b639c, 0x6bc7f005, ++ 0x3d9313f4, 0x9e867b69, 0x8c2b660e, 0x01cf5a7f, 0xcf5f39f8, 0xf781dd2a, ++ 0xe81f7cf4, 0x60a4da63, 0x645bf03a, 0xcbbce6ae, 0x03c289b3, 0x90ace27d, ++ 0x5aecfbfb, 0x8d43f30b, 0x83fc68af, 0x4f6bc1e8, 0xb6f7c5e8, 0xf1129a06, ++ 0x760dedee, 0x70689f2e, 0xbbc10b0a, 0xeb9121b5, 0x5c5c1a3b, 0xf36435b6, ++ 0x7835dff3, 0x61abbeb8, 0x699fd73c, 0x4f7d72f0, 0x7f2e54c3, 0xcfcc50df, ++ 0xf044fe35, 0xf1a43e61, 0x691f8d19, 0xa5f1a5f4, 0x405aba50, 0x80bcbe60, ++ 0xa7fe67bf, 0xc3ac3df1, 0x8fcbd054, 0xd75b3c34, 0x5fb1344e, 0x9173c552, ++ 0xcf53e4f9, 0x91150e02, 0x03d8e79c, 0xc33b4897, 0xf626c525, 0x5c6f8ec0, ++ 0xa35aede6, 0x5637bf93, 0xa3a2c228, 0x1cea9be3, 0xe3a3a2c2, 0x0d63eb9b, ++ 0xeff5f9f5, 0xfa8832bc, 0x3be31f1f, 0xfa1cfc0c, 0xff0fa7c5, 0xfa3f9e99, ++ 0xc019e38b, 0xeb63cd3b, 0x8ef71883, 0x9d1e7570, 0xd8775e72, 0x4c369fd8, ++ 0xcfe10bf5, 0x2cd7cbae, 0xf9bec771, 0xe015f418, 0x57f9e087, 0x54873f15, ++ 0x7e0294fc, 0xab25f744, 0xf2eb3ca4, 0x7c05012b, 0xa7dd49b0, 0x825e3cfa, ++ 0xd124e1e7, 0xedde0119, 0x98f10215, 0xa66677c3, 0x642b5f60, 0x5f87cd54, ++ 0x0e1fed6d, 0xfea53fa2, 0x3ecfeb00, 0x17e7247b, 0xa4f5bf08, 0x7ea51fbe, ++ 0x9d13b73f, 0x7c790c43, 0x36bc6311, 0x069a07f4, 0x5fb34abe, 0xa2dfd814, ++ 0x45027159, 0xf2f3eae5, 0x3f218ab5, 0xe66991d6, 0xc32538fd, 0xb16fe5c2, ++ 0xd10839d7, 0xa348f2cc, 0x9c1be253, 0x9cde578f, 0xe3a45b6f, 0xf3eaa5bf, ++ 0x21936cb2, 0x864a6f5f, 0x2dfdb7cc, 0x77951398, 0x16daa767, 0x7173bf32, ++ 0xbed6b8de, 0x3560bb34, 0xeba59bfc, 0xfbd33590, 0x8b4cc0fd, 0x9ca72f3a, ++ 0x56e49d8f, 0xf4afe714, 0xbd35ffc9, 0x79fe18e5, 0xed9fcf31, 0x4f1dcaa9, ++ 0xac3c40ee, 0x9630c3f2, 0x54a39543, 0x604e447f, 0x77d62cdc, 0xad0a91bc, ++ 0x7bc556b3, 0x451f93e1, 0xe9686f23, 0xa47fe92e, 0xed650bb2, 0xffec151d, ++ 0xbed0f5aa, 0x6afe0018, 0xbcbf2b8c, 0x4ee8c3e3, 0x93f85bf6, 0xce51fcd5, ++ 0x75ddaa83, 0xe0a3f384, 0xe18ff2a7, 0x36cf38fe, 0xcaa5fbf4, 0x12976cd7, ++ 0x453e1962, 0xc0997fcf, 0x2e7dd8f3, 0xe96d7c01, 0xfa12abf3, 0xed0953ca, ++ 0x6b9b8b47, 0x62a5b17e, 0x6f38e7dd, 0xa98ef4b1, 0x6f744547, 0x5ddfa1ff, ++ 0xbdc6a995, 0xb117122f, 0x3822c3ff, 0x9ab961af, 0x90367667, 0xc3be2311, ++ 0x0374b4af, 0x3887147d, 0xf9062baa, 0xd4c867b6, 0xf74f0bea, 0x7d394a66, ++ 0xe215f68a, 0xcd5a67a8, 0x699e2fac, 0x53fde28d, 0x7edf7adb, 0xb76b65c4, ++ 0xab061c28, 0x479c1d11, 0x2ccbbb56, 0x06f97aec, 0xff5c4ebf, 0x327aacf3, ++ 0xb5f40eaa, 0x6ef14da4, 0xb59cf9a5, 0xea0662bb, 0xd2a553e6, 0xdb585557, ++ 0xcdaff438, 0xcfce04bf, 0x96edbd81, 0xf9c7dfb4, 0x34eed480, 0x15ff2feb, ++ 0x9262f1c1, 0x9e626f5c, 0xf68e3627, 0xd25d8ec0, 0xf596b3b6, 0x2708d6de, ++ 0x56e39154, 0xff8079e3, 0x516378c0, 0x04e37d4a, 0x4fed1f4d, 0xdeb330ec, ++ 0x5f62798b, 0x85f3571e, 0x54eeefb5, 0x8553bbbf, 0xdca66a5b, 0x25fb5a9f, ++ 0xe9d15d6d, 0x9ee8fed4, 0xa35cb877, 0xd9125fb6, 0x79f90791, 0xd4c45774, ++ 0x99bf9700, 0x778d1cf2, 0xbc626daa, 0xbf67dba2, 0x7f72b4ce, 0x3cca36a7, ++ 0xc0ec3e45, 0xaf1b40f6, 0xb26b44e7, 0x0d5fbf02, 0xc0f64de0, 0x474f5d89, ++ 0xfb1f789b, 0x68f977ff, 0x484b1573, 0x91c1fd3e, 0x9dec63d0, 0xb77f7e6a, ++ 0xbff967ea, 0x7d56bfe9, 0x562a689e, 0xfaf991c7, 0x700fcb42, 0xe64576ca, ++ 0x77d8419c, 0xaeb9460b, 0xf3fc11bf, 0x27d79975, 0x841eb886, 0x4fe0b79d, ++ 0x238f6c71, 0x2ff5002f, 0x94c320de, 0xb460b3e0, 0x3b1257ca, 0xd9ffc2c7, ++ 0x447a96e5, 0x88325af5, 0x44556e08, 0x6d027e5f, 0x7c2cc075, 0x33397f54, ++ 0xd101d255, 0x22e38dbf, 0x45f84cc1, 0x9f84d90f, 0x93bf3fe3, 0x6a7573f6, ++ 0xe6fe1330, 0x544fd813, 0x66080f56, 0xa71fc1c6, 0x4cf549d2, 0x97a3af7a, ++ 0x4cc1cdea, 0x6d2749e8, 0xf788efd2, 0x0baa87b0, 0xb72ebb64, 0xb5db34f3, ++ 0xf404a3bb, 0x51b3d356, 0x8f35874c, 0xa07e3839, 0x4a96f3f5, 0xfb0fd4a7, ++ 0xe4dbfd5d, 0x3744967c, 0x55273f73, 0xde125efa, 0xa43bf3cc, 0xb12d99e6, ++ 0x55977ac9, 0xfba3fc70, 0xb3b630f1, 0x3c75278f, 0x3f8e7183, 0xe9e39c3e, ++ 0xa2c0ee5d, 0xc1defc3d, 0x9f2a70e7, 0x5e620b08, 0xc51e3d9f, 0xbfa9a77e, ++ 0xed00b0d8, 0x53096ecf, 0x6cf93f10, 0xc625b0a0, 0x40cddce3, 0x299fdb96, ++ 0x7c978e2e, 0xf71c6af6, 0xcf50d957, 0x624a8971, 0xa93fd013, 0xedbd0a9c, ++ 0xa50fadb3, 0x7d52ff60, 0xd13eea2d, 0xd8e7e0bc, 0xd823dba7, 0x89fc71bf, ++ 0xcfae19ff, 0xcacad0df, 0x95bf462d, 0xfded4f86, 0x9ed299e7, 0xda533cff, ++ 0x3a665f11, 0x11355e19, 0xf2a40f6d, 0x26fee4fa, 0x407db338, 0xf38129fb, ++ 0x26f6db1a, 0xe54fd428, 0xc85e51b3, 0x306b2ef9, 0x870c37f3, 0x445f3508, ++ 0xd9f93db0, 0xaff638b6, 0xfdcd3693, 0x972db67c, 0x5bc7effd, 0x99a71cad, ++ 0xf18d9d06, 0x2df0cb98, 0x63cc6f32, 0x0896d5ff, 0xb958f013, 0x373e22e6, ++ 0xfd66eb47, 0xd94772bb, 0x45eeb534, 0xe7f2bf7c, 0xf2f06bb7, 0x0245ffc3, ++ 0xb568f996, 0xd66b47ca, 0xfc831a5c, 0x3327f164, 0xb39fe5e7, 0x4f810678, ++ 0x5265c286, 0x9f47ca96, 0x6df79879, 0xf239d135, 0x726caa84, 0x284f557e, ++ 0xad55efac, 0xe641f4be, 0x055a6f8f, 0xb64f94f2, 0x87ad17dd, 0xe4964e7b, ++ 0x7bdfbd5b, 0xb5157db8, 0x1ebfdf97, 0x66d9f3cd, 0xa13e60f5, 0xdfc1faf8, ++ 0x51fe613f, 0x91b657df, 0xe177901e, 0x8e89cffa, 0x3e087e9f, 0xff60ead0, ++ 0xcf99e117, 0xb6b09cb3, 0x4ffac22d, 0xfe60e53c, 0xcd562270, 0xe7b927f7, ++ 0xae7cc2cf, 0xbbfb15f9, 0x20259ede, 0x8c07162f, 0xcaf36afd, 0xb9fc92cf, ++ 0x8313ce26, 0xf843587d, 0x9f847f40, 0x7ff7f09f, 0xa1f7f2b2, 0x77c189eb, ++ 0xf0fb7563, 0xc3a608a9, 0x5e258313, 0x62c8ec4e, 0x2b15d3b9, 0xcbe69ae9, ++ 0x5889eaf6, 0x0924e259, 0x29d2a1e8, 0xc4c4e1e9, 0x4fcfb636, 0xecb93b28, ++ 0x2aefcab2, 0x2d38d5eb, 0xe82269d1, 0xf88b3407, 0x075d7d94, 0xe3f00ef4, ++ 0x065c0571, 0xe85c06c3, 0x663a26c7, 0x2caeef3b, 0xc604df29, 0x2ae3504b, ++ 0xb36d87ec, 0x54fa9f81, 0xf5baafbd, 0xf01b78c2, 0x70aadd54, 0xeb42a89c, ++ 0xaf1d6687, 0x2e89e1f9, 0x178afcab, 0x4d5549f9, 0xee8096cb, 0xdfd6eaab, ++ 0xada0fd88, 0xa622caa3, 0x52ea5ec2, 0xb21f3ccc, 0x79c66fef, 0x34f1d0d6, ++ 0x3bd2def8, 0x726a708e, 0x7fdaf686, 0x5f18b964, 0x7f5337a8, 0x3aca4dd5, ++ 0xd9adc71e, 0x1a7d729f, 0x362c089c, 0xbf34ddf8, 0xd7eb7f40, 0x7cdfd9e6, ++ 0xf925997e, 0x9e5b9750, 0xa3feed27, 0xb9c9f999, 0x0cc747af, 0x8dbd0ef8, ++ 0xfeb5cd33, 0x901bfe68, 0xdcfd466b, 0x59f92598, 0xf30fcd15, 0x8c68dccc, ++ 0x316f64af, 0x1ab447d6, 0x8cbb39eb, 0x6376bcf5, 0xb1b2f3dd, 0xd5c757ee, ++ 0x18bb04e0, 0x8bb06f79, 0x762ec251, 0x18bb4985, 0x28c5d875, 0x39e31761, ++ 0x61d462ec, 0xbb0ea317, 0xc5d87518, 0xe3176128, 0x9c2aabf9, 0x25ff55aa, ++ 0x58f9c0f0, 0x7c5a1d7b, 0x99cbf79d, 0xff920979, 0x78bda45a, 0xeb0e4966, ++ 0xe90e5d79, 0x619ee9e7, 0x696e40f7, 0xa3ab3c79, 0x0d674f7c, 0x63b41c44, ++ 0xbf9b9275, 0xd2f0bf63, 0x70bf4bdf, 0x12238175, 0x55ce88fe, 0x3d435747, ++ 0xdbe51799, 0xac67f683, 0xdf00dbdd, 0x3897fa9a, 0xc2b9dd6e, 0x242ba7f5, ++ 0xa22fd8fe, 0x4094e5e5, 0x236f81ae, 0x49f1c10e, 0xd7ef5d8f, 0x88d38d0c, ++ 0xf43aba75, 0x3d63169c, 0xbe032e34, 0xabec35e6, 0xa3ffc666, 0xf024eed6, ++ 0xdb8f23fd, 0x11d47cf9, 0xe6268fd5, 0xd26f59da, 0xf9e46ef4, 0xbf2caf82, ++ 0x790cd947, 0x00d641fd, 0x03d9f386, 0x60f38619, 0xf9d965a1, 0xf777acd1, ++ 0x2629d7d4, 0xa6cc338c, 0x37df91fa, 0xf54cbc4b, 0x45ba7cb2, 0x06d6639d, ++ 0xc3fe6193, 0x7a06e103, 0x407db91a, 0xb0713c48, 0x3da8fda1, 0xc4f121a9, ++ 0xd738c611, 0x60fb15ec, 0x375acf7f, 0x9ceed0da, 0xb7383f1a, 0xcff31065, ++ 0x434be2f2, 0x3cea5be2, 0x2dd9f29d, 0x6a17a256, 0x24eecb7f, 0x24e50f96, ++ 0x8871bc5f, 0xbfce0927, 0xabfc514b, 0x526f8f99, 0x4cb16f38, 0xdea23f95, ++ 0x2c2b8f28, 0x9c44efc2, 0x7e87c680, 0x507bbd58, 0x4bd28560, 0xe14e157f, ++ 0x96fea58d, 0x83c8e88c, 0xd5e4b97d, 0x3d038edf, 0xa53798d5, 0xab760e20, ++ 0x8386d812, 0xec07c7be, 0xde98b84c, 0x8e7d9a27, 0x0777e86c, 0x9e39bec6, ++ 0xd5b27ce0, 0x2938c1ec, 0x414260d6, 0xa5dd2f64, 0xc0e19d58, 0x3366a6ff, ++ 0x67f011db, 0xd2f40799, 0xb8e6a6c7, 0xdec8f4f0, 0x30f46b75, 0x721c16cc, ++ 0x3bf5d60b, 0xa459eb07, 0x3abcb357, 0xfaccc077, 0xc544c55c, 0xbaaf7acf, ++ 0xf94ee5ce, 0x8f9eb69d, 0xcc50fb55, 0x75ce1af6, 0x2fbe1c9f, 0xab8d470f, ++ 0x98a4f61b, 0xad4dd7c1, 0xdca892db, 0x63a5f760, 0x329b153d, 0xc6813cfe, ++ 0x2ccf7ca9, 0xa4fea710, 0xc5f47265, 0xb29f3bd0, 0x7d51a67a, 0x6d6ff34d, ++ 0x2d2befd0, 0xd4ec1b01, 0xd937c78a, 0xb95e54bc, 0x5f3f137d, 0xed84bdb4, ++ 0x8ea2c5f5, 0x5a63ceed, 0x8f0aaebe, 0x46ca498a, 0x5d7bcd27, 0x2b8fd4b6, ++ 0x481e65c2, 0x2bc27991, 0x76df58f1, 0x5da79f25, 0x7386d3bc, 0xedab97e2, ++ 0xd9cbf742, 0x0d156637, 0x4daa1f84, 0xb7f7b861, 0x0e0bae3f, 0xeb31fde7, ++ 0xd9cb9bbc, 0x1db247e7, 0xeb209ef6, 0x2723f208, 0x437dfec4, 0x459fd5e6, ++ 0x527d0f5e, 0xcfc60b61, 0x905e1e02, 0x10d40bf7, 0x802f8cfd, 0x25c42d5d, ++ 0x0f231654, 0x154f6f5f, 0x7de81846, 0x23edd0ae, 0x188e6fea, 0x9ecfa86c, ++ 0x7f686696, 0x2191ecfd, 0xf7a0a1fb, 0x4badf33d, 0xbd53df7a, 0x4bbf0ee6, ++ 0x24c4bf61, 0xef2a73e3, 0xdabb3a60, 0x988d7df0, 0x740edbd9, 0x862de5be, ++ 0x361d10b3, 0xea154fd8, 0xbeb985f9, 0x2779f52e, 0x1885a73f, 0x34b0e5f6, ++ 0x9ca59fcf, 0x5f3fb2b4, 0xc5cf6ff3, 0x92fad3bf, 0xf93de193, 0x852fc885, ++ 0xd467c23f, 0x8ed83a43, 0x350f1214, 0x26a8bfaa, 0x6a8bfa5b, 0xe4361dfc, ++ 0x2dfc12ef, 0xda9204c9, 0x80fd8566, 0x3c9eded4, 0xc0efd640, 0x73c65df3, ++ 0x3cefe809, 0x97301fde, 0xbe84bf60, 0x4375a5af, 0xcfc2d41e, 0xa9aa7ec3, ++ 0xa54fd947, 0xaff6a38d, 0x39e869d1, 0xdefed0ee, 0xdf3176ce, 0x73bedcae, ++ 0xcf8260ff, 0x7cd8e2ac, 0xb6eaa3ec, 0x9c92d619, 0xe34de90b, 0x4c2ae7fb, ++ 0xf676e79c, 0xde98978d, 0x3c5856ce, 0xbbf98f32, 0x95eb52e1, 0x3a50d0fe, ++ 0x42eb445c, 0x2ed177fc, 0x645013c5, 0x3067c03b, 0x3e0433e8, 0x4dc07dc9, ++ 0xfc0f5783, 0xc62fde42, 0x5f20c63f, 0xbf7b9e41, 0xf0a12e00, 0xe459c754, ++ 0xd26fac13, 0xaf3c02bc, 0xf8c57e90, 0x8b78fdd0, 0x8dd8ed8d, 0xdf2a708a, ++ 0xe7998f0f, 0x58659fa5, 0xf77f5c9a, 0xbd03c56e, 0x0b79ce7d, 0x9fa1ef3f, ++ 0x3d979962, 0xbf719a7b, 0xb153d0f6, 0x9dd73fdc, 0xfeefe04f, 0x7df5745d, ++ 0x53c5a4f4, 0xb59df342, 0xb30743f3, 0x58e3bf55, 0x7fdbf631, 0x587b6f21, ++ 0xaf09b9cf, 0x2fc07e41, 0xa683ff03, 0xc1e0f42f, 0xd5898ae2, 0x242521e9, ++ 0xa0715d67, 0xf00921df, 0xff54fadb, 0x7da7c69f, 0x9bab7f6a, 0xf7f452d2, ++ 0x5956f891, 0xb29b1fd9, 0x12cb8e22, 0x72013387, 0xbc8564a4, 0x5df0e337, ++ 0x13c61283, 0x655e1d5d, 0x5d469f8d, 0x98d9fe1c, 0x7a8b9114, 0xd6479711, ++ 0xfbd5cd87, 0x6cca7bc9, 0xfcd697a9, 0xb5cb20e2, 0xa237a653, 0xaddf62e7, ++ 0x948d1dda, 0xef55aa9c, 0x3c92738c, 0xa2f9376f, 0x9f858f87, 0x73cb1370, ++ 0x0794dce1, 0x4fa6993f, 0x1a2aae54, 0xfd5fb904, 0x811e97cf, 0xb0adf7dc, ++ 0xfd0f4026, 0x57995dec, 0xf58cf24a, 0x490e6388, 0x46b6c7c7, 0x63b9b9f0, ++ 0x0e22f08a, 0x2fbcc4b4, 0xaf9069cf, 0xfe3073ed, 0xdc6d767b, 0x8c44b6c0, ++ 0x3e73f1eb, 0x46456fa6, 0x13fe5f4c, 0x41ba5cad, 0x34db77ea, 0x17eaaf7f, ++ 0x3a8f5e86, 0x25917af4, 0xa1d47af5, 0x5e84a3d7, 0xaa99e78f, 0x63587fff, ++ 0x52ec3e77, 0x5d9124ff, 0x3236f2c7, 0x2dfb7a1b, 0x7c07b84a, 0x33c516e7, ++ 0xeffee388, 0xab394ac6, 0x3e742fe2, 0x0e937597, 0x2bcfa3a6, 0x3e85dbce, ++ 0x88a26d7f, 0xdb27d435, 0x8bed0c93, 0xfbc36e9c, 0x1b87132b, 0xcae55fde, ++ 0xc9afd437, 0xfed0d8be, 0x4344cf5a, 0xafe327fd, 0xe19fb432, 0xcfa8619d, ++ 0xd0cf3a9a, 0x12e2bafe, 0xe7ebfbc3, 0x9fbc312e, 0xa8665be7, 0x33f158df, ++ 0xea9bfb43, 0x7bde1856, 0x7902d385, 0x8b7b0ed7, 0xec02fee0, 0xf96f2a2d, ++ 0x1ea44663, 0x9b2613af, 0xe5f7bcfa, 0xbf52e1ba, 0xde11aff9, 0xe503e1e2, ++ 0xe1d011f9, 0x487cf550, 0xbf1770d9, 0x4541164f, 0x491dbbda, 0x76d09ba0, ++ 0x4427efa1, 0x45ce78bc, 0xf8737c38, 0xe216d9fe, 0x7a2e1307, 0xd51a7471, ++ 0xbe889f13, 0xbe97eb8e, 0xd52a74f8, 0xcb144753, 0xcf17a8fa, 0x27e6fde1, ++ 0x967d65e2, 0xf3c35560, 0x7ed9cec4, 0x2b84f79a, 0xa479d752, 0xfbcfa4bf, ++ 0x7012b487, 0xe024de40, 0xf4483280, 0xa245f289, 0x132f944f, 0x855b967d, ++ 0x89f44fd8, 0x9dd900f2, 0xd91afe78, 0x20df289d, 0x9be513bb, 0xeca27764, ++ 0xe513bb20, 0xb9730ddb, 0xc7c1b77c, 0x50dfbddf, 0x86c1e5c1, 0x97fe7e3a, ++ 0xff2e7a86, 0xe7e7e0da, 0xed15c30d, 0x61fb3dbc, 0x2d54f8b4, 0xff8882e2, ++ 0xd49eb1ed, 0xaf156bc7, 0x3c5aa394, 0x744eb1b1, 0x769f6046, 0xb53f625a, ++ 0xfb09c6f7, 0xf116abe7, 0x7aff4ea9, 0x7bbde1c7, 0x8637fb38, 0xd4671138, ++ 0xb3121f9e, 0x9e101686, 0x9afb775e, 0x82bafef1, 0xc43155b2, 0xbaf8ae3f, ++ 0x797a0ace, 0x79f7d4cf, 0x4e9532e3, 0xdef08cd6, 0x5cb93a0f, 0x72e727bd, ++ 0xbbdbccbb, 0x08d9d2dc, 0xa5f8d47e, 0x66ef2170, 0x4fcc945f, 0xc2cbbc6f, ++ 0x17ca7a79, 0xc597eb82, 0x7e37ae0b, 0x7e79c1d9, 0x893d3b97, 0xbad45f2c, ++ 0x13d37f96, 0x2e9fc76f, 0x7f8b46af, 0x8535796b, 0x864e745f, 0xa459701e, ++ 0x121615cd, 0x7b9c47af, 0xdafbd45f, 0x1dbef8bc, 0xe5beae2d, 0xfdc4114b, ++ 0xfcfc5a65, 0x1b877b72, 0x6ecb837e, 0x79f47bb5, 0x5c9c5a43, 0x0cc3a2f9, ++ 0x05e5a339, 0xf368e369, 0x7f50b28e, 0x3f79bd05, 0xf2db3b97, 0x58d10f91, ++ 0x0dfdc913, 0x02b6e7a2, 0xf335e76e, 0xc8f96d77, 0x3aacb8d7, 0xde9423d2, ++ 0x7520fcf8, 0xb91651dd, 0x7c2fc2ce, 0x99709f9c, 0x7e809f9a, 0xdf3df2ec, ++ 0x7c5976cb, 0xf582c930, 0xf03cd9d7, 0x48ac3e73, 0x2f96b07f, 0xba11f680, ++ 0xa2798c7d, 0x68aff4df, 0xbddbd0be, 0x2cef865e, 0xe14fa4a7, 0xdcaaeb52, ++ 0x72270715, 0x8bd6acdd, 0x211f9cc3, 0xea985e0e, 0x783a083b, 0xc8cb495b, ++ 0x6d20bb67, 0x8cfdf620, 0xfadd7b90, 0xfe8f9fa0, 0x2bc7e86f, 0xb0443ef1, ++ 0x8e942d9f, 0xf468fc34, 0x3fbde1a4, 0x40e8d2ba, 0x78c5ef97, 0x52dfc9ef, ++ 0xb7a50bfb, 0xa34ce8fe, 0x92edcbaf, 0xe467800e, 0xa57468e5, 0xe7c6d17c, ++ 0xb6ab2f1b, 0xe8d3fcb3, 0x2e2e942a, 0xa7492ba4, 0xb9d9b78d, 0xaae90bbf, ++ 0x97001e97, 0x1d574f1f, 0x7fe3c866, 0xee6e9e95, 0xce705316, 0x6bbce4bb, ++ 0x53afca3f, 0x77c0657d, 0x05389899, 0xe69c2624, 0x42bdf85c, 0xa8d359db, ++ 0xdb0bd8dd, 0xe85fd285, 0xa1693977, 0xe8e5a7fd, 0xcaac9bbf, 0xa6efd0ca, ++ 0x68ddf05d, 0xdd784fce, 0x7893e5a1, 0x727e87ae, 0x779565c0, 0x646f092a, ++ 0xf953fa3e, 0xc75101f8, 0x59d49772, 0x5429c63f, 0xce726a49, 0x0a07b662, ++ 0xeb8efb23, 0x3f7ead5f, 0x26e2ebe5, 0xbc4a63cc, 0x5abedf51, 0x14afd7d5, ++ 0xe87fdccd, 0x73abf939, 0x3e3d64ae, 0x55fc9cf4, 0xdc3d5423, 0xf3e0dc2d, ++ 0xe723c285, 0x506fdea7, 0x64efeea8, 0x5cd25e95, 0x00613166, 0x2cfa1fce, ++ 0xe32f2e10, 0x8c3c837e, 0x55fae7eb, 0x35e5c022, 0x5cfdc822, 0xf508824b, ++ 0xe4aa109f, 0xfcf206bd, 0xf7d9ad66, 0xdaa9e837, 0x0e65cdb9, 0x08238ddf, ++ 0x4c452f8f, 0x27fb8f9f, 0x9c9e8f26, 0x2c5eef8e, 0xf77eb174, 0xf58d3da2, ++ 0xeb47ec4d, 0xf0fe5e80, 0xf4e7c92a, 0x108e790c, 0xa611ce25, 0x03fd1c93, ++ 0xafd46fc9, 0xf0215ece, 0x319714dd, 0xfefb48bf, 0x6164e71a, 0x3e5feb89, ++ 0x77b7935e, 0x5e2ff208, 0x442acd8f, 0xd8f5e0fc, 0xdeb10a8b, 0x990763d7, ++ 0xe3661964, 0xf4d9f732, 0x8d61f4be, 0x9bc77bde, 0x07f5e3c2, 0xa1ae0d67, ++ 0xfce0d4f0, 0xbabae023, 0x0d96b82f, 0x6b4fd217, 0x7e16ba7f, 0xc9089ab4, ++ 0x46cfbd57, 0x975bc409, 0x36f796ef, 0x2229867c, 0xe12edd9f, 0x52feb0b4, ++ 0xf1cd1961, 0xbce03f2c, 0x7e62fea8, 0x13afea1e, 0xdc344eef, 0xf76c562f, ++ 0xe341186d, 0x66082c9d, 0x8e27c692, 0x73e46c6e, 0x9876a7d8, 0xaa97b03d, ++ 0x1e75aecd, 0x375f7df8, 0xf8a51e73, 0xc414a5fa, 0xbe96c54d, 0xedabbbf3, ++ 0x5d9a8e12, 0x98ad3038, 0x1fb6a5f7, 0x5cae7a85, 0x84869fd3, 0xed68fcc9, ++ 0xfa7f737c, 0xc970b8d4, 0x498486b7, 0x6fe1ab7e, 0xeb954da3, 0xe238cfd4, ++ 0x0abfc993, 0xdea9fb67, 0x7c036de9, 0xfb06a109, 0x9c8ff343, 0xbc70978d, ++ 0x083e645c, 0x01e164ff, 0xfbd008ab, 0x78f8d8b3, 0xa4e3289f, 0x339c0f67, ++ 0x4517af83, 0x81cf7c29, 0x2c27ee76, 0x3a5c24d1, 0x8570e07e, 0x8d01ee1b, ++ 0xa8601ec8, 0x1b067947, 0x4f8cc7da, 0xf58fbc35, 0x8fbc308e, 0xa8605a9b, ++ 0xc4be2c0f, 0xdcd07ed0, 0x927a8649, 0xfb436aef, 0x86998ae4, 0x92afc6ba, ++ 0xb43123e5, 0xf7c306ee, 0x0d4beac3, 0x4afedded, 0xee337bc3, 0xf51f0435, ++ 0x13b23b7b, 0xfca2fd70, 0x3cbb5b4b, 0x9353fee4, 0x1deee930, 0x3cb44df9, ++ 0x723532d7, 0x923fdf11, 0xe373fcd1, 0x2cd3cd3c, 0xe95e54b1, 0xa2bff232, ++ 0x727d6344, 0x71053ee4, 0x234ec9c3, 0xb3ae4e1f, 0x23ddea18, 0xb4847de4, ++ 0x7fd8f327, 0xf7f87df1, 0x3fe0308d, 0x0f444e14, 0x59e35f7c, 0xcc7edf92, ++ 0xbe32d5eb, 0x0ef104d7, 0xef103afd, 0xf101c3d0, 0xf11d7d0e, 0xc47b7d0e, ++ 0x11eff43b, 0x1fbfd0ef, 0xff88c07d, 0xfc461db1, 0x88d0745f, 0xfb2e8d7f, ++ 0x9dc5d3c3, 0x3e10fa46, 0x077ca7c5, 0x663d2e9e, 0xfc509fa4, 0x54ea415c, ++ 0xa1f03c6c, 0x1fae8278, 0x91ccaf8f, 0x7e117c46, 0xece5bf38, 0x9f892890, ++ 0x2bce48e0, 0x16603a29, 0xe1e49fb8, 0x6a7e7590, 0xd24679f1, 0xab83ff3e, ++ 0xebfc1120, 0xade3210a, 0x9e4daa53, 0x105b7520, 0x8393ffd2, 0x7ed1637d, ++ 0x14b9dc6e, 0x5ba3e81b, 0xac567fde, 0xff2d5df2, 0xc8493fd4, 0x373f3373, ++ 0x7cff9007, 0x80acd4c8, 0xed1e7f3f, 0x4af90cbb, 0xf1d4e737, 0xf14512fa, ++ 0x37c845ce, 0x29617ffa, 0x26182fa8, 0x391499ef, 0x437e7c9d, 0x920b8be3, ++ 0xd1523e65, 0xed4e3548, 0x53497991, 0x533f4a47, 0xf9c9c794, 0xf23925d2, ++ 0x7f990a7c, 0x01720b29, 0x591c378f, 0x898b4780, 0xb4ec4def, 0xdcf862ba, ++ 0x8166abd0, 0x5bf41c38, 0x554393e8, 0x03f1ae7d, 0xcff31dbb, 0x720c20da, ++ 0x6ec07875, 0xb91dd3c8, 0xe7a869dd, 0xda1a25b6, 0x32e3da8f, 0x660fcfbc, ++ 0x3e8fde1b, 0xc7d431e0, 0xb4378c76, 0xd7a0e8bf, 0x73b8bf50, 0xa5fda1aa, ++ 0xf50d8ac7, 0x10fdd164, 0x914c3be0, 0xc8ff077e, 0xbb6f6954, 0xc171dc64, ++ 0xee79589a, 0x6847f554, 0xbf96bbfa, 0x38e953ed, 0x21b02ed4, 0xb3f04fc0, ++ 0x5cb0b5ad, 0x7daff2d0, 0x9ad6f921, 0xfe73d09d, 0xbfcc6fc3, 0x7baef2d6, ++ 0x4ed508ec, 0x9ef1f4d0, 0x6326ebbc, 0xb082f5de, 0xfde7efbe, 0xd0f78aa5, ++ 0x0af36bf9, 0xf82dff1d, 0xf6f6c6dd, 0xf7ded5bb, 0x2a0da479, 0x5e943d7d, ++ 0xfa741ebc, 0x7073d588, 0x1f5ffbb1, 0xabea31a7, 0xdde71f24, 0x37cff9c9, ++ 0x919e6e99, 0xcd85f7c3, 0xdc6e9dfd, 0x36f1d4c7, 0xdd74aae4, 0x620b38cf, ++ 0xedf1f8d4, 0x7edd79ea, 0x89b44dc6, 0x3701e826, 0x07bb6bad, 0x6df31ba9, ++ 0x5ebdeacd, 0x3ef02b01, 0x57e9126d, 0xb637c4f9, 0x9244b6d6, 0xbd48f3fe, ++ 0x3b4afd85, 0x3ae0fc9e, 0xf9ef7a7f, 0xc7646192, 0xc3a00e80, 0xcec9fec0, ++ 0x6fff7335, 0xbcfb948e, 0xfb480e57, 0xf390acf3, 0xe36f5b3b, 0x741f7238, ++ 0xada6f4c5, 0x4e75dfe7, 0x50cfa340, 0xeb7668f8, 0x86e73d5b, 0x0f4b5ca4, ++ 0x9ced7ba1, 0xb5996b86, 0x9f247378, 0x7c8a98f7, 0x61bf1eb3, 0x39774aae, ++ 0x07680e12, 0xbb5fd37e, 0x0c4e7322, 0x8567edfc, 0x07d9c62b, 0xbfe569bd, ++ 0xc304dcf1, 0x5f73bfbd, 0xfeffedfd, 0xee857dce, 0x10fe50fb, 0xfbfe770a, ++ 0x34c0e701, 0xc3fc68bc, 0x81e73a2a, 0x4dd2058f, 0x135fa71c, 0x39afdc65, ++ 0xefbe1239, 0xc57e948e, 0xc133972e, 0xcba5ee64, 0x399bf785, 0x7eac777e, ++ 0x4bf3df2e, 0x5f323cf2, 0xbdcbceb7, 0x509709c5, 0xab16d2bb, 0xbac2e4d8, ++ 0x976e582a, 0xd4ed43f8, 0xcb5fd66e, 0x5fce29d7, 0x6fbc2fbb, 0x3877d35a, ++ 0xb9c2e6fe, 0x3f7a9f04, 0x62ddb1bd, 0x8d0d8ed5, 0xa8e4a52f, 0x3c23d5f2, ++ 0xf9a96fac, 0x9b6a1503, 0xa409fa1e, 0x1c7ea8c5, 0x72548fde, 0x0f0699fe, ++ 0xa33de217, 0xb704eb7b, 0xdfc86cf0, 0xf99f4b26, 0x2edc1a81, 0xf99073cc, ++ 0x0719e21d, 0x9e5a2bdb, 0x39e449c3, 0x3c5abf00, 0xd27f6d49, 0xe466166f, ++ 0xe30aec5b, 0xd329fcf8, 0x2570731b, 0xe9fc4f56, 0x8895b882, 0xd9c67e46, ++ 0xdaf79956, 0x75f07edf, 0x34790d9a, 0xb15fbc17, 0xa92fef9b, 0xa9c64a7e, ++ 0x297a9faa, 0x27275d21, 0x4c2c730a, 0xdf26ed4f, 0x7b033935, 0xff2a46f3, ++ 0x7287903b, 0x0a1fea9a, 0x5f0f4f5d, 0xf8c8a09b, 0xf98fad2f, 0x7e7954da, ++ 0xc0a2f89c, 0x15f2d27e, 0x3c608866, 0xe41e2d4a, 0xe3317b5b, 0x95078b41, ++ 0x75e62f04, 0xd8b8d75c, 0x3b1dab8a, 0x28a3ba1f, 0x271bd5dc, 0xf32a1cea, ++ 0x178bfa8f, 0xcf9f3acd, 0x7f3ecdfd, 0x9953f729, 0x567a96e3, 0xa0cb3dd3, ++ 0x2ed88e6f, 0xa74380ac, 0xfafbefb5, 0x93eea2ff, 0x8d5f83bf, 0xad35e5d5, ++ 0x2f6f9850, 0xf3204e87, 0x6b6f989c, 0x6acd73f5, 0x6fd648bd, 0x9deb2559, ++ 0xdb56fdea, 0xd604bf54, 0x81eb1289, 0xfaaadcdd, 0x940eb02d, 0x839e0758, ++ 0x7e0ea15f, 0x15f83a85, 0x2857e0ea, 0xbcf0afc1, 0xc0a71454, 0x56b88a7f, ++ 0x209f6ea1, 0xd3a855ae, 0xd2d71077, 0xd2d711d7, 0x4b5c47b7, 0x2d711eff, ++ 0xb5c47bfd, 0xb5c475f4, 0xd711edf4, 0xd711d7d2, 0x5c47b7d2, 0x5c475f4b, ++ 0x711edf4b, 0xc47bfd2d, 0x11eff4b5, 0x11d7d2d7, 0x47b7d2d7, 0xfeff4b5c, ++ 0x10c57ae6, 0xbd59baf7, 0x436ca0e7, 0x6e47d31c, 0x3963f16a, 0x45bfdf84, ++ 0x6b36f3fc, 0xbedcf02a, 0xbcbb7404, 0xf123dc26, 0xe2553cdc, 0x9e2424dd, ++ 0x9e31e7bb, 0x7ac9b0ef, 0x0e87cc91, 0x8fc41fa5, 0x7e32ad0a, 0x23f11284, ++ 0xa11f8894, 0x30a8fc44, 0x508fc643, 0xe7847e22, 0x44a11f88, 0xe22508fc, ++ 0x3f112847, 0x11f88942, 0xf08fc44a, 0x2847e21d, 0x73c23f11, 0x22508fc4, ++ 0x87e7847e, 0x23881e68, 0x7e82f369, 0x1fb06e9e, 0xf60d0e89, 0x8750d3a3, ++ 0x0f6fae7e, 0x1eff5cfd, 0x3dfeb9fa, 0x1d7d73f4, 0x3dbeb9fa, 0xfd7d73f4, ++ 0xef1748d8, 0xfae9e833, 0xeba7a0ef, 0xfecdb9eb, 0xba7be057, 0x97e9e376, ++ 0x29467651, 0xfa4e288f, 0x8e6ea73e, 0x4eb1f485, 0xeb129287, 0xe2b7f921, ++ 0x548539b6, 0x84f9a9f7, 0x04dba279, 0x9f1c737c, 0x0a0be6f0, 0xfdce7fce, ++ 0xd7bf1247, 0x47fccae2, 0x25dfcf78, 0x54cfdf58, 0xdf6aa7cf, 0xccd3847b, ++ 0xfb6aaff9, 0xeddf7ade, 0xdad7c742, 0xcdd4bf31, 0x3e64e483, 0xeff23bf2, ++ 0x5e402c88, 0x229336ff, 0xca575ef3, 0xba50e3bc, 0xe32b921a, 0x3b4cdb1f, ++ 0x5e470c5f, 0xf9c28948, 0x711699a7, 0x38005ac0, 0x5f4015d5, 0xaac6e4b0, ++ 0x04bbaaeb, 0xbcda4f79, 0xf1213f35, 0x37773e09, 0xcad85ba1, 0xbecb9c69, ++ 0x6efc3610, 0xd49b34c1, 0xec1df017, 0xc57e91c4, 0xdf4759bb, 0xedbeaad1, ++ 0xa4bb2ff3, 0x6c8f9e9c, 0xe704bbad, 0xcb85a6f9, 0x347b1eef, 0xbd38e19a, ++ 0xfb8cd949, 0x0ab42656, 0x0ee7ce2f, 0x91baf552, 0x395b4ead, 0x73e4eb8f, ++ 0x25bf5a80, 0xdcf8531b, 0x2ce88962, 0x8c51bf84, 0x71fef851, 0xbeb46e0d, ++ 0x4cbeb197, 0xf7f02ada, 0x40f3e8fe, 0x90fe06a4, 0x8d9740f3, 0x1e422d89, ++ 0xf797689f, 0xa63b5e39, 0x9a40d564, 0xef202f97, 0x8becbc73, 0xbeb857ba, ++ 0xc8e7de45, 0xe78e33e4, 0xcb30f2c7, 0x237df0af, 0x4c9bfdd3, 0x4b9c2ef1, ++ 0x404d615e, 0x81e156fb, 0x6734803a, 0xd6d5ab9c, 0x4c3a2395, 0x22f4050e, ++ 0xd1d38a5e, 0xd98e711f, 0x8f7c97a0, 0x9b35ef95, 0xc15a7161, 0x8df5426f, ++ 0xd217fcd0, 0x7997ae3f, 0xe40b5696, 0x951fa6b1, 0xcf5ce538, 0xff595935, ++ 0xdeadd928, 0x6fa21f67, 0xa4317968, 0x90827877, 0x61aebbe3, 0xb2f5543f, ++ 0xe4ff38f7, 0x0db03bb8, 0x4f1e71f7, 0xbc6739dd, 0xc28b7a1b, 0x86f494fc, ++ 0x7103b999, 0x3e15f61e, 0x7fe9d1d7, 0x738df59a, 0xcb47f74d, 0xfe325cf3, ++ 0x49c2ae51, 0x542d07f3, 0xe6ae51f1, 0x906e1d41, 0xdc92e6f7, 0x68457be5, ++ 0x8457acbe, 0x1e9a87ea, 0x23b3dda9, 0xf87df384, 0x7d682a61, 0x78bb0338, ++ 0x44eac95d, 0x58fea171, 0x4b95eaa5, 0xf79cac9a, 0xb3dea154, 0x25fbfa15, ++ 0x53be6a55, 0xfc90f6d5, 0xfd10dca6, 0x50efbb53, 0xc7f2536d, 0xfd63ae97, ++ 0x71cacea7, 0xa42bf9c5, 0x8a76243e, 0xcc69ce00, 0x84d9315f, 0xefe632fb, ++ 0x3e947af6, 0xaa4fe7e8, 0xd3ad345e, 0x719d70c1, 0xc9f9823e, 0x5cc9f3cc, ++ 0x893e739f, 0xcbcfebcb, 0xf099d0bc, 0x3bbe10fd, 0xfeb9e48b, 0xe87d5477, ++ 0x0289e43a, 0x4c41fe8f, 0x9e8967cf, 0xca9e4431, 0x957846a7, 0x4e6ea097, ++ 0x2156fab3, 0x26da750f, 0xb5e5fac1, 0xffa89bd0, 0xe2a3d0b9, 0x45dc1fb0, ++ 0x553c9f9c, 0xd73b73e1, 0xd2a6598e, 0xc107ed3f, 0x19ef83fc, 0x08ce15f1, ++ 0xae68bf20, 0x7809a76f, 0xcf81f6d7, 0x57f7c5df, 0x6c57eb5e, 0xa7cfd7b8, ++ 0x9d1acbda, 0x0587ee87, 0x2b3faa11, 0x7aabfa52, 0x2c9859fc, 0x77f1ff2e, ++ 0xeebe41cc, 0x071cf802, 0xb04084ab, 0xef91ca8f, 0x31d53fb7, 0xce7489a7, ++ 0x98e7eb1f, 0x73c9326f, 0x71efa45b, 0x28e8bdfe, 0xb2fd841a, 0xfe40294e, ++ 0x869f36bf, 0xcede9351, 0xa5c5d9d3, 0xced2feea, 0x2bbf2e0f, 0x9d77d063, ++ 0x38232d97, 0x882d9f63, 0x214dbce9, 0x0ae474cc, 0xee22616f, 0x25da1703, ++ 0x39e44147, 0xffd6a0de, 0xef37d4f9, 0xf8648daf, 0xdc8dfd70, 0x5e41cdbf, ++ 0x87e68fcb, 0xfe8b15f3, 0xff7096f7, 0xc1f32e7f, 0x6bc029ce, 0xdf374e44, ++ 0x1f0a109b, 0xcff24fcd, 0x87bc975c, 0x525fc421, 0x8be52396, 0x6e52b8b0, ++ 0x8b8bf8e4, 0xbada8afd, 0xe78d5b0f, 0x2bf2b55b, 0xbbfc4e55, 0x603c7dce, ++ 0xfc0cf792, 0xf9d814da, 0x8de9d12c, 0x72c77d03, 0x46bffe69, 0xdfcf3b1e, ++ 0xeed3ebc7, 0x53e1e8eb, 0x1a1cfdea, 0x1fd6951d, 0xed4a6dd9, 0xb5f2a7a5, ++ 0x35b43f9f, 0xd801f71e, 0x7c9077f8, 0xfe79156b, 0x7b3a1fbf, 0xf79c32b4, ++ 0xb73fa3cb, 0x6f9dff31, 0xeec578eb, 0x87e785ee, 0x9569fff5, 0x819832fc, ++ 0xa86ed6fb, 0xc57df073, 0xbf8aa30d, 0x72227e01, 0xb7978c3c, 0x8fb50631, ++ 0x7929f189, 0x74076103, 0x5f844fec, 0xf23ff6f8, 0xdb4bc03d, 0x61ff7cdd, ++ 0xd5fc9ec9, 0x61a597b8, 0x7a06cf94, 0xda74892d, 0x36d467a0, 0x5ddcb2c5, ++ 0xb73d4830, 0xce39ba2a, 0x2523e1a6, 0x1dbbda4f, 0x6738e4a3, 0x00897b54, ++ 0x68619d64, 0xb15fb7d7, 0x10889ee7, 0x3faf563f, 0x6bdf0b65, 0xf2178b6a, ++ 0x7810e0de, 0x2b61cfc1, 0x84a3f5e8, 0xf67a3bfa, 0xdfefadab, 0x9e49fc37, ++ 0x5fbbc862, 0xe6af63d8, 0xbd04194c, 0x84e2bd7e, 0xd23cbb7f, 0x54c5fd75, ++ 0x45603f2f, 0x3698aa46, 0x45ef25c0, 0x8bde4bb9, 0x3e6b7a52, 0xc0f9adf3, ++ 0x6fce0149, 0xb6fbcc5c, 0xe8e5403c, 0x8df7f7fe, 0xba1a5feb, 0x7a0aeb17, ++ 0xb97dbcf9, 0xdfd36bd3, 0xacd65e23, 0xd04bee18, 0x49e457ea, 0x327ce1bf, ++ 0x9bbf0023, 0x70db756e, 0x527cd127, 0xf8ff907f, 0x21973c93, 0x38ed4c8e, ++ 0xaa5a63bf, 0xabef2fd8, 0xe5bb79a2, 0xfeba0578, 0xf78d9b4b, 0xd67b503e, ++ 0x8bcaaedb, 0x9c4afee2, 0x4a376eb4, 0xe093cf27, 0xbeea70c0, 0xf173fa87, ++ 0xb2f70c38, 0xc1eac060, 0x4257907c, 0x019c1bf5, 0x6d29c62b, 0xf8aff792, ++ 0x7c71c9d6, 0xb96d636b, 0x4e2cebd0, 0xbebd50db, 0x1bef24d7, 0x6efeaf9e, ++ 0xf597cd03, 0x138272e1, 0x3ce1a9ce, 0x285a6420, 0xf9d44abc, 0x1ac73797, ++ 0xf5e6c7f5, 0x5e67e056, 0xdc42f73f, 0x6971d2a9, 0xc73e44d3, 0xf2f16e5f, ++ 0x0a9f0fb9, 0x39964fef, 0x62fc46ee, 0x5683cb5e, 0xf26bd537, 0x277d9ea4, ++ 0x70103ce0, 0x7df0660a, 0x9c1ccb4b, 0xd9cf3d87, 0x81edebcc, 0x1f04fdf7, ++ 0x62ce27e8, 0x89d13786, 0xe58cf91f, 0xf6fc462d, 0xfb8a27ce, 0xe1296f2d, ++ 0xe2c8b7fd, 0xf3f539b3, 0x032fb0d8, 0x68f339f9, 0x293ee3df, 0x79f1f4e1, ++ 0xbfef4fd2, 0x0d1f7f9e, 0x317ce4f3, 0xee0a6b8f, 0x61ba224f, 0x47e8d6ba, ++ 0x8dae873b, 0xfd2792d7, 0xbaea2d3a, 0x5a7dd5fe, 0xf384aebe, 0x8512ca7c, ++ 0x7c33f707, 0xf6d53edf, 0xe75fb6a7, 0xb2c97ea9, 0x0ef83375, 0x90df8d22, ++ 0x5dfbaefc, 0x5b79f01f, 0xa83727e5, 0xbe7824f8, 0xbb7e742c, 0xcf5f7576, ++ 0x7bee354f, 0x1f7e87f4, 0x7f3df157, 0xe7033052, 0xdaf6b554, 0xc807f3b8, ++ 0xa0ff40ef, 0xf1d5c7b3, 0xb7397ed0, 0x46f81937, 0x68df0f59, 0xbe00955d, ++ 0x2efe53b1, 0xa47bf2df, 0x29fcb75e, 0xc4fd5e79, 0x9cdf67f2, 0x3f8eed43, ++ 0xfe8169b0, 0x507948fc, 0xa48589f2, 0x2c6f814f, 0x90fee552, 0x3c9edf4c, ++ 0xbf2e3edd, 0xec4ca9ef, 0xf2da1b8b, 0x6c9dc53f, 0x47be6eb4, 0x3d4fafe9, ++ 0xae25def7, 0xadaaf95e, 0x5bed74a3, 0x3d4892d6, 0xefbae4dc, 0xf3e52ece, ++ 0xec17c0e3, 0x4526b2b0, 0x6dea41c6, 0xf86a7fac, 0x1283a50e, 0x9165bfda, ++ 0xd457de17, 0xe1a4de9f, 0x86bfc359, 0x85fb9eef, 0x786b7c54, 0xd193eed2, ++ 0xef36aae4, 0xdf79d50f, 0x21efd2a0, 0x50dddf75, 0xe22db6e1, 0xe1b6eefd, ++ 0xa9e72877, 0x1b95e7ef, 0xc9e0f79f, 0x57dfc3d9, 0x5ce05f63, 0x7674f015, ++ 0x23fa559d, 0x53c02f5b, 0x36bee40a, 0xdfaac58f, 0x3feaa171, 0xc1eaa45c, ++ 0x7a53a784, 0x547e2d3c, 0xc76ca9e2, 0x3dc23f1f, 0x5553f367, 0xbc8f763e, ++ 0x6db4a0e7, 0xde6be327, 0x3756f5da, 0xcf26fbb5, 0xa44fb86d, 0x09df2eac, ++ 0x6b0df9bf, 0xffb15937, 0x79f951bf, 0x57cfbd28, 0xb835a2f3, 0x3a28fe42, ++ 0x07b5a7b9, 0xe349dbdf, 0x11ccbadc, 0xbafdffad, 0xae9251cc, 0x0762eacb, ++ 0xbab2bc60, 0xcf617b92, 0x743f7c68, 0xc8711ddf, 0xfd4a50fd, 0x991e5f61, ++ 0xe073e1e8, 0x25f5c388, 0x928e875f, 0x5637eafb, 0x72667f79, 0x80e3db44, ++ 0x70d2f243, 0xe9d7e20f, 0x4f7c9de9, 0xf318e82d, 0xfde499b6, 0x9dd5e99b, ++ 0xe91e639f, 0xa0d7e642, 0x885dfdc4, 0x7d502477, 0x4f9e49b3, 0x72cb354b, ++ 0x0f4928f2, 0xf7883ef4, 0xef93be22, 0x5be50bf3, 0x1a15e9fd, 0x84fd6a7d, ++ 0xd6fea9f2, 0x4928e977, 0xbeb7df97, 0x6fd56e23, 0xc149ed92, 0x7e0bf13d, ++ 0x85f7c595, 0x6d3adf7e, 0x3d8fbdea, 0xbf930deb, 0x7ac171c3, 0xd41da5d3, ++ 0x8a5b7aff, 0xef58fa12, 0x7565f105, 0xffb9689f, 0x6692713d, 0xa2392719, ++ 0xefa2dc90, 0x70732c8e, 0x2eb69b3e, 0x43ff4fcd, 0x3cdc6bcf, 0xbfea806a, ++ 0x3e828ce8, 0x3dfd5f39, 0x75941113, 0x7ba19f3c, 0xed7bc9ae, 0x3f8d3c3e, ++ 0xcaa75c7f, 0x0f79d143, 0x4fa8b3f6, 0x0e587be3, 0xc2891f35, 0x264733fd, ++ 0xdf69f9ca, 0x6efeaadd, 0xc6155889, 0x37a4fdf9, 0x693f86ad, 0xfd963fa1, ++ 0x8fd53734, 0xf7f714fe, 0x2c94d4dd, 0x7aa9a5cf, 0xff9522fe, 0xb25adc45, ++ 0xdfb422fa, 0x61dfe6e0, 0x6c59185b, 0xa22e1f83, 0x952d8665, 0x07695ef5, ++ 0x5bab7168, 0xe7cc5115, 0xc07bd4e9, 0xa5f699a6, 0xde2cde43, 0x69fff520, ++ 0xf116b126, 0xc58d61cd, 0x1fc09253, 0xfde4521e, 0xf78d1b1e, 0x2ccb6d82, ++ 0xc028d9fe, 0xbd7ee42b, 0x5e6dad5b, 0xf4829dd8, 0xf307ac0b, 0xa1fe5c01, ++ 0x2d43c7f2, 0xbe4f7c5d, 0x7b1fcf06, 0x0ba34a1e, 0x10b67e2d, 0xa0d19ffe, ++ 0xff7cf98f, 0x271ab954, 0x9932dd5b, 0xcd370beb, 0x8d4f73e2, 0x64764c68, ++ 0x07a2faf9, 0xc738b9fc, 0x5e51e12c, 0xf43a7933, 0x61cd8aa2, 0x526bb0b1, ++ 0xbd14feac, 0x69be5a1e, 0x3a839f0d, 0xe7c1c9b6, 0x339d0aa0, 0xb3d7910a, ++ 0x673ca368, 0x4c7bb5a8, 0x35957fdd, 0x99e70d93, 0xb89f5216, 0xb6cbf4c7, ++ 0xd397ce08, 0xb06d29ce, 0x1a8f36fb, 0x5d2bcf2b, 0x94e792ec, 0xabbdb892, ++ 0x56bd3f4f, 0xcf20da7e, 0x5dcee8bd, 0xdf479f4d, 0x1d3cd757, 0xeeaa7e8d, ++ 0xd39c677f, 0x1dadfec4, 0xdce7bfe8, 0xee7906d5, 0x7dfde16a, 0xeed27f9f, ++ 0xa3d8a8b5, 0x378ce218, 0x0f586205, 0x0d8505f5, 0x539f6df1, 0xcc7b9eb0, ++ 0xd721ea2c, 0x7b44bd35, 0xecf9541e, 0xfe6698b1, 0xdb25f11d, 0xe37be41e, ++ 0xf5928b3e, 0x7faedbf9, 0xb7c87c0d, 0xdfea4c25, 0x6dfac116, 0xcbea5f99, ++ 0xdc3a79da, 0xfc3b0017, 0xf21151b5, 0x5cf5287e, 0xed2f3696, 0x2ccfe11e, ++ 0x9c219ef2, 0x7f3d02b7, 0x042e0968, 0x7d243f3e, 0xc78f7114, 0x61f4fe54, ++ 0x1f7f99b3, 0x011b4fc7, 0xcd87c57a, 0x9e21474f, 0x4561e9a8, 0xeff2bfe6, ++ 0x2ddf2f4d, 0x3ee343cf, 0x555bbe7e, 0x3ad497f5, 0xdf2dbd25, 0xfb829d6b, ++ 0xe2af49a0, 0xa096d527, 0x557c2fad, 0x4f537aaa, 0xb64ed77d, 0xa55baacb, ++ 0xd6dd505e, 0xa6817ac5, 0x2be76867, 0x58bb5aab, 0xabbed04f, 0x52e125dd, ++ 0x2f3e4bb3, 0xe93bb9c1, 0xe92af16f, 0xae1597b0, 0xfdfde447, 0x7d1615fa, ++ 0x57ebabfd, 0xaa74a3a4, 0xd66e90fe, 0x7eceefcb, 0x9a99ed9b, 0xaa5fb526, ++ 0x9de3755b, 0x281ee6c1, 0xe245a79f, 0x7ec1977b, 0xed25d9ab, 0xf84d60a1, ++ 0xadbbce5a, 0xeff0b48d, 0xb244d4e0, 0x6758df3c, 0xbe3e46ca, 0x7d670957, ++ 0x17cd5dae, 0xbef5581b, 0x24827e03, 0xee12fdd1, 0xda3cfe2f, 0x38d0f267, ++ 0x4ca61fff, 0x8000e1a2, 0x00008000, 0x00088b1f, 0x00000000, 0x7dedff00, ++ 0xd554780b, 0xb3dae8b9, 0x926619e7, 0x4c90c93d, 0x08498120, 0x9dc46c10, ++ 0xb00d0417, 0x18081303, 0x42c144ea, 0x440130c5, 0x57c05790, 0xc193c6f4, ++ 0x188208f0, 0xdb151104, 0xe5a2d101, 0x1e8a84f4, 0x54076c50, 0x813d568a, ++ 0x55fb6a5a, 0x5b515a88, 0x1ed62124, 0xfef5b53d, 0xced6bfff, 0x0f0c9ecc, ++ 0xdbdef5ad, 0xaed7e2ef, 0x8f5ec7ac, 0xebfffdff, 0x242c1931, 0xfeb19931, ++ 0x41b1222c, 0xf0be758c, 0x80b07141, 0x3b0331b1, 0x630a613e, 0xe9a61596, ++ 0x258c51fe, 0xcbe990a9, 0x28e82b18, 0x7f0a5c0e, 0x02b3621e, 0xb51ec64e, ++ 0x114716b0, 0xec039b94, 0x603f286a, 0x8c3dbf82, 0x2927fe85, 0x7f04b8fc, ++ 0xa58c69e7, 0xc1dcb633, 0xe41f3ff8, 0x6dd63047, 0xb608d9e7, 0x9ff68129, ++ 0xe78fc29b, 0xe452f7c0, 0x97cf9c31, 0x632c6ff8, 0x50685413, 0xe6c058ca, ++ 0x1852916c, 0x64b24abb, 0x910e07ff, 0xc2a7ec1b, 0xf2b9027c, 0xef3085a5, ++ 0x528323ee, 0x169dde70, 0x3eb58ede, 0xdc61d9a8, 0x6cd86271, 0x54b10b13, ++ 0xbcfdacc6, 0x58cc964e, 0x387923b3, 0xa6927683, 0xff9806b1, 0xe68705dd, ++ 0x75d7bce0, 0xe60d99d9, 0xe92bae31, 0x65da091d, 0xb132abf7, 0x407ed8e1, ++ 0x7c93bf18, 0xda133666, 0x45302a1f, 0xd99ed8cc, 0xd99ed8c3, 0x7c8eb52b, ++ 0xb997d63e, 0xa1c98e30, 0x81d277e1, 0x412e7c5f, 0xfb3e5fda, 0xb3ac0a62, ++ 0xda92edff, 0xbb6a6d0c, 0x5ffa3d4f, 0x6cfcce90, 0x4f5c1ec7, 0x44b04a59, ++ 0xe89e7585, 0xe8277aae, 0x36957e83, 0xfbc05abb, 0x81c75d8b, 0x4e4f3e3b, ++ 0xd7e74535, 0xdfea75d9, 0x5304b3ff, 0x77c12abb, 0x11c80ee3, 0xf3def0db, ++ 0xc4c2f4e9, 0xc23b5107, 0x14d3a74f, 0xff6c2496, 0xbf385be2, 0x44677671, ++ 0x2cefc64e, 0xd1ec3ba7, 0xdb2f98ef, 0x0c3bea7d, 0xecbec251, 0xc426c54f, ++ 0x036c52e7, 0x901f75e3, 0x2eeebfa9, 0x7f419867, 0x2e9ccde9, 0xe9e9fc74, ++ 0xfda09aaf, 0x14aba050, 0x1056df56, 0x9aaa9f2d, 0x0553bf08, 0x0a0de79e, ++ 0x32bc44cc, 0xe03b3873, 0x3b34f1a2, 0xb134cbd0, 0xd12bc07e, 0x9fc62c93, ++ 0xcd30e026, 0x9eebe269, 0x416eb71a, 0x8ef8f10f, 0x66c3d3e2, 0xc4f146a6, ++ 0x397f6cee, 0x73f08725, 0x2f1c7de9, 0x3e5e1237, 0x65d56d7f, 0xd7f7ef90, ++ 0x7f9f84c9, 0xa6225e02, 0x9780af92, 0xd25e2376, 0xa18e239b, 0x07ae8780, ++ 0xa40eea4c, 0x11544477, 0xd6099aa5, 0xbe59f2c7, 0x95affa19, 0x607bd493, ++ 0x8024c17d, 0x93282c07, 0x826cbd75, 0x0390867c, 0x2e3aab03, 0x09ffd065, ++ 0xf3807ec6, 0x51b530ea, 0x2e6a13f9, 0xb58b27e1, 0x33396267, 0xed5e9477, ++ 0xe9fc3c42, 0x33143f92, 0x786d79b6, 0x3f427fcf, 0xa1f852cd, 0xd3ffc879, ++ 0xb0e3ea9c, 0x29b0ceee, 0x36718164, 0x7df0d9bb, 0x05e6fe30, 0x2c21a897, ++ 0xa7ef8267, 0xa1ef895b, 0xd603407e, 0xcff5e0cf, 0x7bbdfdfe, 0x067ae247, ++ 0xe6cf5a33, 0x2b643642, 0xe4d737e4, 0xbaf3fd53, 0xc5d7b8dc, 0x72e1afbf, ++ 0xd482f367, 0x0ff20870, 0xa61e1c3f, 0xde6e1d00, 0x42a665ae, 0x183934ba, ++ 0x27eaba46, 0x9cdbfa73, 0x6e90e503, 0x6e330291, 0xe52e7ec0, 0x9198edf3, ++ 0xa02793f4, 0x881e472b, 0xd13f2826, 0xe721dae0, 0xe8f5e944, 0x30e08560, ++ 0x43cef430, 0x38d0a708, 0xfd0f5f96, 0xa674149f, 0x31025dc3, 0xf77000d7, ++ 0x78eb3808, 0x93cde9d0, 0xf287f404, 0x5dd391a1, 0xcf589c68, 0x966e1612, ++ 0xa3acce10, 0xd6b9c00f, 0xde10faa6, 0xee094cbf, 0x2f37f9c3, 0xb8c8fc03, ++ 0x13878e0e, 0x963f3626, 0x45f4f49f, 0x44beabe4, 0x4bf2122e, 0x52fce32d, ++ 0x7484f48b, 0x14f400d8, 0x23ac8743, 0x8faa7dcb, 0xbef827a0, 0x8c3c15dc, ++ 0x724e2de3, 0x963ffcd2, 0x2b02357e, 0x3c9bfb5f, 0xff78d13d, 0xed0bfc85, ++ 0xdf04706f, 0xb37dfe20, 0x72c4e482, 0x5afb8f85, 0x28d907e1, 0xf1dc4f9f, ++ 0xd74c2c8b, 0x628e0724, 0xfe332dbb, 0xc6550132, 0x0b0eccc9, 0x8ce4e7ae, ++ 0x01f6c9ff, 0x7f1b6b3c, 0xb17ff441, 0x51e7d5f3, 0xec5682c3, 0xf40586a7, ++ 0x98ea0074, 0x9726a61a, 0xa79d34f0, 0xb8fc2e5d, 0x3cacf986, 0x53da4455, ++ 0x872d3abe, 0x51a70fca, 0xf3fa267b, 0x5e52f6ad, 0x9435e099, 0x3271fcc3, ++ 0xb970b14c, 0x6b49cff5, 0x07d42cec, 0xafedcce8, 0x7001dd5b, 0x2dbbf0cc, ++ 0x9627a41d, 0x2e5d5e91, 0x9b9022e4, 0x73f210b3, 0xb94fde05, 0x2e500382, ++ 0xc6e87c1f, 0x54fed801, 0x18038de5, 0x903fefa4, 0x547c4161, 0x3f503f62, ++ 0xd58deb77, 0x5a739748, 0x0473206d, 0x757fe1bc, 0x2194362d, 0x79a3f93d, ++ 0xef814b8a, 0xe93ffa8e, 0x35f1a41b, 0x6235cb92, 0x67f200bc, 0xaf37e426, ++ 0x6bf28b39, 0x7df8c856, 0x1f89d6cd, 0x0d3538e0, 0xa14f72c6, 0x657883cb, ++ 0x44bf532a, 0x24406a78, 0x9bd37aa3, 0x10c7029e, 0x00f9e9dd, 0x043c22eb, ++ 0x17885e00, 0x59bfaf48, 0xf227d4c2, 0x44d7a8aa, 0x41f2203e, 0xf28bd691, ++ 0x455b4890, 0x6da45879, 0xf2223ca2, 0x35df22ed, 0xc7694cc0, 0x9abf5108, ++ 0x81c1b8d1, 0x9fb7ca1e, 0x4338f890, 0x72d106d3, 0xe947682d, 0x2bc42ce9, ++ 0x51bb99f0, 0x4b363922, 0x7313c293, 0xa68bb77a, 0xbb636f5d, 0x77cda340, ++ 0x843b4c4f, 0x98a2b8ff, 0x3d34e03c, 0x61ef2635, 0xbe6c465a, 0xd47de731, ++ 0x8b3b0183, 0x724e19f4, 0xccbde09f, 0x58509c11, 0x9245fd4a, 0x5cab7db1, ++ 0xa436e34a, 0x162f5e11, 0x04fec01f, 0x123d4c1f, 0x6f9101a6, 0x14fc2135, ++ 0xdf389416, 0xfbe84930, 0x935347ff, 0xdb41f084, 0x3bf3e10e, 0x10b8b035, ++ 0xcc68a0e0, 0x4c1c0412, 0x553bf1d3, 0x9c81e50a, 0x86756f4f, 0x323c0227, ++ 0x72ec4aa6, 0xf5b4e3c0, 0xf6476449, 0xcaf8e2cf, 0x1d90b332, 0x0eae2dd2, ++ 0x6fda1793, 0xbbd4cfd9, 0x19c1fda1, 0xb410a5ab, 0x54c752df, 0xda65bf6c, ++ 0x89cc998d, 0x212ad472, 0x80e62a1f, 0x62bcf905, 0x05c90d6a, 0x34c30f1d, ++ 0xf8e509ab, 0x7f009db4, 0x9ab4a76c, 0xbcd10502, 0x6c67b45f, 0x30f1f13a, ++ 0x1bd7d3fc, 0x0476bfbf, 0xf60495b2, 0x4de69e9d, 0xa0262295, 0x402d0aa7, ++ 0xc69a64f2, 0x61c7d7fb, 0xfbd47ec2, 0xf79c72c7, 0x6439a9b4, 0xdfab9fbf, ++ 0x5a3f68cd, 0x09bfbb19, 0x6890d284, 0x5755fdf9, 0xbebbf0bb, 0x052736d3, ++ 0xda6bcc13, 0x2c763dd4, 0x9233b61f, 0x6016e98a, 0xc3ce0888, 0x7cd0741c, ++ 0xd3bd7c82, 0xfb26e47a, 0x3f3897fb, 0x6e5d03cc, 0x815cda99, 0x0825b67c, ++ 0xbde10912, 0xfa83b673, 0xc7357e99, 0x933798ab, 0x12be5267, 0xbdece8e1, ++ 0xfcc5fbce, 0x2c05e5a7, 0x3d43c10a, 0x34d8f688, 0xd432a98d, 0x59cd4f77, ++ 0xeef5f661, 0xb4095a67, 0xfc09f487, 0xa9bdd61e, 0x367ea149, 0xff297935, ++ 0xfb03c200, 0xc87f59dd, 0x8081fd81, 0x9eea7643, 0x4961535a, 0x8f9f9fd4, ++ 0xd77c547f, 0x890dfd8e, 0xe884fff6, 0xdf4eda77, 0x37f60f2a, 0xa15f9f5d, ++ 0x5e606004, 0xf2097433, 0xa486abc5, 0xabc7e87a, 0xf614ea41, 0xac77f43d, ++ 0xbfbcbf57, 0x7e9ffb5f, 0xf26816f8, 0x9ffbc99d, 0x93e90bda, 0x5a9ff7fe, ++ 0x597afd00, 0x30adf645, 0x9597778e, 0x53dda2fc, 0xc03ee7b7, 0x7ddfded0, ++ 0xe70c33c9, 0x125c71bd, 0x4980e3ce, 0xd012f9b5, 0x9f0e54cf, 0x0e1a3a78, ++ 0x89fe40d3, 0x62a387a7, 0x8e82ed9d, 0xd4f0109e, 0xc544f9e7, 0x02df0f83, ++ 0x77190efd, 0x909bd147, 0xc2dc68fe, 0xa0de709b, 0x26fa7e07, 0xc9c9ffe0, ++ 0x0cd8ec8f, 0xc1857ef9, 0x1c7ca23f, 0xefaee13a, 0x13f6c5ef, 0xce0f161d, ++ 0x15fa99cf, 0x9e8f55f5, 0x1fa428b2, 0x1791567c, 0x3d72b329, 0x7623edc3, ++ 0x7ff07d4e, 0x24d01a67, 0xb918bfa2, 0xfac114a8, 0x7cbcfc6b, 0xa2b6ab36, ++ 0xc2d95d1d, 0xf5ecdef5, 0x05a7f712, 0x3e09d61f, 0x4ed58604, 0x7e40dfc1, ++ 0xc3804bec, 0xbde7617c, 0xbbe8c79b, 0x30a51b77, 0xbdac3078, 0xf60b3de5, ++ 0x41caeef7, 0xbbffd8c9, 0x89ac832d, 0x96eccae4, 0xf79bcbf3, 0x2e801e90, ++ 0x09f26dde, 0x3df4e67a, 0x5abfb75b, 0xd0095724, 0xa9268d65, 0x7049a113, ++ 0xf686d4bd, 0x8e4b467f, 0x412bec95, 0x8c5d475f, 0x255d1dda, 0x174377a9, ++ 0xe46d2b07, 0xdedd1ce7, 0xe279e887, 0x98a3f74a, 0x18dbf3af, 0x0c563be6, ++ 0x5ecef9a5, 0xb797f859, 0x21755d60, 0xe5055a9b, 0x0a7e0bef, 0x58c97568, ++ 0xf23c212f, 0x9608f0a3, 0x432ddf2b, 0xea2df9f8, 0xbc28bedd, 0xf00f582c, ++ 0xbcc91d9b, 0xe71816fe, 0x62a490c3, 0xeb5ce628, 0x4d85677e, 0x08d0c7c8, ++ 0xb6ef2bd4, 0x0651bda6, 0x5cd9cdfd, 0xc7d01871, 0xc83a2b3a, 0x0764580f, ++ 0x3ce006bb, 0x29d9ed6f, 0x11562900, 0x5ff43492, 0x85b5ef66, 0xd987806d, ++ 0x9c348c80, 0x8a0e5bcf, 0x257ae80b, 0x75672718, 0xbfe3eafc, 0x8c941a1b, ++ 0x45bdb972, 0x2f9dfe4e, 0x2dd9c78a, 0x09bd8769, 0x51e3ade6, 0x85b3e397, ++ 0xdf01dacd, 0x1e01fce3, 0xbcff9c2e, 0xad9ed1b0, 0xd8314c6d, 0xfa75e39d, ++ 0x37f4e46b, 0x50c335a7, 0x859cff0f, 0xfe3cffd0, 0xe7e79b37, 0x1689f276, ++ 0xffec5ef9, 0xb66b86fd, 0x76f2848c, 0x2405b4e9, 0x5add9b14, 0xad698c98, ++ 0x5adfedc6, 0xe8bbd83f, 0xe9d9c7c7, 0xc1948fe8, 0x474b47d0, 0x06dd2326, ++ 0x7b57ba57, 0xeafc517d, 0xab61bbf8, 0x2b9e4ed1, 0x4ae0aaec, 0xf6a2bae3, ++ 0xbb45669f, 0xd78ede24, 0x17683ced, 0xdb555142, 0xbb07ac68, 0x6951556f, ++ 0x9b03ce94, 0xb9253ed2, 0xad729173, 0x41efed16, 0xabbf453c, 0xa059ed12, ++ 0x3d0d598b, 0x10e3cd7c, 0x0021c78c, 0xf9bfc253, 0x9eb94b57, 0x59eefdd2, ++ 0x3f49670d, 0xf4e46acd, 0x78c3cbaa, 0x8d514e38, 0xccaab8f8, 0x9a35a748, ++ 0xa9af2e91, 0x3f68681a, 0x50d4302d, 0x97e9bdff, 0x0467ea19, 0xd7f21a47, ++ 0x686b1fcd, 0x44fd7d7f, 0xe9bfdd23, 0xa0bc7ee6, 0xffe173d7, 0xdf57a135, ++ 0xf4cfb388, 0x6ff8bab4, 0x27c7c8d9, 0x36f4d86b, 0x8a31a74c, 0xe0ac9c23, ++ 0x1e62a0e9, 0xf31673ff, 0x45a7c238, 0x9770bf3c, 0x310ff5a3, 0xe6dc59f3, ++ 0xee97e436, 0x43fd6ccb, 0x0a167acc, 0x245bb2b8, 0x22d9f233, 0xb316c55e, ++ 0x6728018e, 0xf51f26bc, 0x91d4c4bb, 0xd64ef98e, 0x5e90ae95, 0xea5f108d, ++ 0x28e93af8, 0xc44cdbb7, 0x16fe3c1f, 0xc0387f1f, 0x99b7e47c, 0x25293ed9, ++ 0xe3d1ef1a, 0x0472bf3b, 0xe91f20cf, 0x3ce3d7eb, 0x8b8b71f1, 0xc2aeabe5, ++ 0x3c4567e0, 0xabd0639e, 0x5b7984ff, 0x737efb8a, 0x293b06f3, 0x5bf4b8a5, ++ 0xf1567799, 0xeaef0837, 0x6290e0c2, 0x1e25bc23, 0xe7c6f8e7, 0xc24dfc5d, ++ 0x13b0967b, 0xb509e3e3, 0x4dfdc64e, 0x7900be3d, 0x5332d3d4, 0x528bbfbf, ++ 0x0273ffbe, 0xa5095765, 0xef37f261, 0x51e4f5b0, 0x8bb89f7e, 0x3c801fe7, ++ 0xeebaefa3, 0xb4c1cdcd, 0x694f95c3, 0x5991fa98, 0x32f5f93d, 0x41923f6b, ++ 0x720fa0e5, 0xe5c0faa2, 0x72efc7d2, 0xe57aa60d, 0x63aede7e, 0x0bd92e4a, ++ 0xa8c84f5c, 0xf85da827, 0x5f688648, 0x3902ed49, 0x71d38d12, 0x9213f450, ++ 0xf0f76529, 0x0cf6e176, 0xdc6547ea, 0x2ea9e51e, 0x56e27f77, 0x8c9fa3a7, ++ 0x2a721a5b, 0xe83311a5, 0x458bb7cd, 0xcc1cd4dc, 0x03edbc24, 0x6e765ec0, ++ 0xb0b49fb8, 0xbbd0f184, 0x5c3b1c84, 0xbef4a66c, 0x224b6ef2, 0x9fa7b4ff, ++ 0x3855533c, 0x95bffd41, 0x3591fdf0, 0x73df3e2e, 0xa572738d, 0x5df7e139, ++ 0xf353dea2, 0x7b3e7492, 0x29996537, 0xff504e10, 0xfe3e62b7, 0x4d26b763, ++ 0x5673fec7, 0x05c96ced, 0x90d939fa, 0x217e8856, 0xfd19aa90, 0x24286f2c, ++ 0x1fef832d, 0xf831ce29, 0xdf1ab337, 0xc1e19559, 0x910a7bf5, 0x7905bf96, ++ 0x7e8bdc7e, 0x2f1894bb, 0xf47ac573, 0xe8a741fd, 0xb43401ef, 0xf7485d70, ++ 0xa36704b0, 0x9871f68d, 0xd7ec37ea, 0x62c49f30, 0xe9dbd3bf, 0x2a368dfc, ++ 0x7214f4e3, 0x9bf74514, 0x633a51bc, 0xff3a6748, 0x4b0ff7c7, 0xecc7250d, ++ 0xeb0578db, 0x48667f63, 0xfb82a303, 0xc8f45e51, 0x11a99f89, 0x9c9c4b8c, ++ 0x2a3f2766, 0x98737188, 0x69cfa98f, 0x1b07b78a, 0xc50a5c84, 0x4d7d1fed, ++ 0x21d272f9, 0xeb8bb6f4, 0x957ebd71, 0x148fdfd0, 0x7b7a7b7f, 0xf9e045c0, ++ 0xd28cc587, 0xb412a193, 0x016a58c8, 0x932c30c3, 0x7e432a9d, 0xbe0b2acc, ++ 0xd7a06c57, 0xdb84249c, 0xcb278657, 0xcd6e2852, 0xb17ebdb8, 0x52e5d4f0, ++ 0xd88b337f, 0x694893e0, 0x63d453f0, 0x7e296520, 0xebf3cfa1, 0x978eaff2, ++ 0x6c162601, 0xa61f204b, 0x3bfa8895, 0x34f9233f, 0xc51748eb, 0xd6356653, ++ 0x78df3c0d, 0x654d07a8, 0xf3276ab0, 0x1f23ced9, 0x2e2f387d, 0xdd225767, ++ 0x92fbd567, 0x95af20ea, 0x3b54b970, 0xae124875, 0x63ec02b5, 0x9da14f8c, ++ 0x90e262cc, 0x6c73f6b1, 0x765cf0fc, 0xd607eeb5, 0x5c00dc0a, 0x3eae3843, ++ 0x4ec2359f, 0x9d873e6d, 0x574066ba, 0xe9f68ab6, 0x084bb75d, 0x462d1d8f, ++ 0x78d19db9, 0x1d031576, 0x43b91199, 0xae6a61f2, 0x3818d497, 0x3bfe9ad9, ++ 0xf279e71b, 0x2576ffae, 0x86c9df82, 0x78425c4f, 0x2b5bff90, 0x272c5ffc, ++ 0xf8f237f8, 0xfa77fc45, 0xf3d5b6fa, 0x2e3464f9, 0x4fc83493, 0x612f599c, ++ 0x589d61bc, 0x6a99acd7, 0x56594504, 0xf9425841, 0xabbeab3c, 0x9dabc712, ++ 0xca32f5df, 0xa602dae1, 0xdb5e506a, 0xeae89070, 0xf8e0b2b9, 0x1d28d292, ++ 0xf606f4ea, 0x896e4bc0, 0x15887be4, 0x95549f11, 0x7d2abe00, 0x3f389d47, ++ 0xc5b7ddbd, 0xe3f55927, 0xa8eb1842, 0x5371e7a8, 0x94f43ba0, 0x041d7d60, ++ 0xa4a3732f, 0x5cdca046, 0xb07d556f, 0x86a1b93e, 0xf9e575f6, 0x76835556, ++ 0x888d9787, 0xb07f7ca0, 0x44711241, 0x566e1fa3, 0x83e95fea, 0x134cd176, ++ 0xd06ec993, 0x57dfd1aa, 0x62ad9d04, 0x58c1f681, 0xf07fc1ae, 0x5728b25d, ++ 0xc6abcfe6, 0x8d66b24c, 0xfc68178b, 0x6390829c, 0x918d86f6, 0xacf34c0c, ++ 0xae4bff06, 0x01f14d5f, 0xc687b61b, 0xfab8ac96, 0x9f6813f9, 0xe58c564c, ++ 0x3cb89477, 0x750fffb8, 0x74564fb4, 0xefa6f147, 0xee4a7cc1, 0x9857e6ba, ++ 0x823e254a, 0x371588db, 0x3f874da7, 0xba6d56cb, 0xdc1fd306, 0xcbaf97f1, ++ 0x7296cce7, 0x97ae7cf1, 0xcbe42cbf, 0x1cfcf905, 0x7e4e7afc, 0x93b62c69, ++ 0x737c169c, 0x8493f1b2, 0x37ce95f6, 0xa7ac7cf1, 0x0f202eeb, 0xc8e80dd6, ++ 0x713efe46, 0xfc7cc8c7, 0xf6e1b6be, 0xe5166183, 0x65c6daff, 0x6b303fb4, ++ 0xa4aa5326, 0xbe27f2de, 0x575f3ebf, 0xf7adc43e, 0x389c80ff, 0x8c4e4892, ++ 0xd987fbfd, 0xda9fa3e7, 0x8fda2eac, 0x4b447f02, 0xa5fda7a4, 0x94e40f5c, ++ 0x849d28da, 0xc2441e02, 0xf706f864, 0xbad6651d, 0x37d81d6d, 0x15f98163, ++ 0x05469bc8, 0x68728b7f, 0x406de432, 0x6e249327, 0x73370cff, 0xb3f5197d, ++ 0xdba5ddb8, 0xd9cfe959, 0xa298fa3b, 0x6b70d376, 0x43f40cc7, 0xc561de4e, ++ 0xe4ec2f93, 0xfb79fffe, 0xb2b73c76, 0x860eaedf, 0xd8518439, 0xfb3efd60, ++ 0xa24f3c76, 0xdb2773db, 0xe02ecec0, 0xb1ed1afa, 0xed128d59, 0x909f813b, ++ 0x78465ca4, 0x4571aa4b, 0xe870b6ed, 0xc06de910, 0xab9d7677, 0xfd077db7, ++ 0x7867ec30, 0x0564cd63, 0xdcadb5e6, 0x8f489554, 0xfa7016ef, 0xfe0bfcba, ++ 0x63f400df, 0x0e789e70, 0x83be664a, 0x558fdc26, 0x68be7e01, 0xc8eff07b, ++ 0x2286f7ce, 0x65f70d92, 0x3515e656, 0xcbb4be73, 0x2a4cfedc, 0x207dc52d, ++ 0x2a6e5f51, 0xf745f66a, 0xd9875885, 0xf8e7718d, 0xe7bd1973, 0x74a76665, ++ 0xc8478979, 0xa53d0446, 0xdbebe809, 0x94b32fd2, 0x7f79f4c4, 0x0d5f9729, ++ 0x674a0ea5, 0x025da079, 0xfa5b5239, 0xd7bdd9ad, 0xdbe8395e, 0xb1b7cb83, ++ 0xad7faa9e, 0x2c996cf5, 0x27ad4bff, 0x16bfd27d, 0x9b7f8e7e, 0xee7f01eb, ++ 0x35c9123f, 0x5e2fd0af, 0xa7ef3f27, 0xaf904fcb, 0xedf694cf, 0x03fea7ed, ++ 0xa5e7f572, 0xef8f7b7d, 0xe29539c1, 0xc5175226, 0x54a12ceb, 0x59c7fa2b, ++ 0xf4b8231a, 0xcbca33f3, 0xfd429768, 0x0e4c0f40, 0x031a2bca, 0x3aa73c76, ++ 0x186263d0, 0x546bab77, 0x256b3ca9, 0x9d822b8f, 0xbe81f618, 0x71e217ec, ++ 0xd7907ebe, 0xcdaabf20, 0x4237cfcc, 0xf77de31e, 0xfdb05a01, 0xed00ce3b, ++ 0x2baccadb, 0x0e8bf713, 0xf2a565df, 0x49f13d95, 0x8e037b56, 0x71cffa23, ++ 0x9f68c205, 0xc3897caf, 0xc7681def, 0x516c07bf, 0x5023b1bc, 0x99e3c396, ++ 0x5c8f1e36, 0x8d89cd61, 0x51840647, 0x869d91ae, 0x91fb1068, 0xd2bcbfd4, ++ 0x8de313bc, 0xcbb046e6, 0xd6e14787, 0x319d7cfb, 0x0bfba8ae, 0xbd5c5983, ++ 0x8a0617f0, 0xbe21c1f2, 0x0fd7a86f, 0x37ef1cdc, 0xf57ef2f0, 0x6793cb89, ++ 0x7300fd1a, 0xd3a39f88, 0x631ecdeb, 0x57417f7d, 0x8d93dc7a, 0xca837e10, ++ 0xb8df688a, 0xa0bb2245, 0xcb82ed0e, 0x100d76a2, 0x753fc51c, 0xc558eaba, ++ 0xc87082ed, 0x7d36f1c4, 0x93f20ec8, 0xbf53579c, 0xb7a07dba, 0x4ee95baf, ++ 0xec764d9d, 0x26de3cdd, 0x2da7e5f8, 0x0fd0ebc5, 0x9afebbd9, 0x6cfa625f, ++ 0x667dcdeb, 0xa95abc10, 0x9bcdbedd, 0xdebcc4ae, 0x2bd3e00f, 0xe33278f3, ++ 0x6f76e571, 0x2431e132, 0x033e3af2, 0x1e7f0833, 0xd3879d2b, 0x416656e9, ++ 0xac1ef1c6, 0x693a23aa, 0xa530f915, 0x3d7cbc47, 0xbe3c9dab, 0x1ca1f50d, ++ 0xcabbe76a, 0xe89b6944, 0x12feb227, 0x9fbb574e, 0x35fdb4a2, 0xcd3f6f9e, ++ 0xf27de0f3, 0x3895edf9, 0x7a08161d, 0xa73965bc, 0x343e7163, 0xfa2c6478, ++ 0xd8935ea5, 0x21d40cff, 0xed53cb1d, 0x8c37e60a, 0xfbe5e11a, 0x7bdcfc23, ++ 0x63d19c4f, 0xb36338a5, 0x728636eb, 0xdbd2deea, 0x47207822, 0xafe462ce, ++ 0xe52a59ca, 0xc601f06d, 0x43cf81f9, 0x0be90e74, 0xe8230290, 0xb3fd28dc, ++ 0xbc0e824a, 0x1ac7c21e, 0x1c5e6dd7, 0xdba8c364, 0x9befc2de, 0x0fea56dd, ++ 0x7c8e99c6, 0xf22592de, 0x55bc4f25, 0x16978317, 0xf276dde7, 0xe3cee2df, ++ 0x764304b7, 0xecd45f3c, 0x30fbb22b, 0xdf911675, 0xfd4ea7a2, 0x632b3e9c, ++ 0x171a4fb4, 0x5d3d94ff, 0xc33f744d, 0x3ac3e23d, 0xbc4376b1, 0x87a1c055, ++ 0xf8e3f23e, 0xc4b18be4, 0xbddfbaa7, 0xbaf9c5cb, 0xe30b1879, 0xc4b3453e, ++ 0xaacccaf1, 0x24abef17, 0x9ac458f9, 0x268e5bdc, 0xe2663b39, 0x1f7d643c, ++ 0x5cf3c045, 0xa5d9b772, 0xe7c5137a, 0x1bfbfa63, 0x815269f2, 0x1fe93f91, ++ 0x530937cc, 0xa93dff58, 0x3e23844f, 0xf285ec5e, 0xac6e423e, 0x655ee5f3, ++ 0x53db45f2, 0xdfb08317, 0x57d432d0, 0x9dd8dd3a, 0x6091cd56, 0x753cee9c, ++ 0x2aa21cfa, 0xfc7b9516, 0x2f37913c, 0xf4067c66, 0x2bb1788e, 0x8f87f2f1, ++ 0x16677fab, 0x55bf40e3, 0xc2996357, 0x5121a5fb, 0x96993a7e, 0x9bc7e31c, ++ 0xbafec67d, 0x6e505ef1, 0x3fc877dc, 0xdf270ece, 0x0d3b6367, 0xfe2513f1, ++ 0x79cd10fb, 0xf88d4ed8, 0x3f272ae1, 0xd2dcd0d7, 0x7e82625d, 0xae356e87, ++ 0x33e791df, 0x9d91f79c, 0xd7845f4a, 0xe9116f6a, 0x0bf3dec3, 0x72e4fa85, ++ 0x7a3c2180, 0xbe0e33e1, 0xf017be09, 0x166bf4e4, 0xa7ef8970, 0xdc7f7ef7, ++ 0x96cd0e79, 0xb26b1d70, 0xf913d8b7, 0xc6cce37d, 0xa77e2273, 0x1e09fbf1, ++ 0x96557d63, 0x793b2f31, 0x6857ccff, 0xe73775c7, 0x7b3b1f01, 0x7afc71f3, ++ 0x7e3af87b, 0x41d844bf, 0x13ee7951, 0x7077d87a, 0x7cd9c52b, 0x859ef107, ++ 0x2fb4055c, 0x35f914f1, 0xf92bf715, 0xbf90a07e, 0x553be26d, 0x24862fec, ++ 0x645fdc83, 0x7da0e715, 0x25b945bf, 0xd7195997, 0x6f072103, 0x0f32beaf, ++ 0x036c2ef2, 0xdda3f7f5, 0x59bb7f00, 0xd503d717, 0x24df2a26, 0x24fb8eec, ++ 0xd5ddca95, 0x284c2d20, 0x66bef87f, 0xb8c4d306, 0x71632bea, 0xed136adc, ++ 0xa2c2ae4f, 0x46b5044c, 0x2b58d9df, 0x61bbebb5, 0x27bc0ae8, 0x058377d6, ++ 0xd6b0486f, 0xcd6fc3ba, 0xb0f631f1, 0x73b7fea5, 0xb5b91e50, 0xf1507983, ++ 0x64f4e8e2, 0xdc9bbf94, 0xffc70526, 0xedfd5b89, 0xf34f985c, 0xc5ff7e14, ++ 0x1d8370d6, 0xef83dea7, 0x2fa4a911, 0x30565ad3, 0xada7478c, 0xfb107a1f, ++ 0x14ab334d, 0x66ad4e8f, 0xc0fda25a, 0x7ee48cdf, 0x90e51aea, 0x778c0e77, ++ 0xce9fcc3f, 0x23f58aa7, 0x9b4e905c, 0xfa204d47, 0x3e6bf6ed, 0xce6043bc, ++ 0x41e4b60e, 0x5c55adbb, 0xd3cd6e5f, 0x96997ff7, 0xd4f9c452, 0x901af14a, ++ 0x38b690a7, 0x845ce658, 0x152490cf, 0xbc3d8028, 0x22664b60, 0x7117957a, ++ 0xdbdf8f79, 0xebd77a8a, 0x595706e9, 0x959bea26, 0x387c4653, 0xe0f1e617, ++ 0xaf28db94, 0x4234fbcb, 0x71bf4c7d, 0x535dd2f1, 0xdd9bde38, 0xde6007a0, ++ 0x980f409b, 0x3566a011, 0xfc04eaf3, 0xaab723dd, 0xfe401eb9, 0xd699fdc5, ++ 0xe7f9098a, 0xab98b78b, 0xd5493eb8, 0xba9546f5, 0xf06ee302, 0x30ed047d, ++ 0x77cf07ec, 0x7ae1aa43, 0xb7f5245b, 0x8a725f74, 0x98f787d5, 0xd20f33ce, ++ 0xf8b8e61f, 0x4f8114f1, 0xa985e226, 0xda740758, 0xe4b75162, 0x532dbf41, ++ 0x2876ea4c, 0x945d54da, 0xad28ff70, 0x1cfbf39a, 0x1250ea8b, 0x313737d4, ++ 0xedd8f73a, 0x7d9b8f57, 0xd39f99e7, 0x2351af38, 0x0e9bfef9, 0x731edd07, ++ 0x456c7557, 0x26734bba, 0x4249b9d1, 0x8547ca1a, 0xd6f40b7f, 0x2f596882, ++ 0x5945fdf1, 0x726d8bec, 0x7f213d01, 0xbe74acba, 0xdca7d4d1, 0xc83c3e77, ++ 0x1317a0d5, 0x7eddcdc4, 0x9ff0df21, 0xffe0276e, 0x17a0cc69, 0xd20ef5e5, ++ 0xdef9e76f, 0x21f5d667, 0xcccd152c, 0x59ccfed8, 0xea3dfe26, 0x99b7c441, ++ 0xbd45ac85, 0x2657ebfb, 0x0cb4f7e9, 0xe82acbdf, 0x7f5a64d7, 0xe009f908, ++ 0x4278fc42, 0x10967802, 0xb5fbf0bd, 0xb979716f, 0x1617db29, 0x9f4840f7, ++ 0xdcaff15b, 0xfb75e3de, 0x157cf95b, 0xc89fdd16, 0xf5f5e689, 0x7e71243f, ++ 0x68ca5d09, 0x68fdde9c, 0x9de57fa4, 0xcecfea61, 0xd0e98e7c, 0x4da83ece, ++ 0x5bd39b9d, 0xdbfb76ff, 0xbc012e5a, 0xa9ea7bad, 0xda9079b6, 0x0fbecc7d, ++ 0xeecf71e0, 0xc53e1f1d, 0x666ff77a, 0xdf813f9c, 0x429b1d69, 0x0e51f29b, ++ 0xf0fbae39, 0x69833c51, 0x4127db8d, 0xb2bfa004, 0x82d83ab6, 0xdfdf1a74, ++ 0xabdc96a6, 0x9deb8ccc, 0x1cfbe20c, 0x40f2cb92, 0xd20f7a9f, 0x97fb9da1, ++ 0x46129a72, 0x1d569e79, 0x641eb854, 0x4d970879, 0x6af64502, 0xc09fe916, ++ 0x752f5abe, 0xe23df03c, 0x08f74663, 0xe279f7e3, 0x239ffbe7, 0xb4f784dd, ++ 0x07da2eaa, 0x0bd7f6e9, 0x23af817b, 0xbfe39e9e, 0x77d804f7, 0x356ddee9, ++ 0xcfbaafdf, 0x78c5e5d2, 0x82f77df0, 0xe76b169f, 0xece1c1c4, 0x6f5cbe88, ++ 0x473a3354, 0x11ccff7c, 0xbab7bc0e, 0xe1c8aaa9, 0xac764613, 0x7aa9bdbd, ++ 0x17dbb736, 0xec1bbb71, 0xe0ffba25, 0x8f7d06ac, 0xff611271, 0xe23189a7, ++ 0xa0a6fff5, 0xfdc3d7e8, 0xd7e7163f, 0x73ffb05c, 0x95b613d8, 0x3a7744a5, ++ 0xb71daf3d, 0x82f51325, 0xb35beebe, 0xa0e7b36f, 0x626498bc, 0x9376ff78, ++ 0x1eb4d738, 0x1c8effe4, 0xd7a0ff94, 0xe9ea0e88, 0x7726e79e, 0x8f41d11e, ++ 0xca7299be, 0xa4d9788b, 0x7a8ad88e, 0x5ceafef5, 0xfefa4e07, 0xa2d7bbaa, ++ 0x341d5d5c, 0x8f4c58f1, 0x3d2e735d, 0x77cefaa8, 0xebffe65f, 0xff4c7fbf, ++ 0x0a667ae9, 0xba06be1e, 0x62a475b8, 0x8d115738, 0xdf84041b, 0x27bf09af, ++ 0xaff37e3e, 0x3fc69e91, 0x395d0ec1, 0xacba302a, 0x5bef1a34, 0xfa1a5793, ++ 0xb5fdc31e, 0xc0377ea9, 0xd187927b, 0xa78b1b7d, 0xda2fb0cb, 0x03b6a591, ++ 0x2f2bb119, 0xbe7ed5bd, 0x2cb66af3, 0x60748e96, 0x4ca807db, 0x35bb7739, ++ 0xae28a7d9, 0xb7bddefa, 0x6e3cf9db, 0xf6f3b3b5, 0x76c1eadb, 0xbdea59ef, ++ 0x4d630e78, 0x77da08f6, 0x17f9066d, 0x92bf1271, 0x3479b0f0, 0x8d6a2d4a, ++ 0xc2dbf919, 0xdd4cbef8, 0xa9cd5baa, 0xb9f10718, 0x9cd35f69, 0xe44b3015, ++ 0x18672cbf, 0x09e49a8f, 0xcfa01405, 0xadf09ec9, 0x6be26d0a, 0x91e28e3c, ++ 0x93ffc84c, 0xe56fcccd, 0x96378cfb, 0xf2ad1d01, 0x1d63bbbc, 0x06706bc2, ++ 0xe1d3779d, 0xb6eb5169, 0x6e3463af, 0x1031f504, 0x1b49e925, 0x165e3fee, ++ 0xcfd47fdd, 0x90fbe84f, 0x8972ca5b, 0xc3aca53e, 0x1bbca39f, 0x969874ae, ++ 0x2c927c03, 0x07c8751d, 0x71801a6b, 0x64d60f80, 0xc0ab3f71, 0xe8f5cfc5, ++ 0x596c99f7, 0xd075e981, 0x3b0ee92e, 0xefe007cd, 0x71a25254, 0x17b04cbb, ++ 0xe558ded0, 0x11d4a1d9, 0xd6f36efc, 0x7a27d025, 0x582b3c3a, 0x7018708d, ++ 0xd1f90367, 0x0cf523b6, 0x2b2d95e5, 0x8afb5178, 0xf11f1816, 0x31b2736f, ++ 0x5583a3e7, 0x89e9d6d9, 0x613691fc, 0x83470cff, 0x877fd705, 0x6bb9e29d, ++ 0x56f9dff6, 0x3f74495d, 0xb7332816, 0x3ee8d2e6, 0x336e7eac, 0xb3de8e3e, ++ 0x39f8caaf, 0xbeae3d3b, 0x4573025a, 0x76faf8a6, 0x2a6f8be4, 0x88c6febe, ++ 0x12cb8fe0, 0x5b59d7c4, 0x0fed45da, 0xd3368d24, 0xb90189b9, 0xffbb182c, ++ 0x65c051b8, 0xea7c0f63, 0xc16fbf49, 0xe7a526cb, 0x3fd44f86, 0xc0dc6756, ++ 0x1f22dfe3, 0x8cbaf8a6, 0xc5064037, 0xba1de1fa, 0x0fcbd47c, 0x0767b8f2, ++ 0xc8f62b8f, 0x330adf4f, 0x7243c7f7, 0xb7f96c4e, 0xa55d4f2b, 0x09be1c25, ++ 0xa697bbee, 0x3fd10913, 0x8a3cf54f, 0xaf3b37b3, 0xa7ef6256, 0x7924f1eb, ++ 0x23773f3e, 0xf1104f57, 0x31498973, 0x602d347a, 0x55c933d4, 0x73af7cc6, ++ 0xf6fa713a, 0xcf872141, 0xecfb8994, 0x2f88d823, 0xa7e4e0f9, 0x1d738b25, ++ 0x0eb951ae, 0x72aac3b2, 0x0919bce9, 0x49ba1889, 0xf79df2ad, 0xe101da9e, ++ 0xdc4cfd9f, 0xfb888cbb, 0xfdc4878c, 0xfef097b5, 0x0ec610da, 0x7a53e537, ++ 0xf2a549a4, 0x84ca9b57, 0xc4321093, 0x9f022c67, 0xb85b9296, 0x6be6209f, ++ 0xbc05f316, 0x3a788b27, 0xa55c4bdd, 0x1ac1b8f0, 0x17413fe0, 0xd73f1e11, ++ 0xabfa73a6, 0xddf316bf, 0x47f72a59, 0xd397bd58, 0xb795ab61, 0x71361d0f, ++ 0xb88ab53a, 0x8fbc424a, 0xf7b78aee, 0xcfd8f979, 0x93ee1392, 0xfbf8b054, ++ 0xbc7cbc5b, 0x7ec2607d, 0x09a1952a, 0x5ef44fdb, 0x24fdb096, 0xe584c8df, ++ 0x4d8fe657, 0xf705cfd8, 0x7b5a428f, 0xbdf47a7e, 0x2ef29e86, 0xbbbe0ff8, ++ 0x5cedd041, 0xd3379f85, 0xbb886feb, 0xf9d3a5df, 0x6e7eb8c2, 0xb76c6adc, ++ 0xbfb8cb30, 0x7eee20b5, 0xc26542dc, 0x2ce3b107, 0xd7ac65dc, 0x8f2693f7, ++ 0x923df412, 0xfb2afc8d, 0xba3e7aa2, 0xe9d0134f, 0x29f78f4b, 0x46611f3c, ++ 0xc5c4a539, 0xd7913501, 0x7974f7f7, 0x3ef89117, 0xb3c8974c, 0x24af5e54, ++ 0x2a967909, 0xe8ae64e4, 0xf7f448af, 0x1f3e3cd3, 0x6b91d7d3, 0x53f277a8, ++ 0x457ef98d, 0xb11cfcd1, 0x5ae502ff, 0xe03b4c5a, 0xed8bcd56, 0x2ef7f3d6, ++ 0xac6cdeb0, 0x7a130d0f, 0x8e5312cd, 0x5247395b, 0x5a33bbf9, 0x8d27ef11, ++ 0xc8588bb7, 0xe377690f, 0x9fd5903a, 0x53ede22b, 0x22d0bb78, 0xf498579a, ++ 0x1c378e09, 0x21aaf5f3, 0x5e20adde, 0xc4a57be0, 0x03cac523, 0x4533888b, ++ 0xba11d2f1, 0xead6d60c, 0x2360f2e1, 0xe30903ca, 0x762c4525, 0xb7df591f, ++ 0xa2abf6eb, 0x19b8a95c, 0x9f9c7ff8, 0x8b76f091, 0xb88c2bf8, 0xca8fef02, ++ 0xae171e7e, 0x1bfa4660, 0xf0314f6f, 0xe462a559, 0x235e89f7, 0x19f24f9f, ++ 0xd7e41bf9, 0x3f61b32c, 0x90b37db0, 0xbe14e647, 0xc94fe80f, 0xbff8eaf9, ++ 0xbe657a50, 0xbd009e51, 0xd671c4ae, 0xd8a8c160, 0xda0b11f6, 0x9e6e8857, ++ 0x2f26cc46, 0xf2998ff1, 0xec341feb, 0x92ab5573, 0x6edee303, 0x1cd2fc0d, ++ 0x3b5aafda, 0x99619508, 0x40fb2149, 0xc413e9f8, 0xef016ed8, 0xc91d4ac3, ++ 0x98bb7bed, 0x8d90f184, 0xc2ba8b1e, 0xbb6fd007, 0xf5e50b3a, 0x33aa49c4, ++ 0x5955f005, 0xfa9ebf54, 0xcfb233f5, 0x9f6e355b, 0x7bf2746e, 0x3cc68a2b, ++ 0xec3d2073, 0xa8ce2995, 0x9f497d49, 0x27aafdb9, 0xfde88fd6, 0xbddf4a9d, ++ 0xfb20ea5e, 0x32abbc70, 0x7351dfa1, 0x6e418e79, 0xf5209598, 0x92ab0bfb, ++ 0xc6d17689, 0x820adbca, 0xb14ba694, 0xa4b3bbdf, 0x1eb5e784, 0x7446dcbc, ++ 0xffa9695f, 0xdb8051f3, 0xe289bf06, 0xe3fc1bd4, 0xabe60b24, 0xddc5c519, ++ 0xd20f8325, 0xee820a3b, 0x69f74165, 0x3e238efe, 0x9996638c, 0x9776ac54, ++ 0xb7027df1, 0xf9e127df, 0x6e2aeee4, 0xe4b3b84b, 0xf7ac3515, 0x46d5a9f8, ++ 0x4b51b67d, 0xc7efee7c, 0xdd685b97, 0x525db21b, 0x52cfce1e, 0xe5c50b7f, ++ 0xf1ec5db2, 0x74bce89c, 0x6b0bfcfd, 0x23c2017d, 0xb848acd9, 0xf3f7e91f, ++ 0x2b32eef6, 0x06e76bbd, 0x92bcc436, 0x803b0ae5, 0xae6427fe, 0xb7778862, ++ 0x7f408d8f, 0xb2b5a1c2, 0x07880539, 0xfc5e218b, 0xa4ea7f0b, 0x2adda06b, ++ 0xaca78f27, 0xe10aac62, 0xa54b587a, 0x3b4f4ef8, 0x389bfb4f, 0xd1d9d929, ++ 0xc2017667, 0xf4e4e823, 0xa9784a92, 0x9d6c77f6, 0x6b57e303, 0x7b45de8c, ++ 0x95066fb9, 0x6607f78f, 0x363d3cd2, 0xbe749e7d, 0x6669afd6, 0xf654738c, ++ 0xfef79cb5, 0x4a92ab43, 0x7f46d476, 0x7e8894aa, 0x86edb8f4, 0x1dbce951, ++ 0x0fd63bcc, 0xf88cf875, 0x973cbf28, 0xf28ec3e8, 0xfed6e301, 0xebdbd100, ++ 0xc6154096, 0xb52f5e95, 0x5ebcbd10, 0xce3fe7ca, 0x5af9d0af, 0x525b9977, ++ 0xe42fbaf8, 0xbf979d3f, 0x858eb5cb, 0xcff28f08, 0x81a35092, 0x632ede9f, ++ 0x067f67fe, 0x55f8c2ba, 0xb9ef5f35, 0xebfb77fa, 0xb0f51f69, 0x3c212d37, ++ 0x810cfc7a, 0x87f2f8c7, 0x87fe172e, 0xdf1965f3, 0x24f90c2d, 0xfedc33f2, ++ 0x4029f1f6, 0xd707e307, 0xaf20bbd0, 0x4cd47e97, 0xfd78c3f5, 0xbbadd778, ++ 0xb35a9e91, 0x77d8b0fa, 0xadf4f4d3, 0x3dae1c51, 0x7ce345fa, 0x49afe63c, ++ 0xba368f24, 0x0729614c, 0xee066553, 0x1d4a851f, 0x58dd4f14, 0x24235569, ++ 0xb8d1e69f, 0xf4c2678a, 0xc97d201b, 0x9aa3f7cf, 0x6f49b303, 0x5750d78c, ++ 0xa69cffc1, 0xcc8f48c7, 0xcf72499f, 0x66aeec2d, 0xd70738e7, 0xac7b4663, ++ 0xc4745fd5, 0xd6b5df07, 0xcdac549b, 0xe7738d72, 0x5fb87a11, 0x76f19031, ++ 0x95fd8503, 0x9e8567fc, 0x8c6acc99, 0x68d727df, 0x972154bc, 0x0ae165dd, ++ 0x84335174, 0x6f9ee2bd, 0x8f54b3a4, 0x99e1876e, 0xe257687d, 0xf8e30c78, ++ 0x7ec6999e, 0xa7ee1553, 0x3b8dcbc4, 0x5fec4f2f, 0xd759fae8, 0x3625adc7, ++ 0x1f3af392, 0x2e70fcea, 0x47dfd0ba, 0x17f84379, 0xf890ad01, 0x2ff098ef, ++ 0xa5ef14de, 0xc5fe171c, 0x57f792a6, 0x9fdea1a6, 0xf39f68c9, 0xfc6fe12d, ++ 0xbf1bf84e, 0x08637f47, 0x20ed11ca, 0x2bafc5ca, 0x25463bb7, 0xfb965d11, ++ 0x18478e8e, 0xea3fc98f, 0x144bb58c, 0x30aaafdd, 0x97a41599, 0x89954906, ++ 0x152bbb6e, 0xa959d414, 0xed050464, 0x12b0c3ee, 0x567c43b0, 0x9e95a437, ++ 0x3e226b42, 0x87fae089, 0x17653fa0, 0xf857947e, 0xafdd7c51, 0x24be758a, ++ 0xedd0e7de, 0x15d7905b, 0xc1ba5fb8, 0xa727bc62, 0x2cf951a7, 0x779086e4, ++ 0x199bb213, 0x208d8fea, 0xc792258f, 0xb23b5e5c, 0xea9ec98a, 0x7f9ce7cd, ++ 0x9e005836, 0x92cf0405, 0x19cff284, 0xf00902d0, 0x79cbbbfd, 0x238374fc, ++ 0xc0197330, 0x2325436b, 0xc85e36b9, 0xdd179869, 0xf56b71b3, 0x14cf908b, ++ 0x1bd46be0, 0x1d302d7e, 0x2cfe0fe3, 0x2e8bf117, 0x9e9c599f, 0x9da725ec, ++ 0xffdf14a9, 0xddb4e4a6, 0x9c21aad3, 0xc399f2a2, 0xed33e40b, 0xf25b7fef, ++ 0xe3e33479, 0x14ccfe8e, 0xf5f6ff46, 0xe0af51d2, 0xb7215f3b, 0xbbec1d49, ++ 0x2b341cb0, 0x5cd75e5c, 0x2a7e88ce, 0xca3e6765, 0x24a59bd1, 0xbe18e515, ++ 0xbff08761, 0x6e7e06f9, 0x77f0bfa1, 0x36dee2bc, 0xed03ac70, 0xe05dd1f6, ++ 0x8dc8c623, 0xd9d99fb1, 0x557818dc, 0x3f21b730, 0x68699ede, 0x18e4a95f, ++ 0x877a27ea, 0xf927ea19, 0x2bf90d0a, 0xda1947f3, 0x0c2b514f, 0x26caabf9, ++ 0x68d7da19, 0xc6bc8635, 0xf4ff7a14, 0x41aed340, 0x1c60b07f, 0x1fd06da3, ++ 0x5786f706, 0xd3d0edb9, 0xdcb4a03e, 0xdebbefe7, 0x9e5bfc0c, 0x1ce6e872, ++ 0xfcf25fc8, 0x60cdebe6, 0x3ff79737, 0xb00e49f4, 0x0ff3c160, 0x1ceffaf0, ++ 0xf21724fa, 0xc2df9fc3, 0xc180afeb, 0xfd7581fa, 0x87d783fc, 0xcc7fce00, ++ 0x015e1609, 0xb3f6be70, 0x8e5197fa, 0xd5c57aff, 0xf8c8e437, 0x764d5dfe, ++ 0x97e7cc3e, 0x5821c139, 0xf67d2d3f, 0xfd8014aa, 0xe9ea2fd8, 0xaf77e19e, ++ 0x9e75dfe0, 0x767aefe5, 0x78efe59e, 0xc44231e2, 0x314dd7db, 0x68fa8a9e, ++ 0x39cd071c, 0x34957ddf, 0xc6007efe, 0xe60ee67d, 0x314c1f71, 0xc62983ee, ++ 0xb8c5307d, 0x8f0b5ccf, 0x718a60fb, 0xb8c72c1f, 0x35afa60f, 0xd1be9469, ++ 0x7b694554, 0x9ed28053, 0xa84fc97b, 0xc899162d, 0x45c56bfd, 0xaad0e57f, ++ 0x0973a0af, 0x9dd373c6, 0x901fae96, 0x7ccb3ebe, 0xeb80bef4, 0x96fd0fb8, ++ 0xd13b52e6, 0xeed5d4b9, 0x797d43b3, 0x9f37cf09, 0x3ca1f76d, 0x53ee3cc4, ++ 0x0adbba77, 0x2f37ae51, 0x4f78aa76, 0x246cf9bb, 0xbca4f913, 0x79e2aade, ++ 0x57577f14, 0xd3a5f12d, 0xf23b43ea, 0x8bf0eba0, 0xaf3a3c62, 0xa32cf3bc, ++ 0x1d3ae9f7, 0x8c453eed, 0xb8c0fd83, 0xcb7fa839, 0xbbd3b16f, 0xeb67cd7a, ++ 0x333f5197, 0x4ae33d9d, 0xcfdae371, 0x2978ee3f, 0x6ebcdc66, 0x1f387718, ++ 0x371867d7, 0x42b9e322, 0x39464fe8, 0xbd56e9d7, 0xbcf5a728, 0xff21eb1f, ++ 0x1c8585a0, 0x22f7a8a9, 0x3c4dea32, 0xd70765b6, 0xa1c4033a, 0x308d8c83, ++ 0x476813c9, 0xbb3b04fb, 0x34cf3af9, 0x7e426e45, 0x68778bf2, 0xaefe56fd, ++ 0xa9253302, 0x29515fb8, 0x3fb8717f, 0x97ef97e4, 0xfbce510a, 0xc86d816d, ++ 0x5ccc4b8f, 0x838f30de, 0xe665d7de, 0x823f05f6, 0xfbd2c776, 0x5620f7ab, ++ 0xbcb2cfbd, 0x697ef862, 0x89fa0155, 0x13bcf0c7, 0x3936777c, 0xe3f901b8, ++ 0x3d7a829a, 0x78fd405e, 0x40ecfaab, 0x85f3be3f, 0x47c8a5a1, 0xcf7cdb57, ++ 0x1ec58780, 0xe255fe78, 0x7c53abcf, 0xf98292a5, 0xabdfe276, 0xe0cf7c33, ++ 0xf4252c11, 0xccfef5ea, 0x405ee07f, 0x7b4664b5, 0x8a98916c, 0x8edc14d7, ++ 0xf55c5bf3, 0xafcf95b1, 0xf6fe8acb, 0x08f85713, 0x310f7d7e, 0x6bb9877a, ++ 0x03bc2b92, 0x56919be6, 0x33fb885f, 0xef47c0ac, 0x74b00e5f, 0x3bfc2325, ++ 0x2defe0bf, 0xa9e4cb40, 0x3f2bfb31, 0x7c272038, 0x39416187, 0xe697a7b7, ++ 0x1e23d739, 0x76ed7896, 0x9d9c0f4a, 0xe6e19b40, 0x479e1e40, 0x566cacd5, ++ 0x5d7d3d22, 0x39d3d739, 0xc724adab, 0x94c27448, 0xe7a624b5, 0xd2f40c43, ++ 0xe0a0dbf6, 0xe00f5e72, 0x26c1d664, 0xa8f33f91, 0xaf686cdf, 0x3d68fb61, ++ 0xfa7c10d3, 0xe2b9bff7, 0xe65747dd, 0x5e90f189, 0xde30b1e6, 0x3bd78d7f, ++ 0xa353a3b9, 0xcf0057e7, 0xdb1c7a8f, 0x3279cf11, 0x9481a7df, 0xd35fb829, ++ 0xfa83c607, 0x84773ffe, 0x769e819b, 0xe73d383a, 0xd3ba7899, 0x935bdbc4, ++ 0xfa97bbf8, 0xa315ed7b, 0x4bcb6783, 0xf5089fa9, 0xac29ef23, 0xdb6a2277, ++ 0x7e3c79c4, 0x976f500e, 0x84907a05, 0x086bb995, 0x365cabe2, 0x8ae78425, ++ 0xa2bf8af2, 0x14d33a7c, 0xe8c7ef62, 0x927d339b, 0xb7f1621b, 0xc677bf04, ++ 0xbe8e377e, 0xdc5fbfd3, 0x4fbd9e30, 0xa211069b, 0x2679c5a3, 0x25f8fd0d, ++ 0xa2497b32, 0xbd3b5af8, 0x777fa5c3, 0x8e2de41c, 0x5fc826f7, 0xb902df4c, ++ 0xed05befb, 0xfe94e9e4, 0xe54829be, 0x53e69a27, 0x4f54d1da, 0x3536efe5, ++ 0x75ed7a50, 0x9fe412ae, 0xb056fba5, 0x7de863f7, 0xd8259b71, 0x5e3f9311, ++ 0x728e9891, 0x5f008e90, 0xd71273c7, 0x8fd7ae5f, 0xbcecf8e1, 0x00979f81, ++ 0xa4a95cba, 0xe8eedb9e, 0xcc41ef14, 0xd3a224d4, 0xef9e4cce, 0xbca16e5f, ++ 0xf15b6266, 0x4f7899fb, 0x35cffb1a, 0x2d7ac7cd, 0x7c7bf795, 0xb1de8988, ++ 0x322bf936, 0x3a5a8f11, 0xf3451794, 0xf5e12fc7, 0xae5e3f5a, 0x3faf57cf, ++ 0x73f0ae5b, 0x9def0270, 0xa0165de2, 0x6f5fea77, 0x3e38e0ff, 0xe1f6f8bf, ++ 0x97f1c4bc, 0x4b7c137f, 0xe8fe817c, 0xa57f7e3c, 0xf8962f87, 0x3a742f88, ++ 0x772fe9d4, 0x3cd7e734, 0x3ef3a09b, 0x7f6afefc, 0x5df085d4, 0xed070cff, ++ 0x345c0257, 0x29de1fdc, 0xe7897e09, 0xce514807, 0xf3a0fceb, 0xfdef4e81, ++ 0x6a6c20f1, 0xe3a31d74, 0xc74f55e8, 0xb775f397, 0x256ebba7, 0x28b01ebc, ++ 0x6346b7a8, 0x65e71ca0, 0x3ae37eea, 0x9774cfe4, 0x95fb630f, 0x89f59c6b, ++ 0xfaffd8e4, 0xcba1e147, 0xa3c07385, 0x3cac1c17, 0x2070aafd, 0x1c728739, ++ 0xdc8137e9, 0xcbae5f9a, 0x2bbf4e2d, 0xd8d9b5ca, 0x30e4a74f, 0xe9df63a3, ++ 0xc8aefc48, 0x43af8d4c, 0x345ca3a7, 0xff62fbfc, 0x38ce74ed, 0xebe9ee5e, ++ 0x8de759e9, 0x5e5fe48c, 0xc78f2f12, 0x18aebeb3, 0xde50d7f9, 0xc64f0a37, ++ 0x7e81fec0, 0xe93916b2, 0x72d9c8fe, 0xfb3ab7ae, 0x91bb507e, 0x632fd745, ++ 0x88f77c39, 0xd07a2649, 0xb94f4bf5, 0x29aacf24, 0x861de830, 0x0bd750f6, ++ 0x88f7e236, 0x29ffcd89, 0xf638f77c, 0xf39fb319, 0xdd43d0ac, 0x784d4bd3, ++ 0x5fcce1be, 0xd23ef49c, 0x275d7e99, 0xb339ded0, 0x17e742d5, 0x04943ef0, ++ 0xf406f77a, 0xd3c8609d, 0x81833fe8, 0xa7f447f1, 0xb6bb4287, 0xded027b3, ++ 0x4c90fa5a, 0x87e4ef47, 0xe916bd3e, 0x160bde69, 0xadafec85, 0x3d208e9b, ++ 0xf92bda9e, 0xb3392ed0, 0xed0f9617, 0x71166f17, 0xfb63c84b, 0x61c9771b, ++ 0x19d5c49f, 0xde3179e9, 0xb9258efb, 0x7f8f9768, 0xc23356e8, 0x8976de7d, ++ 0x17bfb9e1, 0x387cdeb7, 0xb6a7f213, 0x9a2077f1, 0x703bc91d, 0xf5e413fe, ++ 0x7e507ed6, 0xbe5e76d3, 0x23e139c8, 0xd3719f3c, 0x4ee28c93, 0x9171ed37, ++ 0xb36f3c5f, 0x188edde5, 0x36fe63bb, 0x6b017e63, 0x6f4977a3, 0x5f2c69da, ++ 0x31f21bb4, 0xb94f79f2, 0x8c3587b8, 0x66dc5215, 0xe84b8f33, 0x7db7bdf2, ++ 0x69bc221d, 0x66dcb9cb, 0xf4e9cfec, 0x7c2f0bfb, 0x275de03a, 0xfc88d7cf, ++ 0xf8ff903b, 0x1d178e53, 0xd8c44b2e, 0x92b2671f, 0x92e75836, 0xfe0a1c17, ++ 0xfd92c28e, 0xc03325ef, 0x8ea4d2ff, 0x3eff12ef, 0xef682b27, 0x8727ddad, ++ 0x0f8bbe10, 0xf3c31e38, 0x399e4b00, 0xc4f8a56a, 0xaf6465de, 0xd5a1644c, ++ 0x4c4747e8, 0x744ed626, 0x3b256ed4, 0x879aeb46, 0xefd99cfd, 0x580ed050, ++ 0x0e6fdcf2, 0x67f9875f, 0x8eef8624, 0x20eec99e, 0x10f7993a, 0x7fc7e09d, ++ 0xaeefb8d5, 0x788c89d3, 0xa5b73c45, 0x46ef3c50, 0x19e23bc4, 0x0af78ef0, ++ 0x842c87e5, 0xca4f79f7, 0xb5bcdf54, 0x4fed8ad9, 0x757e3985, 0x1b904fbc, ++ 0x3d37cf09, 0xfe39f1ca, 0xe0b7c7a1, 0x9ef3c23b, 0xfe3d90b4, 0x8fd77c22, ++ 0x03a0677f, 0xffbc0beb, 0xf7f38f33, 0x60e87b2a, 0x0e87adbf, 0xa2179e70, ++ 0xd253e003, 0x83a217fb, 0xef8ce535, 0x9c5fc843, 0x70ed047a, 0x2de29597, ++ 0xe846effa, 0x77d113bf, 0xf197f1e1, 0xdec1e17d, 0xaeeec9a7, 0xe2d3fd4d, ++ 0x9f7e8c65, 0xb728afe4, 0x7d7a4c4e, 0xd8efa215, 0xd2171fe4, 0xc74b0d3d, ++ 0xfc520fe3, 0x3c8a8fa1, 0xb35399dc, 0xc39f7f0d, 0x80f9fa9f, 0xa58eb03d, ++ 0x7429b33f, 0xa9b470e6, 0x73c37ec7, 0xc7198b9f, 0xce9de003, 0x603e2e63, ++ 0xf63af7e3, 0x7eb16a56, 0xa7266768, 0x576b4af3, 0x188dc62d, 0x48e387f4, ++ 0x174ff71a, 0xdfbfe01e, 0x0b93fba0, 0xd871dff5, 0x4f1f7c6d, 0x76a75e52, ++ 0x1e3cd1be, 0xb4632832, 0xe6f2ed0f, 0x34982c19, 0x82fa7ce8, 0x5479f79f, ++ 0xb4e745f8, 0x37a1cf27, 0x85923b74, 0x12c1dee2, 0x1e46eb72, 0xdf2f61fb, ++ 0xe319aaf6, 0x253b9d9a, 0x0382cbc2, 0xb83caf20, 0xc8316e5f, 0xfda2259d, ++ 0xc97f4807, 0xfd6ecef8, 0x563926b3, 0x8fdefcbe, 0x927a2cfd, 0xe904b3f7, ++ 0x91bee28a, 0xdfd0492d, 0xed0b36e9, 0x84c4de73, 0x52e7d9bc, 0x2f581ef1, ++ 0xfb73b2f9, 0xe3df346a, 0xd8216ae9, 0x7888b899, 0xd7b25afa, 0xdd1b4ed8, ++ 0xc52e7723, 0x8d579ffb, 0x40fee267, 0x0a9dc448, 0xecdfd052, 0xe414be66, ++ 0x287d1eef, 0x4398e319, 0xc7cb02b7, 0x6c2c3bf4, 0x22507be7, 0x8a5d9dff, ++ 0x9b697f21, 0xb2fed0d7, 0x7d433e7d, 0x50df2461, 0x35447c5f, 0xcbdb4be4, ++ 0xbe47ed0c, 0xa3f219a5, 0xed0caa3a, 0x6030f8af, 0xc01777c8, 0x0fb3ce7a, ++ 0x192bd132, 0x39f24fda, 0x995ffd0c, 0xbbe436ef, 0xc23e029d, 0xdfedd4ce, ++ 0x7db9a325, 0xf0ea9f14, 0xc71aa29d, 0xabf6fdd1, 0xd5e38cca, 0x2ef1c668, ++ 0x8ef82f16, 0xd84419bb, 0x98b7d02e, 0x7804d53e, 0x77623f00, 0x3ff29793, ++ 0xda51f269, 0xe54f94d6, 0x29526d3f, 0x8ca9b7bf, 0x5f82cff2, 0xe07df982, ++ 0x1cfa60a7, 0x7e5827f8, 0x161df821, 0xe3111ee3, 0xfdc62abe, 0x4d7a70ba, ++ 0xe886f7f4, 0xc793df0f, 0x5c5faf54, 0x0cfa6a55, 0x8fd4bfed, 0xd13f18ac, ++ 0xc04c7796, 0x2bd74638, 0x7c01db32, 0x23e182c3, 0x6fd41e4d, 0x8c0f7469, ++ 0x697eba05, 0x8333fcc2, 0xb9e73c14, 0xdeafdf76, 0x7b33fac0, 0x1cd78a65, ++ 0x325ef7da, 0xb3fa73f6, 0x4b71b43e, 0x8bf2117a, 0x7f28973e, 0x3ee3d40f, ++ 0xb23da4e7, 0x8dbb1f78, 0x3ce9ddf4, 0xe2b61f3d, 0xf760653e, 0x7bff7a1e, ++ 0x543daee1, 0xb5f00aff, 0x76d77ea1, 0xed82bd43, 0x0e685d21, 0x8fe15c53, ++ 0x22fef4fb, 0x9e517ed4, 0xfeb8f744, 0xd5c5ebb8, 0xde3ea057, 0xfb869753, ++ 0x1f770b5f, 0x1e739f4d, 0xecfc7c7c, 0x0f500b8f, 0x8b2fde2c, 0xbfbcb373, ++ 0x222dfbc5, 0x28bfe7cf, 0x5484cf6f, 0x25bb1c54, 0x9a7ebbba, 0xd5b9d2b5, ++ 0x5f1efb85, 0x61767284, 0x8a1675fe, 0x22c9b57f, 0x5fdfc1de, 0x6e30a45b, ++ 0x927db5d7, 0x3fc5fb8c, 0xbbf97b6f, 0xc0f7e21a, 0xa0af748b, 0xf06caf73, ++ 0xcd1cdea7, 0x4737e5ed, 0xf4efff73, 0xf19317de, 0xb6daf07e, 0xcddc3917, ++ 0x21ff5a11, 0x9484ef91, 0xa64fbde0, 0x4cf82ff5, 0xfde83c26, 0x05c7049d, ++ 0x6fb49bfb, 0x75d70bb0, 0xf78f8dac, 0x7a0fa811, 0x6eaf2847, 0x55ffce2e, ++ 0x99528cef, 0xfbd393ef, 0x5c979de4, 0xd9ca38f9, 0x96b26d85, 0xabfbdfc8, ++ 0xd8b0f7e8, 0xef2579b7, 0x00fdc3e9, 0xa556afee, 0xf79ec615, 0x33f844ff, ++ 0x3cc1ac13, 0x9cc723d4, 0x9c3dfa3e, 0xb906abbb, 0x3087bf10, 0xc7aaf2c5, ++ 0xa6e95f68, 0x63bc7cbd, 0xd2327b4a, 0xc5bdb1dd, 0x3f662872, 0x371c63e7, ++ 0x78a3fe86, 0xe69e110b, 0x3ed3b787, 0xbc7f147a, 0x0ad1a3fc, 0x7c357fb5, ++ 0xb3b45af4, 0x21f7e58e, 0x95b0e4fb, 0x70bd7f91, 0x8f93b737, 0x3dbfe81d, ++ 0x23f63f76, 0xf99d6fc1, 0x99c61cfc, 0xeed1167d, 0xa199c7ba, 0x4fdff71d, ++ 0x47ce34ef, 0x01b3bf09, 0x8f45f3ed, 0xe156f4ca, 0x3a7d4b22, 0x6d83ffae, ++ 0x17cdf9c6, 0x89645e70, 0xd0c7a7a4, 0x3dfda2eb, 0x3a24e37c, 0x89f3afdf, ++ 0xe3a9f08f, 0xccbe58f1, 0xd1b5e5e7, 0x7b45c37d, 0xeeba271e, 0xf1e25f1d, ++ 0xdbb7fedb, 0x5d2f8a55, 0xedd69fc0, 0x8b7f1886, 0xa968ffa1, 0xf78a541a, ++ 0xe0fb7587, 0xe0dad1d6, 0x0fd17d31, 0x799f900b, 0x0b7d818c, 0xfb462e63, ++ 0xf2e5053a, 0xb8e0b7ef, 0x742d7bdd, 0x7db1616e, 0x007f4dff, 0x8156ed3a, ++ 0xddde6051, 0x143ef8db, 0x9da323ee, 0xb9d84f3b, 0x2382f81f, 0xc5835df0, ++ 0xbeb44c2b, 0xb0e5bb45, 0x51e30723, 0xbc7dee5c, 0xa42ae727, 0x644745d7, ++ 0xf1a3fd05, 0x95f7396d, 0x277e9097, 0x1b49757b, 0xec9793b7, 0xd62ec892, ++ 0xc2c590ed, 0xec25390e, 0xba2b53e0, 0x82fc7db8, 0xbb4136c4, 0x8f604975, ++ 0x1717bcc0, 0x76bb264c, 0x757ebcb1, 0x0f9e1f7f, 0x0b0dda34, 0x77a41c0e, ++ 0x31cec040, 0x65dc2f94, 0x336e2fcc, 0x717f75e6, 0x2fb118ca, 0x430d8c3d, ++ 0x2e52a6ff, 0x987e40cf, 0x55e3863d, 0xbe6e77f7, 0xbe40cd54, 0x4df66b5f, ++ 0x0812e3d6, 0x3c2fa5af, 0x1de700bd, 0x92a4945e, 0x3cf0d1ff, 0xcff3b5c1, ++ 0xc4e9afdc, 0x67e438bd, 0xb9dbe1c6, 0x52f9d38f, 0x8bc6148b, 0x57514bb2, ++ 0x29767f60, 0xcee302bc, 0x9264eea1, 0xc3bce24f, 0x7fdc19f2, 0xed1e7745, ++ 0x4463a1c2, 0xaf4e2adc, 0xc877318e, 0x713918ee, 0x9a5c98fb, 0xcfcadfbf, ++ 0x52ecdf6b, 0xb40dbf49, 0xa07d7b73, 0x03ebdb9d, 0xe82b5dcd, 0x49fb24f7, ++ 0xf8639f7c, 0xb07fb473, 0xf693896e, 0x9d6f2417, 0xaeb1e119, 0x6f9d1d5f, ++ 0xe5b4a819, 0xe7a75fa3, 0x105f58fd, 0x38260fb5, 0x671c6683, 0xf624a667, ++ 0xad3eb811, 0x77162b31, 0x6c657e8c, 0xe7d7b505, 0xf1bfbfa7, 0x029f9f4f, ++ 0xe74673f3, 0xc14ef807, 0x51293fef, 0x50186ec9, 0xe49c3a03, 0x7635bd42, ++ 0xd034f73f, 0x45701fbb, 0xdd022b6f, 0x9076da2c, 0xacc5cbfc, 0x377e357d, ++ 0x63af9921, 0x5fbf9582, 0xa789213a, 0xf2e18c8f, 0x4d22f7eb, 0xec192b1b, ++ 0xd58fefd8, 0xfc818db6, 0x1f81b1a8, 0xd6bb218e, 0x9377f0c9, 0x932ebf96, ++ 0xf72f175f, 0xe9e89ca1, 0x9443e013, 0x4bd7d77f, 0x73825e4a, 0x51794b1d, ++ 0x7c2d1f0f, 0x13e231fd, 0x7ceefcfd, 0xa4bbc4c6, 0x862f250e, 0xbf22962f, ++ 0x801fbda1, 0x9c6046ff, 0xaf9bff80, 0x24f3a02c, 0x057486c1, 0xf2a5bafd, ++ 0xf897da69, 0x74b77caa, 0x711f319f, 0xb88ffa70, 0x7e93f224, 0xeec7a63e, ++ 0x201c7e27, 0x907b63f8, 0xf6ca6eff, 0x9e3ccc2f, 0xf8a25337, 0x6c2834dd, ++ 0xc4931548, 0xe82bf376, 0xc634e45e, 0xcdb3a88f, 0x82bfbe1e, 0xa99eb095, ++ 0xccd3dd62, 0x57288391, 0xe5b4b65e, 0xe5e93c60, 0xfb1576c5, 0x377e219f, ++ 0xbdf8a66d, 0x967de3b4, 0xcea1133c, 0x7748d943, 0x28da09bf, 0xe57db59e, ++ 0x71177a0e, 0xe0a95b38, 0x6280227e, 0x17c597d7, 0xbfa8efbf, 0x72f60323, ++ 0xe027d206, 0xffe204ff, 0xb78dc043, 0x0bf7f7a8, 0xfd0cfd7f, 0x6e9fc6ee, ++ 0xbc5afa79, 0xeb13751f, 0xa6ea3f22, 0x3bf415fa, 0xed4e401e, 0x78a223f9, ++ 0xe3aef1d5, 0x3eaf07ad, 0xaf162ff8, 0x84d47e1e, 0x486ba7c9, 0xa650fd2e, ++ 0xc21750f3, 0xb1f70eab, 0xee373f02, 0x1e2bf2e7, 0xbe1e3adf, 0x374bbf87, ++ 0x36eef488, 0x91b313c2, 0x87a78cbc, 0x080be10b, 0x8d562673, 0x0fc8d8f7, ++ 0xf2e26fed, 0x893cffb4, 0xb1d795e2, 0x901d0be0, 0xf7e7db5e, 0x954f7e16, ++ 0xc0a66de3, 0x78586fdb, 0xfeffbe0a, 0xfbede14d, 0x63e90363, 0x3c6df013, ++ 0x2f8b9e9f, 0xffd4f917, 0x9865f5d2, 0x188fefd1, 0x5f8e39f9, 0xc2a8f07b, ++ 0x0c78317f, 0x5f132436, 0xde5be0f6, 0x117a717d, 0xd638c0ff, 0xef8c293e, ++ 0x5f905fde, 0xe0085825, 0x51ac64b3, 0xd378ea6f, 0xb8ae72e1, 0xf22cdbe0, ++ 0xbed122b2, 0xdbe3e70a, 0x4d1f746c, 0xf7d157df, 0x390aa64f, 0x0dbe9f19, ++ 0x57ee12f6, 0x8c7f93dd, 0x6e3945de, 0xfbe1fbd5, 0x68af6fbf, 0xddf7c6cf, ++ 0xe9e0aedf, 0xddff2b71, 0x25af3d51, 0xdbe4b8f1, 0xc210b699, 0xd8696de9, ++ 0x6f33d438, 0x977fb74b, 0x3eac33e7, 0x18c8cfcc, 0x8ecdf787, 0xe638f45b, ++ 0x876e42dd, 0x8c663cf9, 0x893b53f4, 0xf0f084bd, 0xe3402c49, 0x156a5248, ++ 0x5bede7cc, 0xfee11707, 0xc6becf44, 0x57876e58, 0xa07ae58c, 0x877fee27, ++ 0x59ff7144, 0x7f709aa8, 0x5583dc62, 0xe27e50b9, 0xb48541ce, 0x38dcba6f, ++ 0x1cfdea3e, 0xa46e978a, 0xd67cc67e, 0xd18ba965, 0xd6fa3d6f, 0xcf97967f, ++ 0x9d21352d, 0xd43817cc, 0xff718752, 0x05283c3c, 0xcfae97f5, 0xed3c8fba, ++ 0x7ee78d8c, 0x3ddfe224, 0x0ef761f9, 0x0787d588, 0x0437589f, 0x0d6f99fb, ++ 0xfca1570d, 0x0c8fedc3, 0xfe65bb40, 0x90866b13, 0xdac4fd3d, 0xcd17e821, ++ 0x886eb1df, 0x413ef946, 0x7ccccbf2, 0xf7fa7fdd, 0x507e7451, 0xc155cfef, ++ 0xf6998afd, 0xb7a89583, 0xe3e77f27, 0x307fb855, 0xe2894ef8, 0xf6b3d77f, ++ 0x6b67a855, 0xb15f39f3, 0xff9276cd, 0xd7ed1fd0, 0x0a6c3e3e, 0x6af687bd, ++ 0xb9967bfe, 0x7c61eed0, 0xbe2fb588, 0x8f5e1dbf, 0x16b2c4ef, 0xd17ee289, ++ 0xffb4d9f6, 0xb252b75b, 0xd75313e2, 0x9ee9bbd7, 0xdd63c3e2, 0x2dd9c704, ++ 0xbcb18785, 0x4f9791b6, 0x1ef785b6, 0xb41e7ec3, 0x904f39d2, 0xf7b1b943, ++ 0x6b1e1fdf, 0xae6eefe5, 0xd08fc897, 0x25bc19c7, 0x3aec7b7d, 0x67f8161f, ++ 0x7c93bfa1, 0xa5e04abb, 0x4be8f1ba, 0xe94a7bf8, 0xe5186096, 0x9c0f1bc9, ++ 0x8c308bca, 0xe7447e83, 0x835b070e, 0x75c02f0f, 0x9c51b0ef, 0x7f7864b4, ++ 0x17da0339, 0x09b152dd, 0x758d59d3, 0x39402f0f, 0xc85ed5bc, 0xf9f2578f, ++ 0x1354972d, 0xb717e9ca, 0xc2366f7f, 0xf807c3ed, 0xdf2f86ef, 0x2583343e, ++ 0xfd3d53e0, 0x371fe011, 0xb26c9e34, 0x26e3fa53, 0x84d5e185, 0x52f26f7f, ++ 0x7c9a3ffe, 0x9ce9b294, 0xcfdff4be, 0xc57f573d, 0x3e61f59f, 0x5a4b8bb0, ++ 0x8c57cc1c, 0xe7b4a4e7, 0x06bc02c7, 0xc778b25f, 0x3c2eb15a, 0xca18567f, ++ 0x28708f19, 0x7e8cbb59, 0xa847eb47, 0xbf1e0060, 0x0032d63c, 0x8d8df585, ++ 0x7f00fcef, 0x6c7baf8f, 0xdefc25e0, 0xc52cedbe, 0xbfdc5e29, 0x3de116a6, ++ 0x973f077f, 0xc3fbafad, 0x3c648607, 0x57e5f18c, 0x5837142c, 0x1f9dedba, ++ 0xce7485ac, 0xdf8665fa, 0xf5d8bb5b, 0xb9f3121e, 0x0b9d5f10, 0xaf9d5f0e, ++ 0xfe200dd6, 0x557c01d9, 0x6af9f5f0, 0x820ae369, 0xfc0b579f, 0x43ebe909, ++ 0xf200684b, 0x46c387d3, 0x5e879d13, 0xbafe0890, 0x9f99ef1c, 0x5342ef58, ++ 0x9cf2fadb, 0x94ff1ca8, 0x0f7c1095, 0x0860ffee, 0xee9fcfda, 0x75de719b, ++ 0x8eeb0b3f, 0x9d78c50c, 0xfaf8d29d, 0x20e0d611, 0xe237d615, 0xffffef1c, ++ 0x18a4006f, 0x008000fe, 0x00000000, 0x00088b1f, 0x00000000, 0x5aa5ff00, ++ 0x559c500b, 0xffffbe96, 0x6e8683f7, 0x3cd00868, 0x0849d212, 0x93b048c1, ++ 0x24d1c640, 0x4863cd36, 0xb125d998, 0x24464dd6, 0x3678628d, 0x6cadd460, ++ 0x12345acd, 0x053a8359, 0x31f1ab2b, 0xf89224da, 0x0d1db320, 0x3da24491, ++ 0xa366c359, 0x44aa616b, 0xd52a6ab7, 0x9091d66a, 0x763e09a5, 0xe7ba89ac, ++ 0xd2dfff3b, 0x7667504d, 0x3ede3353, 0xb9ee71f7, 0x9df39ee7, 0x02cfcf73, ++ 0x8a442ca7, 0x86637fa0, 0x7fe08b4a, 0xcd10aa52, 0x11e14fea, 0x44909bc2, ++ 0x881488f4, 0xf87a27cd, 0x78ba1367, 0xf892fd6a, 0xf39d4628, 0xa3f736ad, ++ 0xe8568d5c, 0xd377f8ff, 0x80b6de5f, 0xf17072cf, 0xc4285109, 0x45903e4f, ++ 0x9f767720, 0x4563069f, 0x12df6220, 0xf3fb7083, 0x19f507e8, 0x3a98840a, ++ 0xbddfde9e, 0xfd1d6884, 0x35f4192f, 0x184f41fb, 0xc7e30fa8, 0x12c75f24, ++ 0x6eb2bd75, 0xc7139cf6, 0x799df327, 0xe5b79f57, 0xa08e64c4, 0x7fe1e6fe, ++ 0xf9f12cbc, 0xf2e84d37, 0xbffcfc7f, 0x1f99383b, 0x7d5f1334, 0xd6959d70, ++ 0xf982194f, 0x5e5b6a0e, 0xfb0b2a7b, 0x087aa5fc, 0x483c37f7, 0xe34b5907, ++ 0x9bbc8c52, 0x2e552ce4, 0x5ce1263d, 0x48c2f467, 0x7e396ae7, 0x3a39e8e0, ++ 0x9c48ccf7, 0x6885d843, 0x6ccac795, 0xf6dfc912, 0xe88da8e1, 0x82473499, ++ 0x9dfcccd5, 0x65fadbd0, 0xf4254762, 0xdace9ba7, 0x9b884ab2, 0xd8850f61, ++ 0x4fdb83b7, 0xafb085db, 0xb37f1f00, 0x3f22be20, 0xbf100c4e, 0xdc31ed8b, ++ 0x497bbd5f, 0x7ff51a57, 0x43594bea, 0xe56f16c7, 0x7a05a9ff, 0xce237a6e, ++ 0x9e812caa, 0xfee237a8, 0x4f873bbe, 0xfd08ce11, 0x271f3d35, 0x5af3119c, ++ 0xc6bff60d, 0x1567ad7e, 0x5afda5e1, 0xc5186e57, 0xe484e23e, 0xf0e74e58, ++ 0x219df9ec, 0x4ddf822d, 0xc766bd4e, 0xe6f72c3d, 0x2594fe37, 0x0dae28e8, ++ 0x449cdbce, 0xcc4c91c7, 0x27c12d2f, 0xba3cda49, 0x064d16ff, 0x8ea488f3, ++ 0xde3c2b97, 0x7488ac3a, 0xf8b349ac, 0xca39d396, 0x2c4e8f45, 0xbfc2be23, ++ 0xbaa0e05e, 0xa46fafe0, 0x94378af1, 0x0644ddb5, 0xd247a44c, 0x3bac596b, ++ 0x73e9177b, 0xbd34965c, 0xd7a00bfa, 0x394f9cb0, 0xbd739625, 0xdfb13922, ++ 0x6f9c7a74, 0xda6d753f, 0xbc82a9e6, 0x651b79e1, 0xa9f11e75, 0x4df6fb67, ++ 0x7f816fe7, 0xb7f3a606, 0xdde7665a, 0x9b5c46f2, 0x5fc2e30f, 0x3ec44b70, ++ 0xaf034e83, 0x215b6cff, 0x17eb49db, 0x0eb8af66, 0x31e572f6, 0x75ddf689, ++ 0x0245ec92, 0xcbef25ff, 0xe92f0e74, 0x493af719, 0x1234eaf7, 0x3a70b73b, ++ 0x52ab3fe1, 0xd69ff07c, 0x15d092c3, 0xfb8cbec0, 0x8b5e6863, 0x7b0a983e, ++ 0x9efc3bde, 0x3adcf601, 0xbec1aef4, 0xc8e9eb0a, 0x2313c87a, 0x56adbf43, ++ 0x1afb89fa, 0xadfef15e, 0x4673cfc4, 0xf7457151, 0x3fc041ae, 0x6bf63e68, ++ 0x0ca47a3a, 0x7408b374, 0x079b3ec1, 0x2666eda3, 0x9d609ecd, 0x9d066fc7, ++ 0xd8ff28f6, 0x8ff54fb4, 0xe6d1145b, 0x2772f337, 0x9a5371ec, 0x8a5bbfad, ++ 0x3af1275c, 0x80f932a7, 0x2d0ae48d, 0xb1121c95, 0xf77ac50a, 0x1c8fa158, ++ 0x8b403ac9, 0x54bfaf43, 0xc5f193b0, 0x9d337057, 0x7c10642f, 0xec1e9b1f, ++ 0xf21129d5, 0x9c511a6c, 0xac5087b8, 0xf7c63fa8, 0xfb885eee, 0xe5437c78, ++ 0x217f616f, 0x373bf4c3, 0x992196d2, 0x3eaf9bd6, 0x2aa36d87, 0x353259cf, ++ 0xee4d6fbe, 0x154ccc8a, 0xed8f84cf, 0xf7565468, 0x8a753727, 0x75ebb335, ++ 0x52faea45, 0xa416cf25, 0xc3925df1, 0x9f679d66, 0xf4907b70, 0xf4f74b5e, ++ 0xda37dd3c, 0xa2addb17, 0xb066f096, 0xdfe98d3d, 0xf5b9dbb6, 0xff72e7b7, ++ 0xa60eedcb, 0xcf5fb68f, 0x2776b1f4, 0xe5edc3d3, 0xaf689edc, 0x10b3fee4, ++ 0xa7fc06f5, 0x18bb07d9, 0xcc65af85, 0x7349e3d2, 0xf9e88ce8, 0x345249e3, ++ 0xfcf1219d, 0xcfb36771, 0x06d1744b, 0x764f86ab, 0x63e9254b, 0x5f3e3622, ++ 0x9b210824, 0xa677bfdd, 0x09f2ce80, 0x969f4f8a, 0xfe0c7a3f, 0xbdb49254, ++ 0x93367e0a, 0xa3c0146c, 0x8fee4505, 0x99ccef31, 0xc65eece2, 0x48c39349, ++ 0xcbfe3ef7, 0xefa0136b, 0x422bbfd0, 0x728b2da1, 0x2029eed7, 0xb12cc8ba, ++ 0x5c5e12fd, 0xb1714957, 0x4f893f15, 0x814d48f1, 0xeb07c54e, 0x6f7a0972, ++ 0xbb3ec5ae, 0x816b4dd2, 0x746d0fc3, 0xec23394f, 0x2ea32cb2, 0xe87d0ddb, ++ 0x34cbefed, 0x7a1ffbcf, 0xeef34031, 0xeca238b6, 0xa2c6cb7a, 0x536f902b, ++ 0x6b3db2ee, 0x0d9c9fc0, 0x3cee4778, 0x729cf908, 0xf8c9d49c, 0x0f01d765, ++ 0xec7668ae, 0x7f6c4bb2, 0x975d8301, 0xb103fc44, 0x5a5ec945, 0xf3ddaa37, ++ 0xcf9eed19, 0x36fcf76a, 0xfb5097f5, 0x1da3f50e, 0x97b47ea3, 0xd5fa6bd7, ++ 0xbf40e74d, 0x1a56713f, 0xd3df588a, 0x7a43a059, 0xb7f60db1, 0xe2a5fe19, ++ 0x86f2164e, 0x4f7ecd6c, 0xada87700, 0xa2d2a9bb, 0x9f33f3ae, 0xb269c426, ++ 0x8fac49c7, 0xbaf0cbb0, 0xdb82f5d9, 0x6f09d7ad, 0x55fef00c, 0x127a0f93, ++ 0x212f290b, 0x36abeb7a, 0x662523c6, 0xf205e572, 0x056badf3, 0xc578a8e3, ++ 0xb34bcea8, 0x484fc217, 0x94cfbc47, 0xc9eaf64f, 0x63493c3e, 0xc3884939, ++ 0xe9857f9a, 0x8c28df63, 0x44359edb, 0xa49afb53, 0x75b3cf9e, 0xeb11272c, ++ 0xfb0c9325, 0xc757ecf2, 0xe7fe69cf, 0xd3f1aa59, 0xfc6223ce, 0xd08fb859, ++ 0x6eb357c9, 0x1cdbba27, 0x7fe2a9d8, 0x5b718720, 0x02b67204, 0x79ff251f, ++ 0x72c210e1, 0xfba35f4a, 0x7fe1f429, 0x29e27406, 0x474b4aa3, 0xc7235bce, ++ 0x9259fc53, 0xa341b415, 0xe8933c8f, 0x2ff5a088, 0xe1b8c79f, 0x094d637e, ++ 0xdf4615d1, 0xcdd87699, 0x65f6a8bf, 0x09f43c3a, 0xdc74d6f4, 0xeb81f9c8, ++ 0x97a5d0f0, 0x2c879f11, 0x457cc00e, 0x77d612d1, 0x0f43f1e7, 0x8ea6dec3, ++ 0xba1fd9e8, 0xe67bdf07, 0x28cf3c57, 0x46156e60, 0x7da0817f, 0xb80d4f52, ++ 0xc744e975, 0xbd073ff9, 0x72c495c2, 0xfd502c54, 0x5295cf3a, 0x86de85e3, ++ 0xfc1dff0e, 0x784122af, 0x25e2b761, 0xd46247ba, 0x2535caf8, 0x29a7f282, ++ 0xf83558cb, 0x7468bcb7, 0x5f1b4ec0, 0xb7e0b9b1, 0x72968adb, 0xd9586adc, ++ 0x2b788593, 0xe0e1789f, 0xcf3192af, 0x6b6f2024, 0x35ef9a92, 0xeeebfd2a, ++ 0x703bfbe2, 0xfdc829f0, 0x27ec4982, 0x03c40d3e, 0x5c1c35fb, 0xd1d2f3ee, ++ 0xe3fafb5e, 0xa943dc6a, 0xf441f4f2, 0x499cfe7f, 0x19ce1e86, 0xe01b099c, ++ 0x8ef4e787, 0xe8d3ac01, 0xaa05f186, 0x32c1713c, 0x9ee4bfbe, 0xc6dbc42c, ++ 0x57ff7f05, 0xe942bb90, 0x9c49e679, 0x205190e7, 0x40bc4c3e, 0x1375a37a, ++ 0xb835fa03, 0x2c17a9e5, 0xa4cbd83a, 0x24fd53d4, 0xf3a80ff8, 0xac3d4d26, ++ 0x0ac0ef4f, 0x9e68fd81, 0x949e3c40, 0x27faa37a, 0xbbe50e06, 0x5f177f49, ++ 0x4773c8ac, 0x5fd86fd8, 0x46339f1a, 0x024645c5, 0xed46a5c2, 0x857ab0b7, ++ 0x836ee299, 0xf63c5e46, 0x6293d4c4, 0x41c5fd76, 0x3a40c07d, 0x3d8a306a, ++ 0xfeb34931, 0xb3f998d0, 0x51af9c72, 0xfe41cfee, 0x5836b0d2, 0x3098bf0d, ++ 0x9a349889, 0xb71696f7, 0x6c768f1a, 0x7dfc1e41, 0x716bf4f2, 0x35348be8, ++ 0x6c317d7e, 0xefa579f2, 0x6fbf438f, 0x97b7d617, 0xb5b7d2cf, 0x0f973919, ++ 0xe0cb7bf3, 0x5f20766f, 0xe3f1524d, 0x241fcd3c, 0x48b67b1c, 0xec768fcd, ++ 0x57df9e8e, 0x2dfdc494, 0xe20e6086, 0x6f7f985f, 0x82d71851, 0xb9abc039, ++ 0x96902aeb, 0x925e4700, 0x8f1a4718, 0xf12a1f4a, 0x67534a9a, 0xe318d9f5, ++ 0xf3f929f5, 0x3ada43df, 0xd7881eed, 0x57ea972a, 0xa726838d, 0xc534f889, ++ 0x2f91e306, 0xf1825b35, 0x4ea683c8, 0x76bf6228, 0xfe61c97d, 0xabf7674b, ++ 0xf7ea11e7, 0xf9a69deb, 0x08e3a3f6, 0xdf87579a, 0x6b970aa4, 0x3f57ef29, ++ 0x09fbc71c, 0xec1d706b, 0xe8e9feb6, 0x35a73875, 0x86a71fc2, 0x23baa40f, ++ 0x86a8cfe2, 0x43e92107, 0xd7d09bf6, 0x0ec1651f, 0x47b1651a, 0xa45ed522, ++ 0xa624a635, 0x7b4a8c45, 0x8df9644d, 0x61639a5f, 0x68bf173f, 0x929e3f66, ++ 0xf7738c82, 0xf8c65a9c, 0x320fa530, 0xaeb835ce, 0x4c7e01a9, 0x81ab0625, ++ 0x6eb8f75b, 0x83d3c750, 0xdf1a76d5, 0x8be31a0a, 0xf701e704, 0x9e32729f, ++ 0x6fd32854, 0x038a6e21, 0x24fc2b7a, 0x4d3aefac, 0x383c424f, 0x10efcede, ++ 0xa1f11dbd, 0x796925d3, 0xfcf66182, 0x4d3facca, 0xa3e1fb09, 0xb37acff0, ++ 0x7d478063, 0x0f232f83, 0xe8ea9edc, 0x37ad5fb6, 0x2672439e, 0x13b57d27, ++ 0x7165d4f7, 0x79be224f, 0xcefc82f2, 0x38e76b20, 0x91baf2d4, 0xfd219bdf, ++ 0xd7e041f4, 0x843b8b76, 0xb186cd79, 0xe91202ae, 0x8a383e92, 0xec337ed4, ++ 0xb544718d, 0x03bca9b7, 0x47d3e606, 0x7ff3a54a, 0xa083ddab, 0xec3f4e47, ++ 0xf9ef5243, 0x795f875f, 0x3533781b, 0x7a718cb6, 0x0c4d3fae, 0xdc0f1a3f, ++ 0xbbe280f8, 0xff6cc577, 0x0c873507, 0x7cf6dfe8, 0xd2ef01bf, 0x9f44f7db, ++ 0xcdcae66f, 0x0f142efc, 0x1ec3f447, 0xb9e9a2fb, 0x065d817a, 0xcbc0fca2, ++ 0xfc0377fe, 0xd726da8d, 0xf0f40b58, 0x6895bd1d, 0x353e8225, 0x5f339e87, ++ 0xc3f9aa54, 0xf582450d, 0x3028bcd1, 0xc3f8efce, 0xef7c017a, 0xf4c6b8a4, ++ 0xef0f9c50, 0xc530f919, 0x6e3564ad, 0xc5345e21, 0x5ee3558f, 0x568c86a6, ++ 0xf8ffbfcc, 0x7e70b21f, 0x9c2cc7b2, 0xabf8e9b7, 0x57df78a9, 0x3f79d914, ++ 0x18a98f8a, 0x9e3a1a6f, 0xb848f78a, 0xe7f659bf, 0x94ca2e40, 0xe11f81f2, ++ 0xc8128f7e, 0xd24dfc81, 0x2bc63e58, 0x659bb934, 0x9ad015a2, 0xf7ea92dc, ++ 0x38c2b8e2, 0x36def73f, 0xf84af66a, 0xf07c8f90, 0xfd6a13fe, 0x0d078c20, ++ 0x429cae1a, 0xffea9e7f, 0x4e1a75d6, 0xf806d2d0, 0x31383cfd, 0xd13dc612, ++ 0x1b9df5c6, 0xe1dcaa5c, 0xdf97ccf5, 0x6f1e5e17, 0x7f326d79, 0xd9d61e69, ++ 0x781175b5, 0x5f166cb4, 0x8c690380, 0x53ebf703, 0xcf8d5ce9, 0x5a4e8e48, ++ 0x51d550d2, 0x9d45d346, 0xe832aeee, 0xf9785eb5, 0xae57373d, 0x1ef476b9, ++ 0x7e0294f4, 0xf1bc3bea, 0x24ebe4a0, 0xd6122eb9, 0xbc61ada7, 0xea7f0009, ++ 0xe0ca3a4a, 0x7b26777f, 0xe5ef910c, 0xb3bfe31f, 0x6bae9a2f, 0xcdb328eb, ++ 0xbb8de7e3, 0xc453477b, 0xdc1afcd5, 0xf6a965fd, 0x72c3fbab, 0xe585345f, ++ 0x2253e974, 0xa3adb1f5, 0xbada852c, 0x3eabff98, 0x3c5f73d4, 0xee200c6e, ++ 0x380d7e92, 0xb63fc6ff, 0xfb712219, 0x0835f8c7, 0xc975995f, 0xb73fcbf7, ++ 0xe302966d, 0xf2092ba8, 0x33f601af, 0xfd889bf2, 0xa9cd17ce, 0x2cd7d44f, ++ 0xdc2dde46, 0xeb238b35, 0x025b7313, 0x7af90cca, 0xc96e37b6, 0xf31dab0f, ++ 0xff3c23e8, 0x76c29721, 0xabf35e78, 0x27a68a8c, 0xd75c165e, 0x7a22e7d9, ++ 0xfe732283, 0x7e9f773e, 0x52c69fcd, 0x9ec2f72d, 0x2b7a2342, 0xa28364fc, ++ 0x9e5333ea, 0x98fe0779, 0x77b16a99, 0xe2d2bf12, 0x49de7538, 0x9ff51593, ++ 0xb2afc9d0, 0xf437c49c, 0xd71b7980, 0x91667457, 0x69a3e34e, 0xbfdf18ab, ++ 0xab153bab, 0xa815c4fb, 0xae6b4ef9, 0x4beb87fe, 0xeaef9679, 0xe46f9c4b, ++ 0x7396f9c5, 0xe38cfe1c, 0xd0a4685b, 0xef81d8aa, 0xadfc333e, 0x49ffebf5, ++ 0x1a9e1c45, 0x3b78aff9, 0x1fcaeb70, 0x7b3f61e2, 0x078e3f87, 0x5e1a9c3e, ++ 0x6e7b4166, 0x7f416ecc, 0x32e3fca8, 0xdad6ebcc, 0x5a82fad9, 0xe1b70b1f, ++ 0x8eb87377, 0xd3377e10, 0xf434fa3b, 0xfbdd603a, 0x439202eb, 0x03acf4c4, ++ 0x3a3bd02e, 0xb663f109, 0xcdb760be, 0xac898f57, 0x572f642f, 0x51680beb, ++ 0xabd6c85f, 0xa8d005f5, 0x7d45a02f, 0x2fa8fd01, 0x017d4680, 0xa00bea34, ++ 0x8b405f51, 0x3ffa02fa, 0xe48b3d47, 0xa6f2510d, 0x8ccd3fd6, 0x280f77ff, ++ 0x77f5e43e, 0xba54549f, 0xbee1f25f, 0x88fed12f, 0xd5cfa183, 0x450857fa, ++ 0x8ff3bc43, 0x107df9ea, 0x2f96f7f2, 0x290dbdc5, 0x45d55c0e, 0xc5324dc4, ++ 0x69f4fd56, 0x8f5a85d4, 0x3b0e8e48, 0x1cb1b7fa, 0xdf0a477b, 0x80ff42af, ++ 0x71db21de, 0xa2a45f5f, 0x3238d5ee, 0x12abf5c0, 0xdf0349db, 0x5024a0f3, ++ 0xa8c5bd77, 0x0a3d93be, 0xe3dc92f5, 0x68f39906, 0xdf8c718f, 0x4bcf4d2f, ++ 0x3c88dad6, 0xcbfaf5b4, 0xa69d138c, 0xd790fdf8, 0x6b5937e3, 0x93abe2a3, ++ 0x7e0f3ef3, 0xcebc7ee2, 0x77a25cb1, 0xc78453aa, 0x9c01365c, 0x22247ce0, ++ 0x6d69da3f, 0x33f239f8, 0xe1d15ca1, 0xe87a1efc, 0xeaf9202e, 0x0a3fe9f6, ++ 0xe0dfec46, 0x471ba68b, 0x0a65748e, 0x8fdd19c8, 0xb2e2034a, 0x6fdd1fc7, ++ 0x7f24b62e, 0x563f4712, 0xb7c8d58b, 0xf6b9ffca, 0x37ed10f0, 0x7ce463d3, ++ 0x7b914165, 0xd7d93141, 0xeb93bd69, 0x9a4fa72f, 0xa175bdf8, 0xfd544577, ++ 0xc85954a5, 0x7a5d8ff5, 0x43f8e389, 0x58e9dd1b, 0x077e5c57, 0xd38a5dd7, ++ 0x61cfec2c, 0xb1b2dc3b, 0xbbe31332, 0xeeb9d956, 0xf7146a55, 0x7bf23f32, ++ 0x3d11e7be, 0xa7695bfb, 0xae8993e4, 0xfc030e11, 0x93a9076b, 0x7e6f49ed, ++ 0xd87f2250, 0x45557b41, 0x5eaed5d8, 0x2e0af389, 0xab9e9040, 0x18ee7d35, ++ 0x24afb7f9, 0x8c3b97f2, 0x299c1e6a, 0xb33fcccb, 0xcd16e29b, 0x0db853bf, ++ 0x1475d788, 0x9c52d157, 0xfd483d7d, 0x5985b8ee, 0xb76f9e6a, 0x59cd7f81, ++ 0x949e00bd, 0xe3917eda, 0x625f78e6, 0x5bee84fd, 0x7caadc0a, 0xe10fed7b, ++ 0x127c4ea8, 0xd69ed791, 0xfa43f8ab, 0x28d6f7e4, 0x3eeb95ec, 0xb6cf6e6e, ++ 0x797b73d7, 0xd9ef8abd, 0x67b79a8a, 0x93595dd3, 0x04716eb8, 0xcd5b4beb, ++ 0x8c3fe80e, 0xf969cf0b, 0x2d4cb67d, 0x562e7bcd, 0xc7440d6d, 0x6a22ff50, ++ 0x0bf31245, 0xa36f3158, 0x5330f19d, 0x0ed6b73e, 0x76697c7d, 0xb6a51f40, ++ 0xeef1ab93, 0x77f1a658, 0x82dca86d, 0x0bc672fb, 0xf7c7f62f, 0x6fd21e9a, ++ 0xa1240e19, 0x2a77ee9e, 0x949f8fa8, 0x5fd778ac, 0x0fbda78d, 0xd967e158, ++ 0xdb751592, 0xd29ed8b2, 0xb65fe254, 0x78038974, 0xf5caf84e, 0x556a29b0, ++ 0xa7d1b83b, 0x5d5aea48, 0xeaf8ea2a, 0xc1be3e3d, 0x385c5b5d, 0xf9a15fdb, ++ 0xb3e46851, 0x3fd7c478, 0x1cfb5ea3, 0xc9857bf8, 0x87f1a031, 0xbb5c541d, ++ 0x61b6eb88, 0xb4199a3b, 0xed1d87ed, 0x5545e2d6, 0xe47abbd5, 0xb9377513, ++ 0xaa1e86ef, 0x903f2f6b, 0xbf9ce7ca, 0x9bb8465e, 0x5b9ddc00, 0xf8e30b2f, ++ 0x0eeead41, 0xf569d5bc, 0xcf569d5c, 0x5cf569d5, 0xd5cf569d, 0x9d5cf569, ++ 0x69d5cf56, 0x569d5cf5, 0xf569d5cf, 0x09d71d5c, 0xa77db8db, 0x63b7377d, ++ 0xa71e5eed, 0xfc5dd138, 0x7b5bd5e7, 0xb7a9e78b, 0x027b188a, 0x77f25bc7, ++ 0xa73dbeb5, 0x2e7e4abe, 0xf179f847, 0x0fede248, 0x33e91f22, 0x510c4838, ++ 0xdf677066, 0x785c666d, 0xaeaffc0a, 0x66f586b3, 0x8cecbae6, 0xfe81ad30, ++ 0x74cbb95d, 0x680f8d32, 0x73ae10f7, 0x3e705fc2, 0xf85a0bf8, 0xacf96e8b, ++ 0x40c6fcbf, 0xe6a05d2e, 0x0fce5e07, 0x5daf7c4c, 0x4427841d, 0x51ac21df, ++ 0x0e697278, 0xe643d09e, 0xe7639097, 0xab745188, 0x37e025fe, 0xb8fe6a2e, ++ 0xf17c1e66, 0x28b2f8ab, 0xf602ffd6, 0xeb12d459, 0x7e4c3e40, 0x7a75f6ce, ++ 0x5e7ec4af, 0xdf792a2b, 0x1e267079, 0x82c771f7, 0xd14ff3e9, 0x321e3bfc, ++ 0x95d39e73, 0xffdd73be, 0xc57c6707, 0x6f1e3eaa, 0x205e340f, 0x7f604a59, ++ 0xd877f1d7, 0xcb87ae5c, 0xa507ecb1, 0xbe12c3ca, 0x4dbaeec7, 0x977dc6ac, ++ 0x869f2b18, 0x73f2369c, 0x6b26f77e, 0x58dd5d75, 0xcfa221c3, 0xf03a66a5, ++ 0xda616d1d, 0x16bd9131, 0x079e5438, 0x7a273c9c, 0x1cbbac24, 0xf84ffeef, ++ 0x7479cde9, 0xcfd6796a, 0xfb71e56c, 0x563ef9bb, 0xb7dee214, 0xa843ed1a, ++ 0xa78b0433, 0x35b0aeb9, 0x3a885ec1, 0x4bf8b043, 0x87d9b695, 0x3f9e0724, ++ 0x6d2f5cd3, 0x73d4de7a, 0x7abe2221, 0x745189fc, 0xcf7a70eb, 0x94efc885, ++ 0x73ef41f8, 0x274973f1, 0xa793be22, 0xb04beec9, 0x7ff94f43, 0x3178efab, ++ 0x72f1f1cd, 0x95f59db1, 0x60044a72, 0x2c9bd3cf, 0xb6cfbdfc, 0xea356da0, ++ 0x5ecf226c, 0xcf947988, 0x1d7ce0ce, 0xa19f9deb, 0x6dced4cd, 0x054fd7c3, ++ 0x426631d6, 0x0efb567b, 0xabbb2a39, 0x7bc596d0, 0xfb2fdc75, 0x25bed00a, ++ 0x3f41effb, 0x9037c5f9, 0xd5d1eca7, 0xce89732b, 0xb757fa34, 0x9d271199, ++ 0xbdff82df, 0x24a29c1b, 0x7f7aeae5, 0x923e76a7, 0xf1f18747, 0xfbf3991c, ++ 0x1b6a95f1, 0x12cc8bb6, 0x585fff35, 0xfad1faa2, 0xf23bf54e, 0x5859fb5c, ++ 0xf9386b22, 0xbc9372c3, 0x2c2fd8c9, 0x29a9e8bf, 0x6f243c80, 0x6f2a894a, ++ 0x4e615a2a, 0xf7cc3ae2, 0x9357abdb, 0xc253b54b, 0x2a0ba6c5, 0xa39b722e, ++ 0x5f2225f3, 0x97cfb8c8, 0xfa337908, 0x6a764da7, 0x9b4ef59f, 0xfb3c3790, ++ 0xf426d30f, 0xe514eb3f, 0x757ee1f3, 0x737cc289, 0xfaf34fd6, 0x8c7bf4c5, ++ 0x89d307df, 0xea72dbc8, 0xc97834df, 0xa3ec576e, 0xb6f2a37d, 0x8b5f8e5c, ++ 0x7c5a5b35, 0x0f602c9f, 0x9c109f8b, 0x64928aa7, 0x518c6f1e, 0xbef1bffd, ++ 0xd1d8647b, 0x3b923e35, 0xec56fec2, 0xa304cdd3, 0x5d7806f8, 0x941b8693, ++ 0x7b8d45a7, 0xe4f23988, 0x908f0d0c, 0xde115637, 0xfcdfea78, 0xc19eff8a, ++ 0x8fc39faf, 0xc38c29b0, 0xfdd6f102, 0x3f0ed07a, 0xf3b79e88, 0xe1755fd6, ++ 0xd55f5b5d, 0x7177e06b, 0xb42e91ed, 0x1aefcdcd, 0xcaf3826c, 0x5794f9a8, ++ 0xc957d146, 0x968e4739, 0xd9772e7b, 0xec97d9e6, 0xed236fe0, 0x7fdeb4e0, ++ 0xa7a9de0d, 0x2f0eb13d, 0x5dff11c7, 0xcdfd97c0, 0xcae20766, 0xb1727f81, ++ 0x82ed857d, 0x9d80efd6, 0x751db8fd, 0x4baf7cf2, 0x7e6fc2e4, 0x1e029dac, ++ 0x43c28f2e, 0x372bd72f, 0x5ae7185b, 0x4b5ff7b5, 0x90f395ad, 0xe8b75fb0, ++ 0x61761ffc, 0xbf85b25e, 0xe6dc1043, 0xce56efe2, 0xee8e19c9, 0xdce27c88, ++ 0xd03e65e6, 0x00fe9da9, 0x42ff4ef8, 0x5c7ea072, 0x6ae2a712, 0x7cd95ca9, ++ 0x94dfc688, 0xbf1b8c03, 0xf8287e01, 0x6e368a3b, 0xbf57af2f, 0xbf09a4ab, ++ 0x82fdfea4, 0xf4ef10bd, 0xbeb477f0, 0x4723bebd, 0x7c97cef1, 0x5d44ec4f, ++ 0x2ccc6ff4, 0x7b27c84f, 0xbe9e74f5, 0xddb8c144, 0xe3873db7, 0x5654484e, ++ 0x67bc85dd, 0x4fd72c5b, 0x8fed12fb, 0x5f697be0, 0xe7ce4ac3, 0xc6a37d8f, ++ 0x312de9fb, 0x7d6fe40e, 0x381dedab, 0x767ddf57, 0x524d7f1e, 0x511f79f9, ++ 0x45b7d3f5, 0x435f673d, 0xc2cbbf12, 0xefd7d0f7, 0xb777c74c, 0x3ef778d6, ++ 0xf6867bdc, 0x096fb1dd, 0x98fb53f5, 0x4efdb954, 0xcaa559f0, 0x9dbd797b, ++ 0xf6f4e6f1, 0x541c8f95, 0xf7c019f5, 0x16cdd6af, 0x2fffb77e, 0xfb20ee11, ++ 0x000024f0 + }; + + #endif /*__BNX2X_INIT_VALUES_H__*/ +diff -r e67cb9a8e847 drivers/net/bnx2x_init_values_e1.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/bnx2x_init_values_e1.c Wed Aug 05 10:51:02 2009 +0100 +@@ -0,0 +1,13901 @@ ++/* init_ops array contains the list of operations needed to initialize the chip. ++ * ++ * For each block in the chip there are three init stages: ++ * common - HW used by both ports, ++ * port1 and port2 - initialization for a specific Ethernet port. ++ * When a port is opened or closed, the management CPU tells the driver ++ * whether to init/disable common HW in addition to the port HW. ++ * This way the first port going up will first initializes the common HW, ++ * and the last port going down also resets the common HW ++ * ++ * For each init stage/block there is a list of actions needed in a format: ++ * {operation, register, data} ++ * where: ++ * OP_WR - write a value to the chip. ++ * OP_RD - read a register (usually a clear on read register). ++ * OP_SW - string write, write a section of consecutive addresses to the chip. ++ * OP_SI - copy a string using indirect writes. ++ * OP_ZR - clear a range of memory. ++ * OP_ZP - unzip and copy using DMAE. ++ * OP_WB - string copy using DMAE. ++ * ++ * The #defines mark the stages. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include "bnx2x_compat.h" ++#include "bnx2x_init.h" ++#include "bnx2x.h" ++ ++ ++static const struct raw_op init_ops_e1[] = { ++/* #define PRS_COMMON_START 0 */ ++ {OP_WR, PRS_REG_INC_VALUE, 0xf}, ++ {OP_WR, PRS_REG_EVENT_ID_1, 0x45}, ++ {OP_WR, PRS_REG_EVENT_ID_2, 0x84}, ++ {OP_WR, PRS_REG_EVENT_ID_3, 0x6}, ++ {OP_WR, PRS_REG_NO_MATCH_EVENT_ID, 0x4}, ++ {OP_WR, PRS_REG_CM_HDR_TYPE_0, 0x0}, ++ {OP_WR, PRS_REG_CM_HDR_TYPE_1, 0x12170000}, ++ {OP_WR, PRS_REG_CM_HDR_TYPE_2, 0x22170000}, ++ {OP_WR, PRS_REG_CM_HDR_TYPE_3, 0x32170000}, ++ {OP_ZR, PRS_REG_CM_HDR_TYPE_4, 0x5}, ++ {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_1, 0x12150000}, ++ {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_2, 0x22150000}, ++ {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_3, 0x32150000}, ++ {OP_ZR, PRS_REG_CM_HDR_LOOPBACK_TYPE_4, 0x4}, ++ {OP_WR, PRS_REG_CM_NO_MATCH_HDR, 0x2100000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0x100000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000}, ++ {OP_ZR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x4}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000}, ++ {OP_ZR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x4}, ++ {OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0}, ++ {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0}, ++ {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0}, ++ {OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_3, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_4, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_5, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_6, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_7, 0xff}, ++ {OP_WR, PRS_REG_PURE_REGIONS, 0x3e}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_0, 0x0}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_4, 0x0}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f}, ++/* #define PRS_COMMON_END 1 */ ++/* #define TSDM_COMMON_START 44 */ ++ {OP_WR, TSDM_REG_CFC_RSP_START_ADDR, 0x411}, ++ {OP_WR, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400}, ++ {OP_WR, TSDM_REG_Q_COUNTER_START_ADDR, 0x404}, ++ {OP_WR, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419}, ++ {OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff}, ++ {OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff}, ++ {OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff}, ++ {OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff}, ++ {OP_ZR, TSDM_REG_AGG_INT_EVENT_0, 0x2}, ++ {OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34}, ++ {OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35}, ++ {OP_ZR, TSDM_REG_AGG_INT_EVENT_4, 0x7c}, ++ {OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff}, ++ {OP_WR, TSDM_REG_ENABLE_IN2, 0x3f}, ++ {OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff}, ++ {OP_WR, TSDM_REG_ENABLE_OUT2, 0xf}, ++ {OP_RD, TSDM_REG_NUM_OF_Q0_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q1_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q3_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q4_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q5_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q6_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q7_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q8_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q9_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q10_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q11_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, ++ {OP_WR, TSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1}, ++ {OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8}, ++ {OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1}, ++ {OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa}, ++/* #define TSDM_COMMON_END 45 */ ++/* #define TCM_COMMON_START 66 */ ++ {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20}, ++ {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32}, ++ {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020}, ++ {OP_WR, TCM_REG_TQM_TCM_HDR_S, 0x2150020}, ++ {OP_WR, TCM_REG_TM_TCM_HDR, 0x30}, ++ {OP_WR, TCM_REG_ERR_TCM_HDR, 0x8100000}, ++ {OP_WR, TCM_REG_ERR_EVNT_ID, 0x33}, ++ {OP_WR, TCM_REG_EXPR_EVNT_ID, 0x30}, ++ {OP_WR, TCM_REG_STOP_EVNT_ID, 0x31}, ++ {OP_WR, TCM_REG_STORM_WEIGHT, 0x2}, ++ {OP_WR, TCM_REG_PRS_WEIGHT, 0x5}, ++ {OP_WR, TCM_REG_PBF_WEIGHT, 0x6}, ++ {OP_WR, TCM_REG_USEM_WEIGHT, 0x2}, ++ {OP_WR, TCM_REG_CSEM_WEIGHT, 0x2}, ++ {OP_WR, TCM_REG_CP_WEIGHT, 0x0}, ++ {OP_WR, TCM_REG_TSDM_WEIGHT, 0x5}, ++ {OP_WR, TCM_REG_TQM_P_WEIGHT, 0x2}, ++ {OP_WR, TCM_REG_TQM_S_WEIGHT, 0x2}, ++ {OP_WR, TCM_REG_TM_WEIGHT, 0x2}, ++ {OP_WR, TCM_REG_TCM_TQM_USE_Q, 0x1}, ++ {OP_WR, TCM_REG_GR_ARB_TYPE, 0x1}, ++ {OP_WR, TCM_REG_GR_LD0_PR, 0x1}, ++ {OP_WR, TCM_REG_GR_LD1_PR, 0x2}, ++ {OP_WR, TCM_REG_CFC_INIT_CRD, 0x1}, ++ {OP_WR, TCM_REG_FIC0_INIT_CRD, 0x40}, ++ {OP_WR, TCM_REG_FIC1_INIT_CRD, 0x40}, ++ {OP_WR, TCM_REG_TQM_INIT_CRD, 0x20}, ++ {OP_WR, TCM_REG_XX_INIT_CRD, 0x13}, ++ {OP_WR, TCM_REG_XX_MSG_NUM, 0x20}, ++ {OP_ZR, TCM_REG_XX_TABLE, 0xa}, ++ {OP_SW, TCM_REG_XX_DESCR_TABLE, 0x200000}, ++ {OP_WR, TCM_REG_N_SM_CTX_LD_0, 0x7}, ++ {OP_WR, TCM_REG_N_SM_CTX_LD_1, 0x7}, ++ {OP_WR, TCM_REG_N_SM_CTX_LD_2, 0x8}, ++ {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8}, ++ {OP_ZR, TCM_REG_N_SM_CTX_LD_4, 0x4}, ++ {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6}, ++ {OP_WR, TCM_REG_PHYS_QNUM0_0, 0xd}, ++ {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x2d}, ++ {OP_WR, TCM_REG_PHYS_QNUM1_0, 0x7}, ++ {OP_WR, TCM_REG_PHYS_QNUM1_1, 0x27}, ++ {OP_WR, TCM_REG_PHYS_QNUM2_0, 0x7}, ++ {OP_WR, TCM_REG_PHYS_QNUM2_1, 0x27}, ++ {OP_WR, TCM_REG_PHYS_QNUM3_0, 0x7}, ++ {OP_WR, TCM_REG_PHYS_QNUM3_1, 0x27}, ++ {OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1}, ++ {OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1}, ++ {OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_STORM_TCM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_TQM_TCM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_TSDM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_TM_TCM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_PRS_IFEN, 0x1}, ++ {OP_WR, TCM_REG_PBF_IFEN, 0x1}, ++ {OP_WR, TCM_REG_USEM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_CSEM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_CDU_AG_WR_IFEN, 0x1}, ++ {OP_WR, TCM_REG_CDU_AG_RD_IFEN, 0x1}, ++ {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1}, ++ {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1}, ++ {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1}, ++/* #define TCM_COMMON_END 67 */ ++/* #define BRB1_COMMON_START 88 */ ++ {OP_SW, BRB1_REG_LL_RAM, 0x2000020}, ++ {OP_WR, BRB1_REG_SOFT_RESET, 0x1}, ++ {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0}, ++ {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220}, ++ {OP_WR, BRB1_REG_SOFT_RESET, 0x0}, ++/* #define BRB1_COMMON_END 89 */ ++/* #define BRB1_PORT0_START 90 */ ++ {OP_WR, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0xb8}, ++ {OP_WR, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 0x114}, ++ {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0}, ++ {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0}, ++/* #define BRB1_PORT0_END 91 */ ++/* #define BRB1_PORT1_START 92 */ ++ {OP_WR, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0xb8}, ++ {OP_WR, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 0x114}, ++ {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0}, ++ {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0}, ++/* #define BRB1_PORT1_END 93 */ ++/* #define TSEM_COMMON_START 110 */ ++ {OP_ZP, TSEM_REG_INT_TABLE, 0x960000}, ++ {OP_WR_64, TSEM_REG_INT_TABLE + 0x360, 0x140223}, ++ {OP_ZP, TSEM_REG_PRAM, 0x34b80000}, ++ {OP_ZP, TSEM_REG_PRAM + 0x8000, 0x34e90d2f}, ++ {OP_ZP, TSEM_REG_PRAM + 0x10000, 0x9dd1a6a}, ++ {OP_WR_64, TSEM_REG_PRAM + 0x11400, 0x5d800225}, ++ {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0}, ++ {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0}, ++ {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0}, ++ {OP_RD, TSEM_REG_MSG_NUM_FOC1, 0x0}, ++ {OP_RD, TSEM_REG_MSG_NUM_FOC2, 0x0}, ++ {OP_RD, TSEM_REG_MSG_NUM_FOC3, 0x0}, ++ {OP_WR, TSEM_REG_ARB_ELEMENT0, 0x1}, ++ {OP_WR, TSEM_REG_ARB_ELEMENT1, 0x2}, ++ {OP_WR, TSEM_REG_ARB_ELEMENT2, 0x3}, ++ {OP_WR, TSEM_REG_ARB_ELEMENT3, 0x0}, ++ {OP_WR, TSEM_REG_ARB_ELEMENT4, 0x4}, ++ {OP_WR, TSEM_REG_ARB_CYCLE_SIZE, 0x1}, ++ {OP_WR, TSEM_REG_TS_0_AS, 0x0}, ++ {OP_WR, TSEM_REG_TS_1_AS, 0x1}, ++ {OP_WR, TSEM_REG_TS_2_AS, 0x4}, ++ {OP_WR, TSEM_REG_TS_3_AS, 0x0}, ++ {OP_WR, TSEM_REG_TS_4_AS, 0x1}, ++ {OP_WR, TSEM_REG_TS_5_AS, 0x3}, ++ {OP_WR, TSEM_REG_TS_6_AS, 0x0}, ++ {OP_WR, TSEM_REG_TS_7_AS, 0x1}, ++ {OP_WR, TSEM_REG_TS_8_AS, 0x4}, ++ {OP_WR, TSEM_REG_TS_9_AS, 0x0}, ++ {OP_WR, TSEM_REG_TS_10_AS, 0x1}, ++ {OP_WR, TSEM_REG_TS_11_AS, 0x3}, ++ {OP_WR, TSEM_REG_TS_12_AS, 0x0}, ++ {OP_WR, TSEM_REG_TS_13_AS, 0x1}, ++ {OP_WR, TSEM_REG_TS_14_AS, 0x4}, ++ {OP_WR, TSEM_REG_TS_15_AS, 0x0}, ++ {OP_WR, TSEM_REG_TS_16_AS, 0x4}, ++ {OP_WR, TSEM_REG_TS_17_AS, 0x3}, ++ {OP_ZR, TSEM_REG_TS_18_AS, 0x2}, ++ {OP_WR, TSEM_REG_ENABLE_IN, 0x3fff}, ++ {OP_WR, TSEM_REG_ENABLE_OUT, 0x3ff}, ++ {OP_WR, TSEM_REG_FIC0_DISABLE, 0x0}, ++ {OP_WR, TSEM_REG_FIC1_DISABLE, 0x0}, ++ {OP_WR, TSEM_REG_PAS_DISABLE, 0x0}, ++ {OP_WR, TSEM_REG_THREADS_LIST, 0xff}, ++ {OP_ZR, TSEM_REG_PASSIVE_BUFFER, 0x400}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x18bc0, 0x1}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x18000, 0x34}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20}, ++ {OP_WR_ASIC, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, ++ {OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x18300, 0x138}, ++ {OP_WR_FPGA, TSEM_REG_FAST_MEMORY + 0x18300, 0x1388}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2000, 0xb2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x23c8, 0x181}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x23c8 + 0x604, 0x10227}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1020, 0xc8}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1000, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1e38, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1e30, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x810, 0x4}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x50228}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x4cb0, 0x8022d}, ++/* #define TSEM_COMMON_END 111 */ ++/* #define TSEM_PORT0_START 112 */ ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x22c8, 0x20}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x124}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x4920, 0x0}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1400, 0xa}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1450, 0x6}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1500, 0x2}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x1500 + 0x8, 0x50235}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1500 + 0x1c, 0x9}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1580, 0x14}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x9c0, 0x48}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x820, 0xe}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x2023a}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2c28, 0x2}, ++/* #define TSEM_PORT0_END 113 */ ++/* #define TSEM_PORT1_START 114 */ ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2348, 0x20}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4490, 0x124}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x4924, 0x0}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1428, 0xa}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1468, 0x6}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1540, 0x2}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x1540 + 0x8, 0x5023c}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1540 + 0x1c, 0x9}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x15d0, 0x14}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xae0, 0x48}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x858, 0xe}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20241}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2c30, 0x2}, ++/* #define TSEM_PORT1_END 115 */ ++/* #define MISC_COMMON_START 220 */ ++ {OP_WR, MISC_REG_GRC_TIMEOUT_EN, 0x1}, ++ {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911}, ++ {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0}, ++ {OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424}, ++ {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0}, ++ {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209}, ++ {OP_WR, MISC_REG_SPIO, 0xff000000}, ++/* #define MISC_COMMON_END 221 */ ++/* #define NIG_COMMON_START 264 */ ++ {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1}, ++ {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1}, ++/* #define NIG_COMMON_END 265 */ ++/* #define NIG_PORT0_START 266 */ ++ {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000}, ++ {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28}, ++ {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0}, ++ {OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4}, ++ {OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1}, ++ {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0}, ++ {OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30}, ++ {OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1}, ++ {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1}, ++/* #define NIG_PORT0_END 267 */ ++/* #define NIG_PORT1_START 268 */ ++ {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000}, ++ {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28}, ++ {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0}, ++ {OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4}, ++ {OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1}, ++ {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0}, ++ {OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30}, ++ {OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1}, ++ {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1}, ++/* #define NIG_PORT1_END 269 */ ++/* #define UPB_COMMON_START 308 */ ++ {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20}, ++/* #define UPB_COMMON_END 309 */ ++/* #define CSDM_COMMON_START 330 */ ++ {OP_WR, CSDM_REG_CFC_RSP_START_ADDR, 0xa11}, ++ {OP_WR, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, ++ {OP_WR, CSDM_REG_Q_COUNTER_START_ADDR, 0xa04}, ++ {OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff}, ++ {OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff}, ++ {OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff}, ++ {OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff}, ++ {OP_ZR, CSDM_REG_AGG_INT_EVENT_0, 0x2}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_2, 0x34}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_3, 0x35}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_4, 0x20}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_5, 0x21}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_6, 0x22}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_7, 0x23}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_8, 0x24}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_9, 0x25}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_10, 0x26}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_11, 0x27}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_12, 0x28}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_13, 0x29}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_14, 0x2a}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_15, 0x2b}, ++ {OP_ZR, CSDM_REG_AGG_INT_EVENT_16, 0x56}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_6, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_7, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_8, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_9, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_10, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_11, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_12, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_13, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_14, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_15, 0x1}, ++ {OP_ZR, CSDM_REG_AGG_INT_MODE_16, 0x10}, ++ {OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff}, ++ {OP_WR, CSDM_REG_ENABLE_IN2, 0x3f}, ++ {OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff}, ++ {OP_WR, CSDM_REG_ENABLE_OUT2, 0xf}, ++ {OP_RD, CSDM_REG_NUM_OF_Q0_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q1_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q3_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q4_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q5_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q6_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q7_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q8_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q9_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q10_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q11_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, ++ {OP_WR, CSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1}, ++ {OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8}, ++ {OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1}, ++ {OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa}, ++/* #define CSDM_COMMON_END 331 */ ++/* #define USDM_COMMON_START 352 */ ++ {OP_WR, USDM_REG_CFC_RSP_START_ADDR, 0x365}, ++ {OP_WR, USDM_REG_CMP_COUNTER_START_ADDR, 0x354}, ++ {OP_WR, USDM_REG_Q_COUNTER_START_ADDR, 0x358}, ++ {OP_WR, USDM_REG_PCK_END_MSG_START_ADDR, 0x375}, ++ {OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff}, ++ {OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff}, ++ {OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff}, ++ {OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff}, ++ {OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46}, ++ {OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5}, ++ {OP_ZR, USDM_REG_AGG_INT_EVENT_2, 0x5e}, ++ {OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1}, ++ {OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x1f}, ++ {OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff}, ++ {OP_WR, USDM_REG_ENABLE_IN2, 0x3f}, ++ {OP_WR, USDM_REG_ENABLE_OUT1, 0x7ffffff}, ++ {OP_WR, USDM_REG_ENABLE_OUT2, 0xf}, ++ {OP_RD, USDM_REG_NUM_OF_Q0_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q1_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q2_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q3_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q4_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q5_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q6_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q7_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q8_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q9_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q10_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q11_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, ++ {OP_WR, USDM_REG_INIT_CREDIT_PXP_CTRL, 0x1}, ++ {OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8}, ++ {OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1}, ++ {OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa}, ++/* #define USDM_COMMON_END 353 */ ++/* #define CCM_COMMON_START 374 */ ++ {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32}, ++ {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020}, ++ {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020}, ++ {OP_WR, CCM_REG_ERR_CCM_HDR, 0x8100000}, ++ {OP_WR, CCM_REG_ERR_EVNT_ID, 0x33}, ++ {OP_WR, CCM_REG_STORM_WEIGHT, 0x2}, ++ {OP_WR, CCM_REG_TSEM_WEIGHT, 0x0}, ++ {OP_WR, CCM_REG_XSEM_WEIGHT, 0x5}, ++ {OP_WR, CCM_REG_USEM_WEIGHT, 0x5}, ++ {OP_ZR, CCM_REG_PBF_WEIGHT, 0x2}, ++ {OP_WR, CCM_REG_CSDM_WEIGHT, 0x2}, ++ {OP_WR, CCM_REG_CQM_P_WEIGHT, 0x3}, ++ {OP_WR, CCM_REG_CQM_S_WEIGHT, 0x2}, ++ {OP_WR, CCM_REG_CCM_CQM_USE_Q, 0x1}, ++ {OP_WR, CCM_REG_CNT_AUX1_Q, 0x2}, ++ {OP_WR, CCM_REG_CNT_AUX2_Q, 0x2}, ++ {OP_WR, CCM_REG_INV_DONE_Q, 0x1}, ++ {OP_WR, CCM_REG_GR_ARB_TYPE, 0x1}, ++ {OP_WR, CCM_REG_GR_LD0_PR, 0x1}, ++ {OP_WR, CCM_REG_GR_LD1_PR, 0x2}, ++ {OP_WR, CCM_REG_CFC_INIT_CRD, 0x1}, ++ {OP_WR, CCM_REG_CQM_INIT_CRD, 0x20}, ++ {OP_WR, CCM_REG_FIC0_INIT_CRD, 0x40}, ++ {OP_WR, CCM_REG_FIC1_INIT_CRD, 0x40}, ++ {OP_WR, CCM_REG_XX_INIT_CRD, 0x3}, ++ {OP_WR, CCM_REG_XX_MSG_NUM, 0x18}, ++ {OP_ZR, CCM_REG_XX_TABLE, 0x12}, ++ {OP_SW, CCM_REG_XX_DESCR_TABLE, 0x240243}, ++ {OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1}, ++ {OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2}, ++ {OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8}, ++ {OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8}, ++ {OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4}, ++ {OP_WR, CCM_REG_CCM_REG0_SZ, 0x4}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x9}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x29}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0xa}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x7}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x27}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x7}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x27}, ++ {OP_WR, CCM_REG_PHYS_QNUM1_0, 0xc}, ++ {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x2c}, ++ {OP_WR, CCM_REG_PHYS_QNUM2_0, 0xc}, ++ {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x2c}, ++ {OP_WR, CCM_REG_PHYS_QNUM3_0, 0xc}, ++ {OP_WR, CCM_REG_PHYS_QNUM3_1, 0x2c}, ++ {OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_STORM_CCM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CQM_CCM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CSDM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_TSEM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_XSEM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_USEM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_PBF_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CDU_AG_WR_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CDU_AG_RD_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1}, ++/* #define CCM_COMMON_END 375 */ ++/* #define UCM_COMMON_START 396 */ ++ {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32}, ++ {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020}, ++ {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020}, ++ {OP_WR, UCM_REG_TM_UCM_HDR, 0x30}, ++ {OP_WR, UCM_REG_ERR_UCM_HDR, 0x8100000}, ++ {OP_WR, UCM_REG_ERR_EVNT_ID, 0x33}, ++ {OP_WR, UCM_REG_EXPR_EVNT_ID, 0x30}, ++ {OP_WR, UCM_REG_STOP_EVNT_ID, 0x31}, ++ {OP_WR, UCM_REG_STORM_WEIGHT, 0x2}, ++ {OP_WR, UCM_REG_TSEM_WEIGHT, 0x4}, ++ {OP_WR, UCM_REG_CSEM_WEIGHT, 0x0}, ++ {OP_WR, UCM_REG_XSEM_WEIGHT, 0x2}, ++ {OP_WR, UCM_REG_DORQ_WEIGHT, 0x2}, ++ {OP_WR, UCM_REG_CP_WEIGHT, 0x0}, ++ {OP_WR, UCM_REG_USDM_WEIGHT, 0x2}, ++ {OP_WR, UCM_REG_UQM_P_WEIGHT, 0x7}, ++ {OP_WR, UCM_REG_UQM_S_WEIGHT, 0x2}, ++ {OP_WR, UCM_REG_TM_WEIGHT, 0x2}, ++ {OP_WR, UCM_REG_UCM_UQM_USE_Q, 0x1}, ++ {OP_WR, UCM_REG_INV_CFLG_Q, 0x1}, ++ {OP_WR, UCM_REG_GR_ARB_TYPE, 0x1}, ++ {OP_WR, UCM_REG_GR_LD0_PR, 0x1}, ++ {OP_WR, UCM_REG_GR_LD1_PR, 0x2}, ++ {OP_WR, UCM_REG_CFC_INIT_CRD, 0x1}, ++ {OP_WR, UCM_REG_FIC0_INIT_CRD, 0x40}, ++ {OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40}, ++ {OP_WR, UCM_REG_TM_INIT_CRD, 0x4}, ++ {OP_WR, UCM_REG_UQM_INIT_CRD, 0x20}, ++ {OP_WR, UCM_REG_XX_INIT_CRD, 0xe}, ++ {OP_WR, UCM_REG_XX_MSG_NUM, 0x1b}, ++ {OP_ZR, UCM_REG_XX_TABLE, 0x12}, ++ {OP_SW, UCM_REG_XX_DESCR_TABLE, 0x1b0267}, ++ {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0xc}, ++ {OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7}, ++ {OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf}, ++ {OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10}, ++ {OP_ZR, UCM_REG_N_SM_CTX_LD_4, 0x4}, ++ {OP_WR, UCM_REG_UCM_REG0_SZ, 0x3}, ++ {OP_WR, UCM_REG_PHYS_QNUM0_0, 0xf}, ++ {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x2f}, ++ {OP_WR, UCM_REG_PHYS_QNUM1_0, 0xe}, ++ {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x2e}, ++ {OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1}, ++ {OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1}, ++ {OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_STORM_UCM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_UQM_UCM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_USDM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_TM_UCM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_UCM_TM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_TSEM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_CSEM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_XSEM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_DORQ_IFEN, 0x1}, ++ {OP_WR, UCM_REG_CDU_AG_WR_IFEN, 0x1}, ++ {OP_WR, UCM_REG_CDU_AG_RD_IFEN, 0x1}, ++ {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1}, ++ {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1}, ++ {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1}, ++/* #define UCM_COMMON_END 397 */ ++/* #define USEM_COMMON_START 418 */ ++ {OP_ZP, USEM_REG_INT_TABLE, 0xc90000}, ++ {OP_WR_64, USEM_REG_INT_TABLE + 0x368, 0x130282}, ++ {OP_ZP, USEM_REG_PRAM, 0x34120000}, ++ {OP_ZP, USEM_REG_PRAM + 0x8000, 0x37b70d05}, ++ {OP_ZP, USEM_REG_PRAM + 0x10000, 0x2e7d1af3}, ++ {OP_WR_64, USEM_REG_PRAM + 0x16f40, 0x52180284}, ++ {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0}, ++ {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0}, ++ {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0}, ++ {OP_RD, USEM_REG_MSG_NUM_FOC1, 0x0}, ++ {OP_RD, USEM_REG_MSG_NUM_FOC2, 0x0}, ++ {OP_RD, USEM_REG_MSG_NUM_FOC3, 0x0}, ++ {OP_WR, USEM_REG_ARB_ELEMENT0, 0x1}, ++ {OP_WR, USEM_REG_ARB_ELEMENT1, 0x2}, ++ {OP_WR, USEM_REG_ARB_ELEMENT2, 0x3}, ++ {OP_WR, USEM_REG_ARB_ELEMENT3, 0x0}, ++ {OP_WR, USEM_REG_ARB_ELEMENT4, 0x4}, ++ {OP_WR, USEM_REG_ARB_CYCLE_SIZE, 0x1}, ++ {OP_WR, USEM_REG_TS_0_AS, 0x0}, ++ {OP_WR, USEM_REG_TS_1_AS, 0x1}, ++ {OP_WR, USEM_REG_TS_2_AS, 0x4}, ++ {OP_WR, USEM_REG_TS_3_AS, 0x0}, ++ {OP_WR, USEM_REG_TS_4_AS, 0x1}, ++ {OP_WR, USEM_REG_TS_5_AS, 0x3}, ++ {OP_WR, USEM_REG_TS_6_AS, 0x0}, ++ {OP_WR, USEM_REG_TS_7_AS, 0x1}, ++ {OP_WR, USEM_REG_TS_8_AS, 0x4}, ++ {OP_WR, USEM_REG_TS_9_AS, 0x0}, ++ {OP_WR, USEM_REG_TS_10_AS, 0x1}, ++ {OP_WR, USEM_REG_TS_11_AS, 0x3}, ++ {OP_WR, USEM_REG_TS_12_AS, 0x0}, ++ {OP_WR, USEM_REG_TS_13_AS, 0x1}, ++ {OP_WR, USEM_REG_TS_14_AS, 0x4}, ++ {OP_WR, USEM_REG_TS_15_AS, 0x0}, ++ {OP_WR, USEM_REG_TS_16_AS, 0x4}, ++ {OP_WR, USEM_REG_TS_17_AS, 0x3}, ++ {OP_ZR, USEM_REG_TS_18_AS, 0x2}, ++ {OP_WR, USEM_REG_ENABLE_IN, 0x3fff}, ++ {OP_WR, USEM_REG_ENABLE_OUT, 0x3ff}, ++ {OP_WR, USEM_REG_FIC0_DISABLE, 0x0}, ++ {OP_WR, USEM_REG_FIC1_DISABLE, 0x0}, ++ {OP_WR, USEM_REG_PAS_DISABLE, 0x0}, ++ {OP_WR, USEM_REG_THREADS_LIST, 0xffff}, ++ {OP_ZR, USEM_REG_PASSIVE_BUFFER, 0x800}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x18bc0, 0x1}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x18000, 0x1a}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20}, ++ {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, ++ {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18300, 0x138}, ++ {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18300, 0x1388}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, ++ {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500}, ++ {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4}, ++ {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x1aa0, 0xc2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x1020, 0xc8}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x1000, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x1400, 0x40}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5098, 0x4}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5080, 0x5}, ++ {OP_SW, USEM_REG_FAST_MEMORY + 0x5080 + 0x14, 0x10286}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x20}, ++ {OP_SW, USEM_REG_FAST_MEMORY + 0x2830, 0x20287}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, ++ {OP_SW, USEM_REG_FAST_MEMORY + 0x10c00, 0x100289}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0}, ++ {OP_SW, USEM_REG_FAST_MEMORY + 0x10c40, 0x100299}, ++/* #define USEM_COMMON_END 419 */ ++/* #define USEM_PORT0_START 420 */ ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x1500, 0xb4}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x1dc8, 0x0}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x4000, 0xd8}, ++/* #define USEM_PORT0_END 421 */ ++/* #define USEM_PORT1_START 422 */ ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x17d0, 0xb4}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x1dcc, 0x0}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x4360, 0xd8}, ++/* #define USEM_PORT1_END 423 */ ++/* #define CSEM_COMMON_START 440 */ ++ {OP_ZP, CSEM_REG_INT_TABLE, 0x920000}, ++ {OP_WR_64, CSEM_REG_INT_TABLE + 0x380, 0x1002a9}, ++ {OP_ZP, CSEM_REG_PRAM, 0x2ccf0000}, ++ {OP_ZP, CSEM_REG_PRAM + 0x8000, 0x2ae50b34}, ++ {OP_WR_64, CSEM_REG_PRAM + 0xdc60, 0x62da02ab}, ++ {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0}, ++ {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0}, ++ {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0}, ++ {OP_RD, CSEM_REG_MSG_NUM_FOC1, 0x0}, ++ {OP_RD, CSEM_REG_MSG_NUM_FOC2, 0x0}, ++ {OP_RD, CSEM_REG_MSG_NUM_FOC3, 0x0}, ++ {OP_WR, CSEM_REG_ARB_ELEMENT0, 0x1}, ++ {OP_WR, CSEM_REG_ARB_ELEMENT1, 0x2}, ++ {OP_WR, CSEM_REG_ARB_ELEMENT2, 0x3}, ++ {OP_WR, CSEM_REG_ARB_ELEMENT3, 0x0}, ++ {OP_WR, CSEM_REG_ARB_ELEMENT4, 0x4}, ++ {OP_WR, CSEM_REG_ARB_CYCLE_SIZE, 0x1}, ++ {OP_WR, CSEM_REG_TS_0_AS, 0x0}, ++ {OP_WR, CSEM_REG_TS_1_AS, 0x1}, ++ {OP_WR, CSEM_REG_TS_2_AS, 0x4}, ++ {OP_WR, CSEM_REG_TS_3_AS, 0x0}, ++ {OP_WR, CSEM_REG_TS_4_AS, 0x1}, ++ {OP_WR, CSEM_REG_TS_5_AS, 0x3}, ++ {OP_WR, CSEM_REG_TS_6_AS, 0x0}, ++ {OP_WR, CSEM_REG_TS_7_AS, 0x1}, ++ {OP_WR, CSEM_REG_TS_8_AS, 0x4}, ++ {OP_WR, CSEM_REG_TS_9_AS, 0x0}, ++ {OP_WR, CSEM_REG_TS_10_AS, 0x1}, ++ {OP_WR, CSEM_REG_TS_11_AS, 0x3}, ++ {OP_WR, CSEM_REG_TS_12_AS, 0x0}, ++ {OP_WR, CSEM_REG_TS_13_AS, 0x1}, ++ {OP_WR, CSEM_REG_TS_14_AS, 0x4}, ++ {OP_WR, CSEM_REG_TS_15_AS, 0x0}, ++ {OP_WR, CSEM_REG_TS_16_AS, 0x4}, ++ {OP_WR, CSEM_REG_TS_17_AS, 0x3}, ++ {OP_ZR, CSEM_REG_TS_18_AS, 0x2}, ++ {OP_WR, CSEM_REG_ENABLE_IN, 0x3fff}, ++ {OP_WR, CSEM_REG_ENABLE_OUT, 0x3ff}, ++ {OP_WR, CSEM_REG_FIC0_DISABLE, 0x0}, ++ {OP_WR, CSEM_REG_FIC1_DISABLE, 0x0}, ++ {OP_WR, CSEM_REG_PAS_DISABLE, 0x0}, ++ {OP_WR, CSEM_REG_THREADS_LIST, 0xffff}, ++ {OP_ZR, CSEM_REG_PASSIVE_BUFFER, 0x800}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x18bc0, 0x1}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x18000, 0x10}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x18040, 0x12}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x5000, 0x42}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1020, 0xc8}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1000, 0x2}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2000, 0xc0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240}, ++ {OP_SW, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802ad}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff}, ++ {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002b5}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0}, ++ {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002c5}, ++/* #define CSEM_COMMON_END 441 */ ++/* #define CSEM_PORT0_START 442 */ ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3040, 0xa0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3540, 0x10}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x36c0, 0x30}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x4000, 0x200}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x35c0, 0x20}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3840, 0x30}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3000, 0x8}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x5118, 0x0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2300, 0xe}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2410, 0x30}, ++/* #define CSEM_PORT0_END 443 */ ++/* #define CSEM_PORT1_START 444 */ ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x32c0, 0xa0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3580, 0x10}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3780, 0x30}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x4800, 0x200}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3640, 0x20}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3900, 0x30}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3020, 0x8}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x511c, 0x0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2338, 0xe}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30}, ++/* #define CSEM_PORT1_END 445 */ ++/* #define XPB_COMMON_START 462 */ ++ {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x28}, ++/* #define XPB_COMMON_END 463 */ ++/* #define DQ_COMMON_START 484 */ ++ {OP_WR, DORQ_REG_MODE_ACT, 0x2}, ++ {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3}, ++ {OP_WR, DORQ_REG_OUTST_REQ, 0x4}, ++ {OP_WR, DORQ_REG_DPM_CID_ADDR, 0x8}, ++ {OP_WR, DORQ_REG_RSP_INIT_CRD, 0x2}, ++ {OP_WR, DORQ_REG_NORM_CMHEAD_TX, 0x90}, ++ {OP_WR, DORQ_REG_CMHEAD_RX, 0x90}, ++ {OP_WR, DORQ_REG_SHRT_CMHEAD, 0x800090}, ++ {OP_WR, DORQ_REG_ERR_CMHEAD, 0x8140000}, ++ {OP_WR, DORQ_REG_AGG_CMD0, 0x8a}, ++ {OP_WR, DORQ_REG_AGG_CMD1, 0x80}, ++ {OP_WR, DORQ_REG_AGG_CMD2, 0x81}, ++ {OP_WR, DORQ_REG_AGG_CMD3, 0x80}, ++ {OP_WR, DORQ_REG_SHRT_ACT_CNT, 0x6}, ++ {OP_WR, DORQ_REG_DQ_FIFO_FULL_TH, 0x7d0}, ++ {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c}, ++ {OP_WR, DORQ_REG_REGN, 0x7c1004}, ++ {OP_WR, DORQ_REG_IF_EN, 0xf}, ++/* #define DQ_COMMON_END 485 */ ++/* #define TIMERS_COMMON_START 506 */ ++ {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2}, ++ {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c}, ++ {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1}, ++ {OP_WR, TM_REG_CFC_CLD_CRDCNT_VAL, 0x1}, ++ {OP_WR, TM_REG_CLOUT_CRDCNT0_VAL, 0x1}, ++ {OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1}, ++ {OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1}, ++ {OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1}, ++ {OP_WR, TM_REG_PCIARB_CRDCNT_VAL, 0x1}, ++ {OP_WR_ASIC, TM_REG_TIMER_TICK_SIZE, 0x3d090}, ++ {OP_WR_EMUL, TM_REG_TIMER_TICK_SIZE, 0x9c}, ++ {OP_WR_FPGA, TM_REG_TIMER_TICK_SIZE, 0x9c4}, ++ {OP_WR, TM_REG_CL0_CONT_REGION, 0x8}, ++ {OP_WR, TM_REG_CL1_CONT_REGION, 0xc}, ++ {OP_WR, TM_REG_CL2_CONT_REGION, 0x10}, ++ {OP_WR, TM_REG_TM_CONTEXT_REGION, 0x20}, ++ {OP_WR, TM_REG_EN_TIMERS, 0x1}, ++ {OP_WR, TM_REG_EN_REAL_TIME_CNT, 0x1}, ++ {OP_WR, TM_REG_EN_CL0_INPUT, 0x1}, ++ {OP_WR, TM_REG_EN_CL1_INPUT, 0x1}, ++ {OP_WR, TM_REG_EN_CL2_INPUT, 0x1}, ++/* #define TIMERS_COMMON_END 507 */ ++/* #define TIMERS_PORT0_START 508 */ ++ {OP_WR, TM_REG_LIN0_LOGIC_ADDR, 0x0}, ++ {OP_WR, TM_REG_LIN0_PHY_ADDR_VALID, 0x0}, ++ {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2}, ++/* #define TIMERS_PORT0_END 509 */ ++/* #define TIMERS_PORT1_START 510 */ ++ {OP_WR, TM_REG_LIN1_LOGIC_ADDR, 0x0}, ++ {OP_WR, TM_REG_LIN1_PHY_ADDR_VALID, 0x0}, ++ {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2}, ++/* #define TIMERS_PORT1_END 511 */ ++/* #define XSDM_COMMON_START 528 */ ++ {OP_WR, XSDM_REG_CFC_RSP_START_ADDR, 0x614}, ++ {OP_WR, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600}, ++ {OP_WR, XSDM_REG_Q_COUNTER_START_ADDR, 0x604}, ++ {OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff}, ++ {OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff}, ++ {OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff}, ++ {OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_2, 0x34}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_3, 0x35}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_4, 0x23}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_5, 0x24}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_6, 0x25}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_7, 0x26}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_8, 0x27}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_9, 0x29}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_10, 0x2a}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_11, 0x2b}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_12, 0x2c}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_13, 0x2d}, ++ {OP_ZR, XSDM_REG_AGG_INT_EVENT_14, 0x52}, ++ {OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1}, ++ {OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f}, ++ {OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff}, ++ {OP_WR, XSDM_REG_ENABLE_IN2, 0x3f}, ++ {OP_WR, XSDM_REG_ENABLE_OUT1, 0x7ffffff}, ++ {OP_WR, XSDM_REG_ENABLE_OUT2, 0xf}, ++ {OP_RD, XSDM_REG_NUM_OF_Q0_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q1_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q3_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q4_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q5_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q6_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q7_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q8_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q9_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q10_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q11_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, ++ {OP_WR, XSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1}, ++ {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8}, ++ {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1}, ++ {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa}, ++/* #define XSDM_COMMON_END 529 */ ++/* #define QM_COMMON_START 550 */ ++ {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6}, ++ {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5}, ++ {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa}, ++ {OP_WR, QM_REG_ACTCTRINITVAL_3, 0x5}, ++ {OP_WR, QM_REG_PCIREQAT, 0x2}, ++ {OP_WR, QM_REG_CMINITCRD_0, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_1, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_2, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_3, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_4, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_5, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_6, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_7, 0x4}, ++ {OP_WR, QM_REG_OUTLDREQ, 0x4}, ++ {OP_WR, QM_REG_CTXREG_0, 0x7c}, ++ {OP_WR, QM_REG_CTXREG_1, 0x3d}, ++ {OP_WR, QM_REG_CTXREG_2, 0x3f}, ++ {OP_WR, QM_REG_CTXREG_3, 0x9c}, ++ {OP_WR, QM_REG_ENSEC, 0x7}, ++ {OP_ZR, QM_REG_QVOQIDX_0, 0x5}, ++ {OP_WR, QM_REG_WRRWEIGHTS_0, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_5, 0x0}, ++ {OP_WR, QM_REG_QVOQIDX_6, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_7, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_8, 0x2}, ++ {OP_WR, QM_REG_WRRWEIGHTS_1, 0x8012004}, ++ {OP_WR, QM_REG_QVOQIDX_9, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_10, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_11, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_12, 0x5}, ++ {OP_WR, QM_REG_WRRWEIGHTS_2, 0x20081001}, ++ {OP_WR, QM_REG_QVOQIDX_13, 0x8}, ++ {OP_WR, QM_REG_QVOQIDX_14, 0x6}, ++ {OP_WR, QM_REG_QVOQIDX_15, 0x7}, ++ {OP_WR, QM_REG_QVOQIDX_16, 0x0}, ++ {OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120}, ++ {OP_ZR, QM_REG_QVOQIDX_17, 0x4}, ++ {OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101}, ++ {OP_ZR, QM_REG_QVOQIDX_21, 0x4}, ++ {OP_WR, QM_REG_WRRWEIGHTS_5, 0x1010101}, ++ {OP_ZR, QM_REG_QVOQIDX_25, 0x4}, ++ {OP_WR, QM_REG_WRRWEIGHTS_6, 0x1010101}, ++ {OP_ZR, QM_REG_QVOQIDX_29, 0x3}, ++ {OP_WR, QM_REG_QVOQIDX_32, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_7, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_33, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_34, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_35, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_36, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_8, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_37, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_38, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_39, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_40, 0x2}, ++ {OP_WR, QM_REG_WRRWEIGHTS_9, 0x8012004}, ++ {OP_WR, QM_REG_QVOQIDX_41, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_42, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_43, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_44, 0x5}, ++ {OP_WR, QM_REG_WRRWEIGHTS_10, 0x20081001}, ++ {OP_WR, QM_REG_QVOQIDX_45, 0x8}, ++ {OP_WR, QM_REG_QVOQIDX_46, 0x6}, ++ {OP_WR, QM_REG_QVOQIDX_47, 0x7}, ++ {OP_WR, QM_REG_QVOQIDX_48, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_11, 0x1010120}, ++ {OP_WR, QM_REG_QVOQIDX_49, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_50, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_51, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_52, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_53, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_54, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_55, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_56, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_13, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_57, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_58, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_59, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_60, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_14, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_61, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_62, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_63, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_15, 0x1010101}, ++ {OP_WR, QM_REG_VOQQMASK_0_LSB, 0xffff003f}, ++ {OP_ZR, QM_REG_VOQQMASK_0_MSB, 0x2}, ++ {OP_WR, QM_REG_VOQQMASK_1_MSB, 0xffff003f}, ++ {OP_WR, QM_REG_VOQQMASK_2_LSB, 0x100}, ++ {OP_WR, QM_REG_VOQQMASK_2_MSB, 0x100}, ++ {OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2}, ++ {OP_WR, QM_REG_VOQQMASK_4_LSB, 0xc0}, ++ {OP_WR, QM_REG_VOQQMASK_4_MSB, 0xc0}, ++ {OP_WR, QM_REG_VOQQMASK_5_LSB, 0x1e00}, ++ {OP_WR, QM_REG_VOQQMASK_5_MSB, 0x1e00}, ++ {OP_WR, QM_REG_VOQQMASK_6_LSB, 0x4000}, ++ {OP_WR, QM_REG_VOQQMASK_6_MSB, 0x4000}, ++ {OP_WR, QM_REG_VOQQMASK_7_LSB, 0x8000}, ++ {OP_WR, QM_REG_VOQQMASK_7_MSB, 0x8000}, ++ {OP_WR, QM_REG_VOQQMASK_8_LSB, 0x2000}, ++ {OP_WR, QM_REG_VOQQMASK_8_MSB, 0x2000}, ++ {OP_ZR, QM_REG_VOQQMASK_9_LSB, 0x7}, ++ {OP_WR, QM_REG_VOQPORT_1, 0x1}, ++ {OP_ZR, QM_REG_VOQPORT_2, 0xa}, ++ {OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08}, ++ {OP_WR, QM_REG_CMINTVOQMASK_1, 0x40}, ++ {OP_WR, QM_REG_CMINTVOQMASK_2, 0x100}, ++ {OP_WR, QM_REG_CMINTVOQMASK_3, 0x20}, ++ {OP_WR, QM_REG_CMINTVOQMASK_4, 0x17}, ++ {OP_WR, QM_REG_CMINTVOQMASK_5, 0x80}, ++ {OP_WR, QM_REG_CMINTVOQMASK_6, 0x200}, ++ {OP_WR, QM_REG_CMINTVOQMASK_7, 0x0}, ++ {OP_WR, QM_REG_HWAEMPTYMASK_LSB, 0xffff01ff}, ++ {OP_WR, QM_REG_HWAEMPTYMASK_MSB, 0xffff01ff}, ++ {OP_WR, QM_REG_ENBYPVOQMASK, 0x13}, ++ {OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f}, ++ {OP_WR, QM_REG_VOQINITCREDIT_0, 0x140}, ++ {OP_WR, QM_REG_VOQINITCREDIT_1, 0x140}, ++ {OP_ZR, QM_REG_VOQINITCREDIT_2, 0x2}, ++ {OP_WR, QM_REG_VOQINITCREDIT_4, 0xc0}, ++ {OP_ZR, QM_REG_VOQINITCREDIT_5, 0x7}, ++ {OP_WR, QM_REG_TASKCRDCOST_0, 0x48}, ++ {OP_WR, QM_REG_TASKCRDCOST_1, 0x48}, ++ {OP_ZR, QM_REG_TASKCRDCOST_2, 0x2}, ++ {OP_WR, QM_REG_TASKCRDCOST_4, 0x48}, ++ {OP_ZR, QM_REG_TASKCRDCOST_5, 0x7}, ++ {OP_WR, QM_REG_BYTECRDINITVAL, 0x8000}, ++ {OP_WR, QM_REG_BYTECRDCOST, 0x25e4}, ++ {OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff}, ++ {OP_WR, QM_REG_ENBYTECRD_LSB, 0x7}, ++ {OP_WR, QM_REG_ENBYTECRD_MSB, 0x7}, ++ {OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0}, ++ {OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff}, ++ {OP_WR, QM_REG_FUNCNUMSEL_LSB, 0x0}, ++ {OP_WR, QM_REG_FUNCNUMSEL_MSB, 0xffffffff}, ++ {OP_WR, QM_REG_CMINTEN, 0xff}, ++/* #define QM_COMMON_END 551 */ ++/* #define PBF_COMMON_START 572 */ ++ {OP_WR, PBF_REG_INIT, 0x1}, ++ {OP_WR, PBF_REG_INIT_P4, 0x1}, ++ {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1}, ++ {OP_WR, PBF_REG_IF_ENABLE_REG, 0x7fff}, ++ {OP_WR, PBF_REG_INIT_P4, 0x0}, ++ {OP_WR, PBF_REG_INIT, 0x0}, ++ {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0}, ++/* #define PBF_COMMON_END 573 */ ++/* #define PBF_PORT0_START 574 */ ++ {OP_WR, PBF_REG_INIT_P0, 0x1}, ++ {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1}, ++ {OP_WR, PBF_REG_INIT_P0, 0x0}, ++ {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0}, ++/* #define PBF_PORT0_END 575 */ ++/* #define PBF_PORT1_START 576 */ ++ {OP_WR, PBF_REG_INIT_P1, 0x1}, ++ {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1}, ++ {OP_WR, PBF_REG_INIT_P1, 0x0}, ++ {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0}, ++/* #define PBF_PORT1_END 577 */ ++/* #define XCM_COMMON_START 594 */ ++ {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32}, ++ {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020}, ++ {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020}, ++ {OP_WR, XCM_REG_TM_XCM_HDR, 0x1000030}, ++ {OP_WR, XCM_REG_ERR_XCM_HDR, 0x8100000}, ++ {OP_WR, XCM_REG_ERR_EVNT_ID, 0x33}, ++ {OP_WR, XCM_REG_EXPR_EVNT_ID, 0x30}, ++ {OP_WR, XCM_REG_STOP_EVNT_ID, 0x31}, ++ {OP_WR, XCM_REG_STORM_WEIGHT, 0x3}, ++ {OP_WR, XCM_REG_TSEM_WEIGHT, 0x6}, ++ {OP_WR, XCM_REG_CSEM_WEIGHT, 0x3}, ++ {OP_WR, XCM_REG_USEM_WEIGHT, 0x3}, ++ {OP_WR, XCM_REG_DORQ_WEIGHT, 0x2}, ++ {OP_WR, XCM_REG_PBF_WEIGHT, 0x0}, ++ {OP_WR, XCM_REG_NIG0_WEIGHT, 0x2}, ++ {OP_WR, XCM_REG_CP_WEIGHT, 0x0}, ++ {OP_WR, XCM_REG_XSDM_WEIGHT, 0x6}, ++ {OP_WR, XCM_REG_XQM_P_WEIGHT, 0x4}, ++ {OP_WR, XCM_REG_XQM_S_WEIGHT, 0x2}, ++ {OP_WR, XCM_REG_TM_WEIGHT, 0x2}, ++ {OP_WR, XCM_REG_XCM_XQM_USE_Q, 0x1}, ++ {OP_WR, XCM_REG_XQM_BYP_ACT_UPD, 0x6}, ++ {OP_WR, XCM_REG_UNA_GT_NXT_Q, 0x0}, ++ {OP_WR, XCM_REG_AUX1_Q, 0x2}, ++ {OP_WR, XCM_REG_AUX_CNT_FLG_Q_19, 0x1}, ++ {OP_WR, XCM_REG_GR_ARB_TYPE, 0x1}, ++ {OP_WR, XCM_REG_GR_LD0_PR, 0x1}, ++ {OP_WR, XCM_REG_GR_LD1_PR, 0x2}, ++ {OP_WR, XCM_REG_CFC_INIT_CRD, 0x1}, ++ {OP_WR, XCM_REG_FIC0_INIT_CRD, 0x40}, ++ {OP_WR, XCM_REG_FIC1_INIT_CRD, 0x40}, ++ {OP_WR, XCM_REG_TM_INIT_CRD, 0x4}, ++ {OP_WR, XCM_REG_XQM_INIT_CRD, 0x20}, ++ {OP_WR, XCM_REG_XX_INIT_CRD, 0x2}, ++ {OP_WR, XCM_REG_XX_MSG_NUM, 0x1f}, ++ {OP_ZR, XCM_REG_XX_TABLE, 0x12}, ++ {OP_SW, XCM_REG_XX_DESCR_TABLE, 0x1f02d5}, ++ {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf}, ++ {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7}, ++ {OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb}, ++ {OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe}, ++ {OP_ZR, XCM_REG_N_SM_CTX_LD_4, 0x4}, ++ {OP_WR, XCM_REG_XCM_REG0_SZ, 0x4}, ++ {OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1}, ++ {OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1}, ++ {OP_WR, XCM_REG_XCM_XQM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_STORM_XCM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_XQM_XCM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_XSDM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_TM_XCM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_XCM_TM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_TSEM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_CSEM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_USEM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_DORQ_IFEN, 0x1}, ++ {OP_WR, XCM_REG_PBF_IFEN, 0x1}, ++ {OP_WR, XCM_REG_NIG0_IFEN, 0x1}, ++ {OP_WR, XCM_REG_NIG1_IFEN, 0x1}, ++ {OP_WR, XCM_REG_CDU_AG_WR_IFEN, 0x1}, ++ {OP_WR, XCM_REG_CDU_AG_RD_IFEN, 0x1}, ++ {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1}, ++ {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1}, ++ {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1}, ++/* #define XCM_COMMON_END 595 */ ++/* #define XCM_PORT0_START 596 */ ++ {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, ++ {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, ++/* #define XCM_PORT0_END 597 */ ++/* #define XCM_PORT1_START 598 */ ++ {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, ++ {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, ++/* #define XCM_PORT1_END 599 */ ++/* #define XSEM_COMMON_START 616 */ ++ {OP_ZP, XSEM_REG_INT_TABLE, 0xb40000}, ++ {OP_WR_64, XSEM_REG_INT_TABLE + 0x368, 0x1302f4}, ++ {OP_ZP, XSEM_REG_PRAM, 0x35d70000}, ++ {OP_ZP, XSEM_REG_PRAM + 0x8000, 0x3a590d76}, ++ {OP_ZP, XSEM_REG_PRAM + 0x10000, 0x3b741c0d}, ++ {OP_ZP, XSEM_REG_PRAM + 0x18000, 0x226c2aeb}, ++ {OP_WR_64, XSEM_REG_PRAM + 0x1c6f0, 0x472202f6}, ++ {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0}, ++ {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0}, ++ {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0}, ++ {OP_RD, XSEM_REG_MSG_NUM_FOC1, 0x0}, ++ {OP_RD, XSEM_REG_MSG_NUM_FOC2, 0x0}, ++ {OP_RD, XSEM_REG_MSG_NUM_FOC3, 0x0}, ++ {OP_WR, XSEM_REG_ARB_ELEMENT0, 0x1}, ++ {OP_WR, XSEM_REG_ARB_ELEMENT1, 0x2}, ++ {OP_WR, XSEM_REG_ARB_ELEMENT2, 0x3}, ++ {OP_WR, XSEM_REG_ARB_ELEMENT3, 0x0}, ++ {OP_WR, XSEM_REG_ARB_ELEMENT4, 0x4}, ++ {OP_WR, XSEM_REG_ARB_CYCLE_SIZE, 0x1}, ++ {OP_WR, XSEM_REG_TS_0_AS, 0x0}, ++ {OP_WR, XSEM_REG_TS_1_AS, 0x1}, ++ {OP_WR, XSEM_REG_TS_2_AS, 0x4}, ++ {OP_WR, XSEM_REG_TS_3_AS, 0x0}, ++ {OP_WR, XSEM_REG_TS_4_AS, 0x1}, ++ {OP_WR, XSEM_REG_TS_5_AS, 0x3}, ++ {OP_WR, XSEM_REG_TS_6_AS, 0x0}, ++ {OP_WR, XSEM_REG_TS_7_AS, 0x1}, ++ {OP_WR, XSEM_REG_TS_8_AS, 0x4}, ++ {OP_WR, XSEM_REG_TS_9_AS, 0x0}, ++ {OP_WR, XSEM_REG_TS_10_AS, 0x1}, ++ {OP_WR, XSEM_REG_TS_11_AS, 0x3}, ++ {OP_WR, XSEM_REG_TS_12_AS, 0x0}, ++ {OP_WR, XSEM_REG_TS_13_AS, 0x1}, ++ {OP_WR, XSEM_REG_TS_14_AS, 0x4}, ++ {OP_WR, XSEM_REG_TS_15_AS, 0x0}, ++ {OP_WR, XSEM_REG_TS_16_AS, 0x4}, ++ {OP_WR, XSEM_REG_TS_17_AS, 0x3}, ++ {OP_ZR, XSEM_REG_TS_18_AS, 0x2}, ++ {OP_WR, XSEM_REG_ENABLE_IN, 0x3fff}, ++ {OP_WR, XSEM_REG_ENABLE_OUT, 0x3ff}, ++ {OP_WR, XSEM_REG_FIC0_DISABLE, 0x0}, ++ {OP_WR, XSEM_REG_FIC1_DISABLE, 0x0}, ++ {OP_WR, XSEM_REG_PAS_DISABLE, 0x0}, ++ {OP_WR, XSEM_REG_THREADS_LIST, 0xffff}, ++ {OP_ZR, XSEM_REG_PASSIVE_BUFFER, 0x800}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x18bc0, 0x1}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x18000, 0x0}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66}, ++ {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, ++ {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18300, 0x138}, ++ {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18300, 0x1388}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, ++ {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4}, ++ {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18340, 0x0}, ++ {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18340, 0x5}, ++ {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4}, ++ {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500}, ++ {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3c40, 0x4}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x3c40 + 0x10, 0x202f8}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3000, 0x48}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1020, 0xc8}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1000, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3128, 0x8e}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x3368, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x3370, 0x202fa}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x3a70, 0x402fc}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x3d00, 0x20300}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x1500, 0x20302}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1500 + 0x8, 0x100}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x1970, 0x0}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x1978, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x1960, 0x20304}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x1f48, 0x20306}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100308}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80318}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80320}, ++/* #define XSEM_COMMON_END 617 */ ++/* #define XSEM_PORT0_START 618 */ ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3a80, 0x14}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3b20, 0x24}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1400, 0xa}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1450, 0x6}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3378, 0xd8}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x3a38, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x3c58, 0x20328}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x3c68, 0x10032a}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5020, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5030, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5010, 0x2}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x5040, 0x0}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5048, 0xe}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x2033a}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4}, ++/* #define XSEM_PORT0_END 619 */ ++/* #define XSEM_PORT1_START 620 */ ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3ad0, 0x14}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3bb0, 0x24}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1428, 0xa}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1468, 0x6}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x36d8, 0xd8}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x3a3c, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x3c60, 0x2033c}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x3ca8, 0x10033e}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5028, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5038, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5008, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5018, 0x2}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x5044, 0x0}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5080, 0xe}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2034e}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4}, ++/* #define XSEM_PORT1_END 621 */ ++/* #define CDU_COMMON_START 638 */ ++ {OP_WR, CDU_REG_CDU_CONTROL0, 0x1}, ++ {OP_WR, CDU_REG_CDU_DEBUG, 0x264}, ++ {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000}, ++ {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d}, ++ {OP_WB, CDU_REG_L1TT, 0x2000350}, ++ {OP_WB, CDU_REG_MATT, 0x200550}, ++ {OP_ZR, CDU_REG_MATT + 0x80, 0x2}, ++ {OP_WB, CDU_REG_MATT + 0x88, 0x60570}, ++ {OP_ZR, CDU_REG_MATT + 0xa0, 0x18}, ++ {OP_WR, CDU_REG_CDU_DEBUG, 0x0}, ++/* #define CDU_COMMON_END 639 */ ++/* #define DMAE_COMMON_START 660 */ ++ {OP_ZR, DMAE_REG_CMD_MEM, 0xe0}, ++ {OP_WR, DMAE_REG_CRC16C_INIT, 0x0}, ++ {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1}, ++ {OP_WR, DMAE_REG_PXP_REQ_INIT_CRD, 0x1}, ++ {OP_WR, DMAE_REG_PCI_IFEN, 0x1}, ++ {OP_WR, DMAE_REG_GRC_IFEN, 0x1}, ++/* #define DMAE_COMMON_END 661 */ ++/* #define PXP_COMMON_START 682 */ ++ {OP_WB, PXP_REG_HST_INBOUND_INT + 0x400, 0x50576}, ++ {OP_WB, PXP_REG_HST_INBOUND_INT + 0x420, 0x5057b}, ++ {OP_WB, PXP_REG_HST_INBOUND_INT, 0x50580}, ++/* #define PXP_COMMON_END 683 */ ++/* #define CFC_COMMON_START 704 */ ++ {OP_WR, CFC_REG_CONTROL0, 0x10}, ++ {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff}, ++ {OP_WR, CFC_REG_INTERFACES, 0x280000}, ++ {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a}, ++ {OP_WR, CFC_REG_INTERFACES, 0x0}, ++/* #define CFC_COMMON_END 705 */ ++/* #define HC_COMMON_START 726 */ ++ {OP_ZR, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4}, ++/* #define HC_COMMON_END 727 */ ++/* #define HC_PORT0_START 728 */ ++ {OP_WR, HC_REG_CONFIG_0, 0x1080}, ++ {OP_ZR, HC_REG_UC_RAM_ADDR_0, 0x2}, ++ {OP_WR, HC_REG_ATTN_NUM_P0, 0x10}, ++ {OP_WR, HC_REG_LEADING_EDGE_0, 0xffff}, ++ {OP_WR, HC_REG_TRAILING_EDGE_0, 0xffff}, ++ {OP_WR, HC_REG_AGG_INT_0, 0x0}, ++ {OP_WR, HC_REG_ATTN_IDX, 0x0}, ++ {OP_ZR, HC_REG_ATTN_BIT, 0x2}, ++ {OP_WR, HC_REG_VQID_0, 0x2b5}, ++ {OP_WR, HC_REG_PCI_CONFIG_0, 0x0}, ++ {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a}, ++ {OP_WR, HC_REG_INT_MASK, 0x1ffff}, ++ {OP_ZR, HC_REG_PBA_COMMAND, 0x2}, ++ {OP_WR, HC_REG_CONFIG_0, 0x1a80}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, ++/* #define HC_PORT0_END 729 */ ++/* #define HC_PORT1_START 730 */ ++ {OP_WR, HC_REG_CONFIG_1, 0x1080}, ++ {OP_ZR, HC_REG_UC_RAM_ADDR_1, 0x2}, ++ {OP_WR, HC_REG_ATTN_NUM_P1, 0x10}, ++ {OP_WR, HC_REG_LEADING_EDGE_1, 0xffff}, ++ {OP_WR, HC_REG_TRAILING_EDGE_1, 0xffff}, ++ {OP_WR, HC_REG_AGG_INT_1, 0x0}, ++ {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0}, ++ {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2}, ++ {OP_WR, HC_REG_VQID_1, 0x2b5}, ++ {OP_WR, HC_REG_PCI_CONFIG_1, 0x0}, ++ {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a}, ++ {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff}, ++ {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2}, ++ {OP_WR, HC_REG_CONFIG_1, 0x1a80}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, ++/* #define HC_PORT1_END 731 */ ++/* #define PXP2_COMMON_START 748 */ ++ {OP_WR, PXP2_REG_PGL_CONTROL0, 0xe38340}, ++ {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10}, ++ {OP_WR, PXP2_REG_PGL_DEBUG, 0x2}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_3, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_4, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_5, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_6, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_7, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_1, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_2, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_3, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_4, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_5, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_6, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_7, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_0, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_1, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_2, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_3, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_4, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_0, 0xffff3330}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_1, 0xffff3340}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_0, 0xf0003000}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8}, ++ {OP_ZR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x2}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ17, 0x4}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ25, 0x0}, ++ {OP_WR, PXP2_REG_RD_START_INIT, 0x1}, ++ {OP_WR, PXP2_REG_WR_DMAE_TH, 0x3f}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD3, 0x803}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD4, 0x40}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD5, 0x3}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD6, 0x803}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD7, 0x803}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD8, 0x803}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD9, 0x10003}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD10, 0x803}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD11, 0x803}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD12, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD13, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD14, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD15, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD16, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD17, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD18, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD19, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD20, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD22, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD23, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD24, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD25, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD26, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD27, 0x3}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD28, 0x2403}, ++ {OP_WR, PXP2_REG_RQ_BW_WR_ADD29, 0x2f}, ++ {OP_WR, PXP2_REG_RQ_BW_WR_ADD30, 0x9}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND0, 0x19}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB1, 0x184}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB2, 0x183}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB3, 0x306}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND4, 0x19}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND5, 0x6}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB6, 0x306}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB7, 0x306}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB8, 0x306}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB9, 0xc86}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB10, 0x306}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB11, 0x306}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND12, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND13, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND14, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND15, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND16, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND17, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND18, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND19, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND20, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND22, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND23, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND24, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND25, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND26, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND27, 0x6}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB28, 0x306}, ++ {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND29, 0x13}, ++ {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND30, 0x6}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_L1, 0x1004}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440}, ++ {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1}, ++/* #define PXP2_COMMON_END 749 */ ++/* #define MISC_AEU_COMMON_START 770 */ ++ {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16}, ++/* #define MISC_AEU_COMMON_END 771 */ ++/* #define MISC_AEU_PORT0_START 772 */ ++ {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef}, ++ {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0x500003e0}, ++ {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000}, ++ {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000}, ++ {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x14}, ++ {OP_WR, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555}, ++ {OP_WR, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_NIG_0, 0x0}, ++ {OP_WR, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555}, ++ {OP_WR, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_PXP_0, 0x0}, ++ {OP_WR, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0}, ++ {OP_ZR, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3}, ++ {OP_WR, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7}, ++/* #define MISC_AEU_PORT0_END 773 */ ++/* #define MISC_AEU_PORT1_START 774 */ ++ {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef}, ++ {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0x500003e0}, ++ {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000}, ++ {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000}, ++ {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x14}, ++ {OP_WR, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555}, ++ {OP_WR, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_NIG_1, 0x0}, ++ {OP_WR, MISC_REG_AEU_ENABLE1_PXP_1, 0x55540000}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_PXP_1, 0x55555555}, ++ {OP_WR, MISC_REG_AEU_ENABLE3_PXP_1, 0x5555}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_PXP_1, 0x0}, ++ {OP_WR, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0}, ++ {OP_ZR, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3}, ++ {OP_WR, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7}, ++/* #define MISC_AEU_PORT1_END 775 */ ++ ++}; ++ ++static const u16 init_ops_offsets_e1[] = { ++ 0x0000, 0x002e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x002e, ++ 0x0050, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0050, 0x008d, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x008d, 0x0092, ++ 0x0092, 0x0096, 0x0096, 0x009a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x009a, 0x00db, 0x00db, 0x00e9, 0x00e9, 0x00f7, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x00f7, 0x00fe, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x00fe, 0x0103, 0x0103, 0x010e, 0x010e, 0x0119, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0119, 0x011a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x011a, 0x0152, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0152, 0x0176, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0176, 0x01b5, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x01b5, 0x01f0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x01f0, 0x0235, 0x0235, 0x0238, 0x0238, ++ 0x023b, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x023b, ++ 0x0276, 0x0276, 0x0280, 0x0280, 0x028a, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x028a, 0x028b, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x028b, 0x029d, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x029d, 0x02b2, 0x02b2, 0x02b5, 0x02b5, 0x02b8, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x02b8, 0x02e6, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x02e6, 0x036d, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x036d, 0x0374, 0x0374, 0x0378, ++ 0x0378, 0x037c, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x037c, 0x03bb, 0x03bb, 0x03c3, 0x03c3, 0x03cb, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x03cb, 0x041f, 0x041f, 0x0431, 0x0431, ++ 0x0443, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0443, ++ 0x044d, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x044d, 0x0453, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0453, 0x0456, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0456, 0x045b, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x045b, 0x045c, 0x045c, ++ 0x046e, 0x046e, 0x0480, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0480, 0x04ed, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x04ed, 0x04ee, 0x04ee, 0x0502, ++ 0x0502, 0x0516, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 ++}; ++ ++static const u32 init_data_e1[] = { ++ 0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0, ++ 0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440, ++ 0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0, ++ 0x00135580, 0x00145a40, 0x00155f00, 0x001663c0, 0x00176880, 0x00186d40, ++ 0x00197200, 0x001a76c0, 0x001b7b80, 0x001c8040, 0x001d8500, 0x001e89c0, ++ 0x001f8e80, 0x00209340, 0x00002000, 0x00004000, 0x00006000, 0x00008000, ++ 0x0000a000, 0x0000c000, 0x0000e000, 0x00010000, 0x00012000, 0x00014000, ++ 0x00016000, 0x00018000, 0x0001a000, 0x0001c000, 0x0001e000, 0x00020000, ++ 0x00022000, 0x00024000, 0x00026000, 0x00028000, 0x0002a000, 0x0002c000, ++ 0x0002e000, 0x00030000, 0x00032000, 0x00034000, 0x00036000, 0x00038000, ++ 0x0003a000, 0x0003c000, 0x0003e000, 0x00040000, 0x00042000, 0x00044000, ++ 0x00046000, 0x00048000, 0x0004a000, 0x0004c000, 0x0004e000, 0x00050000, ++ 0x00052000, 0x00054000, 0x00056000, 0x00058000, 0x0005a000, 0x0005c000, ++ 0x0005e000, 0x00060000, 0x00062000, 0x00064000, 0x00066000, 0x00068000, ++ 0x0006a000, 0x0006c000, 0x0006e000, 0x00070000, 0x00072000, 0x00074000, ++ 0x00076000, 0x00078000, 0x0007a000, 0x0007c000, 0x0007e000, 0x00080000, ++ 0x00082000, 0x00084000, 0x00086000, 0x00088000, 0x0008a000, 0x0008c000, ++ 0x0008e000, 0x00090000, 0x00092000, 0x00094000, 0x00096000, 0x00098000, ++ 0x0009a000, 0x0009c000, 0x0009e000, 0x000a0000, 0x000a2000, 0x000a4000, ++ 0x000a6000, 0x000a8000, 0x000aa000, 0x000ac000, 0x000ae000, 0x000b0000, ++ 0x000b2000, 0x000b4000, 0x000b6000, 0x000b8000, 0x000ba000, 0x000bc000, ++ 0x000be000, 0x000c0000, 0x000c2000, 0x000c4000, 0x000c6000, 0x000c8000, ++ 0x000ca000, 0x000cc000, 0x000ce000, 0x000d0000, 0x000d2000, 0x000d4000, ++ 0x000d6000, 0x000d8000, 0x000da000, 0x000dc000, 0x000de000, 0x000e0000, ++ 0x000e2000, 0x000e4000, 0x000e6000, 0x000e8000, 0x000ea000, 0x000ec000, ++ 0x000ee000, 0x000f0000, 0x000f2000, 0x000f4000, 0x000f6000, 0x000f8000, ++ 0x000fa000, 0x000fc000, 0x000fe000, 0x00100000, 0x00102000, 0x00104000, ++ 0x00106000, 0x00108000, 0x0010a000, 0x0010c000, 0x0010e000, 0x00110000, ++ 0x00112000, 0x00114000, 0x00116000, 0x00118000, 0x0011a000, 0x0011c000, ++ 0x0011e000, 0x00120000, 0x00122000, 0x00124000, 0x00126000, 0x00128000, ++ 0x0012a000, 0x0012c000, 0x0012e000, 0x00130000, 0x00132000, 0x00134000, ++ 0x00136000, 0x00138000, 0x0013a000, 0x0013c000, 0x0013e000, 0x00140000, ++ 0x00142000, 0x00144000, 0x00146000, 0x00148000, 0x0014a000, 0x0014c000, ++ 0x0014e000, 0x00150000, 0x00152000, 0x00154000, 0x00156000, 0x00158000, ++ 0x0015a000, 0x0015c000, 0x0015e000, 0x00160000, 0x00162000, 0x00164000, ++ 0x00166000, 0x00168000, 0x0016a000, 0x0016c000, 0x0016e000, 0x00170000, ++ 0x00172000, 0x00174000, 0x00176000, 0x00178000, 0x0017a000, 0x0017c000, ++ 0x0017e000, 0x00180000, 0x00182000, 0x00184000, 0x00186000, 0x00188000, ++ 0x0018a000, 0x0018c000, 0x0018e000, 0x00190000, 0x00192000, 0x00194000, ++ 0x00196000, 0x00198000, 0x0019a000, 0x0019c000, 0x0019e000, 0x001a0000, ++ 0x001a2000, 0x001a4000, 0x001a6000, 0x001a8000, 0x001aa000, 0x001ac000, ++ 0x001ae000, 0x001b0000, 0x001b2000, 0x001b4000, 0x001b6000, 0x001b8000, ++ 0x001ba000, 0x001bc000, 0x001be000, 0x001c0000, 0x001c2000, 0x001c4000, ++ 0x001c6000, 0x001c8000, 0x001ca000, 0x001cc000, 0x001ce000, 0x001d0000, ++ 0x001d2000, 0x001d4000, 0x001d6000, 0x001d8000, 0x001da000, 0x001dc000, ++ 0x001de000, 0x001e0000, 0x001e2000, 0x001e4000, 0x001e6000, 0x001e8000, ++ 0x001ea000, 0x001ec000, 0x001ee000, 0x001f0000, 0x001f2000, 0x001f4000, ++ 0x001f6000, 0x001f8000, 0x001fa000, 0x001fc000, 0x001fe000, 0x00200000, ++ 0x00202000, 0x00204000, 0x00206000, 0x00208000, 0x0020a000, 0x0020c000, ++ 0x0020e000, 0x00210000, 0x00212000, 0x00214000, 0x00216000, 0x00218000, ++ 0x0021a000, 0x0021c000, 0x0021e000, 0x00220000, 0x00222000, 0x00224000, ++ 0x00226000, 0x00228000, 0x0022a000, 0x0022c000, 0x0022e000, 0x00230000, ++ 0x00232000, 0x00234000, 0x00236000, 0x00238000, 0x0023a000, 0x0023c000, ++ 0x0023e000, 0x00240000, 0x00242000, 0x00244000, 0x00246000, 0x00248000, ++ 0x0024a000, 0x0024c000, 0x0024e000, 0x00250000, 0x00252000, 0x00254000, ++ 0x00256000, 0x00258000, 0x0025a000, 0x0025c000, 0x0025e000, 0x00260000, ++ 0x00262000, 0x00264000, 0x00266000, 0x00268000, 0x0026a000, 0x0026c000, ++ 0x0026e000, 0x00270000, 0x00272000, 0x00274000, 0x00276000, 0x00278000, ++ 0x0027a000, 0x0027c000, 0x0027e000, 0x00280000, 0x00282000, 0x00284000, ++ 0x00286000, 0x00288000, 0x0028a000, 0x0028c000, 0x0028e000, 0x00290000, ++ 0x00292000, 0x00294000, 0x00296000, 0x00298000, 0x0029a000, 0x0029c000, ++ 0x0029e000, 0x002a0000, 0x002a2000, 0x002a4000, 0x002a6000, 0x002a8000, ++ 0x002aa000, 0x002ac000, 0x002ae000, 0x002b0000, 0x002b2000, 0x002b4000, ++ 0x002b6000, 0x002b8000, 0x002ba000, 0x002bc000, 0x002be000, 0x002c0000, ++ 0x002c2000, 0x002c4000, 0x002c6000, 0x002c8000, 0x002ca000, 0x002cc000, ++ 0x002ce000, 0x002d0000, 0x002d2000, 0x002d4000, 0x002d6000, 0x002d8000, ++ 0x002da000, 0x002dc000, 0x002de000, 0x002e0000, 0x002e2000, 0x002e4000, ++ 0x002e6000, 0x002e8000, 0x002ea000, 0x002ec000, 0x002ee000, 0x002f0000, ++ 0x002f2000, 0x002f4000, 0x002f6000, 0x002f8000, 0x002fa000, 0x002fc000, ++ 0x002fe000, 0x00300000, 0x00302000, 0x00304000, 0x00306000, 0x00308000, ++ 0x0030a000, 0x0030c000, 0x0030e000, 0x00310000, 0x00312000, 0x00314000, ++ 0x00316000, 0x00318000, 0x0031a000, 0x0031c000, 0x0031e000, 0x00320000, ++ 0x00322000, 0x00324000, 0x00326000, 0x00328000, 0x0032a000, 0x0032c000, ++ 0x0032e000, 0x00330000, 0x00332000, 0x00334000, 0x00336000, 0x00338000, ++ 0x0033a000, 0x0033c000, 0x0033e000, 0x00340000, 0x00342000, 0x00344000, ++ 0x00346000, 0x00348000, 0x0034a000, 0x0034c000, 0x0034e000, 0x00350000, ++ 0x00352000, 0x00354000, 0x00356000, 0x00358000, 0x0035a000, 0x0035c000, ++ 0x0035e000, 0x00360000, 0x00362000, 0x00364000, 0x00366000, 0x00368000, ++ 0x0036a000, 0x0036c000, 0x0036e000, 0x00370000, 0x00372000, 0x00374000, ++ 0x00376000, 0x00378000, 0x0037a000, 0x0037c000, 0x0037e000, 0x00380000, ++ 0x00382000, 0x00384000, 0x00386000, 0x00388000, 0x0038a000, 0x0038c000, ++ 0x0038e000, 0x00390000, 0x00392000, 0x00394000, 0x00396000, 0x00398000, ++ 0x0039a000, 0x0039c000, 0x0039e000, 0x003a0000, 0x003a2000, 0x003a4000, ++ 0x003a6000, 0x003a8000, 0x003aa000, 0x003ac000, 0x003ae000, 0x003b0000, ++ 0x003b2000, 0x003b4000, 0x003b6000, 0x003b8000, 0x003ba000, 0x003bc000, ++ 0x003be000, 0x003c0000, 0x003c2000, 0x003c4000, 0x003c6000, 0x003c8000, ++ 0x003ca000, 0x003cc000, 0x003ce000, 0x003d0000, 0x003d2000, 0x003d4000, ++ 0x003d6000, 0x003d8000, 0x003da000, 0x003dc000, 0x003de000, 0x003e0000, ++ 0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000, ++ 0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000, ++ 0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff, ++ 0x00000200, 0x00007ff8, 0x00007ff8, 0x0000026f, 0x00001500, 0x00000001, ++ 0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20, 0x00000001, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, ++ 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, ++ 0xffffffff, 0x00000003, 0x00bebc20, 0x00002000, 0x000040c0, 0x00006180, ++ 0x00008240, 0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, 0x00012600, ++ 0x000146c0, 0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, 0x0001ea80, ++ 0x00020b40, 0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, 0x0002af00, ++ 0x0002cfc0, 0x0002f080, 0x00031140, 0x00033200, 0x000352c0, 0x00037380, ++ 0x00039440, 0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, 0x00043800, ++ 0x000458c0, 0x00047980, 0x00049a40, 0x00008000, 0x00010380, 0x00018700, ++ 0x00020a80, 0x00028e00, 0x00031180, 0x00039500, 0x00041880, 0x00049c00, ++ 0x00051f80, 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 0x0007b100, ++ 0x00083480, 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 0x000ac600, ++ 0x000b4980, 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, 0x000ddb00, ++ 0x00007ff8, 0x00007ff8, 0x00000174, 0x00001500, 0x00001900, 0x00000000, ++ 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x00007ff8, 0x00007ff8, 0x00000509, ++ 0x00003500, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00001000, ++ 0x00002080, 0x00003100, 0x00004180, 0x00005200, 0x00006280, 0x00007300, ++ 0x00008380, 0x00009400, 0x0000a480, 0x0000b500, 0x0000c580, 0x0000d600, ++ 0x0000e680, 0x0000f700, 0x00010780, 0x00011800, 0x00012880, 0x00013900, ++ 0x00014980, 0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80, 0x00019c00, ++ 0x0001ac80, 0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80, 0x0001ff00, ++ 0x00007ff8, 0x00007ff8, 0x00000448, 0x00001500, 0x10000000, 0x000028ad, ++ 0x00000000, 0x00010001, 0x00150005, 0xccccccc1, 0xffffffff, 0xffffffff, ++ 0x7058103c, 0x00000000, 0x00000000, 0x00000001, 0xcccc0201, 0xcccccccc, ++ 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x000e01b7, 0x011600d6, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x00100000, 0x00000000, ++ 0x007201bb, 0x012300f3, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x00100000, 0x00000000, 0xfffffff3, 0x318fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x30efffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, ++ 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, ++ 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, ++ 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x302fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, ++ 0xfffffff3, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, ++ 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, ++ 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, ++ 0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x31efffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, ++ 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, ++ 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, ++ 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x056fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, ++ 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, ++ 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, ++ 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, ++ 0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, ++ 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, ++ 0xfffffff3, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, ++ 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, ++ 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, ++ 0xffffff97, 0x040fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, ++ 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x000c0000, 0x000700c0, ++ 0x00028130, 0x000b8158, 0x00020210, 0x00010230, 0x000f0240, 0x00010330, ++ 0x00080000, 0x00080080, 0x00028100, 0x000b8128, 0x000201e0, 0x00010200, ++ 0x00070210, 0x00020280, 0x000f0000, 0x000800f0, 0x00028170, 0x000b8198, ++ 0x00020250, 0x00010270, 0x000b8280, 0x00080338, 0x00100000, 0x00080100, ++ 0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298, 0x00080380, ++ 0x00028000, 0x000b8028, 0x000200e0, 0x00010100, 0x00008110, 0x00000118, ++ 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, ++ 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, ++ 0xcccccccc, 0xcccccccc, 0x00002000 ++}; ++ ++static const u8 tsem_int_table_data_e1[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xfb, 0x51, ++ 0xcf, 0xc0, 0xf0, 0x03, 0x8a, 0x7b, 0xd8, 0x18, 0x18, 0x36, 0x70, 0x20, ++ 0xf8, 0x43, 0x01, 0x5f, 0x64, 0x62, 0x60, 0xb8, 0x0c, 0xc4, 0x57, 0x81, ++ 0x58, 0x80, 0x99, 0x81, 0x21, 0x98, 0x91, 0x81, 0x21, 0x84, 0x91, 0x78, ++ 0xfd, 0x49, 0xa2, 0x08, 0xf6, 0x2b, 0x21, 0x06, 0x06, 0x31, 0x61, 0x06, ++ 0x86, 0x68, 0x41, 0xa0, 0xb9, 0xc2, 0x08, 0xf1, 0xa3, 0x40, 0x35, 0x56, ++ 0x22, 0x0c, 0x0c, 0x7f, 0xa1, 0x62, 0x8d, 0x40, 0x36, 0x9b, 0x28, 0x75, ++ 0xdc, 0x3f, 0xd0, 0x78, 0x93, 0x14, 0xa6, 0xd8, 0x7a, 0x09, 0x04, 0x7b, ++ 0x33, 0x16, 0x79, 0x64, 0xbc, 0x05, 0x4d, 0x9e, 0x4f, 0x12, 0x95, 0xbf, ++ 0x95, 0x80, 0xfe, 0x81, 0xc6, 0x8f, 0x15, 0x51, 0xf9, 0x62, 0x0a, 0x10, ++ 0x3a, 0x1f, 0x2a, 0xfe, 0x04, 0x4d, 0x5e, 0x1c, 0x2a, 0x7f, 0x19, 0xea, ++ 0xaf, 0xa7, 0x8a, 0xd8, 0xcd, 0xbd, 0x02, 0x95, 0x07, 0x00, 0xc8, 0xe9, ++ 0x67, 0x44, 0x60, 0x03, 0x00, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 tsem_pram_data_e1[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d, ++ 0x0b, 0x78, 0x54, 0xd5, 0xb5, 0xf0, 0x3e, 0x73, 0xce, 0x9c, 0x99, 0x49, ++ 0x66, 0x26, 0x27, 0x21, 0x4f, 0x1e, 0x61, 0x12, 0x20, 0x82, 0x86, 0x38, ++ 0xbc, 0x02, 0x28, 0xbd, 0x4e, 0x08, 0x44, 0xac, 0x5c, 0x0d, 0xf8, 0x42, ++ 0x8b, 0x3a, 0xbc, 0x43, 0xde, 0x50, 0xb4, 0xb4, 0xb5, 0x5f, 0x26, 0x10, ++ 0x22, 0x4f, 0x6f, 0xf0, 0x47, 0x45, 0x2f, 0xd8, 0xe1, 0x61, 0x45, 0x8b, ++ 0x36, 0x60, 0xa4, 0xd1, 0x02, 0x1d, 0x40, 0x10, 0x7b, 0xbd, 0xb7, 0xc1, ++ 0x52, 0x8b, 0xd5, 0xfa, 0x45, 0x54, 0x50, 0x0c, 0x24, 0x72, 0x8b, 0xd2, ++ 0x5b, 0x7b, 0xfd, 0xd7, 0x5a, 0x7b, 0xef, 0xcc, 0x39, 0x93, 0x09, 0x60, ++ 0xff, 0xf6, 0xfe, 0xf7, 0xbf, 0xdf, 0x1f, 0x3f, 0xbf, 0xc3, 0x3e, 0x67, ++ 0x3f, 0xd6, 0x5e, 0xaf, 0xbd, 0xd6, 0xda, 0x6b, 0xef, 0xb1, 0xb3, 0x34, ++ 0xa6, 0x0f, 0x64, 0xec, 0x6b, 0xfc, 0xbb, 0x81, 0xb1, 0x1a, 0x1b, 0x63, ++ 0xf0, 0xaa, 0xfb, 0xf9, 0x94, 0x9d, 0xdd, 0x5f, 0xea, 0x66, 0x2c, 0x6f, ++ 0xa3, 0x6f, 0xb9, 0x3b, 0x15, 0xde, 0xb7, 0xe6, 0xec, 0x4a, 0xf4, 0x31, ++ 0x96, 0xb5, 0x77, 0xbd, 0x32, 0x11, 0xde, 0x67, 0x6d, 0x6a, 0x52, 0x66, ++ 0xe7, 0x47, 0xdb, 0x8f, 0x76, 0xc1, 0xc7, 0x31, 0xf0, 0xbe, 0x75, 0xbd, ++ 0x52, 0x04, 0xef, 0xb3, 0xde, 0x6c, 0x52, 0x66, 0xe1, 0xd3, 0x61, 0x63, ++ 0x6d, 0x50, 0x9f, 0x69, 0xbe, 0x24, 0x86, 0x4f, 0x16, 0x60, 0x2c, 0x9d, ++ 0xb1, 0x41, 0xe3, 0x98, 0xf8, 0x0b, 0xb8, 0xb3, 0x0a, 0x19, 0xeb, 0x8f, ++ 0xff, 0x84, 0x2e, 0xce, 0x1b, 0x89, 0xd0, 0x19, 0x63, 0x39, 0x2b, 0x6c, ++ 0xe1, 0x90, 0x02, 0xef, 0x83, 0x65, 0x53, 0x99, 0x97, 0xb1, 0x6d, 0x00, ++ 0x57, 0x56, 0x0a, 0xb4, 0x53, 0xbf, 0x3a, 0x60, 0xc7, 0xba, 0xb5, 0xda, ++ 0xc9, 0x76, 0x27, 0x63, 0x4e, 0xcd, 0xa9, 0x7d, 0x9d, 0xcb, 0x58, 0xf6, ++ 0x0c, 0x66, 0x63, 0xf0, 0x1c, 0xb8, 0x94, 0xbf, 0xc7, 0xbf, 0xaf, 0xe1, ++ 0xff, 0x9c, 0x90, 0xb5, 0x3c, 0x88, 0x99, 0xca, 0x39, 0x58, 0xf6, 0xa4, ++ 0x9e, 0x82, 0x21, 0x99, 0x87, 0x79, 0xbe, 0x56, 0xe3, 0xc1, 0xdb, 0xa5, ++ 0x97, 0x0e, 0x8f, 0xce, 0x53, 0x3e, 0x37, 0xd5, 0xf9, 0xd2, 0xdd, 0x5a, ++ 0xcf, 0xf7, 0xf2, 0xb9, 0x78, 0xd1, 0x27, 0xfa, 0xc3, 0xd0, 0xfa, 0x69, ++ 0xac, 0x37, 0x98, 0xb1, 0x70, 0x4c, 0xfd, 0xaa, 0x90, 0xae, 0xb1, 0x6b, ++ 0xe1, 0x09, 0x08, 0x68, 0xce, 0xef, 0xd9, 0x7e, 0x2a, 0x2b, 0x2a, 0x44, ++ 0x3a, 0xdc, 0xc7, 0x26, 0xd2, 0xb3, 0x46, 0xf3, 0xdd, 0x85, 0x78, 0xa9, ++ 0x39, 0x6a, 0x67, 0x21, 0x80, 0xbb, 0xa6, 0xf6, 0x54, 0x09, 0x96, 0x59, ++ 0xab, 0xc2, 0x86, 0xe4, 0xf4, 0x6c, 0x3f, 0x9c, 0xd9, 0x89, 0x1e, 0x45, ++ 0x4c, 0xd1, 0x4e, 0xe1, 0x7c, 0xbd, 0xcc, 0x8b, 0xf3, 0x53, 0x2b, 0x7d, ++ 0x4f, 0x94, 0x00, 0x9e, 0xe7, 0x26, 0x06, 0x26, 0x61, 0xbf, 0xeb, 0x12, ++ 0x83, 0xf4, 0x94, 0xef, 0x33, 0x67, 0x4f, 0xc9, 0x0c, 0x02, 0x3c, 0xc5, ++ 0x0b, 0xf2, 0x43, 0x0c, 0xe8, 0x7e, 0x7e, 0xa3, 0xe2, 0x77, 0x40, 0xf3, ++ 0xd3, 0x4a, 0x58, 0xb7, 0x03, 0x3d, 0x2a, 0x6e, 0xaf, 0x2d, 0xb8, 0x11, ++ 0xea, 0xfd, 0x56, 0x0f, 0xde, 0x8c, 0xed, 0x2a, 0x67, 0xb4, 0x1d, 0x21, ++ 0x7a, 0xb0, 0xda, 0x3c, 0xc4, 0x53, 0x9b, 0xce, 0xf9, 0x67, 0x60, 0x6b, ++ 0xd1, 0xa7, 0x1a, 0xd0, 0x0d, 0x58, 0x2c, 0x94, 0x94, 0x82, 0x74, 0x61, ++ 0xec, 0xa4, 0x89, 0x0e, 0xf8, 0x77, 0x72, 0xa8, 0x28, 0xab, 0xbd, 0xe3, ++ 0xf1, 0x72, 0xcf, 0xb9, 0xd8, 0x8f, 0x86, 0xbd, 0x84, 0x69, 0xbe, 0xf2, ++ 0x7d, 0x4e, 0xe8, 0xe8, 0xa0, 0xc1, 0x31, 0xe3, 0xb1, 0x42, 0x82, 0x87, ++ 0x31, 0xe4, 0x71, 0xd6, 0xae, 0xc4, 0xa3, 0xeb, 0xc0, 0x57, 0x8a, 0x8e, ++ 0x6a, 0x05, 0xbd, 0x8f, 0xf7, 0xf7, 0x9f, 0x47, 0x88, 0xcb, 0x21, 0xe0, ++ 0x0e, 0xe9, 0x5b, 0xe5, 0xd1, 0xc3, 0xcb, 0x80, 0xbe, 0xc5, 0x2f, 0xdb, ++ 0x23, 0x37, 0x00, 0x3d, 0xaa, 0xb6, 0x28, 0x61, 0x07, 0x94, 0x6d, 0xfb, ++ 0x5d, 0x01, 0xa4, 0xcf, 0xb9, 0xed, 0x50, 0x06, 0xba, 0x44, 0x3c, 0x3a, ++ 0xd5, 0x3f, 0x6b, 0x38, 0xa9, 0x5c, 0xe3, 0x68, 0x7b, 0xe4, 0x7a, 0x28, ++ 0x77, 0xbd, 0xac, 0xb2, 0xad, 0xd8, 0xed, 0xd0, 0x04, 0x1b, 0xca, 0xdd, ++ 0x29, 0x01, 0x3b, 0x1b, 0x0d, 0x65, 0xc0, 0xc7, 0x7c, 0x17, 0x2f, 0x56, ++ 0x6d, 0x39, 0x70, 0x1f, 0xf6, 0x57, 0xd6, 0xea, 0x60, 0x2e, 0xe8, 0xbf, ++ 0xea, 0x95, 0x05, 0xb7, 0x5c, 0x0f, 0xe5, 0x05, 0xc0, 0x6f, 0x58, 0xa5, ++ 0xea, 0x99, 0x7a, 0xbd, 0x2f, 0x94, 0x17, 0x86, 0x95, 0x66, 0x2c, 0x77, ++ 0x4e, 0x64, 0xc4, 0x1f, 0xa1, 0x14, 0x3d, 0xfc, 0x0c, 0x8c, 0xd7, 0xe9, ++ 0x6d, 0x4b, 0xbf, 0x03, 0xe4, 0xe5, 0x4c, 0x9d, 0x93, 0xf9, 0x00, 0x94, ++ 0xe5, 0x9e, 0xb6, 0xf4, 0xdb, 0x81, 0x8f, 0xca, 0xc3, 0xbb, 0x4a, 0xb0, ++ 0x5d, 0xf9, 0x4e, 0xc5, 0x8f, 0x68, 0x2f, 0x7e, 0xf9, 0x99, 0x23, 0x59, ++ 0x38, 0xaf, 0xe7, 0x80, 0xaf, 0x80, 0x8f, 0x2a, 0x76, 0x24, 0x32, 0x9f, ++ 0xc4, 0x1f, 0xfc, 0x7f, 0x0a, 0xa6, 0x72, 0x03, 0x7c, 0x5f, 0x0c, 0xf3, ++ 0x44, 0xf9, 0x5f, 0xc0, 0x9a, 0x4a, 0x98, 0x8a, 0xe3, 0xaf, 0xd7, 0x7d, ++ 0x9e, 0x28, 0xbe, 0xce, 0xd4, 0x19, 0x34, 0x4e, 0xb7, 0x3c, 0x3d, 0x07, ++ 0xe3, 0x40, 0xbb, 0xea, 0x17, 0x15, 0x3f, 0x4e, 0xb1, 0xda, 0xc6, 0x82, ++ 0x28, 0x57, 0xe7, 0x5e, 0x71, 0xcd, 0xd8, 0xe6, 0xc6, 0xf9, 0xd5, 0xeb, ++ 0x79, 0x1e, 0x9c, 0xd7, 0xc3, 0x3a, 0xd6, 0x5b, 0x10, 0x9e, 0xb5, 0x07, ++ 0x55, 0x56, 0x79, 0x78, 0x8b, 0x5e, 0x02, 0xdf, 0xcb, 0x37, 0x6d, 0xd1, ++ 0xe7, 0xe7, 0x23, 0xde, 0x40, 0xef, 0xe5, 0x23, 0x5c, 0x7d, 0xac, 0x70, ++ 0x6d, 0x54, 0x03, 0x88, 0xdf, 0xc5, 0xc9, 0xce, 0xad, 0x2a, 0xe0, 0x87, ++ 0xb9, 0x03, 0x99, 0xd3, 0xe3, 0xf0, 0xcf, 0x99, 0x3a, 0x50, 0x63, 0x79, ++ 0xd1, 0x72, 0x39, 0xca, 0x37, 0xe9, 0x93, 0xb0, 0x3e, 0xcd, 0x54, 0xbf, ++ 0x44, 0x49, 0x26, 0x7e, 0xad, 0xd8, 0xa1, 0x32, 0x9f, 0x85, 0x9f, 0x38, ++ 0xfd, 0x43, 0xc7, 0x38, 0xfd, 0x43, 0xfb, 0x3c, 0xe1, 0x67, 0x72, 0xa2, ++ 0xf4, 0x5b, 0x6c, 0x70, 0x3d, 0x29, 0xe9, 0xb7, 0x38, 0x59, 0xd0, 0x53, ++ 0xeb, 0x2a, 0x8c, 0x07, 0xcf, 0x23, 0x48, 0x0f, 0x80, 0xa7, 0x09, 0xf1, ++ 0x05, 0xcf, 0xb5, 0x02, 0x3e, 0xef, 0x04, 0x56, 0xa4, 0x01, 0x5d, 0xbc, ++ 0x01, 0x66, 0x28, 0xec, 0xf2, 0xfc, 0xd9, 0x64, 0x67, 0xb3, 0x18, 0x8c, ++ 0xfd, 0x16, 0x9b, 0x17, 0xd0, 0xc6, 0x43, 0x59, 0x67, 0x8b, 0x98, 0x9f, ++ 0x31, 0x43, 0xab, 0x0a, 0x4c, 0x82, 0xf2, 0x57, 0xac, 0xf4, 0x4d, 0x9c, ++ 0x0f, 0x63, 0x7e, 0x5f, 0x29, 0xe0, 0xb9, 0x51, 0x61, 0x33, 0x70, 0xde, ++ 0x87, 0x11, 0x58, 0x98, 0x4f, 0x63, 0x96, 0x4e, 0xf8, 0x6b, 0x9a, 0x5c, ++ 0xb8, 0x4d, 0x55, 0x04, 0xcc, 0xa9, 0x58, 0x9e, 0xff, 0x93, 0xd5, 0x39, ++ 0xd4, 0xfe, 0x38, 0xb5, 0xd7, 0xa0, 0xfd, 0xf0, 0xde, 0xdb, 0x1b, 0x25, ++ 0xe3, 0x2c, 0xed, 0x8d, 0x92, 0x32, 0xd9, 0xfe, 0x3d, 0xac, 0xc7, 0x9c, ++ 0x97, 0x6e, 0xdf, 0x54, 0x72, 0x9d, 0x75, 0xfc, 0x92, 0x72, 0xd9, 0xfe, ++ 0x23, 0x1a, 0xdf, 0x7d, 0x69, 0xf8, 0x8d, 0x1b, 0x27, 0x58, 0xc7, 0xbf, ++ 0xb1, 0x92, 0xda, 0xd7, 0x38, 0x38, 0xbd, 0xba, 0x92, 0x9d, 0xe1, 0xad, ++ 0x50, 0x6e, 0x70, 0xf9, 0x03, 0x1a, 0xd2, 0x4d, 0x63, 0x11, 0x7c, 0xaf, ++ 0xa5, 0xe4, 0x6d, 0xc5, 0x7a, 0xaa, 0xe4, 0x07, 0xd6, 0x16, 0x50, 0xa1, ++ 0xbd, 0x7b, 0x67, 0xf2, 0xc8, 0xd5, 0xcc, 0xcc, 0x17, 0x13, 0xff, 0x88, ++ 0xe3, 0x79, 0x40, 0x5a, 0xcc, 0x7c, 0x91, 0x34, 0x2e, 0xc1, 0xc2, 0x8f, ++ 0xc9, 0x81, 0x14, 0x4b, 0x19, 0x7a, 0x32, 0x4e, 0x5d, 0x13, 0xd5, 0x43, ++ 0x01, 0xaf, 0x93, 0xe0, 0xd1, 0xfb, 0xea, 0xa4, 0x2f, 0x8a, 0xfa, 0x3a, ++ 0x09, 0xde, 0x07, 0xf7, 0xbb, 0xa8, 0xfc, 0xe0, 0x75, 0x1c, 0xde, 0x07, ++ 0xfb, 0xba, 0x49, 0xce, 0x10, 0x06, 0x96, 0x05, 0x65, 0x3d, 0x78, 0xad, ++ 0x61, 0x5a, 0x8f, 0x00, 0x4e, 0x85, 0x65, 0x32, 0x76, 0x41, 0x09, 0xba, ++ 0x94, 0x31, 0xe6, 0xf7, 0x3e, 0x1b, 0xbe, 0x4f, 0x50, 0x59, 0x2d, 0xce, ++ 0x27, 0xc1, 0xc1, 0x48, 0x1f, 0x3d, 0x9c, 0x53, 0xb8, 0x2d, 0x64, 0xc2, ++ 0xcf, 0xca, 0x01, 0x40, 0x5f, 0x28, 0xa7, 0x2a, 0x3a, 0xc7, 0xa3, 0xc0, ++ 0xeb, 0xc3, 0x03, 0xe6, 0x67, 0xce, 0x32, 0x8d, 0xd3, 0x38, 0x40, 0x9f, ++ 0xb1, 0x35, 0x9f, 0xbf, 0x9f, 0xe3, 0xc6, 0xf1, 0x4a, 0xd3, 0x15, 0xd4, ++ 0x83, 0x7a, 0x57, 0x9e, 0xe1, 0xee, 0x39, 0x8e, 0x23, 0x77, 0x9c, 0x65, ++ 0x1c, 0x67, 0x76, 0x19, 0x8d, 0x93, 0x13, 0x33, 0x8e, 0x23, 0xbb, 0x2c, ++ 0x66, 0x1c, 0xe7, 0x8c, 0xad, 0xe2, 0xbd, 0x18, 0x67, 0xd0, 0xa5, 0xc6, ++ 0x79, 0x38, 0xf7, 0x3a, 0xeb, 0x7c, 0xb2, 0xcb, 0x69, 0x9c, 0x82, 0xd8, ++ 0xf9, 0x64, 0x97, 0xc7, 0x8c, 0x93, 0xc0, 0xe7, 0x03, 0xef, 0xc5, 0x38, ++ 0x7e, 0xc4, 0x5f, 0xaf, 0xf3, 0x19, 0x34, 0xc1, 0x3a, 0x9f, 0x81, 0x95, ++ 0x34, 0xce, 0xf5, 0x38, 0xce, 0x18, 0xd3, 0x7c, 0x06, 0x56, 0xc6, 0x8c, ++ 0xe3, 0xa6, 0x71, 0xf0, 0x3d, 0x8e, 0x03, 0x86, 0x94, 0x8f, 0x65, 0x00, ++ 0xdd, 0x1d, 0x5d, 0xf3, 0x89, 0xfe, 0xbf, 0x74, 0x91, 0xbd, 0xa0, 0x3b, ++ 0x82, 0xcf, 0x62, 0xbf, 0xec, 0x5d, 0x17, 0x23, 0x7d, 0xe2, 0x83, 0x71, ++ 0x33, 0x50, 0xaf, 0xc0, 0xe2, 0x0c, 0xf2, 0xab, 0x29, 0x29, 0x34, 0xce, ++ 0x17, 0x09, 0x40, 0x7f, 0xb7, 0x99, 0xce, 0x5c, 0x1f, 0xd1, 0x13, 0xf4, ++ 0xcf, 0x3c, 0x01, 0x22, 0x0b, 0x03, 0x44, 0xa0, 0x7f, 0xaa, 0x05, 0x8f, ++ 0xce, 0xdd, 0x39, 0x2d, 0xbb, 0x1e, 0x9f, 0xad, 0xc5, 0x99, 0xb3, 0xd0, ++ 0x2e, 0xd9, 0xe0, 0xf1, 0x0f, 0x01, 0xd1, 0x39, 0xd7, 0x5a, 0xac, 0xcf, ++ 0x89, 0x63, 0xdf, 0xcc, 0x6b, 0xb2, 0x9f, 0x6a, 0xb7, 0xf0, 0xaf, 0xd0, ++ 0x7b, 0x13, 0xd9, 0xd0, 0x5a, 0x18, 0xbf, 0x05, 0x95, 0x8d, 0xa9, 0x7c, ++ 0x0a, 0xf4, 0x17, 0x03, 0xbd, 0x75, 0x12, 0xf4, 0x17, 0x3e, 0x4f, 0x0b, ++ 0xfb, 0xf4, 0x23, 0xd0, 0x6f, 0x4c, 0x37, 0xc3, 0x5b, 0x4f, 0xf3, 0x38, ++ 0xa5, 0x71, 0x3c, 0x9e, 0xda, 0xc4, 0xd7, 0x91, 0x2f, 0xd6, 0x1f, 0xb3, ++ 0x83, 0xb1, 0x87, 0xc3, 0x1c, 0xcf, 0x07, 0xb8, 0xef, 0x14, 0xd3, 0x98, ++ 0xd7, 0x04, 0xc6, 0x9f, 0x49, 0xce, 0x6a, 0x04, 0x3d, 0xba, 0x5e, 0x71, ++ 0x84, 0xb7, 0x12, 0x3d, 0x02, 0xfd, 0x6c, 0xc0, 0xe7, 0x6c, 0x63, 0x1f, ++ 0xc0, 0x95, 0xa8, 0x07, 0x76, 0xe6, 0x1f, 0x84, 0x3d, 0x0a, 0x7f, 0xfd, ++ 0x6c, 0x60, 0xcb, 0xde, 0xb3, 0x72, 0xd7, 0x61, 0xac, 0xf6, 0xb6, 0x32, ++ 0x6b, 0xc0, 0x62, 0x98, 0xef, 0x8c, 0x96, 0xf5, 0xf6, 0x7e, 0x50, 0x3e, ++ 0x67, 0x6f, 0xbf, 0xcf, 0xef, 0x36, 0xf5, 0x33, 0xc3, 0x7e, 0x12, 0xe7, ++ 0xed, 0x84, 0xff, 0xb0, 0x9f, 0xbb, 0x83, 0x76, 0x8b, 0x7d, 0xfa, 0x9d, ++ 0x32, 0x6b, 0xf9, 0xde, 0x18, 0x7b, 0xb5, 0x52, 0xc9, 0x15, 0xf4, 0x10, ++ 0xe3, 0xfa, 0xc2, 0x76, 0xa4, 0xd7, 0x9d, 0xe9, 0x1c, 0x9e, 0x7b, 0xf1, ++ 0x39, 0x12, 0x3f, 0x1b, 0x44, 0xaf, 0xfb, 0x0c, 0xde, 0x56, 0xc2, 0x53, ++ 0xf3, 0x43, 0x3b, 0x8b, 0xd0, 0x7a, 0xd4, 0x9e, 0xc6, 0xf2, 0x11, 0x1f, ++ 0x69, 0x64, 0x17, 0x05, 0xe5, 0xba, 0x12, 0x03, 0xdf, 0x7d, 0x76, 0x67, ++ 0xa0, 0x14, 0xe8, 0x79, 0xdf, 0xf7, 0x55, 0xc2, 0x63, 0x2c, 0xbc, 0xed, ++ 0xfb, 0x13, 0x03, 0x36, 0xb0, 0x97, 0xda, 0x37, 0xfe, 0xbb, 0x1d, 0xed, ++ 0xef, 0xcb, 0xc1, 0x7f, 0xff, 0x52, 0xeb, 0x77, 0x16, 0xe2, 0xe3, 0x49, ++ 0xbc, 0x4a, 0x3e, 0xb8, 0x6b, 0x46, 0x51, 0x9f, 0x8f, 0x4c, 0xf5, 0xee, ++ 0x0e, 0xde, 0xd4, 0xe7, 0x23, 0x13, 0xbf, 0x7c, 0xa7, 0x6c, 0x9a, 0xa5, ++ 0x7c, 0x6f, 0xed, 0xdd, 0x96, 0xfa, 0xf7, 0x2f, 0x9d, 0x65, 0xf9, 0x3e, ++ 0x2b, 0xb4, 0xd0, 0xf2, 0x7d, 0xce, 0xca, 0x45, 0x96, 0xf2, 0xbc, 0xa6, ++ 0xef, 0x5b, 0xea, 0x2f, 0xd8, 0x58, 0x6f, 0xf9, 0xbe, 0x30, 0xbc, 0xca, ++ 0xf2, 0xbd, 0x62, 0xc7, 0x7a, 0x4b, 0xb9, 0xaa, 0xf9, 0x49, 0x4b, 0xfd, ++ 0x9a, 0xd6, 0x2d, 0x96, 0xef, 0xb6, 0xfd, 0xc3, 0x6e, 0x45, 0x79, 0x5c, ++ 0xfe, 0x5b, 0x95, 0xa1, 0x7d, 0x76, 0xc1, 0x7d, 0xea, 0x11, 0xb4, 0xaf, ++ 0x2e, 0x18, 0x9a, 0x1f, 0xeb, 0x54, 0x23, 0xaf, 0x81, 0x1c, 0x7e, 0x52, ++ 0x97, 0x49, 0xfc, 0x7d, 0xa6, 0xce, 0x47, 0xcf, 0x73, 0xad, 0xa3, 0x9c, ++ 0x68, 0x8f, 0xd7, 0x24, 0x80, 0x3c, 0xc3, 0x5a, 0xbf, 0x5f, 0xf9, 0x43, ++ 0x68, 0xe5, 0x04, 0xd4, 0x23, 0x50, 0x1f, 0x74, 0xf8, 0x41, 0xe5, 0xc3, ++ 0x50, 0x08, 0x9c, 0xa7, 0x37, 0x14, 0x1f, 0xf1, 0xbd, 0xba, 0x51, 0x67, ++ 0x11, 0x60, 0x55, 0x85, 0xa5, 0x74, 0xf3, 0x75, 0x97, 0x1a, 0xfd, 0xae, ++ 0xb5, 0xc3, 0xf7, 0x51, 0xbd, 0x7f, 0x57, 0x37, 0x6a, 0x71, 0xbf, 0x6b, ++ 0xed, 0x5a, 0xdc, 0x7e, 0x3b, 0x95, 0xae, 0x3c, 0xb4, 0xef, 0x42, 0xef, ++ 0x38, 0x18, 0xda, 0x81, 0xbd, 0xd9, 0x0f, 0xf0, 0xd7, 0x0f, 0xd7, 0x8b, ++ 0xde, 0xbe, 0x77, 0xd8, 0x58, 0x59, 0xb3, 0x49, 0xef, 0x9c, 0x52, 0x6c, ++ 0xc4, 0x07, 0x77, 0x2a, 0x13, 0x4f, 0xa1, 0x7e, 0xae, 0xd4, 0xb9, 0xbc, ++ 0x57, 0xee, 0xce, 0x9a, 0x88, 0xfe, 0x60, 0xa5, 0x1e, 0xc9, 0xab, 0x75, ++ 0x5f, 0x62, 0xbc, 0x66, 0x00, 0x26, 0x03, 0xfb, 0xc9, 0xa5, 0x79, 0x2d, ++ 0x0c, 0xf7, 0x8b, 0xca, 0x2f, 0xd1, 0x6f, 0x90, 0x45, 0xee, 0x97, 0xb0, ++ 0xe0, 0xc7, 0xa8, 0x9f, 0x3b, 0x0e, 0xa8, 0xa4, 0x67, 0x59, 0xe4, 0x50, ++ 0xf6, 0x6d, 0xc3, 0x71, 0xfc, 0xc0, 0x29, 0x7c, 0xcf, 0x5a, 0xd3, 0x68, ++ 0x7d, 0x7c, 0xbb, 0x2e, 0xd0, 0xe7, 0x23, 0xf0, 0xe7, 0x4e, 0xd4, 0x4d, ++ 0xa1, 0xe7, 0xef, 0xeb, 0x4a, 0xfb, 0x7c, 0x04, 0xba, 0xe6, 0xbd, 0xba, ++ 0x19, 0x54, 0x7e, 0xbf, 0x2e, 0x48, 0xcf, 0xf6, 0xba, 0x32, 0x7a, 0x9e, ++ 0xac, 0xab, 0xa5, 0xef, 0x1f, 0xd5, 0x2d, 0xa5, 0xf2, 0xa9, 0xba, 0x10, ++ 0x3d, 0x3f, 0xa9, 0x5b, 0x49, 0xcf, 0x33, 0x75, 0x4d, 0xf4, 0xbd, 0xa3, ++ 0x6e, 0x23, 0x95, 0xcf, 0xd5, 0x85, 0xe9, 0xd9, 0xed, 0x07, 0x08, 0x7b, ++ 0x94, 0xa5, 0x0a, 0xfb, 0x4f, 0xd8, 0xeb, 0xb0, 0x72, 0x50, 0xf9, 0xbc, ++ 0x98, 0x83, 0x0a, 0xff, 0xe6, 0x7e, 0xab, 0x3f, 0x13, 0xe5, 0xfa, 0xbc, ++ 0xfb, 0x8b, 0x3c, 0xb4, 0x73, 0xcf, 0x9f, 0x00, 0xc3, 0x24, 0x8e, 0x7f, ++ 0x28, 0x9f, 0xb1, 0xfc, 0xd6, 0x3b, 0xfd, 0x02, 0xb4, 0xde, 0xcf, 0x0f, ++ 0x03, 0xfd, 0x47, 0xf5, 0xfc, 0xee, 0x4a, 0xe0, 0xf4, 0x71, 0xd9, 0xd8, ++ 0x14, 0x06, 0xfa, 0x67, 0xd5, 0x10, 0x9d, 0x69, 0x30, 0x7e, 0xc2, 0x2f, ++ 0xaf, 0x21, 0x7b, 0x19, 0xde, 0x6b, 0x8c, 0xf4, 0x65, 0xd8, 0x3f, 0xcd, ++ 0x13, 0xa7, 0x7f, 0x9c, 0x73, 0xc6, 0xe5, 0xe9, 0xd4, 0xcd, 0x1f, 0x4f, ++ 0xfd, 0xb9, 0x10, 0xe3, 0x0f, 0x77, 0x0a, 0x7d, 0x98, 0x70, 0x48, 0xad, ++ 0xe5, 0x74, 0xdb, 0xe6, 0x47, 0xba, 0x99, 0xf0, 0xc7, 0xed, 0xb2, 0x97, ++ 0x85, 0x3e, 0x8f, 0xc1, 0x23, 0xd9, 0x72, 0x59, 0x3d, 0xf1, 0x79, 0x36, ++ 0x4d, 0xe2, 0xb3, 0x2d, 0x1b, 0xe3, 0x00, 0x1b, 0x94, 0xd2, 0x61, 0x36, ++ 0xe0, 0x83, 0xf3, 0x2d, 0x0e, 0x9a, 0xd7, 0xf9, 0xbd, 0x89, 0x61, 0x86, ++ 0x6d, 0x31, 0x38, 0x32, 0xfe, 0x52, 0x78, 0xe3, 0x70, 0x54, 0xec, 0x70, ++ 0x19, 0x66, 0xfd, 0x50, 0xd5, 0x9c, 0x6c, 0x58, 0xf5, 0x45, 0x96, 0x61, ++ 0xd6, 0x17, 0xe7, 0x8f, 0x6e, 0xf3, 0xa2, 0xdc, 0x2f, 0xce, 0xb4, 0x19, ++ 0x1f, 0x8d, 0x42, 0xfe, 0x08, 0x08, 0xfe, 0xe0, 0x7c, 0x27, 0xfb, 0xaf, ++ 0x6a, 0xce, 0x31, 0xdc, 0x96, 0x7e, 0xac, 0xe5, 0xf3, 0x4d, 0xca, 0x14, ++ 0xf4, 0x83, 0x40, 0xb9, 0x27, 0xdd, 0x1e, 0xc7, 0x3f, 0x90, 0xcf, 0xc5, ++ 0x99, 0xba, 0xf1, 0x11, 0xc8, 0xf7, 0x99, 0x1d, 0x83, 0x92, 0x70, 0x5c, ++ 0xf0, 0xe3, 0x0c, 0x1c, 0xa7, 0xa3, 0xce, 0x30, 0xf8, 0xb8, 0x99, 0x86, ++ 0x99, 0x2f, 0x2b, 0x97, 0x26, 0x50, 0x7d, 0x09, 0x5f, 0x6f, 0xfd, 0xfe, ++ 0xad, 0xe1, 0x43, 0xcb, 0xe0, 0x43, 0x27, 0x23, 0xd4, 0x7f, 0x3d, 0xe8, ++ 0x9b, 0xfb, 0xd9, 0x4c, 0xfb, 0x23, 0xc5, 0x73, 0xd8, 0x5e, 0xfb, 0x17, ++ 0xb8, 0xee, 0x38, 0xe0, 0xff, 0xaf, 0x29, 0x1e, 0xa0, 0x51, 0x59, 0xf6, ++ 0x5b, 0xd3, 0xac, 0x86, 0x1c, 0xd7, 0xe2, 0xfb, 0x9d, 0x96, 0xf1, 0xa0, ++ 0x9d, 0x4f, 0xfa, 0xd0, 0xb8, 0x5e, 0xf5, 0x4e, 0x77, 0x8d, 0x9d, 0x32, ++ 0xc5, 0x05, 0xaa, 0x71, 0x0c, 0xf2, 0x8f, 0x9c, 0x44, 0xe7, 0x20, 0xf4, ++ 0x98, 0x04, 0xfd, 0x75, 0x6a, 0xee, 0x95, 0x0a, 0x8c, 0x33, 0xc5, 0xe6, ++ 0xa3, 0xef, 0x35, 0x82, 0x1f, 0xab, 0x9c, 0xed, 0x7a, 0x10, 0x5e, 0x9d, ++ 0x6d, 0xe1, 0xf4, 0xe8, 0x6d, 0x9c, 0x33, 0x75, 0x47, 0x7d, 0x1a, 0xe8, ++ 0x8f, 0x32, 0x27, 0x78, 0x64, 0x30, 0x4e, 0x59, 0xf3, 0xb0, 0x49, 0xa8, ++ 0x1f, 0xcf, 0xb6, 0x2c, 0x4f, 0x0f, 0x02, 0xdf, 0x56, 0xa8, 0xe7, 0x1f, ++ 0x2c, 0x8d, 0xd3, 0x7e, 0xa5, 0x4d, 0xe1, 0xf0, 0x84, 0xed, 0x5d, 0xed, ++ 0xa6, 0xf9, 0xc8, 0x38, 0x0a, 0x63, 0xd0, 0xaf, 0x33, 0x0a, 0x3f, 0x72, ++ 0xfa, 0x29, 0x53, 0x39, 0x56, 0x5f, 0xcb, 0xe7, 0xa3, 0xd8, 0x2f, 0xf0, ++ 0x47, 0xf5, 0xce, 0x63, 0x25, 0xd7, 0x03, 0xfc, 0xd5, 0xad, 0x9f, 0xeb, ++ 0x08, 0xc7, 0x14, 0x5b, 0xf0, 0x51, 0x5b, 0x5a, 0x74, 0xfe, 0x0a, 0xce, ++ 0x1f, 0xfa, 0x29, 0xdf, 0xf1, 0x81, 0x8e, 0xf3, 0xfb, 0xc4, 0x1e, 0xca, ++ 0xfb, 0xe1, 0x25, 0xf4, 0x54, 0x4f, 0x38, 0xdd, 0x99, 0x14, 0xb7, 0x93, ++ 0xf0, 0x85, 0x58, 0x1b, 0xda, 0x31, 0xb3, 0xbb, 0xe3, 0x8a, 0xbe, 0xbb, ++ 0xde, 0x05, 0xd1, 0xfc, 0xf4, 0x5f, 0xec, 0x6c, 0x35, 0xc0, 0xc1, 0xbe, ++ 0x82, 0x5a, 0xf0, 0xdd, 0x2e, 0xbe, 0xce, 0x65, 0xa5, 0x5e, 0xc4, 0xd7, ++ 0xec, 0x96, 0x0a, 0x8a, 0x2f, 0x7e, 0x6a, 0x93, 0x76, 0x53, 0x53, 0x21, ++ 0xf2, 0xc7, 0x59, 0x66, 0x9b, 0x82, 0xf3, 0x3b, 0xcb, 0xde, 0xf2, 0x8e, ++ 0x32, 0xe1, 0xaf, 0xc5, 0xc6, 0xed, 0x7e, 0xb6, 0x92, 0xdb, 0x31, 0x21, ++ 0xf8, 0x0f, 0xe1, 0x01, 0x7b, 0xd6, 0x62, 0xd7, 0x2c, 0xd8, 0x68, 0x2d, ++ 0xcf, 0x67, 0xd3, 0xd3, 0x51, 0x6f, 0xcc, 0xdf, 0x60, 0x67, 0x61, 0x40, ++ 0xd1, 0x42, 0xb4, 0x8b, 0x24, 0x7f, 0xc0, 0xbc, 0xb7, 0xdb, 0xb8, 0xbd, ++ 0xbb, 0x80, 0xd5, 0x36, 0xa2, 0x3d, 0xa7, 0x39, 0xb8, 0x7f, 0x30, 0xdb, ++ 0x60, 0x5a, 0x3f, 0x80, 0xab, 0xea, 0xe7, 0x9b, 0x0b, 0xd1, 0xee, 0xff, ++ 0x85, 0xcd, 0x46, 0xf4, 0x91, 0x71, 0x86, 0x85, 0x29, 0x1c, 0xee, 0xf2, ++ 0xd4, 0xb0, 0x1e, 0x80, 0xef, 0x1f, 0xb6, 0x8c, 0xba, 0xf3, 0x7a, 0xe4, ++ 0x3e, 0x47, 0xb8, 0x11, 0xd7, 0x65, 0x96, 0xc4, 0xfc, 0xcf, 0xb0, 0x9e, ++ 0xf8, 0x9c, 0xb3, 0xd2, 0x0a, 0xdf, 0xe5, 0xe0, 0x8f, 0x85, 0x97, 0xb1, ++ 0x65, 0x16, 0x38, 0x64, 0xbf, 0x12, 0x0e, 0x75, 0x87, 0x12, 0x08, 0xc7, ++ 0xe1, 0xbb, 0x37, 0x24, 0xdf, 0x09, 0x3d, 0x92, 0xa2, 0x5a, 0xed, 0xfc, ++ 0x8c, 0x98, 0xf2, 0x7b, 0x36, 0x11, 0xbf, 0x54, 0x99, 0x8a, 0x74, 0x3e, ++ 0x6b, 0x38, 0x43, 0xb6, 0x24, 0xfa, 0xee, 0x8f, 0x60, 0x7c, 0x64, 0xb7, ++ 0xc3, 0xbf, 0x1c, 0xe8, 0xfb, 0x80, 0xad, 0xb4, 0x1d, 0xf5, 0x33, 0xd8, ++ 0x05, 0x05, 0xcc, 0x54, 0xef, 0x01, 0x5b, 0x90, 0xde, 0x77, 0x28, 0x6f, ++ 0xce, 0x47, 0xfb, 0x94, 0x69, 0x91, 0x02, 0xf4, 0xef, 0x61, 0x4d, 0xd1, ++ 0x90, 0x1f, 0x74, 0xc1, 0x0f, 0x6a, 0x82, 0xb7, 0x00, 0xe3, 0xb1, 0x1e, ++ 0x06, 0xeb, 0x27, 0xc8, 0xa5, 0x03, 0xe1, 0x83, 0x7e, 0x1a, 0x3d, 0x65, ++ 0x53, 0x59, 0x01, 0xc6, 0x5f, 0x41, 0x4e, 0xa1, 0xbf, 0x75, 0xde, 0x92, ++ 0xa3, 0x0a, 0x94, 0x5d, 0xee, 0x16, 0x86, 0xfd, 0x39, 0x32, 0xad, 0xf1, ++ 0x65, 0x97, 0xcf, 0x5a, 0xae, 0xc1, 0x7f, 0x20, 0x1d, 0x86, 0x32, 0x8a, ++ 0xe3, 0x24, 0x0e, 0xb5, 0x7e, 0x87, 0x05, 0x8b, 0x21, 0xbf, 0x79, 0xfc, ++ 0xd6, 0xf7, 0xff, 0xd1, 0x8d, 0xa7, 0x08, 0xf1, 0xad, 0x97, 0x58, 0x1a, ++ 0x9e, 0x4e, 0x77, 0x44, 0x85, 0xf1, 0xd9, 0x38, 0xad, 0xc3, 0x6c, 0x37, ++ 0x57, 0x3b, 0x39, 0xfc, 0xe4, 0x97, 0x43, 0xfd, 0x25, 0xc2, 0x9e, 0xaf, ++ 0x66, 0xbe, 0x10, 0xc5, 0x89, 0x33, 0x39, 0x1f, 0x2c, 0xb9, 0xc9, 0x46, ++ 0xf0, 0x2c, 0xf1, 0xf8, 0xfc, 0x21, 0xf8, 0xae, 0x68, 0x01, 0x86, 0xf2, ++ 0x87, 0xb1, 0x6a, 0xf3, 0x3a, 0x56, 0x73, 0x11, 0x44, 0xae, 0x8f, 0xa9, ++ 0xac, 0x75, 0xe9, 0xc8, 0x97, 0x35, 0x17, 0x35, 0x16, 0x06, 0x7d, 0x5f, ++ 0x60, 0x0b, 0x7a, 0xd4, 0x31, 0x88, 0xbf, 0x00, 0xd9, 0xb9, 0x4e, 0x40, ++ 0xd6, 0xd7, 0x00, 0xb2, 0xe6, 0x9e, 0x62, 0xb1, 0x7b, 0x59, 0xff, 0x14, ++ 0xb1, 0xbe, 0xf6, 0x37, 0xcc, 0xf2, 0xda, 0x1f, 0xe9, 0x3c, 0x26, 0x4a, ++ 0x67, 0xa9, 0x17, 0xec, 0x42, 0x2f, 0x82, 0xbe, 0xc8, 0x50, 0xd3, 0x50, ++ 0x0f, 0x76, 0x95, 0x90, 0x5f, 0xc2, 0xda, 0x49, 0x4f, 0xc8, 0x7a, 0x7a, ++ 0xb4, 0x5e, 0x7f, 0x84, 0xa3, 0xb7, 0x7a, 0xae, 0x68, 0xbd, 0x9c, 0x78, ++ 0xfd, 0x55, 0xfd, 0xfc, 0x85, 0x3d, 0x21, 0xc0, 0x7f, 0xf9, 0xcf, 0x1e, ++ 0xf3, 0x02, 0xf1, 0xd9, 0xa7, 0x5a, 0x53, 0xba, 0x1f, 0xde, 0x57, 0x3e, ++ 0xb3, 0xc2, 0x8b, 0x7c, 0xfc, 0x89, 0x16, 0xf2, 0xe2, 0xbc, 0x3f, 0x0d, ++ 0xab, 0x53, 0xe2, 0xf1, 0xf3, 0x9d, 0xaa, 0x22, 0xfc, 0xb1, 0x80, 0x5b, ++ 0x41, 0x7f, 0x58, 0xd0, 0xe9, 0xcc, 0xf3, 0x6b, 0x6e, 0x41, 0xbc, 0x7f, ++ 0xf1, 0x8c, 0xdd, 0xc0, 0x2a, 0x35, 0x3b, 0x1c, 0x11, 0x07, 0x10, 0xb1, ++ 0xba, 0x65, 0x21, 0xe7, 0xa7, 0x1d, 0x8e, 0x0f, 0x78, 0xf9, 0xe1, 0xcf, ++ 0x91, 0x9e, 0x35, 0xad, 0x56, 0x79, 0x2b, 0x7f, 0xf6, 0xb1, 0x74, 0x8c, ++ 0x77, 0x02, 0x86, 0xb8, 0xdf, 0xc8, 0x22, 0x64, 0x3f, 0x57, 0x6f, 0xff, ++ 0xb8, 0x04, 0xed, 0x91, 0x1a, 0xd6, 0x45, 0x7a, 0x22, 0xb6, 0x1d, 0x8e, ++ 0x7f, 0x31, 0x85, 0xd6, 0xaf, 0x59, 0x7a, 0x52, 0xcf, 0xef, 0x72, 0xff, ++ 0xa5, 0x46, 0xf0, 0x7d, 0x4d, 0xcb, 0x9a, 0xcf, 0x55, 0x2f, 0x96, 0xad, ++ 0xf2, 0x5d, 0x26, 0xfc, 0x91, 0x1b, 0x55, 0x4f, 0x2a, 0xc5, 0x95, 0xc6, ++ 0xb2, 0xb1, 0x48, 0x37, 0x89, 0x07, 0x16, 0xe6, 0xf6, 0xf0, 0xf2, 0xe7, ++ 0x9e, 0x28, 0xf8, 0x00, 0xe0, 0xe8, 0xd8, 0xfe, 0x2f, 0x5e, 0xc5, 0x12, ++ 0x37, 0xe2, 0xfa, 0xe1, 0x7c, 0xf3, 0x9c, 0x1f, 0xbf, 0xea, 0xeb, 0x5d, ++ 0xaf, 0x9f, 0x13, 0xfe, 0x7c, 0xb4, 0x5d, 0x98, 0xda, 0xf9, 0x5a, 0xb9, ++ 0xfd, 0xce, 0xf6, 0xf2, 0x67, 0xa5, 0x3d, 0xe2, 0x45, 0x7f, 0xa9, 0x72, ++ 0x8b, 0xdd, 0x0f, 0x92, 0xc9, 0x2a, 0x5f, 0xd8, 0xf6, 0x93, 0xa7, 0x90, ++ 0xaf, 0xdf, 0x71, 0x50, 0x9c, 0xa1, 0xe2, 0x85, 0xc3, 0x6f, 0x5f, 0x07, ++ 0xe5, 0x8a, 0x5d, 0xf6, 0xd4, 0xa9, 0x7c, 0x1a, 0x6e, 0x25, 0x3d, 0x4a, ++ 0x8f, 0x1a, 0xf8, 0x7f, 0xe9, 0xc8, 0x28, 0xfe, 0xcb, 0x5f, 0x3a, 0xac, ++ 0xfb, 0x86, 0xf3, 0xf7, 0x0f, 0xa5, 0x44, 0xe9, 0x50, 0xb1, 0xeb, 0x80, ++ 0xce, 0x86, 0xf7, 0xc4, 0x5b, 0x71, 0xf3, 0x01, 0xbd, 0xdd, 0x1d, 0x87, ++ 0x1e, 0xcd, 0x1f, 0x94, 0xa0, 0xbd, 0xbd, 0xfc, 0xb9, 0x2f, 0x75, 0x94, ++ 0xab, 0x4f, 0xf7, 0x2b, 0x2c, 0x23, 0xa7, 0x67, 0xfb, 0xb2, 0x2d, 0x87, ++ 0xc9, 0x9e, 0x43, 0x3c, 0x11, 0xfd, 0x04, 0x7d, 0xba, 0xe9, 0xd5, 0x83, ++ 0x4e, 0x91, 0x5b, 0x5e, 0x1d, 0x4d, 0xf5, 0x0c, 0x5c, 0xbf, 0x7a, 0xa3, ++ 0xd3, 0xd5, 0xb8, 0xf6, 0xa5, 0x11, 0x1f, 0xbf, 0xf8, 0x2a, 0xc6, 0xef, ++ 0x7f, 0xef, 0xf0, 0xe3, 0xfc, 0xcb, 0x5e, 0xfc, 0xae, 0x17, 0xe7, 0x71, ++ 0x5a, 0xab, 0xe5, 0xfc, 0xbc, 0x79, 0x45, 0x7a, 0x00, 0xc6, 0x2d, 0xb3, ++ 0x87, 0xd2, 0x0d, 0x7a, 0xf2, 0xf7, 0x65, 0x4f, 0x3f, 0x40, 0x7c, 0xb6, ++ 0xe0, 0xd8, 0x03, 0xe9, 0x14, 0x0f, 0x60, 0x81, 0x2c, 0x1b, 0xad, 0xa1, ++ 0xa1, 0x2c, 0x9c, 0xdf, 0xbc, 0x4d, 0x77, 0xd0, 0xfc, 0xe6, 0xb3, 0x20, ++ 0xf1, 0x5b, 0xd9, 0x66, 0xb5, 0x34, 0x8c, 0xf1, 0x2c, 0x8d, 0x4d, 0xd9, ++ 0x15, 0x47, 0x1e, 0xde, 0x14, 0xf2, 0x70, 0x7a, 0xab, 0x03, 0xd7, 0x1e, ++ 0x76, 0x1a, 0x15, 0x2c, 0xfa, 0x87, 0x6f, 0xa9, 0xb4, 0x4f, 0xc0, 0xd8, ++ 0x22, 0x8a, 0x37, 0x3c, 0x20, 0xf7, 0x21, 0xd8, 0x62, 0x2a, 0x5f, 0x70, ++ 0x72, 0x3a, 0x6d, 0x53, 0x6d, 0x32, 0xbe, 0xe1, 0xb4, 0xf0, 0xe9, 0xf6, ++ 0x87, 0xdb, 0x90, 0x3e, 0x67, 0x06, 0x04, 0x32, 0x30, 0x3e, 0x09, 0x78, ++ 0x08, 0x09, 0x7c, 0x29, 0xa8, 0x77, 0xd4, 0x63, 0x93, 0x33, 0x38, 0x7d, ++ 0x98, 0x4f, 0x2b, 0x14, 0xed, 0x40, 0x2f, 0x16, 0xe3, 0x7b, 0xac, 0xdf, ++ 0x66, 0x0f, 0xb8, 0x0a, 0x2c, 0xed, 0xc4, 0x3a, 0xc6, 0xc7, 0x5f, 0x22, ++ 0xc6, 0x07, 0xb8, 0x13, 0xd0, 0x1e, 0x3b, 0x9d, 0x0e, 0xf6, 0x4d, 0x9c, ++ 0xf9, 0x7d, 0xa9, 0x4a, 0xbd, 0x0c, 0xf6, 0x86, 0x89, 0xbf, 0x4c, 0x72, ++ 0xcd, 0xe5, 0x7c, 0xfb, 0x2a, 0x2e, 0xd7, 0x52, 0xce, 0xc3, 0xd3, 0xa6, ++ 0xe0, 0xf7, 0x3f, 0x1e, 0xe7, 0xf2, 0x83, 0xed, 0x70, 0x5d, 0x07, 0xb8, ++ 0x22, 0x19, 0xf4, 0xfd, 0xc0, 0xed, 0x0a, 0xe9, 0x01, 0x07, 0x8b, 0xc4, ++ 0x93, 0xe7, 0xed, 0x76, 0x21, 0xcf, 0xd6, 0xef, 0x72, 0x7f, 0x12, 0xe0, ++ 0xd6, 0x70, 0x7d, 0x8a, 0xf2, 0x09, 0xf4, 0x9f, 0x42, 0xf8, 0x27, 0x3b, ++ 0x6d, 0xfe, 0x06, 0x68, 0x67, 0xd2, 0xcb, 0x35, 0x38, 0x1e, 0xd5, 0xd3, ++ 0xa3, 0xef, 0x4d, 0xeb, 0xfa, 0x02, 0x21, 0xff, 0xaf, 0xab, 0x62, 0x7f, ++ 0x54, 0xc8, 0x3f, 0xdb, 0xc4, 0xe5, 0xbe, 0x77, 0xbb, 0x37, 0xc4, 0xfd, ++ 0x03, 0x7b, 0xf8, 0x27, 0x4f, 0xa1, 0xbc, 0x82, 0x7c, 0xe2, 0x3a, 0x53, ++ 0xf9, 0x82, 0xbd, 0x14, 0xe7, 0xfd, 0xd9, 0xce, 0x43, 0x6f, 0xdf, 0x03, ++ 0x7c, 0xfd, 0x59, 0xb3, 0x94, 0x53, 0xab, 0xde, 0x8c, 0x95, 0xd3, 0xb2, ++ 0xdd, 0x63, 0x58, 0x3c, 0x39, 0xfd, 0xcc, 0xed, 0x67, 0x71, 0xe5, 0x14, ++ 0xde, 0xc7, 0x95, 0x53, 0x77, 0x3b, 0xf1, 0xf1, 0xdf, 0x5b, 0x6f, 0x4a, ++ 0xbc, 0x9d, 0x8b, 0xd1, 0x9b, 0x52, 0x0f, 0xf6, 0x86, 0xbf, 0x58, 0x3d, ++ 0xb8, 0x56, 0xf5, 0xc5, 0xd5, 0x83, 0xf0, 0x77, 0x9c, 0x15, 0xf6, 0xe4, ++ 0x3b, 0xc9, 0x6f, 0x92, 0xcf, 0xca, 0x7f, 0x5a, 0x35, 0x90, 0xe2, 0x46, ++ 0x92, 0x1f, 0x25, 0xbf, 0x75, 0xf3, 0xa3, 0xe4, 0xb7, 0xd8, 0x79, 0x5a, ++ 0xf1, 0x16, 0xfb, 0xfd, 0x15, 0xa1, 0x6f, 0x24, 0x9d, 0xed, 0xcb, 0x58, ++ 0xc8, 0x83, 0xf1, 0xd2, 0x7d, 0x2a, 0xf9, 0xd7, 0x9d, 0x00, 0x53, 0x23, ++ 0xd0, 0xb7, 0x73, 0x67, 0x4e, 0x18, 0xe3, 0xce, 0x2b, 0x5c, 0x3c, 0x7e, ++ 0xd1, 0x69, 0x74, 0x79, 0x53, 0xe0, 0xb9, 0x22, 0x99, 0x97, 0xbb, 0xd2, ++ 0xf4, 0x46, 0xd4, 0x0f, 0xf2, 0x7d, 0x97, 0x8b, 0xc7, 0xb7, 0x3b, 0x4b, ++ 0xbb, 0xbc, 0xc9, 0x26, 0xbf, 0xe2, 0x83, 0xbd, 0xaa, 0xd7, 0x07, 0xdf, ++ 0xdb, 0xc3, 0x6c, 0x4a, 0x3c, 0x7f, 0x03, 0x34, 0x2f, 0xc1, 0xd1, 0xce, ++ 0x7a, 0xfb, 0xce, 0xe3, 0xc1, 0x93, 0x55, 0x77, 0xf6, 0x52, 0xf4, 0xdb, ++ 0x9b, 0x54, 0xda, 0xcf, 0x9e, 0x5b, 0x7f, 0x97, 0x17, 0xf7, 0x81, 0x3b, ++ 0xf7, 0x0e, 0xfa, 0x27, 0xd4, 0x4f, 0xf3, 0xde, 0x00, 0x03, 0x13, 0xe0, ++ 0xed, 0x44, 0x3b, 0x30, 0x09, 0xa7, 0x17, 0xd0, 0x30, 0x2f, 0x61, 0x8e, ++ 0xa0, 0xf7, 0x27, 0x2c, 0xf4, 0xf8, 0x04, 0x98, 0xdf, 0x9c, 0xbd, 0xdc, ++ 0x5f, 0x98, 0xbb, 0x36, 0xc6, 0xbe, 0x77, 0x2f, 0xd1, 0x51, 0xdf, 0x80, ++ 0x7d, 0x7f, 0xd2, 0x1a, 0xd7, 0xe6, 0x7c, 0x53, 0x2e, 0xfa, 0x29, 0xdb, ++ 0x64, 0xfd, 0x5e, 0xce, 0xd6, 0x12, 0xdd, 0xca, 0x63, 0xf8, 0x28, 0x28, ++ 0xfc, 0xc0, 0xb1, 0x9a, 0xe0, 0xa3, 0x11, 0x6c, 0x84, 0xf0, 0xc3, 0x78, ++ 0xfc, 0x42, 0xe8, 0xab, 0xc9, 0x6a, 0xfe, 0x3f, 0xa1, 0x9d, 0xd1, 0x79, ++ 0x94, 0xc7, 0x15, 0xcf, 0xef, 0x55, 0x09, 0xff, 0xe7, 0x77, 0x2a, 0x61, ++ 0x8c, 0xfb, 0x50, 0x7c, 0x77, 0x3c, 0xd2, 0xbf, 0x4b, 0x67, 0x26, 0x7f, ++ 0xb9, 0x03, 0xf9, 0x4d, 0xef, 0x5d, 0x8e, 0x3b, 0x5e, 0xfe, 0x43, 0xe1, ++ 0x0f, 0xa1, 0x4a, 0xe5, 0x9e, 0x77, 0x0b, 0xfe, 0x19, 0x9e, 0x1d, 0x7b, ++ 0xde, 0xc9, 0xfb, 0x05, 0x96, 0x7f, 0xfe, 0xbb, 0xec, 0x77, 0x59, 0xcf, ++ 0xfa, 0xc5, 0xfb, 0xff, 0x44, 0xfb, 0xc7, 0x9d, 0xfb, 0x1d, 0x04, 0x47, ++ 0xe7, 0xfe, 0xd7, 0xb3, 0x7f, 0x88, 0xe5, 0x57, 0x1d, 0x7e, 0x84, 0xb3, ++ 0x73, 0x99, 0x83, 0xf6, 0xcf, 0x42, 0xfb, 0x3d, 0xe1, 0x21, 0xf8, 0x7d, ++ 0x00, 0xd0, 0x1b, 0xd7, 0xcd, 0x7d, 0x5f, 0x16, 0xb4, 0xd3, 0xba, 0xd3, ++ 0x40, 0x74, 0x9a, 0xad, 0xf1, 0xfd, 0x8e, 0xf3, 0x7b, 0xff, 0xfc, 0xbe, ++ 0x82, 0xf9, 0x07, 0x7b, 0x1d, 0x3e, 0x9c, 0x47, 0xcd, 0x7e, 0x9e, 0x17, ++ 0x52, 0xf3, 0xaa, 0x8b, 0xe2, 0x2e, 0x9d, 0xfb, 0xbe, 0x2c, 0x0c, 0xba, ++ 0xff, 0x76, 0xf3, 0xa9, 0xd6, 0x59, 0x90, 0xf8, 0xcf, 0xc3, 0x66, 0xec, ++ 0x46, 0x7e, 0x4d, 0xe6, 0xfb, 0x00, 0x35, 0xbf, 0x18, 0xbf, 0xad, 0x1e, ++ 0xf7, 0xc3, 0x5b, 0x0e, 0xe8, 0xb8, 0xbf, 0x52, 0xfc, 0xcb, 0xbf, 0x14, ++ 0xa0, 0x7e, 0xe9, 0xdc, 0xcd, 0xed, 0x84, 0x73, 0xf6, 0xf6, 0xa7, 0x71, ++ 0x1f, 0xb4, 0x4a, 0x1b, 0xbc, 0xcc, 0x8e, 0x72, 0x8f, 0x36, 0x5b, 0x5f, ++ 0xb0, 0x3b, 0xed, 0xf3, 0x26, 0x86, 0xf2, 0xe3, 0xe1, 0x85, 0xe3, 0xa1, ++ 0x13, 0xf0, 0x80, 0xf3, 0x02, 0xbc, 0x94, 0xa1, 0x5e, 0xec, 0x0d, 0x1f, ++ 0x0d, 0x1a, 0xf7, 0x37, 0xff, 0xfb, 0xe1, 0xe3, 0xf3, 0xfb, 0x70, 0xfc, ++ 0xca, 0xbd, 0x63, 0x49, 0x6e, 0xa2, 0x78, 0x51, 0x02, 0xfc, 0xbd, 0x27, ++ 0xec, 0x54, 0x68, 0xfe, 0xfc, 0xfd, 0xfe, 0x2f, 0x0b, 0xd0, 0xee, 0xf9, ++ 0xac, 0xb9, 0x9e, 0xd6, 0xf1, 0xcb, 0xcd, 0x7b, 0xdb, 0xff, 0xb8, 0x79, ++ 0x2b, 0x91, 0x2b, 0x99, 0xf7, 0xc1, 0xff, 0xe6, 0xfc, 0x3f, 0x45, 0xe3, ++ 0xeb, 0x52, 0xac, 0x1c, 0xf4, 0xe4, 0xf3, 0x9f, 0x3f, 0x48, 0xe5, 0x17, ++ 0x3d, 0x7e, 0x82, 0xf7, 0x0a, 0xe5, 0xff, 0xe4, 0xff, 0x34, 0xba, 0xef, ++ 0x06, 0xba, 0x7b, 0x2f, 0x4f, 0x77, 0xc5, 0xfe, 0xdf, 0x75, 0xde, 0x97, ++ 0xa3, 0xfb, 0x1b, 0x82, 0xee, 0x1e, 0x03, 0xf3, 0x0a, 0x3a, 0xf7, 0xfd, ++ 0x85, 0xe2, 0xe5, 0x72, 0xfe, 0x97, 0x9b, 0xb7, 0xef, 0xff, 0xd1, 0x79, ++ 0x4b, 0xfb, 0x67, 0xb5, 0xcd, 0xdf, 0x94, 0x0b, 0xf5, 0xd7, 0xb2, 0x48, ++ 0x9b, 0x0f, 0xe0, 0x5c, 0x31, 0x74, 0x7a, 0x13, 0x86, 0x99, 0xc0, 0x4d, ++ 0x28, 0x8d, 0x67, 0x8f, 0x94, 0xda, 0xb9, 0x7f, 0xa4, 0x2a, 0x3c, 0x0e, ++ 0xc3, 0x06, 0xf0, 0xb8, 0x10, 0x13, 0xfe, 0x04, 0xa5, 0x80, 0xf9, 0x30, ++ 0x8e, 0x32, 0x9f, 0xec, 0x3a, 0xcd, 0xdd, 0x48, 0x76, 0x26, 0xd3, 0xfc, ++ 0x6d, 0x01, 0xc0, 0xc7, 0xea, 0xab, 0x67, 0xfb, 0x29, 0x57, 0x83, 0x8d, ++ 0x3c, 0x11, 0xc4, 0x72, 0xff, 0x09, 0x7e, 0x8a, 0x6f, 0xc6, 0xf8, 0x55, ++ 0x0d, 0x0a, 0x0b, 0x28, 0x60, 0xef, 0x69, 0x57, 0x7f, 0xfb, 0x28, 0xda, ++ 0xf9, 0xf6, 0xa1, 0xb6, 0x88, 0xa3, 0x80, 0x9e, 0x1f, 0xe0, 0xf3, 0x61, ++ 0x11, 0xc7, 0xb2, 0x1b, 0xba, 0xc5, 0x9f, 0x70, 0xc7, 0xf8, 0x03, 0x2e, ++ 0x9f, 0xf5, 0xbb, 0x43, 0xf4, 0xe7, 0x64, 0x23, 0x9b, 0x72, 0x31, 0x4f, ++ 0xc1, 0xad, 0x19, 0x61, 0x18, 0xdf, 0x5d, 0xd4, 0x44, 0xf3, 0x71, 0x0f, ++ 0x61, 0xac, 0xc9, 0xb4, 0x0f, 0xe8, 0x60, 0xa6, 0xf6, 0xd0, 0x5f, 0x3e, ++ 0x06, 0x60, 0x4d, 0xf6, 0xe3, 0x37, 0xc5, 0x5f, 0x7d, 0x37, 0xfe, 0x46, ++ 0xb6, 0x05, 0x10, 0x7f, 0xc3, 0x6c, 0x14, 0xd7, 0xa2, 0xa4, 0x3e, 0xc2, ++ 0x87, 0x3f, 0xbc, 0x9a, 0xfc, 0x4c, 0xee, 0x3f, 0x46, 0xf1, 0xd9, 0xd8, ++ 0x86, 0x78, 0xd4, 0x18, 0xf8, 0x7f, 0x7c, 0x7e, 0xe4, 0x37, 0x32, 0xe1, ++ 0x2f, 0x6a, 0xa2, 0x0b, 0x6d, 0xa8, 0x2d, 0xe0, 0xb2, 0xd6, 0x13, 0x7e, ++ 0xd1, 0x65, 0xe9, 0xc3, 0xe9, 0x91, 0x5d, 0x29, 0xe8, 0xb3, 0xd8, 0x42, ++ 0x0f, 0x89, 0xff, 0x38, 0x74, 0xb1, 0xd0, 0x43, 0xe2, 0xf7, 0x9b, 0xd2, ++ 0x25, 0x96, 0x1e, 0xb1, 0x78, 0xbf, 0xdd, 0xce, 0xe3, 0x6d, 0xb1, 0x74, ++ 0xb2, 0xe4, 0x77, 0xa4, 0x71, 0x3f, 0x24, 0x02, 0x7e, 0xc8, 0xeb, 0x3b, ++ 0xb7, 0x51, 0xbc, 0xe3, 0xec, 0xf3, 0x1f, 0xdc, 0x82, 0xf5, 0x2b, 0x7e, ++ 0xa1, 0x32, 0x27, 0xf4, 0x73, 0x6e, 0xa7, 0x87, 0x45, 0x50, 0x7e, 0xb5, ++ 0xb0, 0x8e, 0xfe, 0x54, 0x79, 0x8b, 0x1a, 0x37, 0xce, 0x2b, 0xed, 0xf2, ++ 0x8a, 0x9f, 0x79, 0x68, 0xbc, 0xf2, 0xdd, 0x8e, 0xf0, 0x54, 0x68, 0x5f, ++ 0xbe, 0xe7, 0xc3, 0x02, 0xb2, 0x9b, 0x96, 0x75, 0x1d, 0xe9, 0x87, 0x71, ++ 0x81, 0xe7, 0x15, 0x4e, 0xbf, 0x50, 0x7b, 0x01, 0xee, 0xdb, 0x95, 0x6b, ++ 0xdc, 0x3f, 0x88, 0xed, 0x6f, 0x93, 0x9d, 0xc7, 0x05, 0x3a, 0x5e, 0x49, ++ 0x9c, 0x81, 0xf1, 0x07, 0x65, 0x07, 0xcf, 0x57, 0x2c, 0x6f, 0xbe, 0xcb, ++ 0xee, 0x30, 0xf1, 0xdb, 0xff, 0xb2, 0xf3, 0xbc, 0x57, 0xa8, 0x47, 0xf2, ++ 0x1c, 0x7a, 0x4e, 0xa1, 0xf5, 0xa6, 0x27, 0x7c, 0xdc, 0x2f, 0xe8, 0x78, ++ 0x4e, 0xe1, 0xf0, 0xb5, 0xda, 0xc3, 0x98, 0xf7, 0x58, 0xbe, 0x63, 0x8b, ++ 0x1e, 0x44, 0xbf, 0x72, 0xc7, 0xe7, 0x14, 0xc7, 0x2e, 0xfe, 0xd9, 0x0b, ++ 0xde, 0x76, 0xf2, 0x17, 0x55, 0xab, 0xff, 0xbc, 0x43, 0x25, 0x7a, 0xc2, ++ 0x93, 0xe8, 0x17, 0xeb, 0xc7, 0x56, 0xb7, 0x54, 0x91, 0x9f, 0x50, 0xdd, ++ 0x2c, 0xfc, 0xc4, 0x18, 0x3f, 0xaa, 0xe2, 0x67, 0xfb, 0xf6, 0x84, 0x00, ++ 0x35, 0x15, 0x2f, 0x3d, 0xeb, 0xc5, 0xf8, 0xcb, 0x99, 0xb6, 0x67, 0xbc, ++ 0xe4, 0x9f, 0xee, 0xe0, 0xfe, 0xa7, 0xe6, 0xd6, 0xe2, 0xfb, 0xa7, 0x97, ++ 0xf3, 0x4b, 0x9b, 0x57, 0xc5, 0xf5, 0x4b, 0xcf, 0xe0, 0x3f, 0xc0, 0x9f, ++ 0x38, 0x60, 0x8f, 0xf1, 0xe7, 0x77, 0xf4, 0xb9, 0xb2, 0xfd, 0xcb, 0x17, ++ 0x2e, 0x3c, 0x8d, 0x71, 0xd2, 0x8e, 0xdd, 0x9f, 0x3d, 0x8d, 0x70, 0x57, ++ 0xfe, 0xe7, 0xbf, 0x3f, 0x8d, 0xf6, 0x3d, 0xdb, 0xef, 0x32, 0x9e, 0x81, ++ 0xf9, 0xd6, 0x3c, 0xff, 0x5b, 0x8a, 0x37, 0xc9, 0x76, 0xef, 0x0a, 0x39, ++ 0x3d, 0x37, 0x80, 0x85, 0xb2, 0xa0, 0xde, 0xb9, 0x77, 0x1c, 0x94, 0x3f, ++ 0x72, 0x6e, 0xdf, 0xe9, 0x6c, 0xf4, 0xe7, 0xce, 0xed, 0xfa, 0x53, 0x3a, ++ 0xfa, 0xf5, 0x4b, 0xf6, 0x4d, 0xce, 0xc0, 0x79, 0x2f, 0x79, 0xb9, 0x38, ++ 0x83, 0xc5, 0x91, 0x77, 0xf9, 0x44, 0xbe, 0x0c, 0x5f, 0x41, 0x9c, 0x30, ++ 0x96, 0x0e, 0x87, 0x5a, 0x0e, 0x91, 0x1f, 0x72, 0xf6, 0x84, 0x83, 0xfc, ++ 0xbe, 0xee, 0xf8, 0x42, 0x73, 0x15, 0x8f, 0xd7, 0xf8, 0x44, 0x5c, 0x61, ++ 0x67, 0xfc, 0x38, 0xac, 0xf4, 0x87, 0xab, 0x5b, 0x3e, 0x2c, 0xe1, 0xf1, ++ 0x31, 0xe1, 0x17, 0x5f, 0x2e, 0x8e, 0x70, 0x1c, 0xe8, 0x78, 0xed, 0x15, ++ 0xd0, 0x6b, 0xa7, 0x88, 0x13, 0xc5, 0xd0, 0xeb, 0x2c, 0xfe, 0x03, 0xe8, ++ 0xf2, 0x65, 0x0c, 0xbd, 0x2e, 0xb0, 0xe0, 0x8f, 0xb3, 0x70, 0x1f, 0xb2, ++ 0xa5, 0x4f, 0xaf, 0x71, 0x84, 0xc8, 0x15, 0xe0, 0x49, 0xc6, 0x77, 0x8f, ++ 0xd8, 0x03, 0x36, 0x1d, 0xe5, 0x60, 0x77, 0x62, 0x37, 0x9d, 0xa6, 0x22, ++ 0x9d, 0x5e, 0xb8, 0x90, 0x8d, 0xf1, 0xf0, 0x4f, 0xec, 0x5d, 0x64, 0xf7, ++ 0x74, 0xed, 0x73, 0x18, 0xe8, 0xdf, 0x97, 0xef, 0xfb, 0x1d, 0xc9, 0xc5, ++ 0xb9, 0x97, 0x8f, 0x51, 0xfc, 0x94, 0x89, 0x38, 0xeb, 0x39, 0xd6, 0xfd, ++ 0xc7, 0xe3, 0x62, 0x8a, 0x98, 0xdf, 0x76, 0x0f, 0x8f, 0x3f, 0x08, 0x7c, ++ 0x63, 0x7c, 0xc2, 0xe7, 0xa5, 0xf7, 0x22, 0x0e, 0xc1, 0xf9, 0x55, 0xc6, ++ 0x27, 0x7a, 0x8b, 0x4b, 0x8c, 0xd5, 0x45, 0xde, 0x93, 0x88, 0x3b, 0x57, ++ 0x6d, 0x7f, 0x57, 0x67, 0x31, 0x71, 0x1e, 0x65, 0x1c, 0xd2, 0xe9, 0x03, ++ 0x4b, 0x7c, 0x5c, 0xce, 0x3b, 0xb6, 0x3f, 0x03, 0xf1, 0x30, 0xd6, 0x1c, ++ 0x5f, 0x8b, 0x1f, 0xf7, 0x91, 0x7e, 0x73, 0x94, 0x4e, 0x3c, 0xae, 0x26, ++ 0xe3, 0x67, 0xe7, 0xb6, 0x88, 0xb8, 0x1b, 0xbc, 0xef, 0x3f, 0x12, 0xfd, ++ 0x41, 0x1e, 0xc7, 0xa8, 0x09, 0x2b, 0xbf, 0x63, 0x71, 0xe4, 0x50, 0xc6, ++ 0xd7, 0x46, 0xea, 0x31, 0x72, 0x18, 0xbe, 0xb2, 0xb8, 0xda, 0xe5, 0xe0, ++ 0xfd, 0x6b, 0xf1, 0x31, 0x44, 0xe7, 0xeb, 0x83, 0xc4, 0x4b, 0xc7, 0x57, ++ 0xf1, 0xf5, 0xf0, 0x3f, 0xea, 0x5c, 0xae, 0xa7, 0xd8, 0x82, 0x53, 0x75, ++ 0xd3, 0x7e, 0xf6, 0xfd, 0x62, 0x9f, 0x45, 0xe2, 0x4b, 0xc2, 0xdb, 0x21, ++ 0xf2, 0xf0, 0x3a, 0x9e, 0x57, 0x29, 0x1e, 0xd4, 0xd8, 0x7c, 0x88, 0xf4, ++ 0x69, 0xac, 0x3c, 0x57, 0xf7, 0x72, 0x0e, 0xe2, 0x3e, 0x9d, 0xc7, 0x5b, ++ 0xab, 0x5b, 0x0f, 0x14, 0xa0, 0xde, 0xe9, 0x38, 0xf8, 0x0a, 0xf1, 0x5d, ++ 0xf5, 0xce, 0x0f, 0xf4, 0x10, 0xf4, 0x73, 0x64, 0xc7, 0x4b, 0x3a, 0xb7, ++ 0x27, 0x39, 0x9f, 0xa3, 0x9e, 0x0e, 0x9b, 0xf4, 0x74, 0xc7, 0x8b, 0x07, ++ 0x0a, 0x78, 0xdc, 0x8f, 0xe7, 0xdd, 0xc6, 0xf6, 0x5f, 0x21, 0xfa, 0xaf, ++ 0xd9, 0x6b, 0xed, 0xbf, 0x66, 0xe7, 0xe7, 0x96, 0xfe, 0x2b, 0x42, 0xcd, ++ 0xb4, 0xff, 0x75, 0xb9, 0x71, 0xce, 0x68, 0x81, 0xbb, 0x70, 0xbe, 0x67, ++ 0xda, 0xec, 0x0c, 0xf5, 0xdd, 0x99, 0x66, 0x75, 0x4a, 0x38, 0x9e, 0x1d, ++ 0xa8, 0xdb, 0x2d, 0xfb, 0xa0, 0x8d, 0xc7, 0x74, 0x5a, 0xaf, 0x46, 0xbf, ++ 0x95, 0x40, 0xf9, 0xb9, 0x4b, 0x8e, 0x4d, 0x79, 0x37, 0x09, 0xf7, 0xe9, ++ 0x40, 0xcc, 0xd0, 0xfe, 0x6d, 0xa9, 0xe7, 0x7c, 0xd5, 0xf2, 0xa3, 0x40, ++ 0x3f, 0xa4, 0x4b, 0xcb, 0xb1, 0x7b, 0x54, 0x5c, 0x37, 0xf6, 0x20, 0x1e, ++ 0x4d, 0x76, 0x70, 0xe1, 0xf1, 0xda, 0x62, 0x0f, 0xc8, 0x6b, 0xe1, 0x7b, ++ 0xa5, 0xa3, 0x91, 0xad, 0x62, 0xf5, 0xc0, 0xd8, 0x13, 0x36, 0x0b, 0xdc, ++ 0x30, 0x4e, 0x06, 0xea, 0xe3, 0x06, 0xe8, 0x07, 0xf3, 0xe9, 0x31, 0x7f, ++ 0x08, 0xf7, 0x47, 0x55, 0x6f, 0xc9, 0x14, 0x84, 0x47, 0x35, 0x6c, 0x86, ++ 0x2b, 0xee, 0xfa, 0xc9, 0xfb, 0xb3, 0xbb, 0x4b, 0x19, 0xda, 0xe5, 0x76, ++ 0xc3, 0x9a, 0xaf, 0x9c, 0x39, 0x5d, 0xc4, 0xd1, 0x22, 0xd6, 0xbc, 0xf5, ++ 0x4c, 0x9d, 0x0d, 0xc5, 0x7d, 0x70, 0x66, 0x4b, 0xf0, 0xe3, 0x7e, 0xc0, ++ 0xe2, 0x61, 0x81, 0x11, 0x87, 0x31, 0xaf, 0x7e, 0x5e, 0x26, 0xc5, 0x89, ++ 0xb3, 0x6e, 0xe3, 0xed, 0xce, 0x1a, 0xee, 0x90, 0xed, 0xda, 0xe8, 0xbe, ++ 0x6d, 0xe2, 0x45, 0xe8, 0x1f, 0xf3, 0x60, 0x6c, 0xe1, 0xf5, 0x33, 0xa1, ++ 0x5d, 0xa2, 0xd6, 0xac, 0xe0, 0x3e, 0x00, 0x3c, 0x19, 0xd2, 0xe5, 0x01, ++ 0x5b, 0x70, 0xab, 0x9e, 0x86, 0xf5, 0x74, 0xe6, 0x03, 0xd5, 0xf8, 0xb4, ++ 0xae, 0x68, 0x94, 0x7f, 0x21, 0xce, 0xbd, 0xc8, 0xfe, 0x64, 0xbd, 0xde, ++ 0xf6, 0x83, 0xe5, 0x39, 0x24, 0x55, 0xc0, 0x3f, 0x48, 0xec, 0x07, 0x0f, ++ 0x60, 0xed, 0x0a, 0xee, 0x07, 0x6f, 0xf2, 0xf0, 0xf3, 0x48, 0x03, 0xdd, ++ 0xa9, 0x74, 0xde, 0x68, 0x9b, 0xb0, 0xdb, 0x7c, 0xb8, 0xef, 0x8a, 0xf5, ++ 0x6a, 0xad, 0xeb, 0xf6, 0x65, 0xcf, 0x23, 0xad, 0xb4, 0x96, 0x53, 0x8b, ++ 0x8b, 0x16, 0x0d, 0xf4, 0x33, 0xf6, 0x61, 0xe3, 0x83, 0xc5, 0x1a, 0xe8, ++ 0x83, 0xd4, 0xbb, 0x8a, 0x76, 0xf5, 0x33, 0x70, 0x5f, 0x7a, 0x43, 0x31, ++ 0xe6, 0xdd, 0xa7, 0x3e, 0x5b, 0x34, 0x22, 0x0b, 0xca, 0x77, 0x39, 0x86, ++ 0x4f, 0xa2, 0xef, 0xbf, 0x2e, 0x1a, 0x91, 0x0d, 0xe5, 0x5a, 0xe7, 0xb8, ++ 0x49, 0xf4, 0xbd, 0x42, 0xa1, 0xbc, 0xc0, 0x7d, 0x7a, 0x67, 0x71, 0x28, ++ 0x3f, 0x2a, 0x9f, 0x69, 0x60, 0xdc, 0x62, 0xbe, 0x05, 0xc8, 0xed, 0x41, ++ 0x94, 0xdb, 0xb3, 0xa5, 0x1d, 0x8d, 0xf8, 0xb5, 0xea, 0x8e, 0x2f, 0x74, ++ 0x7e, 0x1e, 0x86, 0x95, 0xe2, 0xfc, 0x07, 0x8c, 0xe3, 0xf3, 0xef, 0xef, ++ 0x7e, 0x6f, 0x17, 0xce, 0x77, 0xa0, 0xad, 0xbd, 0x1e, 0xf9, 0xef, 0xc7, ++ 0xfb, 0xbe, 0x4c, 0xc6, 0x7a, 0x3e, 0x66, 0xd0, 0x3c, 0x0d, 0xd6, 0x60, ++ 0xe0, 0xbe, 0x3c, 0xbc, 0x1a, 0xf7, 0xf5, 0x25, 0xf2, 0x7f, 0x62, 0xf3, ++ 0x60, 0x24, 0xbf, 0x6f, 0x4b, 0x0c, 0xfe, 0x06, 0xe1, 0x58, 0x35, 0x7b, ++ 0xe8, 0x13, 0x25, 0xa8, 0x53, 0x2b, 0xfd, 0xc4, 0x47, 0xb1, 0xfb, 0xc4, ++ 0xcc, 0x48, 0x25, 0xba, 0xcc, 0x15, 0x74, 0x41, 0x38, 0x9d, 0xa6, 0x3c, ++ 0xe4, 0x05, 0x6a, 0x88, 0xf2, 0x5e, 0xf0, 0x44, 0x02, 0xe5, 0xf5, 0xb0, ++ 0x49, 0x06, 0x8e, 0xa7, 0x84, 0x2a, 0xd5, 0xaf, 0xaf, 0xf9, 0xe6, 0x70, ++ 0x9d, 0xd6, 0x45, 0xbe, 0x81, 0x38, 0x0f, 0x66, 0x3a, 0x2f, 0x75, 0x06, ++ 0xe1, 0x5d, 0x97, 0x18, 0xa4, 0x67, 0xec, 0x79, 0xa9, 0x83, 0x7a, 0x69, ++ 0x07, 0xbe, 0xcf, 0x9a, 0x7f, 0x31, 0x1b, 0xe7, 0x21, 0xcf, 0x41, 0x15, ++ 0x2f, 0x70, 0x53, 0x7c, 0xe0, 0xfc, 0x5e, 0x16, 0x76, 0xc4, 0x91, 0x23, ++ 0xf9, 0xdc, 0x5a, 0xc7, 0xd2, 0xb4, 0xc1, 0xbd, 0x7f, 0xff, 0x8d, 0x23, ++ 0xf8, 0x1f, 0xd8, 0x7f, 0xee, 0x2f, 0x7d, 0xbb, 0x8f, 0x42, 0x7f, 0xd7, ++ 0xce, 0xd5, 0xfd, 0x98, 0xc2, 0x76, 0xed, 0xd2, 0xd1, 0x69, 0xda, 0x28, ++ 0xc6, 0x27, 0x84, 0x76, 0x85, 0xa0, 0x5f, 0x26, 0xd2, 0x14, 0xe5, 0xec, ++ 0x41, 0xc6, 0xcf, 0xe7, 0x38, 0x94, 0x00, 0xfa, 0x8f, 0x9d, 0xdf, 0x35, ++ 0x48, 0x0f, 0xf7, 0x9f, 0x3b, 0x95, 0xfc, 0x8c, 0xce, 0xc4, 0x9c, 0x66, ++ 0xcc, 0xa3, 0xe8, 0xfc, 0x21, 0xcf, 0x07, 0x80, 0x95, 0x5e, 0x41, 0x79, ++ 0x18, 0xb0, 0x37, 0x29, 0x82, 0x7e, 0x10, 0xf0, 0xf3, 0x17, 0x31, 0xfc, ++ 0xfc, 0x85, 0x75, 0xbd, 0xb1, 0x8e, 0xdb, 0xf9, 0xb5, 0xaf, 0xb5, 0x9d, ++ 0xfa, 0x33, 0x44, 0x7f, 0x60, 0xf0, 0xa4, 0xa3, 0xfc, 0xf0, 0xbf, 0x4e, ++ 0x95, 0xdb, 0xdb, 0x9d, 0x75, 0x3e, 0x82, 0x03, 0xcc, 0xc3, 0x03, 0xb8, ++ 0xae, 0x5e, 0xe9, 0x78, 0x59, 0x0e, 0x11, 0x0f, 0x17, 0xf4, 0x01, 0xbc, ++ 0xf7, 0x73, 0x98, 0xf0, 0x3e, 0xd0, 0xd1, 0x2b, 0xfd, 0x72, 0x1d, 0x9c, ++ 0x7e, 0xf4, 0x8c, 0xa5, 0xdf, 0x7c, 0x67, 0x6d, 0x36, 0xca, 0x73, 0x79, ++ 0x69, 0x73, 0x09, 0xba, 0xa8, 0xbf, 0xd5, 0x83, 0x57, 0x61, 0xbd, 0xd3, ++ 0xf3, 0x8f, 0x34, 0xda, 0xa1, 0x5e, 0xd5, 0xcc, 0xda, 0x3c, 0x64, 0xf6, ++ 0x9e, 0x74, 0xe5, 0xe7, 0xb1, 0xd2, 0xf7, 0xce, 0xaa, 0xb7, 0x63, 0xbc, ++ 0x02, 0xe9, 0xe2, 0xeb, 0x49, 0xbf, 0x6b, 0x97, 0xfa, 0xd3, 0xb4, 0x3e, ++ 0x16, 0x7a, 0x8e, 0x72, 0x40, 0x3f, 0xd7, 0xee, 0xfd, 0xdc, 0x86, 0x70, ++ 0x4b, 0x3a, 0x3e, 0x21, 0xf2, 0xfc, 0x63, 0xdb, 0xff, 0x83, 0x43, 0x11, ++ 0xe3, 0x56, 0xd6, 0xdb, 0x31, 0x4e, 0xd2, 0xaa, 0x93, 0x3d, 0x1b, 0x5b, ++ 0x6f, 0x0a, 0x1e, 0xaa, 0x1a, 0x13, 0x2d, 0x17, 0x38, 0x0b, 0x69, 0xdc, ++ 0x0c, 0x1b, 0x8f, 0x77, 0xf4, 0xac, 0xcf, 0xd7, 0xbf, 0x68, 0xbf, 0x4e, ++ 0x3a, 0x97, 0xd5, 0x1b, 0x1f, 0x16, 0x18, 0xbc, 0x3f, 0xc0, 0xfb, 0xb7, ++ 0x11, 0x7e, 0x89, 0xf7, 0x5b, 0x1c, 0x42, 0xdf, 0xf6, 0xc4, 0xfb, 0x34, ++ 0xac, 0x07, 0x78, 0xa7, 0xe7, 0x15, 0xe0, 0xfd, 0xce, 0x4b, 0xe1, 0x5d, ++ 0xda, 0xcf, 0x15, 0x42, 0x1f, 0x54, 0xe0, 0xfe, 0x09, 0xf0, 0xcd, 0xc7, ++ 0x81, 0xe9, 0xe9, 0x83, 0x61, 0xdc, 0x12, 0xd5, 0x4d, 0x7c, 0xbf, 0xf0, ++ 0x19, 0x95, 0xe4, 0x0d, 0xea, 0x4f, 0xcd, 0x4a, 0x8f, 0xea, 0x8f, 0x85, ++ 0xe3, 0x6b, 0x0f, 0xe0, 0x3c, 0x17, 0x6e, 0x56, 0x88, 0x3f, 0xe7, 0x8a, ++ 0xf3, 0xa5, 0x9f, 0x89, 0x7c, 0xfe, 0xd8, 0x3c, 0xa8, 0xf9, 0x33, 0x42, ++ 0xb4, 0xaf, 0xd3, 0x23, 0x1f, 0x2a, 0x1c, 0xe3, 0xcf, 0xc5, 0xe4, 0xb9, ++ 0x57, 0x47, 0xf9, 0x74, 0x20, 0xcf, 0x4f, 0xe3, 0xe7, 0xb5, 0x54, 0x21, ++ 0x07, 0xc5, 0x0b, 0xf2, 0x93, 0xd0, 0x0e, 0xda, 0x6f, 0xf7, 0xfd, 0x9a, ++ 0xec, 0xeb, 0x37, 0x54, 0xb6, 0x35, 0x0e, 0xde, 0x89, 0xb9, 0xd2, 0xa2, ++ 0xe5, 0x01, 0xb5, 0x36, 0x4b, 0x7e, 0x2c, 0x9b, 0x9b, 0x6c, 0xe9, 0x77, ++ 0xd2, 0x82, 0x7c, 0xda, 0xef, 0x5e, 0xec, 0xf1, 0x5d, 0xd2, 0x9f, 0x1a, ++ 0xb8, 0xd4, 0xba, 0x5e, 0xe7, 0x84, 0xac, 0xe7, 0x8b, 0x06, 0xad, 0xb4, ++ 0x9e, 0x2f, 0x1a, 0xd2, 0xd4, 0xd7, 0x52, 0xff, 0xaa, 0x8d, 0xb9, 0x96, ++ 0xef, 0xc3, 0xc2, 0x57, 0x5b, 0xbe, 0x5f, 0xb3, 0x63, 0xa4, 0xa5, 0x3c, ++ 0xbc, 0xf9, 0x3a, 0x4b, 0xfd, 0x6b, 0x5b, 0x27, 0x5a, 0xca, 0x23, 0x22, ++ 0xdf, 0xb6, 0xd4, 0x1f, 0x75, 0x74, 0xba, 0xa5, 0x3c, 0xa6, 0xed, 0x1e, ++ 0x4b, 0xfd, 0xb1, 0x27, 0x66, 0x5b, 0xbe, 0x8f, 0x6f, 0x2f, 0xb7, 0x7c, ++ 0xbf, 0xfe, 0x93, 0xc5, 0x96, 0xf2, 0xb7, 0xba, 0x7e, 0x60, 0xb5, 0x4f, ++ 0x6c, 0x8c, 0xf4, 0x21, 0x4b, 0x50, 0x48, 0x3f, 0xbe, 0x56, 0x37, 0x2e, ++ 0x1b, 0xf3, 0xb0, 0xd9, 0x68, 0x65, 0x12, 0xe2, 0xb3, 0x58, 0xe4, 0x11, ++ 0xbe, 0xb6, 0x48, 0xb7, 0x19, 0x5e, 0x7c, 0xe6, 0xd9, 0x0c, 0xd0, 0x53, ++ 0x07, 0xe7, 0x4d, 0xa5, 0xf5, 0xfe, 0xb5, 0x45, 0xe9, 0x01, 0x1f, 0x3d, ++ 0x0b, 0x03, 0xe8, 0xcf, 0x30, 0x75, 0xc2, 0xe8, 0x78, 0x79, 0x9a, 0x93, ++ 0x8d, 0xf1, 0xd9, 0xe6, 0x7c, 0xa8, 0x62, 0xa7, 0xdd, 0xa2, 0xcf, 0x26, ++ 0x1b, 0xd6, 0xf2, 0xcb, 0x92, 0x6f, 0x06, 0x72, 0xbe, 0x79, 0x35, 0x46, ++ 0x9f, 0xd9, 0x6b, 0x27, 0x44, 0xc0, 0x22, 0x64, 0x7d, 0x17, 0x0e, 0xce, ++ 0xc0, 0xf1, 0x40, 0xbe, 0xf6, 0x09, 0xbd, 0xb6, 0xef, 0x0a, 0xf5, 0xda, ++ 0x41, 0x94, 0xc3, 0xd3, 0xe9, 0x91, 0x46, 0x2c, 0x4b, 0xf9, 0x62, 0x62, ++ 0x5d, 0x2d, 0x12, 0x7c, 0x04, 0xcf, 0x80, 0x8e, 0xf9, 0x90, 0x93, 0x3c, ++ 0xb4, 0xfe, 0x06, 0xf0, 0xa5, 0x8f, 0xde, 0x87, 0x34, 0x90, 0x93, 0x89, ++ 0x4e, 0x7f, 0xff, 0xc3, 0x38, 0x1f, 0x9b, 0x3f, 0x15, 0x99, 0x6f, 0xd2, ++ 0x8c, 0xd2, 0xd7, 0x78, 0x6e, 0xa5, 0x58, 0x7f, 0xd9, 0x50, 0xdb, 0x37, ++ 0x59, 0x7f, 0xa5, 0x7c, 0x67, 0xda, 0x44, 0xbe, 0x5a, 0x0a, 0xcf, 0x57, ++ 0x7b, 0x72, 0x5e, 0x5e, 0x12, 0x33, 0xe1, 0xf5, 0x5d, 0x87, 0x4d, 0xd8, ++ 0xcd, 0x4d, 0xfc, 0x69, 0x1c, 0x75, 0x75, 0xe7, 0xa9, 0xe6, 0x9a, 0xdf, ++ 0x7f, 0x92, 0xa0, 0x99, 0xf2, 0xe3, 0x94, 0x05, 0x53, 0x29, 0x3f, 0x24, ++ 0xb3, 0x17, 0x3d, 0xa8, 0x67, 0xe6, 0xde, 0xb4, 0x1d, 0xf4, 0xaf, 0x9e, ++ 0xe5, 0xa3, 0xa7, 0x7c, 0xdf, 0x38, 0xc3, 0x16, 0x37, 0xef, 0xeb, 0x9c, ++ 0xd0, 0x9b, 0xd2, 0xbe, 0x1a, 0x16, 0xb5, 0xaf, 0xce, 0x21, 0x1d, 0xce, ++ 0x66, 0xbe, 0xf5, 0x38, 0xe6, 0x25, 0x55, 0xcf, 0xec, 0x22, 0xfb, 0x2a, ++ 0xd3, 0xd6, 0xb4, 0xe8, 0x08, 0xce, 0xeb, 0x57, 0xaa, 0x88, 0x57, 0xfa, ++ 0xf8, 0x79, 0x2a, 0x61, 0x17, 0xcf, 0xbb, 0xe9, 0xd1, 0x45, 0x47, 0x70, ++ 0x1f, 0xfa, 0x5f, 0x87, 0x90, 0x5e, 0x92, 0xe3, 0x6c, 0xaa, 0x9b, 0x72, ++ 0x93, 0x66, 0x3a, 0x37, 0xde, 0xbf, 0x17, 0x3f, 0x69, 0x98, 0x93, 0xaf, ++ 0x0f, 0x4f, 0xd7, 0x0d, 0xbd, 0x69, 0x2e, 0xe5, 0x69, 0x1b, 0xfc, 0x7c, ++ 0xa8, 0xe8, 0x3f, 0x3b, 0x54, 0x55, 0x82, 0x76, 0xf2, 0x40, 0x91, 0x5f, ++ 0xfa, 0xb8, 0x2d, 0x7e, 0x7e, 0x4b, 0x82, 0x93, 0xcf, 0x2b, 0x03, 0x49, ++ 0x8e, 0xf0, 0x1a, 0x6e, 0x92, 0x8f, 0xb3, 0xf3, 0xdf, 0xf3, 0x6a, 0x30, ++ 0x8f, 0xa7, 0x6c, 0xc1, 0x04, 0x27, 0xee, 0xd3, 0x5e, 0xdb, 0x56, 0xc8, ++ 0xfd, 0xbc, 0x80, 0x1f, 0xcf, 0x9d, 0x66, 0x47, 0xee, 0x7d, 0x1c, 0xeb, ++ 0x67, 0x67, 0x6a, 0x94, 0xdf, 0x1a, 0x3b, 0x7e, 0xc6, 0xcc, 0xe0, 0xca, ++ 0x1c, 0x98, 0x5f, 0x43, 0x8a, 0xcd, 0xef, 0xa6, 0x72, 0x97, 0x82, 0xf5, ++ 0x1d, 0x0f, 0x31, 0xd6, 0x07, 0xea, 0x37, 0xfc, 0xa7, 0x4a, 0xf0, 0x34, ++ 0x1c, 0x1c, 0x4f, 0xf9, 0x1e, 0x0e, 0x77, 0x2d, 0x43, 0xfb, 0x55, 0xce, ++ 0xeb, 0x50, 0xca, 0x53, 0x84, 0x1f, 0xb5, 0x25, 0x91, 0xd6, 0x3d, 0x26, ++ 0xf6, 0xc1, 0x65, 0x7c, 0xf5, 0x42, 0xe6, 0xdc, 0x36, 0xb4, 0x2b, 0x2e, ++ 0x6c, 0xb0, 0xd3, 0x78, 0x17, 0x60, 0x8e, 0x06, 0xf4, 0x7f, 0xa1, 0x45, ++ 0xa5, 0x7d, 0xd6, 0x23, 0x29, 0x09, 0x11, 0x1b, 0x94, 0xd5, 0x95, 0x1e, ++ 0x52, 0xa9, 0xd9, 0x68, 0x6b, 0x42, 0xfd, 0xf9, 0x2d, 0x9e, 0xb0, 0x2f, ++ 0x27, 0x8a, 0x17, 0x6d, 0xe3, 0x04, 0x3a, 0xff, 0xe2, 0xe8, 0xcf, 0xe7, ++ 0xdf, 0x90, 0xe2, 0x0e, 0xbb, 0x73, 0x68, 0xde, 0x29, 0x38, 0x6f, 0x09, ++ 0xa7, 0x9c, 0xf7, 0x80, 0x5e, 0xfc, 0xca, 0x1b, 0x04, 0x1e, 0xb3, 0xae, ++ 0xea, 0x3e, 0x97, 0xc1, 0x90, 0x8f, 0x55, 0x43, 0xa3, 0x7e, 0xe7, 0x25, ++ 0xf3, 0x73, 0x97, 0xe1, 0xba, 0x71, 0x82, 0x5e, 0xd6, 0xf9, 0x34, 0x66, ++ 0x4e, 0xbf, 0xf5, 0x6e, 0x3c, 0x2f, 0x74, 0x5c, 0x65, 0x98, 0x0a, 0xe2, ++ 0x6b, 0x6f, 0xa2, 0xf9, 0xcf, 0x87, 0xf9, 0x63, 0x7c, 0x37, 0x16, 0xbf, ++ 0x67, 0x7d, 0x39, 0x5f, 0xd8, 0x54, 0x82, 0xf3, 0x06, 0x84, 0x53, 0xdd, ++ 0x58, 0x42, 0xf3, 0xa0, 0x7a, 0xd0, 0xae, 0xea, 0xc7, 0x0a, 0x7b, 0x2a, ++ 0x07, 0xf9, 0x30, 0x38, 0x85, 0xe8, 0xda, 0xd7, 0x46, 0xe7, 0x00, 0x63, ++ 0xe1, 0x2e, 0x71, 0xf2, 0x38, 0xeb, 0x8d, 0x4e, 0x1e, 0x0f, 0xd0, 0x33, ++ 0xf3, 0x6e, 0xda, 0xde, 0x07, 0x9f, 0x83, 0x49, 0x2e, 0x6e, 0x76, 0xf6, ++ 0xba, 0xce, 0xdf, 0xe2, 0xe4, 0x7a, 0x88, 0x9e, 0x57, 0x7e, 0x9f, 0x40, ++ 0xc4, 0xb2, 0xce, 0xab, 0x01, 0x1b, 0xd9, 0x41, 0xb1, 0x70, 0x81, 0xde, ++ 0xba, 0xdb, 0x69, 0xb2, 0x6b, 0xd4, 0xa4, 0x87, 0x0a, 0xb0, 0xdf, 0xde, ++ 0xed, 0xb1, 0x5d, 0x07, 0x74, 0xb4, 0xc7, 0xdc, 0x8c, 0xec, 0x64, 0xa9, ++ 0x2f, 0x7b, 0xb3, 0xc7, 0xd0, 0x0e, 0x43, 0x7e, 0x93, 0x76, 0xd8, 0x02, ++ 0xa7, 0x55, 0xef, 0xc2, 0xfc, 0xca, 0xc5, 0xfc, 0xca, 0xe3, 0xcd, 0x2f, ++ 0x8e, 0x9e, 0xad, 0xc1, 0x7a, 0xa7, 0xef, 0x89, 0xc4, 0xb5, 0x63, 0xd2, ++ 0xf4, 0xf8, 0x7a, 0x68, 0xb3, 0xc0, 0x7f, 0x8d, 0xa1, 0x33, 0x8a, 0x2b, ++ 0xf5, 0x12, 0x0f, 0x7f, 0xc2, 0x29, 0xed, 0xc1, 0xbd, 0x07, 0x74, 0xc4, ++ 0x2b, 0xcc, 0x13, 0xf1, 0x9a, 0x09, 0xfe, 0x71, 0x09, 0xe9, 0x19, 0x7b, ++ 0xdc, 0xbc, 0xef, 0xcb, 0xf9, 0x19, 0xb9, 0x6b, 0xf2, 0x77, 0x1f, 0xc5, ++ 0xfe, 0xc0, 0x8e, 0x45, 0xee, 0x39, 0xdf, 0xe4, 0x4b, 0x4a, 0xb9, 0x84, ++ 0x1d, 0x61, 0x5f, 0xfa, 0x2b, 0x97, 0x19, 0x8f, 0x8f, 0xc4, 0xf0, 0x07, ++ 0xe0, 0x6d, 0xbd, 0x93, 0xdb, 0x7f, 0xf4, 0xec, 0x81, 0xb7, 0x54, 0xc0, ++ 0x9b, 0xcd, 0x82, 0xb7, 0xc7, 0x9d, 0x97, 0xb4, 0xff, 0xb8, 0xbe, 0xed, ++ 0x2b, 0xce, 0x0f, 0x9c, 0x13, 0x78, 0x02, 0xbd, 0xfb, 0x7d, 0xec, 0xff, ++ 0xec, 0x6d, 0xe7, 0xee, 0x44, 0xdf, 0xb0, 0xea, 0xb6, 0xaf, 0x84, 0x5f, ++ 0xcb, 0xeb, 0xa7, 0x0b, 0xfd, 0x0c, 0x7e, 0xef, 0x3f, 0x7c, 0xec, 0xa3, ++ 0xfa, 0x4b, 0x70, 0x9c, 0xa8, 0xff, 0xdb, 0x5e, 0x88, 0x7e, 0xcf, 0xf2, ++ 0x97, 0xaf, 0x4a, 0x42, 0xfb, 0x69, 0xd2, 0x9e, 0xbb, 0x0d, 0x7c, 0x9e, ++ 0x4f, 0x1d, 0x4c, 0xeb, 0xcf, 0xd9, 0x3d, 0x8e, 0x00, 0x8e, 0x73, 0x36, ++ 0x85, 0xe7, 0xd3, 0x9d, 0xdd, 0x33, 0xf6, 0x08, 0xc6, 0x07, 0x3e, 0xab, ++ 0x3b, 0x9a, 0x6b, 0xd6, 0xcf, 0x67, 0x5f, 0x3c, 0x56, 0x68, 0x87, 0x7e, ++ 0xce, 0xee, 0x3e, 0x56, 0xa8, 0x51, 0xfe, 0x6e, 0xd8, 0x62, 0x8f, 0x57, ++ 0x7d, 0xfd, 0x9b, 0x42, 0x3c, 0x27, 0x25, 0xf3, 0x9e, 0xbb, 0xe9, 0xec, ++ 0xe4, 0x7a, 0x7d, 0x83, 0x8b, 0xc7, 0x1d, 0xd2, 0xd2, 0xf5, 0x46, 0xcc, ++ 0xe7, 0xee, 0x48, 0x48, 0xa6, 0x79, 0x3f, 0x96, 0x6e, 0x7b, 0x24, 0x5e, ++ 0x3c, 0x05, 0xd5, 0x1d, 0xed, 0xab, 0x7b, 0x74, 0xda, 0x47, 0x5c, 0x3c, ++ 0xcc, 0xb7, 0xdc, 0x8d, 0xf1, 0x94, 0x1c, 0x83, 0xf2, 0x64, 0x97, 0x2b, ++ 0x81, 0xac, 0x79, 0xb8, 0x0f, 0x32, 0xcd, 0xe9, 0xc7, 0x38, 0x7d, 0x6a, ++ 0x2e, 0x1b, 0x9a, 0x93, 0x84, 0xa1, 0xc6, 0x20, 0x73, 0x03, 0x0b, 0x39, ++ 0x5e, 0x6b, 0xa2, 0xe3, 0xa0, 0x09, 0x6d, 0xc6, 0x01, 0x34, 0x63, 0x64, ++ 0x9c, 0x45, 0x2b, 0xe6, 0xfa, 0xb1, 0xeb, 0x0e, 0x9d, 0xf2, 0xba, 0x12, ++ 0x35, 0xdf, 0x13, 0x33, 0xa1, 0x9c, 0x39, 0x43, 0xa3, 0xf5, 0x49, 0xc6, ++ 0x5d, 0xfe, 0x9c, 0x90, 0x42, 0xf0, 0xc9, 0xb8, 0x4b, 0x37, 0x3c, 0x6f, ++ 0xd8, 0x69, 0xdd, 0x58, 0x9c, 0x13, 0x6c, 0x2a, 0x82, 0x76, 0x8b, 0xc7, ++ 0xa7, 0x50, 0x3b, 0xef, 0xb4, 0xb7, 0x89, 0xde, 0x9d, 0x3e, 0x5b, 0xc8, ++ 0x8e, 0xf3, 0xd1, 0xba, 0x28, 0xfe, 0xf2, 0x4f, 0x75, 0x43, 0xd3, 0x06, ++ 0x03, 0x1e, 0x8d, 0x2c, 0xdb, 0x4d, 0x64, 0x83, 0x7c, 0x05, 0xd8, 0x32, ++ 0xe5, 0xe7, 0x7b, 0x35, 0x16, 0x4a, 0x02, 0x7b, 0x64, 0x0d, 0xf0, 0xef, ++ 0x60, 0xe0, 0xdf, 0x96, 0x3a, 0x27, 0xd5, 0x6f, 0x04, 0x3b, 0xce, 0x48, ++ 0xa1, 0x7b, 0x0c, 0xa2, 0xf7, 0x70, 0x98, 0xf8, 0x7e, 0x77, 0x9d, 0x41, ++ 0xf5, 0x7e, 0x52, 0x97, 0x49, 0xed, 0x1e, 0xad, 0xf3, 0xd1, 0xb3, 0x7b, ++ 0xdd, 0x67, 0xbc, 0x1d, 0x95, 0xe3, 0xe8, 0xc3, 0xbf, 0xd7, 0x73, 0x5d, ++ 0x1d, 0xbf, 0xef, 0x43, 0x96, 0xff, 0x7d, 0x34, 0xd8, 0x55, 0x40, 0xef, ++ 0xd4, 0xb1, 0x40, 0x55, 0xc0, 0x4b, 0xaa, 0x38, 0x1f, 0x2e, 0xbf, 0x3f, ++ 0x55, 0xf7, 0xc6, 0xa0, 0x49, 0x83, 0x05, 0x32, 0x00, 0x9f, 0x7d, 0x2b, ++ 0x8d, 0x2d, 0xab, 0x2f, 0x01, 0x6f, 0xaa, 0x23, 0x9c, 0x8c, 0x47, 0x80, ++ 0x07, 0xba, 0x58, 0x68, 0x52, 0x26, 0xe6, 0xe1, 0x75, 0x3d, 0x52, 0x92, ++ 0x8c, 0xe7, 0x17, 0xea, 0x27, 0x4d, 0x1a, 0x06, 0x78, 0xc4, 0xfd, 0xe7, ++ 0xeb, 0xc0, 0x95, 0x70, 0xad, 0x6d, 0x08, 0x4d, 0x00, 0x7e, 0xa8, 0xf4, ++ 0xd5, 0x63, 0x5c, 0x2e, 0xab, 0x55, 0x69, 0xc6, 0xf5, 0x26, 0xab, 0x75, ++ 0x7d, 0x11, 0xc6, 0xf9, 0xa1, 0x1e, 0x9d, 0xeb, 0x93, 0xfd, 0xba, 0x5c, ++ 0x5c, 0x3f, 0x25, 0x1e, 0x7a, 0x52, 0xc9, 0x1d, 0x8e, 0xc1, 0x7f, 0xbe, ++ 0x6f, 0xce, 0xf6, 0x25, 0x86, 0xe3, 0x9d, 0xff, 0x1c, 0xea, 0xe2, 0x7a, ++ 0x6a, 0xb0, 0x68, 0xb7, 0x46, 0xec, 0x7b, 0x77, 0x4d, 0x73, 0xd3, 0x3d, ++ 0x09, 0x89, 0x87, 0x5c, 0xc4, 0x2f, 0x59, 0x7b, 0xaf, 0xa1, 0xfd, 0x37, ++ 0x77, 0x2f, 0xfb, 0xbe, 0xb1, 0xfd, 0x24, 0x1e, 0xfa, 0x13, 0xc5, 0x69, ++ 0xdd, 0x4a, 0xd3, 0x01, 0xdc, 0x47, 0x64, 0xf3, 0xb8, 0xbd, 0x28, 0xf9, ++ 0xa9, 0xb7, 0x76, 0x58, 0x5f, 0xbf, 0x82, 0xfa, 0x9d, 0x7e, 0x8d, 0xe2, ++ 0xb6, 0x60, 0xa6, 0xd2, 0xfc, 0xce, 0x4e, 0xeb, 0x4f, 0xf8, 0xc6, 0xfa, ++ 0xe6, 0x7b, 0x3c, 0x3a, 0xf5, 0xf8, 0x76, 0xd4, 0x68, 0x17, 0xb7, 0x53, ++ 0x57, 0xd8, 0xe3, 0xeb, 0x6f, 0x8d, 0x71, 0xfb, 0x60, 0x74, 0x5b, 0x17, ++ 0xed, 0x37, 0xe2, 0xbd, 0x4a, 0x88, 0xef, 0xac, 0xe3, 0x4d, 0x0a, 0xfa, ++ 0xd3, 0x67, 0x15, 0x9e, 0x2f, 0xd1, 0x17, 0xf0, 0xb1, 0x1b, 0xca, 0x59, ++ 0x13, 0x9a, 0xe8, 0xde, 0xa5, 0x6d, 0xce, 0xe0, 0x75, 0x2e, 0x80, 0xef, ++ 0x8f, 0xc6, 0x89, 0xbc, 0x15, 0x00, 0x8e, 0x2b, 0xff, 0xf7, 0xd9, 0xd8, ++ 0x4e, 0xe2, 0x43, 0x2d, 0xd0, 0x9d, 0xa8, 0x4f, 0xb2, 0xf6, 0x7e, 0xc0, ++ 0xcf, 0xe1, 0xd8, 0xda, 0x75, 0xcc, 0x4f, 0xfb, 0xce, 0xaa, 0x17, 0x28, ++ 0x3e, 0xa8, 0xea, 0xa5, 0x39, 0xbc, 0x5c, 0xb7, 0x02, 0xe3, 0x87, 0x69, ++ 0xde, 0xd2, 0x2d, 0xc8, 0x27, 0x2c, 0xf4, 0xc2, 0xa4, 0xd7, 0xc0, 0xe7, ++ 0x79, 0x4c, 0x9c, 0x2b, 0xc6, 0x37, 0xa8, 0xf7, 0xd6, 0xb8, 0x44, 0x39, ++ 0xf4, 0x7c, 0x43, 0x00, 0xf8, 0x64, 0x8d, 0x9d, 0x97, 0xbf, 0xb3, 0xea, ++ 0xb9, 0x06, 0x3c, 0x77, 0xbc, 0xc6, 0x5e, 0xba, 0x10, 0xcf, 0x25, 0x63, ++ 0xb9, 0x01, 0xfa, 0x5f, 0x93, 0xdc, 0x9c, 0x69, 0x83, 0xb2, 0xbb, 0xfe, ++ 0xd9, 0x86, 0xa3, 0x03, 0xb0, 0x2c, 0xeb, 0x3f, 0x4b, 0x7c, 0x76, 0xa7, ++ 0x8b, 0x9f, 0xef, 0x61, 0xee, 0xd2, 0x2c, 0xc4, 0x7b, 0x77, 0xd9, 0x80, ++ 0xf2, 0x70, 0x53, 0x59, 0xe3, 0x65, 0xe6, 0xe4, 0x4f, 0x39, 0xbf, 0xaa, ++ 0x43, 0x7f, 0x3a, 0xd2, 0x0f, 0xf8, 0xa5, 0x7a, 0x2f, 0xbf, 0x87, 0xa6, ++ 0x1b, 0x6f, 0xad, 0xeb, 0x15, 0x5c, 0x4f, 0x7e, 0x52, 0x77, 0xd4, 0xd7, ++ 0xa0, 0x09, 0x39, 0x91, 0xfa, 0x03, 0xd6, 0xe5, 0xab, 0x32, 0x19, 0xf9, ++ 0x15, 0x7a, 0x58, 0x09, 0xe7, 0x2a, 0x78, 0x1f, 0xc7, 0xca, 0x74, 0x73, ++ 0x3e, 0xc9, 0xad, 0x89, 0x8a, 0x58, 0x5f, 0xa0, 0xbd, 0x39, 0x2e, 0x18, ++ 0x73, 0xee, 0x8c, 0x8e, 0xb2, 0xe0, 0xfa, 0xda, 0xc0, 0xf3, 0x36, 0x62, ++ 0xe9, 0xfa, 0x46, 0x42, 0x51, 0x43, 0xc2, 0x18, 0x3c, 0x2f, 0x1a, 0x5c, ++ 0xad, 0xa2, 0x1e, 0x7c, 0xc1, 0x6e, 0x50, 0xde, 0x7b, 0xbb, 0x46, 0x7a, ++ 0xbb, 0x43, 0xe6, 0xbd, 0xd7, 0xda, 0xc9, 0x7e, 0xab, 0x14, 0xe7, 0x50, ++ 0xed, 0xcb, 0x82, 0xab, 0x87, 0xa1, 0x5c, 0xdc, 0xab, 0xf9, 0x31, 0x0e, ++ 0x50, 0x91, 0xd3, 0x54, 0x84, 0xf6, 0x4b, 0xc5, 0x2b, 0x39, 0xfe, 0x7a, ++ 0x16, 0xcd, 0xa3, 0xad, 0x48, 0x6e, 0x4e, 0x1f, 0xe9, 0x8e, 0xe6, 0xd1, ++ 0xca, 0xf2, 0x72, 0x11, 0x37, 0xca, 0x48, 0xae, 0x4d, 0x4e, 0xce, 0xc7, ++ 0xfd, 0x92, 0xf5, 0xd9, 0xb8, 0x9f, 0x51, 0xcd, 0x9a, 0xee, 0xfb, 0x01, ++ 0xc2, 0xfb, 0xa6, 0xca, 0x90, 0xdf, 0x3f, 0x3d, 0x30, 0x3e, 0x09, 0xef, ++ 0x05, 0xaa, 0x82, 0x32, 0xc6, 0xa9, 0xaa, 0x5a, 0x8e, 0xe9, 0x41, 0xa8, ++ 0x57, 0x90, 0xc0, 0xef, 0xa3, 0xa9, 0x6e, 0x01, 0xbe, 0x71, 0xf3, 0x7b, ++ 0x62, 0x02, 0x79, 0x8c, 0x6d, 0xd1, 0x8c, 0x04, 0xd4, 0xf3, 0x3f, 0x09, ++ 0xd4, 0x5e, 0x8d, 0x26, 0xec, 0x13, 0xae, 0xa3, 0x93, 0x5c, 0x40, 0xd7, ++ 0x67, 0x73, 0x03, 0x06, 0xd2, 0xf9, 0xa5, 0x55, 0x6f, 0x35, 0x38, 0xbf, ++ 0x05, 0x65, 0xdd, 0x18, 0xc6, 0x46, 0x60, 0xf9, 0x9d, 0x06, 0xe4, 0xb3, ++ 0x8a, 0x11, 0x36, 0xca, 0x83, 0x64, 0xa1, 0x77, 0x5e, 0x0b, 0x0c, 0x16, ++ 0xfb, 0xb1, 0x50, 0x7e, 0xc8, 0x95, 0x31, 0xd9, 0x1c, 0x97, 0xce, 0x12, ++ 0xeb, 0x78, 0xcd, 0x26, 0x37, 0x9d, 0xd7, 0x82, 0x75, 0xf9, 0x71, 0xe4, ++ 0xef, 0xea, 0x8d, 0xb6, 0x10, 0xee, 0x6f, 0xd9, 0x9c, 0x6d, 0x74, 0x4e, ++ 0xe7, 0x25, 0x97, 0x5c, 0xff, 0xad, 0xe7, 0x9b, 0x36, 0x28, 0x5c, 0x1f, ++ 0x86, 0xe6, 0xf1, 0x38, 0xe7, 0x92, 0x9b, 0x52, 0xbe, 0x4d, 0xe7, 0x9b, ++ 0x56, 0xe4, 0x1a, 0xa1, 0x4b, 0xc4, 0x5b, 0xcb, 0x2e, 0x26, 0xd0, 0x39, ++ 0x26, 0x59, 0x2e, 0x48, 0xf0, 0x51, 0xff, 0x65, 0x5a, 0x88, 0xf6, 0x79, ++ 0xca, 0x2e, 0x7a, 0xe9, 0xfc, 0xd3, 0xdf, 0x6e, 0x3c, 0xa7, 0xe5, 0x3c, ++ 0x55, 0xcf, 0xf1, 0xdc, 0x04, 0x8f, 0x1c, 0xaf, 0x32, 0x3a, 0x1e, 0xd1, ++ 0xf5, 0xd0, 0xc8, 0x5f, 0x3d, 0x3e, 0x18, 0xe8, 0xb6, 0x64, 0x97, 0xdd, ++ 0xe6, 0x30, 0xf1, 0xdd, 0x92, 0x5d, 0x62, 0xff, 0xdc, 0x15, 0xc8, 0xc0, ++ 0x7e, 0xd2, 0x74, 0x8e, 0x67, 0x86, 0xfe, 0x1b, 0xf0, 0x1a, 0xdd, 0x41, ++ 0xc3, 0xcb, 0x21, 0x0d, 0xd6, 0x81, 0x75, 0x52, 0xbe, 0x43, 0x1d, 0x0d, ++ 0x93, 0x26, 0x20, 0xdd, 0xa2, 0xdf, 0x99, 0x55, 0xfe, 0x03, 0xe8, 0x3f, ++ 0xaf, 0x4b, 0x90, 0xe5, 0x0b, 0xf1, 0xeb, 0x27, 0xc4, 0xd4, 0xcf, 0x95, ++ 0xfd, 0xff, 0x85, 0xea, 0xc7, 0xc2, 0x93, 0x96, 0x10, 0x2d, 0x3b, 0xa1, ++ 0xbe, 0xf6, 0x17, 0x47, 0x77, 0x19, 0xe1, 0x5b, 0x6f, 0x8b, 0xe9, 0x2f, ++ 0x45, 0x96, 0xf5, 0x15, 0x93, 0xfa, 0x47, 0xf9, 0xea, 0xa1, 0x55, 0xde, ++ 0xc3, 0x21, 0xe0, 0xab, 0x75, 0xc9, 0x4d, 0x45, 0xa8, 0xff, 0xbb, 0xe6, ++ 0x31, 0x1f, 0xde, 0x73, 0x85, 0xfc, 0xea, 0x37, 0xe9, 0xdb, 0x87, 0x5c, ++ 0x5c, 0xcf, 0x96, 0x5d, 0xcc, 0xb5, 0xd0, 0x3b, 0x8a, 0xf7, 0x3c, 0x0b, ++ 0x5d, 0x4e, 0xd7, 0x65, 0x5a, 0xf6, 0x25, 0x17, 0xcc, 0x5c, 0x42, 0xfb, ++ 0xa7, 0x0f, 0xa1, 0xb0, 0x60, 0x3f, 0x2c, 0xc4, 0xcf, 0xc1, 0x6c, 0xea, ++ 0xc7, 0xc2, 0xa6, 0xb8, 0xcd, 0xff, 0x87, 0xe3, 0xaf, 0x85, 0xe3, 0xba, ++ 0x5e, 0xe0, 0xf8, 0x87, 0xff, 0x62, 0x38, 0x7c, 0x96, 0xf1, 0xa2, 0x70, ++ 0x0c, 0xb6, 0xc0, 0xf7, 0xd7, 0xc2, 0xb1, 0xf5, 0xce, 0xbc, 0x6f, 0xe7, ++ 0x40, 0x95, 0xc7, 0x94, 0x90, 0x33, 0x17, 0xd7, 0x85, 0x1f, 0xf1, 0xbc, ++ 0x35, 0x35, 0x79, 0x92, 0xaf, 0x1e, 0xf7, 0x4b, 0x7e, 0xa4, 0x51, 0xdc, ++ 0x7d, 0x08, 0xe3, 0xf9, 0x28, 0xb9, 0x1a, 0x3b, 0xaa, 0x8d, 0x44, 0xf9, ++ 0x69, 0x0a, 0x60, 0xdc, 0x82, 0x2d, 0xe3, 0xf6, 0x0a, 0xbc, 0x5f, 0x69, ++ 0x1f, 0x49, 0xeb, 0x10, 0xf9, 0x0b, 0x83, 0xf6, 0x3a, 0x66, 0x61, 0x5e, ++ 0x45, 0x6e, 0x59, 0x60, 0x21, 0x3e, 0x59, 0xff, 0x7c, 0xda, 0x8f, 0x91, ++ 0xfb, 0x98, 0x4c, 0xc4, 0xf5, 0xe4, 0xfe, 0xcb, 0x10, 0x83, 0x15, 0xe1, ++ 0xbd, 0x7c, 0x6f, 0x27, 0xcc, 0xa2, 0x75, 0x2a, 0xb7, 0x74, 0x66, 0x05, ++ 0xc6, 0xbf, 0x55, 0xcf, 0xe8, 0x04, 0x5c, 0x0f, 0x1f, 0xb3, 0x85, 0x43, ++ 0x38, 0x5e, 0xe8, 0x51, 0x3e, 0x5e, 0x9a, 0x2d, 0xdc, 0xec, 0x44, 0x7b, ++ 0xc9, 0x3b, 0xd8, 0xc0, 0xf5, 0x2e, 0xcd, 0xcb, 0xf5, 0x1f, 0x5b, 0x9d, ++ 0x4f, 0xeb, 0xdf, 0x56, 0x5b, 0xee, 0xd5, 0x8b, 0x00, 0x8e, 0x15, 0x4a, ++ 0x51, 0xc2, 0x1b, 0x88, 0xe7, 0xe4, 0x5c, 0x8a, 0x63, 0xe3, 0x7b, 0xbc, ++ 0x07, 0x67, 0xab, 0x58, 0xb7, 0xd4, 0x64, 0xbf, 0x81, 0xeb, 0xd4, 0x56, ++ 0xb1, 0x6e, 0x2d, 0x17, 0xfa, 0x5d, 0xbe, 0x4f, 0x4c, 0x29, 0x9d, 0x85, ++ 0x76, 0xc4, 0xf2, 0xd5, 0x45, 0x93, 0x9d, 0xe3, 0x51, 0x0f, 0x05, 0x56, ++ 0xf6, 0x81, 0xf5, 0x66, 0xd9, 0xea, 0xa2, 0x15, 0x99, 0xe3, 0x71, 0xbd, ++ 0xf1, 0xe5, 0x3a, 0x61, 0x7d, 0x59, 0x96, 0x50, 0xb4, 0xc2, 0x09, 0x93, ++ 0xd9, 0x5a, 0xef, 0xeb, 0x6b, 0x24, 0x47, 0xcb, 0x43, 0xfe, 0x02, 0xab, ++ 0x35, 0xe9, 0x89, 0xa2, 0x15, 0x68, 0xa7, 0x34, 0xb8, 0x17, 0x97, 0xa3, ++ 0x9d, 0x03, 0xdf, 0x0f, 0xa3, 0x5f, 0xf8, 0x6c, 0x8a, 0xd4, 0x3b, 0xfc, ++ 0x7b, 0xae, 0xd4, 0x53, 0xa8, 0x97, 0x40, 0x8f, 0xa9, 0xf5, 0xdd, 0xe5, ++ 0x10, 0xea, 0xa5, 0xdc, 0x6e, 0xbd, 0x53, 0x44, 0x7a, 0x67, 0xfb, 0xd3, ++ 0x2a, 0x95, 0xcb, 0x60, 0x3c, 0xb4, 0x7b, 0x60, 0x1e, 0x21, 0xbc, 0xbf, ++ 0xab, 0x6b, 0x88, 0x46, 0xfe, 0x91, 0x0b, 0x60, 0x49, 0x80, 0xb2, 0x6b, ++ 0x58, 0x2e, 0xed, 0x6b, 0xc1, 0xbc, 0x59, 0x02, 0xc6, 0xf5, 0x87, 0xf1, ++ 0xef, 0x72, 0x5f, 0x42, 0x1f, 0x62, 0xa3, 0x7d, 0x09, 0xac, 0x8f, 0x78, ++ 0x74, 0x65, 0xf1, 0xfa, 0xfa, 0x34, 0x7e, 0x9e, 0x59, 0xf7, 0xb8, 0xc9, ++ 0x6f, 0x93, 0xfb, 0x1c, 0xaa, 0xd8, 0x57, 0x4b, 0x10, 0x79, 0x24, 0x8a, ++ 0x31, 0x8d, 0xce, 0xd9, 0x3a, 0xd7, 0x8e, 0x5c, 0x8c, 0x7e, 0x94, 0x73, ++ 0xb0, 0x75, 0xff, 0x58, 0x8f, 0xc9, 0x37, 0x51, 0x63, 0xf3, 0x4f, 0xdc, ++ 0x11, 0xb2, 0xbb, 0x1a, 0x12, 0x44, 0x9c, 0xb9, 0x0f, 0xcb, 0xa4, 0x7b, ++ 0x0d, 0xc4, 0x7b, 0xc6, 0xfc, 0x23, 0xf1, 0x99, 0x7e, 0x77, 0x43, 0x11, ++ 0xdd, 0x77, 0xe7, 0x61, 0x06, 0xe6, 0x3b, 0x67, 0x06, 0x23, 0xcc, 0x6c, ++ 0x2f, 0xc9, 0xa7, 0x03, 0xd6, 0x51, 0x9f, 0x49, 0x6e, 0x1c, 0x6e, 0x16, ++ 0x88, 0x97, 0xef, 0x70, 0x4f, 0x22, 0xb7, 0x87, 0xdd, 0x17, 0x35, 0xee, ++ 0x27, 0x2a, 0x60, 0xdf, 0xe0, 0x3a, 0xea, 0x11, 0x76, 0xb8, 0xb0, 0x8f, ++ 0xec, 0xf2, 0x1e, 0xa2, 0x98, 0x75, 0x57, 0xda, 0x4b, 0x76, 0x71, 0xdf, ++ 0xdd, 0x92, 0x9b, 0x26, 0x66, 0xe0, 0xb9, 0x21, 0xd5, 0x1d, 0x70, 0xa2, ++ 0x9d, 0x73, 0xc0, 0x18, 0x49, 0xfb, 0x29, 0x2a, 0xf3, 0xdf, 0x5a, 0x64, ++ 0xb2, 0x77, 0x1a, 0x22, 0x37, 0x51, 0x3c, 0x51, 0x33, 0x02, 0x0c, 0xed, ++ 0x9c, 0xfd, 0xc2, 0xce, 0x51, 0x0d, 0x3f, 0x33, 0xdb, 0x39, 0x8d, 0x75, ++ 0xe0, 0x80, 0xc3, 0x5a, 0xb5, 0xad, 0x30, 0x8f, 0xee, 0x97, 0x79, 0xca, ++ 0x15, 0x71, 0x0e, 0x42, 0xfa, 0x3e, 0x66, 0xf3, 0xa3, 0xde, 0x38, 0x34, ++ 0xb2, 0x3c, 0xa4, 0x60, 0x3c, 0x71, 0x29, 0x23, 0x39, 0xdd, 0x56, 0x98, ++ 0x3e, 0x11, 0xf7, 0x03, 0xb6, 0x68, 0xa5, 0x49, 0xf7, 0xa2, 0xbc, 0x1c, ++ 0x87, 0xf1, 0x7c, 0x9c, 0x6e, 0x7c, 0xff, 0x79, 0xb9, 0x82, 0xf1, 0xef, ++ 0x0b, 0xce, 0xd2, 0x24, 0xd4, 0x07, 0xeb, 0x92, 0x99, 0xc5, 0x8f, 0x2a, ++ 0x4e, 0xe4, 0xfe, 0xc8, 0x93, 0x09, 0xdc, 0xee, 0x94, 0x7e, 0x42, 0x23, ++ 0xc0, 0x13, 0x01, 0x38, 0xb4, 0x8b, 0x57, 0xd3, 0x7d, 0x3b, 0x43, 0x84, ++ 0x5d, 0xaa, 0xcf, 0x9c, 0x44, 0xf1, 0x2d, 0x4c, 0xd3, 0xc1, 0x78, 0xa5, ++ 0x83, 0xd5, 0x86, 0x0c, 0x77, 0xf4, 0x3e, 0x39, 0x47, 0xa6, 0xcd, 0x92, ++ 0x9f, 0xa8, 0x5d, 0x2c, 0xa0, 0xf8, 0xdf, 0x93, 0x09, 0x36, 0xcb, 0xfe, ++ 0xd1, 0xc3, 0xe2, 0x3e, 0x40, 0x59, 0x76, 0xb2, 0x5a, 0x1e, 0xe7, 0x05, ++ 0x9e, 0x8e, 0xe7, 0xbf, 0xcd, 0x12, 0x70, 0x3a, 0xc0, 0x1e, 0xf2, 0x91, ++ 0x7d, 0x12, 0xb3, 0x3f, 0xdf, 0xd3, 0x3e, 0x22, 0x7b, 0x45, 0xd2, 0xa7, ++ 0xdb, 0x4e, 0x51, 0xf8, 0xb9, 0xcd, 0xde, 0xec, 0xa3, 0x9a, 0x8b, 0x36, ++ 0x8b, 0x9e, 0x8d, 0x9e, 0x37, 0xd7, 0x49, 0x2f, 0x9f, 0x13, 0xe7, 0xf9, ++ 0x65, 0x9e, 0x86, 0x5b, 0xe8, 0xb3, 0xc6, 0xcc, 0x60, 0xd3, 0xf5, 0x39, ++ 0xd1, 0xf3, 0xfb, 0x9a, 0xc8, 0xd7, 0x58, 0x2b, 0xce, 0xed, 0xb3, 0x4c, ++ 0xad, 0xcb, 0x7c, 0x4e, 0x3e, 0x11, 0xe3, 0x31, 0xf0, 0xbd, 0x41, 0xe4, ++ 0x6d, 0x24, 0xc6, 0x9c, 0xbb, 0x77, 0xb9, 0x97, 0x90, 0xbf, 0xe0, 0x1a, ++ 0xaa, 0x59, 0xce, 0x69, 0x39, 0x59, 0x90, 0xda, 0x39, 0x7c, 0xd6, 0xf7, ++ 0x5a, 0x66, 0xec, 0x79, 0xfe, 0x50, 0x77, 0x9e, 0x16, 0xe5, 0x15, 0x6a, ++ 0xec, 0x49, 0x85, 0x0e, 0xef, 0x73, 0x7b, 0xb7, 0x9f, 0xc8, 0x93, 0x3a, ++ 0x9b, 0xf8, 0x7e, 0x21, 0xca, 0x2f, 0xd8, 0xbb, 0x3f, 0x77, 0xd2, 0x3e, ++ 0x02, 0x3f, 0xc7, 0x29, 0xe3, 0x59, 0xdf, 0xd4, 0x3e, 0xde, 0x8f, 0x76, ++ 0xd5, 0x18, 0xf4, 0x0b, 0xa7, 0x8c, 0xc0, 0x7e, 0xbf, 0x23, 0xd6, 0xa3, ++ 0x2c, 0x56, 0x9a, 0xc5, 0x37, 0x07, 0x9b, 0x19, 0xe5, 0xf5, 0x24, 0xf8, ++ 0xdb, 0x19, 0xbf, 0x13, 0x8c, 0xec, 0x2d, 0x55, 0xea, 0xb9, 0xd0, 0x0b, ++ 0x0d, 0xe8, 0x47, 0xa5, 0x99, 0xed, 0x3b, 0x93, 0xbd, 0x36, 0x70, 0xcd, ++ 0x0b, 0x0d, 0x0d, 0xdc, 0xef, 0xa0, 0xf2, 0x77, 0x56, 0xad, 0x26, 0x3d, ++ 0xb8, 0xc2, 0x25, 0xcb, 0x2b, 0xa8, 0x0c, 0xeb, 0x55, 0x04, 0xfd, 0x1e, ++ 0xb6, 0xc7, 0xe1, 0x43, 0x7e, 0x82, 0xf6, 0x01, 0x94, 0x1b, 0x76, 0x67, ++ 0x1e, 0xd9, 0xcb, 0x6a, 0x2e, 0xb8, 0xb4, 0x00, 0xf7, 0x24, 0xbc, 0x9f, ++ 0x10, 0xe3, 0xf9, 0x7b, 0x1c, 0x5b, 0xd1, 0x9e, 0x05, 0xbf, 0xf6, 0x4e, ++ 0x97, 0x89, 0x4f, 0xcf, 0x7a, 0x4e, 0x64, 0xb3, 0xfc, 0xb8, 0xfd, 0x85, ++ 0x2c, 0xfd, 0x65, 0x7f, 0xb3, 0xfe, 0x60, 0xfc, 0x16, 0xcc, 0x03, 0x92, ++ 0xdf, 0x27, 0x79, 0x37, 0x46, 0x54, 0xde, 0xce, 0x87, 0xed, 0x58, 0xff, ++ 0xb6, 0xf7, 0x43, 0xd0, 0xff, 0x63, 0x2f, 0x3b, 0xe8, 0xde, 0x10, 0x79, ++ 0x0f, 0x72, 0x2c, 0xbf, 0x16, 0x26, 0x72, 0xbb, 0x01, 0xf5, 0x86, 0x39, ++ 0xdf, 0x52, 0x9f, 0x39, 0x37, 0x80, 0xcc, 0x29, 0xe5, 0xd3, 0x91, 0x99, ++ 0x60, 0xc9, 0xd3, 0x96, 0xf2, 0xaa, 0x5d, 0x1c, 0x4a, 0xf2, 0x29, 0xdb, ++ 0xed, 0x4f, 0xc8, 0xe1, 0xf7, 0x73, 0x69, 0x01, 0x8a, 0xab, 0x69, 0x17, ++ 0xf3, 0x49, 0xfe, 0x9f, 0x14, 0x74, 0x6d, 0xac, 0x33, 0x2e, 0x33, 0x4e, ++ 0x4a, 0x2f, 0xe3, 0x8c, 0xa4, 0x7e, 0x7a, 0x1f, 0xa7, 0x50, 0xe8, 0x09, ++ 0x26, 0xf6, 0xb3, 0x34, 0xc3, 0x7c, 0xcf, 0x4b, 0x6f, 0xf2, 0x1a, 0xbb, ++ 0x7f, 0x17, 0xab, 0xdf, 0xe4, 0x53, 0xea, 0xb7, 0xdd, 0xa2, 0xff, 0x3b, ++ 0x12, 0xad, 0xf1, 0xe1, 0xf2, 0x8d, 0xcd, 0x47, 0x90, 0x85, 0x7e, 0x60, ++ 0x0b, 0xce, 0x48, 0x1c, 0x83, 0x79, 0x59, 0xef, 0x79, 0x71, 0x29, 0xae, ++ 0xb4, 0x45, 0x0a, 0x50, 0xde, 0x1e, 0xe8, 0xf9, 0xbe, 0x1a, 0x27, 0xb7, ++ 0xc0, 0xc5, 0xf7, 0x27, 0xf2, 0x76, 0x2c, 0x3a, 0x88, 0xec, 0x3a, 0x37, ++ 0x31, 0xd8, 0x84, 0xf6, 0xcc, 0x7d, 0x89, 0x22, 0x6e, 0x9f, 0x09, 0xeb, ++ 0x9a, 0x8a, 0xeb, 0x16, 0xcf, 0x2b, 0x5a, 0x87, 0xdf, 0x31, 0xfe, 0x1c, ++ 0xf4, 0x3d, 0x31, 0x19, 0xf5, 0xd4, 0xb4, 0x12, 0x8a, 0x3f, 0x6f, 0x4b, ++ 0x2c, 0x7d, 0x1d, 0xdb, 0xad, 0x9a, 0x5e, 0x48, 0xb1, 0x02, 0x09, 0xf7, ++ 0x9a, 0x3a, 0x9e, 0x0f, 0x27, 0xf5, 0xa5, 0x1b, 0xf1, 0x05, 0xf5, 0x1d, ++ 0x5a, 0x2d, 0xe1, 0xcd, 0xe1, 0x0e, 0x44, 0xd0, 0xbe, 0x68, 0x4c, 0xfc, ++ 0xf5, 0x64, 0xf4, 0xb1, 0x54, 0x8d, 0xcb, 0x41, 0xe5, 0x9a, 0xbd, 0x24, ++ 0x07, 0x4e, 0xcd, 0x4f, 0x7c, 0xe5, 0x74, 0xdb, 0x7c, 0xb8, 0xbe, 0x3b, ++ 0xc1, 0xbf, 0xc3, 0x75, 0xaf, 0xde, 0x6d, 0xa3, 0x78, 0xd2, 0x72, 0xbc, ++ 0xa7, 0x37, 0x07, 0xcf, 0x03, 0x4c, 0x35, 0x50, 0x5e, 0x17, 0x7b, 0x72, ++ 0x33, 0xd8, 0x25, 0xf4, 0xa3, 0x76, 0x31, 0x5d, 0xe8, 0x5f, 0xeb, 0xbd, ++ 0x37, 0x7f, 0xfb, 0x71, 0x52, 0xa9, 0x7d, 0x8f, 0xfb, 0x75, 0x0e, 0x8d, ++ 0x8f, 0x60, 0x7f, 0x9a, 0x9f, 0x51, 0x7e, 0x0b, 0x22, 0xe1, 0x43, 0x93, ++ 0x5e, 0x95, 0xeb, 0x7a, 0x6c, 0xbb, 0xd8, 0xfe, 0x25, 0x3e, 0x25, 0x7e, ++ 0x1d, 0x5a, 0x90, 0xf0, 0xaa, 0xa3, 0xdd, 0x10, 0x07, 0xae, 0xcd, 0xdd, ++ 0x71, 0x19, 0xae, 0x0f, 0x33, 0xa4, 0xfe, 0x4c, 0x7e, 0x3b, 0x2f, 0x02, ++ 0x6f, 0xab, 0x94, 0x76, 0x2f, 0xda, 0x27, 0xa0, 0x17, 0x37, 0x27, 0xa2, ++ 0x5e, 0x1c, 0xde, 0xf5, 0x6f, 0x8a, 0x8f, 0xf4, 0x69, 0x3a, 0xb7, 0x67, ++ 0x42, 0xf2, 0x3e, 0x01, 0xcb, 0xfd, 0x45, 0x32, 0x2e, 0xaf, 0xba, 0xb9, ++ 0x5d, 0x23, 0xe1, 0x5f, 0xfc, 0xc6, 0x63, 0x4e, 0xf3, 0x3e, 0x51, 0x2c, ++ 0xbc, 0xb1, 0xeb, 0xa5, 0x3b, 0xdf, 0x9a, 0x47, 0xe1, 0xec, 0x9f, 0x10, ++ 0x73, 0x9f, 0x6f, 0x3d, 0x1f, 0x47, 0x2b, 0x25, 0xbe, 0xb1, 0x4f, 0x08, ++ 0x38, 0x51, 0x4e, 0xea, 0x8d, 0x91, 0x06, 0xda, 0x2b, 0x0d, 0x9a, 0xef, ++ 0x77, 0x01, 0xca, 0xff, 0xb0, 0x93, 0xdd, 0x0c, 0x76, 0xb8, 0x65, 0x7c, ++ 0xf9, 0x5c, 0x27, 0xee, 0xef, 0x3d, 0x2c, 0xec, 0xa8, 0xd8, 0xef, 0x1e, ++ 0x71, 0xdf, 0x71, 0xec, 0xfb, 0x8f, 0x05, 0xfe, 0xd6, 0x1d, 0xb8, 0x9b, ++ 0xf4, 0x70, 0x6f, 0xf4, 0xc3, 0x03, 0xcf, 0x48, 0x5f, 0x4f, 0x2e, 0x33, ++ 0xf0, 0xfc, 0x8c, 0x5d, 0xc0, 0xeb, 0xbd, 0x4c, 0xbf, 0xbd, 0xf1, 0xd1, ++ 0x23, 0x07, 0x78, 0x5c, 0x57, 0x1b, 0xe7, 0x0c, 0xa3, 0x8b, 0x15, 0x3b, ++ 0x9e, 0x6a, 0x2f, 0x0d, 0xe0, 0x79, 0x2f, 0x75, 0x04, 0x23, 0x7b, 0x57, ++ 0x1d, 0xc0, 0xc7, 0x07, 0x5a, 0x1a, 0x18, 0x17, 0xf6, 0x8e, 0x4e, 0x61, ++ 0x43, 0x4d, 0xeb, 0xec, 0xaa, 0xc1, 0xd3, 0xf9, 0xfd, 0xcb, 0x69, 0x06, ++ 0x9d, 0xbf, 0x53, 0x3d, 0xb6, 0xd2, 0x78, 0x76, 0xa6, 0xc4, 0x53, 0x6b, ++ 0xa2, 0xcd, 0xb2, 0x3f, 0x9f, 0x29, 0xf9, 0x66, 0xc8, 0xef, 0x69, 0x3f, ++ 0xc9, 0xc4, 0x37, 0x1f, 0xa1, 0x7e, 0x89, 0xe5, 0x9b, 0x56, 0xe4, 0xe1, ++ 0x34, 0x0e, 0x87, 0x99, 0x9e, 0xab, 0x06, 0xe7, 0x66, 0xc4, 0xa3, 0x4f, ++ 0x54, 0x2f, 0x72, 0xbe, 0xba, 0x1c, 0x5f, 0x14, 0x4e, 0xe0, 0xfc, 0x9e, ++ 0x01, 0xcf, 0x2d, 0x30, 0x8f, 0x16, 0x71, 0x9f, 0x46, 0x15, 0xe2, 0x0a, ++ 0xfc, 0x9d, 0xca, 0xbb, 0xdc, 0xcc, 0x80, 0x75, 0xed, 0x2b, 0x4f, 0xd1, ++ 0x17, 0x08, 0x5f, 0x61, 0xdb, 0x41, 0x9e, 0xef, 0xde, 0x92, 0x46, 0xce, ++ 0x5f, 0xe5, 0x84, 0xf8, 0xf2, 0xb2, 0xc8, 0xcd, 0xe9, 0xb2, 0xc8, 0xcd, ++ 0xe3, 0xa8, 0x49, 0x27, 0x02, 0x3f, 0xc5, 0x7b, 0xc3, 0x5b, 0xda, 0x12, ++ 0x7c, 0x0a, 0x7c, 0x6a, 0x49, 0x89, 0xaf, 0xa7, 0x0b, 0xdc, 0x52, 0xce, ++ 0x44, 0xfe, 0x84, 0xd6, 0x5e, 0x80, 0xf6, 0x88, 0xac, 0x5f, 0x38, 0xd3, ++ 0x3a, 0x9e, 0xcf, 0xcd, 0xd7, 0xbf, 0x01, 0xb2, 0x5d, 0xe8, 0xd6, 0x14, ++ 0xb4, 0xcb, 0xa6, 0x62, 0x17, 0x80, 0xc7, 0x41, 0x7e, 0x85, 0xe7, 0x71, ++ 0xb4, 0x26, 0x86, 0xf1, 0x7e, 0x7a, 0xb0, 0x6a, 0xb5, 0xdb, 0x00, 0xaf, ++ 0x3b, 0x84, 0xff, 0xb7, 0x03, 0xfc, 0xc2, 0x69, 0xd0, 0x6f, 0x7a, 0x02, ++ 0x0b, 0xe2, 0xbc, 0xd3, 0xfa, 0x40, 0x39, 0x9f, 0xda, 0x07, 0x76, 0xb9, ++ 0xa3, 0xfd, 0xbd, 0xc9, 0x51, 0xc6, 0x26, 0x0f, 0x2a, 0xdd, 0x8e, 0xfd, ++ 0x4d, 0xce, 0xc8, 0x1a, 0xb1, 0x3c, 0x87, 0xb7, 0xc7, 0x7e, 0x0e, 0x27, ++ 0xb0, 0x06, 0xe7, 0xc8, 0x28, 0xde, 0x6f, 0x75, 0x00, 0xcb, 0xa5, 0xe0, ++ 0xf7, 0x50, 0xdf, 0x45, 0xf9, 0xd1, 0xf7, 0x87, 0x51, 0x76, 0xa1, 0x5e, ++ 0x7a, 0x7a, 0x7b, 0x81, 0x82, 0xfb, 0x92, 0xb6, 0x40, 0x3a, 0xae, 0x23, ++ 0x1f, 0x1d, 0xfb, 0x01, 0xe5, 0xc1, 0x2e, 0xc0, 0x7b, 0x8c, 0x9c, 0x78, ++ 0xa5, 0x84, 0x4a, 0x7e, 0x52, 0xe1, 0x89, 0x52, 0xba, 0xb7, 0xec, 0x53, ++ 0xfc, 0x98, 0x85, 0xf7, 0x1d, 0x95, 0x0e, 0x73, 0x8f, 0xc1, 0xfc, 0x30, ++ 0xeb, 0x3d, 0xa4, 0x6c, 0x3b, 0x3f, 0x3f, 0x23, 0xf1, 0xd5, 0x93, 0x1f, ++ 0xb8, 0xfe, 0x01, 0x38, 0x43, 0xce, 0x14, 0x0b, 0x9c, 0x6c, 0x1c, 0xc2, ++ 0xed, 0xe4, 0xed, 0x62, 0xf1, 0xdb, 0xfd, 0x14, 0x7c, 0x2c, 0xe9, 0x09, ++ 0xe8, 0xb9, 0xc6, 0x23, 0xe8, 0x89, 0x72, 0xda, 0x22, 0xee, 0xc5, 0xec, ++ 0xe6, 0x1b, 0x71, 0xaf, 0x42, 0x87, 0xb8, 0x0f, 0x6a, 0x76, 0xa2, 0xb8, ++ 0x17, 0xca, 0xe0, 0xfe, 0x95, 0xbc, 0xe7, 0xa4, 0x45, 0x0b, 0x24, 0xa2, ++ 0x7d, 0x3e, 0xbb, 0x3b, 0x3f, 0x21, 0x40, 0xe7, 0x8f, 0x2a, 0x5d, 0x81, ++ 0xa4, 0xf1, 0x48, 0xb7, 0x63, 0xdc, 0x7f, 0x3a, 0x5d, 0xc4, 0xef, 0xa7, ++ 0x3b, 0x6d, 0x0f, 0x24, 0xa1, 0xbc, 0x9e, 0x3e, 0xa6, 0x2a, 0xf5, 0x94, ++ 0xdf, 0xc1, 0xf3, 0x3e, 0x65, 0x5e, 0xdd, 0x69, 0xbb, 0x6f, 0xcd, 0xd5, ++ 0xf0, 0x7d, 0xce, 0x3f, 0xab, 0x81, 0x7a, 0xfa, 0x6c, 0xf5, 0x0b, 0x3a, ++ 0x58, 0x60, 0xd4, 0xbf, 0xa2, 0x9f, 0xd4, 0xaa, 0xd2, 0x3e, 0x64, 0xce, ++ 0xa3, 0xb3, 0xd4, 0xe1, 0x50, 0x7f, 0x2e, 0x38, 0x0c, 0xa8, 0x8f, 0x66, ++ 0x17, 0xbb, 0x43, 0x68, 0xc7, 0xb5, 0xfc, 0xbe, 0xf6, 0x7d, 0x5c, 0xcf, ++ 0xe6, 0x3c, 0xed, 0xf0, 0x2d, 0x83, 0x71, 0x5e, 0xdb, 0x38, 0xea, 0x0b, ++ 0x2c, 0x9f, 0x5a, 0xeb, 0xf1, 0x39, 0x28, 0xde, 0x9a, 0xab, 0xe0, 0xfd, ++ 0xf1, 0x4b, 0xd6, 0xe7, 0x18, 0xb4, 0x0f, 0xb9, 0x94, 0x89, 0x38, 0xf3, ++ 0xc4, 0x92, 0x62, 0x58, 0x83, 0x9f, 0xc7, 0xa1, 0xe5, 0xfe, 0x85, 0x93, ++ 0xee, 0x93, 0x17, 0xdf, 0xab, 0x1b, 0x27, 0xc1, 0xfc, 0xae, 0x4e, 0x6b, ++ 0xb1, 0x21, 0x2a, 0xff, 0xb0, 0xb6, 0xba, 0x11, 0xcf, 0xb3, 0xad, 0xa8, ++ 0x2f, 0xcd, 0xc4, 0x38, 0xc2, 0x5a, 0xf7, 0xe4, 0x46, 0x8c, 0x23, 0xa4, ++ 0xa7, 0x07, 0xda, 0x6e, 0x80, 0x75, 0x3d, 0xe2, 0xbe, 0xb1, 0x04, 0xcb, ++ 0x2d, 0x4f, 0xc9, 0xfe, 0xa6, 0x34, 0x62, 0xdc, 0xe0, 0x17, 0xb6, 0x60, ++ 0x8e, 0x02, 0xdf, 0x4f, 0xbb, 0x67, 0x95, 0x50, 0xfe, 0xf5, 0x20, 0xd9, ++ 0xff, 0x92, 0xc6, 0x00, 0xac, 0x09, 0xb3, 0x7f, 0x7c, 0xd5, 0x17, 0x27, ++ 0x30, 0x5f, 0x7b, 0x5d, 0x63, 0x09, 0xda, 0x05, 0x40, 0x57, 0x61, 0x5f, ++ 0xaf, 0x21, 0xf8, 0xe6, 0x4d, 0x90, 0xe5, 0x26, 0xbd, 0x78, 0x30, 0xb4, ++ 0x4f, 0x64, 0x96, 0x78, 0xaa, 0x3d, 0x1a, 0x97, 0xa0, 0x78, 0x6d, 0x4b, ++ 0xb7, 0x7d, 0xbe, 0xa1, 0x04, 0xe3, 0x10, 0x73, 0x26, 0xd6, 0x16, 0x6b, ++ 0xd0, 0x7f, 0xe1, 0xba, 0xa7, 0x1a, 0xf3, 0x41, 0xc5, 0x8e, 0x6d, 0x2a, ++ 0x32, 0x02, 0x50, 0xbe, 0x7e, 0xdd, 0xa6, 0x12, 0x5c, 0xff, 0x5a, 0x58, ++ 0xa0, 0x02, 0xed, 0x92, 0x1b, 0xd6, 0x3d, 0x5d, 0x82, 0x71, 0xf9, 0xd4, ++ 0x3e, 0xd6, 0xfe, 0x53, 0x55, 0x11, 0x97, 0x67, 0xdb, 0x1a, 0xb1, 0xbf, ++ 0xc2, 0x99, 0x81, 0x11, 0x0a, 0xb4, 0xff, 0x97, 0x75, 0x2f, 0x35, 0xa2, ++ 0x1f, 0x92, 0x86, 0xf9, 0xb9, 0x30, 0xde, 0x05, 0xcf, 0x9f, 0x1a, 0x43, ++ 0xfd, 0xa3, 0xfa, 0xf3, 0x96, 0xe8, 0x3d, 0x5a, 0xab, 0x51, 0x0e, 0xaa, ++ 0x9c, 0xed, 0x47, 0x30, 0x54, 0x9b, 0xbd, 0xb4, 0x4b, 0xe7, 0x79, 0xdb, ++ 0x42, 0x6f, 0xf4, 0xe7, 0xfc, 0xdc, 0x5d, 0x1e, 0xda, 0xce, 0xf3, 0xeb, ++ 0x65, 0x39, 0x93, 0x97, 0x5b, 0x96, 0xc5, 0xd7, 0x43, 0x8f, 0x7a, 0xb9, ++ 0xbf, 0xd9, 0x92, 0x10, 0xff, 0xfb, 0xab, 0x42, 0xef, 0x48, 0x79, 0x49, ++ 0x3a, 0xc1, 0x02, 0x3b, 0xe3, 0xc8, 0xcd, 0x16, 0xb7, 0xfb, 0xff, 0x48, ++ 0xee, 0x5a, 0xff, 0x6f, 0xe9, 0xb5, 0xe4, 0xcb, 0xe8, 0xb5, 0x64, 0xa9, ++ 0xd7, 0x04, 0x3e, 0xf3, 0xad, 0x7a, 0x1a, 0x86, 0x11, 0xfa, 0xfe, 0xea, ++ 0x5c, 0xd4, 0x0f, 0x0b, 0x30, 0xd9, 0xca, 0x64, 0x2f, 0x14, 0xb6, 0x4d, ++ 0xa7, 0x75, 0xe4, 0x7b, 0x5e, 0x6e, 0x3f, 0x33, 0x1f, 0x6f, 0x9f, 0x56, ++ 0xcc, 0xf3, 0x9d, 0xba, 0x5e, 0x49, 0xe4, 0xf7, 0xa4, 0x3a, 0xdb, 0xf2, ++ 0xcc, 0xfb, 0xa2, 0xc7, 0x05, 0x3e, 0x8a, 0x1f, 0x9e, 0xfa, 0x04, 0x9d, ++ 0x77, 0x6f, 0xb3, 0x33, 0x3a, 0xa7, 0xb2, 0xab, 0xe8, 0x92, 0x79, 0xa6, ++ 0x95, 0x18, 0xdf, 0x35, 0xf9, 0x1f, 0x95, 0x5a, 0x84, 0xfc, 0xfa, 0x4a, ++ 0x8c, 0xef, 0x8e, 0xc2, 0xfe, 0xde, 0xa4, 0x73, 0xa6, 0xd8, 0x0f, 0x9e, ++ 0x43, 0xc1, 0x7d, 0x0c, 0x8c, 0xcf, 0xa6, 0x2d, 0x8f, 0x4f, 0x7f, 0x69, ++ 0x4f, 0x55, 0x5e, 0x34, 0x58, 0xa8, 0x4f, 0xcf, 0x75, 0x37, 0xda, 0x7f, ++ 0x2a, 0x0b, 0x8d, 0xba, 0xfc, 0xbc, 0xa2, 0xfd, 0x59, 0xe3, 0x0f, 0x3d, ++ 0xfb, 0xd3, 0xc5, 0x7e, 0x50, 0xcc, 0xfa, 0xa8, 0xc7, 0x87, 0xf3, 0xcf, ++ 0x92, 0x4f, 0x01, 0xdf, 0x36, 0x13, 0x7f, 0xcd, 0x13, 0xfc, 0x26, 0xf7, ++ 0x95, 0xcf, 0xed, 0x19, 0xb6, 0xd5, 0xbc, 0x8f, 0x2f, 0xcf, 0x87, 0x81, ++ 0x7e, 0xfe, 0x29, 0xfe, 0x0e, 0x46, 0x08, 0xf4, 0x3c, 0xda, 0x99, 0x85, ++ 0x5a, 0xe0, 0x66, 0xac, 0x5f, 0xd8, 0x96, 0x42, 0xfb, 0x4c, 0x92, 0x3f, ++ 0x24, 0x5f, 0x48, 0xba, 0xb6, 0xa4, 0xd4, 0x52, 0xdc, 0xae, 0xeb, 0x49, ++ 0x85, 0xce, 0xeb, 0xc5, 0xc2, 0x65, 0xf3, 0x70, 0x3a, 0x16, 0x6e, 0xe4, ++ 0xf7, 0x33, 0x66, 0xcc, 0x0c, 0xaa, 0xe6, 0xfb, 0xe4, 0xa5, 0x3c, 0x40, ++ 0xff, 0x2d, 0xa2, 0xff, 0xd1, 0xe3, 0x48, 0x7e, 0x36, 0x73, 0x79, 0x00, ++ 0xb9, 0xb9, 0x17, 0xe5, 0x17, 0xef, 0xdb, 0xc1, 0x79, 0xf8, 0xdb, 0x0b, ++ 0xcc, 0xbf, 0x3b, 0x21, 0xe1, 0xaf, 0x40, 0x5e, 0x4c, 0x23, 0x3a, 0x72, ++ 0xfc, 0xbf, 0xec, 0xa2, 0xfd, 0xfe, 0xd8, 0x75, 0x32, 0x8a, 0xff, 0xbe, ++ 0x97, 0xa1, 0x67, 0x36, 0xd1, 0x53, 0xda, 0x41, 0x95, 0xbd, 0xae, 0x97, ++ 0x5e, 0x9e, 0xbf, 0x78, 0x22, 0xe2, 0xf5, 0x61, 0xfc, 0x08, 0xf9, 0x1f, ++ 0xf5, 0x49, 0xf3, 0x87, 0x74, 0x7f, 0x5c, 0x4b, 0xab, 0xca, 0x14, 0x1f, ++ 0x9f, 0x37, 0xea, 0xad, 0xc2, 0x6e, 0x7d, 0xfc, 0xf5, 0xe1, 0x89, 0x1a, ++ 0xd9, 0x63, 0xd1, 0xf5, 0xc3, 0x47, 0x76, 0x99, 0xd4, 0x9f, 0x11, 0xa7, ++ 0x33, 0x5a, 0xbf, 0x6b, 0xcd, 0xd7, 0x93, 0x71, 0x9f, 0x39, 0x55, 0xdc, ++ 0xcf, 0x9c, 0xaa, 0xe2, 0x11, 0xec, 0x28, 0x1c, 0x23, 0x3c, 0x5c, 0x8f, ++ 0x8d, 0x0b, 0xc6, 0x8f, 0x87, 0x16, 0xb8, 0x3d, 0x9c, 0x0e, 0x62, 0x1e, ++ 0x4f, 0x2e, 0x9d, 0xc8, 0x3e, 0x84, 0xf9, 0x7f, 0x4f, 0xac, 0xf3, 0xe3, ++ 0xda, 0x43, 0xf4, 0xfb, 0x49, 0x76, 0xc4, 0xe3, 0x98, 0x28, 0x3e, 0xa4, ++ 0x3e, 0xbb, 0xd5, 0xd1, 0xfe, 0xa2, 0x38, 0xf7, 0x62, 0xe1, 0x47, 0x59, ++ 0x06, 0x3b, 0xa7, 0xda, 0x36, 0xc8, 0xf4, 0xdd, 0xcd, 0xf5, 0xae, 0x1c, ++ 0x0f, 0xe0, 0x6d, 0xc0, 0xfb, 0x98, 0xd3, 0xe0, 0x89, 0x57, 0xff, 0x5f, ++ 0xf0, 0xe4, 0x88, 0x7d, 0x77, 0xce, 0x97, 0x27, 0xf7, 0x64, 0x6c, 0xa1, ++ 0xdf, 0x6d, 0x18, 0x14, 0x18, 0x81, 0xfa, 0x46, 0xf2, 0x17, 0xac, 0x27, ++ 0x62, 0xbe, 0xb6, 0xfb, 0xa7, 0xbb, 0x39, 0xff, 0x4f, 0x8f, 0x43, 0x87, ++ 0xe9, 0x82, 0xcf, 0xe6, 0x6d, 0xe4, 0xf3, 0x6f, 0xf9, 0x8f, 0xe2, 0x9b, ++ 0x91, 0x0f, 0x5a, 0xde, 0x4a, 0x49, 0x5e, 0x66, 0xe2, 0xf7, 0x7a, 0xa1, ++ 0x57, 0x64, 0xbf, 0x52, 0x9e, 0x64, 0x3b, 0xf9, 0x7d, 0x86, 0xe8, 0xef, ++ 0x5e, 0x8f, 0x97, 0x9e, 0xf5, 0x02, 0x7f, 0x08, 0x47, 0xbc, 0xfc, 0x0a, ++ 0xd9, 0x0e, 0xe7, 0x4b, 0xfa, 0x7a, 0x25, 0xd7, 0xd7, 0x30, 0xef, 0x10, ++ 0xd2, 0x09, 0xe6, 0x1d, 0xc2, 0x73, 0xf8, 0x17, 0x3c, 0x4a, 0x0c, 0x5e, ++ 0xc5, 0xfa, 0x20, 0xf0, 0x5d, 0xa5, 0x03, 0x9e, 0x01, 0x8f, 0x3b, 0xec, ++ 0xa1, 0xbe, 0x98, 0xaf, 0x95, 0xa6, 0xf2, 0x7c, 0x98, 0xcb, 0xc9, 0x2f, ++ 0xcc, 0x47, 0xfc, 0x8e, 0x80, 0x87, 0xf4, 0x4e, 0x6c, 0xff, 0x6b, 0x05, ++ 0x7f, 0x6c, 0x11, 0xf7, 0xe8, 0x1e, 0xb6, 0x81, 0x3c, 0xa3, 0x9c, 0xb9, ++ 0x39, 0xbc, 0xe7, 0xf6, 0x64, 0x51, 0xbf, 0x75, 0xa2, 0xde, 0xe5, 0xf5, ++ 0xe1, 0x95, 0xc9, 0xcf, 0x16, 0x91, 0xaf, 0x02, 0xf0, 0x53, 0x3e, 0x66, ++ 0xd5, 0xab, 0xfd, 0xb6, 0x58, 0xe1, 0xaf, 0x17, 0xf0, 0x07, 0x97, 0xe3, ++ 0x39, 0xc2, 0xd4, 0x27, 0x98, 0x7f, 0x39, 0x23, 0xbc, 0x45, 0x10, 0x5f, ++ 0x29, 0x5e, 0xbe, 0x9e, 0xb4, 0xe8, 0x41, 0xb2, 0xdf, 0xba, 0x9e, 0x64, ++ 0xe4, 0xb7, 0x0e, 0x01, 0x3b, 0xc2, 0x07, 0xe5, 0x9a, 0x52, 0xf7, 0x48, ++ 0x25, 0x27, 0x2a, 0xa7, 0x79, 0xcd, 0x0a, 0xd1, 0xb1, 0x70, 0x03, 0xac, ++ 0xd3, 0x88, 0x37, 0xa7, 0xc4, 0xdb, 0x1b, 0x3b, 0xcd, 0xe3, 0x6e, 0xf0, ++ 0x78, 0x2c, 0xf7, 0x10, 0x54, 0x0a, 0xfa, 0x0f, 0x81, 0xf5, 0xfd, 0xa7, ++ 0x00, 0xef, 0x10, 0xe8, 0xe7, 0x45, 0x82, 0x9b, 0xc3, 0x75, 0xf2, 0xf1, ++ 0xe6, 0xeb, 0x31, 0x3e, 0xd7, 0xbd, 0xde, 0x0b, 0xbe, 0xe8, 0x09, 0x67, ++ 0x44, 0xef, 0xc7, 0xe1, 0xa4, 0xbc, 0x0a, 0xb4, 0x77, 0x7c, 0xa3, 0xa3, ++ 0x70, 0x62, 0xff, 0x94, 0xe7, 0xe3, 0x2e, 0x5d, 0x86, 0xfd, 0x56, 0xff, ++ 0x66, 0x77, 0x3f, 0x73, 0xbf, 0x2f, 0x76, 0xf7, 0x3b, 0x7b, 0xa2, 0x0b, ++ 0xf5, 0xd8, 0x7a, 0xd0, 0xab, 0xa4, 0x0e, 0x82, 0x87, 0xf0, 0x1c, 0xc9, ++ 0xdc, 0xbd, 0xc9, 0x06, 0xde, 0xf7, 0x00, 0xfe, 0x82, 0x0d, 0xfd, 0x42, ++ 0x39, 0xee, 0x5c, 0x4d, 0xfe, 0xee, 0x4f, 0x7b, 0x21, 0xde, 0x77, 0x9e, ++ 0xd7, 0x3d, 0x0e, 0xe8, 0x4f, 0x93, 0xfe, 0x3b, 0xe0, 0x71, 0xf3, 0xfa, ++ 0xce, 0x83, 0x03, 0xf1, 0x1e, 0x6d, 0xa6, 0xf1, 0xf5, 0x29, 0xad, 0xe9, ++ 0xf4, 0x8f, 0x70, 0x1f, 0xa2, 0xb7, 0x75, 0xf5, 0x6f, 0xc5, 0x0f, 0x40, ++ 0x47, 0x9a, 0x77, 0xd7, 0x2e, 0x98, 0x97, 0x2f, 0x8a, 0xbf, 0x96, 0xe6, ++ 0x59, 0xcb, 0x5c, 0xa8, 0x2f, 0x4f, 0x30, 0x3f, 0xea, 0x4b, 0x39, 0xaf, ++ 0x21, 0x33, 0xdb, 0xbd, 0x98, 0x7f, 0x53, 0x23, 0xf4, 0x28, 0xe0, 0xc5, ++ 0x86, 0x7c, 0x90, 0xfa, 0xcf, 0x3e, 0xb6, 0xdc, 0x67, 0xd2, 0xcf, 0x82, ++ 0x7e, 0x43, 0x19, 0x97, 0x37, 0xe9, 0x9f, 0x0c, 0xc5, 0x0d, 0x12, 0x28, ++ 0xbf, 0xe3, 0x29, 0x10, 0x7a, 0x8b, 0x51, 0x9c, 0xe0, 0xe4, 0xab, 0xfb, ++ 0x7e, 0xca, 0xef, 0xed, 0xe0, 0xf4, 0xaa, 0x99, 0xc9, 0xe9, 0x2b, 0xe5, ++ 0xf5, 0x2b, 0x4f, 0x30, 0xc5, 0x8b, 0xf6, 0xe9, 0x5d, 0x0f, 0x4d, 0xe4, ++ 0x97, 0xe1, 0x46, 0xe8, 0x9e, 0xe6, 0xca, 0x0d, 0x7c, 0x1c, 0xa8, 0xd7, ++ 0xcc, 0x48, 0x6e, 0xdb, 0xb2, 0x67, 0x62, 0xfe, 0x25, 0xf2, 0xd3, 0x98, ++ 0x9e, 0x74, 0x4b, 0x2d, 0x6d, 0x76, 0x51, 0x7b, 0xc1, 0xff, 0x67, 0x5f, ++ 0x19, 0x1e, 0x46, 0x3e, 0x4c, 0xbb, 0xbd, 0xab, 0x18, 0xdf, 0x03, 0x3f, ++ 0x10, 0x3c, 0x2d, 0xcd, 0x9e, 0x30, 0xfa, 0xcb, 0x64, 0x2f, 0x63, 0xfb, ++ 0x7d, 0x0a, 0x5f, 0xbf, 0x58, 0x90, 0xf0, 0x32, 0x77, 0xa6, 0xe1, 0x37, ++ 0xf3, 0x89, 0x84, 0xaf, 0x9b, 0xee, 0x0c, 0xe8, 0x3e, 0x3c, 0xfa, 0x7e, ++ 0xc8, 0x4c, 0xde, 0x6f, 0x4d, 0x2b, 0xf4, 0xcb, 0xfb, 0x21, 0xf9, 0xa9, ++ 0xbc, 0x9f, 0xf1, 0xfb, 0xa9, 0x05, 0x7d, 0x80, 0xd5, 0x42, 0x8e, 0x91, ++ 0x51, 0xbd, 0x03, 0xe5, 0x88, 0x23, 0x25, 0x8a, 0x47, 0x89, 0x3f, 0xd9, ++ 0xbe, 0xfa, 0x7e, 0xfe, 0xdb, 0x3d, 0x18, 0x2f, 0x40, 0x3f, 0xaf, 0x86, ++ 0xb5, 0x53, 0xdc, 0xb4, 0x52, 0x2d, 0xed, 0x8f, 0xfe, 0x1a, 0xcb, 0x70, ++ 0xd0, 0x39, 0x5b, 0xf0, 0x7f, 0x49, 0xff, 0x1c, 0x76, 0x31, 0xcd, 0x05, ++ 0xed, 0x5f, 0x87, 0x27, 0xae, 0xef, 0x93, 0xd5, 0x45, 0x74, 0x1e, 0x6a, ++ 0xf2, 0x20, 0x85, 0xe4, 0x1c, 0x24, 0x49, 0xc6, 0xcb, 0xe8, 0xf7, 0xc6, ++ 0x6e, 0xbd, 0x21, 0x91, 0xe7, 0xbd, 0x7d, 0xf5, 0xdd, 0xc1, 0x38, 0x9f, ++ 0xb4, 0x44, 0xce, 0x77, 0xd0, 0x8f, 0x53, 0xf4, 0xe3, 0x24, 0x3b, 0x55, ++ 0xe8, 0xc3, 0x5f, 0x67, 0x83, 0x3e, 0x34, 0xf9, 0xa5, 0x87, 0x15, 0x85, ++ 0xfa, 0x39, 0xfc, 0xad, 0x6b, 0xb6, 0x2e, 0x57, 0xa2, 0xf3, 0xc4, 0xfe, ++ 0xd0, 0x6e, 0x38, 0xac, 0x4c, 0xeb, 0x4f, 0xf6, 0xac, 0x88, 0x6b, 0x00, ++ 0xde, 0x2c, 0xf9, 0x78, 0x51, 0xfe, 0x0d, 0x09, 0xb8, 0xda, 0xb3, 0xf1, ++ 0xbb, 0xd9, 0x4f, 0x42, 0xbf, 0xa6, 0xdb, 0xcf, 0x62, 0x49, 0x0f, 0xdf, ++ 0x08, 0x7e, 0xd5, 0xd8, 0x29, 0xcd, 0x11, 0xbc, 0x52, 0xbb, 0x3e, 0x94, ++ 0x7c, 0xe3, 0xf7, 0x60, 0xdc, 0xc9, 0xe0, 0x67, 0xb9, 0x60, 0xfe, 0xfd, ++ 0x91, 0x8f, 0xd1, 0x2f, 0xc8, 0x09, 0xa9, 0x5e, 0x84, 0x6b, 0x88, 0x42, ++ 0xf7, 0x47, 0x1f, 0x49, 0x08, 0xe6, 0xf3, 0x7b, 0x88, 0xf9, 0x38, 0xe9, ++ 0x22, 0xee, 0x95, 0x2e, 0xf2, 0xb4, 0xd1, 0x9e, 0xc7, 0xe7, 0x36, 0x2f, ++ 0x5f, 0x2f, 0x86, 0x27, 0xf1, 0xf5, 0xe5, 0xa1, 0x24, 0x5e, 0x4e, 0xf7, ++ 0xc6, 0x8f, 0x93, 0x3d, 0x21, 0xbe, 0xd7, 0x88, 0x7b, 0xbb, 0x57, 0x17, ++ 0xc5, 0xcf, 0x07, 0x1c, 0xe7, 0xb5, 0xc6, 0x39, 0x6f, 0x15, 0xfb, 0x3e, ++ 0xe0, 0x6f, 0x8d, 0xf3, 0xa6, 0xf1, 0xfb, 0xe0, 0x79, 0x9e, 0x32, 0xdf, ++ 0x27, 0x02, 0xbb, 0x96, 0xf0, 0x5b, 0xfc, 0xf0, 0x4c, 0xda, 0xf7, 0xbc, ++ 0xd0, 0x76, 0x47, 0x12, 0xbf, 0x9f, 0x82, 0xcb, 0xff, 0xc7, 0x4a, 0xe0, ++ 0xdf, 0xee, 0x52, 0xf0, 0x59, 0x4a, 0xf7, 0x03, 0x86, 0x7e, 0xab, 0x52, ++ 0xbe, 0xff, 0x47, 0x46, 0xc0, 0x8b, 0xf9, 0x61, 0x55, 0x09, 0xf1, 0xf3, ++ 0xcf, 0xef, 0x15, 0x70, 0x54, 0x89, 0xf9, 0x9f, 0xae, 0xe3, 0xf7, 0x49, ++ 0xcc, 0xc3, 0xfd, 0x48, 0xd0, 0x17, 0xb7, 0x0a, 0xff, 0x6c, 0x41, 0xd3, ++ 0x6d, 0x25, 0x48, 0xef, 0x05, 0xe0, 0xbf, 0xe3, 0x7e, 0xa4, 0xcc, 0x7b, ++ 0x90, 0xf4, 0x2d, 0xdb, 0xa4, 0x5a, 0xf6, 0x23, 0xe6, 0xe1, 0x7e, 0x64, ++ 0x9f, 0xbf, 0xc6, 0x7f, 0xf0, 0xf7, 0xe2, 0x3f, 0x8c, 0xb6, 0xf8, 0x0f, ++ 0x72, 0xdc, 0x58, 0x3f, 0xe2, 0x64, 0x5d, 0xa6, 0x65, 0xdf, 0x64, 0x76, ++ 0xd3, 0x20, 0x71, 0x8f, 0x07, 0xaf, 0x3f, 0x87, 0xf9, 0x09, 0xee, 0x39, ++ 0x2b, 0xfb, 0x59, 0xf6, 0x4f, 0xd9, 0xca, 0xb4, 0x2b, 0xbb, 0xe7, 0x14, ++ 0xfc, 0x86, 0x50, 0x5c, 0xf8, 0x74, 0xd2, 0xaf, 0xf2, 0xfd, 0xc9, 0x3a, ++ 0x27, 0x0b, 0x99, 0xe1, 0xf8, 0x64, 0x30, 0xe5, 0x8d, 0x8c, 0xf3, 0x06, ++ 0x1f, 0xf0, 0x5a, 0xe0, 0x48, 0x64, 0x21, 0x33, 0x1c, 0x6c, 0x02, 0xff, ++ 0x5d, 0x2f, 0x17, 0x8f, 0x5b, 0x03, 0xdd, 0x43, 0x66, 0x7b, 0x3a, 0x16, ++ 0xae, 0x55, 0xde, 0xbf, 0xd6, 0x4f, 0xcb, 0xed, 0x05, 0xcf, 0x79, 0xff, ++ 0x25, 0x7e, 0x5a, 0xe1, 0x04, 0xae, 0xcf, 0xf0, 0x52, 0x22, 0xcc, 0x81, ++ 0x19, 0x3b, 0xc9, 0x6a, 0x37, 0x6f, 0xf6, 0xf2, 0x75, 0x72, 0xb3, 0x37, ++ 0xd1, 0x62, 0x37, 0xcf, 0x9d, 0x69, 0xad, 0xb7, 0x45, 0xd4, 0xdb, 0x22, ++ 0xea, 0x5d, 0xce, 0xff, 0x37, 0xdb, 0xcb, 0xca, 0x20, 0xd4, 0x1b, 0xbc, ++ 0x3f, 0xf9, 0x7b, 0x3c, 0x39, 0x67, 0xde, 0xa2, 0xbc, 0xd3, 0xf7, 0xbc, ++ 0xdc, 0x0e, 0x38, 0x9e, 0x14, 0xd8, 0x81, 0xf2, 0xb8, 0x56, 0xe4, 0xe9, ++ 0x6f, 0xf9, 0xcb, 0xa1, 0xcc, 0x39, 0x68, 0x5f, 0xfc, 0xab, 0x9d, 0xf2, ++ 0x04, 0x8a, 0x36, 0x2f, 0x59, 0x8e, 0x79, 0xd4, 0xee, 0x66, 0xc5, 0xa0, ++ 0x73, 0x4a, 0xad, 0x56, 0x3e, 0xfa, 0xc7, 0xa5, 0xcd, 0x03, 0xe7, 0x02, ++ 0x3e, 0x5e, 0x12, 0x74, 0xaa, 0xf4, 0xf3, 0x79, 0x54, 0xfa, 0x23, 0xfa, ++ 0x60, 0x37, 0xe6, 0x75, 0xf3, 0xf1, 0xfb, 0x37, 0x1f, 0x50, 0x34, 0x93, ++ 0x9e, 0xe8, 0x5f, 0xc6, 0xeb, 0xed, 0xf3, 0xda, 0x2d, 0x71, 0xf7, 0x03, ++ 0x5e, 0x7e, 0x8f, 0xc4, 0x2f, 0xbd, 0x32, 0x3e, 0x18, 0x3e, 0x70, 0x53, ++ 0x2a, 0xd6, 0x0f, 0x68, 0xb8, 0xae, 0xf4, 0xc5, 0xdf, 0xc1, 0x01, 0x78, ++ 0xfa, 0xd6, 0x32, 0x3a, 0x07, 0xd5, 0x77, 0x34, 0xb7, 0xc7, 0xfe, 0x71, ++ 0xf4, 0x16, 0x05, 0x7f, 0x97, 0x4b, 0xce, 0x73, 0xa5, 0x6d, 0x5a, 0xbe, ++ 0x01, 0xed, 0x56, 0xa6, 0x27, 0xfa, 0x51, 0x4f, 0x67, 0x1b, 0xc1, 0xd7, ++ 0x71, 0x9e, 0x95, 0xef, 0x45, 0x22, 0x18, 0xbe, 0x19, 0xfb, 0x5e, 0x9b, ++ 0x86, 0xfe, 0x92, 0xdf, 0x08, 0x1c, 0x45, 0x7e, 0x95, 0xf3, 0xf2, 0xa9, ++ 0x46, 0x5f, 0x5c, 0x6f, 0x12, 0xdf, 0xe3, 0xf0, 0x35, 0x75, 0xc7, 0x21, ++ 0xb8, 0x9e, 0x66, 0x6c, 0x8d, 0xf0, 0x5f, 0xb6, 0x72, 0x3b, 0x56, 0x65, ++ 0x47, 0x19, 0xb7, 0x73, 0x69, 0xbf, 0x36, 0x7d, 0xd9, 0x50, 0x5a, 0x2f, ++ 0xe4, 0x7c, 0xd2, 0x53, 0x84, 0xbe, 0x4d, 0x67, 0xc1, 0xdd, 0x64, 0x6f, ++ 0xb3, 0x95, 0xb4, 0xde, 0x39, 0xf9, 0xfa, 0x99, 0xbe, 0x8c, 0xff, 0x8e, ++ 0x9e, 0xa4, 0x67, 0x34, 0x7e, 0x32, 0x6c, 0x24, 0xc6, 0x4f, 0x06, 0xad, ++ 0x8d, 0x68, 0xb3, 0xa1, 0xdd, 0xab, 0x9b, 0x6c, 0x71, 0xef, 0xdd, 0x38, ++ 0x25, 0xf0, 0x0e, 0xf3, 0xf8, 0x00, 0xe7, 0x17, 0x4b, 0x9f, 0x5e, 0xd7, ++ 0x1d, 0x51, 0xcf, 0xde, 0x4b, 0x5c, 0x4a, 0xf2, 0x7b, 0xe2, 0x94, 0xf8, ++ 0xfe, 0x1e, 0x63, 0x8f, 0xd0, 0xf7, 0xa2, 0xcd, 0xa9, 0xf7, 0x90, 0x5c, ++ 0x36, 0xe8, 0x74, 0x4f, 0xa2, 0xc4, 0xbf, 0xdf, 0x28, 0xfd, 0x23, 0xc2, ++ 0xd3, 0xb7, 0x79, 0x8b, 0x82, 0xb8, 0x39, 0x29, 0xf2, 0x19, 0x4e, 0xae, ++ 0xfe, 0xa9, 0x82, 0xf6, 0xd6, 0x77, 0x17, 0x32, 0x43, 0x8d, 0xc3, 0x4f, ++ 0xdd, 0xf2, 0xba, 0x74, 0xf7, 0xc0, 0xb9, 0x26, 0x7d, 0x03, 0xfd, 0x13, ++ 0x3d, 0xb6, 0xc4, 0xe4, 0xa7, 0x4b, 0xff, 0xc4, 0x9d, 0xc4, 0xf5, 0xf8, ++ 0x3c, 0xa3, 0x54, 0x4d, 0x4a, 0xa3, 0x7c, 0x61, 0x8a, 0xe3, 0x2d, 0xdc, ++ 0xce, 0x7f, 0x8f, 0xa3, 0x57, 0x7c, 0x5c, 0x21, 0xbe, 0x94, 0x32, 0xee, ++ 0xc7, 0x54, 0xce, 0xe0, 0xbf, 0x47, 0x5a, 0xb4, 0x59, 0x23, 0x7a, 0x57, ++ 0x34, 0xf0, 0xdf, 0x23, 0xac, 0xdc, 0xb9, 0x8b, 0xce, 0xe3, 0xb1, 0x87, ++ 0x98, 0x1f, 0xe5, 0xbd, 0xb2, 0x79, 0x97, 0x32, 0x17, 0xc6, 0xad, 0xd8, ++ 0xb9, 0x4b, 0x99, 0x67, 0xc2, 0x5f, 0xbf, 0xca, 0x30, 0xe5, 0x75, 0x5f, ++ 0xe5, 0x91, 0x71, 0xea, 0x08, 0xdd, 0x3b, 0x16, 0xcb, 0xd7, 0x18, 0xdf, ++ 0xc7, 0xf5, 0xfd, 0x88, 0x8b, 0xcb, 0x7b, 0x47, 0x91, 0x3b, 0x84, 0x71, ++ 0xeb, 0x0e, 0x7b, 0xb0, 0x12, 0xeb, 0x75, 0x64, 0x25, 0xfa, 0x71, 0x7f, ++ 0x54, 0xe2, 0xfb, 0xf5, 0x5d, 0x37, 0xd2, 0xfd, 0x07, 0x9e, 0xdd, 0x8e, ++ 0x08, 0x3e, 0x57, 0xda, 0xb6, 0x66, 0x3a, 0xa1, 0xde, 0xca, 0xab, 0x75, ++ 0x3f, 0xf2, 0x91, 0xdf, 0x08, 0x0e, 0x45, 0xbc, 0xa4, 0x68, 0xa5, 0x2d, ++ 0xd8, 0x3e, 0x39, 0xd5, 0xe3, 0xc7, 0xb8, 0xb7, 0xcf, 0xc1, 0x46, 0xd2, ++ 0x3a, 0x77, 0x85, 0x78, 0x18, 0x1b, 0xc3, 0x0f, 0x63, 0x1f, 0xe2, 0x72, ++ 0x72, 0x4f, 0x92, 0x57, 0xda, 0x59, 0x94, 0x6f, 0x35, 0x31, 0xc9, 0x23, ++ 0xed, 0x0e, 0xd2, 0x4f, 0x47, 0xec, 0x7c, 0x1e, 0xbb, 0x19, 0x87, 0x77, ++ 0x9b, 0x37, 0x30, 0x16, 0xe1, 0x61, 0x47, 0xf9, 0xef, 0x29, 0xf4, 0xad, ++ 0x8c, 0x28, 0x98, 0xa7, 0x12, 0x3b, 0x6e, 0x94, 0x9f, 0x02, 0xdf, 0x4a, ++ 0xfa, 0x06, 0xfc, 0x0d, 0xf6, 0x92, 0x8e, 0x7a, 0xbd, 0x42, 0xe8, 0x99, ++ 0xa2, 0xcd, 0xdb, 0x95, 0x0f, 0x4d, 0x70, 0x4f, 0x45, 0x63, 0x04, 0xf9, ++ 0x73, 0xe7, 0x16, 0x05, 0xe3, 0x2a, 0xf0, 0x9d, 0xf4, 0x0c, 0xd4, 0x67, ++ 0x98, 0x0f, 0xd5, 0x77, 0x27, 0x8f, 0x27, 0x55, 0xc0, 0xf7, 0x79, 0x26, ++ 0xbd, 0x22, 0xe7, 0x11, 0x47, 0xbf, 0xdc, 0x86, 0xf0, 0xb9, 0xdf, 0x6b, ++ 0x7b, 0x8d, 0xeb, 0x97, 0x08, 0x8f, 0x23, 0x0b, 0x78, 0x63, 0xe9, 0x79, ++ 0x7f, 0x12, 0xb7, 0xdb, 0x4a, 0x60, 0x59, 0xa5, 0xf7, 0x7a, 0x68, 0x28, ++ 0xfa, 0x9b, 0x47, 0x72, 0x13, 0xa8, 0x3f, 0x29, 0xef, 0xb1, 0xf2, 0x79, ++ 0xbf, 0xe0, 0xf3, 0xbe, 0x9b, 0xb6, 0x2b, 0x36, 0x37, 0xc5, 0xdb, 0xc9, ++ 0xfe, 0x92, 0xf0, 0xc9, 0x7a, 0xc7, 0x93, 0x26, 0xce, 0x49, 0x1a, 0x83, ++ 0x78, 0x68, 0x23, 0x3c, 0x54, 0x6d, 0xd2, 0x68, 0x3e, 0x93, 0xf5, 0xd2, ++ 0xc1, 0x8b, 0x4c, 0xf2, 0xb0, 0x48, 0xf4, 0x77, 0xf0, 0xae, 0xf7, 0xe9, ++ 0x5e, 0xa0, 0x0d, 0x3f, 0x3f, 0x46, 0xfc, 0x58, 0xd5, 0xa4, 0x70, 0xbb, ++ 0xbf, 0xe9, 0x98, 0x7e, 0x07, 0xae, 0x2b, 0xa1, 0xe7, 0x54, 0xdc, 0x1f, ++ 0xb9, 0x99, 0x2f, 0xe5, 0xec, 0x71, 0x71, 0x5f, 0xd6, 0xcd, 0x2d, 0x5c, ++ 0xff, 0x56, 0xb5, 0xec, 0xd2, 0xf0, 0x7e, 0x49, 0xc9, 0xa7, 0x39, 0x67, ++ 0x0e, 0xd2, 0x3d, 0x5b, 0x55, 0xcd, 0x0e, 0x86, 0xfb, 0xa5, 0xc0, 0x7f, ++ 0xdf, 0x43, 0xfc, 0xc4, 0xf2, 0xa9, 0xc4, 0x8f, 0xd4, 0xaf, 0xbd, 0xd1, ++ 0x13, 0xf4, 0x10, 0x3f, 0xa7, 0x10, 0xd2, 0x45, 0x9c, 0x3a, 0x98, 0x33, ++ 0xdd, 0x13, 0xd5, 0xcf, 0xdb, 0xbc, 0x62, 0x7f, 0xd4, 0xcd, 0xdf, 0x6f, ++ 0x48, 0xe2, 0xe5, 0x28, 0xff, 0x04, 0x57, 0x25, 0x59, 0xf4, 0xab, 0x8b, ++ 0xe4, 0x22, 0xe7, 0xcc, 0xc8, 0x83, 0x98, 0x0f, 0x5a, 0xe5, 0x57, 0xe8, ++ 0x5c, 0x65, 0x6a, 0xb1, 0xf8, 0x7d, 0x32, 0x13, 0x5c, 0xe6, 0xf3, 0x31, ++ 0xb1, 0xfa, 0x11, 0xe3, 0xe1, 0x3c, 0x7e, 0xd2, 0x9e, 0x3d, 0xdd, 0x74, ++ 0x3e, 0xae, 0x5b, 0xcf, 0x8b, 0xf6, 0x4f, 0x20, 0xbd, 0xf9, 0xfb, 0x08, ++ 0x7f, 0xcf, 0x72, 0x71, 0xbd, 0x96, 0xf0, 0xc7, 0xd2, 0xef, 0x90, 0xb0, ++ 0xc7, 0xe3, 0xf0, 0x59, 0x38, 0x29, 0xce, 0x3a, 0x26, 0xd7, 0xf5, 0x9c, ++ 0xa7, 0x77, 0x6b, 0x78, 0x8f, 0x92, 0xe4, 0x9f, 0x9b, 0x91, 0xee, 0x26, ++ 0xfe, 0xf9, 0x59, 0x12, 0xbf, 0x8f, 0xf7, 0x67, 0x49, 0x1a, 0xf5, 0xff, ++ 0x78, 0x11, 0xdf, 0xa7, 0x7a, 0xdc, 0xce, 0xd7, 0xaf, 0xc7, 0xeb, 0x9d, ++ 0x94, 0xbf, 0xf9, 0xfa, 0xdd, 0x3c, 0x9f, 0xcc, 0x73, 0x8f, 0x1e, 0xc1, ++ 0xe7, 0x61, 0xdb, 0xec, 0x4a, 0xfc, 0x7e, 0xb8, 0x2f, 0x87, 0x63, 0xa5, ++ 0x6d, 0x19, 0x9d, 0xf7, 0x03, 0xb9, 0x6c, 0x4e, 0x22, 0xfe, 0xf1, 0x32, ++ 0xae, 0x1f, 0xb9, 0x3e, 0xdc, 0xf0, 0x12, 0xd7, 0x67, 0x95, 0x21, 0x37, ++ 0xdd, 0x77, 0x5a, 0x19, 0xbc, 0x7d, 0x2e, 0xe5, 0xd9, 0xa6, 0xba, 0xfc, ++ 0x74, 0x3f, 0x68, 0xf0, 0x35, 0xfd, 0x0e, 0x4f, 0x4f, 0xbe, 0xf2, 0xed, ++ 0x3e, 0x40, 0xbf, 0x8b, 0x7c, 0x73, 0x33, 0x97, 0x3f, 0x49, 0x07, 0xd0, ++ 0xa7, 0xc4, 0x5f, 0x52, 0x1e, 0x24, 0x5e, 0xa3, 0xf8, 0xe4, 0x78, 0x97, ++ 0xf2, 0x24, 0xe9, 0xb1, 0x4d, 0xee, 0x0b, 0x00, 0xbf, 0x70, 0xfb, 0x88, ++ 0xfb, 0x23, 0xf9, 0x4c, 0xa5, 0xfd, 0x9f, 0x32, 0x67, 0xe0, 0x08, 0x9e, ++ 0xcb, 0x2c, 0x13, 0xfb, 0xa5, 0xf9, 0xe2, 0x77, 0x5f, 0xe4, 0x7e, 0xe9, ++ 0x6c, 0x41, 0x97, 0x02, 0x5b, 0xe9, 0xaf, 0x71, 0x9e, 0x3d, 0xf6, 0x4b, ++ 0xaf, 0xd0, 0xae, 0xae, 0x58, 0xfa, 0xab, 0x61, 0x18, 0x0f, 0x29, 0xcf, ++ 0x3c, 0x4a, 0x4f, 0x29, 0xb7, 0xe0, 0xf7, 0x59, 0xe4, 0xfb, 0x7d, 0x41, ++ 0xf7, 0xc3, 0xe2, 0xf9, 0xb1, 0xe0, 0x9b, 0x8a, 0xd1, 0xcd, 0x24, 0x97, ++ 0x15, 0x1f, 0xd5, 0x92, 0x3c, 0xbb, 0xa7, 0x70, 0xbd, 0xe6, 0x7e, 0xcf, ++ 0xaa, 0x8f, 0x19, 0x5b, 0x27, 0xe6, 0xbb, 0x96, 0xda, 0x4f, 0x4e, 0x6c, ++ 0x2e, 0xc1, 0xfd, 0xc6, 0xc9, 0x3f, 0x56, 0x0c, 0xf4, 0x87, 0x7b, 0x83, ++ 0x73, 0x01, 0x9e, 0x53, 0x43, 0xff, 0x68, 0xd3, 0x21, 0xef, 0x2c, 0xc4, ++ 0xaf, 0xf8, 0x7d, 0x29, 0x79, 0x9e, 0xe7, 0x0b, 0xa1, 0x27, 0x3a, 0x76, ++ 0xa8, 0xe2, 0xf7, 0x36, 0x6b, 0xf5, 0x4b, 0xd9, 0xdf, 0x97, 0xeb, 0x8f, ++ 0x45, 0x8e, 0x2b, 0x74, 0xef, 0x89, 0xf0, 0xa9, 0x3a, 0x76, 0x16, 0x8f, ++ 0xff, 0x18, 0xfd, 0xba, 0x1d, 0x49, 0xf4, 0xfb, 0x27, 0x9f, 0xed, 0xbc, ++ 0xed, 0xfb, 0x1f, 0xa7, 0xe2, 0xef, 0x8b, 0xdc, 0xe0, 0x47, 0x3b, 0x21, ++ 0x75, 0x79, 0x29, 0xf1, 0x4f, 0x57, 0x9a, 0xcb, 0xbf, 0x95, 0xc7, 0x3d, ++ 0xa7, 0x60, 0x5c, 0xa7, 0xbe, 0xf9, 0x90, 0x17, 0xcf, 0xff, 0xfc, 0x6f, ++ 0x59, 0x68, 0xc8, 0xa8, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xd5, 0x7d, ++ 0x09, 0x78, 0x54, 0xd5, 0xd9, 0xf0, 0xb9, 0x73, 0x67, 0x0b, 0x99, 0x49, ++ 0x66, 0x26, 0x7b, 0xc8, 0x32, 0x09, 0x10, 0x50, 0x49, 0x98, 0x84, 0x84, ++ 0x7d, 0x99, 0x24, 0x84, 0x45, 0x16, 0x27, 0x08, 0x05, 0x64, 0x1b, 0xf6, ++ 0x00, 0xd9, 0x58, 0xda, 0x62, 0xa5, 0x7f, 0x06, 0x83, 0x88, 0x88, 0x6d, ++ 0x68, 0xad, 0x22, 0x5a, 0xbf, 0x01, 0xc1, 0x62, 0xb5, 0x35, 0x60, 0xa4, ++ 0x41, 0x02, 0x0e, 0xb2, 0x08, 0x55, 0x3f, 0x47, 0x0a, 0x16, 0x5b, 0xb4, ++ 0x23, 0x22, 0xb2, 0x84, 0x64, 0x8a, 0xad, 0xa5, 0x5f, 0xf9, 0x3e, 0xfe, ++ 0xf3, 0xbe, 0xe7, 0x9c, 0xcc, 0xdc, 0x9b, 0x09, 0xa8, 0x5f, 0xdb, 0xe7, ++ 0xff, 0xc3, 0xe3, 0x73, 0x3c, 0xf7, 0xdc, 0x7b, 0x96, 0xf7, 0xbc, 0xfb, ++ 0xfb, 0x9e, 0x33, 0x97, 0x5f, 0xee, 0x57, 0x60, 0xb0, 0x13, 0x62, 0xb6, ++ 0x68, 0x08, 0x49, 0x20, 0xe4, 0xca, 0x6b, 0xf2, 0x1a, 0xaf, 0x89, 0x90, ++ 0x87, 0x7f, 0xf1, 0xea, 0x88, 0xa1, 0x85, 0x84, 0x2c, 0xf7, 0x4a, 0x71, ++ 0x06, 0x42, 0x48, 0xeb, 0xee, 0xff, 0xf8, 0x9f, 0xd4, 0x78, 0x42, 0x2a, ++ 0x76, 0xd6, 0x58, 0x24, 0x5a, 0xaf, 0x7f, 0xf9, 0x4d, 0x7d, 0x80, 0xbe, ++ 0xa7, 0xf1, 0x6e, 0x67, 0xcf, 0x77, 0xc7, 0x5a, 0xe0, 0xbd, 0xcb, 0x2f, ++ 0x6c, 0x19, 0x41, 0xfa, 0xd2, 0xf6, 0xc6, 0x7a, 0x6c, 0xbf, 0xf2, 0xc2, ++ 0x76, 0xac, 0xbf, 0xf5, 0x8b, 0x57, 0x0f, 0xfd, 0x17, 0x7d, 0xaf, 0xd2, ++ 0x15, 0xe3, 0x80, 0xf7, 0xae, 0xbc, 0x76, 0x58, 0x0f, 0xcf, 0x2b, 0xdd, ++ 0x5a, 0x67, 0x23, 0x2d, 0x89, 0xfb, 0xa8, 0x7e, 0xaa, 0x99, 0x96, 0x9e, ++ 0x97, 0x64, 0x92, 0x48, 0xc8, 0x78, 0xc2, 0xfe, 0x9e, 0xda, 0x73, 0x58, ++ 0x6f, 0xcf, 0xa5, 0xf5, 0x46, 0x3a, 0x2a, 0xfd, 0x9e, 0x4c, 0xd7, 0x7b, ++ 0x7b, 0x65, 0xd1, 0xef, 0x1a, 0xf7, 0x68, 0x17, 0x98, 0xe0, 0x0d, 0x2f, ++ 0x21, 0x45, 0x74, 0xdc, 0x5f, 0xcc, 0x1d, 0xec, 0x86, 0x7a, 0x33, 0x5d, ++ 0x44, 0x4a, 0xe8, 0xf9, 0x46, 0x3d, 0xf1, 0x18, 0x6d, 0xb4, 0xec, 0x46, ++ 0x48, 0x14, 0x2d, 0xaf, 0x16, 0x9b, 0x3c, 0x52, 0x2c, 0x5d, 0x57, 0x89, ++ 0x69, 0x23, 0x94, 0x57, 0x7f, 0x15, 0x35, 0x1d, 0xd6, 0x5b, 0xad, 0x0f, ++ 0xe4, 0x58, 0x61, 0x3e, 0x7d, 0x89, 0x13, 0xea, 0xdd, 0x01, 0x1e, 0x45, ++ 0x30, 0xce, 0x0a, 0x5d, 0xb5, 0x09, 0xbf, 0xc7, 0x7e, 0x3e, 0xd4, 0x11, ++ 0x02, 0x65, 0x2e, 0xf1, 0x90, 0x8b, 0x7d, 0xe8, 0xfa, 0x09, 0xd9, 0x79, ++ 0xab, 0x3f, 0x8c, 0xf7, 0x6b, 0x84, 0x1f, 0x7d, 0x6f, 0x50, 0x54, 0x01, ++ 0x21, 0xd3, 0x66, 0x7d, 0x2a, 0xc1, 0x7c, 0xa2, 0xfb, 0xd6, 0xea, 0x96, ++ 0xe3, 0x3c, 0x5f, 0x66, 0xed, 0x74, 0xd5, 0xe1, 0xed, 0x03, 0x56, 0xd3, ++ 0xf1, 0xe8, 0xb8, 0xb7, 0xe0, 0x6f, 0x64, 0xa8, 0x2c, 0xb2, 0x98, 0xf0, ++ 0x7d, 0x0a, 0x10, 0x2c, 0x53, 0x9b, 0xca, 0xd3, 0xec, 0xb0, 0xfe, 0x78, ++ 0x83, 0x03, 0xd6, 0x2f, 0xd6, 0x97, 0x5a, 0xe1, 0xae, 0x37, 0xd3, 0xe7, ++ 0xf7, 0xae, 0x76, 0x3b, 0x64, 0xba, 0x8f, 0x6f, 0x5c, 0x3a, 0x35, 0xba, ++ 0x3b, 0xad, 0xff, 0xa2, 0x8f, 0xd4, 0x5f, 0x86, 0xd7, 0x65, 0x69, 0xae, ++ 0x8b, 0xf6, 0x5f, 0xed, 0x31, 0xe1, 0x38, 0x55, 0x6b, 0x4a, 0xc8, 0x67, ++ 0x74, 0xbe, 0x63, 0x60, 0x17, 0xe9, 0xf7, 0x89, 0x16, 0x12, 0x3f, 0x84, ++ 0xae, 0xa7, 0x4c, 0x4b, 0xe2, 0x4d, 0x50, 0x12, 0x72, 0x5a, 0x57, 0x00, ++ 0xfd, 0xef, 0xc2, 0x76, 0xbb, 0x81, 0x38, 0x09, 0xc5, 0x03, 0xfb, 0x9b, ++ 0xd3, 0x76, 0xad, 0xa3, 0x9f, 0x3c, 0xa5, 0x73, 0xa7, 0x14, 0x41, 0x3f, ++ 0x1b, 0xfd, 0x7a, 0x3b, 0x94, 0x3b, 0xd9, 0xfc, 0xe9, 0xf7, 0x16, 0x53, ++ 0x01, 0xf6, 0x67, 0x19, 0x02, 0xdf, 0x1b, 0xc9, 0x4a, 0xf8, 0xae, 0x7d, ++ 0xdd, 0x84, 0xf8, 0x4d, 0x12, 0xf6, 0xeb, 0xd7, 0xd9, 0x42, 0xf3, 0x26, ++ 0x24, 0x98, 0x31, 0x35, 0x97, 0xf5, 0x57, 0x08, 0x70, 0x1a, 0xeb, 0x99, ++ 0x0e, 0xef, 0x13, 0xbb, 0x1e, 0xd7, 0x77, 0x05, 0x5e, 0xc1, 0x7d, 0xf4, ++ 0xe4, 0xcd, 0xce, 0x85, 0xf2, 0x09, 0x36, 0x5f, 0x0d, 0x71, 0x03, 0xbe, ++ 0x24, 0xea, 0x69, 0x89, 0x70, 0x75, 0x67, 0x95, 0x53, 0xbc, 0x59, 0x64, ++ 0x29, 0x76, 0x5b, 0x8a, 0x42, 0x65, 0x62, 0x37, 0xd6, 0xae, 0x86, 0xeb, ++ 0x4e, 0x68, 0xa7, 0xf0, 0xbc, 0x60, 0x71, 0x62, 0x49, 0x76, 0xc7, 0x11, ++ 0x32, 0xb8, 0xf3, 0x7b, 0xa2, 0x14, 0xf0, 0x7f, 0x6b, 0x5a, 0x9b, 0x3e, ++ 0x40, 0xc7, 0x7d, 0xf2, 0xc0, 0xa7, 0x88, 0xb7, 0xd5, 0x80, 0xb7, 0x30, ++ 0xbe, 0xfb, 0x82, 0x1e, 0xd6, 0x21, 0xf0, 0x76, 0x21, 0x7c, 0x42, 0xf7, ++ 0xe1, 0xa9, 0xfd, 0x9f, 0x22, 0xde, 0x2e, 0x6c, 0x96, 0x10, 0x3e, 0xd5, ++ 0xcd, 0xc5, 0xfa, 0x05, 0xb4, 0xbc, 0x5a, 0xe7, 0x24, 0x9f, 0x69, 0x69, ++ 0x9d, 0xe3, 0xdf, 0x53, 0x52, 0x60, 0x31, 0xe0, 0xb5, 0x67, 0x7f, 0x94, ++ 0x65, 0x17, 0x85, 0x53, 0x9b, 0xc0, 0xcf, 0x86, 0x4f, 0x2f, 0xca, 0xf4, ++ 0x79, 0x76, 0x73, 0x8a, 0x5d, 0x82, 0xe7, 0xfb, 0x19, 0x9e, 0x1e, 0xd3, ++ 0x68, 0x3c, 0x00, 0xa7, 0x63, 0x3b, 0xee, 0xd9, 0x5e, 0x2f, 0x85, 0xcf, ++ 0x73, 0x1d, 0xc2, 0x47, 0xaa, 0x20, 0x48, 0x27, 0xd5, 0xb5, 0xc4, 0x6b, ++ 0xa0, 0xed, 0xc5, 0x3f, 0x5f, 0x7d, 0x6a, 0x1c, 0xad, 0x57, 0x55, 0x10, ++ 0x07, 0xd0, 0x79, 0xb5, 0x0a, 0x8f, 0xb2, 0x9e, 0x3f, 0xbf, 0x01, 0xf0, ++ 0xc5, 0x5a, 0x49, 0x0a, 0xa3, 0xec, 0xb0, 0xce, 0x4f, 0x46, 0x77, 0xa7, ++ 0xfd, 0x57, 0x57, 0x92, 0x22, 0xa0, 0xd3, 0xd4, 0x51, 0xce, 0xfd, 0x50, ++ 0x27, 0xcd, 0x12, 0xe9, 0x05, 0xf5, 0x0a, 0xd7, 0x42, 0x18, 0xff, 0xde, ++ 0xf8, 0xa5, 0x0e, 0x99, 0xf6, 0x6f, 0x1d, 0xe5, 0x6a, 0x82, 0xf1, 0xee, ++ 0x8d, 0x1f, 0xee, 0x90, 0x69, 0x7f, 0x4f, 0xa5, 0x37, 0x6e, 0x30, 0xd2, ++ 0x76, 0x4f, 0x19, 0xb1, 0xec, 0x02, 0x38, 0xe8, 0x1a, 0x4a, 0xb4, 0xb4, ++ 0xfe, 0x54, 0x99, 0xdd, 0x42, 0x21, 0x49, 0xe1, 0xb6, 0x33, 0x19, 0xda, ++ 0x49, 0x1f, 0xbd, 0x63, 0x17, 0xe0, 0xb1, 0x7b, 0x61, 0x25, 0xf4, 0x57, ++ 0x9d, 0x3c, 0xd3, 0x01, 0x78, 0xd2, 0x89, 0xfe, 0xf7, 0xaf, 0xeb, 0x03, ++ 0xf3, 0xad, 0xb6, 0x77, 0x73, 0x44, 0xd1, 0xf7, 0xc7, 0x37, 0x4b, 0x88, ++ 0x57, 0xc4, 0x63, 0x22, 0x30, 0xff, 0x6a, 0x0a, 0x5f, 0xa8, 0x8f, 0xf7, ++ 0x0e, 0xf5, 0xc2, 0x7c, 0xae, 0x71, 0xf8, 0x09, 0x38, 0xb6, 0xe9, 0xfc, ++ 0x73, 0x60, 0x7e, 0x6d, 0xaf, 0x1b, 0x88, 0x87, 0xb6, 0x8f, 0x1f, 0xc5, ++ 0xf0, 0xd5, 0x3a, 0xaa, 0x11, 0xf9, 0xc7, 0xdb, 0xfb, 0xc7, 0x9c, 0x90, ++ 0xf2, 0x42, 0x78, 0x69, 0xde, 0x67, 0xf0, 0x41, 0xdd, 0xa6, 0xb5, 0x48, ++ 0x0e, 0xe0, 0x4b, 0xe4, 0x7e, 0x03, 0xcc, 0x67, 0x01, 0x9f, 0x4f, 0x83, ++ 0x8e, 0xcc, 0x75, 0xd1, 0xef, 0xac, 0x63, 0x59, 0x3f, 0x3d, 0x36, 0x4b, ++ 0xc8, 0x2f, 0x7e, 0x0d, 0xf4, 0x94, 0x00, 0xa5, 0x86, 0x97, 0x7a, 0x8e, ++ 0xe7, 0x0d, 0xac, 0xb4, 0x78, 0xf2, 0x5c, 0x14, 0x1f, 0xae, 0xf1, 0xfd, ++ 0x47, 0x34, 0xa1, 0xfd, 0x2e, 0xe7, 0xf8, 0x52, 0xb5, 0xd0, 0x87, 0xf4, ++ 0x54, 0xf9, 0x0a, 0xeb, 0x2f, 0xde, 0xe0, 0xcc, 0x5f, 0x15, 0x86, 0xbf, ++ 0xf1, 0xa5, 0x04, 0xe9, 0x78, 0x77, 0x14, 0x99, 0x5b, 0x4e, 0x9f, 0xef, ++ 0xb6, 0xb2, 0x52, 0x8d, 0xaf, 0xa7, 0x39, 0x5d, 0x67, 0x3d, 0xbf, 0x12, ++ 0xf7, 0x7d, 0x01, 0xdd, 0x77, 0xd8, 0xd7, 0xd4, 0xcd, 0xf4, 0x39, 0xc0, ++ 0x8d, 0xe2, 0x05, 0xc0, 0x8d, 0xee, 0x23, 0xe2, 0xc1, 0xbd, 0xf1, 0x4b, ++ 0x70, 0xdf, 0x16, 0x6c, 0x96, 0x1e, 0xc0, 0x7d, 0xf4, 0x0c, 0x20, 0x50, ++ 0x4f, 0x88, 0x63, 0xeb, 0x54, 0xf7, 0x7f, 0x96, 0xf3, 0xc5, 0xdd, 0x51, ++ 0xae, 0x42, 0x89, 0xf6, 0x17, 0x4c, 0x30, 0x3b, 0x76, 0x48, 0x30, 0x1f, ++ 0xa7, 0x26, 0x0a, 0xea, 0xf9, 0x56, 0xc7, 0x0e, 0x02, 0xdf, 0xbb, 0x76, ++ 0xc2, 0x78, 0x09, 0x49, 0x51, 0x8e, 0xfa, 0x30, 0x7e, 0x45, 0x88, 0xab, ++ 0x50, 0x43, 0xc7, 0xb9, 0x94, 0x68, 0x66, 0xfb, 0xed, 0x7d, 0x5f, 0x3b, ++ 0x39, 0x17, 0xe8, 0xd1, 0x8e, 0xed, 0x09, 0x32, 0xf1, 0x11, 0xe4, 0x3f, ++ 0x24, 0xdb, 0x95, 0x1b, 0xfa, 0xae, 0xac, 0x07, 0xeb, 0xaf, 0x8c, 0xf7, ++ 0x37, 0xa1, 0xc1, 0x93, 0x47, 0xb2, 0x19, 0x3c, 0x10, 0x2e, 0x1c, 0x1e, ++ 0xde, 0x75, 0xdd, 0xa6, 0x87, 0xf3, 0xd3, 0x4f, 0x38, 0x3c, 0xbc, 0x77, ++ 0x91, 0xe9, 0xc0, 0x37, 0x8e, 0xe9, 0x89, 0xc9, 0x08, 0xfd, 0x5b, 0xe8, ++ 0x38, 0xb4, 0xbf, 0xc4, 0x1d, 0x43, 0x5f, 0xd8, 0x84, 0xf3, 0xab, 0xc7, ++ 0x7d, 0x7b, 0xdb, 0x62, 0xc1, 0xb2, 0x2c, 0xce, 0x55, 0x58, 0x0b, 0x2c, ++ 0xb8, 0x87, 0x6b, 0x35, 0xc0, 0x45, 0xac, 0x53, 0x0d, 0x8f, 0x45, 0x1c, ++ 0x1e, 0x6f, 0x4d, 0x9b, 0x93, 0xaf, 0x01, 0x3c, 0x9e, 0x62, 0x72, 0x00, ++ 0xdd, 0x3d, 0x79, 0x40, 0x9a, 0x8f, 0x78, 0xed, 0x31, 0x52, 0xa2, 0x04, ++ 0xbc, 0x67, 0x74, 0x48, 0xe8, 0x7e, 0x00, 0x5d, 0x10, 0xb7, 0x16, 0xf7, ++ 0xa3, 0xba, 0xd6, 0xe5, 0x8d, 0x8c, 0xf7, 0xe5, 0x48, 0x67, 0xd5, 0xf1, ++ 0x51, 0x8e, 0x28, 0x09, 0xf1, 0xde, 0x89, 0xf2, 0xcf, 0x63, 0xf2, 0x32, ++ 0xbc, 0x67, 0xf2, 0x2f, 0x7a, 0x2c, 0x93, 0x57, 0xc0, 0x27, 0xcb, 0x73, ++ 0x3b, 0xf3, 0x03, 0xc1, 0x67, 0x40, 0xbe, 0x01, 0x3e, 0x0b, 0xba, 0xa8, ++ 0x1e, 0x11, 0xc8, 0x81, 0xfd, 0xfd, 0xba, 0x7c, 0xa5, 0x4d, 0xc7, 0xe8, ++ 0xbc, 0x8d, 0xc2, 0x01, 0xe8, 0x48, 0xd0, 0x8d, 0xf9, 0x0d, 0x46, 0x2f, ++ 0x9b, 0xd6, 0xd9, 0x8b, 0xa1, 0x7d, 0x13, 0xa5, 0xfb, 0xf0, 0xfd, 0x3e, ++ 0xae, 0xf7, 0x20, 0xfd, 0x1e, 0xcf, 0xee, 0xe6, 0x80, 0x7e, 0x61, 0x9e, ++ 0x2e, 0x73, 0x88, 0xbf, 0x67, 0x58, 0x5c, 0x36, 0x2b, 0x85, 0x77, 0xb5, ++ 0xc6, 0xb7, 0x41, 0x9b, 0x15, 0xe2, 0xc7, 0xd5, 0x6f, 0x3c, 0x96, 0xe3, ++ 0x8e, 0x80, 0x7f, 0x82, 0x1f, 0x1b, 0xb5, 0x8c, 0xcf, 0x19, 0xbd, 0xd1, ++ 0x5e, 0xd6, 0x2f, 0x1b, 0xcf, 0x48, 0xc1, 0x6d, 0x2e, 0xc0, 0xd2, 0x03, ++ 0xf2, 0x28, 0x7a, 0x0d, 0x83, 0x8f, 0xba, 0x9f, 0x5e, 0x56, 0x21, 0x5f, ++ 0x8d, 0x96, 0x0b, 0x54, 0x8e, 0x4f, 0xa2, 0x9b, 0x14, 0xdb, 0x83, 0x90, ++ 0xb1, 0x1a, 0x77, 0x2f, 0x2b, 0xed, 0xa7, 0xca, 0x18, 0x38, 0x4e, 0x77, ++ 0x96, 0x64, 0xac, 0x09, 0xea, 0x61, 0x1e, 0x89, 0x20, 0xbb, 0x80, 0x7e, ++ 0x76, 0x44, 0x7b, 0x81, 0x6f, 0x25, 0x26, 0x12, 0xf7, 0xde, 0x08, 0xfd, ++ 0x26, 0x59, 0x19, 0x1f, 0x10, 0xfb, 0xd2, 0x60, 0x63, 0x74, 0x94, 0x18, ++ 0xc3, 0xde, 0x2f, 0xb6, 0x32, 0xfe, 0x50, 0x68, 0x65, 0x78, 0x79, 0x2f, ++ 0x2f, 0xc5, 0xfc, 0x05, 0xfe, 0xdb, 0x35, 0xee, 0x4f, 0x89, 0xdc, 0xb5, ++ 0x1c, 0x13, 0xdf, 0xd1, 0x79, 0x61, 0xbb, 0x98, 0x0f, 0xfd, 0x7e, 0x23, ++ 0x61, 0xf2, 0x17, 0xe7, 0x9b, 0xf8, 0x70, 0xce, 0x8e, 0x4d, 0x61, 0xfb, ++ 0x11, 0xa2, 0xa3, 0xbb, 0x0a, 0x60, 0x9f, 0x7a, 0x6c, 0xf6, 0x69, 0xe7, ++ 0x9b, 0x42, 0xe3, 0x08, 0x79, 0xaa, 0xde, 0x7f, 0x98, 0x3f, 0xd0, 0x0f, ++ 0xac, 0xa7, 0xbc, 0x6f, 0xd7, 0xef, 0x35, 0x1c, 0x66, 0xf4, 0xa8, 0xc6, ++ 0xc7, 0x72, 0xce, 0x17, 0x63, 0xad, 0x84, 0xbd, 0xa7, 0xf3, 0xfd, 0x15, ++ 0xe9, 0x6a, 0x85, 0x99, 0xec, 0x80, 0xf9, 0x6d, 0x25, 0xce, 0x38, 0x3a, ++ 0xaf, 0x9a, 0x43, 0xbd, 0x19, 0x3d, 0x38, 0x83, 0x39, 0xd0, 0xff, 0x11, ++ 0x9b, 0xfb, 0x15, 0xd8, 0x8f, 0x81, 0xa3, 0x38, 0x9e, 0xd3, 0xe7, 0x93, ++ 0xe9, 0xf3, 0xe5, 0x5a, 0xe2, 0x31, 0xd0, 0x3d, 0x59, 0xbe, 0x5b, 0xe7, ++ 0x0d, 0x18, 0x19, 0xcd, 0xdc, 0xa2, 0xff, 0x95, 0xd8, 0x58, 0xff, 0xed, ++ 0x66, 0xa3, 0x47, 0xa6, 0x78, 0x7e, 0xc6, 0xe6, 0x76, 0x03, 0x7e, 0x79, ++ 0x4a, 0x88, 0xc3, 0x07, 0x72, 0xe9, 0x07, 0x94, 0x7f, 0x00, 0xfd, 0x11, ++ 0x5f, 0x11, 0xf0, 0x97, 0x1a, 0x12, 0x88, 0x01, 0x38, 0x57, 0xcb, 0xfe, ++ 0x1c, 0x42, 0xf7, 0x7f, 0xb0, 0xc9, 0xbd, 0x08, 0xc6, 0x3b, 0xaf, 0xf1, ++ 0x67, 0xc0, 0x73, 0x42, 0x02, 0x88, 0xaf, 0xe7, 0xa2, 0x62, 0xf2, 0x08, ++ 0xed, 0xaf, 0x49, 0xef, 0x4b, 0xff, 0x3e, 0xcc, 0xfb, 0xa4, 0x4c, 0x76, ++ 0xd0, 0x7e, 0xae, 0x13, 0xe7, 0x78, 0x58, 0xc7, 0x75, 0xbf, 0xc6, 0xe6, ++ 0xa1, 0xeb, 0xf8, 0xb8, 0xf9, 0x77, 0xbf, 0x3a, 0x40, 0xbf, 0x9a, 0x7d, ++ 0xe0, 0xda, 0xec, 0x87, 0x00, 0x4a, 0x9b, 0xa2, 0xe7, 0x3c, 0x4b, 0xcb, ++ 0x59, 0x46, 0x8d, 0x51, 0xdb, 0x3f, 0x04, 0x8f, 0x73, 0xe6, 0xc8, 0xfc, ++ 0xf5, 0x87, 0x1c, 0x7f, 0x12, 0xea, 0x99, 0xde, 0x15, 0x5c, 0x67, 0xf0, ++ 0x02, 0x7c, 0xd4, 0xef, 0x4d, 0xb0, 0xb1, 0xfd, 0xaf, 0xb9, 0x91, 0x4a, ++ 0x3c, 0x71, 0xe1, 0xcf, 0x19, 0x1f, 0xad, 0xd1, 0x06, 0xf5, 0xa0, 0x42, ++ 0xd6, 0xdc, 0xc8, 0x20, 0x1e, 0x3a, 0xee, 0xc7, 0x1a, 0x52, 0xd1, 0x18, ++ 0x41, 0xcf, 0x0c, 0x58, 0x19, 0xff, 0x6a, 0xa2, 0xa8, 0x1f, 0xa9, 0xfd, ++ 0x73, 0x8e, 0x67, 0xbb, 0x75, 0x24, 0x67, 0x2b, 0xcc, 0x67, 0x3b, 0xe5, ++ 0x83, 0x00, 0x3f, 0xad, 0x1d, 0xf9, 0x45, 0xc5, 0x4f, 0xb3, 0x1c, 0x9b, ++ 0x68, 0xb5, 0x29, 0x3b, 0x78, 0x1c, 0xf4, 0x88, 0xe0, 0xcf, 0x24, 0xe4, ++ 0xff, 0xe7, 0x74, 0x8c, 0xef, 0xd0, 0xbf, 0x29, 0xc6, 0x01, 0x21, 0xf9, ++ 0x09, 0xea, 0x09, 0xe8, 0x87, 0x15, 0x16, 0x8f, 0x4f, 0x43, 0xf9, 0x46, ++ 0xc5, 0x6a, 0xb3, 0x4f, 0xce, 0xc3, 0xe7, 0xda, 0x61, 0xb0, 0x77, 0x1e, ++ 0x8b, 0x16, 0xf8, 0xe0, 0x7c, 0x2e, 0x17, 0x17, 0xd4, 0xbe, 0xfd, 0x77, ++ 0x29, 0x86, 0xb6, 0x6b, 0x89, 0x71, 0x18, 0xfd, 0xee, 0x0b, 0xd3, 0xc2, ++ 0x18, 0x10, 0x0b, 0x8b, 0xbf, 0xbb, 0x2a, 0x11, 0x94, 0xef, 0xa4, 0x59, ++ 0x0d, 0x48, 0x9f, 0x84, 0x8c, 0xb2, 0x80, 0x3e, 0x2e, 0x39, 0x27, 0xc8, ++ 0xb7, 0xa2, 0x6f, 0xa7, 0xcf, 0x69, 0x51, 0x6f, 0x47, 0x7c, 0xa1, 0xfb, ++ 0xeb, 0xb2, 0xb9, 0x5e, 0x80, 0xfd, 0x9e, 0x15, 0xcb, 0xe0, 0x3d, 0x6b, ++ 0x55, 0xb4, 0xd7, 0x13, 0xc6, 0xff, 0xa6, 0x71, 0xf8, 0xa8, 0xf1, 0x6c, ++ 0x37, 0xe0, 0x28, 0x9d, 0xef, 0x27, 0x12, 0x93, 0x2b, 0xea, 0x71, 0x5e, ++ 0xb5, 0x95, 0xdc, 0x07, 0x78, 0x97, 0x14, 0xe3, 0xfa, 0x35, 0xf6, 0xbf, ++ 0xea, 0x9a, 0x82, 0x9f, 0xb5, 0x49, 0x81, 0x17, 0x9f, 0x05, 0x7c, 0x5c, ++ 0x61, 0x76, 0xec, 0x62, 0xdd, 0x66, 0xb8, 0xc2, 0xe8, 0xe5, 0x1d, 0x31, ++ 0xee, 0x0d, 0x0d, 0xee, 0x5f, 0x7b, 0xbe, 0x3f, 0x67, 0x4d, 0x16, 0xe0, ++ 0x7d, 0x30, 0xe3, 0xf7, 0x14, 0xce, 0xcb, 0x5b, 0x0c, 0x16, 0x8f, 0x1d, ++ 0xda, 0xf5, 0x8a, 0xfd, 0x3f, 0x5f, 0x47, 0x19, 0x5f, 0x4e, 0xa8, 0x3e, ++ 0xff, 0x52, 0xcf, 0xd1, 0xc4, 0x04, 0xf0, 0x77, 0x6c, 0x00, 0x7c, 0x58, ++ 0xb0, 0x31, 0x9a, 0x78, 0xfa, 0x84, 0xd6, 0x01, 0x0a, 0x37, 0xe0, 0x77, ++ 0xf5, 0x0d, 0x82, 0xfd, 0xcc, 0x6f, 0x79, 0xfb, 0x2c, 0xf0, 0xf3, 0x6a, ++ 0x6d, 0x00, 0xf1, 0x67, 0xbe, 0xd1, 0x84, 0xfb, 0x53, 0x7d, 0x43, 0x8b, ++ 0xf3, 0x20, 0x1b, 0x75, 0xad, 0x01, 0xf1, 0x3d, 0x95, 0xbf, 0xfd, 0x62, ++ 0x9c, 0x27, 0x91, 0xbe, 0x1e, 0x1d, 0x66, 0xbd, 0x78, 0x0f, 0x7d, 0x98, ++ 0x44, 0x9f, 0xe3, 0xfa, 0xdd, 0xef, 0xc3, 0xba, 0x9f, 0x8e, 0x8e, 0x21, ++ 0x4e, 0x46, 0x2f, 0xde, 0xde, 0x74, 0xfe, 0xd7, 0x8d, 0xf6, 0x58, 0x1b, ++ 0x85, 0x57, 0x8d, 0x9e, 0xe2, 0x47, 0x3f, 0xec, 0xc6, 0x65, 0x0c, 0xd3, ++ 0xaf, 0x48, 0x9a, 0x59, 0xb9, 0xff, 0x2d, 0x27, 0xff, 0x0e, 0xf3, 0x59, ++ 0x68, 0x74, 0xeb, 0x41, 0xde, 0x2f, 0x9a, 0x5e, 0xab, 0x07, 0xba, 0x9c, ++ 0x15, 0xeb, 0x2b, 0xb2, 0xf4, 0x0d, 0xdf, 0xf7, 0x61, 0xf2, 0xad, 0x7b, ++ 0xbe, 0xfe, 0xbe, 0x37, 0x71, 0x3e, 0xf4, 0xb1, 0x9e, 0xd2, 0x45, 0x04, ++ 0x3a, 0xfc, 0x9c, 0xc3, 0x7f, 0x02, 0xe0, 0x24, 0x5d, 0xdf, 0xc7, 0xa9, ++ 0x8c, 0x7e, 0x3e, 0xce, 0x20, 0x15, 0x7b, 0xa1, 0xbc, 0x9b, 0x96, 0xf4, ++ 0xbb, 0x8f, 0xb3, 0x79, 0xbd, 0x80, 0xd5, 0xd5, 0xfd, 0x44, 0xd9, 0x18, ++ 0x3d, 0x7f, 0x9c, 0xc7, 0xe4, 0x95, 0x67, 0x25, 0x93, 0x1f, 0xea, 0xf7, ++ 0xfe, 0xc1, 0xc7, 0x73, 0xd9, 0x9c, 0x5f, 0x02, 0x3c, 0xc5, 0x73, 0xa7, ++ 0x8d, 0x3d, 0x7f, 0xd5, 0xe6, 0xfc, 0x0a, 0x9e, 0x53, 0x7e, 0xf8, 0x5f, ++ 0x1c, 0x5f, 0x7d, 0x56, 0xda, 0xdf, 0xac, 0x37, 0x0d, 0x88, 0xaf, 0x64, ++ 0x7d, 0x30, 0x07, 0xf6, 0xb1, 0x63, 0x5d, 0x39, 0x7c, 0xbe, 0x89, 0x91, ++ 0xe7, 0x95, 0x61, 0x63, 0xfc, 0x98, 0xf6, 0x2b, 0xd9, 0x8a, 0xf0, 0x3d, ++ 0x27, 0xea, 0xed, 0x87, 0xa2, 0xbc, 0x60, 0x87, 0x90, 0x09, 0x94, 0x3f, ++ 0x03, 0x3f, 0x5e, 0x99, 0x4e, 0x80, 0x1f, 0xd3, 0x71, 0xa3, 0x6c, 0xac, ++ 0x5f, 0x9f, 0x15, 0xdf, 0x33, 0xe0, 0x3a, 0xc8, 0x46, 0xca, 0xa7, 0x29, ++ 0xde, 0xb6, 0x17, 0xd9, 0x71, 0x5f, 0x36, 0x15, 0x53, 0xfc, 0x04, 0x3e, ++ 0x71, 0xd0, 0x60, 0x01, 0x3e, 0x21, 0xf0, 0x49, 0xe0, 0x91, 0x1a, 0x7f, ++ 0x12, 0x6d, 0x42, 0xfe, 0x31, 0x39, 0x7c, 0x1f, 0xc8, 0x61, 0x19, 0xe5, ++ 0x70, 0xa2, 0x8d, 0xc9, 0x61, 0x3d, 0xd0, 0x39, 0xed, 0x51, 0xcf, 0xf4, ++ 0xc1, 0x9e, 0xb8, 0xdf, 0x88, 0x67, 0xf2, 0xd7, 0xdf, 0xef, 0x3d, 0x46, ++ 0xb6, 0x8f, 0x94, 0xde, 0xed, 0x36, 0x94, 0xfb, 0xbe, 0xdc, 0x70, 0x7a, ++ 0x13, 0x70, 0x16, 0x7c, 0xf2, 0xe3, 0x6e, 0x4a, 0xbc, 0xd8, 0xcd, 0xf9, ++ 0x60, 0x1f, 0x0e, 0xb7, 0x0e, 0x38, 0xdb, 0xd8, 0x7b, 0xf1, 0x3d, 0x98, ++ 0xdc, 0x13, 0xf6, 0xc1, 0x20, 0xbe, 0xae, 0x57, 0x38, 0x3f, 0x17, 0xa5, ++ 0x90, 0x63, 0x03, 0xc7, 0x2a, 0xf5, 0x92, 0x57, 0xb8, 0x5e, 0xf0, 0x8a, ++ 0x35, 0x46, 0xec, 0x4b, 0x21, 0xac, 0x5f, 0xc8, 0xbf, 0x4e, 0xfb, 0xfd, ++ 0x1c, 0xdb, 0x6f, 0xfa, 0xde, 0x60, 0x58, 0xcf, 0x2c, 0x43, 0x70, 0x4e, ++ 0x1c, 0x95, 0x5f, 0xdf, 0xa1, 0x7a, 0x91, 0xbe, 0x00, 0xbf, 0x6b, 0x82, ++ 0xef, 0x3a, 0xf9, 0x29, 0x46, 0x31, 0xb9, 0x5b, 0xb3, 0xd2, 0x4c, 0x40, ++ 0x2f, 0x28, 0xb5, 0x59, 0x18, 0xfc, 0x0b, 0x83, 0x19, 0xd0, 0x1f, 0xe9, ++ 0x13, 0x44, 0x3e, 0x34, 0x9f, 0x50, 0x7e, 0x23, 0xdd, 0x79, 0xff, 0xc0, ++ 0x27, 0x90, 0x42, 0x69, 0x64, 0x69, 0x0c, 0x93, 0x3b, 0x92, 0x4c, 0x07, ++ 0x04, 0x9a, 0xe9, 0x43, 0xec, 0xd0, 0x1f, 0x85, 0xf7, 0x24, 0x5b, 0x51, ++ 0x08, 0xde, 0xea, 0xf1, 0xce, 0x41, 0x13, 0xd5, 0x03, 0xa7, 0xdb, 0x24, ++ 0x2d, 0xee, 0x57, 0x3e, 0xc9, 0x87, 0xfd, 0x9a, 0xf3, 0xc1, 0x97, 0xe6, ++ 0xd9, 0xb4, 0xcb, 0x6b, 0x16, 0xa3, 0x47, 0x43, 0xe5, 0xc8, 0x77, 0x35, ++ 0xee, 0x59, 0xd0, 0x4f, 0xeb, 0x83, 0x27, 0x51, 0xef, 0x3f, 0xa7, 0xf7, ++ 0xe5, 0x34, 0x98, 0x22, 0xb4, 0xeb, 0x7d, 0xcf, 0x3f, 0x2d, 0x85, 0xda, ++ 0xe7, 0xbe, 0x24, 0x7b, 0xf4, 0x94, 0xcf, 0x34, 0xf9, 0x5b, 0x7f, 0x36, ++ 0x8d, 0xe2, 0xe5, 0x7c, 0xbf, 0xec, 0x80, 0x21, 0xe7, 0xaf, 0xfd, 0xeb, ++ 0x7b, 0x03, 0x41, 0x9f, 0xf6, 0xeb, 0x1c, 0x60, 0xd7, 0x52, 0x7d, 0x62, ++ 0xb3, 0x16, 0xe6, 0x5d, 0xcb, 0xf4, 0xcf, 0x73, 0x1a, 0xe5, 0xfe, 0x5f, ++ 0xfd, 0x1e, 0xdb, 0x5f, 0x51, 0x7f, 0x90, 0xe3, 0x0b, 0xd5, 0xb3, 0xb4, ++ 0x64, 0x40, 0x88, 0x5f, 0x09, 0x3d, 0x61, 0x29, 0xf1, 0xf5, 0x02, 0x7d, ++ 0x62, 0x01, 0x71, 0xea, 0xa1, 0x3c, 0xbf, 0x62, 0xc9, 0x04, 0x42, 0xe1, ++ 0xb7, 0xc8, 0xb4, 0x1a, 0xf9, 0xd8, 0xe5, 0x95, 0xe3, 0x50, 0x7f, 0x5e, ++ 0x4c, 0x3c, 0xd8, 0xbe, 0x60, 0xa3, 0xee, 0x7c, 0xb8, 0x7c, 0x59, 0xd4, ++ 0xa0, 0xac, 0x2f, 0xd9, 0xaa, 0xac, 0x2f, 0xf5, 0x2a, 0xeb, 0x42, 0xff, ++ 0x4a, 0x28, 0x8d, 0xac, 0x57, 0xbc, 0xc8, 0xf9, 0xd0, 0x55, 0x2a, 0x2e, ++ 0x6e, 0xa7, 0x57, 0x6c, 0xe1, 0x78, 0x5b, 0xfa, 0xe8, 0x84, 0xa7, 0x91, ++ 0xfe, 0xfd, 0x3a, 0x62, 0xa0, 0xef, 0xad, 0x3e, 0x58, 0x9c, 0x44, 0x22, ++ 0xf4, 0x2b, 0xca, 0x9a, 0x1b, 0xd9, 0xc4, 0x1b, 0x26, 0x87, 0x42, 0xfa, ++ 0x47, 0x0e, 0xf1, 0xf6, 0x87, 0xfe, 0x6e, 0xa2, 0x3f, 0xf0, 0x79, 0xae, ++ 0x9f, 0x40, 0x7f, 0x60, 0xef, 0xae, 0x8e, 0x72, 0x26, 0x81, 0x5d, 0x72, ++ 0xb5, 0x24, 0xf2, 0xbc, 0xb7, 0xf1, 0x79, 0xd7, 0xdc, 0xe8, 0xa6, 0xe8, ++ 0xff, 0xf9, 0x4e, 0x7a, 0x4e, 0x0c, 0x8e, 0x53, 0x73, 0xc3, 0x88, 0x65, ++ 0xe7, 0x79, 0x98, 0xf0, 0xfb, 0xab, 0x8b, 0x23, 0x8f, 0xb3, 0xbb, 0x43, ++ 0x9f, 0xb2, 0x28, 0xe4, 0x69, 0xe8, 0xfb, 0x78, 0x26, 0xff, 0xb8, 0x3d, ++ 0x2f, 0xf0, 0xa1, 0xe6, 0x46, 0x32, 0x3e, 0x17, 0x75, 0xa1, 0x67, 0x87, ++ 0xbe, 0x4b, 0xc3, 0xfe, 0xa8, 0x60, 0xb3, 0x5c, 0x8c, 0x0e, 0xf1, 0x23, ++ 0x5d, 0x37, 0x36, 0x0f, 0x81, 0xff, 0x9f, 0x49, 0xc4, 0x98, 0x82, 0xfe, ++ 0xb1, 0x2d, 0xdc, 0x2e, 0x71, 0xe4, 0x81, 0x9e, 0xfb, 0x19, 0xe8, 0x51, ++ 0x40, 0x7f, 0x63, 0xec, 0x87, 0x02, 0x74, 0x8a, 0x0b, 0x1e, 0x1a, 0x9c, ++ 0xa3, 0xcd, 0x0e, 0xd1, 0x87, 0x7a, 0x1d, 0x14, 0x8f, 0xae, 0x04, 0xc2, ++ 0xe4, 0xfb, 0x21, 0x9b, 0x39, 0x1e, 0xe5, 0xb2, 0x83, 0x38, 0x60, 0x5c, ++ 0x81, 0xdf, 0x73, 0x1e, 0x2c, 0x8b, 0x75, 0xd3, 0xf9, 0xfe, 0x69, 0x6d, ++ 0x69, 0x92, 0xbb, 0x6f, 0x38, 0xdf, 0xf4, 0xe0, 0xf8, 0xd5, 0x7a, 0xa1, ++ 0xbf, 0x99, 0x14, 0xf2, 0x98, 0xa8, 0xe4, 0xf5, 0x82, 0xe6, 0x93, 0xa8, ++ 0x9f, 0x2d, 0x34, 0xba, 0x72, 0x80, 0xc9, 0x7c, 0x7e, 0xf0, 0x41, 0xc4, ++ 0xef, 0xc5, 0xc4, 0x95, 0x08, 0x78, 0xdd, 0x7e, 0xb0, 0x77, 0x86, 0xfb, ++ 0x7f, 0x21, 0xa7, 0xc5, 0x7c, 0xee, 0xf7, 0xcc, 0xd3, 0x31, 0x7d, 0x9c, ++ 0x12, 0x2d, 0xa5, 0xb7, 0xc9, 0x7c, 0x3e, 0xf7, 0xb7, 0x30, 0xfd, 0x50, ++ 0x63, 0x74, 0xea, 0x70, 0x1c, 0x27, 0xb1, 0x5b, 0x12, 0xd1, 0xe4, 0x66, ++ 0xf3, 0xa5, 0xcc, 0x52, 0x4b, 0xeb, 0xc3, 0x3b, 0xe6, 0x0f, 0xce, 0x43, ++ 0x42, 0x86, 0xf1, 0xf9, 0x4b, 0xf0, 0x3d, 0x85, 0xef, 0x70, 0x5e, 0x92, ++ 0xf9, 0xee, 0x64, 0x98, 0xb7, 0x01, 0xc6, 0xa5, 0xe3, 0x45, 0x11, 0x6f, ++ 0x32, 0x94, 0xf5, 0x83, 0x1d, 0x76, 0x28, 0x47, 0x4a, 0x2e, 0x2d, 0x9b, ++ 0x07, 0xdb, 0xe7, 0xd1, 0xa4, 0x36, 0x0d, 0xde, 0xd7, 0x18, 0x03, 0x32, ++ 0x5b, 0x27, 0x9d, 0x41, 0x22, 0x7c, 0xdf, 0x01, 0x2f, 0xac, 0x9b, 0x79, ++ 0x7d, 0xfd, 0x94, 0xeb, 0x73, 0x16, 0xc1, 0x73, 0x93, 0x19, 0xf9, 0x86, ++ 0x9e, 0xcf, 0xe3, 0x16, 0xf0, 0x3f, 0x23, 0xf2, 0x13, 0x23, 0xac, 0xdb, ++ 0x60, 0xf2, 0x5d, 0x86, 0x75, 0x99, 0x79, 0xe9, 0x29, 0x61, 0xfa, 0xb6, ++ 0x27, 0x9b, 0x38, 0xea, 0xe9, 0x6b, 0xdd, 0x48, 0x23, 0x81, 0x71, 0x4d, ++ 0xa6, 0x6b, 0x1e, 0x58, 0xac, 0x85, 0x58, 0x24, 0xa8, 0x47, 0x59, 0xae, ++ 0xfb, 0xc0, 0xee, 0xb8, 0x66, 0x31, 0x79, 0x34, 0xfd, 0x90, 0x2f, 0xca, ++ 0x71, 0x14, 0x7e, 0xad, 0xd2, 0xbb, 0x8b, 0x61, 0x5f, 0x28, 0x1f, 0x66, ++ 0x7e, 0xa8, 0xae, 0xda, 0xb5, 0x3e, 0xb4, 0x77, 0x04, 0x5f, 0xb3, 0xf1, ++ 0xf9, 0xd5, 0x73, 0xbe, 0x96, 0x42, 0x18, 0x1c, 0xe2, 0x89, 0xeb, 0xb0, ++ 0x93, 0xf2, 0x85, 0x9f, 0x98, 0x17, 0x4f, 0x20, 0x31, 0x20, 0x8e, 0xdd, ++ 0x38, 0xfe, 0x33, 0x31, 0x63, 0x4f, 0xc0, 0x7c, 0x01, 0xf0, 0x28, 0xaf, ++ 0xc7, 0x6a, 0xcf, 0x87, 0xcb, 0x8b, 0x04, 0x97, 0x56, 0xc1, 0xb7, 0x92, ++ 0xa6, 0x2b, 0xeb, 0x29, 0x6e, 0x65, 0xdd, 0x48, 0xce, 0x59, 0x00, 0x7f, ++ 0x25, 0x9f, 0x2b, 0xf9, 0x56, 0x1c, 0xda, 0x71, 0x7d, 0xc0, 0x2f, 0xa3, ++ 0xe3, 0xfc, 0x62, 0x4a, 0x37, 0x36, 0x2f, 0x81, 0x3f, 0xd9, 0x71, 0x1a, ++ 0x85, 0x3e, 0xe1, 0xe2, 0x76, 0x7d, 0xb5, 0x4d, 0x4f, 0xd0, 0x1f, 0x98, ++ 0x68, 0x34, 0x92, 0x7e, 0xa8, 0x5f, 0x64, 0xc7, 0x31, 0xfd, 0xe2, 0x13, ++ 0xba, 0xd3, 0xd4, 0xfe, 0x0b, 0x22, 0x1f, 0xce, 0x1f, 0xe9, 0xec, 0xf5, ++ 0x33, 0x0a, 0xe7, 0x0d, 0x1f, 0xc8, 0x8e, 0x87, 0xe9, 0x3e, 0x6d, 0x30, ++ 0xdb, 0xd7, 0x69, 0x41, 0x6f, 0x9b, 0x21, 0x31, 0x3d, 0x5d, 0xdb, 0xe8, ++ 0x03, 0x3f, 0xcf, 0xf6, 0x39, 0x56, 0xc7, 0x26, 0x68, 0x8f, 0x72, 0xfe, ++ 0xf8, 0xbf, 0xa1, 0xfd, 0x03, 0x99, 0x80, 0xde, 0x54, 0x03, 0xfe, 0x75, ++ 0xa4, 0x77, 0x4b, 0x31, 0x7c, 0xb7, 0x3d, 0xc3, 0x82, 0xef, 0xc5, 0x97, ++ 0x06, 0xd1, 0x2f, 0x1a, 0x7c, 0x8c, 0xa0, 0x5e, 0xd4, 0x09, 0x4f, 0x6f, ++ 0xd2, 0xf9, 0x53, 0x78, 0xbf, 0x00, 0x75, 0x0a, 0xdf, 0x9a, 0x85, 0x96, ++ 0xe5, 0xaf, 0xd0, 0xf7, 0x53, 0x5c, 0xd1, 0x0e, 0x29, 0xac, 0x7d, 0x27, ++ 0xb4, 0xd3, 0x79, 0x4a, 0x1c, 0x2f, 0xe0, 0xf9, 0xc8, 0x01, 0x60, 0xc7, ++ 0xb2, 0xbf, 0x1e, 0x2d, 0xf9, 0x7e, 0x27, 0xf8, 0x29, 0x9c, 0x32, 0xca, ++ 0xb5, 0x9a, 0x96, 0xfc, 0x23, 0x26, 0x3a, 0x8f, 0x1e, 0xee, 0x7c, 0x07, ++ 0xa0, 0x6d, 0xcf, 0x16, 0x1e, 0x47, 0x89, 0x37, 0x78, 0x59, 0x1c, 0x81, ++ 0x52, 0x2d, 0x9d, 0xc7, 0x54, 0x23, 0x9b, 0x47, 0x4d, 0x4b, 0xf1, 0x7d, ++ 0x45, 0xb4, 0xbd, 0xa7, 0xbf, 0x3f, 0x81, 0x78, 0x42, 0xf4, 0x09, 0xfb, ++ 0xcc, 0x4a, 0x68, 0xd2, 0x50, 0xfb, 0x19, 0xbe, 0x2b, 0x89, 0x46, 0xff, ++ 0xd5, 0x69, 0xee, 0x47, 0x22, 0x9c, 0x1f, 0x0c, 0x54, 0xd1, 0xdb, 0xd0, ++ 0x10, 0xfe, 0x63, 0x7b, 0xbe, 0xa8, 0x53, 0xf1, 0xef, 0x1c, 0xc0, 0xdc, ++ 0x13, 0x58, 0x8f, 0x67, 0x74, 0xe0, 0x20, 0xe2, 0x8f, 0xd1, 0xe7, 0x10, ++ 0x12, 0xfa, 0x83, 0xef, 0x4b, 0x43, 0xfd, 0x21, 0x3f, 0x1a, 0x15, 0x6a, ++ 0x0e, 0xd1, 0x1b, 0x5d, 0x5a, 0x81, 0xd1, 0x51, 0x5f, 0x49, 0xdf, 0x3b, ++ 0x56, 0x3e, 0x06, 0xf1, 0xb0, 0x06, 0xec, 0x27, 0xba, 0x1f, 0x03, 0xb5, ++ 0xbe, 0xc3, 0x40, 0xdf, 0x43, 0x79, 0x99, 0xcf, 0x4b, 0x32, 0xbf, 0x01, ++ 0xe1, 0xb9, 0x69, 0x9d, 0x53, 0x06, 0xb8, 0x17, 0x11, 0xb7, 0xbc, 0x85, ++ 0xd6, 0x07, 0x19, 0xfd, 0x71, 0x40, 0x0f, 0xc3, 0x8c, 0x81, 0x75, 0x09, ++ 0xb4, 0xbf, 0xc1, 0xd3, 0xe7, 0x25, 0x43, 0xfd, 0x20, 0x28, 0x59, 0x45, ++ 0xa8, 0x67, 0x79, 0xc0, 0x3f, 0x6f, 0x35, 0x69, 0xbc, 0xeb, 0x70, 0x13, ++ 0xf3, 0x1d, 0x40, 0x37, 0xd3, 0xa6, 0x33, 0x3f, 0xeb, 0xd4, 0xe9, 0x46, ++ 0x2f, 0xf8, 0xed, 0xa7, 0x6a, 0x09, 0x8b, 0x6f, 0x69, 0xdd, 0x59, 0xdf, ++ 0xa1, 0xed, 0xdf, 0x99, 0xc5, 0xfc, 0xbb, 0x50, 0x9f, 0x15, 0xe6, 0x3f, ++ 0x11, 0xf1, 0x8c, 0xd3, 0xd4, 0x1e, 0xd9, 0x13, 0xc1, 0x9e, 0x3c, 0x18, ++ 0xc7, 0xe4, 0x93, 0xf8, 0xbe, 0x66, 0xbd, 0x5e, 0x11, 0x37, 0xda, 0x1f, ++ 0x67, 0xc2, 0xf6, 0xff, 0x88, 0x1b, 0xbd, 0x36, 0x0e, 0xf1, 0xdf, 0x9d, ++ 0x05, 0xf4, 0xf7, 0x70, 0x1c, 0xd7, 0xab, 0xfa, 0x90, 0x3e, 0xc0, 0x57, ++ 0xc2, 0xe8, 0x7e, 0x03, 0xbc, 0xd7, 0x5a, 0xfc, 0x4e, 0x57, 0x7c, 0x41, ++ 0xd9, 0xce, 0xf9, 0xc2, 0x54, 0xe7, 0x4f, 0x75, 0xa8, 0x8f, 0x73, 0xfe, ++ 0x20, 0xf8, 0xb0, 0x0b, 0xe8, 0x90, 0x7e, 0xe7, 0x97, 0x9c, 0x3a, 0x80, ++ 0xe7, 0x47, 0x25, 0x0c, 0xfe, 0xa7, 0x8a, 0x97, 0x22, 0x7f, 0x98, 0x46, ++ 0xdc, 0xf8, 0x9c, 0x22, 0x88, 0xce, 0x15, 0xee, 0x37, 0x1a, 0x1b, 0xa6, ++ 0xc7, 0xd0, 0x71, 0xa6, 0xba, 0x94, 0x7a, 0xcd, 0xb4, 0xe9, 0x6a, 0x3d, ++ 0x87, 0xe1, 0xab, 0x18, 0x77, 0x86, 0x5b, 0xd9, 0x3e, 0x59, 0xe8, 0xa9, ++ 0x63, 0x95, 0x7a, 0xea, 0xac, 0xef, 0xdf, 0xb4, 0xa2, 0xfc, 0x4d, 0x7a, ++ 0xb1, 0xea, 0x56, 0x26, 0xc6, 0x49, 0xd0, 0xde, 0xaf, 0xa1, 0xfb, 0xc4, ++ 0xe2, 0x24, 0x5a, 0x16, 0x37, 0x59, 0xaf, 0xf7, 0x82, 0xbe, 0x53, 0xd3, ++ 0xbc, 0xe2, 0x58, 0x02, 0xd0, 0xd1, 0x5a, 0xc2, 0xe9, 0x68, 0x8f, 0xb4, ++ 0x10, 0xe3, 0x38, 0x7b, 0xa4, 0x45, 0x61, 0xfa, 0x43, 0xf7, 0x4a, 0xaf, ++ 0x04, 0x7c, 0xbf, 0x37, 0x5d, 0x93, 0x1f, 0xf7, 0x35, 0x88, 0xf1, 0xa1, ++ 0xd3, 0x3a, 0xef, 0x61, 0x88, 0x9b, 0x9c, 0x5e, 0x4a, 0x57, 0x4c, 0xe7, ++ 0x79, 0x44, 0xcf, 0xe2, 0x8f, 0x47, 0xa3, 0x88, 0x07, 0xfc, 0xcf, 0x02, ++ 0x3f, 0xcd, 0x93, 0x99, 0xff, 0x94, 0xa2, 0x31, 0xc6, 0x41, 0xd2, 0x2c, ++ 0xd1, 0x0e, 0xd0, 0xcb, 0x37, 0x6a, 0x0a, 0xd0, 0xdf, 0xba, 0x31, 0xc6, ++ 0xec, 0x08, 0xf7, 0x6f, 0x6e, 0x5a, 0xe7, 0x2e, 0x0b, 0xf7, 0xb3, 0xda, ++ 0x0d, 0xa4, 0xc0, 0xc2, 0xf1, 0x26, 0x92, 0x1d, 0x7b, 0x8c, 0xf3, 0xc3, ++ 0xa7, 0x24, 0xe6, 0xef, 0xf6, 0xcc, 0x30, 0xa2, 0xdd, 0x96, 0xd0, 0xc3, ++ 0xa5, 0x88, 0x2f, 0x24, 0xc8, 0xe4, 0x2c, 0xf8, 0x0d, 0xd7, 0xc6, 0xd9, ++ 0x51, 0xde, 0x3e, 0xc5, 0xfd, 0x1a, 0x10, 0x9f, 0xeb, 0x4f, 0x4b, 0xaf, ++ 0x44, 0x05, 0x62, 0x7c, 0xd8, 0xf7, 0x32, 0x59, 0x8f, 0x7e, 0x46, 0x15, ++ 0xff, 0x49, 0x88, 0x73, 0xa0, 0x7f, 0x3f, 0x21, 0x36, 0x17, 0xfd, 0xf4, ++ 0xd3, 0x5b, 0xf2, 0x77, 0x22, 0xbf, 0x31, 0x45, 0x39, 0x7a, 0x49, 0xa1, ++ 0xfe, 0xa7, 0xbb, 0xb7, 0x6b, 0x17, 0x81, 0xfe, 0xd4, 0xb2, 0x5d, 0xbb, ++ 0xd0, 0x14, 0xc2, 0xbb, 0xb3, 0x02, 0x5f, 0xa3, 0x49, 0x34, 0xe0, 0x6b, ++ 0x87, 0xdf, 0x6e, 0xaf, 0x01, 0xfd, 0x76, 0xdf, 0xd5, 0xb8, 0xce, 0x01, ++ 0x5e, 0x56, 0xea, 0x7d, 0x79, 0x44, 0x89, 0xcf, 0xf8, 0xbc, 0x2b, 0x39, ++ 0xb6, 0x84, 0xe3, 0x8b, 0xae, 0xc4, 0x35, 0x63, 0x11, 0x9d, 0x4f, 0xfb, ++ 0x7b, 0x7a, 0xe6, 0xc7, 0x5a, 0x4b, 0x90, 0x5e, 0x5f, 0xdb, 0x6f, 0x45, ++ 0xbf, 0xa3, 0x76, 0x32, 0x41, 0x79, 0xb2, 0xbe, 0x98, 0x20, 0x3e, 0xb4, ++ 0x6f, 0x97, 0x50, 0x4f, 0xfe, 0xc2, 0x5a, 0x81, 0xfa, 0xfb, 0x7a, 0xa9, ++ 0x01, 0xe5, 0x44, 0x9b, 0x6d, 0x34, 0xee, 0xdf, 0x32, 0xd3, 0x51, 0xb4, ++ 0x4f, 0x2b, 0x9e, 0xd3, 0x9d, 0x0f, 0xd7, 0xbb, 0x96, 0xed, 0x54, 0xd6, ++ 0x97, 0x13, 0x3f, 0xda, 0xc7, 0x95, 0xaf, 0x74, 0xc2, 0x67, 0xe4, 0x5f, ++ 0x82, 0x3f, 0x56, 0x37, 0x29, 0xbf, 0x23, 0x3d, 0x95, 0xfc, 0x31, 0x9f, ++ 0xf3, 0xfd, 0x02, 0x97, 0xe3, 0xfe, 0x32, 0x98, 0xfa, 0x74, 0x47, 0x0f, ++ 0x66, 0x1f, 0x13, 0x9f, 0x81, 0xae, 0xa3, 0xe8, 0x5d, 0x3d, 0xf7, 0xf7, ++ 0xce, 0x62, 0x72, 0x93, 0xbc, 0x28, 0x81, 0xbe, 0xd5, 0x6e, 0xbe, 0x24, ++ 0x33, 0x3a, 0x67, 0xfc, 0xb8, 0x88, 0xf7, 0xa7, 0x96, 0x43, 0x45, 0x5c, ++ 0x9f, 0x1a, 0x41, 0xf9, 0x16, 0xd8, 0x91, 0x42, 0x3f, 0xa2, 0xef, 0x63, ++ 0xfd, 0xa8, 0xa6, 0x45, 0x4e, 0xd6, 0x84, 0xe6, 0x55, 0xc8, 0xbf, 0x13, ++ 0x7a, 0x99, 0xe0, 0xdb, 0x62, 0x5f, 0x8a, 0x07, 0x81, 0x2d, 0x4c, 0x48, ++ 0x46, 0x3c, 0xd7, 0x6f, 0xb2, 0x49, 0x36, 0xec, 0x2b, 0xed, 0x1f, 0xe9, ++ 0x81, 0x8e, 0xeb, 0xd1, 0xdb, 0xb0, 0x7f, 0x0f, 0xd8, 0x5f, 0x43, 0xf9, ++ 0x78, 0x74, 0xdf, 0x3d, 0x20, 0x67, 0x3d, 0x1a, 0xa3, 0x17, 0xf0, 0x68, ++ 0x83, 0x54, 0x8b, 0x7c, 0xda, 0x48, 0x38, 0xbf, 0x96, 0xdc, 0xf5, 0xf0, ++ 0xf1, 0x6f, 0x3c, 0x1e, 0xe4, 0xdb, 0x83, 0x49, 0xed, 0xfd, 0x13, 0xb2, ++ 0x80, 0x5f, 0xfb, 0xa3, 0x01, 0x1e, 0x14, 0x1f, 0xb2, 0xe3, 0xc3, 0xf0, ++ 0xa4, 0x9e, 0xf8, 0x32, 0xf6, 0x48, 0x0a, 0x7c, 0xc1, 0xf6, 0x56, 0xeb, ++ 0x3b, 0x11, 0xf1, 0x45, 0xc8, 0x17, 0xdf, 0x47, 0x4c, 0xbf, 0x18, 0x4f, ++ 0x57, 0x0c, 0xfd, 0x94, 0x41, 0xe0, 0x86, 0x96, 0x47, 0x25, 0x66, 0xcf, ++ 0x8d, 0x31, 0x3d, 0xa9, 0x85, 0xef, 0xdf, 0xd1, 0x8c, 0x43, 0x7c, 0x18, ++ 0x4b, 0xbc, 0x5a, 0x98, 0x5f, 0x99, 0x45, 0xb9, 0xcf, 0x63, 0x92, 0x95, ++ 0xf5, 0x71, 0xf6, 0x4e, 0x78, 0x20, 0xc3, 0xb8, 0x4e, 0x0e, 0xcf, 0xf1, ++ 0x7d, 0x94, 0xed, 0x4e, 0xc1, 0xd7, 0x88, 0x92, 0xaf, 0x65, 0x91, 0x9b, ++ 0xb8, 0xcf, 0xe4, 0xb1, 0xe3, 0xdf, 0x05, 0xfb, 0x3e, 0x7a, 0x0d, 0xe9, ++ 0x03, 0x7a, 0x07, 0xd5, 0x10, 0x91, 0xde, 0xd4, 0xfc, 0x60, 0x54, 0xbc, ++ 0x49, 0xa1, 0x1f, 0x85, 0xc5, 0x3d, 0x46, 0xc5, 0x27, 0x74, 0x8e, 0x7b, ++ 0xb4, 0x73, 0x3f, 0xee, 0x10, 0x12, 0x58, 0xfc, 0x8a, 0xd4, 0x19, 0x5f, ++ 0xda, 0x8e, 0xad, 0x91, 0x93, 0xc3, 0xf0, 0x4a, 0xe0, 0xf1, 0x1b, 0x3c, ++ 0x4f, 0x42, 0x7a, 0x93, 0xc7, 0x57, 0x0b, 0x99, 0x5f, 0x2f, 0x24, 0xe7, ++ 0x19, 0xbe, 0x0c, 0xe0, 0xb5, 0x21, 0x80, 0x6f, 0xf4, 0xfd, 0x45, 0x02, ++ 0x4f, 0x32, 0x49, 0x26, 0xe0, 0xc9, 0xf0, 0xe6, 0x28, 0x9f, 0x4c, 0xe1, ++ 0x9a, 0xcf, 0xfb, 0x19, 0x02, 0x78, 0x53, 0x10, 0x92, 0xe7, 0x3e, 0x8d, ++ 0xc9, 0xae, 0xcf, 0x06, 0xfc, 0x70, 0x6c, 0x94, 0xe5, 0xce, 0x7a, 0x7b, ++ 0xa2, 0xcd, 0x8e, 0x78, 0xd2, 0x5f, 0x23, 0xe4, 0xbb, 0x23, 0x8e, 0xa0, ++ 0x7c, 0x6f, 0xac, 0xd7, 0xc2, 0xfc, 0xf7, 0x0f, 0xec, 0xee, 0x36, 0x29, ++ 0xf0, 0x62, 0x29, 0xe2, 0x85, 0x44, 0xf1, 0x02, 0xe9, 0xaa, 0x93, 0x5c, ++ 0x54, 0xb6, 0xab, 0xf0, 0x46, 0xec, 0xdf, 0x09, 0xae, 0x2f, 0x8f, 0x21, ++ 0x9e, 0x9e, 0x30, 0x1e, 0x65, 0x63, 0x47, 0x41, 0x5f, 0xf6, 0x65, 0x31, ++ 0xbc, 0x29, 0x23, 0x4e, 0xc4, 0x93, 0xb7, 0xb3, 0xc7, 0xf1, 0xf8, 0xb3, ++ 0x5b, 0x8b, 0xfd, 0x10, 0xa5, 0x3c, 0x2c, 0x35, 0x2a, 0xf1, 0x40, 0x8d, ++ 0x57, 0x74, 0x44, 0x4d, 0xf8, 0xb8, 0x6a, 0x3c, 0xeb, 0x0a, 0x6f, 0x32, ++ 0x01, 0x6f, 0x84, 0x3c, 0x8c, 0xbb, 0x33, 0xde, 0x3c, 0xde, 0x35, 0xde, ++ 0x3c, 0x7e, 0x3b, 0xbc, 0x51, 0xe3, 0x8b, 0xe0, 0x27, 0x7b, 0xa2, 0x2c, ++ 0xa5, 0xa0, 0x97, 0xd6, 0x54, 0x48, 0xc8, 0x87, 0xfb, 0xbf, 0xd7, 0xb3, ++ 0x1e, 0xea, 0xbd, 0xab, 0xb2, 0x30, 0x8f, 0x65, 0x8f, 0xd5, 0x81, 0x7a, ++ 0x6b, 0x4d, 0x2d, 0x6b, 0x2f, 0xf4, 0x3b, 0x65, 0xc8, 0x73, 0xe9, 0xb1, ++ 0x9a, 0xb7, 0x67, 0xb9, 0x4a, 0xa1, 0x5e, 0xb3, 0x86, 0xc5, 0x1b, 0x8a, ++ 0x4e, 0xb3, 0x3c, 0x98, 0x9e, 0x6b, 0x59, 0x7b, 0xfe, 0xc3, 0xb5, 0x47, ++ 0xcc, 0x20, 0xdf, 0x3d, 0xec, 0xfb, 0x37, 0x2e, 0x6f, 0x90, 0x63, 0x68, ++ 0xbb, 0x77, 0x03, 0xff, 0xbe, 0xb8, 0xa1, 0x14, 0xea, 0x35, 0x1b, 0xd9, ++ 0xf7, 0x5f, 0x40, 0xbc, 0x88, 0xee, 0xef, 0x80, 0xb3, 0xde, 0x7a, 0x78, ++ 0x7e, 0xd7, 0xe6, 0x2c, 0x07, 0x33, 0x3f, 0x99, 0x3e, 0x3b, 0x92, 0xe3, ++ 0xe9, 0x1e, 0x69, 0xef, 0x11, 0xfc, 0xae, 0x81, 0x7d, 0xb7, 0xe4, 0xb8, ++ 0xb1, 0x1b, 0x41, 0x3d, 0x98, 0xe9, 0xad, 0x23, 0xf8, 0x3a, 0x47, 0x3e, ++ 0xc7, 0xd6, 0x19, 0xff, 0xd9, 0xbd, 0x63, 0xed, 0x14, 0x7f, 0x17, 0x05, ++ 0x3d, 0xa8, 0x37, 0x5d, 0xd4, 0x54, 0x0e, 0x40, 0x7e, 0xd3, 0x85, 0x9d, ++ 0x59, 0x2c, 0x35, 0xa4, 0x41, 0x49, 0xf1, 0x06, 0xf9, 0x8c, 0xd3, 0x48, ++ 0xf1, 0x3a, 0x9b, 0xc5, 0x13, 0x77, 0xd0, 0x21, 0xde, 0x8e, 0x67, 0x7a, ++ 0xa0, 0x88, 0xc3, 0x41, 0x5e, 0x40, 0x78, 0x1e, 0xc0, 0xdb, 0xf1, 0x4c, ++ 0xde, 0x8b, 0xf7, 0x12, 0x6d, 0x84, 0xc5, 0x8d, 0xb7, 0x99, 0xd1, 0xaf, ++ 0x2b, 0xe2, 0x84, 0xbe, 0xa7, 0x89, 0x04, 0x74, 0x06, 0x6b, 0xe4, 0xf2, ++ 0x3f, 0x62, 0xdc, 0x70, 0x4c, 0x8f, 0x5a, 0x8c, 0x17, 0x8e, 0xc9, 0x14, ++ 0xf1, 0xc2, 0x80, 0x76, 0x3e, 0x1d, 0x37, 0xff, 0xd6, 0x97, 0xa3, 0x23, ++ 0xf9, 0x51, 0xfe, 0x93, 0x8f, 0x7b, 0x89, 0xe7, 0x39, 0x88, 0xe7, 0x15, ++ 0xde, 0x2c, 0x0d, 0xe0, 0xc5, 0x1e, 0x40, 0x92, 0x54, 0x00, 0x52, 0xf5, ++ 0x6f, 0x41, 0x6f, 0xda, 0x03, 0x7e, 0x54, 0x26, 0x34, 0x3c, 0x64, 0x10, ++ 0xec, 0x2b, 0xab, 0x9f, 0x8b, 0x5f, 0xb6, 0x69, 0x23, 0x35, 0xd2, 0x97, ++ 0x68, 0x6a, 0xb5, 0x1e, 0x10, 0x32, 0x19, 0xd4, 0xfe, 0xa2, 0x5d, 0x4f, ++ 0xf2, 0x13, 0x5f, 0x6c, 0x4c, 0xe7, 0xf9, 0x8f, 0xd1, 0x12, 0x1f, 0xc8, ++ 0x27, 0xa2, 0x65, 0xf3, 0x5f, 0x5c, 0x4f, 0xe5, 0xa0, 0x14, 0xe2, 0x4b, ++ 0x53, 0x05, 0xdb, 0x19, 0xd6, 0x0b, 0xe9, 0x74, 0x0a, 0xdf, 0xa7, 0xcb, ++ 0xf1, 0x5c, 0xdf, 0xe8, 0x4f, 0xfa, 0x03, 0xbf, 0x99, 0xca, 0xf7, 0xed, ++ 0x3b, 0xc6, 0x5a, 0x1d, 0x93, 0x97, 0x0d, 0x3a, 0x15, 0xfd, 0x5f, 0x43, ++ 0xfa, 0x7f, 0xa6, 0x4b, 0xbd, 0x59, 0xd9, 0xae, 0xe2, 0x0f, 0x15, 0x7c, ++ 0xdc, 0xc5, 0x5c, 0x5f, 0x5e, 0x4a, 0x82, 0xa8, 0x17, 0x5c, 0x94, 0xbc, ++ 0x58, 0x5e, 0x7a, 0x86, 0xe9, 0xcb, 0xcb, 0x4d, 0xa7, 0x51, 0xaf, 0x68, ++ 0xdf, 0xc6, 0xf4, 0xc4, 0x4a, 0x12, 0x40, 0xbd, 0x43, 0xed, 0xf7, 0x5b, ++ 0xbe, 0x5b, 0x59, 0xaf, 0x6a, 0x54, 0xd6, 0x6b, 0x9a, 0x95, 0xf5, 0xf6, ++ 0x5c, 0x0f, 0x8e, 0xd3, 0xfe, 0x4c, 0xd5, 0x00, 0xf0, 0xbf, 0x55, 0x6c, ++ 0x7d, 0x0f, 0xfd, 0xbb, 0x15, 0x82, 0x4f, 0x78, 0x95, 0x7c, 0x82, 0x2a, ++ 0x48, 0x8c, 0x4f, 0x3c, 0x7d, 0x37, 0xfa, 0x6d, 0x34, 0x46, 0xca, 0x27, ++ 0x0a, 0x01, 0x5c, 0xdd, 0x30, 0x6f, 0xa4, 0x3f, 0x71, 0xc6, 0x01, 0x3f, ++ 0x00, 0x21, 0x7b, 0x8b, 0xd6, 0x1f, 0x83, 0x4f, 0x52, 0x68, 0x5d, 0xe3, ++ 0x8a, 0x49, 0x40, 0x3f, 0xd6, 0xd8, 0xb8, 0x0b, 0x62, 0x7c, 0x19, 0xe3, ++ 0xb2, 0xef, 0x39, 0xed, 0xa1, 0x7d, 0xe9, 0xb0, 0x0b, 0x55, 0x7c, 0x22, ++ 0x5f, 0xf8, 0x63, 0x7a, 0xda, 0xd0, 0x5f, 0x25, 0xf8, 0x46, 0x3e, 0x61, ++ 0x72, 0x42, 0xad, 0x17, 0xf5, 0x49, 0x50, 0xda, 0x39, 0x42, 0xaf, 0xc8, ++ 0x07, 0xbd, 0x82, 0xe2, 0x85, 0x5f, 0x63, 0xf2, 0x6a, 0x34, 0xe1, 0x7a, ++ 0x84, 0x17, 0xe9, 0x8f, 0xda, 0x8b, 0xe3, 0xa3, 0xb2, 0x01, 0x65, 0x5c, ++ 0x32, 0xd4, 0xfb, 0xcf, 0x28, 0x34, 0xf2, 0x7d, 0x27, 0xaa, 0x7d, 0xed, ++ 0x9b, 0x70, 0x7b, 0x7b, 0x49, 0xd9, 0xae, 0xda, 0x77, 0x61, 0xaf, 0x0c, ++ 0xe0, 0xfb, 0x3e, 0x83, 0xb8, 0xbb, 0xc3, 0x3e, 0x4c, 0x21, 0xae, 0x63, ++ 0x20, 0x17, 0x4e, 0x7d, 0x54, 0xa1, 0xb0, 0x93, 0x3e, 0xfa, 0xc3, 0x68, ++ 0xe1, 0x47, 0x41, 0x7b, 0xe9, 0x9b, 0xdb, 0x49, 0x4e, 0xf9, 0xdb, 0xd8, ++ 0x49, 0x1d, 0xfb, 0x1d, 0x45, 0xf5, 0x46, 0x5a, 0x96, 0x4e, 0x1e, 0xd7, ++ 0xeb, 0x67, 0x10, 0xdf, 0x6e, 0x8a, 0xc2, 0xbc, 0xcd, 0x1a, 0x89, 0xed, ++ 0x6f, 0xe2, 0x8c, 0xd3, 0x19, 0xe1, 0x7e, 0xc3, 0x53, 0x75, 0x24, 0x41, ++ 0x1b, 0x46, 0xef, 0xf5, 0xe3, 0x0c, 0x46, 0x88, 0xef, 0xd5, 0xeb, 0x98, ++ 0x1d, 0x31, 0x79, 0xfc, 0xc7, 0x03, 0xe6, 0x87, 0xf1, 0x8b, 0x17, 0x8c, ++ 0xc5, 0x2e, 0x80, 0xd7, 0x06, 0xc9, 0xff, 0xbd, 0x3f, 0x82, 0x5d, 0x71, ++ 0x52, 0x26, 0x98, 0x17, 0xd3, 0x92, 0x80, 0xfb, 0x7d, 0xbd, 0x81, 0x3e, ++ 0xa7, 0x78, 0x76, 0xfd, 0xb9, 0x7b, 0x1c, 0x1e, 0xfa, 0xf8, 0xaa, 0x8e, ++ 0xc5, 0x0b, 0xbf, 0x90, 0x6a, 0x17, 0x43, 0x2a, 0x93, 0x98, 0xc7, 0xe2, ++ 0x35, 0xbf, 0x8d, 0xd2, 0x52, 0xf9, 0x75, 0x25, 0xfa, 0x10, 0xc6, 0x83, ++ 0xcf, 0xe8, 0xdd, 0xb3, 0x01, 0xef, 0x96, 0xbd, 0xb3, 0x0f, 0xfd, 0x91, ++ 0x95, 0xa0, 0x77, 0xf7, 0x08, 0xf5, 0xdb, 0xb5, 0xdf, 0xd1, 0x83, 0x76, ++ 0x89, 0xfe, 0x2d, 0x26, 0x07, 0x83, 0x52, 0x37, 0x07, 0xe6, 0x25, 0x10, ++ 0x4f, 0x4e, 0x78, 0x9c, 0x68, 0x56, 0x22, 0xe3, 0xaf, 0x67, 0x6c, 0xae, ++ 0xa5, 0x30, 0x7f, 0x21, 0xe7, 0x84, 0xdf, 0xff, 0xdc, 0x8a, 0x31, 0xb1, ++ 0x20, 0x0a, 0xfe, 0x42, 0x9c, 0xb1, 0x10, 0x9f, 0x94, 0x28, 0x4c, 0xba, ++ 0xdb, 0x3a, 0x8f, 0x07, 0xf9, 0x00, 0xeb, 0xc3, 0xfc, 0xcc, 0xe7, 0xa2, ++ 0x94, 0xf1, 0x05, 0x51, 0x7e, 0x2f, 0x81, 0xf9, 0xbf, 0xf7, 0x01, 0x2d, ++ 0xd1, 0xf1, 0xd2, 0xac, 0xce, 0xef, 0xc3, 0xfa, 0x2e, 0x71, 0x7b, 0xef, ++ 0x12, 0x8f, 0x53, 0x5d, 0x8a, 0x61, 0x71, 0xab, 0x87, 0x13, 0x18, 0xff, ++ 0xdd, 0xc7, 0xbf, 0xdb, 0xca, 0xcb, 0x4b, 0x3c, 0xae, 0x75, 0xc9, 0xa6, ++ 0xb4, 0x13, 0xc5, 0x7b, 0xdb, 0xf8, 0x77, 0x17, 0xea, 0x8c, 0xc6, 0xf5, ++ 0x61, 0xfb, 0x68, 0x7f, 0xda, 0x50, 0xeb, 0xc5, 0x3c, 0x28, 0x9e, 0xf7, ++ 0xb1, 0x9a, 0x30, 0xbb, 0x68, 0xbf, 0x75, 0xfb, 0xa6, 0xb0, 0xf8, 0xc1, ++ 0xae, 0x84, 0xe2, 0x7d, 0x30, 0xaf, 0x84, 0x1e, 0x4e, 0x7d, 0x0a, 0xc0, ++ 0x6f, 0x3f, 0x93, 0xbb, 0x10, 0x47, 0x86, 0x78, 0xef, 0x30, 0x8b, 0xbb, ++ 0x01, 0xe0, 0x55, 0x6d, 0x27, 0x4e, 0x88, 0x97, 0x12, 0x7b, 0x40, 0x7f, ++ 0x3f, 0xc4, 0x0d, 0xc1, 0xce, 0x44, 0x7d, 0x81, 0xe1, 0x49, 0x7b, 0x14, ++ 0x2b, 0xc5, 0xbc, 0x76, 0x25, 0x94, 0xef, 0x43, 0x38, 0xaf, 0x08, 0x20, ++ 0xdf, 0xea, 0xa8, 0x97, 0x33, 0x7e, 0xb8, 0x2b, 0xc1, 0x85, 0xe3, 0xb6, ++ 0x4f, 0x15, 0xed, 0xbc, 0xfe, 0x04, 0xab, 0x13, 0xee, 0x2f, 0x10, 0xfe, ++ 0xeb, 0xae, 0xe2, 0x58, 0xea, 0xb8, 0x15, 0xcc, 0x18, 0xf5, 0xea, 0x28, ++ 0xc6, 0xb7, 0xd4, 0xf1, 0xea, 0xd9, 0x82, 0x6f, 0xf1, 0x78, 0xf5, 0x2c, ++ 0xce, 0x87, 0x66, 0xb7, 0x30, 0x7f, 0xf8, 0x1c, 0x23, 0xd9, 0xd0, 0x9d, ++ 0xb6, 0xcf, 0x6d, 0x49, 0x62, 0xf6, 0x61, 0x8c, 0x27, 0x47, 0x11, 0xaf, ++ 0xf6, 0x44, 0x7f, 0xa3, 0x3c, 0x05, 0x81, 0x9f, 0xed, 0xe9, 0xfe, 0x8e, ++ 0x38, 0xeb, 0xb6, 0xb0, 0x38, 0x6b, 0x15, 0x8f, 0xd3, 0x55, 0x89, 0xf5, ++ 0x35, 0x29, 0xd7, 0x77, 0x24, 0xa1, 0xcb, 0x38, 0xeb, 0x91, 0x84, 0x08, ++ 0x71, 0x56, 0x75, 0x3c, 0x7f, 0x1f, 0xc8, 0xf3, 0x9e, 0x21, 0x78, 0xae, ++ 0xb4, 0xb0, 0xf5, 0x97, 0xc9, 0x95, 0xa5, 0x7a, 0xe0, 0x0f, 0x0b, 0x09, ++ 0xe6, 0x7f, 0xaf, 0x3c, 0xb9, 0xa0, 0xde, 0x48, 0xeb, 0x2b, 0x1f, 0x03, ++ 0x4f, 0x1f, 0xf2, 0x21, 0xd4, 0x4f, 0xab, 0x38, 0xbc, 0xba, 0x9a, 0x5f, ++ 0x82, 0x4b, 0x43, 0xec, 0x0a, 0xbf, 0x70, 0x37, 0x62, 0x0f, 0xb3, 0x83, ++ 0x53, 0xdc, 0x36, 0x45, 0x1d, 0x35, 0xde, 0xb0, 0xfc, 0xc9, 0xee, 0x15, ++ 0xa9, 0x8a, 0xef, 0xd3, 0x6b, 0xb3, 0x15, 0xef, 0x67, 0xae, 0xb9, 0x5b, ++ 0xd1, 0x9e, 0xe5, 0x29, 0x50, 0xd4, 0x7b, 0x6c, 0x1c, 0xa2, 0x78, 0xbf, ++ 0x57, 0x43, 0x89, 0xa2, 0xde, 0x7b, 0xeb, 0xbd, 0x8a, 0xf7, 0xf3, 0x49, ++ 0x76, 0x2c, 0xfa, 0x8f, 0x4e, 0xc8, 0xe0, 0x1b, 0x21, 0x77, 0x79, 0x27, ++ 0x2b, 0xda, 0xef, 0xd9, 0xfd, 0x80, 0xe2, 0xfb, 0x2f, 0x48, 0xed, 0x53, ++ 0xc3, 0xe8, 0x7b, 0x4d, 0x51, 0x8c, 0xff, 0x13, 0x8f, 0xd3, 0xdf, 0x77, ++ 0x40, 0x28, 0x5f, 0x38, 0xb7, 0x71, 0xbe, 0xe2, 0xfb, 0x7a, 0xa9, 0x71, ++ 0x80, 0x8f, 0xbe, 0xbf, 0xd0, 0xcf, 0xfc, 0xeb, 0xfd, 0x9a, 0x97, 0x29, ++ 0xfa, 0xbb, 0x1a, 0x33, 0x9a, 0xd9, 0x0d, 0x3c, 0x4e, 0x58, 0x4b, 0xff, ++ 0x31, 0xfe, 0x6d, 0x97, 0x51, 0xff, 0x69, 0x96, 0xc8, 0x36, 0xa9, 0x73, ++ 0xdc, 0xb0, 0xa2, 0x65, 0xcb, 0x86, 0xee, 0x24, 0x52, 0xfc, 0x90, 0xc9, ++ 0xf5, 0x65, 0x54, 0xae, 0x83, 0xde, 0xa4, 0xd6, 0x2b, 0x0c, 0x89, 0x3c, ++ 0x8e, 0x94, 0x4a, 0x52, 0x6f, 0x85, 0xd1, 0x55, 0x08, 0x0f, 0x4c, 0xa8, ++ 0x77, 0x5d, 0x7f, 0x4e, 0x46, 0xff, 0x59, 0x3e, 0xc9, 0x79, 0x7a, 0x18, ++ 0xc2, 0x47, 0x47, 0xbc, 0xf6, 0xce, 0xfb, 0x75, 0x9d, 0x30, 0xbf, 0xce, ++ 0xf5, 0x57, 0xcc, 0x0e, 0xf0, 0x8f, 0x2d, 0x39, 0xb9, 0x00, 0xf1, 0xcf, ++ 0x90, 0xac, 0xc4, 0x83, 0x28, 0xbb, 0x12, 0x0f, 0xa2, 0xfb, 0x28, 0xf1, ++ 0xc0, 0xec, 0x50, 0xee, 0x7b, 0xec, 0x20, 0xe5, 0xbe, 0xab, 0xe1, 0x6c, ++ 0x75, 0x2a, 0xf1, 0x40, 0xc0, 0x51, 0xc0, 0x39, 0x6e, 0xac, 0x12, 0x2f, ++ 0x04, 0x7c, 0x07, 0xd1, 0x7f, 0x00, 0xdf, 0x02, 0x12, 0x3c, 0x8e, 0xf9, ++ 0xd1, 0x5e, 0xc9, 0xe1, 0x23, 0x11, 0xe2, 0xb2, 0xcd, 0xdb, 0x71, 0x1d, ++ 0x77, 0xd2, 0xd3, 0xf2, 0x55, 0xf0, 0xec, 0x7f, 0xd4, 0x59, 0x6f, 0x42, ++ 0x38, 0xb1, 0x7c, 0x29, 0xa1, 0x17, 0x19, 0xb8, 0x5e, 0xa2, 0xf6, 0x93, ++ 0x77, 0xf8, 0x57, 0x12, 0xb9, 0xde, 0xc3, 0xfb, 0x11, 0x7e, 0xed, 0x0d, ++ 0x92, 0x07, 0xf5, 0x9c, 0x8e, 0xf8, 0xd5, 0x20, 0x5f, 0x86, 0x2f, 0x0b, ++ 0xf4, 0x9d, 0x5a, 0xc2, 0xfc, 0x23, 0xae, 0xb2, 0xc4, 0xc8, 0x7e, 0x34, ++ 0x7c, 0xde, 0x95, 0x1f, 0x4d, 0xc0, 0x51, 0xe8, 0x31, 0xcb, 0x41, 0x8f, ++ 0xa1, 0xe3, 0x2c, 0x22, 0x6e, 0xe4, 0x4b, 0x17, 0xb8, 0x1e, 0xb3, 0xc4, ++ 0xf4, 0x24, 0xc6, 0x01, 0xaf, 0xfe, 0x81, 0xc1, 0xb7, 0x82, 0x78, 0x91, ++ 0x5f, 0x7f, 0xe3, 0xb8, 0x36, 0xd5, 0x0b, 0x49, 0x98, 0x7f, 0x51, 0x0d, ++ 0x47, 0xa9, 0x45, 0xf2, 0x99, 0x81, 0x0e, 0x38, 0xdf, 0x4e, 0x25, 0x2d, ++ 0x82, 0x6f, 0xbb, 0x31, 0xdf, 0x81, 0xa2, 0x9d, 0x71, 0x80, 0x22, 0x9e, ++ 0xa0, 0xd4, 0x3b, 0x89, 0x53, 0x0a, 0xe7, 0x4f, 0x42, 0x0f, 0x15, 0xe3, ++ 0x09, 0x78, 0x0a, 0xbe, 0x25, 0xc6, 0x33, 0x90, 0x5a, 0x39, 0x19, 0xe8, ++ 0x40, 0xc5, 0xc7, 0x48, 0x1f, 0x75, 0x3c, 0x43, 0xe9, 0xe7, 0x10, 0x7e, ++ 0x11, 0x1c, 0x2c, 0x2c, 0x6e, 0x31, 0xb0, 0x23, 0x1e, 0xc1, 0xec, 0xc2, ++ 0x90, 0x9f, 0x8b, 0xf9, 0x35, 0xe4, 0xcc, 0xac, 0x7a, 0x02, 0xfa, 0xb6, ++ 0x45, 0xf8, 0x31, 0xfc, 0x33, 0xe1, 0xb9, 0xf0, 0x63, 0xa8, 0xed, 0xf9, ++ 0x3b, 0xc5, 0x41, 0xef, 0xf7, 0x48, 0x81, 0x67, 0xb3, 0x3a, 0xc7, 0x3f, ++ 0x45, 0x3c, 0x95, 0x2e, 0xf3, 0xb3, 0x3f, 0xd2, 0x8f, 0x87, 0x49, 0xf6, ++ 0x74, 0x18, 0x6f, 0xf2, 0x1b, 0xbd, 0x13, 0x88, 0x26, 0x92, 0x1f, 0xce, ++ 0x71, 0xf6, 0x00, 0xed, 0x47, 0xd6, 0x04, 0xe3, 0xc2, 0xfd, 0x63, 0xc2, ++ 0x5f, 0xfd, 0xb6, 0x14, 0xc0, 0x79, 0x7f, 0x87, 0x38, 0x1f, 0x21, 0x61, ++ 0xfa, 0x42, 0x35, 0x69, 0x1c, 0x3d, 0x33, 0x0b, 0xfc, 0x9d, 0x54, 0x6e, ++ 0xc5, 0x40, 0xc9, 0xfc, 0x3c, 0xa4, 0x59, 0xad, 0x8f, 0xb2, 0xf8, 0xa1, ++ 0x86, 0xae, 0x04, 0xf0, 0x7b, 0x39, 0x09, 0x8b, 0x0f, 0x66, 0x85, 0xda, ++ 0xb1, 0x2e, 0x77, 0xae, 0x8b, 0xfc, 0x94, 0x3b, 0xc9, 0xf7, 0x5e, 0x49, ++ 0x16, 0x71, 0x2e, 0x25, 0x87, 0xb5, 0x33, 0xfe, 0x26, 0xec, 0xb5, 0xae, ++ 0xec, 0x23, 0x11, 0xbf, 0x3f, 0xa6, 0xa7, 0x30, 0x29, 0x08, 0xe5, 0xa3, ++ 0x34, 0x26, 0x72, 0x3f, 0x56, 0x1e, 0xc9, 0x83, 0xfe, 0x29, 0x5d, 0x35, ++ 0x25, 0x26, 0x80, 0x3d, 0x4e, 0xe9, 0x50, 0x0a, 0xa7, 0xbb, 0x8e, 0xfc, ++ 0x15, 0x6c, 0xef, 0x44, 0x77, 0xaa, 0xf5, 0x8b, 0xf8, 0xbd, 0x6c, 0x2e, ++ 0x44, 0x3f, 0xcb, 0x82, 0xf0, 0xf5, 0x7e, 0x0d, 0x78, 0x08, 0x3d, 0xe2, ++ 0x06, 0x5d, 0x1b, 0xac, 0xf7, 0x47, 0x89, 0x76, 0x2c, 0xab, 0xba, 0x9d, ++ 0xfb, 0xd0, 0x09, 0xcd, 0x85, 0x7e, 0x45, 0x1e, 0x62, 0x8d, 0x9e, 0xe5, ++ 0xfd, 0x92, 0x46, 0xa5, 0xfe, 0x7c, 0x36, 0x51, 0xc4, 0x59, 0x99, 0x9d, ++ 0x71, 0x27, 0x38, 0x75, 0xbd, 0x0f, 0x3c, 0x9f, 0x8b, 0xef, 0xc3, 0xd7, ++ 0xd5, 0x87, 0x44, 0x3e, 0x97, 0x80, 0xdf, 0x27, 0x82, 0x0f, 0x86, 0xe0, ++ 0x7d, 0x5e, 0x01, 0xcf, 0x0e, 0x7b, 0xad, 0x03, 0xde, 0xe7, 0x23, 0xc1, ++ 0x5b, 0xc0, 0xe3, 0x5a, 0x91, 0xff, 0x45, 0xd8, 0x27, 0xd9, 0x7c, 0x3a, ++ 0x11, 0xe0, 0x9c, 0x14, 0xe3, 0xfa, 0x02, 0xf8, 0x62, 0xfa, 0xd9, 0xc0, ++ 0x45, 0x49, 0x13, 0x9a, 0x57, 0x99, 0xdc, 0x8a, 0x79, 0x9c, 0xd7, 0x9b, ++ 0x65, 0xb4, 0x8f, 0xaa, 0x87, 0xb3, 0x7c, 0x9e, 0xea, 0xfd, 0x18, 0x24, ++ 0x27, 0x6d, 0x2d, 0x06, 0x8c, 0x03, 0x56, 0x34, 0x1f, 0x41, 0xfd, 0xac, ++ 0xb5, 0x8e, 0x32, 0xd2, 0x9e, 0x5d, 0xc3, 0xa9, 0x63, 0xbd, 0x2a, 0x78, ++ 0x77, 0x65, 0xaf, 0x88, 0xf5, 0xdc, 0x52, 0xad, 0x5f, 0xe4, 0x87, 0x40, ++ 0x7c, 0x3f, 0xa9, 0xe8, 0xb6, 0x70, 0x50, 0xb6, 0x73, 0x38, 0x88, 0x7c, ++ 0x96, 0x32, 0xb9, 0x6f, 0x6c, 0x20, 0xcc, 0x2e, 0xf1, 0xf1, 0x7d, 0x8f, ++ 0xd2, 0xba, 0xa2, 0x92, 0xe8, 0xf8, 0x85, 0xbf, 0x4b, 0x8b, 0x01, 0xf8, ++ 0x94, 0xc9, 0x2d, 0xc7, 0x53, 0x01, 0x0e, 0xab, 0x25, 0x3c, 0x67, 0x34, ++ 0xd2, 0x40, 0x3c, 0xe0, 0xdf, 0x4f, 0xe1, 0xe7, 0xcd, 0x06, 0x05, 0x6a, ++ 0x1d, 0x16, 0x0a, 0x8f, 0xe4, 0x34, 0x13, 0x9e, 0x1b, 0xea, 0xfd, 0x5d, ++ 0xd9, 0x05, 0xf1, 0xcb, 0x8f, 0x57, 0xaf, 0xb2, 0xc1, 0xb9, 0xa8, 0x2b, ++ 0x75, 0x74, 0x68, 0x6a, 0x77, 0xf4, 0x96, 0x34, 0x2e, 0xc4, 0x37, 0xb2, ++ 0xf7, 0x93, 0x1f, 0x14, 0x42, 0x5c, 0x6d, 0x16, 0xe6, 0x17, 0xcf, 0x36, ++ 0xb0, 0x78, 0x7f, 0xd6, 0xf7, 0xa2, 0x7d, 0x3d, 0x28, 0x9f, 0x78, 0x53, ++ 0x4f, 0x8c, 0x40, 0x6f, 0xba, 0xec, 0x5a, 0x3c, 0x57, 0x11, 0xb4, 0xca, ++ 0x68, 0x6f, 0xc4, 0xcb, 0x64, 0x14, 0xe0, 0x97, 0x80, 0x73, 0x7c, 0x34, ++ 0x5b, 0x87, 0x78, 0x5e, 0xfc, 0xf3, 0x9d, 0x12, 0xe4, 0x21, 0x89, 0xe7, ++ 0x23, 0xeb, 0x83, 0xfd, 0x57, 0xd2, 0xf2, 0x73, 0xd8, 0xf7, 0x84, 0xd0, ++ 0x3a, 0x47, 0x96, 0x06, 0xfb, 0xd7, 0x9a, 0x42, 0x70, 0x16, 0xf9, 0x7d, ++ 0x44, 0x1b, 0xcc, 0x98, 0x1c, 0x46, 0x1f, 0x47, 0x38, 0x3c, 0xaa, 0x13, ++ 0xf4, 0x1b, 0x40, 0x1e, 0xb6, 0x19, 0xb9, 0x1d, 0xc8, 0xed, 0x41, 0x62, ++ 0xd1, 0x22, 0x1f, 0x59, 0xcd, 0xe3, 0xeb, 0xe7, 0x7a, 0x11, 0xe2, 0xc7, ++ 0x7e, 0x7c, 0x66, 0xc8, 0xa7, 0xaa, 0x8e, 0x72, 0xc6, 0x0e, 0x04, 0xff, ++ 0x16, 0xe4, 0x0f, 0xd0, 0xe2, 0x2f, 0x16, 0x67, 0xac, 0x15, 0xd7, 0x6f, ++ 0x47, 0xbd, 0x79, 0x35, 0xd7, 0xaf, 0xda, 0x78, 0x7e, 0xf6, 0xea, 0x71, ++ 0x25, 0x49, 0x60, 0x4f, 0x25, 0xd4, 0x47, 0xce, 0x63, 0x1a, 0x9d, 0xc4, ++ 0xf4, 0xfc, 0x4a, 0x1e, 0xf7, 0x16, 0xcf, 0x2b, 0xb5, 0x3e, 0xcc, 0x47, ++ 0xaa, 0x84, 0x7c, 0xe1, 0xb0, 0xfc, 0xa8, 0x6f, 0x9a, 0x2f, 0x2c, 0xf2, ++ 0xc4, 0xbb, 0x84, 0x83, 0x55, 0x4b, 0xb4, 0x14, 0x0e, 0xd5, 0x12, 0x71, ++ 0xdd, 0xee, 0xbd, 0x03, 0xff, 0x23, 0x47, 0xb4, 0x77, 0xab, 0x92, 0x34, ++ 0xb7, 0xcd, 0x63, 0x5b, 0xc8, 0xd7, 0x27, 0xf2, 0xd3, 0xaa, 0x21, 0x3f, ++ 0x8d, 0x3e, 0x5a, 0xbd, 0xbf, 0x38, 0x89, 0x44, 0xe8, 0xaf, 0x43, 0xde, ++ 0xdc, 0x18, 0xa2, 0xc8, 0x0b, 0x13, 0xf9, 0xcd, 0xd5, 0x37, 0x46, 0x60, ++ 0x5e, 0x58, 0xe9, 0xa3, 0xad, 0x78, 0xbe, 0x0f, 0xfa, 0xb1, 0x9b, 0x42, ++ 0x79, 0x69, 0x5d, 0xc1, 0xf9, 0x48, 0x22, 0x9b, 0x47, 0x35, 0xe4, 0x8b, ++ 0xf5, 0x0f, 0x7f, 0xce, 0xf8, 0x47, 0xa8, 0xff, 0x78, 0xdc, 0x87, 0x5f, ++ 0x02, 0x00, 0xc1, 0xcf, 0xd1, 0x2c, 0xa3, 0x1f, 0xf6, 0x97, 0x27, 0x34, ++ 0x63, 0x77, 0x44, 0x98, 0xef, 0x16, 0xbe, 0xfe, 0xbb, 0x13, 0xb4, 0x48, ++ 0x1f, 0xf7, 0xf8, 0x88, 0x73, 0x7b, 0x84, 0xf1, 0xc5, 0x7b, 0xe2, 0xfc, ++ 0x07, 0xc0, 0xb9, 0x3c, 0xb7, 0xf3, 0xfc, 0x9a, 0x4a, 0x02, 0x73, 0x60, ++ 0xfe, 0x90, 0x77, 0x1a, 0x69, 0xbc, 0xf5, 0x49, 0xcc, 0xce, 0x16, 0xf3, ++ 0x6e, 0xb2, 0x05, 0x16, 0x73, 0x3c, 0xc7, 0xf3, 0x17, 0x1d, 0x75, 0x8b, ++ 0x72, 0x1f, 0x5f, 0xe0, 0xfb, 0xd8, 0x74, 0x6f, 0x20, 0x03, 0xcf, 0x11, ++ 0x8d, 0x8b, 0x9c, 0x07, 0x2f, 0xf6, 0xfb, 0xa6, 0xd9, 0xfd, 0x26, 0xf0, ++ 0xdb, 0xca, 0x69, 0xf4, 0x65, 0xf0, 0xb3, 0x6b, 0x6b, 0x25, 0x4b, 0x18, ++ 0x7d, 0x75, 0xb5, 0xdf, 0x21, 0x38, 0x6b, 0x14, 0xf9, 0x7f, 0x9d, 0xe1, ++ 0xac, 0xc7, 0xfd, 0x15, 0xfd, 0x09, 0x7b, 0xe4, 0xf2, 0x56, 0x19, 0xe3, ++ 0xfb, 0x97, 0x4f, 0x71, 0x7a, 0x24, 0x4e, 0x93, 0x44, 0xe9, 0x6a, 0x1e, ++ 0x97, 0x57, 0x97, 0x09, 0x8b, 0x13, 0x5c, 0x6e, 0x90, 0xd0, 0x0e, 0x99, ++ 0xef, 0x26, 0x64, 0x0d, 0xe5, 0x2b, 0xf3, 0x76, 0x2e, 0xc7, 0x38, 0xcd, ++ 0xe2, 0x5d, 0xfd, 0x37, 0x80, 0x98, 0x82, 0xe7, 0x6b, 0x29, 0xff, 0x98, ++ 0x97, 0x4c, 0xc8, 0x08, 0x5a, 0xce, 0x5f, 0xaf, 0x8c, 0xd3, 0x2e, 0xdc, ++ 0xdc, 0xc9, 0xff, 0x46, 0xc2, 0xe5, 0x22, 0x55, 0x3b, 0xd1, 0xae, 0x5e, ++ 0xfc, 0xa4, 0xf2, 0xbb, 0x0a, 0xb2, 0xf9, 0xcf, 0xa0, 0xf7, 0x54, 0xa8, ++ 0xf4, 0x9a, 0xde, 0xdc, 0xbf, 0xb5, 0x2f, 0x89, 0xda, 0x09, 0xa0, 0xd7, ++ 0x0d, 0x20, 0x03, 0x80, 0xaf, 0xaf, 0xdc, 0xf5, 0xa5, 0x1e, 0x52, 0x6d, ++ 0xbb, 0xc2, 0xf3, 0x2b, 0x94, 0x9e, 0x7b, 0x6a, 0x81, 0xff, 0x59, 0xb0, ++ 0x3c, 0x91, 0xe4, 0x3c, 0x08, 0xfc, 0xfd, 0xf7, 0x49, 0x6e, 0x1f, 0x94, ++ 0xed, 0x1f, 0x30, 0x38, 0x5c, 0xaf, 0xbc, 0xce, 0xf8, 0xfd, 0x73, 0xf1, ++ 0x28, 0x67, 0x0c, 0xc0, 0x94, 0xe9, 0xff, 0x1a, 0x66, 0xb2, 0x78, 0xeb, ++ 0xa3, 0x94, 0x4d, 0x40, 0x9c, 0xcd, 0x60, 0x60, 0x7a, 0x8d, 0xd0, 0xe7, ++ 0x64, 0x79, 0x95, 0x1c, 0x43, 0xdb, 0x07, 0x7f, 0xbe, 0xda, 0x06, 0xfe, ++ 0xbf, 0xf8, 0x97, 0xc7, 0x8c, 0x05, 0x7d, 0x3f, 0xe1, 0xe5, 0x68, 0x27, ++ 0xc0, 0x6b, 0x53, 0xb1, 0x33, 0x1f, 0xec, 0xff, 0x4d, 0xe5, 0x26, 0xcc, ++ 0x5b, 0x30, 0x1a, 0x58, 0x9c, 0xd7, 0xfb, 0xcb, 0xc1, 0x6f, 0x81, 0xdb, ++ 0xbf, 0x67, 0xe3, 0x96, 0x12, 0xb0, 0x3f, 0x2d, 0x2d, 0x87, 0x7d, 0xe0, ++ 0x1f, 0xd9, 0xa8, 0xf9, 0x33, 0x9e, 0x1b, 0xd9, 0x38, 0x82, 0xe5, 0xb5, ++ 0x75, 0xe4, 0x4f, 0xb6, 0x94, 0xef, 0x81, 0xf9, 0x64, 0x4c, 0x61, 0xf2, ++ 0x62, 0x53, 0x96, 0x33, 0xdf, 0x12, 0xd6, 0x2f, 0xe1, 0xfa, 0x59, 0x35, ++ 0x87, 0x59, 0xfb, 0xc1, 0xde, 0x3f, 0x86, 0xf3, 0xea, 0xcf, 0x9e, 0x40, ++ 0xf5, 0x98, 0xae, 0x2f, 0x1b, 0xfd, 0x70, 0x77, 0x13, 0xb6, 0x9f, 0x22, ++ 0x7f, 0x0a, 0xc6, 0x0e, 0xd7, 0x43, 0x5b, 0xa9, 0xdc, 0x81, 0x24, 0x3c, ++ 0x51, 0xbf, 0xbb, 0x51, 0xf2, 0xe9, 0xe8, 0x7a, 0xaa, 0x9a, 0xf6, 0x60, ++ 0xbc, 0xa2, 0xf2, 0x61, 0x5f, 0xe2, 0x4c, 0x90, 0x2f, 0x2f, 0x69, 0x31, ++ 0xde, 0x23, 0xe6, 0x17, 0xff, 0x66, 0x4a, 0x09, 0xc4, 0x75, 0x84, 0x5c, ++ 0x99, 0x29, 0x59, 0x98, 0x9f, 0x91, 0xeb, 0xd9, 0x33, 0x88, 0xf8, 0x63, ++ 0x71, 0xa1, 0xe9, 0x1c, 0x0f, 0x66, 0x70, 0xfd, 0x7a, 0x66, 0x34, 0x83, ++ 0xef, 0x7c, 0xe2, 0xc8, 0x80, 0xef, 0x1e, 0x30, 0x92, 0x18, 0xf0, 0x4f, ++ 0xcf, 0x2c, 0x6d, 0x2c, 0x42, 0xb9, 0xb3, 0x5c, 0x67, 0x05, 0x79, 0x2e, ++ 0xe2, 0x1b, 0x5d, 0xeb, 0x01, 0x91, 0xfd, 0x44, 0xd5, 0x2f, 0x9a, 0xd9, ++ 0xf9, 0x57, 0x29, 0x98, 0x03, 0x9d, 0x5c, 0xa1, 0x76, 0x07, 0x61, 0xfe, ++ 0xa2, 0x88, 0x79, 0xbf, 0xe6, 0x64, 0x4e, 0x67, 0x39, 0x5c, 0xdf, 0xeb, ++ 0x49, 0x9c, 0x10, 0x4f, 0xab, 0x3e, 0xd4, 0x7b, 0x3b, 0xf8, 0x03, 0x0c, ++ 0xdd, 0x58, 0xdc, 0x95, 0xf2, 0x1b, 0xe3, 0xa0, 0x02, 0xd4, 0x77, 0x8d, ++ 0x60, 0xc7, 0x2c, 0x3d, 0x10, 0xe5, 0x63, 0x7e, 0x6a, 0x2f, 0x3f, 0xe7, ++ 0xea, 0xcc, 0x87, 0xfc, 0x8f, 0x9a, 0xc9, 0x69, 0x05, 0x98, 0x87, 0x70, ++ 0x96, 0xf2, 0x0d, 0x33, 0x9c, 0x1f, 0x0c, 0x64, 0x20, 0x9d, 0x52, 0x7e, ++ 0x22, 0x51, 0x99, 0x96, 0x93, 0x6c, 0x9e, 0xa0, 0x85, 0x73, 0x7e, 0xa9, ++ 0x54, 0x9f, 0xa2, 0xf5, 0x29, 0x5b, 0x53, 0x27, 0x68, 0x29, 0xbe, 0x57, ++ 0x67, 0x07, 0x16, 0x6b, 0x68, 0x7d, 0x6d, 0x72, 0x21, 0x6b, 0xbf, 0x3b, ++ 0x70, 0x11, 0xea, 0x1b, 0x92, 0x47, 0xb2, 0xf6, 0x82, 0xc0, 0x62, 0x99, ++ 0xd6, 0xb7, 0x27, 0x4f, 0x64, 0x75, 0x30, 0xec, 0x28, 0x62, 0xfd, 0x3a, ++ 0x79, 0xca, 0x04, 0x0f, 0xed, 0xff, 0x8a, 0x95, 0xcb, 0x69, 0x47, 0x00, ++ 0xcf, 0xfd, 0x56, 0xbf, 0xd1, 0x5b, 0x13, 0xee, 0xa7, 0xdc, 0x06, 0xc9, ++ 0x0b, 0x14, 0x3e, 0x57, 0xb8, 0xbf, 0xf5, 0x4a, 0x16, 0x99, 0x3b, 0x19, ++ 0xe0, 0xdd, 0x27, 0x80, 0xe7, 0xca, 0xc4, 0x7b, 0xff, 0x87, 0xbf, 0x27, ++ 0xf2, 0x7d, 0xc5, 0x3a, 0xc5, 0x77, 0x24, 0x39, 0x72, 0xff, 0x45, 0xfc, ++ 0xbb, 0xa5, 0xfc, 0xbc, 0xee, 0xc8, 0x68, 0xb2, 0x31, 0x8a, 0xc5, 0xa5, ++ 0x3c, 0x31, 0x14, 0xfe, 0x47, 0x5b, 0x7a, 0x63, 0x5c, 0x2d, 0x35, 0xd9, ++ 0xc6, 0xfa, 0xb7, 0xd0, 0x7e, 0x0a, 0x43, 0xfd, 0x08, 0x38, 0x8a, 0xfe, ++ 0xc4, 0xb8, 0xcb, 0x40, 0x9e, 0x02, 0x9f, 0xd5, 0x31, 0x7f, 0xa9, 0x68, ++ 0x2f, 0x49, 0x66, 0xfc, 0x9b, 0x8e, 0xb3, 0x1e, 0xc7, 0xe9, 0xe9, 0x64, ++ 0xe7, 0x50, 0x27, 0xa7, 0xe5, 0xc3, 0xbe, 0xd1, 0xfd, 0xd2, 0xf2, 0xfd, ++ 0xd2, 0x32, 0xbb, 0x73, 0x3b, 0x9b, 0x1f, 0xed, 0xd7, 0x9a, 0x87, 0x7c, ++ 0xbd, 0x3f, 0xf8, 0xbb, 0x8f, 0xde, 0xa4, 0xef, 0x67, 0x85, 0xe6, 0xad, ++ 0xc6, 0x8f, 0xfb, 0x38, 0x7e, 0x2c, 0xad, 0x67, 0xf1, 0xc4, 0xa0, 0xb5, ++ 0x07, 0xe2, 0xd1, 0xc8, 0x68, 0xa6, 0xe7, 0x91, 0x42, 0xe5, 0x3a, 0xb6, ++ 0x27, 0x33, 0xbe, 0xbf, 0x2d, 0xd9, 0xca, 0xf0, 0xa2, 0x63, 0x3f, 0x92, ++ 0x24, 0x1c, 0xa7, 0x9e, 0xc3, 0x31, 0x8d, 0xc2, 0x3d, 0xf7, 0x9b, 0xaf, ++ 0x7b, 0x1e, 0x9f, 0xcf, 0x3f, 0x7b, 0xdd, 0x61, 0xfb, 0xe5, 0x84, 0xfc, ++ 0xbe, 0xa3, 0xcd, 0x77, 0xed, 0x08, 0x5f, 0x8f, 0xc8, 0xcf, 0x16, 0xfd, ++ 0x5c, 0x59, 0xa7, 0xfa, 0x6e, 0x10, 0xcb, 0x93, 0xaa, 0xb6, 0xf5, 0xc0, ++ 0xef, 0x1e, 0x8d, 0x22, 0x46, 0x7c, 0x4e, 0x76, 0x74, 0x7c, 0x97, 0x95, ++ 0xc7, 0xf4, 0x4b, 0xd0, 0x3b, 0xc5, 0x7d, 0x0c, 0xc4, 0x33, 0x02, 0x9d, ++ 0x04, 0x95, 0x9c, 0x6b, 0x74, 0xdc, 0xaf, 0xd0, 0xc8, 0xf3, 0x05, 0x3b, ++ 0xd6, 0x37, 0xa1, 0x90, 0xaf, 0xcf, 0xc2, 0xd7, 0x67, 0x31, 0x86, 0xdd, ++ 0xab, 0xd0, 0x41, 0x8f, 0xa7, 0x83, 0x19, 0x53, 0xcc, 0x9d, 0xf1, 0xb7, ++ 0x03, 0xee, 0x1d, 0xfd, 0xf5, 0x2d, 0xe0, 0xfd, 0x29, 0xe8, 0x3a, 0x52, ++ 0x7f, 0x40, 0x1f, 0x5d, 0xed, 0xc7, 0x4f, 0xff, 0xd9, 0x78, 0x28, 0xe6, ++ 0xa9, 0x82, 0x67, 0x07, 0x9c, 0x55, 0xf3, 0x13, 0xf0, 0x04, 0x7a, 0xc6, ++ 0xef, 0xfa, 0x2a, 0xf1, 0x51, 0xcc, 0x73, 0x43, 0xc7, 0x3e, 0xaa, 0xe8, ++ 0x3a, 0xeb, 0x5b, 0x8e, 0x57, 0xcc, 0xbe, 0xab, 0x7a, 0x90, 0xe7, 0xfd, ++ 0xda, 0x95, 0xf8, 0x5c, 0xd5, 0x94, 0xa5, 0x81, 0x78, 0xb9, 0xf8, 0x6e, ++ 0x2c, 0xf8, 0xd8, 0x13, 0x42, 0xfe, 0xb6, 0x7d, 0xc9, 0xdc, 0x6e, 0x4b, ++ 0x23, 0x69, 0x5d, 0xe4, 0xbb, 0xbd, 0x91, 0x9c, 0x10, 0xd1, 0x4f, 0x87, ++ 0xcf, 0xd5, 0x76, 0x5b, 0xbb, 0x95, 0xe5, 0x39, 0xab, 0xfd, 0x06, 0xed, ++ 0x09, 0x0e, 0x3f, 0x9c, 0xc3, 0xf3, 0x5c, 0x63, 0xe7, 0xcf, 0x87, 0xaa, ++ 0xf4, 0x0d, 0x88, 0xbf, 0xec, 0x35, 0x85, 0xbe, 0x0b, 0xc9, 0x13, 0x65, ++ 0xdd, 0x90, 0xc2, 0xf8, 0x5b, 0x67, 0x3f, 0x50, 0x10, 0xcf, 0xcb, 0x16, ++ 0x1a, 0x4a, 0x5e, 0xb3, 0x3b, 0x28, 0xba, 0x24, 0x2f, 0x43, 0xfe, 0x5d, ++ 0x18, 0x5b, 0xb2, 0x2a, 0x8b, 0xd6, 0x3f, 0x4a, 0xae, 0x44, 0x7e, 0x5d, ++ 0xd8, 0xbd, 0xe4, 0xcb, 0x2c, 0xca, 0xbf, 0xff, 0x98, 0x5c, 0xc5, 0xea, ++ 0xf7, 0x94, 0x7c, 0x99, 0x0d, 0xf5, 0xad, 0x55, 0xec, 0xfd, 0x91, 0xce, ++ 0xd7, 0x80, 0xbf, 0x13, 0x4f, 0xd5, 0x84, 0x51, 0x29, 0x21, 0xfd, 0xe1, ++ 0x5c, 0xb2, 0x9d, 0xe9, 0x1f, 0xa5, 0x1a, 0x02, 0x78, 0x64, 0x90, 0x57, ++ 0x38, 0x40, 0x4e, 0x0a, 0x78, 0x76, 0x55, 0x16, 0x1a, 0x34, 0xb5, 0x11, ++ 0xcf, 0xb5, 0x76, 0xe0, 0x01, 0x8b, 0x4f, 0x0c, 0xe2, 0xf2, 0x79, 0x90, ++ 0xb0, 0xcb, 0x03, 0x5a, 0x85, 0x5d, 0xde, 0x1e, 0xc3, 0xce, 0x13, 0xb7, ++ 0x83, 0x3c, 0xa5, 0xeb, 0x0d, 0x26, 0xbb, 0xaf, 0x00, 0xfc, 0x6b, 0xa2, ++ 0x5b, 0xe7, 0x64, 0xd1, 0xae, 0x1e, 0x8e, 0xfe, 0x44, 0x0f, 0xfa, 0x90, ++ 0xe4, 0xa4, 0xfa, 0x06, 0xf8, 0x39, 0xec, 0x16, 0x32, 0x0b, 0xf2, 0xe7, ++ 0x5a, 0x37, 0xb9, 0x40, 0x3f, 0x22, 0xcb, 0x1c, 0x46, 0x2d, 0xc2, 0x93, ++ 0xfb, 0x9d, 0xe8, 0xda, 0x6e, 0xd1, 0x7e, 0x0e, 0x1c, 0x7a, 0xe9, 0xa1, ++ 0xee, 0x6c, 0x18, 0x17, 0xcc, 0x63, 0x30, 0xa7, 0xff, 0x9a, 0x43, 0x7f, ++ 0xff, 0x0a, 0xe2, 0xa2, 0x35, 0x57, 0x4c, 0x0e, 0x50, 0xff, 0x06, 0xb7, ++ 0x3c, 0xb3, 0x0a, 0xf4, 0xab, 0xc1, 0x2d, 0xef, 0xfc, 0x9d, 0xc9, 0x5b, ++ 0x76, 0x2e, 0x43, 0xcc, 0x7b, 0x30, 0xf8, 0x0f, 0xe9, 0xf3, 0x41, 0xcd, ++ 0x06, 0x9c, 0xff, 0xe0, 0x96, 0xbb, 0x16, 0xc1, 0xfb, 0x43, 0x7f, 0xd7, ++ 0xd2, 0x03, 0xf0, 0x63, 0xf8, 0x39, 0x5f, 0x3d, 0xb0, 0x83, 0xf6, 0x83, ++ 0xbf, 0xe9, 0xae, 0x38, 0x8f, 0x41, 0xbe, 0x90, 0xbe, 0xcd, 0x79, 0x8c, ++ 0x0e, 0x78, 0x7c, 0x4e, 0x95, 0xa7, 0x58, 0x84, 0x87, 0x29, 0x05, 0xe1, ++ 0x71, 0x13, 0xf3, 0xa2, 0xda, 0x12, 0x4e, 0x6d, 0x08, 0xa0, 0x9e, 0xa6, ++ 0x3c, 0xf7, 0x42, 0xf5, 0x72, 0x8c, 0xaf, 0x5e, 0x27, 0xdd, 0x1c, 0x10, ++ 0x27, 0x10, 0xe7, 0xb4, 0xd5, 0xfe, 0xca, 0xb3, 0xe5, 0x74, 0x7d, 0xf4, ++ 0xf9, 0xf0, 0x20, 0x9d, 0x41, 0x98, 0xbe, 0x3c, 0xf2, 0x06, 0xb5, 0xeb, ++ 0xc3, 0xf4, 0xec, 0x62, 0x62, 0x55, 0xd4, 0x4b, 0x8d, 0x29, 0x8a, 0xf7, ++ 0xcb, 0x2c, 0x59, 0x8a, 0xf6, 0x31, 0xc9, 0x77, 0x29, 0xda, 0xc7, 0xd9, ++ 0xf3, 0x15, 0xf5, 0xf1, 0x7d, 0x06, 0x2b, 0xde, 0x9f, 0xe8, 0x28, 0x56, ++ 0xd4, 0xef, 0x1b, 0x34, 0x4e, 0xf1, 0x7e, 0xb9, 0xb3, 0x5c, 0x51, 0xcf, ++ 0xf7, 0x35, 0x2a, 0xde, 0xef, 0x7f, 0xa2, 0x59, 0xd9, 0x7e, 0xda, 0x8e, ++ 0xfb, 0xd0, 0xff, 0x9c, 0xab, 0x14, 0xf4, 0x78, 0x87, 0xdf, 0x5d, 0x0f, ++ 0xe5, 0xc0, 0xd6, 0x86, 0xd2, 0x58, 0x3b, 0xe9, 0xe4, 0xa7, 0x2d, 0x0c, ++ 0x78, 0xeb, 0xe1, 0xf9, 0xd0, 0x9b, 0xb5, 0x45, 0x3e, 0x12, 0xe1, 0xbc, ++ 0xca, 0x32, 0x37, 0xfa, 0xf7, 0x3b, 0x9d, 0x57, 0x29, 0x66, 0xe7, 0xd7, ++ 0xdb, 0x34, 0xec, 0xbc, 0x86, 0xf0, 0xcb, 0x0e, 0x36, 0xb9, 0x8b, 0x61, ++ 0x9f, 0xde, 0x96, 0x28, 0xd8, 0x29, 0xb0, 0x47, 0x18, 0x83, 0x71, 0xb0, ++ 0x5f, 0x65, 0x73, 0x9f, 0xc0, 0xfc, 0xa8, 0xeb, 0x41, 0x82, 0x7e, 0xac, ++ 0x26, 0x7d, 0xe0, 0x47, 0x43, 0x41, 0xce, 0xcf, 0x96, 0x51, 0xef, 0x6d, ++ 0xe2, 0x79, 0x35, 0x4d, 0xd3, 0x73, 0x31, 0xdf, 0xfd, 0xac, 0x14, 0xd8, ++ 0x07, 0xf1, 0x79, 0xcf, 0x6c, 0x76, 0x1e, 0x60, 0x38, 0xd5, 0x70, 0x71, ++ 0xdd, 0x10, 0xd3, 0x94, 0x60, 0x9f, 0xdc, 0x8a, 0x75, 0x17, 0x93, 0xa5, ++ 0xaa, 0x7d, 0x5a, 0xa1, 0xa8, 0x97, 0x59, 0x1e, 0x54, 0xbc, 0x3f, 0x26, ++ 0x79, 0x9d, 0xa2, 0x7d, 0x9c, 0xfd, 0x31, 0xd5, 0x3e, 0x6d, 0x51, 0xd4, ++ 0x27, 0x3a, 0x9e, 0x51, 0xed, 0xd3, 0x76, 0xd5, 0x3e, 0xbd, 0xa4, 0x68, ++ 0x1f, 0x7e, 0x21, 0x50, 0x0f, 0x64, 0x34, 0xb2, 0xd5, 0x23, 0x9b, 0xe9, ++ 0xfc, 0x87, 0x9c, 0x6d, 0x28, 0x85, 0x7d, 0x19, 0x7a, 0xce, 0x33, 0x1b, ++ 0xe8, 0xa5, 0xd0, 0xe7, 0xae, 0x07, 0x76, 0x58, 0x74, 0xb4, 0xf6, 0x08, ++ 0x94, 0x3e, 0x6a, 0x4f, 0x81, 0x7f, 0xea, 0xad, 0xba, 0x64, 0x2c, 0x8f, ++ 0xd6, 0xd9, 0xd1, 0xbf, 0x74, 0xbc, 0xae, 0x0f, 0x96, 0x27, 0xea, 0x1c, ++ 0xf8, 0xfc, 0xb7, 0x75, 0x83, 0xb0, 0x7c, 0xb7, 0xce, 0x89, 0xe5, 0x7f, ++ 0xd6, 0x8d, 0xc5, 0xd2, 0x5f, 0xe7, 0xc2, 0xb2, 0xb1, 0xae, 0x11, 0xdf, ++ 0xdf, 0x5b, 0xd7, 0x8c, 0x25, 0x85, 0x60, 0x3a, 0xc8, 0x8b, 0xf8, 0xb8, ++ 0x8e, 0x7b, 0x13, 0xd2, 0xc1, 0x8e, 0x6f, 0xd3, 0x04, 0xaa, 0x21, 0x82, ++ 0xfa, 0xfd, 0x67, 0x0e, 0x22, 0x5f, 0x6c, 0xeb, 0x16, 0x68, 0x83, 0xfa, ++ 0xc3, 0xa4, 0x65, 0xc2, 0x28, 0x5a, 0x9f, 0x0f, 0xc6, 0x14, 0xe8, 0x57, ++ 0x50, 0xd2, 0xfd, 0xf4, 0xa4, 0x3a, 0xff, 0x2b, 0x05, 0xf2, 0x29, 0x52, ++ 0xd8, 0x73, 0x91, 0x97, 0xd0, 0xa8, 0x71, 0xe6, 0x83, 0x7e, 0xfd, 0xf8, ++ 0x33, 0xc7, 0x36, 0x6b, 0xd3, 0x09, 0x79, 0x64, 0x9d, 0x2b, 0xd9, 0x62, ++ 0x65, 0x75, 0x23, 0xad, 0xe3, 0x66, 0x43, 0x1f, 0x9e, 0x63, 0x9b, 0x9d, ++ 0x69, 0x84, 0xfc, 0x0a, 0x44, 0xc6, 0x10, 0xac, 0x4f, 0x80, 0x7a, 0x7b, ++ 0x14, 0x6b, 0xdf, 0xf0, 0xcc, 0xb1, 0x09, 0x1e, 0x9c, 0x1f, 0x8b, 0x1f, ++ 0x4f, 0x09, 0xc5, 0x8f, 0x1f, 0x4f, 0x89, 0x10, 0x3f, 0xfe, 0xd5, 0x25, ++ 0xbb, 0x19, 0xfc, 0x28, 0xa7, 0x6e, 0xf6, 0x36, 0xc3, 0xba, 0x4e, 0x71, ++ 0xbf, 0x91, 0x93, 0xe4, 0xeb, 0xe6, 0xd1, 0xb2, 0x58, 0x9b, 0xaf, 0x03, ++ 0xb9, 0x78, 0x56, 0xa5, 0x47, 0x88, 0xb2, 0x46, 0x53, 0xfc, 0x24, 0xe0, ++ 0x69, 0xa3, 0xc6, 0x31, 0x15, 0xf3, 0x80, 0xef, 0xd5, 0x11, 0xc8, 0x3b, ++ 0x9f, 0x2c, 0x31, 0x7b, 0xb4, 0x43, 0x0f, 0x4c, 0x65, 0xf2, 0xa8, 0x7d, ++ 0xa2, 0x01, 0xed, 0x9d, 0xd3, 0x1a, 0xe7, 0x22, 0xcc, 0x6f, 0x92, 0x82, ++ 0xcf, 0x03, 0xbc, 0x5e, 0x49, 0xf9, 0x10, 0xe1, 0xd7, 0x6e, 0x0e, 0x66, ++ 0x00, 0x1c, 0x7e, 0x99, 0x72, 0x86, 0xd5, 0x13, 0x82, 0xcf, 0x4b, 0x8e, ++ 0xb0, 0xba, 0x8e, 0xad, 0xf3, 0x85, 0x94, 0xd3, 0x5d, 0xad, 0x73, 0x37, ++ 0xcc, 0xa7, 0xd3, 0x3a, 0x53, 0xd8, 0x7d, 0x31, 0xc4, 0xe7, 0x4c, 0x07, ++ 0xf9, 0x2b, 0xea, 0xa7, 0xcb, 0x9d, 0x55, 0x20, 0x27, 0x4e, 0x17, 0x3b, ++ 0x7b, 0xc1, 0x7c, 0x4e, 0xb9, 0x0c, 0x48, 0x3f, 0x1e, 0x97, 0xd9, 0x0b, ++ 0xf9, 0x95, 0x44, 0xeb, 0x2c, 0x9a, 0x1a, 0xe6, 0x4f, 0xe9, 0x9d, 0xaa, ++ 0xc3, 0xef, 0xa6, 0xe8, 0x19, 0x9d, 0x91, 0x07, 0xe4, 0x88, 0xe7, 0xc4, ++ 0xcb, 0x52, 0x99, 0x9e, 0x85, 0xfb, 0x06, 0xf6, 0xdc, 0x8c, 0x68, 0xd4, ++ 0xc3, 0x4f, 0x6b, 0x22, 0x9f, 0xf3, 0x9e, 0xcd, 0xe1, 0x73, 0xb5, 0x5b, ++ 0x64, 0xff, 0xca, 0x1c, 0xde, 0x5e, 0x72, 0xbf, 0x19, 0xfb, 0x6b, 0x5f, ++ 0x1d, 0x85, 0xf1, 0xdb, 0x76, 0x57, 0x6f, 0xd4, 0x83, 0xda, 0x6b, 0x29, ++ 0x94, 0x28, 0x7d, 0xb4, 0x5f, 0xaa, 0xbd, 0xf6, 0x3a, 0xb6, 0x1b, 0x44, ++ 0x68, 0x0b, 0xe3, 0x94, 0x33, 0x39, 0x9f, 0xfa, 0x55, 0xcb, 0xaa, 0xbf, ++ 0x9e, 0xa1, 0xef, 0x7f, 0xb2, 0x3a, 0xda, 0x81, 0x3c, 0xdc, 0x72, 0x37, ++ 0xca, 0xa7, 0x07, 0xf8, 0xcb, 0xb3, 0xe3, 0x8c, 0xa8, 0xb7, 0xcc, 0x9e, ++ 0x9c, 0x5e, 0x02, 0x72, 0x69, 0x26, 0x8f, 0x77, 0xcd, 0x31, 0x6b, 0x13, ++ 0x31, 0xec, 0xa5, 0xb5, 0xea, 0xe1, 0x0a, 0xa0, 0x85, 0xa6, 0xfc, 0x0d, ++ 0x20, 0xfe, 0x17, 0xc7, 0x97, 0xeb, 0xad, 0xb4, 0x5e, 0x91, 0xb6, 0x62, ++ 0x03, 0x94, 0xcb, 0x7a, 0x6e, 0xd1, 0xc3, 0x91, 0xcf, 0xca, 0xbe, 0x7b, ++ 0x36, 0x80, 0xfa, 0x58, 0x45, 0x49, 0xab, 0x08, 0xed, 0xa5, 0xc0, 0x7b, ++ 0x75, 0x74, 0x5e, 0x73, 0xd7, 0xc8, 0x76, 0x66, 0x3f, 0x89, 0x73, 0x86, ++ 0xcb, 0xbf, 0x51, 0x7e, 0x85, 0xc0, 0xc3, 0xd3, 0x3c, 0x4f, 0x86, 0xc2, ++ 0x17, 0xed, 0xc2, 0xb9, 0xa9, 0x92, 0xc2, 0x2e, 0x99, 0x9b, 0xca, 0xf4, ++ 0x86, 0x6b, 0x29, 0x5c, 0x6f, 0xcb, 0x25, 0xb9, 0xb7, 0x94, 0x71, 0x9c, ++ 0x3f, 0x03, 0x3d, 0xb4, 0xce, 0x7e, 0x2f, 0xa7, 0x0b, 0x7f, 0xbb, 0xb2, ++ 0x9d, 0xeb, 0x6d, 0x1f, 0xea, 0xd9, 0xb8, 0xea, 0x7b, 0x26, 0xc4, 0xb8, ++ 0x6e, 0x3e, 0x8f, 0xd3, 0x7a, 0xe2, 0x94, 0x40, 0x8f, 0x7b, 0xc0, 0x8c, ++ 0xf8, 0x91, 0x37, 0xfd, 0xcb, 0x87, 0x8b, 0xe8, 0xfa, 0xf3, 0x5a, 0x2c, ++ 0x1a, 0x8c, 0xc3, 0x0b, 0x3e, 0xee, 0x67, 0xf7, 0x7d, 0x15, 0x5d, 0x70, ++ 0x23, 0x9f, 0x1b, 0xd8, 0x1a, 0x78, 0xf1, 0x0c, 0x41, 0x3c, 0x6f, 0x06, ++ 0x3a, 0xb9, 0x93, 0x9c, 0xba, 0xdf, 0xb3, 0x0e, 0xe5, 0xc3, 0xe0, 0xbf, ++ 0x50, 0xf9, 0x03, 0x7c, 0xf1, 0xa6, 0xfb, 0x93, 0x33, 0xd8, 0x1a, 0x1f, ++ 0xf1, 0xfc, 0xa5, 0xaf, 0xae, 0x82, 0xf3, 0xc7, 0x5a, 0xe4, 0x6b, 0x47, ++ 0xeb, 0xd6, 0x60, 0xfd, 0x78, 0x9d, 0x07, 0xcb, 0x13, 0x75, 0x1b, 0x39, ++ 0x7f, 0x6c, 0xc0, 0xf6, 0x77, 0xeb, 0xb6, 0x72, 0xfe, 0xe8, 0xe5, 0xfc, ++ 0x71, 0x37, 0x3e, 0x6f, 0xa9, 0x9b, 0x8e, 0xe5, 0xa1, 0x3a, 0x37, 0x96, ++ 0x49, 0x31, 0xae, 0xc4, 0x54, 0xa0, 0x0b, 0xa3, 0x1b, 0xf3, 0x31, 0x8f, ++ 0x3d, 0x63, 0x20, 0x32, 0xc4, 0x19, 0x5a, 0x0c, 0x88, 0xa7, 0x94, 0x02, ++ 0x9e, 0x7f, 0x36, 0x1e, 0xf2, 0x5f, 0x0c, 0x16, 0x38, 0x67, 0xa7, 0xce, ++ 0x83, 0x51, 0xf3, 0xdb, 0x8e, 0xfd, 0x6f, 0xea, 0x74, 0x8f, 0x45, 0x76, ++ 0x6a, 0x51, 0x58, 0xde, 0x0b, 0xe8, 0x67, 0x99, 0x5d, 0xe3, 0xcf, 0x29, ++ 0x62, 0x37, 0x03, 0x3f, 0x19, 0xb2, 0x2d, 0x65, 0x22, 0xf0, 0x8f, 0x53, ++ 0x76, 0xbb, 0x19, 0xf4, 0xd6, 0xa1, 0xa9, 0xa9, 0xac, 0xee, 0xb4, 0x9b, ++ 0x75, 0xb4, 0x3e, 0x6c, 0x1b, 0xaf, 0xbb, 0xed, 0x66, 0x03, 0xad, 0x0f, ++ 0x4f, 0xed, 0x3e, 0x11, 0xf4, 0xde, 0x53, 0x1e, 0xbb, 0x39, 0x8a, 0xd6, ++ 0x47, 0x6c, 0xeb, 0xce, 0xda, 0xbd, 0x04, 0x83, 0xd4, 0xa5, 0xdb, 0xec, ++ 0x13, 0x81, 0xff, 0x14, 0x13, 0xe9, 0x28, 0xd0, 0x43, 0xa9, 0x31, 0x6b, ++ 0x14, 0xa4, 0xc8, 0x96, 0x59, 0x8a, 0x8f, 0x02, 0x1d, 0x8c, 0x49, 0x9e, ++ 0x37, 0x0a, 0xe8, 0x60, 0x6f, 0x8a, 0x1d, 0xf1, 0x61, 0x9c, 0x7d, 0xdd, ++ 0x51, 0xa8, 0x8f, 0xef, 0xb3, 0x5d, 0x0b, 0x47, 0x6b, 0x9c, 0xa6, 0xfc, ++ 0xf5, 0xf0, 0x5d, 0x49, 0x7c, 0xb9, 0x16, 0xbe, 0x1b, 0x95, 0xb6, 0x62, ++ 0x3d, 0x7c, 0x37, 0xba, 0xe7, 0x16, 0x6d, 0xf8, 0x77, 0x63, 0xfb, 0xee, ++ 0x59, 0x0f, 0xf5, 0x09, 0x8e, 0xed, 0x5a, 0xd0, 0x07, 0xf7, 0xa6, 0xb0, ++ 0xf8, 0xa7, 0xe8, 0x47, 0xd4, 0x45, 0xbb, 0xe0, 0xaf, 0x22, 0x4f, 0xab, ++ 0x5f, 0x8b, 0x0b, 0xf9, 0x78, 0x5e, 0xb3, 0x0b, 0xf9, 0x78, 0x87, 0x3f, ++ 0x62, 0x4a, 0xf9, 0x23, 0xe0, 0xa7, 0xab, 0x69, 0x96, 0x2c, 0x12, 0xcc, ++ 0x63, 0x8a, 0xd4, 0x11, 0x7c, 0x87, 0x5c, 0xb8, 0xea, 0x9b, 0x94, 0x5a, ++ 0x28, 0x9f, 0x9d, 0xbc, 0xed, 0x1e, 0xf3, 0x3a, 0x4a, 0x5f, 0x35, 0x50, ++ 0x1f, 0x82, 0xf5, 0x27, 0xd6, 0x45, 0xe6, 0xbb, 0xd3, 0x52, 0x23, 0xf0, ++ 0xdd, 0xdf, 0x73, 0x3a, 0x05, 0xb9, 0x09, 0xf9, 0xcf, 0xbf, 0xd7, 0xb3, ++ 0x7b, 0x38, 0x7e, 0xc3, 0xd7, 0x57, 0xd3, 0x32, 0xcf, 0x3c, 0x0f, 0xed, ++ 0x19, 0xb7, 0x19, 0xe4, 0xeb, 0xc1, 0x14, 0x26, 0x27, 0x0f, 0x73, 0xf9, ++ 0xf8, 0x67, 0x5e, 0x7e, 0xc5, 0x9f, 0xd7, 0x68, 0x9c, 0xf3, 0x60, 0xff, ++ 0x2b, 0x52, 0x79, 0xdc, 0xb6, 0x33, 0x5d, 0x57, 0xc2, 0x3c, 0x28, 0xdd, ++ 0xaa, 0xce, 0x05, 0x74, 0xd1, 0xce, 0xe9, 0xba, 0x3a, 0x95, 0xcb, 0x07, ++ 0x7e, 0xdf, 0x41, 0x15, 0x61, 0xe7, 0x87, 0xee, 0x94, 0xaf, 0xb5, 0x34, ++ 0xdc, 0x7e, 0xcb, 0x82, 0xbc, 0x9c, 0xc6, 0xe3, 0x90, 0x27, 0xaa, 0xce, ++ 0x7f, 0x10, 0xf9, 0x8d, 0xea, 0xbc, 0x5f, 0xca, 0x17, 0xf1, 0x5e, 0x17, ++ 0xd2, 0xac, 0xcc, 0x1b, 0xed, 0xb0, 0x3f, 0xba, 0x31, 0xbe, 0x07, 0xc7, ++ 0x15, 0xc1, 0xe8, 0x78, 0x34, 0xb5, 0x4b, 0x7e, 0xf6, 0xf8, 0x1d, 0xd6, ++ 0xfd, 0x78, 0xa4, 0x75, 0x2f, 0x25, 0x2c, 0x9f, 0x59, 0xbd, 0x0e, 0xe2, ++ 0x4e, 0x40, 0xda, 0x12, 0xf9, 0xcd, 0x9d, 0xd7, 0x13, 0x88, 0xbc, 0x9e, ++ 0x4e, 0xeb, 0x68, 0x50, 0xdc, 0xbf, 0x20, 0xfc, 0xec, 0x54, 0x0f, 0x7a, ++ 0x16, 0xe6, 0x53, 0x36, 0xd7, 0x4c, 0xc0, 0x7f, 0x13, 0xce, 0x27, 0xce, ++ 0xdc, 0x86, 0x4f, 0xa8, 0xf9, 0xce, 0x3f, 0x8b, 0x9f, 0xdd, 0x86, 0xdf, ++ 0x34, 0xc2, 0x3c, 0xd5, 0xfc, 0x46, 0x9c, 0x6f, 0x56, 0x97, 0x42, 0x9f, ++ 0x83, 0x73, 0x51, 0x90, 0x6f, 0x07, 0xf7, 0xb4, 0x80, 0x9f, 0xfe, 0xa1, ++ 0x44, 0xf7, 0x01, 0xc0, 0xdb, 0xf6, 0x92, 0xe0, 0x57, 0x1a, 0xb0, 0xcf, ++ 0xe2, 0x03, 0x88, 0x67, 0x69, 0x56, 0xf7, 0x21, 0x78, 0x2e, 0xe9, 0x59, ++ 0xdc, 0x5d, 0xe4, 0xb1, 0x5e, 0xd2, 0x78, 0x7e, 0x0d, 0x7a, 0xd1, 0x6f, ++ 0xb7, 0x2d, 0x42, 0x3e, 0xd4, 0x06, 0xc2, 0x81, 0xd2, 0xe3, 0x5b, 0xb4, ++ 0x0e, 0xfe, 0xd3, 0x61, 0x16, 0xd7, 0x51, 0x98, 0x17, 0xe9, 0xc3, 0xf0, ++ 0xa7, 0xab, 0xfc, 0xcc, 0x77, 0xb8, 0x1e, 0xd2, 0xb9, 0x64, 0x74, 0x25, ++ 0xf2, 0x14, 0xdb, 0xb7, 0xff, 0x3d, 0x03, 0xfd, 0x58, 0x77, 0xc0, 0xf7, ++ 0xae, 0xe0, 0x50, 0x26, 0x0f, 0x0b, 0x40, 0xfe, 0xff, 0xf5, 0x41, 0xd1, ++ 0xa8, 0xf2, 0xb4, 0x4a, 0xc4, 0x27, 0x15, 0x40, 0x9e, 0x75, 0x22, 0xea, ++ 0x11, 0xad, 0xe9, 0x7a, 0x2d, 0x94, 0xff, 0x6c, 0x3b, 0xb1, 0x35, 0x3d, ++ 0x07, 0xfb, 0x57, 0xdb, 0x8b, 0xad, 0x29, 0x83, 0x8c, 0x6c, 0xdc, 0xd1, ++ 0x63, 0xa1, 0x6c, 0xd6, 0xbb, 0xb7, 0xce, 0x03, 0x3b, 0x69, 0xb0, 0x01, ++ 0xed, 0xa4, 0xf7, 0x79, 0x7e, 0xdf, 0xa4, 0xf3, 0x37, 0xe3, 0x41, 0x5e, ++ 0x4d, 0x92, 0x7d, 0x89, 0x79, 0x52, 0x67, 0x3b, 0xb3, 0xf5, 0xe4, 0xac, ++ 0x12, 0x7b, 0x5e, 0x67, 0x7b, 0x93, 0xae, 0x6f, 0x14, 0xac, 0xef, 0x4e, ++ 0x76, 0xa7, 0xcb, 0xe8, 0xb7, 0x01, 0x18, 0xd5, 0xf6, 0x67, 0xe5, 0x9a, ++ 0xaf, 0x08, 0xe4, 0x43, 0x0f, 0x5d, 0x73, 0x93, 0xc0, 0x7d, 0x63, 0x77, ++ 0xb6, 0x47, 0x89, 0x0c, 0x6c, 0xa2, 0xe0, 0xac, 0xe3, 0x08, 0x94, 0x45, ++ 0x17, 0x9c, 0x98, 0x86, 0x33, 0xe0, 0x52, 0xed, 0x11, 0x28, 0x07, 0xff, ++ 0x85, 0x99, 0xe7, 0x77, 0xca, 0x27, 0x1a, 0x72, 0xa3, 0xf1, 0x08, 0x3b, ++ 0x0e, 0xde, 0x57, 0x79, 0xbf, 0xc2, 0xa0, 0x77, 0x98, 0xbd, 0xca, 0xcb, ++ 0x4e, 0xf7, 0xb0, 0x2d, 0xf3, 0x28, 0xf3, 0xd4, 0x8a, 0x7d, 0x45, 0x98, ++ 0x3f, 0x21, 0x07, 0x62, 0xa0, 0xbc, 0x26, 0x05, 0xd0, 0xef, 0x25, 0x6b, ++ 0xd8, 0xbd, 0x0b, 0xe2, 0xbe, 0x05, 0x6a, 0xc7, 0xa6, 0x76, 0x4f, 0x00, ++ 0xbb, 0x97, 0xe5, 0x4b, 0x8d, 0x84, 0x3c, 0x23, 0x3a, 0xb9, 0xb2, 0x1f, ++ 0x7c, 0x34, 0xe7, 0x21, 0xa4, 0xfb, 0x28, 0xd4, 0x7f, 0x3a, 0xec, 0xd8, ++ 0xd7, 0x35, 0x98, 0x1f, 0xd0, 0xa4, 0x75, 0xc6, 0x0e, 0x07, 0x3b, 0x76, ++ 0x4d, 0x2f, 0xc7, 0x3a, 0x5a, 0xff, 0x93, 0x3f, 0xe1, 0x67, 0x07, 0x68, ++ 0x59, 0x63, 0xf9, 0x8a, 0x84, 0xdf, 0xcf, 0x56, 0xb9, 0xe6, 0xba, 0xa2, ++ 0xde, 0xba, 0x2e, 0x74, 0xbf, 0x0f, 0xe4, 0x41, 0x57, 0xfe, 0x8f, 0x8c, ++ 0x72, 0xa7, 0x92, 0x90, 0x8d, 0xb0, 0x5f, 0x95, 0xe4, 0x2d, 0xfd, 0xca, ++ 0x30, 0x39, 0x48, 0x1a, 0xff, 0xdc, 0x01, 0xf7, 0x7e, 0x94, 0xcf, 0x95, ++ 0x03, 0xe0, 0xd0, 0xae, 0xd2, 0x4e, 0x72, 0xd2, 0xf7, 0xca, 0xb9, 0xbd, ++ 0x41, 0x3c, 0x8f, 0xb0, 0x3a, 0xb7, 0xb3, 0x08, 0xf9, 0x7c, 0xa2, 0x93, ++ 0xf6, 0x5b, 0x9e, 0xc0, 0xdf, 0x27, 0x33, 0x58, 0x7b, 0xba, 0x68, 0x7f, ++ 0x80, 0xd5, 0x7b, 0x89, 0xfe, 0xf6, 0x4f, 0xc4, 0x7a, 0x8a, 0xa8, 0xf3, ++ 0xfe, 0xee, 0x12, 0xf5, 0x2d, 0xac, 0x9e, 0x25, 0xbe, 0xdf, 0xcb, 0xea, ++ 0xb9, 0x62, 0xfc, 0xf7, 0xd9, 0x78, 0x66, 0xf6, 0x7e, 0x69, 0xf7, 0xef, ++ 0x4d, 0x02, 0xfd, 0x43, 0xf0, 0xf7, 0x71, 0xdd, 0x95, 0xf7, 0xf2, 0x50, ++ 0x7e, 0x3f, 0xb1, 0xfb, 0xed, 0xf3, 0x49, 0x94, 0xed, 0x5c, 0x1e, 0x88, ++ 0x7b, 0x78, 0xca, 0x7e, 0x30, 0x2e, 0xfa, 0x3d, 0xa0, 0xe7, 0x46, 0x09, ++ 0x73, 0xdf, 0x2a, 0xd7, 0xea, 0xd0, 0xbf, 0x7d, 0xd5, 0xd6, 0x98, 0x17, ++ 0x7e, 0x1e, 0x59, 0xe4, 0x9f, 0xb8, 0x4a, 0xcd, 0x4e, 0xd0, 0xf7, 0xaa, ++ 0xf6, 0xf5, 0xde, 0x21, 0xf3, 0x7c, 0x1c, 0xd0, 0x37, 0x7e, 0xc4, 0xe3, ++ 0xca, 0x65, 0xb2, 0x09, 0xe3, 0x11, 0xd7, 0x37, 0x33, 0x3e, 0xdf, 0x95, ++ 0xbe, 0xb6, 0x78, 0xcd, 0x1b, 0x8a, 0xfd, 0xec, 0xd4, 0xce, 0xef, 0x49, ++ 0xc6, 0x40, 0x1d, 0x1d, 0xef, 0xda, 0x13, 0x49, 0x98, 0xdf, 0x4e, 0x7a, ++ 0xfa, 0x31, 0x0e, 0xbe, 0xbc, 0xbb, 0x24, 0xe2, 0xed, 0x78, 0x9e, 0x55, ++ 0xe4, 0x7b, 0xc5, 0xf7, 0x20, 0x4e, 0xb0, 0x4f, 0xe3, 0x7f, 0x13, 0xc5, ++ 0xee, 0xa1, 0xbc, 0xe0, 0x47, 0xfe, 0xbb, 0xf8, 0x37, 0xcc, 0xdf, 0x5b, ++ 0xf5, 0xcc, 0x11, 0x94, 0x73, 0xf3, 0x65, 0x3b, 0xe2, 0xf1, 0xf1, 0x2c, ++ 0xf7, 0x0a, 0x80, 0x4f, 0x9b, 0x99, 0xdd, 0x37, 0xb8, 0x78, 0xcd, 0x21, ++ 0xa4, 0xd7, 0xb5, 0x99, 0x5c, 0x4f, 0xb0, 0x04, 0xfb, 0x86, 0xc3, 0xf3, ++ 0xc1, 0xce, 0xf0, 0xff, 0xe1, 0x1d, 0xe0, 0xff, 0xc3, 0x7f, 0x27, 0xfc, ++ 0xd5, 0x7e, 0x66, 0x71, 0x1e, 0x7a, 0xd9, 0x37, 0xcc, 0x4b, 0x6b, 0x33, ++ 0xb3, 0x38, 0xa8, 0x83, 0xef, 0xd3, 0x79, 0x8d, 0x7d, 0x00, 0x87, 0xd7, ++ 0xd3, 0x40, 0xe7, 0xd7, 0x16, 0xf9, 0x73, 0xac, 0x32, 0x24, 0x0d, 0xfb, ++ 0x13, 0x59, 0xbe, 0xd1, 0xbb, 0x45, 0x60, 0x07, 0x5d, 0xaf, 0x35, 0xe3, ++ 0xfd, 0x44, 0xb3, 0x56, 0x7d, 0x9c, 0x17, 0x7e, 0x1e, 0x45, 0x94, 0x6a, ++ 0xfd, 0xff, 0x73, 0xa0, 0xa3, 0x84, 0x10, 0xbc, 0x76, 0x75, 0xe7, 0xfa, ++ 0x5e, 0x08, 0xbe, 0x2f, 0xdd, 0x01, 0xbe, 0x2f, 0xfd, 0x3b, 0xe1, 0x9b, ++ 0xa4, 0x0d, 0xe8, 0x1d, 0x10, 0x37, 0x3d, 0xcb, 0xee, 0x0b, 0x1b, 0xe0, ++ 0x3f, 0xaf, 0x0f, 0xcf, 0x73, 0x39, 0xd9, 0x9d, 0xc9, 0xdd, 0xd8, 0x66, ++ 0x16, 0x27, 0x52, 0xe7, 0x6b, 0x9d, 0xec, 0x6e, 0x66, 0x78, 0xc5, 0xe3, ++ 0x31, 0x55, 0x93, 0xdf, 0x1d, 0x06, 0xf1, 0x18, 0x41, 0x0f, 0x23, 0xa3, ++ 0x49, 0x23, 0xf8, 0xd7, 0x29, 0x5e, 0x3b, 0x38, 0x5e, 0x3b, 0x00, 0xaf, ++ 0x05, 0xfe, 0x86, 0xe2, 0x32, 0xf4, 0xbb, 0x08, 0xf4, 0x15, 0xc2, 0x5f, ++ 0xc2, 0xec, 0x62, 0x0e, 0x27, 0x7f, 0x67, 0xbc, 0x3d, 0x7d, 0x07, 0xb8, ++ 0x9e, 0xfe, 0x77, 0xc2, 0xb5, 0x89, 0xea, 0xbf, 0x18, 0xc7, 0x7c, 0x3d, ++ 0x0a, 0xfd, 0x27, 0x6a, 0x38, 0xff, 0x8d, 0xd3, 0xbb, 0x80, 0xb7, 0x31, ++ 0xed, 0xf6, 0x70, 0x36, 0xa6, 0xfd, 0x6b, 0xe0, 0x6c, 0x4c, 0xb3, 0x2b, ++ 0xf2, 0xd2, 0x04, 0xbc, 0xbb, 0x92, 0x4f, 0xea, 0xfd, 0x11, 0xf3, 0x8e, ++ 0x40, 0xa7, 0x45, 0xdf, 0x86, 0x4e, 0x1f, 0x4d, 0xe7, 0x7c, 0x4a, 0x1b, ++ 0xc0, 0x3c, 0x51, 0xf5, 0xbe, 0xc7, 0xa6, 0x75, 0xda, 0xf7, 0xb8, 0xb4, ++ 0xdb, 0xef, 0xbb, 0xb2, 0xfd, 0x5f, 0xbc, 0xef, 0x6a, 0xb8, 0xa9, 0xcb, ++ 0x4a, 0x1e, 0xdf, 0x54, 0x3f, 0xcf, 0x4f, 0xd3, 0xfc, 0x4b, 0xe1, 0xf8, ++ 0xff, 0x9b, 0xff, 0x7c, 0x76, 0xed, 0x61, 0x45, 0xfb, 0xdc, 0x35, 0x27, ++ 0x15, 0xed, 0xf3, 0x3c, 0x1f, 0x28, 0xea, 0xc3, 0x02, 0xfe, 0x52, 0x40, ++ 0x73, 0xe1, 0x0f, 0x1f, 0x71, 0x29, 0x88, 0xfa, 0xe5, 0xb7, 0xf5, 0xab, ++ 0x77, 0xe5, 0x4f, 0x9f, 0xf4, 0xda, 0x12, 0x0d, 0xc4, 0xdb, 0x06, 0xf9, ++ 0x99, 0x3f, 0xbf, 0x2d, 0xdd, 0xbd, 0x01, 0xf0, 0xeb, 0x7d, 0x8d, 0xb7, ++ 0xde, 0x4c, 0xe1, 0x3a, 0xf0, 0x5c, 0x23, 0xbb, 0xa7, 0xab, 0x22, 0x07, ++ 0xf3, 0x87, 0x56, 0xf1, 0x39, 0x7e, 0x39, 0xec, 0x6f, 0x9f, 0x3c, 0x44, ++ 0xf1, 0xe6, 0x4b, 0x62, 0x40, 0x7f, 0xa7, 0xef, 0xf0, 0x5d, 0x5a, 0x7b, ++ 0x6e, 0x67, 0x3c, 0x28, 0xbe, 0xa1, 0x21, 0xce, 0xb0, 0x3c, 0xb4, 0x62, ++ 0xa3, 0x55, 0xeb, 0x44, 0x7f, 0x0d, 0x71, 0x46, 0xc2, 0x9b, 0xc7, 0xd3, ++ 0x18, 0xde, 0x61, 0xfe, 0x0f, 0xa5, 0xf7, 0xe9, 0x46, 0xa2, 0x8b, 0xa7, ++ 0x74, 0x3e, 0x7d, 0xba, 0x84, 0xf9, 0x4e, 0xd3, 0x09, 0xcb, 0x87, 0xa6, ++ 0xa5, 0xcf, 0x4d, 0xdb, 0x27, 0x69, 0x89, 0x0f, 0xee, 0x35, 0x2e, 0x37, ++ 0x69, 0x7d, 0x06, 0x8c, 0xf3, 0x29, 0xcf, 0x2f, 0x1b, 0xf8, 0xbd, 0xc7, ++ 0x24, 0x3e, 0x4e, 0x71, 0x8e, 0x59, 0x76, 0xca, 0x98, 0x97, 0x36, 0x75, ++ 0x10, 0x8b, 0x0f, 0x3e, 0x60, 0x6a, 0xc4, 0x73, 0xa4, 0x33, 0x4e, 0x3c, ++ 0x7c, 0xed, 0x21, 0xda, 0x4e, 0xd6, 0x7b, 0x8a, 0x58, 0xbe, 0xb5, 0x38, ++ 0x7f, 0xf6, 0x07, 0xcd, 0x37, 0x89, 0xfb, 0x3d, 0x9e, 0x46, 0x98, 0x9f, ++ 0x5d, 0xe2, 0x71, 0x64, 0x49, 0x87, 0xf7, 0x61, 0xa9, 0xbf, 0x9b, 0xcb, ++ 0xd7, 0x3b, 0x49, 0x5e, 0x27, 0x43, 0xbe, 0x4b, 0xf0, 0x03, 0x82, 0x7a, ++ 0xb7, 0xa0, 0x3b, 0xba, 0xbe, 0x13, 0x86, 0x02, 0x76, 0xbe, 0x02, 0x7e, ++ 0x77, 0xa2, 0x9c, 0xe8, 0x7c, 0xbd, 0xf1, 0x7c, 0xf3, 0x96, 0x52, 0x78, ++ 0xbf, 0xf2, 0xb4, 0x1d, 0xe1, 0x52, 0x33, 0x68, 0x5d, 0x1e, 0xec, 0x63, ++ 0xcd, 0x28, 0xe9, 0x53, 0x43, 0x5e, 0xc8, 0xae, 0xa9, 0x59, 0xf3, 0x17, ++ 0xec, 0xa7, 0x4c, 0x7e, 0xa5, 0x1e, 0xde, 0xbf, 0x7e, 0x96, 0xb9, 0xc2, ++ 0x07, 0xb6, 0x52, 0x3b, 0xc5, 0x1e, 0xee, 0xaf, 0x0c, 0xcc, 0x01, 0xba, ++ 0xbc, 0x93, 0xfd, 0x23, 0xe6, 0x7d, 0xae, 0xce, 0x87, 0xf8, 0xf4, 0x49, ++ 0xdd, 0x09, 0x2c, 0xdf, 0x1f, 0xf1, 0x4e, 0x11, 0xe8, 0x19, 0x81, 0x3a, ++ 0x7f, 0x44, 0xbf, 0xe4, 0xb7, 0xf5, 0x0f, 0x08, 0xbf, 0x80, 0xf0, 0x13, ++ 0x08, 0x3e, 0x20, 0xee, 0xe1, 0x7b, 0x3d, 0x8d, 0xf3, 0x05, 0xa3, 0xd4, ++ 0x1d, 0xef, 0x4f, 0xd3, 0xb2, 0x52, 0xf0, 0xcb, 0x03, 0x9d, 0xf9, 0xeb, ++ 0x9b, 0x77, 0xe0, 0xaf, 0x6f, 0xfe, 0x3b, 0xf9, 0xeb, 0xd7, 0xc5, 0xf3, ++ 0xca, 0x64, 0x26, 0x17, 0xd5, 0xf8, 0xad, 0xc6, 0x6b, 0x81, 0xcf, 0x70, ++ 0x5f, 0x37, 0xfc, 0xde, 0xc0, 0x03, 0x54, 0xdf, 0x03, 0xb9, 0x3a, 0x93, ++ 0x78, 0x72, 0x2b, 0x29, 0x9f, 0x9d, 0xbe, 0xa4, 0x41, 0x37, 0x54, 0xfa, ++ 0xf6, 0x78, 0xbd, 0xcc, 0x74, 0x21, 0x83, 0x44, 0x38, 0x67, 0xf2, 0xcd, ++ 0xf9, 0xb9, 0x1d, 0xf7, 0x4d, 0x2e, 0x95, 0xd1, 0x3e, 0x10, 0xf9, 0x09, ++ 0x62, 0x1f, 0xae, 0xa7, 0x75, 0xd2, 0x33, 0xbf, 0x4a, 0x4b, 0xb8, 0xed, ++ 0xbe, 0x29, 0xdb, 0xff, 0xed, 0x7a, 0xfc, 0x85, 0x39, 0xdf, 0x4e, 0xae, ++ 0x11, 0x85, 0x3e, 0x60, 0x4d, 0xef, 0xb4, 0xee, 0x84, 0xf4, 0xdb, 0xaf, ++ 0x5b, 0xd9, 0xfe, 0x2f, 0x5e, 0x77, 0xd8, 0xf9, 0x97, 0x39, 0xb2, 0x26, ++ 0x74, 0xde, 0x03, 0xf2, 0x87, 0x21, 0x8f, 0xb1, 0xdd, 0xcb, 0xce, 0x33, ++ 0x56, 0x64, 0x35, 0xe0, 0x3d, 0xf1, 0x64, 0x50, 0x30, 0x06, 0xf4, 0xc6, ++ 0xa5, 0x07, 0x65, 0xc4, 0x43, 0xa2, 0x75, 0x6a, 0x53, 0xc2, 0xee, 0x97, ++ 0x6a, 0x25, 0xbe, 0x0f, 0x01, 0x1f, 0x97, 0x0c, 0x5b, 0x82, 0xe7, 0xe0, ++ 0x3a, 0xdd, 0x0b, 0x65, 0x6a, 0xc2, 0x73, 0x71, 0xea, 0xfb, 0xa1, 0x44, ++ 0xbe, 0x70, 0x35, 0xef, 0x47, 0x7d, 0x4f, 0x54, 0x35, 0xcf, 0x13, 0xae, ++ 0x56, 0xe5, 0xed, 0x0c, 0x49, 0xe7, 0xe7, 0x08, 0x0b, 0x48, 0x01, 0xcb, ++ 0xaf, 0x50, 0xea, 0xa5, 0xea, 0xb2, 0xad, 0x8e, 0x28, 0xfc, 0x92, 0x6d, ++ 0x37, 0xeb, 0xd0, 0x0f, 0x50, 0x92, 0xbe, 0xf7, 0x47, 0x9e, 0xb4, 0xd0, ++ 0x3e, 0x8c, 0xed, 0xbc, 0x6f, 0x13, 0xee, 0xb0, 0x6f, 0x13, 0xfe, 0x9d, ++ 0xfb, 0xa6, 0xc6, 0x57, 0xd9, 0xbc, 0x13, 0xcf, 0x43, 0x7d, 0x53, 0x7c, ++ 0x25, 0x76, 0xe7, 0x3c, 0x98, 0xb7, 0xe0, 0xc3, 0xb3, 0x20, 0x87, 0x8b, ++ 0x8e, 0x3b, 0xeb, 0x80, 0xc1, 0x0b, 0xf7, 0xf9, 0x8b, 0x7b, 0xad, 0xdb, ++ 0x25, 0x76, 0xff, 0x4c, 0xfb, 0xa7, 0x04, 0xfd, 0x46, 0x77, 0xba, 0x17, ++ 0x79, 0xf0, 0x69, 0x37, 0x9e, 0xe7, 0x1c, 0xf8, 0xae, 0x53, 0x66, 0x79, ++ 0x04, 0x2c, 0xdf, 0x40, 0xe8, 0x29, 0x42, 0x6f, 0x19, 0xda, 0x1a, 0x94, ++ 0xd9, 0xfd, 0xf5, 0xfc, 0x1c, 0x14, 0xcf, 0x0b, 0xfa, 0xba, 0xfc, 0xcb, ++ 0xe1, 0xb7, 0xa0, 0x9e, 0x23, 0xfc, 0x6f, 0xff, 0x2c, 0xbf, 0xb5, 0x90, ++ 0x73, 0x7b, 0x8c, 0x8c, 0x3e, 0x84, 0x7f, 0xb0, 0x30, 0xe0, 0x42, 0x3d, ++ 0xae, 0x4d, 0xe7, 0x2b, 0x82, 0x7b, 0xe8, 0x3d, 0xfb, 0xa3, 0x22, 0xea, ++ 0x01, 0x3f, 0x49, 0x67, 0xfb, 0xd4, 0xd5, 0xbd, 0xad, 0x49, 0x31, 0xee, ++ 0x9f, 0xa4, 0x43, 0x3b, 0xe7, 0xef, 0xe2, 0xfe, 0xd6, 0x32, 0x99, 0xdd, ++ 0xd3, 0x7c, 0xdd, 0x2f, 0xa3, 0xff, 0x6e, 0xf5, 0x0f, 0x7f, 0xf7, 0xeb, ++ 0x67, 0xed, 0x77, 0xb6, 0xeb, 0x6b, 0x2c, 0xd7, 0x23, 0xda, 0x45, 0xa2, ++ 0xac, 0xd1, 0xb0, 0x73, 0x12, 0x05, 0xa5, 0x76, 0xcc, 0xdb, 0x03, 0x7b, ++ 0x09, 0xfc, 0x77, 0xc2, 0x9f, 0xa7, 0x7e, 0xff, 0x50, 0x66, 0xc9, 0xce, ++ 0x74, 0xf4, 0x2f, 0x0d, 0xc3, 0xfb, 0x34, 0xaf, 0x6f, 0x65, 0xf3, 0xe9, ++ 0x6a, 0x5f, 0x6a, 0xd6, 0x04, 0x71, 0xfc, 0x2e, 0xdb, 0xf9, 0xf8, 0x35, ++ 0x07, 0x8b, 0x2c, 0xe1, 0xf7, 0x60, 0x7c, 0x9e, 0x2e, 0x09, 0x7c, 0xb6, ++ 0x5c, 0x34, 0x86, 0xf6, 0xf5, 0xeb, 0xee, 0xff, 0xf0, 0xe0, 0x74, 0x85, ++ 0x7e, 0xf3, 0xff, 0xba, 0xdd, 0x30, 0x49, 0xa6, 0xaa, 0x23, 0x95, 0x8f, ++ 0xb9, 0x92, 0x97, 0xe9, 0xa7, 0x84, 0xe9, 0xa9, 0xb3, 0x88, 0x1f, 0xcb, ++ 0x39, 0x24, 0x88, 0xa5, 0x9b, 0xb0, 0x7c, 0xfa, 0xf9, 0xc4, 0x81, 0xe5, ++ 0x42, 0xe2, 0xc2, 0xd2, 0x95, 0xe9, 0xfe, 0x28, 0x1d, 0xf3, 0x5b, 0x82, ++ 0x89, 0x98, 0x0f, 0xb9, 0xef, 0x1f, 0x7d, 0x01, 0x6f, 0xae, 0x8d, 0x18, ++ 0xda, 0x00, 0xb9, 0x73, 0xff, 0x2a, 0x3d, 0xad, 0x3d, 0xdf, 0x8e, 0xe3, ++ 0xb7, 0xbf, 0xfe, 0x8f, 0x0c, 0xc8, 0x6b, 0xb9, 0x13, 0xfd, 0xf7, 0x8b, ++ 0x71, 0xb6, 0xa6, 0x47, 0x88, 0x27, 0xff, 0x67, 0xb1, 0x8c, 0xf1, 0x13, ++ 0x92, 0xbc, 0x12, 0xe9, 0xa1, 0x9c, 0xdf, 0x92, 0x40, 0x46, 0xb1, 0xb8, ++ 0xd8, 0x8f, 0x12, 0xb3, 0xd8, 0x3d, 0xf5, 0x1d, 0xfc, 0x2f, 0x69, 0xbb, ++ 0xe0, 0x7f, 0x10, 0x6f, 0xcd, 0xfd, 0x54, 0xc3, 0xf2, 0x43, 0x96, 0x4a, ++ 0x78, 0x7f, 0x6b, 0x73, 0x40, 0x83, 0xa4, 0x95, 0xbb, 0x28, 0xcb, 0x0b, ++ 0xf7, 0xf1, 0x34, 0x37, 0xb1, 0xf6, 0xdc, 0x2a, 0xab, 0x57, 0xa2, 0xf5, ++ 0xdc, 0xc1, 0x51, 0xac, 0x7d, 0x85, 0xd5, 0x0b, 0xe7, 0x1e, 0x66, 0x93, ++ 0x00, 0xd2, 0xe3, 0x5c, 0x38, 0xf5, 0x20, 0xc3, 0x39, 0x18, 0xc6, 0xdf, ++ 0xc4, 0x3d, 0xe5, 0x54, 0x63, 0xcf, 0x06, 0x3d, 0x6b, 0x51, 0x8b, 0x91, ++ 0xe5, 0xef, 0x93, 0x40, 0x4f, 0xe0, 0xe3, 0x79, 0x5d, 0xd8, 0x37, 0x63, ++ 0x33, 0x98, 0x5d, 0xdc, 0x2f, 0x9b, 0xf1, 0xed, 0x7e, 0x25, 0x4a, 0x3f, ++ 0x44, 0x4c, 0x06, 0xe3, 0x03, 0x55, 0x99, 0x25, 0x4b, 0x33, 0x68, 0xb9, ++ 0x2a, 0xc3, 0x19, 0x0b, 0x65, 0x3f, 0x9b, 0x7f, 0xd3, 0x4f, 0x0b, 0xd1, ++ 0x2f, 0x8f, 0xbf, 0xa3, 0xf2, 0xc5, 0xe0, 0x07, 0x31, 0x7e, 0x28, 0xbe, ++ 0x7b, 0x32, 0xb3, 0x24, 0x1e, 0xde, 0x7b, 0x55, 0x62, 0xf9, 0xe6, 0x9e, ++ 0x83, 0xfc, 0xf7, 0x06, 0x48, 0x30, 0x31, 0xfc, 0xfe, 0x50, 0x57, 0x66, ++ 0x69, 0x6a, 0x06, 0x1d, 0x3f, 0x2b, 0x83, 0x30, 0x3a, 0xea, 0x02, 0xae, ++ 0xf0, 0x7b, 0x73, 0xae, 0x08, 0xf6, 0x9c, 0xc8, 0x67, 0xec, 0x07, 0x36, ++ 0x15, 0xfa, 0xc7, 0xd9, 0x3d, 0x54, 0xaf, 0x4a, 0xac, 0x5e, 0xf0, 0xbc, ++ 0xed, 0xbe, 0xf5, 0x7d, 0xd1, 0x87, 0xef, 0x01, 0xbd, 0xf6, 0xc9, 0x4c, ++ 0xf7, 0x3d, 0x38, 0x7f, 0x3d, 0x21, 0x26, 0x98, 0xff, 0xcf, 0x0d, 0xde, ++ 0x1d, 0xa8, 0x7f, 0xd6, 0x66, 0x80, 0x3f, 0x72, 0xc9, 0xf3, 0x06, 0x0d, ++ 0xe8, 0x05, 0x1f, 0x51, 0xb1, 0x0a, 0xe7, 0x4a, 0xfe, 0x58, 0x67, 0xc4, ++ 0xf2, 0x63, 0x6a, 0xe7, 0x42, 0xf9, 0x27, 0x6a, 0xe7, 0x42, 0xf9, 0x29, ++ 0xb5, 0x73, 0xa1, 0xfc, 0x8c, 0xda, 0xb9, 0x50, 0x2e, 0xba, 0xe1, 0x20, ++ 0x84, 0xf2, 0x8f, 0xf7, 0x32, 0x9c, 0xa3, 0x32, 0x8a, 0x42, 0xf1, 0x36, ++ 0xf5, 0x7c, 0x87, 0x73, 0x78, 0x76, 0x8c, 0x7f, 0x50, 0x8f, 0xe3, 0x57, ++ 0x65, 0xba, 0x11, 0xbe, 0x1d, 0xfb, 0xbd, 0x9f, 0x78, 0x21, 0x1e, 0xf2, ++ 0xaa, 0x35, 0x98, 0x6a, 0xbb, 0x0d, 0xbe, 0x75, 0xcd, 0x67, 0x3c, 0xdc, ++ 0xde, 0x8b, 0x9c, 0x9f, 0xd5, 0x9f, 0xef, 0x7b, 0x5e, 0x93, 0x16, 0xe5, ++ 0x78, 0x5e, 0x73, 0x20, 0x66, 0x71, 0xd8, 0x7b, 0x93, 0x33, 0xf4, 0xd8, ++ 0x9e, 0xfb, 0xfa, 0x05, 0x3c, 0x1f, 0xda, 0x66, 0xe9, 0x80, 0xaf, 0x53, ++ 0xa2, 0x4b, 0x9e, 0xa4, 0x61, 0xf5, 0xc9, 0xcf, 0xf7, 0x41, 0xf8, 0x56, ++ 0x65, 0x3a, 0x97, 0xc2, 0x3e, 0x52, 0xfa, 0xfe, 0x0e, 0x94, 0x79, 0xcd, ++ 0xbf, 0xfb, 0x09, 0x9c, 0xe7, 0xa1, 0xfd, 0x63, 0x1e, 0x41, 0xbb, 0x14, ++ 0x7c, 0x0a, 0xf5, 0x7c, 0xd5, 0x3a, 0xd4, 0x70, 0x10, 0xeb, 0x7a, 0xd5, ++ 0xea, 0xdf, 0x04, 0xdf, 0xbf, 0xfa, 0x7a, 0x36, 0xac, 0x84, 0xf2, 0x1b, ++ 0xc2, 0xe8, 0x06, 0xf0, 0x48, 0x8a, 0xb4, 0xde, 0x75, 0x08, 0xd7, 0xfb, ++ 0x0c, 0xc1, 0x42, 0x38, 0xa7, 0x72, 0xdf, 0x2d, 0x39, 0x62, 0xde, 0x70, ++ 0x55, 0x66, 0x31, 0xc2, 0x59, 0x27, 0xf0, 0x4d, 0xc0, 0x89, 0xef, 0xd7, ++ 0xb7, 0xa5, 0xeb, 0x8e, 0x78, 0x36, 0xc7, 0x53, 0x22, 0xee, 0xd7, 0x00, ++ 0xde, 0x69, 0x07, 0x39, 0x74, 0x33, 0x06, 0xf4, 0xba, 0x72, 0x1e, 0xaf, ++ 0x6f, 0x6e, 0xea, 0xf9, 0x3e, 0xac, 0xcf, 0x73, 0x42, 0x26, 0xbd, 0xec, ++ 0x88, 0xbf, 0x0a, 0xba, 0x7b, 0x8e, 0xef, 0x8f, 0x28, 0x73, 0x0f, 0xea, ++ 0x5d, 0xb0, 0x4f, 0xaf, 0x1e, 0xbc, 0xd8, 0x13, 0xee, 0x5b, 0xa5, 0xfb, ++ 0xd2, 0x13, 0xee, 0x5f, 0xdd, 0x9c, 0xd1, 0x4b, 0x91, 0xdf, 0x94, 0x3b, ++ 0xf8, 0xef, 0xdb, 0x7e, 0x1a, 0x8f, 0xef, 0xe3, 0xef, 0x7c, 0xce, 0x20, ++ 0xdb, 0xcb, 0x20, 0x9f, 0x64, 0xa6, 0xf1, 0xf0, 0x31, 0x58, 0xd2, 0x6c, ++ 0xcb, 0xa7, 0x65, 0x90, 0x4f, 0x32, 0x37, 0x59, 0x3a, 0x0e, 0xe5, 0x3c, ++ 0x7b, 0xd6, 0x68, 0xc8, 0x23, 0x11, 0xf9, 0xee, 0x0b, 0xfa, 0x14, 0x1f, ++ 0x07, 0x52, 0x9a, 0xe0, 0x28, 0x47, 0x7d, 0xac, 0x18, 0x98, 0x4b, 0x98, ++ 0x3c, 0x28, 0x35, 0x46, 0xf3, 0xcb, 0x9f, 0x85, 0xfc, 0x89, 0x53, 0xd4, ++ 0xc7, 0x24, 0x77, 0x57, 0xbc, 0x3f, 0xce, 0xde, 0x43, 0xd1, 0x3e, 0xbe, ++ 0xcf, 0x3d, 0x8a, 0x76, 0x31, 0xee, 0x04, 0x47, 0x7f, 0xc5, 0x7b, 0xfd, ++ 0x6c, 0xc1, 0x6c, 0xb0, 0xbf, 0xe8, 0x3a, 0xd8, 0x7d, 0xd7, 0xbb, 0x64, ++ 0xcc, 0xbb, 0xcb, 0x7d, 0xfd, 0xf4, 0xbd, 0xf7, 0xd0, 0xfa, 0xa4, 0x17, ++ 0xa7, 0xe2, 0xfd, 0x7e, 0xaf, 0xf2, 0xf6, 0x49, 0x7b, 0x4b, 0xf1, 0xf7, ++ 0x03, 0xdb, 0x29, 0x3c, 0xf5, 0x54, 0x91, 0xba, 0x34, 0xe8, 0xb1, 0xa7, ++ 0x7e, 0x0a, 0x9d, 0xa9, 0xf4, 0xfb, 0xca, 0x83, 0x2f, 0x1c, 0x77, 0xda, ++ 0x6f, 0xa3, 0xdf, 0xdf, 0x41, 0xaf, 0x17, 0xfc, 0x75, 0x79, 0x8b, 0xb1, ++ 0x08, 0xf8, 0xeb, 0xd7, 0xd5, 0xf3, 0xd5, 0xfb, 0xb2, 0x3f, 0x83, 0x9f, ++ 0x0b, 0xe4, 0x7a, 0x7f, 0x57, 0xf8, 0xd2, 0x41, 0x0f, 0x92, 0x9d, 0xe1, ++ 0x0b, 0xbf, 0x67, 0x4b, 0x8d, 0x2f, 0x90, 0x59, 0xca, 0xf0, 0x8f, 0x95, ++ 0x93, 0x4e, 0xb1, 0x73, 0x60, 0xdf, 0x94, 0x8f, 0x7d, 0x0e, 0x7c, 0x2c, ++ 0xec, 0x1c, 0x66, 0x47, 0xa9, 0xf2, 0xb7, 0xf5, 0xd3, 0x3b, 0xde, 0x5f, ++ 0x05, 0xfe, 0xf7, 0xf7, 0x64, 0x82, 0xe7, 0xea, 0xf8, 0xf9, 0xbc, 0xc5, ++ 0xf0, 0xff, 0x72, 0x08, 0xcf, 0xc9, 0xc2, 0xed, 0x8f, 0xc0, 0x7d, 0x52, ++ 0xf4, 0xb9, 0x07, 0xf4, 0x4f, 0x38, 0x07, 0xea, 0xa4, 0xfd, 0xff, 0x39, ++ 0x83, 0xeb, 0x4d, 0x95, 0x87, 0x1f, 0x49, 0x29, 0x0c, 0xb5, 0x93, 0xd5, ++ 0x9f, 0x2a, 0xde, 0x27, 0x6b, 0xa5, 0x0d, 0x8a, 0xfa, 0xfa, 0x2c, 0x65, ++ 0x7d, 0x73, 0xf1, 0x86, 0xf0, 0xef, 0xbb, 0xe2, 0x87, 0x8b, 0xb7, 0xce, ++ 0xd3, 0xbb, 0xf1, 0xfc, 0xa6, 0x14, 0xf1, 0xf7, 0x5a, 0xc5, 0x7c, 0xca, ++ 0xde, 0x8a, 0xc2, 0xfc, 0xbc, 0x89, 0x90, 0x77, 0x42, 0x1f, 0x55, 0x17, ++ 0x7e, 0xa0, 0x85, 0xf8, 0xea, 0xc4, 0x2e, 0xe4, 0xa7, 0xe0, 0x3b, 0x33, ++ 0x64, 0x52, 0x1b, 0xa9, 0xfd, 0x66, 0x06, 0xf3, 0xdf, 0x4f, 0x78, 0x2b, ++ 0x0a, 0xf3, 0x59, 0xbe, 0x69, 0xbf, 0x1f, 0x51, 0x58, 0x62, 0xbe, 0xe0, ++ 0x6f, 0x98, 0xfc, 0xfc, 0x28, 0xd6, 0xaf, 0x0d, 0xdf, 0x77, 0x43, 0x26, ++ 0xeb, 0xff, 0x5a, 0xd1, 0x96, 0x1f, 0x7e, 0x05, 0x71, 0xcf, 0xfd, 0x04, ++ 0xf3, 0x37, 0xaf, 0x59, 0x19, 0xdf, 0xcf, 0x6b, 0xfa, 0x42, 0xa3, 0xa1, ++ 0x65, 0xbf, 0x6e, 0x0c, 0x5f, 0xf2, 0x2c, 0x01, 0x0d, 0xc8, 0x93, 0xf6, ++ 0x8a, 0x68, 0x0f, 0xe4, 0xe7, 0xd7, 0x2c, 0x35, 0x63, 0x5e, 0x67, 0xbf, ++ 0xec, 0xe0, 0x87, 0xc6, 0x7c, 0x42, 0x62, 0x33, 0x37, 0xff, 0xd8, 0x48, ++ 0xf7, 0xed, 0x0f, 0x70, 0x98, 0x31, 0x4c, 0x9e, 0xb6, 0x83, 0x8d, 0x43, ++ 0xeb, 0xc9, 0xff, 0xf1, 0x38, 0xf2, 0xfb, 0xf1, 0x6f, 0x45, 0xf9, 0x34, ++ 0xdf, 0x62, 0x3d, 0xc9, 0x54, 0x87, 0x42, 0x79, 0x5d, 0xc2, 0xe8, 0x7b, ++ 0x0e, 0xe0, 0x0d, 0x97, 0x2b, 0xe0, 0x3b, 0xaf, 0x79, 0x84, 0x74, 0xc8, ++ 0x19, 0xe0, 0x07, 0xb0, 0x7e, 0xa8, 0x4f, 0xca, 0xfc, 0xf1, 0xfb, 0x4f, ++ 0xd2, 0x71, 0x6b, 0x4e, 0x32, 0xfa, 0x86, 0x4c, 0x39, 0xb5, 0xdd, 0x3e, ++ 0x33, 0xcc, 0x6e, 0x27, 0xcf, 0x31, 0xba, 0x34, 0xd2, 0x7f, 0xa0, 0xcf, ++ 0x2d, 0x3b, 0xda, 0xa0, 0x07, 0x7b, 0xee, 0xce, 0xf4, 0xdd, 0x88, 0x79, ++ 0x33, 0x5f, 0x97, 0xae, 0x0b, 0x32, 0x95, 0xf6, 0x7b, 0x04, 0x3a, 0x3e, ++ 0x35, 0x9e, 0xee, 0x4b, 0xcd, 0x7e, 0x76, 0xbf, 0xc4, 0xf5, 0x96, 0x5e, ++ 0x78, 0xae, 0xb5, 0x2b, 0xf9, 0x5d, 0xb3, 0x55, 0x83, 0xf4, 0x27, 0xea, ++ 0x6d, 0x2d, 0xf2, 0x58, 0xc0, 0x57, 0xf5, 0xf9, 0x70, 0x01, 0x4f, 0x62, ++ 0xc9, 0x51, 0xdc, 0xe3, 0xb4, 0x72, 0xf8, 0xdf, 0x26, 0x83, 0x9c, 0x5c, ++ 0x79, 0x50, 0xcb, 0x92, 0x3d, 0xba, 0x1a, 0x67, 0xa3, 0x86, 0xd8, 0xc3, ++ 0xc6, 0x79, 0xf5, 0x90, 0xa1, 0x82, 0xfd, 0x0e, 0x25, 0x9b, 0x7f, 0xbb, ++ 0x90, 0xcf, 0x07, 0xff, 0x6a, 0x2b, 0xee, 0xcb, 0xca, 0x75, 0x11, 0xe4, ++ 0x1c, 0x95, 0xcb, 0xba, 0x78, 0x90, 0xcb, 0xe5, 0xec, 0xf7, 0x15, 0xce, ++ 0x1c, 0x4c, 0x2a, 0x01, 0xf8, 0x9f, 0x91, 0x88, 0xcf, 0x8e, 0xe7, 0xae, ++ 0x58, 0x9e, 0xf1, 0xfd, 0xac, 0x3b, 0x78, 0x6e, 0xc2, 0xfb, 0x43, 0x92, ++ 0xfb, 0x68, 0xc3, 0xef, 0x37, 0x14, 0x76, 0xe4, 0xd4, 0x83, 0x53, 0x7b, ++ 0x81, 0x1e, 0xf9, 0x61, 0xd3, 0xfc, 0x33, 0x74, 0x67, 0xc8, 0xa2, 0xcc, ++ 0x1e, 0x38, 0xde, 0x34, 0xe2, 0x41, 0xbd, 0xf7, 0x8c, 0xd5, 0x95, 0x0e, ++ 0xfe, 0x86, 0x49, 0x3c, 0xde, 0x7f, 0xc6, 0x1a, 0x6c, 0x05, 0x7e, 0x7c, ++ 0x66, 0x78, 0xb4, 0x04, 0xf1, 0x7b, 0xda, 0xff, 0x7a, 0x12, 0x76, 0x5f, ++ 0xdf, 0x19, 0x9d, 0x2b, 0x9d, 0xdd, 0x03, 0x21, 0xf2, 0x8a, 0xef, 0xfe, ++ 0x56, 0xf7, 0xb6, 0x95, 0xc9, 0x6b, 0x8b, 0xc7, 0x43, 0xbc, 0x7a, 0x16, ++ 0xb1, 0x80, 0x1d, 0x79, 0x9f, 0xcc, 0xf4, 0x5a, 0xf2, 0x26, 0xa3, 0x4b, ++ 0xc1, 0xef, 0x6a, 0x24, 0xbf, 0x0d, 0xe6, 0xe9, 0xca, 0x9c, 0xfc, 0xfd, ++ 0x4c, 0xfa, 0x5d, 0xd2, 0x9a, 0x1f, 0xa1, 0x5d, 0xd9, 0x01, 0x37, 0x2d, ++ 0xff, 0x9d, 0xa6, 0xaf, 0xa9, 0xd7, 0x76, 0xd8, 0xaf, 0xbb, 0x25, 0x76, ++ 0x3f, 0x89, 0x83, 0xe9, 0xfb, 0xd5, 0xc3, 0xae, 0xfe, 0x6c, 0x1a, 0x9c, ++ 0x73, 0xa3, 0x76, 0xb6, 0x44, 0xe7, 0x33, 0xbf, 0xf9, 0x30, 0xde, 0xc3, ++ 0xa3, 0xb6, 0xab, 0x3b, 0xec, 0x9b, 0xff, 0xa5, 0x7f, 0xb4, 0xb3, 0x7d, ++ 0xe4, 0xda, 0x92, 0x59, 0x14, 0xf2, 0x7b, 0xab, 0xed, 0xa4, 0x0e, 0xbd, ++ 0x5c, 0xe8, 0x77, 0xbb, 0x58, 0x9e, 0xfb, 0x91, 0xe1, 0x4f, 0xb7, 0x2d, ++ 0xa7, 0xf5, 0xd5, 0xbb, 0xa2, 0x11, 0x8e, 0x97, 0x9f, 0x37, 0x78, 0x80, ++ 0x7f, 0x5f, 0xde, 0x61, 0x40, 0x7b, 0xe7, 0xb2, 0x2d, 0x78, 0x6e, 0x15, ++ 0xd4, 0xf7, 0xe6, 0x3a, 0x3c, 0x38, 0x5a, 0x0e, 0x9e, 0xef, 0x12, 0xf8, ++ 0xbd, 0x44, 0x63, 0xff, 0x3d, 0xc8, 0x1d, 0xf2, 0x5b, 0x1d, 0xde, 0xb7, ++ 0xf1, 0xc5, 0xcf, 0x0d, 0xf8, 0x7b, 0x1e, 0x4b, 0x5f, 0xb8, 0x6b, 0x07, ++ 0xd8, 0x4f, 0x5f, 0xa4, 0xdb, 0x5f, 0x7e, 0x05, 0xfc, 0x7b, 0x2f, 0x27, ++ 0xe0, 0x7d, 0x00, 0x24, 0x99, 0x7d, 0x3f, 0x91, 0xd3, 0x23, 0xd0, 0x97, ++ 0x9d, 0xee, 0x87, 0xfc, 0x0b, 0x33, 0xea, 0x0d, 0x4b, 0x5f, 0x4b, 0x41, ++ 0xfe, 0x25, 0xf6, 0xef, 0xd2, 0xcf, 0xa3, 0xf0, 0x1c, 0xfc, 0xe5, 0x13, ++ 0xf7, 0xc7, 0x82, 0x1f, 0xac, 0x55, 0xb3, 0x87, 0xfd, 0x8e, 0xa4, 0x6c, ++ 0xf2, 0x00, 0x1f, 0x5e, 0xbe, 0x23, 0x0a, 0xf5, 0x3e, 0xa2, 0x77, 0xbf, ++ 0x06, 0xeb, 0x2f, 0xfd, 0xc5, 0xc4, 0x69, 0xfd, 0x61, 0xfc, 0xdf, 0x25, ++ 0x10, 0x58, 0x4f, 0x7b, 0xcb, 0x6b, 0xe8, 0x7f, 0x0c, 0xed, 0x6f, 0x64, ++ 0xb9, 0x7e, 0xbd, 0xa5, 0x07, 0xe3, 0x03, 0x1d, 0x72, 0x96, 0xe5, 0xcd, ++ 0xce, 0x0d, 0xdd, 0xcb, 0xbc, 0x1f, 0xf0, 0xa7, 0x8a, 0x88, 0x7b, 0x10, ++ 0x59, 0xde, 0x6c, 0x81, 0x2c, 0xb1, 0xdf, 0x95, 0x7c, 0x22, 0xf2, 0x39, ++ 0xf0, 0xdf, 0x66, 0xf2, 0x38, 0xa9, 0xf0, 0x97, 0xc4, 0x11, 0x63, 0x32, ++ 0xd0, 0xa1, 0x9b, 0xb0, 0x7b, 0x1f, 0x9f, 0xe8, 0x8d, 0xf7, 0xea, 0x9e, ++ 0xcf, 0xe4, 0xe7, 0x97, 0x49, 0x90, 0x9f, 0x77, 0x14, 0xf8, 0x76, 0xae, ++ 0xfa, 0x00, 0xfa, 0x4b, 0x0c, 0x2c, 0x5f, 0xaf, 0x8b, 0x7b, 0x2d, 0x3f, ++ 0xcc, 0x64, 0xe7, 0x82, 0x17, 0x1b, 0xff, 0xa2, 0xf0, 0x9b, 0x54, 0xaf, ++ 0xb9, 0xa1, 0xac, 0xf7, 0x65, 0xbf, 0xb3, 0x5c, 0x50, 0x6f, 0xef, 0xbf, ++ 0x82, 0x96, 0xab, 0x38, 0x9c, 0xff, 0x91, 0xe4, 0xfa, 0x08, 0xd6, 0xb7, ++ 0xac, 0x71, 0xcb, 0xbe, 0x77, 0x11, 0x2e, 0xcf, 0x7d, 0xef, 0x0f, 0x30, ++ 0xee, 0x09, 0x13, 0xfa, 0x69, 0xc8, 0xbb, 0x0c, 0x7e, 0x6a, 0xfb, 0x65, ++ 0xb1, 0x31, 0xc8, 0xe3, 0x0e, 0xdb, 0x15, 0x71, 0xf5, 0x8b, 0xcf, 0xfc, ++ 0x1e, 0xf3, 0x47, 0x2e, 0xbe, 0x7e, 0x0f, 0xfe, 0xbe, 0xd8, 0x7c, 0xd9, ++ 0x7f, 0x11, 0xee, 0xc7, 0x6a, 0x33, 0xfb, 0x3f, 0x79, 0x88, 0x96, 0x7b, ++ 0x4f, 0x9c, 0xc2, 0x7d, 0x51, 0xcf, 0xb7, 0x53, 0x1c, 0x5e, 0x62, 0x7c, ++ 0xa5, 0x12, 0xd6, 0xd1, 0x1f, 0xf2, 0x57, 0x5c, 0xed, 0x99, 0x48, 0xb7, ++ 0x8c, 0xde, 0xcf, 0x6f, 0xca, 0x45, 0xf8, 0x09, 0x3f, 0x6d, 0xfb, 0xe5, ++ 0xc8, 0xf6, 0x95, 0x98, 0xa7, 0xe8, 0x5f, 0xcc, 0x4f, 0xf4, 0x2f, 0xde, ++ 0xfb, 0xef, 0x4c, 0xa6, 0xdf, 0x5f, 0xd3, 0xfb, 0xf3, 0x40, 0x2e, 0xef, ++ 0x84, 0x38, 0x44, 0x98, 0x3e, 0x7f, 0x2d, 0xc6, 0x9f, 0x07, 0x3f, 0x75, ++ 0xbb, 0x33, 0x9d, 0xe5, 0x73, 0x5f, 0xb3, 0xd1, 0x7a, 0x18, 0xde, 0xfc, ++ 0x5f, 0x8a, 0x9c, 0x0c, 0xc3, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xad, 0x58, ++ 0x0d, 0x6c, 0x14, 0xd7, 0x11, 0x9e, 0xb7, 0x7b, 0xb7, 0x77, 0xc6, 0x77, ++ 0xf6, 0x81, 0x8d, 0x7f, 0xe2, 0x1f, 0xf6, 0xce, 0xc4, 0x18, 0x7c, 0xf8, ++ 0x16, 0xff, 0xd5, 0xb1, 0x4d, 0x39, 0xfc, 0x83, 0x28, 0x42, 0xcd, 0xf1, ++ 0x93, 0xd4, 0x4a, 0x21, 0x6c, 0x9a, 0x40, 0x28, 0xc4, 0xf8, 0x64, 0x43, ++ 0x8b, 0x92, 0xaa, 0xac, 0x7b, 0x95, 0xf9, 0x11, 0x51, 0x5c, 0x35, 0x8a, ++ 0xa0, 0x4d, 0xab, 0x83, 0x08, 0x14, 0x55, 0x54, 0x18, 0x17, 0x22, 0x8a, ++ 0x30, 0xbd, 0x04, 0x15, 0x70, 0x1b, 0xd1, 0x43, 0x89, 0x14, 0x92, 0x5a, ++ 0x68, 0xeb, 0x36, 0xd4, 0x6d, 0x0c, 0xe7, 0xd2, 0xa4, 0x2d, 0x6a, 0x24, ++ 0x77, 0xe6, 0xed, 0x1e, 0x77, 0xeb, 0x9f, 0xb4, 0x89, 0x7a, 0x96, 0x6f, ++ 0x3c, 0xef, 0xcd, 0x9b, 0x37, 0xf3, 0xcd, 0xbc, 0x99, 0xf7, 0xdc, 0x01, ++ 0xf8, 0xa9, 0x06, 0xe8, 0x70, 0x82, 0x3d, 0x37, 0x17, 0x69, 0x07, 0x53, ++ 0x22, 0x38, 0xd4, 0x01, 0xa0, 0xc1, 0x3c, 0x4e, 0x63, 0x2a, 0xce, 0x3f, ++ 0x57, 0x70, 0x01, 0x6c, 0x35, 0x24, 0x0c, 0x21, 0x67, 0x1e, 0xc0, 0x63, ++ 0x60, 0x7e, 0x72, 0x73, 0x6c, 0x50, 0x0f, 0xb0, 0x91, 0xfe, 0x96, 0x71, ++ 0xbc, 0xe1, 0xb7, 0xf7, 0x59, 0x16, 0xc0, 0x13, 0x30, 0x60, 0x87, 0x32, ++ 0x80, 0x9b, 0x42, 0xef, 0x1e, 0x49, 0x04, 0x18, 0x1f, 0xf8, 0xa1, 0x5d, ++ 0x75, 0x91, 0x50, 0x9b, 0xe7, 0x76, 0x05, 0x00, 0xd3, 0x3e, 0x10, 0x26, ++ 0x2b, 0x01, 0x26, 0xe9, 0xb3, 0x62, 0x3a, 0x05, 0xb0, 0x01, 0xc9, 0xd1, ++ 0x67, 0x52, 0xa4, 0x6f, 0x0d, 0x60, 0x3e, 0x7e, 0xb7, 0x40, 0x45, 0x18, ++ 0xf5, 0xdc, 0xf1, 0xb8, 0x34, 0x21, 0x00, 0x50, 0x2a, 0x33, 0x1b, 0x97, ++ 0x2b, 0x81, 0x12, 0x92, 0xc3, 0x79, 0x25, 0x56, 0x8b, 0x74, 0xd0, 0xa1, ++ 0x44, 0xd0, 0x9e, 0x3d, 0x42, 0xc8, 0x27, 0xe3, 0xba, 0xe7, 0xa4, 0x58, ++ 0x15, 0x88, 0xa9, 0x75, 0x7b, 0x04, 0x95, 0x8f, 0x8f, 0xb3, 0xb7, 0xb7, ++ 0x81, 0x8f, 0xb6, 0x8b, 0x55, 0x85, 0xdc, 0x00, 0x89, 0xb9, 0x12, 0xb0, ++ 0x6c, 0xa4, 0xf3, 0x95, 0x78, 0x10, 0xf1, 0xd0, 0x3e, 0x01, 0xe5, 0x04, ++ 0xea, 0x49, 0xd8, 0xa1, 0x63, 0x10, 0xf7, 0xad, 0x6d, 0x15, 0xc2, 0x83, ++ 0xdc, 0x0f, 0xdb, 0xa8, 0x8e, 0xfb, 0x0a, 0xc0, 0xb8, 0x7d, 0xb5, 0x95, ++ 0x38, 0xee, 0x07, 0x58, 0x4e, 0xe3, 0x4e, 0xd3, 0x6e, 0x2f, 0x8e, 0x07, ++ 0xac, 0xf2, 0x29, 0x7f, 0xac, 0xfc, 0x05, 0x59, 0xe0, 0xfe, 0xd5, 0xe6, ++ 0x08, 0xe1, 0x01, 0xff, 0x74, 0x3c, 0x36, 0xd0, 0x7c, 0x1d, 0x40, 0x04, ++ 0x62, 0x22, 0xe1, 0x8a, 0x9f, 0x8d, 0x4e, 0xc4, 0xbd, 0xc9, 0xc4, 0x1d, ++ 0x20, 0x28, 0x02, 0xc6, 0x65, 0x97, 0xc9, 0xef, 0x72, 0xba, 0x62, 0x62, ++ 0x15, 0xda, 0x9d, 0xe5, 0xd4, 0x44, 0xf4, 0xa7, 0xe9, 0x22, 0xc6, 0x05, ++ 0xf9, 0x26, 0x5b, 0xec, 0x4d, 0xa2, 0x2c, 0x08, 0xb0, 0x17, 0xe3, 0x0b, ++ 0xe7, 0xed, 0xe3, 0x0f, 0xec, 0x20, 0x1c, 0x0a, 0x2a, 0x6d, 0xa4, 0xa7, ++ 0xd1, 0x0c, 0x2f, 0x43, 0x5d, 0x9b, 0x50, 0xae, 0x8f, 0x85, 0x81, 0xf6, ++ 0x75, 0x42, 0x3f, 0xa7, 0x87, 0x58, 0x9c, 0xdb, 0xf1, 0x65, 0x98, 0xe0, ++ 0x34, 0x08, 0x1e, 0x1b, 0x51, 0x84, 0x9f, 0xd3, 0x36, 0x08, 0x71, 0xba, ++ 0x0a, 0xc2, 0x9c, 0xae, 0x86, 0x7e, 0x4e, 0xd7, 0xc0, 0x00, 0xa7, 0x6b, ++ 0x21, 0xce, 0x29, 0x2c, 0x89, 0x45, 0xc0, 0x4b, 0x3b, 0x7d, 0xc7, 0x73, ++ 0x3b, 0x13, 0xc9, 0x57, 0x9e, 0x15, 0x26, 0x91, 0xd6, 0x7e, 0x0d, 0xc2, ++ 0x03, 0xae, 0xe9, 0x38, 0xec, 0x31, 0x71, 0x9a, 0x1d, 0x07, 0x8d, 0x51, ++ 0x3e, 0x7e, 0x5e, 0x1c, 0x56, 0x81, 0x5a, 0xc0, 0xf5, 0x4d, 0xc5, 0xa3, ++ 0xb8, 0x82, 0xe7, 0xf7, 0x54, 0x3c, 0x1c, 0x94, 0x8f, 0x18, 0xb7, 0x0c, ++ 0x88, 0x16, 0x10, 0x5d, 0x0e, 0xba, 0x48, 0x74, 0x05, 0x25, 0x2e, 0xea, ++ 0x59, 0x09, 0xb2, 0x8d, 0xf8, 0x56, 0x08, 0x72, 0xbe, 0xfd, 0x7f, 0xc4, ++ 0xa1, 0x41, 0x57, 0x6d, 0xaa, 0x7f, 0x06, 0x3c, 0x5a, 0x67, 0xce, 0x8b, ++ 0xef, 0x9a, 0x79, 0x21, 0x12, 0x86, 0x75, 0xa9, 0x38, 0x9d, 0x91, 0x65, ++ 0xce, 0x27, 0xe3, 0x05, 0x68, 0x67, 0x68, 0xe9, 0xf4, 0x38, 0x26, 0xc7, ++ 0x6b, 0x33, 0x5b, 0xfe, 0x2e, 0x7b, 0x00, 0x8e, 0x46, 0xdb, 0x42, 0xb6, ++ 0x42, 0xe4, 0x6b, 0x5a, 0x7a, 0xca, 0x90, 0xff, 0x99, 0xbc, 0xd1, 0xe0, ++ 0x9b, 0x5a, 0x7e, 0xe1, 0x43, 0xfe, 0x54, 0xf4, 0x31, 0x83, 0x0f, 0xb4, ++ 0xd4, 0xd8, 0x15, 0x80, 0xde, 0xde, 0xc7, 0x43, 0x6d, 0x8f, 0x00, 0xa8, ++ 0x19, 0x59, 0x55, 0x10, 0xa0, 0xc2, 0x51, 0x2e, 0x50, 0xfe, 0xec, 0xf6, ++ 0x18, 0xf8, 0xab, 0xbd, 0x7b, 0x14, 0x0f, 0x9e, 0x23, 0xb5, 0xc4, 0xa5, ++ 0x90, 0x7f, 0x4e, 0x07, 0x62, 0x86, 0xf8, 0x89, 0x65, 0x22, 0x34, 0x20, ++ 0x6d, 0x93, 0xd4, 0x97, 0x65, 0xb4, 0xb3, 0x74, 0x75, 0xbc, 0xcf, 0x40, ++ 0xb8, 0x25, 0xbf, 0x03, 0xcf, 0xef, 0x78, 0xdc, 0x0e, 0x87, 0x70, 0xfd, ++ 0x7e, 0xc9, 0x90, 0x77, 0xe0, 0x3a, 0x67, 0x75, 0xca, 0x2f, 0x1c, 0xd7, ++ 0x32, 0x90, 0x1f, 0x1c, 0xac, 0xec, 0x61, 0xbe, 0xd9, 0xf7, 0x47, 0xfd, ++ 0xc7, 0x48, 0xbf, 0xda, 0xfb, 0xb0, 0x06, 0x64, 0xc7, 0x39, 0xa6, 0x7c, ++ 0xd6, 0x3e, 0x3f, 0xce, 0x57, 0x4f, 0x92, 0x3c, 0x38, 0xcb, 0x81, 0xe2, ++ 0x5e, 0xe4, 0x34, 0xf4, 0x8c, 0x0f, 0x56, 0x56, 0x52, 0x5c, 0xce, 0x10, ++ 0x48, 0x34, 0x9f, 0xeb, 0xad, 0x21, 0xdc, 0xfe, 0x92, 0x1f, 0x3a, 0x43, ++ 0xf2, 0x09, 0xb7, 0x91, 0x5f, 0x67, 0x28, 0x07, 0xe7, 0xcf, 0x4e, 0xdf, ++ 0x97, 0x83, 0xa7, 0x49, 0x7e, 0xea, 0x78, 0xe2, 0x43, 0x34, 0x00, 0xd7, ++ 0xbf, 0x25, 0xab, 0xe7, 0x68, 0xbe, 0x2b, 0xf3, 0xd3, 0x72, 0xaa, 0x4b, ++ 0x77, 0x97, 0xbd, 0xd3, 0xa7, 0x7b, 0x53, 0x79, 0xca, 0x70, 0xff, 0x4d, ++ 0xe8, 0x77, 0x24, 0x08, 0x51, 0x89, 0xd7, 0x91, 0x66, 0xcf, 0x6d, 0xac, ++ 0xa3, 0x80, 0x31, 0x99, 0xc4, 0x78, 0x26, 0xb6, 0xa2, 0x1e, 0xc4, 0xa1, ++ 0x36, 0xa4, 0x46, 0xec, 0x38, 0xfc, 0xa5, 0x4d, 0x13, 0xf5, 0x58, 0xa4, ++ 0x48, 0x6f, 0x8c, 0xea, 0x5d, 0x97, 0xa4, 0x97, 0x2e, 0xc3, 0x75, 0x2f, ++ 0x6f, 0xb8, 0x25, 0x19, 0x79, 0x56, 0x6c, 0xe4, 0x99, 0x59, 0x87, 0x86, ++ 0x2e, 0x0d, 0xbf, 0x50, 0x64, 0xb0, 0x21, 0x48, 0x3b, 0x57, 0x5d, 0x97, ++ 0xee, 0xff, 0xe3, 0xf7, 0x88, 0x5f, 0xd7, 0x3d, 0x97, 0x42, 0xe2, 0xa9, ++ 0xf3, 0x74, 0xb4, 0x07, 0xb2, 0x48, 0xc8, 0x65, 0xa9, 0x1b, 0xc9, 0x73, ++ 0xd6, 0x78, 0xde, 0x11, 0x13, 0xb3, 0x88, 0x5f, 0xbc, 0x95, 0xe4, 0x96, ++ 0xbf, 0x33, 0x52, 0x46, 0x7e, 0xad, 0x18, 0xd1, 0x23, 0x6e, 0xd2, 0x33, ++ 0xf4, 0x5e, 0x91, 0x61, 0x87, 0xd9, 0x17, 0x82, 0xff, 0x64, 0x5f, 0xa4, ++ 0x2f, 0xb4, 0x8b, 0x54, 0x9c, 0x01, 0xba, 0xcf, 0x89, 0x51, 0x07, 0xe2, ++ 0xd5, 0xcd, 0xc2, 0x97, 0xdd, 0xc4, 0xff, 0x9c, 0x29, 0x1a, 0xda, 0xff, ++ 0x67, 0x27, 0xe6, 0x47, 0x36, 0xc9, 0x07, 0x5d, 0x85, 0xe8, 0xd7, 0x76, ++ 0xd3, 0xaf, 0xce, 0xe1, 0x13, 0x7d, 0x6e, 0xa4, 0xdb, 0x5f, 0x7d, 0x7a, ++ 0x2d, 0x54, 0xd1, 0x71, 0xb0, 0xf3, 0xfa, 0x2d, 0xe3, 0x0f, 0x9d, 0xff, ++ 0x9d, 0xaf, 0xdb, 0x53, 0xf5, 0x9c, 0x7f, 0x63, 0x20, 0xd0, 0xcf, 0x2e, ++ 0x48, 0x7e, 0x62, 0x12, 0xe5, 0x41, 0xe7, 0x80, 0x55, 0xae, 0x0b, 0x0e, ++ 0xff, 0x8d, 0xea, 0x4e, 0x57, 0x7a, 0x9d, 0x47, 0xbb, 0x26, 0x64, 0x77, ++ 0x2e, 0xc7, 0xdb, 0xec, 0x57, 0x40, 0x2d, 0x04, 0xf5, 0x3d, 0x6b, 0xae, ++ 0x25, 0x3f, 0x5c, 0x64, 0xf7, 0x90, 0x14, 0x75, 0x30, 0xa4, 0x3f, 0xe9, ++ 0x51, 0x3c, 0xc4, 0x9b, 0xe7, 0x07, 0x2e, 0x7e, 0x0f, 0xd2, 0xe5, 0xe1, ++ 0xd5, 0x1c, 0x1e, 0xfb, 0xe4, 0x79, 0xfa, 0xe6, 0x01, 0xb4, 0x3d, 0x27, ++ 0x85, 0x57, 0xe0, 0xa4, 0x23, 0x48, 0xb8, 0x07, 0x4e, 0xe6, 0x07, 0xc9, ++ 0xbf, 0x80, 0x04, 0x5b, 0x42, 0x1c, 0xef, 0x28, 0xcf, 0xe3, 0x00, 0xe6, ++ 0x06, 0xc3, 0x7c, 0x3a, 0x3d, 0x77, 0xc2, 0x27, 0xe0, 0x3e, 0xa7, 0x87, ++ 0x2a, 0x14, 0xac, 0xa0, 0x70, 0x61, 0x5f, 0x10, 0xfe, 0xb8, 0x30, 0x65, ++ 0x5f, 0xb7, 0x79, 0x9e, 0xda, 0xc5, 0x53, 0xad, 0x12, 0xe6, 0xc1, 0xbd, ++ 0x67, 0xc0, 0x83, 0x47, 0x12, 0xba, 0x87, 0x5f, 0x8b, 0x38, 0x91, 0xef, ++ 0x3e, 0x08, 0x24, 0x01, 0xf7, 0xe8, 0x0b, 0xf5, 0xdc, 0x1b, 0x13, 0xa2, ++ 0xa4, 0xa7, 0x71, 0xb8, 0xa6, 0x80, 0xe2, 0x7d, 0xd6, 0x3c, 0x9f, 0x8e, ++ 0x02, 0x01, 0xe4, 0x34, 0x9c, 0x32, 0xe4, 0x39, 0x20, 0x57, 0xa4, 0xf8, ++ 0x24, 0xbe, 0x0e, 0x33, 0x3e, 0x99, 0x15, 0xf3, 0x2c, 0xf3, 0x6e, 0xe5, ++ 0x21, 0xcb, 0xfa, 0xec, 0x06, 0x9f, 0x75, 0xbd, 0x16, 0x8c, 0xfb, 0xeb, ++ 0xa9, 0x1e, 0x1b, 0xeb, 0xe7, 0x06, 0x97, 0x58, 0xe4, 0xf7, 0x67, 0xad, ++ 0xba, 0x46, 0x79, 0xb9, 0x3c, 0xbe, 0x6d, 0x2d, 0xe1, 0x92, 0xb3, 0xba, ++ 0xda, 0x32, 0x5f, 0x0f, 0x4e, 0x7e, 0x7f, 0xa8, 0x2b, 0x76, 0x29, 0x51, ++ 0x5c, 0x0f, 0x1f, 0x1b, 0xfd, 0xbc, 0x01, 0x7f, 0x78, 0x3f, 0x80, 0xb0, ++ 0x48, 0xfe, 0x35, 0xe9, 0x00, 0x3f, 0xc2, 0x78, 0x34, 0x8e, 0xdb, 0x2c, ++ 0x71, 0xcf, 0xd0, 0x31, 0x1f, 0x51, 0x2e, 0xe3, 0xdd, 0xb4, 0xb8, 0xe3, ++ 0xaf, 0x43, 0xb6, 0xf2, 0xcb, 0xbc, 0x66, 0x1e, 0x14, 0x43, 0x71, 0x7a, ++ 0x1e, 0xa4, 0x70, 0x76, 0x3d, 0xc0, 0x91, 0xe7, 0xc1, 0x30, 0x0a, 0x11, ++ 0xce, 0x6e, 0x29, 0x8a, 0x57, 0x8e, 0x69, 0x38, 0xd5, 0xc3, 0xc2, 0x6c, ++ 0x9a, 0xaf, 0xbb, 0x26, 0x42, 0x94, 0xe3, 0xde, 0xa3, 0xc4, 0x70, 0x7c, ++ 0x7e, 0xc8, 0x8a, 0x77, 0x7e, 0x87, 0x15, 0xef, 0x42, 0xd5, 0x8a, 0x6f, ++ 0xd1, 0x76, 0x2b, 0xbe, 0x25, 0x61, 0x2b, 0xbe, 0x0b, 0xf6, 0x5a, 0xf1, ++ 0xf4, 0x6a, 0x56, 0xfc, 0xca, 0x0e, 0x34, 0x5a, 0xe4, 0x1f, 0xee, 0x6f, ++ 0xb1, 0xf0, 0x8b, 0x8e, 0xac, 0xb1, 0xc8, 0x2f, 0x8e, 0xae, 0xb7, 0xf0, ++ 0x95, 0xaf, 0x3f, 0x61, 0x91, 0x5f, 0x3a, 0xf0, 0x0d, 0xcb, 0x7c, 0xe0, ++ 0xfc, 0x0e, 0xcb, 0x7c, 0x32, 0xaf, 0xa6, 0xc6, 0x7d, 0x59, 0xac, 0xdb, ++ 0x22, 0x37, 0x35, 0xee, 0x35, 0xd7, 0x9e, 0xb7, 0xe8, 0x4d, 0xc6, 0x59, ++ 0xc3, 0x9f, 0xff, 0x67, 0x9c, 0x77, 0x4d, 0x89, 0xf3, 0xf3, 0x68, 0x1b, ++ 0x9d, 0xbb, 0xeb, 0x59, 0x63, 0x87, 0xe9, 0x18, 0x7e, 0x35, 0xd3, 0xa8, ++ 0x4b, 0xed, 0x62, 0x73, 0x3c, 0x48, 0xf1, 0x6e, 0xb6, 0x2b, 0x14, 0xd3, ++ 0xdf, 0xc9, 0x39, 0xad, 0x6e, 0x3a, 0xef, 0x66, 0x1f, 0x0a, 0x99, 0x7d, ++ 0x08, 0xd4, 0x3e, 0x1e, 0xf7, 0x90, 0x99, 0x27, 0x4a, 0x5c, 0xb9, 0x4c, ++ 0x75, 0xb4, 0xfa, 0x66, 0xa8, 0x35, 0x0b, 0xf9, 0x5a, 0x3d, 0x7c, 0x99, ++ 0xca, 0x71, 0xfd, 0x58, 0x7f, 0x6b, 0xb6, 0xcc, 0xd3, 0x44, 0xf6, 0xa0, ++ 0x3c, 0x33, 0x71, 0x79, 0xb4, 0x81, 0x81, 0xcd, 0x72, 0x5e, 0x90, 0xcf, ++ 0x4b, 0xe1, 0xb6, 0x41, 0xeb, 0x15, 0xb3, 0x51, 0xb8, 0xe9, 0xd3, 0x68, ++ 0x84, 0x97, 0x4b, 0x4a, 0x2a, 0xdc, 0x7f, 0xbd, 0x39, 0xcf, 0x1a, 0x8c, ++ 0xba, 0xbe, 0x2e, 0x98, 0x01, 0xb6, 0x34, 0x3c, 0x96, 0x9b, 0xe3, 0x00, ++ 0x7e, 0x6e, 0x5f, 0xb3, 0x31, 0x05, 0x1b, 0xcc, 0xf7, 0x00, 0xde, 0xcb, ++ 0x41, 0xa2, 0x7b, 0xb9, 0xe0, 0x8c, 0x46, 0xbc, 0x33, 0xdd, 0x27, 0x95, ++ 0x23, 0x22, 0xbf, 0x27, 0xa9, 0xfc, 0xde, 0x74, 0x95, 0xa9, 0x76, 0xa2, ++ 0x1b, 0x9d, 0xf1, 0x52, 0xea, 0x5f, 0xc7, 0xf2, 0xd4, 0x23, 0x5e, 0xac, ++ 0xf3, 0x77, 0x05, 0x45, 0xe6, 0xf7, 0x2c, 0xa6, 0x47, 0xc8, 0xa9, 0x04, ++ 0x39, 0xc6, 0x9b, 0xce, 0x8d, 0x50, 0xd0, 0x4f, 0xf7, 0x77, 0xfc, 0xf3, ++ 0x21, 0xac, 0xbb, 0xc2, 0xf5, 0x90, 0xe6, 0xe7, 0xe6, 0x7b, 0x74, 0xb4, ++ 0x5f, 0x35, 0xed, 0x39, 0xe1, 0x55, 0x8f, 0x91, 0x9e, 0x51, 0xe6, 0xe9, ++ 0xab, 0xc1, 0xb5, 0xd7, 0x1b, 0x3f, 0x2a, 0xa5, 0xfe, 0xe3, 0x10, 0x11, ++ 0x09, 0xac, 0x83, 0x81, 0xac, 0xe0, 0x6b, 0x34, 0xaf, 0xed, 0x6f, 0x9e, ++ 0xcb, 0xfb, 0x6a, 0x3e, 0xfa, 0x87, 0x75, 0x54, 0x17, 0x64, 0x7e, 0x7f, ++ 0xd0, 0x9e, 0x67, 0xfc, 0x3d, 0xf0, 0x11, 0x29, 0x7b, 0x24, 0xed, 0x9c, ++ 0x1e, 0xb0, 0xf3, 0xbe, 0x03, 0xe6, 0xfb, 0x68, 0xb3, 0x89, 0x57, 0xf2, ++ 0x7d, 0xb4, 0xc9, 0xdc, 0x7f, 0x14, 0x55, 0x6c, 0xc7, 0x3a, 0xbd, 0xf9, ++ 0xfc, 0x55, 0x8e, 0xcb, 0xce, 0x82, 0x71, 0xb0, 0xe5, 0xf0, 0x7c, 0xe3, ++ 0xf7, 0xa4, 0xa7, 0x8b, 0x5d, 0xd5, 0x87, 0xc8, 0xa7, 0x60, 0x8d, 0xb2, ++ 0x7e, 0x29, 0x8d, 0x27, 0xdf, 0x4b, 0x45, 0xe2, 0xe7, 0xe9, 0x8b, 0xed, ++ 0xa2, 0x3f, 0x5b, 0x9f, 0xe1, 0xbe, 0x98, 0xa4, 0x3b, 0x0b, 0xc6, 0xf8, ++ 0x7b, 0xee, 0xc1, 0xfa, 0x53, 0x46, 0x1f, 0x99, 0x5d, 0xbf, 0xc6, 0xfb, ++ 0x6c, 0xca, 0x6f, 0x43, 0xff, 0xe8, 0xc1, 0x4c, 0xde, 0x5f, 0x46, 0x0f, ++ 0x96, 0xb4, 0x10, 0x4d, 0xe9, 0xbf, 0xcb, 0xf5, 0x6f, 0x0e, 0xdf, 0xb0, ++ 0xe4, 0xc9, 0x96, 0xbd, 0xef, 0x5b, 0xf2, 0xef, 0x29, 0xed, 0x0f, 0x96, ++ 0x79, 0x3d, 0x77, 0xc2, 0x5e, 0x84, 0xfe, 0xeb, 0x6f, 0x14, 0xae, 0xfa, ++ 0x3a, 0xe2, 0x77, 0xe7, 0x9c, 0xa3, 0x9e, 0xde, 0x8d, 0x18, 0xb7, 0x9b, ++ 0xde, 0xba, 0x94, 0x7e, 0xfd, 0xc5, 0x45, 0x6d, 0xb4, 0xdf, 0x7f, 0xf7, ++ 0xf3, 0xaf, 0x1c, 0xdf, 0x91, 0x7d, 0x71, 0xb0, 0x2d, 0x4c, 0xf9, 0x79, ++ 0x6b, 0xdf, 0x4d, 0xce, 0xeb, 0xfb, 0x74, 0x4e, 0xa7, 0xfa, 0x99, 0x7c, ++ 0x67, 0x26, 0xa9, 0xf4, 0x16, 0x54, 0xd8, 0x30, 0x3e, 0x13, 0x6c, 0x8e, ++ 0x72, 0xdc, 0x3b, 0x7d, 0x9f, 0x2d, 0x3e, 0xe3, 0x5d, 0x32, 0xb2, 0x32, ++ 0xaf, 0x85, 0xfa, 0xec, 0x48, 0x89, 0x64, 0x33, 0x68, 0xb9, 0xc1, 0x17, ++ 0x36, 0x38, 0x0d, 0x7e, 0xd5, 0x6a, 0xa2, 0x09, 0xbb, 0xeb, 0x00, 0xbd, ++ 0x33, 0x47, 0x18, 0x04, 0x19, 0xe6, 0xc3, 0x26, 0x16, 0xfa, 0xe9, 0x53, ++ 0xe8, 0xf7, 0x0b, 0x79, 0xea, 0x27, 0x94, 0x7f, 0x5d, 0x3b, 0x26, 0xaa, ++ 0x6c, 0x78, 0x1e, 0xba, 0x02, 0xfa, 0x93, 0x0c, 0xe3, 0x59, 0x3c, 0x57, ++ 0xfd, 0x17, 0xf9, 0xcf, 0xf0, 0x7a, 0x57, 0x38, 0x8f, 0xdb, 0x59, 0x4e, ++ 0xf7, 0x8e, 0x31, 0x41, 0xab, 0x62, 0x58, 0x0b, 0xaa, 0x7d, 0x85, 0xeb, ++ 0x6c, 0x18, 0x97, 0xb1, 0x39, 0xda, 0x5d, 0xea, 0xc4, 0x4b, 0x8e, 0xe7, ++ 0x1a, 0xbc, 0x64, 0x9c, 0x8f, 0x46, 0xdf, 0x24, 0x3f, 0x0f, 0xcd, 0x1e, ++ 0x55, 0xf0, 0xa1, 0x9e, 0x0f, 0x99, 0x18, 0xe3, 0xf9, 0xfc, 0x4b, 0x16, ++ 0x3d, 0xc1, 0xf3, 0x4d, 0x97, 0xd6, 0xbb, 0xf9, 0x79, 0xea, 0xa0, 0x77, ++ 0x17, 0xbd, 0x77, 0xe9, 0xbd, 0x91, 0xc8, 0x30, 0x68, 0x86, 0x8f, 0x71, ++ 0xff, 0xe6, 0x4c, 0xa1, 0x0b, 0x7d, 0x46, 0x3d, 0x6b, 0x34, 0x69, 0xbb, ++ 0x78, 0xb8, 0x9c, 0xd1, 0xfd, 0xe0, 0x88, 0x03, 0xe8, 0x3c, 0xe0, 0x3e, ++ 0x41, 0x81, 0xf6, 0x19, 0x72, 0x44, 0x4f, 0x20, 0x9f, 0x87, 0xb6, 0xd3, ++ 0x3d, 0xe5, 0xd7, 0x92, 0x71, 0x9f, 0xaf, 0xfe, 0x95, 0x23, 0x46, 0x75, ++ 0x63, 0x9b, 0xf3, 0x63, 0x1e, 0xa7, 0x12, 0x9f, 0x97, 0xeb, 0xc9, 0x2d, ++ 0xc3, 0xca, 0x85, 0xeb, 0x72, 0x5f, 0x72, 0x44, 0x23, 0x64, 0x9f, 0x1e, ++ 0x2f, 0x5d, 0x87, 0xf6, 0xf5, 0xdb, 0xf1, 0xfe, 0x42, 0xef, 0xe9, 0x77, ++ 0x71, 0x1e, 0xcf, 0xdd, 0x9d, 0x17, 0x17, 0x1d, 0x3f, 0x94, 0x16, 0x8f, ++ 0x12, 0x33, 0x0e, 0xf0, 0x0c, 0x80, 0x31, 0x9f, 0x7f, 0x8c, 0xe6, 0x3b, ++ 0x87, 0x47, 0x6f, 0x51, 0x1d, 0xb9, 0xe2, 0x55, 0xbd, 0xe4, 0xff, 0xa8, ++ 0x20, 0xd7, 0x53, 0x1d, 0xe9, 0xcc, 0x7a, 0x53, 0xa2, 0xfa, 0x53, 0xe3, ++ 0x93, 0xf9, 0x3a, 0xb4, 0x97, 0xfb, 0x8f, 0xf5, 0xe0, 0xfb, 0x8c, 0xe3, ++ 0xec, 0xf4, 0xfc, 0x09, 0xf3, 0x75, 0x0b, 0x16, 0x9b, 0x6c, 0x7a, 0xbf, ++ 0x09, 0xea, 0x62, 0x5a, 0xdf, 0xe9, 0xd4, 0x25, 0xd2, 0x87, 0x19, 0xc1, ++ 0xef, 0x7f, 0xb3, 0xf9, 0x7f, 0x67, 0x6b, 0xfc, 0x15, 0x3f, 0xd2, 0xbb, ++ 0x6e, 0xa5, 0x94, 0xf6, 0x49, 0xee, 0x8b, 0x76, 0xd4, 0x90, 0x9e, 0xa4, ++ 0xdf, 0x49, 0x3b, 0x52, 0x7a, 0x3e, 0x3b, 0xaf, 0xb7, 0x39, 0x27, 0x2c, ++ 0xe7, 0xf7, 0xf6, 0xd1, 0xfd, 0xe5, 0x74, 0x4e, 0x10, 0x5f, 0x95, 0xec, ++ 0xaf, 0x16, 0xd9, 0x96, 0xf5, 0x33, 0xac, 0x7f, 0xdc, 0x8c, 0xdb, 0xbf, ++ 0xf3, 0x43, 0x2b, 0x7d, 0x48, 0x77, 0x84, 0x7f, 0xf0, 0xc6, 0xdb, 0x72, ++ 0x6a, 0x3e, 0xc1, 0xfa, 0xbf, 0xf5, 0x01, 0xc5, 0x6b, 0xd8, 0xc5, 0xeb, ++ 0xdc, 0x6c, 0xeb, 0xa7, 0xfa, 0xd9, 0x79, 0x69, 0x98, 0xe3, 0x81, 0x7e, ++ 0x3e, 0x49, 0xfe, 0xa5, 0xf9, 0xf9, 0x28, 0xed, 0x93, 0xf4, 0xf3, 0xce, ++ 0xd0, 0x7b, 0xaf, 0xf8, 0xe5, 0x2f, 0xee, 0x5f, 0xa2, 0x24, 0x2e, 0x91, ++ 0xde, 0xc4, 0xb1, 0xfb, 0xa5, 0x32, 0xae, 0xef, 0xbc, 0x78, 0xf5, 0x26, ++ 0xe5, 0x4f, 0xa7, 0xf9, 0xce, 0x87, 0xb3, 0xd6, 0xf7, 0xbb, 0x63, 0x0e, ++ 0xbe, 0x13, 0xe7, 0xa5, 0xd5, 0x73, 0xaa, 0x71, 0x0b, 0xf8, 0x34, 0x4b, ++ 0xbf, 0x3f, 0x39, 0x92, 0xeb, 0x8b, 0x6d, 0xd6, 0xf5, 0x78, 0x51, 0x16, ++ 0x70, 0xbf, 0xb3, 0xe6, 0xfb, 0xe1, 0x3c, 0x9d, 0xdb, 0x19, 0xde, 0x99, ++ 0x67, 0xe3, 0x02, 0x6f, 0x95, 0x67, 0x0b, 0xf0, 0x7e, 0x46, 0x7d, 0x00, ++ 0xfb, 0x2e, 0xd5, 0xfd, 0x64, 0xdf, 0xdd, 0x7d, 0x43, 0xe0, 0xf9, 0xb8, ++ 0xdb, 0x0b, 0x7c, 0x9e, 0xec, 0xa2, 0xfc, 0x67, 0xfa, 0x15, 0xde, 0x07, ++ 0x92, 0xff, 0x47, 0x88, 0x30, 0xec, 0x6f, 0x98, 0x07, 0xdd, 0x92, 0xfa, ++ 0x6d, 0xca, 0x0f, 0x50, 0x7b, 0x78, 0x5f, 0x10, 0x17, 0xb8, 0x14, 0xca, ++ 0xe3, 0xc1, 0xdf, 0xac, 0x31, 0xdf, 0x4b, 0x46, 0x9f, 0xa9, 0x33, 0xfb, ++ 0x4a, 0x1d, 0xe9, 0x21, 0xfb, 0xfd, 0xd9, 0xbc, 0xdf, 0xd4, 0x9a, 0xfb, ++ 0xd6, 0x3b, 0xf1, 0x1e, 0xe3, 0xa3, 0x92, 0xad, 0x99, 0xff, 0x2f, 0x31, ++ 0xff, 0xaf, 0x70, 0xf0, 0x0a, 0x7f, 0x67, 0xfd, 0x07, 0x74, 0x15, 0x3e, ++ 0xc9, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 usem_int_table_data_e1[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xfb, 0x51, ++ 0xcf, 0xc0, 0xf0, 0x03, 0x8a, 0xb7, 0xc9, 0x33, 0x30, 0x98, 0x29, 0x31, ++ 0x30, 0x24, 0x2a, 0x33, 0x30, 0x9c, 0x01, 0xe2, 0x24, 0x79, 0x84, 0x1c, ++ 0xad, 0xb0, 0x2a, 0x07, 0x65, 0xfa, 0x5f, 0x30, 0x32, 0x30, 0xbc, 0x02, ++ 0xe2, 0x37, 0x40, 0xfc, 0x8e, 0x91, 0x74, 0xfd, 0x3f, 0x85, 0x10, 0xec, ++ 0x87, 0xbc, 0x0c, 0x0c, 0xbf, 0x80, 0xfc, 0x8d, 0x40, 0x5a, 0x4c, 0x80, ++ 0x81, 0xe1, 0x26, 0x90, 0xfd, 0x1b, 0x88, 0xbf, 0x03, 0xf9, 0xe2, 0x7c, ++ 0x0c, 0x0c, 0xca, 0x40, 0x6c, 0x06, 0xe4, 0xbb, 0x00, 0xe9, 0x3c, 0x20, ++ 0xf6, 0x07, 0xe2, 0x3f, 0x40, 0x7e, 0x1b, 0x1f, 0x6e, 0xf3, 0xff, 0x0a, ++ 0xe1, 0xb7, 0xff, 0xaa, 0x00, 0x2a, 0x9f, 0x57, 0x10, 0x95, 0xff, 0x91, ++ 0x1f, 0xbf, 0xfe, 0x0e, 0x41, 0xfc, 0xf2, 0xbc, 0x04, 0xec, 0xc7, 0x86, ++ 0x4f, 0xa8, 0x91, 0x1f, 0x1f, 0x3c, 0xea, 0xb4, 0x4f, 0x33, 0xd4, 0xc4, ++ 0x37, 0x19, 0x50, 0xf9, 0xa7, 0x65, 0x18, 0x18, 0xee, 0xca, 0x32, 0x30, ++ 0x28, 0xc8, 0x43, 0xf8, 0xd7, 0x90, 0xe4, 0x8d, 0x80, 0x62, 0x67, 0x64, ++ 0x20, 0xec, 0xad, 0x62, 0x0c, 0x0c, 0x7b, 0xe5, 0x18, 0x18, 0x2e, 0x33, ++ 0x60, 0x37, 0x77, 0x1b, 0x50, 0x7e, 0x1f, 0x50, 0xde, 0x0e, 0x6a, 0x0e, ++ 0x00, 0xb5, 0xbc, 0x7b, 0x1e, 0x68, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 usem_pram_data_e1[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xe5, 0x7d, ++ 0x0b, 0x78, 0x54, 0xd5, 0xb5, 0xf0, 0x3e, 0x73, 0xce, 0x99, 0x57, 0x66, ++ 0x26, 0x93, 0x84, 0x84, 0x84, 0xf0, 0x98, 0x24, 0x80, 0x3c, 0x02, 0x0e, ++ 0x01, 0x02, 0x48, 0xa8, 0x93, 0x07, 0x14, 0x25, 0xc0, 0x08, 0xa8, 0x68, ++ 0x11, 0x06, 0x51, 0x08, 0x8f, 0x3c, 0x44, 0xed, 0x97, 0x6b, 0xdb, 0xcb, ++ 0xf0, 0x4a, 0xd1, 0xd2, 0x36, 0xd6, 0xb6, 0xd2, 0x5e, 0xd4, 0x01, 0xe1, ++ 0x5e, 0xa4, 0x58, 0x03, 0x44, 0x8d, 0x1a, 0x60, 0x80, 0x60, 0x51, 0xc1, ++ 0x06, 0xeb, 0x03, 0xab, 0xd6, 0x00, 0xb6, 0x08, 0x02, 0x19, 0xa0, 0xea, ++ 0x48, 0xf1, 0xf7, 0x5f, 0x6b, 0xed, 0x7d, 0x92, 0x73, 0x26, 0x33, 0x40, ++ 0x7b, 0xfb, 0xdf, 0xbf, 0xdf, 0xff, 0x8f, 0xb5, 0xdb, 0x7d, 0xce, 0xde, ++ 0xfb, 0xec, 0xbd, 0xde, 0x6b, 0xed, 0xb5, 0x77, 0x54, 0x96, 0xce, 0x58, ++ 0x1f, 0xc6, 0xbe, 0xc1, 0xdf, 0x8d, 0x8c, 0x3d, 0x20, 0x31, 0x86, 0x8f, ++ 0xb4, 0x12, 0x7e, 0xff, 0xeb, 0x9b, 0x0c, 0xc6, 0xa6, 0x5a, 0xe1, 0xbf, ++ 0x64, 0xc6, 0xc6, 0xcb, 0x0e, 0xc6, 0x46, 0x30, 0x36, 0xc5, 0xc1, 0x42, ++ 0x16, 0x68, 0x33, 0xa5, 0x08, 0x1e, 0x76, 0x63, 0xec, 0xcd, 0x4d, 0x52, ++ 0x48, 0xc6, 0x3e, 0xd0, 0x2e, 0x58, 0xc8, 0xd8, 0x22, 0xc6, 0x7f, 0x53, ++ 0x15, 0xd6, 0x24, 0x5d, 0xcf, 0xd8, 0x85, 0xd1, 0x3b, 0xeb, 0x86, 0x79, ++ 0x18, 0x93, 0x7c, 0x3e, 0x56, 0x5b, 0x00, 0xa5, 0xc7, 0xcd, 0x66, 0x61, ++ 0x59, 0xb4, 0xf7, 0x2b, 0xc9, 0xc5, 0x58, 0xf2, 0x68, 0x13, 0x63, 0x03, ++ 0x78, 0x9f, 0x6f, 0xe0, 0xdf, 0x14, 0x9f, 0x9d, 0xc6, 0xd2, 0xea, 0x69, ++ 0x13, 0x53, 0x0d, 0xf5, 0x74, 0x7f, 0x0f, 0x43, 0xfb, 0xee, 0x33, 0x73, ++ 0x0d, 0xef, 0xb3, 0x02, 0x83, 0x0c, 0xef, 0xb3, 0x2b, 0x0a, 0x0c, 0xf5, ++ 0x5e, 0x35, 0x37, 0x18, 0xda, 0xf7, 0xa9, 0x2d, 0x31, 0xd4, 0x73, 0x82, ++ 0x37, 0x1b, 0xda, 0xe7, 0xad, 0x99, 0x66, 0xa8, 0xf7, 0xab, 0xbf, 0xd3, ++ 0xd0, 0xfe, 0xba, 0x75, 0x77, 0x1b, 0xde, 0x0f, 0x0c, 0x2d, 0x32, 0xbc, ++ 0x1f, 0xbc, 0x65, 0xa9, 0xa1, 0x3e, 0xa4, 0xe1, 0x21, 0x43, 0xfb, 0xeb, ++ 0x9b, 0x56, 0x18, 0xde, 0x0f, 0x0b, 0x3f, 0x62, 0x78, 0x3f, 0xfc, 0xe0, ++ 0xcf, 0x0c, 0xf5, 0x91, 0xad, 0xbf, 0x36, 0xb4, 0x1f, 0x75, 0x74, 0xa3, ++ 0xe1, 0xfd, 0x98, 0xb6, 0xad, 0x86, 0xf7, 0x63, 0x3f, 0xdd, 0x61, 0xa8, ++ 0x8f, 0x8b, 0xbc, 0x6c, 0x68, 0x7f, 0x63, 0x74, 0x9f, 0xa1, 0x5e, 0xcc, ++ 0xde, 0x30, 0xb4, 0x2f, 0xb5, 0xfe, 0xc1, 0x50, 0x1f, 0xef, 0xfe, 0xc0, ++ 0xd0, 0xfe, 0xdb, 0x99, 0x27, 0x0c, 0xef, 0x6f, 0xf2, 0x7c, 0x66, 0x78, ++ 0xaf, 0xd1, 0xc1, 0xa4, 0x01, 0x17, 0x0d, 0xcf, 0x27, 0x7b, 0xff, 0x66, ++ 0xe8, 0xa7, 0x30, 0x3f, 0x00, 0x9b, 0x31, 0x33, 0xab, 0xa1, 0xd2, 0xca, ++ 0xea, 0xa9, 0xb4, 0xb3, 0x06, 0x2a, 0x1d, 0xac, 0x95, 0xca, 0xef, 0xf6, ++ 0x0e, 0xdc, 0x49, 0xf4, 0xf9, 0x64, 0xb0, 0x8e, 0x01, 0xdd, 0xad, 0x0c, ++ 0x46, 0xfe, 0x94, 0x06, 0xe5, 0x9b, 0xa3, 0xf3, 0x92, 0x03, 0xf9, 0x38, ++ 0x9a, 0x8f, 0x31, 0xa0, 0xdb, 0x29, 0x7c, 0x68, 0x36, 0xc5, 0xea, 0x08, ++ 0xcb, 0x40, 0x67, 0x16, 0x2b, 0x0b, 0xda, 0x80, 0x14, 0x5c, 0x51, 0xa0, ++ 0xb7, 0x34, 0xa0, 0xbb, 0x28, 0xa3, 0xd2, 0x1d, 0x05, 0x7a, 0x1b, 0x0e, ++ 0x74, 0x17, 0xb5, 0x52, 0x99, 0x1a, 0x4d, 0xa5, 0xe7, 0x69, 0x51, 0x37, ++ 0x95, 0xdd, 0xa2, 0x3d, 0xe8, 0x79, 0x7a, 0x34, 0x93, 0xca, 0x8c, 0x68, ++ 0x2e, 0x95, 0xdd, 0xa3, 0x1e, 0x2a, 0x33, 0xa3, 0x83, 0xa8, 0xcc, 0x8a, ++ 0x0e, 0xa0, 0xb2, 0x47, 0xb4, 0x80, 0xfa, 0x65, 0x47, 0xbd, 0x54, 0xf6, ++ 0x8c, 0xde, 0x40, 0xcf, 0x7b, 0x45, 0x47, 0x53, 0xd9, 0x3b, 0x5a, 0x42, ++ 0xcf, 0xfb, 0x44, 0x7d, 0x54, 0x7a, 0xa2, 0x37, 0x53, 0x99, 0x13, 0x9d, ++ 0x48, 0x65, 0x6e, 0x74, 0x1a, 0xb5, 0xcb, 0x8b, 0xfa, 0xa9, 0xec, 0x1b, ++ 0xbd, 0x93, 0x9e, 0xf7, 0x8b, 0xce, 0xa4, 0xb2, 0x7f, 0xf4, 0x6e, 0x2a, ++ 0xaf, 0x8b, 0x06, 0xa8, 0x1c, 0x10, 0x5d, 0x44, 0xe5, 0xc0, 0x68, 0x05, ++ 0x95, 0x83, 0xa2, 0x4b, 0xa9, 0xdf, 0xe0, 0x68, 0x0d, 0x95, 0xf9, 0xd1, ++ 0x87, 0xe8, 0xf9, 0x90, 0x68, 0x2d, 0x95, 0x43, 0xa3, 0x2b, 0xa8, 0xbc, ++ 0x3e, 0x1a, 0xa4, 0xd2, 0x1b, 0x7d, 0x84, 0xda, 0x0d, 0x8b, 0xae, 0xa1, ++ 0xb2, 0x20, 0xfa, 0x33, 0x7a, 0x3e, 0x3c, 0x5a, 0x4f, 0xe5, 0x88, 0xe8, ++ 0xaf, 0xe9, 0xf9, 0xc8, 0xe8, 0x3a, 0x2a, 0x0b, 0xa3, 0x1b, 0xa9, 0x1c, ++ 0x15, 0x0d, 0x51, 0x39, 0x3a, 0xba, 0x95, 0xca, 0x31, 0xd1, 0x2d, 0x54, ++ 0xde, 0x10, 0xdd, 0x41, 0xfd, 0xc6, 0x46, 0x1b, 0xa8, 0x2c, 0x8a, 0xbe, ++ 0x4c, 0xcf, 0xc7, 0x45, 0x9b, 0xa8, 0xfc, 0x16, 0xd2, 0x5b, 0x1a, 0xd2, ++ 0x5d, 0x98, 0x4a, 0x5f, 0xf4, 0x75, 0x7a, 0x5e, 0x1c, 0x3d, 0x48, 0x65, ++ 0x49, 0xf4, 0x2d, 0x7a, 0x5e, 0x1a, 0x6d, 0xa5, 0xb2, 0x2c, 0xfa, 0x47, ++ 0x7a, 0x3e, 0x3e, 0x7a, 0x94, 0xca, 0x09, 0xd1, 0xe3, 0x54, 0x7e, 0x3b, ++ 0xda, 0x46, 0xe5, 0xc4, 0xe8, 0x69, 0x2a, 0x6f, 0x8a, 0x7e, 0x4a, 0xe5, ++ 0xcd, 0xd1, 0x0b, 0xd4, 0x6f, 0x52, 0x34, 0x42, 0x65, 0x79, 0xf4, 0x12, ++ 0x3d, 0x9f, 0x1c, 0x8d, 0x52, 0xa9, 0xc9, 0x3b, 0x36, 0x5a, 0x3d, 0xd3, ++ 0xa6, 0xd1, 0x5f, 0x2e, 0xfe, 0xff, 0x2c, 0xf7, 0x5f, 0x06, 0x83, 0x5c, ++ 0x62, 0x01, 0xd3, 0x37, 0x50, 0x32, 0x07, 0xd0, 0xc1, 0x98, 0xce, 0xf6, ++ 0xb1, 0x25, 0x48, 0x3b, 0x92, 0x93, 0x2a, 0xd0, 0x55, 0x12, 0xd0, 0x77, ++ 0x0a, 0xc8, 0x42, 0x94, 0x87, 0x53, 0x6a, 0xa4, 0xd0, 0xb7, 0x73, 0x80, ++ 0x3e, 0xba, 0xb5, 0xb5, 0x60, 0x5d, 0x1d, 0x6d, 0xf1, 0x58, 0xa0, 0x7e, ++ 0x17, 0x8b, 0xa8, 0x48, 0xbf, 0x1f, 0xb1, 0x36, 0x27, 0xca, 0xd3, 0xbd, ++ 0x63, 0x4e, 0xf6, 0x6c, 0x03, 0x7a, 0x7d, 0x33, 0x3d, 0xdc, 0x0b, 0x88, ++ 0x1b, 0x7f, 0x24, 0x6f, 0x55, 0x9c, 0x53, 0x1e, 0xca, 0xdb, 0x33, 0x4a, ++ 0x1b, 0x3c, 0x9f, 0xd2, 0x6d, 0x5f, 0x7a, 0xc0, 0x81, 0xfd, 0x81, 0x37, ++ 0x0a, 0x90, 0xbc, 0xe1, 0xfb, 0x48, 0xdf, 0x40, 0x8e, 0x38, 0xce, 0x5d, ++ 0x0a, 0x0b, 0xba, 0x60, 0xaa, 0x47, 0x70, 0x84, 0x31, 0xd4, 0x2e, 0x6c, ++ 0x81, 0xfa, 0xac, 0x72, 0xe6, 0x2b, 0x80, 0xf6, 0x75, 0x63, 0x2c, 0x33, ++ 0x43, 0xf0, 0x9d, 0xba, 0x02, 0x7f, 0x85, 0x1f, 0xca, 0x1f, 0xe7, 0xf8, ++ 0x67, 0x62, 0xf9, 0x3a, 0x32, 0x0f, 0xcc, 0x7f, 0xbf, 0x28, 0x8f, 0x30, ++ 0x13, 0x95, 0x3f, 0xee, 0xed, 0xa6, 0x72, 0xd6, 0x7d, 0xfd, 0x38, 0x3f, ++ 0x95, 0x01, 0x10, 0xb3, 0xae, 0x0e, 0x87, 0xf4, 0x0c, 0xde, 0x8f, 0x39, ++ 0x22, 0xbd, 0xfd, 0x43, 0xae, 0xbd, 0x9f, 0xc2, 0xa0, 0xdf, 0xc8, 0xce, ++ 0xf6, 0xcf, 0x30, 0xff, 0x3b, 0xf8, 0x3c, 0x58, 0xc2, 0x06, 0xd4, 0x38, ++ 0x3a, 0xdb, 0xc1, 0xf3, 0xa3, 0xd8, 0x2e, 0xce, 0xf3, 0x0f, 0xe2, 0x3d, ++ 0x6f, 0x30, 0x81, 0x20, 0x00, 0x7d, 0x15, 0x4c, 0x35, 0x87, 0x36, 0xa3, ++ 0x7e, 0x62, 0x9e, 0xe4, 0x5b, 0x70, 0x5e, 0x56, 0x4f, 0xf2, 0x34, 0x67, ++ 0xe2, 0x79, 0x3d, 0xbc, 0x2c, 0x33, 0x5f, 0xe9, 0xab, 0x9f, 0x67, 0x88, ++ 0xe6, 0xf7, 0xb0, 0xc4, 0x66, 0x36, 0xd0, 0xf8, 0xbe, 0xcc, 0x69, 0x43, ++ 0x68, 0x7c, 0xc2, 0x77, 0x30, 0xd5, 0x1a, 0xda, 0x9c, 0x43, 0xa8, 0x30, ++ 0xd0, 0xcb, 0x5f, 0x11, 0x9e, 0xd0, 0x2f, 0xdf, 0xee, 0x6f, 0xa7, 0xf5, ++ 0x41, 0x3f, 0xbf, 0x13, 0xe1, 0xe3, 0xbe, 0x26, 0xb8, 0x40, 0xbf, 0x2f, ++ 0x08, 0x9e, 0x0a, 0xf4, 0x1b, 0x72, 0xed, 0xfd, 0x12, 0x97, 0xf5, 0x4c, ++ 0xcc, 0xc3, 0x43, 0xe3, 0x89, 0xe7, 0xd5, 0x16, 0x16, 0x94, 0x00, 0x4e, ++ 0x91, 0xcd, 0xce, 0xd0, 0xc6, 0x1c, 0x5c, 0x93, 0x87, 0xe4, 0x67, 0x85, ++ 0x5b, 0x08, 0xd0, 0x6e, 0x00, 0x0c, 0xd0, 0xeb, 0x15, 0x29, 0x08, 0x42, ++ 0xc6, 0x5a, 0x76, 0x27, 0x85, 0x4d, 0xd0, 0xbe, 0x68, 0xb3, 0x73, 0x23, ++ 0xda, 0x01, 0xed, 0x25, 0xc1, 0x8c, 0xa9, 0x08, 0x87, 0x8d, 0x2a, 0xdb, ++ 0x0c, 0x4d, 0x56, 0xec, 0xfe, 0xd1, 0xbb, 0xff, 0x01, 0xf5, 0xa2, 0x0d, ++ 0x2a, 0xb3, 0x40, 0x7d, 0xe1, 0xc5, 0x9f, 0x17, 0x32, 0xa0, 0xa3, 0xeb, ++ 0x24, 0x89, 0x7f, 0x3f, 0xe8, 0xdb, 0xdb, 0x17, 0xc6, 0x0f, 0x30, 0xed, ++ 0xe7, 0x93, 0x70, 0xfc, 0x05, 0x8c, 0x8f, 0xdf, 0x2e, 0x09, 0xb8, 0x6e, ++ 0x4e, 0x26, 0xbc, 0x7d, 0x5a, 0xb6, 0xa9, 0x6e, 0x2c, 0x94, 0x6d, 0xbb, ++ 0x2a, 0xcb, 0x19, 0xc8, 0xf1, 0x93, 0x00, 0xd6, 0x2c, 0xa0, 0xef, 0x85, ++ 0x76, 0xa6, 0x60, 0x39, 0xab, 0x66, 0xbb, 0x99, 0xe8, 0x34, 0xa8, 0x7e, ++ 0xd2, 0xa6, 0xe9, 0x17, 0xe2, 0x67, 0xa5, 0xb3, 0x2e, 0x77, 0xad, 0x2f, ++ 0xc0, 0xba, 0xc6, 0xff, 0xb0, 0xee, 0x85, 0x21, 0xb5, 0xb3, 0x0e, 0xff, ++ 0x2e, 0xde, 0x62, 0xac, 0xeb, 0xe0, 0x45, 0x76, 0x50, 0xe4, 0xbc, 0x12, ++ 0xda, 0x48, 0x74, 0x95, 0xcd, 0xe1, 0xa3, 0xc1, 0xcb, 0x97, 0xcd, 0xe1, ++ 0x27, 0xe0, 0x55, 0x76, 0x5e, 0x09, 0x9a, 0xba, 0x11, 0xbc, 0x42, 0x28, ++ 0x07, 0x92, 0x25, 0x0f, 0xc1, 0xa1, 0xe2, 0xbc, 0x12, 0x96, 0x61, 0x9c, ++ 0x0a, 0x80, 0x23, 0xb2, 0x60, 0xc5, 0xae, 0x87, 0x33, 0x10, 0x4e, 0x8b, ++ 0xb7, 0xd8, 0xdc, 0x9f, 0xe8, 0xbe, 0x5b, 0xd9, 0x90, 0x62, 0xa8, 0x57, ++ 0x37, 0x65, 0xb9, 0x3f, 0xd1, 0xe9, 0xd1, 0x0b, 0x07, 0x9f, 0x76, 0xe1, ++ 0xfa, 0x97, 0x66, 0x9a, 0xdc, 0x9f, 0x80, 0x7c, 0x3b, 0xb3, 0xcc, 0x97, ++ 0xf6, 0x09, 0xa0, 0xec, 0xdc, 0xb2, 0x89, 0x54, 0x6a, 0xf4, 0x51, 0xd9, ++ 0x90, 0xe3, 0x76, 0x18, 0xc6, 0x31, 0xd6, 0x2f, 0xd4, 0x4b, 0x13, 0x1b, ++ 0x48, 0x7f, 0x7a, 0x92, 0x67, 0x0c, 0x49, 0x4c, 0x67, 0x4b, 0x33, 0xcd, ++ 0xee, 0x4f, 0x80, 0x55, 0x4f, 0x6f, 0xe1, 0xfa, 0xf6, 0xf4, 0x32, 0xab, ++ 0x1b, 0xbf, 0x73, 0x66, 0x99, 0xdb, 0xcd, 0xbf, 0x9b, 0x49, 0xa5, 0x06, ++ 0xaf, 0x25, 0xb5, 0x76, 0x6a, 0xaf, 0xcd, 0x2f, 0xd1, 0xb8, 0xff, 0xec, ++ 0xf9, 0x31, 0xd6, 0xc8, 0x4e, 0x58, 0x51, 0x9e, 0xc3, 0xbb, 0xbc, 0xc4, ++ 0xed, 0x13, 0xf2, 0x93, 0xf2, 0x57, 0x33, 0xf1, 0x49, 0xb3, 0xfa, 0x05, ++ 0xd2, 0x8d, 0x15, 0xfe, 0xfd, 0xc6, 0x44, 0x74, 0x44, 0x75, 0x6d, 0xdc, ++ 0xea, 0x06, 0x39, 0x68, 0xb9, 0x1e, 0x9f, 0x6f, 0x33, 0x7c, 0x0f, 0xfa, ++ 0x79, 0xfe, 0xa2, 0xd3, 0x2f, 0x89, 0xf9, 0x56, 0x61, 0x7f, 0xd1, 0xd1, ++ 0xe5, 0xfd, 0x38, 0x00, 0xf1, 0xa9, 0x95, 0xf0, 0x1c, 0x80, 0x11, 0x93, ++ 0x61, 0xbc, 0x76, 0xc5, 0xb1, 0x06, 0xed, 0xa8, 0xc9, 0x82, 0x7e, 0xaa, ++ 0xb1, 0x1d, 0xc8, 0x83, 0x4a, 0x6b, 0x9b, 0x39, 0x00, 0x8f, 0xce, 0x36, ++ 0x72, 0x7c, 0x24, 0xfa, 0xce, 0xe9, 0x65, 0x5b, 0xb2, 0x51, 0xae, 0x55, ++ 0x58, 0xeb, 0xcd, 0x28, 0xac, 0x2a, 0x1a, 0x06, 0x96, 0x21, 0x3f, 0x9d, ++ 0x6d, 0x5c, 0x99, 0x81, 0xfa, 0x65, 0xb1, 0x7c, 0xe1, 0xbb, 0xfe, 0x38, ++ 0xfd, 0x7f, 0xac, 0xf1, 0x6d, 0x48, 0x8d, 0x18, 0xf5, 0x65, 0x48, 0xcc, ++ 0x13, 0xc6, 0x35, 0xf0, 0x19, 0x73, 0x74, 0xac, 0x1b, 0xea, 0x67, 0x4c, ++ 0xf0, 0x29, 0x47, 0xd7, 0x71, 0x1f, 0x97, 0xb8, 0xde, 0xa9, 0xda, 0x76, ++ 0x64, 0xc2, 0x58, 0x98, 0x7f, 0x55, 0xd3, 0x79, 0x33, 0xce, 0x63, 0xb2, ++ 0x14, 0x78, 0x5c, 0x4a, 0xef, 0x5c, 0xbf, 0x84, 0xeb, 0x87, 0x71, 0x16, ++ 0x6d, 0x39, 0x46, 0x7c, 0xfe, 0xa9, 0x1a, 0xec, 0xff, 0xbd, 0x9c, 0x2b, ++ 0xc0, 0xb3, 0xcb, 0x3c, 0x1d, 0x99, 0x7f, 0x49, 0xd2, 0xcd, 0x2f, 0x08, ++ 0x86, 0x24, 0xf0, 0xeb, 0xdd, 0xa3, 0x05, 0xbf, 0x32, 0xcf, 0xed, 0x1f, ++ 0x00, 0x7f, 0x9e, 0x7a, 0x43, 0x65, 0x8f, 0xc0, 0x3c, 0xd8, 0x65, 0x68, ++ 0x05, 0xef, 0x7b, 0x8b, 0xb7, 0xf7, 0x30, 0xbf, 0x0b, 0xe1, 0x75, 0x77, ++ 0xe3, 0x62, 0x92, 0x3f, 0xa7, 0x50, 0xfe, 0xa0, 0x1e, 0x66, 0xf5, 0x85, ++ 0x48, 0x1f, 0x67, 0x99, 0x69, 0x22, 0xae, 0xef, 0x2c, 0x7b, 0xcb, 0x35, ++ 0x5c, 0x07, 0xbf, 0x7d, 0x92, 0x59, 0xc0, 0x07, 0x4c, 0x59, 0x90, 0x07, ++ 0x16, 0xfa, 0x14, 0xc1, 0x2d, 0x0b, 0xf5, 0x80, 0xa5, 0xa2, 0xae, 0x55, ++ 0x1e, 0x8a, 0xcf, 0x95, 0xa0, 0x90, 0x4b, 0xd2, 0x37, 0x24, 0x4f, 0x42, ++ 0x12, 0xe9, 0x89, 0x0a, 0xfe, 0x3c, 0xc8, 0xac, 0xcb, 0x69, 0x1d, 0x6b, ++ 0xb8, 0x3c, 0x0a, 0xc2, 0x3f, 0x58, 0xbf, 0xb7, 0xde, 0x28, 0x9f, 0x16, ++ 0xac, 0x33, 0xd6, 0xe7, 0xb3, 0x69, 0x19, 0x0a, 0xc8, 0x97, 0xf9, 0x3f, ++ 0x57, 0x61, 0x44, 0x90, 0x6f, 0x7a, 0xf9, 0x07, 0xf0, 0x7b, 0x46, 0xe2, ++ 0x7a, 0x77, 0x01, 0xab, 0xa9, 0x73, 0xc3, 0xfc, 0x9f, 0x30, 0x03, 0x9e, ++ 0x60, 0xfe, 0x77, 0xbb, 0x99, 0x92, 0x0d, 0xeb, 0xab, 0x7c, 0xf1, 0x89, ++ 0xc2, 0xb9, 0x50, 0x7f, 0x4d, 0xe2, 0x7a, 0xec, 0xf4, 0x32, 0x98, 0x7e, ++ 0x7f, 0x18, 0x27, 0x95, 0xaf, 0x7f, 0x51, 0x6d, 0xc8, 0xec, 0xcb, 0xef, ++ 0xba, 0xbe, 0x13, 0x8d, 0xc3, 0x6f, 0x1b, 0xcb, 0x68, 0x3c, 0x92, 0x93, ++ 0xc1, 0x45, 0x9a, 0xfe, 0x65, 0x1e, 0xa5, 0x90, 0xa4, 0x25, 0x18, 0xb9, ++ 0x89, 0xd7, 0x9f, 0xdd, 0x28, 0xfb, 0x6c, 0x2e, 0x6c, 0x07, 0xcf, 0x75, ++ 0xf2, 0x79, 0xde, 0x1a, 0xe3, 0xfa, 0xae, 0xb6, 0xfe, 0xd8, 0xf5, 0x32, ++ 0xf6, 0x33, 0xa2, 0xb7, 0x45, 0x5b, 0x6e, 0x61, 0x48, 0x67, 0xda, 0x7a, ++ 0x34, 0x7c, 0x69, 0xeb, 0x51, 0xb7, 0x48, 0xbe, 0x50, 0x1c, 0x3e, 0x68, ++ 0x13, 0xf4, 0xaa, 0xc9, 0xb5, 0x88, 0x80, 0x9f, 0x66, 0x77, 0x7c, 0x1e, ++ 0x53, 0xbf, 0x14, 0x53, 0xff, 0x26, 0xa6, 0xae, 0xd1, 0xb7, 0x2a, 0xf8, ++ 0x1b, 0xe8, 0xfe, 0x73, 0x69, 0x24, 0xf2, 0x73, 0x64, 0x02, 0xa7, 0x93, ++ 0x36, 0xae, 0xd7, 0x44, 0x3b, 0x73, 0x67, 0xbb, 0x4b, 0x57, 0x6a, 0x67, ++ 0x11, 0xfc, 0x02, 0xed, 0xbe, 0xb9, 0x52, 0x3b, 0x5b, 0xe7, 0x78, 0x8a, ++ 0x29, 0xbd, 0x6b, 0xbb, 0xca, 0x17, 0x9f, 0x7d, 0x21, 0x08, 0xf4, 0xbd, ++ 0xe8, 0xb9, 0x5f, 0xb8, 0x18, 0xd0, 0xe3, 0x29, 0xa5, 0x3e, 0xc3, 0x0b, ++ 0xcf, 0x97, 0x6c, 0x5e, 0xed, 0x42, 0x38, 0x7d, 0xaa, 0x04, 0x5d, 0x48, ++ 0x37, 0xa7, 0x42, 0xf2, 0xc4, 0x78, 0xf0, 0x1a, 0x63, 0x92, 0x34, 0x7b, ++ 0xc3, 0x21, 0x01, 0xde, 0xab, 0x34, 0xfa, 0x2f, 0x5a, 0x3e, 0x05, 0xf5, ++ 0xfb, 0x17, 0x9b, 0x55, 0xf7, 0x23, 0x80, 0x97, 0xea, 0x2d, 0x96, 0xb0, ++ 0x05, 0xf0, 0x5d, 0xd5, 0xb8, 0xb0, 0x9c, 0x0d, 0xa5, 0xfa, 0x31, 0x5e, ++ 0xff, 0xe1, 0x79, 0xa4, 0x8f, 0xea, 0x26, 0xf5, 0xb8, 0x1e, 0xaf, 0x8b, ++ 0xfe, 0xeb, 0x17, 0x19, 0x1e, 0x27, 0xe1, 0x21, 0xdb, 0x84, 0x36, 0x30, ++ 0x0b, 0x67, 0x33, 0x28, 0xab, 0x36, 0xfd, 0x79, 0x02, 0xda, 0xd1, 0xd5, ++ 0x2c, 0x42, 0xf4, 0x1c, 0xdb, 0x0f, 0xbf, 0x8f, 0xae, 0x1d, 0xc8, 0xeb, ++ 0xb9, 0xe6, 0xe4, 0xae, 0xef, 0x35, 0xbf, 0xb1, 0x9a, 0x3f, 0x62, 0xd5, ++ 0x8d, 0x3f, 0x3a, 0x8f, 0x7e, 0x63, 0x35, 0x53, 0x8e, 0xeb, 0xe9, 0xa8, ++ 0x02, 0x69, 0x19, 0xec, 0xbc, 0x41, 0x26, 0x67, 0x37, 0xf4, 0x17, 0xd8, ++ 0x28, 0x36, 0x0a, 0xe5, 0x8a, 0x06, 0x07, 0x16, 0x4a, 0x27, 0xb9, 0xbc, ++ 0xf2, 0x99, 0xc7, 0x87, 0x1e, 0x83, 0x79, 0x9c, 0xd9, 0xf4, 0x86, 0x4b, ++ 0xd2, 0xc1, 0x07, 0x2c, 0x24, 0x82, 0xcb, 0x85, 0x86, 0x79, 0x1f, 0xa7, ++ 0x5d, 0x41, 0x2f, 0x9c, 0x03, 0xfa, 0x64, 0xfd, 0xf5, 0xfd, 0x42, 0xd4, ++ 0xcf, 0xd3, 0x04, 0x13, 0xe8, 0x0e, 0xd5, 0x66, 0x5e, 0x2e, 0x51, 0xc3, ++ 0xae, 0xb1, 0x00, 0xcf, 0x25, 0x1b, 0x54, 0x2f, 0x50, 0x26, 0x5b, 0xf2, ++ 0xec, 0xd3, 0xff, 0xf9, 0x6b, 0xe0, 0x3b, 0xf6, 0xbe, 0xc5, 0xdb, 0x0f, ++ 0xe0, 0xbd, 0xf8, 0xd9, 0x03, 0xef, 0xde, 0x00, 0xf5, 0xc5, 0xdb, 0xd5, ++ 0x6e, 0xe5, 0x7c, 0x19, 0x0e, 0x29, 0xa3, 0x13, 0x1f, 0xd5, 0xf0, 0x2f, ++ 0xc6, 0x65, 0x34, 0xf8, 0x2f, 0xda, 0x79, 0xc0, 0xec, 0x19, 0xc2, 0x9f, ++ 0x7f, 0x3f, 0xb5, 0x13, 0x0f, 0x8b, 0xb7, 0xef, 0x35, 0xb3, 0x21, 0x5d, ++ 0xe1, 0x56, 0xda, 0xb0, 0xd7, 0xdc, 0xe6, 0x88, 0x83, 0x8f, 0x86, 0x63, ++ 0x13, 0xd0, 0x9e, 0x59, 0xf9, 0xcc, 0x97, 0x66, 0xc4, 0xf7, 0xa9, 0xdd, ++ 0x12, 0xeb, 0x9e, 0xd3, 0xb5, 0x7f, 0xc5, 0x86, 0x03, 0x64, 0xbf, 0x20, ++ 0x9c, 0x08, 0x7f, 0x02, 0x3f, 0x1d, 0xf8, 0xea, 0x82, 0xa7, 0xf0, 0x94, ++ 0x97, 0x47, 0x50, 0x3b, 0x37, 0xca, 0xeb, 0x44, 0x78, 0x72, 0xa2, 0xae, ++ 0x1e, 0x49, 0x74, 0xfc, 0xdb, 0x97, 0xe1, 0xfb, 0x15, 0x7f, 0xb4, 0x78, ++ 0x71, 0xfd, 0x15, 0xbf, 0xbd, 0xdf, 0x85, 0xeb, 0x38, 0xa9, 0xd4, 0x70, ++ 0x7a, 0x7e, 0x62, 0x75, 0x86, 0x0f, 0xbe, 0x5b, 0xa1, 0x06, 0x33, 0xdc, ++ 0x54, 0xf2, 0xe7, 0x15, 0x4f, 0x3e, 0x48, 0x74, 0xb6, 0xe0, 0xc8, 0x83, ++ 0x64, 0x97, 0x01, 0x7d, 0x64, 0x99, 0x48, 0x67, 0x04, 0xb3, 0x70, 0x7d, ++ 0xf7, 0xae, 0xbf, 0x95, 0xd6, 0x37, 0x9f, 0x05, 0x88, 0xde, 0x2a, 0x9e, ++ 0x90, 0xfd, 0x21, 0x94, 0x03, 0x0a, 0x9b, 0xb8, 0x3d, 0x0e, 0x3f, 0x3c, ++ 0x27, 0xf8, 0xe1, 0xe4, 0x46, 0x90, 0x94, 0xb0, 0xbe, 0x93, 0x28, 0x1f, ++ 0xd1, 0xce, 0x7d, 0x4b, 0x16, 0xf2, 0xf1, 0x3e, 0xb2, 0x23, 0x1f, 0x14, ++ 0x6b, 0x05, 0x4b, 0x86, 0xea, 0x9f, 0x5b, 0x39, 0x9e, 0xea, 0x4c, 0x26, ++ 0x2d, 0x2e, 0x67, 0x35, 0xd0, 0xe9, 0xa6, 0x1f, 0x92, 0x1c, 0x3d, 0xdd, ++ 0xcb, 0xd7, 0xdd, 0x9d, 0x4f, 0x70, 0xd0, 0xe4, 0x26, 0xc9, 0x53, 0xf9, ++ 0xc8, 0xf8, 0xee, 0x1c, 0x3f, 0x5c, 0xfe, 0x52, 0x3f, 0xa0, 0xbb, 0x52, ++ 0x7c, 0x8e, 0xed, 0x5b, 0x55, 0x9f, 0x6d, 0xa8, 0xa1, 0x9f, 0x90, 0x97, ++ 0xfc, 0xfb, 0x0f, 0x88, 0xef, 0xc3, 0xbc, 0xed, 0x68, 0x7f, 0x9c, 0xcc, ++ 0xe0, 0x7a, 0x22, 0x76, 0x7d, 0x7f, 0x34, 0x69, 0xf2, 0x11, 0xf4, 0xab, ++ 0x8e, 0xbe, 0x74, 0x7c, 0xcd, 0xf9, 0x7c, 0xd3, 0xc3, 0x9c, 0xaf, 0x35, ++ 0x3e, 0x0f, 0xdd, 0x32, 0x11, 0xdf, 0xff, 0xf5, 0x6d, 0xce, 0x3f, 0xd8, ++ 0x0f, 0xf5, 0x0f, 0xcc, 0x2b, 0xdc, 0x9d, 0xde, 0xef, 0x9d, 0x21, 0x91, ++ 0x1c, 0xb0, 0xb0, 0x70, 0x3c, 0x7e, 0xde, 0xa4, 0x0a, 0x7e, 0x36, 0xbe, ++ 0x07, 0x09, 0x4d, 0xf6, 0x1b, 0xcc, 0x5b, 0x91, 0x92, 0xf5, 0x74, 0x02, ++ 0xe3, 0xa7, 0x12, 0xfc, 0xc9, 0x2e, 0x99, 0xff, 0x73, 0xe8, 0xa7, 0xb3, ++ 0xa7, 0xab, 0xf1, 0x7b, 0xd4, 0xce, 0xdc, 0xf9, 0x3c, 0xa7, 0x93, 0x6f, ++ 0x17, 0x08, 0xfe, 0xdf, 0x8a, 0xfc, 0x9f, 0xd4, 0xc9, 0xff, 0x6c, 0x7d, ++ 0xfa, 0x35, 0xf9, 0x67, 0x4b, 0xd4, 0xd0, 0x7f, 0xfe, 0x1a, 0xf9, 0x15, ++ 0xf8, 0x33, 0xe8, 0x41, 0x7e, 0x55, 0xfd, 0xb8, 0xee, 0xcf, 0xb6, 0xed, ++ 0x7f, 0xf7, 0x4e, 0xa0, 0xeb, 0xcf, 0x1a, 0x34, 0x3e, 0x35, 0xca, 0xcd, ++ 0x58, 0x3e, 0xad, 0xd8, 0xf1, 0x20, 0x43, 0xfa, 0x8c, 0xe5, 0xd3, 0xcf, ++ 0x7a, 0xd6, 0xb0, 0xb8, 0x7c, 0x0a, 0xcf, 0xe3, 0xf2, 0x69, 0xcf, 0xb6, ++ 0xff, 0x11, 0xb9, 0xa9, 0xc1, 0xed, 0x48, 0x0c, 0xdc, 0x40, 0x0e, 0x3e, ++ 0xf5, 0xb2, 0x27, 0x31, 0xfc, 0x62, 0xe5, 0x60, 0xb5, 0xc9, 0x13, 0x57, ++ 0x0e, 0xc2, 0xef, 0x6d, 0x56, 0xd8, 0x95, 0xee, 0x34, 0x7a, 0xd3, 0xe8, ++ 0x6c, 0xd1, 0x6f, 0x2a, 0xfb, 0xa0, 0xbc, 0xe9, 0xa0, 0x47, 0x8d, 0xde, ++ 0x3a, 0xe8, 0x51, 0xa3, 0xb7, 0xd8, 0x75, 0x1a, 0xe1, 0x16, 0xfb, 0x7e, ++ 0x3d, 0xca, 0x1b, 0x9d, 0x7d, 0xa0, 0xae, 0x60, 0x41, 0x27, 0xe0, 0x39, ++ 0xb2, 0x4b, 0x26, 0x3f, 0xb1, 0xdd, 0x13, 0x71, 0xa5, 0xc2, 0x77, 0x57, ++ 0xdb, 0xd8, 0x1c, 0xb4, 0xb3, 0xdb, 0xdd, 0xa2, 0x9e, 0xc2, 0xeb, 0x91, ++ 0x74, 0x73, 0x1d, 0xca, 0x05, 0xed, 0x79, 0xc4, 0xc6, 0xe3, 0x0d, 0xed, ++ 0xfe, 0x88, 0x2b, 0x45, 0x67, 0x3f, 0x1f, 0x6b, 0x96, 0x5d, 0x1e, 0x78, ++ 0xdf, 0x16, 0x62, 0x13, 0xe3, 0xd9, 0xd5, 0x20, 0x71, 0xe9, 0xfb, 0x6d, ++ 0x2c, 0xd1, 0xfb, 0xe5, 0x04, 0xbf, 0xf1, 0xb2, 0xa3, 0x77, 0xed, 0x08, ++ 0xf4, 0xab, 0x64, 0x2f, 0xda, 0x6e, 0xf7, 0x2c, 0xbf, 0xdd, 0x85, 0x21, ++ 0x8b, 0xf6, 0xe6, 0xbc, 0xa9, 0x33, 0xe1, 0xf9, 0xbd, 0xaf, 0xc9, 0x14, ++ 0xd3, 0x68, 0xb7, 0xbb, 0x86, 0xe2, 0xbc, 0xc0, 0x6f, 0x57, 0xb2, 0x00, ++ 0xbe, 0xf3, 0x04, 0x9e, 0x3f, 0x65, 0xc1, 0x5f, 0x16, 0xc1, 0xba, 0xe6, ++ 0x35, 0x73, 0xbb, 0xf8, 0x9e, 0xb5, 0x46, 0x78, 0xcc, 0x77, 0x3c, 0x60, ++ 0x46, 0x39, 0x03, 0xf6, 0x67, 0x27, 0x1d, 0xe8, 0xe8, 0x45, 0xdb, 0x27, ++ 0xa8, 0x58, 0x6f, 0x7c, 0xbf, 0x88, 0xad, 0x25, 0x7c, 0x2d, 0x8a, 0xa1, ++ 0x9f, 0x80, 0xf0, 0x77, 0xb2, 0x64, 0x41, 0x3f, 0xc3, 0xd8, 0x30, 0xe1, ++ 0x6f, 0x98, 0x70, 0xbc, 0xa5, 0x42, 0x4e, 0x8d, 0x97, 0xf3, 0xa7, 0xce, ++ 0x04, 0xb8, 0xb7, 0x1f, 0x94, 0x99, 0x05, 0xea, 0x17, 0x9a, 0x65, 0x56, ++ 0x87, 0xeb, 0xdc, 0x26, 0x85, 0x18, 0xf2, 0x71, 0x30, 0x9d, 0xe8, 0xb0, ++ 0x0a, 0xe4, 0x03, 0xd3, 0xf9, 0x85, 0x67, 0x90, 0xce, 0xcc, 0x89, 0xf9, ++ 0xf7, 0xcc, 0xf3, 0x1f, 0x15, 0x7e, 0x0f, 0x9a, 0x2c, 0x79, 0xe1, 0x83, ++ 0xa1, 0xff, 0x01, 0xe5, 0x99, 0x17, 0xde, 0xef, 0xff, 0x0a, 0xd6, 0x5f, ++ 0x7c, 0xaf, 0xf7, 0x07, 0xac, 0x6b, 0xfb, 0xd2, 0xdd, 0x5f, 0xcd, 0x46, ++ 0xf9, 0xde, 0xbe, 0xdb, 0xc2, 0x28, 0x4e, 0xb2, 0xfb, 0x77, 0xbd, 0xbf, ++ 0x87, 0xf5, 0x97, 0x2d, 0x5e, 0x8a, 0x73, 0xac, 0xb0, 0xf0, 0xf8, 0xd4, ++ 0x6e, 0x67, 0xa8, 0x1f, 0xbe, 0xef, 0x05, 0xf8, 0x46, 0x7d, 0xb9, 0xeb, ++ 0xcb, 0xa1, 0x6d, 0xa4, 0x6f, 0x56, 0x11, 0x9e, 0xca, 0x64, 0xee, 0x47, ++ 0x5c, 0x68, 0xfe, 0xdb, 0x9f, 0xa4, 0x6e, 0x58, 0xc2, 0xaa, 0x50, 0x8f, ++ 0xee, 0x4e, 0x22, 0xfb, 0xba, 0xfa, 0x65, 0x5b, 0x08, 0x9d, 0xce, 0xf6, ++ 0x5d, 0x5f, 0x16, 0x06, 0x1c, 0xff, 0xbc, 0xf5, 0x54, 0x99, 0x59, 0x80, ++ 0xe8, 0xcf, 0xc9, 0x66, 0xee, 0x40, 0x7a, 0x4d, 0x01, 0xc4, 0xc1, 0xf7, ++ 0xab, 0x5f, 0x19, 0xf3, 0xf4, 0x72, 0xf8, 0x7e, 0x65, 0xe3, 0x5e, 0xf3, ++ 0x3c, 0x78, 0x5f, 0xba, 0xe7, 0xeb, 0xa1, 0x28, 0x57, 0xda, 0x77, 0x70, ++ 0xfb, 0xe0, 0x9c, 0xda, 0xf6, 0x24, 0xf3, 0x32, 0x36, 0x55, 0xfe, 0xc5, ++ 0x72, 0x15, 0xf0, 0x75, 0x0e, 0x6d, 0xb5, 0x1e, 0x20, 0x97, 0xe4, 0x77, ++ 0x8b, 0x83, 0x8e, 0x78, 0x70, 0xe1, 0x70, 0x68, 0x07, 0x38, 0xe0, 0xba, ++ 0x00, 0x2e, 0x15, 0x28, 0x0f, 0x13, 0xc1, 0x63, 0xfe, 0xbf, 0x2c, 0x3c, ++ 0xce, 0xcf, 0xc6, 0xef, 0x2f, 0x69, 0x1e, 0xc5, 0xe4, 0x1c, 0x3d, 0x5c, ++ 0x24, 0x1f, 0x7f, 0xee, 0x0c, 0x59, 0x25, 0x5a, 0x3f, 0x7f, 0xbe, 0xfb, ++ 0xcb, 0xa1, 0x28, 0x77, 0x3f, 0x6b, 0x58, 0x4e, 0xfa, 0xfb, 0x6a, 0xeb, ++ 0x5e, 0x8d, 0xeb, 0x4e, 0xff, 0x7f, 0x69, 0xdd, 0x52, 0xf8, 0x5a, 0xd6, ++ 0xbd, 0xe9, 0x5f, 0x76, 0xdd, 0x9c, 0xfe, 0x07, 0xc9, 0x5c, 0x1f, 0xc5, ++ 0xf2, 0x41, 0x57, 0x3a, 0x7f, 0xf1, 0xbb, 0x54, 0xff, 0xad, 0xd3, 0x4b, ++ 0xf3, 0xbd, 0x46, 0xfe, 0x6f, 0xf9, 0x97, 0x5d, 0xff, 0x3f, 0x88, 0xf7, ++ 0x1d, 0x12, 0xed, 0xc7, 0x5d, 0x0d, 0xef, 0x27, 0xfe, 0x65, 0xd7, 0x7d, ++ 0x35, 0xbc, 0xbf, 0x26, 0xf0, 0xee, 0x74, 0x63, 0xbc, 0xb7, 0x7d, 0xd7, ++ 0xd7, 0xbd, 0x99, 0x6e, 0xfd, 0x57, 0x5b, 0xb7, 0x49, 0xf9, 0x57, 0x95, ++ 0x6f, 0x57, 0x5e, 0xb7, 0x66, 0xf7, 0xb4, 0x9a, 0x6a, 0xdc, 0x23, 0x60, ++ 0x7e, 0xef, 0xb3, 0xfa, 0x5b, 0x73, 0xa0, 0xfc, 0xbd, 0xef, 0x62, 0x37, ++ 0x74, 0x47, 0x81, 0x07, 0xfc, 0xf1, 0xfc, 0x86, 0x02, 0x85, 0xfb, 0x0d, ++ 0x16, 0x8c, 0x33, 0x61, 0xc3, 0x5b, 0x25, 0x2d, 0x5e, 0xd4, 0x6a, 0xd8, ++ 0xc7, 0xed, 0x59, 0x41, 0x76, 0xc6, 0x14, 0xdf, 0x8f, 0xc9, 0x3e, 0x60, ++ 0x4a, 0x4d, 0x6b, 0x31, 0xb4, 0x6f, 0x2d, 0x99, 0xe7, 0x7d, 0x84, 0x5a, ++ 0x14, 0x1c, 0x0d, 0x60, 0x7d, 0xc6, 0x38, 0x51, 0x37, 0xfa, 0x53, 0x6f, ++ 0x4a, 0xcc, 0x27, 0x81, 0x1d, 0x3b, 0xa5, 0x64, 0xd2, 0x41, 0xb4, 0xef, ++ 0xa6, 0xfa, 0x64, 0xb2, 0xff, 0xa0, 0x24, 0xbb, 0xef, 0x9d, 0xde, 0x13, ++ 0xf8, 0xf3, 0xd1, 0x46, 0x3f, 0xe2, 0x8e, 0x18, 0x3f, 0xe0, 0xf6, 0x99, ++ 0xc6, 0xf7, 0xb7, 0x8a, 0xf1, 0x6e, 0x63, 0x4b, 0xdd, 0x23, 0x00, 0x5e, ++ 0xb7, 0xf5, 0x54, 0xdc, 0x21, 0x00, 0xd1, 0x1d, 0xc5, 0x35, 0x2a, 0xae, ++ 0xe7, 0x8e, 0xbb, 0x24, 0x56, 0xaf, 0x8b, 0x57, 0xde, 0x1a, 0x33, 0x9e, ++ 0x4b, 0x61, 0x22, 0x4e, 0xf2, 0x8f, 0xc1, 0xef, 0x9e, 0x0e, 0xf8, 0x2d, ++ 0x25, 0x78, 0xb0, 0x62, 0xd9, 0xbb, 0x99, 0x5d, 0x03, 0xfc, 0x18, 0x87, ++ 0x77, 0xeb, 0x8c, 0x61, 0x21, 0x8c, 0xc3, 0x30, 0xc5, 0xcb, 0xe1, 0x77, ++ 0x5b, 0xa5, 0x97, 0xe2, 0xa0, 0xc2, 0xcf, 0x54, 0x45, 0x7f, 0xd5, 0xb1, ++ 0xa6, 0x15, 0xf9, 0x56, 0x65, 0x46, 0xff, 0x52, 0xf3, 0x13, 0x13, 0xc1, ++ 0x99, 0x09, 0xbf, 0x93, 0xc6, 0xc9, 0xed, 0x84, 0xbb, 0xea, 0x93, 0xc9, ++ 0xef, 0xd4, 0x8d, 0x47, 0xf0, 0xd0, 0xf0, 0xf1, 0xf7, 0xe2, 0x41, 0xc3, ++ 0xdf, 0x7f, 0x17, 0x1f, 0x85, 0x88, 0x8f, 0x38, 0xfb, 0x67, 0x0b, 0xad, ++ 0xd6, 0x5b, 0x71, 0xff, 0xc2, 0x3a, 0x40, 0x22, 0xbf, 0x7d, 0xea, 0x5a, ++ 0x99, 0xf2, 0x60, 0xac, 0xf9, 0x12, 0xc1, 0xd1, 0x3f, 0x5a, 0xa5, 0xfd, ++ 0x9d, 0x3f, 0x9b, 0xfc, 0x85, 0x68, 0x38, 0x97, 0x0f, 0x1f, 0x55, 0xf5, ++ 0x10, 0x1f, 0xd6, 0x8b, 0xf0, 0x59, 0x28, 0xe0, 0x38, 0x9f, 0xd5, 0x90, ++ 0xdd, 0xc9, 0x2e, 0x7f, 0xf3, 0x4d, 0x11, 0xee, 0x1b, 0x11, 0x84, 0xe0, ++ 0xbd, 0x8f, 0xb1, 0xc9, 0xe0, 0x87, 0xcc, 0x2f, 0x92, 0xc2, 0x76, 0x58, ++ 0xff, 0x02, 0x85, 0x05, 0x93, 0x0b, 0x30, 0xae, 0x29, 0xb1, 0xe3, 0xfa, ++ 0xb8, 0x66, 0xc8, 0x58, 0xc7, 0xdf, 0xb7, 0x32, 0x3a, 0xc7, 0xb9, 0x5a, ++ 0xfb, 0x44, 0xf2, 0xe1, 0x9f, 0x5d, 0x7e, 0x0c, 0xf2, 0xe8, 0x78, 0x5f, ++ 0xf0, 0x57, 0xb0, 0x54, 0xe8, 0xf3, 0x8a, 0xde, 0x4f, 0x9c, 0xd3, 0xcc, ++ 0xe1, 0x58, 0xbd, 0x44, 0x0a, 0xe5, 0x12, 0x1d, 0x85, 0x55, 0xbf, 0x6e, ++ 0x5f, 0xe7, 0x7d, 0x41, 0xd7, 0x1f, 0x7f, 0x7f, 0x38, 0xc9, 0xb9, 0xe2, ++ 0x9f, 0x0e, 0x49, 0x26, 0xff, 0xd5, 0x37, 0x88, 0xec, 0xfd, 0x6a, 0x61, ++ 0xef, 0x5f, 0x08, 0x7a, 0x92, 0x31, 0x5e, 0x73, 0xa1, 0x39, 0x2f, 0x19, ++ 0xe3, 0x31, 0x17, 0x0e, 0x96, 0xba, 0xf4, 0x72, 0x51, 0x2b, 0x8f, 0x08, ++ 0x3f, 0xf2, 0x0f, 0xcb, 0xac, 0x54, 0xb6, 0x97, 0x49, 0xf5, 0x32, 0xfa, ++ 0x5b, 0x2c, 0x32, 0x85, 0xf4, 0x70, 0x99, 0x8d, 0xa1, 0xdc, 0x89, 0xed, ++ 0xf7, 0x92, 0xa2, 0xc5, 0x5d, 0x6a, 0xcc, 0x14, 0x97, 0x87, 0x9f, 0x5c, ++ 0x88, 0x78, 0xe4, 0xbf, 0x05, 0xd0, 0x35, 0x39, 0x55, 0x87, 0xb7, 0xb5, ++ 0x93, 0x4f, 0x29, 0x43, 0xbb, 0xe2, 0x01, 0x7f, 0xc7, 0x75, 0xfb, 0x24, ++ 0xff, 0x5d, 0xf8, 0xa2, 0xdf, 0x8a, 0x70, 0x3d, 0x62, 0x6b, 0x9b, 0xe0, ++ 0x8f, 0xb3, 0xde, 0x37, 0x04, 0xfc, 0xca, 0xf7, 0x7d, 0x65, 0xc6, 0x38, ++ 0xc1, 0xb4, 0xe6, 0x1c, 0x15, 0xe1, 0x32, 0xad, 0x4c, 0x36, 0xe4, 0xdd, ++ 0xec, 0x57, 0x84, 0x3f, 0x35, 0x9c, 0x0d, 0xc7, 0x79, 0x95, 0xef, 0xbb, ++ 0xc9, 0x35, 0x06, 0xf1, 0x72, 0x50, 0xf6, 0xda, 0x00, 0xbe, 0xd5, 0xcd, ++ 0xe7, 0xcd, 0x81, 0x38, 0xfb, 0x6d, 0xb1, 0xf0, 0xc4, 0xf1, 0x31, 0x2e, ++ 0x7c, 0x42, 0xf5, 0xce, 0x47, 0x78, 0x9e, 0xf8, 0xb1, 0x8d, 0x05, 0x81, ++ 0x1f, 0x0e, 0x8b, 0xfd, 0x1f, 0x78, 0xe5, 0x43, 0xf9, 0x05, 0x43, 0xf9, ++ 0x30, 0x3e, 0xf6, 0xb6, 0xc2, 0xf7, 0x15, 0x06, 0xaa, 0x3c, 0x2e, 0x3e, ++ 0xbd, 0xbc, 0x58, 0x4d, 0x87, 0xef, 0xe6, 0x37, 0xba, 0x87, 0xa1, 0x8a, ++ 0xe9, 0x21, 0xda, 0x0f, 0x54, 0x3d, 0xf4, 0x3e, 0x5b, 0xf4, 0xd3, 0xda, ++ 0xf5, 0x58, 0xc2, 0xdb, 0x1d, 0x33, 0xbb, 0xab, 0xe2, 0xad, 0x7f, 0xb2, ++ 0x99, 0xaf, 0x7f, 0x01, 0xf3, 0x7e, 0x77, 0xb4, 0xf4, 0xaf, 0x87, 0xb7, ++ 0xe2, 0x9f, 0x3a, 0xc3, 0x25, 0xa8, 0xdf, 0xcb, 0x24, 0x92, 0x23, 0x5d, ++ 0xe9, 0x9a, 0x11, 0x7f, 0x5c, 0x98, 0x28, 0x85, 0x50, 0xff, 0xa2, 0x1f, ++ 0x4b, 0xf5, 0x72, 0x89, 0xf4, 0xff, 0x61, 0x2d, 0xff, 0x60, 0x1a, 0xd7, ++ 0x97, 0x1a, 0xdd, 0xc7, 0xc2, 0x59, 0x52, 0x39, 0x9c, 0xb5, 0xef, 0xe7, ++ 0xa8, 0x9c, 0x9e, 0xcd, 0x2a, 0x87, 0x8f, 0x06, 0x67, 0x0d, 0xbe, 0xb1, ++ 0xf3, 0xd5, 0xda, 0x83, 0xbc, 0xba, 0x51, 0x1f, 0x5f, 0x99, 0xda, 0x34, ++ 0xec, 0xb7, 0x68, 0x9f, 0x54, 0x35, 0x4b, 0x6e, 0x0c, 0xfd, 0x55, 0x29, ++ 0x6d, 0x66, 0xe4, 0xc3, 0xea, 0xa6, 0x47, 0x55, 0xdc, 0x2f, 0xb8, 0xc3, ++ 0xc3, 0xc7, 0x65, 0x8a, 0x7f, 0xa8, 0x7e, 0xbf, 0x76, 0xa0, 0xaa, 0xd0, ++ 0x7c, 0xf6, 0x17, 0x8c, 0x25, 0xfb, 0xf1, 0xe2, 0x5a, 0x6e, 0x1f, 0xfb, ++ 0xee, 0x39, 0xef, 0x42, 0x3b, 0xe8, 0xb0, 0xc9, 0xfb, 0xfb, 0xb1, 0xc8, ++ 0x8f, 0x6f, 0xca, 0x94, 0x4f, 0x90, 0x08, 0x8e, 0x1f, 0x2c, 0xdb, 0x32, ++ 0xa3, 0x4c, 0xd1, 0x8f, 0x9b, 0x43, 0xf3, 0x9c, 0xbe, 0xa4, 0x58, 0xc5, ++ 0x70, 0xd0, 0x77, 0x96, 0xec, 0x55, 0xbb, 0xeb, 0xe8, 0x69, 0xa0, 0x9a, ++ 0x4a, 0xef, 0xb5, 0xe7, 0x3d, 0x96, 0x78, 0x0a, 0xf0, 0x39, 0x7c, 0x8f, ++ 0xe6, 0x11, 0xfc, 0x89, 0x85, 0x61, 0x1e, 0x47, 0x7e, 0x43, 0x6b, 0x49, ++ 0x12, 0xbc, 0xff, 0x4e, 0x4d, 0x0a, 0xa7, 0xc3, 0x8a, 0x86, 0xbd, 0x66, ++ 0xaa, 0xe7, 0x50, 0x7b, 0xed, 0x7b, 0xda, 0x77, 0x62, 0xf9, 0x69, 0x46, ++ 0x79, 0x92, 0xa1, 0x3e, 0xaf, 0xb4, 0xad, 0x27, 0xc2, 0xa5, 0xdc, 0x12, ++ 0x7e, 0xc0, 0x1b, 0x87, 0x4e, 0x5b, 0x54, 0x6d, 0x9f, 0xe4, 0xef, 0xd4, ++ 0x13, 0x3e, 0xa0, 0xdb, 0xa1, 0xff, 0x3f, 0xe8, 0x89, 0xf3, 0x13, 0x7c, ++ 0x71, 0xe0, 0xf6, 0x98, 0xda, 0x45, 0x3f, 0x74, 0x8f, 0xa7, 0x1f, 0x96, ++ 0x2e, 0xf7, 0x74, 0x47, 0xf8, 0x2f, 0xdd, 0x95, 0xd7, 0x1d, 0x99, 0x63, ++ 0xe9, 0x6b, 0xe3, 0x33, 0xe2, 0xe9, 0x87, 0x77, 0x96, 0xf1, 0xfd, 0xc0, ++ 0xf7, 0x40, 0x9e, 0x61, 0xd9, 0x3e, 0x03, 0xf4, 0xc3, 0xf5, 0x3a, 0xfd, ++ 0x30, 0xc3, 0x46, 0xf4, 0x11, 0xdb, 0xef, 0x07, 0xea, 0x35, 0xea, 0x07, ++ 0x0d, 0x5f, 0xff, 0xc3, 0x72, 0xe6, 0x1d, 0xd4, 0x0f, 0x71, 0xf8, 0xba, ++ 0x5e, 0x35, 0xea, 0x87, 0xdb, 0x9a, 0xe7, 0x92, 0x7e, 0xb8, 0x6d, 0x86, ++ 0xcc, 0x3c, 0xba, 0x78, 0xdc, 0x0f, 0x55, 0xb1, 0xcf, 0x95, 0x50, 0x3f, ++ 0x14, 0x67, 0xdc, 0x41, 0x75, 0xd5, 0x9b, 0x14, 0x87, 0x6e, 0xde, 0x11, ++ 0x7e, 0x09, 0xc2, 0x15, 0x4b, 0xfc, 0x0e, 0xea, 0x89, 0x3d, 0x42, 0xee, ++ 0xc7, 0xea, 0x8b, 0x44, 0xf2, 0x7c, 0x9a, 0x59, 0x12, 0xfb, 0xd5, 0x57, ++ 0x91, 0xe7, 0xff, 0x97, 0xe0, 0xac, 0xc9, 0xf3, 0xa5, 0xe0, 0xbf, 0xa0, ++ 0x1d, 0xd8, 0x95, 0x0e, 0x19, 0xc9, 0xeb, 0xa5, 0x77, 0x80, 0x3c, 0x97, ++ 0x90, 0x1e, 0xb9, 0x3c, 0x5f, 0x7a, 0x97, 0x88, 0x4b, 0xc6, 0xc8, 0x57, ++ 0x3f, 0xca, 0xd7, 0x11, 0x7a, 0xf9, 0xca, 0xfb, 0x57, 0x05, 0xb8, 0x3e, ++ 0xa8, 0x6e, 0xca, 0x79, 0x7c, 0x16, 0xbc, 0xbf, 0xb3, 0x5e, 0xf5, 0x5a, ++ 0xa1, 0xfd, 0x9d, 0x9d, 0xf2, 0xb6, 0x50, 0x2f, 0x6f, 0xf7, 0x08, 0x79, ++ 0x0b, 0x70, 0xee, 0xed, 0x8e, 0x83, 0xdf, 0x99, 0xb3, 0x92, 0x98, 0xc7, ++ 0x28, 0xaf, 0xfa, 0xa2, 0x9c, 0x3a, 0x31, 0xec, 0x77, 0xf9, 0x3b, 0x91, ++ 0xee, 0x0f, 0xcb, 0xb4, 0x8f, 0xf8, 0x67, 0xa1, 0xc7, 0x0f, 0x0d, 0xfb, ++ 0xdd, 0x08, 0x8c, 0x9f, 0x77, 0x33, 0x2b, 0x44, 0x3f, 0x7f, 0x16, 0xf2, ++ 0xeb, 0xdc, 0xb2, 0xd0, 0x8c, 0x32, 0xe0, 0xe3, 0xd2, 0x7b, 0xb8, 0x3d, ++ 0x5c, 0xb9, 0x4d, 0x26, 0x38, 0x54, 0x35, 0x72, 0x3b, 0xaf, 0xaa, 0xaf, ++ 0x3d, 0xe4, 0x81, 0xfa, 0x84, 0x82, 0xaf, 0x68, 0x3f, 0x70, 0xf1, 0x2e, ++ 0xbe, 0x1f, 0x08, 0x80, 0x2a, 0x2f, 0xd6, 0xe1, 0x71, 0xf1, 0xe1, 0xb6, ++ 0xba, 0x6c, 0x7c, 0xbf, 0x41, 0xa2, 0xfd, 0xcc, 0xf9, 0xde, 0xc5, 0x14, ++ 0xc7, 0x67, 0xeb, 0x78, 0x9c, 0xd8, 0x0a, 0xff, 0xf0, 0xbc, 0x0e, 0x1f, ++ 0xc5, 0x91, 0x2b, 0x05, 0xbc, 0x16, 0x36, 0x6f, 0xa0, 0x78, 0xf3, 0xc2, ++ 0x90, 0x31, 0x0e, 0x5d, 0xd9, 0xf7, 0xe6, 0x53, 0xe8, 0x0f, 0x68, 0xf2, ++ 0x77, 0xf1, 0x96, 0x98, 0xf7, 0xde, 0x87, 0x69, 0xbf, 0xa2, 0x12, 0xe3, ++ 0xcd, 0x3a, 0x3f, 0x44, 0x16, 0xf6, 0xc3, 0xbd, 0x72, 0x38, 0x7f, 0x27, ++ 0xe6, 0x76, 0xfe, 0x9e, 0xfb, 0x55, 0xb1, 0xf8, 0xd7, 0xda, 0x75, 0xac, ++ 0xbf, 0xe2, 0xbf, 0xb9, 0xfe, 0x23, 0xb0, 0xfe, 0x11, 0xff, 0xfc, 0xf5, ++ 0x5f, 0xeb, 0xba, 0x55, 0xb3, 0xe0, 0xf7, 0x02, 0x36, 0x02, 0xf9, 0xe3, ++ 0xcf, 0x26, 0x1f, 0xf1, 0x7b, 0xf0, 0x75, 0x58, 0x3f, 0x7c, 0xe7, 0x9e, ++ 0x47, 0xfb, 0x75, 0xd7, 0xe7, 0x19, 0xa5, 0x09, 0xbe, 0x3c, 0x6c, 0x0a, ++ 0xd4, 0x65, 0x61, 0xbb, 0x2a, 0x89, 0xda, 0x2d, 0x58, 0xbf, 0xfd, 0x40, ++ 0x06, 0xd4, 0x67, 0x35, 0xb0, 0x61, 0x18, 0xa6, 0x5f, 0xb0, 0xce, 0xa8, ++ 0x17, 0x3b, 0xf4, 0x70, 0xa3, 0x87, 0xf4, 0xec, 0xac, 0x9a, 0xed, 0xd2, ++ 0xdd, 0xf9, 0x08, 0x6f, 0x56, 0x83, 0x74, 0x36, 0xaf, 0xc0, 0x12, 0xc0, ++ 0xfd, 0xd4, 0x23, 0xb6, 0x08, 0xc9, 0x2f, 0x8d, 0xee, 0xc6, 0x99, 0x39, ++ 0x3d, 0x8f, 0x15, 0xdf, 0x3d, 0xd1, 0x23, 0x52, 0x46, 0x7e, 0x44, 0x93, ++ 0xe4, 0x26, 0xbe, 0x08, 0xdb, 0xb8, 0x5f, 0x01, 0xf0, 0xb7, 0x41, 0x7d, ++ 0xff, 0x98, 0x2f, 0x27, 0x08, 0x78, 0x53, 0x3c, 0xa6, 0xba, 0x89, 0xe3, ++ 0xa7, 0x1a, 0xf0, 0x81, 0x7c, 0x35, 0xa1, 0x59, 0xd4, 0xb7, 0x70, 0x3b, ++ 0xec, 0x3b, 0xa0, 0x6f, 0x68, 0x3f, 0xac, 0x79, 0xaf, 0x8a, 0xfd, 0x2a, ++ 0xa0, 0x7d, 0x1a, 0xc9, 0x9b, 0x41, 0x86, 0x7d, 0x2e, 0xdc, 0x9f, 0x2b, ++ 0xce, 0xd0, 0xe1, 0x6d, 0xd7, 0x31, 0x4e, 0xb7, 0x9b, 0x25, 0x2f, 0x8b, ++ 0x83, 0xb7, 0x01, 0xf0, 0x4f, 0x5c, 0xbc, 0xfd, 0x93, 0xe8, 0x55, 0x83, ++ 0xc7, 0x38, 0xb3, 0xb0, 0xe7, 0x05, 0xfe, 0x8e, 0xd8, 0x5a, 0xcb, 0x87, ++ 0xd3, 0x3e, 0x94, 0xe4, 0xdd, 0x88, 0x8d, 0x9b, 0x53, 0x68, 0x1f, 0xe5, ++ 0x93, 0xfa, 0x3c, 0xc2, 0xe3, 0x24, 0x41, 0xbf, 0xb1, 0x74, 0x8d, 0xf6, ++ 0xbd, 0x47, 0x17, 0x4f, 0xba, 0x05, 0x27, 0x0e, 0xf2, 0x95, 0x4d, 0xb4, ++ 0x51, 0x9e, 0x1b, 0x7d, 0x37, 0x97, 0xdb, 0x3f, 0x7a, 0x79, 0x12, 0xeb, ++ 0x37, 0x57, 0xb3, 0x56, 0xb2, 0x63, 0x26, 0x4b, 0x81, 0x8f, 0x14, 0x5d, ++ 0x5e, 0xdb, 0x6d, 0x22, 0xff, 0x44, 0xdb, 0xa7, 0xd5, 0xb5, 0x7b, 0x5c, ++ 0xbd, 0x42, 0x3b, 0x96, 0xe9, 0x36, 0xa1, 0x9c, 0xbc, 0x5f, 0xcb, 0xb7, ++ 0xc4, 0xfc, 0xe1, 0x0c, 0xca, 0x5b, 0xa2, 0xdf, 0xfe, 0x5e, 0x85, 0xef, ++ 0xcd, 0x82, 0xf5, 0x5e, 0x5c, 0x23, 0x7b, 0x71, 0xff, 0xe7, 0x76, 0x93, ++ 0xe7, 0xdd, 0x22, 0xe4, 0xdf, 0x47, 0x54, 0x86, 0x74, 0x79, 0xf1, 0x90, ++ 0xea, 0xe3, 0x76, 0x67, 0x12, 0xc9, 0xdd, 0xb9, 0x87, 0x4f, 0xa8, 0x18, ++ 0x0a, 0x99, 0x0b, 0x30, 0x41, 0x7c, 0xcf, 0xfd, 0x01, 0x97, 0xaf, 0x27, ++ 0x70, 0x30, 0x78, 0xf6, 0x47, 0xd0, 0x5b, 0x3e, 0xdc, 0xab, 0x67, 0x0d, ++ 0x23, 0x31, 0x7f, 0x78, 0x86, 0x77, 0xef, 0x78, 0x0f, 0xe0, 0xe5, 0xd6, ++ 0x11, 0x47, 0x56, 0xe3, 0x3e, 0xdc, 0xf4, 0x52, 0xf7, 0xbb, 0xef, 0x22, ++ 0x7c, 0x1f, 0x96, 0x19, 0xc2, 0xf7, 0xf8, 0x9a, 0x52, 0xf2, 0x4f, 0xee, ++ 0xbf, 0x4f, 0x22, 0xba, 0x3e, 0x0a, 0x70, 0xc4, 0xfe, 0xb7, 0xce, 0xc8, ++ 0x79, 0xf7, 0x5d, 0xf8, 0xee, 0x5d, 0x6b, 0xd2, 0x69, 0x5f, 0x6d, 0x96, ++ 0xef, 0xc0, 0x78, 0xa4, 0xb3, 0x79, 0x53, 0x9d, 0x0e, 0xdc, 0x5f, 0x9b, ++ 0x34, 0x40, 0x66, 0x01, 0x1d, 0x1c, 0xef, 0x62, 0xad, 0xab, 0x51, 0x5e, ++ 0xcf, 0xaa, 0xb9, 0xef, 0x56, 0x9c, 0x6f, 0x05, 0xe8, 0x01, 0x8c, 0xb3, ++ 0x56, 0x34, 0x1f, 0x19, 0xdf, 0x1d, 0xeb, 0xeb, 0x25, 0xaf, 0x07, 0xc6, ++ 0xaf, 0x0e, 0x06, 0xcc, 0xdd, 0x01, 0x85, 0xad, 0xeb, 0xce, 0x9b, 0x31, ++ 0xde, 0x31, 0x1f, 0xda, 0x21, 0x7a, 0xaa, 0xd7, 0xf3, 0x76, 0xd5, 0x9b, ++ 0x24, 0xaf, 0x0d, 0xe9, 0xb1, 0xf9, 0x51, 0x92, 0x3b, 0xf3, 0x37, 0x49, ++ 0xcc, 0x8d, 0xed, 0xc1, 0xde, 0xb3, 0xf2, 0x71, 0x43, 0x56, 0x18, 0xb7, ++ 0x75, 0x3d, 0xf4, 0x87, 0xfa, 0x02, 0xec, 0x8f, 0xe3, 0x6e, 0x4a, 0xb9, ++ 0x0d, 0xf7, 0xd1, 0xaa, 0x0f, 0xc9, 0xbc, 0xff, 0xe8, 0xe5, 0xaf, 0xa2, ++ 0x5c, 0x9a, 0x0f, 0xfd, 0xe0, 0x35, 0x6b, 0xdd, 0x74, 0x1f, 0x8d, 0xb7, ++ 0x70, 0xbd, 0xc4, 0x32, 0x61, 0xbc, 0x8a, 0xd1, 0x39, 0x3f, 0x19, 0x8d, ++ 0xe3, 0x1d, 0x52, 0xbd, 0xf8, 0xfe, 0xbd, 0xbd, 0xbf, 0x32, 0xe3, 0xbc, ++ 0x67, 0xc3, 0xf7, 0xb2, 0x60, 0xfc, 0x79, 0x72, 0xdb, 0x78, 0x6c, 0xcf, ++ 0xbe, 0x27, 0xb9, 0x37, 0x53, 0xbc, 0x89, 0xe7, 0xc9, 0xb6, 0x0b, 0x3e, ++ 0x60, 0x6f, 0x67, 0x71, 0xfe, 0x92, 0x44, 0x5d, 0xd8, 0x81, 0x9a, 0x3e, ++ 0xfc, 0x83, 0x39, 0x97, 0xe8, 0x69, 0x7e, 0xed, 0xf2, 0x3a, 0x5c, 0x57, ++ 0x5b, 0x30, 0x3d, 0x07, 0x5d, 0xa0, 0xea, 0xa6, 0xf3, 0x66, 0xb4, 0xeb, ++ 0x3e, 0x01, 0x38, 0x07, 0xc0, 0x6e, 0x3b, 0x21, 0xf2, 0xd8, 0xf6, 0x07, ++ 0x4f, 0x98, 0xdb, 0x74, 0x72, 0x2a, 0x62, 0xce, 0xa3, 0xfe, 0xf7, 0x34, ++ 0x15, 0x13, 0x7f, 0xdf, 0xcb, 0xfc, 0xb4, 0xdf, 0x1d, 0x58, 0xce, 0xf5, ++ 0xf0, 0xb1, 0xd5, 0xb6, 0x90, 0x84, 0xf6, 0x87, 0xea, 0x26, 0x3d, 0xb9, ++ 0x7f, 0xf5, 0x75, 0xbf, 0xc4, 0xf5, 0x9f, 0x7b, 0x56, 0xa5, 0xfd, 0xd1, ++ 0x73, 0xbd, 0xda, 0x28, 0x1e, 0x7b, 0x72, 0xbd, 0xca, 0x82, 0x30, 0xc7, ++ 0x95, 0xeb, 0x65, 0x92, 0x1b, 0x27, 0xb7, 0xf1, 0x38, 0x90, 0xfc, 0x84, ++ 0x4a, 0xf5, 0x05, 0x0f, 0x9a, 0xa9, 0xbe, 0x7f, 0xfd, 0xf4, 0x09, 0x28, ++ 0x0f, 0x4f, 0x02, 0xfc, 0x91, 0x0e, 0x4b, 0x9f, 0x18, 0x6f, 0xc6, 0xfa, ++ 0x02, 0x90, 0xeb, 0x96, 0x38, 0xf2, 0x63, 0xbe, 0x67, 0x11, 0x97, 0x17, ++ 0x31, 0xf2, 0x61, 0xc1, 0x3a, 0x23, 0xff, 0x77, 0x91, 0x17, 0x0f, 0x4c, ++ 0xe0, 0xf2, 0x3d, 0x46, 0x1e, 0x54, 0xf6, 0xac, 0xa3, 0x38, 0x5f, 0xac, ++ 0x9c, 0xa8, 0x66, 0x0e, 0x4d, 0x3e, 0x14, 0x60, 0xbd, 0x35, 0x9c, 0x45, ++ 0xf4, 0x5b, 0x75, 0x48, 0x65, 0x68, 0xcf, 0x55, 0x29, 0xee, 0xd9, 0xeb, ++ 0x90, 0x6e, 0x66, 0xd9, 0x70, 0xa7, 0x18, 0xf8, 0x22, 0x7c, 0x00, 0xe5, ++ 0xda, 0xc5, 0x90, 0xe4, 0x09, 0xc2, 0xfb, 0xef, 0xcc, 0x79, 0x69, 0x24, ++ 0xc2, 0xef, 0x2f, 0x08, 0x6f, 0xe4, 0x8b, 0xb5, 0x69, 0xb4, 0x9f, 0x3a, ++ 0x3f, 0x34, 0x97, 0xe0, 0xaa, 0xe5, 0x13, 0x2e, 0x58, 0x67, 0xa4, 0x67, ++ 0x2d, 0x7f, 0xe9, 0x8e, 0x80, 0xcc, 0x7c, 0x7a, 0x3d, 0x50, 0x91, 0xc4, ++ 0x7c, 0xba, 0x76, 0xef, 0xfd, 0x00, 0xe8, 0x12, 0xbe, 0x37, 0xa7, 0x49, ++ 0x0a, 0xd9, 0x24, 0xac, 0x1f, 0x7b, 0xf5, 0xc1, 0x11, 0x54, 0x77, 0x23, ++ 0x1d, 0x56, 0xd5, 0x0a, 0x7d, 0xba, 0xd6, 0x49, 0x74, 0xfb, 0xde, 0xbf, ++ 0x9d, 0x5f, 0x8d, 0x74, 0x39, 0xfb, 0xfb, 0x12, 0xcd, 0x9f, 0x05, 0x03, ++ 0x75, 0xa8, 0x57, 0xaa, 0xd6, 0x49, 0x1e, 0x8c, 0x63, 0x2e, 0xf8, 0x3e, ++ 0xef, 0xbf, 0x00, 0xfa, 0x23, 0xbd, 0xbc, 0xf7, 0x2b, 0x4e, 0x3f, 0x40, ++ 0xc7, 0x1e, 0xa4, 0xf3, 0xaa, 0xf5, 0x8f, 0xbe, 0x4a, 0xed, 0x37, 0x49, ++ 0x1e, 0x1c, 0xff, 0xbd, 0x0d, 0x73, 0x49, 0xff, 0x56, 0x04, 0x65, 0x46, ++ 0xef, 0x37, 0x1d, 0x23, 0xfb, 0x18, 0xf4, 0x00, 0xe5, 0x01, 0xed, 0x0f, ++ 0xca, 0x19, 0x48, 0xe7, 0x55, 0xab, 0x2c, 0x6e, 0xc4, 0xa3, 0x46, 0x2f, ++ 0x1a, 0xfd, 0x1d, 0x53, 0xc5, 0x39, 0x01, 0xab, 0x77, 0xe8, 0x74, 0xe8, ++ 0xb7, 0xc1, 0xec, 0xa1, 0x75, 0xc7, 0xd2, 0x9d, 0x3c, 0x33, 0x87, 0xe8, ++ 0xab, 0x7a, 0x9b, 0x4a, 0xf4, 0x51, 0x1d, 0xe4, 0xf4, 0x74, 0xec, 0x59, ++ 0x99, 0xe8, 0x70, 0xff, 0xea, 0xdb, 0x89, 0x7e, 0xce, 0x6d, 0x96, 0x12, ++ 0xd0, 0x5f, 0xa9, 0x39, 0x0b, 0xe9, 0x2f, 0xc4, 0xdf, 0x77, 0xd0, 0xdf, ++ 0x33, 0x92, 0xa0, 0x3f, 0x4e, 0xd7, 0x27, 0x1f, 0xe0, 0xf4, 0x58, 0x8a, ++ 0xef, 0x91, 0xfe, 0x9e, 0x17, 0xf6, 0x29, 0x63, 0x0e, 0xbd, 0xdd, 0xa1, ++ 0xd1, 0x9f, 0x46, 0x4f, 0x57, 0xa3, 0xbb, 0x2e, 0x7a, 0x29, 0x01, 0xbd, ++ 0x81, 0x6d, 0x7c, 0x1b, 0xce, 0xeb, 0xfe, 0xd5, 0x36, 0x9a, 0x77, 0x69, ++ 0xdd, 0x4b, 0xb7, 0xd5, 0x12, 0xdf, 0xa8, 0xb4, 0x3f, 0x5f, 0x5a, 0xf7, ++ 0x6f, 0x19, 0xc8, 0xa7, 0xf3, 0x15, 0x9e, 0x87, 0xa1, 0xc1, 0xb1, 0x52, ++ 0xe1, 0x79, 0x3a, 0x5d, 0xe6, 0xf1, 0xf3, 0xe5, 0xe6, 0xac, 0x6b, 0x99, ++ 0x4f, 0xcc, 0x3c, 0xf6, 0x76, 0xea, 0xc5, 0x02, 0xd4, 0x8b, 0x98, 0x57, ++ 0x12, 0x86, 0xef, 0xfc, 0x6e, 0xdb, 0xd3, 0x94, 0xbf, 0x76, 0x76, 0xeb, ++ 0x31, 0xca, 0x4b, 0x5c, 0xfc, 0x0a, 0xe0, 0x1d, 0xda, 0x9f, 0xdb, 0xe6, ++ 0x64, 0x61, 0xb2, 0xa7, 0x43, 0x24, 0x5f, 0x16, 0x35, 0xca, 0x94, 0x17, ++ 0xca, 0x94, 0x70, 0xe1, 0x74, 0xdd, 0xf9, 0x11, 0x2d, 0xdf, 0x62, 0xf1, ++ 0x73, 0x4e, 0x82, 0xef, 0xa2, 0x1d, 0x96, 0x50, 0x39, 0xf4, 0x5f, 0xf4, ++ 0xc2, 0x89, 0xa1, 0xb4, 0x1f, 0xbe, 0x22, 0xf2, 0x2a, 0xf2, 0x4f, 0x70, ++ 0xab, 0xc4, 0xe3, 0xf2, 0xc1, 0xb6, 0xa1, 0xd3, 0x31, 0xaf, 0x52, 0xe1, ++ 0x79, 0x1f, 0xb1, 0x7a, 0x77, 0x8c, 0x85, 0xc7, 0x6b, 0xce, 0xbc, 0x94, ++ 0x34, 0x13, 0xed, 0x1f, 0x69, 0xcb, 0x5e, 0xda, 0x4f, 0x5a, 0xd4, 0x70, ++ 0xbb, 0x6a, 0xd1, 0xc5, 0x27, 0xbd, 0x16, 0x95, 0xbe, 0x0b, 0xed, 0x68, ++ 0x9f, 0x26, 0x08, 0x78, 0xc7, 0x7d, 0x44, 0x9c, 0xdf, 0x2d, 0x43, 0xf4, ++ 0xf3, 0x5b, 0xce, 0xc7, 0x7b, 0x86, 0xf3, 0xcd, 0xa2, 0x26, 0x95, 0xec, ++ 0xa2, 0x45, 0x5b, 0x36, 0x50, 0x5c, 0xaf, 0x7a, 0xcb, 0x79, 0xca, 0x7b, ++ 0x2d, 0x7d, 0xee, 0x59, 0x17, 0xc2, 0xa1, 0xba, 0x49, 0x36, 0xe6, 0x43, ++ 0x6d, 0x91, 0xc3, 0x16, 0xca, 0xd7, 0x92, 0x8f, 0x59, 0xb8, 0x7c, 0x32, ++ 0xe4, 0x25, 0x55, 0x35, 0xf2, 0x73, 0x19, 0x55, 0x0d, 0x22, 0xef, 0x27, ++ 0x26, 0x2f, 0x66, 0xf1, 0x73, 0xbb, 0x5e, 0x08, 0x02, 0x68, 0x16, 0xef, ++ 0xfc, 0x2f, 0x17, 0xf2, 0xd1, 0xe9, 0xd6, 0xcd, 0x2e, 0x84, 0x27, 0x8c, ++ 0x47, 0xf9, 0x44, 0x53, 0x47, 0x27, 0xc8, 0x37, 0xba, 0x5a, 0x9e, 0x51, ++ 0xc3, 0xc3, 0x71, 0xf3, 0x8c, 0x4e, 0xe3, 0x7f, 0x00, 0x81, 0xcc, 0xb6, ++ 0x18, 0xf3, 0x33, 0xd9, 0x16, 0x2e, 0xa7, 0x00, 0xeb, 0x85, 0xfe, 0x38, ++ 0xf1, 0x4c, 0xcd, 0x5e, 0x59, 0xfc, 0xec, 0xe7, 0x4f, 0x62, 0xde, 0xeb, ++ 0x99, 0x1d, 0x9f, 0x3d, 0x89, 0xf3, 0x5e, 0xf2, 0xbf, 0x2e, 0x3e, 0x89, ++ 0x79, 0x1b, 0x6c, 0xb7, 0xcd, 0x8d, 0xf6, 0x43, 0xf5, 0xd6, 0x77, 0x28, ++ 0x7f, 0x50, 0xeb, 0x57, 0x6b, 0x11, 0xfe, 0xcf, 0x33, 0xff, 0x45, 0x79, ++ 0x97, 0xe7, 0xde, 0xb7, 0x90, 0xfd, 0x77, 0x6e, 0xd7, 0xc9, 0xde, 0x68, ++ 0x1f, 0x9c, 0xdb, 0xfe, 0x55, 0x06, 0xe6, 0x53, 0x3e, 0xb0, 0x6b, 0x3c, ++ 0xc5, 0x1f, 0x1e, 0x78, 0xbe, 0xb4, 0x3b, 0x8b, 0xe3, 0xdf, 0x6a, 0x25, ++ 0xd2, 0x65, 0xe8, 0x1a, 0xf2, 0x3e, 0x63, 0xf1, 0xb0, 0xbf, 0x51, 0x0e, ++ 0x3b, 0x60, 0x9e, 0x67, 0x8f, 0x5a, 0x88, 0xbf, 0x3b, 0xf2, 0xc5, 0x1a, ++ 0x2a, 0x79, 0xfe, 0x9d, 0x47, 0xe4, 0x89, 0x6d, 0x8b, 0x9f, 0x57, 0xab, ++ 0xe5, 0x37, 0x55, 0x35, 0x4e, 0x9f, 0x3a, 0x0e, 0xe5, 0x5b, 0x23, 0xd7, ++ 0xe3, 0x1d, 0xf9, 0x4e, 0x57, 0xcb, 0x0f, 0x7b, 0x1b, 0xf0, 0x79, 0xfd, ++ 0x35, 0xe0, 0x6d, 0x9b, 0xc8, 0xff, 0x8b, 0xc1, 0xdb, 0x59, 0xfc, 0x0f, ++ 0xc0, 0xcf, 0x2f, 0x2c, 0xc6, 0xfc, 0xb0, 0xcf, 0x1b, 0xef, 0x7d, 0xea, ++ 0xd7, 0xf8, 0xae, 0x31, 0xfe, 0x79, 0x32, 0x8d, 0x8f, 0xaf, 0x06, 0x2f, ++ 0x2d, 0x6f, 0x77, 0x9e, 0xc5, 0x17, 0xb2, 0x20, 0xdf, 0xec, 0xf8, 0x0d, ++ 0xe5, 0xe1, 0x21, 0xbe, 0xca, 0x3d, 0xa8, 0xe7, 0x3f, 0xef, 0x8d, 0x71, ++ 0xcb, 0x4f, 0xd5, 0x08, 0xc5, 0x03, 0x23, 0xbb, 0x2c, 0x6e, 0xcc, 0xdb, ++ 0x5a, 0xb4, 0xeb, 0x3d, 0xe2, 0x8f, 0x73, 0xcf, 0x1f, 0xa1, 0xbc, 0x58, ++ 0x26, 0xf2, 0x67, 0xcf, 0xb1, 0x8e, 0x1f, 0xcf, 0x77, 0x14, 0x31, 0x89, ++ 0xea, 0x4d, 0x4e, 0x9e, 0x57, 0x26, 0xe0, 0x8e, 0x79, 0x67, 0x1e, 0x17, ++ 0x3d, 0x17, 0xf9, 0x65, 0x9c, 0x6e, 0xb5, 0xbc, 0xb3, 0x44, 0xf9, 0x66, ++ 0xef, 0x58, 0x72, 0xc5, 0xb9, 0x0b, 0x9e, 0x17, 0x57, 0xe9, 0x69, 0x35, ++ 0x23, 0xfc, 0xf5, 0x79, 0x68, 0xd2, 0x68, 0xc4, 0xd3, 0x31, 0x43, 0xfe, ++ 0x9e, 0xb6, 0xee, 0xd8, 0xf1, 0xdc, 0x08, 0x87, 0x51, 0xfa, 0xbc, 0xc9, ++ 0x44, 0xf9, 0x7c, 0xc2, 0x1e, 0xef, 0xc0, 0x13, 0x97, 0xc3, 0xe7, 0x36, ++ 0x88, 0x3c, 0xca, 0x8e, 0xfc, 0x48, 0xc6, 0x7a, 0x16, 0x60, 0xbe, 0x0f, ++ 0xd7, 0x77, 0xd5, 0x21, 0xe9, 0x3d, 0x16, 0x87, 0x1f, 0xb5, 0xbc, 0xc9, ++ 0xd6, 0x58, 0x7e, 0x0c, 0x5d, 0x5b, 0xbe, 0xe4, 0xd5, 0xe7, 0xfb, 0x8f, ++ 0xc1, 0x63, 0xbf, 0x85, 0xc7, 0x9f, 0x34, 0xb8, 0x9c, 0xb9, 0x1c, 0x5f, ++ 0x1e, 0x7f, 0x26, 0xf8, 0x1b, 0xfc, 0x92, 0xd3, 0x16, 0xdd, 0xb9, 0x94, ++ 0x39, 0xc2, 0x2f, 0xd1, 0xf2, 0xc8, 0xb4, 0xf9, 0xd6, 0x35, 0x70, 0xbd, ++ 0x7b, 0x66, 0x0b, 0xb7, 0x0b, 0x63, 0xf9, 0xb9, 0x4a, 0xc4, 0xdb, 0x63, ++ 0xbf, 0xf3, 0x95, 0xf8, 0x4e, 0x55, 0xd3, 0xde, 0xa1, 0x28, 0x77, 0xce, ++ 0xec, 0x7b, 0x49, 0xd0, 0x1b, 0xa7, 0xe7, 0xaa, 0x6d, 0xc7, 0xcc, 0x41, ++ 0x21, 0x9f, 0x43, 0x7a, 0xf9, 0x8c, 0xe3, 0xc5, 0x91, 0x27, 0xb2, 0x95, ++ 0x8f, 0x07, 0x7e, 0x6c, 0xdc, 0xf1, 0xaa, 0xb7, 0x9d, 0x8f, 0x3b, 0xde, ++ 0x69, 0xc5, 0x77, 0x3b, 0xce, 0xff, 0x74, 0x2b, 0xb7, 0x33, 0x4e, 0x37, ++ 0xc8, 0x13, 0x43, 0x71, 0xc6, 0x3f, 0x2b, 0xf4, 0x4f, 0xc7, 0xba, 0x9d, ++ 0x66, 0xf2, 0xab, 0x64, 0x97, 0x9d, 0xe4, 0xcf, 0x03, 0xce, 0xd1, 0x47, ++ 0x93, 0xbb, 0x61, 0x69, 0xa6, 0xfc, 0x85, 0x95, 0xcb, 0x45, 0xbe, 0xc3, ++ 0x0f, 0xbc, 0x99, 0x08, 0xe7, 0x95, 0xce, 0x9b, 0x19, 0xce, 0x67, 0x35, ++ 0xc2, 0x47, 0xe7, 0x67, 0xaa, 0xee, 0x00, 0x43, 0x3b, 0x47, 0xcd, 0xf4, ++ 0x8f, 0x40, 0xff, 0x49, 0x9b, 0xaf, 0xf6, 0xde, 0xdc, 0xcd, 0xc4, 0x42, ++ 0x7a, 0xfc, 0x2b, 0xc1, 0x9e, 0x18, 0x77, 0x9d, 0x92, 0xfb, 0xa5, 0x82, ++ 0xfa, 0xa5, 0x75, 0x99, 0xf1, 0x5c, 0x47, 0xab, 0xe2, 0x3e, 0x90, 0x06, ++ 0xe3, 0xb5, 0x96, 0x49, 0x5e, 0xb4, 0x67, 0xbb, 0xd2, 0x99, 0x71, 0xfc, ++ 0x5b, 0x7c, 0xb2, 0x21, 0x1e, 0x86, 0xb1, 0x67, 0x5c, 0xd7, 0x05, 0xaf, ++ 0x89, 0xf0, 0xe9, 0x34, 0x85, 0xdd, 0xd0, 0x84, 0x39, 0x6d, 0xad, 0x99, ++ 0xe4, 0xc8, 0x79, 0x98, 0x47, 0xc9, 0xa0, 0x94, 0x6e, 0xda, 0xdf, 0x7e, ++ 0x64, 0xd9, 0x96, 0x5e, 0x78, 0xce, 0xca, 0xc5, 0xbc, 0x12, 0xbe, 0x77, ++ 0x7a, 0x3b, 0xce, 0xb7, 0xd0, 0x78, 0xc9, 0x2c, 0x36, 0xcf, 0x9a, 0xbd, ++ 0xdd, 0xb7, 0x90, 0x89, 0x23, 0xc0, 0xf8, 0xde, 0xbd, 0x17, 0xe3, 0x12, ++ 0xf6, 0x01, 0x6c, 0x00, 0x9e, 0xdf, 0x71, 0x33, 0xbb, 0x17, 0xef, 0x57, ++ 0x78, 0x4c, 0x9c, 0x7b, 0x5c, 0xeb, 0x0c, 0x90, 0xbe, 0x4d, 0xc8, 0x37, ++ 0x5e, 0x7e, 0xee, 0x45, 0x8b, 0x13, 0x25, 0x8f, 0x56, 0x0c, 0xe7, 0x62, ++ 0x52, 0x7c, 0xc6, 0x7a, 0x5a, 0xcc, 0x39, 0x48, 0x4d, 0x5e, 0xd3, 0x11, ++ 0x3a, 0x80, 0xff, 0x04, 0x71, 0xef, 0x43, 0xca, 0x78, 0xbe, 0x7e, 0x8c, ++ 0x57, 0xf5, 0xcb, 0xe8, 0x9c, 0x6f, 0x4a, 0x3a, 0xf3, 0x86, 0xf1, 0xfd, ++ 0x64, 0x07, 0xe5, 0x33, 0x3b, 0x1c, 0x7c, 0x7e, 0xda, 0x7c, 0x61, 0x3e, ++ 0x24, 0x0f, 0x00, 0x4c, 0x7c, 0x3e, 0xf9, 0x6d, 0x41, 0xb4, 0xc3, 0x61, ++ 0x5e, 0x31, 0x7c, 0xcc, 0xe8, 0xdc, 0x13, 0xcc, 0xef, 0x78, 0xcc, 0xfc, ++ 0x0c, 0x76, 0xdc, 0x1d, 0x56, 0xa1, 0x1f, 0x14, 0xa6, 0xa0, 0x1c, 0x71, ++ 0x58, 0x5b, 0x99, 0x80, 0xf3, 0x05, 0x63, 0x9e, 0x69, 0x90, 0x61, 0xde, ++ 0x41, 0x72, 0x07, 0x5c, 0xe1, 0x3d, 0x8c, 0x93, 0x23, 0x4d, 0xb5, 0x60, ++ 0xde, 0x82, 0x1b, 0xbd, 0xe0, 0x3c, 0xfa, 0x5e, 0x4c, 0xbf, 0x9e, 0x6e, ++ 0xfd, 0x79, 0xb1, 0xeb, 0x85, 0xde, 0x28, 0xca, 0x64, 0xf9, 0x74, 0xae, ++ 0xb0, 0xb9, 0x1b, 0xc9, 0xad, 0xdc, 0xda, 0x12, 0x76, 0x02, 0xea, 0x52, ++ 0x3d, 0xa7, 0x8f, 0xbe, 0x6b, 0x19, 0xd1, 0x7d, 0xdf, 0x88, 0xc8, 0x63, ++ 0x59, 0x65, 0x27, 0x7b, 0x4c, 0xbb, 0x77, 0x40, 0x52, 0x58, 0x50, 0x2d, ++ 0xe8, 0xa4, 0x37, 0x80, 0xc8, 0x0a, 0x3c, 0x17, 0xaa, 0xac, 0x01, 0x9a, ++ 0x81, 0x7e, 0xcd, 0x91, 0x12, 0xd3, 0xbd, 0x00, 0xd4, 0x06, 0x7c, 0x05, ++ 0xe3, 0xdf, 0x6b, 0xf5, 0x3d, 0x68, 0x85, 0x76, 0x75, 0xb7, 0x04, 0x32, ++ 0x4d, 0xc3, 0x70, 0x39, 0xc5, 0xab, 0x5a, 0x8a, 0xe8, 0x14, 0xef, 0x40, ++ 0x8c, 0x30, 0x99, 0x96, 0xfb, 0x5a, 0x0e, 0xf6, 0x22, 0x51, 0xc3, 0xd8, ++ 0x0d, 0xf8, 0xde, 0xd7, 0x82, 0xb4, 0x5a, 0xaf, 0xd5, 0x41, 0x20, 0xe2, ++ 0x7d, 0x0b, 0xf5, 0xf6, 0x8e, 0xba, 0xcf, 0x0a, 0x72, 0xb2, 0x3e, 0x97, ++ 0xd7, 0x57, 0xae, 0xf1, 0xad, 0x5a, 0x03, 0xe3, 0xc9, 0x4e, 0xff, 0x4a, ++ 0x2b, 0xf2, 0xb1, 0xd5, 0x3d, 0x88, 0xf6, 0x2f, 0xc2, 0xd7, 0x76, 0xee, ++ 0x5d, 0x9b, 0xe7, 0x80, 0x4d, 0xe1, 0x52, 0x3b, 0x4c, 0xe2, 0xe6, 0x08, ++ 0x00, 0x14, 0xf0, 0xdf, 0x0f, 0x79, 0x90, 0xec, 0xe4, 0x56, 0x33, 0x12, ++ 0xc9, 0x66, 0x87, 0x56, 0x0f, 0x93, 0x1d, 0xed, 0x6f, 0x3c, 0x42, 0x7e, ++ 0x79, 0x65, 0xc3, 0x11, 0x7a, 0x6f, 0xc2, 0x3a, 0x94, 0x7d, 0xd2, 0xc2, ++ 0xa5, 0xd9, 0xb0, 0xce, 0x8d, 0xd6, 0x5b, 0xca, 0x32, 0x07, 0xc2, 0x78, ++ 0x8d, 0x73, 0x33, 0x4d, 0x20, 0xa2, 0x7f, 0x63, 0xbd, 0xa5, 0x45, 0x49, ++ 0xd7, 0xc3, 0xe1, 0x56, 0x03, 0x1c, 0x94, 0x15, 0xd3, 0x5b, 0x0e, 0x8e, ++ 0xd3, 0xc3, 0x61, 0x7a, 0x0b, 0xea, 0xeb, 0x6b, 0x85, 0xc3, 0x6f, 0xd6, ++ 0x4c, 0x5f, 0xb5, 0xa6, 0xe7, 0xb5, 0xaf, 0x3b, 0xcb, 0xe6, 0xdf, 0x8a, ++ 0x78, 0x99, 0x54, 0x6c, 0x22, 0x39, 0x35, 0xea, 0xa8, 0x83, 0xfc, 0x35, ++ 0xf8, 0xd9, 0x28, 0x3e, 0x25, 0xc6, 0xd9, 0x90, 0xe0, 0xdc, 0xa3, 0x66, ++ 0x8f, 0x6b, 0xed, 0x34, 0x3a, 0x4a, 0x44, 0x27, 0x79, 0xcc, 0x3d, 0x88, ++ 0xeb, 0x17, 0x23, 0xbd, 0xd4, 0x63, 0x7e, 0x37, 0xc6, 0xef, 0x02, 0x01, ++ 0x6f, 0xd9, 0xf0, 0x4e, 0x3a, 0x65, 0xee, 0xc0, 0x70, 0x3c, 0x9f, 0x9e, ++ 0x65, 0xbb, 0x3b, 0x6c, 0xd5, 0xc5, 0xf5, 0x26, 0x15, 0x2f, 0x95, 0x73, ++ 0x61, 0x3e, 0x94, 0x33, 0x03, 0xcf, 0xd3, 0x6b, 0x83, 0xb6, 0xfe, 0x40, ++ 0xa7, 0xe9, 0x3e, 0x13, 0xe5, 0x23, 0x67, 0xd9, 0x02, 0x07, 0x70, 0x5d, ++ 0xae, 0x99, 0x91, 0x30, 0xe6, 0xea, 0x8c, 0x62, 0x81, 0xfb, 0xa5, 0xbc, ++ 0x4e, 0x7a, 0xd7, 0xbe, 0x53, 0xb7, 0x8b, 0xfb, 0xa9, 0x75, 0x73, 0x4d, ++ 0xa1, 0x15, 0x24, 0x0f, 0xda, 0x24, 0x5c, 0x77, 0x27, 0xde, 0xdb, 0x62, ++ 0xf0, 0x1e, 0xe1, 0x78, 0x6f, 0x3a, 0x46, 0x78, 0xaf, 0x6a, 0x3e, 0xc6, ++ 0xf1, 0xde, 0xb4, 0xbc, 0xc4, 0x2e, 0xf6, 0x37, 0xd0, 0x0f, 0xac, 0x67, ++ 0x91, 0x61, 0x88, 0xcf, 0x0f, 0xd6, 0x54, 0x96, 0x29, 0x40, 0xd7, 0x7d, ++ 0x92, 0x22, 0x75, 0x48, 0x0f, 0x2a, 0x5b, 0x5c, 0x56, 0x6e, 0x23, 0xb8, ++ 0xbf, 0x8f, 0xeb, 0xe9, 0x02, 0x77, 0x31, 0x3f, 0x0d, 0xfe, 0x89, 0xf0, ++ 0x56, 0x7f, 0x30, 0xf7, 0x47, 0xf9, 0xe8, 0x27, 0x1d, 0x32, 0xd1, 0x7e, ++ 0x86, 0x06, 0xaf, 0x8e, 0x76, 0x36, 0x9e, 0x77, 0xb7, 0xc7, 0x1e, 0xf8, ++ 0x0b, 0x7e, 0xa7, 0x7a, 0x74, 0xdb, 0xab, 0x28, 0xde, 0x77, 0x1c, 0x7c, ++ 0x8b, 0xf6, 0xd5, 0x5d, 0x87, 0xa6, 0xed, 0xc5, 0xfe, 0xae, 0x19, 0x80, ++ 0x09, 0x4f, 0xe7, 0x77, 0xeb, 0x0f, 0xad, 0x28, 0x41, 0xfa, 0xaf, 0x8f, ++ 0x50, 0x58, 0x0d, 0xe4, 0x4c, 0x24, 0x88, 0x76, 0x47, 0x62, 0x78, 0x70, ++ 0xbe, 0xe8, 0x80, 0x47, 0xe3, 0x31, 0x82, 0x8f, 0x09, 0xeb, 0xf0, 0x7c, ++ 0xab, 0x38, 0x97, 0x52, 0xd4, 0x24, 0xf9, 0x50, 0xef, 0xf6, 0x49, 0x02, ++ 0xbb, 0x04, 0xca, 0xaf, 0xac, 0xdc, 0x2f, 0x74, 0xda, 0x64, 0x5a, 0x8f, ++ 0xd3, 0xc6, 0xf5, 0x7b, 0xfa, 0xa1, 0x7d, 0x32, 0xfa, 0x19, 0x45, 0xab, ++ 0x4c, 0xd4, 0x3e, 0x1d, 0xcb, 0x7c, 0xfd, 0xfa, 0x57, 0x89, 0x7e, 0x8a, ++ 0x21, 0xcf, 0x4c, 0xc3, 0xa7, 0x46, 0x47, 0x40, 0x38, 0x49, 0xb7, 0xc0, ++ 0x9c, 0xc7, 0x24, 0x07, 0xcc, 0xb6, 0x91, 0x7a, 0xba, 0x49, 0x4d, 0xca, ++ 0x85, 0xf7, 0xa3, 0x5a, 0xee, 0xbe, 0x1f, 0xf5, 0x9b, 0xd6, 0xef, 0x27, ++ 0xcb, 0x98, 0xf7, 0x1e, 0xdd, 0xf9, 0x72, 0xa0, 0x9f, 0x13, 0x06, 0x7a, ++ 0x1b, 0xa2, 0xda, 0x10, 0x6e, 0x5a, 0x7b, 0xa4, 0x4b, 0x7f, 0x9c, 0x7b, ++ 0x17, 0xa0, 0x5f, 0x37, 0x5b, 0x3a, 0xff, 0x0e, 0xc6, 0x55, 0xb7, 0xb7, ++ 0x2c, 0x95, 0xe9, 0x9c, 0xe2, 0x35, 0xe2, 0xb5, 0xd0, 0xc2, 0x6a, 0x70, ++ 0xfe, 0x85, 0x49, 0xac, 0x66, 0x07, 0xf4, 0x2f, 0x4c, 0x86, 0x12, 0xeb, ++ 0x69, 0xa2, 0xde, 0x5d, 0xd4, 0xb3, 0x45, 0xd9, 0x47, 0x3c, 0x1f, 0xcc, ++ 0xeb, 0x79, 0x1f, 0x7a, 0x4d, 0x92, 0x03, 0xe3, 0x34, 0x3c, 0x6e, 0x38, ++ 0xd4, 0x26, 0xf6, 0x73, 0x15, 0xf7, 0x20, 0xe4, 0xa3, 0xa1, 0x36, 0x1e, ++ 0x1f, 0x2f, 0xca, 0xb4, 0x93, 0xfc, 0xd7, 0xf8, 0x55, 0x01, 0x70, 0xe2, ++ 0x7e, 0xa3, 0x22, 0xf6, 0x1d, 0x73, 0x23, 0xb9, 0x26, 0xc4, 0xa3, 0xc6, ++ 0xbf, 0x4a, 0xc4, 0x14, 0x76, 0x82, 0x1e, 0xcc, 0x55, 0x3c, 0x26, 0xdc, ++ 0x7f, 0x7e, 0x7d, 0x19, 0xc0, 0x41, 0x49, 0x2c, 0x5f, 0x6e, 0x1e, 0xc8, ++ 0xcf, 0x8f, 0xc5, 0x3e, 0x1f, 0x6b, 0x33, 0x19, 0xce, 0x83, 0xfb, 0x3a, ++ 0xcf, 0x77, 0x8e, 0x45, 0x3c, 0x55, 0x5a, 0xdb, 0x7e, 0x32, 0x0d, 0xde, ++ 0x56, 0x0d, 0xbc, 0x48, 0xfb, 0x3f, 0x2b, 0x92, 0xaa, 0xc6, 0x5e, 0xe9, ++ 0x1c, 0x78, 0xec, 0x3c, 0x5e, 0xbf, 0xfc, 0xbb, 0x24, 0xa4, 0xaf, 0xe6, ++ 0xa8, 0x25, 0xee, 0x79, 0x91, 0x07, 0xc4, 0xfa, 0x0f, 0x2e, 0x9b, 0x49, ++ 0xfd, 0x1e, 0xd6, 0xce, 0x83, 0x08, 0xbb, 0xe5, 0x5b, 0x24, 0x9a, 0xa0, ++ 0xec, 0xcb, 0xe3, 0x47, 0x85, 0x96, 0xa0, 0x92, 0x8a, 0xfa, 0x2f, 0x89, ++ 0xc7, 0x3b, 0x0a, 0x93, 0xb8, 0x7e, 0x64, 0xdd, 0x73, 0xe8, 0x9e, 0x8c, ++ 0x42, 0xec, 0x8b, 0xc2, 0xfa, 0xba, 0x41, 0x94, 0xb7, 0x52, 0x98, 0x16, ++ 0x2a, 0xa7, 0xfa, 0xe0, 0x3c, 0xc6, 0xf3, 0x3e, 0x75, 0xf9, 0x85, 0x16, ++ 0xd6, 0x61, 0x5f, 0x11, 0xca, 0x73, 0x11, 0x9f, 0x81, 0x95, 0x78, 0xae, ++ 0x86, 0xc9, 0x39, 0x34, 0xfe, 0x8d, 0xcc, 0x68, 0x4f, 0x15, 0x66, 0xd7, ++ 0xec, 0xa7, 0xf7, 0x96, 0x1c, 0xda, 0x87, 0x62, 0x51, 0x6e, 0xdf, 0x68, ++ 0xf6, 0xd0, 0x78, 0xb1, 0xbf, 0x52, 0xd8, 0xa7, 0xbe, 0x8c, 0xe6, 0x99, ++ 0xcc, 0xc7, 0x29, 0x66, 0xc6, 0xf3, 0xc3, 0x85, 0xd7, 0x05, 0x15, 0xbc, ++ 0xe7, 0x82, 0xe5, 0xe5, 0xd0, 0xbc, 0x4a, 0xad, 0x31, 0xef, 0x07, 0xf3, ++ 0xfb, 0x45, 0xb4, 0x75, 0x8c, 0xef, 0x62, 0x47, 0xd5, 0x7b, 0xf1, 0x9e, ++ 0x91, 0x49, 0x03, 0xe6, 0x7a, 0xcb, 0xc4, 0xf3, 0x8b, 0xf0, 0x6f, 0x1f, ++ 0x0b, 0x9b, 0x73, 0x4b, 0x7e, 0xa7, 0x7c, 0xbf, 0xc9, 0x73, 0x87, 0xb7, ++ 0xcc, 0x60, 0x7f, 0xd4, 0x7b, 0x91, 0x0f, 0xdf, 0xf8, 0x5a, 0x9e, 0x13, ++ 0x6f, 0x1f, 0xfc, 0xb0, 0xe0, 0xfb, 0x83, 0xcb, 0xfc, 0x5e, 0xdc, 0x6f, ++ 0x7c, 0xce, 0x06, 0xf8, 0x00, 0xbf, 0xbb, 0xc4, 0x23, 0xad, 0x72, 0x7a, ++ 0xae, 0x0e, 0xbf, 0x58, 0xbc, 0xc5, 0xc2, 0xef, 0x5b, 0xcd, 0xf3, 0xc9, ++ 0x7e, 0x8b, 0x85, 0x5b, 0xf1, 0x87, 0xde, 0xb2, 0x54, 0x4f, 0x57, 0x38, ++ 0xc5, 0xc2, 0x65, 0x3c, 0xab, 0x1f, 0x40, 0xf7, 0xd7, 0x08, 0x38, 0xc7, ++ 0xc2, 0xe5, 0x75, 0x2b, 0xa7, 0x87, 0xd7, 0xf3, 0x2d, 0x21, 0xf4, 0x2f, ++ 0x5e, 0x57, 0x00, 0xce, 0x80, 0xaf, 0xd7, 0x3d, 0x12, 0xf9, 0x1b, 0x85, ++ 0xe2, 0x7e, 0x0d, 0x20, 0x72, 0x4e, 0x2f, 0x1a, 0xfd, 0x24, 0xe5, 0x70, ++ 0x7a, 0x49, 0x36, 0xc2, 0x3d, 0x16, 0xbe, 0xb1, 0xf0, 0xd4, 0xe4, 0xc0, ++ 0xab, 0x08, 0x2f, 0xca, 0x2f, 0xf1, 0x95, 0x8f, 0xcf, 0xe8, 0x5c, 0x7f, ++ 0x61, 0xf7, 0x9a, 0x96, 0x14, 0x1d, 0xbd, 0x68, 0xeb, 0x2f, 0xcc, 0x16, ++ 0x74, 0xba, 0xa7, 0x3f, 0x9f, 0x87, 0x26, 0x37, 0xae, 0x13, 0x72, 0x44, ++ 0xc8, 0x0f, 0xcd, 0x5e, 0x1e, 0x2f, 0xc6, 0x03, 0x7b, 0x99, 0xec, 0xe1, ++ 0xd2, 0x74, 0x27, 0xc5, 0x65, 0x4b, 0x2b, 0xf9, 0x38, 0xa5, 0xfd, 0x1c, ++ 0x1b, 0x31, 0xbf, 0x81, 0x85, 0x6f, 0xa4, 0x7c, 0xd9, 0x42, 0x26, 0x7e, ++ 0x51, 0x6e, 0xdf, 0x82, 0x3d, 0xca, 0xe9, 0xb3, 0x79, 0xc2, 0x29, 0xf4, ++ 0xaf, 0xfb, 0x58, 0x02, 0xab, 0x9c, 0x18, 0x87, 0x90, 0x52, 0x68, 0x5f, ++ 0x09, 0xe0, 0x7e, 0x3c, 0x06, 0xee, 0xc7, 0x8d, 0x70, 0x37, 0xda, 0xc9, ++ 0xb1, 0x70, 0x78, 0x0e, 0xff, 0x63, 0x4c, 0x57, 0x78, 0x69, 0xf4, 0xd6, ++ 0x62, 0x13, 0x76, 0x75, 0x0f, 0xd6, 0x13, 0xed, 0xde, 0xa1, 0x2f, 0x8d, ++ 0x48, 0x46, 0xf9, 0xcd, 0x9a, 0x53, 0xe3, 0xfa, 0xe9, 0xa3, 0x8e, 0xfa, ++ 0x3b, 0xc6, 0x11, 0x74, 0x4b, 0x74, 0x29, 0xb1, 0x40, 0xc7, 0x73, 0x37, ++ 0xd0, 0x41, 0xd3, 0x80, 0xd5, 0x8f, 0xa1, 0x39, 0x33, 0xd6, 0x5a, 0x2f, ++ 0x23, 0xfd, 0x8d, 0x65, 0xbe, 0x34, 0xbc, 0xcf, 0x04, 0x93, 0x64, 0x71, ++ 0x9e, 0xda, 0xbc, 0x86, 0x4b, 0xfe, 0x77, 0x50, 0x9e, 0x8d, 0x69, 0x9b, ++ 0x98, 0xa6, 0xbf, 0xdf, 0x44, 0xfb, 0xbe, 0x06, 0xe7, 0x71, 0x02, 0xce, ++ 0xe3, 0x58, 0x70, 0x2f, 0xc6, 0x51, 0xc6, 0x31, 0xe5, 0xaf, 0xfa, 0x78, ++ 0x83, 0x36, 0xde, 0x9f, 0x6c, 0x22, 0xde, 0x90, 0xcd, 0xb2, 0x71, 0x3d, ++ 0x45, 0xb8, 0x39, 0x90, 0xde, 0x39, 0x9e, 0xb6, 0xbe, 0x3e, 0x79, 0x2c, ++ 0x4c, 0xf7, 0xdf, 0x48, 0x56, 0x3a, 0xa7, 0x07, 0xff, 0x0b, 0x9a, 0x53, ++ 0x3b, 0xbf, 0xa7, 0xe5, 0x3f, 0x4f, 0x72, 0x4e, 0xfb, 0xd4, 0x46, 0x72, ++ 0xb8, 0x86, 0xf1, 0x3c, 0x9f, 0x30, 0x21, 0xb1, 0x48, 0xbc, 0x2f, 0x12, ++ 0xf7, 0x8c, 0xb1, 0x88, 0x92, 0xe8, 0x5e, 0x29, 0xf6, 0x4d, 0x52, 0xe7, ++ 0xfc, 0xbe, 0xb0, 0x49, 0x0a, 0xdd, 0x93, 0x21, 0xe6, 0x77, 0x76, 0x8b, ++ 0x35, 0x88, 0xf9, 0x46, 0x0f, 0x49, 0x81, 0x4b, 0xf8, 0x9d, 0x33, 0xd2, ++ 0xa1, 0xa1, 0xc4, 0xaf, 0x4a, 0xb8, 0x3f, 0xdd, 0x33, 0x11, 0xf3, 0xfe, ++ 0x62, 0x53, 0x4b, 0x15, 0xbe, 0x87, 0x76, 0xf3, 0xa9, 0x9d, 0x58, 0xd7, ++ 0x62, 0x99, 0xc7, 0x79, 0x23, 0xbb, 0x2c, 0x74, 0x9f, 0x4f, 0x42, 0xfb, ++ 0xd3, 0x0a, 0xaa, 0x4b, 0x27, 0x07, 0x8a, 0xec, 0x5c, 0x8e, 0x8c, 0xc7, ++ 0x78, 0x5f, 0x1e, 0xc9, 0x0b, 0x05, 0xcb, 0xdd, 0xe7, 0x79, 0xde, 0x78, ++ 0x71, 0x53, 0x81, 0x82, 0xdf, 0x39, 0x70, 0x81, 0xe7, 0x59, 0x97, 0x30, ++ 0x9f, 0x82, 0x7e, 0xd7, 0x8d, 0x51, 0xa3, 0xbf, 0x76, 0x55, 0x3a, 0x75, ++ 0xc7, 0xc6, 0x6f, 0xc4, 0xbd, 0x44, 0x4a, 0xa4, 0x37, 0xc2, 0x55, 0xb3, ++ 0xcb, 0xf2, 0xed, 0x81, 0xee, 0x76, 0xc0, 0xd7, 0x2a, 0x21, 0xdf, 0x9a, ++ 0xcf, 0x4f, 0xf0, 0x20, 0xbe, 0x36, 0x0e, 0x18, 0x79, 0xf3, 0x74, 0x68, ++ 0x92, 0x3b, 0x70, 0xf8, 0x34, 0x34, 0x2b, 0x4c, 0xd6, 0x56, 0x15, 0xf5, ++ 0xdd, 0x5d, 0x82, 0xae, 0x46, 0x23, 0x5d, 0x49, 0x64, 0xf5, 0x68, 0x74, ++ 0xe5, 0xb1, 0xa3, 0x1d, 0xbd, 0x26, 0x86, 0xae, 0xdc, 0xa9, 0x06, 0x3f, ++ 0x6e, 0x16, 0x0b, 0xd3, 0x81, 0xc7, 0xa2, 0x1a, 0xf5, 0x92, 0xc1, 0x1f, ++ 0x14, 0x76, 0x48, 0xac, 0x7d, 0xde, 0x69, 0x97, 0xd7, 0xc7, 0xf5, 0xe7, ++ 0x58, 0x0b, 0x38, 0xa8, 0x40, 0x3f, 0xb3, 0x05, 0x7c, 0x57, 0xa5, 0x98, ++ 0x83, 0x28, 0xb7, 0x94, 0xfb, 0x78, 0xbe, 0xcf, 0x5d, 0x8c, 0xf5, 0xc6, ++ 0x3c, 0xa0, 0xbb, 0x6a, 0x54, 0x83, 0xff, 0x39, 0x3b, 0x45, 0x21, 0xfc, ++ 0xcd, 0x5e, 0x6e, 0xa3, 0x3c, 0x4f, 0xbc, 0x37, 0x6a, 0x2e, 0xd4, 0x03, ++ 0xf0, 0x9c, 0xce, 0x35, 0x0c, 0xe0, 0xf7, 0x48, 0x75, 0xe0, 0xb3, 0x56, ++ 0xd7, 0x1f, 0xe9, 0xc0, 0x91, 0x41, 0x74, 0x3b, 0x5b, 0xec, 0x87, 0xff, ++ 0x49, 0xe2, 0x7e, 0xf8, 0xec, 0x94, 0x4f, 0xd2, 0xc9, 0x69, 0x0f, 0xaa, ++ 0x17, 0xf4, 0xf4, 0x19, 0xfb, 0xfd, 0x84, 0xe3, 0xc6, 0xf4, 0x5b, 0x25, ++ 0xf1, 0x78, 0xce, 0x2a, 0xd5, 0x97, 0xe9, 0xd5, 0xd9, 0x1b, 0x13, 0xed, ++ 0xdc, 0x7e, 0xba, 0xe0, 0x2e, 0x5b, 0x67, 0xba, 0xc2, 0xfd, 0x06, 0x01, ++ 0x6b, 0x8f, 0x7c, 0x45, 0x77, 0x1f, 0x50, 0x5b, 0x8a, 0x75, 0x66, 0xbc, ++ 0x7b, 0x24, 0xb4, 0xf1, 0x34, 0x7b, 0xaf, 0x28, 0xc0, 0xfd, 0xf0, 0x44, ++ 0xe3, 0xf6, 0x8d, 0x94, 0x91, 0x1d, 0x66, 0xfa, 0x79, 0x58, 0x46, 0xfb, ++ 0xba, 0x6f, 0x84, 0x91, 0x3d, 0x5c, 0x14, 0xf1, 0x99, 0xe6, 0x19, 0xec, ++ 0x72, 0xee, 0x8f, 0x76, 0xb1, 0xcb, 0xf1, 0x3e, 0x03, 0xa8, 0x2f, 0x69, ++ 0xdc, 0xcb, 0xed, 0xf2, 0x86, 0xe5, 0x64, 0xdf, 0x2f, 0x01, 0xfb, 0x1e, ++ 0xe5, 0xf9, 0x06, 0xdc, 0xf3, 0xec, 0xc1, 0xf8, 0x84, 0xf2, 0xc9, 0x5e, ++ 0xef, 0xf0, 0x2b, 0x31, 0xbf, 0xa5, 0xa8, 0x41, 0xea, 0xf0, 0x3b, 0x15, ++ 0xc0, 0x7b, 0x5e, 0x3d, 0x6f, 0xbf, 0xea, 0x91, 0x71, 0xea, 0xc3, 0x0a, ++ 0xfa, 0x85, 0x81, 0x4c, 0xd5, 0x8b, 0xe1, 0x81, 0x92, 0xd5, 0x56, 0xf0, ++ 0x73, 0xea, 0x72, 0x98, 0x8d, 0x81, 0x9f, 0xb3, 0xc2, 0x5e, 0x32, 0x7e, ++ 0x2d, 0xfa, 0xa5, 0xa9, 0x3e, 0x89, 0xa5, 0x50, 0x7d, 0xb5, 0x23, 0xeb, ++ 0xda, 0xfd, 0xd8, 0x55, 0xf6, 0xe2, 0xd5, 0xe8, 0xc7, 0x26, 0xf2, 0x27, ++ 0xab, 0xed, 0x1e, 0x82, 0x5f, 0x22, 0x7f, 0x52, 0x76, 0xfa, 0x57, 0xd9, ++ 0x75, 0x71, 0x00, 0x90, 0x8b, 0x71, 0xed, 0x8f, 0x49, 0xce, 0x92, 0x35, ++ 0xd8, 0x4e, 0x93, 0x17, 0x0f, 0x9b, 0xc2, 0x79, 0x3f, 0xed, 0x46, 0xf9, ++ 0x41, 0x94, 0x5f, 0x71, 0x73, 0xed, 0xdd, 0x64, 0xef, 0x4f, 0xae, 0xad, ++ 0xf0, 0xe2, 0x95, 0x6e, 0xed, 0xfb, 0x2e, 0xf7, 0xc7, 0xfc, 0x8a, 0x22, ++ 0x81, 0xef, 0x5f, 0xd8, 0xb9, 0x3d, 0x59, 0x9d, 0xc4, 0xed, 0x48, 0x49, ++ 0x0a, 0xfc, 0x02, 0xf9, 0xb3, 0x75, 0xc0, 0xd3, 0x6b, 0x0b, 0x80, 0x3f, ++ 0x66, 0x35, 0xf1, 0xbc, 0x0d, 0xdb, 0x75, 0x97, 0x7b, 0xd3, 0x7d, 0x40, ++ 0x23, 0x9f, 0xfe, 0x79, 0x01, 0x8c, 0xff, 0x51, 0x44, 0xa1, 0xf8, 0x42, ++ 0xb3, 0x93, 0xc7, 0x9b, 0x3f, 0x62, 0x12, 0xd9, 0xab, 0x45, 0x47, 0x2c, ++ 0xfe, 0x46, 0xc0, 0xc3, 0x65, 0x90, 0x50, 0x76, 0x9d, 0xdf, 0x72, 0x99, ++ 0x95, 0x51, 0x9d, 0xf5, 0xcc, 0x30, 0x9c, 0x0f, 0xfe, 0x88, 0xed, 0xcd, ++ 0xfb, 0x29, 0x7c, 0x27, 0x58, 0xc3, 0xf3, 0x94, 0x2e, 0xd4, 0xe4, 0x24, ++ 0x23, 0xde, 0x9b, 0x55, 0x63, 0xfc, 0x77, 0xab, 0x9d, 0xe7, 0xb7, 0x6d, ++ 0x15, 0xf4, 0x37, 0x0b, 0xef, 0x8d, 0x1c, 0x8e, 0xed, 0xc2, 0xd9, 0x78, ++ 0x7f, 0xcb, 0x2c, 0x25, 0xac, 0x52, 0x7e, 0x46, 0xd4, 0xcc, 0xef, 0x39, ++ 0x84, 0x79, 0xe0, 0x7c, 0x9a, 0x6d, 0xc6, 0x71, 0x76, 0xda, 0xb9, 0xdf, ++ 0xb5, 0xd3, 0xce, 0xed, 0xf8, 0x59, 0xe2, 0xde, 0xc9, 0x66, 0x5b, 0xec, ++ 0x38, 0x0a, 0x1f, 0x5f, 0xdc, 0x33, 0x17, 0x0b, 0xf7, 0x34, 0x7b, 0xe9, ++ 0x8b, 0xb8, 0x9e, 0xcb, 0xcc, 0xd7, 0x44, 0x78, 0x02, 0x79, 0x85, 0x7a, ++ 0xa1, 0x68, 0x44, 0xcb, 0x51, 0xb4, 0x17, 0xae, 0xae, 0x7f, 0x7c, 0x12, ++ 0xea, 0x9f, 0xea, 0xcb, 0x52, 0xb8, 0x0f, 0xc6, 0xa7, 0x1b, 0x55, 0xf2, ++ 0xdf, 0xcf, 0x88, 0x73, 0xe2, 0x67, 0x1b, 0xf7, 0x67, 0xdc, 0x0d, 0x65, ++ 0xe5, 0xf6, 0x3f, 0xb8, 0xd0, 0xdf, 0x7b, 0x4d, 0xe0, 0xe9, 0xac, 0xd2, ++ 0x4a, 0xf7, 0xbc, 0x2c, 0x79, 0x5e, 0xa6, 0x7b, 0x0a, 0xe0, 0xbb, 0x19, ++ 0xdf, 0xa1, 0xfe, 0xf3, 0x0a, 0xf9, 0x39, 0x2b, 0x7e, 0x4e, 0x48, 0xd3, ++ 0xcb, 0x05, 0x5f, 0xef, 0xcf, 0xf6, 0xf3, 0xe0, 0x20, 0x9d, 0xfb, 0xd1, ++ 0xec, 0xce, 0x71, 0xd6, 0x60, 0x08, 0xe7, 0xd7, 0xbc, 0x5c, 0x26, 0xb9, ++ 0x01, 0x7a, 0xdb, 0x70, 0xef, 0xcf, 0x8d, 0xe2, 0xde, 0x9f, 0x58, 0x7b, ++ 0xf4, 0x63, 0xbb, 0x16, 0x67, 0xce, 0xa0, 0xbc, 0x9f, 0x07, 0xdc, 0xfc, ++ 0x3b, 0x89, 0xf8, 0xbf, 0x28, 0x9a, 0xca, 0x42, 0x3a, 0xf9, 0x50, 0xa4, ++ 0x84, 0x65, 0x9c, 0x7f, 0x51, 0x34, 0x83, 0x85, 0x00, 0xbe, 0x67, 0x0f, ++ 0xe6, 0x3e, 0x56, 0x8e, 0xf4, 0xca, 0x54, 0x6f, 0x3f, 0x1c, 0x56, 0x61, ++ 0x2d, 0x64, 0x0f, 0x8b, 0xfd, 0x1b, 0xf8, 0xb5, 0xe0, 0xfd, 0x74, 0xbb, ++ 0x45, 0x65, 0x4f, 0xe3, 0xc5, 0xe9, 0x63, 0x89, 0xf9, 0xdc, 0xab, 0x06, ++ 0x43, 0x9b, 0x6f, 0x85, 0x03, 0xdd, 0xc8, 0x3e, 0xc6, 0x10, 0x68, 0x61, ++ 0xa7, 0xdd, 0x77, 0x63, 0xd4, 0x18, 0x57, 0x8d, 0xb5, 0x93, 0x4b, 0x9a, ++ 0x87, 0xad, 0x42, 0x93, 0xf2, 0x0c, 0x3e, 0x40, 0xfa, 0x8b, 0xf0, 0x7b, ++ 0x91, 0xba, 0xd8, 0xcf, 0x91, 0x09, 0x71, 0xed, 0x66, 0xc6, 0x1e, 0x25, ++ 0x38, 0x14, 0x3c, 0x9f, 0x37, 0x09, 0xef, 0x7b, 0x29, 0x78, 0xcd, 0xe4, ++ 0xc6, 0xef, 0xee, 0x41, 0xbe, 0xc6, 0x78, 0x7e, 0xe3, 0x45, 0xba, 0x8f, ++ 0xa4, 0x8a, 0x85, 0x6f, 0xc3, 0xf7, 0x55, 0x8d, 0xb2, 0x3b, 0xcc, 0xae, ++ 0x14, 0xcf, 0x5a, 0xf5, 0xc6, 0x8d, 0x30, 0x8f, 0x3d, 0x11, 0xc5, 0x83, ++ 0xfc, 0xbf, 0x27, 0xd2, 0x62, 0x1d, 0x4a, 0x75, 0x13, 0xc5, 0x31, 0x8a, ++ 0x0e, 0x17, 0x0d, 0x46, 0xbe, 0x6d, 0x8e, 0x28, 0x14, 0xff, 0x2f, 0x3a, ++ 0xdf, 0x92, 0x34, 0x2f, 0xbf, 0xd3, 0x7e, 0x69, 0xbe, 0x6c, 0xa2, 0xe7, ++ 0x7b, 0x2e, 0xef, 0xa3, 0xe7, 0xda, 0xb8, 0xcd, 0x91, 0xd4, 0xc1, 0xa8, ++ 0x8f, 0xb7, 0x9b, 0xb8, 0x3f, 0xdd, 0xf2, 0xea, 0xa5, 0x24, 0x94, 0xa7, ++ 0x7b, 0x2e, 0x5f, 0x48, 0xe3, 0xf7, 0x0f, 0x2d, 0xd7, 0xee, 0x05, 0x8a, ++ 0xb5, 0x9b, 0x09, 0x2e, 0xa5, 0x4e, 0xb9, 0x23, 0xce, 0xac, 0xb7, 0xd3, ++ 0x99, 0x5c, 0xf4, 0x36, 0xe6, 0x2b, 0x8d, 0x4f, 0x56, 0x99, 0x4c, 0x78, ++ 0xe0, 0xfe, 0x66, 0x17, 0xfb, 0xe3, 0x43, 0xb6, 0xca, 0xc9, 0xba, 0xda, ++ 0x21, 0x25, 0x68, 0xd7, 0xc8, 0x71, 0xec, 0x91, 0x4e, 0x78, 0x1b, 0xec, ++ 0xe7, 0xfe, 0x49, 0xc2, 0x7e, 0xec, 0xc5, 0x0a, 0xf0, 0x3e, 0xb7, 0xa6, ++ 0xcb, 0x69, 0x8b, 0xe9, 0x5c, 0x67, 0x73, 0x92, 0x7b, 0x05, 0xc5, 0x9d, ++ 0xb8, 0xfd, 0xd0, 0xde, 0x72, 0xfa, 0x67, 0x93, 0xf0, 0xf9, 0x21, 0x99, ++ 0x9f, 0xeb, 0xbf, 0x2c, 0x13, 0x3f, 0xed, 0xdb, 0xbd, 0xb8, 0x4f, 0x9b, ++ 0x43, 0x0f, 0xef, 0x3a, 0xc2, 0xdf, 0x17, 0x59, 0xe7, 0xcf, 0xbd, 0x02, ++ 0xed, 0xbf, 0x38, 0x60, 0xa7, 0x78, 0x39, 0x53, 0xbc, 0x83, 0xe3, 0xc5, ++ 0x45, 0x3a, 0xe3, 0xc4, 0xe1, 0x1e, 0x7c, 0x7f, 0x2b, 0xd8, 0x83, 0xdf, ++ 0x3f, 0xc3, 0xe3, 0x00, 0xdf, 0xea, 0x8c, 0x03, 0x14, 0x25, 0x8d, 0xe4, ++ 0xf7, 0x37, 0xa1, 0x5a, 0xea, 0xbf, 0xfe, 0x98, 0x19, 0xe3, 0x28, 0x7b, ++ 0xec, 0xfe, 0x6f, 0x25, 0x11, 0xdf, 0x34, 0x24, 0xa1, 0x9c, 0xa8, 0xb0, ++ 0x73, 0xb9, 0x14, 0x64, 0x25, 0xd9, 0x60, 0x24, 0xb1, 0xe7, 0x0f, 0x9a, ++ 0x4a, 0x90, 0x4e, 0x46, 0x2c, 0xf7, 0x10, 0xbe, 0xb7, 0xaa, 0x60, 0x4a, ++ 0x21, 0x5f, 0x6c, 0xe6, 0x7e, 0xfb, 0x56, 0x3c, 0x07, 0x0a, 0xe3, 0x2c, ++ 0x6c, 0xa8, 0x37, 0xe7, 0xe8, 0xf0, 0xbb, 0x50, 0xec, 0x37, 0x7d, 0xaa, ++ 0x06, 0x7b, 0xa7, 0xea, 0x9e, 0xff, 0x3e, 0x89, 0xfb, 0xa5, 0x9f, 0x1e, ++ 0x58, 0xf4, 0x14, 0xe5, 0x23, 0xbc, 0x6f, 0x61, 0xfd, 0xe2, 0xd8, 0x9f, ++ 0xa1, 0x24, 0x2e, 0x07, 0x77, 0x9a, 0x83, 0x93, 0xb6, 0x61, 0xbb, 0xe3, ++ 0x26, 0x3a, 0xe7, 0xd1, 0xf2, 0xea, 0xcb, 0xaf, 0xf6, 0x00, 0xfc, 0x2e, ++ 0x3c, 0xea, 0x19, 0x86, 0xf2, 0x7f, 0x59, 0x92, 0x87, 0xe0, 0xd5, 0x74, ++ 0x68, 0x6b, 0x5d, 0x0f, 0x68, 0xd7, 0xf4, 0x21, 0x6a, 0x49, 0x30, 0xb9, ++ 0x37, 0xcd, 0x95, 0x4d, 0xf0, 0xdd, 0x57, 0x98, 0x87, 0xc7, 0xf3, 0xde, ++ 0x36, 0xd1, 0x7c, 0x3b, 0xe2, 0x9f, 0x60, 0x07, 0xe2, 0x7a, 0x7f, 0x20, ++ 0xe6, 0xf3, 0xca, 0x41, 0x93, 0x61, 0xff, 0xea, 0x15, 0x3b, 0xd7, 0x6b, ++ 0x95, 0x49, 0x2a, 0xbd, 0x9f, 0x97, 0xc4, 0xe3, 0x69, 0x3b, 0x0e, 0x96, ++ 0xa4, 0x61, 0xfe, 0xe9, 0x1e, 0x7b, 0x60, 0x3e, 0xc2, 0xb3, 0xfa, 0x93, ++ 0xb6, 0x3a, 0x97, 0xa7, 0x33, 0xfe, 0xa7, 0xd9, 0x81, 0x63, 0xde, 0xde, ++ 0x31, 0x69, 0x08, 0xfc, 0xe7, 0x98, 0x33, 0x26, 0x37, 0xa2, 0xcf, 0xf3, ++ 0xf6, 0x46, 0x19, 0xd7, 0xeb, 0xf9, 0x94, 0xb1, 0x14, 0xa9, 0x6b, 0x7c, ++ 0x0a, 0xc6, 0xab, 0x41, 0x3c, 0x68, 0xe3, 0xbd, 0x72, 0x86, 0x8f, 0x07, ++ 0xf3, 0xd8, 0x87, 0xfc, 0x16, 0x59, 0xce, 0xdc, 0x94, 0x97, 0xc9, 0xfc, ++ 0x3f, 0xca, 0x87, 0xfa, 0x2b, 0xad, 0x4a, 0x2a, 0xe6, 0x2d, 0x6d, 0x15, ++ 0xfb, 0xaa, 0x1a, 0x1e, 0xb4, 0xf5, 0x68, 0xf3, 0xf0, 0x34, 0x30, 0xdf, ++ 0x06, 0x07, 0xb1, 0x86, 0x6f, 0xc7, 0x95, 0xe2, 0xcc, 0x22, 0x3f, 0x72, ++ 0xb8, 0x90, 0x9b, 0x5f, 0xdb, 0x7d, 0xc1, 0x24, 0x1e, 0x07, 0x24, 0x7b, ++ 0xfb, 0xd3, 0x03, 0x76, 0xb2, 0xbb, 0x76, 0x8a, 0x78, 0x35, 0xcb, 0x9c, ++ 0xdb, 0x07, 0xe1, 0xa7, 0xe1, 0x69, 0xbd, 0x28, 0x63, 0xe7, 0x93, 0xe8, ++ 0xfb, 0x8f, 0x27, 0x71, 0xbd, 0xa1, 0x95, 0x5b, 0x55, 0x4f, 0x90, 0xe8, ++ 0xe1, 0x79, 0xae, 0x6f, 0xb7, 0x3a, 0xc3, 0xd6, 0x3c, 0x94, 0x7f, 0x2f, ++ 0xe5, 0x51, 0xdd, 0x13, 0x0c, 0x26, 0x0d, 0xc5, 0x3c, 0xa8, 0xa6, 0x7e, ++ 0x5e, 0xdc, 0xef, 0xc3, 0xfc, 0xcf, 0x24, 0xdd, 0x3e, 0xeb, 0x38, 0x41, ++ 0xe7, 0x9e, 0x86, 0x88, 0x39, 0x47, 0x87, 0x87, 0xc4, 0x72, 0x8d, 0xc3, ++ 0xbd, 0x83, 0x7e, 0x94, 0x06, 0xa2, 0xab, 0xa6, 0xa3, 0x8c, 0xf8, 0x6d, ++ 0xd1, 0x96, 0xfb, 0x78, 0x7c, 0x11, 0xe4, 0x81, 0xb8, 0xcf, 0x89, 0xf6, ++ 0x8f, 0x91, 0x2f, 0xc4, 0x3e, 0x72, 0x96, 0xc4, 0x4b, 0x17, 0xf2, 0xc9, ++ 0x98, 0xe6, 0x0d, 0x2b, 0xb3, 0x3d, 0x74, 0xbe, 0x80, 0xf6, 0x6d, 0x35, ++ 0x38, 0x78, 0x90, 0x2f, 0xa0, 0xdc, 0x2d, 0xf0, 0x82, 0x70, 0xc1, 0xf7, ++ 0x2f, 0x89, 0x75, 0x6b, 0xef, 0x5f, 0x14, 0xf0, 0x1b, 0x2f, 0xe7, 0x27, ++ 0xeb, 0xf3, 0x11, 0x63, 0xcb, 0x3d, 0xcb, 0x32, 0x29, 0xa6, 0xa8, 0xd5, ++ 0x5f, 0x12, 0xf3, 0x5f, 0xc8, 0x1e, 0x25, 0x3b, 0x74, 0xe1, 0xe5, 0x7a, ++ 0xb2, 0x4f, 0x3d, 0x35, 0xbc, 0x5c, 0xf8, 0x00, 0x2f, 0xfb, 0xaf, 0x9f, ++ 0x6b, 0xc6, 0xf8, 0xef, 0xc2, 0x75, 0xf1, 0xef, 0xad, 0x1b, 0x95, 0xc4, ++ 0xed, 0x97, 0xb3, 0x82, 0x0f, 0x98, 0xc9, 0xde, 0x03, 0xf3, 0x39, 0x3a, ++ 0xf4, 0x63, 0x12, 0xd7, 0xaf, 0xa7, 0x1a, 0x1f, 0xdb, 0x9f, 0x4d, 0xfa, ++ 0x24, 0xf0, 0x2a, 0xd2, 0xc7, 0x0d, 0x4d, 0x8f, 0xfe, 0x12, 0xc1, 0xa4, ++ 0xd1, 0xff, 0xa9, 0x4d, 0x2a, 0xf5, 0xd7, 0xe4, 0x88, 0xd6, 0xff, 0x0d, ++ 0x31, 0xfe, 0xf3, 0x6f, 0x73, 0xfe, 0x19, 0xb3, 0x49, 0x2d, 0xc1, 0x7b, ++ 0x8c, 0xc6, 0x04, 0x99, 0x1b, 0xe3, 0xe4, 0xaf, 0x6c, 0xda, 0x2c, 0xa3, ++ 0x5c, 0x7f, 0x05, 0xf9, 0x23, 0x87, 0xcb, 0x0d, 0xd4, 0xc7, 0x9f, 0x1e, ++ 0x78, 0x24, 0xe9, 0x21, 0xa4, 0x83, 0x63, 0x26, 0x86, 0xf1, 0xf8, 0x9d, ++ 0x66, 0x56, 0xb1, 0x5d, 0x87, 0xdf, 0x96, 0x0d, 0x2f, 0x1a, 0xe4, 0xc1, ++ 0xa2, 0x2d, 0xcb, 0x27, 0xe1, 0x38, 0xa3, 0xda, 0x52, 0x25, 0x94, 0xff, ++ 0x9a, 0x1c, 0xd0, 0xf0, 0xbd, 0xd3, 0xec, 0xbd, 0x89, 0xe4, 0xc9, 0x94, ++ 0x18, 0x79, 0x52, 0xc6, 0xfb, 0x47, 0x05, 0x3c, 0x1f, 0x13, 0xf2, 0xe4, ++ 0xb1, 0x89, 0x20, 0x4f, 0xe0, 0x51, 0xca, 0xa6, 0x14, 0x09, 0xc7, 0xd9, ++ 0x69, 0x8e, 0x7f, 0xaf, 0xd5, 0x67, 0x1a, 0xdf, 0x09, 0x7a, 0x1c, 0xdb, ++ 0x29, 0x77, 0x3f, 0xe3, 0x72, 0xb7, 0xcd, 0x95, 0x07, 0xe3, 0x54, 0x4d, ++ 0xbe, 0x40, 0xf1, 0xd7, 0x8e, 0xef, 0x08, 0xba, 0x7b, 0xac, 0x4c, 0xa3, ++ 0xbb, 0x1c, 0x09, 0xe1, 0x08, 0xf6, 0xbc, 0xa9, 0x2f, 0xae, 0x1b, 0xe0, ++ 0x83, 0xf4, 0x0f, 0xf6, 0xfc, 0x9c, 0x69, 0xf9, 0xc4, 0xa5, 0x07, 0x15, ++ 0xda, 0xf7, 0x11, 0xfb, 0x48, 0x22, 0x6f, 0x82, 0x38, 0x4c, 0xc7, 0xbf, ++ 0x9a, 0x9c, 0xfb, 0xda, 0x1e, 0xf8, 0x1b, 0xf2, 0x49, 0x61, 0x59, 0xcd, ++ 0x4a, 0xf4, 0x33, 0xd2, 0xca, 0x83, 0x44, 0xd7, 0xa7, 0xa4, 0x40, 0x9f, ++ 0x54, 0xd0, 0x57, 0xa7, 0x90, 0xaf, 0xe3, 0xc8, 0x85, 0xe3, 0x62, 0x3d, ++ 0x5f, 0xa8, 0x81, 0x3e, 0xee, 0x38, 0xef, 0x3b, 0xf9, 0x88, 0xf5, 0x40, ++ 0x3e, 0xa8, 0x60, 0x01, 0x13, 0xae, 0x83, 0xad, 0x97, 0xdc, 0xfa, 0xf3, ++ 0x0f, 0x9e, 0xf5, 0x9c, 0xde, 0x52, 0x1c, 0x92, 0x21, 0x7f, 0x5c, 0xab, ++ 0x6b, 0xf0, 0xba, 0x91, 0x75, 0xdc, 0x33, 0x98, 0xe2, 0x48, 0x27, 0x3d, ++ 0x65, 0xc6, 0xbc, 0xca, 0xfe, 0x21, 0xae, 0xa7, 0x98, 0x54, 0x42, 0xf4, ++ 0xc8, 0x4c, 0x37, 0xf7, 0x40, 0x7e, 0x3b, 0xa5, 0x32, 0xa2, 0x9f, 0x53, ++ 0x20, 0x17, 0x11, 0x6e, 0x0b, 0xed, 0x46, 0x3f, 0x44, 0x5b, 0x57, 0x4f, ++ 0x07, 0xe7, 0xab, 0x2f, 0x52, 0xf8, 0x3a, 0xfe, 0x28, 0xf8, 0x8e, 0x7c, ++ 0xdc, 0x91, 0xd4, 0x8e, 0xdb, 0x59, 0xc5, 0x26, 0xda, 0x87, 0x45, 0xfa, ++ 0x20, 0x7a, 0x9b, 0x92, 0x4a, 0x7e, 0x0a, 0x38, 0x46, 0x0a, 0xf1, 0x79, ++ 0xc7, 0x3e, 0x43, 0x58, 0x96, 0xb8, 0x3c, 0x90, 0x71, 0x1e, 0x6e, 0xf4, ++ 0xdf, 0x28, 0x0e, 0xb4, 0x81, 0xe7, 0x85, 0x6d, 0xdb, 0x40, 0x74, 0x93, ++ 0x32, 0xd1, 0x4d, 0xe7, 0x19, 0x1e, 0x53, 0xbc, 0xb6, 0x14, 0x5d, 0x1c, ++ 0xb7, 0x65, 0xf3, 0xe3, 0xe4, 0x37, 0x22, 0x3d, 0xe1, 0x1c, 0x12, 0xd1, ++ 0x63, 0x05, 0xd2, 0x23, 0x8b, 0x43, 0x87, 0x21, 0xa0, 0x43, 0xe8, 0x97, ++ 0x3a, 0xb1, 0x86, 0xf0, 0x08, 0xf8, 0x1d, 0xe5, 0x80, 0x71, 0x53, 0xca, ++ 0x02, 0x32, 0xd2, 0x4d, 0x2c, 0x7e, 0xb5, 0xfd, 0x43, 0x0d, 0x1e, 0x3b, ++ 0x63, 0xf6, 0x1b, 0xbf, 0xe7, 0xe0, 0x7c, 0x39, 0x51, 0x94, 0x9e, 0x04, ++ 0x79, 0x27, 0x9d, 0x7a, 0xc2, 0x28, 0x6f, 0x01, 0x5f, 0xdf, 0xe6, 0xf8, ++ 0xea, 0xa4, 0x6f, 0xc4, 0x9b, 0xc6, 0x6f, 0xc3, 0x1d, 0x57, 0xa6, 0xf3, ++ 0x90, 0x83, 0xdf, 0x07, 0x5e, 0xf7, 0xd1, 0x3c, 0xca, 0xf7, 0xd0, 0xf6, ++ 0x99, 0xb4, 0x7d, 0x63, 0xed, 0xfb, 0x77, 0x08, 0x7a, 0x49, 0xb4, 0x4f, ++ 0x94, 0x65, 0x0b, 0xcc, 0x74, 0x18, 0xf6, 0xa3, 0x96, 0xd2, 0x7e, 0x97, ++ 0xc6, 0x27, 0xda, 0xdf, 0xa5, 0x58, 0xba, 0x99, 0xe7, 0xbd, 0x6d, 0xc7, ++ 0x37, 0x08, 0xf7, 0x16, 0x7b, 0x48, 0x7f, 0x5e, 0xcf, 0xad, 0x30, 0x1f, ++ 0xe2, 0xb3, 0xc2, 0x91, 0x43, 0xdf, 0xd3, 0xf0, 0xeb, 0xa9, 0x35, 0xb3, ++ 0xbe, 0xe0, 0x2f, 0x7c, 0x91, 0x33, 0xb7, 0x05, 0x5f, 0x7d, 0xbb, 0x35, ++ 0x58, 0x3e, 0x04, 0xd6, 0xb1, 0xdd, 0x1c, 0x9c, 0x31, 0x99, 0xec, 0x6e, ++ 0xef, 0x4d, 0x38, 0xfe, 0x4d, 0xe5, 0x26, 0xf7, 0x23, 0x12, 0xe6, 0x0b, ++ 0xb8, 0x25, 0x8c, 0x77, 0x10, 0x89, 0x23, 0x5f, 0x1c, 0xe2, 0xdf, 0x61, ++ 0x1e, 0xaf, 0x61, 0xde, 0x4b, 0x05, 0xdc, 0x35, 0x3c, 0x69, 0x70, 0x48, ++ 0xa4, 0xaf, 0x12, 0xe1, 0x27, 0x24, 0xe0, 0x93, 0x2e, 0xde, 0xc7, 0xf2, ++ 0x75, 0xb9, 0x83, 0xf3, 0x73, 0xbe, 0xe3, 0x5a, 0xf9, 0x3a, 0x28, 0x23, ++ 0xdd, 0xbb, 0x58, 0x60, 0x05, 0xde, 0x3f, 0xcd, 0x8a, 0xb8, 0x1c, 0xea, ++ 0xe0, 0xeb, 0x22, 0x46, 0xfb, 0x88, 0x6b, 0xc5, 0x78, 0xda, 0x73, 0xad, ++ 0x1e, 0x87, 0xaf, 0xd7, 0x3a, 0x46, 0xea, 0xf8, 0x7a, 0x74, 0x9b, 0x91, ++ 0xaf, 0xc1, 0xc2, 0x15, 0xfa, 0x94, 0xf8, 0x2b, 0x7d, 0x93, 0xca, 0xf3, ++ 0x68, 0x05, 0x9f, 0x7d, 0x61, 0xe3, 0xf3, 0xfd, 0x95, 0x83, 0xdb, 0x63, ++ 0xe9, 0xa8, 0x3f, 0x00, 0x7f, 0xe9, 0x41, 0xbe, 0x9f, 0xba, 0x54, 0xd0, ++ 0x19, 0x50, 0x10, 0xe5, 0xe5, 0xd5, 0x6f, 0xb2, 0x30, 0xc4, 0x83, 0xc6, ++ 0xf7, 0xae, 0x19, 0xac, 0x44, 0xc5, 0x7d, 0x59, 0xd4, 0x37, 0xd8, 0x6a, ++ 0x46, 0xe0, 0xe8, 0x38, 0xdc, 0x8f, 0xcd, 0x34, 0x7b, 0x70, 0x7f, 0xf8, ++ 0x94, 0x1a, 0x21, 0x3c, 0x9d, 0x02, 0x07, 0xb5, 0x9e, 0xf0, 0xe9, 0xa7, ++ 0x3c, 0x93, 0x53, 0x07, 0x6e, 0xe0, 0xf2, 0x60, 0x72, 0x87, 0xfe, 0xf1, ++ 0xe1, 0x7e, 0x4f, 0xf0, 0x8f, 0x3d, 0xf9, 0x7e, 0x8e, 0xdc, 0x4c, 0x74, ++ 0xbd, 0x74, 0x3c, 0x23, 0xfd, 0xd1, 0xb2, 0x79, 0x14, 0xd1, 0x41, 0x45, ++ 0x79, 0xae, 0x84, 0x74, 0xb6, 0x68, 0x4b, 0x8a, 0x84, 0xef, 0x53, 0xcb, ++ 0xdc, 0x26, 0x59, 0x27, 0x17, 0x47, 0xd5, 0x9a, 0x58, 0xdf, 0xe1, 0x44, ++ 0xb7, 0xcf, 0x39, 0x74, 0x72, 0x71, 0x54, 0xb0, 0x46, 0x46, 0xb8, 0xf4, ++ 0x49, 0x0b, 0x64, 0xaa, 0x29, 0x60, 0x37, 0x38, 0xe6, 0x4c, 0xd0, 0xc7, ++ 0x7f, 0x5e, 0x81, 0xba, 0x3e, 0xfe, 0x03, 0xf5, 0xba, 0xbf, 0x27, 0xfe, ++ 0xb3, 0x7b, 0xed, 0x5d, 0x75, 0x18, 0xff, 0x69, 0x4f, 0xf2, 0x35, 0x23, ++ 0x3e, 0xb2, 0x6c, 0xfe, 0xdd, 0xf8, 0xfd, 0xc2, 0xec, 0x1a, 0x99, 0xe9, ++ 0xe4, 0xc5, 0xd5, 0xec, 0xa6, 0x6a, 0x11, 0x3f, 0xfa, 0x70, 0xf5, 0xeb, ++ 0x9b, 0xe7, 0xc2, 0xba, 0x67, 0x3d, 0x1c, 0x59, 0x8d, 0x6f, 0xe7, 0x60, ++ 0x7c, 0x75, 0x00, 0xe6, 0x05, 0xf0, 0xf8, 0x6a, 0x75, 0xf3, 0x11, 0x8a, ++ 0xbb, 0x36, 0x0b, 0x7e, 0x1e, 0x2e, 0xf9, 0x0f, 0xe3, 0x77, 0xef, 0xaa, ++ 0xb9, 0xc9, 0x18, 0x67, 0x8d, 0x5c, 0xdb, 0x77, 0xbb, 0x09, 0xbe, 0x65, ++ 0x1f, 0x32, 0x82, 0x7f, 0x37, 0x7f, 0x8d, 0x8c, 0xf1, 0x08, 0x4d, 0x2e, ++ 0x7c, 0x80, 0x7f, 0x8f, 0x81, 0xfb, 0x8d, 0x12, 0xee, 0xab, 0x69, 0xfc, ++ 0x80, 0x72, 0x05, 0xed, 0x4f, 0x2d, 0xbf, 0x01, 0xe3, 0x5e, 0xce, 0xd4, ++ 0x4e, 0xb9, 0x8c, 0xf5, 0x64, 0x9d, 0x5e, 0x5d, 0x5b, 0x6e, 0x8a, 0x7b, ++ 0x5f, 0xed, 0x69, 0x87, 0xc3, 0xa0, 0xb7, 0x34, 0x39, 0xc8, 0x9a, 0xff, ++ 0xf6, 0xc2, 0x43, 0xda, 0xbd, 0x99, 0x5c, 0x2e, 0x9e, 0x76, 0xe8, 0xf4, ++ 0xfe, 0x63, 0xe5, 0xc7, 0xe9, 0x3c, 0x31, 0x13, 0xf7, 0xd0, 0xdd, 0x2f, ++ 0x7c, 0xc8, 0xa7, 0x56, 0x78, 0x7f, 0x7f, 0x5d, 0xb7, 0xce, 0x73, 0xec, ++ 0xc3, 0x2c, 0xe6, 0x20, 0xe6, 0x4f, 0x82, 0xdb, 0xeb, 0x71, 0xeb, 0xf2, ++ 0x61, 0xa5, 0x66, 0x29, 0xec, 0xc4, 0x3c, 0xcb, 0x4b, 0xe8, 0xb9, 0x00, ++ 0xfe, 0x2e, 0x99, 0xa8, 0x7c, 0xea, 0xdf, 0xfd, 0x13, 0x73, 0xd0, 0x8f, ++ 0x6f, 0x32, 0x79, 0xc1, 0x12, 0xc0, 0x3c, 0x09, 0xa2, 0x63, 0x6f, 0x1f, ++ 0x46, 0xe7, 0x1e, 0x1a, 0xc4, 0x3e, 0x6c, 0xf1, 0x7e, 0x87, 0x4f, 0x1d, ++ 0x81, 0xf7, 0xe6, 0x5b, 0x49, 0xfe, 0xb5, 0xef, 0xb5, 0x07, 0x91, 0xaf, ++ 0xdb, 0x9d, 0x26, 0x8a, 0x1f, 0xb7, 0xec, 0xb2, 0x10, 0x5c, 0x2f, 0xf6, ++ 0xb5, 0x0b, 0xbf, 0x3a, 0x64, 0xf0, 0xbf, 0xb5, 0xfd, 0x0d, 0x9b, 0xa5, ++ 0xed, 0xad, 0x22, 0xe8, 0xbf, 0xd1, 0xc6, 0xc7, 0xdd, 0xf8, 0x70, 0x7f, ++ 0xba, 0x4f, 0x23, 0xd1, 0x7e, 0x77, 0x51, 0x6d, 0x2e, 0xc5, 0xf3, 0xb4, ++ 0xf8, 0x62, 0x6e, 0xc4, 0x63, 0xe2, 0x49, 0x61, 0x7c, 0x7c, 0x25, 0xc2, ++ 0x68, 0x5d, 0xda, 0xfe, 0xf7, 0x3a, 0xcc, 0xbf, 0x18, 0x91, 0x38, 0xff, ++ 0xa2, 0x97, 0xd3, 0xac, 0xf9, 0x4b, 0x19, 0x4e, 0xa4, 0xc3, 0x99, 0x6d, ++ 0xaf, 0xe2, 0xdc, 0x62, 0xfd, 0xaf, 0x8c, 0x43, 0xc7, 0xf7, 0xe2, 0x38, ++ 0x19, 0xb5, 0x3c, 0x2c, 0xb0, 0xee, 0xd0, 0x52, 0x09, 0xd7, 0xb7, 0x6e, ++ 0x56, 0x7c, 0xff, 0x4b, 0xa3, 0x9f, 0x75, 0x22, 0xce, 0xa5, 0xcb, 0x73, ++ 0xc8, 0x73, 0xea, 0xf5, 0xca, 0xdc, 0xd4, 0xa4, 0x5c, 0x9d, 0xdc, 0xd4, ++ 0xfa, 0xfd, 0x52, 0xe4, 0x39, 0x8c, 0x6a, 0xb9, 0x7b, 0x27, 0xda, 0x77, ++ 0xc0, 0xd7, 0x69, 0x4e, 0x1d, 0x5f, 0x4f, 0x1a, 0xb2, 0xda, 0x16, 0x6f, ++ 0xbf, 0xdd, 0x5f, 0xfb, 0x10, 0xc5, 0x3f, 0x13, 0xd1, 0xbd, 0xdf, 0xc4, ++ 0xef, 0x5b, 0x8a, 0x7d, 0x3e, 0xde, 0x29, 0xec, 0x18, 0x25, 0xd2, 0x83, ++ 0xec, 0xc0, 0x3d, 0x5f, 0xd8, 0x3d, 0x71, 0xf2, 0x1f, 0xfc, 0xbb, 0x4c, ++ 0xf4, 0x77, 0x41, 0xb4, 0x78, 0x4c, 0xd7, 0xef, 0xff, 0x3b, 0xcd, 0xff, ++ 0x46, 0x67, 0xc7, 0xbe, 0x5e, 0x8f, 0x6b, 0xd9, 0xd7, 0x8b, 0x9d, 0x77, ++ 0xab, 0xca, 0x7a, 0xc5, 0xd3, 0x27, 0xb1, 0x79, 0x93, 0xda, 0xf7, 0xe2, ++ 0xf4, 0xbf, 0x4b, 0x7f, 0xef, 0x81, 0xdf, 0xcc, 0x02, 0xdb, 0x1d, 0x5d, ++ 0xfb, 0x69, 0xf6, 0xae, 0x5f, 0xe2, 0xf7, 0x4e, 0xb1, 0x8f, 0x18, 0xe9, ++ 0x55, 0x8d, 0x4e, 0x00, 0xee, 0x77, 0x20, 0xbe, 0x86, 0x1e, 0x9e, 0x37, ++ 0x1c, 0x43, 0xa9, 0xcc, 0x5a, 0x23, 0xa3, 0x1c, 0xb8, 0xd8, 0xd4, 0x92, ++ 0x8d, 0x71, 0xaa, 0x44, 0x7e, 0xa1, 0x36, 0x1f, 0xf8, 0xf5, 0x8b, 0x17, ++ 0x67, 0xf1, 0xe3, 0xbd, 0x4a, 0x71, 0xd6, 0x77, 0xbf, 0xc0, 0x83, 0x5f, ++ 0xe5, 0xf6, 0xa7, 0x54, 0x7c, 0xe0, 0x3b, 0x38, 0x2f, 0xff, 0x79, 0xb3, ++ 0xa4, 0x3f, 0x87, 0x31, 0xc7, 0x29, 0x19, 0xf8, 0x49, 0x8b, 0x83, 0x36, ++ 0x9f, 0x7f, 0x77, 0x38, 0xc9, 0x47, 0x35, 0x9c, 0x1d, 0x0f, 0x7e, 0xb1, ++ 0xfb, 0x96, 0x73, 0x30, 0x68, 0xc5, 0xf5, 0x1c, 0x87, 0x83, 0x80, 0x4b, ++ 0x5d, 0x31, 0x2b, 0xb1, 0x74, 0xa3, 0x38, 0x01, 0xdb, 0xe8, 0x41, 0xff, ++ 0x8f, 0xcb, 0x49, 0x4f, 0x2d, 0x23, 0xfe, 0xbe, 0x5e, 0xf2, 0xd1, 0xba, ++ 0x57, 0x38, 0xb9, 0x5d, 0xb3, 0x8e, 0xb5, 0x52, 0x5e, 0xe3, 0xc5, 0x43, ++ 0x3c, 0x0f, 0x79, 0xe8, 0x7d, 0x1e, 0xfa, 0xfb, 0x5c, 0xa0, 0x0f, 0x82, ++ 0x48, 0xb7, 0xa3, 0x58, 0x60, 0xa7, 0x49, 0x97, 0xd7, 0xa5, 0xd1, 0x43, ++ 0xdd, 0xb3, 0x60, 0x9f, 0x18, 0xe2, 0x55, 0x9c, 0x7f, 0x34, 0xbf, 0xb5, ++ 0x97, 0x88, 0xfb, 0xf4, 0xc4, 0x7b, 0x42, 0x74, 0xed, 0xba, 0xcf, 0x04, ++ 0x52, 0xd5, 0xc9, 0xfb, 0xac, 0x80, 0x95, 0x29, 0xba, 0xf8, 0x5a, 0x76, ++ 0x85, 0xdb, 0x50, 0xef, 0x55, 0x93, 0x69, 0x68, 0x9f, 0x19, 0x0c, 0x4b, ++ 0xc8, 0x57, 0x99, 0xb5, 0x1e, 0xc3, 0xf3, 0x4e, 0x39, 0xc5, 0xd7, 0xdb, ++ 0x2b, 0xc8, 0x36, 0xa0, 0xde, 0x5f, 0xc7, 0xda, 0x68, 0x7d, 0xbd, 0xc5, ++ 0x7c, 0xae, 0x97, 0x02, 0x44, 0x1f, 0x17, 0x0f, 0x9d, 0x48, 0xc5, 0x38, ++ 0x64, 0x48, 0xe0, 0x03, 0xd6, 0xfb, 0x24, 0xad, 0xb7, 0x36, 0x70, 0x51, ++ 0x4f, 0x1f, 0xda, 0x7a, 0xaf, 0xb6, 0xae, 0x0f, 0x97, 0xc1, 0x7c, 0x80, ++ 0xef, 0xff, 0x84, 0x7e, 0x39, 0x94, 0x77, 0x3d, 0x70, 0x4c, 0xea, 0x4e, ++ 0x70, 0x77, 0x53, 0xda, 0xef, 0x1c, 0xd1, 0xaf, 0xd7, 0xf7, 0x8f, 0x90, ++ 0xff, 0xd8, 0xab, 0xa6, 0x95, 0xec, 0xf7, 0xd9, 0xb5, 0x7b, 0x25, 0xd4, ++ 0x5b, 0x20, 0x37, 0xa8, 0xdf, 0xba, 0x65, 0x56, 0x2a, 0x7f, 0xbd, 0xcc, ++ 0x4d, 0x32, 0x54, 0xc3, 0x6f, 0x4f, 0x68, 0x87, 0x79, 0x47, 0xda, 0x7d, ++ 0xf0, 0x89, 0xf4, 0xd2, 0x2e, 0xe7, 0x35, 0xeb, 0xa5, 0x5d, 0xce, 0x38, ++ 0x7a, 0xc9, 0x64, 0x8d, 0xbc, 0x86, 0xfb, 0xdb, 0x95, 0xcd, 0xb2, 0x07, ++ 0xe9, 0x60, 0xe5, 0xf7, 0x53, 0x29, 0x7f, 0xe2, 0xa9, 0x06, 0x7e, 0x2e, ++ 0x71, 0x7f, 0x33, 0xcf, 0xe7, 0x7b, 0xaa, 0x8e, 0xe7, 0x6d, 0x6b, 0xdf, ++ 0x3d, 0xf7, 0x7c, 0x32, 0xed, 0xef, 0x9c, 0x13, 0xfb, 0x7c, 0xcc, 0x77, ++ 0x29, 0x63, 0x1a, 0xed, 0x7b, 0x5f, 0xca, 0xc0, 0xf3, 0x45, 0x1f, 0x3b, ++ 0x02, 0x6f, 0xe8, 0xe5, 0xe0, 0x53, 0xcd, 0x9f, 0xdb, 0x50, 0x5f, 0x0c, ++ 0xd6, 0xf2, 0x64, 0x63, 0xf4, 0x0b, 0x0a, 0x5e, 0x3c, 0xaf, 0x42, 0x67, ++ 0x1f, 0x25, 0xb4, 0x7b, 0x86, 0xad, 0x91, 0x71, 0x1d, 0xb7, 0x05, 0x86, ++ 0x63, 0x4a, 0x1b, 0xf0, 0xf7, 0x3b, 0x9c, 0x3e, 0xb9, 0x1e, 0xfa, 0xcd, ++ 0xb6, 0x12, 0x93, 0xfe, 0x9e, 0x8e, 0x8b, 0x4d, 0x7f, 0x9d, 0xbd, 0xcf, ++ 0xd3, 0xb9, 0x6f, 0xa4, 0xed, 0x2b, 0x69, 0xef, 0xb5, 0x7d, 0x27, 0x49, ++ 0x0a, 0x7c, 0xac, 0x97, 0xeb, 0xb1, 0xfb, 0x4a, 0xb1, 0xfb, 0x21, 0xb2, ++ 0xcb, 0x4a, 0x79, 0xd6, 0x5e, 0xd9, 0xee, 0x95, 0x8d, 0x7a, 0x95, 0xe8, ++ 0x6e, 0x65, 0x3f, 0xae, 0x37, 0x57, 0xee, 0xb5, 0x13, 0xdc, 0x56, 0xf6, ++ 0x73, 0xd0, 0xfe, 0x2d, 0xcc, 0xf7, 0x0c, 0xce, 0xb7, 0x05, 0xf4, 0x16, ++ 0x9e, 0xc3, 0xbb, 0x78, 0xd4, 0x41, 0xed, 0xb4, 0xf9, 0xc3, 0x7c, 0x87, ++ 0x1e, 0xd2, 0xcd, 0xb7, 0xda, 0x14, 0x99, 0xbd, 0x4f, 0x8a, 0x3b, 0xdf, ++ 0xcf, 0xf5, 0x70, 0xec, 0x3a, 0x5f, 0x63, 0x3e, 0xb2, 0x36, 0x3f, 0xd9, ++ 0xa9, 0xd0, 0xbc, 0xdb, 0x99, 0xdd, 0x8b, 0x78, 0x6b, 0x30, 0xf3, 0xfb, ++ 0xdb, 0x82, 0x6f, 0xda, 0x29, 0x1e, 0xda, 0xee, 0xbb, 0x64, 0xc3, 0x7b, ++ 0x83, 0xdb, 0xd9, 0x25, 0x1b, 0xc6, 0x69, 0x4f, 0x3b, 0x02, 0x92, 0x0b, ++ 0xbe, 0x23, 0xf7, 0x8a, 0xb8, 0xd0, 0x0f, 0xd9, 0xdf, 0x7c, 0x71, 0x20, ++ 0xd2, 0x7f, 0xa2, 0x7d, 0xbe, 0x41, 0xce, 0x12, 0x15, 0xdb, 0xc3, 0x3a, ++ 0xad, 0x58, 0x8e, 0x72, 0x07, 0x2e, 0x6e, 0x63, 0x9c, 0xcf, 0x02, 0x57, ++ 0xe8, 0x37, 0xc9, 0x59, 0xe2, 0x70, 0x8d, 0xfc, 0xbb, 0xd6, 0x9f, 0xee, ++ 0xba, 0x22, 0xbe, 0x8c, 0xeb, 0xaf, 0xc6, 0xbf, 0x83, 0xa2, 0xb3, 0xa3, ++ 0x24, 0x21, 0x6f, 0x63, 0xe9, 0x4d, 0x6a, 0xde, 0xfb, 0x15, 0xc6, 0xf5, ++ 0x81, 0xbf, 0x28, 0x5f, 0x34, 0xd8, 0x9b, 0x85, 0x56, 0x02, 0x9c, 0xea, ++ 0x86, 0x08, 0xba, 0x9b, 0xc1, 0xc4, 0xdf, 0x41, 0x32, 0xd2, 0xc3, 0xc7, ++ 0x0e, 0x7f, 0x3f, 0x5c, 0xaf, 0xc6, 0x97, 0x57, 0x80, 0xcf, 0x40, 0x9c, ++ 0xf7, 0x5b, 0x0e, 0xff, 0x60, 0x6c, 0x8f, 0xf3, 0xc0, 0xf3, 0x3c, 0x20, ++ 0x77, 0x86, 0xb8, 0xb8, 0x9e, 0xda, 0x89, 0x47, 0x96, 0x35, 0xfb, 0xa9, ++ 0x4f, 0x1e, 0x97, 0x63, 0x91, 0x14, 0x46, 0x79, 0x26, 0xb1, 0xfb, 0xb3, ++ 0x93, 0x9c, 0xd3, 0x46, 0x60, 0xbf, 0xdc, 0x01, 0x1e, 0x13, 0xde, 0xe3, ++ 0xfe, 0x77, 0xd0, 0xfb, 0xb8, 0x2b, 0xc3, 0x2f, 0x4c, 0x79, 0x2a, 0xda, ++ 0x79, 0xe2, 0x4a, 0xdc, 0x27, 0xc4, 0x73, 0x7c, 0x8d, 0xea, 0x19, 0xe3, ++ 0xdf, 0x4b, 0x32, 0xc2, 0xe1, 0xb4, 0xc3, 0xff, 0x6d, 0x1c, 0x37, 0x58, ++ 0xd2, 0x49, 0x57, 0x2b, 0x3d, 0x57, 0x84, 0xc7, 0x24, 0x84, 0xc3, 0x5b, ++ 0x8e, 0xc0, 0x14, 0x2c, 0x9d, 0x2a, 0xd0, 0x0b, 0x02, 0x65, 0xf4, 0x5c, ++ 0xfa, 0xfb, 0x55, 0x59, 0x36, 0xdf, 0x2a, 0xdc, 0xbf, 0xdc, 0xba, 0x9c, ++ 0xc3, 0xa1, 0xfd, 0x59, 0x0e, 0x87, 0xed, 0x2d, 0x26, 0xa2, 0xe3, 0x0d, ++ 0x6c, 0x10, 0xf1, 0xdf, 0x20, 0xd3, 0x85, 0xd9, 0x38, 0x3e, 0xc8, 0x97, ++ 0x99, 0x38, 0xce, 0x88, 0xd6, 0x7a, 0x13, 0xe6, 0xf3, 0xf5, 0x0b, 0x79, ++ 0x4c, 0x74, 0x8f, 0x53, 0x6b, 0x83, 0xc9, 0x74, 0x65, 0xba, 0x9d, 0x25, ++ 0xe8, 0x76, 0x8e, 0xc0, 0xc3, 0xfd, 0x88, 0x87, 0xc1, 0xdb, 0x78, 0x5c, ++ 0xe5, 0x0a, 0x74, 0x3b, 0x4f, 0xd0, 0xed, 0xb5, 0xc2, 0x7d, 0x89, 0xeb, ++ 0x8a, 0x7c, 0xdb, 0x85, 0xae, 0x6a, 0xf4, 0x74, 0x75, 0xad, 0xf9, 0x43, ++ 0x92, 0x38, 0x07, 0x1b, 0x3b, 0x1e, 0x63, 0x6d, 0x14, 0xbf, 0xdf, 0xfb, ++ 0x92, 0x85, 0xe4, 0x77, 0xd5, 0x0e, 0x7e, 0xee, 0xb7, 0x6a, 0xf7, 0x49, ++ 0x3a, 0x2f, 0x5a, 0xf5, 0xb2, 0x85, 0x88, 0xb2, 0xec, 0x65, 0x1b, 0x3f, ++ 0xbf, 0xd2, 0xc8, 0xdf, 0x9f, 0x2b, 0x8e, 0xbf, 0xbf, 0xfc, 0x6f, 0x2e, ++ 0xee, 0x5f, 0x55, 0x36, 0xdc, 0xe7, 0xd5, 0xeb, 0x6b, 0xcd, 0x0e, 0xf8, ++ 0xa9, 0xef, 0x82, 0xbb, 0xaf, 0xdc, 0xb9, 0x4f, 0x97, 0x36, 0x99, 0x9f, ++ 0x07, 0x59, 0x69, 0xd3, 0xf2, 0x41, 0xf9, 0x7e, 0x9d, 0x4b, 0xd0, 0x59, ++ 0x5a, 0x2f, 0xbf, 0x0f, 0xf5, 0x4e, 0xda, 0x78, 0x1e, 0x17, 0x72, 0x39, ++ 0xe6, 0xd3, 0x7e, 0x5d, 0xd7, 0x73, 0x1f, 0x9c, 0x6f, 0xd3, 0x45, 0x3f, ++ 0xb7, 0xdb, 0x43, 0xf6, 0x40, 0xec, 0x39, 0x90, 0x74, 0xbc, 0x17, 0x9c, ++ 0xef, 0xbb, 0x12, 0xbd, 0xc8, 0x26, 0xbb, 0x17, 0xf7, 0x2d, 0xd3, 0x26, ++ 0xc6, 0xb4, 0x73, 0x4c, 0xa4, 0xfc, 0xb9, 0xf4, 0x98, 0xfd, 0xbc, 0x90, ++ 0x4b, 0xd8, 0xc1, 0x66, 0x96, 0x49, 0x72, 0xd4, 0x16, 0xff, 0xbc, 0x97, ++ 0x92, 0xac, 0xd9, 0x73, 0x76, 0x93, 0x5e, 0x9e, 0xa0, 0x9c, 0xa7, 0xfb, ++ 0x7a, 0x9c, 0x56, 0x5a, 0xf7, 0xd2, 0x74, 0x96, 0x56, 0x8e, 0xf1, 0x01, ++ 0xa7, 0x42, 0xe7, 0x3d, 0x63, 0xc7, 0xd1, 0xca, 0x14, 0x9f, 0xc9, 0x70, ++ 0x9e, 0x28, 0x6d, 0xa2, 0xdd, 0x70, 0x5f, 0x46, 0xba, 0x3f, 0xd5, 0x50, ++ 0xef, 0x3e, 0xb3, 0x87, 0xa1, 0x7d, 0x56, 0x20, 0xd7, 0xf0, 0x3e, 0xbb, ++ 0x62, 0x90, 0xe1, 0x7d, 0xaf, 0x9a, 0x02, 0x43, 0xbd, 0x4f, 0xed, 0x0d, ++ 0x86, 0xf6, 0x39, 0x40, 0x70, 0xfa, 0x7a, 0xde, 0x9a, 0x9b, 0x0d, 0xed, ++ 0xfb, 0xd5, 0x4f, 0x33, 0xd4, 0xaf, 0x5b, 0x77, 0xa7, 0xa1, 0xfd, 0xc0, ++ 0xd0, 0xdd, 0x86, 0xf7, 0x83, 0xb7, 0x2c, 0x32, 0xbc, 0x1f, 0xd2, 0xb0, ++ 0xd4, 0x50, 0xbf, 0xbe, 0xe9, 0x21, 0x43, 0x7b, 0x39, 0x81, 0x7d, 0xad, ++ 0xc1, 0x59, 0xd6, 0xec, 0x6b, 0xe7, 0x88, 0x00, 0x9d, 0x1f, 0x73, 0x5a, ++ 0x25, 0xbd, 0x1d, 0x72, 0xd8, 0xc5, 0xed, 0xf0, 0x62, 0x97, 0x95, 0xe0, ++ 0xbf, 0x5a, 0xe8, 0xe3, 0xd5, 0xe2, 0xbc, 0xd9, 0x6a, 0xa1, 0x8f, 0x5b, ++ 0xd2, 0x0b, 0xaf, 0xb8, 0xbf, 0xf2, 0x8f, 0xfa, 0x63, 0x67, 0x5d, 0xc6, ++ 0xb8, 0x57, 0x89, 0x88, 0x7b, 0x9d, 0xdb, 0x67, 0x36, 0x21, 0xdd, 0x57, ++ 0xed, 0x07, 0xba, 0xa0, 0xbf, 0xcb, 0x15, 0x38, 0xeb, 0xe2, 0xf6, 0xd7, ++ 0x94, 0xb9, 0xb4, 0x7a, 0x7e, 0x8e, 0xb2, 0x35, 0x41, 0x3e, 0xc7, 0x97, ++ 0x2e, 0xcd, 0xcf, 0x03, 0xbf, 0x24, 0x8e, 0x7f, 0x67, 0x4a, 0xf6, 0xc4, ++ 0xf5, 0xaf, 0x40, 0xae, 0x5d, 0x72, 0xe9, 0xfd, 0x20, 0x56, 0x23, 0xa3, ++ 0x1c, 0xd0, 0xe4, 0x52, 0x75, 0x12, 0x23, 0xbb, 0xad, 0xdd, 0x15, 0xed, ++ 0x8f, 0x7c, 0x04, 0x72, 0x4a, 0x4a, 0x4e, 0x47, 0xf9, 0xf4, 0x58, 0xcd, ++ 0x3e, 0x94, 0x4f, 0xcd, 0x16, 0x92, 0x4f, 0xaf, 0x0f, 0x38, 0x41, 0x7e, ++ 0xf5, 0xcd, 0xb5, 0xf3, 0x09, 0x2e, 0x87, 0x5d, 0x3c, 0x5e, 0x2b, 0x9b, ++ 0xbd, 0x1e, 0x7e, 0xce, 0xd4, 0xa8, 0x77, 0x0f, 0xa9, 0xad, 0x94, 0xa7, ++ 0x7d, 0x68, 0xa4, 0xcc, 0xf0, 0x7e, 0x94, 0x8b, 0xde, 0x51, 0x74, 0x9e, ++ 0x39, 0x11, 0x3c, 0xdf, 0x44, 0xbf, 0x19, 0x64, 0xd7, 0x7e, 0x94, 0x0d, ++ 0x23, 0xaf, 0xee, 0x77, 0x1e, 0x5a, 0x56, 0x41, 0xf9, 0xcc, 0x89, 0xc6, ++ 0x3b, 0x34, 0xcc, 0x46, 0x71, 0xcf, 0xf2, 0x98, 0x7b, 0x70, 0x07, 0x09, ++ 0x3a, 0x2a, 0x4b, 0x16, 0xf0, 0xb4, 0x70, 0xff, 0xf1, 0xec, 0x0b, 0x4e, ++ 0xca, 0x2f, 0x3e, 0x5b, 0xf0, 0x0e, 0xfd, 0xfd, 0xa2, 0xb3, 0x8d, 0x7f, ++ 0x18, 0x1e, 0xa4, 0xbf, 0xd7, 0xd5, 0x7a, 0x3f, 0xee, 0xbf, 0x07, 0xff, ++ 0xea, 0xa0, 0xb8, 0x4c, 0xf9, 0xb0, 0x77, 0x86, 0x2f, 0x27, 0xbb, 0xd6, ++ 0xc7, 0xfd, 0x37, 0xf1, 0x77, 0xc1, 0xc6, 0xbd, 0x78, 0xd8, 0x85, 0x7e, ++ 0x77, 0xf9, 0xf6, 0xfd, 0xdd, 0x82, 0x3a, 0xfc, 0xc5, 0xfa, 0x6d, 0x65, ++ 0x62, 0x7d, 0x4c, 0x69, 0xeb, 0x4f, 0x79, 0xa1, 0xaf, 0x9c, 0xa2, 0xbf, ++ 0x1b, 0x53, 0xfe, 0xd2, 0x81, 0x6e, 0x3c, 0x2e, 0x64, 0xcc, 0x5b, 0x89, ++ 0xf5, 0xd7, 0xcb, 0x6b, 0xab, 0x08, 0x6f, 0x5a, 0xbd, 0x32, 0x6a, 0x35, ++ 0xe4, 0xaf, 0x54, 0x2a, 0xfc, 0xdc, 0x6f, 0x65, 0xd4, 0x41, 0xf9, 0x2b, ++ 0xae, 0x64, 0xa3, 0x3f, 0x9f, 0x10, 0x5e, 0xd7, 0x08, 0xcf, 0xd8, 0xe7, ++ 0x1a, 0x3c, 0x0f, 0x0d, 0x3b, 0xc5, 0xcf, 0xaf, 0xdb, 0xe2, 0xd3, 0x6f, ++ 0x4d, 0xb2, 0x31, 0x3e, 0x1c, 0x7b, 0xae, 0x20, 0x51, 0xfe, 0xfa, 0xed, ++ 0xa2, 0xdf, 0x45, 0xef, 0x18, 0x3a, 0x07, 0x5f, 0x6e, 0x0e, 0xf7, 0xbd, ++ 0x96, 0xf8, 0x82, 0x06, 0xa7, 0xd7, 0x2f, 0x2f, 0xa0, 0xf3, 0x0a, 0x2f, ++ 0x24, 0x38, 0xaf, 0xe0, 0x4f, 0xe6, 0x71, 0xf7, 0x17, 0x06, 0xdc, 0x4b, ++ 0x79, 0xc7, 0x63, 0xac, 0x35, 0xa5, 0xa8, 0xbf, 0xc7, 0x88, 0xf8, 0x65, ++ 0x9c, 0xbc, 0xe3, 0x7b, 0x92, 0x47, 0x62, 0x3e, 0xf3, 0x3f, 0x27, 0xef, ++ 0xb8, 0x52, 0xc3, 0x8f, 0xc8, 0xeb, 0x1d, 0x83, 0x7c, 0x9c, 0xce, 0xba, ++ 0xe4, 0x1d, 0x5f, 0xed, 0x3c, 0xc8, 0x24, 0xbc, 0x8f, 0x3b, 0x0e, 0x7f, ++ 0xdd, 0xd4, 0x01, 0xbf, 0xf7, 0x67, 0xe0, 0xbd, 0x4e, 0xf7, 0x3f, 0xa1, ++ 0x52, 0x1e, 0xd0, 0x02, 0x98, 0x43, 0x10, 0xe3, 0x26, 0x1b, 0x54, 0x8a, ++ 0x9f, 0x1e, 0xbe, 0x6c, 0x61, 0x18, 0xcf, 0x3e, 0xb9, 0x5e, 0x7d, 0x1a, ++ 0xf3, 0x55, 0x2a, 0x9e, 0xd8, 0xdf, 0xf3, 0x31, 0x8c, 0x5f, 0x0f, 0xb3, ++ 0x50, 0x1e, 0xdd, 0x82, 0x0d, 0xfc, 0x3e, 0x10, 0x36, 0xcc, 0x16, 0xc2, ++ 0x3c, 0x8d, 0x8a, 0x0d, 0x0f, 0x66, 0x60, 0x7e, 0xe4, 0x67, 0xc0, 0xb7, ++ 0x4b, 0x60, 0x5e, 0x0b, 0x9e, 0x48, 0xa7, 0x3c, 0x9e, 0xc3, 0x2d, 0x8f, ++ 0x64, 0x20, 0x9e, 0x4e, 0x09, 0x7e, 0xae, 0xf8, 0xfa, 0x87, 0xb7, 0x21, ++ 0xfc, 0xb7, 0x9b, 0xdd, 0x83, 0x87, 0x41, 0xb9, 0x64, 0x9b, 0x64, 0xc8, ++ 0x03, 0x5f, 0xb4, 0xc9, 0x66, 0xa8, 0x6b, 0x79, 0x40, 0x1a, 0xfe, 0x98, ++ 0xd4, 0x99, 0x1f, 0xee, 0x01, 0x39, 0xfa, 0x78, 0xb2, 0xf1, 0x7c, 0xcb, ++ 0xf0, 0xce, 0x7d, 0x85, 0xc7, 0x93, 0x85, 0x3c, 0x9d, 0x0e, 0xf3, 0xad, ++ 0x1a, 0x79, 0xd1, 0x8c, 0x78, 0xdc, 0xff, 0xaa, 0x9d, 0xe6, 0xbd, 0xc7, ++ 0xc1, 0xef, 0x57, 0x0b, 0x0f, 0xfb, 0xf2, 0x8d, 0xeb, 0xa1, 0x5e, 0xfa, ++ 0xb5, 0xa2, 0xdd, 0xab, 0x63, 0xc8, 0x2b, 0x62, 0xb8, 0x09, 0x81, 0xf7, ++ 0x9c, 0x88, 0xfc, 0xbf, 0xd2, 0x97, 0x94, 0x8e, 0xfc, 0x7c, 0xe1, 0x37, ++ 0x38, 0xc6, 0xeb, 0xf2, 0xa0, 0xc3, 0xcb, 0x6a, 0x88, 0x6f, 0x4a, 0x7f, ++ 0xc5, 0xfd, 0xe2, 0x52, 0x1b, 0xcf, 0xd7, 0x4d, 0x98, 0x6f, 0xc4, 0xba, ++ 0xe4, 0x33, 0x0f, 0x40, 0x79, 0xde, 0x25, 0xcf, 0xa8, 0xf3, 0x3c, 0x84, ++ 0xc1, 0x2e, 0xd1, 0xe8, 0xa6, 0x31, 0x59, 0xe4, 0x1b, 0x09, 0xbe, 0xde, ++ 0xff, 0x2a, 0xcf, 0x2b, 0x9a, 0x7f, 0x48, 0xd8, 0x93, 0x57, 0x91, 0x9b, ++ 0x6f, 0xe2, 0xbc, 0x15, 0xc4, 0xd7, 0xeb, 0xb3, 0x70, 0xdf, 0xf1, 0xb0, ++ 0x80, 0xc6, 0xe1, 0xcb, 0x27, 0x57, 0xd1, 0x3d, 0x44, 0xa3, 0x25, 0x8c, ++ 0xb0, 0xb1, 0x93, 0x97, 0xe3, 0xf3, 0x8d, 0x59, 0x93, 0x9f, 0x98, 0xbf, ++ 0x3f, 0xa0, 0x13, 0x3f, 0x93, 0xbd, 0x0b, 0x3b, 0xea, 0xc8, 0x96, 0x53, ++ 0x47, 0xdf, 0x67, 0x38, 0x57, 0x70, 0xed, 0xf2, 0xe6, 0xca, 0xf2, 0xa4, ++ 0x36, 0x99, 0x9f, 0xbf, 0x8b, 0x95, 0xef, 0xb1, 0x74, 0xff, 0x7f, 0x4a, ++ 0xbe, 0x97, 0x0f, 0x3b, 0xd0, 0x1b, 0xcf, 0xc9, 0x43, 0xf9, 0x9f, 0x74, ++ 0x5e, 0x7e, 0x3b, 0x97, 0x8f, 0xb1, 0x7c, 0x1e, 0x2b, 0xcf, 0x6f, 0x8a, ++ 0x91, 0x83, 0x9d, 0x72, 0xdc, 0x64, 0x90, 0xe3, 0x37, 0x09, 0x7d, 0xde, ++ 0x29, 0xcf, 0xcd, 0x24, 0xcf, 0xc1, 0x3c, 0xe3, 0xf7, 0xb7, 0x14, 0x2a, ++ 0xa1, 0x95, 0x12, 0xf9, 0x3d, 0x5f, 0xa0, 0xbe, 0xce, 0x77, 0x78, 0xd2, ++ 0x8a, 0xa1, 0xcb, 0x2a, 0x77, 0x6e, 0x52, 0xe0, 0xca, 0x7e, 0xe8, 0x25, ++ 0xe4, 0x93, 0x76, 0x5b, 0xe0, 0x6b, 0x2c, 0xfb, 0xfc, 0x66, 0x10, 0xfd, ++ 0x5d, 0xcf, 0xc1, 0xdb, 0xea, 0x4d, 0xc8, 0xbf, 0xed, 0x09, 0xec, 0x8f, ++ 0xff, 0x0d, 0x39, 0xa0, 0xfc, 0x77, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xcd, 0x7d, ++ 0x09, 0x7c, 0x94, 0xd5, 0xb5, 0xf8, 0xfd, 0xe6, 0x9b, 0x2d, 0xc9, 0x4c, ++ 0x32, 0x99, 0xec, 0x2b, 0x13, 0x76, 0x15, 0x70, 0x80, 0x10, 0x10, 0xa2, ++ 0x7e, 0x49, 0x00, 0xa3, 0x10, 0x1c, 0x50, 0x01, 0x35, 0xe8, 0x24, 0x90, ++ 0x84, 0x2d, 0x24, 0x20, 0x5a, 0xfa, 0x6a, 0x5f, 0x26, 0x24, 0x60, 0xc4, ++ 0x68, 0x43, 0xb5, 0x8a, 0x8a, 0x76, 0x50, 0xf0, 0x51, 0x45, 0x0d, 0x82, ++ 0x35, 0xb6, 0x51, 0x27, 0x80, 0x14, 0xac, 0x4b, 0xac, 0xb6, 0xa5, 0xad, ++ 0x62, 0x10, 0x44, 0x36, 0x25, 0x82, 0xfa, 0xa7, 0x7d, 0x2a, 0xef, 0x9c, ++ 0x73, 0xef, 0xcd, 0xcc, 0x37, 0x99, 0xb0, 0xf4, 0xf9, 0x7e, 0xbf, 0x7f, ++ 0xfa, 0xb3, 0x97, 0xfb, 0xdd, 0xfd, 0xec, 0xe7, 0xdc, 0x65, 0x66, 0x45, ++ 0x1b, 0x18, 0x1b, 0xc3, 0xd8, 0xb3, 0x26, 0x36, 0xbb, 0xd5, 0x06, 0xa9, ++ 0x02, 0xe9, 0x30, 0xc6, 0xce, 0xe2, 0xdf, 0xd5, 0x8c, 0xc5, 0x38, 0x0a, ++ 0x66, 0x45, 0x27, 0x31, 0xb6, 0xdf, 0x0a, 0x29, 0xd4, 0x63, 0xcc, 0xea, ++ 0x38, 0x34, 0x94, 0xb1, 0x5c, 0x66, 0x60, 0x71, 0x2a, 0x63, 0x25, 0x8a, ++ 0x37, 0xc6, 0x01, 0xe5, 0xd5, 0xd6, 0xae, 0x07, 0xca, 0xa0, 0x74, 0xc9, ++ 0x6f, 0xbe, 0x35, 0x43, 0x11, 0xdb, 0x10, 0xed, 0x4d, 0x35, 0x26, 0x32, ++ 0xe6, 0x4b, 0x37, 0xbb, 0x37, 0xe5, 0x04, 0xfb, 0x93, 0x69, 0x92, 0x03, ++ 0x2a, 0x41, 0xbb, 0xfe, 0x2b, 0x0a, 0xd9, 0xc1, 0x04, 0xc6, 0x2c, 0x56, ++ 0xe6, 0x8b, 0x1a, 0xc5, 0x98, 0x62, 0x64, 0x3e, 0xd3, 0x28, 0x1c, 0xc7, ++ 0xb5, 0xd2, 0x00, 0xed, 0x8d, 0x4d, 0x8c, 0xad, 0x81, 0xf6, 0xb1, 0x76, ++ 0x46, 0xf3, 0x64, 0x43, 0x53, 0x0d, 0x2c, 0x99, 0xb1, 0x3b, 0xac, 0x8c, ++ 0xfe, 0x7c, 0x85, 0x0c, 0x27, 0xc3, 0x7c, 0x3b, 0xa2, 0xfd, 0x0d, 0x0a, ++ 0x63, 0xdf, 0x33, 0x2d, 0x03, 0xe7, 0xf3, 0x03, 0xd3, 0x32, 0x1d, 0x50, ++ 0xff, 0x23, 0xa6, 0x65, 0x61, 0x5e, 0x8e, 0xdb, 0x28, 0xd6, 0x69, 0x34, ++ 0x30, 0xef, 0x56, 0x5b, 0xef, 0x79, 0xcd, 0x74, 0x28, 0x7c, 0x1c, 0xe6, ++ 0x19, 0xec, 0x81, 0x31, 0x2b, 0x0a, 0x99, 0x37, 0x14, 0x1e, 0x32, 0x2d, ++ 0x70, 0x18, 0xa9, 0x5e, 0xc1, 0xc3, 0x37, 0x67, 0x77, 0x41, 0xf9, 0x67, ++ 0x1d, 0xb7, 0x64, 0x33, 0xe8, 0x6f, 0xd7, 0xaf, 0xc6, 0xc6, 0x75, 0x45, ++ 0xa8, 0x2f, 0xd3, 0xb5, 0x75, 0xb5, 0xee, 0x89, 0xd0, 0xf4, 0xfe, 0x3a, ++ 0x2f, 0xa5, 0xf1, 0x8c, 0x69, 0x38, 0x9f, 0x5f, 0xd4, 0xcd, 0xa7, 0xbc, ++ 0x13, 0xf2, 0x5b, 0xa1, 0x7d, 0x85, 0xd9, 0x33, 0x38, 0x3e, 0xa4, 0x9f, ++ 0x81, 0x8e, 0x78, 0x82, 0x97, 0xa3, 0xe0, 0x4f, 0x9e, 0x01, 0x00, 0x97, ++ 0x43, 0xcd, 0xaa, 0x43, 0x71, 0x41, 0xca, 0x0c, 0xc5, 0xd8, 0xfe, 0xa0, ++ 0x3f, 0xae, 0x78, 0xbb, 0x68, 0x97, 0xa8, 0x6b, 0xc7, 0xe7, 0xa9, 0x32, ++ 0x8d, 0xb1, 0x01, 0xb0, 0x6e, 0x9b, 0xf1, 0x5f, 0x5d, 0x02, 0x76, 0x67, ++ 0x19, 0xae, 0x97, 0x51, 0xbf, 0x7d, 0xad, 0x73, 0xa6, 0x83, 0xd3, 0x87, ++ 0x99, 0xb9, 0xad, 0xd8, 0xde, 0xbc, 0xe3, 0x3a, 0x2b, 0xe2, 0x57, 0x55, ++ 0x34, 0x07, 0xe6, 0x25, 0x3d, 0x5c, 0x01, 0x23, 0x20, 0x3d, 0xdc, 0x83, ++ 0x9f, 0xae, 0x60, 0x6c, 0xb4, 0xe2, 0xf5, 0x38, 0xa8, 0x9d, 0x96, 0x20, ++ 0xcb, 0xcf, 0xe6, 0xe0, 0xf8, 0xc5, 0x94, 0x97, 0xe3, 0xb3, 0x4c, 0x58, ++ 0x71, 0x5a, 0xdf, 0xf0, 0x62, 0x8a, 0x76, 0x13, 0xe2, 0xef, 0x08, 0xd3, ++ 0x66, 0x62, 0x7f, 0xad, 0x66, 0x76, 0x99, 0x03, 0xd6, 0xdb, 0x1a, 0xcd, ++ 0xe6, 0x47, 0x9a, 0x6f, 0xa9, 0xc0, 0x5f, 0xba, 0x43, 0xd0, 0x0b, 0xb3, ++ 0x39, 0x0e, 0x5f, 0x26, 0xc6, 0x83, 0xf9, 0x9d, 0x8c, 0xd1, 0x6e, 0xc7, ++ 0x7e, 0xd2, 0xa2, 0x3c, 0x65, 0xd8, 0x6f, 0x5e, 0x46, 0xad, 0x6a, 0x82, ++ 0x26, 0xb3, 0xa2, 0x1d, 0xa2, 0xbe, 0xa6, 0x78, 0x86, 0x53, 0x79, 0x25, ++ 0xd6, 0x63, 0xa9, 0x9a, 0x52, 0x02, 0xf0, 0xce, 0xfb, 0x04, 0xe8, 0x10, ++ 0xb2, 0xdb, 0xf6, 0x14, 0x2a, 0x2e, 0x18, 0x3f, 0xb1, 0x73, 0xa2, 0xe2, ++ 0x82, 0xf1, 0x13, 0x05, 0xfe, 0x7a, 0xcd, 0x5f, 0xc0, 0xed, 0x25, 0xc6, ++ 0x8a, 0x23, 0xcd, 0x73, 0x56, 0x34, 0x9f, 0xe7, 0x52, 0x01, 0xff, 0xfd, ++ 0x56, 0x0f, 0xf1, 0xd7, 0xea, 0x1c, 0x6f, 0x6a, 0x2d, 0xf4, 0xe7, 0x6a, ++ 0x65, 0x9a, 0x1f, 0xda, 0xb5, 0xe2, 0x94, 0x42, 0xe0, 0xf3, 0x96, 0xc3, ++ 0x4c, 0xf5, 0x37, 0x44, 0x77, 0xf9, 0x54, 0xa4, 0xfb, 0x5b, 0x98, 0x7b, ++ 0x13, 0xd0, 0x41, 0x4a, 0xbe, 0x4f, 0x31, 0x42, 0x9a, 0x31, 0xb5, 0xa5, ++ 0x00, 0x30, 0xce, 0x1a, 0x1c, 0x4e, 0xea, 0xdf, 0x59, 0xec, 0x4d, 0x55, ++ 0xa0, 0x5e, 0x7a, 0xaa, 0xd9, 0xad, 0x2a, 0x17, 0xce, 0x6f, 0xc3, 0x5a, ++ 0x35, 0xd5, 0x0b, 0xe3, 0xe7, 0x7a, 0x0d, 0x34, 0x8f, 0x75, 0x9d, 0xbe, ++ 0xa8, 0xc1, 0x30, 0xaf, 0xe4, 0x4e, 0x6f, 0x81, 0x19, 0xd2, 0xa2, 0xf8, ++ 0x64, 0xea, 0x3f, 0x85, 0xd5, 0xd6, 0x23, 0x3e, 0xa0, 0x3d, 0x43, 0xbe, ++ 0x1c, 0xed, 0xe0, 0xff, 0xcc, 0xf5, 0x16, 0xaa, 0xae, 0x10, 0xb8, 0xe4, ++ 0xcd, 0xab, 0x6d, 0x30, 0xc3, 0xf7, 0xef, 0xa3, 0xbd, 0x6b, 0x43, 0xf9, ++ 0x31, 0x63, 0xb1, 0x8f, 0xc6, 0x39, 0xaa, 0x78, 0xfb, 0x39, 0x81, 0x9e, ++ 0x8e, 0xbe, 0x19, 0x3d, 0xdb, 0x8f, 0xfd, 0x05, 0x9c, 0x44, 0x47, 0xb2, ++ 0xde, 0x53, 0x88, 0xd7, 0x24, 0xa4, 0x87, 0xc2, 0x74, 0x96, 0x0a, 0xfd, ++ 0x6f, 0x34, 0xd1, 0xbc, 0x72, 0x37, 0xfe, 0xea, 0x36, 0xe4, 0xff, 0xdc, ++ 0x8d, 0xd7, 0x18, 0x95, 0x10, 0x39, 0xf3, 0x8a, 0xc3, 0x44, 0xf5, 0x8f, ++ 0xbe, 0xb9, 0xb0, 0x1f, 0xae, 0xdf, 0xf7, 0x37, 0x0b, 0x1b, 0x14, 0x41, ++ 0x0e, 0xbd, 0x28, 0xe8, 0xe5, 0x61, 0x81, 0x87, 0x6d, 0xe6, 0xc8, 0x74, ++ 0xf5, 0x9c, 0x1c, 0x5f, 0xd0, 0xfb, 0x04, 0xa6, 0x48, 0xf9, 0xf7, 0x9c, ++ 0x90, 0x7f, 0xb1, 0x03, 0x60, 0x7d, 0x4b, 0xaa, 0x4f, 0x91, 0xfc, 0x6b, ++ 0x76, 0xb8, 0xa8, 0xfe, 0xe3, 0xc6, 0xd6, 0xdd, 0xe9, 0x00, 0xd7, 0xc7, ++ 0xe7, 0x31, 0xb7, 0x0f, 0x3e, 0x2d, 0xdc, 0xbc, 0x41, 0xc1, 0xf5, 0x6e, ++ 0x33, 0xb7, 0x5e, 0xbb, 0x05, 0xe7, 0xb5, 0xc4, 0xc0, 0x10, 0x7f, 0xbb, ++ 0x76, 0xff, 0x6e, 0x77, 0x3a, 0xe4, 0xe7, 0xcf, 0x73, 0x8d, 0xb4, 0xb8, ++ 0x42, 0xda, 0xbf, 0xfd, 0xec, 0x6a, 0xfc, 0xfe, 0xf8, 0x7c, 0x36, 0x12, ++ 0xe1, 0x9a, 0xe6, 0x5f, 0xab, 0x18, 0x00, 0x3e, 0xdf, 0x46, 0xb5, 0xd0, ++ 0xba, 0xbf, 0xdd, 0x64, 0x61, 0xf5, 0x30, 0xb5, 0xc7, 0x37, 0x3e, 0x92, ++ 0x6c, 0xc7, 0x7a, 0x5e, 0x83, 0x03, 0xeb, 0xf5, 0xe2, 0x23, 0x40, 0xb3, ++ 0x21, 0x15, 0xd3, 0x80, 0xc9, 0x30, 0x8e, 0xe3, 0x11, 0xe5, 0x95, 0xc4, ++ 0x9f, 0x84, 0x3b, 0xae, 0x1f, 0xe5, 0xe2, 0xae, 0x4d, 0xaf, 0xd0, 0xbc, ++ 0xe5, 0x7c, 0x80, 0x50, 0xcc, 0x08, 0xf7, 0xa2, 0x78, 0x17, 0xc1, 0x6b, ++ 0xe1, 0xe6, 0xad, 0xd7, 0x22, 0xf1, 0xa7, 0x2f, 0x76, 0x2a, 0x6a, 0x4e, ++ 0x70, 0x5e, 0xe7, 0x93, 0xfb, 0x1f, 0x0a, 0xbe, 0xb8, 0x50, 0x3a, 0x7c, ++ 0x33, 0x9e, 0xf3, 0x31, 0xc8, 0x79, 0x0d, 0xc7, 0xf3, 0xe5, 0x19, 0x49, ++ 0xce, 0x7f, 0x62, 0xf3, 0xfe, 0x1d, 0xe1, 0x3e, 0xcc, 0xe6, 0x4a, 0x28, ++ 0x80, 0x29, 0x35, 0x3a, 0xfa, 0xc7, 0x78, 0x61, 0xfc, 0x7e, 0x03, 0xd8, ++ 0xed, 0x9e, 0x08, 0xfc, 0x78, 0xa9, 0xbd, 0x70, 0x3f, 0xd6, 0x3f, 0x19, ++ 0xe5, 0x3d, 0x80, 0x7c, 0xdd, 0xef, 0xb9, 0x4b, 0x27, 0xb2, 0x58, 0xc6, ++ 0x2e, 0xdb, 0xd2, 0x62, 0x40, 0x7c, 0x9c, 0x54, 0xb8, 0x5e, 0xe8, 0xcd, ++ 0xa7, 0x42, 0x3f, 0x0a, 0xbd, 0x28, 0xf5, 0xa4, 0x2c, 0x3f, 0x29, 0xe8, ++ 0xe2, 0x0e, 0xa1, 0x27, 0x23, 0xe8, 0xc7, 0x93, 0x91, 0xf4, 0xa3, 0x8b, ++ 0xb9, 0xee, 0x1b, 0x06, 0xf8, 0x62, 0x6f, 0x1b, 0x88, 0x7f, 0xc3, 0xc7, ++ 0x5d, 0x2a, 0xe8, 0x72, 0x82, 0xe6, 0x2d, 0x42, 0x7e, 0x9e, 0x1d, 0xe3, ++ 0x3d, 0x83, 0xf3, 0xbe, 0x62, 0x9c, 0x7f, 0xa7, 0x0a, 0xf5, 0xc7, 0x16, ++ 0xfb, 0x76, 0x22, 0xbf, 0xe7, 0x2a, 0xb5, 0x3b, 0xed, 0x00, 0x17, 0x76, ++ 0x2d, 0x97, 0x03, 0x09, 0x5d, 0xac, 0x03, 0x96, 0xc5, 0xe2, 0xf7, 0x75, ++ 0x69, 0xb1, 0x90, 0x9f, 0x8b, 0x72, 0x00, 0xc6, 0x1f, 0x7f, 0x44, 0xeb, ++ 0xc0, 0xf1, 0xe2, 0x3c, 0x4c, 0xc1, 0xf6, 0xcf, 0x22, 0x9d, 0xc3, 0x3a, ++ 0x5a, 0x9c, 0xec, 0xf6, 0xe9, 0x11, 0xe8, 0xfd, 0x36, 0xb1, 0x2e, 0xc3, ++ 0x43, 0xdd, 0x66, 0xd4, 0x67, 0x89, 0xed, 0x0a, 0xf1, 0x5b, 0x6f, 0xf8, ++ 0x70, 0x79, 0x04, 0xf2, 0x32, 0x26, 0x1e, 0xe6, 0x97, 0xd7, 0x0f, 0xe4, ++ 0x69, 0x4e, 0x6f, 0x79, 0x1a, 0x01, 0x7f, 0xce, 0x78, 0x68, 0x77, 0xc9, ++ 0x96, 0xc0, 0x0e, 0xac, 0x35, 0x2a, 0x7e, 0x60, 0x0c, 0x34, 0x3b, 0x17, ++ 0xfe, 0x92, 0xe3, 0x09, 0x7f, 0x5a, 0x0a, 0x8e, 0x23, 0xf1, 0x75, 0xe9, ++ 0x59, 0xf5, 0x76, 0xcf, 0xb0, 0xde, 0xf8, 0xca, 0x8e, 0xe7, 0xf3, 0xbf, ++ 0xd3, 0xae, 0x65, 0x61, 0xbb, 0xcf, 0x84, 0x3e, 0xe8, 0x0b, 0x8f, 0xc3, ++ 0xe3, 0x39, 0xfe, 0x8a, 0xe2, 0xb9, 0x9d, 0xf3, 0xac, 0x5d, 0xd4, 0x8b, ++ 0xd2, 0xd7, 0x2b, 0x8b, 0xe7, 0x78, 0xa9, 0x88, 0xd7, 0xcb, 0x83, 0x10, ++ 0x7c, 0x0f, 0x8f, 0x8f, 0x80, 0x6f, 0x29, 0xc7, 0xb7, 0xed, 0x79, 0x49, ++ 0x45, 0xbc, 0xe5, 0x4d, 0x6c, 0x69, 0x40, 0x3c, 0x00, 0x5e, 0x47, 0xe3, ++ 0x7a, 0xc6, 0xe7, 0xd7, 0x36, 0xe0, 0xf7, 0x84, 0xa9, 0x5c, 0x1e, 0x86, ++ 0xe3, 0x55, 0xca, 0xc3, 0x70, 0xfc, 0x86, 0xe3, 0x95, 0xb1, 0x7a, 0x9a, ++ 0x1f, 0xe0, 0xe3, 0xaa, 0xf8, 0x08, 0xfa, 0x4b, 0xf6, 0x13, 0xae, 0xc7, ++ 0x42, 0xe4, 0x04, 0xad, 0x6b, 0x9d, 0xa0, 0x4f, 0x1f, 0xd2, 0x27, 0xe3, ++ 0xfa, 0x68, 0x83, 0x2d, 0xb8, 0x0e, 0xc9, 0x3f, 0xb7, 0x09, 0x78, 0x4c, ++ 0xf0, 0x7a, 0x8b, 0xcc, 0x9c, 0x4e, 0x4b, 0x70, 0xdc, 0x2b, 0x66, 0xfb, ++ 0x77, 0x9a, 0x90, 0x4e, 0xe7, 0xfb, 0x76, 0x9a, 0x43, 0xe9, 0x74, 0x01, ++ 0xa3, 0xfe, 0xe4, 0x3c, 0x32, 0xba, 0x7c, 0xb4, 0x9e, 0xb4, 0x7d, 0xde, ++ 0x02, 0x4c, 0xc7, 0x1f, 0x09, 0x74, 0x0c, 0x83, 0x7a, 0x29, 0xb5, 0xb0, ++ 0x1e, 0x16, 0x5c, 0x4f, 0x56, 0xe7, 0x87, 0x0a, 0xca, 0xab, 0xac, 0xda, ++ 0x4e, 0x85, 0xa1, 0xfc, 0xdc, 0xb3, 0x83, 0xe6, 0x9d, 0xd9, 0xb9, 0x8b, ++ 0xa7, 0xa8, 0x87, 0x87, 0xf5, 0xd6, 0xb7, 0x8c, 0xad, 0x14, 0x74, 0xc8, ++ 0xfb, 0x79, 0x33, 0x9e, 0xcb, 0xd5, 0xd5, 0x5f, 0xcc, 0x4d, 0x45, 0xba, ++ 0x59, 0x5d, 0xc0, 0xf5, 0xed, 0x2a, 0xbb, 0x56, 0x8e, 0xf3, 0xbe, 0xc3, ++ 0xa1, 0xcd, 0x45, 0xfc, 0xad, 0xb3, 0x6b, 0xf3, 0x30, 0x3f, 0x2b, 0x9a, ++ 0xeb, 0x85, 0xe1, 0xf1, 0x5a, 0x25, 0x7e, 0xcf, 0xea, 0x43, 0xdf, 0x2f, ++ 0x11, 0x70, 0x00, 0xb8, 0x57, 0x63, 0xbb, 0xc4, 0xe5, 0xcc, 0xa7, 0xc0, ++ 0x3a, 0xc6, 0xee, 0xb3, 0xf9, 0x41, 0x55, 0x00, 0xe9, 0xc3, 0xbc, 0x61, ++ 0x41, 0x89, 0xb5, 0x3e, 0xc5, 0x0c, 0x70, 0x4d, 0xd4, 0x98, 0x1b, 0xe5, ++ 0x74, 0xbf, 0x04, 0x6f, 0xbd, 0x09, 0xea, 0x75, 0x5f, 0xc1, 0xdc, 0x4f, ++ 0x41, 0x3e, 0xae, 0xd4, 0x51, 0x80, 0xf0, 0x72, 0xce, 0x77, 0x77, 0x20, ++ 0x3c, 0x57, 0x7f, 0xa1, 0x92, 0x7d, 0xbb, 0x7a, 0x29, 0xf3, 0xaf, 0xa4, ++ 0x7e, 0x18, 0xff, 0x3f, 0x6f, 0x7f, 0x3f, 0xca, 0x57, 0xe4, 0xdf, 0x50, ++ 0x7e, 0xf1, 0x89, 0x79, 0xf8, 0xe2, 0x39, 0x1f, 0x80, 0xbd, 0xf3, 0xf3, ++ 0x78, 0xce, 0x9f, 0x75, 0xc4, 0x9f, 0xc2, 0xde, 0x91, 0x7c, 0xd9, 0x97, ++ 0xfd, 0x12, 0xc2, 0xd7, 0xab, 0x2f, 0x92, 0xaf, 0xef, 0xbf, 0x48, 0xbe, ++ 0x5e, 0x2b, 0xf8, 0xfa, 0x97, 0x94, 0x9e, 0x87, 0xaf, 0x1f, 0x0d, 0xf2, ++ 0xf5, 0x3a, 0x9c, 0xd7, 0xf9, 0xf8, 0x7a, 0xb3, 0xe0, 0xe7, 0x37, 0x05, ++ 0x7f, 0xf7, 0xc5, 0xd7, 0x7f, 0x10, 0x70, 0x7b, 0x27, 0xbe, 0x4f, 0x3f, ++ 0x67, 0x33, 0x8e, 0xd7, 0x5b, 0x8e, 0x73, 0xba, 0x93, 0x7c, 0xf1, 0xd2, ++ 0x9e, 0x51, 0x31, 0xe5, 0xd0, 0xef, 0x4e, 0x31, 0xcf, 0x10, 0xf9, 0xdd, ++ 0x8a, 0xeb, 0x3b, 0x9f, 0xfc, 0xfe, 0x37, 0xf8, 0xfc, 0xf7, 0xd8, 0xef, ++ 0xf9, 0xec, 0x54, 0xd9, 0xaf, 0xc4, 0xf7, 0xf9, 0xf8, 0x64, 0xb8, 0xd3, ++ 0x43, 0xf0, 0x92, 0xf6, 0x68, 0xac, 0xdd, 0x41, 0xeb, 0x91, 0x7c, 0x0f, ++ 0xfc, 0xb2, 0x47, 0xf0, 0xcb, 0x5e, 0xc1, 0x2f, 0x6f, 0x61, 0x3a, 0x2b, ++ 0x9a, 0xdb, 0x07, 0xe1, 0xfc, 0xd5, 0xa3, 0xef, 0x3a, 0xb9, 0x3c, 0x01, ++ 0x4f, 0x26, 0x06, 0xe9, 0x47, 0x8e, 0x7f, 0xa4, 0x37, 0xbc, 0xfe, 0x12, ++ 0x09, 0x5e, 0x59, 0x4c, 0xc0, 0xab, 0x98, 0xcb, 0x91, 0x4c, 0xe6, 0x53, ++ 0x63, 0xb1, 0xdf, 0xa9, 0x0e, 0xca, 0x3b, 0x4e, 0x38, 0xea, 0xd1, 0x55, ++ 0x8c, 0x3d, 0xd4, 0xed, 0x43, 0xb8, 0x7d, 0x1b, 0xcf, 0xfd, 0xcc, 0x5c, ++ 0x85, 0x79, 0x22, 0xd9, 0x75, 0xc7, 0x04, 0x9f, 0x24, 0x76, 0x16, 0x92, ++ 0x7c, 0x01, 0x78, 0x1e, 0xc2, 0x71, 0x25, 0xbd, 0x27, 0x32, 0xc7, 0x14, ++ 0xf4, 0x73, 0xa2, 0x9c, 0x5c, 0x6e, 0x8c, 0x1e, 0xa7, 0xed, 0x44, 0xb9, ++ 0xe4, 0xd0, 0x3c, 0x2a, 0xda, 0x1b, 0xb9, 0x4e, 0xce, 0x0f, 0x12, 0x4e, ++ 0xd0, 0xfe, 0x8b, 0x48, 0xf8, 0xd8, 0x8e, 0xf8, 0x18, 0xd6, 0xdb, 0x6f, ++ 0x08, 0xc7, 0xc3, 0xa7, 0x62, 0xbe, 0x51, 0x4e, 0x0e, 0x8f, 0xf0, 0xfe, ++ 0xa5, 0xfc, 0xc1, 0xfe, 0x87, 0x53, 0xff, 0x2e, 0x03, 0xf6, 0x2f, 0xdb, ++ 0xff, 0x10, 0x94, 0x43, 0xdf, 0x23, 0x7e, 0xc6, 0x2e, 0xaf, 0x55, 0x71, ++ 0x5d, 0x89, 0x4c, 0x8b, 0x41, 0xf9, 0x23, 0xe5, 0x24, 0xcb, 0x84, 0xf6, ++ 0xb9, 0xbd, 0xdb, 0x9b, 0xc4, 0xb8, 0xd0, 0xde, 0xe4, 0x84, 0x74, 0x6c, ++ 0x2d, 0xb4, 0x1f, 0x16, 0x6c, 0x9f, 0xc5, 0x02, 0x0a, 0xc2, 0xc3, 0x39, ++ 0x1f, 0xe4, 0x14, 0x43, 0xfb, 0xdd, 0x4d, 0xf6, 0x6c, 0x9b, 0xd5, 0x63, ++ 0x73, 0x12, 0xbd, 0x30, 0x2e, 0xaf, 0x0a, 0x0c, 0x24, 0x0f, 0xa6, 0xd9, ++ 0x34, 0xe2, 0xa7, 0x48, 0xfa, 0xdf, 0x79, 0x91, 0xfa, 0xdf, 0x29, 0xf4, ++ 0xbf, 0xf3, 0x42, 0xf4, 0xbf, 0x33, 0xa8, 0xff, 0xb1, 0x9d, 0x72, 0x3e, ++ 0xfd, 0x2f, 0xea, 0x8f, 0x70, 0x9e, 0x5b, 0x4e, 0xb8, 0x7b, 0xf0, 0x22, ++ 0xe3, 0x04, 0xbd, 0xf5, 0xbf, 0x33, 0x82, 0xfe, 0xdf, 0x6f, 0xd5, 0xa8, ++ 0xdf, 0x08, 0x7c, 0x34, 0x12, 0xd7, 0x13, 0xe3, 0xd0, 0x46, 0x61, 0x0a, ++ 0x7c, 0x34, 0xda, 0x99, 0x14, 0xd4, 0x3b, 0xd0, 0x6e, 0x0c, 0x7e, 0x6f, ++ 0x13, 0xed, 0x9b, 0xa7, 0x1a, 0x86, 0x92, 0x7d, 0xcd, 0xa2, 0xdd, 0x91, ++ 0xfc, 0x99, 0x42, 0xa7, 0x4d, 0x37, 0xaf, 0x2b, 0x85, 0x9f, 0xc2, 0xda, ++ 0xff, 0xfb, 0xb7, 0xff, 0x91, 0xc7, 0x58, 0x0d, 0x16, 0xf1, 0x79, 0x16, ++ 0x3a, 0x43, 0xfc, 0x96, 0x07, 0xa7, 0x7e, 0x9a, 0xec, 0x25, 0x3f, 0x8e, ++ 0xe9, 0xe2, 0x2b, 0xbf, 0x5e, 0xe9, 0x7e, 0x6f, 0x08, 0x8e, 0xf7, 0xae, ++ 0xca, 0x90, 0xbf, 0x7e, 0xfd, 0x9f, 0x5d, 0x66, 0x84, 0x77, 0x6b, 0x74, ++ 0xec, 0x08, 0x16, 0x17, 0x1c, 0xb7, 0xe6, 0x5f, 0x40, 0x58, 0x60, 0xcf, ++ 0x9f, 0xfc, 0x97, 0x81, 0x52, 0x89, 0xc7, 0x25, 0xed, 0xca, 0x68, 0x06, ++ 0x0c, 0x59, 0xb0, 0xf3, 0x3b, 0x8a, 0x93, 0x9c, 0xec, 0xf8, 0x17, 0xc5, ++ 0x49, 0x2e, 0xb5, 0x97, 0xcf, 0xc0, 0x75, 0xed, 0x7a, 0x8d, 0xc7, 0x4b, ++ 0x4e, 0xbf, 0x7d, 0xd0, 0x89, 0x74, 0x24, 0xc7, 0x5f, 0x26, 0xfc, 0xc8, ++ 0x49, 0xea, 0xb0, 0xd6, 0x00, 0xd0, 0xd3, 0xa9, 0xcd, 0x66, 0x37, 0xfa, ++ 0x21, 0x2a, 0x73, 0x3d, 0x92, 0x0f, 0xf3, 0xa9, 0xd9, 0x63, 0x62, 0x7e, ++ 0x92, 0x83, 0xcc, 0x8a, 0xf5, 0x4d, 0x7c, 0xba, 0xcc, 0xb4, 0x79, 0x75, ++ 0xa7, 0x1a, 0x8b, 0x79, 0xa3, 0x4f, 0xc4, 0x39, 0x94, 0xb3, 0xa4, 0xef, ++ 0x5c, 0x71, 0x48, 0x97, 0xa6, 0x3d, 0x2a, 0xf9, 0x15, 0x2c, 0x91, 0x97, ++ 0xd7, 0x32, 0x6b, 0xfd, 0xd9, 0xfe, 0x20, 0x57, 0xc7, 0x19, 0x98, 0x2b, ++ 0x24, 0x2e, 0x12, 0xaf, 0x45, 0x33, 0x57, 0x48, 0x9c, 0x22, 0xa1, 0xd8, ++ 0xa9, 0xcb, 0x33, 0x8c, 0xa7, 0xc0, 0xb8, 0x8b, 0x18, 0x9f, 0x67, 0x92, ++ 0x27, 0x5d, 0xd7, 0x3e, 0x65, 0x76, 0x7f, 0x5d, 0xfd, 0x34, 0xef, 0xa5, ++ 0xba, 0xf2, 0x8c, 0xf9, 0xa3, 0x74, 0xf9, 0xac, 0xda, 0xf1, 0xba, 0xfa, ++ 0xfd, 0xc0, 0x3f, 0x0a, 0xcd, 0xe7, 0xf8, 0xae, 0xd3, 0xd5, 0x1f, 0xd0, ++ 0x34, 0x43, 0x97, 0x1f, 0xd4, 0x72, 0x8b, 0xae, 0xfe, 0xe7, 0xac, 0xf6, ++ 0xe1, 0x7c, 0x5c, 0xb7, 0x4f, 0xeb, 0x1c, 0x08, 0xf3, 0x9c, 0x27, 0xe6, ++ 0x39, 0x64, 0x5d, 0xb9, 0xae, 0xdd, 0xa5, 0x86, 0xd6, 0x3c, 0xe0, 0x68, ++ 0x36, 0x2f, 0xb0, 0x70, 0x2a, 0x1b, 0x01, 0xfc, 0xe8, 0x5f, 0xa8, 0xeb, ++ 0xe7, 0xf8, 0xb3, 0xc5, 0x7b, 0x14, 0xf8, 0xce, 0x5a, 0x4c, 0x87, 0x38, ++ 0xbc, 0x6a, 0x19, 0xc2, 0x8b, 0xd6, 0x0f, 0xf0, 0xac, 0x6c, 0x53, 0xd8, ++ 0x63, 0xd0, 0xbe, 0x6a, 0x1d, 0x2f, 0x97, 0xed, 0xe6, 0xb7, 0xaf, 0x5d, ++ 0x9d, 0x01, 0xe9, 0x02, 0xbf, 0xfe, 0x3b, 0x63, 0x7e, 0x33, 0xca, 0xfd, ++ 0x45, 0x9b, 0xf5, 0xdf, 0x1f, 0x74, 0xda, 0x13, 0x29, 0x4e, 0x93, 0xce, ++ 0xd2, 0xcf, 0xaa, 0x91, 0xe8, 0xc0, 0x46, 0xe3, 0x9d, 0x5a, 0xaf, 0xfa, ++ 0x2d, 0x80, 0x3f, 0xd5, 0x37, 0x24, 0x8c, 0x0e, 0xf4, 0xf8, 0x60, 0xff, ++ 0x4b, 0xba, 0x70, 0x09, 0xba, 0xb0, 0xa4, 0xea, 0xe9, 0x22, 0xca, 0xa5, ++ 0xa7, 0x8b, 0xaa, 0xbd, 0xdb, 0xf2, 0x02, 0xac, 0x37, 0x9c, 0x63, 0x86, ++ 0x3a, 0x23, 0xc2, 0x51, 0xc2, 0xd9, 0xee, 0xd6, 0xd3, 0x8b, 0x84, 0x2f, ++ 0xe8, 0xc9, 0xff, 0x13, 0xf8, 0xbe, 0x81, 0xf0, 0x8d, 0x09, 0xc2, 0x37, ++ 0x2d, 0xca, 0xbb, 0x03, 0xf9, 0xef, 0x74, 0xdb, 0x72, 0x95, 0xe1, 0x78, ++ 0x5e, 0xef, 0x68, 0x6c, 0xd7, 0x97, 0xfc, 0x9d, 0x62, 0x2f, 0xdc, 0x8d, ++ 0xf2, 0xe2, 0x74, 0xdb, 0xd7, 0xb7, 0xed, 0x80, 0xf5, 0xd5, 0xc4, 0x70, ++ 0xfe, 0x3f, 0xb9, 0xe3, 0xbb, 0xc1, 0x28, 0xdf, 0x64, 0xbd, 0xeb, 0x56, ++ 0x94, 0xbb, 0x27, 0x8e, 0x06, 0xe0, 0x2a, 0xde, 0xf7, 0xb0, 0x7f, 0xf9, ++ 0xbd, 0x73, 0xe8, 0xd3, 0xcd, 0xa3, 0x60, 0x3d, 0xa5, 0x6d, 0x2a, 0xf1, ++ 0xf1, 0x49, 0xa3, 0xad, 0x49, 0xb9, 0x9c, 0x96, 0xe9, 0x72, 0x00, 0xdc, ++ 0x94, 0x1e, 0xbc, 0x71, 0x3c, 0x4a, 0xbc, 0x29, 0xed, 0x3b, 0xff, 0xa9, ++ 0x00, 0xde, 0x2c, 0x30, 0x43, 0x13, 0xc6, 0x1b, 0xc7, 0xb9, 0xad, 0x38, ++ 0x4f, 0x8c, 0xf4, 0x21, 0xbd, 0x28, 0x60, 0x87, 0x9e, 0x8d, 0x21, 0x7d, ++ 0xf2, 0x31, 0xce, 0xcf, 0x57, 0xa8, 0x31, 0x8a, 0xf7, 0xfc, 0x89, 0xb9, ++ 0x1b, 0xa0, 0x56, 0x83, 0x3d, 0xef, 0xb2, 0xf3, 0xc4, 0x05, 0x0e, 0x38, ++ 0x49, 0x5f, 0x7a, 0x1b, 0x51, 0xbe, 0x8e, 0xed, 0xf4, 0x9e, 0xde, 0x82, ++ 0xdd, 0x1b, 0x3b, 0x1d, 0x18, 0xff, 0x9d, 0xe2, 0xf5, 0xd2, 0x7a, 0x2e, ++ 0xc7, 0x09, 0x82, 0xfd, 0xc4, 0x1c, 0x00, 0x27, 0x7b, 0xb0, 0x3d, 0xb4, ++ 0x3b, 0x8e, 0xe3, 0x4e, 0x29, 0x70, 0xc6, 0xa0, 0xbd, 0xb5, 0x75, 0xd7, ++ 0x32, 0xf2, 0xdf, 0x58, 0x7b, 0x22, 0xd9, 0x83, 0x48, 0x32, 0xa1, 0x76, ++ 0x4e, 0xb8, 0x9f, 0x25, 0xed, 0x46, 0xb0, 0xd3, 0x4f, 0xf1, 0x79, 0x78, ++ 0xbe, 0x76, 0x86, 0xda, 0xe9, 0xc2, 0x6e, 0x93, 0xf6, 0x76, 0x5f, 0xfd, ++ 0x80, 0x7e, 0x1d, 0x8a, 0xf6, 0x41, 0x5f, 0xa9, 0xb2, 0x43, 0x1d, 0x6a, ++ 0x04, 0xb8, 0x74, 0x2b, 0xd1, 0xee, 0xa7, 0x22, 0xe8, 0x0d, 0x4b, 0x82, ++ 0xde, 0x9f, 0xbd, 0x32, 0x18, 0xdf, 0xb2, 0x24, 0x84, 0xe8, 0x89, 0x25, ++ 0x77, 0x9e, 0xde, 0x8d, 0xfa, 0x03, 0xe0, 0x1d, 0x9d, 0x00, 0xf3, 0xb4, ++ 0xdb, 0x41, 0x7f, 0x2b, 0x17, 0xa4, 0xbf, 0x63, 0xb1, 0xfe, 0x23, 0x31, ++ 0xb1, 0x44, 0xd7, 0xdd, 0x7b, 0x55, 0xff, 0x10, 0x68, 0x70, 0xca, 0xea, ++ 0x8a, 0x73, 0x02, 0xbc, 0xf2, 0x51, 0x9f, 0x5c, 0x4e, 0x71, 0x20, 0x96, ++ 0xe1, 0x0c, 0xb6, 0xab, 0xb5, 0xa6, 0x0f, 0x33, 0x82, 0x3e, 0xc9, 0x3f, ++ 0x35, 0x34, 0x8e, 0x9d, 0x23, 0xae, 0x9e, 0x8f, 0xf5, 0x46, 0x07, 0xf3, ++ 0xed, 0x51, 0x4c, 0x67, 0x17, 0xac, 0x1e, 0xc5, 0xe7, 0xe5, 0x12, 0xeb, ++ 0x3c, 0x10, 0xc5, 0xed, 0xac, 0xb1, 0x22, 0x5f, 0x13, 0x16, 0x8f, 0xaa, ++ 0x69, 0xe2, 0xf1, 0xd7, 0x0d, 0x66, 0x60, 0xb5, 0x90, 0x7e, 0xc6, 0x26, ++ 0xd8, 0x79, 0xbc, 0xc7, 0x5a, 0x30, 0x16, 0xd7, 0xb3, 0x41, 0xc4, 0xa1, ++ 0x57, 0xe7, 0x28, 0x64, 0x27, 0xac, 0x56, 0x14, 0xb2, 0x1b, 0x76, 0xda, ++ 0x0a, 0xa9, 0xfc, 0x90, 0xb3, 0x20, 0x0f, 0xe1, 0x77, 0xb9, 0x18, 0x67, ++ 0x2c, 0x8c, 0x81, 0xfa, 0xb9, 0xa5, 0xbf, 0x98, 0x8f, 0xb0, 0xc7, 0x64, ++ 0xff, 0xdd, 0xa2, 0x7e, 0xb7, 0xb3, 0x90, 0xd2, 0xb1, 0x09, 0x0e, 0x81, ++ 0x17, 0xc7, 0xa5, 0x88, 0xff, 0x0a, 0xab, 0x46, 0xfd, 0x9a, 0x55, 0x35, ++ 0x22, 0x9c, 0xf3, 0x13, 0xb8, 0xfd, 0x53, 0x13, 0xcd, 0xa4, 0x9f, 0x46, ++ 0xfc, 0x34, 0x49, 0xf0, 0xd7, 0x64, 0x21, 0x47, 0x8b, 0xec, 0x20, 0x47, ++ 0xb9, 0x1f, 0x38, 0x75, 0x12, 0x94, 0x5f, 0x25, 0xf9, 0x4f, 0xcd, 0xff, ++ 0xd0, 0x0c, 0xa4, 0x3b, 0x29, 0xce, 0xc4, 0x30, 0x5e, 0x7c, 0x95, 0x90, ++ 0x57, 0xec, 0x8c, 0xf1, 0x53, 0x94, 0x27, 0x0e, 0xf8, 0x1f, 0xca, 0x27, ++ 0x6d, 0xa8, 0x63, 0x17, 0x8c, 0xc4, 0x0a, 0x98, 0xe9, 0xd3, 0x50, 0x39, ++ 0x53, 0xc8, 0x3a, 0xd3, 0x91, 0x3e, 0x8a, 0xac, 0xfa, 0xef, 0x93, 0xb6, ++ 0x4f, 0x3e, 0x8a, 0xf2, 0x6f, 0x12, 0x33, 0x06, 0xbf, 0xe7, 0x70, 0x78, ++ 0xc7, 0x38, 0x83, 0x7c, 0x70, 0x63, 0x42, 0x8f, 0x1e, 0xc8, 0x44, 0x39, ++ 0xd5, 0x16, 0xdd, 0xf5, 0xcb, 0x29, 0xe8, 0x1f, 0xbf, 0xa3, 0xba, 0x9f, ++ 0x62, 0xbd, 0xd7, 0x5b, 0x91, 0xc0, 0xed, 0xb0, 0x66, 0xb4, 0xa3, 0x6d, ++ 0x04, 0x2a, 0x0d, 0xe3, 0x97, 0xd9, 0x62, 0x1f, 0xa5, 0x77, 0x7d, 0x0e, ++ 0x9f, 0x0d, 0x7d, 0xc4, 0x79, 0x2b, 0xac, 0x05, 0x73, 0x11, 0xbe, 0xaa, ++ 0xdd, 0x53, 0x81, 0x29, 0xb0, 0xc3, 0xa5, 0xc8, 0xef, 0x6d, 0x66, 0x6f, ++ 0x03, 0xfa, 0x1d, 0xdd, 0x2f, 0x33, 0x9a, 0xc7, 0x50, 0x3f, 0xdb, 0x81, ++ 0xf9, 0xe1, 0x3e, 0x17, 0x2e, 0x17, 0xf0, 0xef, 0x8b, 0x19, 0x81, 0x74, ++ 0x3d, 0xd2, 0x40, 0x7e, 0xbc, 0x6b, 0x5d, 0xcb, 0xce, 0x28, 0x28, 0x77, ++ 0xad, 0x57, 0x9c, 0x0a, 0xe4, 0x4d, 0x46, 0xe6, 0xb3, 0x8f, 0x0a, 0xca, ++ 0x93, 0xc6, 0x84, 0x1c, 0x9a, 0x6c, 0x73, 0x57, 0xf9, 0x0e, 0x3b, 0x94, ++ 0x27, 0xad, 0x9f, 0xae, 0xf4, 0x87, 0xf9, 0xb4, 0xb0, 0x96, 0xa2, 0x58, ++ 0xb4, 0xb7, 0xd6, 0xb3, 0x88, 0x71, 0xc1, 0x3a, 0x41, 0x47, 0x53, 0x0a, ++ 0x76, 0x50, 0x7c, 0x3d, 0xa9, 0x1b, 0xe8, 0x34, 0x02, 0x1d, 0xd4, 0x25, ++ 0x18, 0xa4, 0x1d, 0xff, 0x9f, 0xb8, 0x8e, 0xb1, 0xdd, 0xde, 0xd1, 0x4a, ++ 0xff, 0xa0, 0x3c, 0x22, 0x51, 0x8b, 0x7e, 0xd3, 0x2e, 0x83, 0x3f, 0x52, ++ 0x9c, 0x76, 0x9a, 0xad, 0xa8, 0x11, 0xdb, 0x0d, 0xf7, 0xb3, 0x88, 0x71, ++ 0xbf, 0x9a, 0x68, 0x3e, 0x8f, 0x26, 0xab, 0x67, 0x0d, 0xd2, 0xe9, 0xf0, ++ 0xed, 0x01, 0xf2, 0x87, 0xaa, 0xa4, 0x5c, 0x9f, 0x67, 0x60, 0x46, 0xa0, ++ 0xab, 0x1b, 0x84, 0x1c, 0xbf, 0x61, 0x7d, 0xc7, 0x3f, 0xc9, 0x8e, 0xf8, ++ 0xee, 0xec, 0x59, 0x55, 0xda, 0xa1, 0x8c, 0xfa, 0x67, 0x28, 0x97, 0xaa, ++ 0x6e, 0xb4, 0xfb, 0x31, 0x7e, 0x5f, 0xd5, 0x9e, 0xe3, 0xa3, 0x79, 0x79, ++ 0x14, 0xf7, 0x20, 0x48, 0x6a, 0xda, 0xdf, 0xf7, 0x60, 0xbe, 0x2a, 0x37, ++ 0xd7, 0x81, 0x71, 0x66, 0xed, 0xef, 0x4c, 0x39, 0x3c, 0x94, 0x4c, 0x58, ++ 0xc6, 0xe5, 0x9f, 0x91, 0x1d, 0x96, 0x7a, 0x96, 0xec, 0x06, 0x74, 0x8a, ++ 0x18, 0x9b, 0x21, 0xe8, 0xb9, 0x06, 0xfd, 0xd1, 0x24, 0xd2, 0x1f, 0xcd, ++ 0x31, 0x00, 0xff, 0xaa, 0xf5, 0xf5, 0x3b, 0xd2, 0xa0, 0xbf, 0x3f, 0x3f, ++ 0x0d, 0x7d, 0x40, 0xd1, 0x3e, 0xd5, 0xbb, 0xef, 0x67, 0xd0, 0xef, 0x4d, ++ 0xa0, 0xc4, 0x56, 0x8c, 0xc2, 0xd4, 0xc8, 0x4a, 0x29, 0x0e, 0x9d, 0x4a, ++ 0xfd, 0xdc, 0x28, 0xfa, 0xf1, 0xfd, 0x0b, 0xc6, 0xb5, 0x06, 0xc7, 0xbd, ++ 0xa9, 0x7d, 0x2f, 0xad, 0x67, 0x9f, 0x89, 0xf9, 0xac, 0x40, 0xbf, 0xa6, ++ 0x42, 0x3e, 0xb4, 0xe9, 0x3f, 0xe2, 0xfc, 0x0d, 0x28, 0x08, 0x99, 0x9f, ++ 0xe8, 0x6c, 0xa6, 0xb5, 0x65, 0x12, 0xea, 0xd7, 0x93, 0xe6, 0xee, 0x11, ++ 0x6e, 0xb4, 0x7f, 0x5f, 0xfb, 0x6b, 0x96, 0x0f, 0xe0, 0xff, 0xf1, 0xcf, ++ 0x4f, 0xdb, 0xd1, 0x2e, 0xfe, 0xc4, 0xd8, 0x6d, 0xc7, 0xef, 0x47, 0xee, ++ 0xfe, 0xc0, 0xae, 0x01, 0xfc, 0x3e, 0xbe, 0x5b, 0x2d, 0x46, 0x78, 0xdf, ++ 0x26, 0xf4, 0x8d, 0x84, 0x77, 0x87, 0xc0, 0x7b, 0x42, 0xa2, 0xa7, 0x0d, ++ 0xf1, 0x72, 0x7b, 0xdd, 0xf7, 0x79, 0xde, 0x10, 0xbc, 0xb3, 0x15, 0x49, ++ 0xc4, 0x3f, 0x0b, 0xfc, 0x30, 0xc3, 0x10, 0xbb, 0x63, 0xd1, 0xe6, 0x18, ++ 0xb4, 0x84, 0x7a, 0xf2, 0xd5, 0xad, 0x09, 0xba, 0xbc, 0xd4, 0x1f, 0xd5, ++ 0x16, 0x56, 0x1b, 0x29, 0x0e, 0xf4, 0x8d, 0xe0, 0x97, 0x05, 0x5b, 0x36, ++ 0x98, 0x33, 0x5c, 0x38, 0xbe, 0xf7, 0x2d, 0x1c, 0xff, 0x88, 0x91, 0xd3, ++ 0xcf, 0x91, 0xed, 0x76, 0xbf, 0x2f, 0x27, 0x38, 0x9f, 0xf2, 0x2d, 0x23, ++ 0xcd, 0x68, 0x97, 0x7c, 0xd2, 0x6e, 0x61, 0x01, 0xd4, 0x83, 0xc6, 0x4e, ++ 0x13, 0xb3, 0x71, 0x39, 0xa3, 0x00, 0x3d, 0x78, 0x05, 0xde, 0xc3, 0xe7, ++ 0xb9, 0xfb, 0xf5, 0x18, 0xea, 0xaf, 0xe2, 0x57, 0x5c, 0x2e, 0x95, 0xc1, ++ 0x58, 0x2b, 0x00, 0xae, 0xde, 0xf6, 0x05, 0x24, 0x7f, 0xc2, 0xd7, 0x51, ++ 0xf1, 0xb1, 0x6b, 0x72, 0x0a, 0xc0, 0xbb, 0xe2, 0x5e, 0x85, 0xe1, 0xbe, ++ 0x0a, 0xd6, 0xbf, 0x1b, 0xf0, 0xe6, 0x5d, 0x71, 0xcf, 0x57, 0x68, 0xe7, ++ 0x85, 0xaf, 0xb3, 0xcc, 0xa7, 0x97, 0x47, 0x73, 0x9b, 0xf4, 0x79, 0x29, ++ 0x27, 0xab, 0x04, 0xbe, 0xe7, 0x31, 0x77, 0x13, 0xda, 0xcf, 0x15, 0x2d, ++ 0xfa, 0x7a, 0x55, 0xed, 0xf7, 0x51, 0xff, 0x55, 0x61, 0x72, 0xec, 0x78, ++ 0x82, 0xb0, 0xaf, 0xf2, 0xd8, 0xd8, 0xb3, 0x60, 0xa7, 0x34, 0xd8, 0xfa, ++ 0xc7, 0x79, 0xcf, 0xa1, 0xaf, 0x4e, 0xd4, 0x81, 0x5c, 0x1f, 0xcc, 0xd8, ++ 0xb1, 0x3a, 0x2b, 0xa5, 0x47, 0xea, 0x18, 0xa5, 0x6d, 0x09, 0x2e, 0x82, ++ 0xf7, 0xe2, 0xf6, 0xf7, 0xef, 0x42, 0xba, 0x59, 0xd2, 0xb6, 0xd5, 0x8c, ++ 0xfd, 0x34, 0xfa, 0x27, 0x39, 0xc6, 0x43, 0x15, 0x4b, 0xfb, 0xcd, 0x0c, ++ 0xbf, 0x5b, 0x70, 0x5f, 0x15, 0x9a, 0xce, 0xc1, 0x7d, 0x55, 0x98, 0x27, ++ 0xda, 0x3a, 0x88, 0xff, 0xd1, 0x8a, 0xe7, 0x7b, 0xe4, 0x47, 0x93, 0x23, ++ 0x6c, 0x9f, 0x55, 0xac, 0xaf, 0x54, 0xc0, 0x9f, 0xd9, 0xb8, 0x5d, 0x51, ++ 0x8a, 0xeb, 0x19, 0x81, 0xdf, 0x8d, 0x5f, 0x87, 0xae, 0xe7, 0xd4, 0x9e, ++ 0xd1, 0x56, 0x1c, 0xd7, 0x9c, 0x28, 0xe4, 0xf1, 0x58, 0x58, 0x97, 0x7a, ++ 0xe1, 0xeb, 0x92, 0xeb, 0x91, 0xeb, 0x93, 0xe5, 0xd5, 0x2a, 0xd0, 0x59, ++ 0x84, 0xf6, 0x92, 0xbe, 0xdb, 0x04, 0xbd, 0xcd, 0xdb, 0x38, 0x7d, 0x75, ++ 0x3a, 0x80, 0xa2, 0xe1, 0xb5, 0xcf, 0xb3, 0xbb, 0xb8, 0x5f, 0x4a, 0xf6, ++ 0xbc, 0x51, 0xe0, 0xc7, 0x68, 0x5b, 0x43, 0xf6, 0xbc, 0x91, 0x81, 0xbd, ++ 0xce, 0xd7, 0x29, 0xec, 0x79, 0xf6, 0x21, 0xf2, 0xad, 0xa4, 0xb3, 0x70, ++ 0x3a, 0xaa, 0x42, 0x38, 0x50, 0x00, 0x87, 0xb7, 0xb3, 0x0a, 0x3b, 0xbf, ++ 0x87, 0x7e, 0xda, 0xef, 0x27, 0x78, 0x48, 0x3c, 0x03, 0x7f, 0xa4, 0x8a, ++ 0x7d, 0xb3, 0x54, 0xdc, 0x37, 0x03, 0x3a, 0x3a, 0x14, 0x46, 0x47, 0xba, ++ 0x7c, 0x45, 0x8b, 0x3e, 0xff, 0xa5, 0xa9, 0x2b, 0x1b, 0xf9, 0x1b, 0xe8, ++ 0xe5, 0x50, 0x28, 0x7c, 0xbf, 0x0c, 0x3b, 0x67, 0x21, 0xd3, 0xa4, 0xc4, ++ 0xfe, 0x04, 0x87, 0x79, 0x2e, 0x6d, 0xb2, 0x03, 0xca, 0x2b, 0x98, 0x67, ++ 0x35, 0xdf, 0x5f, 0x6d, 0x21, 0xb8, 0x1c, 0x31, 0xb6, 0xec, 0xfe, 0x19, ++ 0xf2, 0xdd, 0x46, 0x4e, 0xf7, 0x9f, 0x08, 0xbc, 0xff, 0x32, 0xd1, 0x33, ++ 0x21, 0x11, 0xf5, 0x95, 0x51, 0x1b, 0x81, 0xf2, 0xbd, 0x70, 0x65, 0x9a, ++ 0x9a, 0x08, 0xf5, 0xca, 0x9a, 0x15, 0x07, 0xf2, 0xd3, 0xdc, 0xc6, 0x91, ++ 0x93, 0x91, 0x0f, 0x47, 0x31, 0x8d, 0xfa, 0x9b, 0x93, 0x10, 0xd9, 0x4e, ++ 0x9b, 0x93, 0xc8, 0xe1, 0x5f, 0x5e, 0x6b, 0x62, 0x66, 0xb0, 0xef, 0xcb, ++ 0x61, 0x0c, 0x94, 0x6b, 0xe5, 0xdb, 0x55, 0xe2, 0x73, 0xa0, 0x23, 0x5b, ++ 0x09, 0xe0, 0x61, 0xbe, 0xc0, 0x43, 0xf5, 0xbd, 0x5b, 0xcd, 0x69, 0x90, ++ 0xce, 0xaf, 0xad, 0xe2, 0x76, 0x82, 0x9f, 0xf3, 0x0b, 0xc0, 0x95, 0xec, ++ 0x84, 0x85, 0xcd, 0x1d, 0x66, 0xa4, 0x57, 0xf0, 0x47, 0x22, 0xf2, 0x9b, ++ 0xd4, 0x03, 0xd5, 0xad, 0xfa, 0xf2, 0x1a, 0xd6, 0x4c, 0x78, 0xa8, 0x41, ++ 0x3e, 0x93, 0x74, 0x0c, 0xe3, 0xcf, 0x4e, 0x14, 0x7c, 0xe6, 0x66, 0x6e, ++ 0xa4, 0x47, 0xef, 0x5d, 0x76, 0xab, 0x12, 0x77, 0xfe, 0xf5, 0xb2, 0xde, ++ 0x71, 0x05, 0x8a, 0x3b, 0x9c, 0xda, 0x33, 0x88, 0xec, 0xca, 0x53, 0x2e, ++ 0x57, 0x0a, 0xd6, 0xf3, 0x02, 0xce, 0x3b, 0xd1, 0x5e, 0x36, 0x7a, 0xc7, ++ 0xe2, 0x77, 0x80, 0x13, 0xe9, 0xa3, 0xee, 0xfa, 0x18, 0x3f, 0xda, 0xcd, ++ 0x07, 0xce, 0x80, 0x3f, 0x88, 0x36, 0x9c, 0xc3, 0x3b, 0x16, 0xed, 0xa4, ++ 0xae, 0xbf, 0x67, 0xb1, 0x35, 0x4a, 0x90, 0x3e, 0xe5, 0x7a, 0x6a, 0xac, ++ 0xcd, 0x44, 0x9f, 0x35, 0x4c, 0xef, 0x6f, 0x96, 0x81, 0x63, 0x83, 0xfb, ++ 0x9b, 0x65, 0x9b, 0x12, 0xfc, 0x3e, 0x85, 0xfa, 0x1f, 0xd1, 0x86, 0x76, ++ 0xc5, 0x26, 0x13, 0xd9, 0x0d, 0x3e, 0xb6, 0x2c, 0x95, 0x01, 0x9d, 0x79, ++ 0x56, 0x99, 0x48, 0x1e, 0x96, 0xb7, 0xc5, 0x93, 0xbf, 0x5b, 0xde, 0xc8, ++ 0xf7, 0x01, 0xca, 0xb7, 0xc4, 0xfb, 0x55, 0xee, 0xd7, 0x7f, 0x38, 0x30, ++ 0x2f, 0x88, 0x87, 0x03, 0x8d, 0x45, 0xe6, 0x34, 0xc2, 0x53, 0x8e, 0x9b, ++ 0xe2, 0xc3, 0x6d, 0x26, 0x1d, 0x7d, 0x4b, 0xfc, 0x84, 0xfb, 0x8b, 0x0b, ++ 0x9b, 0x3a, 0x76, 0xa7, 0xba, 0x7a, 0xfb, 0x8b, 0x11, 0xf0, 0x73, 0xa8, ++ 0x0f, 0xfc, 0x1c, 0x0a, 0xc5, 0x4f, 0x73, 0x18, 0x7e, 0xd8, 0xdd, 0x09, ++ 0x5c, 0xce, 0x2c, 0x7d, 0x73, 0x90, 0x15, 0xe6, 0x77, 0xaa, 0x36, 0xca, ++ 0xad, 0x46, 0xb0, 0x37, 0xa4, 0x1e, 0x62, 0x99, 0x40, 0x80, 0x79, 0xc1, ++ 0xf8, 0x53, 0x71, 0x3a, 0xc7, 0x07, 0x33, 0xba, 0x93, 0x11, 0x9f, 0xa7, ++ 0x9b, 0xc7, 0x10, 0xbe, 0xc2, 0xf1, 0x54, 0xfc, 0xc3, 0x5c, 0xc2, 0x07, ++ 0xfb, 0xbb, 0x9d, 0xa1, 0x3d, 0x33, 0x07, 0xfc, 0x90, 0x19, 0xf0, 0xfd, ++ 0x76, 0x85, 0xf3, 0xc7, 0x9c, 0x86, 0x6b, 0x8b, 0x51, 0x5f, 0x6f, 0x4a, ++ 0xe4, 0x72, 0xe6, 0x3d, 0x90, 0x4f, 0x9a, 0x99, 0xb1, 0xf7, 0x41, 0x3e, ++ 0x69, 0x20, 0x9f, 0x3e, 0x00, 0xb9, 0x85, 0xf9, 0x3f, 0xd7, 0xa5, 0x52, ++ 0xfe, 0xaf, 0x75, 0x2e, 0x4a, 0xff, 0x56, 0x37, 0x94, 0xd2, 0x43, 0x62, ++ 0xbf, 0x54, 0xf2, 0x0d, 0x10, 0x80, 0x19, 0xed, 0xc2, 0xe7, 0x04, 0xbf, ++ 0x3c, 0x97, 0x28, 0xe3, 0x81, 0xcb, 0x53, 0xd1, 0x74, 0x28, 0xfe, 0xe1, ++ 0x83, 0x31, 0x06, 0x34, 0xdd, 0x7d, 0x33, 0xaf, 0x9b, 0x94, 0xc5, 0xd8, ++ 0xf5, 0x9a, 0x5e, 0xdf, 0xcd, 0xbe, 0x51, 0xaf, 0xcf, 0xba, 0x4c, 0x8e, ++ 0xc9, 0xa9, 0xe8, 0xb7, 0xde, 0xab, 0x90, 0xdd, 0x57, 0xee, 0x99, 0xa0, ++ 0xab, 0xcf, 0x8c, 0x2e, 0xf3, 0x74, 0x0c, 0x6c, 0x0f, 0x1d, 0x1d, 0xfc, ++ 0x4e, 0xf6, 0x9c, 0xcb, 0x3c, 0x03, 0xf8, 0xfd, 0xe6, 0xa9, 0x09, 0xba, ++ 0xfa, 0x33, 0x9b, 0x32, 0x74, 0xf9, 0x9d, 0x89, 0x2e, 0x5a, 0xf7, 0xf4, ++ 0xe2, 0x01, 0xba, 0xef, 0xb7, 0x94, 0x5e, 0xa6, 0xcb, 0x97, 0x9d, 0x01, ++ 0x20, 0x8c, 0x46, 0x6a, 0x76, 0x12, 0x1e, 0x96, 0x5b, 0x99, 0x30, 0x16, ++ 0x9d, 0x3c, 0x2e, 0xe8, 0xe0, 0x75, 0xbf, 0xae, 0x1d, 0x9b, 0xf2, 0x13, ++ 0x98, 0xef, 0xd7, 0x6f, 0x9b, 0xa8, 0x3c, 0x1c, 0x1f, 0x12, 0xaf, 0xf3, ++ 0xd6, 0x19, 0x98, 0x17, 0xa6, 0x36, 0x77, 0x1d, 0xac, 0x0d, 0xfa, 0x3d, ++ 0xd4, 0x02, 0x78, 0x82, 0x76, 0xc7, 0xf7, 0xd9, 0xc9, 0xbf, 0x58, 0xbd, ++ 0x65, 0xf4, 0xbb, 0xe3, 0x20, 0x7f, 0x60, 0x8b, 0x89, 0xe2, 0x02, 0x07, ++ 0x1a, 0x13, 0x1e, 0x40, 0xfb, 0xe8, 0xc0, 0x96, 0xa4, 0x58, 0x06, 0xa9, ++ 0x77, 0xb5, 0x2a, 0xec, 0x08, 0x87, 0x99, 0x85, 0xc8, 0xab, 0xa2, 0xc6, ++ 0xfa, 0xdb, 0x50, 0x2e, 0x95, 0xf9, 0x2d, 0x6e, 0xb2, 0x17, 0x76, 0xf9, ++ 0x9e, 0x94, 0x79, 0x17, 0xfa, 0xa3, 0x38, 0x49, 0xe4, 0x97, 0x0f, 0x55, ++ 0x3f, 0xc6, 0xb7, 0x00, 0x7f, 0x3c, 0x2e, 0xf0, 0xac, 0x85, 0xec, 0xdd, ++ 0x23, 0x60, 0xb7, 0xe1, 0xd6, 0xf8, 0x11, 0x85, 0x35, 0x62, 0x8a, 0x8a, ++ 0x25, 0x0e, 0xca, 0xbf, 0xe9, 0x4c, 0xf2, 0x23, 0x3f, 0x17, 0xff, 0xa0, ++ 0x6a, 0xa9, 0x48, 0x4f, 0xcf, 0x46, 0x51, 0x7d, 0x8a, 0x50, 0x40, 0xf9, ++ 0xb1, 0xf7, 0x07, 0x3d, 0xb5, 0x86, 0xe8, 0xcb, 0xd5, 0x1a, 0x20, 0xbe, ++ 0xb5, 0x90, 0x3f, 0x30, 0xb7, 0x8b, 0xaf, 0x8f, 0x29, 0xa3, 0x32, 0x10, ++ 0xff, 0x47, 0xe2, 0x99, 0x16, 0x0f, 0x93, 0xa8, 0x5e, 0xf6, 0xd7, 0xfd, ++ 0x46, 0xc0, 0xd3, 0x82, 0xc1, 0x9d, 0x23, 0x02, 0xd0, 0xae, 0x34, 0x27, ++ 0x90, 0x34, 0x0b, 0xda, 0x9d, 0xd8, 0x68, 0xa2, 0xf3, 0x20, 0xd8, 0xaf, ++ 0x03, 0xf2, 0xd5, 0xcf, 0x59, 0x36, 0x70, 0x39, 0xa2, 0xa5, 0x4c, 0x1f, ++ 0x1e, 0x0a, 0x4f, 0xff, 0x08, 0x5c, 0xf7, 0x1c, 0x83, 0xe7, 0xff, 0x25, ++ 0x02, 0xfe, 0x8e, 0x55, 0xfa, 0x47, 0x90, 0x3c, 0xbb, 0x3b, 0x89, 0xf8, ++ 0x2a, 0x1c, 0xee, 0x87, 0xcc, 0x5e, 0x82, 0xaf, 0x0f, 0xf9, 0x40, 0x09, ++ 0xca, 0xc7, 0x20, 0x9f, 0xf1, 0x7d, 0x1e, 0x10, 0x6a, 0x69, 0x28, 0x67, ++ 0xe6, 0x9a, 0xdc, 0xc9, 0xa8, 0x9f, 0x0e, 0x35, 0x9b, 0xc8, 0xee, 0x04, ++ 0xfd, 0x11, 0x3b, 0x9d, 0xe2, 0x2b, 0x2f, 0x11, 0x1d, 0x1f, 0x32, 0xba, ++ 0x26, 0xe3, 0xba, 0x0f, 0x35, 0xe5, 0x30, 0x94, 0x57, 0x72, 0xdc, 0xf2, ++ 0x66, 0x95, 0xfc, 0x02, 0xa4, 0x3f, 0xaa, 0xbf, 0x56, 0xf5, 0x82, 0x8d, ++ 0xc0, 0xa4, 0x9e, 0xf2, 0x35, 0x29, 0x5e, 0x96, 0xd2, 0x9b, 0x6e, 0xee, ++ 0x58, 0x3a, 0x36, 0x05, 0xd7, 0x13, 0x6e, 0xdf, 0xca, 0xf4, 0x4b, 0xe0, ++ 0x55, 0x6f, 0x88, 0xbd, 0xb0, 0xf0, 0x35, 0xd5, 0x43, 0xe7, 0x81, 0x72, ++ 0xbb, 0x8c, 0x37, 0x0e, 0x0f, 0x5d, 0x47, 0x23, 0xe7, 0xb7, 0x54, 0xde, ++ 0xff, 0x72, 0x21, 0xd7, 0x17, 0xf7, 0xff, 0xc3, 0x7e, 0x9b, 0x01, 0xe5, ++ 0xfa, 0x80, 0x38, 0x8c, 0x93, 0x1f, 0xfd, 0x50, 0x25, 0x3a, 0x3b, 0xda, ++ 0xbf, 0x25, 0x2f, 0x15, 0x48, 0xff, 0x84, 0x61, 0x47, 0xde, 0x4f, 0x20, ++ 0x7f, 0xbc, 0xc4, 0x77, 0xd8, 0x08, 0xf9, 0x27, 0x2d, 0xde, 0x81, 0x49, ++ 0xb0, 0xa4, 0x45, 0x86, 0xe6, 0x6c, 0xf4, 0x8f, 0x4e, 0xb6, 0x1f, 0x7c, ++ 0x60, 0x02, 0xb4, 0x3b, 0xf6, 0xbc, 0xc9, 0x8d, 0xc3, 0x2e, 0x7c, 0x76, ++ 0x41, 0x3f, 0x8a, 0xe7, 0x08, 0xfb, 0xba, 0xb7, 0xdc, 0x0a, 0xa4, 0x73, ++ 0xfb, 0x40, 0x4b, 0x53, 0x00, 0x9e, 0x8b, 0x5c, 0xad, 0xa4, 0xb7, 0x5d, ++ 0x5b, 0x14, 0xc6, 0xd7, 0xef, 0xe7, 0xe7, 0x05, 0x84, 0x1e, 0x77, 0x3c, ++ 0xa4, 0xa0, 0x2d, 0xc5, 0x0e, 0x8e, 0xb1, 0xaf, 0xc1, 0x78, 0xc7, 0x5c, ++ 0x60, 0x8f, 0x50, 0xbb, 0xfb, 0xa0, 0x89, 0xdb, 0x05, 0x79, 0x49, 0x5c, ++ 0x9e, 0x48, 0xfd, 0xbe, 0x5c, 0xe4, 0xe7, 0x1a, 0x38, 0x5d, 0xb3, 0xd7, ++ 0x15, 0xff, 0x26, 0x61, 0xef, 0x84, 0xea, 0x01, 0x29, 0x97, 0x27, 0x25, ++ 0xf5, 0xa7, 0xfa, 0x3d, 0x7a, 0x99, 0xb5, 0x92, 0xbc, 0xaa, 0xc4, 0x73, ++ 0x1d, 0xb0, 0xbe, 0xc5, 0x9b, 0x2d, 0x7e, 0x7f, 0x0e, 0xb5, 0x71, 0x20, ++ 0x9f, 0x2f, 0xe0, 0xe8, 0x61, 0xf5, 0x49, 0x2e, 0x7e, 0xbe, 0xc7, 0xfc, ++ 0xfc, 0xc3, 0xc8, 0x43, 0x55, 0xac, 0x93, 0xe6, 0x7d, 0xcc, 0xe4, 0xaf, ++ 0xec, 0xcc, 0xc1, 0xf6, 0x1b, 0x1a, 0x9d, 0xd4, 0xde, 0xe4, 0xa6, 0xb8, ++ 0xab, 0xd0, 0x27, 0x56, 0x60, 0x20, 0x94, 0x47, 0x55, 0x82, 0xef, 0xaa, ++ 0x5b, 0x14, 0x7f, 0x80, 0xf8, 0x86, 0xeb, 0xc5, 0x0a, 0xd1, 0x3f, 0x43, ++ 0x3d, 0x13, 0x22, 0xbf, 0x7a, 0xeb, 0x15, 0xbd, 0x3e, 0xa9, 0x10, 0x7a, ++ 0xb4, 0x82, 0x85, 0xc5, 0x6d, 0x5b, 0xf4, 0xfa, 0xcd, 0x13, 0x63, 0xa7, ++ 0x75, 0x2d, 0x84, 0x71, 0x51, 0x5f, 0x06, 0xe7, 0x05, 0xf6, 0x31, 0xc0, ++ 0xac, 0xd2, 0xeb, 0xdf, 0x3d, 0x8d, 0xe6, 0xad, 0xb8, 0xfd, 0x11, 0xe6, ++ 0x51, 0xc5, 0xba, 0x03, 0x78, 0x9e, 0xae, 0x7a, 0x8b, 0xe2, 0x0e, 0xb0, ++ 0xde, 0xf3, 0x0a, 0x5f, 0xc7, 0x85, 0xce, 0xb3, 0xd2, 0x3d, 0x7d, 0x62, ++ 0x7c, 0x6e, 0xc8, 0xb8, 0x61, 0xf3, 0x96, 0xf0, 0xa6, 0xc0, 0x6f, 0x08, ++ 0x1e, 0x24, 0xdc, 0x2b, 0x7d, 0x1c, 0x9e, 0x95, 0xed, 0x0a, 0xe1, 0xeb, ++ 0x33, 0x61, 0x97, 0xc1, 0x1f, 0xc5, 0x9b, 0x25, 0xde, 0xab, 0x98, 0x67, ++ 0x1a, 0x9e, 0x37, 0xa8, 0x7a, 0x08, 0xe4, 0x65, 0x4e, 0x90, 0x0e, 0x7a, ++ 0xf4, 0xfe, 0x56, 0xbf, 0x19, 0xed, 0xde, 0xe3, 0xac, 0x25, 0xd6, 0x06, ++ 0x74, 0xbf, 0x78, 0xdd, 0xd6, 0x99, 0x57, 0x60, 0xbb, 0xf5, 0xef, 0x93, ++ 0x7f, 0x51, 0xea, 0x0c, 0x0c, 0x32, 0xc4, 0x83, 0x7f, 0xe7, 0xeb, 0x58, ++ 0x53, 0x9c, 0xd5, 0xdb, 0x4e, 0x08, 0xb7, 0x0f, 0x7e, 0x2c, 0xf8, 0xe0, ++ 0xec, 0x8d, 0x79, 0xa2, 0x1d, 0xc0, 0xa3, 0x62, 0xa3, 0xaa, 0x45, 0x8d, ++ 0xd0, 0xd5, 0xa3, 0xf6, 0xd2, 0x3e, 0x98, 0xef, 0xf3, 0x99, 0x31, 0x9e, ++ 0x39, 0x5f, 0xc4, 0x09, 0xcf, 0x37, 0xcf, 0x1a, 0xac, 0x37, 0xea, 0x42, ++ 0xe6, 0x1b, 0xd9, 0x9e, 0xf9, 0xdf, 0xce, 0xfb, 0x85, 0x24, 0xe1, 0x3f, ++ 0xf5, 0xb2, 0x87, 0x06, 0x45, 0xf4, 0xa3, 0x7a, 0xec, 0xa0, 0xf3, 0xe8, ++ 0xdf, 0x8f, 0x4c, 0x81, 0x2c, 0xd4, 0xbf, 0xdd, 0x59, 0x46, 0xd2, 0x3f, ++ 0x5f, 0x1b, 0xdd, 0x7f, 0x2d, 0x48, 0x44, 0x7d, 0x3c, 0x88, 0xfc, 0x82, ++ 0xbe, 0xe4, 0x6b, 0xa5, 0xd0, 0xc3, 0x15, 0xa8, 0x97, 0x21, 0x3d, 0xbc, ++ 0x6e, 0x5b, 0x2c, 0xfa, 0xed, 0x9f, 0x3d, 0xb4, 0x8d, 0xf6, 0xff, 0xcc, ++ 0xcf, 0x57, 0xc4, 0xa2, 0x5d, 0x7c, 0x78, 0xdd, 0xdc, 0x07, 0x7c, 0xc0, ++ 0x52, 0x87, 0xb7, 0xcc, 0x25, 0x3d, 0x5c, 0xf5, 0x98, 0xd4, 0xc3, 0x5e, ++ 0x73, 0xa8, 0x7e, 0x2f, 0x5a, 0x57, 0xf6, 0xeb, 0x9f, 0x23, 0x7d, 0x6e, ++ 0x8e, 0x72, 0x5b, 0xa0, 0xb8, 0x72, 0x97, 0x57, 0xd8, 0xdd, 0x20, 0xef, ++ 0x50, 0x0e, 0xae, 0xe3, 0xf2, 0x8e, 0x3d, 0xc4, 0xe5, 0x61, 0x15, 0xea, ++ 0xab, 0x61, 0xa4, 0xaf, 0x86, 0x60, 0xbd, 0xbb, 0x2a, 0xbd, 0x43, 0x90, ++ 0xce, 0x43, 0xbe, 0x93, 0x1e, 0xbb, 0x6b, 0xae, 0x77, 0x2c, 0xb5, 0x67, ++ 0x8e, 0x00, 0xfa, 0x5d, 0x20, 0x39, 0x03, 0xa8, 0xaf, 0xa4, 0x3e, 0x95, ++ 0x7a, 0xd6, 0x68, 0xf0, 0x7e, 0x94, 0x84, 0xfc, 0xa3, 0xbe, 0xfd, 0xe7, ++ 0x9f, 0xc2, 0xfa, 0xbf, 0x78, 0x49, 0x25, 0xf7, 0xae, 0x5a, 0xdd, 0x90, ++ 0xed, 0xc0, 0xfd, 0x82, 0x3e, 0xe4, 0xf6, 0xbf, 0x0f, 0x6f, 0x43, 0x0f, ++ 0xbc, 0x73, 0x2e, 0x00, 0xde, 0xe5, 0x08, 0x6f, 0xb2, 0x7f, 0x38, 0xbc, ++ 0x3f, 0x6d, 0xe2, 0x70, 0x3e, 0xd8, 0xcc, 0xe1, 0xbe, 0x7a, 0xcb, 0x80, ++ 0x58, 0xf4, 0x6f, 0x3f, 0x6d, 0x1a, 0x40, 0x76, 0xcf, 0xa7, 0x5b, 0x06, ++ 0x11, 0xbc, 0xe7, 0xad, 0x01, 0x78, 0x93, 0xdd, 0xeb, 0xd2, 0xdb, 0x3d, ++ 0x4d, 0x00, 0x6f, 0xb4, 0xf3, 0x11, 0xde, 0x30, 0x6e, 0xf9, 0x2e, 0x97, ++ 0x80, 0xb7, 0x9b, 0xc3, 0xbb, 0x49, 0xe8, 0x9d, 0x66, 0x9e, 0xce, 0xeb, ++ 0x05, 0x57, 0x1f, 0x9d, 0x1b, 0xbd, 0xeb, 0x69, 0x8b, 0x1b, 0xf5, 0xf9, ++ 0x91, 0xa8, 0x40, 0x12, 0xfa, 0x23, 0x47, 0xb6, 0xaa, 0x0c, 0xf7, 0xe5, ++ 0x7b, 0xec, 0x22, 0x61, 0xbf, 0x48, 0x38, 0x7f, 0xc3, 0x5a, 0x9e, 0x44, ++ 0x3b, 0xaa, 0x97, 0x3d, 0xb3, 0xd6, 0xc2, 0x1c, 0xd0, 0xdf, 0x82, 0x97, ++ 0xed, 0x7e, 0x06, 0xf9, 0x63, 0x4a, 0x41, 0x0a, 0x22, 0xe0, 0x44, 0xcb, ++ 0x1f, 0x62, 0x71, 0xbc, 0xe0, 0xf8, 0x3d, 0x76, 0x8c, 0x23, 0x79, 0x4c, ++ 0x88, 0x1d, 0x73, 0x81, 0xf8, 0x59, 0xc2, 0x3c, 0x74, 0x7e, 0x7d, 0x49, ++ 0xfb, 0x1f, 0xf6, 0xa1, 0x1d, 0xaf, 0x68, 0xdc, 0xaf, 0x5f, 0x62, 0xb5, ++ 0x05, 0x90, 0x6f, 0xc1, 0xdf, 0x39, 0x11, 0x2a, 0xcf, 0x15, 0x17, 0xca, ++ 0x34, 0x8c, 0x93, 0xb8, 0xad, 0x56, 0xa4, 0x83, 0x4c, 0xe6, 0xd2, 0xef, ++ 0x1b, 0x79, 0x19, 0xee, 0x1b, 0x7d, 0x3b, 0xe8, 0xab, 0xdb, 0x96, 0x11, ++ 0x3f, 0x77, 0x0f, 0x0e, 0xdd, 0xd7, 0xa9, 0x89, 0x0e, 0x98, 0x30, 0xbe, ++ 0xd4, 0xbd, 0x55, 0x21, 0x7c, 0x57, 0x2f, 0x2f, 0x88, 0x2d, 0x60, 0xb8, ++ 0x2f, 0x55, 0x4b, 0xf3, 0x18, 0x9e, 0xcc, 0xf5, 0xb1, 0xa2, 0x69, 0x14, ++ 0x37, 0xb4, 0x00, 0xdd, 0x44, 0xc3, 0x78, 0xee, 0x64, 0x17, 0xff, 0xee, ++ 0x72, 0xf0, 0x38, 0xe2, 0x7a, 0x18, 0xd7, 0x1e, 0x9c, 0x6f, 0xf8, 0xf7, ++ 0x69, 0x48, 0x7a, 0xa8, 0xcf, 0x6d, 0x06, 0xd2, 0xe7, 0xe1, 0xeb, 0xbf, ++ 0x2d, 0x99, 0xfb, 0x2b, 0xd5, 0xaa, 0x81, 0xfc, 0x8e, 0xc5, 0x66, 0xee, ++ 0x7f, 0xc8, 0xf3, 0x0f, 0x57, 0x8a, 0xf2, 0x2b, 0x93, 0x79, 0xbc, 0xb7, ++ 0x28, 0x99, 0xef, 0x17, 0x9c, 0x8c, 0x62, 0xa4, 0x37, 0x4e, 0xae, 0x8d, ++ 0xf1, 0xd7, 0xd3, 0xfa, 0x26, 0x52, 0x3c, 0xb3, 0x27, 0x7e, 0x22, 0xe1, ++ 0xe6, 0x30, 0x7e, 0xd9, 0x23, 0xaf, 0x90, 0xaf, 0x44, 0xfc, 0x60, 0x3f, ++ 0xb6, 0x81, 0x79, 0xce, 0xb3, 0x88, 0x78, 0x2e, 0xa8, 0x58, 0x6c, 0x7f, ++ 0xab, 0x68, 0x7f, 0x6b, 0xcb, 0x3b, 0xb4, 0x2f, 0x07, 0x9e, 0xcb, 0x13, ++ 0xa8, 0x77, 0xe7, 0xac, 0xb0, 0xb8, 0xd1, 0x7e, 0xf5, 0xbd, 0x66, 0x21, ++ 0xba, 0xbb, 0x27, 0x9a, 0xef, 0xa3, 0xb0, 0xc4, 0x38, 0x23, 0xf2, 0xd1, ++ 0x2d, 0x42, 0xce, 0xde, 0xda, 0x72, 0x9f, 0x07, 0xcf, 0x3d, 0xcc, 0x69, ++ 0x89, 0xd1, 0x30, 0x85, 0x71, 0x7c, 0x4c, 0xc4, 0x4f, 0x73, 0x71, 0x1f, ++ 0x36, 0xdd, 0x4c, 0xf1, 0xd3, 0x52, 0x6b, 0xd7, 0xf3, 0xe8, 0x66, 0xdf, ++ 0x9e, 0x7a, 0xf0, 0x4e, 0x2b, 0x2c, 0xad, 0xde, 0xc0, 0xed, 0x96, 0x7a, ++ 0x27, 0xa3, 0xf3, 0x23, 0x97, 0x83, 0xd9, 0x8e, 0xf1, 0x58, 0x28, 0xda, ++ 0x7e, 0x36, 0xe1, 0x5c, 0xf4, 0xa3, 0x8f, 0x0f, 0x2f, 0xc6, 0x38, 0xed, ++ 0x78, 0xc6, 0x09, 0x6b, 0x1c, 0xc1, 0x55, 0x97, 0x5f, 0x6c, 0xe6, 0xe5, ++ 0xcb, 0x93, 0x47, 0x4d, 0x79, 0x28, 0x93, 0xb1, 0x3f, 0x31, 0xd7, 0x70, ++ 0xc4, 0xf7, 0x62, 0x84, 0x0d, 0xd2, 0x43, 0x59, 0x1c, 0xc5, 0x01, 0xae, ++ 0xc7, 0x78, 0xb1, 0x13, 0x53, 0x23, 0xd1, 0xd9, 0x0c, 0x23, 0xf3, 0x19, ++ 0x78, 0xda, 0x84, 0xa1, 0x35, 0x19, 0x3f, 0x9e, 0x26, 0xd6, 0x7d, 0xd3, ++ 0x38, 0x16, 0x88, 0x83, 0xf5, 0x06, 0xf6, 0xea, 0xe3, 0xd7, 0xb3, 0x02, ++ 0x86, 0xc0, 0x10, 0xc0, 0xc3, 0xf5, 0xc6, 0x40, 0x07, 0xd2, 0xb5, 0xc1, ++ 0xea, 0x32, 0xa1, 0x3f, 0xe0, 0x29, 0x56, 0x46, 0xa1, 0x9f, 0xbc, 0x78, ++ 0xe5, 0x85, 0xcd, 0xf7, 0x9e, 0xe4, 0x2b, 0x69, 0xbe, 0x8b, 0x0d, 0x06, ++ 0x3e, 0xcf, 0x9f, 0x2a, 0xfe, 0xa7, 0x00, 0x4e, 0xb7, 0x02, 0x93, 0x23, ++ 0x7d, 0xde, 0x66, 0x64, 0xbb, 0xd4, 0x51, 0x1c, 0x7f, 0x48, 0x7f, 0x35, ++ 0x4e, 0x97, 0x8f, 0xea, 0x2d, 0xe5, 0xf4, 0x2d, 0xe3, 0xe6, 0x12, 0x4f, ++ 0x23, 0xa1, 0xfb, 0x50, 0xf8, 0xde, 0x2a, 0xe6, 0x07, 0xfd, 0x34, 0xc5, ++ 0x62, 0x7b, 0x73, 0xe4, 0xf8, 0xd1, 0x83, 0xc9, 0xd2, 0x0f, 0xe6, 0xf6, ++ 0xe6, 0x22, 0xc1, 0xaf, 0x8b, 0x24, 0xbd, 0x6d, 0xd1, 0xf3, 0xe9, 0x36, ++ 0xe4, 0x17, 0x3c, 0x9f, 0x83, 0x76, 0x2d, 0xc0, 0xed, 0x56, 0x91, 0xf6, ++ 0x45, 0xef, 0xad, 0x82, 0xde, 0x5b, 0x05, 0xbd, 0x3f, 0x29, 0xf2, 0x17, ++ 0x3a, 0x5e, 0xb5, 0x85, 0x05, 0x68, 0xdd, 0xaf, 0x59, 0x08, 0x8f, 0x72, ++ 0xdc, 0xeb, 0x45, 0xfa, 0x42, 0x32, 0xb7, 0x9b, 0xe5, 0x3c, 0x24, 0x3d, ++ 0x33, 0x11, 0x87, 0x32, 0x80, 0xe4, 0x40, 0x3a, 0x3a, 0xd4, 0xd2, 0x40, ++ 0x76, 0xd3, 0xfc, 0xb0, 0x38, 0x30, 0x0b, 0x8d, 0x57, 0xa9, 0x91, 0xf2, ++ 0x3d, 0xf2, 0xc7, 0x70, 0x16, 0x53, 0x73, 0xf7, 0x3c, 0x9c, 0x8f, 0x72, ++ 0x55, 0x94, 0x1b, 0xe9, 0xfa, 0x56, 0x73, 0xeb, 0xa0, 0x5a, 0x5b, 0xef, ++ 0x7a, 0x72, 0x1f, 0xb7, 0x94, 0x75, 0x9a, 0xf8, 0xbd, 0x1b, 0x11, 0xcf, ++ 0x12, 0xfa, 0x6a, 0x92, 0x6a, 0xa3, 0x73, 0x41, 0xa5, 0x4a, 0xb4, 0x1b, ++ 0xed, 0xdf, 0x93, 0x05, 0x76, 0x9f, 0x21, 0x0e, 0xe3, 0x2d, 0x26, 0x42, ++ 0x6d, 0x29, 0xd0, 0x03, 0xca, 0xe7, 0x8f, 0xa2, 0xf8, 0xbe, 0xfd, 0x9c, ++ 0xb8, 0xbb, 0xa6, 0xa1, 0x5d, 0x58, 0x1a, 0x6b, 0x36, 0x62, 0x7a, 0x3b, ++ 0xeb, 0xb4, 0xe7, 0xe4, 0x04, 0xed, 0x92, 0xd5, 0x05, 0x2a, 0xee, 0xc1, ++ 0xc1, 0xc0, 0xd5, 0x53, 0x34, 0xc8, 0x37, 0xa0, 0x3c, 0xe1, 0xf9, 0xfb, ++ 0xb4, 0x4c, 0x8a, 0x0e, 0x89, 0xfc, 0xb2, 0x3f, 0x62, 0xf9, 0x8d, 0xdf, ++ 0x01, 0xfe, 0x29, 0x7f, 0xc7, 0x14, 0x0d, 0xe4, 0xc5, 0xc9, 0x37, 0x45, ++ 0x39, 0x5b, 0x4e, 0xed, 0x4f, 0xae, 0x12, 0x74, 0xec, 0x5b, 0x31, 0x05, ++ 0xf7, 0x39, 0x4e, 0xfe, 0x4a, 0x96, 0xff, 0x9c, 0x97, 0xdf, 0x2b, 0xcb, ++ 0xeb, 0x79, 0xf9, 0xfd, 0xb2, 0x7f, 0x91, 0x5f, 0x1b, 0x56, 0x5e, 0x1f, ++ 0x56, 0xfe, 0x28, 0xcf, 0x77, 0x3d, 0x5c, 0x3f, 0xc5, 0x87, 0x70, 0x12, ++ 0xfb, 0x31, 0xa5, 0xe3, 0x15, 0x92, 0x27, 0x2e, 0x41, 0x67, 0xa5, 0x2b, ++ 0x03, 0x04, 0xdf, 0x52, 0xc3, 0x0e, 0x9e, 0x16, 0xb2, 0x80, 0x21, 0xf7, ++ 0xfc, 0xf5, 0x6c, 0x29, 0x1e, 0x57, 0x32, 0xed, 0x0b, 0x1e, 0xb2, 0xa3, ++ 0xde, 0x4e, 0x48, 0xd3, 0x5c, 0xc9, 0x50, 0xcf, 0x96, 0xe4, 0x3d, 0x8e, ++ 0xdf, 0x17, 0x4e, 0x57, 0x7c, 0x66, 0x94, 0x93, 0x1f, 0xfa, 0x07, 0x0b, ++ 0xb9, 0x1e, 0xf1, 0x5c, 0xad, 0x4b, 0xd0, 0x6d, 0x54, 0x2a, 0xef, 0x4f, ++ 0xc2, 0x1b, 0xfa, 0xf9, 0x1a, 0xfb, 0xbb, 0xd8, 0x7e, 0xd6, 0xe1, 0xbc, ++ 0x92, 0x74, 0xfd, 0x7c, 0xff, 0xef, 0xf4, 0x33, 0x2f, 0xb5, 0x57, 0x3f, ++ 0xe6, 0x94, 0x7f, 0xa3, 0x9f, 0xbd, 0x61, 0xeb, 0x92, 0x76, 0x51, 0x59, ++ 0xba, 0x96, 0x83, 0xfd, 0xb1, 0x43, 0x89, 0xba, 0xf3, 0x65, 0x8b, 0xfe, ++ 0xd3, 0x1d, 0x87, 0x76, 0x15, 0xc3, 0xf3, 0x65, 0x00, 0xfa, 0x45, 0x2b, ++ 0x5b, 0xb3, 0x47, 0x43, 0xff, 0x8b, 0x5e, 0x78, 0x35, 0xbb, 0x32, 0xc4, ++ 0xef, 0x5e, 0x72, 0xc6, 0xc0, 0x34, 0xb0, 0x9f, 0x6a, 0xce, 0x30, 0x4a, ++ 0x8f, 0x77, 0xfc, 0xcd, 0xec, 0x82, 0xf9, 0x2c, 0xd9, 0xde, 0x61, 0x9e, ++ 0x0c, 0xf5, 0x6a, 0x20, 0x2d, 0x0a, 0x99, 0xd7, 0x62, 0x79, 0x4e, 0x92, ++ 0x75, 0x19, 0x67, 0x84, 0xe8, 0xf5, 0xc1, 0x29, 0x06, 0x21, 0x9f, 0xd6, ++ 0xd2, 0x7c, 0x17, 0xbd, 0x70, 0xd4, 0x88, 0xf8, 0x5c, 0x64, 0x68, 0x3d, ++ 0xfc, 0x18, 0xc6, 0x7b, 0xc6, 0x2b, 0x11, 0xf7, 0x5d, 0x63, 0x45, 0xbb, ++ 0xfd, 0x7d, 0xdc, 0xe7, 0x1a, 0x96, 0xc2, 0xe5, 0x9e, 0x27, 0x53, 0xbb, ++ 0x2c, 0x05, 0xcf, 0x45, 0xa0, 0xcc, 0x40, 0x7d, 0xdc, 0x10, 0x79, 0x9f, ++ 0xfe, 0x4e, 0xd1, 0x5f, 0x69, 0x34, 0x97, 0x6f, 0x73, 0xf3, 0xec, 0x56, ++ 0x17, 0xc0, 0x79, 0xcc, 0x87, 0x7c, 0x9f, 0xb9, 0x72, 0x7d, 0xce, 0x28, ++ 0x8c, 0xe3, 0x5e, 0x9e, 0x54, 0x38, 0x06, 0xfb, 0xeb, 0x3b, 0x2e, 0xda, ++ 0xcd, 0xe3, 0xa2, 0xed, 0x3c, 0x2e, 0x5a, 0xea, 0xec, 0x5c, 0x0e, 0xc2, ++ 0x9b, 0xd5, 0xa6, 0x6c, 0xb8, 0xcf, 0x7a, 0x25, 0x63, 0x53, 0x1e, 0x91, ++ 0x7c, 0x06, 0x2c, 0x0b, 0x6d, 0x8b, 0x2d, 0x32, 0xdf, 0x36, 0x65, 0x62, ++ 0x3e, 0xc5, 0xb9, 0x28, 0x7f, 0xc3, 0x23, 0x5b, 0xef, 0x43, 0xbe, 0xd9, ++ 0x13, 0xcd, 0xcf, 0x4d, 0xcc, 0x19, 0x3b, 0x3c, 0x1a, 0xe5, 0x42, 0x57, ++ 0x4e, 0x8c, 0xc1, 0x01, 0xf2, 0x62, 0x5c, 0x62, 0x59, 0x2d, 0xe2, 0x6f, ++ 0xce, 0xd8, 0x2b, 0x27, 0xe3, 0xf7, 0x02, 0x8b, 0x7d, 0x70, 0x19, 0x8f, ++ 0xab, 0x13, 0x5d, 0x8c, 0x4b, 0xf4, 0x4c, 0xc1, 0x72, 0xac, 0x8f, 0x71, ++ 0x0d, 0xaf, 0x99, 0xc7, 0xb9, 0xbc, 0x6f, 0xa9, 0x14, 0xe7, 0xf2, 0x8e, ++ 0x88, 0xf1, 0x46, 0xda, 0x47, 0xbe, 0x56, 0xc0, 0xa1, 0x36, 0x85, 0x9f, ++ 0x73, 0xdd, 0x03, 0x68, 0x46, 0xbb, 0x43, 0xce, 0x43, 0x8e, 0x0f, 0x86, ++ 0xca, 0xf2, 0x4e, 0xe8, 0xef, 0xd0, 0xca, 0xb4, 0x91, 0x6b, 0x5c, 0xb8, ++ 0xdf, 0x51, 0x50, 0x43, 0xf4, 0x24, 0xc6, 0xff, 0x65, 0xa2, 0xb7, 0x34, ++ 0x74, 0x7c, 0x58, 0xee, 0x08, 0xfc, 0x7e, 0xa1, 0xf3, 0xb8, 0x39, 0x85, ++ 0xd3, 0x6f, 0x0d, 0xe2, 0x0d, 0xf1, 0x98, 0xaf, 0x32, 0x2d, 0xc4, 0x5f, ++ 0x9c, 0x31, 0x31, 0x46, 0x97, 0xbf, 0x71, 0x6a, 0x02, 0xd3, 0x42, 0xe3, ++ 0xad, 0x37, 0x66, 0xe8, 0xf2, 0xb3, 0x4b, 0x07, 0xe8, 0xea, 0xdf, 0x32, ++ 0xef, 0x32, 0x5d, 0x79, 0x89, 0xa5, 0x33, 0xb7, 0xf6, 0x22, 0xec, 0xdf, ++ 0x1a, 0xbb, 0x3d, 0x1a, 0xed, 0xb0, 0x8f, 0xdb, 0xbf, 0xf9, 0xcb, 0xad, ++ 0x68, 0xd7, 0x6d, 0x54, 0xdd, 0x0a, 0xac, 0x67, 0xc1, 0x6b, 0x9b, 0xfe, ++ 0x32, 0x01, 0x6a, 0x9d, 0xc2, 0xe3, 0x97, 0xfc, 0xfe, 0x14, 0xc5, 0xbd, ++ 0x8e, 0xe1, 0x79, 0x36, 0xe4, 0x3d, 0xa3, 0x66, 0x0c, 0xdd, 0xaf, 0xf9, ++ 0x82, 0x75, 0xd2, 0xb9, 0xc0, 0x90, 0xfd, 0x00, 0xdd, 0xbe, 0xcb, 0x22, ++ 0xc7, 0x2e, 0x3a, 0xaf, 0xfa, 0x63, 0xed, 0xd7, 0x3c, 0x90, 0x22, 0xfc, ++ 0xdf, 0x51, 0x6c, 0x14, 0xea, 0xbf, 0x53, 0xb5, 0x7f, 0xa6, 0x38, 0xdb, ++ 0x12, 0x1b, 0x5f, 0xcf, 0x17, 0xaf, 0x1e, 0x30, 0xe3, 0x39, 0x06, 0x3c, ++ 0x17, 0x70, 0x16, 0xe8, 0xfb, 0x1a, 0x6c, 0xa8, 0x22, 0x9f, 0xfb, 0x28, ++ 0x0e, 0x5d, 0xd4, 0x76, 0xc0, 0x8c, 0xfe, 0x91, 0x3b, 0x85, 0xcb, 0xe5, ++ 0x25, 0x99, 0x4b, 0x8d, 0x60, 0x91, 0xb1, 0x1a, 0x48, 0x51, 0x6f, 0x4c, ++ 0x06, 0xf9, 0x14, 0x07, 0xf4, 0xd1, 0xd9, 0xc1, 0x86, 0x6f, 0xc7, 0x73, ++ 0x13, 0x39, 0x76, 0x3a, 0x07, 0x5e, 0x7d, 0x66, 0x06, 0x08, 0x69, 0xa4, ++ 0x23, 0xdf, 0xb0, 0xa5, 0x50, 0x6f, 0x51, 0x53, 0x31, 0xe5, 0x97, 0x9c, ++ 0x89, 0xa6, 0x7e, 0xdf, 0x53, 0x3b, 0x27, 0xd3, 0x79, 0xe4, 0x57, 0x14, ++ 0xda, 0x2f, 0x28, 0xc9, 0x98, 0xb3, 0x12, 0xed, 0x51, 0xac, 0x7f, 0x07, ++ 0x8c, 0x57, 0xf2, 0xe2, 0x35, 0xc5, 0x08, 0x9f, 0x25, 0xdb, 0xf9, 0xbd, ++ 0xa7, 0x12, 0xf5, 0x4f, 0xb9, 0xd8, 0xcf, 0xe2, 0x96, 0x62, 0x6a, 0x5f, ++ 0xa2, 0xb2, 0x3d, 0x0a, 0xd8, 0x07, 0x53, 0x8a, 0xb8, 0x9e, 0x2d, 0x41, ++ 0xdd, 0x0e, 0x79, 0x35, 0xcf, 0xbe, 0x06, 0xf5, 0xab, 0x6a, 0x0e, 0x0c, ++ 0x7e, 0x1c, 0xe5, 0x89, 0xd9, 0x4e, 0xf2, 0x24, 0xee, 0xcc, 0x2d, 0x34, ++ 0x7e, 0xcd, 0x19, 0x2b, 0xb5, 0xff, 0xad, 0x90, 0x17, 0xa6, 0x2e, 0x3e, ++ 0xaf, 0x49, 0x67, 0x3c, 0xf4, 0x5d, 0xe2, 0xbd, 0x3d, 0x85, 0xef, 0x03, ++ 0xca, 0xbc, 0x29, 0x69, 0xa3, 0x11, 0xef, 0x15, 0x98, 0xba, 0x18, 0xd5, ++ 0xbf, 0xee, 0xcc, 0xa5, 0x94, 0xca, 0x75, 0xbe, 0x35, 0xf4, 0xe9, 0x44, ++ 0x94, 0x63, 0xa6, 0xa4, 0xaf, 0x27, 0x67, 0x00, 0x7d, 0xbc, 0x95, 0xa8, ++ 0x38, 0xc8, 0xdc, 0x08, 0x93, 0xb7, 0xa7, 0x6b, 0xc7, 0xc6, 0xb1, 0x08, ++ 0xf2, 0xa8, 0x67, 0x9c, 0x33, 0xfc, 0xfc, 0xae, 0xe5, 0x0c, 0x3f, 0xcf, ++ 0xdb, 0x9e, 0xa6, 0xfd, 0x09, 0xf9, 0x6a, 0xda, 0xdd, 0x5d, 0x46, 0xdc, ++ 0xbf, 0x61, 0x36, 0xab, 0x03, 0xe1, 0x35, 0x6d, 0xdc, 0x48, 0x57, 0x65, ++ 0x08, 0x1f, 0xa9, 0x3b, 0x6e, 0x36, 0x23, 0x5e, 0x4c, 0x0f, 0xbd, 0x6f, ++ 0x46, 0x7d, 0x6c, 0x81, 0xb4, 0x28, 0xa4, 0xbc, 0x5a, 0x9e, 0x3b, 0x0f, ++ 0x93, 0xc7, 0xfb, 0x04, 0xdf, 0xc9, 0x7b, 0x07, 0x52, 0xbf, 0x30, 0xdf, ++ 0x6c, 0xb2, 0x47, 0x6f, 0x13, 0xfe, 0xb7, 0xe4, 0x93, 0x37, 0x45, 0x7d, ++ 0xd9, 0xbe, 0x13, 0x69, 0x1c, 0xf1, 0xf8, 0xb2, 0x85, 0xfc, 0xa7, 0x3f, ++ 0xa7, 0x79, 0x8f, 0xa3, 0xbc, 0xec, 0x2c, 0x60, 0xb3, 0x5f, 0x22, 0xf9, ++ 0xd8, 0x99, 0x8d, 0xfb, 0x26, 0x3f, 0xd6, 0xfc, 0x01, 0xcf, 0x56, 0x85, ++ 0xec, 0xfb, 0x2e, 0x3a, 0xcf, 0x3e, 0x6d, 0x9c, 0xcb, 0x80, 0xfb, 0x01, ++ 0xdd, 0x3d, 0xeb, 0xe0, 0xfc, 0x7a, 0xbe, 0x75, 0x7c, 0x2c, 0xea, 0xbf, ++ 0xa7, 0xb2, 0x15, 0xd8, 0xef, 0x7b, 0x57, 0x5f, 0xdd, 0xa9, 0x41, 0x7f, ++ 0x1d, 0x3f, 0x1b, 0x3d, 0x1a, 0xe5, 0xbe, 0x1c, 0x57, 0x49, 0xe5, 0xf7, ++ 0x70, 0x98, 0xa3, 0xfb, 0x3b, 0xf4, 0xe7, 0x6a, 0x5e, 0x8f, 0x71, 0x21, ++ 0x5f, 0x97, 0xa0, 0x73, 0x94, 0x1b, 0xb4, 0x63, 0xe1, 0x3b, 0xc3, 0xf8, ++ 0x5f, 0xcd, 0xeb, 0x96, 0xa7, 0x14, 0x28, 0xaf, 0x89, 0x05, 0x7f, 0x16, ++ 0xc6, 0x2f, 0x7a, 0x23, 0x2a, 0x80, 0x74, 0xdc, 0xf1, 0x46, 0x94, 0x11, ++ 0xf5, 0x43, 0x7d, 0xa6, 0x57, 0x49, 0x1d, 0x83, 0xdf, 0x87, 0x4c, 0x44, ++ 0xff, 0x4d, 0x6b, 0xb7, 0x18, 0x19, 0xd9, 0x37, 0x9a, 0x01, 0xbf, 0xf7, ++ 0x35, 0xdf, 0xf3, 0xc9, 0xa7, 0x70, 0x3a, 0x93, 0x7c, 0xe9, 0x6d, 0xe2, ++ 0xfc, 0x52, 0x26, 0xe8, 0xb4, 0x5c, 0xf0, 0x9f, 0x57, 0xf0, 0xd1, 0xe9, ++ 0xda, 0x14, 0xe2, 0xc3, 0xd3, 0x77, 0xc3, 0xa4, 0x71, 0x9f, 0xf3, 0x6e, ++ 0x65, 0xf8, 0x76, 0xb4, 0x07, 0x5c, 0x76, 0xf7, 0x20, 0x57, 0x90, 0x2f, ++ 0x4b, 0xd0, 0xef, 0x81, 0xef, 0x25, 0x97, 0xc5, 0x93, 0xff, 0x17, 0xc2, ++ 0x77, 0xc4, 0x87, 0x8b, 0xcf, 0x38, 0xa8, 0xbf, 0xea, 0x33, 0x2e, 0xc1, ++ 0xe7, 0x4e, 0xca, 0x4b, 0x7e, 0x2b, 0x17, 0xfc, 0x62, 0x11, 0x76, 0xc4, ++ 0x3c, 0x41, 0xdf, 0x49, 0xe9, 0xde, 0x91, 0xa9, 0x30, 0xff, 0x92, 0x06, ++ 0xe0, 0x77, 0x18, 0xc7, 0xbb, 0x32, 0x2d, 0x17, 0xf9, 0x28, 0x48, 0x2f, ++ 0x66, 0x07, 0xd2, 0x15, 0xd0, 0x4b, 0x6a, 0x65, 0x08, 0xdf, 0x34, 0x74, ++ 0xdc, 0xcc, 0xd0, 0xfe, 0xb0, 0x24, 0x7a, 0x88, 0x5e, 0xe6, 0x41, 0x1a, ++ 0x6a, 0x7f, 0x54, 0xf4, 0xd8, 0x1f, 0x8e, 0xc9, 0xc9, 0x30, 0xef, 0x69, ++ 0x8d, 0x39, 0xba, 0x7b, 0x16, 0x79, 0xa9, 0x17, 0x47, 0xf7, 0x03, 0x52, ++ 0xc5, 0xbe, 0xbc, 0x2d, 0x30, 0x08, 0xed, 0x55, 0x53, 0x6d, 0x94, 0x1b, ++ 0xef, 0x83, 0x9d, 0x4a, 0xe4, 0xfb, 0x33, 0xcb, 0xee, 0xe5, 0xf0, 0x5b, ++ 0x66, 0xf2, 0x14, 0xa1, 0xfd, 0xb0, 0xec, 0x51, 0xc5, 0x0d, 0x98, 0x21, ++ 0xbb, 0x02, 0xe5, 0x51, 0xde, 0xbe, 0x5a, 0x73, 0x68, 0xbc, 0xf1, 0xe6, ++ 0x33, 0x23, 0x98, 0x0b, 0xe0, 0x70, 0xc3, 0x99, 0x81, 0x94, 0x5e, 0x9e, ++ 0xe4, 0x9d, 0x88, 0xf8, 0x2f, 0x3b, 0x33, 0x53, 0xc0, 0x6b, 0xc4, 0xbf, ++ 0xb5, 0x0f, 0x38, 0x46, 0xe3, 0xf1, 0x25, 0x93, 0xdf, 0xe2, 0xde, 0x80, ++ 0xfb, 0x6c, 0x51, 0x5e, 0x15, 0xf1, 0x7b, 0x24, 0x8b, 0x39, 0x1e, 0x0c, ++ 0x89, 0x2f, 0x61, 0x3c, 0x0c, 0xe3, 0x62, 0x72, 0x7f, 0x50, 0xc6, 0x9b, ++ 0x2c, 0xb8, 0x9f, 0x1a, 0xa2, 0x27, 0xbf, 0x31, 0xb6, 0x64, 0xa3, 0xbf, ++ 0xd3, 0x2b, 0xee, 0x54, 0xa0, 0xdf, 0x47, 0x5b, 0xdc, 0xf1, 0xa7, 0x3c, ++ 0x03, 0x94, 0x1f, 0xcb, 0xd1, 0x28, 0xfe, 0x34, 0xc7, 0xe0, 0xbd, 0x0d, ++ 0xf1, 0xba, 0x70, 0x86, 0xff, 0x05, 0x13, 0xe4, 0x17, 0xdd, 0xbf, 0x2d, ++ 0x16, 0xe3, 0xdd, 0x12, 0x9e, 0xad, 0xc6, 0xc0, 0x20, 0xd4, 0x93, 0xad, ++ 0x00, 0x47, 0x8c, 0x83, 0xb5, 0x36, 0xab, 0xc5, 0x7e, 0x6e, 0xcf, 0xc4, ++ 0xf0, 0xfd, 0x2f, 0x4e, 0xd7, 0x92, 0x8e, 0xc3, 0xe9, 0x7b, 0xe1, 0x99, ++ 0xfe, 0x44, 0x4f, 0xa7, 0x6b, 0x2d, 0xa4, 0x77, 0x4e, 0x03, 0xbd, 0xb2, ++ 0x10, 0xbd, 0x23, 0xf5, 0x8d, 0x94, 0xef, 0x52, 0xef, 0x48, 0x7a, 0xae, ++ 0x36, 0x72, 0xb9, 0x55, 0x6d, 0x8b, 0xa3, 0x73, 0x15, 0x41, 0x7d, 0x33, ++ 0xdd, 0x83, 0x71, 0x5c, 0x36, 0x94, 0x9f, 0x7f, 0x0b, 0xea, 0x9b, 0xa7, ++ 0x1e, 0x18, 0x8f, 0xf4, 0x7f, 0x32, 0x91, 0xce, 0x35, 0x87, 0xd3, 0xff, ++ 0x2b, 0x75, 0xa9, 0x74, 0xce, 0x46, 0xea, 0x91, 0x70, 0x7d, 0x23, 0xe5, ++ 0xb9, 0x94, 0xef, 0x52, 0x5f, 0xdd, 0x95, 0xe6, 0x5d, 0x8b, 0x70, 0x2a, ++ 0x7c, 0xee, 0xbf, 0xb7, 0xfd, 0x1d, 0x3e, 0x5d, 0x67, 0xe4, 0x7a, 0xeb, ++ 0x3a, 0xa3, 0x9d, 0xe8, 0xe7, 0xc2, 0xe5, 0xe6, 0x01, 0x21, 0x37, 0x0f, ++ 0xe8, 0xe4, 0xe6, 0x92, 0x3e, 0xe4, 0xfe, 0xc3, 0x17, 0x49, 0xff, 0x8d, ++ 0xa2, 0x3e, 0xd8, 0xaf, 0x64, 0x17, 0xa2, 0x5c, 0x0f, 0xed, 0xef, 0xcf, ++ 0x69, 0x85, 0xbf, 0x41, 0xfa, 0x7d, 0x21, 0x95, 0xeb, 0xd5, 0x1f, 0x6b, ++ 0xde, 0x7d, 0xc9, 0xfb, 0x17, 0x52, 0xa5, 0x1f, 0x71, 0x61, 0xf2, 0xfe, ++ 0x71, 0x51, 0xff, 0x7c, 0xf2, 0xbe, 0x43, 0xc8, 0xfb, 0x70, 0xf9, 0xce, ++ 0xa0, 0x3f, 0x94, 0xef, 0x27, 0x5f, 0xbb, 0x84, 0xf6, 0xa7, 0xf7, 0x33, ++ 0xd0, 0x07, 0xa8, 0xf7, 0xda, 0x63, 0x5c, 0x9b, 0x84, 0xfc, 0x27, 0xfd, ++ 0x10, 0x1d, 0xe7, 0x3f, 0x97, 0xfc, 0xf7, 0x64, 0xce, 0xed, 0xe8, 0x43, ++ 0xfe, 0xef, 0xf8, 0xdf, 0xc8, 0x7f, 0x49, 0x8f, 0x92, 0x5f, 0x24, 0x7f, ++ 0x48, 0x7e, 0x08, 0xe7, 0x1f, 0xc9, 0x0f, 0x53, 0xee, 0x03, 0xff, 0x0f, ++ 0xf1, 0xf4, 0x1e, 0xbf, 0x5f, 0x54, 0x6d, 0xf4, 0x6d, 0xa1, 0xfd, 0x43, ++ 0x57, 0xcc, 0x48, 0xe4, 0xcb, 0x1e, 0xbb, 0x6d, 0xbb, 0x42, 0x7c, 0xd6, ++ 0x4b, 0x2f, 0x08, 0xbe, 0x09, 0xf2, 0x89, 0x5e, 0x4f, 0x48, 0xbe, 0x90, ++ 0x7c, 0x22, 0xf9, 0xa3, 0x5a, 0xf0, 0x43, 0x45, 0x18, 0x3f, 0xec, 0x54, ++ 0x5b, 0x1f, 0x1c, 0x0f, 0xed, 0x6e, 0x4e, 0xf3, 0x9e, 0x0e, 0xe5, 0x8b, ++ 0xc5, 0x2f, 0x85, 0xeb, 0x85, 0x3e, 0xe9, 0x0a, 0x23, 0x86, 0xac, 0x22, ++ 0xb1, 0x96, 0x21, 0x5d, 0x55, 0x43, 0x1a, 0x4a, 0x57, 0x96, 0x3e, 0xf8, ++ 0xe1, 0x4c, 0x0f, 0x3d, 0x5d, 0x18, 0x3f, 0x1c, 0xbe, 0x40, 0x7a, 0x8a, ++ 0x49, 0x33, 0x53, 0xbd, 0xff, 0x43, 0x7a, 0x8a, 0x49, 0x4b, 0x8a, 0x48, ++ 0x4f, 0xb6, 0xb4, 0x1f, 0xd1, 0x9e, 0x38, 0x5d, 0xfb, 0xd7, 0x5c, 0x17, ++ 0xcc, 0xe7, 0x74, 0x2e, 0xc8, 0xd9, 0x9c, 0x20, 0xbd, 0x4d, 0xf9, 0x23, ++ 0xe3, 0xf6, 0xc2, 0x00, 0x6e, 0xf7, 0xef, 0x89, 0xe6, 0xeb, 0xdc, 0x63, ++ 0xce, 0xa2, 0x78, 0xce, 0x94, 0xb3, 0xfc, 0x5c, 0xab, 0xa4, 0x4b, 0x89, ++ 0x67, 0x69, 0x07, 0x54, 0x88, 0x78, 0x42, 0x71, 0xba, 0xc7, 0x8d, 0xf3, ++ 0x95, 0xfe, 0xc2, 0x85, 0xe2, 0xd9, 0x92, 0xd8, 0x69, 0x46, 0x3f, 0xa4, ++ 0x02, 0xd2, 0x50, 0xfd, 0xdf, 0x97, 0xbd, 0x3b, 0x26, 0xed, 0xe2, 0xf0, ++ 0x3c, 0x20, 0xed, 0xc2, 0xec, 0xc4, 0xc9, 0x02, 0xcf, 0x3f, 0xa2, 0x9d, ++ 0x38, 0x3d, 0x12, 0x5e, 0x99, 0xc3, 0xa9, 0x8b, 0x43, 0x80, 0xfe, 0xbb, ++ 0x81, 0xec, 0xb7, 0x80, 0x91, 0x8e, 0xc8, 0xf4, 0xe9, 0x57, 0xac, 0xe3, ++ 0x70, 0x96, 0xf9, 0x55, 0x01, 0xa3, 0xd4, 0xb7, 0x09, 0xa8, 0x6f, 0x81, ++ 0x5e, 0x66, 0xe0, 0x78, 0xff, 0x2e, 0xbd, 0x94, 0x14, 0x31, 0x11, 0x0f, ++ 0x7c, 0x79, 0xaa, 0x96, 0x0f, 0x78, 0xff, 0x85, 0xc8, 0xb3, 0x57, 0xa7, ++ 0x22, 0x7e, 0x66, 0x8e, 0x93, 0xe5, 0xbf, 0x6d, 0xd6, 0x06, 0xa2, 0xdc, ++ 0x61, 0x32, 0x8e, 0x4e, 0x71, 0x91, 0xf7, 0x54, 0x91, 0xf7, 0xbd, 0xf2, ++ 0xf6, 0x44, 0xa8, 0x3f, 0xe5, 0x41, 0x16, 0x8c, 0xb3, 0x43, 0xf9, 0xa4, ++ 0xfc, 0xb8, 0x9e, 0x38, 0x8a, 0xc2, 0x82, 0xf5, 0x97, 0x3e, 0xba, 0xfd, ++ 0xed, 0x66, 0xc2, 0x33, 0x3f, 0xf7, 0xc2, 0xbc, 0x5d, 0x46, 0xbe, 0xcf, ++ 0x24, 0xf2, 0xb9, 0x90, 0xb7, 0x87, 0xe4, 0xc7, 0x85, 0xe5, 0xd7, 0xf3, ++ 0xfa, 0xb1, 0xc6, 0x2e, 0xc6, 0xcf, 0x29, 0xfa, 0x39, 0xbf, 0xaa, 0xb8, ++ 0xf5, 0xc6, 0xe9, 0xc7, 0x13, 0x62, 0x8f, 0x00, 0x26, 0x27, 0xe3, 0x79, ++ 0x82, 0x69, 0xdb, 0x15, 0x07, 0xc6, 0x41, 0x6e, 0xc9, 0x3f, 0x49, 0xfb, ++ 0xb1, 0xc1, 0xf5, 0xbf, 0x41, 0xeb, 0x5f, 0xd2, 0xae, 0x88, 0xfc, 0xce, ++ 0xb7, 0x71, 0xbd, 0xb7, 0x6c, 0xe7, 0xf9, 0x47, 0x1e, 0xfd, 0x43, 0xb3, ++ 0x6f, 0xa0, 0xe8, 0x2f, 0x99, 0xe2, 0x64, 0xf4, 0x67, 0x6a, 0x55, 0x34, ++ 0x3c, 0xff, 0xb0, 0x78, 0x9c, 0xe2, 0xef, 0x9f, 0xd3, 0x1b, 0xce, 0x8f, ++ 0xa4, 0xe9, 0xfd, 0x1b, 0xfc, 0x33, 0xea, 0xdb, 0x33, 0x3c, 0x7f, 0x77, ++ 0x31, 0xed, 0x11, 0xcf, 0xd4, 0xbe, 0x3f, 0xb5, 0x0f, 0x58, 0x2e, 0x62, ++ 0xfc, 0x59, 0xf9, 0x91, 0xef, 0x3d, 0xfc, 0x97, 0xac, 0x27, 0xe2, 0x09, ++ 0xd4, 0x3f, 0xc0, 0xf2, 0x86, 0xd6, 0xc8, 0xef, 0x97, 0xbc, 0x28, 0xf8, ++ 0xb1, 0x13, 0xf7, 0x4d, 0x08, 0x5e, 0x1f, 0x35, 0x23, 0xfc, 0x3a, 0xcd, ++ 0x12, 0x9e, 0xff, 0x68, 0xc6, 0x78, 0x37, 0xdd, 0x9f, 0x81, 0xfc, 0xab, ++ 0x8f, 0xfe, 0x63, 0xaa, 0x6f, 0x18, 0x9f, 0xbe, 0x16, 0xb6, 0xfe, 0x73, ++ 0xcd, 0xff, 0xf1, 0x08, 0xeb, 0x77, 0xe9, 0xdb, 0x07, 0xce, 0x05, 0xbf, ++ 0x0d, 0xbd, 0xda, 0x0b, 0xfa, 0x99, 0xaf, 0xa7, 0xa7, 0x38, 0xa3, 0x67, ++ 0xd7, 0x69, 0xe8, 0x27, 0x0e, 0xfc, 0x7f, 0xb4, 0x8b, 0x97, 0x78, 0xa2, ++ 0x9a, 0xd1, 0xfe, 0x0f, 0xd2, 0xc7, 0x61, 0xa2, 0x8f, 0x4e, 0x19, 0xcf, ++ 0xef, 0x45, 0xff, 0x9f, 0x4f, 0x9d, 0x68, 0x23, 0xfb, 0x47, 0xd4, 0x3f, ++ 0xda, 0x8c, 0x7a, 0xcc, 0x63, 0xe8, 0xa9, 0xcf, 0xf9, 0x41, 0xd2, 0x17, ++ 0x5e, 0x05, 0xc2, 0xb3, 0x73, 0x8c, 0xb7, 0xff, 0xe0, 0xd1, 0x23, 0xcd, ++ 0x08, 0x1f, 0xc0, 0x0f, 0x95, 0x53, 0xde, 0x78, 0x0e, 0x7e, 0x68, 0x0d, ++ 0xcb, 0xe7, 0x87, 0xf1, 0x8f, 0xa0, 0x7f, 0xe2, 0x5f, 0x94, 0xf3, 0x00, ++ 0x9f, 0x41, 0x11, 0xe4, 0xcc, 0x29, 0x01, 0x9f, 0x2f, 0xc4, 0xb9, 0xea, ++ 0xce, 0x42, 0x6e, 0x27, 0x76, 0xf6, 0xe7, 0xa9, 0x33, 0x9d, 0xdb, 0x85, ++ 0xff, 0x12, 0xf8, 0x36, 0xa4, 0xf3, 0xfa, 0x9d, 0xd1, 0x21, 0x70, 0x08, ++ 0xc1, 0x33, 0xfc, 0x05, 0xd0, 0x0f, 0x09, 0x59, 0x37, 0xc1, 0xe9, 0xe6, ++ 0x44, 0xb9, 0xee, 0xa8, 0x92, 0xa9, 0xb0, 0xae, 0x4e, 0x27, 0x2f, 0xb7, ++ 0xa5, 0x9b, 0xee, 0xf7, 0xe5, 0x07, 0xf3, 0xe1, 0xfd, 0xc5, 0xa6, 0x47, ++ 0x95, 0x20, 0x5c, 0x82, 0xfd, 0x5b, 0xde, 0x41, 0xb9, 0x74, 0xb3, 0x80, ++ 0x9b, 0x33, 0xdd, 0xfa, 0x8e, 0x8f, 0xcb, 0x43, 0x05, 0xf9, 0xb2, 0x9a, ++ 0x08, 0x04, 0xe8, 0x62, 0xbb, 0xe2, 0x53, 0xd1, 0x4f, 0x40, 0xba, 0x88, ++ 0xb0, 0xee, 0xbf, 0xf7, 0xa6, 0x2b, 0x5f, 0x58, 0x7b, 0xcd, 0x74, 0x8e, ++ 0xf6, 0x5d, 0xbd, 0xdb, 0x6b, 0x61, 0xed, 0x99, 0x29, 0xf7, 0x62, 0xda, ++ 0x0b, 0xbc, 0x4d, 0x0d, 0xc3, 0x6b, 0x71, 0x18, 0x5e, 0x27, 0x86, 0xe5, ++ 0x4b, 0x65, 0xde, 0xaf, 0x93, 0x7f, 0x52, 0x2e, 0x96, 0xb7, 0xad, 0x5d, ++ 0x95, 0x9c, 0x88, 0x71, 0x49, 0x85, 0xee, 0x8a, 0x06, 0xe9, 0x39, 0xa5, ++ 0x04, 0xe9, 0x79, 0x91, 0x43, 0xd2, 0x6f, 0x2a, 0xc1, 0x35, 0x48, 0xcf, ++ 0x69, 0xef, 0x20, 0xfd, 0xce, 0x68, 0x95, 0xf2, 0x30, 0xfd, 0x7e, 0x0d, ++ 0xf0, 0x36, 0x1d, 0xe5, 0xe1, 0xf8, 0x60, 0xfe, 0x06, 0x94, 0x17, 0x94, ++ 0xcf, 0x28, 0xd1, 0xe2, 0x42, 0xf5, 0x45, 0x26, 0x95, 0xcf, 0x6a, 0x92, ++ 0xf5, 0xb3, 0xee, 0x27, 0x79, 0xda, 0x28, 0xfb, 0xcb, 0xa6, 0xbc, 0xc4, ++ 0x23, 0xf3, 0xf5, 0x2b, 0x21, 0xbc, 0xe6, 0x0a, 0x7d, 0xe1, 0x73, 0xbd, ++ 0x83, 0xe5, 0x0b, 0xdb, 0x79, 0xfb, 0x49, 0x8f, 0xe5, 0xbc, 0x73, 0x4e, ++ 0x7e, 0x68, 0x09, 0x83, 0xcb, 0xfa, 0xb0, 0xbc, 0x2f, 0xac, 0xfe, 0x43, ++ 0xe7, 0xd1, 0x2f, 0x8d, 0x61, 0xed, 0xef, 0x0e, 0x2b, 0x6f, 0x0e, 0xcb, ++ 0xaf, 0x0b, 0xcb, 0x37, 0xe9, 0xdb, 0x97, 0xcd, 0x53, 0x88, 0x0f, 0xcb, ++ 0x80, 0x1e, 0x10, 0x11, 0xe7, 0xe3, 0xcb, 0x9b, 0xd2, 0x7b, 0xec, 0xd4, ++ 0x1e, 0x7d, 0xaa, 0xd8, 0xc8, 0x6e, 0xd3, 0xf1, 0xd5, 0x94, 0x06, 0x9e, ++ 0xbf, 0xfd, 0xb1, 0x11, 0x25, 0x4d, 0xb6, 0x90, 0x7c, 0xba, 0xbb, 0x24, ++ 0x94, 0x2f, 0xe4, 0xbd, 0x60, 0x4b, 0x22, 0x23, 0xbe, 0x30, 0xf5, 0x21, ++ 0x2f, 0x4b, 0xd2, 0xf5, 0xfe, 0x59, 0xcf, 0x7a, 0x86, 0x86, 0xeb, 0x5b, ++ 0x5e, 0xfe, 0x09, 0xfe, 0x33, 0x8d, 0xf6, 0x77, 0x74, 0x76, 0xc1, 0x4e, ++ 0x55, 0x9f, 0xef, 0x50, 0xe5, 0xbc, 0xaf, 0x7a, 0x67, 0xb9, 0x2d, 0x64, ++ 0x1f, 0x94, 0x5d, 0x59, 0x82, 0xf1, 0x95, 0xbe, 0xf7, 0x5b, 0x26, 0x94, ++ 0x4c, 0xcc, 0x0c, 0xb1, 0x4b, 0x7c, 0xe3, 0x4b, 0xb4, 0x90, 0x75, 0xca, ++ 0xfa, 0x93, 0xbf, 0x3f, 0xab, 0xe2, 0x78, 0x77, 0xa6, 0x8f, 0x2f, 0xd9, ++ 0x88, 0xfb, 0x39, 0x85, 0x62, 0x1f, 0xd2, 0xc9, 0x53, 0xd0, 0x6b, 0x2a, ++ 0xea, 0xcd, 0x1a, 0x11, 0x8f, 0x99, 0x8c, 0xe7, 0x63, 0xb1, 0x5e, 0x74, ++ 0x60, 0xd0, 0xb2, 0x50, 0x3b, 0x84, 0xb5, 0x0e, 0xc6, 0x75, 0x76, 0xfc, ++ 0x8c, 0xdf, 0x1b, 0xf0, 0x35, 0x00, 0x7e, 0x30, 0xbe, 0xc6, 0xdc, 0x66, ++ 0x8c, 0xa7, 0x74, 0xc4, 0xc5, 0xad, 0x78, 0x06, 0xea, 0xef, 0xfc, 0x99, ++ 0xba, 0x02, 0xf5, 0xe8, 0xfe, 0x15, 0x09, 0x74, 0x2e, 0xe9, 0x4f, 0xe9, ++ 0xdc, 0xff, 0xdc, 0x19, 0xd7, 0x2f, 0xb9, 0x02, 0xf2, 0x1d, 0x31, 0xb7, ++ 0x9b, 0xf1, 0xbd, 0x92, 0x8e, 0x7b, 0x26, 0x51, 0xba, 0x43, 0xd5, 0x56, ++ 0x77, 0x03, 0xaf, 0x3d, 0xf8, 0xd8, 0xb5, 0x25, 0xb6, 0x4b, 0xb0, 0x3c, ++ 0x8e, 0xe0, 0xf3, 0x8b, 0xf4, 0x49, 0x25, 0xf5, 0x40, 0xd7, 0xbf, 0xc4, ++ 0x4b, 0x3b, 0xd0, 0xde, 0xeb, 0x74, 0x24, 0xe3, 0xbd, 0x06, 0xb6, 0xc6, ++ 0x44, 0xfb, 0x7a, 0x8c, 0xb9, 0x9f, 0x24, 0xba, 0xb9, 0xdf, 0x32, 0x12, ++ 0xfd, 0xe7, 0xb2, 0xfa, 0xcb, 0x68, 0xdf, 0xaa, 0xfc, 0x57, 0xd3, 0x27, ++ 0xd3, 0xbd, 0x85, 0x55, 0x26, 0xda, 0xcf, 0x80, 0x3f, 0x3a, 0x7f, 0xe2, ++ 0x5d, 0x33, 0x89, 0xce, 0x3d, 0xcd, 0x6b, 0x14, 0xa9, 0xef, 0x1a, 0x4a, ++ 0xdf, 0xf8, 0xe1, 0xe9, 0x06, 0xbc, 0x1f, 0xd9, 0xfd, 0x84, 0x42, 0xf7, ++ 0x25, 0xae, 0xfc, 0xba, 0xf5, 0x8f, 0x23, 0xf0, 0xdc, 0x63, 0xd3, 0x00, ++ 0x37, 0xa2, 0xe6, 0x75, 0xb0, 0xeb, 0xf1, 0x3c, 0xd2, 0xa7, 0xeb, 0x86, ++ 0xd0, 0x3d, 0x89, 0x83, 0x51, 0xb5, 0x74, 0xee, 0x13, 0xea, 0x33, 0xac, ++ 0x5f, 0xf5, 0x9d, 0xeb, 0xdd, 0x69, 0xb9, 0x58, 0x5f, 0x75, 0xe0, 0xd1, ++ 0x8a, 0xc3, 0xf0, 0x1d, 0xed, 0xe1, 0xc3, 0xf7, 0xaa, 0x4f, 0xe1, 0xfd, ++ 0xc3, 0xb2, 0x58, 0x7b, 0x34, 0x9e, 0x97, 0x3e, 0xfc, 0xbd, 0xeb, 0x5d, ++ 0xb4, 0x6b, 0xa1, 0xdc, 0xb1, 0x12, 0xbe, 0x1f, 0x5e, 0xb5, 0x20, 0x19, ++ 0xed, 0xac, 0xc3, 0x8a, 0x2b, 0x16, 0xdf, 0x12, 0x79, 0xf1, 0xb1, 0x59, ++ 0x25, 0xa9, 0x69, 0x78, 0x2f, 0xdf, 0x22, 0xf0, 0x39, 0xcb, 0x5e, 0x06, ++ 0x7c, 0x5e, 0x66, 0xe8, 0xa1, 0x17, 0xd2, 0x1f, 0x95, 0xf1, 0x3c, 0xff, ++ 0x62, 0xfa, 0xac, 0x92, 0x4d, 0x30, 0xff, 0xc3, 0x8f, 0x0e, 0xa1, 0x73, ++ 0x5f, 0x83, 0x33, 0xb4, 0xd6, 0x74, 0xc0, 0xd3, 0xe9, 0x0c, 0x6d, 0x2b, ++ 0xa6, 0x07, 0xc5, 0x7d, 0xe5, 0x37, 0x7e, 0xe0, 0xfb, 0x85, 0xbf, 0x3f, ++ 0x51, 0x9e, 0x8c, 0xf4, 0xf4, 0x7b, 0x41, 0xc7, 0xaf, 0x9f, 0x29, 0x4f, ++ 0x2e, 0x0f, 0xb1, 0x77, 0x2a, 0xbf, 0x30, 0x12, 0xde, 0xdf, 0x30, 0xbb, ++ 0x96, 0xe3, 0x3c, 0xdf, 0x88, 0xce, 0x52, 0xe8, 0x7c, 0x36, 0x6b, 0x4d, ++ 0xc0, 0x78, 0xf7, 0x3c, 0xe1, 0x7f, 0x00, 0xfd, 0xae, 0xd8, 0x16, 0xc1, ++ 0xee, 0x79, 0x38, 0x5d, 0x25, 0x3c, 0x75, 0xdc, 0x97, 0x94, 0x8f, 0x78, ++ 0x0d, 0xd2, 0x71, 0x25, 0xc9, 0x4b, 0xf2, 0x1b, 0x20, 0xff, 0xf6, 0x63, ++ 0xe5, 0xa4, 0xd7, 0x0e, 0x59, 0x56, 0xb0, 0x83, 0x68, 0x37, 0x8a, 0xf3, ++ 0x8b, 0x6c, 0x67, 0x14, 0xbf, 0xef, 0xb8, 0x25, 0xca, 0x1f, 0x95, 0x83, ++ 0xf1, 0x4f, 0x6d, 0x32, 0xb6, 0x63, 0xa9, 0xad, 0x83, 0x67, 0xd8, 0x43, ++ 0xf8, 0x4e, 0xd4, 0xff, 0xd8, 0xc7, 0xcf, 0xe7, 0x7e, 0x0c, 0xf5, 0xd1, ++ 0x7f, 0xfb, 0xd8, 0xf7, 0x0f, 0x7b, 0xe8, 0x3e, 0x84, 0xac, 0x5f, 0x15, ++ 0x6b, 0xf7, 0xa1, 0x31, 0xf1, 0xb9, 0xdd, 0x6e, 0x44, 0x3c, 0xec, 0x37, ++ 0xd6, 0x1d, 0xc6, 0x73, 0x7d, 0x95, 0x4f, 0x98, 0x48, 0xee, 0x57, 0x3e, ++ 0x91, 0x74, 0x77, 0x37, 0xca, 0x1b, 0xa0, 0x17, 0x8c, 0x8f, 0x85, 0xaf, ++ 0x2b, 0x35, 0xc3, 0x44, 0xf0, 0xea, 0x93, 0x0f, 0x7d, 0x77, 0x94, 0x4c, ++ 0xd4, 0xf9, 0x07, 0x77, 0x9c, 0x93, 0x0f, 0x0f, 0x3f, 0xb6, 0xac, 0x64, ++ 0xa3, 0xad, 0x6f, 0x3e, 0xac, 0x12, 0x7e, 0xca, 0xe4, 0x27, 0x4c, 0x74, ++ 0x4e, 0xbd, 0x6a, 0x8c, 0xdd, 0x88, 0xfb, 0x8f, 0x85, 0x4f, 0xbc, 0xb9, ++ 0x89, 0xee, 0xad, 0x2e, 0x8d, 0x1a, 0x85, 0xf7, 0x13, 0xaa, 0x9e, 0xb0, ++ 0x10, 0xbe, 0xba, 0xec, 0x76, 0x9f, 0x03, 0xf7, 0x47, 0x63, 0xed, 0xc6, ++ 0x78, 0x48, 0xbf, 0x16, 0x76, 0x48, 0x12, 0x5e, 0xae, 0xc4, 0xb8, 0x8c, ++ 0xca, 0x8c, 0xd6, 0x51, 0x94, 0xd2, 0xbd, 0x04, 0xb9, 0xaf, 0x77, 0x74, ++ 0xc5, 0x83, 0x0f, 0xe3, 0x31, 0xca, 0x63, 0xcc, 0x3f, 0x73, 0x2c, 0xc0, ++ 0xef, 0x14, 0x22, 0x0c, 0xe0, 0x72, 0x4a, 0xde, 0xcb, 0x0a, 0xdb, 0xe7, ++ 0xab, 0xde, 0xbb, 0xcd, 0x5c, 0xc0, 0xce, 0xb1, 0xcf, 0x77, 0x9e, 0xfd, ++ 0x3d, 0x20, 0x5f, 0x7a, 0x47, 0xe2, 0x42, 0xf7, 0xf9, 0x62, 0x32, 0xc4, ++ 0xbd, 0x9f, 0x9e, 0x7d, 0x3e, 0x13, 0xbd, 0x0b, 0x51, 0x25, 0xf6, 0xf9, ++ 0x8a, 0xd6, 0xf3, 0xf3, 0x5b, 0x55, 0x2b, 0xf8, 0xfb, 0x1d, 0x45, 0x09, ++ 0x3c, 0xde, 0x7b, 0xa8, 0xce, 0x87, 0x8f, 0xc4, 0xe2, 0x7a, 0x7d, 0x0e, ++ 0xbc, 0x9f, 0xfb, 0x10, 0xd7, 0x2f, 0x55, 0x4c, 0xf1, 0x5b, 0xe1, 0x9f, ++ 0xd7, 0xac, 0x5f, 0x6a, 0xa4, 0xfb, 0x8f, 0xe9, 0x1c, 0x3e, 0x65, 0xe2, ++ 0x1d, 0xa7, 0x83, 0x51, 0xee, 0x6c, 0xf4, 0xd3, 0x2b, 0x9f, 0x88, 0x22, ++ 0xb8, 0x56, 0x3d, 0xb9, 0xe0, 0x2f, 0x8f, 0x42, 0xbb, 0xae, 0xfa, 0x92, ++ 0xc4, 0x50, 0xbf, 0x38, 0x47, 0xd0, 0x03, 0xf4, 0xcf, 0xf0, 0x9e, 0xae, ++ 0xec, 0xe7, 0xf3, 0xfa, 0x9f, 0x67, 0x23, 0xdd, 0x17, 0xfd, 0x1a, 0xfc, ++ 0x5b, 0xbc, 0xef, 0x17, 0xcf, 0x5e, 0xb8, 0x39, 0x07, 0xf1, 0x94, 0x96, ++ 0x8d, 0xfb, 0x91, 0xb2, 0x5e, 0xd5, 0xca, 0x9f, 0x0d, 0xe6, 0xf5, 0xc0, ++ 0x3f, 0x06, 0x3f, 0xb8, 0xec, 0x5e, 0x95, 0xbf, 0xbf, 0xf6, 0xb2, 0x85, ++ 0xf4, 0x1d, 0xf0, 0x78, 0x2a, 0x0b, 0xb9, 0xcf, 0x3c, 0xaf, 0x71, 0xaf, ++ 0xd9, 0x3c, 0x2c, 0x78, 0xff, 0xeb, 0x53, 0xc8, 0xe3, 0x95, 0xfb, 0x90, ++ 0x7b, 0x60, 0x66, 0x84, 0x97, 0xbc, 0x97, 0x84, 0x7f, 0xa9, 0x79, 0xc2, ++ 0xde, 0x76, 0x91, 0xfc, 0xa0, 0x77, 0x78, 0x4b, 0x0d, 0x0a, 0xdd, 0x5f, ++ 0x02, 0xc9, 0x45, 0xf7, 0x7e, 0xae, 0xcf, 0xe0, 0xf6, 0xeb, 0xc4, 0x0c, ++ 0x7e, 0xde, 0xa9, 0x2c, 0xdb, 0x4d, 0xf7, 0x5f, 0xaa, 0x1f, 0xb0, 0xb8, ++ 0x57, 0xe6, 0xf0, 0x7e, 0x7a, 0xee, 0x55, 0xe3, 0x39, 0x27, 0x43, 0x67, ++ 0x25, 0xed, 0x3f, 0xfe, 0xd6, 0x42, 0x71, 0x91, 0x9a, 0xc6, 0x28, 0x2d, ++ 0x2a, 0x96, 0x9f, 0x8b, 0x78, 0x69, 0x18, 0x9d, 0x8b, 0x36, 0x9a, 0x71, ++ 0xdf, 0xc4, 0xc5, 0xe5, 0xc4, 0xf5, 0x82, 0xfe, 0x6a, 0x5c, 0xd3, 0xaf, ++ 0x41, 0x7a, 0x81, 0xf2, 0x7d, 0x46, 0x3c, 0x87, 0x65, 0xe7, 0xf2, 0xb0, ++ 0x3a, 0x1e, 0xe0, 0xce, 0xf5, 0xb0, 0x66, 0x80, 0x71, 0x4e, 0xe2, 0xbf, ++ 0x06, 0xf0, 0x7e, 0xd3, 0x46, 0x84, 0x8c, 0xaf, 0x88, 0xef, 0xd0, 0x8f, ++ 0x2b, 0x36, 0xd8, 0xef, 0x1e, 0x03, 0x6b, 0xc2, 0xb8, 0x0b, 0xd6, 0xbf, ++ 0x64, 0x04, 0xc2, 0x31, 0x61, 0xe6, 0x6c, 0x9c, 0xdf, 0xf3, 0x2a, 0xf1, ++ 0x31, 0x2c, 0xfe, 0x81, 0x71, 0x68, 0xdf, 0x3d, 0xaf, 0x8e, 0x46, 0xbf, ++ 0xb6, 0xec, 0xde, 0x9d, 0x93, 0xd7, 0x61, 0x7e, 0xeb, 0x48, 0xbc, 0xb1, ++ 0xc0, 0xca, 0x5e, 0xf8, 0x80, 0xf4, 0xc5, 0x22, 0x81, 0xff, 0x2e, 0x71, ++ 0x1e, 0xac, 0x1c, 0xf2, 0x78, 0xdf, 0x7f, 0x7e, 0x06, 0x97, 0x93, 0x5e, ++ 0x95, 0xc7, 0x7b, 0xe6, 0x0b, 0x78, 0x49, 0x3a, 0x90, 0xe5, 0xd5, 0xf7, ++ 0xf2, 0xf3, 0x50, 0xd5, 0xab, 0x2c, 0x64, 0xbf, 0x54, 0xd7, 0xff, 0x95, ++ 0xfa, 0xad, 0xb6, 0x77, 0x26, 0xa3, 0xdc, 0xad, 0x7e, 0xd9, 0x44, 0xf7, ++ 0x98, 0x17, 0x89, 0x79, 0x97, 0xd7, 0x67, 0xe5, 0xef, 0x03, 0xba, 0x2a, ++ 0x37, 0xc5, 0xd1, 0x7b, 0xcb, 0x8b, 0x7d, 0x25, 0x66, 0xcc, 0x2f, 0x6e, ++ 0x51, 0x28, 0x1f, 0x6c, 0x97, 0x94, 0x8d, 0x74, 0x7a, 0xbc, 0xf1, 0x95, ++ 0x58, 0xa4, 0x9f, 0x83, 0x51, 0x81, 0x41, 0xa8, 0x87, 0xba, 0x97, 0x46, ++ 0xb9, 0xf1, 0x1c, 0x9e, 0x8c, 0xb7, 0x1d, 0x6f, 0x1c, 0xf4, 0x14, 0xc6, ++ 0x65, 0xe6, 0x39, 0x3a, 0xed, 0x78, 0x1f, 0x69, 0xde, 0xf2, 0x01, 0x4e, ++ 0x94, 0xdb, 0xfb, 0x1d, 0x01, 0x33, 0x96, 0xef, 0x6f, 0xcd, 0x31, 0x60, ++ 0x5e, 0x73, 0x38, 0xf2, 0x31, 0xaf, 0x19, 0x2f, 0xa7, 0xfc, 0x71, 0x71, ++ 0xee, 0x84, 0xfe, 0x90, 0x5e, 0x14, 0x8e, 0xe7, 0xc5, 0x5b, 0x76, 0x9a, ++ 0xfb, 0xc3, 0x78, 0x2d, 0x82, 0x2e, 0xbe, 0x78, 0xfe, 0x83, 0xc1, 0xa8, ++ 0xa7, 0xaa, 0xb3, 0x3b, 0x07, 0xa3, 0x3e, 0x01, 0x3a, 0x18, 0x9c, 0x81, ++ 0x70, 0x7e, 0x56, 0x21, 0x3d, 0xbc, 0x64, 0x0b, 0x3f, 0xa7, 0x2e, 0xe9, ++ 0x60, 0x09, 0xd2, 0x01, 0xf0, 0xdd, 0x42, 0x41, 0x07, 0x4b, 0xb6, 0xbf, ++ 0xf2, 0x13, 0xe4, 0x87, 0x25, 0x88, 0xff, 0x51, 0xbd, 0xe9, 0x08, 0xe8, ++ 0x74, 0x17, 0x7d, 0x7f, 0x69, 0xc3, 0x64, 0xc6, 0xdb, 0xef, 0x42, 0x3a, ++ 0x91, 0xfa, 0x0b, 0xf2, 0x8d, 0x26, 0x27, 0xc6, 0xdf, 0x44, 0x1e, 0xc6, ++ 0xc1, 0xfc, 0x5a, 0x01, 0x4f, 0x28, 0x9f, 0xc8, 0xcb, 0x7d, 0xc3, 0xf8, ++ 0x39, 0xb7, 0x2e, 0x3a, 0xb7, 0x57, 0x23, 0xee, 0x2b, 0xf6, 0xc8, 0xa7, ++ 0x3e, 0xf0, 0xfc, 0x82, 0xc0, 0x63, 0x79, 0xbd, 0x85, 0xe4, 0xed, 0x0b, ++ 0x02, 0xcf, 0x5d, 0xf7, 0xbe, 0x1c, 0x8b, 0x78, 0xfc, 0xe2, 0xf9, 0x9d, ++ 0xbb, 0x71, 0x9f, 0xa4, 0xfa, 0x25, 0xc5, 0xc1, 0xf7, 0xab, 0xc2, 0xf8, ++ 0x42, 0xc0, 0xa5, 0x06, 0xe1, 0x10, 0x4b, 0xeb, 0x20, 0xbb, 0xa2, 0x06, ++ 0xd7, 0x1d, 0x1b, 0x84, 0x43, 0x0f, 0xfd, 0x0b, 0x7e, 0xac, 0x61, 0x7c, ++ 0x9d, 0x72, 0xdd, 0x35, 0x46, 0x01, 0x07, 0x59, 0x2e, 0xda, 0xbf, 0x88, ++ 0xeb, 0x4c, 0x42, 0xf8, 0x0a, 0xb8, 0x6d, 0x1f, 0xc2, 0xf9, 0x4f, 0xf0, ++ 0x1b, 0xf2, 0x33, 0xbd, 0xcf, 0x23, 0xd6, 0xe7, 0x75, 0xea, 0xdf, 0xdd, ++ 0xfe, 0x30, 0x83, 0xeb, 0x83, 0xd7, 0x44, 0xba, 0x18, 0xe8, 0x02, 0xef, ++ 0x67, 0x31, 0xbc, 0x9e, 0x28, 0xe5, 0x04, 0x14, 0x7d, 0xb1, 0x75, 0x03, ++ 0xc5, 0x7d, 0x24, 0xbe, 0xe4, 0xbc, 0x0f, 0x07, 0xf5, 0x88, 0x16, 0xef, ++ 0x0c, 0xe2, 0xb1, 0xcb, 0xc0, 0xef, 0x2f, 0x86, 0xeb, 0xcb, 0x77, 0x04, ++ 0xfc, 0x0e, 0xac, 0x4a, 0xc9, 0x6e, 0x03, 0xb8, 0x1d, 0xdf, 0x4c, 0xcf, ++ 0x54, 0x12, 0xbd, 0x1a, 0x43, 0xc6, 0x93, 0x74, 0x23, 0xc7, 0x2b, 0x7a, ++ 0x6e, 0xfa, 0x75, 0xb8, 0x5e, 0xe8, 0x3f, 0x80, 0xfd, 0xcb, 0x71, 0xf7, ++ 0xfb, 0x62, 0x8c, 0xd8, 0xcf, 0x7e, 0xc6, 0xf9, 0x03, 0xe9, 0x13, 0xe5, ++ 0xa7, 0xe4, 0xcb, 0xa2, 0x86, 0x39, 0xd7, 0x8d, 0xc4, 0x73, 0xbf, 0xbe, ++ 0x2f, 0xec, 0x03, 0x86, 0xe1, 0x7a, 0x39, 0xdd, 0x1e, 0xce, 0xe0, 0xe7, ++ 0x7f, 0x34, 0xb4, 0x13, 0xa0, 0xbd, 0xd6, 0xa6, 0x50, 0xdc, 0xf9, 0x80, ++ 0xf0, 0xe7, 0x0f, 0xac, 0x7a, 0x25, 0xb6, 0x3c, 0x04, 0x4e, 0x87, 0x44, ++ 0x3b, 0x49, 0x67, 0xf8, 0x87, 0xf1, 0x28, 0x39, 0xdf, 0x3d, 0x4e, 0x1e, ++ 0xc7, 0x0d, 0x9f, 0xb7, 0x94, 0x43, 0x72, 0xde, 0x45, 0xf7, 0xcc, 0xba, ++ 0x0e, 0xbf, 0xcb, 0xf9, 0x4b, 0x7a, 0x95, 0xf4, 0x29, 0xe1, 0x28, 0xe9, ++ 0x54, 0xde, 0x7f, 0x0b, 0xa7, 0x57, 0xa2, 0x35, 0xa9, 0x3f, 0x55, 0x9d, ++ 0xbc, 0x27, 0xfd, 0x78, 0x4d, 0xe6, 0x57, 0x66, 0xaf, 0xad, 0xf7, 0xf7, ++ 0xf0, 0xbc, 0xb4, 0x83, 0x0e, 0x8a, 0xf3, 0xdb, 0xdd, 0x49, 0x8c, 0xc7, ++ 0xeb, 0x1b, 0x53, 0x77, 0x85, 0xde, 0xf7, 0x81, 0x3f, 0x5b, 0xa8, 0xde, ++ 0x09, 0xd1, 0x27, 0xcd, 0xc6, 0x10, 0x7d, 0x22, 0xf5, 0x7f, 0x4d, 0xa2, ++ 0x76, 0x14, 0xf1, 0x55, 0x9c, 0xc9, 0xcf, 0x95, 0x1c, 0x63, 0xad, 0xe6, ++ 0x02, 0xe8, 0x77, 0xf1, 0x91, 0xce, 0xc9, 0xf8, 0x4e, 0xa2, 0xb4, 0x3b, ++ 0xaf, 0xfc, 0x3a, 0xa0, 0xc6, 0x61, 0x1c, 0x6a, 0x3b, 0x3f, 0x7f, 0x26, ++ 0xe1, 0xbd, 0xf8, 0xc4, 0x2e, 0xa2, 0xfb, 0x6a, 0x71, 0x2f, 0xa9, 0xec, ++ 0xde, 0x0f, 0x4a, 0xc6, 0x22, 0x7d, 0xff, 0xc6, 0x44, 0xfb, 0x31, 0x65, ++ 0xab, 0x26, 0xd1, 0xfd, 0xe3, 0x05, 0x9b, 0xe6, 0xe6, 0x21, 0xfd, 0xe0, ++ 0x7d, 0x06, 0x94, 0xe7, 0x47, 0x37, 0x8e, 0x19, 0xcd, 0x9f, 0xf3, 0x72, ++ 0x24, 0xcf, 0xc4, 0x7b, 0x0d, 0x1b, 0x1f, 0x9c, 0x79, 0x0b, 0x7c, 0x9f, ++ 0xd7, 0xa6, 0xba, 0x49, 0xae, 0x43, 0x3f, 0xc8, 0xaf, 0x65, 0x77, 0x8e, ++ 0x66, 0x48, 0x2f, 0x07, 0xa3, 0xba, 0x4a, 0xc6, 0xa3, 0xbd, 0xfe, 0x53, ++ 0xd5, 0x81, 0xf6, 0xfa, 0x84, 0x4d, 0x63, 0xee, 0xc6, 0xfa, 0x13, 0xec, ++ 0xfd, 0xe2, 0x71, 0x3d, 0xda, 0xc6, 0x04, 0xca, 0x6b, 0xc6, 0x38, 0xd2, ++ 0x0b, 0xd2, 0xce, 0x95, 0xe7, 0xf2, 0x1a, 0x4c, 0x9c, 0x1e, 0x46, 0x65, ++ 0x72, 0xfe, 0xb9, 0xa4, 0x27, 0x55, 0xc4, 0x79, 0xbc, 0x86, 0xc1, 0xb8, ++ 0x7f, 0xde, 0xbd, 0x21, 0x8a, 0xde, 0x41, 0x2a, 0x35, 0x8b, 0x7b, 0x9c, ++ 0xaf, 0xa5, 0x90, 0x3f, 0x51, 0x63, 0xc6, 0x2b, 0x85, 0x74, 0x2f, 0x94, ++ 0xec, 0xb0, 0xf9, 0x66, 0x66, 0x4d, 0xe3, 0xe7, 0x9d, 0xad, 0x69, 0xf0, ++ 0x7d, 0xaf, 0xa9, 0xf3, 0x4e, 0xd4, 0x1f, 0x7b, 0xef, 0xb4, 0x8f, 0xa4, ++ 0x73, 0xf5, 0xea, 0x77, 0x79, 0xe5, 0xdc, 0x7e, 0xe6, 0xfb, 0x85, 0x09, ++ 0xfa, 0x77, 0x87, 0xe4, 0x3c, 0x46, 0x8a, 0xf1, 0xc3, 0xfb, 0x93, 0xed, ++ 0xf7, 0x88, 0xf3, 0xc6, 0x07, 0xc5, 0xfc, 0x8f, 0x36, 0xfe, 0x66, 0x26, ++ 0xea, 0xbf, 0xa3, 0x9b, 0x07, 0x39, 0x71, 0xdd, 0x9f, 0xbf, 0x16, 0x45, ++ 0xe7, 0xf0, 0x3f, 0x0f, 0x7b, 0xb7, 0xf0, 0x62, 0xef, 0x69, 0x01, 0xdd, ++ 0x86, 0xdd, 0x83, 0x5a, 0xc9, 0xe5, 0x45, 0xa6, 0xfe, 0x9c, 0x96, 0xa4, ++ 0xf3, 0xf3, 0xde, 0x53, 0xfa, 0x28, 0x31, 0x6c, 0x3f, 0xe0, 0xdc, 0xe7, ++ 0x8b, 0x4e, 0xd4, 0x31, 0xba, 0x4f, 0x6d, 0x01, 0x5f, 0x98, 0xec, 0x99, ++ 0x98, 0xef, 0xb7, 0xe1, 0xb9, 0xbe, 0xca, 0x16, 0x8b, 0x03, 0xef, 0xb3, ++ 0x1c, 0x42, 0xba, 0xa7, 0xf3, 0x3c, 0x2a, 0xbf, 0x77, 0x6b, 0xe5, 0x7c, ++ 0x70, 0x68, 0xeb, 0x48, 0x3f, 0xfa, 0x8d, 0x95, 0x1f, 0xf1, 0xfb, 0x45, ++ 0xbb, 0xd6, 0xde, 0x43, 0xe7, 0x0a, 0x2a, 0xc0, 0xae, 0xc4, 0xa3, 0x54, ++ 0x3d, 0x76, 0xf2, 0x43, 0x6b, 0x67, 0x22, 0x1b, 0x9c, 0x72, 0x7b, 0x57, ++ 0xe3, 0x3b, 0x2f, 0xa7, 0x36, 0xf3, 0x73, 0x10, 0xbd, 0xde, 0x2d, 0xd8, ++ 0xbb, 0x6d, 0x77, 0xe8, 0xbb, 0x05, 0x17, 0x6b, 0x1f, 0x5f, 0xa8, 0x5d, ++ 0x2c, 0xe3, 0x0a, 0x35, 0x99, 0xfa, 0x7b, 0xf1, 0x12, 0xae, 0xd2, 0x3f, ++ 0x7a, 0x03, 0xf0, 0x3f, 0x6e, 0x54, 0x10, 0x4e, 0x5f, 0xd6, 0xcd, 0x27, ++ 0xbb, 0xf8, 0x44, 0x9d, 0x97, 0xd2, 0x93, 0xca, 0x81, 0x07, 0x26, 0x20, ++ 0xdd, 0xda, 0xe3, 0xe8, 0xbc, 0xfe, 0xef, 0xdb, 0x1e, 0x54, 0xf1, 0x9d, ++ 0x95, 0xea, 0xed, 0x23, 0xbf, 0x43, 0xff, 0x76, 0xbc, 0x2d, 0xce, 0x81, ++ 0xfc, 0xfa, 0x65, 0xdd, 0x0a, 0xda, 0xef, 0x3c, 0x51, 0x57, 0x4b, 0x69, ++ 0xf0, 0x5d, 0x57, 0x3f, 0xa5, 0x57, 0x6e, 0xef, 0xa0, 0x76, 0x5f, 0xb6, ++ 0x8d, 0x6e, 0xc7, 0x7b, 0xae, 0xaf, 0xdb, 0xe2, 0x84, 0xbc, 0x0f, 0xdf, ++ 0xd7, 0xe1, 0x78, 0xec, 0xeb, 0xfe, 0xae, 0x5c, 0xd7, 0xb1, 0x9f, 0x72, ++ 0x7c, 0xca, 0x79, 0x1f, 0xdb, 0x3c, 0x37, 0x16, 0xd7, 0xd5, 0xf1, 0x78, ++ 0x42, 0xfb, 0x15, 0x88, 0xc7, 0x98, 0x38, 0x07, 0xda, 0x77, 0x55, 0xe2, ++ 0x9c, 0xc7, 0xe1, 0x75, 0xdc, 0x7e, 0x3e, 0x62, 0x8d, 0x7b, 0x66, 0x2a, ++ 0x9e, 0x0f, 0x59, 0x7f, 0x43, 0x32, 0xbe, 0x83, 0x53, 0xd1, 0x71, 0xe3, ++ 0x4c, 0xfc, 0x5e, 0xf9, 0x9a, 0xe2, 0x40, 0xbb, 0xdf, 0xfd, 0xda, 0xf4, ++ 0x58, 0x8c, 0xa3, 0x7d, 0x66, 0xec, 0x8a, 0xc5, 0x7b, 0x4d, 0x9f, 0xad, ++ 0x93, 0xf7, 0xa1, 0xfc, 0xf4, 0x1e, 0xe9, 0xf8, 0x62, 0x46, 0xfb, 0x4e, ++ 0xe3, 0x03, 0x46, 0xe6, 0xca, 0xe1, 0x5b, 0xcc, 0x48, 0x27, 0x57, 0x9c, ++ 0x30, 0xd2, 0xbd, 0xd3, 0xe3, 0xb8, 0x1f, 0x85, 0x71, 0x8f, 0xef, 0xa2, ++ 0x29, 0xee, 0xc1, 0xc4, 0x3e, 0x53, 0xc5, 0xab, 0x3c, 0x5e, 0xd2, 0xe3, ++ 0xc7, 0x0a, 0x3f, 0x6e, 0x82, 0x58, 0xf7, 0x5b, 0x99, 0x4e, 0xb9, 0x7f, ++ 0x40, 0xdf, 0x8b, 0xc6, 0xf1, 0xef, 0x9f, 0xaf, 0xdf, 0x36, 0x0d, 0xfb, ++ 0x3b, 0xba, 0xd1, 0xe4, 0xc0, 0x79, 0x7f, 0xb9, 0x91, 0xbf, 0xcf, 0xb0, ++ 0x10, 0xfc, 0x2f, 0xbc, 0x9a, 0x72, 0x64, 0x33, 0xf7, 0x6f, 0x16, 0xb6, ++ 0x2a, 0xe4, 0x0f, 0x1f, 0xdd, 0x0c, 0xfa, 0x19, 0xd6, 0x55, 0xbd, 0xd4, ++ 0xa4, 0xf1, 0xfb, 0x9a, 0x7a, 0xfa, 0x2b, 0x82, 0x72, 0x3c, 0xd7, 0x28, ++ 0xe9, 0x6f, 0xa1, 0xe6, 0x27, 0xba, 0x0e, 0x7f, 0x3f, 0x23, 0x9e, 0xb5, ++ 0xd2, 0xbd, 0xae, 0x1f, 0x8b, 0x1e, 0x03, 0x99, 0x7a, 0x3f, 0xad, 0x87, ++ 0x0e, 0xfb, 0xc2, 0xbf, 0x80, 0x13, 0xf2, 0x2d, 0xd2, 0xa1, 0xc4, 0xf3, ++ 0xc2, 0x75, 0x7c, 0xdf, 0xdc, 0xd9, 0x3a, 0xb2, 0x00, 0xe9, 0x49, 0xe2, ++ 0x5d, 0xca, 0x05, 0x79, 0x5f, 0xa1, 0xc1, 0xcc, 0xf8, 0x7b, 0xa5, 0x86, ++ 0x68, 0xfa, 0x3d, 0x80, 0xe9, 0x36, 0x97, 0x49, 0x81, 0xf5, 0xdf, 0x90, ++ 0xd8, 0x35, 0x11, 0xc5, 0xe7, 0xb0, 0x2c, 0x6e, 0x7f, 0xa8, 0x45, 0x06, ++ 0x0d, 0xef, 0xa1, 0xb1, 0x06, 0x4b, 0xc4, 0xf7, 0xa8, 0xfe, 0x26, 0xe4, ++ 0xe8, 0x9c, 0x2c, 0x46, 0xe9, 0x37, 0x99, 0xdc, 0x5e, 0x90, 0xf7, 0xb1, ++ 0x64, 0x0a, 0x0b, 0xc9, 0x42, 0x3d, 0x3d, 0x3d, 0xc6, 0xf9, 0x8d, 0x0b, ++ 0xaa, 0x1c, 0x5e, 0xbf, 0x74, 0x9a, 0x11, 0xe6, 0x3f, 0x7d, 0x82, 0xf3, ++ 0xce, 0x01, 0x6e, 0xc0, 0xdb, 0xfa, 0x9f, 0x4c, 0x33, 0x02, 0xdd, 0x4e, ++ 0x1f, 0xed, 0x7c, 0xb9, 0x3f, 0xe4, 0xbb, 0x33, 0xef, 0xe2, 0xf9, 0xcb, ++ 0x9d, 0x63, 0x4c, 0x90, 0xaf, 0xaf, 0x5f, 0x31, 0x6d, 0x22, 0xd4, 0xb7, ++ 0x67, 0x69, 0x87, 0x32, 0x43, 0xc6, 0x91, 0xfd, 0xc2, 0xf7, 0xcf, 0xf1, ++ 0xbb, 0x3f, 0xc1, 0x7b, 0x0c, 0xd3, 0x1a, 0x33, 0xbf, 0x1f, 0x75, 0x52, ++ 0xe9, 0x1e, 0xb1, 0x22, 0x27, 0x58, 0xff, 0x7d, 0x85, 0xed, 0xff, 0xbd, ++ 0x12, 0xcc, 0x77, 0x99, 0x18, 0xbd, 0x03, 0xf3, 0x4d, 0xa6, 0x9c, 0x7f, ++ 0xe4, 0x74, 0x4c, 0x96, 0x76, 0x3a, 0x73, 0x4c, 0xef, 0xef, 0xe5, 0x8c, ++ 0xad, 0xa2, 0xf3, 0x71, 0x3e, 0x7e, 0xbf, 0x05, 0xfe, 0x3c, 0xd6, 0x64, ++ 0xbc, 0x7f, 0xc4, 0xe9, 0xa9, 0x5c, 0xde, 0x77, 0x69, 0xd2, 0xdf, 0x77, ++ 0x61, 0x6e, 0x7e, 0xff, 0x4a, 0xde, 0x43, 0x92, 0xf7, 0x8c, 0x2e, 0x09, ++ 0xde, 0x9f, 0x5a, 0x7f, 0x31, 0xf7, 0xa7, 0x4e, 0x9a, 0x60, 0xbd, 0x71, ++ 0xbd, 0xef, 0xb3, 0x29, 0xed, 0x7f, 0xa0, 0xf7, 0xb0, 0x1a, 0x7c, 0xac, ++ 0x2b, 0x8a, 0xf0, 0xa0, 0xbf, 0xbf, 0x52, 0x1d, 0xc3, 0xdf, 0xf7, 0x5b, ++ 0xf6, 0xf2, 0x17, 0xbb, 0x90, 0xac, 0x16, 0x48, 0x7b, 0x05, 0x95, 0x6d, ++ 0x5e, 0xf0, 0xfe, 0x3e, 0x4b, 0xe5, 0xfb, 0xfe, 0x77, 0x0a, 0x3a, 0xfc, ++ 0xbc, 0x8e, 0x0d, 0x1c, 0x08, 0xac, 0x7c, 0x7d, 0x67, 0x67, 0xac, 0x0b, ++ 0x26, 0x7b, 0x62, 0x5a, 0x60, 0x30, 0xf2, 0xb7, 0xcb, 0xe2, 0xcd, 0xc8, ++ 0x42, 0x3f, 0x7e, 0x7d, 0x43, 0xe6, 0xb2, 0x44, 0xbc, 0xf7, 0x69, 0x71, ++ 0x4f, 0x85, 0xfa, 0x47, 0xfc, 0xfc, 0x5e, 0xe5, 0x62, 0x61, 0x6f, 0xb2, ++ 0x8d, 0x49, 0x82, 0xcf, 0xd5, 0xc0, 0xd5, 0x50, 0x6f, 0x4f, 0xce, 0x25, ++ 0xf4, 0x7e, 0xc3, 0xa0, 0x2c, 0xee, 0x47, 0x9c, 0xc8, 0x09, 0x64, 0xe3, ++ 0x7b, 0x3a, 0xbe, 0x1c, 0xee, 0xdf, 0x40, 0x3d, 0x3a, 0xbf, 0x56, 0xbc, ++ 0xf2, 0x9a, 0x24, 0xac, 0x77, 0x62, 0xeb, 0x3d, 0x03, 0x2b, 0x00, 0x6f, ++ 0x16, 0x7c, 0xbf, 0xcd, 0x49, 0x29, 0xc3, 0xfb, 0x4f, 0xd7, 0x42, 0xdf, ++ 0xe3, 0x9c, 0xf4, 0xae, 0x1b, 0x53, 0x69, 0x9f, 0xd6, 0x4f, 0xfd, 0x61, ++ 0xbd, 0x58, 0xd4, 0xeb, 0xae, 0xb9, 0xa9, 0x3c, 0x8e, 0xce, 0xef, 0xcd, ++ 0x49, 0x3c, 0x49, 0xf8, 0xf7, 0xc2, 0x0b, 0x4c, 0x01, 0xed, 0x51, 0x83, ++ 0x95, 0x99, 0x70, 0xfe, 0x97, 0xb0, 0xf5, 0x0e, 0xe4, 0x53, 0x89, 0x1f, ++ 0xf9, 0xfe, 0xe9, 0xb2, 0x97, 0x79, 0xfc, 0x64, 0x99, 0xd2, 0xd5, 0x98, ++ 0x80, 0xf9, 0xe7, 0x15, 0x3a, 0xff, 0xf6, 0xb9, 0x95, 0xdf, 0xeb, 0xe9, ++ 0xad, 0xe7, 0x36, 0x99, 0x11, 0xd4, 0xf3, 0xd7, 0xcf, 0xd5, 0xbd, 0xcf, ++ 0x23, 0xdf, 0x19, 0xfd, 0xb1, 0xe3, 0x40, 0x53, 0xb3, 0x84, 0x7c, 0x19, ++ 0xc9, 0x46, 0x86, 0xbe, 0xe3, 0x5a, 0x25, 0xda, 0x4e, 0x52, 0x4b, 0x5d, ++ 0xf8, 0xde, 0xdb, 0xb2, 0x24, 0x2b, 0xbd, 0xdb, 0xb1, 0xec, 0x89, 0x01, ++ 0xa4, 0x4f, 0xd8, 0xdb, 0x77, 0xb0, 0xd0, 0x7a, 0x6c, 0x7d, 0x02, 0xd1, ++ 0xc7, 0xea, 0x1c, 0x95, 0xe0, 0xbc, 0xa0, 0x8d, 0xd1, 0xbb, 0x3b, 0x25, ++ 0x6d, 0xe9, 0x74, 0x5e, 0x71, 0x6a, 0x9b, 0x93, 0xd2, 0xd8, 0x33, 0xa9, ++ 0xf4, 0xfd, 0xe8, 0x33, 0x7f, 0xcc, 0xe5, 0xf2, 0x87, 0xe3, 0xa1, 0xe4, ++ 0xbf, 0x52, 0x0a, 0xe9, 0x7c, 0xd0, 0x7f, 0x0d, 0xa1, 0x94, 0xf5, 0xf5, ++ 0xae, 0xb0, 0xcd, 0x4a, 0xf7, 0x68, 0x97, 0xed, 0xe5, 0x7a, 0x69, 0xd9, ++ 0x4d, 0x2a, 0xc5, 0x27, 0x99, 0xb8, 0x1f, 0xee, 0x11, 0xd3, 0xf1, 0xd8, ++ 0x9a, 0x28, 0x9e, 0xe3, 0x61, 0x91, 0xdf, 0x8f, 0xf5, 0xc8, 0xf7, 0x63, ++ 0x35, 0xd3, 0x39, 0xdf, 0x8f, 0x95, 0xf0, 0xb5, 0x08, 0xfc, 0x84, 0xbf, ++ 0x27, 0x7b, 0xd3, 0xde, 0xd1, 0xa9, 0xf4, 0x1e, 0xab, 0x78, 0x4f, 0x76, ++ 0xb6, 0xa8, 0xd7, 0x29, 0xee, 0x6d, 0x85, 0xbf, 0x2b, 0x7b, 0x4f, 0xec, ++ 0x64, 0x7a, 0x57, 0x76, 0xb6, 0x56, 0x15, 0xf1, 0x5d, 0x59, 0xa3, 0x2f, ++ 0xca, 0x8d, 0xf6, 0xad, 0x29, 0xd3, 0xc6, 0xdf, 0x6b, 0xf0, 0x86, 0xbf, ++ 0x33, 0xdb, 0x65, 0xc4, 0x75, 0xcf, 0xcc, 0xe7, 0xef, 0xcc, 0xde, 0x34, ++ 0x3b, 0xe4, 0x5d, 0x04, 0xf8, 0xcf, 0x94, 0xff, 0x15, 0xc9, 0x69, 0x53, ++ 0x7e, 0xaf, 0xf7, 0x81, 0x4c, 0x48, 0xdf, 0x16, 0x8f, 0xbe, 0x7e, 0xb3, ++ 0xc4, 0xff, 0x25, 0xec, 0x92, 0x73, 0xbe, 0xe3, 0x9b, 0x69, 0xa6, 0x77, ++ 0xde, 0x8c, 0xf8, 0x9e, 0x33, 0xe4, 0x67, 0x8a, 0x77, 0x7c, 0xd1, 0x8e, ++ 0x43, 0xfb, 0xfc, 0x94, 0xc6, 0xdf, 0x95, 0xb3, 0x88, 0x77, 0xa6, 0x3b, ++ 0x59, 0x6e, 0x2a, 0xf2, 0xfd, 0xc5, 0xbe, 0xd3, 0xfc, 0xff, 0xdb, 0xbb, ++ 0xcc, 0xe1, 0xef, 0x2f, 0x87, 0xbf, 0xb7, 0x7c, 0xd9, 0xe6, 0x65, 0xba, ++ 0xfc, 0xf0, 0xd6, 0xff, 0xd0, 0xd5, 0xbf, 0xbc, 0x6d, 0xa5, 0xae, 0x7c, ++ 0x64, 0x60, 0x8d, 0xae, 0x7c, 0xf4, 0x9e, 0x5f, 0xea, 0xf2, 0x63, 0x3a, ++ 0x1f, 0xd3, 0xd5, 0x1f, 0xbb, 0xef, 0x29, 0x5d, 0xf9, 0x15, 0x5d, 0xcf, ++ 0xea, 0xca, 0x27, 0x1c, 0x79, 0x49, 0x97, 0xbf, 0xb2, 0xfb, 0x77, 0xba, ++ 0xfa, 0x57, 0x9f, 0xd9, 0xa1, 0xcb, 0x17, 0xb0, 0x3f, 0xea, 0xea, 0x17, ++ 0x59, 0x3f, 0xd0, 0xe5, 0x27, 0x39, 0xfe, 0xa1, 0xab, 0x7f, 0x4d, 0xea, ++ 0x41, 0x5d, 0xf9, 0xb5, 0xae, 0xe3, 0xba, 0xf2, 0x29, 0x43, 0x4f, 0xeb, ++ 0xd7, 0x63, 0xf4, 0xfe, 0x0d, 0xe5, 0x7c, 0x89, 0xfb, 0xbf, 0x75, 0xed, ++ 0xa6, 0x31, 0xd7, 0x2f, 0xf0, 0xfd, 0xe7, 0x59, 0x89, 0x06, 0x7a, 0xaf, ++ 0xe3, 0x1f, 0x59, 0xc2, 0x7f, 0x11, 0x74, 0xf7, 0x57, 0xa9, 0xb7, 0x07, ++ 0xb2, 0x6c, 0x94, 0x5f, 0x93, 0xd4, 0xfc, 0x00, 0xd1, 0x5d, 0x9b, 0xc2, ++ 0xdf, 0x1f, 0x0e, 0xd3, 0x63, 0xc6, 0xe3, 0x1e, 0x0d, 0xe3, 0x71, 0xec, ++ 0x15, 0x7e, 0xff, 0x2b, 0x0e, 0xec, 0x3e, 0x63, 0xc8, 0x78, 0xf1, 0x9a, ++ 0x15, 0x1c, 0xc2, 0x60, 0x3e, 0xa1, 0xd8, 0xa1, 0xcb, 0x27, 0x79, 0x52, ++ 0x75, 0xf5, 0x53, 0x66, 0xbb, 0x74, 0xe5, 0x69, 0xde, 0xa1, 0xba, 0xf2, ++ 0x8c, 0xf9, 0x6e, 0x5d, 0x3e, 0xab, 0x76, 0x9c, 0xae, 0x7e, 0xbf, 0x15, ++ 0x9a, 0x2e, 0x9f, 0xe3, 0x2b, 0xd6, 0xd5, 0x1f, 0xd0, 0xe4, 0xd1, 0xe5, ++ 0x07, 0xb5, 0xcc, 0xd6, 0xd5, 0x1f, 0xb2, 0xce, 0xab, 0x2b, 0xbf, 0xc4, ++ 0x3f, 0x5f, 0x57, 0x7e, 0xd9, 0xe6, 0x5a, 0x5d, 0x7e, 0x78, 0xeb, 0x0a, ++ 0x5d, 0xfd, 0xcb, 0xdb, 0x7c, 0xba, 0xf2, 0x91, 0x81, 0x26, 0x5d, 0xf9, ++ 0xe8, 0x3d, 0x2d, 0xba, 0xfc, 0x98, 0xce, 0x75, 0xba, 0xfa, 0x63, 0xf7, ++ 0xf9, 0x75, 0xe5, 0x57, 0x74, 0x6d, 0xd6, 0x95, 0x4f, 0x38, 0xd2, 0xaa, ++ 0xcb, 0x5f, 0xd9, 0xdd, 0xa6, 0xab, 0x7f, 0xf5, 0x99, 0x80, 0x2e, 0x5f, ++ 0xc0, 0xf6, 0xea, 0xea, 0x17, 0x59, 0xdf, 0xd7, 0xe5, 0x27, 0x39, 0xfe, ++ 0xa6, 0xab, 0x7f, 0x4d, 0xea, 0x01, 0x5d, 0xf9, 0xb5, 0xae, 0xa3, 0xba, ++ 0x72, 0x69, 0xb7, 0x4c, 0x19, 0xfa, 0x95, 0xfe, 0xbb, 0xb0, 0x63, 0x4a, ++ 0xdc, 0xff, 0xd4, 0xb5, 0xf7, 0x15, 0x8a, 0x77, 0xa5, 0x5f, 0x52, 0xdc, ++ 0x0d, 0x2e, 0x58, 0x4f, 0x76, 0x7f, 0xae, 0xef, 0x41, 0x80, 0x46, 0xe1, ++ 0xbb, 0x88, 0x3e, 0x0f, 0xc5, 0x7d, 0x9c, 0x78, 0xb0, 0x0f, 0xe5, 0x14, ++ 0xde, 0xbb, 0x76, 0xf2, 0x73, 0x31, 0xa5, 0x14, 0x3f, 0x4a, 0x24, 0x3b, ++ 0x87, 0x54, 0x91, 0x0b, 0xcf, 0xe9, 0x80, 0x1d, 0x10, 0x8b, 0xde, 0x55, ++ 0x4e, 0x0e, 0xda, 0xc9, 0x31, 0x41, 0x7b, 0x2c, 0xf3, 0x6c, 0xc8, 0x39, ++ 0xb9, 0xf3, 0xd9, 0x63, 0xd7, 0x64, 0x33, 0x9a, 0xc7, 0x5d, 0xd9, 0xde, ++ 0xfc, 0xec, 0x24, 0xf4, 0x3f, 0xb6, 0x4e, 0xa6, 0x77, 0xc1, 0x99, 0x6f, ++ 0x35, 0xce, 0x43, 0xbe, 0x73, 0xf7, 0x6e, 0xd8, 0x7b, 0xc8, 0x32, 0xbd, ++ 0xd6, 0x7a, 0x84, 0x19, 0x43, 0xec, 0xbf, 0xbd, 0x51, 0x2d, 0x99, 0xa3, ++ 0xce, 0xe1, 0xbf, 0x5f, 0x6b, 0x3d, 0xc1, 0xf0, 0x9d, 0xe5, 0x9e, 0x7e, ++ 0x45, 0xbc, 0x42, 0x81, 0xf5, 0x2d, 0x0b, 0xe9, 0xff, 0x01, 0xf0, 0x17, ++ 0x8c, 0x03, 0x19, 0x6b, 0xa9, 0x03, 0xbe, 0xc1, 0x7d, 0xe1, 0x3a, 0x07, ++ 0xe5, 0x1f, 0xaa, 0x4b, 0xa5, 0xfc, 0xc3, 0x75, 0x2e, 0x4a, 0xd7, 0xd5, ++ 0x0d, 0xa5, 0xf4, 0xb1, 0x3a, 0x37, 0x95, 0xaf, 0xaf, 0x1b, 0x47, 0xf9, ++ 0x27, 0xeb, 0x34, 0xca, 0xfb, 0xeb, 0x8a, 0x29, 0x7d, 0xaa, 0xce, 0x43, ++ 0xdf, 0x37, 0xd6, 0xcd, 0xa6, 0xfc, 0x33, 0xe0, 0x17, 0x63, 0xba, 0x19, ++ 0xfc, 0x64, 0x4c, 0x9f, 0x05, 0x7f, 0x17, 0xcb, 0xb7, 0x80, 0xff, 0x8b, ++ 0xf9, 0x17, 0xea, 0x7c, 0x94, 0xb6, 0xd6, 0x35, 0xd1, 0xf7, 0x97, 0xea, ++ 0x5a, 0x28, 0xbf, 0xbd, 0x6e, 0x1d, 0xe5, 0x7f, 0x5b, 0xe7, 0xa7, 0xb4, ++ 0xad, 0x6e, 0x33, 0xa5, 0xbf, 0xab, 0x6b, 0xa5, 0xf2, 0xf6, 0xba, 0x36, ++ 0xca, 0xbf, 0x5e, 0x17, 0xa0, 0x7c, 0xa0, 0x6e, 0x0f, 0xe5, 0x77, 0xd4, ++ 0x75, 0x52, 0x7e, 0x57, 0xdd, 0x3e, 0xca, 0xef, 0xae, 0xeb, 0xa2, 0x74, ++ 0x4f, 0xdd, 0x11, 0x4a, 0xdf, 0xaa, 0xeb, 0xa6, 0xf2, 0xb7, 0xeb, 0xce, ++ 0x50, 0xfe, 0x98, 0x88, 0xb7, 0x2e, 0xcf, 0x56, 0x74, 0xf7, 0x95, 0x64, ++ 0x5e, 0xbe, 0xc7, 0x20, 0xed, 0xbf, 0x69, 0x68, 0xbf, 0x23, 0x71, 0x8c, ++ 0x33, 0x7d, 0xa9, 0xb3, 0xdf, 0xc3, 0xec, 0xe8, 0x70, 0x7c, 0xc8, 0x71, ++ 0x82, 0xef, 0x27, 0x0c, 0x7e, 0xaa, 0x21, 0xc4, 0x7f, 0xf2, 0x65, 0x73, ++ 0xff, 0x4a, 0xbe, 0xc7, 0x10, 0xfe, 0x8e, 0x02, 0x13, 0xf6, 0xa9, 0x7c, ++ 0xf7, 0x54, 0xbe, 0xd7, 0x50, 0x29, 0xe6, 0x55, 0x25, 0xf8, 0x61, 0x0c, ++ 0xd2, 0xe7, 0x50, 0xa2, 0xcf, 0xb7, 0x2f, 0xc6, 0x5f, 0x90, 0xfe, 0xa0, ++ 0x2d, 0xc9, 0xdb, 0x42, 0xf4, 0x99, 0x65, 0xf0, 0x91, 0x3f, 0x6c, 0xe3, ++ 0xf7, 0x89, 0x2f, 0x4f, 0xf2, 0x3e, 0x98, 0x3d, 0x06, 0xf7, 0x0b, 0x2b, ++ 0x76, 0xd3, 0x78, 0x0e, 0x37, 0xed, 0x1b, 0x96, 0x58, 0x02, 0x49, 0xb3, ++ 0x72, 0xe9, 0x9d, 0x70, 0x8a, 0xcb, 0xf5, 0x35, 0x5e, 0x8d, 0x38, 0xf7, ++ 0xdd, 0x67, 0xf9, 0xeb, 0x47, 0x33, 0xd1, 0x9e, 0x2e, 0xfe, 0x41, 0xa5, ++ 0x77, 0xb6, 0xde, 0x35, 0xd9, 0x67, 0xa3, 0xff, 0xff, 0x8c, 0xc0, 0xc3, ++ 0x33, 0xd9, 0x06, 0x5d, 0xba, 0x2d, 0xc9, 0xbb, 0x09, 0xe7, 0xf3, 0xad, ++ 0xbd, 0xf6, 0x36, 0x03, 0xcc, 0xff, 0xdb, 0xab, 0x96, 0x3e, 0x73, 0x47, ++ 0x4e, 0xd0, 0x4f, 0xbe, 0x1e, 0x5d, 0x4d, 0xf0, 0x6f, 0xa6, 0x33, 0x97, ++ 0x89, 0xce, 0x15, 0x32, 0xed, 0xcd, 0x1c, 0xb4, 0x9b, 0xc0, 0xb0, 0xc2, ++ 0xfc, 0x2c, 0xe6, 0xa3, 0x74, 0x5c, 0xa2, 0xf7, 0x05, 0xec, 0xe7, 0x66, ++ 0x30, 0xb8, 0x31, 0xef, 0x1d, 0x6f, 0xc9, 0x8e, 0xb4, 0xae, 0xf0, 0x79, ++ 0xbd, 0x2a, 0xf0, 0xf5, 0x6a, 0xb6, 0x41, 0x97, 0x1e, 0x48, 0xf2, 0xb6, ++ 0x21, 0xfc, 0xbe, 0xb5, 0x6b, 0x34, 0xaf, 0x77, 0xaf, 0xb8, 0x66, 0x30, ++ 0xae, 0x4b, 0xce, 0xab, 0xbf, 0x78, 0x77, 0x64, 0x1a, 0xeb, 0x7e, 0x12, ++ 0xe7, 0xf7, 0xed, 0x6b, 0x5f, 0x1d, 0x56, 0x06, 0x04, 0xe1, 0x2f, 0xfd, ++ 0x71, 0xba, 0xd7, 0x8f, 0x72, 0x6c, 0xa9, 0x22, 0xde, 0xb5, 0xeb, 0xf5, ++ 0x8e, 0x00, 0x95, 0x97, 0xde, 0xa9, 0x90, 0x7d, 0x36, 0x07, 0xfc, 0x19, ++ 0xdc, 0x1f, 0x92, 0xef, 0x06, 0x9c, 0xaa, 0x35, 0xd1, 0x3b, 0xf2, 0xf8, ++ 0xce, 0x00, 0xee, 0x9f, 0x9d, 0xaa, 0xfd, 0xcc, 0x86, 0xe4, 0x0c, 0xf5, ++ 0x18, 0xee, 0x6f, 0x34, 0xe0, 0x01, 0x1d, 0x28, 0x6f, 0xf8, 0x29, 0xbf, ++ 0x4f, 0x5f, 0x8a, 0xef, 0x62, 0x8c, 0xc2, 0x77, 0x0b, 0xac, 0xbc, 0xdf, ++ 0xbb, 0x15, 0xa2, 0xbb, 0xa4, 0xe4, 0x1c, 0x7e, 0xff, 0x19, 0xec, 0x3d, ++ 0xf2, 0x9f, 0x12, 0xbb, 0xe9, 0x9e, 0x1e, 0xd0, 0xc9, 0x9f, 0x11, 0x6e, ++ 0x0b, 0xaf, 0x50, 0xe9, 0xde, 0xf9, 0xbb, 0x06, 0xff, 0x60, 0x85, 0xf6, ++ 0x93, 0x2b, 0xcc, 0x0a, 0xcc, 0xaf, 0x2a, 0x11, 0xe8, 0xa3, 0x7f, 0xdf, ++ 0x74, 0xb0, 0x44, 0xdc, 0x17, 0x90, 0xdf, 0x81, 0xbe, 0x3e, 0x41, 0xb8, ++ 0x7d, 0xf9, 0xea, 0xd8, 0xa1, 0x14, 0x7f, 0x7f, 0xfd, 0x0a, 0x17, 0xc2, ++ 0xab, 0xc1, 0xc0, 0xef, 0x0f, 0xf9, 0xde, 0x52, 0xf9, 0xef, 0x2e, 0x09, ++ 0x11, 0xad, 0x4e, 0x18, 0x4e, 0x71, 0x46, 0x66, 0x74, 0xbb, 0x31, 0x5e, ++ 0x54, 0x22, 0xee, 0x9b, 0x74, 0xa8, 0x6c, 0x45, 0xa4, 0xf7, 0xc4, 0x95, ++ 0x7e, 0x9c, 0x8e, 0xde, 0x4d, 0xe5, 0xef, 0xe7, 0x35, 0x84, 0xed, 0xb3, ++ 0xfc, 0x53, 0xd0, 0xd5, 0x3f, 0x05, 0xbd, 0x95, 0xec, 0xd8, 0x4b, 0xef, ++ 0x08, 0x2d, 0xd9, 0xc3, 0xdf, 0x3b, 0x64, 0xb9, 0x5d, 0xc3, 0x42, 0xdf, ++ 0x9d, 0xe9, 0x59, 0xcf, 0x8a, 0xb7, 0x2e, 0x19, 0x18, 0xb2, 0x8e, 0x9a, ++ 0xb6, 0x03, 0xfc, 0x7c, 0x05, 0xeb, 0x1a, 0x16, 0x7a, 0x9e, 0x3c, 0x5d, ++ 0x8c, 0x2f, 0xe9, 0x48, 0x35, 0xdb, 0xbd, 0x1b, 0x6c, 0xa1, 0xf3, 0xeb, ++ 0xa1, 0x6b, 0xd6, 0x0f, 0xe9, 0x27, 0x1e, 0xe8, 0x7a, 0x00, 0xd1, 0xf5, ++ 0x61, 0xdc, 0x57, 0x9c, 0x66, 0x71, 0xc5, 0xcd, 0x82, 0xb4, 0x0b, 0x40, ++ 0x84, 0xef, 0xfb, 0x78, 0x7f, 0xed, 0xa0, 0xf3, 0x41, 0xf2, 0x9c, 0xd0, ++ 0x3c, 0xe6, 0xa1, 0xb4, 0x0a, 0xc8, 0x00, 0xe9, 0xd8, 0xe3, 0x5b, 0x4b, ++ 0xef, 0xb9, 0x2e, 0xc4, 0x5f, 0x62, 0xc5, 0xf7, 0x78, 0xc6, 0xcd, 0xcd, ++ 0xc6, 0x7c, 0x0d, 0xeb, 0x9e, 0x98, 0x0a, 0x70, 0xbb, 0xa9, 0xa9, 0xfe, ++ 0x4d, 0x7c, 0x0e, 0xef, 0x86, 0x96, 0xb5, 0x93, 0x30, 0xbe, 0x3a, 0xc3, ++ 0x5f, 0xf6, 0x26, 0xa6, 0xd3, 0x37, 0x2a, 0x87, 0xd1, 0x4f, 0x05, 0xbe, ++ 0x88, 0xef, 0x87, 0xf1, 0x10, 0xa5, 0x76, 0x15, 0x1e, 0xc9, 0xbc, 0x65, ++ 0x4b, 0xc1, 0x2a, 0xdc, 0x7a, 0x99, 0xa6, 0x72, 0x7c, 0xb0, 0x3f, 0x72, ++ 0x7c, 0x00, 0xdd, 0x68, 0xaa, 0xb3, 0xf7, 0x3a, 0x81, 0x0f, 0xd2, 0xf8, ++ 0x3a, 0x34, 0x5a, 0x87, 0x1a, 0x5b, 0xac, 0xe3, 0x83, 0xd2, 0x95, 0x4c, ++ 0x53, 0x12, 0x83, 0xe7, 0xdd, 0x7b, 0xf8, 0x62, 0xdc, 0xa2, 0x4f, 0x70, ++ 0x4b, 0x8d, 0x19, 0xbb, 0x69, 0xdf, 0xbc, 0xe6, 0x75, 0x8b, 0x13, 0xf1, ++ 0xbc, 0x90, 0x71, 0xbd, 0x1d, 0x8c, 0x67, 0x48, 0x7d, 0xcd, 0x88, 0xce, ++ 0x17, 0xb1, 0x68, 0x37, 0xd6, 0x3b, 0x26, 0xe8, 0xfa, 0x58, 0x16, 0x23, ++ 0xba, 0x3e, 0xa6, 0x30, 0xba, 0xa7, 0x2e, 0xed, 0x48, 0x96, 0xed, 0x4d, ++ 0x1d, 0x35, 0x20, 0xa8, 0x77, 0x8f, 0x19, 0xfc, 0x79, 0xb1, 0x03, 0x48, ++ 0x2f, 0xbb, 0x71, 0xbd, 0xbb, 0x53, 0x6f, 0x70, 0x61, 0x1c, 0x6c, 0x51, ++ 0xa2, 0x95, 0xde, 0x3f, 0x3d, 0x16, 0xef, 0xcf, 0x0e, 0x7b, 0xe7, 0x83, ++ 0xde, 0x23, 0x92, 0x71, 0xac, 0x07, 0x4c, 0x3c, 0xae, 0x14, 0x3e, 0x2f, ++ 0x65, 0xdc, 0x6e, 0xfe, 0x7b, 0x18, 0x66, 0xe6, 0xc3, 0xfd, 0x09, 0xfc, ++ 0xfd, 0xe3, 0x3c, 0xe4, 0x67, 0x7c, 0x37, 0x47, 0xa1, 0x77, 0xa0, 0xbb, ++ 0x90, 0xef, 0x4d, 0x85, 0x1e, 0x57, 0xa4, 0xfe, 0x1b, 0x45, 0xbf, 0x7b, ++ 0xbe, 0xe7, 0xfe, 0xae, 0x0f, 0xd6, 0x83, 0xf7, 0x1b, 0x7b, 0x8d, 0xe3, ++ 0x10, 0xe3, 0x44, 0xf3, 0x71, 0xa4, 0xfe, 0xe8, 0xf9, 0xbd, 0xe5, 0x64, ++ 0xa6, 0x1b, 0x6f, 0x7a, 0x3f, 0xce, 0xcf, 0xef, 0xda, 0x35, 0x9a, 0x7f, ++ 0xbd, 0x21, 0x9e, 0xe4, 0x4d, 0x9a, 0xd5, 0xeb, 0x41, 0x7c, 0xc9, 0xb8, ++ 0x8e, 0xf4, 0x03, 0xf7, 0xe4, 0x7c, 0x3e, 0x90, 0xfc, 0xf5, 0xef, 0x1a, ++ 0x32, 0xd1, 0x3e, 0xa7, 0x77, 0x08, 0xd0, 0xfe, 0xbe, 0x8a, 0xcb, 0xa5, ++ 0x77, 0x4d, 0x2e, 0x7a, 0x77, 0xf7, 0xdd, 0x82, 0x1c, 0x8a, 0xdf, 0x4b, ++ 0x79, 0x7b, 0xfd, 0x38, 0x1e, 0xff, 0xba, 0x5e, 0xc6, 0xbb, 0xf2, 0xc3, ++ 0xe2, 0x5d, 0x61, 0xf1, 0x16, 0x96, 0x1f, 0x39, 0xfe, 0xc5, 0x98, 0xdb, ++ 0x84, 0xe3, 0x5e, 0xc2, 0x3e, 0x92, 0xf0, 0xa1, 0x38, 0xcb, 0x8e, 0x7c, ++ 0x23, 0xe1, 0x5d, 0xfe, 0xbe, 0xd2, 0x0e, 0xe1, 0x7f, 0x9e, 0x2a, 0x4e, ++ 0xcc, 0x45, 0x3a, 0xff, 0x5d, 0x3f, 0x55, 0x77, 0xae, 0x40, 0xa6, 0x6b, ++ 0x44, 0x7c, 0xb4, 0x39, 0xec, 0xbd, 0xeb, 0x35, 0xb9, 0xcb, 0x1c, 0x78, ++ 0x1e, 0xc0, 0xf2, 0x3c, 0xdf, 0xef, 0xbd, 0xbf, 0x30, 0x7a, 0x7e, 0xe8, ++ 0x39, 0xf4, 0x27, 0x07, 0xf1, 0xf3, 0x29, 0xee, 0xc1, 0x05, 0x9b, 0x11, ++ 0x4e, 0xc3, 0x6c, 0xfe, 0x42, 0x52, 0xcb, 0x9a, 0xd1, 0x85, 0xf3, 0x56, ++ 0xc4, 0x3a, 0x2e, 0x73, 0x00, 0x9c, 0x0d, 0x68, 0x6f, 0x7a, 0x44, 0x9c, ++ 0xd3, 0x6d, 0xe5, 0xf1, 0xa5, 0x89, 0xa4, 0x97, 0x25, 0x7e, 0x2f, 0x54, ++ 0x2f, 0x3f, 0x6b, 0xf4, 0xaf, 0x8c, 0xc6, 0x75, 0x26, 0xf2, 0xdf, 0x19, ++ 0xb0, 0xaf, 0xb3, 0x92, 0xdc, 0x54, 0x5b, 0xb5, 0x00, 0x1e, 0x89, 0xfe, ++ 0x72, 0xd0, 0x8c, 0x55, 0x48, 0xb7, 0xcc, 0xe8, 0x19, 0x8a, 0xe3, 0x74, ++ 0xe4, 0x45, 0x33, 0x1b, 0xd4, 0xff, 0xb6, 0xc3, 0x4c, 0xf1, 0xa7, 0xd7, ++ 0x0d, 0xe5, 0xbf, 0xc6, 0xf3, 0xea, 0xdd, 0x7f, 0xb3, 0x30, 0x3c, 0xdf, ++ 0xd0, 0x6a, 0xcf, 0x30, 0xa2, 0x71, 0xdb, 0xfa, 0x3d, 0xff, 0x5d, 0xab, ++ 0x56, 0xfb, 0x84, 0xc9, 0xfc, 0xdd, 0x49, 0x16, 0x83, 0xef, 0x63, 0x8e, ++ 0x74, 0xb0, 0xa7, 0x5f, 0x44, 0xe4, 0x88, 0x7b, 0x61, 0xad, 0x0a, 0xdb, ++ 0xc3, 0x1f, 0x69, 0xd5, 0x62, 0xf0, 0x7d, 0xb7, 0x56, 0x03, 0x3b, 0x7d, ++ 0x35, 0xcc, 0xeb, 0x25, 0xdb, 0xa8, 0x07, 0x2f, 0x27, 0x12, 0xf3, 0xa8, ++ 0xb8, 0xce, 0x67, 0x07, 0x7a, 0xd7, 0xe1, 0x3c, 0xf2, 0x58, 0x2d, 0xe5, ++ 0xef, 0x37, 0x7b, 0xe6, 0x6f, 0x80, 0x71, 0xef, 0x77, 0x5a, 0x89, 0x2e, ++ 0x0a, 0x07, 0x7a, 0x1e, 0xe7, 0xf3, 0x64, 0xab, 0xa6, 0xc2, 0xfc, 0xae, ++ 0x2a, 0x52, 0xe8, 0xf7, 0xd6, 0x56, 0x89, 0xdf, 0x77, 0xb0, 0xbb, 0xa3, ++ 0x75, 0xef, 0xec, 0x7a, 0xce, 0x0c, 0x26, 0x3d, 0xf1, 0x4c, 0x3f, 0xae, ++ 0x57, 0x1b, 0x53, 0xb5, 0x4e, 0xbc, 0xd0, 0xd1, 0x27, 0xdc, 0x1c, 0xc6, ++ 0x6e, 0xdd, 0xfb, 0x58, 0x2c, 0x93, 0xe2, 0x72, 0x12, 0x8e, 0xa1, 0xf8, ++ 0x72, 0xe4, 0xe9, 0xf0, 0xe5, 0x35, 0x85, 0xe2, 0xab, 0xe7, 0x77, 0x6b, ++ 0x24, 0xbe, 0xf8, 0xef, 0xd6, 0x5c, 0x28, 0xbe, 0xea, 0xfa, 0x31, 0x9a, ++ 0xaf, 0xa4, 0x47, 0x5f, 0xa1, 0x6b, 0xed, 0xc4, 0x5c, 0xae, 0xbf, 0x1a, ++ 0xa8, 0x96, 0x23, 0x17, 0xfb, 0xdf, 0x11, 0x9d, 0x31, 0x2c, 0xf4, 0x77, ++ 0x01, 0x24, 0x3d, 0x4a, 0xfa, 0x8c, 0x40, 0x97, 0x4b, 0x77, 0xa2, 0xdc, ++ 0xcd, 0x32, 0x38, 0x30, 0xfe, 0x79, 0xcf, 0xd4, 0x68, 0xd2, 0x63, 0x92, ++ 0x4e, 0x25, 0x7d, 0x7e, 0x9c, 0xd3, 0x43, 0xa7, 0x43, 0xfa, 0x63, 0x1c, ++ 0xde, 0xe6, 0x99, 0x84, 0xb2, 0x22, 0x9c, 0x4e, 0x31, 0xbe, 0x15, 0x4a, ++ 0x8f, 0xa5, 0x7d, 0xd2, 0x2d, 0x73, 0x84, 0xf2, 0xe5, 0x34, 0xb0, 0x13, ++ 0xe2, 0x9c, 0x68, 0xd7, 0x1c, 0xd9, 0xd8, 0x1a, 0x42, 0x8f, 0xa5, 0xb5, ++ 0x5f, 0x19, 0xb9, 0x9c, 0x38, 0x7b, 0x75, 0x74, 0x5e, 0x30, 0x1e, 0x37, ++ 0x2d, 0x5f, 0x61, 0x9f, 0x86, 0xe2, 0x15, 0xfe, 0xfb, 0x74, 0xa8, 0x58, ++ 0x1f, 0xd9, 0x35, 0x46, 0xf2, 0xa7, 0x24, 0xfc, 0x2e, 0x14, 0xce, 0xa6, ++ 0x1b, 0xeb, 0x87, 0xa2, 0x9d, 0xb6, 0x1a, 0xef, 0x0d, 0x02, 0xbc, 0x9a, ++ 0x14, 0xb7, 0x96, 0x02, 0xfd, 0x19, 0x6b, 0x0f, 0xdc, 0x81, 0xdf, 0x57, ++ 0x89, 0x7b, 0xbb, 0xbe, 0x61, 0x66, 0x6e, 0x3f, 0x09, 0xfe, 0x90, 0xfd, ++ 0x7d, 0x39, 0xa8, 0xf0, 0x38, 0xd2, 0xa3, 0x7d, 0xec, 0x89, 0x98, 0x4a, ++ 0xa8, 0xf7, 0x6d, 0xb2, 0xc1, 0x85, 0xc0, 0x59, 0xe5, 0x2a, 0x7f, 0x91, ++ 0xf8, 0x6d, 0x5f, 0x0c, 0xbd, 0x37, 0x11, 0x9b, 0xd0, 0x39, 0xff, 0x69, ++ 0xe2, 0x9f, 0x21, 0x0c, 0xf7, 0xf3, 0xbe, 0x5d, 0xe0, 0xed, 0x87, 0xfb, ++ 0xea, 0xf7, 0x02, 0x9e, 0x3e, 0xa5, 0xfb, 0x39, 0xfe, 0x14, 0xfe, 0xee, ++ 0x61, 0x57, 0x0a, 0x7f, 0x5f, 0xd6, 0x25, 0xde, 0xa1, 0xf7, 0xa6, 0xf2, ++ 0xef, 0x4c, 0x94, 0xfb, 0x29, 0x7f, 0x47, 0x4e, 0x7f, 0xe1, 0x57, 0x68, ++ 0xa2, 0x7e, 0x17, 0xd5, 0xbf, 0xd7, 0xdc, 0x62, 0x8d, 0xc6, 0x71, 0x72, ++ 0xac, 0x8e, 0xa7, 0x42, 0xe8, 0xfc, 0x6a, 0x11, 0x1f, 0xff, 0x1f, 0xc1, ++ 0x80, 0x23, 0x7d, 0x00, 0x80, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d, 0x0d, 0x78, 0x54, 0xd5, ++ 0xb5, 0xe8, 0x3e, 0x33, 0x67, 0x7e, 0x33, 0x09, 0x27, 0xc9, 0x24, 0x0c, ++ 0xf9, 0x81, 0x33, 0xc9, 0x24, 0x84, 0x64, 0x02, 0x93, 0x04, 0x10, 0x44, ++ 0x65, 0x12, 0x02, 0x0d, 0x08, 0x3a, 0xfc, 0xd5, 0x20, 0x89, 0x0c, 0x8a, ++ 0xde, 0xa8, 0x24, 0x93, 0x42, 0x6c, 0xa3, 0xd7, 0x77, 0x33, 0x90, 0x80, ++ 0x01, 0xec, 0x2d, 0xa2, 0xb5, 0x68, 0x79, 0x3a, 0xd0, 0x42, 0xf1, 0xaf, ++ 0x37, 0x28, 0xa5, 0xa1, 0x8d, 0x74, 0x12, 0x7e, 0x2e, 0x5a, 0x2a, 0x83, ++ 0xd5, 0x16, 0x5b, 0xb5, 0x81, 0xfa, 0xac, 0xb6, 0x05, 0x82, 0x78, 0x5b, ++ 0xbc, 0x97, 0x96, 0xbb, 0xd6, 0xda, 0xe7, 0x64, 0xe6, 0x4c, 0x26, 0x80, ++ 0xf6, 0xbe, 0xbe, 0xef, 0xdd, 0xf7, 0xe6, 0x5e, 0xbb, 0xb3, 0xcf, 0xde, ++ 0x67, 0xff, 0xac, 0xbd, 0xfe, 0xd7, 0xda, 0x87, 0x1c, 0x59, 0xc7, 0x58, ++ 0x06, 0x63, 0xec, 0x52, 0xbb, 0x3c, 0x3f, 0x99, 0xb1, 0x1c, 0x59, 0xa0, ++ 0xfa, 0xe3, 0x6d, 0x5b, 0x7d, 0x1f, 0xb8, 0x18, 0xdb, 0xd0, 0x16, 0xa2, ++ 0x32, 0x7d, 0x6e, 0x88, 0xf9, 0x4b, 0x19, 0xb3, 0x16, 0x05, 0xe5, 0x20, ++ 0xf4, 0x33, 0xaf, 0x65, 0xfe, 0x2e, 0x1b, 0x63, 0x97, 0xf1, 0x37, 0x3d, ++ 0x5a, 0x3e, 0xe0, 0x14, 0x19, 0x9b, 0x04, 0xed, 0x7d, 0x4f, 0x31, 0x19, ++ 0xfa, 0xa5, 0xbb, 0x3c, 0x82, 0x1f, 0xfa, 0xd9, 0xe7, 0xc2, 0x78, 0x45, ++ 0x8c, 0x7e, 0x97, 0xe1, 0xbf, 0x5b, 0x18, 0x0b, 0x8e, 0x28, 0x87, 0x7e, ++ 0x3b, 0x98, 0x97, 0x4d, 0x64, 0x6c, 0x9d, 0x6c, 0x0d, 0x05, 0x85, 0xa1, ++ 0xe3, 0xdd, 0x92, 0x51, 0x75, 0x54, 0x4c, 0x19, 0xfa, 0x7c, 0xb0, 0xfd, ++ 0x06, 0x81, 0x9d, 0x36, 0x47, 0xc7, 0xc5, 0xdf, 0x69, 0x75, 0x1e, 0x3d, ++ 0x8c, 0xff, 0x57, 0xbd, 0xbf, 0xcb, 0x8d, 0x35, 0x87, 0x8e, 0x65, 0x32, ++ 0xd6, 0x82, 0x7d, 0x65, 0xc6, 0xaa, 0xf3, 0xe0, 0x0f, 0x9c, 0xb7, 0xd5, ++ 0xb8, 0xdd, 0x04, 0xf3, 0x4e, 0x96, 0x53, 0x69, 0xdf, 0x9f, 0xda, 0xab, ++ 0x46, 0x30, 0xf7, 0xf0, 0xf3, 0x3d, 0xd3, 0x06, 0x0b, 0x2f, 0x64, 0x2c, ++ 0xd4, 0x66, 0xa6, 0x72, 0x47, 0x9b, 0xc4, 0x82, 0x46, 0xc6, 0xbe, 0xdb, ++ 0xe6, 0xa0, 0xfa, 0xae, 0x36, 0x99, 0xca, 0xdd, 0x6d, 0x45, 0x54, 0x3e, ++ 0xdf, 0xe6, 0xa1, 0xf6, 0x17, 0xdb, 0xa6, 0x50, 0xfd, 0xfb, 0x6d, 0x5e, ++ 0xaa, 0x77, 0xb5, 0xd5, 0x50, 0xfd, 0xe5, 0x36, 0x1f, 0xd5, 0xf7, 0xb6, ++ 0xd5, 0x52, 0x7d, 0x5f, 0x9b, 0x9f, 0xca, 0xee, 0xb6, 0x06, 0x2a, 0x7f, ++ 0xd4, 0xd6, 0x4c, 0xed, 0x3d, 0x6d, 0xad, 0x54, 0x9f, 0x6e, 0x62, 0xcd, ++ 0xb4, 0x9f, 0xa2, 0xa0, 0x63, 0x01, 0x9c, 0x47, 0xe7, 0x83, 0x46, 0xaf, ++ 0x0c, 0xf0, 0x69, 0x54, 0xce, 0xf1, 0xa0, 0x37, 0x2f, 0xdd, 0x63, 0x67, ++ 0xcc, 0x52, 0xa4, 0x63, 0x26, 0xe8, 0x66, 0x39, 0xb6, 0x85, 0xe1, 0x7e, ++ 0x2c, 0x0e, 0x9d, 0x37, 0x04, 0xe7, 0xb0, 0xde, 0xb1, 0x85, 0xdd, 0x05, ++ 0xa5, 0x61, 0x72, 0x72, 0xa7, 0x30, 0x02, 0xf6, 0xff, 0x92, 0xad, 0x53, ++ 0x98, 0x00, 0xed, 0xe2, 0xe3, 0x4c, 0x86, 0xe7, 0xcf, 0x08, 0xc1, 0x06, ++ 0xe6, 0x61, 0x6c, 0x91, 0x3c, 0xd6, 0x27, 0x8e, 0x62, 0xcc, 0xe5, 0xf8, ++ 0x4a, 0x55, 0x1a, 0xd4, 0x6f, 0x97, 0x4b, 0x37, 0x9b, 0x9d, 0x8c, 0x15, ++ 0xca, 0xf3, 0x6b, 0xd7, 0xc4, 0xd4, 0xe5, 0xe4, 0xf2, 0xfb, 0xf6, 0x48, ++ 0xd1, 0xfa, 0x18, 0xf7, 0x76, 0xd1, 0x0a, 0xed, 0xcb, 0x42, 0x13, 0x36, ++ 0xdb, 0x05, 0xbe, 0x0e, 0x96, 0xc5, 0xd8, 0xbd, 0x72, 0xb9, 0x6f, 0x0d, ++ 0xe0, 0x51, 0x38, 0x8f, 0x05, 0x11, 0xee, 0x03, 0x4e, 0x63, 0x68, 0x07, ++ 0xb4, 0xaf, 0xc0, 0xf3, 0x12, 0x71, 0xfd, 0x12, 0xad, 0xff, 0x66, 0xd6, ++ 0xee, 0xd0, 0xc1, 0xfa, 0xc7, 0xc8, 0xc6, 0x72, 0x26, 0x50, 0xff, 0x30, ++ 0xb3, 0x5f, 0x7b, 0xff, 0x46, 0x59, 0xa6, 0xe7, 0xf1, 0xef, 0x5d, 0xa9, ++ 0x9f, 0x6e, 0xe2, 0x35, 0xf5, 0x63, 0xfa, 0x2b, 0x8c, 0x87, 0xed, 0xc2, ++ 0x15, 0xc6, 0x31, 0x0b, 0x0b, 0xcd, 0x11, 0x58, 0xfb, 0x26, 0x03, 0xfc, ++ 0x0f, 0x3c, 0x0f, 0x66, 0xd8, 0x42, 0x3b, 0x01, 0x5e, 0x9d, 0x06, 0xb6, ++ 0xcc, 0x07, 0x70, 0xef, 0xb4, 0xf0, 0xf2, 0x88, 0x93, 0xd3, 0xdf, 0xb3, ++ 0xce, 0xaa, 0xf1, 0x4e, 0xa0, 0xa3, 0xf1, 0x4e, 0x7e, 0xae, 0x9d, 0x96, ++ 0xa0, 0x54, 0x85, 0xf3, 0x97, 0xea, 0x3c, 0x3b, 0x10, 0x9d, 0x5b, 0x9d, ++ 0x3f, 0xcf, 0x83, 0xf9, 0xbe, 0xfa, 0xba, 0xc8, 0x36, 0xca, 0x51, 0xfc, ++ 0xec, 0x40, 0x3c, 0x80, 0xf7, 0x0a, 0xc6, 0x24, 0x7b, 0x71, 0x1e, 0xf6, ++ 0x8f, 0xe6, 0x50, 0x01, 0xcc, 0xf3, 0xa5, 0x31, 0x2f, 0x75, 0xa4, 0x41, ++ 0xbd, 0xe0, 0x3b, 0x1e, 0x8f, 0x1e, 0xfa, 0x6f, 0x62, 0x1e, 0x2b, 0xe2, ++ 0x49, 0xf0, 0x51, 0x1d, 0xdb, 0x09, 0xf5, 0x17, 0x26, 0xe6, 0xa7, 0xcd, ++ 0x87, 0xee, 0x25, 0x93, 0x7e, 0x90, 0xe6, 0x07, 0x7c, 0x39, 0x8d, 0x7c, ++ 0x00, 0xc6, 0x09, 0x31, 0x56, 0x83, 0xf8, 0xb6, 0x66, 0xdd, 0x3d, 0x63, ++ 0xfa, 0xa1, 0xfc, 0xd3, 0x09, 0xff, 0x18, 0x09, 0xd6, 0xf9, 0xb8, 0x32, ++ 0xcf, 0x76, 0x43, 0xa4, 0x99, 0xce, 0x73, 0x92, 0x8d, 0xe1, 0xbe, 0x19, ++ 0xdb, 0x9c, 0xa4, 0x73, 0x40, 0x7f, 0x07, 0x1c, 0xd2, 0x75, 0x8c, 0xe9, ++ 0x46, 0xf1, 0xd2, 0x68, 0x90, 0x6e, 0xc7, 0x7e, 0xc6, 0x75, 0x46, 0x16, ++ 0x84, 0xf5, 0x18, 0xff, 0x72, 0x9d, 0xd9, 0x07, 0xe3, 0xb5, 0x5f, 0x34, ++ 0xd5, 0x20, 0x1f, 0x61, 0x2c, 0x92, 0xa4, 0x9b, 0x02, 0xcf, 0x2d, 0x7e, ++ 0x29, 0x15, 0x9e, 0x6f, 0x0e, 0xea, 0x88, 0x2f, 0xb4, 0xcb, 0xb6, 0x90, ++ 0x00, 0xe3, 0x6e, 0xb2, 0x95, 0x1f, 0x95, 0xa1, 0x1e, 0x94, 0x74, 0x9e, ++ 0x02, 0x84, 0xa3, 0x5b, 0x47, 0x70, 0xec, 0xb0, 0x7d, 0x39, 0xa4, 0x87, ++ 0xf1, 0x44, 0x61, 0x4d, 0x03, 0xcb, 0x87, 0xf5, 0x4a, 0x2f, 0x9b, 0x9d, ++ 0xf0, 0x3c, 0xe4, 0xd6, 0x49, 0x48, 0xe7, 0x21, 0xef, 0x82, 0x1a, 0xac, ++ 0x07, 0xfd, 0xa2, 0xa7, 0x40, 0x56, 0x18, 0x04, 0xb6, 0xfb, 0xd3, 0x42, ++ 0x1b, 0x71, 0x5c, 0x36, 0xf0, 0xd3, 0x09, 0xd8, 0x5e, 0xc7, 0x3c, 0x08, ++ 0x87, 0x75, 0x99, 0xff, 0xde, 0x97, 0x04, 0xf5, 0xf6, 0xc5, 0x92, 0x47, ++ 0xcf, 0x7b, 0xcb, 0xe2, 0x64, 0xc6, 0x46, 0xe1, 0x5f, 0x30, 0x65, 0xbb, ++ 0xa1, 0x7f, 0x6d, 0x12, 0xae, 0x63, 0x09, 0xef, 0x0f, 0x7f, 0x79, 0xe6, ++ 0x03, 0x1d, 0xa6, 0x98, 0xf8, 0xf9, 0x7d, 0xa3, 0x77, 0xb6, 0x94, 0x57, ++ 0x8a, 0xcf, 0xc5, 0x60, 0x3f, 0xe7, 0x4b, 0xc2, 0x65, 0x20, 0x44, 0xd1, ++ 0xe0, 0x31, 0x7b, 0xa0, 0x7d, 0xbc, 0xad, 0xbc, 0xc6, 0x0b, 0xa5, 0x98, ++ 0x5c, 0x6e, 0x96, 0x61, 0x9f, 0x1d, 0x52, 0xb9, 0x79, 0x39, 0xed, 0x9f, ++ 0xd9, 0x18, 0xcc, 0x93, 0xce, 0x38, 0x7f, 0x6a, 0x97, 0x74, 0x35, 0x21, ++ 0xa5, 0xfd, 0x2e, 0xa4, 0x77, 0x91, 0x1d, 0x72, 0x4d, 0x26, 0x52, 0xa2, ++ 0xf6, 0x0e, 0xdb, 0x96, 0x5e, 0x84, 0x87, 0x78, 0x37, 0x63, 0x4e, 0x19, ++ 0xd7, 0x07, 0xf3, 0xa9, 0x7c, 0x0f, 0xe0, 0x61, 0xce, 0xbf, 0xe1, 0xa8, ++ 0x0c, 0xfb, 0xe8, 0xbc, 0x27, 0x8d, 0xf6, 0x21, 0x0a, 0x1e, 0xaa, 0xb3, ++ 0xbb, 0x45, 0x5a, 0x77, 0x96, 0x6c, 0x0d, 0xb3, 0xf1, 0x70, 0x8e, 0xc6, ++ 0x79, 0x47, 0x19, 0xf0, 0x8f, 0x2c, 0xf3, 0xfd, 0x73, 0xb1, 0x3e, 0xaa, ++ 0x41, 0xfc, 0xa0, 0x3f, 0x86, 0x4f, 0x8f, 0xf4, 0x6b, 0xeb, 0x19, 0xb5, ++ 0xda, 0x7a, 0x3a, 0x83, 0xba, 0x39, 0x3a, 0xef, 0x6f, 0x14, 0xf9, 0x11, ++ 0x0f, 0xb7, 0x78, 0x78, 0x8c, 0x92, 0x3a, 0x4e, 0xe0, 0xfa, 0x47, 0xf9, ++ 0x45, 0x7a, 0x18, 0xbf, 0xfe, 0xa7, 0xa4, 0x27, 0x52, 0x2b, 0x19, 0xae, ++ 0xd3, 0x46, 0xeb, 0xcc, 0xb4, 0xdd, 0x59, 0x09, 0x10, 0x82, 0xa1, 0x7d, ++ 0x6b, 0x10, 0xff, 0xfe, 0xd6, 0x75, 0x8e, 0x97, 0x16, 0x98, 0x9d, 0x30, ++ 0xff, 0x78, 0xbb, 0x0e, 0xc1, 0xc9, 0x26, 0xb0, 0x81, 0xb5, 0x38, 0xee, ++ 0x26, 0x05, 0xdf, 0x3b, 0x9d, 0xfc, 0x3c, 0xa3, 0x74, 0xa5, 0x57, 0xe9, ++ 0x72, 0x24, 0xd2, 0xe5, 0x98, 0x56, 0x1d, 0x0b, 0xc6, 0xc8, 0x1d, 0x67, ++ 0xd0, 0xca, 0x82, 0x31, 0xf3, 0xe5, 0x77, 0xa6, 0x69, 0xea, 0x05, 0x9b, ++ 0xb3, 0x34, 0xfd, 0xc7, 0x6e, 0xcd, 0xd3, 0xb4, 0x8f, 0x0b, 0x15, 0x6b, ++ 0xda, 0x4b, 0x76, 0x97, 0x6b, 0xea, 0xa5, 0x5d, 0xd7, 0x6b, 0xfa, 0x4f, ++ 0xe8, 0xae, 0xd2, 0xd4, 0xcb, 0xc2, 0x73, 0x34, 0xfd, 0x2b, 0x8e, 0x2e, ++ 0xd0, 0xd4, 0x27, 0x45, 0x6e, 0xd7, 0xf4, 0xbf, 0xee, 0xe4, 0x9d, 0x9a, ++ 0xf6, 0xa9, 0xfd, 0xf7, 0x69, 0xda, 0xa7, 0x7d, 0xb4, 0x4a, 0x53, 0xbf, ++ 0x71, 0xe0, 0x21, 0x4d, 0x7f, 0x20, 0xe3, 0x86, 0xae, 0x04, 0x72, 0x32, ++ 0x55, 0xe1, 0x57, 0x1d, 0x0e, 0x6f, 0xc4, 0x9b, 0x40, 0x9e, 0xab, 0x25, ++ 0x93, 0xc4, 0x81, 0xc1, 0xf3, 0x00, 0xde, 0x69, 0x72, 0x00, 0x66, 0xc7, ++ 0xcc, 0x97, 0xec, 0xb1, 0x02, 0x12, 0x47, 0xeb, 0xa0, 0x99, 0x48, 0x1f, ++ 0x26, 0x29, 0x75, 0x92, 0xeb, 0xed, 0xf2, 0x5a, 0xc4, 0xe7, 0x14, 0x23, ++ 0xe1, 0xb3, 0x88, 0xf2, 0x1c, 0xea, 0xab, 0x1e, 0x34, 0x86, 0x4c, 0x88, ++ 0xff, 0x37, 0x79, 0x64, 0xe4, 0x2f, 0x26, 0x27, 0xe7, 0x63, 0xfb, 0x0a, ++ 0xbd, 0xa3, 0x9d, 0xb0, 0xae, 0xca, 0x14, 0x33, 0xc9, 0x05, 0xd1, 0xc6, ++ 0xfb, 0x89, 0xb6, 0x59, 0xa4, 0xa7, 0x8c, 0xde, 0x0a, 0x7c, 0xa9, 0x02, ++ 0xea, 0x12, 0x1b, 0x6c, 0x4f, 0x42, 0xfe, 0xdc, 0x16, 0xf4, 0xb9, 0x5c, ++ 0xd1, 0x75, 0x5b, 0xa4, 0xcd, 0x0c, 0xe9, 0xb7, 0x32, 0xa5, 0x86, 0xf5, ++ 0xdb, 0xa2, 0xef, 0x8b, 0x92, 0x97, 0xf9, 0x93, 0x71, 0x3e, 0x99, 0xeb, ++ 0x3f, 0x52, 0x90, 0xfa, 0x59, 0x64, 0x78, 0x3f, 0x66, 0x5f, 0x07, 0x74, ++ 0x3a, 0x66, 0x43, 0x3e, 0xde, 0x0b, 0x72, 0x02, 0xc6, 0xef, 0x4a, 0xce, ++ 0x16, 0x91, 0xfe, 0xba, 0xfe, 0x52, 0x5c, 0x4d, 0x65, 0xf2, 0xb4, 0x59, ++ 0x88, 0xef, 0x65, 0x12, 0xfb, 0xce, 0xbf, 0x40, 0xff, 0x2e, 0x81, 0x1d, ++ 0x65, 0xa0, 0x27, 0x75, 0xe9, 0xd8, 0x85, 0xe9, 0xb0, 0xef, 0x97, 0x6d, ++ 0xe5, 0x8f, 0x83, 0xb8, 0x06, 0xd6, 0xe8, 0xd3, 0x23, 0xbf, 0x9b, 0xcc, ++ 0x9a, 0xa9, 0x1c, 0xad, 0x63, 0x56, 0x2c, 0xb7, 0x0b, 0xfd, 0xab, 0x19, ++ 0xf4, 0x73, 0x37, 0x9f, 0xa8, 0x1a, 0x09, 0xfd, 0x9e, 0x77, 0xf9, 0xbd, ++ 0xb8, 0xef, 0xaf, 0x83, 0x0e, 0x81, 0xfb, 0xfa, 0xfa, 0x78, 0xae, 0x67, ++ 0xad, 0xcb, 0x9c, 0x23, 0xa3, 0x5e, 0xd6, 0xe9, 0xec, 0x3a, 0x9a, 0x87, ++ 0xeb, 0xc9, 0x00, 0xb9, 0x82, 0x84, 0x20, 0xfa, 0x3c, 0xa8, 0x57, 0xa8, ++ 0xfb, 0xbd, 0x4f, 0x39, 0x4f, 0x31, 0xaf, 0xb3, 0x1f, 0xe5, 0xdf, 0xaa, ++ 0x54, 0xb3, 0x8c, 0xfa, 0x92, 0x68, 0xde, 0xec, 0xfb, 0x00, 0xe0, 0xf5, ++ 0x8c, 0xa1, 0xff, 0xb9, 0x76, 0xa8, 0x77, 0x08, 0xd2, 0xca, 0x2e, 0xe4, ++ 0x8b, 0x0f, 0xda, 0x3c, 0x3b, 0x19, 0xea, 0x8f, 0x1c, 0x6e, 0x72, 0xb2, ++ 0xae, 0x62, 0x2d, 0x8c, 0xdb, 0xb5, 0xc6, 0x2b, 0xa6, 0x42, 0x7b, 0xd7, ++ 0x06, 0xe6, 0xe9, 0x40, 0xfa, 0xb0, 0x57, 0xae, 0x4d, 0x85, 0xe7, 0x05, ++ 0x39, 0xcb, 0x75, 0x69, 0x48, 0x0f, 0xae, 0x35, 0x6b, 0xb1, 0xac, 0x73, ++ 0xe6, 0x11, 0xfc, 0xc6, 0xb9, 0xb7, 0xeb, 0xd2, 0xa1, 0xbd, 0x64, 0x62, ++ 0x65, 0x2d, 0x43, 0xd9, 0x2b, 0xc1, 0x7c, 0xe9, 0xc3, 0xe3, 0x93, 0x3e, ++ 0x65, 0x2b, 0xc3, 0xfd, 0x30, 0x97, 0xf8, 0x21, 0xe2, 0x95, 0x4e, 0x06, ++ 0x3e, 0x03, 0x4b, 0xaf, 0x4c, 0x83, 0xf3, 0x86, 0x79, 0x2d, 0x78, 0xde, ++ 0x02, 0x95, 0x04, 0x07, 0xcb, 0x45, 0x5b, 0xc8, 0x82, 0x75, 0x17, 0x87, ++ 0x8b, 0xc5, 0x2b, 0x84, 0x92, 0xa0, 0x6e, 0x77, 0x79, 0x05, 0xaf, 0x1b, ++ 0xdf, 0xdb, 0x4a, 0xe7, 0x6b, 0x09, 0x6b, 0xf5, 0xd8, 0x2a, 0x97, 0xff, ++ 0x3e, 0xa4, 0x7f, 0xfb, 0x5c, 0xed, 0xb9, 0x8a, 0xe6, 0x27, 0x68, 0x7d, ++ 0x9b, 0x74, 0x9c, 0x2e, 0x3a, 0x53, 0xe5, 0x63, 0x28, 0x9f, 0x3b, 0x9d, ++ 0xae, 0xb4, 0x76, 0x39, 0xba, 0x4e, 0x95, 0xaf, 0x3c, 0xa0, 0xe8, 0x6b, ++ 0xea, 0x73, 0x95, 0xaf, 0xfc, 0x0e, 0xcf, 0x20, 0x23, 0xaa, 0xdf, 0x00, ++ 0x9e, 0x6f, 0xd5, 0xe5, 0xa3, 0x7e, 0xb6, 0x99, 0x21, 0x7f, 0xb2, 0x3c, ++ 0xbc, 0x99, 0x21, 0x5e, 0x5b, 0xa4, 0xa0, 0xcc, 0x50, 0x0f, 0xff, 0xa7, ++ 0x20, 0xe1, 0xb9, 0xaa, 0xdf, 0xae, 0x56, 0x68, 0xa6, 0x3a, 0xaf, 0xd6, ++ 0x8c, 0xf2, 0xfa, 0x82, 0xbd, 0x9c, 0xf4, 0x59, 0x4b, 0xeb, 0x2e, 0x3a, ++ 0xaf, 0x78, 0xb8, 0x59, 0xfa, 0x75, 0xcc, 0x7b, 0x05, 0xb8, 0xa6, 0x14, ++ 0x3e, 0x4d, 0xf2, 0x1d, 0x18, 0xb0, 0x5c, 0x00, 0xf0, 0xe9, 0xcb, 0xb4, ++ 0x35, 0x6c, 0x4f, 0xa0, 0xf7, 0x8f, 0x50, 0xf4, 0x85, 0x0d, 0x40, 0xc6, ++ 0x11, 0x92, 0x57, 0x3e, 0x33, 0xf2, 0x6b, 0x83, 0x1e, 0xf4, 0x55, 0x92, ++ 0x6f, 0xb0, 0x61, 0x90, 0x07, 0x17, 0x24, 0x46, 0xf2, 0x8b, 0x75, 0x39, ++ 0xa9, 0xbe, 0x3a, 0x95, 0xd7, 0xd5, 0x71, 0x56, 0x67, 0x94, 0x8f, 0xbc, ++ 0x92, 0xfe, 0x6d, 0xd9, 0x6a, 0x66, 0xfe, 0x98, 0x7d, 0x6c, 0x80, 0x79, ++ 0x10, 0x2e, 0xeb, 0x2e, 0xcd, 0xaf, 0x41, 0xb8, 0x32, 0x91, 0x88, 0x83, ++ 0x6d, 0xfa, 0x8b, 0x7b, 0xfb, 0x46, 0xa0, 0x2f, 0xd5, 0xae, 0x19, 0xa1, ++ 0xe8, 0x2b, 0x39, 0x38, 0x37, 0x94, 0xa3, 0x8d, 0x8c, 0xec, 0x02, 0x8f, ++ 0x7d, 0x6e, 0x0d, 0xd2, 0x9d, 0xef, 0x62, 0x1e, 0x09, 0xdf, 0x83, 0xce, ++ 0x34, 0x6a, 0xf7, 0x04, 0x99, 0xbe, 0x99, 0xd6, 0x6d, 0x50, 0xe5, 0x92, ++ 0xee, 0xf2, 0x04, 0x5a, 0xab, 0x6c, 0x54, 0xe5, 0x30, 0xa9, 0xb6, 0x5c, ++ 0x6e, 0xc1, 0xff, 0xf7, 0x5e, 0x16, 0x90, 0xef, 0xc7, 0xc8, 0x31, 0x5e, ++ 0x90, 0x5c, 0x57, 0xe5, 0x76, 0xc1, 0x66, 0x6d, 0xfb, 0xd8, 0xad, 0xda, ++ 0xfa, 0xb8, 0xd0, 0x90, 0xf7, 0xdf, 0x42, 0xb9, 0xbf, 0x98, 0xff, 0x0d, ++ 0x72, 0x41, 0xdb, 0xfe, 0xb4, 0x22, 0xbf, 0x17, 0xa3, 0xfc, 0x86, 0x92, ++ 0x2d, 0x32, 0x90, 0xdc, 0x33, 0xc3, 0x8a, 0x2e, 0x73, 0xb9, 0x1b, 0x95, ++ 0x83, 0xc0, 0x17, 0x72, 0xbb, 0xc2, 0x95, 0xc8, 0x46, 0x73, 0x5a, 0x62, ++ 0xe4, 0x21, 0xa3, 0x7d, 0x68, 0xe4, 0x63, 0x95, 0x4b, 0x26, 0xfc, 0xf3, ++ 0x1d, 0x15, 0x0d, 0x78, 0x8e, 0xbe, 0x8b, 0x60, 0x7c, 0x54, 0x0c, 0xe5, ++ 0xcb, 0xa3, 0x4d, 0x1c, 0xde, 0x7d, 0xc6, 0xe4, 0xd0, 0x5a, 0x78, 0xef, ++ 0x51, 0xb0, 0x8b, 0xfc, 0xd0, 0x75, 0x3d, 0xd8, 0x43, 0x7e, 0x20, 0xb5, ++ 0xaf, 0x8b, 0x9e, 0x5f, 0xd6, 0xa1, 0x9d, 0x75, 0x54, 0xef, 0x01, 0x8c, ++ 0x1d, 0x3c, 0xa7, 0xf8, 0x73, 0xf5, 0xe4, 0xa9, 0x7a, 0xaf, 0xef, 0x2d, ++ 0xa4, 0x03, 0xc6, 0xfa, 0x2b, 0x7c, 0xc9, 0x7c, 0x3e, 0x7f, 0xcc, 0x7c, ++ 0x7d, 0xd6, 0x94, 0xf1, 0x0c, 0xec, 0x96, 0x5d, 0x85, 0xfe, 0x5f, 0x61, ++ 0xbf, 0x4f, 0x6a, 0xec, 0x13, 0x91, 0x3f, 0x98, 0x72, 0x98, 0x01, 0xe9, ++ 0x13, 0xe7, 0x67, 0xca, 0xfc, 0xcc, 0x88, 0xfa, 0x33, 0x3f, 0xef, 0x4d, ++ 0x9e, 0x37, 0x9b, 0x0f, 0xc2, 0x3a, 0x1e, 0x39, 0x69, 0x42, 0x75, 0x9c, ++ 0xcd, 0xd4, 0x1f, 0x3b, 0xda, 0x06, 0xf5, 0x55, 0xb9, 0x22, 0xf1, 0x33, ++ 0xe9, 0xba, 0x95, 0xcf, 0x5a, 0x81, 0x0f, 0x54, 0xfd, 0x1a, 0xda, 0xe1, ++ 0x9d, 0x47, 0x64, 0x79, 0x24, 0xe9, 0xe9, 0x47, 0x0d, 0x0c, 0xf5, 0xf4, ++ 0x2a, 0x05, 0x8f, 0xab, 0x14, 0xfb, 0xeb, 0x99, 0x02, 0x03, 0x8d, 0xfb, ++ 0x89, 0x22, 0x5f, 0xce, 0x3a, 0x55, 0xbd, 0x27, 0x68, 0x45, 0xfd, 0x17, ++ 0x2c, 0x02, 0x2b, 0xea, 0xb3, 0x25, 0xbb, 0x81, 0x17, 0x6b, 0xcf, 0x33, ++ 0x89, 0xb7, 0x7b, 0x49, 0xdf, 0x2d, 0xed, 0x8a, 0x6f, 0xf7, 0x32, 0xa4, ++ 0xe3, 0x62, 0x05, 0x5f, 0xa0, 0x6e, 0xab, 0x84, 0x7a, 0x99, 0x52, 0xef, ++ 0x62, 0x42, 0xba, 0x04, 0xe7, 0x38, 0xa1, 0xb6, 0xbf, 0x0f, 0x4d, 0x09, ++ 0xf7, 0x6b, 0x87, 0xad, 0x88, 0x87, 0x7b, 0x2c, 0x5c, 0x7f, 0x7b, 0x5e, ++ 0xc1, 0x87, 0x4c, 0x26, 0x78, 0xc2, 0xb0, 0xfe, 0xcc, 0xdd, 0x36, 0x4f, ++ 0x08, 0xfa, 0x25, 0xeb, 0xd9, 0x9e, 0x08, 0xec, 0xc3, 0x73, 0x48, 0x3c, ++ 0x1d, 0x7b, 0xee, 0xe3, 0x7b, 0xb4, 0x75, 0x37, 0x8b, 0xa9, 0x3b, 0x71, ++ 0x1d, 0xda, 0xfa, 0xa3, 0x72, 0xb3, 0x80, 0x70, 0x79, 0xb4, 0x0e, 0x74, ++ 0x74, 0xd8, 0xb2, 0x35, 0x2f, 0xd9, 0xfe, 0x61, 0x09, 0x43, 0x98, 0x17, ++ 0x22, 0x7e, 0xcd, 0xd4, 0xdb, 0xca, 0xd0, 0x9e, 0x5a, 0x55, 0x69, 0x63, ++ 0x08, 0x57, 0xd3, 0xa9, 0xb1, 0xdf, 0x8a, 0x20, 0xff, 0x38, 0xa1, 0x67, ++ 0x28, 0x17, 0xa4, 0x24, 0xf9, 0xb1, 0x6a, 0x78, 0x5f, 0xfa, 0x69, 0xba, ++ 0x67, 0x8d, 0x1c, 0x3d, 0xff, 0xe7, 0xdb, 0x90, 0x75, 0x33, 0xf6, 0xe4, ++ 0x65, 0x0f, 0xeb, 0x00, 0x9e, 0xfc, 0xf5, 0x2a, 0x6b, 0x03, 0xea, 0xbf, ++ 0x2f, 0xc2, 0x79, 0xa2, 0x1c, 0xf9, 0x3e, 0xd8, 0xd9, 0xd8, 0xde, 0x05, ++ 0xe7, 0x8a, 0xf5, 0x97, 0xc1, 0xce, 0xc6, 0x72, 0x2f, 0xd8, 0xd9, 0xf8, ++ 0x7c, 0x1f, 0xd8, 0xd9, 0x58, 0xef, 0x06, 0x3b, 0x1b, 0xcb, 0x1f, 0x81, ++ 0x9d, 0x8d, 0xcf, 0x7b, 0xc0, 0xce, 0xc6, 0xba, 0xa7, 0xb0, 0x72, 0x74, ++ 0x1e, 0x9c, 0x4f, 0xbd, 0xcd, 0x37, 0x53, 0x40, 0xb8, 0x7a, 0x45, 0x59, ++ 0x02, 0xba, 0x12, 0xa2, 0x70, 0x66, 0x1f, 0x16, 0x61, 0xbd, 0x5f, 0xb8, ++ 0x0c, 0x04, 0x52, 0x27, 0xb1, 0x7e, 0x13, 0xc0, 0xf5, 0xf8, 0x18, 0x99, ++ 0xce, 0xd7, 0xc4, 0x7c, 0x0c, 0xe5, 0x2b, 0xf3, 0x7b, 0xcc, 0x88, 0x97, ++ 0x57, 0x1f, 0xc7, 0xab, 0x8e, 0xe3, 0x37, 0x24, 0x1a, 0x67, 0x0a, 0x8c, ++ 0x43, 0x76, 0x82, 0x59, 0x42, 0xbf, 0x48, 0x1e, 0xbc, 0x31, 0x02, 0x9e, ++ 0x9f, 0x79, 0xf0, 0x57, 0xbb, 0x50, 0x5e, 0xcc, 0x13, 0xfc, 0x1e, 0x5c, ++ 0x6f, 0xe3, 0xa4, 0xd3, 0x46, 0xae, 0x3f, 0x0f, 0x18, 0xb1, 0xff, 0x36, ++ 0x0b, 0xe0, 0x3f, 0xf0, 0xa1, 0x1c, 0x85, 0x0e, 0x82, 0x55, 0x00, 0x4f, ++ 0x94, 0xbb, 0xaf, 0xeb, 0x3d, 0xed, 0xd0, 0xeb, 0xa6, 0x19, 0xa7, 0x56, ++ 0x67, 0x80, 0xfd, 0x5d, 0x95, 0xe7, 0x9c, 0x2f, 0x4e, 0x85, 0xfa, 0xfd, ++ 0xa7, 0x2a, 0x46, 0x43, 0xbd, 0x73, 0xc7, 0xa6, 0xf9, 0x68, 0xcf, 0xdf, ++ 0xf4, 0xbd, 0x53, 0xaf, 0x64, 0x03, 0x0f, 0x3e, 0x9b, 0x37, 0x8f, 0xb7, ++ 0x3f, 0x7e, 0xea, 0x42, 0x0e, 0xb4, 0x8f, 0x60, 0x5f, 0x9b, 0x5f, 0x0d, ++ 0xed, 0x29, 0xe9, 0x5c, 0x3e, 0x6d, 0x13, 0x58, 0x6d, 0xac, 0x7e, 0x77, ++ 0x6b, 0x1e, 0xc7, 0xf3, 0x40, 0xeb, 0x16, 0x92, 0x73, 0xc0, 0xdf, 0x19, ++ 0xc2, 0xa1, 0x3d, 0xd3, 0x47, 0xf2, 0xf1, 0x9c, 0x7d, 0x20, 0x65, 0x39, ++ 0xf4, 0x0f, 0x64, 0x0c, 0x64, 0xde, 0x79, 0x05, 0xfe, 0x1d, 0x68, 0x7d, ++ 0x92, 0xe4, 0x50, 0x7b, 0xca, 0xef, 0x49, 0xff, 0x68, 0x1f, 0x94, 0x17, ++ 0x1e, 0x92, 0x17, 0xea, 0xbc, 0xaa, 0xbc, 0xf8, 0x44, 0xc1, 0x3d, 0x55, ++ 0x5e, 0xac, 0xb2, 0xf0, 0xea, 0x60, 0x3f, 0x7f, 0x3e, 0x3d, 0x7f, 0x5c, ++ 0xf1, 0xeb, 0xb0, 0x50, 0x01, 0xd5, 0xd3, 0x2d, 0xbc, 0xfe, 0xcf, 0x55, ++ 0xf2, 0x71, 0xb4, 0x7b, 0x00, 0x3e, 0x64, 0xe7, 0x1e, 0x4c, 0x29, 0xfe, ++ 0xc6, 0x0d, 0x68, 0x57, 0xd6, 0x88, 0x1e, 0x13, 0xd4, 0x1f, 0xb7, 0x95, ++ 0x5b, 0x50, 0xde, 0xfc, 0xa3, 0xc2, 0x7f, 0x60, 0xdc, 0x20, 0xda, 0xf1, ++ 0xc1, 0x99, 0xe6, 0xd0, 0x4e, 0x3c, 0x54, 0xbb, 0x4c, 0xf4, 0x98, 0xa6, ++ 0x8e, 0x6f, 0x77, 0xa1, 0xd2, 0xc5, 0xd2, 0x94, 0x75, 0x1c, 0xba, 0xde, ++ 0x1a, 0x46, 0x3b, 0xbf, 0xbd, 0xda, 0xbc, 0x03, 0xf5, 0xc9, 0x2d, 0xb6, ++ 0x3c, 0x1a, 0xaf, 0x7d, 0x8a, 0x31, 0x88, 0xfe, 0x15, 0xb5, 0xbe, 0xf6, ++ 0xfa, 0xeb, 0xcd, 0xa8, 0x4f, 0xa4, 0xa6, 0xa4, 0x39, 0xb1, 0xae, 0xf2, ++ 0xa7, 0x8d, 0x80, 0xf7, 0x58, 0xc2, 0x4f, 0x8f, 0xe3, 0x56, 0x29, 0xdb, ++ 0xad, 0x32, 0xdb, 0xc2, 0x7a, 0xe4, 0xe7, 0x66, 0xc3, 0x1f, 0x63, 0xf5, ++ 0x64, 0x1b, 0x8b, 0x10, 0xfe, 0x78, 0x74, 0x60, 0x90, 0x00, 0xbd, 0x19, ++ 0xf3, 0x39, 0x5e, 0x55, 0x30, 0x4f, 0x2d, 0x3e, 0x37, 0x0a, 0xcd, 0x41, ++ 0x44, 0xc6, 0x6d, 0xb8, 0x76, 0xdc, 0x47, 0xb2, 0x91, 0xfc, 0x0c, 0x8c, ++ 0x65, 0xf3, 0x75, 0xab, 0xfb, 0xf0, 0x66, 0xf3, 0x7d, 0xa9, 0xfb, 0x48, ++ 0x36, 0x06, 0x95, 0x7d, 0x90, 0x9e, 0xb4, 0xc5, 0xa6, 0x0b, 0xa3, 0xbe, ++ 0xb7, 0x05, 0xf6, 0x85, 0xe3, 0x05, 0xf2, 0x64, 0x82, 0x4f, 0xfc, 0xbe, ++ 0xe0, 0xe7, 0xc3, 0x71, 0x67, 0x4c, 0x51, 0xd6, 0x2d, 0xdd, 0xb0, 0x17, ++ 0xd7, 0x31, 0x53, 0xe7, 0xed, 0xc0, 0xf7, 0x0e, 0x7f, 0x56, 0x67, 0x07, ++ 0xf4, 0x62, 0xb3, 0x58, 0xb3, 0x88, 0xcf, 0xf3, 0xc1, 0xa2, 0xfd, 0xd0, ++ 0x4c, 0xa2, 0xb3, 0xe3, 0xf2, 0x15, 0xf4, 0x0e, 0x14, 0xe4, 0x1f, 0xc6, ++ 0xc8, 0xad, 0x9b, 0x7e, 0x2b, 0xd0, 0x7e, 0xd8, 0xfd, 0x46, 0x3a, 0x97, ++ 0xcd, 0x05, 0x7c, 0xdf, 0x4f, 0x1b, 0x43, 0x4e, 0x46, 0x06, 0x6e, 0x68, ++ 0xd4, 0x82, 0xe4, 0xe1, 0xf1, 0xf7, 0x85, 0x21, 0xf8, 0xeb, 0x65, 0x48, ++ 0x4f, 0xed, 0x69, 0x5e, 0x8e, 0xbf, 0xd2, 0x40, 0xca, 0x1a, 0xc4, 0xdf, ++ 0xd4, 0x81, 0xcc, 0xb5, 0xb4, 0xaf, 0x70, 0xc2, 0xf3, 0x88, 0xc7, 0xe3, ++ 0xf8, 0xf3, 0xd9, 0x07, 0xff, 0x29, 0x72, 0x40, 0x8f, 0xf0, 0xbd, 0xda, ++ 0x79, 0xaa, 0xe7, 0xa8, 0xe2, 0x41, 0xbc, 0xfc, 0x32, 0xe6, 0x4b, 0xea, ++ 0xf9, 0x3a, 0x68, 0x9f, 0xde, 0x22, 0x4e, 0x07, 0xaa, 0x1e, 0xc5, 0xc0, ++ 0xce, 0x49, 0x1e, 0x0a, 0xbf, 0xf5, 0x30, 0x9e, 0x5c, 0x18, 0xad, 0x1b, ++ 0x1d, 0x3e, 0xd2, 0x8f, 0x0d, 0x76, 0x4f, 0x11, 0xfa, 0x6f, 0xdb, 0xff, ++ 0xaa, 0x6f, 0x48, 0xe4, 0xbf, 0xfd, 0x50, 0x81, 0xd3, 0x9a, 0x14, 0x2b, ++ 0xe9, 0xcd, 0xed, 0x29, 0x5c, 0x6f, 0xee, 0x4d, 0x99, 0xa3, 0xb1, 0x77, ++ 0xaa, 0xc1, 0xfe, 0x11, 0x00, 0x3f, 0xf4, 0xe9, 0xac, 0x0b, 0xe9, 0x48, ++ 0x3f, 0xe2, 0x76, 0xf2, 0x7f, 0xe9, 0x47, 0xa2, 0x86, 0x84, 0xeb, 0x8a, ++ 0xd3, 0x47, 0x47, 0xcc, 0xe5, 0xfa, 0xa8, 0x04, 0xfa, 0x68, 0x82, 0x79, ++ 0xd5, 0x52, 0x44, 0x7d, 0x34, 0x81, 0x9e, 0x3a, 0xa8, 0x8f, 0xa6, 0xcd, ++ 0xe1, 0xfa, 0x68, 0x8a, 0x91, 0xf4, 0xd1, 0x6d, 0xc9, 0xc6, 0xda, 0xed, ++ 0x09, 0xf8, 0xcd, 0x81, 0x3c, 0xae, 0x5f, 0xf7, 0xe2, 0x3e, 0x12, 0xd8, ++ 0x7b, 0x60, 0xe7, 0x91, 0x1f, 0x52, 0xb5, 0xf3, 0x8c, 0x92, 0x9f, 0xec, ++ 0x35, 0x75, 0x9f, 0x07, 0x14, 0x7c, 0x57, 0xfb, 0x9b, 0xa4, 0x66, 0x86, ++ 0x7e, 0x31, 0xbd, 0xd1, 0x23, 0xa3, 0xbe, 0xa9, 0xb7, 0x72, 0xfd, 0xd1, ++ 0x04, 0xdb, 0x2c, 0x8a, 0x91, 0xdf, 0xea, 0xfc, 0xfb, 0xf3, 0x0c, 0xf4, ++ 0xfe, 0xb7, 0x0b, 0xb9, 0x1e, 0xaf, 0x33, 0x73, 0xfd, 0xe4, 0xa6, 0xe3, ++ 0x42, 0x73, 0x22, 0xb8, 0xff, 0x59, 0x81, 0xfb, 0x70, 0x78, 0xf7, 0x37, ++ 0xe0, 0x0d, 0xf1, 0x85, 0x72, 0x9b, 0xd1, 0x8b, 0xfa, 0x41, 0xb9, 0xcd, ++ 0x51, 0x85, 0xfa, 0xc1, 0x70, 0xef, 0x81, 0xa9, 0x19, 0xfc, 0x28, 0x2d, ++ 0xca, 0x57, 0x3c, 0x7f, 0x9d, 0xac, 0x27, 0xf9, 0x23, 0x7a, 0x1c, 0x88, ++ 0x67, 0x5d, 0x86, 0xfe, 0x57, 0x8e, 0xa3, 0x1d, 0x77, 0xd8, 0x46, 0xf2, ++ 0x46, 0xd5, 0x9b, 0xc1, 0x4e, 0xf5, 0x7a, 0xe0, 0xe5, 0x3d, 0xff, 0x01, ++ 0x14, 0xa8, 0x1b, 0x6a, 0x9f, 0x82, 0xdd, 0x24, 0xe5, 0xc3, 0x78, 0x7d, ++ 0xab, 0x32, 0x27, 0xf2, 0xf1, 0x40, 0xbf, 0x2b, 0x1d, 0xaa, 0x4f, 0xc6, ++ 0xfb, 0x01, 0x06, 0xe9, 0x3c, 0x65, 0x97, 0x93, 0xbf, 0x17, 0x1a, 0x85, ++ 0xef, 0x09, 0xab, 0xa6, 0x8c, 0x44, 0x7c, 0x8a, 0xa7, 0x73, 0xb5, 0xcc, ++ 0x75, 0xbc, 0x9e, 0xbb, 0x02, 0xd6, 0x95, 0x3b, 0xea, 0x28, 0x95, 0xea, ++ 0xf3, 0xff, 0xc9, 0xf4, 0xe4, 0x57, 0x8b, 0xef, 0x3f, 0x36, 0x5f, 0x85, ++ 0x3f, 0x97, 0xc7, 0xe3, 0x60, 0xb2, 0x11, 0x7a, 0x92, 0xc3, 0x63, 0x71, ++ 0xdd, 0x67, 0x5a, 0xde, 0xcc, 0xf4, 0xc0, 0x52, 0x9a, 0xc4, 0xf3, 0x24, ++ 0x8f, 0x3f, 0x69, 0x9e, 0x32, 0xe2, 0x11, 0x99, 0xf3, 0xd9, 0xdd, 0x28, ++ 0x5f, 0xbe, 0x22, 0x12, 0x9f, 0xcd, 0xb9, 0xb7, 0x37, 0x35, 0x2d, 0xe6, ++ 0x7c, 0x9f, 0x6e, 0xeb, 0xce, 0x15, 0x5d, 0x18, 0x2f, 0x88, 0xe4, 0x56, ++ 0xbb, 0xc8, 0x0e, 0xf0, 0x26, 0x5a, 0xef, 0x42, 0x75, 0xfe, 0xf0, 0x18, ++ 0xe2, 0xcb, 0x06, 0xe5, 0xfc, 0x65, 0x7b, 0x64, 0xf6, 0x58, 0x80, 0xb7, ++ 0x6c, 0xd3, 0x79, 0xd0, 0x15, 0x0d, 0x42, 0x57, 0x43, 0xff, 0x95, 0x62, ++ 0x6a, 0xb5, 0x04, 0xf3, 0xe7, 0xb6, 0x31, 0x8f, 0x0d, 0xea, 0x4e, 0x26, ++ 0x91, 0x1f, 0x2b, 0xf7, 0xb2, 0x9e, 0xf0, 0x2c, 0xf7, 0xe0, 0x12, 0xc2, ++ 0xdf, 0x31, 0xf6, 0x01, 0x21, 0xe8, 0x8e, 0x99, 0x07, 0x59, 0x70, 0x4c, ++ 0x3c, 0xe4, 0xd3, 0xe6, 0x6a, 0xa2, 0xcb, 0xdc, 0x91, 0x83, 0xf6, 0x1b, ++ 0xc5, 0x0d, 0x3e, 0xb5, 0x87, 0xe7, 0x23, 0x5d, 0x7f, 0xfa, 0x04, 0x5f, ++ 0x51, 0xee, 0x77, 0xb4, 0xed, 0x20, 0x5b, 0xc9, 0xcf, 0x7c, 0x4f, 0x8b, ++ 0x35, 0x84, 0x26, 0xe0, 0x98, 0x87, 0x25, 0x1d, 0xd6, 0x73, 0x9f, 0x15, ++ 0x58, 0x8e, 0x13, 0xd7, 0x71, 0xd0, 0xf9, 0x08, 0xfa, 0x69, 0x7e, 0x98, ++ 0x44, 0x7e, 0x1a, 0xfd, 0x56, 0x17, 0xf9, 0x59, 0x9e, 0x15, 0xfc, 0xd3, ++ 0xf2, 0x81, 0x2e, 0xce, 0x84, 0xe4, 0xaf, 0xa2, 0x7d, 0x4b, 0x3f, 0xe8, ++ 0xd7, 0xf8, 0x35, 0xeb, 0x8e, 0x8d, 0x24, 0xbf, 0x22, 0xb3, 0x49, 0x7e, ++ 0x3d, 0xa0, 0x63, 0x3b, 0x13, 0xf8, 0x91, 0x6e, 0xcf, 0xe7, 0xf6, 0xdc, ++ 0xd2, 0x7c, 0x4e, 0x5f, 0xb9, 0x8e, 0x37, 0x72, 0x57, 0x54, 0x60, 0x79, ++ 0x8c, 0xce, 0xfb, 0x5a, 0xe9, 0xa8, 0x13, 0xf9, 0x35, 0x8c, 0xf3, 0xc8, ++ 0x88, 0xcd, 0x14, 0xe7, 0x0a, 0x56, 0xb1, 0x22, 0xb4, 0xfb, 0x3a, 0x0d, ++ 0x80, 0x57, 0x09, 0xe8, 0xf4, 0x5f, 0xf3, 0x95, 0x78, 0x99, 0xca, 0x87, ++ 0x15, 0xf8, 0x59, 0xd0, 0x4a, 0x81, 0x7d, 0xe8, 0x05, 0x45, 0xbf, 0xdb, ++ 0xfd, 0xfc, 0xf3, 0xcf, 0x67, 0xa2, 0xbc, 0x66, 0xa8, 0xdc, 0x0d, 0xd2, ++ 0x9b, 0x3a, 0x4e, 0x52, 0x51, 0x17, 0x35, 0x26, 0x79, 0xbc, 0x0c, 0xfd, ++ 0x0d, 0x82, 0xe4, 0xe5, 0xfc, 0x55, 0x0a, 0x3a, 0x82, 0x18, 0xd7, 0xf9, ++ 0x8b, 0x3e, 0x21, 0x5e, 0x3f, 0xa9, 0x9c, 0xdf, 0x1a, 0xe7, 0x7a, 0x07, ++ 0xf6, 0xaf, 0x76, 0x79, 0x1c, 0x48, 0x07, 0xbd, 0xce, 0xc9, 0x8e, 0x3b, ++ 0x01, 0x7e, 0x36, 0x9b, 0x91, 0x99, 0x62, 0xf8, 0xaf, 0x8a, 0x27, 0x87, ++ 0x92, 0x27, 0x93, 0xfe, 0xa1, 0x8e, 0xb3, 0x2a, 0x39, 0xef, 0x8a, 0x76, ++ 0xb6, 0x11, 0xf8, 0xb0, 0x7c, 0x05, 0xf9, 0x6c, 0x44, 0x7f, 0x37, 0xea, ++ 0x31, 0x7d, 0x53, 0xcd, 0x32, 0xac, 0x77, 0xbd, 0xad, 0x3c, 0x82, 0x7a, ++ 0xd6, 0x7a, 0x9b, 0xbd, 0x9c, 0xfc, 0xe6, 0x36, 0xe0, 0x17, 0x31, 0x7e, ++ 0x24, 0x9b, 0xed, 0x08, 0xe1, 0xa1, 0xcd, 0xc3, 0xfd, 0x6b, 0x36, 0xe4, ++ 0xbb, 0xe8, 0x47, 0x52, 0xf6, 0xdf, 0xeb, 0x3c, 0x42, 0xfb, 0x57, 0xfb, ++ 0xad, 0x52, 0xf8, 0x8f, 0xcd, 0x13, 0xe6, 0x71, 0x47, 0xb0, 0x62, 0xb0, ++ 0x9f, 0x45, 0xf4, 0x05, 0xd1, 0xbe, 0xb0, 0xd8, 0x19, 0xd9, 0x93, 0x16, ++ 0x33, 0xa7, 0xa7, 0x24, 0x38, 0x0e, 0x73, 0x0c, 0x1f, 0x51, 0xe7, 0xbd, ++ 0x3f, 0x9f, 0xdb, 0x69, 0xeb, 0x73, 0xca, 0x23, 0x95, 0xb4, 0x3e, 0x11, ++ 0x3d, 0x01, 0x6c, 0xbd, 0xa3, 0xdc, 0x41, 0x72, 0x10, 0xe1, 0x8c, 0x7a, ++ 0xe8, 0xa8, 0x41, 0x3d, 0x94, 0xfc, 0x25, 0xcf, 0x29, 0x70, 0x56, 0xc7, ++ 0x69, 0xef, 0xe5, 0xfb, 0xf4, 0xb5, 0x3a, 0xbc, 0xd5, 0xe9, 0x68, 0x7f, ++ 0xfa, 0x9e, 0x45, 0xbe, 0xb0, 0xde, 0x76, 0xa7, 0x39, 0x88, 0xf2, 0x20, ++ 0x79, 0xe2, 0x15, 0xc7, 0x7b, 0x25, 0x5f, 0xd0, 0xf8, 0x7b, 0xa2, 0xe3, ++ 0xb5, 0xce, 0x50, 0xc6, 0x7b, 0x0e, 0xc7, 0xd3, 0x27, 0x97, 0x4b, 0x38, ++ 0x9e, 0x01, 0xf9, 0x44, 0x02, 0xfc, 0x0b, 0x2b, 0xeb, 0xfa, 0xa2, 0xfe, ++ 0x30, 0x80, 0xa8, 0x44, 0xf6, 0x1a, 0xe3, 0x7a, 0x15, 0x60, 0xbc, 0x23, ++ 0x91, 0xfe, 0xa0, 0x96, 0x66, 0xc5, 0xaf, 0x35, 0xf4, 0x3d, 0xce, 0x27, ++ 0x9d, 0x8a, 0xdd, 0x02, 0x7c, 0xf2, 0x18, 0xae, 0xbf, 0x31, 0xe7, 0xf4, ++ 0x91, 0x4a, 0xea, 0xc5, 0xed, 0x95, 0xb4, 0xd9, 0x62, 0x91, 0x08, 0xe7, ++ 0xf5, 0x09, 0x9c, 0xa0, 0x5e, 0x88, 0xda, 0xef, 0xf1, 0x7a, 0x4c, 0xa5, ++ 0x7e, 0x80, 0xe4, 0x99, 0x2a, 0x87, 0x54, 0xb9, 0xf4, 0x34, 0xea, 0x31, ++ 0xc6, 0x28, 0x3d, 0xa9, 0x7e, 0x97, 0xec, 0x06, 0x1f, 0xc9, 0x6b, 0xc1, ++ 0xee, 0x23, 0xbc, 0x01, 0xbd, 0x46, 0x46, 0xba, 0xd1, 0x63, 0xbc, 0x37, ++ 0x01, 0xdc, 0x24, 0x17, 0x87, 0x9b, 0x90, 0x32, 0x45, 0x46, 0x7a, 0xa9, ++ 0xbe, 0xd4, 0x9f, 0x4d, 0x72, 0x3e, 0xf9, 0xa3, 0x6c, 0x16, 0xe3, 0x3f, ++ 0x53, 0xf9, 0xe1, 0xa1, 0xcf, 0x76, 0x59, 0xb0, 0xfd, 0xd3, 0x86, 0xaa, ++ 0x2b, 0xea, 0x2b, 0x6a, 0x3c, 0x78, 0xb8, 0x38, 0x70, 0xca, 0x43, 0xbf, ++ 0xff, 0x4a, 0xac, 0xbe, 0x32, 0x5c, 0x5c, 0xf8, 0x6a, 0xf1, 0xe0, 0xbe, ++ 0x14, 0x23, 0xf9, 0xdd, 0x9e, 0x11, 0xb4, 0x7c, 0xc9, 0xea, 0xe2, 0xfc, ++ 0xc8, 0xe0, 0x52, 0xfd, 0x27, 0xfe, 0xbf, 0xe0, 0x39, 0x3c, 0x23, 0xf8, ++ 0x3c, 0xa4, 0x2f, 0x2a, 0x7e, 0x94, 0x7d, 0x85, 0x7e, 0xe6, 0x42, 0xbf, ++ 0x57, 0xa7, 0x91, 0x05, 0xe1, 0x3c, 0x0f, 0x7c, 0x36, 0xd9, 0x81, 0xf8, ++ 0x71, 0xad, 0xf0, 0x55, 0xfd, 0xe6, 0x59, 0x8a, 0x1e, 0x95, 0x65, 0xdb, ++ 0x25, 0x20, 0x9d, 0x66, 0x35, 0x84, 0x04, 0xf4, 0x7b, 0x67, 0x37, 0x74, ++ 0x09, 0xde, 0x2b, 0xf4, 0x7b, 0x07, 0xe9, 0x39, 0x23, 0xda, 0xdf, 0xa0, ++ 0x8c, 0x3f, 0x5d, 0x1c, 0xd0, 0xa3, 0xbc, 0x9a, 0xae, 0xd0, 0x71, 0xf6, ++ 0x45, 0x91, 0x15, 0xc5, 0xe8, 0x7f, 0x6f, 0xe5, 0x73, 0x3d, 0xca, 0xa0, ++ 0xe8, 0xed, 0x29, 0x7d, 0xcf, 0x59, 0x70, 0xbc, 0x3e, 0x9d, 0xaf, 0xb3, ++ 0x10, 0xe5, 0x43, 0x8a, 0x4e, 0xde, 0x19, 0x43, 0xef, 0x86, 0x7b, 0xcb, ++ 0xcd, 0x55, 0x31, 0xf0, 0x69, 0xc7, 0x78, 0x4e, 0x82, 0xf3, 0x2b, 0x77, ++ 0x0d, 0xea, 0x5b, 0x64, 0x17, 0xa9, 0xf2, 0xd6, 0xa0, 0xca, 0x09, 0xbb, ++ 0xa8, 0x91, 0x13, 0x81, 0x24, 0x8e, 0xb7, 0xaa, 0xbe, 0x13, 0xb8, 0x9e, ++ 0xdb, 0x41, 0x82, 0xe0, 0x2f, 0x41, 0xb8, 0x9e, 0xbb, 0xfe, 0xf7, 0xb7, ++ 0xe0, 0x16, 0xcf, 0x09, 0x61, 0x83, 0xdd, 0x79, 0xf5, 0x78, 0xc6, 0xa0, ++ 0x5e, 0xa3, 0x0b, 0x2d, 0x57, 0xed, 0x17, 0xa4, 0x97, 0x2e, 0x83, 0xdc, ++ 0xdd, 0x4f, 0xfa, 0x55, 0x8a, 0x07, 0xfd, 0x00, 0xaa, 0x5e, 0x55, 0xf6, ++ 0x3d, 0x21, 0x1f, 0xfb, 0x79, 0x04, 0x2f, 0xd1, 0xc9, 0x24, 0xe6, 0xa7, ++ 0xf2, 0x3a, 0xc6, 0xf5, 0x40, 0xd0, 0xaf, 0x6e, 0x70, 0x91, 0xbe, 0x07, ++ 0x5b, 0x89, 0x39, 0x77, 0x86, 0xae, 0x88, 0xcc, 0xab, 0xef, 0xaf, 0x00, ++ 0xfd, 0xe0, 0x18, 0x27, 0x10, 0x23, 0xe4, 0x4f, 0xfd, 0xfa, 0x25, 0x81, ++ 0xf8, 0x7b, 0x3c, 0xdc, 0xda, 0x06, 0xe1, 0x36, 0x18, 0xcf, 0xd3, 0xf8, ++ 0x45, 0xb3, 0x15, 0x79, 0x97, 0xad, 0xb4, 0xcb, 0xe8, 0x17, 0x75, 0x62, ++ 0x7c, 0x4a, 0xeb, 0xb7, 0xac, 0x38, 0xaa, 0xad, 0x4f, 0x8a, 0x68, 0xeb, ++ 0xd7, 0x9d, 0x8c, 0xf3, 0x83, 0x06, 0xbd, 0x6f, 0xbb, 0x32, 0x79, 0xfc, ++ 0x1f, 0x07, 0xdd, 0x06, 0xf4, 0x86, 0x7c, 0x62, 0x85, 0x12, 0xb7, 0xcc, ++ 0x09, 0x86, 0x2a, 0x25, 0x58, 0x6f, 0x2e, 0xeb, 0xa2, 0xf8, 0x60, 0x76, ++ 0x43, 0x9a, 0x06, 0xde, 0x37, 0xe9, 0x95, 0xbc, 0x09, 0xe6, 0x15, 0x98, ++ 0xba, 0x4e, 0xf8, 0x65, 0x8b, 0xf3, 0x3e, 0xc6, 0xf7, 0x5b, 0x5c, 0x83, ++ 0xfe, 0x3b, 0xd2, 0xbf, 0xee, 0x51, 0xda, 0xff, 0xa1, 0x7a, 0xc5, 0x57, ++ 0x3b, 0xd0, 0x96, 0xde, 0x6c, 0x20, 0xff, 0xa8, 0x19, 0x26, 0x47, 0x78, ++ 0xfd, 0xc3, 0xec, 0x05, 0x33, 0xf1, 0xbc, 0x87, 0xf8, 0x57, 0x9b, 0xb5, ++ 0x7e, 0xd5, 0xec, 0xd8, 0x76, 0x80, 0xc3, 0x3d, 0xdb, 0x0c, 0x9a, 0x76, ++ 0x9f, 0xb7, 0x8c, 0xec, 0x82, 0x85, 0x8a, 0xdf, 0x76, 0x70, 0xbf, 0xb8, ++ 0x8e, 0x0c, 0xbe, 0xdf, 0xec, 0xf2, 0xa1, 0xf3, 0x5f, 0x7d, 0x5e, 0xf8, ++ 0x2f, 0x6d, 0xe8, 0xfc, 0xea, 0xb8, 0x4f, 0x03, 0x1f, 0x42, 0xfe, 0xca, ++ 0x2e, 0xc1, 0xb9, 0x4e, 0x46, 0xb8, 0x31, 0xf4, 0x40, 0xb0, 0x5c, 0x31, ++ 0x2c, 0x60, 0x9c, 0x3a, 0xab, 0x99, 0x79, 0x51, 0x4f, 0xce, 0x6e, 0x61, ++ 0xde, 0x44, 0xfe, 0xfe, 0x5d, 0x0a, 0xbc, 0xe2, 0xe1, 0xcc, 0x82, 0xd3, ++ 0x09, 0x7e, 0x33, 0x94, 0x67, 0x59, 0x36, 0x3d, 0xd9, 0xed, 0x59, 0x2d, ++ 0x3a, 0xd2, 0x0f, 0xb3, 0x80, 0x4f, 0x20, 0x7f, 0xb8, 0x65, 0x25, 0x90, ++ 0x11, 0xd4, 0xb3, 0x57, 0xca, 0xa4, 0x5f, 0xde, 0xda, 0xa0, 0x63, 0x28, ++ 0x1f, 0xd8, 0xa5, 0x36, 0xcd, 0xfb, 0xb0, 0x5c, 0xf2, 0x7f, 0xaa, 0xe7, ++ 0xfe, 0x34, 0x8e, 0x87, 0xfa, 0x65, 0x23, 0x0b, 0xe9, 0x70, 0x3f, 0xcd, ++ 0xc5, 0x44, 0x67, 0xb4, 0xae, 0xbc, 0x28, 0x3e, 0x00, 0xbc, 0x4e, 0x73, ++ 0x78, 0x99, 0x09, 0x5e, 0xb7, 0x4e, 0x31, 0x68, 0xfc, 0x9c, 0xb9, 0xe8, ++ 0xd7, 0x8c, 0x81, 0x8b, 0x8a, 0x07, 0xd9, 0x71, 0xcf, 0xbf, 0xe4, 0x92, ++ 0x34, 0x74, 0x01, 0x72, 0x6e, 0x97, 0x8b, 0xf0, 0x84, 0xcb, 0xbf, 0x02, ++ 0x94, 0x7f, 0xb0, 0xa4, 0x33, 0x53, 0x4f, 0xee, 0xea, 0x82, 0xf5, 0xdd, ++ 0xb4, 0x96, 0xd1, 0x7e, 0x07, 0x52, 0xad, 0x21, 0x9e, 0x0f, 0x31, 0x18, ++ 0x3f, 0xd0, 0x5f, 0x1e, 0x0b, 0x7c, 0xcb, 0x3c, 0xa3, 0x08, 0xfd, 0x2c, ++ 0x9b, 0x24, 0xab, 0x0e, 0xf3, 0x16, 0x0e, 0xa4, 0xf6, 0x7f, 0x9b, 0xa5, ++ 0x32, 0xd6, 0x0d, 0x6a, 0x71, 0x75, 0x0e, 0x63, 0x3f, 0xb1, 0x0e, 0x94, ++ 0x08, 0x50, 0x3f, 0xe4, 0x6a, 0xd8, 0xd2, 0x79, 0x23, 0xb4, 0x5b, 0x06, ++ 0x5e, 0x40, 0xe7, 0xaf, 0xcd, 0x16, 0x58, 0x50, 0x13, 0x53, 0x4f, 0x49, ++ 0x69, 0x5f, 0x50, 0x83, 0x87, 0x36, 0x85, 0xc9, 0x22, 0xc0, 0xc7, 0x8a, ++ 0x33, 0xc0, 0x3e, 0xad, 0xd2, 0x9c, 0xdd, 0x7a, 0x98, 0xdf, 0xea, 0xb6, ++ 0x91, 0x53, 0xd2, 0xca, 0x06, 0xe9, 0x94, 0xf6, 0xd3, 0x71, 0xbd, 0xfc, ++ 0x28, 0xe6, 0x7d, 0x74, 0x14, 0xe8, 0x48, 0x7f, 0x62, 0xb1, 0xed, 0xb0, ++ 0x8f, 0xb2, 0x02, 0x49, 0xa1, 0x03, 0x6f, 0x11, 0xf1, 0x8f, 0x1a, 0x1e, ++ 0xc7, 0x8f, 0x1d, 0x5f, 0xb4, 0x5f, 0x61, 0xfc, 0x39, 0x30, 0xfe, 0xc4, ++ 0xcf, 0x31, 0xbe, 0x99, 0xaf, 0x3f, 0x13, 0x1f, 0x81, 0xdc, 0xc9, 0xc4, ++ 0xf5, 0xa3, 0xdf, 0x1a, 0xc7, 0xc7, 0xf3, 0x45, 0xe7, 0x51, 0xec, 0xfc, ++ 0xca, 0x78, 0x22, 0x0b, 0x6e, 0xc7, 0x78, 0x0b, 0xcc, 0x67, 0x13, 0xf8, ++ 0x7c, 0x12, 0xe6, 0x95, 0x64, 0x32, 0x6d, 0x1e, 0xc1, 0xe0, 0x7c, 0x12, ++ 0xcc, 0x57, 0xfa, 0x77, 0xd8, 0x4f, 0xed, 0xd0, 0xf3, 0x30, 0x5c, 0xe9, ++ 0x3c, 0x6e, 0xff, 0x7c, 0xe7, 0xd1, 0xa1, 0xf3, 0xd2, 0x7a, 0x83, 0xe3, ++ 0x6d, 0x64, 0x17, 0x31, 0x68, 0xd6, 0x4d, 0x46, 0xfb, 0x83, 0xcf, 0x67, ++ 0x11, 0xd9, 0x21, 0xb1, 0x9c, 0xc3, 0xb5, 0x63, 0x72, 0x14, 0xae, 0xa0, ++ 0x07, 0xd2, 0xb8, 0xd0, 0x7d, 0xcd, 0x65, 0x05, 0xce, 0x06, 0x84, 0xb3, ++ 0x64, 0x24, 0x38, 0x0f, 0x07, 0xb7, 0x3e, 0x89, 0xe7, 0x35, 0x6d, 0x90, ++ 0xac, 0xa1, 0x35, 0xce, 0xff, 0x03, 0xe7, 0xe5, 0xe0, 0xe7, 0x15, 0x3b, ++ 0x1f, 0xea, 0x93, 0xd7, 0x3c, 0xdf, 0xed, 0x30, 0x9f, 0xfd, 0xda, 0xe7, ++ 0x43, 0xf8, 0x22, 0xfd, 0x0c, 0xc2, 0x17, 0xce, 0x64, 0x6d, 0xe6, 0xb5, ++ 0xc3, 0x17, 0x56, 0x15, 0xbc, 0x16, 0xf8, 0xf6, 0xc1, 0xb8, 0xba, 0x18, ++ 0xb8, 0x46, 0xf3, 0x87, 0x9e, 0x92, 0xd0, 0x2e, 0xb0, 0x18, 0x7c, 0x66, ++ 0x0f, 0xf0, 0xdf, 0x9b, 0x0a, 0x52, 0x49, 0xde, 0xba, 0xed, 0x0b, 0xcc, ++ 0x94, 0x4f, 0x90, 0xb1, 0xc0, 0x8c, 0x79, 0x7a, 0xeb, 0xdc, 0xb6, 0x1a, ++ 0xcc, 0xe7, 0x5b, 0xe7, 0x5a, 0x64, 0x36, 0xc4, 0xc8, 0xe9, 0x75, 0xee, ++ 0x3a, 0x6a, 0x87, 0xfe, 0x94, 0xf7, 0xe4, 0x0e, 0x5b, 0xd1, 0x6d, 0xc1, ++ 0x4a, 0x59, 0x84, 0xfc, 0x02, 0x1b, 0x6e, 0xa8, 0x76, 0x2c, 0x47, 0xfc, ++ 0x69, 0xe6, 0x79, 0x54, 0x6a, 0x5e, 0x91, 0x2a, 0x0f, 0x99, 0x12, 0xaf, ++ 0xa4, 0x7d, 0xc1, 0x8b, 0x23, 0x6e, 0xdc, 0x3b, 0xd0, 0x07, 0xfd, 0x37, ++ 0x34, 0x4f, 0xa4, 0xbc, 0xb1, 0x11, 0xa9, 0xff, 0x4e, 0xf9, 0x52, 0x9b, ++ 0x1a, 0x3c, 0x1e, 0x6c, 0xff, 0xb6, 0x85, 0xc7, 0x1d, 0x9f, 0x54, 0xe2, ++ 0x4e, 0x88, 0xa8, 0xe4, 0x57, 0x1b, 0x7f, 0xfd, 0x77, 0x30, 0xfe, 0x5a, ++ 0x5e, 0xb0, 0x4a, 0xa0, 0x78, 0xe3, 0xca, 0x2b, 0xc7, 0x1b, 0xcb, 0xcf, ++ 0x47, 0xaa, 0x30, 0xef, 0x8a, 0x2d, 0xe7, 0x79, 0x55, 0x8e, 0x3a, 0x31, ++ 0x4e, 0x1e, 0x6a, 0xe9, 0x76, 0x13, 0xc2, 0x95, 0xe7, 0x3f, 0x85, 0x04, ++ 0x0e, 0x5f, 0xcd, 0x78, 0x2d, 0x05, 0x19, 0x3c, 0x1e, 0xed, 0xda, 0xc1, ++ 0xd0, 0xee, 0x7b, 0x05, 0xc6, 0xd2, 0x6b, 0xe9, 0x4b, 0x87, 0x79, 0x48, ++ 0xf1, 0xf4, 0x28, 0x1a, 0xbd, 0x52, 0x25, 0xea, 0xeb, 0xab, 0x74, 0xb4, ++ 0x8e, 0x6c, 0x0c, 0xed, 0x83, 0x88, 0x2b, 0x2f, 0x9d, 0xeb, 0x58, 0x0e, ++ 0xcf, 0x73, 0xee, 0x16, 0x3d, 0x02, 0x3c, 0x1f, 0xe9, 0x7e, 0x98, 0xf2, ++ 0x91, 0x40, 0xdb, 0x27, 0x7d, 0xc3, 0xed, 0x3e, 0x56, 0x85, 0xf5, 0x21, ++ 0xfb, 0x5c, 0xa1, 0xdd, 0x47, 0xfc, 0xbe, 0xe2, 0xd7, 0x0d, 0x82, 0x8b, ++ 0xd6, 0xad, 0x9e, 0x57, 0xf9, 0x79, 0x4f, 0x12, 0xda, 0x57, 0xe5, 0x05, ++ 0x0b, 0x28, 0x5f, 0x8c, 0x7e, 0x2a, 0xbd, 0xeb, 0xe3, 0xf6, 0x93, 0x8e, ++ 0x76, 0xb1, 0xce, 0x6b, 0x19, 0x8f, 0x76, 0x41, 0xcc, 0xbe, 0x98, 0xa6, ++ 0x9f, 0x62, 0xbf, 0xfd, 0xd7, 0xd6, 0xef, 0x44, 0x64, 0x42, 0xbd, 0x30, ++ 0x3e, 0x1e, 0xf6, 0x4f, 0x3e, 0x5a, 0xa7, 0x89, 0x79, 0xcc, 0x46, 0x7a, ++ 0xaf, 0x8e, 0xec, 0x48, 0x35, 0xce, 0x96, 0x85, 0xb4, 0x83, 0xe7, 0x3e, ++ 0x9a, 0xf1, 0x38, 0x45, 0xfc, 0xfb, 0x93, 0xf9, 0xfb, 0xcc, 0xc1, 0xe3, ++ 0x6e, 0x26, 0x2b, 0x98, 0xa4, 0x40, 0x7f, 0xc2, 0x7d, 0x56, 0xf2, 0x67, ++ 0x9a, 0x4c, 0x50, 0x87, 0xf3, 0x11, 0x8c, 0xcc, 0x3c, 0x0a, 0x9e, 0x3f, ++ 0xad, 0xf8, 0x03, 0xd7, 0x08, 0x4c, 0xc4, 0x7a, 0x74, 0xbe, 0x30, 0xc3, ++ 0xf9, 0xda, 0x05, 0xdf, 0x66, 0x8f, 0x13, 0x4b, 0x6e, 0x47, 0x19, 0x52, ++ 0x7d, 0x94, 0x6f, 0x88, 0x61, 0xdb, 0x58, 0x7b, 0xb4, 0x0f, 0xf3, 0x38, ++ 0xa0, 0x7d, 0xd5, 0xbd, 0xce, 0x91, 0xe8, 0xcf, 0x1b, 0x01, 0x04, 0x11, ++ 0x41, 0x7b, 0x5a, 0x89, 0x53, 0xa9, 0xfe, 0x93, 0x94, 0xfc, 0xfe, 0xa5, ++ 0x28, 0xbf, 0x5f, 0x2c, 0xf8, 0x68, 0x81, 0x19, 0xe5, 0x33, 0x3a, 0x9c, ++ 0xae, 0x67, 0x6c, 0xff, 0xce, 0xd3, 0x5b, 0x82, 0x39, 0x51, 0xba, 0x34, ++ 0x5d, 0xcc, 0x62, 0x72, 0x8c, 0x5d, 0x63, 0x12, 0x9b, 0x29, 0x9f, 0xc3, ++ 0x74, 0x71, 0xb4, 0xc6, 0xcf, 0x12, 0x56, 0xec, 0x31, 0xb5, 0xee, 0xb5, ++ 0x8b, 0xd5, 0x38, 0x5f, 0x04, 0xed, 0x05, 0xcc, 0x5f, 0x62, 0x52, 0x07, ++ 0xbe, 0x57, 0x09, 0x40, 0x91, 0x63, 0xfd, 0xa6, 0x17, 0x1d, 0x9a, 0x71, ++ 0xa2, 0xe3, 0xe7, 0x68, 0xe6, 0x0d, 0x83, 0x5d, 0x1d, 0x1b, 0x17, 0x18, ++ 0x7e, 0xfc, 0x24, 0x26, 0x17, 0xc5, 0x8e, 0x9f, 0x37, 0xcc, 0xf8, 0x85, ++ 0x71, 0xe3, 0x4b, 0x09, 0xc7, 0x8f, 0x8e, 0x9b, 0xae, 0x19, 0x77, 0x9d, ++ 0xc8, 0xf9, 0x45, 0xd0, 0x6e, 0x0d, 0x25, 0xf2, 0xf3, 0x9d, 0x2d, 0xa8, ++ 0x7a, 0x1b, 0x49, 0x79, 0xb8, 0x7c, 0xb3, 0x33, 0x05, 0xdc, 0x0f, 0x08, ++ 0xfc, 0x58, 0xa4, 0x38, 0x94, 0x82, 0x37, 0x8f, 0x38, 0x9a, 0x29, 0xff, ++ 0x4c, 0x6f, 0xe5, 0xf1, 0x52, 0x83, 0x12, 0x3f, 0x39, 0x98, 0xdc, 0xc0, ++ 0xf3, 0x24, 0x72, 0xb4, 0xf9, 0x67, 0x55, 0x4c, 0x12, 0xb1, 0x7d, 0x5d, ++ 0xca, 0xac, 0xa3, 0x02, 0xb4, 0x57, 0xd9, 0xb4, 0x7a, 0xfa, 0xf4, 0x4b, ++ 0xa7, 0xf5, 0xc8, 0x77, 0xa6, 0x8b, 0x5a, 0x3d, 0xdd, 0xcb, 0x9a, 0x09, ++ 0x3f, 0x6f, 0x62, 0xda, 0xe7, 0x86, 0x1c, 0x2d, 0x1f, 0xd8, 0xa8, 0xd0, ++ 0x87, 0x2e, 0x79, 0x62, 0x84, 0xf2, 0xd4, 0x32, 0x6c, 0x94, 0x77, 0x30, ++ 0x9c, 0x5f, 0xe1, 0xdd, 0x36, 0x46, 0xf9, 0x53, 0x86, 0x24, 0x5f, 0x33, ++ 0xca, 0x38, 0x63, 0xe1, 0xa5, 0xb4, 0x75, 0x0e, 0xa8, 0x8f, 0xe0, 0xf8, ++ 0x65, 0x2f, 0x4c, 0x5d, 0x88, 0x7e, 0xa2, 0x77, 0x15, 0x3c, 0x5e, 0x07, ++ 0x74, 0x8f, 0x70, 0xac, 0x5b, 0x35, 0x72, 0xbb, 0x3e, 0x66, 0xdc, 0x3a, ++ 0x63, 0xb8, 0x00, 0xe5, 0x48, 0x9d, 0x8e, 0xe7, 0xeb, 0xd3, 0x0f, 0xe6, ++ 0x7f, 0x37, 0x23, 0x8b, 0xfc, 0xac, 0xf1, 0xf3, 0x52, 0xc6, 0x6f, 0x8c, ++ 0xdf, 0xab, 0xbe, 0x59, 0xf0, 0xb9, 0x62, 0xf6, 0xf1, 0xae, 0x42, 0x17, ++ 0x83, 0xf3, 0xad, 0xce, 0xde, 0x8e, 0x7a, 0xec, 0xe0, 0x7c, 0xa6, 0xf0, ++ 0x24, 0x9a, 0x6f, 0x30, 0xef, 0x47, 0x99, 0x2f, 0xf3, 0x8b, 0xcd, 0xf7, ++ 0x9e, 0x42, 0xcf, 0xea, 0x7c, 0xf5, 0x5f, 0xd5, 0xee, 0xaf, 0xde, 0x18, ++ 0xa1, 0xfd, 0xd5, 0xeb, 0x98, 0x92, 0xe7, 0xcf, 0xe7, 0x7b, 0x0f, 0xf7, ++ 0xe7, 0xfc, 0x02, 0xf3, 0x29, 0xf9, 0x5b, 0x83, 0xf3, 0x7d, 0x4d, 0xbb, ++ 0xbf, 0x7a, 0x53, 0x84, 0xf6, 0x57, 0x3f, 0x68, 0x4f, 0x2a, 0xf3, 0x65, ++ 0x7e, 0xb1, 0xf9, 0x4c, 0xc6, 0x66, 0x8a, 0xcf, 0x3c, 0x26, 0xf0, 0x73, ++ 0x9d, 0xbb, 0x6b, 0xd4, 0xe3, 0xe8, 0xa7, 0xbf, 0x30, 0x77, 0x95, 0x8c, ++ 0xf8, 0xa6, 0xda, 0x67, 0xb7, 0xe0, 0x0b, 0x80, 0x67, 0xb7, 0x28, 0xf9, ++ 0x4d, 0xb7, 0xe6, 0x18, 0x49, 0x6f, 0x50, 0xc7, 0xdd, 0xdd, 0x36, 0x85, ++ 0x79, 0x8d, 0xdc, 0x9f, 0x83, 0x65, 0xd1, 0x0d, 0x02, 0xe5, 0xfb, 0x8f, ++ 0x9b, 0x22, 0x78, 0x31, 0x3e, 0xb6, 0x0d, 0xe8, 0xde, 0x5b, 0x88, 0xfe, ++ 0x2a, 0x89, 0xda, 0x43, 0x6d, 0x0e, 0x2a, 0x77, 0xb4, 0xc9, 0x54, 0x7e, ++ 0x17, 0xec, 0x41, 0x2f, 0xf9, 0xad, 0x3c, 0x54, 0xff, 0x1f, 0x85, 0xdc, ++ 0xce, 0x7f, 0x6c, 0x94, 0xb4, 0x64, 0x05, 0xea, 0x0b, 0x95, 0x56, 0x9e, ++ 0xef, 0x7c, 0xc3, 0x34, 0xd0, 0x44, 0xa3, 0xf6, 0x16, 0x18, 0x60, 0x7d, ++ 0x16, 0xcc, 0x2b, 0xfc, 0x32, 0x2b, 0xdb, 0x08, 0xb5, 0xc2, 0xad, 0x1c, ++ 0x1e, 0xf6, 0xea, 0xcc, 0x10, 0x9e, 0x93, 0xb5, 0xec, 0x50, 0xa4, 0x0d, ++ 0xea, 0xa6, 0xa9, 0x7a, 0x19, 0xf3, 0xb8, 0x4d, 0x4e, 0xe6, 0x4b, 0xe4, ++ 0x8f, 0x69, 0x2d, 0xe4, 0x7e, 0x9e, 0x47, 0xd4, 0xfc, 0xf8, 0x1b, 0x05, ++ 0x1e, 0x7f, 0x07, 0x7d, 0xa4, 0x12, 0xf6, 0xbf, 0x4c, 0x01, 0x35, 0xd3, ++ 0xcf, 0x15, 0x50, 0xaf, 0xba, 0xf5, 0x6b, 0xa9, 0xa4, 0x8f, 0xd4, 0x2d, ++ 0xea, 0x4f, 0x96, 0x60, 0x1d, 0x77, 0x08, 0x65, 0x6f, 0xbb, 0x00, 0x1e, ++ 0xbf, 0x51, 0xf4, 0x91, 0x65, 0xa3, 0x39, 0x1d, 0xc7, 0xdb, 0x93, 0x76, ++ 0x94, 0x2c, 0x13, 0x31, 0x7f, 0x4f, 0x1f, 0x0a, 0xc1, 0x9f, 0x0b, 0x93, ++ 0x17, 0x92, 0x3d, 0xba, 0x70, 0x31, 0x63, 0x69, 0xf0, 0xfe, 0xad, 0xf8, ++ 0x1e, 0xc8, 0x95, 0xe3, 0x8a, 0x3e, 0xf3, 0x46, 0xbf, 0x89, 0xa1, 0xbd, ++ 0x16, 0xac, 0xe6, 0x71, 0xe7, 0x3b, 0x1e, 0xd6, 0xda, 0x91, 0x8f, 0x59, ++ 0xc2, 0x12, 0xea, 0x71, 0x8f, 0x95, 0xd9, 0x19, 0x9e, 0x47, 0x5d, 0x8b, ++ 0xb6, 0xfd, 0x11, 0x25, 0x8e, 0xb0, 0x30, 0xce, 0xae, 0xbc, 0x35, 0x2e, ++ 0xaf, 0x06, 0xb4, 0x4c, 0x9e, 0x1f, 0x82, 0x7b, 0x9e, 0xca, 0xd8, 0x03, ++ 0x85, 0xda, 0xbc, 0x9a, 0x8a, 0x42, 0x99, 0xf3, 0xb9, 0x1c, 0x3b, 0x25, ++ 0x55, 0xa7, 0xcd, 0x76, 0x8d, 0xc0, 0x78, 0xa4, 0xc9, 0x98, 0xf8, 0x1e, ++ 0x8e, 0x3a, 0xde, 0x33, 0xaa, 0x5c, 0xb6, 0x7b, 0x09, 0x0e, 0x6a, 0x1e, ++ 0x1a, 0xd3, 0xbf, 0x58, 0x46, 0xef, 0x2b, 0xf3, 0xa9, 0xef, 0x3d, 0x2d, ++ 0xbc, 0x38, 0xea, 0x4a, 0xfe, 0x4e, 0xd0, 0xdb, 0x3e, 0xec, 0x2f, 0xe2, ++ 0xf2, 0x19, 0xf5, 0xeb, 0x8d, 0x71, 0xeb, 0xbc, 0x30, 0x37, 0xef, 0x1b, ++ 0xd5, 0x2c, 0x11, 0xde, 0x0e, 0x88, 0xe8, 0x57, 0x50, 0xd7, 0xff, 0xbf, ++ 0x0b, 0x5f, 0xab, 0xd1, 0xa7, 0x01, 0x78, 0x74, 0x7c, 0xc6, 0xa7, 0x13, ++ 0x29, 0x0e, 0xc3, 0x72, 0x68, 0xdf, 0xb7, 0xa8, 0xf8, 0xa3, 0xe4, 0x57, ++ 0x2d, 0x1c, 0xac, 0x8b, 0x4c, 0x8c, 0xc9, 0xaf, 0x63, 0x8e, 0x01, 0x37, ++ 0x9e, 0xf7, 0x5b, 0x37, 0x26, 0x79, 0x36, 0x12, 0xfe, 0x29, 0xfa, 0x43, ++ 0xf8, 0x1d, 0xdd, 0xe5, 0xa4, 0xcf, 0x3f, 0xde, 0xe0, 0x3a, 0x1c, 0xde, ++ 0x5c, 0xee, 0x8f, 0xab, 0x96, 0x28, 0x3f, 0x48, 0x19, 0x6f, 0x38, 0x38, ++ 0xc7, 0xe7, 0x3f, 0xa8, 0x7e, 0x1b, 0xfa, 0xc5, 0xe4, 0x1f, 0xb6, 0x6f, ++ 0xe7, 0xf9, 0x8f, 0x59, 0xf6, 0xaa, 0x8f, 0xf1, 0x9e, 0x14, 0x3e, 0x3f, ++ 0xad, 0xc1, 0x2b, 0xed, 0x7d, 0xa8, 0xf6, 0xde, 0xe7, 0x04, 0xb4, 0x2f, ++ 0xbe, 0x8d, 0xf7, 0xbb, 0xc4, 0xe8, 0x7c, 0xe8, 0xbf, 0x0d, 0x92, 0xfe, ++ 0xaa, 0xbd, 0xa7, 0x15, 0xbf, 0x2e, 0xf5, 0xfe, 0x8d, 0xba, 0x9e, 0x76, ++ 0x23, 0x2b, 0x22, 0x7b, 0x54, 0x07, 0xfc, 0x01, 0xe6, 0x9b, 0x67, 0xeb, ++ 0x17, 0x05, 0x19, 0xfd, 0xf1, 0x03, 0x22, 0xc5, 0xcb, 0xc7, 0x72, 0x3f, ++ 0x11, 0xe6, 0x08, 0xf3, 0x7b, 0x2f, 0x5c, 0xcf, 0xd3, 0x67, 0xeb, 0x78, ++ 0x3e, 0xc7, 0x18, 0x99, 0xeb, 0x7d, 0xae, 0x81, 0xd1, 0xb1, 0xf1, 0xa2, ++ 0x8f, 0x0a, 0xb9, 0x5c, 0x9f, 0x97, 0xf4, 0x66, 0x8b, 0x0c, 0xf2, 0xef, ++ 0xfd, 0xc2, 0xc0, 0x42, 0xcc, 0x57, 0x9a, 0x37, 0xe2, 0xcd, 0x16, 0x27, ++ 0xd4, 0x4f, 0x15, 0x36, 0x2f, 0xc4, 0x7c, 0xa6, 0x79, 0xd9, 0x6f, 0x7e, ++ 0xea, 0x04, 0x9d, 0xed, 0xb7, 0x85, 0x5f, 0xe1, 0xf5, 0x92, 0x37, 0x3f, ++ 0xcd, 0x83, 0xfa, 0xff, 0x2a, 0x5c, 0xc5, 0xeb, 0xd3, 0x18, 0x01, 0xe5, ++ 0x77, 0x85, 0xab, 0x17, 0x22, 0x5f, 0xfd, 0xa8, 0x50, 0x52, 0xfc, 0x97, ++ 0x91, 0x1c, 0x9c, 0x6f, 0x9e, 0xc0, 0xf1, 0xe5, 0x8b, 0x96, 0x7a, 0x93, ++ 0x2e, 0x61, 0x3c, 0xff, 0x7c, 0xa1, 0xea, 0x4f, 0x64, 0x06, 0x9c, 0xc7, ++ 0xd7, 0xf3, 0xaf, 0x27, 0x91, 0x1f, 0xf9, 0x54, 0xff, 0xab, 0x57, 0x1b, ++ 0x87, 0x64, 0xd8, 0x94, 0x89, 0xf7, 0x86, 0x94, 0x9f, 0x3d, 0x85, 0xf4, ++ 0x99, 0x39, 0xf8, 0x37, 0xc0, 0xf3, 0x66, 0x31, 0xdc, 0x8b, 0xef, 0xeb, ++ 0xcc, 0x61, 0x82, 0xeb, 0x58, 0xcc, 0xa3, 0x29, 0x22, 0x14, 0x78, 0xe2, ++ 0xf2, 0x15, 0xf2, 0x25, 0xe2, 0xf1, 0x48, 0x00, 0x74, 0x6d, 0x45, 0x7d, ++ 0x59, 0x96, 0x58, 0x1d, 0xe8, 0xc7, 0xed, 0xad, 0xcc, 0x6f, 0xc9, 0x8f, ++ 0xc1, 0x73, 0xe6, 0x55, 0xf0, 0x9c, 0xe7, 0xf5, 0xa8, 0xeb, 0x51, 0xe7, ++ 0x1f, 0xb2, 0x2e, 0x38, 0x52, 0x31, 0x2d, 0x76, 0x5d, 0xdb, 0x68, 0x1c, ++ 0x75, 0x5d, 0xe7, 0xca, 0x4c, 0x41, 0xbc, 0x5f, 0xa6, 0xc6, 0x55, 0xd5, ++ 0x75, 0x9d, 0x13, 0x06, 0x9e, 0x41, 0x67, 0xc4, 0x9c, 0x92, 0x9d, 0x8b, ++ 0xf1, 0x5c, 0xcf, 0x25, 0x0f, 0x8c, 0x16, 0xa0, 0xfe, 0xfc, 0xd8, 0xb7, ++ 0xe9, 0x9c, 0xcf, 0x65, 0x0c, 0x3c, 0x23, 0x78, 0x62, 0xea, 0x06, 0x7e, ++ 0x8e, 0x23, 0xc7, 0x3e, 0x4a, 0x7a, 0x4f, 0x8b, 0xe0, 0x1d, 0x39, 0x16, ++ 0xf9, 0xa5, 0xd1, 0x46, 0xf7, 0xd8, 0x3a, 0x15, 0x3d, 0x6f, 0x53, 0x86, ++ 0x3f, 0xc8, 0xb8, 0x7e, 0x4f, 0xf9, 0x8f, 0xc1, 0x5c, 0x7e, 0x3f, 0xa0, ++ 0x7a, 0xa2, 0xe0, 0x8d, 0x8d, 0xfb, 0x3b, 0xc7, 0xf2, 0xb8, 0x49, 0x48, ++ 0x29, 0x67, 0x9a, 0x36, 0x37, 0x9f, 0x00, 0x7c, 0x0c, 0xec, 0x15, 0xd8, ++ 0x1a, 0xe8, 0x1f, 0xb8, 0x74, 0xc1, 0x88, 0xf6, 0xf8, 0xbc, 0x9e, 0x53, ++ 0x46, 0xb4, 0xbb, 0x9b, 0xf6, 0x9e, 0x32, 0xa2, 0x5d, 0xdd, 0x84, 0x75, ++ 0x18, 0xa7, 0x69, 0x9b, 0x91, 0xf8, 0x55, 0x3c, 0xbc, 0x77, 0x8e, 0xd5, ++ 0x6b, 0xe2, 0xeb, 0xaa, 0x3d, 0x71, 0x38, 0xb7, 0x70, 0x9d, 0x1d, 0xd6, ++ 0xd3, 0xb4, 0x42, 0xf0, 0x60, 0xca, 0xec, 0xaa, 0xfd, 0xa9, 0x33, 0xb1, ++ 0xbe, 0x6a, 0x39, 0xee, 0x92, 0xb1, 0xdb, 0x6f, 0xd8, 0x33, 0x13, 0xd1, ++ 0xa5, 0xde, 0xd7, 0xbb, 0x0e, 0xcb, 0x65, 0xac, 0xff, 0x30, 0xde, 0x9f, ++ 0x5b, 0xe2, 0xd7, 0xea, 0xf9, 0x4b, 0x1b, 0xb4, 0x7a, 0x79, 0x7d, 0xb3, ++ 0x56, 0x9f, 0x5e, 0xb6, 0x19, 0x4e, 0x07, 0xe4, 0xd7, 0xb2, 0xd6, 0x6c, ++ 0xcd, 0x7b, 0x0c, 0x35, 0x64, 0x58, 0xcf, 0x12, 0xe5, 0x3c, 0x97, 0x38, ++ 0x1e, 0x8d, 0xe8, 0xc7, 0x63, 0x3d, 0xe6, 0x5e, 0x8e, 0x40, 0x64, 0x4d, ++ 0xfe, 0x9d, 0xa5, 0x7c, 0x07, 0x50, 0x6a, 0xfd, 0x16, 0xf3, 0x7a, 0x04, ++ 0xa2, 0xe3, 0xa6, 0x5a, 0x33, 0xf9, 0x5f, 0x0f, 0xe7, 0xf2, 0x7c, 0xfa, ++ 0xc0, 0x4a, 0x3d, 0xe5, 0x09, 0x05, 0x10, 0x1d, 0xb0, 0xde, 0x2c, 0x28, ++ 0xfe, 0x2c, 0x2f, 0xf1, 0x47, 0x55, 0x7e, 0xcf, 0xec, 0x3e, 0x7f, 0x24, ++ 0x1b, 0xdf, 0x5f, 0x69, 0x20, 0x38, 0xb0, 0xa0, 0x37, 0x82, 0x7e, 0xfd, ++ 0x5a, 0x05, 0x9f, 0x96, 0xd5, 0xd6, 0x7c, 0x8c, 0x78, 0x56, 0x2b, 0xdf, ++ 0xc7, 0xe5, 0xf8, 0x98, 0x5d, 0x06, 0xf2, 0xaf, 0xf8, 0xb9, 0x3e, 0x2e, ++ 0x2b, 0xfe, 0xef, 0xba, 0xee, 0xc7, 0xaa, 0xd3, 0x50, 0xff, 0x6c, 0x11, ++ 0xc8, 0xbf, 0xb1, 0xb4, 0x41, 0xab, 0xaf, 0xd7, 0xe3, 0x1f, 0xa8, 0xbf, ++ 0xb5, 0x0a, 0xa1, 0xb0, 0x13, 0xe1, 0xa4, 0x6d, 0x5f, 0xd6, 0xaa, 0xad, ++ 0xdf, 0x35, 0x56, 0x91, 0x63, 0x25, 0xac, 0x04, 0xe9, 0xa4, 0x61, 0xac, ++ 0x20, 0x12, 0xdd, 0x28, 0xf5, 0x3f, 0xe6, 0xfe, 0xe2, 0x8d, 0x30, 0x4c, ++ 0xf4, 0x90, 0xe0, 0xbb, 0x7f, 0x2c, 0x1c, 0xd0, 0x4a, 0x63, 0x78, 0x3c, ++ 0xca, 0xb5, 0x87, 0x04, 0x3f, 0xd5, 0xd5, 0x76, 0x78, 0xde, 0xc4, 0xe5, ++ 0x0e, 0x97, 0xf7, 0x3a, 0xa0, 0x28, 0xe2, 0xbb, 0x06, 0xee, 0x57, 0x08, ++ 0x36, 0x0a, 0x84, 0x8f, 0x4b, 0x87, 0xc8, 0xff, 0x18, 0xfd, 0x40, 0x3f, ++ 0xb4, 0xfe, 0xcc, 0x58, 0x2e, 0xdf, 0xda, 0x2d, 0xbe, 0x16, 0xb2, 0x97, ++ 0x5e, 0x15, 0x24, 0xd4, 0x47, 0xaa, 0x45, 0xaf, 0x98, 0xe6, 0x8e, 0xda, ++ 0xb3, 0xf1, 0xf8, 0xf8, 0xac, 0x82, 0xdf, 0x6f, 0xb0, 0x7e, 0x37, 0xae, ++ 0xab, 0x10, 0x81, 0x0e, 0xf0, 0x2f, 0x5c, 0x38, 0x22, 0x84, 0xfe, 0xb0, ++ 0xc2, 0x9f, 0x2c, 0xa7, 0x7c, 0xc7, 0xc2, 0x0a, 0xc1, 0xa3, 0x23, 0x7a, ++ 0xd6, 0xb1, 0xd6, 0x72, 0x2c, 0x45, 0xe2, 0x0f, 0xa8, 0x6f, 0x5a, 0xa0, ++ 0x2c, 0xd4, 0x77, 0xd5, 0x12, 0xbf, 0x9e, 0x60, 0x94, 0x78, 0x3e, 0xa1, ++ 0x83, 0xc5, 0xf2, 0x01, 0xef, 0x73, 0x4c, 0xc0, 0xbc, 0x3e, 0x5c, 0x3a, ++ 0xce, 0x7b, 0x73, 0xce, 0xd1, 0xcf, 0xf0, 0x1c, 0x6f, 0xd9, 0xfa, 0xe8, ++ 0x79, 0xe4, 0x77, 0xae, 0x7c, 0x6f, 0xf9, 0x63, 0xb0, 0xbe, 0x4d, 0x16, ++ 0x3e, 0xff, 0xa6, 0xfd, 0x02, 0xe9, 0xaf, 0x4d, 0xee, 0x23, 0xc4, 0x17, ++ 0x47, 0x02, 0x9a, 0xe0, 0xbc, 0x4d, 0x0e, 0x85, 0x3f, 0x76, 0x03, 0x7f, ++ 0x54, 0xf7, 0x0f, 0xe7, 0x3d, 0x12, 0xf9, 0x15, 0x5e, 0x10, 0x99, 0xeb, ++ 0xa6, 0x79, 0x47, 0xa9, 0xf1, 0x01, 0x35, 0xdf, 0x36, 0x5c, 0xa5, 0xbb, ++ 0x0c, 0xe7, 0x37, 0x52, 0x99, 0x77, 0x67, 0xa9, 0x4c, 0xfb, 0xce, 0xbc, ++ 0xaf, 0x4b, 0xc0, 0x7d, 0xe7, 0xb2, 0xe0, 0x1a, 0xf4, 0x13, 0xfd, 0xf3, ++ 0x58, 0x46, 0x70, 0x54, 0x4b, 0xd5, 0x8f, 0xbf, 0x38, 0x1a, 0xc7, 0x76, ++ 0xe2, 0x79, 0x36, 0x3a, 0xfa, 0x8d, 0xa4, 0x7f, 0x2b, 0x71, 0xec, 0x04, ++ 0xfd, 0x4a, 0x12, 0xf6, 0xf3, 0x32, 0x8d, 0x1f, 0x61, 0xa6, 0xfe, 0x52, ++ 0x0a, 0xc6, 0x9b, 0x57, 0xbd, 0x9a, 0x7f, 0xc5, 0x7c, 0x0b, 0xbd, 0x59, ++ 0xa7, 0xa1, 0x57, 0x83, 0x64, 0xd5, 0xd0, 0xf5, 0xcd, 0x45, 0x5a, 0x3a, ++ 0x9f, 0xe7, 0xd1, 0xd2, 0xf7, 0xad, 0x53, 0xf2, 0x35, 0xed, 0xf3, 0xbd, ++ 0x25, 0x9a, 0xf6, 0x85, 0x35, 0x15, 0x9a, 0xfa, 0x62, 0xdf, 0x34, 0x4d, ++ 0xff, 0xdb, 0x6a, 0x67, 0x68, 0xed, 0x7d, 0xc7, 0x1c, 0x4d, 0x7f, 0x8b, ++ 0xbc, 0x40, 0x53, 0x4f, 0x2a, 0xba, 0x5d, 0xd3, 0x3f, 0xd9, 0x73, 0xa7, ++ 0x96, 0xdf, 0xd8, 0xbb, 0x28, 0xaf, 0xc0, 0x68, 0x0e, 0xf6, 0xfb, 0x01, ++ 0x0e, 0x9d, 0x80, 0xab, 0x53, 0xd2, 0xa2, 0xfc, 0xba, 0x24, 0xc5, 0x8c, ++ 0x49, 0xc7, 0xcc, 0x5a, 0x61, 0xb1, 0x61, 0xd9, 0x59, 0x66, 0x0a, 0xe3, ++ 0xb9, 0x75, 0x66, 0xf1, 0x38, 0xab, 0xe9, 0xb5, 0x07, 0x1c, 0x61, 0x84, ++ 0xfa, 0x88, 0x17, 0xcd, 0x95, 0x50, 0xbe, 0x20, 0x84, 0xaa, 0x30, 0x5e, ++ 0x64, 0x56, 0xec, 0xbc, 0xe2, 0x87, 0x99, 0x86, 0x9f, 0x8f, 0x2d, 0xe1, ++ 0x78, 0xae, 0x96, 0xef, 0x8f, 0xf5, 0x7f, 0x5c, 0x04, 0xa5, 0x7b, 0xb7, ++ 0x9c, 0xcd, 0xf3, 0xa7, 0x23, 0xc5, 0x78, 0x3e, 0x66, 0x74, 0x20, 0x22, ++ 0x1e, 0xef, 0x33, 0x93, 0xde, 0x31, 0x21, 0x4e, 0xff, 0xfd, 0x5e, 0x69, ++ 0xe5, 0x6f, 0x51, 0xae, 0xb8, 0x1f, 0xf6, 0xce, 0x26, 0xbf, 0x54, 0x37, ++ 0x93, 0xf0, 0xfe, 0xec, 0x0e, 0x23, 0xcf, 0x73, 0x0a, 0xee, 0xe3, 0xf9, ++ 0xb4, 0xee, 0xee, 0x7e, 0x9d, 0x37, 0x86, 0xde, 0x02, 0x45, 0x5c, 0xde, ++ 0x7f, 0xd3, 0x57, 0x45, 0x79, 0x4b, 0x4d, 0x3d, 0x20, 0xcd, 0x10, 0xbf, ++ 0xb7, 0x9e, 0x36, 0xa2, 0xdf, 0xae, 0xa9, 0xa7, 0x37, 0x05, 0xe5, 0xc6, ++ 0x78, 0xdf, 0x69, 0x23, 0xea, 0xd7, 0xd1, 0xe7, 0x8a, 0x3c, 0x11, 0x07, ++ 0xac, 0x18, 0xbf, 0xfc, 0x97, 0xae, 0xc4, 0xf9, 0x69, 0x63, 0x8a, 0x8c, ++ 0x34, 0xfe, 0x11, 0x85, 0xdf, 0xd6, 0x3f, 0xc0, 0xf9, 0x2d, 0x20, 0xdc, ++ 0x5c, 0xb4, 0x8f, 0x54, 0xfe, 0x59, 0xbf, 0x87, 0xef, 0xaf, 0x7e, 0xb1, ++ 0x91, 0xe8, 0x5b, 0xe5, 0xa3, 0xc0, 0x3f, 0x35, 0xf1, 0xb0, 0x78, 0xbe, ++ 0xbc, 0xf4, 0x86, 0xd0, 0x3a, 0xa4, 0x5d, 0xe0, 0xa3, 0x1a, 0xfb, 0x65, ++ 0xd9, 0xa2, 0x59, 0x1f, 0xa3, 0x3d, 0xc4, 0x58, 0x98, 0xf4, 0x18, 0xe0, ++ 0xa3, 0xda, 0xf6, 0x9c, 0xf5, 0x44, 0xdf, 0xcb, 0xe2, 0xec, 0x9b, 0xe4, ++ 0x22, 0xe0, 0xa7, 0xa8, 0x47, 0x94, 0x30, 0xf7, 0x65, 0xa0, 0x97, 0x93, ++ 0x3e, 0x5d, 0xc2, 0x7d, 0xb9, 0x4b, 0xf8, 0xf7, 0x02, 0x4e, 0xfa, 0x67, ++ 0x10, 0xbc, 0xbf, 0x09, 0x70, 0x43, 0xbb, 0xf1, 0x9b, 0x43, 0xe0, 0xc4, ++ 0xe1, 0x77, 0x35, 0xf8, 0xbc, 0xa4, 0xf8, 0x13, 0xd5, 0x73, 0x8a, 0xef, ++ 0x57, 0x56, 0xc2, 0xf9, 0xe8, 0x4b, 0xc3, 0xf0, 0xcb, 0x07, 0x8a, 0x78, ++ 0xfb, 0x0e, 0x21, 0x52, 0x8e, 0xcc, 0x2c, 0xe0, 0xb3, 0x12, 0x9e, 0x2e, ++ 0x35, 0x9b, 0x17, 0x63, 0xfe, 0xc1, 0x91, 0xdc, 0x3f, 0xad, 0xc7, 0x78, ++ 0x42, 0xfd, 0x0f, 0x04, 0xb4, 0x65, 0xd9, 0xaf, 0x7b, 0x5f, 0xcb, 0xc4, ++ 0x7c, 0x04, 0xe3, 0x9e, 0xc3, 0x99, 0x98, 0x27, 0x11, 0xe8, 0x3a, 0x9c, ++ 0xc9, 0x00, 0x4e, 0x2b, 0x0d, 0xf2, 0x1a, 0xd4, 0x8b, 0x01, 0x0f, 0x3c, ++ 0x6b, 0xe0, 0x5c, 0x9a, 0xba, 0xc3, 0xb4, 0xfe, 0xc6, 0xae, 0x8a, 0x5e, ++ 0x7c, 0xde, 0xd8, 0x2d, 0x78, 0x90, 0x15, 0x06, 0xf6, 0x9e, 0x9f, 0x45, ++ 0xfb, 0x64, 0xfd, 0xeb, 0x51, 0x8f, 0xdf, 0x31, 0xcc, 0xba, 0xa6, 0x15, ++ 0x71, 0x7d, 0x78, 0x56, 0x91, 0xcc, 0xf3, 0x98, 0xfd, 0x30, 0x27, 0xca, ++ 0xd9, 0xbd, 0x26, 0xb2, 0x63, 0xeb, 0xf7, 0x00, 0x1f, 0xc2, 0x75, 0xed, ++ 0x17, 0xe8, 0x5e, 0xc6, 0x8e, 0x0d, 0xe6, 0xda, 0x44, 0xfa, 0xc9, 0x64, ++ 0x84, 0x37, 0xc0, 0xe9, 0xd0, 0x06, 0x23, 0xc3, 0x38, 0xca, 0x4a, 0x78, ++ 0x1f, 0xf7, 0x71, 0x24, 0xf7, 0x88, 0xd1, 0x8c, 0x78, 0xb3, 0x47, 0x20, ++ 0x9b, 0x30, 0xd0, 0x75, 0x62, 0x31, 0xfa, 0xe3, 0x03, 0x2d, 0x06, 0x86, ++ 0x71, 0x5b, 0x75, 0x7d, 0x67, 0x72, 0x23, 0xef, 0xe3, 0xfe, 0xdf, 0x59, ++ 0x61, 0x60, 0x78, 0x8f, 0xb0, 0x7d, 0x05, 0x8f, 0xc7, 0xbe, 0xd3, 0xa2, ++ 0xa7, 0x71, 0xf4, 0x77, 0x1b, 0xa8, 0xbe, 0xe4, 0x5e, 0x9e, 0x37, 0x7c, ++ 0x70, 0xc5, 0x6f, 0xd7, 0x67, 0xc3, 0xb8, 0xef, 0xac, 0x14, 0x28, 0xdf, ++ 0x7e, 0xc6, 0xdd, 0xff, 0x76, 0x04, 0xeb, 0x4b, 0xee, 0xe5, 0x7a, 0x50, ++ 0x3c, 0xfe, 0x0e, 0xe2, 0x6b, 0x1c, 0x7e, 0x2e, 0xf1, 0x6b, 0xf1, 0x6e, ++ 0x08, 0x9e, 0x36, 0x7c, 0x31, 0x3c, 0xbd, 0x33, 0x8a, 0xa7, 0xe3, 0x51, ++ 0xce, 0xc2, 0xb9, 0xcf, 0x1c, 0x89, 0xf8, 0xf3, 0x20, 0xa3, 0x7b, 0x8c, ++ 0xb5, 0x97, 0x0e, 0x1a, 0x46, 0xc2, 0x7a, 0xf3, 0xd6, 0x4b, 0x1e, 0x0c, ++ 0xed, 0x96, 0xea, 0x43, 0xeb, 0x32, 0x91, 0x2f, 0x1c, 0xe4, 0xed, 0x65, ++ 0x2b, 0xb7, 0x0b, 0x9c, 0xbf, 0xc8, 0x74, 0xbf, 0x3d, 0xbb, 0xd3, 0xc8, ++ 0xd0, 0x6e, 0x7c, 0x40, 0x39, 0xaf, 0x07, 0x94, 0xf3, 0x92, 0xd9, 0x80, ++ 0x80, 0xf9, 0x6e, 0x4c, 0x8c, 0xe4, 0xe1, 0xfa, 0x9c, 0x4a, 0x7e, 0xd7, ++ 0xcb, 0x06, 0x56, 0xbb, 0x07, 0xfd, 0x48, 0x22, 0xe7, 0x2f, 0xa5, 0x3f, ++ 0x74, 0x6c, 0x8f, 0xf5, 0x23, 0xb9, 0x14, 0xbe, 0xa2, 0xf2, 0xbd, 0x12, ++ 0xb0, 0xf7, 0xf7, 0x90, 0x1f, 0xba, 0x2b, 0x0b, 0xef, 0x9d, 0xbf, 0x64, ++ 0xe0, 0xfe, 0xb1, 0xd1, 0xca, 0x78, 0x05, 0xf9, 0x03, 0xb3, 0xe6, 0x43, ++ 0xf9, 0xcd, 0x22, 0xce, 0x07, 0xdb, 0x94, 0x75, 0xa8, 0x75, 0xaf, 0x82, ++ 0xff, 0xcc, 0xbe, 0x83, 0xe0, 0x3b, 0xcf, 0xcc, 0xe1, 0x3e, 0xa7, 0x35, ++ 0x5c, 0x87, 0xfb, 0xb8, 0x47, 0xf4, 0xaf, 0x2b, 0x82, 0xf6, 0xb9, 0xa3, ++ 0x7f, 0xb1, 0x92, 0x51, 0x7e, 0xe4, 0xeb, 0x6e, 0x3f, 0xf9, 0xb9, 0x8a, ++ 0x49, 0xae, 0x05, 0x94, 0xf3, 0x38, 0x38, 0xf5, 0x77, 0xdb, 0x56, 0x63, ++ 0x1e, 0xde, 0x38, 0x2b, 0x9d, 0xe3, 0xfc, 0xbe, 0xa7, 0x22, 0x78, 0xae, ++ 0x4d, 0x2e, 0x91, 0xf2, 0x0f, 0x2d, 0x05, 0x13, 0x47, 0xfa, 0xaf, 0xe0, ++ 0x47, 0x08, 0x5c, 0x94, 0x35, 0xf7, 0xf8, 0x9a, 0x7a, 0xce, 0xcf, 0xf2, ++ 0x26, 0xa0, 0xeb, 0x69, 0xca, 0x7a, 0x4b, 0x95, 0xfb, 0x7a, 0xac, 0x87, ++ 0xfb, 0x0f, 0x80, 0x1f, 0x8b, 0x53, 0xca, 0xa3, 0xfd, 0xd4, 0xfd, 0xab, ++ 0x7e, 0x0f, 0x4b, 0xc1, 0x77, 0xe9, 0x9c, 0x56, 0x7f, 0x85, 0x95, 0xf1, ++ 0x7b, 0xfc, 0x8f, 0xd1, 0xfe, 0x97, 0xae, 0x3c, 0x21, 0xe0, 0x3d, 0x95, ++ 0xdb, 0x0c, 0x5e, 0x83, 0x0d, 0xe0, 0xfc, 0x8b, 0x11, 0x6c, 0x31, 0xda, ++ 0xc1, 0xaf, 0xb7, 0x31, 0xba, 0xb7, 0x76, 0x0c, 0xef, 0xaf, 0x01, 0x2b, ++ 0x79, 0xa3, 0x4d, 0xa2, 0x7a, 0x44, 0xb9, 0xc7, 0xf6, 0x66, 0x9b, 0x4c, ++ 0xe5, 0x6d, 0x46, 0xdf, 0x6e, 0x84, 0xcf, 0xe2, 0x43, 0xcd, 0x05, 0x08, ++ 0xaf, 0x83, 0xb9, 0x4f, 0xfa, 0xf0, 0xbb, 0x0c, 0xe7, 0x8e, 0x29, 0xfa, ++ 0x2c, 0x93, 0xf8, 0xbd, 0x46, 0x05, 0xf7, 0x2e, 0xf4, 0xe8, 0x99, 0x19, ++ 0xda, 0x2f, 0xec, 0x15, 0x42, 0xe4, 0x34, 0x51, 0xd6, 0x7f, 0xc7, 0xc5, ++ 0x2c, 0xe6, 0x07, 0x7e, 0xf2, 0x2b, 0xe5, 0xbe, 0x5c, 0x63, 0xeb, 0xcf, ++ 0x89, 0xcf, 0x79, 0x1a, 0xce, 0xcf, 0x42, 0x3b, 0xa3, 0x6c, 0xe5, 0xa9, ++ 0xf5, 0x58, 0x0f, 0xb4, 0xfe, 0xdb, 0x2c, 0xd4, 0x1b, 0xde, 0x07, 0x39, ++ 0x81, 0xf8, 0x15, 0xe8, 0x16, 0x98, 0x03, 0xc6, 0xa9, 0xbb, 0x98, 0x46, ++ 0xef, 0x37, 0x76, 0x9f, 0x30, 0xa2, 0x3d, 0xff, 0x92, 0x6e, 0x60, 0x16, ++ 0xc2, 0x3f, 0x78, 0x40, 0xa0, 0x7b, 0x56, 0x81, 0xe6, 0xf3, 0xc4, 0x3f, ++ 0xb7, 0x29, 0xfe, 0x95, 0x8f, 0x8a, 0x78, 0x1c, 0x31, 0xd0, 0x53, 0xa6, ++ 0xa3, 0xf3, 0xf4, 0x16, 0x73, 0xfb, 0x44, 0x39, 0xff, 0xde, 0xe2, 0x7f, ++ 0x4f, 0x41, 0xfe, 0x65, 0x6e, 0x95, 0x8f, 0x4f, 0xc3, 0x73, 0x3c, 0xaa, ++ 0xa7, 0x73, 0xdc, 0x58, 0x35, 0x90, 0x22, 0x25, 0x38, 0x97, 0x93, 0x30, ++ 0x2e, 0xe6, 0x8f, 0xfc, 0x4a, 0xc9, 0xd3, 0x8b, 0x6f, 0xaf, 0x35, 0x06, ++ 0xc9, 0x2f, 0x5b, 0xab, 0xe0, 0x6d, 0x7c, 0xfb, 0x07, 0x0a, 0x3e, 0x02, ++ 0x84, 0x0d, 0x4a, 0x9e, 0x12, 0x13, 0x60, 0x3d, 0x75, 0x0a, 0x7e, 0xd5, ++ 0xe3, 0xf7, 0x61, 0xd2, 0x50, 0xcf, 0x17, 0xc2, 0x56, 0xa0, 0xdb, 0xfa, ++ 0x9e, 0x19, 0xe4, 0xdf, 0xa8, 0x6f, 0xbe, 0xf2, 0xf7, 0x5e, 0x86, 0xc3, ++ 0xb7, 0x6b, 0x2d, 0x9b, 0x18, 0xf7, 0x6f, 0xa8, 0x75, 0xb4, 0xbf, 0x62, ++ 0xf3, 0xb8, 0xd0, 0xfe, 0xd2, 0xde, 0x4b, 0x0f, 0xd2, 0x3e, 0x4c, 0xb9, ++ 0xae, 0x91, 0xfe, 0x2b, 0xe8, 0x77, 0x81, 0xfe, 0x2c, 0x8a, 0x9f, 0x34, ++ 0x75, 0x32, 0x8a, 0x97, 0x34, 0x5e, 0x2c, 0xa6, 0xf2, 0xec, 0xfe, 0x47, ++ 0xe8, 0x1e, 0x94, 0xd9, 0x3a, 0xf0, 0x24, 0xca, 0x05, 0x56, 0xa8, 0x23, ++ 0xbd, 0xbe, 0x31, 0xa8, 0xd5, 0x6f, 0x8e, 0x17, 0x73, 0x3a, 0x38, 0x5e, ++ 0xcc, 0xe9, 0xf9, 0x52, 0x11, 0xd8, 0x27, 0x66, 0x36, 0x68, 0x9f, 0x80, ++ 0x1d, 0x72, 0x19, 0xf1, 0x12, 0xec, 0x90, 0x94, 0x3e, 0xa6, 0xb1, 0x4f, ++ 0xe2, 0x9f, 0x93, 0x7d, 0x62, 0x56, 0xfc, 0x86, 0xa0, 0x2e, 0xf9, 0x5f, ++ 0x4e, 0xb0, 0xee, 0xb7, 0x8a, 0xab, 0xc4, 0x71, 0x19, 0x48, 0x57, 0x9b, ++ 0x09, 0xbf, 0x19, 0xe0, 0x37, 0xe2, 0x55, 0xfc, 0x3e, 0x47, 0x8c, 0xe3, ++ 0xeb, 0x52, 0xe9, 0x79, 0x49, 0xdf, 0xc7, 0x46, 0xd4, 0x77, 0x03, 0xdd, ++ 0x89, 0xe9, 0xf9, 0x37, 0xc5, 0x95, 0x23, 0x70, 0xdc, 0x0d, 0xc3, 0xe4, ++ 0xe5, 0xbd, 0x5d, 0xcc, 0xf9, 0x5d, 0xe3, 0x56, 0x46, 0xf0, 0x0a, 0x6c, ++ 0x4d, 0x23, 0x38, 0x9d, 0x61, 0x5b, 0x7d, 0x55, 0x80, 0x97, 0x67, 0x60, ++ 0x1d, 0x78, 0x4f, 0xfd, 0x9c, 0xcf, 0x97, 0x94, 0x0a, 0xef, 0x9f, 0xf3, ++ 0xfb, 0x92, 0x30, 0x3e, 0xa7, 0xd2, 0x7f, 0xd3, 0x56, 0x2b, 0xbd, 0xb7, ++ 0xc1, 0xb5, 0x20, 0x1d, 0xbf, 0xab, 0xe1, 0x1a, 0xc7, 0xbf, 0xeb, 0x73, ++ 0xb6, 0x7b, 0x86, 0x19, 0xe1, 0x7c, 0xc7, 0x56, 0x4e, 0x77, 0xea, 0x7c, ++ 0xef, 0x87, 0x97, 0xa4, 0x23, 0xfd, 0x4c, 0x32, 0x0c, 0x18, 0xd1, 0x3f, ++ 0x99, 0xd3, 0x73, 0x2a, 0x05, 0xf5, 0xba, 0x49, 0xfb, 0x17, 0xa6, 0x23, ++ 0xfd, 0x0d, 0xb7, 0x4e, 0xbb, 0x72, 0x1e, 0x8d, 0xad, 0x59, 0x8b, 0xe9, ++ 0x1e, 0x10, 0xfc, 0xf4, 0x40, 0xf7, 0xf7, 0x2b, 0x72, 0x2c, 0xb0, 0x36, ++ 0x6c, 0x44, 0xf8, 0xdf, 0xdf, 0xca, 0x08, 0x7f, 0x7b, 0xf7, 0xfd, 0xba, ++ 0x09, 0xe9, 0xf7, 0x6c, 0x4f, 0x92, 0x84, 0x72, 0xf2, 0xcc, 0xab, 0x49, ++ 0x41, 0xe4, 0xf7, 0xe7, 0x0e, 0x98, 0x42, 0x3a, 0x18, 0x6a, 0xa5, 0xf2, ++ 0x3d, 0xa4, 0x33, 0x86, 0xfe, 0x5b, 0x48, 0x7f, 0xdc, 0xaf, 0xa7, 0x7c, ++ 0x85, 0xc0, 0x81, 0x3f, 0x3c, 0x89, 0xf4, 0x18, 0xd8, 0x67, 0xa2, 0x7b, ++ 0x35, 0xf7, 0xf7, 0x3c, 0x72, 0x1e, 0xe5, 0xdc, 0xca, 0x9e, 0xd9, 0x1f, ++ 0x8b, 0x58, 0xbe, 0xf8, 0xf7, 0xa5, 0x87, 0xc6, 0xd6, 0xd1, 0x8b, 0x63, ++ 0xf3, 0x8e, 0xff, 0xd0, 0xb6, 0x3b, 0x0b, 0xf9, 0xe7, 0x59, 0x91, 0xf3, ++ 0x89, 0xfb, 0xbb, 0x5f, 0x21, 0x7d, 0xf6, 0xfe, 0x4b, 0x17, 0xc6, 0x63, ++ 0xfe, 0xe0, 0x99, 0x57, 0xff, 0x63, 0x32, 0xf2, 0xb3, 0xc0, 0x4f, 0x2e, ++ 0x4c, 0x46, 0x3e, 0x16, 0xf8, 0xf1, 0x85, 0xc9, 0xd8, 0x1e, 0xf8, 0x61, ++ 0x52, 0x73, 0x22, 0xfd, 0x64, 0x66, 0x09, 0xff, 0xce, 0x86, 0x2a, 0x1f, ++ 0x9d, 0x6f, 0x89, 0x1a, 0x3f, 0xcb, 0x39, 0x05, 0x3f, 0x9c, 0x1d, 0x9b, ++ 0x6b, 0xf0, 0xbb, 0x05, 0x93, 0x4e, 0x2c, 0xa2, 0x38, 0x80, 0xda, 0x3e, ++ 0xa9, 0x40, 0xe7, 0xc3, 0xfe, 0x93, 0xde, 0xae, 0x4e, 0xbf, 0x3b, 0xe6, ++ 0xbd, 0x8e, 0x88, 0x48, 0xf9, 0x12, 0x13, 0x4f, 0x54, 0x27, 0xad, 0x88, ++ 0xc1, 0xcb, 0x0f, 0x8a, 0x0d, 0xaa, 0x9f, 0xee, 0xda, 0xfc, 0x23, 0x4a, ++ 0x1e, 0x82, 0xea, 0x1f, 0xd9, 0x10, 0x11, 0xf9, 0x3d, 0xbb, 0x06, 0x7d, ++ 0x08, 0xf3, 0x7b, 0x97, 0x46, 0x78, 0xfc, 0x3d, 0xde, 0x6f, 0xc2, 0x98, ++ 0xef, 0xe6, 0x52, 0x3c, 0xef, 0x7b, 0x33, 0x3c, 0xf8, 0xbd, 0x1e, 0xbc, ++ 0xa7, 0x8e, 0x71, 0x91, 0x73, 0x0f, 0x16, 0x84, 0xe8, 0x9e, 0x7a, 0xd0, ++ 0x7c, 0xd8, 0x15, 0xa3, 0x07, 0x2d, 0x89, 0xe8, 0xc2, 0x26, 0xf4, 0x83, ++ 0xf4, 0x98, 0xc2, 0xa8, 0x0f, 0x2d, 0x89, 0x88, 0xa7, 0x4c, 0x31, 0x7e, ++ 0x91, 0xf7, 0xa5, 0x97, 0xd7, 0xa1, 0x1a, 0xbf, 0xc4, 0xaf, 0xf5, 0x63, ++ 0xc4, 0xfb, 0x41, 0xe0, 0x97, 0x2c, 0xc6, 0xc4, 0x4f, 0xea, 0x5b, 0xc2, ++ 0x06, 0x55, 0x4e, 0xcd, 0x83, 0xf9, 0x7f, 0xb1, 0x8e, 0x49, 0x18, 0xb7, ++ 0x19, 0xe2, 0x1f, 0xa9, 0xfd, 0x12, 0xf9, 0x61, 0xe2, 0xfd, 0x24, 0x72, ++ 0xe4, 0x09, 0x33, 0xbe, 0x27, 0xbb, 0xf8, 0xf7, 0x75, 0x54, 0x3d, 0x13, ++ 0xcf, 0x6b, 0x6f, 0x02, 0x7a, 0xb7, 0x29, 0x74, 0xa2, 0xd2, 0x51, 0x47, ++ 0x44, 0x47, 0xe7, 0xd0, 0x11, 0xa9, 0x32, 0xbb, 0xa0, 0x34, 0x28, 0xed, ++ 0x7b, 0x41, 0x6c, 0x06, 0x31, 0x2f, 0xa8, 0x67, 0xe1, 0x4e, 0xb4, 0xd3, ++ 0x3b, 0x2e, 0xdd, 0x96, 0x84, 0xf0, 0xea, 0x78, 0x6b, 0x01, 0xc3, 0xef, ++ 0x47, 0x9c, 0x93, 0xaa, 0xcc, 0x05, 0xf8, 0xde, 0xa5, 0x2f, 0x99, 0x17, ++ 0xbb, 0xa3, 0xf8, 0x31, 0x84, 0x7f, 0x8c, 0xe3, 0x72, 0x65, 0x50, 0x1f, ++ 0x18, 0x46, 0xce, 0x1d, 0x51, 0xf8, 0xd6, 0xdf, 0x4b, 0xde, 0xf5, 0x8d, ++ 0xfb, 0xef, 0x21, 0xef, 0xc0, 0xae, 0x7e, 0x6d, 0x1c, 0xb7, 0xab, 0x97, ++ 0x72, 0xbf, 0x07, 0xb7, 0xab, 0xe3, 0xe5, 0x84, 0xca, 0x7f, 0xd5, 0x71, ++ 0x3f, 0x53, 0xe0, 0x3d, 0x94, 0xff, 0x7e, 0x4c, 0xfa, 0x0b, 0xd8, 0xbf, ++ 0xc4, 0x7f, 0x3f, 0x1b, 0x27, 0xf3, 0xef, 0x34, 0xf4, 0xcc, 0x4f, 0x27, ++ 0xbb, 0xf8, 0xad, 0x45, 0xe9, 0xb2, 0x6d, 0xe8, 0xf8, 0xf9, 0xa2, 0x47, ++ 0x97, 0xe6, 0x1e, 0x3a, 0xbe, 0xaa, 0xaf, 0x05, 0x82, 0xde, 0xc3, 0x66, ++ 0xb4, 0x63, 0xbc, 0x3c, 0xff, 0x34, 0xb0, 0x48, 0xa0, 0xef, 0x48, 0x05, ++ 0x7c, 0x02, 0xe9, 0xd9, 0x81, 0x3a, 0x43, 0x08, 0xdb, 0xd5, 0xf5, 0x44, ++ 0x16, 0xf1, 0xb8, 0xe0, 0x62, 0x8f, 0x40, 0xdf, 0x05, 0x51, 0xf5, 0x3f, ++ 0x55, 0x3f, 0x1c, 0x6c, 0x9f, 0x08, 0xed, 0xce, 0xa8, 0xbe, 0xa8, 0xea, ++ 0x85, 0x11, 0x1f, 0xf7, 0x8b, 0x2e, 0xf2, 0x1a, 0xa8, 0xfd, 0x36, 0xa3, ++ 0x7f, 0x60, 0xdc, 0x24, 0xdc, 0x9f, 0x85, 0x9e, 0x4f, 0x9a, 0xca, 0xc7, ++ 0x05, 0x3e, 0x70, 0x18, 0xfd, 0x9f, 0xb7, 0x7d, 0x59, 0xa0, 0xef, 0x76, ++ 0xa9, 0xfa, 0xa2, 0x8a, 0x9f, 0xf1, 0xfa, 0xe4, 0x27, 0x3d, 0xf9, 0x57, ++ 0xfc, 0x1e, 0xdd, 0x36, 0x05, 0x2f, 0x55, 0xfa, 0x1a, 0x1d, 0x47, 0x17, ++ 0xaa, 0x9c, 0x72, 0x29, 0xf0, 0x69, 0x42, 0x39, 0x9d, 0x8e, 0x72, 0xfa, ++ 0x33, 0x63, 0xbf, 0x6d, 0x78, 0xbd, 0x1b, 0xe4, 0xb4, 0x58, 0x4c, 0xef, ++ 0x31, 0xc2, 0xdb, 0x89, 0x6f, 0x8b, 0xbe, 0x44, 0x76, 0xf7, 0xb7, 0xc6, ++ 0x71, 0x7e, 0x6c, 0x2f, 0x56, 0xce, 0x2d, 0x72, 0xa8, 0x12, 0xd7, 0x9b, ++ 0xcb, 0x22, 0x94, 0x17, 0x35, 0x9c, 0xfc, 0xfc, 0xb4, 0x98, 0xd3, 0xc3, ++ 0x70, 0xed, 0xae, 0x71, 0x5c, 0xcf, 0xb9, 0x1a, 0x1d, 0x4f, 0x2f, 0xfe, ++ 0xfb, 0xd2, 0xf1, 0xb4, 0xe2, 0xff, 0x1e, 0x74, 0x3c, 0xa8, 0xff, 0x19, ++ 0x13, 0xef, 0xf3, 0xad, 0xe2, 0xca, 0x6a, 0x3c, 0x7f, 0xab, 0xbe, 0x99, ++ 0xee, 0x4d, 0xb1, 0x9f, 0x1a, 0xc8, 0x6f, 0x1d, 0xdf, 0xef, 0x33, 0x05, ++ 0xfe, 0x20, 0xcf, 0x34, 0x78, 0x7c, 0x38, 0xd7, 0xa8, 0x43, 0xbb, 0x27, ++ 0xd0, 0xc0, 0xed, 0xfe, 0xce, 0x54, 0xf9, 0x38, 0xd9, 0x27, 0xaf, 0xf1, ++ 0x7b, 0xf8, 0xf7, 0x2b, 0xf9, 0x4a, 0xf7, 0x5d, 0x94, 0xa8, 0xec, 0xc4, ++ 0x0f, 0x85, 0x61, 0xfb, 0x03, 0x4e, 0xf2, 0xdb, 0xdc, 0xb7, 0xfb, 0x84, ++ 0xc1, 0x0b, 0xef, 0x2f, 0x6d, 0x11, 0xca, 0xd0, 0x1f, 0xb4, 0xb4, 0x41, ++ 0xbb, 0x9f, 0xce, 0x0c, 0xef, 0xec, 0x58, 0x3f, 0x78, 0xe7, 0xa8, 0x2e, ++ 0x8a, 0x2b, 0x04, 0x77, 0xe6, 0xcb, 0x38, 0x7e, 0x3d, 0x6e, 0x16, 0xfd, ++ 0x21, 0x9d, 0x59, 0x21, 0x8c, 0x3d, 0x36, 0xa1, 0x1f, 0x67, 0x02, 0x3e, ++ 0x8f, 0xb9, 0x87, 0x01, 0xf3, 0x34, 0x2a, 0xcf, 0xa7, 0x29, 0xfe, 0x1d, ++ 0x16, 0xa7, 0x07, 0xfc, 0xb8, 0xf7, 0x1d, 0xf2, 0xf7, 0x60, 0x5c, 0x08, ++ 0xe9, 0xd7, 0xd8, 0x23, 0x50, 0x5e, 0x48, 0xe0, 0x28, 0xf7, 0x77, 0x34, ++ 0xf5, 0x70, 0xbe, 0xf0, 0x51, 0x83, 0x40, 0xfc, 0xe4, 0x23, 0x25, 0x3f, ++ 0x23, 0xd0, 0x6a, 0x21, 0xff, 0xb6, 0xaa, 0x47, 0x7c, 0xac, 0xf4, 0xbb, ++ 0xf7, 0x41, 0x81, 0xf4, 0xbd, 0x21, 0x7a, 0x85, 0x57, 0x1b, 0x77, 0x69, ++ 0xfc, 0xee, 0xdb, 0xc4, 0x17, 0xe3, 0xf5, 0x88, 0xb4, 0xbd, 0x7c, 0x1c, ++ 0x8c, 0xb7, 0xa0, 0x5f, 0xe6, 0x70, 0xee, 0x64, 0x01, 0xeb, 0x8d, 0x60, ++ 0x17, 0x8e, 0x44, 0x7d, 0x51, 0x96, 0x6f, 0xcd, 0xe6, 0xeb, 0x63, 0x21, ++ 0xe2, 0x2f, 0x5e, 0x8d, 0x1f, 0xe5, 0x93, 0xa3, 0xbf, 0x25, 0x3b, 0x72, ++ 0xe9, 0x7e, 0x81, 0xa5, 0x93, 0xde, 0x11, 0x17, 0x7f, 0xe9, 0x9c, 0x13, ++ 0x17, 0x7f, 0x39, 0x72, 0x38, 0x1b, 0xc7, 0x51, 0xf4, 0x0c, 0x09, 0xfe, ++ 0x0f, 0xfd, 0x87, 0xf1, 0x7a, 0x46, 0x53, 0xf7, 0x09, 0x03, 0xda, 0x05, ++ 0x57, 0x8b, 0xb3, 0x6c, 0x2e, 0xd6, 0xfa, 0x05, 0xc7, 0x88, 0xdc, 0xcf, ++ 0x3a, 0xa6, 0x47, 0x90, 0xd0, 0x9f, 0x34, 0x46, 0x81, 0xd3, 0x75, 0x1b, ++ 0xac, 0x04, 0xa7, 0x59, 0xef, 0xad, 0x48, 0x47, 0x3a, 0x57, 0xcf, 0xe7, ++ 0xec, 0x7c, 0x7e, 0x5e, 0x67, 0xdf, 0xf9, 0xb4, 0x12, 0xdf, 0x9b, 0xfc, ++ 0x9e, 0x28, 0x21, 0xbf, 0xfd, 0xf1, 0x3b, 0x2d, 0x3f, 0xcf, 0xe6, 0x75, ++ 0xd9, 0x2c, 0xe3, 0x7b, 0x2d, 0x49, 0x68, 0x87, 0x9c, 0x7d, 0x6f, 0x55, ++ 0x12, 0xc2, 0xf1, 0xc7, 0x50, 0xe2, 0xf7, 0x92, 0x7e, 0x78, 0x52, 0x4c, ++ 0xe8, 0x3f, 0xfc, 0x6b, 0xf1, 0xa0, 0xdf, 0x78, 0x67, 0x31, 0xca, 0xb7, ++ 0x87, 0x15, 0xbf, 0xb1, 0x08, 0xf2, 0x2d, 0x39, 0xea, 0x7f, 0x89, 0x7f, ++ 0x2f, 0xa7, 0x84, 0xf3, 0xa9, 0x4e, 0xfc, 0x8e, 0x11, 0xe2, 0xdf, 0x7e, ++ 0x1e, 0xdf, 0xee, 0x1c, 0xe5, 0x9f, 0x43, 0xf5, 0xa7, 0xf2, 0x78, 0x1e, ++ 0xb1, 0xc8, 0xf1, 0xf5, 0x95, 0x9e, 0x54, 0x09, 0xf5, 0xbd, 0x12, 0xd8, ++ 0x2c, 0xc6, 0x61, 0xbf, 0x6f, 0x65, 0x1d, 0x18, 0x5f, 0xe9, 0xcc, 0xf0, ++ 0xbf, 0x4e, 0xf4, 0xf1, 0x94, 0x8e, 0xf0, 0x17, 0xde, 0xe7, 0xdf, 0xa1, ++ 0xd8, 0x23, 0x93, 0xbc, 0xc3, 0xd0, 0x14, 0xc6, 0x3f, 0xc6, 0x83, 0xac, ++ 0x31, 0x53, 0x5e, 0xa3, 0x9d, 0xe2, 0x20, 0xea, 0x77, 0x62, 0x46, 0x81, ++ 0x1d, 0xaa, 0x7c, 0x57, 0x61, 0x11, 0xc6, 0x5d, 0x4b, 0x94, 0x38, 0xc8, ++ 0x78, 0x2b, 0x13, 0x71, 0xfc, 0x4d, 0x06, 0xff, 0xc6, 0x71, 0x18, 0x77, ++ 0xe9, 0x15, 0x3d, 0x6b, 0xf0, 0x1d, 0xd1, 0x93, 0x8e, 0xdf, 0x45, 0x8a, ++ 0x8f, 0xc7, 0xa8, 0xf1, 0x61, 0x35, 0x2e, 0xa3, 0xc6, 0x89, 0x87, 0x8b, ++ 0xcb, 0x08, 0x38, 0xcf, 0x78, 0x8e, 0x67, 0xb1, 0xdf, 0x3d, 0x51, 0xe3, ++ 0x2f, 0xec, 0xcb, 0x3c, 0x7f, 0xb3, 0x7d, 0x4a, 0x33, 0xdd, 0x8b, 0xdd, ++ 0x8e, 0x31, 0x12, 0xe2, 0x9f, 0x43, 0xe2, 0x29, 0x7f, 0x46, 0x3b, 0x35, ++ 0x3e, 0x9e, 0x22, 0xa2, 0xfc, 0xa1, 0x38, 0x8d, 0x36, 0x9e, 0xb6, 0xb1, ++ 0xe8, 0x65, 0xc2, 0xb7, 0xcf, 0x1b, 0x47, 0x9b, 0x5e, 0x3c, 0xdc, 0xfc, ++ 0x32, 0xb7, 0xe7, 0xe2, 0xe6, 0x9f, 0x98, 0xfa, 0x49, 0x26, 0xd9, 0x2f, ++ 0x7f, 0xf9, 0x73, 0x0a, 0xc9, 0xb3, 0x9e, 0x0b, 0x24, 0x77, 0xce, 0x0d, ++ 0x98, 0x94, 0xfb, 0x9d, 0xfd, 0xdc, 0x4f, 0xdd, 0x63, 0x20, 0x7b, 0xfd, ++ 0x1c, 0xd8, 0x41, 0x19, 0x31, 0xf2, 0x6c, 0xf9, 0x38, 0x0e, 0x87, 0xbe, ++ 0x9e, 0x19, 0x84, 0x8f, 0x7b, 0x23, 0xd5, 0x49, 0xd8, 0xbf, 0x53, 0xd1, ++ 0x73, 0x36, 0xbc, 0xb5, 0x68, 0x21, 0xea, 0xd3, 0xc1, 0x88, 0xc8, 0xf3, ++ 0xb1, 0x19, 0xb7, 0x6b, 0xf6, 0x46, 0xc4, 0x49, 0x5c, 0x3f, 0x18, 0x02, ++ 0x27, 0xa9, 0x38, 0x41, 0xdc, 0xc9, 0x6c, 0x4d, 0x9c, 0x07, 0x14, 0x56, ++ 0xfc, 0x05, 0x61, 0x65, 0xdf, 0x33, 0xde, 0xe1, 0xf6, 0x4a, 0xa0, 0x85, ++ 0xc7, 0x0f, 0x24, 0x85, 0xde, 0x02, 0x35, 0x46, 0xe2, 0x27, 0x47, 0x72, ++ 0x33, 0x05, 0xd5, 0x8f, 0x3c, 0x32, 0x51, 0x7c, 0x61, 0xff, 0x00, 0xf1, ++ 0xd9, 0xfa, 0x7b, 0x79, 0x7c, 0xf7, 0x9a, 0xe3, 0x0b, 0xdd, 0xbd, 0x06, ++ 0x96, 0x97, 0xc0, 0x6f, 0x5b, 0x33, 0x8b, 0xf8, 0xcd, 0xb5, 0xfa, 0x6b, ++ 0x19, 0x5a, 0xc1, 0x93, 0xa3, 0xfc, 0x39, 0xab, 0x44, 0xe1, 0x27, 0xa5, ++ 0x8a, 0xff, 0xb6, 0x98, 0xe7, 0xf3, 0xa7, 0x35, 0x97, 0x55, 0xe2, 0xf7, ++ 0xef, 0xc2, 0xc3, 0x9e, 0xb7, 0x7f, 0x63, 0x49, 0x82, 0xf3, 0x4e, 0xd0, ++ 0x6f, 0xab, 0xfb, 0xda, 0xe2, 0x81, 0xbf, 0xbe, 0xc6, 0xb8, 0x61, 0x6a, ++ 0xd1, 0xb5, 0xf5, 0x1b, 0x93, 0x88, 0x1e, 0x12, 0xf4, 0x9b, 0x7e, 0x8d, ++ 0xe3, 0x7d, 0xf3, 0x1a, 0xfb, 0xb5, 0x5d, 0xe3, 0xbc, 0x0b, 0xc7, 0x25, ++ 0xea, 0xf7, 0xff, 0x68, 0xfc, 0x33, 0x3e, 0xbe, 0x19, 0x1f, 0x0f, 0x8d, ++ 0x8f, 0x73, 0x9a, 0x5e, 0xbb, 0x3b, 0x88, 0x6d, 0x8f, 0x08, 0x8f, 0x0e, ++ 0x84, 0x11, 0xba, 0x29, 0xfb, 0x6a, 0x05, 0x20, 0x55, 0x31, 0xf5, 0xbb, ++ 0x66, 0xe4, 0x6b, 0x73, 0xa7, 0xf2, 0x78, 0xc0, 0x86, 0x6a, 0x73, 0x68, ++ 0xbb, 0x10, 0x8d, 0x8b, 0xaa, 0xf0, 0x0a, 0x96, 0x72, 0xbd, 0x4b, 0x72, ++ 0x9f, 0x0f, 0xe2, 0x77, 0x12, 0x47, 0x7b, 0x23, 0xd5, 0xe9, 0x40, 0xc7, ++ 0xe7, 0xa6, 0x32, 0xb2, 0x1b, 0xce, 0x59, 0x94, 0xef, 0x23, 0x89, 0xd2, ++ 0xa8, 0xf9, 0x74, 0x7e, 0x12, 0x7d, 0x1f, 0xa7, 0xd3, 0x92, 0x38, 0xbe, ++ 0x34, 0x51, 0x19, 0x6f, 0x38, 0x3e, 0xf2, 0xbd, 0xd2, 0xca, 0xf5, 0x48, ++ 0x2f, 0xd2, 0x30, 0xdf, 0xaf, 0xc8, 0x2d, 0xe1, 0x76, 0x80, 0xd4, 0xcd, ++ 0xc8, 0x5f, 0xc3, 0x44, 0x79, 0xd4, 0x02, 0x9a, 0x57, 0x1e, 0x45, 0xdf, ++ 0xdf, 0x3b, 0xc4, 0x9f, 0xa7, 0x84, 0x19, 0xe5, 0xf7, 0x41, 0xbb, 0x73, ++ 0x01, 0xe9, 0xcf, 0xb2, 0x13, 0xd7, 0xb7, 0x45, 0x89, 0x7b, 0xa5, 0xcd, ++ 0x29, 0x74, 0xa2, 0x9f, 0x2e, 0x0d, 0xe4, 0x2d, 0xc6, 0x45, 0x1e, 0xc3, ++ 0xf8, 0x08, 0xf9, 0xf5, 0x25, 0xea, 0xa7, 0xce, 0x97, 0xec, 0xe6, 0xf3, ++ 0x6d, 0x31, 0x30, 0x01, 0xe3, 0x58, 0xc1, 0x71, 0x3c, 0xaf, 0x82, 0x75, ++ 0x7c, 0x5f, 0x13, 0xd7, 0x38, 0x66, 0x08, 0x7f, 0xb0, 0x5c, 0xa0, 0xb8, ++ 0xc6, 0x76, 0x5c, 0xff, 0xcf, 0x74, 0x61, 0xf7, 0x0e, 0x27, 0x3f, 0x17, ++ 0x84, 0xaf, 0x7b, 0xaf, 0x44, 0xf1, 0x96, 0x37, 0xa6, 0x7e, 0xaf, 0x88, ++ 0xee, 0xcb, 0x2b, 0x71, 0x8e, 0xd5, 0x12, 0xef, 0x72, 0x10, 0xed, 0x0c, ++ 0x58, 0xc7, 0xea, 0x57, 0x2b, 0x08, 0x7f, 0x97, 0xf6, 0x4d, 0xfd, 0x65, ++ 0x1d, 0xea, 0x83, 0x2e, 0x91, 0xe0, 0x3c, 0x44, 0x0f, 0x57, 0xec, 0xab, ++ 0x93, 0x8a, 0x7d, 0xa8, 0xda, 0x57, 0xfd, 0x68, 0x27, 0xc6, 0xd8, 0x1b, ++ 0x3f, 0x50, 0xf4, 0x86, 0x04, 0x74, 0xf5, 0x83, 0x44, 0x7c, 0x69, 0x8b, ++ 0xc0, 0xed, 0xdf, 0xe0, 0xcf, 0xb8, 0xfd, 0x5b, 0x61, 0xf4, 0xe4, 0xc7, ++ 0xe6, 0x53, 0xf5, 0x2a, 0x71, 0x92, 0xe5, 0x61, 0xee, 0x87, 0x55, 0xed, ++ 0xda, 0xf1, 0xde, 0x90, 0x2e, 0x13, 0xe0, 0x50, 0xf1, 0xa0, 0x3e, 0x6c, ++ 0x02, 0x39, 0x5d, 0xb1, 0xbe, 0xd4, 0x88, 0xfc, 0xba, 0x62, 0x7d, 0xae, ++ 0x95, 0xfc, 0x4a, 0x2b, 0xf6, 0xe8, 0x54, 0x78, 0x27, 0x3a, 0xf7, 0x9f, ++ 0x2a, 0xeb, 0xdc, 0x70, 0x74, 0x80, 0xe2, 0x12, 0xaf, 0xc4, 0xc5, 0x27, ++ 0x93, 0xdd, 0x46, 0x6a, 0x7f, 0x48, 0xc1, 0x9f, 0x64, 0x3c, 0x5b, 0x28, ++ 0x57, 0x17, 0x88, 0xed, 0x28, 0x7e, 0x47, 0xdc, 0x20, 0xe9, 0x13, 0xf9, ++ 0xc5, 0xeb, 0x41, 0xef, 0xc7, 0xf5, 0x2d, 0xef, 0xe4, 0xeb, 0x55, 0xe3, ++ 0x20, 0xf5, 0x61, 0x79, 0x06, 0xce, 0x73, 0xea, 0xf0, 0xc0, 0x7a, 0x2c, ++ 0xcb, 0x1b, 0x9c, 0x33, 0xc8, 0x6f, 0xb8, 0xf2, 0xfc, 0x7a, 0x94, 0x9b, ++ 0x81, 0x4b, 0x17, 0x8e, 0x4c, 0x27, 0x3f, 0x80, 0x51, 0x4e, 0x74, 0x5f, ++ 0x60, 0x4b, 0x29, 0xf7, 0x1f, 0xbe, 0x82, 0x8a, 0x08, 0xc2, 0x6b, 0xb6, ++ 0x48, 0x79, 0xbb, 0x15, 0xb3, 0x45, 0x3a, 0xef, 0xb4, 0x7a, 0x0b, 0xd9, ++ 0xe1, 0x69, 0x06, 0xa6, 0xc7, 0xef, 0xb0, 0xa6, 0xcd, 0xe7, 0x72, 0xac, ++ 0xbc, 0xc6, 0x3e, 0x03, 0xeb, 0x6c, 0x51, 0x2a, 0xc9, 0xe1, 0xf2, 0xa3, ++ 0x72, 0xea, 0xdd, 0xee, 0xa8, 0x9d, 0x9f, 0x36, 0xbb, 0x25, 0x03, 0xe1, ++ 0x74, 0xb5, 0xf8, 0x90, 0xea, 0x2f, 0xb8, 0xcd, 0xe8, 0xfd, 0x63, 0x49, ++ 0xc6, 0xe7, 0x8f, 0x0f, 0x35, 0x1e, 0x7b, 0x8b, 0xf2, 0xcc, 0xee, 0xe8, ++ 0xd7, 0xc6, 0x87, 0xd4, 0x78, 0xcf, 0x70, 0xf1, 0x21, 0x35, 0x3e, 0x1b, ++ 0xa8, 0xf9, 0x54, 0x13, 0x4f, 0x0e, 0x88, 0x03, 0xb3, 0xd0, 0xaf, 0x52, ++ 0xf1, 0xea, 0x29, 0x8a, 0x0f, 0x07, 0xba, 0x05, 0xc9, 0xe1, 0x8c, 0xc6, ++ 0x8d, 0x02, 0x7b, 0xcf, 0x1b, 0x09, 0xbe, 0x4a, 0xbc, 0x08, 0xfa, 0x1b, ++ 0xf1, 0xbd, 0x0a, 0x38, 0xf6, 0x51, 0x69, 0xf8, 0x1d, 0x02, 0x1e, 0x3f, ++ 0xda, 0x87, 0xf9, 0xb8, 0x46, 0xfc, 0xbe, 0x9e, 0x44, 0x79, 0xb7, 0x3f, ++ 0xc2, 0x7c, 0xdc, 0x42, 0xfc, 0xbe, 0x1e, 0xcf, 0xc7, 0x3d, 0x80, 0xf9, ++ 0xb8, 0x46, 0xbc, 0xff, 0xc1, 0xf3, 0x71, 0xfb, 0x94, 0xfc, 0xde, 0x40, ++ 0xcf, 0x79, 0x8a, 0x37, 0xa5, 0xb9, 0x87, 0xe4, 0x53, 0x51, 0x3c, 0xe2, ++ 0x21, 0xc1, 0x97, 0xe1, 0x9e, 0xa4, 0x89, 0x57, 0x50, 0x3d, 0x3e, 0x5e, ++ 0xa1, 0xb7, 0x72, 0x3b, 0x34, 0x70, 0xd4, 0x40, 0xdf, 0x3f, 0x0f, 0x1c, ++ 0x33, 0x13, 0x9f, 0xad, 0xec, 0x59, 0x3e, 0x06, 0xf5, 0x31, 0xf5, 0xbb, ++ 0xe4, 0x4d, 0x18, 0x2f, 0x88, 0xf1, 0x2f, 0x9d, 0xf5, 0x7a, 0x2c, 0x78, ++ 0xbf, 0xe7, 0xac, 0xcf, 0x63, 0xc1, 0x38, 0x41, 0x45, 0xef, 0xc7, 0x46, ++ 0x99, 0xf8, 0x4e, 0x38, 0x1b, 0x53, 0x98, 0x9a, 0xc4, 0x88, 0x11, 0xed, ++ 0x7d, 0x84, 0x03, 0xe5, 0xf9, 0xf5, 0x54, 0x5a, 0x10, 0xae, 0x57, 0xf5, ++ 0xeb, 0x77, 0xff, 0x7f, 0xbf, 0xfe, 0xe7, 0xf1, 0xeb, 0x7f, 0x2b, 0x4a, ++ 0x97, 0xc4, 0x3f, 0xca, 0x7d, 0x3a, 0xba, 0x57, 0x5e, 0x7e, 0xd4, 0x6b, ++ 0xb9, 0x3b, 0x86, 0x3f, 0x6c, 0xf0, 0x71, 0xff, 0xf0, 0x06, 0x57, 0x1e, ++ 0xd1, 0xdf, 0x13, 0xbe, 0xbc, 0xd4, 0x15, 0xb1, 0x7e, 0xfc, 0x1a, 0x6e, ++ 0xbf, 0xa5, 0xcd, 0x76, 0x59, 0x62, 0x9f, 0xbf, 0x5b, 0xca, 0xfd, 0xf8, ++ 0x69, 0x42, 0xe2, 0xfb, 0x05, 0x77, 0xb9, 0x87, 0xe5, 0xb7, 0x77, 0xb9, ++ 0x13, 0xea, 0x3b, 0x89, 0xe3, 0x01, 0x1b, 0x6a, 0x38, 0x1f, 0x51, 0xfd, ++ 0xfd, 0x43, 0xe3, 0x03, 0x9e, 0xd7, 0x5c, 0x31, 0x7e, 0xfe, 0xb3, 0x3f, ++ 0x33, 0xd3, 0xbf, 0xaf, 0xd0, 0xbb, 0xdf, 0x44, 0xf2, 0xfc, 0x4f, 0xaf, ++ 0x9a, 0x76, 0xa0, 0xde, 0x5d, 0x5e, 0xb3, 0x62, 0x4c, 0x32, 0xd4, 0xcb, ++ 0x4f, 0x9a, 0x98, 0x93, 0xcb, 0x23, 0x4d, 0x5c, 0x61, 0x69, 0x8d, 0xce, ++ 0x6b, 0x49, 0x49, 0x14, 0x47, 0xf0, 0x66, 0xd3, 0xf7, 0x43, 0xe3, 0xe3, ++ 0x05, 0x35, 0x3a, 0xe2, 0xef, 0x83, 0xf1, 0x82, 0x1a, 0xf1, 0x14, 0xd5, ++ 0x15, 0xfd, 0xfc, 0x8e, 0xf3, 0xbf, 0x4b, 0xc6, 0x4f, 0x94, 0xbe, 0x22, ++ 0x84, 0x3a, 0xd1, 0xbe, 0x78, 0xa5, 0x51, 0xf0, 0xf4, 0xb2, 0xa1, 0xf1, ++ 0x03, 0x18, 0x38, 0x9b, 0x4d, 0x81, 0x5d, 0xd4, 0x70, 0x3b, 0xc1, 0x53, ++ 0x6b, 0x26, 0xbb, 0xe0, 0x6a, 0x71, 0x85, 0xba, 0xbd, 0x27, 0xd6, 0xa1, ++ 0x9f, 0xa0, 0x8c, 0x6d, 0xee, 0xc4, 0xef, 0x51, 0x96, 0xb9, 0x74, 0x12, ++ 0x88, 0xa2, 0x04, 0x71, 0x05, 0x9e, 0xdf, 0x59, 0xae, 0xe8, 0x11, 0xf1, ++ 0xfe, 0x01, 0xc4, 0x0f, 0x94, 0xfb, 0xf1, 0x7e, 0xc1, 0xad, 0x6e, 0x6e, ++ 0x9f, 0x6f, 0x55, 0xe4, 0x7e, 0x5e, 0x09, 0x97, 0x33, 0xea, 0x38, 0xea, ++ 0x7b, 0xf1, 0xe7, 0x7e, 0xc6, 0xad, 0x8d, 0x3f, 0xc4, 0xb7, 0xbf, 0xa7, ++ 0xb4, 0x77, 0xd4, 0x94, 0x6f, 0xc0, 0x73, 0x0b, 0xce, 0xd5, 0x31, 0xe4, ++ 0xff, 0x1d, 0x35, 0x55, 0x66, 0x57, 0xcc, 0x78, 0x2f, 0xb8, 0x79, 0xde, ++ 0xcc, 0x16, 0x8c, 0x53, 0xd8, 0x63, 0xe3, 0x14, 0x3c, 0x1e, 0x11, 0x1f, ++ 0x9f, 0x50, 0xf9, 0x53, 0x45, 0xef, 0x67, 0xb3, 0xf0, 0xdc, 0x9f, 0xe8, ++ 0xe1, 0xfe, 0xa3, 0x80, 0x83, 0xfb, 0x33, 0x2b, 0x0e, 0x54, 0xd2, 0x3d, ++ 0x93, 0xe8, 0x3a, 0x39, 0x7e, 0x3e, 0xe1, 0x18, 0xbc, 0x67, 0x98, 0xca, ++ 0xf8, 0xbe, 0x98, 0x99, 0xfb, 0xb9, 0xc8, 0xaf, 0x50, 0x3e, 0xf7, 0xd3, ++ 0x3e, 0xfc, 0xf7, 0x07, 0x98, 0x2f, 0x95, 0xfe, 0x3d, 0x83, 0xc0, 0x31, ++ 0x57, 0xbb, 0x0d, 0xf9, 0xc8, 0x5c, 0x71, 0x92, 0x20, 0x93, 0x7f, 0x7b, ++ 0xd0, 0xdf, 0x8d, 0xfe, 0xa8, 0x85, 0xc7, 0x1b, 0xe6, 0x60, 0x3e, 0x70, ++ 0xc5, 0xe2, 0xb2, 0x13, 0x78, 0x2e, 0x8b, 0xeb, 0x0c, 0x94, 0x77, 0xb4, ++ 0xf0, 0x78, 0x2d, 0x7d, 0x67, 0x5c, 0x95, 0x57, 0x15, 0x8b, 0xb7, 0xaf, ++ 0xb5, 0x62, 0x7b, 0x91, 0xe0, 0xb1, 0xc8, 0xd8, 0x5e, 0x53, 0x85, 0xed, ++ 0x37, 0xbf, 0x18, 0x46, 0xcf, 0x1e, 0x9b, 0x87, 0xbb, 0x07, 0x7a, 0x89, ++ 0x1c, 0x83, 0xde, 0x79, 0xe4, 0xdf, 0xfe, 0x29, 0xda, 0x45, 0x15, 0xf3, ++ 0x15, 0xbf, 0x77, 0x1d, 0x97, 0xab, 0x8b, 0x7b, 0xe6, 0x1b, 0xf8, 0x47, ++ 0xaf, 0xb4, 0x72, 0xee, 0x60, 0xee, 0x9f, 0xc8, 0x6e, 0xbe, 0xd0, 0x53, ++ 0x41, 0xfe, 0xec, 0x74, 0x8c, 0xb7, 0xba, 0xa3, 0x72, 0xa6, 0xe2, 0x55, ++ 0x90, 0x3f, 0xc9, 0x51, 0xf9, 0xf3, 0xb7, 0xca, 0x9d, 0x33, 0x6e, 0x9e, ++ 0xe7, 0x3f, 0x01, 0xe4, 0x0f, 0xae, 0x27, 0x6d, 0x3e, 0x8f, 0x0b, 0xc6, ++ 0x9f, 0xff, 0x0b, 0x0a, 0x3e, 0x0d, 0x27, 0x4f, 0x86, 0xe3, 0x9f, 0x28, ++ 0x3f, 0x74, 0x53, 0x38, 0xbd, 0x08, 0x8e, 0xa8, 0xdc, 0x95, 0xd1, 0x9e, ++ 0xbe, 0x2e, 0x2a, 0x7f, 0xa5, 0x6e, 0xa8, 0x8f, 0x1c, 0x1e, 0xff, 0xf2, ++ 0x15, 0xbc, 0x4e, 0x1d, 0x46, 0xff, 0x1a, 0x5d, 0x2a, 0x28, 0xdf, 0x1b, ++ 0x1b, 0x26, 0x5f, 0xa3, 0xfb, 0xef, 0xe3, 0xf7, 0xce, 0x2a, 0x55, 0xf9, ++ 0xe7, 0xff, 0xe5, 0x7e, 0x6f, 0xc5, 0xbe, 0x51, 0xfd, 0xdf, 0xaa, 0x3d, ++ 0xd4, 0xa2, 0xc0, 0x59, 0x2d, 0x1f, 0x50, 0xf4, 0xd9, 0xbf, 0x39, 0x5f, ++ 0x19, 0x85, 0x62, 0xc2, 0x7c, 0xe5, 0xb4, 0xc4, 0xf9, 0xca, 0x77, 0x74, ++ 0x09, 0xf4, 0x1d, 0x16, 0x25, 0x5f, 0xf9, 0xb0, 0x91, 0x55, 0xee, 0xb1, ++ 0x63, 0x9e, 0x9e, 0x72, 0x2f, 0x21, 0xe4, 0x23, 0xfd, 0xe6, 0xf0, 0xd3, ++ 0xbf, 0x5a, 0xff, 0x9c, 0x1d, 0xef, 0x25, 0x08, 0x12, 0x8a, 0x9d, 0xc6, ++ 0xae, 0x13, 0x24, 0x9f, 0x1b, 0x41, 0x9f, 0x21, 0x3d, 0xa8, 0xe7, 0x0f, ++ 0xdc, 0x2f, 0xd5, 0xc5, 0xf3, 0x4b, 0x1b, 0xbb, 0xb5, 0xf7, 0x1f, 0xd4, ++ 0x72, 0x5b, 0x29, 0xbf, 0xaf, 0x50, 0x0d, 0xfb, 0x21, 0x3f, 0xb2, 0x92, ++ 0xc7, 0x37, 0x6b, 0x2f, 0xa7, 0xeb, 0x80, 0xd7, 0x18, 0x92, 0x9d, 0xe8, ++ 0x17, 0xfa, 0xaa, 0x18, 0xeb, 0x17, 0x0a, 0xc8, 0x91, 0x0c, 0x35, 0x3f, ++ 0x30, 0xc4, 0xe5, 0x52, 0xc2, 0x3c, 0xbe, 0x26, 0x36, 0x40, 0xf9, 0x7e, ++ 0x4d, 0x0d, 0x82, 0x07, 0xe5, 0xc1, 0x17, 0xf6, 0x13, 0x79, 0x79, 0x7e, ++ 0xdf, 0xb5, 0xfa, 0x89, 0xea, 0x4b, 0xb5, 0x7e, 0xe6, 0xb5, 0x25, 0xdc, ++ 0x2f, 0x54, 0xeb, 0x17, 0x04, 0xd4, 0x47, 0xcd, 0x3a, 0xdf, 0x4a, 0xca, ++ 0xef, 0x3d, 0x20, 0x48, 0x89, 0xf2, 0x44, 0x57, 0x2b, 0xf8, 0x7e, 0xb3, ++ 0xe2, 0xa7, 0xdd, 0x65, 0xe4, 0x78, 0xb0, 0xeb, 0x7a, 0x81, 0xf2, 0x6a, ++ 0xf1, 0x5e, 0x0c, 0x9e, 0xef, 0xae, 0x03, 0x3c, 0x7f, 0x7e, 0x57, 0x39, ++ 0xcf, 0x9f, 0x57, 0xfd, 0xb2, 0x6a, 0x5e, 0xfc, 0xb8, 0xa8, 0x5f, 0x96, ++ 0xee, 0xc3, 0xa8, 0xf9, 0xf4, 0x6a, 0x7e, 0xbc, 0x7a, 0x3f, 0x74, 0xfe, ++ 0x56, 0x6b, 0x18, 0xf5, 0x8b, 0x4d, 0x86, 0x2e, 0x07, 0xd2, 0xa1, 0x9a, ++ 0x57, 0xe4, 0x2a, 0xe5, 0x72, 0xce, 0xaa, 0x7c, 0x77, 0x3c, 0x7e, 0x9d, ++ 0xcb, 0x4a, 0x2b, 0x5d, 0xa5, 0x18, 0xa7, 0x2b, 0xd5, 0x0d, 0xe7, 0xe7, ++ 0x6a, 0x2b, 0x4d, 0xa0, 0xdf, 0xbc, 0xae, 0xc8, 0xcf, 0x75, 0xa5, 0xc3, ++ 0xea, 0xe5, 0x9d, 0xa5, 0x5a, 0xbd, 0x9c, 0xea, 0xf1, 0x7a, 0xf9, 0x7f, ++ 0x95, 0x5f, 0x76, 0xcc, 0xf0, 0x7e, 0xe1, 0x5f, 0x97, 0x5c, 0x9b, 0xdf, ++ 0xea, 0x96, 0xc4, 0x7a, 0xdc, 0x90, 0x7e, 0x95, 0xa5, 0x09, 0xc6, 0x6b, ++ 0xb7, 0x24, 0xfe, 0x8e, 0xe8, 0xef, 0x54, 0xfe, 0x1b, 0xf7, 0xef, 0x8f, ++ 0xb0, 0x21, 0xf7, 0x7b, 0xb8, 0x7c, 0xeb, 0x14, 0xe4, 0x5f, 0x4e, 0xa3, ++ 0x38, 0x97, 0x81, 0xe2, 0x5c, 0x2a, 0x7f, 0xe9, 0x4c, 0xe6, 0xe3, 0xef, ++ 0x53, 0xf8, 0x8a, 0x5a, 0x9e, 0x50, 0xc6, 0x1f, 0xee, 0x7b, 0x93, 0xef, ++ 0x2a, 0xfd, 0x5a, 0x04, 0xef, 0x0f, 0x70, 0xdd, 0x25, 0xbb, 0xb5, 0x7e, ++ 0xb2, 0xd2, 0x2e, 0xad, 0x9f, 0x6c, 0x42, 0x77, 0x9a, 0xa6, 0x5e, 0x16, ++ 0xce, 0xd2, 0xf4, 0xaf, 0x38, 0x9a, 0xa7, 0x69, 0x9f, 0x14, 0x29, 0xd6, ++ 0xb4, 0x5f, 0x77, 0xb2, 0x5c, 0x53, 0x9f, 0xda, 0x7f, 0xbd, 0xa6, 0xff, ++ 0xb4, 0x8f, 0xaa, 0x34, 0xf5, 0x1b, 0x07, 0xb4, 0x7e, 0xb2, 0xe9, 0x17, ++ 0x17, 0xc4, 0xdd, 0x3b, 0xe2, 0xf8, 0x5d, 0x09, 0x18, 0x11, 0xfb, 0xde, ++ 0x0c, 0xf3, 0x5d, 0x9a, 0x7e, 0xd9, 0x0d, 0xda, 0x7d, 0xe5, 0x36, 0x6b, ++ 0xf7, 0x35, 0xa6, 0x55, 0xbb, 0x2f, 0x75, 0x5c, 0x67, 0x50, 0xbb, 0xbf, ++ 0xfc, 0x4e, 0xed, 0xfe, 0xd2, 0xd0, 0x7f, 0xef, 0xfe, 0xe2, 0xfe, 0xfb, ++ 0xdb, 0xdd, 0x32, 0xcd, 0xd3, 0xd7, 0x93, 0x4f, 0xdf, 0x03, 0xdc, 0x52, ++ 0xe3, 0xa2, 0xef, 0x5e, 0xab, 0xf7, 0xff, 0xfe, 0x13, 0x07, 0xaf, 0xfb, ++ 0x52, 0x40, 0x6f, 0x00, 0x00, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 csem_int_table_data_e1[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x53, 0xe1, ++ 0x67, 0x60, 0xf8, 0x51, 0x0f, 0xc1, 0x5b, 0xf9, 0x18, 0x18, 0x2e, 0xf0, ++ 0x21, 0xf8, 0xf4, 0xc0, 0x1c, 0xcc, 0x0c, 0x0c, 0x9c, 0x40, 0xac, 0xc8, ++ 0xc8, 0xc0, 0x20, 0x01, 0xc4, 0xfc, 0x40, 0xcc, 0x06, 0xc4, 0x9e, 0x0c, ++ 0x0c, 0x0c, 0xff, 0x81, 0xf8, 0x1b, 0x10, 0xbf, 0x05, 0xe2, 0x27, 0x40, ++ 0xec, 0x0c, 0xc4, 0x07, 0x58, 0xb0, 0x9b, 0xe3, 0xc6, 0xca, 0xc0, 0xe0, ++ 0x01, 0xc4, 0xdc, 0x40, 0xb3, 0x78, 0x98, 0x89, 0xb7, 0xdf, 0x89, 0x17, ++ 0xc1, 0x7e, 0xcc, 0xc3, 0xc0, 0x70, 0x0e, 0x88, 0x9f, 0xf1, 0xd0, 0x37, ++ 0x0c, 0x06, 0x1b, 0x5e, 0x27, 0x40, 0x3f, 0xbb, 0x7e, 0x43, 0xed, 0x3a, ++ 0x29, 0x32, 0xf0, 0xfe, 0x06, 0x61, 0x21, 0x31, 0x60, 0x9a, 0x14, 0x47, ++ 0xf0, 0xa7, 0x8a, 0xa3, 0xca, 0x0b, 0x8b, 0x21, 0xd8, 0xc9, 0xd2, 0x94, ++ 0xd9, 0x95, 0x0f, 0xd4, 0x0f, 0x00, 0xf1, 0x93, 0x21, 0xf0, 0x80, 0x03, ++ 0x00, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 csem_pram_data_e1[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d, ++ 0x0b, 0x7c, 0x94, 0xc5, 0xb5, 0xf8, 0x7c, 0xbb, 0xdf, 0xbe, 0x92, 0xdd, ++ 0xcd, 0x26, 0xe4, 0x49, 0x00, 0x37, 0x09, 0x60, 0x50, 0x1e, 0x4b, 0x80, ++ 0xc8, 0x4b, 0xdd, 0xf0, 0x32, 0x52, 0xc4, 0x04, 0x11, 0x82, 0x8a, 0x2c, ++ 0xaf, 0x10, 0x02, 0x79, 0x14, 0xa9, 0xa5, 0xff, 0xda, 0xbb, 0x0b, 0x28, ++ 0x04, 0xaa, 0xde, 0x58, 0x51, 0xa3, 0x7f, 0x6a, 0x17, 0x04, 0x1b, 0x2d, ++ 0xda, 0x80, 0xd1, 0x1b, 0x6d, 0xe0, 0x2e, 0xa2, 0x08, 0xd5, 0x6a, 0x68, ++ 0x45, 0x51, 0xab, 0x0d, 0x88, 0x88, 0x08, 0x49, 0x8c, 0x8f, 0x6a, 0xb5, ++ 0x7a, 0xcf, 0x39, 0x33, 0xdf, 0x66, 0xe7, 0xcb, 0x2e, 0x89, 0xb6, 0xfe, ++ 0x6f, 0xff, 0xbf, 0x7b, 0xc3, 0xaf, 0x1d, 0xe7, 0x9b, 0x99, 0x33, 0x67, ++ 0xce, 0x39, 0x73, 0xe6, 0xcc, 0x99, 0x99, 0xb3, 0x26, 0x96, 0xc2, 0x0c, ++ 0x97, 0x33, 0xf6, 0x0d, 0xfe, 0x41, 0x6a, 0x33, 0x31, 0xc6, 0xc6, 0x74, ++ 0xa5, 0xed, 0x4a, 0xc7, 0x70, 0x35, 0xa7, 0xab, 0xfc, 0x36, 0xbf, 0x97, ++ 0x79, 0xcd, 0x8c, 0xd5, 0xf9, 0xad, 0x94, 0x6e, 0xf1, 0xa7, 0x33, 0xef, ++ 0x60, 0xf8, 0xee, 0x33, 0x14, 0x06, 0xed, 0x8c, 0xdd, 0xeb, 0x77, 0x51, ++ 0xfe, 0x17, 0xfe, 0x42, 0x4a, 0x6b, 0xfd, 0x45, 0x54, 0xef, 0x4e, 0x7f, ++ 0x09, 0xe5, 0x6f, 0xf7, 0xfb, 0x28, 0xdd, 0xec, 0x2f, 0xa3, 0xef, 0x35, ++ 0xfe, 0x6a, 0xca, 0x6f, 0xf0, 0xaf, 0xa1, 0x74, 0x93, 0xba, 0x28, 0x0d, ++ 0x50, 0x82, 0xbf, 0xa2, 0xc2, 0xac, 0x64, 0xc6, 0xaa, 0x9e, 0xc9, 0xc9, ++ 0xdb, 0x0c, 0xb9, 0x2d, 0xb3, 0xc6, 0x27, 0xa8, 0xa3, 0x21, 0xff, 0x8a, ++ 0x91, 0x19, 0xb3, 0x00, 0xbe, 0x4f, 0xa5, 0xfe, 0x98, 0xea, 0xde, 0x34, ++ 0x70, 0x74, 0x57, 0x3d, 0x0d, 0xcf, 0x4d, 0xea, 0xa4, 0x7e, 0x08, 0xa7, ++ 0x76, 0x09, 0xc7, 0x8b, 0x59, 0x99, 0x2d, 0x46, 0xbd, 0x2c, 0x1c, 0xe7, ++ 0x9d, 0x4b, 0x04, 0x3c, 0x7b, 0x6b, 0x4d, 0x4e, 0x72, 0xd4, 0x7a, 0x83, ++ 0x11, 0xde, 0xed, 0x25, 0x00, 0x6f, 0x28, 0x14, 0xb8, 0x42, 0xd6, 0x9c, ++ 0xe8, 0xf0, 0x2e, 0x46, 0x78, 0x9b, 0x4b, 0x54, 0x5e, 0x2f, 0x39, 0x58, ++ 0x93, 0x1d, 0x1d, 0x9e, 0x07, 0xeb, 0xd5, 0xdc, 0x20, 0xe0, 0xa5, 0x07, ++ 0xac, 0x31, 0xea, 0x8d, 0xc1, 0x7a, 0x1b, 0x6e, 0x10, 0xf8, 0xf5, 0xf3, ++ 0xd5, 0x64, 0x45, 0xef, 0x77, 0x3c, 0xd6, 0x63, 0x2e, 0xf5, 0x6f, 0xad, ++ 0x56, 0x46, 0x7f, 0xdf, 0x64, 0xe3, 0xff, 0xdb, 0x5d, 0xa7, 0x2e, 0x16, ++ 0x79, 0x23, 0x66, 0x93, 0x18, 0x1b, 0xd7, 0xd5, 0x4e, 0x9f, 0x32, 0x16, ++ 0x60, 0x38, 0x4e, 0x95, 0xf9, 0x0a, 0x89, 0x0f, 0xee, 0xcc, 0xaf, 0xbf, ++ 0xc9, 0x67, 0xec, 0x26, 0x84, 0x09, 0xed, 0x03, 0x93, 0x58, 0xc8, 0x08, ++ 0xfd, 0x07, 0x92, 0x58, 0x70, 0x7d, 0x96, 0x54, 0x7f, 0x26, 0xd5, 0x6f, ++ 0xed, 0xfb, 0xf5, 0x37, 0xa9, 0x52, 0xfd, 0x80, 0x21, 0x4a, 0x7d, 0x13, ++ 0x6b, 0x50, 0xb0, 0xfc, 0xe7, 0x28, 0x47, 0xc0, 0xf7, 0xfb, 0xfc, 0xb9, ++ 0x94, 0x6e, 0x14, 0xf2, 0x73, 0xdf, 0x50, 0x03, 0x63, 0xd8, 0x2e, 0xdd, ++ 0x1c, 0x1c, 0x04, 0xed, 0xee, 0xf1, 0x7b, 0x48, 0x5e, 0xee, 0xf6, 0x8f, ++ 0xa5, 0xf2, 0xbb, 0x84, 0x1c, 0xfe, 0xbb, 0x90, 0xb3, 0xa0, 0x90, 0xb3, ++ 0x07, 0x51, 0xce, 0x20, 0xdd, 0x8a, 0x72, 0x66, 0xc6, 0xfe, 0x7c, 0xad, ++ 0xa5, 0x00, 0xa7, 0x7d, 0x6f, 0x3c, 0xdb, 0xec, 0x26, 0xf9, 0x5a, 0x4c, ++ 0x78, 0xaa, 0x8c, 0xe0, 0x6f, 0xd8, 0x3b, 0x64, 0xfb, 0x66, 0x80, 0x7f, ++ 0xdf, 0x0d, 0xab, 0x4e, 0x6f, 0x03, 0xfa, 0xb7, 0x35, 0x0f, 0xf3, 0x18, ++ 0xa1, 0xde, 0x3d, 0x43, 0x35, 0xf9, 0x62, 0x5e, 0x96, 0xdc, 0x55, 0xef, ++ 0x9e, 0xd9, 0x27, 0x9c, 0x8b, 0x86, 0x12, 0xbd, 0xcb, 0x10, 0xce, 0xdd, ++ 0x1e, 0xc1, 0x3f, 0x15, 0x06, 0x16, 0x51, 0xef, 0xee, 0x19, 0xe1, 0x7a, ++ 0x15, 0x58, 0xef, 0x2e, 0x4f, 0x18, 0x5e, 0x28, 0xb2, 0xdf, 0xbb, 0xa6, ++ 0x84, 0xeb, 0xad, 0x22, 0x3e, 0x2b, 0xac, 0xa4, 0xc1, 0xde, 0x9d, 0x2f, ++ 0x3b, 0x98, 0x42, 0xf3, 0x11, 0x04, 0x85, 0xe8, 0x6b, 0x42, 0xfa, 0xc2, ++ 0xbc, 0x7c, 0x76, 0xc0, 0x75, 0x4a, 0x2b, 0xb4, 0x4f, 0x49, 0xce, 0x4b, ++ 0x63, 0xd0, 0xee, 0x7e, 0x9c, 0x8f, 0x66, 0x9c, 0x77, 0x6e, 0xa2, 0x8b, ++ 0xd6, 0x1e, 0xe9, 0xec, 0x83, 0xef, 0x19, 0x16, 0x56, 0x8d, 0xf0, 0x81, ++ 0xb2, 0xfb, 0x8d, 0x80, 0xaf, 0x69, 0xb6, 0x3b, 0x11, 0xe9, 0x72, 0xfb, ++ 0xb5, 0x45, 0x4c, 0x19, 0xc6, 0x58, 0x5f, 0x51, 0x9e, 0x1a, 0x28, 0x52, ++ 0xb2, 0x00, 0xae, 0x7d, 0x4e, 0x91, 0x82, 0xdf, 0x4d, 0xb3, 0xa1, 0x1c, ++ 0xbe, 0xbb, 0x44, 0x79, 0xf2, 0x1a, 0x5e, 0x7e, 0x3b, 0x96, 0x3b, 0xba, ++ 0xca, 0x13, 0xb1, 0x1c, 0xbe, 0x27, 0x55, 0x43, 0x39, 0xe4, 0xed, 0x73, ++ 0x79, 0xf9, 0x1d, 0x7e, 0xe0, 0xc4, 0xe0, 0xae, 0x7a, 0x9b, 0x80, 0xcf, ++ 0x3e, 0xe2, 0x77, 0x3a, 0xff, 0x0e, 0x6c, 0x45, 0xfa, 0x98, 0x46, 0xf3, ++ 0x54, 0xc3, 0xfb, 0x09, 0x14, 0x12, 0xa0, 0xdf, 0x41, 0x4c, 0xc7, 0x74, ++ 0xe1, 0xbf, 0x69, 0xd0, 0xbd, 0x19, 0x0b, 0xed, 0x5d, 0xf8, 0xda, 0x06, ++ 0xd7, 0x53, 0x5e, 0xc3, 0x6f, 0xd3, 0xe0, 0x38, 0xca, 0x6b, 0xf8, 0xd8, ++ 0x2e, 0xec, 0x97, 0xb1, 0x10, 0xd2, 0xbe, 0x4b, 0xfa, 0x32, 0x6f, 0xae, ++ 0x98, 0x0f, 0xac, 0x3b, 0x9d, 0x13, 0xbd, 0xd9, 0x52, 0x79, 0xa6, 0xea, ++ 0x49, 0x50, 0x81, 0x4e, 0x99, 0x2f, 0x19, 0x59, 0x00, 0x58, 0x90, 0x09, ++ 0xe2, 0x89, 0xf0, 0xf4, 0xed, 0x8a, 0x98, 0x81, 0xf0, 0xec, 0x71, 0xfe, ++ 0x25, 0xf7, 0x6e, 0xfe, 0x99, 0x86, 0xca, 0x74, 0xd0, 0xd2, 0xa3, 0x82, ++ 0x1e, 0x1a, 0x1d, 0x36, 0xf6, 0x97, 0xe9, 0x60, 0x19, 0x20, 0xd3, 0x61, ++ 0xe3, 0x00, 0x99, 0x0e, 0x96, 0x0b, 0xce, 0x4f, 0x87, 0x1d, 0xcc, 0x4d, ++ 0x74, 0x8e, 0x45, 0x0f, 0xad, 0xdf, 0xcd, 0x43, 0xe4, 0x7e, 0xe3, 0x2e, ++ 0x92, 0xfb, 0xdd, 0x7c, 0x91, 0xdc, 0x6f, 0xdc, 0xc5, 0xff, 0x9c, 0x7e, ++ 0x6b, 0xb2, 0xe4, 0x7e, 0xad, 0xd9, 0x72, 0xbf, 0x35, 0xd9, 0x72, 0xbf, ++ 0xd6, 0x9c, 0x7f, 0xac, 0x5f, 0xa6, 0x7a, 0x60, 0x32, 0xa0, 0xbe, 0xd2, ++ 0xfe, 0x2e, 0x94, 0xf4, 0xdb, 0xd5, 0xcc, 0x77, 0x16, 0xdb, 0xa3, 0x9e, ++ 0xc3, 0xf9, 0xa4, 0xe9, 0x39, 0x53, 0xb2, 0x8f, 0xf9, 0xec, 0x5d, 0xfc, ++ 0x84, 0x75, 0x8a, 0xb1, 0xfc, 0x48, 0x38, 0x83, 0x25, 0xbd, 0x0a, 0x70, ++ 0x3e, 0xc5, 0x7a, 0x00, 0xc7, 0x7b, 0x7e, 0x38, 0x2e, 0x1d, 0x9c, 0x41, ++ 0x7a, 0x38, 0x5f, 0x0b, 0x7c, 0x58, 0xa4, 0x9e, 0xee, 0x06, 0x87, 0x0d, ++ 0xd4, 0x8f, 0xc3, 0xa4, 0xf0, 0x76, 0x21, 0x43, 0x44, 0xff, 0x4c, 0xf5, ++ 0xb1, 0x22, 0x47, 0x64, 0x3b, 0x8f, 0xae, 0xff, 0x1c, 0x7d, 0xff, 0x4e, ++ 0x45, 0x8c, 0xc3, 0x70, 0xde, 0xfe, 0xdd, 0x3a, 0xba, 0x66, 0xeb, 0xf1, ++ 0x49, 0x13, 0xf8, 0x30, 0xc3, 0xf9, 0xe8, 0xc1, 0x5c, 0x3a, 0x38, 0x59, ++ 0x7a, 0x38, 0x6e, 0x81, 0x4f, 0x48, 0x39, 0x2f, 0x1c, 0xb7, 0x7e, 0x1c, ++ 0x17, 0x8a, 0xfe, 0x03, 0x8a, 0xb4, 0x7e, 0x01, 0x3d, 0x86, 0x75, 0xb5, ++ 0x6b, 0x07, 0xfc, 0x68, 0x9d, 0xca, 0xb3, 0x04, 0x77, 0x82, 0x7e, 0x08, ++ 0xed, 0xfb, 0xf2, 0x14, 0xae, 0x03, 0xe7, 0x1a, 0xaf, 0x75, 0x5b, 0xa0, ++ 0xfe, 0xfe, 0x91, 0x96, 0xd0, 0xe5, 0x50, 0x7e, 0x2e, 0x58, 0x10, 0xb4, ++ 0x40, 0xf9, 0xe4, 0x27, 0x8f, 0x3a, 0xd1, 0x8e, 0xa9, 0x78, 0xd2, 0xa8, ++ 0x62, 0xb9, 0x61, 0x9f, 0x8d, 0xd6, 0x97, 0xb6, 0x1d, 0x0a, 0x95, 0x57, ++ 0x59, 0x5a, 0xee, 0x9c, 0x00, 0xe5, 0x1d, 0x4f, 0x1a, 0xd9, 0x76, 0xea, ++ 0x2e, 0xd3, 0x80, 0xe3, 0x3b, 0x25, 0x74, 0x0a, 0x0b, 0xf1, 0x7c, 0xa9, ++ 0x8d, 0x67, 0x2b, 0xb6, 0xed, 0xbf, 0x11, 0xdb, 0x97, 0x35, 0x59, 0x98, ++ 0x0d, 0xe0, 0x55, 0x3c, 0xbd, 0x6c, 0xe6, 0x04, 0xc8, 0x2f, 0x3b, 0x64, ++ 0x62, 0x58, 0xa5, 0x62, 0xe7, 0x5a, 0x73, 0x5f, 0xc8, 0x2f, 0x0f, 0x2a, ++ 0x0d, 0x98, 0x07, 0x7c, 0x69, 0x9d, 0x0a, 0xe4, 0xd9, 0x82, 0x3b, 0xa1, ++ 0xfe, 0xba, 0x7d, 0x5f, 0xb6, 0x21, 0xfe, 0xe7, 0x1a, 0x4d, 0x83, 0x10, ++ 0x9f, 0x33, 0xb0, 0x4e, 0xb8, 0x61, 0x9d, 0x78, 0xc9, 0xd1, 0x92, 0x3a, ++ 0x1b, 0xe8, 0x53, 0x1e, 0xdc, 0x3d, 0x0d, 0xdb, 0x97, 0xef, 0x52, 0x3c, ++ 0xa0, 0xe1, 0x00, 0xff, 0x9d, 0x07, 0x33, 0x10, 0xff, 0x47, 0x14, 0x8f, ++ 0x05, 0x58, 0xb8, 0xa2, 0x3e, 0x9e, 0xb9, 0x23, 0xe6, 0xcb, 0xa9, 0x46, ++ 0x23, 0x8d, 0x77, 0xd5, 0x36, 0x25, 0xc8, 0x00, 0xde, 0x32, 0x56, 0x3b, ++ 0x0d, 0xe9, 0x59, 0x81, 0xc4, 0x41, 0x3c, 0x3c, 0x96, 0xa0, 0x4d, 0xe9, ++ 0x9a, 0x6f, 0x67, 0xfc, 0x75, 0xd4, 0x9f, 0x96, 0xaf, 0x78, 0x04, 0xfa, ++ 0x83, 0xf6, 0x95, 0x8f, 0x2b, 0x1e, 0x1c, 0x72, 0xa5, 0x81, 0xf9, 0x70, ++ 0x1e, 0xb7, 0x3d, 0x6d, 0x2b, 0x79, 0xc8, 0x8e, 0xe3, 0x5d, 0x6b, 0x1e, ++ 0xec, 0xc0, 0x71, 0x6e, 0x34, 0x63, 0xbd, 0x65, 0xc1, 0x85, 0x4f, 0xd9, ++ 0xdc, 0x88, 0xe7, 0x36, 0xf3, 0x34, 0xc4, 0x77, 0xeb, 0x36, 0x73, 0xe9, ++ 0x50, 0xa4, 0x23, 0x5b, 0x50, 0x34, 0x14, 0xf1, 0xfb, 0xbf, 0x32, 0x7e, ++ 0x75, 0x46, 0x2f, 0x8e, 0x77, 0xd5, 0x48, 0xcb, 0x76, 0x23, 0xe0, 0xc1, ++ 0xec, 0xa1, 0x81, 0xb3, 0x1c, 0xdd, 0xf5, 0xec, 0x19, 0x58, 0xaf, 0xdc, ++ 0x11, 0xeb, 0x67, 0x39, 0x03, 0xbd, 0x4f, 0xeb, 0x77, 0xd0, 0x5c, 0x3c, ++ 0xac, 0xeb, 0xfb, 0x97, 0x86, 0x44, 0xd2, 0x1f, 0x2b, 0xea, 0x8d, 0xcc, ++ 0x6d, 0xed, 0xea, 0x47, 0x93, 0x8f, 0xc0, 0x11, 0x21, 0x1f, 0x7b, 0x1d, ++ 0x44, 0x6f, 0x8d, 0x9f, 0xab, 0x5c, 0x7c, 0x0a, 0x68, 0xfc, 0x5c, 0x95, ++ 0x28, 0xf8, 0xab, 0x76, 0xe4, 0xcf, 0x1a, 0xd6, 0x1d, 0x9f, 0x3b, 0x91, ++ 0x2f, 0x64, 0x4f, 0xbb, 0x28, 0xfd, 0x05, 0xac, 0x9b, 0x98, 0x6e, 0x81, ++ 0x75, 0x1e, 0xe9, 0x77, 0x2f, 0xd8, 0x4f, 0x6e, 0xb2, 0xcb, 0x3d, 0xf4, ++ 0xfd, 0x01, 0xb0, 0x93, 0x30, 0xdd, 0x0a, 0x76, 0x12, 0xa6, 0x0f, 0x82, ++ 0x9d, 0xe4, 0x16, 0x76, 0x12, 0xd6, 0xdb, 0x0e, 0x76, 0x12, 0xa6, 0x3b, ++ 0xc0, 0x4e, 0xc2, 0xef, 0x0f, 0x83, 0x3d, 0x8e, 0x69, 0x3d, 0xd8, 0xe3, ++ 0xf8, 0xfd, 0x51, 0xb0, 0xc7, 0x31, 0xdd, 0xe5, 0x0f, 0xd0, 0xf7, 0xc7, ++ 0xfd, 0x35, 0x94, 0x36, 0xf8, 0x6b, 0x29, 0xdd, 0x83, 0x7c, 0x83, 0xb4, ++ 0xd1, 0x1f, 0xa4, 0x7a, 0x4f, 0xf9, 0xeb, 0x29, 0x6d, 0xf2, 0x37, 0xd0, ++ 0xf7, 0x67, 0xfc, 0x4d, 0x94, 0xde, 0x2e, 0xe8, 0xe8, 0x9c, 0xc8, 0x0a, ++ 0x70, 0x1d, 0x75, 0x7a, 0x99, 0x0b, 0xc9, 0x9e, 0x34, 0xc3, 0x5b, 0x60, ++ 0x82, 0x7c, 0x52, 0x11, 0xcf, 0xa7, 0xde, 0x10, 0x28, 0x30, 0x43, 0x3e, ++ 0xd5, 0x07, 0x79, 0xa0, 0x4b, 0xdf, 0x95, 0xa1, 0x02, 0x0b, 0xe4, 0xfb, ++ 0x56, 0xf3, 0xf2, 0x01, 0xb7, 0xb0, 0x49, 0x56, 0xc8, 0x0f, 0x08, 0xf0, ++ 0xf2, 0xec, 0xdb, 0xbd, 0x93, 0x6c, 0x90, 0xcf, 0xae, 0xe5, 0xe5, 0x83, ++ 0xb7, 0x06, 0x26, 0xc5, 0x41, 0x7e, 0x70, 0x90, 0x97, 0x5f, 0xb4, 0x2b, ++ 0x34, 0x29, 0x1e, 0xf2, 0x17, 0x35, 0xf0, 0xf2, 0xe1, 0xcd, 0x6c, 0xb2, ++ 0x1d, 0xf2, 0xc3, 0x43, 0x3c, 0x9f, 0xf7, 0x92, 0x77, 0xb2, 0x03, 0xf2, ++ 0x79, 0x2d, 0x3c, 0x9f, 0xff, 0xe7, 0xc0, 0x64, 0x27, 0xe4, 0xf3, 0x5b, ++ 0x79, 0xfb, 0xf1, 0x67, 0x83, 0x46, 0x77, 0x94, 0xf5, 0x77, 0x8f, 0xc9, ++ 0xbd, 0x18, 0x55, 0xce, 0x01, 0xe5, 0x6d, 0xaf, 0x9a, 0x01, 0x79, 0xb3, ++ 0xfb, 0x26, 0x54, 0x89, 0x47, 0x95, 0x53, 0x94, 0x6f, 0x34, 0x79, 0xa9, ++ 0xfc, 0x7d, 0xa5, 0xdd, 0xab, 0xc2, 0x3a, 0xdf, 0x68, 0xf6, 0x52, 0xf9, ++ 0x17, 0xca, 0xe7, 0x94, 0x7f, 0xca, 0xe4, 0xa3, 0xf2, 0x78, 0x83, 0x52, ++ 0x40, 0x79, 0xb3, 0x8f, 0xca, 0xfb, 0x1b, 0xe2, 0x28, 0xdf, 0x64, 0x0a, ++ 0x50, 0xf9, 0x08, 0x43, 0x1f, 0x9e, 0x37, 0x07, 0xa8, 0xbc, 0xc0, 0xd0, ++ 0xaf, 0x00, 0xe1, 0x3f, 0x63, 0x0a, 0x52, 0xf9, 0x35, 0x86, 0x41, 0x3c, ++ 0x6f, 0x0e, 0x52, 0xf9, 0x2f, 0xd4, 0xe1, 0x05, 0x53, 0xa0, 0xfe, 0xe3, ++ 0x06, 0xdf, 0x5e, 0xd4, 0x77, 0xeb, 0x15, 0x5f, 0x19, 0xda, 0x87, 0x4c, ++ 0x6d, 0x48, 0x47, 0x7d, 0xa5, 0xd9, 0x95, 0x3b, 0x71, 0x70, 0x68, 0x67, ++ 0x66, 0x98, 0x69, 0x1e, 0xec, 0xf9, 0x43, 0xfe, 0x43, 0x34, 0x0f, 0xf0, ++ 0x2f, 0x19, 0xf3, 0xa5, 0x0f, 0xa3, 0x5d, 0x0a, 0x70, 0x0e, 0x12, 0x1c, ++ 0x13, 0xc0, 0x31, 0xf6, 0x0c, 0x27, 0xef, 0xe5, 0xb1, 0x12, 0x9c, 0xbc, ++ 0x97, 0xcb, 0x34, 0x38, 0xaf, 0x10, 0x1c, 0x5b, 0xef, 0xe0, 0xec, 0x79, ++ 0x79, 0xbc, 0x8c, 0xcf, 0xcb, 0xe5, 0x1a, 0x9c, 0x63, 0x04, 0xc7, 0xd1, ++ 0xbb, 0x71, 0xe5, 0xbd, 0x32, 0x51, 0xc6, 0xe7, 0x95, 0x95, 0x1a, 0x9c, ++ 0xe3, 0x04, 0x27, 0xb1, 0x77, 0xf8, 0x34, 0x1e, 0x95, 0xe9, 0xd3, 0x78, ++ 0x34, 0x4c, 0x9f, 0x33, 0xb8, 0x3e, 0xac, 0x4f, 0xe9, 0x1d, 0x3e, 0xa3, ++ 0x5f, 0x93, 0xe9, 0x33, 0xfa, 0xb5, 0x30, 0x7d, 0x3e, 0x26, 0x7c, 0x32, ++ 0x7a, 0x07, 0xa7, 0xf1, 0x35, 0x99, 0x3e, 0x8d, 0xaf, 0x85, 0xe9, 0xf3, ++ 0x15, 0xc1, 0xe9, 0xdf, 0xbb, 0x71, 0x8d, 0x7e, 0x5d, 0xa6, 0xcf, 0xe8, ++ 0xd7, 0xc3, 0xf4, 0x31, 0x19, 0x10, 0x4e, 0x56, 0xef, 0xe0, 0x3c, 0xf5, ++ 0xb6, 0x4c, 0x9f, 0xa7, 0xde, 0x0e, 0xd3, 0xc7, 0x69, 0x40, 0xfa, 0x0c, ++ 0xea, 0xdd, 0xb8, 0xf2, 0xdf, 0x91, 0xe9, 0x93, 0xff, 0x4e, 0x98, 0x3e, ++ 0x69, 0x84, 0xcf, 0x90, 0xde, 0xc1, 0x79, 0xea, 0x1d, 0x99, 0x3e, 0x4f, ++ 0xbd, 0x13, 0xa6, 0x8f, 0x9b, 0xf0, 0x19, 0xd6, 0xbb, 0x71, 0xe5, 0xff, ++ 0x45, 0xa6, 0x4f, 0xfe, 0x5f, 0xc2, 0xf4, 0x19, 0x42, 0x70, 0x46, 0xf6, ++ 0x0e, 0x9f, 0xa6, 0xf7, 0x64, 0xfa, 0x34, 0xbd, 0x17, 0xa6, 0x4f, 0x1e, ++ 0xc1, 0x19, 0xd3, 0x3b, 0x7c, 0xc6, 0x9e, 0x92, 0xe9, 0x33, 0xf6, 0x54, ++ 0x98, 0x3e, 0x13, 0x08, 0xce, 0xb8, 0xde, 0xc1, 0x69, 0x3a, 0x25, 0xd3, ++ 0xa7, 0xe9, 0x54, 0x98, 0x3e, 0x53, 0x88, 0xce, 0x97, 0xf6, 0x6e, 0x5c, ++ 0x63, 0xdf, 0x97, 0xe9, 0x33, 0xf6, 0xfd, 0x30, 0x7d, 0xae, 0x22, 0x38, ++ 0x05, 0xbe, 0x7a, 0xc2, 0x87, 0x01, 0x1c, 0x47, 0x6c, 0x38, 0xcf, 0x9c, ++ 0x93, 0xe9, 0xf3, 0xcc, 0xb9, 0x30, 0x7d, 0xe6, 0x10, 0x9c, 0xa9, 0x00, ++ 0x27, 0xa7, 0x67, 0x38, 0xe3, 0xdb, 0x64, 0xfa, 0x8c, 0x6f, 0x0b, 0xd3, ++ 0x67, 0x01, 0xc1, 0xb9, 0xb2, 0x77, 0x70, 0x9e, 0x69, 0x93, 0xe9, 0xf3, ++ 0x4c, 0x5b, 0x98, 0x3e, 0x65, 0x44, 0xe7, 0xab, 0x7a, 0x37, 0xae, 0xf1, ++ 0xed, 0x32, 0x7d, 0xc6, 0xb7, 0x73, 0xfa, 0x54, 0x59, 0x3c, 0x93, 0x1d, ++ 0x68, 0xdf, 0x25, 0x32, 0xcf, 0x76, 0x68, 0x72, 0xc9, 0xc9, 0x86, 0x03, ++ 0x4e, 0xc8, 0x9b, 0xec, 0xcc, 0x83, 0x60, 0x5f, 0x52, 0x42, 0x3b, 0x10, ++ 0x3e, 0xac, 0x95, 0x64, 0x17, 0xaa, 0x1e, 0xcd, 0x4e, 0xf1, 0x30, 0xb4, ++ 0x43, 0x67, 0x38, 0xdd, 0x1e, 0xf4, 0xfb, 0x18, 0x35, 0x7b, 0x84, 0xb5, ++ 0xd0, 0x7e, 0xc1, 0xbe, 0x2b, 0x51, 0xf2, 0x07, 0x7d, 0x69, 0x98, 0x74, ++ 0x0b, 0xe2, 0xeb, 0x00, 0xab, 0x2d, 0xd2, 0x2e, 0x49, 0x18, 0x1b, 0x27, ++ 0xd9, 0x43, 0x89, 0xde, 0x24, 0x29, 0xdf, 0xa7, 0xb0, 0xaf, 0x54, 0x3f, ++ 0xa5, 0x28, 0x5b, 0x2a, 0x4f, 0x2b, 0xb9, 0x48, 0x2a, 0xcf, 0xf0, 0xe5, ++ 0x49, 0xf9, 0xcc, 0xb2, 0xf1, 0x52, 0xfd, 0xfe, 0xd5, 0x93, 0xa4, 0xfc, ++ 0x05, 0x6b, 0xa6, 0x4b, 0xf5, 0xb3, 0x02, 0xb3, 0xa4, 0x7c, 0x4e, 0xcd, ++ 0x75, 0x52, 0xfd, 0x41, 0xb5, 0x8b, 0xa4, 0xf2, 0x0b, 0xeb, 0xca, 0xa5, ++ 0xf2, 0x21, 0xc1, 0x55, 0x52, 0xfe, 0xe2, 0xfa, 0xff, 0x23, 0xd5, 0x1f, ++ 0xd6, 0xb0, 0x4e, 0x2a, 0x1f, 0xd1, 0xb4, 0x59, 0x2a, 0x1f, 0x19, 0xfa, ++ 0x85, 0x94, 0x1f, 0x75, 0xe8, 0x01, 0xa9, 0xfe, 0x98, 0x96, 0xed, 0x52, ++ 0xf9, 0x25, 0xc7, 0x1e, 0x95, 0xca, 0xc7, 0xb5, 0xee, 0x91, 0xf2, 0x13, ++ 0x4e, 0x3f, 0xa3, 0xb3, 0x03, 0xe5, 0xfd, 0xff, 0xfa, 0x02, 0xc6, 0xed, ++ 0xc1, 0x0c, 0x33, 0xd9, 0x83, 0x21, 0x87, 0x99, 0xf2, 0xe6, 0x7d, 0x36, ++ 0xb2, 0xff, 0xf7, 0x63, 0x1e, 0xf8, 0x69, 0xee, 0x3b, 0x83, 0xf2, 0xe6, ++ 0x67, 0x17, 0xbb, 0x93, 0x71, 0x3f, 0x8d, 0x00, 0x60, 0xbd, 0x2f, 0xe8, ++ 0x5b, 0x76, 0x21, 0xfa, 0x7b, 0x6e, 0x1e, 0xef, 0xbb, 0xd0, 0x05, 0xdf, ++ 0x6f, 0x36, 0xfb, 0x46, 0xb8, 0xa2, 0xf8, 0x23, 0x3c, 0xaa, 0x6f, 0x9f, ++ 0x81, 0xfc, 0x45, 0x2d, 0x0a, 0x4b, 0xc7, 0xd4, 0x6d, 0xc0, 0x34, 0xce, ++ 0x28, 0xf6, 0xeb, 0x16, 0x2e, 0x5f, 0x1b, 0xb3, 0xf2, 0x1f, 0x0a, 0x44, ++ 0xc8, 0x69, 0x4d, 0x7f, 0x98, 0x7f, 0x90, 0x3f, 0x6c, 0x30, 0x93, 0xfd, ++ 0xaa, 0xc9, 0xf7, 0xc6, 0xfe, 0xa5, 0xe9, 0x0b, 0x23, 0xfa, 0xd9, 0xd0, ++ 0xdf, 0x5c, 0xb2, 0x7d, 0x28, 0xff, 0xbe, 0xd8, 0x8e, 0xfd, 0x15, 0xbd, ++ 0x88, 0xf3, 0xac, 0xca, 0xdc, 0x31, 0x18, 0xf1, 0xd2, 0xf7, 0x63, 0xc9, ++ 0x1e, 0x2b, 0xf5, 0x63, 0x1d, 0x50, 0x46, 0xfd, 0xbc, 0x86, 0xfd, 0x44, ++ 0xf8, 0xbd, 0x2c, 0x03, 0xca, 0x74, 0xfd, 0x58, 0x4b, 0xb6, 0x8b, 0xef, ++ 0xa2, 0x9f, 0x63, 0x38, 0xae, 0x58, 0xfd, 0x6c, 0xcc, 0x1e, 0x2f, 0x8f, ++ 0x67, 0x40, 0x39, 0xf5, 0xf3, 0xae, 0xae, 0x9f, 0x8d, 0x03, 0xca, 0x75, ++ 0xfd, 0xc4, 0xf1, 0xf1, 0xc0, 0x77, 0xd1, 0xcf, 0x7b, 0xe7, 0x1d, 0x4f, ++ 0xce, 0x44, 0x79, 0x3c, 0x17, 0xac, 0xa4, 0x7e, 0x3a, 0x74, 0x74, 0xb3, ++ 0x5c, 0xb0, 0x52, 0xd7, 0x8f, 0x9d, 0xfa, 0xc1, 0xef, 0x8b, 0xc9, 0x9f, ++ 0x0b, 0xbb, 0x80, 0x34, 0xe0, 0xb3, 0xa5, 0xa3, 0x94, 0xe4, 0xe0, 0x3f, ++ 0x6d, 0x2c, 0x00, 0x72, 0x61, 0xce, 0x2c, 0xff, 0x35, 0xe6, 0xd9, 0x5b, ++ 0x36, 0x36, 0x08, 0xfb, 0x71, 0x43, 0xbf, 0x50, 0x8f, 0xe5, 0x72, 0xff, ++ 0xd1, 0xd3, 0x86, 0x24, 0x1a, 0xcf, 0x67, 0x71, 0xc0, 0xff, 0x08, 0x3b, ++ 0xb5, 0x6b, 0x3f, 0x1b, 0xa0, 0x7d, 0xf1, 0x52, 0x81, 0x22, 0x0b, 0x02, ++ 0x46, 0xb0, 0xbf, 0xad, 0x14, 0xb2, 0xb9, 0x64, 0x57, 0xf1, 0x80, 0x9b, ++ 0xdc, 0x90, 0x36, 0x1d, 0x18, 0x78, 0x37, 0xf6, 0xb3, 0xc5, 0xe1, 0x19, ++ 0x04, 0xf9, 0xb6, 0xa6, 0xc9, 0xe6, 0xc5, 0x51, 0xe4, 0x69, 0x69, 0xad, ++ 0xe9, 0x54, 0x6b, 0xa4, 0x5f, 0x44, 0xdb, 0xdf, 0x4c, 0x62, 0xb9, 0xd5, ++ 0xd0, 0xff, 0x2e, 0x9b, 0x4b, 0xca, 0x6b, 0xe9, 0x4a, 0xc5, 0xc5, 0x84, ++ 0x3f, 0x82, 0xf2, 0x27, 0x60, 0xdf, 0xc2, 0x60, 0x3f, 0xf0, 0x67, 0xd8, ++ 0x17, 0x30, 0x20, 0xd5, 0xbb, 0x26, 0xbe, 0x4f, 0x7b, 0x07, 0xf6, 0x37, ++ 0x98, 0x6f, 0x85, 0xfd, 0x0d, 0x96, 0x33, 0xb6, 0x96, 0xda, 0x9d, 0x10, ++ 0x7e, 0xda, 0x13, 0xb7, 0x2b, 0x41, 0xa4, 0xf7, 0x67, 0x3f, 0xf9, 0xa1, ++ 0x89, 0xf4, 0x78, 0x80, 0xbd, 0x9a, 0x9e, 0x8a, 0x7e, 0x37, 0xfe, 0xb7, ++ 0x60, 0x4d, 0x3c, 0xfa, 0xf8, 0xc3, 0xf8, 0x2d, 0x0c, 0xf4, 0x91, 0xf2, ++ 0xa0, 0x2e, 0x33, 0x0d, 0xe9, 0xb4, 0x2f, 0xa4, 0xfd, 0x6f, 0xc7, 0xd3, ++ 0x96, 0xe0, 0x76, 0xa4, 0x6b, 0x4d, 0x26, 0xd0, 0x54, 0xd4, 0xcb, 0x66, ++ 0xec, 0x75, 0xd8, 0xe4, 0x66, 0x24, 0x51, 0x36, 0xd3, 0x30, 0x96, 0xb1, ++ 0xd9, 0xd5, 0xc5, 0x53, 0xd3, 0x68, 0x16, 0x29, 0xfd, 0x57, 0x01, 0x9e, ++ 0xb3, 0x1a, 0x47, 0x9a, 0xa0, 0x05, 0x6b, 0x33, 0xb5, 0xde, 0xe8, 0xb1, ++ 0x77, 0xc1, 0x65, 0x5e, 0xd3, 0x09, 0xa4, 0x8f, 0x15, 0xfe, 0x21, 0x9c, ++ 0x6b, 0x0a, 0x21, 0x1f, 0xd1, 0xff, 0xb5, 0x45, 0x72, 0x7e, 0x2e, 0x53, ++ 0xbb, 0xf2, 0xc0, 0xef, 0xc1, 0xc6, 0x6c, 0xc1, 0x37, 0xd1, 0xaf, 0xdb, ++ 0x6b, 0x42, 0xbe, 0x16, 0xa5, 0x72, 0x7c, 0xe6, 0x62, 0x9a, 0x87, 0xc5, ++ 0xdc, 0xdf, 0x51, 0xe2, 0xe2, 0x6d, 0x35, 0x7c, 0xaa, 0x16, 0x9b, 0x58, ++ 0x88, 0xf6, 0xa7, 0x81, 0x14, 0x86, 0xfe, 0xe8, 0x40, 0x32, 0xd5, 0xbb, ++ 0x4e, 0xdb, 0x67, 0xea, 0xf0, 0x2b, 0x31, 0x59, 0xbd, 0x45, 0x40, 0xd7, ++ 0x92, 0x85, 0x46, 0xa2, 0xab, 0x1e, 0xdf, 0x37, 0xf7, 0xc5, 0x7b, 0x0d, ++ 0xc3, 0x21, 0xad, 0xb9, 0xdb, 0x84, 0xae, 0xcd, 0x9e, 0xf0, 0x9f, 0xe7, ++ 0x93, 0xcb, 0x59, 0x19, 0xef, 0x4f, 0xa3, 0xab, 0x26, 0x2f, 0xa7, 0x04, ++ 0x7f, 0x4f, 0x20, 0xff, 0x21, 0x7d, 0x1f, 0xf9, 0x0f, 0x78, 0x9f, 0x14, ++ 0xfc, 0xef, 0x92, 0x63, 0xce, 0xff, 0x2a, 0x8b, 0x6f, 0x26, 0xf2, 0xbf, ++ 0xe3, 0x7e, 0x23, 0x23, 0x7e, 0x09, 0xbe, 0xcf, 0x11, 0x7c, 0x5f, 0x5a, ++ 0x2b, 0xf3, 0x7d, 0x0e, 0xfa, 0xc9, 0xa1, 0xfe, 0x9c, 0xd5, 0x59, 0xc1, ++ 0xf5, 0x58, 0xbf, 0xae, 0x8f, 0xc4, 0x5f, 0x18, 0xb8, 0x4c, 0x87, 0xda, ++ 0xbb, 0xa6, 0x82, 0x5a, 0xed, 0x86, 0xff, 0xdb, 0x42, 0x0e, 0xae, 0xab, ++ 0xd9, 0xfd, 0x3c, 0xb2, 0xf7, 0xfa, 0x32, 0xdd, 0xf8, 0x04, 0x1f, 0x6e, ++ 0x14, 0x7c, 0x98, 0xaf, 0xa3, 0xc7, 0x1c, 0xc1, 0xb7, 0xf9, 0x82, 0x6f, ++ 0xcb, 0x58, 0xe0, 0xb6, 0x0c, 0xf2, 0x1f, 0x05, 0x4d, 0xe8, 0x17, 0x9b, ++ 0x57, 0xa6, 0x30, 0xd4, 0x17, 0x55, 0x3f, 0xd5, 0xf8, 0xd6, 0x2a, 0xf1, ++ 0xcd, 0xa7, 0xf1, 0x4d, 0x87, 0xef, 0x8d, 0x82, 0x6f, 0x37, 0xfe, 0x84, ++ 0xf3, 0x4d, 0x8f, 0x77, 0xab, 0xe0, 0x5b, 0x6b, 0xdd, 0xc7, 0x26, 0x96, ++ 0xdd, 0x1d, 0x6f, 0x3d, 0x9e, 0x0b, 0xd6, 0xe8, 0xc6, 0x15, 0xd0, 0xf3, ++ 0xad, 0x56, 0x9c, 0x3b, 0xb8, 0xcc, 0x68, 0xef, 0x14, 0x7b, 0x0b, 0xfa, ++ 0x9c, 0x8c, 0xa8, 0x7f, 0x4d, 0xe1, 0x95, 0x7d, 0x4e, 0x46, 0xe8, 0x85, ++ 0x6b, 0x8b, 0x8a, 0xa5, 0xfc, 0xdc, 0x92, 0x79, 0x52, 0xfd, 0x79, 0xbe, ++ 0x85, 0x52, 0xf9, 0xf5, 0x65, 0xcb, 0xa5, 0xf2, 0xf9, 0xd5, 0x3f, 0x94, ++ 0xf2, 0x0b, 0xd6, 0xfc, 0x44, 0xaa, 0xbf, 0x30, 0xb0, 0x56, 0x2a, 0x5f, ++ 0x5c, 0xb3, 0x49, 0x2a, 0x5f, 0x5a, 0x7b, 0x97, 0x94, 0x5f, 0x56, 0x77, ++ 0xbf, 0x54, 0x7f, 0x79, 0x70, 0x9b, 0x54, 0xbe, 0xa2, 0xfe, 0x11, 0xa9, ++ 0xbc, 0xa2, 0x61, 0xb7, 0x94, 0xaf, 0x6a, 0x7a, 0x5a, 0xaa, 0x6f, 0xd8, ++ 0x37, 0xe4, 0x6a, 0x94, 0xaf, 0x97, 0x8e, 0x1a, 0x19, 0xfa, 0xcb, 0x3e, ++ 0xf5, 0xbc, 0x4f, 0xfe, 0xba, 0x4f, 0x3d, 0x26, 0x0f, 0xd6, 0xa9, 0x44, ++ 0x99, 0x1b, 0x87, 0xf2, 0xec, 0x26, 0x79, 0x3e, 0xe5, 0xcf, 0xa5, 0xf4, ++ 0xb4, 0xdf, 0x43, 0xf2, 0x7e, 0xc6, 0x3f, 0x96, 0xd2, 0xb6, 0xa6, 0x03, ++ 0x76, 0xf4, 0x3f, 0x56, 0xc5, 0x81, 0xde, 0x4f, 0x04, 0x3b, 0xdc, 0xf8, ++ 0xe6, 0xda, 0x9a, 0x7e, 0xb8, 0xde, 0x40, 0xfb, 0xf1, 0x8c, 0x35, 0x1b, ++ 0x5b, 0xd7, 0x06, 0x20, 0x7f, 0x00, 0x0f, 0xa3, 0x60, 0xde, 0xcc, 0xa8, ++ 0x33, 0xb3, 0xd0, 0x28, 0x06, 0xd2, 0xdd, 0x37, 0x2c, 0xcf, 0x1d, 0xc6, ++ 0x88, 0xf2, 0xd6, 0x1e, 0xca, 0xeb, 0x54, 0x16, 0xea, 0xd3, 0xbd, 0x7c, ++ 0x46, 0x6b, 0xf4, 0xef, 0xed, 0x4a, 0xc7, 0xe0, 0x0c, 0xf4, 0x13, 0xbe, ++ 0x61, 0x61, 0x3b, 0x23, 0xfc, 0x75, 0xdd, 0xcf, 0x2b, 0x58, 0x26, 0xda, ++ 0x15, 0xb1, 0xca, 0xcf, 0x1a, 0x58, 0x59, 0xe4, 0x79, 0xd6, 0x49, 0x23, ++ 0x3f, 0x27, 0x71, 0x1a, 0x27, 0x9d, 0x34, 0x42, 0xba, 0xd2, 0xcc, 0xe7, ++ 0xff, 0xca, 0x3d, 0x19, 0x93, 0x98, 0x13, 0xf3, 0xa1, 0xc1, 0xd5, 0x51, ++ 0xfc, 0x2e, 0xe1, 0xfe, 0x1a, 0x00, 0x99, 0x34, 0xe4, 0x73, 0x8e, 0x34, ++ 0xef, 0x97, 0xd5, 0x5d, 0xdc, 0x35, 0xcf, 0x19, 0xf6, 0x93, 0x4d, 0x72, ++ 0xbb, 0x3c, 0x38, 0x4a, 0xfa, 0xbe, 0xa2, 0x7e, 0x82, 0xd4, 0x2e, 0x57, ++ 0xf1, 0xbd, 0x6b, 0x84, 0x7a, 0x67, 0xf7, 0x1b, 0x69, 0xbd, 0x66, 0xa1, ++ 0x03, 0x03, 0xae, 0x19, 0x86, 0xf8, 0x79, 0x4f, 0xe2, 0x77, 0xd6, 0x94, ++ 0x42, 0x76, 0x57, 0x8b, 0xdf, 0xdb, 0xe7, 0xe4, 0x40, 0xc6, 0xfe, 0xe8, ++ 0x2f, 0xa4, 0xf4, 0x55, 0x7f, 0x11, 0xa5, 0xaf, 0xf9, 0x4b, 0x28, 0x3d, ++ 0xe6, 0xf7, 0x51, 0xfa, 0xa6, 0xbf, 0x8c, 0xd2, 0x3f, 0xfb, 0xab, 0x29, ++ 0x7d, 0xc7, 0xbf, 0x86, 0xd2, 0x56, 0x7f, 0x80, 0xd2, 0x13, 0xfe, 0x1a, ++ 0x4a, 0x4f, 0xfa, 0x6b, 0x29, 0x3d, 0xe5, 0xaf, 0xa3, 0xf4, 0xb4, 0x3f, ++ 0x48, 0xe9, 0x19, 0x7f, 0x3d, 0xa5, 0x67, 0xfd, 0x0d, 0x94, 0xb6, 0xf9, ++ 0x9b, 0x28, 0xd5, 0xf4, 0x67, 0x4f, 0xf2, 0x77, 0x5a, 0xac, 0xaf, 0x67, ++ 0x50, 0xfe, 0xa2, 0xc8, 0x99, 0xf9, 0x56, 0xb6, 0xae, 0x66, 0x62, 0x97, ++ 0x9c, 0xc5, 0xa9, 0x96, 0x75, 0x28, 0x67, 0x1a, 0x7d, 0x67, 0xd4, 0x59, ++ 0x84, 0x3c, 0xa4, 0x4a, 0xf2, 0x90, 0x88, 0xeb, 0x30, 0xc9, 0x59, 0x0f, ++ 0xe5, 0x75, 0x26, 0x21, 0x87, 0xb1, 0xda, 0x47, 0x2f, 0x47, 0x79, 0xeb, ++ 0xfb, 0x3d, 0xc8, 0x1b, 0x63, 0xeb, 0x48, 0x0e, 0x66, 0x0a, 0xb9, 0xfb, ++ 0xae, 0xf2, 0xc6, 0xd0, 0x1b, 0x9f, 0x82, 0xf2, 0x94, 0xa9, 0x93, 0x27, ++ 0x59, 0x0e, 0x35, 0x39, 0xd2, 0xf4, 0x40, 0xae, 0x52, 0x34, 0x5c, 0x1d, ++ 0xd3, 0x25, 0x57, 0x33, 0x8d, 0xdc, 0x4e, 0xd2, 0xe4, 0xea, 0xe7, 0x68, ++ 0x27, 0x46, 0xb1, 0xb7, 0x6e, 0x50, 0x15, 0xb1, 0xfe, 0x71, 0xfb, 0x88, ++ 0xf9, 0x32, 0x0c, 0x68, 0xbf, 0xad, 0x12, 0x7e, 0x7f, 0xe6, 0x4e, 0xa7, ++ 0x7c, 0xa7, 0xe8, 0x7b, 0x3d, 0x80, 0x6b, 0xc1, 0x7a, 0x6a, 0x30, 0x17, ++ 0xd7, 0x91, 0xce, 0xdc, 0xbf, 0x0d, 0x46, 0xff, 0x78, 0xe7, 0x31, 0x0b, ++ 0x43, 0x3f, 0x7c, 0xac, 0xf1, 0xe9, 0xe5, 0x25, 0x36, 0xdd, 0xbd, 0xb4, ++ 0x7f, 0x28, 0x0d, 0xc2, 0xa2, 0x36, 0xaa, 0x7b, 0xb9, 0x2d, 0x8e, 0xd3, ++ 0xd5, 0x66, 0x60, 0x85, 0x2c, 0x0f, 0xcf, 0x67, 0xf3, 0x8f, 0xf9, 0x80, ++ 0x9f, 0x71, 0xff, 0x79, 0x71, 0x1e, 0xee, 0x6b, 0xe1, 0xbb, 0xca, 0xc8, ++ 0xae, 0x0a, 0x7a, 0x8a, 0xa3, 0xf8, 0xdb, 0x19, 0xca, 0x78, 0x5a, 0xcf, ++ 0xf4, 0xd5, 0xea, 0x9f, 0x7a, 0xe0, 0xcb, 0x7c, 0x3c, 0x37, 0x9f, 0x29, ++ 0xe6, 0x79, 0xdc, 0x01, 0x23, 0x3f, 0xd7, 0x0e, 0x3d, 0xe4, 0xb9, 0x26, ++ 0xe2, 0x7c, 0x06, 0xf6, 0xdb, 0xe9, 0xe8, 0x77, 0xee, 0x18, 0x64, 0x76, ++ 0x91, 0xfd, 0x10, 0xea, 0x2b, 0xd3, 0x31, 0xd8, 0x57, 0xa2, 0xe3, 0x81, ++ 0x41, 0x9f, 0x0d, 0xc6, 0xf3, 0x8d, 0x4d, 0x20, 0x87, 0x38, 0xbf, 0x3a, ++ 0x07, 0x0e, 0x4e, 0x60, 0xe7, 0x91, 0x8f, 0x9e, 0xf4, 0x7c, 0x4f, 0xf4, ++ 0x5c, 0x14, 0xec, 0xdb, 0x4b, 0x7a, 0x9a, 0x19, 0x9e, 0x1b, 0x01, 0x3d, ++ 0xb7, 0xe3, 0xfd, 0x97, 0xde, 0xd2, 0xb3, 0x27, 0x3d, 0xd9, 0x93, 0x7e, ++ 0x3c, 0xb1, 0x99, 0xd3, 0xd9, 0x29, 0xec, 0xd3, 0x58, 0x74, 0x6e, 0x9f, ++ 0x04, 0xf3, 0x2e, 0x8a, 0x1c, 0xdf, 0xa3, 0xaa, 0xb2, 0x1c, 0xb3, 0x81, ++ 0xfc, 0xbc, 0x43, 0xa3, 0x3f, 0xee, 0x4b, 0x23, 0xe8, 0x7f, 0xa9, 0xdd, ++ 0x4d, 0xf5, 0x9f, 0xdb, 0xf7, 0xd6, 0x80, 0x56, 0xe8, 0xa7, 0xb3, 0xf1, ++ 0xc2, 0x04, 0xc6, 0xcf, 0x73, 0xc8, 0xae, 0xeb, 0x78, 0x52, 0xd8, 0xed, ++ 0xee, 0x4c, 0x99, 0x8f, 0xad, 0x7d, 0x09, 0xae, 0x06, 0xe7, 0xb9, 0x27, ++ 0x5f, 0x1f, 0x80, 0xfb, 0xe4, 0xdb, 0x30, 0x03, 0xf3, 0xec, 0xc9, 0xf8, ++ 0xa2, 0x5f, 0xa9, 0x29, 0x5d, 0xf0, 0x7a, 0x7b, 0x0e, 0x1f, 0x6b, 0x5c, ++ 0xbb, 0xbf, 0xe5, 0xfc, 0x6c, 0x4f, 0xd5, 0xe6, 0x67, 0xcb, 0x00, 0x94, ++ 0xa7, 0xcf, 0x84, 0x1e, 0x88, 0x39, 0xbe, 0x9e, 0xe4, 0x14, 0xc7, 0x07, ++ 0x70, 0xae, 0x52, 0xf8, 0xf8, 0x36, 0x18, 0x8b, 0x7e, 0x87, 0x7a, 0x26, ++ 0x3c, 0xbe, 0xd1, 0x29, 0xbd, 0x1a, 0x5f, 0x55, 0x82, 0x99, 0x29, 0x23, ++ 0x00, 0x3f, 0x87, 0xd9, 0xcc, 0x12, 0x18, 0xdb, 0xa1, 0xfa, 0x0e, 0xaa, ++ 0xb4, 0x8f, 0xf3, 0xb4, 0x06, 0xd0, 0x4f, 0xb1, 0x2f, 0xde, 0xb3, 0x1e, ++ 0x58, 0x52, 0xe5, 0x3c, 0xf3, 0x72, 0xc8, 0x8d, 0xed, 0x64, 0x7f, 0xc6, ++ 0x8a, 0x7a, 0x9b, 0x4b, 0xb6, 0x9f, 0x12, 0x5d, 0xb2, 0xfd, 0x94, 0xe1, ++ 0x8a, 0xb4, 0x9f, 0x3a, 0x0f, 0x3d, 0xe4, 0xf4, 0x01, 0x7e, 0xab, 0xd2, ++ 0x0d, 0xae, 0x93, 0xa3, 0x70, 0x9d, 0xf3, 0x8a, 0x75, 0x8e, 0xaf, 0xab, ++ 0x1a, 0x7e, 0x15, 0x0d, 0x59, 0x2e, 0xbb, 0x04, 0x47, 0xce, 0x77, 0xd6, ++ 0x2a, 0x85, 0x0d, 0x24, 0x4f, 0xee, 0x84, 0xd9, 0x51, 0xce, 0xcb, 0xb4, ++ 0x74, 0x55, 0xba, 0xd9, 0x75, 0x12, 0xd6, 0xab, 0x33, 0xf5, 0x39, 0x09, ++ 0xd8, 0xef, 0x19, 0xbf, 0xd5, 0xc5, 0xd7, 0x57, 0x97, 0x8b, 0xf7, 0x9b, ++ 0xee, 0x8a, 0x5c, 0x5f, 0x57, 0xae, 0x89, 0xa3, 0xfa, 0x1a, 0x7e, 0xb1, ++ 0xe0, 0xfe, 0xb3, 0xf1, 0x63, 0xac, 0x91, 0xbd, 0x6b, 0xc5, 0x75, 0x11, ++ 0xca, 0x72, 0x62, 0xd7, 0x8f, 0xc9, 0x4f, 0xf5, 0x13, 0x33, 0x9d, 0x4b, ++ 0x37, 0x9b, 0x3e, 0x43, 0xfb, 0xdd, 0x96, 0xab, 0xd9, 0xef, 0x2a, 0xe5, ++ 0x35, 0xb8, 0x55, 0x0d, 0xc6, 0x80, 0x65, 0x04, 0x7e, 0xdf, 0x25, 0xf5, ++ 0x07, 0xed, 0xdc, 0xda, 0x19, 0x33, 0xb6, 0x8b, 0x2d, 0x37, 0x2a, 0x3b, ++ 0xa5, 0xf1, 0x13, 0xf8, 0x6f, 0xc5, 0x83, 0x77, 0xda, 0xb7, 0x5a, 0x89, ++ 0xcf, 0x3e, 0x80, 0x98, 0x00, 0xf0, 0xda, 0x55, 0x7b, 0x0d, 0xca, 0xd5, ++ 0x09, 0x95, 0xcf, 0xe7, 0x2a, 0x21, 0xa7, 0x15, 0xd6, 0x56, 0xb3, 0xcf, ++ 0x4d, 0xe4, 0x6e, 0x41, 0x79, 0x5e, 0x34, 0x96, 0x69, 0x13, 0x66, 0xee, ++ 0x5b, 0xa0, 0xa7, 0x3f, 0x78, 0xd1, 0x44, 0xf7, 0xb4, 0xd8, 0x57, 0x00, ++ 0x3d, 0xbf, 0xeb, 0xaa, 0xc0, 0x12, 0x56, 0xe4, 0x44, 0xa7, 0xe7, 0xa2, ++ 0xc6, 0x15, 0x33, 0x70, 0xdd, 0xfe, 0xc0, 0xa0, 0xed, 0x87, 0x6b, 0xf3, ++ 0x71, 0xdc, 0xe7, 0x98, 0xa1, 0x10, 0xf5, 0xd2, 0x39, 0xf6, 0x47, 0xe7, ++ 0xa8, 0x88, 0xf9, 0x3a, 0xc4, 0xc4, 0xfd, 0x31, 0xac, 0x86, 0xef, 0x73, ++ 0x02, 0xf0, 0x0f, 0xc7, 0xb7, 0xb4, 0x56, 0xde, 0xf7, 0x2c, 0xab, 0x93, ++ 0xf3, 0xa5, 0x6c, 0x56, 0x2a, 0xea, 0xdb, 0xd2, 0x2d, 0x26, 0x16, 0x04, ++ 0xdc, 0x97, 0xe3, 0xbe, 0x49, 0x1b, 0x37, 0xe8, 0xdf, 0x0c, 0x13, 0xf7, ++ 0x6b, 0x2c, 0x63, 0xd5, 0x1b, 0x70, 0x9f, 0x7e, 0xaf, 0x89, 0xfb, 0x7b, ++ 0x16, 0xb9, 0x98, 0x9a, 0x09, 0x78, 0x55, 0xfc, 0xc7, 0x2f, 0xf3, 0xd1, ++ 0xef, 0xe3, 0x31, 0x71, 0xbb, 0x43, 0x3b, 0x4f, 0x5e, 0x9e, 0xc4, 0xf1, ++ 0x2e, 0x9f, 0x1d, 0x34, 0x7b, 0xa1, 0xfe, 0xbb, 0x8d, 0xa3, 0xe6, 0x80, ++ 0xc6, 0x85, 0xf6, 0xc1, 0x0d, 0x64, 0xff, 0x14, 0x33, 0xcf, 0x4e, 0xd6, ++ 0x9d, 0xee, 0x8b, 0x6b, 0x64, 0xfc, 0x7a, 0xc2, 0x5f, 0x8f, 0xaf, 0x66, ++ 0x07, 0x75, 0x3b, 0xd7, 0x16, 0x78, 0x24, 0xd7, 0x2b, 0xde, 0x60, 0x14, ++ 0x3d, 0x77, 0x99, 0x49, 0x11, 0xfb, 0x3f, 0x3e, 0x3f, 0x66, 0x9b, 0x64, ++ 0x7f, 0xce, 0x3c, 0x93, 0xec, 0xf7, 0xd1, 0xe4, 0xc0, 0x24, 0xe4, 0xe0, ++ 0x84, 0xea, 0xbb, 0xda, 0x34, 0x86, 0xf3, 0x1d, 0xf9, 0xa8, 0xa8, 0x1d, ++ 0x66, 0x5f, 0x44, 0x3d, 0x73, 0x57, 0xbd, 0xd9, 0xe7, 0xab, 0x67, 0xc1, ++ 0x7a, 0x46, 0xaa, 0x37, 0xcf, 0x94, 0x82, 0xf5, 0x3a, 0xa6, 0xd1, 0xfe, ++ 0x98, 0x81, 0x3c, 0x0d, 0xed, 0xaa, 0x67, 0xeb, 0x82, 0x77, 0x23, 0x87, ++ 0x27, 0xd7, 0xab, 0xf8, 0x8f, 0xc7, 0x9e, 0x0a, 0x80, 0xbc, 0x94, 0xff, ++ 0xf6, 0x1e, 0x27, 0x83, 0x75, 0xf3, 0x03, 0xb5, 0x36, 0xd5, 0x03, 0xdf, ++ 0x57, 0xee, 0xbc, 0xcd, 0xe9, 0x85, 0xf4, 0xb4, 0x1a, 0x70, 0x22, 0x3f, ++ 0x3f, 0x08, 0x1a, 0x0b, 0xa3, 0xd1, 0x63, 0x4b, 0x98, 0x1e, 0x5e, 0xbb, ++ 0x82, 0xfe, 0x34, 0x21, 0x9f, 0xac, 0x26, 0x40, 0x7e, 0x8a, 0xcf, 0x76, ++ 0x9a, 0x5c, 0xe4, 0xe7, 0xaf, 0xb7, 0x84, 0x2c, 0x20, 0xa7, 0x95, 0x8d, ++ 0xcb, 0x67, 0xb0, 0xe1, 0x94, 0x3f, 0xce, 0xf3, 0x1b, 0x3f, 0x32, 0x62, ++ 0xbe, 0x49, 0xe6, 0x57, 0xf9, 0xaf, 0xef, 0x49, 0x75, 0xf3, 0x7b, 0x36, ++ 0xdc, 0x9f, 0xc4, 0x42, 0x64, 0xe7, 0x56, 0xee, 0x78, 0x6f, 0x1a, 0xae, ++ 0x17, 0x55, 0xac, 0x83, 0xe4, 0x4c, 0xdf, 0x0e, 0xfb, 0xff, 0x3c, 0x89, ++ 0xe6, 0xf5, 0x42, 0x73, 0x42, 0xf7, 0x72, 0xc0, 0x93, 0xfc, 0x09, 0x55, ++ 0x62, 0x96, 0x55, 0x35, 0xfe, 0xfc, 0x23, 0xa3, 0x13, 0xf3, 0xb2, 0x7c, ++ 0x94, 0x09, 0x7b, 0x15, 0xe9, 0x84, 0xfb, 0xfc, 0xdb, 0x4c, 0x8e, 0xe4, ++ 0x53, 0xf1, 0x90, 0xbd, 0x84, 0x5d, 0x82, 0xf3, 0x5c, 0xa3, 0x07, 0x0b, ++ 0x72, 0xbb, 0x75, 0xfd, 0x23, 0xf7, 0x0d, 0x3f, 0x0e, 0xf8, 0x9c, 0xdd, ++ 0xf1, 0xa2, 0x53, 0x19, 0x1a, 0xa9, 0x1f, 0xb8, 0x9c, 0x75, 0x36, 0x2c, ++ 0xfe, 0x95, 0xd5, 0x10, 0x5b, 0x8f, 0xb4, 0x81, 0x1c, 0x46, 0xda, 0x47, ++ 0x00, 0x98, 0xda, 0xb9, 0x9b, 0x84, 0xbd, 0xdd, 0xcc, 0xd3, 0x95, 0xa6, ++ 0x90, 0x13, 0xef, 0xb3, 0xac, 0xdc, 0x66, 0xf2, 0x80, 0x04, 0xb2, 0x95, ++ 0x8f, 0x19, 0x19, 0xde, 0x03, 0x60, 0x6f, 0x58, 0x82, 0xe8, 0x17, 0x5d, ++ 0xf1, 0xd8, 0xf3, 0xaf, 0x8d, 0x07, 0xba, 0xaf, 0xd8, 0x6d, 0x4a, 0x9e, ++ 0xc1, 0x87, 0x63, 0x57, 0x52, 0xbb, 0xf8, 0x52, 0x05, 0xff, 0x5b, 0x93, ++ 0xd7, 0xc5, 0x87, 0xf2, 0x27, 0x9e, 0x37, 0xbb, 0x87, 0xf1, 0xef, 0xb7, ++ 0x24, 0x75, 0xf1, 0x63, 0xc5, 0xee, 0xfd, 0x66, 0x36, 0xac, 0x3b, 0xfd, ++ 0x26, 0x37, 0xec, 0x37, 0xb7, 0xda, 0xa3, 0xf0, 0xa5, 0xe1, 0xf8, 0x34, ++ 0x5c, 0x67, 0xd7, 0x3f, 0xf2, 0x57, 0x33, 0xfa, 0x13, 0x3f, 0xd8, 0xa7, ++ 0xb0, 0xb4, 0xac, 0xee, 0xed, 0xcb, 0xb6, 0x3d, 0x4f, 0xeb, 0x1d, 0xd2, ++ 0x89, 0xf8, 0x28, 0xf8, 0x14, 0xe6, 0x5b, 0x37, 0x7e, 0x85, 0x66, 0x3e, ++ 0x33, 0x9a, 0xea, 0xb9, 0x50, 0x0f, 0xc6, 0xe2, 0xd7, 0x32, 0xa1, 0x77, ++ 0x41, 0x9e, 0x1f, 0x7f, 0x06, 0xef, 0xff, 0xbc, 0x69, 0xf1, 0xe0, 0xf8, ++ 0xcb, 0x1e, 0xbf, 0xc9, 0x89, 0xe3, 0x78, 0x5f, 0xad, 0xe6, 0x72, 0xfd, ++ 0xcb, 0xdb, 0x52, 0x71, 0x7e, 0x97, 0x99, 0x02, 0xa9, 0x2e, 0x4a, 0xf9, ++ 0xf7, 0xb2, 0x07, 0x7f, 0x44, 0xf2, 0xb6, 0xec, 0xc8, 0x8f, 0x52, 0xc9, ++ 0x5e, 0x60, 0xde, 0x0c, 0x03, 0xe9, 0xe2, 0x40, 0x06, 0x8e, 0x6f, 0xe9, ++ 0xd6, 0x6b, 0x69, 0x7c, 0xa5, 0xcc, 0x47, 0x72, 0x57, 0xf6, 0x4b, 0x63, ++ 0x11, 0xde, 0x47, 0xfc, 0x54, 0x65, 0x85, 0xbb, 0xa3, 0xcc, 0x8b, 0x38, ++ 0xb3, 0x42, 0xf8, 0xbc, 0xbf, 0x1d, 0x0c, 0x19, 0x18, 0xdf, 0xfb, 0xb8, ++ 0xbf, 0x44, 0x7d, 0xf6, 0x47, 0x23, 0xdd, 0x8b, 0x62, 0xec, 0x87, 0x74, ++ 0x6f, 0xec, 0x47, 0x62, 0xac, 0xb0, 0xf2, 0x51, 0xfe, 0x53, 0x2b, 0xe7, ++ 0xd3, 0x71, 0xa1, 0x27, 0x71, 0x22, 0x4b, 0xf2, 0xba, 0x63, 0x63, 0x0b, ++ 0xf2, 0xe7, 0x4c, 0x7f, 0x6f, 0x1a, 0x9e, 0x73, 0x00, 0x1d, 0x02, 0x82, ++ 0x5e, 0xca, 0x37, 0x00, 0xd7, 0x78, 0x64, 0x6a, 0x1a, 0xe7, 0x0f, 0x73, ++ 0xab, 0xf9, 0xa2, 0x1d, 0xe8, 0xf7, 0xc9, 0xf8, 0x1d, 0xeb, 0xb7, 0x98, ++ 0xbc, 0xb6, 0xe1, 0x52, 0x3b, 0xa1, 0x0f, 0x79, 0xff, 0xab, 0x45, 0xff, ++ 0x80, 0x77, 0x1c, 0xae, 0x57, 0xef, 0xa7, 0x46, 0xb7, 0xf7, 0xc6, 0x88, ++ 0xf1, 0xc1, 0x5f, 0x0b, 0x8b, 0x90, 0xaf, 0x88, 0xf9, 0xcd, 0xe7, 0xfb, ++ 0x8e, 0x4d, 0x7c, 0x7e, 0x6b, 0xf3, 0x3d, 0x58, 0x5c, 0x88, 0xe5, 0x9f, ++ 0xbc, 0xca, 0xe7, 0x0f, 0xb6, 0xc3, 0xf5, 0x01, 0xf0, 0x0a, 0xa5, 0x51, ++ 0xf9, 0xfe, 0xd9, 0x0a, 0xe9, 0x03, 0xd8, 0x57, 0x47, 0x9b, 0xd7, 0x3b, ++ 0x4c, 0x62, 0x5e, 0xcb, 0xe5, 0x60, 0x29, 0xd2, 0x7a, 0x0f, 0x78, 0xab, ++ 0x4a, 0x42, 0xa4, 0x9c, 0x00, 0xfc, 0x24, 0xa2, 0x3f, 0xed, 0x83, 0x4b, ++ 0xb7, 0x40, 0xbb, 0x08, 0xfb, 0xab, 0x0a, 0xfb, 0xa3, 0x7a, 0xe6, 0xae, ++ 0xef, 0x11, 0xeb, 0xc3, 0x32, 0xa1, 0x07, 0x4c, 0x66, 0x98, 0xff, 0x17, ++ 0x77, 0xcd, 0x7f, 0xb6, 0x95, 0xcf, 0xfb, 0x9e, 0xec, 0xc9, 0x95, 0xa6, ++ 0xe0, 0xc3, 0x0f, 0xe0, 0x7c, 0x7d, 0xc3, 0xe2, 0x09, 0xb8, 0x71, 0xbe, ++ 0x9a, 0x8a, 0x70, 0xdc, 0x1f, 0xee, 0x3a, 0xf0, 0xda, 0x75, 0x20, 0xd7, ++ 0x1f, 0x36, 0x68, 0xf3, 0x54, 0xd6, 0x9f, 0xfa, 0x79, 0x5a, 0xb6, 0x67, ++ 0x0c, 0x8b, 0x36, 0x4f, 0x3f, 0xb4, 0xc3, 0xfe, 0x2a, 0xda, 0x3c, 0x85, ++ 0xef, 0x51, 0xe7, 0xa9, 0xbd, 0x95, 0xe4, 0xf8, 0xfb, 0xd6, 0x9f, 0x1a, ++ 0xdd, 0x86, 0x9a, 0x65, 0xbd, 0x89, 0x7a, 0xf0, 0x19, 0x77, 0x6c, 0xfa, ++ 0xe9, 0xf5, 0xe0, 0xef, 0x4d, 0x6e, 0xa2, 0xa3, 0x5e, 0x0f, 0xc2, 0xdf, ++ 0xab, 0x2c, 0xbf, 0xbb, 0xdc, 0x69, 0xf2, 0xa6, 0xc9, 0x59, 0xf9, 0x6f, ++ 0x2a, 0x2e, 0x40, 0x7d, 0x13, 0x96, 0x47, 0x4d, 0xde, 0xc2, 0xf2, 0xa8, ++ 0xc9, 0x9b, 0x7e, 0x9c, 0x32, 0xdd, 0xf4, 0xe5, 0x7f, 0x15, 0xfa, 0xe6, ++ 0x7a, 0x6b, 0xe1, 0x35, 0x68, 0x17, 0x5b, 0x3b, 0x18, 0xed, 0x57, 0x0a, ++ 0x66, 0x1b, 0x83, 0xb8, 0x4f, 0xb6, 0x7e, 0xc2, 0x68, 0xbe, 0x4f, 0xba, ++ 0x21, 0x9e, 0xf2, 0x73, 0x8d, 0xad, 0x4f, 0xa0, 0xcd, 0xf7, 0x56, 0xc5, ++ 0xdc, 0x61, 0xb8, 0x8e, 0x5f, 0xcf, 0x02, 0x26, 0x7e, 0x6e, 0x5e, 0x6b, ++ 0x22, 0x3b, 0xf5, 0xab, 0x6f, 0xbe, 0x99, 0x08, 0xe3, 0xb9, 0x4e, 0xd0, ++ 0xf5, 0x7a, 0x20, 0xf3, 0x55, 0xc0, 0x87, 0x12, 0x55, 0x09, 0xc5, 0x01, ++ 0x9e, 0xf3, 0x54, 0x16, 0x48, 0x48, 0x42, 0x7f, 0xb1, 0xc2, 0x4e, 0x44, ++ 0xe0, 0x71, 0x7d, 0x99, 0x9c, 0xc7, 0xbf, 0xcb, 0x52, 0xbb, 0xe0, 0xf4, ++ 0x54, 0xff, 0xdb, 0xda, 0xd5, 0xdf, 0x35, 0x3d, 0xe2, 0xe7, 0x67, 0x57, ++ 0x7f, 0xc2, 0x94, 0xf6, 0x17, 0x60, 0x38, 0x47, 0xc8, 0x51, 0x71, 0x33, ++ 0x3f, 0xa7, 0xa8, 0x1a, 0xad, 0x04, 0xb3, 0x69, 0xfe, 0xb5, 0xaa, 0x45, ++ 0x11, 0xfb, 0x84, 0xc7, 0xcc, 0xdc, 0xce, 0x38, 0x32, 0xe5, 0x9a, 0x31, ++ 0x48, 0xbf, 0x82, 0xb9, 0xc3, 0x12, 0x48, 0xbe, 0x6b, 0x87, 0xd0, 0x3e, ++ 0xb0, 0x4a, 0xe8, 0xad, 0xce, 0x80, 0x3b, 0x01, 0xf5, 0x79, 0x67, 0x73, ++ 0x0e, 0xed, 0xfb, 0x3a, 0x0f, 0x2d, 0x76, 0xf8, 0xa2, 0xe8, 0xaf, 0x03, ++ 0x42, 0xce, 0x9e, 0x17, 0xe7, 0x2c, 0xed, 0x76, 0xa5, 0xd6, 0x08, 0xf2, ++ 0xde, 0xce, 0x3a, 0xc8, 0x6e, 0x09, 0xd8, 0x6d, 0x51, 0xfd, 0x6e, 0x75, ++ 0x66, 0x83, 0xb0, 0x77, 0x04, 0xdf, 0xe0, 0xcf, 0x08, 0xfd, 0x97, 0x08, ++ 0x39, 0x9c, 0x07, 0x4d, 0x13, 0xf2, 0x22, 0xf8, 0x36, 0xfb, 0xaa, 0x0f, ++ 0x54, 0x67, 0x77, 0x3e, 0xe0, 0xdf, 0x89, 0x88, 0x7d, 0xc3, 0x3f, 0x4a, ++ 0x5f, 0x94, 0x6b, 0xa4, 0xef, 0x01, 0x5b, 0xeb, 0xb4, 0xa2, 0x28, 0xfe, ++ 0x99, 0x47, 0x85, 0xbe, 0xbe, 0xec, 0xd9, 0x2f, 0xcc, 0xb8, 0xce, 0x4d, ++ 0x69, 0x2e, 0x50, 0x91, 0x8e, 0x53, 0xec, 0x46, 0xc9, 0xdf, 0xb1, 0x5d, ++ 0x9b, 0xaf, 0x43, 0xd9, 0x50, 0xc4, 0xeb, 0xb2, 0x67, 0x97, 0xdf, 0x31, ++ 0x06, 0xe4, 0xb8, 0xea, 0x90, 0xd1, 0x63, 0x83, 0xf1, 0x55, 0x35, 0x7f, ++ 0x64, 0xf6, 0x45, 0xd9, 0xbf, 0xe9, 0xe9, 0x89, 0xf0, 0xd1, 0x7e, 0x6c, ++ 0x35, 0x73, 0xfb, 0xf8, 0xa8, 0xa9, 0x68, 0x29, 0xd2, 0xf5, 0xe8, 0xb5, ++ 0xfc, 0x3c, 0xf7, 0x4f, 0x66, 0x4f, 0x45, 0x34, 0x3c, 0x67, 0x5b, 0x39, ++ 0x9e, 0xf3, 0x58, 0xd1, 0xa7, 0xa3, 0x95, 0x7f, 0x3d, 0xfa, 0x16, 0xcc, ++ 0x75, 0x84, 0x26, 0x01, 0x3d, 0x3a, 0xed, 0xfc, 0x7e, 0x72, 0x77, 0xf9, ++ 0xe3, 0xf3, 0xbe, 0xd3, 0xa5, 0x04, 0xd7, 0x2a, 0x28, 0x87, 0x46, 0x9e, ++ 0x4f, 0xe6, 0xf7, 0x7f, 0xa7, 0x31, 0xdf, 0x1d, 0x13, 0x15, 0x9a, 0xef, ++ 0x97, 0x47, 0xea, 0xaf, 0x82, 0xa6, 0xe2, 0xc7, 0xf0, 0x3e, 0x4b, 0x65, ++ 0xb3, 0xe2, 0x32, 0x40, 0x79, 0xa5, 0xda, 0x6a, 0x46, 0x39, 0xae, 0x6a, ++ 0xda, 0xad, 0xa2, 0x5d, 0xfe, 0x03, 0x37, 0x7f, 0x67, 0xc1, 0xd4, 0xea, ++ 0x61, 0xb3, 0x23, 0xfc, 0x5b, 0xad, 0x66, 0xee, 0x4f, 0x3a, 0xf0, 0xb7, ++ 0xeb, 0xe6, 0x23, 0x7d, 0x3f, 0x9e, 0x6d, 0x61, 0x88, 0x97, 0x77, 0xe8, ++ 0x47, 0x4e, 0x5c, 0xef, 0x3f, 0x6e, 0x1e, 0x45, 0xf3, 0x20, 0xd6, 0xb8, ++ 0xfe, 0xe0, 0xf7, 0x5c, 0x33, 0x05, 0xfd, 0xf1, 0x66, 0xae, 0xcf, 0xf4, ++ 0xf2, 0x30, 0x2d, 0x39, 0x5e, 0xca, 0x5f, 0x3b, 0x99, 0xf5, 0xc3, 0x73, ++ 0xde, 0xcb, 0x2c, 0xad, 0x37, 0x79, 0xa2, 0xf0, 0x6f, 0x9d, 0x85, 0xcf, ++ 0xd3, 0x5e, 0xeb, 0x37, 0xeb, 0xff, 0x30, 0xfd, 0x36, 0x11, 0xf4, 0x1b, ++ 0x97, 0x6b, 0x53, 0xa4, 0x7e, 0x9b, 0x6e, 0xe1, 0x72, 0x1f, 0xa1, 0xdf, ++ 0xd2, 0xa2, 0xe9, 0xb7, 0x55, 0x6b, 0xdd, 0x69, 0x28, 0x17, 0xab, 0xf6, ++ 0xe6, 0xa4, 0x21, 0x5f, 0x57, 0x1d, 0x5e, 0x9a, 0x12, 0x4d, 0xbf, 0xbd, ++ 0x20, 0xf6, 0xb5, 0x87, 0xc5, 0x3d, 0xe9, 0xf6, 0x7e, 0xa0, 0xdf, 0x46, ++ 0x44, 0xe8, 0xb7, 0x7e, 0xa0, 0xdf, 0xa2, 0xf8, 0xc1, 0x47, 0x5b, 0x34, ++ 0xbb, 0xb3, 0x07, 0xfd, 0x66, 0xfd, 0xef, 0x99, 0x7f, 0x2f, 0xa0, 0x7e, ++ 0x8b, 0x32, 0xde, 0x2b, 0x84, 0xdc, 0x69, 0xfa, 0xad, 0xb0, 0x79, 0x2d, ++ 0xe9, 0xb7, 0xc2, 0x7e, 0x46, 0xe9, 0x3e, 0xd2, 0x65, 0x16, 0x61, 0xc7, ++ 0xc5, 0xd4, 0x6f, 0x0b, 0xef, 0xb9, 0x96, 0xf2, 0x26, 0x4f, 0x7c, 0x14, ++ 0xf9, 0x41, 0xba, 0xa2, 0x7e, 0x3b, 0x2c, 0xf4, 0x1c, 0xf6, 0x83, 0x7a, ++ 0xee, 0x67, 0x96, 0x6f, 0xa7, 0xe7, 0xe6, 0x59, 0x39, 0xbe, 0x3d, 0xea, ++ 0xb9, 0xff, 0x26, 0x3a, 0x6b, 0x7a, 0x6e, 0x55, 0x7f, 0x85, 0xec, 0x97, ++ 0xee, 0x72, 0xc8, 0xf5, 0xdc, 0xaa, 0x2c, 0xae, 0xe7, 0x56, 0xed, 0xe5, ++ 0x7a, 0x6e, 0xd5, 0x20, 0xae, 0xe7, 0xf4, 0xfa, 0x6d, 0x52, 0x37, 0xfd, ++ 0xc6, 0xdb, 0x57, 0xe6, 0x42, 0x7b, 0xda, 0x27, 0x66, 0xdd, 0x77, 0x03, ++ 0xde, 0xe7, 0x2b, 0x31, 0x79, 0xac, 0x50, 0x7f, 0x86, 0x5b, 0x7b, 0x5f, ++ 0x50, 0x3d, 0x26, 0x52, 0xdf, 0xfd, 0xcc, 0x12, 0x43, 0xdf, 0x79, 0x40, ++ 0xdf, 0xd9, 0x7b, 0xd6, 0x77, 0xaf, 0xa0, 0xbe, 0x53, 0x49, 0x8f, 0x0d, ++ 0xc4, 0x79, 0xa4, 0x97, 0x8f, 0xe9, 0x03, 0xe3, 0xa5, 0xfb, 0x6a, 0x47, ++ 0xbf, 0x38, 0xf5, 0x9b, 0xdf, 0xe2, 0x7c, 0xf9, 0x83, 0x91, 0xee, 0x03, ++ 0xbd, 0x6e, 0xe0, 0xfb, 0xa1, 0x7d, 0x5f, 0x9c, 0x1a, 0x85, 0xf3, 0xee, ++ 0x65, 0xc4, 0x07, 0xe6, 0xcb, 0x4e, 0x21, 0x7f, 0x6d, 0xfe, 0xb1, 0xa4, ++ 0x4f, 0x27, 0x0f, 0xe5, 0xf3, 0xbd, 0xe2, 0x50, 0x1c, 0xad, 0x13, 0x95, ++ 0x8d, 0x0a, 0x1f, 0xef, 0x2d, 0x4a, 0xd0, 0x8d, 0xeb, 0xc0, 0xdf, 0x3e, ++ 0xa7, 0x7d, 0xf2, 0xfc, 0xbd, 0x7c, 0x9f, 0x3c, 0xd7, 0xc2, 0xe9, 0xc1, ++ 0x7e, 0x6c, 0xe4, 0xef, 0x22, 0x80, 0x04, 0x0b, 0x23, 0xe4, 0xa1, 0xe4, ++ 0xf3, 0x72, 0xf2, 0xf3, 0x95, 0xa8, 0xcc, 0x8a, 0xf6, 0xeb, 0x82, 0x43, ++ 0xd3, 0x3f, 0x40, 0xbb, 0x75, 0xc1, 0xe7, 0x35, 0x64, 0xef, 0x2e, 0xc0, ++ 0xef, 0x78, 0xbf, 0x62, 0x77, 0xeb, 0x86, 0x4c, 0xe8, 0x77, 0xfe, 0x72, ++ 0x85, 0xf6, 0x1b, 0x4c, 0xdc, 0x87, 0xd0, 0xee, 0x4b, 0x5c, 0xdf, 0xbc, ++ 0x9f, 0xee, 0xaf, 0xe8, 0xef, 0x41, 0x68, 0xfa, 0x7c, 0x7e, 0xb5, 0xfc, ++ 0x7d, 0x81, 0xce, 0xae, 0x3f, 0x20, 0xc6, 0x09, 0xf6, 0x2c, 0xd1, 0x85, ++ 0xbd, 0x62, 0x8c, 0xea, 0x9f, 0x3b, 0xa0, 0xa7, 0x87, 0x87, 0x8f, 0xbf, ++ 0x62, 0x35, 0xb7, 0x8f, 0xc3, 0xf4, 0x00, 0xfa, 0xb8, 0x95, 0xee, 0xf4, ++ 0x00, 0x8e, 0xce, 0x58, 0x98, 0xda, 0x35, 0xfe, 0xf9, 0x4f, 0xc2, 0xb8, ++ 0x92, 0xbb, 0xc6, 0xa5, 0xd1, 0x43, 0x3f, 0x3e, 0x6d, 0x7f, 0xb2, 0x40, ++ 0xcc, 0x8d, 0x58, 0xe3, 0xd5, 0xe8, 0xd7, 0x6d, 0xbc, 0x1a, 0x3d, 0x75, ++ 0xe3, 0x7e, 0xde, 0x22, 0xec, 0xa2, 0x8b, 0xd9, 0x30, 0x9c, 0x67, 0xaf, ++ 0x1b, 0x7c, 0x77, 0x8c, 0x41, 0xb9, 0xf8, 0x3d, 0x8c, 0x1f, 0xf0, 0x99, ++ 0x33, 0x6f, 0x50, 0x5a, 0xa4, 0x1e, 0x7e, 0x51, 0xe8, 0xf3, 0xab, 0x7c, ++ 0xc7, 0xa7, 0xa4, 0xba, 0x91, 0x5e, 0xfc, 0xfd, 0xdd, 0x75, 0x65, 0xbb, ++ 0x9f, 0x4f, 0x85, 0x71, 0x5c, 0xed, 0xcd, 0xca, 0xc3, 0xab, 0x08, 0xd7, ++ 0xfe, 0xcd, 0xec, 0x43, 0x3f, 0xc2, 0x01, 0x5b, 0x07, 0xe9, 0x35, 0x4d, ++ 0xae, 0x2e, 0xb4, 0x72, 0x39, 0xff, 0xbb, 0x80, 0x73, 0xb4, 0xaf, 0x6b, ++ 0x0a, 0xad, 0x1f, 0x4d, 0x8a, 0x8b, 0xe6, 0x4b, 0x48, 0xa7, 0xb7, 0xc4, ++ 0xbd, 0xb0, 0x2a, 0xa0, 0x27, 0xce, 0xc7, 0xaa, 0x26, 0xb1, 0xde, 0x80, ++ 0xbc, 0xe1, 0x7c, 0x9b, 0xa6, 0xad, 0x3f, 0x48, 0x7f, 0xf8, 0xcf, 0xab, ++ 0x9a, 0x39, 0xfd, 0xab, 0xaa, 0x15, 0xa2, 0xff, 0x4c, 0xd6, 0x71, 0x10, ++ 0xe9, 0x5b, 0x99, 0xac, 0x78, 0x42, 0x00, 0x6a, 0x5a, 0xd3, 0xee, 0xdb, ++ 0xf0, 0x1e, 0xd5, 0x0b, 0x36, 0xf8, 0x8e, 0xf3, 0xb6, 0x4c, 0xf1, 0x6c, ++ 0xe7, 0xe4, 0xb0, 0x67, 0xa4, 0x46, 0x95, 0x4b, 0x35, 0x9a, 0x5c, 0xb2, ++ 0xea, 0x21, 0xe4, 0x57, 0xd0, 0xd6, 0xc1, 0x05, 0x58, 0x2f, 0x09, 0xdf, ++ 0x8b, 0xbc, 0x9e, 0x82, 0xf6, 0x89, 0xde, 0xde, 0xb8, 0xcc, 0xd2, 0x72, ++ 0x14, 0xf1, 0xb8, 0xec, 0xc7, 0x26, 0xb6, 0x8d, 0x75, 0xb7, 0x3f, 0x34, ++ 0x7e, 0xe7, 0xc2, 0xbf, 0x6f, 0xa2, 0xdd, 0xe7, 0xe9, 0x41, 0x7e, 0x07, ++ 0x09, 0xfb, 0xf2, 0x05, 0xa4, 0xb7, 0x1d, 0xe9, 0xda, 0x61, 0x46, 0xb9, ++ 0xaf, 0x0a, 0xf1, 0x75, 0x43, 0x2b, 0xaf, 0x52, 0xdd, 0x53, 0x88, 0x3e, ++ 0x1a, 0xbd, 0x9b, 0x60, 0x5d, 0x18, 0xcd, 0xe9, 0x8d, 0xef, 0xbe, 0xf4, ++ 0xf4, 0xbc, 0x5a, 0xcb, 0xa3, 0x3c, 0x63, 0xfd, 0x66, 0xc5, 0x84, 0xed, ++ 0xaf, 0x04, 0x3e, 0xf4, 0x81, 0xa2, 0xc9, 0x86, 0x2f, 0x0e, 0x6a, 0xf2, ++ 0x8b, 0xef, 0xc4, 0xf4, 0x74, 0xc1, 0xfd, 0x7f, 0x46, 0xc4, 0x7c, 0x47, ++ 0xbd, 0x14, 0x79, 0xee, 0x58, 0xd9, 0x74, 0x84, 0xe8, 0x32, 0x7d, 0x35, ++ 0x98, 0x55, 0x11, 0x74, 0x47, 0x7d, 0x75, 0x3e, 0xfa, 0x74, 0x9b, 0x0f, ++ 0x4d, 0xfb, 0xa3, 0xde, 0x83, 0xfa, 0xb6, 0xf3, 0xe1, 0x42, 0xab, 0x3c, ++ 0x1f, 0xf6, 0xd9, 0x3a, 0x5e, 0x1c, 0x81, 0xfe, 0xad, 0xbd, 0x0a, 0xe9, ++ 0x03, 0xd6, 0x9c, 0x28, 0xed, 0xef, 0xaf, 0xb0, 0xf2, 0x7d, 0xd3, 0x01, ++ 0x9b, 0x8f, 0xe4, 0xb6, 0xe3, 0xb0, 0x89, 0xee, 0x7b, 0xeb, 0xf5, 0xc6, ++ 0x58, 0x41, 0x7f, 0xdc, 0x4f, 0x44, 0xbe, 0x83, 0x9b, 0x8c, 0x03, 0xc1, ++ 0xf3, 0x5d, 0x97, 0x8d, 0xbd, 0xab, 0xe1, 0x91, 0xcd, 0xe5, 0x27, 0x52, ++ 0x5f, 0xbf, 0x60, 0xf3, 0x11, 0x9f, 0x62, 0xc1, 0x9f, 0x26, 0xe0, 0xc7, ++ 0xb2, 0x97, 0xc2, 0xf8, 0x62, 0x7f, 0x78, 0x9e, 0xe2, 0x96, 0xfb, 0xd3, ++ 0xaf, 0x17, 0x9a, 0x9f, 0xa7, 0xa7, 0x71, 0x5d, 0x23, 0xd6, 0xfb, 0xef, ++ 0x3a, 0xae, 0xf0, 0xf9, 0x24, 0x6b, 0x31, 0x33, 0xee, 0xcf, 0xdf, 0x6d, ++ 0x8e, 0x38, 0x67, 0x9a, 0x23, 0xfc, 0xfc, 0x9a, 0x1f, 0x2c, 0xa2, 0xde, ++ 0x4c, 0xcb, 0x98, 0xd8, 0xf5, 0xd0, 0xdf, 0x12, 0x82, 0x71, 0xbf, 0xb0, ++ 0xeb, 0x21, 0xf2, 0xeb, 0x9e, 0x7b, 0xf4, 0xf8, 0x4c, 0x94, 0xdb, 0x15, ++ 0xbf, 0x33, 0x32, 0x2b, 0xf0, 0xb9, 0x6d, 0x97, 0x83, 0x85, 0xf8, 0x3d, ++ 0x0a, 0x33, 0xae, 0xab, 0xe5, 0x8d, 0xc6, 0xa8, 0xe7, 0x22, 0x8c, 0xad, ++ 0x27, 0xfc, 0x56, 0xfc, 0xd6, 0x41, 0x7a, 0xa5, 0x7c, 0x8f, 0x25, 0x38, ++ 0x03, 0xda, 0x97, 0x3f, 0xf5, 0xee, 0x70, 0xf4, 0x4f, 0xb5, 0xad, 0xe3, ++ 0xfa, 0x25, 0xf0, 0xa8, 0x90, 0x8f, 0x40, 0xeb, 0x70, 0x3c, 0x2f, 0x2f, ++ 0x57, 0xf9, 0x79, 0xb1, 0x1e, 0xde, 0x8f, 0x85, 0xbc, 0x9c, 0x7d, 0x3a, ++ 0xbe, 0x04, 0xf5, 0xa3, 0x52, 0xcf, 0xdf, 0x75, 0x96, 0x37, 0xcc, 0x35, ++ 0x59, 0x22, 0xf6, 0xe5, 0x95, 0x78, 0xe0, 0xc6, 0xeb, 0xd1, 0x3d, 0xe4, ++ 0xc0, 0x23, 0x0a, 0xf9, 0xc1, 0xbb, 0xe3, 0xb7, 0x96, 0xd7, 0x7b, 0x84, ++ 0xeb, 0xbd, 0xf2, 0x26, 0x53, 0x10, 0xdf, 0x87, 0x96, 0xd7, 0x6f, 0xa3, ++ 0xfd, 0x6c, 0x55, 0xfd, 0x47, 0x66, 0xb4, 0xe3, 0x26, 0xff, 0xf6, 0x31, ++ 0xb2, 0x23, 0xaa, 0x9a, 0x8c, 0xb2, 0x9f, 0xb0, 0xde, 0x18, 0xb2, 0x90, ++ 0x1f, 0xd3, 0x78, 0x1c, 0x53, 0xbd, 0xbf, 0xae, 0xb2, 0xb1, 0x82, 0xe6, ++ 0x63, 0x65, 0x83, 0xf0, 0x87, 0xe9, 0xfc, 0x45, 0x2b, 0x7e, 0xbb, 0xf7, ++ 0xa9, 0x00, 0x90, 0x66, 0xc5, 0x13, 0xbf, 0x76, 0xa2, 0x9e, 0x39, 0xd3, ++ 0xb2, 0xd3, 0x49, 0x7e, 0xb8, 0x7a, 0xee, 0x67, 0x53, 0xed, 0x6a, 0x74, ++ 0x3f, 0x5c, 0x4f, 0xfe, 0xb7, 0x86, 0x4d, 0x51, 0xfd, 0x6f, 0x67, 0xf0, ++ 0x3f, 0x60, 0xfe, 0x6d, 0xb5, 0xca, 0xfe, 0x37, 0x56, 0xdf, 0xa7, 0x57, ++ 0xe7, 0xe0, 0x2b, 0x1e, 0xfb, 0xf4, 0x41, 0x3c, 0x17, 0x3a, 0xbb, 0xe7, ++ 0xc3, 0x07, 0x11, 0xef, 0x95, 0x5f, 0x7f, 0xfc, 0xe0, 0x4f, 0xd1, 0x3e, ++ 0xd9, 0x67, 0x73, 0xe1, 0x7a, 0x57, 0xf5, 0xe8, 0x51, 0xf2, 0xab, 0x6b, ++ 0xed, 0x9e, 0x12, 0xf3, 0xaa, 0xed, 0x91, 0x5f, 0x3f, 0xfc, 0x00, 0xcc, ++ 0xbf, 0xb6, 0x37, 0x2c, 0x74, 0xff, 0xaa, 0x6d, 0xef, 0xfb, 0x03, 0xdc, ++ 0x30, 0xce, 0xb6, 0xdd, 0x5f, 0xa4, 0xa2, 0xff, 0x72, 0xf5, 0xde, 0xa9, ++ 0xb4, 0x6f, 0x59, 0xfd, 0xe4, 0xe4, 0xb4, 0xf3, 0xdd, 0x23, 0x41, 0xb9, ++ 0x0c, 0xf6, 0xe2, 0x3c, 0x44, 0xcf, 0x87, 0x03, 0x8d, 0x46, 0x86, 0xef, ++ 0x20, 0xcf, 0x1d, 0xb3, 0x90, 0x9d, 0x11, 0xf6, 0xa3, 0x36, 0x54, 0x70, ++ 0xbf, 0xb4, 0x5b, 0xf8, 0x4f, 0x77, 0x45, 0x3f, 0x77, 0xd2, 0xfc, 0x7e, ++ 0x95, 0x8d, 0xd7, 0x5c, 0x7d, 0x29, 0xae, 0x7b, 0x8d, 0x26, 0x8f, 0x9b, ++ 0xbe, 0x0b, 0x3f, 0x60, 0x4f, 0x7e, 0xd3, 0x57, 0x81, 0x9f, 0x23, 0x7a, ++ 0xc1, 0xb7, 0x5d, 0xc2, 0x2f, 0xae, 0xe3, 0xdb, 0x39, 0xfc, 0x0f, 0xe0, ++ 0xcf, 0x9f, 0xac, 0xb2, 0xbf, 0xf9, 0xd3, 0xc6, 0xa5, 0xbf, 0x7a, 0x00, ++ 0xcb, 0x1a, 0xfb, 0xc4, 0xf4, 0x9b, 0x86, 0x7a, 0x41, 0x2f, 0xed, 0x5c, ++ 0x6b, 0x9b, 0xd5, 0xfb, 0x8e, 0x15, 0xe7, 0xc3, 0x9e, 0xdf, 0x90, 0x7f, ++ 0x1a, 0xf9, 0x05, 0x36, 0x37, 0x6b, 0x7b, 0xec, 0xd3, 0x01, 0xe8, 0x6f, ++ 0x38, 0x6d, 0xea, 0xb8, 0x91, 0xee, 0x5f, 0xec, 0xb5, 0xd0, 0x3d, 0xa1, ++ 0xf2, 0xbd, 0xaf, 0xd3, 0xfc, 0x68, 0x7b, 0xf2, 0x08, 0x9d, 0x17, 0x31, ++ 0x71, 0xae, 0xd4, 0xc6, 0xc2, 0x7f, 0xfc, 0x1c, 0x40, 0xec, 0x65, 0xaa, ++ 0x76, 0x38, 0xb8, 0xbf, 0x55, 0xd0, 0x1d, 0xfd, 0xb1, 0x6e, 0x27, 0x7d, ++ 0x17, 0x7e, 0x57, 0x2e, 0xb7, 0x9a, 0x3f, 0x36, 0x96, 0x1f, 0xb6, 0x8f, ++ 0x4d, 0xdc, 0x03, 0x17, 0xe7, 0x6c, 0x15, 0x3b, 0xde, 0x32, 0x33, 0x9d, ++ 0x5f, 0x5b, 0x19, 0x8b, 0x7c, 0x3a, 0x2e, 0x9d, 0x0b, 0x6a, 0xe3, 0xd6, ++ 0xc3, 0x73, 0x21, 0x1d, 0x2e, 0x89, 0x3c, 0x4f, 0x88, 0xe5, 0xe7, 0x16, ++ 0x7a, 0x34, 0xcc, 0x27, 0x7e, 0x8e, 0xd0, 0xb6, 0x4d, 0x9c, 0x2f, 0x84, ++ 0xcf, 0x0d, 0x18, 0xeb, 0x97, 0x87, 0xf7, 0xdf, 0xf9, 0x79, 0x77, 0x55, ++ 0x50, 0x79, 0x9d, 0x45, 0x99, 0x8f, 0xda, 0x79, 0x82, 0xd3, 0xa6, 0x9b, ++ 0x8f, 0xc1, 0xde, 0x9d, 0x23, 0xf4, 0x8c, 0xef, 0x77, 0xa3, 0x87, 0x62, ++ 0xe3, 0xfb, 0x56, 0x8d, 0x2e, 0x67, 0xbf, 0x8a, 0xae, 0x8f, 0x87, 0xd8, ++ 0x14, 0xf1, 0xfe, 0xc0, 0x97, 0x6b, 0x8b, 0x58, 0x77, 0x16, 0x88, 0xf5, ++ 0xa4, 0x12, 0xe8, 0xc5, 0xdf, 0x93, 0x71, 0x7c, 0xcf, 0x8a, 0xfd, 0xdd, ++ 0xd9, 0x47, 0x8d, 0x41, 0xdc, 0x07, 0x6f, 0x68, 0x38, 0x40, 0x7a, 0x55, ++ 0x3f, 0xaf, 0x2b, 0x59, 0xf4, 0xf8, 0x21, 0xe3, 0x6d, 0x5c, 0x9f, 0x54, ++ 0x36, 0xed, 0x1f, 0x8e, 0xfa, 0xe7, 0xec, 0xb3, 0x4f, 0x93, 0xdc, 0x55, ++ 0xee, 0x3a, 0x6e, 0x0e, 0x00, 0x9c, 0x83, 0xf5, 0x4f, 0x98, 0x5b, 0x87, ++ 0x76, 0xc9, 0x39, 0xea, 0xeb, 0x60, 0x84, 0xbe, 0x3e, 0xfb, 0xf8, 0xfe, ++ 0xe1, 0xfc, 0x9c, 0x83, 0xef, 0x23, 0xf5, 0xf0, 0xaf, 0x10, 0xf0, 0xab, ++ 0x9a, 0x65, 0xf8, 0x55, 0xbb, 0x3e, 0x92, 0xe0, 0xaf, 0x08, 0x34, 0x98, ++ 0x5d, 0xf6, 0x9e, 0xfb, 0x39, 0xa3, 0x7a, 0xe7, 0xe2, 0x78, 0xcf, 0xb4, ++ 0x98, 0x28, 0x2e, 0xca, 0x99, 0x06, 0x63, 0x61, 0xb4, 0x78, 0x25, 0x43, ++ 0x31, 0x90, 0x54, 0x4a, 0x17, 0x9d, 0x36, 0x38, 0xf8, 0xfb, 0x38, 0x63, ++ 0x92, 0x99, 0xec, 0xc8, 0xd5, 0x8e, 0xb1, 0xc7, 0x12, 0x92, 0x31, 0x35, ++ 0xbb, 0x71, 0x1f, 0xbd, 0x7e, 0x2d, 0xbf, 0x0f, 0xb9, 0xfe, 0x67, 0x9e, ++ 0x74, 0xe4, 0xcb, 0xfa, 0xc4, 0x39, 0x74, 0x0e, 0x54, 0xab, 0xa3, 0xa3, ++ 0x2b, 0xd9, 0x55, 0x80, 0xfb, 0x6b, 0xd7, 0x94, 0xa2, 0xd1, 0x28, 0x56, ++ 0x7a, 0x3d, 0x90, 0xe8, 0x35, 0x48, 0x78, 0xaf, 0x76, 0x14, 0xa6, 0xe1, ++ 0x7b, 0xee, 0x5b, 0x85, 0x3d, 0xc2, 0x54, 0x0f, 0xbd, 0xdf, 0x33, 0x3a, ++ 0xa7, 0x15, 0xe2, 0x38, 0x8c, 0x2e, 0x83, 0xcb, 0x16, 0x75, 0x1d, 0xe5, ++ 0xf0, 0x4c, 0xf6, 0x22, 0x8a, 0x17, 0x61, 0x72, 0xc9, 0xef, 0xe9, 0xbe, ++ 0xf7, 0xf8, 0x0f, 0xee, 0x7e, 0x72, 0xfc, 0x87, 0x40, 0xbf, 0x7f, 0x34, ++ 0xfe, 0x03, 0xa3, 0x38, 0x18, 0xff, 0xef, 0xe3, 0x3f, 0x04, 0xb0, 0x9f, ++ 0x7f, 0x81, 0xf8, 0x0f, 0x21, 0xf2, 0xdb, 0x68, 0xf1, 0x1f, 0x92, 0xbf, ++ 0xe7, 0xf8, 0x0f, 0x6b, 0x99, 0x1c, 0xff, 0x41, 0xf0, 0x33, 0x1c, 0xff, ++ 0x41, 0xf0, 0xf3, 0x7f, 0xe3, 0x3f, 0xfc, 0xff, 0x15, 0xff, 0xc1, 0x18, ++ 0xf7, 0xf7, 0x29, 0x18, 0x9f, 0x41, 0x8b, 0xff, 0x90, 0x12, 0x67, 0x9e, ++ 0x1a, 0x19, 0xff, 0xe1, 0xc2, 0xb8, 0x84, 0xa9, 0x91, 0xf1, 0x1f, 0xc6, ++ 0xc5, 0xa5, 0x4f, 0x8d, 0x8c, 0xff, 0xf0, 0x83, 0xb8, 0xac, 0xa9, 0x91, ++ 0xf1, 0x1f, 0xe6, 0xc7, 0x5d, 0x34, 0x35, 0x32, 0xfe, 0x43, 0x55, 0xdc, ++ 0xa8, 0xa9, 0x91, 0xf1, 0x1f, 0xd6, 0xc6, 0x4d, 0xa4, 0xbc, 0x16, 0xff, ++ 0xe1, 0xee, 0xb8, 0xa9, 0x53, 0xe5, 0xf8, 0x0f, 0x33, 0xa7, 0x4e, 0x81, ++ 0x7c, 0x5b, 0x9c, 0xef, 0xef, 0xb8, 0x5e, 0xc5, 0x8a, 0xff, 0xf0, 0x1e, ++ 0x4e, 0x96, 0x31, 0x3d, 0xc7, 0x7f, 0x00, 0x38, 0xe6, 0xb8, 0x31, 0xb1, ++ 0xe3, 0x3f, 0xe8, 0xe1, 0xc4, 0x8a, 0xff, 0x00, 0x70, 0x12, 0x08, 0x4e, ++ 0x8c, 0xf8, 0x0f, 0xdd, 0xf0, 0x89, 0x11, 0xff, 0x01, 0xe0, 0xa4, 0x13, ++ 0x9c, 0x18, 0xf1, 0x1f, 0xba, 0xe1, 0x13, 0x23, 0xfe, 0x03, 0xc0, 0xc9, ++ 0x22, 0x38, 0x31, 0xe2, 0x3f, 0xe8, 0xe1, 0xc4, 0x8a, 0xff, 0x00, 0x70, ++ 0x2e, 0x8a, 0x4b, 0x89, 0x1d, 0xff, 0x41, 0x0f, 0x27, 0x56, 0xfc, 0x07, ++ 0x80, 0x33, 0x8a, 0xf0, 0x89, 0x11, 0xff, 0xa1, 0x1b, 0x3e, 0x31, 0xe2, ++ 0x3f, 0x00, 0x9c, 0x89, 0x04, 0x27, 0x46, 0xfc, 0x87, 0x6e, 0xf8, 0xc4, ++ 0x88, 0xff, 0x00, 0x70, 0xa6, 0xd2, 0xb8, 0x62, 0xc4, 0x7f, 0xd0, 0xc3, ++ 0x89, 0x15, 0xff, 0x01, 0xe0, 0xcc, 0x24, 0x7c, 0x62, 0xc4, 0x7f, 0xd0, ++ 0xc3, 0x89, 0x15, 0xff, 0x01, 0xe0, 0xcc, 0x25, 0x7c, 0x62, 0xc4, 0x7f, ++ 0xe8, 0x86, 0x4f, 0x8c, 0xf8, 0x0f, 0x00, 0xc7, 0x47, 0xf8, 0xc4, 0x88, ++ 0xff, 0xd0, 0x0d, 0x9f, 0x18, 0xf1, 0x1f, 0x00, 0xce, 0x72, 0x82, 0x13, ++ 0x23, 0xfe, 0x83, 0x1e, 0x4e, 0xac, 0xf8, 0x0f, 0x00, 0x67, 0x15, 0xc1, ++ 0x89, 0x11, 0xff, 0x41, 0x0f, 0x27, 0x56, 0xfc, 0x07, 0x80, 0xf3, 0x53, ++ 0x82, 0x13, 0x23, 0xfe, 0x43, 0x37, 0x7c, 0x62, 0xc4, 0x7f, 0x00, 0x38, ++ 0xb7, 0x12, 0x9c, 0x18, 0xf1, 0x1f, 0xba, 0xe1, 0x13, 0x23, 0xfe, 0x03, ++ 0xc0, 0xb9, 0x83, 0xe0, 0xc4, 0x88, 0xff, 0xa0, 0x87, 0x13, 0x2b, 0xfe, ++ 0x03, 0xc0, 0xb9, 0x97, 0xe0, 0xc4, 0x88, 0xff, 0xa0, 0x87, 0x13, 0x2b, ++ 0xfe, 0x03, 0xc0, 0xf9, 0x15, 0xc1, 0x89, 0x11, 0xff, 0xa1, 0x1b, 0x3e, ++ 0x31, 0xe2, 0x3f, 0x00, 0x9c, 0x7a, 0x92, 0xc3, 0x18, 0xf1, 0x1f, 0xba, ++ 0xe1, 0xf3, 0x5d, 0xe3, 0x3f, 0xd8, 0x42, 0x03, 0x95, 0x1c, 0x8a, 0xff, ++ 0x40, 0x71, 0x22, 0xc3, 0xf1, 0x1f, 0x92, 0xbf, 0x75, 0xfc, 0x87, 0x66, ++ 0xc4, 0xf7, 0x7f, 0xe3, 0x3f, 0xfc, 0xcf, 0x8c, 0xff, 0x70, 0xb3, 0xdd, ++ 0xf7, 0x75, 0x1c, 0xf9, 0x41, 0xbf, 0x5b, 0xfc, 0x07, 0x5b, 0xfc, 0xb7, ++ 0x8b, 0xff, 0x70, 0xb3, 0xbd, 0x28, 0x3e, 0x1e, 0xf7, 0x97, 0xdf, 0x32, ++ 0xfe, 0x43, 0x6a, 0xfc, 0xb7, 0x8b, 0xff, 0x00, 0xfd, 0xa4, 0xc7, 0x8f, ++ 0x89, 0xdd, 0x4f, 0xac, 0xf8, 0x0f, 0x39, 0xba, 0x7e, 0x7a, 0x8a, 0xff, ++ 0x00, 0xfd, 0x0c, 0x3a, 0xef, 0x78, 0x62, 0xc4, 0x7f, 0xf0, 0xe8, 0xe8, ++ 0xf6, 0x7d, 0xc5, 0x7f, 0xf8, 0x22, 0xee, 0xfc, 0xf1, 0x1f, 0xfe, 0xe5, ++ 0xe2, 0x2c, 0xc0, 0x36, 0x05, 0xcf, 0x7f, 0x8a, 0x49, 0x14, 0xd9, 0xbf, ++ 0x4c, 0xdc, 0x85, 0x6b, 0xe3, 0xff, 0xc9, 0x71, 0x17, 0xc8, 0x58, 0xf8, ++ 0x57, 0x8a, 0xbb, 0xa0, 0xbd, 0xdf, 0x6f, 0x30, 0xe1, 0x7a, 0xf5, 0xa6, ++ 0xe0, 0xfb, 0x6b, 0x42, 0x2e, 0xde, 0x12, 0xf1, 0x17, 0x8e, 0xc5, 0x8c, ++ 0xbf, 0x10, 0xbc, 0x8a, 0xfc, 0xa2, 0xcb, 0xe5, 0xf8, 0x0b, 0xd3, 0x05, ++ 0x1f, 0xe7, 0xf9, 0x64, 0x79, 0x98, 0xce, 0xf8, 0x79, 0xc3, 0xf4, 0x29, ++ 0x59, 0x3c, 0x5e, 0x66, 0x99, 0x2e, 0xfe, 0x42, 0xae, 0x7c, 0x7e, 0x3d, ++ 0xc3, 0x77, 0x64, 0x0a, 0x80, 0x63, 0x57, 0x79, 0xe4, 0x71, 0x1c, 0x11, ++ 0xf2, 0x30, 0xb3, 0xe4, 0xa3, 0xe7, 0x90, 0x3d, 0x57, 0x8f, 0x8d, 0x1e, ++ 0x7f, 0x61, 0x96, 0xe0, 0x47, 0xb1, 0x8e, 0x2e, 0xd3, 0x05, 0xdf, 0x8a, ++ 0x45, 0x7a, 0x3d, 0x3e, 0x49, 0x01, 0x79, 0x9e, 0x51, 0x76, 0x44, 0x45, ++ 0xba, 0xce, 0x74, 0xb7, 0xaa, 0xe4, 0xd7, 0xfe, 0x81, 0xc6, 0x3f, 0xb7, ++ 0xc4, 0xbf, 0xd9, 0x02, 0xae, 0x1e, 0xdf, 0x59, 0x82, 0x7f, 0xb3, 0xae, ++ 0xe4, 0xfc, 0xd3, 0xe3, 0xfd, 0x2a, 0xf2, 0xcf, 0x09, 0x69, 0xd9, 0x28, ++ 0xe2, 0x9f, 0x1e, 0x6f, 0x3d, 0x9e, 0x7a, 0xfe, 0xb3, 0x48, 0x7e, 0x47, ++ 0xc4, 0xcd, 0x28, 0x60, 0x72, 0xdc, 0x85, 0xc9, 0x56, 0x39, 0xee, 0xc2, ++ 0x54, 0x97, 0x1c, 0x77, 0xe1, 0x8a, 0x74, 0x39, 0xee, 0xc2, 0x95, 0x6e, ++ 0x39, 0xee, 0xc2, 0x0f, 0x72, 0xe5, 0xb8, 0x0b, 0x57, 0x79, 0xe4, 0xb8, ++ 0x0b, 0x57, 0x8f, 0x95, 0xe3, 0x2e, 0x14, 0x7b, 0xd7, 0xea, 0xe2, 0x3e, ++ 0x6c, 0xd2, 0xc5, 0x7d, 0xb8, 0x4b, 0x17, 0xf7, 0xe1, 0x7e, 0x5d, 0xdc, ++ 0x87, 0x6d, 0xba, 0xb8, 0x0f, 0x8f, 0xe8, 0xe2, 0x3e, 0xec, 0xd6, 0xc5, ++ 0x7d, 0x78, 0x5a, 0x17, 0xf7, 0x61, 0xbf, 0x94, 0x5f, 0x5c, 0x73, 0x58, ++ 0xaa, 0xbf, 0xb4, 0xf6, 0x88, 0x94, 0x5f, 0x56, 0xf7, 0x86, 0x54, 0x7f, ++ 0x79, 0xf0, 0xb8, 0x54, 0xbe, 0xa2, 0xfe, 0x03, 0xa9, 0xbc, 0xa2, 0xe1, ++ 0x23, 0x29, 0x5f, 0xd5, 0xf4, 0x85, 0x54, 0xbf, 0xb7, 0x71, 0x1f, 0x5e, ++ 0x15, 0xef, 0x81, 0x5f, 0x13, 0xef, 0x81, 0x8f, 0x89, 0xf7, 0xc0, 0x6f, ++ 0xc6, 0x88, 0xfb, 0xf0, 0xd7, 0x9f, 0x7f, 0x71, 0x5b, 0xe4, 0x7b, 0xfc, ++ 0x2f, 0x7f, 0xfe, 0xcd, 0x6d, 0xf8, 0x1e, 0xdf, 0x20, 0xde, 0xc1, 0xc6, ++ 0x8a, 0xfb, 0x10, 0x2e, 0x8f, 0x11, 0xf7, 0xa1, 0xab, 0xfd, 0xb7, 0x8f, ++ 0xfb, 0x90, 0x92, 0xfc, 0xcf, 0x7f, 0x87, 0x9f, 0x63, 0xe7, 0xe7, 0x9b, ++ 0x13, 0xe2, 0x27, 0xe5, 0xd8, 0x53, 0xbe, 0xfb, 0x3b, 0xfc, 0x6b, 0x8b, ++ 0xe4, 0xf7, 0xcc, 0x73, 0x4b, 0xe4, 0xf7, 0xcc, 0x39, 0x76, 0xae, 0xcf, ++ 0xe7, 0xf9, 0xe4, 0x77, 0xcd, 0xd7, 0x97, 0xc9, 0xef, 0x9a, 0xcb, 0x6c, ++ 0xbe, 0x6c, 0xc4, 0x43, 0x1f, 0xf7, 0x61, 0x42, 0xbc, 0x37, 0xc7, 0x8e, ++ 0xfa, 0x52, 0xbc, 0xcf, 0x0f, 0xe1, 0xfb, 0x54, 0x58, 0x1b, 0x9f, 0xc5, ++ 0xf7, 0xa9, 0x90, 0x3e, 0x87, 0x71, 0x1f, 0x20, 0x3d, 0x88, 0x71, 0x1f, ++ 0x20, 0x3d, 0x84, 0x71, 0x1f, 0x20, 0xfd, 0x3d, 0xc6, 0x7d, 0x80, 0xf4, ++ 0x25, 0x8c, 0xfb, 0x00, 0xe9, 0xcb, 0x18, 0xf7, 0x41, 0xc5, 0xb8, 0x11, ++ 0x01, 0x11, 0x37, 0xa2, 0x46, 0xc4, 0x8d, 0xa8, 0x15, 0x71, 0x23, 0xea, ++ 0x44, 0xdc, 0x88, 0xa0, 0x88, 0x1b, 0x51, 0x2f, 0xe2, 0x46, 0x34, 0x88, ++ 0xb8, 0x11, 0x4d, 0x22, 0x6e, 0x44, 0x88, 0xe0, 0x9c, 0xf0, 0x1f, 0xa2, ++ 0xf4, 0xa4, 0xbf, 0x85, 0xd2, 0x53, 0xfe, 0x63, 0x94, 0x9e, 0xf6, 0xb7, ++ 0x52, 0x7a, 0xc6, 0x7f, 0x9a, 0xd2, 0xb3, 0xfe, 0x0e, 0x4a, 0xdb, 0xfc, ++ 0x9f, 0x53, 0xda, 0xdb, 0xb8, 0x11, 0x9a, 0x5c, 0xfe, 0x19, 0xed, 0x06, ++ 0x33, 0xf6, 0xcf, 0xe5, 0x58, 0x93, 0xd3, 0x19, 0xf6, 0x81, 0x1b, 0x22, ++ 0xe5, 0xb4, 0xc8, 0x7e, 0xd1, 0x06, 0x94, 0xd3, 0x58, 0xf1, 0x22, 0xe6, ++ 0x22, 0x4d, 0x53, 0x62, 0xc7, 0x8b, 0x08, 0x97, 0xc7, 0x88, 0x17, 0xd1, ++ 0xd5, 0x3e, 0x76, 0xbc, 0x88, 0xb4, 0xd1, 0xdf, 0x5f, 0xbc, 0x88, 0x7f, ++ 0x8b, 0xe7, 0xf2, 0xfa, 0x8f, 0xc6, 0x8b, 0x98, 0x5f, 0x2d, 0xc7, 0x33, ++ 0x58, 0xb0, 0xe6, 0xfc, 0xf1, 0x22, 0xca, 0x6c, 0x45, 0xab, 0x51, 0x2e, ++ 0x35, 0x79, 0xfc, 0xb7, 0x78, 0x7e, 0x5e, 0xd5, 0x53, 0xbc, 0x88, 0x6d, ++ 0x76, 0x45, 0xac, 0xd7, 0x40, 0x17, 0xb4, 0xbb, 0x80, 0x2e, 0xb4, 0x5e, ++ 0xf7, 0xf0, 0xde, 0xfe, 0x39, 0xc7, 0xc3, 0xb9, 0xb8, 0x9f, 0xe8, 0xcc, ++ 0xbd, 0xe8, 0xbc, 0x71, 0x0e, 0xf4, 0x72, 0x11, 0x9b, 0xde, 0x3c, 0xae, ++ 0xc1, 0x75, 0xdf, 0x73, 0x9c, 0x88, 0x9e, 0xe8, 0xaa, 0xd5, 0x7f, 0xb3, ++ 0x9c, 0xc7, 0x2f, 0xf8, 0xb7, 0xf8, 0xf3, 0xc7, 0x2f, 0xe8, 0x16, 0x27, ++ 0xa2, 0xa7, 0xf8, 0x02, 0x83, 0x3e, 0x23, 0x3d, 0xd9, 0xdb, 0x38, 0x11, ++ 0x3d, 0xad, 0x0b, 0x3d, 0xd1, 0x73, 0xd6, 0xf7, 0x1c, 0x27, 0xa2, 0x27, ++ 0xbd, 0xda, 0x93, 0x3e, 0xfd, 0xe3, 0x74, 0x4e, 0xe7, 0x09, 0xf1, 0xe7, ++ 0x8f, 0xc7, 0x11, 0x8e, 0x0b, 0x67, 0x6d, 0x39, 0x48, 0x8d, 0x5d, 0x5e, ++ 0x9a, 0xda, 0xaa, 0x78, 0x07, 0x5e, 0x30, 0xdb, 0x45, 0xfe, 0x93, 0xf6, ++ 0x5d, 0xe2, 0xde, 0x98, 0x97, 0xb9, 0x5d, 0xa9, 0xfc, 0x9d, 0x3a, 0xda, ++ 0x9b, 0xed, 0x7b, 0x12, 0x86, 0x33, 0x7a, 0xbf, 0xee, 0x62, 0x5e, 0xe0, ++ 0x4f, 0xbc, 0xf8, 0xae, 0xec, 0xda, 0xbf, 0x1f, 0xcf, 0xd3, 0x6f, 0x75, ++ 0x32, 0x6f, 0x62, 0x12, 0xc5, 0x83, 0x77, 0x1b, 0x73, 0x70, 0x1f, 0x36, ++ 0xd2, 0x8a, 0xfe, 0x94, 0x8a, 0xc6, 0x8f, 0x5e, 0xfe, 0x1d, 0xc0, 0xb5, ++ 0x35, 0x1b, 0xe9, 0x3e, 0x59, 0x3b, 0xe0, 0xd0, 0x42, 0x76, 0x9f, 0x37, ++ 0x11, 0xf9, 0x16, 0xcf, 0x6e, 0xa7, 0x7d, 0x3a, 0x9e, 0x71, 0x7d, 0xd3, ++ 0x27, 0xf2, 0x3d, 0xb3, 0xee, 0xf7, 0x1b, 0xb0, 0x4a, 0xc4, 0xf9, 0xcd, ++ 0x54, 0xa3, 0x9d, 0xf6, 0x4d, 0x9d, 0x5b, 0xf9, 0x3d, 0x4f, 0x23, 0xbb, ++ 0xe8, 0xbe, 0x89, 0xc9, 0x74, 0x9f, 0x9a, 0x05, 0xdd, 0xc4, 0x3f, 0xb2, ++ 0x53, 0x57, 0x08, 0x3c, 0x3b, 0x31, 0xc5, 0xfa, 0x3e, 0x2b, 0xd9, 0x8f, ++ 0xcb, 0x0e, 0x3f, 0x91, 0x1f, 0x62, 0xfc, 0xbc, 0x32, 0xd2, 0x6f, 0xd0, ++ 0xa7, 0x50, 0xf6, 0xd3, 0xd4, 0xd9, 0x9c, 0xc3, 0xf1, 0x5d, 0x25, 0x0b, ++ 0x78, 0x5b, 0xd0, 0xfe, 0x5e, 0x22, 0xe0, 0xa5, 0x14, 0xc9, 0xfe, 0x9b, ++ 0x0f, 0x17, 0x15, 0x1e, 0xc2, 0x73, 0xfa, 0x25, 0xbe, 0x52, 0xba, 0x87, ++ 0x90, 0x56, 0x22, 0xfb, 0x73, 0x98, 0x78, 0x37, 0x8e, 0xdb, 0xb1, 0xf0, ++ 0x7d, 0x39, 0xc0, 0xa7, 0xb4, 0x49, 0x61, 0x0f, 0x28, 0xdd, 0xdf, 0x91, ++ 0x97, 0x35, 0xdf, 0xb5, 0x01, 0xf7, 0x39, 0xcb, 0x83, 0x7a, 0xfb, 0x9b, ++ 0xe5, 0xa2, 0x9c, 0x95, 0xb3, 0x38, 0x0f, 0xee, 0x7b, 0x57, 0xd4, 0xcb, ++ 0xe5, 0x0e, 0x87, 0xb8, 0xcf, 0x61, 0x67, 0xf6, 0x5e, 0xd1, 0xad, 0x75, ++ 0xf0, 0x7d, 0x13, 0x47, 0x9f, 0x97, 0x6e, 0x9e, 0x10, 0xd6, 0xdf, 0xe5, ++ 0xa0, 0xfb, 0xb0, 0xcb, 0x0e, 0x2f, 0x36, 0x23, 0xb3, 0x2c, 0xe9, 0x32, ++ 0xdd, 0x6c, 0x6e, 0x99, 0x6e, 0xf1, 0xb9, 0x32, 0x7d, 0xf4, 0xf4, 0x73, ++ 0x78, 0x64, 0xfa, 0xe8, 0xe9, 0x97, 0x30, 0x56, 0xf6, 0x7f, 0x69, 0xf4, ++ 0xd3, 0xee, 0x1b, 0xaa, 0x4c, 0xdc, 0x17, 0x0d, 0xf2, 0x7b, 0xa4, 0xdd, ++ 0xde, 0xe1, 0x37, 0x6d, 0x23, 0x3c, 0xf5, 0xf4, 0xd3, 0xd3, 0x6b, 0x94, ++ 0x43, 0xdc, 0x93, 0xe8, 0xa2, 0x57, 0x91, 0x35, 0x95, 0x54, 0x3e, 0xe1, ++ 0x99, 0xa1, 0x86, 0x48, 0xbe, 0xf5, 0xf3, 0x21, 0xd3, 0x1e, 0x52, 0xf0, ++ 0xbf, 0xfb, 0x27, 0x07, 0xd7, 0x52, 0x2b, 0x8f, 0x43, 0x45, 0xbd, 0x95, ++ 0xce, 0x41, 0x33, 0x65, 0x09, 0x6f, 0x17, 0x8f, 0xf3, 0x01, 0xe3, 0xca, ++ 0x32, 0x0f, 0xcd, 0x07, 0xdc, 0xd1, 0xa3, 0x7f, 0x37, 0x9e, 0xfd, 0x59, ++ 0xc8, 0xfd, 0xbb, 0xec, 0x1b, 0x48, 0x6f, 0x2a, 0x7e, 0xee, 0xf8, 0x22, ++ 0x28, 0xdd, 0x8a, 0xf2, 0x36, 0x82, 0xff, 0xfe, 0x02, 0xf9, 0xab, 0xb4, ++ 0xdf, 0x4d, 0x60, 0x1e, 0x17, 0xee, 0xa3, 0x1a, 0xfc, 0x56, 0xf7, 0x12, ++ 0x15, 0xcf, 0x05, 0x99, 0x7b, 0xc9, 0x40, 0x3c, 0x0f, 0x74, 0x51, 0x7a, ++ 0xa7, 0x78, 0xf7, 0xdb, 0x3e, 0x94, 0xd1, 0xbe, 0xbf, 0x21, 0xf4, 0x49, ++ 0x2a, 0x9e, 0xa3, 0xdd, 0x99, 0xd7, 0x31, 0x13, 0xfd, 0x0f, 0x55, 0x4b, ++ 0x59, 0x11, 0xae, 0x5f, 0x3f, 0x72, 0xf2, 0x77, 0x17, 0x9b, 0x44, 0x3a, ++ 0xc2, 0xc9, 0xfd, 0x33, 0x9b, 0x8b, 0x0c, 0xcc, 0x3b, 0x1a, 0x7f, 0x87, ++ 0xc7, 0x18, 0x54, 0xd0, 0xef, 0xea, 0xf2, 0x1e, 0xbe, 0x1c, 0xed, 0xd1, ++ 0x66, 0x93, 0x9b, 0xde, 0x11, 0xbb, 0x3a, 0x5e, 0xbe, 0x9e, 0xca, 0x47, ++ 0xd1, 0xfb, 0xe8, 0x0c, 0x43, 0xed, 0x48, 0xc4, 0x07, 0xea, 0xd3, 0xfb, ++ 0xda, 0xf6, 0xe6, 0x77, 0x9d, 0x8b, 0x23, 0xf4, 0x70, 0x5b, 0xd3, 0xdd, ++ 0x43, 0xf0, 0x7e, 0xf1, 0xfd, 0x86, 0xe8, 0xef, 0x7a, 0x4b, 0x1d, 0xda, ++ 0xfb, 0x36, 0x7e, 0xbf, 0x63, 0x44, 0x57, 0x9c, 0x81, 0x52, 0xc7, 0x18, ++ 0x8a, 0x47, 0x70, 0x67, 0x36, 0xf4, 0x53, 0x59, 0xdc, 0x49, 0x7c, 0xd4, ++ 0xe4, 0x72, 0x82, 0xa0, 0xff, 0x73, 0xa5, 0xd3, 0x09, 0xbf, 0x27, 0x9b, ++ 0x15, 0x37, 0xfa, 0xeb, 0xa6, 0x19, 0x6f, 0xf8, 0xc1, 0x30, 0xc0, 0x6f, ++ 0xdc, 0x51, 0x95, 0xeb, 0x2f, 0x71, 0xaf, 0x7b, 0xb4, 0xa8, 0xff, 0x34, ++ 0xf3, 0xa4, 0x23, 0xbe, 0xe3, 0x2e, 0x65, 0x0a, 0xce, 0x9f, 0x71, 0x6f, ++ 0x30, 0x4f, 0x00, 0x49, 0x5c, 0x5d, 0x4a, 0xf7, 0xe9, 0x7e, 0xe7, 0x9c, ++ 0x76, 0x08, 0xf9, 0x35, 0xa5, 0x19, 0xe4, 0x09, 0xf5, 0xc8, 0x59, 0xbb, ++ 0x07, 0xaf, 0xca, 0x8f, 0x69, 0x91, 0xef, 0xcb, 0x25, 0x4e, 0xf1, 0x1d, ++ 0xc0, 0xfb, 0x85, 0x97, 0x1c, 0x63, 0xa4, 0xcf, 0x2e, 0x39, 0xa6, 0xea, ++ 0xef, 0xc7, 0x18, 0x71, 0xbf, 0x3f, 0xae, 0x55, 0xfe, 0x3e, 0x41, 0xb7, ++ 0xff, 0x5c, 0xa7, 0xc9, 0x9d, 0x93, 0xa5, 0xa2, 0xdc, 0x6d, 0xf9, 0xca, ++ 0x48, 0x78, 0xb5, 0x77, 0x30, 0xcf, 0x3a, 0x80, 0xdb, 0xbe, 0xa4, 0x2f, ++ 0x9d, 0xdb, 0xb6, 0x7f, 0xc2, 0xc8, 0x4e, 0x6c, 0xff, 0xca, 0x58, 0x18, ++ 0xed, 0x7e, 0xc9, 0xdd, 0x0e, 0xee, 0xf7, 0xba, 0xdf, 0xcc, 0x48, 0x7f, ++ 0xdf, 0x5f, 0x6a, 0xa7, 0x77, 0x0e, 0xcf, 0x96, 0x96, 0x5f, 0x80, 0xf6, ++ 0xc5, 0x67, 0x3f, 0xf1, 0x5d, 0x10, 0xcd, 0x4f, 0x19, 0x61, 0xa7, 0x25, ++ 0xf0, 0xf7, 0xe7, 0xde, 0x04, 0x36, 0x16, 0xe5, 0xf0, 0x56, 0x85, 0xd3, ++ 0xbb, 0x36, 0xa3, 0x28, 0xca, 0xba, 0xa5, 0xc9, 0x9d, 0x26, 0x87, 0x9a, ++ 0xfc, 0x65, 0x94, 0xc6, 0xf9, 0xa2, 0xdd, 0xd7, 0x4c, 0x76, 0x72, 0xfb, ++ 0x68, 0x52, 0x69, 0xae, 0x62, 0x46, 0xf9, 0xd9, 0xa7, 0x30, 0xa4, 0x6b, ++ 0xdb, 0x3a, 0xc0, 0xeb, 0x3c, 0xeb, 0x76, 0x80, 0xad, 0xcb, 0x44, 0x7c, ++ 0xaa, 0x9a, 0x3e, 0xa6, 0x7b, 0x58, 0xd6, 0x66, 0x25, 0xea, 0xef, 0xf2, ++ 0x3c, 0xe1, 0x70, 0xf2, 0xfb, 0x80, 0xeb, 0x02, 0x6b, 0xf1, 0xfe, 0xc5, ++ 0xcd, 0x30, 0x89, 0x50, 0x4f, 0x65, 0x98, 0x6b, 0xb3, 0xa2, 0xc1, 0x0f, ++ 0xb0, 0x2d, 0x64, 0x97, 0x3e, 0xe0, 0x70, 0xf3, 0x77, 0x03, 0x56, 0x11, ++ 0x47, 0x48, 0xad, 0xcd, 0xc0, 0xfb, 0x08, 0x6d, 0x4d, 0x93, 0xaf, 0xdc, ++ 0x00, 0x78, 0x3e, 0x00, 0xf3, 0x01, 0xf9, 0x7b, 0xbf, 0xc9, 0x43, 0x78, ++ 0x07, 0x2a, 0x18, 0xa3, 0xfb, 0xa4, 0xc2, 0x5f, 0xd7, 0x6f, 0x26, 0xdb, ++ 0xb6, 0x39, 0xc2, 0xfe, 0xdd, 0xeb, 0x28, 0x38, 0x8c, 0x72, 0x7b, 0xd8, ++ 0xc1, 0xed, 0xc6, 0x3e, 0x3e, 0x8f, 0x82, 0x78, 0x7b, 0xfe, 0xfe, 0x57, ++ 0x27, 0xc2, 0x6f, 0xff, 0xdc, 0x42, 0xfc, 0xeb, 0x2b, 0xec, 0x4d, 0xad, ++ 0xdd, 0x49, 0x07, 0xa7, 0x4f, 0x89, 0xd3, 0x7b, 0x00, 0xdb, 0xb3, 0xb2, ++ 0x64, 0x52, 0x3e, 0x1e, 0x9f, 0xd3, 0xbd, 0xa4, 0x0f, 0xfa, 0xcd, 0x81, ++ 0xde, 0x51, 0xec, 0x2b, 0x6d, 0x5d, 0x4f, 0xf2, 0x31, 0x3a, 0x9f, 0x48, ++ 0xb2, 0x1b, 0x82, 0xa4, 0x9c, 0xbc, 0x5e, 0xb7, 0x4b, 0xba, 0xef, 0x1d, ++ 0xa0, 0x79, 0xa3, 0xcd, 0x03, 0x16, 0x52, 0x18, 0xbe, 0xd7, 0xd7, 0xf4, ++ 0x9b, 0xd2, 0xac, 0x84, 0x1c, 0x20, 0xf7, 0xa3, 0xad, 0xf6, 0x10, 0xde, ++ 0x3f, 0x4b, 0x2a, 0x83, 0x71, 0x27, 0x63, 0x3c, 0x0f, 0x2b, 0x87, 0xd7, ++ 0xa2, 0x9e, 0x95, 0xfd, 0x5a, 0x20, 0x8f, 0xf9, 0x68, 0xdc, 0x33, 0x7a, ++ 0xef, 0x8f, 0x8e, 0x54, 0x84, 0xaf, 0xe9, 0x3d, 0x4d, 0x5f, 0xde, 0x9a, ++ 0xc8, 0xf5, 0xd1, 0xad, 0x77, 0xa9, 0x14, 0x0f, 0x74, 0xab, 0xda, 0x6a, ++ 0x43, 0x7f, 0x6a, 0x96, 0xd7, 0x3d, 0x09, 0x43, 0xd3, 0x24, 0xa9, 0x6e, ++ 0xba, 0x97, 0xd2, 0xbf, 0x8c, 0xcf, 0xc3, 0xf8, 0x9c, 0x5f, 0x26, 0x86, ++ 0xed, 0x00, 0x98, 0xe4, 0x23, 0xbf, 0x36, 0x2e, 0x88, 0xf6, 0x9e, 0x29, ++ 0x03, 0xe5, 0x29, 0x05, 0xe9, 0xe5, 0xfb, 0xd0, 0x01, 0xe9, 0xf0, 0x43, ++ 0x1d, 0xcf, 0xa2, 0xb9, 0xe0, 0xb1, 0xb1, 0x3e, 0xfc, 0xfe, 0x94, 0xd0, ++ 0x13, 0xc2, 0xae, 0x99, 0x26, 0xd6, 0xbb, 0x71, 0xef, 0x19, 0xf8, 0x3b, ++ 0xca, 0xd0, 0xe5, 0x2c, 0xf2, 0x7d, 0x91, 0x5e, 0x4f, 0x80, 0xdc, 0xff, ++ 0x09, 0x7f, 0xbf, 0xe7, 0xfe, 0xf7, 0x54, 0x8a, 0x13, 0x1a, 0xd6, 0x0f, ++ 0xa5, 0xd3, 0x68, 0x7d, 0x62, 0xc6, 0xa1, 0x07, 0x50, 0xce, 0x26, 0xbc, ++ 0xc8, 0xf8, 0x71, 0x94, 0xd0, 0x0f, 0x2e, 0xf8, 0x87, 0xf4, 0xb9, 0xe4, ++ 0x25, 0xdf, 0x7a, 0x44, 0xe3, 0xbb, 0xea, 0x05, 0x3d, 0xbf, 0x59, 0xc8, ++ 0x1a, 0xce, 0xe3, 0x4f, 0xb3, 0x8d, 0x3a, 0x04, 0xf3, 0x2d, 0x72, 0x9d, ++ 0x75, 0x8a, 0xf5, 0x5e, 0xe8, 0x91, 0x9b, 0x8a, 0x07, 0xae, 0xc7, 0xf9, ++ 0xa5, 0xc9, 0xd1, 0x05, 0xb7, 0x78, 0x8c, 0xbe, 0x08, 0x3a, 0xea, 0xdb, ++ 0x87, 0xfd, 0x94, 0x8a, 0x35, 0xfc, 0xdd, 0x9d, 0x83, 0x7a, 0xe4, 0x25, ++ 0x23, 0xde, 0x0f, 0x6b, 0x2f, 0x00, 0x7e, 0x03, 0x5d, 0x9e, 0xc4, 0xf9, ++ 0x02, 0xf4, 0x4e, 0xfc, 0x24, 0x78, 0x25, 0xf2, 0x7d, 0x4b, 0xf3, 0x15, ++ 0x36, 0x94, 0xef, 0x5b, 0x43, 0x93, 0x5c, 0x33, 0xa0, 0x4d, 0xa2, 0xb5, ++ 0x88, 0x98, 0x97, 0xc8, 0xbc, 0xe4, 0xcf, 0xc9, 0x03, 0xea, 0x60, 0x9c, ++ 0x88, 0xf5, 0x24, 0x14, 0xb0, 0x5f, 0x57, 0x8b, 0xb2, 0x9c, 0x29, 0x78, ++ 0x8f, 0xab, 0x50, 0xf2, 0xf7, 0x68, 0xbf, 0x8b, 0x07, 0x03, 0x25, 0xbe, ++ 0x84, 0xf9, 0x00, 0x72, 0x1c, 0x79, 0x8f, 0x55, 0x93, 0x4f, 0xbd, 0x3c, ++ 0x6a, 0xf2, 0xbb, 0x1e, 0x37, 0x58, 0x78, 0x7e, 0x87, 0x1e, 0x73, 0x48, ++ 0x8d, 0x4a, 0x03, 0x31, 0xc8, 0xc2, 0xb6, 0xba, 0x50, 0xcf, 0x6a, 0xf6, ++ 0xe5, 0xfa, 0xb0, 0x3d, 0x97, 0x48, 0xfb, 0x8c, 0xd5, 0xc2, 0x2e, 0x5a, ++ 0x6f, 0x9f, 0x66, 0x25, 0x35, 0xb0, 0x3f, 0x99, 0xd6, 0xf3, 0xd5, 0xb8, ++ 0x3e, 0xc1, 0xf8, 0x57, 0xa7, 0x30, 0x9a, 0x07, 0xda, 0x38, 0xf4, 0xf2, ++ 0x58, 0xf5, 0xb9, 0x81, 0x05, 0x23, 0xf6, 0x07, 0x55, 0x6a, 0x07, 0xdd, ++ 0xe3, 0xab, 0xfa, 0xdc, 0xcc, 0x82, 0x7d, 0x70, 0xdc, 0xbe, 0x49, 0x38, ++ 0x6e, 0x8d, 0x2e, 0x23, 0x05, 0x5d, 0xf4, 0x74, 0xc8, 0x76, 0x8a, 0xfd, ++ 0xa6, 0xa0, 0x47, 0x6c, 0x3c, 0xf3, 0x5d, 0x78, 0x7f, 0x36, 0xd1, 0xea, ++ 0x65, 0x1b, 0x09, 0xcf, 0x49, 0x74, 0xcf, 0xb9, 0x21, 0x94, 0x67, 0xc5, ++ 0xf5, 0xf6, 0x36, 0x1d, 0x9e, 0xbd, 0xc0, 0x6f, 0x4e, 0x34, 0xfc, 0x54, ++ 0x7b, 0x0c, 0xfc, 0x44, 0xfc, 0xb6, 0x09, 0xcc, 0xf7, 0xbb, 0x56, 0x90, ++ 0xd7, 0xfc, 0x9b, 0xea, 0x32, 0xf8, 0x7a, 0xc1, 0x5e, 0x4d, 0x8f, 0xe0, ++ 0x9f, 0x7e, 0xde, 0x8c, 0x6d, 0xaa, 0x3e, 0x60, 0x8e, 0x98, 0x2f, 0x9a, ++ 0x5f, 0x57, 0x3f, 0x4f, 0x46, 0x34, 0xb3, 0x6b, 0x90, 0xee, 0xe3, 0x42, ++ 0x2a, 0xc3, 0xf3, 0xd7, 0x9e, 0xe6, 0xcb, 0x27, 0x62, 0xbc, 0x55, 0xf1, ++ 0x9c, 0x5e, 0xed, 0x73, 0x3a, 0x06, 0xa3, 0x7c, 0xee, 0x50, 0x7d, 0xd5, ++ 0x4e, 0xb2, 0x2f, 0x5a, 0x0d, 0x18, 0xf7, 0xb7, 0xfd, 0x69, 0x46, 0xf3, ++ 0xd9, 0xb3, 0xff, 0xa4, 0x93, 0xe2, 0x1b, 0xb5, 0xf4, 0xee, 0x7e, 0xba, ++ 0x66, 0x47, 0x69, 0xf6, 0x93, 0xbe, 0x9e, 0x66, 0x3f, 0x69, 0x7a, 0x57, ++ 0xbb, 0x1f, 0xbe, 0xdd, 0xe9, 0xf3, 0x63, 0xff, 0x4a, 0x13, 0xc8, 0x27, ++ 0x8c, 0x7f, 0xbd, 0x8b, 0xef, 0x8b, 0xf6, 0x3a, 0x7c, 0xeb, 0xf0, 0x7b, ++ 0x3c, 0x8c, 0x01, 0x8f, 0x92, 0x58, 0x6e, 0x28, 0x8b, 0xbf, 0x7f, 0x95, ++ 0xe5, 0x3f, 0x96, 0xbc, 0xc7, 0xeb, 0xe4, 0xb9, 0x01, 0xe8, 0x44, 0xbf, ++ 0x93, 0x05, 0xfa, 0x7f, 0x90, 0xd2, 0x1d, 0x0f, 0xad, 0xff, 0x29, 0xce, ++ 0x44, 0x7e, 0xde, 0x02, 0xb3, 0x19, 0xf5, 0x50, 0xbf, 0x7c, 0xc6, 0x3b, ++ 0xab, 0x64, 0x74, 0x7f, 0xb2, 0xdf, 0x70, 0xe6, 0xc3, 0xf5, 0xa9, 0x5f, ++ 0x1e, 0xbf, 0xf7, 0x17, 0x14, 0xeb, 0xf6, 0x36, 0xa1, 0x6f, 0xb5, 0x74, ++ 0xaf, 0xa3, 0xe8, 0x7e, 0xc4, 0xdf, 0xa4, 0xb2, 0x80, 0x25, 0xef, 0xbb, ++ 0xe3, 0x8d, 0xa8, 0xe2, 0x7d, 0xec, 0xed, 0x4e, 0xef, 0x7d, 0x28, 0x7f, ++ 0xd6, 0x42, 0x2f, 0x8d, 0x23, 0xd3, 0xc5, 0x3c, 0x68, 0x7f, 0x66, 0xaa, ++ 0x0d, 0x0a, 0xbe, 0x9b, 0x4c, 0x5a, 0xe9, 0x56, 0xf8, 0x3d, 0x6c, 0xd6, ++ 0xf5, 0x8e, 0x09, 0xe0, 0x65, 0xce, 0x70, 0x17, 0xa0, 0x9c, 0x64, 0xe2, ++ 0x3e, 0x1a, 0xeb, 0x37, 0x47, 0x8f, 0xa3, 0xf5, 0x84, 0xd3, 0x24, 0xd9, ++ 0x99, 0x1e, 0x16, 0x8e, 0x53, 0xf5, 0x04, 0xf6, 0x0b, 0x76, 0xe6, 0x41, ++ 0x33, 0xe0, 0xdd, 0x67, 0x86, 0x16, 0xf7, 0x4a, 0x3b, 0xb7, 0xf1, 0x28, ++ 0x48, 0xa7, 0x36, 0xc7, 0x1c, 0x42, 0xba, 0xed, 0x53, 0x85, 0xdb, 0xe3, ++ 0x89, 0x9c, 0x5e, 0xfa, 0xfd, 0x00, 0x12, 0x1e, 0xf1, 0x53, 0x45, 0xfe, ++ 0x36, 0x33, 0x53, 0x6d, 0x49, 0xac, 0xeb, 0x77, 0x38, 0x0d, 0x56, 0xb2, ++ 0xe3, 0xe3, 0x99, 0xa7, 0x01, 0xf5, 0xd2, 0xcb, 0xce, 0x6c, 0x71, 0x2e, ++ 0xea, 0xa9, 0xc1, 0xfc, 0xbf, 0xab, 0x1d, 0xd6, 0xc4, 0xa1, 0x5d, 0x72, ++ 0x7c, 0xe7, 0xc4, 0x59, 0x1e, 0x15, 0xaa, 0x38, 0x2f, 0xed, 0x1c, 0x8e, ++ 0x7b, 0x26, 0x90, 0xe7, 0xc3, 0x88, 0x6f, 0xdb, 0xc4, 0xce, 0xc1, 0xb7, ++ 0x12, 0x31, 0x3a, 0x06, 0x70, 0xb9, 0xf1, 0x1a, 0xa5, 0xb8, 0x38, 0x1a, ++ 0xfd, 0x9b, 0x4c, 0x12, 0xfd, 0x6d, 0xb8, 0xcf, 0x8e, 0xd4, 0x83, 0x0e, ++ 0x33, 0xed, 0x23, 0xdb, 0x94, 0x38, 0x0f, 0xce, 0xb3, 0xb6, 0xe5, 0x0a, ++ 0xc7, 0x53, 0xb1, 0x8a, 0xb8, 0x41, 0xaa, 0xbc, 0xff, 0x17, 0xfa, 0x48, ++ 0xd3, 0xaf, 0x9d, 0xce, 0x2c, 0xc2, 0x3f, 0x9e, 0x05, 0x68, 0x1f, 0xc0, ++ 0xac, 0x1e, 0x2b, 0xdd, 0x63, 0x17, 0xf8, 0x63, 0x5c, 0x45, 0xf2, 0xeb, ++ 0xec, 0x8d, 0x0f, 0x6e, 0xc7, 0xf3, 0x28, 0x5d, 0x1c, 0x45, 0x7d, 0x9c, ++ 0xc5, 0xc9, 0x8b, 0xed, 0x74, 0xef, 0x62, 0xcb, 0x5e, 0x1b, 0xed, 0x4b, ++ 0x3b, 0x8b, 0xf8, 0xf9, 0x7c, 0x67, 0xb3, 0x85, 0xf4, 0x6f, 0xac, 0x79, ++ 0x9a, 0x86, 0xca, 0xe0, 0x3c, 0xf1, 0x02, 0x81, 0x6e, 0x1d, 0x48, 0xb7, ++ 0x34, 0x53, 0x75, 0x22, 0xea, 0xbd, 0xb4, 0xf9, 0x7c, 0xfe, 0xeb, 0xe9, ++ 0xd1, 0x8e, 0x03, 0xc5, 0xfd, 0xce, 0x1f, 0x4c, 0xc1, 0x68, 0xef, 0xd5, ++ 0xb5, 0x34, 0x3d, 0xbd, 0x6f, 0x31, 0xda, 0x65, 0xe9, 0x19, 0xe9, 0x94, ++ 0x6a, 0xdf, 0xeb, 0xec, 0x6a, 0xd4, 0x7b, 0xd8, 0xc6, 0x04, 0x45, 0x8a, ++ 0xd3, 0x37, 0x04, 0x7a, 0x14, 0xfb, 0x1c, 0x63, 0x02, 0x7c, 0x3f, 0xe7, ++ 0xfb, 0xe3, 0x6b, 0x5e, 0xd6, 0x75, 0xaf, 0xbd, 0x2e, 0x8e, 0xd3, 0xaf, ++ 0xd3, 0x37, 0x3e, 0xe1, 0x61, 0x94, 0x2b, 0x10, 0x38, 0xfa, 0x3d, 0x01, ++ 0xed, 0x5c, 0x53, 0xec, 0xe7, 0xb5, 0xf8, 0x49, 0x5a, 0x3f, 0x5b, 0xfc, ++ 0xd6, 0x62, 0x0c, 0xf9, 0x59, 0xb7, 0x68, 0xba, 0x0d, 0xd7, 0x81, 0x14, ++ 0xe6, 0xbd, 0x72, 0x1e, 0x4e, 0xca, 0x2d, 0x26, 0xb6, 0x93, 0xda, 0xe5, ++ 0x4a, 0xf7, 0x5d, 0xef, 0xf5, 0x8f, 0x2c, 0xc6, 0xf7, 0xc9, 0x99, 0x09, ++ 0xfc, 0x1e, 0xed, 0x27, 0x5b, 0xa6, 0xd2, 0x7b, 0xe6, 0x54, 0xb6, 0xce, ++ 0x36, 0x18, 0xe8, 0x50, 0x5a, 0x64, 0xf0, 0xa0, 0x3f, 0xe0, 0xdc, 0xa2, ++ 0x37, 0x9d, 0x06, 0x90, 0x9f, 0x45, 0x99, 0x2d, 0xf9, 0x28, 0xa7, 0x09, ++ 0x26, 0x5f, 0x66, 0xc2, 0x18, 0x72, 0x5d, 0xd1, 0x7e, 0x63, 0x59, 0x89, ++ 0x39, 0x18, 0x02, 0x7a, 0x25, 0xd7, 0x81, 0x42, 0x20, 0x3a, 0x06, 0xae, ++ 0x24, 0x3a, 0x2e, 0x34, 0x44, 0xf5, 0x0f, 0x67, 0x27, 0xf0, 0x7d, 0xe7, ++ 0x5b, 0x62, 0x3d, 0x49, 0x4f, 0x1f, 0x50, 0xbc, 0x64, 0x54, 0x64, 0xbe, ++ 0x1f, 0xd1, 0x55, 0x93, 0x23, 0x98, 0x3f, 0x19, 0x4b, 0x46, 0x77, 0xc5, ++ 0xc3, 0x04, 0x7e, 0x5e, 0x94, 0x10, 0x65, 0x1e, 0xb4, 0x9b, 0x58, 0x13, ++ 0xbe, 0x97, 0xd0, 0xf4, 0x51, 0xb2, 0x10, 0x33, 0x4d, 0x1f, 0x6a, 0x72, ++ 0x9c, 0x8c, 0xf3, 0x03, 0xed, 0xb8, 0x22, 0xd0, 0x4f, 0xd2, 0x79, 0x1f, ++ 0x54, 0x4d, 0xed, 0xfa, 0x3d, 0x43, 0xa5, 0xf9, 0x85, 0x2f, 0xd0, 0x8e, ++ 0x75, 0x5e, 0x3a, 0x89, 0xf4, 0x0d, 0xcc, 0xdb, 0x1a, 0x92, 0xf3, 0x5c, ++ 0xae, 0x3f, 0x6d, 0xa8, 0xcf, 0x22, 0xfc, 0x56, 0xed, 0x7b, 0x5f, 0xef, ++ 0x8f, 0xef, 0x98, 0xde, 0xfe, 0xd9, 0xc7, 0x0e, 0x7c, 0xd7, 0xf2, 0x17, ++ 0xb5, 0xc3, 0x81, 0xfa, 0xeb, 0xf4, 0x2d, 0x7f, 0x72, 0x60, 0x1c, 0xb0, ++ 0xb7, 0x6f, 0xe1, 0xfb, 0xe4, 0x1b, 0x75, 0xf6, 0xff, 0x55, 0x42, 0x3e, ++ 0x82, 0x09, 0x45, 0x53, 0x90, 0xae, 0x0b, 0xfc, 0x7f, 0xcf, 0x8f, 0xb4, ++ 0xd7, 0xd8, 0x1a, 0xee, 0x7f, 0x5e, 0x1e, 0x94, 0xdf, 0xaf, 0xe2, 0xfd, ++ 0xef, 0x48, 0x3f, 0x60, 0x45, 0x83, 0xfe, 0x3e, 0x40, 0x80, 0xc7, 0x29, ++ 0x13, 0xbf, 0xcf, 0xa9, 0xe7, 0xc3, 0x3a, 0xc1, 0x87, 0xe5, 0xbb, 0xb6, ++ 0x99, 0x33, 0xdd, 0xd8, 0xbf, 0x6f, 0x0e, 0xf6, 0x7f, 0x5a, 0xec, 0x6f, ++ 0x4e, 0x37, 0x3a, 0xe8, 0x3d, 0x85, 0x86, 0xcf, 0xa2, 0x5d, 0x23, 0xcd, ++ 0x68, 0xf3, 0xff, 0xa5, 0xd9, 0x22, 0xde, 0xe9, 0xb5, 0x98, 0xb8, 0x5e, ++ 0xf6, 0xce, 0xc0, 0xf7, 0x39, 0x3e, 0x41, 0x37, 0x3d, 0x9e, 0x07, 0xf7, ++ 0xc5, 0x13, 0xbc, 0xa5, 0xf7, 0xf0, 0xf7, 0xab, 0x0b, 0xa1, 0xaf, 0x35, ++ 0xa0, 0x17, 0x7d, 0xcd, 0x3c, 0x8e, 0x92, 0x7e, 0x1c, 0x4b, 0xdf, 0x76, ++ 0x4f, 0x43, 0x3f, 0xfa, 0xd2, 0x4d, 0x0a, 0xed, 0xe3, 0xb0, 0xfe, 0x2d, ++ 0xb0, 0x4e, 0xf8, 0xd6, 0x6c, 0xa4, 0x77, 0x3c, 0xfa, 0x71, 0x2e, 0x0c, ++ 0xc8, 0xfe, 0x1c, 0x7d, 0xbc, 0x46, 0x6d, 0x3f, 0xb0, 0x4c, 0xf0, 0x7f, ++ 0x09, 0xfe, 0x1a, 0x6f, 0x4e, 0x94, 0x38, 0x8e, 0xcd, 0xfc, 0x3d, 0xdd, ++ 0x32, 0x9d, 0x7d, 0xd1, 0x79, 0x28, 0x27, 0x1e, 0xc7, 0xbf, 0x26, 0x41, ++ 0xd8, 0xd9, 0xf9, 0xec, 0x12, 0x8c, 0xdb, 0xb9, 0xe7, 0x50, 0x76, 0x42, ++ 0xb4, 0x78, 0x18, 0x5a, 0x7a, 0x56, 0x9c, 0xf7, 0xe3, 0xbd, 0x7e, 0x4c, ++ 0x4f, 0xfb, 0x19, 0xa5, 0x53, 0x12, 0xdc, 0x3c, 0x5e, 0x57, 0xf3, 0x91, ++ 0x9b, 0x51, 0xae, 0x2a, 0x9b, 0x76, 0x53, 0x7c, 0xc4, 0x7d, 0xc1, 0xf7, ++ 0xfa, 0x8c, 0x87, 0x2a, 0x05, 0xcd, 0x5f, 0x18, 0x51, 0xa8, 0x0a, 0x84, ++ 0x3d, 0x36, 0x5f, 0xd8, 0x63, 0x7b, 0x18, 0x97, 0x1b, 0xb0, 0xa3, 0x37, ++ 0xa3, 0xfc, 0x5f, 0xfe, 0xb9, 0xce, 0x8e, 0x16, 0xe3, 0xbc, 0x41, 0x93, ++ 0xfb, 0x43, 0x49, 0x24, 0x37, 0x37, 0xe0, 0xb8, 0x86, 0xe3, 0x77, 0xf5, ++ 0x93, 0x68, 0xe3, 0xba, 0x3b, 0x41, 0x7e, 0xff, 0xd5, 0xdb, 0x71, 0x69, ++ 0xe3, 0xd1, 0xc6, 0xa7, 0x95, 0x57, 0x88, 0xf7, 0xe7, 0xfa, 0x76, 0x9a, ++ 0x9c, 0x4f, 0x11, 0x72, 0xb7, 0x64, 0x47, 0xf1, 0x86, 0xbe, 0x40, 0x8a, ++ 0xf5, 0x7b, 0xdf, 0x1f, 0x20, 0xe2, 0xc8, 0x51, 0x9c, 0x2d, 0x4d, 0x8e, ++ 0xf4, 0x72, 0xb2, 0x4c, 0xf0, 0x2d, 0x2c, 0x0f, 0xcd, 0x77, 0xd0, 0xb8, ++ 0x34, 0xbe, 0x81, 0xbc, 0xa7, 0x8b, 0x77, 0x49, 0xe9, 0xe8, 0xcf, 0xe8, ++ 0x49, 0x2e, 0xf4, 0xfc, 0x6f, 0x33, 0xb5, 0x0e, 0xc0, 0xf9, 0xaa, 0xe7, ++ 0x7f, 0x5b, 0x8c, 0x73, 0x9f, 0xed, 0x09, 0xfc, 0x5c, 0x63, 0x89, 0xdb, ++ 0x3b, 0x0d, 0xfd, 0x2b, 0x60, 0x1e, 0x6e, 0x70, 0x45, 0xd8, 0x0f, 0xa7, ++ 0xd5, 0xda, 0x83, 0x3f, 0xc5, 0x79, 0xb4, 0x83, 0xcb, 0x71, 0xe4, 0xba, ++ 0x48, 0xc6, 0xd2, 0x8b, 0x26, 0x5a, 0x67, 0x57, 0x39, 0xdc, 0x69, 0x89, ++ 0x76, 0xc1, 0xb7, 0x71, 0xf8, 0x7e, 0xd1, 0x12, 0xc0, 0x7a, 0x5a, 0x3f, ++ 0xa7, 0xfc, 0x35, 0xb3, 0x06, 0xd2, 0x79, 0x63, 0xed, 0xac, 0x81, 0x03, ++ 0xe9, 0xdd, 0x06, 0xa5, 0x5a, 0x79, 0xe9, 0xfd, 0x1f, 0x3b, 0xd1, 0x3e, ++ 0x6d, 0xcf, 0x65, 0xe4, 0x5f, 0x68, 0x73, 0xc8, 0xf8, 0x1e, 0xc1, 0xc5, ++ 0x66, 0x0c, 0xa6, 0x9c, 0xfe, 0x2b, 0xd5, 0x96, 0xaf, 0xdf, 0x42, 0x1d, ++ 0xb4, 0xa3, 0x85, 0xe2, 0xb7, 0x9e, 0xfa, 0x4a, 0xf8, 0x27, 0xbe, 0xb2, ++ 0x14, 0x46, 0x1b, 0xe7, 0xd9, 0x04, 0x6e, 0x07, 0x6a, 0xf7, 0x4f, 0x6e, ++ 0x14, 0xf3, 0xe8, 0xc6, 0x66, 0xfe, 0xde, 0x6e, 0xd1, 0xd6, 0x62, 0x33, ++ 0xf9, 0x01, 0xd6, 0xc8, 0xf7, 0x35, 0x5e, 0x52, 0x5c, 0xd3, 0x32, 0xa1, ++ 0xa9, 0xaf, 0x61, 0xa4, 0x19, 0xf9, 0xac, 0xe7, 0xc7, 0x52, 0xcf, 0x15, ++ 0xf4, 0x0e, 0xbc, 0x1b, 0x5f, 0xd8, 0xed, 0xc4, 0xd7, 0xa5, 0xfa, 0x77, ++ 0x6d, 0xe2, 0x1e, 0xd3, 0x02, 0x21, 0x1f, 0x33, 0x5d, 0x6e, 0x61, 0xa7, ++ 0xf9, 0xe8, 0x1d, 0xf1, 0x92, 0x3a, 0x23, 0xd9, 0xf7, 0xcb, 0xdc, 0xd5, ++ 0xb4, 0xbf, 0x59, 0xa1, 0x46, 0x7f, 0x8f, 0x35, 0xc6, 0x65, 0x38, 0xef, ++ 0x78, 0xf4, 0xe3, 0x58, 0xd8, 0xa8, 0x90, 0xde, 0xd3, 0xe3, 0xbf, 0x6c, ++ 0xc7, 0xda, 0x0d, 0x7d, 0x19, 0x8e, 0x9f, 0x8f, 0xaf, 0xfb, 0x38, 0x42, ++ 0xfd, 0x48, 0xcf, 0x88, 0x71, 0xb2, 0xd6, 0xcb, 0xf9, 0xbb, 0x4c, 0xb1, ++ 0x6e, 0xff, 0x17, 0x47, 0x94, 0xbc, 0x57, 0x00, 0x80, 0x00, 0x00, 0x00, ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xb5, 0x7c, ++ 0x0d, 0x78, 0x54, 0xd5, 0xb5, 0xe8, 0x3e, 0x73, 0xce, 0xfc, 0x24, 0x33, ++ 0x49, 0x26, 0xff, 0x21, 0x41, 0x3c, 0x21, 0x11, 0x12, 0x12, 0xe2, 0x90, ++ 0x84, 0x00, 0x01, 0x71, 0xf2, 0x4b, 0xc4, 0x08, 0x03, 0x01, 0x82, 0x60, ++ 0x75, 0x40, 0x51, 0x84, 0x90, 0x20, 0x7a, 0x5b, 0xef, 0xab, 0xb7, 0x99, ++ 0x90, 0x68, 0x2d, 0xfa, 0x7a, 0xa3, 0x58, 0xcb, 0x6d, 0xed, 0xfd, 0x06, ++ 0x2b, 0xad, 0x0a, 0x48, 0x80, 0xa0, 0x81, 0x26, 0xe9, 0x04, 0x14, 0x03, ++ 0x04, 0x0d, 0x82, 0x0a, 0x96, 0xd6, 0x80, 0x14, 0xb1, 0x05, 0x32, 0x80, ++ 0xb5, 0x58, 0x7d, 0x8f, 0xb7, 0xd6, 0xda, 0xfb, 0x64, 0x66, 0x4e, 0x92, ++ 0x42, 0x6f, 0x5f, 0x87, 0xd6, 0x9d, 0x7d, 0xce, 0x3e, 0xfb, 0xac, 0xbd, ++ 0xfe, 0xd7, 0xda, 0x6b, 0x9f, 0x65, 0xec, 0xd9, 0x4b, 0x72, 0x0e, 0x63, ++ 0x0f, 0xb7, 0xcb, 0x8c, 0xe5, 0x33, 0x56, 0xfb, 0xac, 0xec, 0x65, 0xa9, ++ 0x8c, 0x2d, 0x63, 0xca, 0xe9, 0xbe, 0x0c, 0x46, 0xbf, 0x6b, 0xa9, 0xf8, ++ 0x5f, 0x67, 0xe5, 0x92, 0x04, 0xc6, 0xee, 0xc5, 0x3f, 0x55, 0x68, 0xdb, ++ 0x57, 0x55, 0x32, 0x78, 0xae, 0x5c, 0xae, 0x99, 0x85, 0xcf, 0xf5, 0x6f, ++ 0x90, 0x99, 0x59, 0x82, 0xeb, 0x1e, 0xef, 0x53, 0xc9, 0x71, 0xd0, 0x36, ++ 0x49, 0x8e, 0x46, 0x18, 0xc7, 0x1e, 0x37, 0x9e, 0xee, 0xb3, 0x30, 0x66, ++ 0x81, 0x7f, 0xd7, 0x46, 0xd3, 0x3c, 0x8c, 0x25, 0xe0, 0xfc, 0xfc, 0xd7, ++ 0x23, 0xb1, 0xa7, 0x52, 0x60, 0xfe, 0xb3, 0x8a, 0xff, 0xbd, 0x08, 0x78, ++ 0xee, 0x2c, 0xc0, 0xe1, 0x81, 0x79, 0x96, 0x78, 0xf8, 0x73, 0xf4, 0x7e, ++ 0xf8, 0xff, 0x32, 0xc7, 0x8c, 0x2f, 0x24, 0x78, 0xdf, 0xfd, 0xed, 0xf2, ++ 0x29, 0x73, 0x0e, 0x5e, 0x5d, 0x6d, 0x32, 0xc0, 0xf8, 0xa5, 0x2f, 0x49, ++ 0x6c, 0x1d, 0x8c, 0xbf, 0xff, 0x69, 0xdd, 0x78, 0xb1, 0x2e, 0xfd, 0x3a, ++ 0x1e, 0xda, 0xf0, 0xa3, 0xb9, 0xe9, 0x19, 0x81, 0x71, 0x0f, 0x7b, 0x9f, ++ 0x0b, 0xe9, 0xc3, 0xda, 0x54, 0x56, 0xc0, 0xd8, 0x7d, 0x02, 0x3e, 0xf6, ++ 0xea, 0x7f, 0x05, 0xee, 0x73, 0xf8, 0x4d, 0xae, 0x08, 0xc6, 0x32, 0xed, ++ 0x11, 0x71, 0x67, 0xb3, 0xa0, 0x5b, 0xc0, 0x26, 0x5d, 0x4b, 0x63, 0xac, ++ 0xce, 0x1a, 0x99, 0xc3, 0xa2, 0xa0, 0x35, 0x33, 0xc2, 0x23, 0x3b, 0x64, ++ 0xf4, 0x6e, 0x02, 0xb8, 0xd6, 0x44, 0xc0, 0x82, 0x01, 0xce, 0x35, 0x5b, ++ 0xa3, 0xbd, 0x1e, 0xc4, 0xe3, 0xea, 0x68, 0xc6, 0x46, 0xc0, 0xb8, 0xf6, ++ 0x8d, 0x26, 0xb7, 0x0d, 0xe6, 0xc4, 0xdf, 0xed, 0x8c, 0x9d, 0xab, 0x6f, ++ 0x9e, 0x9b, 0x9e, 0x0e, 0xeb, 0xaf, 0x7f, 0x7a, 0x6e, 0xba, 0xc2, 0xd8, ++ 0x2c, 0xbb, 0x9d, 0xb1, 0x89, 0x40, 0x8f, 0xb6, 0xe7, 0x68, 0x5c, 0xb7, ++ 0xe2, 0x9a, 0x64, 0x87, 0xfe, 0x2a, 0x4b, 0xdf, 0x8f, 0xef, 0x56, 0x83, ++ 0xf0, 0x38, 0x99, 0xd3, 0x63, 0x99, 0x5c, 0x69, 0x62, 0x86, 0xc0, 0x7c, ++ 0xfa, 0x76, 0x59, 0xb3, 0xf1, 0xcb, 0xbe, 0xa0, 0x75, 0x16, 0x21, 0xfc, ++ 0x56, 0xf8, 0x63, 0x12, 0xc0, 0x2f, 0xff, 0x3d, 0xf8, 0xd5, 0xc4, 0x68, ++ 0x5b, 0x00, 0x6e, 0xfd, 0xbc, 0x7f, 0xaa, 0xdf, 0x10, 0x02, 0xf7, 0x4a, ++ 0x85, 0x39, 0x5b, 0x6c, 0x81, 0xf5, 0x68, 0xe3, 0x26, 0xda, 0x0d, 0xb4, ++ 0x1e, 0xfd, 0xf3, 0x7a, 0x7a, 0x30, 0xe6, 0xa5, 0x71, 0x7a, 0xba, 0xac, ++ 0x44, 0x3a, 0x04, 0xd1, 0x17, 0xe1, 0x54, 0x00, 0xaf, 0x3d, 0x1d, 0x56, ++ 0xef, 0x5a, 0x89, 0xf8, 0x88, 0xe0, 0xf6, 0x74, 0x84, 0x11, 0xdc, 0x17, ++ 0x93, 0xd6, 0xcd, 0x3d, 0x93, 0xc7, 0xd8, 0x61, 0x7c, 0x00, 0xe0, 0xae, ++ 0x1d, 0xf1, 0x32, 0xf5, 0x5f, 0x51, 0x5c, 0x6e, 0x7b, 0x3c, 0x5e, 0xf4, ++ 0x8f, 0x72, 0x8d, 0xc7, 0x67, 0x62, 0x19, 0x9b, 0x32, 0x3c, 0xde, 0x60, ++ 0x46, 0xc6, 0x60, 0x7c, 0x2e, 0xce, 0x0f, 0xe3, 0x76, 0x85, 0x39, 0xf3, ++ 0x98, 0x8c, 0xd7, 0x5d, 0xb1, 0xc8, 0x07, 0xd3, 0x1b, 0xfa, 0xaa, 0x2c, ++ 0x40, 0xaa, 0x3a, 0xfb, 0xa4, 0x0a, 0x05, 0xde, 0x33, 0xfd, 0xb9, 0xbe, ++ 0xaa, 0x30, 0xe8, 0x3f, 0x62, 0x9f, 0xcc, 0xfb, 0x9b, 0xfa, 0x8e, 0x5a, ++ 0x1c, 0x8c, 0x35, 0xb0, 0x29, 0x15, 0xa5, 0xf0, 0xfc, 0x63, 0x70, 0x0f, ++ 0xe7, 0xbb, 0x5e, 0x9b, 0x6f, 0x76, 0x2d, 0x66, 0xc0, 0x57, 0x35, 0x80, ++ 0x53, 0x4b, 0x0c, 0xb4, 0xc7, 0xc6, 0xbc, 0x8d, 0xf2, 0x56, 0xd3, 0x5b, ++ 0x59, 0x21, 0x45, 0x42, 0xcb, 0x98, 0x4f, 0xca, 0x05, 0x7e, 0x70, 0x46, ++ 0xfa, 0xac, 0x39, 0xd4, 0x67, 0x85, 0x30, 0xae, 0x33, 0xca, 0xfd, 0x1f, ++ 0xb8, 0xbe, 0x55, 0x57, 0x9b, 0x2e, 0xc9, 0x38, 0xee, 0x98, 0xc2, 0xe5, ++ 0xa5, 0x3b, 0x8e, 0xf0, 0xa0, 0x00, 0xec, 0x61, 0xf0, 0x5c, 0x53, 0xb8, ++ 0x53, 0xb5, 0x03, 0xbe, 0x9a, 0x62, 0x2c, 0x8e, 0xc6, 0x54, 0xba, 0xee, ++ 0x09, 0x8b, 0xc1, 0xbe, 0x53, 0x55, 0x83, 0xae, 0x6b, 0xf4, 0xc0, 0xe7, ++ 0x10, 0x8e, 0x26, 0x03, 0x73, 0x46, 0x43, 0xdb, 0x75, 0x60, 0x4c, 0x54, ++ 0x5f, 0xf6, 0xf0, 0x78, 0xeb, 0xaa, 0x57, 0xab, 0x14, 0xa0, 0xff, 0xbe, ++ 0xfa, 0x0c, 0x6a, 0xf5, 0xf7, 0x8b, 0x4c, 0xf6, 0x74, 0x07, 0x3c, 0x5f, ++ 0x64, 0x60, 0xee, 0x16, 0xdb, 0xe0, 0xfb, 0xaf, 0x22, 0xbf, 0x10, 0x9d, ++ 0xd4, 0x14, 0xa4, 0x73, 0x6d, 0xb7, 0x89, 0xe4, 0x1c, 0x7f, 0x12, 0xf0, ++ 0xfd, 0x2a, 0xa1, 0x87, 0x6a, 0x81, 0x40, 0x51, 0x00, 0xcf, 0xaa, 0x63, ++ 0xcc, 0x17, 0x1e, 0x89, 0xe3, 0xca, 0xbf, 0x50, 0xb0, 0x6d, 0x95, 0xd8, ++ 0xe9, 0x10, 0xbe, 0x62, 0x81, 0xbe, 0x3c, 0x3c, 0xdc, 0x37, 0xda, 0xd6, ++ 0xe2, 0x7c, 0x4a, 0x30, 0x9f, 0x70, 0x3c, 0x15, 0x2b, 0xa9, 0x55, 0x4a, ++ 0xd0, 0x7b, 0x4b, 0x6d, 0x99, 0x21, 0x7d, 0x39, 0xd1, 0x90, 0x81, 0xeb, ++ 0x61, 0x72, 0xb8, 0x63, 0x13, 0xe0, 0x57, 0x4e, 0x31, 0xac, 0xde, 0x01, ++ 0xeb, 0x97, 0x6f, 0x86, 0x16, 0xf0, 0xa1, 0xd8, 0x1d, 0xf2, 0x12, 0x68, ++ 0x9b, 0x4b, 0xa6, 0xcb, 0x4b, 0xa1, 0x6d, 0x34, 0xb2, 0x85, 0x2d, 0xd8, ++ 0x1a, 0xd8, 0xf2, 0x60, 0x3c, 0x75, 0x08, 0x79, 0xd2, 0xda, 0x4b, 0x76, ++ 0xd7, 0x6f, 0x90, 0xee, 0x17, 0xde, 0xef, 0x2d, 0xb0, 0x92, 0x9e, 0x1a, ++ 0x69, 0x27, 0xf9, 0x16, 0xeb, 0x6d, 0x94, 0x1c, 0x3e, 0xd4, 0x43, 0x9e, ++ 0x2e, 0xe6, 0xd8, 0x04, 0xd7, 0x9a, 0x64, 0x17, 0xe3, 0x7c, 0xdc, 0xc2, ++ 0x90, 0x8f, 0x7f, 0x2f, 0xe6, 0x71, 0x98, 0x0d, 0x3b, 0x55, 0xe0, 0xd7, ++ 0xf7, 0xec, 0x0f, 0x12, 0xff, 0x3a, 0xa2, 0x0c, 0x8f, 0xa6, 0x42, 0xff, ++ 0xa3, 0xe6, 0x15, 0x15, 0x0a, 0xf0, 0xaf, 0x23, 0xc5, 0x70, 0x25, 0x15, ++ 0x78, 0xf4, 0x78, 0xf3, 0x4a, 0xde, 0xcf, 0x32, 0x5c, 0x19, 0x0d, 0xfd, ++ 0x4f, 0x9a, 0x6b, 0x78, 0x7f, 0x2a, 0x4c, 0x99, 0xcc, 0xd8, 0xc9, 0xe6, ++ 0x55, 0x15, 0x9e, 0x6c, 0x9c, 0x97, 0xeb, 0x31, 0xb6, 0xc5, 0x99, 0x85, ++ 0xef, 0x51, 0x0c, 0x12, 0xc9, 0xa9, 0xb2, 0xd7, 0xe4, 0x6d, 0x84, 0x3f, ++ 0x9b, 0x22, 0x39, 0x3f, 0x35, 0x19, 0x81, 0x2f, 0x63, 0x70, 0xbc, 0x4a, ++ 0xe3, 0x9f, 0x6a, 0x28, 0xde, 0x6c, 0x05, 0xfe, 0x57, 0x8a, 0x9d, 0xea, ++ 0x6a, 0x1b, 0xc7, 0x35, 0xf2, 0xc3, 0xff, 0xb4, 0xd5, 0xf0, 0x28, 0x5b, ++ 0x0d, 0xab, 0x11, 0x8f, 0xd8, 0x22, 0xbe, 0xcf, 0x88, 0x75, 0x6b, 0x74, ++ 0x60, 0xad, 0xce, 0xac, 0x39, 0xa8, 0x17, 0x5a, 0x9c, 0x59, 0x73, 0x23, ++ 0x10, 0xaf, 0xee, 0xcf, 0x11, 0xaf, 0x79, 0x3d, 0xbd, 0xd3, 0x51, 0x0f, ++ 0xb7, 0x7e, 0xf0, 0x49, 0x81, 0x3b, 0x9b, 0xd3, 0x0b, 0xe7, 0xc9, 0xeb, ++ 0x61, 0x2c, 0x12, 0xd6, 0x73, 0xe1, 0xad, 0x9b, 0x36, 0xca, 0x52, 0x80, ++ 0x3e, 0x97, 0xec, 0x45, 0xe7, 0x51, 0x5f, 0x4b, 0xa0, 0xa6, 0x1f, 0x87, ++ 0x75, 0x49, 0xaa, 0x9d, 0xdd, 0x03, 0x72, 0xd7, 0xe8, 0x64, 0xaa, 0x09, ++ 0xd6, 0x95, 0xc8, 0x5e, 0xb2, 0xa3, 0xfd, 0x30, 0x20, 0x7d, 0x40, 0x05, ++ 0xb5, 0x32, 0xae, 0x5f, 0x3a, 0xa3, 0x5c, 0x5f, 0xe2, 0x73, 0x6c, 0xa4, ++ 0x8f, 0xec, 0x4c, 0xb5, 0xdd, 0xf5, 0x15, 0xbe, 0x5f, 0xd3, 0xcf, 0xac, ++ 0x37, 0x66, 0x48, 0x3d, 0xac, 0xd7, 0x57, 0xa6, 0x9c, 0xc7, 0x65, 0x06, ++ 0x7c, 0x10, 0x93, 0xd2, 0x76, 0x7c, 0x29, 0xea, 0xf3, 0xdf, 0x9a, 0x1d, ++ 0xb7, 0xa8, 0x08, 0x8f, 0x93, 0x3d, 0x0e, 0x70, 0x6c, 0x33, 0x30, 0x85, ++ 0xc5, 0x10, 0x7b, 0x64, 0x28, 0x70, 0xdf, 0xca, 0xc2, 0x1d, 0xeb, 0x50, ++ 0xde, 0x1d, 0x2c, 0xc9, 0x03, 0xf2, 0x85, 0x68, 0x23, 0xe0, 0xe0, 0x17, ++ 0x07, 0xf6, 0xd0, 0x28, 0x64, 0x48, 0x5b, 0x07, 0x3c, 0x5f, 0xca, 0xa0, ++ 0x9d, 0x84, 0x70, 0xdd, 0x4a, 0xeb, 0x92, 0x91, 0x9f, 0x26, 0x30, 0x97, ++ 0x8c, 0x7a, 0xab, 0x80, 0x79, 0xad, 0xd8, 0xf6, 0x77, 0xbc, 0x95, 0x84, ++ 0xf8, 0x7a, 0x3e, 0x8c, 0xdd, 0xe7, 0x82, 0xd6, 0xf2, 0x2a, 0x73, 0x7a, ++ 0x83, 0xf4, 0x46, 0x7e, 0xb4, 0x44, 0xf8, 0x9f, 0x15, 0x63, 0xa4, 0x36, ++ 0xdc, 0xd8, 0x32, 0x17, 0xf9, 0x34, 0xfc, 0x12, 0xb3, 0xa3, 0x1f, 0xd0, ++ 0xff, 0x0b, 0x93, 0x82, 0xf3, 0x83, 0x60, 0xdc, 0x89, 0xd7, 0x1d, 0xfb, ++ 0x0d, 0x0c, 0xe1, 0xfc, 0xb5, 0xd1, 0x6b, 0x8f, 0x82, 0xbe, 0x3f, 0x53, ++ 0x51, 0x5f, 0x66, 0x81, 0xf9, 0xfa, 0x05, 0x9d, 0xb5, 0x79, 0x9f, 0x37, ++ 0xa9, 0x99, 0xd1, 0xd0, 0xaf, 0x8a, 0x91, 0x08, 0x2f, 0xbf, 0x2e, 0xe2, ++ 0xf6, 0xd8, 0xff, 0x85, 0xc9, 0xfb, 0x72, 0x2a, 0xe2, 0xc7, 0xb2, 0xda, ++ 0x1b, 0x24, 0x57, 0xe3, 0xa3, 0xf9, 0xb8, 0xba, 0xb8, 0xe2, 0xb1, 0xd1, ++ 0xf0, 0x7c, 0x4b, 0x47, 0x38, 0xc3, 0xf7, 0x4f, 0xea, 0x0c, 0x37, 0x20, ++ 0xfe, 0x37, 0x6f, 0xc9, 0x0d, 0x43, 0x3e, 0xd8, 0x86, 0xb8, 0x81, 0xf5, ++ 0xc7, 0x98, 0xed, 0x8f, 0xe0, 0x7c, 0x31, 0x57, 0x00, 0xde, 0x54, 0xba, ++ 0xee, 0x24, 0xbc, 0x2a, 0xea, 0x84, 0x28, 0xc0, 0x6b, 0xe1, 0x4c, 0x9b, ++ 0xba, 0x0e, 0xf0, 0xfe, 0xeb, 0xb0, 0x96, 0x99, 0xc8, 0xf7, 0xfe, 0xad, ++ 0x06, 0xf6, 0x32, 0xbc, 0x62, 0x9b, 0xc9, 0x31, 0x07, 0xfb, 0xdb, 0x2e, ++ 0xab, 0x76, 0xd4, 0xb3, 0xbf, 0x4e, 0x6d, 0x09, 0xa7, 0xf5, 0x6c, 0x35, ++ 0xd0, 0x7a, 0xb6, 0x85, 0xfb, 0xc7, 0xad, 0x01, 0xb8, 0xd7, 0x65, 0x28, ++ 0x15, 0x08, 0x9f, 0x62, 0x65, 0x0a, 0xea, 0x5f, 0xc5, 0x50, 0xac, 0x3e, ++ 0x02, 0xd7, 0xa7, 0x45, 0x73, 0xfd, 0xa8, 0xe9, 0xe3, 0x9a, 0x68, 0x95, ++ 0xfa, 0xcf, 0x4b, 0xf0, 0xfe, 0x5c, 0x1c, 0x57, 0x44, 0x72, 0x53, 0x26, ++ 0xdb, 0x48, 0xde, 0xfa, 0xfd, 0xcc, 0x6b, 0x86, 0xf7, 0xc4, 0xcf, 0xeb, ++ 0x95, 0x91, 0x1e, 0xe1, 0x73, 0x80, 0x95, 0x90, 0xdf, 0x15, 0x9f, 0xcc, ++ 0x70, 0x3e, 0x17, 0x12, 0x1a, 0x5a, 0x9b, 0xd1, 0xab, 0x92, 0x9e, 0x75, ++ 0xda, 0x96, 0x00, 0xdd, 0xa7, 0x0b, 0x3d, 0x3b, 0xfd, 0x64, 0x4d, 0x25, ++ 0x8b, 0xc4, 0x8e, 0xe3, 0xd8, 0x54, 0x98, 0x6f, 0x9f, 0xcd, 0xc8, 0x70, ++ 0x5d, 0xb7, 0xb1, 0x3e, 0xd9, 0x02, 0xfd, 0xdb, 0xae, 0x32, 0x87, 0x0f, ++ 0xf9, 0xe7, 0xaa, 0x42, 0x7e, 0x98, 0x1d, 0xfe, 0x05, 0xfb, 0x7b, 0x65, ++ 0x62, 0x9e, 0x5f, 0x49, 0x4c, 0x89, 0x82, 0x71, 0x45, 0x5f, 0xaa, 0x0a, ++ 0xf2, 0x57, 0x11, 0x0b, 0xf5, 0xdb, 0xca, 0x36, 0x94, 0x7f, 0x81, 0xf6, ++ 0xad, 0xc4, 0xa2, 0xbb, 0x8e, 0xfe, 0x5c, 0x24, 0xb6, 0x4a, 0xe0, 0x3a, ++ 0xcc, 0xb3, 0x28, 0x5a, 0xf8, 0x61, 0xa3, 0xd8, 0xa8, 0x6b, 0xa4, 0xcf, ++ 0x60, 0xd6, 0x04, 0x61, 0x47, 0x55, 0x5c, 0x7f, 0xf6, 0x7f, 0xe1, 0xba, ++ 0xfa, 0x2b, 0x4c, 0x0e, 0x5c, 0xff, 0x76, 0x9b, 0xf3, 0xe3, 0xa9, 0xa8, ++ 0x07, 0x7b, 0x8d, 0x6c, 0x13, 0x1b, 0x5e, 0x8e, 0x7e, 0x55, 0x0f, 0x1a, ++ 0x7d, 0x0c, 0x08, 0xc7, 0xd5, 0x70, 0xe6, 0x8d, 0x25, 0x3e, 0xb4, 0x21, ++ 0xfd, 0xc7, 0x6d, 0x68, 0xf6, 0x84, 0xc1, 0x7a, 0xc7, 0xa5, 0xf3, 0xf9, ++ 0x91, 0xdf, 0x50, 0x6f, 0x8c, 0xfd, 0x45, 0x5c, 0x2c, 0xea, 0xed, 0x88, ++ 0x68, 0xae, 0x4f, 0xb4, 0x56, 0xe3, 0x2f, 0xe4, 0x23, 0x7b, 0x14, 0xe7, ++ 0x23, 0xfb, 0xad, 0x01, 0xf9, 0xfb, 0x5e, 0x74, 0x2a, 0x8d, 0xd3, 0xe4, ++ 0x09, 0xf9, 0x0b, 0xe7, 0xd9, 0x63, 0xf4, 0x2e, 0x76, 0x0d, 0x61, 0x17, ++ 0x81, 0x2f, 0xbf, 0x87, 0x7c, 0xb9, 0xdd, 0xc6, 0x2a, 0x90, 0xcf, 0x9f, ++ 0x19, 0x61, 0x59, 0x88, 0xf2, 0xa4, 0xbd, 0x67, 0xb7, 0xe0, 0x7b, 0x7d, ++ 0xfb, 0x54, 0xc3, 0x9a, 0x2e, 0x23, 0xae, 0xfb, 0x2f, 0xa0, 0xff, 0x01, ++ 0xee, 0xd2, 0xe4, 0xab, 0xa6, 0x60, 0xfb, 0xdd, 0x15, 0xc7, 0xe1, 0x2d, ++ 0x93, 0xbf, 0x25, 0xbf, 0xfa, 0x62, 0xbb, 0x44, 0xfe, 0x7c, 0x42, 0x3b, ++ 0xd7, 0xd7, 0xc1, 0x7c, 0x31, 0x62, 0x68, 0xbe, 0x78, 0x01, 0xf1, 0x7a, ++ 0x3d, 0xbe, 0xd0, 0xc7, 0x01, 0x1a, 0x5f, 0xec, 0xb8, 0x1e, 0x5f, 0x74, ++ 0xff, 0x63, 0x7c, 0xf1, 0x8b, 0x68, 0xe1, 0xdf, 0x0e, 0xcb, 0x17, 0xdf, ++ 0x46, 0xe2, 0xfa, 0x1f, 0xeb, 0x28, 0x49, 0x64, 0x7f, 0xc7, 0x8f, 0x69, ++ 0x13, 0x7c, 0x30, 0xdc, 0xfd, 0x29, 0x56, 0xae, 0xd7, 0xf4, 0xd7, 0xdb, ++ 0x05, 0x3e, 0x77, 0x9b, 0x9a, 0xef, 0xcc, 0x41, 0xb9, 0xbf, 0xcb, 0xe0, ++ 0x40, 0xb9, 0x06, 0xaa, 0xa7, 0xcc, 0x05, 0xfb, 0xb2, 0x3b, 0x9c, 0x3f, ++ 0xc7, 0x94, 0xd5, 0x69, 0xd8, 0xdf, 0xae, 0x70, 0x3d, 0xb2, 0xbd, 0xdd, ++ 0x4c, 0x7a, 0x64, 0xbb, 0xcd, 0xed, 0x26, 0x7b, 0x9d, 0x64, 0x61, 0xe8, ++ 0x27, 0x30, 0xc5, 0xdd, 0xf7, 0x7d, 0xd4, 0x7f, 0xc9, 0x16, 0x75, 0x5d, ++ 0x10, 0xdf, 0x3e, 0x2e, 0xf4, 0x40, 0x8b, 0xd1, 0x37, 0xe5, 0x73, 0xf4, ++ 0x7f, 0x0f, 0x70, 0xfa, 0x4e, 0xbe, 0x2b, 0x57, 0x36, 0xc1, 0xb8, 0x11, ++ 0x0f, 0x70, 0xb9, 0xce, 0x3f, 0x67, 0xda, 0x28, 0xc3, 0x3c, 0xd5, 0x31, ++ 0x45, 0xbe, 0x68, 0x18, 0xdf, 0x17, 0xcd, 0xed, 0x62, 0xdd, 0x19, 0x18, ++ 0x05, 0x7c, 0x59, 0x7b, 0xc6, 0x44, 0xfa, 0xed, 0xad, 0xce, 0x23, 0xe5, ++ 0x4e, 0x1b, 0xf9, 0x37, 0x4e, 0xe4, 0xaf, 0x49, 0x7b, 0x8e, 0x94, 0x17, ++ 0x67, 0xe3, 0x78, 0xce, 0x47, 0xdd, 0xa2, 0xd5, 0xfa, 0x53, 0x70, 0x4d, ++ 0x31, 0x64, 0x76, 0x8e, 0x25, 0x01, 0x7e, 0x5d, 0xc2, 0x4e, 0x4c, 0x61, ++ 0x5c, 0x0f, 0xb9, 0x90, 0x3f, 0x72, 0x02, 0x7d, 0xe6, 0x34, 0x52, 0x3c, ++ 0xa6, 0xf1, 0x41, 0x35, 0x63, 0x59, 0x68, 0x27, 0xe6, 0xf6, 0x39, 0xca, ++ 0x90, 0x8d, 0xaa, 0x2a, 0x42, 0xe9, 0x5b, 0xed, 0x9b, 0x49, 0x71, 0xdf, ++ 0xfc, 0xe3, 0xce, 0xb2, 0x08, 0x58, 0xd7, 0x7c, 0x97, 0xee, 0xbe, 0xa0, ++ 0x7f, 0xb5, 0x8e, 0xfe, 0xe0, 0x07, 0xff, 0x01, 0xe5, 0x64, 0xd5, 0xe6, ++ 0xde, 0x4e, 0x1b, 0xf2, 0xad, 0xca, 0xed, 0x69, 0x8b, 0x69, 0x75, 0x16, ++ 0xf7, 0x7b, 0x56, 0xa7, 0xa1, 0xff, 0xaf, 0xc9, 0x11, 0xfd, 0x00, 0x4f, ++ 0x2d, 0xbf, 0xcf, 0x78, 0x79, 0x5d, 0x90, 0x1d, 0x57, 0x63, 0xf8, 0x3a, ++ 0x9f, 0x75, 0x28, 0x74, 0xdf, 0xd3, 0x67, 0xf2, 0xde, 0x02, 0x97, 0xfe, ++ 0x37, 0xe3, 0xcf, 0xb5, 0x08, 0x7b, 0xf3, 0xad, 0x90, 0xe3, 0xdc, 0xc7, ++ 0xde, 0x58, 0x8c, 0xfc, 0x9b, 0xb7, 0xdc, 0xb9, 0x0f, 0xf1, 0xbf, 0x28, ++ 0x4e, 0xa6, 0xeb, 0xff, 0xc9, 0x7c, 0x96, 0x34, 0xa4, 0x8f, 0x43, 0x21, ++ 0xff, 0xab, 0xc5, 0xa8, 0x96, 0x7c, 0x2e, 0x05, 0xc6, 0x31, 0xc5, 0x95, ++ 0x61, 0x83, 0xfb, 0x7b, 0xe2, 0xc3, 0xf3, 0xf0, 0xfd, 0xd5, 0x31, 0xee, ++ 0x6b, 0x48, 0x27, 0xa6, 0xf8, 0xbb, 0xf1, 0xb9, 0x49, 0x85, 0xb9, 0x79, ++ 0x28, 0x57, 0xb6, 0x09, 0x4d, 0xb1, 0x68, 0x7f, 0x34, 0xb8, 0x01, 0xae, ++ 0x8a, 0x4d, 0xb6, 0x00, 0x1c, 0x1a, 0x5c, 0xe7, 0x85, 0xfe, 0xa9, 0x8e, ++ 0x59, 0x72, 0x0d, 0xf1, 0x80, 0xcf, 0xa1, 0x5e, 0x69, 0x3b, 0x75, 0xd6, ++ 0x82, 0xcf, 0x6b, 0x74, 0x6f, 0xe9, 0xb8, 0xc4, 0xe9, 0x1d, 0x44, 0x7f, ++ 0xa4, 0x77, 0x80, 0xfe, 0xd2, 0x7d, 0xd8, 0xd7, 0xf0, 0x60, 0x11, 0xad, ++ 0xd6, 0xff, 0xe7, 0xe9, 0xef, 0x1b, 0x89, 0xf4, 0x18, 0x96, 0xfe, 0x18, ++ 0xf7, 0x47, 0xfe, 0x8f, 0xe8, 0x3f, 0x2a, 0x66, 0x08, 0xfa, 0x83, 0x3f, ++ 0x95, 0x8e, 0xd7, 0x35, 0x7f, 0xaa, 0xc5, 0x04, 0x7e, 0x75, 0x76, 0xa0, ++ 0xaf, 0xd1, 0xbd, 0xda, 0x5e, 0x44, 0xe3, 0x1c, 0x26, 0x58, 0x19, 0xfa, ++ 0x4f, 0x9d, 0x10, 0x57, 0xa2, 0x1c, 0xba, 0xa3, 0xd1, 0xb9, 0x61, 0x3b, ++ 0xed, 0xfc, 0x5d, 0xfd, 0xbf, 0x3f, 0x3b, 0x0a, 0x5c, 0x40, 0x36, 0x29, ++ 0x26, 0x86, 0xcb, 0x93, 0xc9, 0x3f, 0x06, 0xfd, 0x8d, 0x09, 0x3e, 0x89, ++ 0xfc, 0xbe, 0x09, 0x20, 0xf0, 0xf7, 0x90, 0x9f, 0x35, 0x92, 0xf4, 0x9d, ++ 0x43, 0xe0, 0x87, 0x9d, 0x95, 0xa4, 0xb3, 0x19, 0xdc, 0x05, 0xbf, 0x96, ++ 0x82, 0xfe, 0x9f, 0x2f, 0x16, 0xe5, 0x60, 0x82, 0xb9, 0xd2, 0x87, 0xfc, ++ 0xbe, 0xc3, 0x3a, 0x3d, 0x05, 0xfd, 0xb7, 0x5c, 0xeb, 0xb4, 0x34, 0xe4, ++ 0xa7, 0x37, 0x33, 0x1e, 0x3b, 0x84, 0x26, 0xe7, 0xcd, 0xe4, 0xe5, 0x3b, ++ 0x5f, 0x51, 0x03, 0x7e, 0x8e, 0xa6, 0xd7, 0xf6, 0x89, 0x69, 0xb5, 0xf7, ++ 0x97, 0xc7, 0x70, 0xfa, 0xdf, 0x0e, 0x6a, 0x16, 0xfd, 0x3d, 0x74, 0x0d, ++ 0x83, 0xe1, 0xd0, 0xf4, 0x37, 0x92, 0x05, 0xe1, 0x90, 0x7c, 0xd5, 0x86, ++ 0x6b, 0x56, 0xd2, 0xc7, 0xed, 0x7d, 0x80, 0xaf, 0xdb, 0x11, 0x0e, 0xc0, ++ 0x6b, 0x97, 0xc4, 0x5a, 0x51, 0x7f, 0x17, 0x19, 0x9c, 0x71, 0x25, 0xe8, ++ 0x8f, 0xc5, 0xfb, 0x14, 0xee, 0xd7, 0x7d, 0x3d, 0x4a, 0x05, 0xbe, 0xa9, ++ 0x6c, 0x7f, 0xf7, 0x38, 0xc2, 0x5b, 0x69, 0xb1, 0xf9, 0x30, 0xdf, 0xc2, ++ 0x1c, 0xc6, 0xf3, 0x7d, 0x41, 0xf9, 0x12, 0xbd, 0x9f, 0xab, 0xf9, 0x25, ++ 0x9a, 0xdf, 0xaf, 0xf9, 0x2d, 0x5a, 0x7c, 0x89, 0xfe, 0x0d, 0xde, 0xcf, ++ 0xc7, 0xeb, 0x00, 0xbf, 0xdd, 0x0c, 0x00, 0xa2, 0xfd, 0xf1, 0x59, 0xbc, ++ 0x0d, 0xf0, 0xfe, 0xe7, 0x2f, 0xab, 0x99, 0x4e, 0x21, 0xaf, 0x0a, 0xac, ++ 0xa3, 0x52, 0xac, 0x63, 0x36, 0xeb, 0x25, 0xb8, 0xd8, 0xb7, 0xd7, 0xae, ++ 0x4d, 0x03, 0xfa, 0xcc, 0x12, 0xf8, 0xa8, 0xec, 0x86, 0xb8, 0x30, 0x07, ++ 0xef, 0x33, 0x76, 0x17, 0xe0, 0xe1, 0x2e, 0x85, 0xc7, 0x8b, 0x77, 0x39, ++ 0x20, 0x3e, 0x0c, 0xe2, 0xa3, 0xd9, 0x93, 0x43, 0xfb, 0xf8, 0x9b, 0x9e, ++ 0x10, 0x98, 0xe7, 0x7a, 0xe3, 0xf5, 0xfa, 0x7f, 0xaa, 0xc8, 0x17, 0xfc, ++ 0xb3, 0x71, 0xa6, 0xd6, 0x76, 0x83, 0x1d, 0x3a, 0x0d, 0x0c, 0x70, 0xb0, ++ 0x9e, 0xc7, 0x34, 0x85, 0xa3, 0x65, 0x8f, 0x82, 0xf1, 0x80, 0x3b, 0xd3, ++ 0x80, 0xfc, 0x58, 0x27, 0xec, 0x1a, 0x84, 0xc9, 0x43, 0xdb, 0x23, 0x21, ++ 0xaf, 0x85, 0x86, 0xbe, 0x1c, 0x07, 0xe0, 0xb7, 0x6b, 0xcf, 0x37, 0x64, ++ 0xff, 0xf6, 0xee, 0xf9, 0xe6, 0x23, 0xf4, 0xe7, 0xa6, 0x7c, 0xa1, 0x30, ++ 0x33, 0x3c, 0x5f, 0xf8, 0x45, 0x7e, 0x14, 0xea, 0x07, 0xe6, 0x0a, 0x9d, ++ 0xb7, 0xee, 0x8f, 0xad, 0x56, 0xc6, 0xaf, 0x13, 0xff, 0xd4, 0x8a, 0xb5, ++ 0xef, 0xaf, 0xc7, 0x8c, 0x18, 0xc2, 0x67, 0xa1, 0xf6, 0x37, 0xe7, 0x9f, ++ 0x5f, 0x8f, 0xf3, 0x7d, 0x79, 0x46, 0xe1, 0xbc, 0x2d, 0xde, 0x5f, 0x6e, ++ 0x72, 0xa7, 0xdb, 0x6d, 0xd8, 0xf2, 0x78, 0x7f, 0xbf, 0xc4, 0xfd, 0x1d, ++ 0xed, 0xfe, 0x7e, 0x23, 0xc0, 0x0d, 0xd7, 0x37, 0xc5, 0x68, 0x71, 0x7f, ++ 0xaf, 0x42, 0xf9, 0x19, 0xf8, 0x99, 0x83, 0xe8, 0x7c, 0x17, 0xc6, 0xfb, ++ 0xb9, 0x01, 0xba, 0xde, 0x75, 0xae, 0xe2, 0x0b, 0x25, 0x67, 0x30, 0x7d, ++ 0xf0, 0xf7, 0xff, 0x23, 0xde, 0xd7, 0xe2, 0xfc, 0xb7, 0x44, 0xfc, 0xc0, ++ 0xf6, 0x9d, 0x30, 0xa9, 0x00, 0xd7, 0x8c, 0xd6, 0x47, 0x14, 0xf4, 0xa3, ++ 0x67, 0x24, 0xc9, 0xcc, 0x19, 0xf4, 0xde, 0x3b, 0x54, 0x2b, 0x73, 0x06, ++ 0xc5, 0xfb, 0x6f, 0xc4, 0xe8, 0xfc, 0x90, 0x7d, 0xaf, 0xad, 0x9f, 0x05, ++ 0x76, 0xa4, 0xae, 0x47, 0x76, 0x84, 0xa1, 0xbc, 0xb6, 0x6f, 0x3f, 0x94, ++ 0x83, 0xfd, 0x5e, 0xd9, 0x61, 0x1d, 0x82, 0x8f, 0xf4, 0xf8, 0x9d, 0xd1, ++ 0xfe, 0x88, 0x82, 0xfc, 0x9f, 0x10, 0xcb, 0xe5, 0xe6, 0x7a, 0xef, 0x2f, ++ 0x1c, 0x07, 0x7c, 0x72, 0x2b, 0xd2, 0x9d, 0x91, 0x1f, 0x77, 0xb1, 0x40, ++ 0x22, 0x39, 0xd2, 0xd3, 0x77, 0xef, 0x9e, 0x9f, 0xc7, 0xf6, 0x65, 0x0f, ++ 0x8f, 0xef, 0xe1, 0xe8, 0xaf, 0xa7, 0xc3, 0x6f, 0xce, 0x17, 0x47, 0x21, ++ 0x5e, 0xae, 0x47, 0x0f, 0x3d, 0xdf, 0x76, 0xc2, 0x3a, 0x3d, 0xb0, 0x3e, ++ 0x1f, 0xac, 0xd3, 0x03, 0xfe, 0xd6, 0xde, 0x7a, 0x3b, 0xf5, 0xdf, 0xae, ++ 0x4f, 0xa2, 0xbe, 0xc6, 0xaf, 0x75, 0x1d, 0xbf, 0x8c, 0x45, 0x7f, 0x4d, ++ 0xe3, 0xd3, 0xb2, 0x58, 0xce, 0x37, 0x53, 0x76, 0xaf, 0x8f, 0x65, 0xb6, ++ 0x00, 0xbd, 0x34, 0x7c, 0x5d, 0x14, 0x74, 0xab, 0x66, 0x8e, 0xf9, 0xb3, ++ 0xe0, 0xcf, 0x5d, 0x92, 0x23, 0x82, 0xf4, 0x84, 0x87, 0xf5, 0x26, 0x15, ++ 0x04, 0xec, 0x55, 0xf5, 0xb1, 0x72, 0xf2, 0x33, 0x34, 0x7b, 0x55, 0x2d, ++ 0x67, 0x1b, 0x51, 0xff, 0x6a, 0xf6, 0x0a, 0xd3, 0xc2, 0xa8, 0xcf, 0xf4, ++ 0xf6, 0x69, 0x7e, 0x7a, 0x91, 0x11, 0xd5, 0xaa, 0xde, 0x2e, 0xc1, 0x02, ++ 0x8d, 0xc8, 0xbf, 0xd5, 0x0b, 0x43, 0xaf, 0x57, 0xf4, 0x34, 0x2b, 0x11, ++ 0xd4, 0x33, 0x10, 0x9d, 0x24, 0x49, 0xe0, 0x43, 0xf8, 0xd5, 0x1a, 0x3c, ++ 0x1f, 0x32, 0x17, 0xc1, 0xab, 0xa7, 0xa7, 0x06, 0x9f, 0x1e, 0x2e, 0xcd, ++ 0x9f, 0xae, 0x16, 0x74, 0x83, 0x75, 0x96, 0xe1, 0xd2, 0xe7, 0xaa, 0x45, ++ 0xb4, 0x8e, 0x41, 0x76, 0x55, 0xac, 0xf7, 0x46, 0xed, 0xa9, 0x39, 0x36, ++ 0x34, 0xce, 0xba, 0x72, 0xae, 0xf4, 0xfd, 0x9c, 0x21, 0xf8, 0x75, 0x38, ++ 0xbe, 0xd5, 0xdf, 0xd7, 0xf4, 0x40, 0x39, 0xbe, 0x20, 0x97, 0x5a, 0x0f, ++ 0xfa, 0x11, 0x09, 0xb1, 0x09, 0x44, 0xaf, 0xf2, 0xab, 0x26, 0xe6, 0x04, ++ 0x7b, 0xc1, 0x46, 0x86, 0xb1, 0xcf, 0x82, 0xf3, 0xef, 0xaf, 0x64, 0x92, ++ 0xbd, 0x7b, 0x54, 0xd8, 0xdf, 0xe1, 0xf8, 0xa6, 0xf6, 0xaa, 0x81, 0xb9, ++ 0x63, 0x03, 0xfc, 0x63, 0x6c, 0x7b, 0xce, 0x8a, 0xfc, 0xb3, 0x5b, 0x69, ++ 0xb6, 0x62, 0xde, 0xf1, 0x36, 0xdb, 0x9c, 0xc6, 0x28, 0xc0, 0x53, 0xe9, ++ 0x1f, 0x8b, 0xe7, 0xa1, 0x5f, 0x57, 0xd7, 0x67, 0x60, 0x98, 0x9a, 0x2a, ++ 0x6b, 0xbf, 0xb4, 0x0f, 0xe3, 0xf6, 0xba, 0xe3, 0xcc, 0x81, 0xfa, 0xb0, ++ 0xb8, 0xbd, 0xab, 0x04, 0xf9, 0xed, 0x6d, 0xa5, 0x57, 0xa6, 0x38, 0xfa, ++ 0x4b, 0xc6, 0x9e, 0x0b, 0xf2, 0x0f, 0xdb, 0xda, 0x1b, 0xad, 0xe8, 0x3f, ++ 0xb5, 0xc5, 0xc9, 0x14, 0xa7, 0xef, 0x8f, 0xe6, 0xfc, 0xa8, 0xdd, 0x6f, ++ 0x89, 0xe5, 0xfc, 0xd7, 0x76, 0xe6, 0xf2, 0x2c, 0xe7, 0x10, 0xf7, 0x3f, ++ 0x13, 0xf7, 0x4b, 0x4f, 0xe5, 0x1a, 0xd1, 0x48, 0xf6, 0xc7, 0x47, 0x50, ++ 0xbe, 0xa1, 0xfc, 0x69, 0x03, 0xad, 0xbf, 0x54, 0xb2, 0x57, 0x55, 0xa2, ++ 0xff, 0x71, 0x87, 0x91, 0xfc, 0x7a, 0x88, 0x5b, 0xfe, 0xf0, 0x7d, 0xcc, ++ 0x37, 0xb5, 0x99, 0xb7, 0x63, 0xaa, 0xbe, 0xac, 0xed, 0x87, 0x8f, 0xd8, ++ 0x81, 0x10, 0x2d, 0xff, 0xe7, 0xb3, 0x06, 0x33, 0xe6, 0x0f, 0xe6, 0x48, ++ 0x8e, 0x97, 0x61, 0x5c, 0xb9, 0xea, 0xef, 0xc2, 0x7e, 0xf9, 0xbc, 0x54, ++ 0xda, 0x87, 0x99, 0xf4, 0x7f, 0x65, 0xf2, 0x5f, 0xfd, 0x77, 0x4b, 0x94, ++ 0xf7, 0x28, 0x07, 0x76, 0xc1, 0x7e, 0xf9, 0x3d, 0xa9, 0x5e, 0xcc, 0x3f, ++ 0xec, 0x91, 0x78, 0xdf, 0xd3, 0xc1, 0xf3, 0xfe, 0xcc, 0xee, 0x89, 0x9d, ++ 0x05, 0xef, 0xf9, 0xa0, 0x32, 0x76, 0xc2, 0x3a, 0xe2, 0x29, 0xad, 0x7f, ++ 0x4b, 0xee, 0x3a, 0x26, 0x18, 0x38, 0x28, 0x9e, 0x7a, 0x6c, 0x17, 0xdf, ++ 0x3f, 0x7a, 0xac, 0x4c, 0xa2, 0xfd, 0xa3, 0x32, 0x7b, 0x0a, 0xf3, 0x04, ++ 0xf1, 0x55, 0xf9, 0xd3, 0x40, 0xcf, 0x3c, 0xe0, 0xc7, 0xf6, 0xc4, 0x62, ++ 0xe4, 0xdf, 0xaa, 0x0a, 0x99, 0x79, 0x83, 0xf8, 0x7a, 0xbe, 0xcb, 0xca, ++ 0xbc, 0x41, 0xe3, 0xf7, 0x87, 0x71, 0x78, 0xfc, 0x92, 0xd9, 0x8b, 0xf9, ++ 0x12, 0x4d, 0x5e, 0x67, 0x0a, 0xfe, 0xae, 0x5e, 0x18, 0x1b, 0x32, 0x7e, ++ 0x0e, 0xe3, 0x7e, 0xe2, 0x42, 0xd6, 0x6c, 0x44, 0xf9, 0xae, 0x13, 0xf0, ++ 0xd4, 0x15, 0x01, 0x3c, 0xf0, 0xfc, 0x4c, 0x11, 0xa7, 0xde, 0xed, 0x4e, ++ 0x09, 0x79, 0x6f, 0x25, 0x66, 0x41, 0x60, 0x68, 0x56, 0xdc, 0x68, 0xb2, ++ 0x8f, 0xb3, 0xbf, 0xec, 0x23, 0xb3, 0x3a, 0x47, 0x3e, 0x79, 0x6c, 0x31, ++ 0xbc, 0x87, 0x65, 0x70, 0xf9, 0xd0, 0xe4, 0xac, 0x4c, 0xae, 0x69, 0x22, ++ 0x3e, 0x48, 0x92, 0x1c, 0x18, 0x1f, 0xcf, 0x97, 0xc0, 0xab, 0x94, 0x51, ++ 0xdf, 0x85, 0xca, 0xd1, 0xec, 0xc9, 0xa1, 0xfd, 0x39, 0x4e, 0xbd, 0x7e, ++ 0x08, 0x95, 0x77, 0xbd, 0x1e, 0xd7, 0xe4, 0x7c, 0x7e, 0x87, 0x6c, 0xc4, ++ 0x38, 0x7a, 0x7e, 0x91, 0xe4, 0x60, 0x43, 0xe8, 0x03, 0xbd, 0x3f, 0xad, ++ 0xd7, 0x03, 0x93, 0x0c, 0x8e, 0x77, 0x30, 0xae, 0x9e, 0x7b, 0xd5, 0x49, ++ 0xfc, 0x35, 0x48, 0x0f, 0x9c, 0xac, 0xf8, 0x87, 0xf4, 0xc0, 0x5b, 0x20, ++ 0x5b, 0x93, 0x41, 0x5e, 0x7f, 0xa4, 0xe9, 0x83, 0x9b, 0xd8, 0x4d, 0xa8, ++ 0x0f, 0xca, 0xe4, 0x2d, 0xeb, 0x91, 0x3f, 0xfa, 0xc1, 0xae, 0x99, 0x87, ++ 0xe0, 0x0f, 0xcd, 0x2e, 0x68, 0xf1, 0x76, 0x39, 0xc8, 0x27, 0xf2, 0x03, ++ 0x3b, 0xcf, 0xf7, 0x25, 0xca, 0xae, 0x82, 0x9c, 0xc6, 0x06, 0xe2, 0xed, ++ 0x01, 0xfd, 0x00, 0x7e, 0x83, 0x63, 0x08, 0x7f, 0xe6, 0x57, 0xb1, 0x69, ++ 0x21, 0xfb, 0x49, 0x03, 0xfa, 0x22, 0xc8, 0x6f, 0x30, 0x16, 0xfc, 0xf3, ++ 0x7e, 0x43, 0x19, 0xf8, 0x8b, 0xa6, 0x5c, 0x84, 0x6f, 0x24, 0xf3, 0xe4, ++ 0x91, 0x9e, 0xa2, 0xfc, 0x1e, 0xb4, 0x3e, 0xca, 0xb3, 0x25, 0x5d, 0xa2, ++ 0x3c, 0x4a, 0x1d, 0xc4, 0xf1, 0x14, 0xcf, 0xb3, 0x5f, 0x12, 0x5c, 0xa8, ++ 0xd7, 0xa4, 0x98, 0x00, 0xdf, 0xeb, 0xfd, 0x09, 0x2d, 0x4f, 0x3b, 0x42, ++ 0xe4, 0x09, 0xf4, 0xfc, 0x30, 0x90, 0xb7, 0x9b, 0x67, 0xf4, 0x22, 0x9f, ++ 0x69, 0xfc, 0x50, 0x6e, 0xe7, 0x72, 0x51, 0x3e, 0x4f, 0xa6, 0xfc, 0xb9, ++ 0x9e, 0x3f, 0xb4, 0xf7, 0x5d, 0x8f, 0x2f, 0x7c, 0x12, 0xf0, 0x85, 0xf4, ++ 0x77, 0xf8, 0x42, 0xc8, 0xd3, 0x8d, 0xf2, 0xc5, 0x21, 0x8d, 0x1f, 0xd2, ++ 0x59, 0xfa, 0x8d, 0xf0, 0x83, 0xc6, 0x07, 0x1a, 0x5f, 0xe8, 0xed, 0xc5, ++ 0x41, 0x5d, 0xde, 0x65, 0x38, 0x7b, 0x71, 0xf2, 0x3a, 0xf6, 0xe2, 0x9d, ++ 0x0c, 0x23, 0xe9, 0x65, 0xbd, 0x9d, 0xd0, 0xec, 0xc2, 0x81, 0x38, 0xae, ++ 0x7f, 0xc7, 0xc7, 0xf2, 0x7d, 0x8a, 0x99, 0x99, 0xf3, 0x6d, 0xe8, 0x57, ++ 0x8c, 0x40, 0x7d, 0x80, 0xfe, 0x9e, 0xb0, 0x37, 0x03, 0x79, 0xa3, 0x0d, ++ 0x9c, 0x0f, 0xde, 0xe9, 0x5b, 0xaa, 0x48, 0x68, 0x37, 0x50, 0x0f, 0xa4, ++ 0x06, 0xe1, 0x5d, 0xe4, 0x4d, 0x35, 0xbe, 0xab, 0x7d, 0x9a, 0x51, 0xfe, ++ 0xb0, 0x52, 0xe8, 0x9f, 0x8b, 0x1d, 0x3c, 0x9f, 0x56, 0x57, 0x2a, 0x7b, ++ 0x2d, 0xf0, 0x67, 0x49, 0xfb, 0x73, 0xeb, 0x79, 0xdf, 0x48, 0xf9, 0xb6, ++ 0x22, 0xa5, 0x4b, 0xb1, 0xc0, 0xbc, 0xb3, 0x1d, 0x92, 0x03, 0xf3, 0x35, ++ 0x4e, 0x91, 0x7f, 0x9b, 0x75, 0xd5, 0xe4, 0x55, 0x29, 0x3f, 0x3f, 0xf4, ++ 0x7e, 0x7a, 0x95, 0xe0, 0x1b, 0x8c, 0x73, 0x70, 0xfc, 0x6c, 0xa7, 0xe4, ++ 0x85, 0x10, 0x74, 0x90, 0x1e, 0xaa, 0xba, 0xca, 0xed, 0xbe, 0x5e, 0x1f, ++ 0x55, 0x89, 0xfd, 0xf2, 0x2a, 0xdd, 0x7e, 0xb9, 0x29, 0x4e, 0xd0, 0xf5, ++ 0x66, 0x76, 0xf3, 0xbf, 0xd2, 0xee, 0xc7, 0xc7, 0x25, 0x70, 0xb9, 0x19, ++ 0x86, 0x8e, 0xda, 0xf3, 0x1a, 0x1d, 0x35, 0xfa, 0x4d, 0xc0, 0xb1, 0x28, ++ 0x3f, 0xfb, 0xbe, 0x36, 0xa9, 0x11, 0xdc, 0x3f, 0x46, 0xfa, 0xcd, 0xb8, ++ 0xaa, 0xd0, 0x3c, 0xa3, 0xe2, 0x42, 0xfd, 0x96, 0x2f, 0xcf, 0xe7, 0xfe, ++ 0x27, 0xc5, 0x74, 0x62, 0x7c, 0x5d, 0xfb, 0x25, 0x93, 0x7b, 0xfc, 0xf0, ++ 0xf0, 0x5f, 0xcf, 0x2f, 0xbd, 0x59, 0xf3, 0xc3, 0x85, 0x5f, 0xae, 0xbd, ++ 0x77, 0x26, 0xc8, 0x78, 0x0a, 0x3a, 0x86, 0x3a, 0xfb, 0xa1, 0xbd, 0xe7, ++ 0xba, 0xf6, 0x42, 0x3c, 0xaf, 0xa7, 0xd3, 0xe4, 0xb8, 0xd0, 0x78, 0x42, ++ 0xa3, 0x87, 0xa6, 0x47, 0x07, 0xe1, 0x5b, 0xe8, 0xd9, 0xe1, 0xe8, 0x75, ++ 0x3d, 0x3d, 0xab, 0xe9, 0xb3, 0x7f, 0xb5, 0x9e, 0xd5, 0xe6, 0xd7, 0xec, ++ 0x80, 0xf6, 0x5e, 0xbd, 0xfe, 0x1d, 0x2e, 0x3e, 0xd3, 0xf4, 0xe9, 0x53, ++ 0x1b, 0x0d, 0x94, 0x17, 0xb9, 0x4d, 0xc4, 0xc1, 0xb7, 0x89, 0x3c, 0xeb, ++ 0x83, 0x42, 0xce, 0x97, 0x0b, 0x7d, 0xdb, 0xff, 0x17, 0x8b, 0x01, 0xfd, ++ 0xac, 0x6d, 0x9d, 0xdc, 0x1f, 0x71, 0x98, 0xed, 0x87, 0xd0, 0x6f, 0x08, ++ 0xe4, 0xf3, 0x38, 0x5d, 0x9f, 0x8c, 0x60, 0x1e, 0xdc, 0x2f, 0x67, 0x4a, ++ 0xaf, 0x85, 0xf6, 0x2f, 0x8b, 0x81, 0xa4, 0xb8, 0x7f, 0x99, 0xcc, 0xf7, ++ 0x2f, 0xb7, 0x28, 0x3e, 0x17, 0xe9, 0x69, 0x87, 0xc2, 0x1a, 0x40, 0x5e, ++ 0xfe, 0x2a, 0xf2, 0x16, 0x4f, 0xee, 0xf5, 0x2c, 0x46, 0x3d, 0xfd, 0xe4, ++ 0xe9, 0x31, 0x06, 0xda, 0x47, 0x57, 0x7c, 0xbd, 0x18, 0x17, 0x4f, 0xca, ++ 0x55, 0x68, 0x3f, 0x28, 0xda, 0xac, 0x52, 0xbe, 0xf7, 0x62, 0x87, 0xd9, ++ 0x8e, 0xcf, 0xf5, 0xef, 0xfe, 0x5e, 0x97, 0x11, 0xe7, 0xf9, 0x0b, 0x73, ++ 0x60, 0xa8, 0xf6, 0x76, 0x87, 0x79, 0x60, 0x3f, 0x06, 0xf5, 0x42, 0x99, ++ 0xdc, 0x23, 0x63, 0x5e, 0xbe, 0xdf, 0x0f, 0xbe, 0x38, 0x8c, 0x9f, 0xb6, ++ 0xd0, 0x57, 0x82, 0xf1, 0xce, 0x6d, 0xac, 0xb7, 0x11, 0xe3, 0xea, 0x42, ++ 0xa4, 0xe3, 0x10, 0xf4, 0x7b, 0x55, 0x67, 0x5f, 0xf4, 0x79, 0xfb, 0x92, ++ 0x0e, 0xee, 0x27, 0x95, 0x44, 0xf0, 0xba, 0x9f, 0xe9, 0x80, 0x46, 0x7c, ++ 0xef, 0xf4, 0x36, 0x13, 0xf9, 0x85, 0xd7, 0xcb, 0xdb, 0x17, 0x7d, 0xc9, ++ 0xc8, 0x5f, 0x1a, 0x94, 0xaf, 0x6f, 0xe3, 0x7a, 0x06, 0x06, 0x11, 0x9f, ++ 0xdc, 0x68, 0xde, 0xbe, 0x10, 0x7d, 0x3d, 0xe0, 0xe3, 0x9f, 0xe8, 0xf4, ++ 0x0e, 0x1b, 0x26, 0x7f, 0xbf, 0xcd, 0xc4, 0xf7, 0x73, 0xfc, 0x47, 0x8c, ++ 0x0c, 0xfd, 0x5e, 0x76, 0x2e, 0x6e, 0xc8, 0xbc, 0xcb, 0xf5, 0xf2, 0xf8, ++ 0xbb, 0x3b, 0xc3, 0x9d, 0x6a, 0x24, 0xee, 0xbb, 0x71, 0xff, 0x7c, 0x77, ++ 0x67, 0xb2, 0x53, 0xcd, 0x19, 0x7e, 0x7c, 0x4e, 0x9f, 0xbf, 0x18, 0xf3, ++ 0x95, 0xdb, 0xb6, 0xcc, 0x55, 0x28, 0x4e, 0x14, 0xf9, 0xcf, 0x41, 0xfb, ++ 0x22, 0x3a, 0xfc, 0xed, 0x90, 0x58, 0x93, 0x15, 0xf3, 0x69, 0xed, 0x8e, ++ 0x52, 0x8c, 0x3f, 0x86, 0xdb, 0xe7, 0x28, 0xf6, 0x3b, 0x69, 0xde, 0x1b, ++ 0xc5, 0x1b, 0x63, 0xcd, 0x9c, 0xce, 0xa2, 0x7e, 0xe9, 0x76, 0x21, 0x63, ++ 0xdb, 0xce, 0x86, 0x3b, 0x91, 0xbf, 0xb7, 0x9d, 0x4d, 0x76, 0x22, 0x3c, ++ 0xbb, 0x05, 0x7f, 0x6a, 0xfc, 0xbe, 0xfb, 0xcc, 0xe5, 0x70, 0xda, 0xcf, ++ 0x34, 0x39, 0x55, 0xdc, 0x07, 0xf6, 0x47, 0x5b, 0x1c, 0x2f, 0x13, 0xbf, ++ 0x72, 0x3e, 0x6f, 0x19, 0x31, 0xc6, 0x8b, 0xfb, 0xad, 0xdb, 0x85, 0x3c, ++ 0x6c, 0x0b, 0xf7, 0x1f, 0xcc, 0x8a, 0x0b, 0xde, 0xcf, 0xe0, 0xfb, 0x17, ++ 0x9d, 0xf5, 0x9e, 0xaa, 0x33, 0xe9, 0xb4, 0xdf, 0x2d, 0x61, 0xbe, 0x51, ++ 0xdb, 0x27, 0xf6, 0x80, 0xbc, 0x50, 0x5d, 0x4e, 0x0c, 0x23, 0x7e, 0x32, ++ 0xb2, 0x16, 0x86, 0xef, 0x6d, 0x74, 0xb2, 0x9f, 0x63, 0x3b, 0x7d, 0x9a, ++ 0x1a, 0x85, 0xf8, 0xbe, 0x1c, 0xa7, 0xed, 0x47, 0xaa, 0x51, 0x94, 0x67, ++ 0xf8, 0xf6, 0x4a, 0x81, 0x6b, 0xfc, 0x60, 0xbc, 0xef, 0xa8, 0x77, 0x51, ++ 0x3d, 0x49, 0x6b, 0xfd, 0xc2, 0x2a, 0x05, 0x60, 0x7c, 0xb3, 0xde, 0x4d, ++ 0x6d, 0x5b, 0xfd, 0x72, 0x6a, 0xf7, 0xd4, 0xaf, 0xa6, 0xfb, 0x6b, 0x0f, ++ 0x45, 0x3e, 0x8e, 0x76, 0xbf, 0xce, 0xb9, 0xa0, 0x4a, 0x09, 0xd2, 0x1b, ++ 0x9f, 0xc5, 0xf3, 0xfc, 0x52, 0x6e, 0xd6, 0xe9, 0x12, 0xe4, 0x73, 0xf6, ++ 0x0d, 0x63, 0x18, 0xef, 0x4c, 0x7f, 0xa2, 0x4f, 0x46, 0x3d, 0x71, 0xfb, ++ 0x55, 0x58, 0x47, 0x48, 0xdd, 0x88, 0x72, 0x19, 0xf1, 0x4c, 0xf9, 0xcb, ++ 0xb4, 0x40, 0x3f, 0x55, 0x5a, 0x12, 0x86, 0x7c, 0x79, 0xfb, 0x55, 0xe8, ++ 0x07, 0x8d, 0x97, 0xe2, 0xa3, 0x39, 0x1d, 0x9a, 0x94, 0xa6, 0x5b, 0x0a, ++ 0x48, 0x5a, 0x88, 0x1f, 0xc2, 0xe2, 0x9d, 0x17, 0xe3, 0xe0, 0xfa, 0x0f, ++ 0xed, 0x2e, 0x7f, 0x5c, 0x3c, 0xf2, 0x41, 0xf5, 0xbe, 0x0b, 0x8c, 0xfa, ++ 0x97, 0xf1, 0xfa, 0x0e, 0xe9, 0x6e, 0xf9, 0x02, 0x8c, 0xcb, 0xf3, 0x15, ++ 0x51, 0xde, 0x38, 0x0f, 0xf3, 0xc6, 0xb9, 0x34, 0xed, 0x62, 0xc4, 0xdf, ++ 0xc4, 0x2e, 0x13, 0xed, 0x7b, 0x6b, 0xf9, 0xdb, 0x5c, 0x31, 0xaf, 0xf3, ++ 0xab, 0xd0, 0x3c, 0x72, 0x9e, 0xc8, 0xdb, 0xbe, 0xc9, 0xfa, 0x28, 0x9f, ++ 0x9c, 0x6f, 0x81, 0xc0, 0xca, 0x80, 0x70, 0x71, 0xfa, 0x39, 0xa5, 0xf9, ++ 0x49, 0x12, 0xe6, 0xfb, 0xe2, 0x4d, 0x0e, 0xac, 0x57, 0x98, 0x98, 0xe6, ++ 0xca, 0xc3, 0x7c, 0x6b, 0x57, 0x3c, 0xa3, 0xfc, 0x69, 0x57, 0x57, 0xc2, ++ 0x48, 0x15, 0xf0, 0xe0, 0x54, 0x78, 0x5e, 0xd7, 0xa9, 0xe5, 0x75, 0xd9, ++ 0xdf, 0xcf, 0xeb, 0x76, 0x7f, 0x1a, 0xe9, 0x21, 0x7d, 0x05, 0x7e, 0x0a, ++ 0xea, 0xa7, 0xee, 0xa3, 0x91, 0x0e, 0x1f, 0xed, 0xff, 0x59, 0xc8, 0xff, ++ 0xdb, 0x81, 0x0f, 0x62, 0x7d, 0x43, 0x38, 0xaf, 0x17, 0x60, 0xf3, 0xe6, ++ 0x51, 0x1e, 0xfd, 0x76, 0x0b, 0x5f, 0x07, 0xd8, 0x9f, 0xf8, 0x78, 0xca, ++ 0xfb, 0xf9, 0xf6, 0x1d, 0x86, 0xe7, 0x7e, 0x7b, 0x99, 0xf1, 0x7d, 0xc4, ++ 0xde, 0x93, 0xb4, 0x3f, 0x5d, 0x62, 0xc8, 0x4c, 0xec, 0x03, 0x38, 0xf7, ++ 0x49, 0x63, 0xa3, 0xb0, 0x7d, 0xf1, 0xd3, 0xc8, 0x6c, 0x6a, 0x8f, 0x46, ++ 0x9e, 0x47, 0xfc, 0x74, 0x1a, 0xac, 0x2a, 0xbe, 0xf7, 0xc3, 0x7a, 0x56, ++ 0x85, 0x75, 0x67, 0xce, 0xf7, 0x6d, 0xb4, 0x9f, 0x31, 0xfd, 0x7d, 0x9b, ++ 0x82, 0xed, 0xe1, 0xfa, 0x3e, 0xaa, 0x47, 0x7b, 0xbf, 0xfe, 0x1c, 0xb5, ++ 0x47, 0xea, 0xfd, 0xd4, 0x1e, 0xad, 0xbf, 0x4a, 0xed, 0x3b, 0x70, 0x1d, ++ 0xf9, 0xe7, 0x10, 0x3c, 0x8f, 0x6d, 0xee, 0xe2, 0x08, 0x7a, 0x6e, 0xc7, ++ 0xa2, 0x08, 0x13, 0xc2, 0xdb, 0x19, 0xc9, 0xb6, 0x68, 0xef, 0xc1, 0x7a, ++ 0x33, 0x5f, 0xb8, 0xaf, 0x15, 0x93, 0xf9, 0xef, 0xc5, 0x7f, 0xbe, 0xce, ++ 0x72, 0x13, 0xd8, 0x3b, 0xb3, 0x7b, 0xbc, 0x34, 0x81, 0xb1, 0x13, 0xf1, ++ 0x9f, 0xcf, 0x54, 0xa0, 0x7f, 0x68, 0xc6, 0xa8, 0x7f, 0xff, 0x0b, 0xdc, ++ 0xff, 0xdd, 0x4f, 0x2e, 0xac, 0xb3, 0x00, 0x5c, 0xf3, 0x8e, 0xda, 0x5a, ++ 0x7b, 0xa0, 0xff, 0xe9, 0x4f, 0x2e, 0xae, 0xb3, 0xa1, 0x9e, 0x3d, 0x14, ++ 0x0e, 0xca, 0x0e, 0xf5, 0x46, 0xff, 0x41, 0x90, 0x74, 0x96, 0x87, 0x36, ++ 0x3d, 0x99, 0x71, 0x05, 0x3b, 0x19, 0xfa, 0xb1, 0xa2, 0xef, 0xe9, 0x9f, ++ 0x59, 0x0a, 0x24, 0x5f, 0x50, 0xd2, 0x97, 0xc5, 0x80, 0xb5, 0xa6, 0xfc, ++ 0xc4, 0x3f, 0xd3, 0x02, 0x78, 0x5c, 0x60, 0x75, 0xff, 0x1b, 0xf6, 0x4d, ++ 0x9e, 0x97, 0x66, 0x96, 0xde, 0x84, 0x7d, 0xe6, 0xc1, 0x7a, 0x2e, 0xbf, ++ 0x64, 0xa4, 0xf8, 0x9e, 0x8d, 0x94, 0xe2, 0xb0, 0x7e, 0x65, 0x99, 0xdd, ++ 0x7d, 0x2c, 0x3e, 0xc8, 0x7e, 0x3b, 0xa5, 0x3f, 0xd2, 0xfe, 0x51, 0x81, ++ 0x53, 0x62, 0xd1, 0x71, 0x44, 0x57, 0xda, 0xcf, 0x62, 0xf6, 0x53, 0xb1, ++ 0xc1, 0xf2, 0xb6, 0xcc, 0x5e, 0x76, 0x0c, 0xe9, 0x71, 0x47, 0x3c, 0xdf, ++ 0xbf, 0x9a, 0x38, 0x4d, 0x72, 0x06, 0xd7, 0x49, 0xe8, 0xc7, 0x4d, 0x3c, ++ 0xa3, 0x96, 0x22, 0x9d, 0x0a, 0xce, 0x95, 0x37, 0x61, 0x3b, 0xbb, 0x22, ++ 0x9a, 0xfa, 0xae, 0x85, 0x93, 0x9a, 0x50, 0x9e, 0x4b, 0x6d, 0xc3, 0x3d, ++ 0x5f, 0x42, 0xcf, 0x2f, 0x88, 0x37, 0x12, 0x7f, 0x16, 0x2b, 0x52, 0x48, ++ 0x7d, 0x88, 0x7e, 0x5c, 0x1e, 0x30, 0x13, 0xfa, 0xc7, 0xfe, 0x03, 0xe1, ++ 0x94, 0x17, 0x98, 0x78, 0xcc, 0xdd, 0x88, 0x75, 0xa3, 0x65, 0x49, 0xa9, ++ 0xb9, 0xb2, 0xd0, 0x79, 0x8c, 0xfa, 0xd1, 0x1b, 0x71, 0x1f, 0x6d, 0x62, ++ 0xe5, 0x87, 0xa5, 0xb1, 0x28, 0x3f, 0x36, 0xc9, 0x81, 0xe6, 0xa1, 0x80, ++ 0xf5, 0x35, 0xc5, 0xc6, 0x61, 0xfd, 0x23, 0x16, 0x44, 0xe1, 0xba, 0x9e, ++ 0x2b, 0xc1, 0xfa, 0x9d, 0x89, 0xaa, 0xe4, 0x40, 0xb4, 0x15, 0x39, 0xbb, ++ 0x5a, 0xf1, 0xf9, 0x22, 0x47, 0x84, 0xa3, 0x08, 0xfd, 0xf1, 0x63, 0x6a, ++ 0x29, 0x9a, 0x9c, 0xa3, 0xca, 0x84, 0xc3, 0xf9, 0x30, 0x6e, 0x46, 0xba, ++ 0xec, 0xb0, 0xc0, 0x44, 0x47, 0x7d, 0x77, 0x4c, 0xbd, 0x00, 0xfd, 0xa2, ++ 0x8c, 0x28, 0xca, 0xe3, 0x16, 0x29, 0xab, 0xaf, 0x1c, 0xa6, 0x7e, 0x84, ++ 0xa3, 0x41, 0xc5, 0x75, 0x6c, 0xfc, 0x79, 0x2d, 0xcd, 0x63, 0x26, 0x7b, ++ 0xbe, 0x63, 0x56, 0xc9, 0x7f, 0x20, 0xff, 0x14, 0xbb, 0xa2, 0x28, 0xe7, ++ 0x57, 0x6a, 0x3b, 0x35, 0x37, 0xb8, 0x2e, 0x0c, 0xd6, 0x4d, 0x70, 0x17, ++ 0xd9, 0x65, 0x6f, 0x98, 0x84, 0xfc, 0xfd, 0x83, 0x52, 0x3b, 0xf4, 0x77, ++ 0x8c, 0x92, 0x18, 0xca, 0xcf, 0x51, 0x5f, 0xe6, 0x9f, 0xe9, 0x7e, 0x77, ++ 0xb8, 0x1a, 0x06, 0x80, 0xee, 0x30, 0xd9, 0x4b, 0x71, 0xbe, 0x1d, 0x26, ++ 0xc9, 0xbe, 0x96, 0xfa, 0xae, 0x12, 0x1c, 0xef, 0x19, 0x63, 0x54, 0x31, ++ 0x4f, 0x54, 0x1e, 0xf7, 0x45, 0xc8, 0xfc, 0x33, 0x4a, 0xa5, 0x29, 0x67, ++ 0x10, 0xfe, 0xec, 0xa8, 0x09, 0x78, 0xad, 0x62, 0xe4, 0xa5, 0x90, 0xfb, ++ 0x3d, 0x8b, 0xac, 0x64, 0x27, 0x2a, 0xdf, 0xcf, 0x26, 0x7f, 0xa8, 0x67, ++ 0x51, 0x0a, 0xd9, 0x8b, 0xca, 0xf7, 0xa7, 0x15, 0x63, 0xdb, 0x63, 0xe0, ++ 0x7e, 0x7a, 0xe5, 0xfb, 0x95, 0x15, 0x74, 0xdf, 0xc0, 0xe3, 0xdf, 0xca, ++ 0xc5, 0xdf, 0x71, 0x8a, 0x3e, 0xc5, 0xbb, 0x95, 0x8b, 0x57, 0x51, 0xbf, ++ 0x4b, 0x4a, 0xfc, 0x77, 0x7c, 0xdf, 0x95, 0xec, 0xa8, 0x5c, 0xcc, 0xa3, ++ 0xcd, 0x4c, 0xff, 0x7a, 0xae, 0x12, 0xec, 0xff, 0xad, 0xce, 0x24, 0xf9, ++ 0xcf, 0x15, 0x79, 0xbc, 0x22, 0x43, 0xe6, 0xfa, 0x69, 0x00, 0xff, 0xa3, ++ 0x07, 0xf8, 0x3e, 0x44, 0x65, 0xb6, 0x14, 0x52, 0x37, 0x37, 0x2b, 0xff, ++ 0x54, 0x48, 0x3d, 0xa8, 0x6b, 0xda, 0x17, 0x21, 0xfd, 0xb9, 0xa5, 0x97, ++ 0x42, 0xea, 0x43, 0xe7, 0x55, 0x7e, 0x1d, 0xd2, 0x5f, 0x30, 0x4f, 0xaa, ++ 0x0a, 0x1e, 0x5f, 0x7a, 0x20, 0x9f, 0xec, 0x6b, 0xbe, 0xa8, 0x5f, 0xd2, ++ 0xf2, 0x4b, 0x45, 0x82, 0x85, 0xde, 0xa9, 0xcf, 0xa8, 0x2a, 0x05, 0xb9, ++ 0x3c, 0x00, 0xed, 0x03, 0xa0, 0x1f, 0x8a, 0x7a, 0x45, 0xde, 0x55, 0xe1, ++ 0x71, 0x75, 0x06, 0xfc, 0x43, 0x3d, 0x58, 0x6a, 0xd3, 0xe5, 0x77, 0x99, ++ 0x4a, 0xfb, 0xd9, 0x15, 0xdd, 0x7c, 0xdf, 0xba, 0x3c, 0xce, 0x78, 0x3a, ++ 0xd8, 0x3e, 0x54, 0xc8, 0x4f, 0x70, 0x7f, 0x41, 0xb7, 0xfe, 0xdc, 0x03, ++ 0x46, 0xb2, 0x93, 0xb9, 0xd1, 0x32, 0xe5, 0xab, 0x34, 0xf8, 0x2a, 0x46, ++ 0x86, 0x3e, 0xaf, 0xf9, 0x5f, 0x15, 0x02, 0xce, 0x1d, 0x06, 0x77, 0x53, ++ 0x0c, 0xe5, 0xc7, 0x9c, 0xbd, 0xe8, 0x7f, 0x68, 0xf0, 0x6b, 0xef, 0xd7, ++ 0xe0, 0xae, 0x90, 0xef, 0x29, 0xa5, 0xed, 0xbf, 0xeb, 0xc0, 0xaf, 0x87, ++ 0x17, 0x00, 0x25, 0xff, 0x4d, 0x0f, 0xc7, 0x81, 0x78, 0x11, 0x87, 0x80, ++ 0xbf, 0x41, 0xfe, 0x59, 0x37, 0xaf, 0x4b, 0x83, 0x5f, 0xdc, 0x50, 0x76, ++ 0x5b, 0xf3, 0xcf, 0x2b, 0x41, 0x4f, 0x45, 0x07, 0xeb, 0x29, 0x9b, 0x14, ++ 0x87, 0xf5, 0x76, 0xc3, 0xe9, 0x29, 0x6d, 0xde, 0xe1, 0xfc, 0x30, 0x6d, ++ 0xde, 0x65, 0x76, 0x17, 0x3d, 0xef, 0xdc, 0xfa, 0xd9, 0xd1, 0x42, 0x39, ++ 0xa8, 0x9f, 0x7a, 0x2a, 0x36, 0x26, 0xb8, 0xff, 0xda, 0x67, 0xeb, 0x43, ++ 0xee, 0xc7, 0x9f, 0xaa, 0x8a, 0x0e, 0xee, 0x6f, 0xfa, 0xac, 0x0a, 0xef, ++ 0x4f, 0x57, 0xd4, 0x46, 0x1b, 0xf0, 0xe3, 0x41, 0x26, 0x39, 0x3c, 0xc8, ++ 0x9f, 0x3d, 0xaa, 0x82, 0xfb, 0xcf, 0x25, 0xc7, 0x9c, 0x4d, 0xd8, 0x96, ++ 0x9d, 0x74, 0x63, 0x99, 0x29, 0x9b, 0x71, 0xc6, 0xd3, 0x84, 0xed, 0xd4, ++ 0xf3, 0xde, 0x1e, 0x33, 0xac, 0xeb, 0x8e, 0x0c, 0x59, 0xc5, 0xb8, 0x5d, ++ 0xf3, 0x3f, 0xf4, 0xf0, 0x9a, 0x13, 0x78, 0x1c, 0x72, 0xf0, 0xaa, 0x6a, ++ 0xc5, 0xfd, 0xd3, 0x1d, 0x1e, 0xd5, 0x8a, 0xfe, 0xfb, 0x8e, 0x27, 0x54, ++ 0x2b, 0xfa, 0x1f, 0x3b, 0x9c, 0xac, 0x02, 0xe3, 0x31, 0x67, 0x9a, 0x61, ++ 0x35, 0xfa, 0xf3, 0xce, 0x2c, 0x5e, 0x67, 0x78, 0x55, 0xe8, 0xe1, 0x6f, ++ 0xe2, 0xf9, 0xf3, 0x5a, 0x7b, 0x5a, 0x71, 0x7f, 0x83, 0x7a, 0x11, 0xeb, ++ 0xc2, 0xd1, 0x27, 0xa8, 0xfd, 0xda, 0x4f, 0x75, 0xe0, 0x07, 0xd1, 0xaf, ++ 0xca, 0x1e, 0xec, 0x57, 0x1d, 0x54, 0xbc, 0x36, 0x7c, 0xdf, 0xc1, 0x27, ++ 0xbc, 0xb6, 0xe0, 0x7d, 0xc2, 0x1b, 0xf5, 0xab, 0xfe, 0x8c, 0x36, 0x3a, ++ 0x1e, 0xf9, 0x6c, 0x4e, 0x88, 0x7c, 0x96, 0x58, 0xee, 0xae, 0x0a, 0x96, ++ 0xef, 0x32, 0xfb, 0x92, 0x90, 0xfb, 0x9f, 0xc6, 0xa9, 0x04, 0xff, 0x8c, ++ 0xa4, 0x87, 0x43, 0xc6, 0xdd, 0xa1, 0x3e, 0x12, 0xd2, 0x07, 0x7f, 0x31, ++ 0x03, 0xfd, 0x91, 0x46, 0x13, 0xa3, 0x3a, 0x59, 0x8f, 0x81, 0xd7, 0xc9, ++ 0xea, 0xf1, 0xf8, 0xa8, 0xc0, 0xa3, 0xc3, 0x66, 0x47, 0x37, 0x86, 0x19, ++ 0xe3, 0x54, 0xaa, 0x6b, 0xd3, 0x8f, 0x73, 0x94, 0x70, 0xfc, 0xe9, 0xaf, ++ 0xa7, 0x27, 0xf0, 0xb8, 0x68, 0x23, 0xc8, 0x0c, 0xb6, 0xf7, 0x24, 0x70, ++ 0xf8, 0xf4, 0x75, 0xb1, 0xfa, 0x3e, 0xc4, 0x7c, 0x0b, 0x71, 0x3e, 0x98, ++ 0x39, 0x09, 0xf9, 0xdc, 0x61, 0x35, 0x5c, 0x01, 0x57, 0x97, 0x39, 0x13, ++ 0x92, 0xee, 0xa4, 0x7a, 0xd9, 0x3c, 0xc3, 0xa3, 0x69, 0xd0, 0xaf, 0x4e, ++ 0xc8, 0xe2, 0xfd, 0xa9, 0x86, 0x9d, 0x58, 0x1f, 0x7b, 0x77, 0x42, 0x36, ++ 0xef, 0xdf, 0x6a, 0xc8, 0x33, 0x82, 0x1f, 0xf0, 0x2b, 0x36, 0xfe, 0x4e, ++ 0xac, 0x07, 0xaf, 0x0d, 0x13, 0x75, 0x9d, 0x0f, 0x24, 0xd2, 0x7e, 0x98, ++ 0x16, 0xdf, 0x28, 0x86, 0x53, 0x2f, 0x2e, 0xc6, 0x38, 0x73, 0x8f, 0x91, ++ 0x61, 0xfe, 0xfe, 0x19, 0x13, 0xd8, 0xbd, 0xdc, 0xc0, 0xbe, 0xb9, 0xd5, ++ 0xcc, 0xe3, 0x52, 0xab, 0x89, 0xd7, 0x6d, 0x3f, 0x95, 0x7a, 0xf4, 0x29, ++ 0xd4, 0x1b, 0x6a, 0x98, 0x7b, 0x7a, 0x02, 0xf9, 0x51, 0xc5, 0x2a, 0xe2, ++ 0xef, 0xbc, 0xdd, 0x42, 0x75, 0x9d, 0x8f, 0xed, 0x2e, 0x4b, 0x44, 0xfa, ++ 0xdf, 0x93, 0xc0, 0xf3, 0x5c, 0x59, 0x3b, 0xa7, 0x26, 0xa1, 0x7e, 0xf9, ++ 0x17, 0xbc, 0x7f, 0x56, 0xc2, 0xc4, 0xe1, 0xdf, 0x8f, 0x75, 0xbe, 0x38, ++ 0xcf, 0xf9, 0x1d, 0x59, 0xe4, 0x7f, 0x67, 0xdd, 0x0c, 0xe8, 0x95, 0x02, ++ 0xf8, 0x87, 0xf0, 0x98, 0xae, 0x87, 0x41, 0x98, 0x40, 0xe7, 0x25, 0x98, ++ 0x33, 0x09, 0xf3, 0x6c, 0x8d, 0xd1, 0x26, 0x9a, 0xe7, 0x9e, 0x04, 0xce, ++ 0x7f, 0x37, 0xda, 0x0e, 0xaa, 0xfb, 0x8d, 0x32, 0xac, 0xde, 0x0e, 0xed, ++ 0xfd, 0x82, 0xfe, 0x0f, 0xe0, 0x7b, 0x09, 0x5f, 0xfe, 0x51, 0x73, 0x70, ++ 0x63, 0xce, 0xee, 0x1f, 0x35, 0x77, 0x3c, 0xef, 0x23, 0x7d, 0x65, 0x39, ++ 0xd7, 0x8f, 0x7e, 0xac, 0xff, 0x3b, 0x11, 0xb4, 0xaf, 0xc2, 0x46, 0xfa, ++ 0x69, 0xff, 0xe5, 0xe3, 0x7b, 0xb2, 0x1c, 0xe8, 0x9f, 0x7e, 0x12, 0xce, ++ 0xf1, 0xb7, 0xd0, 0x3b, 0xba, 0xb1, 0x4f, 0xc5, 0xfa, 0x0d, 0xef, 0x4d, ++ 0x58, 0x2f, 0x91, 0x91, 0xe8, 0xae, 0x45, 0x3c, 0x2c, 0x32, 0x7b, 0x6f, ++ 0x21, 0xfe, 0xb1, 0xad, 0x8e, 0xc0, 0xf9, 0x6f, 0xb4, 0x1e, 0x78, 0xf0, ++ 0x7b, 0x21, 0x80, 0x04, 0xfa, 0x54, 0x4f, 0xe1, 0xf4, 0xd1, 0xde, 0x0b, ++ 0x38, 0xb5, 0xa0, 0x3d, 0xf8, 0x58, 0x9c, 0x03, 0xd1, 0xe0, 0x80, 0xf7, ++ 0xff, 0x00, 0xf9, 0x40, 0x83, 0x67, 0x00, 0x0e, 0x5d, 0x5d, 0xb8, 0x96, ++ 0x67, 0xae, 0xfb, 0xa3, 0x81, 0xf2, 0x0c, 0x75, 0x12, 0xe8, 0x3d, 0xe8, ++ 0xef, 0x3c, 0xc9, 0x1c, 0x1e, 0x98, 0xe7, 0xa2, 0xe6, 0xaf, 0x8b, 0xbc, ++ 0x26, 0x6e, 0x45, 0xe1, 0x7b, 0xa6, 0x1c, 0x5e, 0x5a, 0x62, 0x83, 0x36, ++ 0xbf, 0x6d, 0x25, 0x8f, 0x73, 0x7b, 0x95, 0x90, 0x3c, 0xd7, 0xa4, 0xe3, ++ 0x8a, 0x7e, 0xbf, 0x83, 0xec, 0xd6, 0x54, 0xed, 0x79, 0x5d, 0x9e, 0x71, ++ 0xaa, 0x88, 0x6b, 0xa7, 0xea, 0xe2, 0xda, 0x17, 0x13, 0x84, 0x9d, 0x49, ++ 0x66, 0xc9, 0xc1, 0x79, 0x80, 0x35, 0x22, 0x6e, 0xb8, 0xdc, 0x33, 0x3a, ++ 0x0a, 0xfd, 0x4c, 0xd4, 0x51, 0x32, 0xe0, 0xd5, 0xa4, 0xca, 0x6c, 0x72, ++ 0x4c, 0x40, 0xce, 0x5b, 0x21, 0xee, 0x67, 0x41, 0x71, 0xbf, 0xc6, 0x67, ++ 0xe3, 0x8f, 0xd9, 0xef, 0x47, 0xb8, 0xc7, 0x1f, 0x63, 0xf7, 0x91, 0x5d, ++ 0xd7, 0xe6, 0x1d, 0xc8, 0x2f, 0x70, 0xbc, 0x5c, 0x3e, 0xce, 0xf1, 0x32, ++ 0xa1, 0x2f, 0xe3, 0xa7, 0xd3, 0xa0, 0x6f, 0xec, 0x36, 0x32, 0xaf, 0x1a, ++ 0x58, 0x4f, 0x21, 0x07, 0x95, 0x5d, 0xc6, 0xff, 0xe0, 0x78, 0xbb, 0xc9, ++ 0x8b, 0x75, 0xcb, 0x05, 0x07, 0x7e, 0x99, 0xe7, 0x83, 0x4b, 0xe6, 0x24, ++ 0x03, 0x53, 0x83, 0xf0, 0x10, 0xa6, 0x86, 0x33, 0x35, 0x48, 0x2f, 0x5a, ++ 0x33, 0x62, 0x42, 0xfa, 0xb2, 0x86, 0x6f, 0x61, 0xcf, 0xf3, 0xc4, 0xfc, ++ 0x11, 0x8e, 0xe4, 0x90, 0x79, 0xf6, 0xc4, 0x94, 0x77, 0xa3, 0x7d, 0xcf, ++ 0xb3, 0x2d, 0x27, 0xfb, 0x1e, 0x35, 0x79, 0x74, 0xc8, 0x3c, 0xac, 0x47, ++ 0x09, 0xb1, 0xf3, 0xb0, 0x28, 0xda, 0xbf, 0x9c, 0x08, 0x40, 0xfd, 0x0c, ++ 0xf0, 0x5a, 0x70, 0x4c, 0x09, 0xb1, 0xe7, 0x93, 0xe2, 0x3c, 0xb8, 0x62, ++ 0x36, 0xf9, 0xa4, 0xa2, 0xb3, 0xff, 0xcd, 0x32, 0xca, 0x41, 0xe1, 0x99, ++ 0xd0, 0xeb, 0x07, 0x86, 0xa3, 0xcb, 0x70, 0xf8, 0x63, 0x39, 0x3f, 0x45, ++ 0xff, 0xee, 0x1f, 0xc5, 0x5f, 0xb4, 0x33, 0x14, 0x7f, 0xb1, 0x15, 0xa1, ++ 0xf8, 0x8b, 0x77, 0x85, 0xe2, 0x2f, 0x71, 0x61, 0x28, 0x9e, 0x46, 0xb8, ++ 0x43, 0xf1, 0x92, 0xb2, 0x7c, 0x5c, 0xc8, 0xfd, 0x9b, 0x56, 0xe7, 0x86, ++ 0xf4, 0x6f, 0x7e, 0xbc, 0x30, 0x64, 0x7c, 0x2a, 0x18, 0xa4, 0xe0, 0x7e, ++ 0xda, 0xd3, 0x33, 0x43, 0xc6, 0xdf, 0xd2, 0x3c, 0x37, 0xa4, 0x3f, 0x76, ++ 0xc3, 0xa2, 0x90, 0xf1, 0x99, 0xde, 0xa5, 0x21, 0xf7, 0xb3, 0x5e, 0x5d, ++ 0x71, 0x43, 0xf4, 0x1e, 0xdf, 0xb2, 0x26, 0x64, 0x9c, 0x9e, 0xde, 0xb7, ++ 0xb6, 0xfd, 0xaf, 0x90, 0x79, 0x35, 0x7a, 0x7b, 0xe0, 0xdf, 0xbf, 0x82, ++ 0xde, 0xe6, 0xc4, 0x50, 0x7a, 0xa7, 0x0a, 0xfd, 0x1a, 0xed, 0xe4, 0xf5, ++ 0x65, 0xfd, 0x46, 0xdb, 0xd3, 0x12, 0xe8, 0x23, 0x4c, 0x13, 0xa1, 0x5e, ++ 0x8b, 0x6e, 0x7f, 0xf7, 0x6b, 0xcc, 0x43, 0x78, 0x8a, 0x55, 0xaa, 0x9f, ++ 0xf3, 0xcc, 0x64, 0xb4, 0x0f, 0xfd, 0x82, 0xec, 0x92, 0x50, 0x0f, 0xa5, ++ 0xc0, 0x14, 0x86, 0x34, 0xaa, 0x5f, 0xa7, 0xfa, 0xbb, 0x1f, 0x1b, 0x0c, ++ 0x21, 0xfb, 0xe2, 0x89, 0x89, 0xdc, 0xbe, 0x27, 0x26, 0xf2, 0x7c, 0xcd, ++ 0xcf, 0x4d, 0xfc, 0xdc, 0x52, 0x0a, 0xf8, 0x8f, 0x64, 0x87, 0x0c, 0x2c, ++ 0x10, 0x2f, 0x03, 0x1e, 0x22, 0x31, 0x5e, 0xa6, 0x78, 0xfa, 0xc7, 0xcf, ++ 0x60, 0xbc, 0xdc, 0x14, 0xdd, 0x97, 0xa1, 0x42, 0x7c, 0x6c, 0xc6, 0xfe, ++ 0x4d, 0x01, 0x7d, 0xb9, 0xc8, 0xac, 0x36, 0xf6, 0x01, 0x3e, 0x26, 0xc8, ++ 0x5c, 0x1f, 0x82, 0x9e, 0x4c, 0x4b, 0x84, 0xf9, 0x3f, 0x91, 0x9e, 0x30, ++ 0x72, 0x3f, 0xc2, 0x63, 0x44, 0x3f, 0x22, 0xc5, 0xc2, 0x3c, 0x91, 0xb9, ++ 0x64, 0x3f, 0x28, 0x7f, 0x1c, 0xcd, 0xe2, 0x24, 0xac, 0xc7, 0x8f, 0x0a, ++ 0xe8, 0x69, 0xf5, 0x1a, 0x10, 0x6b, 0xdf, 0x8a, 0x2c, 0x3a, 0x07, 0xf5, ++ 0x1e, 0x42, 0x82, 0xfe, 0xaf, 0x25, 0x86, 0xec, 0xe8, 0xdd, 0x9a, 0x7e, ++ 0x5a, 0x9e, 0x49, 0xfa, 0xe9, 0xb2, 0x2d, 0xd4, 0x0f, 0xbb, 0xfc, 0x40, ++ 0x1a, 0x5d, 0x3f, 0x71, 0xaf, 0x99, 0xf6, 0xfb, 0x4f, 0x88, 0x3a, 0x44, ++ 0x6d, 0xfd, 0xe7, 0x84, 0xde, 0xfa, 0x53, 0xbd, 0x85, 0xda, 0xf3, 0xf5, ++ 0xf6, 0x10, 0x3d, 0xb6, 0x7c, 0xe3, 0xfa, 0x08, 0xf4, 0x1f, 0x4f, 0x64, ++ 0x70, 0x7f, 0x51, 0xbb, 0x5e, 0x82, 0x78, 0x9b, 0x88, 0xad, 0x2c, 0xec, ++ 0x9a, 0xc5, 0x8e, 0xf9, 0xac, 0x7b, 0xc0, 0x38, 0x47, 0x01, 0xbe, 0x57, ++ 0x75, 0xf7, 0x45, 0x2e, 0x62, 0xe4, 0x37, 0x16, 0xe3, 0xba, 0x6b, 0x37, ++ 0x5e, 0xb9, 0xf7, 0x4d, 0xe8, 0xd7, 0x19, 0xfc, 0x09, 0xdc, 0x3e, 0x78, ++ 0x78, 0xbd, 0xcc, 0xc7, 0x8c, 0xfc, 0xcf, 0xea, 0x6f, 0x58, 0x88, 0xff, ++ 0x34, 0x37, 0x91, 0xc7, 0xe9, 0x73, 0xc5, 0xfc, 0x0b, 0xa0, 0xb1, 0x03, ++ 0x9e, 0x16, 0x00, 0xfe, 0xa3, 0xb1, 0x7d, 0x77, 0x5a, 0x39, 0xf2, 0x27, ++ 0x5c, 0xa7, 0xf3, 0x69, 0xb3, 0xbb, 0x19, 0xd5, 0x9f, 0xcc, 0x71, 0xa7, ++ 0xd2, 0x3e, 0xe3, 0x51, 0xe6, 0xf8, 0x70, 0x17, 0x80, 0xf8, 0x9d, 0x44, ++ 0x95, 0xe0, 0x9c, 0xc7, 0x5c, 0xb4, 0x5f, 0xff, 0xd1, 0xbd, 0xab, 0x22, ++ 0x70, 0xdc, 0xc0, 0x7c, 0xda, 0x3c, 0xc0, 0x28, 0xe8, 0x6f, 0x7c, 0x1c, ++ 0xed, 0x31, 0x26, 0x60, 0xdc, 0x7f, 0x1b, 0xaf, 0x6f, 0x80, 0xf7, 0x59, ++ 0xf0, 0xba, 0xeb, 0x9e, 0x94, 0x27, 0xd1, 0x0e, 0x69, 0xef, 0xfb, 0x88, ++ 0xb9, 0x2f, 0x7c, 0x88, 0xfb, 0xdd, 0xcc, 0x41, 0xf3, 0x6a, 0xf3, 0x33, ++ 0x16, 0x13, 0xa2, 0x9f, 0x76, 0x2c, 0x5f, 0xf9, 0x69, 0x2c, 0xbc, 0x6f, ++ 0xcd, 0x01, 0x03, 0xe5, 0x13, 0xd6, 0x74, 0x98, 0x29, 0xee, 0xea, 0x5f, ++ 0xf1, 0xd7, 0xad, 0x2f, 0xc2, 0xfd, 0xfb, 0x52, 0xfa, 0x6e, 0x42, 0xbb, ++ 0xfc, 0xc9, 0x8a, 0x6f, 0xc6, 0x20, 0x3f, 0xdc, 0xbd, 0x01, 0xf4, 0x10, ++ 0xac, 0xb1, 0x30, 0xca, 0xfd, 0x70, 0x62, 0x50, 0x9c, 0x72, 0xe2, 0x81, ++ 0x2b, 0x11, 0x78, 0x1f, 0xec, 0xeb, 0xa6, 0x17, 0xd1, 0x38, 0x6e, 0x36, ++ 0x53, 0x7d, 0xef, 0x27, 0x2b, 0x36, 0x8f, 0x09, 0xf6, 0x47, 0x1f, 0x4d, ++ 0x2c, 0xaa, 0xc5, 0xe7, 0xd8, 0xe4, 0x1b, 0x3b, 0x6f, 0x58, 0xf2, 0x7a, ++ 0x66, 0x22, 0xd5, 0x63, 0x09, 0x7e, 0x7a, 0x58, 0xf0, 0xd3, 0x9a, 0xd7, ++ 0xc6, 0x92, 0x1f, 0xb5, 0x26, 0x62, 0x80, 0x9f, 0x78, 0x7f, 0x13, 0xaf, ++ 0xef, 0xd0, 0xd6, 0xf1, 0xa1, 0xe0, 0xc7, 0x15, 0xaf, 0x7f, 0x5d, 0x10, ++ 0x7c, 0xce, 0x74, 0x07, 0xf0, 0x91, 0x3a, 0x86, 0xef, 0x6b, 0xa9, 0x20, ++ 0x53, 0x3b, 0x7b, 0x2e, 0xe7, 0xe0, 0xfd, 0x57, 0x14, 0x77, 0x13, 0xc2, ++ 0xd7, 0x79, 0xf5, 0x74, 0x24, 0xf6, 0x77, 0xbe, 0xf7, 0x37, 0x82, 0x9f, ++ 0xcd, 0xbb, 0x31, 0x78, 0x51, 0x06, 0x3d, 0x05, 0x81, 0xfd, 0x65, 0xed, ++ 0xdc, 0xe5, 0xc2, 0xf6, 0xd8, 0x3c, 0xa4, 0x3b, 0xc8, 0x59, 0x33, 0xce, ++ 0xbf, 0xe8, 0x37, 0xaf, 0x5d, 0xf8, 0x1d, 0xe2, 0xa7, 0x63, 0xf3, 0xa6, ++ 0xef, 0xe3, 0x98, 0x1b, 0x3c, 0x7f, 0xc9, 0x84, 0x7d, 0x71, 0x08, 0x3c, ++ 0x80, 0x7d, 0xa1, 0xf8, 0xa0, 0x9f, 0x85, 0xf3, 0x73, 0x1d, 0x42, 0x8f, ++ 0x2a, 0xb8, 0x83, 0x9e, 0x86, 0xe7, 0x99, 0x1c, 0x2a, 0xf1, 0xb3, 0x93, ++ 0x1d, 0xc2, 0x7d, 0x97, 0xc6, 0x2e, 0x03, 0xc3, 0xba, 0x95, 0x48, 0xdc, ++ 0xb4, 0x09, 0xca, 0xb3, 0x45, 0xca, 0x06, 0xcd, 0x08, 0x39, 0x2d, 0x49, ++ 0xa0, 0x9f, 0x85, 0x5e, 0x79, 0x25, 0xf1, 0xe4, 0x9d, 0x4d, 0xe4, 0xe7, ++ 0x87, 0xfa, 0x3d, 0xf9, 0x6f, 0xaf, 0x08, 0xf1, 0x77, 0x5c, 0xf0, 0x8f, ++ 0xfc, 0x9d, 0x97, 0xdc, 0x8d, 0x98, 0x07, 0xba, 0xae, 0xdf, 0xe3, 0x33, ++ 0x2c, 0x31, 0x45, 0xdd, 0xb8, 0xff, 0x03, 0x81, 0xb0, 0x53, 0x2a, 0x10, ++ 0x5b, 0x38, 0xf0, 0x6b, 0x4b, 0x14, 0xfb, 0x22, 0x42, 0x0f, 0x77, 0xa2, ++ 0x1c, 0x61, 0xfd, 0x3f, 0xce, 0x85, 0xf9, 0x7a, 0x5f, 0x38, 0x3f, 0x67, ++ 0x0c, 0xa6, 0x02, 0xf5, 0xf8, 0x0f, 0x60, 0x4d, 0xf8, 0xb0, 0x29, 0x45, ++ 0xb4, 0xd2, 0xc5, 0x0c, 0x0b, 0xe8, 0xc5, 0xbd, 0x89, 0x7f, 0x78, 0xe6, ++ 0x69, 0xd0, 0x93, 0x96, 0x74, 0xbe, 0x5e, 0xec, 0x37, 0xe2, 0xdf, 0xdd, ++ 0x9c, 0xdf, 0x06, 0xfc, 0xab, 0xb7, 0xc7, 0x91, 0x9e, 0x62, 0xdf, 0xc2, ++ 0xdb, 0x10, 0x0f, 0x22, 0x5f, 0xa1, 0xa7, 0x53, 0x3e, 0xc8, 0x07, 0x8b, ++ 0x0d, 0x92, 0x33, 0xf1, 0xbc, 0x6f, 0xff, 0xdf, 0x22, 0x31, 0x4f, 0xbb, ++ 0x35, 0x46, 0x7d, 0x1f, 0xe9, 0xe0, 0x3f, 0x20, 0xd3, 0x3e, 0x4d, 0x98, ++ 0xd2, 0x67, 0x8a, 0x1e, 0x22, 0x2e, 0x7b, 0x13, 0xf5, 0x9e, 0x89, 0xfb, ++ 0x4d, 0x54, 0x6f, 0xde, 0xc6, 0xf3, 0x81, 0x16, 0xd5, 0xc9, 0x30, 0x0e, ++ 0x08, 0xb3, 0xdb, 0x27, 0x04, 0x9f, 0xb3, 0x6b, 0x17, 0xfa, 0x6e, 0xd5, ++ 0xfe, 0x4f, 0x46, 0x99, 0x80, 0x0e, 0x17, 0x0c, 0x3d, 0x91, 0xd9, 0x30, ++ 0x7f, 0xcd, 0xae, 0x1d, 0x91, 0xe8, 0xc6, 0xdf, 0x6b, 0x74, 0x7f, 0x8a, ++ 0x7c, 0xb7, 0xf2, 0xc4, 0x07, 0x05, 0x76, 0x3a, 0xcf, 0xb6, 0x71, 0x14, ++ 0x9d, 0x03, 0xf0, 0x8d, 0xa6, 0xba, 0x83, 0xf1, 0x0a, 0xf3, 0x28, 0xb9, ++ 0x83, 0xe1, 0xa8, 0xdb, 0x90, 0x4b, 0xc6, 0xb8, 0x76, 0x03, 0x25, 0xe3, ++ 0xd9, 0xf8, 0xf6, 0xbc, 0x87, 0x50, 0x1f, 0xd5, 0xf9, 0xf8, 0x3a, 0x71, ++ 0x6e, 0x2c, 0xfc, 0xcb, 0x6c, 0x63, 0xd4, 0xbf, 0xd8, 0xd6, 0x18, 0x83, ++ 0xf3, 0xd5, 0xfd, 0xb6, 0x23, 0x19, 0xe5, 0x67, 0x73, 0x3c, 0x8f, 0x13, ++ 0x5f, 0xbf, 0x3a, 0x8e, 0x3f, 0xaf, 0x30, 0x05, 0xc7, 0x7f, 0x99, 0x18, ++ 0x2d, 0xf8, 0xd9, 0x6b, 0xc0, 0x38, 0x63, 0xb3, 0x88, 0x4f, 0x2e, 0x5e, ++ 0x35, 0xd0, 0x38, 0xed, 0xfd, 0xe3, 0xdb, 0x8a, 0x64, 0x3b, 0xf0, 0x43, ++ 0xb6, 0xaf, 0x79, 0x2f, 0xc5, 0x43, 0xed, 0x66, 0x15, 0xe9, 0x1a, 0xf6, ++ 0x0a, 0xe3, 0x78, 0x68, 0x0f, 0x23, 0x39, 0xaf, 0xeb, 0x9c, 0xc1, 0x30, ++ 0x9f, 0xdf, 0x1f, 0xcd, 0x1c, 0x12, 0xdc, 0xdf, 0x1a, 0xee, 0xff, 0x03, ++ 0x9d, 0x33, 0xeb, 0x30, 0xab, 0x98, 0x1f, 0x0d, 0xb3, 0x37, 0xb3, 0x18, ++ 0x98, 0x7f, 0xab, 0xd8, 0x0f, 0xcd, 0x04, 0x8e, 0xc2, 0xf3, 0x4a, 0xda, ++ 0x75, 0xed, 0x7d, 0x61, 0xed, 0x3f, 0xc5, 0x58, 0x02, 0xf9, 0x81, 0xf2, ++ 0xb4, 0x61, 0x4a, 0x33, 0xbb, 0xcd, 0x16, 0x8c, 0xe7, 0x08, 0xc2, 0x73, ++ 0x3c, 0xf2, 0x53, 0x3c, 0xbe, 0xc7, 0x67, 0xc0, 0xfc, 0x88, 0xff, 0x16, ++ 0xc6, 0x5e, 0x26, 0xb8, 0x02, 0x70, 0x32, 0x7a, 0xaf, 0x06, 0x67, 0x26, ++ 0xf9, 0x73, 0x5b, 0x4d, 0xfe, 0xb3, 0x78, 0x7e, 0x05, 0xe0, 0xb2, 0x23, ++ 0xfd, 0x33, 0x19, 0x87, 0x93, 0xb5, 0x8f, 0x55, 0x31, 0xbe, 0x0f, 0xb3, ++ 0x3b, 0x69, 0x1d, 0x61, 0x76, 0xd5, 0xe1, 0x91, 0x06, 0xc3, 0x55, 0x97, ++ 0xc3, 0xbc, 0x68, 0xbf, 0x7f, 0xbc, 0x96, 0x0d, 0xc8, 0x2b, 0xca, 0x6f, ++ 0x5d, 0x78, 0xa0, 0x6f, 0x01, 0x19, 0xd8, 0x3a, 0x9a, 0x09, 0xf9, 0xb6, ++ 0x3f, 0x5b, 0x3a, 0x2d, 0xb8, 0x0f, 0x8a, 0x64, 0x72, 0xe0, 0xf9, 0x71, ++ 0x1b, 0x62, 0x9e, 0x6d, 0x1a, 0x49, 0x71, 0x83, 0x47, 0xc6, 0x38, 0x16, ++ 0xda, 0x88, 0x18, 0x5c, 0xa7, 0xca, 0xcf, 0x3b, 0x63, 0x6a, 0x28, 0x97, ++ 0xe3, 0x01, 0xf7, 0xc5, 0xad, 0x16, 0x7e, 0x7f, 0x60, 0x3c, 0xf0, 0xb7, ++ 0x0d, 0xfb, 0x36, 0x3e, 0xce, 0x11, 0x65, 0xb7, 0xce, 0x94, 0x48, 0x4e, ++ 0x28, 0xaf, 0x57, 0x2b, 0xe4, 0xfd, 0x31, 0xc9, 0x77, 0xf6, 0x76, 0x90, ++ 0xd3, 0xbf, 0xf8, 0xf6, 0xe6, 0xa8, 0x00, 0x4b, 0xcd, 0xbb, 0x7b, 0x88, ++ 0x4f, 0x57, 0x1a, 0xda, 0x5f, 0x1c, 0x0f, 0xf7, 0x37, 0x5a, 0xdc, 0xf9, ++ 0x49, 0x80, 0xcf, 0xb7, 0x4e, 0x1a, 0xe8, 0x1c, 0xe9, 0x9f, 0x5e, 0x0b, ++ 0xf3, 0x56, 0x62, 0xfc, 0xb8, 0x7b, 0x63, 0x82, 0x73, 0x08, 0xf9, 0xd0, ++ 0xcf, 0xff, 0xc3, 0xe3, 0x6b, 0x9f, 0x4f, 0x41, 0xfa, 0xef, 0x96, 0x54, ++ 0xcc, 0x9b, 0xf6, 0x1b, 0xfd, 0xa3, 0x10, 0xde, 0xda, 0xf6, 0xcf, 0x4d, ++ 0x54, 0x8f, 0xd0, 0x76, 0x8a, 0xea, 0x93, 0x8e, 0x24, 0xb9, 0x9d, 0xf8, ++ 0x9e, 0xc9, 0x6d, 0x0d, 0xb4, 0x6f, 0x3c, 0x85, 0x35, 0xd3, 0xbe, 0x71, ++ 0x96, 0x38, 0x7f, 0xdd, 0x92, 0xc4, 0xf5, 0xc7, 0xe5, 0x63, 0x63, 0x5e, ++ 0x6e, 0x08, 0xc2, 0xff, 0x83, 0x49, 0xdc, 0x0f, 0x63, 0x7e, 0xf7, 0xcd, ++ 0x28, 0x37, 0xed, 0x42, 0x3e, 0x3b, 0xd1, 0x2f, 0x81, 0x76, 0x97, 0xf0, ++ 0x8f, 0x76, 0x75, 0xdd, 0x9d, 0xa6, 0x06, 0xe5, 0xfd, 0x1a, 0xd8, 0xde, ++ 0x14, 0xc4, 0xf7, 0x5a, 0xf6, 0x36, 0xb5, 0xda, 0xf5, 0x7e, 0x2f, 0x3f, ++ 0xcf, 0x98, 0xf5, 0x91, 0xe5, 0x3e, 0x67, 0x10, 0xff, 0xb9, 0x93, 0xb8, ++ 0x9f, 0xe7, 0x16, 0xef, 0xf3, 0x27, 0xb9, 0x17, 0x24, 0xa1, 0xdc, 0x76, ++ 0x9d, 0x36, 0x45, 0xaa, 0x78, 0x5e, 0xa5, 0x65, 0x14, 0xda, 0x91, 0x16, ++ 0xf0, 0x9f, 0xec, 0x43, 0xe0, 0x65, 0x40, 0x6e, 0x75, 0x72, 0x54, 0xa7, ++ 0xf8, 0x4d, 0x38, 0xbe, 0xee, 0x1c, 0x3f, 0x77, 0x0a, 0x74, 0x6e, 0xc2, ++ 0xfa, 0xff, 0xcd, 0x1f, 0xb5, 0x8d, 0x5b, 0x02, 0xd7, 0x77, 0x01, 0xae, ++ 0xb1, 0xde, 0xd3, 0x73, 0xc2, 0x4c, 0x75, 0x8f, 0xbb, 0x8c, 0xae, 0x14, ++ 0x1c, 0xdf, 0xf0, 0xe1, 0x57, 0x39, 0xa8, 0xb7, 0x2a, 0x10, 0x69, 0xf0, ++ 0xbf, 0xaf, 0x3a, 0x56, 0xde, 0x8c, 0x78, 0x03, 0xbe, 0x2f, 0x0e, 0x47, ++ 0xf9, 0xda, 0xce, 0x48, 0x8f, 0x69, 0xf2, 0x99, 0x8d, 0xf2, 0x09, 0xcf, ++ 0x67, 0x23, 0xdf, 0xe7, 0x63, 0x3f, 0x93, 0xf4, 0xf0, 0x56, 0x53, 0x2f, ++ 0x3f, 0xf7, 0xb9, 0x8b, 0x9f, 0xfb, 0x04, 0xbe, 0x27, 0x39, 0x00, 0xbe, ++ 0xb7, 0xa3, 0x9f, 0x90, 0x6d, 0x07, 0x39, 0xa0, 0xe7, 0xc7, 0x92, 0x7c, ++ 0x6f, 0xed, 0x35, 0xd0, 0xf9, 0x54, 0x0f, 0xe8, 0xf1, 0x5b, 0xa8, 0x5f, ++ 0x5c, 0x85, 0xfd, 0xad, 0xbd, 0xa5, 0x76, 0x92, 0x6f, 0xcc, 0xc3, 0xe7, ++ 0xa2, 0x9c, 0xfa, 0xf6, 0xd2, 0x3c, 0x2d, 0x10, 0x83, 0x20, 0xe9, 0x24, ++ 0xe6, 0x0a, 0xf6, 0x1f, 0xdb, 0x13, 0x23, 0x89, 0x8f, 0x35, 0xfd, 0x78, ++ 0x30, 0x91, 0xeb, 0xff, 0x96, 0x0c, 0x35, 0x0a, 0xeb, 0xff, 0xad, 0xb2, ++ 0x1c, 0x22, 0x17, 0x41, 0x76, 0x90, 0xf7, 0x85, 0x9d, 0xec, 0xdd, 0x50, ++ 0xfc, 0xec, 0x0b, 0xd3, 0xd0, 0xde, 0x09, 0xbb, 0x20, 0xfc, 0x27, 0x76, ++ 0x9c, 0xeb, 0xf9, 0x47, 0x85, 0xad, 0x5a, 0xf3, 0x4e, 0xe1, 0xec, 0x2d, ++ 0xb0, 0xce, 0x35, 0x87, 0xe5, 0x81, 0x7a, 0x6e, 0xf4, 0x57, 0x7d, 0x82, ++ 0x4f, 0xf6, 0x0a, 0xff, 0x15, 0xed, 0x84, 0x9a, 0xc7, 0xeb, 0x67, 0xf0, ++ 0xfa, 0xc4, 0x0d, 0xbc, 0xce, 0xb5, 0xc0, 0xb9, 0xba, 0x04, 0xcb, 0x38, ++ 0x26, 0x57, 0x34, 0xef, 0xc3, 0xb6, 0xd0, 0xd5, 0x52, 0x82, 0x67, 0x8e, ++ 0xa7, 0x2d, 0xec, 0xdd, 0xc7, 0xcf, 0x1e, 0xf3, 0xf3, 0xe3, 0xad, 0x7b, ++ 0xef, 0xc8, 0xc2, 0x7d, 0xea, 0xfe, 0x13, 0x66, 0x86, 0xfb, 0x24, 0xad, ++ 0x7f, 0xf3, 0xff, 0xe1, 0x75, 0xc0, 0xc3, 0x77, 0x3b, 0x01, 0xff, 0x43, ++ 0xd8, 0x25, 0x58, 0x0e, 0xf1, 0x1f, 0x58, 0xea, 0x14, 0x96, 0x34, 0xf8, ++ 0x7e, 0xbf, 0xa4, 0xe9, 0x8f, 0xf9, 0x95, 0x28, 0x6f, 0x17, 0x5b, 0xe5, ++ 0x40, 0x1f, 0xec, 0x61, 0x2d, 0x30, 0x38, 0xf6, 0x7f, 0x9d, 0x54, 0xf5, ++ 0xac, 0x07, 0x00, 0x4b, 0x1b, 0xe1, 0x7c, 0x1d, 0x59, 0xa2, 0x30, 0xd9, ++ 0x4d, 0x6d, 0xff, 0x91, 0xbf, 0x25, 0xa0, 0x2d, 0xd8, 0x75, 0x8c, 0xfb, ++ 0x4d, 0xad, 0x26, 0x67, 0x16, 0xf2, 0x4f, 0xeb, 0xe8, 0xd0, 0xf3, 0xfa, ++ 0x5a, 0xfb, 0x62, 0x12, 0x3f, 0xe7, 0x9c, 0x6f, 0x66, 0x43, 0xe6, 0x25, ++ 0x0f, 0x09, 0xbb, 0x37, 0xc6, 0xc3, 0x9e, 0x41, 0x3e, 0xaa, 0x6d, 0x95, ++ 0xed, 0x5e, 0xa0, 0xfb, 0x85, 0x56, 0xd9, 0x69, 0x02, 0xff, 0xe6, 0xac, ++ 0xd3, 0x9d, 0x80, 0x67, 0x65, 0xce, 0x31, 0xcf, 0x82, 0xa9, 0x68, 0xe7, ++ 0x45, 0xdc, 0xa8, 0x7d, 0x4f, 0x65, 0x19, 0xfa, 0x27, 0x60, 0xa7, 0x1e, ++ 0x7c, 0x61, 0x50, 0x1e, 0xdf, 0x80, 0x7c, 0xf4, 0x50, 0xbb, 0xc4, 0x7e, ++ 0x06, 0x6b, 0x5e, 0xfe, 0xd2, 0xd0, 0xfb, 0x0a, 0x35, 0x62, 0x9e, 0x87, ++ 0xdb, 0x36, 0xee, 0x4f, 0x01, 0x3a, 0xae, 0x78, 0x25, 0x74, 0x5c, 0x8d, ++ 0xa8, 0x13, 0xab, 0xd1, 0xf9, 0x2f, 0x87, 0x92, 0x44, 0x7c, 0x98, 0xc6, ++ 0xd2, 0xd0, 0x2f, 0x01, 0xfe, 0x21, 0xbd, 0x60, 0x54, 0x58, 0xb7, 0x19, ++ 0xf8, 0xf5, 0xc1, 0x64, 0x77, 0x07, 0xc6, 0x1b, 0x9b, 0xc5, 0x77, 0x0c, ++ 0x40, 0x7f, 0x92, 0x1c, 0x76, 0x08, 0xbe, 0xdc, 0x2a, 0xea, 0x04, 0xfc, ++ 0x5b, 0x25, 0xda, 0xd7, 0xcb, 0x7c, 0xd5, 0x2b, 0x1b, 0xe0, 0xf9, 0x42, ++ 0xc5, 0x2b, 0xa3, 0x9d, 0x62, 0xd0, 0xe2, 0x3e, 0xc1, 0x64, 0xa7, 0xbb, ++ 0x1c, 0xf1, 0x0b, 0xeb, 0x3e, 0x86, 0xfb, 0x35, 0xcb, 0x85, 0x1e, 0x5c, ++ 0xae, 0xf9, 0x65, 0x5e, 0xbe, 0x9f, 0x01, 0xe6, 0x96, 0xfc, 0xb2, 0x29, ++ 0xcc, 0xdb, 0x18, 0x89, 0xeb, 0x7e, 0x55, 0x72, 0xf8, 0x54, 0xfc, 0x8e, ++ 0xc8, 0xa0, 0x3a, 0x5c, 0x5a, 0x77, 0x9d, 0x58, 0x77, 0xcd, 0x86, 0x23, ++ 0xfb, 0x31, 0x8c, 0x5b, 0xd5, 0x12, 0x3a, 0xae, 0x4e, 0xac, 0xbb, 0x4e, ++ 0xb7, 0x6e, 0x6d, 0x5f, 0xfb, 0xcf, 0x49, 0xba, 0x73, 0xc8, 0x37, 0xb8, ++ 0x6f, 0xf1, 0x67, 0x23, 0xf7, 0x13, 0x3e, 0x10, 0xf3, 0x68, 0xf7, 0xcd, ++ 0x23, 0xb8, 0x3e, 0xac, 0x05, 0xf0, 0x90, 0x6e, 0x35, 0x5e, 0xd9, 0xeb, ++ 0xe5, 0x7e, 0x9d, 0x0d, 0xbf, 0xc3, 0x73, 0xbf, 0x80, 0xf7, 0x7e, 0x41, ++ 0xef, 0x3a, 0xe6, 0x33, 0xa5, 0xc0, 0xb8, 0x55, 0x2f, 0xf0, 0x75, 0xb2, ++ 0x67, 0x43, 0xeb, 0x3f, 0x1f, 0x6c, 0x7d, 0xc4, 0x84, 0xf1, 0x95, 0x9e, ++ 0x2f, 0x96, 0x6f, 0x31, 0x92, 0x3f, 0x0a, 0x88, 0x33, 0xa1, 0xbf, 0xa8, ++ 0xe7, 0x8b, 0x15, 0x62, 0xdd, 0x2b, 0x74, 0xeb, 0xae, 0x75, 0x4b, 0x3a, ++ 0xb8, 0xb8, 0x9f, 0x3c, 0x18, 0xae, 0x96, 0x05, 0x48, 0xd7, 0x55, 0x5b, ++ 0x8c, 0x0c, 0xeb, 0x11, 0xf5, 0x70, 0x2d, 0x6b, 0x59, 0x52, 0x8e, 0x7c, ++ 0x36, 0x98, 0x5f, 0x39, 0x5d, 0x56, 0x88, 0xf9, 0x02, 0x70, 0xae, 0xa6, ++ 0x73, 0x7c, 0x37, 0x0a, 0xe7, 0xa8, 0x11, 0x82, 0x2f, 0xc7, 0xb1, 0x71, ++ 0x44, 0x97, 0x8a, 0xd8, 0x1b, 0xa2, 0x8b, 0xde, 0x8f, 0xdd, 0xbe, 0x7f, ++ 0x9c, 0x15, 0xe5, 0xfb, 0x72, 0xf7, 0x68, 0x8a, 0xdf, 0x35, 0xba, 0xeb, ++ 0x9f, 0x2f, 0x17, 0x7e, 0xf0, 0x8c, 0x0d, 0x8c, 0xda, 0x0b, 0x6d, 0x25, ++ 0xd6, 0xf1, 0x18, 0xa7, 0xf4, 0x18, 0x1c, 0x92, 0x4a, 0xf1, 0x56, 0xe4, ++ 0x78, 0xc0, 0x47, 0x5e, 0x87, 0xcc, 0x2a, 0xa1, 0xdf, 0xdf, 0x9e, 0xb6, ++ 0xde, 0x03, 0x78, 0xcf, 0x3d, 0x9c, 0x5f, 0x85, 0xf1, 0x7c, 0xde, 0x61, ++ 0x03, 0x9d, 0x77, 0xdb, 0xd9, 0x9d, 0x4f, 0xfb, 0xc0, 0x79, 0x07, 0xd2, ++ 0x63, 0xd3, 0x28, 0x1f, 0xed, 0xa0, 0xef, 0xcd, 0xc0, 0x3c, 0x64, 0x3f, ++ 0xfb, 0x7b, 0x72, 0xd7, 0xe3, 0xb9, 0x80, 0xfe, 0x9e, 0xd2, 0x7c, 0x9c, ++ 0x57, 0x82, 0x71, 0x68, 0xe7, 0x73, 0x85, 0x1d, 0x68, 0xe8, 0xc9, 0xb5, ++ 0x06, 0x9f, 0xef, 0x2e, 0x18, 0xc1, 0xe3, 0xf5, 0xa7, 0x92, 0x3e, 0xfb, ++ 0x31, 0xfa, 0xe1, 0x33, 0xb6, 0x1b, 0xe9, 0x7c, 0xc3, 0x0c, 0xa3, 0xff, ++ 0x3d, 0xac, 0x9f, 0xda, 0xd9, 0xad, 0xd0, 0xbe, 0x75, 0xcd, 0xe1, 0xa5, ++ 0x6b, 0xc3, 0x90, 0xae, 0xaf, 0x49, 0xb4, 0x6f, 0xbd, 0xbf, 0x77, 0x4d, ++ 0xdc, 0x62, 0xe4, 0xab, 0x76, 0xa3, 0x1d, 0xf7, 0xa1, 0xfb, 0xdb, 0xff, ++ 0x6d, 0x2f, 0xde, 0xf7, 0x6c, 0x91, 0xe8, 0x7b, 0x12, 0x75, 0x1d, 0x65, ++ 0x59, 0x5b, 0xa1, 0x9f, 0xbb, 0x31, 0xcf, 0x11, 0x7c, 0xde, 0x2b, 0x37, ++ 0x5a, 0x25, 0xf8, 0xd8, 0x08, 0x2b, 0xc5, 0xc3, 0x33, 0x6e, 0x32, 0x92, ++ 0x5d, 0x3c, 0x9f, 0x6c, 0xfd, 0x25, 0xfa, 0x37, 0x2b, 0x9c, 0x1b, 0x49, ++ 0x8e, 0xcf, 0xef, 0xd9, 0x69, 0xa2, 0xfa, 0xb9, 0xad, 0x12, 0x43, 0xd3, ++ 0xbf, 0x3f, 0x69, 0xdf, 0x1b, 0x88, 0x8f, 0xf3, 0x6f, 0x1e, 0x31, 0xa1, ++ 0x93, 0x5d, 0xd2, 0x7a, 0xc4, 0xd4, 0xf7, 0x77, 0xec, 0xfd, 0x05, 0x2f, ++ 0x04, 0xfe, 0x14, 0x07, 0x37, 0x9b, 0x30, 0x4e, 0x59, 0xb5, 0x51, 0xeb, ++ 0xf7, 0x99, 0x90, 0x4e, 0x2e, 0xe1, 0xff, 0xd4, 0xbe, 0x72, 0x8a, 0xfa, ++ 0x2b, 0xda, 0x24, 0xd2, 0x33, 0x2b, 0x5e, 0x92, 0xe9, 0x3c, 0xfb, 0xbe, ++ 0x8e, 0xb7, 0x4c, 0xc8, 0xc7, 0xb5, 0x5b, 0x24, 0x96, 0x98, 0x1a, 0x74, ++ 0x7f, 0x83, 0x14, 0xf2, 0x1d, 0x84, 0xa5, 0x8c, 0xf3, 0xc1, 0x52, 0xa1, ++ 0x67, 0x56, 0x32, 0xef, 0x53, 0xc9, 0x30, 0x6e, 0x65, 0x33, 0xaf, 0x23, ++ 0x60, 0x4f, 0x87, 0xd6, 0xe5, 0xae, 0xdc, 0x32, 0x87, 0xbe, 0xdb, 0xb4, ++ 0xac, 0x79, 0x68, 0x7d, 0xf3, 0xb0, 0xe0, 0xeb, 0x87, 0x30, 0x1e, 0xbc, ++ 0x15, 0xbf, 0x83, 0x14, 0x3a, 0xee, 0x61, 0xed, 0xbb, 0x5c, 0x3a, 0x7e, ++ 0x7e, 0x5c, 0xe3, 0xe7, 0x4c, 0x96, 0x89, 0xfc, 0xfc, 0x55, 0x91, 0x1a, ++ 0x95, 0x0d, 0xd7, 0xbf, 0x3a, 0xb2, 0xe2, 0xe6, 0xa1, 0xce, 0xb1, 0xf7, ++ 0x08, 0x3b, 0xac, 0xd9, 0xc1, 0xcb, 0x3e, 0x03, 0xd9, 0x11, 0xfd, 0xb8, ++ 0x8b, 0x6d, 0x57, 0x08, 0xde, 0xba, 0x9e, 0xcb, 0x26, 0xb4, 0x83, 0xe5, ++ 0xed, 0x97, 0x08, 0xef, 0x95, 0xed, 0x5d, 0x54, 0xc7, 0x71, 0x17, 0x73, ++ 0xd7, 0x20, 0x9e, 0xee, 0x6a, 0xb7, 0xda, 0x51, 0x8e, 0x2b, 0xfb, 0xb8, ++ 0x5e, 0x9a, 0xd9, 0x6e, 0xf6, 0x7a, 0x25, 0xbc, 0xdf, 0xd2, 0x84, 0xf4, ++ 0xec, 0xef, 0xe4, 0x75, 0x8b, 0x9e, 0x3d, 0x12, 0xf9, 0x2f, 0x9a, 0xbe, ++ 0x7a, 0x48, 0xe0, 0xef, 0x21, 0x81, 0xbf, 0x87, 0x40, 0x41, 0xa7, 0xe4, ++ 0xa2, 0x1f, 0xcb, 0xe3, 0xde, 0x87, 0x33, 0x36, 0xee, 0x8f, 0x81, 0xfb, ++ 0xb5, 0xe2, 0x7a, 0xcd, 0x81, 0x7d, 0x91, 0xe8, 0xef, 0xcd, 0x64, 0x97, ++ 0xee, 0x45, 0x7a, 0xc0, 0x7b, 0x18, 0xbe, 0x87, 0xbd, 0x14, 0x8a, 0xe7, ++ 0x3b, 0x19, 0x87, 0xe3, 0xce, 0x2d, 0xbc, 0xde, 0x59, 0x6f, 0xaf, 0xfa, ++ 0x47, 0x64, 0xcd, 0xa6, 0xfc, 0x23, 0xc4, 0x9d, 0x08, 0x4f, 0xcd, 0x96, ++ 0x50, 0x3c, 0xd7, 0xea, 0xe2, 0xed, 0x75, 0x23, 0xb8, 0x7d, 0xde, 0xa4, ++ 0xc3, 0x73, 0xa5, 0x9f, 0x59, 0xb3, 0x11, 0x0e, 0x55, 0x76, 0x78, 0x69, ++ 0x74, 0xaf, 0x82, 0xef, 0xed, 0xce, 0x91, 0x28, 0xbf, 0xda, 0xad, 0xa6, ++ 0x45, 0x0d, 0xb5, 0xff, 0xa8, 0xb5, 0xef, 0x09, 0xbf, 0x59, 0xeb, 0xcf, ++ 0x16, 0xe7, 0xab, 0x5b, 0xec, 0xcd, 0xb6, 0xe0, 0x38, 0xd8, 0x94, 0xcc, ++ 0xed, 0xff, 0x8a, 0x29, 0xb2, 0x07, 0xe9, 0x34, 0x10, 0x3f, 0xa4, 0xef, ++ 0xcb, 0x51, 0x0d, 0x81, 0xf8, 0x01, 0xe2, 0x86, 0xdf, 0x8c, 0x88, 0xe7, ++ 0x71, 0x04, 0x16, 0x74, 0xbc, 0x3b, 0x52, 0x66, 0x71, 0x71, 0x81, 0xf8, ++ 0xe1, 0x87, 0x49, 0xeb, 0x2b, 0x73, 0xa1, 0x5f, 0xb7, 0x85, 0xcb, 0xf9, ++ 0xc5, 0xc9, 0x30, 0x1f, 0x7e, 0xdf, 0x4b, 0x61, 0xe4, 0x5f, 0xd6, 0x6d, ++ 0x31, 0xd3, 0x39, 0xc0, 0x3a, 0xa0, 0x3b, 0xc5, 0x09, 0xed, 0xfc, 0x1c, ++ 0x83, 0xab, 0x5d, 0x2a, 0x43, 0x7a, 0x83, 0xff, 0xfd, 0xee, 0x88, 0x89, ++ 0x78, 0xae, 0x86, 0x19, 0xe3, 0x60, 0xdd, 0x73, 0xda, 0x38, 0x9f, 0xcf, ++ 0x29, 0xbd, 0x44, 0x7c, 0x72, 0x20, 0x9d, 0xaf, 0xf7, 0xb2, 0xa2, 0x26, ++ 0x0e, 0xe5, 0x8f, 0x6b, 0x7e, 0x38, 0x9e, 0xc3, 0x52, 0x83, 0xcf, 0x3f, ++ 0x80, 0x5c, 0xe2, 0xf8, 0xda, 0x76, 0x5e, 0x0f, 0xd4, 0xba, 0xf7, 0xeb, ++ 0x51, 0xa9, 0xa8, 0xd7, 0x3a, 0xfe, 0x3a, 0x6a, 0x09, 0xb4, 0x57, 0x46, ++ 0xf0, 0xf5, 0x6b, 0x7e, 0x9e, 0x1f, 0xfc, 0xbc, 0xd1, 0xdc, 0xcf, 0x39, ++ 0x86, 0xfe, 0xe7, 0x83, 0x9a, 0xdc, 0xd8, 0xf9, 0x3e, 0xda, 0x83, 0xc2, ++ 0xce, 0x30, 0xa9, 0x89, 0xf8, 0xbb, 0xd6, 0xd8, 0xf2, 0x76, 0x0c, 0xfa, ++ 0x4d, 0x5b, 0xf9, 0xbe, 0x3d, 0xdb, 0x6d, 0xc4, 0x6f, 0x9c, 0xb1, 0x86, ++ 0x0f, 0x5e, 0x6f, 0x8a, 0x81, 0x75, 0x5f, 0x7c, 0x5d, 0xa2, 0x7a, 0x34, ++ 0x7c, 0xfe, 0x09, 0xe0, 0xb3, 0x8b, 0x4b, 0x5b, 0x4e, 0xa3, 0x1f, 0xfd, ++ 0xd5, 0x56, 0x0b, 0xf9, 0x8f, 0x0f, 0x82, 0x8f, 0x38, 0x3d, 0x77, 0xb0, ++ 0x3c, 0x6a, 0x72, 0xab, 0x7d, 0x77, 0xaa, 0x81, 0xad, 0x25, 0x7f, 0x72, ++ 0x2d, 0x6b, 0xa2, 0x76, 0x95, 0xe0, 0xe3, 0x8b, 0x6d, 0x8d, 0x26, 0xca, ++ 0x9b, 0x79, 0x83, 0x9e, 0x1f, 0x3d, 0xd8, 0xef, 0x58, 0xa5, 0xe3, 0x3b, ++ 0x53, 0x72, 0x28, 0xbf, 0x35, 0x7c, 0x10, 0x4e, 0xfe, 0x5f, 0xff, 0x01, ++ 0xd9, 0x8e, 0xfb, 0x27, 0x80, 0xa7, 0xff, 0x4e, 0x0e, 0xc6, 0x87, 0xf0, ++ 0x2f, 0x5a, 0xf7, 0x86, 0x11, 0x3d, 0xfb, 0x8f, 0xd8, 0xc8, 0x5e, 0xfc, ++ 0x49, 0xf0, 0xd9, 0x79, 0x91, 0x37, 0x6e, 0x98, 0x2c, 0xd3, 0xfa, 0x0d, ++ 0x53, 0x78, 0x9b, 0xd5, 0xf9, 0xd6, 0x68, 0xa4, 0x1f, 0xe2, 0x1b, 0xeb, ++ 0xde, 0x37, 0x77, 0xbe, 0x35, 0x8e, 0x9f, 0xa7, 0xf6, 0x12, 0xde, 0x57, ++ 0xbe, 0x8a, 0x49, 0xf1, 0x20, 0x38, 0x5b, 0xac, 0x94, 0xdb, 0xd3, 0xfa, ++ 0x0d, 0x1f, 0x2c, 0xa2, 0xef, 0xf0, 0xd4, 0xed, 0x19, 0x80, 0x6b, 0x8c, ++ 0x29, 0x2e, 0x00, 0xd7, 0x70, 0xfc, 0x2f, 0x49, 0x3c, 0x1e, 0x34, 0x48, ++ 0xa1, 0xf1, 0x60, 0xdd, 0x6e, 0xd9, 0x15, 0x5c, 0xef, 0x05, 0xeb, 0xb9, ++ 0x0f, 0xf5, 0x4f, 0x92, 0x90, 0x03, 0xa6, 0xf8, 0x13, 0xd0, 0x2f, 0x19, ++ 0x99, 0xac, 0x92, 0xfd, 0x6a, 0x68, 0xe7, 0xf4, 0x34, 0x74, 0xf0, 0x16, ++ 0xde, 0xbf, 0x80, 0xe7, 0x3b, 0x8c, 0xf4, 0xfe, 0x41, 0xf7, 0x8b, 0x3d, ++ 0x35, 0x78, 0xff, 0xab, 0x54, 0x2b, 0xdf, 0x4f, 0xbe, 0xea, 0xa9, 0xc4, ++ 0xfe, 0x77, 0x47, 0xcb, 0x54, 0x4f, 0xf9, 0xdd, 0x0f, 0x56, 0x8c, 0x0d, ++ 0xd6, 0x9b, 0x0c, 0xe1, 0x04, 0x7a, 0xd6, 0x19, 0xfd, 0x09, 0x14, 0x37, ++ 0x1e, 0x31, 0x10, 0x7c, 0x75, 0x47, 0x2e, 0x27, 0xa4, 0xdb, 0x50, 0x1f, ++ 0x6d, 0x2c, 0xb5, 0x67, 0xa3, 0xde, 0xe1, 0xfa, 0x6e, 0xff, 0x68, 0xeb, ++ 0x72, 0xe4, 0x63, 0x0f, 0xbe, 0x37, 0x31, 0x30, 0xcf, 0x6b, 0xc2, 0xde, ++ 0x32, 0x5c, 0x6f, 0x12, 0x7a, 0x15, 0x2f, 0xf0, 0x79, 0xc5, 0x7a, 0xd7, ++ 0xb2, 0xb9, 0x22, 0x3e, 0xe6, 0x7c, 0x94, 0x2d, 0xfc, 0x3d, 0x88, 0x2b, ++ 0x26, 0x26, 0x4f, 0x1c, 0x1c, 0x57, 0xdc, 0xa8, 0x3f, 0x09, 0xf6, 0xe0, ++ 0xe8, 0x62, 0x09, 0xeb, 0x89, 0x14, 0x0f, 0xc6, 0xb5, 0x3b, 0x8f, 0x73, ++ 0x7d, 0xd0, 0xd0, 0xf1, 0xd0, 0xa7, 0xc8, 0xe7, 0x75, 0x9f, 0x98, 0xa9, ++ 0xbe, 0xea, 0xbb, 0x9d, 0x0f, 0x8d, 0xa5, 0x3a, 0x5b, 0xb7, 0xfb, 0x56, ++ 0xf4, 0x2b, 0xbe, 0xea, 0x7c, 0xf8, 0x56, 0xca, 0xf3, 0x49, 0x6b, 0x09, ++ 0x2e, 0x0f, 0xc2, 0x97, 0x84, 0xfe, 0xcb, 0x87, 0x09, 0x58, 0x0f, 0xba, ++ 0xaa, 0xe3, 0xc3, 0x04, 0xb2, 0xaf, 0xbb, 0x26, 0xae, 0xf7, 0x44, 0xa0, ++ 0x9f, 0x92, 0x7b, 0x27, 0x5e, 0x07, 0xbf, 0x81, 0xf8, 0x0f, 0xfc, 0x17, ++ 0xe2, 0xbf, 0x9d, 0x3d, 0xf9, 0x9a, 0xbf, 0x62, 0xc5, 0x79, 0x57, 0x1d, ++ 0x50, 0x5c, 0x88, 0x9f, 0x55, 0x07, 0xf2, 0x0f, 0x55, 0xa2, 0x1f, 0x71, ++ 0xb8, 0x38, 0x1f, 0xd5, 0xb8, 0x74, 0x38, 0x9f, 0xfc, 0x95, 0x3c, 0xf4, ++ 0x57, 0x6c, 0x01, 0xff, 0x45, 0x5b, 0x4f, 0x65, 0x32, 0xaf, 0x77, 0xe9, ++ 0xef, 0x0a, 0xa3, 0x3c, 0x81, 0xc4, 0x46, 0x73, 0xfe, 0x61, 0xe9, 0x21, ++ 0xfc, 0x53, 0xd3, 0xfa, 0x0e, 0xd9, 0xf5, 0x9a, 0x36, 0x39, 0xa4, 0x6e, ++ 0x50, 0x7b, 0xce, 0x9d, 0xac, 0xf0, 0x7d, 0x7e, 0x8d, 0x7f, 0x5a, 0x24, ++ 0x27, 0xf1, 0xc7, 0x76, 0xde, 0xd6, 0xb4, 0xed, 0xa4, 0xf5, 0xad, 0x34, ++ 0xb6, 0x10, 0xbd, 0x1b, 0xb6, 0x18, 0xf9, 0xfd, 0xad, 0xbc, 0xd5, 0xea, ++ 0xaa, 0x3d, 0x2c, 0xc6, 0x83, 0xf8, 0x38, 0x84, 0x97, 0x80, 0x0e, 0x33, ++ 0x4d, 0x5e, 0xfa, 0x6e, 0xc5, 0xc1, 0x54, 0xee, 0xbf, 0xeb, 0xe9, 0xf1, ++ 0x59, 0x32, 0xcf, 0x63, 0x1c, 0x3c, 0xe1, 0xbe, 0x19, 0xf9, 0xe5, 0x60, ++ 0x91, 0x7b, 0xac, 0x7d, 0x08, 0xfb, 0xe0, 0x61, 0xc5, 0x3c, 0x3e, 0x95, ++ 0x04, 0xbe, 0x5b, 0xf9, 0x79, 0x25, 0xfd, 0xb8, 0x53, 0xc9, 0x3c, 0x8e, ++ 0x8f, 0x8c, 0x0d, 0x3d, 0x3f, 0x3a, 0x60, 0x5f, 0x92, 0x39, 0xff, 0xcc, ++ 0x34, 0x0d, 0xfd, 0x3d, 0xbd, 0x9f, 0x69, 0xf2, 0xc4, 0xd8, 0x33, 0x06, ++ 0xe0, 0x8b, 0xa3, 0x95, 0x46, 0xfb, 0x3a, 0xe1, 0xb7, 0x8f, 0x08, 0xfa, ++ 0x5e, 0x42, 0xd5, 0x5d, 0x46, 0xf2, 0x0f, 0x8e, 0x32, 0xfb, 0x3b, 0x58, ++ 0x67, 0x38, 0x4b, 0xd3, 0xaf, 0x93, 0xb9, 0x5d, 0xd5, 0xf2, 0xdd, 0xae, ++ 0x0d, 0x2a, 0xdf, 0xd7, 0x19, 0x7c, 0xae, 0x91, 0xf4, 0xe4, 0x7c, 0x6d, ++ 0x3e, 0xfd, 0x79, 0x69, 0xe1, 0xd7, 0xcc, 0xd7, 0xf9, 0x35, 0xeb, 0x35, ++ 0xfd, 0x37, 0x86, 0x8d, 0x41, 0xfd, 0xd7, 0x22, 0xce, 0xb9, 0xad, 0xc9, ++ 0x0c, 0xf3, 0x06, 0xe7, 0xa3, 0xf4, 0xed, 0x7e, 0xb1, 0x8f, 0x81, 0xe7, ++ 0x75, 0xb0, 0x6d, 0xc8, 0xfc, 0x98, 0xf2, 0x36, 0x07, 0xbb, 0x4e, 0xbc, ++ 0x41, 0x75, 0x66, 0x27, 0xc2, 0xd8, 0x68, 0x9e, 0x97, 0xa3, 0xfc, 0xf5, ++ 0xaa, 0x61, 0xf2, 0xd7, 0x0d, 0x03, 0xf2, 0x38, 0x2f, 0x84, 0xbf, 0x34, ++ 0x7a, 0x5c, 0x10, 0xdf, 0x55, 0xd1, 0xd3, 0xe3, 0x0d, 0x81, 0x77, 0x6d, ++ 0x9f, 0x2d, 0x5c, 0xec, 0xb3, 0x9d, 0x56, 0xdc, 0x6f, 0x24, 0x53, 0x5d, ++ 0xd6, 0x79, 0x13, 0xff, 0x8e, 0x9a, 0x9f, 0xe2, 0xab, 0x86, 0x4c, 0xee, ++ 0x1f, 0x5d, 0x28, 0x93, 0x68, 0x5f, 0x1c, 0xe0, 0x1c, 0x65, 0x0e, 0xd2, ++ 0xeb, 0x17, 0x46, 0xf0, 0xb8, 0xea, 0xbb, 0x0b, 0x24, 0xca, 0x9b, 0x76, ++ 0xe1, 0x78, 0x8c, 0x9f, 0x5a, 0x24, 0xaa, 0xab, 0x5e, 0xe5, 0xeb, 0x35, ++ 0x21, 0x1f, 0x8d, 0x69, 0x5d, 0xf2, 0x24, 0xc9, 0xab, 0x87, 0x1d, 0x63, ++ 0x41, 0xdf, 0xa9, 0x98, 0x6d, 0xe1, 0x76, 0x71, 0x80, 0x6e, 0xda, 0xba, ++ 0x07, 0xec, 0x56, 0x8c, 0x87, 0xeb, 0xe1, 0x38, 0x6a, 0x71, 0x3c, 0xda, ++ 0xc1, 0x59, 0xc2, 0xee, 0xe9, 0xcf, 0x21, 0x8d, 0x65, 0xbd, 0xe5, 0x18, ++ 0x57, 0x56, 0x3b, 0x25, 0x07, 0xee, 0xdb, 0xeb, 0xe9, 0x3d, 0x77, 0xe1, ++ 0x84, 0x77, 0xe2, 0xff, 0x01, 0x3a, 0x9f, 0x4b, 0x76, 0x1f, 0x21, 0xfd, ++ 0xd6, 0x7b, 0x79, 0x01, 0xe6, 0x3f, 0x0f, 0x66, 0x7e, 0x3e, 0x0a, 0xed, ++ 0x65, 0xed, 0x30, 0x7c, 0xfb, 0x3b, 0xc1, 0xb7, 0xda, 0xf7, 0x59, 0x1c, ++ 0x63, 0xd5, 0x46, 0xfc, 0x3e, 0xc9, 0x8f, 0x12, 0xdd, 0x9f, 0x20, 0x7e, ++ 0xfb, 0x0d, 0xdf, 0x46, 0x8e, 0x63, 0xf8, 0x7c, 0xdf, 0x7f, 0xaf, 0x91, ++ 0x90, 0x2e, 0x8c, 0xe8, 0x31, 0x9c, 0x9c, 0x9c, 0x12, 0xf3, 0x9d, 0x4a, ++ 0x16, 0xdf, 0x25, 0x8c, 0xe3, 0xfb, 0x24, 0xcb, 0xb1, 0x8f, 0xf2, 0x6a, ++ 0xf4, 0x8e, 0xa4, 0xfc, 0x42, 0xf6, 0x8d, 0xed, 0x4b, 0x35, 0xec, 0x7e, ++ 0x37, 0x07, 0xf5, 0xd6, 0xc5, 0xae, 0x03, 0x39, 0xa6, 0x20, 0x3a, 0x9e, ++ 0x5f, 0x03, 0xf2, 0x8e, 0xf6, 0xa3, 0x63, 0x5f, 0x82, 0x6a, 0x0b, 0xe6, ++ 0x33, 0x03, 0xf1, 0x97, 0x24, 0x69, 0xfc, 0xa6, 0x08, 0xbb, 0x18, 0xca, ++ 0x77, 0xe7, 0x91, 0xef, 0xb2, 0xb1, 0xfd, 0x30, 0x32, 0x1d, 0xf5, 0xee, ++ 0xf6, 0xa3, 0x91, 0xb7, 0xe0, 0x7c, 0xbb, 0x78, 0x3b, 0xc0, 0x9f, 0xed, ++ 0x32, 0x8d, 0x83, 0x78, 0x67, 0xcc, 0xfc, 0x88, 0x60, 0xf8, 0x9e, 0x24, ++ 0xf8, 0x2e, 0xb4, 0xf0, 0x79, 0x18, 0xeb, 0x1b, 0x53, 0x35, 0x3e, 0xf8, ++ 0x7e, 0xe3, 0x70, 0x7c, 0x6b, 0x4c, 0xe1, 0xf5, 0x84, 0x21, 0x7c, 0xab, ++ 0xad, 0xb7, 0x05, 0xbf, 0x87, 0x83, 0xfe, 0x7d, 0xa7, 0x99, 0xbe, 0x87, ++ 0x83, 0xf9, 0xe6, 0xe8, 0x20, 0xb9, 0x48, 0x4d, 0xe1, 0xf2, 0x30, 0x49, ++ 0x7c, 0xff, 0x66, 0x0a, 0xf3, 0xd0, 0xf7, 0x00, 0x27, 0x89, 0xef, 0xe0, ++ 0x4c, 0x51, 0x98, 0x4f, 0x89, 0xc1, 0x7d, 0x2e, 0x9f, 0xcc, 0xf7, 0x65, ++ 0xf9, 0x79, 0x86, 0x02, 0xc1, 0xbf, 0x93, 0x14, 0x5f, 0x17, 0xd6, 0x39, ++ 0x4c, 0x11, 0xfb, 0x32, 0x85, 0xac, 0x97, 0xc6, 0x4d, 0x67, 0x7e, 0x6a, ++ 0x9d, 0xcc, 0x4e, 0xe7, 0x14, 0x8a, 0x99, 0x83, 0xda, 0xc9, 0x16, 0xdf, ++ 0x9d, 0x98, 0x76, 0xc9, 0x6e, 0x69, 0xa1, 0xfa, 0x3f, 0x5f, 0x82, 0x12, ++ 0x7d, 0xd6, 0x22, 0xce, 0x43, 0x0c, 0x41, 0xb7, 0xc0, 0xfa, 0x15, 0xfa, ++ 0xee, 0x0d, 0xf1, 0xa5, 0x8c, 0xe7, 0x61, 0x86, 0xfe, 0x6e, 0x4a, 0x65, ++ 0x0a, 0x97, 0x73, 0xfa, 0x38, 0x07, 0xd2, 0xf7, 0x02, 0xa3, 0xfc, 0x14, ++ 0x7e, 0xdf, 0x0c, 0x5f, 0x32, 0x55, 0x61, 0x15, 0x58, 0x77, 0x74, 0x9b, ++ 0xc2, 0x2c, 0xe1, 0x00, 0xef, 0xf6, 0xb7, 0x0d, 0x24, 0xbf, 0x9d, 0x7d, ++ 0xaa, 0x17, 0xeb, 0x40, 0x1d, 0xb1, 0xe2, 0xb9, 0x2f, 0x18, 0xd5, 0xbb, ++ 0x4e, 0x72, 0x72, 0xf9, 0x44, 0xd3, 0x82, 0x75, 0x12, 0xda, 0x7a, 0xf5, ++ 0x78, 0x28, 0x84, 0xf9, 0x30, 0x3f, 0x36, 0x49, 0x81, 0xc8, 0x92, 0xf0, ++ 0xe8, 0xa3, 0xf7, 0xdd, 0xce, 0xf8, 0x39, 0x8d, 0x22, 0xa6, 0xd2, 0x07, ++ 0x56, 0x6e, 0xc7, 0x8f, 0x27, 0x93, 0x5e, 0xf7, 0x53, 0x9c, 0x54, 0x02, ++ 0x71, 0x12, 0xea, 0x75, 0x83, 0xc5, 0x43, 0xf8, 0x28, 0xc3, 0xe4, 0xca, ++ 0x44, 0xbe, 0xbf, 0x11, 0x09, 0xf3, 0x14, 0x36, 0x4b, 0xec, 0x38, 0xee, ++ 0x57, 0xa4, 0xf1, 0xf5, 0x6a, 0xf3, 0x17, 0x02, 0x23, 0xe0, 0xb9, 0xbd, ++ 0x32, 0xb1, 0x5e, 0x4c, 0x81, 0x1e, 0x8f, 0xe1, 0xfb, 0x1e, 0x91, 0x54, ++ 0x38, 0x5c, 0x6a, 0xe7, 0xdf, 0x09, 0x4a, 0xa0, 0xef, 0x04, 0xdd, 0x28, ++ 0x5e, 0xfb, 0x13, 0xf8, 0x77, 0x21, 0x23, 0xef, 0xf7, 0x5f, 0xfc, 0x7e, ++ 0x7e, 0x60, 0xff, 0xc7, 0x81, 0xdf, 0x0d, 0x8a, 0x0c, 0x7c, 0x8f, 0xd2, ++ 0x81, 0xe7, 0x4c, 0x30, 0x7f, 0xe7, 0x53, 0xce, 0x07, 0xfb, 0xcd, 0x77, ++ 0xa7, 0x2c, 0xad, 0x4e, 0x99, 0x18, 0xa8, 0x97, 0x63, 0x6e, 0xa6, 0xa2, ++ 0x5f, 0xa1, 0xaf, 0x97, 0x43, 0xf4, 0x9d, 0x0b, 0x3a, 0xdf, 0xac, 0xd5, ++ 0x7b, 0xbc, 0xea, 0x9d, 0xab, 0xe2, 0xb9, 0xb9, 0x85, 0x71, 0x16, 0x3a, ++ 0x4f, 0x9b, 0x6b, 0x19, 0x95, 0x87, 0x76, 0x2b, 0x23, 0xd1, 0x5d, 0x9d, ++ 0x42, 0x75, 0x1f, 0x5b, 0x6e, 0xa1, 0x49, 0x14, 0xef, 0x44, 0x57, 0x44, ++ 0x80, 0xcf, 0xad, 0xcc, 0x39, 0x19, 0xf1, 0x1c, 0xa8, 0xd7, 0xe3, 0xdf, ++ 0x4f, 0x1a, 0x38, 0xcf, 0x94, 0xc0, 0xe8, 0xfc, 0x9f, 0xd5, 0xcc, 0xeb, ++ 0x19, 0x9f, 0x01, 0xb9, 0xc0, 0xef, 0x17, 0x81, 0x54, 0xa9, 0x58, 0xd7, ++ 0xc2, 0x9e, 0x28, 0xa1, 0xfa, 0xc7, 0xa7, 0xa2, 0x2d, 0x0e, 0x3c, 0x87, ++ 0x60, 0x46, 0x78, 0xad, 0x01, 0x78, 0x1b, 0x2d, 0xa2, 0xee, 0x47, 0x57, ++ 0x77, 0xd9, 0x68, 0x33, 0xd0, 0xf7, 0x38, 0x1b, 0x59, 0x38, 0x9d, 0xe7, ++ 0x9e, 0x15, 0xe6, 0xfe, 0x1e, 0xae, 0xff, 0xb1, 0x88, 0x62, 0x3a, 0x2f, ++ 0x9d, 0xb5, 0x6d, 0x5a, 0x12, 0xf9, 0x83, 0xb0, 0xde, 0x69, 0xda, 0x7a, ++ 0x0d, 0x83, 0xeb, 0x10, 0xb1, 0xfe, 0x0f, 0x9f, 0xd3, 0xd7, 0xff, 0x69, ++ 0xeb, 0xc2, 0xe3, 0xeb, 0xf8, 0x5e, 0xbb, 0xc0, 0x97, 0xb6, 0x4e, 0xbb, ++ 0x76, 0xde, 0xc7, 0xa9, 0x84, 0x9c, 0xf7, 0xd1, 0xd6, 0xff, 0x4c, 0x38, ++ 0x5f, 0xa7, 0x11, 0x77, 0xe2, 0xd3, 0xe8, 0x59, 0x15, 0xf5, 0x83, 0x7e, ++ 0x7d, 0x1a, 0x3f, 0xfc, 0x3f, 0xdd, 0xfb, 0x35, 0x6d, 0x60, 0x5c, 0x00, ++ 0x00, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 xsem_int_table_data_e1[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xbb, 0x26, ++ 0xcb, 0xc0, 0xf0, 0xa3, 0x1e, 0x81, 0x59, 0x64, 0x18, 0x18, 0x26, 0xf1, ++ 0xa1, 0x8a, 0xd1, 0x12, 0xcf, 0xe0, 0x66, 0x60, 0x78, 0x04, 0xc4, 0x2c, ++ 0x3c, 0x0c, 0x0c, 0x85, 0x40, 0x7b, 0x23, 0x80, 0x74, 0x24, 0x10, 0x1f, ++ 0x01, 0xe2, 0xa3, 0x40, 0xac, 0xc2, 0xcb, 0xc0, 0x10, 0x0b, 0xc4, 0x71, ++ 0x40, 0x3c, 0x07, 0xc8, 0x9f, 0x0b, 0xc4, 0xa5, 0x40, 0x9c, 0x05, 0x75, ++ 0x63, 0x2b, 0x0b, 0x03, 0x43, 0x3b, 0x10, 0x77, 0x02, 0x71, 0x37, 0x10, ++ 0xeb, 0x30, 0x33, 0x30, 0xe8, 0x32, 0x13, 0x6f, 0x7f, 0xb1, 0x08, 0x03, ++ 0xc3, 0x13, 0x09, 0x04, 0x5f, 0x51, 0x12, 0x68, 0xa7, 0x34, 0xfd, 0xfc, ++ 0x3f, 0xd8, 0xf0, 0x0c, 0x7d, 0xfa, 0xda, 0xc7, 0x6d, 0xc0, 0xc0, 0xb0, ++ 0xd4, 0x02, 0xc1, 0x17, 0x03, 0xb2, 0x97, 0x59, 0xa0, 0xaa, 0x59, 0x6e, ++ 0x81, 0xdf, 0x8c, 0x15, 0x68, 0xf2, 0x2b, 0xd1, 0xf8, 0xab, 0xf0, 0xe8, ++ 0xdf, 0xa7, 0x87, 0xca, 0xd7, 0xd3, 0x40, 0x73, 0x9f, 0x16, 0x03, 0x83, ++ 0x15, 0x52, 0x98, 0xe8, 0x6b, 0xe0, 0x77, 0x0b, 0x3a, 0xce, 0x04, 0xea, ++ 0xcd, 0x02, 0x62, 0x00, 0x9f, 0x30, 0x90, 0xcd, 0x68, 0x03, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 xsem_pram_data_e1[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xe5, 0x7d, ++ 0x0b, 0x78, 0x54, 0xd5, 0xb5, 0xf0, 0x3e, 0x73, 0x1e, 0xf3, 0xc8, 0xcc, ++ 0x64, 0x12, 0x42, 0x08, 0x10, 0xc2, 0x09, 0x2f, 0xa3, 0x0d, 0x38, 0x21, ++ 0x21, 0x05, 0x8a, 0xed, 0x10, 0x20, 0xa2, 0x45, 0x8d, 0x8f, 0x2a, 0x54, ++ 0xd4, 0x09, 0x8f, 0x24, 0xe4, 0x35, 0x01, 0x1f, 0x17, 0x6b, 0xdb, 0x0c, ++ 0x04, 0x23, 0x20, 0x68, 0xb0, 0x58, 0xa2, 0x46, 0x3b, 0x41, 0x50, 0xf0, ++ 0x06, 0x1d, 0x68, 0x90, 0x20, 0x01, 0x07, 0xb0, 0x1a, 0x7a, 0x7d, 0x04, ++ 0xaf, 0xf5, 0xd1, 0xf6, 0x7a, 0x83, 0x52, 0x40, 0x08, 0x24, 0xe2, 0x0b, ++ 0xbd, 0x6d, 0xfd, 0xf7, 0x5a, 0x7b, 0x9f, 0xcc, 0x39, 0x27, 0x33, 0x40, ++ 0xff, 0xf6, 0xff, 0x6f, 0xff, 0xfb, 0xc7, 0xaf, 0x3d, 0xec, 0x73, 0xf6, ++ 0x63, 0xed, 0xf5, 0xda, 0x6b, 0xad, 0xbd, 0xf6, 0x1e, 0x99, 0x0c, 0x24, ++ 0xd2, 0x0f, 0x08, 0xf9, 0x16, 0xfe, 0xe8, 0x73, 0xa6, 0x44, 0x08, 0x7d, ++ 0xd5, 0xf7, 0x74, 0xbe, 0x42, 0x54, 0x92, 0x48, 0x48, 0x7d, 0x0e, 0x2d, ++ 0xa7, 0x10, 0x92, 0x3e, 0x8a, 0x84, 0x88, 0x40, 0x48, 0x41, 0x0d, 0x2d, ++ 0xe7, 0x11, 0xf2, 0xd0, 0x6d, 0x24, 0x64, 0xcd, 0x24, 0x64, 0xff, 0xeb, ++ 0x16, 0xfc, 0xbe, 0xca, 0xcf, 0xca, 0xb4, 0x5d, 0xd8, 0x72, 0x39, 0xfd, ++ 0x3e, 0x9a, 0xbd, 0x7f, 0x2c, 0x8b, 0xb6, 0xa3, 0xef, 0x1f, 0x3b, 0x27, ++ 0x62, 0xbb, 0xe0, 0x2c, 0x12, 0xda, 0x4c, 0xcb, 0x49, 0x84, 0xf6, 0x36, ++ 0x92, 0xd0, 0x21, 0xfc, 0xf8, 0x2c, 0xf0, 0x36, 0xd8, 0xc7, 0xd2, 0xfa, ++ 0x4d, 0xb7, 0x59, 0x88, 0x55, 0x25, 0xe4, 0x51, 0x3a, 0x0c, 0x99, 0x44, ++ 0x88, 0x8b, 0xf8, 0xec, 0x84, 0x36, 0x5d, 0x35, 0x8a, 0xf5, 0xf7, 0xc8, ++ 0x2c, 0xcb, 0x33, 0xa2, 0x00, 0x1f, 0x23, 0x69, 0xf3, 0x69, 0x79, 0xf5, ++ 0xf4, 0x92, 0xfc, 0xd5, 0xb4, 0xb4, 0x46, 0x66, 0x70, 0x35, 0xce, 0x29, ++ 0x79, 0x26, 0x48, 0xfb, 0xf7, 0x58, 0x46, 0xe2, 0x3c, 0x68, 0xbd, 0xc7, ++ 0x9c, 0xb4, 0xde, 0xc3, 0xef, 0x97, 0x92, 0xd5, 0xb4, 0xdd, 0x86, 0xb9, ++ 0x16, 0xa1, 0x24, 0x9b, 0xd6, 0x6b, 0x56, 0x66, 0x87, 0xb2, 0xa3, 0xf3, ++ 0xd7, 0x9e, 0x73, 0x89, 0xc4, 0xdb, 0x05, 0xad, 0x96, 0x89, 0xf0, 0xf4, ++ 0xf1, 0x67, 0x44, 0x81, 0xe7, 0x2f, 0xa6, 0x58, 0x70, 0x9c, 0xb5, 0x35, ++ 0x0c, 0x1f, 0xb4, 0x9e, 0x62, 0x49, 0x23, 0xa4, 0xb5, 0xf3, 0x80, 0xcd, ++ 0x4f, 0xfb, 0x5b, 0x5b, 0xd9, 0x7a, 0xb8, 0x90, 0x7e, 0x7f, 0x70, 0x94, ++ 0xc5, 0x4b, 0x31, 0x48, 0x1e, 0xec, 0x3c, 0x60, 0xbf, 0x84, 0x8e, 0x1f, ++ 0xcc, 0xb3, 0x78, 0x47, 0xd3, 0xda, 0xe9, 0x52, 0x44, 0xf0, 0x38, 0xa3, ++ 0xe3, 0x4d, 0x22, 0x14, 0xf0, 0x09, 0xb4, 0x9e, 0x77, 0x87, 0x4d, 0x75, ++ 0xf6, 0xaf, 0x4f, 0xfb, 0x9d, 0x0a, 0xf3, 0x5e, 0x43, 0xf1, 0x2e, 0x66, ++ 0x46, 0xdb, 0x8d, 0x07, 0x38, 0x69, 0xbb, 0xb5, 0x94, 0x64, 0x61, 0x3a, ++ 0xee, 0x2f, 0x65, 0xef, 0x21, 0x18, 0xf7, 0x97, 0xd7, 0x24, 0x0b, 0x41, ++ 0x12, 0xad, 0x77, 0x15, 0x00, 0x09, 0xf5, 0xe6, 0x5a, 0x48, 0x84, 0xd6, ++ 0x23, 0x52, 0xaf, 0x8d, 0xd0, 0x71, 0x56, 0x4f, 0x79, 0xdb, 0x36, 0x9a, ++ 0xd6, 0x5f, 0x5d, 0x64, 0x81, 0x49, 0x90, 0xb5, 0x5e, 0xed, 0xbb, 0xd7, ++ 0x4e, 0xa0, 0xbf, 0x19, 0x63, 0x0e, 0x8d, 0x02, 0xba, 0x5e, 0x45, 0xbf, ++ 0xc3, 0x3c, 0xb2, 0x1f, 0x99, 0x0d, 0xf3, 0x7e, 0x78, 0xba, 0x42, 0x00, ++ 0xff, 0xbf, 0x14, 0x68, 0x3d, 0x8a, 0xe2, 0xc6, 0x62, 0xe5, 0x87, 0x00, ++ 0x9f, 0xab, 0x86, 0x78, 0xe0, 0x3d, 0x7d, 0xfa, 0x62, 0xe1, 0xb5, 0x4d, ++ 0xb0, 0x21, 0x1c, 0x64, 0xcd, 0x06, 0x42, 0xf2, 0x09, 0x80, 0x80, 0x7f, ++ 0xab, 0x7d, 0xa1, 0x95, 0x23, 0x80, 0xbf, 0xf2, 0x88, 0x17, 0xca, 0xe9, ++ 0x5e, 0xda, 0xde, 0xd9, 0xbf, 0x7d, 0x97, 0x60, 0x45, 0xba, 0x34, 0xca, ++ 0xc1, 0xc1, 0x80, 0xbf, 0x78, 0xf4, 0x1b, 0xc5, 0xf1, 0xb9, 0x3a, 0x6b, ++ 0x89, 0x1d, 0xe8, 0x41, 0x48, 0x43, 0x5a, 0xd1, 0x58, 0x42, 0xd6, 0x03, ++ 0x9e, 0x60, 0x50, 0xc9, 0xaf, 0x5e, 0xef, 0x8a, 0xd6, 0x5f, 0x29, 0x30, ++ 0xfc, 0xac, 0x93, 0x89, 0x4f, 0xa0, 0xf3, 0x4b, 0xc8, 0x53, 0x42, 0xcb, ++ 0x28, 0x9e, 0x2d, 0xd9, 0x9e, 0x39, 0x30, 0x5f, 0xa7, 0x5f, 0x21, 0x57, ++ 0xd2, 0xf2, 0x2a, 0x21, 0x38, 0x58, 0x04, 0xba, 0x8c, 0x55, 0xc8, 0x66, ++ 0x15, 0xf9, 0xc2, 0x3e, 0x9a, 0x96, 0xd7, 0x5e, 0x9a, 0xec, 0x05, 0xfe, ++ 0xab, 0x17, 0xc2, 0x69, 0x12, 0x7c, 0xbf, 0x86, 0x7e, 0xa7, 0x5d, 0x1e, ++ 0x28, 0x1a, 0x3f, 0x07, 0xf8, 0xb3, 0xc9, 0xab, 0x20, 0x3f, 0x53, 0xfe, ++ 0x39, 0x04, 0xf8, 0x5e, 0xeb, 0x4f, 0x26, 0xab, 0x55, 0xfc, 0xde, 0x89, ++ 0xed, 0x9d, 0xa3, 0x3c, 0x56, 0xc4, 0x04, 0x85, 0x87, 0xe2, 0x65, 0x00, ++ 0xe5, 0x25, 0xc0, 0x6b, 0xce, 0x75, 0xf5, 0x57, 0x8d, 0x04, 0xfa, 0x4c, ++ 0xb0, 0x78, 0x80, 0x42, 0xab, 0x85, 0xa9, 0xea, 0x7c, 0x90, 0x9f, 0x24, ++ 0x9b, 0x07, 0xc6, 0x97, 0x27, 0xdc, 0x80, 0xf4, 0x93, 0x07, 0x26, 0x0b, ++ 0x44, 0x47, 0xef, 0x9f, 0x03, 0xbd, 0x29, 0x9e, 0x6a, 0xd5, 0xa2, 0x9f, ++ 0xc3, 0xbc, 0x9e, 0xc8, 0xfb, 0x28, 0x69, 0x34, 0xad, 0xbf, 0x26, 0xe7, ++ 0xc5, 0x46, 0xa0, 0xd3, 0x93, 0xf7, 0xd8, 0x90, 0x7e, 0x4f, 0x4e, 0xe8, ++ 0x5c, 0x0c, 0x72, 0xf5, 0xd8, 0xb9, 0xdc, 0xf7, 0xfd, 0x28, 0x97, 0x8a, ++ 0x77, 0x33, 0xed, 0xe7, 0xa9, 0x9c, 0x63, 0x99, 0x84, 0x0e, 0xf8, 0xc8, ++ 0xcc, 0x8f, 0x92, 0x00, 0x7f, 0xc3, 0x46, 0x35, 0xdc, 0x49, 0xdc, 0xf4, ++ 0x39, 0xab, 0xb7, 0x96, 0x8c, 0xa3, 0xf0, 0x91, 0x86, 0xa2, 0x05, 0x99, ++ 0xc8, 0x27, 0xc2, 0x8d, 0x14, 0xaf, 0xc3, 0x96, 0x2a, 0x44, 0xb5, 0x31, ++ 0x5a, 0x7e, 0x4b, 0xe0, 0x3b, 0xf1, 0x85, 0xb3, 0x59, 0xd9, 0x49, 0xe7, ++ 0x33, 0x8c, 0xd3, 0xb9, 0xb5, 0xf3, 0x6d, 0x5b, 0x31, 0xf4, 0x37, 0x97, ++ 0x44, 0xc6, 0xb8, 0xf1, 0xbd, 0x2d, 0x35, 0x39, 0xaa, 0x67, 0x86, 0xe5, ++ 0x91, 0x48, 0x2a, 0xed, 0xff, 0xb1, 0x85, 0xaf, 0xa2, 0x9c, 0x3f, 0x79, ++ 0x59, 0xaa, 0x97, 0xc9, 0x79, 0x1a, 0xf2, 0x4b, 0x06, 0xef, 0x27, 0x1d, ++ 0xea, 0x53, 0xfd, 0x92, 0x66, 0x23, 0xc1, 0x04, 0xfa, 0x1c, 0xd6, 0xd1, ++ 0x7b, 0x03, 0xc0, 0x35, 0x2c, 0xeb, 0xd8, 0x5c, 0x80, 0x73, 0xff, 0x1b, ++ 0xaf, 0x0a, 0x40, 0xb7, 0xa7, 0xc6, 0xa5, 0xaa, 0xa0, 0x8f, 0x92, 0xfc, ++ 0x9d, 0xa4, 0x8b, 0xd2, 0x7d, 0x58, 0xf6, 0xbb, 0xf7, 0x41, 0x3d, 0x97, ++ 0x33, 0x94, 0x56, 0x94, 0x8d, 0xf5, 0xff, 0x82, 0xed, 0x4c, 0xf0, 0x3f, ++ 0xa9, 0xfa, 0x36, 0x01, 0xde, 0xb6, 0x09, 0x35, 0x87, 0x80, 0x3e, 0xc1, ++ 0x1c, 0x8b, 0x97, 0xd1, 0x9b, 0xe9, 0xc1, 0x35, 0x77, 0xa5, 0x86, 0x40, ++ 0x8f, 0x0c, 0x73, 0xfc, 0xf1, 0x7a, 0x71, 0x04, 0xf2, 0x01, 0x21, 0xa9, ++ 0x14, 0x3e, 0x0f, 0x41, 0x39, 0xa9, 0x17, 0x22, 0xb6, 0x91, 0xd0, 0xee, ++ 0x5e, 0xd6, 0x6e, 0x38, 0x09, 0x09, 0x80, 0xe7, 0x61, 0x59, 0xc1, 0xc5, ++ 0xa2, 0x1b, 0xea, 0xfb, 0x85, 0x22, 0x57, 0xff, 0x71, 0x5b, 0x41, 0x23, ++ 0x82, 0x7c, 0x50, 0x4e, 0x07, 0x7e, 0xdd, 0xae, 0x90, 0xf2, 0xa2, 0x18, ++ 0x72, 0xf0, 0x32, 0x97, 0xe7, 0x7a, 0x81, 0xcc, 0x46, 0x7e, 0x26, 0xd2, ++ 0x5f, 0x81, 0x6f, 0x86, 0x27, 0x31, 0xbe, 0xd1, 0xca, 0x4f, 0x01, 0x3c, ++ 0x74, 0xdc, 0xed, 0xaf, 0x24, 0xff, 0x30, 0x9b, 0xc2, 0xf3, 0xab, 0xa5, ++ 0x23, 0x72, 0x44, 0x0a, 0xcf, 0x43, 0xd0, 0x2e, 0x86, 0xdc, 0xac, 0xe5, ++ 0x72, 0xe0, 0xe8, 0x20, 0x41, 0x81, 0xe2, 0x75, 0xff, 0x6f, 0x7f, 0x6b, ++ 0x07, 0xbc, 0x6d, 0xb7, 0x90, 0x32, 0xa8, 0x3f, 0x35, 0x2b, 0x6c, 0xeb, ++ 0xe2, 0x74, 0x05, 0x7a, 0x2c, 0x24, 0xac, 0xff, 0xa6, 0xec, 0x8d, 0x36, ++ 0xd4, 0x17, 0x42, 0x16, 0xf2, 0xdd, 0xc2, 0x89, 0x8a, 0xcf, 0x3e, 0x0e, ++ 0xe4, 0x6f, 0xb9, 0xe0, 0xa7, 0xed, 0xd3, 0x3c, 0x4c, 0x2f, 0xbb, 0xbc, ++ 0x4a, 0x08, 0xf4, 0xb2, 0x2b, 0x2d, 0x28, 0x58, 0x28, 0x3c, 0x6a, 0x36, ++ 0xf1, 0x6c, 0xcc, 0x64, 0xdd, 0x05, 0x29, 0xfe, 0xe6, 0xc1, 0x3f, 0x80, ++ 0xd1, 0x25, 0x56, 0x7f, 0xcd, 0xda, 0xa4, 0xd0, 0x6a, 0xfa, 0x7d, 0x5e, ++ 0x36, 0x15, 0x34, 0xc0, 0x1b, 0xc5, 0x95, 0x85, 0x8e, 0xbb, 0x80, 0xb0, ++ 0x79, 0xce, 0xf3, 0xd6, 0x2f, 0x06, 0xfa, 0x11, 0x52, 0x64, 0x01, 0x7c, ++ 0xae, 0xf6, 0x30, 0xfa, 0x34, 0xc1, 0x38, 0x74, 0x2a, 0x4d, 0xe9, 0xac, ++ 0x9f, 0xb5, 0x77, 0x93, 0xd0, 0x72, 0xe0, 0x23, 0x0f, 0x6b, 0x3f, 0x0a, ++ 0x9a, 0x50, 0xba, 0x8d, 0xca, 0x7b, 0xf1, 0x5f, 0x04, 0xda, 0x6f, 0x3a, ++ 0x6f, 0x07, 0x72, 0x0f, 0xed, 0x12, 0xd2, 0x42, 0x36, 0x0b, 0x6d, 0xa7, ++ 0xd6, 0x58, 0x08, 0xc2, 0x27, 0x45, 0x0e, 0x09, 0x40, 0xf7, 0xb1, 0xa9, ++ 0x2a, 0xc0, 0xd3, 0x94, 0xe6, 0xfd, 0xf7, 0x59, 0x00, 0xff, 0x6c, 0xc9, ++ 0xbb, 0x91, 0x7e, 0x1e, 0x05, 0x70, 0xd0, 0x7e, 0x9a, 0x6a, 0x2c, 0x3e, ++ 0xd4, 0x17, 0x79, 0x4a, 0x33, 0xe8, 0xe9, 0xd5, 0x3e, 0xa6, 0xe7, 0x35, ++ 0x7c, 0x65, 0xf2, 0x71, 0xd3, 0xbd, 0x11, 0x81, 0xce, 0x9d, 0x64, 0x52, ++ 0x3d, 0x89, 0x78, 0xf2, 0x45, 0xec, 0x1e, 0x28, 0x67, 0x33, 0x78, 0x32, ++ 0xf3, 0xd8, 0xbc, 0xfa, 0xe0, 0x1f, 0xab, 0x84, 0x96, 0xd3, 0xc6, 0xe9, ++ 0xb6, 0x08, 0x81, 0x7a, 0x1a, 0x1e, 0x4a, 0x78, 0x7f, 0x25, 0x7c, 0x1e, ++ 0xce, 0xb4, 0xd0, 0x4a, 0x09, 0xe0, 0xce, 0x63, 0x70, 0xd3, 0x75, 0x19, ++ 0xe1, 0x49, 0xcf, 0x56, 0x9a, 0x41, 0x0e, 0xd2, 0xd3, 0x58, 0x7f, 0x2a, ++ 0xc5, 0x8f, 0x86, 0x77, 0x80, 0xcb, 0xa1, 0xc1, 0x95, 0x47, 0xeb, 0x83, ++ 0x1e, 0xf6, 0x2a, 0xcd, 0xc0, 0x0a, 0x0e, 0x0e, 0x5f, 0x49, 0x36, 0x83, ++ 0x67, 0xff, 0xeb, 0x6f, 0x77, 0x08, 0xac, 0x3f, 0x94, 0x2b, 0x07, 0x87, ++ 0xd7, 0xc1, 0xe7, 0x4f, 0x00, 0xde, 0x54, 0xae, 0xd7, 0x69, 0x7f, 0x2d, ++ 0x72, 0x44, 0x10, 0x69, 0xfd, 0xd0, 0x04, 0xa2, 0x6e, 0x64, 0xa3, 0xa9, ++ 0x52, 0x7e, 0xf4, 0xfb, 0x23, 0x35, 0x14, 0x0f, 0xb4, 0xe0, 0xe4, 0xe3, ++ 0x90, 0xf5, 0x56, 0x94, 0x07, 0xfa, 0x2a, 0xf8, 0x2d, 0xe5, 0x83, 0xf9, ++ 0x0d, 0xb4, 0x9c, 0x15, 0x95, 0x8f, 0xd1, 0x2b, 0xad, 0x06, 0x79, 0x71, ++ 0xf2, 0x79, 0x93, 0x06, 0x26, 0x47, 0x94, 0x6d, 0x22, 0xd0, 0x2e, 0x93, ++ 0xb0, 0xb2, 0x05, 0xca, 0x74, 0x1e, 0x25, 0x59, 0x46, 0x39, 0x23, 0x5e, ++ 0x5d, 0x99, 0xc2, 0xe1, 0x02, 0x7e, 0xa7, 0xfa, 0x67, 0xd9, 0x24, 0x85, ++ 0xf1, 0xcf, 0xa5, 0xcc, 0x8e, 0x21, 0x44, 0x57, 0x0f, 0xf8, 0x7c, 0x82, ++ 0xfa, 0xf4, 0x1a, 0xfc, 0xae, 0xe0, 0xba, 0x9e, 0xf1, 0x53, 0xc5, 0x00, ++ 0xdf, 0xb0, 0x9a, 0xd4, 0x02, 0x11, 0xf4, 0x49, 0xc7, 0xe3, 0x37, 0x58, ++ 0x80, 0xaf, 0xee, 0x22, 0x16, 0x31, 0x11, 0xf9, 0x59, 0xe8, 0xd3, 0x5f, ++ 0x74, 0xbc, 0x1d, 0x4b, 0x22, 0x76, 0x98, 0xa4, 0xa3, 0xa3, 0x28, 0x19, ++ 0xf0, 0x96, 0x51, 0x93, 0x5c, 0xa0, 0x00, 0x1e, 0x3b, 0xfc, 0x58, 0x76, ++ 0x74, 0xd4, 0xf8, 0xf0, 0x09, 0x4b, 0xd3, 0x78, 0x42, 0x86, 0x10, 0xdd, ++ 0x38, 0x99, 0xa0, 0x5f, 0x3d, 0x15, 0x2d, 0x14, 0xaf, 0xa4, 0x46, 0x09, ++ 0x83, 0xbe, 0x9e, 0xa0, 0x87, 0x93, 0x7e, 0xcf, 0x78, 0xa5, 0xe1, 0x7a, ++ 0xa0, 0xd7, 0x03, 0x8b, 0x5f, 0x1d, 0x0c, 0xf2, 0x9b, 0x6a, 0x6a, 0x3f, ++ 0xce, 0x32, 0x02, 0xe5, 0x74, 0xd8, 0x2b, 0xb4, 0x16, 0x8e, 0x7f, 0xec, ++ 0x67, 0x50, 0x7f, 0x15, 0xd7, 0x27, 0x0e, 0x80, 0x78, 0x3c, 0x3e, 0x5f, ++ 0x81, 0xe7, 0x30, 0x27, 0xd5, 0xb3, 0x54, 0x4f, 0x67, 0x50, 0x04, 0x2b, ++ 0xe3, 0xa3, 0xfa, 0x62, 0xf5, 0xa5, 0xef, 0xe6, 0xf8, 0x9d, 0x9c, 0x7f, ++ 0x92, 0xf1, 0x19, 0x81, 0xa7, 0x59, 0xaf, 0xe8, 0xea, 0x5f, 0xca, 0xeb, ++ 0x07, 0x85, 0xf3, 0xd6, 0x3b, 0x86, 0xf5, 0x34, 0x78, 0xcc, 0xdf, 0xcf, ++ 0x08, 0x16, 0xd4, 0x53, 0x2e, 0xb0, 0x33, 0x29, 0x7e, 0x1f, 0x26, 0x9e, ++ 0x39, 0xb8, 0x2e, 0x7b, 0x2d, 0xb8, 0x2e, 0x26, 0xf0, 0xf7, 0x61, 0xef, ++ 0x81, 0x02, 0xa4, 0x67, 0x98, 0x78, 0x85, 0x4c, 0xd0, 0xb7, 0x7f, 0xb5, ++ 0xea, 0xf9, 0xe0, 0x27, 0xf0, 0x12, 0xf4, 0xad, 0x14, 0x46, 0x39, 0x51, ++ 0x32, 0x1c, 0x68, 0x1f, 0x52, 0x39, 0x4e, 0x80, 0x75, 0xaf, 0x49, 0xaa, ++ 0x29, 0x83, 0xf7, 0xe1, 0x74, 0x07, 0x01, 0xbd, 0x70, 0x60, 0xc6, 0xab, ++ 0x02, 0xe0, 0x33, 0xbd, 0xcd, 0x3f, 0x1c, 0xe4, 0x50, 0xb3, 0x73, 0x0b, ++ 0xbc, 0xe1, 0x34, 0x78, 0xff, 0xe0, 0x21, 0xff, 0x25, 0x28, 0x9f, 0x71, ++ 0xec, 0x46, 0xcd, 0x4e, 0x34, 0xcf, 0x67, 0xe8, 0x15, 0xcb, 0x51, 0x1f, ++ 0x0c, 0xf7, 0xf7, 0x76, 0xc0, 0x7a, 0xef, 0xac, 0x94, 0xbc, 0x57, 0x02, ++ 0x7f, 0xf9, 0x29, 0x5c, 0x4e, 0xd4, 0x93, 0x2a, 0xf9, 0x2e, 0x85, 0xdf, ++ 0x1b, 0x5c, 0x06, 0x7a, 0x56, 0xf5, 0xd3, 0xf2, 0x20, 0xfa, 0xac, 0xe4, ++ 0xcf, 0x32, 0xf6, 0x7d, 0x55, 0x6d, 0x59, 0xee, 0x51, 0x29, 0xda, 0xef, ++ 0xaa, 0x51, 0xd4, 0x1e, 0xa5, 0x7a, 0x71, 0x7d, 0xe7, 0x7a, 0xdb, 0x35, ++ 0x60, 0x67, 0xd4, 0x58, 0x54, 0xe0, 0xdb, 0xb5, 0xde, 0xb7, 0x6d, 0x3e, ++ 0x27, 0x94, 0x0b, 0x06, 0x00, 0x9e, 0x5b, 0x8b, 0x34, 0xbb, 0x2f, 0x22, ++ 0xc0, 0x78, 0xe9, 0xef, 0xf8, 0xd0, 0xce, 0x9b, 0xe0, 0x51, 0x3c, 0xa0, ++ 0xb4, 0xc6, 0x5a, 0x23, 0x83, 0x3d, 0xba, 0xf5, 0xa2, 0x69, 0xc6, 0xbb, ++ 0xe3, 0x01, 0x0e, 0x72, 0x13, 0x25, 0xe2, 0xe0, 0xf8, 0x74, 0xa4, 0xf3, ++ 0x45, 0x3e, 0x8b, 0xb7, 0x9e, 0x00, 0x2c, 0x16, 0xdd, 0x3a, 0xb2, 0x3f, ++ 0x6b, 0x07, 0xae, 0x2f, 0x6f, 0x90, 0x4b, 0x91, 0x2e, 0xda, 0xba, 0xa2, ++ 0xad, 0x23, 0xd8, 0x23, 0xd5, 0x2f, 0xf3, 0xb9, 0x1c, 0x3d, 0xa8, 0x86, ++ 0x6d, 0x02, 0xea, 0x2b, 0x2a, 0xbb, 0x94, 0x3e, 0xf3, 0xb9, 0x1e, 0x71, ++ 0x72, 0xbd, 0x49, 0xf5, 0x30, 0xd3, 0x73, 0x7c, 0x3d, 0x59, 0xbb, 0x38, ++ 0x15, 0xd7, 0x13, 0x4d, 0x7f, 0x82, 0x6d, 0x0d, 0x4a, 0x62, 0x3e, 0xd7, ++ 0xb7, 0x6b, 0x73, 0x9e, 0x49, 0xba, 0x86, 0xc2, 0xe4, 0x04, 0x3d, 0x0b, ++ 0x7a, 0x29, 0x8d, 0x14, 0xc0, 0xfa, 0x3b, 0x1a, 0xf4, 0x0c, 0xe8, 0x27, ++ 0x29, 0x28, 0xc0, 0x78, 0x4d, 0x13, 0x3c, 0x64, 0x35, 0xae, 0x63, 0x46, ++ 0x7d, 0x3a, 0xba, 0x86, 0xe9, 0xc1, 0x07, 0xd3, 0x08, 0xf2, 0x13, 0x5d, ++ 0x87, 0x9a, 0x61, 0xbd, 0x6b, 0x4a, 0x0f, 0xa7, 0x41, 0x3f, 0x4d, 0x35, ++ 0x07, 0x04, 0xbf, 0x6e, 0xfd, 0xd4, 0xd6, 0x3b, 0x57, 0x4d, 0x27, 0x01, ++ 0x3d, 0x38, 0x2f, 0x8f, 0xad, 0x73, 0xf3, 0xb2, 0xd9, 0x78, 0xbf, 0x07, ++ 0x04, 0x4d, 0x60, 0xf0, 0x82, 0x5e, 0x35, 0xaf, 0x7b, 0xbf, 0x98, 0xb2, ++ 0x03, 0x95, 0x65, 0x02, 0xb7, 0xb7, 0xcc, 0xf8, 0x17, 0x2c, 0xcc, 0x0e, ++ 0x7c, 0x78, 0xd6, 0xdb, 0x88, 0xc7, 0xb5, 0x0b, 0x1e, 0xc1, 0x27, 0x69, ++ 0xd8, 0x80, 0xfd, 0xa5, 0xd9, 0x18, 0x0d, 0x56, 0x65, 0x1d, 0xc0, 0xf7, ++ 0x6b, 0xfc, 0x96, 0x99, 0x60, 0x77, 0xaf, 0x97, 0x3a, 0x57, 0x8e, 0xa2, ++ 0xf0, 0xaf, 0x9f, 0x39, 0x4f, 0x09, 0xd2, 0xef, 0x6b, 0xbc, 0xcc, 0xef, ++ 0x5a, 0x3d, 0x65, 0xde, 0x33, 0xb0, 0xae, 0x59, 0x2d, 0x0a, 0x83, 0xab, ++ 0xa6, 0x0c, 0xed, 0xd5, 0x04, 0x0e, 0xd7, 0x06, 0xe8, 0x1b, 0xfd, 0x44, ++ 0x05, 0xfd, 0xa2, 0xbb, 0x6f, 0xdb, 0xb8, 0x72, 0x04, 0xed, 0x27, 0x8d, ++ 0xfa, 0x31, 0x82, 0x0a, 0x95, 0x42, 0x36, 0x2b, 0xfd, 0xee, 0x04, 0x9a, ++ 0x82, 0xfe, 0xf6, 0x47, 0x18, 0xfc, 0x5e, 0x52, 0x40, 0x62, 0xc0, 0xff, ++ 0x1f, 0x82, 0x83, 0xf9, 0xa1, 0xfe, 0xce, 0x8e, 0xd1, 0x48, 0x4f, 0x8b, ++ 0x07, 0xe0, 0x4d, 0xf0, 0xf6, 0xda, 0xc0, 0x4f, 0x54, 0xa9, 0x1f, 0xa6, ++ 0xaa, 0x00, 0xaf, 0x6a, 0x1f, 0x8b, 0xf0, 0x5a, 0x3c, 0xcb, 0xd4, 0x68, ++ 0xfb, 0xdf, 0x71, 0x7f, 0xe1, 0x76, 0x58, 0xf8, 0xc1, 0xbe, 0x9f, 0xf3, ++ 0xee, 0x4c, 0x90, 0xaf, 0x75, 0xb7, 0x31, 0xbf, 0xcc, 0x0c, 0xff, 0xdd, ++ 0x53, 0x43, 0x1d, 0x16, 0x1c, 0x87, 0xa0, 0x5b, 0xe7, 0x8a, 0x83, 0xd7, ++ 0xb9, 0xa0, 0xc1, 0x40, 0xff, 0x78, 0x43, 0x08, 0x97, 0x2b, 0x8b, 0xc1, ++ 0x75, 0x54, 0x60, 0xf4, 0x7a, 0xb8, 0xb3, 0xe0, 0x2a, 0xf4, 0x93, 0x8a, ++ 0xe8, 0x7b, 0xda, 0xd1, 0x23, 0x9d, 0x23, 0xec, 0x20, 0xdf, 0xfd, 0xec, ++ 0xcc, 0x84, 0x0f, 0x73, 0xd0, 0xde, 0x31, 0xad, 0x33, 0x17, 0x2a, 0x0f, ++ 0x33, 0xe9, 0xfb, 0xb1, 0xd6, 0xf0, 0xd5, 0xc8, 0x6f, 0xdb, 0x2c, 0xa8, ++ 0xa7, 0x08, 0x61, 0x7a, 0x4e, 0x20, 0x16, 0xf5, 0xdb, 0x91, 0xb0, 0x88, ++ 0x30, 0xb8, 0x90, 0xf5, 0xa8, 0xfe, 0x5e, 0x21, 0x47, 0xe6, 0x2c, 0xa0, ++ 0xf5, 0x57, 0xec, 0x74, 0x12, 0xc0, 0x97, 0xc6, 0x0f, 0xe9, 0xbc, 0xcf, ++ 0xd5, 0x35, 0x94, 0x0f, 0x62, 0xcc, 0xbb, 0x43, 0x10, 0xe3, 0xd1, 0x9d, ++ 0xd9, 0x19, 0x9c, 0xee, 0x9d, 0x30, 0xde, 0xc0, 0x0b, 0xd3, 0x9f, 0x4a, ++ 0xb3, 0x1d, 0xec, 0xb6, 0x70, 0xa8, 0x7e, 0x48, 0x39, 0xf8, 0x1f, 0x35, ++ 0xcc, 0xdf, 0x0d, 0x47, 0x0e, 0xa0, 0xfe, 0x49, 0x9f, 0x7e, 0x33, 0xfa, ++ 0x29, 0x5b, 0x9a, 0x53, 0xe7, 0x2c, 0x00, 0xbe, 0xca, 0xf2, 0x79, 0x01, ++ 0x1d, 0x1a, 0x3c, 0x60, 0x9f, 0xc4, 0xf2, 0x13, 0xaf, 0xb6, 0xd8, 0xce, ++ 0xeb, 0xbf, 0xc7, 0xd3, 0xc3, 0x8d, 0x95, 0x2b, 0xd0, 0xef, 0x6d, 0xec, ++ 0x8c, 0x3d, 0xff, 0x29, 0x16, 0xe6, 0x6f, 0x87, 0xa9, 0x9e, 0xf4, 0x66, ++ 0xc7, 0x1f, 0x3f, 0xdf, 0xc2, 0xec, 0xe8, 0x24, 0x0b, 0xe7, 0xbb, 0x19, ++ 0xaf, 0xa6, 0xe9, 0xd7, 0x33, 0x6d, 0x5d, 0xd5, 0xd6, 0xd9, 0x61, 0x12, ++ 0x09, 0x8a, 0xba, 0xf5, 0xf0, 0x26, 0x8e, 0x3f, 0xf3, 0xba, 0x49, 0xa4, ++ 0x06, 0xdb, 0x18, 0xc6, 0xe7, 0xe8, 0x3f, 0x36, 0x2e, 0x60, 0x71, 0x88, ++ 0x0d, 0x53, 0x2c, 0x18, 0x5f, 0xd1, 0xf8, 0x9c, 0xd6, 0x4b, 0x03, 0xbc, ++ 0xd2, 0x79, 0xa0, 0x3d, 0x47, 0xf9, 0x30, 0x04, 0xf6, 0xdc, 0xc3, 0xa4, ++ 0x01, 0xe5, 0x26, 0x48, 0xdb, 0x6f, 0x26, 0xfd, 0xe1, 0xbe, 0x8d, 0x58, ++ 0x2e, 0x6a, 0x7e, 0x93, 0xf9, 0xfc, 0xfa, 0xc6, 0xe3, 0xfe, 0xf5, 0xed, ++ 0x5c, 0x5f, 0xad, 0xcb, 0xb9, 0xc7, 0x0e, 0x5d, 0xd1, 0xf1, 0xd2, 0x80, ++ 0x3f, 0x02, 0x6e, 0xa6, 0x27, 0xab, 0x5c, 0xcc, 0x8e, 0x9d, 0xb6, 0x53, ++ 0x8e, 0xfc, 0x80, 0xc2, 0x51, 0xd5, 0x2c, 0xa0, 0x9d, 0x65, 0xd9, 0x67, ++ 0x47, 0x38, 0xcf, 0x6c, 0xa2, 0x65, 0xda, 0x75, 0xc4, 0xa5, 0x60, 0xfd, ++ 0xd3, 0x1e, 0x1b, 0x96, 0x03, 0xd6, 0xce, 0x87, 0xbe, 0x47, 0xcb, 0xbd, ++ 0x3b, 0x45, 0x82, 0x76, 0x64, 0x96, 0xc3, 0x02, 0xfc, 0x7a, 0x8c, 0xf3, ++ 0x2b, 0xc9, 0xa3, 0x65, 0xb0, 0x87, 0xed, 0xac, 0x58, 0xd5, 0xbc, 0xff, ++ 0x76, 0xe8, 0xaf, 0xac, 0xcd, 0x4a, 0xec, 0xb4, 0xff, 0xaa, 0xdd, 0xa5, ++ 0xd7, 0x7e, 0x8f, 0x96, 0x4b, 0x3b, 0x64, 0x02, 0x55, 0xaa, 0x36, 0x2f, ++ 0x53, 0x86, 0xd0, 0xf2, 0xa2, 0x90, 0x10, 0x86, 0x72, 0x4f, 0x01, 0x5d, ++ 0xa8, 0x00, 0x2f, 0xc9, 0x4a, 0x08, 0xfc, 0xf6, 0x1e, 0x77, 0x67, 0xea, ++ 0x8f, 0xe8, 0xbc, 0x4f, 0xd6, 0xda, 0x88, 0x4a, 0x41, 0xa9, 0x73, 0x75, ++ 0xa6, 0xde, 0x44, 0xf1, 0x51, 0x1e, 0xda, 0x5e, 0x08, 0xed, 0xca, 0x5b, ++ 0x04, 0xd0, 0x88, 0x74, 0x1e, 0x9b, 0x5f, 0x1d, 0x0c, 0xf3, 0xda, 0x2a, ++ 0x78, 0xc1, 0xbf, 0xaf, 0xd8, 0x92, 0x60, 0xb0, 0x07, 0x8f, 0xd1, 0xa9, ++ 0xfc, 0x80, 0x7e, 0x5f, 0x42, 0xe7, 0x09, 0x72, 0x59, 0x4a, 0x1a, 0x0a, ++ 0x61, 0x9d, 0xab, 0xda, 0xbc, 0x4e, 0x51, 0x75, 0xf1, 0x87, 0x93, 0xb5, ++ 0x1e, 0x1c, 0x47, 0x2b, 0x57, 0x6d, 0xa5, 0xe3, 0xd0, 0x76, 0xd5, 0xcf, ++ 0x0b, 0x5e, 0x98, 0x62, 0xb5, 0x85, 0xf8, 0x41, 0x0f, 0x9d, 0xd9, 0x6d, ++ 0x9f, 0xfd, 0xb4, 0x13, 0xe6, 0xb7, 0x4c, 0x19, 0xe3, 0x82, 0x79, 0x3d, ++ 0xa0, 0x40, 0xbd, 0xd2, 0x50, 0xf1, 0x8b, 0x76, 0x15, 0xe0, 0x6b, 0x56, ++ 0x0a, 0xe9, 0xf7, 0xf2, 0xa6, 0x66, 0x05, 0xe2, 0x5b, 0x01, 0x2b, 0xb9, ++ 0x03, 0xfc, 0xdc, 0x8a, 0x2d, 0x03, 0x8c, 0x70, 0x35, 0x8a, 0x28, 0xaf, ++ 0x4b, 0x92, 0x6c, 0x1b, 0x41, 0x9f, 0x13, 0xa7, 0x2f, 0xed, 0x86, 0xb1, ++ 0xfd, 0xe9, 0x7c, 0xb2, 0x96, 0xea, 0xd8, 0x31, 0xd1, 0x72, 0x39, 0xe8, ++ 0x43, 0xe4, 0xc3, 0x90, 0x72, 0xbd, 0xae, 0xfe, 0x70, 0x31, 0x09, 0xf9, ++ 0xb5, 0x62, 0x8b, 0x68, 0xb4, 0xb3, 0xf9, 0xfa, 0x1f, 0x3c, 0xcc, 0xe8, ++ 0x1f, 0xdc, 0xeb, 0xc2, 0xb8, 0x9f, 0x46, 0xbf, 0x25, 0xdc, 0x5f, 0xd6, ++ 0xe8, 0xb7, 0x24, 0x89, 0xd3, 0x53, 0xea, 0xcd, 0x8f, 0x05, 0xcf, 0x43, ++ 0x40, 0x0f, 0x0a, 0x4f, 0x03, 0xe0, 0x8b, 0x3e, 0xd7, 0x70, 0xf8, 0xdc, ++ 0x53, 0xc8, 0x54, 0x88, 0xbb, 0xb8, 0x7d, 0xc4, 0x23, 0xc4, 0xe0, 0x6b, ++ 0xf3, 0xb3, 0x41, 0x26, 0xc5, 0xc0, 0xba, 0xff, 0xba, 0xfc, 0xfa, 0xa9, ++ 0xd2, 0x60, 0x74, 0x1f, 0x16, 0x43, 0xe4, 0xc9, 0xb3, 0x62, 0xce, 0xd4, ++ 0xe9, 0xb4, 0xfc, 0x3b, 0x4b, 0xd1, 0x66, 0x0b, 0xea, 0x0f, 0xaf, 0x0a, ++ 0x72, 0xa4, 0xf9, 0xd9, 0x4f, 0x59, 0x98, 0x5c, 0xd6, 0x0f, 0x56, 0x10, ++ 0x7f, 0x0d, 0x33, 0xf2, 0x9f, 0x66, 0xf1, 0x09, 0x82, 0xeb, 0x5e, 0xc3, ++ 0x8c, 0x92, 0x67, 0xc0, 0x2e, 0xa0, 0xed, 0xb7, 0x59, 0x50, 0x0e, 0x69, ++ 0xfb, 0xb1, 0xf1, 0xdb, 0x7b, 0x0a, 0x27, 0x1a, 0xda, 0x7b, 0x0a, 0xcb, ++ 0xb4, 0xf6, 0x3b, 0xb1, 0xbd, 0xed, 0xfc, 0xed, 0x1b, 0x0a, 0x27, 0x1b, ++ 0xc7, 0x2f, 0x2c, 0xd7, 0xda, 0xef, 0x45, 0xf8, 0x9d, 0xe7, 0x87, 0xdf, ++ 0x73, 0xe5, 0x14, 0xe3, 0xf8, 0x57, 0x56, 0x62, 0xfb, 0x80, 0x95, 0xd1, ++ 0xab, 0x37, 0xc9, 0x86, 0x76, 0xcd, 0x0a, 0xbb, 0xd7, 0x27, 0x31, 0x3b, ++ 0x2a, 0x02, 0xef, 0xa5, 0xe4, 0x31, 0x1b, 0xa1, 0x9e, 0xa8, 0xf1, 0x03, ++ 0xe9, 0xf4, 0x81, 0xfd, 0xed, 0x6c, 0x49, 0x1a, 0xbf, 0x9a, 0xe8, 0xf9, ++ 0xa2, 0xe0, 0x0d, 0x80, 0xc3, 0x45, 0xa5, 0x45, 0xcf, 0x17, 0x89, 0x13, ++ 0x1d, 0x06, 0x7e, 0x4c, 0xf2, 0x25, 0x1b, 0xca, 0xb4, 0x27, 0xcf, 0xb1, ++ 0xef, 0xf0, 0x32, 0x0c, 0xe2, 0xb6, 0x21, 0x3c, 0xca, 0x10, 0x05, 0xf5, ++ 0xc5, 0xd4, 0x21, 0x36, 0x84, 0xf7, 0x9e, 0x7d, 0x76, 0x2c, 0xdf, 0x33, ++ 0x99, 0xc1, 0x7b, 0xcf, 0x10, 0x27, 0xca, 0x19, 0xae, 0x2d, 0x94, 0x8e, ++ 0xf7, 0x28, 0xfe, 0xcb, 0xf5, 0x76, 0x2b, 0xac, 0x4c, 0x10, 0x4a, 0x7a, ++ 0x53, 0xf4, 0x7f, 0x04, 0xf8, 0x8d, 0xbe, 0x57, 0x2d, 0xf0, 0xde, 0x21, ++ 0x92, 0x1a, 0xd4, 0xcf, 0x56, 0x82, 0xfa, 0xe8, 0x81, 0xcc, 0xfc, 0xa7, ++ 0x83, 0x3a, 0xfc, 0xac, 0x1c, 0x46, 0xe9, 0x4b, 0xcb, 0xa7, 0xc1, 0xfe, ++ 0x19, 0x18, 0xc5, 0xeb, 0x03, 0xc3, 0x4a, 0xd2, 0x8a, 0x75, 0xe3, 0xd4, ++ 0x0f, 0x53, 0x66, 0x6f, 0xcc, 0x66, 0xef, 0xe7, 0x3b, 0x61, 0xbc, 0xa2, ++ 0x1e, 0xc0, 0x43, 0x40, 0xe9, 0x1d, 0x03, 0x76, 0xa5, 0x79, 0x1c, 0xeb, ++ 0x88, 0x89, 0x86, 0x71, 0x6c, 0x19, 0x65, 0x38, 0xce, 0x37, 0xa6, 0x71, ++ 0xac, 0x19, 0x65, 0xa6, 0x71, 0x6c, 0xb3, 0x37, 0xf2, 0xf7, 0x7c, 0x9c, ++ 0x3f, 0xc3, 0xbc, 0xe2, 0x8d, 0xf3, 0xc0, 0x88, 0xc9, 0xc6, 0xf9, 0x64, ++ 0x94, 0xe3, 0x38, 0x56, 0xd1, 0x34, 0x9f, 0x8c, 0x72, 0xd3, 0x38, 0x0e, ++ 0x36, 0x1f, 0xfa, 0x9e, 0x8f, 0x63, 0x17, 0xcf, 0x37, 0x9f, 0x91, 0x53, ++ 0x8c, 0xf3, 0x19, 0x5e, 0x89, 0xe3, 0xa4, 0x88, 0x8a, 0x21, 0x6e, 0x65, ++ 0x1d, 0x5e, 0x69, 0x1a, 0xc7, 0x89, 0xe3, 0xc0, 0x7b, 0x18, 0x87, 0xa4, ++ 0x33, 0xff, 0x46, 0xb1, 0xf6, 0x96, 0x20, 0xfd, 0x5f, 0xb6, 0x13, 0xb0, ++ 0xa7, 0x15, 0xab, 0xff, 0x59, 0xe8, 0x97, 0xfc, 0xc1, 0x4e, 0x50, 0x9f, ++ 0xa8, 0x74, 0xdc, 0x41, 0xa0, 0x57, 0x92, 0x71, 0xbf, 0xe0, 0x3f, 0x2c, ++ 0xc9, 0x38, 0x9f, 0x2f, 0x1d, 0x94, 0xfe, 0x4e, 0x3d, 0x9d, 0x83, 0x9a, ++ 0x5d, 0x80, 0xf6, 0xce, 0x42, 0x0e, 0x22, 0x09, 0xd5, 0xa3, 0x7f, 0x5e, ++ 0xcd, 0x79, 0x74, 0x41, 0xcb, 0xf5, 0x19, 0xcb, 0xe0, 0xd9, 0x36, 0x2d, ++ 0xad, 0x18, 0xfc, 0xec, 0xf5, 0x2e, 0x2f, 0xc4, 0x4f, 0xcf, 0xb4, 0x4d, ++ 0x53, 0xe6, 0xc7, 0xb0, 0x0b, 0x16, 0x36, 0xc8, 0xc7, 0xba, 0x0c, 0xfc, ++ 0xcb, 0xf5, 0x5e, 0x01, 0xc9, 0xaa, 0x01, 0x3f, 0x8b, 0xdb, 0x01, 0x5a, ++ 0xf9, 0x18, 0xd5, 0x5f, 0x84, 0xea, 0xad, 0x8f, 0xa8, 0xfe, 0x82, 0xe7, ++ 0x71, 0x99, 0xea, 0x69, 0xfa, 0xfe, 0x28, 0xd5, 0x6f, 0x44, 0xd1, 0xc3, ++ 0xbb, 0x0c, 0xdb, 0x1d, 0x93, 0x18, 0x1e, 0x8f, 0x35, 0xb1, 0x75, 0xe4, ++ 0xcb, 0x75, 0x87, 0x65, 0x8c, 0xf3, 0x05, 0xc9, 0x3b, 0x59, 0x74, 0x1e, ++ 0x37, 0xf3, 0x69, 0x2c, 0x6c, 0x48, 0x60, 0xbe, 0x02, 0x87, 0x23, 0xc0, ++ 0xe9, 0xd1, 0xbb, 0xdb, 0x1a, 0xda, 0x88, 0xf4, 0xf0, 0x0d, 0x05, 0xbb, ++ 0x87, 0x34, 0x0e, 0xa0, 0xb8, 0xe2, 0xf5, 0x46, 0x00, 0xbe, 0xa8, 0xb8, ++ 0x24, 0x63, 0x71, 0x28, 0xd8, 0x47, 0x3f, 0x5e, 0xb9, 0xfd, 0x37, 0x50, ++ 0xed, 0x5d, 0xa1, 0x78, 0xd8, 0x12, 0x3a, 0xdf, 0xd9, 0xad, 0xeb, 0xe4, ++ 0xa1, 0xb4, 0x7c, 0x46, 0xee, 0xba, 0xdd, 0xeb, 0xd4, 0xf5, 0x33, 0x5b, ++ 0xfe, 0x08, 0xe6, 0x6d, 0xa3, 0xff, 0x41, 0x3f, 0x73, 0xfc, 0xb4, 0xac, ++ 0x1b, 0xff, 0xd6, 0x32, 0x63, 0xf9, 0x36, 0x22, 0x45, 0xcb, 0x94, 0x6e, ++ 0x33, 0xc4, 0x11, 0x9c, 0x1e, 0x7c, 0x5c, 0x35, 0x24, 0x03, 0xbd, 0x6e, ++ 0x4e, 0x65, 0xf0, 0xdc, 0x06, 0xcf, 0xf1, 0xf0, 0xd9, 0x83, 0xf4, 0xba, ++ 0xdd, 0xc3, 0xda, 0x6a, 0xf0, 0x04, 0xee, 0x93, 0x49, 0x04, 0xd7, 0xa3, ++ 0xae, 0x81, 0xcc, 0xb8, 0x1d, 0x88, 0xf5, 0xfc, 0xda, 0xba, 0x62, 0x82, ++ 0xef, 0x76, 0xd9, 0xe6, 0x2b, 0xa2, 0xf4, 0xbc, 0xfd, 0x5e, 0x11, 0xf1, ++ 0x68, 0x86, 0xb7, 0x6b, 0x5f, 0x82, 0xcf, 0x42, 0xfd, 0xaa, 0xae, 0xc6, ++ 0xcf, 0x64, 0xf0, 0x2f, 0x2f, 0x04, 0xff, 0x1d, 0x4b, 0x8d, 0xdf, 0x49, ++ 0x90, 0x8d, 0xa7, 0xe1, 0x55, 0xe3, 0x83, 0x5b, 0x66, 0x4f, 0x1d, 0x70, ++ 0x54, 0x57, 0x6f, 0x8e, 0xff, 0xaa, 0x01, 0x47, 0x75, 0xfc, 0x72, 0x6b, ++ 0xd9, 0xf5, 0x86, 0xf2, 0x6d, 0x35, 0x73, 0x0c, 0xf5, 0xef, 0x58, 0x5a, ++ 0x6c, 0xf8, 0x5e, 0x1c, 0x5c, 0x64, 0xf8, 0x3e, 0x7f, 0xe5, 0x62, 0x43, ++ 0x79, 0x61, 0xc3, 0xbd, 0x86, 0xfa, 0xa5, 0x8d, 0xcb, 0x0c, 0xdf, 0x17, ++ 0x85, 0x56, 0x19, 0xbe, 0x57, 0x6c, 0x59, 0x67, 0x28, 0x57, 0x85, 0x1f, ++ 0x33, 0xd4, 0x0f, 0xb4, 0x35, 0x1b, 0xbe, 0x5b, 0xf6, 0x5d, 0x7a, 0x1d, ++ 0xc8, 0x63, 0xdd, 0xef, 0x44, 0x02, 0xf6, 0xd9, 0x17, 0xce, 0x63, 0x0f, ++ 0x81, 0x7d, 0xf5, 0x85, 0x53, 0x42, 0xbf, 0xaa, 0x1a, 0x78, 0x8d, 0xca, ++ 0xe1, 0x89, 0xda, 0x34, 0xe4, 0xef, 0x93, 0xb5, 0x2a, 0x3e, 0xcf, 0xb4, ++ 0xe5, 0xe2, 0xfe, 0x58, 0xc0, 0x41, 0xe5, 0x99, 0xae, 0xf5, 0x1b, 0xea, ++ 0x0e, 0x2d, 0x5b, 0x39, 0x05, 0xf4, 0x08, 0xad, 0x4f, 0x75, 0xf8, 0x13, ++ 0x75, 0x6f, 0x2d, 0x0b, 0x52, 0xdf, 0x7d, 0x23, 0x04, 0xa9, 0x29, 0xdf, ++ 0x8b, 0x8d, 0x0a, 0x89, 0x0c, 0x00, 0x3f, 0x26, 0xb9, 0x8f, 0xaf, 0x7b, ++ 0x45, 0xdd, 0xf7, 0xae, 0x0b, 0x7c, 0x6f, 0xa4, 0x0b, 0x56, 0x6e, 0xff, ++ 0xef, 0x62, 0x57, 0xec, 0xf7, 0x3d, 0x42, 0xef, 0x18, 0xb0, 0xef, 0x82, ++ 0x1f, 0x58, 0x71, 0xff, 0x26, 0x9e, 0xfd, 0x40, 0xff, 0x86, 0x92, 0x18, ++ 0xfe, 0x83, 0xf6, 0xec, 0x86, 0xf8, 0x86, 0x4e, 0xef, 0xbc, 0x2c, 0x32, ++ 0xbb, 0xfa, 0x72, 0xb1, 0xe0, 0x65, 0x91, 0x3e, 0x2b, 0x15, 0x26, 0xef, ++ 0x95, 0x3b, 0x06, 0x17, 0x40, 0xbc, 0xa0, 0x52, 0x89, 0x8c, 0xa9, 0x89, ++ 0x61, 0x67, 0xf7, 0x8d, 0x17, 0xa6, 0xc0, 0x0c, 0x82, 0x7e, 0x98, 0xbc, ++ 0x2c, 0x0a, 0x0d, 0x8d, 0xca, 0x2f, 0xd2, 0x6f, 0xa4, 0x41, 0xee, 0xaf, ++ 0xb1, 0xf8, 0xf7, 0x81, 0x7e, 0xee, 0xde, 0x2f, 0xb2, 0xfd, 0x81, 0xc8, ++ 0xc1, 0x0c, 0xd8, 0xa7, 0xb9, 0x5c, 0xf4, 0xbd, 0x0c, 0xef, 0x49, 0xdb, ++ 0x40, 0x5c, 0x1f, 0xdf, 0xad, 0xf5, 0x0d, 0x38, 0x3a, 0x8a, 0x90, 0xf7, ++ 0x6b, 0x67, 0xe2, 0xf3, 0xf7, 0xb5, 0x45, 0x03, 0x20, 0x7e, 0xf4, 0xc7, ++ 0xda, 0xd9, 0x58, 0xfe, 0xb0, 0xd6, 0x8f, 0xcf, 0xae, 0xda, 0x32, 0x7c, ++ 0x7e, 0x54, 0x5b, 0x83, 0xdf, 0x8f, 0xd6, 0x2e, 0xc5, 0xf2, 0xb1, 0xda, ++ 0x20, 0x3e, 0x4f, 0xd4, 0xae, 0xc4, 0xe7, 0xc9, 0xda, 0x06, 0xfc, 0xde, ++ 0x5d, 0xdb, 0x88, 0xe5, 0x33, 0xb5, 0x21, 0x7c, 0x6a, 0x72, 0xa0, 0xd9, ++ 0xa3, 0x24, 0x85, 0xdb, 0x7f, 0xdc, 0x5e, 0xa7, 0x2b, 0x07, 0x96, 0xcf, ++ 0xf2, 0x39, 0x88, 0xf4, 0xdf, 0x9d, 0x28, 0xd7, 0xde, 0x34, 0x90, 0xeb, ++ 0xb3, 0xce, 0x2f, 0xc7, 0x80, 0x9d, 0x7b, 0xf6, 0x7d, 0x2b, 0x06, 0xd1, ++ 0xe3, 0xe1, 0xc9, 0xcc, 0x6f, 0xf1, 0xe9, 0xe7, 0xc3, 0xf5, 0xbe, 0x24, ++ 0x44, 0xe9, 0x9f, 0xdb, 0xff, 0xbb, 0xdd, 0xc1, 0xe8, 0x63, 0xb7, 0x90, ++ 0x99, 0xe0, 0x9f, 0xad, 0x1a, 0xad, 0x10, 0x88, 0xab, 0x3b, 0x5e, 0xfe, ++ 0x0e, 0xda, 0xcb, 0xf4, 0xbd, 0x44, 0x50, 0x5f, 0x86, 0xbc, 0xfa, 0x7d, ++ 0xc4, 0xbe, 0xfe, 0x61, 0xce, 0x83, 0x2e, 0x4c, 0x27, 0xad, 0xfe, 0xb1, ++ 0xc7, 0xff, 0x2b, 0x7f, 0x5e, 0x36, 0xd0, 0x87, 0xd1, 0xd7, 0x71, 0x50, ++ 0xac, 0x61, 0x74, 0x7b, 0xda, 0x0b, 0x74, 0xd3, 0xe1, 0x8f, 0xd9, 0x65, ++ 0x3b, 0xb9, 0x3e, 0x37, 0xe1, 0x51, 0xe2, 0x72, 0x67, 0xc6, 0xe7, 0xe9, ++ 0x81, 0x1a, 0x3e, 0x3b, 0x33, 0x20, 0xde, 0x52, 0x25, 0x16, 0x59, 0x24, ++ 0xfa, 0xee, 0x6c, 0xab, 0x15, 0xe7, 0x75, 0xb6, 0x3d, 0x81, 0xed, 0x63, ++ 0x7b, 0x52, 0x2e, 0x2a, 0x9e, 0x57, 0xb1, 0xc5, 0xee, 0xd1, 0xeb, 0x87, ++ 0xaa, 0x70, 0x92, 0xc7, 0xa8, 0x2f, 0x06, 0x7b, 0xf4, 0xfa, 0xe2, 0x6c, ++ 0xc7, 0xd3, 0x6e, 0x90, 0xfb, 0x25, 0x69, 0x16, 0xcf, 0xd1, 0x5c, 0xe0, ++ 0x0f, 0x1f, 0xe7, 0x0f, 0xc6, 0x77, 0x5a, 0xff, 0x55, 0xe1, 0x4c, 0x8f, ++ 0xd3, 0xd0, 0x8f, 0xb1, 0x7c, 0xb6, 0x41, 0x98, 0xc9, 0xf6, 0x15, 0xd5, ++ 0xc4, 0x9b, 0x62, 0xf8, 0x07, 0xda, 0x73, 0x49, 0x9a, 0xe2, 0x39, 0x4a, ++ 0xf5, 0xc2, 0xc9, 0x2d, 0x23, 0x13, 0x61, 0x5c, 0xea, 0xc7, 0x79, 0x60, ++ 0x9c, 0xee, 0x5a, 0x8f, 0x87, 0x8d, 0x9b, 0xe6, 0xd1, 0xf3, 0x65, 0xe5, ++ 0x52, 0x07, 0xd6, 0xd7, 0xe0, 0x8b, 0xd7, 0xef, 0x3f, 0x1a, 0x3e, 0xd8, ++ 0xf1, 0xfb, 0xd8, 0xc6, 0x62, 0x4d, 0x10, 0xa7, 0x89, 0x57, 0x3f, 0x2e, ++ 0x3d, 0xa4, 0xcf, 0x15, 0xf0, 0x0f, 0x48, 0xbb, 0xfc, 0x25, 0xac, 0x3b, ++ 0x8e, 0x2c, 0x6d, 0xdd, 0x91, 0xb0, 0xac, 0xf5, 0x1b, 0x08, 0x8b, 0x41, ++ 0xeb, 0xe5, 0xf0, 0xbe, 0xc5, 0x30, 0x1e, 0x6d, 0xa7, 0x6a, 0x3e, 0x34, ++ 0xb4, 0x8b, 0x4f, 0x77, 0x89, 0x1c, 0xd3, 0xe8, 0x49, 0xf5, 0xe4, 0x95, ++ 0x3c, 0x3f, 0x84, 0x32, 0x33, 0xd2, 0xd9, 0x4f, 0x7b, 0x4c, 0xa4, 0xfd, ++ 0xf5, 0x48, 0xce, 0x95, 0x10, 0xe7, 0xcd, 0x94, 0x54, 0xd4, 0x77, 0x01, ++ 0x18, 0x88, 0xf2, 0x53, 0x95, 0xad, 0x4b, 0xf1, 0xab, 0x88, 0xee, 0x4e, ++ 0x8c, 0x7b, 0x4e, 0xd4, 0xe4, 0x5e, 0xbd, 0xe5, 0x0f, 0x94, 0xe5, 0x3e, ++ 0xf9, 0x37, 0x19, 0xe3, 0x19, 0xe4, 0xcf, 0xb4, 0x77, 0xfa, 0x5d, 0xe6, ++ 0x5f, 0x17, 0x90, 0x22, 0x37, 0x38, 0x19, 0xf3, 0x5a, 0x2b, 0x66, 0x81, ++ 0x9e, 0xfc, 0xc4, 0xa2, 0xd9, 0x03, 0x0d, 0xf9, 0x30, 0xef, 0xd3, 0xc4, ++ 0x82, 0xfb, 0xf9, 0xa7, 0xc9, 0xdb, 0xee, 0x5c, 0x9d, 0x5d, 0x56, 0x26, ++ 0xf1, 0xf8, 0xe4, 0x4a, 0xb6, 0x3e, 0x07, 0xe9, 0x7f, 0x30, 0x3f, 0x6a, ++ 0xa7, 0x19, 0xd6, 0xeb, 0xd2, 0x46, 0x63, 0xb9, 0x84, 0xdc, 0x90, 0x0a, ++ 0xf2, 0x50, 0xb2, 0x5e, 0x86, 0x1d, 0x5b, 0xb2, 0x08, 0xd6, 0x7b, 0xdd, ++ 0xbe, 0xc9, 0x6c, 0xc9, 0x83, 0xf3, 0x2e, 0x25, 0x35, 0xf5, 0x60, 0xa7, ++ 0xac, 0x96, 0xd9, 0x3e, 0xea, 0x3c, 0x0f, 0x91, 0x86, 0x52, 0xb8, 0xaa, ++ 0x76, 0x3d, 0x99, 0x0f, 0xf6, 0x6c, 0x40, 0x62, 0xfa, 0x5e, 0xf3, 0x9f, ++ 0x17, 0x25, 0x33, 0xb8, 0xcb, 0x53, 0x42, 0x8a, 0x8f, 0x7e, 0xff, 0xb8, ++ 0x35, 0xf7, 0xe6, 0xef, 0x11, 0x68, 0x1f, 0xaa, 0x07, 0xbd, 0x16, 0x74, ++ 0x11, 0x6f, 0xac, 0x78, 0xcc, 0xfc, 0x95, 0x46, 0xf8, 0x2e, 0x04, 0xbf, ++ 0x19, 0x5e, 0x42, 0x96, 0x1b, 0xe0, 0xd0, 0xfa, 0xd5, 0xe0, 0x10, 0xb7, ++ 0x08, 0x31, 0xf3, 0x34, 0x7e, 0x26, 0x09, 0x3c, 0xae, 0xc3, 0xe4, 0x63, ++ 0xad, 0x64, 0xb4, 0x5f, 0x1f, 0xe1, 0x78, 0xd0, 0xca, 0x1b, 0x4c, 0xe5, ++ 0x26, 0x53, 0x7d, 0x8d, 0x4f, 0x64, 0xce, 0x27, 0x99, 0x92, 0xff, 0x11, ++ 0xd0, 0x3f, 0x55, 0xb6, 0xde, 0x42, 0xb4, 0xd3, 0x08, 0xe5, 0x8f, 0xec, ++ 0x68, 0x3d, 0x25, 0x5a, 0x6f, 0xc3, 0xf9, 0xea, 0x59, 0xa1, 0x9e, 0x88, ++ 0xf5, 0x9a, 0xa4, 0x09, 0xf1, 0xeb, 0xd9, 0xa3, 0xfd, 0x35, 0xc7, 0xea, ++ 0xaf, 0x6a, 0xd7, 0xb6, 0x17, 0x83, 0x94, 0x9f, 0xca, 0x5f, 0x78, 0xd4, ++ 0x0d, 0x41, 0xdf, 0x4f, 0xa4, 0x86, 0x54, 0x88, 0x7f, 0x55, 0x6e, 0xbe, ++ 0xdf, 0x0d, 0x78, 0x3a, 0x21, 0x05, 0xdd, 0x40, 0xef, 0x4f, 0x42, 0x62, ++ 0xcc, 0xb8, 0xe0, 0x7b, 0x7d, 0xf8, 0xf2, 0x39, 0x05, 0xf0, 0x23, 0x90, ++ 0xb5, 0x29, 0xde, 0x9f, 0x7b, 0xf0, 0x5a, 0xd0, 0xd7, 0x5f, 0x6e, 0x96, ++ 0x31, 0x2f, 0x26, 0xb0, 0xc5, 0x1a, 0xb1, 0x52, 0x3e, 0xae, 0x6e, 0x5d, ++ 0x34, 0x0b, 0xe2, 0xf7, 0xb4, 0x7c, 0x84, 0x95, 0x1f, 0xf8, 0x14, 0xf6, ++ 0x0d, 0x03, 0x6d, 0x46, 0x7a, 0x96, 0x3f, 0xfb, 0x68, 0x2a, 0xc4, 0x89, ++ 0x28, 0x26, 0x99, 0xbd, 0x4d, 0x22, 0x68, 0x77, 0x54, 0x6f, 0xfa, 0x53, ++ 0x21, 0xe8, 0xf1, 0x00, 0xe9, 0x45, 0x3e, 0x34, 0xb7, 0x83, 0xf1, 0xcf, ++ 0x25, 0xa3, 0xdc, 0x17, 0x2b, 0x89, 0xfd, 0xbf, 0x6b, 0xf9, 0x0a, 0x01, ++ 0x2e, 0x67, 0x81, 0xd6, 0x07, 0x3f, 0x85, 0xbc, 0x84, 0x80, 0x89, 0x7f, ++ 0xca, 0xfa, 0xd6, 0x93, 0x2e, 0x05, 0xe2, 0x08, 0x1d, 0x92, 0x2b, 0x05, ++ 0xfd, 0xf2, 0xef, 0x92, 0xef, 0x82, 0x1e, 0xd0, 0xf0, 0x41, 0x42, 0xcc, ++ 0x9e, 0xa8, 0xdb, 0xba, 0x61, 0xdc, 0x11, 0x0a, 0x4f, 0xf7, 0xa6, 0x7f, ++ 0x73, 0x0b, 0x06, 0xbf, 0x9b, 0xf1, 0xe1, 0xd9, 0xf0, 0xfc, 0x5f, 0xbd, ++ 0xa4, 0xc6, 0xd7, 0x33, 0x67, 0xb8, 0x3f, 0x14, 0x6d, 0x17, 0xc2, 0x76, ++ 0x6a, 0x1b, 0xb3, 0x7f, 0x48, 0x3b, 0x7b, 0x56, 0xca, 0x11, 0x37, 0xd8, ++ 0x9b, 0x95, 0xcd, 0xb2, 0x97, 0x72, 0x28, 0xa9, 0xdc, 0xf6, 0xf4, 0x33, ++ 0x8f, 0x83, 0x9f, 0xf6, 0x81, 0x15, 0xfd, 0xb4, 0x8a, 0x6d, 0xbf, 0x79, ++ 0x77, 0x32, 0x2d, 0x57, 0x6c, 0x97, 0x53, 0x66, 0xb1, 0xe9, 0x38, 0x85, ++ 0xd4, 0x28, 0x5d, 0x02, 0xf4, 0x7f, 0x4b, 0xc7, 0x47, 0xe9, 0x50, 0xfe, ++ 0xeb, 0xdf, 0x28, 0xea, 0x58, 0xf6, 0xfe, 0xa7, 0xc9, 0x51, 0x7a, 0x54, ++ 0x6c, 0xdf, 0xaf, 0x90, 0xb1, 0xfd, 0xf1, 0x37, 0x2d, 0xbc, 0x5f, 0xe9, ++ 0x72, 0xc6, 0xa0, 0x4b, 0xf8, 0x48, 0x21, 0xd8, 0x2b, 0x75, 0x5b, 0xbf, ++ 0x52, 0xc0, 0xef, 0xfa, 0x64, 0x9f, 0x40, 0x06, 0x65, 0xf6, 0x6f, 0x5f, ++ 0xd6, 0xfc, 0x1b, 0x5c, 0x0f, 0x01, 0x4f, 0x48, 0x47, 0x4e, 0xa7, 0x3e, ++ 0xba, 0xf5, 0xa3, 0x57, 0xe4, 0xda, 0x97, 0xf2, 0xb0, 0x9e, 0x07, 0xf4, ++ 0x64, 0x3c, 0x7a, 0x3d, 0xc7, 0xf5, 0x72, 0xd5, 0x2e, 0x17, 0x49, 0x82, ++ 0xf8, 0xe7, 0xef, 0xad, 0xa1, 0x59, 0x40, 0xc7, 0xe7, 0xef, 0x74, 0xc3, ++ 0x3c, 0x8e, 0x4b, 0x35, 0x8c, 0xaf, 0x9f, 0xbc, 0x3f, 0x15, 0xf6, 0xff, ++ 0xca, 0xe4, 0x60, 0xaa, 0x07, 0x9f, 0xec, 0x7d, 0xd9, 0x53, 0x77, 0x23, ++ 0xbf, 0x95, 0x0a, 0x35, 0xa9, 0x6c, 0x1f, 0xd3, 0x37, 0x98, 0xc7, 0xcb, ++ 0x07, 0xc3, 0xfc, 0x16, 0x36, 0xfd, 0x08, 0xe7, 0x57, 0x42, 0xfc, 0xc8, ++ 0x77, 0x65, 0x4f, 0x8a, 0x45, 0x10, 0x1f, 0xfe, 0x42, 0x22, 0x33, 0xb7, ++ 0xc7, 0x90, 0x8b, 0x6b, 0x64, 0xb6, 0xff, 0x74, 0x7c, 0xa3, 0x15, 0x92, ++ 0xfc, 0xc8, 0x71, 0xb0, 0xf3, 0xc1, 0xbe, 0x7e, 0x5b, 0xc4, 0x38, 0x2b, ++ 0x21, 0x8b, 0x71, 0x1f, 0xec, 0x6e, 0x2d, 0x8e, 0x4b, 0x96, 0x60, 0xf9, ++ 0x0b, 0xbe, 0x2f, 0x35, 0x4a, 0xb6, 0x68, 0xfe, 0xa1, 0xcd, 0xc0, 0xaf, ++ 0x9b, 0x1e, 0xe8, 0x04, 0xfa, 0x9c, 0x1c, 0xe6, 0x1b, 0x04, 0x70, 0x52, ++ 0x3c, 0x04, 0x39, 0xbe, 0x04, 0xd8, 0xef, 0x17, 0x0f, 0xcf, 0x18, 0xc4, ++ 0xe8, 0xc3, 0xf2, 0x0d, 0xb0, 0x1d, 0xd5, 0xff, 0xd3, 0xe0, 0x3d, 0xd4, ++ 0xef, 0x94, 0x71, 0x9f, 0x50, 0xd7, 0x8e, 0xeb, 0x4b, 0x36, 0xfe, 0x5d, ++ 0x7c, 0x7c, 0x0a, 0xb7, 0x03, 0xd6, 0xb3, 0xe3, 0xa9, 0x6c, 0xbf, 0xd2, ++ 0x3c, 0xbf, 0xa5, 0x7c, 0x7e, 0xf4, 0xaf, 0x93, 0xe8, 0xf8, 0x4b, 0x27, ++ 0xdf, 0x4c, 0xde, 0x37, 0xad, 0x62, 0xf2, 0xad, 0xc9, 0x7b, 0xe8, 0xfa, ++ 0x99, 0xf0, 0xfd, 0xf3, 0x77, 0x98, 0xfc, 0x40, 0x3b, 0x58, 0x3f, 0x28, ++ 0x5c, 0x91, 0x41, 0xf8, 0x7d, 0xff, 0x4d, 0x02, 0xea, 0x03, 0x2b, 0x89, ++ 0xc4, 0x92, 0xeb, 0x4d, 0x32, 0x97, 0x6b, 0xe3, 0xf7, 0x00, 0x95, 0x53, ++ 0x88, 0x0b, 0x50, 0xb8, 0x25, 0xc8, 0x67, 0x88, 0xf2, 0x09, 0xed, 0x3f, ++ 0x19, 0xf1, 0x8f, 0x7e, 0x49, 0xc9, 0x7a, 0xda, 0x4e, 0x67, 0x9f, 0x05, ++ 0x60, 0x3c, 0xac, 0xa7, 0x44, 0xdf, 0xeb, 0xd6, 0x8f, 0x52, 0xae, 0x07, ++ 0x66, 0xca, 0x46, 0xf9, 0x27, 0x4d, 0x03, 0x2f, 0xca, 0x5e, 0xac, 0x94, ++ 0x49, 0x10, 0x4c, 0xcb, 0xca, 0x0f, 0xac, 0xe8, 0x77, 0x57, 0x6e, 0x93, ++ 0x8b, 0x60, 0xde, 0xa7, 0x5a, 0x0e, 0xbe, 0xfb, 0x63, 0xca, 0xd7, 0xa7, ++ 0xc2, 0x9a, 0x9c, 0x1a, 0xf5, 0xa7, 0x59, 0x4e, 0xcb, 0x76, 0x6c, 0x16, ++ 0x80, 0x3f, 0xcd, 0x72, 0x7a, 0xaa, 0x8c, 0xae, 0xd6, 0xb1, 0xe4, 0x94, ++ 0xbe, 0x8f, 0x29, 0xa7, 0x65, 0x5d, 0xff, 0x57, 0xf4, 0xa7, 0x86, 0xb7, ++ 0x80, 0x09, 0x6f, 0x54, 0x0f, 0x0e, 0x4f, 0xb2, 0xc4, 0xc7, 0x9f, 0x59, ++ 0x0f, 0xba, 0x64, 0x35, 0xa6, 0x1e, 0xa4, 0x7f, 0xef, 0x90, 0xfc, 0xfe, ++ 0x7c, 0xa7, 0xf1, 0x9b, 0xc6, 0x67, 0xd4, 0x42, 0x1b, 0x0e, 0xfa, 0xbb, ++ 0x8f, 0x1f, 0x35, 0x7e, 0xeb, 0xe3, 0x47, 0x8d, 0xdf, 0xcc, 0xf3, 0x34, ++ 0xe2, 0xcd, 0xfc, 0x7d, 0x32, 0x18, 0x6a, 0x14, 0xae, 0xa2, 0xdd, 0x32, ++ 0xfa, 0x25, 0x95, 0xed, 0x6c, 0xff, 0x86, 0xb6, 0x7b, 0x75, 0x68, 0x1e, ++ 0xe2, 0xc7, 0x87, 0xcb, 0x17, 0x69, 0x78, 0x75, 0x68, 0x8a, 0xbe, 0x1c, ++ 0x32, 0x95, 0xc3, 0xa6, 0xfa, 0x3e, 0x53, 0xb9, 0xc8, 0x54, 0xdf, 0x6f, ++ 0x2a, 0xd7, 0x18, 0xea, 0x57, 0xb6, 0x1d, 0x54, 0x58, 0x92, 0x51, 0xc4, ++ 0x50, 0xcf, 0xba, 0xf4, 0x71, 0xf2, 0x71, 0x0c, 0xfb, 0x5e, 0x5b, 0x67, ++ 0x02, 0xad, 0x9f, 0x2a, 0x41, 0xe0, 0x87, 0xf4, 0x5e, 0x05, 0xf4, 0x9c, ++ 0xbc, 0x9c, 0x9a, 0x66, 0x10, 0x3f, 0xdb, 0x2b, 0xa2, 0xbf, 0xd5, 0xa3, ++ 0xf6, 0xba, 0x93, 0xe9, 0xfb, 0xfb, 0xed, 0xcc, 0x8f, 0xed, 0xf1, 0xf0, ++ 0x72, 0x12, 0x2b, 0xf7, 0x0e, 0x54, 0xea, 0x41, 0xcf, 0x69, 0xef, 0x7b, ++ 0xed, 0x2c, 0xce, 0xd9, 0x53, 0xd4, 0xeb, 0x4e, 0xd2, 0xf9, 0xf7, 0x47, ++ 0xda, 0x45, 0x37, 0xec, 0x07, 0x77, 0x85, 0x58, 0x3e, 0x6a, 0x7f, 0x78, ++ 0xea, 0x50, 0x6e, 0xba, 0x48, 0xbc, 0xef, 0x2c, 0x2e, 0x38, 0x43, 0x74, ++ 0x66, 0x2c, 0x05, 0xff, 0xad, 0x41, 0xf4, 0x82, 0x6b, 0xb8, 0x60, 0xd9, ++ 0x2d, 0x6e, 0xd8, 0x77, 0xeb, 0x69, 0x1f, 0x79, 0xdd, 0x6c, 0xfa, 0x7e, ++ 0xe1, 0x21, 0x11, 0xcc, 0x67, 0xd2, 0xe3, 0x70, 0x8f, 0x03, 0xb8, 0x48, ++ 0xd0, 0x27, 0x0d, 0xce, 0xe7, 0xf9, 0x13, 0xf4, 0xef, 0x04, 0x09, 0xfe, ++ 0x72, 0x0a, 0xe4, 0x4d, 0xb4, 0x33, 0xfb, 0x7a, 0xc1, 0x1a, 0x93, 0x3d, ++ 0xec, 0xbc, 0x4b, 0xc1, 0xfc, 0xb2, 0xf5, 0xba, 0xb8, 0x96, 0x8e, 0xff, ++ 0xcb, 0x79, 0x3f, 0x65, 0x4d, 0xc6, 0xef, 0xe5, 0x64, 0x0d, 0xf2, 0x5f, ++ 0xb9, 0x49, 0x1e, 0xfc, 0xdc, 0x1f, 0x38, 0xac, 0xc9, 0x43, 0x0e, 0xc9, ++ 0x61, 0xfb, 0xdb, 0x84, 0xf9, 0xb1, 0x5c, 0xef, 0xce, 0x10, 0xb3, 0xaf, ++ 0x9b, 0x4d, 0xf1, 0xde, 0xd3, 0x21, 0x62, 0xde, 0xec, 0xd9, 0x76, 0x91, ++ 0xd4, 0xc3, 0x3c, 0x5b, 0x04, 0xdc, 0xe7, 0x24, 0xc1, 0x81, 0x28, 0x57, ++ 0xd5, 0xa4, 0x17, 0xf5, 0x9d, 0x86, 0x97, 0x6e, 0x90, 0x1b, 0x25, 0xbe, ++ 0x3e, 0xea, 0xde, 0xf9, 0x1f, 0xf9, 0xf7, 0x01, 0x7f, 0xbc, 0xf8, 0x87, ++ 0x71, 0x4f, 0xd0, 0x67, 0xf7, 0x8b, 0x1f, 0x8c, 0xd9, 0x03, 0xe5, 0x5d, ++ 0xef, 0x65, 0xfc, 0x81, 0xf4, 0xaf, 0x3f, 0x6d, 0xdf, 0xd7, 0xb8, 0x8f, ++ 0xd8, 0xb3, 0xcf, 0x8a, 0x71, 0xae, 0x9e, 0x7d, 0xaf, 0x65, 0xdc, 0x07, ++ 0xe5, 0x97, 0xac, 0x18, 0xe7, 0xea, 0x59, 0x6e, 0xc5, 0x7d, 0x94, 0xe0, ++ 0x3e, 0x57, 0x68, 0x34, 0x7c, 0x1f, 0xc6, 0xfc, 0x81, 0xba, 0xbd, 0x5f, ++ 0x8d, 0x63, 0x79, 0x92, 0x2b, 0x90, 0x4e, 0x7f, 0x96, 0x99, 0x3f, 0x72, ++ 0xb6, 0xfd, 0xbf, 0x3e, 0x84, 0xfc, 0x91, 0xb3, 0xed, 0x74, 0x56, 0x60, ++ 0x17, 0xec, 0x4b, 0x40, 0xb9, 0x09, 0xbc, 0x64, 0x47, 0xff, 0xbb, 0x67, ++ 0xef, 0x57, 0xf9, 0x7e, 0xe7, 0x3f, 0x6e, 0x3e, 0xd5, 0x0a, 0xf1, 0x23, ++ 0xff, 0xb9, 0xc8, 0xec, 0x1d, 0xc0, 0xaf, 0x49, 0x2c, 0x1e, 0x1c, 0xd8, ++ 0x33, 0xe9, 0x69, 0xc8, 0x6f, 0xae, 0x6a, 0xdd, 0xaf, 0x40, 0x9c, 0x7d, ++ 0xda, 0xcb, 0x7f, 0x19, 0x07, 0x7a, 0xb2, 0x67, 0x07, 0xb3, 0x77, 0xce, ++ 0xc8, 0x5d, 0x4f, 0xc1, 0x7e, 0x98, 0x55, 0xf9, 0x74, 0xb9, 0x4c, 0xf1, ++ 0x7c, 0x06, 0x84, 0x67, 0x08, 0x21, 0x4f, 0x2b, 0xe3, 0xa7, 0x05, 0xb3, ++ 0x63, 0xe1, 0x85, 0xe1, 0xa1, 0x87, 0xe2, 0x01, 0xe6, 0x45, 0xf1, 0x52, ++ 0x06, 0xfa, 0x3d, 0x1e, 0x3e, 0x32, 0x94, 0x7f, 0x56, 0x7c, 0x7c, 0x7a, ++ 0x3b, 0xd3, 0x63, 0xdf, 0xc5, 0x3c, 0xfb, 0x28, 0x5e, 0x04, 0x1f, 0x7b, ++ 0xef, 0x0a, 0xd9, 0x04, 0x9c, 0x3f, 0x7b, 0xbf, 0xef, 0xab, 0x71, 0xa0, ++ 0x67, 0x4e, 0x85, 0x97, 0xa1, 0x3d, 0x72, 0xa1, 0x79, 0x5f, 0xa1, 0xb0, ++ 0x7d, 0x96, 0xff, 0x39, 0xf3, 0x16, 0x22, 0x17, 0x33, 0xef, 0xb9, 0xff, ++ 0xb4, 0xf4, 0x66, 0xfc, 0xff, 0x11, 0xac, 0xaf, 0x03, 0xfb, 0xcb, 0x41, ++ 0x7f, 0x3e, 0xdf, 0x75, 0x0f, 0x96, 0x9f, 0x77, 0x79, 0x11, 0xde, 0x8b, ++ 0x94, 0xff, 0x9f, 0xfe, 0x4f, 0xa3, 0xfb, 0x0e, 0x4a, 0x77, 0xf7, 0x85, ++ 0xe9, 0xfe, 0xc4, 0x3f, 0xed, 0xbc, 0x2f, 0x44, 0xf7, 0x43, 0x9c, 0xee, ++ 0x2e, 0x0f, 0xec, 0x2f, 0xf7, 0xec, 0xfd, 0x0b, 0xc6, 0x4d, 0xb5, 0xf9, ++ 0x5f, 0x68, 0xde, 0x2f, 0xfd, 0x3f, 0x3a, 0x6f, 0xcd, 0x5e, 0x7f, 0xcd, ++ 0xa2, 0xbe, 0x93, 0x43, 0xeb, 0x1f, 0x22, 0x0d, 0xef, 0x8c, 0x11, 0x20, ++ 0x7f, 0xf1, 0xe0, 0x61, 0x38, 0x02, 0x56, 0x20, 0x90, 0xa2, 0x58, 0xf6, ++ 0xc8, 0x49, 0x85, 0xc5, 0x3f, 0x0a, 0x04, 0x96, 0x27, 0x48, 0x92, 0x04, ++ 0xee, 0xdf, 0x31, 0xbf, 0x68, 0x28, 0xb7, 0x13, 0x86, 0xde, 0x55, 0x82, ++ 0x76, 0xc6, 0xd0, 0xf4, 0xb5, 0x68, 0x1f, 0x10, 0x49, 0x5d, 0x0f, 0xfb, ++ 0x71, 0xaf, 0x65, 0xcc, 0xf7, 0xb2, 0x7c, 0xb0, 0xf1, 0x78, 0x0e, 0xe5, ++ 0x35, 0xcf, 0x15, 0xbc, 0x6c, 0xf4, 0x0f, 0x9f, 0x10, 0x88, 0x0f, 0xf2, ++ 0x86, 0x87, 0x66, 0xfc, 0xb0, 0x03, 0xec, 0xd5, 0xf4, 0x74, 0x11, 0xed, ++ 0x59, 0xfa, 0x44, 0x3b, 0xf6, 0x15, 0xf7, 0x4c, 0xf6, 0xbe, 0x52, 0x31, ++ 0xf8, 0x45, 0x57, 0x11, 0x5d, 0x99, 0xce, 0xab, 0x30, 0xc5, 0xe8, 0xff, ++ 0x4c, 0xe7, 0xfd, 0xcd, 0x20, 0x23, 0xde, 0xc9, 0xa1, 0xf0, 0xcf, 0xb0, ++ 0xc9, 0x9e, 0x10, 0x45, 0xd1, 0x55, 0x53, 0xfd, 0x12, 0xcc, 0xe7, 0xaa, ++ 0xc1, 0x02, 0x69, 0xd0, 0xed, 0x07, 0x4d, 0x37, 0xf9, 0x49, 0xaf, 0x82, ++ 0x5f, 0xab, 0x8b, 0x97, 0xfd, 0xad, 0xf8, 0x4b, 0xb7, 0x32, 0x3f, 0xb2, ++ 0x40, 0x18, 0xb1, 0xbe, 0x08, 0xf0, 0x37, 0x4c, 0xc4, 0x78, 0xe0, 0x05, ++ 0xf1, 0x47, 0x58, 0xfe, 0xd7, 0x6b, 0x9e, 0x1c, 0x96, 0xd7, 0x2a, 0x79, ++ 0x19, 0xfe, 0x92, 0xab, 0xbc, 0x18, 0x4f, 0xe5, 0x7e, 0x33, 0x84, 0x05, ++ 0xc0, 0x5e, 0x91, 0x9c, 0xf5, 0x9d, 0x20, 0xb7, 0x12, 0xa1, 0x7e, 0x2f, ++ 0x83, 0x1f, 0xfd, 0x65, 0xcd, 0xef, 0x8d, 0x87, 0x67, 0xc2, 0xfd, 0x68, ++ 0x89, 0x0f, 0xa9, 0xe1, 0x5d, 0x4a, 0x17, 0x31, 0x5f, 0x55, 0xd7, 0x1f, ++ 0xe2, 0x43, 0xa3, 0xc7, 0xdf, 0x4a, 0x07, 0x8d, 0x7e, 0x7f, 0x2f, 0x3d, ++ 0xce, 0x98, 0xe8, 0x91, 0xfe, 0xb9, 0x47, 0x02, 0xf9, 0x9c, 0xc6, 0xed, ++ 0xff, 0xe9, 0x9f, 0x77, 0x8a, 0x58, 0x4e, 0xf7, 0x4a, 0xb8, 0x1f, 0xc5, ++ 0xed, 0xff, 0xa9, 0xce, 0x24, 0x09, 0xec, 0xff, 0x2b, 0xa4, 0xc3, 0x22, ++ 0xc8, 0x65, 0xa9, 0xad, 0xed, 0x6a, 0x88, 0xd3, 0xdb, 0xbc, 0x02, 0xf2, ++ 0xf5, 0x25, 0xdd, 0x16, 0xf4, 0x6f, 0x6c, 0x79, 0x02, 0xe2, 0x3d, 0xab, ++ 0x51, 0xc2, 0xf2, 0x61, 0x8b, 0x67, 0x02, 0x18, 0xda, 0xd7, 0x7e, 0x6f, ++ 0xd7, 0xa9, 0x7b, 0x09, 0xc4, 0x87, 0x7d, 0x0a, 0x1a, 0xde, 0xa4, 0x88, ++ 0xc5, 0xe7, 0xff, 0xfc, 0xed, 0xb7, 0x53, 0xb4, 0xf3, 0x1a, 0xf8, 0x9d, ++ 0x90, 0x6b, 0xa8, 0xff, 0xb5, 0xa0, 0x89, 0x44, 0x1c, 0x14, 0x4f, 0x0b, ++ 0x25, 0x12, 0x4c, 0x4c, 0x86, 0xf8, 0xae, 0x40, 0x3e, 0x32, 0xc4, 0x77, ++ 0x8d, 0x65, 0xf8, 0xfb, 0x7e, 0x6a, 0xb4, 0x9f, 0x0b, 0xd5, 0x8f, 0xa7, ++ 0x47, 0xfe, 0xd1, 0xcf, 0x5d, 0x54, 0x6f, 0x7d, 0x44, 0x99, 0x63, 0x37, ++ 0x3c, 0x71, 0x5f, 0x85, 0xb2, 0x84, 0xce, 0x3f, 0xfe, 0x6e, 0x3b, 0xc3, ++ 0x57, 0xe0, 0x75, 0x12, 0x1a, 0x81, 0x71, 0x05, 0x9f, 0x58, 0xa4, 0xdb, ++ 0x37, 0x7b, 0xd0, 0xca, 0xf4, 0xc7, 0xae, 0x3f, 0xee, 0xc8, 0x85, 0xb8, ++ 0xd8, 0xd4, 0x9e, 0xec, 0x44, 0xa6, 0x4f, 0x47, 0xa1, 0x5f, 0x10, 0xe0, ++ 0x7e, 0xc1, 0x59, 0xa2, 0x26, 0x42, 0xfe, 0xc1, 0xd9, 0xf6, 0x91, 0x89, ++ 0xb8, 0x2f, 0xd8, 0x21, 0xba, 0xfc, 0x31, 0xe2, 0x32, 0x5b, 0xb9, 0xff, ++ 0xfc, 0xaf, 0x90, 0x4f, 0x41, 0x9f, 0x3d, 0x9b, 0x48, 0x03, 0x9c, 0xc3, ++ 0xe8, 0x21, 0xbd, 0x18, 0x8f, 0x0d, 0x6e, 0xb2, 0xc5, 0xdc, 0xdf, 0xbd, ++ 0xc7, 0xaa, 0xc5, 0x9b, 0x38, 0xdd, 0xe8, 0x9f, 0xa8, 0x9d, 0x37, 0x52, ++ 0x31, 0x5f, 0x24, 0x98, 0xa8, 0xa7, 0x5b, 0xf7, 0xac, 0x4f, 0xa4, 0x71, ++ 0xfd, 0xe9, 0x00, 0x7f, 0x1f, 0xe9, 0xf6, 0x4b, 0xfe, 0x5e, 0xfc, 0x82, ++ 0xbf, 0x0e, 0xf8, 0xdd, 0x6a, 0xef, 0x2a, 0x8c, 0x75, 0x1e, 0x6c, 0x25, ++ 0xc7, 0xdf, 0xb5, 0x07, 0xbe, 0xc6, 0x38, 0xe6, 0x65, 0xed, 0xcd, 0x16, ++ 0xe0, 0xdf, 0xcb, 0x36, 0x59, 0x0c, 0xfb, 0x8d, 0x41, 0x2b, 0xf7, 0xbb, ++ 0xc6, 0x93, 0xf1, 0x00, 0xd7, 0xb5, 0x07, 0xec, 0xae, 0x3c, 0xa0, 0x4b, ++ 0x87, 0xe8, 0x85, 0xfc, 0xc1, 0x40, 0xfb, 0xa7, 0x8a, 0x3f, 0xc6, 0xbe, ++ 0x95, 0x19, 0x9f, 0xd0, 0x3f, 0xc4, 0xc5, 0xf7, 0x59, 0x59, 0x9c, 0x7f, ++ 0x8f, 0x1c, 0x9e, 0x0f, 0x78, 0xdd, 0x73, 0xda, 0x86, 0xf9, 0x39, 0xbb, ++ 0x95, 0x86, 0x8a, 0x58, 0x70, 0x5e, 0x62, 0x67, 0x7a, 0x6e, 0x21, 0x09, ++ 0xdf, 0x39, 0x2e, 0xf3, 0x9f, 0x0f, 0xbf, 0x53, 0x7b, 0x9c, 0x91, 0x02, ++ 0xf0, 0x33, 0x37, 0x11, 0x1e, 0xc7, 0x30, 0xf3, 0x1f, 0x41, 0x3e, 0x3e, ++ 0xbb, 0x85, 0xe0, 0xf9, 0x50, 0xf0, 0x4b, 0x41, 0x2f, 0x9c, 0x6d, 0x61, ++ 0xe7, 0x80, 0x29, 0x4a, 0xd6, 0x82, 0x3f, 0x4d, 0xe5, 0xfd, 0x07, 0xfa, ++ 0xb8, 0xcc, 0x25, 0x6d, 0xdb, 0xff, 0x15, 0xec, 0x80, 0xea, 0x76, 0xc1, ++ 0x03, 0xa9, 0xb3, 0xd5, 0x52, 0x97, 0x02, 0xf1, 0xd6, 0x40, 0x5b, 0x92, ++ 0x08, 0xeb, 0x6e, 0x8e, 0xaa, 0xe5, 0x55, 0x7a, 0xc6, 0xde, 0xa4, 0x93, ++ 0x8b, 0x7d, 0x56, 0x96, 0x6f, 0x7c, 0x70, 0xf2, 0x9e, 0x5b, 0x61, 0xdc, ++ 0xcf, 0xba, 0x15, 0x02, 0xf6, 0x88, 0xef, 0x95, 0x5e, 0x37, 0xac, 0xdb, ++ 0x9f, 0xb5, 0xe7, 0x26, 0xc6, 0xca, 0x9b, 0xd7, 0x9e, 0xbf, 0xae, 0x25, ++ 0x57, 0x4f, 0x97, 0xa0, 0x1f, 0x82, 0x78, 0x37, 0xf3, 0x43, 0x76, 0x8b, ++ 0xc3, 0x50, 0xfe, 0x9e, 0xe8, 0x1f, 0x02, 0xf2, 0x75, 0xad, 0xb5, 0xeb, ++ 0x2e, 0x6f, 0x0c, 0xfa, 0xf9, 0x6d, 0x8c, 0xcf, 0x2e, 0x5a, 0xbf, 0x85, ++ 0xfe, 0x3f, 0xd3, 0x6f, 0xef, 0x68, 0xfa, 0xcd, 0x2f, 0x16, 0xe9, 0xe4, ++ 0x28, 0xcb, 0xd6, 0x4f, 0xbf, 0x0d, 0x8a, 0xa5, 0xdf, 0x96, 0x08, 0xea, ++ 0x20, 0xc0, 0xfb, 0x92, 0xbd, 0x23, 0x07, 0x01, 0x5d, 0x97, 0x1c, 0x92, ++ 0x07, 0xc6, 0xd2, 0x6f, 0xdb, 0x6a, 0xd9, 0x7e, 0xde, 0x0b, 0x3c, 0x1f, ++ 0xb6, 0xa7, 0x95, 0xea, 0xb7, 0xcb, 0x75, 0xfa, 0xad, 0xd5, 0x86, 0x79, ++ 0x71, 0xe6, 0x76, 0xc9, 0x36, 0x0b, 0x5f, 0x17, 0x2f, 0xa0, 0xdf, 0x42, ++ 0xff, 0x3d, 0xf2, 0xb7, 0x0d, 0xf4, 0x5b, 0x8c, 0xf9, 0x8e, 0xb6, 0x31, ++ 0xbd, 0xa1, 0xe9, 0xb7, 0x71, 0xed, 0x47, 0x50, 0xbf, 0x8d, 0x6b, 0xb5, ++ 0x18, 0xf2, 0x46, 0xd3, 0x6d, 0x17, 0xd2, 0x6f, 0xc2, 0xc0, 0x9b, 0xc0, ++ 0x1e, 0xee, 0x90, 0xbd, 0x09, 0x31, 0xf8, 0x67, 0x1b, 0xb7, 0xbf, 0x5f, ++ 0xe0, 0x79, 0x78, 0x30, 0x0e, 0xe8, 0xb9, 0x5b, 0x6d, 0x6c, 0x7f, 0xf3, ++ 0x62, 0xf5, 0x5c, 0xb6, 0x9d, 0xd1, 0xfb, 0x82, 0x7a, 0xee, 0xbf, 0x09, ++ 0xcf, 0x9a, 0x9e, 0x5b, 0xb2, 0x53, 0x3b, 0xe7, 0x68, 0xe6, 0x43, 0xa6, ++ 0xe7, 0x96, 0xec, 0xa6, 0x7a, 0x4e, 0x00, 0x7e, 0x64, 0x7a, 0x6e, 0xc9, ++ 0x5e, 0x76, 0x8f, 0x83, 0x59, 0xbf, 0x65, 0xf5, 0xd3, 0x6f, 0x04, 0xeb, ++ 0x57, 0x47, 0x58, 0xfb, 0x40, 0x5b, 0xe6, 0x86, 0xb9, 0xb4, 0xbf, 0xf1, ++ 0x3e, 0xd9, 0x6b, 0xa3, 0xf5, 0xc7, 0x47, 0xf5, 0xdd, 0x04, 0xbd, 0xbe, ++ 0xbb, 0xd5, 0xc6, 0xee, 0x5d, 0xe8, 0xa7, 0xef, 0x3a, 0x2e, 0x4e, 0xdf, ++ 0xed, 0xe4, 0xfa, 0x8e, 0xea, 0xb1, 0x11, 0xa0, 0x5f, 0xcd, 0xfc, 0xe1, ++ 0x6d, 0x37, 0xe6, 0x1d, 0xef, 0x99, 0x74, 0xbc, 0xe5, 0xd7, 0x20, 0x2f, ++ 0x6f, 0x88, 0xb8, 0x6f, 0x78, 0x98, 0x9f, 0x4b, 0x7b, 0x73, 0xd2, 0xf1, ++ 0x3c, 0xe0, 0xaf, 0x16, 0x1b, 0xd3, 0xbf, 0x75, 0x9c, 0xff, 0xce, 0xd4, ++ 0x06, 0xb1, 0xff, 0x69, 0xaf, 0xb0, 0xf9, 0x55, 0x39, 0x59, 0x3e, 0x72, ++ 0x75, 0x2b, 0xb3, 0x0f, 0xab, 0x5b, 0x84, 0x90, 0x4a, 0xff, 0x59, 0x38, ++ 0xf9, 0x6b, 0x05, 0xe0, 0x5f, 0xb4, 0x57, 0x20, 0x83, 0x68, 0xf9, 0x7a, ++ 0x2b, 0xab, 0x4f, 0x9e, 0xd5, 0xf6, 0xbd, 0xc8, 0xac, 0x1c, 0x1d, 0x3f, ++ 0x2c, 0x98, 0x58, 0x81, 0x71, 0xfb, 0x05, 0x12, 0xb1, 0x41, 0x5c, 0xbe, ++ 0xc2, 0x59, 0xf8, 0x09, 0xd8, 0xbf, 0x15, 0x13, 0x59, 0x1c, 0xbf, 0x82, ++ 0xbf, 0x5f, 0x74, 0xa8, 0xab, 0x1e, 0xe2, 0xd9, 0x8b, 0x1e, 0x13, 0x70, ++ 0xdf, 0x93, 0xf0, 0x7c, 0x00, 0x2d, 0xbf, 0xb1, 0xb4, 0x7d, 0x19, 0xc6, ++ 0x6b, 0xcd, 0x79, 0x01, 0x9a, 0x3e, 0x5f, 0x14, 0x32, 0xbe, 0xaf, 0x30, ++ 0xe5, 0x33, 0x36, 0xf3, 0x79, 0x5e, 0x2f, 0x76, 0x21, 0x5e, 0xc8, 0x5b, ++ 0x62, 0xcc, 0xbc, 0x84, 0x66, 0x33, 0x3e, 0x3a, 0x38, 0x3e, 0x36, 0x89, ++ 0xb8, 0x6e, 0xf6, 0xe1, 0x83, 0xe2, 0x47, 0xcd, 0xec, 0x8f, 0x0f, 0x4a, ++ 0xd1, 0x59, 0x39, 0xa9, 0xd1, 0xf9, 0x2f, 0x7a, 0x83, 0xce, 0x2b, 0x2f, ++ 0x3a, 0x2f, 0x0d, 0x1f, 0xe6, 0xf9, 0x69, 0x71, 0xe7, 0x0a, 0xde, 0x2e, ++ 0xde, 0x7c, 0x35, 0xfc, 0xf5, 0x9b, 0xaf, 0x86, 0x4f, 0xd3, 0xbc, 0x9f, ++ 0x06, 0xbd, 0x01, 0x0a, 0x21, 0x87, 0xe4, 0x42, 0x5e, 0x0c, 0xe5, 0x03, ++ 0xd4, 0x1b, 0xc1, 0xdf, 0x8a, 0x78, 0x7e, 0xbf, 0x68, 0xea, 0xe8, 0x41, ++ 0x7a, 0x3d, 0xbc, 0x95, 0xeb, 0xf3, 0xdc, 0x86, 0xa9, 0xd3, 0x06, 0x13, ++ 0xc0, 0x17, 0xa9, 0x01, 0xbe, 0x29, 0x69, 0x5c, 0xfc, 0xea, 0x60, 0x3a, ++ 0xef, 0x09, 0xef, 0xab, 0xe3, 0x61, 0x79, 0xfc, 0xde, 0x64, 0xab, 0x1f, ++ 0xf6, 0x47, 0xb7, 0xda, 0x7b, 0x51, 0xaf, 0x69, 0x7c, 0xf5, 0x0d, 0xe7, ++ 0xab, 0x77, 0x39, 0x1e, 0xf7, 0x0c, 0xa9, 0xc1, 0x73, 0xaa, 0x81, 0x36, ++ 0xc1, 0x03, 0x76, 0x45, 0x20, 0x62, 0x47, 0xfc, 0x05, 0x28, 0xfe, 0xe0, ++ 0xfc, 0x4a, 0x80, 0x9f, 0x5f, 0x0c, 0x50, 0xfe, 0x02, 0x79, 0x3a, 0xf8, ++ 0xd8, 0x97, 0x0c, 0x5f, 0x7b, 0x05, 0x15, 0xe2, 0xe3, 0x85, 0xda, 0xfa, ++ 0x03, 0xf8, 0xa7, 0xf5, 0x73, 0xdb, 0x19, 0xfe, 0x03, 0x21, 0x01, 0xf1, ++ 0x9f, 0x47, 0x7a, 0x71, 0x7f, 0xa4, 0xba, 0x51, 0xf0, 0x46, 0x68, 0xfd, ++ 0xea, 0xb6, 0xc5, 0x98, 0xf7, 0xa0, 0xe9, 0x5b, 0xfa, 0xe7, 0xd4, 0xd3, ++ 0x43, 0xc7, 0x8f, 0x52, 0x2c, 0x7e, 0xc4, 0x4a, 0xba, 0xf5, 0xaf, 0x82, ++ 0xd7, 0xbb, 0xd6, 0xda, 0xf0, 0x2e, 0xf0, 0xe7, 0xb5, 0xcf, 0xca, 0xa4, ++ 0x59, 0xc7, 0x9f, 0x59, 0xf4, 0xbf, 0x6f, 0x63, 0xd0, 0x49, 0xc3, 0xe7, ++ 0x85, 0xf8, 0xf2, 0x1c, 0xc7, 0xd3, 0x36, 0xc0, 0xa3, 0x13, 0xf0, 0xd5, ++ 0xcb, 0xec, 0xa7, 0xc8, 0xd7, 0x78, 0x8e, 0x46, 0xfb, 0x1e, 0x90, 0x82, ++ 0x06, 0x3c, 0x4e, 0x7b, 0xfc, 0xdc, 0x79, 0xf1, 0x34, 0x41, 0xc3, 0x13, ++ 0xf0, 0x29, 0xe8, 0xa9, 0xf6, 0x62, 0x11, 0xca, 0x25, 0x6d, 0x02, 0x19, ++ 0x90, 0xd9, 0x7f, 0x9e, 0xb0, 0x3f, 0xa9, 0x97, 0xdb, 0x45, 0x7b, 0x8f, ++ 0xb0, 0xfe, 0x9f, 0x14, 0xf0, 0xde, 0x12, 0x33, 0xdf, 0x6a, 0xf3, 0xee, ++ 0xc7, 0xb7, 0x71, 0xf8, 0x15, 0xce, 0xa5, 0x81, 0x5f, 0x74, 0xb1, 0x7c, ++ 0xfb, 0x8d, 0x89, 0x6f, 0xdf, 0xb4, 0xf7, 0xbe, 0x9e, 0x0b, 0x7c, 0xbb, ++ 0x57, 0x60, 0xf1, 0x83, 0xf6, 0x24, 0xc3, 0xfe, 0xe2, 0x10, 0x3b, 0x5b, ++ 0xff, 0xb7, 0xda, 0x29, 0x7f, 0xc3, 0xbe, 0xd6, 0x21, 0xd9, 0xbb, 0x51, ++ 0xed, 0x2f, 0xdf, 0x09, 0x7c, 0xfd, 0x02, 0xbb, 0x5f, 0x7f, 0x2e, 0xe9, ++ 0x52, 0x98, 0x08, 0xe4, 0x3d, 0x6e, 0xb1, 0x61, 0x1e, 0x19, 0xc2, 0x31, ++ 0x82, 0xd9, 0x95, 0x7a, 0xbd, 0xba, 0xcd, 0x4e, 0x06, 0xde, 0x94, 0x17, ++ 0xbf, 0xff, 0xc1, 0xbc, 0xff, 0x78, 0x76, 0x8d, 0x56, 0x1e, 0x0b, 0xe3, ++ 0x41, 0xbe, 0x57, 0x1b, 0x1d, 0x2f, 0x2b, 0x3a, 0x9e, 0x59, 0xaf, 0x6b, ++ 0x7e, 0xfe, 0x85, 0xe6, 0x35, 0xe6, 0xef, 0x9c, 0x57, 0x5f, 0x1e, 0x26, ++ 0xe9, 0xc4, 0x7d, 0xa7, 0x4c, 0xc9, 0xff, 0xb0, 0x55, 0x97, 0x07, 0x77, ++ 0x33, 0xcf, 0x33, 0xa2, 0x10, 0xa0, 0x7d, 0xa5, 0xab, 0x97, 0x6d, 0x3b, ++ 0x4f, 0x3d, 0x92, 0xe6, 0xc1, 0xf3, 0x4f, 0x77, 0x7a, 0x34, 0x3e, 0x63, ++ 0xf9, 0xee, 0x45, 0x3c, 0x8f, 0x7d, 0x86, 0x38, 0xe5, 0x3d, 0x58, 0x3f, ++ 0x3f, 0xf3, 0xb1, 0x7d, 0xbe, 0x3c, 0x0b, 0xf9, 0xdd, 0x14, 0xd0, 0xcf, ++ 0x05, 0x32, 0x9e, 0xe3, 0xfb, 0xec, 0x75, 0x19, 0xe3, 0xb5, 0x9f, 0x4d, ++ 0x67, 0x79, 0x9c, 0xd7, 0xbd, 0x71, 0x50, 0x82, 0x38, 0xcd, 0x75, 0xa0, ++ 0x9c, 0x28, 0x3e, 0xae, 0x9b, 0x20, 0xa0, 0xbf, 0x02, 0xc7, 0xb0, 0x60, ++ 0xdf, 0x6c, 0x17, 0xb5, 0x6f, 0x7c, 0x63, 0x70, 0x3e, 0xb9, 0x70, 0x8e, ++ 0x2b, 0x67, 0x53, 0xc3, 0x34, 0x38, 0x7f, 0x3c, 0x7e, 0x4b, 0xa8, 0x0e, ++ 0x9e, 0xde, 0x69, 0xbd, 0x29, 0x6f, 0x02, 0x1e, 0xa7, 0x8a, 0x04, 0xf0, ++ 0xd8, 0xe9, 0x1b, 0x30, 0x0d, 0xee, 0x4f, 0xba, 0xf3, 0x4f, 0x04, 0xef, ++ 0x0f, 0xa1, 0xeb, 0x2c, 0xb6, 0x1f, 0xdf, 0x41, 0x06, 0x42, 0xbd, 0xc9, ++ 0xbe, 0x81, 0xe8, 0x0e, 0x4c, 0x6a, 0x5d, 0x3f, 0x0d, 0xe2, 0xa3, 0xd7, ++ 0x1f, 0x74, 0x3a, 0xe1, 0x7e, 0x96, 0xac, 0x26, 0x0b, 0xf5, 0x19, 0xa2, ++ 0xf8, 0x9b, 0x4c, 0x42, 0x75, 0xb0, 0xdf, 0x3e, 0xe9, 0xa8, 0xef, 0x46, ++ 0x80, 0xb7, 0x8c, 0xda, 0x0b, 0x10, 0x77, 0x2e, 0x6b, 0x6f, 0xae, 0x73, ++ 0x43, 0xb9, 0x49, 0xf0, 0xaa, 0xb4, 0xff, 0x40, 0xd0, 0x5f, 0xe8, 0xa6, ++ 0xf3, 0xd8, 0xd6, 0xf8, 0x69, 0xe1, 0x77, 0x40, 0x1e, 0x69, 0x3d, 0xe8, ++ 0x26, 0xd0, 0xc4, 0xea, 0x05, 0x36, 0xc1, 0xc5, 0x43, 0xf0, 0x7e, 0x1d, ++ 0xe6, 0xd9, 0x94, 0x6c, 0x12, 0xf0, 0xe0, 0xd7, 0xb6, 0x90, 0x40, 0x6c, ++ 0xac, 0xdf, 0x90, 0x8d, 0xf6, 0xbb, 0xad, 0x89, 0xb6, 0xcf, 0x83, 0x75, ++ 0x82, 0xb6, 0x87, 0x7e, 0x37, 0x7d, 0xfa, 0xce, 0x8d, 0x20, 0xef, 0xaf, ++ 0x8b, 0xac, 0x7d, 0x0b, 0xdb, 0xa7, 0x2e, 0xa1, 0xed, 0x54, 0xe0, 0xdb, ++ 0x4d, 0x8b, 0xb1, 0xbf, 0x45, 0x4d, 0x02, 0x49, 0xa3, 0xfd, 0x95, 0xb5, ++ 0xb0, 0x75, 0xa0, 0xec, 0x75, 0xd9, 0x0b, 0xdf, 0x5b, 0xf7, 0x3f, 0x86, ++ 0xeb, 0xd8, 0x2c, 0x3a, 0xde, 0xe0, 0x4c, 0xd0, 0xfb, 0x91, 0xe9, 0x50, ++ 0x26, 0xb9, 0x82, 0x07, 0xcf, 0xa1, 0x54, 0x8e, 0x41, 0xba, 0xf5, 0x70, ++ 0x39, 0x27, 0x53, 0x46, 0x33, 0xfd, 0x21, 0xf0, 0x32, 0xf7, 0x1b, 0x34, ++ 0xbb, 0xe9, 0x5d, 0x3b, 0xcb, 0xf7, 0x2d, 0xf1, 0x2e, 0x53, 0x06, 0xd0, ++ 0x7e, 0xde, 0x9c, 0x38, 0x30, 0x13, 0xd2, 0x02, 0x02, 0x6d, 0x9f, 0xe2, ++ 0xfe, 0xf3, 0x51, 0x8a, 0x67, 0x3f, 0xed, 0xf2, 0x30, 0xcf, 0xdb, 0x38, ++ 0x38, 0xf1, 0x63, 0xa5, 0x4b, 0xb7, 0x0e, 0x7d, 0x66, 0x67, 0xf7, 0x5b, ++ 0x2d, 0x68, 0x9b, 0x8a, 0xf9, 0x0c, 0x0b, 0x49, 0x11, 0xe6, 0x33, 0x5c, ++ 0x3b, 0x89, 0xd9, 0x6b, 0x6f, 0x5d, 0x61, 0x0f, 0xc1, 0x15, 0x07, 0x6f, ++ 0xc9, 0xbd, 0xe9, 0xf0, 0xfe, 0xe0, 0x15, 0x56, 0xb4, 0x7f, 0xcf, 0x6c, ++ 0x93, 0x91, 0x8f, 0xce, 0x0c, 0xeb, 0xc2, 0xf8, 0xf4, 0xf1, 0x26, 0x19, ++ 0xcf, 0x0d, 0xd7, 0x35, 0xb1, 0xfb, 0xb9, 0x8e, 0xb7, 0xb0, 0x75, 0x5c, ++ 0x7c, 0x92, 0xed, 0xeb, 0x97, 0xba, 0x14, 0x2c, 0x1f, 0x6c, 0xba, 0xb1, ++ 0x10, 0xd6, 0xb7, 0xe3, 0x9b, 0xd8, 0x79, 0xc7, 0x69, 0x4f, 0xce, 0x50, ++ 0xa0, 0x5c, 0xda, 0x2c, 0x78, 0xd9, 0xfd, 0x45, 0x4c, 0x3f, 0x6a, 0xfe, ++ 0x5b, 0x89, 0x87, 0xe5, 0x23, 0x68, 0xfa, 0xaf, 0x8a, 0xcf, 0xbb, 0x5f, ++ 0xde, 0xa2, 0x49, 0xdf, 0x55, 0x69, 0xeb, 0x8d, 0x49, 0xdf, 0x55, 0xc1, ++ 0xbe, 0xb2, 0x1b, 0x9e, 0xc6, 0xf7, 0x01, 0xe2, 0x64, 0x7a, 0x10, 0xec, ++ 0x7e, 0xa0, 0x7b, 0xe4, 0x6b, 0xe4, 0xdf, 0xea, 0xd7, 0x65, 0x02, 0x76, ++ 0xbf, 0xf0, 0x71, 0x77, 0x21, 0xe6, 0x63, 0xed, 0x15, 0x30, 0x9e, 0x3f, ++ 0xa9, 0x5d, 0xf0, 0xc1, 0xbe, 0x7e, 0xd9, 0xfb, 0xd6, 0x10, 0xda, 0xab, ++ 0xa1, 0xe2, 0x3b, 0x7e, 0x02, 0x7a, 0xfc, 0x03, 0x2b, 0x11, 0x54, 0xc8, ++ 0x6b, 0xa7, 0x78, 0xa7, 0xfa, 0x61, 0xa2, 0xb5, 0xf7, 0x8f, 0xbf, 0xa0, ++ 0xef, 0x3f, 0x39, 0x6c, 0x83, 0x4c, 0x18, 0xca, 0x27, 0xc5, 0x88, 0x67, ++ 0x2d, 0xff, 0x33, 0x6f, 0x33, 0xcb, 0x63, 0xc9, 0x3b, 0xbc, 0x3e, 0x15, ++ 0xce, 0x5b, 0x92, 0xe9, 0x03, 0x50, 0xdf, 0x96, 0x36, 0x8a, 0xc4, 0xaf, ++ 0xd3, 0x1b, 0x9f, 0x08, 0xbe, 0x1b, 0x7f, 0xcc, 0xf4, 0x32, 0xde, 0x4f, ++ 0xa1, 0xd1, 0x2f, 0x4f, 0x69, 0x28, 0x81, 0x75, 0x6c, 0xa4, 0x83, 0xe9, ++ 0x25, 0x75, 0xb3, 0x0c, 0x39, 0x22, 0xe4, 0x10, 0x8f, 0x93, 0x50, 0x7b, ++ 0x1a, 0xcf, 0xdf, 0x2e, 0xda, 0xbd, 0x2e, 0x55, 0xa1, 0xf5, 0xea, 0x79, ++ 0xfe, 0xc7, 0xa2, 0xbd, 0xeb, 0x52, 0x45, 0xfa, 0xbe, 0x0e, 0xd6, 0x2f, ++ 0x5a, 0x7f, 0x91, 0xc2, 0xfa, 0x5f, 0xb4, 0x4f, 0xf0, 0x34, 0xeb, 0xfa, ++ 0xd7, 0xda, 0x6b, 0xfd, 0x69, 0xfd, 0x28, 0xbb, 0x8d, 0xfd, 0x8c, 0xdc, ++ 0xcb, 0xcb, 0x17, 0xd9, 0x8f, 0x06, 0x87, 0x36, 0x7e, 0x3c, 0x7b, 0x7c, ++ 0xe2, 0xbf, 0x9f, 0x5b, 0x0f, 0xf7, 0xc5, 0x4c, 0x7c, 0x4b, 0xc4, 0xa4, ++ 0xe3, 0x89, 0x1f, 0xcf, 0x1a, 0xa9, 0xdf, 0xef, 0xd0, 0x9e, 0x5a, 0xfc, ++ 0x35, 0xff, 0x1d, 0x0b, 0xf1, 0xe9, 0xf0, 0x36, 0xf1, 0x8f, 0x0e, 0xe2, ++ 0xd3, 0xf1, 0x45, 0xeb, 0x04, 0x2a, 0xdf, 0x94, 0x6e, 0xd7, 0xb4, 0x09, ++ 0x21, 0x00, 0xa5, 0x75, 0xc2, 0x11, 0xa5, 0x2a, 0x0f, 0xcb, 0x1e, 0x90, ++ 0xe7, 0x6a, 0x1e, 0xa7, 0xad, 0x9e, 0xce, 0xf6, 0xad, 0x5a, 0x73, 0x0e, ++ 0xaf, 0x00, 0xf9, 0x9e, 0x95, 0x27, 0x20, 0x1f, 0x90, 0xa0, 0x5f, 0x19, ++ 0x90, 0x82, 0x76, 0x90, 0x0a, 0xf1, 0xf1, 0xd2, 0x3c, 0xd6, 0xbe, 0x94, ++ 0xb6, 0x07, 0xb9, 0x6b, 0x7d, 0x8c, 0xc9, 0x21, 0xd5, 0x07, 0x2a, 0xe8, ++ 0x8b, 0xea, 0xa6, 0x75, 0x85, 0x58, 0x7f, 0x93, 0xa0, 0x42, 0xff, 0xad, ++ 0xcd, 0xc5, 0xb8, 0xde, 0x97, 0x4d, 0x14, 0x09, 0x7e, 0xdf, 0x74, 0x04, ++ 0xed, 0x8f, 0xb2, 0xb6, 0x23, 0x29, 0x20, 0xaf, 0x54, 0x3e, 0xd7, 0xc3, ++ 0xfa, 0x5b, 0x3d, 0xc5, 0x8a, 0xf7, 0x79, 0x69, 0x72, 0xa7, 0xc9, 0xf1, ++ 0x5b, 0x32, 0xbf, 0xaf, 0xc9, 0xe6, 0x19, 0x0b, 0x79, 0xfd, 0xf7, 0x01, ++ 0x50, 0x31, 0xe4, 0x57, 0x7c, 0x9d, 0x30, 0x3f, 0xb5, 0x45, 0x46, 0x39, ++ 0x0b, 0x4c, 0x64, 0x72, 0xf9, 0xd6, 0x36, 0x11, 0xe5, 0xf9, 0xe0, 0x15, ++ 0xb7, 0xa0, 0x1c, 0x9e, 0xd9, 0x2c, 0xc4, 0x91, 0xe3, 0x69, 0x0a, 0x9c, ++ 0x4b, 0x3e, 0x1e, 0x62, 0xdf, 0xfb, 0xe4, 0x78, 0xab, 0xc0, 0xe5, 0x98, ++ 0xe9, 0x87, 0xe3, 0x4e, 0x26, 0xd7, 0xd3, 0xe0, 0x3b, 0xc8, 0xf1, 0x4e, ++ 0x81, 0xfb, 0x83, 0xcc, 0x1e, 0x34, 0xcb, 0xb1, 0x26, 0x97, 0x17, 0x92, ++ 0xdf, 0x8a, 0x2d, 0x26, 0x79, 0x8e, 0x23, 0xb7, 0x9d, 0x52, 0xd7, 0x4d, ++ 0x30, 0xee, 0x9d, 0x57, 0xd8, 0x11, 0xee, 0x69, 0xdf, 0xdf, 0xfd, 0xee, ++ 0x9d, 0xa8, 0x7f, 0x64, 0xcc, 0xfb, 0x98, 0xf6, 0xfd, 0x7b, 0x53, 0x41, ++ 0xdf, 0x95, 0x48, 0x2c, 0x5f, 0x49, 0xc3, 0x63, 0x95, 0xc4, 0xf2, 0xd9, ++ 0xfa, 0xc1, 0xb1, 0x7e, 0x99, 0x32, 0xf8, 0xa2, 0xe0, 0x31, 0xc2, 0xf1, ++ 0x84, 0xdd, 0x15, 0xd5, 0x1f, 0x22, 0xf0, 0x39, 0xbb, 0x87, 0x2b, 0xb8, ++ 0x49, 0x46, 0x3e, 0x37, 0xcb, 0xe1, 0xdf, 0x2b, 0x3f, 0xff, 0x28, 0x79, ++ 0x3e, 0xc4, 0xf9, 0x47, 0x83, 0x47, 0xdc, 0xcb, 0xda, 0x43, 0xfe, 0x58, ++ 0x84, 0xe2, 0xe9, 0xb5, 0x96, 0xa7, 0x31, 0x4f, 0xf5, 0xf4, 0x73, 0x47, ++ 0xae, 0x05, 0x3c, 0x57, 0xec, 0xa1, 0x7c, 0x4b, 0xe7, 0x7b, 0xa6, 0xc5, ++ 0xc5, 0xef, 0x7b, 0x09, 0xe1, 0x3a, 0x53, 0xde, 0x2a, 0x62, 0x1e, 0x38, ++ 0x91, 0x22, 0xf9, 0x37, 0xba, 0xf4, 0x72, 0xc9, 0xf2, 0x90, 0x2a, 0x5e, ++ 0x70, 0x21, 0x7f, 0x94, 0xef, 0x60, 0xf9, 0xa4, 0xe5, 0x2f, 0x7e, 0x3c, ++ 0x0e, 0xf3, 0x44, 0x96, 0xf7, 0x62, 0x7e, 0x55, 0xf0, 0x39, 0x6e, 0x6f, ++ 0x06, 0xbb, 0xc6, 0x01, 0x5f, 0x97, 0x4b, 0x2c, 0x1f, 0xca, 0x2c, 0xe7, ++ 0x37, 0x39, 0x98, 0xfd, 0xd9, 0xbd, 0x3b, 0x61, 0x36, 0xcc, 0x43, 0xd8, ++ 0xc2, 0xce, 0xe9, 0x97, 0x87, 0x6f, 0x91, 0x81, 0x0f, 0xb5, 0x7a, 0x3f, ++ 0x74, 0xc8, 0x5a, 0x3d, 0xdc, 0xbf, 0x0c, 0x52, 0xbe, 0x85, 0xfd, 0x75, ++ 0x80, 0x4f, 0x7f, 0xee, 0x5c, 0xcb, 0x83, 0xea, 0xde, 0xca, 0xe4, 0xbe, ++ 0xbc, 0x4d, 0x46, 0x7f, 0xa9, 0x7c, 0x4b, 0x33, 0xc6, 0xb1, 0x03, 0x5b, ++ 0x3e, 0xc5, 0x3c, 0xf7, 0x69, 0x2f, 0x6c, 0xc3, 0xf8, 0x41, 0xa0, 0x4d, ++ 0x34, 0xe6, 0x3d, 0x6e, 0x11, 0x23, 0x56, 0xcc, 0xcb, 0x14, 0x8f, 0x58, ++ 0xd9, 0x3a, 0x65, 0xc8, 0x3f, 0xac, 0x6e, 0xad, 0xc2, 0xfd, 0xb6, 0xea, ++ 0x30, 0xcf, 0xef, 0x33, 0xe5, 0xbf, 0x55, 0xbc, 0xb0, 0xf7, 0xc5, 0x20, ++ 0x45, 0x4d, 0xc5, 0xaf, 0x9f, 0x75, 0x83, 0x1e, 0x38, 0xd9, 0xb9, 0xd9, ++ 0x0d, 0xf8, 0xa4, 0xfd, 0x61, 0xde, 0xe0, 0xf7, 0x3f, 0x97, 0x0c, 0x79, ++ 0x51, 0xf1, 0xf3, 0x7b, 0x7d, 0xc6, 0x7c, 0xc2, 0xf0, 0xaa, 0x98, 0xf9, ++ 0x84, 0x27, 0xe1, 0x1f, 0x94, 0xc1, 0xef, 0x75, 0x70, 0x7e, 0xd5, 0xf2, ++ 0x30, 0xb7, 0x0c, 0xe0, 0x79, 0xda, 0x91, 0xfc, 0xa2, 0x18, 0xf1, 0xfb, ++ 0xbe, 0x73, 0x3b, 0xdb, 0xbe, 0x78, 0x0a, 0xf2, 0xdc, 0xbb, 0x77, 0x9c, ++ 0x7a, 0x0a, 0xe0, 0xae, 0xfc, 0xeb, 0x67, 0x4f, 0x41, 0x3e, 0x13, 0xd9, ++ 0x67, 0xc7, 0x75, 0x29, 0xf0, 0xdc, 0xef, 0x30, 0x4f, 0x58, 0x6b, 0xf7, ++ 0x0b, 0x07, 0xf7, 0xf3, 0xb7, 0x3e, 0x8b, 0xf9, 0xd5, 0x67, 0x3e, 0xb0, ++ 0xa2, 0x9f, 0x73, 0x66, 0xef, 0xf1, 0x0c, 0xc8, 0x5f, 0x3b, 0xb3, 0xfd, ++ 0xeb, 0x54, 0x88, 0xc7, 0xdd, 0xb5, 0x77, 0x06, 0xc6, 0x2b, 0xef, 0xda, ++ 0x39, 0x6d, 0x10, 0x89, 0xa1, 0xdf, 0xb5, 0x27, 0xf0, 0x65, 0xe8, 0x22, ++ 0xf2, 0xbb, 0xcd, 0x74, 0x38, 0xd8, 0x7a, 0x10, 0xf3, 0xae, 0x4e, 0xbf, ++ 0x6f, 0x45, 0x7d, 0xd6, 0x97, 0x17, 0x1a, 0xae, 0x62, 0x79, 0xb6, 0x2a, ++ 0xcf, 0x07, 0x6d, 0x89, 0x9d, 0x47, 0xaf, 0xe5, 0x31, 0x56, 0xb7, 0xde, ++ 0x78, 0xdd, 0x15, 0xa0, 0x9f, 0x5b, 0x99, 0x3d, 0xd7, 0x97, 0xd7, 0x78, ++ 0xa1, 0x3c, 0xd0, 0x77, 0x28, 0x3d, 0x2f, 0xbf, 0x08, 0xba, 0xb5, 0xf0, ++ 0x3c, 0x5f, 0x13, 0xdd, 0x4e, 0xc3, 0x3f, 0x28, 0x7d, 0xc2, 0x26, 0xba, ++ 0x7d, 0xd1, 0xba, 0xf0, 0x57, 0x8f, 0xc3, 0xb7, 0xd6, 0x01, 0x71, 0xf3, ++ 0x40, 0x23, 0x17, 0x81, 0x2f, 0x2d, 0x4f, 0xff, 0xe7, 0x0e, 0xdf, 0x1e, ++ 0x07, 0x9c, 0xfb, 0xdb, 0x91, 0x10, 0x4c, 0x63, 0xf4, 0x0a, 0xcd, 0x12, ++ 0xc0, 0xde, 0xfb, 0x22, 0x03, 0xce, 0x35, 0x9c, 0x90, 0x7b, 0x31, 0xdf, ++ 0xa3, 0x77, 0xaf, 0xd5, 0x03, 0xf9, 0x8c, 0xe5, 0x7b, 0xdf, 0x43, 0xf9, ++ 0x38, 0xb3, 0xf3, 0x30, 0xc6, 0x55, 0x09, 0xcf, 0x93, 0x3f, 0x43, 0xfa, ++ 0xfe, 0x58, 0x5e, 0xb3, 0xc0, 0xe7, 0xb7, 0xc9, 0xc5, 0xf2, 0x47, 0x39, ++ 0xde, 0x21, 0xbf, 0x54, 0x75, 0xe3, 0x7b, 0x9e, 0x47, 0xca, 0xf8, 0x56, ++ 0xcb, 0x2f, 0x8d, 0x97, 0x57, 0xda, 0xeb, 0x18, 0xc1, 0xe2, 0xd0, 0xfc, ++ 0xdc, 0x40, 0x15, 0xf5, 0x93, 0xf8, 0xbd, 0x59, 0x7d, 0xf9, 0xa6, 0xc2, ++ 0x44, 0xa0, 0xd3, 0x11, 0x43, 0x9e, 0xae, 0x36, 0x6f, 0x73, 0x7f, 0x1e, ++ 0xae, 0x37, 0xa3, 0xf9, 0xd1, 0xb1, 0xf3, 0x76, 0xb5, 0x7c, 0xc1, 0x28, ++ 0x9d, 0xd8, 0x3a, 0xa2, 0xe5, 0x3f, 0x9f, 0x69, 0xe6, 0x79, 0xd3, 0xf4, ++ 0x7d, 0xfa, 0x78, 0xc8, 0x83, 0x63, 0xeb, 0x75, 0x20, 0x24, 0xbc, 0x47, ++ 0x62, 0xc8, 0xa3, 0x96, 0x1f, 0x7d, 0xca, 0x61, 0xca, 0x8b, 0x0e, 0x5d, ++ 0x5c, 0x5e, 0xf4, 0x85, 0xe0, 0xfd, 0xdf, 0xc5, 0xc7, 0x87, 0x0e, 0x16, ++ 0xaf, 0xd6, 0xf0, 0xd2, 0xfd, 0xe7, 0xd8, 0xfa, 0x58, 0x49, 0x60, 0x76, ++ 0x27, 0xf5, 0x4f, 0xe5, 0x04, 0xdc, 0x17, 0x60, 0xfe, 0xe9, 0x1d, 0xdc, ++ 0x3f, 0xd5, 0xf0, 0xa5, 0xc1, 0x5b, 0x1f, 0x66, 0x76, 0x43, 0xf7, 0x16, ++ 0xe6, 0x1f, 0x98, 0xe5, 0xb9, 0x3a, 0xce, 0x7d, 0x49, 0x29, 0x7c, 0x9c, ++ 0xea, 0xb6, 0xfd, 0xe3, 0x40, 0xef, 0x74, 0x1f, 0xd8, 0xcd, 0xf9, 0x8d, ++ 0xf1, 0x73, 0x75, 0xcb, 0x11, 0x96, 0x77, 0x4b, 0xf5, 0x73, 0x48, 0xaf, ++ 0x9f, 0xf9, 0xfd, 0x12, 0xe6, 0xfe, 0x32, 0x78, 0x7f, 0x81, 0xf6, 0xd8, ++ 0xfd, 0x05, 0x5a, 0x3e, 0x8d, 0xd9, 0xdf, 0x49, 0xc9, 0x77, 0x0b, 0xc0, ++ 0x7f, 0xb2, 0x93, 0xd9, 0x49, 0x27, 0xc3, 0xe2, 0xcc, 0x58, 0xf7, 0xdb, ++ 0xd8, 0x12, 0x64, 0x43, 0xfe, 0x40, 0xbd, 0x8b, 0xdd, 0x97, 0x21, 0xba, ++ 0x1d, 0x68, 0x1f, 0xdd, 0xe5, 0x9a, 0xf8, 0x7e, 0x62, 0x0a, 0x3c, 0x15, ++ 0xcc, 0xeb, 0xa9, 0x5b, 0xc6, 0xf3, 0x80, 0x7e, 0xe6, 0xc5, 0x7b, 0x45, ++ 0xeb, 0x5c, 0x57, 0x13, 0x80, 0xe7, 0x7e, 0xc0, 0x8f, 0x2e, 0xce, 0x20, ++ 0x7b, 0xfc, 0x04, 0xec, 0x34, 0x39, 0xad, 0x28, 0x4f, 0x54, 0xa3, 0xf0, ++ 0xf6, 0xd1, 0x23, 0xc5, 0x42, 0x42, 0x7a, 0xfa, 0x4b, 0x91, 0x74, 0xd0, ++ 0xe7, 0x1f, 0xe6, 0x1c, 0x97, 0xa1, 0xbf, 0xff, 0x34, 0xc5, 0x47, 0xfe, ++ 0x53, 0x22, 0xf5, 0x83, 0x28, 0x5c, 0xff, 0x19, 0x14, 0xbc, 0xcb, 0xd4, ++ 0xf8, 0x76, 0xb5, 0x56, 0xf6, 0xff, 0x54, 0x34, 0xc4, 0x33, 0xaa, 0xad, ++ 0xbd, 0x1f, 0x82, 0x7d, 0x4e, 0x5e, 0xb6, 0xe3, 0x7e, 0xb8, 0xb8, 0xcf, ++ 0x1e, 0xc4, 0xf8, 0xd8, 0x53, 0xec, 0x5e, 0x8d, 0x83, 0x3b, 0xbf, 0x7a, ++ 0x06, 0xef, 0xe5, 0xf9, 0x95, 0x95, 0x70, 0xbb, 0x50, 0x00, 0x7d, 0x50, ++ 0xca, 0xe3, 0x14, 0xc7, 0x77, 0x7e, 0xf5, 0xd4, 0x7f, 0x81, 0x1d, 0x09, ++ 0x8d, 0xe9, 0xf8, 0xa5, 0x4f, 0xd1, 0xfa, 0x60, 0x3f, 0xb7, 0x24, 0xa0, ++ 0xbd, 0xdf, 0xb3, 0x23, 0x71, 0x1c, 0xc4, 0x01, 0x4a, 0x5f, 0xbe, 0xef, ++ 0x5a, 0xd0, 0x17, 0xa5, 0xa0, 0xfb, 0xc0, 0xce, 0x7c, 0x61, 0x50, 0xa8, ++ 0x8e, 0xf6, 0x77, 0x6c, 0x20, 0x2b, 0x1f, 0xdb, 0x36, 0x0c, 0xcf, 0x05, ++ 0x54, 0xec, 0x70, 0x61, 0x3e, 0xe1, 0xc1, 0x9d, 0xbb, 0xaa, 0x41, 0xdf, ++ 0x9f, 0x79, 0x21, 0x81, 0x80, 0xbe, 0x3f, 0x2d, 0x77, 0xfd, 0x15, 0xca, ++ 0x81, 0x3d, 0x89, 0xa4, 0x59, 0x45, 0xbb, 0x4f, 0xd5, 0xaf, 0xab, 0x8b, ++ 0x88, 0xa4, 0xea, 0xed, 0xb9, 0x0a, 0x28, 0x1b, 0xf2, 0x5b, 0x08, 0xe6, ++ 0xb7, 0x60, 0xfc, 0x8d, 0xf2, 0x73, 0x45, 0x5b, 0x22, 0x9e, 0xff, 0xd0, ++ 0xd5, 0xe3, 0xf2, 0x1c, 0x1c, 0xc2, 0xef, 0x89, 0x1a, 0x02, 0x72, 0x47, ++ 0xed, 0x46, 0xd5, 0x98, 0xf7, 0xcc, 0xbe, 0x2f, 0x48, 0x60, 0xfa, 0x2b, ++ 0x60, 0xed, 0xbd, 0x87, 0xdd, 0x87, 0xc0, 0xea, 0x07, 0x94, 0xde, 0x12, ++ 0x56, 0x6e, 0x18, 0xc2, 0xe4, 0xb6, 0x13, 0xeb, 0x2f, 0xd6, 0xf8, 0x95, ++ 0x7f, 0xef, 0xdf, 0x2f, 0xab, 0x1f, 0x48, 0x60, 0xf1, 0x80, 0x68, 0x3f, ++ 0xac, 0x7d, 0xb5, 0x95, 0xdd, 0xaf, 0x61, 0xa6, 0xef, 0x4f, 0x13, 0x04, ++ 0x7e, 0x1e, 0xf7, 0x2f, 0x97, 0xc4, 0xba, 0x7f, 0x22, 0x06, 0xfc, 0xec, ++ 0x5e, 0x2e, 0x81, 0x04, 0xe1, 0xfe, 0x55, 0xb2, 0xdd, 0x8e, 0xf7, 0xf1, ++ 0x54, 0x2a, 0x91, 0x31, 0x90, 0xaf, 0xfe, 0xa2, 0xc2, 0xf6, 0x3f, 0x2a, ++ 0xdd, 0x91, 0x31, 0x90, 0xaf, 0xbe, 0x87, 0xeb, 0xbf, 0x4a, 0x07, 0x2d, ++ 0xd3, 0xf7, 0x43, 0x38, 0x1c, 0x50, 0x1f, 0xca, 0xc4, 0xd6, 0xf5, 0x3c, ++ 0xde, 0xeb, 0xb4, 0xcb, 0x8e, 0xf7, 0xe1, 0x55, 0xbd, 0xec, 0xf2, 0xa1, ++ 0x9f, 0xf0, 0xe2, 0x57, 0xc7, 0x9e, 0xc8, 0x83, 0x7c, 0xb5, 0x04, 0xcc, ++ 0x93, 0xae, 0x7a, 0xf9, 0x5f, 0x90, 0xfe, 0x55, 0xd6, 0xc8, 0xed, 0xc0, ++ 0xff, 0xbd, 0xdb, 0xad, 0x78, 0x3f, 0x69, 0xf7, 0xf6, 0x43, 0x19, 0x60, ++ 0x37, 0x74, 0xcb, 0x91, 0x8c, 0xe4, 0xf3, 0xec, 0xeb, 0x54, 0x85, 0xad, ++ 0x86, 0x7d, 0x6a, 0x6d, 0x1e, 0x27, 0x6b, 0x97, 0x4e, 0x86, 0x73, 0xbc, ++ 0xda, 0x39, 0xc3, 0xf2, 0x38, 0xfa, 0xe2, 0x8d, 0x04, 0x96, 0xd7, 0xd1, ++ 0x9c, 0xe0, 0xfb, 0x15, 0xd3, 0x73, 0xc6, 0xfb, 0x65, 0x4e, 0xd6, 0xce, ++ 0x36, 0xdc, 0x9b, 0x58, 0x6e, 0x8b, 0xad, 0xc7, 0x5a, 0x40, 0x2f, 0xe8, ++ 0xe2, 0x78, 0x62, 0xf4, 0x5c, 0x61, 0x0b, 0xf4, 0x7b, 0x9a, 0x74, 0xd5, ++ 0x0f, 0xa1, 0x24, 0xa9, 0x12, 0x7a, 0x71, 0x7f, 0xbc, 0x7c, 0x4b, 0x66, ++ 0x3a, 0xf8, 0xbb, 0x07, 0xec, 0x97, 0xe0, 0xbe, 0xd5, 0x01, 0x59, 0x45, ++ 0x7f, 0x10, 0x9e, 0x7a, 0x7d, 0x7c, 0xa2, 0xd6, 0x9b, 0x2b, 0xe1, 0x79, ++ 0xfa, 0xac, 0x5c, 0x89, 0xc2, 0xd1, 0xd3, 0xfc, 0x69, 0xc9, 0x10, 0x02, ++ 0xf9, 0x81, 0xf6, 0xd9, 0xb1, 0xf4, 0xd3, 0xde, 0x84, 0x04, 0xe4, 0xa7, ++ 0x72, 0x9b, 0x35, 0xe6, 0xf9, 0xcd, 0xdf, 0x72, 0x7e, 0xdb, 0x06, 0xf2, ++ 0x36, 0x81, 0x8d, 0xe7, 0xcd, 0x8e, 0x8e, 0x7b, 0x40, 0x0e, 0x29, 0x00, ++ 0xc7, 0x14, 0xa7, 0x8a, 0xf3, 0x29, 0xa7, 0x7e, 0x00, 0xbb, 0x27, 0x6a, ++ 0x4e, 0xae, 0xfe, 0xdc, 0xf6, 0x22, 0xa9, 0x01, 0xeb, 0x51, 0xf9, 0x42, ++ 0x7c, 0x2c, 0x22, 0xeb, 0x95, 0x3c, 0x67, 0x7f, 0xbd, 0xb2, 0x68, 0x69, ++ 0x5e, 0xae, 0x94, 0x8b, 0x0a, 0xeb, 0x9b, 0x3e, 0x7e, 0x13, 0xa3, 0x74, ++ 0x22, 0xc1, 0x14, 0xb4, 0x93, 0x24, 0x4e, 0x43, 0xb2, 0x7e, 0xb0, 0x21, ++ 0xdf, 0x5f, 0x92, 0x8b, 0x6c, 0x80, 0x2f, 0x85, 0x14, 0x79, 0x24, 0x11, ++ 0x48, 0xdd, 0x80, 0x72, 0xea, 0x20, 0x61, 0x7c, 0x3a, 0xa9, 0x19, 0xc2, ++ 0xd6, 0xa1, 0x1a, 0x02, 0xf1, 0xf1, 0x13, 0x7c, 0x7f, 0xd6, 0x2a, 0xa9, ++ 0x0f, 0xe3, 0x7d, 0x33, 0x1d, 0x22, 0xea, 0xf3, 0x0b, 0xe1, 0xed, 0xbd, ++ 0x04, 0x37, 0xc2, 0x6d, 0x95, 0x6a, 0x88, 0x17, 0xed, 0x8d, 0x59, 0x1e, ++ 0xb0, 0xc7, 0x84, 0xa0, 0x9f, 0x7c, 0x4b, 0xf9, 0xa1, 0xae, 0x76, 0x66, ++ 0x2e, 0x3b, 0x17, 0x4e, 0x7c, 0x90, 0xef, 0xe6, 0x26, 0x0c, 0x3e, 0xb7, ++ 0xe7, 0xd5, 0xaf, 0xc1, 0x3e, 0xa0, 0x7c, 0xc6, 0xee, 0xb1, 0xfa, 0x3e, ++ 0x09, 0xd5, 0xd1, 0xf1, 0xe0, 0x98, 0x31, 0xc6, 0xff, 0x0a, 0xd8, 0x7d, ++ 0xf6, 0xe6, 0xf1, 0xfe, 0xcc, 0xe9, 0x40, 0x82, 0xfb, 0x0d, 0xf7, 0x9d, ++ 0xc3, 0x5f, 0xaf, 0x76, 0x7f, 0x1e, 0xf8, 0xeb, 0x89, 0x7f, 0x9d, 0x08, ++ 0xfb, 0x31, 0x4e, 0x0f, 0x89, 0x80, 0xbd, 0x94, 0xe0, 0x24, 0x91, 0x84, ++ 0x71, 0x70, 0x4f, 0x9e, 0x74, 0x52, 0x2f, 0xbf, 0x6e, 0xc2, 0xca, 0x23, ++ 0x28, 0x3b, 0x83, 0x5e, 0xf3, 0x4c, 0x31, 0x7e, 0x37, 0xf3, 0x35, 0xf1, ++ 0x4a, 0x9f, 0xf7, 0xe9, 0x45, 0x11, 0xdb, 0x7f, 0x6e, 0x6a, 0xff, 0xf9, ++ 0xf9, 0xda, 0x6b, 0xf8, 0x08, 0xd8, 0x36, 0x7a, 0x8f, 0xe6, 0x46, 0xf1, ++ 0xe2, 0xe0, 0x73, 0x08, 0x16, 0x78, 0xcf, 0x75, 0x01, 0x3e, 0xc6, 0xb9, ++ 0xbd, 0x75, 0x40, 0x47, 0xa5, 0xf7, 0xc3, 0xfb, 0x00, 0x1f, 0xe3, 0x9c, ++ 0xcc, 0x1f, 0x4c, 0x69, 0x24, 0x7a, 0x7f, 0x2d, 0xd7, 0xc9, 0xf4, 0xd5, ++ 0x0a, 0x7e, 0xff, 0x34, 0xfd, 0x2b, 0x72, 0xea, 0xfa, 0x23, 0x1e, 0x1b, ++ 0xc6, 0x47, 0x57, 0x71, 0xbc, 0xf7, 0xd5, 0xd7, 0xe2, 0x26, 0xfd, 0xea, ++ 0xdb, 0x25, 0xc0, 0x6b, 0xbf, 0xfa, 0xf6, 0x78, 0xf5, 0x1d, 0xb1, 0xeb, ++ 0xbb, 0xe2, 0xc1, 0x93, 0x10, 0x1b, 0x9e, 0xa4, 0x38, 0xfd, 0x07, 0x63, ++ 0xd7, 0xaf, 0x7e, 0xf9, 0xbd, 0x37, 0x23, 0x2a, 0xbc, 0x64, 0x7a, 0x03, ++ 0x82, 0xf3, 0xfc, 0xdc, 0x72, 0xae, 0x13, 0xfc, 0xab, 0xc4, 0x0f, 0x53, ++ 0x8b, 0x19, 0x57, 0xb0, 0xfd, 0x00, 0x13, 0xdd, 0x1c, 0xc0, 0x7f, 0x94, ++ 0x1f, 0x1c, 0xa3, 0x74, 0xef, 0xe1, 0xff, 0xb2, 0x75, 0xf4, 0x1b, 0x11, ++ 0x83, 0xfe, 0x24, 0x82, 0x7c, 0x57, 0xcc, 0xe1, 0xa1, 0x65, 0xe7, 0x60, ++ 0x0a, 0xdf, 0x8f, 0x39, 0xb8, 0xd3, 0x37, 0xb1, 0xfd, 0xca, 0xb9, 0x77, ++ 0xb1, 0x38, 0xd1, 0x8f, 0x6d, 0xa5, 0xe8, 0xef, 0x1e, 0xe1, 0xf7, 0x01, ++ 0xcd, 0x6d, 0x64, 0x7e, 0xf5, 0xdc, 0xa5, 0x6c, 0x1f, 0x91, 0x94, 0xb1, ++ 0x73, 0x3e, 0x1e, 0xfa, 0x1f, 0x8c, 0x77, 0x1b, 0x74, 0x42, 0xe9, 0x7d, ++ 0x5b, 0x83, 0x10, 0x8a, 0x64, 0xc2, 0xbd, 0x35, 0x26, 0xfb, 0xb5, 0xef, ++ 0x7e, 0x9c, 0x45, 0x0a, 0xd4, 0x2f, 0x36, 0xc5, 0x5d, 0x34, 0x7e, 0xd2, ++ 0xce, 0x23, 0xcd, 0xe7, 0xf6, 0x75, 0x26, 0xe7, 0xcf, 0x85, 0xa4, 0xd7, ++ 0x05, 0x72, 0x6f, 0x3e, 0xf7, 0xfe, 0x0a, 0xd7, 0x6b, 0x9a, 0xde, 0x0f, ++ 0xae, 0x23, 0x59, 0x70, 0x6e, 0x5f, 0xb4, 0x38, 0xbc, 0xb0, 0x3f, 0x2a, ++ 0xf2, 0x73, 0xa6, 0xc4, 0xcd, 0xee, 0xf3, 0x23, 0xbe, 0x61, 0xec, 0x7e, ++ 0x39, 0x2d, 0x8f, 0x2b, 0x4b, 0x4d, 0x84, 0xf5, 0x8d, 0x84, 0xf9, 0x7b, ++ 0xbe, 0xcf, 0xb2, 0xe4, 0x2a, 0x75, 0x90, 0xfe, 0x9c, 0x96, 0x74, 0xce, ++ 0x81, 0xf7, 0x83, 0xd4, 0xc9, 0xde, 0x34, 0xd0, 0x83, 0xf2, 0x39, 0x6a, ++ 0xd7, 0x51, 0x57, 0x4d, 0x39, 0x37, 0x82, 0xa8, 0xba, 0x73, 0x64, 0xd4, ++ 0x9e, 0x43, 0xe1, 0x96, 0x3d, 0xec, 0xbe, 0x44, 0xc9, 0x53, 0x44, 0x4a, ++ 0xc1, 0x0e, 0xe4, 0xf7, 0x03, 0x90, 0x94, 0xab, 0xfb, 0xec, 0xae, 0xb7, ++ 0x28, 0x1e, 0x96, 0xac, 0x53, 0xf1, 0xdc, 0xea, 0x42, 0x27, 0xb3, 0x33, ++ 0x7f, 0xe1, 0x2a, 0xba, 0xd3, 0x39, 0x01, 0xec, 0xcb, 0x89, 0x5e, 0x76, ++ 0xcf, 0xad, 0x91, 0x8e, 0xc1, 0x9d, 0x6c, 0x7e, 0x75, 0x30, 0xbf, 0xcc, ++ 0xfe, 0x70, 0xd7, 0x29, 0x5e, 0x2f, 0xda, 0x9d, 0x57, 0x53, 0x8b, 0x01, ++ 0xe3, 0x38, 0x5e, 0xfc, 0x7d, 0x07, 0xd1, 0xaa, 0xbe, 0xa7, 0x82, 0x3c, ++ 0xfe, 0x9b, 0xcc, 0x7e, 0xaf, 0xa0, 0x1f, 0x1e, 0x18, 0xfd, 0xce, 0xa6, ++ 0x24, 0xe3, 0xbd, 0xec, 0x0b, 0xdc, 0xab, 0x3f, 0x04, 0x3e, 0x5d, 0xc3, ++ 0xef, 0x23, 0x5c, 0x59, 0x9b, 0x85, 0xcf, 0xd5, 0xb5, 0x69, 0x68, 0x77, ++ 0xd6, 0xd7, 0x7a, 0xf1, 0xa9, 0xe1, 0xc5, 0xe6, 0x6d, 0xc0, 0x7b, 0xdf, ++ 0x6c, 0xa3, 0x58, 0x7f, 0x36, 0x8f, 0x9f, 0xd9, 0x15, 0xd4, 0x96, 0x81, ++ 0x7c, 0x0a, 0xc9, 0x53, 0x13, 0x81, 0xb2, 0x2d, 0xbd, 0x86, 0x80, 0xbd, ++ 0x6b, 0xef, 0xc3, 0x4f, 0x03, 0xe2, 0x47, 0xe9, 0x2b, 0xfb, 0xb1, 0x6c, ++ 0xf5, 0xb0, 0xdf, 0x8d, 0x90, 0x1b, 0x67, 0x21, 0x9e, 0x69, 0x7b, 0x52, ++ 0x4a, 0xbf, 0x2f, 0x71, 0xf9, 0x1f, 0x07, 0x39, 0xb1, 0xab, 0x97, 0x19, ++ 0xee, 0x91, 0xb3, 0xa6, 0x8d, 0x37, 0xdd, 0x37, 0x68, 0xc2, 0x9b, 0xc6, ++ 0x1f, 0xdb, 0x18, 0xfe, 0xd6, 0x0a, 0x8c, 0x3f, 0xcc, 0xf8, 0x5b, 0x2b, ++ 0x77, 0xaa, 0xb0, 0xaf, 0xbc, 0xf6, 0xaa, 0xbe, 0x7b, 0x67, 0x10, 0x7f, ++ 0xd4, 0xbc, 0x67, 0xf8, 0xfb, 0x2d, 0xdb, 0x67, 0x8b, 0x8b, 0x3f, 0x4f, ++ 0x32, 0xda, 0xaf, 0x0b, 0xf2, 0xeb, 0x6f, 0xaf, 0xa3, 0xaf, 0x1e, 0xe4, ++ 0xfb, 0x8b, 0x0f, 0xd4, 0x4e, 0x44, 0x7c, 0xad, 0xe2, 0xf7, 0x48, 0xde, ++ 0x5f, 0xeb, 0xc3, 0xa7, 0x08, 0xf8, 0xa3, 0xf3, 0xb3, 0x66, 0x07, 0x09, ++ 0xdc, 0x8f, 0xce, 0x7e, 0x1b, 0x82, 0x3e, 0x9d, 0x45, 0x3e, 0xb8, 0x7f, ++ 0x16, 0x78, 0x17, 0xf0, 0x27, 0x3a, 0x19, 0x3e, 0xad, 0x69, 0x35, 0xb8, ++ 0xbf, 0x66, 0x73, 0x32, 0x7c, 0x89, 0xce, 0x20, 0xe2, 0x45, 0x76, 0x32, ++ 0x7c, 0x89, 0x4e, 0xc6, 0x6f, 0x0a, 0x2f, 0x4b, 0x80, 0xbf, 0x5c, 0x6c, ++ 0x8f, 0xef, 0x29, 0xfe, 0x0e, 0x00, 0x7f, 0xd9, 0xd2, 0x27, 0x1b, 0xf0, ++ 0xa5, 0xa4, 0x14, 0x5c, 0x1c, 0xfe, 0x1e, 0xa3, 0xf8, 0xa3, 0x70, 0xa4, ++ 0x70, 0xf9, 0x32, 0xe3, 0x21, 0x45, 0x61, 0xf7, 0x53, 0x6a, 0x72, 0x15, ++ 0xcf, 0x8e, 0x7b, 0x94, 0xce, 0x1f, 0xd6, 0xed, 0x0d, 0xb5, 0x04, 0x9f, ++ 0x03, 0xe3, 0xf8, 0x8b, 0x23, 0x5c, 0x6c, 0xdd, 0x4c, 0xb1, 0xd4, 0xec, ++ 0x97, 0x01, 0x1f, 0xc9, 0x84, 0xaf, 0x27, 0x41, 0x92, 0x9e, 0x4f, 0x58, ++ 0xea, 0x21, 0xfc, 0xa5, 0x05, 0x89, 0x0a, 0x65, 0x81, 0xc1, 0x41, 0x1a, ++ 0x86, 0x19, 0xee, 0x95, 0x14, 0x3d, 0x92, 0xe9, 0x5e, 0x36, 0x75, 0x03, ++ 0xf0, 0xc1, 0xfa, 0x43, 0xb2, 0x05, 0xee, 0xa3, 0x13, 0x97, 0x5e, 0x6d, ++ 0x38, 0x0f, 0x2a, 0xce, 0xf6, 0x25, 0xa9, 0x88, 0x4f, 0x3f, 0xde, 0xd3, ++ 0xfc, 0x60, 0xad, 0x8a, 0xf4, 0x5b, 0x07, 0x74, 0x84, 0x7b, 0x40, 0xb9, ++ 0xff, 0x75, 0x3f, 0xa7, 0xe7, 0x03, 0xfc, 0x1e, 0xca, 0x55, 0x5c, 0x3e, ++ 0xd6, 0x72, 0x79, 0x79, 0x98, 0xcb, 0x49, 0x1d, 0xbf, 0x37, 0x79, 0xcd, ++ 0x4c, 0x96, 0x67, 0x95, 0x92, 0x63, 0xe1, 0xf7, 0x95, 0x45, 0x88, 0x3e, ++ 0x8f, 0x29, 0xc9, 0x1b, 0x26, 0x0a, 0x85, 0x0b, 0x6d, 0x6a, 0x15, 0x9f, ++ 0x78, 0xcf, 0x22, 0x79, 0xdf, 0x1a, 0x1a, 0x4d, 0xdb, 0x25, 0x64, 0x13, ++ 0x1f, 0xf0, 0x49, 0xd2, 0xfb, 0xf7, 0x86, 0xd8, 0x7d, 0x8d, 0x45, 0x83, ++ 0xc1, 0x0e, 0x4a, 0xd2, 0xee, 0x5f, 0x9c, 0xa2, 0x26, 0xcd, 0xc1, 0x83, ++ 0xb0, 0x11, 0x89, 0xf9, 0x1d, 0x54, 0x15, 0xa2, 0x1f, 0xd3, 0x69, 0x89, ++ 0x75, 0x4f, 0x55, 0x9d, 0xf7, 0x80, 0x0d, 0xe2, 0xa1, 0xf1, 0xe0, 0x49, ++ 0xf0, 0xfa, 0x32, 0xef, 0xa7, 0xe3, 0x25, 0x34, 0xba, 0xd0, 0x7e, 0x1f, ++ 0xe0, 0x2f, 0x9a, 0xb3, 0x90, 0x96, 0x9d, 0x8d, 0x09, 0x18, 0xff, 0x4b, ++ 0xe0, 0xbf, 0xcf, 0xe2, 0xa4, 0x70, 0x97, 0xea, 0xe8, 0x1d, 0xef, 0x1e, ++ 0xea, 0x8d, 0xae, 0xab, 0x12, 0x5d, 0x94, 0x9e, 0x1e, 0x80, 0x91, 0x3e, ++ 0x1f, 0x69, 0x1c, 0x89, 0xbf, 0xcb, 0xf2, 0xa8, 0x5c, 0x84, 0xbf, 0xe3, ++ 0xf2, 0x28, 0x5f, 0x4f, 0xb5, 0x7b, 0xce, 0xb5, 0x76, 0xdf, 0x70, 0xfd, ++ 0xe8, 0xce, 0xbb, 0xcc, 0xe0, 0xb7, 0xae, 0x97, 0x7d, 0xd8, 0xce, 0x33, ++ 0xc5, 0x28, 0xff, 0xeb, 0xb9, 0xbe, 0x4d, 0x9e, 0x6e, 0xe4, 0x73, 0x4d, ++ 0xdf, 0x1e, 0xed, 0xd3, 0xb7, 0xfe, 0x11, 0x00, 0x4f, 0xea, 0xb9, 0xe9, ++ 0xa8, 0xc7, 0x52, 0x6e, 0x88, 0xad, 0x77, 0xeb, 0x64, 0x05, 0xef, 0x2d, ++ 0xaf, 0x1b, 0xcb, 0xe4, 0x3c, 0x58, 0xac, 0xb0, 0xfb, 0x4b, 0xfb, 0xeb, ++ 0x01, 0x8c, 0x53, 0x9f, 0xf5, 0x8f, 0xd9, 0x08, 0x7a, 0x54, 0xe3, 0xab, ++ 0xe5, 0x84, 0xe9, 0x9d, 0x20, 0x71, 0x78, 0x71, 0x1d, 0xe2, 0xf7, 0xdb, ++ 0x68, 0x76, 0xf0, 0x4a, 0xb8, 0x07, 0x90, 0xeb, 0x57, 0x78, 0x8a, 0xa3, ++ 0xd8, 0xef, 0x0f, 0xa4, 0xce, 0x65, 0xf7, 0xf9, 0xae, 0xe1, 0xf7, 0x58, ++ 0x3d, 0x44, 0xf9, 0x8a, 0xe0, 0xbd, 0xa7, 0x5e, 0x7c, 0x5e, 0xed, 0x62, ++ 0xfb, 0x13, 0xcb, 0x6d, 0xe3, 0xf1, 0x3e, 0xb5, 0x3a, 0xa7, 0x05, 0xf5, ++ 0x84, 0xf4, 0x81, 0x35, 0x04, 0x26, 0x87, 0xb4, 0x7f, 0x92, 0x07, 0xe2, ++ 0x05, 0x92, 0xec, 0xed, 0xf4, 0x41, 0xbc, 0xcf, 0x25, 0x85, 0xe1, 0xde, ++ 0xdc, 0x3a, 0x67, 0x1e, 0xde, 0xfb, 0x2e, 0x24, 0xe5, 0x79, 0x80, 0xfe, ++ 0x5f, 0xba, 0x16, 0x0c, 0x3f, 0x5f, 0x3e, 0x1d, 0x9d, 0x28, 0xde, 0x97, ++ 0xe9, 0x49, 0x29, 0x22, 0x1f, 0x65, 0xe3, 0x6e, 0x00, 0x9e, 0x47, 0x96, ++ 0x3d, 0x37, 0x10, 0x88, 0x1b, 0x6e, 0x48, 0xa9, 0xb1, 0x03, 0xde, 0x26, ++ 0xb9, 0x58, 0x5c, 0xbf, 0xb1, 0x38, 0x1f, 0xf1, 0x48, 0xf1, 0x7b, 0x9d, ++ 0x6b, 0x60, 0xb4, 0x9f, 0x41, 0xb3, 0xaf, 0xee, 0xbb, 0x07, 0x0b, 0xba, ++ 0xdd, 0x10, 0xe7, 0x5c, 0xf3, 0xad, 0x2e, 0x66, 0x2f, 0x91, 0xf4, 0x20, ++ 0x19, 0xa5, 0x93, 0xf3, 0x46, 0xed, 0x77, 0x4e, 0xd4, 0x20, 0xc9, 0xd2, ++ 0xc9, 0xfb, 0xf2, 0xd1, 0x85, 0x04, 0xf6, 0x87, 0xfa, 0xcb, 0x79, 0x1c, ++ 0x3d, 0xb6, 0x99, 0xe9, 0xb1, 0x15, 0x42, 0x6c, 0x3d, 0xa6, 0xd9, 0x99, ++ 0x9a, 0x1e, 0x93, 0x4d, 0xfa, 0x41, 0x7b, 0xd6, 0x0f, 0x9f, 0x69, 0x38, ++ 0xa7, 0xa5, 0xa4, 0x78, 0x81, 0x77, 0xe1, 0x19, 0xb4, 0x78, 0xc1, 0xbe, ++ 0x7b, 0xb1, 0xfe, 0xd6, 0x24, 0xc4, 0x43, 0x0d, 0xe0, 0x81, 0xa4, 0x5d, ++ 0xdd, 0xe7, 0xbf, 0xfe, 0x60, 0x04, 0xd8, 0x8f, 0xf9, 0x31, 0xf9, 0xcd, ++ 0xac, 0xbf, 0x16, 0xf4, 0xad, 0xe7, 0xbe, 0x54, 0xa0, 0xd3, 0x09, 0x59, ++ 0x1d, 0x34, 0x07, 0xf8, 0xe9, 0x50, 0xec, 0xf5, 0x7c, 0xea, 0x23, 0x97, ++ 0x3e, 0x0c, 0x7c, 0xb0, 0xe0, 0xb7, 0xa2, 0xa0, 0xdf, 0x4f, 0x29, 0x3d, ++ 0xb7, 0x12, 0xd7, 0xd3, 0x92, 0x73, 0x13, 0xf1, 0x59, 0xd6, 0x38, 0x13, ++ 0xf9, 0x9e, 0x40, 0x14, 0x5c, 0xe7, 0x87, 0x1d, 0x6f, 0xba, 0xdb, 0x0d, ++ 0x70, 0x1d, 0x6f, 0xe4, 0x79, 0x00, 0x4d, 0x72, 0x08, 0xf2, 0x33, 0x8e, ++ 0x37, 0xde, 0x8d, 0xf7, 0x95, 0x40, 0x9e, 0xb7, 0xa8, 0xdb, 0xdf, 0x27, ++ 0x79, 0x2a, 0xda, 0x97, 0xda, 0x3d, 0x63, 0xc7, 0x43, 0x77, 0xba, 0xf5, ++ 0xfb, 0xbb, 0x25, 0xbf, 0xb0, 0xfb, 0xc0, 0x6e, 0x8d, 0xc7, 0x5f, 0x25, ++ 0x4d, 0xb1, 0xfd, 0x7a, 0x58, 0x43, 0x21, 0x7e, 0x4a, 0x01, 0xcc, 0x02, ++ 0x7b, 0x98, 0xda, 0x37, 0xbd, 0x11, 0xb0, 0x7f, 0x36, 0x5a, 0xbd, 0x41, ++ 0x12, 0x2d, 0x07, 0x1f, 0xb1, 0xc7, 0xcc, 0x4f, 0x5c, 0xe2, 0x9a, 0xf1, ++ 0x28, 0xe0, 0x7d, 0x89, 0xcb, 0xf7, 0x24, 0xc8, 0x39, 0x71, 0xb2, 0x7b, ++ 0x41, 0xe3, 0xf3, 0x39, 0x1b, 0xf7, 0x18, 0x6c, 0x02, 0xc3, 0x7e, 0xd3, ++ 0xe3, 0x3c, 0x4f, 0x53, 0xf2, 0xbb, 0xf5, 0xf7, 0xbb, 0xf5, 0xdd, 0xc7, ++ 0xc9, 0xe3, 0x24, 0xc4, 0x16, 0xe7, 0xbb, 0x43, 0xfb, 0x7d, 0x83, 0x38, ++ 0xdf, 0xdd, 0x2c, 0x9f, 0x83, 0x78, 0x62, 0x7f, 0xd7, 0xfc, 0x84, 0x84, ++ 0xa8, 0x9f, 0xd0, 0x06, 0xf3, 0xa8, 0x6a, 0x3c, 0x55, 0xff, 0x01, 0xe2, ++ 0x89, 0xfb, 0x09, 0x1c, 0xee, 0x13, 0x32, 0x83, 0xfb, 0xc4, 0x33, 0x56, ++ 0xf6, 0x3b, 0x37, 0x26, 0xbe, 0x38, 0xc1, 0xf3, 0x47, 0x16, 0x09, 0x0c, ++ 0xaf, 0x1a, 0x7f, 0x9f, 0xe8, 0xb3, 0x77, 0xfc, 0x78, 0x0f, 0x8d, 0x99, ++ 0xff, 0x84, 0x8d, 0x97, 0x6e, 0x98, 0x44, 0xfb, 0xfd, 0xac, 0x43, 0xc6, ++ 0x38, 0x5c, 0x25, 0xe5, 0x1f, 0xe0, 0x1b, 0x61, 0xe3, 0x24, 0xcc, 0x5f, ++ 0x17, 0x1e, 0x99, 0xf4, 0x30, 0xe4, 0x25, 0x7d, 0xfe, 0xba, 0x88, 0xdf, ++ 0xcb, 0xcf, 0xd9, 0xf0, 0x7b, 0xf7, 0xcf, 0xbc, 0x1b, 0xe6, 0x42, 0x9c, ++ 0xe7, 0x0d, 0x19, 0xef, 0xeb, 0xfe, 0xbc, 0x63, 0x46, 0x22, 0x8b, 0xf3, ++ 0x18, 0xe3, 0xd0, 0x0b, 0xdd, 0x6c, 0x9d, 0x3f, 0xc9, 0xe5, 0xbe, 0xe4, ++ 0xdc, 0x6a, 0xe4, 0xcf, 0x3e, 0xfe, 0x68, 0x58, 0xa8, 0x80, 0x5c, 0x95, ++ 0x9c, 0x7b, 0x08, 0xed, 0x99, 0x92, 0x2d, 0x02, 0xde, 0x13, 0x49, 0x82, ++ 0xbd, 0xaf, 0x4e, 0x95, 0x38, 0x1f, 0x4e, 0x86, 0xf6, 0xa7, 0x0b, 0x97, ++ 0x03, 0xbe, 0xa7, 0x34, 0xe0, 0xfe, 0x46, 0xe9, 0x66, 0xab, 0x77, 0xb5, ++ 0xd0, 0x9f, 0xce, 0x27, 0x5d, 0xaa, 0xe1, 0x5e, 0xf5, 0xd2, 0xae, 0x35, ++ 0xd8, 0x2f, 0xa1, 0xf6, 0x54, 0x8a, 0x6e, 0xbf, 0xfb, 0x04, 0xcf, 0x03, ++ 0x2e, 0x3d, 0xc7, 0xee, 0x07, 0x24, 0x9e, 0x20, 0x49, 0x03, 0xbe, 0xe7, ++ 0x7a, 0x27, 0xca, 0xbf, 0xc6, 0x7b, 0x5f, 0xbb, 0xed, 0xb1, 0xe3, 0xec, ++ 0xdf, 0x70, 0x7b, 0xa6, 0xe4, 0xdc, 0x64, 0x83, 0xdf, 0x10, 0x9d, 0xdf, ++ 0xf7, 0x99, 0x7c, 0xf2, 0xf5, 0xbc, 0xb4, 0x6b, 0x22, 0x83, 0xab, 0x6f, ++ 0x3e, 0x1b, 0x26, 0xc5, 0x9a, 0x4f, 0x74, 0x1e, 0x53, 0xb0, 0x7d, 0x77, ++ 0x52, 0xec, 0xf1, 0x33, 0x39, 0x9e, 0x8f, 0xd5, 0x96, 0xc1, 0xc9, 0x0d, ++ 0x52, 0xa6, 0xb0, 0x7a, 0x25, 0x0d, 0x77, 0x2b, 0xa0, 0x4f, 0x4a, 0x9a, ++ 0x92, 0x92, 0x05, 0xdd, 0xbc, 0x4a, 0x1b, 0x2b, 0x0c, 0x79, 0x18, 0xa5, ++ 0x4d, 0xc5, 0xca, 0x3c, 0x5d, 0xbf, 0x51, 0x3a, 0x38, 0x5e, 0x9b, 0x3a, ++ 0x2a, 0x4a, 0x87, 0xcc, 0x87, 0xe4, 0x2b, 0x97, 0x3b, 0x61, 0xbd, 0x2f, ++ 0x72, 0xb9, 0x61, 0xbc, 0x8d, 0x8b, 0xf2, 0x7f, 0xa2, 0x42, 0x7f, 0x4c, ++ 0xff, 0x7c, 0x22, 0x37, 0x64, 0xd4, 0xa0, 0x7e, 0xb9, 0xd3, 0x1d, 0xeb, ++ 0x5c, 0x43, 0xa6, 0x5b, 0x35, 0xc4, 0x95, 0x4a, 0x1b, 0x39, 0x7d, 0xa8, ++ 0x9d, 0x9c, 0xa7, 0xa3, 0x8f, 0x46, 0x17, 0x73, 0xfb, 0x63, 0xcd, 0xa5, ++ 0xf9, 0x3f, 0x81, 0x78, 0xf2, 0x63, 0xec, 0x56, 0x90, 0xf8, 0x7a, 0xc7, ++ 0x44, 0xb7, 0xcc, 0xd8, 0x78, 0x9b, 0xdc, 0x87, 0xb7, 0x2c, 0xcc, 0x07, ++ 0xba, 0x30, 0xde, 0xbe, 0x63, 0xc8, 0xfb, 0xe9, 0x87, 0x37, 0x4e, 0x5f, ++ 0x0d, 0x2f, 0xda, 0x7b, 0x6a, 0x1f, 0xe5, 0x02, 0xbe, 0x26, 0x43, 0xc0, ++ 0x69, 0x20, 0xf4, 0xc3, 0xe8, 0x7f, 0x21, 0x7c, 0x45, 0xc7, 0xe5, 0xf4, ++ 0x9f, 0x1a, 0x7b, 0x1e, 0xfe, 0xbe, 0x79, 0x2c, 0x25, 0x41, 0x6a, 0x3f, ++ 0x2c, 0xb8, 0xe0, 0x3c, 0xee, 0x23, 0x41, 0xdb, 0x79, 0xe6, 0xa1, 0xd1, ++ 0x9f, 0x5c, 0x66, 0xa0, 0xbf, 0xff, 0xa1, 0xd1, 0x57, 0x82, 0x1c, 0x6a, ++ 0xf4, 0x5e, 0x70, 0xe0, 0x31, 0xe4, 0xdf, 0x05, 0x54, 0x1e, 0x61, 0x5f, ++ 0xfe, 0x78, 0xc3, 0xdd, 0x86, 0xf5, 0x21, 0x0a, 0x5f, 0x1c, 0xba, 0x8f, ++ 0x0a, 0x92, 0xec, 0xfc, 0xff, 0x73, 0x74, 0xff, 0x44, 0x0e, 0x66, 0x40, ++ 0xde, 0x57, 0x70, 0x1d, 0x5b, 0x47, 0x4e, 0x6c, 0x7c, 0x30, 0x43, 0x8f, ++ 0xe7, 0x25, 0xae, 0xa9, 0x0b, 0x81, 0x2e, 0x64, 0xd3, 0xc0, 0x8b, 0x5a, ++ 0x3f, 0x82, 0x05, 0xde, 0x0e, 0x15, 0xd7, 0x25, 0x19, 0xe3, 0x61, 0xbb, ++ 0x5d, 0xfe, 0x80, 0x9b, 0xbe, 0x2f, 0xe3, 0x7e, 0xf5, 0x8a, 0xa4, 0xc2, ++ 0x31, 0xb1, 0xd6, 0x7d, 0xea, 0x17, 0x4e, 0x81, 0xf8, 0x73, 0x5d, 0xed, ++ 0xcc, 0x29, 0x10, 0x6f, 0x93, 0xb9, 0xdd, 0x08, 0xbf, 0xac, 0x05, 0xf6, ++ 0x26, 0x5c, 0x81, 0x1e, 0xeb, 0x7e, 0xad, 0x06, 0x4e, 0xd7, 0xfb, 0x6b, ++ 0x6b, 0x30, 0x7e, 0x4d, 0x6c, 0x41, 0xe2, 0xd1, 0x9f, 0xf7, 0x25, 0xcc, ++ 0x2e, 0xfa, 0x86, 0xb0, 0x78, 0x8b, 0xd6, 0x4e, 0x91, 0xfd, 0x1e, 0x88, ++ 0x7f, 0x2a, 0xfc, 0x3c, 0xb2, 0x2c, 0xf9, 0x57, 0x66, 0xe6, 0x41, 0x1c, ++ 0x23, 0x25, 0x27, 0xa8, 0xc3, 0xdf, 0x43, 0x6e, 0x66, 0xd7, 0xad, 0x49, ++ 0x3b, 0xe0, 0x81, 0x7c, 0x52, 0x2b, 0xed, 0x1f, 0xe2, 0x31, 0xb6, 0x74, ++ 0xe9, 0xac, 0x71, 0x9f, 0x92, 0x95, 0x73, 0x84, 0x49, 0x32, 0xcc, 0x47, ++ 0x4e, 0x09, 0x13, 0x8c, 0x67, 0x66, 0xd3, 0xf7, 0x3a, 0x7c, 0x2b, 0x29, ++ 0x14, 0xce, 0xf3, 0xf8, 0x9b, 0x92, 0xcd, 0x8d, 0xfb, 0x45, 0x12, 0x61, ++ 0x76, 0x9a, 0x36, 0x7f, 0xfa, 0x06, 0xd7, 0xb3, 0x07, 0xf8, 0xba, 0xb4, ++ 0x1c, 0xe2, 0xb8, 0x29, 0x60, 0x87, 0x59, 0xd0, 0x1f, 0x5a, 0xcf, 0xe3, ++ 0x94, 0xbf, 0xac, 0x2d, 0xe2, 0x78, 0x90, 0x70, 0x1d, 0xb3, 0x26, 0xb1, ++ 0xfa, 0x4a, 0x22, 0x83, 0xdb, 0x0e, 0x71, 0x6b, 0x11, 0xd6, 0xd5, 0x08, ++ 0x96, 0x5d, 0x70, 0xc3, 0x8e, 0x88, 0x57, 0x93, 0xe1, 0xef, 0x8f, 0x26, ++ 0x11, 0x15, 0x7f, 0xa7, 0x6f, 0x00, 0x89, 0xd4, 0xe3, 0x3d, 0x26, 0x53, ++ 0xbb, 0xee, 0x81, 0xf7, 0xbe, 0x04, 0xff, 0x16, 0xe0, 0x83, 0x2f, 0x07, ++ 0x77, 0x7e, 0x28, 0x40, 0x1c, 0xba, 0xc8, 0x7f, 0x09, 0xac, 0xbf, 0x8d, ++ 0x62, 0x30, 0x47, 0xa5, 0xf5, 0x7f, 0x25, 0xf6, 0xe6, 0x40, 0x3d, 0xf8, ++ 0x7d, 0xaf, 0xf7, 0x93, 0xd9, 0x73, 0x38, 0xe4, 0x2d, 0xfb, 0x75, 0xfb, ++ 0x52, 0xec, 0x5e, 0x4e, 0x55, 0x1f, 0xd7, 0x33, 0x97, 0x87, 0x2f, 0x95, ++ 0x4c, 0xfb, 0x35, 0x7f, 0xbe, 0x44, 0xff, 0xbd, 0x39, 0xc1, 0xb7, 0x0b, ++ 0xe0, 0x48, 0xf9, 0x58, 0xc0, 0x7d, 0x98, 0x3a, 0x3b, 0xbb, 0xd7, 0xa7, ++ 0xce, 0x75, 0x73, 0x22, 0xac, 0xdf, 0x87, 0x39, 0xbd, 0x90, 0xfe, 0xc0, ++ 0x3f, 0x1d, 0xcc, 0x8e, 0x39, 0x2b, 0xa9, 0x89, 0xc9, 0x18, 0xdf, 0xcc, ++ 0xca, 0x7d, 0xc5, 0x30, 0xbe, 0xd7, 0x50, 0x96, 0xb8, 0xff, 0xb6, 0x89, ++ 0xf2, 0xa3, 0xa4, 0xbb, 0x97, 0x75, 0x94, 0xe4, 0xb3, 0x00, 0xbf, 0x8c, ++ 0x6e, 0xa0, 0xef, 0xf5, 0xf4, 0x8b, 0x11, 0x57, 0x4b, 0x76, 0xe2, 0xf5, ++ 0xb7, 0x31, 0xf7, 0x61, 0x34, 0xf8, 0xe8, 0xb8, 0x04, 0xf0, 0x27, 0x9e, ++ 0x2b, 0x64, 0xeb, 0xab, 0x89, 0x0f, 0xf6, 0x08, 0x0c, 0xfe, 0xa0, 0x8b, ++ 0xfb, 0x5b, 0x24, 0x28, 0x02, 0x3d, 0xe7, 0x68, 0xf7, 0x05, 0x4b, 0x2b, ++ 0x58, 0x59, 0xfb, 0xbd, 0x08, 0xa0, 0x22, 0x85, 0xe3, 0x03, 0x6d, 0x7f, ++ 0x81, 0xac, 0x60, 0x65, 0xbe, 0x4f, 0x19, 0x98, 0xc7, 0xf6, 0x21, 0xcd, ++ 0xf0, 0xcc, 0x69, 0x7f, 0xa0, 0x13, 0xe2, 0xfa, 0x73, 0xda, 0x07, 0xcf, ++ 0x87, 0xfd, 0xa9, 0x39, 0xce, 0x31, 0x7f, 0x82, 0xe7, 0x1e, 0xb9, 0xf7, ++ 0x40, 0x02, 0xd8, 0x81, 0x77, 0x0b, 0x78, 0xfe, 0xe3, 0xc7, 0xbf, 0x7b, ++ 0x45, 0x4e, 0xa0, 0xcf, 0x9d, 0xef, 0x6c, 0xc4, 0xf3, 0xc6, 0xa7, 0xb9, ++ 0xdc, 0xdd, 0x4e, 0x7a, 0xf1, 0x1e, 0x76, 0x3f, 0xf1, 0xf0, 0x7d, 0xf2, ++ 0x10, 0xbe, 0x9f, 0x07, 0x3f, 0x30, 0x87, 0xe5, 0xb0, 0x0c, 0x7e, 0xfa, ++ 0xdc, 0x48, 0xe8, 0x47, 0xd7, 0xd0, 0xd2, 0x6d, 0xaf, 0x84, 0xae, 0x01, ++ 0xb3, 0xed, 0xf6, 0x8e, 0xde, 0xdf, 0x80, 0x1a, 0xf0, 0x87, 0x3d, 0x85, ++ 0xb8, 0x07, 0xa0, 0xb5, 0x6b, 0xf3, 0xbe, 0xca, 0xca, 0xac, 0x5d, 0x14, ++ 0x0f, 0x36, 0x6e, 0x8f, 0xda, 0x70, 0x5e, 0xd1, 0x79, 0xdb, 0x10, 0x0f, ++ 0x1f, 0xf4, 0xe5, 0x8d, 0x07, 0x91, 0x1e, 0x7d, 0x78, 0xe2, 0xf7, 0x2a, ++ 0x69, 0x78, 0xe9, 0x9b, 0x77, 0xe2, 0xcd, 0x57, 0x43, 0x9c, 0x37, 0x9e, ++ 0x3e, 0x9b, 0xe3, 0xcc, 0xfa, 0x13, 0xdb, 0xfc, 0x60, 0x70, 0x99, 0xf1, ++ 0xf4, 0x39, 0x7c, 0xa2, 0x76, 0xe4, 0xe7, 0x6e, 0x9f, 0x3d, 0x91, 0xea, ++ 0xb7, 0x8f, 0xdd, 0x3e, 0x07, 0x3c, 0x2b, 0x6d, 0xbd, 0x19, 0xd2, 0x08, ++ 0x94, 0x17, 0x37, 0x94, 0xab, 0x45, 0xff, 0xf0, 0x54, 0x8a, 0x87, 0xd3, ++ 0xc3, 0xfc, 0x97, 0x0c, 0x04, 0x7c, 0x74, 0x0e, 0xb8, 0x28, 0x3d, 0xfa, ++ 0xa1, 0x9d, 0xe9, 0x01, 0x92, 0x97, 0x81, 0xf3, 0xd1, 0xee, 0x7d, 0x3f, ++ 0x78, 0xef, 0x71, 0x17, 0xd8, 0x9d, 0xf5, 0x3b, 0xdf, 0xcb, 0x80, 0x67, ++ 0x95, 0xd8, 0xb5, 0xf6, 0x16, 0x8c, 0x6f, 0x8a, 0xe8, 0x0f, 0x9d, 0x6d, ++ 0xbd, 0xe4, 0xbc, 0xe7, 0xc3, 0x3e, 0x84, 0xb8, 0x13, 0x5d, 0xff, 0x46, ++ 0x27, 0x6a, 0x7c, 0xc8, 0xe6, 0x77, 0x07, 0x3f, 0x5f, 0x73, 0x47, 0x6b, ++ 0x02, 0x9e, 0xaf, 0xb9, 0x63, 0xa9, 0x68, 0xb8, 0xb7, 0xf9, 0x8e, 0xa5, ++ 0x2c, 0xef, 0x8e, 0x48, 0x9d, 0xe3, 0x6e, 0x32, 0xd8, 0xeb, 0x2b, 0xe2, ++ 0xf6, 0x03, 0x71, 0x00, 0x73, 0x3f, 0xf3, 0x97, 0x16, 0x90, 0x8f, 0x07, ++ 0xc0, 0x3e, 0xab, 0x67, 0x2a, 0xc6, 0x05, 0x9e, 0x62, 0xfc, 0x35, 0x7f, ++ 0xba, 0x4f, 0x84, 0x7c, 0xe4, 0xc9, 0x2b, 0x05, 0x8c, 0xb7, 0x4c, 0x3a, ++ 0xaa, 0xb6, 0x75, 0xd1, 0xf2, 0xfc, 0x50, 0x12, 0xfe, 0xde, 0xd1, 0xfc, ++ 0x7b, 0x97, 0xe4, 0xc2, 0x3d, 0x04, 0xd5, 0x9d, 0x2c, 0xbe, 0x37, 0x48, ++ 0x5c, 0x9c, 0xf3, 0x33, 0x88, 0x9f, 0x1c, 0x60, 0xeb, 0x38, 0x94, 0x17, ++ 0x83, 0x7c, 0x3b, 0x7d, 0xaa, 0x53, 0x17, 0xef, 0xef, 0x96, 0x6b, 0x72, ++ 0xe0, 0xde, 0xbd, 0xe0, 0x6d, 0x4e, 0x1f, 0xf0, 0x4f, 0xf1, 0x4d, 0xbe, ++ 0x0f, 0xf0, 0xf7, 0x12, 0x79, 0x1c, 0x42, 0x5b, 0x57, 0x77, 0x35, 0x16, ++ 0x63, 0x1e, 0x6b, 0xf1, 0x5c, 0x75, 0x22, 0xd0, 0xbd, 0x38, 0x6c, 0xc7, ++ 0xdf, 0x1f, 0x2c, 0xb6, 0x11, 0xc9, 0x41, 0xf5, 0x58, 0xb1, 0x44, 0x6c, ++ 0xf0, 0x1c, 0xa4, 0x10, 0xc9, 0x0e, 0x4f, 0x07, 0xb1, 0xc1, 0x33, 0x7f, ++ 0x39, 0xbb, 0x27, 0xbb, 0xa4, 0xf1, 0x7a, 0xb4, 0x0f, 0xdc, 0x13, 0x8b, ++ 0x14, 0xb8, 0xff, 0xb6, 0xb8, 0xfd, 0xd9, 0x2f, 0xa0, 0x7d, 0xa9, 0x14, ++ 0xd9, 0xcf, 0xce, 0xb5, 0x30, 0xfc, 0x14, 0xb7, 0x1f, 0xfa, 0x1a, 0xf8, ++ 0x67, 0xa1, 0xaf, 0x08, 0xf3, 0x0e, 0xbf, 0xb3, 0x45, 0x31, 0xf8, 0x7f, ++ 0x63, 0xc3, 0xc6, 0xf2, 0xe5, 0x6d, 0xc6, 0x72, 0x4e, 0xc4, 0x58, 0xce, ++ 0xed, 0x30, 0x96, 0xb7, 0xc2, 0x1d, 0x67, 0x3a, 0x3b, 0xe2, 0xc0, 0x5e, ++ 0x2b, 0xae, 0x13, 0x15, 0xa7, 0xd8, 0x39, 0xbd, 0x97, 0x04, 0x58, 0x9b, ++ 0x20, 0x1e, 0x6c, 0x45, 0x79, 0x9a, 0x56, 0xd1, 0x9e, 0x0f, 0xfb, 0xd1, ++ 0xa7, 0x9e, 0x77, 0x59, 0xe0, 0xfb, 0x9e, 0xbf, 0x30, 0xbf, 0xb7, 0x77, ++ 0xab, 0x1d, 0xef, 0x7b, 0xdb, 0xff, 0x7b, 0x07, 0x71, 0x40, 0x5e, 0xe1, ++ 0x0b, 0xf6, 0x8d, 0xf0, 0xfd, 0x94, 0x23, 0x9c, 0x0f, 0x71, 0x38, 0x5a, ++ 0x9f, 0xfd, 0xce, 0x56, 0x51, 0x78, 0x0c, 0xf8, 0x6f, 0x2f, 0x5e, 0xa6, ++ 0xf9, 0xe9, 0xa1, 0x71, 0x30, 0xaf, 0x17, 0xff, 0xca, 0xf2, 0x64, 0x7a, ++ 0xb7, 0x5a, 0xf1, 0xf7, 0x53, 0x4e, 0xed, 0x7e, 0xf6, 0x79, 0xd8, 0x17, ++ 0x3b, 0xb5, 0x75, 0x28, 0xda, 0x59, 0x2f, 0x09, 0x41, 0x0b, 0xf4, 0x1b, ++ 0x5c, 0xc5, 0xe8, 0x6f, 0xe6, 0xd3, 0x8a, 0x2d, 0x46, 0xbf, 0xf8, 0x9e, ++ 0x44, 0xa6, 0x6f, 0x7a, 0x04, 0x86, 0xef, 0x4b, 0x1a, 0x8d, 0xf3, 0xbe, ++ 0x34, 0x64, 0x2c, 0xff, 0x3c, 0x91, 0xf9, 0x53, 0xf3, 0x88, 0xee, 0x7d, ++ 0x26, 0xec, 0xdf, 0xab, 0xf5, 0x69, 0xb0, 0xae, 0x3e, 0x1d, 0xfb, 0xbe, ++ 0xe1, 0xfb, 0xb9, 0x5c, 0x3c, 0xf7, 0x9c, 0xa2, 0xf1, 0xad, 0xc8, 0xef, ++ 0x67, 0x23, 0xaa, 0xee, 0xfc, 0xd2, 0x9e, 0xe8, 0xfe, 0xdd, 0x5d, 0x43, ++ 0x21, 0xaf, 0x02, 0x70, 0x31, 0x22, 0xfa, 0xbe, 0xc2, 0x34, 0xae, 0xd6, ++ 0x7f, 0x51, 0x22, 0xdb, 0x87, 0x4f, 0xe1, 0xfb, 0x33, 0xbd, 0x6f, 0x88, ++ 0x88, 0x9f, 0x93, 0xa6, 0xdf, 0x2d, 0xec, 0xb3, 0xeb, 0x6a, 0x6b, 0x06, ++ 0x4f, 0xd7, 0xad, 0x43, 0x25, 0x8d, 0xfb, 0x53, 0x8b, 0xc1, 0x3f, 0x6a, ++ 0xda, 0x9f, 0x3a, 0x4f, 0xb7, 0xbe, 0x54, 0x6e, 0x3d, 0x98, 0x7a, 0x2b, ++ 0xe6, 0x25, 0x49, 0xf8, 0xbb, 0x4c, 0x95, 0x73, 0x9e, 0x79, 0x68, 0x72, ++ 0x0a, 0xbc, 0x17, 0xc3, 0x00, 0x2f, 0x7c, 0x87, 0xb8, 0x57, 0x77, 0xf8, ++ 0x37, 0x6e, 0xa8, 0x47, 0xed, 0xdd, 0xf1, 0xa2, 0x0e, 0xef, 0xa5, 0x8d, ++ 0x77, 0x0f, 0x9e, 0xae, 0x93, 0xd3, 0xbf, 0x95, 0x2f, 0x35, 0x79, 0xaa, ++ 0xe4, 0xf6, 0xc9, 0xae, 0x89, 0x9d, 0x85, 0x90, 0x27, 0x5e, 0xd1, 0xc8, ++ 0x7e, 0xbf, 0xa9, 0x22, 0xfc, 0xa3, 0x1b, 0xe1, 0xf7, 0x17, 0x49, 0x13, ++ 0x3b, 0x67, 0x9a, 0x2f, 0x91, 0x22, 0x91, 0xca, 0x4f, 0xe5, 0xf6, 0x1f, ++ 0xfd, 0x10, 0x7e, 0x8f, 0x2b, 0xf0, 0xe4, 0x04, 0x2f, 0xc0, 0x43, 0xbb, ++ 0xb8, 0x09, 0xde, 0x57, 0xb4, 0x7c, 0x8a, 0xe7, 0x09, 0x56, 0x9b, 0x7e, ++ 0x47, 0x40, 0x7b, 0xee, 0xe3, 0xf4, 0xa5, 0xf5, 0x23, 0x16, 0x5a, 0x7f, ++ 0xf5, 0xcd, 0xce, 0x32, 0xd0, 0x4f, 0xb4, 0xdf, 0x57, 0xa0, 0x7c, 0x20, ++ 0x6b, 0x23, 0xde, 0x6f, 0xe2, 0x3e, 0xc1, 0xe2, 0xb4, 0xf4, 0xfd, 0xfb, ++ 0xf0, 0x93, 0x28, 0x27, 0x0a, 0x82, 0x6f, 0xde, 0x4a, 0x9b, 0x9e, 0x22, ++ 0xe1, 0x77, 0xaf, 0xc9, 0x84, 0x79, 0x1b, 0xf9, 0x8c, 0xf2, 0xad, 0x00, ++ 0x76, 0x57, 0xef, 0x66, 0x01, 0x7f, 0xd7, 0x96, 0x5a, 0x5a, 0xf9, 0x37, ++ 0x80, 0x49, 0xed, 0x5b, 0x86, 0x79, 0xb7, 0xf4, 0xfb, 0x1d, 0xb1, 0xce, ++ 0x3b, 0x2f, 0x0a, 0x19, 0xfb, 0x31, 0xd3, 0xff, 0xf7, 0x9c, 0x7f, 0xe9, ++ 0x5f, 0x96, 0x9e, 0x8f, 0xcc, 0xf5, 0x06, 0xcc, 0x0a, 0xe2, 0xb9, 0xc4, ++ 0xca, 0xa5, 0x54, 0xdf, 0xe9, 0xec, 0xfc, 0xca, 0xa3, 0x0d, 0x78, 0x9f, ++ 0xa3, 0x79, 0x1c, 0x0c, 0xc2, 0xe9, 0xf2, 0x0d, 0x60, 0xbd, 0x54, 0x51, ++ 0xbe, 0xed, 0xdc, 0x6e, 0x20, 0x82, 0x2d, 0x9f, 0xe7, 0xcd, 0x8e, 0x64, ++ 0x65, 0xbc, 0xb7, 0x10, 0xf8, 0x95, 0x32, 0x4a, 0xc5, 0x65, 0x64, 0xba, ++ 0x0a, 0xf8, 0xbe, 0x81, 0xcc, 0x84, 0xe7, 0x4b, 0x42, 0xe4, 0x21, 0x51, ++ 0x64, 0x7a, 0x02, 0xe3, 0x40, 0xdb, 0x12, 0x50, 0x4f, 0x74, 0x7b, 0xba, ++ 0x9e, 0x79, 0x02, 0xf8, 0xab, 0x65, 0x2c, 0xc6, 0x9f, 0x86, 0xf0, 0xf3, ++ 0x9e, 0xdd, 0x6a, 0x04, 0xef, 0x79, 0xec, 0xe1, 0xf1, 0xc9, 0x6e, 0x0f, ++ 0x2b, 0x97, 0xb7, 0xdb, 0x31, 0x0f, 0xe6, 0xd4, 0x69, 0x05, 0xf5, 0xe8, ++ 0xb2, 0xf0, 0x41, 0x37, 0xd0, 0xa3, 0xfb, 0x79, 0xbb, 0x05, 0x7e, 0x97, ++ 0xf4, 0xd4, 0xf6, 0x01, 0x05, 0x90, 0x27, 0xd9, 0x1d, 0x66, 0xf7, 0xff, ++ 0x9e, 0x0c, 0x0f, 0xc0, 0xdf, 0x7f, 0x8d, 0xb7, 0x6e, 0x99, 0xf5, 0x81, ++ 0xb6, 0x4e, 0x1e, 0x81, 0x7f, 0xc2, 0x7a, 0x9a, 0xe8, 0xfb, 0x06, 0xd6, ++ 0x5b, 0xb2, 0x82, 0xe5, 0x91, 0x0e, 0x1a, 0x50, 0x93, 0x13, 0xeb, 0xf7, ++ 0x24, 0xb4, 0x76, 0x29, 0x4a, 0x4d, 0x0e, 0xf8, 0x29, 0xff, 0x0b, 0xc9, ++ 0x35, 0x40, 0x02, 0x00, 0x80, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xdd, 0x7d, 0x0d, 0x78, 0x54, 0xd5, ++ 0x99, 0xf0, 0xb9, 0x73, 0xef, 0xfc, 0x65, 0x66, 0x92, 0x99, 0xc9, 0x24, ++ 0x99, 0x84, 0xfc, 0x4c, 0x42, 0x08, 0x01, 0x02, 0x4e, 0x42, 0x88, 0x48, ++ 0x51, 0x27, 0x21, 0x60, 0xc0, 0x54, 0x07, 0x8a, 0x1a, 0x7f, 0x8a, 0xc3, ++ 0x7f, 0x80, 0xfc, 0x89, 0xb6, 0x1b, 0x95, 0x6e, 0x26, 0x26, 0x62, 0x42, ++ 0x51, 0xc3, 0x1a, 0x11, 0x10, 0x70, 0x40, 0x51, 0xba, 0x6a, 0x1b, 0x5c, ++ 0xd4, 0x68, 0x83, 0xcf, 0x80, 0x68, 0xb1, 0xd5, 0x7e, 0xb1, 0x76, 0xbb, ++ 0xfe, 0xec, 0xb2, 0x23, 0xb0, 0x88, 0x56, 0x20, 0xa2, 0xa5, 0xb4, 0xdb, ++ 0x96, 0xef, 0x7d, 0xdf, 0x73, 0xee, 0xcc, 0xdc, 0x49, 0xa2, 0x74, 0x77, ++ 0xbf, 0xee, 0xf3, 0x7c, 0xe9, 0x43, 0xaf, 0xe7, 0x9e, 0x73, 0xcf, 0xcf, ++ 0xfb, 0xbe, 0xe7, 0xfd, 0x3f, 0x67, 0x86, 0xbe, 0x6b, 0xf5, 0xee, 0xce, ++ 0x67, 0xf0, 0x17, 0xcc, 0x57, 0x5c, 0x8c, 0x9d, 0x0b, 0xb8, 0xbd, 0x1b, ++ 0xa0, 0xbc, 0x58, 0x82, 0x57, 0x57, 0x30, 0x66, 0x71, 0xfa, 0x8d, 0xf6, ++ 0x34, 0xc6, 0x6c, 0xe5, 0x8c, 0xf9, 0xe0, 0x9f, 0xf3, 0x88, 0xbc, 0x5b, ++ 0x86, 0xfa, 0xe3, 0xb2, 0xf7, 0xfb, 0xf6, 0xb1, 0x8c, 0x2d, 0x63, 0x7e, ++ 0x03, 0xc3, 0x67, 0x79, 0xc0, 0xc0, 0x0a, 0xe0, 0x9b, 0x4e, 0x68, 0x9c, ++ 0xc9, 0xd8, 0x52, 0x85, 0x85, 0x15, 0x27, 0x3c, 0x17, 0xfa, 0x3e, 0x90, ++ 0xa6, 0x50, 0x99, 0x31, 0xf8, 0x7e, 0xe9, 0x76, 0x29, 0xd4, 0x01, 0xdf, ++ 0x2f, 0xdb, 0x68, 0x64, 0xcc, 0xc4, 0xe8, 0xef, 0x22, 0xfc, 0x5b, 0xd1, ++ 0x0b, 0xe5, 0xe2, 0x58, 0x79, 0x15, 0x0b, 0x19, 0x98, 0x0c, 0xff, 0xb1, ++ 0x3d, 0xae, 0x1d, 0xf4, 0xbf, 0x4a, 0x09, 0x1f, 0x94, 0x92, 0x19, 0x5b, ++ 0x6d, 0x62, 0x61, 0x0b, 0xf4, 0xbb, 0xfa, 0x29, 0xed, 0x77, 0x6b, 0x58, ++ 0x98, 0xe6, 0xd3, 0xf0, 0xdc, 0x45, 0x63, 0x7c, 0xff, 0xb0, 0x3e, 0xc6, ++ 0x60, 0x6a, 0xbf, 0x63, 0xea, 0xba, 0x7c, 0x1e, 0xfb, 0x34, 0xc6, 0x5c, ++ 0x06, 0x28, 0xc3, 0xba, 0x87, 0xde, 0xd1, 0x87, 0x10, 0x0e, 0xff, 0x21, ++ 0xfb, 0x69, 0x5d, 0x6b, 0x58, 0x80, 0xfa, 0xb9, 0xa5, 0xb5, 0x8a, 0x1d, ++ 0x4f, 0x65, 0xac, 0xf9, 0xee, 0xd6, 0xcc, 0x65, 0xf0, 0x3c, 0xdb, 0x7a, ++ 0x4f, 0xe6, 0xb2, 0xa9, 0x50, 0x8f, 0xf3, 0x80, 0xf1, 0xad, 0x8c, 0x7f, ++ 0xcf, 0x60, 0x5d, 0x7b, 0x00, 0x66, 0x6b, 0xaa, 0x59, 0x38, 0x07, 0xe6, ++ 0xb7, 0x1c, 0xd6, 0x9b, 0x54, 0x06, 0xe5, 0x01, 0x29, 0x3c, 0x19, 0xcb, ++ 0x26, 0x16, 0x4c, 0x2e, 0xe3, 0xef, 0x53, 0xca, 0xf8, 0x7a, 0x7d, 0x71, ++ 0xf3, 0xab, 0x67, 0x3d, 0x34, 0x5e, 0xfd, 0x76, 0xed, 0x7b, 0xf6, 0xeb, ++ 0x54, 0x82, 0x67, 0x03, 0x1b, 0xa4, 0x7a, 0xf6, 0x54, 0x5c, 0x3d, 0xc0, ++ 0xa3, 0x41, 0xc0, 0xa1, 0xe1, 0x39, 0x78, 0x1f, 0x07, 0x87, 0x19, 0xcf, ++ 0x49, 0x41, 0xdb, 0x65, 0x58, 0x0a, 0x75, 0xa4, 0xc3, 0xfc, 0x9a, 0x4e, ++ 0x31, 0xb6, 0x01, 0x4a, 0x4d, 0xfb, 0x2f, 0x1a, 0x35, 0xfd, 0xb3, 0x1e, ++ 0xc6, 0x00, 0x0e, 0x19, 0x49, 0x8c, 0x99, 0x01, 0x5f, 0x8f, 0x4a, 0xac, ++ 0xae, 0xaf, 0x84, 0xbe, 0x9b, 0x30, 0x7f, 0x32, 0xb4, 0xc1, 0xbf, 0xab, ++ 0xb1, 0xdc, 0x4e, 0xed, 0x8e, 0x0a, 0xf8, 0x3d, 0x7a, 0xc3, 0x8a, 0xcc, ++ 0x00, 0xb4, 0x7b, 0xd8, 0x01, 0xe5, 0x2c, 0x01, 0xe0, 0xe9, 0x30, 0x86, ++ 0x0e, 0x07, 0xa7, 0x72, 0xd8, 0x04, 0xe3, 0x24, 0x4d, 0x8d, 0x96, 0xa9, ++ 0xbe, 0xe2, 0x3e, 0x5e, 0x9e, 0x6f, 0x2f, 0xae, 0xd9, 0x92, 0xcd, 0xd8, ++ 0x66, 0x7d, 0x20, 0xd3, 0x0e, 0x40, 0x5c, 0x2a, 0xfb, 0xdf, 0xd4, 0x01, ++ 0xfc, 0x9e, 0x71, 0x06, 0x6e, 0x40, 0xbc, 0x2c, 0xd5, 0xf9, 0x72, 0x15, ++ 0x5c, 0x2f, 0xf3, 0x15, 0xf9, 0x61, 0x1e, 0xac, 0x95, 0xc3, 0xe1, 0xb1, ++ 0xb2, 0x96, 0x09, 0x2d, 0x25, 0xb1, 0x79, 0xc5, 0xe6, 0xc7, 0xf1, 0xbb, ++ 0x59, 0xea, 0x0b, 0xeb, 0x80, 0xce, 0x82, 0xaf, 0x48, 0xde, 0x3d, 0x1e, ++ 0xa4, 0xdb, 0x21, 0x7d, 0xc0, 0x1a, 0x6b, 0xd7, 0x6c, 0x97, 0x68, 0x1d, ++ 0x29, 0x87, 0x22, 0x6f, 0x8e, 0x41, 0xbc, 0xbf, 0x28, 0xb1, 0xdd, 0xd0, ++ 0x6e, 0xab, 0xf4, 0xf1, 0x9b, 0x63, 0xe0, 0xbb, 0xad, 0x73, 0x3d, 0xac, ++ 0x03, 0xca, 0x6e, 0xc0, 0x93, 0x5c, 0x86, 0xef, 0x59, 0xa7, 0x04, 0x70, ++ 0x29, 0xdf, 0x3f, 0xff, 0x8e, 0x37, 0x10, 0xcf, 0xe5, 0x49, 0xde, 0x71, ++ 0xf0, 0x68, 0xdc, 0x5f, 0x29, 0x37, 0x5a, 0x69, 0xfd, 0xb7, 0xfb, 0x61, ++ 0x3e, 0x19, 0x96, 0x96, 0x5d, 0x3a, 0xa8, 0xcf, 0xb8, 0xbd, 0xb8, 0x0c, ++ 0xe9, 0x1b, 0xd6, 0x7d, 0xfb, 0x02, 0x78, 0x7f, 0x97, 0xdd, 0x43, 0xe3, ++ 0x65, 0x5a, 0x39, 0xde, 0xdd, 0xf7, 0x05, 0xf3, 0xd7, 0x96, 0xe0, 0xf8, ++ 0xfe, 0x3b, 0xde, 0x80, 0xf1, 0x86, 0x26, 0x27, 0x79, 0x71, 0xfc, 0x0c, ++ 0x80, 0x95, 0xcd, 0x49, 0xcf, 0x2e, 0x33, 0xb6, 0x63, 0xed, 0x12, 0xb6, ++ 0x7b, 0x34, 0x99, 0xf7, 0x9f, 0xa6, 0x93, 0x6f, 0x9f, 0x8f, 0xe5, 0x32, ++ 0x5e, 0x76, 0xae, 0x93, 0x7c, 0xbb, 0x89, 0xf8, 0x36, 0xd1, 0xba, 0x33, ++ 0x8c, 0xac, 0x06, 0xe7, 0x89, 0xef, 0x43, 0x25, 0xb4, 0x65, 0x7c, 0xfb, ++ 0xa8, 0x3e, 0xc4, 0xf1, 0x3b, 0xab, 0xa5, 0x14, 0xfb, 0xcb, 0x18, 0xcb, ++ 0x9f, 0x2e, 0x43, 0x38, 0x1b, 0xfb, 0x79, 0x5b, 0xc5, 0xf7, 0x40, 0xa6, ++ 0x8e, 0xa5, 0xe3, 0x7c, 0xe1, 0xbf, 0x61, 0x3e, 0x77, 0xed, 0xab, 0xcc, ++ 0x70, 0xc2, 0xf7, 0x6f, 0x7f, 0x6e, 0x52, 0x74, 0x29, 0xf0, 0x74, 0x33, ++ 0x36, 0x88, 0xed, 0x94, 0xb0, 0x95, 0xe1, 0xb3, 0xb0, 0x98, 0xb7, 0x37, ++ 0x89, 0xf6, 0xa5, 0xb3, 0x32, 0x70, 0x33, 0xb8, 0x72, 0xb5, 0xed, 0xce, ++ 0xea, 0x7d, 0x29, 0x53, 0x01, 0x2e, 0xc1, 0x77, 0x65, 0x86, 0xf8, 0xf8, ++ 0xca, 0xea, 0x4b, 0x71, 0x40, 0xbb, 0x6f, 0x19, 0xf8, 0x3a, 0x12, 0xf1, ++ 0xb8, 0x13, 0xf1, 0x03, 0xeb, 0x69, 0xbe, 0x00, 0x33, 0x4f, 0x8d, 0xc3, ++ 0x5b, 0xdd, 0x79, 0x03, 0xf6, 0xd7, 0x7c, 0x41, 0x61, 0xa1, 0xa9, 0xb1, ++ 0xf7, 0x9f, 0xb7, 0x99, 0x58, 0xa8, 0x28, 0x56, 0x6e, 0xa8, 0x3f, 0x34, ++ 0x07, 0xdb, 0x35, 0xb2, 0xc1, 0xf5, 0x48, 0x57, 0x8d, 0x7d, 0x16, 0x16, ++ 0x8a, 0xa3, 0xf7, 0x6f, 0x25, 0x8d, 0x3c, 0xae, 0x4a, 0xdf, 0xcd, 0x17, ++ 0x74, 0x2c, 0x98, 0x4a, 0xe4, 0x9b, 0xed, 0xb7, 0x21, 0x7c, 0x86, 0xd6, ++ 0x2f, 0xc7, 0xf9, 0x1f, 0x90, 0xd8, 0x1e, 0x86, 0xf5, 0x06, 0x16, 0x8c, ++ 0x1b, 0xbf, 0xf9, 0x82, 0x53, 0x5b, 0x8e, 0xce, 0x33, 0x9d, 0xfa, 0x89, ++ 0xb5, 0x63, 0xda, 0x76, 0xfd, 0xbf, 0xa7, 0x76, 0x6c, 0x7a, 0x24, 0x19, ++ 0xc7, 0x39, 0x63, 0x8f, 0x24, 0x3b, 0xc5, 0xfa, 0xf0, 0xbb, 0x2c, 0x99, ++ 0xb5, 0x20, 0x5e, 0xce, 0x86, 0x74, 0x41, 0x3d, 0xec, 0xe3, 0x33, 0x1e, ++ 0x5e, 0x7f, 0x96, 0xb1, 0x9a, 0x3e, 0x6b, 0xac, 0xbd, 0xda, 0xdf, 0x99, ++ 0x3a, 0x03, 0x0b, 0x13, 0xdc, 0x87, 0xa8, 0x5f, 0x84, 0x4b, 0x10, 0x78, ++ 0xdb, 0xb6, 0x81, 0x2f, 0x0c, 0x1e, 0x28, 0x37, 0x0c, 0x1c, 0x24, 0xb8, ++ 0xa8, 0xf4, 0x10, 0x0f, 0x9f, 0x60, 0x1c, 0xdf, 0x48, 0xef, 0x18, 0x0c, ++ 0xeb, 0x60, 0x4f, 0xff, 0xda, 0xbe, 0xaa, 0xab, 0xc4, 0x0c, 0xa8, 0x38, ++ 0xa4, 0xee, 0xdf, 0x35, 0x5d, 0xbe, 0x99, 0x50, 0x2f, 0xeb, 0x34, 0xfb, ++ 0xd9, 0x52, 0x1e, 0xdd, 0xdf, 0xc4, 0x56, 0x1e, 0xd5, 0xc9, 0x82, 0x1f, ++ 0x34, 0x74, 0x55, 0xcf, 0x8c, 0x2f, 0xf3, 0xf6, 0xb1, 0xef, 0x1b, 0x6b, ++ 0xaa, 0x61, 0xff, 0x97, 0x97, 0xf0, 0xef, 0x8f, 0xda, 0x9b, 0x8e, 0xdc, ++ 0xa7, 0xc4, 0xf8, 0x11, 0xac, 0x23, 0x17, 0xe1, 0x12, 0x2d, 0x9b, 0x12, ++ 0xca, 0x56, 0x28, 0x4f, 0x8e, 0x2b, 0xdb, 0x13, 0xea, 0x5d, 0x09, 0xf5, ++ 0xee, 0x84, 0x72, 0x36, 0x6f, 0xff, 0xb9, 0x2d, 0x9c, 0x2b, 0x7b, 0x19, ++ 0xfb, 0xd4, 0xbe, 0xb6, 0x46, 0x01, 0xfe, 0xf2, 0x79, 0x66, 0x78, 0x91, ++ 0x04, 0xe5, 0x8d, 0x1d, 0x77, 0xd5, 0x54, 0x03, 0x9f, 0x6b, 0x2c, 0x1f, ++ 0xf4, 0xc9, 0xc8, 0x3f, 0x07, 0x24, 0xaf, 0xc4, 0x62, 0xf0, 0x6b, 0xf2, ++ 0x32, 0x5f, 0x08, 0xe0, 0x67, 0xf5, 0x46, 0x0c, 0x4b, 0x4b, 0x10, 0x0e, ++ 0x83, 0x6f, 0xe2, 0xfe, 0x6f, 0xe8, 0x97, 0xec, 0x12, 0xd0, 0xb9, 0xb5, ++ 0x6f, 0x5f, 0x98, 0xca, 0xf8, 0x9d, 0x27, 0xee, 0xbb, 0x3e, 0x89, 0xbe, ++ 0x6b, 0xe8, 0xfb, 0x98, 0xbe, 0x1b, 0xb5, 0xff, 0x62, 0x1d, 0xed, 0xe3, ++ 0x0d, 0xc5, 0xc7, 0xa8, 0x1d, 0x00, 0xc0, 0x7e, 0x02, 0xf0, 0x74, 0x13, ++ 0x93, 0x58, 0x0a, 0x80, 0x34, 0x5f, 0x09, 0xfc, 0x11, 0xf9, 0x64, 0x63, ++ 0xdf, 0x27, 0x5c, 0xee, 0xb2, 0x21, 0x03, 0x5f, 0x1f, 0xe7, 0x83, 0x67, ++ 0x32, 0x7d, 0xaf, 0x13, 0x1f, 0x3c, 0x20, 0xd9, 0x71, 0xdf, 0x45, 0xe9, ++ 0x0e, 0xfb, 0xb5, 0xc6, 0xe8, 0x5d, 0x6d, 0xff, 0xd1, 0xe4, 0x81, 0x7f, ++ 0xc6, 0x6e, 0x2c, 0x77, 0x7d, 0xd1, 0xae, 0x40, 0xfb, 0x7f, 0x6b, 0xfc, ++ 0x64, 0x1a, 0x03, 0x54, 0x7d, 0x84, 0x4d, 0xae, 0x40, 0xbe, 0x1a, 0x9a, ++ 0x80, 0xf2, 0x78, 0x1b, 0x0b, 0x4c, 0x40, 0x39, 0xf4, 0xdd, 0xc6, 0x71, ++ 0x07, 0x75, 0xd0, 0xee, 0xa8, 0x3e, 0xb2, 0x83, 0x01, 0xbc, 0x8a, 0x1d, ++ 0x1b, 0x6a, 0x14, 0x68, 0x77, 0xd4, 0x16, 0xc9, 0x91, 0x80, 0x87, 0x4c, ++ 0xdc, 0xd4, 0xcb, 0xcb, 0x69, 0x91, 0x1d, 0x08, 0xcf, 0xe0, 0xa6, 0x47, ++ 0x09, 0xbe, 0x47, 0x73, 0x22, 0x39, 0x3a, 0x28, 0x4f, 0x71, 0x84, 0x79, ++ 0x79, 0x5c, 0x64, 0x07, 0x96, 0x6f, 0xdc, 0xf4, 0x2c, 0x2f, 0x4f, 0x8e, ++ 0xe4, 0xc8, 0xf0, 0x7d, 0x41, 0xf0, 0xb9, 0x9a, 0x6a, 0x28, 0xef, 0xb1, ++ 0x8f, 0xbc, 0x5f, 0xf3, 0x1c, 0x9c, 0x8f, 0xab, 0xf3, 0x3b, 0x31, 0xd6, ++ 0x97, 0xe5, 0x48, 0x43, 0xb2, 0xe3, 0x72, 0x62, 0x87, 0x1e, 0x20, 0x06, ++ 0xfc, 0x70, 0xd1, 0xea, 0xcf, 0x9e, 0xdf, 0x03, 0x70, 0x58, 0x74, 0x8f, ++ 0x85, 0xf8, 0xd4, 0x9e, 0xcf, 0xbf, 0x33, 0xcf, 0x4f, 0xeb, 0x0f, 0xfa, ++ 0x95, 0x0a, 0xe0, 0x87, 0x9c, 0xf4, 0xb9, 0x1c, 0x23, 0x7e, 0xac, 0x90, ++ 0x1e, 0x90, 0x89, 0xb2, 0xcb, 0x19, 0xc3, 0x87, 0x2d, 0x77, 0xd0, 0x43, ++ 0x7c, 0x7e, 0x62, 0xcb, 0x3e, 0x94, 0xf7, 0x19, 0x8b, 0x4a, 0x88, 0xcf, ++ 0x5f, 0x48, 0xf1, 0xb5, 0x3b, 0xa6, 0xc5, 0x9e, 0xbf, 0x4b, 0xe7, 0xcf, ++ 0x76, 0x87, 0x9d, 0xf3, 0x65, 0x59, 0xe7, 0xa3, 0xf6, 0xf7, 0xda, 0x48, ++ 0xef, 0x79, 0xd8, 0xcc, 0xd7, 0x03, 0xfb, 0x86, 0xf0, 0x6b, 0x15, 0xf8, ++ 0x28, 0x17, 0xeb, 0x29, 0x77, 0xe8, 0xe8, 0x99, 0x6b, 0x9f, 0x4d, 0xfd, ++ 0x7c, 0x28, 0xf9, 0xb6, 0x9a, 0x64, 0x7c, 0xb2, 0xa0, 0x19, 0xf1, 0xb9, ++ 0x2a, 0x89, 0xf4, 0x8c, 0x5b, 0x77, 0x01, 0x5f, 0x00, 0xbe, 0xdc, 0x2b, ++ 0xe6, 0xdd, 0xbb, 0x69, 0x42, 0x28, 0x08, 0xfd, 0xdf, 0x2a, 0x31, 0x3f, ++ 0xf2, 0x8d, 0x5e, 0x87, 0x2f, 0x13, 0xf9, 0xc3, 0x4b, 0x7f, 0x91, 0x6f, ++ 0xc7, 0xf5, 0xf6, 0x96, 0x42, 0x19, 0x9e, 0x3f, 0x15, 0xfc, 0xbe, 0x77, ++ 0xbe, 0x2f, 0xd3, 0x11, 0x27, 0x17, 0x7b, 0x77, 0xf1, 0x7a, 0x95, 0xef, ++ 0xf4, 0xe6, 0xf3, 0xef, 0x55, 0x79, 0x93, 0xd1, 0xc1, 0xc7, 0xc9, 0x78, ++ 0x78, 0xc2, 0x6e, 0x5c, 0x87, 0x45, 0x61, 0x3e, 0x2c, 0x2f, 0xaf, 0x2b, ++ 0xda, 0xdd, 0x4e, 0x72, 0x7b, 0x01, 0xcd, 0x97, 0xf9, 0x7c, 0x99, 0x12, ++ 0xac, 0xf7, 0xc4, 0xaa, 0x02, 0x1d, 0xea, 0x91, 0x2a, 0x7e, 0x94, 0x42, ++ 0xdf, 0x75, 0x58, 0x7f, 0x0b, 0xf6, 0x6f, 0x8d, 0xe1, 0x49, 0x1d, 0xbf, ++ 0x1d, 0xd7, 0x9d, 0x86, 0x7a, 0x00, 0xc8, 0x7d, 0x58, 0x6f, 0x9b, 0x33, ++ 0xd0, 0x8e, 0xf8, 0x04, 0x3d, 0x60, 0x0a, 0xe9, 0x81, 0x42, 0x0f, 0x68, ++ 0xc7, 0xf5, 0xc6, 0xc1, 0x97, 0x29, 0x91, 0x69, 0xf8, 0xfe, 0xff, 0x23, ++ 0x38, 0xdd, 0x89, 0xeb, 0xfe, 0xef, 0xc2, 0x69, 0x04, 0x7e, 0x11, 0xc4, ++ 0x71, 0x1b, 0x5b, 0x81, 0x5f, 0xe8, 0xe2, 0xf8, 0x85, 0x80, 0xdf, 0x66, ++ 0x29, 0xac, 0xcf, 0xe0, 0xfc, 0xc2, 0x8b, 0x72, 0x0e, 0xdf, 0x2f, 0x00, ++ 0xfe, 0x78, 0x8b, 0x3d, 0xf0, 0x00, 0xf6, 0xaf, 0x8e, 0xbf, 0xe8, 0xde, ++ 0x46, 0xd2, 0xfb, 0xd4, 0x79, 0x59, 0xfe, 0xee, 0xe5, 0x9a, 0x9b, 0xd8, ++ 0xf0, 0x7d, 0x96, 0xa8, 0x97, 0x1d, 0xfd, 0xd0, 0xb4, 0x91, 0x81, 0x1c, ++ 0x3b, 0x6a, 0xe8, 0x23, 0xbe, 0x78, 0x74, 0x1e, 0xf3, 0xb6, 0x23, 0xff, ++ 0xd0, 0xb1, 0x7a, 0x84, 0xa3, 0xaa, 0x57, 0x56, 0xdc, 0xb3, 0xe6, 0x6d, ++ 0x06, 0xfa, 0xec, 0x97, 0x0e, 0x99, 0xf0, 0xdc, 0x2d, 0xf9, 0x32, 0x71, ++ 0x5d, 0xdd, 0x80, 0x57, 0x13, 0xca, 0xe1, 0xf9, 0x86, 0xd0, 0x9e, 0xfc, ++ 0x98, 0x5c, 0xec, 0x75, 0x84, 0xb6, 0xae, 0x40, 0xbc, 0xde, 0x50, 0xe2, ++ 0x0d, 0x7a, 0x48, 0x3e, 0xd2, 0x7e, 0x0b, 0xb6, 0x5a, 0xa8, 0x5d, 0xaf, ++ 0x23, 0xc2, 0x14, 0xac, 0xbf, 0xc2, 0x63, 0x87, 0x99, 0x20, 0x9e, 0x09, ++ 0x1f, 0x43, 0x37, 0x1b, 0x42, 0xbb, 0x25, 0xc4, 0x37, 0xa7, 0x97, 0xde, ++ 0x55, 0x13, 0x43, 0x41, 0x89, 0xf0, 0x1e, 0xa4, 0xef, 0x6f, 0xe6, 0xf4, ++ 0xd3, 0x3b, 0x9f, 0x91, 0x7e, 0xdf, 0x7b, 0xb3, 0x9b, 0xe8, 0xc6, 0xcc, ++ 0x42, 0x66, 0x9c, 0xcf, 0x68, 0x74, 0x90, 0xde, 0xc1, 0x88, 0x8e, 0x98, ++ 0xe2, 0x9b, 0x32, 0xdf, 0x16, 0x83, 0xc3, 0x2f, 0xc5, 0xbe, 0xb6, 0x94, ++ 0x47, 0x5e, 0xfc, 0x17, 0xd4, 0x23, 0x37, 0x9a, 0x49, 0x8f, 0x44, 0x99, ++ 0x89, 0x76, 0x17, 0xeb, 0xc9, 0xa0, 0xf9, 0x02, 0x3e, 0x5f, 0x22, 0xfa, ++ 0x50, 0xed, 0xa5, 0x47, 0x32, 0x43, 0x1b, 0xc8, 0x3e, 0xf3, 0x56, 0x20, ++ 0x3e, 0x1e, 0xb0, 0xf9, 0x16, 0xd3, 0xfc, 0x7f, 0x60, 0xf1, 0xe0, 0xfc, ++ 0xb7, 0x9b, 0x59, 0x97, 0xa9, 0x0c, 0xcd, 0x0f, 0xd6, 0x49, 0xfc, 0x4e, ++ 0xcc, 0x87, 0xf5, 0x3c, 0xc6, 0x50, 0x3f, 0xbb, 0x5d, 0xe8, 0x67, 0xff, ++ 0x5e, 0x7f, 0xce, 0x86, 0x7a, 0xc0, 0x1b, 0x0e, 0xae, 0x5f, 0x21, 0xa1, ++ 0x98, 0x80, 0xff, 0x2d, 0x61, 0xbc, 0x7e, 0xc9, 0x3a, 0xcb, 0xc7, 0x68, ++ 0xcf, 0x2c, 0x59, 0x27, 0x87, 0x8d, 0x60, 0xaf, 0xb0, 0xae, 0xd9, 0xbe, ++ 0x48, 0x9c, 0x9d, 0x41, 0x14, 0x05, 0xfd, 0x05, 0x04, 0xbf, 0x64, 0x5b, ++ 0x86, 0x6c, 0x48, 0x37, 0x01, 0xfc, 0x2e, 0x19, 0xfb, 0xff, 0xa3, 0xcd, ++ 0x63, 0xc5, 0x32, 0x7c, 0x3f, 0x05, 0xd1, 0x0e, 0xdf, 0x17, 0xc7, 0xbe, ++ 0x7f, 0x5f, 0xec, 0xdb, 0x45, 0x32, 0x9f, 0x3f, 0x6b, 0xb3, 0x78, 0x10, ++ 0xbe, 0x89, 0x7c, 0xfd, 0x7d, 0x75, 0x7e, 0x3d, 0x8f, 0xf9, 0xe2, 0xc7, ++ 0x53, 0xc7, 0x49, 0xec, 0x17, 0xec, 0xb8, 0x0f, 0x90, 0x3e, 0x01, 0xee, ++ 0xe1, 0x14, 0xd4, 0xe7, 0x7f, 0x20, 0x13, 0x5e, 0x13, 0xe7, 0xeb, 0x32, ++ 0x0c, 0x3d, 0x68, 0x86, 0xfa, 0x45, 0x6d, 0xb2, 0xe3, 0x3e, 0x80, 0x67, ++ 0xa0, 0xd5, 0x46, 0xeb, 0x55, 0xe7, 0x7b, 0x7b, 0xc6, 0xd0, 0x95, 0x64, ++ 0x5f, 0x25, 0xf4, 0x7f, 0xd2, 0xd2, 0x54, 0xa1, 0xe0, 0xfa, 0x85, 0xfd, ++ 0xc1, 0xd6, 0x69, 0xed, 0x2f, 0xc6, 0x0c, 0xb1, 0x32, 0xd0, 0xc5, 0x72, ++ 0x36, 0x44, 0x76, 0xcc, 0xb0, 0xf7, 0xc2, 0x6e, 0x4d, 0xb4, 0xfb, 0x18, ++ 0xfb, 0x8b, 0x31, 0xbe, 0x9d, 0xba, 0x5f, 0x98, 0x47, 0x4a, 0x98, 0xbf, ++ 0xa0, 0x2b, 0x8f, 0xa4, 0x20, 0xde, 0x02, 0x12, 0xc7, 0x9b, 0xc1, 0x30, ++ 0xb4, 0x08, 0xf9, 0x4e, 0xe2, 0xbc, 0x55, 0x78, 0x1a, 0x9d, 0x3a, 0x01, ++ 0x77, 0x4e, 0x17, 0x89, 0xf0, 0x36, 0x3a, 0xb9, 0xdc, 0x49, 0x84, 0xb7, ++ 0xcb, 0x10, 0xc9, 0xc1, 0x7e, 0x03, 0xad, 0x46, 0x82, 0x53, 0x62, 0xff, ++ 0xaa, 0x5c, 0x7c, 0xcc, 0x0c, 0xfb, 0x07, 0xe8, 0x6e, 0x8b, 0x24, 0x11, ++ 0xbd, 0x6e, 0xb9, 0xdb, 0x42, 0x72, 0x8e, 0x99, 0x38, 0x9e, 0x9b, 0x57, ++ 0x27, 0x79, 0x90, 0x7e, 0xb7, 0x19, 0x86, 0x9e, 0xa6, 0x7d, 0xf5, 0xaa, ++ 0x91, 0x21, 0xde, 0xcf, 0x9a, 0x87, 0x5e, 0x22, 0x7e, 0x55, 0xc8, 0xfd, ++ 0x0a, 0x67, 0x7f, 0x29, 0xef, 0xc2, 0x76, 0x67, 0xd2, 0x38, 0xdd, 0x9f, ++ 0x79, 0x45, 0x4f, 0xfb, 0x8d, 0x4f, 0x06, 0xf4, 0xa1, 0x5f, 0xca, 0xbb, ++ 0xa9, 0x5e, 0xe2, 0xfd, 0x9e, 0x69, 0xb7, 0x78, 0x70, 0xbf, 0x36, 0x23, ++ 0xa4, 0x61, 0xfc, 0xe6, 0xe0, 0x7f, 0xb6, 0x31, 0x80, 0xef, 0x71, 0x1d, ++ 0xb7, 0x93, 0x9b, 0xfb, 0xb5, 0xf6, 0xf0, 0x19, 0xf8, 0x57, 0x5f, 0x16, ++ 0xe3, 0x1b, 0x67, 0x19, 0x1f, 0x27, 0xd8, 0xcf, 0xf9, 0x04, 0xac, 0x74, ++ 0x15, 0x8d, 0x73, 0x6b, 0x12, 0xdb, 0x00, 0xfd, 0x36, 0xe9, 0x24, 0x1f, ++ 0xea, 0x4f, 0x4d, 0xab, 0x27, 0x86, 0x3a, 0x38, 0x3d, 0x99, 0x70, 0x3f, ++ 0x35, 0x88, 0x29, 0x35, 0xe9, 0xc0, 0x2e, 0x2c, 0x8b, 0xed, 0xff, 0x26, ++ 0xdd, 0xb1, 0x22, 0xb4, 0xab, 0x1a, 0x4c, 0x1b, 0x07, 0xe5, 0x64, 0xaa, ++ 0x3f, 0x8c, 0xf6, 0x18, 0x43, 0x7b, 0x0a, 0xbe, 0x5b, 0x8d, 0x1f, 0xe5, ++ 0x0f, 0x87, 0x7f, 0xd3, 0xc6, 0xdf, 0xfe, 0x19, 0xe7, 0xdd, 0xb4, 0x5f, ++ 0x4b, 0x17, 0x0d, 0x31, 0xfa, 0x91, 0x2e, 0x4a, 0xf8, 0x7d, 0x1c, 0x3d, ++ 0xe5, 0xc7, 0xe8, 0x84, 0xf4, 0x6f, 0xe4, 0x1f, 0xd5, 0x2c, 0x34, 0x4e, ++ 0xe2, 0x7e, 0x1a, 0x2c, 0x5b, 0x6a, 0x06, 0x43, 0xe8, 0xa7, 0x69, 0x16, ++ 0xfe, 0x8b, 0xb4, 0x43, 0x91, 0x39, 0x48, 0x3f, 0xb6, 0xf2, 0x3e, 0xb6, ++ 0x04, 0x9e, 0xcd, 0xa7, 0xb8, 0xfe, 0x31, 0x63, 0x60, 0xd7, 0xeb, 0x68, ++ 0x07, 0x3b, 0x6a, 0x06, 0x73, 0x70, 0x99, 0xcd, 0xad, 0x6b, 0xa7, 0x9e, ++ 0x98, 0x1a, 0xc3, 0xaf, 0x3a, 0xcf, 0x2b, 0x06, 0x36, 0xc9, 0x68, 0xdf, ++ 0xa9, 0x7a, 0x4b, 0x9c, 0x7d, 0x39, 0x61, 0xc1, 0xe4, 0xf8, 0xe7, 0x7d, ++ 0xf4, 0x1d, 0xda, 0xab, 0x38, 0x5e, 0x04, 0x5f, 0xe1, 0xbe, 0x51, 0xb8, ++ 0xbc, 0xdb, 0x2c, 0xe4, 0x1d, 0xc8, 0x45, 0xe2, 0xcb, 0xcb, 0x7b, 0xc6, ++ 0x93, 0x5c, 0x44, 0xb9, 0x85, 0xfc, 0x4d, 0xb5, 0x77, 0x91, 0xdf, 0x21, ++ 0x7f, 0x79, 0xc6, 0x59, 0x75, 0x9b, 0x13, 0xd6, 0xe9, 0x4d, 0xad, 0xba, ++ 0xc9, 0x39, 0x8d, 0x8f, 0x43, 0x7a, 0x3e, 0x1a, 0x49, 0x57, 0x0c, 0x87, ++ 0x67, 0xa2, 0xdc, 0x51, 0xdb, 0xa1, 0xdd, 0xdb, 0x62, 0x1d, 0xbd, 0x5d, ++ 0xd4, 0x0f, 0xb4, 0x35, 0x85, 0xf3, 0x0f, 0x45, 0xa2, 0xf2, 0x8a, 0x5f, ++ 0xe8, 0x77, 0x6d, 0xa0, 0xf9, 0x29, 0x44, 0x2f, 0x6b, 0x77, 0xe4, 0x13, ++ 0x3f, 0x56, 0xfd, 0x35, 0x0d, 0xc2, 0x4f, 0xb5, 0x42, 0xf8, 0x77, 0x56, ++ 0x08, 0xff, 0xce, 0xca, 0x2d, 0x46, 0xe6, 0x89, 0xf7, 0x67, 0x85, 0xb4, ++ 0xe5, 0x06, 0xc1, 0x0f, 0x1a, 0x59, 0x84, 0xfb, 0xb9, 0xf6, 0x42, 0x7d, ++ 0xbc, 0x5f, 0xa7, 0x9a, 0x85, 0x6d, 0x58, 0x8f, 0xfe, 0x1d, 0x7c, 0xf6, ++ 0x69, 0xbf, 0x6f, 0x66, 0xa1, 0x59, 0x0a, 0xe2, 0xb7, 0xff, 0xa2, 0x31, ++ 0xfe, 0x3d, 0xeb, 0xe5, 0xeb, 0xbd, 0x5d, 0xe0, 0x7d, 0xab, 0x99, 0xfb, ++ 0x75, 0x66, 0xac, 0xdb, 0x25, 0x73, 0x67, 0x15, 0x5f, 0x6f, 0x4a, 0x99, ++ 0x2f, 0xff, 0x7e, 0x94, 0x23, 0x6f, 0xe9, 0xc9, 0xff, 0xf0, 0x1f, 0x02, ++ 0x4f, 0x2a, 0x5c, 0x2c, 0xce, 0xaa, 0xc5, 0x08, 0xef, 0x24, 0xb4, 0xd7, ++ 0xb0, 0xdd, 0xfd, 0x46, 0x82, 0xcb, 0x09, 0x90, 0xd7, 0xfb, 0x84, 0xdf, ++ 0x63, 0x01, 0xda, 0xa1, 0x6d, 0x81, 0xcc, 0xc2, 0x42, 0x04, 0x8f, 0x3d, ++ 0x77, 0x81, 0x6d, 0x38, 0x7c, 0x37, 0xbc, 0x6a, 0xae, 0x47, 0x7a, 0xe9, ++ 0x71, 0x72, 0xbd, 0x45, 0x7d, 0x3f, 0xc7, 0xa9, 0xa7, 0x32, 0xf9, 0x83, ++ 0x10, 0xee, 0xed, 0x16, 0xd2, 0xbb, 0x01, 0xcc, 0x53, 0x90, 0x8e, 0x2a, ++ 0x0a, 0x54, 0x39, 0xca, 0xa6, 0xa0, 0x1f, 0xea, 0x63, 0x3d, 0xe8, 0x63, ++ 0x50, 0x6e, 0xba, 0xd1, 0x1a, 0xc0, 0xfe, 0x22, 0xa8, 0x37, 0x40, 0x79, ++ 0x87, 0xe0, 0x5f, 0x3b, 0x9c, 0x06, 0xea, 0x4f, 0x2d, 0x47, 0xed, 0x3c, ++ 0x41, 0x2f, 0x30, 0x0e, 0xf5, 0x87, 0x7e, 0x19, 0x7f, 0x1c, 0x1d, 0x3c, ++ 0x15, 0x6d, 0xbf, 0x49, 0xe8, 0x93, 0x9c, 0x2f, 0x6c, 0x5e, 0x95, 0x44, ++ 0xfc, 0x28, 0x46, 0xb7, 0x3a, 0x46, 0x74, 0x5b, 0xe2, 0x37, 0xa0, 0x3f, ++ 0xe9, 0x55, 0xc1, 0x47, 0x5e, 0x05, 0x80, 0x92, 0x9d, 0xd5, 0x67, 0xe6, ++ 0x7c, 0x44, 0xe1, 0xfc, 0xe9, 0xd5, 0x53, 0x13, 0x89, 0xef, 0x1d, 0xf9, ++ 0x6c, 0x35, 0xf1, 0x95, 0x73, 0x75, 0x49, 0xcc, 0x28, 0x51, 0x7b, 0x9f, ++ 0x84, 0xf5, 0x2f, 0x1a, 0x43, 0xf7, 0x41, 0x79, 0x99, 0xf0, 0xb3, 0xbe, ++ 0x2a, 0x71, 0x3d, 0x31, 0x78, 0xc0, 0x46, 0xfd, 0x34, 0x18, 0x02, 0x5b, ++ 0xd1, 0xef, 0xd0, 0xf0, 0xc2, 0x38, 0x2f, 0x60, 0x8c, 0xbd, 0x64, 0x08, ++ 0xfd, 0xe8, 0x69, 0xac, 0x7f, 0xcd, 0x4c, 0x7e, 0xad, 0x86, 0x64, 0x3e, ++ 0xcf, 0x86, 0x57, 0xc7, 0x10, 0x9f, 0xfc, 0xa9, 0x3e, 0xf4, 0xec, 0x8f, ++ 0xc9, 0x4f, 0x61, 0x24, 0xfd, 0xad, 0x21, 0xc9, 0x93, 0x42, 0xf5, 0x3f, ++ 0x4f, 0x65, 0x58, 0xdf, 0x65, 0x09, 0x84, 0x71, 0x1f, 0x65, 0x19, 0xb9, ++ 0x5e, 0xd9, 0x60, 0x08, 0x17, 0x39, 0x00, 0x8e, 0xc7, 0x42, 0x5c, 0x3f, ++ 0x3e, 0x86, 0x8c, 0x06, 0xfb, 0x1f, 0xb0, 0x91, 0xde, 0x03, 0xd3, 0xcc, ++ 0xc4, 0xf1, 0x8f, 0x77, 0x67, 0x78, 0x37, 0x78, 0x62, 0x70, 0x39, 0xfe, ++ 0xe0, 0x24, 0xa2, 0xff, 0xcd, 0x7a, 0x8e, 0xb7, 0xe0, 0x2b, 0xdc, 0xef, ++ 0x79, 0x4c, 0xef, 0x9f, 0x93, 0x09, 0xe5, 0x63, 0x2f, 0x96, 0x7a, 0xc1, ++ 0xb2, 0x64, 0x67, 0xfd, 0x86, 0xb0, 0x01, 0xe6, 0xd8, 0xfc, 0x30, 0xd7, ++ 0xe7, 0x96, 0xea, 0x3c, 0x3b, 0x5b, 0x91, 0x37, 0xbd, 0x66, 0xf1, 0x6a, ++ 0xec, 0xd1, 0x87, 0x56, 0xd6, 0x62, 0x7d, 0xf3, 0xea, 0x75, 0xd7, 0x21, ++ 0x1f, 0x1c, 0x6d, 0x3f, 0x23, 0x3f, 0x8f, 0xf7, 0xe7, 0x9e, 0x61, 0x43, ++ 0xb9, 0x64, 0x8f, 0xd6, 0x17, 0xf4, 0x85, 0x61, 0xdc, 0x33, 0x03, 0x13, ++ 0xbc, 0x24, 0x3e, 0x99, 0x1b, 0x90, 0x0d, 0x74, 0x62, 0xe7, 0x6d, 0x4f, ++ 0xe8, 0x01, 0xde, 0x48, 0x5f, 0x07, 0xf4, 0x44, 0xbf, 0x97, 0xda, 0x3f, ++ 0xae, 0x17, 0xed, 0x43, 0x94, 0x2f, 0x38, 0x4e, 0x33, 0xf0, 0xdf, 0xa8, ++ 0x9f, 0x99, 0xf8, 0x6f, 0x5c, 0x59, 0x1e, 0xa9, 0xcc, 0xf1, 0xd9, 0xfc, ++ 0x6a, 0x86, 0xd0, 0xdf, 0xb4, 0xf5, 0xb7, 0xa6, 0x04, 0xce, 0xe1, 0xfe, ++ 0x6a, 0xfa, 0x87, 0xdf, 0x1f, 0x6d, 0x25, 0xf8, 0x0e, 0x11, 0xff, 0x63, ++ 0x3d, 0xdc, 0x7f, 0x7e, 0x42, 0xef, 0x5b, 0x84, 0x74, 0xea, 0xa8, 0x0e, ++ 0x1b, 0x96, 0xc4, 0xc9, 0xed, 0xa4, 0x54, 0x2e, 0xcf, 0x97, 0x1a, 0x85, ++ 0x9e, 0xc7, 0xc2, 0x86, 0xf8, 0x7d, 0xa7, 0xd6, 0x57, 0x54, 0x69, 0xe9, ++ 0x5c, 0x7d, 0x9a, 0x53, 0x39, 0xbd, 0xdb, 0x06, 0x39, 0x1f, 0x1f, 0x5e, ++ 0xaf, 0x13, 0xfb, 0xe1, 0x3b, 0x46, 0x94, 0x5b, 0xdc, 0xb5, 0x03, 0xf6, ++ 0xf6, 0x29, 0xee, 0xef, 0x48, 0x4a, 0xf5, 0x50, 0xfd, 0x8c, 0x53, 0x61, ++ 0xc3, 0x52, 0x28, 0xe7, 0xad, 0x0b, 0x1b, 0x56, 0x88, 0x27, 0xee, 0x0b, ++ 0x80, 0x77, 0xd8, 0x04, 0xeb, 0x3e, 0xb1, 0xd5, 0xc6, 0xf7, 0x33, 0x80, ++ 0x01, 0xfb, 0x59, 0x31, 0x9d, 0x91, 0xbe, 0xb2, 0x42, 0x06, 0x3d, 0xb5, ++ 0x0c, 0xdf, 0x7b, 0xfa, 0x23, 0x80, 0x97, 0x93, 0x2f, 0x3a, 0x38, 0x7d, ++ 0xfd, 0x09, 0xa0, 0x02, 0xf0, 0x5e, 0xcc, 0x44, 0x3b, 0x23, 0xe8, 0xb5, ++ 0xc0, 0xb7, 0x5e, 0xee, 0x94, 0xc2, 0xa8, 0xf7, 0x2f, 0xde, 0x62, 0xdc, ++ 0x6d, 0xce, 0xc7, 0x7d, 0xec, 0x93, 0x6d, 0x88, 0xcf, 0x1d, 0x12, 0xf1, ++ 0xad, 0xc5, 0x9d, 0x95, 0x45, 0x5b, 0xa1, 0xbc, 0x7a, 0xff, 0x64, 0xc2, ++ 0x7f, 0xf2, 0x74, 0x4e, 0x97, 0xab, 0x43, 0x0e, 0x92, 0x7f, 0x33, 0x04, ++ 0x1f, 0x5c, 0x6a, 0x0c, 0x19, 0x48, 0xcf, 0x7e, 0x96, 0xfb, 0xf1, 0xa0, ++ 0x7f, 0xd2, 0x97, 0x1b, 0xe0, 0xa3, 0xcc, 0xb2, 0xe1, 0x70, 0x40, 0xfe, ++ 0xad, 0xa1, 0x87, 0x90, 0x36, 0x0e, 0x31, 0xa3, 0x4f, 0xf0, 0xd3, 0xbd, ++ 0x71, 0xf1, 0x87, 0x82, 0x38, 0xbe, 0xde, 0x97, 0xf0, 0x3d, 0xe8, 0x79, ++ 0x5a, 0xfa, 0x08, 0xaa, 0x72, 0x87, 0xf3, 0x39, 0xe6, 0xc9, 0x40, 0x3e, ++ 0xa7, 0xf2, 0x61, 0x8b, 0xd3, 0x3f, 0x2d, 0x95, 0xf0, 0x50, 0x98, 0x81, ++ 0xf8, 0x05, 0x7c, 0x72, 0x3e, 0xb9, 0x4f, 0x22, 0xb8, 0x36, 0xb2, 0x16, ++ 0x2e, 0x37, 0x04, 0xbf, 0x8f, 0x8e, 0x2b, 0xe4, 0xc5, 0x49, 0x39, 0xc8, ++ 0xe5, 0x92, 0x71, 0x13, 0x3d, 0xe7, 0xa5, 0xe6, 0x13, 0xde, 0x56, 0xa3, ++ 0xbc, 0x21, 0xbf, 0x3a, 0xb7, 0xff, 0x46, 0xa3, 0x83, 0x79, 0xa9, 0x3a, ++ 0x61, 0x27, 0x8c, 0x4c, 0x07, 0xd7, 0x0a, 0x3a, 0x68, 0x38, 0xc5, 0xc2, ++ 0x57, 0xc2, 0x78, 0x0d, 0xeb, 0x58, 0xb8, 0x71, 0x0a, 0x7f, 0xda, 0xa6, ++ 0x90, 0x1c, 0xe4, 0xf2, 0xd0, 0x24, 0xe2, 0x1d, 0x26, 0x1e, 0x0f, 0xf9, ++ 0x26, 0xb9, 0x98, 0x28, 0x07, 0x87, 0xc9, 0xbd, 0x04, 0x79, 0x97, 0x61, ++ 0x10, 0xf2, 0x4d, 0xe0, 0x39, 0xde, 0xdf, 0x8d, 0xf2, 0x7e, 0xc6, 0xba, ++ 0x90, 0x8c, 0x7e, 0xcf, 0x5c, 0xbb, 0xaf, 0x32, 0x63, 0x5a, 0x4c, 0x7f, ++ 0x69, 0x7e, 0xdf, 0x64, 0xf2, 0x5c, 0x86, 0x65, 0x3f, 0x2b, 0xb0, 0xa2, ++ 0xff, 0xa6, 0xf2, 0x59, 0x37, 0xfa, 0x7f, 0xc1, 0x5e, 0xc7, 0x7d, 0x65, ++ 0x01, 0xb8, 0xec, 0x42, 0xf9, 0xa2, 0xea, 0xb7, 0x6e, 0xbe, 0x5e, 0xb7, ++ 0x81, 0xd3, 0xaf, 0x5e, 0xf1, 0xb3, 0x52, 0x2b, 0xe2, 0x65, 0x90, 0xec, ++ 0xd9, 0xa1, 0x34, 0x66, 0x47, 0x7a, 0x54, 0xe1, 0xb9, 0xc3, 0x06, 0xdf, ++ 0x95, 0xe1, 0x77, 0x7c, 0xbf, 0x45, 0xbf, 0x37, 0xb1, 0xce, 0xa4, 0xb8, ++ 0xef, 0xab, 0x5e, 0x35, 0x13, 0x5f, 0x3d, 0xff, 0x8a, 0x2d, 0x64, 0x24, ++ 0xbd, 0x23, 0x90, 0xe7, 0x80, 0xfe, 0xd2, 0x3f, 0x32, 0x92, 0x1e, 0x7a, ++ 0xe6, 0x55, 0x1b, 0xc9, 0xcf, 0x33, 0x42, 0xfe, 0xb9, 0x54, 0xbf, 0x00, ++ 0x5b, 0x4f, 0xf8, 0x59, 0x27, 0xf0, 0x1a, 0x64, 0x55, 0x63, 0xd0, 0xbf, ++ 0xca, 0xa4, 0x79, 0x63, 0x90, 0x05, 0xaa, 0x7a, 0x58, 0xa3, 0x63, 0x34, ++ 0x7f, 0xb7, 0xa8, 0xcf, 0x1f, 0xbc, 0x91, 0xd3, 0x95, 0x91, 0xec, 0xc9, ++ 0xf3, 0x8e, 0xc8, 0xf7, 0xb1, 0x0c, 0xf3, 0x61, 0xa8, 0x5f, 0xdf, 0x25, ++ 0xf0, 0xdc, 0xbc, 0x7f, 0x56, 0xe9, 0xbd, 0xf0, 0xbe, 0xd9, 0x6f, 0xf5, ++ 0x72, 0xe8, 0x07, 0x4a, 0x91, 0x5e, 0x8d, 0xf2, 0x5d, 0x37, 0xa2, 0xdf, ++ 0x65, 0x8e, 0xbc, 0x6e, 0xe8, 0x6e, 0x58, 0x47, 0x63, 0x8e, 0xd5, 0x6e, ++ 0x84, 0x4f, 0xaa, 0xf3, 0xfe, 0xf5, 0x37, 0x37, 0x43, 0xf9, 0xd3, 0xfd, ++ 0x7a, 0x66, 0x44, 0x3c, 0xef, 0x99, 0x55, 0xc7, 0x0a, 0x46, 0xe7, 0xbf, ++ 0xab, 0x42, 0xfa, 0x63, 0x91, 0xb8, 0xfd, 0xb2, 0x66, 0xaf, 0xb6, 0xdc, ++ 0xd8, 0xa7, 0x2d, 0x37, 0x33, 0xe5, 0x58, 0x24, 0x8e, 0x1f, 0x3f, 0x9e, ++ 0x6a, 0x73, 0x9d, 0x9c, 0x44, 0xbc, 0xc3, 0x7b, 0x11, 0xe8, 0xdb, 0x68, ++ 0x6c, 0x39, 0xb5, 0x0b, 0xe6, 0x6b, 0xfc, 0xa9, 0x91, 0xe4, 0x51, 0x4b, ++ 0x6a, 0x20, 0x94, 0x9a, 0x86, 0x7a, 0xf9, 0xd0, 0x9b, 0x08, 0x67, 0x63, ++ 0xde, 0xe7, 0x53, 0xd0, 0x8f, 0x51, 0x95, 0xf7, 0x27, 0x8a, 0xfb, 0x9c, ++ 0xff, 0x01, 0xf3, 0xe2, 0xbc, 0xcf, 0x9b, 0x2b, 0x49, 0x7e, 0x9f, 0xdf, ++ 0x6a, 0xf6, 0x04, 0xe3, 0xf8, 0x57, 0xb3, 0xa0, 0xff, 0xde, 0xdc, 0x5a, ++ 0xaa, 0xef, 0xdd, 0x66, 0xf4, 0x48, 0xbc, 0xbe, 0x76, 0x5a, 0x05, 0xea, ++ 0x83, 0x34, 0x36, 0xfe, 0x99, 0x74, 0x00, 0xff, 0xe6, 0x2d, 0x73, 0x3f, ++ 0x25, 0xbb, 0x09, 0xb5, 0x76, 0x28, 0xf7, 0xa2, 0x7e, 0x89, 0xdf, 0xbd, ++ 0x20, 0x85, 0xda, 0x51, 0x7f, 0xdc, 0xc2, 0xe5, 0xde, 0x69, 0xd0, 0x1f, ++ 0x4d, 0x30, 0x9f, 0x93, 0x08, 0x67, 0x8c, 0x7b, 0xc8, 0x03, 0x73, 0x4c, ++ 0xf0, 0x9f, 0xbd, 0xce, 0x9a, 0x09, 0xc8, 0x5f, 0x94, 0x3f, 0x2b, 0x7e, ++ 0xc4, 0xff, 0x03, 0xd8, 0x55, 0x9c, 0xbe, 0x7b, 0x20, 0xca, 0xa7, 0xb9, ++ 0x9f, 0xe7, 0x5a, 0xf4, 0xf3, 0x8c, 0x25, 0x3f, 0xcf, 0x01, 0xe4, 0x1b, ++ 0x8d, 0xa6, 0x88, 0xa1, 0x12, 0xfa, 0xb9, 0xfa, 0xcf, 0x5f, 0x11, 0x5f, ++ 0x5e, 0xd9, 0xba, 0x84, 0xf4, 0xfa, 0x98, 0x9e, 0x6b, 0x24, 0x3e, 0xb2, ++ 0xf2, 0xee, 0x00, 0xbd, 0x7f, 0x7d, 0xeb, 0x35, 0xb4, 0xae, 0x93, 0xb0, ++ 0x6e, 0x84, 0xcf, 0xc9, 0x1d, 0xdc, 0x9e, 0x5b, 0x99, 0x6d, 0x0d, 0xe1, ++ 0xfc, 0xae, 0x76, 0x70, 0xfd, 0x77, 0x25, 0x7c, 0x27, 0x49, 0xc3, 0xe1, ++ 0x92, 0x08, 0x87, 0x4f, 0xb6, 0x5f, 0xe3, 0x46, 0x7c, 0x7f, 0xc2, 0xf8, ++ 0x78, 0xc1, 0x3e, 0xae, 0x27, 0x7c, 0x62, 0x1f, 0x4c, 0x26, 0xfe, 0xe3, ++ 0x69, 0x49, 0x46, 0x3d, 0xaf, 0x79, 0xcb, 0x35, 0x9f, 0x22, 0xdf, 0x5a, ++ 0xb9, 0x43, 0xf6, 0xa2, 0x1c, 0x67, 0x07, 0x6c, 0xe4, 0x17, 0x59, 0xb9, ++ 0x63, 0xf6, 0x84, 0xe5, 0x56, 0xec, 0xe7, 0xcb, 0xd4, 0x4a, 0x84, 0xdb, ++ 0xce, 0xd9, 0x76, 0x99, 0xde, 0xcb, 0xfe, 0x10, 0xf7, 0xaf, 0x0c, 0x5e, ++ 0x0d, 0xef, 0x95, 0x9d, 0x97, 0x7b, 0x70, 0x9f, 0x1c, 0xde, 0x61, 0xe4, ++ 0xf3, 0x73, 0x98, 0x9e, 0xc6, 0xf9, 0x5f, 0xfd, 0x67, 0x99, 0xe8, 0x5e, ++ 0xd1, 0xb1, 0x00, 0xea, 0xab, 0xbd, 0x06, 0xdf, 0x04, 0xdc, 0x6f, 0x9e, ++ 0xed, 0x7b, 0xe6, 0x20, 0x5c, 0x3f, 0x99, 0x9f, 0xa5, 0xa3, 0xf6, 0xcf, ++ 0x4b, 0xcc, 0x8e, 0x70, 0x70, 0xb4, 0xa6, 0xe3, 0xfb, 0x95, 0x92, 0xe2, ++ 0xc7, 0xfd, 0x55, 0xbf, 0x65, 0x55, 0x6d, 0xbc, 0x3e, 0xd2, 0x95, 0x2a, ++ 0x13, 0x7e, 0x2a, 0xf3, 0xd6, 0xa5, 0x47, 0xac, 0x44, 0xef, 0x37, 0xa2, ++ 0x9c, 0x6b, 0xdc, 0xa1, 0x27, 0xbd, 0xee, 0xf0, 0x82, 0x0f, 0x7f, 0x73, ++ 0xb3, 0x2b, 0x46, 0xef, 0x2b, 0xe5, 0x9e, 0x1b, 0x67, 0xc4, 0xe9, 0x1b, ++ 0xcd, 0xdb, 0xbf, 0x2d, 0xe8, 0x01, 0x24, 0x36, 0xc0, 0x69, 0xa5, 0x80, ++ 0x93, 0x31, 0x6f, 0x5d, 0x11, 0x8e, 0xfb, 0x4d, 0xf4, 0xbf, 0xf2, 0xbe, ++ 0x96, 0x22, 0x1e, 0xaf, 0xf9, 0xfa, 0x7d, 0x10, 0xdd, 0xdf, 0xdb, 0xf9, ++ 0x7e, 0xf8, 0x33, 0xc8, 0xfb, 0x8b, 0xe8, 0xef, 0xcb, 0x76, 0x6a, 0xf4, ++ 0xfb, 0xd1, 0xec, 0x20, 0xd5, 0x1f, 0x6d, 0xf2, 0x32, 0xdf, 0x1e, 0x2b, ++ 0xc5, 0x15, 0x7d, 0x68, 0xe7, 0x16, 0xb8, 0x14, 0xaa, 0x2f, 0x40, 0x02, ++ 0x02, 0xfa, 0x52, 0xfe, 0xb0, 0x76, 0xef, 0x3b, 0x30, 0xff, 0xfd, 0xa9, ++ 0x01, 0x8b, 0x0b, 0xca, 0x79, 0xcc, 0x57, 0x8a, 0x78, 0xf5, 0x0c, 0xd9, ++ 0xab, 0x40, 0x9d, 0xc4, 0x25, 0x91, 0xfe, 0xc3, 0xb6, 0x1b, 0xb9, 0x3e, ++ 0xa9, 0x70, 0xbf, 0xdc, 0xe6, 0x34, 0xf6, 0xf4, 0x86, 0xb8, 0x79, 0xe6, ++ 0x8a, 0xfe, 0x60, 0x7f, 0xba, 0xb0, 0x9f, 0x33, 0x1f, 0xfc, 0xe9, 0x4d, ++ 0x84, 0x5f, 0x53, 0xee, 0xe7, 0x53, 0x78, 0xbc, 0xed, 0x2b, 0x8a, 0x5f, ++ 0x59, 0x07, 0x78, 0x5c, 0xd3, 0xea, 0xf5, 0x33, 0xa4, 0x8b, 0xe6, 0x81, ++ 0xf9, 0x6c, 0x59, 0x49, 0x8c, 0x1f, 0x36, 0x7b, 0x39, 0xbf, 0x1e, 0xc6, ++ 0x57, 0x5c, 0x7a, 0xce, 0xbf, 0x5c, 0x43, 0xd4, 0x4f, 0x4d, 0x1a, 0xe7, ++ 0x67, 0xaa, 0x3f, 0x78, 0x5b, 0x6b, 0x12, 0xf9, 0xfd, 0xb6, 0xb9, 0x42, ++ 0x66, 0x6e, 0xdf, 0x06, 0x19, 0xf2, 0xf3, 0xeb, 0xca, 0x65, 0x1e, 0x8f, ++ 0x11, 0x7a, 0x89, 0x5f, 0xf8, 0xd1, 0x4c, 0xbe, 0xd7, 0x19, 0xc6, 0x6b, ++ 0x98, 0x57, 0xf6, 0x8e, 0x83, 0xf2, 0xa0, 0xef, 0x78, 0x67, 0x2a, 0x94, ++ 0xdf, 0x29, 0x9f, 0xed, 0x95, 0xa1, 0x6c, 0xf5, 0x3d, 0xd9, 0x55, 0x80, ++ 0xeb, 0xf6, 0xea, 0x45, 0xfd, 0x58, 0xf2, 0x27, 0xbe, 0x3d, 0xb3, 0x92, ++ 0xf4, 0x93, 0xeb, 0x7c, 0x32, 0x8d, 0xcb, 0xea, 0x93, 0xc9, 0x5e, 0x1f, ++ 0xf4, 0xbd, 0xe7, 0x5a, 0x06, 0xe3, 0x5e, 0xcf, 0x7c, 0xa9, 0x27, 0x60, ++ 0x8c, 0x1a, 0x10, 0xd6, 0x88, 0xc7, 0x41, 0x1c, 0x1b, 0xf0, 0x65, 0x54, ++ 0x02, 0xd3, 0x5d, 0x71, 0x76, 0xd3, 0xb7, 0xbd, 0x73, 0x53, 0x4f, 0xc4, ++ 0xcb, 0x4b, 0x1f, 0x97, 0xff, 0x68, 0x8f, 0xf7, 0x89, 0xb8, 0xc2, 0x48, ++ 0x70, 0xf0, 0xa6, 0x56, 0x5e, 0x85, 0xf0, 0xbd, 0xfa, 0x2a, 0x8e, 0x87, ++ 0xcf, 0x9e, 0xe7, 0xf6, 0xc7, 0x67, 0x66, 0xee, 0xe7, 0x56, 0xdb, 0x7d, ++ 0x66, 0xe3, 0x72, 0xc6, 0xef, 0x52, 0xfd, 0x84, 0x7d, 0xb9, 0xc8, 0xe7, ++ 0xa3, 0xe5, 0xdb, 0x8a, 0x35, 0x71, 0x62, 0x97, 0xa1, 0x2f, 0x17, 0xf7, ++ 0xd9, 0x6f, 0x25, 0x6d, 0x3f, 0xab, 0xbb, 0x74, 0x14, 0xbf, 0x5d, 0xd5, ++ 0xc5, 0x28, 0x5e, 0xfb, 0xd9, 0x8f, 0x5e, 0xce, 0x45, 0x7e, 0xfb, 0xe9, ++ 0x9e, 0x97, 0x73, 0x97, 0xc4, 0xcd, 0x2f, 0xf1, 0x3b, 0xf5, 0x79, 0x8b, ++ 0x3a, 0x9e, 0xf0, 0x4b, 0xa9, 0x7e, 0x4a, 0x97, 0x88, 0x5b, 0x2f, 0xf1, ++ 0x1a, 0xb9, 0x3f, 0x70, 0x14, 0x3f, 0xa5, 0xda, 0x9e, 0x6d, 0xe1, 0xf6, ++ 0xd8, 0x59, 0xe0, 0xee, 0x48, 0x77, 0xea, 0x77, 0x67, 0xeb, 0x93, 0x7c, ++ 0xa8, 0x57, 0x9e, 0x65, 0x26, 0xe2, 0x67, 0x4b, 0x06, 0x84, 0xdf, 0xd3, ++ 0xe7, 0x2b, 0x74, 0xa1, 0xfd, 0xa0, 0x7e, 0x9f, 0xd0, 0xff, 0x23, 0x82, ++ 0x7e, 0xa4, 0x7e, 0x89, 0xec, 0x73, 0x4b, 0xc9, 0x10, 0xf1, 0xd7, 0x55, ++ 0x26, 0xff, 0x9b, 0x63, 0x3c, 0x98, 0xb7, 0xe2, 0x23, 0xfc, 0xcc, 0x45, ++ 0x3c, 0x4a, 0x48, 0xaf, 0x3e, 0x03, 0xae, 0x5b, 0x11, 0x76, 0x9e, 0x51, ++ 0xf1, 0xdf, 0x81, 0x78, 0x58, 0xde, 0xa3, 0xc5, 0x63, 0x8e, 0x4b, 0xc4, ++ 0x33, 0xec, 0x2e, 0xc2, 0xbb, 0xa1, 0xc9, 0xaa, 0xa0, 0x7c, 0x48, 0xef, ++ 0x10, 0xfc, 0xfa, 0x7b, 0x3a, 0xb2, 0x5f, 0x0c, 0x59, 0x6e, 0x2b, 0xf2, ++ 0xa5, 0xab, 0x8b, 0x92, 0x3a, 0x31, 0x2e, 0xef, 0x4a, 0x4a, 0x9e, 0x82, ++ 0x7e, 0xf5, 0x9c, 0xac, 0x62, 0x6a, 0x1f, 0xac, 0xe2, 0x74, 0x1d, 0x4c, ++ 0x67, 0xe4, 0xb7, 0xca, 0x64, 0x2d, 0x12, 0xf1, 0x5b, 0x3b, 0xf7, 0x83, ++ 0x67, 0x4f, 0x67, 0x76, 0xcc, 0x03, 0xf9, 0xa9, 0x8b, 0xeb, 0x0d, 0x6e, ++ 0xe6, 0xdd, 0x22, 0x93, 0x3e, 0xd8, 0x27, 0x51, 0x3c, 0x40, 0xac, 0x5f, ++ 0xe5, 0xeb, 0x48, 0x2f, 0xc8, 0xe7, 0x3e, 0x93, 0x4c, 0x44, 0x2f, 0xd2, ++ 0x80, 0x44, 0xfa, 0x9d, 0xac, 0xeb, 0x5b, 0x84, 0xfd, 0x8e, 0x46, 0x3f, ++ 0x5b, 0x5c, 0xaa, 0x5d, 0xcd, 0xe9, 0x27, 0x5a, 0xfe, 0x1b, 0xd1, 0xcf, ++ 0x6e, 0x75, 0xbc, 0x61, 0xf4, 0x13, 0xa0, 0x38, 0xde, 0x12, 0xb7, 0x69, ++ 0x64, 0xfa, 0x11, 0x7e, 0xd7, 0x4b, 0x6e, 0x3f, 0x5a, 0x1c, 0xf1, 0x7b, ++ 0x26, 0xd5, 0x0f, 0x2d, 0xe1, 0x7a, 0x6b, 0x45, 0x7f, 0xb5, 0x26, 0x6b, ++ 0x58, 0x9e, 0x42, 0xfc, 0xe1, 0xf3, 0x78, 0x7f, 0xea, 0x76, 0xd0, 0x33, ++ 0xd1, 0x1e, 0x51, 0xe3, 0x8e, 0x63, 0x3a, 0x16, 0x7b, 0xb8, 0x9e, 0x3e, ++ 0x18, 0x41, 0xbb, 0xdc, 0x72, 0xb9, 0x89, 0xe4, 0xdc, 0x0f, 0x75, 0x83, ++ 0xf9, 0xa8, 0xcf, 0x27, 0xc6, 0x21, 0x01, 0xb3, 0x0e, 0xe4, 0xf7, 0xc8, ++ 0x63, 0xc8, 0xaf, 0xd8, 0x5a, 0xe5, 0x3f, 0x91, 0x1a, 0x27, 0xef, 0x0f, ++ 0x70, 0xbb, 0xa1, 0xe9, 0x6e, 0x1f, 0xbd, 0x9f, 0x35, 0xc0, 0xe5, 0x7b, ++ 0x73, 0xa1, 0x81, 0xf4, 0xce, 0xe6, 0x7e, 0x29, 0x88, 0x78, 0x6e, 0xf2, ++ 0x1b, 0x42, 0xa6, 0x7c, 0x8a, 0xbb, 0x2c, 0x26, 0xb9, 0xfd, 0xa0, 0xd9, ++ 0xc3, 0xe3, 0x28, 0x9e, 0x76, 0x8a, 0xa3, 0xfc, 0xc0, 0xc3, 0xe3, 0x2c, ++ 0x51, 0x3f, 0x6a, 0x64, 0xe7, 0xbd, 0x48, 0x6f, 0xf5, 0x56, 0xf2, 0x3b, ++ 0x24, 0xc6, 0x63, 0x5e, 0xfa, 0x8b, 0xcc, 0xc7, 0x1f, 0xc7, 0x68, 0xfc, ++ 0xde, 0x52, 0x1e, 0xff, 0xe9, 0x9d, 0xeb, 0x21, 0xbf, 0x46, 0x62, 0x9c, ++ 0x8d, 0x75, 0x69, 0xf7, 0xaf, 0x1a, 0x67, 0x39, 0x6b, 0x03, 0xc0, 0xc0, ++ 0x78, 0x4b, 0x36, 0x9a, 0x09, 0x0f, 0x59, 0x32, 0x87, 0x33, 0x4b, 0x31, ++ 0x71, 0xf9, 0x32, 0x9c, 0x0f, 0x90, 0xbf, 0x36, 0x7d, 0xba, 0x40, 0x8c, ++ 0x88, 0x87, 0x44, 0xf7, 0x35, 0x90, 0x24, 0x96, 0xb3, 0x44, 0xbd, 0x1a, ++ 0xbf, 0xb1, 0x95, 0xf8, 0xf3, 0x51, 0xc3, 0x5d, 0x94, 0xba, 0xff, 0xad, ++ 0xa4, 0x69, 0x7f, 0x4d, 0xbe, 0xc3, 0x3d, 0x3f, 0xc4, 0x7c, 0x86, 0x51, ++ 0xf3, 0x1d, 0x82, 0xc6, 0x5a, 0xac, 0x37, 0xa1, 0xf6, 0x2c, 0xea, 0x71, ++ 0xda, 0x20, 0x6f, 0xd5, 0xb2, 0xcf, 0xec, 0xc1, 0xf8, 0x4e, 0xac, 0x5e, ++ 0x01, 0xbd, 0xd1, 0xd4, 0x2f, 0x89, 0xf1, 0x5e, 0xbe, 0x76, 0x36, 0x88, ++ 0xe0, 0xb3, 0x92, 0x3a, 0x7e, 0xe7, 0x06, 0x9f, 0x95, 0xe2, 0xc9, 0x9a, ++ 0xf1, 0xe2, 0xe7, 0xa7, 0x24, 0xf4, 0xaf, 0x87, 0xfe, 0xad, 0x1e, 0xd1, ++ 0x3e, 0xf8, 0xe3, 0xb9, 0xb3, 0x0b, 0x29, 0x6e, 0x29, 0xea, 0xa5, 0x0d, ++ 0x3e, 0x98, 0xdf, 0xc3, 0x7a, 0x6d, 0x7f, 0x04, 0x52, 0xf1, 0x3d, 0x16, ++ 0xd4, 0xf1, 0x0e, 0x67, 0xd4, 0xfc, 0x70, 0xe3, 0xcc, 0x98, 0xdc, 0x07, ++ 0x3d, 0xc0, 0x9a, 0x36, 0x2d, 0x26, 0xff, 0x1f, 0xf8, 0xb0, 0xb6, 0xe7, ++ 0x32, 0x18, 0xcb, 0x62, 0xff, 0xd2, 0x80, 0x72, 0x55, 0x95, 0xe3, 0xcd, ++ 0x2e, 0x9e, 0xff, 0x90, 0xb8, 0x5f, 0xd3, 0xd3, 0x38, 0xbf, 0x07, 0xfd, ++ 0x35, 0x3d, 0x8d, 0xe4, 0x0e, 0xd7, 0x6b, 0x6b, 0x45, 0xfc, 0x12, 0xf4, ++ 0xd9, 0x39, 0xb8, 0xb5, 0x9a, 0xd7, 0xf9, 0x19, 0xc6, 0x2f, 0x41, 0x5f, ++ 0xc8, 0x4a, 0x23, 0x7d, 0xe1, 0xf3, 0x93, 0x07, 0x11, 0x7f, 0x0b, 0x3e, ++ 0x23, 0x7d, 0xbe, 0xf9, 0x82, 0xc2, 0xfd, 0x2e, 0xa0, 0x77, 0xa0, 0x7e, ++ 0x6e, 0x12, 0x74, 0xce, 0xfa, 0xf5, 0x24, 0x6f, 0x55, 0x3a, 0x58, 0x2d, ++ 0xf8, 0x4f, 0xaf, 0x03, 0xe4, 0x3d, 0xd2, 0xeb, 0x01, 0x69, 0x5a, 0x90, ++ 0xe8, 0xa2, 0x25, 0xf7, 0x06, 0xc0, 0xc1, 0xdf, 0xa7, 0xf9, 0x0a, 0x71, ++ 0x1e, 0xaa, 0xdd, 0x95, 0x38, 0xdf, 0x2b, 0xd3, 0xb8, 0x7d, 0xdc, 0x5c, ++ 0x5c, 0xb5, 0xb5, 0x08, 0xfb, 0x7f, 0x4a, 0x62, 0x28, 0xef, 0x37, 0x14, ++ 0x1f, 0x4b, 0x47, 0xbd, 0xa4, 0x79, 0xe0, 0xe3, 0xf4, 0xe5, 0x71, 0xdf, ++ 0xad, 0xea, 0x7f, 0x94, 0xe0, 0xb0, 0x6a, 0xaf, 0x7e, 0xc4, 0xf5, 0x5f, ++ 0x99, 0xc6, 0xe3, 0x9d, 0x4d, 0xaf, 0xbc, 0x48, 0xfe, 0xc1, 0xcf, 0x42, ++ 0x12, 0xed, 0xe5, 0x7a, 0x25, 0xd4, 0x3d, 0x03, 0xca, 0xf5, 0xf5, 0x3a, ++ 0xd4, 0xd0, 0x58, 0x79, 0x68, 0xf1, 0xcd, 0xe4, 0xef, 0xaf, 0x33, 0xb0, ++ 0x71, 0xb0, 0xbe, 0xb1, 0x28, 0x8f, 0x70, 0x1e, 0x7b, 0xbf, 0x13, 0x9c, ++ 0x81, 0xf6, 0x19, 0xfc, 0x93, 0xe0, 0xd5, 0x36, 0xff, 0x0a, 0x92, 0x7b, ++ 0xdb, 0xea, 0x4c, 0x56, 0x8c, 0x3b, 0x34, 0x17, 0x2f, 0xb9, 0x83, 0xe0, ++ 0x60, 0x4f, 0xf2, 0x21, 0x1c, 0x36, 0x14, 0x57, 0x65, 0xe2, 0x38, 0x4d, ++ 0xf3, 0xe7, 0xd8, 0x29, 0x4e, 0x00, 0xfa, 0x15, 0xd6, 0x37, 0xdd, 0x7d, ++ 0x0b, 0xf9, 0x4d, 0xd4, 0x79, 0x6d, 0xe8, 0xd7, 0xd7, 0xa0, 0xde, 0x55, ++ 0x01, 0x7a, 0xd6, 0x3f, 0xc1, 0xbc, 0x73, 0x9c, 0xf3, 0x6a, 0xbc, 0xb0, ++ 0xff, 0xc6, 0xc8, 0xfb, 0x4a, 0xef, 0xb4, 0x62, 0xdc, 0x78, 0x64, 0xfe, ++ 0xfb, 0x5e, 0x3a, 0xc7, 0x67, 0xa7, 0xe4, 0x0f, 0x5e, 0x5f, 0x4e, 0x7e, ++ 0x42, 0x16, 0xef, 0xf7, 0xcb, 0xeb, 0xe7, 0xfa, 0xdc, 0x0d, 0x69, 0x06, ++ 0x8d, 0x5f, 0xf8, 0x86, 0x34, 0x85, 0xe0, 0x30, 0x33, 0x38, 0x38, 0x0b, ++ 0x69, 0xef, 0x35, 0x25, 0x62, 0x41, 0xbd, 0xb7, 0x99, 0xf9, 0xbe, 0x40, ++ 0xfb, 0x92, 0xf9, 0xad, 0x9e, 0x3d, 0x84, 0x27, 0xce, 0x47, 0x5c, 0x6d, ++ 0x1e, 0xf2, 0x1f, 0x99, 0x5c, 0x91, 0x1f, 0x5e, 0x86, 0xf5, 0x33, 0x15, ++ 0xb2, 0x1f, 0x98, 0x12, 0x79, 0x04, 0xc7, 0x3d, 0xd3, 0xed, 0xf2, 0x6e, ++ 0x60, 0x82, 0x7e, 0xb1, 0x7c, 0x77, 0x49, 0x08, 0xf9, 0xe8, 0xeb, 0x69, ++ 0x81, 0x25, 0x88, 0xdf, 0x0a, 0xa1, 0x3f, 0x9e, 0x79, 0xe5, 0x9a, 0x52, ++ 0xf4, 0xb3, 0xa9, 0xfa, 0x51, 0xf7, 0x2e, 0x73, 0x08, 0xe3, 0x84, 0xdd, ++ 0x36, 0xcf, 0x3f, 0xd4, 0x20, 0x1f, 0xfc, 0x83, 0xc2, 0xe3, 0xe2, 0xa6, ++ 0xa1, 0xc1, 0x59, 0x88, 0x8f, 0x3f, 0x3a, 0xa9, 0xdf, 0x6e, 0x73, 0xa8, ++ 0x1b, 0xf1, 0x1f, 0xdc, 0xa4, 0xa7, 0xfa, 0x57, 0x6c, 0x81, 0x46, 0xa4, ++ 0xcb, 0x53, 0xf3, 0x6b, 0x8a, 0x28, 0x2f, 0xc7, 0x1a, 0x2c, 0xc2, 0x38, ++ 0xb0, 0xde, 0xd5, 0xc3, 0x50, 0x4f, 0x00, 0x73, 0x81, 0xfc, 0x09, 0x26, ++ 0x97, 0x9f, 0x61, 0xbc, 0x74, 0x56, 0x70, 0xb1, 0x22, 0x21, 0x9f, 0x4f, ++ 0xd0, 0x3b, 0x66, 0x89, 0xfc, 0x52, 0x62, 0x9e, 0xf0, 0xbe, 0x4a, 0xb0, ++ 0xb1, 0x71, 0x40, 0x05, 0x27, 0x4d, 0xb4, 0x05, 0x3a, 0x2f, 0xa6, 0xc6, ++ 0xf4, 0x90, 0x23, 0x7f, 0x5a, 0xa8, 0xe0, 0x4b, 0x55, 0x3f, 0xd1, 0x99, ++ 0x78, 0x3c, 0xab, 0xba, 0x2e, 0x89, 0xc9, 0x48, 0xf7, 0xeb, 0x87, 0xde, ++ 0xd4, 0xa1, 0xff, 0xda, 0x35, 0x48, 0xfa, 0x6b, 0x63, 0x9f, 0x44, 0xe3, ++ 0x34, 0x16, 0xbf, 0x40, 0xf9, 0x62, 0x6b, 0x44, 0x5e, 0x52, 0x34, 0x3f, ++ 0x48, 0x89, 0x50, 0xbe, 0xd4, 0xfa, 0x34, 0x8b, 0xd0, 0x03, 0x3b, 0xb9, ++ 0x1e, 0xcd, 0x06, 0xc9, 0x5e, 0x66, 0xcf, 0x71, 0x7c, 0x32, 0x16, 0xa1, ++ 0x3c, 0xaa, 0x98, 0x1d, 0xd1, 0x4e, 0xed, 0xd4, 0xfe, 0x0c, 0xc2, 0xef, ++ 0xde, 0x28, 0xfc, 0x2e, 0x20, 0xc1, 0xa8, 0x7e, 0x53, 0x9a, 0xaa, 0x5f, ++ 0xde, 0xa7, 0xf5, 0xd7, 0x8b, 0x71, 0x37, 0x4b, 0x83, 0x3e, 0x19, 0xe1, ++ 0x5a, 0x2a, 0x69, 0xfc, 0xc5, 0xea, 0x73, 0xaf, 0xf8, 0x3e, 0xe5, 0xd0, ++ 0xd0, 0x1c, 0xdc, 0xbf, 0x43, 0xaf, 0xa8, 0x79, 0x9c, 0x3c, 0x4f, 0x73, ++ 0xeb, 0xb4, 0x89, 0x5e, 0x54, 0x9d, 0x86, 0xe5, 0x71, 0xf6, 0x7f, 0x31, ++ 0x07, 0xe9, 0x06, 0x14, 0x6d, 0xda, 0xaf, 0x4d, 0xfd, 0x97, 0x96, 0xc7, ++ 0xf9, 0xbc, 0xd8, 0x67, 0xff, 0xe3, 0x79, 0x9c, 0x5e, 0xc9, 0xb7, 0x1b, ++ 0x9e, 0x2f, 0xa7, 0x39, 0xb4, 0x79, 0x9c, 0x5e, 0x0e, 0x3f, 0x35, 0xce, ++ 0x96, 0x98, 0xbf, 0x79, 0x26, 0x33, 0xac, 0xf0, 0x7c, 0xac, 0xc8, 0xce, ++ 0x3d, 0x48, 0x9f, 0xfd, 0x46, 0xca, 0xf3, 0xaa, 0xed, 0xff, 0xd9, 0xfb, ++ 0x28, 0x1f, 0x6b, 0x4d, 0xac, 0x0f, 0xe3, 0x90, 0x89, 0x7a, 0x46, 0x9b, ++ 0xfd, 0x3b, 0x61, 0xa4, 0xfb, 0xb3, 0xa7, 0x4f, 0xee, 0xbc, 0x9f, 0x61, ++ 0x1e, 0xef, 0x4b, 0x5e, 0xca, 0xe7, 0x48, 0xd0, 0x1f, 0x12, 0xed, 0x84, ++ 0xdd, 0xd8, 0x24, 0x73, 0x74, 0x7d, 0xef, 0x37, 0x51, 0x7c, 0x72, 0x7d, ++ 0x2f, 0x5a, 0xfe, 0x1f, 0xd7, 0xf7, 0xb8, 0x3e, 0x1f, 0xdc, 0xc3, 0xf3, ++ 0x07, 0x54, 0x7e, 0xde, 0x2c, 0xec, 0xb3, 0xb3, 0xf5, 0xe7, 0x92, 0x51, ++ 0xce, 0x1c, 0x4b, 0x53, 0xf5, 0xcf, 0x84, 0x3c, 0x87, 0xa7, 0x44, 0x9e, ++ 0xc3, 0xc0, 0xc8, 0x79, 0x0e, 0x8a, 0xc8, 0x17, 0x02, 0x7d, 0x3d, 0x48, ++ 0x74, 0xb2, 0x8f, 0xc7, 0x75, 0x8e, 0x3c, 0x6d, 0x21, 0xfe, 0x71, 0xce, ++ 0xae, 0xec, 0x46, 0x7d, 0xe9, 0xb4, 0x6d, 0xe8, 0xfb, 0x08, 0x2c, 0x45, ++ 0xe8, 0x49, 0x9d, 0x07, 0x8c, 0x1e, 0xe4, 0x17, 0xc0, 0xef, 0x88, 0x7f, ++ 0x07, 0xf7, 0xe9, 0x79, 0x9c, 0x06, 0xe3, 0x36, 0x18, 0xc7, 0x79, 0x6d, ++ 0x82, 0x88, 0xe3, 0x88, 0x78, 0xd1, 0xab, 0x16, 0xd2, 0x5b, 0x1a, 0x92, ++ 0x3d, 0x29, 0xf8, 0xbd, 0x1a, 0xa7, 0xf9, 0xa9, 0x90, 0x37, 0x0d, 0x49, ++ 0x3c, 0x3e, 0xd3, 0x65, 0x09, 0xfc, 0x3e, 0x6d, 0x84, 0xb8, 0xcd, 0x2e, ++ 0xa1, 0x7f, 0xed, 0x82, 0xae, 0xec, 0xd8, 0xdf, 0xfb, 0x46, 0x11, 0xc7, ++ 0x06, 0x06, 0x81, 0xf6, 0xce, 0x83, 0x39, 0x3c, 0xee, 0x20, 0xe2, 0x36, ++ 0x67, 0x45, 0xdc, 0xe6, 0x78, 0xb1, 0x2e, 0x6c, 0xe0, 0x7e, 0x08, 0xf2, ++ 0x53, 0x79, 0xba, 0x14, 0x96, 0x09, 0xf5, 0x9e, 0xf7, 0xcd, 0x21, 0x0f, ++ 0xf7, 0x67, 0x99, 0x74, 0x20, 0xf7, 0x97, 0xaa, 0x71, 0x9b, 0xd7, 0xb8, ++ 0x9f, 0x6a, 0xa9, 0x88, 0xcf, 0x1c, 0x5f, 0x30, 0x87, 0xf2, 0x87, 0x96, ++ 0x63, 0x7e, 0xbc, 0x8c, 0x7e, 0x0c, 0xee, 0x67, 0x8e, 0xe6, 0xeb, 0x33, ++ 0xbb, 0x0e, 0xd7, 0xb3, 0x06, 0xd8, 0xc5, 0x36, 0x64, 0x31, 0x41, 0x80, ++ 0xfa, 0xe5, 0xf0, 0x5a, 0xd2, 0x49, 0xa8, 0x4f, 0x78, 0x3a, 0xa1, 0x4c, ++ 0xca, 0xb2, 0xaf, 0xa7, 0x06, 0xc6, 0x5d, 0xd2, 0xa9, 0x23, 0x7b, 0x64, ++ 0x69, 0x97, 0xd6, 0x5f, 0x7e, 0x7e, 0xc3, 0x1d, 0x35, 0x28, 0xbf, 0x1f, ++ 0xe8, 0xe4, 0xf1, 0xc7, 0x60, 0x97, 0x44, 0xf2, 0x7b, 0x29, 0xf3, 0xb9, ++ 0x51, 0xdf, 0x50, 0xe9, 0x61, 0x5c, 0x7a, 0x2a, 0xd1, 0x59, 0xb0, 0x53, ++ 0xe7, 0xc3, 0x71, 0xae, 0x4c, 0xe7, 0xfe, 0x04, 0x00, 0x7d, 0x88, 0xd6, ++ 0x27, 0x9e, 0x9d, 0x7a, 0xe1, 0x67, 0x17, 0xf3, 0x68, 0x67, 0xba, 0x30, ++ 0x3e, 0x75, 0x12, 0x7f, 0x3e, 0x60, 0x57, 0x6a, 0x46, 0x94, 0xcb, 0xa2, ++ 0xbf, 0x4e, 0x7d, 0x8b, 0xa9, 0x12, 0xf5, 0xd8, 0x1c, 0x1d, 0xf9, 0x79, ++ 0xcf, 0x1b, 0x7c, 0x75, 0xe4, 0x27, 0x75, 0x16, 0x11, 0xde, 0x3a, 0x6d, ++ 0x2d, 0x5d, 0x35, 0xbc, 0x9e, 0xf6, 0xca, 0x79, 0xf3, 0x90, 0x9f, 0xea, ++ 0xaf, 0x54, 0xb8, 0xa2, 0xc7, 0x3c, 0x4e, 0xe4, 0x93, 0x63, 0xd2, 0x45, ++ 0xfc, 0x26, 0x61, 0xbd, 0xcb, 0x7b, 0xb4, 0xe5, 0xc4, 0xf8, 0xc3, 0xaa, ++ 0x90, 0xb6, 0xbc, 0x94, 0x05, 0xc6, 0x67, 0xe2, 0x39, 0x85, 0xbd, 0xda, ++ 0xf7, 0x63, 0xd2, 0x39, 0xff, 0x3f, 0xbf, 0x21, 0x5f, 0xf8, 0xf9, 0xbd, ++ 0xe4, 0xe7, 0xef, 0xd4, 0x7b, 0x7e, 0x95, 0x8f, 0x7c, 0xaa, 0x5b, 0x21, ++ 0x3e, 0xd9, 0x9e, 0xcd, 0xe1, 0xa5, 0xcb, 0xe1, 0xcf, 0x02, 0x47, 0x75, ++ 0x1d, 0xe9, 0x07, 0x0e, 0xd0, 0x2b, 0x68, 0xbe, 0x7c, 0xfe, 0x05, 0x57, ++ 0xba, 0x24, 0x94, 0x97, 0x9d, 0x0e, 0x4e, 0x97, 0xff, 0xdd, 0x79, 0x27, ++ 0xce, 0x77, 0x76, 0x7a, 0x11, 0xd7, 0x13, 0x50, 0xb9, 0xc3, 0x7d, 0xd4, ++ 0x2d, 0x85, 0x38, 0xbc, 0xf8, 0xbc, 0x2f, 0xd5, 0x5f, 0xb1, 0x22, 0x5d, ++ 0x6b, 0x6f, 0x46, 0xcb, 0xff, 0xf3, 0xf6, 0x26, 0xa7, 0xc7, 0x6e, 0x59, ++ 0xec, 0x37, 0x3b, 0xf1, 0x9f, 0x25, 0x22, 0xde, 0x78, 0x5c, 0xf2, 0x3e, ++ 0x1d, 0xc6, 0xf7, 0x56, 0xd0, 0x0b, 0x60, 0xde, 0x4b, 0xbb, 0xe5, 0x32, ++ 0xd4, 0x4f, 0x66, 0x7d, 0xc7, 0x4a, 0xeb, 0x68, 0x7a, 0xcd, 0x1c, 0x32, ++ 0x42, 0x7d, 0xe3, 0xba, 0x48, 0x2e, 0xee, 0xa3, 0xa6, 0xaa, 0x48, 0x51, ++ 0xcb, 0x08, 0x70, 0xc5, 0xd9, 0x2a, 0x2a, 0xdf, 0x82, 0x76, 0x4b, 0x5c, ++ 0x60, 0x1f, 0xe0, 0xbe, 0xed, 0xd2, 0xc6, 0xa1, 0x86, 0xc7, 0x15, 0x7d, ++ 0xf7, 0xa6, 0xa7, 0xa1, 0x1d, 0x72, 0x7c, 0xdf, 0xcf, 0x10, 0xdf, 0xfb, ++ 0xcc, 0x24, 0x97, 0xe0, 0xbf, 0x0e, 0x1a, 0xd1, 0xdf, 0xf1, 0x4a, 0x3e, ++ 0xe9, 0x4b, 0x53, 0x52, 0x02, 0x1d, 0xe9, 0x28, 0xcf, 0x93, 0xc2, 0x3b, ++ 0x9f, 0xc9, 0x47, 0xfd, 0x84, 0xeb, 0x47, 0x8d, 0x03, 0xc6, 0x5d, 0xa8, ++ 0xff, 0x2d, 0xe9, 0xd4, 0x9e, 0xab, 0x61, 0x1b, 0xb5, 0x71, 0x2e, 0xd6, ++ 0xe5, 0x24, 0x7f, 0x06, 0xeb, 0xd5, 0xbe, 0xc7, 0xf3, 0x2b, 0x9a, 0xef, ++ 0x86, 0xc5, 0xbd, 0xb8, 0x9c, 0xdf, 0x6c, 0x08, 0x4c, 0x40, 0xbd, 0xee, ++ 0xea, 0xab, 0x78, 0x7c, 0xfd, 0xf4, 0x2a, 0x1d, 0x43, 0xfc, 0x2e, 0x95, ++ 0xbd, 0x2b, 0x90, 0x8f, 0x9c, 0x36, 0x6b, 0xf5, 0xee, 0xd3, 0x36, 0x8e, ++ 0xaf, 0xdd, 0xe9, 0xaa, 0x9c, 0xf1, 0x16, 0x21, 0x9e, 0xa3, 0xe5, 0x61, ++ 0x78, 0xf6, 0x16, 0x21, 0x9e, 0x97, 0xea, 0x58, 0x20, 0xbe, 0x9f, 0x46, ++ 0xc4, 0xf3, 0x54, 0xcc, 0x4e, 0xe7, 0x78, 0x3e, 0xfd, 0xe2, 0xe5, 0x45, ++ 0x88, 0xe7, 0xcf, 0xf7, 0x5d, 0x5e, 0x84, 0x78, 0xde, 0xac, 0xef, 0xf1, ++ 0xe1, 0xbe, 0x79, 0xc6, 0x19, 0x78, 0x1a, 0xe1, 0x73, 0x62, 0xb6, 0x9f, ++ 0xf4, 0x26, 0x35, 0xaf, 0xf2, 0x52, 0xe9, 0xb1, 0x3f, 0x81, 0x1e, 0xfb, ++ 0xff, 0xdf, 0xd1, 0x63, 0x5d, 0x7c, 0xbe, 0x5f, 0xa2, 0x1c, 0x3c, 0x1c, ++ 0x85, 0x97, 0x56, 0x0e, 0xba, 0x0c, 0x9e, 0x6c, 0xe4, 0x87, 0x4b, 0x4c, ++ 0xc6, 0xaf, 0x95, 0x87, 0xf8, 0x37, 0xa2, 0x3f, 0xcd, 0x64, 0x24, 0x7f, ++ 0xc4, 0x6b, 0x7f, 0xfa, 0xf2, 0x21, 0x94, 0x6f, 0xc1, 0x01, 0x99, 0xf4, ++ 0x0f, 0xb5, 0xbf, 0xd7, 0x94, 0xc0, 0x58, 0xf4, 0x17, 0xbc, 0xf6, 0xbe, ++ 0xdb, 0x1b, 0x94, 0x46, 0xef, 0xbf, 0x45, 0xe8, 0x55, 0x6e, 0x13, 0x0b, ++ 0xa2, 0xdf, 0x43, 0xd5, 0xf7, 0x55, 0xbd, 0x31, 0x91, 0x1f, 0xbf, 0x2f, ++ 0xe0, 0x78, 0x2a, 0xdd, 0x57, 0x8b, 0x7a, 0xb6, 0xea, 0x9f, 0xad, 0x17, ++ 0x7d, 0x9a, 0x42, 0x5f, 0x72, 0xfd, 0xf4, 0x29, 0x89, 0xfc, 0xaf, 0x26, ++ 0x4f, 0x1f, 0xcf, 0xaf, 0x3f, 0xb0, 0xd8, 0x8e, 0xfe, 0xd9, 0x53, 0x21, ++ 0xee, 0x8f, 0x6d, 0x7a, 0xb1, 0x94, 0xfc, 0xb5, 0xab, 0x42, 0xaf, 0x87, ++ 0x31, 0xff, 0x89, 0x0d, 0x48, 0x76, 0xb4, 0x1b, 0x56, 0x3d, 0xf5, 0x71, ++ 0x32, 0xc6, 0xb3, 0xc1, 0x0e, 0xfd, 0x24, 0x3d, 0x2e, 0xbe, 0x32, 0x5b, ++ 0xd8, 0xa1, 0xa7, 0x42, 0xc7, 0x93, 0x31, 0xee, 0x0d, 0xe3, 0xd7, 0xa0, ++ 0x5c, 0xb6, 0xb8, 0x86, 0x0c, 0x48, 0xbf, 0x4d, 0x60, 0x9f, 0x41, 0x13, ++ 0xd6, 0xa4, 0x0c, 0xd1, 0xb9, 0xa2, 0x26, 0x17, 0x23, 0x79, 0x5f, 0xde, ++ 0xaf, 0xb5, 0xd7, 0xd4, 0xf8, 0xe4, 0x36, 0xbf, 0x81, 0xf8, 0xdd, 0xb6, ++ 0x01, 0x29, 0x84, 0xf6, 0x59, 0xba, 0x21, 0x90, 0x9f, 0x8d, 0xf2, 0x89, ++ 0x65, 0xdb, 0x4f, 0x5a, 0x62, 0xfb, 0xe5, 0x77, 0xe9, 0x3e, 0x17, 0xc6, ++ 0x2d, 0x63, 0x71, 0x61, 0xdf, 0xef, 0x71, 0x5e, 0xaa, 0x5f, 0x27, 0xb2, ++ 0x35, 0x85, 0xe8, 0x30, 0xa2, 0x67, 0x3e, 0xd2, 0x03, 0xb6, 0xda, 0x04, ++ 0x5f, 0xe2, 0xf1, 0x9a, 0xdf, 0x6d, 0x77, 0x84, 0x78, 0xfe, 0x12, 0x6f, ++ 0xff, 0xbb, 0x50, 0x3e, 0x95, 0x55, 0x79, 0xbd, 0x42, 0x9c, 0xd3, 0x5b, ++ 0x21, 0xce, 0xe9, 0x21, 0xff, 0x0e, 0x27, 0xf0, 0xef, 0xf8, 0x72, 0x34, ++ 0xde, 0xac, 0x9e, 0x47, 0x03, 0x7e, 0x1e, 0x1e, 0x29, 0xfe, 0x1d, 0x97, ++ 0xb7, 0x14, 0xff, 0x7d, 0x13, 0x1b, 0x12, 0xf9, 0x79, 0x17, 0x8d, 0x9a, ++ 0x7e, 0xa3, 0xf9, 0x3a, 0x2d, 0xa5, 0x1e, 0x98, 0xf7, 0x9a, 0xdb, 0xac, ++ 0x74, 0x0e, 0xb1, 0x19, 0xe8, 0xba, 0xb5, 0x2c, 0x46, 0x87, 0x0d, 0x62, ++ 0x29, 0x2a, 0x1d, 0x36, 0x09, 0xbf, 0x6e, 0x73, 0xfd, 0x31, 0xb2, 0x03, ++ 0x9a, 0xf1, 0xfc, 0x05, 0xea, 0x55, 0x5e, 0x4e, 0x87, 0x0d, 0x60, 0x1f, ++ 0x61, 0x7e, 0x67, 0xe2, 0xbe, 0x65, 0x7d, 0xda, 0x7c, 0xc6, 0xd1, 0xf6, ++ 0x71, 0x69, 0x86, 0x76, 0x1f, 0x47, 0xcb, 0x7f, 0x23, 0x3f, 0xe6, 0xcc, ++ 0x0c, 0xed, 0xfe, 0x55, 0xd7, 0xaf, 0xfa, 0xc1, 0xa3, 0xeb, 0x1c, 0x90, ++ 0xf8, 0xfe, 0x4a, 0x58, 0x57, 0xa2, 0x5d, 0x99, 0xe8, 0xbf, 0x56, 0xed, ++ 0xc2, 0x4b, 0xe5, 0x6b, 0xdf, 0x89, 0xce, 0x87, 0xc3, 0x23, 0x5a, 0xfe, ++ 0x1b, 0xf3, 0xb5, 0xdb, 0x33, 0x46, 0xe3, 0x6b, 0xda, 0xf8, 0xc0, 0x5f, ++ 0xcd, 0xd7, 0x12, 0xe3, 0x04, 0x85, 0xdc, 0xff, 0x8d, 0x71, 0x02, 0x8c, ++ 0xdb, 0xfe, 0x77, 0xe3, 0x04, 0x9f, 0x7a, 0x7a, 0xd2, 0x75, 0x3c, 0x4f, ++ 0x5f, 0x13, 0x3f, 0xed, 0x92, 0x5a, 0xae, 0x33, 0x8d, 0xc5, 0xb8, 0x22, ++ 0x8f, 0x2f, 0x37, 0xda, 0x8c, 0x14, 0x87, 0x4d, 0x8c, 0xab, 0x36, 0x7b, ++ 0xe6, 0x88, 0x38, 0xe2, 0xe0, 0x6f, 0xae, 0x40, 0xb9, 0xb9, 0x5f, 0xcf, ++ 0x50, 0x9e, 0xd7, 0x5b, 0x57, 0x52, 0xbc, 0xb2, 0x59, 0x7e, 0xce, 0x80, ++ 0x47, 0x0e, 0x87, 0xc5, 0x13, 0x95, 0x83, 0xa4, 0xb7, 0xff, 0xb5, 0x71, ++ 0xf5, 0xf5, 0x19, 0x36, 0x17, 0xf1, 0x23, 0x0f, 0xcb, 0xc7, 0xb8, 0x7a, ++ 0x62, 0x5e, 0xd1, 0xeb, 0xd6, 0x2f, 0x53, 0x03, 0x71, 0xf8, 0xad, 0x2a, ++ 0x01, 0x85, 0x7f, 0x04, 0x3a, 0x36, 0x29, 0x41, 0x16, 0x7f, 0x5e, 0xad, ++ 0x37, 0x83, 0xeb, 0xc1, 0xaf, 0x8b, 0xfc, 0x17, 0xb7, 0x81, 0xe7, 0xb1, ++ 0x3f, 0x6c, 0x03, 0x3b, 0x0b, 0xd6, 0xe7, 0xd6, 0xf1, 0xfc, 0x9c, 0xbf, ++ 0x4f, 0xf3, 0x6f, 0xce, 0x48, 0x43, 0x3e, 0xce, 0xe1, 0xf7, 0xc4, 0x2b, ++ 0x37, 0x31, 0x3c, 0x77, 0xf4, 0x84, 0xbe, 0x8f, 0xf8, 0x44, 0xb0, 0xd1, ++ 0xea, 0x45, 0x7e, 0xa7, 0xfa, 0x55, 0xa2, 0xe3, 0x09, 0xfb, 0xf3, 0x52, ++ 0xe9, 0xfa, 0xc7, 0x09, 0xfb, 0xfc, 0xc7, 0x7f, 0xe3, 0x7d, 0xde, 0xaf, ++ 0xd2, 0xf3, 0x5f, 0x1b, 0xef, 0xda, 0x02, 0x6b, 0xd5, 0xd0, 0x3f, 0xa3, ++ 0xb8, 0xd6, 0xdb, 0x18, 0xaf, 0xc9, 0x1f, 0x4e, 0xa7, 0xa3, 0xf5, 0x33, ++ 0x1a, 0xbd, 0xfe, 0x22, 0xc3, 0xff, 0x66, 0x06, 0xed, 0x33, 0xdf, 0x14, ++ 0xca, 0xbb, 0xbd, 0x44, 0x7e, 0x62, 0x29, 0x1f, 0x3a, 0x8e, 0xfe, 0x1b, ++ 0xb6, 0xdf, 0xe8, 0x41, 0x7b, 0xc2, 0x24, 0xce, 0x65, 0xb0, 0x8d, 0x99, ++ 0x22, 0x4f, 0xd2, 0x5b, 0x31, 0x9f, 0xf2, 0x85, 0xf9, 0xb9, 0x06, 0xf5, ++ 0xfc, 0xc7, 0x68, 0x7a, 0xdf, 0xc7, 0xd1, 0xfd, 0xce, 0xf5, 0xbe, 0x8f, ++ 0x47, 0xe5, 0x3b, 0xff, 0x35, 0xbd, 0xaf, 0xcd, 0xe9, 0x3f, 0x8e, 0x72, ++ 0xf6, 0x44, 0xa5, 0xaf, 0x08, 0xe5, 0xe2, 0x03, 0x36, 0x98, 0x3f, 0xda, ++ 0x73, 0x3f, 0x32, 0x8e, 0x78, 0xce, 0x42, 0x3d, 0x0f, 0x00, 0xf4, 0xc4, ++ 0xcf, 0x9b, 0x3c, 0xcf, 0xe3, 0xdc, 0x89, 0x74, 0xf5, 0x87, 0x04, 0x7e, ++ 0xf9, 0x87, 0xff, 0x25, 0x7e, 0xa9, 0x77, 0xff, 0x8d, 0xf8, 0x65, 0xfd, ++ 0x1f, 0x93, 0xd1, 0xaf, 0x39, 0x7a, 0x3f, 0x41, 0x9e, 0xf7, 0x5b, 0x35, ++ 0xe8, 0x13, 0x71, 0x29, 0x86, 0x71, 0x21, 0x75, 0x1d, 0xcd, 0x83, 0x3c, ++ 0xbf, 0x2c, 0x5d, 0xe4, 0x4d, 0xa9, 0xef, 0xbf, 0x12, 0x7a, 0xec, 0xed, ++ 0x6e, 0x5f, 0x86, 0x1b, 0x9e, 0x9f, 0x7f, 0x60, 0x32, 0xb1, 0x14, 0x50, ++ 0x71, 0x90, 0xc6, 0x50, 0xdf, 0xf2, 0x5b, 0xc9, 0xdf, 0xdf, 0xd4, 0xc7, ++ 0xf3, 0x40, 0x9a, 0xd6, 0x31, 0x8a, 0xeb, 0xaa, 0xe7, 0x28, 0x9b, 0xfa, ++ 0xe7, 0x33, 0xd4, 0xeb, 0xf6, 0xa7, 0x06, 0xf2, 0xf1, 0xfb, 0x07, 0x3e, ++ 0xb4, 0x06, 0xe5, 0x14, 0xf4, 0x83, 0x2f, 0x60, 0xa8, 0xcf, 0x9d, 0xf9, ++ 0x80, 0x97, 0x5b, 0x52, 0x03, 0xe3, 0xb0, 0xbe, 0x79, 0x5d, 0x44, 0x13, ++ 0x57, 0xa8, 0xb8, 0xf8, 0xe5, 0x7a, 0xf4, 0x57, 0xc0, 0x7c, 0xc9, 0xfe, ++ 0x77, 0x19, 0xb5, 0xe7, 0x29, 0xe6, 0xbb, 0x39, 0x3f, 0x53, 0x9f, 0xd7, ++ 0x09, 0x78, 0x47, 0xd7, 0xe5, 0xe2, 0xf3, 0x64, 0x7d, 0x72, 0x08, 0xf5, ++ 0x40, 0x8b, 0x67, 0x90, 0xfc, 0x44, 0x4d, 0xfb, 0xb9, 0x72, 0x56, 0x21, ++ 0xfb, 0xc8, 0x1f, 0xcf, 0xd6, 0x38, 0xe9, 0x7c, 0x44, 0xd3, 0xfe, 0xca, ++ 0x52, 0x3a, 0x6f, 0xde, 0x67, 0x2e, 0x45, 0x3d, 0xb6, 0xe2, 0xa3, 0x5a, ++ 0x3b, 0xfa, 0x1f, 0x3e, 0xbf, 0xd2, 0x45, 0x79, 0x04, 0xb9, 0x72, 0x64, ++ 0x15, 0xea, 0x51, 0xaf, 0xa7, 0x05, 0x66, 0xe2, 0x7c, 0x6d, 0xe5, 0xa1, ++ 0xb9, 0xa8, 0x87, 0xe6, 0x81, 0x1e, 0x8a, 0x7a, 0xed, 0xe7, 0xfb, 0xe6, ++ 0x96, 0x06, 0xe2, 0xfc, 0xd9, 0x9b, 0xd1, 0x9f, 0x0d, 0xfd, 0x6e, 0xb6, ++ 0x69, 0xfd, 0xd5, 0xcc, 0xc4, 0xf3, 0xc0, 0xeb, 0x77, 0xf3, 0x3c, 0xdf, ++ 0x57, 0x6c, 0x81, 0x39, 0xd8, 0xdf, 0x66, 0x33, 0x9f, 0x6f, 0x70, 0x93, ++ 0xc8, 0x6b, 0x16, 0x7e, 0xec, 0xc4, 0xfd, 0xaf, 0xee, 0xfb, 0xe8, 0x39, ++ 0xc7, 0x5b, 0x4d, 0x14, 0x77, 0x56, 0xf9, 0xc2, 0x66, 0x3d, 0x0b, 0xa0, ++ 0x5c, 0x53, 0xf9, 0x49, 0x89, 0xc8, 0x83, 0x03, 0x78, 0xf0, 0x3c, 0xbc, ++ 0x81, 0xf9, 0x3c, 0x9f, 0x43, 0x94, 0xad, 0x2e, 0x6d, 0x3e, 0xe2, 0xa9, ++ 0xf4, 0xd9, 0x25, 0x38, 0x9f, 0x12, 0x37, 0x8f, 0x0b, 0x2c, 0x37, 0x0d, ++ 0x49, 0xe8, 0x57, 0x5f, 0x2e, 0xe2, 0xec, 0xd7, 0x88, 0x7c, 0x09, 0x35, ++ 0x3f, 0xca, 0xa8, 0xf8, 0xbf, 0x8b, 0xed, 0xd9, 0xba, 0x9a, 0x58, 0x7c, ++ 0xbd, 0x00, 0xbf, 0xb7, 0x8b, 0x73, 0xbf, 0x3c, 0x0f, 0xc6, 0x72, 0x81, ++ 0xeb, 0xc7, 0x05, 0x76, 0x03, 0xd1, 0x8d, 0x0d, 0xf6, 0x17, 0xf9, 0x3f, ++ 0x80, 0x6e, 0x10, 0x3f, 0x33, 0x87, 0x06, 0x67, 0xe1, 0x79, 0xa2, 0xc2, ++ 0xde, 0xf0, 0x4c, 0x84, 0xe7, 0x6b, 0x17, 0x74, 0x04, 0x0f, 0x65, 0xfe, ++ 0xdb, 0x14, 0x1f, 0x49, 0x41, 0xb4, 0x41, 0x3f, 0x63, 0x37, 0x46, 0xba, ++ 0xc7, 0xa3, 0x9f, 0xc4, 0xfe, 0xeb, 0x2b, 0x11, 0x2f, 0x9e, 0x1e, 0x7b, ++ 0x15, 0x82, 0x6e, 0x7f, 0xaa, 0xbf, 0xd1, 0x4d, 0xfe, 0xec, 0x96, 0x62, ++ 0xb4, 0x1b, 0xab, 0xfe, 0x59, 0xcf, 0xf3, 0xfc, 0x0e, 0x58, 0xc8, 0xfe, ++ 0xef, 0xcd, 0x6d, 0xa0, 0x3c, 0xbf, 0x33, 0x1f, 0x1a, 0x47, 0x3c, 0x17, ++ 0xa2, 0x3e, 0x83, 0xec, 0x3e, 0xca, 0xeb, 0x2b, 0xe8, 0x7f, 0x8f, 0xfc, ++ 0xf4, 0xb6, 0xfd, 0xd2, 0x88, 0xf9, 0x9a, 0x5d, 0x6e, 0x2b, 0x8f, 0x1f, ++ 0x05, 0x07, 0x29, 0x7f, 0x8c, 0xcd, 0x74, 0xf1, 0xf3, 0x84, 0x07, 0x3e, ++ 0xa2, 0xb8, 0xae, 0xd2, 0xad, 0x90, 0x87, 0xa2, 0x53, 0xef, 0xd3, 0xe1, ++ 0x39, 0xa8, 0x60, 0x3b, 0x23, 0xff, 0xe4, 0xb8, 0x5e, 0xbb, 0x0e, 0xf1, ++ 0x92, 0x27, 0xf2, 0x47, 0xce, 0xbe, 0xf6, 0x9f, 0x53, 0x02, 0x64, 0x87, ++ 0xa8, 0x7e, 0xf9, 0x10, 0xcf, 0xf7, 0xd1, 0x47, 0xd6, 0xa3, 0x5d, 0xa5, ++ 0xb4, 0x47, 0xae, 0x82, 0x1d, 0xcc, 0x1a, 0xf7, 0x3b, 0x74, 0x4d, 0x25, ++ 0xd8, 0xdf, 0x50, 0x13, 0xcf, 0x5b, 0xb7, 0x30, 0xa4, 0x93, 0xbc, 0xfe, ++ 0xb1, 0xf7, 0x7d, 0x0b, 0xca, 0x79, 0x5d, 0x76, 0x26, 0x21, 0xff, 0x79, ++ 0x75, 0x4d, 0x1e, 0xf9, 0x43, 0x61, 0x9d, 0xe3, 0x46, 0x58, 0xe7, 0x1d, ++ 0x6e, 0x9e, 0x9f, 0xa3, 0x1c, 0xb0, 0xe8, 0x50, 0x6e, 0x29, 0x9b, 0x18, ++ 0xe5, 0x17, 0x2a, 0x8e, 0xf4, 0x2a, 0x9a, 0xf7, 0xa3, 0x50, 0x86, 0x7e, ++ 0xd6, 0x08, 0xba, 0x51, 0xe3, 0x8d, 0x30, 0x5d, 0x37, 0xca, 0xa3, 0xdb, ++ 0xdd, 0x81, 0x1d, 0x88, 0xef, 0xe8, 0x39, 0x98, 0xd6, 0x24, 0x7e, 0x0e, ++ 0x46, 0x9c, 0xbb, 0xb4, 0xb5, 0x7e, 0xf8, 0x3c, 0x9e, 0x2f, 0xd9, 0x69, ++ 0xe0, 0xe7, 0x0c, 0x0f, 0xbd, 0x36, 0x69, 0x01, 0xf9, 0xe5, 0xba, 0x15, ++ 0x09, 0xf1, 0x70, 0xde, 0xb1, 0x38, 0xcf, 0x0e, 0xef, 0xf7, 0x8a, 0x7d, ++ 0x6b, 0x53, 0x06, 0x99, 0xdd, 0x1a, 0x0f, 0xff, 0x43, 0x94, 0x4f, 0x59, ++ 0x70, 0x80, 0xe7, 0x9d, 0x29, 0x7a, 0x4e, 0x27, 0x4a, 0xb7, 0x6b, 0x17, ++ 0xfa, 0xfd, 0x2e, 0xa4, 0x04, 0x28, 0x6f, 0xf4, 0xca, 0xce, 0xb0, 0x4c, ++ 0xf1, 0x2a, 0xfb, 0x89, 0x47, 0x6a, 0x3c, 0x71, 0x76, 0xcb, 0x16, 0x2e, ++ 0x47, 0x9a, 0xf6, 0x72, 0x7b, 0x39, 0xd1, 0x4e, 0xf9, 0x26, 0xf9, 0x71, ++ 0xd0, 0xad, 0xd5, 0x4b, 0xa2, 0xe5, 0xbf, 0x91, 0x5e, 0xf2, 0x76, 0x82, ++ 0xdc, 0xf8, 0xab, 0xed, 0x0f, 0xa6, 0xb5, 0xdb, 0x12, 0xf5, 0x93, 0x44, ++ 0x3b, 0x6d, 0x98, 0x5e, 0x9d, 0xd0, 0xdf, 0x68, 0x7a, 0x8a, 0x9a, 0xb7, ++ 0x51, 0x15, 0x1b, 0x87, 0xe8, 0xe1, 0x75, 0x9b, 0xaa, 0x07, 0x05, 0x35, ++ 0x79, 0x2d, 0x55, 0x56, 0x71, 0xae, 0xcd, 0xa4, 0xed, 0x7f, 0xaf, 0x8b, ++ 0xf3, 0x09, 0x35, 0xcf, 0x25, 0xbd, 0xc3, 0xd3, 0x8e, 0x79, 0xe3, 0x43, ++ 0x3f, 0x60, 0xe4, 0x47, 0x53, 0xf3, 0x6d, 0x82, 0x55, 0xdc, 0x2e, 0x08, ++ 0xea, 0x4c, 0x74, 0xde, 0xcd, 0xcd, 0x7a, 0x28, 0xcf, 0x66, 0x0c, 0x0b, ++ 0x4b, 0x12, 0xe9, 0xf7, 0x11, 0x3a, 0xd7, 0x99, 0x81, 0xf9, 0x36, 0xf0, ++ 0xdd, 0x07, 0xee, 0x02, 0x7e, 0x3e, 0x85, 0x79, 0xbb, 0x64, 0xe2, 0x87, ++ 0x1e, 0x09, 0xe7, 0x6d, 0xc6, 0x3c, 0x0d, 0xca, 0xcb, 0x0c, 0x6d, 0x5d, ++ 0x81, 0xe3, 0xdc, 0x60, 0xa5, 0x71, 0xcc, 0x98, 0xa7, 0x31, 0x15, 0x43, ++ 0xed, 0xbe, 0xad, 0xc8, 0x3f, 0x67, 0xd5, 0xf3, 0x38, 0x43, 0x16, 0xc8, ++ 0x5b, 0xa4, 0xdb, 0xac, 0x42, 0x4e, 0x87, 0xe6, 0x3a, 0x9e, 0xaf, 0xa1, ++ 0xe6, 0x63, 0xa8, 0xf9, 0x13, 0x2a, 0x1c, 0xaa, 0x04, 0x7c, 0xb3, 0xc6, ++ 0xaf, 0xc8, 0x47, 0xfd, 0xbf, 0x5b, 0x0a, 0xfc, 0x48, 0x3d, 0x4f, 0x1b, ++ 0x7f, 0x4e, 0x3a, 0x7a, 0x3e, 0x7a, 0x55, 0x01, 0x9d, 0x27, 0x89, 0x9e, ++ 0x8f, 0x2b, 0x64, 0xa2, 0xfe, 0xd2, 0xce, 0x49, 0x27, 0xc2, 0x53, 0xcd, ++ 0xdf, 0xa8, 0xb2, 0x07, 0xec, 0x99, 0x69, 0xc3, 0xcf, 0xcb, 0xaa, 0xf4, ++ 0x11, 0x87, 0x37, 0x9a, 0xd7, 0xb6, 0x03, 0x5c, 0x5f, 0xaf, 0xaa, 0x37, ++ 0xd0, 0xfc, 0xcf, 0xae, 0x9a, 0x47, 0x7e, 0xc2, 0xb3, 0xab, 0x74, 0x0c, ++ 0xf7, 0x4d, 0xd5, 0x80, 0x91, 0xd3, 0x5b, 0xc2, 0x78, 0xdb, 0xa2, 0xf7, ++ 0x60, 0x84, 0xcc, 0x74, 0xdf, 0x85, 0xc0, 0xfb, 0x37, 0xe9, 0xab, 0x80, ++ 0xcf, 0x62, 0xf4, 0xc3, 0x1e, 0x6a, 0xab, 0x99, 0x7a, 0x02, 0x60, 0x7b, ++ 0xb8, 0xcd, 0x4f, 0xcf, 0xb3, 0x66, 0xa9, 0x4f, 0xbe, 0x8c, 0xce, 0x2b, ++ 0x2e, 0x42, 0xce, 0xf4, 0x65, 0xe6, 0xb6, 0x5a, 0xbc, 0xa7, 0xe0, 0xac, ++ 0x6d, 0x28, 0x17, 0xef, 0x39, 0xf8, 0x32, 0xeb, 0xfe, 0x6f, 0x53, 0x39, ++ 0x6d, 0xe8, 0x28, 0x96, 0x93, 0xb3, 0x9e, 0xff, 0x36, 0xde, 0x7b, 0x70, ++ 0x76, 0xdc, 0xd0, 0x4e, 0xbc, 0xf7, 0xa0, 0x70, 0x5b, 0x25, 0xaf, 0x47, ++ 0x1a, 0xcc, 0x62, 0xec, 0xb2, 0xcc, 0x8a, 0x6f, 0x07, 0x69, 0xdd, 0xdc, ++ 0xaf, 0x34, 0x2b, 0x76, 0x3e, 0xbb, 0x1c, 0xe1, 0xd3, 0xc8, 0x22, 0xeb, ++ 0x07, 0xc9, 0x7f, 0xc3, 0xf3, 0xf3, 0x31, 0x9f, 0x0f, 0xf1, 0xe0, 0xb6, ++ 0x1a, 0x48, 0x9f, 0x71, 0x8b, 0x3c, 0x4a, 0x56, 0x2d, 0xf2, 0x2a, 0x31, ++ 0xc2, 0x02, 0xe5, 0x8e, 0xcc, 0x52, 0x8a, 0x47, 0x5b, 0x99, 0x67, 0xff, ++ 0x20, 0xd6, 0x67, 0xf3, 0x73, 0x40, 0x50, 0x4f, 0xf4, 0xdb, 0x31, 0x8e, ++ 0xfb, 0x7d, 0x4d, 0x02, 0xaf, 0x2c, 0x5b, 0xf5, 0x13, 0x45, 0x82, 0xc8, ++ 0x9f, 0x3a, 0xf2, 0x1d, 0xf4, 0x7d, 0x94, 0x8f, 0xee, 0x37, 0x86, 0xb8, ++ 0xbf, 0x8a, 0x8f, 0xff, 0xee, 0x8b, 0x93, 0x29, 0x7e, 0xa4, 0xe6, 0x87, ++ 0x32, 0x66, 0xcf, 0x59, 0x38, 0x99, 0xf2, 0x49, 0x34, 0x65, 0xf5, 0x7e, ++ 0x03, 0xa6, 0xd8, 0x73, 0x50, 0x5f, 0xe8, 0xd0, 0x0b, 0xbd, 0x54, 0x94, ++ 0x53, 0x53, 0x02, 0xf3, 0x33, 0xe3, 0xf4, 0xa2, 0x77, 0x67, 0xff, 0x5d, ++ 0x09, 0xee, 0x83, 0xd3, 0x2f, 0xdd, 0x5b, 0x88, 0x7c, 0xe9, 0x1a, 0x03, ++ 0xe8, 0xed, 0x23, 0xf0, 0xa1, 0x7f, 0xcd, 0xe2, 0x7c, 0xe8, 0xac, 0xde, ++ 0xda, 0x25, 0x81, 0x9e, 0xf6, 0x5e, 0x72, 0xe0, 0x16, 0xec, 0xe7, 0x7d, ++ 0xcb, 0xa2, 0x39, 0x0e, 0x58, 0x57, 0x5d, 0x6a, 0xa5, 0xc1, 0x81, 0xf3, ++ 0x0d, 0xfe, 0x48, 0x46, 0xbe, 0x98, 0x26, 0xf0, 0xed, 0x58, 0xc8, 0xe7, ++ 0xe7, 0xa8, 0xf6, 0x4b, 0xcb, 0xa1, 0xdf, 0x0e, 0x33, 0xec, 0x5f, 0xf8, ++ 0x3e, 0x2d, 0xa0, 0xf8, 0x28, 0x8f, 0x3e, 0xb0, 0x50, 0xba, 0x01, 0xe6, ++ 0xdd, 0x21, 0x71, 0x7e, 0x0b, 0x1f, 0xa5, 0x90, 0x5d, 0x52, 0xec, 0x49, ++ 0xc1, 0xfc, 0xe4, 0x06, 0x71, 0x1e, 0x52, 0x16, 0xfb, 0xfe, 0x8a, 0xbe, ++ 0x4d, 0x32, 0xea, 0xd3, 0xbf, 0x6a, 0xeb, 0x9f, 0xa1, 0x14, 0xc6, 0xe5, ++ 0x3b, 0x88, 0xf8, 0xf1, 0x7b, 0xf9, 0xec, 0xf6, 0xf9, 0x23, 0xf8, 0x2d, ++ 0x5b, 0x33, 0x39, 0xdf, 0x5e, 0x20, 0x7b, 0x26, 0x23, 0x1d, 0xad, 0x97, ++ 0xfa, 0xdf, 0xae, 0xcd, 0xc4, 0xf7, 0x9c, 0x1e, 0x67, 0x27, 0xb7, 0x96, ++ 0x63, 0x5e, 0xf1, 0x35, 0x96, 0x96, 0x72, 0x94, 0x3f, 0xc3, 0xde, 0xa7, ++ 0xc0, 0xfb, 0x92, 0xb8, 0xb2, 0x91, 0xb7, 0x6b, 0x30, 0x0d, 0xe5, 0xe2, ++ 0xf9, 0x64, 0x9f, 0x25, 0xb0, 0x2e, 0x13, 0xe3, 0x3e, 0x8b, 0x3f, 0xa6, ++ 0xb8, 0xe4, 0xf7, 0xb3, 0xde, 0x3d, 0x8a, 0x79, 0x05, 0xef, 0xea, 0x7b, ++ 0x66, 0x25, 0xa3, 0x7c, 0xc9, 0x17, 0xe7, 0xfa, 0x85, 0x5f, 0xf0, 0xcd, ++ 0xf1, 0xaa, 0x5f, 0xd0, 0xc4, 0xcb, 0x93, 0xb8, 0x5f, 0x30, 0x9a, 0xaf, ++ 0x35, 0x99, 0xe7, 0x8b, 0xd5, 0x2e, 0xe4, 0xe7, 0x10, 0x6b, 0x45, 0x3e, ++ 0xc2, 0x1c, 0x3b, 0x3f, 0xb7, 0x33, 0xa7, 0x3c, 0xdf, 0xdb, 0x01, 0x53, ++ 0xbc, 0x8e, 0x0d, 0x29, 0xc8, 0xf7, 0xe6, 0xbc, 0xef, 0x4f, 0x46, 0xbb, ++ 0x9d, 0x2d, 0x0c, 0x94, 0xfb, 0x27, 0x8f, 0xae, 0xcf, 0x30, 0xb7, 0xde, ++ 0x13, 0xbf, 0x5f, 0xe7, 0x7a, 0xe2, 0xca, 0xf0, 0xef, 0xda, 0x62, 0x6d, ++ 0xf9, 0xdb, 0x5e, 0x6d, 0xf9, 0xfa, 0xe9, 0x7f, 0x1e, 0x1f, 0x5f, 0xde, ++ 0x65, 0xf1, 0x6d, 0xc5, 0x75, 0xff, 0x54, 0xe2, 0xf9, 0x8d, 0xc1, 0x2b, ++ 0x98, 0x9d, 0xd6, 0xe9, 0x92, 0x82, 0xa8, 0x77, 0x4c, 0x7a, 0x39, 0x4b, ++ 0x9c, 0xdf, 0xe4, 0x79, 0x78, 0xff, 0x28, 0xec, 0xa2, 0x97, 0xa7, 0x33, ++ 0xaa, 0x4f, 0xdf, 0x6b, 0xda, 0x8d, 0xf9, 0xed, 0xaa, 0x1f, 0x59, 0x16, ++ 0xf5, 0x93, 0xdc, 0xcc, 0x94, 0xe7, 0xe4, 0xf7, 0x05, 0xa0, 0xbc, 0x1a, ++ 0x92, 0x44, 0x3e, 0x9f, 0x8b, 0x62, 0x25, 0xec, 0xa5, 0x3b, 0xec, 0x1c, ++ 0x7e, 0xd0, 0xd6, 0x00, 0xfd, 0xbc, 0xb4, 0xd8, 0x43, 0xfb, 0x23, 0xdd, ++ 0xaa, 0x63, 0x57, 0xe1, 0x1e, 0x2a, 0x37, 0x91, 0x1e, 0x52, 0x31, 0xc6, ++ 0x94, 0x84, 0x74, 0x73, 0x48, 0xd0, 0x9d, 0x7a, 0x1e, 0x57, 0xa5, 0xc3, ++ 0x0a, 0x85, 0xf9, 0x31, 0x3f, 0x01, 0x86, 0x5e, 0x88, 0xcf, 0x77, 0xf5, ++ 0xf6, 0x83, 0xe8, 0x3f, 0x0e, 0x7e, 0xca, 0x18, 0xc7, 0x57, 0xa5, 0x42, ++ 0xf9, 0x85, 0x62, 0x2c, 0xc6, 0xda, 0xa9, 0xfc, 0x98, 0xa0, 0xef, 0x43, ++ 0x62, 0x4e, 0xc1, 0x1f, 0x28, 0xb4, 0x9f, 0xdf, 0xb0, 0x19, 0x08, 0x9f, ++ 0xf2, 0xcf, 0xe5, 0x5d, 0x28, 0x27, 0x30, 0xf6, 0x82, 0x7e, 0xe1, 0x73, ++ 0x1b, 0x27, 0xd2, 0xfc, 0xd4, 0xfd, 0x03, 0xbb, 0xba, 0xd0, 0x95, 0x4e, ++ 0x2e, 0x6b, 0xd1, 0xaf, 0xa2, 0xc3, 0x49, 0x14, 0x0b, 0x7d, 0x42, 0xa5, ++ 0x6f, 0xd4, 0x80, 0xb0, 0xdd, 0x18, 0xfc, 0xcf, 0x7c, 0xa2, 0x73, 0xe2, ++ 0x37, 0x43, 0xd3, 0xf8, 0xfd, 0x09, 0xef, 0xe5, 0x73, 0x7e, 0x32, 0xb4, ++ 0xc9, 0x29, 0xce, 0x7b, 0xf1, 0x78, 0x58, 0x8e, 0x29, 0xda, 0xaf, 0x0f, ++ 0xfb, 0xcd, 0x8c, 0x8e, 0xc3, 0xcf, 0x13, 0xa5, 0x8b, 0x32, 0x54, 0x85, ++ 0x75, 0xb0, 0xee, 0x4f, 0x32, 0xf3, 0x69, 0xd3, 0x4a, 0x03, 0x3f, 0xfb, ++ 0x03, 0xc9, 0x65, 0xab, 0x37, 0x80, 0xe3, 0x18, 0x92, 0x4d, 0x74, 0x0e, ++ 0x46, 0xdd, 0x37, 0xf6, 0xce, 0xdf, 0xbe, 0x5d, 0x7b, 0x05, 0xae, 0xb3, ++ 0xe8, 0x7b, 0xb4, 0xce, 0x79, 0x36, 0x3b, 0xae, 0xb3, 0x18, 0xc8, 0xba, ++ 0xce, 0x49, 0x4f, 0x5f, 0x2a, 0xf5, 0xc7, 0xf7, 0x8f, 0x9c, 0xe4, 0xf5, ++ 0xe0, 0x3e, 0xf9, 0x4e, 0xcd, 0x2b, 0x33, 0x94, 0x38, 0xba, 0x81, 0xef, ++ 0x1b, 0xf9, 0xf7, 0x16, 0xed, 0xf7, 0x6e, 0xf8, 0xde, 0x19, 0xf7, 0x7d, ++ 0x32, 0x7c, 0x5f, 0x32, 0xfc, 0xfb, 0xa7, 0x6c, 0xa6, 0xb0, 0x6e, 0x0a, ++ 0xf6, 0x53, 0xe1, 0x89, 0x10, 0x3f, 0x0f, 0xd3, 0x62, 0xe6, 0x89, 0x75, ++ 0xc9, 0xe9, 0xfc, 0xbb, 0x79, 0x22, 0xdf, 0xb3, 0x30, 0x19, 0xda, 0xa3, ++ 0xbc, 0x29, 0xd6, 0xe6, 0x63, 0xb0, 0xe9, 0x5e, 0x13, 0xbf, 0xaf, 0x43, ++ 0x9b, 0x7f, 0x71, 0x8d, 0xb4, 0x2e, 0x13, 0xf7, 0xd5, 0x5c, 0x53, 0xe3, ++ 0x40, 0x04, 0xfa, 0xfb, 0x99, 0xc0, 0xdb, 0x35, 0xba, 0xc0, 0x57, 0x78, ++ 0x3f, 0xdd, 0xcf, 0x16, 0x15, 0x1d, 0xc6, 0xfd, 0x56, 0x63, 0x0a, 0x29, ++ 0x68, 0x0f, 0x5d, 0xcb, 0xc2, 0xeb, 0x11, 0x99, 0x67, 0x2b, 0x03, 0x4f, ++ 0x38, 0xc6, 0x12, 0x3f, 0xf8, 0x0b, 0xee, 0x8b, 0x26, 0x39, 0x30, 0xde, ++ 0x09, 0xe5, 0xd3, 0xfa, 0x9e, 0xc2, 0x3b, 0xf2, 0x69, 0xbf, 0x5c, 0xcc, ++ 0x9c, 0x36, 0x7c, 0xbe, 0x2a, 0x5d, 0xa8, 0xf3, 0x45, 0xfa, 0x40, 0x3a, ++ 0x8b, 0xd2, 0x47, 0xc2, 0xbc, 0xa3, 0x78, 0xba, 0xae, 0x8f, 0x12, 0xd5, ++ 0x76, 0x80, 0xde, 0x83, 0x4f, 0x55, 0x0f, 0x02, 0x4b, 0x9a, 0xe7, 0x13, ++ 0x7b, 0x72, 0x62, 0xeb, 0x02, 0x22, 0x9a, 0x63, 0x6a, 0x29, 0x44, 0x3d, ++ 0xe4, 0x67, 0xed, 0x41, 0xe2, 0x1b, 0xd7, 0x38, 0x1e, 0xa1, 0xbc, 0xa5, ++ 0x33, 0x63, 0x02, 0xae, 0x2c, 0xc0, 0x7f, 0xdd, 0x65, 0x5f, 0xd0, 0xbd, ++ 0x26, 0xcc, 0xbd, 0x78, 0x3c, 0xea, 0xf7, 0x30, 0xdf, 0xb4, 0xac, 0xb4, ++ 0xff, 0xbd, 0xf9, 0xaa, 0xfa, 0xde, 0xb0, 0x7c, 0xda, 0x4f, 0x0d, 0x9a, ++ 0x7c, 0xda, 0xd1, 0xf6, 0x95, 0x3a, 0x6e, 0x33, 0xe3, 0xf7, 0xd3, 0xcc, ++ 0x1a, 0xd8, 0x45, 0xf9, 0xb1, 0xcd, 0x0b, 0xad, 0x5e, 0x3c, 0xe7, 0xd0, ++ 0x8c, 0xf9, 0x9d, 0xe5, 0x14, 0x3f, 0x22, 0x3d, 0x0e, 0xcf, 0x01, 0xd3, ++ 0x3d, 0x27, 0x92, 0x49, 0xe8, 0x5d, 0x97, 0x9a, 0x77, 0xcb, 0xf7, 0x61, ++ 0x6f, 0xa3, 0x87, 0xf4, 0xb7, 0x28, 0x1f, 0x17, 0x79, 0xe3, 0xbd, 0xa5, ++ 0x7c, 0xde, 0xbd, 0x77, 0x78, 0xd4, 0x7b, 0x4e, 0xb8, 0x7e, 0xb7, 0x98, ++ 0xf1, 0x7b, 0x52, 0xd4, 0x7b, 0x4e, 0x96, 0xdb, 0xa9, 0x5e, 0xcd, 0x2f, ++ 0xef, 0xdd, 0xc5, 0xfd, 0x78, 0xbd, 0x2f, 0x8e, 0xa7, 0xf3, 0x50, 0xa0, ++ 0xbf, 0x91, 0xbe, 0xc0, 0x52, 0x74, 0x7c, 0x7e, 0xf9, 0xda, 0xfb, 0x55, ++ 0xf0, 0x4f, 0x4a, 0x8f, 0xe5, 0x43, 0x6f, 0xd6, 0x73, 0x7d, 0x73, 0x9b, ++ 0xce, 0x5b, 0x81, 0x70, 0xde, 0x86, 0x71, 0x9e, 0xaf, 0x89, 0xef, 0xde, ++ 0x94, 0xa5, 0xf5, 0x9b, 0xa8, 0xe5, 0x44, 0xbf, 0xde, 0x33, 0xce, 0xc0, ++ 0x2d, 0x59, 0xe8, 0x0f, 0x28, 0xf1, 0xe5, 0x4a, 0x40, 0x3f, 0x4b, 0x0d, ++ 0xdc, 0x6f, 0x07, 0xf4, 0xb5, 0x1d, 0xcf, 0x4e, 0xd4, 0xb0, 0x96, 0xa7, ++ 0xf0, 0xfe, 0xc0, 0xb9, 0xac, 0xe5, 0xd7, 0xba, 0xb1, 0x44, 0x5f, 0x01, ++ 0xa2, 0xaf, 0x49, 0x5f, 0xf0, 0x7b, 0x05, 0x63, 0xf4, 0xb5, 0x98, 0xd3, ++ 0x57, 0x90, 0x98, 0x92, 0x4a, 0x5f, 0x51, 0xba, 0x2a, 0x4e, 0xcc, 0x9f, ++ 0x0a, 0xac, 0xc6, 0xf6, 0xbd, 0x8e, 0xbe, 0x8f, 0x9a, 0x50, 0x4f, 0x1d, ++ 0x30, 0x12, 0x5e, 0xd4, 0x3c, 0xb8, 0xc4, 0x7d, 0x1c, 0x37, 0x9f, 0x13, ++ 0x7a, 0x3e, 0x1f, 0x97, 0x2c, 0xd3, 0x7c, 0xd6, 0x8e, 0x34, 0x9f, 0x4b, ++ 0xa1, 0xf3, 0x78, 0xfa, 0xca, 0x60, 0x9c, 0x9e, 0x47, 0xa3, 0xf7, 0x0c, ++ 0x85, 0x05, 0x6d, 0x65, 0x31, 0x7a, 0xdf, 0x65, 0x09, 0xb4, 0xe3, 0xb8, ++ 0x51, 0xba, 0x5f, 0xcf, 0xed, 0x91, 0x61, 0xf3, 0x96, 0xad, 0x44, 0x1f, ++ 0x37, 0xde, 0x2c, 0xf3, 0xfc, 0x70, 0x0b, 0x97, 0x57, 0x18, 0x8f, 0xc8, ++ 0x84, 0xf1, 0xe7, 0x8b, 0xf1, 0x6f, 0xec, 0xe6, 0x74, 0x74, 0xa3, 0xcd, ++ 0x40, 0x74, 0x37, 0x7f, 0xa0, 0x91, 0xf2, 0x85, 0x58, 0x35, 0x8f, 0x2b, ++ 0x78, 0xe1, 0x7f, 0xdc, 0x0e, 0xf4, 0x11, 0x7c, 0xeb, 0xc4, 0x77, 0x0b, ++ 0x5d, 0xa5, 0x7a, 0x24, 0xd9, 0x85, 0xb5, 0xda, 0xf8, 0x43, 0x9d, 0x55, ++ 0x8d, 0x6f, 0xf8, 0xf5, 0xb8, 0x1f, 0x6f, 0x5c, 0xa8, 0x3f, 0x16, 0x2f, ++ 0xef, 0xeb, 0xd8, 0xc6, 0x2f, 0x30, 0xaf, 0xad, 0x0e, 0xe3, 0x14, 0xea, ++ 0x77, 0x30, 0xee, 0xe3, 0x59, 0xd1, 0xf3, 0x7f, 0xe3, 0x31, 0x4e, 0x71, ++ 0x58, 0xd8, 0xe9, 0x67, 0x81, 0xbe, 0x91, 0xfe, 0xdf, 0x48, 0x5b, 0xb9, ++ 0xfd, 0x0e, 0xa0, 0xdb, 0xf1, 0x8f, 0x97, 0x94, 0xa1, 0x3f, 0x67, 0x76, ++ 0xfa, 0xaa, 0xa7, 0x36, 0x41, 0xf9, 0x99, 0x6d, 0x13, 0xa9, 0xfc, 0x46, ++ 0xfa, 0xad, 0x77, 0xbd, 0x8b, 0xf5, 0x3b, 0x8b, 0xa8, 0x5c, 0x8d, 0x97, ++ 0xb8, 0xa0, 0xbd, 0xd1, 0xc8, 0xbf, 0x2f, 0xae, 0xb8, 0x79, 0x5e, 0x3e, ++ 0x8c, 0x7b, 0xd8, 0x2c, 0xfa, 0xc5, 0x7d, 0x85, 0x76, 0x5f, 0x52, 0xa0, ++ 0x77, 0x3e, 0xb4, 0x73, 0x4f, 0x29, 0x28, 0xc3, 0x7c, 0xc3, 0x6a, 0xc1, ++ 0x1f, 0xce, 0xde, 0xc1, 0xf3, 0xdd, 0xaf, 0xbd, 0xcc, 0xc6, 0x53, 0x38, ++ 0x57, 0x7a, 0xc8, 0x6f, 0x54, 0x9d, 0x24, 0xea, 0xbf, 0xcb, 0xfb, 0x7d, ++ 0xbb, 0xf4, 0x5f, 0xca, 0x30, 0xef, 0xb4, 0xba, 0x80, 0xdf, 0xe3, 0xf2, ++ 0x76, 0xd9, 0x4f, 0x27, 0x62, 0xf9, 0xb0, 0xf4, 0xc5, 0xa2, 0x91, 0xe2, ++ 0xdf, 0x93, 0x8a, 0xa5, 0xf0, 0x04, 0x80, 0x4f, 0xb5, 0x93, 0xb7, 0xaf, ++ 0x2d, 0xfb, 0x51, 0x16, 0xda, 0xf1, 0xd5, 0x55, 0xbc, 0x3c, 0xc9, 0x5b, ++ 0xd9, 0x3d, 0x16, 0xeb, 0x75, 0xe7, 0x16, 0x8d, 0x74, 0xee, 0xf3, 0x17, ++ 0x62, 0x3f, 0x45, 0xcf, 0x35, 0x89, 0x7d, 0xfa, 0xb2, 0xef, 0x63, 0x3a, ++ 0xc7, 0xe4, 0x37, 0x49, 0x5e, 0x5c, 0xa2, 0x7f, 0xfa, 0xc7, 0xfc, 0x5e, ++ 0x22, 0xab, 0x64, 0x47, 0xff, 0xa3, 0xdf, 0x97, 0xaf, 0xa0, 0x9f, 0x74, ++ 0x96, 0x8f, 0xe7, 0x25, 0x56, 0x99, 0xda, 0x33, 0xd1, 0xfe, 0xbd, 0x2e, ++ 0x60, 0x28, 0xc7, 0xfc, 0x52, 0xbb, 0xa9, 0xf4, 0x30, 0xea, 0x19, 0x29, ++ 0xd3, 0x2b, 0xa7, 0x21, 0x7e, 0x67, 0x99, 0x98, 0x1e, 0xe5, 0x12, 0xd0, ++ 0xf9, 0xff, 0x21, 0x3a, 0xbf, 0xfc, 0x8b, 0xdc, 0x64, 0x24, 0x2e, 0xab, ++ 0x96, 0xce, 0x55, 0x3a, 0x9a, 0xaf, 0xd2, 0x77, 0xb5, 0x96, 0x8e, 0x61, ++ 0x7f, 0xfe, 0x73, 0x56, 0xda, 0x37, 0xf3, 0xd7, 0xd1, 0xe8, 0x18, 0xc6, ++ 0xff, 0x77, 0xe4, 0x13, 0x75, 0xdf, 0xd2, 0xca, 0x95, 0x68, 0x7f, 0x09, ++ 0xfb, 0x2d, 0xb1, 0xff, 0xd1, 0xf8, 0x00, 0xfe, 0xc5, 0xf3, 0xb9, 0xd8, ++ 0x3c, 0xfa, 0x68, 0x5f, 0x65, 0x63, 0xd6, 0xd7, 0x58, 0xdc, 0x77, 0x3d, ++ 0xea, 0xbe, 0x1b, 0xc2, 0x75, 0x18, 0x74, 0x83, 0x74, 0xae, 0x23, 0x4f, ++ 0xf2, 0x4e, 0xa4, 0x03, 0x8d, 0xa3, 0xc8, 0x7f, 0x75, 0x7e, 0x39, 0xc0, ++ 0xdb, 0x58, 0xd9, 0xf0, 0x79, 0xe1, 0x9f, 0xa2, 0xea, 0x65, 0xfc, 0xcf, ++ 0x85, 0x76, 0x6e, 0xb6, 0xa8, 0x87, 0xef, 0x7c, 0xcc, 0x19, 0x9b, 0x17, ++ 0x8c, 0xcf, 0xc6, 0xa0, 0xdc, 0x5f, 0xcf, 0xe7, 0xb3, 0x43, 0x6a, 0xe1, ++ 0x7c, 0x43, 0xe8, 0xc5, 0xaa, 0x7d, 0xdc, 0xa4, 0xae, 0xb7, 0x5f, 0xbb, ++ 0xde, 0x8a, 0x24, 0x7e, 0x9e, 0xd9, 0x8d, 0xfe, 0x0b, 0xfc, 0xce, 0x55, ++ 0x3a, 0xf1, 0xeb, 0xe6, 0xdd, 0x2c, 0xe4, 0xe6, 0x42, 0x93, 0xff, 0x41, ++ 0x23, 0xac, 0xe1, 0x06, 0xc7, 0x52, 0xa2, 0x87, 0x9b, 0x58, 0xf0, 0x45, ++ 0xd4, 0x4f, 0x8c, 0x29, 0x01, 0xe7, 0x98, 0x34, 0xb4, 0xbb, 0x82, 0x07, ++ 0x22, 0xf9, 0xe4, 0xcf, 0xa5, 0xbc, 0x00, 0xc0, 0x77, 0xea, 0x98, 0x38, ++ 0xfd, 0x44, 0x9d, 0x57, 0x22, 0x3c, 0x9a, 0x46, 0xe1, 0x87, 0x89, 0xf3, ++ 0x4e, 0x84, 0x43, 0x0c, 0x3f, 0x83, 0xa4, 0x5f, 0xa9, 0xe7, 0xa3, 0xa2, ++ 0xeb, 0x4a, 0x58, 0x8f, 0x2a, 0xff, 0x5d, 0x06, 0xad, 0x1f, 0xc8, 0x29, ++ 0xfc, 0x36, 0x4e, 0xe1, 0xa7, 0x41, 0x0a, 0x41, 0x39, 0x58, 0xcb, 0x92, ++ 0x28, 0x6f, 0x61, 0x96, 0x57, 0x22, 0x39, 0x5e, 0xcb, 0x4c, 0xc4, 0x3f, ++ 0x6b, 0x6b, 0xb8, 0xdc, 0x74, 0x5a, 0xb9, 0x9c, 0x57, 0xe5, 0xeb, 0x68, ++ 0x74, 0x7d, 0xf5, 0x55, 0x9c, 0xcf, 0xd4, 0x36, 0x30, 0x71, 0xee, 0x8a, ++ 0xcf, 0x3f, 0x91, 0xae, 0x32, 0x58, 0xe4, 0x7b, 0xf8, 0xac, 0x35, 0x79, ++ 0xb6, 0x2e, 0xc3, 0xfd, 0x8a, 0xfa, 0x80, 0x27, 0xb6, 0xdf, 0x6b, 0xad, ++ 0xdc, 0xaf, 0x3b, 0x77, 0x8c, 0xf0, 0x1b, 0xb2, 0xc8, 0x34, 0xb4, 0x6f, ++ 0xa3, 0xe5, 0x61, 0x7e, 0xc4, 0xc8, 0x34, 0xe4, 0x1b, 0x89, 0xf7, 0x45, ++ 0xd5, 0x5e, 0xe0, 0x7e, 0x44, 0xa7, 0xb8, 0x97, 0xb5, 0xd6, 0xfb, 0xf1, ++ 0x34, 0xb4, 0xd7, 0x9d, 0x35, 0x91, 0x69, 0xc8, 0x7f, 0x1e, 0x74, 0xf8, ++ 0xe6, 0x21, 0xde, 0xd4, 0xfb, 0xdc, 0x12, 0xf9, 0xce, 0x8d, 0x63, 0x74, ++ 0xaa, 0x1f, 0xf1, 0x92, 0xe8, 0x2d, 0x11, 0x0f, 0x6a, 0xdc, 0x28, 0x35, ++ 0xc5, 0x5f, 0x87, 0xe3, 0x9c, 0x96, 0x06, 0x2b, 0xb0, 0xf2, 0x91, 0x34, ++ 0xe1, 0xd7, 0x67, 0x81, 0x7c, 0xa4, 0x47, 0x87, 0x3d, 0xbf, 0x12, 0xfd, ++ 0x01, 0xc0, 0xdf, 0x2e, 0x5e, 0x44, 0xa3, 0x0a, 0xab, 0x00, 0x5e, 0xd3, ++ 0x9d, 0x81, 0x00, 0xd2, 0xdb, 0x4d, 0xcc, 0x3f, 0x1b, 0xcf, 0xe2, 0x39, ++ 0x6b, 0x02, 0x7a, 0xee, 0xe7, 0x66, 0xb4, 0xfe, 0xb5, 0x62, 0xfd, 0xb3, ++ 0x85, 0xdc, 0x3b, 0xb7, 0x5d, 0x26, 0x3f, 0x7d, 0xb5, 0xaf, 0xf8, 0x31, ++ 0x74, 0xa5, 0x37, 0x1f, 0xd1, 0xb3, 0x10, 0xed, 0x3b, 0x1f, 0xc9, 0xb1, ++ 0x35, 0x62, 0xfe, 0xe7, 0x18, 0xc7, 0xd3, 0x39, 0x2b, 0x97, 0x7f, 0x2b, ++ 0xdf, 0xfa, 0xa7, 0x0a, 0xa0, 0x5c, 0x36, 0x7e, 0x8b, 0x2e, 0x76, 0x8f, ++ 0x01, 0xfc, 0x9b, 0x10, 0x4a, 0xd2, 0xdc, 0x63, 0x30, 0x69, 0xaf, 0x53, ++ 0x53, 0x9e, 0xdc, 0x97, 0xa5, 0x69, 0x7f, 0x59, 0x7f, 0x81, 0xa6, 0xbe, ++ 0x34, 0x3c, 0x51, 0x53, 0x3f, 0xf5, 0x48, 0x99, 0xa6, 0x3c, 0x6d, 0x70, ++ 0x86, 0xa6, 0xfd, 0xe5, 0xef, 0x57, 0x69, 0xca, 0x57, 0x44, 0xe6, 0x69, ++ 0xda, 0x7f, 0xeb, 0xd4, 0x02, 0x4d, 0xf9, 0xca, 0xa1, 0x5b, 0x34, 0xed, ++ 0x8f, 0x0b, 0xfb, 0x94, 0x05, 0x7d, 0x83, 0xc5, 0xe9, 0x78, 0xcf, 0xb7, ++ 0xa0, 0xcb, 0x0b, 0x4b, 0x34, 0xdf, 0xfd, 0x36, 0x79, 0xce, 0x11, 0xa4, ++ 0xcb, 0x65, 0x1b, 0x79, 0x9e, 0x70, 0x25, 0x40, 0x46, 0x73, 0x9f, 0x43, ++ 0x0f, 0x97, 0xef, 0x2d, 0xf0, 0x3f, 0x8e, 0x57, 0xbf, 0x82, 0xf0, 0x5a, ++ 0x01, 0x7a, 0x2f, 0xe6, 0x07, 0xaf, 0xdc, 0xa2, 0x95, 0xff, 0xf5, 0x03, ++ 0x9b, 0xd6, 0x23, 0x4f, 0x4b, 0xcc, 0x5f, 0x58, 0xcd, 0x5a, 0xaa, 0xf0, ++ 0x6a, 0xb8, 0xc4, 0xfc, 0x85, 0x6a, 0xfb, 0x62, 0x1d, 0xd2, 0xe1, 0xe3, ++ 0x63, 0x44, 0x9e, 0xc2, 0xe5, 0xec, 0x72, 0x71, 0xff, 0xca, 0xd7, 0xe2, ++ 0xb5, 0x88, 0x15, 0xfe, 0x97, 0xf0, 0x6a, 0x74, 0x6b, 0xf1, 0x6a, 0xf6, ++ 0x68, 0xf1, 0x6a, 0x29, 0xd6, 0xe2, 0xd5, 0xe6, 0xd5, 0xe2, 0x35, 0x65, ++ 0xba, 0x16, 0xaf, 0x0e, 0x9f, 0x16, 0xaf, 0xa9, 0x35, 0x5a, 0xbc, 0xa6, ++ 0xf9, 0xb5, 0x78, 0xcd, 0xa8, 0xd3, 0xe2, 0x35, 0x33, 0xa0, 0xc5, 0xeb, ++ 0x98, 0x7a, 0x2d, 0x5e, 0x73, 0x5a, 0xb4, 0x78, 0xcd, 0x6b, 0xd5, 0xe2, ++ 0x2f, 0x3f, 0xb8, 0x5a, 0x8b, 0xaf, 0x04, 0x7c, 0xab, 0xfc, 0x6f, 0x6c, ++ 0xd7, 0x5a, 0x4d, 0xbb, 0x28, 0xde, 0xfd, 0xf5, 0x94, 0x77, 0x32, 0xae, ++ 0xe7, 0x1e, 0x4d, 0xbf, 0x2a, 0xde, 0x83, 0xf0, 0x3f, 0x8e, 0xf7, 0x16, ++ 0xca, 0x0b, 0xff, 0x6b, 0xf1, 0x0e, 0xdc, 0x86, 0xfc, 0xa0, 0x89, 0x78, ++ 0xff, 0x20, 0x01, 0xdf, 0x20, 0x37, 0x3e, 0x44, 0xbe, 0x00, 0xf2, 0xfe, ++ 0xdf, 0xf0, 0x59, 0x37, 0x5e, 0xe8, 0xd5, 0xfe, 0x91, 0xe5, 0xbd, 0xca, ++ 0x7f, 0xe2, 0xe5, 0x6b, 0xbc, 0xfd, 0x38, 0x1a, 0x5f, 0x1a, 0x26, 0x4f, ++ 0x84, 0x3d, 0x39, 0xaa, 0x3c, 0x49, 0xb0, 0x27, 0x3f, 0xc0, 0xec, 0x18, ++ 0xd2, 0x53, 0x36, 0x92, 0xbf, 0xe5, 0x66, 0x41, 0x9f, 0x5f, 0xe2, 0xab, ++ 0x2b, 0xd0, 0x9f, 0xf9, 0x63, 0x92, 0x93, 0x1f, 0xc0, 0x44, 0xa6, 0xc3, ++ 0xbc, 0x3e, 0xc0, 0x79, 0xc3, 0x38, 0x1f, 0x24, 0x4d, 0x22, 0x7b, 0xff, ++ 0x56, 0x16, 0xd6, 0xd3, 0xfd, 0xbb, 0x98, 0xf1, 0x07, 0x9d, 0xde, 0x8e, ++ 0x09, 0xc0, 0x32, 0xde, 0x9b, 0xe3, 0xa1, 0xe7, 0x52, 0x21, 0x47, 0x97, ++ 0x0b, 0x7f, 0x80, 0xcf, 0x12, 0xb8, 0x38, 0x86, 0xfb, 0x01, 0xf2, 0xd2, ++ 0x71, 0xdc, 0xec, 0x41, 0x7e, 0x0f, 0xf2, 0xdb, 0xa9, 0x97, 0x74, 0x1f, ++ 0xc0, 0x31, 0xf4, 0x87, 0x2b, 0x8c, 0x9d, 0x40, 0x7f, 0x38, 0x3c, 0xcf, ++ 0x98, 0x39, 0x3d, 0x9c, 0x54, 0xf9, 0x83, 0x8f, 0x79, 0x5c, 0x71, 0x70, ++ 0x5b, 0x32, 0x4b, 0x2a, 0x26, 0xbd, 0x51, 0x4e, 0xa2, 0xbc, 0x9c, 0x25, ++ 0x37, 0x49, 0x24, 0x47, 0x96, 0xfc, 0x9e, 0x3f, 0xd3, 0xb3, 0xb9, 0xfe, ++ 0x99, 0xf8, 0xec, 0x68, 0x55, 0xe1, 0xc6, 0xed, 0x92, 0x99, 0xd9, 0x1e, ++ 0xe2, 0xeb, 0xd9, 0xac, 0x4f, 0xc8, 0x3b, 0x16, 0xb0, 0x8e, 0xa5, 0x7e, ++ 0xb8, 0xff, 0xfa, 0x49, 0x7e, 0x0f, 0xe8, 0xf3, 0x12, 0x53, 0xa6, 0x3b, ++ 0xe9, 0x38, 0x12, 0xe1, 0x31, 0xc3, 0xc4, 0xe7, 0xf5, 0xbc, 0x9e, 0x99, ++ 0x10, 0x7e, 0xcf, 0xb2, 0x80, 0x07, 0xe1, 0xf2, 0x43, 0x05, 0x58, 0x13, ++ 0xcf, 0x87, 0x9f, 0x88, 0xf4, 0xb0, 0xe4, 0xf7, 0xef, 0x16, 0xa0, 0x3f, ++ 0x49, 0xee, 0xb0, 0x5f, 0x87, 0xf7, 0x3c, 0x4f, 0xc0, 0xf1, 0x60, 0x1e, ++ 0xb3, 0x6f, 0x6b, 0x91, 0xd0, 0xbf, 0x9a, 0xe1, 0x6e, 0x91, 0xd0, 0x7f, ++ 0x33, 0xec, 0xfd, 0xfe, 0x7b, 0x24, 0x3c, 0xc7, 0x17, 0x2d, 0x33, 0xde, ++ 0x0e, 0xff, 0x10, 0x0e, 0xaa, 0x9f, 0xac, 0x58, 0xc7, 0xe3, 0xc5, 0x43, ++ 0x77, 0x70, 0x3d, 0xff, 0xa9, 0xef, 0x32, 0xf2, 0xff, 0x74, 0xb4, 0x06, ++ 0x2b, 0x83, 0x18, 0x27, 0x92, 0xc1, 0x20, 0xc3, 0x7c, 0x12, 0x3d, 0x3f, ++ 0xf7, 0x3b, 0x33, 0x9b, 0xfb, 0xbf, 0x32, 0xd9, 0x20, 0xdd, 0x2f, 0xca, ++ 0xde, 0x14, 0xfa, 0x99, 0xb8, 0x97, 0xbd, 0x44, 0xe4, 0x97, 0x9f, 0x11, ++ 0xf1, 0x96, 0x15, 0xbb, 0x4c, 0x0c, 0xf3, 0x15, 0x4a, 0xf6, 0x1d, 0x74, ++ 0x62, 0x7c, 0x65, 0x05, 0xe0, 0x72, 0x10, 0xe5, 0x99, 0x12, 0xa0, 0x7b, ++ 0x2c, 0x4a, 0xb6, 0xbe, 0xe1, 0xe4, 0xf7, 0x7d, 0xeb, 0x1d, 0x78, 0x5e, ++ 0x4c, 0x95, 0xa3, 0xa3, 0xe3, 0x5b, 0x61, 0x27, 0xe3, 0xf2, 0xb4, 0x01, ++ 0x8f, 0x23, 0xde, 0x17, 0x79, 0x5b, 0x0e, 0x97, 0xe3, 0x1d, 0x6d, 0x35, ++ 0x33, 0x31, 0x3e, 0xa2, 0xce, 0xe7, 0xfe, 0x36, 0xdf, 0x4c, 0xa4, 0x0f, ++ 0x59, 0xf1, 0x52, 0x9e, 0x17, 0xde, 0x6f, 0xe3, 0x88, 0xfb, 0xde, 0xe0, ++ 0x82, 0xfa, 0xb8, 0xfd, 0xab, 0x58, 0x6b, 0x34, 0x65, 0xbd, 0xd5, 0x4f, ++ 0x97, 0x46, 0xac, 0x6f, 0x6b, 0x21, 0x3a, 0xd3, 0x8b, 0x7b, 0x78, 0x1e, ++ 0xc8, 0x5e, 0x6b, 0x8f, 0xbf, 0xbf, 0xff, 0xd6, 0x6c, 0xa1, 0x47, 0x98, ++ 0x82, 0xcc, 0x9e, 0xce, 0x84, 0x0a, 0x8b, 0x4f, 0xe5, 0x24, 0xf2, 0x87, ++ 0x3f, 0x32, 0x6e, 0x0f, 0x1a, 0xdd, 0xd0, 0x4f, 0x3c, 0x5f, 0xbb, 0x2b, ++ 0x97, 0xc5, 0xfb, 0x77, 0xbb, 0xda, 0xfc, 0x34, 0xdf, 0xf5, 0x52, 0x20, ++ 0x80, 0x9d, 0x18, 0x0b, 0x59, 0xd8, 0x9c, 0x8c, 0xf9, 0x03, 0x78, 0xc6, ++ 0x11, 0xde, 0x6f, 0xbd, 0xe6, 0x08, 0xe6, 0xb3, 0x18, 0x6c, 0x6b, 0xbd, ++ 0x61, 0xcf, 0xe8, 0x70, 0x33, 0xba, 0x95, 0xf3, 0xf1, 0x7c, 0xa9, 0x21, ++ 0x5b, 0xcb, 0x97, 0xfe, 0xa1, 0xed, 0x14, 0xc1, 0xa9, 0xa3, 0xad, 0x8e, ++ 0xc6, 0x3b, 0x83, 0xba, 0x1c, 0xfa, 0x77, 0x32, 0xb9, 0x7f, 0xa7, 0xa3, ++ 0x6d, 0x31, 0xbd, 0xd7, 0xd5, 0x78, 0x88, 0x9e, 0x5e, 0xdf, 0x3a, 0xfe, ++ 0xa0, 0x07, 0xea, 0x8f, 0xc2, 0x3f, 0xbc, 0x8f, 0xc6, 0xe8, 0xe2, 0xf3, ++ 0x62, 0xe5, 0xb9, 0x24, 0x9f, 0x16, 0x09, 0x3a, 0x40, 0xdf, 0x51, 0x0e, ++ 0xd0, 0xcf, 0xd1, 0x56, 0x3d, 0xd1, 0xd9, 0x9d, 0x39, 0xd6, 0x10, 0x6e, ++ 0xc2, 0x3b, 0xdf, 0x19, 0x77, 0x10, 0xef, 0xd3, 0x34, 0x00, 0x8c, 0xe4, ++ 0xbf, 0x62, 0xde, 0xd1, 0x71, 0x04, 0x9c, 0x0c, 0x82, 0x2f, 0x01, 0x3d, ++ 0xf9, 0x71, 0xbf, 0x19, 0xb2, 0x14, 0xf2, 0xc3, 0x3a, 0xed, 0x0b, 0x08, ++ 0x4f, 0xff, 0xd5, 0xfe, 0x54, 0xf8, 0x1a, 0xcc, 0x8c, 0xee, 0x7b, 0x31, ++ 0xe4, 0x58, 0xc9, 0x7f, 0x72, 0xa9, 0xf3, 0xdc, 0x92, 0x2d, 0xec, 0x7c, ++ 0x55, 0xce, 0x97, 0xe7, 0x12, 0x1f, 0xbd, 0x53, 0xc0, 0xe5, 0xf5, 0xad, ++ 0x3c, 0xff, 0xe7, 0xe8, 0x5d, 0x8c, 0xf4, 0xee, 0x3b, 0xef, 0xe6, 0x7e, ++ 0xb0, 0x3b, 0xc1, 0x8e, 0xc7, 0x7d, 0xc9, 0x5a, 0xe1, 0xaf, 0x22, 0x46, ++ 0x37, 0x2a, 0xbf, 0x4e, 0xc3, 0x1b, 0x37, 0xe0, 0x65, 0x4f, 0x1b, 0x30, ++ 0x9a, 0x22, 0xc6, 0x1e, 0x6a, 0x33, 0xe1, 0x09, 0x27, 0x66, 0x41, 0x7f, ++ 0xd5, 0xd8, 0x18, 0x1e, 0x7b, 0x7c, 0x8a, 0x03, 0xdd, 0xe2, 0x9b, 0xaa, ++ 0x5d, 0xf3, 0xf1, 0xf9, 0xd0, 0xf4, 0x13, 0x3d, 0xc8, 0x56, 0x1e, 0x9e, ++ 0xf9, 0xd5, 0x20, 0x3e, 0xd1, 0xd7, 0x8c, 0xe3, 0xdb, 0x5b, 0x58, 0x08, ++ 0xf5, 0x4c, 0x8a, 0x89, 0xc2, 0xf8, 0x8e, 0x7a, 0x28, 0xc3, 0xf8, 0xc9, ++ 0xa2, 0x3e, 0x39, 0xc0, 0xcb, 0x29, 0xa2, 0x3e, 0xa5, 0x8e, 0x97, 0x73, ++ 0x7c, 0x2f, 0x48, 0xd5, 0x38, 0xb1, 0x84, 0x78, 0x44, 0x8e, 0xd5, 0x39, ++ 0xb7, 0x10, 0xf9, 0xde, 0x32, 0xc6, 0xcf, 0xb7, 0x8a, 0xf3, 0xed, 0x3b, ++ 0x04, 0xdf, 0x1d, 0x63, 0x75, 0xce, 0xaf, 0xc6, 0xfa, 0xdb, 0x18, 0xe5, ++ 0xbd, 0xab, 0xf5, 0x8f, 0x8b, 0xfa, 0x4c, 0xeb, 0xb1, 0xae, 0xb1, 0xc8, ++ 0x97, 0x17, 0x6a, 0xbf, 0xdf, 0x2a, 0xe0, 0x90, 0x61, 0x3d, 0xd6, 0x33, ++ 0x8b, 0xe2, 0x16, 0xda, 0x7a, 0x35, 0xce, 0x90, 0x66, 0x3d, 0x77, 0x84, ++ 0xbe, 0x2f, 0xd1, 0xd6, 0x3f, 0x2a, 0xbe, 0xb7, 0x59, 0xcf, 0x0d, 0xce, ++ 0xc2, 0xfa, 0x42, 0xed, 0xf8, 0x0f, 0x8a, 0x7a, 0x8b, 0x95, 0xf3, 0x43, ++ 0xe6, 0xe7, 0xf7, 0x94, 0xaa, 0xf5, 0x3f, 0x14, 0xf5, 0x66, 0x2b, 0x3f, ++ 0xe7, 0x05, 0x3c, 0x59, 0x53, 0xdf, 0x2d, 0xc6, 0xef, 0x90, 0x42, 0x84, ++ 0x1f, 0xba, 0x8b, 0x15, 0xf7, 0x4f, 0x1a, 0xf7, 0x5b, 0xee, 0x6c, 0x63, ++ 0x57, 0xe2, 0xfe, 0xe9, 0x69, 0x1b, 0xa2, 0x7d, 0xf4, 0x50, 0xdb, 0x05, ++ 0xc2, 0xd3, 0x39, 0xcc, 0xf3, 0x99, 0x16, 0xdb, 0x57, 0xf6, 0x56, 0x36, ++ 0xe2, 0xb9, 0xeb, 0x73, 0x82, 0x9f, 0x24, 0x7b, 0x22, 0x3e, 0xdf, 0x08, ++ 0xfc, 0x4e, 0xad, 0x77, 0xda, 0xf9, 0xb9, 0x72, 0xd9, 0x6d, 0x20, 0x3a, ++ 0x32, 0x5a, 0x05, 0xbf, 0x10, 0xfb, 0x30, 0xca, 0x2f, 0xa4, 0x16, 0x2f, ++ 0x27, 0x2e, 0xee, 0x4f, 0xfe, 0x26, 0x7a, 0x86, 0x0d, 0x76, 0x1e, 0xf5, ++ 0x8b, 0x5c, 0xf8, 0x43, 0x7a, 0xce, 0xbe, 0x4b, 0xc7, 0x02, 0x71, 0x7c, ++ 0x2b, 0xab, 0x21, 0x89, 0x05, 0xe2, 0xda, 0xbb, 0x97, 0x39, 0x35, 0xe5, ++ 0xf4, 0xdb, 0xb2, 0x34, 0xed, 0x5d, 0x0b, 0x0b, 0x34, 0xf5, 0xd6, 0xf2, ++ 0x89, 0x9a, 0x7a, 0xe6, 0xcb, 0xa1, 0xfd, 0xb2, 0x56, 0xd0, 0x55, 0x52, ++ 0x49, 0x99, 0xa6, 0x5e, 0x3d, 0xef, 0xce, 0x7a, 0x72, 0x34, 0xfa, 0xb3, ++ 0xbe, 0x70, 0x86, 0xa6, 0xdd, 0xb9, 0x62, 0x0f, 0xfd, 0x8e, 0xc7, 0xc9, ++ 0xb9, 0xea, 0xef, 0x7d, 0x78, 0x4d, 0xc8, 0x17, 0xd6, 0xda, 0x0a, 0x32, ++ 0x50, 0xee, 0x3c, 0xdb, 0x36, 0x1d, 0x95, 0x6c, 0xf6, 0x3c, 0xec, 0x27, ++ 0x3c, 0xa2, 0xf4, 0x9c, 0x83, 0xe7, 0xf9, 0x3e, 0x87, 0xf1, 0x51, 0xa8, ++ 0xff, 0xc7, 0x36, 0x1f, 0xbd, 0xdf, 0x03, 0xf5, 0xa0, 0xb9, 0xb0, 0x27, ++ 0x61, 0xbf, 0x79, 0xa0, 0xfd, 0xae, 0x36, 0x3b, 0x95, 0x9f, 0x68, 0x73, ++ 0xd3, 0x73, 0x47, 0x9b, 0x87, 0x9e, 0x8f, 0xb7, 0x15, 0x53, 0xfd, 0xd6, ++ 0x36, 0x2f, 0x95, 0x1f, 0x83, 0xfe, 0xf1, 0xf9, 0x28, 0xf4, 0x83, 0xef, ++ 0x1f, 0x69, 0xab, 0xa1, 0xf2, 0xa6, 0x36, 0x3f, 0x95, 0x1f, 0x6e, 0xab, ++ 0xa3, 0xf2, 0x83, 0x6d, 0x01, 0x7a, 0xfe, 0xb0, 0xad, 0x9e, 0xde, 0x77, ++ 0xb7, 0xb5, 0x50, 0xf9, 0x81, 0xb6, 0x56, 0x7a, 0xde, 0xdf, 0x16, 0xa4, ++ 0x67, 0x47, 0x5b, 0x17, 0xd5, 0x17, 0x0b, 0xf9, 0xf6, 0x9c, 0x38, 0x2f, ++ 0xf8, 0x5c, 0x25, 0x3f, 0xff, 0x9b, 0x88, 0xc7, 0xc9, 0x39, 0xc2, 0x8f, ++ 0x26, 0xe2, 0xf8, 0xb6, 0x58, 0x1c, 0x7f, 0x72, 0x0e, 0xc6, 0xf1, 0xfb, ++ 0x22, 0x9a, 0x7b, 0xd6, 0x71, 0xdd, 0xd4, 0x9f, 0x99, 0xaf, 0x3f, 0xb1, ++ 0xbf, 0x2a, 0xd1, 0xdf, 0x44, 0x36, 0xd8, 0x6e, 0xe1, 0xfb, 0x98, 0xe2, ++ 0x7f, 0xe3, 0xfa, 0xbd, 0xf7, 0x59, 0x80, 0xde, 0xc7, 0xb4, 0x70, 0x3c, ++ 0xe4, 0xf7, 0x0f, 0x51, 0x7d, 0x66, 0x3d, 0xc7, 0x45, 0x95, 0x98, 0x2f, ++ 0x73, 0x05, 0x59, 0x76, 0x05, 0x3f, 0xee, 0x89, 0xed, 0xce, 0x48, 0x83, ++ 0x55, 0x16, 0x1e, 0x0f, 0x25, 0x7f, 0x00, 0x73, 0xc3, 0x3a, 0x2b, 0xc4, ++ 0x3d, 0x34, 0x44, 0x76, 0x21, 0x1d, 0xce, 0x4b, 0x99, 0xce, 0xe5, 0xa6, ++ 0x8a, 0xd7, 0xe8, 0xba, 0x1d, 0x7c, 0x9e, 0xb8, 0xfe, 0x91, 0xe6, 0xfb, ++ 0x6d, 0x31, 0x5f, 0xb9, 0xbc, 0x8f, 0xdf, 0x33, 0x51, 0xd3, 0x13, 0x46, ++ 0xb2, 0x4f, 0xf2, 0xb5, 0xd0, 0x3d, 0x13, 0xa6, 0x3a, 0x7f, 0x18, 0x7f, ++ 0x47, 0xc2, 0xe5, 0x0f, 0xd0, 0xb9, 0xf7, 0x89, 0x17, 0xe6, 0x80, 0x71, ++ 0x03, 0x7c, 0xe6, 0xc2, 0x55, 0xcc, 0x03, 0xcf, 0xec, 0x06, 0xad, 0xdd, ++ 0x93, 0xb5, 0xac, 0x4c, 0x63, 0x5f, 0xc8, 0x17, 0x1e, 0x62, 0x9e, 0xa9, ++ 0xd0, 0x6f, 0x89, 0xd6, 0x3e, 0x49, 0x2a, 0x5c, 0xab, 0xf9, 0xce, 0x94, ++ 0x7d, 0x8f, 0xa6, 0xde, 0xe0, 0xba, 0x4f, 0x53, 0xbf, 0x64, 0x4d, 0xfe, ++ 0x7a, 0x37, 0xc2, 0x73, 0x0c, 0xa3, 0x38, 0x89, 0x71, 0x63, 0x3b, 0xc3, ++ 0xd0, 0xde, 0xf2, 0xde, 0x4d, 0x34, 0xaf, 0x7b, 0xc5, 0x3a, 0xce, 0x48, ++ 0x1e, 0x3a, 0x37, 0x1b, 0xdc, 0xa7, 0xc6, 0xc9, 0xb9, 0x7e, 0xfe, 0x8c, ++ 0x90, 0x2b, 0xcc, 0xb4, 0x91, 0xf6, 0xc3, 0x78, 0x07, 0x2f, 0x16, 0xa5, ++ 0x04, 0x75, 0x28, 0x17, 0x3e, 0xff, 0xa7, 0x14, 0xe2, 0x47, 0x4f, 0x3f, ++ 0xa1, 0x0b, 0xa1, 0x1f, 0x74, 0x02, 0x0b, 0xe9, 0x70, 0xff, 0x4f, 0x02, ++ 0x75, 0x0f, 0xeb, 0x27, 0xe3, 0x4d, 0xb5, 0x32, 0x5d, 0x5d, 0x22, 0x63, ++ 0xb9, 0x94, 0x79, 0x64, 0x2c, 0x4f, 0x65, 0x43, 0x64, 0x9f, 0x80, 0x7e, ++ 0x7e, 0x27, 0xd2, 0x0b, 0xe8, 0xe7, 0x4f, 0x98, 0x31, 0x4e, 0x97, 0x13, ++ 0x78, 0x86, 0xe7, 0x0f, 0x85, 0x49, 0x6e, 0x16, 0x09, 0x7c, 0x16, 0xa9, ++ 0xf6, 0xc8, 0x16, 0x25, 0xd1, 0x3f, 0x7a, 0x77, 0x0e, 0xf9, 0x3f, 0xb4, ++ 0xe7, 0x86, 0x3a, 0x85, 0x9e, 0xde, 0xee, 0xa8, 0xc8, 0xc0, 0xf8, 0xe4, ++ 0x99, 0x51, 0xf2, 0xbb, 0x6c, 0xee, 0x19, 0x33, 0xf0, 0xf7, 0xac, 0x6c, ++ 0x99, 0xd3, 0xe9, 0xa9, 0xbe, 0x7f, 0xd0, 0xa3, 0x1b, 0xf1, 0x3c, 0xec, ++ 0xc6, 0x1c, 0xd5, 0x8f, 0xc4, 0xe9, 0x7e, 0x02, 0x10, 0xb9, 0xa0, 0xfb, ++ 0x8d, 0x38, 0x8f, 0xd3, 0xe5, 0xbf, 0x4a, 0x47, 0x73, 0xaf, 0xa9, 0x70, ++ 0x88, 0xe8, 0xff, 0x8c, 0xe4, 0x73, 0x2f, 0x46, 0xb8, 0xbe, 0x25, 0x73, ++ 0x3a, 0x1c, 0xc8, 0xa4, 0x75, 0x29, 0x02, 0xae, 0xca, 0xbe, 0x4a, 0xf7, ++ 0x62, 0x80, 0x9f, 0xf2, 0xce, 0x58, 0x6f, 0x90, 0xc5, 0xc6, 0x79, 0xba, ++ 0xcd, 0x37, 0x43, 0x51, 0x62, 0xe5, 0x22, 0x91, 0x9f, 0xb8, 0xb7, 0x6d, ++ 0xfe, 0x8c, 0xea, 0xb8, 0xf7, 0xfd, 0x02, 0x7f, 0xc5, 0x6c, 0xb0, 0x06, ++ 0xe5, 0x53, 0x71, 0x89, 0xce, 0x1b, 0xa2, 0x9e, 0xdd, 0x1a, 0xfe, 0x65, ++ 0x2e, 0xec, 0xf1, 0xe1, 0x79, 0x6e, 0xa5, 0x8c, 0x79, 0x91, 0xbd, 0x4d, ++ 0x60, 0x3d, 0xf7, 0xa1, 0xac, 0x56, 0xfe, 0x22, 0x53, 0xbe, 0x89, 0x72, ++ 0xe8, 0x0a, 0xe6, 0x01, 0xbb, 0xc0, 0x6a, 0x0d, 0x33, 0xcc, 0xcf, 0xe9, ++ 0x8f, 0xee, 0x6f, 0xa6, 0xf9, 0x9d, 0xa3, 0xaf, 0xec, 0xd5, 0x29, 0x74, ++ 0x2f, 0x5f, 0x56, 0x94, 0xef, 0xa1, 0x4c, 0xc4, 0xdf, 0x35, 0x1a, 0x44, ++ 0xfa, 0xf9, 0xaa, 0x57, 0xcf, 0xd7, 0x75, 0x48, 0x5b, 0x5f, 0x6c, 0xe5, ++ 0x79, 0x34, 0x2b, 0x8a, 0x0d, 0x21, 0x8f, 0x84, 0xe1, 0xed, 0x1e, 0xba, ++ 0x7f, 0x4e, 0xd9, 0x29, 0x31, 0x54, 0xfd, 0x95, 0xbf, 0xcc, 0x22, 0x38, ++ 0xb0, 0x97, 0x2c, 0x44, 0x7f, 0x96, 0x2d, 0x53, 0xe8, 0xea, 0xea, 0xeb, ++ 0x94, 0x40, 0x08, 0xe9, 0xe3, 0x74, 0xd8, 0xf3, 0x92, 0x6e, 0xac, 0xa0, ++ 0x45, 0x68, 0xd7, 0x38, 0xc9, 0xb0, 0x1b, 0xf5, 0xb1, 0xf1, 0x08, 0x17, ++ 0x5c, 0x50, 0x61, 0x31, 0xc1, 0x75, 0xb9, 0x58, 0xef, 0xde, 0xb6, 0xc5, ++ 0x04, 0xa7, 0x77, 0x04, 0xbe, 0x3a, 0x73, 0x12, 0xe6, 0xc3, 0xbc, 0x3e, ++ 0xbc, 0x9f, 0x71, 0x45, 0xaf, 0xea, 0xff, 0xd0, 0xae, 0xf3, 0xc1, 0xf2, ++ 0xaa, 0xeb, 0xf1, 0x3e, 0xbb, 0x8e, 0x41, 0x59, 0xe8, 0x4a, 0x5a, 0x78, ++ 0x6e, 0xd0, 0x0f, 0x4e, 0xc1, 0xdf, 0x88, 0x3b, 0x1d, 0x81, 0x79, 0xc9, ++ 0x34, 0xcf, 0x77, 0x10, 0xff, 0xf2, 0x96, 0x0a, 0xfa, 0x9d, 0x23, 0x10, ++ 0x20, 0xb4, 0xbe, 0xc6, 0x27, 0xc0, 0xde, 0xcf, 0x27, 0x7e, 0x54, 0x43, ++ 0x72, 0x7b, 0x9a, 0x8e, 0xf2, 0x44, 0x13, 0xe9, 0xea, 0xd7, 0x82, 0x8f, ++ 0x2d, 0xce, 0xe1, 0xfe, 0x3c, 0x9b, 0xfb, 0xaa, 0x19, 0xf8, 0x7b, 0x6b, ++ 0xb1, 0xf2, 0x4c, 0xa2, 0xcf, 0x67, 0x75, 0xdc, 0xcf, 0x1a, 0xd4, 0x71, ++ 0xfb, 0x52, 0xcd, 0xa3, 0x00, 0xc5, 0xc1, 0x83, 0x76, 0x5d, 0x41, 0xae, ++ 0xea, 0x67, 0xec, 0x64, 0xf3, 0x50, 0x5e, 0x3b, 0x74, 0x94, 0x7f, 0x27, ++ 0xef, 0x4a, 0xa2, 0x73, 0x80, 0xb2, 0x43, 0xa1, 0x7c, 0xdf, 0x4e, 0x6b, ++ 0xb5, 0x7d, 0x35, 0xf6, 0x63, 0x57, 0x28, 0xbe, 0x31, 0x47, 0x9e, 0x39, ++ 0x88, 0x7a, 0xb3, 0xd1, 0xa1, 0x9b, 0x8a, 0x7a, 0xf7, 0xe1, 0xdd, 0xf7, ++ 0x0c, 0x62, 0x9e, 0x87, 0x9c, 0xa3, 0x30, 0xf4, 0x17, 0x75, 0xda, 0x15, ++ 0xae, 0x77, 0x64, 0xeb, 0x28, 0x2f, 0x4a, 0x71, 0x54, 0x9b, 0x30, 0x1e, ++ 0x52, 0x64, 0x3d, 0x51, 0x89, 0xf0, 0x3c, 0xb8, 0xeb, 0xfb, 0xe4, 0xdf, ++ 0x90, 0xbf, 0x27, 0x72, 0x35, 0x84, 0x3f, 0x49, 0x2f, 0x50, 0xd6, 0xc9, ++ 0x5a, 0xa8, 0xff, 0x60, 0xb6, 0x22, 0xee, 0xcd, 0xf0, 0xd5, 0x96, 0xa6, ++ 0x0b, 0x57, 0xbe, 0x07, 0xed, 0x9f, 0x9a, 0x4f, 0xd1, 0x8f, 0x72, 0xd8, ++ 0x7e, 0xce, 0x8c, 0xfa, 0x8a, 0xc7, 0xba, 0x82, 0xfc, 0x69, 0x69, 0xb9, ++ 0xdc, 0x2e, 0xd4, 0x63, 0xdc, 0x0b, 0xca, 0x4f, 0xac, 0x3b, 0xe7, 0x40, ++ 0xbe, 0xf5, 0xd6, 0xae, 0xf5, 0xce, 0x7c, 0xd4, 0x9f, 0x43, 0x0a, 0xe9, ++ 0x20, 0xc5, 0x7f, 0xee, 0xc8, 0xa2, 0xf3, 0xdd, 0xbb, 0x0c, 0x74, 0xfe, ++ 0x5c, 0x85, 0x6b, 0x5e, 0x50, 0xd1, 0xc4, 0xcf, 0x72, 0x5a, 0xb5, 0x65, ++ 0x63, 0x42, 0x1c, 0x4d, 0x9f, 0x70, 0xfe, 0x27, 0x09, 0xc7, 0xa7, 0xfd, ++ 0x5e, 0xc7, 0xc2, 0x71, 0xeb, 0xd1, 0xbb, 0xb9, 0xbd, 0xc6, 0x5c, 0x56, ++ 0xb2, 0x77, 0xd2, 0x72, 0x25, 0xee, 0xe7, 0x11, 0x65, 0x6b, 0x2e, 0xbf, ++ 0x77, 0x70, 0xaf, 0x3e, 0x98, 0xe5, 0x05, 0xf8, 0x1c, 0xda, 0xb5, 0x22, ++ 0x0f, 0xd7, 0x75, 0xfe, 0x95, 0x00, 0xe5, 0xdb, 0x8e, 0xa6, 0xef, 0x7f, ++ 0x94, 0xe3, 0x11, 0xf8, 0x0b, 0x9a, 0x75, 0x74, 0x8f, 0x69, 0xd8, 0x8c, ++ 0xf9, 0xb7, 0x4f, 0xb5, 0xb1, 0x34, 0xd4, 0xef, 0x4c, 0x21, 0x85, 0xf2, ++ 0x9f, 0xf7, 0x08, 0x7e, 0x56, 0x68, 0xe5, 0xf4, 0xff, 0xfb, 0x5c, 0x4e, ++ 0xe7, 0x89, 0xcf, 0xc2, 0x1e, 0xbe, 0xef, 0x94, 0xe7, 0x92, 0x42, 0x16, ++ 0xc4, 0x9b, 0xbd, 0xaf, 0x2c, 0x08, 0x74, 0x32, 0xe9, 0xf5, 0xb9, 0xcc, ++ 0x03, 0xf2, 0xaf, 0xd0, 0xee, 0x23, 0xff, 0x61, 0x61, 0xab, 0x21, 0x0d, ++ 0xe3, 0xf8, 0x73, 0x7e, 0x62, 0x25, 0x3a, 0x39, 0x67, 0x4d, 0x22, 0x3f, ++ 0xa1, 0xd2, 0x9a, 0xe4, 0xc5, 0xf7, 0x1d, 0xbb, 0x2b, 0x8a, 0xe3, 0xcf, ++ 0x35, 0x85, 0xda, 0xec, 0x69, 0x98, 0x1f, 0xb3, 0xbb, 0xcd, 0x94, 0x86, ++ 0x7c, 0x2a, 0x34, 0x0a, 0x7f, 0x1d, 0xeb, 0xd0, 0x51, 0xde, 0xb0, 0x47, ++ 0xc7, 0xf3, 0xda, 0xbe, 0x25, 0xe6, 0xf5, 0xad, 0x5c, 0x0b, 0xbf, 0x47, ++ 0x39, 0x97, 0xf3, 0x99, 0x27, 0x95, 0xe0, 0x02, 0x9c, 0xe7, 0x93, 0x80, ++ 0x4f, 0xcc, 0x57, 0x3e, 0xb8, 0x91, 0xeb, 0xc3, 0x6b, 0xdb, 0x4d, 0x34, ++ 0x8f, 0xb5, 0x6f, 0x8d, 0x25, 0xbd, 0x6a, 0x34, 0xb8, 0x3d, 0xdd, 0xe6, ++ 0x4e, 0xc3, 0x7b, 0xd8, 0x77, 0x6f, 0xd4, 0x65, 0xa1, 0xff, 0xa8, 0xb2, ++ 0xbb, 0x70, 0x03, 0xde, 0x47, 0xb0, 0xd6, 0xc6, 0xef, 0x63, 0x95, 0x53, ++ 0x26, 0x92, 0xbf, 0x93, 0xfd, 0x42, 0xcf, 0x50, 0x7f, 0xef, 0x48, 0x9e, ++ 0xe1, 0x5d, 0x1a, 0xc7, 0xdf, 0xe5, 0x94, 0x99, 0xc5, 0x48, 0x57, 0xb2, ++ 0x1c, 0xcc, 0x42, 0xbf, 0x88, 0x7f, 0x67, 0xd5, 0xf5, 0x98, 0xb7, 0x08, ++ 0xf8, 0xdb, 0x86, 0xe5, 0xba, 0xdc, 0x89, 0xd7, 0x63, 0x5e, 0xe3, 0x5e, ++ 0x5b, 0x30, 0x0b, 0xf3, 0x1c, 0x03, 0xb9, 0x53, 0x78, 0x39, 0x2d, 0xb8, ++ 0x0d, 0xf3, 0x1c, 0xeb, 0x73, 0xcb, 0x78, 0x39, 0x27, 0x98, 0x85, 0xbf, ++ 0xe7, 0xd4, 0x92, 0x5b, 0xc1, 0xbf, 0x1f, 0x17, 0xdc, 0x86, 0xe5, 0xd6, ++ 0xdc, 0x19, 0xbc, 0x1e, 0x7d, 0x4f, 0xc0, 0x3b, 0x83, 0xb9, 0x57, 0x5d, ++ 0x1f, 0x84, 0xf1, 0x3a, 0x0c, 0xde, 0x7a, 0x64, 0xc8, 0x3f, 0x86, 0xf9, ++ 0x97, 0xc0, 0xfc, 0xfb, 0xc4, 0xf3, 0x3e, 0x01, 0x17, 0xb5, 0xfe, 0x05, ++ 0x7c, 0x0f, 0x70, 0xde, 0x2f, 0x9e, 0x89, 0xf5, 0x2f, 0x89, 0xef, 0xfa, ++ 0x47, 0xa9, 0x7f, 0x55, 0xd4, 0x0f, 0x8c, 0xd2, 0xff, 0x6b, 0xe2, 0xbb, ++ 0xf0, 0x28, 0xdf, 0x1f, 0x12, 0xdf, 0x1d, 0x1e, 0xe5, 0xfb, 0x37, 0xc5, ++ 0x77, 0x47, 0x46, 0xa9, 0xff, 0xb9, 0xa8, 0x7f, 0x7b, 0x94, 0xfe, 0x7f, ++ 0x29, 0xbe, 0x1b, 0x1c, 0xe5, 0xfb, 0x5f, 0x89, 0xef, 0x7e, 0x3d, 0xca, ++ 0xf7, 0xbf, 0x11, 0xdf, 0xbd, 0x3f, 0x4a, 0xfd, 0x87, 0xa2, 0xfe, 0x5f, ++ 0x13, 0xfa, 0x3f, 0x2a, 0xda, 0x47, 0xc4, 0xfb, 0x02, 0xdb, 0xc6, 0x0f, ++ 0xc3, 0x40, 0x77, 0x05, 0xc0, 0x47, 0x90, 0x2f, 0x15, 0xdb, 0x36, 0x3a, ++ 0x71, 0x9f, 0xef, 0xee, 0x2a, 0x27, 0xfa, 0xef, 0xa8, 0xe0, 0xf1, 0x1d, ++ 0x95, 0xde, 0x0b, 0xf0, 0x77, 0x94, 0xa0, 0xfe, 0xcb, 0x5c, 0x7e, 0x3f, ++ 0xe8, 0x97, 0x82, 0xff, 0x6e, 0x17, 0xfd, 0x03, 0x1d, 0x3e, 0x8c, 0x74, ++ 0xb7, 0xf6, 0x1d, 0x99, 0xf2, 0x5d, 0x3a, 0x74, 0xde, 0x53, 0x21, 0xe4, ++ 0xa3, 0x1b, 0x74, 0xa4, 0x0f, 0xac, 0x7d, 0x8b, 0xdb, 0xe7, 0x6b, 0xbb, ++ 0x95, 0x50, 0xfc, 0x39, 0x88, 0xed, 0x09, 0xf3, 0x5f, 0x2f, 0xe6, 0xd7, ++ 0x29, 0xe6, 0xdb, 0x9b, 0xcb, 0xf3, 0xa9, 0x8d, 0x6e, 0x77, 0x5a, 0x6d, ++ 0xbc, 0x1f, 0xc9, 0xae, 0x2d, 0x63, 0x7a, 0x14, 0xf2, 0x5d, 0xe0, 0xdf, ++ 0x94, 0x3f, 0x5b, 0xdc, 0x5d, 0xd5, 0x55, 0x0c, 0xe5, 0x31, 0x4e, 0x1d, ++ 0x69, 0x20, 0x4a, 0xa3, 0x29, 0x8c, 0xf7, 0x22, 0x28, 0x36, 0x21, 0x17, ++ 0xec, 0xe5, 0x3d, 0xc5, 0x38, 0x3f, 0xab, 0x42, 0xe7, 0xc1, 0x15, 0x87, ++ 0x12, 0xde, 0x8b, 0xdf, 0xbb, 0xcb, 0x49, 0xbf, 0x53, 0xe7, 0xd7, 0x69, ++ 0x55, 0xe8, 0x5e, 0x2c, 0xd9, 0xc6, 0xe5, 0xc0, 0x9c, 0x9f, 0xcc, 0xb4, ++ 0xa3, 0x9e, 0xd5, 0xc9, 0x02, 0x83, 0x3e, 0xfc, 0xde, 0xad, 0x90, 0xfe, ++ 0x7e, 0xb0, 0xab, 0xcc, 0x8e, 0x7c, 0xcf, 0x60, 0x5b, 0x66, 0xc7, 0xfd, ++ 0xbb, 0xd6, 0xc3, 0xf7, 0x7f, 0x75, 0x53, 0x71, 0x12, 0xf2, 0x6b, 0xf9, ++ 0x41, 0x1d, 0xf1, 0xef, 0xc3, 0x76, 0xbe, 0xdf, 0x77, 0xba, 0x75, 0xe4, ++ 0xb7, 0x00, 0xb9, 0x42, 0xe7, 0x4a, 0x80, 0x5f, 0x7b, 0x51, 0x46, 0x8c, ++ 0x67, 0xe1, 0x76, 0x3a, 0xa7, 0xf0, 0xd0, 0x4b, 0x8b, 0xb9, 0x5f, 0x8f, ++ 0xd9, 0x4a, 0x2b, 0xe8, 0xdc, 0x86, 0x1a, 0x0f, 0x96, 0x94, 0x38, 0xfd, ++ 0xff, 0x04, 0xc2, 0x07, 0xcf, 0x4b, 0x08, 0x39, 0xa2, 0xa0, 0x7c, 0x81, ++ 0xe7, 0x93, 0xe5, 0xe2, 0xbc, 0x41, 0x90, 0xfb, 0x9f, 0xf2, 0x14, 0xe6, ++ 0x1e, 0x13, 0x77, 0x6e, 0xf2, 0x44, 0xae, 0xcc, 0xcf, 0x63, 0x28, 0x08, ++ 0x23, 0xe8, 0x4b, 0xae, 0xa5, 0xfb, 0x81, 0x72, 0xd7, 0x29, 0x1a, 0xff, ++ 0x7b, 0xf6, 0x5d, 0xda, 0xb2, 0x21, 0x41, 0x6e, 0x28, 0x09, 0x72, 0x65, ++ 0x6c, 0x17, 0xf0, 0xc9, 0x38, 0xb9, 0x93, 0x1f, 0xb4, 0x6b, 0xca, 0xef, ++ 0xe5, 0x0a, 0xbf, 0x99, 0x97, 0x79, 0x51, 0x7f, 0x9d, 0xf3, 0x93, 0x8d, ++ 0xc4, 0x0f, 0xcf, 0xa1, 0x7c, 0x93, 0x46, 0xe7, 0x7b, 0x51, 0xfe, 0x2b, ++ 0xf8, 0xf1, 0x93, 0xe2, 0xbe, 0x9b, 0x27, 0x83, 0xfc, 0xbc, 0xee, 0xc1, ++ 0x8d, 0x65, 0x3f, 0x47, 0x7c, 0xaf, 0xed, 0xd6, 0xd1, 0xfd, 0xce, 0x97, ++ 0xca, 0x47, 0xb7, 0xe7, 0x32, 0x82, 0xc3, 0xb8, 0x00, 0xc8, 0x1d, 0xd4, ++ 0x67, 0x14, 0x96, 0x85, 0xf6, 0xd2, 0x37, 0xc1, 0x61, 0x9c, 0xde, 0xef, ++ 0xa4, 0xfb, 0x0b, 0xbe, 0x01, 0x1e, 0xe3, 0x1e, 0x2d, 0x77, 0x22, 0xbf, ++ 0x1d, 0x17, 0x50, 0x48, 0xee, 0x0c, 0x93, 0x1b, 0xdf, 0x00, 0xaf, 0xe7, ++ 0x25, 0xef, 0xfb, 0x01, 0xc4, 0xa3, 0x23, 0x89, 0xeb, 0xd5, 0x76, 0xbe, ++ 0xee, 0xce, 0x74, 0x17, 0xbf, 0xf7, 0x47, 0x9c, 0x03, 0x94, 0x85, 0xbe, ++ 0x76, 0xbf, 0xf0, 0x83, 0x2b, 0x29, 0x73, 0x3c, 0xf8, 0x53, 0x1c, 0x9d, ++ 0x8e, 0x16, 0x2a, 0xaf, 0x97, 0xbc, 0x19, 0xd7, 0x42, 0xfb, 0x07, 0xa4, ++ 0x80, 0x1d, 0xcb, 0x47, 0x9c, 0x49, 0x5c, 0xee, 0xe4, 0x24, 0x11, 0x1d, ++ 0xee, 0x45, 0x5d, 0x86, 0xee, 0x2f, 0xcc, 0xf4, 0xa3, 0x7f, 0xa4, 0x2f, ++ 0x64, 0x50, 0xef, 0x03, 0x0c, 0xe3, 0xff, 0xed, 0xc3, 0x3c, 0x19, 0xf5, ++ 0xbe, 0x41, 0x37, 0xe9, 0x67, 0xa2, 0xfc, 0xe0, 0xf5, 0xd5, 0xd8, 0x5e, ++ 0xb1, 0x4f, 0x42, 0x95, 0xb3, 0x28, 0xaf, 0xe7, 0x61, 0xfd, 0x95, 0xd0, ++ 0xde, 0xc0, 0xa2, 0xed, 0xf1, 0x5c, 0xd3, 0xb3, 0x87, 0x75, 0xa2, 0xbf, ++ 0xcd, 0x0f, 0xa3, 0xbe, 0xba, 0x2f, 0x89, 0x69, 0xee, 0x5b, 0xdc, 0x87, ++ 0x7e, 0x74, 0x2a, 0x6f, 0x7d, 0x18, 0xef, 0x4f, 0x84, 0xf1, 0xae, 0x95, ++ 0xc1, 0x06, 0x9b, 0xfe, 0xc4, 0x13, 0x0f, 0x5b, 0xaf, 0x88, 0xcd, 0x67, ++ 0x6a, 0xe8, 0xa9, 0x87, 0xdb, 0x29, 0x5f, 0x95, 0xdb, 0x25, 0x0e, 0xc6, ++ 0xef, 0xc3, 0x3e, 0xed, 0x89, 0x24, 0xe3, 0x76, 0x01, 0xfb, 0xc4, 0x93, ++ 0x87, 0x76, 0xf9, 0xae, 0x13, 0xe9, 0x9a, 0xdf, 0x3f, 0x13, 0xed, 0x53, ++ 0x44, 0xfb, 0xa6, 0x81, 0xa1, 0xa6, 0xe7, 0x3c, 0xd4, 0xbe, 0x88, 0xda, ++ 0xf7, 0x0f, 0x25, 0x97, 0xd0, 0xfe, 0x1a, 0xaa, 0x88, 0x6f, 0x9f, 0x2c, ++ 0xec, 0xfd, 0xb8, 0xf6, 0x25, 0x5f, 0xd7, 0xbe, 0x58, 0x9d, 0xcf, 0x73, ++ 0xbf, 0xba, 0xb1, 0x84, 0xb7, 0x2f, 0xc3, 0xf6, 0x67, 0x3c, 0x91, 0x74, ++ 0xca, 0x3d, 0x49, 0x98, 0x4f, 0xea, 0xf0, 0xfe, 0xa7, 0x7f, 0x5d, 0xff, ++ 0x13, 0x45, 0xfb, 0xd3, 0xe1, 0x5f, 0x51, 0xfb, 0x33, 0x2c, 0x92, 0x3e, ++ 0x39, 0x9f, 0xbe, 0xbb, 0x3a, 0x0f, 0xe8, 0xf8, 0xec, 0xdb, 0xbf, 0xaa, ++ 0x10, 0xeb, 0x4e, 0x47, 0x3d, 0x19, 0xb8, 0xa2, 0x0f, 0xdf, 0x27, 0x7b, ++ 0x98, 0xb8, 0x77, 0xad, 0x85, 0xf4, 0xe7, 0x3e, 0x53, 0x8f, 0x1d, 0xf5, ++ 0x35, 0xb3, 0xbe, 0xc7, 0x8f, 0x7c, 0xb7, 0x10, 0xef, 0x4f, 0x9a, 0x1e, ++ 0x7b, 0xce, 0xca, 0x2b, 0xe4, 0x7a, 0x55, 0xc2, 0xfb, 0x3e, 0x13, 0x4b, ++ 0xad, 0x45, 0x7a, 0x6c, 0xd5, 0x91, 0xfd, 0xd2, 0x67, 0x1a, 0x2c, 0x2b, ++ 0x41, 0x7d, 0xfa, 0x65, 0x2b, 0x6b, 0x87, 0x31, 0x74, 0x79, 0xeb, 0xbc, ++ 0xc8, 0x07, 0xfb, 0x23, 0x6b, 0xbd, 0x25, 0xd0, 0x6e, 0x67, 0xf6, 0x4c, ++ 0xb2, 0x2b, 0xf6, 0x19, 0x5a, 0xfa, 0xe8, 0x9c, 0xed, 0x62, 0x2b, 0x9d, ++ 0x03, 0xdd, 0x69, 0xef, 0xb1, 0xe3, 0xfe, 0x31, 0x3b, 0x7a, 0xec, 0x18, ++ 0x47, 0x90, 0xef, 0xe6, 0xfa, 0x93, 0xb2, 0xc4, 0x1a, 0x78, 0x0a, 0xe9, ++ 0x29, 0xbc, 0xb6, 0x78, 0x79, 0xdc, 0xfe, 0x9d, 0xea, 0xe1, 0xbf, 0x23, ++ 0xd3, 0xfd, 0x86, 0x75, 0x23, 0xda, 0x01, 0xdd, 0x7a, 0x6f, 0xcf, 0x78, ++ 0xd4, 0xb3, 0x6d, 0x0a, 0xe5, 0x81, 0x2b, 0x4b, 0x06, 0xe6, 0xd1, 0xb9, ++ 0xbd, 0x1f, 0xeb, 0x18, 0xf1, 0x77, 0x58, 0x57, 0x15, 0x94, 0x3b, 0x1b, ++ 0x75, 0x74, 0x2f, 0x7c, 0x9b, 0x67, 0xc9, 0x32, 0x84, 0x2b, 0x53, 0xfc, ++ 0xfe, 0x2a, 0xf8, 0x2e, 0x37, 0x4d, 0x91, 0xf0, 0x1c, 0xc4, 0xfd, 0x8a, ++ 0xdf, 0x84, 0xf1, 0x0b, 0xa3, 0xd0, 0xdb, 0x76, 0x7a, 0xf9, 0xef, 0xae, ++ 0xaa, 0xe3, 0x6e, 0xc8, 0xe3, 0xf2, 0x69, 0x43, 0x1e, 0xbf, 0x1f, 0xaa, ++ 0x7b, 0xf1, 0x73, 0xc5, 0x6f, 0xc2, 0x77, 0x3b, 0x5b, 0xd7, 0xf6, 0xe1, ++ 0x78, 0xe6, 0x09, 0x26, 0x86, 0xf9, 0x5e, 0x3b, 0xb3, 0x4f, 0x76, 0xe3, ++ 0xb9, 0xcd, 0xc7, 0xdd, 0x60, 0xf1, 0x02, 0x1c, 0xac, 0x0d, 0x3a, 0xfa, ++ 0x5d, 0x94, 0xc7, 0x6b, 0xa1, 0x4d, 0x0a, 0xfa, 0x33, 0x0c, 0x1a, 0x7f, ++ 0xc5, 0xf3, 0x52, 0x1f, 0xb5, 0x0f, 0x36, 0xea, 0xc8, 0x4e, 0xb0, 0x96, ++ 0x18, 0x34, 0xfe, 0x8d, 0xd4, 0x06, 0x9d, 0x0f, 0xfd, 0x8e, 0x3b, 0x3c, ++ 0x81, 0x7b, 0x71, 0xde, 0x53, 0xdf, 0x51, 0xae, 0xc5, 0xf1, 0xdc, 0xe3, ++ 0x14, 0x3b, 0xca, 0xa7, 0x07, 0xdd, 0xbf, 0x36, 0xe9, 0x60, 0x9e, 0xc9, ++ 0xe5, 0xda, 0x7e, 0xed, 0x33, 0xb5, 0xfd, 0x38, 0xab, 0xb5, 0xf5, 0xae, ++ 0x5a, 0x6d, 0x7d, 0xfa, 0x42, 0x6d, 0xbd, 0xfb, 0x36, 0x43, 0x82, 0xbf, ++ 0x46, 0x5b, 0xbe, 0x88, 0x82, 0x08, 0xe1, 0x08, 0x3c, 0xc0, 0x0a, 0x72, ++ 0x28, 0x89, 0x57, 0xb1, 0x24, 0xeb, 0x79, 0xfa, 0x5d, 0xae, 0xee, 0xc0, ++ 0xf6, 0x9e, 0xf1, 0xb0, 0x1e, 0xa3, 0x25, 0x58, 0xfa, 0x26, 0xcc, 0x37, ++ 0x69, 0x62, 0x12, 0xd9, 0xfb, 0x0f, 0xbc, 0x91, 0x84, 0x9b, 0x0f, 0xf8, ++ 0x0f, 0x23, 0xbe, 0xf3, 0xc0, 0x64, 0x46, 0xf9, 0xa7, 0x87, 0x72, 0xbe, ++ 0xef, 0x46, 0x79, 0x9a, 0x08, 0x9f, 0x9d, 0xd9, 0x06, 0x5a, 0xaf, 0xb5, ++ 0x10, 0xe0, 0x99, 0x8f, 0xf6, 0xfa, 0x29, 0xfa, 0xfd, 0x2c, 0x2b, 0x8b, ++ 0x6b, 0x97, 0x8f, 0xf0, 0xf1, 0x6d, 0xcf, 0x9b, 0xc6, 0xcb, 0xee, 0x0a, ++ 0xf4, 0xcf, 0x31, 0xe2, 0x83, 0xcf, 0xab, 0xfe, 0xe3, 0x1b, 0xf8, 0xb9, ++ 0xa6, 0x9d, 0xad, 0xdc, 0x2f, 0xfd, 0x60, 0x1d, 0xcf, 0xcf, 0xa3, 0x15, ++ 0x54, 0xe0, 0xfe, 0xe6, 0xed, 0x93, 0xf1, 0xf7, 0xbc, 0xa6, 0xa0, 0xdf, ++ 0xbe, 0xeb, 0x0e, 0xcc, 0x3b, 0x4c, 0x84, 0x6b, 0x06, 0xe6, 0xe3, 0xc8, ++ 0x31, 0xfa, 0x58, 0xaf, 0x9e, 0x23, 0xc1, 0x53, 0x8c, 0x15, 0x9c, 0x2d, ++ 0xe3, 0xbe, 0x3b, 0xee, 0xe1, 0x74, 0xf2, 0x93, 0x3c, 0x2e, 0xff, 0xf7, ++ 0x89, 0x7b, 0x0f, 0xa2, 0xed, 0x71, 0x1f, 0xa6, 0x33, 0x6e, 0xca, 0x42, ++ 0x7f, 0xaf, 0xe6, 0xa9, 0xfe, 0x07, 0x9e, 0x97, 0xbf, 0x59, 0x8d, 0xc7, ++ 0x88, 0x32, 0x5e, 0x17, 0x88, 0xe5, 0x7d, 0x87, 0x9d, 0xd7, 0xe2, 0x7e, ++ 0xda, 0xbc, 0xd0, 0x59, 0x86, 0xfb, 0xe9, 0x01, 0xa1, 0x97, 0xa5, 0x64, ++ 0x1b, 0x7c, 0x13, 0x60, 0xbe, 0x8f, 0x1c, 0x31, 0x04, 0xa5, 0xcb, 0xa0, ++ 0xac, 0xb0, 0xc3, 0x7a, 0x90, 0xe7, 0xfb, 0x9c, 0x7c, 0x5c, 0xc3, 0x5b, ++ 0x49, 0x41, 0x3c, 0xd7, 0xf4, 0x88, 0xbb, 0x9c, 0xce, 0x49, 0x7d, 0x24, ++ 0xe6, 0xf5, 0x42, 0xa5, 0xf7, 0xbd, 0x5a, 0xda, 0x8f, 0x0a, 0xe5, 0x39, ++ 0x3d, 0xe2, 0xf2, 0x9a, 0xcb, 0xb8, 0xbe, 0x81, 0x77, 0x4a, 0x33, 0xfa, ++ 0x49, 0x54, 0x50, 0x2d, 0x0e, 0xd6, 0x96, 0x91, 0x9d, 0xfa, 0x88, 0xcf, ++ 0x6b, 0xc6, 0xfd, 0xfa, 0x48, 0xb6, 0xd7, 0x8c, 0x79, 0xc2, 0xe6, 0x4c, ++ 0xc5, 0x8e, 0xfb, 0xd8, 0xe9, 0x56, 0xe8, 0xbe, 0xaa, 0x47, 0x4c, 0x01, ++ 0x3b, 0xea, 0x2d, 0x4e, 0x10, 0x80, 0xf8, 0x3b, 0x6d, 0x86, 0x9c, 0x9e, ++ 0xb9, 0x74, 0x3e, 0x08, 0x60, 0xa8, 0xab, 0xe0, 0x21, 0x01, 0x26, 0xf2, ++ 0xe9, 0x30, 0x9f, 0x2d, 0x55, 0xc0, 0x6b, 0xa7, 0x7b, 0x99, 0x1d, 0xcf, ++ 0x91, 0xbb, 0x0a, 0xf7, 0xff, 0x1d, 0xfa, 0xd5, 0x53, 0xb1, 0xbf, 0x64, ++ 0xfe, 0x1d, 0xc2, 0xc9, 0x21, 0xe0, 0x74, 0x3c, 0xcf, 0xc3, 0xf3, 0x83, ++ 0x45, 0xff, 0xa9, 0xcb, 0x5e, 0xa0, 0xf6, 0xf8, 0xd7, 0x59, 0x11, 0xd7, ++ 0x9f, 0x97, 0xd3, 0x97, 0x61, 0x2e, 0x0b, 0xd1, 0xef, 0x8d, 0x89, 0xf1, ++ 0xd5, 0x7e, 0xa2, 0xfd, 0x33, 0x1f, 0xf9, 0xed, 0xd7, 0xff, 0x9c, 0xc3, ++ 0xad, 0x3d, 0x87, 0xdf, 0xd3, 0x63, 0x58, 0xc3, 0xc8, 0x0e, 0x7b, 0xa1, ++ 0x32, 0xb0, 0xf7, 0x20, 0xc2, 0x27, 0x33, 0x89, 0xec, 0xec, 0x2c, 0x77, ++ 0x56, 0x15, 0xd2, 0x47, 0xd6, 0x91, 0x6d, 0x0b, 0xf0, 0x3c, 0xc0, 0xfa, ++ 0x9f, 0x73, 0xf9, 0x69, 0x58, 0xce, 0xe3, 0x4d, 0x59, 0x0a, 0x33, 0x5d, ++ 0x85, 0xeb, 0x4e, 0x0b, 0xd8, 0x11, 0x8e, 0x89, 0xfb, 0x30, 0xf3, 0x70, ++ 0xcf, 0x7c, 0x24, 0x36, 0x15, 0x2f, 0x89, 0xfb, 0x32, 0x53, 0x61, 0x5d, ++ 0xb2, 0x73, 0xf8, 0xfe, 0xcc, 0x74, 0xbb, 0xaa, 0x8a, 0xa6, 0x8c, 0xb0, ++ 0x4f, 0x13, 0xf6, 0x41, 0xe6, 0x91, 0xa1, 0xef, 0x61, 0xff, 0x89, 0xfb, ++ 0x75, 0x87, 0xe5, 0x68, 0x29, 0xc2, 0xe5, 0xff, 0x02, 0x9f, 0x8b, 0xfa, ++ 0xf4, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xd5, 0x7d, 0x0b, 0x7c, 0x94, 0xc5, ++ 0xd5, 0xf7, 0x3c, 0x7b, 0xcb, 0x26, 0xd9, 0x24, 0x9b, 0x04, 0x42, 0x42, ++ 0x48, 0xd8, 0xcd, 0x8d, 0x40, 0x2e, 0x6c, 0xc2, 0xc5, 0x88, 0xa8, 0x4b, ++ 0x48, 0x10, 0x2d, 0xe2, 0x22, 0x72, 0x35, 0xe2, 0x13, 0x12, 0x20, 0x40, ++ 0x02, 0x01, 0xf4, 0x6b, 0x6c, 0xa9, 0x59, 0x0c, 0x37, 0x2d, 0xd6, 0xf0, ++ 0x36, 0x0a, 0x5a, 0xd4, 0x8d, 0x05, 0x8a, 0x8a, 0x36, 0x28, 0x20, 0x56, ++ 0x6c, 0x97, 0x8b, 0x8a, 0xd5, 0x6a, 0x5a, 0xf5, 0x2d, 0x55, 0x4b, 0x13, ++ 0xa1, 0x8a, 0x72, 0x8b, 0xa1, 0x7d, 0x3f, 0xda, 0xfa, 0xb6, 0xdf, 0xfc, ++ 0xcf, 0xcc, 0x24, 0xfb, 0x2c, 0x89, 0xd2, 0x7e, 0x6f, 0x7f, 0xbf, 0xef, ++ 0x4b, 0x7f, 0x75, 0x98, 0xe7, 0x99, 0x67, 0xe6, 0xcc, 0x39, 0x67, 0xce, ++ 0x9c, 0xdb, 0xcc, 0x32, 0x66, 0x63, 0x2e, 0x3b, 0xa3, 0xbf, 0x7f, 0x98, ++ 0xf1, 0xdf, 0xaf, 0xaf, 0xaf, 0xd5, 0x3a, 0xee, 0x1f, 0x36, 0x9a, 0x31, ++ 0x7f, 0x8a, 0xc5, 0xb3, 0xc3, 0xc5, 0x58, 0x5a, 0xe8, 0x7b, 0x37, 0xfe, ++ 0xfb, 0xf7, 0x08, 0xd4, 0x35, 0x66, 0x72, 0xfd, 0x23, 0x93, 0xb1, 0x51, ++ 0xae, 0x78, 0xc6, 0x06, 0xe2, 0x79, 0xbd, 0xcb, 0x57, 0xc0, 0xd8, 0x1e, ++ 0x9b, 0x73, 0xa2, 0x63, 0x00, 0x63, 0x5d, 0x2b, 0x98, 0xe7, 0x29, 0xfe, ++ 0x7d, 0xe9, 0x4b, 0x9b, 0xe6, 0xbe, 0xc5, 0xeb, 0xff, 0x95, 0xe6, 0x70, ++ 0x46, 0xf0, 0x56, 0xa9, 0xc7, 0x9a, 0xdb, 0xf3, 0xf9, 0x73, 0x76, 0x40, ++ 0x1f, 0x86, 0xf6, 0xdb, 0x2c, 0xfa, 0x93, 0xd1, 0xfc, 0xfd, 0xb6, 0xe3, ++ 0x83, 0x98, 0x5f, 0x63, 0x2c, 0x22, 0x9a, 0xd5, 0xb7, 0x39, 0x38, 0x54, ++ 0x26, 0xa6, 0xa3, 0xfc, 0x07, 0xfe, 0xae, 0xc7, 0x38, 0x56, 0x1a, 0x67, ++ 0x94, 0xcb, 0xc4, 0xd8, 0x18, 0xc6, 0x78, 0x17, 0x01, 0x53, 0xf2, 0xbf, ++ 0x5e, 0xb6, 0x0d, 0x19, 0x92, 0xe7, 0xf4, 0xf0, 0xfe, 0x02, 0x29, 0xed, ++ 0x76, 0xde, 0x6f, 0x9b, 0xc5, 0x99, 0x67, 0xe1, 0xf5, 0x9c, 0xa1, 0xcd, ++ 0x0f, 0x59, 0xaf, 0xc5, 0x3c, 0x38, 0x8c, 0xe3, 0x68, 0xda, 0x5e, 0x56, ++ 0xc2, 0xd8, 0xb3, 0x47, 0xf9, 0xb8, 0x83, 0x51, 0x7d, 0xe4, 0xa1, 0x32, ++ 0x0b, 0x7f, 0x1f, 0xd5, 0xf3, 0xde, 0x8f, 0xf7, 0x7b, 0x4c, 0x26, 0x59, ++ 0x7f, 0xf4, 0xa1, 0xb2, 0x21, 0x8c, 0x0d, 0x39, 0xda, 0xb6, 0xc6, 0xe1, ++ 0xe4, 0xf3, 0x1f, 0xda, 0xfa, 0x90, 0x9d, 0xe3, 0x2d, 0xf2, 0x57, 0xe2, ++ 0xfd, 0x04, 0x5e, 0xf7, 0x67, 0x01, 0x2f, 0xb5, 0x43, 0x3b, 0xf8, 0xfc, ++ 0x0e, 0xa7, 0x2f, 0xa1, 0xf9, 0x37, 0xfd, 0x2e, 0x82, 0x45, 0xf0, 0x76, ++ 0x05, 0x66, 0xcf, 0x56, 0xd4, 0xd9, 0x47, 0x91, 0x6c, 0x07, 0xaf, 0xef, ++ 0xda, 0x37, 0x7e, 0xb6, 0x8b, 0xb7, 0x6b, 0x8a, 0x19, 0xeb, 0xd2, 0xf3, ++ 0x19, 0x2b, 0x73, 0x69, 0x34, 0xff, 0x52, 0x59, 0x86, 0xcf, 0xcb, 0x6c, ++ 0xf3, 0xe8, 0x1e, 0xc7, 0xe5, 0xcf, 0xc7, 0x4b, 0xbc, 0x31, 0xe6, 0x39, ++ 0xde, 0xca, 0xe9, 0x5b, 0xf0, 0x63, 0x1b, 0x7b, 0x80, 0xbf, 0xcc, 0x05, ++ 0xdc, 0xa0, 0x57, 0x6b, 0x64, 0xe0, 0x29, 0xd0, 0xb7, 0x79, 0x0b, 0x63, ++ 0x49, 0x8c, 0x55, 0x3b, 0x05, 0xcd, 0xab, 0xf7, 0x3f, 0x90, 0x7e, 0x88, ++ 0x97, 0x2f, 0xc7, 0x4c, 0xbb, 0xcd, 0xc5, 0xf1, 0x54, 0x1d, 0x53, 0x96, ++ 0x04, 0x78, 0x52, 0x2f, 0x31, 0xa6, 0x27, 0x72, 0xba, 0x35, 0xda, 0x99, ++ 0xce, 0x71, 0x95, 0x3a, 0xe0, 0x05, 0x8d, 0x71, 0xf8, 0x86, 0x0c, 0x38, ++ 0x3a, 0x81, 0x39, 0xc0, 0x37, 0xed, 0x6b, 0x9c, 0x28, 0xeb, 0xa3, 0x98, ++ 0xae, 0xf8, 0x07, 0xf4, 0xbf, 0x64, 0x61, 0xfa, 0x28, 0xf4, 0xe7, 0xa5, ++ 0xfe, 0xf0, 0x67, 0x4f, 0x02, 0x17, 0x8a, 0xbf, 0xb5, 0x09, 0x3a, 0x5b, ++ 0xc3, 0xe1, 0xf1, 0x73, 0x5c, 0xef, 0x00, 0x77, 0x3a, 0xa3, 0x3a, 0xb5, ++ 0x42, 0xfe, 0x8f, 0xe4, 0x32, 0x6f, 0x47, 0xae, 0xec, 0x27, 0x03, 0x7c, ++ 0xca, 0x66, 0xb7, 0xf1, 0xf1, 0x2a, 0x81, 0x07, 0xde, 0x8f, 0x8d, 0xd3, ++ 0xc4, 0x5a, 0xcc, 0x4b, 0x87, 0x25, 0x18, 0xd1, 0x47, 0xfb, 0x85, 0x12, ++ 0x5f, 0x66, 0xbb, 0x23, 0x68, 0x1e, 0xc9, 0x4b, 0xe7, 0xeb, 0xc7, 0xa9, ++ 0x5f, 0x87, 0xe5, 0x6c, 0x87, 0xbd, 0xb7, 0x9d, 0x3d, 0x60, 0x21, 0x7c, ++ 0xb0, 0x5a, 0x16, 0xc8, 0xd6, 0x08, 0x4f, 0xfe, 0x08, 0xd4, 0xe3, 0x12, ++ 0xa8, 0xce, 0xbc, 0x5e, 0xd7, 0x80, 0x24, 0xf0, 0x3f, 0x23, 0xe4, 0xa6, ++ 0x5a, 0xd8, 0xd1, 0x08, 0x3e, 0x2e, 0x71, 0x2f, 0x5f, 0x3f, 0x29, 0x2c, ++ 0x48, 0xe5, 0xe3, 0x1c, 0x3d, 0x8e, 0x4c, 0x34, 0x4a, 0x8b, 0xff, 0x34, ++ 0x9a, 0xe1, 0x11, 0x03, 0x1f, 0x3f, 0xc5, 0xd8, 0xe4, 0x50, 0xbe, 0x56, ++ 0xe5, 0xc5, 0x74, 0x13, 0xcd, 0x23, 0xab, 0xc1, 0x34, 0xf0, 0x14, 0xc7, ++ 0x4f, 0xde, 0x91, 0x48, 0x82, 0xc3, 0xb2, 0x91, 0x05, 0x22, 0xf9, 0x60, ++ 0x59, 0xa0, 0x07, 0xa7, 0x5b, 0xd6, 0x26, 0x16, 0xb0, 0xb8, 0xd1, 0xce, ++ 0x36, 0xf0, 0x54, 0x22, 0xbe, 0x73, 0xd1, 0x77, 0x2e, 0xe6, 0x34, 0x31, ++ 0x1a, 0xaf, 0x6d, 0x04, 0xd6, 0xd5, 0xd6, 0xd7, 0x1d, 0x9b, 0x58, 0x1c, ++ 0xd1, 0xf7, 0x4e, 0x1f, 0x1f, 0x6f, 0x6b, 0x14, 0xab, 0x01, 0xbe, 0xd4, ++ 0x78, 0x8c, 0xad, 0x21, 0x7c, 0x6c, 0x76, 0x89, 0x71, 0xb7, 0x35, 0x3a, ++ 0x89, 0x8e, 0xea, 0xfd, 0x90, 0xda, 0xc3, 0x61, 0x74, 0x4c, 0x30, 0xd0, ++ 0x51, 0xb5, 0x4b, 0xbd, 0x34, 0x98, 0xe8, 0xd9, 0xdb, 0x6f, 0x80, 0xfa, ++ 0x4d, 0x6d, 0xd8, 0x4b, 0xfc, 0x90, 0x7a, 0x29, 0x5d, 0xf2, 0x89, 0xeb, ++ 0x1b, 0xfa, 0xcf, 0xe8, 0xa7, 0xff, 0x64, 0xfa, 0xbe, 0xff, 0xfe, 0x87, ++ 0xd0, 0xf8, 0x8f, 0x07, 0xdf, 0x8f, 0x9f, 0xca, 0x51, 0xf1, 0xa3, 0xae, ++ 0xbd, 0xf1, 0x3e, 0x5e, 0x46, 0x5a, 0x9b, 0x7d, 0x9e, 0x3e, 0xf0, 0x9c, ++ 0x7a, 0x57, 0x88, 0x3c, 0xe3, 0xff, 0x1f, 0x79, 0x80, 0xd7, 0x73, 0x7b, ++ 0xeb, 0x0a, 0x2f, 0x91, 0x56, 0xef, 0x80, 0x69, 0x1c, 0xff, 0x91, 0x77, ++ 0x9b, 0x3c, 0xad, 0xbc, 0xbf, 0xab, 0x8e, 0x1b, 0xdb, 0x4d, 0x76, 0x7f, ++ 0x10, 0x8f, 0xf5, 0xd8, 0xdb, 0x3e, 0x38, 0x60, 0x3a, 0xda, 0xd7, 0x89, ++ 0xf6, 0xd7, 0x9c, 0x36, 0xb6, 0xf7, 0x4d, 0xd8, 0x17, 0xd6, 0x5e, 0xc0, ++ 0x77, 0xfd, 0x25, 0x63, 0xbb, 0x70, 0xfa, 0x84, 0xc3, 0xcb, 0xe1, 0x1a, ++ 0x38, 0x23, 0x04, 0xae, 0x89, 0xf6, 0x08, 0xc3, 0xf7, 0xb3, 0x2b, 0x2f, ++ 0x83, 0x6b, 0xe0, 0xac, 0x10, 0xb8, 0x6e, 0x48, 0x36, 0xb6, 0xd7, 0xd7, ++ 0xf4, 0x0d, 0xd7, 0xb7, 0x72, 0x23, 0xbe, 0x16, 0x2e, 0xd5, 0xee, 0x96, ++ 0x92, 0x2b, 0x6b, 0x17, 0x3e, 0x8f, 0xe9, 0x93, 0x23, 0xfa, 0xc1, 0xbb, ++ 0x68, 0x3f, 0x6b, 0xf6, 0x95, 0xf5, 0x7b, 0x7b, 0xcd, 0xd7, 0xb7, 0xbb, ++ 0xb3, 0x21, 0x7c, 0x1c, 0xbf, 0xdc, 0xaf, 0xf8, 0xda, 0xe2, 0xeb, 0x38, ++ 0x11, 0xff, 0xe0, 0x4b, 0x20, 0xb1, 0xc1, 0xe4, 0x8d, 0x8c, 0x65, 0xcc, ++ 0xc9, 0xba, 0x18, 0xd6, 0xd1, 0xc9, 0xa1, 0x2e, 0x6a, 0x97, 0xc0, 0x9c, ++ 0xb4, 0x9e, 0xf9, 0xc2, 0xd7, 0xb0, 0xae, 0xde, 0xc3, 0x3f, 0x53, 0xf8, ++ 0x56, 0xe0, 0xf6, 0x9d, 0x73, 0x8d, 0x01, 0xfe, 0xbd, 0x15, 0x0f, 0xf3, ++ 0xa6, 0x65, 0x72, 0xbf, 0x62, 0x53, 0x78, 0x8f, 0x57, 0xa3, 0x73, 0x5f, ++ 0xc1, 0xad, 0x05, 0x97, 0xf3, 0x1f, 0x63, 0xf7, 0x11, 0x5c, 0xaf, 0x68, ++ 0xba, 0xce, 0x68, 0x9f, 0xb5, 0x7b, 0x76, 0xf0, 0xf5, 0x9d, 0x97, 0xca, ++ 0xec, 0x29, 0x09, 0xfc, 0x75, 0x72, 0x20, 0xe3, 0xd6, 0x18, 0xc6, 0xbe, ++ 0xea, 0x91, 0xd7, 0x5c, 0xd4, 0x70, 0x38, 0x47, 0x48, 0xdc, 0x3d, 0x37, ++ 0xb8, 0x6d, 0x65, 0x3c, 0xad, 0xf3, 0x40, 0x02, 0xe0, 0xf9, 0x67, 0xc7, ++ 0xb5, 0xbb, 0xbd, 0x66, 0xf7, 0x98, 0xde, 0xf6, 0xe1, 0xed, 0x7a, 0xdb, ++ 0x0b, 0x3c, 0xd9, 0x6c, 0x6d, 0x2b, 0x00, 0x67, 0x57, 0x9d, 0xc3, 0x83, ++ 0xfd, 0xe1, 0x7d, 0xbc, 0xe2, 0xdf, 0xfd, 0x78, 0x66, 0x44, 0xd0, 0xcc, ++ 0xf1, 0x75, 0xc1, 0xea, 0xd8, 0xa8, 0x71, 0x39, 0x73, 0x3c, 0x7a, 0xde, ++ 0xeb, 0x03, 0x39, 0x1e, 0xde, 0x8b, 0xd5, 0xe3, 0xd1, 0xff, 0xec, 0x59, ++ 0x37, 0xae, 0x47, 0x5d, 0x3b, 0x9c, 0xe8, 0x5a, 0xc9, 0xe1, 0xbb, 0x50, ++ 0xd9, 0x31, 0x16, 0x78, 0xf5, 0x46, 0xeb, 0x03, 0xdd, 0xbc, 0xdf, 0x5a, ++ 0xbb, 0x3e, 0x34, 0x89, 0x4f, 0xf1, 0x5c, 0x9a, 0x3e, 0x2c, 0x0e, 0xf8, ++ 0xf5, 0x25, 0x12, 0x5e, 0xf9, 0x3f, 0x0a, 0x7c, 0x7d, 0xc2, 0x2f, 0xe0, ++ 0x29, 0xd3, 0x04, 0xfe, 0x13, 0xe3, 0xf4, 0x74, 0xf4, 0x53, 0x66, 0x6a, ++ 0x7f, 0xc2, 0x87, 0x67, 0x96, 0xf6, 0xb1, 0xf8, 0x8e, 0x39, 0x07, 0x12, ++ 0x7c, 0xe7, 0x6c, 0x5c, 0xde, 0xf5, 0xb1, 0xfe, 0x15, 0x1e, 0x4a, 0x65, ++ 0x3f, 0x87, 0xac, 0x9e, 0xaf, 0xba, 0xf8, 0xfc, 0x0e, 0x6d, 0x8e, 0xf3, ++ 0x34, 0x71, 0x78, 0xab, 0x13, 0x67, 0xcd, 0x5b, 0xce, 0x5f, 0x2d, 0x30, ++ 0xf9, 0x92, 0x82, 0x66, 0x03, 0xdc, 0xf9, 0x04, 0xb7, 0xa3, 0x72, 0x68, ++ 0x0a, 0xe0, 0xb6, 0x4a, 0xb8, 0xed, 0x03, 0x25, 0xde, 0xbd, 0x59, 0x5f, ++ 0x07, 0x77, 0x13, 0xc6, 0xc3, 0xbe, 0xf6, 0x3d, 0x2d, 0xb0, 0xc3, 0x2d, ++ 0x68, 0x89, 0xfa, 0x4b, 0xfe, 0xf8, 0xc0, 0x03, 0xbc, 0x1e, 0x61, 0xba, ++ 0xf8, 0x3e, 0xe4, 0x47, 0x57, 0x81, 0xc9, 0xc3, 0xf7, 0x08, 0xb6, 0x8d, ++ 0xeb, 0x17, 0x76, 0xbe, 0xaf, 0xbc, 0x2b, 0xf1, 0xfd, 0x38, 0x57, 0x7f, ++ 0xec, 0x09, 0xf4, 0x7c, 0x23, 0x9e, 0x27, 0x47, 0x89, 0xef, 0x93, 0x1f, ++ 0x31, 0x05, 0x9a, 0xf8, 0xf7, 0xbe, 0xd2, 0x97, 0x89, 0x4e, 0x3f, 0x5e, ++ 0xe6, 0xf0, 0x98, 0xf9, 0x58, 0x95, 0xcc, 0x65, 0x03, 0xdf, 0x56, 0x31, ++ 0xaf, 0x0d, 0xf0, 0xff, 0x71, 0xc2, 0xdf, 0x5e, 0xed, 0xe0, 0xf3, 0xbb, ++ 0xc9, 0xad, 0x97, 0x83, 0x3e, 0x77, 0x26, 0x9a, 0xd2, 0xdf, 0x27, 0x38, ++ 0xf4, 0xbc, 0x69, 0x9c, 0xdf, 0xd8, 0x78, 0x81, 0xff, 0x6f, 0xe2, 0x07, ++ 0xc6, 0x36, 0x99, 0xd8, 0x58, 0xc6, 0x6e, 0x95, 0xfa, 0xc1, 0x02, 0x89, ++ 0xc7, 0xe9, 0xcc, 0x6b, 0xc5, 0x38, 0x33, 0x98, 0x6e, 0xc5, 0xb8, 0xbf, ++ 0x39, 0x6f, 0xf3, 0x32, 0xce, 0x1f, 0xbf, 0xe1, 0xb8, 0x62, 0x1c, 0xde, ++ 0x59, 0xcc, 0x4f, 0xcf, 0xe7, 0xb0, 0x00, 0x95, 0xb7, 0xb3, 0x20, 0xb5, ++ 0xbf, 0x83, 0x75, 0x50, 0xfd, 0xd7, 0xd1, 0x85, 0x69, 0x0d, 0x1c, 0xbe, ++ 0x69, 0x5b, 0x86, 0x65, 0x63, 0x3d, 0x86, 0xe0, 0xfd, 0x76, 0xc9, 0x2f, ++ 0x77, 0x0e, 0x10, 0xfc, 0xf2, 0xd9, 0x20, 0xe0, 0xbd, 0x65, 0xe0, 0x15, ++ 0xf1, 0xef, 0x34, 0x4d, 0xe0, 0x6f, 0xb0, 0x5b, 0xaf, 0x76, 0xd3, 0x7a, ++ 0x75, 0x0d, 0xf0, 0x00, 0x26, 0xe7, 0xc4, 0x21, 0xbe, 0x98, 0x90, 0xf5, ++ 0x53, 0x36, 0x50, 0xf0, 0x9f, 0xc5, 0x99, 0xfd, 0x75, 0xeb, 0xa7, 0xbd, ++ 0x3b, 0xb6, 0x90, 0x8d, 0x24, 0x79, 0xe0, 0x48, 0xe1, 0x78, 0xb8, 0x41, ++ 0x92, 0xf2, 0x06, 0xef, 0xd2, 0x29, 0x98, 0x2f, 0x24, 0x08, 0xd6, 0xeb, ++ 0x2d, 0x72, 0xbd, 0x96, 0x9b, 0x1d, 0x6c, 0x00, 0xa7, 0x4b, 0xbb, 0xcb, ++ 0x1c, 0x88, 0xe0, 0xb0, 0x4c, 0x9e, 0xb0, 0x22, 0x19, 0xf3, 0x7d, 0x63, ++ 0x0d, 0xfb, 0xd5, 0x28, 0x4e, 0xbf, 0x37, 0x26, 0x98, 0x59, 0x13, 0xb5, ++ 0xf4, 0xd2, 0x77, 0x53, 0x65, 0x7f, 0x53, 0x87, 0x4c, 0xfa, 0x1c, 0xfa, ++ 0xc9, 0xdb, 0x2c, 0x38, 0x60, 0x34, 0xff, 0xae, 0xfc, 0x92, 0x7e, 0x34, ++ 0x8e, 0xe3, 0x67, 0xaa, 0x79, 0xf7, 0x5a, 0xae, 0x71, 0xb3, 0xc9, 0x43, ++ 0xac, 0x9f, 0x74, 0x84, 0xc8, 0xb5, 0x1b, 0x07, 0xec, 0xb1, 0x30, 0xae, ++ 0xbf, 0xdc, 0x94, 0x65, 0x7c, 0x3e, 0x25, 0x9f, 0xd7, 0x43, 0xe4, 0xee, ++ 0x54, 0x66, 0xe9, 0x7d, 0xcf, 0xe9, 0x7f, 0x08, 0xf8, 0x81, 0xdc, 0x61, ++ 0xcd, 0x66, 0xf0, 0xef, 0x46, 0x77, 0xcc, 0x80, 0x4f, 0xf3, 0x78, 0x75, ++ 0x04, 0x1b, 0x21, 0xec, 0x03, 0x4e, 0x8d, 0x90, 0xf9, 0x74, 0xdb, 0xff, ++ 0x6e, 0xbb, 0xc0, 0xbf, 0x7b, 0xc5, 0xad, 0x3f, 0x04, 0xba, 0xac, 0x8c, ++ 0x3f, 0x3f, 0x8f, 0xf4, 0x0e, 0x8b, 0x98, 0xcf, 0xb2, 0x77, 0xcc, 0xa4, ++ 0x57, 0x7e, 0xd2, 0xc8, 0xc0, 0x79, 0xec, 0x14, 0xd7, 0x0f, 0xbd, 0x39, ++ 0x8c, 0x7d, 0xca, 0xf5, 0x0b, 0xd4, 0x4f, 0x37, 0x26, 0x53, 0xf9, 0x05, ++ 0xd7, 0x07, 0x50, 0x9e, 0x6d, 0xcc, 0xa5, 0xf7, 0xe7, 0x1b, 0x3d, 0x54, ++ 0xff, 0xc4, 0xed, 0xdb, 0x8a, 0x7e, 0xe7, 0x6f, 0xfc, 0xd2, 0x82, 0x7d, ++ 0x69, 0x43, 0xa4, 0xc2, 0xb7, 0x80, 0x63, 0x95, 0xe4, 0xbb, 0x0d, 0x69, ++ 0x63, 0xb7, 0xfc, 0x95, 0xe3, 0x75, 0xc3, 0xdb, 0x7c, 0x61, 0x70, 0x78, ++ 0x6a, 0xda, 0x9a, 0x27, 0x71, 0x35, 0x8b, 0xad, 0x4a, 0xfb, 0xe4, 0x3e, ++ 0xe8, 0xcf, 0xab, 0x9e, 0xd6, 0x3c, 0x68, 0xb7, 0xf4, 0xa0, 0xd7, 0xe6, ++ 0xe0, 0xf0, 0x2c, 0x38, 0xaa, 0xaf, 0x07, 0x99, 0x17, 0xbd, 0xdd, 0x31, ++ 0x15, 0x62, 0xa2, 0x0e, 0xfa, 0x2b, 0xd7, 0x1b, 0xee, 0xb7, 0xfa, 0x76, ++ 0x62, 0xbc, 0x31, 0x1f, 0x9c, 0x4a, 0xd2, 0x79, 0x03, 0xef, 0xc1, 0xce, ++ 0xd7, 0x13, 0x79, 0xfb, 0xcf, 0x1a, 0x4b, 0x08, 0xae, 0xcf, 0x1b, 0xbd, ++ 0x04, 0xd7, 0x99, 0xc6, 0xc9, 0x54, 0xfe, 0xcd, 0xed, 0xdb, 0x8d, 0xf6, ++ 0x5e, 0xf6, 0xa5, 0x0d, 0xed, 0x6f, 0xde, 0xdd, 0x69, 0x49, 0xe5, 0xed, ++ 0xcb, 0xbd, 0x9a, 0x17, 0xeb, 0xf1, 0x3a, 0x2f, 0x0b, 0x04, 0x38, 0x3c, ++ 0x5b, 0xad, 0x42, 0xbe, 0x6f, 0xe5, 0xf2, 0x1d, 0xeb, 0x73, 0x42, 0xc1, ++ 0xad, 0x8f, 0xdf, 0x05, 0x71, 0xe1, 0xd6, 0xf7, 0x83, 0x0f, 0x67, 0x24, ++ 0x54, 0x95, 0x27, 0xf2, 0xe7, 0x53, 0x4b, 0x2a, 0x2d, 0x68, 0x37, 0xeb, ++ 0x2b, 0x2e, 0xd3, 0xdc, 0xbd, 0x7c, 0xf8, 0xcd, 0xeb, 0x50, 0xe0, 0xa3, ++ 0x4e, 0xd2, 0xe5, 0xdc, 0xcf, 0x35, 0xc2, 0xd3, 0xb9, 0xfd, 0x79, 0xb7, ++ 0x5c, 0xc3, 0xfb, 0xfb, 0xf9, 0x31, 0x33, 0x33, 0x73, 0xb8, 0xba, 0x2f, ++ 0x99, 0x08, 0xae, 0xee, 0xe3, 0x51, 0x01, 0x28, 0xad, 0xaa, 0xdd, 0xca, ++ 0x7d, 0x66, 0xd2, 0x27, 0x57, 0xa6, 0xd9, 0x02, 0xc0, 0xdf, 0xca, 0x7d, ++ 0x79, 0x83, 0xa0, 0x4f, 0x9d, 0xe1, 0x74, 0x63, 0x39, 0xbd, 0xe3, 0x9d, ++ 0x79, 0xee, 0xdb, 0x2e, 0x3d, 0x44, 0x8e, 0x9e, 0x49, 0x68, 0xfb, 0xaf, ++ 0x0f, 0x21, 0xa7, 0x7e, 0x2f, 0xe4, 0x14, 0xd7, 0x37, 0x3f, 0x7d, 0x0c, ++ 0x72, 0x6c, 0xc8, 0x60, 0x0f, 0xe8, 0x7e, 0xde, 0xca, 0xf5, 0x72, 0x20, ++ 0x9a, 0xd5, 0x47, 0x63, 0x1f, 0x5b, 0x66, 0x93, 0xeb, 0x8b, 0xcb, 0x19, ++ 0xd4, 0xcf, 0x44, 0x31, 0xd2, 0x47, 0xc7, 0x3e, 0x9f, 0x5a, 0x8a, 0xf5, ++ 0x82, 0xf1, 0x5c, 0xb6, 0x5e, 0x39, 0x94, 0xf3, 0xfc, 0x96, 0x8c, 0xef, ++ 0xba, 0x7a, 0xc7, 0xdb, 0xd5, 0xb6, 0xe0, 0xc3, 0xc7, 0x78, 0xfd, 0x5c, ++ 0xc0, 0xe4, 0xb7, 0xf2, 0x7d, 0xe6, 0x1c, 0x6b, 0x3b, 0xff, 0x33, 0xc8, ++ 0xd1, 0xed, 0x0e, 0x0f, 0xec, 0x83, 0x0d, 0x1a, 0x87, 0x07, 0xfb, 0xe8, ++ 0x8e, 0xc1, 0x54, 0xcf, 0xd5, 0x2c, 0x51, 0x0d, 0xc4, 0xcf, 0x01, 0x5a, ++ 0xaf, 0xb9, 0x9a, 0xcb, 0xd2, 0xc0, 0xe5, 0x4f, 0xed, 0x0b, 0x8f, 0x0e, ++ 0x06, 0x3f, 0xbd, 0xc2, 0x71, 0x50, 0xc2, 0xdf, 0xbf, 0xb2, 0x39, 0x9a, ++ 0xe4, 0xd3, 0x2b, 0x56, 0xcf, 0x89, 0x06, 0xf4, 0xf7, 0xb8, 0xe8, 0xef, ++ 0x27, 0x3f, 0xb8, 0xe7, 0x93, 0x03, 0x28, 0x1f, 0xac, 0x2b, 0xbe, 0x87, ++ 0x97, 0x17, 0xdd, 0x09, 0xd4, 0x4f, 0xf5, 0x7f, 0x2c, 0x1e, 0x81, 0xef, ++ 0xf9, 0x3e, 0xcd, 0x52, 0x78, 0x7f, 0xcf, 0xbe, 0xa4, 0x05, 0x23, 0xf9, ++ 0xfa, 0x2c, 0x68, 0x39, 0x74, 0x5f, 0x0a, 0x87, 0x6f, 0xe4, 0xb6, 0x4e, ++ 0xd3, 0x60, 0x5e, 0x16, 0x6d, 0xd7, 0x9a, 0x50, 0xe6, 0xa5, 0xdd, 0x74, ++ 0xcc, 0xcc, 0xdf, 0xff, 0xc5, 0xed, 0x12, 0x76, 0xeb, 0x6e, 0xb7, 0x39, ++ 0x15, 0xcb, 0x6a, 0x70, 0xe0, 0xc3, 0xeb, 0x69, 0xff, 0x36, 0xee, 0xeb, ++ 0xf9, 0x2d, 0x5f, 0x96, 0xc2, 0xbc, 0x54, 0xfb, 0xfb, 0x08, 0xad, 0xed, ++ 0x8b, 0x56, 0xd8, 0xc3, 0xe9, 0xc7, 0x8b, 0x75, 0xc2, 0x5f, 0x33, 0xc1, ++ 0xb1, 0xef, 0xe0, 0xf4, 0xf7, 0x6e, 0x67, 0x98, 0x07, 0xd7, 0x1c, 0x00, ++ 0x77, 0xa5, 0xcd, 0x43, 0xfb, 0x49, 0xc0, 0xdf, 0x0a, 0x3a, 0x9f, 0xd3, ++ 0x73, 0x3d, 0x0f, 0x60, 0x4d, 0xfb, 0xfc, 0x8f, 0x82, 0xbe, 0xe7, 0xf4, ++ 0x24, 0x0f, 0xf6, 0x97, 0xfd, 0x26, 0x7f, 0xec, 0x38, 0xb4, 0x3f, 0x61, ++ 0xa1, 0x79, 0xbe, 0xb4, 0xfd, 0xd7, 0xb1, 0x56, 0x5e, 0x8f, 0xdb, 0x6b, ++ 0x65, 0x91, 0xfc, 0x7d, 0x5d, 0x51, 0xd7, 0x24, 0xb4, 0xaf, 0x4b, 0x73, ++ 0x91, 0x1d, 0x9e, 0xf6, 0xc4, 0x0d, 0x93, 0x81, 0x9f, 0x65, 0x7b, 0xf7, ++ 0xb5, 0x52, 0x3f, 0xb5, 0x76, 0x8f, 0x86, 0x75, 0xb6, 0xef, 0xe2, 0xeb, ++ 0xa9, 0xb0, 0x87, 0x6e, 0x64, 0x9e, 0x6c, 0xf0, 0xdd, 0x5e, 0x51, 0xff, ++ 0x7e, 0x99, 0xd7, 0x03, 0x7e, 0xab, 0x69, 0xfd, 0xb3, 0xa8, 0xb7, 0xfb, ++ 0xa8, 0xee, 0x33, 0xfb, 0xdd, 0x16, 0xb4, 0xaf, 0x12, 0x7a, 0xce, 0x16, ++ 0xb9, 0x8f, 0xb1, 0x8e, 0x42, 0x92, 0x77, 0xc4, 0xca, 0xae, 0x5e, 0x7a, ++ 0x7d, 0x9f, 0xbf, 0xc6, 0xfb, 0xad, 0x6e, 0x7f, 0x4a, 0xbd, 0xa3, 0x77, ++ 0xff, 0xe3, 0xfb, 0xd6, 0x90, 0x0c, 0xfe, 0x3e, 0xc5, 0x26, 0xbf, 0x77, ++ 0x4e, 0x4f, 0xf7, 0xfd, 0x13, 0xfb, 0x96, 0x4d, 0xee, 0x43, 0xaa, 0xbf, ++ 0x2d, 0x36, 0xe6, 0x8f, 0xe4, 0xfd, 0xa4, 0xf1, 0xe7, 0x1a, 0xf6, 0x55, ++ 0x9b, 0xd8, 0x6f, 0x77, 0x70, 0xf9, 0x02, 0x7e, 0x51, 0xfb, 0x2d, 0x1f, ++ 0x37, 0x1f, 0xe3, 0xf2, 0xef, 0xbd, 0x90, 0x93, 0xa9, 0x7c, 0x73, 0x2d, ++ 0xe2, 0xf3, 0x49, 0xdd, 0x12, 0x11, 0xa0, 0x3d, 0xfd, 0x0a, 0xc7, 0x57, ++ 0x7a, 0xd2, 0xf2, 0x28, 0x21, 0xcf, 0x94, 0xfe, 0x31, 0x3b, 0xb1, 0xe9, ++ 0xd5, 0x0e, 0x8e, 0xd7, 0x3f, 0xc5, 0xea, 0x25, 0x19, 0xbc, 0xdd, 0x02, ++ 0xb9, 0x5f, 0x33, 0x8b, 0x27, 0x19, 0xf3, 0x3b, 0x19, 0xeb, 0xbd, 0x3a, ++ 0x83, 0xf6, 0xbf, 0xae, 0x74, 0xcc, 0x81, 0xef, 0x87, 0xd7, 0xa2, 0xbe, ++ 0xcc, 0xcc, 0xf5, 0xa7, 0xcc, 0x10, 0xfd, 0xc9, 0x7e, 0x65, 0xfb, 0x61, ++ 0x44, 0x9c, 0x77, 0x22, 0xbe, 0xbf, 0xd2, 0xf6, 0xe3, 0xa3, 0xfa, 0x96, ++ 0xbf, 0xe3, 0xbb, 0x4b, 0x48, 0xfe, 0xbe, 0x2a, 0xe5, 0xef, 0xaa, 0x3f, ++ 0x9b, 0x58, 0x11, 0xaf, 0xaf, 0x7a, 0x38, 0x82, 0xe4, 0x09, 0xed, 0x69, ++ 0x7d, 0xe0, 0xe5, 0x55, 0xbe, 0xde, 0x75, 0x2e, 0x5f, 0x7e, 0x01, 0xbf, ++ 0x01, 0x2f, 0xaf, 0xfd, 0x53, 0x87, 0x99, 0xec, 0x8f, 0xa3, 0xa6, 0xda, ++ 0xd7, 0xf9, 0x7e, 0x4a, 0x43, 0x67, 0xe0, 0x3f, 0x5d, 0x4d, 0x71, 0xa3, ++ 0xa9, 0xee, 0x05, 0x99, 0xaf, 0xfb, 0x93, 0xa9, 0x4f, 0xfb, 0x50, 0x95, ++ 0x9c, 0x4e, 0x95, 0xa0, 0x93, 0xf7, 0x2b, 0xa3, 0xbf, 0xe1, 0xfa, 0xaf, ++ 0x9c, 0x36, 0xea, 0xdf, 0x91, 0x70, 0x45, 0xf3, 0x35, 0xf7, 0x33, 0x5f, ++ 0x73, 0xac, 0x98, 0xef, 0x41, 0xcc, 0x97, 0xd3, 0x6e, 0xd5, 0x97, 0xc5, ++ 0x24, 0x2f, 0x0f, 0x5e, 0xe1, 0x3c, 0xd3, 0x22, 0xbc, 0x2b, 0x01, 0x5f, ++ 0xf8, 0x3c, 0x38, 0xdc, 0x0d, 0xa0, 0x47, 0x38, 0xdc, 0x3d, 0xfc, 0xdd, ++ 0x75, 0x65, 0x70, 0xdf, 0xad, 0x31, 0xbf, 0x09, 0xeb, 0xec, 0x4b, 0x5b, ++ 0x00, 0xeb, 0xec, 0x20, 0x07, 0x13, 0xeb, 0xf6, 0xe0, 0xe2, 0xfc, 0x00, ++ 0xd6, 0xf3, 0x7e, 0x9b, 0xa8, 0xfb, 0x63, 0x6d, 0xa4, 0x7f, 0x1e, 0x8c, ++ 0x61, 0x7e, 0xc8, 0x8f, 0x83, 0xd3, 0x92, 0x02, 0x7e, 0xec, 0xe7, 0x68, ++ 0x0f, 0xf9, 0x30, 0x90, 0x89, 0xf7, 0x91, 0xf2, 0xfb, 0x39, 0x49, 0xf4, ++ 0xfd, 0xe0, 0x08, 0xce, 0xff, 0xbc, 0xce, 0x6e, 0x8f, 0x92, 0xfd, 0xd7, ++ 0xbf, 0x55, 0x80, 0xf7, 0x6b, 0x52, 0x3d, 0x1c, 0x02, 0xae, 0xdf, 0x06, ++ 0x36, 0x66, 0x90, 0x7e, 0x6b, 0x26, 0xbf, 0xe1, 0x71, 0x29, 0xaf, 0x5b, ++ 0xe2, 0x83, 0xb7, 0x9b, 0xf9, 0xf3, 0x96, 0x2f, 0x73, 0x18, 0xc6, 0x39, ++ 0xce, 0x82, 0xa9, 0xcb, 0xd1, 0xae, 0x26, 0x8a, 0xe4, 0x50, 0x4b, 0xbc, ++ 0x37, 0x25, 0x81, 0xe3, 0x71, 0xff, 0xdf, 0xcd, 0xb4, 0x2f, 0xb4, 0x14, ++ 0xf1, 0xba, 0x83, 0xe4, 0x34, 0xf9, 0x77, 0x5a, 0xa6, 0x79, 0x53, 0xe2, ++ 0x79, 0x7d, 0xae, 0xa4, 0x4b, 0x4b, 0x6b, 0x60, 0xc7, 0x23, 0xe8, 0x6f, ++ 0x5a, 0xae, 0xc7, 0xcf, 0xc7, 0x19, 0x6c, 0x66, 0xf5, 0xd4, 0xce, 0x2d, ++ 0xfa, 0xf9, 0xd0, 0x2a, 0xbe, 0xfb, 0x9d, 0xa4, 0x0b, 0x5f, 0xc7, 0xb4, ++ 0xce, 0x8f, 0x66, 0xcc, 0xdf, 0x03, 0xfc, 0xeb, 0x53, 0xa3, 0x2d, 0xf0, ++ 0x8b, 0x70, 0x8c, 0xa7, 0x68, 0x1c, 0xfe, 0xc7, 0xaa, 0xb3, 0x19, 0xc9, ++ 0x4b, 0xe9, 0xf7, 0x9a, 0x2d, 0x69, 0x30, 0xb7, 0x97, 0x0f, 0xbc, 0xf6, ++ 0xb1, 0xd0, 0x6b, 0xc5, 0xdf, 0x9c, 0x05, 0x3b, 0x22, 0x21, 0x8f, 0x67, ++ 0xd4, 0x44, 0x92, 0x5f, 0xea, 0x78, 0xcd, 0x7d, 0x31, 0x2e, 0x3e, 0xde, ++ 0x0c, 0xdd, 0x1c, 0x8c, 0x80, 0xfe, 0x77, 0x5b, 0xb9, 0xc1, 0xef, 0x74, ++ 0x34, 0xc3, 0x4b, 0xe3, 0x72, 0xc3, 0x42, 0xda, 0x09, 0xc1, 0x2a, 0xe0, ++ 0xf1, 0xe7, 0x5d, 0x76, 0x06, 0xb9, 0xdc, 0x1f, 0x3d, 0xeb, 0xda, 0x26, ++ 0x24, 0x9e, 0x0a, 0xe1, 0x87, 0x1a, 0x9b, 0x90, 0x1f, 0xa7, 0xa5, 0x3e, ++ 0xf4, 0x72, 0x8c, 0xfe, 0x0b, 0xf0, 0xcd, 0xf2, 0x03, 0x37, 0x26, 0x9e, ++ 0x0a, 0xd1, 0xf7, 0xaa, 0x17, 0x94, 0xe7, 0x40, 0x7f, 0x56, 0xe3, 0x7d, ++ 0x13, 0xdf, 0x34, 0x81, 0x4e, 0x23, 0x69, 0xbd, 0xfa, 0x4d, 0xe0, 0x8f, ++ 0xb6, 0x48, 0xa2, 0xff, 0xe4, 0x5b, 0xed, 0x44, 0xef, 0x6e, 0x87, 0xe9, ++ 0x29, 0xf8, 0x25, 0xef, 0x94, 0xf2, 0xaa, 0x09, 0x86, 0x30, 0x7f, 0xde, ++ 0xb4, 0x2f, 0x22, 0x70, 0x1f, 0x7f, 0xb6, 0x3c, 0x22, 0x38, 0x13, 0xf2, ++ 0x8a, 0xd3, 0xff, 0xe9, 0x9d, 0xa0, 0xeb, 0xab, 0x91, 0x44, 0xff, 0x5a, ++ 0x9b, 0xe0, 0xa7, 0xda, 0x9f, 0xe5, 0x11, 0x7f, 0xed, 0xb7, 0x79, 0xdd, ++ 0xeb, 0xd0, 0xff, 0xcf, 0x23, 0x88, 0xee, 0xb5, 0xb1, 0xae, 0x38, 0x7a, ++ 0xff, 0xcb, 0x44, 0x26, 0xf9, 0x8f, 0xf4, 0x86, 0xda, 0xa8, 0x60, 0x4e, ++ 0x3c, 0xc7, 0xe7, 0xc6, 0x68, 0xfd, 0x43, 0xe0, 0x8d, 0xf3, 0x1d, 0xf9, ++ 0x83, 0x6b, 0x6d, 0xe2, 0xf9, 0x09, 0xc9, 0x57, 0x27, 0x78, 0x1f, 0x80, ++ 0xc3, 0x5f, 0x1f, 0x43, 0xfc, 0xc8, 0x64, 0x5d, 0xff, 0x6e, 0x22, 0xd9, ++ 0x53, 0x5c, 0x1f, 0x25, 0xfe, 0xd5, 0x1f, 0xca, 0xa3, 0xba, 0x6e, 0xf3, ++ 0xa6, 0x2c, 0xc0, 0xfa, 0x58, 0x19, 0x4d, 0xf0, 0x9d, 0x90, 0xfe, 0xb4, ++ 0x13, 0xb5, 0xf1, 0xc4, 0xdf, 0x15, 0x0f, 0x2d, 0x7d, 0x9b, 0x71, 0x7a, ++ 0x9e, 0xf0, 0xed, 0xbc, 0x3f, 0x87, 0xb7, 0x3b, 0x71, 0xd0, 0xea, 0xc1, ++ 0xbe, 0xf4, 0x71, 0x83, 0x39, 0x68, 0xe3, 0x74, 0x3d, 0xbf, 0xfa, 0xe4, ++ 0xd8, 0xad, 0xbc, 0xde, 0x71, 0xdf, 0x47, 0xe9, 0x7a, 0x88, 0x1f, 0xad, ++ 0xe2, 0xbe, 0xba, 0x29, 0xf8, 0xae, 0x62, 0xc9, 0xea, 0xa9, 0xd8, 0x2f, ++ 0xfb, 0xc3, 0x77, 0x45, 0x6d, 0x04, 0x97, 0xb9, 0xbd, 0x74, 0xb2, 0x66, ++ 0x7a, 0xff, 0x04, 0xfa, 0xb9, 0x33, 0xf5, 0xff, 0x8d, 0x79, 0x2e, 0xcf, ++ 0xef, 0x58, 0x08, 0xb9, 0x77, 0xde, 0xd6, 0xfe, 0x04, 0xec, 0x83, 0x0f, ++ 0xe3, 0xf4, 0xbf, 0xe2, 0xfd, 0x85, 0x97, 0x3f, 0xdb, 0x49, 0xf2, 0xd0, ++ 0xd2, 0x95, 0x03, 0xfd, 0x7c, 0x99, 0x85, 0xf3, 0x01, 0xf8, 0x52, 0xee, ++ 0x9f, 0xcb, 0x25, 0x5f, 0x06, 0x32, 0x75, 0x96, 0x39, 0x86, 0xf0, 0x47, ++ 0xfa, 0x78, 0x74, 0x7e, 0xbb, 0x90, 0x7b, 0xab, 0xaf, 0x4c, 0xce, 0x7f, ++ 0x71, 0x70, 0xc7, 0x7e, 0x8d, 0x8f, 0xb3, 0x34, 0xea, 0xe0, 0x32, 0x2a, ++ 0xcd, 0x81, 0x42, 0xf4, 0x73, 0x46, 0x0b, 0xc6, 0x6a, 0x99, 0xc0, 0x1f, ++ 0xd7, 0xe3, 0x78, 0x7f, 0x67, 0x9d, 0xc1, 0x58, 0xd0, 0x41, 0x97, 0x76, ++ 0xd3, 0xd2, 0x5d, 0xc6, 0x79, 0xe1, 0x0f, 0x7e, 0x95, 0xa5, 0xf8, 0x07, ++ 0xff, 0x6e, 0x69, 0x9b, 0x99, 0xfc, 0x2a, 0x1c, 0x42, 0x1b, 0xe0, 0x5f, ++ 0x0a, 0x4f, 0xaf, 0x21, 0x9e, 0x20, 0xe4, 0x0a, 0xef, 0xe7, 0x29, 0x5a, ++ 0x87, 0x8e, 0x8f, 0xe7, 0x7d, 0x97, 0xe3, 0x7f, 0xc9, 0xd3, 0xc3, 0x8b, ++ 0xa1, 0x4f, 0x2e, 0x8d, 0x3f, 0xf0, 0x83, 0x6b, 0xa8, 0x1d, 0xff, 0x4e, ++ 0xf1, 0xb9, 0xf9, 0xf2, 0xba, 0x9a, 0xcf, 0xe5, 0xf0, 0x88, 0xf9, 0x9d, ++ 0x95, 0x7c, 0x7e, 0x96, 0x49, 0x39, 0x38, 0xdb, 0xd6, 0x63, 0x87, 0x43, ++ 0x0f, 0x3a, 0xff, 0xdc, 0x20, 0x03, 0xdf, 0x9c, 0x7f, 0x7a, 0x38, 0xd5, ++ 0xbf, 0xd0, 0xba, 0xb4, 0x28, 0x0e, 0xd7, 0x79, 0x29, 0x8f, 0x98, 0xa7, ++ 0x6d, 0xec, 0x34, 0x18, 0x10, 0xde, 0xb6, 0xb1, 0xd0, 0x67, 0x1f, 0x91, ++ 0xcf, 0x97, 0x26, 0xb6, 0x8d, 0x85, 0xfc, 0x51, 0xf2, 0x88, 0xd9, 0xdb, ++ 0x0a, 0xc9, 0xae, 0xce, 0x6d, 0x2b, 0x84, 0x3d, 0xa9, 0xe4, 0x19, 0xf3, ++ 0xb5, 0xe5, 0xd0, 0xf3, 0x40, 0x5b, 0x0e, 0xbe, 0xdf, 0x6f, 0x12, 0x7e, ++ 0x0a, 0xfa, 0xc3, 0xbc, 0x9f, 0x4d, 0x6d, 0x25, 0x3c, 0xd8, 0xc5, 0x7a, ++ 0x5c, 0xf2, 0x6c, 0x1e, 0xe1, 0x45, 0x8d, 0x13, 0x4e, 0xbf, 0xf0, 0xf9, ++ 0x5e, 0x9f, 0x29, 0xfc, 0xdc, 0x1c, 0xde, 0x3b, 0x7d, 0xbc, 0xfd, 0xb0, ++ 0xad, 0x36, 0xc3, 0xfb, 0xe1, 0x01, 0x63, 0xfd, 0x06, 0xd9, 0x7e, 0x68, ++ 0x18, 0x5d, 0x06, 0x9b, 0xbb, 0x0e, 0x45, 0x40, 0xde, 0xff, 0x98, 0xd1, ++ 0x7a, 0x0d, 0x1f, 0x77, 0xaa, 0xfc, 0xee, 0x99, 0x67, 0x7a, 0xe8, 0x60, ++ 0x96, 0xf6, 0x22, 0x73, 0x29, 0xfa, 0xbb, 0x84, 0xbe, 0x6d, 0x05, 0xbe, ++ 0x7f, 0xd7, 0x83, 0xef, 0xbb, 0x52, 0xb9, 0x3c, 0x5d, 0x8a, 0x39, 0x66, ++ 0xf4, 0xce, 0x7f, 0x7f, 0x91, 0x9e, 0x0a, 0xb9, 0x7f, 0xde, 0x24, 0xfc, ++ 0xd4, 0xfb, 0xe3, 0x79, 0x3d, 0x1f, 0x7a, 0x8e, 0xc0, 0xa7, 0xaa, 0x2b, ++ 0x3c, 0x86, 0xf3, 0xd1, 0x7d, 0xbf, 0x5b, 0x98, 0x8a, 0x78, 0xca, 0x3d, ++ 0x99, 0x26, 0xa9, 0x54, 0x7a, 0x06, 0x81, 0xdf, 0x9a, 0x20, 0x2f, 0xb9, ++ 0xbc, 0x68, 0xb2, 0x0a, 0x7c, 0x7c, 0xd1, 0x58, 0x33, 0xea, 0x94, 0x05, ++ 0xf6, 0x68, 0x7d, 0x4a, 0xb5, 0xa5, 0x77, 0x3e, 0x0b, 0xb7, 0x16, 0xd9, ++ 0xb1, 0x5e, 0x16, 0x6d, 0x2b, 0xb2, 0xcf, 0x0f, 0xb1, 0x77, 0x9a, 0x76, ++ 0x8d, 0x3a, 0xe6, 0xe2, 0x74, 0x39, 0xbb, 0xcb, 0x42, 0x6e, 0x83, 0x26, ++ 0x4b, 0xe0, 0x07, 0xd0, 0xa3, 0x9b, 0x76, 0x99, 0xdb, 0xfc, 0x8c, 0xde, ++ 0xdb, 0xbd, 0xbc, 0xfd, 0x59, 0xc7, 0xe1, 0x77, 0xd0, 0x6e, 0xe1, 0xb6, ++ 0xf8, 0x62, 0xe8, 0xbd, 0xea, 0xfb, 0x45, 0x5b, 0xef, 0x4e, 0xa9, 0x0e, ++ 0xc1, 0x77, 0xde, 0x2e, 0x23, 0xfe, 0x0b, 0xda, 0x8c, 0x75, 0xf8, 0xa3, ++ 0x43, 0xeb, 0x4d, 0xd0, 0x05, 0xc7, 0xfc, 0xf3, 0xdf, 0x15, 0x05, 0x8d, ++ 0xf5, 0x51, 0xc7, 0x8c, 0xf5, 0xcf, 0xde, 0xbf, 0x6b, 0x26, 0xd8, 0xf8, ++ 0xa5, 0x12, 0xc1, 0xef, 0xa7, 0x03, 0x31, 0x01, 0xc4, 0xa9, 0x6a, 0x3e, ++ 0x9a, 0x74, 0x0c, 0xfb, 0xda, 0xe9, 0xfd, 0x2f, 0xc5, 0x82, 0x3e, 0x4b, ++ 0x7f, 0x5f, 0xfd, 0x3a, 0xec, 0x96, 0x45, 0x5b, 0x8d, 0x7c, 0xc6, 0xe9, ++ 0xa6, 0x41, 0xaf, 0xf7, 0xef, 0xd4, 0x88, 0x3f, 0x16, 0x07, 0xc2, 0xd7, ++ 0x9d, 0x5c, 0xef, 0x97, 0xad, 0xc7, 0x35, 0xca, 0xaf, 0x99, 0x1b, 0xca, ++ 0x27, 0xe1, 0xf4, 0x3c, 0xc3, 0xda, 0x66, 0x7a, 0x39, 0x3f, 0xd5, 0x36, ++ 0xac, 0x1c, 0x85, 0x78, 0x48, 0xcd, 0x14, 0xce, 0xb8, 0x1c, 0x9e, 0xab, ++ 0xdb, 0x36, 0xdb, 0x10, 0x37, 0x08, 0x1f, 0xaf, 0xbf, 0x75, 0xcf, 0x1c, ++ 0x5e, 0x17, 0xfc, 0x55, 0x95, 0x25, 0xe2, 0xdd, 0xb8, 0x86, 0x52, 0x76, ++ 0x12, 0x4e, 0xdf, 0x4d, 0xbf, 0x9e, 0x84, 0xf5, 0x56, 0xf9, 0x7d, 0x8d, ++ 0xf6, 0xff, 0xca, 0x17, 0x87, 0x1d, 0x85, 0xfc, 0xee, 0xdc, 0x33, 0xe7, ++ 0x26, 0x2a, 0x67, 0x4e, 0x26, 0x3c, 0x28, 0xff, 0xd9, 0xa2, 0x83, 0x5a, ++ 0x30, 0x86, 0xd7, 0x9d, 0x25, 0xae, 0x03, 0x1d, 0xfc, 0xbb, 0x05, 0x01, ++ 0x8d, 0xf6, 0x87, 0xf9, 0x6b, 0x23, 0x7a, 0xe5, 0x10, 0xff, 0x7f, 0xf5, ++ 0xa6, 0x30, 0x38, 0x5a, 0x42, 0xde, 0x73, 0xf8, 0x17, 0x1d, 0x38, 0xf4, ++ 0x17, 0x8d, 0xf7, 0x5f, 0xb3, 0xcd, 0xf8, 0xdd, 0x62, 0x8e, 0x2f, 0xc8, ++ 0xfd, 0x25, 0xdb, 0xff, 0x11, 0x11, 0xfa, 0x5c, 0xd9, 0x7d, 0xe3, 0x0e, ++ 0xb6, 0x9a, 0x31, 0xef, 0x05, 0x0a, 0x7e, 0xff, 0x75, 0x0c, 0xf3, 0x12, ++ 0x21, 0x48, 0x2e, 0x3a, 0xa4, 0xbe, 0x72, 0x0a, 0x15, 0x2e, 0xef, 0xa3, ++ 0x13, 0x7c, 0x87, 0x32, 0xf9, 0xfc, 0xc7, 0xb5, 0x88, 0xef, 0xb8, 0xc0, ++ 0xaa, 0xc4, 0x7c, 0xeb, 0x1c, 0x36, 0x17, 0xe6, 0x5b, 0x67, 0x67, 0xc1, ++ 0x68, 0x0e, 0xc7, 0xb1, 0x18, 0x9b, 0xd7, 0xc9, 0x9f, 0x5f, 0xdc, 0x1a, ++ 0x43, 0xfe, 0xa9, 0x85, 0x11, 0x5c, 0x2f, 0x2c, 0xa6, 0x92, 0x45, 0x16, ++ 0xe3, 0x3b, 0x0f, 0xed, 0xd3, 0x9f, 0xbe, 0x6b, 0x26, 0x7d, 0xa5, 0x0e, ++ 0x63, 0xa3, 0x9f, 0x27, 0x35, 0xb2, 0x7f, 0xea, 0xe0, 0x6c, 0x44, 0xfd, ++ 0xc7, 0xa2, 0xbe, 0x98, 0x05, 0x69, 0x1e, 0xe0, 0x17, 0x6f, 0xe8, 0xfc, ++ 0x02, 0xc6, 0x3a, 0x6b, 0x16, 0x76, 0x53, 0xad, 0x25, 0x78, 0x08, 0xf8, ++ 0x58, 0xc2, 0x3a, 0x84, 0xdd, 0xc3, 0xe9, 0xe8, 0x0d, 0x89, 0xc7, 0xd5, ++ 0xf2, 0x79, 0x1e, 0x4f, 0x80, 0x3e, 0x64, 0xfc, 0x7e, 0x39, 0x6b, 0xa3, ++ 0xf6, 0xcb, 0x0f, 0xfc, 0x23, 0x22, 0xf4, 0x79, 0x88, 0x9f, 0x94, 0xec, ++ 0x39, 0x65, 0x57, 0x9a, 0x6d, 0xcc, 0x0b, 0xfd, 0xd8, 0x7c, 0x6f, 0x14, ++ 0xed, 0xf7, 0x5c, 0x10, 0x47, 0x81, 0x3f, 0xd7, 0x69, 0xde, 0x47, 0xed, ++ 0x66, 0x94, 0x62, 0x5e, 0xfe, 0xcd, 0x42, 0xff, 0x99, 0xdb, 0x2a, 0xf6, ++ 0x0b, 0xae, 0x9f, 0xe6, 0x00, 0x3f, 0x2d, 0x9b, 0x87, 0x7b, 0xa0, 0xa7, ++ 0xcc, 0xe5, 0x7a, 0x76, 0x24, 0xf4, 0x88, 0xc5, 0x51, 0xd4, 0xae, 0x25, ++ 0x9e, 0x91, 0x7f, 0xa5, 0x65, 0x4e, 0x8e, 0xd0, 0xb3, 0xff, 0xfe, 0x62, ++ 0x10, 0xe3, 0x74, 0x3d, 0xac, 0x91, 0x7f, 0xa4, 0xa5, 0x48, 0xf4, 0xdb, ++ 0xf2, 0xe0, 0x70, 0x7a, 0x0f, 0x79, 0xa8, 0xd1, 0x38, 0x11, 0xa4, 0xb7, ++ 0xb4, 0x4c, 0x53, 0xef, 0xd3, 0x48, 0x4f, 0xfa, 0x10, 0xa0, 0xa5, 0x40, ++ 0xcf, 0x95, 0xcf, 0x07, 0xba, 0xe8, 0xf9, 0x60, 0xb3, 0x37, 0x07, 0xfa, ++ 0x3a, 0xfb, 0x61, 0x24, 0xd9, 0xfb, 0x4a, 0xaf, 0xfd, 0x49, 0x82, 0xfe, ++ 0x0f, 0xec, 0xfb, 0x6a, 0xbe, 0x4a, 0x0f, 0x66, 0x35, 0x57, 0xa6, 0xff, ++ 0xed, 0x90, 0xfb, 0x5d, 0xd7, 0x66, 0x11, 0xff, 0x3d, 0xa5, 0xf9, 0x5e, ++ 0x37, 0x85, 0xe8, 0xa5, 0xce, 0x2c, 0x21, 0xe7, 0xc7, 0x96, 0x7a, 0x77, ++ 0xca, 0x76, 0x14, 0x07, 0xa8, 0x36, 0x4d, 0x7b, 0xe0, 0x7a, 0x0e, 0x4f, ++ 0xf5, 0x23, 0x26, 0x57, 0x93, 0xbb, 0x17, 0xef, 0xcc, 0xeb, 0xcd, 0xc1, ++ 0xfc, 0x4f, 0x6d, 0x8e, 0x2c, 0x06, 0x9f, 0x8d, 0x2d, 0x15, 0xfe, 0x9e, ++ 0x13, 0x45, 0x42, 0x6e, 0x47, 0x8f, 0x66, 0xde, 0x00, 0x2f, 0x53, 0x64, ++ 0xbf, 0x29, 0x59, 0x26, 0x43, 0x99, 0x1c, 0xc5, 0xf9, 0x8f, 0xf7, 0x73, ++ 0xaa, 0x5c, 0xf8, 0x87, 0x63, 0x46, 0xfb, 0xc8, 0xcf, 0xc6, 0x75, 0x36, ++ 0x92, 0xdf, 0xe1, 0xf3, 0xc8, 0x96, 0xfd, 0x54, 0xdb, 0x7c, 0xbf, 0xbc, ++ 0xb6, 0x0f, 0x78, 0x7a, 0xf8, 0xa0, 0x4c, 0xe8, 0x19, 0xa7, 0x56, 0x68, ++ 0x4f, 0x09, 0xb8, 0x38, 0x5d, 0x79, 0x7d, 0xec, 0x7f, 0x44, 0x92, 0x7f, ++ 0xee, 0x94, 0xdc, 0x57, 0x14, 0xfe, 0x39, 0xdf, 0x8c, 0xa1, 0x7d, 0x5a, ++ 0xc5, 0x49, 0x25, 0x9f, 0x6c, 0x06, 0xfd, 0xb1, 0x9f, 0x2d, 0x16, 0x76, ++ 0x50, 0x2f, 0x9f, 0x18, 0xf9, 0x60, 0xae, 0x26, 0xf0, 0xca, 0x1e, 0x14, ++ 0xfa, 0x69, 0x4b, 0xbc, 0xa8, 0x2b, 0x3e, 0xe0, 0xf6, 0x0e, 0xfb, 0x2b, ++ 0xf8, 0xa4, 0x9c, 0x11, 0xde, 0xfb, 0xb3, 0x7b, 0xd4, 0x3c, 0x5b, 0x5a, ++ 0xc5, 0x7b, 0x4e, 0xef, 0x6b, 0xb3, 0xc6, 0x5c, 0x6e, 0xf7, 0x28, 0x7a, ++ 0x33, 0x4b, 0x60, 0x0c, 0xec, 0xc6, 0xfe, 0xe8, 0x3d, 0xbf, 0x24, 0x7e, ++ 0xac, 0x66, 0xa2, 0xb8, 0xb5, 0x1f, 0x71, 0x6b, 0xec, 0x75, 0x84, 0x97, ++ 0xfb, 0x2d, 0x81, 0xfb, 0x38, 0x1c, 0x43, 0x2c, 0x02, 0xff, 0x69, 0x16, ++ 0xc1, 0x5f, 0x5c, 0x2a, 0xfb, 0xa3, 0x8a, 0xa9, 0xbd, 0xd7, 0xc6, 0xeb, ++ 0x95, 0x3f, 0x5c, 0xc4, 0xbc, 0xbc, 0x7d, 0x65, 0x2a, 0x23, 0x7f, 0x10, ++ 0x6f, 0xcf, 0xe2, 0xd0, 0x9e, 0x77, 0x63, 0x86, 0x7f, 0x84, 0x97, 0xf8, ++ 0xae, 0x32, 0x4e, 0xf4, 0x5b, 0x39, 0x88, 0x91, 0x9d, 0x40, 0x7f, 0x5c, ++ 0x5e, 0x65, 0xa1, 0xcc, 0xa0, 0x7e, 0xbd, 0xa6, 0x04, 0xf1, 0x7d, 0x6c, ++ 0x31, 0x7d, 0xef, 0x37, 0x89, 0xef, 0xbd, 0x16, 0x5e, 0x0e, 0xcd, 0x14, ++ 0xfa, 0x7c, 0xd7, 0xba, 0x88, 0xc0, 0x53, 0x90, 0xcf, 0x1b, 0xd2, 0x72, ++ 0xc0, 0x07, 0x53, 0x4a, 0x8d, 0x7c, 0xd0, 0x26, 0xf9, 0x46, 0x95, 0xa9, ++ 0xd9, 0x2e, 0x95, 0xe7, 0x90, 0x8c, 0xf5, 0x3d, 0x7f, 0xed, 0x70, 0xda, ++ 0x2f, 0x9a, 0x22, 0x7d, 0x75, 0xfb, 0x40, 0xb7, 0xe7, 0x84, 0xfe, 0x5f, ++ 0xb9, 0xfe, 0x8e, 0x9b, 0xc7, 0x00, 0xbe, 0xe7, 0x13, 0x3d, 0x00, 0xef, ++ 0x8b, 0xa9, 0x7b, 0x28, 0xde, 0x30, 0x7f, 0xed, 0x9c, 0xbb, 0x3f, 0x80, ++ 0xdd, 0xb0, 0x2b, 0x92, 0x9e, 0x97, 0x64, 0xeb, 0x4b, 0xb3, 0xa0, 0x1f, ++ 0x6b, 0xae, 0x79, 0xfb, 0xf8, 0x83, 0xf9, 0x33, 0x8e, 0xd8, 0x92, 0xf9, ++ 0xf7, 0x7a, 0xdb, 0xb4, 0x73, 0x3f, 0xe3, 0xe5, 0x54, 0xff, 0x9e, 0x77, ++ 0xa0, 0x0f, 0x4c, 0xbd, 0xcd, 0x4c, 0xed, 0xa7, 0x32, 0xe1, 0x1f, 0x65, ++ 0x6b, 0xc5, 0x38, 0x37, 0xfb, 0xbf, 0xb4, 0x24, 0xf3, 0xfe, 0x6e, 0x1e, ++ 0xaf, 0x51, 0xce, 0x40, 0x67, 0xa4, 0x33, 0x7d, 0x05, 0xf2, 0x16, 0x24, ++ 0xfd, 0xbe, 0x0d, 0xfe, 0x85, 0x1d, 0x16, 0xc9, 0x66, 0xbf, 0xe0, 0x00, ++ 0x5c, 0x69, 0x39, 0x19, 0xfc, 0xf9, 0xcd, 0xd0, 0x30, 0xfb, 0x88, 0x5f, ++ 0xed, 0x93, 0xfc, 0xde, 0x34, 0x41, 0xdb, 0x06, 0xbd, 0x66, 0xe8, 0x44, ++ 0xb1, 0xbe, 0x54, 0x7b, 0xf4, 0x83, 0x7e, 0x5f, 0xc9, 0x12, 0x7a, 0xd0, ++ 0x7d, 0xb2, 0x54, 0x75, 0x8e, 0x57, 0x6a, 0x5f, 0xbd, 0x31, 0xa2, 0x33, ++ 0x33, 0x16, 0xa5, 0x35, 0x38, 0x0c, 0xfb, 0x5d, 0x4e, 0xe9, 0x7a, 0xf0, ++ 0xd5, 0x94, 0x0c, 0x36, 0x69, 0x2b, 0xf0, 0x7e, 0x8f, 0x19, 0xb9, 0x0a, ++ 0x1c, 0xde, 0xae, 0x4a, 0x5a, 0xf7, 0x31, 0x39, 0x2e, 0xf0, 0xa9, 0xce, ++ 0x58, 0x90, 0xf2, 0x23, 0x02, 0xc3, 0x89, 0xaf, 0x3b, 0x27, 0x74, 0x75, ++ 0x6e, 0xe0, 0xf5, 0xce, 0xd6, 0x61, 0x1e, 0xf2, 0xf9, 0x48, 0x3b, 0x7a, ++ 0x01, 0xec, 0x2b, 0x17, 0xde, 0x0b, 0x39, 0xa6, 0xe4, 0xcb, 0x09, 0x67, ++ 0x47, 0x0c, 0xf1, 0xab, 0xb4, 0xab, 0xab, 0x24, 0x6b, 0xfc, 0xb1, 0x61, ++ 0xe2, 0x23, 0x57, 0xf1, 0xf6, 0x55, 0x0e, 0x5b, 0x27, 0xf6, 0x83, 0x05, ++ 0x0f, 0x4f, 0x8f, 0x45, 0x9e, 0x49, 0x55, 0x8b, 0x59, 0xe4, 0x73, 0x6c, ++ 0x32, 0xda, 0xd5, 0xdc, 0xfe, 0x0d, 0x00, 0xde, 0x70, 0x3b, 0x39, 0xdc, ++ 0x1e, 0x06, 0xcf, 0x80, 0x8f, 0xaa, 0x37, 0x69, 0xc4, 0x87, 0x43, 0x9b, ++ 0x3c, 0xb6, 0x14, 0x92, 0x63, 0x9a, 0x13, 0xf3, 0xab, 0x76, 0x04, 0xb3, ++ 0x20, 0xdf, 0xab, 0x3d, 0x91, 0x1e, 0xbc, 0x3f, 0xdb, 0xe8, 0x4d, 0x3c, ++ 0x95, 0x85, 0x78, 0xc4, 0x64, 0x2a, 0xd9, 0x57, 0x1c, 0xef, 0x63, 0xe1, ++ 0x8f, 0x65, 0x94, 0xc4, 0xf1, 0x62, 0xb6, 0xfe, 0x1c, 0xf8, 0xa1, 0xb2, ++ 0xb9, 0x92, 0xec, 0xc5, 0xe8, 0x7c, 0x9d, 0xe4, 0xd3, 0xd9, 0x2c, 0xc1, ++ 0x77, 0x53, 0xe0, 0x4f, 0x84, 0xbc, 0xb1, 0x74, 0xa4, 0x60, 0x1d, 0xce, ++ 0x53, 0xcf, 0x13, 0x9c, 0x39, 0x0e, 0xe2, 0xe7, 0x48, 0x06, 0x3c, 0x74, ++ 0x5a, 0x9d, 0x39, 0x80, 0xab, 0x73, 0x5d, 0xa4, 0x09, 0xfb, 0xe6, 0x94, ++ 0xfb, 0x04, 0x5f, 0xf3, 0x75, 0x66, 0xb7, 0xf0, 0xef, 0xef, 0xb7, 0xb0, ++ 0x28, 0xac, 0xf7, 0xef, 0xe2, 0x7b, 0x3e, 0x5e, 0xc5, 0x1a, 0x8b, 0xaf, ++ 0x95, 0xd7, 0x87, 0xd8, 0x99, 0x25, 0x26, 0x01, 0x7c, 0x55, 0x44, 0x7c, ++ 0x9d, 0x39, 0x4c, 0xbf, 0x0f, 0xf0, 0x9c, 0xfe, 0x1e, 0x2b, 0xc1, 0xfe, ++ 0x5f, 0xb5, 0x69, 0x33, 0xc1, 0xa3, 0xf8, 0x82, 0x59, 0xda, 0xcb, 0x12, ++ 0xa1, 0xdf, 0xed, 0x70, 0x17, 0x3f, 0xc0, 0x7a, 0xf9, 0x28, 0x73, 0x58, ++ 0xe9, 0x51, 0xe0, 0xaf, 0x87, 0x1f, 0x6e, 0xd3, 0x88, 0x0f, 0x78, 0x79, ++ 0x28, 0x93, 0xf8, 0xe1, 0xd6, 0x37, 0x89, 0x1f, 0x4a, 0x83, 0x59, 0x2b, ++ 0xf3, 0x11, 0xc7, 0xaa, 0x65, 0x5e, 0xc4, 0x11, 0x92, 0x99, 0x07, 0xfe, ++ 0x80, 0x6e, 0xd6, 0x45, 0xfa, 0x44, 0x37, 0xd7, 0x27, 0x20, 0xcf, 0x94, ++ 0x3c, 0x51, 0x72, 0x83, 0xf3, 0x81, 0x17, 0x79, 0x3d, 0x8a, 0xbe, 0x4a, ++ 0x7e, 0xec, 0x6c, 0xe4, 0x20, 0x71, 0xbc, 0xee, 0x6a, 0xb4, 0x53, 0xf9, ++ 0x4c, 0xa3, 0x93, 0x59, 0xb8, 0x0c, 0xd8, 0xdd, 0x98, 0x4c, 0xf5, 0xe7, ++ 0x1b, 0x5d, 0x54, 0xb6, 0x35, 0xe6, 0xd2, 0xf3, 0x17, 0x1a, 0x3d, 0x54, ++ 0xdf, 0xdb, 0x58, 0x42, 0xf5, 0xfd, 0x8d, 0x5e, 0xaa, 0x1f, 0x68, 0x9c, ++ 0x4c, 0xe5, 0xcf, 0x1a, 0x7d, 0xf4, 0x9c, 0xe3, 0x85, 0xe4, 0x90, 0x92, ++ 0x2b, 0x4a, 0x1e, 0x29, 0x7e, 0x52, 0x72, 0x29, 0x9c, 0x8f, 0xe6, 0x71, ++ 0xf4, 0x5e, 0x57, 0x4c, 0xdf, 0x93, 0xdc, 0x53, 0xf2, 0x0e, 0xf3, 0x30, ++ 0x15, 0xf7, 0xca, 0x23, 0x45, 0xdf, 0x0c, 0xcd, 0xe7, 0x4f, 0x76, 0x43, ++ 0x8e, 0x75, 0xcc, 0x81, 0xbc, 0x28, 0x37, 0x9f, 0x7d, 0xee, 0x25, 0xf8, ++ 0x49, 0x6a, 0x1c, 0x9e, 0x08, 0x17, 0xf0, 0x22, 0xe4, 0x5e, 0xb7, 0xc3, ++ 0x4e, 0x72, 0x3e, 0xdd, 0xc6, 0x0e, 0xc0, 0x5e, 0x6f, 0x5a, 0xe1, 0xed, ++ 0xdc, 0x10, 0xb2, 0xaf, 0xde, 0x5e, 0xa3, 0x31, 0x4b, 0x08, 0x9f, 0xde, ++ 0x51, 0x1f, 0xc9, 0x2c, 0x21, 0x7c, 0x7c, 0x67, 0x43, 0xbc, 0xa1, 0x5e, ++ 0xd1, 0xf0, 0xde, 0x6b, 0x83, 0x78, 0xff, 0x5a, 0xbc, 0xfe, 0xdf, 0xa0, ++ 0xcb, 0x89, 0x7b, 0x3f, 0x7d, 0xfc, 0xb7, 0xfc, 0xf9, 0x93, 0xf7, 0x7e, ++ 0x91, 0x0d, 0x7a, 0x73, 0x38, 0x76, 0x6c, 0xc1, 0xb8, 0xab, 0xa3, 0x7a, ++ 0xe0, 0x48, 0x40, 0x7d, 0xad, 0x95, 0xf4, 0x87, 0xa1, 0x51, 0xc2, 0x0e, ++ 0xc2, 0x1f, 0xe8, 0x32, 0x9f, 0x89, 0xf5, 0xf9, 0xe4, 0xbd, 0x7f, 0xa5, ++ 0xf5, 0xdd, 0xd9, 0x10, 0xe1, 0x32, 0xf3, 0x76, 0xf3, 0x1b, 0x22, 0x08, ++ 0x5f, 0x1f, 0x82, 0x4e, 0x1c, 0xaf, 0x1f, 0x4b, 0x3a, 0x55, 0xae, 0x3b, ++ 0xf9, 0xdc, 0x4b, 0x58, 0xe7, 0xab, 0x6d, 0x24, 0xe7, 0xe6, 0xaf, 0x95, ++ 0xeb, 0x72, 0x23, 0xc7, 0x67, 0x88, 0xbe, 0xf6, 0x49, 0x0a, 0x23, 0xbd, ++ 0x4c, 0xf3, 0x32, 0x86, 0x38, 0xcc, 0x27, 0xdf, 0xb3, 0x05, 0xf9, 0x9e, ++ 0xcf, 0x3e, 0xd1, 0xec, 0x01, 0x0d, 0xba, 0x0f, 0x37, 0x92, 0x2a, 0xf8, ++ 0x73, 0x7d, 0xe3, 0x1b, 0x94, 0x7f, 0xa5, 0x35, 0x1c, 0x23, 0x7d, 0x58, ++ 0x47, 0x5e, 0x16, 0xfc, 0x04, 0x7e, 0xab, 0x21, 0x1f, 0x4b, 0x6b, 0x90, ++ 0x79, 0x5a, 0x1d, 0x43, 0x0c, 0x79, 0x54, 0xd1, 0xa3, 0xbd, 0x36, 0xc8, ++ 0x07, 0xf0, 0x34, 0xe8, 0x36, 0x3f, 0xf7, 0x30, 0xc3, 0xba, 0x66, 0xcd, ++ 0x9a, 0x13, 0x5b, 0x40, 0xb5, 0x7c, 0x5e, 0xbd, 0x51, 0x23, 0x7d, 0xa3, ++ 0x47, 0x5f, 0xc8, 0x36, 0x13, 0x1d, 0x2b, 0xb3, 0x2c, 0x54, 0xfe, 0x02, ++ 0x6b, 0x9c, 0xec, 0xc5, 0x66, 0xda, 0x9f, 0x14, 0xbf, 0x72, 0x79, 0xe1, ++ 0x0d, 0x60, 0x5d, 0x34, 0x17, 0xd9, 0x16, 0x86, 0xc8, 0xe1, 0xf9, 0xf2, ++ 0x79, 0x55, 0xae, 0x89, 0x4a, 0xf5, 0xbc, 0x32, 0xcb, 0x46, 0xfd, 0xfc, ++ 0x02, 0x8b, 0x91, 0xf7, 0xfb, 0x40, 0x6e, 0x86, 0x6d, 0x01, 0xc9, 0x39, ++ 0x97, 0x0d, 0x72, 0x40, 0xb5, 0x9f, 0x9f, 0x5b, 0xbc, 0x3e, 0x63, 0x34, ++ 0xfa, 0x99, 0x30, 0x80, 0x85, 0xac, 0xc7, 0xa2, 0x6c, 0x0b, 0x7d, 0x5f, ++ 0x89, 0x44, 0x2f, 0xec, 0x5f, 0x76, 0xe1, 0xff, 0xaf, 0xed, 0x67, 0x1f, ++ 0x50, 0x7a, 0xc9, 0x69, 0xfc, 0xf3, 0x6a, 0x82, 0x9f, 0xec, 0xad, 0x25, ++ 0xcf, 0x3f, 0xfb, 0x3c, 0xe2, 0x63, 0x4b, 0x3e, 0x8a, 0x20, 0x3a, 0x2d, ++ 0x19, 0x29, 0xfd, 0x11, 0xf9, 0x81, 0xb1, 0xd3, 0x49, 0x9f, 0xf1, 0x3a, ++ 0x34, 0x3e, 0xcf, 0x65, 0x92, 0xfe, 0x65, 0xcf, 0xfe, 0x3e, 0xb6, 0x83, ++ 0xbf, 0x5f, 0xbe, 0x57, 0xf8, 0x2f, 0x79, 0xd9, 0x89, 0x72, 0xd9, 0xea, ++ 0x1a, 0xf2, 0x6b, 0x2d, 0xf3, 0xf0, 0xf5, 0x91, 0x00, 0xb9, 0x6a, 0x8c, ++ 0x23, 0x1f, 0x7d, 0xfe, 0xa3, 0xd8, 0x0e, 0xb2, 0x2b, 0xfc, 0xa9, 0xc8, ++ 0x2f, 0xe4, 0xdb, 0x42, 0x2a, 0x4b, 0x46, 0xbc, 0xe8, 0xe4, 0x24, 0xf8, ++ 0xc5, 0x97, 0xb3, 0xae, 0xf5, 0xc8, 0xeb, 0x0a, 0xff, 0x6e, 0xb9, 0xf6, ++ 0x55, 0xac, 0xf0, 0xef, 0x8b, 0x38, 0xb9, 0x8a, 0x5f, 0x96, 0xbf, 0xfa, ++ 0xe7, 0x24, 0x82, 0x63, 0xdf, 0xc5, 0x24, 0xc8, 0xb5, 0xe5, 0xaf, 0xae, ++ 0x4b, 0xd2, 0xfb, 0x98, 0xf7, 0xf2, 0xb0, 0xf8, 0xb5, 0x8a, 0x9b, 0x2b, ++ 0x3f, 0xd8, 0x72, 0xb6, 0xe9, 0x4b, 0xc4, 0xdd, 0xc2, 0xdb, 0x55, 0x65, ++ 0xc7, 0x0c, 0x00, 0xff, 0xb0, 0xab, 0xd8, 0x55, 0xe4, 0xa7, 0xb0, 0x30, ++ 0xca, 0x63, 0x58, 0x69, 0x17, 0x78, 0xe8, 0x0e, 0x64, 0xc7, 0xb1, 0x3e, ++ 0xc6, 0xeb, 0x19, 0x77, 0x2b, 0x17, 0xec, 0xdc, 0x0e, 0xed, 0xb6, 0xb8, ++ 0xe2, 0x3c, 0x1c, 0xce, 0x0b, 0xfd, 0xe4, 0xf1, 0xed, 0xca, 0x16, 0xfb, ++ 0xf9, 0x39, 0x19, 0x47, 0xbd, 0xb0, 0xdb, 0x4c, 0x7a, 0xe1, 0x85, 0xdd, ++ 0x31, 0xc4, 0xff, 0xcb, 0x76, 0xff, 0xf0, 0xf5, 0x6b, 0x78, 0x7d, 0xd9, ++ 0x76, 0x0d, 0xc3, 0xb2, 0x3a, 0xd6, 0x4e, 0x78, 0x5a, 0xb6, 0xd7, 0xcc, ++ 0xec, 0xa1, 0xf6, 0x0d, 0xfc, 0x36, 0x89, 0xfd, 0xc3, 0xb9, 0xf4, 0xd9, ++ 0x98, 0x7a, 0xf0, 0xd3, 0xe2, 0x36, 0xcd, 0xbb, 0x23, 0x1f, 0x71, 0x79, ++ 0x57, 0xdc, 0xc0, 0x10, 0x78, 0xd6, 0x49, 0x7e, 0x5a, 0x1a, 0xd1, 0x36, ++ 0x96, 0xe8, 0x20, 0xe1, 0xff, 0xae, 0xd4, 0x8f, 0x54, 0xbb, 0xc5, 0x07, ++ 0x7f, 0x68, 0x03, 0xbd, 0x78, 0xbb, 0xf3, 0xa4, 0xb7, 0xfc, 0x34, 0x1a, ++ 0xba, 0x36, 0xff, 0xeb, 0x7a, 0x07, 0x70, 0x9e, 0xd9, 0x36, 0x8a, 0xe2, ++ 0xba, 0x8b, 0xdb, 0xf6, 0x2c, 0xa3, 0x7d, 0x7f, 0x77, 0xb4, 0x13, 0x53, ++ 0xfc, 0xc2, 0x6a, 0xf4, 0x47, 0x6d, 0x96, 0xe3, 0x6d, 0xce, 0x16, 0x7a, ++ 0xc6, 0x19, 0xe9, 0xff, 0x3d, 0xf3, 0xbc, 0x99, 0xe4, 0x0f, 0xe0, 0xc4, ++ 0x3a, 0xfc, 0x42, 0x13, 0x7e, 0x5e, 0xf5, 0xdd, 0x16, 0xf9, 0xdd, 0x16, ++ 0x89, 0xb7, 0xeb, 0x10, 0x54, 0x1c, 0xd3, 0xdb, 0x7e, 0x71, 0x5b, 0x67, ++ 0x6c, 0x16, 0x6f, 0xff, 0xd9, 0x81, 0xf7, 0xa8, 0x6c, 0x95, 0xed, 0x17, ++ 0x3b, 0xda, 0x0b, 0xb1, 0x5f, 0x7e, 0xb6, 0x37, 0x7a, 0x72, 0x80, 0xca, ++ 0x1f, 0x4d, 0x7a, 0x85, 0x8f, 0x77, 0xae, 0x6d, 0xc2, 0x00, 0x2d, 0x64, ++ 0x5d, 0x3d, 0x9f, 0x6d, 0xa5, 0xfe, 0xce, 0x6d, 0x33, 0x4f, 0x06, 0xbe, ++ 0x58, 0x40, 0xe5, 0x19, 0xb5, 0xd1, 0x7c, 0xce, 0xec, 0x4e, 0xd5, 0xc8, ++ 0xae, 0x05, 0xbe, 0x39, 0x7e, 0xce, 0xec, 0x7d, 0x31, 0xd6, 0x44, 0xeb, ++ 0xd6, 0x6f, 0xa0, 0xa3, 0xc9, 0x2e, 0xfc, 0xa9, 0x6e, 0x8b, 0x4b, 0xea, ++ 0x97, 0x76, 0x27, 0xf4, 0x8c, 0xb9, 0x5c, 0xab, 0x8b, 0xe3, 0xf2, 0xae, ++ 0x6e, 0xaf, 0xc8, 0x07, 0x08, 0x7f, 0xae, 0xda, 0xd3, 0x7a, 0x4b, 0x01, ++ 0xbf, 0x77, 0xd9, 0x04, 0xff, 0xcb, 0xf8, 0xbd, 0x8c, 0x2f, 0x21, 0x4f, ++ 0x84, 0xe2, 0xf1, 0x31, 0xb6, 0x00, 0xf6, 0xd7, 0x79, 0x23, 0x5d, 0xb3, ++ 0x6e, 0x87, 0x3c, 0x7b, 0xcb, 0x2a, 0xe8, 0x31, 0xc4, 0xb5, 0x05, 0x76, ++ 0xd5, 0xbc, 0x77, 0x13, 0xc9, 0x5f, 0xb1, 0xd2, 0xea, 0x1a, 0x84, 0xfa, ++ 0x9f, 0xde, 0xb6, 0x92, 0xff, 0x7c, 0xde, 0x28, 0xb9, 0xce, 0x93, 0x3b, ++ 0xc6, 0xc0, 0x3f, 0xd9, 0xe9, 0x16, 0xfb, 0x7a, 0xed, 0x46, 0xbe, 0x42, ++ 0xf8, 0x94, 0x07, 0x73, 0xfa, 0xfb, 0xf9, 0xfc, 0x6a, 0x03, 0x26, 0xca, ++ 0xa7, 0x7c, 0x3f, 0x3b, 0x83, 0xe6, 0xf7, 0x58, 0x8d, 0xc9, 0x6b, 0xa3, ++ 0x38, 0x47, 0x30, 0x07, 0x7e, 0xca, 0x13, 0x36, 0xe6, 0x37, 0x43, 0x4f, ++ 0x7e, 0x21, 0x92, 0xf4, 0xbb, 0xda, 0x0c, 0xe1, 0x77, 0x7f, 0x0c, 0xfc, ++ 0xce, 0xcb, 0xda, 0x84, 0x60, 0x4e, 0x22, 0xf4, 0x1d, 0x49, 0xc7, 0xda, ++ 0x5b, 0xf9, 0xfb, 0x10, 0x7a, 0xd6, 0x3e, 0x15, 0xcc, 0x81, 0xde, 0x72, ++ 0xd6, 0x26, 0xfc, 0x78, 0x78, 0xef, 0x44, 0x59, 0x2c, 0xda, 0x35, 0x49, ++ 0xbe, 0x41, 0x3f, 0xe8, 0xb7, 0xd3, 0xed, 0x3c, 0x4f, 0xfa, 0xe5, 0xbe, ++ 0x18, 0x06, 0x3d, 0xdf, 0xf4, 0x52, 0x8c, 0xf0, 0x27, 0xfc, 0x24, 0x92, ++ 0xe2, 0x0e, 0xaa, 0xdf, 0x53, 0xd9, 0x42, 0xbf, 0x6f, 0x92, 0x71, 0x2e, ++ 0xff, 0x0e, 0x01, 0x1f, 0xe0, 0x82, 0xde, 0xbc, 0xd8, 0xd6, 0x9c, 0x03, ++ 0xbd, 0x52, 0x8d, 0xbb, 0x38, 0xb6, 0x99, 0xc6, 0x3b, 0x2b, 0xc7, 0x5b, ++ 0x1c, 0xd5, 0x2c, 0xe2, 0x07, 0x32, 0x2f, 0x0c, 0xed, 0x69, 0x7c, 0x2b, ++ 0xf3, 0xc2, 0x1e, 0xef, 0x7a, 0x3a, 0x82, 0xf4, 0xd3, 0x2f, 0x52, 0xda, ++ 0xf7, 0x63, 0xfc, 0x2f, 0x9e, 0x1e, 0x4e, 0x71, 0xf0, 0x4e, 0x77, 0x60, ++ 0xe1, 0x01, 0x7a, 0xcf, 0xf5, 0x36, 0x4e, 0x87, 0x25, 0xcf, 0x44, 0x04, ++ 0x01, 0xef, 0xe7, 0x4f, 0xc7, 0x50, 0x9c, 0xf3, 0x73, 0xab, 0xd0, 0x83, ++ 0x3e, 0x8f, 0x49, 0x22, 0x3d, 0xe8, 0x58, 0xcc, 0x23, 0xf3, 0xd0, 0x5f, ++ 0xf7, 0xf6, 0x08, 0x0d, 0xfe, 0x94, 0xcf, 0x35, 0x66, 0x4b, 0xc6, 0xfb, ++ 0x1d, 0x03, 0x29, 0x5e, 0xb5, 0xa4, 0xb1, 0x81, 0xe2, 0x04, 0x4b, 0xf8, ++ 0x72, 0x47, 0x3c, 0x9a, 0x97, 0x93, 0x11, 0x57, 0xfe, 0x7c, 0xc7, 0x70, ++ 0xf2, 0xb3, 0x7c, 0xfe, 0xa6, 0x99, 0xe2, 0x8b, 0xfc, 0xf9, 0x46, 0x3c, ++ 0xd7, 0x59, 0xf3, 0xbc, 0xef, 0x60, 0xdd, 0xed, 0x8a, 0x26, 0x3f, 0xdb, ++ 0x17, 0xcf, 0xfc, 0x6d, 0x78, 0x68, 0xfc, 0x41, 0x95, 0x4b, 0xb6, 0x1b, ++ 0xfd, 0x49, 0x8a, 0xfe, 0xea, 0xbd, 0x35, 0x47, 0xd8, 0x0d, 0xd6, 0x1c, ++ 0x81, 0xc7, 0xc8, 0x1c, 0xb1, 0xcf, 0xd4, 0x45, 0xb7, 0x3d, 0x92, 0x41, ++ 0xf3, 0x14, 0xeb, 0x95, 0xd3, 0x81, 0xec, 0x2d, 0xbe, 0x3e, 0x92, 0xe0, ++ 0x9f, 0x3e, 0xd1, 0xf6, 0x72, 0x92, 0xe6, 0x00, 0x9e, 0x83, 0x39, 0x3f, ++ 0x02, 0xde, 0x77, 0x09, 0xbb, 0xe6, 0x8b, 0xdd, 0x56, 0x8a, 0x8b, 0x2c, ++ 0x79, 0x29, 0xc6, 0x4b, 0xfe, 0x9b, 0x0d, 0x57, 0x99, 0xb0, 0x5f, 0x2c, ++ 0x31, 0x0b, 0xfd, 0x77, 0x09, 0x67, 0x37, 0x51, 0x0a, 0xff, 0xd0, 0x92, ++ 0xd8, 0x1c, 0xf2, 0x0f, 0x71, 0x7c, 0x93, 0xfd, 0xd8, 0xb5, 0xc3, 0x2c, ++ 0xc7, 0x11, 0xe3, 0x7e, 0xbe, 0x33, 0x4d, 0xf8, 0xdf, 0x83, 0xb2, 0xbe, ++ 0xbf, 0x20, 0x00, 0x3e, 0x9f, 0x92, 0xc0, 0xee, 0xbc, 0x95, 0xf4, 0x9b, ++ 0x6d, 0x85, 0xc0, 0xeb, 0xc5, 0xed, 0xd1, 0x26, 0xf0, 0x05, 0x1f, 0xc7, ++ 0x8b, 0xb8, 0xfd, 0x92, 0xef, 0x7c, 0x57, 0xe0, 0x33, 0x6e, 0x21, 0xe9, ++ 0xe3, 0x0c, 0x79, 0xd0, 0x63, 0x11, 0x2f, 0x17, 0xf2, 0xb2, 0x6e, 0xc3, ++ 0x35, 0x71, 0xc8, 0x87, 0x61, 0xef, 0x9a, 0x19, 0x44, 0xdf, 0x45, 0x8b, ++ 0x67, 0x10, 0xe4, 0x61, 0x38, 0xbe, 0x66, 0xe7, 0x48, 0x79, 0xb9, 0xff, ++ 0x71, 0x1b, 0xe2, 0x67, 0xb5, 0x7c, 0xbd, 0x20, 0x3f, 0x68, 0xa9, 0x8c, ++ 0x9b, 0x2e, 0x7d, 0x46, 0x23, 0x7d, 0x6e, 0xe9, 0xfa, 0x6b, 0xb6, 0x90, ++ 0x1c, 0x7c, 0xc7, 0xca, 0xb2, 0x39, 0x1c, 0x67, 0xdb, 0x7e, 0x18, 0x1b, ++ 0x4a, 0x8f, 0xd2, 0x1c, 0xa1, 0x57, 0xf4, 0x7e, 0xef, 0xa1, 0xf6, 0x4b, ++ 0x79, 0x7b, 0xf1, 0xfd, 0x5b, 0xb1, 0x04, 0xcf, 0x4e, 0xab, 0x07, 0xf0, ++ 0x84, 0xd3, 0xf1, 0x8a, 0xbf, 0x7f, 0xc6, 0x7c, 0x45, 0xdf, 0xf7, 0xf0, ++ 0x47, 0x1b, 0xdf, 0xd7, 0x0b, 0x2f, 0x9f, 0xf7, 0x45, 0xd6, 0xfe, 0xbf, ++ 0x3e, 0x82, 0x1c, 0xd9, 0x1d, 0xe9, 0xf1, 0xd3, 0xd3, 0x36, 0x8a, 0x3b, ++ 0x9f, 0xb1, 0xb6, 0x2d, 0xc4, 0xbc, 0xcf, 0x3c, 0x17, 0x49, 0xf2, 0xe5, ++ 0x4c, 0xbc, 0x58, 0xef, 0x9f, 0x71, 0x79, 0xe8, 0xb7, 0x01, 0x8e, 0x6f, ++ 0x3d, 0x44, 0xfe, 0x8d, 0xdf, 0x4c, 0x67, 0x10, 0xdd, 0x8b, 0x02, 0xc6, ++ 0x7e, 0xd5, 0xb8, 0x37, 0xe4, 0x88, 0x73, 0x1b, 0x75, 0x89, 0x9e, 0x38, ++ 0xc4, 0x33, 0xea, 0x38, 0x1d, 0xd0, 0x1f, 0xa7, 0xcb, 0x2d, 0xf4, 0xfd, ++ 0xbb, 0x56, 0xfa, 0x3e, 0x7c, 0x1e, 0x39, 0x39, 0x42, 0x6e, 0xf7, 0xac, ++ 0xcf, 0xe7, 0xa2, 0x89, 0x5f, 0xce, 0x0c, 0x16, 0xf4, 0x38, 0xf3, 0xfc, ++ 0x30, 0xda, 0x57, 0x3a, 0xe3, 0x05, 0x9f, 0x73, 0x78, 0xd3, 0x61, 0xa7, ++ 0x9c, 0x89, 0x17, 0x25, 0x83, 0x32, 0xc2, 0xf9, 0x60, 0x89, 0xb4, 0x43, ++ 0xcf, 0x4c, 0x68, 0x23, 0xbb, 0xfb, 0x8c, 0xb6, 0x87, 0xca, 0x4e, 0xab, ++ 0xf8, 0x6e, 0x49, 0x83, 0x8c, 0xdb, 0x72, 0xbe, 0x4b, 0x06, 0xdf, 0x80, ++ 0x27, 0x11, 0xb7, 0xb2, 0x6f, 0x6a, 0x87, 0x1e, 0x01, 0xff, 0xf4, 0xd8, ++ 0x62, 0x2a, 0x83, 0x11, 0x09, 0x97, 0xfb, 0x99, 0xc1, 0x9f, 0xd8, 0x87, ++ 0x9e, 0x94, 0xeb, 0x0b, 0x6a, 0x0d, 0xe4, 0x3a, 0xc5, 0x37, 0x48, 0x3f, ++ 0x69, 0xb3, 0x41, 0x1e, 0xeb, 0x52, 0x8f, 0xab, 0xdd, 0x7d, 0x79, 0xbc, ++ 0x8c, 0xe2, 0xa0, 0xbb, 0x35, 0x8a, 0xfb, 0xdc, 0xab, 0xfa, 0xe1, 0x50, ++ 0x0f, 0x50, 0xfe, 0x71, 0xce, 0x8f, 0x4b, 0xfd, 0x9a, 0x17, 0xf9, 0x46, ++ 0x4b, 0xd7, 0xae, 0x58, 0x0c, 0x7e, 0x5f, 0x5a, 0xbf, 0xf9, 0x76, 0xf0, ++ 0xbb, 0x9a, 0xc7, 0x52, 0x0b, 0x9b, 0x0c, 0xfb, 0xaa, 0x53, 0x33, 0x13, ++ 0x3c, 0x9d, 0x91, 0x7c, 0xdd, 0x00, 0x0f, 0xa1, 0xe3, 0x65, 0xf4, 0xe2, ++ 0xf7, 0xfe, 0x1c, 0xad, 0x27, 0x0f, 0xda, 0x99, 0x44, 0x7a, 0x26, 0x29, ++ 0xd7, 0x0f, 0xe6, 0x88, 0xfd, 0x0a, 0xf5, 0x66, 0xde, 0x5f, 0xed, 0x5a, ++ 0x6d, 0x13, 0x8d, 0xe3, 0x56, 0xf6, 0xa4, 0x98, 0x9f, 0xc2, 0x13, 0x47, ++ 0x8b, 0x0d, 0x7e, 0x32, 0x6e, 0xe7, 0x8b, 0xf7, 0xfd, 0xcc, 0x5f, 0xc1, ++ 0x19, 0x3e, 0x7f, 0x05, 0x4f, 0x6b, 0x8e, 0xd0, 0x1b, 0x3a, 0xdd, 0xae, ++ 0x87, 0xc6, 0x83, 0xde, 0xbf, 0x32, 0x93, 0xff, 0xf4, 0xe2, 0x57, 0xa3, ++ 0xe2, 0x12, 0xbe, 0x46, 0x2f, 0x83, 0xc5, 0xd6, 0xe3, 0x2f, 0xe6, 0xf0, ++ 0x3f, 0xcf, 0xf7, 0x6a, 0xc0, 0xbf, 0x42, 0xca, 0xb7, 0xa5, 0xf0, 0x47, ++ 0x73, 0x38, 0x73, 0xb6, 0x19, 0xe3, 0x1f, 0xb9, 0xdb, 0x8d, 0xf5, 0x11, ++ 0xbb, 0x8d, 0xf5, 0xfc, 0xbd, 0xc6, 0x7a, 0xe1, 0x41, 0x63, 0xdd, 0x73, ++ 0xd4, 0x58, 0x7f, 0x04, 0xe3, 0x0e, 0xec, 0xc5, 0x13, 0xec, 0x5c, 0xe4, ++ 0xb5, 0xc1, 0xce, 0x45, 0x09, 0x3b, 0xd7, 0x95, 0x23, 0xec, 0x5c, 0xd4, ++ 0x61, 0xe7, 0xa2, 0x84, 0x9d, 0x8b, 0xe7, 0xb0, 0x73, 0x51, 0x87, 0x9d, ++ 0x8b, 0x3a, 0xec, 0x5c, 0xd4, 0x61, 0xe7, 0xa2, 0x84, 0x9d, 0x8b, 0xe7, ++ 0x7f, 0x90, 0x78, 0xaa, 0x95, 0x7e, 0x47, 0xd0, 0x81, 0xf2, 0xab, 0x5e, ++ 0x8e, 0x54, 0x71, 0x70, 0x5a, 0x2f, 0x17, 0xe6, 0x24, 0x91, 0xfc, 0x54, ++ 0xf1, 0xcc, 0x0b, 0x8b, 0xf3, 0xa9, 0xde, 0xe3, 0xcf, 0x99, 0x66, 0x27, ++ 0x7f, 0x8e, 0xca, 0xd3, 0xb9, 0x3d, 0x4e, 0x7f, 0x33, 0x87, 0xe2, 0x86, ++ 0xed, 0xeb, 0x53, 0x40, 0x37, 0x4b, 0x07, 0xf9, 0x71, 0x97, 0xff, 0x4c, ++ 0xf8, 0x71, 0x6b, 0x8b, 0x23, 0x1d, 0xf0, 0x2f, 0x74, 0xac, 0xfb, 0x6c, ++ 0x3d, 0xd4, 0xa7, 0xc2, 0x38, 0xfd, 0x1d, 0xb4, 0xbf, 0x60, 0xed, 0xda, ++ 0x29, 0xf2, 0x95, 0x82, 0x24, 0x37, 0x3a, 0xd6, 0xb8, 0xde, 0xbd, 0x5e, ++ 0xd0, 0x8f, 0xfc, 0x1c, 0x2a, 0xef, 0xa6, 0x12, 0xfb, 0x5d, 0x42, 0xff, ++ 0x74, 0x0c, 0x8f, 0xa3, 0xb0, 0x4d, 0xc6, 0xb8, 0x49, 0x78, 0x1c, 0x25, ++ 0x3c, 0x7e, 0x12, 0xce, 0x07, 0x2a, 0x6e, 0xf2, 0xa4, 0xb5, 0x2b, 0x05, ++ 0xf2, 0xfe, 0xe4, 0xd3, 0xf6, 0x4d, 0x80, 0xff, 0xa4, 0xf4, 0x8f, 0xb1, ++ 0xd9, 0x4e, 0xd2, 0xbf, 0x94, 0x5e, 0xdd, 0xa3, 0x7f, 0x3d, 0xa8, 0x3d, ++ 0x85, 0x7d, 0xfb, 0x42, 0x8e, 0xc8, 0xfb, 0xeb, 0x3e, 0xc6, 0xf5, 0xed, ++ 0x3e, 0xf6, 0x5b, 0x55, 0x56, 0x5d, 0x2a, 0x26, 0xbd, 0xb1, 0xa7, 0xbe, ++ 0x49, 0x33, 0x51, 0xde, 0x48, 0x72, 0x2c, 0xed, 0x43, 0xab, 0x24, 0x4c, ++ 0xe9, 0x5a, 0x57, 0xe7, 0x06, 0xc8, 0xbb, 0x18, 0x13, 0xed, 0xe3, 0x17, ++ 0x1d, 0x26, 0xb2, 0x0b, 0x2e, 0xbe, 0x6f, 0x26, 0x3d, 0x62, 0x18, 0xf4, ++ 0xf3, 0x90, 0xf9, 0x0c, 0x0f, 0x44, 0x19, 0xf8, 0x2b, 0x6f, 0x57, 0x42, ++ 0x58, 0xfc, 0x6f, 0xb0, 0xa1, 0xfd, 0xc8, 0x03, 0x19, 0x61, 0xf1, 0xbf, ++ 0x11, 0xc6, 0xb8, 0xd4, 0x6d, 0x6b, 0x0e, 0xc1, 0xbe, 0x9e, 0xbe, 0x69, ++ 0x94, 0xa1, 0x5d, 0xb5, 0xef, 0x9a, 0x30, 0x3c, 0x4a, 0xb8, 0xa5, 0x5e, ++ 0xda, 0xb4, 0x7a, 0x6b, 0x3a, 0xe4, 0xcf, 0xaa, 0x98, 0x6e, 0x82, 0x7f, ++ 0xd5, 0xbe, 0x48, 0xca, 0xab, 0xad, 0xe6, 0xf0, 0x7a, 0x11, 0x97, 0x43, ++ 0x85, 0xa3, 0xa0, 0xc6, 0xee, 0x9d, 0x0a, 0xfc, 0xd5, 0xb4, 0x59, 0xe3, ++ 0xb1, 0xcf, 0x57, 0xc9, 0xfd, 0x87, 0x35, 0x18, 0xf7, 0xe3, 0x1a, 0x0b, ++ 0xf3, 0x3b, 0x13, 0x7a, 0xf9, 0xae, 0xc6, 0xc9, 0xbc, 0xf1, 0xfc, 0xfb, ++ 0x73, 0x45, 0xcd, 0x3b, 0x4d, 0x9c, 0x6e, 0xe7, 0x4c, 0xdb, 0x1e, 0x19, ++ 0xef, 0x42, 0x5c, 0xa9, 0x35, 0xdd, 0xc9, 0xf9, 0xea, 0x2e, 0xad, 0x2d, ++ 0xe9, 0x6a, 0xde, 0xdf, 0xdf, 0x2c, 0x7a, 0xda, 0x30, 0x4e, 0x8f, 0x74, ++ 0x6b, 0xf0, 0x07, 0x15, 0x90, 0x97, 0x7b, 0x32, 0xd9, 0x1a, 0xde, 0xee, ++ 0xe4, 0xa6, 0x17, 0x63, 0x49, 0xef, 0x96, 0x7c, 0x96, 0x6e, 0x75, 0x46, ++ 0x81, 0xde, 0xad, 0xcd, 0x66, 0xb2, 0x0b, 0xe0, 0x97, 0x32, 0x27, 0xf4, ++ 0xf2, 0x43, 0x6b, 0x73, 0x62, 0x54, 0x96, 0xa3, 0x77, 0x9e, 0xbd, 0xf4, ++ 0xff, 0x8a, 0xe6, 0xc7, 0xe9, 0xe2, 0xc1, 0x39, 0xc5, 0x6e, 0xc7, 0xe1, ++ 0x21, 0xab, 0xa0, 0xc7, 0xb5, 0x89, 0xf9, 0xd6, 0x4c, 0xd0, 0xfc, 0xa4, ++ 0x27, 0xcb, 0xf9, 0xac, 0x94, 0xfb, 0x0a, 0xcb, 0x12, 0xfd, 0xdc, 0x25, ++ 0xeb, 0xa7, 0xa4, 0xbd, 0xa0, 0xe6, 0x77, 0x76, 0xf8, 0xa1, 0x42, 0x17, ++ 0xe2, 0x98, 0x8d, 0x07, 0xd2, 0xcd, 0x90, 0xe3, 0xa6, 0xdd, 0x3b, 0x71, ++ 0x7e, 0xe0, 0xde, 0x28, 0xbd, 0x64, 0xd8, 0x40, 0xe4, 0x4b, 0x66, 0xff, ++ 0x76, 0x3c, 0x1f, 0x77, 0xc9, 0x07, 0x22, 0x5f, 0xf7, 0x8f, 0x2d, 0x13, ++ 0x63, 0xaf, 0x86, 0xfe, 0xf9, 0x9c, 0xd5, 0x33, 0x85, 0xd7, 0x37, 0x34, ++ 0xff, 0xd8, 0x06, 0xbb, 0x78, 0x89, 0x25, 0x60, 0x83, 0xdd, 0x59, 0xf3, ++ 0x74, 0xab, 0xcd, 0xcb, 0xcb, 0x1b, 0x76, 0xb5, 0xd2, 0xf3, 0x85, 0xbb, ++ 0x2a, 0xc9, 0xde, 0x5e, 0xc4, 0xea, 0xc9, 0x8e, 0x3c, 0xad, 0xf2, 0x6f, ++ 0x25, 0x3e, 0x6a, 0x4a, 0xb5, 0x6d, 0x4e, 0x0e, 0xf7, 0x93, 0xc3, 0x84, ++ 0xdc, 0xa8, 0x89, 0x12, 0x79, 0x1b, 0xe5, 0xe6, 0xf1, 0xaf, 0x21, 0x2f, ++ 0xfd, 0xe2, 0x2e, 0xad, 0x08, 0xf3, 0xbd, 0xcd, 0xb7, 0xc7, 0x56, 0xc9, ++ 0x9f, 0xdf, 0x3a, 0x4c, 0x9e, 0x3b, 0x09, 0x5b, 0x1f, 0xdd, 0x6f, 0x4f, ++ 0x2f, 0x1f, 0x08, 0x7f, 0x52, 0x9b, 0x88, 0x7b, 0xf6, 0xb7, 0x1e, 0x66, ++ 0x04, 0x73, 0x69, 0x3d, 0x4c, 0xbf, 0xe4, 0xa2, 0xf2, 0xb6, 0x4b, 0x23, ++ 0xc8, 0x8e, 0xfd, 0x80, 0xf9, 0x0a, 0x48, 0x4e, 0xe4, 0x87, 0xd9, 0xb3, ++ 0x6f, 0x8b, 0x3c, 0xe4, 0xee, 0x83, 0x62, 0x1d, 0xd4, 0xd8, 0x82, 0x03, ++ 0xa6, 0x63, 0x9d, 0xfc, 0xdc, 0x4a, 0xeb, 0xa4, 0x8e, 0xcb, 0xaf, 0x92, ++ 0x62, 0xd8, 0xc9, 0x8c, 0x8d, 0xe3, 0xa5, 0x6f, 0xbc, 0xd9, 0xc0, 0xaf, ++ 0xcb, 0xcb, 0xa2, 0x0d, 0xfc, 0x3c, 0x9b, 0x25, 0x18, 0xe2, 0xc8, 0x33, ++ 0x71, 0x68, 0x33, 0xa4, 0x7e, 0xdb, 0x94, 0x4c, 0x43, 0xfb, 0x59, 0xb7, ++ 0xe5, 0x85, 0xf1, 0x7f, 0x71, 0xef, 0x7b, 0x92, 0x23, 0xe3, 0x0c, 0x79, ++ 0x26, 0x75, 0xab, 0xfd, 0x2e, 0x8d, 0xf2, 0x59, 0x4a, 0x8d, 0xcf, 0x79, ++ 0xb9, 0x9a, 0xf8, 0xec, 0x26, 0xc3, 0xf7, 0x75, 0xec, 0xd6, 0xde, 0x76, ++ 0xb0, 0x83, 0xb7, 0xff, 0x9a, 0xf0, 0xcc, 0x58, 0xbb, 0x0d, 0xf6, 0x56, ++ 0x8d, 0x49, 0xe4, 0xd5, 0xcc, 0xd6, 0x3b, 0xe5, 0xf3, 0x0e, 0x7a, 0xce, ++ 0x27, 0x62, 0x58, 0x87, 0x43, 0x33, 0x3d, 0xbf, 0x15, 0xfb, 0xa2, 0x95, ++ 0xfc, 0xf2, 0xca, 0x2f, 0x3d, 0x1b, 0xff, 0xce, 0xec, 0x6b, 0x5f, 0xe4, ++ 0x84, 0x96, 0xe3, 0x22, 0x3f, 0x14, 0xfe, 0x05, 0x43, 0x7e, 0x21, 0x07, ++ 0x80, 0xec, 0x4f, 0x26, 0xe8, 0x50, 0x27, 0xfd, 0x3d, 0x75, 0xb9, 0xc2, ++ 0xdf, 0x53, 0xe7, 0x6f, 0xb7, 0x21, 0xff, 0x96, 0xe3, 0xdf, 0x92, 0xca, ++ 0x51, 0xb2, 0xac, 0x59, 0x23, 0x7f, 0x1e, 0x6f, 0x6f, 0x4f, 0x4d, 0x10, ++ 0xf5, 0xd5, 0x78, 0xbe, 0xd7, 0x78, 0xde, 0x00, 0xfd, 0x5d, 0xc2, 0xfb, ++ 0x63, 0xe6, 0x4a, 0xac, 0x97, 0xf0, 0xf7, 0xcb, 0xf8, 0xbc, 0xa1, 0x67, ++ 0x2c, 0x83, 0x9f, 0x06, 0x7e, 0x26, 0xd5, 0xbf, 0xec, 0x57, 0xf1, 0xe7, ++ 0xa2, 0xad, 0x46, 0xbf, 0xd1, 0x32, 0xf8, 0x73, 0x42, 0xe8, 0xf8, 0xc9, ++ 0x30, 0x17, 0xf1, 0xf3, 0x92, 0x5d, 0x7b, 0x5e, 0x1f, 0xcc, 0xf1, 0x32, ++ 0xdd, 0x17, 0x5f, 0x84, 0xf5, 0x53, 0xdb, 0x36, 0xcd, 0x5a, 0x99, 0x7f, ++ 0x39, 0x9f, 0x29, 0xf9, 0x7e, 0xb1, 0xc6, 0x44, 0x71, 0xee, 0xee, 0xb7, ++ 0x8f, 0x10, 0x9f, 0x75, 0xd7, 0x58, 0x88, 0x9f, 0xbf, 0x09, 0x1f, 0xcb, ++ 0xbc, 0xc2, 0x9f, 0x19, 0xce, 0x7f, 0x0b, 0xf9, 0x7c, 0x10, 0x97, 0x5d, ++ 0xb8, 0x57, 0xf3, 0x04, 0x34, 0xd1, 0x0e, 0x78, 0x19, 0x0c, 0xbe, 0x0c, ++ 0xc3, 0x4b, 0x6a, 0x1f, 0xf8, 0x52, 0x78, 0xea, 0xc1, 0x5b, 0xd8, 0xfb, ++ 0x45, 0xf8, 0xc7, 0x68, 0xe4, 0x0d, 0x68, 0x81, 0xa0, 0xbb, 0x2f, 0xbc, ++ 0x48, 0x3c, 0xaa, 0xfe, 0xc3, 0xf0, 0xc4, 0x4a, 0x8c, 0x78, 0x58, 0xa8, ++ 0xbb, 0xde, 0x85, 0xbc, 0x59, 0x78, 0xcc, 0xcc, 0x02, 0x57, 0x30, 0xef, ++ 0x45, 0x98, 0x1f, 0xc6, 0xe7, 0xf3, 0xc3, 0xf8, 0xb7, 0x5e, 0x12, 0x7e, ++ 0x12, 0x15, 0x37, 0x98, 0x79, 0xc9, 0x42, 0xf5, 0x1e, 0x3e, 0xf1, 0x89, ++ 0xfc, 0xe9, 0xdb, 0xa6, 0x18, 0xd7, 0x65, 0x0f, 0xdf, 0xf8, 0xc4, 0x3a, ++ 0x99, 0x71, 0x29, 0x89, 0xbe, 0xfb, 0x9f, 0xe6, 0x9f, 0x6f, 0xe2, 0x1b, ++ 0x05, 0x77, 0x78, 0x7e, 0xb2, 0x3a, 0xdf, 0x73, 0x7a, 0x98, 0x3c, 0xff, ++ 0x32, 0x86, 0x8d, 0xa1, 0xf5, 0x7f, 0x85, 0x79, 0xc3, 0x6a, 0xbf, 0x57, ++ 0x78, 0x1e, 0x7a, 0x6f, 0x09, 0xe5, 0x13, 0x75, 0x3b, 0x32, 0x48, 0x7f, ++ 0xe8, 0xd9, 0x6f, 0x9c, 0xc6, 0xf7, 0x2b, 0x63, 0x32, 0x28, 0x8f, 0x58, ++ 0x97, 0xfe, 0x39, 0x25, 0x77, 0x75, 0xd9, 0x4e, 0x8d, 0x53, 0xc9, 0xdf, ++ 0xbb, 0x46, 0x81, 0x8f, 0x87, 0x24, 0xc1, 0xef, 0xba, 0x7e, 0x6d, 0x66, ++ 0x7a, 0x47, 0x88, 0x5e, 0xa2, 0xaf, 0xb3, 0x92, 0xdf, 0x34, 0x7d, 0x4d, ++ 0x22, 0x95, 0x95, 0x91, 0xce, 0x24, 0xec, 0x17, 0x95, 0x6b, 0xcc, 0x3e, ++ 0xec, 0x83, 0x9f, 0xdc, 0x3f, 0x28, 0xa9, 0x04, 0x7e, 0xf8, 0x75, 0xd6, ++ 0x01, 0x53, 0x78, 0xd7, 0x9f, 0xdc, 0x33, 0x3a, 0x9d, 0x15, 0xa0, 0x5e, ++ 0x4e, 0xe5, 0xc9, 0xcd, 0x11, 0xb3, 0x43, 0xfd, 0xd9, 0xaa, 0x8c, 0xcf, ++ 0x15, 0xfb, 0x46, 0xdd, 0xbd, 0xc7, 0x69, 0xff, 0x3a, 0x67, 0x7a, 0x3b, ++ 0x76, 0x36, 0xd6, 0xd9, 0xba, 0x7d, 0xb1, 0x48, 0xa9, 0x59, 0xba, 0xee, ++ 0xbd, 0xb1, 0x4e, 0xae, 0x7a, 0xb4, 0x5a, 0x74, 0x67, 0x2e, 0xc5, 0x49, ++ 0x5b, 0x77, 0x3a, 0x81, 0x37, 0x67, 0x6b, 0x21, 0xfc, 0xd1, 0x74, 0xf6, ++ 0x72, 0x60, 0xaf, 0x9e, 0xb0, 0x64, 0x5d, 0xf9, 0x20, 0xf8, 0xbf, 0x6a, ++ 0xff, 0x7e, 0xe4, 0x09, 0xec, 0xef, 0xfa, 0x1a, 0x6b, 0x12, 0xf4, 0xcc, ++ 0xcf, 0xdf, 0xe7, 0xfb, 0x9f, 0x46, 0xfb, 0x17, 0xe9, 0x07, 0xa7, 0x91, ++ 0x7f, 0x3c, 0x00, 0x71, 0xab, 0x68, 0x3a, 0xdf, 0x76, 0x5a, 0x63, 0x5e, ++ 0xc4, 0x6f, 0x16, 0x9b, 0x0f, 0x15, 0x3a, 0x0d, 0xfb, 0xe9, 0xc1, 0x99, ++ 0x80, 0xe3, 0xe5, 0x28, 0xdd, 0x95, 0x3b, 0x06, 0xe3, 0x07, 0x76, 0x26, ++ 0x63, 0x7c, 0x8f, 0x9f, 0xf2, 0x25, 0xf5, 0x35, 0xd9, 0x71, 0x7d, 0xf9, ++ 0x4b, 0x54, 0xb9, 0x7c, 0xab, 0xd0, 0xdf, 0x76, 0x2a, 0x7f, 0xad, 0xf4, ++ 0xeb, 0x42, 0x6f, 0x47, 0x1d, 0x7a, 0x3b, 0x82, 0x42, 0xd0, 0xdb, 0x51, ++ 0x87, 0xde, 0x8e, 0x12, 0x7a, 0x3b, 0x9e, 0x97, 0xc2, 0x5f, 0x8f, 0xb8, ++ 0x6a, 0x53, 0x57, 0x11, 0xec, 0x4e, 0x7f, 0x29, 0xcb, 0xad, 0xa7, 0xfd, ++ 0xd5, 0x91, 0x0b, 0xbd, 0x7c, 0x95, 0x16, 0xe5, 0x81, 0xbc, 0x59, 0xa5, ++ 0x79, 0x06, 0xc1, 0x0f, 0xc6, 0xb6, 0xa7, 0x88, 0x7d, 0x35, 0x8c, 0xbe, ++ 0xaa, 0xbc, 0xb6, 0x8b, 0xeb, 0x56, 0x21, 0xfc, 0x7e, 0xfd, 0x25, 0x3b, ++ 0x0b, 0xcd, 0x1f, 0x9b, 0xc0, 0xe2, 0x0d, 0xf5, 0x89, 0xf6, 0x14, 0x43, ++ 0xfb, 0x72, 0xa7, 0xdb, 0xf0, 0xfe, 0x86, 0xe4, 0xe1, 0x86, 0xf7, 0x37, ++ 0xba, 0x8a, 0x0c, 0xf5, 0x6f, 0xe5, 0x5e, 0x6d, 0x68, 0x7f, 0xb3, 0x67, ++ 0x82, 0xa1, 0x7e, 0x4b, 0xc9, 0x8d, 0x86, 0xf6, 0xd3, 0xbc, 0xd3, 0x0c, ++ 0xf5, 0xe9, 0x93, 0xe7, 0x18, 0xda, 0xcf, 0xf0, 0x55, 0x1a, 0xde, 0xcf, ++ 0x9a, 0xbd, 0xd8, 0xf0, 0x7e, 0x8e, 0xbe, 0xc2, 0x50, 0xbf, 0xbd, 0xe6, ++ 0x1e, 0x43, 0xfb, 0x3b, 0xea, 0xd7, 0x18, 0xde, 0x7b, 0x99, 0xd3, 0x82, ++ 0xfd, 0xed, 0x20, 0xec, 0x29, 0x8e, 0xf7, 0x9f, 0xc3, 0x9e, 0xe2, 0xe5, ++ 0xaa, 0x5f, 0x65, 0x3b, 0x42, 0xe9, 0x3a, 0x7e, 0xa2, 0xa9, 0xbe, 0x2f, ++ 0x7f, 0xfc, 0xa2, 0x5c, 0xa1, 0xcf, 0xdc, 0x3f, 0xdc, 0x3b, 0x1f, 0xfc, ++ 0x91, 0x26, 0xcf, 0x81, 0xa4, 0xc9, 0xf3, 0x1c, 0x77, 0xe7, 0xba, 0x44, ++ 0xde, 0x00, 0xce, 0xed, 0x93, 0x3d, 0xdb, 0x9e, 0x02, 0xbe, 0x09, 0x6f, ++ 0x17, 0xfe, 0x7e, 0x7c, 0xf4, 0xe1, 0x8b, 0x2e, 0x4e, 0xc3, 0xf6, 0xdc, ++ 0x5b, 0x6e, 0xb3, 0x70, 0xf9, 0x30, 0xfe, 0xaa, 0xc3, 0xa3, 0x32, 0x79, ++ 0xdd, 0xfc, 0x74, 0xd3, 0x6d, 0x16, 0x2e, 0x57, 0xc6, 0x5f, 0x73, 0xf8, ++ 0xc5, 0x0c, 0x5e, 0x8f, 0x7e, 0xfa, 0x55, 0x51, 0x1f, 0x79, 0xf8, 0x22, ++ 0xde, 0xaf, 0x7e, 0x7a, 0x83, 0xa8, 0x4f, 0x67, 0xa4, 0x5a, 0x24, 0x3e, ++ 0x3d, 0xee, 0x36, 0x3f, 0x9f, 0xc7, 0xf8, 0xeb, 0x33, 0x36, 0x79, 0x84, ++ 0x3f, 0xa4, 0xcf, 0x7c, 0x4b, 0x55, 0x02, 0x0f, 0xc8, 0x5b, 0x04, 0x1e, ++ 0x50, 0x06, 0x39, 0x7f, 0xa2, 0x3c, 0xcc, 0xf9, 0x13, 0xe5, 0x51, 0xce, ++ 0x9f, 0xd5, 0x59, 0x8c, 0xbd, 0xce, 0xf9, 0x13, 0xe5, 0x31, 0x6e, 0x57, ++ 0xe2, 0xf9, 0x2f, 0xb9, 0x5d, 0x89, 0xf2, 0x6d, 0x6e, 0x57, 0xa2, 0x7c, ++ 0x87, 0xdb, 0x95, 0x28, 0xdb, 0xb9, 0x5d, 0x89, 0xf2, 0x37, 0x8d, 0xb3, ++ 0xa9, 0x7c, 0xbf, 0x51, 0xa7, 0xef, 0xfe, 0xb3, 0xb1, 0x86, 0xca, 0xe3, ++ 0x8d, 0xf5, 0xf4, 0xfc, 0xc3, 0xc6, 0x06, 0x2a, 0x3f, 0x6e, 0xf4, 0xd3, ++ 0xf3, 0xcd, 0xb9, 0xca, 0x4f, 0x11, 0x24, 0x3f, 0x8b, 0x8a, 0x27, 0x2d, ++ 0x43, 0x1c, 0x0f, 0x7e, 0xb8, 0x03, 0xd6, 0xb3, 0xa1, 0x71, 0x56, 0x15, ++ 0x0f, 0x54, 0xf1, 0xbf, 0xa6, 0x7a, 0xd6, 0x11, 0x8d, 0x75, 0xda, 0x61, ++ 0x89, 0xff, 0xd4, 0xde, 0x1b, 0xd7, 0xeb, 0x5f, 0xce, 0x5a, 0xd8, 0xa7, ++ 0x21, 0xfa, 0x56, 0x6b, 0xb4, 0x77, 0x5b, 0x2e, 0xf9, 0x2f, 0x86, 0x38, ++ 0x29, 0xae, 0x23, 0x9f, 0x97, 0x6a, 0xd3, 0xd3, 0x8a, 0x79, 0xf9, 0x85, ++ 0x4b, 0x7f, 0x0a, 0xef, 0x67, 0x14, 0x57, 0xad, 0x8b, 0x73, 0xe3, 0x1c, ++ 0x48, 0xbd, 0x15, 0xfc, 0xf2, 0x81, 0xa9, 0xef, 0x73, 0xc1, 0x77, 0x4b, ++ 0x3e, 0xa9, 0x1a, 0xee, 0xfd, 0x09, 0xbe, 0x53, 0x71, 0x6c, 0x15, 0x47, ++ 0xee, 0xc9, 0x4f, 0x09, 0x89, 0x73, 0x9b, 0x42, 0xf2, 0x62, 0xe8, 0x2f, ++ 0x24, 0xbf, 0x45, 0xc5, 0x9b, 0x55, 0x3e, 0xcd, 0x75, 0x76, 0x91, 0x9f, ++ 0xa7, 0xe2, 0xc9, 0x2a, 0x6f, 0x46, 0xf5, 0x57, 0x7e, 0x89, 0x91, 0xbc, ++ 0xbb, 0x76, 0xa3, 0x85, 0xf4, 0x93, 0x18, 0x0b, 0x0b, 0xa2, 0x7f, 0x95, ++ 0x1f, 0x73, 0xad, 0xbd, 0xad, 0x08, 0xf9, 0x02, 0xd7, 0xd6, 0x3a, 0x28, ++ 0x0f, 0x6d, 0x10, 0x7f, 0x6e, 0x2b, 0xa6, 0x76, 0x5e, 0x33, 0x2f, 0xb7, ++ 0xff, 0x99, 0xb7, 0x2f, 0xec, 0x8d, 0x5f, 0x0f, 0x92, 0xf0, 0xf3, 0xf7, ++ 0x04, 0x7f, 0xf9, 0x25, 0x9d, 0xfc, 0xae, 0xd7, 0xca, 0xf8, 0x3d, 0xbe, ++ 0xb7, 0x8b, 0xf7, 0x7e, 0x7c, 0x8f, 0xdc, 0x29, 0xe8, 0x19, 0xbc, 0x24, ++ 0xbf, 0xda, 0xe3, 0xc8, 0x73, 0x2a, 0xee, 0x8d, 0xa7, 0xa3, 0x7d, 0xb4, ++ 0x68, 0x1f, 0x44, 0x7f, 0x59, 0xff, 0xc5, 0xc7, 0x8b, 0xed, 0x5d, 0x3f, ++ 0x69, 0x09, 0x6d, 0x45, 0xc8, 0xa7, 0x4a, 0x5b, 0xe6, 0xa0, 0x7c, 0xaa, ++ 0x6d, 0x13, 0x82, 0x74, 0x7e, 0x4b, 0x77, 0xeb, 0xef, 0x01, 0x9f, 0xbe, ++ 0x08, 0xe7, 0xef, 0xa3, 0x69, 0xfd, 0x64, 0xa6, 0xc1, 0x4f, 0x30, 0x4d, ++ 0xea, 0xbd, 0x5f, 0x43, 0x87, 0xe3, 0x58, 0xaf, 0x0a, 0x3f, 0x0a, 0xcf, ++ 0x8a, 0x2e, 0x0a, 0xbf, 0x21, 0x79, 0x47, 0x84, 0xd7, 0xfe, 0xe8, 0x14, ++ 0x4e, 0x9f, 0x70, 0xba, 0x28, 0x7a, 0x94, 0x5f, 0xea, 0xc5, 0x33, 0xf0, ++ 0x74, 0x39, 0x1d, 0x7a, 0xe9, 0x04, 0x7f, 0xec, 0xff, 0x2b, 0x74, 0x18, ++ 0x6d, 0x69, 0xa3, 0xf3, 0x7f, 0x11, 0xb5, 0x76, 0x0f, 0xe0, 0xfa, 0x26, ++ 0xba, 0xdc, 0xd9, 0xc5, 0x26, 0xe1, 0x3c, 0x71, 0x72, 0x86, 0x7e, 0x37, ++ 0xe8, 0x53, 0x79, 0xc9, 0xf5, 0x3a, 0xea, 0x55, 0x6c, 0xc2, 0x24, 0x6c, ++ 0x4d, 0xea, 0xbd, 0xfb, 0x1b, 0xde, 0x4f, 0xfe, 0x86, 0xf7, 0x0b, 0xfb, ++ 0x79, 0xff, 0x56, 0xa4, 0xca, 0x47, 0xf0, 0x3a, 0x8a, 0x38, 0x5d, 0x26, ++ 0x4a, 0xf9, 0xb1, 0xaa, 0x5c, 0xe0, 0x77, 0xb2, 0xdb, 0x4c, 0xf8, 0x9d, ++ 0x98, 0xbf, 0x88, 0xf4, 0x51, 0xe6, 0x10, 0x7a, 0x9d, 0x8b, 0xff, 0x0f, ++ 0xf2, 0x64, 0xd2, 0x57, 0xbe, 0xb5, 0xe8, 0x6f, 0xd2, 0x00, 0xa3, 0x7e, ++ 0xa8, 0xe2, 0xc1, 0x37, 0xc9, 0xfe, 0x26, 0x87, 0xc5, 0x81, 0x6f, 0x92, ++ 0x7a, 0xe3, 0x4d, 0x61, 0x7a, 0xe1, 0xb0, 0xe1, 0x32, 0x3e, 0xec, 0x66, ++ 0x6e, 0x61, 0xf7, 0x89, 0x73, 0xee, 0x65, 0x72, 0x9f, 0x4e, 0x95, 0x74, ++ 0xce, 0xe4, 0xc6, 0xfc, 0x78, 0xd0, 0x91, 0xe9, 0x16, 0x08, 0xad, 0xa3, ++ 0x38, 0xe7, 0x5e, 0x88, 0x73, 0xe0, 0x7e, 0xaa, 0xdf, 0xc8, 0x02, 0x54, ++ 0x7e, 0x8b, 0x05, 0x69, 0xdf, 0xba, 0x99, 0x0b, 0x38, 0xd4, 0x6f, 0x61, ++ 0x8c, 0xf2, 0x19, 0x8f, 0x44, 0x4f, 0xad, 0x58, 0xce, 0xfb, 0x9b, 0x38, ++ 0x6a, 0x62, 0x16, 0x9e, 0x87, 0x9c, 0xeb, 0x2b, 0x19, 0x3e, 0x86, 0xce, ++ 0xf5, 0xfd, 0xc1, 0x19, 0x72, 0xae, 0xef, 0x70, 0x99, 0x8b, 0xf4, 0x86, ++ 0xc3, 0xf6, 0x4c, 0xd2, 0x63, 0xb0, 0x0e, 0xac, 0x21, 0x7e, 0xb4, 0x37, ++ 0xb9, 0xdc, 0x47, 0x2a, 0xc3, 0x11, 0xbe, 0x2f, 0xa0, 0x7c, 0x8d, 0xef, ++ 0x0b, 0x59, 0x9c, 0xc9, 0xdf, 0xe0, 0xfb, 0x02, 0xea, 0x37, 0xe5, 0xae, ++ 0x61, 0xf8, 0x6e, 0x92, 0xcb, 0x98, 0x6f, 0xa2, 0xbe, 0xff, 0x96, 0xb3, ++ 0x94, 0x59, 0x46, 0xf5, 0x2f, 0x77, 0xbf, 0x55, 0xf8, 0xf2, 0x10, 0xf8, ++ 0x57, 0xde, 0x8a, 0x1f, 0x56, 0x06, 0xbf, 0xf3, 0x5b, 0xf1, 0x57, 0x95, ++ 0x61, 0xbe, 0x6f, 0xc5, 0x0f, 0x32, 0x89, 0x32, 0xc2, 0x46, 0x65, 0xc1, ++ 0x4b, 0x59, 0x7d, 0xe9, 0x59, 0x8a, 0x0f, 0x7b, 0xc7, 0x9b, 0xc4, 0x2c, ++ 0x89, 0x97, 0xe3, 0x57, 0xe1, 0x33, 0x1c, 0x8f, 0x0a, 0xbf, 0xff, 0x02, ++ 0x3e, 0xe7, 0xf7, 0x85, 0xcf, 0xbb, 0xa5, 0x3e, 0xda, 0x6d, 0x7f, 0x2f, ++ 0x36, 0x39, 0x03, 0xf1, 0x2f, 0xb1, 0xfe, 0xeb, 0x5e, 0x2a, 0x18, 0x04, ++ 0xf8, 0x3f, 0x07, 0x68, 0xc8, 0x4b, 0xb6, 0x0b, 0xbc, 0x84, 0xfb, 0x77, ++ 0x3e, 0x6b, 0x64, 0x43, 0x80, 0x5f, 0xb6, 0x3d, 0x8e, 0x9e, 0xdf, 0x2d, ++ 0x79, 0xe8, 0xda, 0x86, 0x71, 0xd4, 0xfe, 0xba, 0x86, 0x12, 0x9a, 0xdf, ++ 0x35, 0x51, 0xfa, 0xaa, 0xe1, 0x38, 0x77, 0x52, 0x1c, 0xcc, 0xe1, 0x9a, ++ 0x03, 0xfb, 0x6c, 0x5b, 0x13, 0x9d, 0xbf, 0x3d, 0xf7, 0xbc, 0xd9, 0x03, ++ 0xfd, 0xbb, 0xd6, 0xec, 0xda, 0xe4, 0xc1, 0x5a, 0x7f, 0x4b, 0x9c, 0x97, ++ 0x63, 0x5f, 0x1d, 0x49, 0x47, 0xbc, 0x8d, 0x6d, 0xef, 0x3b, 0x6f, 0xb7, ++ 0xd6, 0xae, 0xf0, 0xe6, 0x27, 0xf8, 0x8b, 0x32, 0xbc, 0x77, 0x8b, 0xfd, ++ 0x4f, 0x9c, 0x23, 0x56, 0xfb, 0xef, 0x90, 0x08, 0x91, 0xef, 0xaa, 0xce, ++ 0xb3, 0xf6, 0xb7, 0x1f, 0x8f, 0x8d, 0x12, 0x72, 0x65, 0x48, 0x84, 0x90, ++ 0x83, 0x8a, 0x4e, 0xfc, 0x3b, 0xaa, 0xa7, 0xf2, 0x7e, 0xc6, 0x72, 0xb9, ++ 0x91, 0xfa, 0x50, 0x14, 0xe9, 0xdf, 0x25, 0x09, 0xde, 0x07, 0x80, 0x4f, ++ 0x56, 0xc6, 0x0c, 0xfa, 0xab, 0xb2, 0xab, 0xbb, 0x07, 0x98, 0x29, 0x6e, ++ 0xbd, 0x12, 0xf1, 0xcb, 0x01, 0xb0, 0x6b, 0xec, 0xe4, 0xcf, 0xb9, 0x8e, ++ 0xe5, 0xdc, 0x02, 0x3d, 0xb8, 0x0c, 0xf6, 0x26, 0xc7, 0x43, 0xf9, 0x9b, ++ 0x55, 0x74, 0x4f, 0x81, 0x3a, 0x97, 0x11, 0x91, 0x6c, 0x32, 0xde, 0x6f, ++ 0xe3, 0x8a, 0x32, 0xdc, 0xd7, 0x12, 0x9d, 0x9b, 0x60, 0xa8, 0xc7, 0x78, ++ 0x06, 0x1b, 0xda, 0xc7, 0x95, 0x64, 0x18, 0xde, 0xc7, 0x7b, 0x47, 0x18, ++ 0xde, 0x27, 0x4e, 0x2e, 0x36, 0xd4, 0x07, 0xfa, 0xc6, 0x19, 0xda, 0x0f, ++ 0x9a, 0x5d, 0x6a, 0xa8, 0xa7, 0xe8, 0x37, 0x19, 0xda, 0xa7, 0xd6, 0xdc, ++ 0x6a, 0xa8, 0x2b, 0xf9, 0x92, 0x2a, 0x1e, 0xb1, 0xb4, 0xfa, 0xb9, 0x86, ++ 0xef, 0x87, 0x36, 0xcc, 0x37, 0xb4, 0x77, 0xfb, 0x97, 0x18, 0xef, 0x9f, ++ 0xf1, 0x7b, 0xdb, 0x73, 0x93, 0x20, 0x97, 0xc4, 0x5f, 0xe6, 0xc6, 0x95, ++ 0x86, 0xf7, 0x3f, 0x8a, 0x15, 0xe7, 0x0e, 0x26, 0x3b, 0x16, 0xd2, 0x7d, ++ 0x12, 0xd9, 0xcd, 0xdf, 0x31, 0x8e, 0x6f, 0xfe, 0xca, 0x0c, 0xfc, 0xa6, ++ 0xc6, 0x69, 0xe2, 0xbe, 0x00, 0x97, 0x90, 0x7f, 0x7e, 0xfe, 0x3f, 0xd0, ++ 0xb5, 0x3c, 0xd9, 0x28, 0x0f, 0x27, 0x3a, 0x8d, 0xf6, 0x30, 0xd7, 0xd7, ++ 0x34, 0xec, 0xbf, 0xa9, 0xf5, 0x16, 0xc3, 0xf3, 0x37, 0x86, 0x4b, 0xbb, ++ 0xb7, 0x90, 0x15, 0x92, 0xfc, 0xfb, 0x27, 0xe9, 0x1c, 0x8e, 0x97, 0xee, ++ 0x32, 0xe6, 0x09, 0xa2, 0x3d, 0xf4, 0x15, 0x5e, 0xbf, 0x4e, 0x1f, 0xf1, ++ 0x10, 0xfc, 0x0e, 0x65, 0x03, 0xac, 0x9e, 0x00, 0x13, 0xfe, 0xee, 0xd0, ++ 0x79, 0xc1, 0xdf, 0x1d, 0x8a, 0x07, 0xf8, 0xbb, 0x43, 0xeb, 0xf0, 0x77, ++ 0x1b, 0xef, 0x6d, 0x32, 0xd2, 0x1d, 0xfe, 0xee, 0xd0, 0xf7, 0xa3, 0x8e, ++ 0x19, 0xe9, 0x3e, 0xa6, 0xdd, 0x48, 0xf7, 0xab, 0x8e, 0x1b, 0xe9, 0xae, ++ 0xf8, 0x31, 0x9c, 0x3e, 0x57, 0x77, 0x18, 0xf9, 0x21, 0x9c, 0x3e, 0xd7, ++ 0x9c, 0x0e, 0xe3, 0x0f, 0x49, 0x8f, 0xd9, 0xfc, 0x7f, 0xff, 0x10, 0xe7, ++ 0x98, 0x89, 0x5e, 0x93, 0x1c, 0x1a, 0x7b, 0xcc, 0xfd, 0xaf, 0xd3, 0xe7, ++ 0x6f, 0x61, 0xf4, 0xe9, 0xa1, 0x87, 0xc3, 0x4e, 0xfa, 0xe2, 0x75, 0xc1, ++ 0xbc, 0x38, 0xd4, 0xcb, 0xb1, 0xce, 0xa0, 0x37, 0xc8, 0xf9, 0xdc, 0x90, ++ 0x57, 0xef, 0xc8, 0x80, 0x9c, 0xb4, 0xe9, 0xd6, 0x11, 0x03, 0x7b, 0xf9, ++ 0xa7, 0x29, 0x45, 0xf0, 0x4f, 0xf7, 0xb1, 0x17, 0x23, 0x21, 0xf7, 0x22, ++ 0x46, 0x18, 0xfb, 0x3f, 0x9f, 0xaa, 0x47, 0xa1, 0xfd, 0xec, 0xc4, 0x8b, ++ 0xe9, 0x36, 0xf0, 0x43, 0x97, 0xb8, 0xaf, 0x6f, 0xbe, 0x94, 0x9f, 0x2a, ++ 0x9f, 0x90, 0xdb, 0xbb, 0xe2, 0x3c, 0xdd, 0x77, 0xcc, 0x14, 0xdf, 0x3f, ++ 0x61, 0x6a, 0xa6, 0xfb, 0x92, 0x0e, 0x3b, 0xf5, 0x04, 0x7c, 0x7f, 0x67, ++ 0x7e, 0xbd, 0x86, 0xf8, 0x41, 0x32, 0xf3, 0xed, 0x59, 0xc8, 0xc7, 0x9b, ++ 0xf7, 0x8b, 0x08, 0x8a, 0x27, 0xcc, 0x1b, 0x2a, 0xce, 0x75, 0xb2, 0xfc, ++ 0x0e, 0xca, 0xb3, 0x57, 0x72, 0x6e, 0x5e, 0xaa, 0xc8, 0x63, 0x19, 0x3c, ++ 0x42, 0xc6, 0x27, 0x3d, 0x22, 0x9f, 0x25, 0x6d, 0x84, 0xd0, 0x0b, 0x63, ++ 0x3c, 0x4e, 0xca, 0x7b, 0xad, 0xcc, 0x17, 0xe7, 0x08, 0xb8, 0x59, 0x90, ++ 0x3e, 0xaf, 0x00, 0xf8, 0x78, 0x3b, 0x12, 0xf7, 0x16, 0x76, 0xb7, 0x08, ++ 0xff, 0x7d, 0x87, 0x55, 0x9c, 0x2f, 0xf5, 0x73, 0x3e, 0x45, 0x5c, 0x0c, ++ 0x7a, 0x22, 0xf4, 0xb8, 0x34, 0xa9, 0x47, 0x35, 0xfd, 0xce, 0x6e, 0x07, ++ 0xfc, 0xc3, 0xb6, 0x32, 0xc3, 0xbe, 0x38, 0x3c, 0x60, 0x37, 0xe4, 0x5d, ++ 0xe6, 0xed, 0x72, 0x1a, 0xea, 0x05, 0x6d, 0xc9, 0x86, 0xf6, 0x23, 0x0f, ++ 0xb8, 0x0c, 0xef, 0x8b, 0x82, 0xb9, 0x86, 0xf7, 0xa3, 0x8e, 0x79, 0x0c, ++ 0xf5, 0x31, 0xed, 0x25, 0x86, 0xf6, 0x57, 0x1d, 0xf7, 0x1a, 0xea, 0x57, ++ 0x77, 0x4c, 0x36, 0xb4, 0xbf, 0xe6, 0xb4, 0xcf, 0x50, 0x4f, 0x65, 0x5d, ++ 0x8f, 0x02, 0xbf, 0x43, 0x35, 0x61, 0x8f, 0xce, 0x18, 0x21, 0xf2, 0x78, ++ 0xf8, 0x1a, 0xa5, 0x78, 0xd2, 0xbc, 0x0d, 0xf1, 0xe2, 0xfc, 0xa0, 0xb4, ++ 0x53, 0x95, 0x1e, 0xac, 0xf2, 0x71, 0x75, 0xc9, 0xd7, 0xe1, 0xfa, 0xf4, ++ 0x50, 0x9b, 0x4e, 0xf9, 0xbd, 0x4d, 0x29, 0xcc, 0x43, 0xe7, 0x00, 0xec, ++ 0xd2, 0x3e, 0x61, 0x46, 0x3d, 0x5b, 0x97, 0xf9, 0xb4, 0x4a, 0x1f, 0x65, ++ 0x7e, 0x63, 0x3e, 0xad, 0xca, 0xa3, 0xed, 0xd1, 0xc7, 0xa5, 0xfe, 0xad, ++ 0xf4, 0xe1, 0x90, 0x3c, 0x5a, 0x6f, 0x68, 0x1e, 0xed, 0x3c, 0x79, 0xce, ++ 0x37, 0x7c, 0xdf, 0xab, 0x1c, 0x21, 0xcf, 0xf3, 0x85, 0xc1, 0x3f, 0xd4, ++ 0x26, 0xe6, 0xdb, 0x74, 0x8f, 0x8d, 0xce, 0x2d, 0x28, 0xb8, 0xc2, 0xe1, ++ 0x39, 0x2b, 0xf3, 0x3b, 0x77, 0xd8, 0xfb, 0x3e, 0x3f, 0xb2, 0x7c, 0x84, ++ 0xb0, 0x63, 0x7f, 0x96, 0xe9, 0x5b, 0x34, 0x82, 0x97, 0x4f, 0x40, 0x3c, ++ 0x65, 0xf6, 0x35, 0x9e, 0xa7, 0xc3, 0xcf, 0xf9, 0xab, 0xe9, 0x7b, 0x36, ++ 0xcf, 0x7d, 0xae, 0x6f, 0x1e, 0x6f, 0xde, 0x48, 0x31, 0x9f, 0x0a, 0x93, ++ 0xe9, 0xce, 0x69, 0xf9, 0x94, 0xb7, 0x34, 0xfb, 0x85, 0x90, 0xf1, 0x1b, ++ 0x25, 0x7f, 0x57, 0xe7, 0x6b, 0x7d, 0xce, 0x6f, 0x5e, 0x9c, 0xc8, 0x2b, ++ 0x62, 0x71, 0x36, 0x17, 0xf8, 0xb7, 0xff, 0xf1, 0x04, 0x3e, 0x93, 0x6d, ++ 0x6c, 0x2d, 0x9d, 0x73, 0x91, 0x79, 0xe7, 0x77, 0x6c, 0x6a, 0x7b, 0x10, ++ 0x2e, 0xf2, 0x0a, 0x5b, 0xb3, 0x55, 0xdc, 0x5f, 0x16, 0xb0, 0x82, 0x1f, ++ 0xa6, 0x94, 0x72, 0xfd, 0xa9, 0x88, 0xdb, 0xc9, 0xdb, 0xff, 0xeb, 0x87, ++ 0x0e, 0xae, 0xe7, 0x3c, 0xd1, 0x60, 0x21, 0x3f, 0xc4, 0xfa, 0x67, 0xca, ++ 0x67, 0x70, 0xcd, 0xab, 0xe7, 0x1c, 0xc1, 0x50, 0x6e, 0x5f, 0x80, 0x3f, ++ 0xa0, 0xab, 0xc0, 0x2e, 0xf9, 0x4b, 0x9e, 0xc8, 0x9b, 0xfd, 0xc9, 0x08, ++ 0x46, 0x65, 0xb9, 0xf9, 0xab, 0x9e, 0xfc, 0x6f, 0xf2, 0xa7, 0x33, 0x26, ++ 0xf7, 0x07, 0x61, 0xb7, 0xf4, 0xc1, 0x6f, 0xc4, 0x87, 0x6a, 0x1e, 0xff, ++ 0xee, 0x3c, 0xf0, 0x70, 0x3c, 0x29, 0xbb, 0x90, 0xc9, 0xbc, 0xbb, 0x2c, ++ 0x09, 0x97, 0xc2, 0x5f, 0x8f, 0x1d, 0x2f, 0xf1, 0xa7, 0xf2, 0xf1, 0x5d, ++ 0x2b, 0xac, 0xbe, 0xa7, 0x1c, 0x94, 0xd7, 0x3f, 0x19, 0xf9, 0x4c, 0x8a, ++ 0x7e, 0x31, 0xf9, 0x82, 0x2f, 0x7f, 0x27, 0xf1, 0x81, 0x76, 0x90, 0x47, ++ 0xfd, 0xb5, 0x2b, 0x37, 0xe7, 0xc7, 0xc1, 0x5f, 0xdb, 0xcd, 0x5c, 0x71, ++ 0xce, 0xaf, 0xf1, 0x47, 0xfe, 0xbb, 0xf0, 0xa2, 0xf0, 0xdf, 0xdf, 0xf9, ++ 0x9e, 0xfe, 0xe4, 0xc3, 0x65, 0x72, 0xa1, 0x9f, 0xf3, 0x3e, 0xfd, 0xf1, ++ 0x27, 0xfd, 0xfd, 0x13, 0xe7, 0x7e, 0x42, 0xe4, 0x83, 0xc8, 0x2f, 0x91, ++ 0xf4, 0x08, 0x64, 0x99, 0x28, 0x9e, 0xbb, 0x21, 0xc6, 0xb8, 0x8e, 0xed, ++ 0x79, 0x62, 0x5f, 0x78, 0x4e, 0xed, 0x17, 0x7e, 0x6e, 0x4f, 0x1a, 0xe5, ++ 0x04, 0x83, 0x7f, 0xb9, 0x69, 0x9d, 0x59, 0xca, 0x09, 0xb1, 0x6f, 0x63, ++ 0xff, 0xc4, 0xf3, 0x05, 0xeb, 0xac, 0xa4, 0xcf, 0xb0, 0x06, 0x91, 0x8f, ++ 0x5c, 0x23, 0x65, 0x31, 0x63, 0xbe, 0xa4, 0x71, 0xa3, 0x11, 0x8f, 0xb5, ++ 0xd2, 0x7d, 0x56, 0xd7, 0x79, 0x19, 0xe9, 0x3b, 0xf3, 0x1d, 0xb6, 0x40, ++ 0x2b, 0x6f, 0x5f, 0xe9, 0x0f, 0xdf, 0xb7, 0xbd, 0xf4, 0x3d, 0xc5, 0x6b, ++ 0x5c, 0xb8, 0xb7, 0xc4, 0xb3, 0x1e, 0xfe, 0xf7, 0xaa, 0x8d, 0xc6, 0x76, ++ 0x8b, 0x1c, 0xe2, 0x5e, 0xaf, 0x05, 0x61, 0x76, 0xe9, 0x22, 0x69, 0x97, ++ 0x2e, 0x0a, 0xb3, 0x4b, 0xff, 0x3a, 0x42, 0xda, 0xa5, 0x1e, 0xe6, 0x21, ++ 0xbd, 0x4c, 0xc6, 0x9f, 0x15, 0x9c, 0x3d, 0x7c, 0x15, 0xc8, 0xa4, 0xbc, ++ 0x60, 0xd8, 0xa9, 0x66, 0xe1, 0x2f, 0xa1, 0x7c, 0x25, 0x85, 0x27, 0x17, ++ 0xe2, 0x0b, 0x21, 0xf7, 0x68, 0x72, 0x7c, 0x46, 0xe5, 0x62, 0xdf, 0x5e, ++ 0x6b, 0xe9, 0x33, 0x8f, 0xac, 0x07, 0x9f, 0xfd, 0xc4, 0xc9, 0xcf, 0x22, ++ 0x4e, 0xee, 0xc2, 0xfa, 0xef, 0xa6, 0xf3, 0x3f, 0xdd, 0x7b, 0x23, 0x45, ++ 0x1c, 0x4d, 0xc5, 0x2f, 0x64, 0xfb, 0xb3, 0xfe, 0x8b, 0xf4, 0x1e, 0xed, ++ 0xd1, 0xdb, 0xb9, 0xa2, 0xf6, 0x42, 0xc4, 0x91, 0x7a, 0xe2, 0x1d, 0x61, ++ 0x71, 0x93, 0x6e, 0x87, 0x29, 0xb6, 0x04, 0xfd, 0xed, 0x16, 0xf7, 0x2f, ++ 0xa8, 0x3c, 0x80, 0x25, 0x7f, 0x0d, 0x14, 0x3a, 0x43, 0xe2, 0x9c, 0x7a, ++ 0x87, 0xc9, 0x90, 0x77, 0x11, 0x5e, 0xea, 0x6b, 0xf6, 0x51, 0x5e, 0x40, ++ 0xab, 0x45, 0xcf, 0xcc, 0x43, 0x3e, 0xb2, 0xc5, 0x63, 0xc7, 0x7d, 0x91, ++ 0xf7, 0x3b, 0x0e, 0x27, 0xe1, 0xbc, 0xf6, 0x14, 0xe9, 0xaf, 0x09, 0x87, ++ 0xb7, 0x47, 0xaf, 0x1a, 0xaf, 0x89, 0x38, 0xa1, 0x5f, 0xe8, 0xb9, 0xdd, ++ 0x93, 0x35, 0xd2, 0x73, 0xb9, 0x5c, 0x64, 0x58, 0x47, 0x2a, 0x9e, 0x3d, ++ 0x8d, 0x05, 0x07, 0xa0, 0x54, 0xf1, 0x03, 0x7d, 0x63, 0x09, 0xe1, 0x59, ++ 0xc5, 0x0f, 0x2a, 0x83, 0x25, 0x04, 0xe7, 0x8c, 0xa6, 0x45, 0x56, 0x5c, ++ 0xd9, 0xd7, 0xf1, 0xe8, 0xea, 0xf2, 0x28, 0x57, 0x6f, 0x5c, 0xa1, 0x23, ++ 0x4d, 0xe4, 0xa3, 0xf4, 0x17, 0x5f, 0x98, 0x7e, 0xc9, 0x43, 0xfd, 0xdd, ++ 0x76, 0x69, 0x1c, 0xf5, 0x53, 0x9a, 0xe7, 0x16, 0xe7, 0xf5, 0xd7, 0x3e, ++ 0xb8, 0x02, 0x7c, 0x34, 0x62, 0x17, 0xb3, 0x62, 0x9e, 0x1d, 0x61, 0xf9, ++ 0xd8, 0xaa, 0x7c, 0x21, 0x4f, 0xc8, 0x9f, 0x77, 0xf3, 0x94, 0xdc, 0x96, ++ 0x79, 0x2e, 0x6b, 0x34, 0xa1, 0xc7, 0x6b, 0x4c, 0xe5, 0xbd, 0x90, 0xdc, ++ 0x56, 0xf5, 0x8b, 0xcd, 0xb2, 0x5e, 0x2e, 0xea, 0xab, 0xd6, 0x89, 0x7a, ++ 0x87, 0xbc, 0xc7, 0x68, 0xa7, 0xf4, 0x37, 0x60, 0x9e, 0x28, 0x31, 0x1f, ++ 0xd8, 0xc5, 0xbb, 0xa5, 0x3f, 0x02, 0xf3, 0x40, 0x89, 0x79, 0xe0, 0x39, ++ 0xe4, 0x14, 0xea, 0x90, 0x53, 0xa8, 0x43, 0x4e, 0xa1, 0x0e, 0x39, 0x85, ++ 0x12, 0x72, 0x0a, 0xcf, 0xe7, 0x33, 0x5f, 0x7a, 0x91, 0x59, 0xc4, 0x41, ++ 0xca, 0x42, 0xd6, 0x0d, 0xe2, 0x20, 0x65, 0x21, 0x7a, 0x10, 0xe2, 0x20, ++ 0xa1, 0x75, 0xc4, 0x41, 0x42, 0xdb, 0x23, 0x0e, 0x12, 0xfa, 0x1e, 0x71, ++ 0x90, 0xd0, 0xf7, 0x88, 0x83, 0x84, 0xd6, 0x11, 0x07, 0x09, 0x6d, 0x8f, ++ 0x38, 0x48, 0x68, 0x9d, 0x95, 0xdc, 0xd8, 0x5b, 0x87, 0x5c, 0xf3, 0x4e, ++ 0x33, 0xd4, 0xa7, 0x73, 0x7d, 0xbf, 0x2c, 0x64, 0xdd, 0x22, 0x0e, 0x12, ++ 0xda, 0x3f, 0xe2, 0x20, 0x86, 0xfe, 0xf4, 0x15, 0x86, 0xef, 0x6f, 0x67, ++ 0x0d, 0x86, 0xef, 0x11, 0x07, 0x09, 0x6d, 0x7f, 0x67, 0x83, 0x66, 0x88, ++ 0x93, 0xdc, 0x29, 0xcf, 0xa5, 0x57, 0x6d, 0x4d, 0x20, 0xfe, 0xb8, 0xc9, ++ 0xed, 0x6b, 0xcc, 0xe3, 0xf4, 0xfd, 0x43, 0xf4, 0xdf, 0xef, 0xb6, 0xc2, ++ 0x0e, 0x34, 0x1f, 0x5c, 0x4c, 0xf6, 0x59, 0x5d, 0x94, 0x47, 0xd0, 0xb9, ++ 0x79, 0xb2, 0xa0, 0xbb, 0x89, 0x09, 0x3a, 0x77, 0xcd, 0x21, 0x3a, 0xaf, ++ 0xb6, 0x89, 0x7a, 0xb9, 0xc8, 0x8b, 0xed, 0x2b, 0xde, 0x50, 0x96, 0x25, ++ 0xe2, 0x0d, 0x28, 0x11, 0x6f, 0x40, 0x89, 0x78, 0x03, 0x4a, 0xc4, 0x1b, ++ 0x70, 0x1f, 0x36, 0xe2, 0x0d, 0x28, 0x11, 0x6f, 0xc0, 0x73, 0xc4, 0x1b, ++ 0x50, 0x22, 0xde, 0x80, 0x12, 0xf1, 0x06, 0x94, 0x88, 0x37, 0xa0, 0x44, ++ 0xbc, 0x01, 0x25, 0xe2, 0x0d, 0xf8, 0x0e, 0xf1, 0x06, 0x94, 0x88, 0x37, ++ 0xe0, 0x39, 0xe2, 0x0d, 0x28, 0x11, 0x6f, 0xc0, 0xf3, 0x13, 0x88, 0x7b, ++ 0x64, 0xf5, 0xc2, 0x05, 0xbd, 0x3d, 0xcb, 0x60, 0x3f, 0x72, 0x3e, 0x34, ++ 0xd8, 0x8f, 0x4e, 0x43, 0x1d, 0x7a, 0x7b, 0x68, 0x7b, 0xe8, 0xed, 0xa1, ++ 0xef, 0xa1, 0xb7, 0x87, 0xbe, 0x87, 0xde, 0x1e, 0x5a, 0x87, 0xde, 0x1e, ++ 0xda, 0x1e, 0x7a, 0x7b, 0x68, 0xfd, 0xd0, 0x08, 0x17, 0xad, 0x33, 0xe8, ++ 0xef, 0xa1, 0xdf, 0x41, 0x7f, 0x0f, 0xad, 0x17, 0x34, 0xfb, 0x5f, 0x83, ++ 0x8f, 0xe9, 0xe6, 0x6d, 0xe7, 0x8f, 0xa2, 0xec, 0x88, 0xd1, 0x9e, 0xd0, ++ 0xb8, 0x28, 0x08, 0xe6, 0x7d, 0x3c, 0x03, 0x71, 0xa4, 0x8e, 0x48, 0x2d, ++ 0x3d, 0x9e, 0x2f, 0x79, 0xeb, 0x9a, 0xce, 0x19, 0x65, 0xbc, 0xae, 0xcb, ++ 0xfc, 0xb2, 0x42, 0xd6, 0x45, 0xf7, 0x3b, 0xeb, 0xf2, 0xde, 0x1a, 0x3d, ++ 0xc8, 0x28, 0x1f, 0xb6, 0xe0, 0x2f, 0xc9, 0x42, 0x2e, 0xc8, 0x38, 0x24, ++ 0xfd, 0x71, 0xba, 0x17, 0xed, 0x65, 0x64, 0x07, 0x94, 0xca, 0xf3, 0x83, ++ 0xea, 0x7b, 0x0f, 0x73, 0x9a, 0x51, 0xaa, 0xf6, 0xbd, 0xf5, 0xbe, 0xdb, ++ 0x85, 0x8f, 0xaf, 0xda, 0x91, 0xbc, 0x0c, 0x81, 0x83, 0x1b, 0x88, 0x45, ++ 0xc8, 0x83, 0x28, 0x5a, 0xed, 0x28, 0x46, 0x1e, 0xf7, 0x4e, 0x93, 0x26, ++ 0xf2, 0x20, 0xef, 0x13, 0x79, 0xa8, 0xe1, 0x7c, 0xf5, 0x27, 0xb9, 0x6f, ++ 0xef, 0x34, 0xed, 0x39, 0x1c, 0x85, 0xbc, 0x96, 0x4a, 0x8d, 0xee, 0x8b, ++ 0xcf, 0xb1, 0xb0, 0x63, 0xb8, 0xc7, 0xbb, 0xa0, 0xb9, 0xbe, 0x18, 0xfa, ++ 0xc2, 0xc7, 0x79, 0x3d, 0xf7, 0xcb, 0x8f, 0x43, 0x5e, 0x8c, 0x82, 0x5b, ++ 0xf9, 0x01, 0xb9, 0x9c, 0xa0, 0x73, 0x55, 0xe3, 0xbb, 0x98, 0xad, 0x3a, ++ 0x1f, 0xf7, 0x89, 0x31, 0xdb, 0x02, 0xc8, 0x77, 0x9b, 0xd0, 0x13, 0xf0, ++ 0x1d, 0xec, 0xc7, 0x3c, 0xbf, 0xe6, 0x7d, 0x2a, 0x84, 0xbf, 0x3f, 0xcd, ++ 0x13, 0x7a, 0xbf, 0xee, 0x5f, 0x31, 0xae, 0x9a, 0x3f, 0xcf, 0xdb, 0x5d, ++ 0x3f, 0x0e, 0xe7, 0xb5, 0xa6, 0x44, 0x89, 0xef, 0x7e, 0xf2, 0x64, 0x2c, ++ 0xe1, 0x71, 0xea, 0x5a, 0xed, 0x29, 0x9c, 0x8b, 0x1b, 0xbf, 0x9b, 0x79, ++ 0x71, 0xfe, 0xf2, 0x82, 0x84, 0x3b, 0x6f, 0xb7, 0xd3, 0x56, 0x4d, 0xe3, ++ 0x3a, 0xe9, 0x9c, 0x57, 0x8f, 0xbd, 0xb2, 0x2d, 0x9d, 0xce, 0xa5, 0x55, ++ 0xb2, 0x8e, 0xb2, 0x64, 0xf2, 0xe5, 0x6b, 0x74, 0x8f, 0xb9, 0xc2, 0x1b, ++ 0x9f, 0xdf, 0x51, 0xcc, 0x8f, 0x8b, 0xf8, 0x63, 0x56, 0xd2, 0x47, 0xc5, ++ 0x79, 0x91, 0x28, 0x79, 0x5e, 0x44, 0x9d, 0x13, 0x71, 0x5b, 0x7c, 0x7b, ++ 0x60, 0x8f, 0xa8, 0xf3, 0x22, 0xd7, 0x8e, 0x8e, 0x2f, 0x47, 0xbe, 0x16, ++ 0x3b, 0x28, 0xee, 0xdd, 0xbb, 0x79, 0x74, 0xe5, 0xba, 0x81, 0xbc, 0x7f, ++ 0x3d, 0x20, 0xee, 0xdd, 0xbb, 0xf6, 0x4f, 0xf5, 0xaf, 0x51, 0x7d, 0xbb, ++ 0xb8, 0x77, 0x8f, 0xd8, 0x60, 0x2c, 0x8d, 0x43, 0xfb, 0xda, 0x30, 0xbf, ++ 0x46, 0xf7, 0x3d, 0x4c, 0xf5, 0xb7, 0x9a, 0x06, 0xb8, 0x70, 0x7e, 0x74, ++ 0x8d, 0x35, 0x09, 0xed, 0x77, 0x33, 0x0f, 0xd4, 0x9f, 0x61, 0x4c, 0x9c, ++ 0x83, 0x54, 0xf0, 0xe5, 0xb3, 0x76, 0x13, 0xee, 0x1d, 0xe7, 0x5b, 0xcc, ++ 0x91, 0xc4, 0x10, 0x3e, 0xe2, 0x9c, 0x7a, 0x1b, 0xe8, 0x5e, 0xe4, 0xb1, ++ 0xd2, 0x7d, 0x10, 0xd3, 0x2c, 0x4e, 0x2b, 0xe4, 0x46, 0xf8, 0x3e, 0x7e, ++ 0x79, 0x3e, 0x5d, 0x98, 0x9e, 0x10, 0x96, 0x0f, 0xd1, 0xb4, 0xfa, 0x78, ++ 0xba, 0x39, 0x03, 0xfe, 0x24, 0x93, 0x27, 0x08, 0xb9, 0xb5, 0x2f, 0x9a, ++ 0xf4, 0x05, 0xa5, 0xef, 0x54, 0xca, 0x3c, 0xa8, 0x8b, 0x6b, 0x5f, 0xa3, ++ 0xfb, 0xac, 0x2b, 0xf7, 0x08, 0xfd, 0x40, 0xe7, 0x72, 0x00, 0xf2, 0x4f, ++ 0xe5, 0x47, 0xd4, 0x65, 0x06, 0xd2, 0x4d, 0xd0, 0x17, 0x06, 0xb7, 0x16, ++ 0x26, 0x98, 0xc5, 0xfe, 0x9f, 0xcf, 0xf1, 0x78, 0xc6, 0xff, 0xe2, 0xcc, ++ 0x12, 0x17, 0xce, 0x31, 0xbe, 0x46, 0xf9, 0xfa, 0x95, 0xeb, 0xc6, 0xc4, ++ 0x89, 0xf3, 0x3a, 0x22, 0xfe, 0x50, 0x2d, 0xf1, 0x54, 0x2d, 0xf3, 0x5f, ++ 0x58, 0xbe, 0x33, 0x09, 0x7a, 0xa7, 0xba, 0xc7, 0xb4, 0xdc, 0x3c, 0x3e, ++ 0x8e, 0xce, 0xbb, 0x35, 0x0b, 0x7d, 0x4e, 0xf9, 0x77, 0x2a, 0x7f, 0x35, ++ 0xea, 0x75, 0xd0, 0xb9, 0xf2, 0x71, 0x79, 0x1f, 0xc8, 0xc6, 0x4a, 0x3a, ++ 0x07, 0x14, 0x9e, 0x87, 0xa2, 0xf4, 0x43, 0x75, 0xdf, 0xc9, 0xe2, 0xb5, ++ 0x56, 0xca, 0x6f, 0x59, 0x1c, 0xa6, 0x07, 0x2e, 0x95, 0x7a, 0xe0, 0xd2, ++ 0x30, 0x3d, 0xf0, 0x9a, 0x7c, 0xe9, 0x9f, 0x51, 0x7a, 0xa0, 0xba, 0x9f, ++ 0x4e, 0xb6, 0xa9, 0xfc, 0xd5, 0x91, 0x19, 0xa4, 0xa7, 0xd4, 0x8b, 0xfb, ++ 0xf8, 0x2a, 0xd6, 0x08, 0xbd, 0x85, 0xed, 0x11, 0xf7, 0xd8, 0x57, 0xac, ++ 0x99, 0x68, 0xc2, 0xbd, 0x15, 0x15, 0xfb, 0xbc, 0x1e, 0xad, 0x0f, 0xfe, ++ 0x78, 0x57, 0xea, 0x2f, 0x53, 0x30, 0x68, 0x22, 0xf2, 0x7c, 0x06, 0x53, ++ 0x39, 0xf3, 0x52, 0x32, 0x95, 0xb3, 0x2e, 0xe5, 0x92, 0x1c, 0xc0, 0x59, ++ 0x0c, 0xd0, 0xbf, 0xe3, 0x65, 0x46, 0xfa, 0xf4, 0x7b, 0x52, 0x5f, 0x99, ++ 0x81, 0x3c, 0x3f, 0x9c, 0x8f, 0xf3, 0x47, 0xc8, 0x7c, 0x3e, 0x46, 0xfa, ++ 0x52, 0x11, 0x73, 0x96, 0x43, 0x6e, 0x8c, 0xf0, 0x6a, 0x47, 0xe0, 0xbe, ++ 0x9e, 0x62, 0xd5, 0xd7, 0x21, 0x8f, 0x70, 0x4a, 0x2b, 0xa3, 0xf3, 0x30, ++ 0x37, 0x43, 0xaf, 0xe1, 0x2f, 0x66, 0x43, 0xcf, 0x19, 0x05, 0x3e, 0x77, ++ 0x97, 0xd3, 0xb9, 0x80, 0xc9, 0x1a, 0x9d, 0xaf, 0xb8, 0x79, 0xf4, 0x0a, ++ 0xc9, 0xd7, 0x9c, 0xcf, 0x19, 0xf8, 0xdc, 0x2f, 0xf9, 0xd6, 0x47, 0xf5, ++ 0x9e, 0xfd, 0x40, 0xf2, 0xb7, 0xee, 0xef, 0xb4, 0xd0, 0xbd, 0xac, 0x7e, ++ 0xcd, 0x86, 0x7b, 0xd9, 0x74, 0x69, 0xcf, 0x2a, 0xfe, 0x0d, 0xe7, 0xf3, ++ 0x79, 0xf2, 0xf7, 0x26, 0x98, 0x43, 0xf8, 0x99, 0x7a, 0xfc, 0x50, 0x00, ++ 0x16, 0x97, 0xab, 0xf8, 0xc7, 0xce, 0x84, 0xbe, 0x38, 0x0f, 0xbe, 0xc1, ++ 0xc1, 0x92, 0x90, 0x76, 0xd8, 0x75, 0xe2, 0xfd, 0xdd, 0xbb, 0xc7, 0xce, ++ 0x5c, 0x8b, 0x1c, 0xeb, 0xff, 0x4b, 0xff, 0x44, 0x85, 0xfa, 0x1d, 0x06, ++ 0xae, 0x67, 0x41, 0x9e, 0xde, 0x71, 0x57, 0x91, 0x6d, 0x7e, 0x88, 0x5c, ++ 0x29, 0x2d, 0x2c, 0x6d, 0x29, 0x18, 0xd8, 0x4b, 0xf7, 0xf9, 0x3d, 0xe7, ++ 0xc6, 0xf2, 0x07, 0x41, 0xff, 0x5f, 0x79, 0x7f, 0xf6, 0xa0, 0xaf, 0x3b, ++ 0xbf, 0x58, 0xc5, 0xf1, 0x8c, 0xf5, 0x31, 0x2f, 0xae, 0xe3, 0x6e, 0xdc, ++ 0x8c, 0xfb, 0x70, 0x3e, 0xf3, 0x96, 0x25, 0xe3, 0x3e, 0x66, 0xa6, 0x2e, ++ 0x91, 0x09, 0x22, 0x5f, 0x6d, 0xae, 0xac, 0x1f, 0xde, 0x7d, 0xe7, 0x7f, ++ 0x6e, 0x74, 0x10, 0x7e, 0xa8, 0xbe, 0x39, 0xbf, 0x7c, 0xa6, 0x9f, 0xd6, ++ 0x8b, 0x90, 0x57, 0xb7, 0x43, 0x5e, 0x99, 0x21, 0xa7, 0xf4, 0x87, 0xf2, ++ 0x91, 0x1f, 0x64, 0xef, 0x98, 0x04, 0x7a, 0x44, 0xe7, 0x77, 0xc9, 0xf3, ++ 0xf0, 0xf2, 0x1c, 0x6b, 0x98, 0x3f, 0xe2, 0x70, 0xbe, 0xa0, 0x43, 0xb8, ++ 0x5f, 0xa2, 0x2a, 0x5f, 0xc8, 0x71, 0x66, 0x71, 0xa5, 0xdf, 0x4e, 0xe7, ++ 0x54, 0x5d, 0xe4, 0xd7, 0x53, 0xf0, 0x7f, 0x62, 0x35, 0x9e, 0x1b, 0x54, ++ 0xe5, 0xcf, 0xa4, 0x7d, 0xfd, 0xef, 0xca, 0xb7, 0xff, 0x73, 0x92, 0xfe, ++ 0x2c, 0xe6, 0xf7, 0x88, 0x49, 0x9c, 0xdf, 0x1e, 0x6c, 0x6e, 0x66, 0xd2, ++ 0x3f, 0x24, 0x7e, 0x27, 0x43, 0xae, 0x1f, 0x26, 0xef, 0x33, 0xe8, 0xa5, ++ 0x3f, 0x97, 0x1a, 0xa0, 0xff, 0xfd, 0x9a, 0x33, 0x94, 0xfe, 0xfa, 0x46, ++ 0x4d, 0x9c, 0x9b, 0xee, 0xc7, 0x8f, 0xc3, 0x72, 0xbb, 0x1e, 0xdd, 0x01, ++ 0x3f, 0x5e, 0xa3, 0xf8, 0x7d, 0x8e, 0x27, 0x73, 0x04, 0x1f, 0x3d, 0xf9, ++ 0x1d, 0x1b, 0xe9, 0xdf, 0x15, 0xb6, 0xf6, 0xd7, 0x70, 0x4f, 0x93, 0xc2, ++ 0xe3, 0x47, 0x0d, 0xff, 0x61, 0xa5, 0xfb, 0xfe, 0x58, 0x30, 0x1b, 0xf7, ++ 0x4f, 0xcd, 0xad, 0x8f, 0xa4, 0xfb, 0x5e, 0x4b, 0x0b, 0x7d, 0x87, 0x20, ++ 0xf7, 0xa2, 0xf3, 0x3d, 0x44, 0x8f, 0x96, 0x02, 0xc1, 0x67, 0x1d, 0x4e, ++ 0xdf, 0x51, 0x3c, 0xaf, 0xdb, 0x74, 0xe8, 0x09, 0x9c, 0x1f, 0x5f, 0x7e, ++ 0xd0, 0x4d, 0xe7, 0x1a, 0x2b, 0x0f, 0x14, 0xad, 0xc7, 0xbd, 0x16, 0xa5, ++ 0x85, 0xfa, 0x9b, 0x98, 0x6f, 0xa5, 0xc3, 0x69, 0xc3, 0xfe, 0xbd, 0x6c, ++ 0x6d, 0x3c, 0xed, 0x67, 0xf3, 0x06, 0xc9, 0xf3, 0x85, 0xac, 0x8b, 0xe2, ++ 0x54, 0x0a, 0xff, 0x9d, 0xf9, 0x62, 0x1f, 0xdd, 0x52, 0xc8, 0xe4, 0x3d, ++ 0xa7, 0x32, 0xbf, 0x9e, 0x0b, 0xca, 0x69, 0x86, 0x76, 0x32, 0xaf, 0x38, ++ 0x6c, 0x9d, 0x28, 0xff, 0x60, 0xb8, 0x9f, 0x21, 0xfc, 0x3e, 0x81, 0xfe, ++ 0xd6, 0x8f, 0xf2, 0x27, 0xc0, 0x7f, 0x60, 0x0b, 0xf1, 0x2f, 0x2a, 0xff, ++ 0x84, 0x35, 0xf7, 0x93, 0x39, 0xd8, 0x3f, 0x2b, 0x6c, 0xc6, 0xf3, 0x70, ++ 0xaa, 0x4c, 0x28, 0x90, 0x76, 0xae, 0xb4, 0x03, 0x17, 0xf4, 0xec, 0x5f, ++ 0xf9, 0x93, 0x06, 0x41, 0x5f, 0xde, 0xac, 0xd1, 0xef, 0xd6, 0x54, 0x3b, ++ 0x5c, 0xb3, 0xae, 0xe6, 0xf5, 0xea, 0x63, 0x56, 0x64, 0x0a, 0xb2, 0x29, ++ 0x09, 0x2e, 0x71, 0x8f, 0xc4, 0xfd, 0xe2, 0x1e, 0x89, 0xf9, 0x7c, 0xbd, ++ 0x42, 0xde, 0x54, 0xc8, 0xbc, 0xa1, 0xea, 0xad, 0x25, 0xb4, 0xde, 0xaa, ++ 0x03, 0xbc, 0x4c, 0xec, 0x7f, 0x5d, 0xde, 0xbe, 0xf9, 0x48, 0xda, 0xcb, ++ 0xe0, 0x9f, 0xa0, 0x97, 0xce, 0x89, 0x57, 0x3b, 0xbd, 0xb6, 0x84, 0x90, ++ 0x75, 0x5f, 0xd5, 0xac, 0x19, 0xce, 0x99, 0xab, 0xba, 0xa9, 0xc0, 0x2c, ++ 0xd6, 0x11, 0xae, 0x30, 0x2f, 0x86, 0xbc, 0x70, 0xdb, 0x70, 0x97, 0x4b, ++ 0x05, 0x57, 0x2b, 0x90, 0x87, 0x96, 0x50, 0x20, 0xf8, 0x43, 0x7d, 0xc7, ++ 0xdb, 0x51, 0x1e, 0xc3, 0x94, 0x0c, 0xf6, 0xba, 0xb8, 0xc7, 0x87, 0xc3, ++ 0xed, 0x16, 0xe3, 0x15, 0x87, 0xf4, 0x3f, 0xbf, 0xd9, 0x78, 0x5e, 0x9e, ++ 0xb7, 0x27, 0x7d, 0xc8, 0x51, 0x10, 0x23, 0xce, 0xa7, 0x3b, 0xf9, 0xbc, ++ 0xe1, 0xff, 0x70, 0x3a, 0x09, 0x4e, 0x8e, 0x07, 0xc2, 0x53, 0xd7, 0x83, ++ 0xbc, 0x3f, 0x17, 0x8d, 0x43, 0xf4, 0xa8, 0x0a, 0x06, 0xac, 0xb0, 0xb7, ++ 0x2b, 0x90, 0x3f, 0xc1, 0xeb, 0x73, 0x9d, 0x01, 0x2b, 0xc6, 0x99, 0xbf, ++ 0x56, 0xdc, 0x5b, 0xa1, 0x6f, 0x12, 0xe3, 0xe8, 0x1b, 0xe3, 0x6d, 0x05, ++ 0xd0, 0x97, 0x2c, 0x4e, 0x5b, 0x1a, 0xf0, 0x27, 0xef, 0xb5, 0xe7, 0xf0, ++ 0x91, 0x1c, 0xac, 0xe6, 0x78, 0xc1, 0xf9, 0x1f, 0x75, 0x0e, 0x30, 0x1c, ++ 0x3f, 0x95, 0x12, 0xde, 0xea, 0xe6, 0x78, 0xa3, 0x1e, 0xd6, 0xbc, 0xd9, ++ 0x0a, 0x7a, 0xcc, 0xe9, 0xe7, 0xfc, 0xfc, 0x75, 0x05, 0x82, 0x6f, 0xe7, ++ 0xaf, 0x9d, 0x40, 0xe7, 0x9f, 0xab, 0x2d, 0x5e, 0xca, 0xaf, 0xd7, 0x25, ++ 0x7e, 0xff, 0xb8, 0x22, 0xf2, 0x01, 0xc4, 0x07, 0xe6, 0xb4, 0x6c, 0xb1, ++ 0xba, 0x79, 0xbd, 0xb0, 0x40, 0xc8, 0x99, 0xeb, 0x0a, 0x04, 0x7f, 0x4d, ++ 0xc9, 0x08, 0x66, 0xd3, 0xfd, 0x34, 0x2b, 0x22, 0x3d, 0x80, 0x73, 0x8e, ++ 0xb3, 0x99, 0xe6, 0xd7, 0x83, 0xdf, 0x87, 0x39, 0x3e, 0x34, 0xdc, 0x83, ++ 0xe2, 0x23, 0xfc, 0x72, 0xbe, 0xf0, 0x23, 0x8f, 0xac, 0xba, 0xc5, 0x48, ++ 0xcf, 0x5e, 0x78, 0x62, 0xc4, 0x3d, 0x46, 0x2d, 0x95, 0xb4, 0xde, 0x16, ++ 0x5a, 0x74, 0x9b, 0x33, 0x14, 0x8e, 0xad, 0x87, 0xb2, 0x71, 0xae, 0x67, ++ 0x0e, 0x5f, 0xdf, 0xb8, 0x77, 0x87, 0x39, 0x75, 0x3a, 0x6f, 0xf3, 0xe9, ++ 0xc3, 0xb3, 0xd2, 0x69, 0x9e, 0x1c, 0x4e, 0xe0, 0x35, 0xc6, 0xe3, 0x9a, ++ 0x84, 0xfb, 0x66, 0x38, 0x9f, 0x10, 0x1f, 0x2b, 0x7e, 0x51, 0xe7, 0x83, ++ 0xd5, 0x78, 0x33, 0x0b, 0xc4, 0x79, 0xc7, 0x99, 0x05, 0x7d, 0xfb, 0xd7, ++ 0x7b, 0xd7, 0xa5, 0x97, 0xf4, 0x9b, 0x26, 0x4e, 0x5f, 0xf8, 0xbd, 0xfb, ++ 0x5b, 0x97, 0x36, 0x1c, 0x34, 0xe2, 0xe3, 0xda, 0xaa, 0xc5, 0x3d, 0x60, ++ 0xe1, 0xeb, 0x54, 0xad, 0x4f, 0xb5, 0x2e, 0xd5, 0x3a, 0x55, 0xeb, 0xf7, ++ 0x09, 0xab, 0x2f, 0x98, 0xac, 0xf5, 0xca, 0x19, 0xbe, 0xdf, 0xd6, 0xbf, ++ 0xd0, 0x07, 0x9e, 0x5a, 0x0a, 0x84, 0x1c, 0x99, 0x2b, 0xe9, 0xca, 0xf1, ++ 0x7a, 0x34, 0xf4, 0x5c, 0xd1, 0xf7, 0xe4, 0x7a, 0xae, 0xc8, 0x30, 0xae, ++ 0x77, 0xf4, 0x47, 0xf7, 0x06, 0x4a, 0xba, 0x57, 0x94, 0x06, 0xb3, 0x71, ++ 0x0e, 0x50, 0xb5, 0x57, 0xe3, 0x56, 0x24, 0x88, 0xef, 0xc0, 0xf7, 0xe0, ++ 0xb7, 0xa5, 0x72, 0x3c, 0xb4, 0x5f, 0x49, 0xed, 0x4d, 0x06, 0x79, 0x51, ++ 0xd5, 0x23, 0x2f, 0x76, 0xaf, 0x4b, 0x82, 0xbc, 0xd8, 0xa3, 0x91, 0xbe, ++ 0xbb, 0xf2, 0xc1, 0x23, 0x69, 0xdf, 0x86, 0x1e, 0xfb, 0x9c, 0xd0, 0x63, ++ 0xcf, 0xd4, 0xee, 0x58, 0x96, 0x02, 0xbf, 0x81, 0x25, 0x90, 0x1e, 0x7a, ++ 0x3f, 0x53, 0x75, 0x50, 0xc8, 0x87, 0x05, 0x5c, 0xff, 0x81, 0xbc, 0x58, ++ 0x28, 0xf7, 0xe9, 0x92, 0x6c, 0xfd, 0x3b, 0x05, 0x21, 0xeb, 0xb7, 0xfa, ++ 0x87, 0xcf, 0xe5, 0xe8, 0x42, 0xbe, 0x04, 0x21, 0x5f, 0x3e, 0x7e, 0xee, ++ 0x95, 0x0f, 0xc6, 0xb9, 0x7a, 0xf7, 0x4f, 0x05, 0xff, 0xfc, 0x8d, 0xbf, ++ 0xb6, 0x56, 0x3a, 0x42, 0xf1, 0xa5, 0xc9, 0xfb, 0x28, 0xba, 0xe9, 0xdc, ++ 0x57, 0x95, 0xc3, 0xe6, 0x42, 0x9e, 0x6d, 0xd5, 0xda, 0x4a, 0x92, 0xb7, ++ 0x2c, 0x99, 0xdb, 0x13, 0x5a, 0x48, 0x9e, 0x54, 0x18, 0x1f, 0x54, 0xae, ++ 0xd5, 0xe8, 0xde, 0xac, 0xaa, 0x86, 0xb1, 0x01, 0xf3, 0xff, 0xa0, 0x5c, ++ 0xae, 0xda, 0x34, 0x8d, 0xee, 0xe6, 0x51, 0x74, 0x52, 0xf7, 0x6f, 0xa8, ++ 0xfd, 0x54, 0xc1, 0xff, 0xb8, 0x84, 0x7f, 0xae, 0xe4, 0xe3, 0x80, 0x94, ++ 0x6b, 0x73, 0x6b, 0xdc, 0xb6, 0x85, 0xb4, 0xee, 0xdd, 0xb6, 0x2a, 0xf0, ++ 0xbf, 0x7c, 0x3f, 0xa7, 0xda, 0xf8, 0xbc, 0x87, 0x4e, 0x3d, 0x71, 0xec, ++ 0xfc, 0xf5, 0xc9, 0xf2, 0x1c, 0x0b, 0xd9, 0x25, 0x9b, 0xac, 0xc2, 0xbf, ++ 0xb7, 0x3b, 0x86, 0xf4, 0xd5, 0x33, 0x2b, 0x5f, 0x7a, 0x67, 0x26, 0x6f, ++ 0xf7, 0xc5, 0x23, 0xad, 0xe9, 0xd0, 0x4f, 0x14, 0x1c, 0x8b, 0xa4, 0x1f, ++ 0x6f, 0x81, 0xf4, 0xc7, 0x2d, 0x94, 0x7a, 0x2b, 0xa7, 0xd3, 0x4f, 0x0b, ++ 0x42, 0xf2, 0x5b, 0x16, 0x3d, 0x29, 0xe8, 0x54, 0xf5, 0xfc, 0xaf, 0x7e, ++ 0x8f, 0xfb, 0xa1, 0x2a, 0x32, 0xa4, 0x3c, 0x7b, 0x50, 0x9c, 0x2f, 0x9f, ++ 0xdf, 0xb6, 0x87, 0xe8, 0x36, 0x67, 0xe3, 0x66, 0xab, 0x9b, 0xb7, 0xfb, ++ 0x45, 0x81, 0xdb, 0x20, 0xa7, 0xab, 0xea, 0x8b, 0x9c, 0xf0, 0x4f, 0xcf, ++ 0xdd, 0xd8, 0x6a, 0x85, 0x1c, 0xf8, 0x85, 0x94, 0x37, 0xe1, 0xfc, 0x5e, ++ 0x21, 0xf3, 0x52, 0x15, 0x5e, 0xb1, 0xef, 0x68, 0x21, 0xf1, 0x0b, 0xd5, ++ 0x1e, 0xf2, 0x6f, 0x0f, 0x1f, 0xe7, 0xae, 0x15, 0x91, 0xb1, 0xc8, 0x73, ++ 0x51, 0xe3, 0x9c, 0x96, 0x7c, 0x5c, 0x55, 0x1f, 0x9f, 0x80, 0xf1, 0xaa, ++ 0xea, 0x2b, 0x7f, 0x00, 0xbb, 0x47, 0xc9, 0xfb, 0xf0, 0x75, 0x77, 0x32, ++ 0x52, 0xac, 0x87, 0xf9, 0xbc, 0x3f, 0xac, 0xcb, 0x93, 0x13, 0x3c, 0x74, ++ 0xce, 0xb6, 0x42, 0xfe, 0xbe, 0x54, 0x78, 0xfb, 0x3f, 0x48, 0xba, 0xfd, ++ 0xc8, 0x2a, 0xee, 0x11, 0x4c, 0x8d, 0x6e, 0x7b, 0x9a, 0xf2, 0x16, 0x96, ++ 0x47, 0x79, 0x20, 0x1f, 0xb2, 0xb2, 0x3a, 0x02, 0x18, 0x17, 0xfc, 0x0c, ++ 0xb8, 0x6d, 0x26, 0x71, 0xef, 0x60, 0x56, 0x6d, 0xc7, 0x97, 0x80, 0x83, ++ 0xab, 0xc5, 0x94, 0x9f, 0x82, 0x12, 0xf7, 0x1d, 0x41, 0x4d, 0x4e, 0xe2, ++ 0xf5, 0xa7, 0x4c, 0xe2, 0x3c, 0x50, 0x86, 0x59, 0x94, 0xd6, 0x42, 0xc1, ++ 0x0f, 0x70, 0x4d, 0xe1, 0x3d, 0x1b, 0xd0, 0x41, 0xf7, 0x9f, 0x85, 0xe4, ++ 0x67, 0x1a, 0xf8, 0xd5, 0xc6, 0xb6, 0x6f, 0xc4, 0xfd, 0x2b, 0xb6, 0x01, ++ 0x8c, 0x7e, 0xef, 0x45, 0xf1, 0xa7, 0xea, 0x47, 0xf1, 0xa7, 0xe2, 0xdf, ++ 0xfe, 0xe6, 0xf7, 0xdf, 0x57, 0x38, 0xbf, 0x93, 0x6e, 0xe9, 0x87, 0xc8, ++ 0xf5, 0xa4, 0xe3, 0x1c, 0xc5, 0xbc, 0x87, 0x86, 0xd1, 0xfd, 0xfc, 0xdf, ++ 0x34, 0x4f, 0x9b, 0xbc, 0x07, 0xaf, 0x67, 0xbe, 0x11, 0xe2, 0x77, 0x0b, ++ 0x2e, 0x9b, 0x6f, 0x96, 0x8c, 0x8f, 0xf7, 0x3b, 0xdf, 0x96, 0xf2, 0xa4, ++ 0x3e, 0xe6, 0x1b, 0x3e, 0x4f, 0xb5, 0x4e, 0x54, 0xee, 0x75, 0x4f, 0x5c, ++ 0xa1, 0x59, 0xc4, 0x15, 0x4e, 0x6a, 0x7c, 0xff, 0xe2, 0xdf, 0x9d, 0x5c, ++ 0x11, 0x49, 0x79, 0x5f, 0x6a, 0x5e, 0xca, 0xef, 0x7d, 0xa5, 0xf9, 0xf2, ++ 0xee, 0xc2, 0x04, 0x99, 0x37, 0xdc, 0x11, 0x03, 0x3d, 0xb2, 0x42, 0xfe, ++ 0x1e, 0x04, 0x0b, 0x8a, 0x3a, 0x9e, 0x4f, 0x0b, 0x79, 0xae, 0xf6, 0x7d, ++ 0x75, 0x6f, 0x98, 0x92, 0xcf, 0xa7, 0xea, 0xe5, 0xbe, 0xc8, 0x3a, 0x1e, ++ 0xc4, 0x7a, 0x66, 0x0d, 0x99, 0x74, 0x4f, 0xc6, 0x89, 0xe6, 0x93, 0x31, ++ 0xb8, 0xbf, 0xe3, 0xe4, 0x04, 0x01, 0x9f, 0xfa, 0xee, 0x2e, 0xab, 0x38, ++ 0xf7, 0xca, 0x62, 0x6c, 0x2e, 0xdc, 0x9f, 0xc8, 0xed, 0x2b, 0xfa, 0xdd, ++ 0x87, 0x05, 0x6b, 0x07, 0x91, 0x1d, 0x79, 0x47, 0x43, 0x26, 0xc9, 0x85, ++ 0x3b, 0xfc, 0xf1, 0xc2, 0xef, 0x20, 0xf5, 0xfb, 0x85, 0x52, 0x0e, 0x46, ++ 0xdf, 0x55, 0xb9, 0xfe, 0x2a, 0xb4, 0xdf, 0xea, 0x76, 0x6a, 0x7c, 0x9c, ++ 0x05, 0x0e, 0xcf, 0xa7, 0x5b, 0xe9, 0xfb, 0x3c, 0x0f, 0xf4, 0xc1, 0xe8, ++ 0x96, 0x69, 0xb6, 0x0c, 0xd2, 0x7b, 0x85, 0x1d, 0xa0, 0xe2, 0x40, 0x77, ++ 0x69, 0xcc, 0x47, 0xe7, 0x99, 0x20, 0x27, 0xb1, 0xbe, 0x4c, 0x87, 0xb2, ++ 0xb0, 0xef, 0x2c, 0xda, 0x2a, 0xec, 0x80, 0x29, 0x26, 0xb6, 0x11, 0xf1, ++ 0xc2, 0xa1, 0x4d, 0xbe, 0x49, 0x29, 0x90, 0x13, 0x8f, 0x8a, 0x7b, 0x23, ++ 0xd9, 0x36, 0xe3, 0xbd, 0x4a, 0x2f, 0x66, 0xfb, 0xc6, 0x17, 0x02, 0x6f, ++ 0x61, 0xf7, 0x91, 0xdd, 0x65, 0x6d, 0xf3, 0x0e, 0x82, 0x1c, 0xe7, 0xfa, ++ 0x06, 0xfc, 0x4c, 0x0b, 0x1c, 0x3e, 0xd2, 0xdb, 0x5f, 0x91, 0x72, 0xf2, ++ 0x44, 0x4b, 0x27, 0xdd, 0x4f, 0xae, 0xf0, 0x7a, 0xd9, 0x39, 0x15, 0x9b, ++ 0x38, 0x97, 0xda, 0x15, 0x63, 0x22, 0xff, 0xdb, 0x95, 0x9e, 0x57, 0xa9, ++ 0x96, 0xf1, 0x24, 0xc5, 0x37, 0x2a, 0x1e, 0xf5, 0x18, 0xfe, 0x73, 0x35, ++ 0xf0, 0x64, 0xa2, 0x7d, 0xad, 0xdc, 0x5c, 0x41, 0xf7, 0xfa, 0xac, 0x6f, ++ 0x99, 0x48, 0x65, 0xf5, 0xe6, 0xf2, 0x47, 0xfc, 0x05, 0x38, 0x0f, 0xeb, ++ 0x4b, 0x1a, 0x47, 0x70, 0x5b, 0xc9, 0x3f, 0x56, 0x5d, 0x37, 0x51, 0x9c, ++ 0x1f, 0x7d, 0x2a, 0x22, 0x1e, 0xf6, 0x4d, 0xba, 0xd5, 0x9f, 0x1e, 0xaa, ++ 0x97, 0x56, 0xb7, 0x6e, 0xa0, 0x73, 0x2a, 0xa7, 0x5b, 0x23, 0xe9, 0x9c, ++ 0x4a, 0x99, 0x73, 0x5a, 0x59, 0xfc, 0x00, 0xba, 0x6f, 0x97, 0xce, 0x7d, ++ 0xa9, 0x76, 0xb5, 0x85, 0x62, 0x3f, 0x5f, 0x52, 0x37, 0xd1, 0x70, 0xce, ++ 0x64, 0x01, 0xef, 0x13, 0x79, 0xb0, 0x7f, 0x6e, 0x8b, 0xa6, 0xbc, 0x52, ++ 0x75, 0x7e, 0xe4, 0xde, 0x28, 0x7d, 0x51, 0xe1, 0x40, 0x71, 0x8e, 0xe4, ++ 0x6a, 0x97, 0x38, 0x3f, 0x92, 0x42, 0xed, 0x5d, 0x7d, 0xfa, 0xc3, 0x55, ++ 0xf9, 0x69, 0xa3, 0x38, 0x8f, 0x10, 0x72, 0x2e, 0x66, 0xea, 0x1c, 0xfe, ++ 0x7d, 0x6d, 0xdd, 0x8b, 0xb1, 0xe8, 0x67, 0xe9, 0xc3, 0xef, 0x8d, 0xe5, ++ 0x98, 0x81, 0xff, 0x69, 0x15, 0xfa, 0xef, 0x39, 0x17, 0xb3, 0x55, 0x9c, ++ 0x8b, 0xb9, 0x0b, 0xf6, 0x12, 0xf4, 0xc8, 0x04, 0xdf, 0xcc, 0x39, 0xc0, ++ 0xff, 0x9b, 0x66, 0xc2, 0x7f, 0x7f, 0xe3, 0xd5, 0xe0, 0x47, 0x49, 0x42, ++ 0xec, 0x88, 0x3b, 0x02, 0x71, 0xa4, 0xb7, 0xea, 0x41, 0x66, 0x43, 0x3c, ++ 0x59, 0x77, 0x32, 0xd2, 0x8b, 0x4f, 0x9b, 0x59, 0x03, 0xf4, 0x00, 0xa5, ++ 0xbf, 0xa8, 0xe7, 0x1b, 0x24, 0x5e, 0x4e, 0xc7, 0x35, 0xa7, 0x83, 0x3f, ++ 0x16, 0xef, 0xdc, 0x92, 0x8e, 0xfd, 0xe5, 0xf3, 0x18, 0x51, 0xaf, 0xd8, ++ 0x39, 0xeb, 0x97, 0x90, 0x57, 0xfa, 0xf6, 0x08, 0xa1, 0x9f, 0x5b, 0x18, ++ 0xe9, 0xc3, 0x55, 0x7e, 0xa1, 0x5f, 0xb3, 0x9a, 0x04, 0x75, 0x2f, 0x66, ++ 0xe4, 0x3c, 0xce, 0x47, 0x9b, 0x0b, 0xa3, 0xc5, 0x3d, 0x3d, 0xf2, 0xfc, ++ 0x8c, 0x82, 0x4b, 0xdd, 0xb7, 0xfa, 0xb9, 0x45, 0xdc, 0x17, 0x83, 0x73, ++ 0x31, 0xe0, 0xf7, 0x8f, 0x2c, 0xc1, 0x05, 0xa0, 0xef, 0x47, 0x5c, 0x7f, ++ 0x85, 0x1d, 0x5b, 0x2b, 0xe5, 0xd8, 0x47, 0xcd, 0x66, 0xfa, 0xdd, 0x11, ++ 0x3f, 0x5f, 0x28, 0xd0, 0x43, 0x3e, 0x6a, 0x7e, 0x31, 0x06, 0xe7, 0x73, ++ 0x95, 0xbe, 0x56, 0x6e, 0xfe, 0xd8, 0x8b, 0xfb, 0x68, 0x56, 0xee, 0x13, ++ 0xe7, 0x54, 0x71, 0xaf, 0x39, 0xdd, 0x59, 0x29, 0xfd, 0x20, 0xcb, 0xa4, ++ 0x1f, 0x64, 0xe5, 0xcb, 0xd6, 0x49, 0xf8, 0xdd, 0x11, 0xae, 0x7f, 0xd1, ++ 0x93, 0x5a, 0x4b, 0xd0, 0xd6, 0x17, 0xfd, 0x96, 0x48, 0xfd, 0xaa, 0xa7, ++ 0xbe, 0x77, 0x0f, 0xd9, 0x6d, 0xb5, 0xbb, 0x85, 0xfe, 0x50, 0xdb, 0xd6, ++ 0x49, 0xfa, 0x83, 0xd2, 0x47, 0xd4, 0xb9, 0xb8, 0xa5, 0xbb, 0x3b, 0x49, ++ 0x9f, 0x50, 0xdf, 0x2d, 0xdb, 0x2b, 0xf0, 0x52, 0xb7, 0x57, 0x3c, 0xaf, ++ 0x44, 0xde, 0xba, 0xfc, 0xbd, 0x50, 0x2d, 0x0b, 0xf6, 0xb4, 0x46, 0xf5, ++ 0x77, 0x76, 0xcf, 0x9d, 0xb5, 0xc6, 0x50, 0x9f, 0x43, 0xf5, 0x77, 0xf2, ++ 0xa5, 0xbf, 0xde, 0xd2, 0x45, 0xfa, 0xe0, 0x03, 0xb9, 0xbf, 0x21, 0x3b, ++ 0xbc, 0x6e, 0xad, 0xec, 0x97, 0xd7, 0xad, 0x21, 0xe3, 0xed, 0x07, 0x13, ++ 0x8d, 0x11, 0xcf, 0x33, 0x1d, 0xf8, 0xde, 0x65, 0xd0, 0x1b, 0xea, 0xf6, ++ 0xc6, 0xd3, 0xf7, 0xc1, 0xba, 0xa8, 0x8d, 0xd8, 0xe7, 0xbd, 0xcb, 0x1c, ++ 0x16, 0x94, 0x4d, 0x75, 0x0e, 0xda, 0xf7, 0xb7, 0xd5, 0x9b, 0x72, 0x2d, ++ 0xa3, 0x01, 0x5c, 0x94, 0x07, 0x7a, 0xdc, 0x41, 0x99, 0xbf, 0x35, 0x70, ++ 0xe9, 0x7f, 0x46, 0xc2, 0x7f, 0x90, 0xc2, 0xba, 0x8e, 0xe0, 0xde, 0xd7, ++ 0xc3, 0x4e, 0xfd, 0x4d, 0xc8, 0x19, 0xf5, 0x7b, 0x96, 0xea, 0xdc, 0xcb, ++ 0x85, 0x57, 0x3f, 0x1b, 0x85, 0xfe, 0xaf, 0x1b, 0xda, 0x71, 0x11, 0x77, ++ 0x3c, 0x58, 0xb5, 0x85, 0xb3, 0x10, 0x9f, 0xf8, 0x75, 0xa1, 0x9c, 0x47, ++ 0x7e, 0xc7, 0x28, 0xf0, 0xf5, 0xc0, 0xc3, 0x42, 0x3e, 0x3f, 0x6e, 0x65, ++ 0x1b, 0xe9, 0xfe, 0x60, 0x8b, 0x8f, 0xc1, 0x6f, 0x1f, 0x94, 0x71, 0x45, ++ 0xff, 0x5f, 0x4c, 0xe2, 0xf7, 0x25, 0xb4, 0xe0, 0x8f, 0x43, 0xf5, 0x2b, ++ 0xeb, 0x48, 0xb1, 0x9f, 0xfa, 0x22, 0x44, 0x7c, 0xb1, 0xc8, 0xad, 0x7f, ++ 0x08, 0x38, 0x6e, 0xd1, 0xac, 0x05, 0x45, 0xb0, 0xa9, 0x5d, 0xe6, 0x6c, ++ 0xf4, 0xaf, 0x7e, 0x47, 0x45, 0xe9, 0xa9, 0xa5, 0x52, 0x3e, 0xa7, 0x49, ++ 0xfb, 0xca, 0x36, 0x38, 0xd9, 0x01, 0x3e, 0xd6, 0xbc, 0x5e, 0x3a, 0x87, ++ 0x78, 0x5f, 0xfe, 0xe1, 0x2a, 0xec, 0xcb, 0xdf, 0xef, 0xb2, 0xd3, 0xef, ++ 0xab, 0xaa, 0x3c, 0xbf, 0xd2, 0xae, 0x28, 0xd2, 0x5b, 0xd3, 0x06, 0x4f, ++ 0xa6, 0xfd, 0x4c, 0x73, 0x59, 0x58, 0x45, 0x31, 0xfc, 0x2a, 0xa6, 0x20, ++ 0xf2, 0x55, 0xbf, 0xcf, 0xec, 0x22, 0x2f, 0xc0, 0x1e, 0xa6, 0xd7, 0x9a, ++ 0x22, 0x29, 0x1f, 0x59, 0x3b, 0xf8, 0xc6, 0x5f, 0x20, 0xcf, 0x53, 0xcd, ++ 0x5f, 0x1e, 0xc1, 0xef, 0x94, 0xa4, 0x7e, 0x5b, 0xa3, 0xfb, 0x2f, 0xe7, ++ 0x75, 0x7f, 0xfa, 0x38, 0x7e, 0x63, 0xa6, 0x82, 0x05, 0x8a, 0xe8, 0x1e, ++ 0xbc, 0x78, 0xfd, 0x22, 0x48, 0x77, 0xa2, 0x7b, 0x72, 0xa7, 0xce, 0x49, ++ 0xf6, 0x7d, 0x67, 0x9b, 0xdd, 0x23, 0xf6, 0x09, 0x16, 0x0a, 0xff, 0xc1, ++ 0x7b, 0xfe, 0x12, 0x9b, 0x60, 0xea, 0x85, 0xeb, 0x42, 0xd7, 0xa7, 0x74, ++ 0xaf, 0xe0, 0x85, 0x2e, 0x3b, 0xf9, 0x6b, 0x4b, 0x0f, 0xca, 0xfb, 0xf6, ++ 0xc2, 0xe0, 0xb9, 0x90, 0xec, 0xa2, 0xbc, 0x68, 0xde, 0x8e, 0xf4, 0xcc, ++ 0x0b, 0x0e, 0x13, 0xdd, 0x33, 0x56, 0x7a, 0xf0, 0x08, 0xdd, 0x9b, 0x57, ++ 0xaa, 0xee, 0xd5, 0xb3, 0x1b, 0xef, 0xd5, 0x63, 0xae, 0xb4, 0x78, 0xf8, ++ 0x93, 0xc9, 0x87, 0xca, 0x95, 0x82, 0xa4, 0x26, 0x41, 0xb7, 0xeb, 0xe2, ++ 0x8c, 0x76, 0x62, 0xd2, 0x48, 0xa1, 0x27, 0x26, 0x8d, 0xd4, 0xe4, 0x3d, ++ 0xa5, 0x02, 0x7f, 0xdd, 0xf6, 0xf3, 0x6f, 0xe9, 0x5a, 0xef, 0x3a, 0x5c, ++ 0xae, 0xe2, 0xf7, 0xea, 0xf7, 0xa6, 0x6a, 0x22, 0xe8, 0xf7, 0xa6, 0xba, ++ 0x0f, 0x66, 0x7e, 0xed, 0xfd, 0x09, 0xef, 0x41, 0x7f, 0xe0, 0x7a, 0xc1, ++ 0xf7, 0x32, 0xbc, 0xe9, 0x23, 0xc7, 0xf4, 0xee, 0x9f, 0x33, 0x24, 0x5e, ++ 0xd4, 0x3e, 0x6c, 0x96, 0xfd, 0xcf, 0x90, 0xf8, 0x99, 0xe1, 0x30, 0x09, ++ 0x7c, 0x84, 0xfd, 0xde, 0x86, 0xe2, 0x0f, 0x45, 0x7f, 0x05, 0xaf, 0x3a, ++ 0x77, 0xa4, 0xe8, 0xc6, 0xbe, 0xd3, 0xfe, 0x1a, 0xce, 0x05, 0x71, 0x7a, ++ 0x15, 0x3c, 0xc4, 0x88, 0x4e, 0xb9, 0x18, 0xff, 0xc4, 0x5f, 0xde, 0x5e, ++ 0x87, 0x63, 0xfe, 0x83, 0xcd, 0xde, 0x4e, 0xdd, 0xfd, 0x6f, 0xa1, 0x53, ++ 0x10, 0xf7, 0xe0, 0x5c, 0x31, 0x9d, 0xda, 0xc3, 0xe9, 0x14, 0x8c, 0x1c, ++ 0x06, 0x3d, 0xe1, 0x61, 0xf1, 0xfb, 0x5b, 0xe1, 0x79, 0x8d, 0x2c, 0x97, ++ 0xd1, 0x3a, 0x9f, 0x67, 0x8e, 0x22, 0x3f, 0xa0, 0x2e, 0xef, 0x05, 0xe7, ++ 0xeb, 0xfb, 0x35, 0xac, 0x6f, 0xb5, 0xae, 0x87, 0x4e, 0xee, 0x28, 0xc0, ++ 0xfe, 0x78, 0x82, 0x9b, 0xde, 0x80, 0xab, 0xc3, 0xd4, 0x46, 0xcf, 0x17, ++ 0x8d, 0xcc, 0xa0, 0x75, 0x38, 0x84, 0xb5, 0xa7, 0xc8, 0xfc, 0x9b, 0x31, ++ 0xd0, 0xcb, 0x9a, 0xe4, 0xfd, 0xc7, 0x3d, 0xbf, 0x63, 0xb8, 0xd8, 0x41, ++ 0xf7, 0x8d, 0x5c, 0x08, 0xa8, 0xfb, 0x8f, 0x03, 0x8f, 0x2e, 0xe4, 0xe3, ++ 0xb6, 0xcc, 0xc8, 0x27, 0xbf, 0xfe, 0x05, 0x26, 0xd7, 0x7b, 0x4d, 0xcf, ++ 0x3d, 0xd9, 0xe2, 0xfe, 0xe3, 0x9e, 0x7b, 0xb2, 0xcd, 0x7e, 0xf2, 0x93, ++ 0xcc, 0x89, 0x22, 0x3f, 0x4f, 0xcf, 0x3d, 0xd9, 0xd9, 0xe2, 0xbe, 0xeb, ++ 0x57, 0x34, 0x96, 0x83, 0x7b, 0x68, 0xfd, 0xd3, 0xec, 0x94, 0x1f, 0x1f, ++ 0x7e, 0x4f, 0x36, 0xdf, 0x67, 0x9e, 0x46, 0x3c, 0xe3, 0xb1, 0x9a, 0x28, ++ 0x8a, 0x43, 0xa9, 0xfb, 0x91, 0x4b, 0x9d, 0x7a, 0xe5, 0xc8, 0x81, 0x97, ++ 0xdf, 0x8f, 0xfc, 0x88, 0xe6, 0x9b, 0xb3, 0x00, 0xfd, 0x15, 0x38, 0xa8, ++ 0xbf, 0x8e, 0x39, 0x51, 0xcf, 0xef, 0x14, 0x68, 0x0e, 0xc2, 0x8f, 0x73, ++ 0xa2, 0x21, 0x86, 0xee, 0x85, 0x56, 0x7c, 0xa9, 0xfc, 0xd7, 0x43, 0xfd, ++ 0x9d, 0x8f, 0x02, 0x4f, 0xea, 0x5c, 0xe7, 0x1f, 0x24, 0x7f, 0x29, 0xbc, ++ 0xab, 0x73, 0x6d, 0x0a, 0xff, 0x8a, 0xcf, 0xd4, 0x7d, 0xec, 0xda, 0x6a, ++ 0xc1, 0x6f, 0x3d, 0x79, 0xb2, 0xcb, 0x18, 0xf9, 0x47, 0x86, 0x70, 0x10, ++ 0xa2, 0x29, 0xef, 0xd1, 0xe3, 0x02, 0x9e, 0x1f, 0x8c, 0xd7, 0x1b, 0x00, ++ 0x77, 0xd3, 0x0a, 0x2e, 0x37, 0xc8, 0x2f, 0x2e, 0xf2, 0x37, 0x4f, 0x98, ++ 0x8c, 0xbf, 0xdb, 0xab, 0xca, 0x26, 0xb9, 0x2e, 0x99, 0xcc, 0xff, 0x9f, ++ 0x27, 0xf7, 0xa9, 0x79, 0x2a, 0xdf, 0xbf, 0xc1, 0x98, 0xef, 0x1f, 0x7e, ++ 0x7f, 0x66, 0x62, 0x9c, 0x6f, 0x1d, 0xc6, 0x3b, 0xa7, 0xbd, 0x37, 0x16, ++ 0x0f, 0xdf, 0xfe, 0x6f, 0x73, 0x9f, 0xf9, 0x23, 0x3f, 0x90, 0x72, 0x79, ++ 0x74, 0xb4, 0xfe, 0x20, 0xda, 0xab, 0x73, 0x0f, 0x4a, 0x2f, 0x7c, 0xbb, ++ 0xe8, 0xb3, 0x34, 0xfa, 0x9d, 0x91, 0xaf, 0x8e, 0xd0, 0xef, 0x29, 0xce, ++ 0x75, 0xfa, 0x9a, 0xb1, 0x8e, 0x22, 0xb3, 0x44, 0x1c, 0xe0, 0x0f, 0x29, ++ 0x1d, 0x74, 0x4e, 0xe3, 0x0f, 0x73, 0xfe, 0x9a, 0x46, 0x7e, 0xe4, 0xd5, ++ 0xe2, 0xde, 0xcf, 0x2b, 0x85, 0xf3, 0xf2, 0x73, 0xb4, 0x82, 0x0f, 0x56, ++ 0x2d, 0x10, 0x79, 0x86, 0xa9, 0xac, 0x9e, 0xf8, 0x36, 0xb9, 0xf7, 0x7c, ++ 0x66, 0x24, 0xe0, 0xf8, 0xff, 0xed, 0x1c, 0x6d, 0xef, 0x39, 0xd7, 0xc9, ++ 0xa3, 0x4e, 0x51, 0xbe, 0x85, 0x8f, 0x7e, 0xa7, 0x22, 0x9c, 0x1e, 0xe3, ++ 0x23, 0x0e, 0xbf, 0xe8, 0xe2, 0x16, 0xca, 0x1b, 0x23, 0x3f, 0x99, 0x45, ++ 0xe7, 0x4e, 0xe3, 0x0e, 0xaf, 0x72, 0xf3, 0xfa, 0x3b, 0x3f, 0xfd, 0x54, ++ 0xd4, 0x53, 0x0f, 0x5f, 0x74, 0xe3, 0x5c, 0xea, 0x4f, 0x3f, 0x9b, 0x45, ++ 0xe7, 0x4c, 0xf3, 0x0e, 0x5f, 0xc4, 0x39, 0xd4, 0xdf, 0xfc, 0xf4, 0xb4, ++ 0x78, 0x7f, 0x0d, 0xa3, 0x38, 0xd6, 0xfb, 0x3f, 0xfd, 0x7c, 0x16, 0xce, ++ 0x9d, 0xda, 0xdd, 0xfa, 0x07, 0xa0, 0xeb, 0xcc, 0x4b, 0xf5, 0xaf, 0x61, ++ 0x5b, 0xfd, 0x60, 0xcd, 0xad, 0x0b, 0xdc, 0x74, 0x8e, 0x72, 0x5a, 0x5a, ++ 0xae, 0x38, 0x47, 0xf9, 0x16, 0xe8, 0x39, 0x23, 0x69, 0xfe, 0xba, 0x38, ++ 0xad, 0xf7, 0x1c, 0x65, 0xf7, 0x48, 0xdf, 0x07, 0x78, 0x7e, 0xe1, 0x4b, ++ 0xc1, 0xe7, 0x6e, 0xc4, 0xc0, 0x06, 0xfe, 0xeb, 0xa5, 0x3a, 0x47, 0xaa, ++ 0xe4, 0x6c, 0x7f, 0xf2, 0x50, 0xad, 0xb7, 0x7f, 0xd7, 0x39, 0x58, 0xb5, ++ 0x7e, 0xd9, 0x4e, 0xcf, 0x46, 0x2b, 0x98, 0xd0, 0xff, 0x2f, 0x9f, 0x4f, ++ 0xed, 0x12, 0xfb, 0x99, 0xf1, 0x7c, 0xea, 0x6b, 0xaf, 0xfe, 0xd6, 0x85, ++ 0xbc, 0xc3, 0xf1, 0xa3, 0xed, 0xc4, 0xcf, 0xe3, 0x1d, 0xed, 0x2e, 0xf8, ++ 0x05, 0x50, 0x87, 0x5c, 0xdc, 0xfe, 0xa5, 0x38, 0xcf, 0x87, 0x76, 0x96, ++ 0xd0, 0x76, 0x03, 0xc4, 0x39, 0xbe, 0xf1, 0x38, 0x4f, 0x01, 0xff, 0x41, ++ 0xb7, 0x38, 0x67, 0xf8, 0xda, 0xab, 0x6f, 0xa4, 0x40, 0xde, 0x8f, 0xaf, ++ 0xb7, 0x51, 0x9e, 0xcf, 0x16, 0xf9, 0xbb, 0x00, 0x31, 0xa6, 0x43, 0x66, ++ 0x8c, 0xf3, 0x7f, 0x00, 0xb1, 0x49, 0x2f, 0x16, 0x00, 0x80, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x0b, 0xb5, 0x3c, 0x0b, 0x58, 0x94, 0xd7, 0x95, 0xf7, 0x9f, 0x7f, ++ 0x9e, 0x30, 0xc0, 0x80, 0x08, 0x28, 0x8a, 0x3f, 0x82, 0x04, 0x13, 0xa4, ++ 0x33, 0xbc, 0x34, 0x5b, 0xdb, 0x8e, 0x0a, 0x14, 0xa5, 0x4d, 0x31, 0xdd, ++ 0xa4, 0x1a, 0x09, 0x8e, 0x91, 0x20, 0xaf, 0x01, 0xd4, 0xb6, 0x71, 0xb7, ++ 0xc9, 0xc7, 0x18, 0x8c, 0x51, 0x9b, 0x74, 0x75, 0x63, 0x12, 0x63, 0x8c, ++ 0x19, 0x50, 0xd4, 0x34, 0xb8, 0x3b, 0x46, 0x30, 0xa0, 0xd8, 0x4c, 0x4c, ++ 0xa4, 0xc6, 0x3c, 0x96, 0xb0, 0x5b, 0xe2, 0xb7, 0xdb, 0xf8, 0x61, 0x62, ++ 0x8c, 0xaf, 0x0c, 0x48, 0x92, 0x6e, 0xfc, 0xd6, 0xd6, 0x3d, 0xe7, 0xdc, ++ 0xfb, 0x33, 0x0f, 0x20, 0x26, 0xed, 0x2e, 0x7e, 0xed, 0xcd, 0xb9, 0xef, ++ 0x7b, 0xde, 0xe7, 0xdc, 0xfb, 0x4f, 0xc4, 0x30, 0x63, 0x4d, 0x12, 0x63, ++ 0x53, 0x0c, 0x8c, 0x19, 0xb3, 0x18, 0x8b, 0xd7, 0x33, 0x66, 0x8a, 0x61, ++ 0xec, 0x59, 0x1d, 0xc0, 0x50, 0xee, 0x1d, 0x66, 0x5e, 0x4d, 0x24, 0x63, ++ 0x53, 0x63, 0x1a, 0x56, 0xb3, 0x1c, 0x28, 0xcb, 0xcc, 0xd6, 0xa6, 0x64, ++ 0x06, 0x7f, 0x6e, 0xc6, 0x72, 0x19, 0x4b, 0x9c, 0xe0, 0x9d, 0x64, 0x84, ++ 0xfa, 0xc4, 0xb5, 0x7a, 0xaa, 0x8f, 0xd0, 0xf4, 0x29, 0x0d, 0x66, 0xc6, ++ 0x7c, 0x8d, 0xde, 0x45, 0xe7, 0x53, 0x19, 0xcb, 0x0f, 0x8b, 0xcc, 0x64, ++ 0xdf, 0x81, 0x52, 0xcf, 0xd2, 0xb5, 0xd0, 0x8f, 0x69, 0xc2, 0xac, 0xad, ++ 0xb0, 0x5e, 0x81, 0x7c, 0xa3, 0x27, 0x11, 0xe0, 0x35, 0x5d, 0x92, 0x0d, ++ 0x96, 0x66, 0xf9, 0x86, 0x92, 0x5d, 0x2c, 0x85, 0xb1, 0x3a, 0x2d, 0x00, ++ 0xb1, 0xf8, 0x3f, 0x93, 0xbb, 0x15, 0xd7, 0xd1, 0xf6, 0x56, 0xed, 0x87, ++ 0x7e, 0x7d, 0x71, 0x89, 0xd6, 0x2d, 0x00, 0x4e, 0x49, 0x38, 0xc2, 0x52, ++ 0xb3, 0x61, 0x7c, 0x7d, 0x51, 0x06, 0x9b, 0xce, 0xd8, 0x09, 0x8b, 0x63, ++ 0x8a, 0x75, 0x22, 0xb4, 0xb3, 0xad, 0x12, 0x8e, 0x0f, 0xcf, 0xe0, 0xe3, ++ 0x7f, 0x5a, 0x14, 0xde, 0x22, 0xc3, 0xf8, 0xc1, 0xe3, 0xb7, 0xe5, 0x3a, ++ 0xa0, 0xee, 0x6e, 0x83, 0xd2, 0xc1, 0xac, 0x8c, 0xa5, 0x78, 0xa2, 0x97, ++ 0x68, 0xef, 0x04, 0x38, 0x4a, 0xc9, 0x95, 0x2c, 0x00, 0x5b, 0x63, 0x97, ++ 0x68, 0x27, 0x01, 0x1c, 0xaf, 0x74, 0x48, 0xd0, 0x6e, 0x74, 0x45, 0x2f, ++ 0xc9, 0x9f, 0x84, 0xe7, 0x33, 0x5a, 0xce, 0xa7, 0x33, 0xf6, 0x33, 0x26, ++ 0xb1, 0x28, 0x99, 0xb1, 0x64, 0xad, 0x23, 0x1d, 0xd7, 0x71, 0x16, 0x7d, ++ 0xa6, 0x67, 0x1a, 0x6c, 0x1f, 0xd2, 0x97, 0xcc, 0x62, 0x2c, 0xc3, 0x6a, ++ 0x21, 0x3c, 0x4c, 0x3c, 0x01, 0x78, 0x82, 0x7d, 0x0e, 0x2d, 0x8c, 0x70, ++ 0xb7, 0xc0, 0xf9, 0x58, 0x86, 0x92, 0x8b, 0xed, 0x49, 0xba, 0xa1, 0x48, ++ 0x0b, 0xe0, 0x63, 0xf0, 0x86, 0xb6, 0xc8, 0x6d, 0xa6, 0x71, 0x91, 0x7f, ++ 0x0f, 0xf5, 0x37, 0xf1, 0xef, 0x07, 0x8c, 0xed, 0xee, 0x96, 0xa9, 0x5e, ++ 0x85, 0xd5, 0xd2, 0x67, 0x85, 0x49, 0x60, 0xbd, 0xfa, 0x54, 0xf3, 0x13, ++ 0x88, 0xbf, 0xba, 0x04, 0xa3, 0x91, 0xca, 0xee, 0x6b, 0x85, 0x0c, 0xe7, ++ 0xd1, 0x96, 0xa4, 0xde, 0x0d, 0xf3, 0xd8, 0xf5, 0x6c, 0x79, 0x49, 0xc6, ++ 0xe8, 0xf1, 0x03, 0x56, 0x0d, 0xed, 0x2b, 0x79, 0x23, 0x10, 0x74, 0x32, ++ 0xae, 0xcb, 0xec, 0x4c, 0x81, 0xff, 0x0b, 0x63, 0x2a, 0xec, 0x62, 0x73, ++ 0x18, 0x6b, 0xfe, 0x25, 0x54, 0xfc, 0x1d, 0x6f, 0x87, 0x93, 0x30, 0xfd, ++ 0x0c, 0x8d, 0x80, 0x6d, 0x3b, 0xf2, 0x53, 0x83, 0xfa, 0xdb, 0xb1, 0xbf, ++ 0xbf, 0x9d, 0xd9, 0x8d, 0xcc, 0x3f, 0xfe, 0x7e, 0xeb, 0x8c, 0x1d, 0x1b, ++ 0xb4, 0x62, 0x3d, 0xa4, 0x73, 0x05, 0x73, 0xcf, 0x80, 0x23, 0x24, 0xb2, ++ 0x06, 0x89, 0x01, 0xfe, 0x12, 0x98, 0x97, 0xe8, 0xb3, 0xdb, 0x16, 0x43, ++ 0xfb, 0xa2, 0x3f, 0xa0, 0xd3, 0x0b, 0xb1, 0xa6, 0xe6, 0x2d, 0xd0, 0x2f, ++ 0x55, 0x66, 0x2e, 0x53, 0x16, 0x95, 0xcc, 0x02, 0x65, 0x62, 0x38, 0xac, ++ 0x07, 0xed, 0x89, 0xaf, 0x99, 0xdc, 0xc8, 0x57, 0x7b, 0x4d, 0xd0, 0x0e, ++ 0x43, 0x53, 0x35, 0xbc, 0xdc, 0xab, 0xe1, 0xfd, 0xf5, 0x61, 0xcc, 0x85, ++ 0x7c, 0x3a, 0x15, 0x60, 0x06, 0xe5, 0x31, 0x9b, 0xa3, 0xce, 0x36, 0x91, ++ 0xe6, 0xf1, 0xd2, 0x3c, 0xf2, 0x21, 0x1b, 0xf2, 0xe3, 0x24, 0xe6, 0xa1, ++ 0xf5, 0xe3, 0x99, 0x8b, 0xf6, 0xa3, 0xf6, 0x9b, 0xc2, 0x7a, 0x4d, 0x08, ++ 0x33, 0xed, 0x50, 0x1a, 0xd2, 0x6b, 0xae, 0xac, 0x19, 0x13, 0x9f, 0x3a, ++ 0xdb, 0xbc, 0xf5, 0x48, 0x7f, 0x5f, 0xa3, 0x9d, 0x7d, 0xa2, 0x0d, 0xa0, ++ 0x53, 0x78, 0xe4, 0xba, 0x40, 0xfa, 0xd5, 0xe1, 0x78, 0x73, 0xe0, 0xb8, ++ 0xf9, 0x34, 0x4e, 0x1d, 0xef, 0x5c, 0xa7, 0x61, 0x9f, 0x4c, 0xc0, 0xc3, ++ 0x7b, 0x89, 0x7f, 0x9c, 0xa9, 0x1a, 0xbb, 0x3b, 0x03, 0xc7, 0xb1, 0x37, ++ 0xa5, 0x2c, 0xac, 0xef, 0xd5, 0x97, 0x44, 0xf8, 0xc7, 0xf5, 0x37, 0x1a, ++ 0xd9, 0x27, 0x40, 0x87, 0xff, 0x68, 0x64, 0x54, 0x9e, 0x69, 0xb4, 0xd0, ++ 0xfa, 0xff, 0xd9, 0x98, 0x40, 0xe5, 0x1f, 0x1b, 0x15, 0xaa, 0x3f, 0xdb, ++ 0x98, 0x4e, 0xe5, 0x40, 0xa3, 0x95, 0xea, 0x3f, 0x6a, 0x9c, 0x43, 0xe5, ++ 0xbd, 0xcb, 0x22, 0x72, 0x90, 0xff, 0xeb, 0x3b, 0xe7, 0xb1, 0x4f, 0x8c, ++ 0x1c, 0xed, 0x37, 0xe1, 0x7f, 0x4e, 0x8f, 0xce, 0x31, 0x10, 0x00, 0xf7, ++ 0xcf, 0x1b, 0x9b, 0x8f, 0xf6, 0x0b, 0x3e, 0xea, 0x4f, 0x1e, 0xbb, 0xdd, ++ 0x8b, 0xed, 0xb8, 0xcf, 0xef, 0x73, 0x7a, 0x0e, 0x3e, 0xc8, 0xdc, 0x2d, ++ 0xc9, 0xc4, 0x97, 0x1b, 0x2c, 0x31, 0xa3, 0xe9, 0x0f, 0xe7, 0x33, 0xe1, ++ 0xf9, 0x06, 0x23, 0xd8, 0x12, 0x0f, 0xe0, 0xe9, 0x58, 0x8e, 0x44, 0xf3, ++ 0x0f, 0x4e, 0xe2, 0x70, 0xb3, 0x55, 0x47, 0xf3, 0xd9, 0x35, 0x6c, 0x07, ++ 0x8e, 0x3f, 0x96, 0xa3, 0xe7, 0xf3, 0x4f, 0xd7, 0x54, 0x62, 0xbb, 0x3d, ++ 0x86, 0xcf, 0xdb, 0x9f, 0x06, 0x30, 0xec, 0xa7, 0x68, 0xce, 0xbc, 0x17, ++ 0x11, 0x4f, 0xf6, 0x38, 0xa8, 0xcf, 0xf2, 0xc3, 0xfd, 0xb7, 0xf3, 0x76, ++ 0xfb, 0x64, 0x5e, 0xaf, 0xee, 0x57, 0x6d, 0xaf, 0xb3, 0x59, 0x68, 0x5e, ++ 0x95, 0xee, 0x83, 0x3a, 0x58, 0x3f, 0x83, 0xf8, 0x9d, 0xe6, 0x57, 0xfb, ++ 0x7f, 0x96, 0xc7, 0xe5, 0x30, 0xb4, 0xbf, 0x3b, 0x55, 0x53, 0xe4, 0x1e, ++ 0x03, 0x1f, 0x1a, 0x1b, 0xef, 0x4f, 0x72, 0x01, 0xf8, 0x70, 0xa1, 0x1c, ++ 0x24, 0x07, 0xc8, 0x45, 0x9d, 0x42, 0x72, 0xa1, 0xf2, 0xa1, 0xca, 0x7f, ++ 0xbb, 0x6d, 0x1c, 0x8f, 0xa9, 0x06, 0xc1, 0xe7, 0xe1, 0x20, 0x07, 0x31, ++ 0x24, 0x07, 0x34, 0x2e, 0x31, 0x1e, 0xe4, 0x40, 0x22, 0xbc, 0xd8, 0x19, ++ 0x9c, 0x67, 0xaf, 0x24, 0xe4, 0x25, 0x54, 0x1e, 0xa0, 0x44, 0x3d, 0xae, ++ 0xca, 0x83, 0x2a, 0x07, 0x2a, 0xbf, 0x27, 0x82, 0x9c, 0x49, 0x31, 0xfe, ++ 0x73, 0x7c, 0x2f, 0x84, 0x5f, 0xd5, 0xf2, 0x94, 0x95, 0xd3, 0xa5, 0x37, ++ 0x2e, 0xe2, 0x17, 0x44, 0xd7, 0x6e, 0x9d, 0x05, 0x54, 0x21, 0xf4, 0x07, ++ 0x42, 0xc6, 0x20, 0x7c, 0x4f, 0x8e, 0x1d, 0xc6, 0x15, 0x3c, 0x6e, 0x6e, ++ 0x18, 0x4b, 0x7f, 0xdd, 0xb4, 0xfe, 0x8d, 0x78, 0x50, 0xf5, 0xc1, 0x38, ++ 0x78, 0x18, 0x75, 0x7e, 0x3d, 0x2f, 0xbf, 0xed, 0xf9, 0x49, 0xbf, 0xa1, ++ 0xde, 0x46, 0xbe, 0x1d, 0x43, 0x5f, 0x7d, 0x66, 0x55, 0xf5, 0x15, 0xe7, ++ 0x5b, 0x9d, 0xcd, 0xfe, 0xa9, 0x15, 0xf9, 0x55, 0x32, 0x69, 0xa5, 0x28, ++ 0x28, 0x4d, 0x9c, 0x6f, 0x42, 0xcf, 0x7f, 0x2c, 0x87, 0xcb, 0x8d, 0xca, ++ 0x3f, 0xbb, 0x6d, 0x8c, 0xdb, 0x4b, 0x3c, 0x67, 0xca, 0x68, 0x7d, 0xa7, ++ 0x9e, 0x67, 0xe4, 0x9c, 0xab, 0x18, 0xe9, 0xbd, 0xd4, 0x30, 0x5e, 0x1f, ++ 0x4a, 0x5f, 0xf5, 0x5c, 0x01, 0x7a, 0xef, 0xcf, 0xb8, 0x2f, 0x15, 0x9f, ++ 0x8c, 0x79, 0x6c, 0x16, 0x98, 0x67, 0x4a, 0xad, 0xd9, 0xba, 0x25, 0xd9, ++ 0xcf, 0xbf, 0xbe, 0x89, 0xd7, 0x2b, 0xd0, 0x7e, 0x6d, 0xb6, 0x2a, 0xb4, ++ 0x9f, 0xe7, 0x35, 0x32, 0xd1, 0x5f, 0xb5, 0x27, 0x23, 0xf5, 0x92, 0xbc, ++ 0x7c, 0x71, 0x46, 0x90, 0x9d, 0x61, 0x16, 0xa0, 0xe3, 0xd0, 0x71, 0x03, ++ 0xc9, 0xb7, 0x57, 0xc3, 0x2a, 0x5f, 0x81, 0x71, 0xad, 0xb8, 0xd4, 0x9d, ++ 0xfe, 0x73, 0xcf, 0x16, 0xf4, 0x1b, 0x5e, 0x32, 0x43, 0xb3, 0x0e, 0xf6, ++ 0xe5, 0xfb, 0x93, 0xd9, 0x85, 0x76, 0xcb, 0x37, 0x79, 0xe8, 0xac, 0x04, ++ 0xe3, 0x7d, 0x3b, 0x74, 0xcc, 0x45, 0xfe, 0x83, 0xfd, 0x47, 0x52, 0x1c, ++ 0x63, 0x0f, 0x82, 0x4d, 0x41, 0xbb, 0x74, 0x15, 0xf4, 0x1c, 0x4b, 0x63, ++ 0x4c, 0x7e, 0xee, 0xcb, 0xb3, 0x12, 0xec, 0xbb, 0xe2, 0x39, 0x99, 0x19, ++ 0x00, 0x75, 0x3e, 0x50, 0xdb, 0x32, 0x8c, 0xab, 0x7f, 0x3a, 0xc2, 0x6d, ++ 0xe4, 0xe3, 0x18, 0x83, 0x71, 0xb5, 0x62, 0x5c, 0xd3, 0x8e, 0xcf, 0xef, ++ 0x45, 0xfe, 0xba, 0x00, 0xfc, 0x69, 0x80, 0xf6, 0x4f, 0x4c, 0x75, 0xd3, ++ 0x59, 0x26, 0x63, 0x0b, 0x9e, 0xd3, 0x11, 0x1e, 0x2b, 0x22, 0xf4, 0x6e, ++ 0xac, 0x7f, 0x63, 0xc7, 0x53, 0xa7, 0x96, 0x01, 0x7c, 0xa1, 0x5d, 0x52, ++ 0xd0, 0xdf, 0x28, 0x94, 0xcd, 0xd4, 0x5e, 0xfd, 0x92, 0xec, 0xc6, 0x75, ++ 0x6a, 0xcd, 0x85, 0x97, 0x24, 0xf0, 0x73, 0x7c, 0xed, 0xcd, 0xcf, 0x84, ++ 0x41, 0xbd, 0xf3, 0x80, 0x8e, 0x99, 0x60, 0x5c, 0x61, 0xbb, 0x64, 0xf5, ++ 0xc2, 0xfc, 0xab, 0x3c, 0x11, 0x88, 0x19, 0x56, 0xb1, 0x5d, 0xf7, 0xd1, ++ 0x40, 0xba, 0x5f, 0x6f, 0xfe, 0x50, 0xd8, 0xb1, 0xca, 0xbd, 0x92, 0x1b, ++ 0x38, 0x86, 0x55, 0xee, 0x0a, 0x6e, 0xaf, 0xde, 0x1b, 0x0c, 0xd7, 0x32, ++ 0xad, 0x1f, 0x86, 0xf9, 0xb3, 0x6c, 0x11, 0xb1, 0x17, 0xee, 0x00, 0x60, ++ 0x26, 0xb3, 0xdd, 0x44, 0xba, 0x6d, 0x8f, 0x41, 0x63, 0x35, 0xa2, 0xb7, ++ 0x43, 0xf9, 0x0a, 0xcd, 0x36, 0xe9, 0xc7, 0x35, 0x5c, 0x1f, 0x33, 0xf6, ++ 0x45, 0xdc, 0xdd, 0xc0, 0x97, 0xf2, 0xf1, 0x2f, 0x93, 0x3e, 0x32, 0x73, ++ 0x78, 0xb1, 0x80, 0xcf, 0x01, 0xfc, 0xd9, 0x97, 0x1c, 0xff, 0x2a, 0xde, ++ 0xea, 0x84, 0xce, 0xff, 0x6c, 0x12, 0xcb, 0xf1, 0xc0, 0x39, 0xeb, 0x8e, ++ 0x9b, 0x2c, 0x2e, 0x38, 0x58, 0x5d, 0x97, 0x4c, 0xe7, 0xf0, 0x79, 0xa2, ++ 0x08, 0xcf, 0xf5, 0x61, 0x03, 0x77, 0x91, 0x9c, 0x1e, 0x95, 0x2d, 0xe8, ++ 0x87, 0x6d, 0xee, 0x94, 0x5d, 0xd8, 0xee, 0xec, 0x36, 0xed, 0xd1, 0xc0, ++ 0x39, 0xeb, 0x3a, 0x24, 0xa6, 0x45, 0xb8, 0xd3, 0xe0, 0xe6, 0x78, 0xba, ++ 0x56, 0x81, 0xed, 0xab, 0x3a, 0x4d, 0x16, 0x05, 0xdb, 0x8f, 0x1a, 0x98, ++ 0x0c, 0xe3, 0x7d, 0x40, 0x37, 0x13, 0xd2, 0x71, 0xea, 0x00, 0xd1, 0x1f, ++ 0xe9, 0xea, 0x92, 0x68, 0x0b, 0x3f, 0x92, 0xf2, 0xfc, 0xf4, 0x97, 0x91, ++ 0x5e, 0xb1, 0x7e, 0x7a, 0x35, 0xed, 0xe0, 0xfb, 0xb9, 0x70, 0x80, 0xd3, ++ 0xa7, 0x50, 0x7e, 0x58, 0x4b, 0xf4, 0x6a, 0x96, 0x58, 0x7c, 0x00, 0x9d, ++ 0x7f, 0xaf, 0x79, 0x79, 0x84, 0x5e, 0xd8, 0x6f, 0xc1, 0x73, 0x7f, 0xe8, ++ 0x41, 0x3a, 0x57, 0xc0, 0xfe, 0x0c, 0x0a, 0xd2, 0x5d, 0x26, 0x3a, 0x5f, ++ 0x00, 0xfa, 0xe0, 0xbc, 0xfa, 0xe3, 0x9f, 0x24, 0x0d, 0x98, 0xfd, 0xf4, ++ 0x96, 0x81, 0xde, 0xbf, 0x52, 0xc7, 0x43, 0xff, 0x55, 0xb7, 0xa0, 0x77, ++ 0x25, 0x73, 0x6d, 0x44, 0x7f, 0xee, 0xdb, 0xd2, 0x39, 0x5c, 0xc8, 0x3f, ++ 0xf8, 0xbd, 0x17, 0x9e, 0x47, 0xbf, 0x37, 0x42, 0x6f, 0x45, 0x3e, 0x8c, ++ 0x15, 0xfe, 0xf1, 0xc4, 0x9a, 0xfe, 0x93, 0xb1, 0xb0, 0x60, 0x59, 0xcc, ++ 0x15, 0xe7, 0x6a, 0xa8, 0x9f, 0x91, 0xf0, 0x0a, 0x4b, 0x05, 0x3f, 0x41, ++ 0x8a, 0x76, 0x3c, 0x64, 0x83, 0x71, 0x67, 0x17, 0xbe, 0xfb, 0x18, 0x92, ++ 0xa3, 0x6f, 0xd1, 0xcb, 0x36, 0xe4, 0x8b, 0x26, 0xdd, 0x40, 0xeb, 0xb3, ++ 0x50, 0xe1, 0x8a, 0x0e, 0xb7, 0xa2, 0x0c, 0x0e, 0x26, 0x2f, 0xde, 0xf5, ++ 0x2a, 0xac, 0x93, 0x1f, 0x73, 0x3d, 0xe9, 0x10, 0xca, 0xcb, 0xef, 0x0c, ++ 0x16, 0x64, 0xa7, 0x26, 0x21, 0x8f, 0xf8, 0x67, 0x04, 0xfa, 0x3b, 0x19, ++ 0xc7, 0x37, 0xd0, 0xf1, 0x1c, 0x9e, 0xdf, 0xd9, 0x6d, 0xf0, 0x1a, 0x00, ++ 0x8f, 0xac, 0xbd, 0xc0, 0x3e, 0xe2, 0x0f, 0x4c, 0x47, 0x7b, 0xec, 0xd1, ++ 0xa3, 0x9e, 0x2a, 0xd0, 0x0f, 0x95, 0xad, 0x46, 0x7f, 0x1c, 0xe6, 0xc3, ++ 0x75, 0x24, 0x60, 0x23, 0x94, 0xeb, 0x9a, 0xee, 0xdf, 0x9f, 0x91, 0x60, ++ 0x9c, 0xa4, 0xc4, 0xb2, 0x52, 0x84, 0x8d, 0x66, 0xaf, 0x8c, 0xf3, 0xb4, ++ 0xe9, 0xae, 0x8e, 0x9c, 0x1b, 0xe6, 0x91, 0x2c, 0xef, 0x52, 0xbf, 0x5d, ++ 0xb6, 0xe9, 0xb4, 0x8f, 0x94, 0xf8, 0xef, 0x29, 0xa8, 0x7f, 0x9a, 0x96, ++ 0x32, 0x47, 0x58, 0xca, 0xd7, 0xe9, 0x79, 0x46, 0x7a, 0xfe, 0x05, 0x9d, ++ 0xd0, 0xef, 0xe3, 0xf9, 0x7f, 0xe3, 0xe8, 0x7b, 0xd5, 0xef, 0x63, 0xae, ++ 0x29, 0xd1, 0x17, 0x60, 0x4e, 0xc4, 0x05, 0x97, 0x1f, 0xae, 0x77, 0x56, ++ 0xcd, 0x61, 0xe2, 0x4f, 0xc8, 0x85, 0x80, 0x2b, 0xd7, 0xbb, 0x22, 0x8d, ++ 0xd0, 0x79, 0xd5, 0x1d, 0xd6, 0x04, 0x3c, 0xff, 0xa7, 0xc8, 0x67, 0x91, ++ 0xc8, 0x7f, 0xef, 0x68, 0x27, 0xc0, 0xbe, 0x6a, 0x5b, 0x25, 0xa2, 0x5b, ++ 0x1d, 0xf2, 0x0f, 0x9c, 0xeb, 0x24, 0xda, 0x37, 0xa8, 0x1f, 0xf4, 0x08, ++ 0x3d, 0xf2, 0x52, 0x6f, 0xfe, 0x84, 0x58, 0x2c, 0x25, 0x2b, 0x48, 0x2a, ++ 0xab, 0xea, 0x96, 0xad, 0x5e, 0x68, 0xaf, 0xea, 0xe4, 0xfc, 0x34, 0x8a, ++ 0x6f, 0x84, 0xfe, 0xa8, 0x6e, 0xe3, 0xfa, 0x63, 0x14, 0x1f, 0xb5, 0x01, ++ 0x1c, 0xe0, 0xa7, 0xd5, 0x21, 0x5f, 0xa9, 0x30, 0xd0, 0xfb, 0xa8, 0x5f, ++ 0x7f, 0xcc, 0xba, 0x09, 0xfb, 0x7d, 0x71, 0x36, 0x13, 0xf4, 0xe6, 0x7a, ++ 0xa2, 0x40, 0xce, 0x88, 0x1a, 0x00, 0x7e, 0x19, 0x66, 0x4a, 0x94, 0x25, ++ 0x23, 0xc0, 0x6e, 0x49, 0xdc, 0xdf, 0x52, 0xf5, 0xca, 0x6d, 0x3b, 0x40, ++ 0xd5, 0x07, 0xac, 0x3b, 0xd3, 0x6d, 0x64, 0xda, 0x80, 0x75, 0xef, 0x38, ++ 0x60, 0x09, 0x82, 0x67, 0x79, 0x12, 0x82, 0xfa, 0x7f, 0xa7, 0x53, 0x09, ++ 0x6a, 0xb7, 0x79, 0xd3, 0x83, 0xda, 0xb3, 0x4f, 0x59, 0x83, 0xe0, 0xdc, ++ 0xde, 0x39, 0x41, 0xfd, 0x67, 0x9f, 0xb1, 0x07, 0xc1, 0x77, 0x0e, 0x14, ++ 0x05, 0xf5, 0xff, 0xee, 0xc5, 0x92, 0x20, 0x78, 0x38, 0x03, 0xce, 0x33, ++ 0x96, 0xdf, 0x21, 0xca, 0x1f, 0x26, 0x48, 0x41, 0xfd, 0x17, 0x2a, 0xa6, ++ 0xa0, 0xf9, 0x8b, 0xd3, 0xa3, 0x83, 0xe0, 0x61, 0xb3, 0xc0, 0x8f, 0xf0, ++ 0x03, 0x55, 0xff, 0xf4, 0xa2, 0x8d, 0xfb, 0x41, 0xa1, 0xa5, 0x8a, 0xdf, ++ 0x1f, 0x5b, 0x83, 0xd7, 0x51, 0xe3, 0xe2, 0x9f, 0xcc, 0x09, 0x5e, 0x6f, ++ 0xb1, 0x3d, 0x78, 0xbd, 0x6f, 0x4a, 0x97, 0x7d, 0xe0, 0xf7, 0x6b, 0xc1, ++ 0xaf, 0x3f, 0x00, 0xf6, 0x11, 0xcb, 0xdf, 0x82, 0xff, 0xaf, 0x05, 0xbf, ++ 0xbe, 0x0d, 0xfc, 0x7f, 0x84, 0xff, 0x05, 0xfc, 0x7f, 0x2c, 0x3d, 0xe0, ++ 0xff, 0x63, 0xfd, 0x2b, 0xe0, 0xff, 0x23, 0xdc, 0x0e, 0xfe, 0x3f, 0xc2, ++ 0x47, 0x20, 0x5e, 0x41, 0xb8, 0xb3, 0xb1, 0x88, 0xca, 0xa3, 0x8d, 0x25, ++ 0x54, 0x7f, 0x2b, 0xfc, 0xf5, 0x88, 0x75, 0x4f, 0x89, 0x75, 0x4f, 0x8b, ++ 0x75, 0xff, 0x5a, 0x3c, 0xa9, 0xa5, 0xb3, 0x68, 0x86, 0xe6, 0x2b, 0x90, ++ 0xd3, 0x79, 0x31, 0x97, 0xf4, 0xa8, 0x87, 0xed, 0x6b, 0x06, 0x0a, 0x31, ++ 0x0f, 0x30, 0xf4, 0x96, 0xcc, 0x5a, 0x50, 0x40, 0x1c, 0xee, 0x53, 0x8d, ++ 0xb1, 0x68, 0x8f, 0x26, 0x30, 0xf4, 0x5b, 0x58, 0xc9, 0xd0, 0xdb, 0x1a, ++ 0x84, 0x3b, 0x52, 0x2c, 0x5b, 0x14, 0xb4, 0x43, 0xff, 0xfe, 0x1e, 0xb6, ++ 0xfb, 0xda, 0x65, 0x05, 0xf5, 0xf9, 0x89, 0xce, 0x8f, 0x23, 0x71, 0x9e, ++ 0xab, 0x5f, 0x81, 0x1c, 0x66, 0xe3, 0xb8, 0x8f, 0x23, 0x31, 0x3e, 0xae, ++ 0xbd, 0xce, 0x08, 0xde, 0x02, 0xed, 0x0a, 0xc0, 0x0b, 0x0f, 0x81, 0x62, ++ 0x20, 0x7f, 0x06, 0xf4, 0x1a, 0xf6, 0x4f, 0x55, 0x61, 0xb7, 0x9e, 0x41, ++ 0x59, 0xd2, 0x76, 0x48, 0x8f, 0xf4, 0xa8, 0x39, 0x70, 0x88, 0xda, 0xdf, ++ 0xf2, 0xe8, 0x82, 0xdb, 0x0f, 0x34, 0x07, 0xb5, 0x5b, 0xb0, 0x3f, 0x94, ++ 0x35, 0x5a, 0x37, 0xc5, 0xf7, 0x97, 0x3b, 0xd5, 0xf9, 0xbc, 0xd4, 0xbf, ++ 0x36, 0x55, 0xb2, 0xa3, 0x5f, 0x7c, 0xf9, 0xc0, 0xbf, 0xc7, 0x55, 0x60, ++ 0xbf, 0xb6, 0xf7, 0xe3, 0x56, 0x7e, 0x0d, 0xbe, 0x3f, 0x3b, 0xf2, 0x72, ++ 0x06, 0xea, 0x75, 0x27, 0xd8, 0x61, 0xaf, 0xd9, 0x3f, 0x8f, 0xb3, 0x4b, ++ 0x27, 0x60, 0xbe, 0xef, 0xda, 0xd4, 0x43, 0x85, 0x31, 0x68, 0x08, 0xda, ++ 0x24, 0x36, 0x03, 0x8a, 0xab, 0x6c, 0x2b, 0x5b, 0x07, 0xfa, 0xae, 0xa6, ++ 0xb3, 0xb5, 0x16, 0xf5, 0x50, 0x4d, 0xfa, 0x32, 0x1d, 0x4b, 0x26, 0x7d, ++ 0x24, 0xf2, 0x0d, 0xa0, 0x6d, 0xd1, 0x5f, 0xc2, 0xe0, 0x1e, 0xf0, 0x77, ++ 0xd5, 0xf3, 0x79, 0xe4, 0x4a, 0x98, 0xf7, 0x35, 0xcf, 0xc9, 0xbb, 0xec, ++ 0x48, 0xbf, 0xee, 0x37, 0x22, 0x71, 0xdd, 0xc1, 0x76, 0x39, 0x28, 0x9e, ++ 0x59, 0x94, 0xc5, 0xfd, 0xd6, 0x45, 0x59, 0x7a, 0xa2, 0xe3, 0xd5, 0xf6, ++ 0x37, 0x22, 0x15, 0x68, 0xdf, 0xec, 0x79, 0x83, 0xe3, 0x5b, 0xeb, 0xa5, ++ 0x73, 0x9f, 0x10, 0xf0, 0x20, 0x94, 0x84, 0xe7, 0x4e, 0x99, 0xce, 0x5d, ++ 0xf5, 0x95, 0x86, 0xf0, 0xaf, 0xce, 0x77, 0x4f, 0x96, 0x4c, 0xf3, 0x2d, ++ 0xec, 0x9c, 0x11, 0x81, 0xe7, 0xea, 0xf3, 0xf0, 0xf5, 0x96, 0x67, 0x29, ++ 0x34, 0xff, 0xc2, 0xd4, 0x15, 0xe5, 0xb8, 0xff, 0xd3, 0x09, 0x4b, 0x73, ++ 0x65, 0xf2, 0xf3, 0x40, 0x31, 0xa3, 0x5e, 0xbd, 0xbd, 0xb8, 0x15, 0xf3, ++ 0x03, 0x35, 0x1e, 0xd9, 0x3e, 0x56, 0xbc, 0xb5, 0x5a, 0xcc, 0xdb, 0xa3, ++ 0xe3, 0x7c, 0xf8, 0x56, 0xea, 0xe1, 0x9e, 0xc9, 0xc0, 0x1f, 0xa7, 0x8b, ++ 0x26, 0xd8, 0x48, 0xe7, 0x8b, 0x7e, 0x55, 0x59, 0xdc, 0x1f, 0x2f, 0xd4, ++ 0x3b, 0x52, 0xd1, 0x2e, 0xf4, 0x99, 0x95, 0x08, 0xe4, 0xe3, 0x47, 0x8b, ++ 0x52, 0x22, 0x90, 0xae, 0x27, 0xb0, 0xc4, 0xfa, 0xa2, 0x3d, 0x7a, 0x07, ++ 0x94, 0xd5, 0xed, 0x7c, 0xbd, 0x3e, 0x4b, 0x6f, 0x24, 0xf2, 0x5b, 0x5f, ++ 0x7b, 0xb6, 0x8c, 0x7e, 0x8b, 0x3a, 0xdf, 0x4a, 0xb1, 0xee, 0x08, 0x5f, ++ 0x8f, 0xd0, 0xcd, 0x45, 0x74, 0xaa, 0x74, 0x37, 0x9b, 0x71, 0x1e, 0x3f, ++ 0xfd, 0x78, 0xfd, 0xf2, 0x2c, 0x9e, 0x2f, 0x3a, 0xed, 0x7e, 0xff, 0x5e, ++ 0xf4, 0x53, 0xfa, 0xd2, 0xc3, 0xad, 0x48, 0x97, 0x1e, 0x3d, 0xa3, 0xf8, ++ 0xb6, 0x06, 0xe8, 0x8a, 0xf6, 0xa0, 0xaf, 0x3b, 0xb1, 0x19, 0xf1, 0xa0, ++ 0xae, 0xb7, 0x3c, 0x4b, 0xc4, 0xc9, 0xe9, 0x1a, 0xa2, 0xab, 0xaf, 0x53, ++ 0x27, 0xfa, 0x2d, 0x6b, 0x65, 0x41, 0xfd, 0x78, 0xfc, 0x7c, 0x75, 0x6f, ++ 0xf0, 0x7e, 0x2c, 0xee, 0x73, 0xbf, 0x59, 0x86, 0x76, 0xe9, 0x05, 0xf0, ++ 0xab, 0xa1, 0xba, 0x56, 0xd7, 0x10, 0x87, 0xe7, 0xff, 0x74, 0x57, 0xf0, ++ 0xfe, 0x2a, 0x05, 0x9e, 0x6b, 0x75, 0xde, 0xb8, 0xb8, 0x00, 0x7e, 0xad, ++ 0xed, 0x1a, 0x91, 0x17, 0x33, 0xf1, 0x77, 0x97, 0x2a, 0x1f, 0x0a, 0xd1, ++ 0x53, 0xa5, 0x63, 0x5f, 0x3a, 0xf7, 0xdb, 0xfa, 0x12, 0x0c, 0x6e, 0x8c, ++ 0x17, 0x6b, 0x0f, 0xb5, 0x12, 0x5f, 0x8f, 0xce, 0xef, 0xf4, 0x26, 0xa3, ++ 0x9f, 0x9f, 0xf8, 0x90, 0x91, 0xf2, 0x86, 0xb7, 0x8a, 0x67, 0x55, 0x3f, ++ 0x20, 0x20, 0xee, 0x61, 0x18, 0xc7, 0xe9, 0x8a, 0x52, 0x72, 0x35, 0xd3, ++ 0xfd, 0xf6, 0x7e, 0xd0, 0x66, 0x7f, 0x3e, 0x6b, 0x22, 0xc6, 0x43, 0x25, ++ 0x14, 0xef, 0xf5, 0xb1, 0xa1, 0x0a, 0x34, 0xfe, 0x4e, 0xf4, 0x83, 0xa3, ++ 0x50, 0xef, 0xfe, 0xf1, 0x19, 0x5c, 0x77, 0xb8, 0x1d, 0xfc, 0x3d, 0x58, ++ 0xd7, 0x69, 0xec, 0x5c, 0x74, 0x1e, 0xfc, 0xac, 0x61, 0x2b, 0x08, 0x0a, ++ 0xec, 0x7b, 0x78, 0x97, 0xce, 0x2d, 0xe2, 0x13, 0x33, 0xfa, 0xa7, 0x15, ++ 0xc2, 0x3f, 0xfd, 0x54, 0x71, 0xe4, 0xc9, 0x60, 0x5f, 0x9d, 0xeb, 0x35, ++ 0x74, 0xbe, 0xda, 0x8c, 0x30, 0xee, 0xd7, 0x0a, 0x3d, 0xf9, 0xd9, 0xa1, ++ 0xe4, 0x9f, 0x20, 0xbf, 0xd6, 0x9e, 0x92, 0x2d, 0x46, 0xf4, 0x43, 0x21, ++ 0x6e, 0x21, 0xb8, 0x8d, 0xfb, 0x05, 0x75, 0x9e, 0xe4, 0x7f, 0x9a, 0x8b, ++ 0xfe, 0x76, 0x9b, 0x8e, 0xfc, 0x00, 0xd5, 0xef, 0x70, 0x0a, 0xbf, 0xe3, ++ 0x82, 0xf0, 0x67, 0x2f, 0xac, 0x1f, 0xd2, 0x93, 0xbf, 0x7a, 0x5c, 0x62, ++ 0x4f, 0xc1, 0x3e, 0x2a, 0x3b, 0xb7, 0xf5, 0x24, 0x42, 0xbb, 0x33, 0x63, ++ 0x11, 0xf9, 0xab, 0x4e, 0xb9, 0x8d, 0xf2, 0x8f, 0xab, 0x76, 0x04, 0xfb, ++ 0x05, 0x55, 0xee, 0x60, 0xb8, 0xe6, 0x40, 0x30, 0xec, 0x0c, 0xf1, 0x1b, ++ 0xd4, 0xb8, 0xed, 0x44, 0xd6, 0x88, 0xff, 0x30, 0x13, 0xe3, 0x8f, 0x02, ++ 0x79, 0x6e, 0x3c, 0xca, 0xc1, 0x07, 0x82, 0x9e, 0x6a, 0x3c, 0xb2, 0x76, ++ 0x96, 0x35, 0x1e, 0xe5, 0x7d, 0xb3, 0x56, 0x59, 0xa4, 0xe6, 0x03, 0x10, ++ 0x4f, 0xf5, 0xc7, 0x0f, 0x57, 0xe1, 0x7e, 0xdd, 0xb5, 0x61, 0x56, 0x8a, ++ 0x0b, 0xd6, 0x1d, 0x25, 0x7c, 0x0e, 0x7e, 0xc1, 0xe3, 0x8e, 0xc1, 0x04, ++ 0xc6, 0xfd, 0x23, 0xc6, 0xf1, 0x3a, 0xd8, 0xc9, 0xf9, 0xbb, 0x5e, 0x27, ++ 0xf1, 0x38, 0x03, 0xd8, 0x95, 0xe6, 0x33, 0x4a, 0xee, 0xf5, 0xd0, 0x34, ++ 0xe8, 0x1a, 0x8e, 0x24, 0xbd, 0xc4, 0x58, 0x11, 0xca, 0xc3, 0x9a, 0xa5, ++ 0x3c, 0x8e, 0xb4, 0x63, 0xce, 0x15, 0xca, 0x17, 0x84, 0x5e, 0x0a, 0xb5, ++ 0x97, 0xdf, 0xd7, 0x0e, 0xc8, 0xd1, 0x01, 0xfa, 0xe1, 0x7c, 0x16, 0xf7, ++ 0x37, 0xf3, 0xf5, 0xcc, 0x81, 0x76, 0x6a, 0x6d, 0x84, 0x95, 0xec, 0xd6, ++ 0x34, 0x23, 0xf7, 0xb7, 0x0b, 0x1e, 0xf6, 0xd8, 0x90, 0x0f, 0xa6, 0x41, ++ 0x7c, 0x6c, 0x08, 0xc8, 0x67, 0x4f, 0x33, 0x0f, 0x49, 0xd8, 0x6f, 0xef, ++ 0x23, 0x10, 0xe2, 0x66, 0xfa, 0xe3, 0xfb, 0xc5, 0x5a, 0x8b, 0x2e, 0x3a, ++ 0xc0, 0xee, 0x31, 0xb6, 0x9e, 0xfa, 0xab, 0xf3, 0x83, 0x26, 0xe1, 0xe3, ++ 0x6f, 0x35, 0xbf, 0x05, 0xe6, 0x37, 0xfb, 0xe7, 0x07, 0x7c, 0x47, 0x21, ++ 0xbe, 0x3f, 0xcf, 0xb1, 0x92, 0x3d, 0x4e, 0x5a, 0xcc, 0x58, 0x2f, 0xc9, ++ 0x63, 0x03, 0xc9, 0xa3, 0x7a, 0x9e, 0xab, 0xc0, 0x67, 0x98, 0x8f, 0xc5, ++ 0x9c, 0x09, 0xd2, 0xad, 0x76, 0xd7, 0xeb, 0x94, 0x07, 0x76, 0xb2, 0x5e, ++ 0x8a, 0x47, 0x0a, 0x23, 0xf9, 0x3e, 0x0a, 0x71, 0x3f, 0x08, 0x87, 0xf1, ++ 0x92, 0x65, 0x73, 0x7c, 0xd9, 0xb3, 0xb9, 0xfe, 0x58, 0x9b, 0x1d, 0x6c, ++ 0x97, 0xbb, 0xb2, 0xed, 0x52, 0x36, 0x94, 0x3b, 0xb2, 0x1d, 0xba, 0x6c, ++ 0xd2, 0x67, 0x16, 0xe2, 0xcb, 0xb5, 0x82, 0x57, 0xc0, 0x4f, 0x89, 0x1f, ++ 0x18, 0x43, 0xef, 0xae, 0x79, 0x97, 0xc7, 0x55, 0x9f, 0x83, 0x1c, 0xa0, ++ 0x9c, 0xdf, 0xdf, 0x20, 0x29, 0xa9, 0x41, 0x7e, 0x10, 0xe7, 0xef, 0x7a, ++ 0x5e, 0xc5, 0xae, 0x30, 0x4f, 0xff, 0x5c, 0xc4, 0x83, 0xcb, 0xde, 0x9b, ++ 0x1e, 0x87, 0x71, 0x14, 0x97, 0xab, 0xe5, 0xeb, 0x4c, 0x4a, 0x6a, 0x00, ++ 0x9f, 0xd6, 0x23, 0x9f, 0x03, 0x5e, 0x2a, 0x2d, 0x55, 0x3f, 0x42, 0xbf, ++ 0xdb, 0xb1, 0x2e, 0x4e, 0xc1, 0x7c, 0x7f, 0x3d, 0xf2, 0xfd, 0x74, 0x44, ++ 0x23, 0xe7, 0xeb, 0x58, 0xf8, 0x87, 0xf1, 0xc5, 0x28, 0x3e, 0xf7, 0x04, ++ 0xc3, 0xf0, 0xb7, 0x0b, 0xf9, 0xab, 0x8e, 0x19, 0xac, 0x68, 0x47, 0xea, ++ 0x3b, 0x43, 0xdb, 0xad, 0x5a, 0xcc, 0xeb, 0xa4, 0x64, 0x83, 0x1c, 0x84, ++ 0xfb, 0xe5, 0x20, 0x49, 0xf0, 0x65, 0xb3, 0x43, 0x72, 0xa3, 0xde, 0x6f, ++ 0xbe, 0xa1, 0xe5, 0x79, 0xac, 0x52, 0x89, 0xf2, 0x56, 0xf7, 0x40, 0x25, ++ 0xf2, 0x25, 0xfd, 0x61, 0xbf, 0xca, 0x79, 0x6e, 0x9c, 0xff, 0x1e, 0x00, ++ 0x31, 0x1e, 0x62, 0xdb, 0x63, 0x49, 0x6e, 0xa8, 0x11, 0xf4, 0xc8, 0xdf, ++ 0x8b, 0xf3, 0xde, 0xa3, 0xf5, 0xbe, 0x8e, 0x72, 0x7c, 0x52, 0xe7, 0x49, ++ 0xc6, 0x7c, 0xca, 0x49, 0xa7, 0xd1, 0x8a, 0xf3, 0x2f, 0x65, 0xe0, 0x70, ++ 0x80, 0x7e, 0x29, 0x65, 0xbd, 0x54, 0xf6, 0x87, 0xd7, 0x75, 0x78, 0x69, ++ 0x72, 0xd7, 0x54, 0x8c, 0x9b, 0x3f, 0x70, 0x18, 0x28, 0x8f, 0xd3, 0xbc, ++ 0xa1, 0x25, 0x02, 0xf5, 0x69, 0x26, 0xdb, 0x60, 0xb9, 0x90, 0x8e, 0xc6, ++ 0x9d, 0x1d, 0xb8, 0x99, 0x3d, 0xbe, 0x5f, 0x01, 0x8c, 0xc4, 0x2e, 0xa8, ++ 0x74, 0xa1, 0xbc, 0xd0, 0x56, 0x11, 0x87, 0x72, 0xba, 0xee, 0xc8, 0xb6, ++ 0xcf, 0xcb, 0xce, 0x1d, 0x7f, 0x7c, 0xcd, 0x1f, 0x3a, 0xee, 0xc2, 0x90, ++ 0xa2, 0xe6, 0x17, 0xad, 0xfa, 0x78, 0xce, 0x36, 0xbd, 0xe9, 0x79, 0x7e, ++ 0xfa, 0xd5, 0x33, 0x4f, 0x3a, 0xee, 0x57, 0xa5, 0xd7, 0x08, 0xfd, 0x60, ++ 0xcf, 0x53, 0x00, 0x0f, 0x4b, 0xd8, 0x50, 0x1e, 0xc6, 0x35, 0x2a, 0xdd, ++ 0x8c, 0xf0, 0x6f, 0x2c, 0xba, 0xa9, 0xf8, 0x4c, 0xd2, 0x0d, 0xfd, 0x14, ++ 0x51, 0x06, 0x76, 0x89, 0xf4, 0x4b, 0x28, 0x3d, 0x55, 0xfc, 0xd6, 0xb1, ++ 0x06, 0x1d, 0xcf, 0x73, 0x35, 0xbc, 0xb7, 0x14, 0xfa, 0xdf, 0xb7, 0x41, ++ 0xa3, 0xa0, 0x7f, 0x38, 0x8a, 0xbe, 0xb7, 0xa0, 0x83, 0xd7, 0xc4, 0x9b, ++ 0xbc, 0x11, 0x12, 0xc5, 0x9b, 0xe3, 0xd1, 0x45, 0xa5, 0x87, 0x4a, 0x9f, ++ 0x33, 0xd1, 0x7c, 0xdc, 0x99, 0xfb, 0x65, 0xca, 0xd3, 0xfd, 0x5f, 0xd3, ++ 0xa5, 0x2b, 0xdb, 0xf1, 0xd0, 0xd7, 0xc9, 0x63, 0xa8, 0xfc, 0x8d, 0x27, ++ 0x6f, 0xcb, 0xd7, 0x85, 0xc8, 0x65, 0x88, 0xfc, 0xa9, 0xf4, 0x72, 0xac, ++ 0x8b, 0x24, 0x39, 0x53, 0xe9, 0x58, 0xab, 0x30, 0x8a, 0x5b, 0x6b, 0xbb, ++ 0x23, 0xac, 0x6e, 0xe6, 0xa7, 0x9f, 0x19, 0xfe, 0x21, 0xfd, 0xf0, 0x9e, ++ 0x82, 0xf2, 0x31, 0xed, 0x12, 0xdb, 0x29, 0x7d, 0x13, 0x39, 0x1c, 0xa0, ++ 0x7b, 0x8d, 0x50, 0xfa, 0x00, 0x6f, 0xd8, 0x51, 0xaf, 0x3f, 0x95, 0x1d, ++ 0x6c, 0x87, 0x54, 0xba, 0x8d, 0xa7, 0x7f, 0x54, 0xfd, 0xf5, 0x21, 0xf3, ++ 0x9e, 0xb4, 0x48, 0x74, 0x3f, 0xc0, 0xe5, 0xf3, 0x97, 0x06, 0x37, 0xde, ++ 0x2f, 0xaa, 0xf7, 0x03, 0xea, 0x3d, 0xc0, 0x61, 0xa1, 0xf7, 0x42, 0xcb, ++ 0x0f, 0xc1, 0xef, 0xc0, 0x7b, 0x97, 0x2d, 0xe9, 0x7d, 0x13, 0xd1, 0x5f, ++ 0xeb, 0xd7, 0xab, 0xf3, 0xf0, 0xfb, 0xc7, 0x0f, 0xd7, 0xf7, 0x4e, 0x5d, ++ 0x0d, 0xe3, 0x3f, 0x9c, 0xc7, 0xcb, 0x7e, 0xf4, 0xd3, 0x02, 0x60, 0x7b, ++ 0x18, 0xcf, 0xc3, 0x7d, 0x38, 0xc9, 0xe0, 0x42, 0xbc, 0x7d, 0x28, 0xcd, ++ 0x9c, 0x8f, 0x76, 0xfc, 0x43, 0xe9, 0xa1, 0xbb, 0x38, 0x1c, 0xaf, 0x57, ++ 0x10, 0x5e, 0x1a, 0x3f, 0xdf, 0x02, 0x70, 0xbf, 0x4e, 0xcd, 0xdb, 0x3d, ++ 0x2a, 0xf4, 0xb0, 0x9b, 0xef, 0x63, 0xe9, 0xec, 0x7c, 0xea, 0x27, 0xb1, ++ 0x37, 0x11, 0x1f, 0x8a, 0xc4, 0x4a, 0x68, 0x1d, 0x49, 0x8a, 0x29, 0x82, ++ 0xfd, 0x7c, 0xf8, 0x8b, 0x19, 0x59, 0x4d, 0xcc, 0x7f, 0xfe, 0x96, 0x6c, ++ 0xee, 0xcf, 0xba, 0x55, 0xfd, 0xae, 0xe6, 0xb1, 0xff, 0x41, 0xa2, 0x3c, ++ 0xf6, 0x72, 0x30, 0x01, 0x16, 0xcc, 0xb7, 0xcf, 0x7f, 0xb6, 0x68, 0x3a, ++ 0xd4, 0x9f, 0xfd, 0xc7, 0x14, 0x1b, 0xdd, 0xff, 0xad, 0x09, 0x5e, 0x1f, ++ 0xed, 0x68, 0x32, 0xe5, 0x07, 0xb7, 0xd1, 0x3c, 0xdf, 0xff, 0x6a, 0x48, ++ 0xb7, 0x22, 0xc3, 0xbf, 0xaf, 0x11, 0xfb, 0x97, 0x7f, 0x8d, 0xd7, 0x97, ++ 0xcf, 0xa0, 0x78, 0xa2, 0x52, 0xd0, 0xd0, 0x1e, 0x33, 0x93, 0xc7, 0xb1, ++ 0xee, 0x94, 0x28, 0xb4, 0x47, 0xaa, 0x7d, 0x1a, 0x3e, 0x75, 0xd8, 0x1c, ++ 0x98, 0xbf, 0xbc, 0x04, 0xf6, 0x8b, 0xe9, 0x03, 0xe0, 0x99, 0x4f, 0x26, ++ 0x05, 0xda, 0xb7, 0xd7, 0xf7, 0xfd, 0x3a, 0x0d, 0xe7, 0xa9, 0xd4, 0xbb, ++ 0x32, 0xad, 0x18, 0x4f, 0x36, 0x3f, 0x9f, 0x84, 0x7e, 0x40, 0xe5, 0xbe, ++ 0xc7, 0xd3, 0xc8, 0x2f, 0xdd, 0xb7, 0x39, 0x0d, 0xe3, 0x8b, 0xca, 0x96, ++ 0x5f, 0xa7, 0xd9, 0x09, 0x0e, 0x77, 0x50, 0x7c, 0xa3, 0xe5, 0xe7, 0xbe, ++ 0x72, 0xf0, 0xce, 0x3d, 0x5b, 0x02, 0xfc, 0xe0, 0xea, 0x5c, 0x99, 0xf6, ++ 0x5f, 0x6a, 0x7c, 0xbd, 0x00, 0xfd, 0xd3, 0x45, 0x77, 0x7c, 0xf6, 0x18, ++ 0xe6, 0xc3, 0x67, 0xfc, 0xa3, 0x44, 0x79, 0xb1, 0xfb, 0x59, 0xef, 0x63, ++ 0x68, 0x37, 0xcb, 0xd2, 0xb9, 0x1c, 0xb1, 0xed, 0x46, 0xd2, 0xeb, 0x30, ++ 0x1f, 0xdd, 0x3b, 0xb6, 0xce, 0xfc, 0xf1, 0x5e, 0xd4, 0xe7, 0xa7, 0xd3, ++ 0x3f, 0xd6, 0x95, 0x43, 0xbf, 0xeb, 0xd9, 0x5a, 0xc2, 0x4f, 0x19, 0x73, ++ 0x3f, 0x11, 0x8f, 0xf9, 0xb0, 0x4d, 0x12, 0xe5, 0xc3, 0xfc, 0xfd, 0xa7, ++ 0xd2, 0x3d, 0xe6, 0x8a, 0x0d, 0x92, 0x3e, 0x21, 0x16, 0xed, 0x61, 0xb4, ++ 0x4d, 0x56, 0x70, 0x5c, 0x34, 0xed, 0xe3, 0x81, 0x4d, 0xb6, 0x1e, 0xac, ++ 0x2f, 0x7b, 0x98, 0xd7, 0x2f, 0x32, 0xb8, 0xdb, 0xfb, 0x70, 0x9e, 0x67, ++ 0xf5, 0xd6, 0x56, 0x05, 0x27, 0x2a, 0x99, 0x5e, 0x12, 0x70, 0x2f, 0x7c, ++ 0x3d, 0x9b, 0xc7, 0x5d, 0xcb, 0x9f, 0x90, 0xc8, 0x1f, 0x57, 0xd7, 0x99, ++ 0xf1, 0x4c, 0x5c, 0x73, 0xe0, 0x39, 0xaf, 0x0b, 0xfa, 0xb3, 0x1b, 0xff, ++ 0x46, 0xfa, 0xed, 0x27, 0x82, 0x2e, 0x3f, 0x7a, 0xf8, 0xfd, 0x37, 0x13, ++ 0x14, 0xbc, 0x4f, 0x72, 0xdc, 0x44, 0x3d, 0xf2, 0xde, 0xd3, 0x17, 0x52, ++ 0x51, 0x7f, 0xe5, 0xc7, 0x5c, 0xca, 0x40, 0x3e, 0x9f, 0xa1, 0x77, 0xec, ++ 0xac, 0xc2, 0x73, 0xb7, 0x18, 0x28, 0x7f, 0x98, 0x93, 0x99, 0x28, 0xc7, ++ 0x43, 0xff, 0xac, 0x9f, 0xcf, 0x7b, 0x0a, 0xcb, 0xe5, 0x0f, 0xaf, 0xd8, ++ 0x59, 0x85, 0x79, 0xd0, 0x1d, 0x46, 0x8a, 0xa3, 0xd4, 0xfd, 0xad, 0x91, ++ 0x14, 0x0d, 0xc6, 0x9b, 0x6f, 0x34, 0xff, 0xec, 0x01, 0xc4, 0xdb, 0xc5, ++ 0xa7, 0x8d, 0xe4, 0x47, 0xaf, 0x69, 0xbe, 0x2d, 0x9e, 0x8d, 0x21, 0xa7, ++ 0x6a, 0xb9, 0x1f, 0xe8, 0xaf, 0xa4, 0x31, 0xf6, 0x52, 0xa3, 0x91, 0xca, ++ 0x97, 0x1b, 0x2d, 0x4c, 0x81, 0x23, 0x1e, 0x6c, 0x4c, 0x20, 0xf8, 0x5f, ++ 0x1b, 0x15, 0x2a, 0xd9, 0x12, 0xce, 0x5f, 0x6b, 0x44, 0xbc, 0x3a, 0xde, ++ 0x7c, 0xd9, 0x10, 0xef, 0x2b, 0xa0, 0xaf, 0x72, 0x36, 0xc1, 0x7c, 0xe0, ++ 0x6f, 0xda, 0x4c, 0xf6, 0xc9, 0x39, 0x80, 0xaf, 0x19, 0xb7, 0x3b, 0x5b, ++ 0x36, 0x8b, 0x73, 0xcd, 0x80, 0xf1, 0x36, 0x57, 0xf2, 0x02, 0xc4, 0x43, ++ 0xce, 0xe6, 0xd5, 0x3d, 0xe8, 0x8a, 0xea, 0x73, 0x78, 0x7c, 0xf4, 0x76, ++ 0xdf, 0xa6, 0x24, 0xf2, 0xa3, 0x1f, 0x3e, 0xb7, 0xbb, 0x0a, 0xda, 0x17, ++ 0xe7, 0x94, 0xa4, 0xe0, 0x78, 0xe3, 0xae, 0x6b, 0x14, 0xe7, 0xbf, 0xd1, ++ 0xf5, 0x78, 0x19, 0xe5, 0xf5, 0x5b, 0x0c, 0xfc, 0x7c, 0xe2, 0xdc, 0x17, ++ 0x9f, 0x4e, 0x8b, 0xdf, 0x89, 0x79, 0xd7, 0xb7, 0x74, 0x14, 0x7f, 0xd7, ++ 0xef, 0x3a, 0xb7, 0x7b, 0x33, 0x94, 0x2b, 0x9f, 0x58, 0xad, 0x0f, 0xe4, ++ 0xf7, 0x6f, 0x7a, 0xde, 0x64, 0xb1, 0x9f, 0x5b, 0xc9, 0xd5, 0x78, 0x78, ++ 0xf8, 0xf6, 0x72, 0xf5, 0xeb, 0x24, 0x92, 0x9f, 0x16, 0x90, 0xab, 0x8c, ++ 0xbf, 0x5e, 0xae, 0xea, 0x1f, 0x5e, 0x4f, 0xf8, 0x7b, 0x28, 0xa7, 0x64, ++ 0x51, 0x0e, 0xec, 0xff, 0xa2, 0xce, 0x95, 0x84, 0xf2, 0x74, 0x71, 0xe6, ++ 0xf7, 0x88, 0xcf, 0x5d, 0xc7, 0x25, 0xc2, 0xbf, 0xaa, 0xc7, 0xd5, 0xf1, ++ 0x45, 0xe2, 0xbc, 0x35, 0x1a, 0xcf, 0x13, 0xe4, 0x0f, 0x0a, 0x3d, 0xfe, ++ 0x25, 0x44, 0x7e, 0x88, 0xdf, 0xd7, 0xbb, 0x3e, 0x4d, 0x43, 0x7f, 0xf8, ++ 0xcb, 0xce, 0xa5, 0x5f, 0x7b, 0xee, 0x23, 0x8d, 0x78, 0x83, 0x8e, 0x79, ++ 0x2d, 0x23, 0x95, 0xa1, 0xed, 0x79, 0x7a, 0x47, 0x8a, 0x15, 0xce, 0x97, ++ 0xa7, 0xe1, 0x7e, 0xf0, 0x28, 0xff, 0x55, 0xdc, 0xcf, 0xa9, 0xf7, 0xed, ++ 0xf8, 0x87, 0x79, 0xe1, 0x5a, 0x61, 0x3f, 0x9d, 0xb0, 0xb1, 0xa8, 0x18, ++ 0xb4, 0x7f, 0x92, 0x37, 0x2c, 0x13, 0xef, 0x39, 0x7e, 0x78, 0x49, 0x8b, ++ 0xf1, 0x17, 0xc4, 0x75, 0x1f, 0x05, 0xfb, 0x97, 0xec, 0xa3, 0x00, 0x3b, ++ 0x3e, 0xde, 0x7e, 0x6f, 0x55, 0xd6, 0xe1, 0x3c, 0x5a, 0xbf, 0xde, 0x9d, ++ 0x7d, 0x46, 0xc3, 0xbc, 0x01, 0x76, 0xfb, 0xce, 0x81, 0x30, 0xe6, 0x0d, ++ 0x58, 0x77, 0x24, 0xee, 0x30, 0x22, 0x4f, 0x43, 0x1c, 0xda, 0x35, 0x89, ++ 0xf4, 0x02, 0xd2, 0x0d, 0xef, 0x65, 0x7c, 0x5d, 0x33, 0x5b, 0x10, 0xbe, ++ 0xa4, 0xe7, 0x74, 0xf4, 0x1d, 0x81, 0xf8, 0x8a, 0xe7, 0x55, 0x98, 0x9c, ++ 0xe7, 0x3f, 0xe7, 0xa5, 0xae, 0x2b, 0x99, 0xa8, 0x67, 0x43, 0xcf, 0x5b, ++ 0x77, 0xf4, 0x0a, 0xf1, 0x47, 0x6d, 0xe7, 0xe3, 0xd7, 0x24, 0x3a, 0xff, ++ 0xc2, 0x4b, 0xda, 0xcc, 0x5b, 0x9f, 0xff, 0xf5, 0x7d, 0x57, 0x32, 0x91, ++ 0x7e, 0x97, 0x74, 0x03, 0x79, 0x18, 0x47, 0xf9, 0xf4, 0x03, 0x99, 0x48, ++ 0x87, 0xba, 0x63, 0x5c, 0x9f, 0x7f, 0x5b, 0x3c, 0xa8, 0xf5, 0x55, 0x9b, ++ 0xf4, 0x3c, 0xbf, 0x27, 0x59, 0x28, 0x1e, 0x2c, 0x90, 0xaf, 0x52, 0x1c, ++ 0xef, 0x3b, 0xc5, 0xe3, 0xf8, 0xba, 0xae, 0x3d, 0xa4, 0x4f, 0x87, 0xbb, ++ 0x79, 0x3e, 0xa5, 0x5e, 0xd3, 0x5b, 0x18, 0x8f, 0xf9, 0x87, 0x86, 0x73, ++ 0x3d, 0xa8, 0xcf, 0x86, 0x13, 0x78, 0x7c, 0x05, 0xf3, 0xdb, 0x11, 0x6f, ++ 0x73, 0x53, 0x84, 0x1d, 0xd4, 0x0e, 0x25, 0x2d, 0x06, 0xbd, 0xf6, 0xca, ++ 0x08, 0x3f, 0xf0, 0xb8, 0xee, 0x22, 0xca, 0xaf, 0x1e, 0xe7, 0xf1, 0xd4, ++ 0xd2, 0x7b, 0xa4, 0xcc, 0x70, 0x86, 0x7e, 0xc5, 0x65, 0x94, 0x67, 0xa8, ++ 0x2f, 0x5b, 0x97, 0xbc, 0x11, 0xf9, 0xfc, 0xa2, 0x7b, 0x22, 0x66, 0x82, ++ 0xd8, 0xdb, 0x99, 0xff, 0x53, 0x47, 0xf9, 0xb7, 0xd7, 0xc2, 0x2d, 0x32, ++ 0xf9, 0xad, 0x50, 0x1b, 0x40, 0xbf, 0x91, 0x73, 0xb8, 0x65, 0xfe, 0x70, ++ 0x86, 0xa9, 0x71, 0x7a, 0x38, 0xb3, 0x07, 0xf4, 0xab, 0xd7, 0x2b, 0x3f, ++ 0xa1, 0xf8, 0xf8, 0x34, 0xbf, 0x27, 0xab, 0xbf, 0x9d, 0xcb, 0x13, 0x3b, ++ 0xca, 0xe5, 0xc9, 0xb9, 0xe1, 0x75, 0x7d, 0x42, 0xc0, 0x7c, 0xbb, 0x51, ++ 0x9e, 0x68, 0xdf, 0xdc, 0x7f, 0x5c, 0xf4, 0xda, 0xff, 0x90, 0x5c, 0x76, ++ 0xdb, 0xec, 0xdd, 0x28, 0x97, 0xe1, 0xa8, 0x0b, 0x71, 0xbe, 0x84, 0x28, ++ 0xb7, 0x24, 0x89, 0x7e, 0x79, 0xfe, 0x7b, 0x40, 0x73, 0xb7, 0x88, 0xc7, ++ 0x8b, 0x64, 0x6a, 0xaf, 0xef, 0x94, 0xd9, 0x24, 0x1c, 0x93, 0x10, 0x41, ++ 0xf7, 0xf5, 0x45, 0x6c, 0xab, 0x16, 0xfd, 0xdd, 0x45, 0xcc, 0x33, 0x97, ++ 0xbf, 0x93, 0x19, 0xf8, 0xcd, 0x77, 0xa1, 0xbd, 0xf8, 0x35, 0x39, 0x1b, ++ 0xdf, 0x63, 0x81, 0xff, 0x4c, 0xf7, 0xc7, 0x85, 0x61, 0x8e, 0xd4, 0x35, ++ 0xe8, 0x1f, 0x69, 0x24, 0x81, 0x57, 0x4f, 0xce, 0xe2, 0x40, 0x7b, 0x26, ++ 0xde, 0x79, 0xcc, 0x95, 0x25, 0xb2, 0x63, 0x43, 0x93, 0xc2, 0xc9, 0x4f, ++ 0x59, 0xb8, 0xc4, 0x59, 0x8a, 0xfb, 0x1d, 0xd1, 0x0f, 0x5a, 0xde, 0x0f, ++ 0xe6, 0x21, 0x3f, 0x8b, 0xb9, 0x87, 0x32, 0xf1, 0x3e, 0x93, 0x79, 0x87, ++ 0x32, 0xf1, 0x9e, 0x53, 0xed, 0x77, 0xef, 0x6b, 0xe1, 0x0d, 0x64, 0x17, ++ 0x99, 0x27, 0xe7, 0xde, 0x80, 0x75, 0xc2, 0x72, 0xb9, 0xdd, 0xfc, 0x1c, ++ 0xef, 0x9f, 0x41, 0x9f, 0xd4, 0x8b, 0xfb, 0xcf, 0x02, 0xf9, 0xc6, 0x33, ++ 0x18, 0x47, 0xad, 0x39, 0xce, 0xef, 0x09, 0xfb, 0x35, 0xc9, 0x1f, 0xe0, ++ 0x7b, 0x2d, 0x17, 0xe0, 0x19, 0xe9, 0x7a, 0x05, 0xe8, 0x6a, 0x47, 0xfb, ++ 0xe3, 0x60, 0x76, 0x3b, 0xca, 0xcf, 0xac, 0x89, 0x6e, 0x94, 0x9f, 0xfa, ++ 0x83, 0x12, 0xc3, 0x77, 0x6b, 0x75, 0x5d, 0x86, 0x16, 0xcc, 0xeb, 0xd4, ++ 0xe9, 0x06, 0xe2, 0x90, 0x9f, 0x37, 0x77, 0xfe, 0x41, 0x8f, 0xfc, 0x5c, ++ 0xdf, 0xf1, 0xbe, 0x5e, 0x99, 0x85, 0xe3, 0x79, 0x1e, 0x08, 0xfc, 0x75, ++ 0x0d, 0xe2, 0xb7, 0x5e, 0xd8, 0x2f, 0x67, 0xe7, 0x6d, 0x1f, 0x60, 0xde, ++ 0xcd, 0x79, 0x8a, 0x5b, 0x51, 0xa7, 0xf6, 0x7d, 0x8a, 0xeb, 0x6b, 0xda, ++ 0x0f, 0x51, 0xfc, 0x5e, 0xcb, 0xbc, 0x14, 0xbf, 0xd7, 0xb6, 0x05, 0xf3, ++ 0xcb, 0x70, 0x02, 0xcf, 0xb3, 0x87, 0xca, 0x47, 0x58, 0xae, 0x42, 0xfa, ++ 0x52, 0x85, 0x17, 0xee, 0xe0, 0x72, 0x71, 0xaf, 0xcc, 0x1a, 0x28, 0xde, ++ 0x17, 0x79, 0xd3, 0x85, 0x09, 0xf1, 0xe4, 0x8f, 0xf8, 0xc7, 0x09, 0x3f, ++ 0x51, 0xbe, 0xf2, 0x18, 0xfa, 0x2f, 0x83, 0xd3, 0x25, 0xab, 0x04, 0x53, ++ 0x0d, 0x86, 0xb9, 0x36, 0xa0, 0x5f, 0xe4, 0x4a, 0xe3, 0xfe, 0xcc, 0xe0, ++ 0xef, 0x5e, 0xce, 0xa9, 0x20, 0xbd, 0xe2, 0xce, 0xf9, 0x29, 0xbe, 0x8b, ++ 0x11, 0xfe, 0xee, 0xc2, 0x4d, 0xdb, 0xb4, 0x72, 0xc0, 0x7e, 0x16, 0x76, ++ 0xf3, 0x3c, 0xe1, 0x60, 0x18, 0xab, 0x3c, 0x42, 0xf4, 0x76, 0x4c, 0x41, ++ 0x3a, 0x44, 0x66, 0x95, 0x98, 0x73, 0x73, 0x49, 0xae, 0x32, 0xe9, 0x9d, ++ 0x8f, 0x86, 0xe7, 0x35, 0x43, 0xcf, 0xf1, 0xa4, 0xc8, 0x67, 0x9e, 0xc6, ++ 0x3c, 0x4f, 0x86, 0x7f, 0xdf, 0xc5, 0x89, 0x89, 0x5c, 0x8f, 0x31, 0x37, ++ 0xf1, 0x4f, 0x8f, 0x86, 0xaf, 0xaf, 0xbe, 0x7b, 0x51, 0xc7, 0xaf, 0xc8, ++ 0x95, 0x82, 0xe2, 0xa5, 0x35, 0x12, 0xcf, 0x4f, 0x8d, 0xa7, 0x57, 0xf0, ++ 0x1e, 0xa5, 0x5c, 0xdc, 0xa3, 0x94, 0x8b, 0x7b, 0x94, 0x72, 0x71, 0x8f, ++ 0x52, 0x2e, 0xee, 0x51, 0xca, 0xc5, 0x3d, 0x4a, 0xb9, 0xb8, 0x47, 0x29, ++ 0x17, 0xf7, 0x28, 0xe5, 0xe2, 0x1e, 0xa5, 0x5c, 0xdc, 0xa3, 0x94, 0x8b, ++ 0x7b, 0x14, 0xac, 0x3f, 0x8d, 0x5b, 0xa5, 0xf7, 0x70, 0xcf, 0xef, 0x44, ++ 0xfb, 0xd9, 0x83, 0x32, 0x36, 0xd9, 0x0f, 0xf7, 0xc7, 0x84, 0xc0, 0x93, ++ 0x83, 0xfb, 0xf7, 0xc7, 0x48, 0xc1, 0xf0, 0x64, 0x89, 0xfa, 0xe7, 0xe4, ++ 0x3e, 0xbf, 0xd3, 0x95, 0x81, 0x79, 0x4c, 0x8b, 0x90, 0x6f, 0x25, 0x02, ++ 0xfd, 0xaf, 0x8b, 0x26, 0x9e, 0x5f, 0xea, 0x8a, 0x70, 0xfc, 0x1d, 0xe2, ++ 0xb9, 0x7c, 0x61, 0xd3, 0x3e, 0xfe, 0x1e, 0xd1, 0x4e, 0xef, 0x59, 0xf2, ++ 0x63, 0x96, 0x96, 0xa2, 0x7c, 0x0d, 0xc7, 0x1a, 0x18, 0xea, 0xa1, 0x86, ++ 0x5c, 0xc7, 0xbc, 0x5c, 0xa0, 0xfb, 0xa9, 0x53, 0x0b, 0x52, 0xb7, 0x91, ++ 0x7e, 0x34, 0x59, 0xf1, 0x9e, 0xbb, 0xff, 0xbe, 0x3b, 0xa2, 0x28, 0x2f, ++ 0xf7, 0x96, 0xcc, 0x64, 0x58, 0x72, 0x5e, 0x7a, 0xf6, 0x86, 0x1c, 0x80, ++ 0xe7, 0x99, 0x25, 0xe2, 0x5b, 0xd0, 0x13, 0xdf, 0x29, 0x51, 0xe3, 0x49, ++ 0x98, 0x67, 0x41, 0x37, 0xbf, 0xcf, 0x28, 0x90, 0x6b, 0xcb, 0x71, 0xfe, ++ 0x35, 0x93, 0x4c, 0xd9, 0xa8, 0x77, 0x87, 0xb2, 0x1c, 0xc5, 0xb9, 0x01, ++ 0xfc, 0x58, 0x38, 0x79, 0x55, 0x2a, 0xfa, 0x41, 0x3d, 0x3a, 0xe5, 0x03, ++ 0xcc, 0xa7, 0xba, 0xde, 0xd5, 0x31, 0x8c, 0xa3, 0xd4, 0xfc, 0x9b, 0xda, ++ 0xaf, 0x27, 0x6b, 0xde, 0x52, 0x1c, 0xb7, 0x30, 0x3d, 0x65, 0x43, 0x16, ++ 0xea, 0x1b, 0x10, 0x2e, 0xd4, 0x6f, 0x76, 0x3d, 0x6b, 0xc3, 0x7d, 0xd9, ++ 0x35, 0xe1, 0x52, 0x13, 0xe9, 0x2b, 0x45, 0x8b, 0xf2, 0xbf, 0x54, 0xf0, ++ 0xef, 0x7c, 0x85, 0xfb, 0xc3, 0x5e, 0xbd, 0xa2, 0x8d, 0xc1, 0xb8, 0x3d, ++ 0x6c, 0x5e, 0xac, 0x4b, 0xe1, 0xf7, 0x55, 0xe5, 0xe2, 0xbe, 0xaa, 0x5c, ++ 0xdc, 0x57, 0x21, 0x7d, 0xde, 0xc1, 0xbc, 0x19, 0x94, 0xef, 0x41, 0x3d, ++ 0x96, 0xbd, 0x50, 0x8f, 0x65, 0xe8, 0x7b, 0xae, 0x67, 0x72, 0x4a, 0x56, ++ 0xe6, 0x52, 0xbc, 0x3d, 0x94, 0x14, 0xf8, 0x1e, 0x6c, 0x11, 0xca, 0x15, ++ 0xd7, 0x33, 0x49, 0xc8, 0xcf, 0x3b, 0x05, 0xdf, 0x26, 0x08, 0x3d, 0xd3, ++ 0x93, 0x5d, 0x52, 0x4d, 0xfc, 0xce, 0x3c, 0x34, 0x4f, 0x8d, 0xc8, 0xbf, ++ 0x5d, 0xd1, 0x05, 0xdf, 0xe3, 0xa9, 0xe3, 0xfc, 0xe3, 0x19, 0x95, 0x77, ++ 0x7f, 0x87, 0xeb, 0x67, 0x16, 0xa5, 0xe7, 0xef, 0x5d, 0xa7, 0x30, 0x17, ++ 0xbe, 0xa7, 0xbd, 0xfb, 0xd5, 0x49, 0x94, 0x4f, 0xf2, 0xb9, 0x35, 0x2e, ++ 0x5d, 0x14, 0xc0, 0x20, 0xe3, 0xa8, 0xbf, 0xd8, 0xab, 0x3c, 0xbe, 0x65, ++ 0x09, 0x5c, 0x5e, 0xee, 0x3e, 0x1c, 0x4f, 0xfd, 0x9a, 0x44, 0x1e, 0xd4, ++ 0x19, 0xd3, 0x9b, 0x16, 0x83, 0x76, 0x57, 0xc8, 0x95, 0x0a, 0x1f, 0xf9, ++ 0x0b, 0x7f, 0xe7, 0xe3, 0xcc, 0x02, 0x18, 0xca, 0x63, 0x12, 0x3f, 0x9f, ++ 0xf3, 0xee, 0xde, 0xb4, 0x68, 0x80, 0x7d, 0x92, 0x49, 0x83, 0xf9, 0x71, ++ 0x67, 0x0b, 0x6f, 0xef, 0x13, 0x72, 0xe7, 0x9c, 0x2e, 0xe6, 0x13, 0xe7, ++ 0x61, 0x46, 0x4f, 0x12, 0xd2, 0x63, 0xf0, 0xf8, 0xab, 0x49, 0x0f, 0x00, ++ 0xbc, 0xc5, 0xec, 0xad, 0xe0, 0xfa, 0xde, 0x9b, 0x46, 0x7a, 0x9a, 0x79, ++ 0xd3, 0xf0, 0xbd, 0xd0, 0x15, 0xc9, 0x73, 0x16, 0xdf, 0xdb, 0xae, 0x3a, ++ 0x92, 0xb5, 0x0c, 0xdf, 0xd7, 0x5e, 0xd1, 0x79, 0x76, 0x23, 0x5c, 0x73, ++ 0x24, 0x87, 0xc3, 0xd2, 0xa1, 0xb3, 0x96, 0xc0, 0xf6, 0x89, 0x9e, 0x24, ++ 0x7c, 0x8f, 0xbb, 0xea, 0x48, 0xf6, 0x32, 0x7c, 0x9f, 0x7b, 0x65, 0xe2, ++ 0xa1, 0xdd, 0xd1, 0xd6, 0x00, 0x58, 0xf7, 0xca, 0x59, 0x6c, 0xd7, 0x3f, ++ 0x9a, 0xb3, 0x2c, 0x1f, 0xe0, 0x62, 0x83, 0xfb, 0x54, 0x23, 0xf2, 0xcd, ++ 0xbf, 0x72, 0xfe, 0x32, 0x1d, 0xec, 0xb8, 0x80, 0xf8, 0xa9, 0xe9, 0xe2, ++ 0xfe, 0xfa, 0xfc, 0x83, 0x1d, 0x57, 0x5f, 0x41, 0x7b, 0xdc, 0x11, 0x41, ++ 0xf7, 0xf5, 0x07, 0x72, 0x93, 0x89, 0xde, 0x4d, 0x5d, 0xfb, 0x9f, 0x40, ++ 0x7e, 0xf3, 0x1d, 0xd2, 0x91, 0x1c, 0x6c, 0x69, 0xfb, 0xc3, 0xee, 0x5f, ++ 0x51, 0x3f, 0x03, 0xa5, 0x51, 0x8a, 0x0d, 0x9e, 0x1c, 0x4c, 0xb9, 0x34, ++ 0xe4, 0xfd, 0xc7, 0x7d, 0xb8, 0x6e, 0x71, 0xb8, 0xe7, 0x0b, 0x84, 0xd7, ++ 0xe7, 0xfd, 0x80, 0xf6, 0x51, 0x3c, 0x81, 0xcb, 0xf3, 0xc6, 0xbc, 0xf9, ++ 0xcb, 0x50, 0x3e, 0x7d, 0x1d, 0x07, 0x7f, 0x89, 0xf2, 0x57, 0x1c, 0x05, ++ 0x8e, 0x2c, 0xee, 0xe7, 0x65, 0x13, 0xd1, 0xa7, 0xfa, 0xf0, 0xcc, 0x7c, ++ 0xcc, 0x03, 0xf8, 0x22, 0x7a, 0xcb, 0x70, 0xfe, 0xba, 0xdf, 0x1a, 0xac, ++ 0xc8, 0xa7, 0xd5, 0x87, 0xe3, 0xe7, 0x63, 0x5e, 0xa0, 0x23, 0x97, 0xe7, ++ 0xa7, 0xab, 0x6e, 0xdf, 0x9a, 0x84, 0xf6, 0x55, 0x73, 0xf4, 0xa5, 0x7d, ++ 0xbf, 0xc2, 0x3c, 0xe5, 0x6f, 0x4d, 0x74, 0x3f, 0x53, 0x1f, 0xc3, 0xfd, ++ 0xbb, 0x6a, 0xb9, 0x39, 0x6f, 0x35, 0xd1, 0x6f, 0xcf, 0x3e, 0x7c, 0x37, ++ 0xe2, 0x7b, 0xc9, 0x44, 0xf7, 0xa4, 0x55, 0x30, 0x07, 0xae, 0x57, 0xb5, ++ 0x6f, 0x06, 0xe5, 0xd5, 0x8f, 0xfd, 0xf9, 0xe3, 0x32, 0xa4, 0x43, 0x81, ++ 0xbc, 0x6b, 0x1f, 0xd6, 0x7f, 0xb1, 0xd7, 0xa4, 0x41, 0x3c, 0xf4, 0xe9, ++ 0xed, 0x51, 0xdf, 0x43, 0x39, 0xec, 0xd3, 0x51, 0x9c, 0x59, 0x25, 0xe0, ++ 0xaa, 0xfe, 0x09, 0x7c, 0x3f, 0xe1, 0x03, 0x85, 0x44, 0xbf, 0xd8, 0xad, ++ 0x49, 0x68, 0x5f, 0xab, 0x27, 0xfc, 0xc3, 0x5d, 0xb8, 0xef, 0x62, 0x79, ++ 0xeb, 0x6e, 0x8c, 0x73, 0xd8, 0x7e, 0x03, 0xdd, 0x15, 0x5c, 0x7a, 0x09, ++ 0xf0, 0x06, 0xe3, 0x2e, 0xb5, 0xea, 0xe8, 0x95, 0xaa, 0xef, 0xa5, 0x08, ++ 0x2d, 0xf2, 0xcb, 0x15, 0x69, 0x6b, 0xd9, 0x4e, 0x9c, 0xbf, 0x95, 0xf7, ++ 0xbb, 0x62, 0xda, 0x4a, 0xf8, 0x74, 0xb5, 0xde, 0xc6, 0x70, 0x3d, 0xe8, ++ 0xc7, 0x50, 0x5f, 0x5d, 0x91, 0xb6, 0x05, 0xd5, 0x5f, 0x6a, 0xdd, 0x9f, ++ 0x89, 0x71, 0xe8, 0xe5, 0xdf, 0x16, 0x53, 0x3c, 0xaa, 0xf2, 0xf9, 0x48, ++ 0x9c, 0xb1, 0xd7, 0x10, 0x64, 0x0f, 0x49, 0x13, 0xc4, 0x89, 0xf7, 0x12, ++ 0x64, 0x66, 0x5d, 0xcc, 0x0c, 0x76, 0xb6, 0x4a, 0x80, 0x97, 0x8f, 0x3c, ++ 0xe7, 0xdb, 0xc9, 0xfc, 0xe3, 0x2f, 0xb7, 0xe9, 0xbc, 0x7a, 0xc0, 0x51, ++ 0x95, 0x81, 0x6d, 0xc0, 0xf7, 0xc1, 0xaa, 0x3c, 0x54, 0x27, 0xfe, 0xb0, ++ 0x08, 0xcf, 0x57, 0xad, 0x69, 0x4e, 0x43, 0x7f, 0xa5, 0x2a, 0x7b, 0xa0, ++ 0x0c, 0xe5, 0xe2, 0x92, 0x89, 0x19, 0x13, 0xa0, 0xdf, 0xdb, 0xc2, 0x5e, ++ 0x55, 0xb7, 0xaf, 0x5f, 0x8c, 0x7e, 0xef, 0x78, 0xfb, 0xf9, 0x8b, 0xb0, ++ 0x3f, 0x5f, 0x0a, 0x39, 0xfc, 0xb2, 0xd3, 0xe4, 0x0e, 0xbc, 0x1f, 0x0c, ++ 0x2d, 0xff, 0xd8, 0xc8, 0x94, 0x77, 0x02, 0xde, 0x0d, 0xdf, 0xdf, 0x60, ++ 0x20, 0xdf, 0x5d, 0x9d, 0xef, 0x6d, 0xbd, 0xa7, 0x16, 0xe3, 0xb3, 0xba, ++ 0x18, 0xae, 0x3f, 0xce, 0x42, 0xff, 0x36, 0xd0, 0x63, 0x37, 0x84, 0xde, ++ 0x5b, 0xbe, 0x2e, 0xb8, 0xff, 0xb5, 0xdc, 0x18, 0xfe, 0x2e, 0x55, 0x3f, ++ 0x90, 0x86, 0x76, 0x4f, 0x9d, 0xdf, 0x97, 0xab, 0xea, 0xb5, 0x81, 0x34, ++ 0xd4, 0x57, 0xa1, 0xe3, 0x8a, 0x65, 0xa1, 0x6f, 0x5e, 0x96, 0x48, 0xdf, ++ 0x54, 0xb7, 0x4b, 0xe7, 0x64, 0xc0, 0x53, 0xb5, 0xd1, 0xe5, 0xc6, 0xf7, ++ 0x3b, 0xd5, 0x18, 0x4c, 0xf2, 0x73, 0x6a, 0x6f, 0x4a, 0x7c, 0x5c, 0x42, ++ 0x9e, 0xc0, 0x3b, 0x8c, 0x7d, 0x3c, 0x2f, 0x99, 0xce, 0x5d, 0xdd, 0x66, ++ 0xb2, 0x9b, 0x60, 0x5c, 0x4d, 0xd8, 0x40, 0x24, 0xfa, 0x43, 0xb5, 0x11, ++ 0x03, 0x91, 0xe8, 0xe7, 0xf8, 0x8e, 0xca, 0xac, 0x45, 0x90, 0x2b, 0x36, ++ 0x4e, 0xd0, 0x67, 0xba, 0x20, 0x59, 0x40, 0xde, 0xb1, 0xca, 0xa3, 0xb3, ++ 0x9b, 0x32, 0xc7, 0xa0, 0x33, 0xfa, 0x4d, 0xf8, 0x3e, 0x07, 0xff, 0x1b, ++ 0xd6, 0xdf, 0x95, 0x37, 0x9d, 0xd6, 0xab, 0xec, 0x0c, 0xa7, 0xf5, 0x98, ++ 0x65, 0x20, 0x0f, 0xf9, 0xb4, 0x72, 0x57, 0xf0, 0x38, 0x3c, 0x97, 0x25, ++ 0x40, 0xfe, 0x7c, 0x9d, 0x7b, 0xe2, 0x02, 0xe3, 0xf1, 0x64, 0xb1, 0xef, ++ 0x41, 0xe9, 0x1c, 0xc9, 0xc9, 0xe0, 0x9f, 0x3f, 0x4a, 0x42, 0xba, 0x57, ++ 0x6b, 0xd8, 0x06, 0xbc, 0x47, 0xbc, 0x2c, 0xf1, 0xef, 0x1e, 0x00, 0xa6, ++ 0xef, 0x1e, 0x2e, 0x8b, 0xfb, 0xc8, 0xea, 0x3f, 0x99, 0xc3, 0x90, 0x5f, ++ 0x2e, 0x7f, 0x59, 0x4b, 0x72, 0xeb, 0x93, 0x06, 0x48, 0xaf, 0xbd, 0x7b, ++ 0xa4, 0x84, 0xf4, 0x81, 0x4f, 0x37, 0x40, 0x7a, 0xed, 0x44, 0xde, 0xbd, ++ 0xa4, 0xc7, 0x7c, 0xd1, 0x03, 0x65, 0xa8, 0xa7, 0xde, 0x3d, 0x52, 0xc1, ++ 0xdb, 0x27, 0x0d, 0x94, 0x29, 0xd0, 0xde, 0x86, 0x30, 0xb6, 0x4f, 0x65, ++ 0x64, 0xef, 0xff, 0x2b, 0xcf, 0x49, 0xfa, 0xa3, 0x58, 0xe6, 0xef, 0x1b, ++ 0xd8, 0x1e, 0x9d, 0x85, 0xe7, 0x81, 0x36, 0xf5, 0x37, 0x52, 0x5c, 0xa1, ++ 0x53, 0x02, 0xe3, 0xee, 0x3f, 0xe6, 0xa9, 0xf7, 0x36, 0x7a, 0xff, 0xb9, ++ 0x65, 0xbf, 0xdc, 0xf8, 0x98, 0x72, 0xb0, 0x1d, 0xe5, 0xb0, 0xd2, 0x4c, ++ 0xf9, 0x1c, 0xf0, 0x9f, 0xda, 0x5e, 0x41, 0x3f, 0x6f, 0x69, 0x9c, 0x15, ++ 0xf3, 0xe2, 0x95, 0x38, 0x8e, 0xf3, 0x81, 0x3e, 0xf0, 0xfe, 0x2f, 0x36, ++ 0xe6, 0x7a, 0x05, 0xd2, 0x67, 0x59, 0x94, 0xa3, 0x20, 0x2f, 0x17, 0xef, ++ 0x19, 0x07, 0x28, 0x7e, 0x00, 0xae, 0x26, 0x3f, 0xbd, 0xee, 0x77, 0x06, ++ 0x8a, 0x23, 0x07, 0x75, 0x43, 0xfb, 0x50, 0x4f, 0x65, 0x46, 0x39, 0x16, ++ 0xe6, 0x01, 0x7f, 0xd5, 0xea, 0x7b, 0x37, 0xa2, 0x4b, 0x7f, 0x55, 0x37, ++ 0xd0, 0x83, 0xf7, 0x7e, 0x8b, 0x64, 0xae, 0x8f, 0xd8, 0x7e, 0xce, 0x57, ++ 0xbe, 0x8c, 0x3d, 0xfc, 0x3b, 0x09, 0x71, 0x7f, 0xb8, 0x54, 0xe0, 0x1f, ++ 0xec, 0x16, 0x6b, 0x46, 0xbe, 0x90, 0x38, 0x7d, 0xdf, 0xe8, 0x3c, 0xfc, ++ 0x0e, 0xea, 0x15, 0x5f, 0x6f, 0x0a, 0xe9, 0xe3, 0x50, 0xb9, 0xb9, 0xd4, ++ 0xf9, 0x54, 0x24, 0xea, 0x87, 0x33, 0x60, 0xc7, 0x5d, 0x01, 0x71, 0xfe, ++ 0x99, 0x15, 0xfb, 0xe9, 0x9e, 0x7e, 0x09, 0xbe, 0xcb, 0x80, 0xf2, 0x81, ++ 0x0d, 0xc1, 0xfc, 0x30, 0x7c, 0xe3, 0xa7, 0x14, 0xef, 0xb1, 0x27, 0x02, ++ 0xea, 0x91, 0x0f, 0xb7, 0x07, 0xc3, 0xa1, 0x7c, 0x84, 0xfc, 0xe8, 0x0d, ++ 0xd2, 0x3b, 0x2e, 0x92, 0xa7, 0x67, 0x73, 0xb9, 0x1f, 0x56, 0x33, 0xbf, ++ 0xb7, 0x0e, 0xf1, 0x30, 0x02, 0xdf, 0x0d, 0xb0, 0x1c, 0x00, 0x9f, 0x08, ++ 0x81, 0x43, 0xfa, 0xb3, 0x12, 0xee, 0x27, 0x3c, 0x8b, 0xff, 0x8d, 0x78, ++ 0x9c, 0xea, 0xed, 0xa7, 0xf8, 0xfc, 0x20, 0x7f, 0x17, 0xdb, 0x04, 0xf6, ++ 0x8b, 0xe0, 0x8e, 0x70, 0xba, 0x37, 0xd6, 0x1c, 0x04, 0xfb, 0x14, 0xcb, ++ 0xed, 0x13, 0xda, 0x85, 0x9a, 0xc8, 0x5e, 0xca, 0x4b, 0xf9, 0x3a, 0x0c, ++ 0x74, 0x3f, 0xf2, 0x68, 0xd7, 0xa7, 0xf4, 0x9e, 0x11, 0xf8, 0x90, 0xf2, ++ 0x2f, 0x35, 0x5d, 0xaf, 0xc6, 0x61, 0xdc, 0x7e, 0x00, 0xe3, 0x84, 0x5c, ++ 0xb2, 0x83, 0x71, 0xf4, 0x4e, 0xa5, 0xa3, 0x2b, 0x0e, 0xe3, 0x0d, 0xb5, ++ 0xbe, 0x56, 0xe3, 0x49, 0x13, 0xef, 0xf1, 0xc9, 0x4f, 0x57, 0xeb, 0x9d, ++ 0xb2, 0x37, 0x0d, 0xf7, 0x5f, 0x23, 0xf5, 0x66, 0x62, 0xfb, 0x01, 0xb1, ++ 0xef, 0x5a, 0x0d, 0xc0, 0x32, 0xc2, 0x62, 0xdf, 0x12, 0x97, 0x77, 0xd6, ++ 0x25, 0x93, 0x3e, 0x0f, 0xa5, 0xdb, 0x0e, 0xc1, 0xaf, 0xa0, 0x17, 0x32, ++ 0xe9, 0x9d, 0xc5, 0x51, 0x9e, 0x17, 0x50, 0xf5, 0x40, 0x95, 0xd0, 0x27, ++ 0x27, 0xb0, 0x3e, 0x83, 0xcb, 0xbd, 0x45, 0xbd, 0x57, 0x92, 0xf0, 0xbd, ++ 0x5c, 0xf8, 0x98, 0xfa, 0x21, 0x3e, 0x4f, 0xe8, 0x37, 0xd6, 0x40, 0x79, ++ 0x9b, 0xed, 0x79, 0x7c, 0xdf, 0xea, 0x78, 0x9a, 0x97, 0xe7, 0x95, 0xa8, ++ 0xbd, 0xee, 0xd8, 0x95, 0xcc, 0xe9, 0x19, 0x38, 0x4e, 0x19, 0x79, 0x07, ++ 0x39, 0xa2, 0x87, 0x52, 0xfc, 0x7a, 0x05, 0xe5, 0x3f, 0x81, 0xe4, 0xff, ++ 0x51, 0x5d, 0x1c, 0x9c, 0xab, 0x7a, 0xb7, 0x64, 0x6d, 0x42, 0x3d, 0x55, ++ 0xba, 0xbe, 0x10, 0xba, 0xb3, 0x55, 0xda, 0xd5, 0x85, 0x94, 0x2f, 0x13, ++ 0xef, 0x3f, 0x43, 0xf7, 0x15, 0xca, 0x47, 0x56, 0xd8, 0x0b, 0xe9, 0x49, ++ 0x4d, 0x74, 0x41, 0x6c, 0xc0, 0x7c, 0x97, 0x21, 0x5c, 0x4f, 0xc8, 0x22, ++ 0x3d, 0x43, 0xef, 0xe8, 0x1f, 0x8c, 0x7d, 0xb2, 0x10, 0xf3, 0x13, 0x3f, ++ 0x2b, 0xdd, 0x46, 0xfc, 0x3c, 0x62, 0x6f, 0x02, 0xe5, 0x1c, 0xcf, 0xb3, ++ 0x8b, 0xeb, 0x71, 0x14, 0x9b, 0x9b, 0x9a, 0xd1, 0x7c, 0xbc, 0xaa, 0xa1, ++ 0x79, 0x63, 0xfc, 0x18, 0xfb, 0x08, 0xdd, 0x67, 0x95, 0xa3, 0xb9, 0x30, ++ 0x4e, 0x19, 0x5d, 0xaf, 0xee, 0xf7, 0xb2, 0x49, 0xdd, 0xdf, 0x7c, 0xdd, ++ 0xc4, 0x40, 0x3c, 0x2c, 0x59, 0x5f, 0x38, 0x11, 0xca, 0x55, 0xc6, 0xbf, ++ 0x16, 0x0f, 0xfc, 0xbc, 0x97, 0xbb, 0x0c, 0x5e, 0xb4, 0xab, 0x55, 0xa5, ++ 0xab, 0x37, 0x46, 0x8d, 0xc1, 0x37, 0xa3, 0xec, 0xc1, 0xae, 0x00, 0xfb, ++ 0x35, 0x1d, 0xe9, 0xeb, 0xa6, 0x7b, 0x8d, 0xf1, 0xf6, 0x1f, 0x5a, 0xd6, ++ 0x4a, 0xde, 0x7e, 0xcc, 0x13, 0x31, 0x90, 0xab, 0x56, 0x92, 0x2f, 0x90, ++ 0x97, 0x00, 0xbb, 0x30, 0x27, 0x2f, 0x24, 0xdf, 0x50, 0xb9, 0x62, 0x1a, ++ 0xc6, 0x9d, 0xcc, 0xb1, 0x62, 0x1a, 0xda, 0x19, 0x90, 0xab, 0x32, 0xeb, ++ 0x18, 0x71, 0x25, 0x7e, 0x59, 0xa2, 0xa1, 0xb7, 0x1b, 0x2e, 0x2a, 0x43, ++ 0xf7, 0x73, 0x3e, 0x8f, 0xe7, 0x49, 0xe7, 0xe4, 0x71, 0x79, 0xe9, 0xb6, ++ 0xd9, 0x7d, 0xa8, 0x37, 0xc7, 0xfb, 0xde, 0xe2, 0xbf, 0xc5, 0x3e, 0xc6, ++ 0xfb, 0xde, 0x22, 0x51, 0x33, 0xfc, 0x1e, 0xca, 0x5b, 0x62, 0x5c, 0x84, ++ 0x82, 0xf7, 0x40, 0x05, 0x0b, 0xc2, 0x79, 0xbf, 0xe3, 0x26, 0x0b, 0xe6, ++ 0x6d, 0x06, 0x8f, 0x5f, 0xa7, 0xbc, 0xee, 0xe0, 0x63, 0xe6, 0x25, 0xfc, ++ 0xbe, 0xc0, 0xcc, 0x26, 0x41, 0x7b, 0x4f, 0xc2, 0xac, 0x96, 0x40, 0x3b, ++ 0xb2, 0x75, 0x36, 0x5f, 0x27, 0x3c, 0x87, 0xfb, 0x2d, 0xf5, 0xe9, 0xba, ++ 0xaf, 0xcf, 0x0b, 0x65, 0x44, 0x8c, 0xe4, 0x85, 0xc8, 0x6f, 0xc8, 0x08, ++ 0xa7, 0x7b, 0x12, 0x5f, 0xe7, 0xe7, 0x64, 0xb7, 0x06, 0xbb, 0x73, 0x2d, ++ 0x78, 0x9f, 0xe1, 0xeb, 0x85, 0xe8, 0x10, 0xe4, 0xa9, 0xfe, 0xcf, 0xff, ++ 0x1d, 0x87, 0xf6, 0xd5, 0xd7, 0xfd, 0x09, 0xbd, 0x07, 0xf3, 0xdd, 0xf8, ++ 0x94, 0xde, 0x89, 0x6d, 0x16, 0xef, 0xf4, 0x4e, 0x74, 0x8a, 0x77, 0x56, ++ 0xbd, 0x4a, 0x04, 0x7d, 0x17, 0x57, 0xf4, 0x71, 0x21, 0xf6, 0xdb, 0x22, ++ 0x4a, 0x7f, 0x7e, 0x80, 0xe7, 0x89, 0xd5, 0x52, 0x8d, 0xff, 0x03, 0xe2, ++ 0xdf, 0xc9, 0xb3, 0xc7, 0x8e, 0x7f, 0x63, 0x1c, 0xe6, 0xc0, 0xbc, 0x80, ++ 0x12, 0x3f, 0x56, 0x1e, 0x25, 0x30, 0x2f, 0x90, 0xaa, 0xe5, 0x79, 0x01, ++ 0x2c, 0x31, 0x2f, 0x90, 0x9a, 0xca, 0xf3, 0x02, 0x08, 0x63, 0x5e, 0x00, ++ 0x4b, 0xcc, 0x0b, 0x60, 0x3d, 0xe6, 0x05, 0x10, 0xc6, 0xbc, 0x00, 0xc2, ++ 0x98, 0x17, 0x40, 0x18, 0xf3, 0x02, 0x58, 0x62, 0x5e, 0x00, 0xeb, 0xbf, ++ 0x10, 0xdf, 0x3f, 0x0c, 0x82, 0x62, 0xe2, 0xf9, 0x4a, 0x33, 0xe9, 0xf5, ++ 0xb5, 0xf8, 0xbe, 0x1d, 0xf0, 0xb7, 0xf6, 0x38, 0xbf, 0x77, 0x5a, 0xdb, ++ 0x2a, 0xd3, 0xfd, 0x2d, 0x7e, 0xff, 0x80, 0xf6, 0x6d, 0xd4, 0xbb, 0x99, ++ 0x76, 0xf1, 0x6e, 0xc6, 0xb3, 0x8d, 0xee, 0xf1, 0xea, 0x3b, 0x64, 0x2b, ++ 0x92, 0xa8, 0x5e, 0x37, 0x74, 0x12, 0xf3, 0x38, 0xf5, 0x87, 0x24, 0xeb, ++ 0x7a, 0xd4, 0x2b, 0x8d, 0x4b, 0x68, 0xfd, 0xcd, 0xdd, 0xb9, 0x1f, 0x94, ++ 0x62, 0x7d, 0xab, 0xce, 0xaa, 0x51, 0x88, 0x8f, 0x38, 0x1d, 0x9b, 0x25, ++ 0x7a, 0xa7, 0x5f, 0xdd, 0xdd, 0x4a, 0x79, 0xa7, 0xfc, 0xf8, 0xe3, 0x7a, ++ 0xaa, 0x6f, 0x93, 0x18, 0xe6, 0x49, 0xef, 0x35, 0xf0, 0x38, 0xd7, 0x29, ++ 0x43, 0x6d, 0x16, 0xdd, 0x83, 0x92, 0x1f, 0xec, 0x34, 0xf4, 0x52, 0xfc, ++ 0x51, 0x73, 0x40, 0x52, 0xca, 0x03, 0xdf, 0x69, 0xcc, 0xb9, 0x46, 0x7a, ++ 0x40, 0xbd, 0x4f, 0xae, 0xe0, 0x4d, 0xcc, 0xe9, 0x31, 0x29, 0xe5, 0x63, ++ 0xbc, 0x03, 0x19, 0x79, 0x77, 0x2e, 0xde, 0x4d, 0x57, 0xe0, 0x3d, 0x33, ++ 0xbe, 0x17, 0x97, 0x6f, 0xd0, 0xbb, 0x7e, 0x27, 0x04, 0xa4, 0x13, 0x90, ++ 0x0f, 0x77, 0xf0, 0xf7, 0xcf, 0x16, 0xf8, 0x47, 0xf2, 0x1e, 0xf2, 0xae, ++ 0xa9, 0xba, 0xfb, 0xd0, 0x46, 0x7c, 0x0f, 0x15, 0x7a, 0xdf, 0x3c, 0xf2, ++ 0x3d, 0x5d, 0xc8, 0xbd, 0x73, 0xd9, 0x6c, 0x71, 0xaf, 0x6c, 0xe3, 0xdf, ++ 0x57, 0x14, 0x3d, 0x5d, 0x7e, 0xb0, 0x03, 0xd6, 0x1b, 0xde, 0x6a, 0x20, ++ 0x7f, 0xa3, 0x21, 0xd7, 0xf1, 0x20, 0xf2, 0xd1, 0x49, 0x9d, 0x9d, 0xf2, ++ 0x23, 0x27, 0x8f, 0x9b, 0x28, 0x2e, 0x3a, 0xbf, 0xed, 0xb6, 0xa0, 0xfc, ++ 0xc8, 0x50, 0x96, 0xa3, 0x7a, 0x36, 0xe5, 0x9b, 0xa6, 0x50, 0xbe, 0x62, ++ 0x8d, 0x4e, 0x22, 0x7b, 0xbc, 0xa0, 0x28, 0x25, 0x1e, 0xf1, 0xb8, 0xe0, ++ 0x94, 0x8e, 0xec, 0x4e, 0x4f, 0x56, 0x49, 0x2d, 0xf6, 0x5b, 0x33, 0x4b, ++ 0xa1, 0x7c, 0x54, 0x81, 0x81, 0xfd, 0x82, 0xe6, 0x11, 0xef, 0xa5, 0x54, ++ 0x7a, 0x14, 0x34, 0x49, 0x6e, 0x0d, 0xc0, 0x2b, 0x98, 0x95, 0xde, 0xd9, ++ 0x2f, 0x07, 0x34, 0x61, 0xbe, 0x72, 0x50, 0x67, 0xde, 0x84, 0xef, 0x9a, ++ 0x96, 0x33, 0xfe, 0xce, 0x41, 0xe5, 0x9b, 0x35, 0xdb, 0x24, 0xe2, 0x1b, ++ 0x4c, 0x10, 0x20, 0x3e, 0xcb, 0x04, 0x3e, 0x97, 0x77, 0xff, 0xfe, 0x3a, ++ 0xbe, 0x63, 0x58, 0x69, 0xe0, 0x7e, 0x6b, 0xa2, 0x86, 0xdf, 0x5f, 0x27, ++ 0x6e, 0xe1, 0xef, 0x19, 0x1e, 0x64, 0x0e, 0x3d, 0xda, 0xd9, 0x55, 0xc8, ++ 0x5d, 0x32, 0xd9, 0xc7, 0xdf, 0x0d, 0x40, 0xbd, 0x23, 0x7c, 0x4a, 0x12, ++ 0xf7, 0xcb, 0x95, 0x78, 0x9c, 0x7f, 0xc5, 0x69, 0x1d, 0xbd, 0xb7, 0x2d, ++ 0x88, 0xff, 0x71, 0x9a, 0x83, 0xec, 0x74, 0x3e, 0xbd, 0x63, 0x90, 0xbc, ++ 0xcb, 0xe4, 0x9b, 0x77, 0x8c, 0x2f, 0x3f, 0xa1, 0xef, 0x18, 0x4e, 0xea, ++ 0xb8, 0x5e, 0x01, 0x3c, 0x52, 0x3c, 0xd4, 0x83, 0x7c, 0x49, 0x79, 0x19, ++ 0x07, 0x95, 0xa7, 0x1b, 0x2b, 0xa9, 0xac, 0x13, 0xdf, 0x43, 0x8c, 0x7e, ++ 0xff, 0x3f, 0x74, 0x16, 0xe3, 0xc4, 0xc4, 0xf8, 0x08, 0x2b, 0xea, 0xb9, ++ 0x71, 0xbf, 0x77, 0x0b, 0xfb, 0xfa, 0xef, 0xbd, 0x76, 0x8a, 0xf7, 0x6b, ++ 0x89, 0x9a, 0xbe, 0x6c, 0x05, 0xf1, 0xf1, 0x27, 0xb3, 0x15, 0xf1, 0xa1, ++ 0xbe, 0x13, 0xec, 0xb6, 0x95, 0x34, 0x23, 0x9d, 0xec, 0x91, 0xcc, 0x65, ++ 0xa1, 0xef, 0xc1, 0x40, 0x03, 0x02, 0x5e, 0x0b, 0xf1, 0x20, 0x12, 0xe6, ++ 0xb5, 0x3d, 0x76, 0xfc, 0xee, 0x68, 0xe8, 0xb8, 0x64, 0xa1, 0x77, 0xc9, ++ 0xa3, 0xf4, 0xe3, 0xb6, 0xc7, 0xf0, 0x9d, 0x48, 0x7d, 0xaa, 0x64, 0x91, ++ 0x14, 0xcc, 0x7f, 0x6f, 0x2d, 0x88, 0x83, 0x7d, 0x17, 0x4e, 0x4f, 0xa6, ++ 0x7d, 0xd7, 0x77, 0xf2, 0xfc, 0x28, 0x61, 0x28, 0x0e, 0xf3, 0xe7, 0x9c, ++ 0x5e, 0x91, 0x59, 0x8e, 0xc3, 0xb3, 0x73, 0xfd, 0xf5, 0xc5, 0x42, 0x6e, ++ 0x7c, 0xd0, 0x9f, 0xf3, 0xc9, 0x77, 0xdd, 0xc8, 0x6f, 0xdf, 0x20, 0x6f, ++ 0xba, 0x17, 0xfb, 0xbb, 0x98, 0x89, 0xbe, 0xa7, 0xa6, 0x3f, 0xd8, 0x4f, ++ 0xf1, 0x1d, 0x53, 0x29, 0x7f, 0xaa, 0xf2, 0xcd, 0x70, 0x5b, 0x7c, 0x0b, ++ 0xf2, 0xcd, 0xef, 0x67, 0xf3, 0x38, 0xb2, 0xb4, 0xf4, 0x7d, 0x1d, 0xda, ++ 0xff, 0x9e, 0x6c, 0xc7, 0x09, 0xdc, 0x47, 0x59, 0xf9, 0xb5, 0xc7, 0xe2, ++ 0xe8, 0x7c, 0x63, 0xe7, 0xaf, 0xd4, 0x77, 0xea, 0xa1, 0xf9, 0xab, 0x40, ++ 0xfd, 0xf9, 0xff, 0xf1, 0x3e, 0xfd, 0x9d, 0xc6, 0x06, 0x2a, 0xdf, 0x6b, ++ 0x5c, 0x47, 0x65, 0x6f, 0xa3, 0x8b, 0xda, 0x03, 0xf4, 0xff, 0x7f, 0x8e, ++ 0xa3, 0xff, 0x43, 0xf3, 0x9f, 0xe7, 0xb0, 0x5f, 0x68, 0xfe, 0x93, 0x19, ++ 0x95, 0x28, 0xb2, 0x9f, 0x20, 0xdf, 0x3c, 0xdf, 0x1c, 0x92, 0xef, 0x2c, ++ 0x9a, 0xf0, 0xc0, 0x26, 0xc0, 0xdf, 0x82, 0xed, 0x7a, 0x2b, 0x56, 0xa9, ++ 0xf9, 0x4f, 0x7c, 0x3f, 0xbc, 0xd6, 0x4c, 0xfa, 0xe0, 0xf2, 0xec, 0x31, ++ 0xf3, 0x9e, 0x2a, 0xde, 0xcc, 0x94, 0x27, 0x1d, 0x66, 0xa6, 0x2c, 0xc4, ++ 0xff, 0xfc, 0xf4, 0x14, 0xad, 0x06, 0xda, 0xbf, 0x10, 0x74, 0x50, 0xf3, ++ 0x8e, 0x28, 0x1f, 0x78, 0x3e, 0x94, 0x0f, 0x2c, 0x51, 0x3e, 0xb4, 0x5a, ++ 0xbf, 0x7c, 0xbc, 0xa0, 0x07, 0x11, 0xce, 0xe1, 0x76, 0xde, 0x45, 0x76, ++ 0xde, 0x44, 0x74, 0xdd, 0xb8, 0x1e, 0xf4, 0x07, 0xc0, 0x2b, 0x99, 0x25, ++ 0x48, 0x7f, 0x5c, 0x0d, 0xd1, 0x1f, 0x10, 0x70, 0xdc, 0x47, 0xdf, 0x55, ++ 0x75, 0x1b, 0x18, 0xe6, 0x09, 0xd5, 0x77, 0x94, 0xf3, 0xa1, 0xf8, 0x2a, ++ 0x6b, 0x0c, 0x7d, 0xe2, 0xe1, 0xfa, 0x64, 0x6a, 0x98, 0xe7, 0x25, 0xfa, ++ 0xde, 0xbf, 0x2e, 0x8c, 0xde, 0xe7, 0x9e, 0x14, 0xef, 0xe1, 0x4e, 0x6e, ++ 0xe6, 0xef, 0xe1, 0xca, 0x59, 0x09, 0xad, 0x3b, 0x86, 0x5e, 0x89, 0x44, ++ 0x7a, 0xac, 0x9c, 0x30, 0x74, 0xf6, 0x79, 0xe8, 0xbf, 0xf2, 0xd7, 0x66, ++ 0xf2, 0x57, 0x36, 0x4e, 0xaa, 0xc8, 0xfb, 0x5b, 0xf4, 0xca, 0xe0, 0x6c, ++ 0x8e, 0x8f, 0x67, 0xf1, 0x77, 0x05, 0xb4, 0x5f, 0xf7, 0xbb, 0x02, 0x4f, ++ 0x48, 0x78, 0x1f, 0xba, 0xe6, 0x7e, 0x66, 0x43, 0x3a, 0xab, 0xbf, 0x2b, ++ 0x10, 0x2f, 0xee, 0xb3, 0xbf, 0xc5, 0xef, 0x0a, 0xdc, 0x36, 0x67, 0xe2, ++ 0x37, 0xff, 0x5d, 0x81, 0xcc, 0x39, 0xf1, 0xa5, 0x81, 0xbf, 0x2b, 0x90, ++ 0xd9, 0x39, 0x89, 0xc3, 0xea, 0xef, 0x0a, 0xb0, 0xf8, 0xd2, 0x71, 0x7e, ++ 0x57, 0x20, 0x7b, 0x4e, 0xee, 0xe8, 0xdf, 0x15, 0x98, 0x3d, 0x87, 0xc7, ++ 0x39, 0xe3, 0xfd, 0xae, 0x00, 0xf8, 0x93, 0x73, 0x70, 0x7f, 0x3a, 0x9b, ++ 0xfd, 0x4e, 0x2c, 0x13, 0xc5, 0x3e, 0x43, 0xbf, 0xa7, 0x3d, 0x2d, 0xee, ++ 0xef, 0x7a, 0x34, 0x8e, 0x52, 0x2c, 0x0b, 0x23, 0x5d, 0x5a, 0xaa, 0xd7, ++ 0xb8, 0x73, 0xb0, 0x7c, 0x5b, 0xe3, 0xf9, 0x39, 0xd6, 0x03, 0x3f, 0xe7, ++ 0xe3, 0x3e, 0x0a, 0x9f, 0xb2, 0xdd, 0x9e, 0x0e, 0x70, 0xa2, 0xc1, 0x43, ++ 0x7a, 0xb2, 0x27, 0xcb, 0x5e, 0x80, 0xf5, 0x83, 0x36, 0x7b, 0x21, 0xae, ++ 0x13, 0x9a, 0x37, 0x47, 0xda, 0x62, 0x7c, 0x0f, 0xfb, 0x59, 0x84, 0xed, ++ 0xa1, 0xef, 0xae, 0x54, 0x7a, 0xae, 0x98, 0xc3, 0xf9, 0xfe, 0x01, 0x51, ++ 0xce, 0x6d, 0x1a, 0xfb, 0x7b, 0xf2, 0x07, 0xe6, 0xf0, 0xef, 0xd5, 0x6e, ++ 0xb5, 0x6f, 0xd8, 0xef, 0x7d, 0xb8, 0x2f, 0x75, 0xff, 0x6c, 0xeb, 0x8a, ++ 0x1c, 0x92, 0xa7, 0x2c, 0xfb, 0x32, 0xb1, 0xdf, 0x52, 0x2c, 0x99, 0x39, ++ 0x26, 0xe8, 0xfb, 0xd4, 0xd1, 0x7c, 0xe6, 0x12, 0xfb, 0xe2, 0xfc, 0x05, ++ 0xfa, 0xac, 0xf8, 0x3c, 0xf7, 0x07, 0xa9, 0x4c, 0xd3, 0xba, 0xa3, 0xd1, ++ 0x7f, 0x9c, 0xfc, 0x88, 0x3b, 0x1a, 0xf7, 0x3b, 0xb9, 0x79, 0xc8, 0x84, ++ 0xdf, 0x41, 0xbc, 0xe8, 0x1a, 0x32, 0xa1, 0x7d, 0x7f, 0xf1, 0xe1, 0x21, ++ 0x13, 0xd6, 0xbf, 0x68, 0xe7, 0xef, 0x95, 0x43, 0xe7, 0x7f, 0x71, 0x0e, ++ 0xff, 0x4e, 0x20, 0x6d, 0xee, 0x10, 0x8d, 0x9f, 0x06, 0xff, 0xdd, 0x4b, ++ 0xfe, 0xf9, 0x50, 0x34, 0xfa, 0x4f, 0x69, 0x95, 0xe7, 0x37, 0xd2, 0x7d, ++ 0xcb, 0x81, 0x99, 0x64, 0x5f, 0xa6, 0x09, 0xfb, 0x32, 0xed, 0x91, 0xe9, ++ 0x9d, 0x03, 0xc0, 0x6f, 0xd3, 0x9e, 0x8b, 0xa2, 0xfb, 0x6c, 0x96, 0x1f, ++ 0x4b, 0xed, 0xd5, 0x46, 0x2e, 0xa7, 0xd5, 0x8f, 0x94, 0x1f, 0xe9, 0x50, ++ 0xe8, 0xbb, 0xad, 0xe2, 0xf3, 0x01, 0xfe, 0xce, 0x4c, 0x37, 0xec, 0x3b, ++ 0xc8, 0xff, 0xd2, 0x0e, 0xf3, 0x77, 0x97, 0x00, 0x23, 0x9e, 0x0e, 0xe8, ++ 0x08, 0x46, 0x9e, 0x45, 0xff, 0xca, 0xc9, 0xf8, 0xbb, 0xcb, 0xc9, 0x42, ++ 0x6f, 0xa0, 0x9f, 0x56, 0x0a, 0x7a, 0xc1, 0x59, 0xf9, 0xe6, 0x75, 0xba, ++ 0xf7, 0xc7, 0xf1, 0x38, 0x1f, 0xde, 0xd1, 0x22, 0xff, 0x75, 0xea, 0x86, ++ 0xc5, 0xf7, 0x69, 0x16, 0x8c, 0x43, 0x57, 0x2d, 0x59, 0xdf, 0x43, 0x71, ++ 0xe1, 0x8e, 0x91, 0x7a, 0x11, 0x67, 0x1e, 0xda, 0x88, 0x71, 0x33, 0xf8, ++ 0x6f, 0x41, 0xf5, 0xd5, 0xe5, 0xaf, 0xf7, 0xa0, 0xbd, 0xa9, 0x39, 0x10, ++ 0x5c, 0xef, 0x6c, 0xb8, 0x46, 0xf1, 0x2b, 0xf8, 0x6f, 0x41, 0xf5, 0xf7, ++ 0xff, 0xfc, 0x9c, 0x9e, 0xff, 0x7e, 0x41, 0x70, 0x3d, 0xd0, 0x77, 0x07, ++ 0xf2, 0x9b, 0x4a, 0xdf, 0x93, 0x3a, 0xcf, 0x4c, 0x8c, 0xf3, 0x4e, 0x3a, ++ 0xc3, 0xac, 0xfc, 0xfd, 0xbe, 0x87, 0x7e, 0xaf, 0xa4, 0x45, 0x7c, 0xff, ++ 0xbc, 0xe7, 0x9f, 0xe7, 0xe7, 0xf0, 0xf7, 0xa2, 0x9c, 0xde, 0x30, 0xde, ++ 0xfd, 0xcd, 0xf8, 0xa3, 0x89, 0xfa, 0xbb, 0xe6, 0xb3, 0x74, 0x94, 0x87, ++ 0x5b, 0x95, 0xaa, 0x5e, 0x1a, 0xf9, 0xfd, 0x13, 0x3d, 0x73, 0x51, 0x7e, ++ 0x6f, 0x51, 0x04, 0xe9, 0x9d, 0x7a, 0x11, 0x57, 0xd5, 0x95, 0x5b, 0xc8, ++ 0xce, 0x27, 0xd6, 0x19, 0x49, 0x7f, 0x15, 0xc8, 0x61, 0x56, 0x84, 0x47, ++ 0x7e, 0xff, 0xa4, 0x48, 0x16, 0x7a, 0xca, 0x43, 0xf2, 0xdf, 0x77, 0x57, ++ 0x34, 0xe5, 0xf1, 0xe8, 0x00, 0x08, 0xc7, 0xcc, 0xa2, 0x7b, 0x9f, 0xb8, ++ 0x26, 0x0e, 0x0f, 0x4d, 0x34, 0x90, 0x7e, 0x28, 0xd0, 0x94, 0xd4, 0xee, ++ 0x87, 0xf2, 0x4d, 0x4d, 0xf0, 0x77, 0xec, 0x2f, 0xa0, 0x7e, 0x90, 0x51, ++ 0x7e, 0x79, 0x3e, 0xb5, 0x5e, 0xef, 0xe1, 0xdf, 0x89, 0x6b, 0x95, 0x5c, ++ 0x8c, 0x73, 0x9b, 0x24, 0xfb, 0x73, 0xf8, 0xdd, 0x63, 0x93, 0x24, 0xf2, ++ 0x88, 0x55, 0x66, 0xba, 0x2f, 0x18, 0xc4, 0xfc, 0x22, 0x9c, 0x67, 0x7b, ++ 0xb4, 0xfb, 0xb9, 0x0a, 0x58, 0x67, 0xfb, 0x3d, 0x19, 0xe4, 0x1f, 0x0f, ++ 0x32, 0xae, 0x4f, 0x5d, 0x4b, 0xf8, 0xbd, 0xd5, 0xf6, 0xe8, 0x92, 0xd2, ++ 0xd5, 0xd8, 0xbe, 0xf4, 0x76, 0x6a, 0x3f, 0xf2, 0x97, 0x94, 0x27, 0x73, ++ 0xd0, 0x7f, 0xaa, 0x0a, 0xb3, 0xa2, 0xff, 0xb4, 0xdd, 0xc6, 0xfd, 0xeb, ++ 0xed, 0x8b, 0xd3, 0xa9, 0xfd, 0x98, 0xa4, 0xac, 0xc7, 0x73, 0xbb, 0x1e, ++ 0x61, 0xb4, 0xce, 0xf6, 0xc5, 0xfc, 0xdc, 0xdb, 0x9f, 0x9c, 0x2a, 0xbe, ++ 0xbf, 0x70, 0x9b, 0x50, 0x9e, 0xb7, 0x37, 0xdb, 0x27, 0xe1, 0x7d, 0xd4, ++ 0x7c, 0x8b, 0xe3, 0x0c, 0xd2, 0x6b, 0xb2, 0xb8, 0x8f, 0xdb, 0x9e, 0x0c, ++ 0xf5, 0x50, 0x3e, 0x23, 0x95, 0x2c, 0x7d, 0x10, 0xe7, 0x99, 0xc5, 0xf7, ++ 0x5b, 0x67, 0x53, 0x88, 0x5e, 0x27, 0x97, 0xde, 0xfe, 0xe4, 0x3e, 0x85, ++ 0xcc, 0x88, 0x17, 0xef, 0x85, 0xea, 0x17, 0x45, 0x50, 0x1c, 0xfc, 0xbf, ++ 0x93, 0x01, 0x13, 0x53, 0xf0, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++}; ++ ++void bnx2x_init_e1_firmware(struct bnx2x *bp) ++{ ++ INIT_OPS(bp) = (struct raw_op *)init_ops_e1; ++ INIT_DATA(bp) = (u32 *)init_data_e1; ++ INIT_OPS_OFFSETS(bp) = (u16 *)init_ops_offsets_e1; ++ INIT_TSEM_INT_TABLE_DATA(bp) = tsem_int_table_data_e1; ++ INIT_TSEM_PRAM_DATA(bp) = tsem_pram_data_e1; ++ INIT_USEM_INT_TABLE_DATA(bp) = usem_int_table_data_e1; ++ INIT_USEM_PRAM_DATA(bp) = usem_pram_data_e1; ++ INIT_XSEM_INT_TABLE_DATA(bp) = xsem_int_table_data_e1; ++ INIT_XSEM_PRAM_DATA(bp) = xsem_pram_data_e1; ++ INIT_CSEM_INT_TABLE_DATA(bp) = csem_int_table_data_e1; ++ INIT_CSEM_PRAM_DATA(bp) = csem_pram_data_e1; ++} ++ +diff -r e67cb9a8e847 drivers/net/bnx2x_init_values_e1h.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/bnx2x_init_values_e1h.c Wed Aug 05 10:51:03 2009 +0100 +@@ -0,0 +1,17784 @@ ++/* init_ops array contains the list of operations needed to initialize the chip. ++ * ++ * For each block in the chip there are three init stages: ++ * common - HW used by both ports, ++ * port1 and port2 - initialization for a specific Ethernet port. ++ * When a port is opened or closed, the management CPU tells the driver ++ * whether to init/disable common HW in addition to the port HW. ++ * This way the first port going up will first initializes the common HW, ++ * and the last port going down also resets the common HW ++ * ++ * For each init stage/block there is a list of actions needed in a format: ++ * {operation, register, data} ++ * where: ++ * OP_WR - write a value to the chip. ++ * OP_RD - read a register (usually a clear on read register). ++ * OP_SW - string write, write a section of consecutive addresses to the chip. ++ * OP_SI - copy a string using indirect writes. ++ * OP_ZR - clear a range of memory. ++ * OP_ZP - unzip and copy using DMAE. ++ * OP_WB - string copy using DMAE. ++ * ++ * The #defines mark the stages. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include "bnx2x_compat.h" ++#include "bnx2x_init.h" ++#include "bnx2x.h" ++ ++ ++static const struct raw_op init_ops_e1h[] = { ++/* #define PRS_COMMON_START 0 */ ++ {OP_WR, PRS_REG_INC_VALUE, 0xf}, ++ {OP_WR, PRS_REG_EVENT_ID_1, 0x45}, ++ {OP_WR, PRS_REG_EVENT_ID_2, 0x84}, ++ {OP_WR, PRS_REG_EVENT_ID_3, 0x6}, ++ {OP_WR, PRS_REG_NO_MATCH_EVENT_ID, 0x4}, ++ {OP_WR, PRS_REG_CM_HDR_TYPE_0, 0x0}, ++ {OP_WR, PRS_REG_CM_HDR_TYPE_1, 0x12170000}, ++ {OP_WR, PRS_REG_CM_HDR_TYPE_2, 0x22170000}, ++ {OP_WR, PRS_REG_CM_HDR_TYPE_3, 0x32170000}, ++ {OP_ZR, PRS_REG_CM_HDR_TYPE_4, 0x5}, ++ {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_1, 0x12150000}, ++ {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_2, 0x22150000}, ++ {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_3, 0x32150000}, ++ {OP_ZR, PRS_REG_CM_HDR_LOOPBACK_TYPE_4, 0x4}, ++ {OP_WR, PRS_REG_CM_NO_MATCH_HDR, 0x2100000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0x100000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x40100000}, ++ {OP_ZR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5, 0x3}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000}, ++ {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x42140000}, ++ {OP_ZR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5, 0x3}, ++ {OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0}, ++ {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0}, ++ {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0}, ++ {OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0}, ++ {OP_WR, PRS_REG_FCOE_TYPE, 0x8906}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_3, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_4, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_5, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_6, 0xff}, ++ {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_7, 0xff}, ++ {OP_WR, PRS_REG_PURE_REGIONS, 0x3e}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_0, 0x0}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_4, 0x3f}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f}, ++ {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f}, ++/* #define PRS_COMMON_END 1 */ ++/* #define SRCH_COMMON_START 22 */ ++ {OP_WR, SRC_REG_E1HMF_ENABLE, 0x1}, ++/* #define SRCH_COMMON_END 23 */ ++/* #define TSDM_COMMON_START 44 */ ++ {OP_WR, TSDM_REG_CFC_RSP_START_ADDR, 0x211}, ++ {OP_WR, TSDM_REG_CMP_COUNTER_START_ADDR, 0x200}, ++ {OP_WR, TSDM_REG_Q_COUNTER_START_ADDR, 0x204}, ++ {OP_WR, TSDM_REG_PCK_END_MSG_START_ADDR, 0x219}, ++ {OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff}, ++ {OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff}, ++ {OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff}, ++ {OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff}, ++ {OP_WR, TSDM_REG_AGG_INT_EVENT_0, 0x20}, ++ {OP_WR, TSDM_REG_AGG_INT_EVENT_1, 0x0}, ++ {OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34}, ++ {OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35}, ++ {OP_ZR, TSDM_REG_AGG_INT_EVENT_4, 0x1c}, ++ {OP_WR, TSDM_REG_AGG_INT_T_0, 0x1}, ++ {OP_ZR, TSDM_REG_AGG_INT_T_1, 0x5f}, ++ {OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff}, ++ {OP_WR, TSDM_REG_ENABLE_IN2, 0x3f}, ++ {OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff}, ++ {OP_WR, TSDM_REG_ENABLE_OUT2, 0xf}, ++ {OP_RD, TSDM_REG_NUM_OF_Q0_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q1_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q3_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q4_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q5_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q6_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q7_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q8_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q9_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q10_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_Q11_CMD, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, ++ {OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, ++ {OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8}, ++ {OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1}, ++ {OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa}, ++/* #define TSDM_COMMON_END 45 */ ++/* #define TCM_COMMON_START 66 */ ++ {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20}, ++ {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32}, ++ {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020}, ++ {OP_WR, TCM_REG_TQM_TCM_HDR_S, 0x2150020}, ++ {OP_WR, TCM_REG_TM_TCM_HDR, 0x30}, ++ {OP_WR, TCM_REG_ERR_TCM_HDR, 0x8100000}, ++ {OP_WR, TCM_REG_ERR_EVNT_ID, 0x33}, ++ {OP_WR, TCM_REG_EXPR_EVNT_ID, 0x30}, ++ {OP_WR, TCM_REG_STOP_EVNT_ID, 0x31}, ++ {OP_WR, TCM_REG_STORM_WEIGHT, 0x2}, ++ {OP_WR, TCM_REG_PRS_WEIGHT, 0x5}, ++ {OP_WR, TCM_REG_PBF_WEIGHT, 0x6}, ++ {OP_WR, TCM_REG_USEM_WEIGHT, 0x2}, ++ {OP_WR, TCM_REG_CSEM_WEIGHT, 0x2}, ++ {OP_WR, TCM_REG_CP_WEIGHT, 0x0}, ++ {OP_WR, TCM_REG_TSDM_WEIGHT, 0x5}, ++ {OP_WR, TCM_REG_TQM_P_WEIGHT, 0x2}, ++ {OP_WR, TCM_REG_TQM_S_WEIGHT, 0x2}, ++ {OP_WR, TCM_REG_TM_WEIGHT, 0x2}, ++ {OP_WR, TCM_REG_TCM_TQM_USE_Q, 0x1}, ++ {OP_WR, TCM_REG_GR_ARB_TYPE, 0x1}, ++ {OP_WR, TCM_REG_GR_LD0_PR, 0x1}, ++ {OP_WR, TCM_REG_GR_LD1_PR, 0x2}, ++ {OP_WR, TCM_REG_CFC_INIT_CRD, 0x1}, ++ {OP_WR, TCM_REG_FIC0_INIT_CRD, 0x40}, ++ {OP_WR, TCM_REG_FIC1_INIT_CRD, 0x40}, ++ {OP_WR, TCM_REG_TQM_INIT_CRD, 0x20}, ++ {OP_WR, TCM_REG_XX_INIT_CRD, 0x13}, ++ {OP_WR, TCM_REG_XX_MSG_NUM, 0x20}, ++ {OP_ZR, TCM_REG_XX_TABLE, 0xa}, ++ {OP_SW, TCM_REG_XX_DESCR_TABLE, 0x200000}, ++ {OP_WR, TCM_REG_N_SM_CTX_LD_0, 0x7}, ++ {OP_WR, TCM_REG_N_SM_CTX_LD_1, 0x7}, ++ {OP_WR, TCM_REG_N_SM_CTX_LD_2, 0x8}, ++ {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8}, ++ {OP_WR, TCM_REG_N_SM_CTX_LD_4, 0x1}, ++ {OP_ZR, TCM_REG_N_SM_CTX_LD_5, 0x3}, ++ {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6}, ++ {OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1}, ++ {OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1}, ++ {OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_STORM_TCM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_TQM_TCM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_TSDM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_TM_TCM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_PRS_IFEN, 0x1}, ++ {OP_WR, TCM_REG_PBF_IFEN, 0x1}, ++ {OP_WR, TCM_REG_USEM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_CSEM_IFEN, 0x1}, ++ {OP_WR, TCM_REG_CDU_AG_WR_IFEN, 0x1}, ++ {OP_WR, TCM_REG_CDU_AG_RD_IFEN, 0x1}, ++ {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1}, ++ {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1}, ++ {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1}, ++/* #define TCM_COMMON_END 67 */ ++/* #define TCM_FUNC0_START 72 */ ++ {OP_WR, TCM_REG_PHYS_QNUM0_0, 0xd}, ++ {OP_WR, TCM_REG_PHYS_QNUM1_0, 0x7}, ++ {OP_WR, TCM_REG_PHYS_QNUM2_0, 0x7}, ++ {OP_WR, TCM_REG_PHYS_QNUM3_0, 0x7}, ++/* #define TCM_FUNC0_END 73 */ ++/* #define TCM_FUNC1_START 74 */ ++ {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x2d}, ++ {OP_WR, TCM_REG_PHYS_QNUM1_1, 0x27}, ++ {OP_WR, TCM_REG_PHYS_QNUM2_1, 0x27}, ++ {OP_WR, TCM_REG_PHYS_QNUM3_1, 0x27}, ++/* #define TCM_FUNC1_END 75 */ ++/* #define TCM_FUNC2_START 76 */ ++ {OP_WR, TCM_REG_PHYS_QNUM0_0, 0x1d}, ++ {OP_WR, TCM_REG_PHYS_QNUM1_0, 0x17}, ++ {OP_WR, TCM_REG_PHYS_QNUM2_0, 0x17}, ++ {OP_WR, TCM_REG_PHYS_QNUM3_0, 0x17}, ++/* #define TCM_FUNC2_END 77 */ ++/* #define TCM_FUNC3_START 78 */ ++ {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x3d}, ++ {OP_WR, TCM_REG_PHYS_QNUM1_1, 0x37}, ++ {OP_WR, TCM_REG_PHYS_QNUM2_1, 0x37}, ++ {OP_WR, TCM_REG_PHYS_QNUM3_1, 0x37}, ++/* #define TCM_FUNC3_END 79 */ ++/* #define TCM_FUNC4_START 80 */ ++ {OP_WR, TCM_REG_PHYS_QNUM0_0, 0x4d}, ++ {OP_WR, TCM_REG_PHYS_QNUM1_0, 0x47}, ++ {OP_WR, TCM_REG_PHYS_QNUM2_0, 0x47}, ++ {OP_WR, TCM_REG_PHYS_QNUM3_0, 0x47}, ++/* #define TCM_FUNC4_END 81 */ ++/* #define TCM_FUNC5_START 82 */ ++ {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x6d}, ++ {OP_WR, TCM_REG_PHYS_QNUM1_1, 0x67}, ++ {OP_WR, TCM_REG_PHYS_QNUM2_1, 0x67}, ++ {OP_WR, TCM_REG_PHYS_QNUM3_1, 0x67}, ++/* #define TCM_FUNC5_END 83 */ ++/* #define TCM_FUNC6_START 84 */ ++ {OP_WR, TCM_REG_PHYS_QNUM0_0, 0x5d}, ++ {OP_WR, TCM_REG_PHYS_QNUM1_0, 0x57}, ++ {OP_WR, TCM_REG_PHYS_QNUM2_0, 0x57}, ++ {OP_WR, TCM_REG_PHYS_QNUM3_0, 0x57}, ++/* #define TCM_FUNC6_END 85 */ ++/* #define TCM_FUNC7_START 86 */ ++ {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x7d}, ++ {OP_WR, TCM_REG_PHYS_QNUM1_1, 0x77}, ++ {OP_WR, TCM_REG_PHYS_QNUM2_1, 0x77}, ++ {OP_WR, TCM_REG_PHYS_QNUM3_1, 0x77}, ++/* #define TCM_FUNC7_END 87 */ ++/* #define BRB1_COMMON_START 88 */ ++ {OP_SW, BRB1_REG_LL_RAM, 0x2000020}, ++ {OP_WR, BRB1_REG_SOFT_RESET, 0x1}, ++ {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0}, ++ {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220}, ++ {OP_WR, BRB1_REG_SOFT_RESET, 0x0}, ++/* #define BRB1_COMMON_END 89 */ ++/* #define BRB1_PORT0_START 90 */ ++ {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0}, ++ {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0}, ++/* #define BRB1_PORT0_END 91 */ ++/* #define BRB1_PORT1_START 92 */ ++ {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0}, ++ {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0}, ++/* #define BRB1_PORT1_END 93 */ ++/* #define TSEM_COMMON_START 110 */ ++ {OP_ZP, TSEM_REG_INT_TABLE, 0xa90000}, ++ {OP_WR_64, TSEM_REG_INT_TABLE + 0x3c8, 0x70223}, ++ {OP_ZP, TSEM_REG_PRAM, 0x2c2d0000}, ++ {OP_ZP, TSEM_REG_PRAM + 0x8000, 0x38a20b0c}, ++ {OP_ZP, TSEM_REG_PRAM + 0x10000, 0x28ef1935}, ++ {OP_WR_64, TSEM_REG_PRAM + 0x16810, 0x52fe0225}, ++ {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0}, ++ {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0}, ++ {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0}, ++ {OP_RD, TSEM_REG_MSG_NUM_FOC1, 0x0}, ++ {OP_RD, TSEM_REG_MSG_NUM_FOC2, 0x0}, ++ {OP_RD, TSEM_REG_MSG_NUM_FOC3, 0x0}, ++ {OP_WR, TSEM_REG_ARB_ELEMENT0, 0x1}, ++ {OP_WR, TSEM_REG_ARB_ELEMENT1, 0x2}, ++ {OP_WR, TSEM_REG_ARB_ELEMENT2, 0x3}, ++ {OP_WR, TSEM_REG_ARB_ELEMENT3, 0x0}, ++ {OP_WR, TSEM_REG_ARB_ELEMENT4, 0x4}, ++ {OP_WR, TSEM_REG_ARB_CYCLE_SIZE, 0x1}, ++ {OP_WR, TSEM_REG_TS_0_AS, 0x0}, ++ {OP_WR, TSEM_REG_TS_1_AS, 0x1}, ++ {OP_WR, TSEM_REG_TS_2_AS, 0x4}, ++ {OP_WR, TSEM_REG_TS_3_AS, 0x0}, ++ {OP_WR, TSEM_REG_TS_4_AS, 0x1}, ++ {OP_WR, TSEM_REG_TS_5_AS, 0x3}, ++ {OP_WR, TSEM_REG_TS_6_AS, 0x0}, ++ {OP_WR, TSEM_REG_TS_7_AS, 0x1}, ++ {OP_WR, TSEM_REG_TS_8_AS, 0x4}, ++ {OP_WR, TSEM_REG_TS_9_AS, 0x0}, ++ {OP_WR, TSEM_REG_TS_10_AS, 0x1}, ++ {OP_WR, TSEM_REG_TS_11_AS, 0x3}, ++ {OP_WR, TSEM_REG_TS_12_AS, 0x0}, ++ {OP_WR, TSEM_REG_TS_13_AS, 0x1}, ++ {OP_WR, TSEM_REG_TS_14_AS, 0x4}, ++ {OP_WR, TSEM_REG_TS_15_AS, 0x0}, ++ {OP_WR, TSEM_REG_TS_16_AS, 0x4}, ++ {OP_WR, TSEM_REG_TS_17_AS, 0x3}, ++ {OP_ZR, TSEM_REG_TS_18_AS, 0x2}, ++ {OP_WR, TSEM_REG_ENABLE_IN, 0x3fff}, ++ {OP_WR, TSEM_REG_ENABLE_OUT, 0x3ff}, ++ {OP_WR, TSEM_REG_FIC0_DISABLE, 0x0}, ++ {OP_WR, TSEM_REG_FIC1_DISABLE, 0x0}, ++ {OP_WR, TSEM_REG_PAS_DISABLE, 0x0}, ++ {OP_WR, TSEM_REG_THREADS_LIST, 0xff}, ++ {OP_ZR, TSEM_REG_PASSIVE_BUFFER, 0x400}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x18bc0, 0x1}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x18000, 0x34}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20}, ++ {OP_WR_ASIC, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, ++ {OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x18300, 0x138}, ++ {OP_WR_FPGA, TSEM_REG_FAST_MEMORY + 0x18300, 0x1388}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x11480, 0x1}, ++ {OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x11480, 0x0}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1000, 0x3b3}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x1000 + 0xecc, 0x10227}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xa020, 0xc8}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xa000, 0x2}, ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x1ed0, 0x0}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1ed8, 0x6}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x36e8, 0x4}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x36e0, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5000, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5008, 0x4}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5018, 0x4}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5028, 0x4}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5038, 0x4}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5048, 0x4}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5058, 0x4}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5068, 0x4}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5078, 0x2}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x4040, 0x20228}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4008, 0x2}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x62c0, 0x20022a}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd100, 0x2}, ++/* #define TSEM_COMMON_END 111 */ ++/* #define TSEM_PORT0_START 112 */ ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2000, 0x124}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xb000, 0x28}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xb140, 0xc}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3300, 0x14}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x33a0, 0x68}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x8108, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd1c8, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd1d8, 0x20}, ++/* #define TSEM_PORT0_END 113 */ ++/* #define TSEM_PORT1_START 114 */ ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2490, 0x124}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xb0a0, 0x28}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xb170, 0xc}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3350, 0x14}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3540, 0x68}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x8110, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd1d0, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd258, 0x20}, ++/* #define TSEM_PORT1_END 115 */ ++/* #define TSEM_FUNC0_START 116 */ ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x2920, 0x0}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3000, 0x2}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x3000 + 0x8, 0x5024a}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3000 + 0x1c, 0x9}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3200, 0x8}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5000, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5080, 0x12}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0c0, 0x2}, ++/* #define TSEM_FUNC0_END 117 */ ++/* #define TSEM_FUNC1_START 118 */ ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x2924, 0x0}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3040, 0x2}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x3040 + 0x8, 0x5024f}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3040 + 0x1c, 0x9}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3220, 0x8}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5010, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x50c8, 0x12}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4008, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0c8, 0x2}, ++/* #define TSEM_FUNC1_END 119 */ ++/* #define TSEM_FUNC2_START 120 */ ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x2928, 0x0}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3080, 0x2}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x3080 + 0x8, 0x50254}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3080 + 0x1c, 0x9}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3240, 0x8}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5020, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5110, 0x12}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x4010, 0x20259}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0d0, 0x2}, ++/* #define TSEM_FUNC2_END 121 */ ++/* #define TSEM_FUNC3_START 122 */ ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x292c, 0x0}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x30c0, 0x2}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x30c0 + 0x8, 0x5025b}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x30c0 + 0x1c, 0x9}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3260, 0x8}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5030, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5158, 0x12}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x4018, 0x20260}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0d8, 0x2}, ++/* #define TSEM_FUNC3_END 123 */ ++/* #define TSEM_FUNC4_START 124 */ ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x2930, 0x0}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3100, 0x2}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x3100 + 0x8, 0x50262}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3100 + 0x1c, 0x9}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3280, 0x8}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5040, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x51a0, 0x12}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x4020, 0x20267}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0e0, 0x2}, ++/* #define TSEM_FUNC4_END 125 */ ++/* #define TSEM_FUNC5_START 126 */ ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x2934, 0x0}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3140, 0x2}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x3140 + 0x8, 0x50269}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3140 + 0x1c, 0x9}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x32a0, 0x8}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5050, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x51e8, 0x12}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x4028, 0x2026e}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0e8, 0x2}, ++/* #define TSEM_FUNC5_END 127 */ ++/* #define TSEM_FUNC6_START 128 */ ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x2938, 0x0}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3180, 0x2}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x3180 + 0x8, 0x50270}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3180 + 0x1c, 0x9}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x32c0, 0x8}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5060, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5230, 0x12}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x4030, 0x20275}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0f0, 0x2}, ++/* #define TSEM_FUNC6_END 129 */ ++/* #define TSEM_FUNC7_START 130 */ ++ {OP_WR, TSEM_REG_FAST_MEMORY + 0x293c, 0x0}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x31c0, 0x2}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x31c0 + 0x8, 0x50277}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x31c0 + 0x1c, 0x9}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x32e0, 0x8}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5070, 0x2}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5278, 0x12}, ++ {OP_SW, TSEM_REG_FAST_MEMORY + 0x4038, 0x2027c}, ++ {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0f8, 0x2}, ++/* #define TSEM_FUNC7_END 131 */ ++/* #define MISC_COMMON_START 220 */ ++ {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911}, ++ {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0}, ++ {OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424}, ++ {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0}, ++ {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209}, ++/* #define MISC_COMMON_END 221 */ ++/* #define MISC_FUNC0_START 226 */ ++ {OP_WR, MISC_REG_NIG_WOL_P0, 0x0}, ++/* #define MISC_FUNC0_END 227 */ ++/* #define MISC_FUNC1_START 228 */ ++ {OP_WR, MISC_REG_NIG_WOL_P1, 0x0}, ++/* #define MISC_FUNC1_END 229 */ ++/* #define MISC_FUNC2_START 230 */ ++ {OP_WR, MISC_REG_NIG_WOL_P0, 0x0}, ++/* #define MISC_FUNC2_END 231 */ ++/* #define MISC_FUNC3_START 232 */ ++ {OP_WR, MISC_REG_NIG_WOL_P1, 0x0}, ++/* #define MISC_FUNC3_END 233 */ ++/* #define MISC_FUNC4_START 234 */ ++ {OP_WR, MISC_REG_NIG_WOL_P0, 0x0}, ++/* #define MISC_FUNC4_END 235 */ ++/* #define MISC_FUNC5_START 236 */ ++ {OP_WR, MISC_REG_NIG_WOL_P1, 0x0}, ++/* #define MISC_FUNC5_END 237 */ ++/* #define MISC_FUNC6_START 238 */ ++ {OP_WR, MISC_REG_NIG_WOL_P0, 0x0}, ++/* #define MISC_FUNC6_END 239 */ ++/* #define MISC_FUNC7_START 240 */ ++ {OP_WR, MISC_REG_NIG_WOL_P1, 0x0}, ++/* #define MISC_FUNC7_END 241 */ ++/* #define NIG_COMMON_START 264 */ ++ {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1}, ++ {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1}, ++/* #define NIG_COMMON_END 265 */ ++/* #define NIG_PORT0_START 266 */ ++ {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000}, ++ {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28}, ++ {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0}, ++ {OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4}, ++ {OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1}, ++ {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0}, ++ {OP_WR, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7}, ++ {OP_WR, NIG_REG_LLH0_CLS_TYPE, 0x1}, ++ {OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30}, ++ {OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1}, ++ {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1}, ++/* #define NIG_PORT0_END 267 */ ++/* #define NIG_PORT1_START 268 */ ++ {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000}, ++ {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28}, ++ {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0}, ++ {OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4}, ++ {OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1}, ++ {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0}, ++ {OP_WR, NIG_REG_LLFC_EGRESS_SRC_ENABLE_1, 0x7}, ++ {OP_WR, NIG_REG_LLH1_CLS_TYPE, 0x1}, ++ {OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30}, ++ {OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1}, ++ {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1}, ++ {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1}, ++/* #define NIG_PORT1_END 269 */ ++/* #define UPB_COMMON_START 308 */ ++ {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20}, ++/* #define UPB_COMMON_END 309 */ ++/* #define CSDM_COMMON_START 330 */ ++ {OP_WR, CSDM_REG_CFC_RSP_START_ADDR, 0x211}, ++ {OP_WR, CSDM_REG_CMP_COUNTER_START_ADDR, 0x200}, ++ {OP_WR, CSDM_REG_Q_COUNTER_START_ADDR, 0x204}, ++ {OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff}, ++ {OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff}, ++ {OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff}, ++ {OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff}, ++ {OP_ZR, CSDM_REG_AGG_INT_EVENT_0, 0x2}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_2, 0x34}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_3, 0x35}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_4, 0x20}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_5, 0x21}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_6, 0x22}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_7, 0x23}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_8, 0x24}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_9, 0x25}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_10, 0x26}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_11, 0x27}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_12, 0x28}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_13, 0x29}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_14, 0x2a}, ++ {OP_WR, CSDM_REG_AGG_INT_EVENT_15, 0x2b}, ++ {OP_ZR, CSDM_REG_AGG_INT_EVENT_16, 0x56}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_6, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_7, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_8, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_9, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_10, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_11, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_12, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_13, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_14, 0x1}, ++ {OP_WR, CSDM_REG_AGG_INT_MODE_15, 0x1}, ++ {OP_ZR, CSDM_REG_AGG_INT_MODE_16, 0x10}, ++ {OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff}, ++ {OP_WR, CSDM_REG_ENABLE_IN2, 0x3f}, ++ {OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff}, ++ {OP_WR, CSDM_REG_ENABLE_OUT2, 0xf}, ++ {OP_RD, CSDM_REG_NUM_OF_Q0_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q1_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q3_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q4_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q5_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q6_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q7_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q8_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q9_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q10_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_Q11_CMD, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, ++ {OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, ++ {OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8}, ++ {OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1}, ++ {OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa}, ++/* #define CSDM_COMMON_END 331 */ ++/* #define USDM_COMMON_START 352 */ ++ {OP_WR, USDM_REG_CFC_RSP_START_ADDR, 0x411}, ++ {OP_WR, USDM_REG_CMP_COUNTER_START_ADDR, 0x400}, ++ {OP_WR, USDM_REG_Q_COUNTER_START_ADDR, 0x404}, ++ {OP_WR, USDM_REG_PCK_END_MSG_START_ADDR, 0x421}, ++ {OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff}, ++ {OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff}, ++ {OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff}, ++ {OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff}, ++ {OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46}, ++ {OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5}, ++ {OP_ZR, USDM_REG_AGG_INT_EVENT_2, 0x2}, ++ {OP_WR, USDM_REG_AGG_INT_EVENT_4, 0xa}, ++ {OP_WR, USDM_REG_AGG_INT_EVENT_5, 0xf0}, ++ {OP_ZR, USDM_REG_AGG_INT_EVENT_6, 0x1f}, ++ {OP_WR, USDM_REG_AGG_INT_T_5, 0x1}, ++ {OP_ZR, USDM_REG_AGG_INT_T_6, 0x3a}, ++ {OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1}, ++ {OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x3}, ++ {OP_WR, USDM_REG_AGG_INT_MODE_4, 0x1}, ++ {OP_WR, USDM_REG_AGG_INT_MODE_5, 0x1}, ++ {OP_ZR, USDM_REG_AGG_INT_MODE_6, 0x1a}, ++ {OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff}, ++ {OP_WR, USDM_REG_ENABLE_IN2, 0x3f}, ++ {OP_WR, USDM_REG_ENABLE_OUT1, 0x7ffffff}, ++ {OP_WR, USDM_REG_ENABLE_OUT2, 0xf}, ++ {OP_RD, USDM_REG_NUM_OF_Q0_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q1_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q2_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q3_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q4_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q5_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q6_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q7_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q8_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q9_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q10_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_Q11_CMD, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, ++ {OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, ++ {OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8}, ++ {OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1}, ++ {OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa}, ++/* #define USDM_COMMON_END 353 */ ++/* #define CCM_COMMON_START 374 */ ++ {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32}, ++ {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020}, ++ {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020}, ++ {OP_WR, CCM_REG_ERR_CCM_HDR, 0x8100000}, ++ {OP_WR, CCM_REG_ERR_EVNT_ID, 0x33}, ++ {OP_WR, CCM_REG_STORM_WEIGHT, 0x2}, ++ {OP_WR, CCM_REG_TSEM_WEIGHT, 0x0}, ++ {OP_WR, CCM_REG_XSEM_WEIGHT, 0x5}, ++ {OP_WR, CCM_REG_USEM_WEIGHT, 0x5}, ++ {OP_ZR, CCM_REG_PBF_WEIGHT, 0x2}, ++ {OP_WR, CCM_REG_CSDM_WEIGHT, 0x2}, ++ {OP_WR, CCM_REG_CQM_P_WEIGHT, 0x3}, ++ {OP_WR, CCM_REG_CQM_S_WEIGHT, 0x2}, ++ {OP_WR, CCM_REG_CCM_CQM_USE_Q, 0x1}, ++ {OP_WR, CCM_REG_CNT_AUX1_Q, 0x2}, ++ {OP_WR, CCM_REG_CNT_AUX2_Q, 0x2}, ++ {OP_WR, CCM_REG_INV_DONE_Q, 0x1}, ++ {OP_WR, CCM_REG_GR_ARB_TYPE, 0x1}, ++ {OP_WR, CCM_REG_GR_LD0_PR, 0x1}, ++ {OP_WR, CCM_REG_GR_LD1_PR, 0x2}, ++ {OP_WR, CCM_REG_CFC_INIT_CRD, 0x1}, ++ {OP_WR, CCM_REG_CQM_INIT_CRD, 0x20}, ++ {OP_WR, CCM_REG_FIC0_INIT_CRD, 0x40}, ++ {OP_WR, CCM_REG_FIC1_INIT_CRD, 0x40}, ++ {OP_WR, CCM_REG_XX_INIT_CRD, 0x3}, ++ {OP_WR, CCM_REG_XX_MSG_NUM, 0x18}, ++ {OP_ZR, CCM_REG_XX_TABLE, 0x12}, ++ {OP_SW, CCM_REG_XX_DESCR_TABLE, 0x24027e}, ++ {OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1}, ++ {OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2}, ++ {OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8}, ++ {OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8}, ++ {OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4}, ++ {OP_WR, CCM_REG_CCM_REG0_SZ, 0x4}, ++ {OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_STORM_CCM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CQM_CCM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CSDM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_TSEM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_XSEM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_USEM_IFEN, 0x1}, ++ {OP_WR, CCM_REG_PBF_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CDU_AG_WR_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CDU_AG_RD_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1}, ++ {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1}, ++/* #define CCM_COMMON_END 375 */ ++/* #define CCM_FUNC0_START 380 */ ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x9}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0xa}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x7}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x7}, ++ {OP_WR, CCM_REG_PHYS_QNUM1_0, 0xc}, ++ {OP_WR, CCM_REG_PHYS_QNUM2_0, 0xb}, ++ {OP_WR, CCM_REG_PHYS_QNUM3_0, 0x7}, ++/* #define CCM_FUNC0_END 381 */ ++/* #define CCM_FUNC1_START 382 */ ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x29}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x27}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x27}, ++ {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x2c}, ++ {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x2b}, ++ {OP_WR, CCM_REG_PHYS_QNUM3_1, 0x27}, ++/* #define CCM_FUNC1_END 383 */ ++/* #define CCM_FUNC2_START 384 */ ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x19}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0x1a}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x17}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x17}, ++ {OP_WR, CCM_REG_PHYS_QNUM1_0, 0x1c}, ++ {OP_WR, CCM_REG_PHYS_QNUM2_0, 0x1b}, ++ {OP_WR, CCM_REG_PHYS_QNUM3_0, 0x17}, ++/* #define CCM_FUNC2_END 385 */ ++/* #define CCM_FUNC3_START 386 */ ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x39}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x3a}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x37}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x37}, ++ {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x3c}, ++ {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x3b}, ++ {OP_WR, CCM_REG_PHYS_QNUM3_1, 0x37}, ++/* #define CCM_FUNC3_END 387 */ ++/* #define CCM_FUNC4_START 388 */ ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x49}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0x4a}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x47}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x47}, ++ {OP_WR, CCM_REG_PHYS_QNUM1_0, 0x4c}, ++ {OP_WR, CCM_REG_PHYS_QNUM2_0, 0x4b}, ++ {OP_WR, CCM_REG_PHYS_QNUM3_0, 0x47}, ++/* #define CCM_FUNC4_END 389 */ ++/* #define CCM_FUNC5_START 390 */ ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x69}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x6a}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x67}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x67}, ++ {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x6c}, ++ {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x6b}, ++ {OP_WR, CCM_REG_PHYS_QNUM3_1, 0x67}, ++/* #define CCM_FUNC5_END 391 */ ++/* #define CCM_FUNC6_START 392 */ ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x59}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0x5a}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x57}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x57}, ++ {OP_WR, CCM_REG_PHYS_QNUM1_0, 0x5c}, ++ {OP_WR, CCM_REG_PHYS_QNUM2_0, 0x5b}, ++ {OP_WR, CCM_REG_PHYS_QNUM3_0, 0x57}, ++/* #define CCM_FUNC6_END 393 */ ++/* #define CCM_FUNC7_START 394 */ ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x79}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x7a}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x77}, ++ {OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x77}, ++ {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x7c}, ++ {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x7b}, ++ {OP_WR, CCM_REG_PHYS_QNUM3_1, 0x77}, ++/* #define CCM_FUNC7_END 395 */ ++/* #define UCM_COMMON_START 396 */ ++ {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32}, ++ {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020}, ++ {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020}, ++ {OP_WR, UCM_REG_TM_UCM_HDR, 0x30}, ++ {OP_WR, UCM_REG_ERR_UCM_HDR, 0x8100000}, ++ {OP_WR, UCM_REG_ERR_EVNT_ID, 0x33}, ++ {OP_WR, UCM_REG_EXPR_EVNT_ID, 0x30}, ++ {OP_WR, UCM_REG_STOP_EVNT_ID, 0x31}, ++ {OP_WR, UCM_REG_STORM_WEIGHT, 0x2}, ++ {OP_WR, UCM_REG_TSEM_WEIGHT, 0x4}, ++ {OP_WR, UCM_REG_CSEM_WEIGHT, 0x0}, ++ {OP_WR, UCM_REG_XSEM_WEIGHT, 0x2}, ++ {OP_WR, UCM_REG_DORQ_WEIGHT, 0x2}, ++ {OP_WR, UCM_REG_CP_WEIGHT, 0x0}, ++ {OP_WR, UCM_REG_USDM_WEIGHT, 0x2}, ++ {OP_WR, UCM_REG_UQM_P_WEIGHT, 0x7}, ++ {OP_WR, UCM_REG_UQM_S_WEIGHT, 0x2}, ++ {OP_WR, UCM_REG_TM_WEIGHT, 0x2}, ++ {OP_WR, UCM_REG_UCM_UQM_USE_Q, 0x1}, ++ {OP_WR, UCM_REG_INV_CFLG_Q, 0x1}, ++ {OP_WR, UCM_REG_GR_ARB_TYPE, 0x1}, ++ {OP_WR, UCM_REG_GR_LD0_PR, 0x1}, ++ {OP_WR, UCM_REG_GR_LD1_PR, 0x2}, ++ {OP_WR, UCM_REG_CFC_INIT_CRD, 0x1}, ++ {OP_WR, UCM_REG_FIC0_INIT_CRD, 0x40}, ++ {OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40}, ++ {OP_WR, UCM_REG_TM_INIT_CRD, 0x4}, ++ {OP_WR, UCM_REG_UQM_INIT_CRD, 0x20}, ++ {OP_WR, UCM_REG_XX_INIT_CRD, 0xe}, ++ {OP_WR, UCM_REG_XX_MSG_NUM, 0x1b}, ++ {OP_ZR, UCM_REG_XX_TABLE, 0x12}, ++ {OP_SW, UCM_REG_XX_DESCR_TABLE, 0x1b02a2}, ++ {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0xc}, ++ {OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7}, ++ {OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf}, ++ {OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10}, ++ {OP_WR, UCM_REG_N_SM_CTX_LD_4, 0xb}, ++ {OP_ZR, UCM_REG_N_SM_CTX_LD_5, 0x3}, ++ {OP_WR, UCM_REG_UCM_REG0_SZ, 0x3}, ++ {OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1}, ++ {OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1}, ++ {OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_STORM_UCM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_UQM_UCM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_USDM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_TM_UCM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_UCM_TM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_TSEM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_CSEM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_XSEM_IFEN, 0x1}, ++ {OP_WR, UCM_REG_DORQ_IFEN, 0x1}, ++ {OP_WR, UCM_REG_CDU_AG_WR_IFEN, 0x1}, ++ {OP_WR, UCM_REG_CDU_AG_RD_IFEN, 0x1}, ++ {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1}, ++ {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1}, ++ {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1}, ++/* #define UCM_COMMON_END 397 */ ++/* #define UCM_FUNC0_START 402 */ ++ {OP_WR, UCM_REG_PHYS_QNUM0_0, 0xf}, ++ {OP_WR, UCM_REG_PHYS_QNUM1_0, 0xe}, ++ {OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0}, ++ {OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0}, ++/* #define UCM_FUNC0_END 403 */ ++/* #define UCM_FUNC1_START 404 */ ++ {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x2f}, ++ {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x2e}, ++ {OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0}, ++ {OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0}, ++/* #define UCM_FUNC1_END 405 */ ++/* #define UCM_FUNC2_START 406 */ ++ {OP_WR, UCM_REG_PHYS_QNUM0_0, 0x1f}, ++ {OP_WR, UCM_REG_PHYS_QNUM1_0, 0x1e}, ++ {OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0}, ++ {OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0}, ++/* #define UCM_FUNC2_END 407 */ ++/* #define UCM_FUNC3_START 408 */ ++ {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x3f}, ++ {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x3e}, ++ {OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0}, ++ {OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0}, ++/* #define UCM_FUNC3_END 409 */ ++/* #define UCM_FUNC4_START 410 */ ++ {OP_WR, UCM_REG_PHYS_QNUM0_0, 0x4f}, ++ {OP_WR, UCM_REG_PHYS_QNUM1_0, 0x4e}, ++ {OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0}, ++ {OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0}, ++/* #define UCM_FUNC4_END 411 */ ++/* #define UCM_FUNC5_START 412 */ ++ {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x6f}, ++ {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x6e}, ++ {OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0}, ++ {OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0}, ++/* #define UCM_FUNC5_END 413 */ ++/* #define UCM_FUNC6_START 414 */ ++ {OP_WR, UCM_REG_PHYS_QNUM0_0, 0x5f}, ++ {OP_WR, UCM_REG_PHYS_QNUM1_0, 0x5e}, ++ {OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0}, ++ {OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0}, ++/* #define UCM_FUNC6_END 415 */ ++/* #define UCM_FUNC7_START 416 */ ++ {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x7f}, ++ {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x7e}, ++ {OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0}, ++ {OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0}, ++/* #define UCM_FUNC7_END 417 */ ++/* #define USEM_COMMON_START 418 */ ++ {OP_ZP, USEM_REG_INT_TABLE, 0xe10000}, ++ {OP_WR_64, USEM_REG_INT_TABLE + 0x3d8, 0x502bd}, ++ {OP_ZP, USEM_REG_PRAM, 0x2eca0000}, ++ {OP_ZP, USEM_REG_PRAM + 0x8000, 0x311a0bb3}, ++ {OP_ZP, USEM_REG_PRAM + 0x10000, 0x368b17fa}, ++ {OP_ZP, USEM_REG_PRAM + 0x18000, 0x39c6259d}, ++ {OP_ZP, USEM_REG_PRAM + 0x20000, 0x13d5340f}, ++ {OP_WR_64, USEM_REG_PRAM + 0x23070, 0x39f202bf}, ++ {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0}, ++ {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0}, ++ {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0}, ++ {OP_RD, USEM_REG_MSG_NUM_FOC1, 0x0}, ++ {OP_RD, USEM_REG_MSG_NUM_FOC2, 0x0}, ++ {OP_RD, USEM_REG_MSG_NUM_FOC3, 0x0}, ++ {OP_WR, USEM_REG_ARB_ELEMENT0, 0x1}, ++ {OP_WR, USEM_REG_ARB_ELEMENT1, 0x2}, ++ {OP_WR, USEM_REG_ARB_ELEMENT2, 0x3}, ++ {OP_WR, USEM_REG_ARB_ELEMENT3, 0x0}, ++ {OP_WR, USEM_REG_ARB_ELEMENT4, 0x4}, ++ {OP_WR, USEM_REG_ARB_CYCLE_SIZE, 0x1}, ++ {OP_WR, USEM_REG_TS_0_AS, 0x0}, ++ {OP_WR, USEM_REG_TS_1_AS, 0x1}, ++ {OP_WR, USEM_REG_TS_2_AS, 0x4}, ++ {OP_WR, USEM_REG_TS_3_AS, 0x0}, ++ {OP_WR, USEM_REG_TS_4_AS, 0x1}, ++ {OP_WR, USEM_REG_TS_5_AS, 0x3}, ++ {OP_WR, USEM_REG_TS_6_AS, 0x0}, ++ {OP_WR, USEM_REG_TS_7_AS, 0x1}, ++ {OP_WR, USEM_REG_TS_8_AS, 0x4}, ++ {OP_WR, USEM_REG_TS_9_AS, 0x0}, ++ {OP_WR, USEM_REG_TS_10_AS, 0x1}, ++ {OP_WR, USEM_REG_TS_11_AS, 0x3}, ++ {OP_WR, USEM_REG_TS_12_AS, 0x0}, ++ {OP_WR, USEM_REG_TS_13_AS, 0x1}, ++ {OP_WR, USEM_REG_TS_14_AS, 0x4}, ++ {OP_WR, USEM_REG_TS_15_AS, 0x0}, ++ {OP_WR, USEM_REG_TS_16_AS, 0x4}, ++ {OP_WR, USEM_REG_TS_17_AS, 0x3}, ++ {OP_ZR, USEM_REG_TS_18_AS, 0x2}, ++ {OP_WR, USEM_REG_ENABLE_IN, 0x3fff}, ++ {OP_WR, USEM_REG_ENABLE_OUT, 0x3ff}, ++ {OP_WR, USEM_REG_FIC0_DISABLE, 0x0}, ++ {OP_WR, USEM_REG_FIC1_DISABLE, 0x0}, ++ {OP_WR, USEM_REG_PAS_DISABLE, 0x0}, ++ {OP_WR, USEM_REG_THREADS_LIST, 0xffff}, ++ {OP_ZR, USEM_REG_PASSIVE_BUFFER, 0x800}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x18bc0, 0x1}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x18000, 0x1a}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20}, ++ {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, ++ {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18300, 0x138}, ++ {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18300, 0x1388}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, ++ {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500}, ++ {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4}, ++ {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40}, ++ {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x11480, 0x0}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x11480, 0x1}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x2000, 0x102}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x8020, 0xc8}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x8000, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x3da8, 0x4}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x3d80, 0x9}, ++ {OP_SW, USEM_REG_FAST_MEMORY + 0x3d80 + 0x24, 0x102c1}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x3d00, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x400}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x4000, 0x2}, ++ {OP_SW, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x102c2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x4000 + 0xc, 0x3}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x40d8, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x6b68, 0x2}, ++ {OP_SW, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x202c3}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x6b10, 0x2}, ++ {OP_SW, USEM_REG_FAST_MEMORY + 0x74c0, 0x202c5}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0xda40, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0xe000, 0x800}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, ++ {OP_SW, USEM_REG_FAST_MEMORY + 0x10c00, 0x1002c7}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0}, ++ {OP_SW, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002d7}, ++/* #define USEM_COMMON_END 419 */ ++/* #define USEM_PORT0_START 420 */ ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x2450, 0xb4}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x2ad0, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x1000, 0x1a0}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x3db8, 0x0}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5100, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5200, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5300, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5400, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5500, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5600, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5700, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5800, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5900, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5a00, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5b00, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5c00, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5d00, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5e00, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5f00, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x6b78, 0x52}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x6e08, 0xc}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0xda88, 0x2}, ++/* #define USEM_PORT0_END 421 */ ++/* #define USEM_PORT1_START 422 */ ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x2720, 0xb4}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x2ad8, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x1680, 0x1a0}, ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x3dbc, 0x0}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5080, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5180, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5280, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5380, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5480, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5580, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5680, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5780, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5880, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5980, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5a80, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5b80, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5c80, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5d80, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5e80, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x5f80, 0x20}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x6e38, 0xc}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0xda90, 0x2}, ++/* #define USEM_PORT1_END 423 */ ++/* #define USEM_FUNC0_START 424 */ ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x2a30, 0x0}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x4018, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0xd000, 0x6}, ++/* #define USEM_FUNC0_END 425 */ ++/* #define USEM_FUNC1_START 426 */ ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x2a34, 0x0}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x4028, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0xd018, 0x6}, ++/* #define USEM_FUNC1_END 427 */ ++/* #define USEM_FUNC2_START 428 */ ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x2a38, 0x0}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x4038, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0xd030, 0x6}, ++/* #define USEM_FUNC2_END 429 */ ++/* #define USEM_FUNC3_START 430 */ ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x2a3c, 0x0}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x4048, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0xd048, 0x6}, ++/* #define USEM_FUNC3_END 431 */ ++/* #define USEM_FUNC4_START 432 */ ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x2a40, 0x0}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x4058, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0xd060, 0x6}, ++/* #define USEM_FUNC4_END 433 */ ++/* #define USEM_FUNC5_START 434 */ ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x2a44, 0x0}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x4068, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0xd078, 0x6}, ++/* #define USEM_FUNC5_END 435 */ ++/* #define USEM_FUNC6_START 436 */ ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x2a48, 0x0}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x4078, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0xd090, 0x6}, ++/* #define USEM_FUNC6_END 437 */ ++/* #define USEM_FUNC7_START 438 */ ++ {OP_WR, USEM_REG_FAST_MEMORY + 0x2a4c, 0x0}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0x4088, 0x2}, ++ {OP_ZR, USEM_REG_FAST_MEMORY + 0xd0a8, 0x6}, ++/* #define USEM_FUNC7_END 439 */ ++/* #define CSEM_COMMON_START 440 */ ++ {OP_ZP, CSEM_REG_INT_TABLE, 0x930000}, ++ {OP_WR_64, CSEM_REG_INT_TABLE + 0x380, 0x1002e7}, ++ {OP_ZP, CSEM_REG_PRAM, 0x2adf0000}, ++ {OP_ZP, CSEM_REG_PRAM + 0x8000, 0x2e050ab8}, ++ {OP_WR_64, CSEM_REG_PRAM + 0xe4a0, 0x61d202e9}, ++ {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0}, ++ {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0}, ++ {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0}, ++ {OP_RD, CSEM_REG_MSG_NUM_FOC1, 0x0}, ++ {OP_RD, CSEM_REG_MSG_NUM_FOC2, 0x0}, ++ {OP_RD, CSEM_REG_MSG_NUM_FOC3, 0x0}, ++ {OP_WR, CSEM_REG_ARB_ELEMENT0, 0x1}, ++ {OP_WR, CSEM_REG_ARB_ELEMENT1, 0x2}, ++ {OP_WR, CSEM_REG_ARB_ELEMENT2, 0x3}, ++ {OP_WR, CSEM_REG_ARB_ELEMENT3, 0x0}, ++ {OP_WR, CSEM_REG_ARB_ELEMENT4, 0x4}, ++ {OP_WR, CSEM_REG_ARB_CYCLE_SIZE, 0x1}, ++ {OP_WR, CSEM_REG_TS_0_AS, 0x0}, ++ {OP_WR, CSEM_REG_TS_1_AS, 0x1}, ++ {OP_WR, CSEM_REG_TS_2_AS, 0x4}, ++ {OP_WR, CSEM_REG_TS_3_AS, 0x0}, ++ {OP_WR, CSEM_REG_TS_4_AS, 0x1}, ++ {OP_WR, CSEM_REG_TS_5_AS, 0x3}, ++ {OP_WR, CSEM_REG_TS_6_AS, 0x0}, ++ {OP_WR, CSEM_REG_TS_7_AS, 0x1}, ++ {OP_WR, CSEM_REG_TS_8_AS, 0x4}, ++ {OP_WR, CSEM_REG_TS_9_AS, 0x0}, ++ {OP_WR, CSEM_REG_TS_10_AS, 0x1}, ++ {OP_WR, CSEM_REG_TS_11_AS, 0x3}, ++ {OP_WR, CSEM_REG_TS_12_AS, 0x0}, ++ {OP_WR, CSEM_REG_TS_13_AS, 0x1}, ++ {OP_WR, CSEM_REG_TS_14_AS, 0x4}, ++ {OP_WR, CSEM_REG_TS_15_AS, 0x0}, ++ {OP_WR, CSEM_REG_TS_16_AS, 0x4}, ++ {OP_WR, CSEM_REG_TS_17_AS, 0x3}, ++ {OP_ZR, CSEM_REG_TS_18_AS, 0x2}, ++ {OP_WR, CSEM_REG_ENABLE_IN, 0x3fff}, ++ {OP_WR, CSEM_REG_ENABLE_OUT, 0x3ff}, ++ {OP_WR, CSEM_REG_FIC0_DISABLE, 0x0}, ++ {OP_WR, CSEM_REG_FIC1_DISABLE, 0x0}, ++ {OP_WR, CSEM_REG_PAS_DISABLE, 0x0}, ++ {OP_WR, CSEM_REG_THREADS_LIST, 0xffff}, ++ {OP_ZR, CSEM_REG_PASSIVE_BUFFER, 0x800}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x18bc0, 0x1}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x18000, 0x10}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x18040, 0x12}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x11480, 0x1}, ++ {OP_WR_EMUL, CSEM_REG_FAST_MEMORY + 0x11480, 0x0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1000, 0x42}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x7020, 0xc8}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x7000, 0x2}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x4070, 0x80}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x5280, 0x4}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6700, 0x100}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x9000, 0x400}, ++ {OP_SW, CSEM_REG_FAST_MEMORY + 0x6b08, 0x2002eb}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff}, ++ {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c00, 0x10030b}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0}, ++ {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c40, 0x10031b}, ++/* #define CSEM_COMMON_END 441 */ ++/* #define CSEM_PORT0_START 442 */ ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8100, 0xa0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8600, 0x40}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8c00, 0x3c}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0xb000, 0x200}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8800, 0x80}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8de0, 0x3c}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x4040, 0x6}, ++/* #define CSEM_PORT0_END 443 */ ++/* #define CSEM_PORT1_START 444 */ ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8380, 0xa0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8700, 0x40}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8cf0, 0x3c}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0xb800, 0x200}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8a00, 0x80}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8ed0, 0x3c}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x4058, 0x6}, ++/* #define CSEM_PORT1_END 445 */ ++/* #define CSEM_FUNC0_START 446 */ ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8000, 0x8}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x1148, 0x0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3300, 0x2}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6040, 0x30}, ++/* #define CSEM_FUNC0_END 447 */ ++/* #define CSEM_FUNC1_START 448 */ ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8020, 0x8}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x114c, 0x0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3308, 0x2}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6100, 0x30}, ++/* #define CSEM_FUNC1_END 449 */ ++/* #define CSEM_FUNC2_START 450 */ ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8040, 0x8}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x1150, 0x0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3310, 0x2}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x61c0, 0x30}, ++/* #define CSEM_FUNC2_END 451 */ ++/* #define CSEM_FUNC3_START 452 */ ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8060, 0x8}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x1154, 0x0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3318, 0x2}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6280, 0x30}, ++/* #define CSEM_FUNC3_END 453 */ ++/* #define CSEM_FUNC4_START 454 */ ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8080, 0x8}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x1158, 0x0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3320, 0x2}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6340, 0x30}, ++/* #define CSEM_FUNC4_END 455 */ ++/* #define CSEM_FUNC5_START 456 */ ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x80a0, 0x8}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x115c, 0x0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3328, 0x2}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6400, 0x30}, ++/* #define CSEM_FUNC5_END 457 */ ++/* #define CSEM_FUNC6_START 458 */ ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x80c0, 0x8}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x1160, 0x0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3330, 0x2}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x64c0, 0x30}, ++/* #define CSEM_FUNC6_END 459 */ ++/* #define CSEM_FUNC7_START 460 */ ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x80e0, 0x8}, ++ {OP_WR, CSEM_REG_FAST_MEMORY + 0x1164, 0x0}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3338, 0x2}, ++ {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6580, 0x30}, ++/* #define CSEM_FUNC7_END 461 */ ++/* #define XPB_COMMON_START 462 */ ++ {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x28}, ++/* #define XPB_COMMON_END 463 */ ++/* #define DQ_COMMON_START 484 */ ++ {OP_WR, DORQ_REG_MODE_ACT, 0x2}, ++ {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3}, ++ {OP_WR, DORQ_REG_OUTST_REQ, 0x4}, ++ {OP_WR, DORQ_REG_DPM_CID_ADDR, 0x8}, ++ {OP_WR, DORQ_REG_RSP_INIT_CRD, 0x2}, ++ {OP_WR, DORQ_REG_NORM_CMHEAD_TX, 0x90}, ++ {OP_WR, DORQ_REG_CMHEAD_RX, 0x90}, ++ {OP_WR, DORQ_REG_SHRT_CMHEAD, 0x800090}, ++ {OP_WR, DORQ_REG_ERR_CMHEAD, 0x8140000}, ++ {OP_WR, DORQ_REG_AGG_CMD0, 0x8a}, ++ {OP_WR, DORQ_REG_AGG_CMD1, 0x80}, ++ {OP_WR, DORQ_REG_AGG_CMD2, 0x81}, ++ {OP_WR, DORQ_REG_AGG_CMD3, 0x80}, ++ {OP_WR, DORQ_REG_SHRT_ACT_CNT, 0x6}, ++ {OP_WR, DORQ_REG_DQ_FIFO_FULL_TH, 0x7d0}, ++ {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c}, ++ {OP_WR, DORQ_REG_REGN, 0x7c1004}, ++ {OP_WR, DORQ_REG_IF_EN, 0xf}, ++/* #define DQ_COMMON_END 485 */ ++/* #define TIMERS_COMMON_START 506 */ ++ {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2}, ++ {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c}, ++ {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1}, ++ {OP_WR, TM_REG_CFC_CLD_CRDCNT_VAL, 0x1}, ++ {OP_WR, TM_REG_CLOUT_CRDCNT0_VAL, 0x1}, ++ {OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1}, ++ {OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1}, ++ {OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1}, ++ {OP_WR, TM_REG_PCIARB_CRDCNT_VAL, 0x2}, ++ {OP_WR_ASIC, TM_REG_TIMER_TICK_SIZE, 0x3d090}, ++ {OP_WR_EMUL, TM_REG_TIMER_TICK_SIZE, 0x9c}, ++ {OP_WR_FPGA, TM_REG_TIMER_TICK_SIZE, 0x9c4}, ++ {OP_WR, TM_REG_CL0_CONT_REGION, 0x8}, ++ {OP_WR, TM_REG_CL1_CONT_REGION, 0xc}, ++ {OP_WR, TM_REG_CL2_CONT_REGION, 0x10}, ++ {OP_WR, TM_REG_TM_CONTEXT_REGION, 0x20}, ++ {OP_WR, TM_REG_EN_TIMERS, 0x1}, ++ {OP_WR, TM_REG_EN_REAL_TIME_CNT, 0x1}, ++ {OP_WR, TM_REG_EN_CL0_INPUT, 0x1}, ++ {OP_WR, TM_REG_EN_CL1_INPUT, 0x1}, ++ {OP_WR, TM_REG_EN_CL2_INPUT, 0x1}, ++/* #define TIMERS_COMMON_END 507 */ ++/* #define TIMERS_PORT0_START 508 */ ++ {OP_WR, TM_REG_LIN0_LOGIC_ADDR, 0x0}, ++ {OP_WR, TM_REG_LIN0_PHY_ADDR_VALID, 0x0}, ++ {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2}, ++/* #define TIMERS_PORT0_END 509 */ ++/* #define TIMERS_PORT1_START 510 */ ++ {OP_WR, TM_REG_LIN1_LOGIC_ADDR, 0x0}, ++ {OP_WR, TM_REG_LIN1_PHY_ADDR_VALID, 0x0}, ++ {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2}, ++/* #define TIMERS_PORT1_END 511 */ ++/* #define XSDM_COMMON_START 528 */ ++ {OP_WR, XSDM_REG_CFC_RSP_START_ADDR, 0x424}, ++ {OP_WR, XSDM_REG_CMP_COUNTER_START_ADDR, 0x410}, ++ {OP_WR, XSDM_REG_Q_COUNTER_START_ADDR, 0x414}, ++ {OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff}, ++ {OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff}, ++ {OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff}, ++ {OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_2, 0x34}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_3, 0x35}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_4, 0x23}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_5, 0x24}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_6, 0x25}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_7, 0x26}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_8, 0x27}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_9, 0x29}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_10, 0x2a}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_11, 0x2b}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_12, 0x2c}, ++ {OP_WR, XSDM_REG_AGG_INT_EVENT_13, 0x2d}, ++ {OP_ZR, XSDM_REG_AGG_INT_EVENT_14, 0x52}, ++ {OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1}, ++ {OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f}, ++ {OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff}, ++ {OP_WR, XSDM_REG_ENABLE_IN2, 0x3f}, ++ {OP_WR, XSDM_REG_ENABLE_OUT1, 0x7ffffff}, ++ {OP_WR, XSDM_REG_ENABLE_OUT2, 0xf}, ++ {OP_RD, XSDM_REG_NUM_OF_Q0_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q1_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q3_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q4_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q5_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q6_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q7_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q8_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q9_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q10_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_Q11_CMD, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, ++ {OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, ++ {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8}, ++ {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1}, ++ {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa}, ++/* #define XSDM_COMMON_END 529 */ ++/* #define QM_COMMON_START 550 */ ++ {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6}, ++ {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5}, ++ {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa}, ++ {OP_WR, QM_REG_ACTCTRINITVAL_3, 0x5}, ++ {OP_WR, QM_REG_PCIREQAT, 0x2}, ++ {OP_WR, QM_REG_CMINITCRD_0, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_1, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_2, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_3, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_4, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_5, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_6, 0x4}, ++ {OP_WR, QM_REG_CMINITCRD_7, 0x4}, ++ {OP_WR, QM_REG_OUTLDREQ, 0x4}, ++ {OP_WR, QM_REG_CTXREG_0, 0x7c}, ++ {OP_WR, QM_REG_CTXREG_1, 0x3d}, ++ {OP_WR, QM_REG_CTXREG_2, 0x3f}, ++ {OP_WR, QM_REG_CTXREG_3, 0x9c}, ++ {OP_WR, QM_REG_ENSEC, 0x7}, ++ {OP_ZR, QM_REG_QVOQIDX_0, 0x5}, ++ {OP_WR, QM_REG_WRRWEIGHTS_0, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_5, 0x0}, ++ {OP_WR, QM_REG_QVOQIDX_6, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_7, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_8, 0x2}, ++ {OP_WR, QM_REG_WRRWEIGHTS_1, 0x8012004}, ++ {OP_WR, QM_REG_QVOQIDX_9, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_10, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_11, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_12, 0x5}, ++ {OP_WR, QM_REG_WRRWEIGHTS_2, 0x20081001}, ++ {OP_WR, QM_REG_QVOQIDX_13, 0x8}, ++ {OP_WR, QM_REG_QVOQIDX_14, 0x6}, ++ {OP_WR, QM_REG_QVOQIDX_15, 0x7}, ++ {OP_WR, QM_REG_QVOQIDX_16, 0x0}, ++ {OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120}, ++ {OP_ZR, QM_REG_QVOQIDX_17, 0x4}, ++ {OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_21, 0x0}, ++ {OP_WR, QM_REG_QVOQIDX_22, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_23, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_24, 0x2}, ++ {OP_WR, QM_REG_WRRWEIGHTS_5, 0x8012004}, ++ {OP_WR, QM_REG_QVOQIDX_25, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_26, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_27, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_28, 0x5}, ++ {OP_WR, QM_REG_WRRWEIGHTS_6, 0x20081001}, ++ {OP_WR, QM_REG_QVOQIDX_29, 0x8}, ++ {OP_WR, QM_REG_QVOQIDX_30, 0x6}, ++ {OP_WR, QM_REG_QVOQIDX_31, 0x7}, ++ {OP_WR, QM_REG_QVOQIDX_32, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_7, 0x1010120}, ++ {OP_WR, QM_REG_QVOQIDX_33, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_34, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_35, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_36, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_8, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_37, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_38, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_39, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_40, 0x2}, ++ {OP_WR, QM_REG_WRRWEIGHTS_9, 0x8012004}, ++ {OP_WR, QM_REG_QVOQIDX_41, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_42, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_43, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_44, 0x5}, ++ {OP_WR, QM_REG_WRRWEIGHTS_10, 0x20081001}, ++ {OP_WR, QM_REG_QVOQIDX_45, 0x8}, ++ {OP_WR, QM_REG_QVOQIDX_46, 0x6}, ++ {OP_WR, QM_REG_QVOQIDX_47, 0x7}, ++ {OP_WR, QM_REG_QVOQIDX_48, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_11, 0x1010120}, ++ {OP_WR, QM_REG_QVOQIDX_49, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_50, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_51, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_52, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_53, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_54, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_55, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_56, 0x2}, ++ {OP_WR, QM_REG_WRRWEIGHTS_13, 0x8012004}, ++ {OP_WR, QM_REG_QVOQIDX_57, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_58, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_59, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_60, 0x5}, ++ {OP_WR, QM_REG_WRRWEIGHTS_14, 0x20081001}, ++ {OP_WR, QM_REG_QVOQIDX_61, 0x8}, ++ {OP_WR, QM_REG_QVOQIDX_62, 0x6}, ++ {OP_WR, QM_REG_QVOQIDX_63, 0x7}, ++ {OP_WR, QM_REG_QVOQIDX_64, 0x0}, ++ {OP_WR, QM_REG_WRRWEIGHTS_15, 0x1010120}, ++ {OP_ZR, QM_REG_QVOQIDX_65, 0x4}, ++ {OP_WR, QM_REG_WRRWEIGHTS_16, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_69, 0x0}, ++ {OP_WR, QM_REG_QVOQIDX_70, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_71, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_72, 0x2}, ++ {OP_WR, QM_REG_WRRWEIGHTS_17, 0x8012004}, ++ {OP_WR, QM_REG_QVOQIDX_73, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_74, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_75, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_76, 0x5}, ++ {OP_WR, QM_REG_WRRWEIGHTS_18, 0x20081001}, ++ {OP_WR, QM_REG_QVOQIDX_77, 0x8}, ++ {OP_WR, QM_REG_QVOQIDX_78, 0x6}, ++ {OP_WR, QM_REG_QVOQIDX_79, 0x7}, ++ {OP_WR, QM_REG_QVOQIDX_80, 0x0}, ++ {OP_WR, QM_REG_WRRWEIGHTS_19, 0x1010120}, ++ {OP_ZR, QM_REG_QVOQIDX_81, 0x4}, ++ {OP_WR, QM_REG_WRRWEIGHTS_20, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_85, 0x0}, ++ {OP_WR, QM_REG_QVOQIDX_86, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_87, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_88, 0x2}, ++ {OP_WR, QM_REG_WRRWEIGHTS_21, 0x8012004}, ++ {OP_WR, QM_REG_QVOQIDX_89, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_90, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_91, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_92, 0x5}, ++ {OP_WR, QM_REG_WRRWEIGHTS_22, 0x20081001}, ++ {OP_WR, QM_REG_QVOQIDX_93, 0x8}, ++ {OP_WR, QM_REG_QVOQIDX_94, 0x6}, ++ {OP_WR, QM_REG_QVOQIDX_95, 0x7}, ++ {OP_WR, QM_REG_QVOQIDX_96, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_23, 0x1010120}, ++ {OP_WR, QM_REG_QVOQIDX_97, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_98, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_99, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_100, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_24, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_101, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_102, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_103, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_104, 0x2}, ++ {OP_WR, QM_REG_WRRWEIGHTS_25, 0x8012004}, ++ {OP_WR, QM_REG_QVOQIDX_105, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_106, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_107, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_108, 0x5}, ++ {OP_WR, QM_REG_WRRWEIGHTS_26, 0x20081001}, ++ {OP_WR, QM_REG_QVOQIDX_109, 0x8}, ++ {OP_WR, QM_REG_QVOQIDX_110, 0x6}, ++ {OP_WR, QM_REG_QVOQIDX_111, 0x7}, ++ {OP_WR, QM_REG_QVOQIDX_112, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_27, 0x1010120}, ++ {OP_WR, QM_REG_QVOQIDX_113, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_114, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_115, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_116, 0x1}, ++ {OP_WR, QM_REG_WRRWEIGHTS_28, 0x1010101}, ++ {OP_WR, QM_REG_QVOQIDX_117, 0x1}, ++ {OP_WR, QM_REG_QVOQIDX_118, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_119, 0x4}, ++ {OP_WR, QM_REG_QVOQIDX_120, 0x2}, ++ {OP_WR, QM_REG_WRRWEIGHTS_29, 0x8012004}, ++ {OP_WR, QM_REG_QVOQIDX_121, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_122, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_123, 0x5}, ++ {OP_WR, QM_REG_QVOQIDX_124, 0x5}, ++ {OP_WR, QM_REG_WRRWEIGHTS_30, 0x20081001}, ++ {OP_WR, QM_REG_QVOQIDX_125, 0x8}, ++ {OP_WR, QM_REG_QVOQIDX_126, 0x6}, ++ {OP_WR, QM_REG_QVOQIDX_127, 0x7}, ++ {OP_WR, QM_REG_WRRWEIGHTS_31, 0x1010120}, ++ {OP_WR, QM_REG_VOQQMASK_0_LSB, 0x3f003f}, ++ {OP_WR, QM_REG_VOQQMASK_0_MSB, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_0_LSB_EXT_A, 0x3f003f}, ++ {OP_WR, QM_REG_VOQQMASK_0_MSB_EXT_A, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_1_LSB, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_1_MSB, 0x3f003f}, ++ {OP_WR, QM_REG_VOQQMASK_1_LSB_EXT_A, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_1_MSB_EXT_A, 0x3f003f}, ++ {OP_WR, QM_REG_VOQQMASK_2_LSB, 0x1000100}, ++ {OP_WR, QM_REG_VOQQMASK_2_MSB, 0x1000100}, ++ {OP_WR, QM_REG_VOQQMASK_2_LSB_EXT_A, 0x1000100}, ++ {OP_WR, QM_REG_VOQQMASK_2_MSB_EXT_A, 0x1000100}, ++ {OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2}, ++ {OP_WR, QM_REG_VOQQMASK_3_LSB_EXT_A, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_3_MSB_EXT_A, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_4_LSB, 0xc000c0}, ++ {OP_WR, QM_REG_VOQQMASK_4_MSB, 0xc000c0}, ++ {OP_WR, QM_REG_VOQQMASK_4_LSB_EXT_A, 0xc000c0}, ++ {OP_WR, QM_REG_VOQQMASK_4_MSB_EXT_A, 0xc000c0}, ++ {OP_WR, QM_REG_VOQQMASK_5_LSB, 0x1e001e00}, ++ {OP_WR, QM_REG_VOQQMASK_5_MSB, 0x1e001e00}, ++ {OP_WR, QM_REG_VOQQMASK_5_LSB_EXT_A, 0x1e001e00}, ++ {OP_WR, QM_REG_VOQQMASK_5_MSB_EXT_A, 0x1e001e00}, ++ {OP_WR, QM_REG_VOQQMASK_6_LSB, 0x40004000}, ++ {OP_WR, QM_REG_VOQQMASK_6_MSB, 0x40004000}, ++ {OP_WR, QM_REG_VOQQMASK_6_LSB_EXT_A, 0x40004000}, ++ {OP_WR, QM_REG_VOQQMASK_6_MSB_EXT_A, 0x40004000}, ++ {OP_WR, QM_REG_VOQQMASK_7_LSB, 0x80008000}, ++ {OP_WR, QM_REG_VOQQMASK_7_MSB, 0x80008000}, ++ {OP_WR, QM_REG_VOQQMASK_7_LSB_EXT_A, 0x80008000}, ++ {OP_WR, QM_REG_VOQQMASK_7_MSB_EXT_A, 0x80008000}, ++ {OP_WR, QM_REG_VOQQMASK_8_LSB, 0x20002000}, ++ {OP_WR, QM_REG_VOQQMASK_8_MSB, 0x20002000}, ++ {OP_WR, QM_REG_VOQQMASK_8_LSB_EXT_A, 0x20002000}, ++ {OP_WR, QM_REG_VOQQMASK_8_MSB_EXT_A, 0x20002000}, ++ {OP_ZR, QM_REG_VOQQMASK_9_LSB, 0x2}, ++ {OP_WR, QM_REG_VOQQMASK_9_LSB_EXT_A, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_9_MSB_EXT_A, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_10_LSB, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_10_MSB, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_10_LSB_EXT_A, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_10_MSB_EXT_A, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_11_LSB, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_11_MSB, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_11_LSB_EXT_A, 0x0}, ++ {OP_WR, QM_REG_VOQQMASK_11_MSB_EXT_A, 0x0}, ++ {OP_WR, QM_REG_VOQPORT_0, 0x0}, ++ {OP_WR, QM_REG_VOQPORT_1, 0x1}, ++ {OP_ZR, QM_REG_VOQPORT_2, 0xa}, ++ {OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08}, ++ {OP_WR, QM_REG_CMINTVOQMASK_1, 0x40}, ++ {OP_WR, QM_REG_CMINTVOQMASK_2, 0x100}, ++ {OP_WR, QM_REG_CMINTVOQMASK_3, 0x20}, ++ {OP_WR, QM_REG_CMINTVOQMASK_4, 0x17}, ++ {OP_WR, QM_REG_CMINTVOQMASK_5, 0x80}, ++ {OP_WR, QM_REG_CMINTVOQMASK_6, 0x200}, ++ {OP_WR, QM_REG_CMINTVOQMASK_7, 0x0}, ++ {OP_WR, QM_REG_HWAEMPTYMASK_LSB, 0x1ff01ff}, ++ {OP_WR, QM_REG_HWAEMPTYMASK_MSB, 0x1ff01ff}, ++ {OP_WR, QM_REG_HWAEMPTYMASK_LSB_EXT_A, 0x1ff01ff}, ++ {OP_WR, QM_REG_HWAEMPTYMASK_MSB_EXT_A, 0x1ff01ff}, ++ {OP_WR, QM_REG_ENBYPVOQMASK, 0x13}, ++ {OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f}, ++ {OP_WR, QM_REG_VOQINITCREDIT_0, 0x140}, ++ {OP_WR, QM_REG_VOQINITCREDIT_1, 0x140}, ++ {OP_ZR, QM_REG_VOQINITCREDIT_2, 0x2}, ++ {OP_WR, QM_REG_VOQINITCREDIT_4, 0xc0}, ++ {OP_ZR, QM_REG_VOQINITCREDIT_5, 0x7}, ++ {OP_WR, QM_REG_TASKCRDCOST_0, 0x48}, ++ {OP_WR, QM_REG_TASKCRDCOST_1, 0x48}, ++ {OP_ZR, QM_REG_TASKCRDCOST_2, 0x2}, ++ {OP_WR, QM_REG_TASKCRDCOST_4, 0x48}, ++ {OP_ZR, QM_REG_TASKCRDCOST_5, 0x7}, ++ {OP_WR, QM_REG_BYTECRDINITVAL, 0x8000}, ++ {OP_WR, QM_REG_BYTECRDCOST, 0x25e4}, ++ {OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff}, ++ {OP_WR, QM_REG_ENBYTECRD_LSB, 0xf000f}, ++ {OP_WR, QM_REG_ENBYTECRD_MSB, 0xf000f}, ++ {OP_WR, QM_REG_ENBYTECRD_LSB_EXT_A, 0xf000f}, ++ {OP_WR, QM_REG_ENBYTECRD_MSB_EXT_A, 0xf000f}, ++ {OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0}, ++ {OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff}, ++ {OP_WR, QM_REG_BYTECRDPORT_LSB_EXT_A, 0x0}, ++ {OP_WR, QM_REG_BYTECRDPORT_MSB_EXT_A, 0xffffffff}, ++ {OP_WR, QM_REG_PQ2PCIFUNC_0, 0x0}, ++ {OP_WR, QM_REG_PQ2PCIFUNC_1, 0x2}, ++ {OP_WR, QM_REG_PQ2PCIFUNC_2, 0x1}, ++ {OP_WR, QM_REG_PQ2PCIFUNC_3, 0x3}, ++ {OP_WR, QM_REG_PQ2PCIFUNC_4, 0x4}, ++ {OP_WR, QM_REG_PQ2PCIFUNC_5, 0x6}, ++ {OP_WR, QM_REG_PQ2PCIFUNC_6, 0x5}, ++ {OP_WR, QM_REG_PQ2PCIFUNC_7, 0x7}, ++ {OP_WR, QM_REG_CMINTEN, 0xff}, ++/* #define QM_COMMON_END 551 */ ++/* #define PBF_COMMON_START 572 */ ++ {OP_WR, PBF_REG_INIT, 0x1}, ++ {OP_WR, PBF_REG_INIT_P4, 0x1}, ++ {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1}, ++ {OP_WR, PBF_REG_IF_ENABLE_REG, 0x7fff}, ++ {OP_WR, PBF_REG_INIT_P4, 0x0}, ++ {OP_WR, PBF_REG_INIT, 0x0}, ++ {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0}, ++/* #define PBF_COMMON_END 573 */ ++/* #define PBF_PORT0_START 574 */ ++ {OP_WR, PBF_REG_INIT_P0, 0x1}, ++ {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1}, ++ {OP_WR, PBF_REG_INIT_P0, 0x0}, ++ {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0}, ++/* #define PBF_PORT0_END 575 */ ++/* #define PBF_PORT1_START 576 */ ++ {OP_WR, PBF_REG_INIT_P1, 0x1}, ++ {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1}, ++ {OP_WR, PBF_REG_INIT_P1, 0x0}, ++ {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0}, ++/* #define PBF_PORT1_END 577 */ ++/* #define XCM_COMMON_START 594 */ ++ {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32}, ++ {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020}, ++ {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020}, ++ {OP_WR, XCM_REG_TM_XCM_HDR, 0x1000030}, ++ {OP_WR, XCM_REG_ERR_XCM_HDR, 0x8100000}, ++ {OP_WR, XCM_REG_ERR_EVNT_ID, 0x33}, ++ {OP_WR, XCM_REG_EXPR_EVNT_ID, 0x30}, ++ {OP_WR, XCM_REG_STOP_EVNT_ID, 0x31}, ++ {OP_WR, XCM_REG_STORM_WEIGHT, 0x3}, ++ {OP_WR, XCM_REG_TSEM_WEIGHT, 0x6}, ++ {OP_WR, XCM_REG_CSEM_WEIGHT, 0x3}, ++ {OP_WR, XCM_REG_USEM_WEIGHT, 0x3}, ++ {OP_WR, XCM_REG_DORQ_WEIGHT, 0x2}, ++ {OP_WR, XCM_REG_PBF_WEIGHT, 0x0}, ++ {OP_WR, XCM_REG_NIG0_WEIGHT, 0x2}, ++ {OP_WR, XCM_REG_CP_WEIGHT, 0x0}, ++ {OP_WR, XCM_REG_XSDM_WEIGHT, 0x6}, ++ {OP_WR, XCM_REG_XQM_P_WEIGHT, 0x4}, ++ {OP_WR, XCM_REG_XQM_S_WEIGHT, 0x2}, ++ {OP_WR, XCM_REG_TM_WEIGHT, 0x2}, ++ {OP_WR, XCM_REG_XCM_XQM_USE_Q, 0x1}, ++ {OP_WR, XCM_REG_XQM_BYP_ACT_UPD, 0x6}, ++ {OP_WR, XCM_REG_UNA_GT_NXT_Q, 0x0}, ++ {OP_WR, XCM_REG_AUX1_Q, 0x2}, ++ {OP_WR, XCM_REG_AUX_CNT_FLG_Q_19, 0x1}, ++ {OP_WR, XCM_REG_GR_ARB_TYPE, 0x1}, ++ {OP_WR, XCM_REG_GR_LD0_PR, 0x1}, ++ {OP_WR, XCM_REG_GR_LD1_PR, 0x2}, ++ {OP_WR, XCM_REG_CFC_INIT_CRD, 0x1}, ++ {OP_WR, XCM_REG_FIC0_INIT_CRD, 0x40}, ++ {OP_WR, XCM_REG_FIC1_INIT_CRD, 0x40}, ++ {OP_WR, XCM_REG_TM_INIT_CRD, 0x4}, ++ {OP_WR, XCM_REG_XQM_INIT_CRD, 0x20}, ++ {OP_WR, XCM_REG_XX_INIT_CRD, 0x2}, ++ {OP_WR, XCM_REG_XX_MSG_NUM, 0x20}, ++ {OP_ZR, XCM_REG_XX_TABLE, 0x12}, ++ {OP_SW, XCM_REG_XX_DESCR_TABLE, 0x1f032b}, ++ {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf}, ++ {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7}, ++ {OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb}, ++ {OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe}, ++ {OP_WR, XCM_REG_N_SM_CTX_LD_4, 0xe}, ++ {OP_ZR, XCM_REG_N_SM_CTX_LD_5, 0x3}, ++ {OP_WR, XCM_REG_XCM_REG0_SZ, 0x4}, ++ {OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1}, ++ {OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1}, ++ {OP_WR, XCM_REG_XCM_XQM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_STORM_XCM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_XQM_XCM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_XSDM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_TM_XCM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_XCM_TM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_TSEM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_CSEM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_USEM_IFEN, 0x1}, ++ {OP_WR, XCM_REG_DORQ_IFEN, 0x1}, ++ {OP_WR, XCM_REG_PBF_IFEN, 0x1}, ++ {OP_WR, XCM_REG_NIG0_IFEN, 0x1}, ++ {OP_WR, XCM_REG_NIG1_IFEN, 0x1}, ++ {OP_WR, XCM_REG_CDU_AG_WR_IFEN, 0x1}, ++ {OP_WR, XCM_REG_CDU_AG_RD_IFEN, 0x1}, ++ {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1}, ++ {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1}, ++ {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1}, ++/* #define XCM_COMMON_END 595 */ ++/* #define XCM_FUNC0_START 600 */ ++ {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, ++ {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, ++ {OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0}, ++/* #define XCM_FUNC0_END 601 */ ++/* #define XCM_FUNC1_START 602 */ ++ {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, ++ {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, ++ {OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0}, ++/* #define XCM_FUNC1_END 603 */ ++/* #define XCM_FUNC2_START 604 */ ++ {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, ++ {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, ++ {OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0}, ++/* #define XCM_FUNC2_END 605 */ ++/* #define XCM_FUNC3_START 606 */ ++ {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, ++ {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, ++ {OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0}, ++/* #define XCM_FUNC3_END 607 */ ++/* #define XCM_FUNC4_START 608 */ ++ {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, ++ {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, ++ {OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0}, ++/* #define XCM_FUNC4_END 609 */ ++/* #define XCM_FUNC5_START 610 */ ++ {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, ++ {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, ++ {OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0}, ++/* #define XCM_FUNC5_END 611 */ ++/* #define XCM_FUNC6_START 612 */ ++ {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, ++ {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, ++ {OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0}, ++/* #define XCM_FUNC6_END 613 */ ++/* #define XCM_FUNC7_START 614 */ ++ {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, ++ {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, ++ {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, ++ {OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0}, ++/* #define XCM_FUNC7_END 615 */ ++/* #define XSEM_COMMON_START 616 */ ++ {OP_ZP, XSEM_REG_INT_TABLE, 0xc00000}, ++ {OP_WR_64, XSEM_REG_INT_TABLE + 0x3a8, 0xb034a}, ++ {OP_ZP, XSEM_REG_PRAM, 0x32fd0000}, ++ {OP_ZP, XSEM_REG_PRAM + 0x8000, 0x357e0cc0}, ++ {OP_ZP, XSEM_REG_PRAM + 0x10000, 0x3ae41a20}, ++ {OP_ZP, XSEM_REG_PRAM + 0x18000, 0x39cf28da}, ++ {OP_ZP, XSEM_REG_PRAM + 0x20000, 0x1c3c374e}, ++ {OP_WR_64, XSEM_REG_PRAM + 0x23710, 0x391e034c}, ++ {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0}, ++ {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0}, ++ {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0}, ++ {OP_RD, XSEM_REG_MSG_NUM_FOC1, 0x0}, ++ {OP_RD, XSEM_REG_MSG_NUM_FOC2, 0x0}, ++ {OP_RD, XSEM_REG_MSG_NUM_FOC3, 0x0}, ++ {OP_WR, XSEM_REG_ARB_ELEMENT0, 0x1}, ++ {OP_WR, XSEM_REG_ARB_ELEMENT1, 0x2}, ++ {OP_WR, XSEM_REG_ARB_ELEMENT2, 0x3}, ++ {OP_WR, XSEM_REG_ARB_ELEMENT3, 0x0}, ++ {OP_WR, XSEM_REG_ARB_ELEMENT4, 0x4}, ++ {OP_WR, XSEM_REG_ARB_CYCLE_SIZE, 0x1}, ++ {OP_WR, XSEM_REG_TS_0_AS, 0x0}, ++ {OP_WR, XSEM_REG_TS_1_AS, 0x1}, ++ {OP_WR, XSEM_REG_TS_2_AS, 0x4}, ++ {OP_WR, XSEM_REG_TS_3_AS, 0x0}, ++ {OP_WR, XSEM_REG_TS_4_AS, 0x1}, ++ {OP_WR, XSEM_REG_TS_5_AS, 0x3}, ++ {OP_WR, XSEM_REG_TS_6_AS, 0x0}, ++ {OP_WR, XSEM_REG_TS_7_AS, 0x1}, ++ {OP_WR, XSEM_REG_TS_8_AS, 0x4}, ++ {OP_WR, XSEM_REG_TS_9_AS, 0x0}, ++ {OP_WR, XSEM_REG_TS_10_AS, 0x1}, ++ {OP_WR, XSEM_REG_TS_11_AS, 0x3}, ++ {OP_WR, XSEM_REG_TS_12_AS, 0x0}, ++ {OP_WR, XSEM_REG_TS_13_AS, 0x1}, ++ {OP_WR, XSEM_REG_TS_14_AS, 0x4}, ++ {OP_WR, XSEM_REG_TS_15_AS, 0x0}, ++ {OP_WR, XSEM_REG_TS_16_AS, 0x4}, ++ {OP_WR, XSEM_REG_TS_17_AS, 0x3}, ++ {OP_ZR, XSEM_REG_TS_18_AS, 0x2}, ++ {OP_WR, XSEM_REG_ENABLE_IN, 0x3fff}, ++ {OP_WR, XSEM_REG_ENABLE_OUT, 0x3ff}, ++ {OP_WR, XSEM_REG_FIC0_DISABLE, 0x0}, ++ {OP_WR, XSEM_REG_FIC1_DISABLE, 0x0}, ++ {OP_WR, XSEM_REG_PAS_DISABLE, 0x0}, ++ {OP_WR, XSEM_REG_THREADS_LIST, 0xffff}, ++ {OP_ZR, XSEM_REG_PASSIVE_BUFFER, 0x800}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x18bc0, 0x1}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x18000, 0x0}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66}, ++ {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, ++ {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18300, 0x138}, ++ {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18300, 0x1388}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, ++ {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4}, ++ {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18340, 0x0}, ++ {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18340, 0x5}, ++ {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4}, ++ {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500}, ++ {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x11480, 0x0}, ++ {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x11480, 0x1}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x29c8, 0x4}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x29c8 + 0x10, 0x2034e}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2080, 0x48}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x9020, 0xc8}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x9000, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2000, 0x20}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x23d0, 0x20350}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x2498, 0x40352}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x2c50, 0x0}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x2c10, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x2c08, 0x20356}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x3000, 0x20358}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3000 + 0x8, 0x100}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4040, 0x10}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x4000, 0x10035a}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x8408, 0x2036a}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c00, 0x10036c}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c40, 0x8037c}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80384}, ++/* #define XSEM_COMMON_END 617 */ ++/* #define XSEM_PORT0_START 618 */ ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xc000, 0xd8}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x24a8, 0x14}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2548, 0x24}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2668, 0x24}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2788, 0x24}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x28a8, 0x24}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xa000, 0x28}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xa140, 0xc}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x29e0, 0x2038c}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5020, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5030, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5010, 0x2}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x5208, 0x1}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x2038e}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xbcd0, 0x2}, ++/* #define XSEM_PORT0_END 619 */ ++/* #define XSEM_PORT1_START 620 */ ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xc360, 0xd8}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x24f8, 0x14}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x25d8, 0x24}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x26f8, 0x24}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2818, 0x24}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2938, 0x24}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xa170, 0xc}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x29e8, 0x20390}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5028, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5038, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5008, 0x2}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5018, 0x2}, ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0x520c, 0x1}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x20392}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xbcd8, 0x2}, ++/* #define XSEM_PORT1_END 621 */ ++/* #define XSEM_FUNC0_START 622 */ ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6c0, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x29f0, 0x100394}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5048, 0xe}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb000, 0x6}, ++/* #define XSEM_FUNC0_END 623 */ ++/* #define XSEM_FUNC1_START 624 */ ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6c4, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x2a30, 0x1003a4}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5080, 0xe}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb018, 0x6}, ++/* #define XSEM_FUNC1_END 625 */ ++/* #define XSEM_FUNC2_START 626 */ ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6c8, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x2a70, 0x1003b4}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb030, 0x6}, ++/* #define XSEM_FUNC2_END 627 */ ++/* #define XSEM_FUNC3_START 628 */ ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6cc, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x2ab0, 0x1003c4}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb048, 0x6}, ++/* #define XSEM_FUNC3_END 629 */ ++/* #define XSEM_FUNC4_START 630 */ ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6d0, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x2af0, 0x1003d4}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5128, 0xe}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb060, 0x6}, ++/* #define XSEM_FUNC4_END 631 */ ++/* #define XSEM_FUNC5_START 632 */ ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6d4, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x2b30, 0x1003e4}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5160, 0xe}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb078, 0x6}, ++/* #define XSEM_FUNC5_END 633 */ ++/* #define XSEM_FUNC6_START 634 */ ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6d8, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x2b70, 0x1003f4}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5198, 0xe}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb090, 0x6}, ++/* #define XSEM_FUNC6_END 635 */ ++/* #define XSEM_FUNC7_START 636 */ ++ {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6dc, 0x0}, ++ {OP_SW, XSEM_REG_FAST_MEMORY + 0x2bb0, 0x100404}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe}, ++ {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb0a8, 0x6}, ++/* #define XSEM_FUNC7_END 637 */ ++/* #define CDU_COMMON_START 638 */ ++ {OP_WR, CDU_REG_CDU_CONTROL0, 0x1}, ++ {OP_WR, CDU_REG_MF_MODE, 0x1}, ++ {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000}, ++ {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d}, ++ {OP_WB, CDU_REG_L1TT, 0x2000414}, ++ {OP_WB, CDU_REG_MATT, 0x280614}, ++ {OP_ZR, CDU_REG_MATT + 0xa0, 0x18}, ++/* #define CDU_COMMON_END 639 */ ++/* #define DMAE_COMMON_START 660 */ ++ {OP_ZR, DMAE_REG_CMD_MEM, 0xe0}, ++ {OP_WR, DMAE_REG_CRC16C_INIT, 0x0}, ++ {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1}, ++ {OP_WR, DMAE_REG_PXP_REQ_INIT_CRD, 0x2}, ++ {OP_WR, DMAE_REG_PCI_IFEN, 0x1}, ++ {OP_WR, DMAE_REG_GRC_IFEN, 0x1}, ++/* #define DMAE_COMMON_END 661 */ ++/* #define PXP_COMMON_START 682 */ ++ {OP_WB, PXP_REG_HST_INBOUND_INT + 0x400, 0x5063c}, ++ {OP_WB, PXP_REG_HST_INBOUND_INT, 0x50641}, ++ {OP_WB, PXP_REG_HST_INBOUND_INT + 0x20, 0x50646}, ++/* #define PXP_COMMON_END 683 */ ++/* #define CFC_COMMON_START 704 */ ++ {OP_ZR, CFC_REG_LINK_LIST, 0x100}, ++ {OP_WR, CFC_REG_CONTROL0, 0x10}, ++ {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff}, ++ {OP_WR, CFC_REG_INTERFACES, 0x280000}, ++ {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a}, ++ {OP_WR, CFC_REG_INTERFACES, 0x0}, ++/* #define CFC_COMMON_END 705 */ ++/* #define HC_FUNC0_START 732 */ ++ {OP_WR, HC_REG_CONFIG_0, 0x1080}, ++ {OP_WR, HC_REG_FUNC_NUM_P0, 0x0}, ++ {OP_WR, HC_REG_ATTN_NUM_P0, 0x10}, ++ {OP_WR, HC_REG_ATTN_IDX, 0x0}, ++ {OP_ZR, HC_REG_ATTN_BIT, 0x2}, ++ {OP_WR, HC_REG_VQID_0, 0x2b5}, ++ {OP_WR, HC_REG_PCI_CONFIG_0, 0x0}, ++ {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a}, ++ {OP_WR, HC_REG_INT_MASK, 0x1ffff}, ++ {OP_ZR, HC_REG_PBA_COMMAND, 0x2}, ++ {OP_WR, HC_REG_CONFIG_0, 0x1a80}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, ++/* #define HC_FUNC0_END 733 */ ++/* #define HC_FUNC1_START 734 */ ++ {OP_WR, HC_REG_CONFIG_1, 0x1080}, ++ {OP_WR, HC_REG_FUNC_NUM_P1, 0x1}, ++ {OP_WR, HC_REG_ATTN_NUM_P1, 0x10}, ++ {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0}, ++ {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2}, ++ {OP_WR, HC_REG_VQID_1, 0x2b5}, ++ {OP_WR, HC_REG_PCI_CONFIG_1, 0x0}, ++ {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a}, ++ {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff}, ++ {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2}, ++ {OP_WR, HC_REG_CONFIG_1, 0x1a80}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, ++/* #define HC_FUNC1_END 735 */ ++/* #define HC_FUNC2_START 736 */ ++ {OP_WR, HC_REG_CONFIG_0, 0x1080}, ++ {OP_WR, HC_REG_FUNC_NUM_P0, 0x2}, ++ {OP_WR, HC_REG_ATTN_NUM_P0, 0x10}, ++ {OP_WR, HC_REG_ATTN_IDX, 0x0}, ++ {OP_ZR, HC_REG_ATTN_BIT, 0x2}, ++ {OP_WR, HC_REG_VQID_0, 0x2b5}, ++ {OP_WR, HC_REG_PCI_CONFIG_0, 0x0}, ++ {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a}, ++ {OP_WR, HC_REG_INT_MASK, 0x1ffff}, ++ {OP_ZR, HC_REG_PBA_COMMAND, 0x2}, ++ {OP_WR, HC_REG_CONFIG_0, 0x1a80}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, ++/* #define HC_FUNC2_END 737 */ ++/* #define HC_FUNC3_START 738 */ ++ {OP_WR, HC_REG_CONFIG_1, 0x1080}, ++ {OP_WR, HC_REG_FUNC_NUM_P1, 0x3}, ++ {OP_WR, HC_REG_ATTN_NUM_P1, 0x10}, ++ {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0}, ++ {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2}, ++ {OP_WR, HC_REG_VQID_1, 0x2b5}, ++ {OP_WR, HC_REG_PCI_CONFIG_1, 0x0}, ++ {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a}, ++ {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff}, ++ {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2}, ++ {OP_WR, HC_REG_CONFIG_1, 0x1a80}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, ++/* #define HC_FUNC3_END 739 */ ++/* #define HC_FUNC4_START 740 */ ++ {OP_WR, HC_REG_CONFIG_0, 0x1080}, ++ {OP_WR, HC_REG_FUNC_NUM_P0, 0x4}, ++ {OP_WR, HC_REG_ATTN_NUM_P0, 0x10}, ++ {OP_WR, HC_REG_ATTN_IDX, 0x0}, ++ {OP_ZR, HC_REG_ATTN_BIT, 0x2}, ++ {OP_WR, HC_REG_VQID_0, 0x2b5}, ++ {OP_WR, HC_REG_PCI_CONFIG_0, 0x0}, ++ {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a}, ++ {OP_WR, HC_REG_INT_MASK, 0x1ffff}, ++ {OP_ZR, HC_REG_PBA_COMMAND, 0x2}, ++ {OP_WR, HC_REG_CONFIG_0, 0x1a80}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, ++/* #define HC_FUNC4_END 741 */ ++/* #define HC_FUNC5_START 742 */ ++ {OP_WR, HC_REG_CONFIG_1, 0x1080}, ++ {OP_WR, HC_REG_FUNC_NUM_P1, 0x5}, ++ {OP_WR, HC_REG_ATTN_NUM_P1, 0x10}, ++ {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0}, ++ {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2}, ++ {OP_WR, HC_REG_VQID_1, 0x2b5}, ++ {OP_WR, HC_REG_PCI_CONFIG_1, 0x0}, ++ {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a}, ++ {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff}, ++ {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2}, ++ {OP_WR, HC_REG_CONFIG_1, 0x1a80}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, ++/* #define HC_FUNC5_END 743 */ ++/* #define HC_FUNC6_START 744 */ ++ {OP_WR, HC_REG_CONFIG_0, 0x1080}, ++ {OP_WR, HC_REG_FUNC_NUM_P0, 0x6}, ++ {OP_WR, HC_REG_ATTN_NUM_P0, 0x10}, ++ {OP_WR, HC_REG_ATTN_IDX, 0x0}, ++ {OP_ZR, HC_REG_ATTN_BIT, 0x2}, ++ {OP_WR, HC_REG_VQID_0, 0x2b5}, ++ {OP_WR, HC_REG_PCI_CONFIG_0, 0x0}, ++ {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a}, ++ {OP_WR, HC_REG_INT_MASK, 0x1ffff}, ++ {OP_ZR, HC_REG_PBA_COMMAND, 0x2}, ++ {OP_WR, HC_REG_CONFIG_0, 0x1a80}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, ++/* #define HC_FUNC6_END 745 */ ++/* #define HC_FUNC7_START 746 */ ++ {OP_WR, HC_REG_CONFIG_1, 0x1080}, ++ {OP_WR, HC_REG_FUNC_NUM_P1, 0x7}, ++ {OP_WR, HC_REG_ATTN_NUM_P1, 0x10}, ++ {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0}, ++ {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2}, ++ {OP_WR, HC_REG_VQID_1, 0x2b5}, ++ {OP_WR, HC_REG_PCI_CONFIG_1, 0x0}, ++ {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a}, ++ {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff}, ++ {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2}, ++ {OP_WR, HC_REG_CONFIG_1, 0x1a80}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, ++ {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, ++/* #define HC_FUNC7_END 747 */ ++/* #define PXP2_COMMON_START 748 */ ++ {OP_WR, PXP2_REG_RQ_DRAM_ALIGN, 0x1}, ++ {OP_WR, PXP2_REG_PGL_CONTROL0, 0xe38340}, ++ {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10}, ++ {OP_WR, PXP2_REG_RQ_ELT_DISABLE, 0x1}, ++ {OP_WR, PXP2_REG_WR_REV_MODE, 0x0}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_3, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_4, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_5, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_6, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_TSDM_7, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_2, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_3, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_4, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_1, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_5, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_6, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_7, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_0, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_1, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_2, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_3, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_4, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff}, ++ {OP_WR, PXP2_REG_PGL_INT_XSDM_0, 0xff802000}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_0, 0xf0005000}, ++ {OP_WR, PXP2_REG_PGL_INT_USDM_1, 0xf0001000}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x8}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ11, 0x2}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ17, 0x4}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ18, 0x5}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4}, ++ {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0}, ++ {OP_WR, PXP2_REG_RD_START_INIT, 0x1}, ++ {OP_WR, PXP2_REG_WR_DMAE_TH, 0x3f}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD3, 0x803}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD4, 0x40}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD5, 0x3}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD6, 0x803}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD7, 0x803}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD8, 0x803}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD9, 0x10003}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD10, 0x803}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD11, 0x803}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD12, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD13, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD14, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD15, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD16, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD17, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD18, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD19, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD20, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD22, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD23, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD24, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD25, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD26, 0x3}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_ADD27, 0x3}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_ADD28, 0x2403}, ++ {OP_WR, PXP2_REG_RQ_BW_WR_ADD29, 0x2f}, ++ {OP_WR, PXP2_REG_RQ_BW_WR_ADD30, 0x9}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND0, 0x19}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB1, 0x184}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB2, 0x183}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB3, 0x306}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND4, 0x19}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND5, 0x6}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB6, 0x306}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB7, 0x306}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB8, 0x306}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB9, 0xc86}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB10, 0x306}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB11, 0x306}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND12, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND13, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND14, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND15, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND16, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND17, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND18, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND19, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND20, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND22, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND23, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND24, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND25, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND26, 0x6}, ++ {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND27, 0x6}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_UB28, 0x306}, ++ {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND29, 0x13}, ++ {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND30, 0x6}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_L1, 0x1004}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440}, ++ {OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440}, ++ {OP_WR, PXP2_REG_RQ_ILT_MODE, 0x1}, ++ {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1}, ++/* #define PXP2_COMMON_END 749 */ ++/* #define MISC_AEU_COMMON_START 770 */ ++ {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16}, ++ {OP_WR, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555}, ++ {OP_WR, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_NIG_0, 0xf0000000}, ++ {OP_WR, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555}, ++ {OP_WR, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_PXP_0, 0xf0000000}, ++ {OP_WR, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555}, ++ {OP_WR, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_NIG_1, 0xf0000000}, ++ {OP_WR, MISC_REG_AEU_ENABLE1_PXP_1, 0x0}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_PXP_1, 0x10000}, ++ {OP_WR, MISC_REG_AEU_ENABLE3_PXP_1, 0x5014}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_PXP_1, 0x0}, ++ {OP_WR, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00}, ++ {OP_WR, MISC_REG_AEU_GENERAL_MASK, 0x3}, ++/* #define MISC_AEU_COMMON_END 771 */ ++/* #define MISC_AEU_PORT0_START 772 */ ++ {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff55fff}, ++ {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0xf00003e0}, ++ {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000}, ++ {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000}, ++ {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x7}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4, 0x400}, ++ {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5, 0x3}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5, 0x1000}, ++ {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6, 0x3}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6, 0x4000}, ++ {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7, 0x3}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7, 0x10000}, ++ {OP_ZR, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x4}, ++/* #define MISC_AEU_PORT0_END 773 */ ++/* #define MISC_AEU_PORT1_START 774 */ ++ {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff55fff}, ++ {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0xf00003e0}, ++ {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0}, ++ {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000}, ++ {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000}, ++ {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x7}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4, 0x800}, ++ {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5, 0x3}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5, 0x2000}, ++ {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6, 0x3}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6, 0x8000}, ++ {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7, 0x3}, ++ {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7, 0x20000}, ++ {OP_ZR, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x4}, ++/* #define MISC_AEU_PORT1_END 775 */ ++ ++}; ++ ++static const u16 init_ops_offsets_e1h[] = { ++ 0x0000, 0x0031, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0031, 0x0032, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0032, ++ 0x0056, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0056, 0x008c, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x008c, 0x0090, 0x0090, 0x0094, 0x0094, 0x0098, 0x0098, 0x009c, 0x009c, ++ 0x00a0, 0x00a0, 0x00a4, 0x00a4, 0x00a8, 0x00a8, 0x00ac, 0x00ac, 0x00b1, ++ 0x00b1, 0x00b3, 0x00b3, 0x00b5, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x00b5, 0x0102, 0x0102, 0x010a, 0x010a, 0x0112, 0x0112, ++ 0x011b, 0x011b, 0x0124, 0x0124, 0x012d, 0x012d, 0x0136, 0x0136, 0x013f, ++ 0x013f, 0x0148, 0x0148, 0x0151, 0x0151, 0x015a, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x015a, 0x015f, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x015f, 0x0160, 0x0160, 0x0161, 0x0161, 0x0162, 0x0162, 0x0163, ++ 0x0163, 0x0164, 0x0164, 0x0165, 0x0165, 0x0166, 0x0166, 0x0167, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0167, 0x016c, 0x016c, 0x0179, 0x0179, 0x0186, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0186, 0x0187, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0187, 0x01be, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x01be, 0x01e9, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x01e9, 0x021a, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x021a, 0x0221, 0x0221, 0x0228, 0x0228, 0x022f, 0x022f, ++ 0x0236, 0x0236, 0x023d, 0x023d, 0x0244, 0x0244, 0x024b, 0x024b, 0x0252, ++ 0x0252, 0x028a, 0x0000, 0x0000, 0x0000, 0x0000, 0x028a, 0x028e, 0x028e, ++ 0x0292, 0x0292, 0x0296, 0x0296, 0x029a, 0x029a, 0x029e, 0x029e, 0x02a2, ++ 0x02a2, 0x02a6, 0x02a6, 0x02aa, 0x02aa, 0x02fc, 0x02fc, 0x0313, 0x0313, ++ 0x032a, 0x032a, 0x032d, 0x032d, 0x0330, 0x0330, 0x0333, 0x0333, 0x0336, ++ 0x0336, 0x0339, 0x0339, 0x033c, 0x033c, 0x033f, 0x033f, 0x0342, 0x0342, ++ 0x0383, 0x0383, 0x038a, 0x038a, 0x0391, 0x0391, 0x0395, 0x0395, 0x0399, ++ 0x0399, 0x039d, 0x039d, 0x03a1, 0x03a1, 0x03a5, 0x03a5, 0x03a9, 0x03a9, ++ 0x03ad, 0x03ad, 0x03b1, 0x03b1, 0x03b2, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03b2, 0x03c4, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x03c4, 0x03d9, 0x03d9, 0x03dc, 0x03dc, 0x03df, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03df, 0x040c, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x040c, 0x050f, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x050f, 0x0516, 0x0516, 0x051a, ++ 0x051a, 0x051e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x051e, 0x055e, 0x0000, 0x0000, 0x0000, 0x0000, 0x055e, 0x0567, 0x0567, ++ 0x0570, 0x0570, 0x0579, 0x0579, 0x0582, 0x0582, 0x058b, 0x058b, 0x0594, ++ 0x0594, 0x059d, 0x059d, 0x05a6, 0x05a6, 0x05ff, 0x05ff, 0x0611, 0x0611, ++ 0x0623, 0x0623, 0x0627, 0x0627, 0x062b, 0x062b, 0x062f, 0x062f, 0x0633, ++ 0x0633, 0x0637, 0x0637, 0x063b, 0x063b, 0x063f, 0x063f, 0x0643, 0x0643, ++ 0x064a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x064a, 0x0650, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0650, 0x0653, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0653, 0x0659, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0659, 0x0668, 0x0668, 0x0677, 0x0677, 0x0686, ++ 0x0686, 0x0695, 0x0695, 0x06a4, 0x06a4, 0x06b3, 0x06b3, 0x06c2, 0x06c2, ++ 0x06d1, 0x06d1, 0x0742, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0742, 0x0755, 0x0755, 0x0766, ++ 0x0766, 0x0777, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 ++}; ++ ++static const u32 init_data_e1h[] = { ++ 0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0, ++ 0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440, ++ 0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0, ++ 0x00135580, 0x00145a40, 0x00155f00, 0x001663c0, 0x00176880, 0x00186d40, ++ 0x00197200, 0x001a76c0, 0x001b7b80, 0x001c8040, 0x001d8500, 0x001e89c0, ++ 0x001f8e80, 0x00209340, 0x00002000, 0x00004000, 0x00006000, 0x00008000, ++ 0x0000a000, 0x0000c000, 0x0000e000, 0x00010000, 0x00012000, 0x00014000, ++ 0x00016000, 0x00018000, 0x0001a000, 0x0001c000, 0x0001e000, 0x00020000, ++ 0x00022000, 0x00024000, 0x00026000, 0x00028000, 0x0002a000, 0x0002c000, ++ 0x0002e000, 0x00030000, 0x00032000, 0x00034000, 0x00036000, 0x00038000, ++ 0x0003a000, 0x0003c000, 0x0003e000, 0x00040000, 0x00042000, 0x00044000, ++ 0x00046000, 0x00048000, 0x0004a000, 0x0004c000, 0x0004e000, 0x00050000, ++ 0x00052000, 0x00054000, 0x00056000, 0x00058000, 0x0005a000, 0x0005c000, ++ 0x0005e000, 0x00060000, 0x00062000, 0x00064000, 0x00066000, 0x00068000, ++ 0x0006a000, 0x0006c000, 0x0006e000, 0x00070000, 0x00072000, 0x00074000, ++ 0x00076000, 0x00078000, 0x0007a000, 0x0007c000, 0x0007e000, 0x00080000, ++ 0x00082000, 0x00084000, 0x00086000, 0x00088000, 0x0008a000, 0x0008c000, ++ 0x0008e000, 0x00090000, 0x00092000, 0x00094000, 0x00096000, 0x00098000, ++ 0x0009a000, 0x0009c000, 0x0009e000, 0x000a0000, 0x000a2000, 0x000a4000, ++ 0x000a6000, 0x000a8000, 0x000aa000, 0x000ac000, 0x000ae000, 0x000b0000, ++ 0x000b2000, 0x000b4000, 0x000b6000, 0x000b8000, 0x000ba000, 0x000bc000, ++ 0x000be000, 0x000c0000, 0x000c2000, 0x000c4000, 0x000c6000, 0x000c8000, ++ 0x000ca000, 0x000cc000, 0x000ce000, 0x000d0000, 0x000d2000, 0x000d4000, ++ 0x000d6000, 0x000d8000, 0x000da000, 0x000dc000, 0x000de000, 0x000e0000, ++ 0x000e2000, 0x000e4000, 0x000e6000, 0x000e8000, 0x000ea000, 0x000ec000, ++ 0x000ee000, 0x000f0000, 0x000f2000, 0x000f4000, 0x000f6000, 0x000f8000, ++ 0x000fa000, 0x000fc000, 0x000fe000, 0x00100000, 0x00102000, 0x00104000, ++ 0x00106000, 0x00108000, 0x0010a000, 0x0010c000, 0x0010e000, 0x00110000, ++ 0x00112000, 0x00114000, 0x00116000, 0x00118000, 0x0011a000, 0x0011c000, ++ 0x0011e000, 0x00120000, 0x00122000, 0x00124000, 0x00126000, 0x00128000, ++ 0x0012a000, 0x0012c000, 0x0012e000, 0x00130000, 0x00132000, 0x00134000, ++ 0x00136000, 0x00138000, 0x0013a000, 0x0013c000, 0x0013e000, 0x00140000, ++ 0x00142000, 0x00144000, 0x00146000, 0x00148000, 0x0014a000, 0x0014c000, ++ 0x0014e000, 0x00150000, 0x00152000, 0x00154000, 0x00156000, 0x00158000, ++ 0x0015a000, 0x0015c000, 0x0015e000, 0x00160000, 0x00162000, 0x00164000, ++ 0x00166000, 0x00168000, 0x0016a000, 0x0016c000, 0x0016e000, 0x00170000, ++ 0x00172000, 0x00174000, 0x00176000, 0x00178000, 0x0017a000, 0x0017c000, ++ 0x0017e000, 0x00180000, 0x00182000, 0x00184000, 0x00186000, 0x00188000, ++ 0x0018a000, 0x0018c000, 0x0018e000, 0x00190000, 0x00192000, 0x00194000, ++ 0x00196000, 0x00198000, 0x0019a000, 0x0019c000, 0x0019e000, 0x001a0000, ++ 0x001a2000, 0x001a4000, 0x001a6000, 0x001a8000, 0x001aa000, 0x001ac000, ++ 0x001ae000, 0x001b0000, 0x001b2000, 0x001b4000, 0x001b6000, 0x001b8000, ++ 0x001ba000, 0x001bc000, 0x001be000, 0x001c0000, 0x001c2000, 0x001c4000, ++ 0x001c6000, 0x001c8000, 0x001ca000, 0x001cc000, 0x001ce000, 0x001d0000, ++ 0x001d2000, 0x001d4000, 0x001d6000, 0x001d8000, 0x001da000, 0x001dc000, ++ 0x001de000, 0x001e0000, 0x001e2000, 0x001e4000, 0x001e6000, 0x001e8000, ++ 0x001ea000, 0x001ec000, 0x001ee000, 0x001f0000, 0x001f2000, 0x001f4000, ++ 0x001f6000, 0x001f8000, 0x001fa000, 0x001fc000, 0x001fe000, 0x00200000, ++ 0x00202000, 0x00204000, 0x00206000, 0x00208000, 0x0020a000, 0x0020c000, ++ 0x0020e000, 0x00210000, 0x00212000, 0x00214000, 0x00216000, 0x00218000, ++ 0x0021a000, 0x0021c000, 0x0021e000, 0x00220000, 0x00222000, 0x00224000, ++ 0x00226000, 0x00228000, 0x0022a000, 0x0022c000, 0x0022e000, 0x00230000, ++ 0x00232000, 0x00234000, 0x00236000, 0x00238000, 0x0023a000, 0x0023c000, ++ 0x0023e000, 0x00240000, 0x00242000, 0x00244000, 0x00246000, 0x00248000, ++ 0x0024a000, 0x0024c000, 0x0024e000, 0x00250000, 0x00252000, 0x00254000, ++ 0x00256000, 0x00258000, 0x0025a000, 0x0025c000, 0x0025e000, 0x00260000, ++ 0x00262000, 0x00264000, 0x00266000, 0x00268000, 0x0026a000, 0x0026c000, ++ 0x0026e000, 0x00270000, 0x00272000, 0x00274000, 0x00276000, 0x00278000, ++ 0x0027a000, 0x0027c000, 0x0027e000, 0x00280000, 0x00282000, 0x00284000, ++ 0x00286000, 0x00288000, 0x0028a000, 0x0028c000, 0x0028e000, 0x00290000, ++ 0x00292000, 0x00294000, 0x00296000, 0x00298000, 0x0029a000, 0x0029c000, ++ 0x0029e000, 0x002a0000, 0x002a2000, 0x002a4000, 0x002a6000, 0x002a8000, ++ 0x002aa000, 0x002ac000, 0x002ae000, 0x002b0000, 0x002b2000, 0x002b4000, ++ 0x002b6000, 0x002b8000, 0x002ba000, 0x002bc000, 0x002be000, 0x002c0000, ++ 0x002c2000, 0x002c4000, 0x002c6000, 0x002c8000, 0x002ca000, 0x002cc000, ++ 0x002ce000, 0x002d0000, 0x002d2000, 0x002d4000, 0x002d6000, 0x002d8000, ++ 0x002da000, 0x002dc000, 0x002de000, 0x002e0000, 0x002e2000, 0x002e4000, ++ 0x002e6000, 0x002e8000, 0x002ea000, 0x002ec000, 0x002ee000, 0x002f0000, ++ 0x002f2000, 0x002f4000, 0x002f6000, 0x002f8000, 0x002fa000, 0x002fc000, ++ 0x002fe000, 0x00300000, 0x00302000, 0x00304000, 0x00306000, 0x00308000, ++ 0x0030a000, 0x0030c000, 0x0030e000, 0x00310000, 0x00312000, 0x00314000, ++ 0x00316000, 0x00318000, 0x0031a000, 0x0031c000, 0x0031e000, 0x00320000, ++ 0x00322000, 0x00324000, 0x00326000, 0x00328000, 0x0032a000, 0x0032c000, ++ 0x0032e000, 0x00330000, 0x00332000, 0x00334000, 0x00336000, 0x00338000, ++ 0x0033a000, 0x0033c000, 0x0033e000, 0x00340000, 0x00342000, 0x00344000, ++ 0x00346000, 0x00348000, 0x0034a000, 0x0034c000, 0x0034e000, 0x00350000, ++ 0x00352000, 0x00354000, 0x00356000, 0x00358000, 0x0035a000, 0x0035c000, ++ 0x0035e000, 0x00360000, 0x00362000, 0x00364000, 0x00366000, 0x00368000, ++ 0x0036a000, 0x0036c000, 0x0036e000, 0x00370000, 0x00372000, 0x00374000, ++ 0x00376000, 0x00378000, 0x0037a000, 0x0037c000, 0x0037e000, 0x00380000, ++ 0x00382000, 0x00384000, 0x00386000, 0x00388000, 0x0038a000, 0x0038c000, ++ 0x0038e000, 0x00390000, 0x00392000, 0x00394000, 0x00396000, 0x00398000, ++ 0x0039a000, 0x0039c000, 0x0039e000, 0x003a0000, 0x003a2000, 0x003a4000, ++ 0x003a6000, 0x003a8000, 0x003aa000, 0x003ac000, 0x003ae000, 0x003b0000, ++ 0x003b2000, 0x003b4000, 0x003b6000, 0x003b8000, 0x003ba000, 0x003bc000, ++ 0x003be000, 0x003c0000, 0x003c2000, 0x003c4000, 0x003c6000, 0x003c8000, ++ 0x003ca000, 0x003cc000, 0x003ce000, 0x003d0000, 0x003d2000, 0x003d4000, ++ 0x003d6000, 0x003d8000, 0x003da000, 0x003dc000, 0x003de000, 0x003e0000, ++ 0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000, ++ 0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000, ++ 0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff, ++ 0x00000200, 0x00007ff8, 0x00007ff8, 0x00000cdf, 0x00001500, 0x00000001, ++ 0x00000001, 0x00000001, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, ++ 0xffffffff, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff, ++ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, ++ 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, ++ 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000, ++ 0xffffffff, 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, ++ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, ++ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003, ++ 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, ++ 0x00000003, 0x00bebc20, 0x00002000, 0x000040c0, 0x00006180, 0x00008240, ++ 0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, 0x00012600, 0x000146c0, ++ 0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, 0x0001ea80, 0x00020b40, ++ 0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, 0x0002af00, 0x0002cfc0, ++ 0x0002f080, 0x00031140, 0x00033200, 0x000352c0, 0x00037380, 0x00039440, ++ 0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, 0x00043800, 0x000458c0, ++ 0x00047980, 0x00049a40, 0x00008000, 0x00010380, 0x00018700, 0x00020a80, ++ 0x00028e00, 0x00031180, 0x00039500, 0x00041880, 0x00049c00, 0x00051f80, ++ 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 0x0007b100, 0x00083480, ++ 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 0x000ac600, 0x000b4980, ++ 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, 0x000ddb00, 0x00007ff8, ++ 0x00007ff8, 0x0000193c, 0x00001500, 0x00001900, 0x00000028, 0x00100000, ++ 0x00000000, 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00007ff8, ++ 0x00007ff8, 0x000005c7, 0x00001500, 0xffffffff, 0xffffffff, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, ++ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x00001000, 0x00002080, 0x00003100, 0x00004180, 0x00005200, ++ 0x00006280, 0x00007300, 0x00008380, 0x00009400, 0x0000a480, 0x0000b500, ++ 0x0000c580, 0x0000d600, 0x0000e680, 0x0000f700, 0x00010780, 0x00011800, ++ 0x00012880, 0x00013900, 0x00014980, 0x00015a00, 0x00016a80, 0x00017b00, ++ 0x00018b80, 0x00019c00, 0x0001ac80, 0x0001bd00, 0x0001cd80, 0x0001de00, ++ 0x0001ee80, 0x0001ff00, 0x00007ff8, 0x00007ff8, 0x0000112e, 0x00003500, ++ 0x10000000, 0x000028ad, 0x00000000, 0x00010001, 0x00150005, 0xccccccc5, ++ 0xffffffff, 0xffffffff, 0x7058103c, 0x00000000, 0x00000000, 0x00000001, ++ 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, ++ 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, ++ 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0x00000000, 0xffffffff, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, ++ 0x40000000, 0x40000000, 0x000e0232, 0x011600d6, 0x00100000, 0x00000000, ++ 0x00720236, 0x012300f3, 0x00100000, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, ++ 0xfffffff3, 0x318fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x30efffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, ++ 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, ++ 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, ++ 0xfffffff7, 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x302fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x310fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, ++ 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, ++ 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, ++ 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x30efffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, ++ 0xfffffff5, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x31efffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, ++ 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, ++ 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, ++ 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x056fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, ++ 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, ++ 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, ++ 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffff8a, 0x042fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, ++ 0xffffff97, 0x05cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, ++ 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x316fffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, ++ 0xfffffff1, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffffff6, 0x30bfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf314, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, ++ 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, ++ 0xfffffff0, 0x307fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, ++ 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, ++ 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, ++ 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, ++ 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, ++ 0x0040cf3c, 0xcdcdcdcd, 0x000c0000, 0x000700c0, 0x00028130, 0x000b8158, ++ 0x00020210, 0x00010230, 0x000f0240, 0x00010330, 0x00080000, 0x00080080, ++ 0x00028100, 0x000b8128, 0x000201e0, 0x00010200, 0x00070210, 0x00020280, ++ 0x000f0000, 0x000800f0, 0x00028170, 0x000b8198, 0x00020250, 0x00010270, ++ 0x000b8280, 0x00080338, 0x00100000, 0x00080100, 0x00028180, 0x000b81a8, ++ 0x00020260, 0x00018280, 0x000e8298, 0x00080380, 0x000b0000, 0x000100b0, ++ 0x000280c0, 0x000580e8, 0x00020140, 0x00010160, 0x000e0170, 0x00038250, ++ 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, ++ 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, ++ 0xcccccccc, 0xcccccccc, 0x04002000 ++}; ++ ++static const u8 tsem_int_table_data_e1h[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xfb, 0x51, ++ 0xcf, 0xc0, 0xf0, 0x03, 0x8a, 0x59, 0x05, 0x19, 0x18, 0xf4, 0x84, 0x11, ++ 0x7c, 0x7a, 0x60, 0x7e, 0x4e, 0xca, 0xf4, 0x3b, 0xf2, 0x32, 0x30, 0x38, ++ 0x03, 0xb1, 0x2b, 0x10, 0x37, 0x00, 0xf1, 0x61, 0x6e, 0x06, 0x86, 0x23, ++ 0xdc, 0xc4, 0xeb, 0x3f, 0x2b, 0x8f, 0x60, 0x07, 0xca, 0x32, 0x30, 0xd4, ++ 0x02, 0xf1, 0x7e, 0x69, 0x06, 0x06, 0x2b, 0x39, 0x84, 0xb8, 0xa1, 0x02, ++ 0x03, 0xc3, 0x12, 0x20, 0x3f, 0x0d, 0x2a, 0xf6, 0x1a, 0x48, 0x17, 0xca, ++ 0x53, 0xe6, 0xee, 0xc1, 0x82, 0x55, 0x54, 0x31, 0xc5, 0x14, 0x95, 0x11, ++ 0x6c, 0x55, 0x2c, 0xf2, 0xc8, 0x58, 0x0d, 0x4d, 0xbe, 0x41, 0x19, 0x95, ++ 0xaf, 0x4e, 0x40, 0xff, 0x40, 0xe3, 0x64, 0x1d, 0x54, 0xfe, 0x04, 0x2d, ++ 0x08, 0xfd, 0x5e, 0x1b, 0x42, 0xa7, 0xa0, 0xc9, 0x4f, 0x84, 0xca, 0xbb, ++ 0x42, 0xfd, 0x95, 0xaa, 0x83, 0xdd, 0x5c, 0x37, 0x22, 0xfd, 0x9d, 0xc6, ++ 0x82, 0xca, 0x4f, 0x40, 0xe3, 0xb7, 0x30, 0xa2, 0xf2, 0xcd, 0x38, 0xd0, ++ 0xdc, 0x0f, 0x55, 0x0f, 0x00, 0x00, 0x17, 0x4b, 0x67, 0xc8, 0x03, 0x00, ++ 0x00, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 tsem_pram_data_e1h[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d, ++ 0x0d, 0x78, 0x54, 0xd5, 0xb5, 0xe8, 0x3e, 0x3f, 0x73, 0xe6, 0xcc, 0xe4, ++ 0xcc, 0xe4, 0x24, 0x24, 0x61, 0xc2, 0xef, 0x24, 0x84, 0x10, 0x34, 0xe2, ++ 0x10, 0x22, 0x06, 0x4b, 0xeb, 0x09, 0x7f, 0x86, 0x9a, 0x7a, 0x07, 0xaa, ++ 0x98, 0x5a, 0xc5, 0x01, 0x23, 0x06, 0x08, 0x24, 0x52, 0xf5, 0xe1, 0xd3, ++ 0x7e, 0x99, 0x48, 0x02, 0x01, 0x11, 0x06, 0xb5, 0x34, 0x14, 0xd4, 0xe1, ++ 0x4f, 0x69, 0x2f, 0xb6, 0x91, 0x8b, 0x96, 0x5a, 0x8a, 0x03, 0x3e, 0x2d, ++ 0xb6, 0xbe, 0xef, 0x05, 0x9f, 0xb5, 0x7a, 0xb5, 0x7d, 0xd1, 0x52, 0xfc, ++ 0x29, 0x4a, 0xca, 0xbb, 0x52, 0xfb, 0xae, 0xad, 0x6f, 0xaf, 0xb5, 0xf7, ++ 0x4e, 0xce, 0x39, 0xcc, 0x90, 0xe0, 0x4f, 0xdb, 0xfb, 0xde, 0xa5, 0x9f, ++ 0xdd, 0xd9, 0xe7, 0xec, 0x9f, 0xb5, 0xd7, 0xdf, 0x5e, 0x6b, 0xed, 0xb5, ++ 0xcf, 0x78, 0x48, 0x3e, 0x29, 0xb8, 0x9c, 0x90, 0x4f, 0xe0, 0x1f, 0x2d, ++ 0xff, 0x97, 0x41, 0x08, 0x7d, 0xd4, 0x57, 0x7a, 0x74, 0x12, 0xcf, 0xba, ++ 0x98, 0x90, 0x9c, 0x3c, 0x2b, 0xde, 0x53, 0x4e, 0xc8, 0xd0, 0x3c, 0x2b, ++ 0x45, 0x2a, 0xe9, 0x73, 0x53, 0x0b, 0x7b, 0xa5, 0xfe, 0x7e, 0xa2, 0x3c, ++ 0x9c, 0x33, 0x2b, 0x04, 0xed, 0xda, 0xf2, 0xad, 0x10, 0xa1, 0x63, 0xb4, ++ 0xe5, 0xcc, 0x23, 0x31, 0x18, 0x2b, 0xd6, 0x40, 0x48, 0x01, 0x21, 0xaa, ++ 0x4e, 0xf0, 0x9f, 0x68, 0xef, 0x31, 0xe7, 0xea, 0xa4, 0x1c, 0x1f, 0xfd, ++ 0xf5, 0x13, 0xf1, 0x5e, 0x21, 0xa4, 0xdd, 0x2c, 0xce, 0x86, 0x7e, 0xee, ++ 0xf1, 0x09, 0x49, 0x12, 0x72, 0x89, 0xbd, 0x2e, 0x13, 0x22, 0xc6, 0xa4, ++ 0xfd, 0x7c, 0x02, 0xde, 0x12, 0xfa, 0x20, 0x8f, 0x10, 0x7f, 0x95, 0x9c, ++ 0xbc, 0xa2, 0x88, 0xc2, 0x5d, 0x92, 0x4c, 0x41, 0xdd, 0x08, 0x33, 0xb8, ++ 0x0f, 0x17, 0xbd, 0x52, 0x33, 0x86, 0xae, 0x63, 0x5d, 0xb5, 0x1c, 0xf1, ++ 0x86, 0xa1, 0xf7, 0xad, 0x84, 0x4c, 0x26, 0x64, 0x05, 0x8c, 0x45, 0xeb, ++ 0xeb, 0x26, 0x76, 0xd7, 0x8c, 0xc9, 0x83, 0xf7, 0x6a, 0x04, 0xde, 0xce, ++ 0x54, 0xf6, 0xb6, 0x6a, 0xb4, 0xbd, 0x51, 0x42, 0xb0, 0x7d, 0x70, 0x62, ++ 0x3c, 0xa5, 0x61, 0x3f, 0xcb, 0x28, 0xa4, 0xfd, 0x72, 0x18, 0x08, 0x24, ++ 0xa7, 0x6c, 0x51, 0x2d, 0x09, 0x12, 0x62, 0xce, 0xd0, 0xfa, 0xe1, 0xc2, ++ 0xff, 0xb7, 0x70, 0xfd, 0x06, 0x6f, 0xa7, 0x97, 0x38, 0xdf, 0x1b, 0x64, ++ 0xfd, 0x1f, 0x95, 0x09, 0x50, 0xeb, 0x25, 0xd1, 0x8b, 0xe8, 0xf8, 0x53, ++ 0x5d, 0xef, 0xcb, 0x66, 0xbd, 0x0d, 0xe3, 0x1a, 0x84, 0x3e, 0x2f, 0xe3, ++ 0xcf, 0xe9, 0xba, 0xee, 0x87, 0x3f, 0x0a, 0x09, 0xf9, 0x12, 0x09, 0xe4, ++ 0x9d, 0xc8, 0xa2, 0x7f, 0x5f, 0x4a, 0x2e, 0x05, 0x3c, 0x90, 0x9a, 0x5c, ++ 0x42, 0xa6, 0x9c, 0x8d, 0xbf, 0x7e, 0xbc, 0xc5, 0x91, 0xbe, 0x84, 0x30, ++ 0xba, 0x68, 0xa4, 0xef, 0x1f, 0xd2, 0x41, 0xe7, 0x74, 0xb8, 0x62, 0x46, ++ 0x4f, 0xa7, 0x44, 0xd7, 0xed, 0x8b, 0xc8, 0xc4, 0x4b, 0x1f, 0xcd, 0x52, ++ 0x5e, 0xd4, 0x8b, 0x01, 0x2f, 0x47, 0x15, 0xc4, 0xc3, 0xba, 0x3a, 0x86, ++ 0xe7, 0x75, 0x33, 0xe4, 0x64, 0x5c, 0xc2, 0x75, 0xd6, 0x16, 0xd2, 0xfe, ++ 0xa3, 0x09, 0xc3, 0x63, 0xce, 0xf8, 0x62, 0x89, 0x14, 0x13, 0xb2, 0xb1, ++ 0x85, 0xd6, 0xc7, 0x9d, 0x8d, 0xe7, 0xec, 0x92, 0x84, 0x05, 0xf4, 0xf7, ++ 0x95, 0x10, 0x09, 0xf8, 0x2a, 0x9b, 0x3e, 0x1b, 0x42, 0xd7, 0x95, 0x3d, ++ 0x35, 0x85, 0x7c, 0x33, 0xba, 0x8a, 0xe1, 0x93, 0xdc, 0xcd, 0xf0, 0x11, ++ 0xa7, 0xff, 0xfb, 0xa4, 0xb8, 0x1f, 0x9f, 0xd9, 0x02, 0x9f, 0x11, 0x27, ++ 0xbe, 0xb2, 0x39, 0x3e, 0x73, 0x6a, 0x6c, 0xf8, 0x82, 0xe7, 0x55, 0x14, ++ 0x8f, 0x13, 0xe0, 0xbd, 0x13, 0x8f, 0x49, 0xf8, 0x83, 0xe2, 0xab, 0x5e, ++ 0xe0, 0x31, 0x9f, 0x8c, 0x45, 0x3c, 0xc6, 0x73, 0x11, 0xbf, 0x03, 0xe1, ++ 0xf1, 0x0a, 0x8a, 0x83, 0x2c, 0x0a, 0xbf, 0xff, 0x55, 0x6f, 0xd2, 0x5b, ++ 0xd4, 0x8f, 0x57, 0xc1, 0x17, 0x02, 0xaf, 0x26, 0xc7, 0xeb, 0x86, 0x99, ++ 0xbd, 0x3a, 0x30, 0xc3, 0x46, 0x8b, 0xf1, 0x39, 0x21, 0x29, 0x49, 0x0e, ++ 0xe1, 0x78, 0x92, 0x5c, 0x85, 0xeb, 0xc3, 0xb2, 0x03, 0xf0, 0xe6, 0xc5, ++ 0xfe, 0xf8, 0x5e, 0xa7, 0x30, 0x1b, 0x7c, 0x9e, 0x30, 0x9d, 0xc7, 0x5f, ++ 0x96, 0x40, 0xfc, 0xeb, 0x14, 0x1d, 0x43, 0x24, 0xe0, 0x53, 0x43, 0x52, ++ 0x81, 0xaf, 0x81, 0x4f, 0xd3, 0xcc, 0xbb, 0x4e, 0x4f, 0xea, 0x12, 0x6d, ++ 0xbf, 0x69, 0xaa, 0x4c, 0x80, 0x5e, 0xeb, 0x2c, 0x99, 0x84, 0x69, 0xfd, ++ 0x74, 0x99, 0x9a, 0x54, 0x00, 0xee, 0xb8, 0xd5, 0x1d, 0xb2, 0xf1, 0xa9, ++ 0x01, 0xf8, 0xa7, 0xf8, 0xba, 0x8f, 0xe3, 0x47, 0x1b, 0x21, 0x3b, 0xf0, ++ 0xa9, 0xe6, 0xf9, 0x5d, 0x7c, 0xee, 0x5c, 0xc7, 0xa6, 0xbe, 0xf5, 0x59, ++ 0x7c, 0x5d, 0x6c, 0x1d, 0xa4, 0x3b, 0xd9, 0x01, 0x70, 0x9c, 0x99, 0x29, ++ 0x93, 0x75, 0xd2, 0xc0, 0xe3, 0x0e, 0x84, 0x27, 0x31, 0xee, 0x80, 0xf0, ++ 0xf5, 0x98, 0xbe, 0x12, 0x98, 0xf7, 0x05, 0x25, 0xb2, 0x8e, 0xf2, 0xda, ++ 0xba, 0x70, 0xb2, 0x43, 0xa6, 0xf8, 0xda, 0x38, 0x83, 0xe1, 0xe3, 0x6c, ++ 0xfa, 0x7e, 0xc6, 0xf9, 0x7a, 0x7b, 0xf5, 0x92, 0x4a, 0xdb, 0x7c, 0x91, ++ 0x5e, 0xdd, 0x2c, 0xff, 0x02, 0xe6, 0x21, 0x39, 0xce, 0x75, 0x55, 0x99, ++ 0x3e, 0x33, 0xad, 0xfe, 0x3c, 0xbf, 0x79, 0x88, 0xb9, 0x60, 0x74, 0x34, ++ 0x90, 0x99, 0x1e, 0x9f, 0x1b, 0xfc, 0x61, 0x0a, 0xbf, 0x0d, 0x4f, 0x7a, ++ 0xd8, 0x94, 0x60, 0x7c, 0x7d, 0xfc, 0x3d, 0x3a, 0xa8, 0x78, 0x42, 0x76, ++ 0xe8, 0xa0, 0x17, 0xdd, 0xf3, 0x9c, 0x05, 0xaf, 0x6b, 0x5e, 0xf7, 0x3c, ++ 0x6a, 0x49, 0xb3, 0xa5, 0x62, 0xcd, 0xa9, 0x87, 0x34, 0x33, 0x41, 0xd8, ++ 0x3c, 0x16, 0xdb, 0xa7, 0x08, 0x7b, 0xae, 0x82, 0x1e, 0xa1, 0xfa, 0xc7, ++ 0x1f, 0x71, 0xea, 0x11, 0xb7, 0xfe, 0xd6, 0x46, 0x38, 0xeb, 0x6a, 0x15, ++ 0xd3, 0xd7, 0x2a, 0xb1, 0x3d, 0x2f, 0x02, 0xed, 0x4e, 0xf5, 0xcb, 0x85, ++ 0xa4, 0x5f, 0x4f, 0x57, 0x0e, 0x4e, 0xbf, 0x10, 0xab, 0x01, 0xe1, 0x75, ++ 0xeb, 0x93, 0x31, 0x5c, 0xae, 0xa7, 0xef, 0xed, 0xa9, 0x53, 0x29, 0xfd, ++ 0x4b, 0xb6, 0x09, 0x3d, 0x7d, 0xf7, 0x2f, 0xca, 0x68, 0x7d, 0x37, 0xe8, ++ 0x69, 0x5a, 0xdf, 0xdd, 0x09, 0x73, 0xd1, 0xb2, 0xcb, 0xa9, 0xa7, 0x27, ++ 0xf0, 0xc1, 0xca, 0xbf, 0xf3, 0x92, 0x0c, 0x7a, 0x7a, 0x47, 0x06, 0x3d, ++ 0x5d, 0x9c, 0xb0, 0xa6, 0x81, 0x9e, 0x2e, 0x49, 0xd0, 0x8d, 0x80, 0x8e, ++ 0x53, 0xbc, 0x9e, 0xe9, 0xe9, 0xe2, 0x8e, 0x66, 0x19, 0xe8, 0x34, 0x81, ++ 0xeb, 0x09, 0x72, 0x80, 0xe1, 0x49, 0xa7, 0xff, 0xb3, 0xeb, 0xe9, 0x62, ++ 0x3e, 0xcf, 0x98, 0x6d, 0x4e, 0x3c, 0x15, 0x73, 0x3d, 0x5d, 0xbe, 0xdf, ++ 0xf5, 0x9c, 0xeb, 0xe9, 0x62, 0x97, 0x9e, 0xde, 0x08, 0x7f, 0x50, 0x7c, ++ 0x15, 0x4a, 0x1c, 0x8f, 0x63, 0x49, 0x29, 0xe2, 0x71, 0xea, 0x20, 0xf7, ++ 0x3b, 0x8e, 0x47, 0xf7, 0x7e, 0x57, 0x0c, 0x73, 0x8f, 0xa1, 0x78, 0x7c, ++ 0x90, 0xed, 0x77, 0x39, 0x79, 0x0c, 0x8f, 0xed, 0x1d, 0x32, 0x01, 0xfd, ++ 0x70, 0x7a, 0x9b, 0x8c, 0xfa, 0x71, 0x5c, 0x51, 0x54, 0x86, 0x76, 0x42, ++ 0x4f, 0x72, 0xd0, 0x48, 0x19, 0x5f, 0xff, 0x4e, 0xae, 0xaf, 0x05, 0x9c, ++ 0x63, 0x66, 0x98, 0xd5, 0xa0, 0x4c, 0x4b, 0x88, 0x59, 0x0d, 0xf4, 0xd1, ++ 0xd6, 0x93, 0x48, 0x2a, 0x0c, 0x7a, 0xba, 0x31, 0x0e, 0xf3, 0x6c, 0x4a, ++ 0x30, 0x3d, 0x5d, 0x92, 0x20, 0x72, 0xcc, 0x66, 0x07, 0x69, 0x1c, 0x9e, ++ 0x4d, 0xa1, 0xdc, 0xd9, 0x20, 0xd7, 0xa7, 0x13, 0x6a, 0x04, 0x96, 0xb9, ++ 0x8b, 0x84, 0x65, 0xbd, 0xa8, 0x1f, 0xaf, 0x7d, 0x76, 0x07, 0xc7, 0xe3, ++ 0xd7, 0xa0, 0x95, 0x43, 0x1e, 0x9c, 0x74, 0xcc, 0xe1, 0x78, 0x75, 0xe3, ++ 0x67, 0x5c, 0xd2, 0xc9, 0xdf, 0x25, 0x0f, 0xba, 0xe8, 0xb1, 0xde, 0x59, ++ 0xcf, 0x71, 0xd1, 0xe5, 0x4a, 0xc9, 0x65, 0x7f, 0x0c, 0x92, 0x1e, 0x5e, ++ 0x95, 0xc4, 0xbd, 0xb9, 0x50, 0x4f, 0xa2, 0x5d, 0xa7, 0xd3, 0xb5, 0xe6, ++ 0xd3, 0xba, 0xf2, 0x2f, 0xcf, 0x5a, 0xc0, 0xd7, 0x46, 0x27, 0x7b, 0xa6, ++ 0x75, 0xc8, 0xc9, 0x22, 0xca, 0xb7, 0x81, 0x36, 0x56, 0xf7, 0x74, 0xa8, ++ 0xc9, 0x6a, 0x5a, 0xbf, 0x21, 0x8f, 0xf1, 0xf5, 0xd8, 0x38, 0x49, 0x82, ++ 0x5d, 0xa7, 0x84, 0xa2, 0x04, 0xec, 0xcf, 0xb1, 0x79, 0x54, 0x7f, 0xd8, ++ 0xf0, 0xe9, 0xe1, 0xf8, 0x14, 0x74, 0x83, 0x3f, 0x01, 0x1f, 0x63, 0xb8, ++ 0x7d, 0x91, 0x3d, 0x33, 0xd7, 0x07, 0xfc, 0xbd, 0x29, 0x8f, 0xe3, 0x7b, ++ 0x06, 0xc3, 0x37, 0x55, 0x80, 0x3e, 0xd0, 0x7f, 0x02, 0xdf, 0x1e, 0x8e, ++ 0x6f, 0xa3, 0xb2, 0x1b, 0xc0, 0x23, 0xb3, 0xc3, 0x4e, 0x7c, 0x4f, 0x3a, ++ 0xea, 0xd4, 0x37, 0xd7, 0xd6, 0x0d, 0x71, 0xd4, 0xaf, 0x89, 0x0e, 0x3f, ++ 0x27, 0x7d, 0x3c, 0x9c, 0x8e, 0x1e, 0x4e, 0x27, 0xc1, 0x47, 0x67, 0xe1, ++ 0x3f, 0xee, 0xb2, 0x0f, 0x2b, 0x9d, 0x75, 0x8f, 0x8b, 0x3e, 0x2d, 0x92, ++ 0x4b, 0xef, 0x0c, 0x92, 0x3e, 0xda, 0x11, 0x52, 0x06, 0x7c, 0x3b, 0x4e, ++ 0xf6, 0x47, 0x76, 0x14, 0x9d, 0xdd, 0x2e, 0x21, 0xc9, 0x48, 0x37, 0x3a, ++ 0x79, 0xf2, 0x38, 0x9d, 0x7f, 0x01, 0x35, 0xe3, 0xb2, 0xe9, 0xf8, 0xcb, ++ 0x48, 0xcf, 0x28, 0x40, 0xd0, 0x01, 0x23, 0x8c, 0xe3, 0x2c, 0x97, 0x7b, ++ 0x0a, 0xa0, 0x7e, 0x8a, 0xf4, 0x6e, 0x1e, 0x39, 0xa6, 0x7f, 0xfc, 0x51, ++ 0x2a, 0x39, 0x20, 0x51, 0x23, 0x4e, 0xa2, 0xe8, 0x5d, 0x49, 0x41, 0x1a, ++ 0xa6, 0x93, 0x54, 0x56, 0x10, 0xc1, 0x8e, 0xea, 0x05, 0xb8, 0x74, 0xc4, ++ 0x8b, 0x44, 0xff, 0xbb, 0x1e, 0xf9, 0x44, 0x95, 0x01, 0x5f, 0xc3, 0x4d, ++ 0xf6, 0x9c, 0xc4, 0xb3, 0x55, 0xa8, 0x87, 0x88, 0xf8, 0x17, 0x46, 0x3a, ++ 0x79, 0xf9, 0x9f, 0x85, 0x2b, 0x9f, 0xff, 0xb3, 0x44, 0xf1, 0x28, 0xf1, ++ 0x52, 0x01, 0x3a, 0x8e, 0x01, 0xfc, 0xc4, 0x50, 0x6f, 0xea, 0x24, 0x81, ++ 0x75, 0x3f, 0xe9, 0xc2, 0xd2, 0x20, 0xdd, 0x58, 0x06, 0xa9, 0xa6, 0x86, ++ 0xd2, 0x24, 0xa6, 0x04, 0x65, 0x2e, 0x89, 0x60, 0x49, 0x2e, 0x48, 0x3e, ++ 0x91, 0x42, 0xfd, 0x79, 0xb7, 0x89, 0xfc, 0xee, 0xfb, 0x1d, 0xf9, 0x24, ++ 0xab, 0x7f, 0x3d, 0xf7, 0xc2, 0x9f, 0x14, 0xaf, 0xc3, 0x48, 0xf4, 0x71, ++ 0x09, 0xfc, 0x27, 0x3a, 0x9e, 0xae, 0xf4, 0xf3, 0xa1, 0x8f, 0xf3, 0x21, ++ 0xb5, 0xd3, 0x90, 0x6f, 0x75, 0x93, 0xf1, 0xad, 0x5e, 0x42, 0xf7, 0xd3, ++ 0x72, 0x94, 0x7b, 0xf4, 0x5f, 0xdc, 0x78, 0x5e, 0xcb, 0xf5, 0xf2, 0x86, ++ 0x16, 0x1d, 0xcb, 0xf5, 0x2d, 0x26, 0x2e, 0x72, 0x68, 0x28, 0x19, 0x97, ++ 0x29, 0x7d, 0x7c, 0xb5, 0x4c, 0x8f, 0xe4, 0x84, 0x7a, 0x3a, 0xc0, 0x6f, ++ 0xf1, 0x37, 0xab, 0x91, 0x2b, 0x68, 0xdd, 0x6f, 0xf4, 0xbe, 0x7a, 0x13, ++ 0xd8, 0x7b, 0xb7, 0x6b, 0x91, 0x7b, 0x68, 0xfd, 0xf0, 0xcc, 0xe7, 0x43, ++ 0x50, 0xef, 0xb8, 0xdd, 0x60, 0xf6, 0x61, 0x1b, 0xb3, 0x53, 0xfd, 0x1c, ++ 0x7b, 0x1d, 0x63, 0x7b, 0x7b, 0x56, 0x51, 0xb8, 0x36, 0xdc, 0xae, 0x47, ++ 0xf8, 0x23, 0x87, 0x3e, 0xda, 0x30, 0xbe, 0xf7, 0x9d, 0x9d, 0xa0, 0xb7, ++ 0x6e, 0xf3, 0x47, 0x00, 0xbf, 0x9b, 0x42, 0x47, 0xc2, 0xab, 0x40, 0x5e, ++ 0x9a, 0x35, 0x94, 0x17, 0x6a, 0x7b, 0x22, 0xfd, 0xd6, 0x57, 0xfc, 0xa2, ++ 0x08, 0xed, 0xb5, 0x8f, 0x29, 0xfc, 0x94, 0x3e, 0x28, 0x42, 0xb4, 0xbf, ++ 0xfe, 0x11, 0x6d, 0x35, 0x89, 0xb6, 0x1b, 0xd1, 0xdb, 0x82, 0x76, 0x7d, ++ 0x73, 0x77, 0xb5, 0x92, 0x87, 0xef, 0xe3, 0x81, 0x70, 0xff, 0x7a, 0x3b, ++ 0x8a, 0x87, 0xe1, 0xfe, 0xdf, 0x71, 0x64, 0x2d, 0x09, 0xd3, 0x97, 0x39, ++ 0x95, 0x71, 0x0b, 0xf0, 0xe5, 0x2b, 0xa3, 0xa6, 0x2c, 0xe5, 0x43, 0x5f, ++ 0xa5, 0x29, 0xc5, 0x0d, 0x90, 0xca, 0xd8, 0xeb, 0x12, 0xe5, 0x3f, 0xff, ++ 0x8c, 0x18, 0xb1, 0x28, 0xfe, 0x02, 0x21, 0xb3, 0x15, 0x78, 0x45, 0xe7, ++ 0x74, 0x23, 0x6a, 0x22, 0x04, 0xf2, 0xeb, 0xc6, 0x67, 0xc7, 0xc8, 0x78, ++ 0x68, 0x21, 0x9d, 0x37, 0x3e, 0x5e, 0x8b, 0xec, 0x46, 0xb6, 0x32, 0xa5, ++ 0x79, 0x69, 0xda, 0xf5, 0xe1, 0x7f, 0xe6, 0x1d, 0xd7, 0x59, 0x69, 0xec, ++ 0xa9, 0x6c, 0x59, 0x42, 0xfe, 0x3f, 0x32, 0x7e, 0x11, 0xfa, 0xbd, 0x5e, ++ 0x12, 0x0b, 0x65, 0x81, 0x4e, 0x2a, 0xd3, 0xc8, 0x6e, 0x0a, 0xe7, 0xba, ++ 0xf1, 0x8b, 0x46, 0xc7, 0xd2, 0xd8, 0x7b, 0x36, 0x39, 0xe3, 0xf6, 0x4a, ++ 0xfa, 0x32, 0x53, 0x3f, 0x4d, 0x21, 0xcd, 0x5d, 0x36, 0x78, 0xc6, 0xca, ++ 0x32, 0xf2, 0x9f, 0x24, 0xeb, 0x4c, 0x6e, 0x43, 0x94, 0x8f, 0xa8, 0x5c, ++ 0xe5, 0x98, 0x8c, 0x9f, 0xb4, 0x19, 0xc4, 0x4a, 0xa6, 0x81, 0xe3, 0x72, ++ 0x0e, 0xbf, 0xae, 0xc6, 0x89, 0x89, 0xf6, 0xb5, 0x29, 0x81, 0x9d, 0xf5, ++ 0x45, 0xe1, 0xeb, 0x5d, 0x89, 0xc1, 0xb9, 0x56, 0x22, 0x75, 0x5d, 0x69, ++ 0xde, 0x6f, 0x07, 0x78, 0xf2, 0x41, 0x3e, 0xee, 0x4e, 0xc1, 0xfe, 0x98, ++ 0x3d, 0x93, 0xf1, 0x35, 0xfd, 0xcf, 0xea, 0xa2, 0xf0, 0xe7, 0xa8, 0xac, ++ 0x14, 0xed, 0x6b, 0x38, 0xfc, 0x7b, 0x78, 0xbf, 0xf3, 0xd0, 0x43, 0x05, ++ 0x0f, 0x02, 0x7f, 0x94, 0x0f, 0xce, 0xfe, 0xf2, 0xc2, 0xbc, 0x69, 0xe0, ++ 0x9d, 0xf8, 0x29, 0xe6, 0xdd, 0x48, 0xe7, 0x95, 0x65, 0x13, 0x9f, 0x0b, ++ 0xbc, 0xbb, 0xe9, 0x29, 0x4a, 0x49, 0xf6, 0xe1, 0xfa, 0xce, 0x8c, 0xdf, ++ 0x1c, 0x02, 0xfb, 0x34, 0x13, 0x9c, 0xe1, 0xdb, 0x50, 0xb7, 0x93, 0x70, ++ 0x33, 0x2d, 0x87, 0xd2, 0xb2, 0x96, 0x97, 0x26, 0x2b, 0xdd, 0xf3, 0x9d, ++ 0xef, 0x78, 0x5f, 0x96, 0xd9, 0x3a, 0xdc, 0xe3, 0x92, 0x5d, 0xcc, 0x9e, ++ 0xf2, 0xf3, 0xfd, 0xeb, 0xf0, 0x94, 0x57, 0x2c, 0x85, 0xd2, 0x6d, 0x74, ++ 0x9c, 0xf0, 0xb8, 0x8a, 0x53, 0x7f, 0x8c, 0x2e, 0x93, 0xd1, 0x5f, 0xdd, ++ 0xb4, 0x87, 0x6e, 0xf8, 0x45, 0xa0, 0x3f, 0x58, 0xfd, 0x91, 0x5d, 0x24, ++ 0xa9, 0x50, 0x54, 0x9e, 0xbe, 0xfb, 0x1e, 0x19, 0xe0, 0x1a, 0x49, 0xed, ++ 0x7c, 0x68, 0x3f, 0x84, 0xc4, 0x64, 0xc0, 0x5b, 0x11, 0x09, 0x4b, 0x50, ++ 0x0a, 0x3d, 0xb8, 0x86, 0xeb, 0xc1, 0x0f, 0x49, 0xf4, 0x3a, 0x39, 0x1f, ++ 0xf4, 0x74, 0x17, 0xda, 0x45, 0xb5, 0x95, 0xb7, 0x4e, 0x4b, 0x17, 0x37, ++ 0xaa, 0xe7, 0xf2, 0x71, 0x3e, 0xfb, 0xd4, 0x57, 0x68, 0xb9, 0x40, 0x8f, ++ 0x2e, 0x82, 0xf1, 0x8d, 0xc8, 0x31, 0x8b, 0xee, 0xe4, 0x44, 0x7b, 0x31, ++ 0xbd, 0x5c, 0xd1, 0xed, 0x2a, 0x34, 0xd7, 0x26, 0x0f, 0x44, 0x11, 0x7c, ++ 0xc1, 0xe4, 0xa9, 0x9d, 0xf3, 0x3b, 0xc8, 0xcd, 0x1c, 0x5a, 0x9f, 0x77, ++ 0x7d, 0x7a, 0x38, 0x37, 0xcd, 0xd4, 0x86, 0x31, 0xbb, 0xc5, 0x2c, 0x44, ++ 0x7f, 0x47, 0x35, 0x0b, 0xe7, 0xda, 0xe4, 0x71, 0x53, 0x2b, 0x95, 0x2b, ++ 0xfa, 0x3e, 0x09, 0xe3, 0xd9, 0xe4, 0xe0, 0xbb, 0x7c, 0x7d, 0xad, 0x5c, ++ 0x1e, 0xce, 0x87, 0x1f, 0x6b, 0x68, 0x69, 0x46, 0x2c, 0x4b, 0xa1, 0xaf, ++ 0x6a, 0x92, 0x89, 0x19, 0x40, 0xb7, 0xab, 0xa5, 0xd8, 0x6a, 0x99, 0x8e, ++ 0x53, 0xd1, 0x1c, 0x79, 0x56, 0xa5, 0x75, 0x63, 0x4f, 0xb7, 0xe5, 0x67, ++ 0xcf, 0xd7, 0xc2, 0xf3, 0x79, 0x25, 0xcd, 0xed, 0xc0, 0x12, 0x86, 0xd5, ++ 0x4d, 0x40, 0xdf, 0x3e, 0x72, 0xf7, 0x0a, 0x0b, 0xe8, 0x78, 0x7a, 0x04, ++ 0x5d, 0x7a, 0x1a, 0x3b, 0x41, 0x94, 0xaa, 0x25, 0x3b, 0xec, 0x14, 0x7d, ++ 0x84, 0xdf, 0x69, 0x0f, 0x0d, 0x52, 0x1e, 0x2f, 0x88, 0x24, 0xa6, 0x01, ++ 0xbc, 0x65, 0xe1, 0x63, 0xd5, 0xb9, 0x61, 0xa0, 0x53, 0x6c, 0x1b, 0xd0, ++ 0x69, 0xc4, 0xd1, 0xc8, 0x61, 0x58, 0xa2, 0x51, 0x77, 0x2c, 0x95, 0x6f, ++ 0xa3, 0x57, 0xd8, 0x64, 0x65, 0x23, 0x00, 0x4d, 0xe1, 0xd7, 0xe2, 0x94, ++ 0x6e, 0x48, 0x8f, 0x68, 0x08, 0xe8, 0xb1, 0x98, 0x44, 0x77, 0x42, 0xff, ++ 0x40, 0x65, 0x94, 0xc5, 0x2b, 0x07, 0x09, 0x47, 0x26, 0xfe, 0x0f, 0x87, ++ 0x98, 0xde, 0x0a, 0x73, 0x7e, 0x6f, 0x8f, 0x50, 0x7e, 0x97, 0xfa, 0xe5, ++ 0xc1, 0xcf, 0xe5, 0xa1, 0x9d, 0xbf, 0x3f, 0x5d, 0x49, 0xd0, 0xbf, 0x68, ++ 0xcf, 0xab, 0x30, 0xd3, 0xed, 0x17, 0x82, 0xdf, 0x05, 0xff, 0x0b, 0x7d, ++ 0xe8, 0x6e, 0x77, 0xf8, 0x53, 0xf0, 0xf9, 0x78, 0x5a, 0x96, 0x12, 0x13, ++ 0xfd, 0x9a, 0x0f, 0x49, 0xec, 0x39, 0xc0, 0x03, 0x5d, 0x3d, 0xca, 0x9f, ++ 0x16, 0xea, 0x42, 0xff, 0x4e, 0xc8, 0x55, 0x6d, 0xe4, 0xd8, 0x8c, 0x21, ++ 0x10, 0x47, 0xad, 0x0c, 0x57, 0x28, 0xb6, 0xfd, 0xfa, 0x7d, 0xce, 0x77, ++ 0x0b, 0x74, 0xeb, 0x97, 0xd0, 0x7f, 0xde, 0xf5, 0x0b, 0xda, 0xf3, 0x29, ++ 0x1e, 0xc6, 0xdd, 0x4d, 0x22, 0xa0, 0x66, 0xaf, 0xbd, 0x7e, 0x01, 0xb1, ++ 0xf3, 0xfb, 0xaf, 0xfb, 0xda, 0x47, 0x5f, 0x42, 0xf9, 0xba, 0xbb, 0x1b, ++ 0xdd, 0xd2, 0x81, 0xfa, 0x75, 0xf3, 0xf5, 0x5d, 0x2d, 0x45, 0x5f, 0xb3, ++ 0xf3, 0x21, 0x1d, 0xe7, 0x75, 0x1c, 0xa7, 0xa4, 0x3b, 0x2e, 0xdb, 0xf4, ++ 0x4e, 0x0e, 0xc7, 0xb3, 0x32, 0xb3, 0x8f, 0x3f, 0x4d, 0x10, 0xcd, 0x9a, ++ 0xdb, 0x12, 0x2a, 0xd0, 0xa7, 0xa2, 0x36, 0xa2, 0x48, 0xb6, 0x75, 0x5c, ++ 0x5b, 0xe7, 0xb4, 0xe7, 0x29, 0xbf, 0xbf, 0x03, 0xe3, 0xba, 0xf9, 0x74, ++ 0x1e, 0x69, 0xf6, 0x90, 0xf3, 0xd8, 0x3f, 0x46, 0x49, 0xb1, 0x5e, 0x80, ++ 0xb7, 0xb6, 0xa4, 0xbb, 0x0d, 0xe0, 0xd3, 0x42, 0x51, 0xf4, 0xf7, 0x28, ++ 0xdc, 0xa7, 0xe1, 0xf9, 0x17, 0x00, 0xf7, 0x27, 0xe7, 0x82, 0xfb, 0x1d, ++ 0x88, 0x75, 0x80, 0xde, 0x8c, 0x54, 0x5b, 0x43, 0xc2, 0x08, 0x9f, 0xaa, ++ 0x5c, 0x02, 0x7e, 0x54, 0xaa, 0x2d, 0x3f, 0x0c, 0x78, 0x3f, 0xa6, 0x02, ++ 0xde, 0x29, 0x9e, 0x35, 0xc5, 0x86, 0xe7, 0xc1, 0xca, 0xf9, 0xfd, 0x7c, ++ 0xbf, 0x18, 0x48, 0xde, 0xdb, 0xe0, 0x0f, 0xb4, 0x97, 0x63, 0x79, 0x0a, ++ 0x6d, 0x3f, 0x44, 0x67, 0x72, 0x4a, 0x7a, 0x8e, 0x11, 0xe6, 0x77, 0x39, ++ 0xe3, 0x97, 0xc2, 0x6e, 0x0e, 0x86, 0x08, 0xc6, 0x59, 0x73, 0x6a, 0x7b, ++ 0x08, 0xf8, 0x6b, 0x17, 0x1f, 0x55, 0xd0, 0xde, 0x1d, 0x5a, 0x4b, 0x24, ++ 0xb0, 0xc3, 0x84, 0x5d, 0x3b, 0xc4, 0x75, 0xde, 0xb0, 0x01, 0xec, 0x66, ++ 0x2a, 0x3f, 0xf7, 0xb5, 0x84, 0x50, 0x88, 0x2e, 0x36, 0x7a, 0x8f, 0xc2, ++ 0x39, 0xc0, 0x86, 0x42, 0x99, 0xd9, 0xc7, 0x53, 0xce, 0x0c, 0x83, 0xfe, ++ 0x3f, 0xaa, 0xee, 0x09, 0x81, 0x3f, 0x68, 0x56, 0x9d, 0x59, 0x77, 0x53, ++ 0x18, 0xec, 0xed, 0x30, 0xb6, 0x5f, 0xdb, 0x12, 0xe1, 0xfb, 0x4f, 0x15, ++ 0x96, 0x89, 0xda, 0xb7, 0xf6, 0xec, 0xa4, 0xf3, 0x6f, 0x08, 0xf9, 0xd1, ++ 0x5e, 0xbe, 0xb7, 0xa5, 0x4c, 0xc4, 0x6b, 0x11, 0xee, 0x21, 0x22, 0xde, ++ 0x5b, 0xcb, 0xec, 0x7b, 0x11, 0x17, 0x16, 0x70, 0xd1, 0xfe, 0x3a, 0x0f, ++ 0xb6, 0x3a, 0xda, 0x93, 0x90, 0x0d, 0x6f, 0xc5, 0xb6, 0xfe, 0x61, 0xa6, ++ 0x6f, 0x06, 0xea, 0x9f, 0x55, 0xe9, 0xc4, 0x7b, 0x5f, 0x7f, 0x6b, 0x70, ++ 0xfd, 0x21, 0xde, 0x6f, 0xef, 0x5f, 0x6d, 0xf5, 0x1c, 0x85, 0xf8, 0x9c, ++ 0xc9, 0xe3, 0xfe, 0x42, 0xef, 0x05, 0x79, 0x1b, 0xb3, 0x4a, 0x46, 0xff, ++ 0x59, 0xe0, 0xd9, 0x5b, 0xe6, 0x8c, 0xcb, 0x25, 0xf8, 0xfc, 0x99, 0xf8, ++ 0xc5, 0x3d, 0x1f, 0x09, 0xfb, 0x1d, 0xeb, 0x27, 0xf1, 0x06, 0x84, 0x6f, ++ 0x05, 0x97, 0x8b, 0x4c, 0xe3, 0xb4, 0x73, 0xfd, 0x28, 0xea, 0x1e, 0x92, ++ 0xde, 0x6e, 0x5b, 0xa6, 0xf0, 0x7d, 0x92, 0x9f, 0x4b, 0x99, 0x7c, 0xae, ++ 0x1f, 0x59, 0x4e, 0x7c, 0x5c, 0x2c, 0xe8, 0x77, 0x90, 0xe3, 0xcf, 0x64, ++ 0xf2, 0x2e, 0xfc, 0x1a, 0x8c, 0x07, 0x28, 0xf6, 0xf9, 0xd8, 0x3a, 0xb0, ++ 0x8e, 0x71, 0x9a, 0x38, 0xd3, 0xc7, 0x2e, 0xf8, 0x45, 0x7f, 0x8d, 0xf7, ++ 0xcf, 0x04, 0x87, 0xe6, 0x1e, 0xef, 0x38, 0x1d, 0x67, 0xb2, 0x6d, 0x1c, ++ 0x17, 0x9c, 0x99, 0xe0, 0x73, 0x9f, 0x93, 0x91, 0x77, 0x9c, 0xe3, 0x64, ++ 0xd6, 0x5f, 0xae, 0x7e, 0x27, 0x07, 0x47, 0x87, 0xb3, 0xfa, 0x11, 0x9b, ++ 0xdc, 0x63, 0x3d, 0xd7, 0x55, 0x1f, 0xe6, 0x6a, 0x5f, 0xec, 0x7a, 0x7f, ++ 0x81, 0xeb, 0x7d, 0x85, 0xab, 0x7e, 0x99, 0xab, 0xfd, 0x34, 0x57, 0xfd, ++ 0xab, 0xae, 0xf6, 0x73, 0x5d, 0xf5, 0xeb, 0x5c, 0xed, 0x17, 0xba, 0xde, ++ 0x2f, 0x71, 0xbd, 0x5f, 0xe1, 0xaa, 0xff, 0x57, 0x67, 0xfb, 0xf2, 0xc5, ++ 0x9f, 0x0e, 0xbf, 0xff, 0x9f, 0xe1, 0x49, 0xc8, 0xd5, 0xd9, 0x78, 0x49, ++ 0x3a, 0xce, 0x79, 0xdd, 0x72, 0x55, 0x4c, 0x52, 0xa3, 0x52, 0xb4, 0xdc, ++ 0x91, 0xf3, 0xe2, 0x22, 0x78, 0xd5, 0xa3, 0x48, 0xea, 0x09, 0x98, 0x47, ++ 0xc4, 0xb7, 0x48, 0x6a, 0x82, 0xdd, 0x8f, 0xfd, 0xbd, 0x11, 0xfb, 0x1d, ++ 0xec, 0x63, 0x3b, 0x3e, 0xb6, 0xfc, 0x51, 0x2a, 0x57, 0xbb, 0x12, 0x2f, ++ 0x05, 0x61, 0x7f, 0x13, 0xcf, 0x4f, 0x4a, 0x6f, 0x04, 0xc7, 0x87, 0xa9, ++ 0x7d, 0xa8, 0xa5, 0x96, 0xb3, 0x78, 0x50, 0x02, 0xe5, 0xc6, 0x4f, 0xd4, ++ 0xb7, 0x7a, 0xca, 0x80, 0x4a, 0x12, 0xc6, 0xd1, 0x74, 0xa3, 0x1e, 0x51, ++ 0xae, 0x97, 0xd0, 0xe7, 0x36, 0x7d, 0xe5, 0x25, 0x51, 0xa4, 0xb3, 0x36, ++ 0xc2, 0xf9, 0x9c, 0x24, 0x98, 0x1c, 0x96, 0x40, 0x80, 0x8a, 0x8e, 0x17, ++ 0xdf, 0xa4, 0xa1, 0xbd, 0x17, 0x1f, 0x49, 0x92, 0x63, 0x41, 0x9e, 0xf3, ++ 0xd8, 0xf8, 0xd8, 0xbe, 0xb8, 0x1f, 0xde, 0x49, 0x2a, 0xd3, 0x4f, 0xa1, ++ 0x68, 0xa2, 0x1a, 0x64, 0x78, 0x58, 0x5d, 0xd7, 0x61, 0x28, 0xdd, 0x78, ++ 0x0a, 0x4d, 0x8f, 0x4f, 0x7c, 0x9e, 0xea, 0x65, 0xf2, 0x00, 0xf3, 0xcb, ++ 0x77, 0xcd, 0x74, 0xfa, 0xd5, 0xd7, 0xf1, 0x71, 0xe6, 0xab, 0xe7, 0xed, ++ 0xa7, 0xbe, 0x32, 0x49, 0xe9, 0x1f, 0x7f, 0xd7, 0xb7, 0x8d, 0x48, 0x2b, ++ 0x6d, 0xb2, 0x0b, 0x80, 0xa0, 0xf5, 0xf8, 0xb7, 0xf5, 0x24, 0xc4, 0x37, ++ 0x46, 0x41, 0xbc, 0x8e, 0x1d, 0x22, 0x60, 0xbc, 0x6e, 0x24, 0xe1, 0xff, ++ 0x78, 0x5c, 0x6e, 0x04, 0xfc, 0x4d, 0xfb, 0x8d, 0x34, 0x8e, 0x62, 0xfc, ++ 0x2d, 0xdc, 0x60, 0x1e, 0x01, 0x9d, 0xf7, 0x75, 0xb5, 0x14, 0xe1, 0x7a, ++ 0x44, 0xea, 0x1d, 0x0f, 0xf3, 0xc9, 0x59, 0x27, 0x27, 0xb2, 0xf3, 0xbd, ++ 0xbf, 0x7e, 0x82, 0xf1, 0x78, 0x8e, 0xaf, 0xd0, 0xbd, 0x93, 0x7b, 0xe2, ++ 0x10, 0x4f, 0xd9, 0xa8, 0x45, 0xc6, 0x22, 0x9e, 0x23, 0x88, 0x67, 0xea, ++ 0x8f, 0xb7, 0x79, 0x2b, 0x80, 0x4d, 0x18, 0x7e, 0x57, 0xc1, 0xee, 0xcb, ++ 0x9e, 0xab, 0x81, 0x5c, 0x38, 0x77, 0xe1, 0xf4, 0x00, 0xfd, 0x4b, 0x4b, ++ 0x1f, 0xf0, 0x13, 0xec, 0x8b, 0x24, 0x85, 0xf5, 0x00, 0xe9, 0xc1, 0x7a, ++ 0x36, 0xb7, 0x73, 0xcb, 0xd4, 0x22, 0x5c, 0x7f, 0x0e, 0xf7, 0x33, 0x09, ++ 0x89, 0x48, 0x60, 0x7f, 0x84, 0xae, 0x4c, 0xef, 0x97, 0x47, 0xa5, 0xea, ++ 0x32, 0xf5, 0x92, 0xfe, 0xb8, 0xa5, 0x14, 0x66, 0xf1, 0x49, 0x69, 0xfd, ++ 0xf3, 0x7f, 0x96, 0x20, 0xae, 0x55, 0x46, 0xc2, 0xcc, 0x7e, 0xe1, 0x71, ++ 0xc2, 0xb5, 0x8a, 0xf4, 0x09, 0xc4, 0x5f, 0xcd, 0xc1, 0xd9, 0x8b, 0xa1, ++ 0x6f, 0x3a, 0xe9, 0x4a, 0xd4, 0x66, 0x32, 0xc7, 0xe6, 0x5f, 0x5e, 0xaf, ++ 0x0a, 0x3f, 0x8f, 0xe1, 0x6b, 0x4c, 0x88, 0xad, 0x3f, 0xb4, 0x51, 0x6b, ++ 0x06, 0xbf, 0x66, 0xd7, 0x6c, 0x27, 0x1f, 0x88, 0xf6, 0xea, 0xf9, 0xf3, ++ 0xc1, 0xe6, 0x09, 0x63, 0xbe, 0x38, 0x3e, 0xc8, 0x55, 0xc7, 0x64, 0xe0, ++ 0x83, 0xeb, 0x4d, 0x88, 0x57, 0x4b, 0x71, 0x8a, 0xb7, 0xac, 0xc1, 0xe3, ++ 0xcd, 0x54, 0xac, 0x6f, 0xaa, 0xb8, 0x4e, 0x82, 0xe3, 0xfe, 0x40, 0xb2, ++ 0x6e, 0xb0, 0xd7, 0x55, 0x62, 0xdd, 0xa8, 0xe6, 0xf7, 0xd7, 0x7f, 0xad, ++ 0x44, 0x17, 0xc2, 0xfb, 0xf8, 0x34, 0x52, 0xd6, 0x6c, 0xf4, 0x8f, 0x43, ++ 0x9f, 0xdf, 0x0c, 0xed, 0xd2, 0x3c, 0x6f, 0x48, 0xd7, 0x7e, 0x1c, 0x8f, ++ 0xdb, 0xd2, 0xfd, 0x19, 0xf7, 0xf1, 0x52, 0xae, 0x03, 0x86, 0x6e, 0x33, ++ 0x65, 0xb0, 0x27, 0x8b, 0x3a, 0x57, 0xf8, 0xed, 0x79, 0x2e, 0xa5, 0x7c, ++ 0xbf, 0x7e, 0xac, 0x73, 0x9f, 0x0f, 0xd6, 0xbb, 0xb5, 0xf1, 0xdc, 0xf6, ++ 0xd1, 0x7d, 0x2d, 0xc8, 0xfc, 0x19, 0xdb, 0x05, 0xa5, 0xee, 0x28, 0xd0, ++ 0x83, 0x5c, 0xa2, 0x92, 0xdd, 0x69, 0xce, 0xb1, 0x7f, 0xca, 0xf9, 0xbb, ++ 0xaf, 0xbd, 0xcb, 0x3e, 0x9c, 0xd1, 0x16, 0xaf, 0x86, 0xfe, 0xb9, 0x75, ++ 0x32, 0x81, 0x78, 0x34, 0xdd, 0xe7, 0xd1, 0xbe, 0x2b, 0xe2, 0x7e, 0xed, ++ 0xe6, 0xa9, 0x71, 0x49, 0xa3, 0x72, 0xf8, 0xc0, 0x16, 0x82, 0x76, 0x72, ++ 0x6e, 0xdb, 0x42, 0x9f, 0x7d, 0x3d, 0x85, 0x7c, 0x3d, 0x9b, 0x6b, 0x0b, ++ 0xfc, 0x60, 0xb7, 0x6c, 0xaf, 0x5f, 0xf8, 0x55, 0xf4, 0x13, 0xa8, 0xfd, ++ 0xaf, 0xa0, 0xdf, 0x1b, 0x5b, 0x07, 0xe3, 0x17, 0xd6, 0xb0, 0xf3, 0x7e, ++ 0x37, 0x7c, 0xf7, 0xf2, 0xf5, 0x25, 0xea, 0x19, 0x9e, 0xdc, 0xef, 0xb3, ++ 0x34, 0x12, 0x4b, 0x27, 0x87, 0x3f, 0x55, 0xf9, 0xf9, 0x83, 0x4a, 0xdd, ++ 0xc7, 0x82, 0xfe, 0x73, 0x94, 0x7b, 0x0f, 0xdf, 0xf9, 0x8b, 0xf1, 0x74, ++ 0xbe, 0xd2, 0x2a, 0x39, 0xe2, 0x0b, 0xf7, 0xc3, 0x39, 0xae, 0xcf, 0x6e, ++ 0xea, 0x41, 0x7c, 0x65, 0x5d, 0xa6, 0x9a, 0xeb, 0x40, 0x0f, 0x77, 0x6a, ++ 0x0e, 0x7b, 0x73, 0xfb, 0xb6, 0xfb, 0xb7, 0xd4, 0xc3, 0xb9, 0x1f, 0x7d, ++ 0x0e, 0xea, 0xe0, 0xd1, 0x2f, 0x37, 0x0f, 0x8b, 0x52, 0xb8, 0x1e, 0xfb, ++ 0xda, 0xa2, 0x17, 0x16, 0x03, 0xdf, 0xb7, 0xcb, 0x04, 0xf4, 0x91, 0x80, ++ 0xc3, 0x28, 0x77, 0xda, 0xbb, 0x47, 0xfa, 0xe4, 0xcc, 0x39, 0x2f, 0x1d, ++ 0xb7, 0x1a, 0xf1, 0x52, 0x7f, 0x6e, 0xff, 0xe9, 0xd3, 0xe2, 0x63, 0x0b, ++ 0x97, 0xf3, 0x4c, 0x7c, 0xe2, 0xde, 0x57, 0xdd, 0x7c, 0x70, 0x3e, 0xfb, ++ 0xc3, 0x55, 0xca, 0x67, 0x5f, 0xdf, 0x7e, 0x90, 0x43, 0x3a, 0x6e, 0x01, ++ 0xf7, 0xfb, 0x86, 0xd6, 0x85, 0xa5, 0x1e, 0xa3, 0x5f, 0x8e, 0x84, 0x9f, ++ 0x22, 0xe6, 0x29, 0xe0, 0x7c, 0x96, 0x5b, 0x7b, 0xbf, 0x0f, 0xf8, 0x6c, ++ 0x4b, 0x5d, 0x05, 0xca, 0xcf, 0xe9, 0xda, 0x85, 0x12, 0xe8, 0x93, 0x4d, ++ 0xd0, 0x32, 0x8d, 0x9e, 0x10, 0xf3, 0x65, 0x82, 0x27, 0xcb, 0x93, 0xc0, ++ 0x7c, 0x89, 0x2d, 0xf5, 0xf7, 0x4b, 0xe9, 0xf0, 0x56, 0x18, 0x63, 0xf1, ++ 0x22, 0xf7, 0xf3, 0x6a, 0x0f, 0xa3, 0xf3, 0x7a, 0x35, 0x21, 0x41, 0xff, ++ 0x4c, 0xed, 0x46, 0x7b, 0xb8, 0xbe, 0xe6, 0x72, 0x55, 0xc8, 0xd7, 0x15, ++ 0x9a, 0x9a, 0x8a, 0x02, 0xbe, 0x0a, 0x22, 0x2a, 0xb9, 0x87, 0xe2, 0xeb, ++ 0x81, 0xda, 0x85, 0xd5, 0xa5, 0xc0, 0x77, 0x54, 0x0e, 0x21, 0xbe, 0x32, ++ 0xa3, 0x86, 0xa0, 0xbd, 0x50, 0x68, 0xb1, 0x73, 0x22, 0x93, 0xe2, 0xeb, ++ 0x69, 0xba, 0xef, 0x6d, 0xae, 0x27, 0x91, 0x14, 0x6d, 0xb7, 0xd9, 0xd2, ++ 0xf0, 0x1c, 0xc6, 0x2d, 0x87, 0x6e, 0x7e, 0xdc, 0x5c, 0x7f, 0x6e, 0xfd, ++ 0x42, 0x2c, 0x5b, 0x7b, 0xca, 0xff, 0x1e, 0x8f, 0xc1, 0xce, 0x73, 0x4b, ++ 0x48, 0x09, 0xd8, 0x53, 0x0f, 0x0c, 0xe0, 0xbf, 0x0d, 0x16, 0xbf, 0xa1, ++ 0x7a, 0x99, 0xc5, 0x4b, 0x67, 0x54, 0x0c, 0xa0, 0xcf, 0x5b, 0xcf, 0x37, ++ 0x8e, 0x39, 0xef, 0xcb, 0xc0, 0x8f, 0x33, 0x06, 0x99, 0x07, 0xe0, 0xd2, ++ 0x17, 0xe4, 0xd9, 0x2d, 0xb3, 0x4b, 0xf3, 0x20, 0x1e, 0x42, 0xf5, 0x05, ++ 0x49, 0x87, 0x1f, 0xa7, 0x7e, 0x18, 0x08, 0x1f, 0x6e, 0xfc, 0x5f, 0x0c, ++ 0xf8, 0xbc, 0xf0, 0x8b, 0xc3, 0xa7, 0xfb, 0x7d, 0x9e, 0x87, 0xc7, 0x01, ++ 0x07, 0x89, 0x8f, 0xf5, 0x75, 0xc5, 0xff, 0x03, 0x52, 0x26, 0x33, 0xb5, ++ 0x77, 0xaf, 0x47, 0xf4, 0x13, 0x79, 0x61, 0x5f, 0x21, 0xbd, 0x0a, 0xc8, ++ 0xbf, 0x05, 0x1c, 0x3a, 0x06, 0xbc, 0x8a, 0x08, 0x96, 0x33, 0x48, 0x14, ++ 0xcb, 0x63, 0x6a, 0x2c, 0xea, 0xa1, 0xed, 0x67, 0x91, 0x66, 0xac, 0xd7, ++ 0x90, 0x04, 0x96, 0x8b, 0x55, 0x93, 0xd1, 0x99, 0xe7, 0xc1, 0x88, 0xf3, ++ 0x6e, 0x75, 0x3a, 0xe3, 0xfb, 0x71, 0x97, 0x92, 0x24, 0x9c, 0x3b, 0x93, ++ 0xa9, 0x73, 0xf9, 0x61, 0xb0, 0x6a, 0x9d, 0xd0, 0x09, 0x86, 0x52, 0x3f, ++ 0x49, 0xe3, 0x57, 0x11, 0x72, 0x0f, 0x8e, 0x37, 0xdc, 0xb5, 0x1f, 0x8b, ++ 0x38, 0xc5, 0xd0, 0xc6, 0x44, 0x6d, 0x05, 0x1d, 0x77, 0x78, 0x2d, 0xcb, ++ 0xfb, 0x1c, 0x5e, 0xb5, 0xcf, 0xb1, 0x8f, 0x05, 0xb9, 0xfc, 0x88, 0xf1, ++ 0xb6, 0x56, 0x0d, 0x6e, 0x7f, 0x7e, 0xd4, 0xb5, 0x3f, 0x3f, 0xaa, 0xf6, ++ 0xe8, 0x40, 0x9f, 0x47, 0xab, 0xee, 0x69, 0x85, 0xed, 0x46, 0xcd, 0x7d, ++ 0x27, 0x94, 0xae, 0xff, 0xb8, 0x4e, 0x27, 0x5e, 0x37, 0x7c, 0xdc, 0xe5, ++ 0x8b, 0xa6, 0x81, 0x67, 0x6b, 0xfd, 0x01, 0x1f, 0xe4, 0x8d, 0x6d, 0xad, ++ 0x4a, 0x9f, 0x17, 0xeb, 0x86, 0x23, 0xd3, 0xfb, 0x71, 0x19, 0xce, 0x99, ++ 0xbe, 0xe2, 0x65, 0xe7, 0x4c, 0x5b, 0x73, 0xf4, 0x6f, 0xb0, 0x64, 0x9d, ++ 0x95, 0x8e, 0xbc, 0x04, 0xa2, 0x18, 0x45, 0xf6, 0x79, 0xb7, 0x7e, 0x4c, ++ 0x72, 0xa2, 0xe7, 0xd4, 0x27, 0x4e, 0x79, 0xd9, 0xe8, 0xe1, 0xf9, 0x21, ++ 0x01, 0x12, 0x00, 0xfe, 0xcf, 0x84, 0x0f, 0x51, 0x7e, 0xd1, 0x78, 0x78, ++ 0x6c, 0x5a, 0xf3, 0x92, 0x68, 0x9a, 0xfe, 0xa5, 0x5e, 0x26, 0x37, 0xed, ++ 0x39, 0x24, 0x0e, 0xe7, 0xd2, 0x8f, 0xbd, 0xa6, 0x32, 0xfe, 0xe3, 0x7a, ++ 0x78, 0xf2, 0x37, 0xc2, 0x49, 0xb0, 0x17, 0xda, 0x41, 0x49, 0x50, 0xfd, ++ 0xfb, 0x58, 0x35, 0xe3, 0xcf, 0xc9, 0x39, 0xfc, 0xfd, 0x43, 0x61, 0xcc, ++ 0xaf, 0x1a, 0xde, 0x49, 0xe2, 0x1a, 0xdd, 0xcf, 0x86, 0xbf, 0x5a, 0xff, ++ 0x40, 0x0e, 0x6d, 0x77, 0x5f, 0x3d, 0xf5, 0x20, 0x6d, 0xcf, 0xef, 0xab, ++ 0x7c, 0xa9, 0x03, 0xce, 0x89, 0x9f, 0x7a, 0x59, 0xc6, 0xb8, 0xee, 0x64, ++ 0x5f, 0xb7, 0x1e, 0xa1, 0xf0, 0x54, 0xf1, 0x7d, 0x70, 0x6b, 0xfd, 0x4b, ++ 0x98, 0x9f, 0x1c, 0xdf, 0xa6, 0x46, 0xc6, 0xa2, 0x7e, 0x97, 0x88, 0x34, ++ 0x19, 0xbd, 0x79, 0xa4, 0x87, 0x80, 0xf7, 0x19, 0x8f, 0xca, 0xe8, 0x56, ++ 0x79, 0xbf, 0x2f, 0x0c, 0xfb, 0x57, 0xb8, 0x47, 0x8f, 0x50, 0xfc, 0xdc, ++ 0x3e, 0xe5, 0x25, 0x3d, 0x4c, 0xcb, 0xfb, 0x46, 0xa4, 0x74, 0x58, 0xe7, ++ 0xfa, 0xaa, 0xfb, 0x91, 0xcf, 0xf7, 0xd5, 0x17, 0x7f, 0xbd, 0x14, 0xd1, ++ 0xea, 0xcc, 0x3b, 0x99, 0xa5, 0x4c, 0xed, 0xb6, 0xe8, 0x7c, 0xeb, 0xeb, ++ 0xd9, 0xb9, 0x5d, 0x4e, 0x4f, 0x4a, 0xf7, 0x42, 0x9c, 0xb5, 0x4e, 0x25, ++ 0x57, 0x50, 0xf8, 0x82, 0x06, 0x5b, 0xef, 0x7d, 0xed, 0x24, 0x79, 0x8f, ++ 0x04, 0x70, 0x30, 0xfa, 0x4a, 0x64, 0x0e, 0xfa, 0xc5, 0x85, 0xae, 0xbc, ++ 0xae, 0x02, 0x57, 0xde, 0x9b, 0x59, 0x39, 0xeb, 0x5d, 0xc8, 0x67, 0x31, ++ 0xe1, 0x9c, 0x1f, 0x16, 0xa1, 0x34, 0x3e, 0x70, 0x11, 0xe8, 0xdb, 0x26, ++ 0x99, 0xb9, 0x5b, 0xae, 0xfc, 0x68, 0xa3, 0xd2, 0x7a, 0x17, 0xf2, 0x03, ++ 0x66, 0x29, 0x07, 0x7d, 0x90, 0x7f, 0xb5, 0xa5, 0x4d, 0x35, 0x71, 0xff, ++ 0x73, 0x8d, 0xeb, 0x5e, 0x87, 0x49, 0x62, 0x87, 0x2d, 0x09, 0xc7, 0x89, ++ 0x83, 0x1f, 0xb8, 0xe5, 0x41, 0xb6, 0x4f, 0x9a, 0x13, 0x8d, 0x48, 0x3c, ++ 0x0c, 0x5d, 0x39, 0xdc, 0x26, 0x85, 0x7b, 0x08, 0x9d, 0xb2, 0xcd, 0x09, ++ 0xb7, 0xc0, 0xab, 0x7b, 0x1e, 0x77, 0xde, 0xf5, 0xbb, 0x82, 0x9f, 0x87, ++ 0x93, 0xb1, 0xa0, 0x87, 0x44, 0xbc, 0x59, 0xc0, 0xef, 0xe6, 0xdb, 0xbc, ++ 0x8a, 0xe4, 0xfe, 0x97, 0x28, 0x1c, 0x5b, 0x5f, 0x36, 0x70, 0xbf, 0xde, ++ 0x5a, 0xf5, 0xd2, 0x37, 0x9b, 0x60, 0x9f, 0x2f, 0xf3, 0x62, 0xde, 0xc4, ++ 0x57, 0xcf, 0xec, 0x69, 0xfc, 0x11, 0x2d, 0x7f, 0xf9, 0xc7, 0x03, 0x25, ++ 0x50, 0x5e, 0x59, 0xb8, 0xab, 0xb2, 0x89, 0xb6, 0x0b, 0xf0, 0x7c, 0x09, ++ 0x11, 0xcf, 0x2b, 0x80, 0x91, 0xd1, 0x7e, 0xe5, 0x7a, 0x8d, 0xf3, 0x03, ++ 0x29, 0xdf, 0xde, 0xe6, 0xc9, 0xc3, 0x47, 0x98, 0x47, 0x71, 0xdf, 0x11, ++ 0x1f, 0xd2, 0xab, 0xb0, 0x4d, 0x4e, 0xfa, 0x80, 0x3e, 0x6a, 0x8a, 0x00, ++ 0x7f, 0xe5, 0x5d, 0x96, 0x40, 0xbb, 0xe9, 0xbe, 0xeb, 0xba, 0x31, 0xe9, ++ 0x22, 0x50, 0xd7, 0x25, 0xc5, 0x6d, 0x72, 0x16, 0x10, 0xf6, 0x43, 0x63, ++ 0x4c, 0x82, 0xf3, 0xfb, 0x2b, 0xea, 0x12, 0xb3, 0x81, 0x0f, 0x0d, 0x9e, ++ 0x47, 0x68, 0x44, 0x12, 0x68, 0x1f, 0xcd, 0x54, 0x5e, 0xd4, 0x31, 0xce, ++ 0xce, 0xe9, 0x66, 0x72, 0x38, 0x84, 0xdc, 0xb9, 0xe9, 0x52, 0x5a, 0x9f, ++ 0xd2, 0x21, 0x2f, 0x65, 0x78, 0x9b, 0x1a, 0x01, 0x70, 0x87, 0x37, 0x36, ++ 0xcb, 0x20, 0x2f, 0xa5, 0x55, 0x2c, 0x6f, 0xb9, 0xb4, 0xb3, 0x4b, 0xe2, ++ 0x79, 0xc2, 0x98, 0x4f, 0x3f, 0x8e, 0x23, 0x71, 0x5c, 0xb4, 0x81, 0xe5, ++ 0x15, 0x6e, 0x63, 0xf8, 0x17, 0xf9, 0xdf, 0xc1, 0x46, 0x27, 0xdd, 0x4c, ++ 0x9e, 0xa7, 0x49, 0xfd, 0x0c, 0x19, 0xfc, 0xee, 0xa2, 0x4e, 0xd7, 0xfb, ++ 0x68, 0x0d, 0xe6, 0x63, 0xba, 0xe9, 0x5a, 0xac, 0xf1, 0xbc, 0xa8, 0x52, ++ 0x9e, 0x47, 0xc8, 0xf1, 0x30, 0x9c, 0xdb, 0xb3, 0xeb, 0x1b, 0xf9, 0xf9, ++ 0x9c, 0xa1, 0x27, 0xcf, 0x65, 0xcf, 0xee, 0xe3, 0xe7, 0x73, 0x47, 0x61, ++ 0xfd, 0xe3, 0xce, 0x7e, 0x3f, 0x29, 0x83, 0xde, 0xbd, 0x0a, 0xf4, 0x2e, ++ 0xd5, 0x37, 0x8a, 0x9c, 0xea, 0x40, 0xff, 0xed, 0x32, 0x19, 0xfd, 0x37, ++ 0x37, 0x1c, 0x1b, 0x1a, 0x99, 0xbe, 0xdb, 0xa5, 0xc9, 0x0e, 0xfb, 0xfd, ++ 0xb3, 0xce, 0x7f, 0x03, 0xd7, 0xfb, 0x8a, 0xdc, 0xd3, 0x01, 0xeb, 0xfc, ++ 0x5b, 0xcf, 0xdf, 0xd8, 0xb7, 0xfe, 0xbf, 0xcf, 0xfc, 0x77, 0xfd, 0x9d, ++ 0xe7, 0x5f, 0xf7, 0x77, 0xc6, 0xff, 0x96, 0xbf, 0xf3, 0xfa, 0xf7, 0xfc, ++ 0x8d, 0xd7, 0x5f, 0x53, 0x26, 0x39, 0xfc, 0xb3, 0x1d, 0x90, 0x98, 0x42, ++ 0xc7, 0xfb, 0xb1, 0x57, 0xc4, 0xd3, 0x9c, 0x7a, 0x5b, 0x91, 0xd3, 0xfb, ++ 0xd9, 0x6f, 0x69, 0xb2, 0x23, 0x9f, 0x58, 0xe4, 0x29, 0x4e, 0xaf, 0xb3, ++ 0x16, 0x68, 0x78, 0x3e, 0x2e, 0x13, 0x7b, 0xfe, 0x8b, 0x18, 0x6f, 0xa6, ++ 0xf2, 0x46, 0x07, 0xe8, 0xd3, 0x2d, 0x5c, 0x9f, 0x52, 0x3d, 0x4a, 0x20, ++ 0x5f, 0x20, 0x7b, 0x8a, 0xc8, 0x97, 0x61, 0xfa, 0xaf, 0x86, 0xeb, 0xbf, ++ 0x1a, 0xae, 0xff, 0xf6, 0x65, 0xd0, 0xab, 0x15, 0x90, 0x2b, 0x96, 0x87, ++ 0x76, 0x05, 0xde, 0x07, 0x99, 0x44, 0x12, 0xe8, 0xc7, 0x04, 0x8f, 0xaa, ++ 0x98, 0x67, 0xbc, 0x8f, 0xd0, 0xed, 0x05, 0xf4, 0x5a, 0xd8, 0x9b, 0x36, ++ 0x2f, 0xbb, 0x80, 0xc3, 0xed, 0xd6, 0xa7, 0x05, 0x5c, 0x9f, 0x56, 0xbc, ++ 0xe8, 0x7a, 0xce, 0xf5, 0xa8, 0x7b, 0x7f, 0x2f, 0xea, 0x8b, 0x9b, 0x12, ++ 0x8c, 0x9b, 0xfe, 0x77, 0x8d, 0xef, 0x8f, 0x2e, 0xbd, 0x2a, 0xf0, 0xb0, ++ 0xa5, 0x8a, 0xd9, 0xc9, 0x79, 0x73, 0xd3, 0xdb, 0x81, 0xeb, 0x5d, 0x74, ++ 0x34, 0x2a, 0x9b, 0x31, 0xff, 0xc0, 0x4d, 0x8f, 0xb7, 0x34, 0xe6, 0x7f, ++ 0x0b, 0x7a, 0x2c, 0xd0, 0xad, 0xd7, 0xb5, 0xfc, 0xcc, 0xf4, 0xee, 0xe1, ++ 0xf4, 0xbe, 0x9c, 0xd3, 0xfb, 0x57, 0x1a, 0xf3, 0x3f, 0x44, 0xbe, 0x48, ++ 0x26, 0x7a, 0x57, 0x79, 0xd9, 0x3c, 0x97, 0x06, 0x8e, 0x87, 0x5a, 0x61, ++ 0x35, 0xd1, 0x6a, 0xa4, 0x83, 0xc2, 0xe9, 0xa4, 0x90, 0xf5, 0xdd, 0x18, ++ 0xf7, 0x25, 0xb7, 0x13, 0xbb, 0x5f, 0xb9, 0xe1, 0x63, 0x6a, 0x7f, 0x50, ++ 0x7a, 0x6c, 0x35, 0x8c, 0xc8, 0x3d, 0xb4, 0x7e, 0x69, 0x1e, 0x91, 0x45, ++ 0xd2, 0xfd, 0xc7, 0x93, 0xfb, 0xf3, 0x89, 0x3d, 0xdd, 0x2c, 0x7e, 0xaa, ++ 0xe4, 0x69, 0x2e, 0x3f, 0xcb, 0x6d, 0xff, 0xea, 0x98, 0x37, 0xbe, 0xd5, ++ 0x92, 0x93, 0xf1, 0x22, 0xb0, 0x23, 0x76, 0x6c, 0x5d, 0x0e, 0x76, 0xc4, ++ 0xcb, 0xfe, 0x08, 0xc4, 0x0b, 0xb6, 0xe6, 0x74, 0xbe, 0x88, 0x7e, 0x5c, ++ 0x62, 0x92, 0x0a, 0x70, 0x08, 0x7b, 0x91, 0xf0, 0xb8, 0x2c, 0x98, 0x12, ++ 0x04, 0xed, 0x26, 0xf7, 0xb9, 0x93, 0xd3, 0xde, 0xdf, 0xfa, 0x71, 0x57, ++ 0x0a, 0xec, 0x2e, 0xb3, 0x48, 0xc2, 0x78, 0x5f, 0x47, 0xf8, 0xfe, 0xbc, ++ 0xb4, 0xf7, 0xf1, 0x5c, 0x76, 0xbe, 0xe1, 0x0d, 0x38, 0xe2, 0x06, 0xe4, ++ 0x8a, 0xc1, 0xd9, 0xeb, 0xab, 0x38, 0xbd, 0xa9, 0x9f, 0x98, 0xef, 0xb5, ++ 0xc5, 0x29, 0x57, 0x05, 0x66, 0x4d, 0x62, 0xe7, 0xe6, 0x33, 0x4c, 0x38, ++ 0xdf, 0x91, 0xac, 0x59, 0x32, 0xc4, 0xd1, 0x33, 0x8d, 0x03, 0x11, 0xde, ++ 0x13, 0xb6, 0xf3, 0xa6, 0xc5, 0xaa, 0x35, 0x12, 0xc6, 0x93, 0xc0, 0x6f, ++ 0x2c, 0xeb, 0xf7, 0x1b, 0x09, 0x19, 0xc1, 0xe2, 0xf2, 0x62, 0xfd, 0x83, ++ 0xbd, 0x3f, 0xd0, 0xb8, 0x98, 0x9d, 0x7b, 0x73, 0xbc, 0xe6, 0x5d, 0xd6, ++ 0xf5, 0xb9, 0xf8, 0x8f, 0xc2, 0xdf, 0x17, 0xed, 0x0c, 0x6a, 0xaf, 0xa5, ++ 0xbb, 0xbf, 0xe3, 0xf6, 0xc3, 0x6b, 0x3c, 0xd6, 0x14, 0xef, 0x25, 0x83, ++ 0x87, 0xff, 0x11, 0x60, 0x38, 0xda, 0xfe, 0x85, 0x72, 0xa5, 0x26, 0x5d, ++ 0xdc, 0xa0, 0x87, 0xeb, 0xd7, 0xc0, 0xd1, 0xae, 0xd9, 0x73, 0xe9, 0xfa, ++ 0x2a, 0x5f, 0xe4, 0x71, 0x7d, 0x6a, 0xb6, 0xd9, 0xcf, 0xd3, 0xee, 0xcb, ++ 0x53, 0xd3, 0xf6, 0xff, 0x39, 0x97, 0x93, 0x5f, 0xc1, 0xe5, 0x48, 0xd4, ++ 0xeb, 0xa9, 0x78, 0xbe, 0x84, 0xf9, 0x24, 0x04, 0xd6, 0x25, 0xe4, 0xd1, ++ 0x3d, 0xff, 0x44, 0x3e, 0xef, 0xc4, 0xcf, 0x38, 0xff, 0xcb, 0x5c, 0xae, ++ 0x27, 0x72, 0xb9, 0x26, 0x24, 0x82, 0xe7, 0x30, 0x99, 0xe6, 0xad, 0xe6, ++ 0x7a, 0x43, 0x94, 0x9f, 0x76, 0xde, 0x1e, 0xbe, 0xee, 0x6a, 0xcd, 0xe4, ++ 0x71, 0xdf, 0x73, 0xcf, 0x3b, 0x87, 0xaf, 0x73, 0xce, 0x67, 0x5c, 0xef, ++ 0x49, 0x3e, 0xef, 0x9c, 0x41, 0xae, 0x77, 0x01, 0x9f, 0x6f, 0xc1, 0x67, ++ 0x9c, 0xf7, 0x23, 0x3e, 0xef, 0x82, 0x41, 0xce, 0x7b, 0x2b, 0xc7, 0xef, ++ 0xad, 0x9f, 0x11, 0xcf, 0xaa, 0x2e, 0xf1, 0x71, 0x06, 0x87, 0xe7, 0x56, ++ 0x3e, 0x5f, 0xeb, 0x67, 0x9c, 0xd7, 0xe4, 0xf3, 0xb6, 0x0e, 0x72, 0xde, ++ 0x4d, 0x1c, 0xbf, 0x9b, 0x3e, 0x23, 0x9e, 0x47, 0xf0, 0x79, 0x37, 0xb9, ++ 0xf0, 0x9c, 0x49, 0x7e, 0x77, 0x7c, 0xc6, 0xf9, 0xca, 0x74, 0x26, 0x3f, ++ 0xbb, 0xb8, 0xfc, 0xba, 0xf5, 0x9a, 0x98, 0x3f, 0x50, 0x28, 0x47, 0xa1, ++ 0xff, 0xd6, 0x10, 0x1d, 0xc7, 0xa6, 0xa7, 0xae, 0xf4, 0xb2, 0xf9, 0x45, ++ 0x49, 0x52, 0x9f, 0xa0, 0xdf, 0x3a, 0x9c, 0x9f, 0xe7, 0x4e, 0x59, 0x7e, ++ 0xc7, 0xc2, 0x74, 0x79, 0xe1, 0xa2, 0xbd, 0x7b, 0x3f, 0xce, 0x34, 0xcf, ++ 0x37, 0x79, 0x9c, 0x46, 0x94, 0x62, 0x9e, 0x20, 0x3f, 0x07, 0x9d, 0x72, ++ 0x19, 0x9d, 0x27, 0xcd, 0xfa, 0x44, 0xfb, 0x89, 0x70, 0x58, 0x90, 0x9f, ++ 0x79, 0xfc, 0x25, 0x1c, 0x9e, 0x25, 0xe7, 0xb9, 0x0e, 0xd1, 0xbe, 0x5a, ++ 0x63, 0x7a, 0x36, 0xd3, 0xf8, 0x77, 0x72, 0x38, 0xee, 0x74, 0xc1, 0x3f, ++ 0xd0, 0xf8, 0xa2, 0xfd, 0x9c, 0x01, 0xe0, 0xef, 0xe0, 0x70, 0x74, 0x9c, ++ 0x27, 0xfc, 0xa2, 0xfd, 0x82, 0x01, 0xc6, 0xff, 0x2e, 0x87, 0xe3, 0xbb, ++ 0xe7, 0x09, 0xbf, 0x68, 0x7f, 0xeb, 0x00, 0xf8, 0x79, 0x94, 0xc3, 0xf1, ++ 0xe8, 0x79, 0xc2, 0x2f, 0xda, 0xb7, 0x0e, 0x30, 0xfe, 0x93, 0x1c, 0x8e, ++ 0x27, 0xcf, 0x13, 0x7e, 0xd1, 0x7e, 0xd3, 0x00, 0xf8, 0x79, 0x96, 0xc3, ++ 0xf1, 0xec, 0x79, 0xc2, 0x2f, 0xda, 0xef, 0xea, 0x93, 0x77, 0xa7, 0xfc, ++ 0x19, 0xe2, 0xfb, 0x06, 0x11, 0x52, 0x06, 0xf7, 0xbc, 0x47, 0x11, 0x7f, ++ 0x04, 0xbf, 0x6f, 0x10, 0xe9, 0x39, 0x8c, 0xdf, 0x37, 0x58, 0xa9, 0x85, ++ 0xf1, 0xfe, 0x79, 0x97, 0xfb, 0x5e, 0x94, 0xed, 0x3e, 0x15, 0x15, 0xf1, ++ 0xc3, 0x77, 0x96, 0xc6, 0xa1, 0xfd, 0xc3, 0x8b, 0x59, 0x9e, 0xf2, 0xc3, ++ 0x13, 0x09, 0xfa, 0x11, 0x0f, 0xe7, 0xb3, 0xbc, 0xfc, 0xbe, 0x78, 0x16, ++ 0xb7, 0x07, 0x1f, 0x9e, 0x28, 0x63, 0x3c, 0xe9, 0xe1, 0x90, 0x33, 0x8f, ++ 0xd9, 0xe0, 0xfe, 0xd9, 0xc3, 0x11, 0x1e, 0x27, 0x19, 0xc1, 0xf2, 0x98, ++ 0x8d, 0x72, 0x71, 0x9f, 0x96, 0x4e, 0x57, 0xc0, 0x4d, 0xc4, 0x30, 0xe4, ++ 0xd3, 0xb0, 0xfb, 0x55, 0xc2, 0xde, 0x13, 0xf7, 0xac, 0x56, 0xa9, 0x7c, ++ 0x7e, 0x8b, 0x24, 0x5b, 0x69, 0xff, 0x87, 0xcb, 0x59, 0x7d, 0xeb, 0x0c, ++ 0x92, 0x94, 0x8b, 0x6c, 0xf7, 0xaf, 0xca, 0x52, 0x78, 0x0f, 0x08, 0x0c, ++ 0x5b, 0x88, 0xc3, 0xf6, 0xdf, 0x1f, 0xb3, 0xc8, 0xca, 0x0a, 0x5b, 0x1e, ++ 0xc6, 0xca, 0x14, 0xe6, 0x19, 0xa8, 0x3c, 0x5f, 0x84, 0x22, 0x84, 0x38, ++ 0xf2, 0x31, 0x5c, 0xf7, 0xb6, 0xc4, 0xb9, 0xe1, 0x35, 0x11, 0x6b, 0x26, ++ 0xa8, 0xb9, 0xa2, 0x4a, 0x76, 0x8e, 0x57, 0x14, 0x75, 0xfa, 0x0f, 0x8d, ++ 0x70, 0x99, 0x8b, 0xb6, 0xff, 0x2d, 0xd7, 0x93, 0x66, 0x65, 0xfa, 0x7b, ++ 0x35, 0x7b, 0x75, 0x16, 0x97, 0x15, 0xf9, 0x9a, 0x57, 0xf3, 0xf5, 0x0b, ++ 0xbc, 0x55, 0x70, 0x7a, 0x6e, 0x98, 0xf3, 0xc7, 0xee, 0xe9, 0x74, 0x9d, ++ 0x2f, 0x4c, 0xf5, 0x60, 0xfe, 0xe8, 0x0b, 0x47, 0x39, 0x1e, 0xa7, 0x2a, ++ 0x49, 0x76, 0x6e, 0x4e, 0x3c, 0xe9, 0xee, 0xe3, 0x64, 0x8a, 0xb3, 0x19, ++ 0x9d, 0xcd, 0x47, 0x7c, 0x14, 0x3f, 0xd7, 0xbc, 0x48, 0x22, 0x40, 0xc6, ++ 0xc0, 0x36, 0xab, 0x3d, 0x8c, 0x71, 0xb5, 0x8f, 0x91, 0xff, 0x30, 0xae, ++ 0x46, 0xe7, 0xbd, 0x66, 0x5b, 0x42, 0x05, 0xfe, 0x9b, 0xdd, 0x19, 0x9e, ++ 0x0e, 0xf1, 0xc0, 0xab, 0x5f, 0x0c, 0xaf, 0x82, 0xef, 0x0a, 0x8c, 0xeb, ++ 0x24, 0x11, 0x0b, 0xd0, 0xfb, 0xf1, 0xb7, 0x70, 0x9c, 0xdc, 0x36, 0x12, ++ 0x49, 0x32, 0x52, 0xb5, 0x9a, 0x2c, 0xde, 0xe7, 0x8c, 0xcf, 0x89, 0x7b, ++ 0xbf, 0x3c, 0x3e, 0x07, 0x61, 0x6a, 0xbb, 0x7f, 0x39, 0x9b, 0xaf, 0xbb, ++ 0xa2, 0xcd, 0x6c, 0x87, 0x23, 0xbb, 0x8a, 0x19, 0x5e, 0x87, 0xfd, 0x3a, ++ 0x9b, 0xfb, 0x99, 0xff, 0x64, 0x79, 0x1d, 0x7e, 0xe6, 0x6c, 0x7e, 0x7f, ++ 0x7a, 0xb6, 0xcb, 0xcf, 0xec, 0xd4, 0x9d, 0xf1, 0x3a, 0xa3, 0x33, 0x3a, ++ 0x13, 0xe2, 0xdc, 0xca, 0xd5, 0xc7, 0x2c, 0x1d, 0xe0, 0x8f, 0x4a, 0x26, ++ 0x5c, 0x4b, 0xb9, 0x21, 0xba, 0x49, 0x85, 0x73, 0xe4, 0xd9, 0xdb, 0x9a, ++ 0xd9, 0xbd, 0xda, 0x0c, 0xe7, 0x5a, 0xd9, 0x0f, 0xcd, 0x0d, 0xd8, 0xed, ++ 0x77, 0x71, 0x8e, 0xfd, 0xab, 0x6d, 0xe7, 0xb6, 0xd7, 0x45, 0x9c, 0x41, ++ 0xc4, 0x1d, 0x5e, 0xe1, 0xf7, 0xf1, 0x5e, 0xe6, 0x79, 0xc5, 0x7d, 0xf9, ++ 0x28, 0x9c, 0x3f, 0x72, 0xaf, 0x96, 0x1c, 0x7c, 0xd2, 0xa9, 0x33, 0x3d, ++ 0xd2, 0x09, 0x7c, 0x92, 0xff, 0x9f, 0x7c, 0xf2, 0x79, 0xf3, 0xc9, 0x6f, ++ 0x74, 0x67, 0xfc, 0xa1, 0x13, 0xde, 0x51, 0x79, 0x2c, 0x8d, 0xa4, 0x3f, ++ 0x9f, 0x6f, 0xd0, 0xb5, 0xff, 0x94, 0xd7, 0x2f, 0x80, 0x0e, 0x41, 0x5f, ++ 0x7a, 0x3a, 0x90, 0xc6, 0x6c, 0x47, 0x1e, 0xb1, 0xc8, 0xa7, 0x72, 0xe3, ++ 0x6d, 0x0d, 0xc7, 0x9b, 0xa8, 0xeb, 0x19, 0xee, 0xbd, 0x8c, 0xf0, 0xf1, ++ 0x7d, 0xd6, 0xed, 0xd7, 0xbf, 0x11, 0xab, 0x86, 0x75, 0x89, 0x38, 0x0d, ++ 0x21, 0x77, 0xb9, 0xce, 0x35, 0xa7, 0x46, 0xce, 0x15, 0x97, 0x50, 0xc4, ++ 0xb9, 0x8f, 0xfc, 0x86, 0x02, 0xeb, 0x29, 0xf3, 0x71, 0xfd, 0xa3, 0x12, ++ 0x15, 0xc7, 0x77, 0xad, 0x03, 0xe5, 0xbe, 0x00, 0xf2, 0x0d, 0x39, 0x0c, ++ 0xae, 0xf1, 0xda, 0x41, 0x5f, 0x78, 0xfb, 0xd7, 0xe5, 0x29, 0x89, 0x5a, ++ 0x12, 0xde, 0x17, 0x25, 0x78, 0xce, 0x07, 0xf9, 0xea, 0xfb, 0xca, 0x61, ++ 0x7f, 0x34, 0x1d, 0xeb, 0xb6, 0x7c, 0x6c, 0xbf, 0x59, 0xc7, 0xef, 0x0b, ++ 0xad, 0x2b, 0x53, 0x93, 0x59, 0x2c, 0xaf, 0xca, 0xf9, 0xdd, 0xa2, 0x92, ++ 0x1d, 0x7a, 0x3a, 0xbb, 0x42, 0x94, 0x70, 0x2f, 0xd5, 0x9e, 0xe7, 0xe1, ++ 0x86, 0x57, 0x2b, 0x89, 0xc5, 0xed, 0xf0, 0x68, 0x1c, 0x1e, 0xf7, 0x38, ++ 0x73, 0x33, 0xc2, 0xd3, 0xe0, 0x88, 0x7f, 0x9d, 0x2f, 0x3c, 0xde, 0xf1, ++ 0x84, 0x74, 0x03, 0xdf, 0xaa, 0x94, 0x8b, 0x91, 0x7f, 0xbf, 0xe5, 0x18, ++ 0x4f, 0x2e, 0x4b, 0x92, 0x9e, 0x74, 0x71, 0x28, 0x3e, 0x0e, 0xdc, 0x55, ++ 0xc3, 0x75, 0xb9, 0xe8, 0x92, 0x69, 0x7e, 0x7d, 0x84, 0x33, 0xff, 0x49, ++ 0xcb, 0x73, 0xde, 0x4f, 0x51, 0x8d, 0x5c, 0x57, 0x7e, 0x94, 0x8b, 0xbf, ++ 0xfa, 0xe2, 0x42, 0x83, 0x9b, 0x4f, 0x7c, 0xcf, 0x67, 0x35, 0xe7, 0x83, ++ 0x36, 0x7e, 0x1f, 0xc5, 0xdd, 0xdf, 0xa7, 0x26, 0x48, 0x24, 0x0d, 0xde, ++ 0x7d, 0x61, 0x77, 0x1e, 0x46, 0x12, 0xe9, 0xe0, 0x0d, 0x39, 0xbf, 0x3b, ++ 0xe0, 0x31, 0x5d, 0x70, 0xbb, 0xc6, 0x5f, 0x0f, 0xcf, 0xd2, 0xe4, 0xdf, ++ 0xb8, 0xef, 0x57, 0xae, 0x55, 0x93, 0x68, 0x6f, 0xc5, 0x29, 0x98, 0x90, ++ 0xe7, 0xd9, 0xce, 0xf9, 0x52, 0x35, 0x93, 0x78, 0x2f, 0xeb, 0x3b, 0x3e, ++ 0x29, 0xed, 0xfa, 0x49, 0x24, 0xfd, 0x7e, 0xab, 0x96, 0xa4, 0x87, 0xdf, ++ 0x7d, 0x2f, 0x48, 0xcb, 0xcb, 0x75, 0xd2, 0x21, 0xc3, 0xfd, 0xdb, 0xb5, ++ 0x42, 0xee, 0xcd, 0x5d, 0x16, 0xf0, 0x09, 0x92, 0x26, 0x0c, 0xff, 0xe7, ++ 0x96, 0xf3, 0x83, 0x91, 0x73, 0xed, 0xe7, 0x59, 0x42, 0x6f, 0x49, 0xbf, ++ 0x51, 0x3e, 0xa1, 0x4b, 0xda, 0xed, 0x73, 0x7d, 0x2f, 0x61, 0x90, 0xf4, ++ 0x55, 0x3f, 0x1a, 0x02, 0x97, 0x56, 0xfb, 0xeb, 0x54, 0xaf, 0x42, 0xbc, ++ 0x96, 0xca, 0x08, 0xe6, 0xf1, 0xba, 0xdb, 0x1f, 0x13, 0xf8, 0x7b, 0x63, ++ 0x07, 0xc2, 0x2f, 0xf4, 0x74, 0xd6, 0x36, 0x91, 0x4f, 0xfb, 0xe9, 0xd6, ++ 0x01, 0xb9, 0x06, 0xec, 0x7c, 0xdc, 0xd9, 0x3f, 0xa3, 0x1c, 0x72, 0x3d, ++ 0xa7, 0x70, 0xbe, 0x7e, 0x6e, 0x80, 0xf5, 0x67, 0xa2, 0xaf, 0xbf, 0xc4, ++ 0x9d, 0x4f, 0x38, 0x38, 0xfa, 0xfa, 0x40, 0xee, 0x61, 0xdf, 0x53, 0x2d, ++ 0x7e, 0x88, 0xee, 0x94, 0xfb, 0x4c, 0xf3, 0x11, 0x93, 0xad, 0xf7, 0x7c, ++ 0xe5, 0xfe, 0xd3, 0xc2, 0x39, 0xa4, 0x26, 0x46, 0x40, 0x9f, 0x69, 0xa1, ++ 0x18, 0x89, 0xd1, 0x7d, 0xbe, 0x30, 0x94, 0x90, 0x20, 0xce, 0x60, 0x48, ++ 0xbd, 0x71, 0xf0, 0xc7, 0xa8, 0x4c, 0x85, 0x81, 0xce, 0x1b, 0xe1, 0x52, ++ 0x5d, 0xbe, 0xb3, 0xdd, 0x34, 0xda, 0xcf, 0x53, 0x24, 0xc7, 0x3d, 0xd9, ++ 0x20, 0x7f, 0x91, 0xc3, 0xd0, 0x3e, 0x1e, 0x22, 0x5d, 0xd0, 0x7e, 0x7d, ++ 0x9e, 0x5a, 0xb3, 0xa3, 0xbc, 0xbf, 0x9d, 0x21, 0x91, 0x28, 0xf0, 0xbb, ++ 0x91, 0xaf, 0x46, 0xe1, 0xb9, 0x18, 0x2f, 0x7b, 0xaa, 0x73, 0x3c, 0x6a, ++ 0x26, 0x28, 0xf6, 0x7b, 0x58, 0xee, 0xef, 0x2d, 0x78, 0xa6, 0x30, 0xff, ++ 0x54, 0xa3, 0x76, 0xe8, 0xf6, 0x74, 0xfa, 0xc4, 0xcf, 0xec, 0xd0, 0xac, ++ 0x67, 0x7d, 0x78, 0xaf, 0x2f, 0x10, 0x35, 0x92, 0xc0, 0x92, 0x85, 0x95, ++ 0x49, 0xcc, 0xe3, 0x2c, 0x6c, 0x20, 0x11, 0xf0, 0xe7, 0x4a, 0x3b, 0xbb, ++ 0x49, 0x8c, 0x0e, 0xba, 0x96, 0xc3, 0x51, 0x58, 0x99, 0xc0, 0xfc, 0x80, ++ 0xc2, 0x6d, 0x09, 0x3c, 0xb7, 0xcf, 0xf3, 0x92, 0x66, 0xd8, 0x97, 0x0b, ++ 0x1b, 0x13, 0xd2, 0x02, 0xdb, 0x3c, 0x65, 0x7e, 0xc6, 0xdf, 0xd3, 0xe6, ++ 0xea, 0xb8, 0x4f, 0x7c, 0xab, 0x9a, 0xdd, 0xdb, 0xeb, 0x0e, 0x2d, 0x4c, ++ 0x54, 0xc3, 0x7c, 0x55, 0xec, 0xdc, 0x2b, 0x90, 0xa7, 0x92, 0x61, 0x14, ++ 0x1f, 0x81, 0x57, 0xbd, 0xcc, 0xff, 0xac, 0xec, 0x81, 0x6f, 0x49, 0xb0, ++ 0x7c, 0x11, 0xfa, 0xfe, 0x9d, 0x16, 0x52, 0x51, 0x3f, 0x96, 0x90, 0xf7, ++ 0x5a, 0x74, 0x2c, 0x4f, 0xb6, 0x98, 0x58, 0x9a, 0x1f, 0xff, 0xcf, 0x10, ++ 0xe4, 0xb7, 0xb4, 0x5f, 0x32, 0x39, 0x0c, 0xf9, 0x08, 0x67, 0x02, 0x0d, ++ 0xa3, 0x61, 0xdf, 0xf8, 0xa0, 0x25, 0x84, 0xef, 0xef, 0xfb, 0x76, 0x24, ++ 0x0c, 0x79, 0x44, 0xca, 0x91, 0xd7, 0xf0, 0x3b, 0x12, 0xfd, 0xfc, 0x1e, ++ 0x57, 0x48, 0x15, 0xe4, 0xbf, 0xf6, 0x58, 0x40, 0x3f, 0xdb, 0xfa, 0x77, ++ 0xf8, 0x6c, 0xe7, 0xfc, 0x7d, 0xeb, 0xa2, 0xeb, 0x5d, 0x40, 0xe7, 0xb9, ++ 0x57, 0x92, 0x6f, 0x84, 0xf9, 0xa0, 0xbe, 0x10, 0xf9, 0x54, 0x57, 0xb4, ++ 0x02, 0x8e, 0xef, 0x30, 0xc3, 0x33, 0xd8, 0x97, 0x9e, 0x76, 0x12, 0x7d, ++ 0xa2, 0x1c, 0xbe, 0x67, 0x92, 0x94, 0x6e, 0x2d, 0xb7, 0x3d, 0xf7, 0x51, ++ 0xbb, 0x0d, 0xf6, 0xd7, 0x4b, 0x4c, 0xa4, 0x7b, 0x3f, 0x3e, 0x93, 0xad, ++ 0x1c, 0xdf, 0x13, 0xc1, 0xdf, 0x2d, 0x7c, 0x91, 0xe3, 0x75, 0x6e, 0xd5, ++ 0x39, 0xcf, 0x4d, 0xd6, 0xb7, 0xa4, 0xba, 0x67, 0x8c, 0xed, 0xaf, 0x1b, ++ 0x19, 0xee, 0xbb, 0xcd, 0xf5, 0x4c, 0xbb, 0xdc, 0x4f, 0xe7, 0x99, 0x09, ++ 0x97, 0xd8, 0x29, 0x9f, 0x4f, 0x9f, 0x5b, 0x36, 0x14, 0xf0, 0xf5, 0xa0, ++ 0xc7, 0x79, 0x8f, 0x5c, 0x94, 0x8a, 0x39, 0x29, 0x52, 0x02, 0x6d, 0xe3, ++ 0x85, 0x32, 0xca, 0x21, 0xff, 0xde, 0xca, 0x8a, 0xf1, 0xe1, 0xa1, 0x39, ++ 0xb6, 0xf1, 0x67, 0x72, 0xf8, 0x95, 0x23, 0x3f, 0x41, 0xfc, 0x66, 0x95, ++ 0x27, 0xc4, 0x77, 0x77, 0x6a, 0x0b, 0x6d, 0x79, 0xff, 0x23, 0x62, 0x0d, ++ 0xec, 0x3b, 0x7e, 0xcd, 0xec, 0x7e, 0x8c, 0x38, 0x87, 0x1c, 0x7d, 0x7d, ++ 0x4f, 0x2b, 0x1c, 0x49, 0x8c, 0x5e, 0xe9, 0xbc, 0x37, 0x33, 0x8b, 0xdf, ++ 0xf3, 0x2c, 0x6a, 0x97, 0x31, 0xef, 0xb5, 0x68, 0x0a, 0xea, 0x50, 0x52, ++ 0xd4, 0x4a, 0x30, 0xbf, 0x6a, 0xa7, 0x12, 0xa9, 0x00, 0xfe, 0x7e, 0x88, ++ 0xbc, 0x9c, 0x63, 0x29, 0xb0, 0x2b, 0x13, 0x32, 0x92, 0x8a, 0x6a, 0x51, ++ 0xdc, 0x39, 0xce, 0xce, 0x45, 0xb5, 0xcf, 0x43, 0x1c, 0x40, 0xdc, 0x1b, ++ 0x5d, 0xd5, 0xc6, 0xc6, 0x1b, 0x15, 0x8e, 0x1c, 0x0d, 0x43, 0xfc, 0xa4, ++ 0x5c, 0x46, 0x7b, 0x79, 0x34, 0x89, 0xe8, 0x30, 0xfe, 0x68, 0x43, 0x26, ++ 0x70, 0xaf, 0x68, 0x0c, 0xb1, 0x8d, 0x43, 0xeb, 0x23, 0x9b, 0x9d, 0xe3, ++ 0xba, 0xe1, 0x2d, 0x0a, 0xc8, 0xf8, 0xdd, 0x02, 0x01, 0xcf, 0x28, 0xb2, ++ 0x5f, 0xb7, 0xf2, 0x70, 0x7c, 0x92, 0xa4, 0xfd, 0x47, 0x50, 0x37, 0x6f, ++ 0x78, 0x1a, 0xf8, 0xdc, 0xf3, 0x8c, 0x11, 0xed, 0x2e, 0xaa, 0xa8, 0x48, ++ 0x91, 0x34, 0xf3, 0x92, 0xde, 0x56, 0x38, 0x17, 0x3a, 0x6b, 0xfe, 0x01, ++ 0xc6, 0x6d, 0xf1, 0xf7, 0xe5, 0xdf, 0x05, 0x41, 0x9f, 0x6f, 0x93, 0xd8, ++ 0xfa, 0xe3, 0x2f, 0x28, 0x91, 0xdd, 0x40, 0xd7, 0x5b, 0xf7, 0x60, 0xbc, ++ 0x66, 0xc4, 0x8a, 0x4e, 0xdc, 0xd7, 0x3b, 0xfd, 0xcc, 0xbe, 0x5b, 0x4d, ++ 0xed, 0x01, 0xc3, 0x03, 0x76, 0x0a, 0x2d, 0xc7, 0x66, 0xe6, 0x43, 0xc5, ++ 0xa4, 0x88, 0xcb, 0xc6, 0xfd, 0x23, 0x2d, 0xff, 0x3d, 0xe6, 0xaf, 0xde, ++ 0xe8, 0x87, 0x78, 0x98, 0x7f, 0xda, 0x46, 0xe0, 0x43, 0xbf, 0x1a, 0xbe, ++ 0x16, 0xe8, 0xe1, 0x3f, 0xea, 0x21, 0x70, 0x8e, 0xe9, 0xb7, 0x12, 0x28, ++ 0x7f, 0xa4, 0x84, 0xd9, 0x19, 0xf7, 0x96, 0x17, 0x67, 0x83, 0xbc, 0xf9, ++ 0x9b, 0xb5, 0xb4, 0xfe, 0x5a, 0x9b, 0xdf, 0x83, 0xf0, 0x6d, 0xf3, 0x4b, ++ 0x2a, 0xe4, 0x83, 0x52, 0xde, 0xc2, 0x75, 0xa9, 0x8d, 0xe1, 0xef, 0xce, ++ 0xa2, 0xd5, 0xff, 0x96, 0x6f, 0x3d, 0x02, 0xf3, 0xbc, 0x9f, 0x1f, 0xc3, ++ 0x52, 0x3c, 0x0f, 0x2d, 0xac, 0x0b, 0x03, 0x7f, 0x4e, 0xbf, 0xa5, 0x1c, ++ 0xe3, 0x5f, 0xa7, 0x3b, 0x25, 0x8c, 0x7f, 0xbd, 0x2d, 0x25, 0x35, 0x48, ++ 0xd1, 0x5e, 0x7a, 0x75, 0xf3, 0x84, 0x2b, 0x28, 0x3e, 0xe6, 0xe4, 0xc4, ++ 0x1e, 0x85, 0x7e, 0x8d, 0x75, 0xdd, 0xcf, 0xb3, 0x33, 0xda, 0xe6, 0x52, ++ 0xf0, 0xeb, 0x6a, 0x21, 0xcf, 0x2f, 0x1f, 0xa6, 0x8b, 0x33, 0x7f, 0x70, ++ 0xc4, 0x5b, 0x11, 0x15, 0xee, 0x83, 0x8d, 0x50, 0x53, 0x9e, 0x20, 0x7c, ++ 0xcf, 0xe7, 0xc8, 0xab, 0xac, 0x8c, 0x57, 0x03, 0xbf, 0xeb, 0x70, 0x03, ++ 0x86, 0xd2, 0x33, 0x58, 0x62, 0xbd, 0x0b, 0x7e, 0x53, 0x80, 0xdf, 0x3f, ++ 0x52, 0x48, 0x6f, 0x5c, 0x02, 0xff, 0x68, 0x2a, 0x21, 0x6f, 0xd9, 0xe8, ++ 0x06, 0x3e, 0x9d, 0xbd, 0x0e, 0x67, 0xba, 0xf6, 0x7a, 0x26, 0xfc, 0x0f, ++ 0x54, 0xd6, 0xd3, 0xbe, 0x6f, 0x8d, 0x85, 0x5d, 0x3e, 0x62, 0x49, 0x68, ++ 0x17, 0x24, 0xd9, 0x77, 0x10, 0xcc, 0xc8, 0x04, 0x80, 0x53, 0x09, 0x1d, ++ 0x2d, 0x28, 0xb1, 0xed, 0x73, 0x5e, 0xbe, 0x3e, 0xef, 0xf4, 0x85, 0xfc, ++ 0x7b, 0x49, 0x16, 0xf7, 0x6f, 0x22, 0xc4, 0xee, 0xdf, 0x7a, 0xf9, 0xba, ++ 0x40, 0x87, 0xbf, 0x65, 0xeb, 0xef, 0x09, 0x39, 0xeb, 0x8a, 0xf9, 0xf9, ++ 0xae, 0x43, 0xd8, 0xdd, 0xd2, 0x33, 0x7f, 0x39, 0x01, 0x74, 0x5c, 0xf5, ++ 0xa4, 0x07, 0xe3, 0x9e, 0xd3, 0x9f, 0xf4, 0xa4, 0x2e, 0xa7, 0xf5, 0x65, ++ 0xdb, 0x25, 0xdc, 0x67, 0xe4, 0x43, 0x4c, 0xaf, 0x7f, 0xb0, 0x4b, 0x42, ++ 0xb9, 0x4f, 0x05, 0x34, 0xd4, 0x03, 0xef, 0x9b, 0x3a, 0xd6, 0x9b, 0xbc, ++ 0xdd, 0x1b, 0xbe, 0x44, 0xeb, 0xbd, 0x4f, 0x2a, 0x64, 0x07, 0xa2, 0xa5, ++ 0x0e, 0xbf, 0x2f, 0x75, 0x42, 0xec, 0xa7, 0x07, 0x58, 0x7d, 0x11, 0x77, ++ 0x90, 0x96, 0x6d, 0x3f, 0x3c, 0x1f, 0xc6, 0x6b, 0x38, 0xe0, 0x25, 0xb0, ++ 0x4f, 0x2c, 0xfb, 0xc9, 0x2d, 0x57, 0x7d, 0x89, 0xd6, 0x6f, 0xa1, 0x7c, ++ 0x0c, 0x4d, 0x96, 0xed, 0x6e, 0xd5, 0x86, 0xd1, 0xfa, 0xe2, 0xa4, 0xd4, ++ 0x05, 0xf5, 0x53, 0xd3, 0x08, 0xf2, 0x59, 0x3c, 0x57, 0x4b, 0x42, 0x5e, ++ 0xcb, 0xa9, 0x60, 0x77, 0xc1, 0x35, 0x06, 0xee, 0x63, 0x24, 0x3c, 0x0e, ++ 0xce, 0xb7, 0xbb, 0x0b, 0xae, 0xa6, 0xfc, 0xb8, 0x24, 0xf9, 0xc4, 0x2c, ++ 0xe8, 0xb7, 0x64, 0xaf, 0x04, 0x91, 0x54, 0xba, 0x8e, 0xdd, 0xcf, 0x17, ++ 0x52, 0xb8, 0x96, 0x7d, 0x5f, 0xc2, 0xfd, 0x71, 0xe9, 0x9e, 0x2c, 0x12, ++ 0xb6, 0xe1, 0xf3, 0x04, 0x5d, 0xca, 0xe5, 0xf4, 0xfd, 0x0a, 0xba, 0x4e, ++ 0xd0, 0x87, 0xb7, 0x90, 0xc4, 0x2c, 0xa0, 0xd7, 0xb2, 0xdd, 0x9b, 0x34, ++ 0xfb, 0x3e, 0xf7, 0x5e, 0x4b, 0x19, 0xa6, 0x7e, 0x88, 0xfa, 0xb2, 0xef, ++ 0xd3, 0x79, 0x68, 0xbf, 0xe5, 0x3f, 0x94, 0x22, 0xb0, 0xc4, 0xe5, 0x90, ++ 0xef, 0x00, 0xfb, 0xe5, 0x4f, 0x7c, 0x75, 0x3b, 0x0d, 0x58, 0x5f, 0xab, ++ 0x56, 0x1a, 0x80, 0x75, 0xad, 0xd1, 0xa0, 0xdd, 0x2d, 0xc9, 0x05, 0x4f, ++ 0xf9, 0xc2, 0x00, 0xdf, 0x76, 0x6d, 0x16, 0x7d, 0xbf, 0x64, 0xdb, 0x76, ++ 0x6d, 0x51, 0x39, 0xe0, 0x8d, 0xdc, 0x08, 0xfb, 0xea, 0xd2, 0x3d, 0x17, ++ 0x92, 0xb0, 0x8d, 0xae, 0x27, 0x3a, 0x15, 0xf4, 0x17, 0x56, 0xe4, 0xe8, ++ 0x3b, 0xf0, 0x7b, 0xa2, 0x86, 0x15, 0x9a, 0x9b, 0x26, 0x1e, 0xf2, 0x5e, ++ 0x0b, 0x71, 0xc0, 0xb5, 0x84, 0xeb, 0x0d, 0xea, 0xf7, 0x69, 0x73, 0x6c, ++ 0xed, 0x9f, 0xca, 0xca, 0x41, 0x3e, 0x5d, 0xba, 0x47, 0x71, 0xcc, 0x23, ++ 0xe8, 0x1f, 0x3f, 0x46, 0xd8, 0x3d, 0xb4, 0x9f, 0x05, 0xf0, 0x1e, 0x9a, ++ 0xa0, 0x9f, 0xd8, 0xaf, 0x04, 0xfd, 0x56, 0x88, 0x0f, 0xe5, 0xa9, 0xbd, ++ 0x93, 0xd3, 0xc1, 0x03, 0xdf, 0xd5, 0x02, 0x78, 0x12, 0xd4, 0xbf, 0x81, ++ 0xf2, 0xfe, 0x96, 0x10, 0x96, 0x0f, 0xb6, 0x84, 0x91, 0x4e, 0x9b, 0x01, ++ 0x8f, 0xe3, 0x58, 0x5e, 0x0a, 0x3c, 0xa7, 0x72, 0x8b, 0xdf, 0xf3, 0x0b, ++ 0x5a, 0xf0, 0xa1, 0x29, 0xb8, 0x8f, 0x62, 0x55, 0x43, 0xfe, 0x65, 0x6e, ++ 0x94, 0xd5, 0x0b, 0xae, 0x8f, 0x49, 0xe1, 0x73, 0xd8, 0xe9, 0xa2, 0xdc, ++ 0xec, 0x89, 0x2d, 0x00, 0x23, 0x67, 0x6a, 0xd6, 0xf7, 0x66, 0xaa, 0xd4, ++ 0x1f, 0xdb, 0xac, 0xc5, 0x6e, 0x85, 0x90, 0xb5, 0xa9, 0xee, 0x98, 0x39, ++ 0x83, 0xee, 0x79, 0x8d, 0x59, 0xd1, 0xc9, 0x59, 0xb6, 0x73, 0xbf, 0xd5, ++ 0xfc, 0x3b, 0x32, 0x17, 0x67, 0x85, 0x71, 0xfd, 0xab, 0x0b, 0x35, 0xc4, ++ 0xf7, 0xe6, 0x1b, 0x26, 0xef, 0xe4, 0xf1, 0x27, 0xdc, 0x27, 0x37, 0xdf, ++ 0xb0, 0xe8, 0x51, 0x88, 0x8f, 0xd3, 0xfe, 0x5f, 0xc9, 0x02, 0xff, 0x82, ++ 0x9f, 0xff, 0x65, 0xea, 0x5f, 0x30, 0xbf, 0xca, 0xd1, 0xbf, 0x60, 0x7e, ++ 0x83, 0xe8, 0x3f, 0x0b, 0xfb, 0xeb, 0xe7, 0xee, 0xbf, 0x79, 0xfe, 0x65, ++ 0xce, 0xf9, 0xe7, 0x2f, 0x11, 0xfd, 0xaf, 0x42, 0xf8, 0x8d, 0x73, 0xc3, ++ 0x5f, 0x70, 0xe3, 0x54, 0xe7, 0xfc, 0x37, 0x36, 0x62, 0xff, 0x26, 0x2f, ++ 0xa3, 0x6f, 0x6f, 0x8e, 0x8e, 0x79, 0xd6, 0x6d, 0xbe, 0x48, 0xca, 0x03, ++ 0x74, 0x56, 0x09, 0x7e, 0x87, 0x5a, 0xcd, 0x2d, 0xdd, 0x01, 0xed, 0xc4, ++ 0xbe, 0x43, 0x2d, 0x4b, 0x0b, 0xf2, 0xb6, 0x8d, 0xbd, 0x39, 0x15, 0xeb, ++ 0x88, 0x9d, 0x8f, 0xa6, 0xcd, 0x07, 0x38, 0x02, 0x54, 0xba, 0xec, 0x7c, ++ 0x94, 0x5d, 0xe5, 0x77, 0xc8, 0x55, 0x8e, 0x95, 0xeb, 0xa8, 0x0f, 0xa9, ++ 0x19, 0xe6, 0x68, 0x9f, 0x1f, 0x2d, 0x76, 0xbc, 0x1f, 0x5a, 0x77, 0x81, ++ 0x8b, 0x2f, 0x0d, 0xbc, 0xb7, 0x88, 0x75, 0x00, 0x0a, 0x0c, 0x73, 0x0a, ++ 0xa7, 0x36, 0x4c, 0x43, 0x7d, 0x54, 0x3d, 0x8c, 0xd9, 0xc1, 0x77, 0x1c, ++ 0xf2, 0x61, 0xfd, 0x8e, 0xcb, 0xd8, 0xfa, 0xee, 0x18, 0x66, 0xa0, 0x1c, ++ 0x03, 0xcc, 0xe0, 0x97, 0xdf, 0xa1, 0xc5, 0x2e, 0xb6, 0x7f, 0x27, 0x96, ++ 0xae, 0x4b, 0x82, 0xc3, 0x9c, 0x9b, 0x8d, 0xd8, 0x9d, 0xb0, 0x8e, 0xfe, ++ 0xe7, 0x61, 0x19, 0x9e, 0xfb, 0x79, 0xbe, 0x93, 0xdf, 0x4b, 0x50, 0xdf, ++ 0xad, 0x29, 0x9a, 0xbc, 0x33, 0x6e, 0xc3, 0x67, 0xc7, 0x48, 0xca, 0x0f, ++ 0xb4, 0xde, 0x96, 0xa5, 0x31, 0xbc, 0x73, 0x3a, 0xac, 0x19, 0xb9, 0x28, ++ 0x64, 0xb7, 0xd7, 0x57, 0x8f, 0xd4, 0xea, 0xc0, 0xdf, 0x80, 0xe7, 0x37, ++ 0x19, 0x30, 0x5f, 0x74, 0x35, 0xcc, 0xd7, 0xa4, 0xf5, 0x96, 0x82, 0xdd, ++ 0xe1, 0x9e, 0xc7, 0x5b, 0x5c, 0xe5, 0x98, 0x47, 0x1f, 0xd5, 0x80, 0xf3, ++ 0x6c, 0xca, 0x62, 0xf1, 0x54, 0x31, 0x8f, 0x77, 0x54, 0x83, 0x6b, 0x1e, ++ 0xbd, 0x6e, 0x07, 0x7f, 0xce, 0xe7, 0x79, 0x00, 0xf8, 0x2c, 0xd3, 0x3c, ++ 0x6b, 0x8a, 0x2f, 0x73, 0xae, 0x67, 0xd4, 0x12, 0x9c, 0xe7, 0x61, 0xd7, ++ 0x3c, 0x6b, 0x46, 0x2d, 0x71, 0xcd, 0xe3, 0x67, 0xeb, 0xa1, 0xcf, 0xf9, ++ 0x3c, 0xc9, 0x73, 0xcd, 0xe3, 0x1d, 0x33, 0xd5, 0xb9, 0x9e, 0xd1, 0x8d, ++ 0x38, 0xcf, 0x3f, 0xbb, 0xd7, 0x33, 0xba, 0xd1, 0x35, 0x8f, 0x81, 0xf3, ++ 0xc0, 0x73, 0x98, 0x87, 0x1a, 0xbe, 0x61, 0xf8, 0x3e, 0x96, 0xe6, 0xed, ++ 0x5d, 0x84, 0xf4, 0x7f, 0xc6, 0x87, 0x76, 0x8e, 0xe6, 0x8d, 0x3d, 0x86, ++ 0x76, 0xce, 0xeb, 0x3e, 0xb4, 0x73, 0x68, 0x2b, 0x0b, 0xbf, 0xa3, 0x55, ++ 0xc6, 0xfc, 0xdb, 0xdb, 0xb2, 0x72, 0x91, 0x3e, 0x67, 0xfc, 0x94, 0xfe, ++ 0x86, 0x9d, 0xce, 0x71, 0x9e, 0x77, 0x10, 0x47, 0xbf, 0xf8, 0x66, 0x0e, ++ 0x22, 0x49, 0x52, 0x88, 0xa8, 0x7e, 0x5b, 0xce, 0x79, 0xb0, 0x7e, 0xef, ++ 0x9c, 0x51, 0xad, 0x50, 0x1e, 0x98, 0x1e, 0x5a, 0x00, 0xfe, 0xe8, 0x83, ++ 0x01, 0x8c, 0xe3, 0x7d, 0x70, 0x60, 0xba, 0x76, 0x53, 0x1a, 0x7d, 0x74, ++ 0x73, 0xc2, 0x73, 0xa2, 0xc7, 0xc6, 0xcf, 0x7d, 0x7a, 0x95, 0xc7, 0x63, ++ 0x43, 0x59, 0xec, 0x1c, 0x52, 0xd4, 0x4f, 0xf0, 0xf8, 0xcf, 0x5b, 0x10, ++ 0x27, 0xa2, 0xe5, 0xdb, 0x1e, 0x82, 0xfe, 0xd0, 0x71, 0x1e, 0x2f, 0xea, ++ 0x87, 0xb7, 0x15, 0xfb, 0x9d, 0xe0, 0xe7, 0x7a, 0x27, 0xb6, 0xb1, 0x7d, ++ 0xea, 0xcc, 0xa6, 0x63, 0xec, 0xbb, 0x39, 0x71, 0xf2, 0x72, 0xf9, 0x64, ++ 0xf8, 0x1e, 0x0d, 0xfb, 0x77, 0x73, 0x22, 0xcb, 0xe1, 0x8f, 0x37, 0x71, ++ 0x7a, 0xf4, 0xfe, 0xc4, 0x9b, 0xdc, 0x81, 0xf4, 0xb0, 0x86, 0xe3, 0x77, ++ 0x7f, 0x3b, 0x87, 0x38, 0xe2, 0x85, 0xbf, 0x39, 0xf4, 0xb5, 0xe7, 0x59, ++ 0xde, 0x1d, 0x19, 0x0e, 0xdf, 0xcb, 0xbb, 0xae, 0xe3, 0x89, 0xe7, 0xa0, ++ 0xd9, 0x2b, 0xd2, 0x82, 0x91, 0x2b, 0xe8, 0x7a, 0xeb, 0xf6, 0x6f, 0xf2, ++ 0x0c, 0xa7, 0xf5, 0x0f, 0x3c, 0x3d, 0xf3, 0x23, 0x86, 0x6d, 0x9c, 0x3a, ++ 0x0f, 0xde, 0xbb, 0x17, 0x7e, 0xc8, 0x37, 0x62, 0x1e, 0x87, 0xfd, 0xfc, ++ 0xcd, 0x06, 0x67, 0xfd, 0x06, 0x97, 0x3d, 0xfd, 0x46, 0x56, 0xb1, 0x38, ++ 0x9f, 0x65, 0xf3, 0x86, 0x93, 0x1e, 0xa0, 0xd7, 0x3c, 0x38, 0x63, 0xa5, ++ 0x24, 0xbc, 0x01, 0x4a, 0x4c, 0xbe, 0x33, 0x91, 0x5e, 0xf3, 0x4d, 0xd6, ++ 0x57, 0xc0, 0xd3, 0x74, 0x97, 0x87, 0xa4, 0x70, 0xbf, 0xeb, 0xc9, 0xc7, ++ 0x38, 0x67, 0x3c, 0x1f, 0xe3, 0x34, 0x31, 0xb1, 0x6f, 0xb9, 0xe0, 0x9b, ++ 0xef, 0xd1, 0xad, 0x28, 0xa5, 0xe7, 0xfc, 0x3b, 0x15, 0xc4, 0xa3, 0x1b, ++ 0xde, 0x9e, 0x43, 0x59, 0x96, 0x4c, 0xfd, 0x9c, 0x9e, 0xce, 0xff, 0xed, ++ 0x81, 0xfb, 0x3b, 0x03, 0xc1, 0x7f, 0xe3, 0x4a, 0xe7, 0x7b, 0x12, 0xf7, ++ 0x38, 0xbe, 0x43, 0x20, 0xf8, 0xe0, 0xda, 0xba, 0xea, 0x9d, 0xc7, 0x6d, ++ 0xfc, 0xf1, 0x8d, 0xd8, 0xec, 0x9d, 0xc7, 0x1d, 0x78, 0x9a, 0xe3, 0xa8, ++ 0xdf, 0xd0, 0xfc, 0x0d, 0x47, 0xfb, 0x1b, 0x57, 0x2e, 0x70, 0xbc, 0x5f, ++ 0x10, 0x5f, 0xec, 0x78, 0x7f, 0x53, 0xc7, 0xad, 0x8e, 0xfa, 0xcd, 0x89, ++ 0x3b, 0x1d, 0xed, 0x6f, 0xe9, 0x6c, 0x75, 0xbc, 0x5f, 0x9c, 0x5c, 0xeb, ++ 0x78, 0xbf, 0x74, 0xcf, 0x26, 0x47, 0x7d, 0x59, 0xd7, 0x16, 0x47, 0xfb, ++ 0xa6, 0x03, 0xdb, 0x1d, 0xef, 0xe5, 0x43, 0xe3, 0xff, 0x09, 0xfd, 0xc0, ++ 0x5f, 0x29, 0x78, 0xcf, 0xf9, 0x43, 0xe3, 0xc4, 0x06, 0xb0, 0xdf, 0x3e, ++ 0x34, 0xd9, 0x77, 0xfe, 0xdf, 0xe1, 0xe7, 0x77, 0xef, 0xf1, 0xef, 0xfd, ++ 0x2c, 0x07, 0xde, 0x9b, 0x02, 0xf2, 0x33, 0x49, 0x07, 0xbf, 0xa1, 0xc9, ++ 0x4f, 0xe5, 0x99, 0xda, 0x12, 0x13, 0x8c, 0xfc, 0xd5, 0x1d, 0x53, 0x41, ++ 0x8f, 0x10, 0xfc, 0xa4, 0x46, 0x85, 0x31, 0x7c, 0x75, 0x9c, 0x3a, 0xbb, ++ 0x53, 0xf8, 0xbd, 0x44, 0xa5, 0x53, 0x23, 0xa9, 0x21, 0x70, 0xbc, 0xd2, ++ 0x1f, 0x87, 0xed, 0x55, 0xfa, 0xdf, 0xab, 0x3d, 0xf4, 0xfd, 0xa4, 0xcc, ++ 0xef, 0x95, 0x4e, 0x35, 0xed, 0x7b, 0xb5, 0x47, 0x4d, 0x3b, 0xee, 0x29, ++ 0xa9, 0xb7, 0x14, 0xec, 0xc7, 0xf8, 0x6b, 0xde, 0xb4, 0xf7, 0xbf, 0xfb, ++ 0xe5, 0x92, 0x0c, 0x87, 0xfd, 0x22, 0xd3, 0xfb, 0x93, 0x32, 0x69, 0xb0, ++ 0xfb, 0x6f, 0xf3, 0x0c, 0x16, 0x1f, 0x7a, 0x3e, 0x6b, 0xda, 0x3c, 0x03, ++ 0xfc, 0x21, 0x8d, 0xc9, 0x7b, 0xe3, 0xbe, 0xc2, 0x69, 0xe0, 0x37, 0x34, ++ 0x6a, 0xa9, 0xd2, 0x74, 0xe7, 0x36, 0x7d, 0xf3, 0x75, 0x49, 0xf8, 0x9d, ++ 0xc0, 0x79, 0x06, 0x93, 0x97, 0xc5, 0x49, 0xe7, 0xf7, 0x6f, 0x97, 0xee, ++ 0x19, 0xe3, 0x90, 0xfb, 0x57, 0xfd, 0xb1, 0x6b, 0x0c, 0xda, 0xee, 0xe4, ++ 0x61, 0x85, 0x7d, 0x2f, 0x2f, 0xf5, 0xec, 0xa8, 0xaf, 0x5f, 0x04, 0xf3, ++ 0x5b, 0xf3, 0xe0, 0x39, 0x39, 0x90, 0x8f, 0xfb, 0xe3, 0x2b, 0x2d, 0xd6, ++ 0xce, 0xe3, 0xd4, 0x0f, 0x78, 0xb5, 0xa5, 0x06, 0xcb, 0x7f, 0x6d, 0x89, ++ 0xee, 0x3c, 0x4e, 0x1d, 0xb5, 0x37, 0x5a, 0xea, 0xb0, 0xfe, 0xdb, 0x96, ++ 0x18, 0x96, 0x3d, 0x2d, 0x0d, 0x58, 0xbe, 0xd5, 0xd2, 0x8c, 0xef, 0x8f, ++ 0xb7, 0xac, 0xc4, 0xfa, 0x89, 0x96, 0x38, 0x96, 0xef, 0xb4, 0x74, 0x60, ++ 0xf9, 0x5e, 0x4b, 0x02, 0xdf, 0x9f, 0x6c, 0xe9, 0xc4, 0xfa, 0x07, 0x2d, ++ 0x49, 0x2c, 0x85, 0x1c, 0x08, 0x7b, 0x97, 0x44, 0xb9, 0x3d, 0x29, 0x0e, ++ 0x4c, 0x08, 0xab, 0x9f, 0xe6, 0x6b, 0x50, 0x0a, 0x44, 0x1c, 0x33, 0x82, ++ 0xdf, 0x8f, 0x3a, 0x6d, 0x9c, 0x29, 0x05, 0x3b, 0xfa, 0xf4, 0xab, 0x5e, ++ 0xcc, 0xbb, 0xcd, 0x84, 0x27, 0x37, 0xdf, 0x65, 0xa6, 0x9f, 0x85, 0xfb, ++ 0xfd, 0xa2, 0xa4, 0x33, 0xce, 0x2c, 0x4a, 0x9f, 0x9f, 0xd1, 0xc7, 0x27, ++ 0x93, 0x1a, 0xc8, 0x91, 0x58, 0x3b, 0x56, 0xc3, 0x38, 0x9a, 0xff, 0x99, ++ 0x0b, 0xd1, 0x1e, 0xa7, 0xcf, 0x55, 0xc2, 0xbe, 0xb7, 0x1c, 0xb1, 0x7f, ++ 0x4f, 0xa2, 0x6f, 0x7c, 0x48, 0x1e, 0x1e, 0x3a, 0x30, 0x9d, 0x44, 0xfb, ++ 0x13, 0xdf, 0xfb, 0xf7, 0xc9, 0x0b, 0xcb, 0x81, 0x3e, 0xc5, 0x88, 0x27, ++ 0xff, 0xb3, 0x4a, 0x33, 0xa3, 0xdb, 0xce, 0xc8, 0xd7, 0x2f, 0x1a, 0x18, ++ 0x7f, 0x68, 0xf3, 0x15, 0x9e, 0x8d, 0x47, 0xe9, 0x99, 0xdf, 0x8c, 0x82, ++ 0xf8, 0xd4, 0xfb, 0xf9, 0x02, 0x9f, 0xdd, 0xa3, 0x20, 0xb8, 0xa5, 0x1a, ++ 0xd1, 0x2d, 0xc0, 0x87, 0xa7, 0xf7, 0x7b, 0x71, 0x5d, 0xa7, 0x0f, 0x66, ++ 0xb1, 0x7c, 0x14, 0x08, 0xaa, 0x0d, 0x22, 0xff, 0x75, 0xe9, 0x1e, 0x5f, ++ 0xd2, 0xae, 0x1f, 0x96, 0x75, 0xe5, 0x24, 0x9d, 0xfa, 0xa2, 0x30, 0x69, ++ 0xd7, 0x17, 0xa7, 0x8f, 0xee, 0x0c, 0x82, 0xdc, 0xaf, 0x08, 0x29, 0xc9, ++ 0xe3, 0x93, 0x80, 0x3f, 0x2c, 0xce, 0x1f, 0x8c, 0xef, 0xc4, 0xf8, 0xcb, ++ 0xba, 0x8a, 0x92, 0x86, 0x63, 0x1c, 0x67, 0xfd, 0x74, 0x42, 0xaa, 0xe9, ++ 0xc2, 0xb8, 0x58, 0x38, 0xfb, 0xea, 0x34, 0xfe, 0x87, 0x28, 0x57, 0x84, ++ 0x34, 0x9c, 0xe7, 0xbd, 0x3d, 0x63, 0x30, 0xff, 0x80, 0xfa, 0x89, 0xc9, ++ 0xe3, 0x2c, 0xde, 0x99, 0x64, 0xf3, 0x86, 0x92, 0x76, 0xbe, 0x6c, 0x5c, ++ 0x99, 0x95, 0x3c, 0x3e, 0xa4, 0x1f, 0xbe, 0x4c, 0xe3, 0x7e, 0xde, 0xf0, ++ 0x11, 0xb2, 0x9f, 0xfc, 0x4e, 0xcf, 0x7c, 0x0f, 0x77, 0xa0, 0x92, 0xa8, ++ 0xff, 0xa6, 0xe1, 0xf7, 0x2d, 0x0f, 0x7a, 0xce, 0xc0, 0xbe, 0xe3, 0xa5, ++ 0xff, 0x7d, 0x82, 0xf9, 0x42, 0x2a, 0xd6, 0xc5, 0xb8, 0x4d, 0x5d, 0x4a, ++ 0xdc, 0x0b, 0xf7, 0x78, 0xc9, 0x5e, 0xc7, 0x7c, 0xb4, 0x5f, 0x58, 0xf8, ++ 0xe8, 0xf6, 0xef, 0xe6, 0x9c, 0x4d, 0x77, 0x67, 0x3e, 0xf8, 0x6f, 0x81, ++ 0x97, 0x70, 0xdf, 0x66, 0xf7, 0xca, 0x63, 0x70, 0xaf, 0x9c, 0x8e, 0x77, ++ 0x4a, 0x35, 0x3a, 0xa4, 0x8b, 0xfb, 0xef, 0x95, 0x37, 0x71, 0xbe, 0x5c, ++ 0xa6, 0xf7, 0x68, 0x31, 0xfa, 0xe8, 0xfd, 0xfd, 0x63, 0xce, 0x99, 0x0f, ++ 0xf2, 0x5e, 0xcb, 0x51, 0x53, 0x1d, 0x0b, 0x79, 0x04, 0x09, 0xfc, 0x60, ++ 0x44, 0x43, 0xd7, 0xf8, 0x19, 0xa0, 0x1f, 0xdf, 0xdf, 0xbf, 0xaa, 0x00, ++ 0xe2, 0x69, 0x4b, 0x95, 0xd3, 0x77, 0xa4, 0xbb, 0x2f, 0xfb, 0x91, 0xc1, ++ 0xe2, 0x6c, 0x24, 0xe9, 0xe9, 0xed, 0xb1, 0xad, 0x47, 0xc4, 0x67, 0x08, ++ 0xa1, 0xe3, 0xea, 0xfd, 0xf0, 0x03, 0xa7, 0x9f, 0xb0, 0xd5, 0xdd, 0xfa, ++ 0x5a, 0x94, 0x72, 0x80, 0xc5, 0xdd, 0x97, 0xef, 0x3d, 0x36, 0xeb, 0x4b, ++ 0x14, 0xfe, 0xe5, 0x07, 0xfe, 0xa8, 0x01, 0x1c, 0x07, 0x8c, 0x98, 0x1c, ++ 0xb0, 0xad, 0x5f, 0xe2, 0xf7, 0xea, 0x97, 0xec, 0x79, 0x53, 0x83, 0xf5, ++ 0xbd, 0xe3, 0x89, 0x97, 0xde, 0x75, 0x0e, 0x3d, 0x75, 0x36, 0x9c, 0x46, ++ 0xc8, 0x71, 0x1e, 0x1a, 0x27, 0xdd, 0x20, 0xc7, 0x0b, 0xd9, 0x6f, 0x30, ++ 0x00, 0x3f, 0x5d, 0xfb, 0x3a, 0x15, 0xcd, 0x77, 0x7f, 0xe9, 0x21, 0xf0, ++ 0xbb, 0x0e, 0xe2, 0xbc, 0x42, 0xdc, 0x7b, 0xa8, 0x27, 0xd1, 0x20, 0xe0, ++ 0x6b, 0xe1, 0xfe, 0xa5, 0x18, 0x1f, 0x7e, 0xf7, 0xa9, 0x2b, 0xb9, 0x3d, ++ 0x97, 0x98, 0x0c, 0xfc, 0xf1, 0x3e, 0x91, 0x6b, 0x60, 0x7d, 0xef, 0x93, ++ 0x97, 0x82, 0x93, 0x6c, 0xf8, 0x2b, 0x09, 0x30, 0x3f, 0x86, 0x74, 0x30, ++ 0x3b, 0x46, 0xdc, 0x0b, 0xa4, 0xf6, 0xac, 0xc3, 0xae, 0xb9, 0xa5, 0xd3, ++ 0x59, 0x5f, 0x44, 0xe6, 0x16, 0x80, 0xde, 0x58, 0xf4, 0xa0, 0x07, 0xbe, ++ 0xa1, 0x4a, 0x16, 0x13, 0xdb, 0xf7, 0x97, 0xe8, 0xba, 0xf3, 0x02, 0xcc, ++ 0xde, 0xbd, 0x85, 0x34, 0xaf, 0x06, 0x7b, 0x4e, 0xf5, 0x32, 0xff, 0x60, ++ 0xa1, 0x49, 0xd4, 0xe1, 0x54, 0x9f, 0x2e, 0xfb, 0xf1, 0x43, 0x93, 0xc1, ++ 0xee, 0xbf, 0x30, 0xc0, 0xce, 0x1d, 0x45, 0x1c, 0x63, 0x71, 0x2e, 0xb3, ++ 0xf7, 0x96, 0xe4, 0x25, 0x35, 0x38, 0x4f, 0xf8, 0xdd, 0xfe, 0x49, 0xf3, ++ 0xbe, 0x04, 0xdc, 0xe7, 0x4d, 0xae, 0x86, 0x7d, 0x99, 0x64, 0xa7, 0x3f, ++ 0xff, 0xbb, 0xa9, 0xc3, 0x09, 0xdf, 0x40, 0xf0, 0xbb, 0xe1, 0x15, 0xf7, ++ 0xdd, 0xcf, 0x8a, 0xa7, 0x70, 0x38, 0x94, 0x3d, 0x52, 0xda, 0xfc, 0xb4, ++ 0x29, 0x01, 0xce, 0x77, 0x5c, 0x8f, 0xdc, 0x13, 0x70, 0xda, 0xf9, 0x6b, ++ 0x5c, 0xf5, 0xda, 0x00, 0x8f, 0xb3, 0x2a, 0x44, 0x01, 0x3a, 0xbf, 0x6f, ++ 0xea, 0x71, 0x39, 0x1b, 0xdf, 0xe3, 0xfd, 0xda, 0xf8, 0x3e, 0x6f, 0x64, ++ 0x55, 0x18, 0xbe, 0xa7, 0x15, 0x8d, 0x02, 0x7f, 0x51, 0xbb, 0x60, 0x02, ++ 0xb1, 0xb5, 0xfb, 0xbd, 0x11, 0xc3, 0xe7, 0x27, 0xa5, 0x17, 0x17, 0xe1, ++ 0xfd, 0x72, 0x35, 0x35, 0x01, 0xf3, 0xf1, 0x74, 0xa2, 0xda, 0x7f, 0x8f, ++ 0x41, 0xf1, 0x07, 0x27, 0x90, 0x8b, 0x21, 0x4e, 0xda, 0x8c, 0x4e, 0xfd, ++ 0x2a, 0x5f, 0x70, 0x07, 0xd4, 0x57, 0x07, 0xd8, 0x3d, 0xa8, 0x26, 0x90, ++ 0x53, 0xb8, 0x3f, 0x1d, 0x9c, 0x75, 0x14, 0xe2, 0xfa, 0x3a, 0x49, 0xa4, ++ 0xac, 0x22, 0x38, 0xff, 0x76, 0xc6, 0xbf, 0x7d, 0x61, 0x67, 0x3d, 0x0b, ++ 0xe4, 0x09, 0xf4, 0x09, 0x3c, 0x00, 0x7a, 0x44, 0x08, 0xc6, 0x8b, 0xb2, ++ 0xca, 0x9c, 0xed, 0x02, 0x11, 0x67, 0x7d, 0x49, 0x1f, 0x9e, 0x52, 0x8a, ++ 0xfd, 0xde, 0x47, 0x50, 0x37, 0x52, 0xf8, 0x7b, 0x4d, 0x55, 0xea, 0x49, ++ 0xbb, 0xdd, 0xbc, 0x5c, 0x67, 0xf0, 0x13, 0xf8, 0x9e, 0x2a, 0x6d, 0x7f, ++ 0x1b, 0xb7, 0xe7, 0x97, 0x93, 0x70, 0x1c, 0xf3, 0x16, 0x43, 0x8c, 0x0f, ++ 0x6e, 0x9b, 0xcd, 0xf2, 0x26, 0x6e, 0x0b, 0x84, 0xf1, 0x5e, 0xb2, 0xa4, ++ 0x5a, 0x78, 0x3f, 0x62, 0x0d, 0x74, 0xb5, 0xed, 0x63, 0x4d, 0x1f, 0x49, ++ 0x24, 0x69, 0xd3, 0xeb, 0x4d, 0x6a, 0xaf, 0x06, 0x7c, 0xd9, 0xf4, 0x91, ++ 0x8a, 0xcf, 0x1f, 0x36, 0x62, 0xdf, 0x06, 0xbc, 0x6a, 0xc4, 0x42, 0x3b, ++ 0x57, 0xa7, 0x48, 0x83, 0xf3, 0x6b, 0xd5, 0xa8, 0x71, 0xd8, 0xbd, 0x64, ++ 0x04, 0xff, 0x2e, 0xa0, 0x2b, 0x7f, 0x61, 0x7d, 0xc0, 0x74, 0xf8, 0x7b, ++ 0x42, 0x2f, 0x78, 0xb8, 0x5e, 0xa4, 0xfa, 0x62, 0x4d, 0x20, 0x1f, 0xf4, ++ 0x60, 0xef, 0x2c, 0x76, 0xae, 0xde, 0xa3, 0xb1, 0xf3, 0x1d, 0xd6, 0x4e, ++ 0xeb, 0x6f, 0xb7, 0x1e, 0xe0, 0xc8, 0xd4, 0xce, 0xd7, 0xdf, 0x6e, 0x53, ++ 0xba, 0x76, 0xcb, 0x7e, 0xfc, 0xf8, 0x53, 0x71, 0x2a, 0xef, 0x4b, 0x7e, ++ 0xf4, 0x9d, 0x20, 0x1c, 0xa6, 0xbd, 0xab, 0x26, 0x0a, 0x20, 0xff, 0xa1, ++ 0x71, 0x77, 0x7b, 0x10, 0xf8, 0xf8, 0x1d, 0x35, 0x1e, 0x84, 0x75, 0xbf, ++ 0x9b, 0x4c, 0x9f, 0xf7, 0xfe, 0x73, 0xae, 0xef, 0x20, 0xdf, 0x09, 0xee, ++ 0xc9, 0x2f, 0xe7, 0x74, 0x7a, 0xef, 0x07, 0xf7, 0x5e, 0x05, 0x78, 0x3f, ++ 0xb3, 0xdb, 0x83, 0xf7, 0xec, 0x9b, 0xf6, 0x78, 0x53, 0x5e, 0x4a, 0xc4, ++ 0xe5, 0xfb, 0x17, 0x33, 0x7e, 0xda, 0xe3, 0x7d, 0x93, 0xd5, 0xd7, 0xe0, ++ 0xef, 0x2e, 0x34, 0x1d, 0x70, 0xca, 0xdb, 0x92, 0xc7, 0xbe, 0x53, 0x10, ++ 0xc6, 0xc3, 0xbd, 0x38, 0xf3, 0x1b, 0x49, 0x0a, 0xed, 0xe7, 0xe5, 0xbb, ++ 0x7e, 0x3f, 0x0b, 0xec, 0x91, 0x26, 0xd2, 0x8b, 0x7a, 0xc2, 0xdd, 0x0f, ++ 0xe6, 0xff, 0x28, 0x17, 0xf7, 0xaf, 0x05, 0x70, 0xdf, 0xdf, 0xfd, 0x5e, ++ 0xe4, 0x5b, 0x35, 0x71, 0xbe, 0x6f, 0xda, 0x7f, 0x2f, 0xe6, 0x55, 0x35, ++ 0xed, 0x9f, 0x8d, 0x79, 0x54, 0x4d, 0x2e, 0x39, 0x6f, 0xe0, 0x7e, 0xc8, ++ 0x81, 0x80, 0xf3, 0x77, 0x36, 0x04, 0x3e, 0x48, 0x92, 0xd9, 0xc5, 0xab, ++ 0xbe, 0xff, 0xdd, 0x09, 0x6f, 0x52, 0x78, 0x4e, 0xee, 0xfa, 0x65, 0x50, ++ 0x72, 0xc4, 0x8f, 0x98, 0x9e, 0x38, 0xdd, 0x75, 0xd3, 0x23, 0x4f, 0x87, ++ 0x33, 0xeb, 0xf7, 0x0f, 0xb8, 0x5f, 0xdf, 0xdf, 0x2f, 0x89, 0xfd, 0xc2, ++ 0x07, 0x98, 0x1d, 0x4f, 0x0e, 0xb2, 0xb2, 0xd1, 0x93, 0x0a, 0x82, 0xdf, ++ 0xd4, 0xb8, 0xdd, 0x13, 0xa1, 0x1a, 0x84, 0x34, 0x3e, 0xbe, 0xf3, 0xd1, ++ 0xef, 0x01, 0x7f, 0xbf, 0xe6, 0xc5, 0x78, 0xc3, 0xd2, 0xc7, 0x9f, 0x7b, ++ 0xe5, 0x32, 0x5a, 0x5f, 0xfa, 0x84, 0x27, 0xaf, 0x96, 0x2d, 0xc3, 0x80, ++ 0x3c, 0x60, 0x41, 0x17, 0xb8, 0xdb, 0x0e, 0xf9, 0xba, 0x82, 0x0e, 0x4b, ++ 0xfe, 0xe5, 0x39, 0x2d, 0x7c, 0x11, 0x7b, 0x7e, 0x77, 0x6e, 0x3f, 0x3d, ++ 0x96, 0x3e, 0x71, 0x58, 0x23, 0x17, 0x9d, 0x8d, 0xbf, 0xe9, 0x5d, 0x87, ++ 0x35, 0xfc, 0x4e, 0x90, 0x9b, 0x2e, 0x5d, 0x6f, 0xce, 0x02, 0xbb, 0x7b, ++ 0xd5, 0xf7, 0xff, 0xa4, 0x81, 0x7c, 0xbd, 0x7b, 0x48, 0x22, 0x43, 0x8b, ++ 0xce, 0xee, 0xdf, 0xb0, 0xfd, 0x39, 0xb4, 0xeb, 0x00, 0x4f, 0x48, 0x47, ++ 0x4e, 0xa7, 0x3e, 0xba, 0x9d, 0x45, 0xaf, 0xd4, 0x55, 0x4f, 0x57, 0x62, ++ 0x3b, 0x13, 0xf6, 0xb1, 0x81, 0xe8, 0xf5, 0x3d, 0xe0, 0x99, 0x7c, 0xe4, ++ 0xeb, 0x1f, 0x3e, 0x0d, 0xe7, 0x05, 0xff, 0xea, 0x8d, 0x00, 0x1e, 0x1a, ++ 0x7e, 0xf8, 0xad, 0x20, 0xac, 0xe7, 0x6d, 0xb5, 0x99, 0xf1, 0xf7, 0x43, ++ 0xed, 0x05, 0x70, 0x8e, 0xde, 0xe0, 0x89, 0x17, 0x98, 0x58, 0xb2, 0xe7, ++ 0x0d, 0x0f, 0xdf, 0x8e, 0x7c, 0x77, 0xcb, 0xb1, 0xdb, 0x0b, 0x58, 0x1e, ++ 0x94, 0x55, 0xc8, 0x7f, 0x17, 0xa0, 0x10, 0xe3, 0x80, 0xdb, 0xae, 0xc1, ++ 0x75, 0x2e, 0x22, 0x31, 0xe4, 0xbf, 0x86, 0x87, 0x94, 0x28, 0x9c, 0x93, ++ 0x7d, 0xa8, 0x92, 0x9a, 0x27, 0xd2, 0xc8, 0xc7, 0xe5, 0x41, 0xa6, 0xc7, ++ 0xde, 0xde, 0xe1, 0xc5, 0x8f, 0xde, 0xbd, 0x0d, 0x0a, 0x17, 0xfc, 0xc5, ++ 0x97, 0x94, 0x24, 0xbb, 0x6f, 0xcb, 0xf2, 0x12, 0x6f, 0x17, 0xe7, 0x1e, ++ 0xf0, 0xdd, 0x46, 0x5a, 0xff, 0x50, 0x67, 0xf4, 0xca, 0x0f, 0xca, 0xe2, ++ 0x7b, 0x56, 0xba, 0x83, 0x6f, 0x77, 0xad, 0xe9, 0x06, 0x3a, 0xbd, 0x37, ++ 0xd2, 0x1a, 0x0a, 0xf1, 0x4a, 0x8a, 0x87, 0x38, 0xc7, 0x9b, 0x04, 0x7a, ++ 0x48, 0x39, 0x36, 0x73, 0x28, 0xa3, 0x13, 0x09, 0xab, 0x93, 0x79, 0x3f, ++ 0xaa, 0x27, 0xa7, 0xc3, 0x73, 0x68, 0xdf, 0xed, 0xb1, 0x7c, 0x13, 0x1c, ++ 0xfd, 0xf8, 0xbe, 0xc6, 0xe6, 0xbf, 0x8d, 0xcf, 0x4f, 0xe1, 0xf6, 0x83, ++ 0x7d, 0xf6, 0x76, 0x01, 0xb5, 0x77, 0xd2, 0xac, 0x6f, 0x69, 0x50, 0xc8, ++ 0x3f, 0xb5, 0x3f, 0x6c, 0x7c, 0x66, 0x93, 0x73, 0x26, 0xf7, 0xbb, 0xd6, ++ 0x32, 0x39, 0x17, 0x72, 0x9f, 0x9c, 0x53, 0x03, 0xef, 0xff, 0xed, 0x65, ++ 0x26, 0x47, 0xd0, 0x0f, 0xf6, 0x79, 0x0a, 0x57, 0x6a, 0x28, 0xbe, 0x3f, ++ 0x7c, 0xb5, 0x84, 0x7a, 0xc1, 0x4b, 0x52, 0xe9, 0xe4, 0x7b, 0x97, 0x87, ++ 0xcb, 0xb7, 0xf3, 0x3d, 0xf5, 0xca, 0xd1, 0xbe, 0x15, 0x7c, 0x42, 0xe1, ++ 0x57, 0x61, 0xdf, 0xea, 0xe7, 0x17, 0x76, 0xce, 0x4b, 0xe9, 0x80, 0xf6, ++ 0xdb, 0xa2, 0x07, 0x69, 0x7f, 0xbb, 0x7d, 0x0e, 0xf3, 0x62, 0x3b, 0xad, ++ 0xff, 0xb9, 0x6d, 0xbf, 0xbf, 0x85, 0xeb, 0x83, 0xcb, 0x82, 0xae, 0xdf, ++ 0xdd, 0xd9, 0x96, 0x3f, 0xa8, 0xef, 0xe4, 0x35, 0x7a, 0x92, 0x8f, 0x7e, ++ 0x0f, 0xe4, 0x97, 0xca, 0x2b, 0xec, 0x3f, 0x8d, 0x8f, 0x7b, 0x30, 0x4f, ++ 0xe4, 0x0f, 0x7b, 0x9f, 0x7d, 0xe5, 0x3a, 0xca, 0xe7, 0x7f, 0xe8, 0x12, ++ 0x72, 0xeb, 0xd4, 0xa7, 0x6e, 0xb9, 0x6d, 0xd8, 0x77, 0x09, 0x49, 0x27, ++ 0xb7, 0x7f, 0x30, 0x22, 0x24, 0xad, 0xdc, 0xd2, 0xe7, 0x69, 0xe5, 0xd6, ++ 0xe8, 0x41, 0x7e, 0xfe, 0x5b, 0xe9, 0x53, 0x81, 0xbf, 0x85, 0x41, 0x67, ++ 0x9e, 0x93, 0xd0, 0x8f, 0x99, 0xf0, 0xe8, 0xd6, 0x8f, 0x7f, 0x0d, 0x84, ++ 0xd9, 0xef, 0x22, 0xb8, 0xf4, 0x23, 0xfd, 0xf7, 0x32, 0x99, 0x7c, 0x36, ++ 0x1f, 0x0a, 0xfe, 0x13, 0x7c, 0xb7, 0xe4, 0x9f, 0x97, 0xe1, 0xef, 0x83, ++ 0xf4, 0xf1, 0xa7, 0xe0, 0xbf, 0x3e, 0xfe, 0x14, 0xfc, 0xe7, 0x5e, 0xaf, ++ 0x13, 0x7f, 0xee, 0xf7, 0x17, 0x82, 0xa1, 0x22, 0xe2, 0xc5, 0xb4, 0xf4, ++ 0xdc, 0x43, 0xe2, 0x01, 0x88, 0xa7, 0xfe, 0x4c, 0xc1, 0x78, 0xea, 0x29, ++ 0x0a, 0xd3, 0x6a, 0x4a, 0xe7, 0x53, 0x7b, 0x8b, 0xf0, 0x1e, 0x71, 0xbb, ++ 0x8f, 0xf9, 0xe7, 0xa7, 0xcc, 0xde, 0x60, 0x6e, 0x39, 0x7e, 0xff, 0x06, ++ 0xeb, 0xbd, 0xf9, 0xda, 0x6a, 0xd0, 0x17, 0xe2, 0x79, 0xaf, 0x8f, 0xc5, ++ 0xbf, 0x4f, 0x45, 0x7b, 0x83, 0xf6, 0x3c, 0x90, 0x37, 0x0f, 0x2a, 0x41, ++ 0x38, 0xef, 0xea, 0x49, 0x92, 0x9a, 0x74, 0xfe, 0x08, 0xd5, 0xc8, 0x08, ++ 0x47, 0x0f, 0xc9, 0xf4, 0x9e, 0xc5, 0x8b, 0x4f, 0x81, 0xfd, 0x07, 0xf3, ++ 0xf9, 0x47, 0x25, 0x81, 0x6e, 0x33, 0x15, 0x63, 0xd4, 0x4a, 0xf0, 0xf3, ++ 0x13, 0xec, 0xbe, 0x7c, 0x7d, 0xeb, 0xb5, 0x41, 0xc8, 0x53, 0x38, 0x75, ++ 0x70, 0xcc, 0x46, 0xd0, 0x5f, 0x37, 0xbf, 0xa0, 0x10, 0xfe, 0xbb, 0x85, ++ 0x2a, 0xe4, 0x9b, 0xdc, 0xc4, 0xe9, 0xff, 0x0e, 0x89, 0x6f, 0x9e, 0x4a, ++ 0xd7, 0x79, 0xd3, 0x41, 0xe6, 0x57, 0xd4, 0xaf, 0x4f, 0xcf, 0x2f, 0x4b, ++ 0x78, 0xfb, 0x45, 0xc6, 0x6d, 0x1a, 0xe8, 0x25, 0xea, 0x17, 0xbc, 0x65, ++ 0x8f, 0x87, 0x2f, 0xe1, 0xbf, 0xc7, 0xd4, 0xb0, 0xcd, 0xf5, 0xfc, 0xe0, ++ 0x95, 0xc8, 0x57, 0x4b, 0x5c, 0x7c, 0x15, 0xe3, 0x7e, 0xe3, 0xe3, 0x82, ++ 0xaf, 0x26, 0x92, 0x89, 0xdc, 0x6f, 0x93, 0xed, 0xf9, 0x6c, 0x33, 0x95, ++ 0xf2, 0x8d, 0x60, 0x97, 0x9c, 0x3a, 0xca, 0xe2, 0x90, 0xa7, 0x0f, 0x2a, ++ 0x48, 0x8f, 0xd3, 0x7b, 0x25, 0x96, 0xff, 0x04, 0xf1, 0xe0, 0x29, 0xc0, ++ 0x0f, 0xbd, 0x9a, 0x3d, 0x8f, 0xed, 0x24, 0xf0, 0x5f, 0x9a, 0xef, 0x1b, ++ 0xf4, 0xbd, 0x7f, 0xf2, 0x37, 0x93, 0xef, 0xa2, 0x4d, 0x1a, 0x9f, 0x7a, ++ 0x7d, 0xc2, 0x56, 0x5a, 0x9e, 0x7c, 0xea, 0xb5, 0xd2, 0x9f, 0x42, 0xfd, ++ 0xc7, 0xbf, 0x1e, 0xf5, 0x3a, 0x39, 0xbb, 0xfd, 0xf4, 0x43, 0x7f, 0xc6, ++ 0xf3, 0xec, 0x53, 0x87, 0xbc, 0x08, 0xc7, 0xa9, 0x43, 0x3f, 0x1f, 0x75, ++ 0x17, 0xd4, 0x9f, 0xf6, 0xe2, 0x77, 0x6a, 0x4e, 0xdd, 0xe3, 0x65, 0xf9, ++ 0x9f, 0x87, 0x02, 0xc9, 0xb1, 0xf0, 0x7e, 0x24, 0xcb, 0x17, 0x5a, 0xf5, ++ 0xb3, 0x3f, 0x4d, 0x60, 0xdf, 0x7f, 0x69, 0x43, 0xba, 0xbd, 0x1a, 0x64, ++ 0xfe, 0xd8, 0xe9, 0x83, 0xff, 0xfe, 0x5b, 0xc8, 0x1f, 0x3e, 0x7d, 0xd0, ++ 0x1b, 0x86, 0x75, 0x34, 0x1d, 0xca, 0xc2, 0xf3, 0xad, 0xa6, 0xa7, 0x7d, ++ 0x18, 0xa7, 0x39, 0xf5, 0xb3, 0x3f, 0x4d, 0xb6, 0xe7, 0x33, 0x7d, 0xd6, ++ 0xf5, 0x2c, 0xe7, 0xdf, 0x41, 0x3c, 0x15, 0x20, 0x75, 0x90, 0xa7, 0x7c, ++ 0x2a, 0x87, 0x9d, 0x1b, 0x34, 0xfd, 0x74, 0xca, 0x4e, 0xb8, 0x47, 0xb4, ++ 0x6c, 0xff, 0x61, 0x0d, 0xce, 0x63, 0xa6, 0x3f, 0xf3, 0x97, 0x09, 0xa0, ++ 0x77, 0x4e, 0xed, 0x63, 0xf6, 0xc4, 0x07, 0x9e, 0x9e, 0x87, 0xe1, 0x9c, ++ 0xf5, 0x77, 0xc1, 0x1b, 0xd7, 0x78, 0x20, 0xbe, 0x0b, 0xfb, 0xf5, 0x30, ++ 0x42, 0x5a, 0xb2, 0x93, 0x57, 0xc4, 0x8d, 0x74, 0x78, 0x61, 0x78, 0x38, ++ 0x45, 0xf1, 0x00, 0xeb, 0xa2, 0x78, 0x69, 0x00, 0x7d, 0x99, 0x09, 0x1f, ++ 0xff, 0xe7, 0x1f, 0x16, 0x1f, 0x7f, 0x9c, 0x0f, 0xf3, 0x37, 0x1e, 0xbc, ++ 0x14, 0xe5, 0xa6, 0x1f, 0x2f, 0x92, 0xc5, 0x9e, 0x07, 0x92, 0x70, 0xb5, ++ 0x89, 0xae, 0x9f, 0x3d, 0x3f, 0xf4, 0xa7, 0x09, 0x60, 0x1f, 0xfd, 0xa1, ++ 0xab, 0x15, 0xf7, 0xf9, 0x81, 0xd6, 0x5d, 0x98, 0xfd, 0xff, 0xda, 0xba, ++ 0xa5, 0xd4, 0x60, 0xd6, 0x5d, 0xf5, 0x0f, 0xbb, 0x6e, 0xc6, 0xff, 0x87, ++ 0x82, 0x61, 0x96, 0xf7, 0xe7, 0x92, 0x83, 0xb3, 0xf9, 0xfc, 0xc7, 0x77, ++ 0x60, 0xfd, 0x87, 0x81, 0x08, 0xc2, 0x3b, 0x48, 0xf9, 0xaf, 0xfb, 0x87, ++ 0x5d, 0xff, 0xa7, 0xa4, 0xfb, 0x3e, 0x4a, 0xf7, 0xe0, 0xc0, 0x74, 0xff, ++ 0x2f, 0xd9, 0xec, 0x5c, 0xf8, 0x1f, 0x6f, 0xdd, 0x03, 0xd1, 0xfd, 0x05, ++ 0x4e, 0xf7, 0x80, 0x09, 0x79, 0x08, 0xa7, 0x7e, 0xf6, 0x17, 0x8c, 0xaf, ++ 0x8b, 0xf5, 0x0f, 0xb4, 0xee, 0xcd, 0xff, 0x41, 0xd7, 0x2d, 0xec, 0xa1, ++ 0x75, 0x72, 0x24, 0x51, 0x5c, 0x04, 0x79, 0xd8, 0xa9, 0xee, 0xb0, 0x04, ++ 0xbf, 0xc3, 0x33, 0x37, 0x01, 0x61, 0x29, 0x85, 0xe7, 0x5d, 0xbb, 0xe1, ++ 0x7a, 0x3e, 0x9b, 0xf9, 0x17, 0x8a, 0xc4, 0xe2, 0x36, 0x64, 0x24, 0x8b, ++ 0x1f, 0x11, 0xee, 0x6f, 0xf4, 0xfd, 0x5e, 0xac, 0xc1, 0xee, 0x57, 0xa9, ++ 0xc6, 0x6a, 0xf6, 0x3d, 0x32, 0x35, 0x82, 0xdf, 0xd5, 0x5b, 0x77, 0xc1, ++ 0xc2, 0x08, 0xe6, 0x76, 0x90, 0x8a, 0x57, 0x63, 0x50, 0x1f, 0x31, 0x15, ++ 0x7f, 0xe7, 0xd6, 0xed, 0x77, 0xb5, 0x49, 0xc4, 0x92, 0xa8, 0xfd, 0xa7, ++ 0x5e, 0xf0, 0xd5, 0xa3, 0x60, 0xff, 0x7b, 0xca, 0xe4, 0x94, 0x77, 0x02, ++ 0x96, 0x6f, 0x42, 0xb9, 0x86, 0xc7, 0xbd, 0x3c, 0xa6, 0xe6, 0xf0, 0x37, ++ 0x0c, 0x97, 0x9f, 0xe0, 0x0b, 0x3b, 0xdf, 0x7b, 0xf9, 0x78, 0x3a, 0xa9, ++ 0x48, 0xc0, 0xef, 0x77, 0xeb, 0x86, 0x6a, 0x26, 0xe9, 0xfc, 0x46, 0x35, ++ 0xfb, 0xfd, 0x68, 0xc8, 0xed, 0x4c, 0xd8, 0xce, 0x0d, 0xbd, 0xc4, 0xd6, ++ 0x9f, 0x8e, 0xb7, 0x03, 0x7e, 0x93, 0xc5, 0x66, 0x4f, 0x9e, 0x2f, 0xfe, ++ 0xfe, 0x94, 0xcd, 0xfc, 0x4f, 0x45, 0xaa, 0xe8, 0x86, 0xbc, 0x58, 0x32, ++ 0x5e, 0x66, 0xdf, 0x35, 0x27, 0xec, 0x5e, 0xf1, 0xba, 0x11, 0x91, 0xe4, ++ 0x3a, 0xf4, 0x43, 0x99, 0x7f, 0xd9, 0x8f, 0xcf, 0xd5, 0xdd, 0x80, 0x47, ++ 0x95, 0x50, 0xff, 0x90, 0xad, 0x0f, 0xfd, 0x4a, 0xc2, 0xfd, 0x49, 0x95, ++ 0x0f, 0xa1, 0x96, 0xc9, 0x96, 0xcf, 0xd9, 0x8e, 0xfb, 0x4b, 0x03, 0xd2, ++ 0x87, 0xd1, 0x63, 0x54, 0x23, 0xa7, 0xcf, 0x0a, 0x07, 0x3d, 0x04, 0xfe, ++ 0xd3, 0xd0, 0xc5, 0x41, 0x0f, 0x81, 0xdf, 0xf3, 0xa5, 0x8b, 0x9b, 0x1e, ++ 0x6e, 0xbc, 0xff, 0x22, 0x9b, 0xc5, 0xe7, 0xdc, 0x74, 0x72, 0xe4, 0x83, ++ 0xe4, 0x33, 0xbf, 0x24, 0x45, 0x0d, 0xe4, 0x9f, 0xef, 0xdd, 0x89, 0x71, ++ 0x91, 0xf7, 0x7f, 0xf0, 0xe6, 0x55, 0xd0, 0x7e, 0xe9, 0x4f, 0x15, 0x02, ++ 0xbf, 0x8b, 0xf6, 0xc1, 0xde, 0x00, 0x49, 0x81, 0xfc, 0xaa, 0x49, 0x0d, ++ 0xfc, 0xac, 0x25, 0xfb, 0x15, 0x8c, 0x0b, 0xff, 0x5f, 0x82, 0x42, 0xfc, ++ 0xff, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d, 0x7b, 0x7c, 0x54, 0xd5, ++ 0xb5, 0xf0, 0x3e, 0x73, 0xce, 0x4c, 0x66, 0x92, 0x49, 0x32, 0x49, 0x66, ++ 0x26, 0x33, 0x79, 0x31, 0x49, 0x20, 0x82, 0x46, 0x98, 0x04, 0x08, 0xa8, ++ 0x28, 0x13, 0x02, 0x08, 0x42, 0xaf, 0x03, 0x8a, 0x60, 0x6f, 0xd4, 0x91, ++ 0x67, 0x30, 0x4f, 0x90, 0xb6, 0xb4, 0xd5, 0x1f, 0x03, 0x89, 0x31, 0x3c, ++ 0x6c, 0x83, 0x22, 0x0f, 0x4b, 0x75, 0x40, 0x54, 0x5a, 0xa9, 0x0d, 0x18, ++ 0x29, 0x28, 0xda, 0x41, 0x1e, 0x62, 0xad, 0x5f, 0xa3, 0xd2, 0x5b, 0x6c, ++ 0xb1, 0x37, 0xe2, 0x03, 0x15, 0x08, 0x29, 0xad, 0xfd, 0xe8, 0xbd, 0xf6, ++ 0x72, 0xd7, 0x5a, 0x7b, 0xef, 0xcc, 0x39, 0x93, 0x89, 0x68, 0x6f, 0x7f, ++ 0xf7, 0xfb, 0xe7, 0xcb, 0x3f, 0x27, 0xfb, 0x9c, 0x7d, 0xf6, 0x5e, 0x7b, ++ 0xbd, 0xd7, 0xda, 0xeb, 0xec, 0xb9, 0x74, 0x09, 0xfe, 0xc6, 0x33, 0x76, ++ 0x49, 0x5c, 0x19, 0x6b, 0x66, 0xcc, 0xc5, 0x58, 0xed, 0xcf, 0x53, 0x19, ++ 0x73, 0x32, 0x76, 0xcf, 0x9e, 0xa4, 0xc8, 0xf4, 0x42, 0xb8, 0xee, 0xfd, ++ 0x60, 0x38, 0xbb, 0x9a, 0xb1, 0x9e, 0x55, 0xbd, 0x47, 0x73, 0xe1, 0x7e, ++ 0xf8, 0xa7, 0x8a, 0xff, 0x29, 0xec, 0x1e, 0xee, 0x1e, 0x7e, 0x0b, 0xdc, ++ 0xbf, 0x47, 0x63, 0x77, 0x05, 0x4b, 0x63, 0xe3, 0xc8, 0x6b, 0xa6, 0xc3, ++ 0xc4, 0xd8, 0x68, 0xc6, 0xce, 0xee, 0x4f, 0x99, 0x13, 0xb1, 0x33, 0xa6, ++ 0xec, 0x3c, 0x78, 0x27, 0x8d, 0xdb, 0x31, 0xdb, 0x9c, 0xa4, 0xc4, 0xfa, ++ 0xd9, 0x1c, 0x66, 0x9a, 0x17, 0xfa, 0x05, 0xf0, 0x79, 0xf8, 0x27, 0x4a, ++ 0x64, 0x88, 0xd2, 0x7f, 0x3c, 0xc6, 0x56, 0xf2, 0xf1, 0x7e, 0xa2, 0x70, ++ 0xf8, 0xf6, 0x99, 0x23, 0x36, 0x84, 0x6f, 0xe7, 0x36, 0x4b, 0x08, 0xe0, ++ 0x68, 0xdc, 0xf9, 0x27, 0x4b, 0x00, 0xe0, 0xa8, 0xfa, 0xf9, 0xcf, 0xd2, ++ 0xba, 0x61, 0xbe, 0xc6, 0x7d, 0x2a, 0x8b, 0x0e, 0x65, 0xf4, 0x77, 0x89, ++ 0xe1, 0x73, 0x35, 0x9a, 0x34, 0x9c, 0xae, 0xef, 0xe3, 0x95, 0xb1, 0x80, ++ 0x5d, 0xa9, 0x60, 0xac, 0x01, 0xff, 0xf5, 0xc1, 0xb5, 0xb3, 0x7e, 0x3a, ++ 0x4b, 0x83, 0x6b, 0xc7, 0xda, 0x3f, 0xa9, 0x69, 0xf8, 0xbe, 0xf9, 0x54, ++ 0xb7, 0x35, 0xf6, 0x7e, 0xed, 0xcf, 0x5f, 0xde, 0x1b, 0x06, 0xd4, 0xd4, ++ 0x3e, 0xff, 0x4c, 0x9a, 0x0f, 0xae, 0x9f, 0x75, 0x3d, 0x95, 0xc6, 0x4a, ++ 0x69, 0xbc, 0xbb, 0x2d, 0xe9, 0x8c, 0x69, 0x76, 0xcd, 0xd0, 0x1f, 0xc7, ++ 0xbd, 0x98, 0xd9, 0x7f, 0x1c, 0x98, 0x97, 0x31, 0x37, 0xdc, 0xe7, 0xb7, ++ 0x58, 0x63, 0xc7, 0x6a, 0x3e, 0x5f, 0xe7, 0x37, 0x4e, 0x33, 0x84, 0x8f, ++ 0xc1, 0x38, 0x12, 0x6e, 0x58, 0xdf, 0x67, 0xf8, 0x8f, 0x97, 0xb1, 0xb1, ++ 0x8e, 0x54, 0xe7, 0xc7, 0x57, 0xc1, 0xff, 0x63, 0xd8, 0x98, 0x4b, 0x2a, ++ 0x5c, 0x77, 0x66, 0x31, 0x76, 0x4d, 0x7f, 0x3c, 0xc5, 0xf0, 0x15, 0xe6, ++ 0xf4, 0xfc, 0xd9, 0xe7, 0x8f, 0x87, 0x01, 0x3f, 0x67, 0xf7, 0x9c, 0x79, ++ 0x1c, 0xe1, 0xaf, 0xfb, 0xaf, 0x3f, 0x3f, 0xfe, 0x7d, 0xc0, 0x1f, 0x7b, ++ 0xc5, 0xe6, 0x78, 0x0a, 0xd6, 0xdd, 0xf8, 0xd3, 0xdf, 0xa6, 0x21, 0x7d, ++ 0xe5, 0x7b, 0x33, 0x1d, 0x0a, 0xbd, 0xd7, 0x93, 0xcf, 0xc2, 0x5e, 0xe8, ++ 0xd7, 0xf3, 0x6e, 0x52, 0x24, 0x0c, 0xb7, 0x7a, 0x5e, 0x3e, 0x5d, 0xe0, ++ 0x83, 0xf5, 0xf6, 0xec, 0xfe, 0x9b, 0xdb, 0x07, 0xfd, 0x97, 0xbd, 0x3c, ++ 0x29, 0x1b, 0xd7, 0xbf, 0xec, 0x85, 0xaa, 0x6c, 0x66, 0x1f, 0x18, 0x8e, ++ 0x9e, 0x15, 0x8c, 0x45, 0x92, 0xf4, 0x70, 0x45, 0x88, 0x8e, 0xbe, 0x7d, ++ 0x30, 0x68, 0x36, 0x34, 0x0f, 0x88, 0x6b, 0x1c, 0x3d, 0x0e, 0x75, 0x1e, ++ 0x2a, 0x40, 0x38, 0xcf, 0x9d, 0x48, 0xf2, 0x27, 0x21, 0x9e, 0xe0, 0xde, ++ 0xf2, 0x72, 0xa4, 0x0f, 0xd0, 0x69, 0x38, 0x6f, 0xdf, 0x07, 0xf8, 0x6d, ++ 0xd8, 0xf5, 0xe0, 0x9f, 0xd4, 0xe1, 0x89, 0xf0, 0x1c, 0xce, 0x35, 0x79, ++ 0x90, 0xae, 0x1f, 0x4c, 0x46, 0x38, 0x19, 0x8b, 0xe6, 0x32, 0x0f, 0xe2, ++ 0xb7, 0xb7, 0xd5, 0x61, 0xef, 0xdf, 0xbf, 0x8f, 0x5e, 0xc7, 0x81, 0x9e, ++ 0x23, 0xbe, 0x02, 0xdd, 0x76, 0xad, 0xe6, 0xf3, 0x76, 0x00, 0xdd, 0xd2, ++ 0xfa, 0xd3, 0xed, 0x1c, 0xfe, 0x03, 0xf4, 0x69, 0x44, 0xba, 0xa5, 0xc4, ++ 0xe8, 0xf6, 0x39, 0x0b, 0x3d, 0xe1, 0x2d, 0x86, 0x76, 0x67, 0x16, 0xd1, ++ 0x35, 0x11, 0xbe, 0xa2, 0x5f, 0x01, 0x5f, 0x35, 0x0a, 0x1f, 0xff, 0x7a, ++ 0x47, 0xe0, 0x7b, 0x0e, 0x94, 0x9f, 0x3d, 0x29, 0x7d, 0xf4, 0x9a, 0x8e, ++ 0xf4, 0xfa, 0xd9, 0xe7, 0x05, 0x0c, 0xe8, 0xfd, 0x89, 0xb9, 0xf7, 0x4e, ++ 0x36, 0x8a, 0xb1, 0xde, 0x97, 0x93, 0x1c, 0xdb, 0xe1, 0xfe, 0x3d, 0x2f, ++ 0xff, 0x8e, 0xe4, 0xa4, 0xe7, 0x85, 0xb7, 0x2c, 0x48, 0x47, 0xf8, 0xb3, ++ 0x2b, 0xb0, 0xae, 0x1e, 0xd6, 0xf7, 0xd7, 0x85, 0xeb, 0x6c, 0x50, 0xc4, ++ 0x3a, 0x77, 0xa4, 0x46, 0x93, 0xd2, 0x62, 0x78, 0x6f, 0x88, 0xcc, 0x98, ++ 0xe2, 0x4b, 0xa3, 0xfb, 0xef, 0xd3, 0xfd, 0x08, 0xe7, 0x5f, 0xc4, 0x5f, ++ 0x2e, 0xd2, 0x27, 0x72, 0xf0, 0x56, 0x25, 0x01, 0x3d, 0x3a, 0x1c, 0x45, ++ 0xb4, 0x0e, 0x16, 0x71, 0xd1, 0xba, 0xeb, 0x77, 0xfc, 0xc1, 0x82, 0x7c, ++ 0x23, 0xe9, 0x84, 0xf4, 0x51, 0xc6, 0x22, 0xbd, 0xde, 0x9f, 0x8c, 0xf7, ++ 0x25, 0x9d, 0xe4, 0xba, 0xe3, 0xc7, 0x73, 0x20, 0x1e, 0xc6, 0xe8, 0xe8, ++ 0xb6, 0x83, 0xcb, 0x61, 0x7f, 0xba, 0xf6, 0x5a, 0x58, 0x71, 0x22, 0x7a, ++ 0x01, 0xbc, 0xf8, 0x1e, 0xc2, 0x0b, 0xed, 0x9e, 0x6d, 0x49, 0x9a, 0x92, ++ 0xce, 0xef, 0xe7, 0xc1, 0x3a, 0x7a, 0xcc, 0x6c, 0x4e, 0x07, 0xc2, 0x11, ++ 0x51, 0x7e, 0x97, 0x88, 0xbe, 0x8c, 0xad, 0xa2, 0xf5, 0x3c, 0x1b, 0x2f, ++ 0x97, 0x62, 0x7d, 0x97, 0x93, 0xcb, 0xcb, 0xc1, 0xfd, 0x8f, 0xe2, 0xe5, ++ 0xc7, 0x0e, 0x07, 0x8d, 0x2f, 0xf1, 0x73, 0xf6, 0x8b, 0xc4, 0xfa, 0xf9, ++ 0x28, 0xca, 0x39, 0xc0, 0xbf, 0xcf, 0x1e, 0x3a, 0x82, 0xfc, 0xc3, 0x98, ++ 0x35, 0xf2, 0x21, 0x8c, 0x73, 0x17, 0x53, 0x58, 0x7a, 0x71, 0x0c, 0x6f, ++ 0x12, 0xde, 0xb3, 0x1a, 0x23, 0xbd, 0x7b, 0xf6, 0xa7, 0x6a, 0x24, 0x0c, ++ 0xeb, 0x6f, 0xed, 0x38, 0x44, 0x7a, 0x36, 0x5e, 0xbe, 0x61, 0x5d, 0x81, ++ 0x8e, 0x04, 0xf3, 0xfd, 0x4e, 0xcc, 0xd7, 0xb0, 0xef, 0xe0, 0x70, 0xd4, ++ 0x43, 0x67, 0x5f, 0xdd, 0x4f, 0xfc, 0xd7, 0xb0, 0xeb, 0x7d, 0x4b, 0x18, ++ 0xc6, 0x39, 0xba, 0xf3, 0x79, 0x4b, 0x77, 0x69, 0x8c, 0xdf, 0x51, 0x7f, ++ 0x47, 0x74, 0xfa, 0xfb, 0xec, 0x73, 0x07, 0x87, 0x93, 0xbe, 0xc5, 0xf1, ++ 0x13, 0xe8, 0x9b, 0x0f, 0xc5, 0xf8, 0x8d, 0x07, 0x8c, 0xe3, 0x37, 0xee, ++ 0xfa, 0x93, 0x61, 0xfc, 0xda, 0x70, 0x87, 0xc5, 0x61, 0xbf, 0xfc, 0x3c, ++ 0x9f, 0x69, 0x81, 0xd9, 0xb8, 0xde, 0xcf, 0xba, 0xcc, 0x0c, 0xf5, 0xdf, ++ 0x67, 0x1d, 0xea, 0x94, 0x48, 0x82, 0x79, 0x5f, 0x17, 0xf6, 0x4b, 0xe2, ++ 0xa9, 0xf5, 0x2d, 0x0b, 0xd9, 0xb1, 0x51, 0x6f, 0x27, 0x47, 0x92, 0x00, ++ 0x4f, 0xcb, 0xde, 0x9a, 0xf2, 0x87, 0x74, 0x27, 0x5e, 0x2d, 0x3e, 0x40, ++ 0x2d, 0xeb, 0x5c, 0xc9, 0xf9, 0xaa, 0xf3, 0xfe, 0x40, 0x2e, 0xd2, 0xa5, ++ 0xf3, 0xad, 0x6f, 0xaa, 0x68, 0x4f, 0xf6, 0x22, 0x1e, 0xaf, 0x88, 0x8d, ++ 0x5b, 0x71, 0xbc, 0xa9, 0x2a, 0x15, 0xe4, 0xb6, 0xe2, 0x64, 0x70, 0x14, ++ 0xb2, 0x55, 0xbc, 0x3e, 0x18, 0x73, 0xc2, 0x64, 0x80, 0x1b, 0xe6, 0xc9, ++ 0x46, 0xfd, 0xdc, 0x02, 0xe3, 0xf8, 0x60, 0x1c, 0xa6, 0xf9, 0x3d, 0x41, ++ 0x18, 0x57, 0x4d, 0x9b, 0x3c, 0x05, 0xe1, 0x51, 0x1d, 0x26, 0x87, 0x2d, ++ 0xa1, 0x5d, 0xe5, 0xe3, 0x99, 0xed, 0x41, 0x16, 0x02, 0xb8, 0xcc, 0x60, ++ 0xb7, 0x7d, 0x3a, 0x7e, 0xf2, 0xcc, 0x4c, 0x1b, 0xce, 0xd2, 0x71, 0x79, ++ 0x5e, 0x13, 0xea, 0x85, 0xa5, 0xc0, 0x5e, 0xa8, 0x9f, 0x3d, 0x16, 0x36, ++ 0x54, 0x03, 0xf8, 0x98, 0x29, 0xd9, 0xff, 0x14, 0x8c, 0xbb, 0x74, 0x58, ++ 0xa0, 0xec, 0x08, 0xb4, 0x97, 0x2e, 0xf0, 0xf8, 0xc3, 0xf0, 0xdc, 0x7b, ++ 0x0b, 0x7f, 0xef, 0x9c, 0xc3, 0x1e, 0x36, 0x8d, 0xc0, 0x76, 0x41, 0x04, ++ 0xe5, 0x28, 0xe5, 0xa2, 0xca, 0x7c, 0xa0, 0xfa, 0xce, 0x2a, 0xbf, 0x5e, ++ 0xc8, 0x40, 0x25, 0xa4, 0x08, 0xbe, 0xca, 0xed, 0x48, 0x21, 0x3b, 0x93, ++ 0xa2, 0xf9, 0x36, 0x55, 0x43, 0x3b, 0xa5, 0x46, 0xf3, 0x03, 0x46, 0xd9, ++ 0x47, 0xf6, 0x50, 0x7e, 0x86, 0x0b, 0xdf, 0xb3, 0xd0, 0x7b, 0xde, 0x0c, ++ 0x45, 0xfb, 0x18, 0xd7, 0x9d, 0xc6, 0xd2, 0x50, 0xde, 0xe4, 0xf8, 0xb2, ++ 0x9f, 0x1c, 0x97, 0x69, 0xd1, 0xe1, 0xb8, 0x7e, 0x66, 0x65, 0x1a, 0x03, ++ 0xbb, 0x92, 0xc7, 0x38, 0xdc, 0xaa, 0x58, 0x4f, 0x31, 0xeb, 0x52, 0x90, ++ 0xbf, 0x9b, 0x67, 0xa4, 0x6d, 0xc7, 0xf6, 0xd6, 0xd4, 0x1a, 0xb2, 0xff, ++ 0x05, 0xac, 0xf7, 0x60, 0x00, 0xe8, 0xf6, 0x64, 0xda, 0xe4, 0x63, 0xa8, ++ 0xc7, 0xe0, 0x5f, 0x13, 0xf6, 0xcb, 0x6f, 0x32, 0xda, 0xf7, 0x41, 0xcb, ++ 0x8d, 0xed, 0xc2, 0xb0, 0x16, 0x27, 0xbf, 0x3e, 0x53, 0x10, 0xf8, 0xaf, ++ 0xb8, 0xcd, 0x78, 0xdf, 0x59, 0x55, 0xb9, 0x64, 0x90, 0x1f, 0xe4, 0x6c, ++ 0x7d, 0xe7, 0x14, 0x0d, 0xf4, 0xb7, 0x73, 0x76, 0xe5, 0xee, 0x5c, 0xc0, ++ 0xe9, 0xb4, 0x35, 0x6f, 0xf3, 0xf6, 0x33, 0x95, 0x65, 0x5e, 0x68, 0x1f, ++ 0x5f, 0x5f, 0x37, 0x55, 0x03, 0x3d, 0xe2, 0xfc, 0x4d, 0x65, 0x59, 0x01, ++ 0xb4, 0xcf, 0x3f, 0xfc, 0x9d, 0xa9, 0xf4, 0xbc, 0x16, 0x90, 0x74, 0x2d, ++ 0xa8, 0xfe, 0xf5, 0x57, 0x4f, 0x0d, 0x97, 0xc6, 0xe4, 0xd6, 0x05, 0x60, ++ 0xa6, 0xab, 0x24, 0xcf, 0x37, 0x20, 0x1e, 0xce, 0x05, 0xcf, 0xb6, 0xe2, ++ 0xd3, 0xfa, 0x59, 0x7f, 0xb5, 0xc0, 0x23, 0xfc, 0x0b, 0x22, 0x1e, 0xf2, ++ 0xc7, 0x72, 0x3c, 0xe4, 0xd9, 0x4f, 0xee, 0x66, 0xd0, 0x7f, 0x90, 0xa9, ++ 0x7b, 0x25, 0xf2, 0xe5, 0x13, 0x2f, 0xff, 0xdf, 0x0c, 0xec, 0xe7, 0x63, ++ 0x0e, 0x5a, 0xaf, 0x83, 0xb5, 0x38, 0x3e, 0xb6, 0xe2, 0xe2, 0xd9, 0xd8, ++ 0x4b, 0x23, 0xbf, 0x4c, 0x9f, 0x69, 0xec, 0x63, 0xc9, 0x87, 0x6a, 0x4c, ++ 0x0e, 0x54, 0x77, 0xe8, 0xe6, 0x0c, 0xe0, 0xab, 0xd6, 0xb9, 0x43, 0x37, ++ 0x4d, 0x46, 0x5d, 0x5b, 0xe7, 0x27, 0xfe, 0x82, 0x99, 0x1d, 0x64, 0x0f, ++ 0x65, 0x7f, 0x87, 0x93, 0xe8, 0x33, 0x5f, 0xd0, 0x07, 0xe1, 0xb4, 0x02, ++ 0x9f, 0x2d, 0xe0, 0x5d, 0xd8, 0x22, 0x35, 0x6c, 0x61, 0x34, 0x6e, 0xbb, ++ 0x25, 0x48, 0xf6, 0x6a, 0xa2, 0x03, 0xe7, 0x53, 0xc2, 0x75, 0xea, 0xa5, ++ 0xab, 0xbe, 0x3e, 0x5c, 0xf3, 0x90, 0x7f, 0x90, 0x1e, 0xa9, 0x2c, 0x15, ++ 0xef, 0x6b, 0x75, 0x3e, 0x82, 0xef, 0xb0, 0x2b, 0xb0, 0x90, 0xf0, 0xe6, ++ 0x0a, 0xd1, 0x55, 0xde, 0xf7, 0xcc, 0x9d, 0xe3, 0x0b, 0x01, 0x9e, 0x6f, ++ 0xc8, 0x08, 0xd6, 0xe0, 0x7a, 0xbc, 0x0b, 0x2f, 0x16, 0xe0, 0x3a, 0xa6, ++ 0x67, 0x30, 0x1a, 0xaf, 0x6a, 0x91, 0x3d, 0x80, 0xf6, 0xf5, 0xc2, 0x01, ++ 0x50, 0x83, 0x09, 0xe4, 0x4b, 0x5e, 0xb7, 0xaf, 0x60, 0x7e, 0x6d, 0xc8, ++ 0xc0, 0xcf, 0x83, 0x99, 0xa1, 0x6f, 0xe3, 0xbc, 0x45, 0xbf, 0xf4, 0xed, ++ 0x39, 0x06, 0xe3, 0x8d, 0x98, 0x6f, 0xf1, 0xdb, 0x60, 0x8a, 0x11, 0xcb, ++ 0x47, 0xf9, 0xb5, 0x2c, 0xc6, 0x17, 0x84, 0xfe, 0x87, 0xa0, 0x9f, 0x07, ++ 0x69, 0x8a, 0xf2, 0xf7, 0x6d, 0x16, 0x41, 0xf9, 0x3b, 0x9f, 0xa4, 0x04, ++ 0x02, 0xd0, 0x3e, 0x7f, 0xaf, 0x83, 0xf4, 0x73, 0xde, 0xfc, 0xe9, 0xc7, ++ 0xd0, 0xae, 0x9d, 0x4f, 0x29, 0xec, 0x88, 0xe2, 0xfd, 0xef, 0xfb, 0x48, ++ 0x2e, 0xc1, 0x13, 0x50, 0x50, 0x2e, 0xf2, 0x0f, 0xa4, 0x47, 0x6d, 0x69, ++ 0xc4, 0xd7, 0x7f, 0x8d, 0xe3, 0xeb, 0xbf, 0x1a, 0xf9, 0xd8, 0x38, 0xef, ++ 0xf9, 0x4b, 0xbe, 0x7d, 0xdd, 0x34, 0x9e, 0x43, 0x8c, 0x07, 0x8e, 0x11, ++ 0x3c, 0xcf, 0x17, 0xf4, 0x3a, 0xaf, 0x72, 0xff, 0xfc, 0xfc, 0x0a, 0x1f, ++ 0xc1, 0x01, 0x6e, 0xe4, 0x41, 0xb4, 0xbb, 0x5f, 0x75, 0xbe, 0x47, 0x33, ++ 0x84, 0x3d, 0x15, 0xf4, 0xb9, 0xdf, 0x16, 0xd8, 0x88, 0x78, 0x01, 0xfc, ++ 0x6f, 0xd6, 0xe3, 0x7f, 0xeb, 0xc0, 0x74, 0x7c, 0x42, 0xd0, 0xf1, 0x89, ++ 0x44, 0x74, 0x5c, 0x68, 0x6d, 0x2a, 0x40, 0xfd, 0x70, 0x4f, 0xb0, 0x63, ++ 0x32, 0x68, 0x6e, 0x36, 0x23, 0x23, 0xb4, 0x03, 0xc7, 0x3d, 0xbd, 0xf0, ++ 0x68, 0xab, 0x19, 0xd6, 0x53, 0x5f, 0xdd, 0x54, 0x82, 0x4c, 0xdf, 0x9f, ++ 0xbe, 0x0a, 0xe9, 0x73, 0xf7, 0x81, 0xbb, 0x57, 0x9a, 0xa1, 0xdd, 0x88, ++ 0xf4, 0xf1, 0xf5, 0xa7, 0xe3, 0x88, 0xe5, 0x65, 0x44, 0x2f, 0x1d, 0x5d, ++ 0x3b, 0x10, 0x8e, 0x11, 0x07, 0xfe, 0x64, 0x42, 0xb8, 0x25, 0x3d, 0x37, ++ 0x29, 0xdc, 0x0e, 0xc4, 0xbf, 0xff, 0x52, 0x86, 0x22, 0xe6, 0xad, 0x5b, ++ 0x69, 0x06, 0x3c, 0x5e, 0xd8, 0x67, 0x21, 0xff, 0x37, 0xbe, 0xdf, 0x91, ++ 0x0c, 0x1f, 0xf5, 0x93, 0xed, 0xe1, 0xd6, 0x0a, 0xbf, 0x06, 0x72, 0x9a, ++ 0x6d, 0x62, 0xa1, 0x44, 0xe3, 0x1e, 0xe9, 0x37, 0xae, 0xd5, 0x9f, 0x94, ++ 0x00, 0xfe, 0xbe, 0xf1, 0x1c, 0x7c, 0x3c, 0xc0, 0xfb, 0x6b, 0x7a, 0xbc, ++ 0xbf, 0x21, 0xf5, 0x6f, 0x7f, 0xbc, 0xff, 0x1f, 0xec, 0x07, 0x78, 0xa7, ++ 0xeb, 0x57, 0xc0, 0xfb, 0x3b, 0x5f, 0x86, 0x77, 0xe9, 0x6f, 0xd7, 0x0a, ++ 0xbd, 0x50, 0xcb, 0xd6, 0x91, 0x9f, 0xf9, 0x51, 0x60, 0xa6, 0x7b, 0x30, ++ 0xcc, 0x3b, 0x59, 0xb5, 0x13, 0xff, 0x2f, 0x7e, 0x4a, 0x25, 0xb9, 0x83, ++ 0xfe, 0xd3, 0xbd, 0xee, 0x98, 0x1e, 0x59, 0x7c, 0x4d, 0xd3, 0x41, 0x5c, ++ 0xe7, 0xe2, 0x1f, 0x2b, 0xc4, 0xa7, 0xf3, 0x43, 0x5c, 0xbf, 0x9f, 0x59, ++ 0x38, 0xfd, 0x28, 0xea, 0xf5, 0x05, 0xed, 0x46, 0xbf, 0x69, 0xe1, 0x1c, ++ 0xd0, 0x33, 0x00, 0xdf, 0xa2, 0xcd, 0xc6, 0xfb, 0x8b, 0x23, 0x71, 0x71, ++ 0x20, 0xd3, 0xe9, 0x73, 0xe0, 0x87, 0x33, 0x31, 0x7e, 0x1d, 0xc4, 0xf5, ++ 0x8c, 0x87, 0xec, 0xa4, 0x2a, 0xe4, 0xa1, 0x6a, 0x51, 0x69, 0x3a, 0xfa, ++ 0x49, 0xaf, 0x98, 0x7d, 0xbf, 0x21, 0x3f, 0xfc, 0x75, 0x95, 0x6d, 0x4f, ++ 0x80, 0xf7, 0xfc, 0xcc, 0x42, 0xb2, 0xc3, 0x7d, 0xed, 0x26, 0x40, 0x86, ++ 0xce, 0xbe, 0xb3, 0xf9, 0x36, 0x13, 0xea, 0x49, 0x39, 0xee, 0xc4, 0x45, ++ 0xa5, 0xd9, 0xe8, 0xcf, 0x2c, 0x4d, 0xf5, 0x7d, 0x69, 0xfc, 0x35, 0x68, ++ 0xb9, 0xd1, 0x9e, 0x17, 0x86, 0x93, 0x99, 0x4f, 0x37, 0x6e, 0x71, 0x5b, ++ 0xa6, 0xa1, 0x3d, 0xa4, 0x3d, 0xc7, 0xd0, 0xff, 0x8a, 0xcd, 0x45, 0x86, ++ 0xe7, 0xc3, 0x22, 0x57, 0x1a, 0x9e, 0x5f, 0xb5, 0xb3, 0xdc, 0xd0, 0xbe, ++ 0xba, 0xe3, 0x5a, 0x43, 0xff, 0x11, 0xfb, 0x26, 0x18, 0xda, 0x65, 0xd1, ++ 0x9b, 0x0c, 0xfd, 0x47, 0x1e, 0x9b, 0x69, 0x68, 0x8f, 0xee, 0xfa, 0xa6, ++ 0xa1, 0xff, 0x98, 0x13, 0x73, 0x0d, 0xcf, 0xaf, 0xe9, 0xbe, 0xc7, 0xf0, ++ 0xfc, 0xba, 0x4f, 0x96, 0x1a, 0xda, 0xd7, 0xf7, 0x7e, 0xcf, 0xe8, 0xbf, ++ 0x98, 0x18, 0xe9, 0x45, 0x96, 0xac, 0x90, 0x9e, 0x3c, 0xbc, 0xe2, 0x93, ++ 0x8a, 0x0f, 0x91, 0x01, 0x47, 0x29, 0x13, 0x11, 0x9f, 0x55, 0x63, 0x79, ++ 0xdf, 0xc3, 0x4b, 0x2c, 0x26, 0x47, 0x1a, 0x5e, 0x4b, 0x4c, 0x0e, 0xe0, ++ 0x8f, 0x57, 0x17, 0x4c, 0x27, 0xfb, 0x7f, 0x78, 0x89, 0x3b, 0xe0, 0xa3, ++ 0x6b, 0x45, 0x00, 0xe3, 0x1e, 0xa6, 0x8e, 0x1b, 0x15, 0x4a, 0xe0, 0xdf, ++ 0x4e, 0x72, 0x7c, 0x5a, 0xf1, 0xa1, 0x6e, 0xde, 0x2a, 0xab, 0xd9, 0xa0, ++ 0xd7, 0x26, 0x39, 0x8c, 0xed, 0xf2, 0x4c, 0x11, 0x17, 0x0e, 0xe2, 0x7c, ++ 0x33, 0x26, 0xd3, 0x28, 0x57, 0x6a, 0xd3, 0xf4, 0xa8, 0x05, 0x9a, 0x39, ++ 0x8b, 0x07, 0x67, 0xe3, 0x7c, 0x20, 0x5f, 0xd7, 0x66, 0x72, 0xbd, 0x46, ++ 0xd7, 0xaf, 0x20, 0x5f, 0xe3, 0xb1, 0xdf, 0xe9, 0xb4, 0x68, 0x2b, 0xb6, ++ 0xa5, 0x7c, 0x31, 0x61, 0x5f, 0x2b, 0x05, 0x1f, 0xc1, 0x35, 0x60, 0x29, ++ 0x47, 0x86, 0x4a, 0x25, 0x3b, 0x1c, 0xc0, 0x9b, 0x3e, 0xba, 0x1f, 0xd6, ++ 0x20, 0x3e, 0x99, 0x60, 0xf5, 0xe7, 0x1d, 0xc1, 0xf5, 0x98, 0xfc, 0x4e, ++ 0x64, 0xbe, 0x89, 0x73, 0x82, 0x87, 0xcd, 0x9c, 0x03, 0xb9, 0x1d, 0x66, ++ 0x43, 0x4d, 0x5f, 0xc7, 0x0e, 0x4b, 0xf9, 0xf6, 0x98, 0x7c, 0x61, 0xb2, ++ 0x5f, 0x99, 0x8c, 0xf2, 0x49, 0x5b, 0x16, 0x94, 0xa4, 0x33, 0x1d, 0x5e, ++ 0xe7, 0x64, 0xf2, 0xfc, 0x11, 0xd8, 0x7d, 0x7e, 0x75, 0xec, 0x1c, 0xa9, ++ 0x49, 0xfc, 0x15, 0xe9, 0xef, 0x4f, 0x19, 0xad, 0x0d, 0x8d, 0xdd, 0x57, ++ 0x16, 0x4d, 0xcf, 0x46, 0x79, 0xf3, 0x0c, 0xa0, 0x07, 0x2d, 0x9e, 0xe2, ++ 0x61, 0x3b, 0x40, 0xff, 0x5a, 0xbc, 0x85, 0x74, 0x95, 0xf7, 0x5b, 0xe7, ++ 0x98, 0xa6, 0x44, 0x12, 0xd0, 0xb5, 0x36, 0x53, 0x11, 0x70, 0x70, 0x3f, ++ 0x6b, 0x58, 0xcc, 0xcf, 0xaa, 0x25, 0x7a, 0x78, 0xde, 0xde, 0x38, 0x04, ++ 0xf0, 0xd5, 0x50, 0xdd, 0x4b, 0x7e, 0x96, 0xc7, 0xd4, 0xbe, 0xe4, 0x28, ++ 0xae, 0xeb, 0x57, 0x2a, 0xcf, 0x93, 0x81, 0x27, 0x85, 0xfa, 0x60, 0x81, ++ 0xf0, 0x9b, 0x17, 0x4c, 0x7d, 0x78, 0xc9, 0x51, 0xd0, 0x4b, 0x0b, 0xde, ++ 0x1c, 0x42, 0x7a, 0x49, 0xce, 0xb3, 0x75, 0x45, 0x74, 0x98, 0xde, 0x3f, ++ 0xc8, 0x1b, 0x20, 0x8e, 0x7a, 0x3a, 0x93, 0xeb, 0xf1, 0xc7, 0x57, 0x04, ++ 0x86, 0xcd, 0x1f, 0x42, 0x70, 0x91, 0x5e, 0x90, 0x7e, 0x79, 0x41, 0xb8, ++ 0x7e, 0x32, 0xc6, 0x37, 0x83, 0x58, 0x13, 0xc5, 0x89, 0x1b, 0x4d, 0xac, ++ 0x26, 0xd1, 0x38, 0x0f, 0x8a, 0x71, 0xb2, 0x91, 0xe4, 0x08, 0xaf, 0xc3, ++ 0x4e, 0xf2, 0x71, 0x6e, 0xe1, 0xc9, 0x34, 0x0d, 0xd6, 0x91, 0x9c, 0x1a, ++ 0x7a, 0x10, 0xd7, 0x37, 0x77, 0x44, 0x57, 0x05, 0x8f, 0x03, 0x03, 0xfe, ++ 0x99, 0xe0, 0x7f, 0x15, 0x44, 0xef, 0xd8, 0x88, 0xfd, 0x0b, 0x3c, 0x1a, ++ 0x8b, 0x28, 0xfd, 0xe7, 0xcf, 0xae, 0x0e, 0xb5, 0x15, 0xc2, 0xfa, 0x5a, ++ 0x32, 0x4d, 0x7e, 0x3b, 0xb5, 0x7b, 0x15, 0xec, 0x9f, 0x74, 0x1f, 0x63, ++ 0x59, 0xd0, 0xbf, 0xe5, 0xbf, 0x54, 0x82, 0xa7, 0xe5, 0xd5, 0x6b, 0x18, ++ 0xc6, 0x67, 0x49, 0xf6, 0x26, 0x86, 0x7e, 0xac, 0x5c, 0xd7, 0xa1, 0xcc, ++ 0xc7, 0x08, 0x3f, 0x6a, 0x67, 0x0a, 0xd9, 0x3d, 0x86, 0x2e, 0x28, 0xe0, ++ 0xef, 0x5b, 0x82, 0xf6, 0x9f, 0x7b, 0xe6, 0x77, 0xa1, 0x7f, 0xf1, 0xf9, ++ 0x06, 0x33, 0xcd, 0xf7, 0x39, 0xac, 0xd1, 0x01, 0xe3, 0x7f, 0xde, 0xa9, ++ 0x46, 0xd0, 0x59, 0x3f, 0x9a, 0x99, 0x1c, 0x35, 0x41, 0x5b, 0x6d, 0x4b, ++ 0x25, 0x7b, 0x5d, 0x80, 0x3e, 0x27, 0xf4, 0x5f, 0xd8, 0x99, 0x1a, 0xf1, ++ 0x15, 0xc6, 0xf0, 0xa2, 0x6d, 0x1e, 0xc7, 0xa2, 0x60, 0xdf, 0x92, 0xf2, ++ 0xf8, 0xfa, 0x5b, 0x32, 0xed, 0x11, 0x7b, 0x21, 0xad, 0xfb, 0x87, 0x99, ++ 0xa3, 0x63, 0x70, 0xca, 0x75, 0xe7, 0x0f, 0x10, 0x77, 0xbe, 0x22, 0xe0, ++ 0x66, 0x81, 0xa1, 0x06, 0x3a, 0x7b, 0x21, 0x06, 0xeb, 0xc2, 0xb9, 0x35, ++ 0x70, 0xf6, 0x61, 0x1c, 0x75, 0x83, 0x99, 0xe2, 0xc2, 0x05, 0x19, 0x76, ++ 0x82, 0x33, 0xb2, 0x22, 0x3c, 0x6c, 0xbe, 0xb9, 0xff, 0xfa, 0x5a, 0x3d, ++ 0x33, 0x6f, 0xbe, 0x1d, 0xe0, 0x69, 0x3e, 0xae, 0x32, 0x15, 0xc6, 0xf1, ++ 0x75, 0xb7, 0x13, 0x3e, 0x16, 0x02, 0x3e, 0x22, 0xbe, 0xfe, 0xf8, 0x3e, ++ 0xe7, 0x2b, 0xfc, 0xab, 0x49, 0x25, 0xb8, 0x5f, 0x41, 0x7a, 0xa9, 0x9b, ++ 0x27, 0xd3, 0xba, 0x18, 0xfa, 0xf1, 0xf0, 0x5e, 0xfd, 0x13, 0x0a, 0x7b, ++ 0xac, 0x10, 0xf9, 0x32, 0x34, 0x85, 0xe8, 0x9c, 0x63, 0x62, 0x4f, 0x15, ++ 0x26, 0xf0, 0x0f, 0x50, 0xde, 0x5c, 0x88, 0x3f, 0x9e, 0x3f, 0xb0, 0x78, ++ 0x4a, 0xb8, 0x9c, 0x78, 0x06, 0x0f, 0xdb, 0x01, 0xe3, 0xfd, 0x2a, 0x73, ++ 0x40, 0x7f, 0xeb, 0xcd, 0x4c, 0x6e, 0xf7, 0xe9, 0x1a, 0xaf, 0x97, 0xc0, ++ 0xfe, 0x85, 0x11, 0x8e, 0x0b, 0x9b, 0x15, 0xa2, 0xe7, 0x69, 0x25, 0x62, ++ 0x31, 0x03, 0xca, 0x6a, 0x6f, 0x8d, 0x1a, 0xec, 0xbe, 0x1a, 0x50, 0xc9, ++ 0xdf, 0x88, 0x87, 0x0b, 0xf4, 0xd8, 0x89, 0x4c, 0x9d, 0x9f, 0xa3, 0xa6, ++ 0xdf, 0x37, 0x1c, 0xc7, 0x1d, 0xd8, 0x3f, 0xdb, 0x7d, 0xd0, 0x82, 0xfe, ++ 0x99, 0x83, 0x91, 0x7f, 0x26, 0xf5, 0xe7, 0x40, 0xfe, 0x19, 0xfa, 0x65, ++ 0xc8, 0x7f, 0xd2, 0x2f, 0xfb, 0x38, 0x4e, 0x0f, 0xc3, 0xfa, 0x3e, 0x15, ++ 0xeb, 0xfb, 0x34, 0xd1, 0xfa, 0x12, 0xe8, 0xdd, 0x1e, 0xd2, 0xbb, 0xdf, ++ 0x8c, 0x26, 0xf4, 0x6b, 0x5c, 0x96, 0xc4, 0x7a, 0x29, 0x37, 0x8b, 0xeb, ++ 0xbb, 0x46, 0x87, 0x85, 0x51, 0x1e, 0x6a, 0x80, 0xbc, 0xba, 0x2b, 0x4b, ++ 0xfa, 0x71, 0xdc, 0xaf, 0x18, 0x48, 0xcf, 0x5d, 0x2e, 0xde, 0x28, 0x5a, ++ 0x5b, 0x4a, 0xfa, 0xf6, 0x42, 0x97, 0x2f, 0x3d, 0x13, 0xae, 0xce, 0x0f, ++ 0x94, 0xa6, 0x44, 0xe3, 0xa8, 0xcb, 0x9f, 0x1d, 0x89, 0x74, 0x59, 0x6c, ++ 0xab, 0x4c, 0xca, 0x02, 0xf8, 0xec, 0x59, 0x46, 0xfc, 0x6c, 0x59, 0xdd, ++ 0xcf, 0x4e, 0xa5, 0x67, 0x71, 0x7c, 0xd1, 0xb5, 0x1f, 0xbe, 0xec, 0x80, ++ 0x2f, 0x93, 0x01, 0x5f, 0xce, 0xac, 0x2f, 0xf5, 0x03, 0xb9, 0xde, 0xcd, ++ 0xc1, 0xbc, 0x14, 0xcc, 0xd7, 0x23, 0xf0, 0x03, 0xfa, 0xf7, 0x22, 0xe9, ++ 0xdf, 0x5b, 0x7a, 0x6e, 0xc3, 0x58, 0xb1, 0xfe, 0x96, 0x2f, 0x44, 0x9c, ++ 0xcb, 0xfb, 0xbb, 0x85, 0x9e, 0x86, 0x38, 0xf8, 0x86, 0x8f, 0x7c, 0xd4, ++ 0xff, 0xcf, 0x48, 0xbf, 0x58, 0x3c, 0xdc, 0x5d, 0x81, 0x71, 0x50, 0xf3, ++ 0x0b, 0x57, 0xa4, 0xa3, 0x1f, 0x35, 0x71, 0xef, 0xed, 0x0e, 0xbc, 0x5e, ++ 0x70, 0x0e, 0x26, 0xbc, 0x9c, 0xdb, 0x9b, 0x14, 0xc0, 0x79, 0xce, 0x65, ++ 0x82, 0xfe, 0xb4, 0x63, 0x7b, 0xcc, 0x51, 0xcc, 0x13, 0x9c, 0x59, 0x71, ++ 0x2c, 0x53, 0x8f, 0xd7, 0x73, 0xcf, 0xbd, 0x55, 0x61, 0x86, 0x71, 0xce, ++ 0xed, 0x79, 0xab, 0x42, 0xc3, 0x7c, 0x83, 0xc8, 0xa7, 0xc8, 0xe7, 0xf5, ++ 0x97, 0xde, 0xa9, 0x08, 0xc2, 0xfb, 0xe1, 0x09, 0x6c, 0x68, 0x93, 0x5d, ++ 0x47, 0x5f, 0x2b, 0xd7, 0xef, 0x1b, 0x6c, 0x3c, 0x1f, 0xe1, 0x72, 0x5b, ++ 0x5a, 0xd9, 0x08, 0xf0, 0x6b, 0x5d, 0x19, 0xf4, 0xfe, 0xa3, 0x6e, 0xd3, ++ 0x0f, 0xf0, 0xbe, 0x6a, 0x7d, 0xa7, 0xe0, 0x43, 0x94, 0xe7, 0xb8, 0xfc, ++ 0xcb, 0x06, 0xb3, 0xaf, 0xd9, 0x0e, 0x7c, 0x0e, 0x31, 0x96, 0x1f, 0xf3, ++ 0xf8, 0x4b, 0x87, 0x05, 0xbc, 0x0b, 0x30, 0xff, 0x32, 0xc3, 0x43, 0x79, ++ 0x93, 0x66, 0x85, 0xeb, 0xbd, 0xf0, 0x02, 0x1e, 0x1f, 0x3a, 0x8b, 0xd8, ++ 0xd0, 0x42, 0x18, 0xcf, 0x6c, 0x52, 0x55, 0x7c, 0xaf, 0xd7, 0xcb, 0xfc, ++ 0xdb, 0xa1, 0x4b, 0xd2, 0xe1, 0xf6, 0x28, 0xaa, 0xa9, 0xe4, 0xae, 0x8e, ++ 0x00, 0x82, 0x3f, 0x2a, 0x39, 0x93, 0xf0, 0x7e, 0xdd, 0x59, 0x87, 0x82, ++ 0xfe, 0xbe, 0xcc, 0xd7, 0x68, 0x55, 0x7c, 0xbc, 0xde, 0x59, 0x96, 0xc8, ++ 0x76, 0x5d, 0x9e, 0xc6, 0x33, 0x47, 0x23, 0x3b, 0x96, 0xa2, 0x75, 0x30, ++ 0xd4, 0xab, 0xb3, 0x5c, 0xfc, 0x7d, 0x99, 0xaf, 0xa9, 0x9a, 0x39, 0x27, ++ 0x58, 0x89, 0x70, 0x3d, 0x60, 0xa2, 0x78, 0x03, 0x14, 0xa5, 0x82, 0xfa, ++ 0x2b, 0x57, 0xac, 0xa3, 0xd0, 0xbb, 0x67, 0xb5, 0xf4, 0x45, 0x34, 0x37, ++ 0xb2, 0x15, 0xc3, 0xe4, 0x0c, 0x5b, 0x0b, 0xfc, 0x3b, 0x18, 0xf0, 0x9c, ++ 0xe6, 0x33, 0x05, 0x30, 0x3f, 0x9a, 0x96, 0x17, 0x3d, 0x61, 0x06, 0x3f, ++ 0x2c, 0xb7, 0x85, 0xb1, 0x53, 0x3a, 0x7f, 0x2f, 0x05, 0x99, 0x0f, 0xd7, ++ 0xf3, 0xa6, 0x1a, 0xd9, 0x0e, 0xf2, 0x9f, 0xfa, 0xc5, 0x78, 0xeb, 0x1c, ++ 0xf0, 0x67, 0x52, 0x92, 0xb9, 0xfc, 0xa4, 0x05, 0x5b, 0x97, 0x60, 0xde, ++ 0x1a, 0xef, 0xff, 0x6b, 0x39, 0xd2, 0x85, 0xbf, 0x4f, 0xf4, 0x51, 0x31, ++ 0x8d, 0xc4, 0xc2, 0xe9, 0x00, 0x72, 0xea, 0x58, 0xe3, 0xb8, 0x92, 0x7e, ++ 0x9d, 0x2b, 0xac, 0xfe, 0xc1, 0xc0, 0xa8, 0x7b, 0x56, 0x38, 0xe8, 0xfa, ++ 0xf4, 0x0a, 0x0f, 0xc1, 0xf5, 0xf0, 0x0a, 0x1f, 0x5d, 0x7f, 0xb8, 0x62, ++ 0x28, 0xdd, 0x1f, 0x48, 0xce, 0x2e, 0x77, 0x7d, 0x68, 0x05, 0xcc, 0xab, ++ 0xe3, 0x27, 0xe7, 0x18, 0xc0, 0x0a, 0xac, 0xd7, 0xa9, 0x32, 0x92, 0xc7, ++ 0x87, 0x46, 0x57, 0xa4, 0xcf, 0x4d, 0xa0, 0x07, 0xe4, 0xf5, 0xb1, 0x15, ++ 0xc7, 0xdc, 0x13, 0x87, 0x08, 0x04, 0x02, 0x3d, 0x72, 0xea, 0x1c, 0xdb, ++ 0xd6, 0x14, 0x12, 0x9d, 0x51, 0x68, 0x60, 0x75, 0xaf, 0xad, 0x0e, 0x8c, ++ 0x63, 0xec, 0x01, 0x73, 0x60, 0x09, 0x03, 0xd6, 0x7a, 0x20, 0xeb, 0x8b, ++ 0x89, 0x98, 0x57, 0x5a, 0xab, 0x98, 0x28, 0x8f, 0xd4, 0x9a, 0x75, 0x70, ++ 0x75, 0x38, 0x0f, 0xaf, 0x3e, 0x4e, 0xb7, 0x43, 0xef, 0x32, 0xcc, 0x47, ++ 0x7a, 0x47, 0xb5, 0x2b, 0x28, 0xaf, 0xde, 0xba, 0x76, 0xe2, 0x83, 0x51, ++ 0x5d, 0x5d, 0x2c, 0x24, 0xee, 0x07, 0xa0, 0xed, 0x3d, 0xce, 0xef, 0x3f, ++ 0x60, 0xe3, 0x78, 0x5e, 0xc7, 0xd8, 0x14, 0x84, 0xd7, 0xae, 0xb0, 0x20, ++ 0x5e, 0x7b, 0x6c, 0xdc, 0x9e, 0x7c, 0x6c, 0xe3, 0x7a, 0xed, 0x53, 0x71, ++ 0x2d, 0xcc, 0x0a, 0x3d, 0x9c, 0x05, 0xf7, 0xff, 0xe2, 0x38, 0x51, 0xf2, ++ 0x00, 0x80, 0x67, 0x2b, 0xfd, 0x7d, 0x01, 0xee, 0x47, 0xa4, 0x1c, 0xfa, ++ 0x1b, 0xe5, 0x6b, 0xd5, 0xe1, 0x16, 0x2b, 0xca, 0x87, 0xf7, 0xc0, 0xfb, ++ 0xb4, 0x4f, 0xa1, 0x9a, 0xba, 0x2d, 0x0c, 0x4c, 0xe8, 0xf3, 0x8f, 0xbc, ++ 0x4b, 0xf9, 0x2f, 0xd5, 0x12, 0x2c, 0xe4, 0xed, 0x9f, 0xaf, 0xc1, 0x75, ++ 0xb8, 0xd2, 0x82, 0xdb, 0xd0, 0xc5, 0x62, 0xe1, 0x77, 0xa7, 0x1e, 0xf6, ++ 0x80, 0xdc, 0x20, 0x3f, 0x5c, 0x4b, 0xd8, 0x08, 0xa3, 0x1c, 0xaf, 0xb5, ++ 0x89, 0x76, 0xf8, 0xdf, 0x08, 0x0f, 0x6b, 0xcd, 0xbc, 0xfd, 0xfc, 0x23, ++ 0xbf, 0x5d, 0x1d, 0xa6, 0x76, 0x70, 0x31, 0xe2, 0x05, 0xdb, 0x2d, 0x88, ++ 0x97, 0x8c, 0x0e, 0x8f, 0x09, 0xda, 0xf6, 0x95, 0xef, 0xac, 0x3e, 0x76, ++ 0x3d, 0xb6, 0x65, 0xff, 0x77, 0xa8, 0xff, 0x73, 0x59, 0xdc, 0x3e, 0x32, ++ 0x7b, 0xd0, 0x8b, 0xfa, 0xa3, 0xaf, 0xed, 0x80, 0xf6, 0xd5, 0xba, 0xb6, ++ 0xc6, 0xdb, 0xcc, 0xca, 0xaf, 0x72, 0x7d, 0xf5, 0x87, 0xfe, 0x76, 0x34, ++ 0x17, 0xf8, 0xb5, 0xe1, 0x80, 0xd2, 0x81, 0xa0, 0x79, 0x0f, 0xac, 0x57, ++ 0x70, 0x9d, 0xde, 0x7d, 0xeb, 0x09, 0xdf, 0xf4, 0x07, 0xf2, 0x81, 0xcb, ++ 0xa0, 0x3c, 0xa6, 0x35, 0x4c, 0x79, 0xaf, 0xa7, 0x57, 0x1c, 0x73, 0xb4, ++ 0x00, 0x9d, 0xb5, 0xcc, 0x36, 0x37, 0xe2, 0xfd, 0x0a, 0x4f, 0x28, 0x10, ++ 0x48, 0xa0, 0xaf, 0x7f, 0xee, 0x92, 0xfe, 0x2a, 0xf4, 0xd7, 0xe7, 0xbf, ++ 0x22, 0xe6, 0xde, 0x6e, 0x9d, 0xff, 0xec, 0x65, 0x5c, 0x6e, 0x58, 0x0b, ++ 0xe8, 0x87, 0x04, 0xfe, 0x40, 0x91, 0xab, 0xf2, 0x3d, 0x27, 0xac, 0x63, ++ 0x83, 0x12, 0x5a, 0xa3, 0xa2, 0x9e, 0xf9, 0x99, 0xd9, 0x81, 0x7a, 0x84, ++ 0x75, 0x71, 0x3d, 0x74, 0x56, 0x8c, 0xc5, 0x22, 0x39, 0xe4, 0x8f, 0xd4, ++ 0xd9, 0x78, 0xd3, 0xbc, 0x2a, 0xb4, 0x66, 0x18, 0xea, 0x89, 0x3b, 0x34, ++ 0x3f, 0xc6, 0xb9, 0xb5, 0x85, 0xed, 0x95, 0x68, 0x8f, 0x6b, 0xf7, 0x17, ++ 0xfa, 0x57, 0xb2, 0x18, 0xbf, 0xd4, 0x66, 0x74, 0xb8, 0xcb, 0x91, 0x7f, ++ 0x32, 0x8c, 0xed, 0x66, 0x91, 0x17, 0xc9, 0xce, 0x68, 0xca, 0xc8, 0x28, ++ 0xc5, 0xfd, 0x82, 0xf5, 0x05, 0x98, 0xcf, 0x6f, 0x60, 0xed, 0x77, 0x7e, ++ 0x0f, 0xe1, 0xfd, 0xb5, 0xca, 0xd0, 0xaf, 0xfe, 0xf4, 0xe0, 0x35, 0xe9, ++ 0xd7, 0x41, 0xbb, 0x1e, 0xda, 0x68, 0xe7, 0xeb, 0x3b, 0xdf, 0xb2, 0x20, ++ 0x7f, 0x3e, 0xe8, 0xe4, 0xfa, 0xb3, 0xa1, 0x13, 0xf8, 0x07, 0xc6, 0x59, ++ 0x07, 0xf2, 0x15, 0x00, 0xc7, 0x63, 0x9b, 0xe6, 0x48, 0x46, 0xfd, 0xf4, ++ 0x74, 0xa0, 0xe9, 0x4a, 0x74, 0xc9, 0x7a, 0x1f, 0xf9, 0xcb, 0x54, 0x1b, ++ 0x38, 0x75, 0xcf, 0x14, 0x05, 0x1c, 0x44, 0x6f, 0xe7, 0xa5, 0xd5, 0x56, ++ 0x6c, 0x5b, 0x1c, 0xc3, 0x58, 0x19, 0xb6, 0x2d, 0x6b, 0x90, 0xdf, 0x6a, ++ 0xcb, 0x4c, 0x5c, 0x8e, 0x98, 0xe5, 0x57, 0x01, 0x4d, 0xec, 0x4f, 0x42, ++ 0xfb, 0xb7, 0x8f, 0x54, 0xdd, 0x14, 0xb6, 0xc7, 0xec, 0x8d, 0x57, 0xd8, ++ 0xa7, 0xc6, 0xad, 0xf6, 0xb0, 0x89, 0xdb, 0xa7, 0xf3, 0x68, 0xd7, 0x1a, ++ 0x36, 0x9b, 0xc2, 0xa8, 0xbf, 0x4c, 0xd6, 0x2e, 0x0b, 0xd2, 0xd7, 0x8e, ++ 0x7b, 0xaf, 0x44, 0x1f, 0x07, 0xe1, 0x6d, 0x99, 0xd4, 0xe7, 0x71, 0xfa, ++ 0x7a, 0xd9, 0xd4, 0xcc, 0x9b, 0xb0, 0xbd, 0xec, 0x81, 0x22, 0x47, 0xf8, ++ 0x4b, 0xf2, 0x8a, 0x35, 0x17, 0x53, 0x58, 0x44, 0xe7, 0xcf, 0x3c, 0xe8, ++ 0xe4, 0x72, 0x5c, 0xa3, 0x85, 0x69, 0x9f, 0xa3, 0xe6, 0x62, 0x1a, 0x3d, ++ 0xff, 0xe7, 0xcd, 0x67, 0x63, 0x91, 0x91, 0x5f, 0x36, 0x9f, 0x9d, 0x9e, ++ 0xcb, 0xf9, 0xea, 0x62, 0xf3, 0x11, 0x5d, 0x0f, 0x95, 0xff, 0x6a, 0xe3, ++ 0x60, 0xa0, 0xdb, 0xb2, 0xdd, 0x66, 0x53, 0x92, 0x8e, 0xef, 0x96, 0xed, ++ 0x16, 0xfb, 0xc9, 0xb6, 0x40, 0x36, 0x8e, 0xe3, 0xb2, 0x30, 0x81, 0x77, ++ 0xf0, 0xcf, 0x01, 0xbf, 0x5a, 0x61, 0x5f, 0x3b, 0xac, 0x81, 0x9c, 0x3f, ++ 0xd4, 0x27, 0xe7, 0xde, 0x35, 0x13, 0xc7, 0x21, 0xdd, 0x62, 0xcf, 0xd9, ++ 0x58, 0x83, 0x1e, 0x08, 0x60, 0x7c, 0xf8, 0x50, 0xb2, 0xd4, 0x03, 0x85, ++ 0x89, 0xfb, 0x27, 0xc7, 0xf5, 0x2f, 0x92, 0xed, 0x2b, 0xa9, 0x7f, 0x3c, ++ 0x3c, 0xae, 0xe4, 0x58, 0xdb, 0x0a, 0xfd, 0xb5, 0xbf, 0x27, 0xf5, 0xb5, ++ 0x11, 0xbe, 0xf5, 0xa6, 0xb8, 0xf1, 0x32, 0xe5, 0xfc, 0xe5, 0x6b, 0x26, ++ 0xe6, 0xc5, 0xf8, 0xea, 0xb7, 0x59, 0xd7, 0xfd, 0x2a, 0x3c, 0x18, 0x9e, ++ 0x67, 0xb4, 0x57, 0x62, 0x7d, 0x45, 0xef, 0x02, 0xe6, 0x43, 0xbb, 0x8c, ++ 0xfc, 0xea, 0xd7, 0xe9, 0xfd, 0xdf, 0x0a, 0xbf, 0xaf, 0xe6, 0x62, 0xb1, ++ 0x81, 0xde, 0x31, 0xbc, 0x97, 0x18, 0xee, 0x9f, 0x5e, 0xe1, 0x31, 0xec, ++ 0xcb, 0x2d, 0xaa, 0x5e, 0x46, 0xfb, 0x87, 0xbf, 0x15, 0x7a, 0xbe, 0x86, ++ 0x85, 0x29, 0x0e, 0xaa, 0xd9, 0x9a, 0xcb, 0x22, 0xba, 0xbc, 0xc4, 0xff, ++ 0x87, 0xe3, 0x1f, 0x85, 0xe3, 0xba, 0x01, 0xe0, 0xb8, 0xe1, 0x7f, 0x19, ++ 0x8e, 0x42, 0x83, 0x7c, 0xc6, 0xe0, 0x18, 0x6c, 0xb8, 0xff, 0x8f, 0xc2, ++ 0xb1, 0xfd, 0xb6, 0x92, 0x9b, 0x0a, 0xa1, 0xcb, 0xa3, 0x4a, 0xd8, 0x5a, ++ 0x84, 0x76, 0xe1, 0x7e, 0x13, 0xe5, 0x39, 0xd4, 0x8c, 0x89, 0xbe, 0x95, ++ 0xb8, 0x2f, 0x70, 0xbf, 0x46, 0x7e, 0x1e, 0xba, 0x24, 0x58, 0x9f, 0x51, ++ 0xa4, 0xb1, 0x63, 0x5a, 0x39, 0xca, 0x4f, 0x7b, 0x00, 0xe3, 0x72, 0xb6, ++ 0x8a, 0xe7, 0x7b, 0xe0, 0x7e, 0x9b, 0xb9, 0x9c, 0xec, 0x10, 0xf9, 0xc1, ++ 0xc5, 0x07, 0x92, 0xee, 0x46, 0x3f, 0xad, 0xa8, 0x26, 0xb0, 0x18, 0xaf, ++ 0x2c, 0xaf, 0x94, 0xf6, 0x1d, 0xe4, 0xbe, 0x1d, 0x13, 0x79, 0x2b, 0xb9, ++ 0xcf, 0x30, 0xc4, 0xc1, 0x2a, 0x35, 0x70, 0xde, 0x46, 0xb8, 0xee, 0x26, ++ 0x3b, 0x55, 0x14, 0xac, 0xae, 0x45, 0x67, 0x4e, 0x4d, 0x1d, 0x95, 0x8c, ++ 0xf6, 0xf1, 0x51, 0x53, 0x24, 0x8c, 0xf3, 0x85, 0x1f, 0xe6, 0xf3, 0xb9, ++ 0x4c, 0x91, 0x0e, 0x2b, 0xea, 0xde, 0xb4, 0xc1, 0x0e, 0xb4, 0x77, 0xae, ++ 0x34, 0xae, 0xff, 0xd8, 0x9a, 0x52, 0xb2, 0x7f, 0xdb, 0x4d, 0x45, 0x57, ++ 0x2e, 0x01, 0x38, 0x1e, 0x50, 0x2a, 0x93, 0x5f, 0x47, 0x3c, 0x67, 0x14, ++ 0x51, 0x9e, 0x16, 0xef, 0x2f, 0x85, 0xfb, 0xdb, 0x85, 0xdd, 0x52, 0x33, ++ 0xfc, 0x0e, 0xb4, 0x53, 0xdb, 0x85, 0xdd, 0x6a, 0x16, 0xfa, 0x5d, 0xde, ++ 0x4f, 0xc9, 0x0c, 0xde, 0x8d, 0xfe, 0xc4, 0x49, 0x67, 0xc3, 0x4d, 0xd6, ++ 0x6b, 0x50, 0x0f, 0x05, 0xda, 0xb2, 0xc0, 0xde, 0xfc, 0xc1, 0xd9, 0xb0, ++ 0xc6, 0x73, 0x0d, 0xda, 0x1b, 0x5f, 0x91, 0x15, 0xec, 0xcb, 0x1f, 0x36, ++ 0xd4, 0xaf, 0x41, 0x7b, 0xb3, 0x7d, 0xa5, 0x2f, 0xc7, 0x91, 0x11, 0x6b, ++ 0x0f, 0xf9, 0x3b, 0x58, 0x6b, 0xd2, 0x13, 0xf5, 0x6b, 0xd0, 0x5f, 0x69, ++ 0xb1, 0x2f, 0xbd, 0x07, 0xfd, 0x1d, 0x78, 0xfe, 0x2b, 0x2b, 0xac, 0xf3, ++ 0x99, 0x4c, 0xa1, 0x77, 0xc4, 0xf3, 0xa2, 0x3e, 0x3d, 0x05, 0x7a, 0x09, ++ 0xf4, 0x98, 0xba, 0xb2, 0xaf, 0x1d, 0x46, 0xbd, 0x54, 0xd4, 0xa7, 0x77, ++ 0xea, 0x49, 0xef, 0xec, 0x78, 0x5c, 0xa5, 0xf6, 0x41, 0x98, 0x0f, 0xfd, ++ 0x3e, 0x58, 0x47, 0x58, 0xc5, 0xf5, 0x0e, 0xd1, 0xc8, 0xaf, 0xb7, 0x01, ++ 0x2c, 0xc9, 0xd0, 0xb6, 0x0d, 0x2b, 0xa2, 0xfd, 0x1b, 0x58, 0x37, 0x4b, ++ 0x46, 0xff, 0x7a, 0x18, 0x7f, 0x2e, 0xf3, 0xee, 0x96, 0x21, 0x26, 0xca, ++ 0xbb, 0x63, 0x7f, 0xc4, 0xa3, 0xcd, 0xcb, 0xfb, 0x5b, 0x66, 0x30, 0x3f, ++ 0xee, 0x37, 0x59, 0x52, 0xed, 0x14, 0x87, 0xc8, 0x3c, 0xbe, 0x2a, 0xf6, ++ 0x8f, 0x92, 0x45, 0x1d, 0x85, 0xe2, 0x98, 0xc1, 0x2e, 0xc1, 0xfb, 0xd6, ++ 0x75, 0xe5, 0x4b, 0x31, 0x1e, 0xb3, 0x0e, 0x36, 0xee, 0x93, 0x5a, 0xe2, ++ 0xea, 0x2d, 0xd4, 0xf8, 0xfa, 0x0b, 0x7b, 0x94, 0xfc, 0xaf, 0xf7, 0x9c, ++ 0x22, 0xff, 0x9e, 0xc5, 0x3c, 0x97, 0x8a, 0x63, 0xf7, 0x19, 0xf3, 0x97, ++ 0xe3, 0xd5, 0x7d, 0x7b, 0x4b, 0x25, 0xc2, 0xbb, 0x34, 0x95, 0x39, 0x54, ++ 0xcc, 0x83, 0x84, 0xa2, 0xb4, 0x0f, 0x19, 0x6f, 0xd7, 0xac, 0x60, 0x47, ++ 0x7d, 0x3a, 0xf9, 0xb0, 0xda, 0x59, 0x20, 0xd1, 0x7e, 0xff, 0x8b, 0x2e, ++ 0xee, 0xd7, 0xda, 0x2f, 0x6a, 0x14, 0xdf, 0x6c, 0x50, 0xc0, 0xbf, 0x41, ++ 0x3b, 0x9a, 0xca, 0xf9, 0x4c, 0xfa, 0x47, 0x66, 0x87, 0xe4, 0x5b, 0xa3, ++ 0xdd, 0x95, 0xfe, 0x92, 0x39, 0x83, 0xaf, 0x65, 0xd9, 0xd4, 0x09, 0xd9, ++ 0x18, 0x7f, 0xab, 0xf6, 0x80, 0x15, 0xfd, 0x9c, 0x83, 0x8e, 0x72, 0x8a, ++ 0xeb, 0x55, 0xe6, 0xbf, 0xb9, 0x52, 0xe7, 0xef, 0xb4, 0x44, 0xa7, 0x52, ++ 0xbe, 0x4c, 0x73, 0x04, 0xc8, 0x0f, 0xcf, 0xc6, 0x38, 0x11, 0xf3, 0x3d, ++ 0x0e, 0x3f, 0xd3, 0xfb, 0x39, 0xad, 0x2b, 0x20, 0xb0, 0xbc, 0x82, 0xb1, ++ 0x27, 0x2b, 0x4a, 0x26, 0xa0, 0x3c, 0x3c, 0x66, 0x8b, 0x5a, 0x8b, 0x91, ++ 0xbe, 0x8f, 0x9a, 0x28, 0xde, 0x3b, 0x54, 0x7e, 0x4f, 0x58, 0xc1, 0x7c, ++ 0xd9, 0x72, 0x46, 0x72, 0xfa, 0x64, 0x85, 0x7b, 0x02, 0xe6, 0xbb, 0xb7, ++ 0x69, 0xc1, 0xf4, 0x3b, 0x50, 0x5e, 0x8e, 0xc3, 0x7c, 0x3e, 0x4e, 0x37, ++ 0xbe, 0xcf, 0xda, 0xac, 0x60, 0x7e, 0xf7, 0x73, 0x6b, 0x30, 0x1d, 0xf5, ++ 0xc1, 0x43, 0xc8, 0xf7, 0x3a, 0xbc, 0x3c, 0xe9, 0xe2, 0x7e, 0xfd, 0x05, ++ 0x27, 0xf7, 0x3b, 0x1f, 0x30, 0x73, 0xb9, 0x68, 0x05, 0x78, 0xa2, 0x00, ++ 0x87, 0x76, 0xf1, 0x2a, 0xca, 0x47, 0x3d, 0xe0, 0xe2, 0xfa, 0xc9, 0x52, ++ 0x3d, 0x91, 0xf2, 0x35, 0x16, 0xc0, 0x07, 0xe6, 0xe3, 0x92, 0x58, 0x53, ++ 0xd8, 0x41, 0xeb, 0xe5, 0xf9, 0xb5, 0x24, 0x8f, 0xc9, 0x50, 0xb7, 0xa7, ++ 0x5d, 0x1c, 0x4e, 0xef, 0x5f, 0x70, 0x9a, 0x0c, 0x71, 0x75, 0x1b, 0xac, ++ 0xd3, 0xa7, 0xd3, 0x5f, 0x36, 0x16, 0xa6, 0xfc, 0x1a, 0xe2, 0xf8, 0xa9, ++ 0x04, 0xfe, 0xcb, 0x41, 0x41, 0x37, 0x2b, 0xf8, 0x43, 0x3e, 0xf2, 0x4f, ++ 0xe2, 0xf6, 0xa1, 0xfb, 0xfb, 0x47, 0xe4, 0xaf, 0x48, 0xfa, 0xf4, 0xf9, ++ 0x29, 0x0a, 0xf8, 0x27, 0x5f, 0x12, 0x8f, 0x35, 0x42, 0xbc, 0xac, 0xd7, ++ 0xf7, 0x8d, 0x5a, 0x2f, 0xe9, 0xdf, 0x46, 0x88, 0x87, 0xf1, 0x7e, 0x8f, ++ 0xc3, 0x4a, 0xfe, 0xa1, 0xac, 0x4b, 0xb0, 0x0b, 0x7d, 0xd6, 0xea, 0x09, ++ 0xb5, 0x5f, 0x87, 0x7c, 0x9e, 0x9c, 0x36, 0x1c, 0xf3, 0x00, 0x1a, 0xeb, ++ 0x20, 0xa4, 0xac, 0xc3, 0xba, 0x04, 0xd4, 0x87, 0x1e, 0xad, 0xb7, 0x8f, ++ 0xff, 0x41, 0xe6, 0x9b, 0x6d, 0x69, 0xdb, 0xb1, 0x5f, 0x8b, 0xa8, 0x53, ++ 0x48, 0xf1, 0x1b, 0xe5, 0x27, 0x99, 0xb5, 0x47, 0x03, 0x28, 0x9f, 0x43, ++ 0x75, 0x72, 0xc3, 0x10, 0xdf, 0x61, 0x1a, 0x37, 0xc9, 0x67, 0xbc, 0xcf, ++ 0x58, 0x88, 0x61, 0x9c, 0xa1, 0x79, 0xe2, 0xeb, 0x18, 0xc2, 0x7d, 0xf5, ++ 0x4a, 0x54, 0x6f, 0xa7, 0xb1, 0x2d, 0xb8, 0xaf, 0x2c, 0xfd, 0xde, 0x5c, ++ 0x51, 0x2f, 0x74, 0x2e, 0xe5, 0x8f, 0x15, 0x28, 0xc7, 0xe0, 0xf7, 0x8e, ++ 0xce, 0xa2, 0xbc, 0x4d, 0x2f, 0xc5, 0x2d, 0x32, 0x5f, 0xf3, 0x75, 0xfd, ++ 0xe4, 0x6c, 0x1c, 0x03, 0xe3, 0xd1, 0xe5, 0x7f, 0xae, 0xf8, 0x10, 0xe5, ++ 0x6c, 0xc6, 0xe4, 0x42, 0xbc, 0x9f, 0xa2, 0x71, 0x3e, 0x01, 0x57, 0x5c, ++ 0x4b, 0x2a, 0xc7, 0xf0, 0x6a, 0xf2, 0xe2, 0x0c, 0x58, 0xff, 0x37, 0xb2, ++ 0x38, 0xff, 0x39, 0xd5, 0x76, 0xaa, 0xeb, 0x78, 0x5e, 0xd8, 0xb1, 0xbf, ++ 0x38, 0xe6, 0x78, 0x29, 0x8e, 0x02, 0x7c, 0x52, 0x3d, 0x4c, 0xb2, 0xbf, ++ 0x9b, 0xe2, 0x45, 0xe1, 0xa7, 0xa9, 0x7d, 0xfa, 0xf1, 0xdd, 0xd5, 0x01, ++ 0xa3, 0xdf, 0x19, 0xd6, 0xfb, 0x79, 0x2b, 0x1e, 0x7d, 0x77, 0x75, 0x4b, ++ 0x29, 0xc5, 0x2b, 0xd4, 0x7e, 0xfe, 0x91, 0x17, 0xd7, 0x60, 0x3c, 0xf8, ++ 0x80, 0x4d, 0xb6, 0x5f, 0xa0, 0x36, 0xd8, 0xb9, 0x28, 0xc6, 0x4b, 0x6c, ++ 0x6f, 0x92, 0x0f, 0xf9, 0x10, 0xde, 0x0f, 0xa0, 0xbc, 0xb1, 0xdb, 0x4a, ++ 0xc8, 0xcf, 0x56, 0x8b, 0x58, 0x0e, 0xe2, 0x63, 0x62, 0x9a, 0x95, 0xf4, ++ 0xa6, 0xba, 0x37, 0x69, 0x3b, 0xfa, 0xc1, 0x10, 0x17, 0x3f, 0x97, 0xa5, ++ 0xcb, 0x73, 0x9e, 0x4b, 0x3d, 0x51, 0x80, 0xfe, 0x70, 0x82, 0xf1, 0xc2, ++ 0x86, 0xf1, 0x0a, 0xbe, 0xde, 0x78, 0x30, 0x7f, 0x27, 0xd6, 0xcb, 0xc8, ++ 0xe7, 0x13, 0xd3, 0x36, 0x47, 0x55, 0xfe, 0x9e, 0x0f, 0xdf, 0x63, 0x79, ++ 0x5d, 0x7f, 0x0c, 0xc3, 0xf8, 0x8f, 0xbe, 0x90, 0xc4, 0xd6, 0x00, 0x0a, ++ 0x1f, 0x33, 0x1b, 0xe5, 0x5d, 0x5e, 0x37, 0x8a, 0x38, 0x13, 0xf5, 0x8d, ++ 0xbe, 0x5e, 0xd1, 0x52, 0x3d, 0x3f, 0x80, 0x4c, 0x2d, 0xe5, 0x3a, 0xc9, ++ 0x93, 0xcc, 0xa2, 0x3a, 0x7e, 0x92, 0x72, 0xae, 0x5d, 0x1c, 0xc6, 0xa2, ++ 0x3a, 0x39, 0xc9, 0x76, 0x15, 0x12, 0xbd, 0x34, 0x2d, 0x40, 0x79, 0x24, ++ 0xed, 0x62, 0x29, 0x3d, 0xbf, 0xe0, 0xe4, 0x7c, 0xd0, 0xba, 0xc2, 0x71, ++ 0x99, 0x79, 0x32, 0x07, 0x98, 0x67, 0x24, 0xe9, 0x8f, 0x81, 0xe7, 0xa9, ++ 0x10, 0xfa, 0x85, 0x89, 0x7c, 0xa3, 0x46, 0x75, 0x2f, 0x52, 0x2f, 0x0c, ++ 0x24, 0xe7, 0xf1, 0xfb, 0x5a, 0xf1, 0x7a, 0x51, 0x5e, 0xa5, 0x5e, 0x4c, ++ 0xc1, 0xb1, 0xe1, 0xfa, 0x82, 0xcb, 0x98, 0x47, 0xbf, 0x67, 0x73, 0xc7, ++ 0x51, 0x64, 0xa1, 0xcf, 0xec, 0xa1, 0x7d, 0xae, 0xd1, 0x58, 0xbf, 0x74, ++ 0x32, 0x0d, 0x4d, 0x78, 0x9d, 0x29, 0x3a, 0x1c, 0xf9, 0xf8, 0xa3, 0xfe, ++ 0xf7, 0x1b, 0x70, 0x71, 0x51, 0xcc, 0x33, 0xc0, 0xfd, 0x92, 0x9d, 0x4b, ++ 0x5e, 0x45, 0x76, 0x3d, 0xec, 0x0a, 0x7d, 0x8a, 0x7e, 0xd0, 0x2b, 0x2e, ++ 0x91, 0x9f, 0xf5, 0x80, 0x3d, 0x54, 0xd1, 0xde, 0x81, 0xbd, 0x28, 0xe5, ++ 0xf9, 0x6b, 0x27, 0xe6, 0x63, 0x43, 0xbe, 0x4d, 0x93, 0x18, 0xca, 0xd3, ++ 0x6d, 0x94, 0x8f, 0x55, 0xdd, 0x41, 0x9f, 0x0b, 0xf1, 0x3b, 0xb3, 0x82, ++ 0x72, 0x0e, 0x12, 0xee, 0xb5, 0x2b, 0x78, 0x1d, 0x99, 0xd4, 0xb3, 0x76, ++ 0x2d, 0x44, 0xf8, 0xb2, 0x6a, 0x61, 0x7e, 0x75, 0x84, 0xc0, 0x86, 0x33, ++ 0xf6, 0xb1, 0xeb, 0xd2, 0x4d, 0x18, 0x9b, 0x69, 0x1a, 0x97, 0xa3, 0x5f, ++ 0x3f, 0x7a, 0x96, 0xfc, 0x0a, 0x9b, 0x16, 0x20, 0xbe, 0xb2, 0x39, 0x4c, ++ 0x3e, 0xf4, 0x0b, 0x6c, 0x10, 0x17, 0xa2, 0xde, 0x5d, 0xe9, 0x30, 0xf1, ++ 0xfd, 0x16, 0x8f, 0x95, 0xf2, 0xf5, 0xad, 0x0a, 0x44, 0x88, 0xa0, 0x37, ++ 0x96, 0x66, 0x14, 0x7d, 0xe9, 0x3e, 0xb6, 0xe5, 0xa2, 0x9b, 0xec, 0x2d, ++ 0x40, 0xe2, 0xd1, 0xeb, 0xed, 0x7f, 0xfe, 0x3c, 0x4e, 0x61, 0x1f, 0x8c, ++ 0xf3, 0x68, 0x0e, 0xee, 0x37, 0xb0, 0x43, 0xdc, 0x0e, 0x23, 0x12, 0x3e, ++ 0xd0, 0xe9, 0x63, 0xe9, 0x0f, 0xc4, 0xbf, 0x17, 0x3f, 0xbe, 0xc4, 0xa7, ++ 0xc4, 0xaf, 0x15, 0xf1, 0x5a, 0x4a, 0xf6, 0x30, 0xa1, 0xbf, 0xf1, 0x77, ++ 0x61, 0x37, 0xa5, 0xfe, 0xcc, 0x96, 0xfa, 0xd6, 0x75, 0xa2, 0x24, 0x0a, ++ 0x77, 0xeb, 0x95, 0xee, 0x34, 0xf4, 0x6b, 0x40, 0x8f, 0xfe, 0x1d, 0xf9, ++ 0xa4, 0xe1, 0xea, 0xde, 0x34, 0x93, 0x8f, 0xf4, 0xaf, 0x9b, 0xfb, 0x41, ++ 0x61, 0xf1, 0x3e, 0xb3, 0xeb, 0xf9, 0x5a, 0xe6, 0xa9, 0xe5, 0xba, 0x24, ++ 0xfc, 0x4b, 0x5f, 0x5f, 0x60, 0xd5, 0xef, 0x97, 0xc4, 0xc3, 0x1b, 0x6f, ++ 0x67, 0xed, 0xa5, 0xc6, 0xfa, 0x02, 0x9b, 0xcf, 0x58, 0x5f, 0x20, 0xeb, ++ 0xf6, 0x55, 0x2d, 0x48, 0x7c, 0x63, 0x1e, 0x17, 0xb0, 0xa2, 0x9c, 0xac, ++ 0x74, 0x94, 0x3b, 0xd0, 0xcf, 0x69, 0xd1, 0x7c, 0xbf, 0x0b, 0x50, 0x5d, ++ 0x84, 0x99, 0xfc, 0x6d, 0xf0, 0xdf, 0x0d, 0xf3, 0xcb, 0xeb, 0x43, 0x20, ++ 0xff, 0x08, 0xc7, 0x10, 0xb7, 0xc9, 0x50, 0xf7, 0x22, 0xaf, 0xa9, 0xb8, ++ 0x0f, 0x92, 0xe0, 0xbd, 0x49, 0x6e, 0x8e, 0xbf, 0x87, 0x0e, 0xde, 0x4e, ++ 0x7a, 0x58, 0xf3, 0xf3, 0x7d, 0xa1, 0x78, 0xfa, 0x31, 0xd6, 0x4e, 0xfc, ++ 0x92, 0x5a, 0xc2, 0x1c, 0x94, 0x3f, 0x15, 0xf0, 0xa6, 0x5d, 0x66, 0xdc, ++ 0x81, 0xf8, 0xe8, 0x07, 0x07, 0x6d, 0xe4, 0x27, 0x6b, 0x63, 0xad, 0x11, ++ 0xac, 0xbb, 0x8c, 0x9f, 0x4f, 0x35, 0x07, 0x03, 0x0a, 0xea, 0xdd, 0x32, ++ 0x46, 0x7e, 0xb2, 0x9a, 0xcf, 0xe7, 0x57, 0x87, 0x30, 0xaa, 0xd3, 0x4e, ++ 0x1b, 0x95, 0xc9, 0x86, 0xea, 0xf0, 0xd8, 0xea, 0x99, 0x49, 0xcf, 0x97, ++ 0xba, 0x1c, 0x0c, 0xe9, 0xad, 0xa6, 0x9a, 0x82, 0x89, 0xf8, 0x45, 0xe2, ++ 0xc9, 0xe3, 0x36, 0x19, 0xf6, 0xad, 0x3d, 0x92, 0x6f, 0xbc, 0xbf, 0xa7, ++ 0xfd, 0x15, 0x1d, 0xdf, 0x4c, 0x74, 0xbb, 0xfa, 0xf3, 0x8d, 0xc7, 0xcd, ++ 0xf5, 0x21, 0xc2, 0xa1, 0xa7, 0x6f, 0xab, 0xa7, 0x28, 0x3b, 0x11, 0x7d, ++ 0x62, 0x7a, 0x91, 0xf3, 0xd5, 0xe5, 0xf8, 0xa2, 0x62, 0x1c, 0xf0, 0x3b, ++ 0xda, 0x79, 0xb8, 0x6e, 0x83, 0x75, 0x74, 0x6a, 0x6c, 0xca, 0xee, 0x52, ++ 0x84, 0x8b, 0x51, 0x5d, 0x7b, 0xdd, 0x6c, 0x3b, 0x73, 0x80, 0x5d, 0xbb, ++ 0xc3, 0x53, 0x79, 0x9b, 0x1b, 0xc6, 0xab, 0xe8, 0x7a, 0x95, 0xd7, 0x8b, ++ 0x77, 0xba, 0x28, 0x68, 0xac, 0x13, 0xef, 0xc7, 0xcf, 0xff, 0xb6, 0x9b, ++ 0xeb, 0xdb, 0xb7, 0xdd, 0x5c, 0x3f, 0xa6, 0x9f, 0x08, 0x3c, 0x3b, 0x1e, ++ 0xf0, 0xdc, 0xd9, 0x95, 0xec, 0x53, 0xe0, 0x51, 0x67, 0x66, 0x62, 0x3d, ++ 0xfd, 0x03, 0xb7, 0x62, 0xac, 0x37, 0xd0, 0xba, 0x87, 0xa3, 0xff, 0x22, ++ 0xfb, 0x57, 0x54, 0x1b, 0xe7, 0x0b, 0x0b, 0xfa, 0xdf, 0x2f, 0xdf, 0x0b, ++ 0xdf, 0x9c, 0x89, 0xfe, 0xdc, 0x74, 0xc6, 0x65, 0xa3, 0xd8, 0xaf, 0xf0, ++ 0xfa, 0x86, 0x7d, 0x29, 0x91, 0x21, 0x68, 0x57, 0x59, 0x54, 0xbb, 0x05, ++ 0xf0, 0xba, 0x53, 0xc4, 0x8d, 0x3b, 0x21, 0x9e, 0x9c, 0x01, 0xe3, 0xba, ++ 0x93, 0x59, 0x08, 0xd7, 0xed, 0xca, 0x82, 0x76, 0x29, 0xbd, 0x1f, 0xd8, ++ 0x6d, 0x8f, 0x8d, 0xf7, 0x6b, 0x8e, 0x32, 0x36, 0xa9, 0x38, 0xb8, 0x03, ++ 0xc7, 0x9b, 0x94, 0xed, 0x2d, 0x6b, 0x2e, 0xe4, 0xef, 0xe3, 0x38, 0x47, ++ 0x92, 0x59, 0x8b, 0xb5, 0x3c, 0x86, 0xf7, 0x9b, 0x93, 0x80, 0xe5, 0x32, ++ 0xf1, 0x79, 0x38, 0x67, 0x49, 0x69, 0xec, 0xfe, 0x11, 0x50, 0xee, 0xd8, ++ 0xcf, 0xed, 0xee, 0x1e, 0xae, 0x80, 0xfc, 0xcf, 0x37, 0x05, 0xdc, 0x68, ++ 0x47, 0x3e, 0x7c, 0xeb, 0x7b, 0x54, 0x27, 0xba, 0x88, 0x05, 0x9e, 0xfc, ++ 0x10, 0xe8, 0x73, 0x35, 0xdc, 0xc4, 0xf8, 0xaa, 0xe2, 0x44, 0xd0, 0x82, ++ 0x7a, 0xe1, 0x53, 0x7c, 0x08, 0xf8, 0x7e, 0xdc, 0x1e, 0x5c, 0x8d, 0x7c, ++ 0xb2, 0xa0, 0x7d, 0xea, 0x93, 0xfa, 0x3a, 0x17, 0xb6, 0x83, 0x7f, 0x87, ++ 0x22, 0xf1, 0xd5, 0x9f, 0x1f, 0xb8, 0xfe, 0x01, 0x38, 0xc3, 0xd6, 0x4c, ++ 0x03, 0x9c, 0x6c, 0x2c, 0xc2, 0x6d, 0xe5, 0xef, 0xc5, 0xe3, 0x57, 0x5e, ++ 0xef, 0x12, 0x7c, 0x2c, 0xe9, 0x09, 0xe8, 0xb9, 0x2a, 0x55, 0xd0, 0x73, ++ 0x0d, 0xa0, 0x7e, 0x6e, 0x0a, 0xf7, 0x97, 0x3b, 0x2d, 0x9c, 0x4e, 0x7d, ++ 0xfc, 0xe3, 0xb2, 0xb4, 0xe2, 0x3e, 0xca, 0x59, 0x2b, 0x7f, 0xce, 0x02, ++ 0x43, 0xb9, 0x7f, 0x6f, 0xe5, 0xf4, 0x99, 0x9b, 0x52, 0x10, 0x41, 0xbf, ++ 0xba, 0x53, 0x0b, 0xa4, 0xa0, 0x7f, 0x3f, 0xb7, 0x6f, 0xbf, 0x3e, 0x40, ++ 0xdf, 0xf5, 0xd4, 0xd9, 0x02, 0xe9, 0xd7, 0x20, 0xfd, 0xde, 0xe2, 0xf1, ++ 0xd7, 0xe9, 0x4a, 0x7b, 0x9b, 0x02, 0xe3, 0x9c, 0x36, 0x07, 0xd2, 0x51, ++ 0x6e, 0x4f, 0xbf, 0xa5, 0x2a, 0x2b, 0xa9, 0xfe, 0x81, 0xd7, 0x47, 0xca, ++ 0xba, 0xb3, 0xd3, 0x66, 0xdf, 0xda, 0x2b, 0xe1, 0xf9, 0xbc, 0x1f, 0xa9, ++ 0x81, 0x95, 0xf4, 0xd8, 0x18, 0x57, 0x9c, 0x65, 0x81, 0x91, 0x6f, 0x62, ++ 0x9c, 0xb5, 0x4f, 0xa5, 0x7d, 0xbb, 0xc2, 0x87, 0xef, 0x56, 0xaf, 0x86, ++ 0xfe, 0xf3, 0x21, 0xe0, 0x40, 0xbd, 0x34, 0xb7, 0xca, 0x1e, 0x46, 0x7f, ++ 0xae, 0xf3, 0xf7, 0x4d, 0x7f, 0x44, 0xbb, 0x36, 0xef, 0xf1, 0x24, 0xdf, ++ 0x2a, 0x98, 0xe7, 0xf0, 0xe6, 0x91, 0x7f, 0xc5, 0xf6, 0xc7, 0xeb, 0x52, ++ 0x7d, 0x49, 0x94, 0xaf, 0x2d, 0x52, 0xbc, 0x98, 0x47, 0x5d, 0x5f, 0xe8, ++ 0xa0, 0xfd, 0xb7, 0xe5, 0x4c, 0xf8, 0xad, 0xf7, 0x4e, 0xab, 0x1a, 0xcc, ++ 0xd8, 0x4f, 0xf1, 0x5f, 0xb9, 0x0f, 0x02, 0x6b, 0xfe, 0x98, 0xc9, 0xe7, ++ 0x4f, 0xac, 0x9d, 0x08, 0xeb, 0xbc, 0xd2, 0xd5, 0x69, 0xb2, 0x03, 0x4c, ++ 0x37, 0x64, 0x3f, 0xb1, 0xd6, 0x0a, 0xf4, 0x7e, 0x60, 0x65, 0xd0, 0x83, ++ 0x79, 0x88, 0x73, 0x1b, 0xbf, 0xb5, 0x16, 0xf3, 0x10, 0x6e, 0x77, 0xa0, ++ 0x6b, 0xbc, 0x1f, 0xe0, 0xdb, 0xf4, 0x9d, 0x69, 0xd8, 0xee, 0x7c, 0x4c, ++ 0x8c, 0x17, 0x5e, 0xbe, 0x16, 0xf3, 0x0e, 0x2f, 0x99, 0x42, 0x85, 0x0a, ++ 0x3c, 0x9f, 0xb2, 0x69, 0xfd, 0x34, 0xaa, 0x53, 0x2e, 0x96, 0xe3, 0x3f, ++ 0xb5, 0x36, 0x00, 0xf6, 0x7f, 0xee, 0x13, 0x57, 0xfc, 0xf5, 0x04, 0x8c, ++ 0xdf, 0x90, 0xfd, 0x8b, 0x69, 0xe8, 0x1f, 0x00, 0x7d, 0x05, 0x3c, 0x07, ++ 0x08, 0xbe, 0x05, 0xe3, 0x64, 0xfb, 0x60, 0x4a, 0x15, 0xf8, 0x0e, 0xce, ++ 0x14, 0x66, 0xc8, 0xc7, 0x9a, 0x63, 0x79, 0x0d, 0xca, 0xf7, 0x76, 0x4a, ++ 0x3f, 0x9d, 0x1d, 0x99, 0x86, 0xf9, 0xd8, 0x79, 0x13, 0x9a, 0xaa, 0x34, ++ 0x18, 0x7f, 0x53, 0xf6, 0x1b, 0x6b, 0x4b, 0x87, 0x31, 0x36, 0xa6, 0xbd, ++ 0xd2, 0x11, 0x80, 0xf6, 0xd6, 0xec, 0x37, 0xa7, 0xa5, 0x00, 0x9f, 0x74, ++ 0xb2, 0x40, 0x2d, 0xe6, 0x4d, 0x22, 0xd9, 0xbf, 0x99, 0x66, 0xbd, 0x1e, ++ 0xc6, 0xcf, 0x32, 0x8e, 0xef, 0x54, 0x45, 0x5e, 0x3f, 0xfc, 0xce, 0x5a, ++ 0x1c, 0xaf, 0xa2, 0x3a, 0x50, 0x86, 0xfe, 0x4c, 0xa9, 0xe7, 0xc3, 0xb5, ++ 0x56, 0x78, 0xdf, 0x85, 0x75, 0xac, 0x30, 0xdf, 0x6d, 0x9b, 0x87, 0xad, ++ 0x43, 0xbf, 0x5e, 0xea, 0xd1, 0x7f, 0x11, 0x7a, 0x14, 0xf4, 0xe6, 0x19, ++ 0x94, 0x87, 0x7a, 0x6b, 0xf7, 0x51, 0x4c, 0xf5, 0x16, 0x2c, 0xef, 0xb5, ++ 0xf0, 0xfa, 0x66, 0xa1, 0x3f, 0xf2, 0x38, 0x5f, 0xf7, 0xb5, 0x87, 0x76, ++ 0xf3, 0x7a, 0x74, 0xd9, 0xf6, 0xf0, 0x76, 0xe7, 0xaa, 0xc4, 0xfa, 0xe8, ++ 0x2f, 0x1e, 0xce, 0xf7, 0x9d, 0xc9, 0x89, 0x9f, 0xe7, 0x66, 0x73, 0xfd, ++ 0x23, 0xe5, 0x26, 0xfd, 0x04, 0x0b, 0xec, 0x4a, 0x20, 0x3f, 0xa6, 0x6c, ++ 0xfb, 0xff, 0x48, 0xfe, 0xbc, 0xd9, 0xff, 0x8f, 0xf4, 0x5b, 0xc6, 0x65, ++ 0xf4, 0x5b, 0x86, 0xd4, 0x6f, 0x02, 0x9f, 0xa5, 0x46, 0x7d, 0x0d, 0xd3, ++ 0x08, 0xbd, 0x7f, 0x65, 0x11, 0xea, 0x89, 0x63, 0x6e, 0x9f, 0xc1, 0x5e, ++ 0x57, 0x74, 0xcd, 0x24, 0x7b, 0xf2, 0xae, 0x47, 0xe8, 0x15, 0x1f, 0x7f, ++ 0xdf, 0x55, 0xc5, 0xeb, 0x81, 0x7a, 0xf7, 0xa7, 0x50, 0xbe, 0x8b, 0x59, ++ 0xbb, 0x4a, 0x90, 0x4e, 0xf2, 0xbd, 0xd1, 0x02, 0xef, 0x55, 0x0f, 0x4e, ++ 0xdf, 0x84, 0xfd, 0xea, 0xba, 0xcc, 0x8c, 0xbe, 0xf3, 0xd8, 0x5d, 0xf9, ++ 0xa5, 0x7e, 0x65, 0x1d, 0xe6, 0x87, 0x75, 0x71, 0x48, 0x9d, 0x16, 0xa5, ++ 0xbc, 0x40, 0x1d, 0xe6, 0x87, 0x47, 0xe2, 0x78, 0xbf, 0xb6, 0xa0, 0x3f, ++ 0x84, 0xe3, 0xe0, 0x77, 0x1c, 0xb8, 0x0f, 0x82, 0xf9, 0x5d, 0x57, 0x73, ++ 0x62, 0xfa, 0x4b, 0xbf, 0xaa, 0xee, 0x62, 0x06, 0x0b, 0x8f, 0xec, 0x6f, ++ 0x7f, 0x63, 0xe3, 0x3b, 0xe9, 0xf9, 0xe5, 0xd6, 0x15, 0x1b, 0xcf, 0x98, ++ 0xbf, 0xe8, 0x3f, 0x9e, 0x45, 0xec, 0x27, 0xc5, 0xd9, 0x49, 0x4b, 0x62, ++ 0x38, 0xab, 0x25, 0x9f, 0x02, 0xbe, 0x4d, 0x3a, 0xfe, 0x5a, 0x20, 0xf8, ++ 0x0d, 0xb4, 0x27, 0xf9, 0x93, 0x3d, 0x7b, 0x87, 0x6d, 0x5f, 0x53, 0xa8, ++ 0x9f, 0x97, 0x7f, 0x5f, 0x05, 0xfa, 0xf9, 0xd9, 0xf1, 0xa8, 0x2f, 0x41, ++ 0xdf, 0xa3, 0xbf, 0x59, 0xa1, 0x05, 0xa6, 0x61, 0xff, 0x8a, 0xae, 0x4c, ++ 0xda, 0xa7, 0x92, 0xfc, 0x21, 0xf9, 0x42, 0xd2, 0xb5, 0x33, 0xb3, 0x89, ++ 0xf2, 0x7e, 0xbd, 0x5b, 0x14, 0xf2, 0xa7, 0xe2, 0xe1, 0x9a, 0x27, 0xe1, ++ 0xda, 0xac, 0x70, 0x3f, 0xa4, 0x3a, 0xa4, 0xde, 0xad, 0x83, 0x4f, 0xca, ++ 0x03, 0x8c, 0xdf, 0x29, 0xc6, 0x1f, 0x35, 0x96, 0xe4, 0xe7, 0xc7, 0xdc, ++ 0x9f, 0x06, 0xb9, 0xb9, 0x03, 0xe5, 0x17, 0xf7, 0xbd, 0x71, 0x1d, 0xfe, ++ 0xee, 0xe1, 0x33, 0xaf, 0xee, 0x0f, 0xff, 0xaf, 0x85, 0x1f, 0x05, 0x74, ++ 0xe4, 0xf8, 0x7f, 0xc1, 0x46, 0x75, 0x0a, 0xf1, 0xf6, 0x32, 0x86, 0xff, ++ 0xdc, 0xcb, 0xd0, 0xb3, 0x80, 0x9e, 0x4b, 0x7f, 0xa8, 0x6e, 0x40, 0xbb, ++ 0x99, 0x46, 0xef, 0x65, 0x9f, 0x88, 0xa6, 0xf9, 0xa0, 0x5f, 0x97, 0xe0, ++ 0xff, 0xce, 0x8e, 0x0f, 0xd2, 0xae, 0x43, 0xb9, 0xd8, 0xa7, 0x32, 0xc5, ++ 0xc7, 0xd7, 0x8d, 0x7a, 0xab, 0x42, 0xea, 0xe3, 0xf0, 0x88, 0x37, 0x26, ++ 0x68, 0xe4, 0x97, 0xc5, 0xec, 0x87, 0x8f, 0xfc, 0x33, 0xa9, 0x3f, 0xa3, ++ 0x56, 0x6b, 0xac, 0x7f, 0x70, 0xe3, 0x88, 0x69, 0x2d, 0xa8, 0xbf, 0x93, ++ 0xb8, 0xbc, 0x3a, 0x55, 0xb0, 0x36, 0xe5, 0x31, 0x38, 0x1e, 0xce, 0xe6, ++ 0x7a, 0x6c, 0x6c, 0x28, 0x71, 0x7c, 0xf3, 0x03, 0x77, 0x2a, 0x3d, 0x97, ++ 0xf8, 0xde, 0xb2, 0xbc, 0x8a, 0x7d, 0x00, 0xeb, 0x3b, 0x21, 0xec, 0xfd, ++ 0xd8, 0xee, 0xb0, 0x82, 0x74, 0x59, 0x20, 0xf0, 0xd8, 0xe7, 0xcf, 0x08, ++ 0x7d, 0x76, 0x73, 0x52, 0xf7, 0x73, 0xe2, 0xfb, 0x10, 0x03, 0x3f, 0xca, ++ 0x36, 0xf8, 0x3b, 0x0d, 0xa6, 0x62, 0xdd, 0x73, 0x3b, 0xd7, 0xbb, 0x72, ++ 0x3e, 0x80, 0xb7, 0x85, 0x61, 0xc9, 0x0a, 0x5c, 0x15, 0xb8, 0xde, 0xe6, ++ 0x29, 0x14, 0xe3, 0x70, 0xbe, 0x3c, 0xb5, 0x37, 0x7b, 0x1b, 0xea, 0x0f, ++ 0x67, 0x71, 0xa0, 0x0c, 0xf5, 0x8d, 0xe4, 0x2f, 0xb0, 0x27, 0x62, 0xbd, ++ 0xa6, 0xbb, 0x66, 0xda, 0x39, 0xff, 0xcf, 0x4c, 0x40, 0x87, 0xe7, 0x85, ++ 0xfe, 0x5c, 0xb0, 0x99, 0xaf, 0xbf, 0xf3, 0x3f, 0xaa, 0xa6, 0x21, 0x1f, ++ 0x74, 0xbe, 0x9d, 0x99, 0xb1, 0x4a, 0xc7, 0xef, 0xa7, 0x84, 0x1f, 0x29, ++ 0xc7, 0x95, 0xf2, 0x24, 0xdf, 0x93, 0xcf, 0xf7, 0x8b, 0xf1, 0x5e, 0xc9, ++ 0x4e, 0x23, 0x7c, 0x9c, 0x12, 0xf8, 0x43, 0x38, 0x12, 0xd5, 0x8b, 0xc9, ++ 0xf7, 0x70, 0xbd, 0xa4, 0xaf, 0xdb, 0xb8, 0xbe, 0x86, 0x75, 0x87, 0x91, ++ 0x4e, 0xb0, 0xee, 0xb0, 0x52, 0x8e, 0xeb, 0x56, 0x0c, 0x76, 0xa2, 0xcf, ++ 0x3e, 0x08, 0x7c, 0xd7, 0x5b, 0x00, 0xcf, 0x80, 0xc7, 0x9d, 0xe6, 0x70, ++ 0x0e, 0xd6, 0x31, 0xb9, 0x70, 0x3e, 0xfb, 0xe5, 0xe5, 0x17, 0xd6, 0x43, ++ 0xcf, 0x7b, 0xf7, 0xa7, 0x92, 0xde, 0x89, 0x1f, 0xff, 0x5c, 0x36, 0x8f, ++ 0xe7, 0xb6, 0x99, 0x78, 0x9d, 0xd5, 0x11, 0x13, 0xc8, 0x33, 0xca, 0x99, ++ 0x9d, 0xc3, 0xdb, 0xb3, 0xd7, 0x4b, 0xe3, 0x76, 0x0b, 0x3e, 0xba, 0xbc, ++ 0x3e, 0xfc, 0x6a, 0xf2, 0xb3, 0xcd, 0xc2, 0xeb, 0x62, 0x01, 0x7e, 0xaa, ++ 0x4f, 0xac, 0x7f, 0x31, 0x77, 0x9b, 0x11, 0xfe, 0x95, 0x02, 0xfe, 0x50, ++ 0x33, 0x7e, 0x87, 0xe7, 0xdc, 0xc4, 0xfc, 0xcd, 0x8c, 0xf0, 0x16, 0x45, ++ 0x7c, 0xdd, 0xeb, 0xf1, 0x71, 0xfd, 0x64, 0x09, 0x91, 0xff, 0xd6, 0xbb, ++ 0x85, 0x51, 0xfc, 0x3a, 0x04, 0xfc, 0x08, 0x1f, 0xb4, 0x1b, 0x83, 0xf6, ++ 0x72, 0xa5, 0x30, 0x26, 0xa7, 0x25, 0x1d, 0x0a, 0xd1, 0xb1, 0x62, 0x03, ++ 0xd8, 0x69, 0xc4, 0x9b, 0x55, 0xe2, 0xed, 0xf5, 0x5d, 0xfa, 0x79, 0x3f, ++ 0xcf, 0x4e, 0x35, 0x7c, 0x4f, 0x58, 0x27, 0xe8, 0x3f, 0x04, 0xec, 0xfb, ++ 0xb3, 0x00, 0xef, 0x10, 0x18, 0xe7, 0x39, 0x82, 0x9b, 0xc3, 0x75, 0x6a, ++ 0x63, 0xc7, 0x75, 0x98, 0xa7, 0xeb, 0xb3, 0xf7, 0x9e, 0x34, 0xc1, 0x0f, ++ 0xf1, 0x70, 0x46, 0x2d, 0xb9, 0x1c, 0x4e, 0xaa, 0xcb, 0x40, 0x7f, 0xc7, ++ 0x37, 0x2a, 0x06, 0x27, 0x8e, 0x8f, 0xf3, 0x30, 0x7b, 0x70, 0x15, 0x8e, ++ 0xdb, 0xf0, 0xce, 0x9e, 0x5c, 0xfd, 0xb8, 0xe9, 0x1e, 0xce, 0x6f, 0x4e, ++ 0x75, 0xee, 0x04, 0x1b, 0xea, 0xb1, 0xf5, 0xa0, 0x57, 0x49, 0x1d, 0x84, ++ 0x0e, 0xe1, 0x77, 0x16, 0xf3, 0x0f, 0x64, 0x38, 0xd6, 0x30, 0x8a, 0x1b, ++ 0x4c, 0x18, 0x1f, 0xca, 0x79, 0xe7, 0x8b, 0x7c, 0x2d, 0xc8, 0x65, 0xc5, ++ 0x0c, 0x58, 0x5a, 0x49, 0xdf, 0x3c, 0xa0, 0x3f, 0x75, 0xfa, 0xaf, 0xc8, ++ 0x63, 0xe7, 0xfd, 0xad, 0x55, 0x01, 0xaa, 0x77, 0xd3, 0xb8, 0x7d, 0x72, ++ 0xb5, 0x9f, 0xbe, 0x1f, 0xf7, 0x31, 0x06, 0xb2, 0xab, 0xff, 0x2c, 0x7e, ++ 0x00, 0x3a, 0xd2, 0xba, 0x7b, 0x77, 0xc3, 0xba, 0x7c, 0x31, 0xfc, 0x75, ++ 0x76, 0xdc, 0xbd, 0xca, 0x86, 0xfa, 0xf2, 0x04, 0xf3, 0xa3, 0xbe, 0x94, ++ 0xeb, 0x1a, 0x52, 0xdd, 0x9d, 0x86, 0x75, 0x3c, 0x8d, 0x42, 0x8f, 0x02, ++ 0x5e, 0x4c, 0xc8, 0x07, 0xce, 0x1f, 0xf9, 0x58, 0xb3, 0x4f, 0xa7, 0x9f, ++ 0x05, 0xfd, 0x86, 0x32, 0x2e, 0x6f, 0x32, 0x3e, 0x19, 0x8a, 0x1b, 0x2c, ++ 0xd0, 0xbe, 0xd6, 0x33, 0x5c, 0xea, 0x1b, 0xca, 0x17, 0x9c, 0x7a, 0xf1, ++ 0xe5, 0x67, 0xd7, 0x50, 0x5c, 0xc1, 0xe9, 0xd5, 0x58, 0xcd, 0xe9, 0x2b, ++ 0xe5, 0xf5, 0x0e, 0x4f, 0xe8, 0x5e, 0x0f, 0xca, 0xc1, 0xec, 0xfb, 0x68, ++ 0x7f, 0x07, 0xfa, 0x55, 0xa0, 0xbe, 0xab, 0xdb, 0xc0, 0xe7, 0x81, 0x7e, ++ 0x1d, 0x8c, 0xe4, 0xb6, 0xab, 0xa0, 0x1a, 0xf0, 0xf7, 0x2f, 0x9e, 0xd4, ++ 0x84, 0x74, 0x73, 0x06, 0x3b, 0x6c, 0xf4, 0xbe, 0xe0, 0xff, 0x73, 0xfb, ++ 0xaf, 0x8e, 0x20, 0x1f, 0xba, 0x6e, 0xed, 0xad, 0xc2, 0xfb, 0xc0, 0x0f, ++ 0x04, 0x4f, 0x67, 0x47, 0x6a, 0x04, 0xe3, 0x66, 0xf2, 0x97, 0xf1, 0xfd, ++ 0x97, 0x15, 0x6e, 0xbf, 0x58, 0x88, 0xf0, 0x32, 0xbf, 0xda, 0xe1, 0xd7, ++ 0xf3, 0x89, 0x84, 0xaf, 0x8f, 0xee, 0x0c, 0xe8, 0x7e, 0x75, 0xec, 0xfe, ++ 0x90, 0x6a, 0x3e, 0x6e, 0xe3, 0x3e, 0x18, 0x97, 0x8f, 0x43, 0xf2, 0x53, ++ 0x77, 0x17, 0xa3, 0x7c, 0xb3, 0xa4, 0x0f, 0x80, 0x1c, 0xc6, 0xfc, 0xbe, ++ 0xd4, 0x3b, 0x2e, 0xfc, 0x2c, 0x3e, 0x33, 0x86, 0x47, 0x89, 0x3f, 0xf9, ++ 0x7e, 0x03, 0xbe, 0xcf, 0x78, 0xde, 0x00, 0xe3, 0xbd, 0x46, 0xd6, 0x4d, ++ 0xf9, 0xd3, 0x3a, 0x35, 0x98, 0x87, 0xf1, 0x1a, 0xcb, 0x4e, 0xa2, 0xef, ++ 0x54, 0x21, 0x0e, 0x26, 0xfd, 0x73, 0xc4, 0xc6, 0x34, 0x1b, 0xbc, 0xff, ++ 0x1a, 0x5c, 0xd1, 0xbe, 0x4f, 0x52, 0x97, 0xd0, 0xf7, 0x42, 0x93, 0x8a, ++ 0x15, 0x92, 0x73, 0xd0, 0x10, 0x32, 0x6f, 0x16, 0x45, 0x3f, 0xf2, 0xe6, ++ 0xf1, 0x29, 0xa4, 0x1f, 0xd8, 0x17, 0xf7, 0x0e, 0xc6, 0xf5, 0xb8, 0x52, ++ 0x38, 0xdf, 0xc1, 0x38, 0x56, 0x31, 0x8e, 0x95, 0xfc, 0x54, 0xa1, 0x0f, ++ 0x7f, 0x53, 0x00, 0xfa, 0x50, 0x89, 0xe9, 0xf1, 0x23, 0x8a, 0x42, 0xe3, ++ 0x1c, 0xb9, 0xfe, 0xaa, 0xed, 0x54, 0x9b, 0x29, 0xd6, 0x89, 0xe3, 0xa1, ++ 0xdf, 0x70, 0x44, 0x99, 0x91, 0x47, 0xfe, 0xac, 0xc8, 0x6f, 0x00, 0xde, ++ 0x86, 0xeb, 0xfd, 0xb3, 0x18, 0xff, 0x86, 0x05, 0x5c, 0xdd, 0x05, 0xf8, ++ 0x5c, 0x1f, 0x27, 0x61, 0x5c, 0xd3, 0x17, 0x67, 0x85, 0xc7, 0xaf, 0xbb, ++ 0x11, 0xe2, 0xac, 0x31, 0x53, 0x3a, 0xa2, 0x26, 0x07, 0x4a, 0xc3, 0x84, ++ 0xe9, 0xdf, 0x81, 0x79, 0x27, 0x41, 0x9c, 0x65, 0x83, 0xf5, 0xdf, 0x8f, ++ 0x7c, 0x8c, 0xfa, 0xbe, 0x30, 0xac, 0xa6, 0x21, 0x5c, 0x43, 0x60, 0xdd, ++ 0x70, 0xeb, 0x68, 0x72, 0xa8, 0xb4, 0xc9, 0x1e, 0x9b, 0xc7, 0x2d, 0xf2, ++ 0x5f, 0x6e, 0x51, 0xb7, 0x8c, 0xfe, 0x3c, 0x5e, 0xcd, 0x5e, 0x6e, 0x57, ++ 0xd6, 0x7b, 0xb9, 0xdd, 0xe8, 0x16, 0x57, 0x70, 0x3b, 0x12, 0xe6, 0xcb, ++ 0xfe, 0x53, 0x3c, 0xff, 0x77, 0x3b, 0xd7, 0xe3, 0x6b, 0x2a, 0x13, 0xd7, ++ 0x37, 0x6f, 0xf1, 0x18, 0xf3, 0x9d, 0x37, 0x8b, 0xfd, 0x22, 0x88, 0xb7, ++ 0xb6, 0x20, 0xff, 0x40, 0xbc, 0x25, 0xea, 0x77, 0xf9, 0xfe, 0x12, 0xf8, ++ 0xb5, 0x84, 0xdf, 0xaa, 0x07, 0xab, 0x69, 0xdf, 0xf4, 0xf3, 0xae, 0x59, ++ 0xe9, 0xfc, 0xbc, 0x07, 0x2e, 0xff, 0x0b, 0x44, 0xfd, 0xec, 0x5d, 0xf7, ++ 0xcf, 0xfa, 0x21, 0xf2, 0xdd, 0x87, 0x58, 0x57, 0x0f, 0x74, 0xfc, 0x48, ++ 0xec, 0xef, 0x7d, 0xe8, 0x08, 0xa4, 0x61, 0x9d, 0x59, 0x7d, 0x72, 0xe2, ++ 0x3a, 0xea, 0x5f, 0x7a, 0xf8, 0x3a, 0xeb, 0x05, 0x1e, 0x4e, 0xaf, 0xe0, ++ 0xe7, 0x33, 0x2c, 0xc0, 0x7d, 0x4d, 0xf0, 0x83, 0x77, 0x7b, 0xb8, 0xfd, ++ 0x5a, 0xd4, 0x7e, 0xcb, 0x64, 0xa4, 0xfb, 0x22, 0x88, 0xe3, 0x71, 0x5f, ++ 0x53, 0xd6, 0x4f, 0x48, 0x3a, 0xd7, 0x6c, 0x55, 0x0d, 0xfb, 0x13, 0x0b, ++ 0x70, 0x5f, 0x33, 0xeb, 0x1f, 0x89, 0x23, 0xca, 0x06, 0x88, 0x23, 0x46, ++ 0x19, 0xe2, 0x08, 0x39, 0x6f, 0x7c, 0x3c, 0x71, 0x6a, 0x85, 0xc7, 0xb0, ++ 0x8f, 0x32, 0xb7, 0xbd, 0x58, 0x9c, 0x8f, 0xc1, 0xfb, 0xcf, 0x63, 0x7e, ++ 0x82, 0x7b, 0x5e, 0x5b, 0xae, 0x61, 0x1f, 0x96, 0xb5, 0xb9, 0xbe, 0xd2, ++ 0xb9, 0x06, 0x18, 0x3f, 0x84, 0x13, 0xc2, 0x67, 0x31, 0xdc, 0x3f, 0xb5, ++ 0xc2, 0x0a, 0x02, 0xae, 0x83, 0xe3, 0x93, 0xc1, 0x54, 0x7f, 0xb2, 0xc5, ++ 0x13, 0xfa, 0x9d, 0xc7, 0x00, 0x47, 0x0a, 0x0b, 0x1b, 0xf2, 0xc9, 0xe3, ++ 0x1c, 0xb4, 0xdf, 0x6f, 0xe3, 0x79, 0x6c, 0xa0, 0x7f, 0x58, 0xef, 0x57, ++ 0xc7, 0xc3, 0x75, 0xc6, 0xf3, 0x8f, 0xc6, 0x6b, 0xc5, 0x03, 0xe0, 0xb9, ++ 0xe4, 0x7f, 0x25, 0x5e, 0xab, 0x18, 0xc7, 0xf5, 0x1a, 0x6b, 0x57, 0xa8, ++ 0x96, 0x66, 0xcc, 0xc4, 0x38, 0xff, 0x59, 0xd8, 0xcb, 0x4b, 0x9e, 0x14, ++ 0x43, 0x1e, 0x60, 0x7e, 0xb5, 0xb1, 0x9f, 0xea, 0xe5, 0xf1, 0xbf, 0xea, ++ 0x4d, 0x31, 0xf8, 0xcd, 0x03, 0xe5, 0x01, 0xf4, 0x7e, 0xb3, 0x52, 0x8c, ++ 0xfa, 0x83, 0x8f, 0xd7, 0x20, 0xec, 0x56, 0xe1, 0x67, 0x6f, 0x53, 0x1d, ++ 0xeb, 0x78, 0x2f, 0xf7, 0x33, 0xc6, 0xe6, 0x04, 0x92, 0xbd, 0x70, 0x5d, ++ 0x27, 0xea, 0xd8, 0xd7, 0xd9, 0xf8, 0x77, 0xfe, 0xdb, 0xfe, 0x7e, 0xc8, ++ 0x33, 0x0f, 0xfd, 0x8d, 0x37, 0xcd, 0x54, 0x77, 0xc0, 0xf6, 0x71, 0xfe, ++ 0xa9, 0xfc, 0xf1, 0xb2, 0x66, 0x3c, 0x37, 0xc0, 0xde, 0xa1, 0x38, 0xf4, ++ 0xdf, 0xb5, 0x7e, 0x63, 0xb9, 0x12, 0x98, 0x0f, 0xf2, 0xe0, 0x16, 0x7a, ++ 0xa2, 0xce, 0xcf, 0xd7, 0x53, 0xe7, 0x8f, 0x5a, 0x06, 0xdb, 0xb1, 0xae, ++ 0x99, 0xc3, 0x91, 0xd7, 0x71, 0x50, 0xd1, 0x74, 0x7a, 0x23, 0xaf, 0x86, ++ 0xf7, 0xf3, 0x79, 0xcd, 0x86, 0xfa, 0x80, 0xc1, 0x5e, 0x7e, 0x2e, 0x43, ++ 0x91, 0x57, 0xe6, 0x0d, 0x23, 0x07, 0xa7, 0x3a, 0xb1, 0x7f, 0x40, 0x43, ++ 0x3b, 0x93, 0xd3, 0xa1, 0x90, 0x1d, 0xca, 0x69, 0x62, 0xf4, 0x3d, 0x4e, ++ 0xce, 0x28, 0xee, 0x9f, 0x7d, 0x63, 0xd4, 0x36, 0x65, 0x5e, 0x69, 0x6c, ++ 0xbd, 0x6d, 0xa6, 0x19, 0xa5, 0x0e, 0x78, 0xaf, 0xcd, 0x9d, 0xe2, 0x47, ++ 0xbd, 0xbd, 0x2a, 0x27, 0x74, 0xa5, 0x17, 0xe1, 0x3b, 0x19, 0x8d, 0x62, ++ 0x3a, 0x67, 0xcc, 0xc9, 0x2e, 0x0d, 0xe3, 0xa7, 0x0d, 0x39, 0x81, 0xab, ++ 0x10, 0x0f, 0x72, 0x9d, 0x3e, 0xd5, 0x91, 0x83, 0xf6, 0x27, 0xe5, 0x24, ++ 0x87, 0xaf, 0xbd, 0x2f, 0x2f, 0xc1, 0xf5, 0x36, 0x63, 0x6b, 0x05, 0x5c, ++ 0xdb, 0x79, 0x7c, 0xa8, 0xb2, 0x63, 0x8c, 0xfb, 0xbd, 0xb4, 0x8f, 0xeb, ++ 0x5e, 0x35, 0x94, 0xec, 0x87, 0x5c, 0x8f, 0x3b, 0x53, 0xe8, 0x5f, 0x37, ++ 0x0b, 0xed, 0x21, 0xff, 0x9b, 0xb5, 0x91, 0xfd, 0xb3, 0x72, 0x7b, 0xea, ++ 0x5e, 0x55, 0x42, 0x7e, 0xb2, 0xa4, 0x6b, 0x2c, 0x9f, 0x32, 0xac, 0x1c, ++ 0xf3, 0x29, 0xc5, 0xeb, 0xa2, 0xda, 0x5c, 0x78, 0xef, 0xc5, 0xad, 0xa6, ++ 0x84, 0xe7, 0x58, 0x4c, 0x15, 0x78, 0x87, 0x75, 0x4c, 0xd4, 0xaf, 0xe3, ++ 0x72, 0xf2, 0x2e, 0xfb, 0x99, 0x07, 0xc8, 0x53, 0x49, 0xbe, 0x4f, 0x99, ++ 0x92, 0x38, 0xfe, 0x83, 0x08, 0x90, 0x9e, 0x57, 0xfe, 0xd8, 0xf9, 0x4d, ++ 0x92, 0xcf, 0x16, 0x0b, 0xc3, 0xfc, 0xa6, 0xc4, 0xff, 0x86, 0x9c, 0xe0, ++ 0x6c, 0x84, 0x27, 0xa7, 0x63, 0x9b, 0x82, 0xb8, 0x39, 0x25, 0xea, 0x23, ++ 0x4e, 0x25, 0xf3, 0xfc, 0xed, 0xa9, 0x35, 0xcf, 0x2a, 0xe8, 0x87, 0xdd, ++ 0xbb, 0x98, 0x39, 0x54, 0x36, 0x30, 0xdc, 0x75, 0xcb, 0xd5, 0xc0, 0x7c, ++ 0xbd, 0x3c, 0xb7, 0x58, 0x88, 0x2e, 0x32, 0x0e, 0x88, 0xc1, 0xc3, 0xe3, ++ 0x96, 0x26, 0x2f, 0xd7, 0xeb, 0xaf, 0xe7, 0x04, 0x17, 0x21, 0xbd, 0x1b, ++ 0xf6, 0xad, 0xa7, 0xfc, 0xde, 0xe2, 0x1d, 0xef, 0x5b, 0xbe, 0x74, 0xff, ++ 0xe3, 0x2b, 0xe2, 0x4d, 0xa9, 0xe1, 0xf1, 0x4d, 0xdd, 0x1c, 0x2b, 0xd5, ++ 0x51, 0x55, 0xfe, 0x58, 0x23, 0xba, 0xd7, 0xb6, 0x58, 0x68, 0xbf, 0xb2, ++ 0x6e, 0xd7, 0x6e, 0xfa, 0x8e, 0x8d, 0xdd, 0xc7, 0xfc, 0x28, 0xff, 0x75, ++ 0x1d, 0xbb, 0x95, 0xf9, 0x30, 0x6f, 0xed, 0xae, 0xdd, 0xca, 0x02, 0x1d, ++ 0x1e, 0x73, 0xeb, 0x22, 0x54, 0x37, 0x7e, 0x45, 0xaa, 0xcc, 0x5f, 0x47, ++ 0x2d, 0xa8, 0xcf, 0xe3, 0xf9, 0x1b, 0xf3, 0xff, 0x68, 0xf7, 0x8f, 0xda, ++ 0xb8, 0xfc, 0x9f, 0xad, 0xb4, 0x87, 0x31, 0x9f, 0x7d, 0xd6, 0x1c, 0xaa, ++ 0xc3, 0x7e, 0x67, 0xbd, 0x29, 0x7e, 0xdc, 0x3f, 0x95, 0x78, 0x7f, 0x6d, ++ 0xf7, 0x8d, 0x74, 0x7e, 0x40, 0xea, 0x9e, 0xa4, 0x28, 0x5e, 0xdb, 0x4c, ++ 0xdb, 0x3d, 0x56, 0xe8, 0xd7, 0x76, 0xa5, 0xc5, 0x8f, 0xfc, 0xb4, 0x21, ++ 0x27, 0xb4, 0x0e, 0xe9, 0x92, 0xa9, 0x05, 0x3b, 0xf1, 0xfd, 0x0c, 0x67, ++ 0xaa, 0x1f, 0xf3, 0xe1, 0xbe, 0x24, 0x56, 0x4e, 0x76, 0xef, 0x2b, 0xe2, ++ 0x61, 0x4c, 0x1c, 0x5f, 0x8c, 0xb9, 0x8f, 0xcb, 0xcb, 0x2b, 0x42, 0xbf, ++ 0xc0, 0x1f, 0xd5, 0x71, 0x3d, 0xed, 0xe5, 0x71, 0x2e, 0x6e, 0x07, 0xa0, ++ 0xbe, 0x3a, 0x6a, 0xe6, 0xeb, 0xd8, 0xc3, 0x38, 0xbc, 0x66, 0x6f, 0xe0, ++ 0x47, 0xc4, 0xb7, 0xc7, 0x32, 0x69, 0xde, 0x9c, 0xba, 0xa8, 0x82, 0x75, ++ 0x1f, 0xf1, 0xf3, 0xc6, 0xf8, 0x2a, 0xb0, 0xcd, 0xeb, 0xfa, 0x3a, 0x70, ++ 0x76, 0x58, 0x50, 0xcf, 0xd7, 0x0a, 0x7d, 0x53, 0xf9, 0xe3, 0x1d, 0xca, ++ 0x07, 0x3a, 0xb8, 0x3b, 0xbc, 0x2a, 0xc1, 0x97, 0xb3, 0x6b, 0x9b, 0x82, ++ 0xf9, 0x16, 0x78, 0x4e, 0xfa, 0x06, 0xfa, 0x33, 0xac, 0xb3, 0xca, 0xd9, ++ 0xc5, 0xf3, 0x4c, 0xb5, 0xf0, 0x7c, 0x81, 0x4e, 0xbf, 0xc8, 0x75, 0x24, ++ 0xd0, 0x33, 0xbf, 0xc0, 0xf5, 0xd8, 0x4f, 0x76, 0x1d, 0xe6, 0x7a, 0x26, ++ 0xca, 0xf3, 0xcb, 0x02, 0xde, 0x78, 0x7a, 0x1e, 0xf2, 0xfa, 0x68, 0xfe, ++ 0xc9, 0x60, 0x66, 0xe9, 0xbe, 0x25, 0x3c, 0x14, 0xe3, 0xd0, 0xa3, 0x45, ++ 0xc9, 0x34, 0x9e, 0x94, 0xfb, 0x78, 0x39, 0x3d, 0xe4, 0xe5, 0xfe, 0x58, ++ 0xce, 0xd6, 0x1d, 0x8a, 0xc9, 0x4e, 0x79, 0x78, 0xf2, 0xcb, 0x24, 0x7c, ++ 0xb2, 0xdf, 0xd8, 0x9c, 0x09, 0xaf, 0x21, 0x3c, 0x63, 0xa6, 0x74, 0x11, ++ 0x1e, 0xea, 0xb7, 0x6a, 0xb4, 0x9e, 0x49, 0x96, 0xe0, 0xe0, 0x25, 0x3a, ++ 0x79, 0xf8, 0xad, 0x90, 0x9b, 0x57, 0x67, 0xff, 0x91, 0xce, 0xdb, 0xd9, ++ 0xf0, 0x8b, 0xb7, 0x88, 0x1f, 0xeb, 0xdb, 0x15, 0x1e, 0x0f, 0xb4, 0xbf, ++ 0x65, 0x99, 0x85, 0x76, 0x26, 0xfc, 0x13, 0x15, 0xf7, 0x4d, 0xa6, 0x71, ++ 0xd3, 0xce, 0x36, 0x8a, 0xf3, 0xa8, 0xa6, 0x75, 0x72, 0x3d, 0x5c, 0xdf, ++ 0xb9, 0x5b, 0x9b, 0x67, 0x8f, 0xf1, 0x69, 0xe1, 0x67, 0xaf, 0xd2, 0x39, ++ 0x56, 0xf5, 0x1d, 0x49, 0x0c, 0xf7, 0x53, 0x81, 0xff, 0xfe, 0x80, 0xf4, ++ 0x8b, 0xe7, 0x53, 0x89, 0x1f, 0xa9, 0x67, 0x07, 0xa2, 0x27, 0xe8, 0x23, ++ 0xfe, 0xfd, 0x43, 0xd8, 0x22, 0xf2, 0xd7, 0xa1, 0xc2, 0x99, 0xa9, 0x31, ++ 0x3d, 0x6d, 0x16, 0x78, 0x61, 0x76, 0x7e, 0xff, 0xa2, 0x58, 0x57, 0x8c, ++ 0x7f, 0x42, 0xe7, 0x70, 0xfe, 0x98, 0x9e, 0xb5, 0x91, 0x5c, 0x14, 0x7e, ++ 0x56, 0xfe, 0x2a, 0xd6, 0x99, 0xd6, 0xfb, 0x15, 0x3a, 0xbf, 0xc3, 0x59, ++ 0xc5, 0xf1, 0xa9, 0x87, 0x6b, 0x46, 0xc2, 0x7d, 0x32, 0xae, 0x27, 0x31, ++ 0x4f, 0xce, 0xf3, 0x2a, 0xdd, 0x05, 0x33, 0x75, 0xdf, 0x93, 0xf5, 0xe9, ++ 0x7b, 0xf1, 0xfe, 0x7f, 0x22, 0xbd, 0xb9, 0xdd, 0x88, 0xf2, 0xfb, 0xac, ++ 0x08, 0xed, 0xb7, 0x84, 0x3f, 0x9e, 0x7e, 0x57, 0xe4, 0x70, 0x3f, 0x36, ++ 0x01, 0x9f, 0x69, 0x39, 0x09, 0xec, 0x99, 0xb4, 0xf3, 0x85, 0x8f, 0xef, ++ 0xd1, 0xf0, 0x7b, 0x20, 0xc9, 0x3f, 0xd3, 0x90, 0xee, 0x3a, 0xfe, 0xc9, ++ 0xca, 0xb1, 0xd0, 0xb8, 0x59, 0x39, 0x1a, 0xc1, 0xb3, 0xb1, 0x92, 0xef, ++ 0x5f, 0x6d, 0x34, 0x73, 0x3b, 0xb6, 0x71, 0xa5, 0x95, 0xea, 0x42, 0x5f, ++ 0xbb, 0x9d, 0xd7, 0xa9, 0xa5, 0x7e, 0xd3, 0x12, 0xc5, 0xeb, 0x11, 0xd3, ++ 0xdc, 0x3a, 0x7c, 0x7e, 0x24, 0x87, 0xc3, 0xd1, 0x66, 0x5a, 0x45, 0xdf, ++ 0xc7, 0x81, 0x5c, 0x3a, 0x73, 0x46, 0x23, 0xff, 0xa4, 0x31, 0xae, 0x1f, ++ 0xb9, 0x3e, 0xdc, 0xf0, 0x3c, 0xd7, 0x67, 0x75, 0x61, 0x7b, 0x04, 0xcf, ++ 0xab, 0xa9, 0x0b, 0xdd, 0x3a, 0x9f, 0xea, 0x10, 0x9c, 0x36, 0x3f, 0xd6, ++ 0xef, 0xb2, 0xd0, 0x61, 0xcb, 0xac, 0xd4, 0xfe, 0x7c, 0xe5, 0xdb, 0x73, ++ 0xd0, 0x82, 0xf0, 0x4f, 0xeb, 0xe0, 0xf2, 0x27, 0xe9, 0x00, 0xfa, 0x94, ++ 0xf8, 0x4b, 0xca, 0x83, 0xc4, 0x6b, 0x0c, 0x9f, 0x11, 0x83, 0x3c, 0x49, ++ 0x7a, 0x98, 0xfb, 0xfc, 0x89, 0x50, 0x21, 0xf7, 0x97, 0x78, 0x9c, 0x52, ++ 0xca, 0x54, 0xda, 0x17, 0xaa, 0xb1, 0x06, 0x8e, 0xe2, 0x77, 0x8c, 0x35, ++ 0x62, 0x3f, 0x15, 0xef, 0x63, 0x9d, 0xab, 0xdc, 0x4f, 0x9d, 0x2b, 0xe8, ++ 0xf2, 0xb8, 0x3d, 0x38, 0x12, 0xd7, 0xd9, 0x6f, 0x3f, 0xf5, 0x2b, 0xfa, ++ 0xd9, 0xb5, 0xcb, 0xdf, 0xa0, 0xb8, 0xe6, 0x1e, 0xcf, 0xeb, 0x74, 0x95, ++ 0x72, 0x0b, 0xf1, 0xa0, 0x41, 0xbe, 0x27, 0x08, 0xba, 0x0f, 0xcb, 0xe1, ++ 0xf6, 0x7d, 0x6a, 0x0e, 0xe7, 0x9b, 0xda, 0x51, 0x1d, 0x24, 0x97, 0xb5, ++ 0x1f, 0x36, 0x91, 0x3c, 0xdb, 0xa7, 0x70, 0xbd, 0x66, 0x3f, 0x69, 0xd4, ++ 0xc7, 0x8c, 0x3d, 0x24, 0xd6, 0xbb, 0x8e, 0xde, 0x9b, 0x94, 0xd2, 0x31, ++ 0x19, 0xf7, 0x21, 0x27, 0x3d, 0xa1, 0x38, 0x30, 0x4e, 0x1e, 0x08, 0xce, ++ 0x45, 0xf8, 0x1d, 0x18, 0xc6, 0x4b, 0x5b, 0x0f, 0xa5, 0xdd, 0x8d, 0xf8, ++ 0xfd, 0x02, 0xbc, 0x75, 0xdd, 0x77, 0x42, 0xdf, 0xcc, 0x11, 0xe7, 0x43, ++ 0xee, 0x04, 0x84, 0x13, 0xbf, 0x37, 0x59, 0xbe, 0xcc, 0x1f, 0xbf, 0xdc, ++ 0x78, 0x2c, 0x7a, 0x5c, 0xa1, 0xf3, 0x42, 0x04, 0x2e, 0xcf, 0xee, 0xaa, ++ 0xba, 0xe6, 0x23, 0xdc, 0x37, 0xd8, 0x99, 0xee, 0xc7, 0xef, 0xf3, 0xcf, ++ 0xec, 0xba, 0xe5, 0xbb, 0x1f, 0x01, 0xdc, 0x67, 0x77, 0x8c, 0xf7, 0xa3, ++ 0x9f, 0xe0, 0x6c, 0x0e, 0x12, 0xff, 0xf4, 0xba, 0x6c, 0xfe, 0xed, 0x3c, ++ 0x1f, 0x3a, 0x05, 0xf3, 0x3d, 0x2b, 0x3b, 0x0e, 0xa5, 0xe1, 0x77, 0x45, ++ 0x9f, 0x3e, 0x3b, 0xa2, 0x1c, 0xf5, 0xf6, 0x12, 0x01, 0xe7, 0x67, 0xcf, ++ 0xab, 0xcb, 0x11, 0x2f, 0xab, 0x9e, 0xf9, 0xf9, 0x0d, 0xf8, 0xbc, 0x36, ++ 0xa2, 0x64, 0xa1, 0xff, 0x7a, 0x76, 0xe7, 0x13, 0xff, 0x95, 0x03, 0xe3, ++ 0xd4, 0xec, 0x68, 0xc4, 0x13, 0xc8, 0x58, 0xf3, 0xb3, 0xbf, 0xa4, 0xb8, ++ 0xc0, 0x14, 0xd9, 0xc6, 0xef, 0xef, 0x4c, 0x27, 0x3f, 0xf7, 0xd3, 0x27, ++ 0xd7, 0xdf, 0x80, 0xf8, 0x6e, 0xee, 0x68, 0xa6, 0xe7, 0x9f, 0x3d, 0xb9, ++ 0x8d, 0xda, 0xaf, 0x3e, 0xf3, 0xf3, 0x57, 0xfe, 0x03, 0xf3, 0x1f, 0xc1, ++ 0x34, 0xfa, 0x3e, 0xfa, 0xb3, 0xe7, 0x0f, 0x12, 0x5d, 0xea, 0x42, 0x1a, ++ 0xd5, 0xc5, 0x0f, 0xc4, 0xd7, 0x1b, 0x77, 0x1f, 0xe4, 0xfa, 0x12, 0xed, ++ 0x3c, 0xca, 0xc1, 0x1c, 0xae, 0xc7, 0x24, 0x5f, 0x4b, 0xfe, 0xfd, 0xf4, ++ 0x99, 0xbb, 0xae, 0xd1, 0xdb, 0x0d, 0x79, 0xbf, 0x4d, 0xe4, 0x41, 0xda, ++ 0x92, 0xb9, 0x1d, 0x39, 0x23, 0xe4, 0xb6, 0x76, 0x82, 0xbd, 0x0d, 0xaf, ++ 0x67, 0x7e, 0x66, 0xa3, 0x73, 0x3b, 0x1b, 0x2c, 0xdd, 0x25, 0x18, 0x1f, ++ 0xd7, 0x95, 0x72, 0xbe, 0x58, 0x91, 0xc3, 0xf5, 0x60, 0x5d, 0xc7, 0x12, ++ 0x73, 0x83, 0x9d, 0xde, 0xa7, 0x71, 0xfe, 0x0d, 0xe4, 0x1d, 0xaf, 0x57, ++ 0x03, 0x7f, 0x62, 0xfd, 0x19, 0xf4, 0xda, 0x71, 0x89, 0xea, 0xa8, 0x9e, ++ 0xa3, 0xfe, 0xd0, 0x6f, 0x2c, 0xe6, 0x49, 0x66, 0x57, 0xbf, 0xcf, 0xbf, ++ 0x2b, 0x2d, 0x6d, 0x32, 0xd7, 0x12, 0x9c, 0xcf, 0xf2, 0xe7, 0xb0, 0x6a, ++ 0xfd, 0xf3, 0x8a, 0x65, 0x89, 0xf7, 0x35, 0xb6, 0xe4, 0xd8, 0x0d, 0xf9, ++ 0xd1, 0x9c, 0xce, 0x19, 0x79, 0x3e, 0xd2, 0x03, 0x49, 0xfe, 0x21, 0x3a, ++ 0xff, 0x37, 0xa7, 0x26, 0xd4, 0x8c, 0x75, 0x02, 0x37, 0x2d, 0x0b, 0xf9, ++ 0xf1, 0x3b, 0xfa, 0x17, 0x3f, 0x79, 0x7b, 0x32, 0xe6, 0xd3, 0x9e, 0x19, ++ 0xaa, 0x8c, 0x24, 0xfa, 0xab, 0x0a, 0xb7, 0x73, 0x61, 0x3b, 0xcd, 0x53, ++ 0x8f, 0xfb, 0x0e, 0x10, 0x7f, 0x3c, 0x2b, 0xe4, 0xc4, 0xed, 0x60, 0xce, ++ 0x6b, 0x61, 0x3d, 0x93, 0x34, 0xe6, 0xb4, 0xe3, 0x95, 0xb1, 0xe3, 0x66, ++ 0xd2, 0x0b, 0x4f, 0xd1, 0xf8, 0xe0, 0xe7, 0x90, 0xff, 0xe6, 0xfb, 0xe5, ++ 0xec, 0xa7, 0xd0, 0xef, 0xd9, 0x68, 0x0e, 0x79, 0x47, 0xe3, 0x38, 0x6d, ++ 0xc2, 0x3e, 0xee, 0xe0, 0xf0, 0xc3, 0xfb, 0x0e, 0x7b, 0x39, 0x8d, 0xe7, ++ 0xb8, 0x96, 0xfb, 0xeb, 0x4b, 0xf1, 0xbd, 0xf3, 0x2b, 0xa7, 0x3b, 0xd1, ++ 0xbf, 0x87, 0x71, 0xbb, 0xcc, 0xba, 0x78, 0x0c, 0x38, 0xb2, 0x00, 0xed, ++ 0x23, 0x8e, 0x37, 0x0a, 0xf1, 0x34, 0x25, 0x3c, 0x87, 0xec, 0x94, 0xcf, ++ 0x42, 0xeb, 0x93, 0xe7, 0x81, 0xc2, 0xfa, 0x29, 0x7f, 0x2a, 0xe5, 0x33, ++ 0x3e, 0x4f, 0x83, 0xfa, 0x09, 0xf3, 0xad, 0xaf, 0xe7, 0x54, 0x1e, 0xce, ++ 0x71, 0xc5, 0xae, 0xee, 0x01, 0xf2, 0x1c, 0xd6, 0x5c, 0xfe, 0x7c, 0x4a, ++ 0x6e, 0x80, 0xae, 0x5f, 0xf5, 0x7c, 0xd1, 0x57, 0x67, 0xf7, 0x70, 0x3b, ++ 0xff, 0xd2, 0xfb, 0xc4, 0xb7, 0x0d, 0xc8, 0xb7, 0x38, 0x7f, 0xe8, 0x43, ++ 0x83, 0x9d, 0x97, 0xf5, 0x11, 0x1b, 0xf7, 0xbf, 0x4f, 0x7c, 0x3b, 0x7f, ++ 0x1f, 0xd7, 0xc7, 0x0d, 0xfb, 0x2a, 0x2d, 0x18, 0x6f, 0x9d, 0x59, 0x11, ++ 0x60, 0x1f, 0x80, 0xa3, 0xdb, 0x20, 0xf8, 0x6f, 0xa3, 0xd2, 0xbd, 0x90, ++ 0xbe, 0x4f, 0xdb, 0x6f, 0xa3, 0xef, 0x0e, 0x7b, 0x24, 0x7f, 0xb6, 0xbf, ++ 0xff, 0x31, 0xea, 0x9f, 0xa2, 0x7d, 0x5e, 0xaa, 0xe7, 0xe9, 0xd9, 0xcf, ++ 0xf9, 0xf4, 0x88, 0xc9, 0x44, 0x79, 0x80, 0x23, 0xdb, 0xaf, 0xda, 0xd6, ++ 0xac, 0xf4, 0xb7, 0xab, 0xe0, 0x6f, 0x93, 0x9c, 0x34, 0x34, 0x31, 0xe1, ++ 0x6f, 0x2f, 0x7b, 0x1b, 0xfd, 0xb3, 0xfa, 0x1a, 0x5e, 0x07, 0xdf, 0x10, ++ 0xc7, 0x47, 0x85, 0x8f, 0x9f, 0x6a, 0x45, 0x7e, 0xc9, 0x00, 0xef, 0x18, ++ 0xeb, 0x32, 0xc0, 0x9f, 0x99, 0x4c, 0xdf, 0x6d, 0xd6, 0xb1, 0xd1, 0x28, ++ 0xa7, 0x39, 0x13, 0x03, 0xfb, 0x73, 0x69, 0xff, 0x9b, 0xc7, 0xe7, 0x39, ++ 0x35, 0xa0, 0x4f, 0xa0, 0x7d, 0x93, 0x73, 0xb1, 0x1f, 0x4b, 0x07, 0x32, ++ 0x26, 0x82, 0x5f, 0x8c, 0xfc, 0xe7, 0xbc, 0xde, 0x8f, 0xf9, 0xa6, 0x8d, ++ 0xf9, 0x1d, 0xad, 0xe8, 0x3f, 0x87, 0x27, 0x31, 0x3a, 0x77, 0x75, 0xa3, ++ 0xb9, 0x7d, 0x02, 0xc6, 0xc1, 0x1b, 0x27, 0xf9, 0x1c, 0x80, 0x49, 0xc0, ++ 0xdb, 0x0e, 0xf2, 0xaf, 0xd9, 0x50, 0x8b, 0xb0, 0x67, 0xf3, 0xc9, 0x2f, ++ 0x6f, 0xf0, 0xfc, 0xab, 0x9f, 0xf2, 0xc1, 0xf1, 0xf2, 0xbf, 0x7f, 0x25, ++ 0xf9, 0x77, 0x0d, 0xbe, 0x64, 0x3f, 0x9e, 0x83, 0x3b, 0x6d, 0x9f, 0xb2, ++ 0x94, 0xfb, 0x33, 0x76, 0x86, 0xf0, 0x37, 0x00, 0x7e, 0xb1, 0x3d, 0x2d, ++ 0x72, 0x5d, 0x04, 0xe1, 0x39, 0x27, 0xf0, 0x27, 0xf1, 0xd8, 0x63, 0xee, ++ 0xa2, 0xf3, 0x78, 0x7b, 0x5e, 0x48, 0xa2, 0xf3, 0x0d, 0xa7, 0x4d, 0xe4, ++ 0xfc, 0x9a, 0x31, 0xb1, 0x83, 0xf4, 0xc7, 0x6b, 0xfb, 0x6f, 0x24, 0x7b, ++ 0x2d, 0xf9, 0x32, 0x75, 0x6f, 0x12, 0xd9, 0xed, 0x4c, 0xcd, 0xa1, 0xf8, ++ 0x29, 0x5f, 0x74, 0x4b, 0x12, 0xc2, 0x33, 0x4f, 0xc0, 0xd3, 0x2e, 0xea, ++ 0x84, 0x33, 0x84, 0x1d, 0x29, 0x5e, 0xc7, 0xfd, 0xb8, 0xcc, 0x5c, 0x2e, ++ 0x4f, 0x99, 0xb9, 0x26, 0x71, 0xb5, 0x18, 0xeb, 0xac, 0x1c, 0x61, 0xca, ++ 0x3b, 0x9c, 0x13, 0xf4, 0x27, 0x36, 0xd1, 0x9d, 0xfb, 0x54, 0x3f, 0x3f, ++ 0x4a, 0xf2, 0x54, 0xb7, 0x8b, 0x8f, 0xe7, 0x4c, 0x0a, 0x94, 0xdd, 0xab, ++ 0xe3, 0x5f, 0xe9, 0x5f, 0xc9, 0x7a, 0x03, 0xac, 0x1b, 0x98, 0x91, 0x80, ++ 0xbf, 0xc7, 0xe6, 0x72, 0x3b, 0x58, 0xf8, 0xf8, 0x52, 0xa2, 0xfb, 0xbc, ++ 0x1a, 0x71, 0x3e, 0xc4, 0x3a, 0xee, 0x57, 0x30, 0xe0, 0x0b, 0xc4, 0x1b, ++ 0xd0, 0x91, 0xf8, 0xe0, 0x26, 0xe7, 0x22, 0xa2, 0xdb, 0xbc, 0x75, 0xca, ++ 0x37, 0x89, 0x8e, 0xe1, 0x0a, 0xca, 0x1b, 0x4a, 0xff, 0x2c, 0x7e, 0xfc, ++ 0x71, 0x62, 0x7d, 0x3b, 0x6d, 0xc1, 0x51, 0x58, 0x67, 0xd8, 0xeb, 0x4a, ++ 0xf5, 0xe3, 0x7e, 0xd7, 0xce, 0x8c, 0x80, 0x89, 0xf2, 0xee, 0x65, 0x19, ++ 0x94, 0x07, 0x71, 0x65, 0x71, 0x7f, 0xd1, 0x25, 0xfc, 0xc5, 0x98, 0xdc, ++ 0x07, 0x47, 0x99, 0x60, 0x9e, 0x4f, 0xdc, 0xa9, 0x9c, 0xde, 0x91, 0xdf, ++ 0x68, 0x98, 0x17, 0x9e, 0x92, 0xeb, 0x4b, 0xe8, 0xe7, 0xf5, 0x8f, 0xf3, ++ 0xf9, 0x78, 0xd3, 0xdb, 0xc3, 0xc3, 0x31, 0xee, 0x91, 0xf5, 0x61, 0x12, ++ 0x1f, 0x91, 0x95, 0xc9, 0x73, 0xf4, 0xfa, 0x74, 0x82, 0xa0, 0x4b, 0x64, ++ 0x18, 0x9b, 0x83, 0x7a, 0x03, 0xe2, 0x09, 0x3b, 0xe5, 0xaf, 0x1d, 0x30, ++ 0x0f, 0xe6, 0x13, 0xb6, 0x5f, 0xf7, 0x24, 0xcf, 0x27, 0xf0, 0x73, 0xa1, ++ 0xaf, 0xca, 0xe5, 0xdf, 0x35, 0x4f, 0xca, 0x0a, 0x8e, 0xa2, 0xfd, 0xbf, ++ 0xe2, 0xe0, 0x32, 0x6e, 0x3f, 0xf9, 0x3a, 0xe3, 0xf1, 0xf1, 0xba, 0xb0, ++ 0x9b, 0xaf, 0xce, 0xbe, 0xb3, 0x0c, 0xe3, 0xd8, 0x86, 0x5b, 0xed, 0x7e, ++ 0x94, 0xbb, 0x0d, 0x2f, 0x29, 0x73, 0x89, 0xaf, 0xc3, 0x56, 0x3c, 0x3c, ++ 0x08, 0xf8, 0x9e, 0xcb, 0x21, 0x38, 0x4c, 0x54, 0x0f, 0xc5, 0x42, 0x1a, ++ 0xd1, 0xa3, 0xa1, 0x29, 0x18, 0x49, 0xcc, 0xf7, 0x33, 0x48, 0xce, 0x1a, ++ 0xc0, 0xef, 0xc3, 0x38, 0x60, 0x1a, 0xf2, 0xb9, 0x93, 0xf8, 0x3e, 0xc2, ++ 0xf9, 0x9e, 0xdb, 0x3f, 0x99, 0x6f, 0x40, 0x3d, 0xa9, 0xf7, 0xb7, 0xa5, ++ 0x3e, 0x90, 0x7a, 0x06, 0xed, 0x1b, 0xf2, 0xb3, 0x94, 0x8b, 0x86, 0x1b, ++ 0xba, 0x4b, 0x90, 0xbe, 0x5f, 0x55, 0xaf, 0xf4, 0x98, 0xb9, 0x9c, 0xf7, ++ 0x00, 0x1e, 0x50, 0x8e, 0xa4, 0xdc, 0xa4, 0xbe, 0xc8, 0xe5, 0x65, 0xcd, ++ 0x4a, 0x5f, 0x25, 0x3e, 0x5f, 0x03, 0x72, 0xaf, 0xa7, 0x77, 0x7c, 0x7c, ++ 0x86, 0x70, 0x62, 0xbc, 0x22, 0xf5, 0xfb, 0xaa, 0x9c, 0xe0, 0xb7, 0x73, ++ 0x11, 0x4e, 0x53, 0xb4, 0x95, 0xbe, 0x7d, 0x15, 0xfa, 0xb8, 0xe1, 0xc5, ++ 0xd5, 0x25, 0x89, 0xbe, 0x5f, 0x92, 0xfa, 0xd8, 0x2a, 0xce, 0xd3, 0xb4, ++ 0x46, 0x52, 0x22, 0xfa, 0x7d, 0x06, 0xdc, 0xb3, 0x4f, 0x2d, 0xa7, 0x6b, ++ 0x18, 0xed, 0x51, 0xca, 0xf2, 0xc4, 0xf9, 0x98, 0xd5, 0xb9, 0xd2, 0xbe, ++ 0xf6, 0xab, 0x77, 0x5a, 0x9d, 0xeb, 0xea, 0x5f, 0xef, 0xe4, 0x46, 0xdb, ++ 0x85, 0xf2, 0xb3, 0x3d, 0x85, 0xbe, 0xa3, 0x93, 0xf9, 0xa9, 0xf8, 0x71, ++ 0xbf, 0x2f, 0xf8, 0x4d, 0xd2, 0x45, 0xc6, 0x29, 0xb8, 0x5f, 0x80, 0xfd, ++ 0x9f, 0x12, 0xf2, 0xb3, 0x59, 0xc8, 0xe9, 0x73, 0xe2, 0xaa, 0x8b, 0x7f, ++ 0x88, 0xff, 0x7d, 0xa6, 0xd0, 0xfb, 0xb8, 0xdf, 0x3f, 0x90, 0x1d, 0x93, ++ 0xef, 0xfd, 0xb3, 0xf2, 0x65, 0x72, 0x1e, 0x69, 0x4f, 0xe3, 0xe9, 0x2f, ++ 0xf7, 0x3b, 0x70, 0x3d, 0x33, 0x4a, 0x07, 0xee, 0xd7, 0x7e, 0x50, 0xc4, ++ 0x81, 0x71, 0xfc, 0xf8, 0x82, 0xf0, 0xa7, 0xee, 0xcd, 0x65, 0x74, 0x6d, ++ 0x37, 0x47, 0x3f, 0x27, 0xb9, 0x5a, 0x92, 0xca, 0x68, 0x9f, 0x6d, 0x33, ++ 0x0b, 0x64, 0xe1, 0x7e, 0xd9, 0x2b, 0x57, 0x70, 0x79, 0x08, 0xf4, 0x96, ++ 0xe0, 0xf8, 0x57, 0xe6, 0x87, 0x32, 0xf2, 0x46, 0xc7, 0xf2, 0xc2, 0x78, ++ 0x1f, 0xe3, 0x93, 0x5a, 0x8d, 0x85, 0x71, 0x9f, 0xac, 0x76, 0xa7, 0x39, ++ 0xa2, 0xff, 0x8e, 0x67, 0x27, 0x7e, 0x48, 0x09, 0xfd, 0xcf, 0xa7, 0x5a, ++ 0xc3, 0x2a, 0xf0, 0xf9, 0xb8, 0xfc, 0xd0, 0x61, 0xa4, 0x67, 0x78, 0x02, ++ 0xff, 0x5e, 0x2f, 0xfc, 0x3d, 0x1b, 0xed, 0xff, 0x80, 0x23, 0x3d, 0x1a, ++ 0xf5, 0x4b, 0x23, 0xeb, 0x4e, 0x43, 0x3c, 0x37, 0xa8, 0x5d, 0x25, 0x98, ++ 0xc7, 0xdc, 0xe2, 0x0e, 0xbd, 0x8e, 0xfd, 0x4f, 0x99, 0xba, 0x0a, 0x78, ++ 0xbd, 0x05, 0xdf, 0x9f, 0x3a, 0x29, 0xf2, 0xbe, 0x27, 0x45, 0xde, 0xb7, ++ 0xd3, 0x12, 0xcd, 0xff, 0x8e, 0x33, 0x76, 0xce, 0xdd, 0x05, 0xc6, 0xeb, ++ 0x75, 0x2e, 0x74, 0x99, 0x32, 0x31, 0x0e, 0x7c, 0x6f, 0xdf, 0x3b, 0x3f, ++ 0x7b, 0x09, 0xde, 0xbe, 0xe3, 0xa5, 0x73, 0x77, 0x7c, 0x1f, 0xb1, 0xb5, ++ 0x26, 0xe5, 0xce, 0x1f, 0xc1, 0xb5, 0xda, 0xaa, 0x06, 0xf5, 0xe7, 0xff, ++ 0x9c, 0x4c, 0x4d, 0xac, 0x67, 0x4f, 0x09, 0x3e, 0xea, 0xab, 0xa7, 0x59, ++ 0x99, 0x94, 0x30, 0xef, 0xbf, 0x27, 0x8f, 0xf3, 0x41, 0x63, 0xdc, 0xfe, ++ 0xef, 0x9e, 0x3c, 0x1f, 0xbf, 0xdf, 0xf7, 0x5d, 0x16, 0xdf, 0xff, 0x7d, ++ 0x6f, 0x80, 0x73, 0xb2, 0x26, 0xe7, 0x71, 0xfa, 0x74, 0x8a, 0x3a, 0x9f, ++ 0xf8, 0xe7, 0xd3, 0xc4, 0x3c, 0x3b, 0xcd, 0xac, 0x64, 0x33, 0xc2, 0xb3, ++ 0x2d, 0x95, 0xf6, 0xd7, 0x99, 0xc6, 0xcf, 0x37, 0xab, 0x79, 0xa4, 0xd0, ++ 0x8f, 0xfb, 0x92, 0x9d, 0x45, 0xfc, 0xfc, 0xfc, 0xde, 0x47, 0x15, 0xb2, ++ 0x03, 0x27, 0xcd, 0x5c, 0xff, 0xc0, 0xdf, 0xad, 0xd6, 0x8a, 0x98, 0x1d, ++ 0x45, 0x37, 0x05, 0xfd, 0xc4, 0x1a, 0x47, 0x38, 0x6a, 0x02, 0xfd, 0x51, ++ 0xb3, 0x2c, 0x35, 0x8a, 0xe7, 0x67, 0xc2, 0x7d, 0x6d, 0x1c, 0xca, 0x5a, ++ 0xd8, 0x41, 0xf5, 0xa6, 0x73, 0x85, 0x7d, 0x9c, 0xd7, 0xf4, 0xda, 0xdf, ++ 0x30, 0xef, 0x51, 0xa3, 0x31, 0xeb, 0x38, 0x78, 0xef, 0xb4, 0x7d, 0x7e, ++ 0x1a, 0x9a, 0x87, 0x85, 0xdf, 0xba, 0x17, 0x8f, 0xc0, 0x61, 0xd9, 0xd5, ++ 0xed, 0xa2, 0x2e, 0x51, 0x9c, 0xd7, 0x16, 0x98, 0xae, 0x5e, 0x4a, 0xf9, ++ 0x32, 0xbf, 0xce, 0xf8, 0x5d, 0xcb, 0xde, 0xbc, 0xa0, 0x15, 0xf9, 0xac, ++ 0x3a, 0x9d, 0xe3, 0xbb, 0xfa, 0x5e, 0x7e, 0x4e, 0xaf, 0xec, 0xff, 0x92, ++ 0x90, 0xdb, 0x7e, 0xfc, 0x86, 0xbc, 0x0a, 0xf0, 0xfe, 0x51, 0xe1, 0xf6, ++ 0x25, 0x7e, 0x1e, 0x77, 0xfe, 0x84, 0xe7, 0x51, 0xbf, 0x2d, 0xf7, 0x04, ++ 0xb3, 0x68, 0xfc, 0x7b, 0xcf, 0x19, 0xf4, 0x5a, 0x8f, 0xd2, 0xfd, 0xf4, ++ 0x8f, 0x90, 0x2f, 0x97, 0xa4, 0x8a, 0x73, 0xd4, 0x58, 0x81, 0xbe, 0x5e, ++ 0xca, 0x9f, 0xc7, 0xed, 0x4b, 0x2d, 0xee, 0x37, 0x81, 0x6a, 0x3c, 0x5f, ++ 0xd6, 0x55, 0xb2, 0xbc, 0x10, 0xf9, 0xbf, 0xb7, 0xe0, 0x77, 0x98, 0x77, ++ 0x3b, 0x90, 0x44, 0x75, 0xb1, 0xb5, 0xb8, 0xef, 0xa4, 0xab, 0x67, 0x1b, ++ 0x68, 0xdf, 0x69, 0xe0, 0xfd, 0x26, 0x9f, 0x05, 0xf9, 0xbc, 0xe1, 0xa2, ++ 0x42, 0x7c, 0x32, 0xf7, 0xc0, 0x6b, 0x27, 0x50, 0xaf, 0x37, 0x68, 0xdd, ++ 0xc4, 0x3f, 0x73, 0xad, 0x76, 0xa2, 0x4f, 0xc3, 0x45, 0x8d, 0x9e, 0xb3, ++ 0x36, 0xf3, 0x59, 0xfd, 0x77, 0x7a, 0xed, 0x9e, 0xc0, 0x70, 0x5c, 0x5f, ++ 0xf8, 0xc1, 0x71, 0x19, 0xb4, 0x6f, 0x95, 0x0d, 0xf7, 0x09, 0xcf, 0x43, ++ 0xe9, 0x9c, 0x8f, 0xa5, 0xa2, 0x1e, 0xd9, 0x9d, 0x1f, 0x1a, 0x8d, 0xfd, ++ 0x36, 0xa5, 0xa4, 0xdd, 0x85, 0xf1, 0xe1, 0x05, 0x2b, 0x3f, 0x97, 0xa9, ++ 0xd1, 0xc2, 0xeb, 0x8e, 0x99, 0xf8, 0xfe, 0x59, 0xf2, 0x09, 0xcb, 0x4b, ++ 0x35, 0xf2, 0xc1, 0x81, 0xd7, 0xff, 0x86, 0x70, 0xcd, 0xb7, 0x86, 0xe8, ++ 0x1c, 0xcb, 0x05, 0x73, 0x9a, 0xe8, 0xdc, 0xdc, 0xea, 0xf4, 0xe8, 0x68, ++ 0x47, 0xa9, 0x9e, 0xfe, 0xe3, 0xbe, 0xd6, 0xb9, 0xb9, 0x5e, 0xa1, 0x37, ++ 0xde, 0xb3, 0xf0, 0xfa, 0x9c, 0xfe, 0xfc, 0xcf, 0xe9, 0xb0, 0x27, 0x8f, ++ 0xeb, 0xaf, 0xf7, 0x72, 0xb8, 0x1c, 0xbd, 0x57, 0xc0, 0x6a, 0xf6, 0xe0, ++ 0xf5, 0x4a, 0xb8, 0xc2, 0x7b, 0xef, 0x15, 0x89, 0x76, 0x39, 0x6f, 0xc7, ++ 0x8f, 0xd3, 0x28, 0xe4, 0xe8, 0xbd, 0xe1, 0xdc, 0x7e, 0x85, 0x97, 0xa6, ++ 0x24, 0x3c, 0x97, 0xe4, 0x6e, 0x21, 0x8f, 0x7b, 0xf3, 0x02, 0xb7, 0x23, ++ 0xbe, 0xe4, 0xfd, 0xa7, 0x05, 0x1c, 0xee, 0xfc, 0x40, 0x75, 0x9e, 0x8b, ++ 0xf4, 0x63, 0x48, 0xf0, 0x6d, 0x34, 0x03, 0xc6, 0xab, 0xfe, 0x25, 0xff, ++ 0x1d, 0x03, 0xd6, 0xd2, 0x4b, 0x75, 0x25, 0x7d, 0xeb, 0x2a, 0x11, 0xf0, ++ 0xba, 0x13, 0xc3, 0xd5, 0x12, 0x1b, 0x77, 0x11, 0x8e, 0x07, 0xfd, 0x02, ++ 0xe4, 0xc7, 0xbf, 0x62, 0xa3, 0xef, 0xef, 0xd8, 0x74, 0xd0, 0xd7, 0xa8, ++ 0x9f, 0x97, 0xe6, 0x33, 0xd4, 0xcf, 0x30, 0x6f, 0x63, 0x1e, 0x1f, 0x37, ++ 0x9a, 0x41, 0xfd, 0x92, 0x68, 0x1d, 0xac, 0x0d, 0xf4, 0x36, 0xf0, 0xef, ++ 0xf9, 0xd1, 0x3e, 0xa2, 0xcb, 0x9a, 0x4a, 0xe0, 0xd3, 0x51, 0xe2, 0x5c, ++ 0x7e, 0x5f, 0x8c, 0xaf, 0x24, 0x3f, 0xc5, 0xf3, 0xd1, 0x7d, 0x79, 0xca, ++ 0x40, 0xfb, 0xe2, 0xf7, 0xe1, 0x7c, 0xf1, 0xfb, 0xe2, 0x8c, 0x0d, 0x26, ++ 0x7a, 0x13, 0xbf, 0x7d, 0x8d, 0xef, 0xd8, 0x46, 0x64, 0x71, 0xbc, 0x80, ++ 0xdc, 0xb7, 0xe6, 0x91, 0xfd, 0x8d, 0x5e, 0xad, 0x97, 0x3b, 0x89, 0x67, ++ 0xa9, 0x2f, 0xdf, 0x4b, 0x36, 0xf2, 0x45, 0xaa, 0x80, 0xf3, 0x07, 0xa2, ++ 0x5f, 0x1f, 0x9e, 0xc5, 0x39, 0x5a, 0xce, 0x62, 0x6e, 0x07, 0x65, 0xbc, ++ 0xf0, 0xb8, 0xe8, 0x9f, 0x21, 0xe8, 0x2f, 0xaf, 0xd2, 0xae, 0xc5, 0xef, ++ 0x0f, 0x64, 0x88, 0x71, 0x33, 0xf2, 0xd2, 0x24, 0x5d, 0x1e, 0x13, 0xf4, ++ 0xce, 0x48, 0x48, 0xef, 0xad, 0x9c, 0xde, 0xd0, 0xef, 0x09, 0xec, 0x57, ++ 0x9d, 0xd4, 0x7b, 0x67, 0x16, 0xd8, 0xb3, 0xdb, 0xc0, 0x4f, 0xc2, 0x73, ++ 0x2f, 0xe1, 0x3d, 0x2f, 0xde, 0xef, 0x97, 0xb7, 0x98, 0xc8, 0xed, 0x70, ++ 0xe3, 0xd2, 0x54, 0x86, 0x7e, 0xc2, 0x4f, 0xf2, 0x44, 0xde, 0x6f, 0x54, ++ 0x2f, 0xdf, 0xbf, 0x1b, 0xda, 0x4b, 0xfa, 0x68, 0x2e, 0x03, 0xbd, 0xa3, ++ 0x5c, 0x9e, 0x7e, 0x98, 0x23, 0xf0, 0x82, 0x3e, 0x7c, 0x43, 0xd4, 0x0f, ++ 0x29, 0x58, 0xcf, 0x93, 0x49, 0x6a, 0xc0, 0x87, 0xe3, 0x01, 0xbe, 0x3b, ++ 0xf3, 0x5c, 0x31, 0x7c, 0xc7, 0xcf, 0x77, 0x12, 0x1f, 0x81, 0x5f, 0xf8, ++ 0x4a, 0x9e, 0xf8, 0xbe, 0xaf, 0x8c, 0x95, 0x21, 0xbd, 0xee, 0x7c, 0xeb, ++ 0xcf, 0xa9, 0x77, 0xf8, 0xf0, 0x1c, 0x74, 0xfe, 0x5d, 0xf1, 0x47, 0xf6, ++ 0xd0, 0xab, 0x38, 0xce, 0xd9, 0xef, 0xbe, 0x4e, 0x71, 0xc0, 0x49, 0x4b, ++ 0xb4, 0xa4, 0xdd, 0x9e, 0xe0, 0xb9, 0x25, 0xfa, 0xf8, 0x26, 0x25, 0xf6, ++ 0xfc, 0xae, 0x9f, 0xa8, 0x61, 0xfc, 0xdd, 0x8b, 0xce, 0xae, 0xb3, 0x8f, ++ 0xce, 0x06, 0xbe, 0x9c, 0xdb, 0xa5, 0xfa, 0x71, 0xca, 0xb9, 0xf7, 0x7d, ++ 0xfe, 0xe6, 0x18, 0xf4, 0xaf, 0xbb, 0xcc, 0xb4, 0x0f, 0x05, 0xfe, 0xc5, ++ 0x3a, 0x3c, 0x17, 0x94, 0x35, 0x71, 0x7f, 0xf4, 0xa4, 0xc9, 0x48, 0xff, ++ 0x33, 0xdf, 0x36, 0xd6, 0x75, 0x74, 0x0b, 0x79, 0x95, 0xdf, 0x3b, 0x4b, ++ 0x7d, 0x25, 0xfd, 0x86, 0xc5, 0xcc, 0xcf, 0xf5, 0x54, 0x32, 0x3f, 0x87, ++ 0xfd, 0xd4, 0x92, 0x45, 0xf4, 0xbd, 0xf3, 0x7c, 0x16, 0x3c, 0x8a, 0xe7, ++ 0xb0, 0x7f, 0xba, 0x74, 0x2a, 0xf9, 0xd3, 0x8b, 0x58, 0x88, 0x7e, 0x8f, ++ 0x60, 0x5e, 0x9b, 0xf1, 0x3c, 0xde, 0xf8, 0x73, 0x7c, 0xe3, 0xcf, 0xef, ++ 0xc5, 0x04, 0x3f, 0xe2, 0x2f, 0xfe, 0x1c, 0xdf, 0xbe, 0x7c, 0x7b, 0x55, ++ 0x62, 0x3f, 0x23, 0x35, 0x9f, 0xf3, 0xe1, 0x19, 0x8b, 0xa8, 0x2f, 0x18, ++ 0xc0, 0xcf, 0xb8, 0x28, 0xf8, 0x57, 0xd6, 0x17, 0x34, 0xca, 0xfa, 0x82, ++ 0x97, 0xbf, 0xbc, 0xbe, 0xa0, 0x31, 0xae, 0xbe, 0x20, 0xe6, 0x8f, 0xc8, ++ 0xfa, 0x82, 0x2f, 0x28, 0x4f, 0x68, 0xce, 0xf7, 0xd1, 0xf8, 0x38, 0x9e, ++ 0xbe, 0xce, 0xe0, 0xcc, 0x84, 0xc4, 0x70, 0x2b, 0xf9, 0xd2, 0xef, 0x49, ++ 0x31, 0x8c, 0x2f, 0xc7, 0x89, 0xcd, 0x93, 0x46, 0xcf, 0x1b, 0xf1, 0x3c, ++ 0x9f, 0x84, 0xdf, 0xab, 0xdb, 0xe9, 0xfe, 0x99, 0x85, 0x89, 0xe7, 0x49, ++ 0xcf, 0xe7, 0xeb, 0x6e, 0x8c, 0xab, 0x67, 0x88, 0xbd, 0xcf, 0xeb, 0x18, ++ 0x64, 0x9c, 0x2f, 0xf9, 0xa2, 0xf1, 0xa2, 0x97, 0xec, 0xb1, 0x6c, 0xf7, ++ 0xfd, 0x0e, 0x43, 0xdf, 0x7b, 0x79, 0xf4, 0x3c, 0xfe, 0xfb, 0x7c, 0x99, ++ 0xa7, 0x97, 0x72, 0xf0, 0x81, 0xc2, 0xac, 0x5e, 0xca, 0x9b, 0xad, 0x17, ++ 0x7a, 0xd1, 0x3f, 0x1c, 0xfd, 0xdf, 0x0f, 0xd0, 0xaf, 0x42, 0x39, 0xbc, ++ 0xd1, 0xf7, 0x4a, 0x37, 0x80, 0x38, 0xef, 0xfb, 0xd7, 0x94, 0x68, 0x45, ++ 0x31, 0x39, 0x89, 0x5f, 0x07, 0xf0, 0xd3, 0x67, 0xfa, 0xef, 0xe0, 0x87, ++ 0xe4, 0x8b, 0x73, 0x79, 0xfd, 0xcc, 0x4f, 0xdf, 0x49, 0x0a, 0x3e, 0xbf, ++ 0xf3, 0xbb, 0x93, 0xd2, 0x71, 0x9f, 0xf5, 0xdf, 0xef, 0xab, 0x32, 0x7c, ++ 0xff, 0xd6, 0xf7, 0x7d, 0xbc, 0x45, 0xfa, 0x73, 0x76, 0x83, 0x5d, 0x66, ++ 0x71, 0x76, 0x7b, 0xde, 0xbe, 0xd7, 0xc9, 0x5f, 0x9b, 0x6f, 0x0d, 0xd2, ++ 0x77, 0x78, 0x1f, 0xbd, 0xfc, 0x5d, 0xb2, 0xd7, 0x0b, 0x59, 0xd0, 0x8d, ++ 0xfc, 0x7d, 0xfe, 0xe5, 0x2b, 0x0a, 0x42, 0xff, 0x03, 0x7b, 0x2d, 0xe1, ++ 0xb9, 0x25, 0x7c, 0xb7, 0x99, 0xfb, 0xe9, 0x4e, 0xf2, 0x33, 0x66, 0x0a, ++ 0x78, 0x6e, 0x39, 0xc0, 0xfd, 0x45, 0x93, 0x35, 0x60, 0xa6, 0x79, 0x02, ++ 0xcc, 0xe7, 0x70, 0x53, 0x28, 0xce, 0xe1, 0x05, 0xa5, 0x89, 0xe7, 0xf0, ++ 0x5d, 0xdf, 0x07, 0x7f, 0x29, 0x9d, 0xdf, 0x31, 0x4e, 0xc0, 0xaf, 0xe0, ++ 0xfb, 0x80, 0xdf, 0xeb, 0xc5, 0x95, 0xcd, 0x0d, 0x79, 0x10, 0x6e, 0x79, ++ 0xae, 0x00, 0x70, 0x93, 0x07, 0xaf, 0xcd, 0xd7, 0xf8, 0x7d, 0x78, 0x1d, ++ 0xaf, 0x04, 0x35, 0xa6, 0xfb, 0xde, 0x74, 0x32, 0x6b, 0xca, 0xc3, 0xfe, ++ 0x26, 0x6b, 0xb7, 0x2a, 0xce, 0x3b, 0xa3, 0xf3, 0xe3, 0x93, 0x62, 0xf8, ++ 0xa2, 0x76, 0xaa, 0x68, 0xb7, 0xdc, 0x7a, 0xe1, 0xce, 0x05, 0x78, 0xdf, ++ 0xce, 0xcf, 0x27, 0xb6, 0x08, 0x38, 0x16, 0xe6, 0x8b, 0xef, 0xa8, 0xad, ++ 0xcc, 0x8a, 0xeb, 0x4e, 0xb2, 0x47, 0x3f, 0xa5, 0x7d, 0x40, 0x71, 0x0d, ++ 0x4f, 0xe0, 0xfe, 0x77, 0xb8, 0x88, 0xd7, 0xed, 0x26, 0xe3, 0x79, 0x0a, ++ 0x30, 0xaf, 0xdd, 0x7e, 0x2e, 0x8c, 0x8b, 0x75, 0x30, 0x07, 0x9d, 0x13, ++ 0x60, 0x73, 0x5c, 0x88, 0x62, 0x1c, 0xa2, 0xfb, 0x1d, 0x89, 0x7b, 0xf2, ++ 0x5d, 0xba, 0xdf, 0x91, 0x60, 0x51, 0x9e, 0x9f, 0x1a, 0xe8, 0x79, 0xdc, ++ 0xef, 0x4c, 0x64, 0x0a, 0xf8, 0x9a, 0x85, 0x7e, 0xf3, 0xe2, 0x79, 0x87, ++ 0xc5, 0x74, 0xae, 0x03, 0xe9, 0xb7, 0x87, 0x53, 0x17, 0xd2, 0x39, 0xe4, ++ 0x2e, 0xfb, 0x32, 0xda, 0x9f, 0xde, 0x92, 0x36, 0x85, 0xf6, 0x2f, 0xdd, ++ 0x88, 0x78, 0xac, 0x53, 0x9f, 0xa2, 0x3b, 0x97, 0x01, 0x9e, 0xbb, 0x82, ++ 0xc6, 0xf3, 0x18, 0xb2, 0xe7, 0x18, 0xdb, 0xde, 0x90, 0xb1, 0x6d, 0x65, ++ 0x27, 0xa9, 0x3e, 0x4a, 0x89, 0x06, 0x3d, 0x97, 0xb2, 0x62, 0xe7, 0x4e, ++ 0x9a, 0x85, 0xbe, 0xb8, 0x35, 0x99, 0xc3, 0x75, 0x6b, 0x32, 0x8f, 0xd7, ++ 0x56, 0xe7, 0x1b, 0xbf, 0x13, 0x0d, 0xca, 0xdf, 0x7f, 0xc9, 0xe4, 0xe7, ++ 0x36, 0xf4, 0xb8, 0xad, 0x56, 0xac, 0xb7, 0xc0, 0xf8, 0x3f, 0x9f, 0xc7, ++ 0xff, 0x7f, 0x04, 0x4a, 0x43, 0x5c, 0xc8, 0x7f, 0x1f, 0xa6, 0x6c, 0x7c, ++ 0x60, 0xc8, 0xa3, 0xa3, 0xf0, 0x77, 0x4f, 0x54, 0xff, 0x2a, 0xa0, 0x53, ++ 0x6b, 0xaa, 0x6f, 0xa5, 0x86, 0xfe, 0xdb, 0xed, 0xe2, 0x77, 0xc2, 0xb4, ++ 0x0e, 0xaa, 0x63, 0xd8, 0x76, 0x67, 0x06, 0xd5, 0x89, 0xb6, 0xda, 0x1c, ++ 0x95, 0x98, 0xf7, 0x0c, 0xe7, 0xf3, 0x7c, 0x4f, 0xa3, 0xa8, 0xf7, 0x07, ++ 0x8a, 0xd4, 0xee, 0x82, 0xf7, 0xb6, 0xcd, 0xcc, 0xa5, 0x7e, 0xce, 0xaa, ++ 0x5e, 0xca, 0x97, 0xf6, 0xae, 0x66, 0xe4, 0x1f, 0xf5, 0xe3, 0xd3, 0x2f, ++ 0x80, 0xff, 0x01, 0xdf, 0x4f, 0x62, 0x1b, 0xcf, 0x93, 0x98, 0xef, 0xef, ++ 0xc2, 0xef, 0x88, 0xbd, 0x01, 0x95, 0xea, 0x74, 0xe5, 0xf3, 0x1d, 0xf8, ++ 0x1c, 0xe0, 0x54, 0x04, 0x5f, 0xe0, 0xfd, 0xf1, 0x15, 0xb1, 0xdf, 0x71, ++ 0x2a, 0x3e, 0x50, 0x76, 0x08, 0xcf, 0xc3, 0x64, 0x21, 0xc5, 0xcf, 0xd3, ++ 0x8f, 0x3e, 0xe2, 0xf7, 0x59, 0xc2, 0x2f, 0x6f, 0x3c, 0x50, 0x79, 0xf3, ++ 0x68, 0x80, 0xab, 0xb8, 0x6b, 0x24, 0xb1, 0xf1, 0xe0, 0x03, 0x62, 0xbf, ++ 0xc5, 0x99, 0x24, 0xf6, 0x8d, 0xf9, 0xf9, 0xbd, 0xf1, 0xfd, 0x07, 0x63, ++ 0x7f, 0x68, 0xa7, 0x1c, 0xf3, 0xfd, 0x6b, 0x1d, 0x3e, 0x32, 0x41, 0x9c, ++ 0x8d, 0xef, 0x4d, 0x48, 0xa1, 0x75, 0x1f, 0x17, 0xf9, 0x26, 0x26, 0xf4, ++ 0xc3, 0x98, 0x38, 0xf9, 0xbb, 0x2e, 0x26, 0x0f, 0xf4, 0xbc, 0x4c, 0xb4, ++ 0x1b, 0x45, 0x7d, 0x1d, 0x9e, 0x61, 0x11, 0xa8, 0xe0, 0xe9, 0x0c, 0xea, ++ 0xe7, 0xe4, 0xf2, 0xe1, 0x67, 0xf2, 0x8f, 0xcb, 0xed, 0xb5, 0x2c, 0xf6, ++ 0x87, 0xe3, 0x54, 0xc5, 0xc6, 0x25, 0x3d, 0x35, 0x31, 0xf6, 0x38, 0x26, ++ 0x87, 0xb0, 0xc4, 0x72, 0xab, 0xbf, 0xb9, 0x0e, 0xfa, 0x1d, 0x99, 0xc1, ++ 0xf7, 0xd7, 0xc7, 0x68, 0xd1, 0x83, 0x28, 0xef, 0xd7, 0x89, 0x6b, 0x99, ++ 0xb8, 0xb2, 0xb9, 0xed, 0x84, 0xdf, 0x35, 0x2b, 0x03, 0x2a, 0xa3, 0x12, ++ 0x88, 0x90, 0xba, 0x1e, 0xda, 0x63, 0xad, 0x5d, 0x59, 0xc8, 0xdf, 0xe3, ++ 0xac, 0xdd, 0x2b, 0x5d, 0x30, 0xce, 0x35, 0x73, 0xee, 0xf6, 0x60, 0xbb, ++ 0xa4, 0xa0, 0x98, 0xf8, 0x0d, 0xfc, 0x2f, 0x3a, 0x77, 0x28, 0xc3, 0x6e, ++ 0x8a, 0xf0, 0xef, 0x28, 0xcb, 0xfc, 0x28, 0x47, 0xb3, 0xe7, 0xf0, 0x7c, ++ 0xec, 0xac, 0x39, 0x56, 0xaa, 0x3b, 0x9e, 0xa5, 0xf1, 0xf3, 0xa1, 0x98, ++ 0x16, 0x2a, 0xbc, 0x0d, 0x9e, 0xdf, 0x56, 0xcd, 0xf3, 0xc0, 0xd8, 0xae, ++ 0xd6, 0xe5, 0x59, 0xe4, 0xbe, 0xc7, 0x71, 0x88, 0x53, 0x76, 0x27, 0x88, ++ 0x37, 0x4b, 0x0a, 0xb8, 0x5d, 0x94, 0xef, 0x37, 0x8a, 0xfa, 0x1f, 0xf9, ++ 0xbc, 0x08, 0x0f, 0x8a, 0xc6, 0x3c, 0x59, 0xc1, 0xe4, 0x8f, 0xf2, 0xc9, ++ 0x9e, 0xf0, 0xfd, 0xdd, 0x33, 0x52, 0xcf, 0x0c, 0x65, 0x43, 0xe3, 0x7e, ++ 0x6f, 0xe6, 0x7c, 0x3e, 0xee, 0x5f, 0x56, 0xbe, 0x31, 0x90, 0x9e, 0x30, ++ 0x3e, 0x17, 0x7a, 0x62, 0x56, 0xe0, 0x11, 0x33, 0xf9, 0xe9, 0x42, 0x5f, ++ 0x48, 0xbd, 0x1c, 0x14, 0x75, 0x4d, 0x5d, 0xe2, 0x5c, 0x97, 0x77, 0x27, ++ 0x70, 0xbc, 0xbf, 0x5d, 0xb9, 0x98, 0xf4, 0xc5, 0xad, 0xac, 0x89, 0xf4, ++ 0xf9, 0x6d, 0x2c, 0x6c, 0x46, 0x7c, 0xf7, 0xe9, 0xff, 0x29, 0x3a, 0xbf, ++ 0x06, 0xe6, 0x99, 0x15, 0x34, 0xfa, 0x39, 0xb3, 0xe7, 0xc4, 0xfb, 0x3d, ++ 0x9c, 0x5f, 0xe5, 0xbc, 0xb7, 0x87, 0x8c, 0xcf, 0x67, 0x4a, 0xff, 0x75, ++ 0x8a, 0xd1, 0x7f, 0xad, 0xfe, 0xce, 0x17, 0x19, 0x64, 0x17, 0xb3, 0x9f, ++ 0xae, 0xbf, 0x34, 0x28, 0x56, 0xbf, 0xd4, 0x18, 0x57, 0xbf, 0xd4, 0x20, ++ 0xea, 0x97, 0x1a, 0xf7, 0x2d, 0x39, 0xe2, 0xd2, 0xd5, 0x2f, 0x35, 0x1e, ++ 0xe0, 0xf5, 0x4b, 0x0d, 0xfb, 0x2e, 0x57, 0xbf, 0xd4, 0x4b, 0xfb, 0x48, ++ 0xc7, 0xcd, 0x91, 0x83, 0xb8, 0xbf, 0x72, 0x7c, 0x31, 0x88, 0x04, 0xc0, ++ 0x79, 0x48, 0xd4, 0xbb, 0x1c, 0xc6, 0x7a, 0x97, 0xf2, 0x18, 0x5f, 0xa6, ++ 0xce, 0xe4, 0x79, 0x56, 0x60, 0x5f, 0xda, 0x2f, 0xc9, 0x73, 0xa4, 0xf8, ++ 0xd1, 0x5f, 0x6f, 0x33, 0x95, 0x53, 0x5e, 0xb6, 0x2d, 0x2d, 0xd5, 0xaf, ++ 0xcf, 0x83, 0xae, 0x59, 0x19, 0x9a, 0xa4, 0xcf, 0xc7, 0xca, 0x7a, 0xa5, ++ 0xe3, 0x03, 0xc4, 0xb7, 0xc3, 0x0b, 0xb8, 0xff, 0xba, 0x51, 0xe1, 0x79, ++ 0xf1, 0xf0, 0xed, 0x56, 0x8a, 0xe7, 0x5c, 0xc5, 0x41, 0xc3, 0x3e, 0x84, ++ 0x4b, 0x65, 0x27, 0x30, 0xbf, 0xf8, 0x11, 0xfa, 0x59, 0xa3, 0xa9, 0x3f, ++ 0xe5, 0x3d, 0x70, 0x1f, 0x6f, 0x24, 0x5c, 0x23, 0x0a, 0xaf, 0xb3, 0xef, ++ 0x7b, 0x1f, 0xbf, 0x3b, 0xc2, 0x7c, 0x64, 0x9c, 0x3e, 0x72, 0x65, 0xf9, ++ 0x69, 0x1f, 0xc0, 0x95, 0x7e, 0x35, 0xe5, 0xf3, 0xe7, 0x1c, 0x28, 0xdb, ++ 0x41, 0xfa, 0xc6, 0x6e, 0xf3, 0xe3, 0xef, 0x22, 0xca, 0xf1, 0xe7, 0x84, ++ 0xb6, 0x69, 0x58, 0x47, 0xd4, 0x78, 0x60, 0x9b, 0x36, 0xdf, 0x1e, 0xe3, ++ 0xbb, 0xca, 0x02, 0xc1, 0xaf, 0x29, 0x2c, 0x05, 0xf9, 0xb5, 0x2f, 0xbf, ++ 0xb7, 0x27, 0x89, 0xf2, 0x7b, 0x1f, 0xd9, 0x83, 0x93, 0x0a, 0xe0, 0xfd, ++ 0x3a, 0x4b, 0x74, 0x38, 0x33, 0xf2, 0x33, 0xdd, 0x1f, 0xc8, 0xae, 0x2d, ++ 0x12, 0xfc, 0x62, 0x9e, 0x10, 0xbc, 0x7d, 0x01, 0xc0, 0x73, 0xfe, 0x4d, ++ 0x0b, 0xcf, 0x73, 0xdd, 0xc7, 0x48, 0x5e, 0x9f, 0xdf, 0x9f, 0x41, 0xf9, ++ 0x49, 0x6d, 0x26, 0x23, 0xfb, 0xd2, 0x52, 0xc9, 0xf8, 0xef, 0xc0, 0x6c, ++ 0xe3, 0xdf, 0x0b, 0x9c, 0xce, 0xe0, 0xe7, 0x18, 0xb5, 0xcc, 0x60, 0x64, ++ 0x07, 0x7b, 0x32, 0x27, 0x13, 0xfd, 0x16, 0xb3, 0xc8, 0x51, 0x3c, 0xa7, ++ 0xa8, 0x66, 0xab, 0xd9, 0x70, 0x1e, 0xd1, 0x3d, 0x3b, 0x8c, 0xed, 0x3a, ++ 0xd6, 0x41, 0xf6, 0xa6, 0x6e, 0x57, 0x3f, 0x7e, 0x26, 0xbd, 0x25, 0xf5, ++ 0x63, 0x3d, 0xf3, 0xa9, 0x66, 0xdc, 0x07, 0xe8, 0x34, 0xbe, 0xcf, 0x06, ++ 0x1b, 0xf5, 0x63, 0x99, 0xb0, 0x07, 0x23, 0x67, 0x4d, 0x6c, 0xc6, 0x7a, ++ 0x8d, 0x91, 0xa6, 0xa0, 0x4a, 0xf6, 0xf7, 0x3e, 0x7f, 0xee, 0x4c, 0x8a, ++ 0x9f, 0xab, 0xb9, 0x1d, 0x65, 0x4f, 0xd3, 0xf9, 0x57, 0xe7, 0x53, 0x3f, ++ 0x51, 0xb9, 0x9c, 0x73, 0x7d, 0x3c, 0x3a, 0xa6, 0x35, 0x0d, 0x76, 0x69, ++ 0xb4, 0xf0, 0xaf, 0x6e, 0xd0, 0xf8, 0xef, 0x2a, 0x48, 0x7f, 0x69, 0xb4, ++ 0xf8, 0x9d, 0x85, 0xc3, 0xa6, 0x03, 0x2a, 0xfd, 0x76, 0x8f, 0x80, 0x67, ++ 0x94, 0x78, 0x4f, 0xfa, 0x69, 0x52, 0x5f, 0xf7, 0xd1, 0x73, 0x2c, 0xe8, ++ 0x52, 0xe0, 0xfb, 0x07, 0x25, 0x5d, 0x8b, 0x58, 0x11, 0xd2, 0x15, 0xc6, ++ 0x27, 0x79, 0x50, 0x30, 0xc0, 0xc9, 0xa4, 0xf1, 0xe9, 0xf7, 0x1a, 0xae, ++ 0x13, 0xf3, 0x01, 0xdd, 0xf9, 0xf9, 0x77, 0x26, 0x6b, 0x04, 0xf9, 0xa8, ++ 0x55, 0x69, 0x22, 0x3d, 0x6d, 0x65, 0x42, 0x5f, 0x2b, 0xa1, 0x66, 0x7c, ++ 0xf9, 0x17, 0xe1, 0x30, 0xe9, 0xed, 0x6b, 0x58, 0xd3, 0x2d, 0xf8, 0x7b, ++ 0x9f, 0xe3, 0xac, 0x5d, 0x29, 0xe4, 0x97, 0xda, 0x43, 0x6b, 0x0b, 0x5c, ++ 0x31, 0x3e, 0x69, 0x66, 0xd1, 0x82, 0xdd, 0x8a, 0x81, 0x5f, 0xe8, 0xf9, ++ 0xd9, 0x8c, 0x37, 0x12, 0xf2, 0x8b, 0xb4, 0x2b, 0xd1, 0x77, 0xb9, 0xbf, ++ 0x31, 0x8d, 0x81, 0x1f, 0x08, 0xf3, 0x06, 0x7e, 0xcf, 0xfd, 0xa0, 0xc3, ++ 0x0a, 0x8f, 0xf3, 0xc0, 0x1f, 0x3c, 0x8c, 0x71, 0xde, 0x1b, 0xa6, 0xa9, ++ 0xc4, 0x0f, 0x53, 0x61, 0x19, 0xd8, 0x6f, 0x92, 0xc3, 0x48, 0xe7, 0x1b, ++ 0x3d, 0xc6, 0xf6, 0x54, 0x5f, 0x3f, 0x3e, 0x50, 0xf5, 0xbf, 0x5f, 0x01, ++ 0x12, 0xa7, 0x21, 0x3c, 0xd3, 0x86, 0x1a, 0xfb, 0x05, 0xa4, 0x7e, 0x63, ++ 0x46, 0xfd, 0x56, 0xc8, 0xbe, 0xe0, 0x75, 0xe5, 0xab, 0x8f, 0x7e, 0x0b, ++ 0xe3, 0xff, 0x94, 0xe5, 0x6c, 0x28, 0xfa, 0x31, 0xe0, 0x39, 0xfa, 0x13, ++ 0xfd, 0x1e, 0xe9, 0x73, 0x05, 0x03, 0xee, 0x93, 0x3c, 0x57, 0x90, 0x60, ++ 0x9f, 0xe4, 0xbc, 0xc8, 0xf7, 0x5e, 0xcb, 0xba, 0x17, 0xee, 0x52, 0xfa, ++ 0xf3, 0x4d, 0xcf, 0x91, 0xe5, 0xaa, 0x47, 0xc7, 0x5f, 0x92, 0x9f, 0x5f, ++ 0x14, 0x75, 0x15, 0xca, 0x2f, 0xc5, 0x7e, 0xec, 0x28, 0x9e, 0xf7, 0x8b, ++ 0xd9, 0x79, 0xce, 0x37, 0x15, 0xa2, 0x75, 0x2d, 0xf2, 0x5d, 0x26, 0x7e, ++ 0x7f, 0x22, 0xf8, 0x45, 0xfc, 0xbe, 0xc8, 0xf5, 0xfb, 0x6c, 0x51, 0xfc, ++ 0xfd, 0x9c, 0x32, 0x31, 0xce, 0xb5, 0xc8, 0x3f, 0xe5, 0x31, 0xbb, 0x1e, ++ 0x35, 0xd9, 0x7d, 0x96, 0x22, 0xe4, 0x13, 0x7f, 0x9b, 0xaa, 0xf6, 0xf7, ++ 0xe7, 0xdd, 0x99, 0x3e, 0xe2, 0x97, 0x91, 0x26, 0x69, 0xe7, 0xfd, 0x59, ++ 0x8c, 0xec, 0x7c, 0x47, 0xb3, 0x86, 0xf0, 0xef, 0x1f, 0x93, 0x1b, 0xb2, ++ 0x1b, 0xf8, 0xe3, 0x1d, 0xae, 0x4f, 0x80, 0x3f, 0x28, 0x2f, 0xd5, 0xcf, ++ 0x3e, 0x1a, 0x9f, 0xc7, 0xf1, 0x8f, 0xa4, 0xe3, 0x31, 0xe1, 0x47, 0xdf, ++ 0xc8, 0x7c, 0x14, 0x47, 0x4c, 0x11, 0x7e, 0x74, 0xb4, 0x90, 0xf3, 0x4f, ++ 0x95, 0xfd, 0x56, 0x0d, 0xdf, 0x7f, 0xad, 0x88, 0xe7, 0x09, 0x26, 0xe2, ++ 0x06, 0x22, 0x7d, 0xef, 0x69, 0xb4, 0x8b, 0x55, 0x56, 0x23, 0x1f, 0xc4, ++ 0xf3, 0x17, 0xcc, 0x68, 0xd2, 0xcf, 0x1b, 0xcf, 0x6f, 0x03, 0xf1, 0xcd, ++ 0x20, 0xe4, 0x1b, 0x69, 0x17, 0xb3, 0x2e, 0xcf, 0x37, 0x9f, 0x0b, 0x3f, ++ 0x23, 0x01, 0xdf, 0x7c, 0x5e, 0x30, 0x7a, 0x60, 0xbe, 0x89, 0xe7, 0x17, ++ 0xa9, 0x57, 0x76, 0xdb, 0x1c, 0x55, 0x78, 0xa6, 0x70, 0x63, 0x8d, 0x42, ++ 0xfa, 0x78, 0xe4, 0x9b, 0x83, 0x9b, 0xb1, 0x7d, 0x45, 0x7d, 0x21, 0xd5, ++ 0xbd, 0xec, 0xce, 0xf0, 0x1f, 0xa2, 0xe7, 0x4d, 0xfc, 0xf9, 0xa8, 0xae, ++ 0x80, 0x8a, 0x75, 0x31, 0xc5, 0xcb, 0xc4, 0xf3, 0xc2, 0x60, 0x15, 0xb6, ++ 0x1b, 0x97, 0xf3, 0x7d, 0x89, 0xd1, 0xc7, 0x79, 0xdd, 0xcc, 0xe0, 0xfb, ++ 0xf8, 0xf3, 0xb2, 0x55, 0x4d, 0x87, 0xf0, 0xbb, 0xb8, 0xc6, 0x30, 0x7f, ++ 0xff, 0xc5, 0x4f, 0x5b, 0xe9, 0x7b, 0xa1, 0x48, 0xab, 0x78, 0xbf, 0xb2, ++ 0xbd, 0x0a, 0xdb, 0x8d, 0x6d, 0xfc, 0xfd, 0xd3, 0xb8, 0xbf, 0x34, 0x02, ++ 0xeb, 0xdd, 0x22, 0xcd, 0x78, 0x7f, 0xd8, 0xba, 0x42, 0x3f, 0x0f, 0x4b, ++ 0xb9, 0x5f, 0x3b, 0x5e, 0xf0, 0xe9, 0x6e, 0x65, 0xcf, 0x21, 0x7a, 0xaf, ++ 0x9d, 0xbf, 0xb7, 0xe8, 0xa8, 0x35, 0x99, 0x7e, 0x67, 0x50, 0xf8, 0xad, ++ 0x37, 0x88, 0x75, 0x8e, 0xdf, 0xca, 0xd7, 0xe9, 0xfc, 0xe0, 0x26, 0xfa, ++ 0xdd, 0xd1, 0x05, 0xbd, 0x61, 0xf2, 0x9f, 0x3e, 0x36, 0xd5, 0x55, 0x90, ++ 0xde, 0x19, 0x20, 0xfe, 0xac, 0x54, 0xda, 0xf3, 0xf0, 0x7a, 0x23, 0xea, ++ 0x13, 0x15, 0xe9, 0x07, 0x7c, 0x5d, 0xc4, 0xf7, 0x1f, 0xb7, 0xc3, 0x14, ++ 0x65, 0x83, 0x78, 0xfe, 0x42, 0xee, 0xdb, 0x61, 0x1d, 0x81, 0xbe, 0x6e, ++ 0xa0, 0x6c, 0x10, 0xb7, 0xfb, 0xb2, 0x9f, 0x3b, 0x93, 0x7f, 0xd7, 0xc5, ++ 0x1e, 0x4b, 0xa5, 0xbc, 0xaf, 0xdc, 0x57, 0x8c, 0x6e, 0x62, 0x0a, 0xca, ++ 0x19, 0xae, 0x51, 0xf8, 0x01, 0x09, 0xf7, 0x19, 0x6f, 0x2c, 0x6e, 0xa2, ++ 0xfd, 0xc5, 0x1b, 0x07, 0xc9, 0xfd, 0xc5, 0x6e, 0x0d, 0xcf, 0x75, 0x2f, ++ 0xbb, 0xf4, 0xe7, 0xc9, 0x89, 0xf2, 0x2b, 0x63, 0xc5, 0xbc, 0x9f, 0x88, ++ 0xba, 0x08, 0x79, 0xbf, 0x26, 0x52, 0x48, 0xbf, 0x23, 0xb6, 0x1b, 0x99, ++ 0x84, 0xbe, 0xc7, 0x7e, 0xf2, 0x37, 0xd4, 0x16, 0xe7, 0x94, 0x33, 0xf1, ++ 0x1d, 0xd8, 0xee, 0x42, 0xde, 0x9e, 0x3c, 0xe8, 0x89, 0x1f, 0xb6, 0xe5, ++ 0x01, 0x7e, 0x4d, 0x4d, 0x1a, 0x9e, 0xeb, 0xc6, 0x0a, 0x14, 0xfa, 0x0e, ++ 0xee, 0x5f, 0xba, 0x58, 0x34, 0x3d, 0xad, 0x3f, 0xfc, 0x37, 0x6a, 0x2c, ++ 0x6a, 0xe1, 0xdf, 0xb1, 0x11, 0xfc, 0x0b, 0x9b, 0x2d, 0xdb, 0xf9, 0xf7, ++ 0x88, 0x5c, 0x2f, 0xcd, 0x92, 0x6a, 0x67, 0xdc, 0x10, 0x92, 0xd3, 0x5b, ++ 0x05, 0x9d, 0x6e, 0x19, 0x24, 0xf2, 0x92, 0x23, 0xd9, 0x48, 0xd4, 0x37, ++ 0xb3, 0x04, 0xdd, 0x6e, 0xb3, 0x82, 0xdf, 0x4a, 0x7a, 0xad, 0xdd, 0x1c, ++ 0x27, 0xff, 0xb3, 0x07, 0xa1, 0xfd, 0xd8, 0x32, 0xa0, 0xff, 0x6c, 0x7c, ++ 0x1e, 0xa7, 0x1f, 0x6a, 0xc4, 0xbc, 0x0b, 0x85, 0xdf, 0xbc, 0x18, 0x7f, ++ 0xaf, 0x54, 0xc5, 0xf3, 0xe6, 0xb9, 0xff, 0xfc, 0xc9, 0x16, 0xee, 0x37, ++ 0xdf, 0xc3, 0x3a, 0x28, 0x8f, 0x78, 0xfe, 0x31, 0xee, 0x2f, 0xd6, 0xc3, ++ 0xf2, 0x90, 0x5f, 0xfa, 0xfd, 0xae, 0xd7, 0x4e, 0x63, 0xbb, 0xbe, 0x23, ++ 0xfe, 0x77, 0x64, 0xf9, 0xef, 0x10, 0xf6, 0xfb, 0x9d, 0xd6, 0x52, 0x9e, ++ 0x9f, 0x3d, 0xbf, 0xa5, 0xbe, 0x02, 0xf3, 0x73, 0x35, 0x9b, 0xdf, 0xa4, ++ 0x3c, 0x70, 0x8d, 0xd4, 0x17, 0x11, 0xa3, 0xbe, 0x00, 0x07, 0x83, 0xeb, ++ 0x8b, 0x4d, 0x57, 0x52, 0x5e, 0xc7, 0x64, 0xe5, 0xbf, 0xa3, 0x39, 0x12, ++ 0xf4, 0x05, 0xd6, 0x97, 0x8c, 0xc4, 0xba, 0x51, 0x18, 0x7f, 0xb8, 0x38, ++ 0x87, 0x67, 0x35, 0xbe, 0xc2, 0xcf, 0xdf, 0xf9, 0xee, 0x20, 0xb2, 0x37, ++ 0x53, 0xa8, 0xae, 0x94, 0xc6, 0x53, 0x69, 0x3f, 0xf7, 0xcd, 0x80, 0x2f, ++ 0x46, 0x1f, 0x69, 0x37, 0xe2, 0xf5, 0x45, 0x99, 0xcc, 0xd7, 0x0c, 0xce, ++ 0xa4, 0x7c, 0x96, 0xd4, 0x1f, 0x65, 0x8c, 0xdb, 0x8b, 0x78, 0xff, 0xe8, ++ 0x11, 0x49, 0x4f, 0x11, 0xf7, 0x48, 0x3f, 0xa3, 0x0c, 0xfd, 0x0c, 0xe0, ++ 0x8f, 0x2e, 0x93, 0x3d, 0x62, 0x32, 0xe9, 0xfd, 0x8a, 0x08, 0xc9, 0x21, ++ 0xc4, 0x8d, 0xd3, 0x6c, 0x45, 0xc8, 0x3a, 0xdc, 0x9f, 0x1a, 0x79, 0xfb, ++ 0x28, 0xab, 0xa0, 0x3f, 0x8b, 0xa3, 0xef, 0x26, 0xa2, 0xef, 0xc0, 0xf1, ++ 0x93, 0xf1, 0x79, 0x1c, 0xfd, 0x65, 0xfc, 0x52, 0x21, 0xe8, 0x7f, 0x3b, ++ 0x0b, 0x50, 0x5c, 0xb4, 0x57, 0xd0, 0xff, 0xed, 0x77, 0xf9, 0xef, 0xbd, ++ 0xcd, 0xb2, 0x2f, 0x23, 0xfe, 0x7b, 0xf7, 0xf7, 0xdc, 0xdf, 0x94, 0xf1, ++ 0xd3, 0xd7, 0x8f, 0x9b, 0x02, 0xea, 0x3f, 0x12, 0x37, 0xf5, 0xd1, 0xdb, ++ 0x06, 0x7e, 0x64, 0x0a, 0xfe, 0x1e, 0xc6, 0xd4, 0x21, 0x8f, 0xe2, 0x7e, ++ 0x78, 0xa7, 0x8d, 0xff, 0xae, 0xb5, 0xc2, 0xe9, 0xeb, 0xbe, 0xfd, 0x78, ++ 0x81, 0x3e, 0xaf, 0xf8, 0x36, 0xfe, 0x7e, 0x8b, 0xee, 0x77, 0x25, 0x9a, ++ 0xa7, 0x26, 0x59, 0x71, 0x1f, 0xb0, 0xd9, 0xcc, 0xe3, 0x8a, 0x99, 0xd3, ++ 0xde, 0xab, 0x98, 0xab, 0xd3, 0x1b, 0x85, 0x59, 0x95, 0x2f, 0x0d, 0x1a, ++ 0x8d, 0xf4, 0xe8, 0xfa, 0xf6, 0x1f, 0x30, 0xce, 0x78, 0x5d, 0x9c, 0xe3, ++ 0x7a, 0xc0, 0x45, 0xf4, 0xbe, 0xd0, 0xc5, 0xef, 0x5f, 0xd8, 0x7a, 0x95, ++ 0x3f, 0x0c, 0xb7, 0xcf, 0x98, 0xc5, 0x79, 0x46, 0x4a, 0xd3, 0x42, 0x2c, ++ 0x81, 0x92, 0x70, 0x2c, 0x14, 0xbf, 0xf7, 0xf2, 0x59, 0xca, 0x2b, 0xb4, ++ 0x7f, 0x3c, 0x23, 0x23, 0x74, 0x0c, 0xe9, 0x70, 0xcf, 0x1b, 0x7b, 0x29, ++ 0x5f, 0x59, 0xc7, 0xba, 0xf8, 0xef, 0x02, 0x8b, 0x71, 0x07, 0xce, 0x4b, ++ 0x86, 0x49, 0x7f, 0x59, 0x5e, 0xe5, 0xf6, 0xb0, 0x57, 0x49, 0xf6, 0xf3, ++ 0xef, 0x86, 0xc3, 0x25, 0xfa, 0xfd, 0xa4, 0x63, 0x3e, 0xae, 0x67, 0xc7, ++ 0xe5, 0x07, 0x8f, 0xe3, 0x3c, 0xd2, 0xde, 0xc5, 0xd7, 0x15, 0x9c, 0x5c, ++ 0x72, 0x23, 0x7d, 0xd7, 0xf9, 0x17, 0x16, 0x48, 0xc7, 0xfd, 0x4c, 0x45, ++ 0xe3, 0xbf, 0xdf, 0x1c, 0x3f, 0x2f, 0xd6, 0x11, 0xb4, 0xe8, 0xf2, 0xd9, ++ 0x27, 0x6d, 0x89, 0xbf, 0x33, 0x3d, 0x35, 0x88, 0xe7, 0x03, 0x8a, 0x10, ++ 0x47, 0x58, 0x07, 0x91, 0x1b, 0xf8, 0x00, 0xf1, 0xf7, 0x89, 0x88, 0x03, ++ 0x3f, 0x11, 0xfb, 0x5a, 0x9f, 0xa4, 0xf1, 0x7d, 0xae, 0x9e, 0xbe, 0xfe, ++ 0xfc, 0xaa, 0xf9, 0x84, 0x7e, 0x16, 0xfb, 0x60, 0x9f, 0x64, 0x1a, 0xe3, ++ 0x47, 0xd9, 0xcf, 0x22, 0xae, 0x1f, 0xae, 0xb0, 0x06, 0x5b, 0x74, 0xf4, ++ 0xf4, 0x6d, 0x4a, 0x6a, 0x8a, 0x50, 0x1d, 0x95, 0xa8, 0x1b, 0x59, 0xc6, ++ 0x78, 0xbc, 0xb4, 0x3f, 0xc3, 0x70, 0x0e, 0x41, 0x86, 0xaf, 0xb2, 0xc8, ++ 0x87, 0xfb, 0x14, 0xc5, 0x01, 0x0b, 0xfe, 0xbe, 0x77, 0xef, 0x7e, 0x6e, ++ 0x87, 0x71, 0xff, 0x19, 0xf7, 0x87, 0x23, 0x39, 0xa1, 0x2f, 0x10, 0xee, ++ 0x06, 0x1f, 0x0b, 0xe0, 0xfe, 0x2a, 0xf3, 0x75, 0x5b, 0x6e, 0xc1, 0x7d, ++ 0x46, 0xf1, 0x7d, 0xeb, 0x79, 0xc1, 0x2f, 0xe7, 0x6d, 0xfc, 0x2a, 0xe1, ++ 0xfa, 0x6f, 0xc3, 0xaf, 0xb7, 0x2e, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xd5, 0x7d, ++ 0x09, 0x78, 0x54, 0xd5, 0xd9, 0xf0, 0xb9, 0x73, 0x27, 0x33, 0x13, 0x32, ++ 0x13, 0x26, 0x1b, 0x84, 0x2d, 0x4e, 0x16, 0xb2, 0x90, 0x6d, 0xb2, 0x61, ++ 0xd8, 0x27, 0x09, 0x20, 0xb8, 0x60, 0xc2, 0x52, 0x51, 0xb6, 0x61, 0xdf, ++ 0xb2, 0x09, 0xd8, 0x8f, 0xb6, 0xf6, 0xcf, 0x60, 0x10, 0x90, 0x47, 0x5b, ++ 0xa8, 0xb6, 0xc5, 0xcf, 0xe5, 0x19, 0x10, 0xa8, 0x56, 0x2c, 0x11, 0x83, ++ 0x46, 0x0d, 0x1a, 0x94, 0x22, 0x58, 0x5b, 0x47, 0x04, 0x45, 0x4b, 0x75, ++ 0xa4, 0xca, 0x22, 0x21, 0x89, 0x60, 0x2d, 0xf6, 0xa3, 0xe5, 0x7f, 0xdf, ++ 0xf7, 0x9c, 0x93, 0x99, 0x7b, 0x33, 0x61, 0xfb, 0xd5, 0xe7, 0xff, 0xc8, ++ 0xf3, 0x70, 0x72, 0xee, 0x3d, 0xf7, 0x2c, 0xef, 0x79, 0xf7, 0xf3, 0xbe, ++ 0x27, 0x51, 0x8e, 0x8a, 0x24, 0x47, 0x1c, 0x63, 0xed, 0x77, 0xfb, 0x4d, ++ 0x4c, 0x65, 0x2c, 0x4a, 0xd6, 0x2b, 0xa0, 0x9e, 0x8c, 0xf5, 0xf2, 0x24, ++ 0x47, 0x11, 0xd4, 0xa7, 0xc8, 0xf7, 0xa2, 0xfe, 0x10, 0xaf, 0xc3, 0x3f, ++ 0x03, 0xeb, 0xc5, 0xd8, 0x1c, 0xfc, 0xcd, 0x01, 0xa5, 0xc5, 0xda, 0xa2, ++ 0xe6, 0xc0, 0xef, 0xeb, 0xc2, 0x5a, 0xfd, 0xe9, 0xf4, 0x9e, 0x5d, 0x4a, ++ 0x62, 0x4c, 0x51, 0x99, 0x87, 0x45, 0x43, 0x25, 0x9d, 0x39, 0xca, 0x6d, ++ 0xf8, 0x74, 0xb8, 0xfd, 0x44, 0x26, 0x14, 0xe1, 0xf0, 0x1e, 0xfa, 0xa9, ++ 0x31, 0x59, 0xd7, 0x29, 0xb9, 0xd4, 0xbc, 0xdc, 0x02, 0xfd, 0xcd, 0x10, ++ 0xfd, 0xb1, 0xfe, 0x36, 0x23, 0xf6, 0x3f, 0x9d, 0x77, 0xc5, 0x66, 0x34, ++ 0x1f, 0xfc, 0x56, 0x89, 0x64, 0x6c, 0xa6, 0x85, 0xad, 0xe9, 0x07, 0xef, ++ 0x67, 0x35, 0xf7, 0x36, 0xc1, 0x0c, 0xd8, 0xa2, 0x48, 0x4f, 0xaa, 0x3d, ++ 0x0b, 0x5b, 0x8c, 0xb6, 0x9f, 0x80, 0x71, 0x15, 0x4f, 0x84, 0x7a, 0x29, ++ 0x02, 0xfa, 0xc6, 0x7f, 0xa3, 0xba, 0x96, 0x8c, 0x19, 0xd9, 0x09, 0x39, ++ 0x3f, 0x5a, 0x87, 0x87, 0x31, 0x5c, 0xf7, 0x00, 0x1f, 0xad, 0x6b, 0x7d, ++ 0x49, 0x47, 0xc2, 0x7f, 0x17, 0x32, 0xd6, 0xb1, 0xc7, 0x6c, 0xdf, 0x02, ++ 0xe3, 0x54, 0x35, 0xbf, 0x75, 0x54, 0x81, 0x75, 0x55, 0xc9, 0xf5, 0x35, ++ 0x6a, 0xd7, 0x97, 0xeb, 0x50, 0xe8, 0x7b, 0xc6, 0x2c, 0xde, 0xcf, 0x2d, ++ 0x8c, 0xdd, 0xce, 0x14, 0xd6, 0x13, 0xfa, 0x69, 0xb2, 0xba, 0x73, 0x11, ++ 0x5e, 0x55, 0x16, 0x3f, 0xcd, 0x13, 0x7a, 0x34, 0x95, 0x67, 0xc3, 0x68, ++ 0x6b, 0x87, 0x47, 0xd1, 0xfa, 0x7b, 0xc3, 0xf7, 0x30, 0x9f, 0x17, 0xeb, ++ 0x5c, 0xec, 0xef, 0x61, 0x01, 0x78, 0x2e, 0xb3, 0xf3, 0xf5, 0x8f, 0x51, ++ 0x2b, 0xcb, 0x4c, 0xb1, 0x8c, 0x9d, 0x9b, 0xc7, 0xec, 0x66, 0x78, 0xb4, ++ 0xec, 0xe0, 0xdc, 0x7a, 0x0b, 0xd4, 0x97, 0x3d, 0xc0, 0xec, 0x7c, 0x74, ++ 0x97, 0x81, 0x0d, 0x86, 0xfe, 0x05, 0xbc, 0xba, 0x9b, 0x5f, 0x5c, 0xb9, ++ 0x81, 0x39, 0x2c, 0xa2, 0x8e, 0xc3, 0x4e, 0xed, 0xc1, 0x1c, 0xe9, 0x81, ++ 0x7a, 0x1f, 0x77, 0xb4, 0xa6, 0x0e, 0xfd, 0x32, 0x9c, 0xc7, 0x52, 0xd1, ++ 0x6f, 0xbf, 0x45, 0x7d, 0x35, 0xdf, 0x0f, 0xa8, 0x4d, 0xd2, 0xb4, 0xbf, ++ 0x61, 0xe5, 0x20, 0xcd, 0xfb, 0x44, 0x4f, 0xbe, 0xa6, 0x9e, 0xbc, 0x6e, ++ 0xa8, 0xa6, 0xfd, 0xc0, 0x0d, 0xa5, 0x9a, 0x7a, 0xda, 0xa6, 0x9b, 0x35, ++ 0xed, 0xf3, 0x58, 0x52, 0x4f, 0x06, 0xf0, 0xaf, 0x39, 0xa0, 0x32, 0x2f, ++ 0x80, 0x36, 0xc3, 0x3b, 0x51, 0xf3, 0x3e, 0xf3, 0xe9, 0xbb, 0x34, 0xdf, ++ 0x9f, 0x64, 0xb5, 0xbf, 0x19, 0x0e, 0xed, 0x1a, 0xc3, 0x23, 0x73, 0x18, ++ 0xe0, 0x51, 0x7d, 0x78, 0xe4, 0x16, 0x2c, 0x99, 0xc7, 0xe5, 0xcb, 0x02, ++ 0xf8, 0xcc, 0x13, 0xeb, 0xc8, 0x6e, 0x98, 0xa3, 0xe9, 0xe7, 0x4c, 0xe4, ++ 0xd8, 0x03, 0xb8, 0xaf, 0xf3, 0x7c, 0x0b, 0x6e, 0x65, 0x80, 0x57, 0xb9, ++ 0x4d, 0x4b, 0x34, 0xfd, 0x2e, 0x55, 0x2b, 0xf9, 0xbe, 0x6d, 0x08, 0x3b, ++ 0xee, 0x87, 0xef, 0x6a, 0xe1, 0x07, 0xe1, 0x99, 0xcf, 0x3a, 0xf6, 0xf7, ++ 0x83, 0xf9, 0x55, 0x7b, 0x15, 0x67, 0x0b, 0xbc, 0x5e, 0xb8, 0x89, 0xbf, ++ 0x97, 0xdf, 0x2d, 0x6e, 0xda, 0x4c, 0xdf, 0x2d, 0xf6, 0x6a, 0x9f, 0x2f, ++ 0x7d, 0x5a, 0x5b, 0xf7, 0x94, 0xb2, 0xf4, 0x5a, 0x2b, 0x63, 0xcb, 0x1d, ++ 0xb6, 0x58, 0xc2, 0x87, 0xbe, 0xac, 0xef, 0xa5, 0x20, 0xba, 0x0a, 0xe0, ++ 0x01, 0x34, 0x82, 0xf1, 0xce, 0x3d, 0xae, 0x7a, 0xcd, 0x89, 0x08, 0x9f, ++ 0xd4, 0xdf, 0x0e, 0x27, 0xf8, 0x84, 0x31, 0xaf, 0xa3, 0xeb, 0x7e, 0x9d, ++ 0x63, 0xcc, 0xd9, 0x82, 0xed, 0x77, 0xd8, 0x9c, 0x1e, 0xa8, 0x2f, 0x3c, ++ 0x38, 0x97, 0xe6, 0x63, 0x8e, 0xd7, 0xe2, 0x41, 0xb8, 0x43, 0x8b, 0x07, ++ 0x11, 0xe9, 0x5a, 0x3c, 0xb0, 0x39, 0xb5, 0xfb, 0xde, 0xb3, 0x58, 0xbb, ++ 0xef, 0x7a, 0xf8, 0x46, 0xb9, 0x06, 0x5d, 0x16, 0xbe, 0x31, 0xe3, 0xb4, ++ 0x78, 0x21, 0xe1, 0x5a, 0x0c, 0x3f, 0xdf, 0x25, 0x5c, 0x9f, 0xd0, 0xc1, ++ 0xb3, 0x60, 0x9f, 0xab, 0xde, 0x4a, 0x70, 0x62, 0x93, 0x2d, 0x83, 0x11, ++ 0x7e, 0x7c, 0xbe, 0x66, 0x56, 0xae, 0x22, 0x9f, 0x63, 0xb1, 0xc0, 0x67, ++ 0xe0, 0xb9, 0x93, 0x77, 0xc1, 0xce, 0xda, 0xad, 0x1e, 0x03, 0xe0, 0xcf, ++ 0x73, 0x0e, 0xc5, 0x78, 0xc2, 0x12, 0xe8, 0x27, 0xcf, 0xd8, 0xb2, 0x17, ++ 0xd7, 0xb3, 0x46, 0xf1, 0x30, 0xfc, 0x2e, 0x9c, 0x79, 0xe3, 0x91, 0x5f, ++ 0xd4, 0x17, 0xb7, 0x24, 0xb4, 0xc0, 0xbe, 0xe4, 0x5b, 0x6a, 0x71, 0xe7, ++ 0xd8, 0x17, 0xd6, 0xf2, 0xe7, 0x91, 0xee, 0x2b, 0x4d, 0x2d, 0x39, 0xf8, ++ 0x5e, 0xf6, 0xf7, 0x85, 0xd5, 0x4d, 0xcf, 0x5b, 0x95, 0x77, 0x16, 0x30, ++ 0x58, 0x2f, 0x33, 0xb6, 0xe4, 0x10, 0x3f, 0xb4, 0x30, 0x1a, 0x5f, 0xc2, ++ 0x71, 0x70, 0x0f, 0x8e, 0xc7, 0x4b, 0x59, 0x39, 0xf1, 0xe1, 0x17, 0x05, ++ 0x3e, 0x7f, 0xfe, 0xd1, 0x22, 0x82, 0xe3, 0x02, 0x56, 0xbb, 0xdf, 0x05, ++ 0xe3, 0x9d, 0xf9, 0x98, 0xc3, 0x77, 0x31, 0xf3, 0x50, 0xbb, 0xf9, 0x1b, ++ 0xb4, 0x70, 0xe8, 0x02, 0x3f, 0x1d, 0xdc, 0x00, 0x6d, 0x1c, 0x38, 0x6e, ++ 0x8d, 0x58, 0xf7, 0x12, 0xc6, 0xbc, 0x86, 0xe4, 0xae, 0xf0, 0x54, 0x9a, ++ 0x95, 0x16, 0x5b, 0x0e, 0x82, 0xa1, 0x59, 0xf2, 0x6d, 0xf7, 0xa5, 0x02, ++ 0x8e, 0x76, 0x08, 0xcf, 0xa1, 0xac, 0xf3, 0x1f, 0xf1, 0x6f, 0x09, 0x5f, ++ 0x68, 0xa0, 0x04, 0xf3, 0x27, 0x1c, 0xcf, 0xde, 0x2b, 0x30, 0x9e, 0x84, ++ 0xa7, 0xe4, 0x5b, 0x72, 0x1c, 0x33, 0xab, 0x55, 0xe3, 0x91, 0x0e, 0x74, ++ 0x7c, 0x8c, 0xa5, 0x6b, 0xf7, 0x09, 0x36, 0x8e, 0x61, 0x7d, 0xb0, 0xa8, ++ 0xbd, 0x02, 0x3c, 0xd4, 0x12, 0x2d, 0x06, 0xeb, 0x85, 0xfd, 0xe0, 0xe4, ++ 0x19, 0xbb, 0x51, 0x8c, 0xc3, 0xe6, 0xb8, 0xe3, 0x11, 0x4e, 0x16, 0xb6, ++ 0x81, 0xf6, 0x6f, 0xbd, 0xe2, 0x5c, 0xa7, 0xc2, 0x38, 0xea, 0x0d, 0x89, ++ 0xf5, 0x0c, 0xe0, 0x59, 0x60, 0x77, 0xa9, 0xb8, 0x5f, 0x45, 0xcc, 0x37, ++ 0x0d, 0x9f, 0x17, 0x5b, 0x1a, 0xea, 0x8d, 0xd0, 0xd5, 0x0d, 0xec, 0xa2, ++ 0xfd, 0x04, 0xc8, 0x13, 0xd6, 0x7b, 0x7b, 0xd5, 0xa5, 0x98, 0xc0, 0x3a, ++ 0x14, 0xb9, 0x2e, 0x8f, 0xc2, 0x8c, 0x50, 0x1f, 0x21, 0xea, 0x93, 0x3c, ++ 0x8a, 0xff, 0xb1, 0x44, 0x5c, 0xcf, 0x5b, 0xdf, 0xe2, 0xb8, 0x23, 0x44, ++ 0x39, 0x09, 0x4b, 0xd8, 0x3f, 0x58, 0xe6, 0xdf, 0xff, 0x0a, 0x1f, 0x0f, ++ 0x57, 0x1c, 0x03, 0x70, 0xbc, 0x89, 0xaf, 0xa4, 0xc5, 0x21, 0xde, 0xac, ++ 0x51, 0x6a, 0x99, 0x6e, 0x7e, 0x47, 0x5f, 0x85, 0x7e, 0x54, 0x43, 0x47, ++ 0x0c, 0xb6, 0x1b, 0xc3, 0xdc, 0x46, 0x2e, 0x77, 0xbd, 0x38, 0x49, 0xf6, ++ 0x96, 0xe2, 0xa7, 0x79, 0xff, 0x88, 0xb9, 0xee, 0xc7, 0x52, 0xca, 0xb7, ++ 0x6a, 0xd6, 0x30, 0x76, 0x1a, 0xd4, 0xab, 0x1b, 0x41, 0x6e, 0x45, 0x62, ++ 0x19, 0xde, 0xa2, 0x42, 0xc9, 0x9a, 0x74, 0xf0, 0x64, 0xc6, 0xe3, 0x58, ++ 0x37, 0xc0, 0x4a, 0x10, 0xbf, 0x97, 0x62, 0x5d, 0xee, 0x7b, 0x62, 0xe0, ++ 0x3d, 0xd5, 0xd5, 0xae, 0xf5, 0x55, 0xb0, 0x86, 0x3e, 0xd1, 0x57, 0x96, ++ 0xef, 0x1b, 0x13, 0xed, 0x34, 0x5f, 0x90, 0x7f, 0xa9, 0xfc, 0x3d, 0xe7, ++ 0x6f, 0x8b, 0x04, 0xbc, 0x16, 0x49, 0xb9, 0xe5, 0xd5, 0xce, 0xef, 0x18, ++ 0xfe, 0xd2, 0x87, 0xb1, 0x3f, 0x9a, 0x00, 0x26, 0xf9, 0x48, 0x47, 0x16, ++ 0x8f, 0xa1, 0x27, 0xa8, 0x05, 0x89, 0x40, 0x97, 0xd8, 0x2e, 0x87, 0xe5, ++ 0x60, 0xff, 0x40, 0x57, 0x8e, 0x44, 0xe8, 0xbf, 0x57, 0x34, 0xd0, 0xa1, ++ 0x12, 0x4c, 0x77, 0xbc, 0xbd, 0x7c, 0xdf, 0x85, 0xee, 0x74, 0xeb, 0x67, ++ 0xb5, 0xb0, 0xb9, 0x43, 0x00, 0xde, 0xb6, 0x42, 0x93, 0x1b, 0x58, 0xee, ++ 0xdc, 0xe0, 0xf5, 0x5e, 0x05, 0x3c, 0xa4, 0x1e, 0x31, 0x0f, 0xdb, 0x42, ++ 0xf9, 0x2f, 0x87, 0x83, 0xd6, 0x5d, 0xd5, 0xe3, 0xd8, 0x07, 0x2e, 0x7c, ++ 0x5d, 0xe8, 0x4b, 0x40, 0xf9, 0x2f, 0xf7, 0xa9, 0xc6, 0xc4, 0xdc, 0x0d, ++ 0xa8, 0xb7, 0x34, 0xc4, 0xd1, 0xb8, 0xf2, 0xf9, 0xe8, 0x44, 0x83, 0xd0, ++ 0x27, 0x00, 0x1f, 0xaf, 0x02, 0x4e, 0xdd, 0xef, 0x43, 0x0a, 0xe9, 0x43, ++ 0x72, 0x1f, 0xae, 0x56, 0x1f, 0xca, 0x45, 0x1c, 0x2f, 0x0a, 0xc0, 0xef, ++ 0xe6, 0xae, 0xf0, 0x9e, 0x90, 0x18, 0x17, 0x04, 0x4f, 0x06, 0xf0, 0xcc, ++ 0xd6, 0xc0, 0x5b, 0xfb, 0x5e, 0xc0, 0x5b, 0xc2, 0xe3, 0x6c, 0x91, 0x6f, ++ 0x3b, 0xee, 0x93, 0x6a, 0x3b, 0xdc, 0x0b, 0xe1, 0xbc, 0x32, 0xbe, 0x7c, ++ 0x12, 0xee, 0xcf, 0x80, 0xa3, 0xfe, 0x13, 0x8a, 0x21, 0x30, 0xaf, 0x31, ++ 0x6a, 0xeb, 0xf6, 0xc7, 0x50, 0x8e, 0x35, 0xa9, 0x4e, 0xa4, 0xe5, 0xea, ++ 0x11, 0x9c, 0xcf, 0x55, 0xbf, 0xac, 0x12, 0xe9, 0xb7, 0x35, 0x9b, 0xbd, ++ 0x0a, 0xf4, 0xb3, 0xa8, 0xe9, 0x4d, 0xd2, 0xcf, 0x5a, 0xeb, 0x80, 0x91, ++ 0x86, 0x75, 0x0f, 0xa7, 0xce, 0xf5, 0xea, 0xe0, 0xdd, 0x15, 0x1e, 0x7c, ++ 0x1f, 0xe5, 0x7a, 0x96, 0xea, 0xd6, 0x3f, 0xf3, 0xbd, 0xf3, 0xb6, 0x19, ++ 0x0e, 0x5a, 0x67, 0xcd, 0x15, 0xe0, 0x50, 0x13, 0x0a, 0x0e, 0x67, 0x7e, ++ 0xcc, 0x66, 0x95, 0x67, 0xe1, 0xfa, 0xb2, 0x7a, 0xfa, 0xb3, 0x02, 0xe3, ++ 0x66, 0xe1, 0xbe, 0x03, 0x1c, 0x7e, 0x1e, 0x59, 0x7e, 0x0f, 0xc2, 0xa3, ++ 0xf0, 0xfd, 0xfe, 0x91, 0x08, 0x9f, 0x31, 0x6a, 0xf3, 0xfe, 0xbe, 0x08, ++ 0x87, 0x15, 0x8a, 0xd3, 0x0c, 0xe3, 0x8e, 0x32, 0x33, 0x4f, 0x38, 0xec, ++ 0x73, 0x9f, 0x95, 0x65, 0xec, 0xef, 0xb0, 0x57, 0xc5, 0xfe, 0x5a, 0xa7, ++ 0x1d, 0xe0, 0x11, 0xdf, 0xdf, 0xea, 0x54, 0x01, 0x1e, 0x69, 0xf7, 0xa8, ++ 0xe5, 0x5e, 0xe8, 0xf7, 0x6f, 0x2b, 0x96, 0x47, 0xcf, 0x85, 0xf2, 0xcb, ++ 0x3a, 0x18, 0x7a, 0x20, 0x3c, 0x57, 0x0c, 0xe5, 0x84, 0x6f, 0x6c, 0xd7, ++ 0x27, 0x3f, 0x85, 0xfe, 0xd2, 0x6c, 0xd3, 0x9d, 0xeb, 0xa1, 0x36, 0xc3, ++ 0x0c, 0xf3, 0x81, 0x71, 0x12, 0x7f, 0x1c, 0xd1, 0x92, 0x0c, 0x7c, 0xe2, ++ 0x75, 0x13, 0xb3, 0x20, 0xbd, 0x85, 0x25, 0xd5, 0x1e, 0x1a, 0x0f, 0xfd, ++ 0x76, 0x44, 0xa9, 0x4e, 0xd4, 0x83, 0x63, 0x55, 0x36, 0x1a, 0xf1, 0x4b, ++ 0xc2, 0x39, 0x36, 0x82, 0xaf, 0x43, 0x3e, 0x2f, 0x79, 0x62, 0xab, 0xe2, ++ 0xb7, 0x06, 0x9e, 0x8f, 0xaa, 0xef, 0x28, 0x58, 0x06, 0x65, 0x45, 0x22, ++ 0xdf, 0x77, 0xb9, 0xce, 0x51, 0x65, 0x1d, 0x05, 0xa8, 0xf7, 0x48, 0x38, ++ 0xc7, 0x26, 0xf3, 0xf6, 0xcc, 0xd8, 0x91, 0x30, 0x31, 0x88, 0x3e, 0x72, ++ 0x05, 0x3c, 0x8e, 0xa1, 0x5e, 0x07, 0xf0, 0xac, 0x8e, 0x33, 0xad, 0x41, ++ 0x39, 0xd8, 0x66, 0xe1, 0x75, 0xe6, 0x4a, 0x27, 0xfd, 0x77, 0x85, 0x85, ++ 0xd3, 0xc7, 0xb1, 0xf0, 0x04, 0x2f, 0xca, 0xc7, 0x63, 0xb0, 0x56, 0x1f, ++ 0xf5, 0xd7, 0x62, 0x63, 0xd6, 0x20, 0xbe, 0x18, 0xee, 0xea, 0x79, 0x23, ++ 0xac, 0x9b, 0xbd, 0xa7, 0xb2, 0x6d, 0x50, 0x7c, 0x6d, 0x77, 0xf5, 0x8c, ++ 0x22, 0x78, 0xd8, 0x79, 0x3f, 0x42, 0xdf, 0x6a, 0x63, 0x6c, 0x1c, 0xc2, ++ 0x69, 0xc5, 0xf8, 0xd2, 0xde, 0xd1, 0x50, 0xc6, 0xd5, 0x73, 0xf8, 0xe8, ++ 0xf1, 0xa4, 0x31, 0x91, 0xeb, 0xfd, 0x95, 0x17, 0x80, 0xf0, 0x0a, 0x02, ++ 0xcf, 0x2b, 0x8d, 0x2d, 0x26, 0xbb, 0x15, 0x9f, 0x9b, 0x34, 0xcf, 0x8f, ++ 0x03, 0xdc, 0x3c, 0xe6, 0x40, 0x7d, 0xce, 0xa9, 0x94, 0xb1, 0x8c, 0xf8, ++ 0x8c, 0x73, 0x0d, 0xb6, 0x9f, 0xbb, 0x2e, 0x82, 0x79, 0x82, 0xf4, 0xab, ++ 0x46, 0x31, 0x8f, 0xee, 0xe0, 0x52, 0x1d, 0x65, 0x64, 0x46, 0x80, 0x47, ++ 0xb5, 0xc2, 0xca, 0x2f, 0xd7, 0xee, 0xd5, 0xff, 0xa8, 0x04, 0x5f, 0xfd, ++ 0xfc, 0xff, 0x2a, 0xf8, 0x4c, 0x5c, 0x59, 0xe8, 0xf5, 0x1d, 0x12, 0xeb, ++ 0x2b, 0x5b, 0x7b, 0xeb, 0x6f, 0x51, 0xff, 0xac, 0xf6, 0x85, 0x31, 0x33, ++ 0x3c, 0x5a, 0xf1, 0x72, 0x49, 0x6f, 0x16, 0xa2, 0xbf, 0x4e, 0x38, 0x5f, ++ 0x18, 0xc6, 0xbc, 0x31, 0x41, 0x75, 0xa3, 0x9f, 0xe0, 0x51, 0x7d, 0x61, ++ 0x24, 0x3d, 0x2f, 0x5b, 0xdb, 0x6a, 0x42, 0xbc, 0xc7, 0x7e, 0x1c, 0xf0, ++ 0x7c, 0x45, 0xb8, 0xab, 0xb7, 0xf3, 0x32, 0x70, 0xce, 0xc5, 0x79, 0xe0, ++ 0x7a, 0x2f, 0x44, 0x31, 0x4f, 0x4c, 0xf0, 0x73, 0x8e, 0x57, 0x81, 0xfe, ++ 0x63, 0xe9, 0xfd, 0xef, 0x11, 0x80, 0x80, 0xb7, 0x9e, 0x26, 0xd5, 0xbb, ++ 0x0d, 0x3e, 0xfd, 0xfd, 0x01, 0xc3, 0xb8, 0x2d, 0xa1, 0xe6, 0x2b, 0xd6, ++ 0x3f, 0x28, 0xce, 0x48, 0xf4, 0x92, 0xd9, 0xc2, 0x5c, 0x9b, 0x43, 0x8c, ++ 0x2f, 0xdb, 0xf5, 0x8a, 0x06, 0x7e, 0x6d, 0xe5, 0x70, 0xae, 0xc8, 0xee, ++ 0x3a, 0xbf, 0xc6, 0x52, 0xff, 0x4c, 0x9c, 0xff, 0x8d, 0xa3, 0x99, 0x2b, ++ 0xd4, 0x78, 0xe7, 0x44, 0x3b, 0x39, 0xef, 0xc6, 0x68, 0xff, 0x02, 0x81, ++ 0xf7, 0xa9, 0x15, 0xb6, 0xa0, 0xba, 0x5d, 0xbb, 0x8f, 0x3d, 0xc5, 0xf8, ++ 0x8d, 0x37, 0xfb, 0x13, 0xb0, 0xff, 0xb6, 0xf1, 0x6c, 0x6a, 0x43, 0x88, ++ 0xfe, 0xe5, 0x7e, 0xcf, 0x88, 0x77, 0x67, 0x22, 0xdf, 0xa9, 0xbc, 0x03, ++ 0x1a, 0x03, 0x7e, 0x0c, 0x36, 0xd6, 0x2a, 0xf6, 0x20, 0x7a, 0xeb, 0x6e, ++ 0xbf, 0x03, 0x70, 0x06, 0xbb, 0xab, 0xe0, 0x72, 0x70, 0x36, 0xd1, 0x7b, ++ 0xd9, 0xdf, 0xe9, 0x43, 0x82, 0x1e, 0x99, 0xcb, 0xaa, 0x00, 0x1d, 0xcd, ++ 0x16, 0xf2, 0x6a, 0xf6, 0xd6, 0xa5, 0xb7, 0x02, 0xcf, 0xec, 0xb4, 0x5f, ++ 0x4e, 0x6f, 0x02, 0xfb, 0x05, 0x86, 0x38, 0xcd, 0x6a, 0xdf, 0xb4, 0x61, ++ 0x7d, 0x83, 0x42, 0xf6, 0xc9, 0x1c, 0x37, 0xc8, 0x00, 0xe0, 0x37, 0x0b, ++ 0xb6, 0x15, 0xac, 0x41, 0xb1, 0x35, 0x3b, 0x9e, 0xb1, 0x91, 0xd1, 0xfc, ++ 0xf9, 0xbd, 0x58, 0xae, 0x0e, 0x0b, 0xc8, 0x59, 0xfa, 0xdf, 0xc5, 0x82, ++ 0xe5, 0xa2, 0x1c, 0x7f, 0xde, 0x83, 0x5a, 0xbd, 0x75, 0x11, 0x7b, 0xf0, ++ 0x2b, 0xd4, 0x7b, 0x4e, 0x1f, 0xe2, 0x7c, 0x01, 0xd4, 0x53, 0xb2, 0xbf, ++ 0x17, 0x3c, 0xa2, 0xed, 0x6f, 0xd1, 0xd6, 0x5b, 0x4e, 0xe2, 0x3c, 0x17, ++ 0xe9, 0xf4, 0x9f, 0x34, 0x54, 0xf0, 0x40, 0xff, 0x48, 0x4b, 0x12, 0xf6, ++ 0xc4, 0x60, 0x36, 0x18, 0xf9, 0xff, 0xb2, 0x6d, 0xe7, 0x4d, 0x91, 0x8e, ++ 0xee, 0xf1, 0xff, 0x4b, 0xa0, 0xf3, 0x94, 0x81, 0xc8, 0x27, 0xed, 0x54, ++ 0x0e, 0x4d, 0x72, 0xe5, 0x24, 0xa1, 0x7f, 0xe1, 0x3d, 0x3e, 0xcf, 0xf1, ++ 0x49, 0xee, 0xfc, 0x24, 0xf4, 0xa3, 0xbc, 0xc7, 0xe7, 0x75, 0xae, 0xf2, ++ 0x1c, 0x97, 0x0f, 0x8f, 0xc7, 0x92, 0x5c, 0x32, 0x23, 0x13, 0x87, 0x5f, ++ 0xcd, 0xd3, 0x2c, 0xde, 0x7a, 0x98, 0xc7, 0x5a, 0x60, 0x23, 0xe1, 0x00, ++ 0x1f, 0xb3, 0x99, 0xeb, 0x41, 0x52, 0xff, 0x53, 0xd5, 0xe5, 0x6a, 0x24, ++ 0xbc, 0x1f, 0xf2, 0xc5, 0x8a, 0x68, 0x37, 0xf2, 0xe1, 0x67, 0x6f, 0x1a, ++ 0x87, 0xfd, 0xc5, 0x3d, 0x1b, 0xe1, 0xc2, 0xf5, 0xac, 0x2f, 0x71, 0xe5, ++ 0xa1, 0xbf, 0x60, 0x7d, 0x85, 0xd5, 0x59, 0x0f, 0x5d, 0x5a, 0xe0, 0x7b, ++ 0x94, 0x1b, 0xde, 0xdf, 0x0f, 0x79, 0xa3, 0x2f, 0x6a, 0x07, 0x0d, 0x1b, ++ 0x4b, 0xfb, 0x21, 0xba, 0x35, 0xef, 0x6d, 0x41, 0x7f, 0xca, 0x3a, 0xc3, ++ 0x57, 0xfb, 0xfb, 0x41, 0xfb, 0x75, 0x23, 0x99, 0xb3, 0x9e, 0x05, 0xc6, ++ 0xa9, 0x69, 0xae, 0x78, 0x1e, 0xe7, 0x93, 0x30, 0x99, 0xcb, 0x97, 0xf5, ++ 0x89, 0xae, 0x3c, 0x7b, 0x50, 0xbf, 0x4c, 0xe8, 0x73, 0xd5, 0x02, 0x76, ++ 0xed, 0x7b, 0xd2, 0x7e, 0x39, 0x0c, 0xf6, 0xf7, 0xb1, 0x03, 0xa4, 0x4e, ++ 0xc3, 0xfa, 0xc0, 0x9e, 0x87, 0xf9, 0x0d, 0x62, 0x7c, 0x9f, 0xd9, 0x45, ++ 0x80, 0x13, 0xe0, 0x09, 0x8e, 0x1d, 0xac, 0xb7, 0xb6, 0x82, 0x9c, 0x62, ++ 0x69, 0x81, 0xfa, 0xa0, 0x06, 0xa5, 0x25, 0x0c, 0xd6, 0x53, 0xd5, 0xf8, ++ 0xbc, 0x01, 0xe5, 0x60, 0xe5, 0x7d, 0x2d, 0xbd, 0xa6, 0xa1, 0x3c, 0x7a, ++ 0xc6, 0xe8, 0xdc, 0x12, 0x34, 0xbf, 0xd8, 0xd7, 0xfb, 0x94, 0x3a, 0x22, ++ 0x03, 0x72, 0x68, 0x9a, 0x62, 0x27, 0x3d, 0x41, 0xea, 0xe5, 0x77, 0x32, ++ 0xf9, 0x2f, 0x8b, 0xf0, 0x66, 0xaa, 0xc0, 0x9b, 0x3b, 0x85, 0x3e, 0x3e, ++ 0x2d, 0x82, 0xc3, 0x77, 0x0e, 0x73, 0x26, 0xe0, 0x77, 0x77, 0x59, 0x58, ++ 0xa4, 0x01, 0x48, 0x69, 0x5a, 0x59, 0x43, 0x11, 0xc9, 0xa9, 0xa5, 0x61, ++ 0x51, 0x28, 0xff, 0x71, 0x2d, 0xa1, 0xf6, 0x5b, 0x96, 0xdd, 0xf9, 0x95, ++ 0xaa, 0xb7, 0xdb, 0x3c, 0x0a, 0xec, 0x7b, 0x9b, 0xd2, 0x91, 0x8a, 0x9d, ++ 0x7c, 0x89, 0xbe, 0x1e, 0xee, 0x5f, 0xf2, 0x6e, 0x49, 0xec, 0xda, 0x4f, ++ 0x5d, 0x92, 0xa0, 0xc3, 0x54, 0xa1, 0x1f, 0xa6, 0x30, 0x97, 0x0d, 0xd6, ++ 0x5d, 0xfd, 0x5a, 0xda, 0xe6, 0xf5, 0xf0, 0xca, 0xdc, 0x03, 0xf6, 0x31, ++ 0x9f, 0xf8, 0x91, 0xa5, 0x38, 0x9f, 0xf4, 0x63, 0x0b, 0xda, 0x3d, 0x8b, ++ 0x5f, 0x0d, 0x6f, 0x51, 0x22, 0x03, 0x70, 0x61, 0x76, 0x57, 0x9e, 0x01, ++ 0xbe, 0xab, 0x99, 0xd8, 0x3f, 0x7f, 0x3d, 0xea, 0xa4, 0x47, 0x81, 0xaf, ++ 0x00, 0x81, 0xb5, 0x85, 0xf9, 0x13, 0x88, 0x8e, 0x81, 0xdf, 0x28, 0x20, ++ 0xf3, 0x36, 0x25, 0x8d, 0xad, 0x30, 0x02, 0xde, 0x55, 0xf7, 0x05, 0xfd, ++ 0x0b, 0xea, 0xfb, 0xb7, 0x4c, 0xaa, 0x30, 0x02, 0xde, 0x57, 0x27, 0xf9, ++ 0x17, 0x18, 0xa0, 0xde, 0x96, 0x54, 0xc5, 0xeb, 0x83, 0xfc, 0x27, 0xb0, ++ 0x7e, 0x21, 0x69, 0x25, 0xaf, 0xe7, 0xfb, 0x17, 0xa8, 0x50, 0x8f, 0x49, ++ 0x5e, 0xc3, 0xeb, 0x68, 0x08, 0x02, 0x62, 0x39, 0x92, 0x1f, 0xaa, 0xf0, ++ 0x40, 0xff, 0x5f, 0x46, 0x09, 0xb9, 0xee, 0xf4, 0xcf, 0x44, 0xfc, 0xa9, ++ 0x7e, 0x25, 0xcd, 0xb0, 0x3e, 0x68, 0xbd, 0xd6, 0x64, 0xce, 0xaf, 0xbe, ++ 0x0c, 0xe7, 0xed, 0xbe, 0x4c, 0x64, 0xb3, 0x26, 0x22, 0xbc, 0xd3, 0xfd, ++ 0xa9, 0x38, 0x4f, 0xd9, 0xae, 0x23, 0x49, 0xea, 0xc3, 0x1b, 0xa8, 0xbd, ++ 0x5c, 0xa7, 0xfc, 0x8e, 0xc5, 0x87, 0xee, 0xff, 0x77, 0x49, 0xbc, 0xff, ++ 0xc5, 0x65, 0x42, 0x1f, 0x89, 0x60, 0xeb, 0x10, 0x6e, 0xb0, 0x4d, 0x9e, ++ 0x48, 0x80, 0xff, 0xbe, 0xe6, 0xb4, 0x2d, 0xd8, 0xfe, 0xc1, 0xa4, 0x68, ++ 0xde, 0xbf, 0x1d, 0xfa, 0x29, 0x0c, 0xf4, 0x23, 0xe1, 0x28, 0xfb, 0x93, ++ 0xe3, 0x2e, 0x41, 0x79, 0x8b, 0x7c, 0x38, 0x0c, 0xf8, 0x70, 0x10, 0x1f, ++ 0x6d, 0x4c, 0xe2, 0xf2, 0x12, 0xc6, 0x59, 0x4d, 0xe3, 0xa4, 0x00, 0xfc, ++ 0xb1, 0xbf, 0x89, 0xfd, 0xf3, 0x70, 0xdf, 0x60, 0xbf, 0x8c, 0x62, 0xbf, ++ 0x8c, 0xdc, 0x4e, 0xdd, 0x4c, 0xed, 0xb1, 0xdf, 0xa8, 0x1c, 0xe2, 0xfb, ++ 0x05, 0x46, 0x58, 0xc7, 0xbe, 0x8b, 0xd0, 0x3e, 0x31, 0x30, 0x6f, 0x3d, ++ 0x7e, 0xec, 0x15, 0xf8, 0xb1, 0xb8, 0x1e, 0x18, 0x21, 0xe9, 0x67, 0xc9, ++ 0x84, 0x47, 0xa3, 0x22, 0xb8, 0x5e, 0xc8, 0x0a, 0xb5, 0xeb, 0x88, 0x49, ++ 0xe6, 0xf0, 0xb3, 0x26, 0x47, 0xf1, 0x75, 0x76, 0xee, 0x47, 0x6f, 0x85, ++ 0xc6, 0xa9, 0x17, 0x70, 0xec, 0x0f, 0x70, 0xcf, 0xbe, 0xf6, 0x75, 0xbf, ++ 0x2f, 0xe6, 0xf3, 0x5d, 0xaf, 0x3b, 0x68, 0xbf, 0x5c, 0x2a, 0xbe, 0x6f, ++ 0xca, 0xd8, 0x12, 0xbc, 0x1e, 0xb0, 0x2c, 0x35, 0xfd, 0x7c, 0xb9, 0x4a, ++ 0xf7, 0x5d, 0x31, 0x10, 0x20, 0xae, 0x33, 0x3a, 0x99, 0xbe, 0x5b, 0x1b, ++ 0xce, 0x2c, 0xf4, 0x9c, 0x6d, 0xe9, 0xfc, 0x2e, 0x31, 0x87, 0xeb, 0xa3, ++ 0xa8, 0xa7, 0x56, 0x09, 0x7d, 0x9a, 0x79, 0x46, 0x92, 0x53, 0xa1, 0x52, ++ 0x70, 0x8d, 0xaa, 0x75, 0x3e, 0x93, 0x03, 0xdf, 0x37, 0x28, 0x2e, 0xaf, ++ 0x35, 0x78, 0x7d, 0xb7, 0x16, 0x8a, 0xf5, 0xd9, 0xc5, 0xfa, 0xec, 0x7c, ++ 0x7d, 0x5e, 0x0d, 0x9e, 0xb2, 0xc3, 0x1d, 0x09, 0x93, 0x6d, 0x5d, 0xf1, ++ 0xb7, 0x13, 0xee, 0x9d, 0xfd, 0x65, 0xe5, 0x8b, 0xfe, 0x34, 0x74, 0x1d, ++ 0xaa, 0x3f, 0xa4, 0x8f, 0xee, 0xf6, 0x23, 0x2c, 0xf9, 0x3b, 0xde, 0x0f, ++ 0x39, 0x4f, 0x1d, 0x3c, 0x3b, 0xe1, 0xac, 0x9b, 0x9f, 0x84, 0x27, 0xd2, ++ 0x33, 0x7d, 0x97, 0xa5, 0xc5, 0x47, 0x39, 0xcf, 0x0b, 0x82, 0x3e, 0xbb, ++ 0xd0, 0x75, 0xe2, 0x75, 0x8e, 0x57, 0xc2, 0xbf, 0xab, 0xfa, 0x09, 0xec, ++ 0x23, 0xea, 0x27, 0x0e, 0x2d, 0x3e, 0x57, 0x35, 0x26, 0x1a, 0xe6, 0x64, ++ 0x05, 0xbe, 0x6b, 0xc2, 0xbd, 0x2c, 0x0a, 0xf8, 0xe7, 0xd2, 0x93, 0x85, ++ 0x9d, 0xd7, 0x9f, 0xf5, 0x47, 0xfe, 0xed, 0x29, 0xe5, 0x7e, 0x54, 0xcf, ++ 0x2e, 0xb3, 0xb3, 0xde, 0x41, 0x7e, 0xbd, 0xac, 0xe4, 0xb8, 0x90, 0x7e, ++ 0x3d, 0x7a, 0xae, 0xb7, 0xf3, 0xda, 0xa3, 0x4c, 0x4c, 0x21, 0xbd, 0x48, ++ 0xeb, 0x67, 0x68, 0x8f, 0x73, 0xfa, 0x5c, 0xa8, 0x9f, 0x9e, 0x65, 0xce, ++ 0x6d, 0xd0, 0xef, 0x30, 0x9d, 0xde, 0xd1, 0x0e, 0xfb, 0xb9, 0xcb, 0x1a, ++ 0xf8, 0x2e, 0x20, 0x4f, 0xb4, 0xf5, 0x9f, 0x08, 0x3a, 0xe8, 0xea, 0x37, ++ 0xea, 0x48, 0xc0, 0xf9, 0x15, 0x9a, 0x4b, 0x5f, 0x70, 0x38, 0x19, 0x1b, ++ 0x9b, 0xfc, 0x14, 0xf1, 0xf7, 0xc2, 0x9e, 0xa5, 0xcb, 0x13, 0xa1, 0x7e, ++ 0x4b, 0xf2, 0x36, 0xe2, 0xd7, 0x85, 0xfd, 0x4a, 0xcf, 0xa3, 0x6b, 0xe6, ++ 0xb6, 0xe4, 0xed, 0xbc, 0x9e, 0x59, 0x7a, 0x3e, 0x09, 0xeb, 0x4f, 0x6d, ++ 0xe7, 0xed, 0x47, 0xb9, 0x5e, 0x40, 0xfe, 0xce, 0x3c, 0xdb, 0x2b, 0x46, ++ 0x0f, 0x09, 0xe8, 0x0f, 0x13, 0x92, 0x1d, 0x5c, 0xff, 0x28, 0x33, 0x30, ++ 0xc4, 0x23, 0xb3, 0x7a, 0xb7, 0x13, 0xe5, 0xa4, 0x84, 0x67, 0x77, 0x65, ++ 0xa1, 0xd9, 0x50, 0x1b, 0x4a, 0x6f, 0xbd, 0xa3, 0x93, 0x9e, 0xf9, 0x79, ++ 0x46, 0xb1, 0x90, 0xcf, 0xc5, 0xd2, 0x8e, 0xf7, 0x1b, 0x35, 0x76, 0x7c, ++ 0x7b, 0xa4, 0xc5, 0xa3, 0x02, 0x5c, 0xdb, 0x51, 0x9e, 0xc2, 0x7a, 0xe7, ++ 0x24, 0xbb, 0xa7, 0x23, 0xfc, 0x6b, 0x22, 0x5a, 0x67, 0xa2, 0x0a, 0x7c, ++ 0x5f, 0xc4, 0x27, 0x26, 0xd4, 0x87, 0x14, 0x17, 0xe8, 0x1b, 0xe8, 0x17, ++ 0x71, 0xd8, 0xd9, 0x74, 0x98, 0xa7, 0xd2, 0xba, 0xbe, 0x9c, 0xf4, 0xc0, ++ 0x25, 0x4e, 0x8b, 0x91, 0xe0, 0x29, 0xfc, 0x54, 0xb0, 0xf6, 0x4b, 0xd0, ++ 0xcf, 0xab, 0xaf, 0x3d, 0xf3, 0xb3, 0x7e, 0x7c, 0x98, 0x72, 0x9c, 0xc7, ++ 0x10, 0x41, 0xff, 0x35, 0xaf, 0x7d, 0xfb, 0xcd, 0x5f, 0x51, 0x8e, 0x7e, ++ 0x69, 0x75, 0xa2, 0x1b, 0x70, 0x48, 0xf3, 0xa3, 0xcb, 0x51, 0xbf, 0x1a, ++ 0xd2, 0xfc, 0xa7, 0x6f, 0xb9, 0xbc, 0xb5, 0xd2, 0x39, 0x95, 0x9c, 0xf7, ++ 0x10, 0xf4, 0x37, 0xc2, 0xf3, 0xe2, 0x26, 0x33, 0xcd, 0x7f, 0x48, 0x73, ++ 0xc6, 0x7c, 0x6c, 0x3f, 0xec, 0xfd, 0xe6, 0x64, 0xc4, 0x8f, 0x11, 0xc7, ++ 0x5a, 0xea, 0x91, 0x1d, 0xb4, 0xef, 0x79, 0xa9, 0x9f, 0x3b, 0xf8, 0xdc, ++ 0x8a, 0x9d, 0x54, 0x2e, 0x65, 0x5e, 0xbb, 0x7e, 0xd1, 0x09, 0x8f, 0x2f, ++ 0x4c, 0x0c, 0xf5, 0x4b, 0x80, 0xc7, 0xff, 0xe1, 0xf0, 0xb8, 0xb8, 0x00, ++ 0xfd, 0x8a, 0x6d, 0x71, 0x87, 0xd6, 0xf8, 0x49, 0x4f, 0xeb, 0xcf, 0xfd, ++ 0x98, 0xe2, 0x7b, 0xd0, 0xcb, 0xd3, 0x91, 0xce, 0xcf, 0xb1, 0x1e, 0x4e, ++ 0x3c, 0x57, 0x68, 0xb7, 0xf1, 0x7e, 0xf4, 0xfe, 0xcd, 0xa3, 0x15, 0xb0, ++ 0x3e, 0x78, 0x3e, 0xa2, 0x03, 0x66, 0x10, 0xa4, 0x37, 0x8f, 0xba, 0x60, ++ 0x01, 0x06, 0x12, 0xa8, 0x97, 0xb0, 0x28, 0x4d, 0xbd, 0xcc, 0xd2, 0x47, ++ 0xd3, 0x7e, 0x8c, 0x3d, 0x51, 0xf3, 0xfe, 0xa6, 0xf8, 0x0c, 0xcd, 0xfb, ++ 0xf1, 0x8e, 0x3c, 0x4d, 0xfd, 0x96, 0xf4, 0x21, 0x9a, 0xf6, 0xb7, 0x39, ++ 0x4b, 0x34, 0xf5, 0xdb, 0x8b, 0xc7, 0x6b, 0xda, 0x57, 0xb8, 0x2a, 0x34, ++ 0xf5, 0xbc, 0x96, 0x06, 0x4d, 0xfb, 0x82, 0x03, 0x4d, 0xda, 0xf7, 0x87, ++ 0x1d, 0xb4, 0x0f, 0x05, 0xc7, 0xca, 0xcb, 0x50, 0x9f, 0x77, 0xfa, 0xdc, ++ 0xf5, 0x58, 0xde, 0xd8, 0xba, 0xa1, 0xac, 0xa7, 0x83, 0x75, 0xf1, 0xeb, ++ 0x16, 0xfa, 0xbd, 0xf5, 0xf8, 0x7c, 0xd8, 0xc5, 0xda, 0xa2, 0x16, 0xd6, ++ 0xd5, 0xbf, 0xcb, 0x96, 0xb8, 0xe9, 0x3c, 0xc0, 0x8c, 0xfb, 0xa2, 0x06, ++ 0x9d, 0x0f, 0x94, 0xf8, 0x88, 0x1e, 0xdb, 0x0c, 0x4e, 0x47, 0xb0, 0x1f, ++ 0xf7, 0xd1, 0x5e, 0xee, 0x17, 0x70, 0x9f, 0xde, 0x52, 0x00, 0xec, 0x00, ++ 0xec, 0x91, 0x96, 0x8e, 0x18, 0xdc, 0xaf, 0x31, 0xb3, 0x1e, 0x52, 0x23, ++ 0x71, 0x5f, 0x3a, 0x18, 0xf9, 0xbd, 0x1a, 0x4d, 0xfe, 0x5f, 0x0c, 0x43, ++ 0x39, 0x3f, 0x43, 0x25, 0xbd, 0xb7, 0xd1, 0xc8, 0x48, 0x7f, 0x6c, 0x9c, ++ 0x9a, 0xed, 0x45, 0xdf, 0xdf, 0x51, 0xc5, 0xff, 0xe2, 0x5f, 0x91, 0x4f, ++ 0xcd, 0x88, 0x20, 0x7e, 0x32, 0x02, 0x34, 0x5c, 0x5a, 0x37, 0x9e, 0x81, ++ 0x2a, 0xb8, 0x4f, 0x6e, 0xcd, 0xba, 0x4b, 0xd8, 0x62, 0xdd, 0x3e, 0xdd, ++ 0xad, 0xa9, 0x8f, 0xb1, 0xff, 0x44, 0xd3, 0xfe, 0xa6, 0xf8, 0x55, 0x9a, ++ 0xf7, 0xe3, 0x1d, 0x0f, 0xe8, 0xf6, 0x69, 0xa3, 0xa6, 0x7e, 0x9b, 0xf3, ++ 0x51, 0xdd, 0x3e, 0x6d, 0xd6, 0xed, 0xd3, 0x33, 0x9a, 0xf7, 0x23, 0x3e, ++ 0xf7, 0xd7, 0x23, 0x19, 0x8d, 0x6a, 0xf5, 0xa8, 0x36, 0x98, 0xff, 0xd0, ++ 0xa3, 0x1b, 0xca, 0x70, 0x5f, 0x86, 0x1d, 0xf3, 0xcc, 0x40, 0x7a, 0x29, ++ 0x6c, 0x71, 0xd7, 0x13, 0x0b, 0xd9, 0x57, 0xfb, 0x26, 0x96, 0x2d, 0x60, ++ 0x57, 0xa1, 0x3f, 0xeb, 0x8d, 0xba, 0x78, 0x2a, 0xf7, 0xd5, 0x39, 0xc8, ++ 0x1f, 0xb5, 0xbf, 0x2e, 0x9d, 0xca, 0x03, 0x75, 0x4e, 0x7a, 0xfe, 0x76, ++ 0x5d, 0x31, 0x95, 0xef, 0xd4, 0xb9, 0xa8, 0xfc, 0x4b, 0xdd, 0x38, 0x2a, ++ 0x7d, 0x75, 0xe5, 0x54, 0x36, 0xd4, 0x35, 0x50, 0xfb, 0x5d, 0x75, 0x4d, ++ 0x54, 0x02, 0x04, 0x07, 0xa0, 0xbc, 0x88, 0x8d, 0x11, 0xf2, 0x07, 0xea, ++ 0x68, 0xe7, 0xb7, 0x19, 0xfc, 0xd5, 0x78, 0xe2, 0x7a, 0xfa, 0xa9, 0x6f, ++ 0x88, 0x4f, 0xb6, 0xf5, 0xf0, 0xb7, 0x61, 0xfd, 0x3e, 0xf6, 0x8f, 0x8a, ++ 0xd1, 0x50, 0x3f, 0x9c, 0xc2, 0x88, 0xbf, 0x59, 0xa1, 0x4f, 0xa4, 0xc7, ++ 0x73, 0x29, 0xae, 0xca, 0x14, 0xa8, 0x5f, 0x48, 0xe6, 0xcf, 0xdb, 0xc3, ++ 0xac, 0xeb, 0x50, 0x0e, 0x34, 0x18, 0x5c, 0x79, 0xa8, 0x5f, 0xff, 0xfb, ++ 0xa9, 0xff, 0x6c, 0x34, 0x0e, 0x60, 0xec, 0xfe, 0x55, 0xe5, 0xf1, 0xf6, ++ 0x28, 0x5e, 0xb7, 0x40, 0x9d, 0x36, 0x1b, 0x0d, 0x33, 0xcf, 0x7f, 0x36, ++ 0xba, 0x86, 0x33, 0xf6, 0x1c, 0x8a, 0x8c, 0xa1, 0x54, 0xaf, 0xc0, 0x7a, ++ 0x7b, 0x38, 0x7f, 0x7f, 0xe1, 0xa9, 0xff, 0x90, 0x7e, 0x2d, 0xcf, 0x9b, ++ 0x27, 0x07, 0xce, 0x9b, 0xff, 0x9d, 0x1c, 0xe2, 0xbc, 0xf9, 0xb9, 0x53, ++ 0x0e, 0x1b, 0xfa, 0x59, 0x0e, 0x5d, 0x4c, 0xb3, 0xe1, 0xba, 0x0e, 0x09, ++ 0xbf, 0x92, 0x8b, 0xe5, 0x85, 0xcd, 0x86, 0xb2, 0xc4, 0x98, 0x17, 0x86, ++ 0x72, 0xf1, 0xa8, 0x4e, 0x8f, 0x90, 0xe5, 0xa7, 0xd6, 0x12, 0x53, 0x4a, ++ 0x1c, 0xce, 0xdf, 0x39, 0x05, 0xf5, 0x08, 0xcf, 0xcd, 0x61, 0x6c, 0x1b, ++ 0xf0, 0x8b, 0x89, 0x0a, 0xb7, 0x47, 0x3b, 0xf5, 0xc0, 0x14, 0x2e, 0xcf, ++ 0xdb, 0x6f, 0x33, 0x93, 0xbd, 0x73, 0xd8, 0xe0, 0x9a, 0x8f, 0x78, 0x0e, ++ 0x7c, 0xfa, 0x49, 0x84, 0x57, 0x42, 0x4a, 0xcf, 0x89, 0x28, 0x57, 0xda, ++ 0x6d, 0x1d, 0x09, 0x08, 0x87, 0xfe, 0x29, 0x91, 0xbc, 0x1e, 0xd7, 0xf1, ++ 0xa4, 0xe2, 0x0c, 0xaa, 0x87, 0xf1, 0x75, 0xc6, 0xa5, 0xd8, 0x26, 0x76, ++ 0xb3, 0xce, 0xbe, 0x38, 0x1f, 0xfd, 0x3a, 0x6f, 0x48, 0x11, 0xe7, 0x0c, ++ 0x2d, 0xae, 0x01, 0x28, 0x7f, 0x65, 0xfd, 0x70, 0x85, 0xab, 0x0a, 0xe5, ++ 0xc4, 0xe1, 0x12, 0xd7, 0x40, 0x9c, 0xcf, 0xa1, 0x72, 0x33, 0xd1, 0x8f, ++ 0xa7, 0xdc, 0xe6, 0x1d, 0x88, 0x4c, 0xce, 0xe8, 0x2a, 0x9a, 0x12, 0xe4, ++ 0x6f, 0x79, 0x34, 0x25, 0x8c, 0xbe, 0x9b, 0x6c, 0xe2, 0x74, 0xc6, 0xee, ++ 0x52, 0xbd, 0xdb, 0x42, 0xd8, 0x69, 0x2f, 0xa5, 0x70, 0x7d, 0x9f, 0xf6, ++ 0x0d, 0xed, 0xb9, 0x3b, 0x23, 0x48, 0x0f, 0x3f, 0x6c, 0x60, 0x8b, 0x76, ++ 0x85, 0x80, 0xe3, 0xbb, 0x29, 0x5c, 0xce, 0x9d, 0xe9, 0x11, 0xda, 0xff, ++ 0xe2, 0x13, 0xf0, 0x2b, 0x9d, 0x64, 0xa3, 0xfe, 0xda, 0x57, 0x84, 0xd3, ++ 0x79, 0x6f, 0x7b, 0x79, 0x1a, 0xe9, 0x41, 0xed, 0xb5, 0x00, 0x25, 0xa0, ++ 0x8f, 0xf6, 0x53, 0xb5, 0x67, 0x77, 0xd3, 0x7b, 0xb3, 0x3c, 0x0a, 0xa3, ++ 0x73, 0xcd, 0x69, 0x82, 0x4f, 0x3d, 0xd7, 0xbc, 0xfc, 0x1f, 0x47, 0xa0, ++ 0xfd, 0x27, 0x2b, 0x22, 0x9c, 0xc4, 0xc3, 0xed, 0x83, 0x48, 0x3e, 0xdd, ++ 0x25, 0x1a, 0xcf, 0x88, 0xb1, 0x90, 0xde, 0x32, 0x63, 0xe2, 0x80, 0x52, ++ 0x94, 0x4b, 0xd3, 0xc4, 0xf9, 0xd8, 0x4c, 0x9b, 0xb1, 0x17, 0x1d, 0x93, ++ 0x19, 0xa3, 0x4c, 0x76, 0xe8, 0x67, 0x9e, 0x35, 0x6f, 0x0d, 0x8a, 0xff, ++ 0x05, 0xb1, 0x15, 0xa6, 0x28, 0xa8, 0x2f, 0xea, 0x7f, 0xf7, 0x1a, 0x2c, ++ 0x97, 0xa4, 0x6c, 0x34, 0x45, 0x43, 0x59, 0x99, 0xf5, 0xfc, 0x1a, 0x54, ++ 0x1f, 0xab, 0x80, 0xb4, 0x8a, 0xc8, 0x5e, 0xf2, 0xff, 0xb9, 0x0e, 0xe6, ++ 0x35, 0x6b, 0xa5, 0xea, 0xe0, 0xf6, 0x93, 0x90, 0x6b, 0xae, 0xa5, 0xd7, ++ 0x14, 0x8f, 0x21, 0xf1, 0x10, 0xe1, 0x88, 0x78, 0x0a, 0xf0, 0x25, 0xbb, ++ 0xf0, 0x3d, 0x01, 0x6f, 0xf9, 0xdd, 0x7b, 0x02, 0x9e, 0xb3, 0x52, 0xc4, ++ 0x39, 0x6d, 0x36, 0xcb, 0xbe, 0xa4, 0x3d, 0xf7, 0x99, 0x8b, 0x78, 0xd2, ++ 0x3a, 0xe3, 0xcf, 0xa9, 0xdd, 0xf8, 0xe7, 0xb5, 0xef, 0x85, 0xde, 0xf6, ++ 0x81, 0x89, 0x8f, 0xbb, 0xf4, 0xe9, 0x30, 0x6f, 0xb0, 0x3f, 0x49, 0x8e, ++ 0x7b, 0x48, 0xcc, 0xe3, 0xb0, 0x89, 0xb9, 0x14, 0xd4, 0xe3, 0xee, 0xb2, ++ 0x11, 0x7e, 0xe4, 0x4c, 0x3d, 0x7f, 0x5f, 0x11, 0xac, 0x3f, 0xa7, 0xd9, ++ 0x6e, 0xa0, 0x73, 0x7b, 0xc9, 0xc7, 0x7d, 0x8c, 0xfc, 0xf6, 0x45, 0x9f, ++ 0xbb, 0x89, 0xcf, 0xdd, 0xd8, 0xea, 0xdf, 0x7e, 0x84, 0x11, 0x9e, 0x37, ++ 0x21, 0x9d, 0x5c, 0x49, 0x4e, 0x4d, 0xf2, 0xac, 0x22, 0xf9, 0x30, 0xe4, ++ 0x6b, 0x90, 0x3f, 0xc8, 0x17, 0x2f, 0xba, 0x3f, 0x39, 0x42, 0x7c, 0x70, ++ 0x91, 0xe0, 0x83, 0xb5, 0xc4, 0xbf, 0xf6, 0xd5, 0xad, 0xa4, 0xfa, 0xfe, ++ 0x3a, 0x0f, 0x95, 0x07, 0xea, 0xd6, 0x09, 0x3e, 0xb8, 0x81, 0xde, 0xbf, ++ 0x53, 0xb7, 0x49, 0xf0, 0x41, 0xaf, 0xe0, 0x83, 0x4f, 0xd3, 0xf3, 0xe6, ++ 0xba, 0xa9, 0x54, 0xbe, 0x56, 0xe7, 0x16, 0x7c, 0x90, 0x9f, 0xab, 0x4e, ++ 0x14, 0xf8, 0xb4, 0x32, 0xde, 0xbd, 0x0e, 0xf9, 0x99, 0x3c, 0xbf, 0x9c, ++ 0x6c, 0x71, 0x87, 0x21, 0xbc, 0xfe, 0xf8, 0xa8, 0x99, 0xa9, 0x78, 0x2e, ++ 0xd1, 0x6c, 0x26, 0x3c, 0x05, 0x0a, 0x78, 0xf2, 0xb1, 0x58, 0x8c, 0x97, ++ 0x31, 0xdb, 0xd7, 0x3b, 0xba, 0xc6, 0xcd, 0xe8, 0xf9, 0x6d, 0xe7, 0xfe, ++ 0xeb, 0xce, 0x79, 0x37, 0xc4, 0xbb, 0x1e, 0xc1, 0xf1, 0x3a, 0xe3, 0x64, ++ 0x50, 0x3f, 0xbb, 0xa1, 0x7b, 0xfc, 0x39, 0xc4, 0x1c, 0x36, 0xe4, 0x27, ++ 0x3b, 0xb6, 0x4e, 0x24, 0xfe, 0x71, 0xc8, 0xe1, 0xb0, 0xa1, 0xde, 0xfa, ++ 0x5c, 0xca, 0xa4, 0x89, 0xc8, 0xaf, 0x0f, 0xb9, 0x1c, 0xb6, 0x30, 0xa8, ++ 0xff, 0x61, 0xeb, 0x24, 0xfe, 0xde, 0xed, 0xb0, 0x99, 0xa1, 0xbe, 0x33, ++ 0x65, 0x32, 0x7f, 0xef, 0x71, 0xd8, 0xc2, 0xa1, 0xde, 0xb0, 0x55, 0xd4, ++ 0xbd, 0x8c, 0x0e, 0xb5, 0x77, 0x6f, 0xbd, 0x93, 0xf8, 0x4f, 0x09, 0x53, ++ 0xf6, 0x21, 0x3d, 0x94, 0x59, 0x12, 0x47, 0x03, 0xbb, 0x06, 0xf9, 0x58, ++ 0xb2, 0x0f, 0xe9, 0xe0, 0xa6, 0xf8, 0xd9, 0xa3, 0x91, 0x0e, 0x52, 0x52, ++ 0x1c, 0x84, 0x0f, 0xe3, 0x1d, 0xab, 0xf6, 0x61, 0xfd, 0x96, 0xf4, 0xcd, ++ 0xc6, 0x18, 0x07, 0x7a, 0x43, 0xf3, 0x56, 0xe3, 0x77, 0xa5, 0xb1, 0x15, ++ 0x46, 0xfc, 0x6e, 0x74, 0xff, 0xbb, 0x57, 0xe3, 0x77, 0x63, 0x53, 0x36, ++ 0x1a, 0x83, 0xbf, 0x1b, 0x97, 0xf5, 0xfc, 0x6a, 0xac, 0xdf, 0xea, 0xdc, ++ 0x6c, 0x44, 0x7d, 0x30, 0x05, 0xf9, 0x56, 0x5c, 0xa0, 0x1f, 0x59, 0x97, ++ 0xef, 0x25, 0x7f, 0x45, 0x3b, 0x01, 0xf1, 0x34, 0xb7, 0xb9, 0x9c, 0xf8, ++ 0x78, 0x4e, 0x53, 0x39, 0xf1, 0x71, 0x09, 0x97, 0xd2, 0xc9, 0x15, 0xf7, ++ 0xa3, 0x9f, 0xae, 0xa6, 0x49, 0xb1, 0x2b, 0x38, 0x8f, 0xc9, 0x4a, 0xe7, ++ 0x61, 0xbd, 0x02, 0x3a, 0x44, 0xf5, 0x45, 0xa0, 0x16, 0xe0, 0xb3, 0xfb, ++ 0xb6, 0xce, 0x8b, 0x5e, 0x05, 0xdf, 0xd5, 0x60, 0x7d, 0x28, 0xd5, 0x7f, ++ 0xb5, 0x2a, 0x34, 0xdf, 0x3d, 0x98, 0x12, 0x42, 0xbe, 0x7c, 0x28, 0xe8, ++ 0x14, 0xe5, 0x66, 0x05, 0x7c, 0xf7, 0x21, 0xd0, 0xcf, 0x2e, 0xa8, 0x67, ++ 0xe0, 0xfa, 0xc8, 0x7f, 0x38, 0xdb, 0x36, 0x9b, 0xfa, 0x73, 0xdb, 0x50, ++ 0xbe, 0xe6, 0xa6, 0x70, 0x39, 0x59, 0x20, 0xe4, 0xe6, 0x5c, 0x51, 0x2e, ++ 0x12, 0xcf, 0x3f, 0xb5, 0xba, 0xde, 0x47, 0xba, 0xfc, 0x38, 0x45, 0xd8, ++ 0x63, 0x5d, 0xe9, 0xfa, 0x13, 0x41, 0xb7, 0x0b, 0xf8, 0x3c, 0xba, 0xd0, ++ 0xb5, 0xf6, 0xbd, 0xa0, 0x6b, 0xbf, 0x94, 0x0f, 0x85, 0x1d, 0x09, 0x58, ++ 0xaf, 0x62, 0x1b, 0xc8, 0x4f, 0x78, 0xa5, 0xf8, 0xae, 0xc5, 0xc1, 0xf6, ++ 0x5b, 0x22, 0xc6, 0x49, 0x34, 0x50, 0xfc, 0x85, 0x3e, 0x4e, 0xa2, 0x92, ++ 0xf9, 0x78, 0x7f, 0x0d, 0xba, 0x38, 0x0b, 0xe6, 0x37, 0xd1, 0x79, 0x6c, ++ 0x53, 0xd0, 0x73, 0xe2, 0x47, 0xc2, 0xfe, 0xe8, 0xc1, 0xf9, 0xde, 0x54, ++ 0x64, 0xd6, 0x80, 0x9f, 0xdf, 0x76, 0xcf, 0xcf, 0xfe, 0x8d, 0xf0, 0xbf, ++ 0xcc, 0xba, 0xb5, 0xef, 0xc5, 0xba, 0x17, 0x33, 0x2f, 0xc5, 0xb5, 0xe9, ++ 0xd7, 0xc1, 0xdc, 0x71, 0x44, 0x5b, 0x4b, 0xad, 0x87, 0x69, 0x3f, 0xbb, ++ 0xae, 0xc7, 0x1f, 0x7a, 0x3d, 0x5d, 0xd6, 0xc1, 0xed, 0x77, 0x19, 0xc7, ++ 0x22, 0xfd, 0xf2, 0xa0, 0x07, 0xd9, 0x06, 0x16, 0x21, 0x1f, 0xb4, 0x31, ++ 0xf4, 0xdf, 0x04, 0xf3, 0x89, 0x23, 0x97, 0xe1, 0x13, 0x7a, 0x7e, 0xf4, ++ 0x5d, 0xf1, 0xb9, 0xcb, 0xf0, 0x9b, 0xa4, 0x81, 0x21, 0xf8, 0x8d, 0x8c, ++ 0xcf, 0xd2, 0x97, 0x52, 0x9f, 0x83, 0xba, 0x07, 0xe3, 0xf3, 0x3c, 0xaf, ++ 0x85, 0x93, 0x9f, 0xfe, 0xa4, 0xc3, 0x9d, 0x8d, 0xfd, 0xb4, 0x97, 0x76, ++ 0x7c, 0x63, 0x40, 0xfb, 0x2c, 0xd6, 0x4f, 0x78, 0xe6, 0xe9, 0xe7, 0x76, ++ 0xe2, 0x73, 0xc5, 0xc4, 0xcf, 0xe9, 0xe1, 0x49, 0x2a, 0xee, 0xdb, 0x29, ++ 0x83, 0xe7, 0x0f, 0xa8, 0x17, 0x0d, 0xdf, 0xf6, 0x24, 0xf1, 0x9d, 0x36, ++ 0x14, 0x0e, 0x40, 0x8f, 0x85, 0x50, 0x47, 0xbe, 0xe3, 0xed, 0x5b, 0x3e, ++ 0x18, 0xbf, 0x63, 0xe9, 0x1c, 0x7f, 0xda, 0x15, 0x2e, 0x17, 0x25, 0xdd, ++ 0x83, 0x3e, 0x48, 0xe5, 0x88, 0x81, 0x5c, 0x1e, 0x75, 0x2d, 0x39, 0x5d, ++ 0xc9, 0xb8, 0xc6, 0xf6, 0xcd, 0xdf, 0x26, 0x90, 0x1f, 0xeb, 0x0a, 0xf8, ++ 0xde, 0x1d, 0x1c, 0xc6, 0xa8, 0xc3, 0xfd, 0x1e, 0xe4, 0xf7, 0xc5, 0x11, ++ 0xa4, 0xf2, 0xb4, 0x2a, 0xac, 0x45, 0x01, 0xfd, 0xaf, 0xb5, 0xa4, 0x17, ++ 0xe9, 0x11, 0xad, 0x03, 0x4c, 0x46, 0x2c, 0xbf, 0x6b, 0x3b, 0xb1, 0x75, ++ 0x40, 0x2a, 0xf5, 0xaf, 0xb7, 0x17, 0x5b, 0xfb, 0x14, 0x5b, 0xf8, 0xb8, ++ 0x63, 0xc7, 0x61, 0xd9, 0x64, 0x72, 0x6f, 0x9a, 0x8d, 0x76, 0xd2, 0x10, ++ 0x33, 0xd9, 0x49, 0xef, 0x8a, 0x78, 0xc0, 0x09, 0x11, 0x3c, 0x7e, 0xea, ++ 0x5d, 0x3c, 0x1f, 0x86, 0x76, 0x13, 0x8e, 0x5f, 0x8c, 0x45, 0xf9, 0xa5, ++ 0xb7, 0x37, 0x5b, 0x0f, 0x4e, 0x2f, 0x75, 0xe4, 0x74, 0xb5, 0x3b, 0x61, ++ 0x9d, 0xa3, 0x71, 0x9d, 0x95, 0x9f, 0x19, 0xee, 0xc7, 0x67, 0xd7, 0x6a, ++ 0x87, 0x56, 0xae, 0xfc, 0x86, 0x19, 0x63, 0x40, 0x6e, 0xaf, 0xbc, 0xc8, ++ 0x8c, 0x05, 0x57, 0x63, 0x97, 0x32, 0x15, 0xd9, 0x45, 0xfe, 0x51, 0xe7, ++ 0x9b, 0x58, 0x16, 0x7d, 0xee, 0x8b, 0xce, 0x71, 0xa0, 0xfd, 0x29, 0xf5, ++ 0x07, 0x61, 0x9f, 0x5e, 0x21, 0x0e, 0xa9, 0xb8, 0x83, 0xeb, 0x0b, 0xa3, ++ 0x2e, 0xb2, 0x74, 0x63, 0x21, 0xfa, 0x99, 0x7a, 0xd0, 0xf9, 0x8d, 0x52, ++ 0xfc, 0x27, 0x6e, 0xb7, 0x8a, 0x52, 0x9e, 0x8b, 0x0c, 0xe7, 0x53, 0x60, ++ 0x33, 0x0d, 0x56, 0xaf, 0x29, 0x49, 0x13, 0x87, 0x14, 0x6f, 0x84, 0x72, ++ 0xba, 0xea, 0x1f, 0x8c, 0xf5, 0x36, 0xe6, 0xa3, 0x73, 0x12, 0xbd, 0x3d, ++ 0xfb, 0x96, 0xf0, 0x43, 0x81, 0x5d, 0xfb, 0x0b, 0xc4, 0xdb, 0x35, 0x22, ++ 0x3e, 0x09, 0x76, 0x24, 0x06, 0xf1, 0x77, 0xcc, 0x4f, 0x3f, 0x9a, 0xf9, ++ 0x33, 0xe2, 0x03, 0xe1, 0xa4, 0x0f, 0x75, 0xda, 0xb5, 0xbb, 0x0d, 0x14, ++ 0x5f, 0xd0, 0x68, 0x74, 0xf5, 0x1c, 0x81, 0x76, 0xed, 0xca, 0x81, 0xce, ++ 0x55, 0x50, 0xff, 0xd4, 0x17, 0xf7, 0xeb, 0x57, 0xa1, 0xac, 0xb1, 0x7f, ++ 0x43, 0x70, 0x93, 0xf4, 0x5b, 0xb9, 0xf2, 0x3c, 0xc1, 0x53, 0xd6, 0x5b, ++ 0x85, 0xdf, 0x77, 0x43, 0x18, 0xc8, 0x1f, 0x28, 0x2b, 0xff, 0xa3, 0x92, ++ 0x1c, 0xaa, 0x64, 0x6c, 0x1d, 0xed, 0x1b, 0x7b, 0xc3, 0xb4, 0x2c, 0x48, ++ 0x2e, 0xb2, 0x86, 0xaf, 0x3a, 0xe1, 0x9f, 0x0b, 0x7c, 0xaf, 0x02, 0x01, ++ 0x48, 0x76, 0xd6, 0xc8, 0x49, 0x2e, 0x68, 0x57, 0x21, 0xec, 0x0f, 0xe6, ++ 0x79, 0x9d, 0xd7, 0x85, 0xdd, 0x05, 0x16, 0xc5, 0x24, 0x17, 0xf4, 0x5b, ++ 0x11, 0x27, 0xda, 0xb3, 0x87, 0xf9, 0xfb, 0x01, 0xf2, 0xfd, 0x23, 0xfc, ++ 0xfd, 0x40, 0xd9, 0xdf, 0xf9, 0x89, 0xf4, 0xbe, 0x8f, 0xac, 0x8b, 0xfe, ++ 0x32, 0x64, 0xfd, 0x4f, 0xbc, 0x9e, 0x28, 0xc7, 0x6b, 0xe5, 0xf5, 0x6c, ++ 0x59, 0x0f, 0xe7, 0xfd, 0xd9, 0x78, 0xfb, 0x97, 0x06, 0x36, 0x4c, 0xf2, ++ 0x64, 0x05, 0xf8, 0xfd, 0x9e, 0x81, 0x42, 0x3e, 0xe6, 0xb1, 0x3c, 0x11, ++ 0x97, 0xb3, 0x77, 0xe0, 0xe5, 0xe3, 0x51, 0xb4, 0xef, 0x85, 0x7c, 0x98, ++ 0xf5, 0x8c, 0xea, 0x31, 0xe5, 0xe2, 0xfe, 0x8c, 0x8f, 0xf8, 0x33, 0xd2, ++ 0x77, 0x83, 0x42, 0xb1, 0x73, 0x95, 0xf7, 0x86, 0x91, 0xbf, 0xfb, 0x4c, ++ 0x74, 0x43, 0xce, 0xf2, 0x20, 0x7b, 0x45, 0xc6, 0xaf, 0x94, 0x97, 0xd9, ++ 0x5c, 0xa8, 0xff, 0x55, 0xbd, 0x98, 0xb6, 0x45, 0x15, 0xf1, 0x3c, 0xa8, ++ 0x7f, 0xfc, 0xcb, 0xc1, 0xed, 0x98, 0x31, 0xaa, 0x95, 0xce, 0x27, 0xce, ++ 0x3d, 0xc8, 0xf9, 0x7e, 0x77, 0xfa, 0xdb, 0x82, 0x95, 0xaf, 0x6a, 0xf6, ++ 0xb3, 0xcb, 0x7b, 0x55, 0xe1, 0xf6, 0x38, 0x1e, 0xdc, 0xc1, 0x78, 0x67, ++ 0x1f, 0xea, 0xbd, 0x99, 0xec, 0x8b, 0x14, 0x1f, 0x9d, 0x9b, 0x7f, 0x2a, ++ 0xf8, 0x5d, 0x2f, 0xe0, 0xad, 0xc5, 0xd1, 0x81, 0x78, 0xb1, 0xd8, 0x64, ++ 0xe6, 0x42, 0x7b, 0x35, 0xf6, 0x25, 0xe0, 0xcf, 0xb8, 0xc7, 0x9f, 0xfb, ++ 0x88, 0x1f, 0x2f, 0x78, 0x89, 0xfb, 0x7f, 0xab, 0x1e, 0x7d, 0x93, 0xe4, ++ 0xde, 0x1c, 0xd5, 0x41, 0xfe, 0xdc, 0xb1, 0x59, 0xee, 0x2f, 0x10, 0x6f, ++ 0xdb, 0x6c, 0x3e, 0xf2, 0x2b, 0x2e, 0x58, 0xf9, 0x1a, 0xcd, 0xeb, 0x9b, ++ 0x0c, 0xa1, 0x37, 0xd8, 0x3b, 0xb2, 0x82, 0xe1, 0x79, 0xb6, 0x2b, 0xfc, ++ 0xbf, 0xba, 0x02, 0xfc, 0xbf, 0xfa, 0x21, 0xe1, 0xaf, 0xf7, 0x3b, 0x2f, ++ 0xb1, 0xee, 0xa3, 0xf5, 0x2e, 0xb9, 0xc6, 0xb8, 0xb6, 0x36, 0x1b, 0x3f, ++ 0x17, 0x75, 0x8a, 0x7d, 0x3a, 0x6e, 0x70, 0x0c, 0x16, 0xf0, 0x8a, 0x48, ++ 0x45, 0xff, 0xf9, 0x7c, 0x5f, 0x6a, 0x94, 0x8a, 0x41, 0xc7, 0xbe, 0x5e, ++ 0x3c, 0x5e, 0xe9, 0x9d, 0x22, 0xb4, 0x8b, 0xce, 0xd5, 0xda, 0x18, 0xee, ++ 0xfb, 0xf4, 0xe5, 0x7f, 0xcb, 0x71, 0x87, 0xf0, 0xfb, 0xea, 0xed, 0x81, ++ 0x19, 0x38, 0x66, 0x5c, 0x00, 0x5e, 0x7d, 0x52, 0x85, 0x1e, 0x14, 0x80, ++ 0xef, 0x00, 0x1c, 0xef, 0x32, 0xf0, 0xd5, 0xbe, 0xff, 0x9e, 0xe1, 0xdb, ++ 0xdb, 0xe8, 0x37, 0x39, 0xf1, 0x1c, 0xf5, 0x28, 0xa3, 0x7e, 0x06, 0xfb, ++ 0x8e, 0x9b, 0x82, 0xe3, 0x62, 0x46, 0xa4, 0x72, 0xbc, 0xec, 0xd9, 0xc4, ++ 0xcf, 0x8d, 0xf4, 0xf1, 0x5e, 0x23, 0x52, 0x6d, 0xdc, 0xef, 0x2d, 0xce, ++ 0x67, 0xaa, 0x26, 0xbe, 0x33, 0x1c, 0xcf, 0x67, 0x24, 0x3d, 0x8c, 0x8a, ++ 0x60, 0x0d, 0xe8, 0x6f, 0x07, 0xbc, 0x76, 0x0a, 0xbc, 0x76, 0x22, 0x5e, ++ 0x4b, 0xfc, 0x0d, 0x9c, 0xd3, 0xc0, 0x77, 0x21, 0xe8, 0x2b, 0x80, 0xbf, ++ 0x5a, 0xb8, 0x8e, 0x4e, 0xed, 0x82, 0xb7, 0xe3, 0xae, 0x00, 0xd7, 0x71, ++ 0x3f, 0x24, 0x5c, 0x1b, 0x41, 0x1f, 0xa6, 0x73, 0xcd, 0xdd, 0xe1, 0xe4, ++ 0x4f, 0xd1, 0xc3, 0x79, 0xa9, 0x80, 0xab, 0x84, 0xf7, 0xbd, 0x57, 0x80, ++ 0xf3, 0xbd, 0xdf, 0x13, 0x9c, 0xef, 0x4d, 0x75, 0x68, 0xfc, 0x11, 0x12, ++ 0xde, 0xdd, 0xc9, 0x27, 0xfd, 0xfe, 0xc8, 0x79, 0x87, 0xa0, 0xd3, 0xa2, ++ 0xeb, 0xa1, 0xd3, 0x4b, 0x69, 0xdc, 0x4e, 0x64, 0x46, 0x3f, 0xc5, 0x99, ++ 0xea, 0xf7, 0xbd, 0xbe, 0x2b, 0x3d, 0xad, 0xbd, 0xc2, 0xbe, 0xaf, 0xfd, ++ 0x21, 0xf7, 0x5d, 0x0f, 0x37, 0x7d, 0x59, 0x29, 0xce, 0x3b, 0xf5, 0xcf, ++ 0xb7, 0xa5, 0x76, 0xcb, 0xef, 0xbe, 0x13, 0x38, 0xfe, 0x6f, 0xf3, 0xa7, ++ 0xcf, 0xa8, 0xdd, 0xab, 0x79, 0x3f, 0x6b, 0xe5, 0x41, 0xcd, 0xfb, 0xd9, ++ 0x9e, 0xf7, 0x34, 0xf5, 0xe1, 0x7e, 0x5f, 0x19, 0xa2, 0xb9, 0xf4, 0x8f, ++ 0x8f, 0x3c, 0xd5, 0xf1, 0x26, 0xd6, 0xaf, 0xd7, 0xcf, 0xde, 0x9d, 0x7f, ++ 0x7d, 0xc2, 0x0b, 0x0b, 0x0d, 0x78, 0xfe, 0x56, 0xec, 0xe3, 0xfe, 0xfd, ++ 0x05, 0xe9, 0xee, 0x7f, 0xa5, 0x02, 0x9c, 0xdf, 0x35, 0x78, 0xeb, 0x6d, ++ 0x00, 0xd7, 0x1b, 0x8f, 0x35, 0xa8, 0x74, 0x1e, 0xe6, 0xcd, 0xa3, 0x73, ++ 0xc0, 0xe5, 0x62, 0x8e, 0xe7, 0x87, 0xff, 0xf3, 0x93, 0x9f, 0x01, 0xde, ++ 0x9c, 0x67, 0x66, 0xf2, 0x7f, 0xb6, 0xec, 0xcd, 0x30, 0x3a, 0xb2, 0xbb, ++ 0xe2, 0x41, 0xc9, 0x05, 0x95, 0xb9, 0x82, 0xf4, 0xc4, 0x12, 0x4b, 0x94, ++ 0x11, 0xf5, 0xa9, 0x12, 0xd0, 0x94, 0x43, 0xe1, 0xcd, 0x25, 0x81, 0x37, ++ 0x14, 0x0f, 0x04, 0xf4, 0x3e, 0xd5, 0xc2, 0xc2, 0x62, 0x81, 0xce, 0xa7, ++ 0x4e, 0x55, 0x28, 0xfe, 0x69, 0x2a, 0xe3, 0xf1, 0xd4, 0x50, 0xb6, 0xb8, ++ 0xe1, 0xfd, 0x04, 0x23, 0x6b, 0x31, 0x43, 0xbd, 0xc2, 0x6a, 0x6c, 0x31, ++ 0xd3, 0xb9, 0x1f, 0xcf, 0x77, 0x98, 0xc2, 0xa7, 0xc9, 0xcc, 0x46, 0xe6, ++ 0xc1, 0xf7, 0x2c, 0x36, 0x86, 0xec, 0xe0, 0xc9, 0xf8, 0x10, 0xe6, 0xab, ++ 0xba, 0x54, 0x8a, 0x67, 0x9b, 0x52, 0xcc, 0xcf, 0x0b, 0xef, 0xb2, 0x36, ++ 0x84, 0xa1, 0x3c, 0xbd, 0xf3, 0xc0, 0x7d, 0x67, 0x7f, 0x06, 0xef, 0xd9, ++ 0x6a, 0x4f, 0x11, 0x8f, 0xd7, 0x96, 0xf9, 0x6b, 0x1f, 0x1b, 0xae, 0xe5, ++ 0x1c, 0xf0, 0x52, 0x2a, 0xa7, 0xf3, 0x76, 0x45, 0x9c, 0x2b, 0x2b, 0x61, ++ 0x4e, 0x8c, 0x6f, 0xd5, 0x7f, 0xf7, 0x7e, 0x2a, 0xf7, 0x97, 0x4e, 0x50, ++ 0x57, 0xa9, 0x18, 0xff, 0xd2, 0xf1, 0x1e, 0x23, 0xbd, 0x5b, 0xd2, 0x1d, ++ 0xac, 0xef, 0x80, 0x39, 0x9f, 0xe7, 0x67, 0x0c, 0xc5, 0x75, 0xb2, 0xb0, ++ 0x96, 0xb4, 0x48, 0xd4, 0x9f, 0x37, 0x96, 0x61, 0xfb, 0xca, 0xc3, 0x0e, ++ 0x82, 0x4b, 0x4d, 0xf1, 0xaa, 0x1c, 0xdc, 0xc7, 0x9a, 0xd1, 0xca, 0x67, ++ 0xe6, 0x9c, 0x80, 0x7d, 0x53, 0xb3, 0xf2, 0x6b, 0xd2, 0xd3, 0xc7, 0xa8, ++ 0x3b, 0xea, 0xb1, 0xfd, 0xb9, 0xa3, 0xdc, 0x35, 0x7e, 0x63, 0xab, 0x47, ++ 0x45, 0x7b, 0x25, 0xe0, 0xbf, 0xf4, 0xcf, 0x44, 0xba, 0xbc, 0x92, 0x1d, ++ 0x24, 0xe7, 0x7d, 0xac, 0xae, 0x85, 0xf0, 0xe9, 0x93, 0xba, 0x03, 0x54, ++ 0xbe, 0x3b, 0xf2, 0x4f, 0x45, 0xa8, 0x67, 0xf8, 0xeb, 0x7c, 0x21, 0xfd, ++ 0x97, 0xd7, 0xeb, 0x2f, 0x90, 0x7e, 0x02, 0xe9, 0x37, 0x90, 0x7c, 0xe0, ++ 0xd3, 0x7b, 0xcb, 0x7a, 0x23, 0x5e, 0x66, 0xa4, 0x09, 0x3d, 0xd0, 0xa2, ++ 0xf4, 0x43, 0xbe, 0xc0, 0x8c, 0xbc, 0x94, 0xfc, 0x32, 0x37, 0xad, 0x8b, ++ 0x5c, 0x2d, 0x48, 0xbb, 0xbc, 0x3e, 0xa8, 0x7d, 0xff, 0x3d, 0xf3, 0xd7, ++ 0xab, 0xc5, 0xf3, 0xca, 0x78, 0x2e, 0x17, 0xf5, 0xf8, 0xad, 0xc7, 0x6b, ++ 0x89, 0xcf, 0xf0, 0x59, 0x91, 0x02, 0xe3, 0xde, 0x05, 0xfa, 0x1e, 0xca, ++ 0xd5, 0x69, 0xcc, 0x93, 0x5d, 0x09, 0x7c, 0x76, 0xea, 0xc2, 0x0d, 0x61, ++ 0xc3, 0x94, 0xeb, 0xc7, 0xeb, 0x25, 0xd6, 0xcf, 0x13, 0x58, 0x88, 0x3c, ++ 0x95, 0x6b, 0xe7, 0xe7, 0x0e, 0xda, 0x47, 0xb5, 0x4c, 0x25, 0xfb, 0x40, ++ 0xc6, 0x2b, 0xc8, 0x7d, 0x58, 0x90, 0xd6, 0x45, 0x2e, 0x2e, 0xb9, 0xc2, ++ 0xbe, 0x2d, 0xf9, 0x21, 0xf7, 0xad, 0xab, 0x5c, 0xfb, 0x7c, 0xe6, 0xf5, ++ 0xc9, 0x35, 0xa6, 0xc9, 0xeb, 0xb8, 0xbf, 0x2b, 0xbe, 0x3e, 0x90, 0x76, ++ 0x79, 0x7d, 0x40, 0xfb, 0xfe, 0x7b, 0x5e, 0x77, 0x50, 0xfe, 0xcc, 0x4c, ++ 0xd5, 0x10, 0xc8, 0x17, 0xc1, 0x78, 0x62, 0x8c, 0x6b, 0x6c, 0xf7, 0xf2, ++ 0x7c, 0xc8, 0x45, 0x89, 0x1b, 0x22, 0x29, 0x38, 0xb3, 0xb8, 0x23, 0x12, ++ 0xf5, 0xc6, 0xc5, 0x7b, 0x54, 0xc2, 0x43, 0x66, 0x74, 0x19, 0xfb, 0x00, ++ 0xbe, 0x2e, 0x14, 0xf8, 0xda, 0xca, 0x5a, 0x3e, 0x40, 0x7c, 0x5c, 0x38, ++ 0x7c, 0x21, 0xe5, 0xd1, 0x2d, 0x7a, 0x3c, 0x74, 0x5c, 0x71, 0xb5, 0x68, ++ 0xbf, 0xc4, 0xda, 0x68, 0xc2, 0x75, 0x2e, 0xd9, 0xaa, 0x6d, 0x57, 0x2d, ++ 0xe2, 0x8a, 0x2b, 0x77, 0x68, 0xfd, 0xa2, 0xd5, 0xc3, 0x6f, 0x3a, 0x89, ++ 0xfd, 0x56, 0xeb, 0xe2, 0x79, 0x76, 0xa6, 0x89, 0xf8, 0xe1, 0x7c, 0x96, ++ 0xcf, 0xe3, 0x2e, 0xb4, 0xfa, 0xa9, 0xbe, 0x6c, 0xab, 0x63, 0x1a, 0x7f, ++ 0x65, 0xdb, 0xc5, 0x3a, 0xf2, 0x07, 0xbc, 0xf4, 0xbb, 0xd6, 0x87, 0x3d, ++ 0xfd, 0x83, 0xec, 0xff, 0xae, 0x78, 0xbb, 0xf7, 0x0a, 0xfb, 0xb7, 0xf7, ++ 0x87, 0xdc, 0x3f, 0x3d, 0xde, 0xaa, 0xb6, 0xad, 0x94, 0x57, 0x75, 0xad, ++ 0x78, 0xfb, 0xd3, 0x41, 0xae, 0x0f, 0x70, 0xde, 0x92, 0x1f, 0x4f, 0x47, ++ 0xde, 0x04, 0xe3, 0x4e, 0x7f, 0xd5, 0xec, 0xf5, 0xe0, 0xf9, 0x68, 0x91, ++ 0x83, 0xfb, 0x37, 0x15, 0x6f, 0x3d, 0x9e, 0xb7, 0xb5, 0x7f, 0xcb, 0xc8, ++ 0x7f, 0x34, 0x47, 0xf8, 0x39, 0xbb, 0xcb, 0x4b, 0x97, 0xf1, 0x06, 0x43, ++ 0x0e, 0x7b, 0xeb, 0x79, 0xbc, 0x81, 0x4b, 0xc5, 0x3c, 0xd1, 0xc1, 0x07, ++ 0xca, 0xcb, 0xf0, 0xb8, 0xa2, 0xe0, 0x9d, 0x5a, 0xd2, 0x47, 0xba, 0x3d, ++ 0xb7, 0x92, 0xf9, 0x55, 0x22, 0x7e, 0xe8, 0x6a, 0xf9, 0x9a, 0xf4, 0xeb, ++ 0x0d, 0x3e, 0x55, 0x4b, 0x7a, 0x96, 0xd3, 0x67, 0x27, 0x7d, 0x68, 0xe8, ++ 0x85, 0x86, 0x37, 0x51, 0x3e, 0x7e, 0x57, 0xfe, 0x6e, 0x29, 0x0f, 0x73, ++ 0x63, 0x38, 0xdc, 0x0a, 0xfd, 0xe5, 0xa4, 0xe7, 0xb5, 0x85, 0xb5, 0x14, ++ 0x7d, 0x88, 0x7a, 0xc2, 0xcb, 0xe1, 0x21, 0xf5, 0x84, 0x1e, 0xe9, 0x5c, ++ 0x4f, 0x98, 0xe4, 0x99, 0x1d, 0xc6, 0xf3, 0x0d, 0xbb, 0x9c, 0x07, 0xf6, ++ 0x48, 0xc7, 0xf3, 0x40, 0xc1, 0xff, 0x0d, 0x16, 0x57, 0x18, 0xc2, 0x69, ++ 0x8c, 0xda, 0xfa, 0xeb, 0x3b, 0x10, 0x7f, 0x7c, 0x2a, 0xf9, 0xf7, 0x56, ++ 0xfc, 0xfc, 0xfd, 0x3f, 0x3c, 0xe6, 0xb8, 0xb2, 0xdd, 0x5f, 0x63, 0x3f, ++ 0x4f, 0x7a, 0x43, 0x77, 0xfa, 0x7f, 0x8d, 0x81, 0xe7, 0x5d, 0xe4, 0x97, ++ 0x39, 0x28, 0xce, 0x0f, 0xed, 0x29, 0xf4, 0xef, 0x49, 0x7f, 0x9f, 0xbe, ++ 0x7d, 0xf1, 0xa0, 0xd2, 0xfe, 0xe9, 0x71, 0xe4, 0xaf, 0xf6, 0xb9, 0x70, ++ 0x3e, 0x9b, 0xf8, 0x7c, 0xba, 0xdb, 0x9f, 0x9a, 0x95, 0x5f, 0x69, 0xfc, ++ 0x8b, 0xdd, 0x8d, 0x5f, 0xb3, 0xa7, 0xc8, 0x3e, 0x27, 0x88, 0x0e, 0x66, ++ 0xa4, 0x2b, 0x12, 0xcf, 0xed, 0x27, 0x2c, 0x81, 0xfd, 0xbd, 0x5a, 0x3c, ++ 0x18, 0xd1, 0x31, 0x55, 0xa3, 0xff, 0xfc, 0xff, 0x6e, 0x57, 0x4c, 0x50, ++ 0x41, 0xb5, 0x04, 0xf9, 0x99, 0xad, 0x78, 0xb9, 0xfe, 0xca, 0xb8, 0x1e, ++ 0x3b, 0x9d, 0xf9, 0xa8, 0x9c, 0xc9, 0x3a, 0xa8, 0x74, 0x33, 0x1e, 0x7f, ++ 0x3f, 0x87, 0x39, 0xa9, 0x9c, 0x27, 0xf2, 0x98, 0xdf, 0xce, 0x70, 0x57, ++ 0xa4, 0x53, 0x3c, 0x4c, 0x47, 0x2f, 0x8a, 0x9f, 0x7c, 0xf1, 0x7f, 0xb2, ++ 0x10, 0x6f, 0xce, 0x8e, 0x1c, 0xb6, 0x01, 0x63, 0xed, 0xbe, 0x2f, 0x3d, ++ 0xae, 0x3d, 0xcf, 0x41, 0xe3, 0xb7, 0xef, 0xfe, 0x9f, 0x04, 0x8c, 0x83, ++ 0xb9, 0x12, 0x5f, 0xd8, 0x10, 0xef, 0x9a, 0x97, 0x1e, 0xe2, 0x3c, 0xe8, ++ 0x2f, 0x25, 0x2a, 0x9d, 0xb7, 0xb0, 0x53, 0x8f, 0x91, 0x9c, 0xa8, 0x10, ++ 0xb7, 0x30, 0xb0, 0xd1, 0xfc, 0x1c, 0xed, 0x5f, 0x8e, 0x44, 0xa2, 0x9b, ++ 0x00, 0x5f, 0xec, 0xbd, 0x59, 0xf2, 0x45, 0x3c, 0x9f, 0xcd, 0xfe, 0xcc, ++ 0xc0, 0xe3, 0x49, 0x16, 0x2b, 0xde, 0x81, 0xd0, 0xb4, 0xc9, 0x6f, 0x20, ++ 0xd2, 0xca, 0x9e, 0x9f, 0xe8, 0x55, 0xb1, 0xde, 0xc8, 0xdf, 0x67, 0x57, ++ 0x45, 0x79, 0x15, 0xa8, 0x67, 0x0f, 0x09, 0xe7, 0xef, 0xef, 0x8e, 0xf2, ++ 0xa2, 0x1f, 0x7d, 0x06, 0xf3, 0x13, 0x3d, 0xce, 0x62, 0x8c, 0xf8, 0xdd, ++ 0x6c, 0xc6, 0xf9, 0xde, 0x5c, 0xe6, 0xe2, 0xf9, 0x0e, 0xac, 0x23, 0x09, ++ 0xf5, 0xb0, 0xf9, 0xcd, 0x16, 0x1e, 0xef, 0xcf, 0xfc, 0x29, 0xc8, 0xdf, ++ 0x73, 0xba, 0xb1, 0x7f, 0x5a, 0x04, 0x9d, 0xe7, 0x26, 0x71, 0x7e, 0x9e, ++ 0x5b, 0xaa, 0xf5, 0x53, 0xac, 0x49, 0xe7, 0x7c, 0xfc, 0x64, 0x46, 0xe9, ++ 0x67, 0x48, 0x4f, 0x67, 0xd2, 0x5d, 0x6b, 0xb1, 0xcc, 0x8d, 0xf6, 0xad, ++ 0x7f, 0xb8, 0x90, 0xfc, 0xf6, 0x0c, 0xed, 0x87, 0x93, 0x43, 0x7e, 0x42, ++ 0xe7, 0x8d, 0xf2, 0xbb, 0xc8, 0x41, 0xa5, 0x0f, 0x62, 0xbb, 0x9d, 0x0a, ++ 0x8f, 0x4f, 0xf7, 0xec, 0x31, 0x53, 0x7c, 0x04, 0x7c, 0xd1, 0xab, 0x3c, ++ 0x28, 0xae, 0xff, 0xed, 0x8c, 0xb2, 0x5f, 0x61, 0xbb, 0x47, 0x11, 0xf6, ++ 0x45, 0xdd, 0xc3, 0x15, 0xbe, 0xd3, 0xe4, 0xcd, 0x06, 0xe8, 0xc9, 0xc3, ++ 0xe7, 0x8f, 0x36, 0x17, 0xf9, 0xdf, 0xe1, 0x41, 0x31, 0x8d, 0x4b, 0xf5, ++ 0xdf, 0x3f, 0x3d, 0x61, 0xf2, 0x6a, 0x2b, 0xf9, 0xf8, 0x3d, 0xa8, 0xf7, ++ 0x46, 0x0e, 0x72, 0x3f, 0x85, 0xfb, 0x9a, 0x6b, 0x62, 0xcc, 0x8a, 0xf3, ++ 0x7f, 0xc2, 0xec, 0xdd, 0x42, 0xfa, 0x69, 0x6d, 0x02, 0xfa, 0x2b, 0x17, ++ 0x3e, 0x69, 0x36, 0xa0, 0xde, 0xf0, 0x11, 0x88, 0x5b, 0xcc, 0x43, 0xf9, ++ 0x6b, 0x9d, 0x85, 0xca, 0xbf, 0x81, 0x1d, 0x8c, 0xe5, 0xa7, 0x60, 0x07, ++ 0x63, 0xf9, 0x19, 0xd8, 0xc1, 0x58, 0xfe, 0x1d, 0xec, 0x60, 0x2c, 0xe7, ++ 0x5f, 0xc8, 0x03, 0x61, 0xc1, 0xd8, 0xd8, 0x0c, 0x57, 0x33, 0xc7, 0xef, ++ 0xd0, 0xf9, 0x59, 0xbb, 0x05, 0x3c, 0x3b, 0xc7, 0xdf, 0x63, 0xa2, 0xf1, ++ 0x4f, 0x66, 0xb8, 0x09, 0xbe, 0x9d, 0xfb, 0xfd, 0x32, 0xf3, 0xe2, 0xa1, ++ 0xce, 0xce, 0xa8, 0x8e, 0xbe, 0xd1, 0x97, 0xc1, 0xb7, 0xee, 0xf9, 0x8c, ++ 0x47, 0xd8, 0x83, 0xa1, 0xe3, 0xb9, 0x9e, 0x15, 0xf3, 0xc8, 0x69, 0x34, ++ 0x92, 0x7c, 0xcf, 0x69, 0xf2, 0x47, 0x2e, 0x08, 0x6a, 0xf7, 0x76, 0xba, ++ 0x89, 0xde, 0x67, 0xef, 0xfe, 0x9c, 0xf2, 0x4f, 0xdb, 0xec, 0x9d, 0xf0, ++ 0x75, 0x29, 0xb0, 0xe4, 0x09, 0x06, 0x5e, 0x7f, 0xfb, 0xe9, 0x79, 0x93, ++ 0x57, 0x67, 0xe1, 0xfc, 0x5d, 0x9f, 0xe1, 0xba, 0x81, 0xbe, 0xff, 0x82, ++ 0x65, 0x4e, 0xd3, 0xfb, 0xbf, 0xc2, 0xfc, 0x1f, 0xe8, 0x9f, 0xe2, 0x0e, ++ 0xda, 0x95, 0x8e, 0xdf, 0x90, 0x1d, 0xa0, 0x5b, 0x87, 0x1e, 0x0e, 0x72, ++ 0x5d, 0x3b, 0xa3, 0x7c, 0xeb, 0xf1, 0xfb, 0x9d, 0xbb, 0x93, 0x70, 0x25, ++ 0xc0, 0x6f, 0x18, 0xa7, 0x1b, 0xc4, 0x23, 0x25, 0xd4, 0x7a, 0x57, 0xd1, ++ 0x7c, 0x6f, 0x37, 0x77, 0x14, 0x62, 0x5e, 0xcb, 0xed, 0x97, 0xd4, 0x90, ++ 0x71, 0xc6, 0x27, 0x33, 0x4a, 0x08, 0xce, 0x3f, 0x97, 0xf8, 0x26, 0xe1, ++ 0x24, 0xf6, 0xeb, 0x7a, 0xe9, 0xba, 0xf3, 0xfc, 0x5b, 0xe0, 0x29, 0x93, ++ 0xf7, 0x77, 0x20, 0xef, 0x74, 0xa0, 0x1c, 0xba, 0x18, 0x89, 0xfa, 0x5e, ++ 0x85, 0x38, 0xdf, 0x6f, 0x6a, 0x4c, 0x79, 0x17, 0xd7, 0xe7, 0x39, 0xa0, ++ 0xb2, 0x81, 0x0e, 0xc2, 0x5f, 0x0d, 0xdd, 0xc5, 0x66, 0xf0, 0xfd, 0x91, ++ 0x65, 0xf6, 0x1e, 0x53, 0x39, 0xee, 0xd3, 0xce, 0x3d, 0x27, 0x52, 0xe6, ++ 0x59, 0x69, 0x5f, 0x52, 0xe6, 0x43, 0x7b, 0x63, 0xc6, 0x40, 0x8d, 0xff, ++ 0x31, 0x7b, 0xc8, 0xb7, 0xff, 0xfd, 0x70, 0x2c, 0xb5, 0xb7, 0xe3, 0x50, ++ 0x77, 0xb2, 0xcd, 0x63, 0x30, 0xfe, 0x64, 0x9a, 0x65, 0xef, 0x1f, 0x71, ++ 0x49, 0x33, 0xec, 0x9f, 0x8d, 0xc1, 0xf8, 0x93, 0x59, 0xf1, 0xca, 0x7e, ++ 0x2c, 0x67, 0x3b, 0x12, 0xc7, 0x62, 0xdc, 0x89, 0x8c, 0x8f, 0x9f, 0x9b, ++ 0x5e, 0xb2, 0x1f, 0x49, 0xe9, 0x56, 0x67, 0x05, 0xe9, 0x69, 0x25, 0xc8, ++ 0x5c, 0x82, 0xe4, 0x41, 0x99, 0x25, 0x02, 0x0f, 0x05, 0x3b, 0xeb, 0x63, ++ 0xec, 0x31, 0x9a, 0xfa, 0x4d, 0xf1, 0xfd, 0x34, 0xed, 0xc7, 0x3b, 0x92, ++ 0x35, 0xef, 0x6f, 0x49, 0xcf, 0xd4, 0xbc, 0x97, 0xe3, 0xde, 0xea, 0x2c, ++ 0xd0, 0xb4, 0xcb, 0x8d, 0xee, 0x48, 0x42, 0xfb, 0x0c, 0xd6, 0x41, 0xf4, ++ 0xc0, 0xb6, 0xa9, 0x14, 0xa7, 0x97, 0xbd, 0xfb, 0xf0, 0xcd, 0x99, 0x50, ++ 0x9f, 0xb0, 0x7d, 0x8a, 0x13, 0xd5, 0x92, 0x9d, 0xe2, 0xfd, 0x84, 0x5d, ++ 0x65, 0x5e, 0xdc, 0x8f, 0x76, 0x80, 0xa7, 0x09, 0x14, 0xa8, 0x53, 0xc5, ++ 0x0f, 0xfc, 0xe6, 0x61, 0xec, 0x4c, 0xa7, 0xff, 0x57, 0xee, 0x79, 0x6a, ++ 0xbf, 0xcb, 0x71, 0x0d, 0xfa, 0x7f, 0x37, 0x7a, 0xbf, 0xe4, 0xb3, 0x4b, ++ 0x9b, 0x2d, 0x45, 0xc8, 0x67, 0xaf, 0xd6, 0x0e, 0xd0, 0xef, 0x4f, 0x7e, ++ 0x86, 0xd6, 0x2e, 0xe8, 0x0e, 0x6f, 0x3a, 0xe9, 0x42, 0x71, 0x70, 0xbc, ++ 0x39, 0xa8, 0xb2, 0x6d, 0x21, 0xf0, 0x06, 0x23, 0x52, 0x39, 0x1e, 0xf2, ++ 0x72, 0xc2, 0x21, 0x9e, 0x3f, 0x76, 0xad, 0xfc, 0xec, 0x0b, 0xe4, 0x67, ++ 0x31, 0x01, 0xfa, 0xe8, 0x2c, 0x75, 0x7e, 0xb9, 0x5c, 0x93, 0xf3, 0xdd, ++ 0xe5, 0xe8, 0xa7, 0xff, 0xb3, 0xca, 0x28, 0x1f, 0x4f, 0xe4, 0xf5, 0x2d, ++ 0xc0, 0xdf, 0xd5, 0x00, 0xbe, 0xb3, 0x79, 0x9b, 0xef, 0xef, 0x13, 0x4b, ++ 0xcf, 0x3d, 0xa8, 0xe7, 0x62, 0x7e, 0xa9, 0x0b, 0xfa, 0x5f, 0x92, 0x21, ++ 0xf4, 0xa7, 0xca, 0xbd, 0xf7, 0xf7, 0x29, 0x0c, 0xbc, 0x67, 0x2b, 0x3e, ++ 0xd3, 0xb4, 0x67, 0xf7, 0x2a, 0x6b, 0x34, 0xf5, 0xd5, 0x89, 0xda, 0xfa, ++ 0x83, 0x25, 0x6b, 0x82, 0xbf, 0xef, 0x8e, 0x2f, 0x2e, 0xd8, 0x34, 0xdb, ++ 0xe4, 0xa6, 0xfc, 0x4f, 0xc5, 0xe5, 0x0d, 0xc1, 0x1f, 0xe4, 0x7c, 0xc6, ++ 0xbc, 0x11, 0x4e, 0x71, 0x7d, 0xb7, 0x61, 0xbc, 0x0a, 0x3c, 0xaa, 0x2e, ++ 0x7c, 0xcf, 0x88, 0xe7, 0xb0, 0xb7, 0x75, 0x23, 0x47, 0x25, 0xff, 0xb9, ++ 0x53, 0x65, 0xb5, 0xa1, 0xde, 0xdf, 0x93, 0xc1, 0xfd, 0xfc, 0xb7, 0xbe, ++ 0x11, 0x4e, 0x71, 0x30, 0xd7, 0xda, 0xef, 0x47, 0x00, 0x4b, 0x8a, 0x33, ++ 0x7c, 0x89, 0xcb, 0xd1, 0x8f, 0x7a, 0xfa, 0x8c, 0xc1, 0xfb, 0xee, 0x11, ++ 0xfd, 0x9f, 0x2d, 0xda, 0xf8, 0xf3, 0x6f, 0xf0, 0x7c, 0xf4, 0x65, 0x46, ++ 0x71, 0x9f, 0x67, 0xa3, 0x38, 0xff, 0xcf, 0x69, 0x3c, 0x69, 0x30, 0xa0, ++ 0x1c, 0xec, 0xc1, 0xf1, 0x25, 0xc7, 0xee, 0x37, 0xa0, 0x5c, 0x69, 0x5f, ++ 0x14, 0xe1, 0xc1, 0xb8, 0xfe, 0x9a, 0xc5, 0x36, 0x8a, 0x07, 0xcd, 0x4d, ++ 0xea, 0xf8, 0xc0, 0x02, 0x5b, 0xbf, 0xee, 0x99, 0x03, 0x8f, 0x58, 0x00, ++ 0xdf, 0x3e, 0xc6, 0x24, 0xc8, 0x20, 0xb9, 0xda, 0x8e, 0x46, 0x11, 0xd4, ++ 0x37, 0x66, 0x1c, 0x20, 0xb9, 0x7a, 0xcb, 0x1b, 0xe1, 0x2d, 0x86, 0xeb, ++ 0x58, 0xcf, 0x46, 0x3c, 0x97, 0x40, 0x39, 0x58, 0xca, 0xe9, 0x7c, 0x26, ++ 0xe2, 0x8d, 0x90, 0x2f, 0xe8, 0x63, 0xaf, 0xb9, 0x9f, 0x75, 0xca, 0x1b, ++ 0xe4, 0x0b, 0xb8, 0x7e, 0xac, 0x1f, 0x78, 0xe6, 0x4f, 0x87, 0x1f, 0x81, ++ 0x79, 0xd7, 0x1c, 0xe4, 0x74, 0x8e, 0x11, 0x76, 0x7a, 0xfb, 0x7e, 0x5a, ++ 0x90, 0x7d, 0xcf, 0x1e, 0xe7, 0x74, 0x69, 0x81, 0x1f, 0x1e, 0xa7, 0xa4, ++ 0xa3, 0xef, 0x7d, 0x1b, 0x4c, 0xd6, 0xcb, 0xd2, 0x79, 0x03, 0xc5, 0xdd, ++ 0x5c, 0x2d, 0x7d, 0xef, 0x40, 0x7a, 0x8e, 0xb8, 0x2c, 0x3d, 0x1f, 0xba, ++ 0x05, 0xf6, 0xa7, 0xe6, 0x65, 0x7e, 0x9f, 0xc5, 0xb9, 0xe6, 0x81, 0x94, ++ 0x17, 0xdb, 0x9d, 0x3c, 0xaf, 0xd9, 0xa4, 0x12, 0x1d, 0xca, 0x7a, 0x5b, ++ 0xb3, 0x3a, 0x0e, 0xf1, 0x56, 0x9f, 0x7f, 0x2e, 0xe1, 0xca, 0x5c, 0x4e, ++ 0xa2, 0x4f, 0x79, 0x6f, 0xd4, 0xb2, 0x11, 0xff, 0x9c, 0x88, 0x72, 0x73, ++ 0xd9, 0x1e, 0x23, 0x0f, 0x12, 0xe9, 0x6e, 0x9c, 0x75, 0x2a, 0x73, 0x04, ++ 0x8d, 0xb3, 0xf3, 0x35, 0xf3, 0x22, 0xca, 0x73, 0x13, 0xf3, 0x6f, 0x97, ++ 0xf2, 0x7a, 0xcf, 0x3f, 0xa2, 0x4b, 0xb2, 0x78, 0xb9, 0x2a, 0x84, 0xdc, ++ 0x03, 0x39, 0x1d, 0x16, 0x8b, 0x72, 0xba, 0x42, 0x21, 0xbb, 0xf2, 0xc8, ++ 0x9e, 0xde, 0xa5, 0x08, 0xa7, 0x23, 0x0a, 0x6b, 0x71, 0x50, 0xde, 0x16, ++ 0x8f, 0x53, 0x9e, 0xc4, 0xbb, 0xc3, 0xe7, 0x56, 0xba, 0xaf, 0x24, 0x3e, ++ 0x9d, 0xe2, 0x93, 0xa5, 0x7d, 0x29, 0xed, 0xca, 0x29, 0x7b, 0xa6, 0x0c, ++ 0x44, 0xbd, 0xf2, 0x83, 0xc6, 0x39, 0x47, 0x60, 0xe7, 0xd8, 0xa7, 0x19, ++ 0xc9, 0x84, 0xe7, 0x77, 0x30, 0x0f, 0xe9, 0xc1, 0x47, 0xa2, 0xca, 0x07, ++ 0xa0, 0x5f, 0x62, 0x82, 0x88, 0x0f, 0x38, 0x12, 0xd5, 0xd1, 0x8a, 0x7c, ++ 0xf9, 0xc8, 0x88, 0x08, 0x05, 0xcf, 0xfb, 0xa1, 0xff, 0xd5, 0xd8, 0xbf, ++ 0x5c, 0xd7, 0x91, 0xb0, 0xf2, 0x01, 0xfc, 0xde, 0x09, 0x19, 0x97, 0x3c, ++ 0xe8, 0xba, 0xee, 0x89, 0x1b, 0xa3, 0xde, 0x5b, 0x72, 0x0b, 0x9e, 0x6f, ++ 0x4f, 0x67, 0x76, 0xb4, 0x2b, 0x6f, 0x57, 0xb9, 0x9e, 0xcb, 0x5e, 0xe7, ++ 0xf4, 0x29, 0xf9, 0x5e, 0x8d, 0xe2, 0x8b, 0xc6, 0x79, 0xbe, 0x9d, 0x31, ++ 0xf1, 0xab, 0x0c, 0x3c, 0x2f, 0x5e, 0xf9, 0x0b, 0xe1, 0x57, 0x15, 0x70, ++ 0x33, 0xf2, 0x38, 0xc4, 0xab, 0xd5, 0x73, 0x3b, 0xed, 0xd9, 0xa7, 0x15, ++ 0x7e, 0x1f, 0x8a, 0x93, 0xeb, 0xff, 0xd5, 0xc3, 0xcf, 0xfc, 0xfa, 0x0e, ++ 0xcc, 0x93, 0x03, 0xbb, 0x5b, 0x81, 0xf9, 0xcc, 0x69, 0xda, 0x4b, 0xf7, ++ 0xfe, 0xe8, 0xed, 0xec, 0x4e, 0x7b, 0xe7, 0xff, 0xd1, 0x9f, 0xda, 0xd5, ++ 0x5e, 0x2a, 0x8f, 0x18, 0x54, 0x14, 0xf0, 0x93, 0xeb, 0xed, 0xa6, 0x4e, ++ 0x3d, 0x5d, 0xea, 0x7b, 0xdb, 0x78, 0x9c, 0xfc, 0x9b, 0x23, 0x7e, 0xdb, ++ 0xb6, 0x14, 0xea, 0x2b, 0xb6, 0x45, 0x10, 0x1c, 0x4f, 0x3f, 0x69, 0xf6, ++ 0x20, 0x1f, 0x3f, 0xbd, 0xc5, 0x4c, 0xf6, 0xcf, 0xe9, 0xe8, 0x8e, 0x63, ++ 0xcb, 0xb1, 0xbe, 0x2b, 0xdb, 0xe9, 0xa1, 0xd1, 0x9c, 0x9a, 0x7b, 0xd1, ++ 0x16, 0x1a, 0x1c, 0x1f, 0xa2, 0xfc, 0x61, 0x6f, 0x87, 0xd1, 0x7d, 0x1e, ++ 0x27, 0x9f, 0x30, 0xb7, 0xe0, 0xf9, 0xee, 0xe2, 0xa7, 0x32, 0xb6, 0xa0, ++ 0x3d, 0x75, 0x72, 0x80, 0xe3, 0xd9, 0x1d, 0xe8, 0x0f, 0x7c, 0x36, 0x8e, ++ 0xee, 0x19, 0x60, 0x6e, 0xfe, 0xfd, 0x6d, 0x82, 0x1e, 0x91, 0xbe, 0x1c, ++ 0xa0, 0x7a, 0xa8, 0xbf, 0xb3, 0x91, 0x1e, 0xb1, 0xf8, 0x85, 0x3e, 0xc4, ++ 0xc7, 0xe4, 0xfe, 0x9d, 0x7a, 0x22, 0x9c, 0xf2, 0xe8, 0x4f, 0x1f, 0x98, ++ 0xd4, 0x13, 0xfd, 0x65, 0xad, 0x86, 0xe7, 0x29, 0x8f, 0x87, 0xa9, 0x56, ++ 0x0f, 0xf2, 0xe3, 0xa5, 0x5b, 0xc2, 0x49, 0x0f, 0x5c, 0x69, 0x77, 0x67, ++ 0xe3, 0xfa, 0xcb, 0x7e, 0x77, 0xdb, 0x1d, 0x05, 0x38, 0xfe, 0xfb, 0x71, ++ 0x0c, 0xd7, 0xd3, 0xde, 0xfc, 0x02, 0xf9, 0x2b, 0x03, 0xfb, 0x1b, 0x5a, ++ 0xbe, 0x9f, 0x6b, 0x4e, 0xe6, 0x7c, 0xa0, 0x53, 0xde, 0xf2, 0xb8, 0xdb, ++ 0x59, 0x18, 0x77, 0x9b, 0x4c, 0x71, 0xb7, 0x05, 0x83, 0xe2, 0x30, 0x5e, ++ 0x55, 0xde, 0xbb, 0xc8, 0xe3, 0x6e, 0xf3, 0x55, 0xc5, 0x45, 0x79, 0x07, ++ 0x0f, 0x85, 0xce, 0x23, 0x1f, 0x3d, 0x48, 0x9c, 0xab, 0x4a, 0xff, 0x49, ++ 0x0c, 0xb3, 0xc4, 0x23, 0x1d, 0xba, 0x19, 0xad, 0xb7, 0xfd, 0xa1, 0xb4, ++ 0x2d, 0x68, 0xef, 0x4c, 0x1f, 0x24, 0xf2, 0x9f, 0x59, 0x87, 0xc8, 0x97, ++ 0x94, 0xf8, 0x76, 0xac, 0xfa, 0x55, 0xf2, 0x9f, 0x98, 0x79, 0xbc, 0x5f, ++ 0x78, 0xe8, 0x73, 0xec, 0xf2, 0x41, 0x3c, 0xaf, 0x78, 0x81, 0xe5, 0x6b, ++ 0x8d, 0xff, 0xa6, 0x7a, 0xe5, 0xb7, 0x1a, 0xbf, 0x4a, 0x75, 0x16, 0x23, ++ 0xb9, 0x9b, 0x5f, 0xef, 0x28, 0xb8, 0x1b, 0xca, 0xe5, 0x02, 0xce, 0x55, ++ 0x49, 0xe5, 0x93, 0x10, 0x7e, 0x4b, 0x1a, 0x36, 0xbe, 0xf8, 0x0e, 0xc1, ++ 0xe5, 0xf1, 0x1f, 0x7f, 0x8c, 0xe3, 0x1e, 0xb0, 0x92, 0xdf, 0x86, 0xbd, ++ 0xc3, 0xe1, 0xa7, 0xb7, 0x67, 0x16, 0x58, 0xbe, 0x12, 0xf4, 0xb4, 0x59, ++ 0xa3, 0x07, 0x9f, 0x78, 0xf4, 0x43, 0x8a, 0x37, 0x39, 0xb1, 0x3b, 0x33, ++ 0x07, 0xf7, 0x6d, 0x8e, 0xea, 0x3b, 0x81, 0xf7, 0x71, 0xb5, 0xd9, 0x7c, ++ 0x9f, 0xfc, 0x0c, 0xca, 0x5d, 0x07, 0x0e, 0xd1, 0xbe, 0xe8, 0xe7, 0xdb, ++ 0xe5, 0xdc, 0x5e, 0xe1, 0x7c, 0xa5, 0x12, 0xd7, 0x11, 0x83, 0xf1, 0x2e, ++ 0xe5, 0x8b, 0x07, 0xd1, 0xb9, 0x30, 0xa7, 0xf7, 0xe3, 0xeb, 0xb3, 0x09, ++ 0x7e, 0xd2, 0x9f, 0xdb, 0x7e, 0x3a, 0xb4, 0xbd, 0x25, 0xe7, 0x29, 0xfb, ++ 0x97, 0xf3, 0x93, 0xfd, 0xcb, 0x76, 0xff, 0x25, 0xf6, 0xeb, 0xac, 0xc9, ++ 0x97, 0x83, 0xf2, 0xb9, 0x7f, 0xba, 0x43, 0x93, 0x87, 0x7d, 0x36, 0xd2, ++ 0x97, 0x13, 0x65, 0xc5, 0xe7, 0xfc, 0x1c, 0xea, 0x6c, 0x34, 0xd4, 0x83, ++ 0xf0, 0xe6, 0xfb, 0x3a, 0xdf, 0xb9, 0x4b, 0xf8, 0x79, 0x8e, 0x1a, 0x56, ++ 0xdd, 0x63, 0x02, 0xfc, 0x6b, 0x6d, 0x78, 0x38, 0xcc, 0x1d, 0xcc, 0x47, ++ 0xaf, 0xf1, 0x5c, 0x47, 0xce, 0x57, 0xc6, 0x95, 0xca, 0x3c, 0xda, 0x4d, ++ 0x83, 0x84, 0x3f, 0x7b, 0x00, 0x1b, 0xd0, 0x4d, 0xfe, 0xed, 0xe3, 0x88, ++ 0x27, 0x95, 0x5d, 0xf3, 0x6f, 0xe9, 0x79, 0x77, 0xf9, 0xb7, 0x9d, 0xf9, ++ 0xb6, 0xff, 0xe0, 0xf9, 0xb6, 0x32, 0xbf, 0xb6, 0xb0, 0xcc, 0x50, 0x1b, ++ 0x9c, 0x67, 0x2b, 0xf9, 0x61, 0x61, 0x26, 0x3c, 0xcf, 0xc2, 0x73, 0x7f, ++ 0xad, 0x7c, 0x2f, 0xcc, 0xd5, 0xb6, 0xef, 0x8e, 0x3f, 0x0e, 0xce, 0xe4, ++ 0x7e, 0x95, 0xc2, 0x98, 0xd0, 0xf9, 0xae, 0x7f, 0x1e, 0xc4, 0xdf, 0xd7, ++ 0xb3, 0x16, 0x7e, 0xff, 0xa0, 0x90, 0x8b, 0xc3, 0x04, 0xdc, 0xe5, 0xbd, ++ 0x5f, 0x52, 0x4f, 0xa9, 0x16, 0x7c, 0x5b, 0xe6, 0x79, 0x0e, 0x6b, 0xe6, ++ 0x71, 0x9b, 0xc3, 0x44, 0xde, 0x0e, 0x70, 0x01, 0xca, 0x73, 0xed, 0x72, ++ 0xbf, 0x5b, 0x7c, 0x26, 0xc9, 0x55, 0x79, 0x3f, 0x9f, 0x02, 0x7d, 0x4d, ++ 0x8f, 0x0e, 0x95, 0x2f, 0xec, 0xa3, 0x79, 0x8c, 0x64, 0x1d, 0x54, 0xba, ++ 0x98, 0xdd, 0x88, 0x25, 0x80, 0x9f, 0xca, 0xd1, 0xac, 0x9c, 0xca, 0xb1, ++ 0xac, 0x96, 0xca, 0x71, 0x6c, 0x03, 0x95, 0x37, 0xb3, 0x06, 0x2a, 0x6f, ++ 0x65, 0x3e, 0x2a, 0xd9, 0xa0, 0x16, 0x11, 0xef, 0x79, 0x2f, 0xcf, 0x33, ++ 0x1d, 0xbf, 0xd0, 0x80, 0xf2, 0xb5, 0xf0, 0x8e, 0xd0, 0x7a, 0x71, 0xfb, ++ 0x15, 0xe1, 0xe0, 0xa1, 0xfb, 0x03, 0xaf, 0x15, 0x0e, 0x63, 0x19, 0xbf, ++ 0xe7, 0xaf, 0x0b, 0x3c, 0xfa, 0xa7, 0x13, 0x7e, 0xeb, 0xe1, 0xa1, 0xcf, ++ 0xd7, 0x1c, 0xc1, 0xfc, 0x74, 0x71, 0xc9, 0x28, 0x44, 0xdc, 0x64, 0xb4, ++ 0x83, 0x1d, 0x14, 0xdf, 0x5a, 0xc6, 0x5c, 0x54, 0x1f, 0x73, 0x95, 0x70, ++ 0x28, 0xf6, 0xbb, 0x8d, 0x3c, 0xbf, 0x57, 0x07, 0x8f, 0xb2, 0xd0, 0x78, ++ 0x71, 0x41, 0xc0, 0x63, 0x15, 0xca, 0xce, 0xa2, 0xc0, 0x3e, 0x65, 0x67, ++ 0x3a, 0xe8, 0xb9, 0xdc, 0x2f, 0x30, 0xc4, 0xe2, 0x91, 0xff, 0xeb, 0xf7, ++ 0x51, 0x3e, 0x2f, 0x8c, 0x28, 0x3d, 0xef, 0xb0, 0xe3, 0x7d, 0x30, 0xab, ++ 0xa6, 0x50, 0x1e, 0x77, 0x41, 0xe9, 0xf2, 0x64, 0xa8, 0xa7, 0x66, 0xfe, ++ 0x6a, 0x0a, 0xe5, 0x79, 0x0f, 0x2b, 0x7d, 0x01, 0xf3, 0xbc, 0xd3, 0x9f, ++ 0x7d, 0x98, 0xbf, 0xcf, 0x2d, 0x2d, 0x08, 0x73, 0xc2, 0xb8, 0xab, 0x1e, ++ 0x99, 0x82, 0xf9, 0x8c, 0x6e, 0x11, 0x37, 0xed, 0x16, 0xf1, 0xd2, 0xcc, ++ 0x9d, 0xa7, 0xb9, 0x1f, 0xcb, 0xbd, 0xea, 0x1e, 0xba, 0x6f, 0xcc, 0x3d, ++ 0xc0, 0xea, 0xc4, 0x75, 0xca, 0xbc, 0x70, 0x35, 0x99, 0x9f, 0xaf, 0xee, ++ 0xb1, 0xbb, 0x7b, 0x66, 0xc2, 0x7c, 0x13, 0xc6, 0xf9, 0xd6, 0x70, 0x48, ++ 0x97, 0xf6, 0x9e, 0x0a, 0x74, 0xdc, 0xea, 0x0b, 0x63, 0x18, 0xef, 0xbf, ++ 0xd6, 0xc4, 0xdb, 0xcb, 0xfb, 0x6c, 0xe4, 0xfa, 0xe4, 0x3d, 0x37, 0xbb, ++ 0x76, 0x65, 0x2e, 0x57, 0x92, 0xae, 0x3c, 0x0f, 0x18, 0x67, 0x00, 0x8e, ++ 0xe3, 0x5e, 0x35, 0x90, 0xf2, 0xe3, 0xdc, 0xbb, 0x15, 0xe7, 0xe5, 0xc6, ++ 0x0b, 0x4f, 0x72, 0x27, 0x65, 0xa2, 0xde, 0x85, 0x49, 0xf1, 0x40, 0x17, ++ 0xfd, 0x84, 0x1c, 0x6e, 0xdd, 0x95, 0x99, 0x89, 0xfb, 0x94, 0x9d, 0x29, ++ 0xe2, 0x7e, 0x62, 0x13, 0x0b, 0x10, 0x8e, 0xd3, 0x92, 0xca, 0xb3, 0xb1, ++ 0x7f, 0x99, 0x17, 0x9d, 0x2d, 0xf6, 0xa5, 0xbb, 0x72, 0x4a, 0xa6, 0x2b, ++ 0x13, 0xdb, 0xeb, 0x9f, 0xcb, 0xbc, 0xec, 0x91, 0x99, 0xee, 0x3c, 0x1c, ++ 0xbf, 0x26, 0xe2, 0x22, 0xe5, 0x9b, 0xb5, 0xe5, 0xbd, 0xbf, 0xc6, 0x9f, ++ 0xd8, 0x35, 0x4f, 0xbd, 0xde, 0xc5, 0xbc, 0x26, 0xe2, 0x2b, 0xda, 0xfc, ++ 0xf4, 0xf6, 0xf9, 0x26, 0xba, 0xcf, 0xa9, 0xb0, 0xdc, 0x5d, 0x8f, 0x21, ++ 0xca, 0x37, 0x4e, 0xef, 0x18, 0x8c, 0xfa, 0x31, 0xf4, 0x3b, 0x1c, 0xc7, ++ 0xad, 0x31, 0xf9, 0x13, 0xf2, 0x54, 0x8c, 0x42, 0xe6, 0xf9, 0xef, 0xfa, ++ 0x7c, 0xef, 0x3d, 0xaf, 0x1d, 0xd4, 0xe4, 0xb7, 0x4b, 0x3a, 0xeb, 0xcc, ++ 0x6f, 0x3f, 0xc7, 0xf3, 0xdb, 0x03, 0xf4, 0xf5, 0xe8, 0x72, 0x16, 0x94, ++ 0xdf, 0x2e, 0xe9, 0x46, 0xd2, 0xdd, 0x50, 0xcc, 0x6f, 0x8f, 0xc4, 0x7a, ++ 0xc6, 0x7c, 0x6c, 0x37, 0xe2, 0xfd, 0x63, 0x94, 0xdf, 0x3e, 0xea, 0x98, ++ 0x5f, 0xe4, 0xb7, 0x7f, 0xa8, 0xcd, 0x6f, 0x77, 0xfd, 0xf3, 0xba, 0xf2, ++ 0xdb, 0x4f, 0x8a, 0xfb, 0xde, 0x4e, 0x5a, 0xf8, 0x7d, 0x49, 0xf2, 0x3e, ++ 0xa9, 0x65, 0xbb, 0xf9, 0xf9, 0xef, 0x32, 0x85, 0xdf, 0x27, 0xb5, 0xec, ++ 0x39, 0x7e, 0x9f, 0x94, 0xb4, 0x0b, 0x17, 0x89, 0xf5, 0x55, 0x1d, 0xdc, ++ 0xb6, 0x06, 0xcf, 0xf9, 0x16, 0x3d, 0x3e, 0x97, 0xee, 0xa3, 0x62, 0xe2, ++ 0x1e, 0x54, 0x07, 0xfc, 0x04, 0xdb, 0x85, 0xf2, 0x5e, 0x52, 0x7d, 0x1e, ++ 0x4c, 0x0d, 0xda, 0x83, 0xa4, 0x37, 0xb7, 0x90, 0xde, 0xa5, 0xcf, 0x87, ++ 0xa9, 0x79, 0xbc, 0x8c, 0xec, 0xc1, 0x1a, 0x9d, 0x1e, 0x5d, 0x9d, 0x29, ++ 0xec, 0x41, 0x21, 0xcf, 0x98, 0xd0, 0xff, 0x16, 0x8a, 0x6f, 0x71, 0x1d, ++ 0x56, 0xb2, 0xcf, 0x4c, 0xa4, 0x77, 0x2e, 0x7b, 0x62, 0xb9, 0xd3, 0x8e, ++ 0x75, 0x41, 0x57, 0x6c, 0xc7, 0x0e, 0x3a, 0x77, 0x93, 0xed, 0xd9, 0xe3, ++ 0x31, 0x84, 0x0b, 0x92, 0xce, 0x16, 0xaf, 0x53, 0x48, 0x7f, 0x95, 0xf0, ++ 0xcb, 0xdd, 0x6e, 0x76, 0xd1, 0x3d, 0xc6, 0xdb, 0x7b, 0x93, 0xde, 0x0a, ++ 0xfa, 0xb6, 0xc8, 0x63, 0xf6, 0x72, 0x7b, 0x1b, 0x70, 0x05, 0xe3, 0xe1, ++ 0x77, 0x46, 0x75, 0x24, 0xa1, 0x9e, 0xbc, 0x73, 0x4f, 0xba, 0x13, 0x38, ++ 0x2c, 0x7b, 0xa5, 0xdb, 0xfb, 0xa7, 0x77, 0xe8, 0xee, 0x9f, 0x7e, 0x4a, ++ 0x73, 0xff, 0xf4, 0x39, 0xfc, 0x0f, 0xf5, 0xb4, 0x53, 0x06, 0x2f, 0xf6, ++ 0x33, 0x98, 0xa5, 0xff, 0x12, 0xef, 0x25, 0x2e, 0x3a, 0x65, 0x74, 0x7a, ++ 0x1d, 0x81, 0xfb, 0x98, 0xaf, 0x74, 0xef, 0xb0, 0x84, 0xbf, 0x59, 0xec, ++ 0xd7, 0xb5, 0xde, 0x43, 0xac, 0xbf, 0xef, 0x59, 0xe6, 0x3f, 0xe8, 0xef, ++ 0x23, 0x5e, 0x2b, 0xee, 0x23, 0x1e, 0xd1, 0xcd, 0x7d, 0xc4, 0x66, 0xb5, ++ 0x59, 0x25, 0xfd, 0xe1, 0x6b, 0xa3, 0xe6, 0x5e, 0xe2, 0x1b, 0xc5, 0x3a, ++ 0x8b, 0x1d, 0xcc, 0x8b, 0xf7, 0xfc, 0x0e, 0x6d, 0x35, 0x6a, 0xf6, 0xbf, ++ 0xd8, 0xbf, 0x81, 0xa1, 0x3e, 0x14, 0x7e, 0xd8, 0xa8, 0xf1, 0x23, 0x98, ++ 0x1d, 0xda, 0x7a, 0x83, 0xc4, 0x07, 0x71, 0xbf, 0x48, 0x57, 0x78, 0x5b, ++ 0x3b, 0xe1, 0x69, 0x26, 0x78, 0xa6, 0xd0, 0x3d, 0xcf, 0x45, 0xba, 0x7b, ++ 0x9e, 0x25, 0x9c, 0x3a, 0xef, 0x79, 0xee, 0x6f, 0x25, 0xbc, 0x1f, 0x7a, ++ 0xf0, 0x05, 0x15, 0xf9, 0xc1, 0xb5, 0xde, 0xf7, 0xfd, 0x43, 0xdf, 0xef, ++ 0x7d, 0xa5, 0xfb, 0xbc, 0xf5, 0xf7, 0x74, 0xeb, 0xef, 0xe5, 0xee, 0xee, ++ 0x9e, 0x6f, 0xb9, 0xef, 0x79, 0x2d, 0xcb, 0x34, 0xed, 0xf5, 0xfb, 0x5e, ++ 0x70, 0xe0, 0xa7, 0xda, 0x7b, 0xa8, 0xc5, 0x7e, 0x7b, 0xe0, 0xe7, 0xbb, ++ 0xdc, 0xef, 0xb6, 0x4c, 0xe1, 0xdf, 0x15, 0xfb, 0xfd, 0x35, 0x5e, 0x80, ++ 0x06, 0x74, 0xf8, 0x97, 0xc8, 0x53, 0x0f, 0x22, 0x59, 0x4e, 0x88, 0xe0, ++ 0x7c, 0xad, 0xd3, 0xae, 0x1f, 0x1e, 0x46, 0x76, 0xd6, 0xbb, 0x8e, 0x98, ++ 0x32, 0x1b, 0xd2, 0xbf, 0x90, 0x53, 0xe5, 0x42, 0x4e, 0x81, 0x15, 0xc7, ++ 0xeb, 0x02, 0x5f, 0x9c, 0x3e, 0x1e, 0x47, 0x90, 0x7f, 0x94, 0xdf, 0x5f, ++ 0x51, 0xe8, 0xe7, 0xf1, 0x04, 0x83, 0x4f, 0x85, 0xce, 0x0f, 0xba, 0xbd, ++ 0x58, 0xd1, 0x9c, 0xef, 0x76, 0xbd, 0xb7, 0x98, 0xe7, 0x19, 0x0f, 0xbb, ++ 0xc8, 0xe3, 0xf4, 0xf4, 0xe7, 0xfe, 0x32, 0x6f, 0xa8, 0xc2, 0x15, 0xae, ++ 0xbd, 0xbf, 0xa1, 0x9b, 0x3c, 0x22, 0xe9, 0xc7, 0x01, 0x3d, 0x9e, 0x99, ++ 0x50, 0x8f, 0x37, 0xf0, 0xfb, 0xec, 0x42, 0xdc, 0x73, 0xbc, 0x49, 0x4d, ++ 0x0e, 0xce, 0x23, 0x72, 0x93, 0x7f, 0x67, 0xb2, 0xc5, 0x97, 0x80, 0xf8, ++ 0x6c, 0x4b, 0x74, 0xc7, 0x67, 0x15, 0x05, 0xf2, 0x8d, 0x46, 0x61, 0x5e, ++ 0x91, 0x42, 0xf6, 0xa0, 0x10, 0x4a, 0x51, 0x3f, 0xc2, 0x38, 0xcf, 0x76, ++ 0x4c, 0xb2, 0xed, 0x8b, 0xf9, 0xa3, 0x91, 0x3f, 0xc2, 0x3c, 0x19, 0x98, ++ 0xbe, 0xdd, 0x3f, 0x98, 0x9b, 0xbb, 0xf8, 0x6f, 0x60, 0x96, 0x3b, 0x31, ++ 0x0b, 0xe4, 0xc9, 0x71, 0xc5, 0xbe, 0xa6, 0x00, 0xbe, 0xfd, 0xcb, 0xd0, ++ 0x33, 0x09, 0x28, 0x9f, 0xcc, 0x78, 0xae, 0x9d, 0x4f, 0xe7, 0xbe, 0xc9, ++ 0xf8, 0x5e, 0x7f, 0x3f, 0xbf, 0xdf, 0xe0, 0x20, 0xfd, 0xc2, 0xf3, 0x53, ++ 0x85, 0xec, 0x87, 0x33, 0xd8, 0xd9, 0x90, 0x20, 0x7a, 0x5d, 0x17, 0x26, ++ 0xf2, 0x1a, 0x75, 0x7f, 0xbf, 0x40, 0xd8, 0x53, 0xf2, 0xef, 0x17, 0x1c, ++ 0x87, 0x2e, 0x16, 0x01, 0xdf, 0x9e, 0xd1, 0xc4, 0xf3, 0xa8, 0x97, 0xc6, ++ 0xb7, 0x0a, 0x3b, 0x8c, 0xdf, 0xdf, 0x3a, 0xb7, 0xbf, 0x95, 0xee, 0x7f, ++ 0x62, 0xae, 0x02, 0x27, 0xb7, 0xc3, 0xa5, 0x7d, 0xd5, 0x4f, 0xbd, 0x16, ++ 0xb9, 0x79, 0xa5, 0xf8, 0xa2, 0xa5, 0xf1, 0xa7, 0x35, 0x76, 0x2e, 0xdb, ++ 0x11, 0x73, 0x55, 0xe7, 0x89, 0x81, 0x75, 0xf3, 0xfe, 0x8f, 0x3f, 0x10, ++ 0x41, 0xf2, 0xe6, 0xf8, 0x03, 0x03, 0xc8, 0xcf, 0x17, 0xe8, 0xbf, 0x8d, ++ 0xec, 0xfe, 0x19, 0xb5, 0xda, 0x38, 0xe3, 0x59, 0x2b, 0x3f, 0xd2, 0xe0, ++ 0xdf, 0x6c, 0xcf, 0x67, 0x9a, 0xf7, 0xfe, 0xd8, 0x8e, 0xb0, 0x7e, 0xb0, ++ 0x7e, 0xff, 0x8b, 0x7d, 0xc6, 0x4e, 0x03, 0xf8, 0x9d, 0xdd, 0x6d, 0x1e, ++ 0x8c, 0x74, 0x06, 0xfb, 0x36, 0x35, 0x2b, 0xc8, 0x0e, 0xf6, 0x3f, 0x94, ++ 0x36, 0x9a, 0xeb, 0x01, 0x57, 0x5a, 0xe7, 0x19, 0x9a, 0xc7, 0x31, 0x11, ++ 0x27, 0x2a, 0xd7, 0xf9, 0x49, 0xdd, 0x51, 0xaa, 0xfb, 0xeb, 0xfc, 0xba, ++ 0x78, 0x1e, 0x8f, 0xc6, 0x2e, 0x95, 0xa5, 0xe9, 0x0d, 0x46, 0xf7, 0xe4, ++ 0x74, 0x28, 0x3d, 0x9c, 0xa1, 0xfc, 0x2c, 0x9f, 0x66, 0x71, 0xbd, 0xfd, ++ 0x98, 0xc8, 0x83, 0x3c, 0x26, 0xf2, 0x20, 0x8f, 0x89, 0xbc, 0xc5, 0x63, ++ 0x22, 0x4f, 0xf1, 0x98, 0xc8, 0x53, 0x94, 0xf9, 0xa3, 0xc7, 0x14, 0xe6, ++ 0xc2, 0x78, 0x8a, 0xe9, 0x4a, 0xf9, 0x93, 0xb3, 0x15, 0xca, 0x1f, 0xbd, ++ 0x07, 0xf1, 0xaf, 0x66, 0x49, 0x47, 0x0e, 0xe6, 0xdb, 0xd5, 0xe4, 0xfa, ++ 0x67, 0x2a, 0x2a, 0xe5, 0x8f, 0xae, 0xc4, 0xf5, 0x87, 0xc8, 0x1f, 0xcd, ++ 0xc1, 0xbc, 0xf7, 0x5d, 0x59, 0x77, 0xfe, 0x08, 0xf5, 0xf8, 0x53, 0x3d, ++ 0x3c, 0x74, 0x2f, 0xc9, 0xef, 0x77, 0x4c, 0xe6, 0x75, 0x13, 0xa7, 0x8f, ++ 0x57, 0xb2, 0x46, 0x11, 0x3d, 0x78, 0xfb, 0xba, 0xef, 0xc3, 0x7e, 0xbe, ++ 0x50, 0xd4, 0x16, 0xc2, 0xe7, 0x97, 0x15, 0x3a, 0x4f, 0x65, 0x2e, 0xbf, ++ 0x69, 0xe2, 0x65, 0xf2, 0x4b, 0x1f, 0xc8, 0xe2, 0xe7, 0x0b, 0xeb, 0x75, ++ 0xe5, 0xd6, 0x2c, 0xce, 0xcf, 0x5e, 0x11, 0xe5, 0x18, 0xf5, 0xc1, 0x54, ++ 0xca, 0xfb, 0xd9, 0x64, 0xa6, 0xbc, 0x1f, 0x18, 0xc7, 0x65, 0x08, 0x3a, ++ 0xff, 0xd7, 0xe7, 0x67, 0xe5, 0xbf, 0x6e, 0x6e, 0x41, 0xbe, 0x21, 0xfd, ++ 0x30, 0x4f, 0x64, 0x25, 0xf2, 0x73, 0xcf, 0x64, 0xee, 0x5f, 0x89, 0xfd, ++ 0xa5, 0x99, 0xe7, 0x6d, 0xf9, 0x7d, 0x09, 0x98, 0xe7, 0x85, 0xf1, 0x3e, ++ 0x78, 0x6f, 0x06, 0x3b, 0xcc, 0x5c, 0x3c, 0x0f, 0x8c, 0xdf, 0xdf, 0x27, ++ 0xf7, 0xe1, 0x09, 0xb1, 0x0f, 0x74, 0x91, 0x7e, 0x61, 0x20, 0x4f, 0xac, ++ 0xea, 0xe0, 0xf1, 0x4f, 0x90, 0x8f, 0x8c, 0xcd, 0x72, 0x6f, 0xc6, 0xf5, ++ 0xcb, 0xfc, 0xa5, 0xaa, 0xc8, 0xbd, 0x14, 0x37, 0xf1, 0x42, 0x96, 0x83, ++ 0xbe, 0x83, 0xf9, 0xd2, 0xfa, 0x81, 0x1f, 0xac, 0x56, 0x08, 0xce, 0x5d, ++ 0xfc, 0x70, 0xcf, 0xe0, 0xfe, 0xe8, 0xf3, 0xdf, 0xbb, 0x5b, 0xff, 0xd9, ++ 0xf9, 0xbe, 0xdf, 0x64, 0x25, 0x06, 0xf2, 0xa7, 0x82, 0xf2, 0xa6, 0x5e, ++ 0xc0, 0x79, 0xc8, 0x75, 0xcb, 0x79, 0x04, 0xfa, 0xb9, 0x3c, 0x5e, 0x4b, ++ 0x7f, 0x52, 0xc0, 0xdf, 0xb5, 0x36, 0x15, 0xe9, 0x44, 0xde, 0x4f, 0x9b, ++ 0xaf, 0x2a, 0xb3, 0x26, 0x86, 0xf8, 0xfe, 0x03, 0xb1, 0x6f, 0x55, 0x49, ++ 0xe5, 0x7b, 0x71, 0x1d, 0x4b, 0x6a, 0xb9, 0xbf, 0xad, 0xd3, 0x1e, 0x57, ++ 0x36, 0xfc, 0xf8, 0x63, 0xdc, 0xaf, 0x83, 0x56, 0xe2, 0x73, 0xdd, 0x7d, ++ 0xaf, 0x5f, 0x67, 0xd5, 0x6b, 0x07, 0x09, 0x1e, 0xb0, 0xce, 0x99, 0xb8, ++ 0xbe, 0xa0, 0x75, 0xbe, 0x9b, 0x15, 0xe4, 0x17, 0x3c, 0xbb, 0xe7, 0xc3, ++ 0xdf, 0x20, 0xa8, 0xaf, 0x77, 0x7d, 0xd7, 0x9a, 0xc7, 0x6c, 0xee, 0xc1, ++ 0xef, 0x43, 0xec, 0xea, 0x8f, 0x86, 0x0d, 0x0d, 0xd2, 0xa3, 0xcc, 0xf2, ++ 0xfb, 0xfe, 0xda, 0x7b, 0xc6, 0xcc, 0xf8, 0xf7, 0x10, 0x60, 0xbc, 0x46, ++ 0x61, 0x7f, 0x34, 0x0a, 0xfb, 0xa3, 0x29, 0x4c, 0xfc, 0xbd, 0x1a, 0x9d, ++ 0x3d, 0xda, 0xe8, 0xe3, 0xf1, 0x3c, 0x8d, 0xf1, 0x26, 0x8a, 0xd7, 0x61, ++ 0xe2, 0xef, 0x2b, 0x48, 0xf9, 0xbb, 0xe2, 0x3d, 0x1e, 0xdf, 0xb3, 0x22, ++ 0x91, 0xd1, 0x7b, 0x9c, 0x1f, 0xd2, 0x81, 0xe2, 0xdf, 0x4f, 0xf2, 0xa0, ++ 0xf3, 0xbe, 0x28, 0x05, 0xe4, 0x1c, 0xe0, 0xc3, 0x19, 0xbb, 0xfb, 0x02, ++ 0xc2, 0x8f, 0xb9, 0x97, 0x93, 0x7c, 0x50, 0x6f, 0xb0, 0x3a, 0x11, 0x9f, ++ 0x77, 0xbd, 0x7d, 0xb3, 0xb0, 0xab, 0xb8, 0xbc, 0x29, 0x12, 0xf2, 0xa5, ++ 0x08, 0xfb, 0xc1, 0x75, 0x64, 0xf5, 0x24, 0xb9, 0x53, 0x28, 0xc6, 0x1d, ++ 0x6c, 0xa9, 0x25, 0xbd, 0x76, 0x08, 0xf3, 0x08, 0x3f, 0x8b, 0xf0, 0x47, ++ 0x3c, 0xb0, 0x5f, 0x63, 0x8f, 0xfd, 0x5f, 0x0d, 0xf6, 0x2d, 0x39, 0x10, ++ 0x68, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 usem_int_table_data_e1h[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xfb, 0x51, ++ 0xcf, 0xc0, 0xf0, 0x03, 0x8a, 0xd7, 0x98, 0x33, 0x30, 0x38, 0x5a, 0x31, ++ 0x30, 0xe4, 0x59, 0x33, 0x30, 0x5c, 0x07, 0xe2, 0x30, 0x73, 0x84, 0xdc, ++ 0x4b, 0x71, 0x04, 0x9b, 0x9a, 0xf8, 0xa7, 0x3c, 0x65, 0xfa, 0x37, 0x48, ++ 0x32, 0x30, 0x6c, 0x02, 0xe2, 0x2d, 0x40, 0xbc, 0x4d, 0x92, 0x74, 0xfd, ++ 0xb7, 0xb4, 0x10, 0xec, 0xbd, 0xaa, 0x0c, 0x0c, 0xb7, 0x81, 0xfc, 0x6e, ++ 0x20, 0xfd, 0x5d, 0x9d, 0x81, 0x61, 0x17, 0x90, 0x7d, 0x07, 0x88, 0x2f, ++ 0x83, 0xf8, 0x40, 0xcc, 0xac, 0xc6, 0xc0, 0x20, 0x0e, 0xe4, 0xab, 0x00, ++ 0x69, 0x3f, 0x20, 0xd6, 0x07, 0xe2, 0xbb, 0x40, 0x7e, 0x9a, 0x1a, 0x6e, ++ 0xf3, 0xef, 0x69, 0xe1, 0xb7, 0x7f, 0x9b, 0x06, 0x2a, 0xff, 0x1d, 0x1a, ++ 0xff, 0x92, 0x3a, 0x7e, 0xfd, 0x99, 0x9a, 0xf8, 0xe5, 0xdf, 0x11, 0x90, ++ 0xc7, 0x86, 0x1f, 0xdb, 0x91, 0x1f, 0x1f, 0xea, 0xf6, 0xb4, 0x49, 0x27, ++ 0xb4, 0xc2, 0x07, 0xd0, 0xd2, 0xf5, 0x4e, 0x13, 0x06, 0x86, 0x0b, 0xa6, ++ 0x0c, 0x0c, 0x22, 0xd0, 0xb4, 0xbf, 0x17, 0x49, 0x5e, 0x0d, 0x28, 0xb6, ++ 0xcb, 0x04, 0xc2, 0x9e, 0xab, 0x07, 0x4c, 0x7b, 0x66, 0x40, 0x3e, 0x8e, ++ 0x7c, 0x31, 0x0f, 0x28, 0xbf, 0x11, 0x28, 0x6f, 0x64, 0x8e, 0xdf, 0x7e, ++ 0x05, 0x66, 0x54, 0xbe, 0x00, 0x2f, 0xa6, 0x9a, 0x6f, 0x4c, 0x08, 0xf6, ++ 0x04, 0x21, 0x54, 0xb9, 0xc3, 0xc2, 0x98, 0xea, 0xb9, 0x44, 0x19, 0x18, ++ 0x00, 0x65, 0x83, 0x84, 0x86, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 usem_pram_data_e1h[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xe5, 0x7d, ++ 0x0d, 0x78, 0x54, 0xd5, 0xb5, 0xf6, 0x3e, 0x73, 0xce, 0x9c, 0x99, 0x64, ++ 0x4e, 0x26, 0x93, 0x10, 0xc2, 0x40, 0x02, 0x4e, 0x7e, 0xd0, 0xa8, 0x09, ++ 0x8e, 0x10, 0x30, 0x26, 0x13, 0x72, 0x26, 0x3f, 0x24, 0x24, 0x01, 0xc3, ++ 0x4f, 0x69, 0x5a, 0x69, 0x9d, 0xa0, 0x45, 0xda, 0x82, 0x22, 0xda, 0x5e, ++ 0x6f, 0x2f, 0x5f, 0x19, 0x7e, 0x1a, 0x22, 0x45, 0xc5, 0x16, 0xad, 0xda, ++ 0xde, 0xde, 0x81, 0x2a, 0x4f, 0xdb, 0xeb, 0x73, 0x9f, 0x60, 0xa9, 0xe5, ++ 0x86, 0x44, 0x26, 0x10, 0x10, 0x0d, 0x3f, 0x11, 0xad, 0xde, 0x7e, 0xb6, ++ 0xdf, 0x8d, 0xda, 0x8b, 0xa1, 0x0d, 0x38, 0xc1, 0x60, 0xe9, 0xf7, 0x60, ++ 0xf9, 0xf6, 0x5a, 0x7b, 0xef, 0xcc, 0x9c, 0x93, 0x99, 0x04, 0xd4, 0xef, ++ 0xde, 0xef, 0x07, 0x1f, 0x9f, 0x93, 0x73, 0xce, 0x3e, 0x7b, 0xaf, 0xbd, ++ 0xf6, 0x5a, 0x6b, 0xbf, 0x6b, 0xed, 0xb5, 0xf7, 0x58, 0xc9, 0x44, 0xe2, ++ 0xaa, 0x20, 0xe4, 0x0a, 0xfc, 0xa3, 0x57, 0xdf, 0x64, 0x42, 0xe8, 0xa3, ++ 0x91, 0xab, 0x78, 0x5e, 0x69, 0x27, 0x41, 0xc7, 0x2d, 0x84, 0xa4, 0xd9, ++ 0xf7, 0xf6, 0xce, 0xc8, 0x20, 0x64, 0x9e, 0x26, 0x7b, 0x6b, 0x3d, 0x84, ++ 0x4c, 0xb2, 0xb7, 0xf4, 0x90, 0x62, 0x42, 0xca, 0x89, 0xcd, 0x63, 0xcb, ++ 0x21, 0xa4, 0x5b, 0xfa, 0x4d, 0xef, 0x0c, 0x7a, 0x7f, 0x34, 0xc5, 0xea, ++ 0xb5, 0x11, 0xf8, 0xf7, 0x00, 0x21, 0x73, 0x08, 0x59, 0x67, 0xa7, 0x7f, ++ 0xd2, 0xf2, 0x47, 0x2f, 0xd2, 0x2b, 0xfd, 0xfe, 0xe8, 0x5f, 0x2d, 0x21, ++ 0x22, 0x11, 0x52, 0x23, 0x37, 0x12, 0x09, 0xbe, 0xb7, 0x4b, 0xbc, 0xbc, ++ 0xae, 0x2d, 0xc8, 0x24, 0xa4, 0x9a, 0xb0, 0x7f, 0x73, 0x2f, 0x92, 0x6a, ++ 0x5a, 0x8c, 0x54, 0xbb, 0xef, 0x6d, 0x24, 0x33, 0x08, 0xa9, 0x72, 0xd1, ++ 0x52, 0x76, 0xf6, 0xee, 0x0a, 0x2b, 0x4f, 0x08, 0x2d, 0x5f, 0x46, 0x58, ++ 0xfd, 0xba, 0xdd, 0xf8, 0xbe, 0x8c, 0x6c, 0x1f, 0x92, 0x9d, 0x70, 0x17, ++ 0x91, 0x9b, 0x8a, 0x68, 0x7d, 0x97, 0x55, 0xe3, 0x7b, 0x77, 0xed, 0x07, ++ 0xc4, 0x09, 0xe5, 0x62, 0x9e, 0x43, 0x3f, 0xe0, 0x0f, 0xca, 0x83, 0xeb, ++ 0x49, 0x4a, 0xc6, 0x19, 0x07, 0xfd, 0xfb, 0x36, 0x72, 0xdb, 0x15, 0x99, ++ 0x5e, 0x95, 0x09, 0x84, 0xdc, 0x1e, 0xe5, 0x8b, 0xf9, 0x4a, 0x48, 0x10, ++ 0xf9, 0xd6, 0xc1, 0xbf, 0x57, 0x48, 0xd3, 0x0c, 0xb8, 0x27, 0xe4, 0x45, ++ 0x6c, 0x3f, 0x5d, 0xf0, 0xb1, 0xae, 0x9f, 0xb8, 0x69, 0xbf, 0x33, 0x4a, ++ 0x88, 0xb7, 0x96, 0x76, 0x70, 0x52, 0x9d, 0xde, 0x0d, 0x7c, 0x29, 0xab, ++ 0x56, 0x3d, 0x36, 0x7a, 0xdf, 0x5d, 0x33, 0x67, 0x72, 0xbf, 0x46, 0xc8, ++ 0x0f, 0xcf, 0xb5, 0x67, 0x91, 0x42, 0xfa, 0x79, 0x68, 0x35, 0xf2, 0x31, ++ 0x83, 0xf3, 0xb1, 0xfb, 0xdc, 0x4b, 0xef, 0xdc, 0x47, 0xbf, 0xf7, 0xd5, ++ 0x11, 0xaf, 0x8d, 0xde, 0x1f, 0xb0, 0x7a, 0x27, 0x37, 0x15, 0x8e, 0xa6, ++ 0xc7, 0x57, 0x97, 0x9e, 0x44, 0x68, 0x3d, 0x4f, 0x34, 0x1d, 0x72, 0x60, ++ 0x3d, 0x84, 0xfc, 0xed, 0x4a, 0x26, 0xaf, 0x27, 0x8f, 0x90, 0xce, 0xa6, ++ 0xdc, 0xd4, 0x40, 0x9c, 0xef, 0xc4, 0xf5, 0xf1, 0x0d, 0x2e, 0x42, 0x6c, ++ 0xd1, 0xfb, 0x1d, 0x3a, 0xa9, 0x6b, 0xd7, 0x46, 0x97, 0x7b, 0x09, 0x06, ++ 0x73, 0x36, 0x54, 0xbf, 0x1c, 0xe9, 0x2c, 0xe3, 0xbc, 0xfc, 0xa1, 0x44, ++ 0x9a, 0xdb, 0xb1, 0xdd, 0x66, 0x1c, 0xa7, 0x03, 0x9c, 0xfe, 0x1e, 0xfd, ++ 0x90, 0xa3, 0xbf, 0x10, 0xde, 0x87, 0x1d, 0x16, 0xda, 0x8f, 0xe0, 0x90, ++ 0x85, 0x3c, 0x4f, 0xab, 0xe8, 0x1c, 0xac, 0x4c, 0x06, 0x7a, 0x37, 0xe9, ++ 0x96, 0x30, 0x3c, 0xef, 0x1c, 0x54, 0x43, 0xc0, 0x0f, 0xe2, 0x6e, 0xcf, ++ 0x5a, 0x54, 0x34, 0x9a, 0xfe, 0x03, 0x43, 0x2b, 0x66, 0x62, 0xbf, 0x02, ++ 0xab, 0x0d, 0xed, 0xfe, 0x60, 0x90, 0xf6, 0x57, 0x83, 0xfe, 0xbd, 0xe8, ++ 0x98, 0x47, 0xeb, 0xb9, 0x30, 0x68, 0x71, 0xc9, 0x74, 0x5c, 0x9f, 0xe0, ++ 0xcf, 0x0f, 0x04, 0xda, 0x1d, 0x2e, 0xf8, 0x6e, 0x20, 0x1d, 0xc7, 0xf3, ++ 0xf1, 0x0d, 0xf4, 0xef, 0x1b, 0x12, 0xf3, 0xe3, 0xf1, 0xb9, 0xdf, 0xc8, ++ 0x0d, 0x68, 0x50, 0xce, 0x6e, 0xe4, 0xc7, 0xe0, 0x85, 0x63, 0x79, 0x74, ++ 0xdc, 0x3a, 0x77, 0x2a, 0x5e, 0xe8, 0xd7, 0x78, 0xfc, 0xfc, 0x01, 0x6f, ++ 0x47, 0xdc, 0xa7, 0x7b, 0xc3, 0x55, 0x2e, 0x5a, 0xaf, 0x2f, 0xe2, 0x95, ++ 0x40, 0x8f, 0xd2, 0x07, 0x09, 0x99, 0x90, 0x03, 0x7a, 0xd1, 0x79, 0xd8, ++ 0x09, 0xe3, 0xdb, 0x48, 0x50, 0x2f, 0x7c, 0x4d, 0x95, 0x49, 0xd3, 0x59, ++ 0x3f, 0xbc, 0xb2, 0x07, 0xde, 0x1f, 0x97, 0x41, 0x3e, 0x7c, 0xae, 0x30, ++ 0xf6, 0x63, 0x84, 0x1e, 0xa0, 0xef, 0x06, 0xa0, 0xd3, 0x8d, 0xd7, 0xa7, ++ 0x79, 0x7b, 0x4f, 0xc1, 0x38, 0x62, 0xff, 0x36, 0x25, 0x5d, 0x4f, 0xe9, ++ 0xbd, 0x50, 0xa2, 0x60, 0x3d, 0xbb, 0xf5, 0x4d, 0x7e, 0x05, 0xeb, 0xbb, ++ 0x1c, 0x96, 0x41, 0x1e, 0x57, 0x33, 0x79, 0xca, 0xf0, 0x04, 0x36, 0x5a, ++ 0x81, 0xff, 0xf7, 0x10, 0x6f, 0xd0, 0x03, 0xf5, 0x12, 0xec, 0xf7, 0x4f, ++ 0x79, 0xff, 0x7f, 0xc2, 0xeb, 0x13, 0xed, 0x74, 0x0e, 0xa6, 0xfb, 0x15, ++ 0xa0, 0xaf, 0x99, 0x78, 0x41, 0x4d, 0x6a, 0xe4, 0xf5, 0xdd, 0xf0, 0xbd, ++ 0x6f, 0x15, 0xa3, 0x7f, 0xda, 0xc3, 0x6b, 0x25, 0xe0, 0xdf, 0x75, 0xeb, ++ 0xfb, 0xf1, 0x1a, 0xe2, 0x74, 0xee, 0x80, 0xef, 0x69, 0x81, 0xec, 0xb5, ++ 0x11, 0x09, 0xf8, 0x36, 0xf5, 0xa1, 0x30, 0x5e, 0x77, 0x6e, 0xfc, 0x7d, ++ 0x37, 0xd0, 0x97, 0xba, 0x85, 0x24, 0x81, 0x2d, 0x78, 0xa2, 0xda, 0x92, ++ 0x06, 0xdf, 0x3d, 0x31, 0x6f, 0x4a, 0x12, 0xbc, 0x77, 0x36, 0x51, 0xc5, ++ 0xa7, 0xf6, 0xc0, 0xe7, 0x75, 0x3d, 0xd0, 0x43, 0xfb, 0xb3, 0xb3, 0x5a, ++ 0x41, 0x3a, 0x77, 0x0e, 0x52, 0xfe, 0xd3, 0x72, 0xce, 0xa0, 0xcb, 0x0b, ++ 0x7a, 0xed, 0x0c, 0x7a, 0xf8, 0xd5, 0xeb, 0x85, 0xf2, 0x07, 0x39, 0x3f, ++ 0x0e, 0xf0, 0x76, 0xbb, 0x38, 0x1d, 0xce, 0xa0, 0xce, 0xcb, 0xad, 0x2d, ++ 0x84, 0x72, 0xce, 0x60, 0x10, 0xaf, 0x21, 0xde, 0x4f, 0xe2, 0x59, 0x83, ++ 0x72, 0xb7, 0x8e, 0xcb, 0xdd, 0x41, 0x6b, 0xe0, 0x26, 0xe0, 0x7b, 0xc6, ++ 0x20, 0x71, 0x13, 0xaa, 0xcf, 0x07, 0xce, 0xd7, 0x4f, 0x86, 0x76, 0x45, ++ 0xfd, 0xe6, 0xf2, 0x7b, 0x9e, 0xfd, 0x9f, 0xb3, 0xe0, 0xfd, 0xc4, 0x41, ++ 0xf2, 0xae, 0x75, 0x06, 0x5c, 0xc3, 0x2d, 0xd0, 0xde, 0x0d, 0xd0, 0x0f, ++ 0x27, 0xdc, 0xf7, 0xb5, 0x48, 0x68, 0xa7, 0x42, 0xa8, 0x47, 0xfa, 0x65, ++ 0x0b, 0x21, 0x05, 0x51, 0x3b, 0x95, 0x71, 0xa9, 0x69, 0xfe, 0x1d, 0x1e, ++ 0xb8, 0xab, 0x41, 0x3d, 0x12, 0x76, 0xa0, 0x6c, 0x50, 0xb5, 0x48, 0xa9, ++ 0xb1, 0x7a, 0x56, 0x8d, 0x7a, 0xb0, 0x93, 0xeb, 0x41, 0xf5, 0x60, 0x18, ++ 0xe5, 0x84, 0xea, 0xd9, 0x61, 0x0b, 0xe5, 0x53, 0xf0, 0x1c, 0xd5, 0x33, ++ 0x2a, 0x5f, 0x07, 0x9a, 0x2c, 0x38, 0xde, 0xcf, 0x45, 0x54, 0xb4, 0xc3, ++ 0xa4, 0x20, 0x9c, 0xb5, 0x28, 0x65, 0xb4, 0x1e, 0x75, 0x0e, 0xad, 0x9c, ++ 0x09, 0xfc, 0x16, 0xfa, 0x34, 0xda, 0x7e, 0xfc, 0xbf, 0xa1, 0x5f, 0x3b, ++ 0x69, 0x3f, 0x02, 0x71, 0xec, 0x9a, 0x68, 0x4f, 0xe8, 0x9b, 0xf9, 0xfd, ++ 0xb8, 0xfa, 0xe6, 0x0a, 0xa2, 0xbe, 0x75, 0x52, 0x7d, 0x0b, 0x02, 0x3f, ++ 0x9b, 0x2c, 0x49, 0xf9, 0xa0, 0x7f, 0x6d, 0x16, 0xd4, 0x13, 0x77, 0x75, ++ 0x7b, 0x37, 0xd3, 0x97, 0xd5, 0xa8, 0x6f, 0x19, 0xf7, 0x30, 0x7a, 0x26, ++ 0x2d, 0x0f, 0xa1, 0x1e, 0x8c, 0xa7, 0x77, 0x3b, 0x3d, 0x2e, 0xbf, 0x02, ++ 0xf5, 0x37, 0x33, 0x3d, 0xed, 0x1c, 0x7c, 0x6f, 0xa3, 0x0d, 0xc6, 0x63, ++ 0x39, 0xe1, 0x76, 0xe2, 0x72, 0x37, 0xdc, 0xfb, 0x1e, 0x66, 0x7a, 0x6d, ++ 0xd6, 0x33, 0xb3, 0x1e, 0xa6, 0xfa, 0xfa, 0x50, 0x3f, 0x73, 0xb6, 0x44, ++ 0x08, 0x5c, 0x3d, 0x9b, 0x1b, 0x51, 0xae, 0x69, 0x2b, 0x49, 0xa8, 0x7f, ++ 0x09, 0xf4, 0xb0, 0x13, 0xf4, 0xb0, 0xf8, 0xff, 0x1f, 0x3d, 0xac, 0x82, ++ 0x79, 0x9c, 0xea, 0x5d, 0x9a, 0x76, 0x6b, 0x8f, 0x8b, 0xf6, 0x7b, 0x7e, ++ 0x84, 0x30, 0x3c, 0xa4, 0x3d, 0xd1, 0x03, 0xf3, 0x78, 0x4d, 0xb6, 0x8d, ++ 0xcd, 0xe3, 0x53, 0xdf, 0xbe, 0xf3, 0x7e, 0x7a, 0x7f, 0xcc, 0xea, 0x40, ++ 0xfe, 0x1f, 0x9b, 0x48, 0x1f, 0x16, 0xc3, 0xbd, 0x8c, 0x7a, 0xd7, 0x9d, ++ 0xb3, 0x35, 0x7b, 0x1d, 0x7d, 0x3f, 0x3f, 0x43, 0xc2, 0xf7, 0x84, 0xac, ++ 0x42, 0xfd, 0xae, 0x15, 0x78, 0x09, 0x1e, 0x51, 0xfd, 0xf1, 0xf7, 0x4b, ++ 0x64, 0x4e, 0x3a, 0x94, 0x7b, 0x7f, 0x47, 0x15, 0xfd, 0xfe, 0xd5, 0x01, ++ 0xe2, 0x85, 0x57, 0xaf, 0x66, 0xcb, 0x58, 0xdf, 0xe1, 0x41, 0xc2, 0xf4, ++ 0x98, 0xeb, 0x67, 0x2d, 0xef, 0xef, 0x61, 0xfe, 0xfe, 0xc2, 0x25, 0x12, ++ 0x02, 0xfd, 0xac, 0x00, 0x48, 0x42, 0x9f, 0x7f, 0x7c, 0x36, 0x32, 0xcd, ++ 0x4e, 0x5f, 0x7d, 0x68, 0xb9, 0x5c, 0x44, 0x72, 0xe9, 0x7c, 0x2c, 0xf8, ++ 0xc5, 0x71, 0x46, 0x0d, 0xd7, 0xff, 0x57, 0x33, 0x64, 0x1d, 0xec, 0xc6, ++ 0xe1, 0xf5, 0x29, 0x21, 0x92, 0x83, 0xf5, 0x85, 0x41, 0xde, 0x5e, 0x7d, ++ 0xd8, 0x16, 0x92, 0x69, 0x7b, 0x17, 0xf2, 0xf3, 0x5e, 0x08, 0x13, 0xc0, ++ 0x7f, 0x91, 0xeb, 0xd7, 0xd1, 0xf7, 0x3d, 0xae, 0x8f, 0x52, 0x62, 0xf5, ++ 0x73, 0x80, 0xcb, 0xef, 0x9f, 0xb8, 0xfc, 0x0e, 0x72, 0x3c, 0xb1, 0xe3, ++ 0xe6, 0xa6, 0x45, 0x12, 0xe5, 0xef, 0xab, 0xf9, 0x79, 0xa8, 0x5f, 0x17, ++ 0xf2, 0x3f, 0x9a, 0x46, 0x28, 0xab, 0xef, 0xcf, 0xfb, 0xcb, 0x19, 0xb8, ++ 0x12, 0x12, 0xb6, 0x02, 0x5e, 0x32, 0xd7, 0x23, 0xbe, 0x7f, 0xd5, 0x1d, ++ 0xf8, 0xb2, 0x44, 0x71, 0xd5, 0x40, 0xe8, 0x7d, 0x27, 0x8c, 0xe7, 0xb9, ++ 0x7d, 0x1f, 0xcd, 0x80, 0x2b, 0x71, 0x4f, 0x40, 0xdc, 0x35, 0x1e, 0x3e, ++ 0xf3, 0x09, 0x1c, 0x16, 0xe9, 0xdb, 0x0c, 0x38, 0x84, 0x54, 0x53, 0x39, ++ 0x99, 0x13, 0x95, 0x93, 0x49, 0x91, 0xbe, 0xc3, 0xc0, 0x37, 0xdf, 0x30, ++ 0xc3, 0x63, 0xa4, 0x6e, 0x0d, 0x8e, 0x4b, 0xb9, 0x8b, 0xf1, 0xa5, 0xfb, ++ 0xe2, 0x5b, 0x59, 0xf0, 0x5d, 0x07, 0xe7, 0x5b, 0xd7, 0x50, 0x5f, 0x16, ++ 0xda, 0xc7, 0x3a, 0x63, 0x3d, 0x5d, 0xd6, 0xfe, 0xe5, 0x4d, 0xac, 0x7e, ++ 0xfc, 0xde, 0xe7, 0x62, 0xe3, 0x2a, 0xe8, 0x79, 0x99, 0xf7, 0xeb, 0x69, ++ 0x49, 0x22, 0x0c, 0x27, 0xb2, 0xf1, 0xf3, 0xf1, 0xef, 0xe7, 0x2a, 0x7d, ++ 0x13, 0x6e, 0xa1, 0x74, 0xcc, 0x3d, 0x26, 0x7b, 0x37, 0xd2, 0x47, 0x73, ++ 0x07, 0xfa, 0xab, 0x49, 0x1c, 0x3b, 0xb4, 0x5b, 0x4a, 0x43, 0x79, 0xad, ++ 0xb8, 0x64, 0x94, 0xd7, 0xae, 0x8b, 0x47, 0x65, 0xe0, 0x0b, 0xa5, 0x57, ++ 0x06, 0x7a, 0xcb, 0x23, 0x7d, 0x32, 0xb3, 0xe3, 0x4c, 0xce, 0x7c, 0x5c, ++ 0xce, 0xca, 0x23, 0xa7, 0x0d, 0xf6, 0x5d, 0xb4, 0xdf, 0x15, 0x39, 0xdd, ++ 0x00, 0xed, 0x5f, 0x18, 0x60, 0xf6, 0x2a, 0x11, 0x5f, 0x85, 0xfc, 0x1c, ++ 0xe2, 0xe3, 0xfc, 0xb2, 0xd0, 0x57, 0x12, 0x72, 0xdc, 0x42, 0xe5, 0xe5, ++ 0x08, 0xa5, 0x7f, 0xdb, 0x18, 0xdf, 0xd7, 0xb8, 0x64, 0x03, 0xdd, 0x42, ++ 0xff, 0xaa, 0xec, 0x0e, 0x03, 0x5e, 0xaf, 0xb8, 0x94, 0x6e, 0xc2, 0xff, ++ 0x46, 0x7a, 0x4b, 0x95, 0x30, 0xf2, 0xab, 0x14, 0xf8, 0xe5, 0x49, 0xcc, ++ 0xaf, 0xf5, 0x52, 0x3a, 0xd6, 0x5f, 0x36, 0xf0, 0xe9, 0xf8, 0x65, 0xb6, ++ 0x2b, 0xa2, 0xde, 0x2e, 0xe0, 0x63, 0xe1, 0x68, 0xba, 0x08, 0x08, 0xb5, ++ 0xa0, 0x5b, 0xfe, 0x3f, 0x9f, 0xaf, 0x9d, 0xf0, 0x07, 0xf3, 0x5f, 0x8e, ++ 0x82, 0x9e, 0x92, 0xfe, 0xbd, 0x72, 0x53, 0x0a, 0xcc, 0x27, 0x1a, 0xda, ++ 0x93, 0xb2, 0x6a, 0x89, 0xe1, 0x72, 0xde, 0xcf, 0x46, 0xf8, 0x96, 0x36, ++ 0x55, 0x27, 0xf4, 0xca, 0x23, 0xa1, 0x9f, 0x57, 0xef, 0x93, 0x42, 0xb5, ++ 0x80, 0x37, 0xbc, 0x3f, 0x43, 0x3f, 0xf1, 0x42, 0xb1, 0xcd, 0x03, 0x76, ++ 0x68, 0x92, 0xe7, 0x09, 0xa5, 0x3f, 0x46, 0xde, 0xea, 0xf9, 0xf7, 0x23, ++ 0x7c, 0xdc, 0xa0, 0x63, 0x3f, 0xbb, 0x67, 0xbf, 0x9d, 0x05, 0xe5, 0xba, ++ 0xa6, 0x6f, 0xcc, 0x86, 0x71, 0x98, 0xef, 0x79, 0xdb, 0xb1, 0x8e, 0xf2, ++ 0xff, 0x28, 0xd7, 0x9b, 0x8e, 0x0d, 0x75, 0x58, 0xae, 0xec, 0x12, 0x79, ++ 0xf4, 0x56, 0x18, 0x97, 0x7c, 0xa6, 0x67, 0x73, 0x79, 0x5f, 0x7a, 0x38, ++ 0xdf, 0x0e, 0x71, 0xbb, 0x71, 0x90, 0xcf, 0x9b, 0x6f, 0x6d, 0x08, 0xe0, ++ 0xf5, 0xcd, 0x0d, 0xab, 0xf0, 0x7a, 0x7a, 0xc3, 0x5a, 0xbc, 0xbe, 0x7a, ++ 0xe9, 0x45, 0x0d, 0xc6, 0xaf, 0xb7, 0x20, 0x0f, 0xe7, 0xaf, 0x3a, 0xa5, ++ 0x5d, 0x89, 0xe7, 0x57, 0x95, 0x0e, 0x1a, 0xe5, 0xe6, 0x65, 0x0f, 0xc5, ++ 0x3b, 0xb4, 0x7c, 0xc3, 0xe0, 0x8a, 0xed, 0xb7, 0xd2, 0x7e, 0x1f, 0xbf, ++ 0x64, 0x41, 0xfb, 0x7c, 0xbc, 0x20, 0x6f, 0x4c, 0xbc, 0x22, 0xec, 0x87, ++ 0x28, 0xf7, 0x8a, 0xfb, 0x67, 0x55, 0xc0, 0xb7, 0xc6, 0x01, 0x4a, 0x6e, ++ 0xce, 0xe8, 0xf2, 0x66, 0x79, 0x2d, 0x23, 0x52, 0x3b, 0xe0, 0xbf, 0x32, ++ 0xef, 0xeb, 0x0a, 0xa1, 0xf6, 0x72, 0x41, 0xf1, 0x2e, 0x2d, 0x16, 0xc7, ++ 0x1c, 0x38, 0x97, 0x59, 0x04, 0xf5, 0x1e, 0x90, 0xfe, 0xb0, 0x64, 0x96, ++ 0x27, 0x31, 0x1d, 0x65, 0xbe, 0x3e, 0xec, 0xe7, 0x82, 0xf0, 0xef, 0x14, ++ 0x4f, 0x4a, 0xe2, 0x72, 0x27, 0x94, 0xbe, 0xc6, 0x59, 0xe8, 0xa7, 0x32, ++ 0xfd, 0x2a, 0xf3, 0xbe, 0x5b, 0xad, 0xd3, 0xf6, 0x6a, 0x0b, 0x77, 0x35, ++ 0xa2, 0x5c, 0x0c, 0x2b, 0x16, 0x90, 0x8b, 0xc6, 0xc2, 0xbd, 0x7c, 0x7c, ++ 0x5d, 0x38, 0x1e, 0x0b, 0xc4, 0x7c, 0x56, 0x2c, 0xd7, 0x85, 0x80, 0x9e, ++ 0xc1, 0x0b, 0x48, 0x67, 0x6f, 0xa1, 0x3c, 0x11, 0xe8, 0xdb, 0x66, 0x91, ++ 0x51, 0x2e, 0x17, 0x78, 0x6c, 0x88, 0x67, 0x13, 0xb6, 0x3f, 0xac, 0x90, ++ 0x30, 0xe8, 0x97, 0x12, 0xc6, 0x71, 0x3a, 0x4e, 0xeb, 0x01, 0xb9, 0x38, ++ 0x41, 0xed, 0x1e, 0x7b, 0xde, 0xc7, 0xee, 0x69, 0xbd, 0xf0, 0xbe, 0x3b, ++ 0xc7, 0xa6, 0x79, 0x81, 0x9f, 0x6e, 0x11, 0x8f, 0x58, 0x65, 0x90, 0x8f, ++ 0xc6, 0xfc, 0x59, 0xc7, 0xbd, 0x94, 0xee, 0x5e, 0xb7, 0x8c, 0xf8, 0xb2, ++ 0xf7, 0x52, 0xa5, 0x92, 0x46, 0xef, 0x4f, 0xc0, 0xfc, 0xea, 0x89, 0xca, ++ 0x67, 0x19, 0x97, 0xcf, 0x13, 0x30, 0xee, 0x20, 0xc7, 0x21, 0x19, 0xe7, ++ 0x3f, 0x81, 0x97, 0x45, 0x7d, 0x5d, 0x97, 0x72, 0x1f, 0x2d, 0xa6, 0xed, ++ 0x9d, 0x08, 0x59, 0xe3, 0x7e, 0xdf, 0x54, 0x6d, 0xd4, 0xc7, 0x3b, 0xdc, ++ 0x0e, 0xc3, 0x7d, 0x75, 0xf6, 0x04, 0xc3, 0xfd, 0x89, 0xc1, 0x99, 0x6f, ++ 0x36, 0x41, 0x7b, 0x94, 0x7e, 0xc0, 0x73, 0x24, 0xb8, 0xda, 0x40, 0x7f, ++ 0x17, 0xd8, 0x7b, 0x68, 0xcf, 0x25, 0xe1, 0xfc, 0x7f, 0xf4, 0x72, 0xf5, ++ 0xe0, 0xfd, 0x50, 0x2e, 0x64, 0xa4, 0xcb, 0x4c, 0x47, 0xef, 0xa5, 0xdc, ++ 0x27, 0x97, 0xd2, 0x7a, 0x8f, 0xef, 0x93, 0x51, 0x4e, 0xab, 0xdd, 0x46, ++ 0xba, 0xaa, 0x2e, 0xbe, 0x79, 0x1c, 0xe2, 0x38, 0x0d, 0xd4, 0xbe, 0x00, ++ 0xdf, 0x5e, 0xd6, 0x15, 0x1d, 0xfa, 0x7d, 0x62, 0x5f, 0x4a, 0x68, 0x23, ++ 0x95, 0xcb, 0x97, 0x0b, 0x5f, 0x77, 0x00, 0x6e, 0xa0, 0xff, 0xb4, 0x05, ++ 0xb4, 0x9d, 0x2a, 0xc2, 0xc6, 0xb7, 0x32, 0xc3, 0x58, 0xcf, 0xf1, 0xc1, ++ 0xf7, 0xbe, 0x0f, 0x76, 0xea, 0x82, 0x5d, 0x46, 0x3b, 0x57, 0xf9, 0xd7, ++ 0x43, 0x5b, 0x00, 0x5e, 0x9d, 0x2a, 0x7e, 0xb0, 0x07, 0xf8, 0x7c, 0x80, ++ 0x48, 0xc8, 0xa7, 0xf2, 0x73, 0xbb, 0x65, 0xa8, 0x6f, 0x59, 0xc8, 0xf8, ++ 0xfd, 0xd2, 0xe5, 0x46, 0xfe, 0xac, 0x59, 0x3a, 0xc1, 0x64, 0xff, 0x8d, ++ 0xf1, 0xa5, 0x2a, 0x0f, 0x8b, 0x13, 0xcd, 0xf5, 0x0e, 0x61, 0x7d, 0xa5, ++ 0x10, 0xff, 0xa1, 0xf7, 0x95, 0x9a, 0x31, 0x2e, 0x34, 0x17, 0x8c, 0x41, ++ 0x4c, 0xbd, 0xe5, 0xa6, 0xb8, 0x50, 0xa9, 0x87, 0xc5, 0x85, 0x4a, 0x21, ++ 0x2e, 0x24, 0xca, 0xe5, 0x90, 0x51, 0x76, 0x9f, 0xde, 0x63, 0xfb, 0xe6, ++ 0x79, 0xdd, 0xac, 0xdf, 0x09, 0xf5, 0xdf, 0x42, 0x56, 0x41, 0x3c, 0x85, ++ 0x44, 0x16, 0x8f, 0x83, 0x5b, 0x36, 0xf1, 0xf8, 0x8a, 0xd1, 0xde, 0x12, ++ 0x65, 0xa7, 0x04, 0xf2, 0x50, 0xca, 0xdb, 0xef, 0xb0, 0xb6, 0x3b, 0x80, ++ 0x2e, 0xdf, 0xad, 0xcc, 0x7e, 0x91, 0x48, 0x7a, 0xdc, 0x78, 0x95, 0xd9, ++ 0x8e, 0x10, 0xf2, 0x20, 0xca, 0x95, 0xe0, 0x23, 0x71, 0x05, 0x49, 0xc6, ++ 0x1c, 0xe8, 0x3f, 0x2f, 0x63, 0xb6, 0x7f, 0x9c, 0x2f, 0x6d, 0x74, 0x38, ++ 0xae, 0xe0, 0x3c, 0x10, 0xe4, 0xf8, 0xc5, 0x13, 0x57, 0xdf, 0xcd, 0xdf, ++ 0x67, 0x73, 0x7d, 0x9f, 0x37, 0x40, 0xed, 0x66, 0x06, 0x8c, 0x97, 0xec, ++ 0x02, 0xbb, 0x71, 0xfc, 0x12, 0xd1, 0x40, 0x1f, 0x4f, 0x51, 0x79, 0x67, ++ 0x2d, 0xf7, 0x5f, 0x89, 0x95, 0xdb, 0x86, 0x81, 0x76, 0x94, 0x4b, 0x5a, ++ 0x1e, 0x46, 0x90, 0x96, 0xf7, 0xa2, 0xfe, 0x36, 0x4d, 0x66, 0xfa, 0xdb, ++ 0x9d, 0x53, 0xab, 0xa4, 0x31, 0xfb, 0x19, 0x57, 0xdf, 0xcd, 0x7a, 0x30, ++ 0x40, 0x82, 0x4f, 0x15, 0xd3, 0x71, 0x3d, 0x9e, 0x9f, 0xf7, 0xe4, 0x52, ++ 0xfa, 0x5d, 0xef, 0x3e, 0x61, 0x07, 0x2c, 0x3a, 0xea, 0xd5, 0x3e, 0x86, ++ 0x7b, 0x4f, 0x0c, 0xae, 0x43, 0x79, 0xbd, 0x40, 0xe5, 0x15, 0xd8, 0x3e, ++ 0x5a, 0xef, 0x4f, 0x6b, 0xb1, 0xf3, 0xfe, 0x7f, 0x96, 0xbe, 0x9b, 0xf5, ++ 0x7c, 0x44, 0xff, 0x47, 0xe9, 0x3b, 0xb3, 0x5b, 0xc7, 0x87, 0x2d, 0xd8, ++ 0x9f, 0xaa, 0x8b, 0x0a, 0xd6, 0xd3, 0x70, 0x99, 0xe0, 0x3c, 0x6e, 0xd6, ++ 0xff, 0x13, 0xdc, 0x7f, 0x7b, 0x59, 0x7f, 0x53, 0xf3, 0xc2, 0x7c, 0x58, ++ 0xf8, 0x3e, 0xfa, 0xc7, 0xe4, 0x53, 0xeb, 0x3b, 0xf3, 0x43, 0x0e, 0x0c, ++ 0x10, 0x6c, 0xbf, 0xfc, 0xdc, 0x7b, 0x32, 0xed, 0xf9, 0xe7, 0xa6, 0xef, ++ 0x42, 0xcf, 0x85, 0xde, 0x5e, 0xb3, 0xbe, 0xff, 0x27, 0xe9, 0xb9, 0xf9, ++ 0xf9, 0xb7, 0x2d, 0x1c, 0xf7, 0x27, 0xd0, 0xd3, 0xa8, 0xfe, 0x07, 0xb1, ++ 0xdc, 0xe6, 0x14, 0x52, 0x00, 0x71, 0xb6, 0x0e, 0x29, 0xd9, 0xbb, 0x29, ++ 0x07, 0xf4, 0x9d, 0xc5, 0x7d, 0xcc, 0xe5, 0x27, 0xc8, 0x22, 0x1e, 0x6b, ++ 0x0f, 0xfe, 0x91, 0xf6, 0xab, 0x85, 0x0a, 0x4b, 0x2a, 0x65, 0xf5, 0x1a, ++ 0xd2, 0x3f, 0x0d, 0xe4, 0x61, 0xe2, 0x64, 0x0f, 0xd6, 0x77, 0x9f, 0xa5, ++ 0x3f, 0x13, 0xee, 0x3f, 0x24, 0x91, 0xcc, 0x9b, 0x65, 0xc0, 0xcf, 0x64, ++ 0x3f, 0xcc, 0xbf, 0x92, 0x4e, 0xc8, 0xc3, 0x94, 0x24, 0xc9, 0xe3, 0x22, ++ 0xcb, 0x67, 0x12, 0xf2, 0xb8, 0x1c, 0xb0, 0xcb, 0xb4, 0x3e, 0x69, 0x20, ++ 0xfc, 0x57, 0x89, 0xf2, 0x99, 0x3c, 0x44, 0x3c, 0x80, 0x07, 0x6f, 0x90, ++ 0x02, 0x0e, 0x78, 0x6e, 0xa3, 0x7c, 0xd2, 0x68, 0x79, 0xa2, 0x9c, 0x46, ++ 0x9c, 0x48, 0xfd, 0x37, 0xe4, 0xd7, 0x42, 0xae, 0x74, 0x0b, 0xed, 0x5a, ++ 0x18, 0xe3, 0xf0, 0x25, 0xd6, 0xc1, 0x7e, 0xc1, 0x77, 0x9c, 0x3f, 0x96, ++ 0xbb, 0xce, 0xdc, 0x4c, 0xeb, 0x25, 0x61, 0xe9, 0xca, 0xcd, 0xd1, 0x7e, ++ 0xee, 0xb1, 0x86, 0xb2, 0xbc, 0x1a, 0xf4, 0x33, 0xf4, 0xe3, 0xfb, 0x20, ++ 0x6e, 0xf5, 0x8c, 0xea, 0x7d, 0x3e, 0x0e, 0xdf, 0x2d, 0x9f, 0xb2, 0x9f, ++ 0x60, 0x7e, 0x90, 0x9f, 0x16, 0xc6, 0xcf, 0xa0, 0x25, 0xd9, 0xfb, 0x7c, ++ 0x1c, 0xbc, 0x35, 0xff, 0xda, 0xeb, 0x7f, 0x2b, 0x99, 0x5e, 0xcb, 0x80, ++ 0x8f, 0xb7, 0x8c, 0xe6, 0xa3, 0x34, 0x48, 0xf9, 0x07, 0x7c, 0x50, 0xfe, ++ 0x76, 0x05, 0xfc, 0xc4, 0x32, 0x37, 0x93, 0x2f, 0xf9, 0x43, 0x55, 0x87, ++ 0x38, 0x0d, 0x91, 0xed, 0xa1, 0xe9, 0x71, 0xe8, 0x58, 0xc3, 0xe9, 0x78, ++ 0x5c, 0xd6, 0x6f, 0xa3, 0xc8, 0x86, 0xc8, 0x55, 0xed, 0xc8, 0x9f, 0x03, ++ 0x30, 0xfe, 0x1a, 0xf0, 0x2f, 0x83, 0x7c, 0x3b, 0x46, 0xbe, 0xe6, 0xc9, ++ 0x2a, 0xd2, 0x25, 0x37, 0x90, 0xb5, 0x38, 0xbf, 0x90, 0xb0, 0x05, 0xec, ++ 0xc8, 0x78, 0xe3, 0x61, 0x55, 0x88, 0x22, 0xc3, 0x38, 0xf6, 0x5d, 0x41, ++ 0xbb, 0xdb, 0xca, 0xe9, 0xb3, 0xd1, 0xe7, 0xda, 0xcc, 0xc4, 0xe3, 0x25, ++ 0x37, 0x78, 0x23, 0x61, 0x3a, 0x4e, 0xe4, 0x43, 0x36, 0x4e, 0x07, 0xe6, ++ 0x1b, 0xe5, 0x72, 0x3d, 0xa7, 0xff, 0x41, 0x4e, 0x17, 0x98, 0x27, 0xa8, ++ 0xbf, 0x14, 0xea, 0xa7, 0xfc, 0x92, 0xff, 0xac, 0xae, 0x8d, 0x37, 0x4f, ++ 0x6c, 0x17, 0xfc, 0xe7, 0xfc, 0x32, 0x97, 0x3f, 0xf0, 0x25, 0xd6, 0x7f, ++ 0x51, 0x7e, 0xab, 0xcc, 0xf4, 0x29, 0x78, 0xed, 0xe3, 0xb6, 0x6c, 0x52, ++ 0x5e, 0xe2, 0x71, 0x13, 0xf2, 0x2e, 0x0d, 0x1e, 0x4d, 0x34, 0x7e, 0x6b, ++ 0x43, 0x71, 0xf4, 0x7b, 0x8e, 0x6c, 0xe1, 0xfd, 0x0d, 0x4a, 0x57, 0xa3, ++ 0x0f, 0xf3, 0xb8, 0x5c, 0xca, 0x55, 0x74, 0xdc, 0xa0, 0x7f, 0x35, 0x46, ++ 0x3e, 0x6e, 0xe6, 0xfd, 0x5a, 0xce, 0xeb, 0xbd, 0x4b, 0xd2, 0xff, 0x1e, ++ 0xe4, 0xe1, 0x06, 0xa9, 0xe9, 0x1f, 0xe0, 0x4a, 0xaa, 0xfb, 0x50, 0xff, ++ 0x40, 0xc6, 0xa1, 0xdc, 0xcd, 0x44, 0xff, 0x6f, 0xfc, 0xfd, 0x06, 0xd0, ++ 0x53, 0x52, 0x67, 0x7c, 0x4f, 0x9f, 0x6f, 0xc2, 0xef, 0x9a, 0xfb, 0x70, ++ 0x7d, 0x4a, 0x3c, 0x3f, 0x2c, 0xe9, 0x5b, 0x64, 0xf6, 0xbe, 0x15, 0xbf, ++ 0xd3, 0x8d, 0xef, 0xa9, 0x1c, 0xb6, 0xc1, 0x73, 0x2a, 0x2f, 0x44, 0x9e, ++ 0x09, 0xcf, 0x19, 0x3f, 0xa9, 0x9c, 0x10, 0x3b, 0xbd, 0x6f, 0xdd, 0x75, ++ 0xf7, 0x97, 0x81, 0xaf, 0xf4, 0xfb, 0xc7, 0xb0, 0x7e, 0x72, 0xda, 0xf0, ++ 0xbd, 0x15, 0x0c, 0x44, 0x3a, 0xbb, 0x4a, 0x33, 0xd9, 0xf5, 0x59, 0x90, ++ 0x3b, 0xee, 0x9f, 0x6e, 0x6e, 0xd6, 0x91, 0xaf, 0x2a, 0x59, 0xcb, 0xfd, ++ 0x67, 0x36, 0x9f, 0xcd, 0xe5, 0xf3, 0x99, 0xfd, 0xaf, 0x6c, 0x1e, 0xbc, ++ 0xe0, 0x52, 0x31, 0xae, 0xa5, 0x24, 0xe9, 0xa1, 0x30, 0xbd, 0xa6, 0xbb, ++ 0xc2, 0x3a, 0xc4, 0x03, 0x27, 0x90, 0xbe, 0x20, 0xf8, 0x63, 0xcb, 0x96, ++ 0xca, 0x06, 0x3b, 0xdf, 0x6c, 0x9a, 0x5f, 0xbe, 0x7c, 0x8f, 0x71, 0xfe, ++ 0x5d, 0xbe, 0x3a, 0xcb, 0x70, 0xff, 0xd5, 0x87, 0xf2, 0x0c, 0xf7, 0x81, ++ 0xf5, 0x37, 0x1b, 0xea, 0x5b, 0xb1, 0x65, 0x96, 0xe1, 0xfe, 0x9e, 0xed, ++ 0x65, 0x86, 0xfb, 0x95, 0x3b, 0xab, 0x0c, 0xdf, 0xaf, 0xfa, 0x49, 0x83, ++ 0xe1, 0xfd, 0x37, 0x9e, 0x5b, 0x62, 0xb8, 0x5f, 0xfd, 0xc2, 0x9d, 0x71, ++ 0xd7, 0x37, 0xc5, 0x7c, 0xf7, 0x88, 0xe5, 0xdd, 0xd5, 0x4d, 0xb4, 0x5f, ++ 0x9b, 0xe1, 0x55, 0x0c, 0x5e, 0x54, 0xa2, 0xeb, 0x97, 0x16, 0x86, 0xc7, ++ 0x8c, 0xdf, 0x51, 0xf1, 0xf3, 0x28, 0x73, 0xa0, 0x1c, 0xc1, 0x50, 0x84, ++ 0x59, 0x4e, 0x15, 0xd3, 0xfa, 0x67, 0xff, 0x88, 0xfe, 0xac, 0x33, 0xcc, ++ 0xb7, 0x87, 0x82, 0x39, 0x19, 0x00, 0x15, 0xf4, 0x1c, 0x45, 0x43, 0xfc, ++ 0x1f, 0xd4, 0xfb, 0xf2, 0x33, 0xa3, 0x78, 0xa0, 0xca, 0xb3, 0xb2, 0x31, ++ 0xde, 0xfc, 0x2b, 0xe8, 0x51, 0x78, 0x39, 0x3f, 0xe9, 0xaf, 0x82, 0x71, ++ 0xd3, 0x15, 0x63, 0x39, 0x85, 0xaf, 0xd7, 0x6a, 0xde, 0x08, 0xc6, 0x61, ++ 0xcc, 0xeb, 0xb5, 0x8a, 0x67, 0x1e, 0xce, 0xef, 0x66, 0x7a, 0xdf, 0x91, ++ 0x53, 0x32, 0xc0, 0x2e, 0xd1, 0xba, 0x3d, 0xb8, 0x4e, 0xab, 0x5d, 0xdd, ++ 0x7c, 0x3a, 0x6e, 0xff, 0xa8, 0x25, 0xbc, 0xaa, 0xfe, 0xf1, 0xf6, 0xfc, ++ 0xd0, 0xcf, 0xbc, 0xc4, 0xfd, 0x9a, 0x5b, 0x1c, 0x91, 0x81, 0xbc, 0xab, ++ 0xed, 0x57, 0x94, 0x4e, 0x23, 0xee, 0x11, 0xeb, 0xe4, 0x0b, 0x58, 0x51, ++ 0x52, 0x9a, 0xf3, 0x1c, 0xfa, 0x63, 0x0b, 0x80, 0x3e, 0x98, 0x9f, 0x8b, ++ 0x19, 0xde, 0xb1, 0xd3, 0xff, 0xd8, 0x3c, 0xcb, 0xf8, 0xdf, 0xc0, 0xcb, ++ 0x37, 0x3d, 0xe4, 0xb2, 0x02, 0x3e, 0x6e, 0xaa, 0x36, 0xd2, 0xd9, 0xc0, ++ 0x71, 0x14, 0xd5, 0x43, 0x05, 0xec, 0x44, 0x69, 0x81, 0xe9, 0x3d, 0xd0, ++ 0x39, 0x03, 0xca, 0x19, 0xf1, 0x52, 0x0f, 0x97, 0x47, 0x4d, 0xe1, 0xeb, ++ 0xe5, 0x73, 0xc8, 0x1c, 0x1c, 0x07, 0xae, 0xb7, 0x8b, 0x84, 0xde, 0xd6, ++ 0xb0, 0x38, 0x07, 0x71, 0xc5, 0x5f, 0x47, 0xaf, 0xbf, 0x44, 0x0b, 0xcd, ++ 0xc2, 0xf6, 0x51, 0xfe, 0xc4, 0xf3, 0xd7, 0x0a, 0xf2, 0x92, 0xe1, 0xbb, ++ 0x05, 0x6d, 0xc4, 0x63, 0xa3, 0xf8, 0xe4, 0x91, 0xd9, 0x1b, 0x5d, 0x95, ++ 0x80, 0xf3, 0x75, 0xab, 0xb7, 0x8e, 0x96, 0xae, 0xf2, 0xf2, 0x78, 0x93, ++ 0x2e, 0x23, 0x9e, 0xbd, 0xae, 0x80, 0xdd, 0x37, 0x56, 0xb3, 0xf8, 0x53, ++ 0x7d, 0xa0, 0x0f, 0xe3, 0x80, 0x8d, 0xf7, 0x84, 0x36, 0xc2, 0x75, 0xca, ++ 0xaa, 0xb0, 0x82, 0x74, 0x98, 0xf8, 0xfa, 0xac, 0x27, 0x94, 0x86, 0xd8, ++ 0x80, 0xf3, 0x37, 0x8b, 0xf3, 0x2b, 0x4b, 0xf0, 0x95, 0xf3, 0x51, 0xd8, ++ 0xf1, 0x29, 0xab, 0x8d, 0xe3, 0xd8, 0x58, 0x6c, 0xe4, 0xd7, 0x42, 0xce, ++ 0x4f, 0x33, 0x9f, 0x17, 0x72, 0x3e, 0x2e, 0x34, 0xf1, 0xb1, 0x0b, 0xfe, ++ 0xa0, 0x7c, 0x99, 0x9d, 0x80, 0x8f, 0x0b, 0x38, 0x1e, 0xb5, 0xcf, 0xe6, ++ 0xfe, 0xdd, 0x70, 0x7a, 0x5c, 0xbf, 0xf1, 0x59, 0x1e, 0x1f, 0x13, 0xf2, ++ 0xa3, 0x98, 0xe6, 0x35, 0x61, 0x3f, 0x46, 0xe6, 0x37, 0x2e, 0xbf, 0x8f, ++ 0x83, 0x1d, 0x07, 0x9c, 0xe7, 0xe2, 0x38, 0x85, 0xcf, 0x7b, 0x89, 0xf4, ++ 0xc8, 0x9f, 0xdf, 0xb2, 0xc3, 0x0f, 0xf1, 0xd6, 0x0c, 0xab, 0x61, 0xfd, ++ 0x62, 0x1e, 0xef, 0x6b, 0x69, 0x3e, 0x5b, 0xef, 0x28, 0xcd, 0x90, 0x11, ++ 0xf7, 0x97, 0xba, 0xdf, 0x30, 0xc4, 0x99, 0x4b, 0x47, 0xe2, 0xa3, 0xba, ++ 0x56, 0x33, 0x27, 0x2a, 0x9f, 0x5d, 0x03, 0xcc, 0xff, 0x68, 0x75, 0x9f, ++ 0x96, 0x61, 0x9c, 0x1a, 0xf2, 0x19, 0xce, 0xdf, 0xc2, 0xf9, 0x23, 0xe2, ++ 0x7f, 0x07, 0xf8, 0xba, 0x91, 0x99, 0xae, 0xa3, 0xd3, 0x82, 0xd9, 0x80, ++ 0x8f, 0x8e, 0x5d, 0x0c, 0x66, 0xaf, 0x2b, 0x86, 0xf8, 0x8f, 0x84, 0x72, ++ 0xd2, 0x79, 0xeb, 0x03, 0xd9, 0x2c, 0x5f, 0x80, 0xc7, 0x73, 0x79, 0x7b, ++ 0xaf, 0x0c, 0x05, 0xd1, 0x7f, 0x3b, 0x36, 0x30, 0xf6, 0xfa, 0xa2, 0xc0, ++ 0xf9, 0x66, 0xb9, 0x29, 0xf5, 0x86, 0x70, 0x9d, 0xb1, 0x74, 0xa0, 0x5d, ++ 0x86, 0xfe, 0xd6, 0x45, 0xe8, 0x1c, 0x44, 0xbb, 0x3e, 0x2f, 0xfc, 0x0b, ++ 0xd9, 0x53, 0x84, 0x71, 0x69, 0x05, 0xe8, 0x69, 0x74, 0xaf, 0x50, 0x30, ++ 0x5e, 0xe6, 0x6e, 0x51, 0x20, 0xbe, 0x5c, 0xe7, 0xde, 0x55, 0x05, 0xfc, ++ 0xf0, 0x91, 0xd0, 0x66, 0x27, 0xc4, 0xd5, 0x3c, 0x92, 0x37, 0x0c, 0x7c, ++ 0x2c, 0x64, 0xfa, 0xbb, 0x8a, 0xfe, 0x17, 0xab, 0xbf, 0x82, 0xde, 0xda, ++ 0xc1, 0x80, 0x02, 0xfa, 0x5e, 0xeb, 0x31, 0xfa, 0x35, 0x3e, 0x2e, 0x6f, ++ 0x35, 0x6e, 0xd3, 0xf3, 0xfc, 0x5a, 0x94, 0x37, 0x9f, 0x49, 0xde, 0x36, ++ 0x09, 0x39, 0x9b, 0x4e, 0xa6, 0xc7, 0xca, 0x99, 0x88, 0x5b, 0xab, 0x43, ++ 0xb9, 0x5c, 0x5f, 0xe3, 0xcb, 0x59, 0x27, 0xe7, 0xc7, 0xbf, 0xf3, 0x38, ++ 0xeb, 0x1f, 0x78, 0x7c, 0xfa, 0x1d, 0xbe, 0xae, 0xf7, 0xbb, 0x0d, 0x1e, ++ 0xbc, 0xbe, 0xb2, 0xa1, 0x00, 0x9f, 0x1f, 0xd9, 0xe0, 0xc5, 0xfb, 0xb7, ++ 0x37, 0x94, 0xe0, 0xfd, 0x6f, 0x21, 0xce, 0x4b, 0xef, 0xdf, 0xe0, 0x71, ++ 0xdc, 0xd7, 0x37, 0x34, 0xe1, 0xfd, 0xa9, 0x0d, 0xcd, 0x78, 0xdf, 0xcb, ++ 0xe3, 0xb4, 0x42, 0x8e, 0xb7, 0xf2, 0xf5, 0x94, 0x1a, 0xb9, 0x13, 0xe3, ++ 0x8b, 0x0d, 0xde, 0x80, 0xdd, 0x15, 0x23, 0x4f, 0x0d, 0x9c, 0x6e, 0x14, ++ 0x7d, 0xc0, 0x21, 0x85, 0xf1, 0xe3, 0xaf, 0xb6, 0x69, 0xfb, 0x15, 0x90, ++ 0xaf, 0xd3, 0x23, 0x7a, 0x42, 0xd0, 0x5e, 0x2c, 0x6e, 0xcc, 0xd9, 0xbd, ++ 0x8d, 0xf2, 0xc5, 0xf6, 0x5d, 0x12, 0x00, 0x5c, 0x69, 0x3b, 0xf4, 0xaf, ++ 0xca, 0xf5, 0x54, 0xfe, 0x1b, 0xea, 0x72, 0xac, 0x2b, 0xa1, 0xbd, 0x60, ++ 0xbb, 0x32, 0x0b, 0xe4, 0x31, 0xfc, 0xaf, 0x4a, 0x1e, 0x3c, 0x6f, 0xbc, ++ 0xd5, 0x7a, 0x77, 0x9c, 0xf6, 0x45, 0x3b, 0x89, 0xda, 0x37, 0xdb, 0xb7, ++ 0x25, 0x75, 0x46, 0x3f, 0xb8, 0x54, 0xc4, 0xd1, 0x07, 0x02, 0x41, 0xe8, ++ 0xe7, 0xa4, 0x81, 0x40, 0x18, 0xe8, 0x2b, 0x75, 0xab, 0x9e, 0x78, 0x71, ++ 0xe1, 0xee, 0xc9, 0x2b, 0xdd, 0x20, 0x4f, 0xad, 0x67, 0x03, 0x6e, 0x90, ++ 0xa7, 0xd6, 0xc9, 0x7b, 0x64, 0xe6, 0xaf, 0xb3, 0x78, 0xb8, 0xca, 0xe5, ++ 0x54, 0x94, 0x2f, 0x75, 0xef, 0x36, 0xe8, 0xa1, 0xca, 0xe9, 0xee, 0xa0, ++ 0xcf, 0x81, 0xde, 0x8e, 0x71, 0xf4, 0xe0, 0x00, 0xe7, 0x9b, 0x28, 0xe7, ++ 0x53, 0xc2, 0xb2, 0x4b, 0x4b, 0xdc, 0x3f, 0x9f, 0x29, 0x5e, 0xbe, 0x45, ++ 0x8a, 0xef, 0xb7, 0x26, 0x5b, 0x19, 0xae, 0x75, 0xf2, 0xf5, 0x55, 0x6a, ++ 0x33, 0x15, 0xd0, 0x33, 0x10, 0x51, 0xa0, 0x7f, 0x12, 0x15, 0x1b, 0xd0, ++ 0x2f, 0x4d, 0x63, 0x71, 0x0b, 0x87, 0x37, 0xc0, 0xed, 0xb2, 0x71, 0x1e, ++ 0x4f, 0x2b, 0x69, 0x6a, 0x02, 0xbb, 0xa4, 0x65, 0x10, 0x6f, 0x2d, 0x98, ++ 0x37, 0xad, 0xdf, 0x0d, 0x72, 0x23, 0x97, 0xcc, 0x3b, 0x0b, 0xf3, 0x2c, ++ 0x29, 0x8c, 0xb1, 0xdb, 0xe0, 0xf7, 0x98, 0xfd, 0xff, 0xd8, 0x7b, 0x19, ++ 0xa7, 0xae, 0x60, 0x4a, 0x3a, 0x5c, 0xcd, 0xe5, 0x18, 0x7f, 0x35, 0x2e, ++ 0x42, 0x6d, 0xb7, 0x32, 0xfa, 0x1e, 0xe3, 0x71, 0x0e, 0xc1, 0x5f, 0x8d, ++ 0xf3, 0xb7, 0xd4, 0x73, 0xec, 0xdf, 0xc0, 0xae, 0x3e, 0xe6, 0x65, 0xf1, ++ 0x98, 0xc7, 0x32, 0xd8, 0xba, 0xec, 0x85, 0x92, 0x15, 0x88, 0xcb, 0x4a, ++ 0xb9, 0x5f, 0x60, 0x23, 0x3b, 0xb0, 0x7c, 0x32, 0x69, 0xc7, 0xeb, 0x66, ++ 0xae, 0x67, 0x17, 0x4a, 0x4e, 0x13, 0xd0, 0x7b, 0x59, 0xa1, 0xb8, 0x39, ++ 0x03, 0xe8, 0xb1, 0x87, 0x82, 0xf4, 0x7b, 0xa7, 0xc9, 0xbe, 0x2b, 0x9a, ++ 0x91, 0xdf, 0x12, 0xe5, 0xc9, 0x72, 0xc0, 0xd7, 0x03, 0x8a, 0xc1, 0xdf, ++ 0x90, 0x4a, 0x98, 0x9d, 0xb7, 0x83, 0xbf, 0x0e, 0x7e, 0x0c, 0xc7, 0x2f, ++ 0x51, 0x3f, 0x2f, 0x40, 0xae, 0x00, 0xf3, 0xaf, 0x12, 0x4f, 0x6d, 0xb1, ++ 0x1a, 0xfd, 0x31, 0x71, 0x1d, 0x50, 0x2c, 0x28, 0x0f, 0x2e, 0xab, 0x29, ++ 0x9f, 0xee, 0xff, 0x7a, 0xfe, 0x1d, 0xfd, 0x5c, 0xf9, 0x27, 0xfc, 0xc4, ++ 0x11, 0x9c, 0x77, 0xf8, 0xeb, 0x04, 0xd6, 0x63, 0x44, 0x3e, 0xa1, 0x28, ++ 0xff, 0x8a, 0x29, 0xde, 0xa4, 0x66, 0xb3, 0x75, 0x18, 0x73, 0xbd, 0x77, ++ 0x58, 0x19, 0xdf, 0x2b, 0xac, 0x1c, 0x1f, 0x0b, 0x3c, 0xe1, 0x33, 0xb7, ++ 0x93, 0x14, 0x04, 0x7e, 0xaa, 0xd4, 0x9f, 0x4a, 0x92, 0x46, 0xd7, 0x93, ++ 0xa8, 0x3d, 0x32, 0x30, 0x73, 0x9c, 0xb8, 0xf5, 0x46, 0x6c, 0xff, 0x94, ++ 0xe2, 0x62, 0xfe, 0x04, 0xcf, 0x07, 0xa2, 0x6e, 0xb9, 0x64, 0xf0, 0x4f, ++ 0xec, 0xba, 0x3b, 0x76, 0xbd, 0x7f, 0xe4, 0x7b, 0xb7, 0xc5, 0xa0, 0xa7, ++ 0xa3, 0xe9, 0x66, 0xfc, 0xf9, 0xbc, 0xe9, 0x5d, 0x40, 0x1d, 0x52, 0xb8, ++ 0x2e, 0x14, 0x76, 0xb8, 0x84, 0xe1, 0xc9, 0x45, 0x1e, 0x8a, 0x27, 0xe9, ++ 0x9f, 0x8b, 0x34, 0x26, 0xa7, 0x27, 0xfd, 0x52, 0x68, 0x13, 0xca, 0xa9, ++ 0x6e, 0xf0, 0xb7, 0xea, 0x4a, 0x6a, 0xcf, 0xa2, 0x5d, 0xa2, 0xfe, 0x88, ++ 0x3a, 0x87, 0xe3, 0x74, 0x4a, 0x7f, 0x1b, 0xd4, 0x4b, 0xeb, 0x79, 0x7d, ++ 0xb2, 0xf8, 0x6e, 0xc4, 0x9e, 0x58, 0xae, 0xdc, 0x32, 0xba, 0x9e, 0xa6, ++ 0x6a, 0x86, 0x7b, 0x48, 0xf0, 0x97, 0xf3, 0x63, 0xe3, 0x07, 0x4d, 0x54, ++ 0x5c, 0x0a, 0x66, 0x42, 0xbd, 0xec, 0x7b, 0x5a, 0xb4, 0xfb, 0x4a, 0x3c, ++ 0x3a, 0xb8, 0xdd, 0x6a, 0x2a, 0x79, 0x60, 0xa1, 0xe6, 0x84, 0x7b, 0x5d, ++ 0x7a, 0x1a, 0xf0, 0x5e, 0x61, 0x0c, 0x3e, 0x00, 0xbe, 0xe6, 0xdb, 0x8c, ++ 0x7c, 0x36, 0xd9, 0xbf, 0xea, 0x51, 0x76, 0xcf, 0x68, 0x6f, 0xe7, 0x51, ++ 0xf9, 0xdd, 0x4f, 0xdb, 0xa9, 0x93, 0xd7, 0x36, 0x42, 0xc8, 0xbb, 0xf6, ++ 0x89, 0x15, 0xfb, 0x5e, 0x45, 0x72, 0x84, 0x1f, 0xe2, 0x89, 0x5b, 0xef, ++ 0x71, 0xf8, 0xe3, 0x76, 0x40, 0x7f, 0x46, 0xbc, 0x42, 0xbc, 0x2c, 0x8f, ++ 0xa3, 0x2a, 0xe8, 0x69, 0x44, 0xbe, 0x67, 0x48, 0x24, 0x94, 0x03, 0xf4, ++ 0x1b, 0xe9, 0x98, 0x97, 0x6d, 0xf2, 0xc3, 0x32, 0xcc, 0xfd, 0xd8, 0x81, ++ 0xe3, 0x78, 0x48, 0xa1, 0xf3, 0x08, 0x1d, 0xaf, 0x43, 0x74, 0x1c, 0x77, ++ 0xa0, 0x7f, 0x1c, 0xdf, 0x9f, 0x12, 0x7e, 0x5e, 0x45, 0xce, 0x30, 0xfa, ++ 0x53, 0xc2, 0xdf, 0x23, 0xdc, 0xdf, 0x73, 0xd1, 0xff, 0x62, 0xf1, 0x58, ++ 0x39, 0x2f, 0xef, 0x7f, 0xc8, 0xa3, 0x00, 0xfe, 0xf5, 0xdb, 0x4d, 0x71, ++ 0xe6, 0x91, 0xfc, 0x63, 0x82, 0xfe, 0x54, 0x05, 0x31, 0xd2, 0x5b, 0xce, ++ 0xfd, 0xbe, 0x72, 0x93, 0xdf, 0x27, 0xf4, 0xfd, 0x25, 0x61, 0x2f, 0x85, ++ 0x5f, 0xcb, 0xed, 0xe1, 0x1d, 0xc2, 0x9f, 0x2a, 0x1f, 0x7b, 0x7d, 0xb9, ++ 0xc7, 0x94, 0x4f, 0x57, 0x4d, 0x09, 0x6f, 0xbf, 0x06, 0x3d, 0x20, 0x40, ++ 0x15, 0xac, 0x37, 0x91, 0x11, 0x3e, 0x19, 0xe4, 0xab, 0x3b, 0xe7, 0xfa, ++ 0xf6, 0x30, 0xe5, 0xeb, 0x1d, 0xde, 0x24, 0xb6, 0xde, 0x42, 0xe9, 0x54, ++ 0x84, 0x3d, 0x47, 0x3e, 0x31, 0x9c, 0xbd, 0x90, 0x97, 0xbf, 0xc3, 0xa3, ++ 0xa2, 0xfc, 0xfb, 0x34, 0xb6, 0x7e, 0xd1, 0x38, 0x4e, 0xdc, 0xc2, 0x57, ++ 0xc2, 0xd6, 0x0d, 0x4e, 0xd9, 0x25, 0x36, 0x1f, 0x04, 0xc9, 0x9b, 0x24, ++ 0x26, 0x3f, 0xbc, 0xca, 0xc3, 0xec, 0xb5, 0x66, 0x92, 0x8b, 0x6c, 0x4f, ++ 0x53, 0x35, 0xac, 0x03, 0x69, 0x8a, 0xe4, 0x0d, 0x91, 0xd1, 0xf2, 0x5a, ++ 0xcd, 0xfd, 0x39, 0xf8, 0x7e, 0x3d, 0x65, 0x45, 0x75, 0x3e, 0xf5, 0xc9, ++ 0x67, 0xc6, 0xcb, 0x2f, 0xef, 0x83, 0xd0, 0x2a, 0x29, 0xa7, 0x34, 0x3c, ++ 0x9b, 0x93, 0x78, 0x7c, 0x75, 0x6f, 0xa4, 0x0a, 0x86, 0xe7, 0x6a, 0xc7, ++ 0x97, 0x98, 0x70, 0xf6, 0xa9, 0xc8, 0x7b, 0x98, 0xd7, 0x75, 0xa1, 0x50, ++ 0xc2, 0x75, 0x9f, 0xee, 0x9c, 0x8f, 0xd1, 0x3f, 0x10, 0xeb, 0x3b, 0x51, ++ 0xfe, 0x1d, 0xc5, 0x7c, 0x14, 0x5f, 0xc9, 0x47, 0xe8, 0xaf, 0x8c, 0xe4, ++ 0x6d, 0xf1, 0xfa, 0x16, 0x8a, 0xfa, 0x4a, 0x0e, 0xe3, 0x7a, 0xcd, 0xf7, ++ 0x5c, 0x87, 0x31, 0x4f, 0xe4, 0x24, 0xac, 0xe3, 0xd2, 0xef, 0x4f, 0x2a, ++ 0x11, 0x0d, 0xfc, 0x90, 0xf9, 0x02, 0x5f, 0x51, 0x8e, 0x86, 0x05, 0x3f, ++ 0x73, 0x20, 0x4f, 0x82, 0xd5, 0x17, 0xe6, 0x7e, 0xd5, 0x29, 0xfb, 0x1b, ++ 0x0e, 0xb0, 0x9b, 0x22, 0xef, 0xa4, 0xcb, 0x27, 0xd7, 0xc5, 0x8b, 0x73, ++ 0x56, 0xc8, 0x2c, 0xce, 0x2c, 0xae, 0x37, 0xa9, 0x6c, 0xde, 0x99, 0xa3, ++ 0x32, 0x3c, 0x27, 0xee, 0xc5, 0xf8, 0x8e, 0xc8, 0x93, 0x7c, 0xbc, 0x98, ++ 0xf9, 0xe1, 0xdf, 0x31, 0x8c, 0xbb, 0xb9, 0x7e, 0x28, 0xdf, 0x8c, 0xf1, ++ 0xc1, 0x70, 0xe1, 0x58, 0xfe, 0x68, 0xa3, 0x89, 0xcf, 0xd3, 0x54, 0x3e, ++ 0xef, 0x71, 0xbc, 0xd1, 0x19, 0x19, 0x1b, 0xd7, 0x8a, 0x7e, 0x9a, 0xf9, ++ 0x60, 0xee, 0xa7, 0xf9, 0x3b, 0xa7, 0xca, 0xe2, 0x65, 0xf7, 0x58, 0xf5, ++ 0x9b, 0xd5, 0xd9, 0xd1, 0x76, 0xc4, 0x7c, 0x67, 0x2e, 0xbf, 0xc8, 0x1e, ++ 0x3f, 0x2f, 0xc7, 0x5f, 0x62, 0x8c, 0x4f, 0x9a, 0xf3, 0x72, 0xee, 0xb1, ++ 0x06, 0x4a, 0x55, 0xca, 0xcf, 0x2a, 0x45, 0xda, 0x92, 0xea, 0x41, 0xbb, ++ 0x86, 0xfa, 0x74, 0xe8, 0xb2, 0x86, 0x38, 0xe6, 0x42, 0xe4, 0xd0, 0x16, ++ 0x18, 0xd6, 0x23, 0xc3, 0x2c, 0x3e, 0x5a, 0x4e, 0xe4, 0x90, 0x8d, 0xcd, ++ 0x0b, 0x8d, 0xb0, 0x6e, 0x27, 0xf4, 0x46, 0xc8, 0xbf, 0x99, 0x8e, 0xf1, ++ 0xda, 0x2f, 0x1f, 0xee, 0x47, 0x7f, 0xdc, 0x7f, 0x29, 0x52, 0x0d, 0xf2, ++ 0x77, 0x87, 0xaf, 0x1b, 0xed, 0xea, 0x02, 0x6a, 0x57, 0x27, 0xc4, 0xb1, ++ 0xab, 0xf3, 0xe4, 0xc1, 0x2d, 0x13, 0x40, 0x7f, 0xbd, 0x6c, 0x7f, 0xc7, ++ 0xa9, 0xdf, 0xf7, 0x55, 0xe3, 0xbd, 0x26, 0x61, 0x3e, 0xac, 0x5e, 0x9e, ++ 0xa7, 0x4c, 0x00, 0x39, 0x70, 0xc5, 0x8f, 0x57, 0xcd, 0xe5, 0x72, 0x32, ++ 0x7a, 0x3d, 0x4f, 0xd8, 0x55, 0x97, 0x02, 0xb8, 0xc1, 0x1c, 0x6f, 0x9b, ++ 0xcb, 0xf5, 0x6e, 0xae, 0x49, 0x1e, 0x02, 0xea, 0x08, 0x0e, 0xba, 0xed, ++ 0x4a, 0xde, 0xf8, 0xe3, 0x94, 0x48, 0x1e, 0x2e, 0x44, 0x2e, 0x3c, 0x18, ++ 0x2f, 0x8e, 0x2a, 0xae, 0x55, 0x09, 0xc6, 0xf7, 0x3e, 0x62, 0xe2, 0x6f, ++ 0xa7, 0x31, 0xfe, 0x6c, 0xae, 0x47, 0xc4, 0x83, 0x88, 0xdc, 0x99, 0x0d, ++ 0xfa, 0x2c, 0xfc, 0x5f, 0x73, 0xb9, 0x36, 0x95, 0xad, 0x7b, 0x1c, 0x29, ++ 0xba, 0x97, 0xc4, 0xe6, 0x55, 0x09, 0x7b, 0xa0, 0x96, 0xb4, 0x6b, 0x10, ++ 0x17, 0xef, 0x2d, 0x19, 0x7b, 0xbe, 0x30, 0xe7, 0x0f, 0xfa, 0x89, 0x31, ++ 0x4f, 0xac, 0xca, 0x6e, 0x5c, 0x8f, 0x7d, 0x4a, 0xd1, 0x1f, 0x01, 0x79, ++ 0x8c, 0xe2, 0xa4, 0x16, 0xe6, 0xaf, 0x96, 0xb4, 0xa0, 0xbf, 0xba, 0xb0, ++ 0x90, 0xef, 0x0b, 0x2a, 0xba, 0x17, 0xfd, 0x53, 0xe1, 0x57, 0xb7, 0xde, ++ 0xbe, 0x17, 0xf3, 0xb9, 0x44, 0xbe, 0x96, 0xf0, 0x4f, 0xcd, 0x74, 0xf7, ++ 0x4e, 0x7e, 0x11, 0xf3, 0x79, 0xc6, 0xa3, 0x5b, 0xf8, 0xf1, 0xc7, 0x6d, ++ 0x32, 0x5b, 0x87, 0xa0, 0x7e, 0xbb, 0x07, 0xfd, 0x76, 0x8a, 0xfb, 0xe2, ++ 0x7c, 0xf7, 0x8a, 0x8d, 0xf1, 0xeb, 0x57, 0x8a, 0xbe, 0x0b, 0xf4, 0x75, ++ 0x8b, 0x55, 0x77, 0xb7, 0xc0, 0x3a, 0x63, 0x91, 0xcd, 0xfb, 0x7c, 0x9c, ++ 0x71, 0x18, 0xb0, 0x31, 0xfd, 0xee, 0x4d, 0xb0, 0xde, 0xfa, 0x07, 0x58, ++ 0xf8, 0x98, 0x8d, 0xfd, 0x40, 0x3e, 0x98, 0xe7, 0x1b, 0xe1, 0xc7, 0x8a, ++ 0x7d, 0x4a, 0x93, 0xdc, 0x4c, 0x6f, 0x1b, 0xb8, 0x1f, 0x5b, 0x56, 0xd8, ++ 0x82, 0xfa, 0x98, 0xe6, 0xa6, 0x7e, 0x2b, 0xf0, 0xcd, 0xcb, 0xfc, 0x56, ++ 0x32, 0x68, 0xf4, 0x53, 0x17, 0x6a, 0x7d, 0x59, 0x30, 0xfe, 0xe6, 0xf9, ++ 0x4e, 0x1e, 0xe6, 0x7e, 0xed, 0x55, 0xfa, 0xad, 0x5b, 0x93, 0x98, 0x1c, ++ 0x05, 0x5c, 0xc4, 0xee, 0xa6, 0xef, 0x93, 0x14, 0x0a, 0x4d, 0xe9, 0xfc, ++ 0xf7, 0xa4, 0x5c, 0x79, 0x18, 0xf8, 0xb1, 0x35, 0x8d, 0xa0, 0x3f, 0x70, ++ 0x32, 0x4d, 0x0d, 0xed, 0x8e, 0x13, 0x6f, 0x78, 0x9b, 0xcb, 0x5b, 0x8d, ++ 0xbc, 0xda, 0x20, 0x6f, 0xe5, 0x1c, 0x97, 0xa8, 0xd5, 0xfd, 0x1a, 0xc4, ++ 0x03, 0x4e, 0x0e, 0xb3, 0x38, 0x5e, 0xa2, 0x71, 0xdb, 0x66, 0xc2, 0xe9, ++ 0xb9, 0x05, 0xc4, 0x6f, 0x73, 0xc2, 0x35, 0xe2, 0x07, 0x7e, 0xd0, 0x7b, ++ 0xdd, 0x86, 0xd7, 0x08, 0xe6, 0x67, 0x7f, 0xbf, 0x68, 0x65, 0x6e, 0xbc, ++ 0xfa, 0x76, 0xb7, 0x29, 0x71, 0xe7, 0xa5, 0x3f, 0xf3, 0x71, 0x5b, 0x2c, ++ 0xf2, 0xb5, 0xeb, 0x58, 0x3c, 0xf2, 0xbe, 0x42, 0x15, 0xe3, 0xc2, 0x93, ++ 0xea, 0xde, 0x3d, 0x8a, 0x72, 0xda, 0xc8, 0xe5, 0x74, 0x81, 0x0d, 0xfb, ++ 0xdd, 0x5b, 0xa4, 0xe0, 0xb8, 0xf4, 0xde, 0x9e, 0xd3, 0x0e, 0xeb, 0x9a, ++ 0xbd, 0x45, 0x76, 0xcc, 0x47, 0xe9, 0x2e, 0xfa, 0xcd, 0xef, 0x21, 0x5f, ++ 0xbb, 0xbc, 0x44, 0x32, 0xe4, 0x97, 0x08, 0xf9, 0x2d, 0x07, 0x5c, 0x0d, ++ 0xf5, 0xdb, 0x59, 0xbc, 0xf3, 0x3e, 0x37, 0xb3, 0xc3, 0xbd, 0x1a, 0xc7, ++ 0x2f, 0x3c, 0x6f, 0x64, 0x0d, 0x1f, 0xd3, 0x93, 0xfb, 0xde, 0x77, 0xc6, ++ 0xe6, 0x8d, 0x2c, 0x11, 0x72, 0xdf, 0xc8, 0xe3, 0xe4, 0x26, 0xfc, 0x44, ++ 0xcd, 0x48, 0xdc, 0x75, 0x1c, 0x91, 0x47, 0x7c, 0xbe, 0x91, 0xc5, 0x85, ++ 0xef, 0x13, 0xfd, 0xdd, 0xbf, 0x77, 0x0b, 0xe8, 0x5d, 0x03, 0x97, 0x9b, ++ 0xee, 0x8b, 0x2b, 0xdd, 0xa8, 0x9f, 0xfb, 0x59, 0x7e, 0x5e, 0x6b, 0x51, ++ 0x0b, 0xc6, 0x8b, 0xba, 0x27, 0xbf, 0xa5, 0xc2, 0xfd, 0x1a, 0xf7, 0x19, ++ 0x15, 0xee, 0xcd, 0xb8, 0x42, 0x8c, 0xeb, 0x7d, 0x25, 0xbf, 0x62, 0xf9, ++ 0x91, 0x7c, 0x5c, 0xd7, 0x40, 0x3c, 0x9e, 0xca, 0xfb, 0xcb, 0x99, 0x37, ++ 0x5b, 0x3d, 0xf4, 0x7e, 0x71, 0xf8, 0x76, 0x2b, 0xc4, 0x3b, 0x45, 0x7c, ++ 0x76, 0xd4, 0x3a, 0x14, 0x5f, 0x4f, 0xa9, 0x65, 0xdd, 0x27, 0xb5, 0x6e, ++ 0x86, 0xaf, 0x8f, 0x66, 0x3a, 0x48, 0x72, 0x06, 0xf0, 0x4b, 0x0e, 0x49, ++ 0xc0, 0xb7, 0x70, 0x12, 0x49, 0x86, 0xfc, 0x33, 0xb7, 0x35, 0x94, 0x44, ++ 0xef, 0x1b, 0x94, 0xfe, 0x69, 0x80, 0x5b, 0x1c, 0x26, 0xbc, 0x78, 0xfe, ++ 0xd7, 0x7b, 0xb3, 0x41, 0xbf, 0x8f, 0xcc, 0xf8, 0x40, 0x81, 0x76, 0xaf, ++ 0x2b, 0x79, 0xb7, 0x15, 0xfa, 0x31, 0xa5, 0x64, 0x2f, 0xc6, 0xfb, 0xb3, ++ 0xf6, 0xef, 0xed, 0x49, 0xa7, 0xf5, 0x2c, 0x2c, 0x20, 0x5e, 0xdd, 0x33, ++ 0x9a, 0x9e, 0x1a, 0x3e, 0x3f, 0xdd, 0x97, 0xc1, 0xf2, 0x85, 0xee, 0xf3, ++ 0x86, 0x82, 0xb0, 0xef, 0xec, 0xdc, 0x65, 0xb6, 0x9f, 0xa2, 0xf2, 0xd7, ++ 0x6f, 0x54, 0xc1, 0xb4, 0x36, 0x7a, 0x5d, 0x46, 0x27, 0x80, 0x43, 0xc4, ++ 0xba, 0x8e, 0xe2, 0xe6, 0xeb, 0x22, 0x7c, 0x7d, 0x82, 0x5c, 0xbe, 0x22, ++ 0xc5, 0x8e, 0x5b, 0x83, 0x12, 0xb0, 0x83, 0xfd, 0x6d, 0x2d, 0x79, 0xc3, ++ 0x09, 0xf4, 0x2e, 0xe6, 0x7c, 0xcb, 0xdd, 0x27, 0xb7, 0x80, 0x7c, 0x57, ++ 0xff, 0x7a, 0xd6, 0x57, 0x40, 0x4e, 0xc8, 0xed, 0x36, 0xd7, 0x74, 0xda, ++ 0xe0, 0x39, 0xd7, 0x6f, 0x9d, 0xd7, 0x6b, 0xec, 0xfd, 0xbd, 0xac, 0xde, ++ 0xb9, 0x01, 0x5a, 0xbe, 0xa1, 0x70, 0x6f, 0xf6, 0xca, 0xa2, 0xd1, 0xf6, ++ 0x65, 0x44, 0x7f, 0x0a, 0xff, 0xb2, 0x21, 0x40, 0xe9, 0x39, 0x39, 0xff, ++ 0x37, 0xd9, 0x80, 0xdb, 0xde, 0xa0, 0x76, 0xd7, 0x03, 0xed, 0x72, 0xbb, ++ 0x65, 0xf6, 0x97, 0xcc, 0xf3, 0xaa, 0x39, 0x2f, 0xc6, 0xdc, 0xef, 0x4c, ++ 0x65, 0x51, 0x9d, 0x6d, 0x36, 0x8c, 0xf7, 0x8f, 0xdd, 0x39, 0x31, 0x72, ++ 0x46, 0xed, 0xc0, 0x0a, 0xa0, 0x7f, 0xcd, 0xd3, 0x76, 0xcc, 0xe3, 0x4a, ++ 0xdb, 0xff, 0xba, 0x2a, 0x83, 0x7d, 0xa3, 0xf8, 0xbd, 0x56, 0x8a, 0xca, ++ 0xd1, 0x1a, 0x2e, 0x47, 0x0d, 0x1a, 0xb3, 0x7f, 0xad, 0x45, 0x24, 0xb4, ++ 0x49, 0x02, 0xf9, 0x3b, 0xd3, 0x58, 0x06, 0x7a, 0xf7, 0x2a, 0xcb, 0x37, ++ 0x9c, 0xb4, 0xff, 0x5d, 0x96, 0x3f, 0x6a, 0x9a, 0x1f, 0x7a, 0xf9, 0xbc, ++ 0x21, 0xe6, 0xe3, 0xde, 0xc9, 0xef, 0xa1, 0xfe, 0x9c, 0xdf, 0xc7, 0xf5, ++ 0x25, 0x68, 0x91, 0x62, 0xe3, 0x49, 0x5a, 0x49, 0x64, 0x29, 0x8c, 0x8b, ++ 0xe0, 0x4f, 0xa7, 0xc9, 0xde, 0xf8, 0xec, 0xf1, 0xe3, 0x26, 0xef, 0xd8, ++ 0x18, 0x5e, 0x2d, 0xd7, 0xd8, 0x7b, 0x8d, 0xda, 0x6f, 0x58, 0xd7, 0x36, ++ 0xbf, 0xaf, 0xe4, 0xfe, 0x54, 0x15, 0x5c, 0x63, 0xe6, 0x85, 0x07, 0x6d, ++ 0x0c, 0xf7, 0x8a, 0xeb, 0x35, 0xe4, 0x21, 0x3c, 0xf5, 0x5d, 0xaa, 0xff, ++ 0xdd, 0xdb, 0x0f, 0xb9, 0xef, 0x46, 0x3b, 0xa5, 0x21, 0x6e, 0x5f, 0xb3, ++ 0x7f, 0x6f, 0x01, 0xac, 0xd9, 0x64, 0xee, 0xdb, 0x5b, 0xcd, 0xed, 0x05, ++ 0xfa, 0x65, 0x32, 0xef, 0xe7, 0x24, 0xe2, 0x41, 0x3b, 0xb5, 0x50, 0xb3, ++ 0xb3, 0xf5, 0x03, 0x93, 0x9c, 0x5b, 0x4b, 0x76, 0x85, 0x01, 0x3e, 0x8b, ++ 0x79, 0x1a, 0x1c, 0x72, 0x25, 0x33, 0x6a, 0x47, 0xe4, 0xd8, 0x38, 0x44, ++ 0x1c, 0x3f, 0x8c, 0x04, 0xf5, 0x37, 0xf3, 0x63, 0xf2, 0xbe, 0xe8, 0xfc, ++ 0x4e, 0xc0, 0xae, 0x54, 0xb9, 0x59, 0xfc, 0xd5, 0x2c, 0x27, 0x69, 0x25, ++ 0xd4, 0xee, 0xe0, 0x20, 0x50, 0xee, 0xc5, 0xac, 0xfb, 0x9a, 0xe5, 0xb6, ++ 0x41, 0x0b, 0xb8, 0x61, 0x3d, 0x9b, 0xea, 0xcf, 0x59, 0xb6, 0xfe, 0x49, ++ 0xe7, 0x2b, 0x88, 0x4f, 0xc8, 0x8d, 0x5e, 0x1c, 0x4f, 0x2e, 0x9f, 0x16, ++ 0xfa, 0x1f, 0xcc, 0x7f, 0x0e, 0xaf, 0x51, 0x3e, 0xad, 0x05, 0xaa, 0x01, ++ 0xaf, 0x98, 0xe9, 0xf8, 0xa9, 0xcd, 0x88, 0xff, 0xc5, 0xfc, 0x9c, 0xe6, ++ 0xee, 0x47, 0xfa, 0x16, 0x6a, 0xed, 0xd9, 0xd0, 0xfe, 0x24, 0x77, 0x3f, ++ 0xfa, 0x5b, 0xd4, 0xbe, 0x67, 0xc3, 0x55, 0xc8, 0x99, 0xb0, 0xd7, 0x23, ++ 0xf2, 0x57, 0x74, 0x5b, 0x3d, 0xd8, 0x77, 0x90, 0x6b, 0x58, 0x22, 0x3f, ++ 0x59, 0x32, 0x2b, 0x19, 0xec, 0x60, 0x83, 0x9b, 0xe1, 0x14, 0x62, 0x8a, ++ 0xa7, 0xf7, 0xba, 0xc7, 0xf6, 0x37, 0x7a, 0x4c, 0xf2, 0x78, 0xd2, 0xc5, ++ 0xfc, 0xab, 0x86, 0x12, 0x92, 0xec, 0x4a, 0x05, 0x7d, 0x67, 0x71, 0xa7, ++ 0xde, 0x47, 0xd3, 0x77, 0x39, 0x62, 0xe2, 0x72, 0xff, 0x64, 0x0d, 0x74, ++ 0xd8, 0x62, 0xe2, 0xeb, 0xce, 0xc2, 0x2f, 0xd6, 0xbb, 0x9c, 0x60, 0x67, ++ 0x58, 0xfe, 0x56, 0x29, 0x35, 0x5f, 0xd6, 0xbc, 0x68, 0x3c, 0x53, 0xc4, ++ 0x4d, 0xc5, 0x7a, 0x9f, 0x88, 0x93, 0x8e, 0x8a, 0x67, 0x16, 0x76, 0x63, ++ 0x7e, 0x97, 0x55, 0xe4, 0x5d, 0xf0, 0xf5, 0xbf, 0x51, 0x79, 0x3f, 0x09, ++ 0xd6, 0x1d, 0xc5, 0x55, 0xc4, 0x33, 0x6d, 0x9b, 0xda, 0x15, 0x2f, 0x5f, ++ 0x2f, 0x41, 0x3c, 0xd6, 0xc8, 0xe3, 0x70, 0xc3, 0x33, 0xc7, 0x89, 0x87, ++ 0xb2, 0xf8, 0x03, 0xc5, 0x67, 0xbf, 0xb5, 0x4d, 0x1c, 0x1f, 0x9f, 0xed, ++ 0xe1, 0x7e, 0xe6, 0x00, 0x18, 0x0f, 0x7a, 0x5d, 0x65, 0x73, 0xe1, 0x55, ++ 0x83, 0x7c, 0x14, 0x4a, 0x6a, 0x6f, 0x52, 0x7c, 0xdc, 0x76, 0x90, 0xfb, ++ 0x6d, 0xd7, 0xa2, 0x9f, 0xc7, 0x64, 0xf8, 0x8e, 0xb5, 0xf3, 0x27, 0x93, ++ 0x7c, 0x89, 0xe7, 0x51, 0x3c, 0xcc, 0xf4, 0x60, 0x52, 0xc9, 0xde, 0x9e, ++ 0x58, 0x3c, 0x5c, 0xde, 0x46, 0x79, 0x43, 0xc7, 0x49, 0x6d, 0x23, 0xd3, ++ 0x48, 0x6a, 0x62, 0xb9, 0x5b, 0x38, 0x62, 0xf7, 0x7e, 0x65, 0x90, 0xaf, ++ 0x11, 0x7c, 0x3c, 0x0e, 0x2e, 0x16, 0xf2, 0x75, 0x51, 0xd6, 0xff, 0x66, ++ 0x9b, 0x98, 0xb8, 0x5c, 0x03, 0xa7, 0x23, 0xd1, 0xfb, 0xd6, 0x22, 0x5b, ++ 0x33, 0xe4, 0x5b, 0xd1, 0x72, 0x64, 0x52, 0x2a, 0xbb, 0xde, 0x40, 0xaf, ++ 0x3d, 0x33, 0xf6, 0x66, 0x5b, 0xe8, 0xf3, 0xd7, 0x00, 0x7f, 0xc5, 0xd0, ++ 0xd1, 0xfb, 0xcc, 0x7e, 0xec, 0xc7, 0x1f, 0x54, 0xb6, 0xcf, 0xa6, 0xf7, ++ 0xe2, 0xca, 0x5c, 0xc0, 0x07, 0xa7, 0x14, 0x3d, 0xd5, 0x3e, 0xf1, 0xea, ++ 0xe5, 0xc7, 0xac, 0x4f, 0xf6, 0xd9, 0xba, 0x67, 0x23, 0xd5, 0xbf, 0xae, ++ 0x6c, 0x3b, 0xce, 0xcf, 0x5d, 0x6e, 0x86, 0x43, 0x5e, 0x87, 0x92, 0x31, ++ 0xf2, 0xb4, 0x4e, 0x0d, 0x5c, 0x67, 0x9f, 0x8d, 0x10, 0x44, 0x27, 0xe9, ++ 0xdc, 0xc8, 0x09, 0x39, 0x07, 0xa3, 0x59, 0x7d, 0x75, 0xfb, 0xc4, 0xee, ++ 0x72, 0xf4, 0x3f, 0xd4, 0x14, 0x33, 0x3f, 0x6c, 0x87, 0x57, 0x93, 0x61, ++ 0x9d, 0x8f, 0xc9, 0xcd, 0x23, 0x6a, 0x3f, 0xe6, 0xe3, 0xdc, 0x45, 0x6b, ++ 0xb7, 0xd1, 0x76, 0x0e, 0x6b, 0x72, 0xe6, 0x0a, 0x7a, 0x3f, 0xd3, 0xce, ++ 0xe4, 0xf1, 0x70, 0xd0, 0x1a, 0x37, 0xff, 0x79, 0xa6, 0x9d, 0xe1, 0xe7, ++ 0x75, 0x6a, 0xd3, 0x4c, 0xa0, 0x93, 0xb4, 0xaf, 0x45, 0x3d, 0x6b, 0x91, ++ 0xe4, 0x26, 0xd0, 0x7f, 0xe2, 0xbd, 0xba, 0xf8, 0xdc, 0xe6, 0x8e, 0xf8, ++ 0x79, 0xa5, 0x55, 0xd1, 0xfa, 0xe7, 0x62, 0xfd, 0xfb, 0x68, 0xfd, 0x80, ++ 0x1b, 0xbc, 0x3c, 0xfe, 0x4e, 0x5c, 0x99, 0x71, 0xe3, 0xed, 0xbc, 0xdf, ++ 0x61, 0x42, 0xea, 0x40, 0x5f, 0x1e, 0x4b, 0x33, 0xfa, 0x9b, 0x3e, 0x3b, ++ 0x9b, 0xf7, 0xe6, 0x46, 0xeb, 0xaf, 0x8f, 0xad, 0x1f, 0xf3, 0xb3, 0x66, ++ 0xe3, 0xf3, 0x05, 0x38, 0xce, 0x2f, 0xb0, 0xe7, 0x05, 0x76, 0xa6, 0x17, ++ 0xfe, 0x3c, 0x96, 0xd7, 0x26, 0xf8, 0x28, 0xea, 0x5d, 0x1a, 0xad, 0x6f, ++ 0x29, 0xd6, 0xb7, 0x9f, 0x7d, 0x97, 0x6f, 0xe7, 0xeb, 0x06, 0x9c, 0x6e, ++ 0x81, 0xf3, 0xcd, 0xf9, 0x4f, 0x35, 0x49, 0x6c, 0x3c, 0xa2, 0xfb, 0xfa, ++ 0x08, 0xda, 0xcd, 0x52, 0x8a, 0xc3, 0xf1, 0x7c, 0x85, 0x48, 0xe8, 0x30, ++ 0xdc, 0xfb, 0x09, 0xdf, 0x97, 0x29, 0x31, 0x9c, 0xde, 0x95, 0xc2, 0xf6, ++ 0x31, 0x75, 0x59, 0x87, 0xf0, 0x9c, 0x85, 0xee, 0x4f, 0x3e, 0x7e, 0x07, ++ 0xf6, 0x6b, 0x2a, 0x8a, 0x11, 0xdf, 0xdb, 0xb8, 0xec, 0x28, 0x97, 0xf7, ++ 0xc8, 0x50, 0xae, 0x34, 0xfb, 0x82, 0x23, 0xf6, 0xdc, 0x81, 0x72, 0xfe, ++ 0xbe, 0x7b, 0xd8, 0xb8, 0xae, 0xaa, 0x73, 0xbc, 0x73, 0x90, 0xf0, 0x7c, ++ 0x0d, 0x5e, 0x9f, 0x3f, 0x41, 0x9c, 0x4b, 0xe0, 0xf8, 0x0e, 0x5e, 0x3e, ++ 0xba, 0x0e, 0xcc, 0xf6, 0x29, 0x4e, 0x1a, 0x60, 0xfb, 0x12, 0x2b, 0x5c, ++ 0xfc, 0x9c, 0x88, 0xb4, 0x6f, 0xa3, 0x5f, 0x2d, 0xf4, 0x7c, 0xeb, 0x27, ++ 0x6b, 0x19, 0x9e, 0x9f, 0xca, 0xf7, 0xaf, 0x65, 0xef, 0x91, 0x63, 0xe9, ++ 0x51, 0x38, 0x3d, 0xa5, 0xca, 0xfb, 0xdf, 0xdc, 0x0b, 0xfd, 0x8f, 0x10, ++ 0x17, 0xc6, 0x59, 0xc3, 0xbf, 0x73, 0xe4, 0xd0, 0x7e, 0xeb, 0xc7, 0x64, ++ 0x6f, 0x12, 0x94, 0x36, 0xf9, 0x19, 0x3e, 0x8e, 0x6b, 0xcb, 0x39, 0x6e, ++ 0x4d, 0x84, 0xef, 0x8f, 0x4a, 0x81, 0xe7, 0xc2, 0x2c, 0xbe, 0x69, 0xc0, ++ 0xf9, 0x47, 0x33, 0xff, 0x59, 0x06, 0x1c, 0x5a, 0x1a, 0x66, 0xeb, 0x4c, ++ 0x15, 0x1c, 0xd7, 0x57, 0x28, 0xa1, 0x2c, 0x98, 0x1f, 0x6a, 0xb3, 0x59, ++ 0x3c, 0xaa, 0xe3, 0x62, 0x5f, 0x16, 0xe2, 0xf9, 0x8f, 0x33, 0x71, 0xbe, ++ 0xb8, 0x4e, 0xd9, 0x85, 0xfd, 0x9e, 0xa2, 0x0c, 0x61, 0x9e, 0xc4, 0x3c, ++ 0x13, 0xfe, 0xcf, 0x1a, 0x20, 0xe8, 0x37, 0xf8, 0xa9, 0xdf, 0xa0, 0xc7, ++ 0xc1, 0x2d, 0x35, 0x72, 0x76, 0x35, 0xec, 0xcf, 0x2d, 0xf5, 0xb0, 0xfd, ++ 0xb5, 0xa5, 0x5e, 0x56, 0xbe, 0x8b, 0xb6, 0x1f, 0xa4, 0xe5, 0x2b, 0x2f, ++ 0xfe, 0xa0, 0x07, 0xe0, 0xfa, 0x68, 0x7c, 0x6f, 0xc4, 0x29, 0xe5, 0x9e, ++ 0xa1, 0x2a, 0x34, 0x23, 0x26, 0xdc, 0x7f, 0xcd, 0x78, 0x3a, 0x9b, 0xc5, ++ 0xa5, 0x2a, 0x4c, 0x7e, 0x82, 0x90, 0x07, 0xca, 0x0f, 0xdc, 0x37, 0xdf, ++ 0xa1, 0x3c, 0x68, 0x07, 0x3e, 0xe4, 0x66, 0x5b, 0x98, 0x7f, 0x30, 0xd5, ++ 0xb2, 0x1c, 0xf8, 0x46, 0xac, 0xcc, 0x3f, 0xd8, 0xea, 0xfa, 0x96, 0x1d, ++ 0xfd, 0x03, 0xfa, 0x1e, 0xfc, 0x83, 0x0a, 0xee, 0x1f, 0x54, 0x5c, 0x8e, ++ 0x64, 0x81, 0x7f, 0x60, 0xee, 0x8f, 0x90, 0xaf, 0xdc, 0xcb, 0x1f, 0xa3, ++ 0x7f, 0xd0, 0x3d, 0xf4, 0x31, 0xf2, 0x39, 0xfc, 0xc9, 0x9e, 0x2c, 0xb0, ++ 0xcb, 0x22, 0x8f, 0x5c, 0xe0, 0x7a, 0x51, 0x3e, 0x53, 0xf1, 0x1f, 0x01, ++ 0x3d, 0x2e, 0x37, 0xe1, 0x7c, 0x9b, 0xc0, 0xf9, 0xc3, 0x6b, 0x09, 0xe0, ++ 0xfc, 0x0a, 0xc5, 0x88, 0xf3, 0x6d, 0x5c, 0xce, 0x2a, 0x38, 0xce, 0xef, ++ 0x80, 0xf5, 0x2e, 0x90, 0xd7, 0xb3, 0x99, 0xc7, 0x73, 0x68, 0x3f, 0x0e, ++ 0x0a, 0x9c, 0x3f, 0xec, 0x32, 0xe0, 0xfc, 0x52, 0xce, 0x87, 0x83, 0xa0, ++ 0x8f, 0x31, 0x38, 0xff, 0xe0, 0x59, 0xb6, 0xaf, 0xb2, 0x2b, 0x3b, 0xd7, ++ 0x80, 0xf3, 0x47, 0xfc, 0xc8, 0x4f, 0x89, 0xf3, 0x7d, 0x49, 0xcc, 0xee, ++ 0x08, 0x1c, 0x5f, 0xcb, 0xf1, 0x82, 0x78, 0xff, 0x21, 0xb7, 0xe3, 0x66, ++ 0x7c, 0x6f, 0x7e, 0x7f, 0xad, 0xf8, 0x9e, 0x70, 0xfc, 0x1e, 0xc5, 0xc5, ++ 0x46, 0xb9, 0xed, 0xde, 0x9e, 0x8b, 0xeb, 0x2a, 0xa5, 0x2e, 0x3b, 0xca, ++ 0x6d, 0xf9, 0x40, 0x60, 0xf8, 0x01, 0xfa, 0x2a, 0x73, 0x78, 0xed, 0x1f, ++ 0x9f, 0x00, 0x7e, 0xbb, 0x1d, 0x5e, 0xf8, 0xcc, 0xc6, 0xc7, 0x65, 0xdc, ++ 0xfc, 0x4f, 0x13, 0xde, 0x9f, 0x44, 0x22, 0x87, 0x53, 0x41, 0x6f, 0xf2, ++ 0x59, 0xbe, 0x51, 0x5a, 0xb6, 0x0b, 0xf5, 0xa4, 0x82, 0xea, 0x49, 0x6d, ++ 0x3c, 0x7d, 0x30, 0xe3, 0xff, 0x6c, 0x36, 0x6e, 0x55, 0x4a, 0x8b, 0xc8, ++ 0x8b, 0x1b, 0x13, 0xe7, 0x57, 0x68, 0x2e, 0xc4, 0xd9, 0x8a, 0x52, 0x7b, ++ 0x55, 0x38, 0xdf, 0xac, 0x57, 0x75, 0xf9, 0xb6, 0x31, 0xfd, 0xd2, 0xac, ++ 0x24, 0x23, 0x0e, 0xf3, 0x0b, 0xbb, 0xa9, 0x3c, 0x10, 0x44, 0xbb, 0xa9, ++ 0x3c, 0x10, 0x06, 0xfd, 0xf1, 0x5f, 0x66, 0xf9, 0x33, 0xdd, 0x9f, 0x7c, ++ 0xdb, 0x1d, 0x7b, 0x9e, 0xc3, 0x56, 0x6e, 0xff, 0x85, 0x3d, 0x17, 0xfa, ++ 0x78, 0xf0, 0x93, 0x8f, 0x79, 0x1e, 0x8d, 0x49, 0xae, 0x95, 0x8f, 0x1c, ++ 0xb1, 0xfb, 0x8a, 0x0f, 0x66, 0x33, 0x1c, 0xf2, 0x33, 0x25, 0x82, 0xfa, ++ 0x7b, 0xf0, 0xf2, 0xcc, 0xe4, 0xd8, 0x38, 0x95, 0x19, 0xe7, 0x1f, 0xe4, ++ 0x38, 0xbf, 0x82, 0xe3, 0xfc, 0x8a, 0xcb, 0x4c, 0x4f, 0x0e, 0x8e, 0xc6, ++ 0xf9, 0xb7, 0x25, 0xc5, 0xe0, 0x36, 0xe7, 0xe5, 0x65, 0x88, 0xf3, 0xaf, ++ 0x36, 0x9f, 0x40, 0xf8, 0xaf, 0xb5, 0x26, 0xff, 0xf5, 0x5d, 0xbb, 0xd1, ++ 0x7f, 0x4d, 0x24, 0xd7, 0xff, 0xc1, 0xe7, 0xf3, 0x28, 0x3f, 0x87, 0x36, ++ 0x23, 0x9e, 0x55, 0x86, 0xd8, 0x7c, 0xca, 0xf9, 0xa9, 0x70, 0x3c, 0x6b, ++ 0x03, 0x1c, 0x79, 0x0b, 0xce, 0xa3, 0xb8, 0x3f, 0x5e, 0xe8, 0xf1, 0x28, ++ 0xbe, 0x5a, 0x3f, 0x32, 0xcc, 0x93, 0x7e, 0x8e, 0xef, 0x0e, 0x2a, 0x57, ++ 0x8d, 0x67, 0x9b, 0x93, 0x66, 0x27, 0x2e, 0x57, 0x31, 0x0e, 0x9e, 0xdd, ++ 0xfa, 0x89, 0xda, 0x8c, 0xfc, 0xe7, 0x78, 0xb6, 0x42, 0xe0, 0xd9, 0xbf, ++ 0x45, 0xb2, 0x62, 0xf1, 0x2c, 0xd1, 0x18, 0x0e, 0x3b, 0xf8, 0xcc, 0x25, ++ 0xec, 0xc7, 0xc1, 0x34, 0x86, 0x63, 0xcd, 0x38, 0x2c, 0x31, 0xee, 0x60, ++ 0xf7, 0x7e, 0x4d, 0xe2, 0xeb, 0x30, 0x46, 0x3c, 0x21, 0xea, 0xe9, 0x48, ++ 0x21, 0xd9, 0x18, 0x9f, 0x93, 0xde, 0x46, 0xbe, 0x75, 0x59, 0xff, 0x12, ++ 0x17, 0x8f, 0x08, 0xfc, 0x61, 0xc6, 0x1d, 0xc4, 0x84, 0x37, 0x46, 0xea, ++ 0x05, 0x9c, 0x02, 0x78, 0x60, 0xf8, 0x82, 0x03, 0xf6, 0xc1, 0x76, 0x1c, ++ 0x93, 0xf9, 0xbe, 0xba, 0xcf, 0x8a, 0x43, 0x22, 0x72, 0x2c, 0xee, 0x10, ++ 0xdf, 0x75, 0xa5, 0xe8, 0xe8, 0xcf, 0x0b, 0x5c, 0xb2, 0xf5, 0x93, 0x33, ++ 0x88, 0x33, 0xb6, 0x0e, 0x11, 0x3c, 0x39, 0x41, 0xe0, 0x12, 0x8a, 0x37, ++ 0x0e, 0x83, 0x3f, 0xa7, 0xd3, 0xf9, 0x3b, 0xc9, 0x13, 0xa5, 0x5f, 0xe0, ++ 0x13, 0x81, 0x37, 0x46, 0xfa, 0xa1, 0xb0, 0xbc, 0xd1, 0x2e, 0x17, 0xb7, ++ 0xff, 0x09, 0xe2, 0xa0, 0x9f, 0x37, 0x3e, 0x11, 0xb8, 0xc4, 0xcc, 0x9f, ++ 0x83, 0x56, 0x86, 0x5b, 0x3a, 0x2e, 0xbe, 0xf5, 0x99, 0xf0, 0x8a, 0x19, ++ 0x9f, 0x98, 0xe9, 0x9d, 0xb7, 0x6b, 0x47, 0x4f, 0x2a, 0x2d, 0x37, 0x3f, ++ 0x7f, 0x08, 0xed, 0x50, 0x87, 0xb7, 0x0f, 0xf7, 0x99, 0x77, 0x0d, 0xe7, ++ 0x66, 0x00, 0x1f, 0xc6, 0xc7, 0x2d, 0x7e, 0x5c, 0x87, 0x1f, 0x89, 0x53, ++ 0x72, 0xfc, 0x71, 0xad, 0xb8, 0x25, 0x11, 0x5e, 0x49, 0x84, 0x33, 0x0e, ++ 0x02, 0x8e, 0xd1, 0xa2, 0x38, 0xc6, 0x8c, 0x5f, 0xcc, 0xfc, 0xcc, 0xcd, ++ 0x26, 0x2d, 0x10, 0xf7, 0x17, 0xb8, 0x26, 0x91, 0xde, 0x42, 0xb9, 0x7b, ++ 0x9d, 0x51, 0xbc, 0x93, 0xa8, 0x1c, 0xb5, 0xdb, 0x88, 0x83, 0x12, 0xd6, ++ 0x73, 0x39, 0x72, 0xad, 0x38, 0xe8, 0x4c, 0xd2, 0x98, 0x38, 0x88, 0x10, ++ 0x26, 0x37, 0x2c, 0x3f, 0x28, 0x11, 0x3e, 0xd9, 0xea, 0x75, 0x69, 0xb1, ++ 0xf9, 0xaa, 0x62, 0x3e, 0xe9, 0xce, 0xbe, 0xf0, 0x0e, 0xee, 0x2b, 0x1f, ++ 0x50, 0xf1, 0x7c, 0x84, 0xee, 0xb3, 0xcc, 0x7e, 0x26, 0xc2, 0x47, 0x87, ++ 0x4c, 0x7a, 0x77, 0x10, 0xec, 0x85, 0x16, 0x9d, 0xaf, 0x12, 0xf2, 0x65, ++ 0x80, 0x9d, 0xf3, 0x21, 0x70, 0x54, 0xa2, 0x72, 0x57, 0x8b, 0x9f, 0xc4, ++ 0x3c, 0xe2, 0x4b, 0x62, 0xf3, 0x44, 0xa2, 0xf5, 0xc9, 0xac, 0x64, 0x86, ++ 0xb3, 0x1e, 0xc9, 0x65, 0xfe, 0xb2, 0xf9, 0x7d, 0x34, 0xdf, 0xc4, 0x88, ++ 0xa3, 0x48, 0x46, 0x11, 0xca, 0xf3, 0xfd, 0x7c, 0xdf, 0x65, 0x22, 0x5c, ++ 0x45, 0x48, 0xc4, 0xc9, 0xe2, 0x54, 0x41, 0x7c, 0xbe, 0x8c, 0xfb, 0x9b, ++ 0x18, 0x1b, 0x9c, 0xc3, 0xf3, 0x0d, 0x28, 0xa9, 0x4d, 0xf9, 0x24, 0x1f, ++ 0xe6, 0x85, 0x26, 0x3b, 0x1b, 0xaf, 0x93, 0xb3, 0x25, 0xf4, 0x03, 0x16, ++ 0xc1, 0x73, 0x2a, 0x4f, 0xfe, 0x6a, 0xb6, 0x3e, 0x74, 0xba, 0x88, 0xd9, ++ 0xeb, 0x93, 0x7e, 0x1b, 0xda, 0xef, 0xe3, 0xe7, 0x59, 0x3e, 0x62, 0x77, ++ 0x0a, 0x8b, 0xb3, 0x9e, 0xbc, 0x35, 0xc9, 0xbb, 0x9b, 0x92, 0x70, 0x1e, ++ 0xea, 0xa5, 0xf3, 0xf0, 0xe9, 0xa4, 0xbe, 0x62, 0x98, 0xf7, 0x67, 0x88, ++ 0x7e, 0xa6, 0xb3, 0x7e, 0x2e, 0x70, 0x84, 0x57, 0xe3, 0xfa, 0xf8, 0xac, ++ 0x9b, 0x2d, 0xc1, 0x9c, 0xd1, 0xfa, 0xfd, 0x48, 0x32, 0xa7, 0x23, 0x5d, ++ 0xc3, 0x75, 0xb6, 0x06, 0x8e, 0x3f, 0x61, 0x9d, 0x30, 0x6b, 0xe6, 0xe8, ++ 0xfd, 0x04, 0xcf, 0x24, 0xe7, 0x20, 0x9f, 0x20, 0x4f, 0x3e, 0x8b, 0x96, ++ 0xdb, 0x62, 0xe9, 0xfb, 0x7e, 0x2e, 0x7d, 0x94, 0x64, 0x61, 0xeb, 0xaa, ++ 0x66, 0xbe, 0xfe, 0x99, 0xd3, 0x03, 0x8c, 0xb1, 0xc5, 0xf0, 0xa1, 0x31, ++ 0xdf, 0xae, 0x27, 0x51, 0xf9, 0x4f, 0xba, 0x89, 0xad, 0x4f, 0x75, 0x55, ++ 0xdb, 0x30, 0x1f, 0x27, 0x09, 0x96, 0xd2, 0x69, 0xbd, 0xdb, 0x0a, 0x72, ++ 0x53, 0xe2, 0xc9, 0x91, 0xe8, 0x97, 0xf9, 0xf9, 0x4f, 0x93, 0x99, 0xff, ++ 0x7d, 0x7a, 0x6a, 0x04, 0xe7, 0xb1, 0x53, 0x3c, 0xbf, 0x77, 0x8d, 0x22, ++ 0x05, 0x09, 0x73, 0xb0, 0xb0, 0x9f, 0xca, 0x84, 0x29, 0xbb, 0xb6, 0xd1, ++ 0xa2, 0x5f, 0x4e, 0x66, 0xe7, 0xd5, 0x9c, 0xfa, 0xf5, 0xeb, 0x18, 0x27, ++ 0x3a, 0x91, 0xc6, 0xf9, 0xa0, 0x4b, 0x98, 0xc7, 0x70, 0x12, 0x6c, 0x21, ++ 0xc4, 0xfb, 0x5c, 0x5a, 0x08, 0xf6, 0x65, 0xd2, 0xef, 0xad, 0xcb, 0xc6, ++ 0xc8, 0xfb, 0xe8, 0xf3, 0xd7, 0x16, 0xb0, 0xf5, 0x32, 0x42, 0x24, 0x58, ++ 0x47, 0x83, 0x3f, 0x72, 0x47, 0xf3, 0x7b, 0x49, 0x9d, 0x8c, 0xfd, 0x5e, ++ 0xe2, 0xda, 0xfe, 0x00, 0xe8, 0xe3, 0xe9, 0xba, 0x37, 0x1c, 0x70, 0xfe, ++ 0xe4, 0xc2, 0x61, 0x0b, 0x01, 0xbd, 0x5b, 0xe2, 0x2a, 0xbd, 0x17, 0x9e, ++ 0x77, 0xa7, 0x30, 0x39, 0x06, 0x3e, 0x03, 0x6e, 0x5a, 0x52, 0xfd, 0xc5, ++ 0x6f, 0xc2, 0xf3, 0xc6, 0x46, 0xe3, 0x78, 0x1c, 0x49, 0xce, 0x65, 0xe7, ++ 0xc8, 0x28, 0x6c, 0x3c, 0x60, 0xfc, 0xb2, 0x66, 0x8e, 0x6e, 0x97, 0xce, ++ 0x7e, 0x01, 0x35, 0x33, 0x86, 0xff, 0xbe, 0xdf, 0xfc, 0x9d, 0x14, 0x33, ++ 0xaf, 0x88, 0xbc, 0x15, 0x7b, 0x82, 0x3c, 0xbe, 0x44, 0xfd, 0x96, 0x62, ++ 0xed, 0xaf, 0x1c, 0x8d, 0x3b, 0x4e, 0x2a, 0xd9, 0xb5, 0x03, 0xf6, 0xc7, ++ 0x34, 0x15, 0xb3, 0x73, 0x2f, 0x1a, 0x3c, 0x24, 0x08, 0xeb, 0xbc, 0x0d, ++ 0x5e, 0x12, 0xce, 0xe1, 0xf2, 0x85, 0xf9, 0x34, 0x3d, 0xf9, 0x6c, 0x5f, ++ 0x10, 0xd7, 0xaf, 0xb4, 0x92, 0x5d, 0x6d, 0xb9, 0x10, 0xa7, 0x1c, 0x56, ++ 0xd8, 0xfa, 0xb3, 0x69, 0x3e, 0x29, 0xa3, 0x63, 0x95, 0x9d, 0x0e, 0x71, ++ 0x73, 0x36, 0x3e, 0x27, 0x67, 0xcb, 0xe8, 0xd7, 0x95, 0x95, 0x30, 0x5c, ++ 0x5f, 0xc6, 0x71, 0x7d, 0x83, 0xde, 0x82, 0xeb, 0x7a, 0x8d, 0x8f, 0xf6, ++ 0x6c, 0xcf, 0x85, 0xf7, 0x72, 0x76, 0x8d, 0xdf, 0xc3, 0xd7, 0x47, 0x63, ++ 0xf8, 0x47, 0xf6, 0xb3, 0x38, 0xdc, 0x22, 0x93, 0x9c, 0xa7, 0x98, 0xe2, ++ 0xfc, 0x65, 0x5e, 0x53, 0x7e, 0x20, 0xcf, 0xeb, 0xeb, 0x2a, 0x78, 0xce, ++ 0x05, 0xf2, 0xf3, 0x48, 0x3a, 0x97, 0x9f, 0x99, 0x12, 0xea, 0xd1, 0xeb, ++ 0x92, 0xe7, 0xd1, 0xdc, 0x98, 0xf9, 0xa8, 0x3e, 0x59, 0xe4, 0x1f, 0x11, ++ 0x8f, 0x35, 0x46, 0x3e, 0x46, 0xe4, 0x81, 0x8f, 0xaf, 0x99, 0xef, 0x89, ++ 0xf8, 0x69, 0xe6, 0x93, 0x59, 0x2e, 0xcc, 0xfc, 0x3e, 0x99, 0x62, 0xe2, ++ 0x57, 0x02, 0xfe, 0x27, 0xe2, 0x77, 0x59, 0x89, 0xff, 0xbf, 0x94, 0xbf, ++ 0xe7, 0xac, 0x36, 0x2b, 0xc8, 0x6d, 0xb7, 0xf5, 0x83, 0x6c, 0xee, 0x0f, ++ 0x11, 0x39, 0xc6, 0x9e, 0x98, 0xf9, 0x76, 0x4e, 0xf3, 0xa4, 0x80, 0x9d, ++ 0x38, 0x3d, 0xcc, 0xe6, 0x9b, 0x13, 0x53, 0x3d, 0x5f, 0xc1, 0x73, 0xb0, ++ 0xa8, 0x1e, 0xe3, 0x39, 0x9e, 0x5c, 0x1f, 0xa2, 0xe3, 0x40, 0xf5, 0xc1, ++ 0x19, 0xab, 0xcf, 0x6f, 0x4f, 0x03, 0x7d, 0xa6, 0x72, 0x66, 0x85, 0x7a, ++ 0x1a, 0x75, 0x49, 0x4f, 0x02, 0xfd, 0xdb, 0xb7, 0xf5, 0x01, 0xec, 0x37, ++ 0xe8, 0xa9, 0x33, 0xaa, 0x47, 0x66, 0xfe, 0x8f, 0xd2, 0x3f, 0xfa, 0xbf, ++ 0x22, 0xe8, 0xcd, 0x1b, 0xad, 0x47, 0xe6, 0xbc, 0xb1, 0x4f, 0xab, 0x7f, ++ 0xdf, 0x01, 0x7b, 0x0e, 0xf1, 0x82, 0x64, 0x0f, 0xf2, 0x4f, 0xd8, 0xd3, ++ 0x46, 0xe2, 0xfa, 0x4a, 0xec, 0x3e, 0x56, 0xb1, 0x9e, 0xde, 0x9d, 0xd3, ++ 0xda, 0x04, 0xfb, 0xcf, 0x1b, 0x06, 0x2c, 0x78, 0xde, 0x4f, 0xc7, 0xf0, ++ 0x8b, 0xca, 0x0a, 0xd8, 0xd7, 0x5a, 0x27, 0xe1, 0xb4, 0xa6, 0x91, 0x3e, ++ 0xa4, 0x57, 0x6b, 0x63, 0x79, 0x11, 0xd7, 0x3f, 0xfb, 0x30, 0x81, 0xbc, ++ 0xf5, 0x47, 0xa7, 0x12, 0x2f, 0xd8, 0x2b, 0xad, 0x8d, 0xe5, 0x49, 0xd0, ++ 0xf7, 0x98, 0x27, 0x21, 0x70, 0xbd, 0x38, 0xbf, 0x91, 0xbe, 0xd7, 0x59, ++ 0x5e, 0x88, 0xf1, 0x9c, 0xa5, 0x14, 0xaf, 0x31, 0xcf, 0x67, 0xf1, 0x60, ++ 0x25, 0xae, 0x2f, 0xf4, 0xf0, 0x73, 0x8f, 0x46, 0xfc, 0x0b, 0x22, 0xe4, ++ 0xd2, 0xb8, 0xbf, 0xa5, 0x15, 0x9e, 0x4c, 0x8e, 0xee, 0x87, 0x6a, 0xbb, ++ 0x18, 0xc2, 0xf8, 0x4c, 0x47, 0x82, 0xfd, 0x2e, 0xe2, 0x6a, 0xf6, 0x17, ++ 0xcc, 0xd7, 0x23, 0x87, 0x7e, 0xf1, 0xcd, 0xbd, 0x90, 0x5f, 0x91, 0xaf, ++ 0xba, 0x00, 0x52, 0x94, 0x0f, 0x87, 0xed, 0x50, 0xdf, 0xf7, 0x0b, 0x0f, ++ 0xd5, 0x61, 0x3e, 0x5b, 0x9d, 0xe4, 0x82, 0x75, 0xb7, 0x23, 0x1f, 0xb7, ++ 0x6f, 0x86, 0xf3, 0x8e, 0x16, 0x17, 0xbe, 0x17, 0x37, 0xbf, 0xe7, 0xc0, ++ 0xb9, 0xa7, 0xbc, 0xd0, 0x8f, 0x03, 0xd6, 0x1d, 0xde, 0x74, 0xb0, 0x0f, ++ 0x9b, 0xd8, 0xbc, 0x95, 0x74, 0x43, 0xe1, 0xd4, 0x15, 0x63, 0xe0, 0xa3, ++ 0x40, 0x9d, 0xbf, 0x2e, 0x67, 0x46, 0xe2, 0x7c, 0x92, 0xd5, 0x0e, 0x1e, ++ 0xf7, 0xef, 0xfe, 0xfa, 0xee, 0x47, 0x60, 0x7d, 0x7b, 0x50, 0xf5, 0x82, ++ 0xff, 0x52, 0xcf, 0xfd, 0x8e, 0x06, 0x65, 0x47, 0xf3, 0x0a, 0x3a, 0x9e, ++ 0x3d, 0xf3, 0x25, 0xef, 0x46, 0xfa, 0xbc, 0xe7, 0xc6, 0x27, 0xd6, 0x1e, ++ 0x82, 0x38, 0xeb, 0x59, 0x15, 0x38, 0x4e, 0x7a, 0x2f, 0xee, 0xc9, 0x06, ++ 0x3f, 0xe3, 0xb5, 0x67, 0xec, 0xe8, 0x7f, 0x1e, 0xf9, 0x78, 0xcf, 0x4f, ++ 0x30, 0x9f, 0x64, 0x50, 0x9d, 0x03, 0xfd, 0x1d, 0xa1, 0x7f, 0xba, 0xc6, ++ 0xde, 0x9f, 0x7f, 0xe9, 0x18, 0xd8, 0x99, 0xc5, 0x05, 0x8b, 0x8b, 0xa1, ++ 0x9d, 0x24, 0x85, 0xec, 0x00, 0x79, 0xba, 0x6e, 0xb8, 0xfd, 0x1d, 0x38, ++ 0x17, 0xa1, 0x61, 0x40, 0x9d, 0x0d, 0xf6, 0x67, 0x71, 0xdd, 0x2e, 0xfb, ++ 0xd7, 0x80, 0x4f, 0x75, 0xbf, 0xb2, 0x4f, 0x07, 0xff, 0x63, 0xd8, 0x53, ++ 0x03, 0xe3, 0x99, 0x9d, 0x1c, 0xd0, 0x1d, 0x54, 0x1e, 0xb3, 0x0a, 0x73, ++ 0xbe, 0x97, 0x01, 0xed, 0x78, 0x89, 0x57, 0x47, 0xbe, 0xf6, 0x11, 0xe0, ++ 0xab, 0xc8, 0x43, 0x10, 0xb8, 0x5e, 0xf8, 0x93, 0x1d, 0xf3, 0x73, 0x52, ++ 0x48, 0x0c, 0x5f, 0x4f, 0x0f, 0xe7, 0xa6, 0x60, 0x3c, 0xb2, 0x8e, 0xe7, ++ 0x2b, 0xcc, 0x97, 0x9b, 0xc0, 0x3f, 0x3e, 0xed, 0x9a, 0x9e, 0x82, 0x71, ++ 0xc8, 0x3a, 0x96, 0xa7, 0x60, 0xe6, 0xd7, 0x62, 0xc0, 0xe9, 0xa9, 0x40, ++ 0x5f, 0xce, 0xd4, 0x95, 0x71, 0xe6, 0xef, 0xdc, 0xba, 0xbf, 0x6c, 0x08, ++ 0x40, 0xdc, 0xf7, 0x46, 0x5b, 0x73, 0x3c, 0x7e, 0x07, 0x38, 0xbf, 0x93, ++ 0xfe, 0xbc, 0x72, 0x37, 0xf4, 0x37, 0xe9, 0xc7, 0x76, 0x17, 0xc0, 0xeb, ++ 0xa4, 0x04, 0x79, 0x98, 0x79, 0x0e, 0x1e, 0x8f, 0x73, 0x5f, 0x5d, 0x7c, ++ 0x44, 0xe0, 0x19, 0xca, 0x57, 0xbb, 0x35, 0x26, 0xee, 0x47, 0xf1, 0xfe, ++ 0xd7, 0x1c, 0x31, 0x71, 0x97, 0x6b, 0x6d, 0xff, 0x4e, 0xc8, 0xd9, 0x9e, ++ 0x0d, 0x71, 0x8a, 0xc0, 0xfd, 0x50, 0x4f, 0x19, 0x8f, 0x8f, 0x94, 0xf3, ++ 0xf8, 0x48, 0x22, 0xba, 0x4a, 0xc7, 0x89, 0x5b, 0x50, 0x39, 0x42, 0x3e, ++ 0x2d, 0x86, 0xb8, 0xc5, 0x2d, 0xec, 0x7a, 0x03, 0xbd, 0xf6, 0xd4, 0xe7, ++ 0x4c, 0x35, 0xc4, 0x2d, 0x88, 0xee, 0x06, 0x3b, 0x7b, 0x1a, 0xd6, 0xe1, ++ 0x00, 0x8f, 0x29, 0x8b, 0x36, 0x38, 0x60, 0x1d, 0xee, 0x1c, 0x8b, 0x5f, ++ 0x24, 0x92, 0xdf, 0xc5, 0xf9, 0x7b, 0xee, 0x3c, 0x14, 0x63, 0xef, 0x7a, ++ 0xad, 0x7a, 0x36, 0xf8, 0xb9, 0x3d, 0x37, 0xbe, 0x8d, 0x7e, 0xd2, 0xff, ++ 0x2e, 0xf9, 0x1d, 0x91, 0xb3, 0xba, 0x5f, 0xb5, 0xc1, 0xf9, 0x59, 0xdb, ++ 0x0a, 0x17, 0x4f, 0x04, 0xfb, 0x17, 0x23, 0xc7, 0xcf, 0x00, 0xfd, 0xd7, ++ 0x2a, 0xc7, 0x66, 0xfe, 0x75, 0xcc, 0xcf, 0x4b, 0x21, 0x5a, 0x54, 0x9e, ++ 0x85, 0x1c, 0x8f, 0x96, 0x4b, 0x09, 0xfd, 0x51, 0x21, 0xdf, 0x89, 0xc6, ++ 0x03, 0xca, 0x81, 0x3f, 0x2a, 0xe4, 0x3c, 0x51, 0xb9, 0xd3, 0xf3, 0x6f, ++ 0x88, 0x2b, 0xff, 0xd1, 0x7a, 0x86, 0xc6, 0xd4, 0x83, 0x2f, 0x38, 0x18, ++ 0x7e, 0x09, 0x38, 0xd8, 0xfc, 0x52, 0x4e, 0x74, 0x17, 0xd8, 0xe1, 0x79, ++ 0x59, 0xef, 0xa0, 0xdf, 0xfa, 0x0a, 0xb7, 0xc7, 0x23, 0x72, 0x92, 0xd2, ++ 0x77, 0xe7, 0xfd, 0xd4, 0xee, 0x04, 0x9f, 0xb7, 0xe3, 0x7a, 0x79, 0xd7, ++ 0x45, 0x15, 0xcf, 0x59, 0xef, 0x7a, 0x6e, 0xd5, 0xcf, 0x60, 0xde, 0xe8, ++ 0x19, 0xae, 0x74, 0x9d, 0xc1, 0x79, 0xdc, 0xef, 0x5a, 0x42, 0xe9, 0xba, ++ 0x11, 0xfc, 0x87, 0x42, 0x1c, 0x9f, 0x1e, 0x25, 0x26, 0x4e, 0xf8, 0x27, ++ 0x87, 0xf0, 0x1f, 0x8c, 0x79, 0xbd, 0xff, 0xe2, 0xfa, 0x63, 0xba, 0x9f, ++ 0xcd, 0xb3, 0x9a, 0x9f, 0xf2, 0xfb, 0x16, 0x3e, 0x4f, 0xdc, 0x94, 0xf3, ++ 0x5c, 0x32, 0xcc, 0xe7, 0xb7, 0xf0, 0x7d, 0x13, 0x33, 0x3a, 0xd5, 0xb8, ++ 0xf3, 0x32, 0x87, 0x10, 0xa4, 0x30, 0xe3, 0x75, 0x0b, 0x40, 0xff, 0xc2, ++ 0x7d, 0xc6, 0x72, 0xda, 0xc8, 0x3e, 0xf4, 0x76, 0x0b, 0xac, 0x03, 0xde, ++ 0xf4, 0x82, 0xe9, 0x3d, 0xdf, 0x3f, 0x6d, 0xce, 0x83, 0xfc, 0xbd, 0xc3, ++ 0xb4, 0xcf, 0xc9, 0x34, 0xdf, 0xda, 0x2f, 0x8e, 0xed, 0xf7, 0xfe, 0x12, ++ 0xe6, 0x27, 0x0a, 0x25, 0x5e, 0xe0, 0x79, 0xbe, 0xff, 0xc2, 0xcf, 0x0d, ++ 0x6c, 0xe7, 0xe7, 0x06, 0xbe, 0x08, 0xfb, 0x59, 0xe9, 0x75, 0x1f, 0xec, ++ 0x67, 0xa5, 0xcf, 0x5f, 0x82, 0xfd, 0xac, 0xf4, 0x7e, 0x3f, 0xdf, 0xcf, ++ 0x4a, 0xb2, 0xaf, 0xee, 0x7c, 0x78, 0x71, 0xae, 0x93, 0xca, 0xf9, 0xd0, ++ 0x36, 0x39, 0x64, 0x88, 0x87, 0x8a, 0x7d, 0xde, 0x1d, 0x70, 0x6e, 0x12, ++ 0xe0, 0x01, 0xb7, 0xca, 0xce, 0x9b, 0x73, 0x51, 0xb4, 0x05, 0xf9, 0x28, ++ 0x1c, 0x2f, 0x5a, 0x1c, 0x3e, 0xbb, 0x4a, 0xc7, 0x55, 0xfd, 0x13, 0xc1, ++ 0x7c, 0x94, 0x6f, 0x9d, 0xed, 0x43, 0x79, 0xd8, 0xce, 0xe7, 0x59, 0x33, ++ 0x8e, 0x11, 0xe7, 0x3a, 0x9a, 0xe9, 0x52, 0xa3, 0x7c, 0x54, 0x20, 0x4e, ++ 0xd5, 0x35, 0x35, 0xd0, 0xdc, 0x54, 0xc8, 0x07, 0x0c, 0xe4, 0x66, 0xf6, ++ 0xa4, 0x5d, 0xdb, 0x62, 0xf0, 0xb4, 0xa6, 0x31, 0xb9, 0x68, 0xe5, 0x7e, ++ 0x5b, 0xf0, 0x22, 0x09, 0x3d, 0x2f, 0x45, 0xcb, 0x9f, 0xb8, 0x48, 0xf6, ++ 0x6c, 0x63, 0x71, 0xb6, 0xa0, 0x0c, 0xb8, 0x03, 0xfe, 0xa2, 0x22, 0x5c, ++ 0x3f, 0x40, 0x10, 0xc7, 0xd5, 0x17, 0x6f, 0x45, 0xff, 0x0b, 0x70, 0x20, ++ 0xe0, 0x32, 0x3c, 0x67, 0x2c, 0x17, 0xf6, 0xa5, 0xbe, 0x84, 0x78, 0xae, ++ 0x7e, 0x78, 0xce, 0xbd, 0x0c, 0xb7, 0xe8, 0xa3, 0x70, 0xdc, 0x08, 0xdf, ++ 0x64, 0xe4, 0x13, 0xc3, 0xe7, 0xc5, 0xaf, 0xe3, 0xf9, 0xcc, 0xf5, 0x03, ++ 0xf1, 0xe5, 0x2d, 0x9a, 0xc7, 0xd4, 0xdc, 0x93, 0x1f, 0xb3, 0xff, 0xa0, ++ 0x71, 0x38, 0xd0, 0xc8, 0xf1, 0x91, 0x2b, 0xf6, 0x7c, 0x04, 0xd5, 0x24, ++ 0x57, 0xe6, 0x7a, 0xd2, 0x8a, 0x25, 0x1c, 0x97, 0x05, 0x05, 0x3c, 0xde, ++ 0xc3, 0xd7, 0x3f, 0xc4, 0x78, 0x6e, 0x5e, 0xdb, 0x87, 0xf9, 0x1e, 0xbd, ++ 0xc5, 0x36, 0x0f, 0xc4, 0x17, 0xcc, 0x38, 0xd1, 0x8c, 0xf3, 0xd5, 0x62, ++ 0xb6, 0x5f, 0x4c, 0xb9, 0x9d, 0xed, 0x5b, 0xad, 0xbf, 0x48, 0x30, 0x3f, ++ 0x1e, 0x05, 0x26, 0x33, 0x7a, 0x0e, 0x9b, 0xca, 0xf3, 0x79, 0x3b, 0x5c, ++ 0x01, 0x2f, 0xc4, 0x31, 0x1b, 0xbc, 0x26, 0xdc, 0xcb, 0xcf, 0x91, 0x2a, ++ 0x2f, 0x30, 0xe2, 0x79, 0x33, 0xde, 0x57, 0x07, 0x54, 0x13, 0xde, 0x0f, ++ 0xb2, 0xf9, 0x70, 0x13, 0x1b, 0xcf, 0x93, 0xe7, 0x09, 0xfa, 0x51, 0xcf, ++ 0xef, 0x64, 0xf1, 0x81, 0x03, 0x6e, 0x0f, 0x93, 0x3f, 0x12, 0x42, 0xbf, ++ 0xa7, 0xc2, 0x6d, 0xb9, 0x75, 0x9b, 0x07, 0xd6, 0xa9, 0xd8, 0x3e, 0xcc, ++ 0xd2, 0x61, 0x82, 0xf1, 0x92, 0xd2, 0x01, 0x0f, 0xee, 0xab, 0xae, 0x18, ++ 0x24, 0xe1, 0xeb, 0x67, 0xe0, 0x79, 0xc3, 0x6d, 0x78, 0x9e, 0x90, 0x89, ++ 0x7f, 0x15, 0x10, 0xea, 0x4d, 0x87, 0x7a, 0x3c, 0x3d, 0x13, 0x21, 0x9e, ++ 0xa7, 0x90, 0x2d, 0x70, 0x8e, 0x4c, 0xa6, 0xbd, 0x45, 0x07, 0x3d, 0x50, ++ 0xdd, 0x6b, 0x71, 0xdf, 0x0d, 0xe4, 0x31, 0x4c, 0x60, 0x72, 0x64, 0x8f, ++ 0xe5, 0xaf, 0x9a, 0x7c, 0x7c, 0x33, 0xa8, 0x40, 0x05, 0x8f, 0xab, 0x89, ++ 0xdf, 0xa7, 0x98, 0x64, 0xdf, 0x8b, 0x72, 0x10, 0x33, 0x7e, 0x63, 0xae, ++ 0x87, 0xa9, 0x5c, 0xee, 0xc4, 0xfa, 0x96, 0x9f, 0xd7, 0xef, 0x1f, 0x64, ++ 0x79, 0x6d, 0x66, 0x39, 0x48, 0xb3, 0x0f, 0x61, 0x3c, 0xbe, 0x72, 0x58, ++ 0xc3, 0xf3, 0x9e, 0xcd, 0xe3, 0x6e, 0x1e, 0xd7, 0x4a, 0x2d, 0xf2, 0xfe, ++ 0xe3, 0xb0, 0x3f, 0xe3, 0x62, 0xb2, 0x77, 0x13, 0x8c, 0xb3, 0x9d, 0x8d, ++ 0xb3, 0x18, 0x47, 0x55, 0xee, 0x94, 0x61, 0x1f, 0x07, 0x51, 0xd8, 0x78, ++ 0x89, 0xf5, 0x2f, 0x73, 0xfc, 0xb5, 0xcc, 0xb4, 0x3f, 0xce, 0x4c, 0x97, ++ 0x38, 0x17, 0x61, 0xbd, 0x66, 0xda, 0x2f, 0xc6, 0x71, 0x7c, 0x25, 0xa7, ++ 0xae, 0x2d, 0x69, 0xaf, 0xe1, 0x7c, 0xda, 0x4a, 0x6e, 0x67, 0x46, 0xe6, ++ 0x6d, 0x7b, 0x1e, 0x5f, 0xc7, 0x62, 0xe7, 0x99, 0x1e, 0x18, 0x1c, 0x7b, ++ 0x1d, 0xeb, 0x80, 0x8b, 0x9d, 0xef, 0x47, 0x5c, 0x8b, 0xc7, 0xb1, 0x7b, ++ 0x9b, 0x98, 0xff, 0xcd, 0xcf, 0x11, 0x28, 0x2b, 0x21, 0xc9, 0x80, 0x73, ++ 0xca, 0x06, 0x09, 0x93, 0xaf, 0x47, 0x2d, 0x21, 0x47, 0x4e, 0x6c, 0xf9, ++ 0x90, 0x61, 0xff, 0xb8, 0x73, 0x70, 0x59, 0x3d, 0x9e, 0xc7, 0xe8, 0x72, ++ 0x55, 0x43, 0x9c, 0xad, 0x8c, 0xb0, 0xf5, 0x4a, 0x7d, 0x80, 0xe0, 0xfa, ++ 0xa5, 0x4e, 0xf6, 0xca, 0x81, 0x98, 0x7e, 0x89, 0x75, 0x10, 0x95, 0xc7, ++ 0xc5, 0x54, 0x89, 0xf5, 0x4b, 0xf0, 0xc9, 0x4c, 0xdf, 0x5d, 0xc3, 0x46, ++ 0x7f, 0xe8, 0x2b, 0x41, 0xe3, 0xbe, 0x87, 0x3b, 0x1f, 0x36, 0xee, 0xd3, ++ 0xf8, 0xd2, 0xda, 0x2c, 0xc3, 0xfb, 0xda, 0x55, 0x79, 0x86, 0xf7, 0x35, ++ 0x9e, 0x9b, 0x0d, 0xf7, 0x5f, 0x74, 0x1b, 0xcf, 0x09, 0xfa, 0x42, 0xc0, ++ 0x78, 0x4e, 0xd0, 0x92, 0xe6, 0x2a, 0x43, 0xf9, 0x45, 0x4d, 0xc6, 0x73, ++ 0x82, 0xee, 0xa8, 0x33, 0x9e, 0x13, 0xd4, 0xa0, 0xdf, 0x69, 0xd2, 0x5f, ++ 0xdd, 0x20, 0xdf, 0x5d, 0x52, 0xdf, 0x0f, 0xa1, 0xff, 0x16, 0xc7, 0xef, ++ 0xf3, 0xc6, 0x8a, 0x07, 0x97, 0x8f, 0xb7, 0x6e, 0x1c, 0x64, 0xe7, 0x06, ++ 0xa1, 0x1f, 0x18, 0x67, 0xbf, 0x8b, 0x79, 0x5f, 0xdb, 0x07, 0x9a, 0xc0, ++ 0x0b, 0x46, 0x3d, 0xe8, 0x09, 0xfa, 0xd9, 0xb9, 0x3a, 0x03, 0x9e, 0x9d, ++ 0x7e, 0x7a, 0x7f, 0x88, 0x78, 0x15, 0x74, 0x70, 0xf9, 0xf9, 0x41, 0x35, ++ 0x84, 0x95, 0xab, 0x71, 0xb3, 0xf5, 0x96, 0xea, 0x8c, 0xf8, 0xfe, 0xbc, ++ 0xb0, 0x83, 0xe6, 0xf5, 0x0a, 0x71, 0xfe, 0x5f, 0xd9, 0x60, 0x1f, 0xca, ++ 0x41, 0xb9, 0xe9, 0xbc, 0xbf, 0x52, 0xf7, 0xbc, 0xb8, 0xe7, 0x79, 0xbe, ++ 0xa7, 0x71, 0xbc, 0x20, 0xce, 0xbf, 0x48, 0x70, 0xce, 0xc5, 0xa8, 0xf9, ++ 0xfb, 0x6a, 0xfb, 0xc7, 0xd7, 0x99, 0xc6, 0xed, 0x1f, 0x6f, 0xb7, 0x94, ++ 0xf4, 0x1d, 0x76, 0xe6, 0x24, 0xee, 0xdf, 0xd5, 0xf6, 0x6b, 0x24, 0x8f, ++ 0x0b, 0xce, 0x1d, 0xa4, 0xfc, 0xe8, 0x83, 0x47, 0x93, 0xd9, 0x7b, 0x8d, ++ 0xea, 0xdb, 0x96, 0xb4, 0x02, 0x3c, 0xe7, 0x22, 0xc3, 0x5e, 0x29, 0xa5, ++ 0x4c, 0x8c, 0xc6, 0x3b, 0x89, 0x3e, 0xeb, 0xaa, 0xf2, 0xce, 0xba, 0x79, ++ 0x1c, 0x9f, 0xe8, 0x4b, 0xae, 0xea, 0xdc, 0xd2, 0x0c, 0xbb, 0x87, 0xe9, ++ 0xbf, 0xce, 0xf0, 0xd1, 0x16, 0x49, 0x0f, 0xc1, 0x39, 0x79, 0xe6, 0x75, ++ 0x53, 0x95, 0xcf, 0xa7, 0x93, 0x22, 0xec, 0xbc, 0x0b, 0x1f, 0x3f, 0xef, ++ 0x22, 0x69, 0x0b, 0xd1, 0x0b, 0x29, 0x8b, 0x82, 0x95, 0x04, 0xd7, 0xf1, ++ 0x83, 0xb9, 0xf6, 0xd0, 0x66, 0x09, 0xf2, 0xc6, 0xd9, 0x7e, 0xd2, 0xd6, ++ 0x1b, 0x2d, 0x38, 0xff, 0xb4, 0x0e, 0xe9, 0x3b, 0xe0, 0x77, 0x2d, 0xda, ++ 0x6e, 0x54, 0x70, 0x3f, 0x63, 0x8d, 0xac, 0x61, 0x79, 0x35, 0x9b, 0xcd, ++ 0x4f, 0x3e, 0xc8, 0xb1, 0x87, 0x7c, 0x89, 0xd7, 0xf4, 0x66, 0xc3, 0x39, ++ 0x1d, 0xee, 0x4d, 0x2e, 0xd0, 0x13, 0xf5, 0x27, 0xec, 0x7d, 0xa2, 0xfe, ++ 0x74, 0x4e, 0x56, 0x9b, 0xe3, 0xf9, 0x0b, 0xc5, 0x29, 0x4c, 0xee, 0x4f, ++ 0x29, 0x4d, 0x85, 0x29, 0x28, 0x1f, 0xba, 0x9b, 0xad, 0x47, 0x84, 0xf0, ++ 0xdc, 0x33, 0x91, 0x7f, 0x9b, 0x28, 0xef, 0x96, 0x02, 0x47, 0x17, 0xda, ++ 0x6d, 0x22, 0xf0, 0x01, 0x1b, 0xbf, 0xef, 0xc1, 0x7a, 0x4a, 0x1c, 0xfd, ++ 0xf5, 0xa7, 0x30, 0xbf, 0xd8, 0x57, 0x28, 0x85, 0xac, 0x90, 0x47, 0xba, ++ 0x94, 0x84, 0xac, 0x63, 0xf8, 0x95, 0x9d, 0x6e, 0x4b, 0xdc, 0x78, 0xc6, ++ 0x4d, 0x29, 0xdc, 0x5f, 0xbe, 0x7c, 0x05, 0xcf, 0xb3, 0x53, 0xc5, 0xf9, ++ 0x7a, 0x59, 0xec, 0x7c, 0xbd, 0x6e, 0xd3, 0xb9, 0x95, 0x37, 0xf1, 0x7e, ++ 0x1e, 0x4a, 0xb1, 0xe3, 0xb5, 0x3b, 0x67, 0x0f, 0xdb, 0xa7, 0x6a, 0x3a, ++ 0x1f, 0xbd, 0xde, 0xb3, 0x92, 0xc4, 0xe2, 0x59, 0x71, 0xce, 0x8f, 0x1a, ++ 0x79, 0x0f, 0xe3, 0x4c, 0x27, 0xc7, 0x39, 0x5f, 0x44, 0xac, 0x3f, 0x6d, ++ 0xe7, 0xfb, 0x97, 0xab, 0x2e, 0x5a, 0x9a, 0xe2, 0xd1, 0xff, 0x61, 0x8a, ++ 0x82, 0x74, 0x3c, 0xaf, 0x59, 0xe3, 0xf6, 0xef, 0x5b, 0x9c, 0xde, 0xce, ++ 0x69, 0x5e, 0x3c, 0x57, 0xb5, 0xf5, 0x49, 0x0b, 0x9e, 0xa3, 0xef, 0x73, ++ 0xb7, 0x4e, 0xc1, 0xfd, 0xdd, 0x29, 0x5f, 0x23, 0x2c, 0xde, 0xc5, 0xe8, ++ 0xaf, 0xe7, 0x7a, 0xea, 0x73, 0x87, 0x36, 0x93, 0x14, 0x5c, 0xa7, 0x7e, ++ 0x1a, 0x7e, 0x27, 0x44, 0x2d, 0xb1, 0x41, 0x2c, 0x8f, 0x9c, 0xbc, 0xb1, ++ 0x05, 0xcf, 0x85, 0xdd, 0x0e, 0x79, 0x73, 0x39, 0xd1, 0xfe, 0xa5, 0x88, ++ 0x75, 0xeb, 0x9d, 0x87, 0xea, 0xf2, 0x8a, 0xd9, 0xf9, 0xf3, 0x10, 0xef, ++ 0xa9, 0x1d, 0x60, 0x79, 0xe5, 0x0b, 0x4b, 0x76, 0xf1, 0x3c, 0x92, 0x7e, ++ 0xdc, 0xaf, 0x68, 0xfe, 0x9d, 0x92, 0xd2, 0xba, 0x80, 0x0e, 0xf3, 0xf2, ++ 0xc2, 0xc6, 0xf0, 0x66, 0xc4, 0x3f, 0x5e, 0x8f, 0x1f, 0x7f, 0xb7, 0x84, ++ 0x78, 0x37, 0xe2, 0xef, 0xa8, 0x8c, 0xda, 0x57, 0xa9, 0x21, 0xee, 0xea, ++ 0x1c, 0x66, 0x72, 0xdf, 0xf9, 0x73, 0x6f, 0x37, 0xfe, 0x0e, 0x88, 0x5b, ++ 0xe0, 0x46, 0xbd, 0xb1, 0x26, 0x33, 0x7a, 0x3e, 0x58, 0xf9, 0xd0, 0xa1, ++ 0x2d, 0xb0, 0x04, 0x63, 0x3e, 0x1f, 0xcc, 0x7c, 0xbe, 0x90, 0xf0, 0xcb, ++ 0x54, 0x13, 0xae, 0x14, 0xfe, 0x58, 0x03, 0x09, 0x1d, 0x56, 0xa4, 0xd1, ++ 0x71, 0xe6, 0x44, 0xfe, 0xd8, 0x63, 0x29, 0x1c, 0x8f, 0xdc, 0x48, 0xfd, ++ 0x31, 0x3a, 0xfe, 0x77, 0xd9, 0x58, 0x3e, 0xad, 0x6f, 0xbd, 0x54, 0x02, ++ 0x4e, 0x63, 0xd2, 0x7a, 0x69, 0x32, 0xd8, 0xaf, 0x1f, 0xf1, 0x71, 0x7a, ++ 0xb3, 0x3c, 0x80, 0xe7, 0xb4, 0xb4, 0x26, 0xd8, 0x67, 0x77, 0x69, 0xa4, ++ 0x5c, 0x18, 0xf7, 0x33, 0x75, 0xe6, 0x04, 0xdc, 0xde, 0x31, 0xca, 0xdf, ++ 0x94, 0x22, 0xb3, 0x7d, 0x79, 0x97, 0xd9, 0xf9, 0x1e, 0xaa, 0x9d, 0xe5, ++ 0x71, 0x8d, 0x5c, 0x79, 0xfe, 0x8b, 0x90, 0xeb, 0x59, 0x4e, 0x1b, 0x96, ++ 0x2f, 0x71, 0x32, 0xbd, 0xa8, 0xb8, 0xf2, 0x42, 0xd6, 0x58, 0xf3, 0x67, ++ 0xa9, 0x2f, 0x40, 0xa0, 0x3f, 0xd4, 0xbe, 0xc4, 0xcd, 0x0f, 0x7b, 0x31, ++ 0x85, 0xed, 0x47, 0x54, 0xc3, 0xec, 0x9c, 0x0a, 0xb5, 0xed, 0xbd, 0xea, ++ 0x78, 0xfa, 0x2c, 0xf4, 0x70, 0x9d, 0xda, 0xb4, 0x0f, 0xec, 0xc7, 0x16, ++ 0x69, 0x6d, 0x28, 0x09, 0xed, 0xc0, 0xd5, 0x9f, 0x5f, 0x79, 0x8b, 0xfc, ++ 0xd9, 0xed, 0xcd, 0x65, 0x4d, 0x3f, 0x9c, 0x42, 0xfb, 0xff, 0x9a, 0xf5, ++ 0x47, 0x1e, 0xd0, 0x8f, 0xcd, 0x01, 0xe3, 0xef, 0x4b, 0x89, 0xeb, 0x6b, ++ 0x5a, 0xc0, 0x8e, 0xfc, 0x77, 0x1f, 0x72, 0x80, 0xbf, 0x79, 0x3e, 0x39, ++ 0x70, 0x1c, 0xe8, 0x86, 0x78, 0x37, 0xec, 0x23, 0xec, 0x8c, 0xbc, 0x68, ++ 0x47, 0x7b, 0x6a, 0xe2, 0xbb, 0xb9, 0x9e, 0xb5, 0x4e, 0xc6, 0x77, 0xd5, ++ 0xc3, 0xde, 0x93, 0x7f, 0xd3, 0x3d, 0x8b, 0x63, 0xe2, 0x24, 0x75, 0x4e, ++ 0x89, 0xcf, 0x1f, 0xfa, 0x5b, 0x40, 0xd7, 0x4c, 0xab, 0xfe, 0x36, 0xb4, ++ 0xf3, 0x48, 0x65, 0xfc, 0x75, 0xc8, 0x4c, 0xa5, 0xf2, 0x1d, 0x78, 0x5f, ++ 0xa9, 0x35, 0xfd, 0x01, 0xae, 0x9d, 0x91, 0xdd, 0x18, 0x3f, 0x4e, 0x4e, ++ 0xd6, 0xff, 0x07, 0x7c, 0x5f, 0xae, 0xe8, 0xff, 0x0e, 0xcf, 0xff, 0xc9, ++ 0xaa, 0xf7, 0x33, 0x3b, 0x5d, 0xed, 0x3a, 0x53, 0x10, 0xdd, 0xd7, 0x90, ++ 0x68, 0x9c, 0x61, 0xe1, 0xe2, 0x4c, 0x41, 0x2c, 0xbf, 0x3e, 0x1b, 0x9f, ++ 0x33, 0xec, 0x4d, 0x43, 0x6c, 0x9c, 0xf5, 0x80, 0x76, 0x8d, 0xe3, 0xec, ++ 0xa4, 0xd7, 0x2f, 0xc1, 0xdc, 0x42, 0x9f, 0xf7, 0x97, 0xc7, 0x5f, 0x6f, ++ 0xff, 0x11, 0x97, 0x27, 0xaa, 0x67, 0x98, 0xaf, 0x20, 0xf6, 0xbd, 0xf8, ++ 0xdc, 0x44, 0x8f, 0x37, 0x7f, 0x89, 0xf2, 0x74, 0xfc, 0x65, 0x27, 0xe6, ++ 0xb5, 0x07, 0x9b, 0x20, 0xaf, 0xf3, 0xe4, 0x14, 0x0b, 0xd9, 0x1d, 0x63, ++ 0xe7, 0xc4, 0x79, 0x05, 0xad, 0x11, 0xe6, 0x17, 0x5e, 0x78, 0x48, 0xda, ++ 0xcd, 0xfc, 0x42, 0x82, 0xf7, 0x3f, 0xff, 0x7a, 0xce, 0x6e, 0x58, 0xdf, ++ 0x5d, 0x3a, 0x8d, 0xeb, 0x31, 0xdf, 0x77, 0x71, 0xf7, 0x43, 0xc6, 0xfd, ++ 0xd0, 0xa2, 0xdd, 0x39, 0xa9, 0x7c, 0xfc, 0xc7, 0xd1, 0xcf, 0x36, 0x5e, ++ 0x6e, 0x73, 0x2a, 0xd3, 0xcf, 0x1f, 0xa4, 0xb2, 0x78, 0xd8, 0x55, 0xeb, ++ 0x67, 0x06, 0xab, 0x47, 0xe8, 0xa9, 0xaa, 0xb0, 0xeb, 0x5d, 0x2e, 0x26, ++ 0x5f, 0xef, 0xa7, 0xb2, 0xab, 0x2d, 0x4d, 0x12, 0xf9, 0xeb, 0xd3, 0x81, ++ 0x0f, 0x54, 0x0f, 0xfb, 0x53, 0xae, 0x6d, 0x7c, 0x9e, 0x5a, 0x92, 0xf7, ++ 0xd9, 0xe5, 0x43, 0xe8, 0x83, 0xea, 0x35, 0xe6, 0xe7, 0x6d, 0xe3, 0xfa, ++ 0x22, 0xec, 0x15, 0xa5, 0xb3, 0xd4, 0xc9, 0xec, 0x45, 0x20, 0xf9, 0xda, ++ 0xe8, 0xcc, 0x2c, 0xfd, 0x1c, 0xe4, 0x58, 0xec, 0x3f, 0x90, 0x1d, 0x92, ++ 0x21, 0x1e, 0xbe, 0xc0, 0xc9, 0xe3, 0x95, 0x5c, 0x7f, 0x4f, 0x29, 0xfa, ++ 0x42, 0xa0, 0x93, 0xea, 0xef, 0x1d, 0x28, 0x5f, 0x89, 0xf5, 0x77, 0x89, ++ 0x93, 0xe9, 0xef, 0x17, 0x9c, 0x46, 0xfd, 0x5d, 0xe6, 0x64, 0xfa, 0xfb, ++ 0x45, 0x27, 0xd3, 0xdf, 0x66, 0xe7, 0x67, 0xd0, 0xdf, 0x0f, 0xb8, 0xfe, ++ 0xf8, 0x79, 0x1c, 0x9f, 0x1c, 0x37, 0xda, 0x1d, 0x8a, 0x8b, 0xef, 0x81, ++ 0xfa, 0xeb, 0x15, 0x89, 0xef, 0xe7, 0x26, 0x7f, 0x94, 0x62, 0xfc, 0x8f, ++ 0xfa, 0x81, 0x00, 0xd1, 0xd9, 0x64, 0xf9, 0x5c, 0x2c, 0x6e, 0xa0, 0xf8, ++ 0x55, 0xc7, 0xfd, 0x1b, 0x6f, 0x1a, 0xeb, 0x7b, 0x8b, 0x8f, 0x17, 0xb5, ++ 0x63, 0xf7, 0x43, 0xbd, 0x6f, 0x41, 0xfb, 0xb4, 0x3f, 0x9b, 0xff, 0x3b, ++ 0xe3, 0x1f, 0xf0, 0xf1, 0xc5, 0x38, 0x7a, 0x29, 0xf8, 0x28, 0xdb, 0x5a, ++ 0xdc, 0xb0, 0xff, 0x35, 0xd1, 0x3c, 0xb7, 0xc0, 0xc9, 0xe6, 0x19, 0xbf, ++ 0x8d, 0xed, 0xaf, 0x20, 0xc7, 0x68, 0xfb, 0x45, 0x86, 0xfe, 0x7c, 0x17, ++ 0xf8, 0x37, 0xd2, 0x9f, 0x20, 0xf5, 0xec, 0xe2, 0xf7, 0x27, 0x18, 0xb7, ++ 0x3f, 0x7d, 0xc6, 0xfa, 0x62, 0xfa, 0xf3, 0x08, 0xd4, 0x2b, 0xfa, 0x53, ++ 0x71, 0xe5, 0xf8, 0x98, 0xfa, 0xe8, 0x13, 0xfa, 0xe8, 0x0a, 0xcb, 0x30, ++ 0x6f, 0xfb, 0x94, 0xf8, 0xf3, 0x42, 0xaf, 0x93, 0xcd, 0xdb, 0x1f, 0x3a, ++ 0xf4, 0x27, 0xa1, 0x7e, 0xb3, 0x7c, 0x89, 0xeb, 0x3f, 0x72, 0x7d, 0x48, ++ 0xb4, 0x0f, 0xe6, 0x94, 0x52, 0xf9, 0x8f, 0xc0, 0xef, 0x52, 0x85, 0xd9, ++ 0x41, 0xa2, 0x85, 0xfb, 0xe5, 0x98, 0xfe, 0x95, 0x16, 0xb4, 0x88, 0x7e, ++ 0x07, 0x2c, 0xb1, 0x71, 0xb6, 0x81, 0xf8, 0x76, 0xf2, 0x17, 0xce, 0x11, ++ 0xfb, 0xf0, 0x0b, 0x94, 0xbf, 0x9d, 0x6c, 0xdf, 0x0e, 0x95, 0xeb, 0x5f, ++ 0xc2, 0xfd, 0x5d, 0x13, 0x5c, 0xcb, 0x70, 0x9f, 0xd7, 0x47, 0xcc, 0x6e, ++ 0xbe, 0xf5, 0xc9, 0x7a, 0x6b, 0x1a, 0x6d, 0xa7, 0x39, 0xe3, 0x89, 0xef, ++ 0xc1, 0xf5, 0x1d, 0x67, 0x1a, 0xd2, 0xdb, 0x32, 0x94, 0xeb, 0x84, 0x61, ++ 0xe8, 0x2f, 0x67, 0xfb, 0x1f, 0x5b, 0x27, 0xb3, 0x73, 0xd3, 0x5a, 0x25, ++ 0xe3, 0xf9, 0x69, 0xef, 0xf0, 0xf6, 0x6e, 0xe2, 0xf6, 0xe9, 0x1a, 0xf4, ++ 0xfb, 0xad, 0x5c, 0xf9, 0xd3, 0xeb, 0xc7, 0x67, 0xb5, 0x0b, 0x94, 0x3f, ++ 0x27, 0x84, 0xfd, 0x4c, 0xca, 0xbb, 0x36, 0xbb, 0x34, 0xfb, 0x73, 0x68, ++ 0x7f, 0xe9, 0x34, 0x82, 0xf8, 0xb8, 0x75, 0x97, 0x8a, 0xe7, 0x6c, 0x09, ++ 0xbd, 0xb9, 0x0b, 0xc6, 0x96, 0x9d, 0x77, 0xa0, 0x43, 0x1e, 0xc5, 0x57, ++ 0xe9, 0xbd, 0x85, 0xde, 0x0f, 0x81, 0xd3, 0x0d, 0xf6, 0x2a, 0x9b, 0x10, ++ 0xf7, 0x4c, 0x2c, 0x17, 0x54, 0xf1, 0x3c, 0x04, 0xfd, 0x3f, 0x98, 0x3d, ++ 0xd2, 0xcf, 0xc0, 0x95, 0xda, 0xa1, 0x0f, 0xb8, 0x1d, 0x1a, 0x80, 0x2b, ++ 0xb5, 0x43, 0x67, 0x3f, 0x8b, 0x1d, 0x3a, 0xec, 0x64, 0x76, 0xa8, 0x8d, ++ 0xca, 0x50, 0x1f, 0xc8, 0xa1, 0x12, 0x62, 0xf9, 0xbd, 0xdc, 0x9f, 0xaa, ++ 0xe7, 0x7d, 0x2d, 0x2d, 0x38, 0x6c, 0x88, 0xdb, 0x09, 0x7f, 0xaa, 0x73, ++ 0x60, 0xb7, 0x16, 0x84, 0xbc, 0xc1, 0x02, 0xb6, 0x1f, 0x35, 0x51, 0xbb, ++ 0x61, 0xf0, 0x37, 0x20, 0x71, 0x25, 0xc1, 0xef, 0x56, 0x89, 0xab, 0xff, ++ 0xc9, 0x15, 0x76, 0x70, 0x02, 0x36, 0x53, 0x5c, 0x07, 0x71, 0x54, 0xf1, ++ 0x3b, 0x7a, 0x9d, 0xd0, 0xbe, 0x06, 0xed, 0x59, 0xf0, 0x77, 0x7e, 0x5e, ++ 0x23, 0x32, 0xae, 0xc3, 0x9b, 0xeb, 0x6b, 0x9d, 0xca, 0xe7, 0xfd, 0x14, ++ 0x2e, 0xcf, 0x93, 0x57, 0xa2, 0x7f, 0x65, 0xfe, 0x1d, 0xbd, 0x2a, 0x77, ++ 0x68, 0xfb, 0x4c, 0x5a, 0x8f, 0xef, 0xd8, 0xdd, 0x6c, 0x9f, 0xd5, 0xe5, ++ 0xbb, 0xc9, 0xb2, 0x22, 0xc0, 0x27, 0x01, 0x02, 0xe7, 0x6d, 0xaa, 0xf4, ++ 0x0a, 0xf9, 0x9b, 0x82, 0xee, 0x69, 0xa9, 0xd7, 0x93, 0xd8, 0xdf, 0x23, ++ 0x56, 0x89, 0xa4, 0xcc, 0x2b, 0x8c, 0xda, 0x91, 0xaa, 0x08, 0x09, 0x57, ++ 0x14, 0x23, 0xbe, 0xc1, 0xfd, 0x5c, 0x50, 0x8f, 0x87, 0xd7, 0x13, 0x28, ++ 0x82, 0xf9, 0x3e, 0x4d, 0x81, 0xf5, 0xbe, 0xd7, 0x12, 0xfc, 0x1e, 0xd3, ++ 0x93, 0x72, 0x60, 0x7a, 0x6a, 0x4c, 0xfd, 0x7e, 0x62, 0xc4, 0x2b, 0x74, ++ 0xfc, 0xaf, 0x4f, 0x9d, 0x8d, 0xe3, 0x7f, 0x03, 0x94, 0xa3, 0xe3, 0x5f, ++ 0x90, 0xca, 0xe6, 0xa1, 0x1b, 0xe1, 0xf9, 0x59, 0x27, 0xb3, 0x7f, 0x4f, ++ 0xca, 0x4d, 0x85, 0xf0, 0x3c, 0x90, 0xc1, 0x96, 0xa0, 0x69, 0xf9, 0x22, ++ 0x5e, 0x7e, 0x46, 0xea, 0xe7, 0x20, 0x27, 0x9b, 0x09, 0xfb, 0xfd, 0x5d, ++ 0x90, 0xdf, 0xd8, 0xf5, 0xea, 0xdd, 0xdc, 0x3e, 0x74, 0x4c, 0x0c, 0x94, ++ 0x43, 0x3b, 0xd5, 0x3f, 0x5f, 0xd4, 0x33, 0x85, 0x7e, 0xb2, 0xba, 0xbd, ++ 0x05, 0xcf, 0x39, 0xae, 0xb8, 0x2e, 0xf2, 0xd1, 0x29, 0xc8, 0xbf, 0xcd, ++ 0x52, 0x71, 0x3d, 0xb0, 0xf5, 0x51, 0xe3, 0x3c, 0xf2, 0x1c, 0xff, 0xfe, ++ 0x40, 0xaa, 0x88, 0xdf, 0x5d, 0x1b, 0x8e, 0xa0, 0xf6, 0xaf, 0x3e, 0x15, ++ 0xe9, 0x63, 0xf6, 0x2f, 0xe8, 0x66, 0xbf, 0x33, 0xda, 0x32, 0x39, 0xf7, ++ 0x31, 0x06, 0x1f, 0xa9, 0x83, 0x99, 0x19, 0x3d, 0xbf, 0xb6, 0xda, 0xb5, ++ 0x08, 0xcf, 0xe7, 0xfa, 0xc6, 0x0b, 0x39, 0x33, 0xe1, 0xbc, 0x2b, 0x95, ++ 0xdb, 0xe7, 0x79, 0xee, 0x6e, 0x75, 0x05, 0x8c, 0x6b, 0xa4, 0x3f, 0x6e, ++ 0xbe, 0xe9, 0x57, 0x46, 0xec, 0x20, 0xb5, 0xde, 0x86, 0x79, 0x2a, 0xfe, ++ 0x39, 0x2f, 0xf7, 0xa7, 0x32, 0x5c, 0x4b, 0xf5, 0xf8, 0xab, 0x7c, 0xfc, ++ 0xee, 0x02, 0x3a, 0x5f, 0x9c, 0xa8, 0x07, 0x52, 0x67, 0xff, 0xd7, 0xd9, ++ 0x47, 0x61, 0x87, 0x02, 0x0a, 0xb3, 0x37, 0xd4, 0x6f, 0x0a, 0x82, 0xdf, ++ 0xb4, 0xec, 0xd2, 0xda, 0x23, 0x30, 0x4d, 0x35, 0x93, 0x27, 0x6a, 0x60, ++ 0x7d, 0x83, 0xca, 0xe5, 0xdf, 0x01, 0x9d, 0x5f, 0xb6, 0xef, 0x3d, 0xc2, ++ 0x7e, 0x7a, 0x30, 0x38, 0x05, 0xda, 0xa5, 0xf2, 0xf8, 0x70, 0x2a, 0xb3, ++ 0x47, 0x7f, 0x9f, 0xca, 0xec, 0xd1, 0x77, 0x52, 0x99, 0x3d, 0xfa, 0x87, ++ 0xcf, 0x22, 0x67, 0xf7, 0xa6, 0x92, 0x31, 0xf1, 0xa7, 0xc0, 0xe1, 0x02, ++ 0x7f, 0x53, 0x3b, 0xbf, 0x2d, 0x95, 0xe1, 0x4f, 0x8f, 0xf3, 0xf3, 0x99, ++ 0x37, 0x76, 0xf2, 0xfa, 0x02, 0xce, 0x6b, 0x9c, 0x37, 0xbe, 0xf4, 0x39, ++ 0xb4, 0x4f, 0xf1, 0xc6, 0xcf, 0x50, 0x5f, 0x39, 0x1f, 0x12, 0xe1, 0xdb, ++ 0x5f, 0x70, 0xb9, 0xfa, 0x65, 0xaa, 0x88, 0xfb, 0xe9, 0xbf, 0x04, 0xfe, ++ 0x2f, 0xb4, 0xeb, 0xff, 0x9c, 0x1a, 0x8b, 0x37, 0x0a, 0x8f, 0xfd, 0x11, ++ 0xf2, 0xe4, 0xa2, 0x78, 0xa3, 0x5b, 0xe6, 0x78, 0x43, 0x89, 0x8d, 0x67, ++ 0xfb, 0x28, 0xfe, 0xe2, 0x79, 0x75, 0xf7, 0x58, 0xe6, 0x44, 0xf5, 0x44, ++ 0x8d, 0xc4, 0xc7, 0x21, 0xf3, 0x53, 0x47, 0x70, 0x48, 0x07, 0x8e, 0xf7, ++ 0x76, 0x86, 0x43, 0xe6, 0x8f, 0xd0, 0xed, 0x1d, 0x08, 0x81, 0x1e, 0x4e, ++ 0xe1, 0xfa, 0xfe, 0x3b, 0x66, 0x8f, 0x5b, 0xd4, 0xfe, 0x7b, 0xf0, 0x1c, ++ 0xdc, 0x74, 0x46, 0xb7, 0x94, 0xce, 0xc6, 0xf1, 0x28, 0xef, 0xc7, 0xbb, ++ 0x52, 0x4a, 0xdc, 0xf8, 0xe6, 0xb1, 0x68, 0x7b, 0xc7, 0xb0, 0xbd, 0xf5, ++ 0xac, 0x3d, 0xd9, 0x71, 0x2b, 0xfb, 0xdd, 0x0f, 0x61, 0x57, 0xac, 0x12, ++ 0xb6, 0x23, 0xe2, 0xc3, 0xf3, 0xd3, 0xd9, 0x77, 0xa2, 0x9d, 0x79, 0xfc, ++ 0x2a, 0x70, 0xaa, 0xb9, 0x9d, 0xdf, 0x46, 0xdb, 0xf9, 0x2d, 0xb6, 0xf3, ++ 0x90, 0xd8, 0x07, 0xac, 0xbf, 0x05, 0xf7, 0xbe, 0x28, 0x5f, 0xc3, 0xb1, ++ 0x7c, 0x05, 0xfb, 0x62, 0x99, 0x13, 0xc3, 0x4f, 0x8e, 0xeb, 0x12, 0xe1, ++ 0xb8, 0x18, 0xfe, 0xbd, 0x87, 0x76, 0xa0, 0x8d, 0xb5, 0x33, 0xc2, 0xbf, ++ 0x40, 0x7c, 0x3b, 0xbb, 0xcc, 0x25, 0x0b, 0x39, 0x19, 0x48, 0x1d, 0x43, ++ 0x3e, 0xce, 0x71, 0xf9, 0x38, 0x1f, 0x95, 0x8f, 0xf3, 0x5c, 0x3e, 0x3e, ++ 0x4c, 0x45, 0x7c, 0xc2, 0xc6, 0xe1, 0xae, 0x09, 0xc6, 0xfd, 0xe5, 0xc3, ++ 0x5c, 0xaf, 0x1e, 0xe1, 0x7c, 0x12, 0xe3, 0x65, 0xa6, 0xbf, 0x95, 0xbf, ++ 0x1f, 0xe1, 0x87, 0xe7, 0xd8, 0x73, 0xb1, 0xb8, 0xd6, 0x57, 0x90, 0xb6, ++ 0xac, 0x19, 0xe2, 0x96, 0x6d, 0xb2, 0xd7, 0xe2, 0x19, 0x2d, 0x6f, 0xf4, ++ 0x5f, 0x3e, 0xe0, 0xdd, 0xff, 0x05, 0xcc, 0x52, 0xb1, 0xef, 0x00, 0x80, ++ 0x00, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x0b, 0xe5, 0x7d, 0x0b, 0x60, 0x14, 0xd5, 0xb9, 0xf0, 0x99, 0x9d, ++ 0xd9, 0xd9, 0x4d, 0xb2, 0x9b, 0x4c, 0xde, 0x1b, 0x48, 0xc2, 0x26, 0x80, ++ 0x0d, 0x1a, 0x70, 0x09, 0x21, 0x06, 0x08, 0x3a, 0x79, 0xf2, 0x0a, 0x10, ++ 0x11, 0x10, 0x14, 0x61, 0x79, 0x85, 0xf0, 0x4a, 0x22, 0x62, 0xeb, 0xf3, ++ 0x67, 0x31, 0x21, 0x3c, 0xd5, 0xe8, 0x55, 0x6b, 0x5b, 0xb4, 0x0b, 0x82, ++ 0x62, 0x8b, 0x36, 0x60, 0xaa, 0x88, 0x01, 0x37, 0x20, 0x88, 0xef, 0xd0, ++ 0x2a, 0x68, 0xf5, 0xb6, 0x41, 0xac, 0xa0, 0x22, 0x59, 0x50, 0xeb, 0xda, ++ 0xda, 0xf2, 0x9f, 0xef, 0x3b, 0x67, 0xb2, 0x33, 0x9b, 0x5d, 0xc0, 0xda, ++ 0xf6, 0x7a, 0xff, 0x3f, 0xde, 0xde, 0xc3, 0x39, 0x73, 0x9e, 0xdf, 0xfb, ++ 0xfb, 0xce, 0x37, 0xb3, 0x45, 0x84, 0xfd, 0xc9, 0x27, 0xbd, 0x92, 0x3b, ++ 0x97, 0x90, 0xb1, 0x7e, 0xa2, 0x7a, 0x6d, 0x84, 0x9c, 0x83, 0xbf, 0xab, ++ 0x82, 0xa5, 0x55, 0x11, 0x08, 0x49, 0x26, 0x64, 0x99, 0x5c, 0x65, 0x55, ++ 0x86, 0xd2, 0x01, 0x65, 0xf5, 0xce, 0xaa, 0x81, 0x84, 0xb4, 0x97, 0x74, ++ 0x2e, 0xa9, 0x0a, 0xd3, 0xff, 0xb6, 0x04, 0xda, 0x9f, 0xf6, 0x9b, 0x9e, ++ 0xbe, 0xa9, 0x2c, 0xd9, 0x49, 0xfb, 0x7b, 0x68, 0x7b, 0x0a, 0x21, 0xc3, ++ 0x1d, 0xf4, 0xdf, 0x22, 0x21, 0xd7, 0xd5, 0xb4, 0x8b, 0x6e, 0xdd, 0xb8, ++ 0xe9, 0x9f, 0x7e, 0x3c, 0x4f, 0x0d, 0x33, 0xcf, 0x4f, 0x12, 0x4c, 0xb8, ++ 0x6e, 0xc3, 0x0c, 0xd7, 0x21, 0x67, 0x3e, 0x9d, 0xc6, 0x61, 0x72, 0x6d, ++ 0x25, 0x3d, 0xfb, 0x35, 0xc7, 0xcb, 0xb8, 0xde, 0xa8, 0x6c, 0xaf, 0x14, ++ 0x47, 0xfb, 0xbd, 0x79, 0x86, 0x28, 0x9b, 0x69, 0xbf, 0xeb, 0x26, 0x0b, ++ 0xaa, 0x97, 0x9e, 0xab, 0x82, 0x9f, 0xcb, 0x96, 0xc0, 0xce, 0x91, 0xa5, ++ 0x48, 0xd8, 0x5f, 0xe5, 0xfb, 0x1c, 0x25, 0x77, 0xce, 0x0b, 0x77, 0x8e, ++ 0x7c, 0xfe, 0x7c, 0xb4, 0x93, 0xa8, 0x2d, 0x74, 0x9e, 0xd1, 0x0a, 0x51, ++ 0x77, 0x86, 0xe9, 0x57, 0x08, 0xfb, 0x84, 0x79, 0xa2, 0xc3, 0xcf, 0x33, ++ 0x8d, 0xcf, 0x33, 0x86, 0xb0, 0x79, 0x42, 0x9f, 0xcf, 0xe0, 0xfb, 0x1a, ++ 0x55, 0x12, 0x7e, 0xfc, 0x08, 0x3e, 0xff, 0x34, 0xc7, 0x8e, 0xf2, 0x04, ++ 0x02, 0xfb, 0xd9, 0x64, 0x06, 0xf8, 0xe5, 0x99, 0xd5, 0x61, 0x0a, 0x1d, ++ 0xb7, 0x36, 0x02, 0x1e, 0x52, 0xa4, 0x92, 0x91, 0x80, 0xaf, 0x28, 0x0a, ++ 0x3a, 0x73, 0x1e, 0x21, 0x33, 0xe9, 0x58, 0x13, 0x9d, 0x60, 0x16, 0xe0, ++ 0x9c, 0x96, 0x0f, 0x8a, 0xee, 0x52, 0x78, 0xee, 0xa6, 0xe0, 0x70, 0xe4, ++ 0x01, 0x25, 0x78, 0x7a, 0x01, 0x5e, 0x4b, 0x6c, 0x6a, 0x19, 0xb4, 0x47, ++ 0x47, 0xab, 0xe5, 0x30, 0xff, 0x48, 0x49, 0xad, 0x80, 0xf2, 0x97, 0x66, ++ 0x75, 0x14, 0xe2, 0x9f, 0xf8, 0x08, 0x29, 0x20, 0x64, 0x02, 0xa7, 0x9f, ++ 0x09, 0x56, 0x9b, 0x4f, 0x8c, 0xa5, 0xff, 0x28, 0x34, 0x9f, 0xea, 0xb4, ++ 0xb2, 0xb6, 0x73, 0xd9, 0xf0, 0xff, 0x67, 0x28, 0x1f, 0x5f, 0x46, 0x88, ++ 0x40, 0x7c, 0xc2, 0xb9, 0xcb, 0xa0, 0xee, 0x15, 0x61, 0xfe, 0xe1, 0xce, ++ 0x43, 0xef, 0x0a, 0xb4, 0xff, 0x70, 0x6d, 0xdc, 0x49, 0x29, 0x64, 0x5c, ++ 0xba, 0xf2, 0x71, 0x0c, 0xaf, 0x8b, 0xb8, 0x2f, 0x84, 0xcf, 0x6e, 0xf3, ++ 0x4f, 0x9d, 0x36, 0x53, 0xcf, 0x73, 0x6a, 0xe5, 0x6e, 0x9b, 0xdb, 0x0a, ++ 0x70, 0x38, 0x1d, 0xed, 0x9e, 0x09, 0xfb, 0x6c, 0x70, 0x6c, 0xb6, 0x39, ++ 0x29, 0xbc, 0x5f, 0x75, 0xb7, 0x58, 0x5d, 0xb4, 0xfd, 0x64, 0x1c, 0x41, ++ 0x38, 0x76, 0xc5, 0xa8, 0x6e, 0x7c, 0xbe, 0x9b, 0xd4, 0xb4, 0xd0, 0x76, ++ 0x31, 0x46, 0xa8, 0x6f, 0xd1, 0xc1, 0x6f, 0xbe, 0xc2, 0xe0, 0x5d, 0xad, ++ 0x30, 0xbc, 0xbd, 0x25, 0xa9, 0xd5, 0x70, 0xfe, 0x09, 0x56, 0x75, 0x01, ++ 0x8c, 0x9b, 0x9c, 0x49, 0xf1, 0x44, 0xe7, 0x9d, 0x95, 0xd8, 0xb9, 0x5c, ++ 0x0f, 0xf7, 0x7a, 0x8e, 0xa7, 0x85, 0x9c, 0x6e, 0x67, 0xca, 0xac, 0x5f, ++ 0xe8, 0x3e, 0xab, 0xf9, 0xf3, 0x22, 0x49, 0xf0, 0xc4, 0xc0, 0x9e, 0x6c, ++ 0x87, 0x3e, 0x12, 0x81, 0x3f, 0x48, 0xf7, 0x5f, 0x3f, 0x13, 0xad, 0x8f, ++ 0x85, 0x7f, 0x51, 0xfe, 0x29, 0x3a, 0xa9, 0x4c, 0x9d, 0x96, 0x44, 0x71, ++ 0xb6, 0x46, 0x74, 0x99, 0x68, 0x5d, 0xce, 0x11, 0xc2, 0xf2, 0xe9, 0x9d, ++ 0x7c, 0xbf, 0x94, 0x4f, 0xef, 0x84, 0xfd, 0x12, 0x27, 0xe5, 0x53, 0x3b, ++ 0xa5, 0x0f, 0x39, 0x3c, 0x7d, 0x7c, 0xc5, 0xfb, 0x97, 0x47, 0xa0, 0xcb, ++ 0x3c, 0x7e, 0x9e, 0x32, 0x78, 0x1e, 0x66, 0xfc, 0xa5, 0x9c, 0xae, 0xcb, ++ 0x92, 0xda, 0x45, 0x42, 0xc7, 0x17, 0x71, 0x7e, 0x0b, 0xed, 0x37, 0x37, ++ 0x41, 0xc4, 0x7e, 0x0d, 0x2e, 0x32, 0x3a, 0xdc, 0x3c, 0x0f, 0x04, 0xe5, ++ 0xcb, 0x03, 0x48, 0x5f, 0x0a, 0xdb, 0x77, 0x9e, 0xb9, 0xea, 0x21, 0xa8, ++ 0xcf, 0x50, 0x0e, 0x97, 0xc7, 0xd3, 0xe6, 0xe2, 0xbb, 0x93, 0xa6, 0x92, ++ 0x24, 0x80, 0x87, 0x89, 0x58, 0xb2, 0x10, 0x4e, 0x56, 0x42, 0xe1, 0x24, ++ 0x71, 0x38, 0xd1, 0x6d, 0x12, 0xa8, 0x2f, 0xb3, 0xb2, 0xba, 0x14, 0xbd, ++ 0x84, 0xc4, 0xd1, 0x32, 0xd3, 0xe1, 0x5d, 0x3f, 0x08, 0xe0, 0xd7, 0x68, ++ 0x76, 0x39, 0x69, 0xfd, 0xc3, 0x93, 0x1f, 0x8a, 0x84, 0xd2, 0xd9, 0xd6, ++ 0x07, 0xce, 0x0a, 0x84, 0xca, 0x8b, 0xdd, 0x7e, 0x42, 0x12, 0xb3, 0x60, ++ 0x1e, 0x19, 0x66, 0x84, 0x3f, 0xd3, 0x39, 0xa1, 0xe7, 0x7c, 0xf4, 0x99, ++ 0x53, 0xd2, 0xd6, 0xa3, 0xa0, 0xb9, 0xf2, 0x24, 0x51, 0x2d, 0x94, 0x7e, ++ 0xaf, 0x2c, 0xf4, 0x4f, 0x22, 0xb1, 0x86, 0xf1, 0xe4, 0x1c, 0x9d, 0xcf, ++ 0xe6, 0xef, 0xf0, 0x08, 0x80, 0x3f, 0x2b, 0xf1, 0xc4, 0x5c, 0x8e, 0x64, ++ 0xfc, 0x76, 0xbf, 0x14, 0x9c, 0x15, 0xe7, 0x4b, 0xa5, 0xeb, 0xc2, 0x79, ++ 0xe4, 0x2f, 0x89, 0x17, 0xce, 0xa3, 0x3a, 0xdc, 0x95, 0x64, 0x10, 0x21, ++ 0xf1, 0xfe, 0xce, 0x5f, 0xd4, 0x61, 0xbb, 0xcd, 0x35, 0x0a, 0xcf, 0x45, ++ 0x6c, 0xc0, 0x6f, 0xc1, 0x73, 0x2e, 0x43, 0xfe, 0xd3, 0xf6, 0x25, 0xdb, ++ 0x3a, 0x1f, 0xbb, 0x97, 0xf6, 0x6f, 0xfb, 0x2a, 0xda, 0x75, 0x17, 0x9c, ++ 0xdb, 0x5f, 0xf1, 0x09, 0xdb, 0x0f, 0xf1, 0xd8, 0x81, 0xaf, 0xc5, 0x4a, ++ 0x17, 0xc8, 0x77, 0x42, 0x2c, 0xb8, 0x3f, 0x13, 0xfd, 0x0f, 0xf8, 0x6c, ++ 0x64, 0x80, 0xee, 0x37, 0x87, 0xef, 0x17, 0x16, 0xc9, 0xd7, 0xed, 0x9f, ++ 0xf4, 0x3c, 0xcf, 0x83, 0x62, 0xd5, 0x21, 0xc0, 0xc7, 0x2c, 0x2b, 0x51, ++ 0x63, 0xf3, 0x50, 0x3e, 0xbc, 0x02, 0xf5, 0xbe, 0x66, 0xda, 0x81, 0xc2, ++ 0xb1, 0x49, 0x11, 0xbc, 0x1e, 0xda, 0xaf, 0xe9, 0x81, 0x79, 0x6b, 0xb2, ++ 0x40, 0x5e, 0x6f, 0x90, 0x5c, 0xfd, 0x09, 0xd0, 0x39, 0xd9, 0x25, 0x50, ++ 0x3a, 0x1f, 0x41, 0xd7, 0xbd, 0x85, 0xca, 0x1d, 0xb9, 0x90, 0xd8, 0x14, ++ 0x5a, 0x97, 0x1d, 0xec, 0xfc, 0x4d, 0x77, 0x27, 0x6d, 0x8a, 0x11, 0xe0, ++ 0xb9, 0x44, 0x65, 0x21, 0x2d, 0xfd, 0xbe, 0x6f, 0x04, 0x0a, 0x87, 0x58, ++ 0x47, 0x75, 0xa5, 0x42, 0xcf, 0x21, 0xf3, 0xf1, 0x02, 0x05, 0x1c, 0x8c, ++ 0x17, 0x9c, 0x0a, 0x99, 0x91, 0x07, 0x74, 0xdb, 0x21, 0x12, 0x94, 0x0f, ++ 0x0e, 0x84, 0x87, 0xc6, 0x3f, 0xea, 0x8f, 0x88, 0xf0, 0xb1, 0x15, 0x55, ++ 0x0d, 0x01, 0xfa, 0x2a, 0x93, 0x88, 0xc7, 0x4a, 0xfb, 0x0b, 0x0e, 0x36, ++ 0xef, 0x95, 0xc4, 0x2f, 0x92, 0xbe, 0x80, 0x07, 0xaa, 0x08, 0x68, 0x59, ++ 0x42, 0x5c, 0x58, 0xde, 0x2b, 0xba, 0x3f, 0x06, 0xbe, 0xb1, 0xca, 0x14, ++ 0xaf, 0x74, 0xff, 0x56, 0x93, 0xd5, 0xbb, 0x52, 0x00, 0xfc, 0x55, 0xbd, ++ 0x3e, 0x1a, 0xe1, 0x5e, 0xa6, 0x7c, 0x9c, 0x13, 0x94, 0x67, 0x91, 0xe4, ++ 0x10, 0x40, 0xee, 0x63, 0x0d, 0xae, 0xe2, 0xf7, 0x97, 0x7b, 0xe5, 0xcb, ++ 0xc3, 0xf3, 0xd5, 0xdf, 0x82, 0x7c, 0xf3, 0x37, 0x26, 0x97, 0x99, 0x5e, ++ 0x9e, 0x9c, 0xcd, 0xe4, 0xce, 0x01, 0x7b, 0xe7, 0x0c, 0x3d, 0xdf, 0xaf, ++ 0x52, 0x98, 0xdc, 0x59, 0xc5, 0xc7, 0x11, 0x89, 0xf1, 0xd9, 0x32, 0x59, ++ 0x35, 0xc5, 0x9f, 0x87, 0xcf, 0xd7, 0xf2, 0x71, 0x97, 0x82, 0xf2, 0x01, ++ 0x7d, 0x4c, 0xc2, 0xf3, 0x71, 0x4b, 0x3c, 0x93, 0x07, 0x93, 0xef, 0xf2, ++ 0x36, 0xf5, 0xa2, 0xf0, 0x9b, 0x90, 0x20, 0xb8, 0x40, 0x0f, 0x97, 0x6f, ++ 0x9f, 0x2d, 0xf5, 0x76, 0x06, 0xfb, 0xa5, 0x72, 0x7d, 0xa7, 0xa4, 0xa8, ++ 0xf1, 0xf1, 0x30, 0xdf, 0x6e, 0xd7, 0x49, 0x6f, 0x12, 0x68, 0x1f, 0x19, ++ 0xf5, 0x7b, 0xd3, 0x7b, 0x64, 0x1a, 0xcc, 0x3f, 0x9b, 0xcb, 0xcf, 0x00, ++ 0x9f, 0xf7, 0x2f, 0xf1, 0x6c, 0x1f, 0xe9, 0xbc, 0x7e, 0x4c, 0xb0, 0x4f, ++ 0x0b, 0x07, 0x97, 0xcc, 0xf8, 0x6e, 0xb8, 0x64, 0xc2, 0xb9, 0x88, 0x9b, ++ 0xc1, 0x45, 0x8c, 0x19, 0xec, 0xf7, 0xd1, 0x75, 0x48, 0x6f, 0xbe, 0x8e, ++ 0x59, 0xc0, 0x75, 0xda, 0xb3, 0x99, 0x7c, 0xcc, 0xe6, 0xfb, 0xd2, 0xd6, ++ 0xe9, 0xc3, 0xe5, 0x1f, 0x95, 0xfb, 0x97, 0xc0, 0x3e, 0x27, 0x67, 0x7a, ++ 0xd3, 0xa1, 0xdf, 0xab, 0x66, 0xb6, 0xbf, 0xd0, 0x75, 0x07, 0x06, 0xd7, ++ 0x1d, 0x88, 0xeb, 0x2e, 0x61, 0xeb, 0x8e, 0x05, 0x39, 0x0f, 0xfc, 0xef, ++ 0x3c, 0xf4, 0x12, 0xc8, 0xf9, 0x22, 0x4e, 0xa7, 0x63, 0xfd, 0x6e, 0x02, ++ 0x76, 0x0f, 0xf0, 0xb0, 0xa9, 0x20, 0x28, 0xef, 0x65, 0xa7, 0x4f, 0xac, ++ 0xa7, 0xed, 0x45, 0x11, 0xe4, 0xfc, 0xf0, 0xe0, 0x3a, 0xc3, 0x71, 0x9d, ++ 0x7a, 0x86, 0xc7, 0x3d, 0x29, 0xea, 0x08, 0xd8, 0x27, 0xb5, 0x0b, 0x8a, ++ 0xa0, 0xbd, 0x3d, 0x5b, 0x41, 0x79, 0xf9, 0x66, 0x2f, 0x13, 0xd9, 0x4c, ++ 0xf9, 0x72, 0x76, 0x5a, 0xf6, 0x3d, 0x20, 0x36, 0xb5, 0x79, 0x76, 0xf2, ++ 0x73, 0xb6, 0x67, 0x35, 0x39, 0xe6, 0x50, 0x7c, 0xc9, 0x7e, 0xe2, 0xb2, ++ 0x20, 0x9d, 0xd7, 0xa0, 0xdc, 0x2b, 0xe2, 0xf2, 0xa5, 0x61, 0xb7, 0x9b, ++ 0xc0, 0x73, 0x4f, 0x2f, 0x2a, 0x33, 0x75, 0xe3, 0x65, 0xff, 0x1c, 0x2b, ++ 0xb1, 0xe1, 0x51, 0xfe, 0x71, 0x4e, 0xeb, 0x4f, 0xf9, 0xa8, 0xc9, 0x9f, ++ 0x1d, 0xe7, 0x0e, 0x83, 0x17, 0xad, 0x5c, 0xbf, 0x82, 0x89, 0x22, 0xe2, ++ 0x5c, 0x8a, 0xe3, 0x96, 0xf1, 0x71, 0xa1, 0xfd, 0x6c, 0x0f, 0xee, 0x8b, ++ 0x81, 0xf9, 0x37, 0x40, 0xff, 0x1f, 0x11, 0x32, 0x91, 0xeb, 0x1b, 0x7a, ++ 0x60, 0xdc, 0xdf, 0x58, 0xce, 0x3b, 0x0d, 0xfe, 0xcd, 0x31, 0x9d, 0xb4, ++ 0xdf, 0xee, 0x9c, 0xb9, 0x86, 0xfd, 0xe0, 0x73, 0xca, 0x47, 0x4d, 0x39, ++ 0x8f, 0xc5, 0x80, 0xbd, 0xd4, 0x96, 0x41, 0xf5, 0x00, 0xc8, 0xa9, 0x57, ++ 0x44, 0x94, 0x93, 0x4d, 0x76, 0x86, 0xc7, 0xa6, 0xb4, 0x6a, 0xa2, 0xb7, ++ 0x47, 0x4b, 0x1d, 0x3e, 0xf1, 0x63, 0x98, 0xe7, 0xdb, 0xb9, 0x64, 0x2a, ++ 0xc5, 0x5f, 0x91, 0xc3, 0x4d, 0x2e, 0xa1, 0xf0, 0x5d, 0xc7, 0xf7, 0x51, ++ 0xe4, 0xaa, 0xf6, 0x08, 0x49, 0xd8, 0xfe, 0x6c, 0x14, 0x9d, 0x67, 0x79, ++ 0xfc, 0x25, 0x08, 0x47, 0x39, 0xc7, 0x4d, 0x2a, 0x72, 0x01, 0x2e, 0x5e, ++ 0x52, 0x4d, 0xc7, 0xcb, 0x8a, 0x4f, 0x74, 0xd1, 0x7a, 0xa9, 0x9f, 0xf8, ++ 0xae, 0xca, 0x87, 0xfe, 0x54, 0xce, 0x0b, 0x6c, 0x3e, 0xa7, 0x5d, 0x3f, ++ 0x0f, 0x69, 0x81, 0x79, 0xe4, 0x5c, 0x46, 0x0f, 0xb2, 0xbf, 0x85, 0x00, ++ 0xfc, 0x76, 0x9f, 0x3c, 0x3f, 0x1c, 0x63, 0x72, 0x4c, 0x06, 0xf9, 0xad, ++ 0xf1, 0x25, 0xb5, 0xeb, 0x56, 0x00, 0x1d, 0x94, 0x29, 0x57, 0x97, 0xc5, ++ 0xd3, 0xf9, 0x17, 0x6d, 0xcf, 0xca, 0x13, 0xe9, 0xfc, 0x15, 0x8e, 0x76, ++ 0x79, 0x4e, 0x2e, 0xca, 0x6d, 0x0f, 0xd0, 0xc7, 0xce, 0x64, 0x75, 0x65, ++ 0xfc, 0xff, 0xa0, 0x3d, 0x37, 0x8d, 0x78, 0xcd, 0x80, 0xf7, 0x51, 0x99, ++ 0x4c, 0x0f, 0x4c, 0xa8, 0x15, 0xbc, 0x9b, 0x29, 0x7c, 0x9a, 0x42, 0xec, ++ 0x84, 0x9f, 0xc6, 0x33, 0x3e, 0x2c, 0x0c, 0xca, 0xbb, 0x9f, 0xe1, 0xbe, ++ 0x0b, 0x35, 0x3b, 0x41, 0xfd, 0x39, 0xd4, 0xcf, 0x63, 0x07, 0x3f, 0x0a, ++ 0xf0, 0x38, 0x8f, 0x1d, 0xbc, 0x05, 0x9e, 0x87, 0xb1, 0x83, 0xb7, 0x42, ++ 0x3b, 0x85, 0xd7, 0xe3, 0xf1, 0xcc, 0x0e, 0x7e, 0x02, 0xd6, 0xa1, 0x76, ++ 0xf0, 0xb6, 0xef, 0x03, 0xb7, 0x09, 0x0a, 0x93, 0xa3, 0xd4, 0x0e, 0xdd, ++ 0x01, 0xf3, 0xc6, 0x83, 0x71, 0x03, 0xf6, 0xd1, 0x1f, 0x98, 0x3d, 0x1a, ++ 0xba, 0xff, 0xdb, 0xf8, 0xf9, 0xd7, 0xd0, 0xb3, 0x76, 0x00, 0x5d, 0x4a, ++ 0x5e, 0x89, 0xd1, 0x39, 0xe3, 0xd3, 0xe1, 0x9c, 0x4f, 0xc7, 0x9e, 0xa4, ++ 0xfc, 0x92, 0xdb, 0x93, 0xfe, 0xdb, 0x28, 0xfd, 0x7b, 0x28, 0xfd, 0x9d, ++ 0xa5, 0x76, 0x93, 0x98, 0x15, 0x99, 0x9e, 0x7c, 0x17, 0xc9, 0x97, 0xc5, ++ 0x0f, 0x32, 0xbe, 0x6f, 0x70, 0xec, 0x43, 0xbe, 0x7b, 0x91, 0xf3, 0x45, ++ 0x1b, 0x5f, 0xbf, 0x2d, 0x47, 0xac, 0x04, 0x7c, 0xbe, 0x4a, 0x44, 0x45, ++ 0x14, 0x7a, 0xce, 0xd7, 0x94, 0xe1, 0x76, 0x80, 0x5c, 0x0f, 0xe5, 0x3f, ++ 0xf5, 0x5b, 0x23, 0x3d, 0x97, 0x3a, 0xbc, 0x1b, 0xf2, 0x80, 0x6f, 0x0e, ++ 0xcd, 0x75, 0xc1, 0xb6, 0x42, 0xf9, 0x51, 0xa6, 0x65, 0xf5, 0xc0, 0xe0, ++ 0xbe, 0x8f, 0x03, 0x1f, 0x0e, 0xd5, 0xc9, 0x27, 0x22, 0x48, 0xc8, 0x8f, ++ 0x17, 0xe0, 0x43, 0x98, 0xc7, 0x3d, 0x10, 0xec, 0x8c, 0x78, 0x49, 0xcd, ++ 0x05, 0x3e, 0x62, 0xeb, 0x7a, 0x0e, 0x89, 0xa8, 0x27, 0x22, 0xf1, 0x11, ++ 0xa5, 0x9b, 0x53, 0x80, 0xbf, 0x6e, 0xb8, 0x00, 0xb0, 0x75, 0xfb, 0xa7, ++ 0x74, 0xf3, 0x39, 0x3c, 0xa7, 0x7c, 0x76, 0xfa, 0xfb, 0xd0, 0xcb, 0x1a, ++ 0x4e, 0x1f, 0xd4, 0x0f, 0xf9, 0x1a, 0xe6, 0xeb, 0x1f, 0xcf, 0xe8, 0x67, ++ 0x76, 0x04, 0xff, 0xe2, 0x1f, 0xf1, 0xdd, 0x7e, 0xc0, 0x3f, 0xa0, 0x3f, ++ 0x99, 0xc1, 0xf4, 0x50, 0x66, 0xbc, 0x93, 0x8d, 0x23, 0x49, 0x32, 0xe8, ++ 0x17, 0x55, 0xcc, 0xc8, 0x04, 0xf9, 0x42, 0xe7, 0x35, 0x25, 0xd0, 0xf6, ++ 0xb7, 0xb8, 0x7f, 0x14, 0x69, 0xde, 0xa8, 0x84, 0x6e, 0xfe, 0x8b, 0x4a, ++ 0x80, 0xf3, 0xdc, 0xc2, 0xe6, 0x3d, 0x04, 0x46, 0xf6, 0xd0, 0x9e, 0xf3, ++ 0x8e, 0x4a, 0xa0, 0xf6, 0x47, 0x98, 0x79, 0xd2, 0xb8, 0x1c, 0xbf, 0x2e, ++ 0x82, 0xbf, 0x90, 0xc5, 0xfd, 0x12, 0x92, 0xdb, 0x6d, 0x9f, 0xa4, 0xc0, ++ 0x7a, 0x59, 0x9c, 0x6f, 0x76, 0x27, 0xab, 0x8e, 0x04, 0x1d, 0xdf, 0x14, ++ 0x71, 0xbb, 0xe5, 0x65, 0xc1, 0xa8, 0x97, 0x73, 0xba, 0xfd, 0x7d, 0xc6, ++ 0x3f, 0x49, 0x09, 0xac, 0x3f, 0x99, 0xd7, 0x3d, 0x6f, 0x56, 0x82, 0x0e, ++ 0x9e, 0x9a, 0x1d, 0x30, 0x9b, 0xcb, 0x07, 0x6d, 0x9e, 0xfe, 0x9c, 0xff, ++ 0x9c, 0x09, 0x0a, 0x1b, 0x5f, 0xc3, 0xc6, 0xc7, 0x43, 0x9d, 0x8e, 0xab, ++ 0xe0, 0xfe, 0x13, 0x85, 0x4b, 0x2e, 0xcc, 0x47, 0xac, 0xec, 0xf9, 0x85, ++ 0xfc, 0xa2, 0x7b, 0x14, 0x19, 0xc7, 0xcf, 0xe5, 0xfb, 0x12, 0xe2, 0x15, ++ 0x4d, 0xbf, 0x21, 0x5c, 0x47, 0x47, 0xf2, 0xbb, 0x82, 0x72, 0x70, 0x38, ++ 0xe2, 0xc1, 0xc5, 0xfa, 0x5f, 0xaa, 0x10, 0x0d, 0xef, 0x23, 0x71, 0x1f, ++ 0x95, 0x6c, 0x1f, 0x85, 0x0a, 0xc3, 0x7b, 0x68, 0xfc, 0x20, 0x12, 0x7e, ++ 0x34, 0xf8, 0x27, 0x6b, 0xe7, 0xcd, 0x61, 0xf3, 0x13, 0x4f, 0x37, 0xdc, ++ 0x46, 0xeb, 0xe9, 0x25, 0x12, 0xdc, 0xde, 0x8a, 0x63, 0xf6, 0xc5, 0x28, ++ 0x0e, 0x27, 0xd2, 0xc8, 0xe7, 0x09, 0x91, 0x07, 0x77, 0x4b, 0x1d, 0x56, ++ 0x25, 0xcc, 0x39, 0xaf, 0x8d, 0x77, 0x1a, 0xf8, 0xd9, 0xee, 0x32, 0xca, ++ 0x87, 0x48, 0xf1, 0x94, 0xbc, 0x20, 0x7c, 0x66, 0x22, 0x1c, 0xf2, 0xd9, ++ 0xbe, 0x23, 0xc5, 0x57, 0x0a, 0xf8, 0x79, 0x47, 0x70, 0xfb, 0x96, 0x8e, ++ 0x9b, 0x8f, 0x70, 0xb5, 0xb1, 0xfd, 0xde, 0xa3, 0x74, 0xb7, 0xd7, 0xe0, ++ 0x7c, 0xe9, 0x6c, 0xbe, 0xfa, 0x20, 0xbc, 0x17, 0x63, 0xbb, 0x83, 0xf5, ++ 0x8f, 0xe4, 0xf7, 0xd7, 0xf3, 0x7d, 0x55, 0x27, 0x74, 0x8f, 0x5b, 0x86, ++ 0xeb, 0x24, 0xb1, 0x71, 0xa1, 0xf1, 0x04, 0xad, 0x5c, 0xc2, 0xf7, 0xb7, ++ 0x30, 0x38, 0xee, 0x56, 0x5c, 0xaf, 0x1f, 0x1b, 0x97, 0x1c, 0xdc, 0xc7, ++ 0x1d, 0xd8, 0x3e, 0x9a, 0xb5, 0x7f, 0xdf, 0xf8, 0x5b, 0x32, 0xdf, 0xef, ++ 0x4f, 0x82, 0xeb, 0xae, 0xc1, 0xfd, 0xaa, 0xec, 0xfc, 0x81, 0xb8, 0x6e, ++ 0xb8, 0xac, 0xc7, 0xf6, 0x22, 0xb6, 0x6e, 0x24, 0xf9, 0x11, 0x88, 0x63, ++ 0xe7, 0x68, 0xe2, 0x70, 0xbe, 0x12, 0xfc, 0x62, 0x3a, 0x47, 0x7c, 0x80, ++ 0xe4, 0x48, 0x49, 0xe0, 0x35, 0x45, 0xbb, 0x46, 0xd1, 0x2e, 0xa9, 0x01, ++ 0xd5, 0x07, 0xfa, 0xa3, 0xe4, 0x4b, 0xd9, 0x09, 0x72, 0xba, 0x5c, 0xb4, ++ 0x79, 0x04, 0x2a, 0x8f, 0x25, 0xa7, 0x15, 0xfd, 0xe4, 0x28, 0x89, 0xa8, ++ 0xe0, 0xd7, 0xb6, 0x7f, 0xf5, 0x63, 0x47, 0x67, 0x2e, 0xd6, 0x7d, 0xa0, ++ 0xd7, 0x57, 0x47, 0x15, 0x5b, 0xc1, 0xef, 0x5c, 0x93, 0x25, 0xb9, 0x40, ++ 0x1f, 0x16, 0xdf, 0x27, 0x31, 0xff, 0xfa, 0x94, 0x09, 0xe5, 0x7d, 0x85, ++ 0xb8, 0x04, 0xe7, 0xd9, 0xa7, 0x68, 0x76, 0xee, 0x8d, 0x06, 0x3f, 0xda, ++ 0xa9, 0x38, 0x2b, 0xa3, 0x60, 0x1f, 0x56, 0x91, 0x38, 0x99, 0xff, 0x5f, ++ 0x39, 0x9e, 0x3e, 0xbf, 0x8a, 0xcb, 0xeb, 0x7d, 0xd6, 0x44, 0x13, 0xcc, ++ 0x37, 0x22, 0x83, 0xc5, 0x0b, 0xae, 0x72, 0x56, 0xa3, 0xbf, 0x4e, 0xbe, ++ 0x65, 0x7e, 0xb4, 0x4a, 0xff, 0x63, 0xf2, 0x5b, 0x45, 0xbd, 0x2c, 0xf3, ++ 0x71, 0x52, 0x7a, 0x3d, 0x11, 0xb0, 0x34, 0xfa, 0xdb, 0x32, 0xd9, 0x70, ++ 0x46, 0x1c, 0x84, 0x7a, 0x01, 0xed, 0xa8, 0x11, 0x7e, 0xa3, 0xff, 0x2d, ++ 0x3b, 0x2b, 0x4e, 0xc0, 0xfc, 0x32, 0xd1, 0x8d, 0xa3, 0xeb, 0x3e, 0x9f, ++ 0x60, 0x4f, 0x42, 0x7b, 0xaa, 0x1f, 0xe9, 0x7f, 0x8e, 0xf2, 0x8f, 0x25, ++ 0x47, 0x20, 0x16, 0xea, 0x5f, 0x94, 0x4b, 0xee, 0x3d, 0x80, 0x87, 0x31, ++ 0xce, 0x6a, 0xa5, 0x84, 0x9e, 0xc7, 0x92, 0xee, 0xb6, 0x82, 0x1c, 0xee, ++ 0x67, 0xf6, 0xf5, 0x86, 0x78, 0x42, 0x63, 0xba, 0xec, 0xf2, 0x00, 0x1b, ++ 0x3e, 0x50, 0x66, 0xcd, 0x02, 0x7f, 0xab, 0x99, 0xfa, 0xe7, 0x08, 0x07, ++ 0x35, 0xe1, 0xea, 0x81, 0x41, 0x3c, 0x59, 0x8a, 0x54, 0x02, 0x74, 0x48, ++ 0x71, 0x82, 0xfc, 0xd5, 0x5d, 0xda, 0x58, 0x99, 0x90, 0xc8, 0xf0, 0xf8, ++ 0x49, 0x82, 0x05, 0xcb, 0x12, 0x5e, 0xd7, 0x9e, 0x87, 0xe2, 0x7d, 0x48, ++ 0x62, 0x34, 0xe3, 0x7f, 0x62, 0xf5, 0x7c, 0x94, 0x03, 0x72, 0x42, 0x20, ++ 0x71, 0x94, 0x0e, 0x97, 0x92, 0xce, 0x4c, 0xa0, 0xc7, 0xe4, 0x34, 0x26, ++ 0x9f, 0x6a, 0x4d, 0x9d, 0x29, 0x50, 0xef, 0x22, 0xfe, 0x94, 0x24, 0x5a, ++ 0x36, 0x34, 0x4b, 0xa3, 0xc3, 0xf9, 0x3f, 0x1b, 0x79, 0xfc, 0x6c, 0xad, ++ 0x29, 0xbc, 0xbd, 0xf4, 0x4b, 0xf3, 0x98, 0x0f, 0x00, 0x0e, 0x12, 0xc4, ++ 0x0d, 0x2e, 0xc7, 0xb8, 0x80, 0xdb, 0xd2, 0x37, 0x18, 0x3f, 0xd0, 0xec, ++ 0x55, 0x2d, 0x8e, 0x10, 0xc9, 0x6e, 0xbd, 0x57, 0xac, 0xfa, 0x18, 0xe6, ++ 0x11, 0x14, 0xdf, 0x37, 0xd0, 0xbf, 0xa7, 0xfd, 0xeb, 0xc1, 0x7d, 0x48, ++ 0xe9, 0x4c, 0x4e, 0x6b, 0xa5, 0xb6, 0x8f, 0x99, 0x89, 0x8c, 0x7f, 0x1c, ++ 0x89, 0x56, 0x84, 0xcf, 0xde, 0x3b, 0x4a, 0xc9, 0x1c, 0x27, 0xe2, 0xe9, ++ 0x2c, 0xf0, 0x29, 0xc5, 0xd3, 0xa1, 0x2b, 0x00, 0x2a, 0x59, 0xf3, 0x14, ++ 0xc0, 0xd3, 0x2b, 0x59, 0x0f, 0xf5, 0x83, 0xb8, 0x94, 0x35, 0xeb, 0x81, ++ 0x24, 0xe0, 0xcf, 0xd1, 0x84, 0xd9, 0xa7, 0xe5, 0x74, 0x8c, 0x83, 0x96, ++ 0x0f, 0xd9, 0xdc, 0xdf, 0x24, 0xe8, 0xe4, 0xe1, 0x98, 0x7e, 0xb3, 0xd1, ++ 0x6e, 0x2a, 0xca, 0xac, 0x47, 0x7b, 0x6a, 0x75, 0x04, 0xbf, 0xf4, 0xc7, ++ 0x7c, 0x1f, 0x12, 0xa7, 0x93, 0x12, 0x9b, 0xdb, 0x94, 0x38, 0x14, 0xe2, ++ 0x5f, 0xcb, 0xac, 0x30, 0x5e, 0x52, 0xaa, 0xa2, 0xa1, 0xdc, 0x1b, 0x98, ++ 0x84, 0x25, 0xb5, 0x7b, 0xa5, 0x44, 0xda, 0x7f, 0x75, 0x3a, 0xab, 0x5f, ++ 0x08, 0x0f, 0xef, 0x72, 0xf9, 0x10, 0x69, 0xff, 0xa3, 0x40, 0x2f, 0x40, ++ 0xbc, 0x26, 0xbd, 0xfb, 0x1c, 0x09, 0x30, 0x3f, 0x7d, 0xee, 0x91, 0xf3, ++ 0x82, 0xe7, 0xd0, 0xed, 0x2f, 0x25, 0xdc, 0xfe, 0xcc, 0x89, 0x4c, 0x1f, ++ 0x69, 0xfb, 0x92, 0xfa, 0x71, 0xba, 0xcc, 0x31, 0xd2, 0xdd, 0x78, 0x4e, ++ 0x8f, 0x39, 0x89, 0x9a, 0xbf, 0x78, 0xd1, 0x74, 0x77, 0xe4, 0x62, 0xe8, ++ 0x2e, 0xf4, 0xbc, 0x63, 0xb2, 0x96, 0x8f, 0x1e, 0x40, 0x82, 0xfb, 0xd7, ++ 0xce, 0xab, 0x9d, 0x9f, 0x9e, 0xd7, 0x05, 0xe7, 0x2d, 0x97, 0xd8, 0xf9, ++ 0xb7, 0x2a, 0x6e, 0x15, 0xa6, 0xa0, 0x70, 0x1e, 0x0c, 0xed, 0x3d, 0xce, ++ 0x65, 0x0d, 0xaf, 0xf7, 0x33, 0x12, 0x4d, 0xdf, 0xf5, 0x3c, 0x0f, 0x25, ++ 0xf4, 0xbd, 0xf8, 0xf3, 0x7c, 0x87, 0x79, 0xa7, 0x26, 0x7e, 0x07, 0x38, ++ 0x1d, 0x18, 0xa9, 0x3a, 0x40, 0x9e, 0x34, 0x26, 0x53, 0xfa, 0xa4, 0x78, ++ 0x6a, 0x14, 0x58, 0xa9, 0xf5, 0x8f, 0xe6, 0x78, 0x6a, 0xe1, 0x74, 0xfa, ++ 0x5d, 0xe4, 0x44, 0xff, 0xef, 0x70, 0xbe, 0x62, 0x87, 0xf0, 0x12, 0xe8, ++ 0xc3, 0xab, 0xdc, 0xc7, 0x4a, 0x61, 0x99, 0xb2, 0xa2, 0xc1, 0xa0, 0x76, ++ 0x80, 0x1f, 0xe7, 0x01, 0xbd, 0x95, 0xe4, 0xde, 0x27, 0xcd, 0xa1, 0xf5, ++ 0xa6, 0x3b, 0xe6, 0xa2, 0xfc, 0x3c, 0x30, 0xb2, 0x1e, 0xf7, 0xbd, 0xda, ++ 0x6e, 0xdc, 0xaf, 0x56, 0x26, 0x70, 0x7c, 0x14, 0x65, 0xaa, 0xc8, 0x7f, ++ 0x8d, 0x9c, 0xff, 0xca, 0x09, 0xf3, 0x23, 0xb5, 0x7e, 0x6d, 0xfc, 0x5c, ++ 0xa1, 0xfc, 0x11, 0x3a, 0x5f, 0x28, 0x5f, 0x3f, 0x64, 0x53, 0x6f, 0x06, ++ 0xfa, 0x48, 0x48, 0x64, 0xfa, 0x32, 0xe8, 0xff, 0x75, 0x88, 0x7a, 0xff, ++ 0xaf, 0x84, 0xeb, 0xaf, 0x91, 0xd6, 0x9b, 0x0c, 0xf1, 0x8f, 0x91, 0xdc, ++ 0xff, 0x5b, 0xfd, 0x65, 0xb6, 0xcd, 0x43, 0x0f, 0x7a, 0x96, 0xea, 0xb5, ++ 0x7f, 0x89, 0xff, 0xf7, 0x0d, 0x7d, 0x02, 0x7e, 0x52, 0x7a, 0x89, 0x55, ++ 0xef, 0xff, 0x35, 0x5a, 0x4b, 0xb1, 0x7d, 0x75, 0x86, 0x3a, 0xfa, 0xf2, ++ 0x24, 0xd0, 0xc7, 0xa2, 0xeb, 0x2e, 0x82, 0xf0, 0x43, 0x7f, 0xd0, 0x23, ++ 0x88, 0xca, 0xd6, 0x30, 0xfe, 0xe0, 0xea, 0x0c, 0xd9, 0x77, 0x15, 0x7d, ++ 0x6e, 0x51, 0xc8, 0xe3, 0xb0, 0xbf, 0x52, 0xaa, 0x2f, 0x21, 0xfe, 0x62, ++ 0x51, 0x54, 0x72, 0xc9, 0xc0, 0x9e, 0x7e, 0xe1, 0x3e, 0x6b, 0x29, 0x81, ++ 0xb8, 0xc9, 0x59, 0x85, 0x3c, 0x0b, 0xfe, 0xd8, 0x85, 0xce, 0xf3, 0x78, ++ 0xa2, 0xd1, 0x2f, 0x94, 0xc0, 0x2f, 0xe4, 0xf3, 0xa3, 0x5f, 0xa8, 0xd4, ++ 0x93, 0x4e, 0x8c, 0xf7, 0x94, 0x12, 0xb0, 0x6b, 0xa0, 0xdd, 0x39, 0x10, ++ 0xe4, 0x8e, 0x4a, 0xdc, 0x76, 0xd0, 0x23, 0xd4, 0x2f, 0xd4, 0xc9, 0xa7, ++ 0xb3, 0xd6, 0x9b, 0x90, 0xdf, 0x43, 0xd7, 0xa3, 0x72, 0xeb, 0x69, 0xa0, ++ 0xa3, 0x46, 0x85, 0xf1, 0x71, 0xa8, 0x3f, 0x28, 0x72, 0x3e, 0xd7, 0xe4, ++ 0x6c, 0x28, 0x3d, 0x94, 0x3b, 0x18, 0xdd, 0x44, 0xd1, 0xad, 0x9b, 0x99, ++ 0xdc, 0x78, 0x2e, 0x31, 0xb9, 0x27, 0x5d, 0x7c, 0x77, 0xf9, 0x34, 0xaf, ++ 0x0c, 0x5c, 0x80, 0x6b, 0xc9, 0xca, 0x03, 0xe0, 0xaa, 0x4d, 0x09, 0xf8, ++ 0x25, 0x70, 0x79, 0x96, 0x27, 0x3a, 0xb1, 0x5f, 0x95, 0x6d, 0x47, 0x23, ++ 0x3c, 0xd7, 0xe6, 0x0f, 0xc5, 0x0f, 0x3d, 0xb9, 0x0a, 0xf1, 0x74, 0xb0, ++ 0x67, 0x58, 0xfc, 0x86, 0xda, 0x6b, 0xd4, 0x8e, 0x32, 0x53, 0x7b, 0x6d, ++ 0x9d, 0x10, 0x5c, 0x7f, 0x35, 0x87, 0x77, 0x24, 0x7c, 0xac, 0x06, 0x7d, ++ 0x1d, 0x86, 0x8f, 0xde, 0xee, 0x96, 0x6b, 0xa1, 0x71, 0xa2, 0x9b, 0x8c, ++ 0xf7, 0x2f, 0x8a, 0x87, 0x24, 0x15, 0xb0, 0xb8, 0x3e, 0x09, 0x03, 0x7f, ++ 0x91, 0xdb, 0x49, 0x6b, 0x28, 0xbf, 0xc0, 0xfd, 0xcd, 0x6a, 0xb3, 0xcb, ++ 0xa1, 0x00, 0x9d, 0x66, 0x14, 0xbd, 0xeb, 0x06, 0x7f, 0x3e, 0x43, 0xc6, ++ 0xfb, 0x08, 0x22, 0xd5, 0x3b, 0xae, 0xb6, 0xf7, 0x3c, 0xe7, 0x1a, 0x88, ++ 0x9f, 0x85, 0xd9, 0xdf, 0x17, 0x89, 0x09, 0x08, 0x57, 0x6b, 0xba, 0xc9, ++ 0x60, 0x9f, 0x11, 0x72, 0xa7, 0xc1, 0x7e, 0x8c, 0x74, 0x6e, 0xc2, 0xf7, ++ 0x65, 0xe6, 0xe7, 0x12, 0x00, 0x9e, 0x39, 0x7a, 0x78, 0x86, 0x9c, 0xbb, ++ 0x4c, 0xc1, 0x73, 0x83, 0x59, 0x0f, 0xf3, 0xc6, 0x9a, 0x5c, 0xc4, 0x47, ++ 0xf9, 0x22, 0x36, 0x93, 0xb8, 0x50, 0x60, 0xc5, 0x9a, 0x30, 0x0e, 0xab, ++ 0xf1, 0xb9, 0xc2, 0xf9, 0x5c, 0x93, 0x07, 0x36, 0x85, 0x8d, 0xab, 0x4c, ++ 0xea, 0xcb, 0xee, 0xf7, 0x44, 0x9b, 0x5f, 0xa4, 0xe7, 0x5f, 0x9f, 0x44, ++ 0xed, 0x69, 0x3a, 0x4f, 0x83, 0xba, 0x0f, 0xf5, 0xaa, 0x36, 0x3e, 0x8e, ++ 0x9f, 0xdf, 0x36, 0x92, 0xc5, 0x1b, 0x6d, 0x76, 0x9f, 0xa2, 0x84, 0x81, ++ 0xc3, 0xbd, 0x9c, 0xcf, 0x23, 0x9d, 0xb3, 0x59, 0x95, 0xe2, 0xcb, 0xe8, ++ 0xfe, 0xee, 0x55, 0x98, 0xfd, 0x2d, 0x8d, 0x34, 0x55, 0x79, 0x31, 0x1e, ++ 0xc5, 0xe2, 0xb5, 0x0a, 0x87, 0x9d, 0x58, 0x9c, 0x6f, 0x05, 0xbb, 0x7d, ++ 0x54, 0x52, 0x3c, 0x8b, 0x7b, 0xa9, 0x3b, 0x15, 0x7d, 0xdc, 0x4a, 0xe4, ++ 0xfb, 0x89, 0xb1, 0xd3, 0xfd, 0x9c, 0x47, 0x4e, 0xae, 0x0d, 0xd9, 0x4f, ++ 0x54, 0x4e, 0x67, 0x19, 0xec, 0x5f, 0xca, 0x52, 0x95, 0x78, 0xdd, 0xfe, ++ 0x4b, 0x92, 0x34, 0xbd, 0xd2, 0x81, 0xfc, 0x1d, 0x69, 0xbe, 0xbb, 0xb9, ++ 0x9c, 0x8f, 0xea, 0xe7, 0xc2, 0xf8, 0xad, 0xd5, 0xe6, 0xf2, 0xc1, 0xbd, ++ 0x56, 0x94, 0x5a, 0x5d, 0x00, 0x62, 0x31, 0x3a, 0xc7, 0x45, 0xe6, 0xea, ++ 0xda, 0xa3, 0xd5, 0x82, 0x21, 0x16, 0x1d, 0x1d, 0x36, 0x67, 0xc8, 0x61, ++ 0xef, 0x23, 0x6e, 0xe7, 0xeb, 0xdb, 0x25, 0xb5, 0x0a, 0xc6, 0xd9, 0x15, ++ 0x89, 0xc0, 0x3d, 0x99, 0x9d, 0xdb, 0xcb, 0x91, 0xe6, 0x8d, 0xb4, 0x8f, ++ 0x0b, 0xad, 0x37, 0x2d, 0x89, 0xe9, 0xd3, 0x1e, 0xeb, 0x39, 0xc3, 0xdb, ++ 0x15, 0x7d, 0x92, 0x18, 0xff, 0x49, 0x23, 0x77, 0x56, 0x81, 0x9c, 0x26, ++ 0x03, 0x25, 0xd2, 0x3f, 0x8c, 0x9e, 0x48, 0x48, 0x62, 0xf2, 0x25, 0x56, ++ 0xee, 0x74, 0x82, 0xbf, 0x4e, 0xe9, 0xd1, 0x1d, 0x6e, 0x3e, 0x92, 0x24, ++ 0x73, 0x7e, 0xfe, 0x37, 0xf1, 0x87, 0x66, 0x77, 0x17, 0xb7, 0x1e, 0xca, ++ 0xa6, 0xfb, 0x6d, 0xb0, 0x49, 0x2e, 0x01, 0xe4, 0x57, 0xe1, 0xc9, 0x0e, ++ 0xa7, 0x0e, 0x3e, 0x54, 0xaf, 0xcf, 0x4a, 0xd2, 0xc9, 0x7d, 0xd1, 0xe6, ++ 0x46, 0xf9, 0x26, 0x3a, 0xd9, 0xbd, 0xfb, 0x68, 0x0b, 0xf3, 0xb7, 0x0f, ++ 0x8c, 0x34, 0xde, 0x93, 0xcd, 0xe7, 0xf8, 0xfa, 0x80, 0xc3, 0x31, 0x92, ++ 0x5c, 0x28, 0xe2, 0xf0, 0xf8, 0x77, 0x9d, 0xf3, 0xbb, 0xe2, 0xaf, 0x24, ++ 0x89, 0xc9, 0x7d, 0x0d, 0x2e, 0xcd, 0x00, 0x17, 0x02, 0xfc, 0x75, 0x7f, ++ 0x63, 0x43, 0x18, 0x79, 0x49, 0xe1, 0xd3, 0x90, 0x94, 0xfc, 0xdd, 0xe1, ++ 0xb3, 0x96, 0xc3, 0xe5, 0xe9, 0x0b, 0xc0, 0x67, 0xd0, 0x7f, 0x18, 0x3e, ++ 0x17, 0xe2, 0xeb, 0x20, 0x9f, 0x79, 0xc9, 0xf1, 0x30, 0x70, 0x6c, 0xb0, ++ 0xcb, 0x69, 0x73, 0x0d, 0xfc, 0xdf, 0x8c, 0x76, 0x48, 0xb8, 0x7e, 0xd5, ++ 0xba, 0xf3, 0x46, 0xe2, 0x43, 0x8d, 0x3e, 0x20, 0x77, 0x03, 0xe1, 0xd0, ++ 0xac, 0x1a, 0xe2, 0x02, 0x72, 0x92, 0xa7, 0x83, 0xf9, 0x95, 0x37, 0x1b, ++ 0xf5, 0x9c, 0xb8, 0xc4, 0xc5, 0xe5, 0x33, 0xf9, 0x96, 0xc2, 0x2d, 0x9e, ++ 0xf7, 0x8f, 0xb7, 0x11, 0x5f, 0x4c, 0x6c, 0x70, 0x7e, 0xb9, 0xcc, 0x18, ++ 0x4f, 0x68, 0x4b, 0xe2, 0x71, 0x81, 0x28, 0x12, 0x05, 0xf0, 0x39, 0xeb, ++ 0x9a, 0x24, 0x40, 0x9e, 0x82, 0xc5, 0x34, 0x63, 0xb0, 0x92, 0x0d, 0x4b, ++ 0x34, 0x0b, 0xa0, 0x27, 0x52, 0x60, 0x9e, 0x41, 0x84, 0xdc, 0xc7, 0xe5, ++ 0x67, 0xa8, 0x1e, 0x4c, 0x56, 0x99, 0x9f, 0xdc, 0x9b, 0xd4, 0x0b, 0x4c, ++ 0xaf, 0xa4, 0xe3, 0xfe, 0x92, 0xf8, 0x3e, 0x42, 0xf5, 0x60, 0x1a, 0xf5, ++ 0x6b, 0x20, 0x1e, 0x03, 0x47, 0x04, 0x7f, 0xba, 0x37, 0xad, 0x5b, 0xc1, ++ 0x06, 0x21, 0x2a, 0xde, 0x83, 0x0b, 0x1e, 0x13, 0xfa, 0xcb, 0x0e, 0xe2, ++ 0x15, 0x60, 0xfe, 0x74, 0xd2, 0x89, 0x65, 0x1f, 0x48, 0x45, 0xa0, 0xf3, ++ 0x67, 0x91, 0x0e, 0xa1, 0x1f, 0xc5, 0xdf, 0x7d, 0xe5, 0xd5, 0x83, 0x41, ++ 0x7e, 0xbf, 0x13, 0x72, 0x8e, 0x0b, 0xd9, 0xa3, 0x5a, 0xa9, 0xd9, 0x1f, ++ 0x6b, 0xff, 0x43, 0xf0, 0xfe, 0xf4, 0x7f, 0x2f, 0xbc, 0x57, 0x96, 0xea, ++ 0xe0, 0x2d, 0x26, 0x7f, 0x3f, 0x78, 0xcf, 0xe7, 0x72, 0x27, 0x34, 0x9e, ++ 0x57, 0x04, 0xf1, 0xbc, 0x2c, 0x88, 0xe7, 0xf9, 0xf6, 0x03, 0x9f, 0xca, ++ 0xdf, 0x32, 0xfb, 0xa3, 0xfd, 0xef, 0x32, 0xc6, 0xf7, 0x1a, 0xb3, 0x58, ++ 0x3c, 0xaf, 0x5c, 0xac, 0x7c, 0x18, 0xef, 0x41, 0x9d, 0x32, 0xba, 0x1f, ++ 0x52, 0x4e, 0xe7, 0x7a, 0xc8, 0x73, 0xd2, 0xec, 0x4e, 0xd4, 0x79, 0x7d, ++ 0x83, 0x71, 0x3f, 0xeb, 0x99, 0xfb, 0x25, 0x88, 0xa3, 0x10, 0xe9, 0x24, ++ 0xc2, 0x09, 0xef, 0x86, 0x9c, 0x28, 0xcf, 0x32, 0x93, 0x51, 0xde, 0x30, ++ 0x3b, 0xe2, 0x2a, 0xbe, 0x7f, 0x39, 0x6b, 0x9e, 0x15, 0xee, 0xbd, 0x83, ++ 0xfe, 0x93, 0x4f, 0x64, 0xf6, 0x06, 0xb3, 0x97, 0x64, 0x4e, 0x07, 0x45, ++ 0x8e, 0x12, 0xf4, 0x5f, 0x1a, 0xbf, 0x3d, 0xbf, 0xdd, 0x71, 0xb1, 0x7e, ++ 0xd2, 0x5e, 0xe9, 0x00, 0xde, 0x5f, 0x6b, 0xfe, 0x51, 0x83, 0x7f, 0x0e, ++ 0xfa, 0x4b, 0xa1, 0xe3, 0x7c, 0x92, 0xef, 0x7d, 0x38, 0xbf, 0xcf, 0x2f, ++ 0x3b, 0x21, 0xdf, 0xa4, 0x8d, 0xdf, 0x8b, 0xb5, 0x9d, 0x39, 0x68, 0x88, ++ 0xd3, 0x86, 0xfa, 0x41, 0x9a, 0x5d, 0x75, 0x15, 0xdf, 0x7f, 0xa9, 0xdf, ++ 0x7d, 0xe8, 0x72, 0xb8, 0xdf, 0x52, 0xe6, 0x10, 0x16, 0xdf, 0x64, 0x70, ++ 0x90, 0xf9, 0x3a, 0x8d, 0x8e, 0xb3, 0x78, 0x0f, 0xfe, 0xe2, 0xb7, 0x26, ++ 0xf4, 0xb7, 0xce, 0x72, 0x7f, 0xab, 0x08, 0xfc, 0x2c, 0x3b, 0xf3, 0x77, ++ 0xaa, 0xed, 0x3d, 0xcf, 0x39, 0x21, 0x39, 0xbc, 0xff, 0x04, 0xe3, 0x20, ++ 0xaf, 0xae, 0x54, 0xf1, 0x89, 0x60, 0xcf, 0x69, 0xfe, 0x13, 0xb4, 0x3b, ++ 0xed, 0x3d, 0xfd, 0xa7, 0xd1, 0x16, 0xff, 0x6b, 0xb0, 0xbf, 0x09, 0xaf, ++ 0x89, 0x98, 0x17, 0x12, 0x09, 0xbe, 0xa1, 0x7e, 0x53, 0xa8, 0xfe, 0x99, ++ 0x9e, 0xcc, 0xf4, 0xce, 0x4d, 0xc9, 0xdc, 0xae, 0x0b, 0x81, 0xa7, 0x16, ++ 0xef, 0x0b, 0xbd, 0x97, 0x6e, 0xd2, 0xf8, 0x4f, 0xf2, 0x08, 0x7a, 0xfe, ++ 0x0f, 0x5d, 0x5f, 0xde, 0x37, 0x06, 0xf7, 0x4f, 0x14, 0x5d, 0x3c, 0x36, ++ 0x3b, 0x18, 0x4f, 0x14, 0x54, 0x0f, 0xb9, 0x25, 0x2f, 0x18, 0x3f, 0x0c, ++ 0x13, 0x37, 0x5c, 0x0a, 0x74, 0xa8, 0xc5, 0x0d, 0x35, 0x3d, 0xa6, 0xd1, ++ 0xb1, 0x85, 0xf6, 0xb5, 0xe2, 0x3d, 0x73, 0xf8, 0x78, 0x62, 0x5b, 0xd6, ++ 0xc1, 0xbe, 0xcc, 0x2f, 0x7c, 0x29, 0x11, 0xf8, 0xb3, 0x5c, 0x61, 0x71, ++ 0x23, 0x6d, 0x7f, 0xd4, 0x2f, 0xbc, 0x2d, 0x59, 0x87, 0x8f, 0x22, 0x3f, ++ 0xd3, 0xdb, 0x96, 0xff, 0x53, 0xdf, 0xb9, 0x92, 0xc2, 0x97, 0x24, 0x10, ++ 0x17, 0xf3, 0x0f, 0xea, 0x9d, 0x56, 0x5a, 0xaf, 0x50, 0x48, 0xe2, 0x3a, ++ 0xe4, 0x33, 0x1b, 0xe6, 0x69, 0x15, 0x25, 0x09, 0xc8, 0x77, 0x92, 0x2f, ++ 0x0a, 0xeb, 0x15, 0xa7, 0x5c, 0xde, 0x28, 0x5a, 0xb7, 0xec, 0x7b, 0x45, ++ 0x14, 0x93, 0x60, 0xbd, 0x39, 0x24, 0x4a, 0x08, 0xd2, 0x8f, 0x96, 0xd7, ++ 0xd1, 0xe8, 0xff, 0x70, 0x3d, 0xe0, 0xef, 0xec, 0x29, 0xc9, 0x75, 0x3e, ++ 0xbf, 0xbb, 0x02, 0x82, 0x68, 0x06, 0x3f, 0x29, 0x3a, 0x88, 0x4f, 0x94, ++ 0x6f, 0x09, 0x86, 0xfa, 0x43, 0x92, 0xfb, 0xa1, 0x64, 0xb4, 0x17, 0x7b, ++ 0x05, 0xc7, 0x89, 0x90, 0x0f, 0x96, 0x6d, 0xc8, 0x3f, 0x7b, 0x46, 0x52, ++ 0x7f, 0x0a, 0x70, 0x9d, 0x6a, 0x55, 0x1f, 0xc6, 0xfe, 0x3f, 0x3c, 0xbc, ++ 0x6f, 0x4f, 0xc6, 0x78, 0xf1, 0xc1, 0x7f, 0x0a, 0xef, 0xc1, 0x75, 0x98, ++ 0x3e, 0x00, 0x9b, 0x8d, 0xa4, 0xe9, 0xd6, 0xb3, 0xd1, 0xc6, 0x61, 0xb0, ++ 0x8e, 0x93, 0xdd, 0x17, 0x6a, 0x71, 0xe9, 0xe5, 0x04, 0xef, 0x63, 0xb6, ++ 0x01, 0xce, 0x20, 0xce, 0xf2, 0x39, 0xf1, 0x42, 0x9c, 0xe5, 0x05, 0xf3, ++ 0xcb, 0x22, 0xe8, 0xa3, 0x26, 0x3e, 0xcf, 0x70, 0xd2, 0xec, 0x94, 0xfb, ++ 0xb2, 0xfd, 0x42, 0xbf, 0x27, 0xb7, 0x3a, 0x36, 0x01, 0x5d, 0xfc, 0x2e, ++ 0x39, 0x0b, 0xd7, 0x7f, 0xc1, 0xe6, 0xde, 0x30, 0x98, 0xb6, 0x1f, 0xda, ++ 0x22, 0x0d, 0x86, 0xb8, 0x4d, 0x83, 0xf3, 0x19, 0x2b, 0xe4, 0xcf, 0xee, ++ 0xdb, 0xda, 0x94, 0xde, 0xa9, 0xe3, 0xbf, 0x43, 0x4f, 0xba, 0xfb, 0x84, ++ 0xf3, 0x0f, 0xb5, 0x92, 0xfe, 0xc5, 0x99, 0x0a, 0xf1, 0x5c, 0xb1, 0xac, ++ 0x54, 0x45, 0x93, 0x03, 0xdb, 0x45, 0xa8, 0xf7, 0xb0, 0xcf, 0xb6, 0xb4, ++ 0x2a, 0xb0, 0xce, 0x93, 0x5b, 0xad, 0xd3, 0xc2, 0xc5, 0x35, 0xc4, 0x14, ++ 0xc6, 0xef, 0xc3, 0xb7, 0x30, 0xbb, 0x76, 0x74, 0x8e, 0xc9, 0x05, 0xe2, ++ 0xad, 0x88, 0x78, 0xa4, 0x04, 0xb8, 0x8f, 0x71, 0x11, 0x97, 0x8f, 0x36, ++ 0xc4, 0x0c, 0xdc, 0xd9, 0x81, 0x36, 0x70, 0x96, 0x88, 0xf7, 0x1a, 0xb4, ++ 0xbe, 0x3f, 0x96, 0xd6, 0x63, 0x86, 0xaa, 0xe8, 0x1f, 0x0c, 0x18, 0xb8, ++ 0x13, 0xc7, 0x0f, 0xf8, 0xbc, 0xc4, 0xc5, 0xf2, 0x28, 0x3d, 0xb6, 0x3c, ++ 0x5a, 0x5f, 0x9f, 0x53, 0x32, 0x74, 0x1d, 0xad, 0xa7, 0x47, 0xbb, 0x3f, ++ 0x06, 0xfa, 0xa2, 0x7a, 0xa6, 0x59, 0x42, 0x7d, 0xda, 0x12, 0x03, 0x79, ++ 0x00, 0x31, 0x03, 0x27, 0x25, 0xaf, 0xa3, 0xb5, 0x18, 0x81, 0x54, 0x85, ++ 0xb3, 0x73, 0xff, 0x9a, 0xcc, 0xec, 0xef, 0x27, 0xcd, 0x1a, 0x5c, 0x25, ++ 0xcc, 0x83, 0xdc, 0xb7, 0x55, 0x46, 0xfe, 0x3a, 0x94, 0x26, 0xe2, 0xfd, ++ 0x13, 0x85, 0xdb, 0x12, 0xa8, 0xff, 0x25, 0x2d, 0x86, 0x50, 0x4a, 0x24, ++ 0x65, 0xaa, 0xa7, 0x0c, 0xe0, 0x58, 0x4e, 0x5a, 0x1a, 0xc0, 0x9f, 0x2a, ++ 0x73, 0x5e, 0xfd, 0x52, 0x2c, 0xf9, 0x27, 0xe0, 0x97, 0xbf, 0x53, 0x01, ++ 0xfe, 0x5f, 0x1f, 0xc1, 0x0e, 0xff, 0x1d, 0xdf, 0x1f, 0x0a, 0x11, 0x4a, ++ 0x3f, 0x07, 0xb7, 0x34, 0x5e, 0x47, 0xc2, 0xe4, 0x51, 0x6b, 0x74, 0xf8, ++ 0x5c, 0x8c, 0x2a, 0xa5, 0xd0, 0xfe, 0x6b, 0xf9, 0xbd, 0x2e, 0x71, 0x4c, ++ 0x42, 0xfa, 0x89, 0x8c, 0xef, 0xbb, 0x98, 0xbf, 0xd9, 0xe2, 0x6b, 0x88, ++ 0xa6, 0x70, 0x1c, 0xbe, 0xbd, 0xb9, 0x97, 0x7e, 0xfe, 0x23, 0x10, 0x74, ++ 0x4d, 0xee, 0x89, 0x6f, 0xc8, 0x7f, 0x26, 0x97, 0x43, 0xfe, 0xad, 0x1b, ++ 0xf3, 0x69, 0x1b, 0x4e, 0x9a, 0x10, 0x7e, 0xaf, 0xe6, 0x0a, 0x5e, 0x81, ++ 0xc2, 0xe7, 0x60, 0x8e, 0x48, 0x6d, 0x36, 0xba, 0xab, 0x7e, 0x56, 0x6f, ++ 0x7f, 0x5a, 0xdf, 0xc0, 0xe9, 0xb8, 0x72, 0xfb, 0xe1, 0xc6, 0x5e, 0xc0, ++ 0xc2, 0x29, 0x49, 0xb8, 0xee, 0xab, 0x39, 0x8f, 0x59, 0x59, 0x7e, 0xeb, ++ 0xc5, 0xc7, 0xaf, 0x87, 0x50, 0x3e, 0x58, 0x04, 0xf9, 0x53, 0x14, 0x1f, ++ 0xa3, 0x94, 0x68, 0xaf, 0x93, 0xe2, 0x6b, 0x31, 0x4c, 0x41, 0xeb, 0x23, ++ 0x15, 0xab, 0xd7, 0x47, 0xd7, 0x6b, 0xb7, 0x77, 0x94, 0xc6, 0xd1, 0x25, ++ 0x5e, 0x48, 0x16, 0x5c, 0x9b, 0x81, 0x5e, 0x72, 0x88, 0x02, 0xf2, 0x03, ++ 0x5d, 0x10, 0x13, 0x43, 0x94, 0x42, 0xeb, 0x20, 0x32, 0x90, 0x9e, 0x92, ++ 0x08, 0xe6, 0x73, 0xad, 0x2f, 0xc8, 0xdd, 0x0c, 0x71, 0xb1, 0x75, 0xe9, ++ 0xce, 0x16, 0xc8, 0x37, 0xdc, 0x33, 0xd0, 0x8a, 0xf9, 0x66, 0xa1, 0xf9, ++ 0xc4, 0x7b, 0x84, 0xfa, 0x97, 0xe2, 0x21, 0x2e, 0x15, 0x2f, 0xa0, 0xbc, ++ 0x3e, 0x98, 0xf3, 0x3b, 0xbc, 0xa7, 0x3b, 0x98, 0x6e, 0x21, 0x40, 0xaf, ++ 0x98, 0xf0, 0x4b, 0x9f, 0x37, 0x26, 0x30, 0x3e, 0x8d, 0xc9, 0x37, 0xda, ++ 0x9f, 0xe5, 0x29, 0x59, 0xdc, 0xcf, 0x26, 0x1e, 0x4b, 0x41, 0x70, 0x5f, ++ 0x31, 0xfd, 0xac, 0x6a, 0x14, 0x25, 0xa4, 0x97, 0xe3, 0xd9, 0xf8, 0x43, ++ 0xfd, 0x04, 0x2f, 0xd0, 0xdb, 0x21, 0x27, 0x97, 0x0f, 0xf4, 0xbc, 0x5b, ++ 0xc1, 0x20, 0x92, 0x9a, 0xa5, 0xa9, 0x03, 0x23, 0xe3, 0xf5, 0x95, 0xfe, ++ 0xa3, 0x9c, 0x9a, 0x5d, 0x2c, 0x68, 0xe7, 0x34, 0xf5, 0x3c, 0xc7, 0x0b, ++ 0x82, 0x77, 0x4d, 0x36, 0x9c, 0x63, 0x00, 0x3d, 0x07, 0xad, 0xdb, 0x73, ++ 0x04, 0x5c, 0xdf, 0xae, 0xac, 0xbb, 0x91, 0x60, 0x59, 0xb8, 0x00, 0xee, ++ 0x31, 0x43, 0xf7, 0xbf, 0x22, 0x85, 0xf9, 0x47, 0x32, 0x25, 0xbb, 0x1c, ++ 0x90, 0x6f, 0x2d, 0x6b, 0xc6, 0xe8, 0xf3, 0x63, 0xe4, 0xc2, 0x1b, 0x27, ++ 0xd8, 0x62, 0x31, 0x8f, 0x09, 0xed, 0xca, 0xd4, 0x1c, 0x01, 0xcf, 0x33, ++ 0xe6, 0x24, 0xbb, 0xcf, 0xed, 0x91, 0x9f, 0xad, 0x10, 0xb7, 0x6c, 0xc0, ++ 0x0f, 0xb5, 0x3a, 0x52, 0x82, 0xf3, 0xc5, 0x7c, 0xf9, 0xec, 0x4f, 0x20, ++ 0xff, 0x77, 0x5c, 0xa1, 0xe0, 0x8b, 0x82, 0xfd, 0xf0, 0xfc, 0x66, 0xfa, ++ 0x7f, 0xed, 0xa0, 0x5f, 0xe4, 0x7e, 0xb3, 0x59, 0xfe, 0x75, 0xce, 0x26, ++ 0x3c, 0xcf, 0xd8, 0x42, 0xb3, 0x0b, 0xee, 0x72, 0xc6, 0xda, 0xbc, 0xcd, ++ 0x25, 0xb4, 0xfe, 0xca, 0x27, 0x12, 0xc6, 0xb3, 0xc7, 0xf5, 0x1b, 0x85, ++ 0xf9, 0xd5, 0xa1, 0xeb, 0xaf, 0x53, 0x88, 0x6f, 0x34, 0x85, 0xef, 0x2b, ++ 0xb9, 0x12, 0xc2, 0x3b, 0xea, 0x92, 0xc7, 0x70, 0x9e, 0x37, 0x73, 0x4d, ++ 0x28, 0x6f, 0xc6, 0x41, 0x3e, 0x36, 0xe4, 0x2f, 0xeb, 0xf3, 0xaa, 0x51, ++ 0x1f, 0x1a, 0xf3, 0xb9, 0xc7, 0x89, 0x1f, 0xa8, 0xc5, 0xd0, 0xec, 0x62, ++ 0xfc, 0x4a, 0x24, 0x4f, 0x2f, 0x90, 0xef, 0x13, 0x1c, 0x46, 0xf8, 0xd9, ++ 0x4f, 0x1a, 0xef, 0x8b, 0x2b, 0xf3, 0x2d, 0x86, 0xfa, 0xb8, 0x5c, 0x39, ++ 0x44, 0x0f, 0x7b, 0x10, 0xde, 0x2f, 0x67, 0x30, 0xba, 0x78, 0x79, 0x80, ++ 0xe0, 0xdd, 0x9c, 0x15, 0xa4, 0xb3, 0xb1, 0x27, 0x13, 0xbc, 0x40, 0x67, ++ 0xf0, 0x27, 0x16, 0x18, 0xe0, 0x68, 0x38, 0x67, 0x8c, 0x5f, 0x56, 0x01, ++ 0x7e, 0x87, 0x06, 0x3c, 0xf1, 0x5f, 0x70, 0x4f, 0x12, 0xe3, 0x5c, 0x7d, ++ 0x23, 0xde, 0x83, 0x73, 0xf8, 0x6b, 0x74, 0x12, 0xc3, 0xf1, 0x6e, 0x4f, ++ 0x7f, 0xee, 0x27, 0xa0, 0xa7, 0x34, 0xf8, 0x87, 0xd2, 0xc1, 0xc5, 0xe3, ++ 0xff, 0xea, 0xaa, 0x62, 0xc0, 0x7f, 0xbe, 0x76, 0x7f, 0x1f, 0x82, 0xff, ++ 0x10, 0x7c, 0x63, 0x0c, 0x52, 0x3b, 0x47, 0xdf, 0x9e, 0x78, 0xc7, 0xf5, ++ 0xb3, 0x7a, 0xe2, 0x5b, 0xa3, 0x83, 0x1e, 0xe7, 0xbe, 0xbb, 0x75, 0x4d, ++ 0x36, 0xc5, 0xeb, 0xab, 0x76, 0xfa, 0x00, 0xf0, 0xbc, 0x49, 0xf6, 0xde, ++ 0x25, 0x04, 0xf1, 0x74, 0x41, 0xbc, 0xf6, 0x2b, 0x46, 0xba, 0x59, 0xa7, ++ 0x34, 0xdb, 0x40, 0xee, 0x47, 0x5d, 0x72, 0xdc, 0x06, 0xfe, 0x81, 0x46, ++ 0x17, 0x44, 0x6c, 0xcb, 0xd7, 0xdb, 0xfb, 0xff, 0x2a, 0x7c, 0x97, 0x6c, ++ 0x10, 0x98, 0x33, 0xe9, 0x12, 0xbc, 0x10, 0xd7, 0x7b, 0x0b, 0x1e, 0x0d, ++ 0x0b, 0xae, 0xf3, 0x52, 0x4a, 0x77, 0xbe, 0xcc, 0x4b, 0x20, 0xf7, 0x49, ++ 0x15, 0xcb, 0xe3, 0x68, 0x50, 0xf3, 0xd8, 0x7b, 0x57, 0xf9, 0x4c, 0x9f, ++ 0x86, 0xca, 0x87, 0x3f, 0xa4, 0xb0, 0xf7, 0x3a, 0xda, 0xcd, 0x2f, 0xa7, ++ 0x9f, 0x2f, 0x4f, 0xb5, 0xd2, 0xe6, 0x26, 0x70, 0x3f, 0xd6, 0x00, 0xf9, ++ 0x76, 0xf4, 0x7c, 0xf2, 0x86, 0xd9, 0xf0, 0x46, 0x03, 0x91, 0x27, 0xcf, ++ 0x46, 0x79, 0x49, 0x36, 0x08, 0x2c, 0x0f, 0xa1, 0xe8, 0xf7, 0x28, 0xdf, ++ 0xe7, 0x39, 0xbc, 0xab, 0x84, 0x30, 0xeb, 0xa1, 0x25, 0x83, 0xfb, 0x74, ++ 0x32, 0xbb, 0xbf, 0x28, 0x11, 0xfb, 0x93, 0x69, 0x5a, 0x5e, 0x52, 0xd5, ++ 0x07, 0xb8, 0xff, 0xc9, 0xac, 0x7e, 0xb1, 0xfb, 0x7a, 0xe3, 0x5f, 0xb4, ++ 0xaf, 0xa3, 0x94, 0x56, 0x88, 0xce, 0xff, 0x9c, 0xc8, 0xe3, 0xf2, 0x9a, ++ 0xdd, 0x3d, 0xc1, 0xc6, 0xf2, 0x0e, 0x27, 0x14, 0x89, 0x88, 0x8f, 0x37, ++ 0xb7, 0x08, 0x5e, 0xcc, 0x8f, 0xa4, 0xfd, 0x3c, 0x94, 0x4e, 0x16, 0x71, ++ 0xb2, 0x9d, 0xc8, 0xed, 0xc0, 0xb3, 0x85, 0xcf, 0x34, 0x0d, 0x76, 0x82, ++ 0x3d, 0xa8, 0x1a, 0xec, 0x4e, 0xa1, 0xa8, 0x1d, 0xed, 0xbe, 0xb8, 0x42, ++ 0xa3, 0x3f, 0x18, 0xaf, 0x46, 0x1b, 0xf0, 0x9f, 0x38, 0x3a, 0xc1, 0x50, ++ 0x4f, 0xae, 0xea, 0x65, 0xe8, 0x9f, 0x3a, 0x2d, 0xdb, 0x18, 0x57, 0x70, ++ 0x5f, 0x6a, 0x78, 0xde, 0xbb, 0x26, 0xcf, 0x50, 0xcf, 0xa8, 0x1f, 0x6e, ++ 0xe8, 0xdf, 0xe7, 0x96, 0x12, 0x43, 0x3d, 0xcb, 0x33, 0xd6, 0xd0, 0xbf, ++ 0xef, 0x9a, 0x49, 0x86, 0x7a, 0xff, 0xe6, 0xeb, 0x0c, 0xfd, 0x7f, 0xf4, ++ 0xf0, 0x1c, 0xc3, 0xf3, 0x01, 0xde, 0x45, 0x86, 0xe7, 0x97, 0x6d, 0x5b, ++ 0x66, 0xa8, 0x0f, 0x6c, 0xb9, 0xcd, 0xd0, 0xff, 0xf2, 0x5d, 0x77, 0x19, ++ 0x9e, 0x0f, 0xf6, 0xad, 0x33, 0x3c, 0x1f, 0x72, 0xe8, 0x7e, 0x43, 0x7d, ++ 0x68, 0xc7, 0xcf, 0x0d, 0xfd, 0xaf, 0x78, 0x77, 0xb3, 0xe1, 0xf9, 0xb0, ++ 0xce, 0x5f, 0x19, 0x9e, 0x8f, 0x38, 0xb9, 0xd3, 0x50, 0x1f, 0xe9, 0xdf, ++ 0x6d, 0xe8, 0x7f, 0x55, 0x60, 0x9f, 0xa1, 0x5e, 0x4c, 0x5e, 0x33, 0xf4, ++ 0x2f, 0xb5, 0xfe, 0xde, 0x50, 0x2f, 0x57, 0xde, 0x37, 0xf4, 0x1f, 0xe5, ++ 0x38, 0x6e, 0x78, 0x3e, 0xc6, 0xf9, 0x99, 0xe1, 0xb9, 0x46, 0x07, 0xe3, ++ 0x72, 0xbe, 0x30, 0xb4, 0x8f, 0x77, 0xfd, 0x2d, 0xe4, 0x3d, 0x9d, 0x2a, ++ 0x16, 0xe7, 0x80, 0x78, 0x40, 0x5f, 0x78, 0xd4, 0x8c, 0x65, 0x34, 0x69, ++ 0x61, 0xf7, 0x3a, 0xa4, 0x03, 0xcb, 0x85, 0x05, 0xee, 0xe2, 0x54, 0xe0, ++ 0x8f, 0x47, 0x3d, 0x4d, 0x90, 0x90, 0xd4, 0xe0, 0xf1, 0xff, 0x11, 0xae, ++ 0xa6, 0xdf, 0x2c, 0xec, 0x1b, 0xc7, 0xec, 0x27, 0x95, 0xe8, 0xe5, 0xa7, ++ 0x96, 0x9f, 0x4a, 0xfd, 0x16, 0x4f, 0x14, 0x25, 0x85, 0xd8, 0x00, 0xa5, ++ 0xdb, 0x21, 0x94, 0xee, 0x02, 0x02, 0x96, 0x4a, 0x80, 0x4a, 0xd6, 0x44, ++ 0x88, 0xf7, 0x44, 0x61, 0x99, 0x10, 0x48, 0xc4, 0xf6, 0xc4, 0x40, 0x3c, ++ 0x96, 0x49, 0x81, 0xde, 0xd8, 0x9e, 0x1c, 0x48, 0xc3, 0x32, 0x25, 0xd0, ++ 0x17, 0xcb, 0xd4, 0x40, 0x16, 0x96, 0x8e, 0xc0, 0x65, 0x58, 0xa6, 0x05, ++ 0x06, 0x60, 0xd9, 0x2b, 0x30, 0x04, 0xc7, 0xf5, 0x0e, 0x0c, 0xc6, 0x32, ++ 0x3d, 0x30, 0x02, 0xdb, 0x33, 0x02, 0xc3, 0xb0, 0xcc, 0x0c, 0x94, 0x62, ++ 0x7b, 0x9f, 0x40, 0x31, 0x96, 0xce, 0xc0, 0x38, 0x2c, 0xb3, 0x02, 0x63, ++ 0xb0, 0xcc, 0x0e, 0x5c, 0x83, 0xfd, 0xfa, 0x06, 0xae, 0xc6, 0xb2, 0x5f, ++ 0xe0, 0x7a, 0x6c, 0xef, 0x1f, 0x98, 0x8e, 0xe5, 0x25, 0x81, 0xb9, 0x58, ++ 0xfe, 0x28, 0x30, 0x1b, 0xcb, 0x9c, 0xc0, 0x62, 0x2c, 0x07, 0x04, 0x16, ++ 0x62, 0x79, 0x69, 0xe0, 0x26, 0x1c, 0x77, 0x59, 0xe0, 0x46, 0x2c, 0x73, ++ 0x03, 0xb7, 0x63, 0xfb, 0xc0, 0xc0, 0xad, 0x58, 0x0e, 0x0a, 0x34, 0x60, ++ 0x79, 0x79, 0x60, 0x25, 0x96, 0xae, 0xc0, 0x7a, 0xec, 0x37, 0x38, 0xb0, ++ 0x16, 0xcb, 0xbc, 0xc0, 0x7f, 0x61, 0xfb, 0x90, 0xc0, 0x7d, 0x58, 0xe6, ++ 0x07, 0x7e, 0x81, 0xed, 0x43, 0x03, 0x3f, 0xc3, 0xb2, 0x20, 0xf0, 0x18, ++ 0x96, 0x57, 0x04, 0x36, 0x61, 0x59, 0x18, 0xf8, 0x35, 0x96, 0xc3, 0x02, ++ 0x4f, 0x62, 0x39, 0x3c, 0xf0, 0x0c, 0x8e, 0x1b, 0x11, 0xd8, 0x81, 0x65, ++ 0x51, 0xe0, 0x05, 0x6c, 0x1f, 0x19, 0x78, 0x1e, 0xcb, 0x2b, 0x03, 0xfb, ++ 0xb1, 0xfd, 0xaa, 0x40, 0x3b, 0x96, 0x6a, 0xe0, 0x35, 0x6c, 0x2f, 0x0e, ++ 0xbc, 0x82, 0x65, 0x49, 0xe0, 0xf7, 0xd8, 0x5e, 0x1a, 0x38, 0x8c, 0x65, ++ 0x59, 0xe0, 0x7d, 0x6c, 0x2f, 0x0f, 0xbc, 0x87, 0x65, 0x45, 0xe0, 0x38, ++ 0x96, 0xa3, 0x02, 0xc7, 0xb0, 0x1c, 0x1d, 0xf8, 0x0c, 0xcb, 0x31, 0x81, ++ 0x4f, 0xb0, 0x1c, 0x1b, 0xf8, 0x02, 0xc7, 0x8d, 0x0b, 0x9c, 0xc1, 0xb2, ++ 0x32, 0xf0, 0x37, 0x6c, 0x1f, 0x1f, 0xf8, 0x06, 0xcb, 0x6e, 0x79, 0x17, ++ 0x31, 0x5f, 0xd9, 0x6d, 0x42, 0x7f, 0x96, 0xfb, 0xa9, 0x91, 0xfd, 0x05, ++ 0x0f, 0xca, 0x49, 0x33, 0x7f, 0x2f, 0x0e, 0x72, 0xab, 0x31, 0xff, 0xbf, ++ 0x5e, 0xf0, 0x62, 0xbc, 0x30, 0xa9, 0xf3, 0x25, 0xa8, 0x9b, 0x0b, 0x2d, ++ 0x18, 0x2f, 0xbc, 0x81, 0xf8, 0xf1, 0x3d, 0x81, 0xff, 0x26, 0x9d, 0x76, ++ 0x90, 0xa7, 0xed, 0xc3, 0x4e, 0xa4, 0x43, 0xbc, 0xe9, 0xcd, 0x64, 0x5f, ++ 0x86, 0x3e, 0xdf, 0xc1, 0xcc, 0xe3, 0x00, 0xe5, 0xe2, 0x29, 0x09, 0xfc, ++ 0xd5, 0x09, 0x49, 0xfb, 0x92, 0x41, 0x9f, 0xde, 0x40, 0x9b, 0x21, 0xcf, ++ 0x88, 0xa8, 0xe7, 0x30, 0x0f, 0x72, 0x02, 0xcf, 0x83, 0xbc, 0x41, 0xa2, ++ 0x0e, 0x16, 0xdd, 0xea, 0x61, 0x98, 0x61, 0x18, 0xf6, 0xf3, 0x59, 0x68, ++ 0x7d, 0x46, 0x25, 0x51, 0xf3, 0x68, 0xff, 0xa6, 0x61, 0x16, 0x8c, 0xeb, ++ 0x37, 0xe5, 0x51, 0x3f, 0x88, 0x96, 0x77, 0x67, 0xb1, 0x7c, 0xd9, 0x1d, ++ 0xa9, 0x4c, 0x5f, 0xfe, 0x8a, 0x97, 0xbb, 0x52, 0x99, 0x1d, 0xeb, 0x29, ++ 0x60, 0xf7, 0xfb, 0x33, 0x6e, 0xec, 0xcf, 0xf8, 0xa9, 0x2c, 0xf1, 0x02, ++ 0x7e, 0x13, 0x83, 0xc3, 0xdf, 0x07, 0xf2, 0x3c, 0x5b, 0x9b, 0x3f, 0x13, ++ 0xf3, 0x63, 0x2f, 0x72, 0xdc, 0x67, 0x29, 0x7c, 0x1c, 0xef, 0xdf, 0x9c, ++ 0x5a, 0xd5, 0x96, 0x0a, 0xfb, 0x28, 0x21, 0x39, 0xf5, 0xb6, 0x60, 0x3f, ++ 0xda, 0xfe, 0x62, 0x84, 0xf6, 0x7d, 0xe1, 0xda, 0xf7, 0x99, 0x18, 0x3e, ++ 0x3c, 0x47, 0x44, 0xee, 0x27, 0x54, 0xc5, 0x4d, 0x3a, 0x8f, 0x9f, 0xf0, ++ 0xe6, 0x8a, 0x8e, 0x4b, 0x5f, 0xea, 0x1f, 0xac, 0xbf, 0x15, 0xc1, 0x0f, ++ 0x25, 0x64, 0x25, 0xee, 0x37, 0x76, 0xdf, 0x27, 0x95, 0xd7, 0x52, 0x7d, ++ 0x38, 0xb1, 0x50, 0x74, 0x51, 0xc9, 0x41, 0x3e, 0x58, 0xb1, 0x6b, 0xe4, ++ 0x47, 0xfd, 0xd9, 0xba, 0x90, 0x9f, 0xe9, 0x29, 0x11, 0x31, 0x7e, 0x31, ++ 0xa3, 0xe8, 0xf0, 0x81, 0x44, 0x5a, 0x9f, 0xb1, 0x3c, 0x1e, 0xf3, 0xee, ++ 0xbb, 0xf7, 0x55, 0x62, 0xc6, 0xe7, 0x13, 0x1c, 0x47, 0x2e, 0x7d, 0x89, ++ 0x1e, 0xfd, 0x86, 0xfa, 0xe7, 0x47, 0x7e, 0x64, 0x88, 0x8b, 0xba, 0xd1, ++ 0xee, 0xba, 0x89, 0xd3, 0x28, 0x51, 0xcd, 0x7f, 0xed, 0xd4, 0x9e, 0x23, ++ 0xbd, 0xb2, 0xb8, 0xef, 0x4d, 0xb0, 0xb8, 0x13, 0xe4, 0x9f, 0x19, 0xe7, ++ 0xed, 0x50, 0xcd, 0xde, 0xf3, 0xe5, 0xc7, 0x10, 0xd5, 0x42, 0x54, 0x03, ++ 0xdd, 0x33, 0x78, 0xad, 0x87, 0xfd, 0x83, 0xef, 0x4f, 0xac, 0x26, 0x58, ++ 0x37, 0x96, 0xf7, 0xa1, 0x70, 0x45, 0xbd, 0xef, 0x89, 0x95, 0xbd, 0x0d, ++ 0x02, 0x38, 0xef, 0xce, 0x38, 0xa0, 0xbb, 0x98, 0x5c, 0x3f, 0x39, 0x5f, ++ 0x7c, 0x19, 0xe0, 0x29, 0x61, 0xa2, 0x42, 0xa7, 0x0d, 0xec, 0x98, 0x48, ++ 0xf0, 0x4c, 0x70, 0x30, 0xfa, 0x8b, 0x2b, 0x52, 0x1d, 0x1e, 0x8a, 0x9f, ++ 0xc6, 0xbf, 0x8b, 0x78, 0xcf, 0xb5, 0x3f, 0xbe, 0x40, 0x01, 0xfa, 0xbf, ++ 0xc7, 0xd6, 0x2f, 0x15, 0xf8, 0x23, 0xd9, 0xc1, 0xe2, 0x27, 0x8d, 0xed, ++ 0xef, 0x61, 0x7c, 0x2b, 0x2e, 0xdf, 0x4f, 0x3c, 0x36, 0x76, 0x7f, 0xee, ++ 0xb4, 0x40, 0x1c, 0xdf, 0x8a, 0xe5, 0xaa, 0x15, 0x2e, 0x2c, 0x1b, 0x57, ++ 0x14, 0x62, 0xb9, 0x2e, 0xfd, 0x7e, 0x2b, 0xc4, 0x4b, 0xc4, 0x64, 0x09, ++ 0x32, 0x81, 0x49, 0x54, 0xc6, 0x3c, 0x8c, 0x07, 0x69, 0xeb, 0x9b, 0xe3, ++ 0xe7, 0x58, 0x8b, 0x5d, 0x94, 0x6c, 0x1d, 0x72, 0x25, 0x84, 0x90, 0x44, ++ 0x88, 0x33, 0x0c, 0x87, 0xf7, 0x36, 0xe5, 0xca, 0x95, 0xfd, 0x08, 0xf9, ++ 0x26, 0x95, 0xe5, 0x7d, 0xbf, 0xe9, 0xf8, 0xc8, 0x06, 0xfc, 0xf0, 0x4d, ++ 0xaa, 0x13, 0xeb, 0xa2, 0x89, 0xdd, 0x1b, 0xc7, 0xe4, 0xfb, 0x54, 0xc8, ++ 0x4b, 0x88, 0x71, 0x29, 0x25, 0x92, 0x33, 0xd8, 0x8e, 0x7f, 0x49, 0xd8, ++ 0xbe, 0x19, 0xfc, 0x91, 0x37, 0x49, 0xe7, 0x86, 0x6b, 0x00, 0x8e, 0x2a, ++ 0x7b, 0x1f, 0xa3, 0x81, 0xbf, 0x6f, 0xda, 0x50, 0xdc, 0x9f, 0xc3, 0x55, ++ 0x1b, 0x17, 0x82, 0xf7, 0x10, 0x3c, 0x8b, 0xb2, 0x0b, 0xef, 0xad, 0xc5, ++ 0x68, 0xda, 0x3f, 0x37, 0x32, 0x5e, 0x07, 0x38, 0xe2, 0x71, 0x9f, 0x40, ++ 0x5f, 0x12, 0xa5, 0x2f, 0x3f, 0xdf, 0x37, 0x51, 0x63, 0x4c, 0x30, 0x9f, ++ 0x86, 0xdf, 0xb3, 0x92, 0x1f, 0xf3, 0xa9, 0x1a, 0x84, 0xf0, 0x79, 0x97, ++ 0x43, 0x38, 0x7e, 0x1a, 0x15, 0x55, 0x39, 0xdf, 0x3d, 0x0a, 0x51, 0xa4, ++ 0xbf, 0xea, 0xe5, 0xa9, 0x2d, 0x77, 0x57, 0x08, 0x3d, 0xdb, 0x50, 0xbe, ++ 0x62, 0x1d, 0xf2, 0xb9, 0xb8, 0xbc, 0xda, 0x9f, 0xaa, 0x0e, 0x73, 0xd0, ++ 0xf9, 0xc7, 0x5c, 0xc9, 0xf3, 0xeb, 0xd3, 0x13, 0x50, 0x0e, 0xd0, 0xf6, ++ 0x01, 0xc3, 0x21, 0x9f, 0xce, 0x44, 0x15, 0x3a, 0xc0, 0x2d, 0x41, 0x46, ++ 0x7e, 0xa1, 0x40, 0x88, 0x83, 0x3c, 0x5f, 0x62, 0x75, 0xc6, 0x4d, 0x3a, ++ 0x4f, 0x1e, 0xc4, 0xda, 0x15, 0x0e, 0x55, 0x32, 0xc3, 0xfd, 0x80, 0x33, ++ 0x0e, 0xe0, 0xb5, 0x96, 0x9f, 0x0f, 0xde, 0x50, 0xd6, 0xcb, 0x81, 0x7f, ++ 0x57, 0xbf, 0xa0, 0xbc, 0xf0, 0x22, 0xdd, 0x86, 0xf6, 0x6f, 0xd1, 0xe4, ++ 0x40, 0x82, 0x15, 0xe5, 0x93, 0xc8, 0xe1, 0xa1, 0x8d, 0x5b, 0xe8, 0x60, ++ 0xf2, 0xd8, 0x94, 0x5d, 0x35, 0xd3, 0x31, 0x94, 0x8d, 0x03, 0x3e, 0xa2, ++ 0x75, 0x37, 0xc0, 0x8b, 0x58, 0x69, 0x7d, 0x20, 0xd6, 0xe7, 0xe0, 0x73, ++ 0xa5, 0xbb, 0x3e, 0x0f, 0xeb, 0x0e, 0xd6, 0x1f, 0x13, 0x69, 0x2e, 0x42, ++ 0x0e, 0xd3, 0x71, 0x8b, 0x71, 0x9c, 0xd4, 0x3d, 0xcf, 0x52, 0xac, 0xdb, ++ 0xba, 0xd7, 0xad, 0xc3, 0x75, 0x93, 0xba, 0xeb, 0x37, 0x62, 0x3d, 0x9d, ++ 0xf5, 0xbf, 0xd8, 0x75, 0xb4, 0xb2, 0xfb, 0xfc, 0xbf, 0x63, 0x72, 0xf2, ++ 0x4b, 0x49, 0x8d, 0x4b, 0xa0, 0xf4, 0x3c, 0xf6, 0x96, 0xb9, 0x55, 0xa0, ++ 0x0a, 0xc6, 0xdf, 0xb2, 0xb0, 0xaa, 0x8c, 0xea, 0xef, 0x3f, 0xae, 0x78, ++ 0x57, 0x05, 0xb9, 0xf4, 0x01, 0x95, 0x27, 0x8d, 0xb4, 0x1c, 0x3b, 0x60, ++ 0x7f, 0x22, 0xf8, 0x39, 0xe3, 0x87, 0xee, 0x8f, 0x71, 0xea, 0xe8, 0xf5, ++ 0x06, 0x1e, 0xd7, 0x6c, 0xbb, 0xc5, 0x3c, 0x1a, 0xf4, 0x5d, 0xd1, 0xad, ++ 0x62, 0xd5, 0x16, 0x84, 0xf7, 0x4a, 0xc3, 0xbd, 0xcf, 0x1a, 0x87, 0x99, ++ 0xc7, 0x9b, 0xd8, 0x3e, 0x66, 0x48, 0x84, 0xdc, 0x91, 0x00, 0xf2, 0xf7, ++ 0xf0, 0xa5, 0x8d, 0x06, 0xbf, 0x93, 0xf3, 0xa1, 0xc2, 0xda, 0xba, 0xf7, ++ 0x7b, 0x9b, 0x80, 0xfb, 0xfd, 0xa0, 0x9e, 0xc9, 0xdb, 0x0f, 0x96, 0x0b, ++ 0x28, 0x6f, 0xbb, 0xf9, 0x34, 0x9e, 0x70, 0x3f, 0xde, 0x97, 0x0c, 0x70, ++ 0x9a, 0xb9, 0x5c, 0x27, 0xb7, 0x49, 0x18, 0xb8, 0xd4, 0x5b, 0x88, 0xdb, ++ 0x20, 0xd7, 0x23, 0xc1, 0x87, 0x90, 0xbf, 0xd2, 0xfa, 0x97, 0xb6, 0x7e, ++ 0x18, 0x97, 0xa5, 0x96, 0x9a, 0xb5, 0x2a, 0x8c, 0x3e, 0xd3, 0xe0, 0x14, ++ 0x09, 0x0f, 0x37, 0x44, 0x88, 0xff, 0x6a, 0x70, 0xd2, 0xe0, 0xad, 0xb5, ++ 0xff, 0xe9, 0x8e, 0x21, 0x0a, 0xb3, 0xab, 0xbd, 0x06, 0x38, 0xce, 0xba, ++ 0x73, 0x28, 0xc6, 0x2b, 0x6f, 0xe0, 0xf1, 0x7a, 0x12, 0x6f, 0xe5, 0xfc, ++ 0xc9, 0xfa, 0xcd, 0xa0, 0xeb, 0xec, 0xcc, 0x45, 0x7a, 0x72, 0x02, 0xbd, ++ 0x43, 0x3d, 0x6c, 0x9e, 0x0d, 0x5f, 0x77, 0x06, 0xfd, 0xd7, 0x1d, 0x79, ++ 0x17, 0x85, 0x07, 0xcc, 0x97, 0xff, 0xa0, 0xfe, 0x80, 0xdd, 0xad, 0xbb, ++ 0xff, 0x0c, 0x85, 0x7b, 0x44, 0x3a, 0x8c, 0x00, 0xef, 0x3a, 0x0b, 0xc1, ++ 0xf7, 0x2a, 0xfc, 0x5b, 0xed, 0x2c, 0x9e, 0x94, 0x34, 0x0d, 0xe7, 0xad, ++ 0xe1, 0xeb, 0x92, 0xa4, 0x19, 0xb8, 0x8f, 0x1a, 0xbe, 0xce, 0x4b, 0x7b, ++ 0x63, 0x7c, 0x26, 0xb8, 0x87, 0xda, 0x6a, 0xdf, 0x0c, 0xfe, 0x70, 0x57, ++ 0x89, 0x27, 0x65, 0x22, 0xe0, 0x6b, 0xb3, 0x19, 0xf3, 0xda, 0xee, 0xda, ++ 0xbb, 0xfe, 0xc8, 0x2f, 0xe0, 0x3e, 0x78, 0x93, 0x19, 0xef, 0x4e, 0x16, ++ 0x7e, 0xf1, 0x40, 0x01, 0xdc, 0xcb, 0x76, 0x71, 0x3d, 0x46, 0x15, 0x41, ++ 0x3b, 0x7c, 0x47, 0xc1, 0x4d, 0xb4, 0x3f, 0x55, 0x80, 0xf9, 0x17, 0x10, ++ 0x36, 0x7f, 0x97, 0x76, 0x0f, 0xb2, 0x35, 0x0e, 0xe1, 0x7a, 0xb2, 0x6c, ++ 0x4b, 0xd3, 0x08, 0x5a, 0x76, 0xee, 0x59, 0x5a, 0x09, 0xf1, 0x97, 0x13, ++ 0x7b, 0xc7, 0x1f, 0x04, 0xff, 0x79, 0x61, 0x34, 0x91, 0xd2, 0xc0, 0xde, ++ 0xab, 0xdf, 0x21, 0x23, 0x3c, 0x3c, 0xe6, 0x8f, 0x8c, 0x76, 0x82, 0x14, ++ 0xac, 0x8b, 0x3d, 0xeb, 0x0b, 0xa0, 0xae, 0x8b, 0x23, 0x2d, 0xf4, 0x9a, ++ 0x83, 0x75, 0xfa, 0xbf, 0xc5, 0xdb, 0x8c, 0x75, 0x3d, 0xbc, 0x4c, 0x7a, ++ 0x78, 0x39, 0xcb, 0x8c, 0xf0, 0x72, 0x96, 0x1b, 0xe0, 0x25, 0xbc, 0x68, ++ 0xf7, 0x89, 0x3a, 0x78, 0x95, 0x9d, 0x79, 0x29, 0x11, 0xf4, 0xfb, 0x51, ++ 0x87, 0x13, 0xe7, 0xab, 0x39, 0xd3, 0x98, 0x02, 0xf0, 0xa9, 0xd9, 0xb3, ++ 0x16, 0xcb, 0xc5, 0xdb, 0xa2, 0x3c, 0x1f, 0xe9, 0xd6, 0x5d, 0xda, 0x12, ++ 0x6f, 0xa8, 0xd7, 0xed, 0x4a, 0xf3, 0xe8, 0xf5, 0xcb, 0xd9, 0x43, 0x8f, ++ 0xc5, 0xc2, 0xf9, 0x97, 0x39, 0x44, 0xcf, 0x47, 0x54, 0x7e, 0x9c, 0x5a, ++ 0xa1, 0x36, 0x00, 0x1d, 0x9f, 0x5e, 0x31, 0xba, 0x41, 0x4f, 0xcf, 0x4b, ++ 0x5b, 0xb2, 0x3c, 0x36, 0xc3, 0x3c, 0xc6, 0xfa, 0xd9, 0x66, 0x01, 0xed, ++ 0x14, 0xd0, 0x33, 0x93, 0xcf, 0x63, 0x2f, 0x2e, 0x73, 0xc8, 0xb8, 0xce, ++ 0xa7, 0xdb, 0x98, 0xdf, 0xf9, 0xe9, 0x0a, 0xab, 0x07, 0xd6, 0x39, 0xb5, ++ 0x42, 0xf1, 0xb0, 0x75, 0x1d, 0x1e, 0x66, 0x4f, 0x31, 0x78, 0x2d, 0xb9, ++ 0x25, 0xc6, 0xf3, 0xd1, 0x90, 0xe0, 0xfe, 0x22, 0xcd, 0xfb, 0xaf, 0xde, ++ 0x1f, 0x21, 0xad, 0xe4, 0xb8, 0x95, 0xe0, 0xbb, 0x3b, 0xe7, 0xce, 0xa3, ++ 0xbf, 0x23, 0xf2, 0x8b, 0xf4, 0xa5, 0x8c, 0xf2, 0xbd, 0xcd, 0xfc, 0x17, ++ 0xa0, 0x1b, 0x2b, 0xfd, 0xdf, 0x39, 0x8c, 0xa7, 0x4a, 0x58, 0xd7, 0xe6, ++ 0xad, 0x6b, 0x11, 0x3d, 0x90, 0x57, 0x4c, 0xc8, 0x76, 0xc3, 0x7a, 0x74, ++ 0x9c, 0xf3, 0x63, 0x9d, 0x5d, 0x10, 0x59, 0x3f, 0x18, 0xbf, 0x37, 0x31, ++ 0x02, 0x62, 0x62, 0x28, 0xa7, 0xd9, 0x7d, 0x88, 0x1b, 0xee, 0x43, 0xe8, ++ 0x7c, 0x5d, 0x92, 0x6d, 0x0d, 0xc4, 0x13, 0xb4, 0xfb, 0x90, 0x3a, 0x58, ++ 0x88, 0xf6, 0x5d, 0x6a, 0xed, 0x94, 0xdd, 0xb4, 0xe9, 0xf3, 0xd6, 0xbe, ++ 0xe7, 0x7d, 0xdf, 0x9c, 0xe2, 0x29, 0x0b, 0xf4, 0x73, 0x8d, 0xb5, 0x59, ++ 0x06, 0xa5, 0x5b, 0xd3, 0x32, 0xa0, 0x0c, 0xf8, 0xe9, 0xf3, 0xd6, 0x86, ++ 0x14, 0xb0, 0x67, 0x17, 0x8b, 0x67, 0x7f, 0x1c, 0xee, 0xbd, 0xaf, 0x29, ++ 0x69, 0x9c, 0x6f, 0xbd, 0x66, 0xbf, 0xd1, 0x6f, 0xf4, 0x6a, 0xfb, 0xcc, ++ 0x92, 0x0c, 0x7c, 0x46, 0x6c, 0xdd, 0xe7, 0xa6, 0xf5, 0x53, 0x11, 0xde, ++ 0xf3, 0x99, 0xc5, 0xe7, 0xad, 0xdd, 0x7e, 0xb8, 0x62, 0x04, 0xdd, 0x7f, ++ 0xed, 0xae, 0x33, 0x32, 0xec, 0x23, 0x39, 0xcd, 0x3d, 0x2b, 0x2d, 0x39, ++ 0x78, 0x7e, 0x81, 0xdf, 0x07, 0x2d, 0xda, 0x76, 0x0c, 0xf9, 0xfc, 0xa4, ++ 0xd9, 0x73, 0xc9, 0xed, 0xe7, 0xb3, 0xf3, 0x7b, 0xec, 0xd3, 0xe6, 0x30, ++ 0xe4, 0x1f, 0x7a, 0x48, 0x07, 0xf0, 0xe7, 0x9c, 0x42, 0xa2, 0x31, 0xec, ++ 0xb5, 0xef, 0x53, 0x79, 0xf3, 0xc9, 0x6b, 0x66, 0x02, 0xf7, 0x88, 0xe4, ++ 0x5b, 0xda, 0x8b, 0x3e, 0xcf, 0xe4, 0x4f, 0xe7, 0x91, 0xaa, 0x58, 0x80, ++ 0xd7, 0x9c, 0xd6, 0xc5, 0x28, 0x7f, 0x3e, 0x79, 0x76, 0xdc, 0x41, 0x96, ++ 0x87, 0xd4, 0x5c, 0x00, 0xf4, 0xf1, 0x39, 0x31, 0xe1, 0xfb, 0xee, 0x9f, ++ 0x93, 0xdf, 0xc5, 0x0e, 0xd1, 0xc1, 0x6f, 0x5d, 0x9a, 0x96, 0x47, 0xc9, ++ 0xbe, 0x73, 0xa3, 0xe5, 0xb9, 0xd0, 0x0d, 0xa6, 0x61, 0x9e, 0x7a, 0x4d, ++ 0x53, 0x07, 0xbc, 0x3f, 0x66, 0x21, 0x92, 0x87, 0xcb, 0x25, 0x81, 0x7d, ++ 0xb7, 0xc6, 0x2b, 0xa0, 0xfd, 0x52, 0xc3, 0xda, 0x3d, 0xc4, 0xba, 0x12, ++ 0xcf, 0xb1, 0x86, 0xc9, 0x23, 0x0f, 0xfd, 0x0f, 0xea, 0xf3, 0x9b, 0x8d, ++ 0xf2, 0x69, 0xc1, 0xc3, 0xc6, 0x7a, 0x35, 0x99, 0x94, 0x02, 0x79, 0xde, ++ 0xd5, 0x0f, 0x98, 0x21, 0x93, 0x88, 0x2c, 0xd4, 0xcb, 0x3f, 0x0a, 0xbf, ++ 0x1b, 0xd3, 0x98, 0xff, 0xb9, 0x80, 0xd4, 0x37, 0x81, 0x5d, 0xf7, 0x88, ++ 0xcc, 0xf2, 0xbb, 0xe7, 0x28, 0x44, 0xea, 0x4d, 0xf5, 0xd1, 0xd2, 0xe7, ++ 0x1e, 0x29, 0x98, 0x4d, 0xeb, 0xf7, 0xa5, 0x31, 0x7b, 0xec, 0x53, 0xee, ++ 0x6f, 0xc0, 0x7b, 0x8c, 0x69, 0xf4, 0xf9, 0xa2, 0x5b, 0xbc, 0xb2, 0x9a, ++ 0xdb, 0xf3, 0x7c, 0xc7, 0x5b, 0x87, 0x4c, 0x1d, 0x41, 0x70, 0x3e, 0xe6, ++ 0x3f, 0x2d, 0xd2, 0xec, 0x57, 0xe2, 0x84, 0x78, 0x7e, 0x6f, 0xf8, 0x57, ++ 0x76, 0xe4, 0xf3, 0xf7, 0x6e, 0x15, 0xf1, 0xfe, 0xa9, 0x37, 0xb4, 0xeb, ++ 0xe4, 0xf3, 0xdc, 0x35, 0xc6, 0xf3, 0x5d, 0xe8, 0xfc, 0xa1, 0xe7, 0x25, ++ 0xe4, 0x7e, 0x3c, 0xc7, 0xa2, 0x6d, 0x57, 0xa3, 0xff, 0xa6, 0x9d, 0x47, ++ 0xc3, 0x97, 0x76, 0x1e, 0xf3, 0xb6, 0xf0, 0xef, 0xfb, 0x6e, 0x4b, 0x13, ++ 0x0c, 0x76, 0xdc, 0x2e, 0x0e, 0x3f, 0xcd, 0xff, 0xde, 0x13, 0x52, 0xdf, ++ 0x97, 0xc6, 0xec, 0x7a, 0xad, 0xfe, 0x72, 0x48, 0x5d, 0xa3, 0x6f, 0x33, ++ 0xe7, 0x6f, 0x4a, 0xf7, 0x7b, 0x80, 0xee, 0x97, 0x5a, 0xfd, 0x15, 0x8c, ++ 0x4e, 0x3a, 0x65, 0xfd, 0xbd, 0xa8, 0x1c, 0xec, 0xb7, 0x2f, 0x6d, 0x68, ++ 0xe4, 0x7e, 0x16, 0xce, 0x2f, 0xb4, 0xdf, 0xcb, 0xe7, 0xeb, 0x17, 0x15, ++ 0x9c, 0xef, 0xf5, 0x70, 0xeb, 0x2e, 0x7d, 0xee, 0xa9, 0x67, 0xc1, 0x2f, ++ 0x5d, 0xf4, 0x9b, 0x07, 0x63, 0xe1, 0x52, 0xe8, 0x13, 0xa9, 0x39, 0x05, ++ 0xde, 0xb7, 0x58, 0xb2, 0x75, 0x55, 0x2c, 0xc0, 0xe9, 0xa4, 0xe4, 0x89, ++ 0x05, 0xba, 0xf9, 0xc4, 0x2b, 0x8e, 0x0e, 0x07, 0x2f, 0x53, 0x2f, 0x0d, ++ 0x5e, 0xaa, 0x4d, 0xa0, 0x78, 0xaf, 0xd5, 0xe8, 0xbf, 0x68, 0xe5, 0x04, ++ 0xd0, 0xef, 0x7f, 0xd9, 0x6a, 0x56, 0xc0, 0x3f, 0xac, 0xdb, 0x66, 0xf1, ++ 0xc1, 0x77, 0x98, 0x6a, 0x5b, 0x17, 0xe2, 0xbd, 0x0d, 0xad, 0x1f, 0x63, ++ 0xf5, 0xd5, 0xf8, 0x7e, 0x65, 0xdd, 0x2e, 0xf3, 0x87, 0x7a, 0xbc, 0x2e, ++ 0x7a, 0xe2, 0xc1, 0x14, 0xcc, 0xf3, 0x20, 0x9e, 0xde, 0xec, 0x5e, 0xdd, ++ 0xd7, 0x1b, 0x3e, 0x21, 0x54, 0xbb, 0xe5, 0xcf, 0x15, 0xe0, 0x2f, 0xd7, ++ 0x11, 0x3f, 0xd2, 0x73, 0xe8, 0x38, 0x58, 0x3f, 0x90, 0x80, 0xf2, 0x7a, ++ 0xb6, 0x1c, 0xd7, 0xf3, 0xb9, 0x16, 0x3f, 0xad, 0x63, 0x4d, 0xa4, 0xae, ++ 0x75, 0xfd, 0x19, 0x88, 0x9f, 0xd6, 0xb5, 0x8e, 0x39, 0x01, 0x7c, 0x5f, ++ 0x47, 0xa4, 0x0f, 0xf5, 0xf4, 0x54, 0x03, 0x34, 0x4d, 0xfd, 0x96, 0x2f, ++ 0xd2, 0x78, 0xfe, 0xdd, 0x15, 0xe4, 0x0a, 0x90, 0x2f, 0x1a, 0x3c, 0x88, ++ 0x37, 0x19, 0xe5, 0x73, 0xc3, 0x93, 0x3f, 0x1d, 0x74, 0x8c, 0xee, 0xe7, ++ 0xd4, 0x96, 0xd7, 0x62, 0x05, 0xbd, 0xdf, 0xca, 0xef, 0xdd, 0xcf, 0xb6, ++ 0xcc, 0xfd, 0x53, 0xe2, 0x79, 0xf4, 0xc3, 0x69, 0x4a, 0xa7, 0xfa, 0xf7, ++ 0x32, 0x34, 0xb9, 0xeb, 0xdc, 0x45, 0x37, 0x90, 0x4a, 0xab, 0x6d, 0xac, ++ 0x5c, 0x62, 0xf6, 0xc5, 0x8e, 0xa0, 0x70, 0x5d, 0xb2, 0xc9, 0x8c, 0xef, ++ 0x89, 0x2e, 0x79, 0xea, 0xb1, 0xc7, 0x7f, 0x0e, 0xf9, 0x44, 0xef, 0x59, ++ 0xf0, 0x1e, 0x64, 0xf1, 0x53, 0x07, 0x8e, 0x0c, 0xa7, 0xf5, 0xc5, 0x3b, ++ 0xcc, 0x49, 0x95, 0xec, 0x18, 0x36, 0xb8, 0x17, 0xd6, 0xf0, 0x52, 0x47, ++ 0xff, 0x07, 0xf7, 0x14, 0x1a, 0x1e, 0x16, 0x3d, 0x73, 0x40, 0x86, 0xf7, ++ 0x68, 0xa0, 0x1d, 0xfc, 0x04, 0x0d, 0x1f, 0x8b, 0x77, 0xb4, 0xcb, 0x64, ++ 0x60, 0x4f, 0xf8, 0x95, 0xb6, 0xb4, 0xcb, 0x9d, 0xb6, 0x30, 0x78, 0x69, ++ 0x39, 0x56, 0x81, 0xef, 0x1b, 0x3d, 0xf9, 0xb5, 0x0c, 0x78, 0xff, 0x64, ++ 0xaf, 0x40, 0x52, 0xb3, 0x7a, 0x8e, 0xaf, 0xd9, 0x74, 0x00, 0xed, 0x18, ++ 0x80, 0x13, 0xe2, 0x91, 0xe3, 0xa9, 0x1b, 0x6f, 0x3d, 0xf0, 0xe5, 0x9b, ++ 0xb0, 0x3b, 0x1f, 0xfb, 0x29, 0x20, 0xb7, 0x2f, 0x84, 0xaf, 0x77, 0xb8, ++ 0x5e, 0xa5, 0x74, 0xfd, 0xf4, 0x6e, 0xba, 0x8f, 0x9a, 0x3f, 0x58, 0x5c, ++ 0x00, 0x87, 0x9a, 0xa7, 0x6f, 0x8a, 0x85, 0xf3, 0x9c, 0x90, 0xea, 0x19, ++ 0x7d, 0x3f, 0xb2, 0x2a, 0x05, 0xf2, 0xdd, 0x6a, 0xcc, 0x9e, 0x14, 0x05, ++ 0x4b, 0xd6, 0x5e, 0xf3, 0xe8, 0xcd, 0x48, 0x77, 0x0b, 0x0e, 0xdf, 0x9c, ++ 0xc2, 0xf2, 0x0f, 0xd5, 0x34, 0x9e, 0xe7, 0x91, 0x06, 0xe7, 0x9c, 0xbf, ++ 0x71, 0x0a, 0x9e, 0xb3, 0x9a, 0xb8, 0x91, 0xfe, 0x6a, 0x1e, 0x11, 0xab, ++ 0x20, 0x1f, 0xe6, 0x2b, 0x89, 0x8c, 0xde, 0x11, 0x86, 0x3f, 0x6e, 0xe3, ++ 0xfc, 0x71, 0x62, 0x33, 0x45, 0x2e, 0x3d, 0xe7, 0x09, 0x90, 0x97, 0x3a, ++ 0xbf, 0x47, 0x7b, 0xbf, 0xf9, 0xe6, 0xee, 0x78, 0x08, 0xbb, 0x8f, 0xfc, ++ 0x8a, 0xdf, 0x47, 0x56, 0xf5, 0x32, 0x19, 0xf4, 0x4b, 0x37, 0xdd, 0x6e, ++ 0x59, 0x8d, 0x72, 0xf5, 0xd3, 0x0c, 0x35, 0x15, 0xee, 0x29, 0x29, 0x1c, ++ 0x34, 0x39, 0x8a, 0xf2, 0x55, 0x3c, 0x5c, 0x9e, 0xca, 0xf0, 0xc4, 0xe4, ++ 0x31, 0x8e, 0xa3, 0xf4, 0x57, 0x0a, 0xed, 0xd0, 0xbf, 0xc3, 0x8c, 0xf7, ++ 0xc3, 0xba, 0x71, 0x5c, 0x7e, 0xb2, 0xf5, 0x97, 0xf3, 0xf5, 0xe9, 0xbe, ++ 0xa3, 0xc1, 0x1e, 0x39, 0x91, 0x12, 0xfe, 0xbd, 0xa0, 0xc7, 0x7b, 0x09, ++ 0xda, 0xfe, 0x3a, 0x88, 0x8e, 0xce, 0x74, 0x7c, 0xce, 0xf8, 0x7e, 0xcb, ++ 0x5a, 0xc6, 0xe7, 0x1a, 0xdf, 0x7b, 0xaf, 0x1e, 0x0d, 0xcf, 0xbf, 0x7c, ++ 0x9b, 0xf1, 0x11, 0x8c, 0x03, 0x7d, 0x44, 0xf7, 0xe5, 0x4b, 0xc5, 0xe7, ++ 0xed, 0x93, 0x05, 0x94, 0x0b, 0x16, 0xe2, 0x0b, 0xc7, 0xdf, 0x5b, 0xcc, ++ 0x9c, 0xbf, 0x8d, 0xcf, 0xa9, 0xc5, 0x8e, 0xf6, 0x9c, 0x46, 0x27, 0x74, ++ 0xff, 0x12, 0x7c, 0x97, 0x2c, 0x48, 0x2f, 0x74, 0x9d, 0x04, 0xc4, 0x03, ++ 0xda, 0x2b, 0xd5, 0x0f, 0xd0, 0xf1, 0x3a, 0x3b, 0xbb, 0x0e, 0xd6, 0xc5, ++ 0x7e, 0x72, 0xb0, 0x3d, 0x2b, 0xc8, 0xc7, 0x0b, 0xb8, 0x3c, 0xb8, 0xb9, ++ 0x17, 0x95, 0x07, 0x97, 0x05, 0xe5, 0x01, 0xd9, 0x98, 0x7c, 0x51, 0xf1, ++ 0x81, 0x25, 0x66, 0xef, 0xe3, 0x3f, 0x07, 0xfe, 0xa5, 0xfc, 0xea, 0x71, ++ 0x02, 0xff, 0x9a, 0xf1, 0xfd, 0x9b, 0xcf, 0xb6, 0xef, 0x3f, 0x72, 0x1d, ++ 0xa5, 0xf3, 0xcf, 0x5a, 0x34, 0xbe, 0x35, 0xca, 0xd3, 0x50, 0xbe, 0xad, ++ 0xd9, 0x79, 0x33, 0xc6, 0x09, 0x43, 0xf9, 0xf6, 0xb3, 0xf4, 0x7a, 0x12, ++ 0x96, 0x6f, 0xd3, 0xf9, 0xfb, 0x73, 0xa1, 0x7c, 0x9b, 0xde, 0xf9, 0x1f, ++ 0x95, 0xa7, 0x1a, 0xfc, 0x1e, 0x09, 0x81, 0x1f, 0x95, 0x8f, 0xbf, 0xdc, ++ 0xed, 0x8c, 0x0c, 0xc7, 0x50, 0xf9, 0x38, 0xac, 0x97, 0x33, 0xac, 0x7c, ++ 0xa4, 0x7f, 0x6f, 0x93, 0x82, 0x9e, 0x74, 0xa8, 0xd1, 0x9f, 0x46, 0x77, ++ 0x8b, 0x7e, 0xbd, 0xb4, 0x0f, 0xc8, 0xa1, 0x6e, 0xfa, 0xd4, 0xe8, 0xaf, ++ 0x9b, 0x3e, 0x35, 0xfa, 0x0b, 0x3d, 0xaf, 0x11, 0x7e, 0xa1, 0xcf, 0xab, ++ 0x21, 0xe9, 0x49, 0x67, 0x3f, 0x98, 0xef, 0x22, 0x1e, 0x3b, 0xc5, 0xb7, ++ 0x7f, 0x8f, 0x88, 0xdf, 0x4d, 0xea, 0x72, 0xfa, 0x63, 0x21, 0x0e, 0xb4, ++ 0x2a, 0x8a, 0xcc, 0x02, 0x3b, 0xbc, 0x4b, 0xe1, 0xf5, 0x78, 0x56, 0xf7, ++ 0x27, 0xcb, 0x4d, 0x20, 0x27, 0xb4, 0x76, 0x7f, 0x14, 0x8b, 0xab, 0x75, ++ 0x55, 0xf9, 0x63, 0xe3, 0x75, 0xf6, 0xf5, 0xb1, 0x36, 0x31, 0x16, 0xe2, ++ 0xbc, 0x9d, 0xde, 0xf0, 0xdf, 0x79, 0xc3, 0xcc, 0x44, 0xba, 0x7e, 0x67, ++ 0x84, 0xef, 0xc0, 0x69, 0x71, 0x89, 0xae, 0xe8, 0xd8, 0x41, 0xb8, 0x5e, ++ 0x74, 0xa6, 0x17, 0xf0, 0x55, 0x2e, 0xda, 0x32, 0x6f, 0x81, 0xfc, 0xd1, ++ 0x66, 0x11, 0xbf, 0xe7, 0x33, 0x6f, 0xe5, 0xb5, 0xb1, 0x90, 0x27, 0xd2, ++ 0xd5, 0xd6, 0x77, 0xe2, 0x34, 0xda, 0x3e, 0xff, 0x15, 0xfe, 0x39, 0x3f, ++ 0x8f, 0x2a, 0xa5, 0x51, 0x38, 0xcf, 0xe5, 0x78, 0x3f, 0x49, 0x3c, 0x0f, ++ 0x15, 0xd1, 0xf3, 0xcd, 0x6d, 0x63, 0xf6, 0xf3, 0xbc, 0x0d, 0xe1, 0xe9, ++ 0x44, 0xbb, 0x3f, 0xaf, 0xb6, 0x2d, 0x97, 0x41, 0x1e, 0x51, 0xbb, 0xf5, ++ 0x43, 0x7d, 0xfc, 0x68, 0x11, 0xff, 0xde, 0x42, 0xcd, 0xc6, 0x90, 0xf6, ++ 0xb6, 0x71, 0x48, 0x4f, 0x8b, 0x42, 0xe8, 0xc9, 0xcd, 0xfd, 0xa3, 0x13, ++ 0xbd, 0xb8, 0x7e, 0x1e, 0x4c, 0x06, 0x73, 0xff, 0xc4, 0xa4, 0xcf, 0x0b, ++ 0x29, 0x17, 0x73, 0x27, 0xc2, 0x3b, 0x1e, 0x5d, 0x87, 0x44, 0xcc, 0xbb, ++ 0x3e, 0xdb, 0x26, 0x92, 0x26, 0x38, 0xe7, 0x76, 0xc1, 0x4b, 0x80, 0xbf, ++ 0x3d, 0xc9, 0x48, 0x97, 0xb5, 0x54, 0x7e, 0xe8, 0xe3, 0xc0, 0xa7, 0x80, ++ 0xee, 0xce, 0xf3, 0x3e, 0xdd, 0xa9, 0xdf, 0xfe, 0x77, 0xc1, 0xed, 0xb4, ++ 0xcb, 0x92, 0x67, 0xdf, 0x1f, 0xf4, 0x0b, 0x5a, 0x9e, 0x7a, 0xf6, 0xbd, ++ 0x4b, 0x5e, 0x80, 0xfa, 0x73, 0x47, 0x33, 0xdf, 0x27, 0x3d, 0xfb, 0x97, ++ 0xee, 0xfd, 0x66, 0x26, 0xc8, 0xff, 0xae, 0xbd, 0x16, 0x82, 0x71, 0x95, ++ 0xbd, 0x2f, 0x67, 0xde, 0x0e, 0xf5, 0xdd, 0x16, 0xcc, 0x3f, 0xea, 0xba, ++ 0xcb, 0xc2, 0xe2, 0xc1, 0x7b, 0xed, 0x98, 0x4f, 0xd7, 0x95, 0xc1, 0xde, ++ 0x8b, 0x69, 0xd8, 0xf3, 0xf5, 0x20, 0xcc, 0xdf, 0x26, 0x8d, 0x88, 0xb7, ++ 0x84, 0xde, 0xcc, 0xef, 0x38, 0xdb, 0xf6, 0xb7, 0x3f, 0xe2, 0x7b, 0xb6, ++ 0x6d, 0xf4, 0x54, 0xa0, 0x6f, 0xf7, 0xc6, 0xa0, 0x3d, 0x5e, 0xb7, 0x3b, ++ 0xca, 0x0b, 0x4e, 0x6a, 0xd7, 0x9e, 0xaf, 0x0b, 0xf4, 0xf7, 0x18, 0xdf, ++ 0xf7, 0x3c, 0xb5, 0x32, 0x8b, 0xe3, 0x77, 0xd9, 0xc9, 0x34, 0x88, 0x7f, ++ 0x75, 0xc5, 0xb3, 0x3c, 0x9b, 0xba, 0x17, 0x86, 0x3d, 0xb6, 0x92, 0xae, ++ 0xbf, 0xb4, 0xb5, 0x5d, 0x86, 0xf7, 0x77, 0x4a, 0x5f, 0xfc, 0xfb, 0x20, ++ 0x90, 0x37, 0x5d, 0x3b, 0x99, 0x1d, 0x71, 0xda, 0xdc, 0xf9, 0x28, 0x71, ++ 0x11, 0x92, 0xd1, 0xfb, 0x8e, 0xbb, 0xcd, 0x14, 0x5f, 0xa7, 0xc1, 0xb6, ++ 0xa3, 0xbc, 0xf2, 0x7c, 0xef, 0x3d, 0xe3, 0xe1, 0x9e, 0xa3, 0x27, 0x5c, ++ 0x18, 0x1c, 0xba, 0x28, 0x1c, 0xe0, 0x5c, 0x14, 0x2e, 0x35, 0x20, 0x27, ++ 0x23, 0xc1, 0x23, 0xbf, 0x37, 0xfb, 0x4e, 0xcf, 0x0f, 0x0f, 0x1e, 0x67, ++ 0x66, 0xc2, 0xfa, 0x4b, 0xda, 0xae, 0xc0, 0x7b, 0x88, 0x20, 0x5c, 0x04, ++ 0x95, 0xb5, 0xdb, 0xbd, 0x56, 0x01, 0xcf, 0xcf, 0xda, 0xf7, 0x7e, 0x3d, ++ 0x08, 0xe4, 0xf1, 0x67, 0x2d, 0x2b, 0x51, 0xbf, 0x5f, 0xe8, 0xdc, 0xd7, ++ 0xfc, 0x60, 0xe9, 0xe0, 0x9f, 0x3d, 0xb7, 0xe0, 0xbb, 0x98, 0x73, 0x2f, ++ 0xfb, 0xc1, 0x9e, 0x9b, 0xd1, 0x7f, 0x00, 0xf4, 0x53, 0x72, 0x4f, 0x3e, ++ 0xe8, 0x49, 0xe7, 0xcf, 0xfd, 0x18, 0xeb, 0x4f, 0xdb, 0x5d, 0xb8, 0xdf, ++ 0x8b, 0xe4, 0xff, 0xfb, 0xff, 0x5f, 0xa3, 0xf7, 0x9d, 0x02, 0xe6, 0xb1, ++ 0x5c, 0x08, 0xef, 0x3b, 0xfe, 0xd7, 0xe2, 0xfd, 0x15, 0x8e, 0x77, 0xbb, ++ 0x02, 0xf9, 0x12, 0x5d, 0x7b, 0xfe, 0x9e, 0x49, 0x74, 0xe7, 0xbf, 0xd0, ++ 0xb9, 0x3b, 0x7e, 0xb0, 0xf8, 0x3e, 0xff, 0xb9, 0x35, 0x3b, 0xa8, 0xc3, ++ 0x54, 0xaf, 0xe4, 0xd3, 0xfd, 0xbd, 0x47, 0x9a, 0xa7, 0x64, 0xd1, 0xf2, ++ 0x2d, 0xf5, 0x8b, 0x24, 0x70, 0x5b, 0x2d, 0x91, 0xee, 0x6b, 0xd2, 0x99, ++ 0x5f, 0x61, 0x11, 0x58, 0xfe, 0x37, 0x99, 0x22, 0x68, 0xf1, 0xa5, 0x0e, ++ 0x43, 0xfe, 0x53, 0x7a, 0x0d, 0xda, 0x1b, 0x13, 0xd4, 0xbb, 0xd9, 0x77, ++ 0x9a, 0xa4, 0xfa, 0x0e, 0xc8, 0x3f, 0xed, 0x28, 0x99, 0xeb, 0x5a, 0x87, ++ 0x3d, 0xf2, 0xf0, 0xbb, 0x02, 0x1d, 0x93, 0x47, 0xf2, 0xba, 0xd1, 0xdf, ++ 0x7a, 0x53, 0x20, 0xaa, 0x40, 0xed, 0xdb, 0x09, 0x25, 0xe3, 0x0e, 0x81, ++ 0xbd, 0x37, 0x51, 0x15, 0xd1, 0x1e, 0xa4, 0x25, 0xda, 0x81, 0xef, 0x64, ++ 0x56, 0xb0, 0xf6, 0x42, 0xa3, 0x9f, 0x31, 0x3d, 0xc4, 0x3f, 0xb8, 0x76, ++ 0x9a, 0xf1, 0xf9, 0x14, 0x3e, 0xdf, 0x54, 0xb2, 0x4c, 0xc9, 0xa7, 0xf0, ++ 0x9a, 0x9a, 0x2e, 0x29, 0x5e, 0x0a, 0xa2, 0xe9, 0xc5, 0xf5, 0x66, 0x38, ++ 0xcf, 0xf4, 0x1b, 0x04, 0xd2, 0xac, 0x8b, 0x6f, 0x4e, 0x09, 0x99, 0xef, ++ 0x03, 0x08, 0xa0, 0xe9, 0xec, 0xc8, 0xef, 0x0a, 0xbf, 0xbc, 0x74, 0xe6, ++ 0x77, 0x5a, 0x84, 0x65, 0x08, 0x0f, 0x52, 0x2c, 0xf2, 0xf7, 0x8d, 0x2e, ++ 0x00, 0x3f, 0xc2, 0xe0, 0xdd, 0x31, 0x79, 0x30, 0xcb, 0x33, 0x96, 0x5c, ++ 0x0c, 0x7e, 0x53, 0x97, 0xba, 0x30, 0x6e, 0xca, 0xfd, 0x50, 0x33, 0x1f, ++ 0x6f, 0xb6, 0xad, 0xe9, 0x00, 0xbe, 0x35, 0x13, 0xa3, 0xff, 0xa9, 0xf9, ++ 0x91, 0x91, 0xe0, 0x4c, 0xb8, 0x5f, 0x8a, 0xf3, 0x64, 0x07, 0xe1, 0x6e, ++ 0x56, 0x45, 0xf4, 0x4b, 0x75, 0xf3, 0x21, 0x3c, 0x34, 0x7c, 0x7c, 0x57, ++ 0x3c, 0x68, 0xf8, 0xfb, 0xbe, 0xf8, 0x90, 0xd2, 0x89, 0xe1, 0x5e, 0x55, ++ 0x2b, 0x17, 0x5a, 0x67, 0x2f, 0x86, 0x7b, 0x08, 0x2b, 0xe4, 0xbd, 0xd3, ++ 0x79, 0x27, 0x6e, 0x60, 0xef, 0x91, 0x58, 0x73, 0x05, 0x84, 0x63, 0x55, ++ 0xa1, 0x19, 0xdf, 0xe3, 0xfa, 0xb3, 0xa9, 0xaa, 0x00, 0x0c, 0xe7, 0xca, ++ 0x21, 0x57, 0xd4, 0xde, 0xc6, 0xa6, 0x75, 0x01, 0x7c, 0x16, 0x72, 0x38, ++ 0x56, 0x93, 0x7a, 0xb4, 0x3b, 0xc9, 0xb7, 0xe7, 0xce, 0x15, 0x15, 0xe0, ++ 0xad, 0x1f, 0xda, 0xad, 0x0b, 0x55, 0x42, 0xc6, 0x53, 0xbf, 0xa4, 0xba, ++ 0x48, 0xf0, 0x45, 0xd3, 0xf3, 0x2f, 0x90, 0x88, 0x27, 0x2e, 0x0f, 0xe2, ++ 0xa0, 0x02, 0xf9, 0x50, 0x1f, 0x07, 0xf5, 0x1a, 0xeb, 0xf0, 0x77, 0x65, ++ 0x4a, 0x70, 0x9e, 0x0b, 0xf5, 0x8f, 0x24, 0x1f, 0xfe, 0xd5, 0xe5, 0x9f, ++ 0xa8, 0x3c, 0xfa, 0x90, 0x22, 0xfd, 0x18, 0x94, 0x98, 0x3f, 0x43, 0x24, ++ 0xbd, 0xff, 0x38, 0xab, 0x8d, 0xc1, 0xb1, 0x6e, 0x89, 0xe0, 0xcd, 0x46, ++ 0x3a, 0xf2, 0x99, 0xf5, 0xf7, 0xc0, 0x4f, 0x70, 0xba, 0xfe, 0xd3, 0x1d, ++ 0x43, 0x50, 0xce, 0x15, 0xdf, 0x3b, 0x30, 0x8e, 0xf9, 0xb5, 0xf9, 0x98, ++ 0xd7, 0x53, 0xc7, 0xed, 0xfd, 0xb3, 0x1e, 0x67, 0x1c, 0xc4, 0x73, 0xce, ++ 0xb6, 0xf5, 0x8d, 0x83, 0x78, 0xcd, 0xd9, 0x43, 0xa5, 0xb1, 0xe1, 0xf2, ++ 0x79, 0x0e, 0x73, 0xbf, 0xf2, 0xf7, 0x2b, 0xac, 0x58, 0x76, 0x95, 0x09, ++ 0xcd, 0x62, 0x1c, 0xbe, 0x7f, 0x32, 0x01, 0xf5, 0x70, 0x59, 0x14, 0x01, ++ 0xb9, 0x13, 0x3a, 0x6e, 0x75, 0xba, 0x16, 0x97, 0xa9, 0x97, 0x31, 0x8e, ++ 0x4f, 0x58, 0x3e, 0x7e, 0x35, 0x3f, 0xc7, 0x02, 0x3a, 0x34, 0x2e, 0x41, ++ 0x87, 0xb7, 0x0d, 0xe3, 0x3f, 0x91, 0x06, 0xf5, 0xc4, 0x03, 0xfc, 0x7d, ++ 0xa8, 0xbb, 0x57, 0xf9, 0xbe, 0xf0, 0x05, 0x3f, 0x16, 0xe0, 0x7a, 0x38, ++ 0xaa, 0xb3, 0x22, 0xdc, 0x77, 0x0a, 0x7f, 0xc6, 0xe5, 0x6a, 0xe5, 0xbe, ++ 0x6f, 0x64, 0x88, 0x1f, 0x4c, 0x6a, 0xcb, 0xc2, 0xef, 0x4c, 0x4e, 0x2a, ++ 0x33, 0xbe, 0x0f, 0x78, 0x5f, 0x3a, 0xf7, 0xcf, 0x87, 0x90, 0x21, 0xb0, ++ 0xaf, 0xca, 0x7d, 0x63, 0x62, 0x87, 0x01, 0x5e, 0x0e, 0x89, 0xae, 0x28, ++ 0x0a, 0xdf, 0xba, 0xb6, 0x33, 0xb2, 0x3b, 0xcc, 0xfd, 0x5c, 0x28, 0x3c, ++ 0x61, 0x7e, 0x88, 0x23, 0x1f, 0x37, 0xbb, 0xaa, 0x01, 0x9e, 0xc7, 0xef, ++ 0x8e, 0xc2, 0xef, 0x00, 0xbc, 0xc1, 0xef, 0x8b, 0x72, 0xf9, 0xf7, 0x21, ++ 0xe1, 0x13, 0x42, 0x10, 0x3f, 0xdb, 0x9c, 0xce, 0xee, 0x21, 0xbe, 0x4e, ++ 0x67, 0x71, 0xf4, 0x6b, 0x2a, 0x8b, 0xcd, 0xc9, 0x74, 0xdd, 0xdc, 0x56, ++ 0x65, 0x30, 0xe4, 0x97, 0xf5, 0xe2, 0xfd, 0xbf, 0x4e, 0x77, 0xe2, 0xf3, ++ 0xde, 0x7c, 0x9c, 0xd6, 0xaf, 0xd7, 0x12, 0xd6, 0xef, 0x98, 0xac, 0xd4, ++ 0x86, 0x3b, 0x7f, 0x46, 0x26, 0xa3, 0x9f, 0x05, 0xc4, 0xf5, 0xe3, 0x42, ++ 0xe1, 0x87, 0x87, 0xb7, 0xe2, 0x7b, 0xed, 0x3e, 0x78, 0x3f, 0xee, 0x6c, ++ 0x99, 0xc0, 0xdf, 0x9f, 0x09, 0xa5, 0x6b, 0x82, 0xfc, 0x71, 0x76, 0xb4, ++ 0xe0, 0x05, 0xfd, 0x0b, 0x7e, 0x2c, 0xd6, 0x2b, 0x05, 0xd4, 0xff, 0x6f, ++ 0x68, 0x79, 0x15, 0x93, 0x98, 0xbe, 0xd4, 0xe8, 0x3e, 0x14, 0xce, 0x6f, ++ 0x71, 0xfa, 0xd5, 0xd6, 0xef, 0xe2, 0x70, 0x7f, 0x9b, 0xd3, 0x87, 0x06, ++ 0x67, 0x0d, 0xbe, 0xa1, 0xfb, 0xd5, 0xfa, 0x53, 0x79, 0x75, 0x95, 0x3e, ++ 0xde, 0x32, 0x71, 0xd7, 0xe0, 0xa7, 0xc1, 0x3e, 0xa9, 0x6d, 0x13, 0x14, ++ 0x13, 0x9d, 0xaa, 0x56, 0xea, 0x94, 0x81, 0x0f, 0xeb, 0x76, 0xdd, 0x67, ++ 0x86, 0xfb, 0x85, 0xe9, 0xfc, 0x77, 0x5a, 0x88, 0x54, 0x35, 0x48, 0x7f, ++ 0xbf, 0xfb, 0x75, 0xba, 0x84, 0xf3, 0xed, 0xcf, 0x1b, 0x81, 0xf6, 0xe3, ++ 0x17, 0x1b, 0x98, 0x7d, 0xac, 0xce, 0x3b, 0x13, 0x0b, 0x76, 0xd0, 0x1b, ++ 0x26, 0xd7, 0x5b, 0x23, 0x80, 0x1f, 0xdf, 0x14, 0x0d, 0xdf, 0x37, 0x0f, ++ 0x2d, 0xdf, 0x5f, 0xa1, 0x2c, 0x2a, 0x33, 0xeb, 0xe7, 0xcd, 0x62, 0x7e, ++ 0xd2, 0x92, 0x62, 0x33, 0x84, 0x87, 0xae, 0x5f, 0xd2, 0x6e, 0x4e, 0xd5, ++ 0xd1, 0xd3, 0xd7, 0x90, 0x8f, 0x35, 0x34, 0xd8, 0xde, 0x6b, 0x89, 0x13, ++ 0xf3, 0x18, 0xe9, 0x7a, 0xb8, 0x0f, 0xcf, 0x3d, 0x16, 0x02, 0xf9, 0x4b, ++ 0xb9, 0x2d, 0x1d, 0x25, 0x31, 0xf4, 0xf9, 0xf5, 0xf5, 0xf1, 0x8c, 0x0e, ++ 0x6b, 0x5a, 0xda, 0x65, 0xac, 0xb3, 0xef, 0x0d, 0x6b, 0xeb, 0x69, 0xeb, ++ 0x84, 0xf2, 0xd3, 0xe4, 0xca, 0x18, 0x43, 0x7d, 0x6e, 0x69, 0x67, 0x3a, ++ 0xc0, 0xa5, 0xd2, 0xe2, 0x5b, 0xee, 0x0a, 0x43, 0xa7, 0xf7, 0x67, 0x74, ++ 0xc7, 0x55, 0xbf, 0x9b, 0x9e, 0x50, 0x29, 0xdd, 0x0e, 0xfa, 0xff, 0x41, ++ 0x4f, 0x9c, 0xa9, 0x08, 0xf7, 0x3d, 0xd4, 0xd9, 0x1c, 0x6e, 0x3a, 0xfd, ++ 0x90, 0x1a, 0x4e, 0x3f, 0x2c, 0x5b, 0xe9, 0x4c, 0x05, 0xf8, 0x2f, 0xdb, ++ 0xd3, 0x37, 0x15, 0x98, 0x63, 0xd9, 0x2b, 0xe5, 0x29, 0xe1, 0xf4, 0xc3, ++ 0x3b, 0x2b, 0xd8, 0xfd, 0xe1, 0x51, 0x9e, 0x7f, 0xd9, 0x35, 0x99, 0xea, ++ 0x87, 0xcb, 0x75, 0xfa, 0x61, 0x72, 0x14, 0xd2, 0x47, 0xe8, 0xb8, 0x71, ++ 0x19, 0xda, 0x77, 0x55, 0x2e, 0xa0, 0x1f, 0x34, 0x7c, 0xfd, 0x87, 0xe5, ++ 0xcc, 0x3b, 0xa0, 0x1f, 0xc2, 0xf0, 0xf5, 0xcc, 0x0c, 0xa3, 0x7e, 0x98, ++ 0xda, 0x36, 0x1b, 0xf5, 0xc3, 0xd4, 0xc9, 0x22, 0x71, 0xea, 0xe2, 0x71, ++ 0x53, 0x32, 0x2e, 0xa4, 0x1f, 0x8a, 0x53, 0xa6, 0x63, 0xdd, 0xec, 0x8a, ++ 0x09, 0x43, 0x37, 0xef, 0x70, 0xbf, 0x04, 0xe0, 0x0a, 0x25, 0xac, 0x03, ++ 0x7a, 0xe2, 0xee, 0x0c, 0x26, 0xf7, 0x43, 0xf5, 0x45, 0x24, 0x79, 0x9e, ++ 0x7d, 0xb1, 0xf2, 0xfc, 0x7f, 0x08, 0xce, 0x9a, 0x3c, 0x5f, 0x36, 0x85, ++ 0xbd, 0xcf, 0xdf, 0x93, 0x0e, 0x09, 0xca, 0xeb, 0x65, 0xd3, 0x05, 0xfc, ++ 0x1d, 0x93, 0x65, 0x7b, 0x98, 0x3c, 0x5f, 0x76, 0x03, 0x8f, 0x4b, 0x86, ++ 0xc8, 0xd7, 0x2a, 0x90, 0xaf, 0xf9, 0x7a, 0xf9, 0xca, 0xc6, 0xd7, 0xba, ++ 0x99, 0x3e, 0xa8, 0xdb, 0x95, 0xf5, 0xd3, 0x19, 0xf4, 0xf9, 0x75, 0xcd, ++ 0x66, 0x97, 0x95, 0xf6, 0xbf, 0x2e, 0x28, 0x6f, 0x0b, 0xf4, 0xf2, 0xf6, ++ 0xee, 0x0c, 0x49, 0x83, 0x73, 0xa6, 0x12, 0x06, 0xbf, 0xd3, 0x66, 0xc4, ++ 0x10, 0xa7, 0x51, 0x5e, 0xf5, 0x03, 0x39, 0x75, 0x7c, 0xf0, 0xcb, 0xb9, ++ 0xcf, 0x00, 0xdd, 0xbf, 0xc1, 0xde, 0x37, 0xfb, 0x33, 0xd7, 0xe3, 0xaf, ++ 0x0f, 0x7e, 0x39, 0x1f, 0xe2, 0xe9, 0x1f, 0xf1, 0x79, 0x5b, 0x33, 0x18, ++ 0x5e, 0x4e, 0xaf, 0x20, 0x8b, 0xca, 0x28, 0x1c, 0x4a, 0xe7, 0x31, 0x7b, ++ 0x78, 0xe9, 0x76, 0x11, 0xe1, 0x50, 0xdb, 0xca, 0xec, 0xbc, 0xda, 0x6d, ++ 0x02, 0xbe, 0xd7, 0x5b, 0x91, 0xf7, 0x0d, 0xde, 0x1b, 0x2e, 0xde, 0xc3, ++ 0xee, 0x0d, 0xe1, 0xbb, 0xbe, 0xc5, 0x3a, 0x3c, 0x2e, 0x7e, 0xa3, 0xb3, ++ 0xa9, 0x37, 0x3c, 0xdf, 0x24, 0xe0, 0xbd, 0x67, 0xb5, 0x6b, 0x31, 0x7b, ++ 0xff, 0xef, 0x61, 0x16, 0x27, 0xb6, 0xd2, 0xff, 0x20, 0x5f, 0x62, 0x6d, ++ 0x74, 0xec, 0x66, 0x82, 0x79, 0x3a, 0x2a, 0xc6, 0x9b, 0x97, 0x72, 0xb8, ++ 0x55, 0x5a, 0xfc, 0x07, 0x61, 0x7c, 0xe5, 0x13, 0x82, 0x6b, 0x13, 0xca, ++ 0x35, 0x63, 0x7c, 0x7a, 0x69, 0xbf, 0xb1, 0x9f, 0x80, 0x7f, 0xb0, 0x78, ++ 0x5b, 0x48, 0xbb, 0x6b, 0x2d, 0xde, 0x67, 0x2c, 0x85, 0xb8, 0xb3, 0xce, ++ 0x1f, 0xf9, 0x3d, 0xe7, 0x93, 0xf9, 0xa2, 0x2f, 0xf7, 0x19, 0xc8, 0x0f, ++ 0x7c, 0x4b, 0x0c, 0xfb, 0xbb, 0x67, 0x5a, 0xbf, 0x6e, 0x38, 0xd4, 0x7c, ++ 0x4f, 0x38, 0x1c, 0xa6, 0x70, 0xc8, 0xff, 0xe7, 0xe1, 0x50, 0xd7, 0x76, ++ 0x1f, 0xe6, 0xdf, 0x7c, 0xdf, 0xf3, 0xbf, 0x93, 0xc1, 0xe3, 0xed, 0x79, ++ 0x24, 0x1f, 0xf8, 0xe5, 0xcf, 0x26, 0x15, 0xf9, 0xdf, 0xf3, 0xaa, 0x88, ++ 0xef, 0x17, 0xcf, 0xbb, 0xaf, 0x7f, 0xaa, 0x3e, 0x4f, 0xe9, 0x38, 0x87, ++ 0xc3, 0x1b, 0x26, 0x77, 0x53, 0x1a, 0xf4, 0xab, 0x65, 0xef, 0x21, 0x2f, ++ 0xd8, 0xb8, 0xe3, 0x00, 0xbc, 0x22, 0x3e, 0xa3, 0x85, 0x0c, 0x86, 0xb0, ++ 0xfd, 0x82, 0x87, 0x8d, 0x7a, 0xb2, 0x5b, 0x2f, 0xb7, 0x3a, 0x51, 0xef, ++ 0xce, 0xa8, 0xdf, 0x21, 0xc0, 0x77, 0xfd, 0xe7, 0x8b, 0x04, 0x7f, 0x0f, ++ 0x6c, 0x6e, 0x9e, 0xc5, 0x0d, 0xf7, 0xaf, 0x87, 0xa3, 0xfc, 0x28, 0xcf, ++ 0x34, 0x3a, 0xb4, 0x67, 0xb2, 0xdf, 0x8f, 0x8b, 0xc9, 0x64, 0xeb, 0x1e, ++ 0xef, 0xe5, 0x2f, 0x43, 0xbf, 0x62, 0x97, 0xa0, 0x20, 0x9f, 0xc0, 0x77, ++ 0x35, 0xa0, 0x4e, 0xf1, 0x00, 0xdf, 0xd5, 0xd8, 0x3f, 0xec, 0xeb, 0x0a, ++ 0x0e, 0x77, 0x8c, 0xcf, 0xd4, 0xed, 0x62, 0x78, 0xaa, 0xa3, 0x78, 0x01, ++ 0x3e, 0xab, 0xa0, 0xf6, 0x2e, 0xe8, 0x91, 0xeb, 0xa9, 0xde, 0xc1, 0xfb, ++ 0xb2, 0xb6, 0x76, 0x33, 0xf4, 0xaf, 0xa1, 0xfd, 0x12, 0x51, 0xee, 0xb8, ++ 0xd0, 0xdf, 0xd5, 0xf4, 0x13, 0xdc, 0xdf, 0x15, 0xa7, 0xe8, 0xf0, 0xb6, ++ 0xe7, 0x18, 0xa3, 0xdf, 0xad, 0x82, 0x8b, 0x84, 0xc1, 0x5b, 0x0e, 0xfd, ++ 0xef, 0x7c, 0x78, 0x8b, 0x84, 0x2f, 0xcd, 0x7e, 0xb8, 0x58, 0xbc, 0x69, ++ 0xf0, 0xb0, 0x67, 0x1a, 0xf1, 0x77, 0x38, 0xaa, 0xa3, 0x72, 0x08, 0xde, ++ 0x53, 0xb1, 0xdf, 0x03, 0x22, 0x6d, 0xf1, 0x78, 0xaf, 0xf2, 0x51, 0x73, ++ 0x5f, 0xc4, 0x63, 0x6f, 0x2e, 0x67, 0x43, 0xe9, 0x1b, 0xec, 0x7d, 0xa7, ++ 0x2e, 0xbe, 0x74, 0x35, 0x6c, 0x1c, 0x3f, 0x60, 0x1f, 0x85, 0x79, 0x72, ++ 0xb8, 0x6e, 0x36, 0xb3, 0x87, 0xf4, 0xf2, 0x25, 0xd4, 0x8f, 0xae, 0x23, ++ 0x1d, 0x68, 0xd7, 0x24, 0xa7, 0xb9, 0x7f, 0x9d, 0xae, 0xcb, 0x8b, 0x9b, ++ 0xca, 0xf3, 0x57, 0xba, 0xef, 0x75, 0x83, 0xfd, 0xe6, 0x67, 0x9c, 0xa7, ++ 0x1f, 0x71, 0x94, 0xe0, 0xfd, 0x8f, 0x96, 0x57, 0x0b, 0xbf, 0x20, 0x85, ++ 0xf9, 0x60, 0xbc, 0xbe, 0x3f, 0xa3, 0xe0, 0xe8, 0x0c, 0x7a, 0xde, 0x2f, ++ 0xd6, 0x88, 0xf8, 0x9e, 0xf2, 0xb5, 0x26, 0xe7, 0x91, 0x22, 0xe0, 0xe3, ++ 0x75, 0x66, 0x02, 0x74, 0xf9, 0xc5, 0xeb, 0x66, 0x95, 0xd9, 0xa1, 0x31, ++ 0x28, 0x87, 0x67, 0xbf, 0x71, 0xdc, 0x0c, 0xa1, 0x91, 0xd9, 0x90, 0x5f, ++ 0x40, 0xfb, 0xcd, 0xbe, 0x93, 0xc9, 0xdb, 0xe3, 0x30, 0x19, 0x6d, 0xfb, ++ 0x03, 0xd5, 0x63, 0x2a, 0x7c, 0xbf, 0x84, 0xb4, 0x0c, 0x85, 0xfc, 0xfd, ++ 0xc9, 0xae, 0xf6, 0x72, 0xc8, 0xdf, 0x9e, 0x92, 0x7f, 0x78, 0x15, 0xdc, ++ 0xd3, 0x5d, 0x53, 0xaa, 0x1c, 0x39, 0x02, 0xf0, 0x5d, 0x2b, 0x12, 0x80, ++ 0xef, 0x87, 0x6b, 0x4a, 0xd1, 0x5f, 0xb9, 0xe9, 0x46, 0x01, 0xe9, 0xfa, ++ 0xdd, 0x15, 0xf8, 0x9b, 0x58, 0x64, 0xca, 0xe4, 0xac, 0x23, 0x47, 0xe8, ++ 0xba, 0x37, 0xac, 0x49, 0xc6, 0x7b, 0xb6, 0x19, 0xea, 0x81, 0x72, 0xa0, ++ 0xb7, 0xb9, 0x13, 0xed, 0x36, 0xb8, 0xa7, 0x1b, 0x97, 0x23, 0x06, 0xf3, ++ 0x7b, 0x09, 0xbc, 0x0f, 0xd5, 0xb1, 0x0a, 0xe4, 0xf7, 0x8c, 0xfa, 0x1b, ++ 0xa7, 0xc0, 0x7e, 0x6b, 0xa8, 0x5e, 0x80, 0xb8, 0x6b, 0x4d, 0xdb, 0xe1, ++ 0xf2, 0x54, 0xa8, 0x6f, 0x14, 0xf0, 0xf7, 0xd4, 0xea, 0x3c, 0x6e, 0x19, ++ 0x5e, 0x85, 0xea, 0x78, 0xf8, 0x8c, 0x0c, 0xf1, 0x8f, 0x6a, 0xda, 0x0f, ++ 0xd0, 0x53, 0xb7, 0x91, 0xf5, 0xab, 0xdb, 0x22, 0xe0, 0x7b, 0x3e, 0xd5, ++ 0x54, 0x3e, 0xc0, 0xf9, 0xaa, 0xb7, 0x08, 0x04, 0x5e, 0x28, 0xe9, 0xa0, ++ 0xf6, 0x9f, 0x95, 0xcd, 0xeb, 0x85, 0x0f, 0x34, 0x75, 0x6c, 0xa4, 0xe3, ++ 0x69, 0x7d, 0x01, 0x8c, 0x87, 0x79, 0xb7, 0xc4, 0xe3, 0xef, 0xde, 0xd5, ++ 0xbd, 0xce, 0xde, 0x13, 0xaa, 0x2e, 0x5c, 0x79, 0x10, 0xe4, 0x53, 0x35, ++ 0x1d, 0x47, 0x1f, 0x93, 0x8e, 0x2d, 0x37, 0xe2, 0x7c, 0x0b, 0x37, 0x0a, ++ 0x04, 0x52, 0x83, 0x6b, 0x0a, 0xb3, 0xee, 0x29, 0x84, 0xf9, 0x5e, 0x37, ++ 0xe3, 0xf7, 0x41, 0x8e, 0xb6, 0xff, 0x4c, 0x86, 0x7d, 0xcf, 0xa4, 0xeb, ++ 0xa5, 0xd1, 0xf9, 0xe7, 0x8a, 0x9d, 0xe5, 0x98, 0x6f, 0x7d, 0xbb, 0xa0, ++ 0xe0, 0x7b, 0x4d, 0x65, 0xb7, 0x21, 0x1f, 0x74, 0x71, 0x3e, 0x20, 0x49, ++ 0xb7, 0xb2, 0xfb, 0x66, 0x81, 0xd7, 0xb9, 0x5d, 0xa8, 0xe9, 0xc7, 0xc7, ++ 0x32, 0xb3, 0x91, 0xbe, 0xab, 0x6f, 0x59, 0xd9, 0x04, 0xe7, 0xea, 0xf4, ++ 0x24, 0x67, 0x81, 0x4b, 0x54, 0xb7, 0xeb, 0x8c, 0x0c, 0x76, 0xde, 0x47, ++ 0x2b, 0xe0, 0x03, 0x34, 0x14, 0x6f, 0x3c, 0x0f, 0x6e, 0xbf, 0xe7, 0xb8, ++ 0xdc, 0xa9, 0x93, 0x53, 0xbe, 0xcc, 0xbe, 0x48, 0x8f, 0xf3, 0x76, 0x15, ++ 0x23, 0x9f, 0xcf, 0x27, 0x55, 0x78, 0x2f, 0xee, 0x5e, 0xc9, 0xf4, 0xf2, ++ 0xb1, 0x55, 0x51, 0x5e, 0x01, 0xec, 0x11, 0xb3, 0x82, 0x7a, 0x73, 0xff, ++ 0xaa, 0x1f, 0x3d, 0x04, 0xe7, 0x3f, 0xfd, 0x94, 0x19, 0xef, 0x4b, 0x4f, ++ 0x67, 0x74, 0x62, 0x7c, 0xf6, 0xc4, 0x46, 0x33, 0x7e, 0x3f, 0xa4, 0x61, ++ 0xa3, 0x88, 0x72, 0xe4, 0xc4, 0x76, 0x16, 0x17, 0x12, 0x1f, 0x99, 0x52, ++ 0x91, 0x06, 0xf0, 0xa3, 0x72, 0x00, 0xe8, 0x6e, 0xff, 0xc6, 0x52, 0x19, ++ 0xe4, 0xe1, 0x09, 0xaf, 0x80, 0xe3, 0x4b, 0x1f, 0xb9, 0x39, 0x85, 0xc5, ++ 0x7d, 0x8d, 0xf2, 0xa3, 0xda, 0xb9, 0x08, 0xe5, 0xc5, 0x23, 0x51, 0x4c, ++ 0x3e, 0x2c, 0x78, 0x38, 0xfc, 0xfd, 0x6a, 0x44, 0x79, 0xb1, 0xbc, 0x82, ++ 0xc9, 0xf7, 0x10, 0x79, 0xb0, 0x34, 0xbd, 0x09, 0xe3, 0x7e, 0xa1, 0x72, ++ 0xa2, 0x8e, 0xd8, 0x34, 0xf9, 0x90, 0x07, 0xf5, 0x0e, 0x5f, 0x1a, 0xd2, ++ 0x6f, 0xed, 0xeb, 0x66, 0x02, 0xf6, 0x5d, 0xad, 0xa4, 0xcc, 0x7c, 0x18, ++ 0xe8, 0x66, 0x46, 0x14, 0xdc, 0x24, 0x53, 0xbe, 0xf0, 0x1d, 0x00, 0xf9, ++ 0xf6, 0x85, 0x57, 0x70, 0x7a, 0xe8, 0xf3, 0xeb, 0x67, 0x3d, 0x3f, 0x14, ++ 0xe0, 0xf7, 0x31, 0xc0, 0x1b, 0xf8, 0x62, 0x43, 0x22, 0xde, 0xaf, 0x56, ++ 0x7b, 0x67, 0x23, 0x5c, 0xb5, 0x7c, 0xc4, 0x05, 0x0f, 0x1b, 0xe9, 0x59, ++ 0xcb, 0x7b, 0x9a, 0xee, 0x16, 0x83, 0xef, 0xfb, 0xd0, 0xff, 0x5d, 0x5f, ++ 0x13, 0x43, 0x54, 0x5d, 0xbf, 0xa3, 0x77, 0x52, 0xba, 0xa4, 0xeb, 0xcd, ++ 0xda, 0x25, 0x78, 0xe1, 0x3b, 0x48, 0x47, 0xef, 0x3c, 0x76, 0xf0, 0xe6, ++ 0x7c, 0xac, 0x2b, 0x40, 0x87, 0xb5, 0xb7, 0x70, 0xbd, 0xba, 0xc1, 0x8e, ++ 0x74, 0x7b, 0xf4, 0xd6, 0x33, 0xab, 0x80, 0x2e, 0x67, 0xde, 0x21, 0xe0, ++ 0xfe, 0x89, 0xc7, 0xdd, 0x04, 0x7a, 0xa5, 0xf6, 0x61, 0xc1, 0x09, 0x71, ++ 0xcd, 0x05, 0x77, 0xb0, 0xf1, 0x0b, 0xe8, 0x78, 0xa0, 0x97, 0xa3, 0x3f, ++ 0x63, 0xf4, 0x43, 0xe9, 0xd8, 0x09, 0x74, 0x5e, 0xbb, 0xf1, 0xbe, 0x83, ++ 0xd8, 0x7f, 0x8b, 0xe0, 0x84, 0xf9, 0x8f, 0x6e, 0x9a, 0x8d, 0x7a, 0xb8, ++ 0xc6, 0x23, 0x12, 0x7c, 0xbe, 0xe5, 0x18, 0xda, 0xcb, 0x54, 0x1f, 0x60, ++ 0xde, 0xd0, 0x7e, 0x8f, 0x98, 0x02, 0x74, 0x5e, 0xdb, 0x68, 0x51, 0x00, ++ 0xaf, 0x1a, 0xbd, 0x68, 0xf4, 0x77, 0x8c, 0x7f, 0x87, 0x9a, 0x58, 0x5d, ++ 0x83, 0xae, 0xa1, 0xe3, 0x6e, 0xcc, 0x74, 0x86, 0xa5, 0x3b, 0x71, 0x5a, ++ 0x16, 0xd2, 0x57, 0xdd, 0x76, 0x33, 0xd2, 0x4b, 0x9d, 0x87, 0xd1, 0xd3, ++ 0xb1, 0xa7, 0x44, 0xa4, 0xc3, 0xfd, 0xab, 0xae, 0xad, 0x00, 0xfa, 0x39, ++ 0xbd, 0x55, 0x88, 0x40, 0x7f, 0x94, 0xbe, 0xf2, 0x83, 0xf4, 0x25, 0x3e, ++ 0x62, 0xc6, 0xf1, 0x0b, 0x9e, 0x64, 0xf1, 0x85, 0xfd, 0x1b, 0x19, 0x5d, ++ 0x9f, 0x68, 0x65, 0xf6, 0x69, 0xe9, 0x23, 0xfd, 0xd1, 0xaf, 0x59, 0xf0, ++ 0x86, 0x99, 0xb0, 0xf8, 0x03, 0xb1, 0xe9, 0xed, 0x8f, 0x0b, 0xd1, 0x61, ++ 0x28, 0xdd, 0xf5, 0xd0, 0x4b, 0x9c, 0x0e, 0x23, 0xd1, 0x9d, 0xdb, 0xdc, ++ 0x32, 0x15, 0xf2, 0x0f, 0x66, 0x3f, 0x4d, 0xf7, 0xef, 0x0c, 0xc2, 0xab, ++ 0xb4, 0xe9, 0x56, 0x8c, 0x03, 0x94, 0x36, 0x4d, 0xc7, 0xf3, 0x6a, 0xfc, ++ 0x53, 0x2d, 0xb1, 0xbc, 0x8d, 0x79, 0xcd, 0x2b, 0x59, 0x3e, 0xa3, 0xc4, ++ 0xf2, 0x7b, 0xbe, 0xf3, 0xbe, 0x42, 0xf6, 0x71, 0x5f, 0x50, 0x3f, 0xe6, ++ 0x81, 0x7e, 0x84, 0xfc, 0x13, 0x1f, 0xdd, 0xc7, 0xcb, 0xdb, 0x1f, 0x43, ++ 0x3b, 0xe0, 0xf3, 0x5f, 0x1d, 0xc3, 0xfc, 0xc6, 0xc5, 0x2f, 0x50, 0xfc, ++ 0xd3, 0xfe, 0xa7, 0xb7, 0xdb, 0x89, 0x0f, 0xed, 0x6c, 0x2f, 0xca, 0x99, ++ 0x45, 0xad, 0x22, 0xe6, 0x97, 0x12, 0xc9, 0x57, 0x70, 0x8d, 0xee, 0x7d, ++ 0x0d, 0x2d, 0x2f, 0x63, 0xf1, 0x6f, 0xec, 0x08, 0xf7, 0x45, 0x3b, 0x2d, ++ 0xde, 0x4a, 0x3a, 0x7e, 0xd1, 0xb3, 0xc7, 0x07, 0xe1, 0x3d, 0xf9, 0x5d, ++ 0xcc, 0x4e, 0xf5, 0xfc, 0x8a, 0x7d, 0x6f, 0x86, 0x78, 0x3a, 0x07, 0x5d, ++ 0x03, 0xf9, 0x99, 0x12, 0xcb, 0x0f, 0x09, 0xd5, 0xbf, 0xd1, 0x7d, 0x58, ++ 0x1c, 0xe7, 0xd4, 0xf3, 0x31, 0xf8, 0x5d, 0x26, 0x61, 0x5b, 0x3b, 0xde, ++ 0x33, 0x2d, 0x6a, 0xb9, 0xd6, 0x6c, 0xd1, 0xc5, 0x2d, 0x85, 0x3e, 0x66, ++ 0xad, 0x1f, 0xde, 0xdf, 0x78, 0x28, 0xfe, 0xe1, 0x7e, 0x11, 0xf6, 0xa7, ++ 0xff, 0x5d, 0x09, 0x2d, 0x2f, 0xe4, 0xd4, 0x93, 0x8c, 0x7f, 0x16, 0xed, ++ 0x32, 0xa3, 0x7d, 0xb4, 0x68, 0xdb, 0x26, 0x8c, 0xf7, 0xd5, 0x6d, 0x3b, ++ 0x83, 0xf9, 0xb3, 0xa5, 0xbf, 0x79, 0x2a, 0x16, 0xe0, 0x50, 0xb7, 0x4b, ++ 0x34, 0xe6, 0x4f, 0x6d, 0x13, 0x7d, 0x16, 0xcc, 0xf3, 0x12, 0x8f, 0x59, ++ 0xd8, 0xf7, 0x39, 0x0c, 0x79, 0x4c, 0xb5, 0xad, 0xec, 0xfd, 0x8e, 0xda, ++ 0x16, 0x9e, 0x27, 0x14, 0x92, 0x3f, 0xb3, 0xf8, 0x37, 0x7b, 0x9e, 0xf5, ++ 0x50, 0xd0, 0x2c, 0x7e, 0xe6, 0x89, 0x58, 0xe0, 0xa7, 0x4f, 0x3b, 0xb6, ++ 0xc6, 0x02, 0x3c, 0xe9, 0x7c, 0x98, 0x7f, 0x34, 0xb1, 0x30, 0x42, 0x7e, ++ 0xd2, 0x85, 0xf2, 0x92, 0x5a, 0xd6, 0xf2, 0xbc, 0xa4, 0xf1, 0xf8, 0x7b, ++ 0x1d, 0xa1, 0x79, 0x49, 0x9f, 0xc2, 0x3f, 0xa8, 0x1e, 0x77, 0xf5, 0x31, ++ 0xe6, 0x79, 0x92, 0x6d, 0x4c, 0x6e, 0x51, 0xec, 0x17, 0x84, 0x7b, 0x1f, ++ 0x49, 0xb3, 0x5f, 0x16, 0x3f, 0xf5, 0xd5, 0xa3, 0x90, 0x47, 0x7b, 0x6a, ++ 0xe7, 0x67, 0x8f, 0xc2, 0xfe, 0x97, 0xfc, 0xe3, 0x8b, 0x47, 0x21, 0xaf, ++ 0x83, 0xec, 0x8d, 0x52, 0xc0, 0x9e, 0xa8, 0xfb, 0xd5, 0x3b, 0x98, 0x7f, ++ 0xa8, 0x8d, 0x1b, 0xdb, 0x87, 0xfb, 0x47, 0x4f, 0x3e, 0x81, 0xf9, 0x9b, ++ 0xa7, 0xdf, 0xb3, 0xa0, 0x5d, 0x78, 0x7a, 0xcf, 0x89, 0x4c, 0xb0, 0x17, ++ 0x4e, 0xef, 0xf8, 0x26, 0x05, 0xf2, 0x32, 0x97, 0xef, 0x29, 0xc7, 0xf8, ++ 0xc4, 0xf2, 0xdf, 0x96, 0xe2, 0x7b, 0xa2, 0x91, 0xfc, 0x4d, 0xa0, 0x4f, ++ 0xef, 0x45, 0xe4, 0x8f, 0x86, 0xe2, 0x63, 0x7f, 0xab, 0xe8, 0xb3, 0xd1, ++ 0x7d, 0x7e, 0xfe, 0xae, 0x05, 0xf9, 0xbf, 0x3b, 0xcf, 0xac, 0x65, 0x29, ++ 0xcb, 0xdf, 0x73, 0xf2, 0xfc, 0xb2, 0xed, 0xe1, 0xf3, 0x74, 0xb5, 0x7c, ++ 0xa8, 0xda, 0xd6, 0x6b, 0x26, 0x8e, 0x04, 0x79, 0xd7, 0xca, 0xf4, 0x7a, ++ 0x77, 0x7e, 0xd4, 0x85, 0xf2, 0xca, 0xde, 0xa6, 0x78, 0xbd, 0xfc, 0x22, ++ 0xf0, 0xb7, 0x9d, 0xe7, 0x0f, 0xb6, 0x8c, 0x0f, 0x9b, 0x57, 0xf6, 0x39, ++ 0xfc, 0x83, 0xe2, 0xa9, 0xa6, 0x8f, 0x31, 0xaf, 0xec, 0xab, 0xd6, 0xf9, ++ 0xbf, 0xfc, 0x39, 0x3c, 0x6b, 0x0d, 0xff, 0xbe, 0xb6, 0xc6, 0xd7, 0x17, ++ 0x82, 0x9b, 0x96, 0x07, 0x3c, 0xb4, 0x8f, 0x7a, 0x53, 0x1f, 0xe0, 0x8f, ++ 0x9d, 0xbf, 0xc6, 0x3c, 0x3e, 0xc0, 0x5b, 0xa5, 0x13, 0xf4, 0xff, 0x57, ++ 0x99, 0x10, 0xdf, 0x3c, 0x69, 0xf6, 0x63, 0xdc, 0xd0, 0xbf, 0xc7, 0xa2, ++ 0x40, 0xbe, 0xd7, 0xa2, 0x3d, 0x47, 0x91, 0x5f, 0x4e, 0xff, 0xf6, 0x30, ++ 0xe6, 0xd9, 0x12, 0x9e, 0x8f, 0x7b, 0x9a, 0x74, 0xff, 0xb1, 0xbc, 0x49, ++ 0x1e, 0xbb, 0xa8, 0xdb, 0x62, 0x67, 0xf9, 0x68, 0x1c, 0xfe, 0x90, 0xaf, ++ 0xe6, 0x8c, 0xc5, 0x76, 0x9e, 0x97, 0xc6, 0xe8, 0x58, 0xcb, 0x57, 0x8b, ++ 0x94, 0xa7, 0xf6, 0x64, 0x9f, 0x6c, 0x66, 0x5f, 0xf3, 0xfc, 0xe4, 0xa5, ++ 0xce, 0x0e, 0x59, 0xb1, 0x05, 0xf1, 0x05, 0xf8, 0x11, 0x0a, 0x01, 0x5f, ++ 0xc7, 0x0c, 0xf9, 0x7f, 0xda, 0xb9, 0x43, 0xe7, 0x53, 0x00, 0x0e, 0x57, ++ 0xe8, 0xf3, 0x2f, 0x23, 0xe5, 0x03, 0x72, 0x3b, 0xbd, 0x07, 0xbe, 0x98, ++ 0x5c, 0x3e, 0xbd, 0x89, 0xe7, 0x63, 0x76, 0xe7, 0x59, 0x12, 0x92, 0x9e, ++ 0x07, 0xf9, 0x41, 0x4c, 0x1f, 0xd6, 0x79, 0x85, 0xa3, 0xe1, 0xf0, 0xab, ++ 0xe5, 0x5f, 0x6e, 0x09, 0xc1, 0xaf, 0x76, 0xbe, 0x48, 0x7c, 0xa1, 0xf1, ++ 0xe7, 0x85, 0xf7, 0xfd, 0xcf, 0xc1, 0xe5, 0xa1, 0x3e, 0xec, 0x7d, 0x00, ++ 0x0d, 0x3e, 0xa7, 0xbe, 0x0d, 0x2f, 0xa7, 0x5f, 0xe4, 0xfc, 0x4e, 0xfd, ++ 0x96, 0xbd, 0x7d, 0x74, 0xef, 0xbd, 0xcc, 0xe2, 0x7e, 0x8b, 0x96, 0x77, ++ 0xa6, 0xed, 0xb7, 0xa9, 0x85, 0xe9, 0xe5, 0x53, 0xdb, 0x98, 0xdd, 0x18, ++ 0xca, 0xdf, 0xb5, 0x11, 0x7e, 0x57, 0xeb, 0x0d, 0xbe, 0x4e, 0xed, 0xae, ++ 0xf6, 0x41, 0x20, 0x87, 0x4e, 0xed, 0x7b, 0x9e, 0xd3, 0x9d, 0x97, 0xbf, ++ 0x87, 0x73, 0x4c, 0xf6, 0x70, 0xb9, 0xed, 0xd5, 0xcb, 0xed, 0x08, 0xbf, ++ 0x63, 0x76, 0xb4, 0x0f, 0xf3, 0x17, 0xa9, 0xbf, 0x1b, 0x76, 0xbe, 0xba, ++ 0xed, 0x67, 0xc2, 0xce, 0xf7, 0xa9, 0xa4, 0x5e, 0x0b, 0xfb, 0xff, 0xb4, ++ 0x83, 0xd9, 0x21, 0x9f, 0xb6, 0x88, 0x61, 0x7f, 0x0f, 0xa1, 0xbd, 0x8f, ++ 0xf1, 0x7d, 0xd5, 0x26, 0xbb, 0x8c, 0x7e, 0x97, 0x18, 0x1b, 0x8d, 0xf2, ++ 0x68, 0xb9, 0xbd, 0xf0, 0x5d, 0xf8, 0xbe, 0xdb, 0x72, 0xbb, 0x8c, 0xf9, ++ 0x0e, 0x0d, 0x2b, 0x79, 0x7e, 0xc4, 0x9d, 0x2e, 0xfc, 0x3d, 0x8f, 0x06, ++ 0xfb, 0x58, 0xfc, 0x1d, 0x88, 0x55, 0x00, 0x1f, 0x9d, 0x1f, 0x6a, 0x56, ++ 0xdc, 0xf8, 0xfb, 0x13, 0x66, 0x47, 0x55, 0x3e, 0xf8, 0x57, 0xa1, 0xef, ++ 0x77, 0xca, 0x49, 0x26, 0xe2, 0xd5, 0xe3, 0x5f, 0xf2, 0xa4, 0xe3, 0xf7, ++ 0xbb, 0xb2, 0xbf, 0x96, 0x40, 0xef, 0x74, 0xac, 0x30, 0xbe, 0x37, 0xd2, ++ 0x21, 0x29, 0x07, 0x12, 0xe9, 0x7c, 0x1d, 0x65, 0x82, 0x0b, 0xec, 0xdd, ++ 0x9e, 0x74, 0x66, 0x9c, 0xff, 0x6a, 0x55, 0x34, 0xc4, 0xcf, 0x20, 0x56, ++ 0x0d, 0xe7, 0x3a, 0xeb, 0x62, 0xdf, 0x45, 0xb3, 0x9b, 0x7c, 0x0a, 0xed, ++ 0x42, 0xec, 0x51, 0x1d, 0x0e, 0x74, 0xf4, 0x9c, 0xec, 0x77, 0xab, 0xe1, ++ 0xe7, 0xba, 0xe0, 0x3e, 0x7c, 0xdd, 0x0a, 0x6b, 0x3f, 0x78, 0x8f, 0xeb, ++ 0xff, 0x02, 0x2f, 0xb6, 0xd5, 0x84, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xb5, 0x7d, ++ 0x09, 0x7c, 0x54, 0xd5, 0xb9, 0xf8, 0xb9, 0x73, 0xef, 0x4c, 0x26, 0xcb, ++ 0x24, 0x93, 0x65, 0x60, 0x20, 0x2c, 0x37, 0xfb, 0x1e, 0x26, 0x10, 0x12, ++ 0xd0, 0x58, 0x26, 0x1b, 0x06, 0x09, 0x38, 0x22, 0x55, 0xd4, 0x80, 0x37, ++ 0x6c, 0x61, 0x0b, 0x89, 0x68, 0x6d, 0x6c, 0xfd, 0x97, 0x61, 0x31, 0x45, ++ 0xe5, 0xb5, 0xa1, 0x2e, 0x50, 0xa5, 0xcf, 0x01, 0xc1, 0xc7, 0xa3, 0xf8, ++ 0x1a, 0x16, 0x6b, 0xac, 0x51, 0x07, 0x08, 0x14, 0x2d, 0xda, 0xd0, 0xe2, ++ 0x93, 0xfa, 0x57, 0x1b, 0x94, 0x2a, 0x28, 0x98, 0x11, 0x94, 0xf2, 0x5a, ++ 0x2c, 0xff, 0xf3, 0x7d, 0xe7, 0x9c, 0xcc, 0xdc, 0x9b, 0x09, 0x84, 0xbe, ++ 0xfe, 0xa3, 0xfe, 0xae, 0xe7, 0xde, 0xb3, 0x7e, 0xfb, 0xf7, 0x9d, 0xef, ++ 0x9c, 0x89, 0x25, 0x2e, 0x89, 0xc8, 0x84, 0xd8, 0x5c, 0x8a, 0xb7, 0x27, ++ 0x9b, 0xe0, 0xdf, 0x15, 0xfa, 0x5f, 0x1c, 0xa1, 0x65, 0x2b, 0x2f, 0xa7, ++ 0xe0, 0xe3, 0x78, 0x7a, 0x09, 0x21, 0x31, 0xec, 0x15, 0xfd, 0x6e, 0xdf, ++ 0x6f, 0x92, 0x08, 0x89, 0xca, 0x26, 0xd9, 0x4a, 0x31, 0x21, 0x76, 0x12, ++ 0xe5, 0x92, 0x69, 0xf9, 0x89, 0x58, 0xf7, 0x61, 0x29, 0x96, 0x90, 0xf5, ++ 0x36, 0xad, 0x96, 0xd0, 0xe7, 0x15, 0xf8, 0x9b, 0xd4, 0xff, 0x49, 0x5c, ++ 0xca, 0x29, 0x18, 0xcf, 0x4a, 0xff, 0xb9, 0x92, 0x4a, 0xfb, 0x9b, 0x40, ++ 0xcb, 0xd6, 0xe0, 0xf8, 0xf1, 0x6e, 0x7d, 0x39, 0x91, 0x84, 0x94, 0x71, ++ 0x3e, 0x6e, 0x42, 0x86, 0xc0, 0x7b, 0xfa, 0xa7, 0x12, 0x32, 0x59, 0xa6, ++ 0x33, 0xa3, 0xf3, 0x88, 0xaf, 0x36, 0xf9, 0x22, 0x24, 0xfc, 0x5e, 0x9b, ++ 0x31, 0x24, 0x38, 0xdf, 0x78, 0x07, 0x71, 0xf9, 0xe1, 0xfb, 0xb4, 0x18, ++ 0x97, 0x97, 0xd6, 0x8f, 0x89, 0x61, 0xf3, 0x13, 0xf3, 0xa5, 0xf3, 0xf9, ++ 0x18, 0xe6, 0xa3, 0xd2, 0x7f, 0x70, 0x3e, 0xf9, 0x3d, 0x5e, 0x13, 0xc1, ++ 0x79, 0x7d, 0x1c, 0x3a, 0x0f, 0xfa, 0x27, 0x79, 0x6c, 0x38, 0xbf, 0x8f, ++ 0x0d, 0xf3, 0xfb, 0x38, 0x74, 0x7e, 0x05, 0xaa, 0x2d, 0xe9, 0xd3, 0x68, ++ 0x5a, 0x50, 0x88, 0x72, 0x85, 0xc2, 0x37, 0xc6, 0xda, 0x4d, 0x38, 0x9c, ++ 0xcf, 0x87, 0xc2, 0x99, 0x10, 0x2f, 0x51, 0x4a, 0x00, 0x9e, 0x02, 0xae, ++ 0xf4, 0x3b, 0xed, 0x27, 0x45, 0x7a, 0x52, 0xb9, 0x22, 0x01, 0x5c, 0xed, ++ 0x12, 0x49, 0xc3, 0xf1, 0x0c, 0xed, 0x46, 0xd8, 0xb1, 0x7f, 0x28, 0xd3, ++ 0x7e, 0xc7, 0xc0, 0x9a, 0x27, 0x12, 0x52, 0xe6, 0x94, 0xdc, 0xa7, 0xc6, ++ 0xd1, 0xff, 0xef, 0x4c, 0x22, 0x64, 0x18, 0x21, 0xa9, 0x2d, 0x95, 0xe4, ++ 0x13, 0x5a, 0x96, 0xda, 0x08, 0xc2, 0x27, 0x7d, 0x3d, 0xf1, 0x45, 0xd0, ++ 0xf9, 0xa5, 0x07, 0x4c, 0x58, 0x26, 0x6b, 0xa3, 0x7c, 0x19, 0xb4, 0x6d, ++ 0x84, 0x95, 0x78, 0x23, 0xc7, 0xd2, 0x7a, 0x0a, 0xf1, 0x9a, 0xc7, 0x42, ++ 0xaf, 0x3e, 0x42, 0xc6, 0x23, 0x70, 0x57, 0x9b, 0x68, 0x57, 0xca, 0x3a, ++ 0x42, 0x1e, 0xa3, 0xed, 0x3a, 0x03, 0x15, 0xa6, 0x05, 0x14, 0xa8, 0xed, ++ 0xf0, 0x89, 0xf6, 0x3f, 0x51, 0x75, 0x4f, 0x51, 0x69, 0xbd, 0xd6, 0xdb, ++ 0x34, 0xa7, 0xa9, 0x08, 0x96, 0x93, 0xd7, 0xd6, 0x55, 0x46, 0x08, 0x1d, ++ 0x2e, 0x47, 0x72, 0x11, 0x62, 0x5a, 0x95, 0xdb, 0x7d, 0x64, 0x24, 0x21, ++ 0x49, 0x50, 0xff, 0x06, 0xf8, 0x9e, 0xdb, 0xed, 0x8e, 0xc1, 0xef, 0xac, ++ 0x4c, 0x88, 0x9f, 0xd0, 0x75, 0xb5, 0x45, 0xf5, 0x95, 0xdd, 0x56, 0x27, ++ 0x2d, 0xa7, 0xb2, 0xf2, 0x9d, 0xbe, 0xdc, 0xb6, 0x75, 0xb4, 0xbf, 0x0f, ++ 0xd2, 0x3d, 0x77, 0xaa, 0x0e, 0xfa, 0xce, 0x6a, 0xcf, 0x05, 0xf8, 0x13, ++ 0x7f, 0x02, 0xae, 0x77, 0x40, 0xfa, 0xa2, 0x70, 0x25, 0x8e, 0xe0, 0x3c, ++ 0xb3, 0xb7, 0xf9, 0x2b, 0xa3, 0xe8, 0x24, 0x6e, 0x09, 0x50, 0x80, 0x52, ++ 0xfc, 0x67, 0xd0, 0x3e, 0xba, 0xf3, 0x01, 0x3f, 0xdd, 0x16, 0x20, 0x92, ++ 0xed, 0x31, 0xa2, 0xec, 0xb7, 0x10, 0xfa, 0xf4, 0xec, 0x3b, 0x66, 0xe9, ++ 0xa1, 0xcf, 0xc6, 0xf6, 0x63, 0xf8, 0xdd, 0x04, 0x65, 0xfa, 0x1c, 0x9d, ++ 0xe8, 0xaf, 0x4c, 0xa6, 0xeb, 0x7c, 0x50, 0xbd, 0xd1, 0xe3, 0xcc, 0xa1, ++ 0xfd, 0xed, 0xab, 0x77, 0x9a, 0xec, 0x84, 0xac, 0x54, 0x6f, 0xec, 0x56, ++ 0x1c, 0xa1, 0x70, 0x98, 0xa4, 0x83, 0x83, 0xb2, 0xfa, 0x26, 0x03, 0x1c, ++ 0x6e, 0xba, 0x2e, 0x38, 0xac, 0xf4, 0xdd, 0x84, 0x70, 0x18, 0xec, 0xba, ++ 0xcf, 0xa9, 0x9e, 0x1f, 0x01, 0x5e, 0xa6, 0x96, 0x9b, 0x88, 0x44, 0x07, ++ 0x2d, 0x3d, 0x11, 0xe3, 0x93, 0x18, 0x1f, 0x47, 0x7a, 0x0a, 0x82, 0xfd, ++ 0x6c, 0x31, 0x91, 0x45, 0xed, 0x31, 0xe1, 0xfa, 0x59, 0xc5, 0xf0, 0xcf, ++ 0xeb, 0x09, 0x3a, 0x1a, 0x88, 0x4e, 0xd2, 0x88, 0x3d, 0x17, 0xe8, 0xd4, ++ 0x48, 0x2f, 0x74, 0x7d, 0x35, 0xed, 0x14, 0x8e, 0x53, 0xb5, 0x7a, 0x4f, ++ 0x55, 0x62, 0x90, 0x4e, 0x89, 0x5d, 0x1b, 0x37, 0xa3, 0x00, 0xe6, 0x39, ++ 0xf7, 0x49, 0x98, 0xa7, 0x18, 0x77, 0x6a, 0xf9, 0x0a, 0x39, 0x95, 0xce, ++ 0xe7, 0x49, 0x8a, 0x23, 0xe8, 0xd7, 0xd1, 0xe2, 0x8d, 0xcc, 0xa4, 0x74, ++ 0xea, 0x70, 0x9b, 0x5c, 0xc0, 0xe7, 0xe7, 0x54, 0xed, 0xe7, 0x50, 0x3f, ++ 0x76, 0x56, 0xc0, 0x6f, 0xa6, 0x55, 0x4a, 0x89, 0x76, 0xbf, 0x94, 0x16, ++ 0xec, 0x5f, 0xd0, 0x7d, 0xeb, 0x6b, 0x32, 0xd2, 0x77, 0x6b, 0xbd, 0xc9, ++ 0xb7, 0x1a, 0xe5, 0x41, 0x8f, 0x04, 0xeb, 0x0e, 0xe2, 0xbd, 0xc7, 0x80, ++ 0xf7, 0x00, 0xc3, 0x7b, 0xc7, 0x49, 0xc4, 0xfb, 0xf2, 0xce, 0x93, 0x0c, ++ 0xef, 0x1d, 0xab, 0x2a, 0xa2, 0x8a, 0xa1, 0x2c, 0xd9, 0x23, 0x54, 0x58, ++ 0x4f, 0xa0, 0x08, 0xf0, 0xf9, 0x2b, 0xdf, 0x9d, 0x1e, 0x85, 0xe2, 0x73, ++ 0x74, 0x74, 0xa0, 0x15, 0xe8, 0xc1, 0x4c, 0xbe, 0xeb, 0xa9, 0xcd, 0x41, ++ 0xb8, 0xbf, 0x08, 0x74, 0xda, 0x0f, 0xee, 0x7c, 0x5e, 0x02, 0xfe, 0x03, ++ 0xe1, 0xad, 0xed, 0x48, 0xea, 0xe3, 0xf9, 0xb4, 0xaa, 0xf7, 0xa8, 0xc9, ++ 0x95, 0xa1, 0x06, 0xe1, 0x25, 0xea, 0x1d, 0x57, 0x2d, 0x58, 0x6f, 0x63, ++ 0xaa, 0xf6, 0x1b, 0x18, 0xa7, 0x69, 0x42, 0xcf, 0x61, 0xba, 0x52, 0xb2, ++ 0xe7, 0xc8, 0x1f, 0x62, 0x35, 0x3a, 0xdf, 0xd8, 0xa3, 0x33, 0xf6, 0x43, ++ 0xfb, 0xd8, 0x99, 0x14, 0x13, 0x6a, 0x70, 0xdc, 0xb6, 0xa3, 0xab, 0x2b, ++ 0x80, 0xfe, 0xdb, 0x80, 0xfe, 0x51, 0xce, 0x04, 0xbc, 0xf6, 0x98, 0xab, ++ 0xc1, 0x83, 0xf1, 0x45, 0x1f, 0x3c, 0xf6, 0x9d, 0x44, 0xf8, 0x98, 0xa0, ++ 0x4c, 0xdf, 0xef, 0xb4, 0x30, 0xba, 0x29, 0xeb, 0x90, 0xdc, 0x3e, 0xe0, ++ 0x8b, 0x68, 0x72, 0xaf, 0x87, 0x3e, 0xdf, 0x56, 0x4d, 0x38, 0xbf, 0x93, ++ 0xaa, 0xcc, 0x9f, 0x12, 0xc3, 0xe3, 0xd1, 0x03, 0xb2, 0x4a, 0xdb, 0x97, ++ 0xad, 0x35, 0x61, 0x7d, 0x07, 0x3c, 0xf3, 0x43, 0xd7, 0xbf, 0x16, 0xeb, ++ 0x9d, 0x54, 0x15, 0x2e, 0x77, 0x18, 0x3c, 0x04, 0x5e, 0x05, 0x1d, 0x51, ++ 0xc2, 0x89, 0xbe, 0x8d, 0xce, 0x79, 0x78, 0x96, 0xf6, 0x3e, 0xac, 0x3f, ++ 0x48, 0x37, 0x09, 0xd1, 0xa9, 0xf4, 0x7b, 0x69, 0xd7, 0xdc, 0xfb, 0x49, ++ 0x6a, 0xb0, 0xdd, 0x4f, 0x56, 0x12, 0xcf, 0x7c, 0x73, 0xb0, 0x1e, 0xa5, ++ 0x9f, 0x97, 0x75, 0xf4, 0x56, 0x60, 0x8e, 0x04, 0xb8, 0xf5, 0xd1, 0x0f, ++ 0xa5, 0x4b, 0x90, 0x2f, 0x46, 0xfc, 0xd0, 0x76, 0xa7, 0x19, 0x3f, 0x25, ++ 0x44, 0xab, 0xb4, 0xfe, 0xee, 0xae, 0x15, 0xb2, 0x96, 0x3f, 0x78, 0xbc, ++ 0x96, 0x44, 0x90, 0x66, 0x98, 0x7f, 0x49, 0x34, 0x69, 0xde, 0x43, 0xdb, ++ 0x97, 0xc4, 0xd1, 0x27, 0x94, 0x13, 0x79, 0x79, 0x28, 0x2f, 0x27, 0xf3, ++ 0xe7, 0x68, 0xfe, 0x3e, 0x8f, 0x95, 0xd3, 0x3e, 0x70, 0x99, 0x24, 0x5a, ++ 0xde, 0x02, 0x70, 0x07, 0x3c, 0xa4, 0x98, 0x18, 0x9c, 0x14, 0x7b, 0x2e, ++ 0xf0, 0x91, 0x29, 0x85, 0xc1, 0xb9, 0xcc, 0x19, 0x8d, 0xf2, 0x5f, 0xf0, ++ 0xab, 0x42, 0xc1, 0x19, 0x97, 0x00, 0x6a, 0x88, 0x78, 0xe1, 0x99, 0x1a, ++ 0x48, 0x35, 0x01, 0x1e, 0x05, 0xff, 0x2a, 0x01, 0x93, 0xdf, 0x46, 0xf5, ++ 0x5f, 0xaa, 0xa2, 0x9a, 0x5c, 0xf4, 0xfd, 0x5b, 0x2b, 0x35, 0x4f, 0x55, ++ 0xc6, 0xc0, 0xf2, 0xe5, 0x96, 0x1c, 0xd9, 0xe3, 0x0b, 0x23, 0x2f, 0xe2, ++ 0x52, 0x18, 0xde, 0xa9, 0x80, 0xf6, 0x9e, 0xca, 0x06, 0xed, 0x2c, 0x91, ++ 0x38, 0x20, 0x81, 0x61, 0x5a, 0x5c, 0x0a, 0x9d, 0x57, 0xa3, 0xb5, 0xe7, ++ 0x27, 0x33, 0xe8, 0xd7, 0xe5, 0x39, 0x17, 0x2c, 0x80, 0x9f, 0xd5, 0xd1, ++ 0xcb, 0x6f, 0xd4, 0xf2, 0x07, 0x1e, 0xc7, 0x38, 0x8f, 0xb7, 0x2e, 0xff, ++ 0x36, 0x1a, 0xe8, 0xab, 0xf3, 0x52, 0x44, 0x4d, 0x38, 0x79, 0x55, 0x03, ++ 0xeb, 0xa7, 0xe3, 0x1f, 0x59, 0x39, 0x0b, 0xdb, 0x3d, 0x1a, 0x15, 0x5b, ++ 0xc8, 0x95, 0x2a, 0xda, 0x2d, 0xdf, 0x41, 0xd1, 0x44, 0x9f, 0xe9, 0x4b, ++ 0x6a, 0x49, 0x21, 0xe0, 0xc3, 0xab, 0x24, 0x80, 0xfe, 0x8b, 0x96, 0x5c, ++ 0xdb, 0x09, 0xe2, 0x85, 0xe9, 0xc3, 0xa1, 0x29, 0xbe, 0xed, 0x29, 0x80, ++ 0x1f, 0x5f, 0x2d, 0x96, 0xf3, 0xd2, 0xc8, 0x76, 0x09, 0xf0, 0xa4, 0xad, ++ 0xb1, 0x41, 0x59, 0x4e, 0xc1, 0xfa, 0x14, 0x72, 0xc2, 0x3e, 0x92, 0xae, ++ 0x44, 0x60, 0xdf, 0xaa, 0x42, 0xed, 0x0d, 0x44, 0x79, 0x2a, 0xe0, 0xb3, ++ 0xf9, 0xa0, 0x0d, 0x84, 0x7d, 0x04, 0xad, 0xaf, 0xc2, 0x7b, 0xbd, 0x3d, ++ 0x45, 0xe7, 0xb7, 0x95, 0x8c, 0x01, 0x7c, 0xb7, 0x55, 0x25, 0x40, 0xbd, ++ 0x38, 0xde, 0xef, 0x25, 0x66, 0xe7, 0x08, 0xbb, 0xa8, 0x3a, 0xfd, 0x96, ++ 0x33, 0x12, 0xcc, 0x77, 0xb4, 0x57, 0x01, 0xb9, 0x4a, 0xd2, 0x52, 0x70, ++ 0x3e, 0xe5, 0xc4, 0xac, 0xb3, 0x8f, 0x4a, 0xb2, 0x28, 0xc8, 0x61, 0x7e, ++ 0x59, 0xb9, 0x3e, 0xf8, 0x5e, 0x69, 0x35, 0x7c, 0xe7, 0x74, 0x54, 0xdd, ++ 0xcf, 0x8e, 0x6a, 0x73, 0xcd, 0xa0, 0xf4, 0x3e, 0x35, 0x9b, 0xd2, 0x3f, ++ 0x7f, 0x7f, 0x81, 0xfe, 0x37, 0x3a, 0x82, 0xdc, 0x7b, 0x5b, 0x7e, 0x50, ++ 0xbe, 0x4f, 0x51, 0xef, 0xf2, 0x54, 0xe9, 0xec, 0x8f, 0x36, 0x17, 0xf0, ++ 0xe1, 0xef, 0xbe, 0x95, 0x91, 0xef, 0x8d, 0xf8, 0xd8, 0xca, 0xe9, 0xf1, ++ 0xc8, 0x4a, 0x8f, 0xa7, 0x8a, 0xf2, 0xdf, 0xaf, 0x22, 0x29, 0x3e, 0xe8, ++ 0x7a, 0x2b, 0x54, 0x69, 0xad, 0x4d, 0xbd, 0x36, 0xfc, 0x8c, 0x78, 0x33, ++ 0xc2, 0xef, 0x3b, 0x9d, 0x0b, 0xd1, 0x7e, 0x33, 0xc2, 0xab, 0xfc, 0x03, ++ 0x57, 0x55, 0x82, 0xda, 0x1f, 0x3e, 0x46, 0x78, 0x08, 0xf8, 0xd3, 0xf5, ++ 0xad, 0x07, 0xb8, 0x55, 0x67, 0xcb, 0xa8, 0xaf, 0x04, 0xbc, 0xfb, 0xc3, ++ 0x89, 0xd1, 0xc3, 0xef, 0x72, 0x68, 0x3d, 0x89, 0xd1, 0x0f, 0xc3, 0x87, ++ 0x44, 0x90, 0x5e, 0x04, 0xfd, 0xc4, 0xa5, 0x21, 0xfc, 0x4b, 0x80, 0xf6, ++ 0xe0, 0x7b, 0x74, 0x0a, 0x96, 0x8d, 0xf0, 0x35, 0xc2, 0x93, 0xca, 0x01, ++ 0x37, 0xd6, 0xe7, 0xf8, 0x3b, 0x0c, 0x70, 0xcb, 0x80, 0xaf, 0xee, 0xda, ++ 0xea, 0x21, 0x41, 0x38, 0x50, 0xba, 0xea, 0x8a, 0x0f, 0xa1, 0x2b, 0x01, ++ 0x87, 0x7e, 0x72, 0x23, 0x8b, 0x97, 0x39, 0xde, 0x85, 0xbd, 0x5c, 0xcd, ++ 0xfb, 0xa1, 0xf6, 0x32, 0xda, 0xc3, 0x95, 0x0e, 0x9b, 0x0b, 0xc0, 0x5f, ++ 0xd9, 0xc8, 0xe6, 0x5b, 0x99, 0x11, 0xb3, 0xd5, 0x9b, 0x82, 0xf8, 0xda, ++ 0x8a, 0xfc, 0xe3, 0xa7, 0x18, 0x29, 0xc1, 0x7f, 0xd9, 0xdf, 0x25, 0x66, ++ 0xe7, 0x52, 0xbb, 0x94, 0xd1, 0x67, 0xe7, 0xe4, 0x33, 0x60, 0x3f, 0x8f, ++ 0x8e, 0xd0, 0xd6, 0x02, 0x7f, 0x04, 0xa4, 0x78, 0xb2, 0x95, 0x20, 0xfc, ++ 0x3f, 0x36, 0xc0, 0x5f, 0x57, 0xae, 0x36, 0xd8, 0xcb, 0x46, 0x78, 0xfc, ++ 0x0a, 0xfe, 0x67, 0x62, 0x7f, 0xb8, 0x09, 0xba, 0xfb, 0x79, 0x0a, 0xb5, ++ 0xaf, 0xf3, 0x68, 0x71, 0x38, 0x19, 0x01, 0xf6, 0x6f, 0xe1, 0x2b, 0xc5, ++ 0x71, 0x20, 0xc7, 0x49, 0x67, 0x02, 0xca, 0x63, 0x23, 0x3d, 0x96, 0x9e, ++ 0xf0, 0xf4, 0xf5, 0xc3, 0xe9, 0x17, 0xe9, 0x53, 0x22, 0x5a, 0xdf, 0x7b, ++ 0x3b, 0xb5, 0x23, 0x3a, 0xb2, 0x1f, 0x79, 0x02, 0xcc, 0x9a, 0x1b, 0xad, ++ 0x6d, 0x32, 0xd0, 0xe1, 0x8d, 0xc4, 0xbd, 0xe6, 0x94, 0x15, 0xd6, 0x2f, ++ 0xe3, 0x3c, 0xc5, 0xbc, 0xfe, 0xee, 0xf4, 0xec, 0x4c, 0xa1, 0xf2, 0x66, ++ 0x62, 0x4f, 0xcd, 0x9a, 0x53, 0xa1, 0x7c, 0xc1, 0xc7, 0x17, 0xf0, 0xbe, ++ 0x89, 0xc3, 0xfb, 0x26, 0xe2, 0xdd, 0x2f, 0xc7, 0xc2, 0x53, 0xf9, 0xba, ++ 0xcf, 0x8e, 0x0f, 0xe9, 0x6f, 0x6f, 0x0a, 0xf7, 0x17, 0x92, 0x49, 0x32, ++ 0xac, 0xc7, 0x9e, 0xa2, 0x32, 0xf9, 0xce, 0xfb, 0x13, 0xeb, 0x1b, 0x9d, ++ 0x46, 0xfc, 0x12, 0xc2, 0xd9, 0xea, 0xdb, 0x2a, 0xc1, 0xfc, 0x89, 0xd7, ++ 0x92, 0x10, 0x1c, 0xcf, 0xcc, 0xd1, 0x94, 0x91, 0x31, 0xe3, 0xb5, 0x14, ++ 0x94, 0xc7, 0xcd, 0x04, 0xed, 0x65, 0x6a, 0x5e, 0x02, 0x12, 0xcb, 0xf8, ++ 0xf7, 0x32, 0x6b, 0x8c, 0x1f, 0xe6, 0x43, 0x02, 0xca, 0xd9, 0x3e, 0x3c, ++ 0x20, 0xdf, 0xd5, 0xd9, 0x01, 0xae, 0x14, 0x2e, 0xe4, 0x4a, 0x74, 0x70, ++ 0x7e, 0xbf, 0x4b, 0x91, 0x94, 0x4f, 0xb3, 0x83, 0xf3, 0x3b, 0xb7, 0xc3, ++ 0xea, 0x95, 0x81, 0x9f, 0x87, 0x69, 0xbf, 0x87, 0x71, 0xce, 0x4a, 0x47, ++ 0x0b, 0x91, 0x6f, 0x15, 0x7f, 0x26, 0xe8, 0x41, 0xe3, 0xf7, 0x0b, 0x1d, ++ 0x5d, 0xcb, 0xe1, 0x3b, 0xad, 0xb7, 0x10, 0xeb, 0xf1, 0x75, 0x2d, 0x05, ++ 0xa7, 0x91, 0xd2, 0x5d, 0xe0, 0xb5, 0x08, 0xdf, 0xd6, 0x94, 0xab, 0xd8, ++ 0xa1, 0x56, 0xaa, 0xc2, 0x42, 0xe4, 0x41, 0x59, 0x14, 0x93, 0x27, 0xd5, ++ 0x24, 0x20, 0x83, 0xdd, 0xd9, 0x19, 0xc9, 0xf8, 0xf9, 0xf5, 0xaf, 0x16, ++ 0x21, 0x3f, 0xb8, 0x89, 0x7d, 0x6d, 0x1e, 0xed, 0xef, 0xd0, 0xf9, 0xc9, ++ 0x47, 0x80, 0x9f, 0x2b, 0xa9, 0x78, 0x81, 0x7a, 0x93, 0x2e, 0xe9, 0xfd, ++ 0xb6, 0x6b, 0xd1, 0x69, 0x15, 0x09, 0xcc, 0x81, 0x76, 0xd5, 0x76, 0xb3, ++ 0xc1, 0x0f, 0xf4, 0xa2, 0xbe, 0x59, 0xcb, 0xe5, 0x9a, 0xb0, 0xd3, 0x4c, ++ 0xa9, 0xda, 0xb9, 0x14, 0x7c, 0x3f, 0xca, 0x07, 0x7a, 0xa6, 0xf3, 0xab, ++ 0xc9, 0x2a, 0xe0, 0x6d, 0x6b, 0xf6, 0xf8, 0x5b, 0x6e, 0xa7, 0x55, 0x52, ++ 0x73, 0xc6, 0xcd, 0x00, 0xf7, 0xcc, 0x64, 0xed, 0x36, 0x83, 0xfe, 0x9b, ++ 0xcd, 0xe9, 0x6b, 0x02, 0xd0, 0x97, 0x84, 0x56, 0x90, 0xa0, 0xaf, 0x8b, ++ 0xd0, 0x4f, 0xda, 0x3a, 0x03, 0x7d, 0xd9, 0x13, 0x74, 0x7e, 0xdd, 0x2d, ++ 0xc4, 0x8f, 0xeb, 0x2f, 0xcb, 0x36, 0xff, 0x4d, 0x37, 0x3f, 0x6e, 0x97, ++ 0x18, 0xed, 0xf5, 0xa0, 0x9d, 0xde, 0x16, 0xd6, 0xbf, 0x23, 0x5d, 0x0a, ++ 0xc9, 0xa6, 0x70, 0x9e, 0xc3, 0xe1, 0xbc, 0x36, 0xde, 0xe2, 0x05, 0xb9, ++ 0xa6, 0xdc, 0x27, 0xf9, 0x48, 0x0a, 0xcc, 0x97, 0x8c, 0x5a, 0x45, 0xe7, ++ 0x39, 0xbb, 0xd9, 0xac, 0xf3, 0x47, 0xe7, 0xc4, 0x2b, 0x88, 0xc7, 0x39, ++ 0xab, 0x22, 0x7d, 0x84, 0xf9, 0xdf, 0xce, 0x7a, 0x5a, 0xd6, 0xe8, 0xfb, ++ 0xc7, 0xa0, 0x98, 0xed, 0x76, 0x86, 0xda, 0x55, 0xa4, 0x25, 0xa4, 0x3d, ++ 0xd0, 0x43, 0x8c, 0x8a, 0xf4, 0x3b, 0xc7, 0xce, 0xde, 0x7d, 0x44, 0xfb, ++ 0x18, 0x96, 0x00, 0xfd, 0x9e, 0x72, 0xa0, 0x13, 0xef, 0x35, 0x9f, 0x0f, ++ 0xa5, 0x53, 0xe3, 0xf8, 0x03, 0xf6, 0x6b, 0x68, 0xb7, 0x56, 0x22, 0xb3, ++ 0xc0, 0x7e, 0x5a, 0x6b, 0x76, 0x3b, 0x5d, 0x21, 0xf6, 0xc7, 0xa8, 0x54, ++ 0x66, 0xbf, 0x9c, 0xb7, 0x57, 0x6d, 0x32, 0xa5, 0x0e, 0x6c, 0x97, 0x68, ++ 0xd6, 0x64, 0xb7, 0x92, 0x18, 0x2c, 0xf7, 0xc4, 0x5b, 0x67, 0xf9, 0xc2, ++ 0xd8, 0x31, 0xa2, 0x3f, 0x41, 0x27, 0x65, 0x1a, 0xf3, 0xcb, 0x07, 0xea, ++ 0x37, 0x3d, 0x50, 0x85, 0x76, 0x99, 0xe9, 0x49, 0xbf, 0x0c, 0xf6, 0x76, ++ 0x7a, 0x80, 0xa0, 0x7d, 0x5c, 0x16, 0x70, 0x9b, 0xe6, 0xe9, 0xec, 0x74, ++ 0xe6, 0x9f, 0xf6, 0xb3, 0xd3, 0xdb, 0xf7, 0xa3, 0x9d, 0xbe, 0x6c, 0xdf, ++ 0x7e, 0x66, 0xa7, 0xb7, 0xaf, 0x42, 0x7b, 0x7f, 0x19, 0xb5, 0xf7, 0x41, ++ 0xbe, 0x53, 0xbb, 0x11, 0x64, 0x25, 0x9b, 0x50, 0x3e, 0xda, 0xef, 0x7d, ++ 0x7e, 0x26, 0xe5, 0x2d, 0x52, 0xd6, 0x2e, 0xf5, 0xf9, 0xa1, 0x0a, 0x45, ++ 0x45, 0x5a, 0x1b, 0xab, 0x7f, 0xf7, 0xd6, 0xec, 0xf8, 0x47, 0xd3, 0xc1, ++ 0x4f, 0xd4, 0x9c, 0x66, 0xea, 0xf7, 0xdc, 0x9d, 0x5a, 0xb0, 0xc1, 0x4a, ++ 0xfd, 0x9e, 0xd6, 0x14, 0x12, 0x49, 0xa8, 0xdf, 0x33, 0x2b, 0xb5, 0xe0, ++ 0xb6, 0xf5, 0x13, 0x28, 0x35, 0x25, 0xb8, 0x25, 0x12, 0x8f, 0xe5, 0x0d, ++ 0x31, 0x13, 0x07, 0xef, 0xd7, 0xde, 0x9d, 0x9a, 0xbf, 0x01, 0xfc, 0xda, ++ 0x81, 0xfc, 0xcb, 0xea, 0x54, 0xf5, 0xaa, 0xfe, 0xe5, 0x07, 0xe9, 0x9e, ++ 0xbb, 0x53, 0x43, 0xe2, 0x02, 0x54, 0x3e, 0x86, 0xb5, 0x47, 0x32, 0x32, ++ 0x2a, 0xe6, 0x40, 0x3d, 0x21, 0x37, 0xca, 0xa2, 0x18, 0x7f, 0x3e, 0x6a, ++ 0xf2, 0xa7, 0xfd, 0x14, 0xfc, 0xad, 0xb7, 0x64, 0x02, 0xfa, 0xf4, 0x96, ++ 0x96, 0x79, 0xe8, 0x07, 0x4c, 0x6b, 0x59, 0xec, 0xa9, 0xa2, 0xf3, 0xe9, ++ 0x3d, 0x70, 0x39, 0x93, 0x98, 0x40, 0x5e, 0x32, 0xbc, 0x37, 0xa6, 0x32, ++ 0xbb, 0xa6, 0x29, 0x9a, 0xd9, 0x97, 0x4d, 0xd1, 0xb4, 0x1f, 0x2a, 0x6f, ++ 0xde, 0x74, 0x6a, 0x8d, 0xd0, 0x7f, 0x77, 0xf6, 0xf3, 0xeb, 0xc7, 0x52, ++ 0x7e, 0xa9, 0xeb, 0x90, 0x5d, 0xe0, 0x2f, 0x46, 0x66, 0x5d, 0x1e, 0x05, ++ 0xfc, 0x3f, 0x6d, 0xfc, 0xf3, 0x4f, 0x8e, 0xa5, 0xe3, 0x7c, 0x18, 0x50, ++ 0x30, 0xfe, 0xd0, 0x69, 0xa3, 0x74, 0x48, 0xdf, 0x7f, 0x48, 0x24, 0xb4, ++ 0x67, 0xcb, 0x8e, 0x45, 0x78, 0xf6, 0x51, 0xbc, 0x7c, 0xdf, 0x59, 0xde, ++ 0x96, 0x1a, 0xe2, 0x9f, 0x7c, 0xdf, 0x59, 0x85, 0x65, 0x52, 0x4b, 0x1d, ++ 0x2b, 0xca, 0x1f, 0x2b, 0xac, 0x8c, 0x2f, 0x3f, 0x24, 0xfb, 0xd3, 0x7e, ++ 0x4a, 0xc7, 0xf1, 0x36, 0x4b, 0x68, 0x07, 0x9c, 0x6f, 0x4e, 0x89, 0x03, ++ 0x3a, 0xe8, 0x34, 0xd3, 0xf5, 0x87, 0xd0, 0xe3, 0xea, 0x54, 0x05, 0xe9, ++ 0x6f, 0x35, 0xa7, 0xc7, 0xba, 0x4b, 0x32, 0x06, 0xcd, 0x3a, 0xcd, 0xfe, ++ 0xe4, 0x66, 0x5a, 0xbf, 0x4e, 0xf1, 0x9b, 0xc1, 0x0f, 0xac, 0xbb, 0x64, ++ 0xc1, 0xf7, 0x30, 0x0f, 0x98, 0x4f, 0x67, 0xa4, 0xbe, 0x9f, 0xc7, 0x79, ++ 0x3f, 0x8f, 0xf7, 0xf5, 0x43, 0xe1, 0x30, 0x0e, 0xea, 0x19, 0xfb, 0x51, ++ 0xd8, 0x7b, 0x89, 0xad, 0xcf, 0x88, 0x87, 0xd3, 0x29, 0x95, 0x3f, 0x85, ++ 0xf5, 0x7c, 0xdf, 0xe9, 0x6e, 0x43, 0xbc, 0x51, 0xf9, 0x05, 0xfa, 0xa2, ++ 0xac, 0xb8, 0xeb, 0x04, 0xd8, 0x11, 0xd7, 0xd6, 0x4b, 0x6e, 0x09, 0xf4, ++ 0x52, 0xd3, 0x65, 0xc9, 0x3f, 0x9a, 0xc2, 0xf3, 0xec, 0x3e, 0x33, 0xfa, ++ 0xf7, 0x67, 0xc1, 0x3f, 0xa4, 0xe3, 0x9d, 0xdb, 0x77, 0x70, 0xc8, 0x5c, ++ 0xfa, 0x6c, 0xdc, 0xfd, 0xc7, 0x58, 0xf0, 0x07, 0xb7, 0x70, 0x7c, 0x9d, ++ 0x53, 0xba, 0x63, 0x61, 0x7e, 0xcb, 0x5e, 0xa2, 0xfe, 0x0b, 0xda, 0x43, ++ 0xfe, 0x21, 0xf7, 0x60, 0xfb, 0x79, 0x25, 0x8f, 0xb1, 0x61, 0xac, 0xa1, ++ 0xfa, 0x7a, 0xec, 0xb7, 0x07, 0x93, 0x3d, 0x2c, 0x78, 0xa8, 0x42, 0x7c, ++ 0x4e, 0xd8, 0xa5, 0x37, 0x59, 0xbd, 0x3e, 0x98, 0x5f, 0xe7, 0x2a, 0x19, ++ 0xe5, 0x08, 0xd5, 0xe7, 0x22, 0x6e, 0x2a, 0x81, 0xfc, 0x9e, 0xb4, 0x4f, ++ 0x76, 0x47, 0xc6, 0xf6, 0xb7, 0x57, 0x5f, 0x4e, 0x35, 0x0b, 0x79, 0x6b, ++ 0x02, 0x3d, 0xf6, 0x80, 0x9d, 0x8d, 0x33, 0x90, 0x3c, 0x28, 0xbb, 0x94, ++ 0x48, 0x7c, 0x21, 0xf2, 0xa2, 0x4c, 0xf1, 0xcb, 0x30, 0xff, 0xb2, 0x4b, ++ 0x43, 0xf0, 0xfd, 0xb9, 0x23, 0xa9, 0x4f, 0xd4, 0x02, 0xdd, 0x12, 0xb3, ++ 0x0b, 0xcd, 0x44, 0x85, 0x74, 0xa1, 0xbd, 0x2c, 0x11, 0xf1, 0xd7, 0x95, ++ 0x4e, 0xd7, 0xf3, 0x3a, 0x2f, 0xbc, 0xb1, 0xef, 0xc2, 0xed, 0x37, 0x22, ++ 0x33, 0x52, 0xbd, 0x48, 0xeb, 0x7c, 0xc7, 0xaf, 0x25, 0xa1, 0xfd, 0x0c, ++ 0x21, 0xd2, 0x92, 0xa0, 0x5d, 0x38, 0xe9, 0x92, 0x3e, 0xee, 0x6a, 0xb4, ++ 0xa3, 0x85, 0x9e, 0xad, 0xe8, 0x2c, 0x5a, 0x9b, 0x4c, 0x00, 0xee, 0xea, ++ 0xed, 0x37, 0x02, 0x1d, 0x1e, 0x51, 0x90, 0x7f, 0x8c, 0x76, 0x76, 0x75, ++ 0x60, 0xf2, 0x00, 0xf6, 0xf4, 0x06, 0xa4, 0xa3, 0x3d, 0xfb, 0xd2, 0xa2, ++ 0x21, 0x2e, 0xb0, 0x91, 0xf3, 0x79, 0xd3, 0xbe, 0x0b, 0x93, 0x41, 0x3e, ++ 0x2d, 0x27, 0xfe, 0x3b, 0x6e, 0x4c, 0x82, 0xb8, 0x83, 0x6c, 0xf7, 0x93, ++ 0xab, 0xc5, 0xbb, 0xd6, 0xfe, 0x6e, 0x12, 0x1d, 0xff, 0x8d, 0x80, 0xa2, ++ 0x82, 0x3c, 0x78, 0x23, 0xd0, 0x65, 0x2d, 0xc4, 0xb2, 0x09, 0xe3, 0x1c, ++ 0x65, 0x6f, 0x97, 0xe5, 0x01, 0xff, 0x76, 0x06, 0x94, 0x1a, 0xf0, 0x5b, ++ 0xcb, 0xbe, 0xea, 0x8a, 0x9e, 0x97, 0x1f, 0xb4, 0x6b, 0x3a, 0x2f, 0x9b, ++ 0xf0, 0xfd, 0x1b, 0x97, 0x0f, 0xe0, 0x7b, 0xd1, 0x6f, 0x67, 0x20, 0x21, ++ 0x0f, 0xf4, 0xf3, 0x6e, 0x13, 0xf3, 0xb7, 0xbb, 0x0e, 0xff, 0x2d, 0x1a, ++ 0xe4, 0xeb, 0x1b, 0x97, 0xcf, 0x27, 0xa2, 0xdf, 0x2f, 0xec, 0x92, 0xfe, ++ 0x76, 0x35, 0xfa, 0x01, 0x95, 0x36, 0xb9, 0x2f, 0x0e, 0x1d, 0x6a, 0xbf, ++ 0x13, 0xb9, 0xec, 0xb8, 0x15, 0xfc, 0x8d, 0x38, 0x33, 0x91, 0x11, 0x0f, ++ 0xcc, 0x1f, 0xed, 0x67, 0x97, 0x7c, 0x40, 0xd6, 0xda, 0x48, 0x7f, 0xfb, ++ 0x44, 0xc0, 0x1f, 0xc8, 0x12, 0xf8, 0xa6, 0x9f, 0x5d, 0x1d, 0x84, 0xb7, ++ 0xce, 0xbe, 0xbe, 0x92, 0xca, 0xed, 0xe5, 0x91, 0x64, 0xec, 0x15, 0xb0, ++ 0x73, 0x2f, 0x27, 0x2e, 0x05, 0x7d, 0xdd, 0xdb, 0x19, 0x6d, 0x5f, 0x8d, ++ 0xf1, 0x29, 0x66, 0x57, 0xf4, 0x76, 0x7d, 0xfe, 0xb3, 0xa9, 0xf0, 0xfe, ++ 0xa8, 0x8c, 0xf1, 0xb6, 0xde, 0xcb, 0x32, 0xf2, 0xd5, 0x81, 0xd7, 0x97, ++ 0x8e, 0xee, 0x89, 0x09, 0x85, 0x7b, 0x2b, 0xe2, 0xef, 0xe2, 0xb0, 0xaf, ++ 0xbe, 0x7c, 0x95, 0xd6, 0xbf, 0x78, 0x28, 0x0a, 0xe3, 0xea, 0x44, 0x71, ++ 0xe5, 0x85, 0x8b, 0x9f, 0x04, 0xe3, 0xc9, 0xfe, 0xe1, 0x26, 0x27, 0x3c, ++ 0xbd, 0xc3, 0x4d, 0x13, 0x90, 0xed, 0x30, 0x5e, 0xf0, 0x9d, 0x60, 0xbc, ++ 0xc0, 0x91, 0x86, 0xf1, 0x82, 0xc0, 0x64, 0x50, 0x57, 0x99, 0x9b, 0x4f, ++ 0x5a, 0x20, 0xde, 0xb2, 0x31, 0xd5, 0x33, 0x34, 0x0d, 0xdb, 0xb7, 0x47, ++ 0xc3, 0xba, 0x17, 0x45, 0x31, 0xf9, 0xe4, 0x25, 0x15, 0xc9, 0xd4, 0x78, ++ 0x22, 0x2f, 0x1d, 0x31, 0x55, 0x00, 0xbd, 0x14, 0xaf, 0x52, 0x11, 0xef, ++ 0x3b, 0xcd, 0xd4, 0xc4, 0x02, 0xfe, 0xd8, 0xce, 0xfc, 0xfb, 0x9d, 0x54, ++ 0xde, 0x82, 0x5f, 0xb4, 0xb8, 0xbd, 0xcd, 0x92, 0x12, 0x82, 0xe7, 0xc5, ++ 0x14, 0x41, 0xb0, 0xbe, 0xd3, 0x66, 0xef, 0xa8, 0x84, 0x90, 0xf7, 0x3b, ++ 0xd2, 0x58, 0x3c, 0xe1, 0xf4, 0xa1, 0x25, 0xcf, 0x01, 0x9c, 0xbc, 0x7f, ++ 0x8a, 0x20, 0x19, 0x61, 0xec, 0xd3, 0x87, 0xd2, 0x98, 0x3c, 0xdc, 0x6b, ++ 0xf1, 0x4e, 0xdd, 0x05, 0xf5, 0x3e, 0x36, 0x11, 0x18, 0xaf, 0xeb, 0xf0, ++ 0x6f, 0x0e, 0x0f, 0xa7, 0x78, 0x5e, 0x7c, 0x42, 0x2d, 0x02, 0x3d, 0x30, ++ 0x2b, 0x4d, 0xc5, 0x7a, 0x1d, 0x47, 0x77, 0xb6, 0x0e, 0xa7, 0xf5, 0x3a, ++ 0x3e, 0x00, 0xed, 0x49, 0x4d, 0xf2, 0x6d, 0xf5, 0xb2, 0x89, 0x8e, 0xfb, ++ 0x2a, 0x51, 0x59, 0xdc, 0xef, 0xb8, 0x09, 0xe7, 0xdb, 0x17, 0x27, 0x25, ++ 0xee, 0x44, 0x58, 0xef, 0x1d, 0x69, 0x4c, 0x8e, 0xbd, 0x7a, 0x84, 0xd1, ++ 0xab, 0x18, 0xff, 0xd5, 0x28, 0xa6, 0xef, 0x26, 0xa7, 0x31, 0xf9, 0x52, ++ 0x96, 0xc6, 0xe2, 0x6e, 0x7b, 0x8e, 0x54, 0x24, 0xce, 0x45, 0xbe, 0xd2, ++ 0x26, 0x01, 0xdc, 0x9a, 0x4e, 0xf5, 0xb4, 0xc6, 0xaa, 0xc1, 0x38, 0xa1, ++ 0xb0, 0x0f, 0x27, 0x1e, 0xdf, 0x33, 0xb5, 0x80, 0xfe, 0xef, 0xc4, 0xb3, ++ 0x26, 0x3b, 0xa0, 0x4f, 0x3d, 0xbe, 0x55, 0x86, 0xf5, 0xaa, 0xa7, 0x09, ++ 0x89, 0x97, 0xfa, 0xc7, 0xb1, 0x68, 0x7f, 0x53, 0xd2, 0x1c, 0xc1, 0xfe, ++ 0x5e, 0x3d, 0xcb, 0xfa, 0xa3, 0xf3, 0x38, 0x00, 0x7c, 0x17, 0x58, 0x45, ++ 0xec, 0x5b, 0x91, 0xea, 0x3c, 0x8f, 0xe7, 0xd3, 0xf2, 0xab, 0xdd, 0x4a, ++ 0xc2, 0x63, 0x2a, 0xe2, 0x03, 0xf5, 0x81, 0xc0, 0x83, 0x58, 0x8f, 0x98, ++ 0x87, 0xda, 0x4e, 0xdc, 0x5b, 0x62, 0x90, 0x45, 0xdc, 0x7b, 0xae, 0x16, ++ 0x8f, 0xa6, 0x7e, 0x27, 0xf0, 0xdb, 0x38, 0x2e, 0x3f, 0xdf, 0x4d, 0x75, ++ 0xdf, 0x95, 0xc6, 0xec, 0xac, 0x51, 0x40, 0x77, 0xa7, 0x0f, 0x45, 0xa1, ++ 0x3d, 0xb6, 0x97, 0xc7, 0xb5, 0x89, 0xb3, 0x7e, 0x34, 0xc0, 0x4f, 0xe0, ++ 0xe9, 0x7b, 0xfc, 0x69, 0x9c, 0xcf, 0x40, 0xe3, 0x37, 0x73, 0x3a, 0x10, ++ 0xcf, 0x9d, 0x66, 0xd5, 0x8b, 0xf4, 0xf0, 0x12, 0xd3, 0xbb, 0x3b, 0x6d, ++ 0x7e, 0x6b, 0x1a, 0xc8, 0xbf, 0x57, 0xd2, 0xb0, 0xac, 0x7a, 0xbd, 0xd1, ++ 0x85, 0xf4, 0x7b, 0x53, 0x47, 0x86, 0x4b, 0x56, 0x91, 0x9e, 0x9b, 0x19, ++ 0xdd, 0x32, 0x3a, 0xbf, 0x89, 0xd3, 0xb9, 0xda, 0x1e, 0xb0, 0xa4, 0x84, ++ 0xe0, 0x61, 0x60, 0xf9, 0xc6, 0xe0, 0xde, 0x47, 0x3f, 0x4a, 0x3b, 0xd2, ++ 0x55, 0xc7, 0x09, 0x82, 0xfc, 0xb6, 0x64, 0xc7, 0x7d, 0x2c, 0x0e, 0x49, ++ 0xfc, 0xc9, 0x8c, 0x9f, 0xbc, 0xc9, 0xc0, 0x5f, 0xc0, 0x17, 0x8c, 0xcf, ++ 0xfc, 0xc3, 0x24, 0xf6, 0x8c, 0x05, 0x3e, 0x99, 0xd8, 0xb9, 0x65, 0x4d, ++ 0x32, 0x6d, 0xd7, 0x00, 0x74, 0x9f, 0x1f, 0x84, 0x83, 0x0a, 0x7c, 0x01, ++ 0x7c, 0x26, 0xd6, 0x69, 0x63, 0x76, 0xf2, 0xcf, 0x78, 0x59, 0x7c, 0x6f, ++ 0x4b, 0x63, 0x71, 0xc7, 0x6a, 0x39, 0x3f, 0xae, 0xe7, 0x2a, 0xf1, 0xbb, ++ 0x37, 0x56, 0x3a, 0x89, 0x12, 0x12, 0xbf, 0xfb, 0x19, 0x9f, 0xff, 0x62, ++ 0xb2, 0x01, 0xed, 0xd3, 0xc5, 0x97, 0xdb, 0xd0, 0x6e, 0x55, 0x9b, 0xd9, ++ 0x73, 0xf1, 0x03, 0xec, 0x99, 0xb9, 0xb9, 0xde, 0x02, 0xfa, 0x60, 0xf1, ++ 0x26, 0xc9, 0x1d, 0xce, 0xae, 0xb6, 0x73, 0xfc, 0x9d, 0xe3, 0x7c, 0x40, ++ 0x4c, 0x51, 0xc3, 0x89, 0x33, 0xf8, 0xdd, 0xc1, 0xf9, 0xe0, 0xcc, 0xbe, ++ 0x27, 0x0e, 0xc2, 0x3a, 0x29, 0xbd, 0x3e, 0x07, 0xf0, 0xbf, 0xa1, 0x63, ++ 0xc3, 0xd3, 0x00, 0x26, 0x41, 0xff, 0x67, 0xb6, 0x99, 0xb1, 0xbd, 0x90, ++ 0x23, 0xa2, 0xfd, 0x36, 0xde, 0xff, 0x4b, 0xc7, 0x19, 0xff, 0x4c, 0xdc, ++ 0x66, 0xae, 0xb8, 0x9b, 0xc2, 0x7b, 0xa2, 0x97, 0xd8, 0x21, 0x9e, 0xfe, ++ 0xea, 0xb6, 0xed, 0x32, 0xc8, 0xf7, 0x57, 0x81, 0x3f, 0x52, 0x98, 0xdc, ++ 0x00, 0xbd, 0x7c, 0xfa, 0xd0, 0x63, 0xd1, 0x3f, 0x00, 0x3a, 0x38, 0x69, ++ 0x22, 0x10, 0xb7, 0xdf, 0x6b, 0x21, 0x8b, 0x76, 0x87, 0xe0, 0xb7, 0x6b, ++ 0xcb, 0xcb, 0x3a, 0x79, 0xb0, 0x64, 0xc7, 0xaa, 0xa9, 0xd0, 0x4f, 0x69, ++ 0x4f, 0x82, 0x04, 0x7a, 0x40, 0xc8, 0x01, 0x81, 0xef, 0xbd, 0x16, 0xd7, ++ 0x14, 0x94, 0x27, 0xd3, 0x0d, 0xf2, 0xa4, 0x8a, 0xb5, 0x3f, 0x06, 0xf0, ++ 0xa4, 0xeb, 0x7a, 0x82, 0xcb, 0x93, 0x27, 0x6a, 0xa8, 0x3c, 0xa1, 0xaf, ++ 0xe2, 0xb7, 0xc5, 0x4b, 0xd0, 0xcf, 0x5e, 0x1e, 0x27, 0x36, 0xc2, 0xaf, ++ 0x8b, 0xe3, 0x53, 0xd0, 0xe3, 0x8d, 0x41, 0xb9, 0xdb, 0xc5, 0xe4, 0x6e, ++ 0x4f, 0x2c, 0x74, 0xbd, 0x7c, 0xda, 0x79, 0x8c, 0xd3, 0xf6, 0x8d, 0xc3, ++ 0xe9, 0xee, 0x89, 0x2a, 0x41, 0x77, 0x29, 0x12, 0xc0, 0x91, 0xda, 0xf9, ++ 0xa6, 0x74, 0x58, 0x37, 0x85, 0x0f, 0xd0, 0x3f, 0xb5, 0xf3, 0xef, 0x9d, ++ 0x91, 0x8f, 0x5c, 0x7a, 0x44, 0xc1, 0xfd, 0x21, 0xbe, 0xdf, 0x44, 0x56, ++ 0x0b, 0xfb, 0x47, 0xc7, 0xbf, 0x42, 0xce, 0xbd, 0x9b, 0xaa, 0x1d, 0x87, ++ 0xf1, 0x4b, 0xaa, 0x9a, 0xd7, 0x80, 0xff, 0x91, 0x58, 0xeb, 0x45, 0xba, ++ 0x3e, 0x23, 0x69, 0xa3, 0x13, 0xa8, 0xbe, 0x3a, 0x03, 0x7c, 0x1d, 0x46, ++ 0x2e, 0xbc, 0xca, 0xe5, 0xc8, 0x45, 0xb3, 0x36, 0xda, 0x1e, 0xe6, 0x7b, ++ 0x90, 0x8f, 0xc8, 0x70, 0xe0, 0x83, 0x45, 0x44, 0x33, 0xc1, 0x3a, 0xc8, ++ 0x66, 0xc9, 0x0e, 0x70, 0x15, 0xdf, 0xd5, 0xcd, 0x8c, 0xde, 0x3e, 0xe7, ++ 0xf0, 0x11, 0xef, 0x3f, 0x37, 0xc0, 0x6b, 0x12, 0xc0, 0x2b, 0x0d, 0xe1, ++ 0xf5, 0x39, 0xd7, 0x53, 0x16, 0x2b, 0x9d, 0x6f, 0xa6, 0x8f, 0xe9, 0x29, ++ 0x22, 0x55, 0x20, 0x3d, 0x12, 0xd3, 0x2d, 0xc3, 0x81, 0xdf, 0xce, 0x98, ++ 0x09, 0xd2, 0xcf, 0x19, 0x2a, 0x17, 0x01, 0x6e, 0x8b, 0xa3, 0xf4, 0xfe, ++ 0x89, 0x58, 0xd7, 0x37, 0x9c, 0xaf, 0x2e, 0xc6, 0xb3, 0x75, 0xec, 0xe5, ++ 0xe3, 0xfe, 0x09, 0x7c, 0x9e, 0xf1, 0x58, 0x0f, 0xed, 0x0a, 0x6f, 0xb9, ++ 0x09, 0xf7, 0x6b, 0x81, 0x3e, 0x90, 0xde, 0xa6, 0x27, 0xa0, 0xdd, 0x45, ++ 0x1d, 0x26, 0x05, 0xf9, 0xbc, 0x6f, 0x3f, 0xc2, 0x2f, 0x4b, 0x4c, 0x1e, ++ 0xc8, 0x30, 0x0f, 0x3b, 0xf8, 0x75, 0x18, 0x27, 0xda, 0x82, 0xfd, 0x2e, ++ 0xdd, 0xb5, 0x05, 0xe9, 0x26, 0xbe, 0xc6, 0x5e, 0x04, 0xfb, 0x47, 0x4f, ++ 0x28, 0xae, 0xc8, 0xf8, 0x90, 0x78, 0x6f, 0xd7, 0xf6, 0x8d, 0xe8, 0x4f, ++ 0x02, 0x3d, 0x01, 0x5f, 0x0e, 0x44, 0x8f, 0x8b, 0x80, 0x1e, 0x49, 0x18, ++ 0x3a, 0xf4, 0x51, 0x3a, 0xa4, 0xed, 0x12, 0x6a, 0x9a, 0x11, 0x8f, 0x14, ++ 0xbf, 0xf6, 0x74, 0xda, 0x6f, 0x7c, 0x95, 0x26, 0x03, 0xdd, 0x18, 0xf1, ++ 0x2b, 0xf6, 0x19, 0x05, 0x3c, 0xf6, 0x1a, 0xf6, 0x25, 0x67, 0xa6, 0x33, ++ 0xf8, 0xa4, 0xa4, 0x33, 0xfe, 0x54, 0xb9, 0xfc, 0x1a, 0x58, 0x4f, 0xe8, ++ 0xe5, 0x2d, 0xc5, 0x97, 0x9a, 0xee, 0xd0, 0xd3, 0x37, 0xe0, 0x4d, 0xf0, ++ 0x5b, 0x4c, 0x3a, 0x93, 0x4f, 0x03, 0xd1, 0xf9, 0x43, 0xe9, 0x76, 0xec, ++ 0xb7, 0xf5, 0xc3, 0x79, 0x4e, 0x90, 0x17, 0x62, 0x3f, 0x4a, 0xec, 0x2f, ++ 0x8b, 0xf1, 0xc7, 0xa6, 0x33, 0x7a, 0x1c, 0x68, 0x3f, 0xe9, 0x9c, 0xaa, ++ 0x15, 0xa5, 0x1b, 0xf6, 0x3b, 0xd5, 0xfc, 0x20, 0x9f, 0x54, 0x73, 0xfb, ++ 0x71, 0xc5, 0xf6, 0x08, 0xdc, 0xa7, 0xdf, 0x0d, 0x5f, 0x00, 0xee, 0x5d, ++ 0x51, 0xb8, 0x2f, 0xd1, 0x27, 0x07, 0x15, 0xe2, 0x06, 0x7c, 0x96, 0xa7, ++ 0xa7, 0xe0, 0x78, 0x02, 0xbf, 0x6a, 0x8b, 0x85, 0xa4, 0xd3, 0x71, 0x2f, ++ 0xa6, 0xd4, 0x77, 0xc5, 0xd0, 0x4f, 0x37, 0x77, 0x7b, 0x6b, 0x0b, 0xe8, ++ 0x3a, 0x76, 0x5b, 0xbc, 0x33, 0xa7, 0xa1, 0xdd, 0xed, 0x9a, 0x02, 0xfd, ++ 0x4f, 0xa9, 0x35, 0xd9, 0x21, 0x8e, 0x1d, 0xef, 0xb6, 0x4b, 0x10, 0x07, ++ 0x41, 0x12, 0x07, 0xbe, 0x38, 0xca, 0xc6, 0x21, 0xaa, 0x4b, 0x37, 0xef, ++ 0xa9, 0x1c, 0xee, 0x02, 0x4f, 0x02, 0x0e, 0x03, 0xe9, 0xab, 0x81, 0xf0, ++ 0xf3, 0x10, 0x87, 0x8f, 0x83, 0x7f, 0x37, 0xf2, 0x75, 0x06, 0xff, 0x6e, ++ 0x4e, 0x67, 0xf4, 0x7f, 0x6d, 0xbe, 0xf6, 0xca, 0x40, 0xf7, 0xb1, 0x44, ++ 0x5b, 0x2d, 0xc3, 0xfc, 0xcb, 0x98, 0x1c, 0xea, 0xe3, 0xeb, 0x32, 0x82, ++ 0xfb, 0x8d, 0x0b, 0xd2, 0xf5, 0x7c, 0x2d, 0xca, 0x61, 0xf8, 0x7a, 0x41, ++ 0x7a, 0x28, 0x5f, 0x4f, 0xe8, 0xd1, 0xf3, 0x35, 0xb5, 0x70, 0xb9, 0x3e, ++ 0x45, 0xfe, 0x72, 0x6c, 0x33, 0xbb, 0x99, 0x3f, 0xc9, 0xf8, 0xec, 0x62, ++ 0x24, 0x9b, 0xef, 0x8a, 0x74, 0xa6, 0x87, 0x1c, 0xa0, 0x3f, 0x28, 0xfe, ++ 0x1c, 0x5e, 0xb6, 0xef, 0x3a, 0x95, 0xd3, 0x19, 0xa5, 0xa0, 0x39, 0x00, ++ 0xef, 0xb6, 0x6d, 0x11, 0xb8, 0x9f, 0x20, 0xf8, 0x3e, 0x76, 0x26, 0xa9, ++ 0x30, 0xc3, 0xfe, 0x2d, 0xe8, 0x1b, 0xa8, 0x35, 0x53, 0x3b, 0x71, 0x13, ++ 0xec, 0xdb, 0x3a, 0x2d, 0x2a, 0xec, 0x23, 0x9f, 0x31, 0x07, 0x10, 0x4f, ++ 0x67, 0xa8, 0xa3, 0xda, 0x86, 0xf8, 0xf4, 0x60, 0x3e, 0xca, 0x99, 0x43, ++ 0x37, 0x30, 0x79, 0x30, 0xad, 0x4f, 0xff, 0xb8, 0x4d, 0x50, 0x7e, 0x7f, ++ 0x04, 0xee, 0x27, 0x54, 0xcb, 0x9d, 0x48, 0xd7, 0x2b, 0xaa, 0x09, 0xea, ++ 0x8f, 0xae, 0xed, 0xa5, 0x48, 0x07, 0x8b, 0x6a, 0x53, 0x25, 0xa0, 0xb3, ++ 0x25, 0x3b, 0xe2, 0x25, 0xf8, 0x9e, 0x50, 0x65, 0x37, 0xc9, 0x21, 0x72, ++ 0xb1, 0xb4, 0x45, 0x46, 0x7a, 0xa2, 0x74, 0xbb, 0x2e, 0x3d, 0x04, 0x7e, ++ 0xa5, 0xde, 0x66, 0x19, 0xe0, 0x32, 0x3a, 0x51, 0x73, 0x9a, 0xe3, 0xa9, ++ 0x9e, 0xdd, 0x36, 0x75, 0x46, 0x68, 0x5c, 0xe8, 0x49, 0x5a, 0x5e, 0xef, ++ 0x0c, 0xc6, 0x85, 0x68, 0xf9, 0x67, 0x31, 0xc3, 0x06, 0x1f, 0x17, 0xda, ++ 0x98, 0x7e, 0xcb, 0xcf, 0xd6, 0x8d, 0xa0, 0x4a, 0x24, 0xcd, 0xfd, 0x14, ++ 0x8c, 0x7b, 0x4e, 0xf5, 0x6c, 0x04, 0xbc, 0x94, 0x24, 0x37, 0x63, 0xbc, ++ 0x73, 0xb0, 0x79, 0x10, 0x4d, 0x3c, 0xae, 0xf4, 0xc1, 0x23, 0x6f, 0x6d, ++ 0xaf, 0xa7, 0xeb, 0xae, 0x7b, 0x34, 0xf0, 0x08, 0x7c, 0xbd, 0x17, 0xe2, ++ 0xae, 0xd9, 0x90, 0x3f, 0xc0, 0xe2, 0xae, 0x4d, 0x9d, 0xc7, 0x30, 0x1e, ++ 0xdb, 0xc9, 0xf9, 0xf9, 0xef, 0x4e, 0xcf, 0x0b, 0x30, 0xee, 0xec, 0xe6, ++ 0x29, 0xfa, 0xf8, 0x6b, 0x60, 0x70, 0xe3, 0x26, 0x71, 0xbe, 0x25, 0x1f, ++ 0x10, 0x84, 0x7f, 0x92, 0xa7, 0x59, 0x86, 0xb8, 0x84, 0x90, 0x0b, 0xfb, ++ 0xd2, 0x13, 0x84, 0xff, 0x28, 0xc1, 0xfe, 0x9b, 0xe0, 0x07, 0x90, 0x2b, ++ 0x60, 0x7f, 0x8a, 0x3c, 0x08, 0x88, 0x87, 0xd9, 0x12, 0x82, 0x72, 0x19, ++ 0xca, 0x71, 0x21, 0x7a, 0x75, 0x7d, 0x2d, 0xb5, 0x83, 0xc2, 0xf0, 0xd9, ++ 0xc1, 0xf4, 0x98, 0xb0, 0x72, 0x90, 0x74, 0xfe, 0xfd, 0xd7, 0x3f, 0xa0, ++ 0xfe, 0x7e, 0x13, 0x7c, 0x62, 0x72, 0xf1, 0x60, 0x7a, 0x88, 0xde, 0x7f, ++ 0xa2, 0xf6, 0xe3, 0x21, 0x1a, 0x8b, 0x7b, 0x60, 0xbc, 0xe9, 0x7e, 0xee, ++ 0x43, 0x3e, 0xb7, 0xda, 0xf5, 0xfb, 0x2c, 0x90, 0x43, 0xef, 0xc8, 0x28, ++ 0xff, 0x8b, 0x22, 0x2c, 0x5e, 0x09, 0xf6, 0x87, 0xdc, 0x44, 0xb5, 0x0f, ++ 0xe1, 0xfd, 0x01, 0x9b, 0x74, 0x4a, 0x7e, 0x1b, 0xf5, 0x3f, 0x9b, 0xfe, ++ 0x26, 0x11, 0x37, 0xc4, 0xcf, 0xfe, 0x26, 0xe3, 0xf3, 0xb9, 0x1f, 0x79, ++ 0x6a, 0x52, 0xc0, 0x9f, 0xef, 0x30, 0xb9, 0xa8, 0x25, 0x00, 0xf9, 0x14, ++ 0x48, 0xc7, 0xae, 0xd1, 0xc4, 0x67, 0xa5, 0xf4, 0xd7, 0xce, 0xf7, 0x6b, ++ 0xcb, 0x0f, 0xc6, 0xb8, 0xcd, 0xf4, 0x7d, 0xaf, 0x64, 0x45, 0xf9, 0xd7, ++ 0xbb, 0x3f, 0xca, 0x0b, 0x7c, 0xdd, 0x6b, 0x33, 0x61, 0x5c, 0xb9, 0xeb, ++ 0xb5, 0x08, 0x84, 0xeb, 0x85, 0xf4, 0x28, 0xee, 0x5f, 0xfb, 0x74, 0x7e, ++ 0xb8, 0xd8, 0xff, 0x88, 0x8c, 0xe8, 0xf9, 0x43, 0x19, 0x6d, 0xbf, 0x35, ++ 0x92, 0xf5, 0xbb, 0x35, 0x92, 0xc5, 0xe9, 0xb6, 0x3e, 0x9a, 0x19, 0x07, ++ 0xf6, 0xe7, 0x40, 0xfb, 0xe3, 0x65, 0x2d, 0x69, 0x18, 0xe7, 0x13, 0xf1, ++ 0xc7, 0xd4, 0x80, 0x6a, 0x62, 0x49, 0x64, 0x6c, 0x1c, 0x25, 0x40, 0x70, ++ 0x7d, 0x62, 0xbf, 0x7c, 0x13, 0xe4, 0x6b, 0x14, 0x0f, 0x9c, 0xaf, 0xf1, ++ 0xd7, 0xf4, 0xbe, 0x7c, 0x8d, 0x00, 0xd0, 0x53, 0xd3, 0xac, 0x9e, 0xc3, ++ 0x30, 0x47, 0xa3, 0x1f, 0x36, 0xe4, 0xe8, 0xc7, 0xfb, 0xa1, 0x9f, 0x21, ++ 0x2d, 0x2c, 0x4c, 0xb0, 0xe9, 0xe8, 0x0a, 0x09, 0xd6, 0xb9, 0xa9, 0x2e, ++ 0xbc, 0x1f, 0x26, 0xe8, 0x68, 0x13, 0x8f, 0x7b, 0x85, 0xe4, 0x45, 0x7c, ++ 0xab, 0xd3, 0x2f, 0xf5, 0x09, 0xd1, 0xa9, 0x21, 0xf2, 0x53, 0xb4, 0x7b, ++ 0x9a, 0xe7, 0x45, 0x94, 0x76, 0xcd, 0xdd, 0x0b, 0x76, 0x1e, 0xe5, 0xef, ++ 0x73, 0xa1, 0xfc, 0x3d, 0xb5, 0xe0, 0x91, 0xc8, 0x70, 0xfb, 0xf3, 0x9e, ++ 0x96, 0x1f, 0x62, 0x5c, 0x74, 0x20, 0xfa, 0xf7, 0x98, 0x88, 0x16, 0x2e, ++ 0xee, 0x37, 0x3a, 0x83, 0xcb, 0x5b, 0x25, 0x30, 0x1c, 0xed, 0xc1, 0x37, ++ 0x2e, 0x46, 0xa9, 0x61, 0xf2, 0x25, 0x3c, 0xaf, 0x99, 0x1c, 0x00, 0x17, ++ 0x11, 0x9f, 0xe9, 0x3f, 0xfe, 0x8f, 0x70, 0xfc, 0x61, 0x19, 0x7d, 0xfb, ++ 0x7f, 0xc3, 0x07, 0xb3, 0xff, 0x67, 0x9c, 0x77, 0xb7, 0x99, 0x8c, 0x0c, ++ 0xa7, 0x57, 0x04, 0x9e, 0x8d, 0xe3, 0x85, 0x69, 0x3f, 0xdb, 0x15, 0xd2, ++ 0xde, 0x63, 0x21, 0xda, 0xee, 0x98, 0xfe, 0xed, 0x84, 0xdd, 0xeb, 0x91, ++ 0xf8, 0xfe, 0xee, 0x87, 0x04, 0xf5, 0xab, 0xa0, 0x13, 0x0a, 0xf7, 0x71, ++ 0x19, 0xf4, 0x7b, 0xe1, 0xdb, 0xf3, 0xc6, 0x45, 0x41, 0xc2, 0xa1, 0xb5, ++ 0x59, 0x06, 0x79, 0x70, 0xa1, 0xa3, 0x2b, 0x19, 0xe2, 0x56, 0x03, 0xf9, ++ 0x87, 0x62, 0x3e, 0xf4, 0x2f, 0x23, 0x5c, 0xbc, 0x85, 0x8e, 0xe7, 0x09, ++ 0x87, 0x87, 0x69, 0x19, 0x4c, 0xbf, 0x7a, 0xcc, 0xcc, 0x0e, 0x95, 0xca, ++ 0x0f, 0xdd, 0x03, 0xf3, 0xf2, 0x7c, 0x65, 0x91, 0x22, 0x42, 0xe8, 0x6c, ++ 0x22, 0xaf, 0x67, 0xdc, 0xc7, 0xec, 0xfc, 0xea, 0xbf, 0xc7, 0xa1, 0x9c, ++ 0x34, 0xfb, 0x93, 0xc3, 0xc1, 0xcf, 0xb8, 0xbf, 0x39, 0x11, 0x82, 0x93, ++ 0x4c, 0xdf, 0xb1, 0x71, 0x39, 0x5c, 0x5a, 0xcb, 0x49, 0x45, 0x44, 0x12, ++ 0xc6, 0x0b, 0xc8, 0x56, 0x15, 0xfc, 0x40, 0x26, 0x2f, 0xd5, 0x16, 0x82, ++ 0x7c, 0x3e, 0x46, 0x72, 0xe3, 0xba, 0xeb, 0x20, 0xe8, 0xe2, 0x00, 0x3a, ++ 0xef, 0xc6, 0x3c, 0xc8, 0x0b, 0x47, 0x65, 0xac, 0x57, 0x78, 0x9f, 0xea, ++ 0x03, 0xbf, 0x89, 0xea, 0x85, 0xbb, 0x01, 0x7e, 0xa5, 0x44, 0xdb, 0x6b, ++ 0x4a, 0x0b, 0xc2, 0x4b, 0xd0, 0x43, 0xeb, 0x8b, 0xd4, 0x4e, 0xd1, 0xc5, ++ 0xad, 0x18, 0xff, 0x08, 0xff, 0x75, 0x24, 0x8f, 0xff, 0x50, 0x55, 0xe3, ++ 0x0e, 0xc5, 0xdf, 0xd0, 0x59, 0x94, 0x54, 0x43, 0xe4, 0xfe, 0x30, 0xcd, ++ 0x4a, 0x94, 0x90, 0x38, 0x5b, 0xf2, 0x22, 0xbb, 0xae, 0x3c, 0xb2, 0xd9, ++ 0xa9, 0xab, 0xef, 0xf4, 0xfa, 0x25, 0xe0, 0x2b, 0x67, 0x8b, 0xaa, 0x7b, ++ 0x1f, 0x94, 0x57, 0x6c, 0xbd, 0x23, 0xbd, 0x64, 0x0b, 0xe8, 0xff, 0x4d, ++ 0xa4, 0x07, 0xd7, 0x37, 0x8a, 0xcf, 0x67, 0x8c, 0xa4, 0x21, 0x7d, 0x5c, ++ 0x38, 0xfa, 0x49, 0x02, 0xc4, 0x25, 0x7f, 0xc0, 0xf9, 0x87, 0xae, 0xb7, ++ 0x05, 0xd7, 0xdb, 0xa2, 0x5d, 0x08, 0xa5, 0x0f, 0xb1, 0xde, 0x6b, 0xad, ++ 0xeb, 0x83, 0x95, 0x74, 0x3e, 0x94, 0xef, 0x3f, 0x02, 0xff, 0x9c, 0x3e, ++ 0x67, 0x3f, 0x70, 0x52, 0x1a, 0x8a, 0x70, 0xb7, 0x83, 0x3a, 0xa0, 0x7a, ++ 0x91, 0xb5, 0x1b, 0xf9, 0xf0, 0x31, 0xf4, 0x23, 0x47, 0x36, 0x77, 0xa3, ++ 0x1d, 0x3f, 0xa7, 0x65, 0xbf, 0x04, 0xfa, 0x8b, 0xca, 0x0d, 0x6c, 0xb7, ++ 0x69, 0xa5, 0x15, 0x9f, 0xcf, 0xac, 0xb4, 0xa3, 0x9f, 0x2f, 0xf0, 0x3b, ++ 0x82, 0xd6, 0x83, 0x3c, 0x25, 0x6f, 0x05, 0xc9, 0x86, 0x7d, 0x81, 0x81, ++ 0xf4, 0xd3, 0xc6, 0x8c, 0x41, 0xeb, 0xa7, 0x8d, 0x19, 0x61, 0xf4, 0x93, ++ 0xc9, 0x1a, 0x78, 0x13, 0xf6, 0xc1, 0x1b, 0x3b, 0x65, 0x15, 0xe8, 0x60, ++ 0xcd, 0xc3, 0x09, 0x98, 0xff, 0xf2, 0x5c, 0xbb, 0x84, 0xfb, 0x2e, 0x07, ++ 0x3b, 0x59, 0xfe, 0xdf, 0x73, 0xad, 0x51, 0xa8, 0x47, 0xc4, 0xb8, 0x5f, ++ 0xbe, 0x14, 0x87, 0xfb, 0x3f, 0x5f, 0xf2, 0x7d, 0x40, 0xd2, 0x15, 0x8f, ++ 0xf4, 0xdd, 0x14, 0xcf, 0x71, 0xb2, 0x36, 0x1e, 0xf7, 0xc9, 0x7b, 0xf9, ++ 0x3e, 0x64, 0x47, 0xba, 0xf6, 0x1f, 0x19, 0x21, 0xf2, 0xe0, 0xb9, 0xce, ++ 0x6f, 0x22, 0x41, 0x7f, 0xe4, 0x89, 0x3c, 0x5b, 0x83, 0xde, 0x01, 0x41, ++ 0x2c, 0xd1, 0xf6, 0xe0, 0x13, 0x01, 0x1d, 0xb7, 0xa6, 0x14, 0xad, 0x93, ++ 0x61, 0x5d, 0x77, 0x68, 0xe3, 0x22, 0x65, 0xe4, 0xf7, 0xdd, 0x8c, 0x5e, ++ 0x99, 0x7e, 0xfa, 0xe5, 0xae, 0x0a, 0x93, 0x16, 0x82, 0x9f, 0x0b, 0x1d, ++ 0x5f, 0xcf, 0x39, 0xa0, 0xf6, 0xdf, 0x5f, 0x12, 0xfb, 0x50, 0x62, 0x7f, ++ 0xea, 0x4d, 0xa7, 0xf6, 0x6a, 0x46, 0x88, 0xbc, 0x36, 0xee, 0x3b, 0x19, ++ 0xf7, 0x4b, 0xe4, 0x58, 0x2b, 0xe6, 0x69, 0xbb, 0xe4, 0x28, 0x97, 0xac, ++ 0xd7, 0xb7, 0x48, 0x87, 0x6b, 0x32, 0x98, 0x3e, 0x5d, 0xb3, 0x3f, 0x0a, ++ 0xe1, 0xb8, 0x26, 0x23, 0x06, 0xf7, 0x7b, 0xe9, 0x7c, 0x8f, 0xc0, 0x38, ++ 0x5d, 0x36, 0x0b, 0x19, 0x46, 0xdf, 0x5f, 0x38, 0x11, 0x83, 0xf5, 0xc4, ++ 0xfc, 0xe9, 0x7c, 0x0b, 0x8f, 0x86, 0x99, 0x6f, 0x93, 0x29, 0x30, 0xe7, ++ 0x80, 0xa4, 0x9b, 0xef, 0xb1, 0xab, 0xcf, 0x57, 0x9f, 0xcf, 0x2c, 0xe6, ++ 0xd7, 0x87, 0x1f, 0x1e, 0x2f, 0x90, 0x6d, 0x0a, 0xae, 0xa3, 0x97, 0x44, ++ 0xb9, 0x00, 0xaf, 0xed, 0x16, 0xd7, 0x09, 0x0d, 0xf4, 0xef, 0x3b, 0x51, ++ 0x2c, 0x7f, 0x8a, 0xe3, 0x6f, 0x39, 0xe7, 0xcd, 0x5e, 0x8a, 0x2f, 0x89, ++ 0xe2, 0xab, 0xb7, 0xe3, 0x42, 0x24, 0xd0, 0xf1, 0xc1, 0x74, 0xed, 0x24, ++ 0xcc, 0x43, 0x1e, 0x19, 0x88, 0x05, 0xff, 0xe5, 0x60, 0xe7, 0x85, 0x1c, ++ 0xe0, 0x97, 0x81, 0xf6, 0x0d, 0x95, 0x8c, 0x8a, 0xbf, 0x00, 0xbe, 0x20, ++ 0xff, 0x0f, 0xf1, 0x66, 0xd7, 0x2e, 0xec, 0x22, 0x8c, 0x2f, 0xb5, 0xab, ++ 0xb4, 0xcb, 0xc8, 0xa8, 0x38, 0x0b, 0xf5, 0xaf, 0x03, 0x3e, 0xdf, 0x5c, ++ 0x0f, 0x7c, 0x9a, 0x94, 0x98, 0x75, 0xa1, 0xf6, 0x97, 0xc4, 0xe5, 0xb3, ++ 0x91, 0x1e, 0xa5, 0xce, 0xfd, 0xff, 0x03, 0xfb, 0x01, 0x94, 0x1f, 0x31, ++ 0x1f, 0xd5, 0x3b, 0x8a, 0xf8, 0xd6, 0x50, 0xb8, 0xb5, 0x16, 0x70, 0xba, ++ 0x9c, 0x49, 0x54, 0x16, 0x9f, 0xd1, 0xd3, 0x4b, 0x47, 0xba, 0xc7, 0x9c, ++ 0xe9, 0x08, 0xf2, 0xf1, 0x55, 0xe0, 0x13, 0x09, 0xf5, 0x7e, 0x99, 0xee, ++ 0x89, 0x86, 0x27, 0xcc, 0x23, 0x79, 0x2c, 0xca, 0x29, 0x1b, 0x94, 0xa9, ++ 0x5e, 0xdb, 0x6b, 0x49, 0x0d, 0xda, 0x5b, 0xa3, 0xd3, 0x98, 0xdc, 0x0b, ++ 0xc4, 0x13, 0xcc, 0x5f, 0x31, 0xee, 0xf7, 0x66, 0x64, 0xcc, 0x48, 0xca, ++ 0xa4, 0x70, 0x4b, 0xcd, 0x56, 0x4d, 0xf6, 0xfc, 0xeb, 0xe2, 0x87, 0x91, ++ 0x99, 0x57, 0x85, 0x9f, 0x1f, 0xe9, 0xa2, 0x91, 0xc3, 0xa9, 0x11, 0xf6, ++ 0x19, 0x29, 0x5c, 0xc8, 0x3e, 0xf3, 0x59, 0x5d, 0xbe, 0x80, 0x01, 0x0e, ++ 0x07, 0xd3, 0x3d, 0x59, 0x0c, 0x0e, 0x41, 0x3a, 0x5b, 0xa3, 0x5e, 0x15, ++ 0x1e, 0x79, 0x0c, 0x1e, 0x5a, 0x21, 0xac, 0xc3, 0x66, 0xa6, 0xf4, 0x02, ++ 0x40, 0x99, 0x50, 0xef, 0xc4, 0xbc, 0x18, 0xd5, 0x7d, 0x37, 0xec, 0x7f, ++ 0xee, 0x5c, 0xc5, 0xe0, 0xd0, 0xfb, 0x22, 0x83, 0xc3, 0xee, 0x2e, 0x13, ++ 0xd2, 0xf5, 0x16, 0x92, 0x8b, 0xfc, 0x99, 0x6b, 0x3a, 0x3f, 0x07, 0xfa, ++ 0xa7, 0xf2, 0x67, 0x02, 0xf4, 0x53, 0xdc, 0xdd, 0x66, 0x82, 0x7c, 0xc2, ++ 0x0c, 0x9f, 0x6a, 0x82, 0xb8, 0x72, 0x4e, 0x77, 0xbb, 0xc9, 0x74, 0x75, ++ 0xba, 0x2d, 0xcb, 0x44, 0x7d, 0xa1, 0x4d, 0xca, 0x64, 0xf6, 0xc5, 0xfd, ++ 0x80, 0x87, 0xbc, 0x5d, 0x2c, 0x1e, 0x73, 0x15, 0xba, 0xad, 0xcc, 0x1c, ++ 0x7f, 0x5d, 0x70, 0xaf, 0xcd, 0x1c, 0x3f, 0x78, 0x39, 0x44, 0xe9, 0xca, ++ 0x13, 0x4a, 0x57, 0x83, 0xcd, 0x4b, 0xa2, 0xf4, 0x41, 0x92, 0x13, 0xfa, ++ 0xf7, 0x47, 0x48, 0x0f, 0xc6, 0xfd, 0xf7, 0xbf, 0x12, 0x81, 0xf2, 0x7e, ++ 0xf9, 0x1e, 0x09, 0xe5, 0xd3, 0xf2, 0xd7, 0x3f, 0x9b, 0x03, 0xf0, 0x5d, ++ 0xfe, 0x9b, 0x08, 0x24, 0xca, 0xaa, 0xdf, 0x44, 0xe2, 0xf7, 0xf3, 0xfb, ++ 0xd8, 0xf7, 0x2f, 0xcb, 0xc3, 0xef, 0x4f, 0xdf, 0x95, 0x99, 0x80, 0x7a, ++ 0xb6, 0xb1, 0xfd, 0x3e, 0x4f, 0xa8, 0x7e, 0x17, 0x76, 0xc3, 0x4f, 0xdd, ++ 0xe7, 0xed, 0xe9, 0x72, 0x70, 0x9f, 0x2f, 0x71, 0x1a, 0x3b, 0x6f, 0xb2, ++ 0x26, 0x52, 0xe4, 0x9b, 0xb2, 0xfd, 0xbe, 0x58, 0x4e, 0x67, 0x89, 0x23, ++ 0x3d, 0x6e, 0xd0, 0x53, 0x89, 0xd5, 0x2c, 0x9e, 0x14, 0x1b, 0xb3, 0x10, ++ 0xf7, 0xfb, 0xfa, 0x9f, 0x2b, 0x61, 0x7c, 0xeb, 0xe0, 0xed, 0xec, 0x76, ++ 0x15, 0xed, 0x07, 0xe3, 0x39, 0x13, 0x39, 0x8a, 0xe5, 0xe5, 0x39, 0xc8, ++ 0xfa, 0xaf, 0x00, 0x4e, 0x89, 0x35, 0xfa, 0xef, 0x8e, 0x98, 0x1a, 0xcc, ++ 0xc7, 0x73, 0x18, 0xf6, 0xff, 0x04, 0xbc, 0xbd, 0x99, 0xdc, 0x6e, 0xb6, ++ 0x10, 0x27, 0xca, 0x59, 0xc3, 0x3e, 0xbf, 0x78, 0xfe, 0x25, 0x93, 0xdb, ++ 0xeb, 0x6b, 0xe3, 0x4d, 0xa1, 0xf2, 0x04, 0xf4, 0x00, 0xc0, 0x75, 0x85, ++ 0xcd, 0x8a, 0xeb, 0x5e, 0xe1, 0x20, 0x89, 0xb5, 0x10, 0x57, 0xb0, 0x29, ++ 0x2e, 0x1c, 0xcb, 0xd0, 0x8f, 0x78, 0xc6, 0xbb, 0x4d, 0x44, 0x0d, 0x3d, ++ 0x2f, 0x53, 0x13, 0x45, 0xd4, 0x10, 0xbb, 0xc8, 0xe1, 0x49, 0xd0, 0x95, ++ 0x87, 0xce, 0x1a, 0xae, 0xab, 0x3f, 0x4c, 0x4b, 0xd5, 0x7d, 0x4f, 0x5e, ++ 0x94, 0xab, 0xfb, 0x3e, 0xb2, 0x79, 0xac, 0xae, 0x3c, 0xba, 0xe5, 0x06, ++ 0x5d, 0xfd, 0x14, 0x0a, 0x80, 0xd0, 0x72, 0xda, 0xba, 0x5b, 0x74, 0xf5, ++ 0x33, 0xda, 0x66, 0xe8, 0xca, 0x59, 0x9b, 0xee, 0xd6, 0xd5, 0xcf, 0xf1, ++ 0xcd, 0xd5, 0x7d, 0xcf, 0xdb, 0xb1, 0x44, 0xf7, 0xbd, 0xa0, 0x7d, 0x85, ++ 0xae, 0x3c, 0xa6, 0xe3, 0x07, 0xba, 0xfa, 0xf2, 0x00, 0xf6, 0xb8, 0x80, ++ 0xb3, 0x2c, 0xec, 0x71, 0x5b, 0xb1, 0x06, 0x74, 0x25, 0xdb, 0xac, 0x52, ++ 0xa8, 0xdd, 0xf2, 0x22, 0xaf, 0x57, 0x1e, 0x6b, 0x45, 0xf8, 0x3f, 0xc2, ++ 0xf5, 0xf5, 0x23, 0x36, 0x0b, 0xea, 0xeb, 0x47, 0xb8, 0xbe, 0xee, 0x72, ++ 0x94, 0x5c, 0x75, 0x5f, 0xe6, 0x9f, 0xf5, 0xdf, 0xde, 0x16, 0xf4, 0xc0, ++ 0xed, 0xb5, 0x0a, 0x1e, 0x2f, 0xfb, 0xf2, 0x80, 0xc5, 0x04, 0xf4, 0xb8, ++ 0xfc, 0x20, 0xa5, 0x8b, 0x31, 0x68, 0xaf, 0xbd, 0x9d, 0xc9, 0xec, 0xb5, ++ 0xe9, 0xf5, 0xb8, 0xfa, 0x80, 0x05, 0xe4, 0x5e, 0xf7, 0x00, 0xf9, 0x20, ++ 0xef, 0x65, 0x72, 0x3f, 0x43, 0xa1, 0x7e, 0x4c, 0x18, 0x7f, 0xf0, 0x93, ++ 0x4c, 0x55, 0x17, 0xb7, 0x13, 0xfe, 0x03, 0x95, 0x6b, 0xef, 0x73, 0xfd, ++ 0xc2, 0xfc, 0x26, 0xd2, 0x2c, 0x83, 0x1c, 0x10, 0x72, 0xa9, 0x29, 0x9a, ++ 0xa0, 0x9d, 0xd7, 0x14, 0x6d, 0xc7, 0x3c, 0x9f, 0xde, 0xd8, 0x4b, 0x99, ++ 0xc0, 0x4f, 0x54, 0x5e, 0x7d, 0x0c, 0xed, 0xba, 0xb3, 0x9f, 0x68, 0x3e, ++ 0x00, 0x72, 0xaa, 0x33, 0x02, 0xe5, 0xd4, 0x5b, 0xd9, 0x9f, 0xa0, 0x3f, ++ 0x7e, 0x4b, 0xcb, 0x42, 0x6c, 0xff, 0x62, 0xa6, 0x9d, 0xe1, 0xc5, 0xe2, ++ 0x52, 0xed, 0x28, 0xa7, 0xf4, 0xfa, 0xf7, 0xa8, 0xb9, 0xbb, 0x16, 0xf0, ++ 0x70, 0x74, 0xbc, 0x4c, 0x56, 0x81, 0x1d, 0xe4, 0x2a, 0x1d, 0x4a, 0xae, ++ 0x02, 0xf7, 0x77, 0xc0, 0xdf, 0xa6, 0x76, 0xf2, 0xb6, 0x2c, 0x82, 0xfd, ++ 0x5e, 0xcb, 0x5f, 0x3d, 0xba, 0x72, 0x11, 0xe6, 0x4d, 0x0f, 0xd4, 0xdf, ++ 0xd1, 0xa2, 0x48, 0x8c, 0x9b, 0xd6, 0x02, 0x5d, 0x85, 0x8c, 0x1b, 0x9d, ++ 0xc5, 0xe0, 0x99, 0xc1, 0x9f, 0xd4, 0x10, 0x45, 0xbf, 0xf3, 0xdc, 0xaf, ++ 0x6d, 0x3e, 0x2f, 0xf8, 0x4b, 0x63, 0xdf, 0x8d, 0x25, 0x36, 0xc8, 0x93, ++ 0xf9, 0xe3, 0x38, 0x2f, 0xe8, 0x23, 0xd2, 0x7d, 0x3f, 0xec, 0xdf, 0x7b, ++ 0xbf, 0x8e, 0xc1, 0xb8, 0x4e, 0x6d, 0xd1, 0xbb, 0xe3, 0x56, 0x61, 0xbe, ++ 0xa8, 0x9b, 0xf9, 0x7d, 0x13, 0xd8, 0x9a, 0x6f, 0x7a, 0xf9, 0xed, 0x58, ++ 0xf0, 0xd7, 0x6b, 0x77, 0x1f, 0x4c, 0xf2, 0x86, 0xe0, 0xd1, 0xe8, 0xef, ++ 0x65, 0xf0, 0xf5, 0x11, 0xa5, 0x27, 0x13, 0xf3, 0x4e, 0x5f, 0x3d, 0x33, ++ 0x44, 0xa5, 0xcf, 0xda, 0x57, 0x0e, 0x25, 0xb1, 0xb8, 0x92, 0x3e, 0xff, ++ 0xc5, 0xe8, 0xe7, 0xd7, 0xb6, 0x2c, 0xd7, 0xd1, 0x67, 0xe3, 0xa5, 0x48, ++ 0x5d, 0x1e, 0x4c, 0xa3, 0xd2, 0x6d, 0x01, 0x7c, 0x34, 0x5e, 0x8a, 0xc1, ++ 0xf7, 0xbd, 0x99, 0xfa, 0x38, 0xc0, 0x80, 0xf0, 0x1a, 0x24, 0x3c, 0x8d, ++ 0xef, 0x05, 0x3c, 0x8f, 0x16, 0x9d, 0x19, 0x05, 0x71, 0xfa, 0x2f, 0x23, ++ 0xc3, 0xd3, 0xf1, 0x6d, 0xbc, 0x9e, 0x28, 0x1b, 0xcf, 0x2f, 0x0c, 0x94, ++ 0x27, 0x3f, 0x81, 0xb7, 0xbb, 0xe0, 0x9a, 0x38, 0x14, 0xe2, 0x4c, 0xb5, ++ 0x16, 0x7f, 0xfa, 0x60, 0xe2, 0x12, 0x02, 0x4e, 0x6f, 0x5d, 0x6e, 0xc0, ++ 0x73, 0x11, 0xbf, 0x1e, 0xe0, 0x5c, 0x44, 0x51, 0x16, 0xdb, 0x37, 0xf9, ++ 0x75, 0xf6, 0x02, 0xcc, 0x6b, 0x9e, 0x68, 0x6d, 0xae, 0x04, 0xfd, 0x3d, ++ 0x91, 0xc7, 0x3f, 0xc3, 0xe4, 0x35, 0x57, 0x67, 0x81, 0x9d, 0x7b, 0xe2, ++ 0x5f, 0x93, 0xd7, 0x3c, 0x3d, 0x8b, 0xe3, 0x87, 0xe7, 0x0d, 0x0f, 0xcf, ++ 0x52, 0xc3, 0xe6, 0x35, 0x5f, 0xeb, 0xdc, 0xc9, 0x54, 0x0b, 0x95, 0x4b, ++ 0x61, 0xf8, 0x2b, 0xb7, 0x0f, 0x7e, 0x7f, 0x9a, 0x39, 0x8e, 0xd2, 0xf1, ++ 0xfd, 0xbf, 0x30, 0xdb, 0x61, 0x5e, 0x0d, 0xa0, 0xf3, 0x20, 0xde, 0xb2, ++ 0xc5, 0x8c, 0xf1, 0xd7, 0xb7, 0x2f, 0x47, 0x10, 0x88, 0x87, 0x7f, 0xb6, ++ 0xd9, 0xfc, 0x3c, 0xe4, 0xbb, 0x2c, 0xfa, 0xc5, 0xc1, 0x11, 0x4f, 0x40, ++ 0xfc, 0xbb, 0x28, 0x02, 0xf3, 0xf1, 0x1a, 0xb6, 0x98, 0x59, 0xbc, 0xb6, ++ 0x28, 0xd2, 0x07, 0x21, 0x87, 0x45, 0x5b, 0xbe, 0x37, 0x04, 0xf2, 0x2e, ++ 0xbf, 0xa0, 0x7c, 0xbb, 0x8c, 0xce, 0xab, 0xe1, 0x17, 0x0e, 0xcc, 0x07, ++ 0x7a, 0xbb, 0xeb, 0xb1, 0x21, 0x80, 0xa7, 0x33, 0x9c, 0x9f, 0x17, 0x7d, ++ 0xfb, 0xe3, 0x3b, 0x00, 0xfe, 0xbb, 0x2d, 0xf6, 0xbc, 0x22, 0xfa, 0x5c, ++ 0xb6, 0x4b, 0xd2, 0xe5, 0x99, 0x2f, 0xd9, 0x16, 0xa9, 0x2b, 0x8b, 0x7c, ++ 0x22, 0x81, 0x3f, 0x22, 0x05, 0xf3, 0xcf, 0x55, 0x2a, 0x4f, 0x5b, 0xb2, ++ 0xf4, 0xe7, 0x68, 0xc6, 0x05, 0xf7, 0x25, 0x5a, 0xb2, 0xb8, 0x5c, 0xbd, ++ 0x9d, 0xce, 0x77, 0xf9, 0xf8, 0x0b, 0x16, 0xc0, 0xe3, 0xc1, 0xc3, 0x51, ++ 0x38, 0xef, 0x37, 0x62, 0x64, 0xf4, 0x73, 0xfd, 0x45, 0x7f, 0xfd, 0xdd, ++ 0x18, 0x5a, 0xae, 0xfc, 0x56, 0xc1, 0xbc, 0x7e, 0x63, 0x7e, 0x12, 0x21, ++ 0x88, 0x74, 0xb2, 0x90, 0xe7, 0x11, 0x56, 0xbe, 0xa2, 0xf4, 0x9d, 0x03, ++ 0x80, 0xb2, 0x7f, 0x65, 0x33, 0xf2, 0x09, 0x6d, 0x17, 0x53, 0x1d, 0x92, ++ 0x6f, 0x5d, 0xf9, 0x73, 0xe6, 0x4f, 0x57, 0x46, 0xb2, 0x3c, 0xe0, 0x01, ++ 0xf3, 0x96, 0x0c, 0xf9, 0x4a, 0xe2, 0x9c, 0x45, 0xbf, 0x3c, 0xa5, 0xe0, ++ 0x39, 0x0b, 0x9d, 0x9d, 0x22, 0xe8, 0xe6, 0xa9, 0x2c, 0x3d, 0x5f, 0x1f, ++ 0x3c, 0xcc, 0xf2, 0x92, 0x16, 0x1e, 0xe5, 0x76, 0xe5, 0x35, 0xe4, 0xe6, ++ 0x3b, 0xb0, 0x8e, 0x0c, 0xc0, 0xd7, 0x5b, 0x75, 0xb0, 0x6f, 0xf9, 0x36, ++ 0x87, 0xc6, 0xdb, 0x97, 0x3f, 0x5b, 0x3b, 0x8c, 0x96, 0x3f, 0x9b, 0x20, ++ 0x41, 0x64, 0x8e, 0x7c, 0x76, 0x39, 0x3c, 0xdf, 0x7c, 0x26, 0xf4, 0x12, ++ 0x9c, 0x0f, 0xc8, 0x0e, 0xe2, 0x67, 0x9a, 0x6b, 0x71, 0x5f, 0x19, 0xd8, ++ 0xf2, 0xd6, 0x09, 0xf7, 0xe9, 0xce, 0x2d, 0x0c, 0x5e, 0xde, 0x5c, 0x5d, ++ 0x9e, 0xdc, 0x95, 0x65, 0xc1, 0xf1, 0x8d, 0xf2, 0xdd, 0x48, 0xf7, 0xff, ++ 0xbf, 0xe4, 0x7b, 0x6d, 0xd1, 0xa1, 0x51, 0x5e, 0x1b, 0x3e, 0x5f, 0x80, ++ 0xe7, 0xd9, 0xdd, 0x4c, 0x3e, 0x1a, 0xf9, 0xdc, 0x28, 0xcf, 0x73, 0x0d, ++ 0x72, 0x30, 0x28, 0xc7, 0x65, 0x9d, 0x1c, 0xcf, 0xe5, 0x72, 0x20, 0x28, ++ 0xcf, 0x2d, 0xf8, 0x9d, 0x9a, 0x69, 0xb8, 0x1e, 0x6f, 0x89, 0xe2, 0x5b, ++ 0x23, 0xa1, 0xff, 0xf3, 0x1e, 0xd0, 0x7d, 0x7e, 0x8c, 0x9a, 0x58, 0x4e, ++ 0x9b, 0xac, 0xb5, 0xa7, 0x46, 0x6b, 0x57, 0xf7, 0x47, 0xff, 0x2f, 0xd4, ++ 0xef, 0x4a, 0xd1, 0x3e, 0xca, 0xa2, 0x7c, 0x34, 0xfa, 0x97, 0xb9, 0x55, ++ 0x60, 0x8c, 0xe7, 0xed, 0x6a, 0x33, 0x01, 0xff, 0xf6, 0x0e, 0x60, 0x87, ++ 0x14, 0xa4, 0x1a, 0xf2, 0x82, 0x78, 0x7c, 0x48, 0x7c, 0x3f, 0x9b, 0x55, ++ 0x5e, 0x00, 0xf9, 0xaa, 0x7b, 0x54, 0xf6, 0x14, 0xfc, 0x59, 0x4c, 0x99, ++ 0x90, 0xef, 0x2f, 0x9f, 0xcd, 0x62, 0xfb, 0xcb, 0x3f, 0x01, 0xbb, 0x67, ++ 0xf9, 0x7f, 0x5e, 0x44, 0xfe, 0xdc, 0x12, 0xa5, 0x39, 0x15, 0x58, 0xcf, ++ 0x70, 0x8b, 0x2b, 0x74, 0xff, 0x56, 0x3c, 0x2f, 0x72, 0x7e, 0x1f, 0xf8, ++ 0x7c, 0xad, 0x3e, 0xdf, 0xf9, 0x74, 0x3a, 0x61, 0x78, 0xcf, 0xce, 0xd6, ++ 0xed, 0xcf, 0x80, 0x7f, 0x8f, 0xf9, 0x01, 0x07, 0xa2, 0x10, 0x6e, 0xcf, ++ 0x3a, 0xdd, 0x97, 0x01, 0x0e, 0xed, 0x4e, 0xf7, 0xb7, 0x30, 0xaf, 0x32, ++ 0xa7, 0xfb, 0x1f, 0x59, 0x21, 0x78, 0x59, 0xcb, 0xd7, 0xa9, 0x98, 0xf4, ++ 0x71, 0x6b, 0xf1, 0x2c, 0xcd, 0x16, 0xf4, 0xef, 0x41, 0x3d, 0xbe, 0xa0, ++ 0x22, 0xbc, 0xfc, 0x4d, 0xcd, 0x66, 0x79, 0xc1, 0xe5, 0x4f, 0xdf, 0x35, ++ 0x0a, 0xec, 0xce, 0xbf, 0xec, 0xbf, 0x7b, 0x14, 0xc8, 0xc7, 0xae, 0xa7, ++ 0x4a, 0xaf, 0x6a, 0x87, 0x6e, 0xe0, 0xfc, 0xf9, 0x6f, 0x5c, 0xee, 0xc7, ++ 0xf3, 0xb8, 0xe3, 0x4f, 0x81, 0x6f, 0x68, 0x39, 0x01, 0xe2, 0x96, 0xb4, ++ 0xfd, 0x02, 0x8b, 0x27, 0x33, 0x3e, 0xa4, 0x1f, 0x73, 0x76, 0x3c, 0xdb, ++ 0xef, 0x2e, 0xff, 0x83, 0x27, 0x8d, 0xc2, 0xe5, 0xd4, 0x7a, 0x19, 0xe5, ++ 0xf7, 0xa9, 0x18, 0x16, 0x67, 0xfc, 0x24, 0x46, 0xa9, 0xd9, 0xc6, 0xdb, ++ 0x25, 0xe9, 0xda, 0xb1, 0x79, 0xca, 0x40, 0xf7, 0x94, 0x8f, 0x95, 0x18, ++ 0x45, 0x77, 0x5e, 0xa2, 0x14, 0x68, 0xda, 0x31, 0xf0, 0x3a, 0x4b, 0xb3, ++ 0x99, 0x1e, 0xb5, 0x10, 0x97, 0x15, 0xda, 0x5b, 0x0e, 0xdc, 0x62, 0x05, ++ 0xfc, 0xca, 0x92, 0xdb, 0xce, 0xf2, 0xd2, 0x19, 0x3d, 0x4c, 0xa4, 0x23, ++ 0x00, 0x3d, 0xfc, 0x98, 0xcb, 0xb1, 0xbf, 0x3b, 0xb5, 0xa2, 0x6c, 0x6c, ++ 0xc7, 0xf4, 0xed, 0x44, 0xae, 0x6f, 0x95, 0x18, 0x83, 0x7e, 0x1d, 0x11, ++ 0x5e, 0x9e, 0x89, 0xe7, 0x4b, 0x4e, 0x77, 0x09, 0xf4, 0x73, 0xa7, 0xd3, ++ 0x5d, 0x9a, 0xed, 0x80, 0xb8, 0x17, 0xc9, 0x03, 0xbe, 0x69, 0x8f, 0x0a, ++ 0x9f, 0xe7, 0x73, 0x13, 0xc7, 0xdf, 0xdf, 0x85, 0x3d, 0x46, 0x62, 0xd0, ++ 0x6f, 0xc6, 0xf1, 0x64, 0xdc, 0x57, 0x75, 0x67, 0x63, 0x5c, 0xcb, 0x53, ++ 0x01, 0xfd, 0xc1, 0xbe, 0xaa, 0x59, 0x02, 0x3e, 0xb0, 0xf3, 0xfa, 0x6e, ++ 0x89, 0xc5, 0x2b, 0x3c, 0x37, 0xc3, 0x77, 0xe2, 0x74, 0x4b, 0xd3, 0x28, ++ 0xbc, 0x4b, 0xfe, 0x4c, 0xf0, 0x3c, 0xc7, 0xde, 0x23, 0x15, 0x12, 0xec, ++ 0xff, 0x26, 0x75, 0x57, 0x49, 0x20, 0xc7, 0x92, 0x38, 0xfe, 0x8c, 0xf3, ++ 0xe8, 0xe1, 0x70, 0xdb, 0xc3, 0xf3, 0x25, 0xfa, 0xf3, 0x1d, 0xf3, 0x2b, ++ 0x66, 0x70, 0xf8, 0xef, 0x51, 0x3d, 0xc8, 0x5f, 0xad, 0x29, 0x9a, 0x13, ++ 0xfc, 0x55, 0xc8, 0xcb, 0x03, 0xbc, 0x1a, 0xf3, 0x2c, 0x7e, 0x99, 0xcd, ++ 0xf6, 0xd5, 0xb6, 0x44, 0xf5, 0xe0, 0xfe, 0xa0, 0xf7, 0x6e, 0x82, 0xf9, ++ 0x77, 0x43, 0xcb, 0xbc, 0x12, 0xe4, 0x0f, 0x25, 0xd7, 0xb6, 0x95, 0x53, ++ 0x8c, 0x93, 0xf9, 0xd9, 0xcc, 0x9f, 0x4f, 0xa8, 0xd1, 0x9c, 0xe0, 0x87, ++ 0x0f, 0x77, 0x5a, 0xf0, 0x9e, 0x8a, 0xc1, 0xf2, 0x5b, 0x7e, 0xbb, 0x1b, ++ 0xe3, 0x25, 0xc5, 0x1a, 0x3b, 0xaf, 0xbc, 0xa9, 0xdb, 0x1b, 0x99, 0x49, ++ 0xe7, 0x35, 0xa4, 0x5b, 0x2b, 0xb7, 0xd0, 0x67, 0x7a, 0xce, 0x10, 0x5c, ++ 0xdf, 0x50, 0xd2, 0xbc, 0x8a, 0xf9, 0x09, 0xaa, 0x2e, 0xbf, 0xa9, 0x58, ++ 0xab, 0xc0, 0x7d, 0x72, 0x31, 0xef, 0x92, 0xf9, 0xcd, 0x6b, 0x2c, 0x2a, ++ 0xe6, 0xc3, 0xac, 0xc8, 0x0e, 0xf1, 0x6b, 0x92, 0x97, 0x79, 0xc3, 0xe6, ++ 0x3b, 0x19, 0xf7, 0xb9, 0xd7, 0x08, 0xbe, 0xe4, 0xf9, 0x08, 0xc5, 0x3c, ++ 0xff, 0xa0, 0x78, 0xdb, 0x53, 0x98, 0x4f, 0x50, 0xbc, 0xed, 0x66, 0x45, ++ 0x0a, 0x91, 0x33, 0x9b, 0xb2, 0xcd, 0xb8, 0xfe, 0x33, 0x87, 0x96, 0x8c, ++ 0x86, 0xf5, 0x0f, 0x94, 0xc7, 0xda, 0x96, 0xcd, 0xf0, 0xf0, 0xfd, 0x6c, ++ 0x26, 0x5f, 0x06, 0xca, 0x1f, 0x5b, 0xdf, 0x27, 0x17, 0xfa, 0xe5, 0x8f, ++ 0xad, 0xcf, 0x76, 0x84, 0xe4, 0xd7, 0x34, 0x9e, 0x47, 0xf9, 0xd7, 0x98, ++ 0xcd, 0xe4, 0xfc, 0xb3, 0x90, 0x57, 0x43, 0xe1, 0xfa, 0xec, 0x7c, 0x91, ++ 0x57, 0xb3, 0x45, 0x82, 0xf5, 0xee, 0xb5, 0xb4, 0x4f, 0xd9, 0x05, 0xf3, ++ 0x5a, 0x6e, 0xc2, 0x3c, 0xa6, 0xbe, 0xbc, 0xa2, 0xf9, 0x2c, 0xcf, 0xad, ++ 0xaf, 0x3d, 0xe4, 0x17, 0xd1, 0xf7, 0xcf, 0x2e, 0x62, 0xf9, 0x45, 0xc3, ++ 0x7c, 0x1b, 0x70, 0x5f, 0xe2, 0x62, 0x24, 0xcb, 0xa3, 0xb8, 0xb8, 0x3d, ++ 0x82, 0xc0, 0xb9, 0xa4, 0x67, 0xb7, 0x6d, 0x1c, 0x02, 0xe7, 0x10, 0x9f, ++ 0xd5, 0x4c, 0x68, 0x07, 0x1a, 0xe7, 0x0f, 0x07, 0x82, 0x78, 0x5e, 0xa4, ++ 0x19, 0xf2, 0x25, 0x01, 0x8f, 0x20, 0xaf, 0x04, 0xfe, 0xfa, 0xf2, 0x8f, ++ 0x78, 0xfe, 0x5e, 0xd7, 0xf6, 0x97, 0x71, 0xde, 0x62, 0x3e, 0x94, 0x50, ++ 0x2c, 0x00, 0xf7, 0xf4, 0x1c, 0x36, 0xaf, 0x25, 0x3b, 0x76, 0x4f, 0x01, ++ 0xe2, 0x1f, 0xbe, 0x2c, 0x41, 0x82, 0xb8, 0x9d, 0x98, 0xd7, 0xb5, 0xe4, ++ 0xfe, 0x4b, 0x9c, 0x2f, 0x06, 0x4b, 0x87, 0x2f, 0xe4, 0x30, 0xfe, 0x08, ++ 0xa3, 0x1f, 0x5f, 0xcd, 0xbe, 0x3e, 0xfd, 0xf8, 0x06, 0xe0, 0x89, 0xea, ++ 0xc7, 0x03, 0xd0, 0xee, 0xba, 0xf5, 0x23, 0xd7, 0x8b, 0x42, 0x4f, 0x8a, ++ 0xef, 0xdd, 0x9c, 0x2e, 0x66, 0x66, 0x0f, 0xa8, 0x1f, 0xbb, 0xb3, 0xc3, ++ 0xe8, 0x47, 0x15, 0xf2, 0x9e, 0x31, 0xef, 0xc8, 0xe4, 0xda, 0x1e, 0x06, ++ 0x5f, 0x33, 0x78, 0xbf, 0x37, 0xba, 0xb5, 0x4a, 0xe0, 0xe7, 0xa2, 0x34, ++ 0xed, 0x4f, 0xd0, 0xcf, 0xc4, 0x09, 0xbe, 0x83, 0x10, 0x07, 0x2d, 0xad, ++ 0xf1, 0x1e, 0x04, 0x7e, 0x2f, 0x96, 0xf8, 0x79, 0xeb, 0x29, 0x4c, 0x0e, ++ 0x24, 0xf6, 0x90, 0xfd, 0x10, 0x83, 0x8b, 0x3f, 0xd1, 0xe3, 0x86, 0x3c, ++ 0xe5, 0xaa, 0x6c, 0x96, 0x6f, 0x71, 0xc3, 0x69, 0x37, 0xee, 0xb3, 0xc7, ++ 0x79, 0x88, 0x04, 0xed, 0xc5, 0x3d, 0x06, 0x6d, 0x09, 0xec, 0xbc, 0xb3, ++ 0x71, 0xfc, 0x49, 0x9c, 0x2f, 0x4c, 0x4f, 0x06, 0x30, 0x1f, 0x2e, 0xa9, ++ 0x33, 0x7c, 0x5e, 0x6a, 0x41, 0x2a, 0xb3, 0xd7, 0xa8, 0xbc, 0x3c, 0x0b, ++ 0x70, 0x2d, 0x19, 0x4d, 0xe5, 0x69, 0x4a, 0x7f, 0x79, 0x1a, 0x06, 0x7f, ++ 0x17, 0xa0, 0x7e, 0xce, 0x2e, 0xff, 0x01, 0xa8, 0x35, 0x36, 0x3e, 0x3d, ++ 0x1a, 0xcc, 0xaa, 0xab, 0xe0, 0xef, 0xaf, 0x0c, 0x7f, 0xee, 0x4b, 0xf0, ++ 0x14, 0xf8, 0xca, 0xbd, 0x22, 0xeb, 0xe2, 0x78, 0x02, 0x5f, 0x57, 0xf8, ++ 0xfc, 0x6f, 0xcd, 0x70, 0xff, 0x03, 0xc6, 0x39, 0xcc, 0xf9, 0x7b, 0x20, ++ 0x3c, 0xc6, 0xe6, 0x50, 0xfc, 0x8d, 0x07, 0xfa, 0x66, 0x78, 0x14, 0x79, ++ 0xc0, 0x3b, 0x0d, 0x76, 0x6a, 0x45, 0x0e, 0xc3, 0xcb, 0xe4, 0x1c, 0x7d, ++ 0x5c, 0x28, 0x04, 0xdf, 0xb1, 0x39, 0xe3, 0xfb, 0xe3, 0x5b, 0xc8, 0xf1, ++ 0xbd, 0x47, 0xf6, 0xc8, 0x80, 0xb7, 0x92, 0xaa, 0xb6, 0x35, 0x80, 0x07, ++ 0x8a, 0xd7, 0xa4, 0x1c, 0xda, 0xcf, 0x0d, 0x65, 0xfa, 0xfc, 0x4f, 0x23, ++ 0x5e, 0x85, 0x3c, 0x34, 0xe2, 0xd7, 0x88, 0x57, 0x91, 0x07, 0x48, 0xf1, ++ 0x31, 0x3a, 0x27, 0x8c, 0xfe, 0x12, 0xfd, 0x18, 0xf5, 0x58, 0x88, 0x9c, ++ 0xe0, 0xfb, 0xce, 0x6a, 0x5f, 0x7e, 0x07, 0xd8, 0xcf, 0x22, 0x4f, 0x5c, ++ 0xac, 0x43, 0xf0, 0xcf, 0x24, 0x0e, 0x8f, 0x1b, 0x35, 0xad, 0xd2, 0xc2, ++ 0xe8, 0xb4, 0x10, 0xc6, 0x9d, 0x38, 0xcb, 0x77, 0xd0, 0x0c, 0x74, 0xba, ++ 0xc8, 0x7b, 0xd0, 0x12, 0x4a, 0xa7, 0x8b, 0x09, 0xdb, 0xaf, 0xe2, 0xf3, ++ 0x48, 0xee, 0xf1, 0xe2, 0x7a, 0x86, 0x9d, 0xd0, 0xca, 0xe1, 0x79, 0xc3, ++ 0x69, 0x3f, 0xde, 0xe3, 0x31, 0xb4, 0x99, 0xae, 0x87, 0x04, 0xd7, 0x33, ++ 0xb2, 0xfb, 0x38, 0xe6, 0x63, 0xc2, 0xbe, 0x2c, 0xc4, 0x9b, 0xf6, 0x1e, ++ 0x39, 0x80, 0xf3, 0x1e, 0xd1, 0xdd, 0xc5, 0x9e, 0x3c, 0x8f, 0xc8, 0xa8, ++ 0x6f, 0x83, 0xf9, 0xb7, 0xac, 0x9f, 0x17, 0xb8, 0xfc, 0x6a, 0x3d, 0xc7, ++ 0xf2, 0xf8, 0x5a, 0xcb, 0x99, 0xbe, 0xbd, 0x37, 0xc3, 0x5d, 0x99, 0x83, ++ 0x7c, 0xec, 0xae, 0x82, 0xf9, 0xaf, 0xc8, 0x70, 0x57, 0x43, 0xb9, 0x20, ++ 0x95, 0xd1, 0x4d, 0x6c, 0x8e, 0xfb, 0x66, 0x28, 0x8f, 0x1c, 0x40, 0xdf, ++ 0xdf, 0x9a, 0xd3, 0xb7, 0x4f, 0x3d, 0x1d, 0xea, 0x25, 0x3d, 0x40, 0xbc, ++ 0xe2, 0x1e, 0x14, 0x88, 0xc3, 0x27, 0x41, 0x24, 0x10, 0xb6, 0xf0, 0x9b, ++ 0xbd, 0x92, 0x85, 0xc2, 0x35, 0xc9, 0x4d, 0xd0, 0xef, 0x1c, 0x9d, 0xa8, ++ 0xad, 0x82, 0xbc, 0xb7, 0xc0, 0x44, 0xe2, 0x82, 0x7c, 0x80, 0xb8, 0x3a, ++ 0x7b, 0x39, 0xc0, 0x2b, 0x61, 0x91, 0x6b, 0x3f, 0xc0, 0xb3, 0xf5, 0x1c, ++ 0xbf, 0xcf, 0xe5, 0x3e, 0x82, 0xe7, 0xbd, 0xfa, 0xf2, 0xab, 0xb4, 0x54, ++ 0xcc, 0xa7, 0x00, 0xfe, 0x0d, 0xe5, 0x97, 0x7a, 0x3e, 0x8f, 0xfa, 0x1c, ++ 0xc6, 0x07, 0xd4, 0xde, 0x99, 0x93, 0xc3, 0xe6, 0xa5, 0xc1, 0xbc, 0x84, ++ 0xbd, 0x23, 0xf8, 0x72, 0x20, 0xfb, 0x25, 0x84, 0xaf, 0x1b, 0xa0, 0xfd, ++ 0x75, 0xf0, 0xf5, 0xf2, 0x9c, 0xeb, 0xe3, 0xeb, 0x15, 0x39, 0x8c, 0xaf, ++ 0xef, 0x87, 0x76, 0xd7, 0xe2, 0xeb, 0x1f, 0xe4, 0xf4, 0xf1, 0xf5, 0x43, ++ 0xd0, 0xee, 0x5a, 0x7c, 0xfd, 0x28, 0xe7, 0xeb, 0x17, 0xae, 0xc1, 0xd7, ++ 0x3b, 0x78, 0xbf, 0xff, 0xc5, 0xeb, 0x87, 0xe1, 0xeb, 0x47, 0xc3, 0xf1, ++ 0xb5, 0xca, 0xe9, 0x4e, 0xf0, 0xc5, 0x9e, 0x23, 0x63, 0xa3, 0x21, 0x5f, ++ 0x60, 0x1b, 0xef, 0x2f, 0x44, 0x7e, 0x6f, 0x80, 0xf6, 0xd7, 0x92, 0xdf, ++ 0xff, 0x04, 0x9f, 0x6f, 0x86, 0x7e, 0xaf, 0x65, 0xa7, 0x8a, 0x7e, 0x05, ++ 0xbe, 0xaf, 0xc5, 0x27, 0xb1, 0xb9, 0x1e, 0x84, 0x83, 0xb0, 0x47, 0x4f, ++ 0xa7, 0x33, 0xbc, 0x0b, 0xbe, 0xa7, 0xfc, 0xf2, 0x9f, 0x00, 0x7f, 0xca, ++ 0x2f, 0x3b, 0x39, 0xbf, 0xfc, 0x92, 0xf1, 0x8b, 0x8a, 0xf5, 0x8c, 0xfc, ++ 0xd5, 0xa7, 0xef, 0xba, 0x4d, 0xfc, 0x1e, 0x11, 0x7b, 0x74, 0x68, 0xdc, ++ 0xfb, 0xcd, 0x9c, 0x7e, 0xfa, 0xee, 0xe5, 0x9c, 0x30, 0xfa, 0x6e, 0x24, ++ 0xe1, 0xf0, 0xaa, 0x61, 0x72, 0x64, 0x04, 0xf1, 0xca, 0xb1, 0xd0, 0x6f, ++ 0xad, 0x1d, 0xcb, 0xf6, 0xb3, 0x76, 0x74, 0xf3, 0x63, 0x4f, 0x05, 0xbc, ++ 0x00, 0xb7, 0xf7, 0x72, 0x98, 0xbd, 0x51, 0x3c, 0x40, 0x3c, 0xe1, 0x77, ++ 0x9c, 0x4f, 0x92, 0xba, 0x2b, 0x50, 0xbe, 0x50, 0x78, 0x1e, 0xca, 0x09, ++ 0xd1, 0x63, 0x49, 0xc4, 0x3e, 0x15, 0xfc, 0x9c, 0xcf, 0x73, 0xd8, 0xba, ++ 0xc6, 0x4d, 0x70, 0x1f, 0x04, 0xb9, 0x64, 0x77, 0x7b, 0x30, 0x9f, 0xdb, ++ 0x91, 0xcb, 0xe0, 0x22, 0xe0, 0x44, 0xdb, 0xbf, 0x13, 0x4e, 0xee, 0xee, ++ 0x03, 0x7c, 0xe4, 0xf7, 0xf7, 0x1b, 0x8c, 0x78, 0x38, 0xc8, 0xe7, 0xfb, ++ 0x39, 0xa7, 0x1f, 0x63, 0xff, 0x42, 0xfe, 0x40, 0xff, 0x05, 0xd8, 0xbf, ++ 0x6a, 0x82, 0xfe, 0x45, 0xfb, 0x3f, 0x07, 0xe5, 0xd0, 0x47, 0xb0, 0x8e, ++ 0xd2, 0x07, 0x9a, 0x65, 0x58, 0x57, 0x12, 0x71, 0x47, 0x83, 0xfc, 0x11, ++ 0x72, 0x92, 0x8c, 0xa0, 0xed, 0x8b, 0xfb, 0xb7, 0xff, 0x34, 0xd8, 0xfe, ++ 0x53, 0x58, 0x47, 0x69, 0x33, 0x6d, 0x9f, 0x1f, 0x6c, 0x3f, 0x92, 0xf8, ++ 0x31, 0x5f, 0x27, 0x61, 0x11, 0x95, 0x53, 0x04, 0xec, 0x77, 0x17, 0xda, ++ 0xb3, 0xeb, 0x55, 0xcf, 0xb9, 0x1c, 0x9c, 0x27, 0x61, 0xf2, 0xaa, 0xdc, ++ 0x84, 0xf2, 0x20, 0x2b, 0xdd, 0x8d, 0x7c, 0x17, 0x4e, 0xff, 0x43, 0xfd, ++ 0xeb, 0xd1, 0xff, 0xb0, 0x1e, 0xd0, 0xff, 0x83, 0x91, 0x13, 0x57, 0x38, ++ 0x3d, 0x81, 0xfe, 0x87, 0x71, 0x3e, 0xce, 0xba, 0x86, 0xfe, 0xcf, 0x65, ++ 0xeb, 0x8e, 0xcb, 0xbd, 0xba, 0x9c, 0x88, 0xcf, 0x65, 0xfd, 0x3a, 0x72, ++ 0x07, 0xd6, 0xff, 0xb9, 0x61, 0xe4, 0xc4, 0x1e, 0xd5, 0x8d, 0xfc, 0x14, ++ 0x86, 0x8f, 0x12, 0x72, 0x1d, 0x10, 0x67, 0x71, 0x27, 0x42, 0x3b, 0xca, ++ 0x47, 0x49, 0x50, 0x16, 0x7a, 0x87, 0xb6, 0x1b, 0x02, 0xef, 0xd7, 0xab, ++ 0x0c, 0x8e, 0xeb, 0x6b, 0x4d, 0xd9, 0x68, 0x5f, 0x93, 0x28, 0x57, 0x38, ++ 0x7f, 0x26, 0x2d, 0x37, 0x66, 0xb0, 0xf9, 0x45, 0x69, 0x7c, 0x9e, 0xd7, ++ 0x95, 0xff, 0xfa, 0xdc, 0x8f, 0x7a, 0x2c, 0x00, 0x6f, 0x91, 0xa7, 0x22, ++ 0xc6, 0x35, 0xe6, 0xbd, 0x0a, 0x3c, 0x2e, 0xef, 0x94, 0xc6, 0x41, 0x5c, ++ 0xae, 0xfc, 0xe0, 0x65, 0x8c, 0x93, 0xf4, 0xee, 0xff, 0x1b, 0xc6, 0x49, ++ 0x94, 0x8c, 0xb9, 0xe3, 0x60, 0xfc, 0xae, 0xd7, 0x58, 0xbc, 0x44, 0xe4, ++ 0x95, 0x88, 0xf1, 0x57, 0x70, 0x3f, 0xb2, 0x5a, 0xce, 0x6f, 0x87, 0x38, ++ 0xed, 0xf9, 0x1d, 0x16, 0x8c, 0x7f, 0xca, 0x44, 0xdd, 0x58, 0x46, 0xe7, ++ 0xd3, 0x74, 0xc4, 0x4c, 0x7c, 0x28, 0x07, 0xd9, 0xf9, 0x65, 0xb1, 0x4f, ++ 0x6b, 0xde, 0xd1, 0xda, 0x0d, 0x71, 0x79, 0x33, 0x09, 0xb9, 0x67, 0x07, ++ 0xf5, 0x9d, 0x1a, 0x07, 0x74, 0x69, 0x3e, 0xc2, 0xee, 0xbb, 0x21, 0x49, ++ 0xec, 0x7b, 0x33, 0xb1, 0xae, 0x62, 0xf7, 0x30, 0xea, 0xf7, 0x69, 0xe3, ++ 0xdd, 0xfa, 0x7d, 0xda, 0xc4, 0x1a, 0xfd, 0x3e, 0xad, 0x88, 0x23, 0x2e, ++ 0x25, 0x6c, 0x9e, 0x0e, 0x8f, 0x7e, 0xdf, 0x76, 0xe8, 0x2c, 0xfd, 0xbe, ++ 0xed, 0x30, 0x4d, 0xbf, 0x6f, 0x9b, 0xbc, 0x68, 0xac, 0x61, 0x1f, 0x57, ++ 0xbf, 0x6f, 0x3b, 0xba, 0xa5, 0xc2, 0xb0, 0x8f, 0xab, 0xdf, 0xb7, 0x4d, ++ 0x5b, 0x37, 0xc3, 0xb0, 0x8f, 0xab, 0xdf, 0xb7, 0xfd, 0x8c, 0x34, 0x3f, ++ 0x5d, 0x46, 0xd7, 0x9d, 0x2b, 0xee, 0xfb, 0xf1, 0xba, 0xbb, 0xe1, 0x5c, ++ 0xf4, 0x7c, 0x3e, 0xdf, 0xac, 0x4d, 0xfa, 0x7d, 0xdd, 0x2f, 0x76, 0xd6, ++ 0xe0, 0x7d, 0x21, 0xf3, 0x79, 0x7c, 0x3b, 0xc7, 0xa7, 0xdf, 0xe7, 0x5d, ++ 0x2a, 0x2f, 0x43, 0x3a, 0x26, 0x6d, 0xec, 0x9c, 0x73, 0x33, 0xfd, 0x07, ++ 0xe0, 0xa6, 0x90, 0xc0, 0xe1, 0x64, 0xc8, 0x3f, 0xf0, 0x49, 0x2e, 0x3f, ++ 0xfd, 0xdc, 0xb0, 0x49, 0x7f, 0x0e, 0x7a, 0x71, 0xc7, 0x16, 0x6c, 0xb7, ++ 0xd8, 0xa7, 0x7f, 0xbf, 0x74, 0x87, 0xbe, 0xfc, 0x40, 0x2e, 0xbf, 0x07, ++ 0x86, 0xc7, 0xbd, 0xfb, 0xd3, 0x41, 0x0c, 0xcb, 0x63, 0xd8, 0xcc, 0xe2, ++ 0xfd, 0xb2, 0x37, 0xcb, 0x40, 0x07, 0x7a, 0x7c, 0xfc, 0x6f, 0xe9, 0x42, ++ 0xe5, 0x74, 0x11, 0xe1, 0xd4, 0xd3, 0x45, 0xa4, 0xaa, 0xa7, 0x8b, 0x86, ++ 0x37, 0xf7, 0x96, 0xc0, 0xba, 0x8d, 0xf0, 0x8d, 0xce, 0xd6, 0xd3, 0x8b, ++ 0x11, 0xbe, 0x36, 0x97, 0x9e, 0x5e, 0x04, 0x5c, 0xa9, 0x9e, 0xe4, 0xf9, ++ 0x38, 0x6e, 0x5c, 0xef, 0xc2, 0x0e, 0x89, 0x3c, 0x23, 0xf5, 0x87, 0xeb, ++ 0xa2, 0xce, 0x0d, 0xad, 0x70, 0x0e, 0xdd, 0x08, 0x57, 0x42, 0x7c, 0xb8, ++ 0xef, 0x6c, 0x84, 0xaf, 0xcf, 0x00, 0xdf, 0x73, 0xaa, 0xf6, 0x3c, 0xf0, ++ 0xdf, 0x85, 0x8e, 0x07, 0xf0, 0xbe, 0x1f, 0xa2, 0x69, 0xe3, 0xa0, 0xdd, ++ 0x55, 0xf2, 0x63, 0xfe, 0x83, 0xd5, 0x1f, 0x74, 0x7e, 0x4c, 0x3b, 0xd4, ++ 0x0f, 0xfa, 0xc9, 0xfa, 0xfc, 0x98, 0x5e, 0xc8, 0xe3, 0x1a, 0x43, 0x06, ++ 0x91, 0xc7, 0x75, 0xf0, 0x7f, 0x20, 0xaf, 0x23, 0x82, 0xce, 0xd0, 0x0c, ++ 0xf1, 0xc6, 0x09, 0x2e, 0x6b, 0xf8, 0xbc, 0x2d, 0xed, 0xf5, 0x5c, 0xd4, ++ 0x33, 0x6e, 0x82, 0xf1, 0x9e, 0x3f, 0x10, 0xd7, 0x1a, 0x5a, 0x6b, 0x8d, ++ 0xad, 0x24, 0xef, 0x1a, 0x71, 0x81, 0x03, 0xb9, 0x68, 0x47, 0x69, 0x78, ++ 0x9f, 0x46, 0x69, 0x37, 0xcb, 0x73, 0x23, 0x4a, 0xb7, 0x1d, 0xe2, 0xbf, ++ 0xe1, 0xee, 0x6f, 0x34, 0x9c, 0x6b, 0x3a, 0x0a, 0xed, 0xff, 0xd9, 0xfb, ++ 0xf1, 0x84, 0xdd, 0x48, 0xed, 0xf4, 0x3f, 0xe6, 0x32, 0xbd, 0xfb, 0x2e, ++ 0x3c, 0xfb, 0xec, 0x74, 0x6e, 0xb7, 0x09, 0x7b, 0x7b, 0xa0, 0x7e, 0xfa, ++ 0xf2, 0x5c, 0x06, 0x78, 0x4a, 0x07, 0x64, 0xcc, 0xb3, 0x0a, 0x48, 0x51, ++ 0xae, 0x70, 0xf7, 0x0d, 0x9d, 0xce, 0x95, 0xc2, 0xea, 0x0d, 0xaa, 0x27, ++ 0x4e, 0xe7, 0x3a, 0x42, 0xe2, 0x5b, 0xdf, 0xbb, 0x70, 0x18, 0xf4, 0x07, ++ 0x85, 0xf7, 0x17, 0xf0, 0xde, 0x66, 0xa3, 0xfa, 0x5b, 0x1a, 0x94, 0xfe, ++ 0xee, 0x05, 0x38, 0x6d, 0x8c, 0x8e, 0x45, 0xba, 0x0e, 0xbc, 0x29, 0xfb, ++ 0xb2, 0x68, 0x83, 0xf3, 0x56, 0x35, 0x0e, 0xce, 0x9f, 0x1b, 0xef, 0x27, ++ 0x11, 0x79, 0x4f, 0xcd, 0x70, 0xff, 0x08, 0xd5, 0x27, 0x65, 0xe7, 0xb3, ++ 0xe3, 0xae, 0x96, 0x67, 0x50, 0x66, 0xb8, 0x9f, 0xc6, 0x78, 0x8f, 0x47, ++ 0xeb, 0x58, 0x9e, 0x67, 0x92, 0xc7, 0xd6, 0xf9, 0x6b, 0x7e, 0x8f, 0xa0, ++ 0x33, 0x4f, 0xd2, 0x9d, 0x97, 0x11, 0xf1, 0xa8, 0xa6, 0x75, 0x2c, 0xfe, ++ 0x0a, 0xf7, 0x0e, 0x76, 0x86, 0xf4, 0xe3, 0xcc, 0x63, 0x87, 0x56, 0x6e, ++ 0x56, 0xcb, 0x9d, 0x79, 0x0e, 0x88, 0x77, 0xb1, 0x78, 0x61, 0x6b, 0x8a, ++ 0x84, 0x76, 0x42, 0xab, 0x24, 0xa1, 0xdd, 0xb0, 0x39, 0xbd, 0xc2, 0x99, ++ 0x47, 0xfb, 0x3f, 0x94, 0x5b, 0x3e, 0x14, 0xea, 0xd9, 0xf9, 0xb8, 0x4e, ++ 0x88, 0x45, 0x8f, 0xc7, 0xf3, 0x3e, 0x38, 0x1f, 0xd5, 0x70, 0x5e, 0xec, ++ 0x18, 0xaf, 0x7f, 0x2c, 0xb7, 0x02, 0x9f, 0xce, 0x3c, 0xe1, 0x6f, 0xd9, ++ 0x73, 0x01, 0xff, 0x13, 0x55, 0x37, 0xf6, 0x6b, 0x91, 0xc3, 0xef, 0xab, ++ 0x8f, 0xcc, 0x63, 0xf6, 0x4f, 0x35, 0xf0, 0xb4, 0x23, 0xc8, 0x4f, 0xd7, ++ 0x73, 0x4f, 0x83, 0x25, 0xa9, 0xff, 0x3d, 0x0d, 0xc6, 0xfb, 0xcf, 0xdc, ++ 0xd9, 0xf6, 0x2e, 0x50, 0x07, 0xc6, 0x7d, 0xcf, 0x17, 0xaf, 0x75, 0x4f, ++ 0xc3, 0xbe, 0xf0, 0xf7, 0x34, 0x00, 0xdc, 0xa3, 0x13, 0x82, 0xfc, 0x50, ++ 0x92, 0xa7, 0xbf, 0xe7, 0xac, 0x23, 0xaa, 0x07, 0xf7, 0x41, 0x03, 0x6f, ++ 0xcb, 0xae, 0xad, 0xa4, 0xff, 0xba, 0x6f, 0xe6, 0x78, 0x5c, 0xcf, 0xcf, ++ 0x85, 0x38, 0x78, 0xfe, 0xf7, 0x28, 0xbe, 0x9f, 0xd2, 0xbf, 0x3e, 0x83, ++ 0xd3, 0x96, 0x01, 0xe2, 0xbd, 0x13, 0xd5, 0xf2, 0x6a, 0x80, 0xf3, 0x07, ++ 0xe9, 0x9e, 0x9b, 0x01, 0x0f, 0xe2, 0x9e, 0x9d, 0x0e, 0x8b, 0xb6, 0x06, ++ 0xfc, 0x8f, 0xc0, 0x4b, 0x04, 0xe7, 0x91, 0xed, 0x23, 0x07, 0xa0, 0x5c, ++ 0xe0, 0x55, 0x31, 0x8f, 0xbc, 0x35, 0xc5, 0x1b, 0x8d, 0xf7, 0x01, 0x14, ++ 0x99, 0xd0, 0x9f, 0x57, 0x37, 0xb5, 0x1d, 0x8c, 0x4c, 0xc2, 0x73, 0xb6, ++ 0x09, 0x92, 0x1a, 0x94, 0x27, 0x66, 0x85, 0x78, 0x6d, 0x94, 0xce, 0x16, ++ 0xc2, 0x65, 0x5d, 0x60, 0xdf, 0xf5, 0xcc, 0x3d, 0x60, 0xa3, 0xdf, 0x1d, ++ 0x9b, 0x6f, 0x93, 0xe0, 0xfe, 0x96, 0x36, 0xd2, 0x56, 0x19, 0x0b, 0x76, ++ 0xd7, 0x66, 0x12, 0x36, 0x3e, 0x58, 0xcf, 0xe9, 0x69, 0x6a, 0xf9, 0x01, ++ 0x8c, 0xb3, 0x3b, 0x02, 0xec, 0xbc, 0x5f, 0xff, 0x7a, 0x26, 0xe1, 0x27, ++ 0x6a, 0xb0, 0x8e, 0xd2, 0x80, 0x36, 0x4e, 0x4a, 0x0d, 0xca, 0x25, 0x14, ++ 0xb9, 0xe0, 0x3f, 0x75, 0x99, 0x7c, 0xe1, 0xe2, 0xb5, 0x59, 0xe9, 0x95, ++ 0x0b, 0xa1, 0x5d, 0x81, 0x8f, 0x84, 0x8d, 0xff, 0x55, 0xf3, 0x7b, 0x66, ++ 0xea, 0x54, 0xcf, 0x32, 0xac, 0xb7, 0xcf, 0x8f, 0x7e, 0x51, 0x83, 0x90, ++ 0xef, 0xf3, 0x4d, 0x04, 0xee, 0x37, 0xbc, 0x9d, 0xcb, 0xf3, 0xdb, 0x37, ++ 0xb3, 0xbc, 0x5c, 0x72, 0xf9, 0xca, 0x15, 0xb9, 0x24, 0x78, 0x7e, 0x8a, ++ 0xf6, 0x4f, 0x40, 0x3e, 0x35, 0xcc, 0xb4, 0xe1, 0xbd, 0xb1, 0x0d, 0x9d, ++ 0x29, 0x78, 0xff, 0x16, 0xf1, 0x48, 0x78, 0xcf, 0x4b, 0x53, 0xe7, 0x31, ++ 0x0f, 0x94, 0x1b, 0x8a, 0x8b, 0xed, 0x10, 0x6f, 0x76, 0xbf, 0x4f, 0x24, ++ 0xb8, 0x97, 0x0d, 0xcf, 0xec, 0xa1, 0x1c, 0x54, 0xc8, 0xa7, 0x42, 0xdf, ++ 0xa2, 0xfd, 0x90, 0x84, 0xfb, 0xfd, 0x33, 0x38, 0x5d, 0x8b, 0xfb, 0x94, ++ 0xa8, 0x1e, 0x59, 0x1f, 0x4d, 0xe1, 0xde, 0xb0, 0x79, 0xd5, 0x01, 0xc8, ++ 0xeb, 0x7e, 0xf7, 0x79, 0xda, 0x07, 0xfd, 0x74, 0x42, 0xd6, 0x4e, 0xfc, ++ 0x90, 0xf6, 0xfb, 0x5d, 0xaa, 0xc4, 0x5a, 0xc6, 0xc2, 0x53, 0x21, 0x75, ++ 0x18, 0x8f, 0x76, 0x62, 0x3f, 0x33, 0x79, 0x3f, 0xde, 0xbf, 0xd1, 0x71, ++ 0xad, 0xc1, 0x71, 0xbf, 0xdb, 0xf9, 0x26, 0xae, 0xe7, 0x84, 0x99, 0x78, ++ 0xad, 0x94, 0x7e, 0xcd, 0x15, 0x6c, 0x68, 0xf3, 0x0f, 0xe2, 0x30, 0xdf, ++ 0x58, 0xe4, 0xaf, 0xdc, 0x61, 0x6d, 0xab, 0x06, 0x3d, 0xdb, 0x6b, 0x09, ++ 0x14, 0xc2, 0xf9, 0xa9, 0xde, 0xd7, 0xde, 0x1b, 0x09, 0xfb, 0xd4, 0x1f, ++ 0xfe, 0x9f, 0x0b, 0x36, 0xb0, 0x8f, 0xff, 0xac, 0x04, 0x6c, 0xf0, 0xfe, ++ 0xf4, 0xc3, 0x7f, 0xb4, 0xc1, 0xfd, 0xc8, 0x1f, 0x3e, 0x2c, 0xe3, 0xbe, ++ 0xde, 0x1c, 0xae, 0x77, 0x04, 0xbc, 0x9f, 0xe7, 0x74, 0x7e, 0x31, 0xcf, ++ 0xf3, 0x0c, 0xd0, 0xe7, 0xbd, 0x2b, 0xbf, 0x2d, 0x09, 0xcd, 0xa3, 0x27, ++ 0x2d, 0x0e, 0xe4, 0x9f, 0xc5, 0x3e, 0x19, 0x53, 0x1e, 0x04, 0xdf, 0x2d, ++ 0xdd, 0x11, 0x0d, 0x16, 0x51, 0x5f, 0xb9, 0xb1, 0x3d, 0x51, 0x57, 0x16, ++ 0x7a, 0xa4, 0x11, 0xee, 0x6b, 0x0d, 0x43, 0x47, 0x27, 0x38, 0xbf, 0x2c, ++ 0xde, 0xb5, 0xc5, 0x02, 0xf7, 0x0b, 0x5c, 0xcc, 0xd3, 0x76, 0xc1, 0xf8, ++ 0xa7, 0x15, 0x46, 0x3f, 0xa7, 0xf7, 0xd9, 0x7c, 0x70, 0x7f, 0xa2, 0x98, ++ 0xcf, 0xdc, 0x5d, 0x45, 0x16, 0xb0, 0x4f, 0xfe, 0xdc, 0x19, 0x41, 0xfc, ++ 0xa0, 0x0f, 0x95, 0x6e, 0x33, 0x3b, 0x4f, 0xe6, 0xae, 0x95, 0x28, 0x3d, ++ 0x68, 0x1c, 0xef, 0xc6, 0x79, 0x1e, 0x7e, 0x3d, 0x1a, 0xfb, 0x5b, 0xf0, ++ 0x14, 0x93, 0x4f, 0xf5, 0x74, 0xac, 0x16, 0x0a, 0x57, 0xad, 0x73, 0x31, ++ 0xca, 0x21, 0xe3, 0x3a, 0x16, 0x7c, 0xa8, 0x4e, 0x86, 0x73, 0x1c, 0x0b, ++ 0x1e, 0x95, 0x08, 0xec, 0xaf, 0x40, 0xfd, 0x87, 0x29, 0xde, 0xb4, 0x96, ++ 0x1f, 0x63, 0x9e, 0xa8, 0x71, 0x9d, 0xf5, 0x5e, 0xe3, 0x7d, 0x76, 0x6e, ++ 0x94, 0x8f, 0x0d, 0x1c, 0xbf, 0xf3, 0xd6, 0xe9, 0xbf, 0x37, 0x74, 0x3e, ++ 0x8e, 0xfd, 0xcc, 0x27, 0xea, 0x7a, 0xb0, 0xa7, 0x17, 0xb4, 0x19, 0xbf, ++ 0x4f, 0xf9, 0x0c, 0xec, 0x9f, 0x06, 0x83, 0x3c, 0x7b, 0x27, 0x8f, 0xdb, ++ 0x5b, 0x25, 0xa4, 0x14, 0xee, 0x9d, 0x39, 0x60, 0x4d, 0x8b, 0xbb, 0xda, ++ 0xbd, 0xaf, 0x67, 0x57, 0xda, 0x91, 0x38, 0x3f, 0x5f, 0x69, 0xc5, 0xe7, ++ 0xe9, 0x95, 0x04, 0x9f, 0xcf, 0xe4, 0xa9, 0x08, 0xf7, 0x65, 0x9d, 0xc7, ++ 0x1e, 0x04, 0xfa, 0x59, 0xde, 0xb1, 0xdb, 0x02, 0xfd, 0x1c, 0xf4, 0x8d, ++ 0x4f, 0x82, 0xe3, 0xa3, 0x53, 0x3b, 0xa7, 0x28, 0x60, 0x77, 0x4d, 0xe5, ++ 0xfb, 0xac, 0xb3, 0xf9, 0xb9, 0x4e, 0x74, 0xaa, 0xd9, 0x79, 0xce, 0x1e, ++ 0xc0, 0x53, 0x55, 0x8c, 0xe1, 0x3c, 0x27, 0x5f, 0x77, 0x1d, 0xc7, 0x03, ++ 0xb1, 0x26, 0x22, 0x9d, 0xd5, 0xc1, 0x7a, 0x0b, 0xe1, 0xbd, 0xf2, 0x75, ++ 0xe8, 0x7a, 0xce, 0x1f, 0x49, 0x8b, 0xc1, 0x7d, 0x3a, 0xb1, 0xae, 0x52, ++ 0xba, 0x2e, 0x79, 0xf0, 0xeb, 0x12, 0xeb, 0x11, 0xeb, 0x13, 0xdf, 0x1b, ++ 0x65, 0x76, 0x3f, 0xb0, 0xb1, 0x9d, 0xa0, 0xf3, 0x67, 0x38, 0xdd, 0xcd, ++ 0xdf, 0x76, 0x5b, 0xeb, 0x70, 0x0a, 0x8a, 0x35, 0xaf, 0x7d, 0x36, 0xaa, ++ 0x87, 0xf9, 0xa9, 0x68, 0xdf, 0x57, 0x72, 0xbc, 0x55, 0x5a, 0x1f, 0x47, ++ 0xfb, 0xbe, 0x92, 0xe8, 0xef, 0xa5, 0xa2, 0x7f, 0xc7, 0x81, 0x7f, 0x05, ++ 0xbd, 0x35, 0x10, 0x97, 0x02, 0xcc, 0x6b, 0xa4, 0x2b, 0x81, 0x67, 0x12, ++ 0x63, 0xf6, 0xf2, 0xfb, 0xf9, 0xd1, 0xfe, 0xef, 0xa3, 0xa7, 0xce, 0x7f, ++ 0x43, 0xb8, 0x08, 0x7c, 0x53, 0x7e, 0x71, 0xf2, 0xfd, 0x34, 0x27, 0xec, ++ 0xa7, 0x51, 0xba, 0xd2, 0xd9, 0xdb, 0x94, 0x8e, 0x74, 0xe5, 0x05, 0x6d, ++ 0xfa, 0xf2, 0x97, 0xe6, 0x9e, 0x51, 0xc0, 0xef, 0x0d, 0x86, 0xfb, 0xa1, ++ 0xbe, 0x34, 0xe4, 0x5f, 0x88, 0xe7, 0xa5, 0xbc, 0x54, 0x06, 0x07, 0xd5, ++ 0x3d, 0x19, 0xce, 0x07, 0x2c, 0x20, 0x9e, 0x56, 0xb6, 0xef, 0xca, 0xce, ++ 0x1f, 0x9d, 0x56, 0xda, 0x0e, 0xff, 0x10, 0xf8, 0x70, 0x1b, 0xe3, 0x83, ++ 0x3f, 0x73, 0xfc, 0xb7, 0xe4, 0x7b, 0x46, 0xe7, 0x83, 0xfe, 0x52, 0xdc, ++ 0x85, 0x20, 0xef, 0x2b, 0x56, 0x0f, 0x93, 0x93, 0x68, 0xbd, 0xfa, 0xf5, ++ 0x92, 0x1d, 0xf8, 0x6b, 0xde, 0xda, 0xa2, 0xc9, 0xc0, 0x97, 0x63, 0x89, ++ 0x1b, 0xfb, 0x9b, 0x9d, 0x18, 0xde, 0x7e, 0xab, 0xc8, 0x67, 0x7a, 0x64, ++ 0x6e, 0xb3, 0x99, 0x58, 0xa8, 0xdd, 0x3f, 0x97, 0x8e, 0x01, 0x72, 0x6e, ++ 0xee, 0x3e, 0x19, 0xf9, 0x1e, 0xf2, 0xa6, 0xa6, 0x0d, 0x81, 0x7b, 0x26, ++ 0x18, 0x3e, 0x1a, 0x1f, 0xdd, 0x6d, 0x19, 0x46, 0x9f, 0x8b, 0x9a, 0x1b, ++ 0x98, 0xfd, 0xe0, 0x63, 0x7c, 0x23, 0xee, 0xab, 0x15, 0xf4, 0x27, 0xe4, ++ 0xff, 0x92, 0xf5, 0xfb, 0xf1, 0xde, 0x0d, 0xea, 0xb7, 0xe8, 0xf8, 0xab, ++ 0x09, 0xf2, 0xbd, 0x0b, 0x81, 0x8f, 0x0d, 0xef, 0x9b, 0x6f, 0x46, 0x3c, ++ 0x34, 0x11, 0xf6, 0xfb, 0x05, 0x02, 0x7e, 0x37, 0xe5, 0x73, 0xbb, 0xc1, ++ 0x45, 0x5c, 0x40, 0x9f, 0xda, 0x83, 0x36, 0x2b, 0x9c, 0x17, 0xb9, 0xd6, ++ 0xba, 0x49, 0xff, 0xb8, 0x03, 0xc6, 0x25, 0xce, 0x1f, 0xc9, 0x40, 0xbb, ++ 0xf3, 0xbc, 0xaa, 0x0e, 0x85, 0x7a, 0x1a, 0x1d, 0xb3, 0x1b, 0xec, 0x48, ++ 0x45, 0x2b, 0x85, 0xf7, 0x14, 0x5e, 0xa8, 0xa7, 0x02, 0xab, 0xa2, 0xf1, ++ 0x1e, 0xcf, 0x93, 0x97, 0x64, 0xa2, 0x42, 0x7e, 0x9b, 0x5d, 0x2b, 0x05, ++ 0x3b, 0xaa, 0xe7, 0xfd, 0x91, 0x78, 0xce, 0x5d, 0xd0, 0xab, 0x58, 0x6f, ++ 0x93, 0x75, 0x3d, 0xd2, 0x6b, 0x13, 0xd1, 0xfb, 0xa3, 0xf5, 0xd4, 0xf1, ++ 0x81, 0xfd, 0xcf, 0xfa, 0xed, 0x89, 0x98, 0xd7, 0x44, 0xfb, 0x2f, 0xec, ++ 0x00, 0x7b, 0x63, 0xbb, 0x19, 0xed, 0x09, 0x2f, 0x59, 0xe1, 0x84, 0xf3, ++ 0xf6, 0x9e, 0x47, 0xcc, 0x28, 0x27, 0xe7, 0x76, 0xc4, 0xa3, 0x3f, 0x3c, ++ 0x77, 0x2d, 0xdb, 0x27, 0x98, 0xbb, 0x2b, 0x1e, 0xcf, 0x07, 0x52, 0x7f, ++ 0x14, 0xef, 0x11, 0x16, 0xf8, 0x38, 0xb9, 0xb6, 0xd2, 0x32, 0x0c, 0xf1, ++ 0x95, 0x82, 0xf7, 0xf3, 0x90, 0x0e, 0x3d, 0x9d, 0x0b, 0x3c, 0xf5, 0xf7, ++ 0x27, 0x0d, 0x78, 0x5a, 0xb7, 0xff, 0xb0, 0x53, 0xed, 0xef, 0x5f, 0x86, ++ 0xe0, 0xe9, 0xd4, 0x00, 0x78, 0x3a, 0x15, 0x8a, 0xa7, 0x15, 0xf9, 0x5c, ++ 0x8e, 0x70, 0x3c, 0x91, 0x87, 0xb9, 0xfc, 0xb9, 0xef, 0x50, 0x06, 0xdc, ++ 0x5f, 0x75, 0xbe, 0x39, 0x12, 0xcf, 0x83, 0x18, 0xe9, 0x50, 0xe8, 0x29, ++ 0x32, 0xff, 0x06, 0xcc, 0xbf, 0x12, 0x71, 0xaa, 0x9a, 0xe1, 0x0c, 0x2f, ++ 0x44, 0x71, 0x61, 0x9e, 0xe2, 0x85, 0xf5, 0xe3, 0x11, 0x6f, 0x46, 0x7c, ++ 0xd5, 0xfc, 0x63, 0x1e, 0xe2, 0x85, 0xbc, 0x6f, 0xc3, 0xfb, 0x8b, 0x67, ++ 0xa7, 0xb1, 0x7b, 0x5b, 0xee, 0x95, 0x18, 0xbf, 0xcc, 0x5e, 0x33, 0xa5, ++ 0x06, 0xf4, 0xf9, 0xe3, 0xf9, 0xcc, 0xae, 0xf9, 0x3d, 0x95, 0x5b, 0xee, ++ 0x2c, 0x6a, 0x8f, 0x53, 0xb9, 0xe5, 0xa6, 0x72, 0xeb, 0x8f, 0x54, 0x9e, ++ 0x41, 0xf9, 0xdd, 0x95, 0x4e, 0x2c, 0xbf, 0xb7, 0x52, 0xc5, 0xe7, 0x9f, ++ 0x56, 0x66, 0xe3, 0xf3, 0x14, 0xdf, 0x57, 0x15, 0x7c, 0x44, 0x09, 0xc1, ++ 0x02, 0x76, 0xe3, 0x86, 0x7c, 0x26, 0xc7, 0x36, 0xe4, 0x8b, 0xb8, 0xe1, ++ 0x03, 0x4e, 0x30, 0x2d, 0x6a, 0xfe, 0xf1, 0xc7, 0xf1, 0xf0, 0x3b, 0x0a, ++ 0x0e, 0xef, 0x94, 0x3b, 0xaa, 0x47, 0x12, 0x72, 0xab, 0x5b, 0xaf, 0x0f, ++ 0x67, 0xcd, 0xd4, 0xeb, 0xbb, 0x1e, 0xb3, 0x7d, 0xb2, 0x13, 0xfc, 0xdb, ++ 0x47, 0xd9, 0x3d, 0x4c, 0x73, 0x3d, 0x37, 0xea, 0xea, 0x13, 0x45, 0xb5, ++ 0xc0, 0x79, 0x68, 0x92, 0x3d, 0x2e, 0xf8, 0x1e, 0xf9, 0x4d, 0xb5, 0xc0, ++ 0x7d, 0xe9, 0x77, 0xd5, 0x26, 0xea, 0xea, 0xdf, 0xb1, 0x2e, 0x59, 0x57, ++ 0xfe, 0xcf, 0x7c, 0x15, 0xd7, 0x7d, 0x5b, 0x4d, 0x9a, 0xee, 0xfd, 0xdd, ++ 0x75, 0x79, 0xba, 0x72, 0x3d, 0xdc, 0x9b, 0x08, 0x74, 0xae, 0x4e, 0x40, ++ 0xbe, 0x79, 0x80, 0xe7, 0x55, 0x52, 0x07, 0x9d, 0xe1, 0x85, 0x9f, 0x23, ++ 0xfc, 0xba, 0xb9, 0x74, 0xe8, 0xf7, 0xe9, 0x7c, 0xbf, 0x3e, 0x6a, 0xc6, ++ 0xef, 0x46, 0x7c, 0x08, 0xbc, 0xce, 0xdf, 0x24, 0x13, 0x8d, 0xf6, 0x37, ++ 0x6f, 0x13, 0x95, 0x5f, 0x74, 0x8a, 0xa7, 0xda, 0x28, 0x9e, 0x68, 0xbb, ++ 0x2f, 0x4e, 0xd8, 0xd0, 0x0f, 0x69, 0xdd, 0x35, 0xee, 0x9d, 0x09, 0xb4, ++ 0x7c, 0x72, 0x97, 0x19, 0xe3, 0x07, 0x27, 0xd7, 0x26, 0xfe, 0x04, 0xec, ++ 0xa7, 0x93, 0xbb, 0x1c, 0xb1, 0x84, 0x3e, 0xb5, 0x56, 0x99, 0xdb, 0x19, ++ 0x76, 0xbc, 0x4f, 0x49, 0xf4, 0x5b, 0xb9, 0x76, 0x15, 0x9e, 0x87, 0xa9, ++ 0xf7, 0x45, 0xb8, 0xd0, 0x9e, 0xe8, 0xf2, 0xfe, 0xbb, 0x28, 0xab, 0xe0, ++ 0xb7, 0xc2, 0x24, 0x81, 0x6f, 0x8e, 0xcb, 0x3e, 0xbf, 0x84, 0xf8, 0x63, ++ 0xf1, 0x83, 0x9d, 0x11, 0x68, 0x0f, 0x9f, 0xa6, 0x76, 0x1d, 0x5c, 0x3d, ++ 0x7b, 0x5a, 0x22, 0x6b, 0xe1, 0x09, 0x07, 0xe6, 0xe3, 0xe8, 0xf7, 0x6f, ++ 0xba, 0x1d, 0x3e, 0xe0, 0xeb, 0x9a, 0x7f, 0xc8, 0x6e, 0x27, 0xd0, 0xd3, ++ 0xce, 0x48, 0x76, 0x7f, 0x08, 0x38, 0xc3, 0xf4, 0xfb, 0xe7, 0xc7, 0x32, ++ 0xb6, 0x3e, 0x86, 0xf4, 0xa5, 0xb6, 0xfb, 0x91, 0x7f, 0x23, 0xd0, 0x5f, ++ 0x98, 0xd7, 0xc3, 0xd6, 0x47, 0xa4, 0xb1, 0xc9, 0x80, 0xff, 0xd3, 0xf1, ++ 0xc4, 0x1d, 0x4f, 0x27, 0xd1, 0xb8, 0xe2, 0xbd, 0x8f, 0x14, 0x8a, 0xa7, ++ 0xc5, 0x99, 0xdd, 0x85, 0x7e, 0xda, 0xae, 0x2e, 0xc5, 0xef, 0xb8, 0x93, ++ 0xb6, 0x3b, 0xbb, 0xcd, 0xcc, 0xee, 0x97, 0xa3, 0xfd, 0xda, 0x69, 0xb9, ++ 0xf1, 0x97, 0x11, 0x5b, 0x98, 0x3c, 0x71, 0x0f, 0xbd, 0xad, 0x20, 0x14, ++ 0x9e, 0xbe, 0x42, 0x58, 0x77, 0xd6, 0x70, 0xcf, 0x87, 0xf9, 0xb0, 0x7f, ++ 0xb0, 0xd0, 0x57, 0x88, 0x72, 0xed, 0x61, 0x07, 0xf2, 0x95, 0x11, 0xee, ++ 0xa7, 0x2c, 0x1a, 0xc2, 0xd7, 0x0b, 0x7c, 0x20, 0x05, 0xe5, 0x64, 0x90, ++ 0xcf, 0xd8, 0x7e, 0x10, 0x15, 0x6e, 0xc3, 0x40, 0xde, 0xcc, 0x33, 0xbb, ++ 0x86, 0x80, 0xbe, 0x3a, 0xb5, 0xde, 0x8c, 0x76, 0x29, 0xd5, 0x27, 0xb1, ++ 0xb7, 0x61, 0x1c, 0x66, 0x0f, 0xd2, 0xf1, 0x29, 0x45, 0x9d, 0x0c, 0xeb, ++ 0x3e, 0xb5, 0x2e, 0x85, 0x80, 0xdc, 0x12, 0xe3, 0xce, 0x5d, 0x2f, 0xf3, ++ 0x7b, 0x42, 0x28, 0x5d, 0x42, 0xfd, 0x0d, 0xb2, 0x46, 0x6d, 0x07, 0x22, ++ 0xf4, 0x96, 0x77, 0x9d, 0xa4, 0x91, 0xa1, 0xfd, 0xe9, 0xe6, 0xfe, 0xfb, ++ 0x4a, 0x31, 0x2f, 0xdc, 0x68, 0xff, 0x8a, 0xe7, 0x97, 0x94, 0x57, 0xb5, ++ 0x10, 0x3b, 0x62, 0xc9, 0x6b, 0xec, 0x7e, 0x7e, 0x52, 0xdc, 0xa3, 0xcc, ++ 0x2c, 0x08, 0x5d, 0x07, 0xfb, 0x7d, 0x05, 0xa2, 0x4d, 0xd0, 0xe5, 0x6b, ++ 0x2e, 0x4b, 0xfd, 0xed, 0x47, 0x31, 0x26, 0xb4, 0x6b, 0xe2, 0x20, 0x9e, ++ 0x7e, 0xe6, 0xb8, 0x8c, 0x74, 0x76, 0x26, 0xb5, 0xad, 0xc4, 0x49, 0x49, ++ 0xff, 0xac, 0xe9, 0x40, 0xc9, 0xf7, 0x69, 0xf9, 0x8b, 0x69, 0xde, 0x4f, ++ 0x15, 0x5a, 0xbe, 0x6f, 0xb4, 0x16, 0x55, 0x40, 0x97, 0xb4, 0xd4, 0xb4, ++ 0x7e, 0x14, 0xf8, 0x4f, 0xbd, 0x9d, 0x9f, 0xfc, 0x04, 0xee, 0xdd, 0xfb, ++ 0xfc, 0x45, 0x33, 0x1c, 0x87, 0x27, 0x4b, 0x76, 0x2e, 0x1e, 0x8d, 0x71, ++ 0x1f, 0x6e, 0x7f, 0xf7, 0x97, 0x5b, 0xe2, 0xfe, 0x3f, 0xf7, 0x30, 0xb8, ++ 0x3f, 0x65, 0xa9, 0xda, 0x8e, 0x7a, 0x5c, 0x85, 0x43, 0x72, 0xb8, 0x7e, ++ 0x1f, 0xce, 0x53, 0xe8, 0x75, 0xfb, 0x93, 0x12, 0xd8, 0x58, 0xe4, 0x93, ++ 0xf1, 0xb6, 0xc7, 0xc0, 0x9f, 0x9e, 0x67, 0x38, 0x9f, 0xf2, 0x89, 0x99, ++ 0xd9, 0x09, 0x23, 0x0a, 0x98, 0x9c, 0x12, 0xfa, 0xfe, 0x1e, 0x5e, 0x9e, ++ 0x67, 0x62, 0x74, 0x4d, 0x5e, 0x97, 0x30, 0x0f, 0x9c, 0xf0, 0x7b, 0xe5, ++ 0x85, 0x3e, 0x10, 0xf2, 0x5a, 0xc8, 0xfd, 0xfc, 0x02, 0x66, 0x5f, 0x08, ++ 0x79, 0x0d, 0x99, 0x76, 0x20, 0xb7, 0x16, 0xc2, 0xed, 0x2d, 0x74, 0x9d, ++ 0xcb, 0x76, 0x44, 0xf8, 0x7c, 0x29, 0xd8, 0xd6, 0x0e, 0x70, 0x5c, 0xcc, ++ 0xd0, 0x44, 0x16, 0x17, 0xa8, 0xd8, 0x6e, 0x89, 0xe5, 0xc5, 0xa7, 0x81, ++ 0x97, 0x1a, 0x48, 0x37, 0xce, 0xff, 0x73, 0xb3, 0x6f, 0x61, 0x77, 0x0a, ++ 0xb4, 0xdf, 0xb2, 0x36, 0x01, 0xdb, 0x9b, 0x5d, 0x18, 0xa7, 0xe5, 0xfa, ++ 0x05, 0xae, 0xb5, 0x06, 0xb9, 0xd4, 0xc0, 0xf9, 0xaf, 0xb1, 0x4d, 0xf2, ++ 0xf9, 0x91, 0x7f, 0x98, 0x9e, 0x5c, 0xc0, 0xfb, 0x27, 0xa0, 0x67, 0x42, ++ 0xe4, 0x58, 0x3f, 0xfd, 0x62, 0xd0, 0x2b, 0x0b, 0xb8, 0x5e, 0x5d, 0x40, ++ 0x0c, 0x71, 0xde, 0x36, 0xbd, 0xbe, 0xf3, 0x44, 0xdb, 0x70, 0x5d, 0x4b, ++ 0xe8, 0xb8, 0xa0, 0x3f, 0x83, 0xf3, 0xa2, 0xf6, 0x33, 0x85, 0xdd, 0x42, ++ 0xcd, 0x77, 0x78, 0x3a, 0xce, 0x5b, 0x72, 0xf9, 0xc2, 0xcc, 0xa3, 0x81, ++ 0x04, 0xfc, 0x90, 0x7f, 0xd7, 0xb8, 0x8b, 0xc5, 0xbd, 0x8d, 0xf3, 0x32, ++ 0xae, 0x63, 0xb0, 0xf3, 0x5c, 0xe8, 0xba, 0xad, 0x2a, 0xbe, 0x38, 0x64, ++ 0x5c, 0xc3, 0xbc, 0x05, 0xbc, 0x31, 0x50, 0x1c, 0x82, 0x07, 0x01, 0xf7, ++ 0x85, 0x5e, 0x06, 0xcf, 0x85, 0x9d, 0x12, 0xe2, 0xeb, 0x2f, 0xdc, 0x5e, ++ 0xa3, 0x7f, 0x18, 0x9f, 0x36, 0xe2, 0xbf, 0x81, 0x78, 0xa6, 0x43, 0x9e, ++ 0x42, 0xc3, 0x93, 0x54, 0x7e, 0xa6, 0x04, 0xe9, 0x41, 0xd0, 0xc1, 0xe2, ++ 0xdd, 0x3e, 0x0b, 0xd8, 0xcb, 0x5f, 0x90, 0xb6, 0xd8, 0x18, 0xca, 0x07, ++ 0xcb, 0x36, 0xed, 0xbe, 0x63, 0xa2, 0x0a, 0xfe, 0xf3, 0x31, 0xf4, 0x43, ++ 0xea, 0x12, 0xfc, 0x19, 0xa6, 0x78, 0x42, 0x12, 0xbd, 0x2f, 0x3d, 0x5d, ++ 0x73, 0xd3, 0xb5, 0xe3, 0xfc, 0xff, 0x2a, 0x38, 0xc1, 0x2a, 0xe0, 0x7e, ++ 0x5a, 0x6c, 0x47, 0xe1, 0xb2, 0x60, 0x9b, 0xec, 0x8e, 0x2c, 0xd4, 0xd5, ++ 0xe3, 0x79, 0xda, 0x5e, 0x84, 0xd7, 0x22, 0xaf, 0xd7, 0x02, 0x71, 0xd0, ++ 0x45, 0x3c, 0xae, 0x78, 0xad, 0x79, 0x36, 0x29, 0xec, 0x3c, 0xef, 0xb5, ++ 0xe7, 0xcb, 0xe0, 0xf8, 0xaf, 0x9e, 0xf7, 0xd3, 0x05, 0x7a, 0x3b, 0x36, ++ 0x68, 0x1f, 0x65, 0x84, 0xf5, 0xb7, 0xfa, 0xec, 0xa2, 0x6b, 0xe8, 0xe3, ++ 0x0f, 0xcc, 0xfe, 0x91, 0xa0, 0x8f, 0x03, 0x23, 0x15, 0xd4, 0x47, 0x5f, ++ 0x2b, 0xae, 0xf7, 0xca, 0x93, 0x40, 0x3f, 0x67, 0xa0, 0xdf, 0x30, 0x90, ++ 0xbc, 0x5d, 0xc8, 0xf5, 0xf2, 0x02, 0xd0, 0xd3, 0xf4, 0xf9, 0xe9, 0xa6, ++ 0xbd, 0x78, 0x6e, 0xec, 0x2f, 0x4f, 0xee, 0xc5, 0x7d, 0x43, 0xcb, 0x8b, ++ 0x0b, 0x62, 0xc1, 0x5e, 0xfe, 0x74, 0xd3, 0xbc, 0x9f, 0x40, 0xde, 0xfc, ++ 0xa7, 0xbb, 0xe6, 0xa1, 0x5e, 0x6e, 0x78, 0x46, 0xe8, 0x65, 0xcd, 0x12, ++ 0xaa, 0xef, 0x2b, 0x37, 0xd5, 0x3f, 0xf7, 0x7f, 0x80, 0x4e, 0x77, 0x44, ++ 0xe2, 0x09, 0x85, 0x85, 0x5d, 0x1a, 0xb7, 0xc7, 0xa9, 0xfc, 0x03, 0xb9, ++ 0xb8, 0x89, 0xc9, 0x3f, 0xf2, 0x24, 0x93, 0x8f, 0x0d, 0xb1, 0xec, 0xde, ++ 0x6f, 0xaa, 0xbf, 0xb2, 0xa0, 0xde, 0x83, 0x0b, 0xb5, 0x2c, 0xa0, 0xf7, ++ 0x90, 0xf7, 0xa8, 0xd7, 0x1e, 0x9c, 0xa7, 0x95, 0x62, 0x7b, 0x62, 0xf7, ++ 0xb3, 0x7b, 0x21, 0xed, 0x7e, 0xd0, 0x5f, 0x42, 0xbf, 0x0a, 0xbd, 0x7b, ++ 0x74, 0x98, 0xd6, 0x55, 0x00, 0x7a, 0x41, 0x3e, 0xfa, 0xee, 0x43, 0x74, ++ 0xfd, 0xe7, 0xf6, 0xc8, 0x18, 0xd3, 0x69, 0x94, 0xb7, 0x8c, 0x82, 0xdf, ++ 0x43, 0x18, 0x48, 0x8e, 0xff, 0xf3, 0xf0, 0x36, 0xf5, 0xc1, 0x3b, 0x65, ++ 0x10, 0xf0, 0x9e, 0x0b, 0xf0, 0x46, 0x7b, 0x88, 0xc1, 0xfb, 0xe3, 0x75, ++ 0x0c, 0xce, 0x9f, 0xac, 0x67, 0x70, 0x6f, 0xdd, 0x95, 0x16, 0x0b, 0x7e, ++ 0xf0, 0xc7, 0xeb, 0xd2, 0xd0, 0x0e, 0xfa, 0x78, 0x57, 0x06, 0xc2, 0x7b, ++ 0xfe, 0x63, 0x14, 0xde, 0x68, 0x07, 0xab, 0x7a, 0x3b, 0x68, 0x1d, 0x85, ++ 0x37, 0xd8, 0xff, 0x00, 0x6f, 0x3a, 0xee, 0xdc, 0x2e, 0x95, 0xc3, 0xdb, ++ 0xc5, 0xe0, 0xbd, 0x8e, 0xeb, 0xa1, 0xf5, 0xec, 0x39, 0xbf, 0x1f, 0x5c, ++ 0xbd, 0x98, 0x6f, 0xfa, 0xe0, 0xf3, 0x11, 0x2e, 0xd0, 0xef, 0xa7, 0x23, ++ 0xfd, 0x0e, 0xf0, 0x53, 0x4e, 0xef, 0x96, 0x09, 0xec, 0xe7, 0xf7, 0xd9, ++ 0x49, 0xdc, 0x9e, 0x11, 0x70, 0xfe, 0x86, 0xb4, 0xfd, 0x3b, 0xd8, 0x55, ++ 0xfd, 0xec, 0x9b, 0x0d, 0x11, 0xc4, 0x4e, 0xfb, 0x5b, 0xfc, 0x92, 0x0d, ++ 0xcf, 0xd5, 0x7c, 0x2e, 0x95, 0x0f, 0x05, 0x04, 0x9c, 0x6d, 0xfb, 0x6d, ++ 0x2c, 0x8c, 0x17, 0x1c, 0xbf, 0xcf, 0xae, 0xb9, 0x54, 0x10, 0x6a, 0xd7, ++ 0x0c, 0x12, 0x3f, 0xcb, 0x89, 0x07, 0xf3, 0xde, 0x97, 0x77, 0xfe, 0xf6, ++ 0x04, 0xd8, 0xf5, 0x70, 0xbd, 0x0a, 0xf8, 0xfd, 0xcb, 0xc5, 0x39, 0xf8, ++ 0x0e, 0xfd, 0x39, 0x78, 0x49, 0x05, 0x99, 0x06, 0x21, 0x0a, 0x97, 0xd5, ++ 0x0a, 0x74, 0x30, 0xc2, 0x78, 0x4f, 0x80, 0x86, 0xbf, 0x0f, 0x71, 0x31, ++ 0xe3, 0xab, 0x39, 0x2b, 0x90, 0x9f, 0x03, 0x99, 0xa1, 0xfb, 0x41, 0x4d, ++ 0x51, 0x7e, 0x33, 0xc4, 0xa3, 0x02, 0xbb, 0x25, 0xc4, 0x77, 0xe3, 0x03, ++ 0xe5, 0xb1, 0xe5, 0x04, 0xf6, 0xb3, 0x9a, 0x71, 0x1e, 0x8e, 0x42, 0xa6, ++ 0x9f, 0x25, 0xb7, 0x1b, 0xe3, 0x8c, 0x11, 0x94, 0x6e, 0xa2, 0xe8, 0x78, ++ 0xce, 0x42, 0x15, 0xe7, 0x2b, 0xa9, 0x76, 0x16, 0x77, 0xdc, 0x4c, 0xc7, ++ 0xb5, 0x05, 0xe7, 0x6b, 0x7c, 0x3f, 0x1d, 0x04, 0x11, 0xe8, 0xf7, 0x18, ++ 0x13, 0xea, 0x77, 0xe3, 0xfa, 0x27, 0xf3, 0x71, 0x1a, 0x65, 0x13, 0xfa, ++ 0x21, 0xcb, 0x2c, 0xcc, 0x1f, 0x11, 0x79, 0x13, 0x19, 0xfc, 0x7b, 0x46, ++ 0x21, 0xf3, 0xeb, 0xf3, 0x0a, 0xd9, 0x3e, 0x43, 0x6f, 0x24, 0x41, 0xfd, ++ 0xd1, 0xbb, 0x21, 0xda, 0xb7, 0x0a, 0xd7, 0x57, 0x85, 0xf1, 0x4f, 0x85, ++ 0x30, 0xfa, 0x56, 0x04, 0xdc, 0xec, 0xca, 0x97, 0xba, 0x7b, 0xca, 0x79, ++ 0x7c, 0x01, 0x7e, 0xbf, 0x00, 0x8c, 0xea, 0xf9, 0x11, 0x3c, 0xfe, 0x4b, ++ 0x55, 0x2d, 0xb4, 0xbf, 0x87, 0xb7, 0xbf, 0xa7, 0xed, 0x6d, 0xdc, 0xcf, ++ 0xa3, 0x9e, 0xcc, 0x2f, 0x40, 0xff, 0xce, 0x6e, 0x89, 0x70, 0x81, 0x3d, ++ 0xeb, 0x85, 0xfb, 0xad, 0x28, 0xdd, 0xfd, 0x38, 0x8a, 0xed, 0xbf, 0x90, ++ 0xa4, 0x38, 0x05, 0xf8, 0xea, 0x6e, 0x2e, 0x67, 0xef, 0x69, 0x7b, 0xdc, ++ 0x03, 0xfa, 0x68, 0x76, 0x5b, 0xb4, 0x1b, 0x9e, 0x74, 0x1c, 0x2f, 0xe1, ++ 0xf1, 0xd6, 0x62, 0xd8, 0xbf, 0x1d, 0x6e, 0xc1, 0x78, 0x6b, 0x9d, 0xb5, ++ 0xe7, 0x45, 0x30, 0xaf, 0xef, 0x75, 0x7e, 0xf2, 0x3d, 0x2b, 0x5d, 0xda, ++ 0x2a, 0x13, 0xb3, 0x5f, 0x56, 0x25, 0x10, 0xcc, 0x3b, 0x19, 0x43, 0xcd, ++ 0x78, 0x88, 0xdf, 0xd2, 0x4f, 0xfb, 0xae, 0x24, 0x5e, 0x8d, 0x7e, 0xf4, ++ 0xf1, 0xe4, 0x65, 0x10, 0xd7, 0x65, 0xf7, 0xb5, 0x79, 0x51, 0x9e, 0xc8, ++ 0x26, 0x5d, 0x79, 0x19, 0xff, 0x5d, 0x81, 0xba, 0xc2, 0xcc, 0x3b, 0x9f, ++ 0x1c, 0x41, 0xc8, 0x1f, 0x88, 0x5a, 0x00, 0xf8, 0x5e, 0x06, 0xb0, 0x01, ++ 0x7a, 0xa8, 0x8f, 0xc3, 0xf8, 0xc0, 0xad, 0x10, 0x5f, 0x4e, 0x80, 0xa7, ++ 0x82, 0x74, 0x36, 0x43, 0x21, 0x5e, 0x13, 0x7b, 0xae, 0x8b, 0xc1, 0x73, ++ 0xfe, 0x2c, 0xde, 0x3c, 0x9d, 0xaf, 0xfb, 0xbb, 0x13, 0x88, 0x3f, 0x8e, ++ 0xae, 0xd7, 0xff, 0xa6, 0x3e, 0xde, 0x7d, 0xa7, 0xdf, 0xe4, 0xcf, 0xa2, ++ 0x78, 0xb8, 0x55, 0xf1, 0xef, 0x07, 0xba, 0x36, 0x59, 0x55, 0x33, 0xf8, ++ 0x07, 0x9e, 0x1a, 0x69, 0x2c, 0xf8, 0xcd, 0xcb, 0x56, 0x0f, 0x6e, 0xbe, ++ 0x4d, 0x85, 0x45, 0x38, 0xdf, 0x65, 0x26, 0x13, 0x9b, 0xe7, 0x43, 0x12, ++ 0xde, 0xcb, 0x70, 0x0f, 0x65, 0x72, 0xa0, 0xcf, 0x39, 0x0a, 0xe9, 0x92, ++ 0xc7, 0x32, 0xfc, 0x01, 0xfd, 0x35, 0x25, 0xb0, 0x7b, 0x80, 0x03, 0xf7, ++ 0x31, 0xfa, 0x16, 0x71, 0x76, 0x81, 0xa7, 0x22, 0xda, 0x7d, 0x28, 0x7c, ++ 0xef, 0xe1, 0xf3, 0xa3, 0xfd, 0xac, 0x8b, 0x85, 0xf6, 0x96, 0xf0, 0xf1, ++ 0xa5, 0x1f, 0x16, 0x0a, 0xbf, 0x98, 0xd9, 0x9d, 0x4b, 0x39, 0xbf, 0x2e, ++ 0x15, 0xf4, 0xb6, 0x4b, 0xcf, 0xa7, 0xcf, 0x02, 0xbf, 0x00, 0x1f, 0x81, ++ 0x9d, 0x4b, 0xe1, 0x76, 0x0f, 0x7f, 0x0e, 0x44, 0xef, 0x9b, 0x38, 0xbd, ++ 0x6f, 0xe2, 0xf4, 0xde, 0xca, 0xcb, 0x83, 0x1d, 0xaf, 0x31, 0x82, 0xf8, ++ 0x43, 0x7f, 0xaf, 0x45, 0x8c, 0x7b, 0x2b, 0x7f, 0x3e, 0x5d, 0x98, 0x8a, ++ 0xfd, 0x89, 0x79, 0x08, 0x7a, 0x26, 0x3c, 0x3e, 0x65, 0xa2, 0x92, 0x03, ++ 0xe8, 0xe8, 0x54, 0xdb, 0x1a, 0xb4, 0x9b, 0x16, 0x19, 0xe2, 0xc5, 0x24, ++ 0x34, 0x8e, 0x25, 0x87, 0x2b, 0xf7, 0xc9, 0x1f, 0xd3, 0x15, 0x78, 0x5a, ++ 0x02, 0xf3, 0x61, 0x3e, 0xd2, 0x77, 0x22, 0x5d, 0x40, 0xd7, 0xf7, 0x58, ++ 0xda, 0x33, 0xd8, 0xbd, 0x12, 0xfa, 0x7a, 0x62, 0xff, 0xb7, 0x0e, 0x6e, ++ 0xee, 0xc2, 0xf3, 0x3a, 0x44, 0xf7, 0x7b, 0x0a, 0xd5, 0x72, 0x0c, 0xe6, ++ 0x13, 0xd5, 0x49, 0xec, 0x5e, 0x99, 0xde, 0x72, 0x9b, 0xd7, 0x44, 0xed, ++ 0xc5, 0x0f, 0xf8, 0xbd, 0x0e, 0xe7, 0x9b, 0xd9, 0xf9, 0xd0, 0xba, 0x87, ++ 0xf8, 0xef, 0xa0, 0xc4, 0x3d, 0x38, 0x1d, 0xec, 0xc3, 0xba, 0x58, 0x8b, ++ 0x02, 0xcf, 0x0f, 0xf8, 0xfd, 0x72, 0xf7, 0x92, 0x6e, 0x5b, 0x4a, 0x4a, ++ 0xd0, 0x3e, 0x69, 0x2d, 0x97, 0xf9, 0xef, 0x6e, 0xcc, 0xbd, 0xd3, 0x9d, ++ 0x0f, 0xf7, 0x44, 0x10, 0x51, 0xde, 0xe8, 0x1e, 0x81, 0x51, 0x25, 0x5e, ++ 0x6e, 0x78, 0x0f, 0xf6, 0x3b, 0x66, 0x5e, 0xa6, 0x74, 0x80, 0xe5, 0x45, ++ 0x77, 0xba, 0xa9, 0xdc, 0xe8, 0x3d, 0xc4, 0xbf, 0x7b, 0x69, 0x19, 0xf0, ++ 0xf8, 0x88, 0xa0, 0xe7, 0x46, 0xec, 0xaf, 0xf7, 0x29, 0xf1, 0xfd, 0x3e, ++ 0x56, 0x7e, 0x54, 0x7c, 0x7f, 0x90, 0x95, 0xff, 0x4d, 0xf4, 0xcf, 0xcb, ++ 0x1b, 0x0c, 0xdf, 0x57, 0x19, 0xbe, 0xff, 0x9c, 0x95, 0xdf, 0x2c, 0x7c, ++ 0xf0, 0x4e, 0x2f, 0xd8, 0xb5, 0x7c, 0x1f, 0xa7, 0xee, 0x06, 0x09, 0xe5, ++ 0x8a, 0x95, 0xd3, 0x5b, 0xdd, 0x6a, 0x3f, 0xc2, 0xb9, 0xce, 0x74, 0x80, ++ 0x3d, 0x2b, 0x88, 0x1f, 0xce, 0xd7, 0x5e, 0xab, 0xde, 0x37, 0x85, 0x1e, ++ 0x6b, 0xa1, 0x03, 0xee, 0x37, 0x38, 0x65, 0x03, 0xfd, 0xfd, 0xad, 0xcb, ++ 0x8d, 0xe5, 0xf3, 0xf9, 0xda, 0xf1, 0x42, 0x5a, 0x7f, 0xc9, 0x6d, 0x92, ++ 0xd7, 0x02, 0xf2, 0xf2, 0xb8, 0x2f, 0x93, 0xcb, 0xf7, 0xb0, 0x79, 0xb9, ++ 0x56, 0x4e, 0xbf, 0x17, 0xc6, 0xd0, 0xfe, 0xc6, 0x07, 0xe1, 0x4d, 0xfb, ++ 0xf9, 0xf0, 0x9f, 0xe9, 0x67, 0x75, 0xff, 0x7e, 0x3e, 0x85, 0x79, 0x5d, ++ 0x6f, 0x3f, 0xd3, 0x5d, 0x6c, 0x7d, 0x21, 0xfd, 0xf4, 0xfe, 0x33, 0xfd, ++ 0xec, 0x75, 0xe9, 0xe7, 0x23, 0xec, 0xa3, 0xa9, 0x63, 0xdd, 0x51, 0x63, ++ 0x40, 0x3e, 0x54, 0xdd, 0xa8, 0x8b, 0xfb, 0x2d, 0xfd, 0x91, 0x2b, 0x0e, ++ 0xec, 0x2b, 0xf2, 0x0e, 0xfb, 0x1d, 0x93, 0xa5, 0xab, 0xdb, 0x47, 0x8d, ++ 0xa3, 0xfd, 0x2f, 0xfd, 0xaf, 0x57, 0x46, 0x2d, 0x0c, 0xf1, 0xc7, 0x97, ++ 0x5f, 0x92, 0x89, 0x1b, 0xee, 0x47, 0xb8, 0x24, 0xe1, 0xf3, 0x8b, 0xfd, ++ 0x7f, 0xb2, 0xc0, 0xf9, 0xfc, 0xe5, 0xfb, 0xf6, 0x5b, 0x26, 0xe7, 0xc3, ++ 0xef, 0x2f, 0xec, 0xb7, 0x54, 0x86, 0xcc, 0x6b, 0x99, 0xc8, 0xb3, 0x24, ++ 0x3d, 0xca, 0x8c, 0x10, 0xfd, 0x1e, 0x37, 0xc6, 0xc4, 0xe5, 0x06, 0xfb, ++ 0x1d, 0x87, 0xa5, 0xff, 0x75, 0x46, 0x01, 0x7c, 0x2e, 0x35, 0xb5, 0x7f, ++ 0xfa, 0x0c, 0xc4, 0x81, 0x6e, 0x90, 0xc2, 0xee, 0xd7, 0xfe, 0x95, 0xaf, ++ 0xef, 0xa3, 0x01, 0xce, 0x83, 0x39, 0xc6, 0x30, 0xf9, 0x57, 0x56, 0xec, ++ 0x4e, 0x82, 0x75, 0x5e, 0x04, 0x19, 0x44, 0xeb, 0x57, 0xae, 0x09, 0xbf, ++ 0xcf, 0x3f, 0x67, 0x0c, 0x8b, 0x27, 0xd6, 0xf1, 0x7b, 0x95, 0xe7, 0x95, ++ 0xd8, 0xac, 0x2a, 0x85, 0xf3, 0xf8, 0xe3, 0x6c, 0x7f, 0x7a, 0xe1, 0xe6, ++ 0x94, 0xb1, 0x10, 0xe7, 0x75, 0x14, 0x54, 0x8c, 0x1a, 0x03, 0xf3, 0x1d, ++ 0x30, 0x5e, 0x1a, 0x60, 0xf1, 0xd2, 0x4e, 0x16, 0x2f, 0xad, 0x4b, 0xe8, ++ 0x7e, 0x00, 0xee, 0x31, 0xbd, 0xeb, 0x57, 0x4f, 0x6d, 0x84, 0x7b, 0x4d, ++ 0xa7, 0x6e, 0x14, 0x7c, 0x42, 0xf0, 0xf7, 0x72, 0x6a, 0x22, 0x04, 0xdf, ++ 0xed, 0xba, 0xb3, 0xaa, 0x0c, 0xe3, 0x5f, 0x58, 0x2e, 0x1b, 0xf3, 0xc2, ++ 0x46, 0xe0, 0x9b, 0x23, 0xfc, 0x5e, 0xf1, 0xd9, 0xa5, 0x05, 0x51, 0x20, ++ 0x1f, 0x7a, 0x52, 0xa2, 0x4d, 0x76, 0x2a, 0x47, 0x46, 0xe4, 0xd7, 0xdf, ++ 0x05, 0xf3, 0x98, 0x5d, 0x7a, 0xd3, 0x64, 0x78, 0x5f, 0x1e, 0x61, 0xcb, ++ 0xac, 0x67, 0x71, 0x77, 0xa4, 0x8b, 0x11, 0xf9, 0x9e, 0x62, 0xf8, 0x0e, ++ 0xf5, 0x21, 0xde, 0xa1, 0x59, 0x58, 0xfc, 0x4b, 0x7b, 0x4b, 0xc6, 0xf8, ++ 0x97, 0x56, 0x18, 0xad, 0x85, 0xdb, 0x7f, 0x1e, 0xcb, 0xe1, 0x70, 0xd7, ++ 0x18, 0x76, 0x4f, 0xf1, 0x11, 0x13, 0x9d, 0xe7, 0xd8, 0xe0, 0x3c, 0xc4, ++ 0xf8, 0xd4, 0x60, 0x79, 0xa0, 0x9b, 0xf6, 0x77, 0x6a, 0xf5, 0xb0, 0x22, ++ 0xb8, 0x97, 0xbf, 0x25, 0xbf, 0x7c, 0x16, 0xd2, 0x13, 0x1f, 0xbf, 0x25, ++ 0x5f, 0xab, 0x86, 0xb2, 0x18, 0x9f, 0x2e, 0xb7, 0x10, 0xde, 0x0f, 0x76, ++ 0x1e, 0x15, 0x9c, 0x2e, 0x66, 0x8d, 0x61, 0x78, 0xf3, 0x94, 0x51, 0x7a, ++ 0x0b, 0xf1, 0x1b, 0x67, 0x54, 0x45, 0xeb, 0xca, 0x33, 0x6b, 0x13, 0x89, ++ 0x3b, 0x34, 0x0e, 0x3b, 0x33, 0x59, 0x57, 0x9e, 0x55, 0x97, 0xa6, 0xab, ++ 0x7f, 0xf7, 0xfc, 0x3c, 0xdd, 0xf7, 0x69, 0x11, 0xdd, 0xc5, 0xcd, 0xd7, ++ 0x61, 0x07, 0x37, 0xd9, 0x6c, 0x51, 0x60, 0x8f, 0x7d, 0xd8, 0xf9, 0xcd, ++ 0x7f, 0xdf, 0x03, 0xf6, 0xdd, 0x36, 0xd9, 0x25, 0xd1, 0xf5, 0x2c, 0x7e, ++ 0x6d, 0xfb, 0x7f, 0xc3, 0xef, 0xa3, 0x9c, 0x87, 0x1f, 0x5c, 0x60, 0xe7, ++ 0xaf, 0x30, 0x1e, 0xf6, 0xf9, 0x11, 0xf6, 0x7b, 0x7f, 0xd4, 0xae, 0x53, ++ 0x42, 0xf7, 0x75, 0xce, 0x91, 0x6e, 0xcc, 0x2b, 0x0c, 0xd9, 0x2f, 0x08, ++ 0xbb, 0x9f, 0x2a, 0xf6, 0x0b, 0x96, 0xda, 0xbb, 0x30, 0xff, 0xef, 0x7f, ++ 0xbb, 0xaf, 0xd3, 0x32, 0x86, 0xef, 0x17, 0x8c, 0x25, 0x63, 0x41, 0x1f, ++ 0x9e, 0x6f, 0x7e, 0x17, 0xe3, 0x70, 0xcb, 0x63, 0xd8, 0xba, 0xce, 0xbd, ++ 0xc2, 0xef, 0x21, 0x07, 0x3d, 0x42, 0xe9, 0xfc, 0x66, 0x68, 0x08, 0xf7, ++ 0x85, 0x5d, 0x5a, 0x85, 0xbf, 0xef, 0x53, 0xc9, 0x7f, 0xbf, 0x75, 0xd8, ++ 0x18, 0x95, 0xf9, 0x05, 0x23, 0xee, 0x53, 0xe0, 0xdc, 0x77, 0x13, 0x7d, ++ 0x82, 0xfc, 0x9f, 0x4c, 0xe5, 0x54, 0x1c, 0xa5, 0x93, 0xee, 0xfd, 0xa4, ++ 0x60, 0x1f, 0xe4, 0x5d, 0xa4, 0xd8, 0x30, 0x9f, 0xbc, 0xf1, 0xd2, 0xed, ++ 0x18, 0xe7, 0x3e, 0x12, 0xe5, 0xcd, 0xbf, 0x8f, 0xd6, 0x5b, 0xba, 0x6e, ++ 0x0a, 0x96, 0x97, 0x5f, 0x8a, 0xc6, 0x7e, 0x7f, 0x2f, 0x77, 0x4f, 0xc6, ++ 0xbc, 0xe6, 0x97, 0xd9, 0xef, 0x21, 0x4e, 0x4b, 0x9e, 0xbd, 0x1a, 0xe6, ++ 0x0f, 0xf5, 0xef, 0xa7, 0xe3, 0x4d, 0xfb, 0xd5, 0xcd, 0x35, 0x00, 0xa7, ++ 0xe5, 0xfb, 0xd8, 0xf9, 0xa9, 0x69, 0xf2, 0x1f, 0x8a, 0xa1, 0x9f, 0x65, ++ 0x6d, 0x53, 0xb0, 0xfd, 0x34, 0x99, 0x1c, 0x91, 0xa8, 0xbd, 0x10, 0x77, ++ 0xe9, 0x1e, 0xec, 0x77, 0x1a, 0xe8, 0x7a, 0x5a, 0x96, 0x4b, 0x6c, 0x8f, ++ 0x81, 0xfe, 0x95, 0x2d, 0xfe, 0xcc, 0x67, 0x41, 0xae, 0x58, 0x6c, 0x28, ++ 0x57, 0x9a, 0x2e, 0x45, 0x62, 0xbb, 0xa9, 0x95, 0x4c, 0x4f, 0xfb, 0xc6, ++ 0x30, 0x3b, 0xc6, 0xdc, 0xc3, 0xe6, 0x55, 0x7d, 0xe9, 0x36, 0xfc, 0x2e, ++ 0xf0, 0xff, 0xc2, 0x98, 0x54, 0xdd, 0x3d, 0x32, 0x66, 0xc7, 0x36, 0x05, ++ 0xce, 0x27, 0x98, 0x7b, 0x24, 0xac, 0x7f, 0xcb, 0xa5, 0x3c, 0x7c, 0x8a, ++ 0x75, 0xbe, 0x95, 0xfd, 0x3c, 0xde, 0x57, 0x62, 0x76, 0x7c, 0x3d, 0x19, ++ 0xf2, 0x3a, 0xdf, 0x4a, 0x92, 0xec, 0x68, 0x7e, 0x18, 0xe4, 0xee, 0x85, ++ 0xe6, 0xd2, 0x38, 0x12, 0x46, 0x2e, 0xf5, 0x8d, 0x73, 0x89, 0xe5, 0x01, ++ 0x47, 0x5c, 0x62, 0x79, 0xc1, 0x2f, 0x14, 0xb9, 0x3b, 0x81, 0xbf, 0xa7, ++ 0x3f, 0xdc, 0xa3, 0xc0, 0xfe, 0x0e, 0x89, 0xb1, 0xda, 0x01, 0x5e, 0xd3, ++ 0x27, 0x14, 0xa9, 0x0b, 0x43, 0xf8, 0x49, 0x3e, 0x70, 0x97, 0x05, 0xf0, ++ 0x62, 0x7e, 0xf2, 0x98, 0x05, 0xf4, 0x7e, 0x04, 0x7d, 0x56, 0x86, 0x7c, ++ 0x6f, 0x14, 0xf9, 0xeb, 0x06, 0xb9, 0x7c, 0x80, 0xcb, 0x01, 0x71, 0x7e, ++ 0x41, 0xe8, 0x19, 0xa2, 0x76, 0xe8, 0x7e, 0x5f, 0x4d, 0xf0, 0xcb, 0xaf, ++ 0x38, 0xbf, 0x8a, 0xf6, 0xdd, 0x40, 0xeb, 0x80, 0xc7, 0x97, 0x22, 0xd0, ++ 0x9f, 0x7a, 0xa3, 0x48, 0x7b, 0x17, 0xe6, 0xdb, 0x5d, 0xce, 0x7e, 0x27, ++ 0x83, 0x28, 0xdd, 0xa3, 0x60, 0x5f, 0xe5, 0x5f, 0x35, 0x7f, 0x8a, 0x67, ++ 0xab, 0x84, 0xf6, 0x7e, 0x0f, 0xe6, 0xc5, 0x4f, 0x9f, 0xa0, 0x9a, 0x60, ++ 0xbf, 0xe0, 0xfd, 0xbe, 0x75, 0x30, 0xbe, 0xbd, 0xd6, 0x3a, 0x7e, 0xcb, ++ 0xeb, 0xff, 0x5e, 0x26, 0x2d, 0xd0, 0xef, 0xef, 0x27, 0x4d, 0xea, 0x76, ++ 0xd3, 0xfe, 0xf6, 0xff, 0x70, 0xdc, 0x38, 0x90, 0xff, 0x62, 0xdc, 0x2f, ++ 0xc6, 0xb0, 0x73, 0xc3, 0xc4, 0x1e, 0xb8, 0x0c, 0xfe, 0x5d, 0xd3, 0xeb, ++ 0xd1, 0x2a, 0xf0, 0xf7, 0x34, 0x70, 0x96, 0x8a, 0x83, 0x76, 0x2d, 0x7d, ++ 0x8f, 0xf7, 0xe5, 0x35, 0xbd, 0x1e, 0xb1, 0x55, 0xa2, 0xdf, 0x9b, 0x62, ++ 0xa9, 0x7f, 0x4b, 0xc7, 0xaf, 0x7c, 0x23, 0xd2, 0x0f, 0x74, 0xbc, 0xff, ++ 0x8d, 0x48, 0x05, 0x7f, 0xa7, 0xa8, 0x58, 0xfb, 0x02, 0xe4, 0x65, 0xe5, ++ 0x1b, 0x59, 0x55, 0xe0, 0xcf, 0xb9, 0x3b, 0x23, 0x14, 0x82, 0x76, 0x8e, ++ 0xfb, 0x2c, 0xca, 0xd5, 0x01, 0xe6, 0x7b, 0x2d, 0x39, 0x65, 0xa4, 0x33, ++ 0xc1, 0x97, 0xda, 0x3a, 0xc6, 0x2f, 0xf5, 0x9c, 0x4e, 0xe7, 0x72, 0xfe, ++ 0xd3, 0x38, 0x1f, 0x5d, 0x68, 0x1e, 0x8a, 0x7c, 0x78, 0xe1, 0x61, 0x3a, ++ 0x69, 0xd8, 0x0f, 0x7d, 0x58, 0x2a, 0xd8, 0x07, 0x76, 0x81, 0x6a, 0xc3, ++ 0xfb, 0x89, 0x05, 0x5f, 0x4e, 0x03, 0x3f, 0x88, 0xbe, 0xff, 0x7f, 0x46, ++ 0xe4, 0x8e, 0x2c, 0x00, 0x80, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xc5, 0x7d, 0x0b, 0x78, 0x54, 0xd5, ++ 0xb5, 0xf0, 0x3e, 0x73, 0xce, 0xbc, 0x92, 0x99, 0xc9, 0xe4, 0x49, 0x42, ++ 0x1e, 0x9c, 0x40, 0x08, 0x41, 0x02, 0x4c, 0x26, 0x21, 0x84, 0x10, 0x60, ++ 0x12, 0x02, 0xa2, 0x02, 0x0e, 0x50, 0x15, 0x30, 0xc8, 0x80, 0x08, 0x11, ++ 0x09, 0x09, 0x51, 0x5b, 0xac, 0xf6, 0xcf, 0x84, 0x24, 0x10, 0x45, 0x2d, ++ 0x56, 0xdb, 0x06, 0x8b, 0x74, 0xc0, 0x47, 0x51, 0x69, 0x6f, 0x40, 0x6c, ++ 0xd3, 0x16, 0x61, 0x78, 0x68, 0x63, 0xf5, 0xd3, 0x68, 0xef, 0x6d, 0xf1, ++ 0xd6, 0xda, 0xf8, 0xb8, 0x88, 0x8a, 0x35, 0x82, 0xf5, 0xa3, 0xb7, 0x28, ++ 0xff, 0x5a, 0x6b, 0xef, 0x9d, 0x99, 0x33, 0x49, 0x10, 0xed, 0xbd, 0xff, ++ 0x1f, 0xe5, 0x3b, 0x59, 0x67, 0xef, 0xb3, 0x1f, 0x6b, 0xad, 0xbd, 0x5e, ++ 0x7b, 0xed, 0x9d, 0x79, 0xe3, 0x12, 0x43, 0x2d, 0x0a, 0x63, 0xeb, 0xce, ++ 0x25, 0x32, 0x96, 0xcc, 0xd8, 0x3c, 0x95, 0x75, 0x2b, 0x49, 0x8c, 0xd5, ++ 0x9d, 0xcb, 0x65, 0xac, 0x98, 0xb1, 0xf5, 0xe7, 0x92, 0xe9, 0x7d, 0xfd, ++ 0x39, 0x3b, 0x3d, 0x57, 0x9e, 0x1b, 0x47, 0xef, 0xad, 0xe7, 0x54, 0xe6, ++ 0x03, 0x78, 0xd5, 0x39, 0x85, 0xf9, 0x00, 0xbe, 0x6a, 0xa6, 0x33, 0x68, ++ 0x4a, 0x60, 0xec, 0x42, 0x51, 0x20, 0xd3, 0x93, 0x0a, 0xed, 0xb4, 0x5c, ++ 0x3e, 0x87, 0xb9, 0x18, 0x0b, 0x6c, 0xca, 0x28, 0x09, 0x38, 0x18, 0x9b, ++ 0x7f, 0x57, 0xaf, 0x66, 0x4b, 0x61, 0x8c, 0x39, 0x2c, 0xee, 0xc7, 0xa1, ++ 0xbf, 0xf9, 0x65, 0x45, 0xe9, 0xab, 0xe1, 0xfd, 0x05, 0xfc, 0x99, 0xc1, ++ 0x58, 0xcb, 0x91, 0x25, 0x4c, 0x77, 0x42, 0xbb, 0x29, 0x7e, 0x8b, 0x0f, ++ 0xde, 0xaf, 0x82, 0xe7, 0xcc, 0xa8, 0xf2, 0x9b, 0x18, 0xf3, 0x75, 0x02, ++ 0xcc, 0x98, 0x7b, 0x76, 0x5a, 0x09, 0x7c, 0xdf, 0x9a, 0x6b, 0xba, 0x87, ++ 0x45, 0xca, 0x75, 0x8f, 0x89, 0xb1, 0x49, 0x58, 0xde, 0x4c, 0xcf, 0xf9, ++ 0xb2, 0xbe, 0xde, 0xc5, 0x58, 0x1a, 0x63, 0x37, 0xb8, 0x19, 0xff, 0xd9, ++ 0x08, 0x83, 0xcb, 0x60, 0xcc, 0x29, 0xea, 0xaf, 0x74, 0x84, 0x47, 0x9b, ++ 0xa0, 0x3d, 0x73, 0x83, 0xdd, 0xb3, 0x09, 0xc6, 0x75, 0x26, 0x45, 0x9f, ++ 0xcd, 0x00, 0x6e, 0xbc, 0x1b, 0x00, 0x40, 0x41, 0xa3, 0xd9, 0x3f, 0xd3, ++ 0x09, 0xe3, 0x6e, 0xdc, 0xae, 0x78, 0x82, 0xf0, 0xf9, 0x8d, 0xa5, 0x4e, ++ 0x1b, 0x83, 0x79, 0x96, 0x9e, 0x68, 0xb0, 0x04, 0x0a, 0x23, 0xfd, 0x2f, ++ 0x39, 0x37, 0x81, 0xe9, 0x80, 0x87, 0x45, 0xe7, 0xf2, 0xe8, 0x99, 0x3a, ++ 0x3e, 0x30, 0x01, 0xf1, 0xb0, 0xe2, 0xdc, 0xb5, 0x84, 0xaf, 0x95, 0x50, ++ 0x8e, 0x4f, 0xa6, 0x97, 0x99, 0x70, 0x3c, 0xb7, 0xd9, 0xf0, 0x77, 0x1c, ++ 0x10, 0xc0, 0xa5, 0x8c, 0xdd, 0x2a, 0xc6, 0xf7, 0x59, 0xc3, 0xe4, 0x61, ++ 0xdf, 0x81, 0xfe, 0x3f, 0x7b, 0xd9, 0x4c, 0xe5, 0x93, 0x7c, 0xc1, 0x1b, ++ 0x70, 0x3c, 0xe6, 0x90, 0xd5, 0xb3, 0x0b, 0xc6, 0x73, 0xca, 0x1e, 0x50, ++ 0x19, 0x8c, 0xe7, 0x54, 0x36, 0x73, 0x3f, 0x08, 0x43, 0x3c, 0x65, 0x66, ++ 0x41, 0x37, 0xd0, 0xeb, 0xc6, 0x0e, 0x95, 0x05, 0xa1, 0xfd, 0x55, 0xf0, ++ 0x0c, 0xc0, 0xf3, 0x54, 0x22, 0xf3, 0x25, 0x7a, 0x11, 0x9f, 0x30, 0xcf, ++ 0x02, 0xde, 0xf6, 0x05, 0xf8, 0xf7, 0x77, 0x6d, 0x5b, 0x0e, 0x1b, 0x05, ++ 0xf4, 0x6d, 0xfc, 0xd3, 0x5b, 0xda, 0x48, 0xc6, 0x6e, 0xce, 0xef, 0x99, ++ 0x10, 0x86, 0x76, 0x6b, 0x2a, 0xc3, 0xa9, 0xd7, 0x41, 0xbb, 0xa7, 0x1f, ++ 0x33, 0x7b, 0x82, 0xd0, 0xef, 0xba, 0x23, 0xaf, 0x97, 0x9a, 0xa0, 0xfc, ++ 0xc3, 0x5c, 0xdf, 0x30, 0xa6, 0x32, 0x36, 0x66, 0x78, 0x60, 0x0e, 0xce, ++ 0x67, 0xed, 0xc2, 0xd0, 0x2f, 0xcc, 0x00, 0xdf, 0x72, 0xdf, 0x33, 0xae, ++ 0x29, 0x7a, 0x04, 0x9f, 0x9d, 0x5a, 0x78, 0xb4, 0x06, 0xdf, 0x77, 0x02, ++ 0x1e, 0x83, 0x30, 0xae, 0xce, 0x7b, 0xd5, 0x39, 0x21, 0xa2, 0x17, 0x8b, ++ 0x5f, 0x30, 0x1e, 0x1f, 0x80, 0x3d, 0xa8, 0x3a, 0x7b, 0x81, 0x12, 0x4c, ++ 0x00, 0xfc, 0xb1, 0xea, 0xa9, 0x7c, 0xde, 0x36, 0x3e, 0xb6, 0xb5, 0xe7, ++ 0x46, 0x11, 0x7e, 0xce, 0x36, 0x58, 0xc7, 0x1f, 0x80, 0x76, 0xce, 0xea, ++ 0x4e, 0x0f, 0xbe, 0xaf, 0x3b, 0xb7, 0x88, 0xde, 0xdf, 0xd2, 0x7e, 0x05, ++ 0x3d, 0xcd, 0xbd, 0x57, 0x08, 0xbe, 0x8c, 0xe7, 0xfc, 0x9a, 0xb9, 0x6c, ++ 0x13, 0xf2, 0x59, 0x9d, 0x06, 0x95, 0xe1, 0xbb, 0x3a, 0x47, 0x42, 0x28, ++ 0x08, 0xf3, 0x99, 0xf7, 0x6f, 0xc0, 0x7f, 0x80, 0xf2, 0xf5, 0x07, 0x16, ++ 0xf8, 0x2b, 0x91, 0xef, 0x0a, 0x14, 0xcf, 0x68, 0x78, 0xac, 0xdb, 0x76, ++ 0x85, 0xe0, 0xf3, 0xdd, 0xf7, 0x97, 0x03, 0x5e, 0xe7, 0x7d, 0x92, 0xe2, ++ 0x69, 0x81, 0xf7, 0xbf, 0x6a, 0x4a, 0x07, 0x64, 0x45, 0xf8, 0x7f, 0xd6, ++ 0xb9, 0x05, 0x54, 0x2f, 0xe1, 0xdc, 0xf5, 0xd4, 0x9f, 0xe4, 0x7f, 0xab, ++ 0xe0, 0x77, 0x33, 0xf2, 0x7f, 0x14, 0xdf, 0xc3, 0x77, 0x8c, 0xc1, 0x77, ++ 0x81, 0xa2, 0xc0, 0x9d, 0x88, 0xa7, 0xaa, 0xa7, 0xff, 0xf9, 0xcc, 0x7f, ++ 0xc2, 0xab, 0x2b, 0xb5, 0x70, 0xfe, 0x4f, 0x52, 0xf0, 0xe9, 0x24, 0xfe, ++ 0x89, 0xac, 0x03, 0x9b, 0xfb, 0xf1, 0x5c, 0x5a, 0x07, 0xfa, 0xea, 0x28, ++ 0x3e, 0x52, 0x8f, 0x2e, 0xb1, 0xe8, 0x80, 0x2f, 0xf3, 0x43, 0x6f, 0xd3, ++ 0x3a, 0xb0, 0xc2, 0x73, 0x66, 0x54, 0xf9, 0x7a, 0xe4, 0xeb, 0x42, 0xc4, ++ 0x4c, 0xaf, 0xb6, 0xd0, 0x19, 0x79, 0x1f, 0xfc, 0x9a, 0xfc, 0xbf, 0x5e, ++ 0xd4, 0x9f, 0x63, 0x65, 0xcb, 0xfd, 0xd8, 0x9e, 0xd6, 0x93, 0x13, 0xdd, ++ 0xde, 0xe1, 0xa2, 0xaa, 0x07, 0x3d, 0x50, 0xde, 0xe1, 0x51, 0x78, 0x7b, ++ 0xff, 0x43, 0xe3, 0x06, 0x3c, 0xd9, 0x10, 0xbf, 0x30, 0x7e, 0x1f, 0xd2, ++ 0x6b, 0x7e, 0x99, 0x6e, 0xba, 0x27, 0x17, 0xfb, 0x91, 0xe3, 0xe7, 0x7c, ++ 0xf2, 0x55, 0xe3, 0x6f, 0x13, 0xf5, 0x5f, 0x55, 0xd9, 0x46, 0x6c, 0xf7, ++ 0xd5, 0x19, 0x33, 0x7a, 0x7c, 0xd0, 0xde, 0x91, 0x3b, 0x8b, 0x8b, 0x55, ++ 0x3d, 0xd2, 0xef, 0xd3, 0x1e, 0x0b, 0xb5, 0x37, 0x0f, 0x68, 0x87, 0xeb, ++ 0xa8, 0xef, 0x39, 0x6b, 0x68, 0x77, 0x2e, 0x8a, 0x11, 0xc6, 0x14, 0xa8, ++ 0xff, 0xc9, 0x73, 0x63, 0x43, 0xf7, 0xc0, 0x14, 0xdf, 0x62, 0x7d, 0xe7, ++ 0x71, 0x3c, 0xc1, 0x83, 0xf1, 0x3a, 0xce, 0xaf, 0xfe, 0x50, 0x3c, 0xd5, ++ 0xaf, 0x8f, 0x4b, 0x08, 0x29, 0x50, 0x5e, 0xef, 0xea, 0xcb, 0xf7, 0xc3, ++ 0x78, 0x66, 0x1e, 0xb6, 0x87, 0x91, 0xaf, 0x8e, 0x1c, 0xb6, 0x6b, 0x0c, ++ 0xfa, 0xad, 0x28, 0xb9, 0xf1, 0x69, 0xc4, 0xd3, 0xcc, 0xc3, 0x63, 0xaa, ++ 0x15, 0xe0, 0x43, 0xdf, 0x41, 0xab, 0xc6, 0xa0, 0xde, 0xdf, 0x27, 0xf8, ++ 0xf6, 0x22, 0x1f, 0x0c, 0x35, 0x7e, 0x39, 0xbe, 0xd8, 0xa7, 0x9c, 0xbf, ++ 0xe4, 0x2b, 0xb9, 0x5e, 0xe4, 0xfa, 0x90, 0xeb, 0x21, 0x76, 0xfd, 0xc8, ++ 0xf5, 0x70, 0xd5, 0x56, 0x4f, 0xc2, 0x77, 0x90, 0x4e, 0x80, 0x98, 0xc7, ++ 0x71, 0xfd, 0x68, 0xc1, 0xbd, 0x38, 0x8f, 0x3a, 0x3d, 0xbe, 0x08, 0xd7, ++ 0xa5, 0x5c, 0x47, 0xeb, 0x0f, 0x28, 0xb4, 0xce, 0x40, 0xe8, 0x7a, 0x46, ++ 0xeb, 0x91, 0x75, 0x24, 0xd7, 0x4d, 0x64, 0x9d, 0x98, 0x08, 0x0f, 0xf3, ++ 0x84, 0x9e, 0x18, 0x6a, 0x9d, 0xd4, 0x89, 0x75, 0x71, 0x93, 0x58, 0x17, ++ 0x72, 0x3d, 0x1c, 0x53, 0x3b, 0x1f, 0x2c, 0x87, 0xef, 0x66, 0x16, 0x05, ++ 0xfe, 0x82, 0x78, 0x92, 0xeb, 0x62, 0xdd, 0xfe, 0x58, 0xbd, 0x30, 0x24, ++ 0x5f, 0x31, 0xe4, 0xab, 0x9b, 0x52, 0x1a, 0x18, 0xf2, 0x55, 0x1d, 0x3c, ++ 0xa3, 0xf9, 0xca, 0x3a, 0xc4, 0x7a, 0x78, 0x07, 0xf9, 0x23, 0xf5, 0xd2, ++ 0xd7, 0x43, 0xcf, 0x25, 0xf2, 0xd3, 0xdf, 0x91, 0x9f, 0x26, 0xfd, 0xaf, ++ 0xf2, 0xd3, 0xdf, 0x91, 0x6f, 0x06, 0xe1, 0xa7, 0xcf, 0xff, 0x15, 0x7e, ++ 0x8a, 0xe5, 0x97, 0xb3, 0x0d, 0x7f, 0x2a, 0xd1, 0x61, 0x3c, 0x67, 0x4b, ++ 0x40, 0xce, 0xe6, 0x46, 0xf8, 0xed, 0xaa, 0x97, 0xd8, 0xf8, 0x03, 0xf0, ++ 0x9e, 0x8d, 0x72, 0x7a, 0x90, 0x7f, 0xba, 0xe3, 0xf8, 0x3c, 0xbb, 0x2d, ++ 0xd9, 0xa1, 0x16, 0xac, 0x77, 0x81, 0x35, 0x20, 0x1e, 0xa5, 0xfe, 0xbf, ++ 0x09, 0xe9, 0x9e, 0x1c, 0xe1, 0x53, 0xaf, 0x37, 0x30, 0xbc, 0x68, 0x52, ++ 0x84, 0xfe, 0xdd, 0x71, 0xc1, 0xc2, 0x0d, 0x85, 0x97, 0x4e, 0x67, 0x6b, ++ 0x4a, 0x8f, 0xc5, 0x57, 0x88, 0xf4, 0xee, 0x31, 0xe8, 0xff, 0xba, 0x21, ++ 0xe8, 0x3c, 0xa2, 0xe8, 0xeb, 0xd1, 0xd9, 0x29, 0xea, 0x7f, 0x15, 0x9d, ++ 0x3d, 0x45, 0x5c, 0x6e, 0x30, 0x37, 0xd0, 0xb1, 0x84, 0xe8, 0xa7, 0x23, ++ 0x5d, 0x63, 0xe9, 0x8e, 0x74, 0x45, 0xba, 0xd7, 0x1f, 0xb2, 0xee, 0xbe, ++ 0x18, 0x5d, 0xd7, 0x97, 0x04, 0xa6, 0x16, 0x0d, 0x22, 0x27, 0x98, 0x8f, ++ 0xdb, 0x03, 0x11, 0xba, 0x58, 0x17, 0x21, 0xdf, 0x9c, 0x0d, 0x83, 0x42, ++ 0x53, 0x86, 0xa6, 0xab, 0xb9, 0x83, 0xe3, 0x5d, 0xc2, 0x6d, 0x61, 0x4d, ++ 0xea, 0xdb, 0x64, 0xd4, 0xb7, 0xc0, 0x2f, 0x15, 0xd8, 0xdf, 0x37, 0xe5, ++ 0x97, 0x79, 0x33, 0xe1, 0xd7, 0xe1, 0x08, 0x3e, 0xb5, 0xd8, 0x97, 0x05, ++ 0x74, 0xff, 0xbe, 0x80, 0xd9, 0x2f, 0x16, 0x23, 0x7d, 0xae, 0x2d, 0x93, ++ 0xe5, 0x4f, 0x77, 0xf8, 0xf2, 0x50, 0xee, 0xc0, 0xef, 0xe5, 0xd4, 0x83, ++ 0x8f, 0xd9, 0x08, 0xbf, 0x1c, 0x0e, 0xee, 0x3d, 0x51, 0x0d, 0xf5, 0xaf, ++ 0x7a, 0xb0, 0xbf, 0x3c, 0x88, 0xe5, 0xb3, 0x2a, 0x12, 0x44, 0x7b, 0xcc, ++ 0xa7, 0xb0, 0x48, 0xfd, 0xeb, 0xf7, 0x3d, 0x79, 0xe2, 0x5e, 0x9a, 0xc7, ++ 0x36, 0xae, 0x0f, 0x02, 0xbd, 0x9a, 0x7f, 0x7c, 0x14, 0x5c, 0x02, 0xb0, ++ 0x33, 0x0a, 0x2e, 0x8b, 0x81, 0x77, 0xf0, 0xfa, 0x2e, 0xad, 0x97, 0xb9, ++ 0xa9, 0x9d, 0x10, 0x5f, 0xaf, 0xd0, 0xbe, 0xe2, 0xe5, 0xfc, 0xe3, 0x8f, ++ 0xb2, 0x47, 0x80, 0x92, 0xb3, 0x13, 0xd1, 0x9e, 0x3c, 0xa0, 0xb8, 0xef, ++ 0x01, 0xfa, 0x2f, 0xad, 0xf8, 0xc4, 0x82, 0xf4, 0x8a, 0xcc, 0xff, 0x00, ++ 0xcd, 0x7f, 0xfd, 0x41, 0x45, 0xc0, 0x5d, 0x27, 0x70, 0xbe, 0x4b, 0x0f, ++ 0x70, 0xb8, 0x79, 0xdf, 0xc1, 0x8e, 0xa0, 0x26, 0xda, 0x03, 0x3c, 0xaf, ++ 0x13, 0x68, 0x36, 0x77, 0x2a, 0x3e, 0x15, 0xda, 0x5d, 0x57, 0xa6, 0x84, ++ 0x46, 0xe6, 0x0e, 0xc4, 0x73, 0x73, 0x91, 0x51, 0xdf, 0xe1, 0x8f, 0x66, ++ 0xfc, 0x9e, 0x59, 0x52, 0xbe, 0xde, 0xf7, 0xb8, 0xbe, 0xe9, 0xfb, 0x91, ++ 0xf4, 0x7d, 0xd8, 0xfa, 0x35, 0xfa, 0xbf, 0xae, 0x82, 0xf9, 0x42, 0x8e, ++ 0x81, 0xf5, 0x1e, 0x90, 0xeb, 0xeb, 0x3c, 0xc0, 0xb2, 0x7d, 0xc0, 0xe5, ++ 0x22, 0x98, 0x5f, 0xa8, 0x70, 0x60, 0xfd, 0xed, 0xa2, 0xdd, 0x1e, 0x93, ++ 0x49, 0xe0, 0xeb, 0xb5, 0x0e, 0xc4, 0x5f, 0x8f, 0x45, 0xe2, 0xb3, 0xa7, ++ 0xc3, 0x57, 0x01, 0xf4, 0x67, 0x1c, 0x7e, 0x74, 0x5f, 0xcf, 0xe2, 0x60, ++ 0x21, 0x1f, 0xbe, 0x2f, 0x66, 0xfe, 0x17, 0x1b, 0x7f, 0x5b, 0xff, 0xba, ++ 0x8f, 0xcc, 0x5f, 0x37, 0x7e, 0x1f, 0xbe, 0x18, 0xfe, 0xb6, 0x0e, 0xc0, ++ 0x9f, 0xe0, 0x9f, 0x5a, 0x23, 0x3f, 0x25, 0x68, 0xfe, 0xe3, 0x67, 0xa1, ++ 0x9d, 0x84, 0x14, 0xc5, 0x8d, 0x76, 0xf1, 0x7a, 0xbf, 0xfd, 0x5e, 0xb4, ++ 0xff, 0x23, 0xfc, 0xf1, 0x67, 0xe2, 0x8f, 0x1e, 0x3b, 0xeb, 0xe7, 0x67, ++ 0x23, 0xff, 0xbf, 0xb9, 0x18, 0xf9, 0x7f, 0x3d, 0x93, 0xf5, 0xdf, 0xea, ++ 0xc0, 0xf5, 0xe3, 0x37, 0xf5, 0xd7, 0xe7, 0xeb, 0x41, 0xf2, 0x17, 0x7c, ++ 0x5f, 0x00, 0xfc, 0x84, 0x26, 0x32, 0x7e, 0xff, 0xdc, 0xbe, 0xbf, 0x74, ++ 0x04, 0x1d, 0x44, 0x1f, 0x2a, 0x27, 0x38, 0xef, 0x22, 0xeb, 0xa1, 0x33, ++ 0x06, 0xae, 0x88, 0x59, 0x3f, 0x82, 0xff, 0x69, 0xfd, 0xa2, 0x9c, 0x07, ++ 0xfc, 0x8c, 0x1e, 0x44, 0xce, 0xbc, 0x29, 0xf0, 0xfb, 0xb1, 0xc2, 0x16, ++ 0xa3, 0x9c, 0xec, 0xa9, 0xe2, 0x76, 0x62, 0xcf, 0x48, 0xfe, 0x3c, 0x5f, ++ 0xc4, 0xed, 0xc2, 0xf7, 0x04, 0x1e, 0x4f, 0x8b, 0xfa, 0x3d, 0x71, 0x51, ++ 0x78, 0xc8, 0x8a, 0xd0, 0x19, 0x7e, 0xc2, 0xe8, 0x87, 0x44, 0xcd, 0x9b, ++ 0xf0, 0xb4, 0x24, 0x45, 0xce, 0xfb, 0xcb, 0xc5, 0x73, 0x61, 0xde, 0x3d, ++ 0x49, 0xbc, 0xfc, 0xf3, 0xa2, 0xff, 0xee, 0x08, 0x66, 0x45, 0xe0, 0xd8, ++ 0xf6, 0xce, 0x15, 0x7d, 0x49, 0x7c, 0x13, 0x69, 0xff, 0xfc, 0x09, 0xc4, ++ 0xeb, 0x12, 0x81, 0xb7, 0xf3, 0x45, 0x5f, 0x9c, 0x10, 0x7c, 0xa5, 0xe0, ++ 0xba, 0xac, 0x23, 0x06, 0x01, 0xbe, 0x38, 0xa0, 0x04, 0x55, 0xf4, 0x13, ++ 0x90, 0x2f, 0x06, 0x99, 0xf7, 0xf1, 0x81, 0x7c, 0x15, 0x8c, 0xf9, 0xde, ++ 0x67, 0xbe, 0xc8, 0xf7, 0xbf, 0x1f, 0xb8, 0x2e, 0x7d, 0x31, 0xdf, 0x33, ++ 0x73, 0xc9, 0xd7, 0xf9, 0x5e, 0xd0, 0x6d, 0x6e, 0x0c, 0x5d, 0xe7, 0xc4, ++ 0xd0, 0xb5, 0x3a, 0x06, 0xae, 0x91, 0x70, 0xc8, 0x20, 0xff, 0xa4, 0x5c, ++ 0x5c, 0xd9, 0xf5, 0x40, 0x5b, 0x1a, 0xcc, 0xe3, 0x96, 0x3d, 0x0a, 0xaa, ++ 0x99, 0x28, 0x7e, 0x76, 0x2c, 0xc1, 0xf5, 0x79, 0x8b, 0x5b, 0xf2, 0xaf, ++ 0xf3, 0x0d, 0xb4, 0xbb, 0x22, 0xfc, 0xec, 0x22, 0x78, 0x61, 0xa7, 0x94, ++ 0x87, 0x09, 0xdb, 0x51, 0x1e, 0x2e, 0x40, 0x79, 0x58, 0x1e, 0x81, 0x17, ++ 0xa1, 0xbc, 0x20, 0xd8, 0xbd, 0xc4, 0x37, 0x31, 0x5a, 0x5f, 0x24, 0x52, ++ 0xf9, 0x75, 0xed, 0xb2, 0x7e, 0x12, 0xc1, 0x4b, 0x5b, 0x65, 0x7b, 0xc9, ++ 0xdb, 0x7d, 0x5a, 0x84, 0x8e, 0x2c, 0x98, 0xb2, 0x04, 0xfb, 0x5b, 0x52, ++ 0x22, 0xf4, 0x45, 0x30, 0xf5, 0x0d, 0xac, 0xbf, 0xf6, 0x20, 0xff, 0x7e, ++ 0xe2, 0xfe, 0xb4, 0x37, 0x2e, 0xba, 0x1e, 0xb6, 0xc5, 0xe0, 0x65, 0x47, ++ 0x0c, 0x1c, 0x8c, 0xa9, 0xff, 0xd0, 0x57, 0xe8, 0x97, 0xd6, 0x98, 0xef, ++ 0xef, 0x8a, 0x29, 0xbf, 0x37, 0x06, 0xee, 0x88, 0x81, 0xdb, 0x8d, 0xdf, ++ 0xaf, 0x58, 0xa5, 0xd0, 0x3a, 0x5c, 0x01, 0xfc, 0x80, 0x84, 0xf8, 0xaa, ++ 0x75, 0x39, 0xc3, 0xdb, 0x6f, 0xa7, 0xf6, 0xeb, 0x53, 0xc5, 0x41, 0x76, ++ 0x9b, 0x61, 0x5d, 0x5d, 0xd5, 0xc2, 0xe1, 0x2b, 0xf6, 0x8f, 0x5a, 0xd2, ++ 0xee, 0x88, 0x82, 0xbd, 0xa3, 0x97, 0x04, 0x1d, 0x91, 0x75, 0x61, 0x66, ++ 0xfc, 0xc7, 0x9a, 0xc2, 0x68, 0x5d, 0x98, 0x87, 0x90, 0x97, 0x93, 0xbd, ++ 0xb1, 0xeb, 0x42, 0xcc, 0xa7, 0x20, 0x56, 0xdf, 0xf2, 0xf2, 0xbf, 0xe2, ++ 0xaf, 0x19, 0x68, 0x07, 0x33, 0x83, 0x5d, 0x70, 0x4c, 0x35, 0xc2, 0x47, ++ 0x54, 0x39, 0xee, 0xe2, 0x37, 0x6e, 0x2b, 0xc4, 0x97, 0x12, 0xf6, 0x2e, ++ 0xc1, 0xf8, 0xca, 0x55, 0x3f, 0x36, 0xce, 0x0b, 0xfc, 0x55, 0x01, 0x7b, ++ 0x96, 0x54, 0x57, 0x44, 0xd9, 0x25, 0xc1, 0x89, 0x4b, 0x70, 0xfd, 0xcb, ++ 0x79, 0xca, 0xfa, 0xb3, 0xbf, 0xb8, 0xa0, 0x62, 0x7f, 0xcb, 0xbd, 0x13, ++ 0x97, 0x3c, 0x06, 0xe5, 0x35, 0x55, 0xe1, 0xd1, 0x0d, 0x30, 0xce, 0x9a, ++ 0x24, 0xfe, 0x04, 0xbd, 0xa6, 0xa2, 0xde, 0xac, 0x17, 0xf1, 0x98, 0xd9, ++ 0xcf, 0xa9, 0x7e, 0xd4, 0x6b, 0x35, 0x71, 0xe1, 0xd1, 0x8d, 0x85, 0x51, ++ 0xf3, 0x64, 0x9d, 0xf9, 0x38, 0xcf, 0x23, 0x77, 0xaa, 0x44, 0x9f, 0x60, ++ 0x0b, 0xd0, 0x07, 0xf0, 0xb4, 0x92, 0x81, 0x43, 0x00, 0xae, 0xd9, 0x91, ++ 0x84, 0x84, 0x8d, 0x4f, 0x40, 0xfd, 0x63, 0x77, 0xaa, 0x1b, 0x51, 0x8f, ++ 0xbe, 0xb5, 0x31, 0x39, 0x0d, 0xfd, 0x9b, 0x83, 0x5e, 0xee, 0x2f, 0x1c, ++ 0x4b, 0x18, 0x91, 0x76, 0x13, 0xc0, 0x47, 0xe2, 0x97, 0x5b, 0x74, 0xa8, ++ 0x77, 0x64, 0xcb, 0x2c, 0x7a, 0x1e, 0x55, 0x7d, 0x9b, 0xfb, 0x60, 0xad, ++ 0x7d, 0x6f, 0xff, 0xf4, 0x25, 0x8e, 0xb1, 0x58, 0x9e, 0x40, 0xf8, 0xb9, ++ 0xc3, 0x5b, 0xbe, 0xa4, 0x19, 0xf8, 0xfa, 0x2e, 0xaf, 0x4e, 0xf8, 0x0c, ++ 0x24, 0xb9, 0xd3, 0xba, 0xd0, 0x7e, 0xbe, 0xc7, 0xcc, 0x1e, 0xd7, 0x69, ++ 0xfe, 0x3b, 0x89, 0x6f, 0xee, 0xb3, 0x16, 0xa1, 0xff, 0xbc, 0xa2, 0x79, ++ 0x5c, 0x1a, 0xda, 0x93, 0x2b, 0x7f, 0xb8, 0x60, 0x76, 0x06, 0xd4, 0x5b, ++ 0xd9, 0x66, 0xf6, 0x28, 0x54, 0x8f, 0x4d, 0xc0, 0x71, 0x07, 0xee, 0x99, ++ 0x65, 0xc1, 0xf2, 0x55, 0xad, 0xe2, 0x19, 0xbc, 0x9c, 0x9e, 0x87, 0xbf, ++ 0x7c, 0xb4, 0xc5, 0x05, 0xf5, 0xfb, 0x1e, 0x51, 0x3c, 0xbb, 0xa1, 0xfe, ++ 0xb4, 0xcf, 0x3a, 0x5f, 0x9a, 0x00, 0xf0, 0x9a, 0xf6, 0x51, 0x1e, 0x24, ++ 0xcd, 0xa1, 0x73, 0x26, 0xe6, 0x86, 0x7e, 0xde, 0xe9, 0x18, 0x13, 0x52, ++ 0x81, 0x1f, 0xdf, 0xb5, 0x37, 0xbc, 0x30, 0x9f, 0xd7, 0x67, 0x58, 0x7f, ++ 0xcd, 0x79, 0xfd, 0x95, 0xf9, 0x25, 0x58, 0x5f, 0x75, 0x6f, 0x82, 0xfa, ++ 0x27, 0xe1, 0x3d, 0xda, 0xc3, 0x27, 0xef, 0x56, 0x77, 0x2b, 0x38, 0x2e, ++ 0x97, 0x33, 0x4e, 0x81, 0x29, 0x9d, 0xfc, 0x42, 0x7f, 0x05, 0xed, 0x5a, ++ 0x28, 0x77, 0x6f, 0x82, 0xf7, 0x27, 0xdb, 0x6e, 0x4e, 0x43, 0x3b, 0xeb, ++ 0xa4, 0xa2, 0xbb, 0x14, 0x98, 0xff, 0xf6, 0xfd, 0x73, 0x97, 0xa4, 0x03, ++ 0xbf, 0xac, 0xe9, 0xb0, 0x0a, 0x7a, 0xce, 0xcd, 0x58, 0x01, 0xf3, 0x5f, ++ 0x61, 0xea, 0xe7, 0x17, 0xd2, 0x1f, 0xab, 0x13, 0x39, 0xbc, 0xdd, 0x3b, ++ 0x77, 0xc9, 0xe3, 0x30, 0xfe, 0x93, 0xdb, 0xc7, 0xb8, 0x10, 0xcf, 0x89, ++ 0xc5, 0xbe, 0x87, 0xbd, 0x80, 0xe7, 0xb7, 0x8a, 0x7d, 0x3f, 0xf1, 0xa6, ++ 0xe2, 0x38, 0xb9, 0x9e, 0x3a, 0xfc, 0xa5, 0xba, 0x1c, 0xed, 0xf1, 0xdf, ++ 0x9e, 0x5e, 0x99, 0x86, 0xfc, 0xf4, 0xb8, 0x58, 0x3f, 0x87, 0xce, 0xad, ++ 0x4c, 0x5b, 0x19, 0x65, 0xef, 0xac, 0xfe, 0x58, 0x23, 0xba, 0x1f, 0xb6, ++ 0xe8, 0xb7, 0xe1, 0x38, 0x0f, 0xc7, 0x65, 0x2b, 0xe8, 0x2f, 0x03, 0xdd, ++ 0x93, 0x17, 0xc0, 0xfa, 0x5d, 0x25, 0xfc, 0x0f, 0xe0, 0xdf, 0x8d, 0xcf, ++ 0x0c, 0x62, 0xf7, 0x04, 0xbd, 0x2a, 0xb5, 0x7b, 0x64, 0x6b, 0x6a, 0x85, ++ 0x6e, 0xe0, 0xe3, 0xeb, 0xdf, 0x40, 0xbe, 0x24, 0xbf, 0x01, 0xe0, 0x5f, ++ 0xee, 0xbf, 0x6e, 0x3b, 0xea, 0xb5, 0xf7, 0xac, 0x1b, 0xd9, 0xbb, 0xb8, ++ 0xf8, 0xee, 0x82, 0x82, 0x29, 0xf0, 0x3c, 0x66, 0xa7, 0xf8, 0x95, 0x79, ++ 0xaf, 0x3d, 0x64, 0xcf, 0xc5, 0xf8, 0xa7, 0x6f, 0x36, 0xca, 0x3d, 0x96, ++ 0xde, 0x99, 0xbf, 0xd0, 0x19, 0xb5, 0xee, 0x44, 0xfd, 0xbf, 0x04, 0x9d, ++ 0x54, 0xff, 0x2f, 0x50, 0x1f, 0xfd, 0xb7, 0xbf, 0x04, 0xff, 0xec, 0x64, ++ 0x8e, 0x81, 0x76, 0xfc, 0x1a, 0x97, 0x33, 0x88, 0xc6, 0xc4, 0xfb, 0x4e, ++ 0xa7, 0x86, 0x74, 0x78, 0x4b, 0x6b, 0x3a, 0x79, 0x07, 0x7c, 0xb7, 0xfa, ++ 0x11, 0x33, 0xc9, 0xfd, 0xd5, 0x8f, 0xa4, 0xde, 0xd5, 0x87, 0xf2, 0x06, ++ 0xf8, 0x05, 0xe3, 0x63, 0xb1, 0xf3, 0x52, 0x8b, 0xcd, 0x34, 0xaf, 0x21, ++ 0xd7, 0x61, 0xb0, 0xd6, 0xb8, 0x0e, 0x59, 0x2d, 0xc9, 0xeb, 0xa1, 0xd6, ++ 0x61, 0xcf, 0xfe, 0x35, 0x17, 0x5d, 0x87, 0x6b, 0x84, 0x9f, 0x32, 0xfb, ++ 0x11, 0xb3, 0x1f, 0xd7, 0xd1, 0x9a, 0x49, 0x4e, 0x8d, 0x81, 0xfe, 0xa8, ++ 0x7a, 0xe4, 0xf9, 0xc7, 0x91, 0xdf, 0xd7, 0x6c, 0xb0, 0x7b, 0xad, 0x30, ++ 0xf0, 0x35, 0x8f, 0x58, 0x89, 0x5e, 0xbd, 0x4e, 0x67, 0xd0, 0x0d, 0xe5, ++ 0x01, 0x97, 0x53, 0x4b, 0x84, 0xe7, 0x5b, 0x82, 0xbe, 0xac, 0x98, 0xaf, ++ 0x9b, 0x99, 0x2a, 0xd3, 0x6c, 0x5e, 0x7a, 0xb6, 0x62, 0x9c, 0xf4, 0x0c, ++ 0x8c, 0x27, 0x19, 0xe0, 0x0f, 0x36, 0x3e, 0xf8, 0xa3, 0xc9, 0x50, 0xed, ++ 0x43, 0x16, 0xba, 0x76, 0x32, 0xe0, 0xef, 0x0c, 0x12, 0x0c, 0xf0, 0x72, ++ 0xe6, 0x80, 0x4a, 0xf1, 0x43, 0xa6, 0xf9, 0xb4, 0x79, 0x20, 0x1f, 0x6b, ++ 0x19, 0x97, 0x0b, 0x75, 0x2f, 0x3e, 0x63, 0xa9, 0xc4, 0xd9, 0x35, 0xac, ++ 0x99, 0x8b, 0x7e, 0xdd, 0xcd, 0x21, 0xf3, 0x3b, 0xbd, 0xc2, 0x67, 0xbb, ++ 0x20, 0xa6, 0x89, 0xf2, 0xb4, 0x9e, 0xbf, 0x02, 0xbd, 0x6a, 0x2c, 0xaf, ++ 0x67, 0xf7, 0x7e, 0xaa, 0x4e, 0x20, 0x36, 0xb6, 0xe0, 0x7a, 0xac, 0xeb, ++ 0x8c, 0x29, 0x6f, 0xb8, 0xfc, 0x7d, 0x8c, 0xbf, 0xd4, 0x33, 0xed, 0x9d, ++ 0x5e, 0x19, 0xaf, 0x85, 0x71, 0x7c, 0xee, 0x75, 0xa6, 0x9c, 0x8c, 0x47, ++ 0x71, 0xc8, 0xbc, 0x80, 0x21, 0x76, 0xa6, 0xc1, 0x9c, 0xcf, 0x60, 0x8a, ++ 0x6b, 0x1c, 0xb0, 0xae, 0x60, 0xbe, 0x33, 0x77, 0x28, 0x34, 0xee, 0x35, ++ 0x1b, 0xd5, 0x90, 0x15, 0xea, 0xcf, 0x4c, 0xe6, 0x71, 0xdf, 0xf7, 0x9a, ++ 0x80, 0xfe, 0x63, 0x68, 0xde, 0x41, 0x37, 0xc0, 0x6b, 0x1e, 0xe2, 0x7a, ++ 0x66, 0x0d, 0x53, 0x42, 0x36, 0xf8, 0xf5, 0xf2, 0x1d, 0x1b, 0x34, 0x5c, ++ 0x0f, 0xeb, 0x85, 0x7c, 0x59, 0xa1, 0x30, 0x3f, 0xf2, 0xf7, 0xbb, 0x76, ++ 0x4f, 0x0e, 0xfa, 0xeb, 0xab, 0x1f, 0xb1, 0x13, 0x7e, 0xd7, 0xec, 0xbc, ++ 0xf9, 0x8f, 0xdb, 0xe1, 0xbb, 0xde, 0xe6, 0x79, 0x29, 0xd1, 0xfe, 0xb1, ++ 0x43, 0xf0, 0x05, 0xb4, 0xcf, 0x6c, 0x49, 0x91, 0x76, 0xde, 0x6f, 0xfe, ++ 0x5e, 0x0e, 0xf2, 0xff, 0xcc, 0x9f, 0x82, 0x9f, 0x0b, 0xf3, 0x5d, 0x93, ++ 0xc8, 0x7e, 0xb1, 0x24, 0x17, 0xe9, 0x95, 0x91, 0xa3, 0x3b, 0x22, 0xf5, ++ 0xd6, 0x6c, 0xba, 0x33, 0x9f, 0xd7, 0x03, 0x3f, 0x19, 0xe6, 0xbd, 0xe2, ++ 0x6e, 0x95, 0xe6, 0xc1, 0x9e, 0xb5, 0x92, 0xde, 0x83, 0xb5, 0x9e, 0x4e, ++ 0x72, 0x59, 0xe0, 0x73, 0x55, 0xeb, 0x8b, 0x16, 0x4b, 0x21, 0xca, 0xe9, ++ 0x7b, 0x7b, 0x54, 0xa8, 0xff, 0x0e, 0xc0, 0xaa, 0x83, 0xf0, 0x15, 0x14, ++ 0x78, 0xb4, 0x20, 0xbe, 0x96, 0xe3, 0xb7, 0x19, 0xfc, 0x9b, 0xf4, 0x52, ++ 0x61, 0x77, 0xeb, 0x24, 0x47, 0x02, 0x38, 0xbf, 0x1a, 0x93, 0xb2, 0x7c, ++ 0x21, 0xc9, 0xf5, 0x3e, 0x0b, 0xae, 0xeb, 0xf2, 0x62, 0x85, 0xc6, 0x33, ++ 0xb1, 0x98, 0xdb, 0xb3, 0x2b, 0x72, 0x3c, 0x37, 0x50, 0x1c, 0xf9, 0x7e, ++ 0xab, 0x07, 0xe5, 0x14, 0xfe, 0xa8, 0x72, 0x1c, 0xe0, 0x57, 0xd5, 0x99, ++ 0x7a, 0x56, 0x63, 0x3c, 0x97, 0xfd, 0xd2, 0x4a, 0xf1, 0x91, 0xfa, 0x56, ++ 0xbb, 0xcf, 0xee, 0x22, 0xbf, 0xc3, 0xb7, 0x1f, 0xc7, 0xa7, 0x31, 0xcd, ++ 0x02, 0xf8, 0x58, 0xa7, 0x73, 0x79, 0x51, 0x2e, 0xf8, 0xb0, 0x5e, 0x5f, ++ 0x70, 0x39, 0xf2, 0x0d, 0x94, 0x9f, 0xd0, 0x70, 0x7f, 0xc5, 0xc9, 0xe5, ++ 0x62, 0x5d, 0x22, 0xe0, 0x9d, 0xeb, 0x63, 0x9f, 0x09, 0xfa, 0xf9, 0x04, ++ 0x7f, 0x1b, 0xc5, 0xdb, 0xcd, 0x98, 0x10, 0xd5, 0xbf, 0x22, 0xde, 0x43, ++ 0x3b, 0xba, 0x2b, 0xd2, 0x6e, 0xb7, 0x89, 0xb5, 0x63, 0x9c, 0x05, 0xeb, ++ 0x8f, 0x9d, 0x80, 0x78, 0x4c, 0xbe, 0x76, 0x31, 0x8e, 0xef, 0xe7, 0x2a, ++ 0xad, 0x67, 0x98, 0xfc, 0xfd, 0x65, 0x68, 0xe7, 0xfd, 0x5c, 0x2d, 0x46, ++ 0xff, 0x76, 0xc5, 0xdd, 0xc7, 0x66, 0x77, 0x20, 0xbc, 0xaf, 0xc8, 0x8d, ++ 0x4d, 0xae, 0xf8, 0xc5, 0x1f, 0x48, 0x6f, 0xdc, 0x22, 0xe8, 0xdf, 0x8b, ++ 0xf6, 0x3e, 0xea, 0x11, 0x80, 0xf7, 0xc1, 0x73, 0x51, 0x31, 0xd7, 0xfb, ++ 0x01, 0x95, 0xc7, 0x7d, 0x16, 0x09, 0x7c, 0x49, 0x3e, 0x90, 0xe5, 0x75, ++ 0x77, 0x9b, 0x79, 0xfc, 0xbd, 0xcd, 0x4a, 0x76, 0x4c, 0x5d, 0xf3, 0x9f, ++ 0xa8, 0xdd, 0x3a, 0x67, 0x4f, 0x1a, 0xca, 0xdf, 0xba, 0x67, 0xcd, 0xa5, ++ 0x28, 0xa7, 0xaf, 0x15, 0xe3, 0x5e, 0xd9, 0x9c, 0x5d, 0x71, 0x02, 0xf8, ++ 0x6a, 0xa5, 0x39, 0xc1, 0xad, 0xc0, 0xab, 0x75, 0xc1, 0x79, 0x16, 0x84, ++ 0xd7, 0x6d, 0x53, 0x08, 0x8e, 0x7c, 0x97, 0x9a, 0x83, 0x7c, 0xfa, 0x51, ++ 0xeb, 0xaf, 0x5c, 0xc8, 0x3f, 0xef, 0xda, 0xc3, 0xa3, 0x51, 0x1f, 0xf5, ++ 0x6d, 0xb0, 0x7b, 0x76, 0xe3, 0x04, 0x44, 0xdc, 0xed, 0xa3, 0xd6, 0xd1, ++ 0xbb, 0x31, 0x3e, 0xb3, 0xca, 0xdd, 0xe3, 0x54, 0xa0, 0x7c, 0xd5, 0x6d, ++ 0xa3, 0x92, 0x50, 0x7e, 0xbf, 0xe5, 0x0e, 0x5b, 0xb0, 0xfc, 0xad, 0xce, ++ 0x5c, 0x13, 0xc2, 0x3e, 0xb7, 0xbb, 0x02, 0x61, 0x9f, 0x36, 0x91, 0xe0, ++ 0x8f, 0x40, 0x94, 0x75, 0x0a, 0xff, 0x13, 0xf9, 0x6d, 0xbd, 0xc2, 0xe9, ++ 0xbc, 0x6e, 0xef, 0x31, 0xcb, 0x48, 0xe8, 0xef, 0x4e, 0x31, 0xdf, 0x8f, ++ 0x7f, 0xfe, 0x87, 0x7c, 0xd4, 0x57, 0x75, 0x39, 0x3d, 0xf9, 0xa8, 0x57, ++ 0x80, 0x0f, 0xf2, 0x33, 0x11, 0xcf, 0x4f, 0x29, 0xa4, 0x8f, 0xd7, 0xef, ++ 0x55, 0x7d, 0xf6, 0x09, 0x11, 0x3e, 0x58, 0x8f, 0x7c, 0x00, 0xeb, 0x6e, ++ 0xad, 0xe0, 0x83, 0xf5, 0x07, 0x7e, 0xf5, 0x1d, 0x5c, 0x0f, 0xeb, 0x91, ++ 0xfe, 0xde, 0x81, 0x7c, 0x04, 0x7c, 0x7a, 0x9c, 0xde, 0xef, 0xdf, 0x35, ++ 0x9b, 0xf1, 0xef, 0x8f, 0x23, 0x9f, 0x48, 0x3d, 0x06, 0x70, 0xab, 0x19, ++ 0xe3, 0x69, 0x16, 0x01, 0x43, 0x3f, 0x08, 0xdf, 0x85, 0xf8, 0x9c, 0x44, ++ 0xe5, 0xd5, 0xbc, 0x3c, 0x58, 0x48, 0xf2, 0x94, 0xf5, 0x5a, 0xd0, 0xee, ++ 0xac, 0xef, 0x32, 0x07, 0x7b, 0xa3, 0xf6, 0x7f, 0x86, 0xa2, 0xf3, 0x76, ++ 0x41, 0xc7, 0x95, 0xcd, 0x56, 0x92, 0xbb, 0xdb, 0xc5, 0xbc, 0x7b, 0xef, ++ 0x7e, 0xd6, 0x85, 0x74, 0xfc, 0xf8, 0xe7, 0xc7, 0x5e, 0xc0, 0xfd, 0x92, ++ 0xba, 0xfd, 0xa0, 0xad, 0xf5, 0x41, 0xd6, 0x85, 0xc0, 0x4b, 0x3d, 0xe2, ++ 0xc1, 0x45, 0xf3, 0x20, 0xfb, 0xa2, 0x1e, 0xe7, 0xed, 0x8a, 0xe0, 0xa1, ++ 0x9f, 0xff, 0xc5, 0x7a, 0xac, 0x67, 0x7c, 0x9e, 0x72, 0xde, 0xf5, 0x9a, ++ 0xc0, 0x83, 0x2c, 0x17, 0xdf, 0x3f, 0x2c, 0xf8, 0x66, 0x1d, 0x13, 0x78, ++ 0x3b, 0x30, 0x86, 0xaf, 0x3f, 0xb1, 0xde, 0x70, 0x3d, 0xa3, 0x5c, 0x95, ++ 0xf3, 0x0b, 0x24, 0xf1, 0xef, 0x25, 0x9f, 0x1e, 0x2e, 0xe6, 0x7a, 0x61, ++ 0x8f, 0x78, 0xae, 0x03, 0xbe, 0xf0, 0x14, 0x12, 0xff, 0xf8, 0x2c, 0x52, ++ 0x4e, 0x40, 0xd1, 0xc7, 0xfb, 0x76, 0x51, 0xfc, 0x47, 0xd2, 0x4b, 0x8e, ++ 0xfb, 0xb5, 0x88, 0x3e, 0xf1, 0x25, 0x26, 0x45, 0xe8, 0xd8, 0x6b, 0x62, ++ 0xb5, 0x9d, 0x83, 0xc4, 0x4d, 0xba, 0x04, 0xfe, 0xde, 0x6e, 0x1b, 0x96, ++ 0xd3, 0x05, 0x78, 0xfb, 0x08, 0xfc, 0x2c, 0xb4, 0xa7, 0x90, 0x5f, 0xb5, ++ 0xa8, 0xfe, 0x24, 0xdf, 0xc8, 0xfe, 0x66, 0x3e, 0xbd, 0xe0, 0x4a, 0x9c, ++ 0x2f, 0xb4, 0x1f, 0xc6, 0xf6, 0x65, 0xbf, 0x6f, 0x05, 0xe3, 0x35, 0x6c, ++ 0xe7, 0x2d, 0xc6, 0xd7, 0x07, 0xf2, 0x27, 0xca, 0x4f, 0xb9, 0x2e, 0x67, ++ 0xb6, 0x2c, 0xbb, 0xb2, 0xc8, 0x85, 0xf5, 0x3e, 0x76, 0x8e, 0x42, 0x3b, ++ 0x46, 0xc8, 0xb3, 0xd7, 0x8a, 0xdd, 0xf4, 0xbd, 0x0f, 0xed, 0x05, 0xf8, ++ 0xde, 0xd7, 0xa5, 0x50, 0xfc, 0xf9, 0x6d, 0xe1, 0xd7, 0xbf, 0xdd, 0xf6, ++ 0x2b, 0xd7, 0xca, 0x28, 0x3c, 0xbd, 0x2a, 0xc6, 0x2d, 0xf9, 0x0c, 0x7f, ++ 0x30, 0x2e, 0x25, 0xc7, 0xdb, 0x9d, 0xc4, 0xe3, 0xb9, 0xb1, 0xe3, 0x96, ++ 0x72, 0x48, 0x8e, 0x7b, 0xe6, 0x96, 0xeb, 0xae, 0xc4, 0xf7, 0x72, 0xfc, ++ 0x92, 0x5f, 0x25, 0x7f, 0x4a, 0x3c, 0x4a, 0x3e, 0x65, 0x77, 0xa5, 0x92, ++ 0x5d, 0x13, 0xcb, 0xaf, 0xc4, 0x6b, 0x52, 0xaf, 0xaa, 0x06, 0x79, 0x4f, ++ 0xfa, 0xf1, 0xf2, 0xac, 0x4f, 0x2d, 0x01, 0xc7, 0xc0, 0xf7, 0xb1, 0xb0, ++ 0xb4, 0x87, 0xde, 0xc5, 0x38, 0x0d, 0xca, 0x8f, 0x27, 0xd5, 0x10, 0xc9, ++ 0x8f, 0xd6, 0xf4, 0xe3, 0x79, 0x51, 0x7a, 0x1e, 0x7e, 0x1c, 0xd1, 0x7a, ++ 0xa7, 0x79, 0xc3, 0xe5, 0xee, 0x4a, 0xdc, 0x7f, 0xdd, 0xab, 0x78, 0xd0, ++ 0xe4, 0x89, 0xd2, 0x2f, 0xf7, 0x6a, 0x51, 0xfa, 0x45, 0xda, 0x05, 0x25, ++ 0x25, 0x23, 0x09, 0xef, 0xf5, 0x29, 0xbe, 0x0f, 0x90, 0x8e, 0xeb, 0x4e, ++ 0xf5, 0xcc, 0x76, 0xe9, 0x11, 0x3b, 0x74, 0xda, 0x67, 0x61, 0x35, 0x01, ++ 0xe3, 0x52, 0x07, 0x72, 0xbd, 0xd1, 0xfa, 0x74, 0xdd, 0xe9, 0xe3, 0xc4, ++ 0xff, 0x75, 0xac, 0x67, 0x33, 0xfa, 0x51, 0x2b, 0xee, 0xfe, 0xc3, 0xbc, ++ 0xc9, 0xc8, 0xe7, 0x4f, 0x9a, 0x69, 0x7f, 0x66, 0x45, 0xdb, 0x2c, 0x0b, ++ 0xda, 0xf5, 0x37, 0x3f, 0x7e, 0x63, 0x29, 0xf2, 0xd1, 0x3b, 0xed, 0xa3, ++ 0x48, 0xae, 0x7f, 0xf0, 0xd8, 0xa4, 0x62, 0xe2, 0x2b, 0xe6, 0x4e, 0xbb, ++ 0x16, 0xf8, 0x7f, 0xd5, 0x63, 0x0f, 0x5e, 0xbb, 0x14, 0xde, 0xaf, 0xea, ++ 0x52, 0x3d, 0x24, 0xdf, 0xa1, 0x1d, 0x5c, 0xb7, 0x2b, 0x6e, 0x2f, 0x66, ++ 0xc8, 0x37, 0xef, 0xda, 0x7b, 0xe7, 0x95, 0xa3, 0xfd, 0x7e, 0x87, 0xea, ++ 0x46, 0xfb, 0x7d, 0xea, 0xe3, 0x93, 0xee, 0xc2, 0xfa, 0x53, 0x9d, 0x23, ++ 0x12, 0x71, 0x1e, 0xbe, 0xc7, 0x92, 0x09, 0xf6, 0x69, 0x09, 0xa4, 0x1f, ++ 0xa4, 0xdd, 0xfb, 0x96, 0x90, 0x93, 0x2d, 0x66, 0xce, 0x17, 0x39, 0x25, ++ 0x7c, 0x1d, 0xa5, 0x96, 0x70, 0xb9, 0x91, 0x5a, 0xc2, 0xf9, 0x66, 0x66, ++ 0x4b, 0x4b, 0x3e, 0xee, 0xa7, 0xf7, 0xed, 0x02, 0xf9, 0x8c, 0xfb, 0xca, ++ 0x16, 0xbd, 0x33, 0x8c, 0xfd, 0x3d, 0x37, 0x8c, 0xfc, 0x8b, 0x7a, 0x70, ++ 0x87, 0xd2, 0x81, 0xee, 0xa7, 0x14, 0x6e, 0x97, 0xd5, 0x5a, 0x98, 0x2d, ++ 0xc3, 0x4b, 0xef, 0x6d, 0x19, 0xf0, 0xfe, 0x45, 0x73, 0xcf, 0xed, 0xa8, ++ 0x47, 0x5e, 0xbc, 0xdd, 0x59, 0xd4, 0x8c, 0x03, 0x50, 0xcf, 0x97, 0xae, ++ 0xe4, 0xf6, 0x34, 0xdf, 0x3f, 0x4c, 0xe6, 0xfd, 0x4b, 0xbc, 0xc9, 0x71, ++ 0x64, 0x97, 0x70, 0x7e, 0x8f, 0x6d, 0x4f, 0x7e, 0xdf, 0x8d, 0x7e, 0x04, ++ 0xca, 0x53, 0x31, 0xfe, 0x0f, 0x5a, 0x9f, 0xbc, 0x16, 0xf5, 0xe0, 0x07, ++ 0x7b, 0x46, 0x27, 0xe1, 0xbc, 0xdf, 0x7f, 0xce, 0xde, 0x8e, 0xf6, 0xd4, ++ 0xfb, 0x66, 0x2e, 0x17, 0x65, 0xfb, 0x60, 0xe7, 0xbd, 0x17, 0x6d, 0xa7, ++ 0x81, 0x5d, 0x67, 0x80, 0xc1, 0x8e, 0x33, 0xc0, 0xc0, 0xbf, 0xef, 0x19, ++ 0xed, 0xc2, 0x4d, 0x34, 0xae, 0x89, 0x25, 0x60, 0xc7, 0x8d, 0x63, 0xfd, ++ 0x76, 0x9c, 0xe4, 0xf7, 0x9a, 0x0d, 0xa3, 0x13, 0xa2, 0xf3, 0x08, 0x62, ++ 0xed, 0x77, 0x96, 0x17, 0xbb, 0x6f, 0x33, 0x39, 0x81, 0x0d, 0x22, 0x6f, ++ 0xe4, 0xf3, 0x74, 0x13, 0x20, 0x0a, 0x18, 0xf5, 0x2c, 0xee, 0x11, 0x42, ++ 0xbf, 0xd5, 0xf1, 0x5f, 0x3c, 0xd3, 0x83, 0xf6, 0xfe, 0x36, 0xab, 0xdb, ++ 0x0a, 0xf3, 0x7c, 0x0f, 0xf9, 0x1f, 0xf7, 0xa5, 0x9e, 0x55, 0x43, 0xb8, ++ 0x0f, 0x83, 0xb6, 0x39, 0xae, 0x87, 0xf7, 0xf6, 0x15, 0x85, 0xd0, 0x8f, ++ 0x5c, 0xfd, 0x66, 0x60, 0x36, 0xb6, 0x7f, 0xfc, 0x81, 0x2d, 0x94, 0x67, ++ 0x70, 0x13, 0xd8, 0x97, 0xc3, 0x94, 0x28, 0xbb, 0xf9, 0xa1, 0x07, 0xae, ++ 0x45, 0xf6, 0x3f, 0xe3, 0x09, 0x6c, 0xce, 0x80, 0xef, 0xce, 0xec, 0xe1, ++ 0x79, 0x11, 0x50, 0xec, 0x88, 0xb1, 0x97, 0x5f, 0xc8, 0xd0, 0xff, 0x75, ++ 0x7b, 0xf9, 0x52, 0xed, 0x64, 0x19, 0x6f, 0xa8, 0x29, 0x11, 0xf6, 0xb2, ++ 0x87, 0x79, 0x10, 0xcf, 0x12, 0xbf, 0xd2, 0x6f, 0x3a, 0x0c, 0x7c, 0x50, ++ 0xe6, 0x8d, 0xe0, 0xeb, 0x6f, 0x4d, 0xb5, 0x64, 0x27, 0x9f, 0x6e, 0x0a, ++ 0xd0, 0xf3, 0x13, 0xe5, 0xed, 0xfb, 0xa7, 0x22, 0xff, 0x3a, 0x13, 0x3c, ++ 0xbb, 0xe1, 0xb3, 0xdf, 0x76, 0x3d, 0xa8, 0x66, 0x22, 0x9d, 0x0f, 0x14, ++ 0x9d, 0x47, 0xbf, 0xb7, 0xdc, 0x91, 0xe0, 0xc6, 0x75, 0xfb, 0xb7, 0xa6, ++ 0x8d, 0xb4, 0xf9, 0x78, 0xba, 0xa9, 0x81, 0x9e, 0x92, 0xce, 0x32, 0xde, ++ 0x36, 0xed, 0xc0, 0x11, 0xfa, 0xee, 0x6f, 0x5d, 0xc5, 0x07, 0xa7, 0xc2, ++ 0x77, 0x87, 0x1c, 0x09, 0x5c, 0xfe, 0x0f, 0xd8, 0xef, 0xe1, 0xf4, 0x8c, ++ 0xcd, 0x03, 0xb9, 0x75, 0xc3, 0xe4, 0x61, 0xf8, 0x5e, 0xce, 0xeb, 0xc3, ++ 0x3b, 0x38, 0x5d, 0xe5, 0xb8, 0x3f, 0xdc, 0x73, 0xa3, 0x0b, 0xe7, 0x75, ++ 0xe4, 0x27, 0xc9, 0x07, 0xa7, 0x20, 0x3d, 0xe3, 0x13, 0xdc, 0x68, 0xef, ++ 0xad, 0x11, 0xf9, 0x1f, 0x27, 0x3b, 0xb8, 0x3d, 0x7d, 0xca, 0x96, 0xf0, ++ 0xc4, 0x5c, 0xcc, 0x1b, 0xd9, 0xb1, 0x28, 0x8d, 0x81, 0x9c, 0xbd, 0xe9, ++ 0xc8, 0xb7, 0xae, 0xc5, 0xf7, 0xab, 0x9f, 0x53, 0xdc, 0xe8, 0x07, 0x78, ++ 0x9e, 0x5b, 0xe0, 0x42, 0xff, 0xf4, 0xbf, 0xb4, 0x5e, 0x97, 0x1b, 0x9f, ++ 0xf0, 0x5d, 0x18, 0xc7, 0xa3, 0x85, 0x54, 0x94, 0x47, 0xe5, 0x73, 0x18, ++ 0xed, 0x47, 0x95, 0x87, 0x35, 0xa6, 0xe7, 0xd2, 0x56, 0x2f, 0xf1, 0xcb, ++ 0x94, 0xd3, 0x5a, 0x08, 0xf3, 0x46, 0x3e, 0xc2, 0x7d, 0x2a, 0x8c, 0x87, ++ 0x9c, 0x8f, 0xa3, 0x78, 0x08, 0x13, 0xfb, 0x4f, 0x37, 0xfd, 0x9a, 0xc7, ++ 0x51, 0xfa, 0xfd, 0x5b, 0xe1, 0xdf, 0x4d, 0x15, 0xf3, 0xee, 0x2a, 0x49, ++ 0x92, 0xfb, 0x0a, 0xf4, 0x7e, 0x66, 0x19, 0x7f, 0xff, 0xfe, 0x8e, 0x67, ++ 0xe6, 0x63, 0x7b, 0x1f, 0x3c, 0x66, 0x76, 0xe3, 0xb8, 0xff, 0xf6, 0x98, ++ 0x99, 0xda, 0x5f, 0x0b, 0x7e, 0x99, 0x09, 0xc6, 0x7b, 0x6a, 0x0f, 0xf7, ++ 0x77, 0xd6, 0x76, 0x2a, 0xe4, 0x27, 0x7f, 0xb0, 0x07, 0xf4, 0x35, 0xcc, ++ 0xab, 0x6e, 0x83, 0xd9, 0x67, 0x49, 0x18, 0xc8, 0x87, 0x33, 0xa1, 0xbc, ++ 0xd7, 0x11, 0xe1, 0xc3, 0xb5, 0xbe, 0x10, 0xf1, 0x37, 0x13, 0xfc, 0x68, ++ 0x83, 0xff, 0x2e, 0x8c, 0x1c, 0xc8, 0x8f, 0x89, 0xac, 0x73, 0x33, 0xe2, ++ 0xe3, 0x5f, 0xe5, 0xcb, 0x5f, 0xc4, 0xac, 0xfb, 0x7e, 0x7e, 0x1c, 0x8a, ++ 0x0f, 0x04, 0xbe, 0x70, 0x1d, 0x23, 0x3f, 0x4a, 0x7a, 0xaf, 0xed, 0xe0, ++ 0xfb, 0xea, 0x49, 0x9d, 0x45, 0x95, 0xc8, 0x57, 0x92, 0xfe, 0x52, 0x4e, ++ 0x04, 0xab, 0x58, 0x01, 0xea, 0xd5, 0x16, 0x0b, 0x2b, 0xc0, 0x3c, 0x9c, ++ 0xa0, 0x29, 0xce, 0x83, 0xeb, 0x7b, 0x81, 0x43, 0x37, 0x2b, 0x80, 0x87, ++ 0x45, 0x29, 0xbd, 0xd5, 0x28, 0x4e, 0x33, 0x27, 0x71, 0x39, 0xad, 0xce, ++ 0x34, 0xf9, 0x4c, 0xa8, 0x5f, 0x5a, 0xac, 0x24, 0x07, 0x62, 0xe5, 0xc8, ++ 0xef, 0x84, 0x5c, 0x9f, 0x8f, 0x3c, 0x0d, 0xff, 0xde, 0x2d, 0xe1, 0x76, ++ 0x84, 0x99, 0x35, 0x90, 0x1f, 0x22, 0x9f, 0xa0, 0x77, 0xb2, 0x51, 0x7f, ++ 0x2f, 0x88, 0x4f, 0xfa, 0xbb, 0x0e, 0x55, 0xfe, 0xfd, 0x40, 0xed, 0x52, ++ 0x0d, 0xc6, 0xbf, 0x60, 0x6a, 0xd2, 0xed, 0xa3, 0x3c, 0x8c, 0xbd, 0x79, ++ 0x60, 0xfd, 0x52, 0x0d, 0xf8, 0x77, 0x41, 0x71, 0xd2, 0xb3, 0x23, 0x01, ++ 0x7e, 0xab, 0xa4, 0x8e, 0xc3, 0x13, 0x93, 0x26, 0x99, 0x01, 0x6e, 0x6e, ++ 0xae, 0x5f, 0x5a, 0x0d, 0xf5, 0xff, 0x59, 0xe2, 0x7b, 0xbd, 0x24, 0xaa, ++ 0x1f, 0xd9, 0x2e, 0xbc, 0xff, 0x8f, 0x12, 0x80, 0x37, 0x8d, 0x0b, 0x9c, ++ 0xc0, 0x67, 0xbd, 0xc5, 0x41, 0x72, 0xfa, 0x13, 0xa5, 0x6f, 0xc2, 0xc6, ++ 0xdc, 0x48, 0xfd, 0xd7, 0x14, 0xf6, 0xd6, 0x6f, 0x95, 0x08, 0xdc, 0x6b, ++ 0x66, 0x39, 0x68, 0xdf, 0xbd, 0x5b, 0x22, 0xc7, 0x3f, 0xf8, 0x33, 0x6f, ++ 0x92, 0xef, 0xed, 0x92, 0x41, 0xde, 0xaf, 0x64, 0xac, 0x0d, 0xe3, 0x2a, ++ 0x2b, 0x83, 0xbf, 0x3b, 0xa1, 0x70, 0x3f, 0xcc, 0x6f, 0x03, 0x7a, 0x5d, ++ 0x2d, 0xf8, 0x6a, 0xa5, 0xcd, 0x11, 0x26, 0x7f, 0xbe, 0xdd, 0x7c, 0xba, ++ 0x9f, 0xde, 0xc8, 0x47, 0x9e, 0x04, 0x0d, 0xe9, 0x3a, 0x5f, 0xf0, 0xd1, ++ 0xd5, 0x5a, 0xf8, 0x08, 0x7e, 0x3f, 0x96, 0xb5, 0xba, 0x4f, 0xda, 0xc8, ++ 0x84, 0xda, 0x71, 0x21, 0x79, 0x68, 0xf9, 0x0d, 0x0b, 0x8f, 0x9d, 0x94, ++ 0xed, 0x01, 0xbf, 0x7c, 0x62, 0x86, 0xf9, 0x02, 0x5f, 0x2b, 0xc0, 0x9e, ++ 0x1b, 0x61, 0xc9, 0x28, 0x80, 0xe4, 0x1a, 0x90, 0x5f, 0xca, 0xc1, 0xdf, ++ 0xfd, 0x03, 0xdb, 0x6d, 0x09, 0xb2, 0x5e, 0x3b, 0xd1, 0xa1, 0xc6, 0x8d, ++ 0x7c, 0xa6, 0xb0, 0x80, 0xe9, 0x02, 0x3c, 0xeb, 0xe2, 0x5d, 0x13, 0x30, ++ 0x6e, 0x52, 0x17, 0x9f, 0x13, 0x42, 0xbe, 0x6f, 0x7c, 0xf6, 0xe3, 0xe3, ++ 0xc8, 0x5e, 0x37, 0x4b, 0xfb, 0x25, 0x50, 0x46, 0xfc, 0x7e, 0x9b, 0x9b, ++ 0xcf, 0x87, 0x05, 0xca, 0x89, 0x1f, 0x6f, 0x17, 0xfc, 0xf8, 0x7e, 0x13, ++ 0x6b, 0xc8, 0x83, 0xa5, 0x77, 0x75, 0x4f, 0x8f, 0x4b, 0x87, 0x41, 0x9f, ++ 0x9e, 0x1f, 0xce, 0xc7, 0xf5, 0xfe, 0x69, 0x4e, 0x20, 0x6e, 0x12, 0xfa, ++ 0xf9, 0x3b, 0x5a, 0xb2, 0x1a, 0x81, 0x7f, 0x3e, 0xde, 0x6f, 0xf5, 0xcc, ++ 0x85, 0xfa, 0xa7, 0x42, 0xcf, 0x50, 0x1c, 0x6e, 0x9d, 0xb0, 0x47, 0xd9, ++ 0x63, 0xa9, 0x62, 0xdd, 0xab, 0xe1, 0x19, 0x50, 0xaf, 0x3b, 0x77, 0xec, ++ 0x6e, 0xd4, 0x2f, 0x29, 0x93, 0x38, 0x5f, 0x9d, 0xce, 0x0d, 0xe7, 0xdc, ++ 0x89, 0x72, 0x23, 0x97, 0xfb, 0x3f, 0x50, 0x8f, 0xf2, 0xdc, 0xe6, 0x6c, ++ 0xba, 0x3c, 0x15, 0xeb, 0x9d, 0xde, 0xb7, 0x25, 0xef, 0x26, 0xa0, 0x9f, ++ 0x55, 0x63, 0x41, 0x67, 0x12, 0x3d, 0x99, 0x0b, 0xe6, 0x7d, 0x05, 0xb4, ++ 0x5d, 0x06, 0xb0, 0x19, 0x60, 0x95, 0xf6, 0x73, 0x43, 0x44, 0x2f, 0xac, ++ 0xe7, 0x42, 0x7d, 0xaf, 0xdf, 0x98, 0xce, 0xe3, 0xed, 0xcc, 0x8f, 0x72, ++ 0x45, 0xd2, 0x4b, 0xd2, 0x61, 0x00, 0x7d, 0x60, 0x08, 0x68, 0xaf, 0x9a, ++ 0x6c, 0xcc, 0x8c, 0xe3, 0x1f, 0xcb, 0x76, 0xb8, 0x51, 0x7f, 0x48, 0x3a, ++ 0xbd, 0x6f, 0x03, 0x3c, 0x62, 0xfc, 0xcc, 0x06, 0x78, 0x84, 0xf5, 0x3d, ++ 0x0b, 0x83, 0x0e, 0x25, 0x88, 0x4f, 0x1e, 0x6f, 0x69, 0x54, 0x7a, 0x5b, ++ 0x93, 0x11, 0xfe, 0xb9, 0x42, 0x79, 0x73, 0x03, 0xf5, 0xe0, 0xe3, 0x16, ++ 0x44, 0x79, 0xed, 0x8e, 0x1b, 0x49, 0xfe, 0x48, 0xb9, 0xa3, 0xc3, 0x7f, ++ 0x83, 0xc9, 0x9d, 0xaf, 0x1d, 0x37, 0xda, 0x31, 0x73, 0x50, 0xb9, 0x33, ++ 0x6d, 0x92, 0xd0, 0x83, 0x45, 0xac, 0xe8, 0x02, 0x37, 0x10, 0x89, 0xbe, ++ 0x6b, 0xc4, 0xb7, 0xb3, 0xd4, 0x1a, 0x5d, 0xc3, 0x71, 0xa7, 0xda, 0x3c, ++ 0x18, 0x4f, 0x6b, 0x7c, 0x64, 0x14, 0xe9, 0x1b, 0xd6, 0xfa, 0x07, 0x16, ++ 0x5d, 0x8f, 0xed, 0x48, 0x26, 0x7e, 0xd9, 0x9c, 0xab, 0x12, 0xde, 0x6f, ++ 0xee, 0x52, 0x28, 0xbf, 0x71, 0x5e, 0x57, 0x26, 0xd3, 0xa1, 0x68, 0x6e, ++ 0x57, 0x32, 0x3d, 0x5d, 0xe7, 0x32, 0xe8, 0xfd, 0x07, 0x4f, 0xbc, 0x54, ++ 0xc2, 0xe5, 0x12, 0xa7, 0xcb, 0xbc, 0x9f, 0x0d, 0xab, 0xa2, 0xbc, 0xa2, ++ 0x9f, 0x8d, 0xa1, 0xa7, 0x1c, 0x47, 0xa3, 0xe0, 0xbb, 0x59, 0x6a, 0x61, ++ 0x67, 0x18, 0xed, 0x08, 0x07, 0x8c, 0x03, 0xe0, 0xc6, 0x17, 0xb9, 0xde, ++ 0x6a, 0xbc, 0x46, 0xa5, 0xb8, 0x26, 0x43, 0x11, 0x9d, 0x86, 0xc4, 0xe4, ++ 0x3f, 0x7e, 0x47, 0x3b, 0xc5, 0x7f, 0xfc, 0xac, 0xdf, 0xbe, 0x57, 0x2e, ++ 0x50, 0x9c, 0x56, 0x4f, 0x40, 0xba, 0xf8, 0xbb, 0x55, 0x86, 0xfc, 0x03, ++ 0xde, 0x46, 0x90, 0xe3, 0xd9, 0xd6, 0x8c, 0x78, 0xb6, 0xa6, 0x9b, 0x98, ++ 0x3e, 0x88, 0xfd, 0x61, 0x15, 0x74, 0xb2, 0xeb, 0x71, 0x4c, 0x8f, 0xf2, ++ 0x3b, 0xb4, 0xe0, 0xd8, 0xef, 0x57, 0x60, 0x3c, 0xf6, 0x5b, 0x66, 0x4f, ++ 0x08, 0xca, 0x5b, 0xec, 0xae, 0xdd, 0xb8, 0x9e, 0x58, 0xd0, 0xd7, 0x83, ++ 0xfe, 0xc2, 0x62, 0xf1, 0x5d, 0x8f, 0x9d, 0xf3, 0x47, 0x7c, 0x41, 0x92, ++ 0xe1, 0xfb, 0x2d, 0xae, 0xd9, 0xdd, 0xc8, 0x6f, 0x8b, 0x7d, 0x5c, 0xef, ++ 0x38, 0x3d, 0xc3, 0x0d, 0xfd, 0x5b, 0xd5, 0x75, 0x66, 0x64, 0x32, 0x16, ++ 0xe0, 0xf6, 0xa2, 0xe4, 0x07, 0xe2, 0x4b, 0xe8, 0xf7, 0x6a, 0xbf, 0x42, ++ 0xfa, 0xf5, 0x9a, 0xc5, 0x50, 0x1e, 0xd5, 0xae, 0xb9, 0xe2, 0x53, 0x92, ++ 0xe3, 0xe6, 0x0a, 0xa3, 0x9d, 0x69, 0xf5, 0x1b, 0xeb, 0x7d, 0x6f, 0x92, ++ 0xd0, 0x3b, 0x63, 0xd9, 0xd8, 0x68, 0xfa, 0x47, 0xf0, 0xee, 0xf0, 0xa1, ++ 0x9d, 0x7e, 0xc6, 0xe7, 0x24, 0x3e, 0x06, 0xed, 0xfe, 0xe3, 0x0a, 0x80, ++ 0xaf, 0xed, 0x36, 0x33, 0x9c, 0xaf, 0x35, 0x8e, 0xcf, 0xeb, 0x0c, 0x62, ++ 0x0a, 0xe3, 0xa2, 0x3e, 0x35, 0x84, 0xf1, 0x92, 0x2d, 0x88, 0x07, 0x78, ++ 0x9f, 0x50, 0x66, 0xc4, 0x67, 0xa2, 0xcf, 0x88, 0xbf, 0xe4, 0x39, 0x46, ++ 0x7c, 0xa4, 0xfa, 0x8d, 0xf3, 0x1f, 0xb6, 0x78, 0xa4, 0xa1, 0x3c, 0x23, ++ 0x70, 0x99, 0xa1, 0x3c, 0xb3, 0xd6, 0x6b, 0x80, 0xb3, 0x1b, 0xca, 0x0d, ++ 0xf5, 0x47, 0x6c, 0xac, 0x32, 0xc0, 0xb9, 0xc1, 0x2b, 0x0d, 0xf5, 0x47, ++ 0xb5, 0x2f, 0x34, 0xc0, 0xa3, 0xb7, 0x2d, 0x35, 0xd4, 0x1f, 0xd3, 0xb1, ++ 0xd2, 0x50, 0x3e, 0x36, 0xb4, 0xd6, 0x50, 0x3e, 0x6e, 0x4f, 0xa3, 0x01, ++ 0x1e, 0xdf, 0xf9, 0x5d, 0x43, 0xfd, 0x89, 0x5d, 0x9b, 0x0c, 0xe5, 0x45, ++ 0xe1, 0x7b, 0x0c, 0xe5, 0xc5, 0xdd, 0x3f, 0x30, 0xc0, 0x93, 0x7a, 0x1e, ++ 0x36, 0xd4, 0x9f, 0x7c, 0x62, 0xb7, 0xa1, 0x7c, 0x4a, 0xef, 0x53, 0x86, ++ 0xf2, 0xa9, 0xa7, 0xf6, 0x1b, 0xe0, 0x69, 0x7d, 0xbf, 0x31, 0xd4, 0x9f, ++ 0x71, 0xee, 0xa8, 0x01, 0xae, 0x64, 0x2f, 0x19, 0xea, 0xcf, 0xb4, 0xfd, ++ 0xc1, 0x00, 0xcf, 0x72, 0xff, 0xd9, 0x50, 0xff, 0xf2, 0xf4, 0x77, 0x0d, ++ 0xe5, 0x57, 0xe8, 0x1f, 0x19, 0xca, 0xaf, 0x2a, 0x38, 0x6b, 0xe4, 0xd7, ++ 0x38, 0x2e, 0xff, 0xe6, 0x79, 0xfe, 0x69, 0xf8, 0x4e, 0xc9, 0x0a, 0xbc, ++ 0x3c, 0x09, 0x6d, 0x04, 0xf5, 0xb4, 0x86, 0x7c, 0xdb, 0xb2, 0x4c, 0x61, ++ 0xc9, 0x18, 0x4f, 0xef, 0x5e, 0x64, 0x43, 0x39, 0xf0, 0x8a, 0x94, 0x43, ++ 0x82, 0x0f, 0x9f, 0x47, 0xfd, 0x8c, 0xf5, 0xf3, 0x58, 0x0e, 0xca, 0xb3, ++ 0x59, 0x6a, 0x45, 0x18, 0xd7, 0xed, 0x99, 0x2e, 0x85, 0xd6, 0x7f, 0xac, ++ 0xbe, 0xd3, 0x3e, 0xf2, 0xfb, 0x30, 0x9e, 0xc7, 0x7e, 0xa5, 0x78, 0x30, ++ 0xce, 0x96, 0x00, 0x6a, 0x4b, 0x8b, 0xea, 0x3f, 0xd1, 0x67, 0x03, 0x47, ++ 0x32, 0x02, 0x27, 0xcf, 0x71, 0x1b, 0xe0, 0x54, 0x7f, 0xba, 0xa1, 0xfe, ++ 0xb0, 0xc5, 0xba, 0xa1, 0x3c, 0x23, 0x50, 0x60, 0x28, 0xcf, 0xac, 0xf5, ++ 0x18, 0xe0, 0xec, 0x86, 0x32, 0x43, 0xfd, 0x11, 0x1b, 0x7d, 0x06, 0x38, ++ 0x37, 0x38, 0xc7, 0x50, 0x7f, 0x54, 0xbb, 0xdf, 0x00, 0x8f, 0xde, 0xb6, ++ 0xd8, 0x50, 0x7f, 0x4c, 0x47, 0xc0, 0x50, 0x3e, 0x36, 0x54, 0x6b, 0x28, ++ 0x1f, 0xb7, 0xa7, 0xc1, 0x00, 0x8f, 0xef, 0xdc, 0x68, 0xa8, 0x3f, 0xb1, ++ 0x2b, 0x68, 0x28, 0x2f, 0x0a, 0xb7, 0x1b, 0xca, 0x8b, 0xbb, 0xb7, 0x19, ++ 0xe0, 0x49, 0x3d, 0x1d, 0x86, 0xfa, 0x93, 0x4f, 0x84, 0x0c, 0xe5, 0x53, ++ 0x7a, 0xf7, 0x18, 0xca, 0xa7, 0x9e, 0xea, 0x34, 0xc0, 0xd3, 0xfa, 0xba, ++ 0x0c, 0xf5, 0x67, 0x9c, 0x0b, 0x1b, 0xe0, 0x4a, 0xf6, 0xa2, 0xa1, 0xfe, ++ 0x4c, 0xdb, 0x6b, 0x06, 0x78, 0x96, 0xfb, 0x0d, 0x43, 0xfd, 0xcb, 0xd3, ++ 0xdf, 0x36, 0x94, 0x5f, 0xa1, 0x7f, 0x60, 0x28, 0x97, 0xf6, 0xcd, 0x55, ++ 0x05, 0x9f, 0x1a, 0xdf, 0x0b, 0x7b, 0x67, 0x9e, 0xe7, 0x1f, 0x86, 0xef, ++ 0x83, 0x55, 0x3e, 0x86, 0xfc, 0x11, 0xdc, 0xaf, 0x78, 0x5a, 0x74, 0xc6, ++ 0x0a, 0x4b, 0x47, 0x92, 0x7d, 0x01, 0x72, 0xbd, 0xd7, 0xae, 0xa2, 0x7d, ++ 0xe4, 0xa7, 0xb8, 0x51, 0x12, 0x26, 0x08, 0x02, 0x5f, 0x26, 0x80, 0x10, ++ 0x43, 0xbe, 0x42, 0x57, 0xa1, 0x86, 0xe2, 0x4f, 0x29, 0x14, 0xf7, 0x25, ++ 0xd5, 0xa4, 0x63, 0xbe, 0x0f, 0xd8, 0x09, 0x00, 0x24, 0x99, 0x72, 0x73, ++ 0xd1, 0x9e, 0x8e, 0x8f, 0xd8, 0x6d, 0x59, 0x17, 0x8a, 0x2f, 0xdd, 0x6e, ++ 0x2b, 0x2f, 0x65, 0xc4, 0xe7, 0x37, 0x97, 0x06, 0x26, 0x96, 0xa6, 0xa2, ++ 0xbf, 0xb2, 0x6f, 0x36, 0xda, 0xed, 0x37, 0xb3, 0xe0, 0x66, 0x1c, 0x07, ++ 0xe8, 0xbd, 0x84, 0x5e, 0x5c, 0x1f, 0x76, 0x63, 0x3c, 0x43, 0x3e, 0xaf, ++ 0xb0, 0x01, 0x5e, 0xa2, 0xfa, 0x7b, 0xd1, 0xbe, 0x2d, 0xcb, 0x7b, 0x11, ++ 0xbf, 0xff, 0x0a, 0xdb, 0x69, 0xaa, 0xdf, 0xdf, 0xae, 0x88, 0x73, 0x28, ++ 0x30, 0xbf, 0xc6, 0xa8, 0xf6, 0xef, 0x07, 0xbf, 0x42, 0x03, 0xbb, 0x6e, ++ 0x5b, 0x13, 0xac, 0x1b, 0x70, 0x18, 0x7f, 0xd0, 0xe4, 0x26, 0xf8, 0xa1, ++ 0xa6, 0x74, 0x82, 0x7f, 0xd4, 0xa4, 0xd3, 0xb3, 0xa3, 0xa9, 0x80, 0x9e, ++ 0x0f, 0x37, 0x79, 0xa8, 0x7c, 0x47, 0x53, 0x19, 0xc1, 0x3b, 0x9b, 0x7c, ++ 0x04, 0x87, 0x9a, 0xe6, 0xd0, 0x73, 0x77, 0x93, 0x9f, 0xde, 0x3f, 0xd6, ++ 0xb4, 0x98, 0xe0, 0x27, 0xc0, 0x8f, 0xc6, 0xe7, 0x1e, 0xf0, 0xab, 0xf1, ++ 0xf9, 0x14, 0xf8, 0xc7, 0x58, 0xbe, 0x17, 0xfc, 0x65, 0x84, 0x7f, 0xd1, ++ 0x14, 0xa4, 0x67, 0x67, 0x53, 0x3b, 0xbd, 0xdf, 0xdf, 0xb4, 0x8d, 0xe0, ++ 0x03, 0x4d, 0x1d, 0x04, 0xff, 0xb2, 0x29, 0x44, 0xcf, 0xae, 0xa6, 0x3d, ++ 0xf4, 0xfc, 0x4d, 0x53, 0x27, 0x95, 0x1f, 0x6c, 0xea, 0x22, 0xf8, 0x50, ++ 0x53, 0x98, 0xe0, 0x70, 0x53, 0x37, 0xc1, 0x47, 0x9b, 0x7a, 0x08, 0x3e, ++ 0xde, 0x74, 0x82, 0xe0, 0x17, 0x9a, 0x7a, 0xe9, 0xd9, 0xdd, 0x74, 0x8a, ++ 0x9e, 0xbf, 0x6f, 0xea, 0xa3, 0xf2, 0x97, 0x9b, 0xce, 0x11, 0xfc, 0xa1, ++ 0x88, 0xd7, 0xae, 0x29, 0xe5, 0xf1, 0x22, 0x89, 0x17, 0x09, 0x33, 0x56, ++ 0x4d, 0xfc, 0x20, 0xed, 0xc3, 0xf9, 0x68, 0xe7, 0x23, 0x73, 0x94, 0x99, ++ 0xff, 0x66, 0xb0, 0xf3, 0x63, 0xec, 0xed, 0x58, 0x7a, 0xc8, 0x7e, 0xcc, ++ 0x55, 0x18, 0x13, 0x84, 0xe7, 0xf0, 0xfc, 0xdd, 0x2d, 0x51, 0x7e, 0xd6, ++ 0xad, 0xa2, 0xbf, 0x2d, 0x71, 0x2c, 0x68, 0x07, 0x7e, 0x6f, 0x36, 0x71, ++ 0xbf, 0xb6, 0x39, 0x89, 0x51, 0x9e, 0x35, 0x13, 0xf6, 0xeb, 0x1a, 0xc1, ++ 0x97, 0x2c, 0x85, 0xdb, 0xad, 0xab, 0xc5, 0xb8, 0xd6, 0x88, 0xf5, 0x30, ++ 0x09, 0xf9, 0xb3, 0x80, 0xf8, 0xf3, 0xe5, 0xaf, 0xe3, 0x57, 0x48, 0xbf, ++ 0xf1, 0x4c, 0x61, 0xa0, 0x85, 0xf8, 0x33, 0xdb, 0x14, 0x24, 0xff, 0xd9, ++ 0x11, 0xca, 0x47, 0xfb, 0x39, 0x75, 0x7c, 0x60, 0x73, 0xe9, 0x24, 0xdc, ++ 0x6f, 0xbc, 0xe9, 0x05, 0xea, 0xcf, 0xed, 0xa1, 0x7d, 0xc7, 0x79, 0xd6, ++ 0x70, 0xea, 0x75, 0x18, 0x1f, 0x79, 0x51, 0xa5, 0x78, 0xde, 0x50, 0xfd, ++ 0xd5, 0x8b, 0xfc, 0xf1, 0x21, 0xcb, 0x0f, 0x7d, 0x90, 0x85, 0xf6, 0xf6, ++ 0x9c, 0x2f, 0xd5, 0x00, 0xe2, 0xe9, 0x15, 0xb3, 0x73, 0x31, 0xc6, 0x0b, ++ 0xb6, 0x97, 0x72, 0xff, 0x74, 0x7b, 0xa9, 0xc9, 0xf0, 0xfc, 0xc9, 0xf8, ++ 0x40, 0x07, 0x8e, 0xe7, 0x73, 0x67, 0xc3, 0x0d, 0x26, 0x18, 0xff, 0xe7, ++ 0xd3, 0x37, 0x3c, 0x71, 0x6b, 0x6e, 0xc4, 0x9f, 0xbe, 0x1a, 0x5d, 0x52, ++ 0xf0, 0x83, 0x16, 0x30, 0xdd, 0x4c, 0xf9, 0x89, 0xcc, 0xf7, 0x7c, 0x2e, ++ 0x34, 0x75, 0x0d, 0x18, 0x58, 0x08, 0x5f, 0xc7, 0x82, 0xf4, 0xcc, 0x2a, ++ 0x0c, 0xec, 0xc2, 0xf9, 0x2e, 0x01, 0x43, 0x1c, 0xe1, 0x40, 0xb9, 0x35, ++ 0x67, 0xb0, 0x79, 0xc5, 0x8e, 0x6b, 0xaf, 0x18, 0xd7, 0x5e, 0x31, 0x1e, ++ 0xf9, 0x7c, 0x71, 0x7c, 0xe0, 0x69, 0x6c, 0xef, 0x73, 0xa7, 0x8f, 0xc6, ++ 0xf5, 0xca, 0x94, 0xcb, 0xf3, 0x71, 0x5e, 0x72, 0x5c, 0x71, 0x13, 0x74, ++ 0x71, 0x9e, 0xa1, 0x6f, 0x27, 0x8e, 0xef, 0xf3, 0xe7, 0x3e, 0x3d, 0xa9, ++ 0x8c, 0x8a, 0xe0, 0x5f, 0xfa, 0xed, 0x9b, 0x2b, 0x45, 0x5e, 0xc9, 0x06, ++ 0x85, 0xc7, 0xe5, 0xa4, 0xbd, 0x26, 0xf2, 0x52, 0xa4, 0xdf, 0x51, 0x73, ++ 0xbb, 0x12, 0x42, 0x7b, 0x7d, 0x19, 0xf8, 0x3b, 0xb8, 0xbf, 0xf4, 0xa6, ++ 0xb0, 0x3f, 0xdf, 0xb4, 0x73, 0xfd, 0x7c, 0xa6, 0xc1, 0x5c, 0x80, 0x76, ++ 0x7d, 0x8d, 0x12, 0xe7, 0xc1, 0x7d, 0xb8, 0x33, 0x0d, 0xff, 0xe5, 0x40, ++ 0x77, 0x1a, 0xea, 0x33, 0xdc, 0x27, 0x69, 0xc1, 0x9c, 0x03, 0x28, 0x6f, ++ 0xb9, 0x43, 0xa1, 0x7c, 0xee, 0x1a, 0x68, 0xc7, 0x04, 0xed, 0xd4, 0x60, ++ 0x20, 0x10, 0xbf, 0xbb, 0x4b, 0x21, 0xfe, 0xfb, 0x62, 0x7c, 0x2e, 0x8d, ++ 0xaf, 0x06, 0xcc, 0x3f, 0xf2, 0xb3, 0x52, 0xfa, 0x72, 0x70, 0xbf, 0x14, ++ 0xf8, 0xe5, 0x45, 0xa4, 0xc3, 0xda, 0x29, 0x6a, 0xd0, 0x02, 0xf6, 0xf0, ++ 0x2b, 0xa6, 0x50, 0xbe, 0x42, 0xfb, 0xd2, 0x37, 0x59, 0x14, 0x18, 0xe7, ++ 0x9a, 0x14, 0xe0, 0x93, 0x91, 0x43, 0xf3, 0xc3, 0x7a, 0x71, 0xfe, 0x40, ++ 0xbe, 0x07, 0x3e, 0xfb, 0x03, 0xb6, 0xf7, 0xb7, 0x5f, 0x4f, 0x2e, 0xa0, ++ 0x38, 0xfe, 0xa1, 0x29, 0x3a, 0xe2, 0xad, 0xc5, 0xc4, 0xcf, 0x23, 0x05, ++ 0x7f, 0xaf, 0x7a, 0x78, 0xbe, 0x0b, 0x17, 0xd5, 0xea, 0xd4, 0xf1, 0x14, ++ 0xa7, 0x64, 0x9a, 0xc7, 0x83, 0x71, 0xa6, 0x79, 0xe2, 0xfc, 0xca, 0x11, ++ 0x95, 0x6d, 0xdc, 0x37, 0x88, 0x1c, 0xfd, 0xbb, 0xa0, 0xdb, 0x2b, 0xe9, ++ 0xe6, 0x39, 0x21, 0x6a, 0xd7, 0xb8, 0x5f, 0xf3, 0xb1, 0xa0, 0xe3, 0xc7, ++ 0xa2, 0xde, 0xbc, 0xa3, 0x2f, 0x66, 0xe3, 0xf9, 0xab, 0xf5, 0xdd, 0x66, ++ 0xb2, 0x47, 0x58, 0x49, 0x6f, 0xa1, 0xdf, 0x39, 0xc8, 0x7c, 0x36, 0x6e, ++ 0xfd, 0x76, 0x5e, 0x14, 0x7f, 0xd7, 0x77, 0xbd, 0xcd, 0xf3, 0x35, 0x58, ++ 0x6f, 0x61, 0x74, 0x7e, 0xba, 0x6b, 0x32, 0x6f, 0x57, 0xf2, 0x93, 0x6a, ++ 0x71, 0x06, 0x76, 0x39, 0xa2, 0xc7, 0xd7, 0xcf, 0xdf, 0x9f, 0x11, 0x7f, ++ 0x27, 0x02, 0x7f, 0x8f, 0x22, 0xfe, 0x3e, 0x89, 0xf6, 0xf6, 0x7c, 0xab, ++ 0x9e, 0x70, 0x1d, 0x3c, 0x7b, 0x01, 0x45, 0x61, 0x78, 0x06, 0x7e, 0xea, ++ 0xa6, 0x7c, 0x23, 0x99, 0x77, 0xb4, 0x8a, 0xf9, 0xe9, 0xb9, 0x06, 0xd8, ++ 0x01, 0xf9, 0xd9, 0x1f, 0x7c, 0xc0, 0x82, 0xf8, 0x5f, 0xcb, 0x3a, 0xe9, ++ 0xfd, 0xfa, 0xb2, 0x1b, 0x73, 0x10, 0xae, 0x67, 0x7d, 0xd5, 0xe9, 0xe8, ++ 0x4f, 0xb4, 0x37, 0x3f, 0x9f, 0x0e, 0xa3, 0x5c, 0xb4, 0xed, 0x81, 0x59, ++ 0x18, 0x9f, 0x5d, 0x18, 0x5a, 0xf1, 0x3c, 0x3e, 0x17, 0x3c, 0xa6, 0x9c, ++ 0x44, 0xff, 0x15, 0xd6, 0x87, 0x79, 0x32, 0xc6, 0x4f, 0x94, 0x86, 0xb6, ++ 0xe1, 0xd0, 0xdf, 0xd2, 0xbd, 0x95, 0x6d, 0x99, 0xf0, 0x7e, 0xbe, 0xca, ++ 0xe9, 0xc1, 0x5e, 0xe2, 0xf4, 0x00, 0xbe, 0xf1, 0xa9, 0x49, 0x03, 0xe7, ++ 0x09, 0xeb, 0xc1, 0x39, 0x99, 0xe6, 0xe1, 0xa3, 0x79, 0xa8, 0xae, 0x39, ++ 0x86, 0xf5, 0x50, 0xb3, 0x89, 0xf9, 0x94, 0x94, 0x48, 0xfe, 0x7c, 0xff, ++ 0xfa, 0x28, 0xbb, 0xe5, 0xaf, 0x99, 0xe8, 0x0f, 0x69, 0x7d, 0xb4, 0xff, ++ 0x5e, 0x7f, 0xc8, 0x9a, 0x84, 0x74, 0x5e, 0xcb, 0xb8, 0xfe, 0x8e, 0xc4, ++ 0x3f, 0xa4, 0xde, 0x66, 0xc4, 0xe7, 0xb7, 0xb0, 0x38, 0x0f, 0xd6, 0xfb, ++ 0x50, 0xf0, 0xf5, 0x87, 0xd9, 0x8c, 0xf8, 0xfa, 0x43, 0x05, 0x1c, 0x3c, ++ 0x6f, 0xc4, 0x9e, 0x64, 0x39, 0x81, 0x74, 0xef, 0xa8, 0x88, 0xfe, 0xfd, ++ 0xd0, 0x14, 0x2a, 0x75, 0x8d, 0x22, 0xfd, 0x9c, 0x87, 0xf3, 0x7d, 0x21, ++ 0x7d, 0x91, 0x8e, 0x71, 0xb3, 0x5b, 0x52, 0x6c, 0x1e, 0x15, 0xcb, 0x13, ++ 0x43, 0x39, 0x7c, 0x1f, 0xb5, 0x5f, 0xce, 0xb3, 0x0b, 0xf1, 0x91, 0xb8, ++ 0xd7, 0xfd, 0x66, 0x1e, 0x87, 0x8a, 0x1d, 0x97, 0x52, 0xf6, 0xc2, 0x3f, ++ 0xd0, 0x7e, 0xb0, 0x5a, 0x58, 0x10, 0xf7, 0x37, 0x60, 0x7d, 0xb3, 0x52, ++ 0x5c, 0xd7, 0xc3, 0x2d, 0xb4, 0xae, 0x5a, 0x10, 0xb5, 0x18, 0x3f, 0xab, ++ 0xf2, 0xeb, 0x83, 0xb5, 0xdf, 0x2a, 0xda, 0xed, 0xfe, 0x82, 0xfb, 0xc1, ++ 0x41, 0x98, 0x0f, 0x9e, 0x97, 0x1c, 0xd0, 0x8f, 0x5b, 0xf4, 0x13, 0xc7, ++ 0xfb, 0x91, 0x7a, 0x04, 0xfb, 0x23, 0x39, 0x92, 0xc6, 0x0c, 0xfd, 0xcd, ++ 0xc2, 0x24, 0x17, 0xa0, 0xcb, 0x2b, 0x4e, 0x1f, 0x8d, 0xbf, 0xd9, 0x94, ++ 0x48, 0x72, 0xe7, 0xe3, 0x11, 0x81, 0x6a, 0xa4, 0x97, 0x8c, 0xff, 0x48, ++ 0xff, 0xb0, 0x3b, 0xf7, 0xfd, 0x3c, 0xf2, 0xe3, 0xcf, 0xb7, 0x64, 0xa1, ++ 0x9d, 0x0e, 0xfc, 0xcb, 0xf3, 0x12, 0xa7, 0x73, 0xf9, 0xf4, 0x8a, 0x59, ++ 0x0f, 0x22, 0xfc, 0x4a, 0x65, 0x2e, 0xc5, 0xff, 0xa5, 0xdc, 0xbd, 0xba, ++ 0x8c, 0xc7, 0xcb, 0xae, 0x96, 0xf1, 0xb1, 0x8a, 0x98, 0xf8, 0x58, 0x4c, ++ 0x5c, 0x86, 0x55, 0x0c, 0x1e, 0x2f, 0x63, 0xcc, 0x63, 0xc6, 0x7e, 0xc7, ++ 0xb2, 0x37, 0x25, 0x7e, 0x28, 0x1e, 0x73, 0xb4, 0x42, 0x23, 0xba, 0x07, ++ 0x81, 0xee, 0x18, 0x6f, 0x3e, 0x2a, 0xfc, 0xd4, 0xca, 0x78, 0xee, 0x9f, ++ 0x77, 0x4e, 0x4e, 0x26, 0x7e, 0x4a, 0xba, 0x22, 0x6f, 0xd0, 0x7d, 0x15, ++ 0xf9, 0xbc, 0x47, 0xc4, 0x57, 0xef, 0x05, 0x3b, 0x88, 0x45, 0xc5, 0xd5, ++ 0xef, 0x29, 0x69, 0xb4, 0x61, 0x9e, 0xc1, 0x96, 0x42, 0x85, 0xf6, 0xbb, ++ 0xee, 0xab, 0x8a, 0xab, 0x8d, 0xce, 0x73, 0xdf, 0x3b, 0xcd, 0xcc, 0xf7, ++ 0x53, 0xa7, 0x57, 0xee, 0x44, 0xbc, 0x15, 0x3a, 0x42, 0x55, 0xa4, 0xae, ++ 0x7d, 0x9a, 0x8e, 0xf3, 0x50, 0xc4, 0xbc, 0xc6, 0xb9, 0x01, 0xef, 0x26, ++ 0x6c, 0xda, 0x2f, 0xe2, 0xa4, 0x1e, 0x1b, 0x8f, 0x4b, 0x55, 0x93, 0xbe, ++ 0x96, 0xf4, 0xbe, 0x54, 0x7d, 0xfd, 0x94, 0x16, 0xda, 0x14, 0x87, 0xf3, ++ 0x4e, 0x61, 0xb4, 0xfe, 0x9c, 0x1d, 0x76, 0x92, 0xa3, 0x6a, 0xa7, 0x2f, ++ 0x8c, 0x29, 0xd7, 0x5f, 0x4e, 0x5b, 0x78, 0x27, 0xd1, 0x51, 0xf3, 0x17, ++ 0x60, 0x3f, 0x47, 0x4a, 0xe3, 0x98, 0x03, 0xea, 0x7f, 0x7e, 0xc4, 0x42, ++ 0xfe, 0xfd, 0x21, 0xd3, 0xca, 0x9f, 0x62, 0x3e, 0x7c, 0xdf, 0x1b, 0x56, ++ 0x86, 0xfb, 0x9e, 0x9d, 0xce, 0x4c, 0x0d, 0xf5, 0x45, 0xe7, 0x17, 0x97, ++ 0x55, 0xd3, 0xd3, 0x39, 0x75, 0x36, 0xe3, 0x71, 0xce, 0x78, 0x13, 0x08, ++ 0x88, 0x22, 0x37, 0x7b, 0xf4, 0xdf, 0x90, 0x58, 0xe2, 0xdc, 0x59, 0xa7, ++ 0xc2, 0xba, 0x19, 0xc5, 0xdb, 0x7c, 0xf1, 0x26, 0xf0, 0xc1, 0x3a, 0x4d, ++ 0xec, 0xec, 0x0c, 0x18, 0xd7, 0x7e, 0x87, 0xf7, 0xc1, 0x89, 0xc4, 0x72, ++ 0x7e, 0x15, 0xe7, 0xd9, 0x55, 0x11, 0xb8, 0x1f, 0xd7, 0x53, 0x29, 0x6b, ++ 0x20, 0xf8, 0x3e, 0x8b, 0xbf, 0x76, 0x17, 0xf4, 0x7b, 0x5f, 0x92, 0x8d, ++ 0xf8, 0xc4, 0x5f, 0xe1, 0x7f, 0x80, 0x8f, 0x93, 0xb5, 0xcd, 0x85, 0xf1, ++ 0x4d, 0x9f, 0xa9, 0x30, 0x3c, 0xc7, 0xdb, 0x66, 0x01, 0xb9, 0x5c, 0x88, ++ 0x71, 0x92, 0x38, 0xbe, 0x27, 0xc5, 0xb8, 0x7d, 0xef, 0x3f, 0x97, 0x4f, ++ 0xfd, 0xef, 0x98, 0xcc, 0xf7, 0xf9, 0x5a, 0xd3, 0x7d, 0x3d, 0x78, 0x60, ++ 0x64, 0x48, 0xbc, 0xb9, 0xb5, 0xbe, 0xfe, 0xb8, 0x08, 0xf1, 0x5b, 0x16, ++ 0xc5, 0xf3, 0x24, 0x1e, 0xa3, 0xe9, 0xe5, 0x2e, 0x35, 0xd0, 0x2b, 0x60, ++ 0x8e, 0xa6, 0x57, 0x19, 0xd0, 0x6b, 0x7c, 0x34, 0xbd, 0x7c, 0xca, 0xd7, ++ 0xa1, 0xd7, 0xed, 0x98, 0x5c, 0x36, 0x69, 0x20, 0x7f, 0x06, 0xab, 0xf4, ++ 0x07, 0xaa, 0x4b, 0xb8, 0x5e, 0xc3, 0x14, 0xb9, 0x4a, 0x6b, 0x76, 0x21, ++ 0xda, 0xeb, 0x47, 0xe2, 0x32, 0x0b, 0xa3, 0xf7, 0xf5, 0x24, 0x5f, 0x4a, ++ 0x3e, 0x1d, 0x84, 0x3f, 0x37, 0x1c, 0x43, 0xf9, 0x90, 0xa5, 0xb9, 0x31, ++ 0x7e, 0x6a, 0x9d, 0x17, 0x47, 0xfb, 0x2d, 0x92, 0x5f, 0x25, 0x9f, 0xfe, ++ 0x75, 0x4a, 0x3f, 0xbf, 0x7a, 0xcb, 0xe1, 0xb9, 0xcc, 0xe1, 0x9f, 0x85, ++ 0x32, 0x24, 0x96, 0x5f, 0x31, 0x1e, 0x16, 0xcd, 0x97, 0x35, 0x43, 0xf2, ++ 0x2f, 0x73, 0x47, 0xaf, 0xd7, 0xf9, 0x60, 0x3f, 0x24, 0x24, 0xa1, 0xdd, ++ 0x73, 0xea, 0xb1, 0xce, 0x28, 0xbe, 0xac, 0x69, 0xf8, 0x54, 0xe3, 0xf2, ++ 0xe3, 0xc2, 0x8c, 0xb8, 0xd2, 0x48, 0xfc, 0x6e, 0x7e, 0x85, 0xc2, 0xde, ++ 0x89, 0xa6, 0x2f, 0xfc, 0x7b, 0xa7, 0x40, 0xcc, 0x8f, 0xec, 0x1e, 0x8d, ++ 0xfc, 0x2d, 0x89, 0xc7, 0x4b, 0xc5, 0xb7, 0xf9, 0x5b, 0xcd, 0x05, 0x68, ++ 0xc7, 0x6d, 0xc6, 0xf3, 0x89, 0x80, 0xaf, 0x76, 0xc5, 0xe3, 0x1b, 0x86, ++ 0x71, 0xad, 0x86, 0xb7, 0x6f, 0xc5, 0xf7, 0x6d, 0xe2, 0x7c, 0x70, 0xb0, ++ 0xd0, 0xc2, 0xed, 0x2b, 0xb1, 0x4e, 0x64, 0x7b, 0x5f, 0x4e, 0xab, 0x7a, ++ 0x07, 0xf9, 0xd6, 0x39, 0xf9, 0x74, 0xfc, 0x6a, 0xa8, 0xf7, 0x79, 0x9a, ++ 0x49, 0x47, 0xe4, 0xb4, 0xe9, 0x2b, 0xff, 0x8d, 0xd6, 0xdd, 0x89, 0x78, ++ 0x86, 0xdf, 0xb9, 0x92, 0x7b, 0x6a, 0x1f, 0xa5, 0x75, 0x34, 0x86, 0xe1, ++ 0xfe, 0xe0, 0xe7, 0x37, 0x07, 0x46, 0xe0, 0x7e, 0xfd, 0xdd, 0x40, 0xa7, ++ 0x77, 0x28, 0x99, 0x3a, 0x34, 0xcc, 0x44, 0x7b, 0x59, 0xbd, 0xc3, 0x70, ++ 0x1d, 0x01, 0x72, 0xd3, 0xf9, 0x33, 0x90, 0xce, 0xdf, 0x33, 0x51, 0x1e, ++ 0x22, 0xf8, 0x3b, 0x53, 0x46, 0x0a, 0xbf, 0xc3, 0x27, 0xea, 0xf7, 0x52, ++ 0xfd, 0xbb, 0x2d, 0xdb, 0x6c, 0x71, 0xd8, 0x4f, 0xae, 0xcd, 0xbd, 0x3b, ++ 0x8a, 0xdf, 0x67, 0x88, 0xf8, 0x3a, 0x1e, 0x23, 0xe7, 0xfb, 0x67, 0x2d, ++ 0x3a, 0xda, 0x65, 0x7a, 0x19, 0xd7, 0xbf, 0x0f, 0x36, 0xed, 0x99, 0xf6, ++ 0xde, 0x68, 0x1c, 0x4f, 0xe7, 0xb4, 0xf7, 0x60, 0x3c, 0xc9, 0x73, 0x43, ++ 0x2c, 0x00, 0x7c, 0x1c, 0x57, 0x10, 0xd4, 0x31, 0x05, 0xc4, 0xf6, 0xe5, ++ 0x4c, 0x05, 0xcf, 0x2f, 0xb0, 0xcb, 0x58, 0x27, 0xf2, 0x0d, 0xbe, 0x6f, ++ 0x1e, 0x1f, 0x69, 0xdf, 0x5c, 0xc6, 0xd7, 0x99, 0x0d, 0xed, 0x15, 0xa0, ++ 0x9f, 0x6d, 0x53, 0x50, 0x4f, 0x8a, 0x92, 0x7f, 0x36, 0x93, 0x12, 0x18, ++ 0x2c, 0xdf, 0xe5, 0x8e, 0x29, 0x1a, 0xff, 0x6e, 0x13, 0xa3, 0x72, 0xdb, ++ 0xd1, 0xed, 0x74, 0x9e, 0x3f, 0x39, 0xcf, 0xa3, 0x60, 0xde, 0xb3, 0x6d, ++ 0xd3, 0x36, 0x86, 0xfb, 0x31, 0xf6, 0x30, 0x7f, 0x9f, 0x92, 0xe7, 0x53, ++ 0x56, 0x45, 0xb5, 0x9b, 0x32, 0x17, 0xc6, 0x1d, 0xc5, 0x17, 0xf3, 0xf1, ++ 0x24, 0x01, 0xc8, 0x1b, 0xdb, 0x6e, 0x60, 0xcc, 0x12, 0xa4, 0x43, 0x1c, ++ 0xc5, 0x1f, 0x63, 0xfb, 0x9d, 0x9f, 0x5a, 0xd5, 0xad, 0xb9, 0x86, 0xe6, ++ 0x93, 0x58, 0x7e, 0x63, 0x82, 0xdf, 0x24, 0xdf, 0xc8, 0x79, 0xd2, 0xc9, ++ 0x94, 0xa8, 0x73, 0xf9, 0xd5, 0x23, 0xb9, 0x3d, 0xdc, 0xb6, 0xd1, 0xb2, ++ 0x0b, 0xed, 0xed, 0xf2, 0xb2, 0x44, 0xc2, 0xef, 0x67, 0x29, 0x55, 0x09, ++ 0xec, 0x22, 0x7a, 0x65, 0x27, 0xf0, 0x41, 0xd0, 0x8a, 0xfe, 0xb1, 0x8d, ++ 0x9e, 0xbb, 0xc1, 0xbf, 0x0e, 0x8e, 0x41, 0xff, 0x38, 0x9d, 0xe0, 0x27, ++ 0xc0, 0xbf, 0xc6, 0xe7, 0x1e, 0xf0, 0xaf, 0xf1, 0xf9, 0x14, 0xf8, 0xd7, ++ 0x58, 0xbe, 0x17, 0xfc, 0x6b, 0x84, 0x7f, 0x01, 0xfe, 0x35, 0xc2, 0x9d, ++ 0xe0, 0x5f, 0x23, 0xbc, 0x1f, 0xfc, 0x6b, 0x84, 0x0f, 0x80, 0x7f, 0x8d, ++ 0xf0, 0x2f, 0xc1, 0xbf, 0xc6, 0x67, 0x17, 0xf8, 0xd7, 0xf8, 0xfc, 0x0d, ++ 0xf8, 0xd7, 0x58, 0x7e, 0x10, 0xfc, 0x6b, 0x84, 0x67, 0x58, 0x81, 0x3f, ++ 0x70, 0x3e, 0x05, 0xc1, 0xf4, 0x85, 0x40, 0xd7, 0xf6, 0x3b, 0x2c, 0x3e, ++ 0xcc, 0x17, 0xdc, 0x20, 0xe8, 0x7a, 0xcc, 0x37, 0x32, 0xd9, 0x03, 0xf4, ++ 0xb7, 0x17, 0x98, 0x28, 0xf6, 0x6d, 0x7f, 0xf9, 0x07, 0x0c, 0xe7, 0x63, ++ 0x4f, 0x37, 0xd1, 0xf9, 0xaf, 0xcd, 0xe9, 0x3f, 0x60, 0x37, 0xa2, 0xdf, ++ 0x5a, 0xea, 0x24, 0xbb, 0xa9, 0xed, 0xe7, 0xdc, 0x1e, 0xb1, 0x6b, 0x0f, ++ 0x32, 0x94, 0x3b, 0x3b, 0x95, 0x60, 0x2d, 0xf3, 0x30, 0xb6, 0xb8, 0x6c, ++ 0x6c, 0x0d, 0xee, 0xf3, 0xe5, 0xa5, 0x6f, 0xa8, 0x4a, 0x02, 0xf8, 0x86, ++ 0xb2, 0x89, 0x3b, 0x6c, 0xb0, 0x3e, 0xf2, 0xf5, 0x05, 0x8b, 0x9b, 0xa3, ++ 0x60, 0xdd, 0xe9, 0x5d, 0xbb, 0xcf, 0x1d, 0x81, 0x47, 0x14, 0xee, 0xd2, ++ 0xc0, 0x33, 0x61, 0x37, 0x76, 0x15, 0xed, 0xc0, 0xa3, 0x3f, 0x38, 0x0e, ++ 0xcc, 0x13, 0xae, 0x2b, 0x2b, 0xa9, 0x69, 0x06, 0x16, 0x0a, 0x8f, 0x64, ++ 0x64, 0x57, 0xf4, 0xe5, 0x5a, 0x28, 0x3f, 0x67, 0x15, 0xd2, 0x6b, 0x34, ++ 0x8e, 0x9f, 0xc7, 0x0d, 0xaf, 0x62, 0x2d, 0xe9, 0xb8, 0x6f, 0x39, 0x42, ++ 0x07, 0xef, 0x47, 0xa1, 0xfa, 0x61, 0x96, 0x72, 0xe9, 0xf5, 0x37, 0x94, ++ 0xe9, 0xf4, 0x3e, 0xf6, 0xbb, 0x8b, 0xd5, 0x33, 0x95, 0x5c, 0x52, 0x3d, ++ 0xa6, 0x5e, 0xa4, 0x3d, 0x2c, 0x57, 0x2e, 0xd2, 0x8e, 0x4d, 0x59, 0x64, ++ 0xeb, 0x81, 0xb1, 0x6f, 0x35, 0x0b, 0x39, 0x95, 0xea, 0x20, 0x39, 0xd5, ++ 0x8e, 0x71, 0x1c, 0xc0, 0x7b, 0xbb, 0x9d, 0x3f, 0xbb, 0xa7, 0xf0, 0xb8, ++ 0xc1, 0xae, 0x29, 0x55, 0xde, 0x29, 0xf0, 0xf4, 0x4e, 0xe1, 0x74, 0x6d, ++ 0xb7, 0x07, 0xdd, 0x55, 0xd8, 0xff, 0x78, 0x13, 0xe5, 0x2d, 0xb0, 0x8d, ++ 0xb9, 0x7f, 0x18, 0x09, 0xfd, 0x7d, 0xfb, 0xf7, 0x1a, 0xc3, 0xbc, 0x4f, ++ 0xc9, 0x9f, 0xed, 0x82, 0x0f, 0x46, 0x8f, 0x70, 0xd2, 0xf9, 0x7b, 0x76, ++ 0xa7, 0x8d, 0xf6, 0xed, 0x2f, 0x1f, 0xf1, 0xf3, 0xd6, 0x24, 0x80, 0x47, ++ 0x3f, 0xea, 0xf1, 0x60, 0x7e, 0xc3, 0x56, 0xe6, 0x89, 0x43, 0x3e, 0x09, ++ 0xde, 0x6b, 0xa2, 0xfc, 0xc6, 0xa7, 0x4b, 0x46, 0x25, 0x2d, 0x80, 0xea, ++ 0xe3, 0x26, 0x3d, 0x9b, 0x84, 0x72, 0xfd, 0xa4, 0x90, 0x37, 0x21, 0x91, ++ 0x17, 0xd4, 0xdc, 0xb6, 0x7a, 0x04, 0xea, 0xb1, 0xcf, 0x5f, 0xe3, 0xf2, ++ 0xf0, 0xc7, 0x42, 0x3e, 0xed, 0x32, 0xf7, 0x34, 0x10, 0x3d, 0x27, 0x39, ++ 0xc8, 0xee, 0x60, 0x6c, 0x1b, 0xd9, 0x17, 0xcd, 0xe9, 0x40, 0x6c, 0xd0, ++ 0x91, 0xa6, 0x0c, 0xfe, 0xb4, 0x98, 0xdd, 0x4b, 0xb1, 0x9e, 0x05, 0x0c, ++ 0x01, 0xcc, 0xbf, 0xb6, 0x7c, 0x31, 0xd9, 0x86, 0x7e, 0x5d, 0xcb, 0x39, ++ 0xeb, 0x1c, 0x9e, 0x1f, 0xdb, 0x43, 0x76, 0x87, 0xc5, 0x1e, 0x70, 0x27, ++ 0xc2, 0xfb, 0x6d, 0x41, 0x13, 0xc9, 0x85, 0x16, 0xdd, 0x41, 0xf9, 0x6c, ++ 0x5b, 0x1d, 0xde, 0x6e, 0x3c, 0xcf, 0x1c, 0x74, 0x9b, 0x28, 0xef, 0x75, ++ 0x6b, 0xa1, 0x89, 0xf0, 0xd8, 0xea, 0xb8, 0x36, 0x84, 0xf6, 0xbc, 0xa6, ++ 0x34, 0xd7, 0xa2, 0x1e, 0x0b, 0xb9, 0xf7, 0xdb, 0x72, 0xe1, 0x7d, 0xa8, ++ 0xd0, 0x44, 0x79, 0x8c, 0x21, 0xdf, 0xc2, 0x39, 0x08, 0x07, 0x03, 0x1a, ++ 0xe5, 0x59, 0xd1, 0x0f, 0x96, 0x07, 0x92, 0xe8, 0x1c, 0xf7, 0x56, 0xd6, ++ 0xf7, 0xd2, 0x44, 0x2c, 0xaf, 0xe1, 0x76, 0x57, 0x5b, 0xda, 0x7f, 0x1f, ++ 0x8d, 0xc7, 0x38, 0xf7, 0x35, 0x6e, 0x0f, 0xdf, 0x56, 0x61, 0x3a, 0xe6, ++ 0x81, 0x51, 0x4a, 0x98, 0x09, 0xfd, 0xeb, 0xde, 0x4d, 0xf1, 0x38, 0x8e, ++ 0x25, 0x4c, 0xf8, 0xad, 0x41, 0xf2, 0x53, 0x5d, 0x56, 0x4e, 0xbf, 0xef, ++ 0x1f, 0xb9, 0xc2, 0x3d, 0x92, 0xec, 0x8a, 0xa8, 0xfd, 0x2b, 0x2b, 0xc6, ++ 0xe4, 0x3c, 0x36, 0x0f, 0x94, 0x4f, 0x70, 0x78, 0xe7, 0xa0, 0x1f, 0xa9, ++ 0x39, 0xbd, 0x36, 0xcc, 0xef, 0x6b, 0x75, 0x7b, 0x6d, 0x2b, 0x68, 0xfe, ++ 0x3c, 0x2f, 0x8d, 0xf2, 0x2f, 0xa0, 0xdd, 0x16, 0xb7, 0x89, 0xfc, 0x59, ++ 0x2c, 0xbf, 0xb1, 0x90, 0xd4, 0xe1, 0xf1, 0xbc, 0x52, 0x91, 0x72, 0xaf, ++ 0xe3, 0xbc, 0x7f, 0x70, 0x04, 0xf1, 0xa1, 0xdd, 0xc4, 0x58, 0xae, 0x8e, ++ 0xe3, 0xd3, 0x82, 0xd1, 0xfb, 0x83, 0xb6, 0x51, 0x15, 0xdd, 0x3a, 0xcc, ++ 0xa3, 0x7d, 0x75, 0x12, 0xcd, 0x43, 0x53, 0x3c, 0x04, 0xb3, 0x9b, 0x34, ++ 0x1a, 0xf7, 0x70, 0x3d, 0x8e, 0xce, 0x2f, 0x3f, 0x68, 0x99, 0xd7, 0x8d, ++ 0xf6, 0xe1, 0x70, 0xdb, 0x2d, 0xb4, 0x8f, 0x95, 0x51, 0xab, 0x19, 0xf6, ++ 0x99, 0x86, 0x05, 0x8c, 0x70, 0xea, 0x62, 0x23, 0x9c, 0xcc, 0xb4, 0xc8, ++ 0x3e, 0x15, 0xf4, 0xfb, 0xae, 0xe0, 0x9b, 0x58, 0xbc, 0xc5, 0xe2, 0x23, ++ 0xc3, 0xdd, 0xfa, 0x1a, 0x8e, 0x3f, 0x23, 0x40, 0x87, 0x6b, 0x07, 0x8c, ++ 0x7f, 0xbb, 0xfb, 0xa1, 0xc4, 0x4a, 0x86, 0xe3, 0x74, 0xd0, 0x38, 0xd3, ++ 0x1c, 0x2b, 0x2b, 0xd1, 0x7e, 0x4a, 0x65, 0xfe, 0x66, 0xe4, 0xbf, 0x7f, ++ 0x75, 0x9c, 0x13, 0xdc, 0x0b, 0x6d, 0xb9, 0xd0, 0xff, 0x84, 0x14, 0x13, ++ 0x99, 0x47, 0x13, 0x59, 0xdf, 0x26, 0x6c, 0x77, 0xab, 0xe0, 0xf7, 0xf6, ++ 0x5c, 0x4e, 0xcf, 0xc8, 0xba, 0x52, 0x39, 0xbf, 0x4f, 0xa9, 0xca, 0x9c, ++ 0x92, 0x8a, 0xfb, 0x04, 0x26, 0x70, 0xcc, 0x22, 0xed, 0xe7, 0x06, 0xc1, ++ 0x41, 0x33, 0xec, 0x13, 0x24, 0x19, 0xe0, 0xd1, 0xdb, 0x86, 0x1b, 0xea, ++ 0x8f, 0xe9, 0x18, 0x69, 0x28, 0x1f, 0x1b, 0xba, 0xcc, 0x50, 0x3e, 0x6e, ++ 0x8f, 0xd7, 0x00, 0x8f, 0xef, 0x2c, 0x37, 0xd4, 0x9f, 0xd8, 0x55, 0x65, ++ 0x80, 0x8b, 0xc2, 0x57, 0x1a, 0xea, 0x17, 0x77, 0x2f, 0x34, 0xc0, 0x93, ++ 0x7a, 0x96, 0x1a, 0xea, 0x4f, 0x3e, 0xb1, 0xd2, 0x50, 0x3e, 0xa5, 0x77, ++ 0xad, 0xa1, 0x7c, 0xea, 0xa9, 0x46, 0x03, 0x3c, 0xad, 0xef, 0xbb, 0x86, ++ 0xfa, 0xd2, 0x9e, 0x8f, 0xd5, 0x8f, 0xa9, 0x53, 0xbe, 0x99, 0x1d, 0x6f, ++ 0x4d, 0x1f, 0x6e, 0xb8, 0xc7, 0x26, 0xd6, 0x4f, 0x88, 0xb5, 0xf3, 0x6d, ++ 0x5f, 0xb6, 0xe8, 0x9b, 0x90, 0x9f, 0x5d, 0x16, 0xe2, 0x67, 0x0d, 0xf5, ++ 0x39, 0xee, 0x2b, 0xdf, 0xc1, 0xfd, 0x21, 0xdb, 0x74, 0x8f, 0x8e, 0xf2, ++ 0x25, 0x5e, 0xc8, 0xd3, 0x57, 0xa6, 0xfb, 0x46, 0x22, 0xdd, 0x2a, 0x5d, ++ 0x36, 0xd2, 0x0b, 0x9a, 0x83, 0xd7, 0xd3, 0x1c, 0xb3, 0xc9, 0x5e, 0xc9, ++ 0xe9, 0xb0, 0xd0, 0xfd, 0x3a, 0x9a, 0x9b, 0xf5, 0x97, 0xc7, 0xa3, 0x7c, ++ 0x6e, 0x0a, 0x4e, 0xcb, 0x1b, 0x1d, 0x19, 0xb7, 0xdd, 0xbd, 0x8d, 0xee, ++ 0xa9, 0xa8, 0x74, 0xcd, 0x61, 0x98, 0x77, 0x24, 0xbf, 0xd7, 0xdc, 0x3e, ++ 0x16, 0x70, 0x62, 0x7f, 0x3a, 0xb7, 0x93, 0xdc, 0x41, 0xaa, 0x67, 0xd7, ++ 0xe1, 0xfb, 0xa8, 0x79, 0x1c, 0x32, 0x99, 0x98, 0x03, 0xe5, 0x38, 0xf8, ++ 0x6d, 0x18, 0x1f, 0x19, 0xca, 0x4f, 0x93, 0xfe, 0x99, 0xf4, 0xcb, 0x86, ++ 0xf2, 0xc7, 0xa4, 0x1f, 0x96, 0x63, 0x62, 0x71, 0xf8, 0xdc, 0xa5, 0xf4, ++ 0xde, 0x8a, 0x7e, 0x7a, 0x61, 0xc3, 0x6b, 0x55, 0xc3, 0x18, 0xf9, 0x6b, ++ 0xd5, 0xa8, 0x47, 0xee, 0xc3, 0xf3, 0xd9, 0xe8, 0xa7, 0x4d, 0xe0, 0x76, ++ 0x56, 0x5b, 0xda, 0x95, 0x3a, 0xc6, 0x6d, 0xda, 0x73, 0x3b, 0xbb, 0x47, ++ 0xe2, 0x78, 0x52, 0x4d, 0x14, 0x17, 0x05, 0xbb, 0xd9, 0xb3, 0x30, 0xca, ++ 0x5e, 0x5c, 0x2f, 0xe8, 0xa9, 0x8d, 0x6c, 0xef, 0x45, 0xfd, 0xd7, 0x98, ++ 0x68, 0xd3, 0xd1, 0x5e, 0xd2, 0x6c, 0xbb, 0xa6, 0xbd, 0x07, 0xf8, 0xda, ++ 0x69, 0xee, 0x7d, 0x12, 0xe3, 0x10, 0xad, 0x8a, 0x7b, 0x5d, 0x27, 0xca, ++ 0xc5, 0x3b, 0x1c, 0x94, 0xef, 0xf1, 0xa0, 0xc0, 0x9b, 0xee, 0x34, 0x15, ++ 0x6f, 0x82, 0x76, 0x3b, 0x9b, 0x7d, 0x1a, 0x9e, 0xc3, 0xef, 0xbc, 0x9b, ++ 0x79, 0x5a, 0x71, 0x7d, 0xa4, 0x54, 0x6e, 0x4a, 0x84, 0xf7, 0xa3, 0xb3, ++ 0x56, 0x98, 0x30, 0xdc, 0x33, 0x26, 0xaf, 0x79, 0x13, 0x3e, 0x03, 0xc2, ++ 0x5e, 0x1e, 0x5b, 0xb8, 0xcb, 0x94, 0x0c, 0xe5, 0xe3, 0x4a, 0x2a, 0x17, ++ 0x63, 0x7c, 0x4b, 0x75, 0x43, 0x7f, 0x17, 0x89, 0x37, 0xab, 0xae, 0x0e, ++ 0x86, 0xf3, 0x61, 0x79, 0xda, 0x49, 0xe4, 0x2b, 0xb4, 0xee, 0x2f, 0xc0, ++ 0xd0, 0x2b, 0x93, 0x6c, 0xb4, 0xff, 0x68, 0x47, 0x7a, 0x2b, 0xf4, 0x24, ++ 0x3c, 0xd8, 0xcf, 0x39, 0x42, 0x76, 0x84, 0xf3, 0x38, 0x5e, 0xec, 0x3e, ++ 0x25, 0x14, 0xaf, 0x70, 0xbb, 0x15, 0xf3, 0xe5, 0x2a, 0x93, 0x3a, 0x88, ++ 0xbe, 0xd2, 0x9e, 0x45, 0x3b, 0x17, 0xdb, 0xf7, 0x57, 0x04, 0xd6, 0x23, ++ 0x1f, 0xa5, 0xcc, 0x35, 0xd2, 0x55, 0xb3, 0x3d, 0x46, 0xf8, 0xd8, 0x6a, ++ 0xe2, 0xeb, 0xa2, 0x3d, 0x51, 0x7f, 0x19, 0xf5, 0x73, 0x7b, 0x6e, 0x5e, ++ 0x12, 0xee, 0x5b, 0xf5, 0xcb, 0x11, 0x21, 0x57, 0xee, 0x10, 0xfa, 0x53, ++ 0xbe, 0x97, 0x72, 0xe5, 0x23, 0xf4, 0x1d, 0x52, 0x23, 0xf6, 0x0d, 0xf0, ++ 0x79, 0x07, 0xc6, 0xd9, 0xec, 0xda, 0x36, 0x3a, 0x7f, 0x69, 0xbf, 0x6b, ++ 0x1b, 0x43, 0xbe, 0xb6, 0xe3, 0x69, 0x75, 0xb2, 0xf7, 0x83, 0xba, 0x9f, ++ 0xf4, 0x87, 0xdf, 0x90, 0x6f, 0x56, 0x3d, 0x72, 0xb1, 0x0d, 0xf5, 0xf5, ++ 0xd9, 0x14, 0x2f, 0xd9, 0xb3, 0xf6, 0x8d, 0xbf, 0xa4, 0xf1, 0xc5, 0xe2, ++ 0xcd, 0xde, 0xcb, 0xf3, 0xce, 0x86, 0xc2, 0xab, 0x2b, 0xff, 0x61, 0xd2, ++ 0xef, 0x20, 0x80, 0x75, 0x3c, 0xb7, 0x73, 0x34, 0xcd, 0x51, 0x1b, 0x1d, ++ 0xdf, 0x94, 0xcf, 0x64, 0x21, 0xf7, 0xcd, 0x32, 0x3f, 0x08, 0x3c, 0x09, ++ 0xd4, 0x67, 0x67, 0x65, 0xfe, 0x91, 0x2f, 0x9e, 0x8f, 0x2f, 0x91, 0xc3, ++ 0xc7, 0xf2, 0x97, 0xd2, 0xf8, 0x6e, 0x4d, 0xf5, 0x0e, 0xbb, 0x98, 0xbd, ++ 0x6d, 0x07, 0x7f, 0x33, 0x10, 0x45, 0xf7, 0xbb, 0x35, 0xbf, 0x0d, 0xf1, ++ 0xd0, 0x76, 0x7e, 0xc1, 0x1c, 0x9a, 0xb7, 0x46, 0x8b, 0x81, 0x6d, 0xfd, ++ 0xa2, 0x70, 0x17, 0xc5, 0x8d, 0x85, 0xbf, 0x94, 0x2c, 0xf0, 0xab, 0x23, ++ 0x3e, 0x01, 0x8f, 0x39, 0x16, 0x7e, 0x5e, 0xc0, 0x93, 0x32, 0x97, 0xee, ++ 0x2d, 0x93, 0x71, 0x8f, 0xe7, 0xa7, 0x24, 0x51, 0xb9, 0x27, 0xc8, 0x54, ++ 0x1e, 0xaf, 0xeb, 0xcf, 0x4f, 0x37, 0x5d, 0x98, 0x48, 0x63, 0xd5, 0x2d, ++ 0x52, 0xef, 0x92, 0x29, 0xcb, 0xf5, 0x14, 0xfc, 0x7f, 0x04, 0xf3, 0x52, ++ 0x46, 0xb5, 0x6b, 0xc6, 0x7c, 0x76, 0xa1, 0xc7, 0xa5, 0x9e, 0x1e, 0xbd, ++ 0xcd, 0x58, 0x3e, 0xa6, 0xc3, 0x08, 0x8f, 0x0d, 0x0d, 0xf8, 0xfe, 0xdf, ++ 0x51, 0xcf, 0x5f, 0xc3, 0x7f, 0x07, 0x3d, 0x60, 0x2c, 0x7f, 0x58, 0xe8, ++ 0xeb, 0x6b, 0x50, 0x5f, 0xe3, 0xbe, 0xd5, 0xb7, 0x78, 0x5e, 0x88, 0x0d, ++ 0x46, 0x74, 0x81, 0xeb, 0xd9, 0x88, 0xde, 0x03, 0x39, 0x90, 0xdd, 0x19, ++ 0xae, 0x44, 0xb1, 0x99, 0x75, 0x9b, 0x66, 0xc8, 0x27, 0x19, 0x1e, 0xa3, ++ 0x0f, 0xfd, 0x15, 0x3a, 0xe1, 0xcb, 0xdf, 0xad, 0x99, 0x51, 0xcf, 0xca, ++ 0xb8, 0x4c, 0xac, 0x1c, 0x56, 0xee, 0x3c, 0xbd, 0x01, 0xd7, 0x4b, 0x65, ++ 0x7c, 0xbc, 0x8e, 0xf2, 0x13, 0xe3, 0x18, 0x01, 0x2b, 0xf7, 0xcb, 0x03, ++ 0xe0, 0xa7, 0xdc, 0xa7, 0x79, 0xfe, 0x54, 0x83, 0x7e, 0x55, 0xb7, 0x4a, ++ 0xf9, 0x52, 0x92, 0x4e, 0xb1, 0x74, 0x9d, 0x5a, 0x2e, 0xed, 0x5c, 0xff, ++ 0x1f, 0xa7, 0x90, 0x7f, 0xdc, 0x5b, 0x8c, 0xfe, 0x3a, 0xf6, 0x17, 0x88, ++ 0xea, 0x4f, 0xc6, 0x57, 0x0e, 0x4d, 0x0f, 0xbc, 0x89, 0xf5, 0x64, 0x9c, ++ 0xe5, 0xcc, 0x1c, 0xed, 0x79, 0x45, 0x8f, 0xc4, 0x51, 0x64, 0x5c, 0xc0, ++ 0x3b, 0x85, 0xaf, 0x9f, 0xad, 0x9e, 0xd7, 0x1b, 0x8e, 0xc1, 0x38, 0x8e, ++ 0x9d, 0xb0, 0x52, 0x0c, 0x64, 0x96, 0xfa, 0x72, 0x77, 0x13, 0xe6, 0x43, ++ 0x65, 0x6b, 0x24, 0xbf, 0xdc, 0x93, 0xd7, 0xfd, 0x14, 0xfd, 0xef, 0xaa, ++ 0x3f, 0x43, 0x39, 0xcc, 0xe3, 0x98, 0xae, 0x0f, 0x23, 0xbb, 0xbc, 0xdb, ++ 0x4c, 0x71, 0x80, 0x2a, 0xc1, 0xc7, 0x55, 0xc2, 0xdf, 0x92, 0xf1, 0x96, ++ 0xcf, 0x84, 0x3e, 0xe9, 0x9b, 0x22, 0xed, 0x9c, 0x60, 0x1c, 0xf7, 0xeb, ++ 0xc3, 0x71, 0x68, 0xbf, 0x8e, 0xdb, 0x03, 0xb2, 0xd7, 0x48, 0xcf, 0x78, ++ 0x5e, 0xce, 0xe3, 0x6a, 0xe3, 0x3b, 0x63, 0xcb, 0x7d, 0x94, 0xa7, 0x74, ++ 0x99, 0xe0, 0x17, 0xcc, 0x2f, 0xab, 0x4c, 0xc3, 0xb4, 0x2e, 0x0e, 0x77, ++ 0x32, 0x25, 0xd9, 0x0d, 0x74, 0x9c, 0xb8, 0xb8, 0xf7, 0x28, 0xba, 0x0e, ++ 0x85, 0x2f, 0x3e, 0x1f, 0x87, 0x7c, 0xb8, 0xcf, 0xce, 0xed, 0xb5, 0xa7, ++ 0x04, 0x3f, 0xa4, 0x31, 0xc5, 0x83, 0x79, 0xf8, 0x69, 0x7b, 0x1c, 0x9e, ++ 0x10, 0xd4, 0x73, 0xaa, 0x6c, 0x5f, 0x0f, 0xcc, 0xc3, 0x73, 0x5c, 0x33, ++ 0xe4, 0x93, 0x4d, 0x38, 0x68, 0x84, 0x0b, 0x59, 0x14, 0x9c, 0x8b, 0xe3, ++ 0x30, 0xc2, 0xf7, 0xea, 0x0d, 0xb8, 0xc5, 0xcc, 0xee, 0xad, 0x01, 0x9b, ++ 0x1c, 0xa6, 0xec, 0x28, 0x17, 0x79, 0x47, 0xf9, 0x2c, 0x1f, 0xf9, 0x6b, ++ 0x96, 0xea, 0x28, 0x42, 0xff, 0xa9, 0xb1, 0xd2, 0xc1, 0x10, 0xaf, 0xd6, ++ 0xb7, 0xc7, 0xfc, 0xb8, 0x07, 0xe5, 0xc5, 0x6b, 0xfc, 0x7e, 0x2a, 0x77, ++ 0xbc, 0xfe, 0x40, 0x35, 0x7c, 0xef, 0x7e, 0x29, 0xd9, 0xd3, 0xac, 0x47, ++ 0xe8, 0xff, 0x14, 0xf8, 0xd1, 0xa8, 0x1f, 0x7e, 0x74, 0xc1, 0xc3, 0x5a, ++ 0xcd, 0x51, 0x71, 0x2d, 0xa0, 0x67, 0x1e, 0xed, 0x23, 0xbb, 0xa9, 0xbc, ++ 0x13, 0xe8, 0x8a, 0xf0, 0x7e, 0xf0, 0xab, 0xf3, 0x68, 0x1f, 0xb9, 0x80, ++ 0xde, 0xff, 0x12, 0xfc, 0x6a, 0x84, 0xbb, 0xc0, 0xaf, 0xc6, 0xe7, 0x6f, ++ 0xc0, 0xaf, 0xc6, 0xf7, 0x07, 0xc1, 0xaf, 0x46, 0xd8, 0x37, 0xbd, 0x72, ++ 0x2c, 0xc6, 0xc3, 0xde, 0x84, 0x7a, 0xc8, 0x17, 0x71, 0x45, 0x07, 0x6c, ++ 0xa3, 0x30, 0x9e, 0xed, 0x50, 0xe9, 0x7c, 0x4d, 0x2c, 0x3f, 0x6e, 0x69, ++ 0x78, 0xd7, 0x71, 0x1d, 0xc8, 0xaa, 0xa9, 0x1d, 0xd9, 0x73, 0x53, 0x91, ++ 0x1f, 0x6e, 0x53, 0xe9, 0x1c, 0xf2, 0xd8, 0xdf, 0x64, 0xcf, 0x45, 0xbf, ++ 0x35, 0x3a, 0xae, 0x16, 0x1d, 0x57, 0x8c, 0xc4, 0xd5, 0x7a, 0x15, 0x19, ++ 0x57, 0xb3, 0x02, 0x7d, 0x5e, 0x98, 0xac, 0xf3, 0xbc, 0x45, 0x19, 0x5f, ++ 0x0b, 0xf0, 0xf8, 0xda, 0x57, 0xb7, 0xe3, 0x93, 0xed, 0x50, 0xbc, 0x72, ++ 0x40, 0x3b, 0xfd, 0x71, 0x4b, 0x5b, 0xf0, 0xbd, 0x02, 0x3c, 0x9a, 0xa5, ++ 0xb0, 0x04, 0x78, 0xff, 0xf1, 0x1d, 0xff, 0xf9, 0x04, 0xea, 0x99, 0xd4, ++ 0x8c, 0xc0, 0x54, 0x9c, 0x77, 0xdd, 0xa4, 0x77, 0x2c, 0xdc, 0xee, 0xe6, ++ 0xe7, 0xa6, 0xb2, 0xc4, 0x3a, 0xda, 0x61, 0xe7, 0x79, 0xa3, 0x59, 0x22, ++ 0xdf, 0x27, 0x36, 0x5e, 0x39, 0x7d, 0xe6, 0xdb, 0xb7, 0xa6, 0x02, 0xca, ++ 0xe6, 0x97, 0x8f, 0x59, 0x86, 0xfe, 0xff, 0xf4, 0x5b, 0xde, 0x2e, 0xce, ++ 0x01, 0xf8, 0x87, 0xe5, 0x3f, 0x58, 0x86, 0x79, 0xbd, 0xd3, 0x7f, 0xf6, ++ 0xf6, 0x33, 0x99, 0x80, 0xa7, 0x7f, 0xfe, 0x66, 0x11, 0x2f, 0x7f, 0xf0, ++ 0xed, 0xb3, 0x59, 0x1e, 0xcc, 0xbb, 0xf8, 0xde, 0x32, 0xcc, 0xf3, 0x75, ++ 0x25, 0x73, 0xfd, 0xb6, 0x43, 0x9c, 0x3f, 0x92, 0xf8, 0xbd, 0x5e, 0xac, ++ 0xf7, 0xfa, 0x8d, 0x8f, 0x92, 0x1e, 0x07, 0x3b, 0x83, 0x21, 0x3e, 0x5a, ++ 0xd2, 0xfc, 0xa4, 0x5f, 0x3f, 0x49, 0xe9, 0x73, 0xad, 0x80, 0xfa, 0xf5, ++ 0xa9, 0x7d, 0x69, 0x2b, 0x2f, 0xa2, 0x0f, 0xea, 0x37, 0x3e, 0x41, 0xdf, ++ 0xef, 0x50, 0x3c, 0xa7, 0x42, 0x38, 0xee, 0x29, 0x36, 0x9e, 0x5f, 0x2a, ++ 0xf4, 0xcd, 0x19, 0xc1, 0xbb, 0x52, 0xdf, 0x34, 0xda, 0x39, 0x28, 0xc7, ++ 0xc3, 0x58, 0x3a, 0xbd, 0x7f, 0x50, 0xc4, 0x81, 0x98, 0x2f, 0x93, 0xbe, ++ 0x4b, 0xb6, 0x73, 0xf8, 0x98, 0xab, 0x9c, 0xf4, 0xd2, 0xfd, 0x55, 0xfa, ++ 0xab, 0x3a, 0xdf, 0x9f, 0x24, 0xff, 0xf8, 0x98, 0xeb, 0xb2, 0xef, 0x63, ++ 0xfe, 0x5c, 0xcb, 0x1c, 0x8d, 0xf6, 0x0d, 0x1f, 0x74, 0x78, 0xed, 0xa8, ++ 0xb7, 0x36, 0x8b, 0x79, 0x41, 0xfb, 0x41, 0xca, 0x53, 0x99, 0x65, 0xa3, ++ 0xfd, 0x1c, 0x96, 0xb2, 0x98, 0xd6, 0x75, 0x92, 0xec, 0x27, 0xa5, 0x86, ++ 0xf2, 0x0e, 0x92, 0xc4, 0x78, 0x8e, 0x97, 0xc7, 0x85, 0x31, 0x3e, 0xd0, ++ 0x52, 0x6d, 0xdb, 0x8d, 0x72, 0xf4, 0x07, 0x8e, 0x91, 0xd4, 0x5e, 0x4b, ++ 0x99, 0x25, 0x88, 0x71, 0x19, 0x09, 0x6f, 0x2a, 0x87, 0xf1, 0x00, 0x3e, ++ 0x13, 0x5d, 0x49, 0xb9, 0xd4, 0x9f, 0x90, 0x73, 0x32, 0x6e, 0xcc, 0x70, ++ 0xf7, 0x0c, 0xda, 0xad, 0x12, 0xd3, 0xae, 0x92, 0xf9, 0x0c, 0x36, 0xf3, ++ 0xe9, 0x68, 0xfb, 0xda, 0xc1, 0x7a, 0x88, 0x7f, 0x3c, 0x26, 0x5d, 0x45, ++ 0xfb, 0x30, 0x79, 0xaa, 0x4e, 0xf2, 0xab, 0x98, 0x79, 0x16, 0xe3, 0x7b, ++ 0x8b, 0xd2, 0x10, 0x44, 0x66, 0xc4, 0x79, 0x98, 0xa2, 0xe7, 0xa1, 0x57, ++ 0x1b, 0xe7, 0xa1, 0xcf, 0x32, 0xcc, 0x43, 0x69, 0xb4, 0x85, 0xd1, 0x2e, ++ 0x6c, 0x99, 0x05, 0xf3, 0x80, 0xfa, 0xc7, 0x9d, 0xa5, 0x34, 0xde, 0x58, ++ 0xba, 0xc9, 0xf9, 0x7c, 0xb7, 0x9c, 0xf3, 0x73, 0xec, 0x3c, 0x99, 0xd8, ++ 0x37, 0x92, 0xe7, 0x04, 0xaa, 0xdc, 0x15, 0x07, 0x70, 0x5c, 0xb3, 0x4c, ++ 0xbe, 0x56, 0x1c, 0xd7, 0xf3, 0xff, 0xa8, 0x49, 0xc1, 0x0b, 0x23, 0x67, ++ 0xb3, 0x06, 0x0d, 0xdf, 0x8f, 0x8a, 0xe4, 0xed, 0xb4, 0x7e, 0x9d, 0xbc, ++ 0x88, 0xe9, 0xef, 0x2a, 0x7c, 0x9f, 0xeb, 0x16, 0x0b, 0xcd, 0x6f, 0xe7, ++ 0x34, 0x8e, 0x87, 0x87, 0x2d, 0xa1, 0x5c, 0x3a, 0xc0, 0xa1, 0x85, 0x32, ++ 0x70, 0x7f, 0x77, 0x28, 0x3e, 0xee, 0x2a, 0xe7, 0x72, 0x3f, 0xc2, 0xc7, ++ 0x3e, 0x86, 0xeb, 0xab, 0x25, 0xc9, 0xc7, 0xf9, 0xd8, 0xdd, 0xe7, 0x6a, ++ 0x46, 0x3e, 0x4e, 0xec, 0x4b, 0xdb, 0x44, 0xf3, 0x0a, 0x0f, 0x4a, 0x9f, ++ 0x58, 0x7e, 0x8e, 0xa5, 0xd7, 0x31, 0xbc, 0x13, 0x81, 0xf4, 0x62, 0x50, ++ 0x45, 0xfc, 0x7f, 0x15, 0x7d, 0x25, 0x5d, 0x63, 0xf7, 0xbd, 0x24, 0xbf, ++ 0x24, 0x4f, 0x75, 0x4b, 0x7a, 0xa7, 0xd3, 0x3c, 0xc3, 0x39, 0x86, 0xfd, ++ 0x40, 0x68, 0x41, 0x1f, 0x6c, 0x1f, 0x7c, 0x33, 0xb4, 0xa7, 0x47, 0xed, ++ 0x9f, 0x59, 0xd2, 0xfd, 0x64, 0x67, 0x9b, 0x53, 0x3c, 0x05, 0x18, 0x6f, ++ 0x6e, 0xf9, 0x52, 0x1d, 0xf4, 0x7c, 0xe4, 0x59, 0x81, 0xa7, 0x66, 0x57, ++ 0x1c, 0xd9, 0xdf, 0x2d, 0x2e, 0x6e, 0x7f, 0x1f, 0x71, 0x5d, 0x69, 0xf0, ++ 0x9b, 0xaa, 0xc1, 0x8f, 0xc2, 0xfd, 0x62, 0x35, 0x99, 0x75, 0xe2, 0xba, ++ 0x52, 0x13, 0x96, 0x52, 0x1c, 0x4d, 0x1d, 0x86, 0x96, 0x17, 0xb1, 0x85, ++ 0xd1, 0xae, 0x4d, 0x98, 0xcb, 0xed, 0x5a, 0xb7, 0xf7, 0xa2, 0xe7, 0xa4, ++ 0xb4, 0x5e, 0xd5, 0x70, 0x7f, 0xda, 0x00, 0xbb, 0x36, 0xe9, 0x4a, 0x6e, ++ 0xd7, 0xba, 0x2c, 0x64, 0xd7, 0xee, 0x70, 0x5a, 0x16, 0xef, 0x1a, 0x44, ++ 0xee, 0xbc, 0x54, 0xce, 0xfd, 0x9f, 0x23, 0x38, 0x8f, 0x41, 0xfc, 0x46, ++ 0xf0, 0x17, 0x29, 0x9e, 0x29, 0xfd, 0x45, 0x8b, 0x3b, 0x40, 0x7e, 0x9f, ++ 0x9c, 0xe7, 0x4b, 0x82, 0xdf, 0x65, 0x7d, 0xab, 0xbb, 0x81, 0x61, 0x7c, ++ 0x4d, 0xb5, 0x78, 0x74, 0xb4, 0x63, 0x55, 0x71, 0x8e, 0x15, 0xf3, 0x97, ++ 0x0b, 0xa2, 0xec, 0x02, 0xd9, 0xff, 0x0b, 0xe5, 0xfc, 0x1c, 0xfe, 0x33, ++ 0xd3, 0x39, 0xfd, 0x64, 0x1e, 0xfb, 0xf4, 0x57, 0x95, 0x86, 0xc1, 0xf0, ++ 0xae, 0x4d, 0x95, 0x76, 0xc9, 0xe0, 0x7c, 0xf7, 0x2f, 0xf0, 0x0d, 0xc9, ++ 0x09, 0xaf, 0xc3, 0xe2, 0x43, 0xbb, 0xc3, 0xeb, 0x48, 0xa7, 0x7c, 0xef, ++ 0xa1, 0xbe, 0xc3, 0xad, 0xea, 0x53, 0x49, 0x11, 0x39, 0xe3, 0xf9, 0xb2, ++ 0x54, 0x25, 0x7d, 0xa4, 0x79, 0x28, 0x7f, 0xbf, 0xd3, 0xdc, 0xfb, 0xcc, ++ 0xab, 0xe8, 0x0f, 0x3e, 0xef, 0x20, 0xbd, 0x23, 0xed, 0x71, 0x30, 0x56, ++ 0x29, 0xff, 0x18, 0xfc, 0x5e, 0x9f, 0x07, 0x1a, 0xd9, 0xf7, 0x4f, 0x58, ++ 0x89, 0xa6, 0x88, 0xbf, 0x0b, 0xfe, 0x57, 0xf6, 0xd4, 0xa8, 0xfd, 0xc7, ++ 0xa3, 0x8d, 0x27, 0x69, 0xff, 0x27, 0xd6, 0x4e, 0x8d, 0x8d, 0x27, 0xf4, ++ 0xaf, 0x73, 0xd7, 0x13, 0xb9, 0x7c, 0x1c, 0xa1, 0x0c, 0x5c, 0xb7, 0x4a, ++ 0x63, 0xd9, 0x30, 0xe4, 0xa7, 0xd8, 0x75, 0x2e, 0x9f, 0xd9, 0xe9, 0xc5, ++ 0x97, 0xad, 0x82, 0x71, 0x65, 0x67, 0x14, 0xd1, 0x53, 0xbe, 0x7f, 0x84, ++ 0xa9, 0x73, 0x06, 0xbb, 0x1f, 0xad, 0xa4, 0x1f, 0xff, 0x5c, 0x3f, 0x8f, ++ 0x85, 0xce, 0x12, 0x54, 0xd2, 0xcb, 0x25, 0x53, 0x81, 0x8e, 0x1f, 0xdf, ++ 0xf6, 0x7a, 0x9a, 0x47, 0xc7, 0x73, 0xb4, 0x9f, 0x92, 0x7e, 0x3e, 0xd3, ++ 0x50, 0x96, 0xb0, 0x05, 0xf9, 0xbc, 0x20, 0x89, 0xe4, 0x6a, 0x96, 0x38, ++ 0x1f, 0x26, 0xc7, 0x93, 0x75, 0xf3, 0x91, 0xc4, 0x24, 0x07, 0xe6, 0xe9, ++ 0xf5, 0x8d, 0xc5, 0xfc, 0xb6, 0x50, 0x93, 0xff, 0xb2, 0x6a, 0x33, 0xf9, ++ 0x17, 0xbe, 0xc1, 0xc6, 0x1b, 0x98, 0xca, 0xf5, 0x11, 0x0b, 0x8f, 0x60, ++ 0xd1, 0xf7, 0xff, 0xe8, 0x29, 0x3d, 0x57, 0x8c, 0x01, 0x7c, 0xeb, 0x0e, ++ 0x93, 0x47, 0xa7, 0x75, 0xe5, 0x26, 0xbd, 0x27, 0xd7, 0x7f, 0xa5, 0x96, ++ 0x58, 0xed, 0x06, 0xfe, 0xce, 0x6e, 0x62, 0x1e, 0x87, 0x8e, 0x57, 0x23, ++ 0xbb, 0x29, 0x1e, 0x96, 0x7d, 0x41, 0x25, 0x3e, 0xcb, 0x3e, 0xc6, 0xef, ++ 0x6f, 0x1e, 0x91, 0xd2, 0xa7, 0xe0, 0xbd, 0x5b, 0xfd, 0xfd, 0x88, 0x3c, ++ 0x26, 0xb9, 0xaf, 0xf2, 0x59, 0x43, 0x35, 0xad, 0xcb, 0xec, 0x61, 0x8c, ++ 0xf5, 0x50, 0xdc, 0xd2, 0x4f, 0xfb, 0x0f, 0x9f, 0xa5, 0x84, 0x17, 0xe0, ++ 0xba, 0xfe, 0xec, 0x21, 0x3e, 0xa2, 0xec, 0x47, 0x8d, 0xe5, 0xa0, 0x6b, ++ 0x29, 0x5e, 0xbd, 0xfa, 0xb6, 0xb8, 0x90, 0x0e, 0x4d, 0x8f, 0xb8, 0x0b, ++ 0xc6, 0x87, 0xe3, 0xf9, 0xa9, 0xc2, 0xb2, 0x72, 0x71, 0x1c, 0xc7, 0x72, ++ 0xb7, 0x60, 0xbc, 0xe7, 0x57, 0xf1, 0x14, 0xef, 0x51, 0x3b, 0xf2, 0x28, ++ 0x5e, 0xb3, 0x26, 0x23, 0x30, 0x07, 0xf9, 0xe1, 0xe3, 0x90, 0xfe, 0x6d, ++ 0xd3, 0x28, 0x31, 0x59, 0xa8, 0x57, 0xf7, 0x9d, 0x38, 0xba, 0x2f, 0x60, ++ 0x87, 0xd2, 0x73, 0x05, 0xe5, 0x4b, 0xdc, 0x6e, 0x62, 0x8f, 0x0f, 0x12, ++ 0x8f, 0x5a, 0x33, 0x95, 0xfb, 0x89, 0xb5, 0x82, 0xcf, 0xb3, 0xd3, 0x4b, ++ 0x39, 0xbd, 0xd3, 0x4b, 0x2e, 0x5b, 0x95, 0x7c, 0xe9, 0xeb, 0xe8, 0x87, ++ 0x42, 0x5e, 0x6f, 0x4d, 0x08, 0xd1, 0xfe, 0x9c, 0xcc, 0xfb, 0xba, 0xd7, ++ 0x3c, 0x38, 0x5f, 0xbd, 0x3e, 0xd5, 0x24, 0xe8, 0x94, 0x63, 0xc8, 0x03, ++ 0xb3, 0xa1, 0xf7, 0x03, 0xfc, 0xa2, 0x2a, 0xc2, 0xde, 0xdb, 0xf3, 0xd4, ++ 0x53, 0x4f, 0xa5, 0x31, 0x7e, 0x84, 0x70, 0x24, 0xdf, 0x87, 0x8c, 0xde, ++ 0x2f, 0x8e, 0xcb, 0x0b, 0x51, 0x61, 0x9c, 0xc7, 0x47, 0x72, 0x47, 0x71, ++ 0xfb, 0xb8, 0x7c, 0x75, 0x37, 0xa4, 0x07, 0x81, 0xbf, 0xb7, 0x7c, 0xa1, ++ 0x0e, 0xda, 0xff, 0xa3, 0x82, 0x7e, 0xcd, 0xd9, 0xdf, 0x4e, 0xc7, 0xfa, ++ 0xd5, 0xba, 0x87, 0x9e, 0x47, 0xb2, 0x4b, 0x4f, 0xac, 0x00, 0xfc, 0x39, ++ 0x1c, 0x16, 0x66, 0x8d, 0x92, 0xbf, 0x92, 0x4f, 0x62, 0xf5, 0x7b, 0xa3, ++ 0x73, 0xe4, 0x45, 0xfd, 0x77, 0x0b, 0xc8, 0x61, 0xfd, 0x22, 0xf1, 0x05, ++ 0x8b, 0xc8, 0xef, 0xda, 0x7c, 0x74, 0x8a, 0x0d, 0xef, 0x07, 0xdd, 0xec, ++ 0xf0, 0xf6, 0xa0, 0xdd, 0xb5, 0xd9, 0x91, 0xe2, 0xa5, 0xf8, 0xbb, 0x03, ++ 0xe4, 0x45, 0x54, 0x3c, 0xca, 0xe1, 0x78, 0x81, 0xf8, 0xd0, 0xe1, 0xe1, ++ 0x71, 0x3a, 0x07, 0xca, 0x5d, 0x8c, 0x47, 0xe1, 0xfc, 0x0b, 0x71, 0xfc, ++ 0x2f, 0xd0, 0xfc, 0x65, 0xbd, 0x26, 0x21, 0x7f, 0x1c, 0x9e, 0x30, 0xed, ++ 0x93, 0xda, 0x3d, 0xdb, 0xa8, 0x9e, 0x4d, 0xf3, 0xd3, 0xf9, 0x38, 0x5b, ++ 0x0a, 0xa3, 0xbc, 0x05, 0x9b, 0x9b, 0xdf, 0x2b, 0x1a, 0x97, 0x67, 0x62, ++ 0xb6, 0x41, 0xe4, 0xf0, 0xc6, 0xa9, 0xdc, 0xff, 0xdb, 0x5c, 0xe8, 0xed, ++ 0xa9, 0xa2, 0xf1, 0x69, 0x78, 0x6c, 0x8a, 0x6d, 0x4e, 0xf7, 0xa6, 0x93, ++ 0x1e, 0x44, 0x3c, 0xc3, 0xf7, 0xc7, 0x9c, 0xa5, 0x09, 0xd1, 0xf8, 0x79, ++ 0x56, 0xc8, 0x83, 0x96, 0x23, 0x7c, 0x7e, 0xfe, 0x8d, 0x19, 0xee, 0xea, ++ 0x62, 0xf4, 0x67, 0xfd, 0x7b, 0x51, 0x1e, 0x6c, 0x76, 0xac, 0xb4, 0xe1, ++ 0x7d, 0x5d, 0xaa, 0xb3, 0xe4, 0xa2, 0xed, 0x1c, 0x12, 0xf4, 0x8a, 0xb4, ++ 0xb3, 0x3d, 0xad, 0x3a, 0x99, 0xda, 0x79, 0x16, 0xf9, 0x5f, 0x75, 0x7a, ++ 0xdd, 0xd8, 0x8e, 0x59, 0xdc, 0x8f, 0x3a, 0x40, 0x8f, 0x89, 0x71, 0x7c, ++ 0xd3, 0x38, 0x1a, 0x60, 0x90, 0xf2, 0x74, 0x08, 0x2f, 0x44, 0x98, 0xb0, ++ 0x81, 0x2e, 0xb1, 0x4f, 0x07, 0xc6, 0xc3, 0x92, 0x07, 0xfb, 0x8e, 0xcb, ++ 0xc5, 0x5c, 0xe1, 0xb7, 0x80, 0x5c, 0xfc, 0x13, 0x8e, 0xbf, 0xae, 0xf0, ++ 0x9d, 0x17, 0xf8, 0x1a, 0xe3, 0xfe, 0x4a, 0xd2, 0x15, 0x3c, 0x0f, 0xe8, ++ 0x0c, 0x70, 0x36, 0xde, 0x4b, 0x15, 0x9b, 0x67, 0x11, 0x6b, 0xbf, 0x48, ++ 0xbd, 0x23, 0xf5, 0x10, 0xb4, 0xa3, 0x62, 0x3b, 0x0f, 0xa3, 0xfd, 0x32, ++ 0x26, 0xb2, 0x8e, 0x64, 0x1c, 0x27, 0xb3, 0xd6, 0xcf, 0xd7, 0x4b, 0x8a, ++ 0x9f, 0xf8, 0x05, 0xec, 0x19, 0x1d, 0xd7, 0x8b, 0x2a, 0xf2, 0xf8, 0x06, ++ 0xe8, 0x81, 0x0a, 0x8e, 0x3f, 0xc5, 0x55, 0xa6, 0xa3, 0xbe, 0xa8, 0x3e, ++ 0xdf, 0x9b, 0x89, 0xdf, 0x1d, 0x72, 0x9e, 0xca, 0xe4, 0xf6, 0xab, 0x71, ++ 0x7f, 0xf9, 0xf8, 0x3f, 0x9e, 0xb0, 0x63, 0xf9, 0x67, 0xb5, 0x55, 0x17, ++ 0xb5, 0x53, 0xe4, 0x7e, 0xf2, 0x50, 0xfb, 0xc8, 0xae, 0xef, 0x7e, 0xb8, ++ 0x21, 0xda, 0x4e, 0x19, 0x6a, 0x5f, 0xf9, 0xab, 0xf6, 0x93, 0x8f, 0xba, ++ 0x2c, 0x14, 0xb7, 0xdb, 0xa9, 0x18, 0xcf, 0xbf, 0x0f, 0xab, 0xe0, 0xf2, ++ 0x2f, 0x49, 0xcc, 0x6f, 0xd7, 0x94, 0x80, 0xbd, 0x22, 0x15, 0xeb, 0xf9, ++ 0x3d, 0xfc, 0x40, 0x33, 0x8f, 0xcb, 0xbc, 0x32, 0x3d, 0xe0, 0xa8, 0xc0, ++ 0x38, 0x5a, 0xbb, 0x85, 0x05, 0x91, 0xef, 0xfe, 0x51, 0x9a, 0x1e, 0x88, ++ 0x6a, 0xe7, 0x52, 0xf1, 0x2c, 0xe3, 0xef, 0xc3, 0x85, 0x1d, 0x35, 0xdc, ++ 0xf1, 0x84, 0x82, 0xeb, 0x74, 0x78, 0x6d, 0x48, 0xc1, 0xf8, 0x79, 0x66, ++ 0x6d, 0xa7, 0xe2, 0xbb, 0x48, 0xbd, 0xff, 0x12, 0xeb, 0x59, 0xd6, 0x37, ++ 0x8b, 0xf6, 0x67, 0x68, 0x7d, 0x2a, 0xea, 0xab, 0x19, 0x6e, 0xae, 0x17, ++ 0x33, 0xcf, 0x69, 0xac, 0x20, 0x4a, 0xee, 0xf4, 0x4e, 0xe5, 0x76, 0x94, ++ 0x59, 0xd8, 0xed, 0xae, 0xa3, 0x4f, 0xda, 0xb1, 0xbd, 0xa3, 0x26, 0x7f, ++ 0x7b, 0x3e, 0xea, 0x07, 0x97, 0x49, 0x7f, 0x3c, 0x6a, 0xbd, 0x9b, 0x6f, ++ 0xf6, 0xda, 0xaa, 0xa2, 0xe6, 0xd7, 0x82, 0xfb, 0x42, 0x83, 0xd0, 0xd1, ++ 0x57, 0x21, 0xf5, 0x60, 0x98, 0xf4, 0xb7, 0xd4, 0xb7, 0x66, 0xa9, 0x27, ++ 0x52, 0x34, 0x83, 0x9e, 0xa8, 0x8f, 0xe7, 0x7c, 0x2c, 0xed, 0x9d, 0xfa, ++ 0x72, 0xee, 0x07, 0xd5, 0xc7, 0x73, 0x7f, 0xfc, 0xc5, 0xf4, 0xc0, 0x14, ++ 0xc4, 0xf3, 0x27, 0xe5, 0x1f, 0xce, 0x1f, 0xa5, 0xe3, 0x39, 0xd8, 0xb0, ++ 0x39, 0x25, 0xf7, 0xab, 0xf7, 0x47, 0xfa, 0xed, 0x1b, 0x53, 0x68, 0x85, ++ 0xf4, 0x63, 0x90, 0xff, 0x3b, 0xcd, 0x7a, 0x57, 0x2f, 0xd9, 0x59, 0x2e, ++ 0x3a, 0x3f, 0x21, 0xed, 0xaa, 0xa2, 0x9f, 0x29, 0xa3, 0xb0, 0x9e, 0x47, ++ 0xf1, 0x91, 0xfd, 0x37, 0x09, 0x6f, 0x1a, 0x51, 0x71, 0xab, 0x96, 0xdb, ++ 0x83, 0x60, 0x67, 0x5d, 0x59, 0x91, 0xca, 0xaf, 0xe4, 0x8f, 0xe6, 0x03, ++ 0x16, 0x73, 0xaf, 0xe0, 0x50, 0xf3, 0xf4, 0xe2, 0x7d, 0xa6, 0xa9, 0x18, ++ 0x0f, 0xec, 0xa1, 0x78, 0xed, 0x7d, 0xe7, 0x95, 0x41, 0xcf, 0x41, 0xdc, ++ 0x57, 0x21, 0xed, 0xa5, 0xfe, 0xfd, 0x41, 0x43, 0xdc, 0x35, 0x53, 0xe8, ++ 0xbd, 0x4c, 0x51, 0xae, 0x63, 0xdc, 0x35, 0x17, 0xf7, 0xbb, 0x8c, 0x71, ++ 0xd1, 0xe2, 0x6e, 0x23, 0x3c, 0xa9, 0xc7, 0x08, 0x4f, 0x3e, 0x11, 0x13, ++ 0x67, 0x0d, 0xfa, 0xfe, 0x03, 0xcf, 0xf9, 0x61, 0x3e, 0x01, 0x36, 0xba, ++ 0x03, 0xd6, 0x1f, 0xca, 0x8f, 0x55, 0x62, 0x1f, 0x34, 0x2b, 0x18, 0xaa, ++ 0xc4, 0xf3, 0xe1, 0xd9, 0xac, 0x93, 0xf6, 0x1b, 0x33, 0x6b, 0x93, 0x0c, ++ 0xf8, 0x9e, 0xae, 0x8a, 0x3c, 0x0c, 0xbc, 0xde, 0x58, 0x8e, 0x13, 0x7e, ++ 0x32, 0xb5, 0x79, 0x1f, 0xe0, 0xf7, 0x9b, 0xfa, 0xe7, 0x15, 0x64, 0x86, ++ 0xbc, 0xfe, 0xea, 0x55, 0xdf, 0xc6, 0xab, 0x30, 0xd9, 0x36, 0x7e, 0xbe, ++ 0xcf, 0x06, 0x9d, 0x23, 0xbe, 0xd6, 0x5c, 0xb1, 0x70, 0x16, 0xd2, 0x7b, ++ 0x40, 0xfc, 0xb6, 0xc1, 0x18, 0xb7, 0xcd, 0x8c, 0x2e, 0x07, 0x3c, 0xac, ++ 0xde, 0x61, 0x3c, 0x27, 0xe8, 0xf7, 0x15, 0x91, 0x7f, 0xb0, 0xe8, 0x5b, ++ 0xc6, 0xf3, 0x82, 0x32, 0x1f, 0x1d, 0xe7, 0x9b, 0xe9, 0x1d, 0xd8, 0xff, ++ 0x57, 0xf7, 0x0b, 0xff, 0x92, 0x06, 0xf6, 0x2f, 0xdb, 0x7d, 0x18, 0xe4, ++ 0x12, 0xc9, 0x5d, 0x71, 0x8f, 0x70, 0x36, 0x16, 0x61, 0x3b, 0x5a, 0x58, ++ 0xc1, 0x7d, 0xef, 0xe1, 0x0d, 0x8c, 0xee, 0x13, 0xce, 0xbc, 0x8d, 0xf9, ++ 0x06, 0xdb, 0x3f, 0x38, 0x20, 0xf0, 0x15, 0x8b, 0x67, 0x16, 0x9c, 0x41, ++ 0xf8, 0x9b, 0x29, 0xde, 0x0d, 0x77, 0xf0, 0x3c, 0xd5, 0xe1, 0xb7, 0x99, ++ 0xc8, 0x4e, 0x1c, 0x0e, 0xf2, 0x82, 0xfe, 0xce, 0xc0, 0x3a, 0xf0, 0x35, ++ 0x00, 0xce, 0x5c, 0xa7, 0x93, 0x9d, 0x79, 0x75, 0xad, 0x89, 0xa1, 0xde, ++ 0x60, 0xe7, 0x9b, 0x0c, 0xdf, 0xc3, 0x70, 0x29, 0xbe, 0x2a, 0xe9, 0xfe, ++ 0xb0, 0x83, 0xe7, 0xe1, 0x66, 0xd7, 0xb1, 0x90, 0x09, 0xe7, 0xd3, 0x70, ++ 0x19, 0xad, 0x33, 0x1a, 0xd7, 0xc8, 0x08, 0x3f, 0x00, 0xbe, 0x0c, 0xf7, ++ 0x09, 0x5c, 0x5d, 0x66, 0x3c, 0xa7, 0x9b, 0x1d, 0x73, 0x3e, 0x57, 0xf2, ++ 0x41, 0x66, 0xcc, 0xfb, 0x6b, 0x2a, 0xdc, 0x86, 0x75, 0x01, 0xfa, 0xef, ++ 0x40, 0x05, 0xc9, 0x0f, 0xae, 0x17, 0x47, 0xa3, 0x5e, 0x84, 0x21, 0x7d, ++ 0x3c, 0xe5, 0xc4, 0x13, 0x98, 0x6f, 0x37, 0x7d, 0x13, 0xe3, 0xf7, 0xd9, ++ 0x24, 0xc6, 0xf1, 0xfb, 0x6c, 0x22, 0xfb, 0x13, 0xea, 0x05, 0xe0, 0xd7, ++ 0xa3, 0xb6, 0x99, 0x05, 0x68, 0xc7, 0x6c, 0x75, 0xc7, 0x99, 0x30, 0x0f, ++ 0xe2, 0x50, 0x62, 0xef, 0x4f, 0x58, 0x22, 0xf8, 0x8d, 0x15, 0x2c, 0x58, ++ 0x9d, 0x85, 0xf7, 0x1c, 0xf6, 0x8d, 0x53, 0x00, 0x7e, 0xbd, 0xa2, 0x7e, ++ 0x67, 0xfb, 0x34, 0x28, 0xb7, 0xf7, 0x3d, 0x8d, 0xc1, 0x65, 0x87, 0xe3, ++ 0xdb, 0x37, 0xcc, 0xc9, 0x8e, 0xc0, 0x2e, 0xd7, 0x3d, 0x04, 0xb3, 0x32, ++ 0xa6, 0xe3, 0x7d, 0x40, 0x98, 0x73, 0x8a, 0xeb, 0x2e, 0xce, 0x7d, 0xe5, ++ 0x1e, 0xbc, 0xe7, 0x3a, 0xae, 0xd0, 0x41, 0xc1, 0xca, 0x38, 0x66, 0xbc, ++ 0x77, 0xa7, 0xb5, 0x5c, 0xbf, 0x17, 0xf3, 0x48, 0x5a, 0x47, 0x9b, 0xc4, ++ 0xf9, 0xe8, 0xa8, 0x72, 0x98, 0xc7, 0x8c, 0x69, 0x6e, 0x99, 0xff, 0x46, ++ 0xf9, 0x78, 0x6c, 0x0e, 0xcf, 0x0b, 0x88, 0x6e, 0x1f, 0xf3, 0xb2, 0x87, ++ 0x6c, 0xff, 0x4a, 0x68, 0xbf, 0xe4, 0x6b, 0xb4, 0x6f, 0xe3, 0xe3, 0x4f, ++ 0xc3, 0x57, 0xa0, 0x7f, 0xd2, 0x70, 0xfc, 0x18, 0x17, 0xc7, 0xf6, 0x91, ++ 0xbe, 0x18, 0x44, 0x8a, 0xee, 0x5f, 0xb4, 0xa7, 0xb1, 0xe0, 0x2e, 0xdc, ++ 0xcf, 0x81, 0xfe, 0x1c, 0x0a, 0xef, 0xcf, 0x8d, 0x79, 0x2a, 0x69, 0xcc, ++ 0x98, 0x97, 0xd0, 0xdf, 0x9f, 0x1b, 0xfa, 0x1b, 0xff, 0xff, 0x60, 0x3e, ++ 0x8b, 0x07, 0xd2, 0xc3, 0x7c, 0x31, 0x7a, 0x2c, 0xfd, 0x7a, 0xf4, 0x68, ++ 0x35, 0xf9, 0x68, 0xbc, 0xc1, 0x09, 0x0e, 0xf2, 0x8f, 0xf0, 0xfe, 0x2a, ++ 0xbc, 0xa7, 0xce, 0x2e, 0xfa, 0xb3, 0x8b, 0xfb, 0xba, 0x10, 0xaf, 0xad, ++ 0xa5, 0x11, 0xbc, 0x82, 0x7d, 0x48, 0xed, 0x42, 0xf5, 0xe6, 0x0b, 0x02, ++ 0xcf, 0x98, 0x77, 0x98, 0xe6, 0xb6, 0x10, 0x9e, 0x87, 0xc2, 0xdb, 0x51, ++ 0x37, 0xcf, 0x93, 0xba, 0xdb, 0x1d, 0x17, 0x6a, 0xce, 0xfd, 0xff, 0x40, ++ 0xaf, 0x74, 0x4e, 0xaf, 0xe8, 0xfe, 0xd0, 0xce, 0xbc, 0xe4, 0xfe, 0x96, ++ 0x42, 0x7f, 0x29, 0x97, 0xde, 0x1f, 0xe2, 0x17, 0xd7, 0x4f, 0x3f, 0x7e, ++ 0x81, 0x26, 0x9b, 0xd2, 0x2e, 0x1d, 0xbf, 0x30, 0xaa, 0xe0, 0xa5, 0xe0, ++ 0xf7, 0x28, 0xb4, 0x6b, 0x8a, 0xc2, 0x6b, 0x24, 0x1f, 0x69, 0xbb, 0x1b, ++ 0xfd, 0x05, 0xbb, 0xd9, 0x6f, 0xc3, 0xfc, 0xcc, 0xb9, 0xd3, 0x12, 0x69, ++ 0x7c, 0x85, 0x29, 0x0b, 0x6d, 0x94, 0x9f, 0x90, 0xba, 0x90, 0xf2, 0x8d, ++ 0xdb, 0x0a, 0x1d, 0xf4, 0xf7, 0x05, 0xda, 0xf2, 0xbe, 0x65, 0x33, 0x47, ++ 0xe9, 0xe9, 0xb6, 0xc2, 0x1a, 0x2a, 0x87, 0xfa, 0x94, 0x47, 0x55, 0x18, ++ 0x8e, 0xc3, 0xf0, 0x05, 0x1b, 0xcf, 0x7a, 0x28, 0x3e, 0x70, 0x77, 0x45, ++ 0x75, 0x3a, 0xfa, 0x8b, 0xc1, 0x06, 0x9e, 0x97, 0x25, 0xf3, 0x94, 0xa4, ++ 0x3e, 0x64, 0x62, 0x3f, 0x94, 0xe6, 0x05, 0x1f, 0x26, 0x4c, 0x3b, 0xd0, ++ 0x77, 0x14, 0xea, 0xdf, 0xdd, 0x50, 0x42, 0x79, 0x68, 0x09, 0x89, 0xff, ++ 0x4d, 0xf9, 0x57, 0x5b, 0x6b, 0x3d, 0x1e, 0x2c, 0xff, 0x89, 0x9d, 0xef, ++ 0x6b, 0xfe, 0x48, 0xec, 0x6b, 0x21, 0xa3, 0x52, 0x7c, 0x6d, 0x42, 0xf9, ++ 0xa3, 0xb8, 0xbf, 0xeb, 0x1d, 0xdd, 0xa8, 0xd0, 0x7e, 0xe6, 0xba, 0x8b, ++ 0xef, 0x67, 0x7a, 0x3f, 0xed, 0xa9, 0xc2, 0x3c, 0x2e, 0xb6, 0x82, 0xe7, ++ 0x69, 0xa5, 0xd7, 0x68, 0x31, 0xfa, 0xd0, 0xb8, 0x6e, 0xb7, 0x22, 0x5e, ++ 0x79, 0x3e, 0x55, 0x48, 0xe1, 0xf8, 0x35, 0xb4, 0xb7, 0x69, 0x5a, 0x2a, ++ 0xe1, 0xed, 0xee, 0xbc, 0xdd, 0x0c, 0xff, 0xde, 0xd0, 0x33, 0xd0, 0x96, ++ 0x6a, 0x5c, 0x5f, 0x26, 0xcc, 0x6b, 0x8a, 0x5d, 0x8f, 0x9a, 0xc5, 0x47, ++ 0xf7, 0x8b, 0xb1, 0x46, 0x13, 0x8d, 0x23, 0x13, 0x53, 0x05, 0x40, 0xc5, ++ 0x79, 0xc7, 0xcf, 0x4d, 0x5f, 0x01, 0xef, 0xb3, 0x6e, 0xd2, 0xe8, 0x1e, ++ 0xdf, 0x61, 0x85, 0x77, 0x51, 0x7e, 0x13, 0x58, 0xff, 0x64, 0x6f, 0x14, ++ 0x16, 0xbe, 0x5c, 0x85, 0xf0, 0x80, 0x79, 0xae, 0x32, 0xce, 0x23, 0x76, ++ 0x5e, 0xb1, 0xe3, 0x96, 0xf7, 0x1b, 0x4b, 0x7a, 0x79, 0x3f, 0xf5, 0xc4, ++ 0xa3, 0xdf, 0xe5, 0x1d, 0xbd, 0x90, 0xf2, 0xcf, 0xe8, 0x47, 0xae, 0x77, ++ 0x35, 0x66, 0x3e, 0x60, 0x27, 0xdb, 0x53, 0x4c, 0x74, 0x0f, 0x5c, 0x5c, ++ 0x5e, 0xd4, 0xbc, 0x98, 0xa1, 0x9e, 0xf0, 0xeb, 0xfe, 0x67, 0xe1, 0x06, ++ 0xd0, 0x55, 0xb4, 0x8e, 0x62, 0xf7, 0xc9, 0xfe, 0x0f, 0x3f, 0x2f, 0x64, ++ 0x65, 0x1e, 0x9b, 0x85, 0xbe, 0x93, 0xe7, 0x6b, 0xf8, 0xfe, 0xdb, 0x70, ++ 0x5c, 0x3b, 0x48, 0xf7, 0x1c, 0xc6, 0xf3, 0xc0, 0x63, 0xbf, 0x2f, 0xe5, ++ 0xdf, 0xb3, 0x74, 0xbe, 0x1f, 0x67, 0x8d, 0x63, 0x36, 0x3c, 0x5f, 0xa3, ++ 0xac, 0x8d, 0xa3, 0xb8, 0xa6, 0xd5, 0x0a, 0x30, 0x9e, 0xbf, 0x11, 0xf7, ++ 0x8c, 0x3d, 0x2c, 0xe2, 0x70, 0xcd, 0x0a, 0xd3, 0x32, 0xbc, 0xd1, 0xfd, ++ 0x85, 0x29, 0x8f, 0x5e, 0xb5, 0x5d, 0x95, 0x87, 0xfe, 0xc4, 0x51, 0xdb, ++ 0x22, 0x37, 0x9d, 0x6b, 0x13, 0xfe, 0x95, 0x39, 0xd1, 0x4f, 0x79, 0x8c, ++ 0xac, 0x20, 0xc9, 0xe0, 0xa7, 0x1e, 0x15, 0xe7, 0xd3, 0x1a, 0x6f, 0xce, ++ 0x1d, 0x86, 0x71, 0xbd, 0x04, 0x28, 0xeb, 0x41, 0x7f, 0x5b, 0xf3, 0xd8, ++ 0x90, 0xde, 0x32, 0x9e, 0xe2, 0x1a, 0xd5, 0x7b, 0x3d, 0xea, 0xf1, 0xdf, ++ 0x3e, 0xf7, 0xc9, 0x0d, 0x36, 0xd4, 0xdb, 0xe8, 0x1c, 0x97, 0x33, 0xd6, ++ 0x3d, 0xed, 0xc3, 0x9d, 0x78, 0xbf, 0xb0, 0x5c, 0x9f, 0xd6, 0x73, 0xfc, ++ 0x9e, 0x8e, 0x7e, 0x58, 0x6b, 0xa0, 0x3c, 0x11, 0xeb, 0xb9, 0x1c, 0xc3, ++ 0xfb, 0xb0, 0xf0, 0xcf, 0xfa, 0xfd, 0x96, 0x14, 0xad, 0x9a, 0xee, 0x9f, ++ 0x12, 0x7e, 0x43, 0x25, 0x73, 0xb7, 0xe2, 0x77, 0x95, 0x80, 0x1c, 0xc3, ++ 0xbd, 0x00, 0xe2, 0xde, 0x8f, 0x81, 0xed, 0x67, 0x19, 0xde, 0x87, 0xc1, ++ 0xef, 0x8e, 0xde, 0x27, 0x18, 0xba, 0xfd, 0x78, 0xc3, 0xfd, 0x02, 0x56, ++ 0xf0, 0x83, 0x06, 0x6f, 0x3f, 0x3f, 0xa6, 0x7d, 0xf7, 0xa0, 0xed, 0x47, ++ 0xda, 0x4d, 0x36, 0xb4, 0xdb, 0xa6, 0x71, 0xb9, 0x11, 0x4c, 0x89, 0x0b, ++ 0x0d, 0x16, 0xf7, 0xfb, 0x72, 0x5a, 0xd5, 0x7b, 0xb8, 0xa4, 0x87, 0xca, ++ 0x63, 0xfb, 0x62, 0x9a, 0xc8, 0xbf, 0xb7, 0x81, 0x44, 0xc3, 0x7d, 0x29, ++ 0xc1, 0x3f, 0x5b, 0xd2, 0x1b, 0x28, 0xaf, 0x4d, 0x8d, 0xe3, 0xfb, 0xa8, ++ 0x66, 0x10, 0x23, 0xc8, 0x4f, 0xc7, 0x9c, 0xb5, 0x3c, 0x1f, 0x23, 0xcb, ++ 0x98, 0xd7, 0x26, 0xef, 0x15, 0x69, 0xc3, 0xfb, 0x42, 0xa0, 0xbc, 0xca, ++ 0x61, 0xb4, 0xd7, 0x2b, 0x59, 0xdf, 0xb1, 0x89, 0x0a, 0xfa, 0xaf, 0x46, ++ 0x7b, 0x7d, 0x3a, 0x4a, 0x52, 0xdc, 0xaf, 0x62, 0xb1, 0x76, 0x7c, 0x03, ++ 0xed, 0x9b, 0x9a, 0xb3, 0x8c, 0x72, 0xa1, 0x43, 0xac, 0x17, 0x93, 0xb3, ++ 0xa4, 0x87, 0xf2, 0xe0, 0x52, 0x1d, 0x94, 0xe7, 0x30, 0x54, 0xdc, 0xe1, ++ 0xcd, 0x26, 0x46, 0xf9, 0x59, 0xe6, 0x78, 0x7f, 0x03, 0xea, 0xbc, 0xb4, ++ 0xe9, 0xda, 0x88, 0xb6, 0x32, 0x80, 0x13, 0x38, 0x9f, 0xe5, 0x4d, 0xcf, ++ 0x58, 0x8e, 0x71, 0xde, 0x37, 0x05, 0x3f, 0xb7, 0x81, 0x1c, 0xa0, 0xf3, ++ 0xa3, 0x8d, 0xc3, 0x76, 0xa9, 0x51, 0xed, 0xd6, 0x58, 0xc2, 0xa3, 0x51, ++ 0xaf, 0xd4, 0x98, 0xf8, 0xb9, 0x00, 0xfa, 0x81, 0xfe, 0xdf, 0x4c, 0x1d, ++ 0x4e, 0xf1, 0xd7, 0xd8, 0x7e, 0xe5, 0xbd, 0x31, 0x12, 0x5e, 0xd6, 0xa0, ++ 0x4c, 0xcb, 0x8b, 0x9a, 0xdf, 0x9b, 0x62, 0x7d, 0xf4, 0xf7, 0x77, 0x6b, ++ 0xe6, 0x2e, 0xb4, 0x6b, 0xfb, 0xfb, 0xb3, 0x86, 0x27, 0x51, 0x7f, 0xfd, ++ 0x79, 0x46, 0xa2, 0xbf, 0xb4, 0x6f, 0xd6, 0xdf, 0x5f, 0xc4, 0xfa, 0x96, ++ 0xfd, 0x2d, 0xfb, 0xb6, 0x71, 0x7e, 0xcb, 0x2c, 0x3d, 0x34, 0xbf, 0x65, ++ 0xe2, 0xbe, 0x52, 0xd9, 0xdf, 0x5f, 0x70, 0x7e, 0xb9, 0xdf, 0xa0, 0x3f, ++ 0x91, 0x1f, 0xd6, 0xdf, 0xdf, 0x77, 0x8c, 0xf3, 0x5b, 0x66, 0xed, 0xa1, ++ 0xf9, 0x2d, 0xeb, 0xf7, 0x2f, 0x45, 0x7f, 0x69, 0xdf, 0xac, 0x3f, 0x99, ++ 0xff, 0x60, 0xb5, 0x36, 0xd4, 0x22, 0x3f, 0x0d, 0x95, 0x07, 0x21, 0xf3, ++ 0x1f, 0x26, 0x77, 0x64, 0x1a, 0xf2, 0x1f, 0x58, 0x30, 0x73, 0x6e, 0x65, ++ 0x1e, 0x63, 0x0f, 0x28, 0x9c, 0x2f, 0x56, 0x1d, 0x1a, 0xfd, 0x53, 0xe4, ++ 0x8b, 0xb3, 0x73, 0x1b, 0x3d, 0x64, 0xa7, 0x08, 0x7f, 0x8f, 0xce, 0x0b, ++ 0xa9, 0x74, 0x5e, 0x88, 0xf4, 0xe8, 0xd5, 0x59, 0xdc, 0x0e, 0x91, 0xed, ++ 0xef, 0x69, 0x2a, 0x63, 0xbe, 0x31, 0x3c, 0x4e, 0x84, 0xcf, 0x82, 0x0a, ++ 0x85, 0xce, 0x23, 0x8c, 0x2d, 0x53, 0x7c, 0xb8, 0xef, 0xb6, 0x03, 0xe4, ++ 0x07, 0xde, 0x7f, 0xb7, 0x13, 0xd6, 0x39, 0x96, 0x87, 0x9a, 0xd2, 0xe9, ++ 0xb9, 0xbb, 0x49, 0xa7, 0xe7, 0x63, 0xe0, 0x5f, 0xfa, 0x28, 0x2e, 0xe6, ++ 0x21, 0xf8, 0x87, 0xd3, 0x79, 0xdc, 0xe5, 0x81, 0x0c, 0xf7, 0x92, 0x55, ++ 0x68, 0x7f, 0x54, 0xc6, 0xf1, 0x7c, 0xec, 0x8a, 0xa9, 0x60, 0xd9, 0x46, ++ 0xfc, 0x37, 0x58, 0x2f, 0x47, 0xed, 0x98, 0xf7, 0x78, 0x2d, 0x2b, 0xc2, ++ 0x73, 0x68, 0xf9, 0x1d, 0x1c, 0x9f, 0x29, 0xd5, 0x69, 0x74, 0xdf, 0x7d, ++ 0x5c, 0xd1, 0xf1, 0x9e, 0x26, 0x80, 0xb7, 0x94, 0xa9, 0x3a, 0xe6, 0x99, ++ 0x6f, 0xd1, 0x07, 0x8f, 0xf3, 0x6c, 0x9b, 0xce, 0xe3, 0xbf, 0x5b, 0x44, ++ 0x1e, 0x65, 0x10, 0xcf, 0x49, 0x92, 0x52, 0x01, 0x7f, 0x12, 0xe6, 0xbf, ++ 0x5c, 0x90, 0x8a, 0xa9, 0x73, 0xe9, 0xfc, 0xcd, 0xd5, 0xdf, 0x49, 0x24, ++ 0xfb, 0xa6, 0xe6, 0x5b, 0xbd, 0x4e, 0x37, 0x8c, 0xe3, 0x06, 0xa5, 0xe8, ++ 0x3f, 0xf2, 0x00, 0x1f, 0x7f, 0x15, 0xf6, 0xcd, 0xf2, 0x9c, 0x2b, 0x49, ++ 0x1e, 0xc4, 0xfa, 0xa7, 0x29, 0xa8, 0xa9, 0x4a, 0x30, 0xbf, 0x50, 0x0d, ++ 0x85, 0xe0, 0xd7, 0x45, 0xce, 0x45, 0xe4, 0xdf, 0x2e, 0xba, 0x86, 0xb1, ++ 0x24, 0xf8, 0xfe, 0x6a, 0xfc, 0x0e, 0xf4, 0xd4, 0xab, 0xc2, 0x3e, 0x7a, ++ 0xa5, 0xd7, 0xca, 0xd0, 0xff, 0x0b, 0x56, 0xf3, 0xfd, 0xec, 0x1b, 0xee, ++ 0x32, 0xfa, 0xa5, 0x0f, 0xd8, 0xc3, 0x6e, 0xb4, 0x0b, 0x1f, 0x28, 0x4a, ++ 0x61, 0x48, 0x8f, 0x9a, 0xdb, 0x8c, 0xe5, 0x5b, 0x2c, 0x7c, 0xbd, 0x2d, ++ 0x8a, 0xf1, 0x53, 0xaf, 0x8e, 0xc9, 0x03, 0x92, 0xf7, 0x1f, 0x6e, 0xc1, ++ 0x5f, 0xa7, 0x00, 0x3e, 0xa7, 0x8b, 0x7b, 0x5f, 0x44, 0x1e, 0xd0, 0x55, ++ 0xd3, 0x75, 0xae, 0xaf, 0xb3, 0x92, 0x28, 0xe9, 0x5b, 0x9e, 0xcf, 0xb4, ++ 0x5a, 0xd9, 0xa0, 0xfb, 0x94, 0xb2, 0xbd, 0xbd, 0x28, 0xb7, 0x50, 0xce, ++ 0xa6, 0xf8, 0x08, 0x0f, 0x32, 0x6f, 0x8e, 0xa9, 0x7b, 0x8b, 0xf0, 0x7b, ++ 0xd9, 0x9f, 0xfc, 0xee, 0x61, 0x65, 0x6f, 0xc6, 0xc5, 0xe2, 0xa9, 0x60, ++ 0x07, 0x9e, 0xec, 0x2d, 0xe0, 0xfa, 0x1e, 0xed, 0xf5, 0xdd, 0xd3, 0x8d, ++ 0xf9, 0x4a, 0x67, 0xe7, 0x8e, 0xfc, 0x7e, 0x35, 0x1b, 0x8c, 0x6f, 0xfb, ++ 0x34, 0x8c, 0x53, 0xc8, 0xf1, 0xff, 0x6f, 0xf1, 0x6b, 0xcd, 0x74, 0x3e, ++ 0xdf, 0x57, 0x67, 0x7e, 0x56, 0xc2, 0xcf, 0xdd, 0x65, 0xb1, 0xe8, 0xf3, ++ 0x76, 0x32, 0x1f, 0x6c, 0x51, 0x3f, 0xac, 0xd1, 0x7d, 0xc2, 0x32, 0x1f, ++ 0x90, 0xa5, 0xf7, 0x15, 0x22, 0xbd, 0xff, 0x7d, 0x5a, 0xbc, 0xe7, 0x1e, ++ 0xe2, 0x3f, 0x61, 0x8f, 0x84, 0xdf, 0x30, 0x5d, 0x88, 0xff, 0xfa, 0xed, ++ 0xf5, 0x8f, 0x23, 0xdd, 0x97, 0x6d, 0x38, 0xbf, 0x2a, 0xda, 0x1b, 0x0a, ++ 0xcf, 0x43, 0xdd, 0x37, 0x41, 0x3f, 0x51, 0xf9, 0x92, 0x2d, 0xcd, 0x9e, ++ 0x74, 0x3a, 0x5f, 0x97, 0xca, 0xf7, 0xdf, 0x86, 0xa7, 0x54, 0x7d, 0x80, ++ 0xe7, 0xb9, 0xb0, 0xfc, 0x1d, 0x03, 0x7f, 0x19, 0xcf, 0x6d, 0xb5, 0x1c, ++ 0x79, 0x52, 0x41, 0xbf, 0xe5, 0x27, 0x78, 0xde, 0xcd, 0x1c, 0xe9, 0x17, ++ 0xe3, 0xc3, 0x6d, 0x0e, 0x6c, 0x37, 0xc4, 0xe3, 0x4a, 0xe1, 0x27, 0x29, ++ 0x2e, 0x9c, 0x55, 0x1b, 0x56, 0x5a, 0x0b, 0x23, 0xe7, 0x83, 0x62, 0xe5, ++ 0x62, 0xd6, 0x3a, 0xe3, 0xf9, 0xb3, 0xd8, 0x7b, 0x14, 0xe7, 0x39, 0x7a, ++ 0x35, 0x45, 0xc7, 0x7d, 0x80, 0x3e, 0x3a, 0xd7, 0x98, 0x33, 0x43, 0xec, ++ 0xdb, 0x20, 0x8e, 0xb1, 0x5e, 0x2a, 0xb7, 0x27, 0xd5, 0x4c, 0x13, 0xcf, ++ 0x1f, 0x19, 0xa1, 0x73, 0xfb, 0x32, 0xaf, 0x2f, 0x27, 0x7a, 0x1f, 0x44, ++ 0x9d, 0xc1, 0xed, 0x86, 0x79, 0xf1, 0xaf, 0xdf, 0xa6, 0x83, 0xe8, 0xfd, ++ 0xc7, 0xa1, 0xbb, 0x96, 0x63, 0x9e, 0xd4, 0xbc, 0x84, 0xd7, 0x6f, 0xcb, ++ 0x05, 0xf8, 0xfc, 0xa1, 0xef, 0x2d, 0xc7, 0x3c, 0xaa, 0x79, 0x99, 0xaf, ++ 0x7f, 0x96, 0x0b, 0xf2, 0xf6, 0xcb, 0x43, 0xff, 0x87, 0x97, 0x8f, 0x7b, ++ 0xfd, 0xb3, 0x91, 0x68, 0x23, 0x1e, 0x6e, 0xe2, 0xe5, 0x53, 0x19, 0x21, ++ 0xc9, 0x74, 0x38, 0xb8, 0x9c, 0xf6, 0x87, 0x66, 0xc8, 0x7b, 0x13, 0x7b, ++ 0xe8, 0xbc, 0x76, 0x2a, 0x1e, 0xac, 0x98, 0xf4, 0xcd, 0x9f, 0xaa, 0xd5, ++ 0x34, 0xe8, 0xba, 0x74, 0xcc, 0x90, 0x71, 0x4b, 0x46, 0xe7, 0xb3, 0xfd, ++ 0x07, 0x7f, 0x77, 0x02, 0xe5, 0x94, 0x5f, 0xc6, 0x79, 0x7d, 0xc6, 0x7d, ++ 0x4f, 0x26, 0xee, 0x4d, 0xbc, 0x4a, 0xb2, 0x57, 0x8a, 0x8b, 0xec, 0xa5, ++ 0x2b, 0xf1, 0x77, 0xc0, 0xe7, 0x55, 0xe2, 0xbe, 0x1d, 0x93, 0x2d, 0x4c, ++ 0x78, 0x1d, 0x13, 0xb9, 0xcf, 0xe4, 0xa1, 0xaf, 0x73, 0xdf, 0x4e, 0xe4, ++ 0x7c, 0x3c, 0xbf, 0x3f, 0xa8, 0x65, 0x23, 0x0b, 0x18, 0xef, 0x45, 0xf4, ++ 0x09, 0xfe, 0xe7, 0x79, 0x44, 0x72, 0x3c, 0xb2, 0xff, 0x01, 0xe3, 0xc2, ++ 0x7b, 0x01, 0x93, 0xa2, 0xc7, 0xb5, 0x83, 0xda, 0x91, 0xe3, 0xfa, 0xa4, ++ 0xc8, 0x1a, 0x54, 0x26, 0x46, 0xf6, 0x71, 0xe5, 0xb8, 0x3e, 0x51, 0xfa, ++ 0x76, 0x62, 0xd0, 0xa3, 0xee, 0xd8, 0x2f, 0x57, 0x20, 0xdd, 0x3e, 0x71, ++ 0xf6, 0xe5, 0xe0, 0xdf, 0x37, 0x39, 0x3e, 0xe3, 0x1d, 0xa2, 0xe3, 0x27, ++ 0xa9, 0x7d, 0x3b, 0x15, 0x4f, 0x14, 0x6c, 0xe6, 0x74, 0xf4, 0x1e, 0xde, ++ 0x4e, 0xf6, 0x54, 0x45, 0x86, 0xcf, 0x3b, 0x23, 0x15, 0xef, 0x0f, 0xe0, ++ 0xf7, 0x16, 0xb4, 0x0b, 0x3b, 0x72, 0x6b, 0x6a, 0x20, 0x88, 0x7e, 0x3d, ++ 0xf0, 0x1b, 0xe5, 0x71, 0x06, 0xb3, 0xf9, 0xb9, 0x86, 0xea, 0x12, 0xe3, ++ 0xdf, 0x61, 0xab, 0x10, 0xfc, 0xf5, 0x9b, 0x19, 0x7c, 0xff, 0x78, 0x96, ++ 0x75, 0x5b, 0xc3, 0x6b, 0x25, 0x78, 0x8f, 0xba, 0xc2, 0x9a, 0xa1, 0x7e, ++ 0xfd, 0xf9, 0xb3, 0x16, 0xf4, 0xfb, 0xe7, 0x1d, 0xe4, 0x7f, 0xa7, 0x75, ++ 0xfd, 0x81, 0xb7, 0x2d, 0xf4, 0x77, 0x19, 0x10, 0x86, 0x76, 0xd6, 0xef, ++ 0xb0, 0x0c, 0xfa, 0x77, 0xe0, 0x0e, 0xcf, 0x50, 0x25, 0xdd, 0x0d, 0xfe, ++ 0xca, 0xf3, 0xd9, 0xf9, 0x6d, 0x29, 0x30, 0x9e, 0xf5, 0xab, 0xf8, 0xfd, ++ 0xd8, 0x8d, 0xbf, 0x4e, 0x9c, 0x85, 0x70, 0xe3, 0x0a, 0x9c, 0x25, 0xfe, ++ 0x3d, 0xbd, 0x7d, 0xb3, 0xf0, 0xb3, 0x65, 0xfe, 0x23, 0x6d, 0xf8, 0x5c, ++ 0xce, 0x7a, 0x9f, 0xc7, 0x73, 0x7f, 0x4b, 0x02, 0x46, 0x3f, 0xe2, 0xfa, ++ 0x5a, 0xa3, 0xdd, 0xbf, 0xac, 0xc1, 0x68, 0xaf, 0x2f, 0xdf, 0x06, 0xd4, ++ 0x01, 0xbd, 0xb6, 0x7c, 0x63, 0x66, 0xcc, 0x3d, 0x7e, 0xfc, 0x7e, 0xc0, ++ 0x25, 0x82, 0x9e, 0x4b, 0xd2, 0xef, 0xed, 0xc1, 0x7b, 0x07, 0x96, 0xb0, ++ 0x98, 0xfb, 0x01, 0x83, 0x3c, 0x8e, 0x74, 0x3d, 0x9f, 0x01, 0x3c, 0x8d, ++ 0xf1, 0x91, 0x79, 0xf8, 0xf7, 0xa4, 0x70, 0x1e, 0xeb, 0x54, 0x8a, 0xf3, ++ 0x3e, 0x9f, 0xbd, 0x59, 0xc3, 0xf3, 0x70, 0xf5, 0x0d, 0xfc, 0x5e, 0xb2, ++ 0x59, 0x5d, 0x9f, 0x5a, 0xa8, 0x1c, 0xea, 0xe1, 0x7e, 0x53, 0xda, 0x70, ++ 0x7e, 0x0f, 0x9e, 0x94, 0x9f, 0x52, 0xbf, 0x5f, 0xff, 0xdc, 0x2e, 0x33, ++ 0xc6, 0x0b, 0x62, 0xef, 0x09, 0x5c, 0xbe, 0x78, 0x0e, 0xdd, 0x07, 0xbe, ++ 0x58, 0x5f, 0xcb, 0xf5, 0xfb, 0x88, 0x3f, 0xce, 0x4a, 0x82, 0xf7, 0xb1, ++ 0xf7, 0xff, 0xd5, 0x74, 0x71, 0xfd, 0x5e, 0xb3, 0x51, 0x09, 0xe1, 0x7d, ++ 0xbb, 0xd7, 0xd7, 0x1a, 0xfd, 0x81, 0x65, 0xac, 0xa7, 0x0d, 0xfd, 0x99, ++ 0x65, 0x0d, 0xc6, 0xf7, 0xcb, 0x37, 0x1a, 0xe1, 0xef, 0xcd, 0x10, 0x7a, ++ 0x6d, 0x1c, 0x1b, 0x87, 0xeb, 0x63, 0xd3, 0x0c, 0x45, 0xa3, 0x73, 0xd5, ++ 0x02, 0x3e, 0x9d, 0xfd, 0xc7, 0x57, 0xc2, 0xd0, 0x7f, 0x55, 0x86, 0xbf, ++ 0x6d, 0x06, 0xf0, 0xc9, 0x3a, 0x4b, 0x78, 0x02, 0xea, 0xb9, 0xaa, 0x8c, ++ 0x00, 0xc1, 0xb2, 0x1c, 0xde, 0xaf, 0xe7, 0x7a, 0x88, 0xeb, 0x7f, 0x13, ++ 0xac, 0x24, 0x92, 0xbf, 0x66, 0x1e, 0xb7, 0x08, 0xd6, 0xf1, 0x7b, 0xd9, ++ 0xae, 0x1f, 0x60, 0x0f, 0x44, 0xd9, 0x0b, 0xea, 0x40, 0xb8, 0x4b, 0xca, ++ 0x4f, 0xbb, 0xff, 0x36, 0xf2, 0xc3, 0x9e, 0x53, 0xe8, 0xef, 0x82, 0x57, ++ 0x6b, 0x3e, 0x2d, 0x29, 0xca, 0x4f, 0x8e, 0xe5, 0xc3, 0x5f, 0x0b, 0xbe, ++ 0x7e, 0x85, 0xf5, 0x16, 0xe2, 0xb8, 0xf2, 0x91, 0xe9, 0x80, 0x2e, 0xf9, ++ 0x8b, 0xf8, 0xdf, 0x7d, 0xce, 0x3f, 0xbc, 0x82, 0xf2, 0x2c, 0xf3, 0x8b, ++ 0x15, 0x8f, 0x89, 0xd6, 0xb1, 0x89, 0x6d, 0xc4, 0xfb, 0xc4, 0x40, 0x5e, ++ 0xa0, 0x5c, 0x40, 0xfb, 0x13, 0xef, 0xc9, 0xc8, 0x57, 0x3b, 0x17, 0x93, ++ 0x9c, 0x9e, 0x68, 0x71, 0xf3, 0xfb, 0x76, 0xd2, 0x59, 0xf4, 0xfa, 0xf7, ++ 0x3d, 0xc9, 0x14, 0xc4, 0x17, 0x0e, 0x1d, 0xfb, 0xbd, 0x2a, 0xab, 0x9b, ++ 0xee, 0xdb, 0x98, 0xdf, 0x71, 0xef, 0xa7, 0x28, 0xe7, 0xf2, 0x46, 0xf9, ++ 0xbc, 0x0f, 0xc0, 0xf8, 0xb6, 0x8a, 0xfb, 0xb4, 0xb7, 0xfe, 0x5a, 0x21, ++ 0x7b, 0x76, 0x7d, 0xe1, 0x0b, 0x24, 0x0f, 0x87, 0x01, 0x5b, 0x60, 0xbf, ++ 0xeb, 0xd3, 0x85, 0x5c, 0xec, 0x32, 0xde, 0x83, 0x31, 0x0c, 0xe5, 0x14, ++ 0x1e, 0x68, 0x99, 0x5b, 0x48, 0xfd, 0x66, 0xc8, 0xfd, 0x07, 0x99, 0xe7, ++ 0x1b, 0xae, 0xa2, 0x7b, 0xa5, 0x86, 0x89, 0x7e, 0x7f, 0x3f, 0x4b, 0xa7, ++ 0x79, 0xa7, 0xad, 0xed, 0x54, 0x70, 0xde, 0xd9, 0x2c, 0xd8, 0x8c, 0x71, ++ 0xa8, 0x3d, 0x28, 0x0b, 0x53, 0x23, 0x4f, 0xb9, 0x4f, 0x70, 0x4d, 0x64, ++ 0xff, 0xbc, 0x02, 0xe9, 0x59, 0x97, 0xde, 0x4b, 0xf7, 0xc2, 0xc8, 0xfd, ++ 0xf3, 0x41, 0xea, 0xcd, 0x46, 0xb9, 0x33, 0xa0, 0x9e, 0x8f, 0x19, 0xf2, ++ 0x80, 0x66, 0xa9, 0xe7, 0x5d, 0xb8, 0xbf, 0xdd, 0xf8, 0xdc, 0xa8, 0x8b, ++ 0xe6, 0x75, 0xa8, 0x36, 0xe3, 0xfd, 0x90, 0x66, 0xb7, 0xf1, 0x7e, 0xc8, ++ 0xab, 0x0a, 0x8c, 0xeb, 0x7b, 0x9e, 0xc7, 0xb8, 0xae, 0xaf, 0x2e, 0x1b, ++ 0x65, 0x28, 0x5f, 0xe0, 0x1b, 0x67, 0x28, 0x5f, 0x34, 0xa7, 0xd8, 0x00, ++ 0x5f, 0xe3, 0x9f, 0x6a, 0xa8, 0x7f, 0xdd, 0xe2, 0x99, 0xc6, 0x38, 0x42, ++ 0xba, 0xf1, 0x7e, 0x48, 0xbb, 0x6e, 0xbc, 0x1f, 0x32, 0xbe, 0xc0, 0x78, ++ 0x3f, 0xa4, 0xd3, 0x63, 0xbc, 0x1f, 0x92, 0xa5, 0x74, 0x52, 0x5e, 0x9a, ++ 0xc5, 0x16, 0xec, 0x0d, 0xe8, 0x78, 0xbf, 0x00, 0xbf, 0x87, 0x56, 0xca, ++ 0xe9, 0x71, 0x2e, 0x1b, 0x5d, 0x2a, 0x17, 0x57, 0x6c, 0x77, 0xe0, 0xb3, ++ 0xbd, 0xc8, 0x1a, 0x46, 0xba, 0xb5, 0x0f, 0xe7, 0xfb, 0xb9, 0xd6, 0x17, ++ 0x6f, 0x4f, 0x0f, 0x23, 0xd6, 0x13, 0xf6, 0xda, 0x2a, 0xe1, 0xf9, 0xb4, ++ 0x12, 0xaa, 0xc2, 0xfd, 0x28, 0x9b, 0xf0, 0x1b, 0x2f, 0xbb, 0x8b, 0x19, ++ 0xe4, 0xf8, 0x95, 0x33, 0xb9, 0x1c, 0x97, 0x4f, 0xe6, 0x0b, 0xc4, 0x57, ++ 0x62, 0x5c, 0x76, 0x8f, 0x9e, 0xc9, 0xf3, 0xb6, 0x7b, 0x2e, 0xbb, 0x58, ++ 0x7e, 0xc5, 0xa5, 0x3e, 0xff, 0x2f, 0xc2, 0x78, 0x4b, 0x6b, 0x00, 0x80, ++ 0x00, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x0b, 0xed, 0x5a, 0x7d, 0x50, 0x54, 0x57, 0x96, 0x3f, 0xb7, 0xfb, ++ 0x75, 0xd3, 0x0d, 0x88, 0x0d, 0x28, 0x1f, 0x41, 0xf4, 0xa1, 0xa0, 0x26, ++ 0x20, 0x69, 0x41, 0x8c, 0x4e, 0x66, 0x36, 0xaf, 0xbb, 0x81, 0x69, 0x3f, ++ 0x32, 0x69, 0xfc, 0x98, 0x60, 0x10, 0xd3, 0xec, 0xe8, 0x16, 0x13, 0x81, ++ 0x26, 0xd1, 0x4c, 0x91, 0xaa, 0xdd, 0xa2, 0x55, 0x86, 0x34, 0x66, 0xfe, ++ 0x48, 0xac, 0x4c, 0xc6, 0xa4, 0x52, 0xb5, 0xad, 0x15, 0x33, 0x99, 0xa9, ++ 0x71, 0x17, 0x13, 0x56, 0xdb, 0x4d, 0xeb, 0x36, 0x2a, 0xae, 0xc9, 0x9a, ++ 0xb1, 0xdd, 0x31, 0x19, 0x4d, 0x2a, 0x29, 0x74, 0xdd, 0x4c, 0xac, 0x8c, ++ 0x0a, 0x31, 0xe3, 0x98, 0x5d, 0x77, 0xdd, 0x73, 0xee, 0x7d, 0x8f, 0xee, ++ 0xd7, 0x3c, 0x12, 0xb2, 0x35, 0x95, 0xaa, 0x9d, 0x5a, 0x28, 0xea, 0x72, ++ 0xdf, 0xbb, 0x9f, 0xe7, 0xfb, 0xfc, 0xce, 0xb3, 0xa5, 0x03, 0xc0, 0x22, ++ 0xfc, 0x3b, 0x68, 0x0b, 0xef, 0x2b, 0x01, 0xb8, 0x97, 0xe1, 0xff, 0x4b, ++ 0x01, 0xee, 0xd0, 0xcf, 0x03, 0x00, 0xa7, 0xeb, 0x5c, 0x16, 0xa5, 0x06, ++ 0xa0, 0xe2, 0xaf, 0x95, 0x65, 0x30, 0x0d, 0xdf, 0x45, 0xc0, 0x51, 0x86, ++ 0xe3, 0xf6, 0x5a, 0x41, 0xa1, 0x7e, 0xf0, 0xa0, 0x95, 0xcf, 0xab, 0x88, ++ 0x0c, 0x9b, 0x94, 0xcc, 0xc4, 0xbc, 0xe7, 0x14, 0x5c, 0x68, 0x3a, 0xc0, ++ 0x4f, 0x7d, 0xee, 0x65, 0xb4, 0x7e, 0x47, 0x94, 0x39, 0x00, 0xc7, 0x75, ++ 0xec, 0xbe, 0x64, 0x95, 0x2b, 0xa8, 0x3f, 0x98, 0xa5, 0x60, 0x5b, 0xe9, ++ 0xbb, 0x64, 0x85, 0xcc, 0xe4, 0xe7, 0x17, 0xad, 0xf4, 0xbc, 0x43, 0x1a, ++ 0x49, 0x77, 0x60, 0xfb, 0xf7, 0xfd, 0x66, 0x6f, 0xb8, 0x22, 0xb1, 0xae, ++ 0xd6, 0xba, 0x14, 0x2b, 0x5f, 0xff, 0x64, 0x31, 0xb6, 0x78, 0x8e, 0xe6, ++ 0x27, 0xcd, 0xe1, 0x34, 0x3a, 0x3b, 0x28, 0x2b, 0x5d, 0x8b, 0x01, 0x1a, ++ 0xe9, 0x5f, 0x19, 0x9f, 0x1f, 0x18, 0x89, 0x99, 0x71, 0xff, 0xe6, 0x76, ++ 0xe6, 0x0c, 0xe2, 0xa3, 0x46, 0xf9, 0xb1, 0x95, 0x90, 0x85, 0xff, 0xf8, ++ 0x2d, 0x97, 0x86, 0x6d, 0x00, 0x36, 0xfc, 0xbd, 0x33, 0x1b, 0xcf, 0x59, ++ 0x98, 0xb5, 0x17, 0xee, 0xe5, 0xf3, 0x01, 0xf2, 0x00, 0x1e, 0x05, 0xf1, ++ 0xf3, 0xc8, 0x92, 0x98, 0x05, 0x4c, 0x00, 0x4d, 0xad, 0x62, 0x3c, 0xfd, ++ 0xdc, 0xc1, 0xbf, 0x47, 0xd7, 0xd4, 0x5f, 0x61, 0x95, 0xb8, 0x6e, 0x67, ++ 0xca, 0xf3, 0x19, 0xbd, 0xa3, 0xe6, 0x2c, 0x9a, 0x2f, 0x5d, 0x1a, 0x9e, ++ 0xaf, 0x3e, 0x27, 0xba, 0x2a, 0x53, 0xa6, 0x7d, 0x5c, 0x8e, 0x9d, 0x72, ++ 0xa8, 0xb8, 0x33, 0x07, 0xe0, 0xbc, 0xcf, 0x64, 0x78, 0xaf, 0x87, 0x3c, ++ 0x12, 0xbf, 0xd7, 0x79, 0xbf, 0x87, 0xd3, 0xfb, 0xa7, 0x48, 0x37, 0x33, ++ 0x23, 0x3a, 0xa6, 0xd2, 0x49, 0xd0, 0xef, 0xab, 0xe8, 0xb3, 0x1f, 0xcf, ++ 0x9e, 0xcc, 0xa7, 0xd4, 0x71, 0x6b, 0x3c, 0x82, 0x4f, 0xfb, 0x19, 0x34, ++ 0xf6, 0x67, 0x8e, 0x7f, 0xff, 0x33, 0x95, 0x8f, 0x7b, 0x59, 0xbc, 0x0a, ++ 0xcc, 0x00, 0x01, 0x1f, 0x0a, 0xcc, 0x54, 0xa4, 0x87, 0xad, 0x65, 0xf3, ++ 0xe5, 0x6a, 0xa2, 0xff, 0xcd, 0x5e, 0x46, 0xf4, 0xff, 0x07, 0x06, 0x69, ++ 0xb8, 0xfe, 0x07, 0x83, 0x6f, 0xe5, 0xc9, 0x53, 0x00, 0xac, 0x07, 0x86, ++ 0xf2, 0x86, 0x71, 0xbd, 0x40, 0xff, 0x50, 0x1e, 0x2c, 0x00, 0x68, 0xb3, ++ 0xc8, 0xdb, 0xa4, 0x69, 0x5c, 0x0e, 0x9c, 0xdb, 0x90, 0x2f, 0x1d, 0x91, ++ 0x18, 0x3f, 0x7f, 0x7b, 0x7f, 0xf5, 0x20, 0x3d, 0x6f, 0x8f, 0x30, 0xa7, ++ 0x1d, 0x8f, 0x1a, 0x18, 0x18, 0xad, 0xe7, 0xf7, 0x84, 0xe1, 0x5e, 0x47, ++ 0x26, 0xed, 0x6b, 0x7c, 0xae, 0x66, 0xc5, 0xc4, 0xcf, 0xd5, 0xaa, 0xc8, ++ 0xbc, 0x0d, 0xf8, 0x71, 0xcf, 0x69, 0x34, 0x3f, 0x2d, 0x1c, 0x66, 0xc4, ++ 0xf7, 0x61, 0x2b, 0x97, 0x8b, 0xc3, 0x0c, 0x9e, 0xc5, 0xfe, 0xde, 0x3e, ++ 0x5b, 0x63, 0xd8, 0x60, 0x9d, 0x75, 0x44, 0x6f, 0x94, 0xef, 0x13, 0x7d, ++ 0x56, 0x90, 0x50, 0x4e, 0xda, 0x70, 0x3e, 0xdd, 0xe3, 0x64, 0xf1, 0x49, ++ 0xab, 0x8d, 0xe4, 0xe6, 0x00, 0xde, 0x8b, 0xd1, 0x3d, 0xce, 0xae, 0xcd, ++ 0xa0, 0xf5, 0xb7, 0x5a, 0x40, 0x66, 0x89, 0xf3, 0x5d, 0x2d, 0x8e, 0x7f, ++ 0x44, 0xf7, 0xbf, 0xb0, 0xd1, 0x02, 0x41, 0x7c, 0xbe, 0x63, 0xa3, 0x99, ++ 0xd3, 0xfb, 0xc2, 0x56, 0x33, 0x5f, 0xc7, 0xbc, 0xe9, 0xdf, 0x7b, 0x8b, ++ 0xb0, 0xbf, 0x0e, 0xe5, 0x2f, 0x0d, 0x8f, 0x7a, 0x7c, 0xe3, 0x8d, 0x93, ++ 0x45, 0xb8, 0xee, 0x85, 0x56, 0xec, 0xe3, 0x7d, 0x3d, 0x9b, 0x2c, 0x5c, ++ 0xff, 0xd6, 0x3d, 0xce, 0xf8, 0xf8, 0x54, 0xf9, 0xd5, 0xe4, 0xf5, 0x25, ++ 0x55, 0x3e, 0xd7, 0xf9, 0xf5, 0xf2, 0x96, 0x2a, 0xaf, 0xe3, 0xe4, 0xb4, ++ 0xf5, 0xeb, 0xc9, 0x69, 0x0f, 0xc9, 0x69, 0x06, 0x97, 0xd3, 0xca, 0x3b, ++ 0x66, 0xce, 0xf7, 0xba, 0x7c, 0x92, 0x9f, 0xa7, 0xc0, 0xb9, 0x8f, 0xf4, ++ 0xe7, 0xf6, 0x71, 0x4b, 0x3e, 0x9e, 0x77, 0x76, 0xaf, 0xc3, 0xb9, 0x1d, ++ 0xfb, 0x0b, 0xcc, 0xe1, 0x1f, 0xe7, 0x91, 0x5d, 0x38, 0x2e, 0xde, 0x2f, ++ 0x6c, 0xdb, 0xc3, 0x48, 0x5f, 0xf0, 0xf0, 0x8f, 0xd0, 0xbd, 0x8a, 0x42, ++ 0x56, 0xd8, 0xc9, 0x48, 0x8e, 0x04, 0xbf, 0x7e, 0xa6, 0xf2, 0x4b, 0x86, ++ 0x11, 0x96, 0x41, 0xfa, 0x2a, 0xc5, 0x67, 0xfb, 0x50, 0x3e, 0x70, 0x6b, ++ 0x85, 0xf8, 0xfc, 0xba, 0x05, 0x1a, 0x0f, 0x54, 0xd0, 0x73, 0x61, 0x5f, ++ 0x16, 0x1c, 0x2a, 0xd8, 0xb3, 0x33, 0x49, 0x6e, 0xeb, 0x55, 0x79, 0xb4, ++ 0x99, 0xc0, 0xdf, 0x8f, 0xe3, 0xca, 0xad, 0xe0, 0x3f, 0x90, 0x49, 0xe3, ++ 0xfb, 0xef, 0x6a, 0xc0, 0x75, 0xf6, 0xe3, 0x7c, 0x7a, 0x3e, 0x53, 0x5d, ++ 0xaf, 0x6c, 0xce, 0x48, 0x7d, 0x03, 0xb6, 0x87, 0x68, 0x7f, 0xe4, 0xf3, ++ 0x1e, 0xf5, 0x1c, 0x5a, 0xff, 0x07, 0x24, 0xff, 0xd8, 0xc2, 0xcb, 0x26, ++ 0x06, 0x48, 0xf7, 0x07, 0x6d, 0x82, 0xee, 0xcb, 0xbb, 0x62, 0xeb, 0xe9, ++ 0x1e, 0x8b, 0x66, 0xf8, 0x7f, 0x4e, 0xf6, 0x6f, 0xe5, 0xcc, 0xf7, 0xda, ++ 0x00, 0xed, 0x44, 0x68, 0xf6, 0xdb, 0x15, 0x7e, 0x3a, 0x1f, 0x38, 0x4d, ++ 0x44, 0xf7, 0x80, 0x4a, 0xf7, 0xe3, 0x4b, 0x7f, 0xf7, 0xf2, 0x16, 0xbc, ++ 0xaf, 0xfd, 0xee, 0x74, 0xce, 0xd7, 0x86, 0x63, 0x2f, 0xc6, 0x89, 0xcf, ++ 0x1d, 0xa5, 0x12, 0x10, 0xdf, 0xed, 0x65, 0x8b, 0xf2, 0xfd, 0x06, 0xf2, ++ 0xa7, 0xb5, 0x81, 0x5b, 0x25, 0xe0, 0xcf, 0x4d, 0xf4, 0x3b, 0xa2, 0xa3, ++ 0xf5, 0x8a, 0x81, 0x5e, 0x6f, 0x50, 0xf5, 0x75, 0x81, 0x55, 0xdc, 0x1f, ++ 0xa2, 0x48, 0xa4, 0x42, 0x6e, 0x8f, 0xa5, 0x25, 0x55, 0x89, 0x71, 0xda, ++ 0xfd, 0x01, 0xb6, 0xf3, 0xfb, 0xd9, 0xcb, 0x5e, 0xe1, 0x7c, 0xda, 0xf2, ++ 0x38, 0x2c, 0x34, 0xf3, 0x13, 0x3f, 0xc7, 0xd7, 0x69, 0x6a, 0x3b, 0xcb, ++ 0x5a, 0x70, 0x9d, 0x87, 0x2d, 0x8a, 0x25, 0x13, 0xe9, 0xfc, 0xde, 0xd4, ++ 0xc6, 0xcd, 0x97, 0xcb, 0x00, 0xde, 0xee, 0x46, 0x13, 0x89, 0x17, 0x39, ++ 0xdd, 0x6d, 0x03, 0xff, 0x3c, 0x80, 0x5f, 0x77, 0x3b, 0x78, 0x3f, 0xde, ++ 0x5d, 0xc0, 0xfb, 0xff, 0xda, 0x2d, 0xf3, 0x76, 0xde, 0x4c, 0xdf, 0xdb, ++ 0x0a, 0xae, 0xb3, 0xf6, 0x44, 0x67, 0x19, 0xd1, 0xeb, 0x78, 0xf1, 0x0b, ++ 0x3e, 0x37, 0xee, 0x73, 0xfd, 0xb4, 0x85, 0xd3, 0x01, 0xc0, 0xcd, 0xe9, ++ 0xb4, 0x45, 0x95, 0xbd, 0x1b, 0x51, 0x33, 0xd8, 0xf0, 0xfd, 0x8d, 0x01, ++ 0x16, 0x06, 0x96, 0x38, 0xff, 0x86, 0x5b, 0x45, 0xe0, 0x47, 0x7b, 0xf2, ++ 0x3e, 0xed, 0x87, 0x13, 0xdb, 0xbb, 0x7e, 0xc3, 0xed, 0x9c, 0xb3, 0x75, ++ 0xb4, 0x5e, 0xce, 0x24, 0xb9, 0xba, 0xd8, 0x4b, 0xfd, 0x40, 0xd7, 0x1f, ++ 0xea, 0x01, 0xdb, 0x8f, 0xd0, 0x4f, 0x90, 0x7c, 0x05, 0x22, 0x0c, 0x0a, ++ 0x70, 0x9d, 0xf5, 0xb7, 0x72, 0xf9, 0xfc, 0xf6, 0xc8, 0x59, 0xab, 0x4c, ++ 0x72, 0x60, 0x1a, 0xa9, 0x27, 0xfa, 0x07, 0x8f, 0x32, 0x20, 0xb9, 0x0c, ++ 0x74, 0x8e, 0x72, 0xfb, 0xf9, 0x32, 0xde, 0x4b, 0xc1, 0x73, 0xa7, 0xbb, ++ 0xb2, 0x39, 0x5d, 0x02, 0xd1, 0x85, 0x26, 0xc1, 0xcf, 0x45, 0x26, 0xe2, ++ 0xff, 0x13, 0x2a, 0xff, 0x07, 0xef, 0xf9, 0x8f, 0x2c, 0xb2, 0x5f, 0xb6, ++ 0x2e, 0xf9, 0xcc, 0xfd, 0xc4, 0xc7, 0x53, 0x66, 0xce, 0xc7, 0x9d, 0xee, ++ 0x91, 0x2c, 0x87, 0x01, 0x5f, 0xce, 0xe3, 0xba, 0x90, 0x26, 0xce, 0x4f, ++ 0x6d, 0xea, 0xfb, 0x46, 0x6b, 0xb0, 0xcc, 0x89, 0xf3, 0x1a, 0x55, 0xb9, ++ 0x4d, 0x7d, 0x6f, 0x75, 0x09, 0xb9, 0x44, 0x0a, 0x5b, 0x7c, 0x53, 0x04, ++ 0xad, 0x18, 0xd2, 0x6d, 0xbd, 0x2a, 0x5f, 0xcd, 0x78, 0x95, 0xa9, 0x39, ++ 0xd8, 0x8f, 0xb0, 0x58, 0x3a, 0xea, 0x6d, 0x73, 0xd4, 0x73, 0x45, 0xa2, ++ 0xb6, 0x93, 0xc1, 0x25, 0x9d, 0x3d, 0x00, 0xb8, 0xa4, 0xe9, 0xb3, 0x79, ++ 0x62, 0x79, 0x9b, 0x6c, 0xdb, 0x41, 0xeb, 0x95, 0x25, 0xd9, 0x4b, 0x3f, ++ 0x2e, 0x3a, 0x3f, 0xb1, 0x5f, 0x53, 0x6b, 0x06, 0x39, 0xd1, 0xa4, 0xfd, ++ 0x83, 0xfc, 0x1e, 0x69, 0xc5, 0xa5, 0xf9, 0x7e, 0x83, 0x7b, 0x8e, 0xc9, ++ 0xfb, 0x70, 0x11, 0xc8, 0xc8, 0xaf, 0x8e, 0x10, 0x03, 0x19, 0xe5, 0xbe, ++ 0xfd, 0x56, 0x39, 0x6f, 0xaf, 0x1d, 0x7e, 0x5a, 0x26, 0x3d, 0xb1, 0xa5, ++ 0x8f, 0xbc, 0x40, 0x7e, 0x01, 0xe6, 0x9a, 0x1c, 0xfb, 0x90, 0xbf, 0xed, ++ 0x41, 0x50, 0x92, 0xfd, 0xdc, 0xa8, 0x5b, 0xe8, 0xed, 0xa8, 0x5b, 0xe8, ++ 0xf1, 0x4c, 0x17, 0x93, 0x3e, 0xb6, 0x71, 0xbb, 0x55, 0x4e, 0xf7, 0x76, ++ 0x17, 0xfa, 0x4b, 0x5c, 0x78, 0x8e, 0xdf, 0x17, 0xbf, 0x97, 0x75, 0x0c, ++ 0x1f, 0xb7, 0x59, 0x63, 0x95, 0x60, 0xfc, 0xbc, 0x03, 0xd0, 0x1f, 0xdb, ++ 0x48, 0x9f, 0x70, 0xdf, 0x72, 0xe4, 0xcf, 0xeb, 0x06, 0xe7, 0xbe, 0xe9, ++ 0x76, 0xcf, 0xa5, 0x79, 0x33, 0xe1, 0x59, 0x2e, 0xdf, 0x80, 0xf2, 0x4d, ++ 0x72, 0x95, 0x7a, 0xcf, 0x85, 0x2e, 0x71, 0x2e, 0x4d, 0x9f, 0xd7, 0x1d, ++ 0xbb, 0x62, 0x1d, 0x26, 0xb9, 0x8d, 0x18, 0xeb, 0x33, 0xf3, 0xb8, 0x16, ++ 0xd2, 0xba, 0x7d, 0x00, 0x5e, 0x23, 0x3f, 0xf7, 0x47, 0xf5, 0x9e, 0xed, ++ 0xbb, 0x19, 0xa7, 0x57, 0x60, 0x77, 0x2e, 0xa7, 0xd3, 0x55, 0xd8, 0xed, ++ 0x73, 0xa3, 0x5c, 0x5e, 0xc5, 0x73, 0xec, 0x45, 0xb9, 0xbc, 0xee, 0xf3, ++ 0x65, 0x64, 0xe3, 0xfc, 0xeb, 0x7e, 0x5f, 0x46, 0x4e, 0x66, 0x42, 0xff, ++ 0x3b, 0x76, 0x67, 0xf0, 0x79, 0x7d, 0xa5, 0xab, 0x72, 0x5b, 0xb0, 0x5f, ++ 0x4f, 0x72, 0x8f, 0xfb, 0x5d, 0x8b, 0x78, 0x6c, 0x44, 0xe7, 0x0d, 0xbb, ++ 0x85, 0xde, 0x69, 0xfb, 0x7d, 0x14, 0x5b, 0x97, 0x4b, 0xfa, 0x53, 0x63, ++ 0x19, 0xb1, 0x3a, 0xf1, 0xfd, 0x8c, 0xe8, 0xc5, 0x2c, 0x8a, 0xeb, 0x6a, ++ 0x0e, 0xaf, 0xce, 0x25, 0xfd, 0x9b, 0xe8, 0x9c, 0x8b, 0xdd, 0xc2, 0x2e, ++ 0xb5, 0x77, 0x6d, 0xd9, 0x7c, 0x39, 0x57, 0xc8, 0x83, 0x19, 0xf5, 0x69, ++ 0xb3, 0xea, 0xc7, 0x02, 0xdb, 0x63, 0x56, 0xa2, 0xff, 0xe6, 0x2e, 0xe0, ++ 0xf2, 0x3b, 0x78, 0xf0, 0x83, 0x0e, 0xd2, 0xdf, 0x6b, 0xd1, 0x0c, 0x07, ++ 0xf9, 0xbd, 0xab, 0x47, 0x32, 0x82, 0x64, 0xef, 0xaf, 0x1f, 0x4d, 0x0b, ++ 0xa3, 0x25, 0x86, 0x36, 0x92, 0x77, 0xb4, 0x67, 0x57, 0x2d, 0xc3, 0xdf, ++ 0xe3, 0xf1, 0xe3, 0x61, 0xb3, 0x23, 0x88, 0xe3, 0x02, 0x47, 0x3f, 0x7d, ++ 0x81, 0xf4, 0x31, 0x70, 0x10, 0xb5, 0x11, 0xd7, 0xdd, 0x1c, 0x7d, 0x7a, ++ 0x94, 0xfc, 0x5b, 0x5b, 0x74, 0xd9, 0x15, 0x89, 0xda, 0x5f, 0x7d, 0xb3, ++ 0xfa, 0xd0, 0xde, 0xf5, 0x23, 0x7e, 0x5f, 0xad, 0xff, 0x69, 0xb7, 0x4d, ++ 0x26, 0xfb, 0x79, 0x4d, 0x12, 0x76, 0x62, 0x73, 0xe4, 0x0d, 0x1e, 0xcf, ++ 0x6e, 0xbe, 0x7d, 0xa3, 0xd2, 0x57, 0x41, 0xf7, 0xfc, 0xcf, 0xc5, 0x64, ++ 0xcf, 0x02, 0xff, 0x74, 0x63, 0x31, 0xd9, 0xb1, 0xc0, 0x9b, 0x37, 0x16, ++ 0xd3, 0xfb, 0xc0, 0xa1, 0x8c, 0x4e, 0xa3, 0xf8, 0xa4, 0xd5, 0x63, 0xe6, ++ 0xfc, 0xd7, 0xfc, 0x63, 0xc9, 0x39, 0x49, 0x49, 0x1e, 0x97, 0xad, 0xfa, ++ 0xaf, 0x92, 0x9e, 0x67, 0xbd, 0xb3, 0x91, 0x7e, 0x35, 0x67, 0xd7, 0x38, ++ 0xcd, 0x72, 0xe2, 0x7d, 0x4d, 0x99, 0xc9, 0x47, 0xe3, 0x6b, 0xde, 0xad, ++ 0xcd, 0xdd, 0x94, 0x34, 0xaf, 0x27, 0x2e, 0x79, 0xe9, 0xf9, 0xa2, 0xb3, ++ 0xb5, 0x19, 0x1b, 0x93, 0xe4, 0xd2, 0xea, 0xb1, 0xa8, 0x76, 0x08, 0xb5, ++ 0x1a, 0xed, 0xcf, 0x3a, 0x95, 0x86, 0xeb, 0x0a, 0x7e, 0x12, 0x37, 0x57, ++ 0x52, 0x5f, 0x0a, 0xaa, 0x71, 0x04, 0xbb, 0xc3, 0xe3, 0x6d, 0x90, 0x25, ++ 0xe4, 0x73, 0x13, 0xfd, 0x87, 0xaa, 0xd8, 0x17, 0x97, 0x78, 0x3c, 0x13, ++ 0x6c, 0x35, 0x87, 0xcb, 0xf0, 0x7d, 0x53, 0xdc, 0xa4, 0xd8, 0x2b, 0xe9, ++ 0x3d, 0xce, 0x4b, 0x8a, 0x33, 0x00, 0x7c, 0x2b, 0x16, 0x10, 0xbf, 0x7f, ++ 0x38, 0xdd, 0xb9, 0x53, 0xe6, 0xfe, 0x1e, 0xba, 0xa9, 0xff, 0x54, 0x59, ++ 0x98, 0xfc, 0x3d, 0x04, 0x6d, 0x43, 0xa5, 0x49, 0x71, 0xd0, 0xba, 0xb8, ++ 0x29, 0x96, 0x86, 0x72, 0xd3, 0x18, 0x4d, 0x8b, 0x51, 0x3c, 0xb4, 0x2e, ++ 0x2e, 0x5d, 0xe4, 0x7d, 0x35, 0x3e, 0xfa, 0xc8, 0xf1, 0xfa, 0x8f, 0x67, ++ 0x03, 0x8f, 0x8f, 0x2e, 0x27, 0xc7, 0x39, 0x18, 0x0f, 0x5d, 0xd6, 0xc7, ++ 0x4b, 0x30, 0x85, 0xce, 0xab, 0xc5, 0x4b, 0xef, 0x51, 0x5c, 0x85, 0xf1, ++ 0x6c, 0xf3, 0xd6, 0x98, 0x85, 0xfc, 0x15, 0xc6, 0x49, 0xba, 0xf1, 0x8f, ++ 0x36, 0x7e, 0xf7, 0x0a, 0xa3, 0x38, 0xa9, 0x4b, 0xff, 0xbc, 0x24, 0x2e, ++ 0x99, 0x1e, 0xc4, 0x7b, 0x96, 0xa0, 0xb9, 0x23, 0x32, 0xf4, 0xc5, 0x9f, ++ 0xb7, 0x91, 0x7e, 0x68, 0x71, 0x26, 0xf1, 0x6b, 0xc0, 0x40, 0xdf, 0x2b, ++ 0x55, 0x3d, 0xd1, 0xf4, 0xa8, 0x27, 0x6e, 0xe2, 0x7c, 0xe8, 0x89, 0xbb, ++ 0x6d, 0xa5, 0xd8, 0xce, 0x53, 0xdf, 0x0f, 0x38, 0x4c, 0x10, 0xc4, 0xf5, ++ 0x7b, 0xa2, 0xab, 0xf7, 0x31, 0x8a, 0xcb, 0x6e, 0x3f, 0x9c, 0x41, 0xf4, ++ 0xea, 0x39, 0xb7, 0x0a, 0xb6, 0x93, 0xbe, 0x3b, 0xdc, 0xb6, 0x32, 0x9a, ++ 0x77, 0xfb, 0xbb, 0xb6, 0xb5, 0x15, 0x09, 0xf9, 0x18, 0x67, 0x3f, 0x5c, ++ 0xaa, 0x7d, 0x1c, 0x8b, 0x07, 0x8c, 0xfd, 0xdc, 0x27, 0x2e, 0x35, 0xae, ++ 0xfa, 0x86, 0xfc, 0xdd, 0xe5, 0x3f, 0x17, 0x7f, 0xa7, 0xf8, 0x3f, 0x25, ++ 0xfb, 0x5d, 0xf1, 0x9a, 0xdc, 0x44, 0xf1, 0x21, 0xde, 0xe7, 0x1e, 0x8a, ++ 0x67, 0x53, 0xfd, 0x84, 0x66, 0x7f, 0xb5, 0x75, 0x8b, 0x54, 0x3e, 0x8f, ++ 0xb7, 0xbf, 0x57, 0x78, 0xfc, 0x82, 0xf9, 0x2f, 0xb7, 0xbf, 0x45, 0x6e, ++ 0x99, 0x8f, 0x9b, 0x11, 0x6d, 0xc8, 0xe5, 0x79, 0xf1, 0xb9, 0x35, 0xb9, ++ 0x72, 0xe6, 0xf8, 0xf5, 0xe7, 0x48, 0x4e, 0x53, 0x4e, 0xc5, 0xf8, 0xf5, ++ 0xb5, 0x78, 0x2d, 0x10, 0x54, 0x86, 0x6c, 0x94, 0xc7, 0x28, 0x66, 0xae, ++ 0x9f, 0x81, 0x35, 0x2c, 0xcc, 0xa8, 0xef, 0x63, 0x3c, 0xce, 0x0e, 0xac, ++ 0xb7, 0x84, 0xe9, 0xbd, 0x76, 0x9e, 0xf8, 0x1a, 0xc6, 0xc7, 0xad, 0x75, ++ 0xb2, 0xb0, 0x9d, 0x25, 0xe2, 0x3f, 0x2d, 0x3e, 0x1c, 0x7b, 0xbf, 0x08, ++ 0xdf, 0x97, 0x24, 0xe2, 0x45, 0x2d, 0x2e, 0x8c, 0xfb, 0x18, 0xcf, 0x83, ++ 0xd6, 0x28, 0x16, 0xfe, 0x7e, 0xde, 0x4c, 0x7f, 0x8e, 0xbb, 0x86, 0xee, ++ 0x67, 0xe7, 0xcf, 0x6b, 0x96, 0x8a, 0x75, 0xd1, 0x0e, 0x0c, 0x51, 0x7e, ++ 0xf4, 0xf0, 0xf7, 0x19, 0x70, 0x3b, 0xa0, 0xc6, 0x8b, 0x9a, 0x7c, 0xa6, ++ 0xc6, 0x93, 0x9f, 0x45, 0xe7, 0x4c, 0x85, 0x2f, 0x89, 0x2b, 0x5e, 0x56, ++ 0xe5, 0x52, 0xd3, 0xaf, 0x99, 0x29, 0x7a, 0xa1, 0xf9, 0xa9, 0x7a, 0xd5, ++ 0x4f, 0x77, 0x90, 0x9f, 0xae, 0x26, 0x3f, 0xfd, 0x85, 0x95, 0xf4, 0x60, ++ 0xa2, 0xb8, 0x1b, 0xfd, 0xf4, 0x5c, 0x37, 0x9f, 0x07, 0x7c, 0xfe, 0xa2, ++ 0x77, 0x25, 0x9f, 0x51, 0xde, 0x7d, 0x58, 0x5d, 0x77, 0xb1, 0xc6, 0xb7, ++ 0xf8, 0x09, 0x17, 0x9d, 0xb7, 0x18, 0xe2, 0xdb, 0x28, 0x5f, 0x9c, 0xc8, ++ 0x7f, 0xe6, 0x79, 0x4c, 0x3a, 0xbb, 0x90, 0xfa, 0xbe, 0x7e, 0x92, 0x7a, ++ 0xdc, 0xa2, 0xc6, 0x0b, 0xdf, 0x94, 0x1e, 0x37, 0xab, 0xf1, 0xd7, 0xff, ++ 0x75, 0x3d, 0x1e, 0x8b, 0xff, 0xac, 0xc6, 0xf7, 0xbc, 0xe9, 0x76, 0xfd, ++ 0x15, 0xc9, 0x6f, 0xba, 0xb9, 0x33, 0xee, 0x22, 0xbd, 0xfb, 0x17, 0xd4, ++ 0x3b, 0x79, 0xfc, 0xb8, 0x22, 0x2d, 0x9f, 0x94, 0x40, 0xc7, 0x9f, 0xa1, ++ 0x62, 0xab, 0x89, 0xf2, 0x9e, 0x40, 0xab, 0xc0, 0x01, 0x42, 0xd9, 0xf2, ++ 0x19, 0x9e, 0x9f, 0xbc, 0x65, 0x06, 0x5a, 0x67, 0xf3, 0xad, 0x42, 0x1e, ++ 0xa7, 0x3d, 0x76, 0x2b, 0x9b, 0xb7, 0xa1, 0x42, 0x10, 0x7e, 0xf4, 0xc9, ++ 0x12, 0x8e, 0xdb, 0x3c, 0xf6, 0xda, 0x59, 0x8b, 0x82, 0xf3, 0x9b, 0xb6, ++ 0xb2, 0x85, 0x84, 0x07, 0x35, 0xb5, 0xea, 0xef, 0x13, 0x9a, 0xae, 0x70, ++ 0x9c, 0x2d, 0x78, 0x84, 0xf1, 0x78, 0x39, 0x54, 0xd8, 0x7f, 0x92, 0xf4, ++ 0x2a, 0xb8, 0x6f, 0x8e, 0x4c, 0xeb, 0x37, 0xd3, 0x65, 0x09, 0x0f, 0x69, ++ 0xcd, 0x0e, 0xef, 0x20, 0xfc, 0x82, 0x70, 0x9c, 0x7b, 0xe9, 0x79, 0x7a, ++ 0x82, 0x0e, 0xb8, 0x4f, 0xbb, 0xfa, 0xfc, 0x7e, 0x15, 0xdf, 0x81, 0x94, ++ 0x38, 0xe0, 0xcd, 0xc1, 0x0b, 0x1c, 0xef, 0x09, 0x0c, 0x30, 0x20, 0xfd, ++ 0xb5, 0x46, 0xd1, 0x7e, 0x90, 0x3d, 0x39, 0x25, 0xf0, 0x8e, 0x8e, 0xa8, ++ 0xb0, 0x0b, 0x9f, 0x74, 0xd9, 0xb9, 0x3d, 0xf9, 0x44, 0x12, 0xf7, 0x08, ++ 0x74, 0xb1, 0xf0, 0x36, 0x96, 0x88, 0x23, 0xae, 0x44, 0x9f, 0xcb, 0x23, ++ 0x3d, 0x1b, 0x17, 0x4f, 0x28, 0x18, 0x4f, 0xe4, 0x25, 0xe2, 0x89, 0xf6, ++ 0x57, 0xde, 0xe5, 0xf6, 0x30, 0x35, 0x7e, 0xc8, 0x19, 0x10, 0xfb, 0x04, ++ 0xda, 0xcc, 0x61, 0xc2, 0x63, 0x86, 0x8a, 0x17, 0x33, 0xea, 0xb7, 0x63, ++ 0x3e, 0x98, 0x4f, 0x71, 0xa2, 0x2c, 0x3f, 0x54, 0x24, 0xce, 0x05, 0x61, ++ 0x6e, 0x57, 0x14, 0x1d, 0x4e, 0xb2, 0xf7, 0x2e, 0xe1, 0xf7, 0x3f, 0x3b, ++ 0xf5, 0x6f, 0x3c, 0x8f, 0x6c, 0x3a, 0xcc, 0x20, 0x97, 0xc7, 0x1d, 0x4a, ++ 0xbc, 0x34, 0x2f, 0x11, 0x77, 0x3c, 0x1a, 0x5a, 0xce, 0xfd, 0xbf, 0x16, ++ 0x67, 0x3c, 0x3a, 0xeb, 0xe4, 0x50, 0x11, 0xad, 0xa7, 0xc6, 0x19, 0x0e, ++ 0xfc, 0x25, 0xfc, 0x30, 0x35, 0xce, 0xe8, 0x88, 0x9c, 0xb5, 0x50, 0x5e, ++ 0x30, 0x2e, 0x9e, 0x48, 0x89, 0x23, 0x5e, 0x77, 0xeb, 0x71, 0xc1, 0x59, ++ 0x92, 0xc0, 0x59, 0x67, 0x45, 0x99, 0x83, 0xf0, 0xa4, 0x59, 0x2a, 0x3d, ++ 0xef, 0xeb, 0x4b, 0xe7, 0x71, 0x71, 0xfd, 0x87, 0x1b, 0x73, 0x49, 0xcf, ++ 0x35, 0xfe, 0x5c, 0x6b, 0x10, 0xfc, 0xba, 0x76, 0xe1, 0x73, 0x17, 0xcd, ++ 0x5b, 0xfc, 0xa1, 0xe4, 0x20, 0x7b, 0xfb, 0xe6, 0x85, 0xad, 0xbf, 0x29, ++ 0x12, 0x7d, 0xd9, 0x26, 0xd3, 0xbc, 0xad, 0x19, 0x94, 0x87, 0x5c, 0xfb, ++ 0xf0, 0x89, 0x0c, 0xa2, 0xe7, 0x9b, 0xd8, 0x02, 0xea, 0xeb, 0xa1, 0xf3, ++ 0x92, 0x21, 0x7e, 0x28, 0xab, 0xf6, 0x08, 0xfd, 0xdb, 0x3f, 0xbb, 0x39, ++ 0xfe, 0x2b, 0x17, 0x71, 0x5c, 0x47, 0x42, 0xff, 0x36, 0x25, 0x81, 0xbf, ++ 0xa4, 0xce, 0x7b, 0xc0, 0x23, 0xec, 0x41, 0x08, 0xd3, 0x0c, 0x8e, 0x3b, ++ 0x1e, 0x06, 0x2e, 0xbf, 0xa1, 0x42, 0xff, 0x72, 0xde, 0x7f, 0x71, 0x36, ++ 0xec, 0xe3, 0xb8, 0x8f, 0x90, 0xd7, 0x37, 0xa2, 0xd9, 0x0e, 0x8a, 0xf7, ++ 0xca, 0xf1, 0xb2, 0x5d, 0x68, 0x27, 0xfe, 0x2e, 0x1d, 0x7a, 0xec, 0x55, ++ 0x24, 0xcf, 0xfe, 0xb7, 0xb9, 0x7e, 0xbc, 0x68, 0xe2, 0xf2, 0x8b, 0xf3, ++ 0x83, 0x8c, 0xfa, 0x07, 0x64, 0xee, 0xef, 0x88, 0x64, 0xeb, 0x71, 0x7c, ++ 0xa5, 0x15, 0xcf, 0x52, 0x05, 0x62, 0x33, 0xd4, 0xb7, 0x7b, 0x54, 0xbe, ++ 0x15, 0x62, 0x1e, 0x4a, 0xf9, 0x20, 0x9e, 0x66, 0xcd, 0x1d, 0xa4, 0x53, ++ 0xf9, 0x8c, 0x53, 0x5f, 0x10, 0x1f, 0x2b, 0xd3, 0x41, 0xa2, 0xf5, 0x9f, ++ 0xb1, 0xf8, 0x77, 0xde, 0x8d, 0x53, 0x9e, 0x19, 0x94, 0x9c, 0xdb, 0x68, ++ 0x8e, 0xe4, 0xcc, 0x6d, 0xc0, 0x7b, 0x3d, 0x63, 0x17, 0x4b, 0x3d, 0x73, ++ 0x18, 0xe5, 0x15, 0xcf, 0x85, 0xd2, 0xcd, 0xcf, 0xd5, 0x51, 0x71, 0xf2, ++ 0x3c, 0xcd, 0x67, 0xb2, 0x03, 0xd6, 0xe3, 0xfc, 0x8e, 0x82, 0xcc, 0x18, ++ 0xe1, 0x67, 0x10, 0xb1, 0xfc, 0x7e, 0x4c, 0x2e, 0x51, 0x0e, 0x18, 0xed, ++ 0x53, 0x29, 0xe4, 0xed, 0xe3, 0xf9, 0x14, 0x1b, 0x2a, 0xec, 0x0e, 0x9a, ++ 0x9a, 0xb7, 0xeb, 0x64, 0x61, 0x17, 0xbe, 0xef, 0x03, 0xca, 0x83, 0x76, ++ 0x2c, 0xe9, 0x04, 0xca, 0x3b, 0x4f, 0xd6, 0x81, 0x1a, 0x07, 0xd9, 0x82, ++ 0x97, 0x71, 0xfc, 0x5a, 0x9c, 0x31, 0x15, 0x9f, 0x4f, 0x2f, 0xf4, 0x17, ++ 0x52, 0x5c, 0xd1, 0x5e, 0x30, 0x6c, 0x15, 0x71, 0xc5, 0x88, 0x95, 0xe2, ++ 0x8a, 0xb9, 0x2e, 0x6d, 0xbc, 0xc0, 0xed, 0x4c, 0x38, 0x9e, 0xec, 0xe5, ++ 0xce, 0xf9, 0xaf, 0x73, 0x79, 0x6b, 0xa2, 0xe7, 0x49, 0xfa, 0x0c, 0xc9, ++ 0xf8, 0x9e, 0x79, 0x7c, 0xbf, 0xc5, 0x3d, 0xd1, 0xfe, 0xb2, 0xc8, 0xe7, ++ 0x52, 0xf6, 0x5f, 0x94, 0xfd, 0x59, 0x1e, 0xcf, 0x5f, 0xfe, 0xeb, 0x8f, ++ 0x59, 0xdc, 0x9f, 0x45, 0x6f, 0x70, 0xbf, 0x73, 0x7d, 0x24, 0x0d, 0xe2, ++ 0x1c, 0xb7, 0x1b, 0x16, 0x38, 0x75, 0xd4, 0xc2, 0xf3, 0xf5, 0xeb, 0x98, ++ 0x07, 0x4d, 0x4f, 0xf2, 0x67, 0x3b, 0x5c, 0x82, 0x0e, 0xc7, 0xa2, 0x1e, ++ 0x2e, 0x8f, 0x03, 0xf1, 0xda, 0x0c, 0x1a, 0xff, 0x4b, 0x97, 0xd8, 0xaf, ++ 0xef, 0xdc, 0x9a, 0xd5, 0x0f, 0x92, 0x9c, 0xc4, 0x25, 0x67, 0x19, 0x3f, ++ 0xa5, 0xc8, 0x6b, 0x06, 0xe2, 0x52, 0x8d, 0x88, 0x0f, 0xc6, 0xd1, 0xa9, ++ 0xca, 0x6d, 0x70, 0x4e, 0x5b, 0xba, 0xb0, 0xe7, 0xa9, 0xf2, 0x79, 0xc9, ++ 0x2d, 0xe4, 0xfa, 0x12, 0xdd, 0x1b, 0xcf, 0xe1, 0xb9, 0x20, 0xf2, 0x95, ++ 0xc0, 0x56, 0x51, 0x3f, 0x70, 0xa8, 0xfa, 0x16, 0xe8, 0x64, 0xdc, 0xae, ++ 0x9c, 0x2c, 0xce, 0x63, 0x1a, 0x8e, 0x9c, 0x6f, 0x54, 0x5f, 0x38, 0x3c, ++ 0xc2, 0xed, 0x6c, 0xf3, 0x0f, 0x99, 0x33, 0x28, 0x4f, 0x5c, 0x5f, 0xd8, ++ 0xa5, 0xe6, 0x19, 0xa9, 0x76, 0xa8, 0x23, 0x72, 0x40, 0xf0, 0x2d, 0x15, ++ 0xb7, 0xf5, 0xd6, 0x73, 0xbb, 0x33, 0x59, 0xdc, 0x16, 0x28, 0x1b, 0x5e, ++ 0x9c, 0xb0, 0xd3, 0xdf, 0xf1, 0xa8, 0x76, 0x65, 0x81, 0xc0, 0x71, 0x4f, ++ 0xb8, 0x1d, 0xfc, 0xbe, 0x39, 0x9d, 0x0b, 0x5d, 0xf9, 0x90, 0xb8, 0xbf, ++ 0x01, 0x3d, 0xf7, 0x7b, 0x6a, 0xc6, 0xd3, 0xd3, 0x60, 0x5c, 0xb4, 0xd6, ++ 0x80, 0xee, 0x06, 0xe3, 0xfe, 0xf0, 0xc0, 0xe4, 0xd6, 0xab, 0x56, 0x26, ++ 0xb7, 0x9e, 0x6b, 0x92, 0xe3, 0x5a, 0x94, 0xc9, 0xed, 0x7b, 0x68, 0x92, ++ 0xeb, 0xed, 0x99, 0xe4, 0x7a, 0x4f, 0x1a, 0xe9, 0x2d, 0xb2, 0x5d, 0xc4, ++ 0x03, 0x0e, 0x21, 0x37, 0x75, 0xe6, 0xdb, 0x59, 0x24, 0xff, 0x4f, 0x1c, ++ 0x99, 0x93, 0xff, 0x65, 0xf1, 0xac, 0x19, 0x0d, 0xad, 0x9c, 0xc4, 0x7f, ++ 0x8b, 0x23, 0x1d, 0xe4, 0x24, 0xbf, 0xbf, 0x62, 0x7e, 0xae, 0xae, 0xff, ++ 0xa0, 0xb3, 0x48, 0x37, 0xfe, 0xa1, 0x25, 0x73, 0x74, 0xef, 0x1b, 0x94, ++ 0x72, 0xdd, 0xfb, 0xd5, 0xde, 0x6a, 0x5d, 0x7f, 0xad, 0xef, 0x7e, 0xdd, ++ 0xf8, 0x87, 0x1b, 0x3d, 0xba, 0x7e, 0x5a, 0xc1, 0x72, 0xdd, 0x78, 0xbb, ++ 0xbc, 0x4a, 0xd7, 0xcf, 0x98, 0xff, 0x88, 0x6e, 0x7c, 0x08, 0x75, 0x66, ++ 0x09, 0xda, 0xcf, 0x34, 0x6b, 0x66, 0x88, 0xa1, 0xfc, 0x4f, 0x71, 0xfe, ++ 0xa5, 0x6e, 0x7c, 0x7a, 0xb5, 0x3d, 0x93, 0xf4, 0x22, 0xb4, 0x30, 0x2d, ++ 0x46, 0xf2, 0x9e, 0xf6, 0xd6, 0xa6, 0x20, 0xbd, 0x7b, 0x9a, 0xfd, 0x64, ++ 0x24, 0x46, 0xd4, 0xcd, 0x3a, 0xd8, 0xc8, 0x50, 0x65, 0xa5, 0xec, 0x57, ++ 0x6c, 0xa4, 0x27, 0x2b, 0x97, 0x8a, 0xba, 0x40, 0x5f, 0xad, 0x2d, 0xbc, ++ 0x87, 0xe2, 0x9c, 0xbb, 0xb2, 0x2a, 0x69, 0xbe, 0x46, 0xaf, 0x7d, 0x75, ++ 0x22, 0xfe, 0x72, 0x54, 0x8c, 0x06, 0x73, 0x91, 0xce, 0x33, 0x95, 0x78, ++ 0x6d, 0x2e, 0xea, 0xf3, 0xf5, 0xa5, 0xc0, 0xf3, 0x87, 0xeb, 0x76, 0x51, ++ 0x1f, 0x00, 0xc9, 0x51, 0xd8, 0xc0, 0xf9, 0xe7, 0x28, 0x5c, 0x85, 0x76, ++ 0x3f, 0x64, 0x37, 0xae, 0x33, 0x35, 0xd6, 0xa9, 0x79, 0xf1, 0x04, 0xf6, ++ 0xe4, 0x74, 0x9d, 0xeb, 0x17, 0xa4, 0x2f, 0x0e, 0x8a, 0xcb, 0x0d, 0xf8, ++ 0xa8, 0xa8, 0x78, 0xbd, 0x23, 0x02, 0x1c, 0xb7, 0x01, 0x49, 0x2e, 0x5c, ++ 0xc5, 0xf7, 0x95, 0x0b, 0xc9, 0xdf, 0x4c, 0x3d, 0x21, 0x9e, 0x67, 0xc5, ++ 0x40, 0xd9, 0xc3, 0xcf, 0x25, 0x97, 0xac, 0xe2, 0x71, 0xb4, 0x5c, 0x42, ++ 0xe7, 0xdb, 0xa5, 0xd6, 0xbf, 0x72, 0x96, 0xcf, 0x2d, 0x21, 0xbc, 0x2e, ++ 0x07, 0xfd, 0x2e, 0xd5, 0x47, 0x9e, 0xa3, 0x3a, 0x09, 0xcf, 0x03, 0x1c, ++ 0x7c, 0x9c, 0xb6, 0x9f, 0xb3, 0x56, 0xec, 0xb7, 0xcb, 0x02, 0x8c, 0xea, ++ 0x59, 0xc1, 0xbb, 0x19, 0x8f, 0x53, 0xc1, 0x31, 0x55, 0x57, 0xdf, 0x38, ++ 0x6d, 0x89, 0x5d, 0x6e, 0x61, 0xbc, 0xbe, 0x71, 0x82, 0xce, 0xff, 0x8e, ++ 0x29, 0x56, 0xb1, 0xb7, 0x44, 0xf0, 0x85, 0xe8, 0x5b, 0x31, 0xe0, 0xe0, ++ 0x75, 0x97, 0x5f, 0x2f, 0xfd, 0xf9, 0x7c, 0x3f, 0xdf, 0x47, 0xd4, 0x3b, ++ 0xb6, 0x38, 0xc4, 0x90, 0xe3, 0x94, 0x6f, 0xe0, 0x39, 0xb6, 0x1c, 0xa9, ++ 0xe6, 0xf2, 0xdb, 0x74, 0x6c, 0xe9, 0x6f, 0xd7, 0x53, 0x5c, 0x58, 0x2a, ++ 0x71, 0x3a, 0x8f, 0x8b, 0xc7, 0xd5, 0x3c, 0xeb, 0xbc, 0x9a, 0x27, 0x6a, ++ 0x79, 0xd6, 0x30, 0xe5, 0x8b, 0x49, 0x79, 0xc7, 0x79, 0x8f, 0x69, 0x22, ++ 0xbb, 0x74, 0xde, 0x63, 0xa0, 0x57, 0xbb, 0x98, 0xc8, 0x83, 0x83, 0xef, ++ 0x88, 0x3c, 0xb8, 0xda, 0xea, 0x9c, 0xd3, 0x99, 0xc4, 0xa7, 0xcb, 0x6a, ++ 0x3c, 0xde, 0x12, 0x13, 0x78, 0xac, 0x96, 0xdf, 0x56, 0x2a, 0x61, 0x53, ++ 0x1e, 0xd2, 0xa1, 0xfa, 0x29, 0x73, 0x2c, 0x0d, 0xfd, 0x75, 0x75, 0xef, ++ 0x02, 0x2b, 0xd9, 0xed, 0xea, 0xde, 0xe2, 0x74, 0x8e, 0x2f, 0x6d, 0x3c, ++ 0x60, 0xd2, 0xe8, 0x6d, 0xc4, 0xf7, 0x6b, 0xea, 0x39, 0xfb, 0x4e, 0x8d, ++ 0xf0, 0xfa, 0xc4, 0x1b, 0x29, 0x75, 0x4a, 0x67, 0xad, 0x95, 0xbf, 0xff, ++ 0x5b, 0x55, 0x1e, 0x9d, 0xb5, 0xc0, 0xdb, 0x2d, 0x65, 0xd2, 0x0e, 0x72, ++ 0xc3, 0x53, 0xbf, 0xed, 0x30, 0x1b, 0xe1, 0xe3, 0xcd, 0x18, 0xff, 0xd3, ++ 0xf9, 0x5a, 0x42, 0xe2, 0xbc, 0x5a, 0x3d, 0xa4, 0x39, 0x26, 0x7b, 0x68, ++ 0x9f, 0x8b, 0x43, 0x23, 0xbd, 0xd4, 0x56, 0xb5, 0x96, 0x78, 0x38, 0x7e, ++ 0xd8, 0x36, 0xda, 0x4b, 0xfe, 0x33, 0x70, 0xfb, 0xc6, 0xc9, 0x07, 0x38, ++ 0x1e, 0x60, 0x95, 0x29, 0xbe, 0x4a, 0x5d, 0xf7, 0x50, 0x9d, 0x99, 0xcb, ++ 0xc5, 0x1b, 0x14, 0x90, 0x10, 0xbd, 0x96, 0x49, 0x61, 0x1a, 0x57, 0xbd, ++ 0x4c, 0xe2, 0xfc, 0xce, 0x69, 0xb6, 0xf3, 0x7c, 0x3c, 0xc7, 0x02, 0xe6, ++ 0x4c, 0xea, 0x37, 0x08, 0x7f, 0x56, 0xe5, 0x9d, 0xe6, 0xa1, 0x3e, 0xac, ++ 0xc9, 0xe6, 0xfe, 0xb8, 0xea, 0x94, 0x9c, 0xbd, 0xa9, 0x22, 0x91, 0xef, ++ 0xe7, 0x2c, 0xdb, 0x3a, 0x9d, 0xe8, 0xf4, 0x55, 0x75, 0x22, 0x0d, 0x37, ++ 0x98, 0x37, 0x53, 0x99, 0x4a, 0x7e, 0xe3, 0xeb, 0xd6, 0x89, 0xda, 0x4f, ++ 0x9f, 0xb3, 0xd2, 0xbd, 0x37, 0x0c, 0xeb, 0xeb, 0x44, 0x5a, 0xdd, 0x67, ++ 0xa2, 0x3a, 0x91, 0x56, 0xa7, 0x0d, 0x78, 0x3f, 0xd7, 0xd5, 0x95, 0x03, ++ 0xd2, 0x48, 0x3d, 0xe1, 0x2b, 0xd5, 0x47, 0x2e, 0xf2, 0x3a, 0x71, 0x20, ++ 0xc2, 0x1c, 0x05, 0x25, 0x89, 0xfa, 0x51, 0x60, 0x60, 0xd4, 0xca, 0xe9, ++ 0xab, 0xd6, 0x8d, 0x70, 0xbc, 0x95, 0xe6, 0x0d, 0x74, 0x8b, 0xfa, 0xd1, ++ 0x41, 0xdc, 0x9f, 0xda, 0x08, 0xde, 0x57, 0xc1, 0x73, 0xfc, 0x23, 0xde, ++ 0x97, 0xda, 0x28, 0xde, 0x97, 0x9e, 0x1f, 0xed, 0x9e, 0xcf, 0xdb, 0x58, ++ 0xb7, 0x93, 0xb7, 0xc7, 0xba, 0x97, 0xf0, 0xb6, 0x1a, 0xc5, 0xa6, 0x30, ++ 0x87, 0xea, 0x4e, 0xa3, 0xbc, 0xee, 0x54, 0x53, 0xab, 0xaf, 0x5b, 0x68, ++ 0x75, 0x09, 0x77, 0xa1, 0x6f, 0x49, 0x6d, 0x8d, 0xae, 0x6e, 0xc1, 0xfb, ++ 0xa9, 0x75, 0x0b, 0x73, 0xba, 0xc8, 0x47, 0x03, 0xa7, 0x2c, 0xce, 0xbd, ++ 0xf8, 0x3c, 0x70, 0xda, 0xc6, 0xed, 0xac, 0x2b, 0xda, 0x32, 0x8b, 0xe2, ++ 0xb2, 0x9b, 0x67, 0xfd, 0xb3, 0x1c, 0xbc, 0x0e, 0x90, 0xcb, 0xf3, 0xca, ++ 0x31, 0xf9, 0x55, 0x9c, 0xf6, 0x6c, 0xca, 0x07, 0x7c, 0x4e, 0x3b, 0xd5, ++ 0x0b, 0xaa, 0x07, 0xaf, 0x58, 0x65, 0x6e, 0x77, 0x62, 0x45, 0x50, 0x40, ++ 0xf8, 0x53, 0xdc, 0x4a, 0x79, 0x3f, 0xd1, 0x41, 0xe1, 0xf1, 0x9c, 0xcb, ++ 0x4e, 0x74, 0xfd, 0x4a, 0x7c, 0x3f, 0xf2, 0xff, 0xf8, 0xfe, 0xd7, 0xc1, ++ 0xf7, 0xa3, 0x75, 0x02, 0xdf, 0xd7, 0xec, 0x47, 0x95, 0xcf, 0xa4, 0xec, ++ 0xa1, 0xf6, 0x94, 0x62, 0xdf, 0x94, 0x64, 0x1f, 0xfa, 0x7c, 0x02, 0x27, ++ 0xee, 0x2b, 0x9d, 0xcd, 0xf5, 0xef, 0x79, 0xdf, 0xec, 0xec, 0x8d, 0xc9, ++ 0x78, 0xbe, 0x57, 0xe4, 0x71, 0x39, 0xcb, 0x4a, 0xed, 0xc9, 0xcf, 0x59, ++ 0xbd, 0x45, 0xc4, 0x7d, 0x0c, 0x7c, 0x46, 0x76, 0xac, 0xb7, 0x76, 0x42, ++ 0x7b, 0xdb, 0x6b, 0x1c, 0xdf, 0x19, 0xd7, 0x05, 0xfa, 0xbc, 0xc2, 0x8e, ++ 0x68, 0xb8, 0xff, 0xf8, 0x3a, 0x81, 0xf3, 0xad, 0xd2, 0x24, 0xbc, 0xff, ++ 0xda, 0x3b, 0x28, 0xa7, 0x98, 0xb7, 0x0e, 0x1e, 0x4e, 0xe3, 0xfe, 0xfc, ++ 0xe6, 0x91, 0xb4, 0xbd, 0x14, 0x7f, 0x57, 0x79, 0x37, 0xce, 0x9a, 0x82, ++ 0xfd, 0xaa, 0xf3, 0x69, 0x50, 0x22, 0xfc, 0x91, 0xae, 0xbe, 0xd0, 0xe4, ++ 0x35, 0x29, 0xf6, 0x2c, 0xa3, 0x7a, 0x82, 0x52, 0x64, 0x42, 0xb9, 0x1d, ++ 0x57, 0x37, 0xf0, 0x9a, 0xb8, 0x7d, 0x1f, 0xab, 0x1b, 0x78, 0xa5, 0x8b, ++ 0xbc, 0xaf, 0xc6, 0xe9, 0x1b, 0x46, 0x7f, 0x37, 0xa5, 0x84, 0x11, 0xfd, ++ 0xc3, 0x21, 0xca, 0x33, 0xde, 0x68, 0x67, 0xce, 0x41, 0x18, 0x5f, 0x47, ++ 0xc0, 0x85, 0x8b, 0x60, 0x09, 0xde, 0xc2, 0x7b, 0x8e, 0xd7, 0x95, 0x9d, ++ 0x9d, 0xcc, 0x29, 0xcb, 0x5f, 0x5d, 0x5f, 0xc8, 0x53, 0x71, 0x86, 0x8e, ++ 0x48, 0xb6, 0x99, 0xe4, 0xbc, 0xf9, 0x04, 0x40, 0x2e, 0x33, 0xaa, 0x33, ++ 0x78, 0x79, 0xbc, 0x5f, 0x05, 0xcf, 0x86, 0x6a, 0xe9, 0x7b, 0xac, 0x52, ++ 0x93, 0x83, 0xfc, 0x59, 0x2a, 0x5e, 0x40, 0x72, 0x42, 0xfe, 0x3f, 0x15, ++ 0x27, 0x8c, 0xaa, 0x7c, 0x8c, 0xd6, 0x0a, 0x7f, 0x53, 0xe7, 0x11, 0xfe, ++ 0xa6, 0x4a, 0x8d, 0x4b, 0xb4, 0x79, 0xa9, 0xfc, 0xcf, 0x56, 0xfd, 0xd3, ++ 0x44, 0xb8, 0x23, 0x53, 0xe3, 0x9f, 0x1e, 0x6f, 0x55, 0x1f, 0xf1, 0x2f, ++ 0xb8, 0xd2, 0x04, 0xe4, 0x07, 0x7a, 0xbc, 0x6e, 0x5b, 0x69, 0xd2, 0x7a, ++ 0x67, 0x6a, 0xc5, 0x77, 0x4b, 0xbb, 0xa8, 0x6e, 0x31, 0x2d, 0xb9, 0x6e, ++ 0x21, 0xea, 0x13, 0xa9, 0xf5, 0x0a, 0xcd, 0x4e, 0x55, 0x0f, 0x7e, 0x51, ++ 0x4f, 0xfc, 0x7f, 0x3e, 0x2a, 0xf0, 0xa4, 0x40, 0x81, 0xc0, 0x37, 0xab, ++ 0x8f, 0xba, 0x4e, 0x91, 0xde, 0x27, 0xce, 0x29, 0xee, 0xf7, 0x3c, 0xf2, ++ 0x38, 0xce, 0xe3, 0x28, 0x67, 0x36, 0x88, 0x7b, 0x81, 0x4d, 0xe0, 0x5e, ++ 0x1c, 0x67, 0xa8, 0x5a, 0xf9, 0xf9, 0xb1, 0x0c, 0xa2, 0x9f, 0x0f, 0xfd, ++ 0x15, 0xd9, 0xa5, 0xd3, 0xa5, 0x3b, 0x32, 0xc9, 0x9e, 0xac, 0x94, 0x6a, ++ 0x98, 0xcc, 0xf1, 0xee, 0x31, 0xfc, 0x9b, 0xf0, 0xa9, 0xd5, 0x67, 0x5a, ++ 0x97, 0x03, 0xf9, 0xff, 0xb5, 0x0b, 0xcf, 0x12, 0xdd, 0xd7, 0xae, 0xb7, ++ 0xf0, 0xef, 0x90, 0x34, 0x7f, 0xb5, 0xfa, 0x4c, 0x63, 0xbd, 0x78, 0xbf, ++ 0x67, 0x7b, 0x3a, 0xbd, 0x9f, 0xcf, 0x9c, 0x76, 0x99, 0x9e, 0x7b, 0xdd, ++ 0xf4, 0x7c, 0xc5, 0xaf, 0x62, 0x84, 0xf4, 0xc1, 0x83, 0x74, 0x7b, 0xd4, ++ 0x9b, 0xf8, 0xe9, 0xcb, 0x12, 0xe9, 0xcb, 0xbc, 0x99, 0xfe, 0xeb, 0xa4, ++ 0x3f, 0xd5, 0x0d, 0x2a, 0x0e, 0xbe, 0x5e, 0xf8, 0xd7, 0xb5, 0xd1, 0x06, ++ 0x0b, 0x64, 0x8e, 0xf7, 0x77, 0xc7, 0x8b, 0x6f, 0xf2, 0x3c, 0xfa, 0x46, ++ 0xb4, 0x9a, 0xe3, 0xdb, 0xb9, 0x54, 0x7f, 0xad, 0x48, 0xf8, 0x8b, 0xea, ++ 0x23, 0xe8, 0x87, 0xa6, 0xfc, 0xe9, 0xfc, 0x50, 0x76, 0x9d, 0xc8, 0x07, ++ 0xef, 0x45, 0x3f, 0x44, 0xe7, 0xc9, 0x69, 0x10, 0x75, 0xc2, 0x54, 0xfe, ++ 0x9f, 0x51, 0xe3, 0xc9, 0x89, 0xfc, 0xca, 0x44, 0x76, 0x94, 0xfc, 0x88, ++ 0x69, 0x89, 0xd0, 0x1b, 0x56, 0x90, 0xf0, 0xbf, 0x32, 0xe5, 0xd7, 0xf7, ++ 0x25, 0xfc, 0xb0, 0x23, 0x82, 0xfd, 0xfc, 0x2f, 0xc1, 0xbd, 0x55, 0xb9, ++ 0xce, 0x9e, 0x20, 0x0e, 0x73, 0xab, 0xf2, 0x3b, 0xe1, 0xf7, 0x1b, 0x91, ++ 0x6f, 0x06, 0x07, 0xff, 0x8b, 0xba, 0x3f, 0x8f, 0x7a, 0x96, 0x96, 0xe7, ++ 0x68, 0x78, 0xb8, 0x96, 0x17, 0xbd, 0xa8, 0xd2, 0x59, 0x6b, 0x5f, 0x52, ++ 0xdb, 0x54, 0xbc, 0x4c, 0xc3, 0xc9, 0xf2, 0x15, 0x80, 0xae, 0x2f, 0xc1, ++ 0xc9, 0xf2, 0x09, 0x47, 0xcb, 0x21, 0xb3, 0x5d, 0xc1, 0x71, 0xbb, 0x42, ++ 0xf5, 0x0c, 0x63, 0xb8, 0x59, 0x2c, 0xc7, 0x74, 0xa7, 0x1c, 0xc7, 0xa9, ++ 0xb8, 0x9d, 0x86, 0x9f, 0xe5, 0x6d, 0xe8, 0x67, 0x14, 0x67, 0x14, 0x43, ++ 0x70, 0x1b, 0xd9, 0x97, 0x21, 0x2b, 0xb8, 0x0e, 0x4c, 0xa3, 0xef, 0xf6, ++ 0x18, 0x6c, 0x23, 0xfd, 0x0e, 0x37, 0xf0, 0x38, 0x67, 0xe8, 0xa5, 0xf7, ++ 0x7b, 0x7f, 0x41, 0xdf, 0x1b, 0x0e, 0x30, 0x07, 0xb9, 0x9f, 0xf6, 0xfe, ++ 0xb3, 0xdc, 0x4f, 0xb7, 0x63, 0x5c, 0xc3, 0xe3, 0xa1, 0xe8, 0xa7, 0x02, ++ 0xa7, 0xea, 0x17, 0xdf, 0x9b, 0xb6, 0x47, 0x98, 0x62, 0x84, 0x83, 0x0e, ++ 0xaa, 0xfe, 0xb9, 0x56, 0x01, 0x6e, 0x37, 0xda, 0xd5, 0xef, 0xfa, 0xea, ++ 0x07, 0x84, 0x5e, 0x27, 0x70, 0xa2, 0x1f, 0x49, 0xc9, 0x38, 0x51, 0x40, ++ 0x8e, 0x4f, 0xd7, 0xbe, 0x17, 0x0c, 0x0b, 0xff, 0x64, 0xf8, 0x5d, 0x5f, ++ 0x07, 0x8c, 0xf0, 0xef, 0x01, 0x3b, 0x5a, 0x99, 0x33, 0x86, 0xcf, 0x53, ++ 0x71, 0xa3, 0x54, 0xbc, 0xe8, 0x59, 0xf5, 0x3b, 0xc0, 0x09, 0x71, 0x23, ++ 0xe5, 0xeb, 0x7d, 0xef, 0xb7, 0xbd, 0x6e, 0xec, 0x7b, 0x3f, 0x8e, 0x3f, ++ 0xef, 0xf3, 0x08, 0xbb, 0xd0, 0xe8, 0x67, 0x8c, 0xd6, 0xb7, 0x99, 0x7c, ++ 0x6d, 0xfc, 0xbb, 0xdf, 0xa3, 0xcc, 0x61, 0xf4, 0xfd, 0xe8, 0x6e, 0x55, ++ 0xee, 0x57, 0xa8, 0xf8, 0xed, 0xab, 0x56, 0x21, 0x0f, 0xaf, 0x7e, 0x8b, ++ 0x85, 0x29, 0x9e, 0x5b, 0x01, 0x02, 0xa7, 0x7d, 0xf5, 0x68, 0x0b, 0xc7, ++ 0x6f, 0x5f, 0xad, 0x62, 0x4e, 0x13, 0xdd, 0x53, 0xc5, 0x6b, 0x97, 0xab, ++ 0xf4, 0xb8, 0x3b, 0x81, 0xd7, 0x3e, 0x4f, 0x78, 0xed, 0xf7, 0xd0, 0x9d, ++ 0x10, 0x4e, 0xbb, 0x42, 0xe5, 0x3f, 0x40, 0x98, 0x9f, 0xab, 0x61, 0x77, ++ 0x7a, 0x8c, 0xe2, 0x8d, 0x67, 0x2c, 0xfd, 0x05, 0xa4, 0x8f, 0xda, 0xf7, ++ 0x46, 0x5e, 0x15, 0x47, 0x4d, 0x4f, 0x83, 0x4e, 0x23, 0xfd, 0xec, 0xa9, ++ 0x73, 0x79, 0xeb, 0x6a, 0x68, 0xdc, 0x84, 0xf1, 0xce, 0x2b, 0x75, 0x06, ++ 0xf8, 0xce, 0x55, 0x8f, 0x58, 0xf7, 0x97, 0x75, 0x18, 0xa7, 0xcf, 0x07, ++ 0xa3, 0x38, 0x7d, 0x7f, 0xdd, 0x74, 0x5d, 0x9c, 0xce, 0xfb, 0xa9, 0x71, ++ 0xfa, 0x9f, 0x0a, 0xaf, 0xf5, 0xd0, 0x3d, 0x8d, 0xcf, 0xff, 0xdf, 0x93, ++ 0xc4, 0xed, 0x1e, 0xaf, 0x9d, 0xdc, 0xb8, 0x4d, 0x75, 0x06, 0xf1, 0xdf, ++ 0x0e, 0x15, 0x3f, 0x49, 0xa5, 0x6f, 0x66, 0xbd, 0x66, 0x87, 0x67, 0x38, ++ 0xb8, 0x3c, 0x8d, 0x9d, 0x1f, 0x44, 0x3d, 0x57, 0xc5, 0xbd, 0x86, 0x54, ++ 0x3f, 0x17, 0x62, 0xf2, 0x6f, 0xef, 0xe7, 0xf5, 0x2f, 0x0b, 0xaf, 0x7f, ++ 0x69, 0x76, 0x26, 0x34, 0x45, 0xac, 0xff, 0x81, 0x6a, 0x5f, 0xb4, 0xf6, ++ 0xa6, 0xda, 0x86, 0x2c, 0xc6, 0x38, 0x0d, 0xab, 0x17, 0x7e, 0xea, 0xdb, ++ 0x85, 0xca, 0xfb, 0xc4, 0xc7, 0xf2, 0xd7, 0xf4, 0xb8, 0xd9, 0x82, 0x7e, ++ 0x3d, 0x6e, 0x76, 0x6f, 0x24, 0x47, 0xd7, 0x5f, 0x18, 0xbb, 0x4b, 0x37, ++ 0xbe, 0xfa, 0xd4, 0x6c, 0xdd, 0xfb, 0x9a, 0xf8, 0x3d, 0xba, 0xf7, 0xf7, ++ 0x9d, 0xaf, 0xd2, 0xf5, 0x97, 0x0e, 0x7f, 0x4b, 0x37, 0xfe, 0xfe, 0x4f, ++ 0xdc, 0xba, 0xfe, 0x77, 0x46, 0xf4, 0xb8, 0xd9, 0x03, 0xb7, 0xf4, 0xb8, ++ 0x99, 0x26, 0xdf, 0x2e, 0x94, 0x88, 0xe4, 0x79, 0x1e, 0xdb, 0x0f, 0x74, ++ 0xe3, 0x8a, 0x5a, 0xf5, 0xf7, 0x2a, 0xee, 0xd4, 0xdf, 0x6b, 0x56, 0x97, ++ 0xfe, 0x5e, 0xda, 0xba, 0x25, 0x41, 0xfd, 0xfd, 0xe6, 0x84, 0xf4, 0xf7, ++ 0xcb, 0x21, 0x5c, 0xbf, 0xe2, 0x7f, 0x8f, 0xeb, 0xff, 0x4d, 0xad, 0xcc, ++ 0xe9, 0x7f, 0x2c, 0x3a, 0xc7, 0x4e, 0xf3, 0x76, 0x79, 0x4b, 0xed, 0x14, ++ 0xc7, 0x4c, 0x2f, 0x14, 0xf2, 0xaa, 0x8d, 0xfb, 0x1f, 0xac, 0x27, 0xe8, ++ 0xd9, 0x70, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 csem_int_table_data_e1h[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xe3, 0x14, ++ 0x60, 0x60, 0xf8, 0x51, 0x0f, 0xc1, 0xd3, 0xf9, 0x19, 0x18, 0x36, 0xf3, ++ 0x23, 0xf8, 0xf4, 0xc0, 0xc7, 0x98, 0x19, 0x18, 0x8e, 0x83, 0x30, 0x23, ++ 0x03, 0xc3, 0x3e, 0x20, 0xde, 0x0a, 0xc4, 0x6b, 0x80, 0xf8, 0x3d, 0x03, ++ 0x03, 0xc3, 0x52, 0x20, 0x3d, 0x07, 0x88, 0x27, 0x03, 0x71, 0x17, 0x10, ++ 0xbf, 0x04, 0x8a, 0xd5, 0xb1, 0x62, 0x37, 0x87, 0x85, 0x8d, 0x81, 0x81, ++ 0x0d, 0x88, 0x4f, 0x02, 0xcd, 0x3a, 0xc5, 0x4c, 0xbc, 0xfd, 0x8a, 0x7c, ++ 0x08, 0xf6, 0x21, 0x5e, 0x06, 0x86, 0xb5, 0x40, 0x7c, 0x94, 0x97, 0xbe, ++ 0x61, 0x30, 0xd8, 0xf0, 0x0c, 0x41, 0xfa, 0xd9, 0xf5, 0x0c, 0x6a, 0xd7, ++ 0x6e, 0xd1, 0x81, 0xf7, 0x37, 0x08, 0xb3, 0x8a, 0x33, 0x30, 0x30, 0x4a, ++ 0x20, 0xf8, 0xfd, 0x12, 0xa8, 0xf2, 0x6c, 0xe2, 0x08, 0x76, 0x96, 0x0c, ++ 0x65, 0x76, 0x95, 0x01, 0xf5, 0x03, 0x00, 0x29, 0x51, 0x28, 0x15, 0x80, ++ 0x03, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 csem_pram_data_e1h[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d, ++ 0x09, 0x78, 0x54, 0x45, 0xb6, 0x70, 0xdd, 0xee, 0x7b, 0x7b, 0x49, 0xba, ++ 0x3b, 0x9d, 0x90, 0x95, 0x25, 0x74, 0x80, 0x20, 0x2a, 0x4b, 0xcb, 0x12, ++ 0x01, 0x11, 0x3b, 0x21, 0x89, 0x01, 0x03, 0x06, 0x44, 0x09, 0x28, 0xd2, ++ 0x6c, 0x21, 0x84, 0x24, 0x9d, 0x01, 0x66, 0x1e, 0x3e, 0xfd, 0xff, 0x6e, ++ 0x08, 0x42, 0xc4, 0xd1, 0x89, 0x8a, 0x1a, 0xfc, 0x19, 0x5f, 0x83, 0xe0, ++ 0x04, 0x07, 0x9d, 0xe0, 0xa0, 0x13, 0x9d, 0xc0, 0x34, 0x8b, 0x88, 0x33, ++ 0xe8, 0x04, 0xc7, 0x05, 0x97, 0x79, 0x5f, 0x40, 0x1e, 0x20, 0x42, 0x12, ++ 0xa3, 0x38, 0xe8, 0xf3, 0xc9, 0xab, 0x73, 0xaa, 0x6e, 0xba, 0xeb, 0x76, ++ 0x37, 0x69, 0xb7, 0xff, 0xf9, 0x7f, 0xff, 0x84, 0x0f, 0x8a, 0xba, 0x55, ++ 0xf7, 0xd4, 0xa9, 0xb3, 0xd5, 0xa9, 0x53, 0x75, 0x4f, 0x14, 0x92, 0x42, ++ 0x92, 0xfa, 0x13, 0x72, 0x09, 0x7e, 0x6e, 0x20, 0xe4, 0x55, 0x85, 0x10, ++ 0xfa, 0xa8, 0xbb, 0xec, 0x90, 0x3a, 0x87, 0xcb, 0x03, 0x83, 0xed, 0x6b, ++ 0xbd, 0x2e, 0xe2, 0x32, 0x12, 0xf2, 0x80, 0xd7, 0x84, 0xe5, 0x7a, 0x6f, ++ 0x3a, 0x71, 0x5d, 0x41, 0x9f, 0x8f, 0xd6, 0x15, 0xf9, 0x2d, 0x84, 0xdc, ++ 0xef, 0xb5, 0xe3, 0xf3, 0xc7, 0xbd, 0x25, 0x58, 0x3e, 0xea, 0x2d, 0xc5, ++ 0xf2, 0x11, 0xaf, 0x1b, 0xfb, 0x3d, 0xe4, 0x2d, 0xc7, 0xf2, 0x57, 0xde, ++ 0x1a, 0x2c, 0xef, 0xf5, 0x16, 0x61, 0x7b, 0x9d, 0x77, 0x15, 0xd6, 0x6f, ++ 0x54, 0x16, 0xa4, 0xc1, 0xb8, 0x84, 0xb8, 0x4c, 0x59, 0xc9, 0x84, 0x78, ++ 0x5e, 0x1e, 0x38, 0x72, 0x03, 0xad, 0xad, 0xcf, 0x1c, 0x9f, 0x20, 0x8f, ++ 0xa6, 0xf5, 0xbf, 0xea, 0x89, 0x3e, 0x8b, 0xbe, 0x37, 0x5a, 0x2e, 0xf2, ++ 0x0f, 0xa5, 0x0d, 0x72, 0x49, 0x51, 0xd6, 0xe8, 0x60, 0x3f, 0x15, 0xcf, ++ 0x1b, 0x95, 0xbc, 0xbe, 0x00, 0xe7, 0xf1, 0xb1, 0x3a, 0xd6, 0xcf, 0x54, ++ 0xf3, 0x5a, 0x76, 0xe4, 0x7e, 0x59, 0x64, 0x0c, 0xc5, 0x73, 0xac, 0x8c, ++ 0xf8, 0x13, 0x4b, 0xc9, 0xe4, 0xec, 0xe4, 0x88, 0xfd, 0x06, 0x03, 0xbc, ++ 0x47, 0x86, 0xb2, 0x79, 0x12, 0xbb, 0xf3, 0xb5, 0x41, 0x91, 0xe1, 0x5d, ++ 0x0d, 0xf0, 0x1e, 0x1a, 0xca, 0xf1, 0x4b, 0xb6, 0x4f, 0x1e, 0x14, 0x19, ++ 0x9e, 0x13, 0xfa, 0xfd, 0xca, 0xc9, 0xe1, 0xa5, 0x77, 0x1e, 0x1e, 0x18, ++ 0xb9, 0xdf, 0x18, 0xe8, 0x57, 0xe7, 0xe4, 0xf0, 0xfa, 0xfa, 0x4c, 0x03, ++ 0x22, 0x8f, 0x3b, 0x1e, 0xfa, 0xc5, 0xc0, 0x27, 0x8a, 0x13, 0x21, 0xbe, ++ 0x16, 0xa3, 0x3f, 0x3b, 0xeb, 0xfb, 0xf3, 0x8b, 0xb8, 0xe8, 0x5f, 0x8a, ++ 0x4f, 0xc7, 0x5e, 0xf3, 0xd6, 0x0d, 0x12, 0xf2, 0x6f, 0x1a, 0xd0, 0x69, ++ 0xad, 0x7d, 0xf9, 0x99, 0x2d, 0x74, 0x9c, 0xf6, 0x96, 0x61, 0x4e, 0xbd, ++ 0x83, 0x90, 0xcf, 0x5c, 0xce, 0x04, 0xbb, 0x25, 0x26, 0xbe, 0xdd, 0x02, ++ 0xf3, 0x88, 0x81, 0x6f, 0xa5, 0x30, 0x4e, 0x0c, 0x7c, 0x9b, 0x1b, 0x23, ++ 0xdf, 0x16, 0x40, 0xbf, 0x18, 0xf8, 0xb6, 0x04, 0xfa, 0xc5, 0xc0, 0xb7, ++ 0xca, 0x18, 0xf9, 0xf6, 0xb3, 0x9f, 0x08, 0xdf, 0xee, 0x05, 0x3c, 0xbe, ++ 0x07, 0xdf, 0x36, 0xc4, 0xa8, 0x6f, 0xbf, 0x8a, 0x91, 0x6f, 0x1b, 0x63, ++ 0xe4, 0xdb, 0xa6, 0x18, 0xf5, 0xed, 0xc9, 0x18, 0xf9, 0xf6, 0x54, 0x28, ++ 0xdf, 0xd4, 0xe7, 0x6a, 0xb9, 0x83, 0x48, 0x68, 0x17, 0x6f, 0x54, 0x4a, ++ 0x76, 0x40, 0x3f, 0x4f, 0x66, 0x9b, 0x6d, 0x40, 0xd6, 0x4f, 0x82, 0x7f, ++ 0x7b, 0xbe, 0xa7, 0xde, 0xed, 0x8f, 0x91, 0x7f, 0xaf, 0xc6, 0xc8, 0xbf, ++ 0x23, 0x40, 0x9f, 0x18, 0xf8, 0x77, 0x34, 0x46, 0xfe, 0xbd, 0x13, 0x23, ++ 0xff, 0x3e, 0x88, 0x51, 0xef, 0xda, 0x70, 0x9d, 0xb1, 0xc8, 0x5f, 0xb5, ++ 0x0d, 0x21, 0xf8, 0x73, 0x69, 0x00, 0xfc, 0x6b, 0xb1, 0x9f, 0xba, 0x9a, ++ 0xd7, 0xf5, 0x80, 0x77, 0x12, 0x21, 0x19, 0xe1, 0x72, 0xa0, 0x96, 0x94, ++ 0xa3, 0x28, 0x0f, 0x32, 0x71, 0xb7, 0xb3, 0x75, 0xab, 0xe0, 0x9b, 0x4b, ++ 0x39, 0x84, 0xac, 0x30, 0xd1, 0xff, 0xd2, 0xf7, 0x7d, 0x79, 0x24, 0xa0, ++ 0xa7, 0xe3, 0xfb, 0x6c, 0xc4, 0x5f, 0x2b, 0x09, 0xfd, 0x3f, 0x07, 0x3c, ++ 0x09, 0xc9, 0xff, 0xe6, 0x52, 0xaa, 0xd0, 0xdf, 0xa7, 0x8b, 0xd8, 0x9f, ++ 0xe8, 0xa0, 0xfd, 0x61, 0x90, 0x2b, 0xca, 0xff, 0xcd, 0xde, 0x21, 0x58, ++ 0xd6, 0x73, 0x39, 0xda, 0x5c, 0xa4, 0x43, 0x79, 0xf0, 0x25, 0x1b, 0x50, ++ 0xbe, 0x9e, 0xf0, 0x3a, 0xb1, 0xbd, 0xc1, 0x3b, 0x16, 0xcb, 0xc7, 0xb8, ++ 0x5c, 0x6e, 0xe4, 0x72, 0xf4, 0x00, 0xc8, 0xdd, 0x15, 0x20, 0x87, 0xa5, ++ 0x5c, 0xae, 0x98, 0xdc, 0x11, 0x52, 0xe2, 0x28, 0xa7, 0x74, 0xed, 0xd8, ++ 0x13, 0x4f, 0x36, 0x38, 0x50, 0xae, 0xcc, 0x12, 0xe0, 0x29, 0x33, 0x79, ++ 0xbb, 0x77, 0xcf, 0x95, 0x5b, 0x37, 0x50, 0xf8, 0x9b, 0x6b, 0x74, 0x57, ++ 0x6e, 0x0b, 0x91, 0xb3, 0x27, 0x8a, 0x54, 0xf9, 0xa2, 0x92, 0x99, 0x1c, ++ 0xec, 0xf7, 0x44, 0xf9, 0x09, 0xdb, 0x82, 0xa1, 0x48, 0x6f, 0x1b, 0xc0, ++ 0x69, 0x28, 0xd6, 0xa9, 0xfd, 0x7c, 0xa1, 0xfd, 0x1a, 0xdc, 0xdd, 0xfd, ++ 0x7a, 0x41, 0xbf, 0xc7, 0x8a, 0xb9, 0x7c, 0xc9, 0x24, 0x10, 0x3a, 0xee, ++ 0x63, 0xa5, 0xdd, 0xfd, 0xd2, 0x25, 0x4a, 0x97, 0x7b, 0x25, 0x52, 0xda, ++ 0x64, 0x09, 0xe7, 0xcb, 0x14, 0x89, 0xe9, 0x29, 0x55, 0x14, 0xe4, 0x87, ++ 0xcc, 0xe9, 0xbb, 0x3f, 0xef, 0x2c, 0x69, 0xa3, 0xef, 0xdb, 0xec, 0x23, ++ 0xd3, 0x08, 0x2d, 0x9f, 0x04, 0xfd, 0x44, 0xfd, 0x73, 0x60, 0xa9, 0xbe, ++ 0x5f, 0x4f, 0xe9, 0xec, 0xa6, 0xf4, 0xc8, 0x34, 0x92, 0x9a, 0x26, 0xc0, ++ 0x97, 0xb4, 0x4a, 0x0a, 0xc5, 0x57, 0x1e, 0xeb, 0x48, 0x04, 0x39, 0x7a, ++ 0x68, 0x9c, 0x8b, 0x48, 0x56, 0x42, 0xfa, 0x43, 0x3b, 0x1d, 0xbf, 0xcf, ++ 0xe8, 0x36, 0x92, 0x45, 0xcb, 0xc4, 0xf1, 0x6d, 0x44, 0x1a, 0x06, 0xfd, ++ 0x68, 0x3b, 0xad, 0xa7, 0xf0, 0xf6, 0x8c, 0xa1, 0xb4, 0x9d, 0xc2, 0x79, ++ 0x08, 0xda, 0xad, 0xc1, 0xf6, 0x54, 0xde, 0x9e, 0xe6, 0xe0, 0xef, 0x5f, ++ 0xc7, 0xda, 0x1f, 0xf6, 0x12, 0x1c, 0x5f, 0xed, 0x77, 0x1f, 0xe5, 0xb3, ++ 0x9b, 0xe2, 0xb7, 0x8e, 0xe2, 0x8b, 0xcf, 0x8b, 0x89, 0x0b, 0xe8, 0x28, ++ 0x53, 0x76, 0xfa, 0x43, 0xe6, 0x3f, 0x5b, 0xd2, 0xe3, 0xbc, 0x2b, 0x79, ++ 0xa9, 0xe2, 0x7f, 0x5f, 0xf6, 0xa9, 0x8c, 0xf9, 0x43, 0x83, 0xf8, 0x9a, ++ 0x07, 0x5f, 0xcc, 0x98, 0x1f, 0x82, 0xdf, 0x7d, 0x83, 0xe7, 0x60, 0x5d, ++ 0xc5, 0xc7, 0x7c, 0x45, 0x25, 0xd6, 0xfb, 0xaf, 0xea, 0x4d, 0x3d, 0x31, ++ 0xae, 0x0f, 0x24, 0x9c, 0xce, 0xa9, 0x33, 0x07, 0x08, 0xed, 0x0e, 0xd9, ++ 0x89, 0x7e, 0x9a, 0xe3, 0x88, 0x9e, 0xf8, 0x28, 0xbf, 0x1c, 0x54, 0x3c, ++ 0x23, 0xf1, 0xe7, 0x0b, 0x2a, 0xce, 0x3f, 0xa8, 0xfe, 0xb9, 0x18, 0x3d, ++ 0xb4, 0xed, 0x77, 0x6b, 0xe8, 0xb0, 0x2e, 0x43, 0xa4, 0x83, 0xa1, 0xb7, ++ 0x48, 0x87, 0x75, 0xbd, 0x45, 0x3a, 0x18, 0xfa, 0x5c, 0x9e, 0x0e, 0x53, ++ 0x24, 0x07, 0xc2, 0x8f, 0x46, 0x0f, 0x75, 0xdc, 0x0d, 0x57, 0x8a, 0xe3, ++ 0xc6, 0x5d, 0x25, 0x8e, 0xbb, 0xe1, 0x2a, 0x71, 0xdc, 0xb8, 0xab, 0x7f, ++ 0x98, 0x71, 0xd7, 0xf7, 0x13, 0xc7, 0x35, 0x66, 0x8a, 0xe3, 0xae, 0xcf, ++ 0x14, 0xc7, 0x35, 0xf6, 0xff, 0x7e, 0xe3, 0x12, 0xd9, 0x49, 0x1f, 0x32, ++ 0x73, 0x41, 0x1c, 0xf0, 0xcf, 0x3c, 0xc1, 0xbe, 0x5d, 0x20, 0xee, 0x87, ++ 0x41, 0xbf, 0xc1, 0xce, 0xe9, 0x93, 0x83, 0x76, 0x4e, 0xb6, 0x97, 0x10, ++ 0xb7, 0x25, 0xc8, 0x4f, 0x22, 0xd3, 0x97, 0x73, 0x42, 0xe1, 0xdc, 0x29, ++ 0xd8, 0x55, 0x0a, 0xe7, 0xff, 0x70, 0x38, 0xae, 0xcb, 0xc3, 0xb1, 0x6b, ++ 0xe0, 0xcc, 0xd5, 0xc2, 0xd9, 0xc6, 0xe1, 0x90, 0x50, 0x3b, 0x1d, 0x06, ++ 0x87, 0xdc, 0xa1, 0x9d, 0xc7, 0x6f, 0xf9, 0x7b, 0x01, 0x5d, 0xc8, 0xf8, ++ 0x74, 0x7d, 0x25, 0x25, 0xd6, 0xd0, 0xf7, 0x9c, 0x9a, 0xf1, 0x6f, 0xd7, ++ 0x8e, 0xbf, 0x1b, 0xec, 0x18, 0xcc, 0x43, 0x77, 0xd9, 0xf1, 0x1d, 0x1a, ++ 0xba, 0xce, 0xd1, 0xe2, 0xb3, 0x87, 0xc3, 0x21, 0xba, 0xcb, 0xd1, 0x83, ++ 0xd8, 0x35, 0x70, 0x66, 0x6b, 0xe1, 0x1c, 0xe2, 0x70, 0x02, 0xd2, 0x65, ++ 0xe1, 0x94, 0x6a, 0xe7, 0xf1, 0xba, 0xca, 0x57, 0x49, 0x58, 0xbf, 0x28, ++ 0x3d, 0x86, 0x05, 0xdf, 0xeb, 0xc8, 0xeb, 0x3c, 0x85, 0x7e, 0xd0, 0x8b, ++ 0x8a, 0x63, 0x3b, 0x6d, 0x97, 0xfe, 0x64, 0x0d, 0xdc, 0x40, 0xfb, 0x1f, ++ 0xd9, 0x22, 0xf9, 0x8d, 0xb4, 0x1e, 0xd8, 0x1b, 0x8f, 0xeb, 0xc7, 0xf9, ++ 0x6d, 0xd3, 0xb1, 0xbe, 0xef, 0x1a, 0x23, 0xae, 0x13, 0xe7, 0x9d, 0x93, ++ 0xfd, 0x46, 0x6a, 0x4f, 0x26, 0xbd, 0xf0, 0xb6, 0x0d, 0xec, 0x4b, 0xd5, ++ 0x0b, 0x7a, 0x19, 0xea, 0xba, 0xbd, 0x1f, 0xdb, 0xda, 0x28, 0x5e, 0x1e, ++ 0x63, 0xeb, 0x83, 0xd7, 0xd1, 0xe7, 0x9d, 0x2f, 0xe8, 0xc9, 0x56, 0x94, ++ 0xc6, 0x42, 0x1d, 0xd0, 0xfd, 0x14, 0x97, 0x4d, 0xb2, 0x8a, 0xd5, 0xcb, ++ 0xcc, 0xac, 0x5a, 0xb5, 0x65, 0xdf, 0x9d, 0x00, 0xb7, 0xbc, 0xd9, 0x48, ++ 0xcc, 0x14, 0x4e, 0xd5, 0x4b, 0x4b, 0xa6, 0x5d, 0x47, 0xeb, 0x4b, 0x0e, ++ 0x2b, 0x04, 0xba, 0x54, 0x6d, 0x5f, 0x6d, 0xe8, 0x4d, 0xeb, 0x4b, 0xfd, ++ 0x52, 0x13, 0xd4, 0x3b, 0xf2, 0x48, 0x39, 0xe8, 0xd3, 0x9a, 0xbd, 0xff, ++ 0xd9, 0x0e, 0xeb, 0xd1, 0xf9, 0xdd, 0x4a, 0x36, 0x8c, 0x7f, 0x96, 0xae, ++ 0x13, 0x0e, 0x6a, 0x8f, 0x8f, 0x58, 0x5b, 0x53, 0x67, 0x52, 0x3c, 0x2a, ++ 0xfc, 0xbb, 0x0a, 0xe1, 0xbd, 0x8a, 0x9d, 0x92, 0x93, 0x5a, 0x38, 0x8a, ++ 0xef, 0xf6, 0x43, 0x19, 0x80, 0xef, 0x0e, 0xc9, 0x69, 0xa4, 0xf4, 0x5e, ++ 0xd6, 0x18, 0x4f, 0x1c, 0xaa, 0xbd, 0xa3, 0x7f, 0x4f, 0xed, 0xd6, 0xe3, ++ 0xfc, 0x97, 0xd3, 0xf9, 0x13, 0x0a, 0x6f, 0x09, 0xa9, 0x2f, 0x04, 0x7a, ++ 0x56, 0x01, 0x71, 0x60, 0x7c, 0xa7, 0xd1, 0x6f, 0x96, 0x82, 0xfa, 0x76, ++ 0xd6, 0x7b, 0x18, 0xc7, 0x53, 0xeb, 0x55, 0x3b, 0xe8, 0x78, 0xf4, 0xfd, ++ 0xea, 0xe7, 0x24, 0x27, 0x4c, 0xb5, 0x5a, 0x47, 0xdc, 0x80, 0x67, 0xfb, ++ 0x4b, 0xe6, 0xd2, 0xa7, 0x2c, 0x30, 0xcf, 0xd5, 0x86, 0xc1, 0x56, 0x98, ++ 0xdf, 0x7a, 0x03, 0xf4, 0x5b, 0xe2, 0x9f, 0xff, 0xa2, 0xd9, 0x01, 0x78, ++ 0x6e, 0x31, 0x14, 0x02, 0xbe, 0x9b, 0xb7, 0x18, 0xca, 0x86, 0x02, 0xfd, ++ 0xc8, 0xbc, 0x92, 0xa1, 0x80, 0xdf, 0x5f, 0x44, 0xfc, 0x1a, 0xf4, 0x2e, ++ 0x98, 0xef, 0xf2, 0x6b, 0x8c, 0x5b, 0xf5, 0xc0, 0x4f, 0x4b, 0x60, 0xd0, ++ 0x0c, 0x6b, 0xb8, 0x9d, 0x3d, 0x4b, 0xd7, 0x2b, 0x47, 0xc8, 0xfa, 0x59, ++ 0x41, 0x98, 0xdd, 0x27, 0xb2, 0xdf, 0x30, 0x7d, 0x58, 0xf0, 0xf9, 0x4b, ++ 0xfa, 0x44, 0x94, 0x83, 0x65, 0x8d, 0x7a, 0xe2, 0x08, 0xb5, 0x1b, 0x5c, ++ 0x3e, 0x7c, 0x47, 0x09, 0xf3, 0x63, 0xf6, 0x58, 0xfd, 0xdb, 0xb3, 0x82, ++ 0x7c, 0x5c, 0x6e, 0xe7, 0xf2, 0xca, 0xf9, 0xb8, 0x3c, 0x91, 0xf3, 0x55, ++ 0xee, 0xcc, 0x99, 0x31, 0x2c, 0x1c, 0x9f, 0x07, 0x81, 0x2f, 0x46, 0xe6, ++ 0x1f, 0x41, 0xf9, 0x30, 0x5d, 0x37, 0x1d, 0xe8, 0xff, 0x38, 0x90, 0x7e, ++ 0x8f, 0x51, 0xff, 0xc9, 0x81, 0xfe, 0x91, 0x13, 0x9f, 0x3f, 0x41, 0xfd, ++ 0x24, 0x28, 0x37, 0x53, 0x3f, 0x09, 0xca, 0x27, 0xa9, 0x9f, 0x04, 0xa5, ++ 0x9f, 0xfa, 0x49, 0xd0, 0x6f, 0x2b, 0xf5, 0x93, 0xa0, 0xdc, 0x46, 0xfd, ++ 0x24, 0x78, 0xfe, 0x34, 0xf5, 0xcf, 0xa1, 0x6c, 0xa4, 0xfe, 0x39, 0x3c, ++ 0x7f, 0x86, 0xfa, 0xe5, 0x50, 0xee, 0xf4, 0xfa, 0xf0, 0xf9, 0x73, 0xde, ++ 0x3a, 0x2c, 0x9b, 0xbc, 0xf5, 0x58, 0x3e, 0xef, 0x6d, 0xc0, 0x72, 0xb7, ++ 0xd7, 0x8f, 0xfd, 0x5e, 0xf4, 0x36, 0x62, 0xd9, 0xec, 0x6d, 0xc2, 0xe7, ++ 0x2f, 0x7b, 0x9b, 0xb1, 0x6c, 0xf1, 0x06, 0xb0, 0xdc, 0x0b, 0x7c, 0xa6, ++ 0x65, 0xc0, 0xdb, 0x8a, 0xe5, 0x7e, 0xef, 0x31, 0x2c, 0x0f, 0x7a, 0xdb, ++ 0xf0, 0xbd, 0x43, 0xde, 0x33, 0x58, 0xfe, 0x92, 0xd3, 0xdd, 0x36, 0x81, ++ 0xe4, 0xca, 0x54, 0x5e, 0x6c, 0x2e, 0x62, 0x07, 0x36, 0x25, 0x15, 0xbb, ++ 0x72, 0xc1, 0x5f, 0x49, 0x2a, 0x61, 0xf5, 0xd4, 0x3b, 0x7c, 0xb9, 0x06, ++ 0x5a, 0x4f, 0x75, 0xd3, 0x3a, 0xa5, 0x63, 0xef, 0xca, 0x40, 0xae, 0x91, ++ 0xd6, 0x7b, 0xd7, 0xb0, 0xf6, 0xcc, 0x7b, 0x48, 0x9e, 0x89, 0xd6, 0x33, ++ 0x7d, 0xac, 0x7d, 0xc0, 0x2f, 0x5d, 0x79, 0x66, 0x5a, 0x1f, 0x50, 0xcf, ++ 0xda, 0x07, 0x6f, 0xf6, 0xe5, 0xc5, 0xd1, 0xfa, 0x60, 0x3f, 0x6b, 0xbf, ++ 0x6a, 0x67, 0x20, 0x2f, 0x9e, 0xd6, 0xaf, 0x6a, 0x62, 0xed, 0xc3, 0x5b, ++ 0xc8, 0x24, 0x0b, 0xad, 0x0f, 0x0f, 0xb0, 0xfa, 0xc8, 0x23, 0xae, 0x49, ++ 0x56, 0x5a, 0x1f, 0xd9, 0xca, 0xea, 0x39, 0x1f, 0xfa, 0x26, 0xd9, 0x68, ++ 0x3d, 0xa7, 0x8d, 0xbd, 0x3f, 0xfe, 0x5c, 0x60, 0x52, 0x02, 0xad, 0x8f, ++ 0xef, 0x64, 0xed, 0x13, 0xbf, 0x26, 0xf9, 0x76, 0x5a, 0x9f, 0x48, 0x24, ++ 0xac, 0xe7, 0x59, 0x72, 0xf3, 0x13, 0x69, 0x3d, 0xcf, 0xce, 0xea, 0x85, ++ 0x7d, 0xe7, 0xcb, 0x8e, 0x08, 0xeb, 0xfb, 0x5e, 0xa5, 0x6d, 0x21, 0x98, ++ 0xb4, 0x9f, 0xeb, 0x72, 0x72, 0x65, 0xea, 0x27, 0xec, 0x35, 0xb4, 0xad, ++ 0x00, 0x93, 0xbb, 0x5e, 0x77, 0x43, 0xae, 0x3c, 0x8e, 0xd2, 0x4f, 0x21, ++ 0x8b, 0xa0, 0x7d, 0x93, 0xae, 0x88, 0xd5, 0x0d, 0x64, 0x25, 0xb4, 0xff, ++ 0x56, 0x37, 0x1d, 0xeb, 0xfb, 0x15, 0x07, 0xb6, 0xef, 0xd1, 0xcd, 0x61, ++ 0x75, 0x83, 0x03, 0xdb, 0xff, 0xaa, 0x5b, 0x88, 0xf5, 0x83, 0x8a, 0x0b, ++ 0xdb, 0x8f, 0xeb, 0x2a, 0x59, 0xdd, 0xe0, 0xc2, 0xf6, 0xcf, 0x74, 0x3f, ++ 0xc7, 0xf1, 0x0e, 0x29, 0x6e, 0x6c, 0x57, 0xf4, 0xff, 0x9b, 0xd5, 0x0d, ++ 0x6e, 0x6c, 0x7f, 0x58, 0x5e, 0x9f, 0x9b, 0x4f, 0xfb, 0x57, 0xea, 0xdd, ++ 0x1e, 0x1d, 0x95, 0xeb, 0x5a, 0xc9, 0x5d, 0x4e, 0x06, 0x82, 0xbc, 0x36, ++ 0xa5, 0x83, 0x3d, 0x5c, 0xc7, 0xfd, 0xd6, 0x59, 0x3a, 0x07, 0xca, 0xfd, ++ 0xba, 0x0c, 0x03, 0xea, 0xd9, 0xde, 0xff, 0xca, 0x79, 0x0a, 0xf5, 0x0c, ++ 0x7e, 0x92, 0xa1, 0x5e, 0xf6, 0x34, 0xf8, 0xbd, 0x14, 0xce, 0x2a, 0x84, ++ 0xa3, 0x50, 0x38, 0xfa, 0x9e, 0xe1, 0x4c, 0xfc, 0x66, 0xac, 0x00, 0x67, ++ 0xe2, 0x37, 0xe5, 0x2a, 0x9c, 0xd5, 0x08, 0xc7, 0x1c, 0x1b, 0x9c, 0xbd, ++ 0xdf, 0x8c, 0x17, 0xf1, 0xf9, 0xa6, 0x42, 0x85, 0xb3, 0x41, 0x47, 0xed, ++ 0x7d, 0xad, 0x35, 0xb6, 0x79, 0x4d, 0xbc, 0x34, 0x41, 0xc4, 0xe7, 0x52, ++ 0xa5, 0x0a, 0xe7, 0x11, 0xc4, 0x27, 0x31, 0x36, 0x7c, 0x02, 0xca, 0xb5, ++ 0x02, 0x9c, 0x80, 0xb2, 0x44, 0x85, 0xb3, 0x19, 0xe1, 0xa4, 0xc4, 0x86, ++ 0x8f, 0xcb, 0x30, 0x4e, 0x80, 0xe3, 0x32, 0x2c, 0x55, 0xe1, 0x6c, 0x47, ++ 0x38, 0x19, 0xb1, 0xc1, 0x09, 0x18, 0xae, 0x13, 0xf1, 0x31, 0x2c, 0x53, ++ 0xe1, 0x3c, 0x87, 0xf4, 0xe9, 0x17, 0xdb, 0xbc, 0x5c, 0xc6, 0xeb, 0x45, ++ 0x7c, 0x8c, 0x55, 0x2a, 0x9c, 0x3f, 0x20, 0x3e, 0x59, 0xb1, 0xc1, 0xd9, ++ 0x6f, 0x15, 0xe9, 0xb3, 0xdf, 0xda, 0x4d, 0x9f, 0x00, 0xc2, 0xc9, 0x8e, ++ 0x6d, 0x5e, 0x79, 0x36, 0x91, 0x3e, 0x79, 0xb6, 0x6e, 0xfa, 0xbc, 0x86, ++ 0x70, 0xae, 0x8c, 0x0d, 0xce, 0x7e, 0x9b, 0x48, 0x9f, 0xfd, 0xb6, 0x6e, ++ 0xfa, 0xbc, 0x89, 0x70, 0x86, 0xc5, 0x36, 0xaf, 0xbc, 0x04, 0x91, 0x3e, ++ 0x79, 0x09, 0xdd, 0xf4, 0xf9, 0x00, 0xe1, 0x5c, 0x13, 0x1b, 0x3e, 0x07, ++ 0x53, 0x44, 0xfa, 0x1c, 0x4c, 0xe9, 0xa6, 0xcf, 0x49, 0x84, 0x33, 0x26, ++ 0x36, 0x7c, 0xf2, 0x53, 0x45, 0xfa, 0xe4, 0xa7, 0x76, 0xd3, 0xe7, 0x3c, ++ 0xc2, 0x19, 0x17, 0x1b, 0x9c, 0x83, 0xa9, 0x22, 0x7d, 0x0e, 0xa6, 0x76, ++ 0xd3, 0xe7, 0x0b, 0x84, 0x73, 0x7d, 0x6c, 0xf3, 0xca, 0x4f, 0x13, 0xe9, ++ 0x93, 0x9f, 0xd6, 0x4d, 0x9f, 0x4b, 0x08, 0x27, 0xd7, 0xdd, 0x88, 0xf8, ++ 0x10, 0x0a, 0xc7, 0x1a, 0x1d, 0xce, 0xa1, 0x7e, 0x22, 0x7d, 0x0e, 0xf5, ++ 0xeb, 0xa6, 0x8f, 0x49, 0x0f, 0x70, 0x0a, 0x28, 0x9c, 0x81, 0x3d, 0xc3, ++ 0x29, 0xcc, 0x14, 0xe9, 0x53, 0x98, 0xd9, 0x4d, 0x9f, 0x44, 0x3d, 0xe8, ++ 0xc5, 0xe4, 0xd8, 0xe0, 0x1c, 0xca, 0x14, 0xe9, 0x73, 0x28, 0xb3, 0x9b, ++ 0x3e, 0xbd, 0x11, 0x9f, 0xa9, 0xb1, 0xcd, 0xab, 0xb0, 0xbf, 0x48, 0x9f, ++ 0xc2, 0xfe, 0x8c, 0x3e, 0x1e, 0x63, 0xe7, 0x24, 0x3b, 0xf8, 0x8d, 0x89, ++ 0xc4, 0xb9, 0x95, 0xbe, 0x32, 0x29, 0xf9, 0x67, 0x07, 0x61, 0xdd, 0x51, ++ 0x2c, 0xc4, 0x09, 0x60, 0x8f, 0x48, 0x81, 0x6d, 0x00, 0x9f, 0xae, 0xad, ++ 0xe8, 0x97, 0xca, 0x4e, 0xd5, 0x0f, 0x72, 0x12, 0xf0, 0x73, 0x8b, 0x6d, ++ 0x0e, 0x27, 0xc4, 0x03, 0xf4, 0xaa, 0xbf, 0x43, 0x5a, 0x71, 0x3f, 0x62, ++ 0xd9, 0x99, 0x28, 0xc4, 0x9b, 0x5e, 0xd2, 0xe7, 0x0d, 0x07, 0x7c, 0xad, ++ 0xd4, 0x2b, 0x0c, 0xf5, 0x7b, 0x12, 0xc6, 0xc6, 0x09, 0xfe, 0x56, 0xa2, ++ 0x2b, 0x49, 0xa8, 0xf7, 0x2a, 0xea, 0x2d, 0xf4, 0x4f, 0x29, 0x19, 0x20, ++ 0xb4, 0xa7, 0x95, 0x5e, 0x25, 0xb4, 0x67, 0xb8, 0x47, 0x0a, 0xf5, 0x3e, ++ 0xe5, 0xe3, 0x85, 0xfe, 0xfd, 0x6a, 0xf2, 0x84, 0x7a, 0xff, 0x55, 0x53, ++ 0x84, 0xfe, 0x59, 0xbe, 0x19, 0x42, 0x7d, 0x60, 0xdd, 0x1c, 0xa1, 0x7f, ++ 0x76, 0xfd, 0x02, 0xa1, 0xfd, 0x8a, 0x86, 0x0a, 0xa1, 0xfd, 0x4a, 0xff, ++ 0x72, 0xa1, 0x7e, 0x75, 0xe3, 0xbf, 0x0a, 0xfd, 0x87, 0x35, 0xad, 0x11, ++ 0xda, 0x47, 0x34, 0x6f, 0x10, 0xda, 0xaf, 0x09, 0x3c, 0x2c, 0xd4, 0x47, ++ 0x1d, 0x7e, 0x42, 0xe8, 0x3f, 0xa6, 0x75, 0xab, 0xd0, 0x7e, 0xed, 0xb1, ++ 0x67, 0x84, 0xf6, 0x71, 0x6d, 0xcf, 0x0b, 0xf5, 0xeb, 0xce, 0xbc, 0x2c, ++ 0xf4, 0xbf, 0xbe, 0x73, 0xbf, 0x50, 0xbf, 0xe1, 0xe2, 0x9f, 0x85, 0xfe, ++ 0xb9, 0xe4, 0x6f, 0x42, 0x7d, 0x92, 0xe9, 0x03, 0xa1, 0x7f, 0x81, 0xfd, ++ 0x23, 0xa1, 0xfd, 0xc6, 0xf4, 0x4f, 0x34, 0x7e, 0xac, 0x18, 0xbf, 0xa8, ++ 0xcd, 0x25, 0xcc, 0x9f, 0xcd, 0x30, 0xa0, 0x3f, 0x1b, 0xb0, 0x1a, 0xb0, ++ 0x6e, 0xd8, 0x6b, 0x66, 0xfb, 0x1b, 0xa8, 0x27, 0x43, 0x1c, 0xa2, 0x18, ++ 0xeb, 0x86, 0xfd, 0x0b, 0x1d, 0xc9, 0x10, 0x0f, 0x00, 0x00, 0xd4, 0x9f, ++ 0xc8, 0xed, 0x5d, 0x7e, 0x05, 0xc4, 0xab, 0x7e, 0x31, 0xde, 0x7d, 0x05, ++ 0xc4, 0x71, 0x7f, 0x61, 0x70, 0x8f, 0xb0, 0x47, 0xf0, 0x83, 0xda, 0x65, ++ 0xf7, 0x3d, 0x7a, 0x8c, 0x27, 0xb6, 0x4a, 0x24, 0x1d, 0x4a, 0x87, 0x0e, ++ 0xca, 0x38, 0x3d, 0x8f, 0x27, 0x18, 0x99, 0xfc, 0xae, 0xcf, 0xca, 0x79, ++ 0xca, 0x17, 0xa2, 0x07, 0x75, 0xfd, 0xa8, 0x7f, 0x41, 0xeb, 0xeb, 0xf5, ++ 0x14, 0x8f, 0x31, 0x41, 0xfd, 0x59, 0xdf, 0xaf, 0x2c, 0x7d, 0x7e, 0xc8, ++ 0x38, 0xeb, 0xfa, 0x19, 0x4a, 0xb7, 0x0e, 0x65, 0xcf, 0x17, 0x5a, 0x60, ++ 0xbc, 0x92, 0xfb, 0x60, 0x3c, 0x8f, 0xa1, 0x73, 0x30, 0xe0, 0xa5, 0x1d, ++ 0xc7, 0x38, 0x60, 0xac, 0x30, 0x8e, 0x29, 0xb3, 0x1c, 0xc7, 0xd9, 0x08, ++ 0xe3, 0xa4, 0x04, 0xc7, 0x31, 0x66, 0x96, 0x6b, 0xc6, 0x31, 0x95, 0x6e, ++ 0xe5, 0xcf, 0xf9, 0x38, 0x8f, 0x81, 0xde, 0x44, 0x1b, 0x67, 0xfd, 0x80, ++ 0xf1, 0xe2, 0x7c, 0x32, 0x2b, 0x70, 0x9c, 0x2d, 0x9a, 0x71, 0xd6, 0x67, ++ 0x56, 0x68, 0xc6, 0x89, 0x63, 0xf3, 0xa1, 0xcf, 0xf9, 0x38, 0x4f, 0x5d, ++ 0x6e, 0x1c, 0xe3, 0xc0, 0x09, 0xe2, 0x7c, 0xfa, 0x57, 0xe2, 0x38, 0xcf, ++ 0x69, 0xe7, 0xd3, 0xbf, 0x52, 0x33, 0x8e, 0x05, 0xc7, 0x81, 0xe7, 0x30, ++ 0x0e, 0xe9, 0x4b, 0x77, 0x31, 0x69, 0x94, 0xcf, 0xc6, 0xce, 0x32, 0x94, ++ 0x83, 0x3f, 0x99, 0x31, 0x4e, 0x66, 0xe8, 0x53, 0xf1, 0x1b, 0xa8, 0x93, ++ 0x0f, 0xcc, 0x24, 0x1b, 0xc6, 0x71, 0xd0, 0x71, 0x69, 0x3f, 0x32, 0x24, ++ 0x89, 0x0a, 0x35, 0x21, 0xff, 0xa2, 0x4f, 0x42, 0xfe, 0x7c, 0x11, 0x47, ++ 0xf9, 0x1f, 0x12, 0x4f, 0x0b, 0xee, 0xc7, 0x7d, 0xb8, 0xaf, 0x5f, 0xcc, ++ 0x51, 0x24, 0x7e, 0x8a, 0x11, 0xdd, 0x27, 0x55, 0x73, 0xd9, 0x5c, 0xb4, ++ 0x73, 0x7a, 0xe6, 0x0a, 0x07, 0x2d, 0x9b, 0x0f, 0x0c, 0x7a, 0x04, 0xc6, ++ 0xd9, 0x68, 0x75, 0x66, 0xd3, 0x7a, 0x7b, 0xf3, 0x24, 0xc3, 0xc2, 0x08, ++ 0xf2, 0xb4, 0xb8, 0x5e, 0x39, 0xd5, 0x16, 0x22, 0xe7, 0xdd, 0xfb, 0xb3, ++ 0x3c, 0x32, 0xa4, 0x86, 0x8e, 0xbf, 0x22, 0xce, 0x8e, 0xf8, 0xa8, 0x75, ++ 0xb5, 0x4c, 0xd2, 0x89, 0xcf, 0x4f, 0xd0, 0x7d, 0x17, 0xa1, 0xfb, 0x93, ++ 0x0f, 0xe9, 0x3e, 0x85, 0xd0, 0xfd, 0xca, 0x47, 0x0a, 0xdb, 0x67, 0xfe, ++ 0x3b, 0xdd, 0x9f, 0x41, 0xbd, 0x8d, 0xee, 0xcf, 0xa0, 0x9d, 0x90, 0xd5, ++ 0xf8, 0xde, 0x09, 0x1e, 0x67, 0x3e, 0xf1, 0x4b, 0xc9, 0x0f, 0xf4, 0xfe, ++ 0xe2, 0xae, 0x9f, 0x29, 0xb8, 0x4e, 0xf8, 0xc8, 0x5b, 0xe9, 0xa9, 0x10, ++ 0x4d, 0x60, 0x3f, 0xf3, 0x56, 0xc5, 0x53, 0x26, 0x04, 0xf1, 0x9b, 0xef, ++ 0xeb, 0x25, 0xd4, 0xa9, 0x39, 0xee, 0xa3, 0x4b, 0xc7, 0x7d, 0x2d, 0xc6, ++ 0x0f, 0x3a, 0x5f, 0x32, 0xfa, 0xb7, 0x02, 0x5d, 0xeb, 0xfa, 0x50, 0x9a, ++ 0xf2, 0x7e, 0x03, 0x08, 0x79, 0x77, 0xef, 0xd4, 0x43, 0x92, 0x0d, 0xab, ++ 0x7d, 0x74, 0x63, 0x09, 0x99, 0x59, 0x33, 0xbd, 0x20, 0x0d, 0xb5, 0x48, ++ 0xea, 0xb7, 0x9c, 0xe2, 0x39, 0x63, 0xf7, 0x35, 0x0a, 0x7d, 0x83, 0xb4, ++ 0x2b, 0x6d, 0x77, 0x3a, 0x2d, 0x41, 0xb8, 0xc4, 0xa5, 0x9c, 0x00, 0xfa, ++ 0x98, 0xe8, 0x1f, 0x80, 0x73, 0x4b, 0x11, 0xad, 0x87, 0x8c, 0x7f, 0x6b, ++ 0x89, 0x58, 0x9f, 0x45, 0xe4, 0x60, 0x9d, 0xf2, 0xfb, 0xa4, 0x7e, 0x00, ++ 0x61, 0xf1, 0x7f, 0x3e, 0xae, 0xc3, 0xa5, 0x00, 0x5f, 0x4b, 0xe8, 0x1c, ++ 0x33, 0x28, 0xab, 0x67, 0x41, 0x39, 0x12, 0x9a, 0x59, 0xbc, 0xa6, 0xd4, ++ 0xce, 0xde, 0x55, 0xf1, 0xf1, 0x2c, 0x54, 0x48, 0x00, 0xf7, 0xd7, 0xbe, ++ 0x14, 0x88, 0x63, 0x13, 0x5f, 0x32, 0xf6, 0x9b, 0xa3, 0xee, 0x93, 0x35, ++ 0xf8, 0x95, 0x2a, 0x26, 0x57, 0x09, 0xa5, 0x6b, 0xe9, 0x7c, 0x3d, 0xd2, ++ 0x55, 0x8b, 0xef, 0xfb, 0x7b, 0xe3, 0x5d, 0xba, 0xe1, 0xb4, 0xac, 0x7b, ++ 0x44, 0x81, 0xd0, 0x6c, 0x4f, 0xf8, 0xcf, 0x76, 0x8b, 0xed, 0xa4, 0x9c, ++ 0x8d, 0xa7, 0xd2, 0x55, 0x95, 0x97, 0x53, 0x9c, 0xbf, 0x27, 0x80, 0xff, ++ 0xb4, 0x3c, 0x0d, 0xfc, 0xa7, 0x78, 0x9f, 0xe4, 0xfc, 0x0f, 0xca, 0x31, ++ 0xe3, 0xbf, 0xc7, 0xe8, 0x9e, 0x06, 0xfc, 0xef, 0xdc, 0xa4, 0x27, 0xc8, ++ 0x2f, 0xce, 0xf7, 0xdb, 0x38, 0xdf, 0x17, 0xd7, 0x8b, 0x7c, 0xbf, 0x0d, ++ 0xce, 0xe3, 0x68, 0xff, 0xdb, 0x56, 0x66, 0xb1, 0x78, 0x53, 0x43, 0x2f, ++ 0x81, 0xbf, 0x74, 0xe2, 0x22, 0x1d, 0xea, 0x1f, 0x2a, 0xa0, 0x66, 0x35, ++ 0x0c, 0xff, 0xbf, 0x73, 0x39, 0x98, 0x53, 0xb7, 0xeb, 0x15, 0x60, 0xef, ++ 0xed, 0xe5, 0x9a, 0xf9, 0x71, 0x3e, 0xdc, 0xc9, 0xf9, 0x30, 0x57, 0x43, ++ 0x8f, 0xdb, 0x38, 0xdf, 0xe6, 0x72, 0xbe, 0x2d, 0x21, 0xbe, 0x7b, 0x33, ++ 0x30, 0x7e, 0xe1, 0x57, 0x20, 0xae, 0x37, 0xbb, 0x5c, 0x22, 0x60, 0x2f, ++ 0x3c, 0x77, 0xab, 0x7c, 0x6b, 0x13, 0xf8, 0xe6, 0x56, 0xf9, 0xa6, 0xc1, ++ 0xf7, 0x4e, 0xce, 0xb7, 0x3b, 0xef, 0x62, 0x7c, 0xd3, 0xe2, 0xdd, 0xc6, ++ 0xf9, 0xd6, 0xd6, 0xf0, 0x99, 0x42, 0x06, 0x84, 0xe3, 0xad, 0xc5, 0x73, ++ 0xde, 0x2a, 0xcd, 0xbc, 0x7c, 0x5a, 0xbe, 0xd5, 0x73, 0xb9, 0xb4, 0x1b, ++ 0xc0, 0x9f, 0x9a, 0xee, 0xca, 0x5d, 0x71, 0x32, 0xa4, 0xff, 0x2d, 0x45, ++ 0x93, 0x57, 0x9c, 0x0c, 0xb1, 0x0b, 0xb7, 0x96, 0x4c, 0x17, 0xea, 0xb3, ++ 0x4a, 0x67, 0x0b, 0xfd, 0x67, 0xbb, 0xe7, 0x0b, 0xed, 0xb7, 0x97, 0x2f, ++ 0x15, 0xda, 0xe7, 0xd6, 0xfc, 0x4c, 0xa8, 0xcf, 0x5b, 0x75, 0x97, 0xd0, ++ 0x7f, 0xbe, 0x6f, 0xb5, 0xd0, 0xbe, 0xb0, 0xee, 0x3e, 0xa1, 0x7d, 0x71, ++ 0xfd, 0x43, 0x42, 0x7d, 0x49, 0xc3, 0x26, 0xa1, 0xff, 0x52, 0xff, 0x16, ++ 0xa1, 0x7d, 0x59, 0xe3, 0x0e, 0xa1, 0xbd, 0xaa, 0x69, 0x97, 0x50, 0xf7, ++ 0x34, 0xbf, 0x24, 0xf4, 0xd7, 0xed, 0xbd, 0xf2, 0x66, 0x90, 0xaf, 0x23, ++ 0x6f, 0xeb, 0x09, 0xc4, 0xfb, 0x2e, 0x38, 0x4f, 0x63, 0x9c, 0xf1, 0x82, ++ 0x53, 0x71, 0x42, 0x9f, 0x93, 0x5e, 0x07, 0xca, 0xf1, 0x29, 0xef, 0x10, ++ 0x2c, 0xcf, 0x78, 0x9d, 0x28, 0xe7, 0x67, 0xbd, 0x63, 0xb1, 0xac, 0x06, ++ 0x99, 0x1c, 0x07, 0x76, 0xf6, 0x80, 0x05, 0xe2, 0xa7, 0x9e, 0x38, 0x6a, ++ 0xf7, 0x13, 0xe9, 0x3a, 0x2e, 0x8f, 0x5b, 0x53, 0x37, 0x01, 0xd6, 0x1b, ++ 0xda, 0x3e, 0x9e, 0x90, 0x7f, 0x95, 0x6f, 0x58, 0xe3, 0xeb, 0x4b, 0xb5, ++ 0x00, 0xe2, 0xde, 0x94, 0xfe, 0xc5, 0x0d, 0x06, 0x12, 0x18, 0x45, 0xa8, ++ 0x74, 0xf7, 0xee, 0x96, 0xe7, 0x4e, 0x7d, 0x48, 0x7b, 0x5b, 0x0f, 0xed, ++ 0x0d, 0x32, 0x09, 0xf4, 0x0a, 0x6f, 0x2f, 0x6e, 0x8b, 0xfc, 0xbc, 0x43, ++ 0xea, 0x1c, 0x9c, 0x01, 0x71, 0xd9, 0xf7, 0x8c, 0x64, 0x7b, 0x48, 0xbc, ++ 0x31, 0xfc, 0xbc, 0x85, 0xf4, 0x01, 0xbf, 0x22, 0x5a, 0xfb, 0x39, 0x1d, ++ 0x29, 0x0f, 0x3d, 0xef, 0xd9, 0x2a, 0xb3, 0x73, 0x9e, 0x23, 0xfa, 0xbc, ++ 0xad, 0x32, 0xc5, 0xab, 0xd2, 0xc0, 0xf4, 0xbf, 0xf2, 0xf9, 0x8c, 0x3c, ++ 0x62, 0x83, 0x7a, 0x60, 0x70, 0x8d, 0xe5, 0x32, 0xe3, 0x35, 0x51, 0x64, ++ 0xd2, 0x80, 0xcf, 0x03, 0x05, 0xbd, 0x5f, 0xd2, 0x70, 0x75, 0x50, 0xcf, ++ 0x09, 0x8c, 0xc3, 0xec, 0xe9, 0x52, 0xff, 0x28, 0xe1, 0xf9, 0xb2, 0xc6, ++ 0xeb, 0x84, 0xf7, 0xde, 0x90, 0xdc, 0x5b, 0x00, 0x8f, 0x73, 0xfb, 0xf4, ++ 0xb8, 0x5e, 0x93, 0xc0, 0x81, 0xcc, 0x5b, 0x86, 0x01, 0x7e, 0xae, 0xad, ++ 0x32, 0xac, 0xa3, 0xcd, 0x29, 0xe8, 0x77, 0xb5, 0x7a, 0x5d, 0x2b, 0x4e, ++ 0x2a, 0x84, 0xbc, 0xe9, 0x2d, 0xc2, 0xf2, 0x2d, 0x6f, 0x09, 0x96, 0xef, ++ 0x78, 0x4b, 0xb1, 0x3c, 0xe6, 0x75, 0x63, 0xf9, 0xbe, 0xb7, 0x1c, 0xcb, ++ 0x0f, 0xbd, 0x35, 0x58, 0xfe, 0xbb, 0x77, 0x15, 0x96, 0x6d, 0x5e, 0x1f, ++ 0x96, 0x27, 0xbc, 0x75, 0x58, 0x9e, 0xf4, 0xd6, 0x63, 0x79, 0xca, 0xdb, ++ 0x80, 0xe5, 0x19, 0xaf, 0x1f, 0xcb, 0xb3, 0xde, 0x46, 0x2c, 0xcf, 0x79, ++ 0x9b, 0xb0, 0x6c, 0xf7, 0x36, 0x63, 0xa9, 0xda, 0xcf, 0x9e, 0xe4, 0xef, ++ 0x0c, 0x5f, 0x5f, 0xcf, 0x82, 0x1c, 0x1a, 0xc3, 0xe5, 0xec, 0xe0, 0xda, ++ 0x79, 0x6b, 0xea, 0xfa, 0x06, 0xe5, 0xec, 0xb0, 0x5c, 0x86, 0x72, 0xa6, ++ 0xd2, 0xb7, 0xb8, 0xc1, 0xc8, 0xe5, 0x21, 0x55, 0x90, 0x87, 0xbf, 0xc2, ++ 0x3a, 0x9c, 0x02, 0xf2, 0xd2, 0x43, 0x7b, 0x83, 0xc2, 0xe5, 0x30, 0xda, ++ 0xfb, 0x91, 0xdb, 0x41, 0xde, 0x7a, 0xff, 0x08, 0xf2, 0x46, 0xc8, 0x1a, ++ 0x94, 0x03, 0x0b, 0xc8, 0xdd, 0xf7, 0x90, 0x37, 0x02, 0xa7, 0x08, 0x29, ++ 0x20, 0x4f, 0x7d, 0x34, 0xf2, 0x24, 0xca, 0xa1, 0x2a, 0x47, 0xaa, 0x9e, ++ 0xbf, 0x21, 0x95, 0x9c, 0x03, 0xf9, 0x52, 0xe5, 0xca, 0x22, 0x33, 0x7f, ++ 0x48, 0x95, 0xab, 0xfb, 0xc1, 0x4f, 0x8c, 0xe0, 0x6f, 0xf5, 0x56, 0x24, ++ 0xbe, 0xfe, 0x31, 0xff, 0x88, 0x04, 0x72, 0x75, 0x40, 0xb2, 0xe5, 0xfc, ++ 0xbc, 0x82, 0xf8, 0x5c, 0x58, 0xef, 0xe2, 0x63, 0xd7, 0x52, 0x70, 0xad, ++ 0xd0, 0x4f, 0xf6, 0x0f, 0x81, 0x75, 0xa4, 0x6b, 0xc8, 0x57, 0x83, 0x21, ++ 0xbe, 0xdf, 0x75, 0x8c, 0x0a, 0x41, 0x56, 0xf4, 0xf9, 0x69, 0xe5, 0x25, ++ 0x3a, 0xdd, 0x5d, 0xb8, 0x7f, 0x28, 0xf3, 0x53, 0xe6, 0xf7, 0x0a, 0x6f, ++ 0x37, 0xc7, 0x31, 0xba, 0x9a, 0x75, 0xa4, 0x88, 0x8c, 0x84, 0xf3, 0xe5, ++ 0x9c, 0x63, 0x6e, 0xca, 0xcf, 0xb8, 0x3f, 0x5d, 0x3d, 0x12, 0xf6, 0xcd, ++ 0xf4, 0xb9, 0x4c, 0x92, 0x00, 0x8e, 0xdf, 0x39, 0x3d, 0xc2, 0x79, 0x01, ++ 0x19, 0x44, 0x90, 0xce, 0x3d, 0xd1, 0x57, 0xed, 0x7f, 0xea, 0x89, 0xff, ++ 0xcc, 0x81, 0x73, 0x7f, 0x0b, 0xe8, 0x39, 0x9d, 0x7b, 0xdc, 0x01, 0x7d, ++ 0x0d, 0xd3, 0xdf, 0xa7, 0x9c, 0xb7, 0x84, 0x9c, 0x2f, 0x79, 0x8c, 0xce, ++ 0x74, 0x88, 0x83, 0x77, 0x66, 0x1b, 0xec, 0xcc, 0x7f, 0x98, 0x24, 0xd2, ++ 0x91, 0x4c, 0xc2, 0xf3, 0x03, 0x95, 0x8e, 0x07, 0xb2, 0xbf, 0x18, 0x0c, ++ 0xe7, 0x33, 0xf7, 0x51, 0x39, 0x04, 0xfd, 0xea, 0x1a, 0x34, 0x38, 0x81, ++ 0x5c, 0x46, 0x3e, 0x7a, 0xb2, 0xf7, 0x3d, 0xd1, 0x73, 0x01, 0xcc, 0x37, ++ 0x26, 0x7a, 0x1a, 0x08, 0x9c, 0x73, 0x51, 0x7a, 0x6e, 0x85, 0xfb, 0x8e, ++ 0xb1, 0xd2, 0xb3, 0x27, 0x3b, 0xd9, 0x93, 0x7d, 0x3c, 0xb1, 0x81, 0xd1, ++ 0xf9, 0x08, 0xf7, 0x4f, 0xa3, 0xd1, 0x59, 0x3d, 0x0f, 0xd3, 0xe2, 0x71, ++ 0x8b, 0x22, 0x73, 0x3e, 0x70, 0x39, 0x26, 0x77, 0x68, 0xe8, 0x5f, 0x2a, ++ 0xd0, 0xbf, 0xaf, 0xd5, 0x81, 0xfd, 0x0f, 0xee, 0xfd, 0x20, 0x13, 0xce, ++ 0xf1, 0xba, 0x76, 0x5f, 0x91, 0x40, 0x86, 0x86, 0xbe, 0x5f, 0xc0, 0xce, ++ 0x7b, 0xba, 0xdf, 0xcf, 0x17, 0xf4, 0x40, 0xfa, 0xd3, 0xdf, 0x33, 0x61, ++ 0x7f, 0x7c, 0xf0, 0x85, 0x77, 0xb1, 0x5c, 0x4b, 0x98, 0x1e, 0x6e, 0xb4, ++ 0x94, 0xcc, 0x55, 0xc6, 0x04, 0xe1, 0xc5, 0x7a, 0x8f, 0x20, 0xda, 0xbc, ++ 0x3c, 0x8a, 0x24, 0xce, 0xab, 0x07, 0xfd, 0xec, 0x48, 0x55, 0xf5, 0xb3, ++ 0x35, 0x13, 0xe4, 0x69, 0x37, 0xb7, 0x03, 0x61, 0xf3, 0xeb, 0x41, 0x3e, ++ 0xd5, 0xf9, 0x1d, 0x80, 0xf9, 0x51, 0x38, 0x53, 0x41, 0xa6, 0xe9, 0x3c, ++ 0xf2, 0xe5, 0x92, 0xbb, 0x84, 0xf9, 0x8d, 0x4e, 0xc1, 0x79, 0xf7, 0x34, ++ 0x3f, 0x4f, 0x82, 0x81, 0x48, 0x23, 0x28, 0x7e, 0x56, 0x83, 0x81, 0x24, ++ 0x50, 0x79, 0x54, 0xdc, 0x6b, 0x15, 0xdc, 0xd7, 0x39, 0xdb, 0x7c, 0x10, ++ 0xa7, 0xd8, 0x1b, 0xef, 0xac, 0xa5, 0x2c, 0xf1, 0xd8, 0xce, 0xbe, 0x11, ++ 0x70, 0xc0, 0x7b, 0x62, 0x3c, 0x63, 0x59, 0xa3, 0xb9, 0x46, 0xf4, 0x9f, ++ 0x12, 0x6b, 0x44, 0xff, 0x29, 0xa3, 0x26, 0xd4, 0x7f, 0xea, 0x3a, 0xfc, ++ 0x94, 0xcd, 0x4d, 0xf1, 0x5b, 0x9e, 0xae, 0xaf, 0x39, 0xd9, 0x0b, 0xd6, ++ 0x39, 0x17, 0x5f, 0xe7, 0xd8, 0xba, 0xaa, 0xe2, 0x57, 0xd5, 0x94, 0x55, ++ 0x63, 0x11, 0xe0, 0x88, 0xf5, 0xae, 0x7a, 0xa9, 0x88, 0xdd, 0xc3, 0x71, ++ 0x24, 0xcc, 0x8c, 0x70, 0xde, 0xa7, 0x96, 0xcb, 0xd3, 0x0d, 0x38, 0xce, ++ 0xd9, 0xc6, 0x81, 0x09, 0x30, 0xee, 0x59, 0xaf, 0xa9, 0x86, 0xad, 0xaf, ++ 0xf6, 0x1a, 0x36, 0x6e, 0x7a, 0x4d, 0xe8, 0xfa, 0x5a, 0xb9, 0x2a, 0xbe, ++ 0xe6, 0xe4, 0xa8, 0x20, 0x7e, 0xd1, 0xe0, 0xfe, 0xd0, 0xf8, 0x51, 0x89, ++ 0x20, 0x1f, 0x99, 0x60, 0x5d, 0xa4, 0x6d, 0x03, 0xa3, 0xf7, 0x8f, 0xca, ++ 0x4f, 0xf9, 0x73, 0x03, 0x9e, 0xab, 0xb7, 0x28, 0x5f, 0x80, 0xff, 0x6e, ++ 0x1e, 0xa2, 0xfa, 0xef, 0x32, 0xd6, 0x55, 0xb8, 0x9e, 0x26, 0xbd, 0xcf, ++ 0x38, 0x02, 0x9e, 0xef, 0x14, 0xc6, 0xa3, 0xef, 0x39, 0xd4, 0xb3, 0x71, ++ 0x78, 0x2f, 0xba, 0xdc, 0xc8, 0xe4, 0x94, 0xca, 0x4f, 0x3d, 0x9c, 0x77, ++ 0x11, 0xbe, 0x3f, 0x30, 0x21, 0x9f, 0xdd, 0x14, 0x62, 0x02, 0x85, 0xd7, ++ 0x21, 0x5b, 0xea, 0x40, 0xae, 0xfc, 0x0a, 0xd3, 0x67, 0x0f, 0x97, 0xd3, ++ 0x2a, 0x53, 0x9b, 0xc1, 0xed, 0x40, 0x72, 0xb7, 0x82, 0x5c, 0x2f, 0x18, ++ 0xab, 0xca, 0xb9, 0x63, 0xd6, 0x07, 0xd4, 0x4e, 0x7f, 0xfc, 0x17, 0x05, ++ 0xef, 0x99, 0x91, 0xaf, 0x29, 0xf4, 0x9c, 0xe0, 0x55, 0x87, 0x45, 0xa4, ++ 0xc4, 0x06, 0x41, 0xd5, 0x05, 0xbb, 0x97, 0x15, 0xc3, 0xba, 0xfd, 0xf1, ++ 0x8b, 0x37, 0xf1, 0x7d, 0x7a, 0x7d, 0x0e, 0xcc, 0xfb, 0x3c, 0xd1, 0x15, ++ 0x81, 0x5d, 0x3a, 0x4f, 0xde, 0xb4, 0x8d, 0x0a, 0xd1, 0xd7, 0xd3, 0x0a, ++ 0x8b, 0x63, 0x91, 0x3a, 0xb6, 0xcf, 0xf1, 0xd1, 0x3f, 0x30, 0xbf, 0xc5, ++ 0xf5, 0xe2, 0xbe, 0x67, 0x49, 0x83, 0x58, 0x2f, 0x23, 0x33, 0x52, 0xc1, ++ 0xde, 0x96, 0x6d, 0x54, 0x88, 0x9f, 0xe2, 0xbe, 0x14, 0xf6, 0x4d, 0xea, ++ 0xbc, 0xa9, 0xfd, 0x7d, 0x57, 0xb1, 0x23, 0x72, 0x4b, 0x48, 0xcd, 0x3a, ++ 0xd8, 0xa7, 0x3f, 0xa6, 0xb0, 0x78, 0xcf, 0x02, 0x3b, 0x91, 0xfb, 0x50, ++ 0x7b, 0x5d, 0xf5, 0x87, 0x5f, 0xe7, 0x40, 0xdc, 0xa7, 0x5d, 0x61, 0xfe, ++ 0xae, 0x7a, 0x1e, 0xbe, 0x34, 0x89, 0xed, 0x07, 0x2b, 0x66, 0xfa, 0x0d, ++ 0x2e, 0xda, 0xff, 0xa3, 0xdd, 0xa3, 0x6e, 0xa3, 0x16, 0x97, 0xbe, 0xef, ++ 0x5f, 0x87, 0xfe, 0xcf, 0x74, 0xe2, 0xdc, 0x4e, 0xc2, 0xe9, 0xbe, 0xb0, ++ 0x4e, 0xc4, 0xaf, 0x27, 0xfc, 0xb5, 0xf8, 0xaa, 0x7e, 0x50, 0xd8, 0xb9, ++ 0x3c, 0xc7, 0x23, 0xb9, 0x51, 0x8a, 0x78, 0x5f, 0xea, 0x6b, 0x6e, 0xe7, ++ 0x54, 0xfd, 0x48, 0x32, 0xd8, 0x85, 0xb8, 0x4f, 0x9a, 0xa6, 0xae, 0xca, ++ 0x81, 0xc2, 0xe5, 0xc0, 0xaf, 0xb8, 0xad, 0x86, 0x14, 0xc6, 0x77, 0xe0, ++ 0xa3, 0x24, 0x77, 0x1a, 0xdc, 0x21, 0xfd, 0x0c, 0xc1, 0x7e, 0x49, 0x86, ++ 0x31, 0xd1, 0xfb, 0x19, 0xa1, 0x9f, 0x1e, 0xfb, 0xa5, 0xb1, 0x7e, 0x9d, ++ 0x85, 0xb8, 0x3f, 0x26, 0x54, 0x9e, 0x86, 0x06, 0xfb, 0x99, 0x83, 0xf0, ++ 0xfa, 0xb2, 0x71, 0xc5, 0x7e, 0x55, 0x7f, 0x78, 0xf6, 0x45, 0x1f, 0x95, ++ 0x97, 0x8a, 0xdf, 0x3d, 0x6a, 0x23, 0x74, 0xdd, 0xfc, 0x58, 0xae, 0x4f, ++ 0x75, 0xd2, 0xe7, 0x95, 0xdb, 0xef, 0xb5, 0xb9, 0x68, 0x79, 0x46, 0xf6, ++ 0xd9, 0x80, 0x9f, 0x1f, 0xfb, 0xf5, 0x11, 0xef, 0xfb, 0xde, 0x62, 0x50, ++ 0xe9, 0xe1, 0xb2, 0x48, 0x10, 0x4f, 0xe3, 0xf2, 0x49, 0xea, 0x7c, 0x18, ++ 0xa7, 0xf8, 0x62, 0xbb, 0x62, 0xc7, 0x73, 0x84, 0x46, 0x63, 0xc0, 0x48, ++ 0xe5, 0xb3, 0x7a, 0xf7, 0xd2, 0x62, 0x32, 0x1c, 0xeb, 0xc7, 0x59, 0x7d, ++ 0xfd, 0xa7, 0x7a, 0xa8, 0x37, 0x8b, 0xfc, 0xaa, 0xf8, 0xcd, 0xa3, 0xa9, ++ 0x0e, 0x76, 0x4f, 0x88, 0xc5, 0x93, 0x48, 0x00, 0xfd, 0xdc, 0xea, 0x6d, ++ 0xff, 0x51, 0x08, 0xeb, 0x85, 0x87, 0x74, 0xa2, 0x9c, 0x69, 0xdf, 0x83, ++ 0xf1, 0x2f, 0x26, 0xa1, 0x5e, 0xcf, 0x37, 0x24, 0x84, 0xb7, 0xe3, 0xc5, ++ 0xe0, 0x54, 0x78, 0x9f, 0xfd, 0x78, 0x76, 0xdf, 0xff, 0xa9, 0xde, 0x06, ++ 0xe5, 0xe4, 0xd3, 0xa0, 0x47, 0x1e, 0x8d, 0x9c, 0x94, 0x73, 0xbf, 0x15, ++ 0xe8, 0x05, 0xfb, 0xfd, 0x7c, 0x83, 0x35, 0x19, 0xed, 0xfd, 0xb5, 0xe4, ++ 0x5a, 0xd0, 0x77, 0x95, 0x2e, 0xc4, 0xcf, 0xfc, 0xd7, 0xda, 0x1d, 0x8f, ++ 0x0f, 0x3f, 0x4e, 0xf1, 0x3a, 0xb7, 0xed, 0x2f, 0x36, 0x69, 0x68, 0xa8, ++ 0x9d, 0x60, 0xf2, 0xd6, 0xd5, 0xb4, 0xf0, 0xdf, 0x4c, 0xba, 0xe8, 0xf6, ++ 0xa4, 0x9d, 0xca, 0x63, 0xa8, 0x9f, 0x44, 0x01, 0xe3, 0x7b, 0x8e, 0x66, ++ 0xee, 0x77, 0xb7, 0xb0, 0xb2, 0x52, 0x09, 0xd8, 0xe0, 0x3e, 0x4e, 0xe5, ++ 0x16, 0xc5, 0x49, 0x25, 0x91, 0x54, 0x3e, 0xab, 0x27, 0x70, 0x3f, 0x81, ++ 0xbc, 0x67, 0xf4, 0x43, 0x7c, 0x74, 0xd9, 0xb3, 0xaf, 0xbc, 0x33, 0x9e, ++ 0xd2, 0x7f, 0xd9, 0x2e, 0x25, 0xb9, 0x98, 0x4d, 0xc7, 0x22, 0xa5, 0x06, ++ 0xf9, 0xe3, 0xa1, 0x7f, 0x57, 0x8d, 0x0c, 0xf2, 0xa3, 0xe2, 0xf7, 0xaf, ++ 0x18, 0x1c, 0xc3, 0xd8, 0xf3, 0x7b, 0x92, 0x82, 0x7c, 0x59, 0xb6, 0x6b, ++ 0x9f, 0x81, 0x0c, 0x0b, 0xa7, 0xe3, 0xa4, 0xa6, 0x7d, 0x86, 0x36, 0x4b, ++ 0x04, 0xfe, 0x34, 0x1d, 0x2f, 0x84, 0xf5, 0xb6, 0x76, 0xc7, 0x3f, 0x0c, ++ 0x10, 0x57, 0xfc, 0x78, 0xaf, 0x44, 0xd2, 0xb2, 0xc2, 0xdf, 0x2f, 0xdf, ++ 0xf2, 0x0a, 0xae, 0x7b, 0x40, 0x27, 0xe4, 0x27, 0xe7, 0x57, 0x37, 0xff, ++ 0xc2, 0xf8, 0x16, 0x98, 0xf6, 0xf2, 0x68, 0xec, 0x67, 0x07, 0x7b, 0xd8, ++ 0x13, 0xdf, 0xb2, 0x61, 0x3f, 0x97, 0x82, 0xf2, 0xfd, 0xdc, 0xcb, 0x70, ++ 0x8f, 0xe9, 0x7d, 0xa3, 0x13, 0xe8, 0x50, 0xfe, 0xdc, 0x0a, 0x1b, 0xcc, ++ 0xe7, 0xb4, 0x5c, 0xc3, 0xe4, 0xfc, 0xd7, 0xf7, 0xa6, 0x82, 0xbe, 0x97, ++ 0x2b, 0xbe, 0x54, 0x3b, 0x96, 0xec, 0x79, 0xf9, 0x93, 0x3f, 0x47, 0xf9, ++ 0x5b, 0x72, 0xf4, 0xe7, 0xa9, 0xe8, 0x3f, 0x10, 0x57, 0x86, 0x0e, 0x6d, ++ 0xb3, 0x2f, 0x03, 0xe6, 0xb9, 0x78, 0xf3, 0xad, 0x38, 0xcf, 0x32, 0xe2, ++ 0x46, 0x39, 0x2c, 0xff, 0xb5, 0xbe, 0x04, 0xee, 0x99, 0x5e, 0x90, 0x49, ++ 0xd1, 0xae, 0x08, 0x7a, 0xf2, 0x17, 0x03, 0xdb, 0xbf, 0x9c, 0xde, 0x4a, ++ 0x99, 0x4b, 0xe7, 0x79, 0x1a, 0xf0, 0x03, 0xfb, 0xf6, 0xa6, 0xde, 0xbf, ++ 0x1d, 0xe3, 0xe6, 0x3f, 0xc3, 0x7b, 0x70, 0x3f, 0xe7, 0x73, 0xa6, 0x2b, ++ 0x21, 0xd6, 0x2f, 0x98, 0x18, 0xbf, 0xb6, 0x18, 0x74, 0x6a, 0x3c, 0xd4, ++ 0x24, 0xc8, 0xef, 0xb6, 0xf5, 0xad, 0xc0, 0xa7, 0xb3, 0xfd, 0x5c, 0x69, ++ 0x70, 0xee, 0x41, 0xe9, 0xe0, 0xe3, 0x74, 0x93, 0x2e, 0x51, 0xb8, 0xfa, ++ 0xa3, 0x05, 0x69, 0x8c, 0x4f, 0xc4, 0x21, 0xe7, 0xf0, 0xf7, 0xa8, 0xbd, ++ 0x9f, 0x04, 0xcf, 0xa1, 0x7f, 0xab, 0xe2, 0x32, 0x0f, 0x17, 0xde, 0xe3, ++ 0xf6, 0x91, 0x8d, 0xbf, 0x92, 0x8f, 0x4f, 0xf1, 0x8e, 0x83, 0xf5, 0xeb, ++ 0x74, 0x6a, 0x64, 0xff, 0xef, 0x1f, 0x7c, 0x7e, 0xf4, 0xa7, 0x95, 0x84, ++ 0xc8, 0x59, 0x88, 0xbe, 0x33, 0xfd, 0xdf, 0x76, 0x1f, 0xd3, 0x77, 0x55, ++ 0xff, 0xfd, 0xd3, 0x8b, 0xa0, 0xfd, 0xf3, 0xb7, 0x98, 0x1e, 0xc1, 0x7b, ++ 0xb0, 0x5e, 0x50, 0xbc, 0x02, 0x69, 0xd8, 0xbe, 0x6f, 0xa6, 0x84, 0xf6, ++ 0x81, 0xee, 0xb3, 0x23, 0xe9, 0xf9, 0x36, 0x85, 0xeb, 0xb9, 0xd8, 0x4e, ++ 0x77, 0x38, 0xb8, 0xfe, 0xab, 0x72, 0x42, 0xf1, 0x97, 0xa5, 0x84, 0x50, ++ 0x79, 0xa1, 0xe3, 0x24, 0x21, 0x1f, 0x70, 0x7f, 0x5c, 0xb6, 0x91, 0xbe, ++ 0x1f, 0xe2, 0x97, 0x79, 0x60, 0x5c, 0xec, 0x67, 0x08, 0x3e, 0x0f, 0x59, ++ 0x37, 0x96, 0x70, 0xbb, 0x70, 0x48, 0x63, 0x0f, 0xc8, 0xe6, 0x94, 0x98, ++ 0xfc, 0xe8, 0x4a, 0xc5, 0xff, 0xf4, 0x13, 0xa0, 0xbf, 0xef, 0x19, 0x9d, ++ 0x3e, 0x07, 0xe8, 0xaf, 0x52, 0x02, 0xf3, 0xff, 0x64, 0xe7, 0x81, 0x77, ++ 0xe6, 0x50, 0x39, 0xff, 0xa4, 0x49, 0xd5, 0x5b, 0xd1, 0xae, 0x6a, 0xf5, ++ 0xb6, 0xfc, 0xf9, 0x31, 0x24, 0x92, 0xde, 0x7e, 0x62, 0xa1, 0xfb, 0xae, ++ 0x48, 0x7a, 0x4b, 0x9f, 0x47, 0xd4, 0x5b, 0x4b, 0x1b, 0xca, 0xf3, 0xff, ++ 0x2d, 0xbb, 0xaa, 0xd2, 0xaf, 0x5d, 0x43, 0x3f, 0xb0, 0x8f, 0x2f, 0x3b, ++ 0xa2, 0xd3, 0x51, 0x6b, 0x1f, 0x37, 0x18, 0x1c, 0x11, 0xed, 0x23, 0xfd, ++ 0x79, 0x8b, 0xe4, 0x84, 0xcb, 0xa1, 0x2a, 0x7f, 0xaa, 0xdc, 0x55, 0xfc, ++ 0xb6, 0xaa, 0x3f, 0xd8, 0xa1, 0x6e, 0xf9, 0x54, 0xe5, 0xaf, 0x5b, 0x3e, ++ 0x55, 0xf9, 0xd3, 0xce, 0x57, 0xa4, 0x9f, 0xb6, 0xfd, 0x0f, 0xa0, 0xdf, ++ 0x14, 0xaf, 0xdb, 0x4d, 0x9b, 0xa6, 0x81, 0xff, 0x6c, 0xea, 0x24, 0x18, ++ 0x87, 0xcf, 0x9d, 0xa9, 0xc7, 0x7b, 0x9a, 0xa6, 0xcf, 0x09, 0xbb, 0xa7, ++ 0x71, 0x47, 0x3c, 0xd6, 0x67, 0xe9, 0xdb, 0x7e, 0x0f, 0x3e, 0xe1, 0x07, ++ 0x55, 0xb3, 0x86, 0xc1, 0x3a, 0x7f, 0x3b, 0xf1, 0x29, 0xec, 0xdc, 0xbe, ++ 0x5e, 0x41, 0x3f, 0xf6, 0xeb, 0x4b, 0x97, 0x26, 0xd0, 0xf9, 0xcc, 0xe1, ++ 0xf4, 0xbd, 0x9d, 0x92, 0x7b, 0x2a, 0xe5, 0x47, 0xa9, 0x2c, 0x05, 0xe2, ++ 0x28, 0x9e, 0xb3, 0x65, 0xe2, 0x4b, 0x48, 0x82, 0x78, 0xb2, 0x44, 0x4e, ++ 0x84, 0xe0, 0x71, 0x7b, 0xb9, 0x58, 0x87, 0x9f, 0x89, 0xa9, 0x41, 0x38, ++ 0x3d, 0xf5, 0xff, 0xb6, 0x7e, 0xf7, 0x77, 0x2d, 0x8f, 0x52, 0xbe, 0x9e, ++ 0xc8, 0x26, 0xe4, 0x6f, 0x50, 0xe2, 0xfe, 0x83, 0x3a, 0xd6, 0x21, 0xf2, ++ 0x34, 0xbd, 0x85, 0x9d, 0x63, 0x78, 0x46, 0x4b, 0xfe, 0x01, 0xa8, 0x87, ++ 0x6d, 0x72, 0x49, 0xc8, 0x3e, 0xc2, 0x63, 0x64, 0xf6, 0xe7, 0x68, 0xfe, ++ 0x2d, 0x63, 0x80, 0x7e, 0xb9, 0xb3, 0x86, 0x25, 0x30, 0x39, 0x1f, 0x8c, ++ 0xfb, 0x45, 0x0f, 0xb7, 0x63, 0x5d, 0x3e, 0x47, 0x02, 0xd8, 0xf7, 0xae, ++ 0x96, 0x81, 0xb8, 0x2f, 0xec, 0x3a, 0xbc, 0xd0, 0xea, 0x8e, 0x60, 0xcf, ++ 0x0e, 0x70, 0x39, 0x7b, 0x85, 0x9f, 0xc3, 0x74, 0x58, 0xa4, 0x7a, 0x3d, ++ 0x95, 0xfb, 0x0e, 0xd2, 0x89, 0x7e, 0x8d, 0xcf, 0x62, 0x8e, 0x18, 0x97, ++ 0x9b, 0x63, 0x54, 0xed, 0x34, 0xe7, 0x1b, 0xfd, 0xd1, 0xd3, 0xf1, 0x4b, ++ 0xb9, 0x1c, 0xce, 0xa6, 0xaf, 0x26, 0x8c, 0x0c, 0xe1, 0xdb, 0xcc, 0xa9, ++ 0x1f, 0xcb, 0xb6, 0x70, 0x3e, 0xc0, 0xcf, 0x89, 0x90, 0x7d, 0xc5, 0xf7, ++ 0xa5, 0x2f, 0xc8, 0x35, 0xd0, 0xf7, 0x80, 0xb9, 0xad, 0xb0, 0x24, 0x42, ++ 0xfc, 0xa6, 0x92, 0xd3, 0x6f, 0xe2, 0xfe, 0x2f, 0x0d, 0xb0, 0xee, 0xe5, ++ 0xb7, 0xe4, 0xca, 0x40, 0xc7, 0x7c, 0x8b, 0x5e, 0x88, 0x87, 0x2c, 0x32, ++ 0x72, 0x7d, 0x1d, 0x4a, 0x86, 0x02, 0x5e, 0x13, 0xf7, 0x2f, 0x7d, 0x60, ++ 0x0c, 0x95, 0x63, 0xcf, 0x61, 0xbd, 0xd3, 0x4c, 0xe7, 0xe7, 0x69, 0xf9, ++ 0xd4, 0xe0, 0x8e, 0xb0, 0xbf, 0xd3, 0xd2, 0x13, 0xe0, 0x83, 0x7f, 0xb9, ++ 0xd5, 0xc8, 0xfc, 0xe5, 0xb7, 0x95, 0x92, 0xc5, 0x40, 0xd7, 0xb7, 0x6f, ++ 0x65, 0xe7, 0xbd, 0x7f, 0x33, 0x38, 0xab, 0x22, 0xe1, 0x99, 0x6e, 0x66, ++ 0xfe, 0xe6, 0x6c, 0x52, 0x72, 0x61, 0xb4, 0xf4, 0xd3, 0xa3, 0x6f, 0xee, ++ 0x2c, 0x6b, 0x20, 0x8f, 0xd2, 0xa3, 0xcb, 0xc2, 0xee, 0x6b, 0x87, 0xcb, ++ 0x1f, 0xd3, 0xfb, 0x2e, 0xbb, 0xe4, 0x5f, 0x2d, 0x81, 0x1c, 0xea, 0x59, ++ 0x3d, 0x99, 0xdd, 0x6f, 0x2e, 0x24, 0xee, 0x07, 0x26, 0x48, 0xa8, 0xef, ++ 0x37, 0x84, 0xda, 0xaf, 0xdc, 0xe6, 0xe9, 0xcf, 0xc2, 0x7d, 0x9a, 0xea, ++ 0x16, 0xc9, 0xae, 0xa3, 0xed, 0xd5, 0x72, 0x9b, 0x01, 0xe4, 0xd8, 0xd3, ++ 0xbc, 0x4b, 0x06, 0xbf, 0xfd, 0x26, 0x07, 0x71, 0xe1, 0xfe, 0x5a, 0xae, ++ 0x19, 0x36, 0x33, 0x24, 0xfe, 0x45, 0x97, 0x3d, 0xa4, 0xd7, 0x81, 0xaf, ++ 0xe6, 0xcc, 0x05, 0xfa, 0x7e, 0x36, 0xd3, 0x48, 0x00, 0x2f, 0xd7, 0xd0, ++ 0x4f, 0x6d, 0xb0, 0xfe, 0x7f, 0xd6, 0x32, 0x0a, 0xf5, 0x20, 0xda, 0xbc, ++ 0x5e, 0xf7, 0x92, 0x69, 0xf9, 0x0a, 0xc0, 0x61, 0xf6, 0x4c, 0x2b, 0x0f, ++ 0x85, 0xc9, 0xf1, 0x42, 0xfd, 0xd6, 0x49, 0xa4, 0x2f, 0x9c, 0x03, 0x4f, ++ 0x34, 0xb6, 0xad, 0x70, 0x46, 0xe0, 0x5f, 0xbe, 0x89, 0xc9, 0x59, 0xcc, ++ 0xf6, 0xcd, 0xf4, 0xff, 0x99, 0x7d, 0x9b, 0x40, 0xed, 0x1b, 0x93, 0x6b, ++ 0x25, 0xd4, 0xbe, 0x59, 0x4c, 0x61, 0xf6, 0x2d, 0x2d, 0x92, 0x7d, 0x5b, ++ 0xbe, 0xda, 0x91, 0x06, 0x72, 0xb1, 0x7c, 0xcf, 0x40, 0xfc, 0x7e, 0x6b, ++ 0xf9, 0x6b, 0x8b, 0x53, 0x22, 0xd9, 0xb7, 0x57, 0xf9, 0xbe, 0xf7, 0x35, ++ 0x7e, 0x0f, 0xbc, 0xa3, 0x2f, 0xb5, 0x6f, 0x23, 0x42, 0xec, 0x5b, 0x5f, ++ 0x6a, 0xdf, 0x22, 0xc4, 0xc9, 0xbf, 0x88, 0xd5, 0xbe, 0x99, 0xfe, 0x67, ++ 0xf4, 0xef, 0x55, 0xb0, 0x6f, 0x11, 0xe6, 0x6b, 0x36, 0x89, 0xf6, 0xad, ++ 0xa8, 0x65, 0x35, 0xda, 0xb7, 0xa2, 0xbe, 0x7a, 0xe1, 0xbe, 0x12, 0x31, ++ 0x51, 0xfb, 0x16, 0x7f, 0x39, 0xfb, 0x36, 0xff, 0xd1, 0x5b, 0xb1, 0xae, ++ 0x38, 0xe3, 0x23, 0xc8, 0x0f, 0xd0, 0x15, 0xec, 0xdb, 0x6b, 0xdc, 0xce, ++ 0xc1, 0x38, 0x60, 0xe7, 0x6e, 0x30, 0xb1, 0xf8, 0x66, 0xac, 0x76, 0xae, ++ 0x5f, 0xac, 0x76, 0xee, 0x7f, 0x88, 0xce, 0xaa, 0x9d, 0x5b, 0xde, 0x4f, ++ 0x42, 0xff, 0x25, 0x5c, 0x0e, 0x99, 0x9d, 0x5b, 0x9e, 0xc5, 0xec, 0xdc, ++ 0xf2, 0x3d, 0xcc, 0xce, 0x2d, 0xcf, 0x66, 0x76, 0x4e, 0x6b, 0xdf, 0xf2, ++ 0xc2, 0xec, 0x1b, 0x7b, 0xbf, 0x7a, 0x08, 0x7d, 0x1f, 0xf7, 0x8f, 0x59, ++ 0x8f, 0xdf, 0x01, 0xf7, 0x09, 0x4b, 0x15, 0xa7, 0x89, 0xf6, 0x2f, 0x76, ++ 0xa8, 0xdf, 0x4f, 0xd4, 0x8c, 0x09, 0xb5, 0x77, 0x37, 0x98, 0x64, 0xa4, ++ 0x73, 0x98, 0xbd, 0x73, 0x7e, 0x8a, 0xdf, 0xc1, 0xf4, 0x64, 0xef, 0xfe, ++ 0x0a, 0xf6, 0x2e, 0x1b, 0xed, 0xd8, 0x20, 0xd0, 0x23, 0xad, 0x7c, 0x4c, ++ 0x19, 0x14, 0x2f, 0xdc, 0x67, 0x7b, 0xfb, 0xcb, 0x53, 0xbf, 0xfd, 0x1d, ++ 0xe8, 0xcb, 0xeb, 0x7a, 0xbc, 0x2f, 0xf4, 0xae, 0x8e, 0xed, 0x8f, 0xf6, ++ 0x7e, 0x79, 0x6a, 0x14, 0xe8, 0xdd, 0x43, 0x26, 0x66, 0x7f, 0x97, 0x98, ++ 0x18, 0x3f, 0xdb, 0xbd, 0x3e, 0xb4, 0xa7, 0x93, 0x86, 0x32, 0x7d, 0xaf, ++ 0xba, 0x87, 0xd1, 0xaf, 0x7a, 0xb7, 0xc4, 0xe6, 0xbb, 0x52, 0xef, 0x77, ++ 0xc0, 0x3a, 0xf0, 0xd5, 0x45, 0xdc, 0x3f, 0xcf, 0xdd, 0xc3, 0xf6, 0xcf, ++ 0xb3, 0x8c, 0xad, 0x29, 0xf1, 0x70, 0x2f, 0xe9, 0x5f, 0x14, 0xc2, 0xbe, ++ 0xfb, 0x20, 0xc5, 0xf3, 0x43, 0xe4, 0xa1, 0xf4, 0x62, 0x05, 0xc6, 0x01, ++ 0x9f, 0x8f, 0xb3, 0x6d, 0x85, 0xfd, 0x65, 0xa9, 0x4c, 0x4c, 0xe0, 0xc7, ++ 0xce, 0x3b, 0x3c, 0xe5, 0x63, 0xf0, 0x5f, 0xe7, 0x5d, 0xac, 0x43, 0xbf, ++ 0x77, 0x1e, 0x3c, 0x87, 0x73, 0x12, 0x7e, 0x4f, 0x42, 0xbd, 0x47, 0x31, ++ 0xa7, 0x79, 0xd7, 0x2b, 0x7d, 0x48, 0xf8, 0xfd, 0x88, 0x89, 0x46, 0xc6, ++ 0x87, 0x89, 0x2b, 0x24, 0xff, 0x96, 0x2c, 0xb8, 0x8f, 0x20, 0xb6, 0xcf, ++ 0xd3, 0xf8, 0xf5, 0xeb, 0xf8, 0x3c, 0xa9, 0x3f, 0x8b, 0x74, 0x21, 0x7f, ++ 0xd5, 0x47, 0x8c, 0xdf, 0xad, 0xd3, 0xd2, 0xc3, 0xc9, 0xe6, 0x5f, 0xb5, ++ 0x52, 0x2f, 0xd2, 0xa3, 0x46, 0x8a, 0x48, 0x0f, 0xca, 0xd1, 0xe2, 0xf9, ++ 0xa9, 0xc1, 0xf9, 0xcf, 0x7d, 0xa1, 0x6d, 0x5d, 0x1f, 0x68, 0x5f, 0x2a, ++ 0xe1, 0x7e, 0x4a, 0xa5, 0x87, 0x76, 0x9e, 0x2a, 0x7d, 0xd4, 0xfd, 0xca, ++ 0x3c, 0xae, 0x23, 0x9e, 0x96, 0x5d, 0x0a, 0xf0, 0x4b, 0x3b, 0x7f, 0x95, ++ 0x7e, 0x61, 0xf3, 0x56, 0xe9, 0xa9, 0x99, 0x7f, 0x9d, 0x6a, 0x3f, 0xae, ++ 0x26, 0xc3, 0x40, 0xdf, 0xde, 0xd5, 0xb9, 0x1f, 0x18, 0x03, 0xf2, 0xf1, ++ 0x67, 0x4a, 0x07, 0x8a, 0xd7, 0x6d, 0xb3, 0xb3, 0xd3, 0x42, 0xed, 0xf1, ++ 0x83, 0xdc, 0x2e, 0x4d, 0x75, 0x1f, 0xcf, 0x4f, 0x75, 0x00, 0xdd, 0xd8, ++ 0x77, 0x89, 0x73, 0xca, 0x77, 0xbd, 0x92, 0x4a, 0xe7, 0x73, 0xb3, 0x2b, ++ 0x6b, 0x24, 0x7c, 0x3f, 0x7c, 0xeb, 0x57, 0x06, 0x37, 0xc4, 0x17, 0x0e, ++ 0x98, 0x3b, 0xd1, 0xbe, 0xa9, 0xf2, 0xf5, 0x09, 0x97, 0xf7, 0x00, 0x87, ++ 0xf3, 0x76, 0x6f, 0x7b, 0x3e, 0xae, 0x23, 0xcd, 0x92, 0x1d, 0xf5, 0x26, ++ 0xa0, 0xb1, 0x5f, 0xfc, 0xfe, 0x98, 0xe7, 0x1e, 0xa6, 0x57, 0x07, 0xa4, ++ 0x7f, 0xac, 0xeb, 0x33, 0x1a, 0xe9, 0x0a, 0xcb, 0x00, 0x29, 0x54, 0xd7, ++ 0x21, 0xe0, 0x03, 0xfd, 0xef, 0xd4, 0x16, 0xc6, 0x07, 0x0f, 0xf0, 0x81, ++ 0xfe, 0x77, 0x1a, 0xe9, 0x3c, 0x04, 0x74, 0xae, 0x4e, 0x96, 0x9c, 0x01, ++ 0xe8, 0xdf, 0xbc, 0xeb, 0x5e, 0x90, 0x9b, 0x57, 0xcd, 0xf4, 0x39, 0xe8, ++ 0x6f, 0xb9, 0xe4, 0x64, 0xdf, 0x97, 0x11, 0x4b, 0x46, 0xea, 0x65, 0xe5, ++ 0x53, 0x8e, 0x24, 0x9f, 0x18, 0x9c, 0xc8, 0x09, 0xae, 0x8b, 0xf3, 0xa0, ++ 0x5f, 0x52, 0xb8, 0xdf, 0x31, 0xd1, 0xd8, 0xfa, 0x36, 0xe0, 0x31, 0x91, ++ 0xea, 0xc3, 0x16, 0x12, 0xee, 0x87, 0xa8, 0x7c, 0x1f, 0x42, 0xff, 0x5c, ++ 0x8a, 0x74, 0xef, 0xa7, 0x07, 0x39, 0xfe, 0x98, 0xcb, 0xe7, 0xab, 0x40, ++ 0x6f, 0x0b, 0xd0, 0xb5, 0xd3, 0x00, 0xfe, 0x8c, 0x27, 0xc0, 0xd6, 0x0f, ++ 0xb5, 0xdd, 0x23, 0x3b, 0xf2, 0x91, 0x3e, 0x2a, 0xbd, 0x9b, 0xe9, 0xfa, ++ 0x30, 0x9a, 0xd1, 0x5b, 0x17, 0x81, 0x9e, 0x37, 0xab, 0x75, 0x4e, 0x4f, ++ 0x4f, 0x8b, 0xa4, 0xc0, 0xfb, 0x93, 0xe9, 0xfe, 0xb5, 0x97, 0x04, 0xa7, ++ 0x5b, 0x5f, 0x1e, 0x52, 0xe5, 0x18, 0xbe, 0x87, 0xd3, 0xd2, 0x03, 0xe2, ++ 0x01, 0x19, 0x21, 0x7a, 0x0f, 0xf6, 0x29, 0xf4, 0x7c, 0xb2, 0xba, 0xf9, ++ 0x28, 0xd2, 0x65, 0xca, 0x4a, 0xea, 0x5e, 0x85, 0xd0, 0x1d, 0xec, 0xd6, ++ 0xe5, 0xe8, 0x13, 0x4d, 0x2f, 0xaa, 0x9b, 0x7f, 0x18, 0xbd, 0xf8, 0x44, ++ 0xa3, 0x17, 0x7b, 0xcd, 0x9d, 0x7f, 0x19, 0x01, 0xf1, 0xaf, 0x3d, 0x12, ++ 0xda, 0x07, 0xd2, 0x92, 0x28, 0xec, 0xf7, 0xe3, 0xcd, 0xcc, 0xcf, 0x38, ++ 0x60, 0x76, 0xa3, 0xfc, 0x76, 0xbe, 0xa6, 0xe0, 0xfd, 0x73, 0xad, 0x1d, ++ 0xf9, 0x9a, 0xcb, 0x3d, 0xec, 0x2f, 0x42, 0xbf, 0xfb, 0x9b, 0x04, 0x13, ++ 0x01, 0x3b, 0x67, 0x37, 0x93, 0x8f, 0x54, 0x3c, 0x06, 0x30, 0x39, 0x0a, ++ 0xb5, 0xdf, 0xaf, 0x9a, 0xdd, 0xc8, 0xaf, 0x68, 0xf0, 0xe3, 0xf8, 0x3a, ++ 0x1c, 0xcd, 0x7f, 0x52, 0xeb, 0x37, 0xc2, 0x78, 0x70, 0x1f, 0xd1, 0x21, ++ 0x8e, 0x17, 0xe6, 0x5f, 0xf0, 0xf8, 0x4f, 0x4f, 0xf3, 0x4a, 0xe3, 0xe3, ++ 0x7e, 0xd7, 0x79, 0x75, 0x9f, 0x67, 0x92, 0x56, 0x03, 0x61, 0xf1, 0xff, ++ 0x15, 0xc6, 0x90, 0x73, 0xa9, 0xdb, 0xf8, 0xb9, 0x40, 0x77, 0x9c, 0x2c, ++ 0xd8, 0xcf, 0x6e, 0xba, 0x4c, 0x3f, 0x88, 0xbf, 0x04, 0xe8, 0xbc, 0x5f, ++ 0xdd, 0xf9, 0x14, 0xc6, 0x7f, 0xcf, 0x3f, 0x73, 0x7c, 0x1a, 0xc8, 0xef, ++ 0xb2, 0x3f, 0xea, 0x89, 0x89, 0xf2, 0xb9, 0x7d, 0xa7, 0x95, 0x04, 0xd8, ++ 0xbd, 0x0b, 0x03, 0xac, 0xb3, 0x15, 0xbb, 0xf5, 0x11, 0xcf, 0x51, 0x08, ++ 0xa9, 0x65, 0xdf, 0x39, 0xfe, 0xce, 0x8a, 0xf6, 0xa5, 0xe2, 0x79, 0xa3, ++ 0xbf, 0x98, 0xbe, 0x5f, 0xf1, 0xe2, 0x47, 0xc3, 0x21, 0x6e, 0xd5, 0xbe, ++ 0x86, 0xd9, 0x19, 0xdf, 0x33, 0x5c, 0x3e, 0x7c, 0x6d, 0xc3, 0xe1, 0x7c, ++ 0xbd, 0x42, 0x66, 0xe7, 0xc2, 0x5a, 0x78, 0xd7, 0x71, 0x79, 0x39, 0xf7, ++ 0x52, 0x7c, 0x29, 0xd8, 0x49, 0xa9, 0x91, 0x7d, 0xbf, 0x5a, 0xd1, 0x34, ++ 0x4b, 0x31, 0x86, 0xec, 0xd3, 0x47, 0x9a, 0x15, 0x1c, 0x97, 0xf6, 0xc3, ++ 0x7b, 0xcb, 0xbe, 0x1d, 0x12, 0xc6, 0xcb, 0xc3, 0xf1, 0x5b, 0xcd, 0xe0, ++ 0xed, 0x60, 0xf6, 0xaf, 0xa2, 0x59, 0xf1, 0xc3, 0x77, 0xb0, 0x15, 0x8d, ++ 0x5b, 0x70, 0x7f, 0xeb, 0x69, 0xfc, 0xd4, 0x00, 0x7e, 0xdd, 0xa4, 0xdf, ++ 0x3d, 0xcb, 0xbe, 0xaf, 0x6d, 0xd6, 0x8b, 0xf1, 0xc3, 0x46, 0x7d, 0xc0, ++ 0x88, 0x71, 0x4e, 0xfd, 0x71, 0xe3, 0x70, 0xa6, 0xb7, 0x92, 0x10, 0x8f, ++ 0xaa, 0x42, 0xbd, 0xac, 0x6e, 0xe2, 0x71, 0x32, 0x4d, 0xfc, 0x68, 0xd9, ++ 0xef, 0xf6, 0xbc, 0xe8, 0xa3, 0xa4, 0x59, 0xf6, 0xfb, 0xdf, 0xd8, 0xc0, ++ 0xde, 0x9c, 0x6d, 0xdd, 0x6e, 0xc3, 0xf8, 0x5c, 0x23, 0x8b, 0xbf, 0xc9, ++ 0x16, 0x39, 0x72, 0x7c, 0xae, 0xa7, 0xb8, 0x5c, 0xd3, 0x7d, 0x3c, 0x2e, ++ 0x37, 0xf5, 0x34, 0x19, 0x1e, 0x1e, 0x97, 0x3b, 0x0b, 0xff, 0xa1, 0x7a, ++ 0x38, 0xdf, 0xcc, 0xf5, 0x55, 0x8d, 0x6b, 0x36, 0xf6, 0x8a, 0xe9, 0xfc, ++ 0x7c, 0xd9, 0xb3, 0x17, 0x9e, 0x84, 0xf3, 0xa4, 0x73, 0xcf, 0x7f, 0xf2, ++ 0x24, 0xe0, 0x5f, 0xf9, 0xcd, 0x67, 0x4f, 0xde, 0x0d, 0xe7, 0x12, 0x7b, ++ 0xcd, 0x76, 0x58, 0xff, 0x3c, 0xcf, 0xbc, 0x8d, 0xf1, 0x77, 0xf5, 0xbd, ++ 0xbb, 0xb9, 0x9c, 0xb7, 0xef, 0xf8, 0xcd, 0xd3, 0x4f, 0x50, 0x3d, 0x6c, ++ 0x7f, 0xcf, 0x88, 0xf7, 0xb6, 0xda, 0xf7, 0x9c, 0xce, 0x84, 0xef, 0x19, ++ 0xdb, 0x77, 0x7d, 0x99, 0x0a, 0xf1, 0xcd, 0x95, 0x7b, 0x0a, 0x70, 0x3f, ++ 0xb3, 0xf2, 0x85, 0x49, 0x69, 0x97, 0xbb, 0x7f, 0x02, 0xf2, 0xe9, 0x8f, ++ 0xe1, 0xfc, 0x44, 0xcb, 0x8f, 0x03, 0xbb, 0xf5, 0x04, 0xbe, 0xe7, 0x3c, ++ 0x7f, 0xcc, 0x88, 0xfe, 0x47, 0x77, 0x9c, 0xb5, 0xa9, 0x8a, 0xc5, 0xaf, ++ 0x1d, 0x3c, 0xbe, 0xba, 0x33, 0xf2, 0x79, 0x95, 0x1a, 0x0f, 0xac, 0xde, ++ 0x7d, 0xcb, 0xcd, 0xd7, 0xc3, 0x3a, 0xb8, 0x5b, 0x71, 0x3a, 0xf0, 0x39, ++ 0x8f, 0x0f, 0xf6, 0x14, 0x57, 0x7d, 0x8b, 0xf2, 0x75, 0x44, 0x0c, 0xfc, ++ 0xdb, 0xc9, 0xe3, 0xe7, 0x4d, 0x53, 0x23, 0xc6, 0x55, 0xcf, 0xc3, 0x7f, ++ 0x28, 0x9f, 0x36, 0x99, 0xc5, 0xb8, 0xea, 0x85, 0xdd, 0x8b, 0xff, 0xed, ++ 0x09, 0x68, 0xdb, 0xdd, 0x2b, 0x6a, 0x5c, 0x35, 0x10, 0x03, 0xdd, 0xd4, ++ 0xf3, 0xb0, 0x32, 0xb3, 0x6b, 0x9b, 0x19, 0xf4, 0xe3, 0xf9, 0xdf, 0x62, ++ 0x1c, 0x1b, 0xf8, 0x46, 0x7d, 0x72, 0xd2, 0xfe, 0xec, 0x85, 0x4c, 0x88, ++ 0x47, 0x9c, 0x51, 0x3a, 0xef, 0xc4, 0x7b, 0xca, 0x7b, 0x8c, 0x78, 0xcf, ++ 0xa8, 0x62, 0xcf, 0xbb, 0xa8, 0x2f, 0xed, 0x2f, 0x1c, 0xc5, 0x73, 0x26, ++ 0xc2, 0xcf, 0xa3, 0xda, 0x49, 0xf7, 0x0f, 0x3b, 0x37, 0xe0, 0x7b, 0x1d, ++ 0xcf, 0x36, 0x2b, 0x8b, 0xc7, 0x72, 0xfa, 0x43, 0xbc, 0xd6, 0x61, 0xc3, ++ 0xe7, 0x3c, 0x2e, 0xcb, 0xe4, 0x58, 0x8d, 0xd7, 0x46, 0x8b, 0xd3, 0xbe, ++ 0x6f, 0x66, 0xf7, 0xa1, 0xd4, 0xf3, 0xb9, 0xaa, 0x6d, 0x1f, 0x18, 0x88, ++ 0x26, 0xfe, 0x2d, 0x8d, 0x05, 0x7e, 0x1d, 0x17, 0xce, 0x15, 0xd5, 0x79, ++ 0x6b, 0xe1, 0xd9, 0x81, 0x0e, 0xd7, 0x86, 0x9e, 0x3f, 0x44, 0x8b, 0x87, ++ 0x73, 0xbb, 0x1a, 0xc6, 0x2f, 0x76, 0xee, 0xd0, 0xbe, 0x85, 0x9f, 0x47, ++ 0x74, 0x9f, 0x33, 0x10, 0xd2, 0x77, 0x24, 0x9c, 0x8f, 0xb3, 0x73, 0x73, ++ 0x8f, 0x5f, 0x7a, 0x37, 0x12, 0x7f, 0xd5, 0xf3, 0x87, 0xb7, 0xb5, 0xfa, ++ 0xe9, 0x8f, 0xed, 0xdc, 0xa1, 0x67, 0xbc, 0xbf, 0x1b, 0x5d, 0x5e, 0x35, ++ 0xb3, 0xfd, 0xad, 0x4a, 0x9f, 0x73, 0x5f, 0x47, 0xb6, 0xd3, 0x9d, 0x5c, ++ 0xdf, 0xe9, 0x3a, 0xd3, 0x61, 0xc6, 0x73, 0x63, 0xb6, 0xce, 0xcc, 0xe3, ++ 0xeb, 0x4c, 0x35, 0xa5, 0x1b, 0xfb, 0xee, 0x8d, 0xe1, 0x7b, 0x8e, 0xef, ++ 0x03, 0xcf, 0x3d, 0xa3, 0xf7, 0xc3, 0x7e, 0x79, 0x5d, 0xd3, 0x01, 0xb4, ++ 0xb7, 0x5a, 0x3d, 0xaf, 0x26, 0x2c, 0xfe, 0xa5, 0x1d, 0x4f, 0x8a, 0x63, ++ 0xfe, 0x41, 0x75, 0xf3, 0xbe, 0xe1, 0x60, 0x8f, 0xce, 0xed, 0x7f, 0x09, ++ 0xe5, 0xaf, 0x7a, 0xe7, 0x71, 0x83, 0x8f, 0xc2, 0x39, 0xd4, 0xf8, 0x7b, ++ 0x43, 0xdb, 0xd0, 0xa0, 0xbc, 0x83, 0x1d, 0xf7, 0x87, 0xd8, 0xf1, 0x73, ++ 0xcf, 0xed, 0x1b, 0xce, 0xce, 0x45, 0x22, 0xe7, 0x69, 0xb1, 0x71, 0xf8, ++ 0x9e, 0x16, 0x11, 0xbe, 0x67, 0xe7, 0xa7, 0x02, 0xfc, 0x65, 0xbe, 0x26, ++ 0x83, 0xdd, 0xd2, 0xf3, 0x38, 0x67, 0x65, 0xd7, 0x2c, 0x98, 0xef, 0xd9, ++ 0x56, 0x85, 0xc0, 0x7d, 0xf6, 0xb3, 0x4d, 0xfa, 0x22, 0x7f, 0x84, 0x71, ++ 0x3f, 0x83, 0x75, 0x6c, 0x4c, 0x90, 0x4e, 0xeb, 0xac, 0xec, 0x3b, 0x3e, ++ 0x7d, 0x92, 0x01, 0xfd, 0xcc, 0x95, 0xd6, 0xb1, 0xc7, 0xe0, 0xfb, 0xf1, ++ 0x95, 0x56, 0x83, 0x03, 0xf6, 0xdb, 0xb5, 0xab, 0xd9, 0xbd, 0xca, 0xda, ++ 0xff, 0xe5, 0x4c, 0x07, 0xbe, 0xd4, 0x26, 0xde, 0x86, 0xe7, 0x46, 0xf5, ++ 0x1a, 0x3a, 0xda, 0x93, 0xed, 0xb9, 0xb0, 0x0f, 0xb7, 0xe7, 0x97, 0x8c, ++ 0x06, 0xb1, 0xd2, 0xda, 0x83, 0x44, 0x97, 0x4e, 0xc0, 0x7b, 0xa5, 0xb5, ++ 0x28, 0xcd, 0x61, 0x81, 0xbc, 0x5e, 0xcc, 0x4f, 0x21, 0xb2, 0x13, 0xbf, ++ 0x33, 0xd4, 0xdb, 0x0a, 0x8b, 0x60, 0x1e, 0x7a, 0xbb, 0xce, 0x6e, 0x8e, ++ 0xb8, 0xbe, 0x32, 0x78, 0x8a, 0x85, 0xe5, 0xcd, 0x50, 0xec, 0xe2, 0x77, ++ 0x7f, 0xdf, 0x21, 0x0f, 0x06, 0x81, 0x7c, 0x1c, 0xdf, 0x3a, 0x0f, 0x46, ++ 0xa7, 0x26, 0x0f, 0x46, 0xf9, 0x8d, 0xff, 0xaf, 0xe5, 0xc1, 0xf0, 0xc1, ++ 0x38, 0x3f, 0x81, 0x3c, 0x18, 0x01, 0x8c, 0xef, 0xa8, 0x79, 0x30, 0x92, ++ 0x7f, 0xe4, 0x3c, 0x18, 0x10, 0x5f, 0x1a, 0x1d, 0x92, 0x07, 0xa3, 0x53, ++ 0x93, 0x07, 0x83, 0xf3, 0xf1, 0x9f, 0x79, 0x30, 0xfe, 0x99, 0x07, 0x03, ++ 0x4a, 0x35, 0x0f, 0xc6, 0x3b, 0x1b, 0xca, 0x0a, 0x20, 0x4f, 0x85, 0x9a, ++ 0x07, 0xe3, 0xcc, 0x06, 0x4f, 0x01, 0xe4, 0xa5, 0x50, 0xf3, 0x60, 0x7c, ++ 0xb5, 0x61, 0x15, 0xab, 0xf3, 0x3c, 0x18, 0x96, 0xfb, 0x57, 0x17, 0x84, ++ 0xe6, 0xc1, 0xc8, 0xbc, 0x7f, 0x03, 0xb6, 0xab, 0x79, 0x30, 0x9c, 0xf7, ++ 0x3f, 0x52, 0x10, 0x9a, 0x07, 0x23, 0xef, 0xfe, 0xcd, 0x05, 0xa1, 0x79, ++ 0x30, 0x66, 0xde, 0xbf, 0xbd, 0x20, 0x34, 0x0f, 0x46, 0xd9, 0xfd, 0xcf, ++ 0x15, 0x08, 0x79, 0x30, 0xd6, 0xfe, 0xa1, 0x00, 0xf2, 0x60, 0xbc, 0x1e, ++ 0xef, 0x6e, 0x8d, 0x4b, 0x89, 0x9e, 0x07, 0xa3, 0x39, 0xce, 0x11, 0x53, ++ 0x1e, 0x0c, 0x0a, 0xe7, 0x3d, 0x84, 0x13, 0x25, 0x0f, 0x86, 0x16, 0x4e, ++ 0xb4, 0x3c, 0x18, 0x14, 0xce, 0x89, 0xb8, 0x31, 0xd1, 0xf3, 0x60, 0x84, ++ 0xe1, 0x13, 0x25, 0x0f, 0x06, 0x85, 0xf3, 0x09, 0xc2, 0x89, 0x92, 0x07, ++ 0x23, 0x0c, 0x9f, 0x28, 0x79, 0x30, 0x28, 0x9c, 0xcf, 0x71, 0x5e, 0x51, ++ 0xf2, 0x60, 0x68, 0xe1, 0x44, 0xcb, 0x83, 0x41, 0xe1, 0xfc, 0x17, 0xc2, ++ 0x89, 0x92, 0x07, 0x43, 0x0b, 0x27, 0x5a, 0x1e, 0x0c, 0x0a, 0xc7, 0x10, ++ 0x9f, 0x12, 0x3d, 0x0f, 0x46, 0x18, 0x3e, 0x51, 0xf2, 0x60, 0x50, 0x38, ++ 0x09, 0x08, 0x27, 0x4a, 0x1e, 0x8c, 0x30, 0x7c, 0xa2, 0xe4, 0xc1, 0xa0, ++ 0x70, 0xd2, 0x11, 0x4e, 0x94, 0x3c, 0x18, 0x5a, 0x38, 0xd1, 0xf2, 0x60, ++ 0x50, 0x38, 0x59, 0x08, 0x27, 0x4a, 0x1e, 0x0c, 0x2d, 0x9c, 0x68, 0x79, ++ 0x30, 0x28, 0x9c, 0xab, 0xe2, 0xc7, 0x44, 0xcf, 0x83, 0x11, 0x86, 0x4f, ++ 0x94, 0x3c, 0x18, 0x14, 0xce, 0x28, 0xc4, 0x27, 0x4a, 0x1e, 0x8c, 0x30, ++ 0x7c, 0xa2, 0xe4, 0xc1, 0xa0, 0x70, 0x26, 0x20, 0x9c, 0x28, 0x79, 0x30, ++ 0xb4, 0x70, 0xa2, 0xe5, 0xc1, 0xa0, 0x70, 0x0a, 0x70, 0x5e, 0x51, 0xf2, ++ 0x60, 0x68, 0xe1, 0x44, 0xcb, 0x83, 0x41, 0xe1, 0x4c, 0x43, 0x7c, 0xa2, ++ 0xe4, 0xc1, 0x08, 0xc3, 0x27, 0x4a, 0x1e, 0x0c, 0x0a, 0x67, 0x16, 0xe2, ++ 0x13, 0x25, 0x0f, 0x46, 0x18, 0x3e, 0x51, 0xf2, 0x60, 0x50, 0x38, 0x6e, ++ 0xc4, 0x27, 0x4a, 0x1e, 0x0c, 0x2d, 0x9c, 0x68, 0x79, 0x30, 0x28, 0x9c, ++ 0xa5, 0x08, 0x27, 0x4a, 0x1e, 0x0c, 0x2d, 0x9c, 0x68, 0x79, 0x30, 0x28, ++ 0x9c, 0xe5, 0x08, 0x27, 0x4a, 0x1e, 0x8c, 0x30, 0x7c, 0xa2, 0xe4, 0xc1, ++ 0xa0, 0x70, 0xee, 0x46, 0x38, 0x51, 0xf2, 0x60, 0x84, 0xe1, 0xf3, 0x5d, ++ 0xf3, 0x60, 0x98, 0x03, 0x83, 0xa4, 0x81, 0x98, 0x07, 0x03, 0xf3, 0x71, ++ 0x76, 0xe7, 0xc1, 0x48, 0xfe, 0xd6, 0x79, 0x30, 0x7e, 0x05, 0xf8, 0xfe, ++ 0x33, 0x0f, 0xc6, 0x3f, 0xf3, 0x60, 0xfc, 0x18, 0x79, 0x30, 0x6e, 0xb5, ++ 0xba, 0xff, 0x1e, 0x8f, 0xfb, 0xc6, 0xef, 0x96, 0x07, 0xe3, 0x4c, 0xbc, ++ 0x26, 0x6f, 0x44, 0x0f, 0x79, 0x30, 0x6e, 0xb5, 0x96, 0x9c, 0x05, 0x79, ++ 0xfe, 0xb6, 0x79, 0x30, 0x2e, 0xc4, 0x7f, 0xbb, 0x3c, 0x18, 0x74, 0x9c, ++ 0x7f, 0x5c, 0x6e, 0x9c, 0x68, 0x79, 0x30, 0x74, 0x96, 0x6f, 0x97, 0x07, ++ 0x83, 0x8e, 0x23, 0x5b, 0xc6, 0x5c, 0x66, 0x3e, 0x51, 0xf2, 0x60, 0x24, ++ 0x58, 0xc4, 0xfc, 0x21, 0x3f, 0x56, 0x1e, 0x8c, 0x63, 0xf1, 0x49, 0x38, ++ 0x9f, 0x68, 0x79, 0x30, 0x7e, 0x72, 0xf9, 0x26, 0xe8, 0x36, 0x0b, 0xf6, ++ 0x69, 0xd3, 0x51, 0x14, 0xc9, 0x4f, 0x26, 0xff, 0xc4, 0x68, 0x0b, 0x8f, ++ 0x1b, 0xfe, 0x50, 0xf9, 0x27, 0x60, 0xd2, 0x39, 0x3f, 0xa5, 0xfc, 0x13, ++ 0x6a, 0x1e, 0x83, 0x26, 0x05, 0xd6, 0xc3, 0xf7, 0x39, 0xdf, 0xdf, 0xe1, ++ 0x72, 0xf1, 0x01, 0xcf, 0x43, 0x71, 0x2c, 0x6a, 0x1e, 0x0a, 0xff, 0x54, ++ 0x8c, 0xef, 0x2e, 0x15, 0xf3, 0x50, 0x4c, 0xe1, 0x7c, 0x9c, 0xed, 0x16, ++ 0xe5, 0x61, 0x0a, 0x61, 0xe7, 0x28, 0x53, 0xf2, 0xb3, 0xfc, 0xb5, 0xb0, ++ 0x5f, 0x2f, 0xd7, 0xe4, 0xa1, 0x18, 0x22, 0x9e, 0xd3, 0x17, 0xbb, 0x8f, ++ 0xe6, 0x53, 0x70, 0x64, 0xaa, 0x53, 0x9c, 0xc7, 0x51, 0x2e, 0x0f, 0xd3, ++ 0x4a, 0x3f, 0x3d, 0x08, 0xec, 0xb9, 0x79, 0x6c, 0xe4, 0x3c, 0x14, 0x33, ++ 0x38, 0x3f, 0xa6, 0x6b, 0xe8, 0x32, 0x85, 0xf3, 0x6d, 0x3a, 0x2f, 0x6f, ++ 0x87, 0x4f, 0x73, 0xa8, 0x3c, 0x17, 0x97, 0x1f, 0x95, 0x81, 0xae, 0xd3, ++ 0x1c, 0x6d, 0x32, 0xc6, 0xe9, 0x6f, 0x52, 0xf9, 0xe7, 0x10, 0xf8, 0x37, ++ 0x93, 0xc3, 0xd5, 0xe2, 0x3b, 0x83, 0xf3, 0x6f, 0xc6, 0x64, 0xc6, 0x3f, ++ 0x2d, 0xde, 0x6f, 0x01, 0xff, 0x28, 0xde, 0x6f, 0x95, 0x8f, 0x42, 0xfe, ++ 0x69, 0xf1, 0xd6, 0xe2, 0xa9, 0xe5, 0x3f, 0x09, 0xe5, 0x77, 0x48, 0xfe, ++ 0x90, 0x5c, 0x22, 0xe6, 0x9f, 0x98, 0x64, 0x12, 0xf3, 0x4f, 0x14, 0xd8, ++ 0xc5, 0xfc, 0x13, 0x37, 0xa6, 0x8b, 0xf9, 0x27, 0x26, 0x3b, 0xc4, 0xfc, ++ 0x13, 0x37, 0x0d, 0x11, 0xf3, 0x4f, 0x4c, 0x75, 0x8a, 0xf9, 0x27, 0x6e, ++ 0x1e, 0x2b, 0xe6, 0x9f, 0x98, 0xee, 0x5a, 0xad, 0xc9, 0x7f, 0x71, 0x9f, ++ 0x26, 0xff, 0xc5, 0x43, 0x9a, 0xfc, 0x17, 0x9b, 0x34, 0xf9, 0x2f, 0xb6, ++ 0x68, 0xf2, 0x5f, 0xec, 0xd0, 0xe4, 0xbf, 0xd8, 0xa5, 0xc9, 0x7f, 0xf1, ++ 0x92, 0x26, 0xff, 0xc5, 0x3e, 0xa1, 0xbe, 0xb0, 0xee, 0x35, 0xa1, 0xff, ++ 0xe2, 0xfa, 0xa3, 0x42, 0x7d, 0x49, 0xc3, 0x7b, 0x42, 0xff, 0xa5, 0xfe, ++ 0xe3, 0x42, 0xfb, 0xb2, 0xc6, 0x8f, 0x85, 0xf6, 0xaa, 0xa6, 0x4f, 0x85, ++ 0xba, 0xa7, 0xf9, 0x4b, 0xa1, 0x7f, 0x4f, 0xf9, 0x07, 0xde, 0xe2, 0xdf, ++ 0x43, 0xbf, 0xc3, 0xbf, 0x87, 0x3e, 0xc6, 0xbf, 0x87, 0x7e, 0xbf, 0x87, ++ 0xfc, 0x17, 0xef, 0x58, 0x96, 0xae, 0x0b, 0xcd, 0x7f, 0xf1, 0xbe, 0xc5, ++ 0xb3, 0x0e, 0xf2, 0x12, 0x1c, 0xb7, 0x38, 0x78, 0x5e, 0x81, 0xc8, 0xf9, ++ 0x2d, 0xba, 0xdb, 0xa3, 0xe4, 0xbf, 0x08, 0xbe, 0xff, 0xed, 0xf3, 0x5f, ++ 0xa4, 0x24, 0xff, 0xf0, 0xf9, 0x08, 0x74, 0x56, 0xf6, 0x3d, 0x60, 0x6f, ++ 0x4b, 0x9e, 0xce, 0x9a, 0xf2, 0xdd, 0xf3, 0x11, 0xdc, 0x5a, 0x22, 0x7e, ++ 0xd7, 0x3d, 0xab, 0x54, 0xfc, 0xae, 0x5b, 0x67, 0x65, 0xdf, 0x6b, 0xcf, ++ 0x76, 0x8b, 0xdf, 0x77, 0xdf, 0x5e, 0x2e, 0x7e, 0xdf, 0x3d, 0x22, 0xce, ++ 0x2d, 0x01, 0x1e, 0xda, 0xfc, 0x17, 0xbd, 0x2d, 0x2e, 0x9d, 0x15, 0xec, ++ 0x25, 0xcf, 0x53, 0x10, 0x80, 0xef, 0x74, 0xb3, 0x21, 0xde, 0x56, 0x84, ++ 0xe5, 0x41, 0xc8, 0x7f, 0x91, 0x0d, 0xf1, 0xb6, 0x52, 0x2c, 0x0f, 0x43, ++ 0xfe, 0x0b, 0x5a, 0xfe, 0x19, 0xf2, 0x5f, 0xd0, 0xf2, 0x08, 0xe4, 0xbf, ++ 0xa0, 0xe5, 0x1b, 0x90, 0xff, 0x22, 0x1b, 0xf2, 0x67, 0xf8, 0x78, 0xfe, ++ 0x8c, 0x3a, 0x9e, 0x3f, 0xa3, 0x9e, 0xe7, 0xcf, 0x68, 0xe0, 0xf9, 0x33, ++ 0xfc, 0x3c, 0x7f, 0x46, 0x23, 0xcf, 0x9f, 0xd1, 0xc4, 0xf3, 0x67, 0x34, ++ 0xf3, 0xfc, 0x19, 0x01, 0x84, 0x73, 0xc2, 0x7b, 0x18, 0xcb, 0x93, 0xde, ++ 0x56, 0x2c, 0x4f, 0x79, 0x8f, 0x61, 0x79, 0xc6, 0xdb, 0x86, 0xe5, 0x59, ++ 0xef, 0x19, 0x2c, 0xcf, 0x79, 0x3b, 0xb1, 0x6c, 0xf7, 0x5e, 0xc4, 0x32, ++ 0xd6, 0xfc, 0x19, 0xaa, 0x5c, 0x7e, 0x08, 0x7e, 0xc3, 0x15, 0x30, 0x3e, ++ 0x93, 0x67, 0x55, 0x4e, 0xaf, 0x7e, 0xe0, 0x91, 0x75, 0xa1, 0xf9, 0x33, ++ 0x46, 0x3c, 0xb0, 0x09, 0xe5, 0x34, 0x5a, 0xde, 0x8c, 0x1c, 0xf8, 0xa6, ++ 0x2f, 0x25, 0x7a, 0xde, 0x8c, 0xee, 0xf6, 0x28, 0x79, 0x33, 0x82, 0xef, ++ 0x47, 0xcf, 0x9b, 0x91, 0x36, 0xfa, 0xc7, 0xcb, 0x9b, 0x31, 0xd7, 0xf2, ++ 0xc3, 0xe4, 0xcd, 0x98, 0x5b, 0x23, 0xe6, 0x75, 0x98, 0xb7, 0xea, 0xf2, ++ 0x79, 0x33, 0x46, 0xc4, 0x95, 0xdc, 0x82, 0xf2, 0xc7, 0xe5, 0x71, 0xae, ++ 0x25, 0xb6, 0xbc, 0x19, 0x3e, 0xab, 0xc4, 0xbf, 0xcb, 0xa7, 0x74, 0x01, ++ 0xbf, 0x8b, 0xd2, 0x05, 0xd7, 0xeb, 0x1e, 0xf2, 0x0e, 0x1c, 0xb4, 0x3e, ++ 0x3d, 0x04, 0xf6, 0x13, 0x5d, 0x43, 0xae, 0xba, 0x6c, 0xbe, 0x07, 0xad, ++ 0x5c, 0x44, 0xa7, 0x37, 0xcb, 0xef, 0x30, 0xe7, 0x47, 0xce, 0x97, 0xd1, ++ 0x13, 0x5d, 0xd5, 0xfe, 0xef, 0x57, 0xb0, 0x3c, 0x0e, 0x73, 0x2d, 0xdf, ++ 0x32, 0x5f, 0x46, 0x0f, 0xf9, 0x16, 0x0e, 0x66, 0x7f, 0x81, 0x76, 0x32, ++ 0xd6, 0x7c, 0x19, 0x3d, 0xad, 0x0f, 0x3d, 0xd1, 0x73, 0xc6, 0x8f, 0x9c, ++ 0x2f, 0xa3, 0x27, 0xbb, 0xda, 0x93, 0x3d, 0x7d, 0x73, 0x0a, 0xa3, 0x73, ++ 0xef, 0x1e, 0xe8, 0xac, 0x7e, 0x2f, 0x5d, 0x69, 0x6a, 0x3d, 0x84, 0x2f, ++ 0xdb, 0x5d, 0xa8, 0xda, 0x32, 0xff, 0x1e, 0x3e, 0x77, 0xa6, 0x1d, 0xe3, ++ 0x33, 0x1d, 0x3b, 0xf9, 0xbd, 0x38, 0x17, 0x71, 0xd8, 0x53, 0xd9, 0xf7, ++ 0xfa, 0xe0, 0x6f, 0x76, 0x3c, 0x9f, 0x30, 0x9c, 0xe0, 0x77, 0xfc, 0x76, ++ 0xe2, 0xa2, 0xfc, 0x89, 0xe7, 0xcf, 0xa5, 0x9d, 0xfb, 0xf6, 0xc1, 0xbd, ++ 0x80, 0xb5, 0x36, 0xe2, 0x4a, 0x4c, 0x02, 0x67, 0x8f, 0x38, 0xf4, 0x03, ++ 0x61, 0x1f, 0x76, 0x8d, 0x09, 0xe2, 0x35, 0x55, 0xbb, 0x3f, 0x7d, 0xe3, ++ 0x8f, 0x14, 0xae, 0xb9, 0x45, 0x8f, 0xf7, 0xe5, 0x3a, 0x28, 0x0e, 0xad, ++ 0xe8, 0xf7, 0xb9, 0x12, 0x81, 0x6f, 0xf1, 0xe4, 0x97, 0xb8, 0x4f, 0x87, ++ 0x33, 0xba, 0x4b, 0xbd, 0x42, 0xbf, 0xeb, 0xd6, 0xfc, 0x1e, 0x0e, 0xe8, ++ 0x92, 0x1a, 0x3c, 0x7f, 0x2a, 0xd0, 0x5b, 0x70, 0xdf, 0xd4, 0xb5, 0x99, ++ 0xdd, 0x67, 0xd5, 0x93, 0xab, 0x1e, 0x9f, 0x90, 0x8c, 0xf7, 0xc6, 0x89, ++ 0xdf, 0x81, 0xfc, 0x43, 0x3f, 0x75, 0x19, 0xc7, 0xb3, 0x8b, 0x10, 0x67, ++ 0x00, 0xfa, 0xef, 0xb4, 0xe2, 0xfd, 0xd5, 0x25, 0xaf, 0x2d, 0x34, 0xc0, ++ 0xa0, 0x70, 0xde, 0x1a, 0x1a, 0x37, 0xe8, 0x55, 0x24, 0xc6, 0x81, 0x1a, ++ 0xcc, 0xb6, 0xe1, 0x70, 0x6f, 0x2f, 0x5d, 0xbd, 0xbf, 0xe7, 0x73, 0xb5, ++ 0x82, 0x1f, 0xbe, 0x88, 0xc3, 0x4d, 0x29, 0x11, 0xe3, 0x44, 0x9f, 0x2c, ++ 0x28, 0x3a, 0x0c, 0xfe, 0xf3, 0x22, 0x77, 0x19, 0xde, 0xab, 0x48, 0x2b, ++ 0x15, 0xe3, 0x46, 0x84, 0x7f, 0x47, 0x0f, 0xdb, 0x32, 0xf0, 0x33, 0x65, ++ 0xc2, 0xef, 0x75, 0xfa, 0xd9, 0x7d, 0xcf, 0xb0, 0xef, 0xea, 0x9b, 0xb7, ++ 0x20, 0x9e, 0x4b, 0xfd, 0x9a, 0xfb, 0x4b, 0x8d, 0x62, 0x5d, 0xa5, 0xdb, ++ 0x39, 0x2b, 0xbf, 0x97, 0x62, 0x21, 0x96, 0x98, 0xe8, 0xd6, 0x36, 0xf8, ++ 0xf1, 0x09, 0xa3, 0xbf, 0x3d, 0xdd, 0x8c, 0xe9, 0x22, 0xdd, 0xcc, 0x0e, ++ 0x91, 0x6e, 0xf1, 0x43, 0x44, 0xba, 0x68, 0xe9, 0x66, 0x75, 0x8a, 0x74, ++ 0xd1, 0xd2, 0x2d, 0x61, 0xac, 0x18, 0x5f, 0x53, 0xe9, 0xa6, 0xde, 0xa7, ++ 0xfc, 0xa1, 0xe8, 0x96, 0x64, 0xe3, 0xf7, 0x3c, 0x82, 0xf4, 0x2a, 0x31, ++ 0xa5, 0xa2, 0xc9, 0x47, 0x3c, 0x33, 0xe4, 0x00, 0xca, 0xb7, 0x56, 0x1f, ++ 0xfa, 0x58, 0x02, 0xf0, 0x1b, 0x7e, 0x48, 0xbf, 0x64, 0xff, 0x6a, 0x7c, ++ 0xcb, 0x69, 0x95, 0xc1, 0x6e, 0xa5, 0x33, 0xd0, 0x44, 0x5a, 0xc4, 0xde, ++ 0x8b, 0x07, 0x7d, 0x80, 0xfc, 0xbd, 0xc4, 0x89, 0xfa, 0xa0, 0xfe, 0x3e, ++ 0x8a, 0x78, 0xf2, 0x21, 0x97, 0xfb, 0x8f, 0xc8, 0x25, 0x5a, 0xae, 0x98, ++ 0x7e, 0xf0, 0xf8, 0x02, 0xda, 0xba, 0x19, 0xe4, 0x6d, 0x04, 0xfb, 0x3d, ++ 0x1a, 0x18, 0xaf, 0x4a, 0x22, 0xb8, 0x9f, 0x53, 0x88, 0xd3, 0x0e, 0xfb, ++ 0xa8, 0x26, 0xaf, 0xc9, 0xb9, 0x48, 0x81, 0x73, 0x4d, 0xe2, 0x5c, 0x94, ++ 0x0d, 0xe7, 0x99, 0x76, 0x2c, 0x1f, 0xe4, 0xdf, 0x3b, 0x77, 0x0c, 0x25, ++ 0xb8, 0xef, 0x6f, 0x0a, 0x7c, 0x9e, 0x0a, 0xf7, 0x06, 0x1e, 0x1c, 0xd9, ++ 0x39, 0x0d, 0xe2, 0x0f, 0x9e, 0xc5, 0xa4, 0x04, 0xd6, 0xaf, 0x59, 0x09, ++ 0x6c, 0x7d, 0x5d, 0xc6, 0x4b, 0x5b, 0x02, 0x8b, 0xcf, 0x6c, 0x28, 0xd1, ++ 0x11, 0xd7, 0x68, 0xf8, 0x7d, 0x4a, 0x7a, 0xbf, 0x44, 0xc7, 0x6b, 0xb7, ++ 0xbb, 0x5e, 0xbb, 0x01, 0xfc, 0xd1, 0x16, 0x76, 0x3f, 0x80, 0xd8, 0x3b, ++ 0xdf, 0xb8, 0x1d, 0xdb, 0x47, 0xe1, 0xf7, 0xe1, 0x19, 0xba, 0xfa, 0x6b, ++ 0x00, 0x1f, 0xda, 0x1f, 0xbf, 0x2b, 0xee, 0x68, 0xf9, 0xc8, 0xb6, 0x30, ++ 0xc4, 0x0e, 0xb7, 0x37, 0x3f, 0x72, 0x25, 0xdc, 0x6b, 0xdd, 0xa4, 0x8b, ++ 0xfc, 0x3d, 0x73, 0x81, 0x8d, 0xff, 0xfe, 0x1d, 0x7e, 0x3f, 0x65, 0x44, ++ 0x30, 0xdf, 0x42, 0x81, 0x6d, 0x0c, 0xe6, 0x65, 0x78, 0x70, 0x00, 0x1d, ++ 0xa7, 0x7a, 0x7a, 0x17, 0xf2, 0x51, 0x95, 0xcb, 0xeb, 0x38, 0xfd, 0x0f, ++ 0x96, 0x4d, 0x41, 0xfc, 0x5e, 0x68, 0x91, 0x1c, 0x10, 0xaf, 0x2b, 0xd4, ++ 0xdf, 0x71, 0xd3, 0x30, 0x8a, 0xdf, 0xb8, 0xb7, 0x65, 0x7e, 0xaf, 0x97, ++ 0xdd, 0x5f, 0x1f, 0xcd, 0xfb, 0xd7, 0x9a, 0xa9, 0xfe, 0xa2, 0xfd, 0xaa, ++ 0xff, 0x1b, 0xfc, 0x9e, 0x95, 0x97, 0x4e, 0xca, 0x98, 0x0f, 0x71, 0x74, ++ 0x4d, 0x19, 0xde, 0x13, 0xfc, 0xa3, 0xad, 0xf0, 0x30, 0xf0, 0x2b, 0xc7, ++ 0xd5, 0x34, 0x0a, 0xe4, 0x29, 0xbf, 0x25, 0x11, 0xcf, 0x71, 0x3d, 0x1f, ++ 0x12, 0x27, 0x7e, 0x9a, 0xd5, 0x2a, 0xde, 0x07, 0xcc, 0xe1, 0xf7, 0xb6, ++ 0x73, 0xda, 0x88, 0x1f, 0x84, 0xe2, 0xda, 0x63, 0x62, 0xfb, 0xb8, 0x36, ++ 0xb1, 0x7e, 0x9d, 0x66, 0xff, 0x39, 0xdf, 0xc6, 0xf5, 0xd4, 0x46, 0x52, ++ 0x41, 0xee, 0x36, 0x7e, 0xad, 0x97, 0x60, 0xfd, 0xe8, 0xe8, 0x24, 0xce, ++ 0x35, 0x14, 0xdf, 0x8e, 0x45, 0xbd, 0x71, 0xfc, 0x8e, 0xcf, 0x09, 0xfa, ++ 0x89, 0x1d, 0x5f, 0xeb, 0x8b, 0x22, 0xdd, 0x8f, 0x59, 0x6e, 0x63, 0xfc, ++ 0xdb, 0x64, 0x20, 0x68, 0xbf, 0x37, 0x95, 0x59, 0xf0, 0xde, 0xf9, 0xfe, ++ 0xb2, 0x8a, 0xfe, 0xe0, 0x5f, 0x7c, 0x71, 0x97, 0xbb, 0x7f, 0xa4, 0x38, ++ 0x65, 0x88, 0x9f, 0x96, 0xc0, 0xbe, 0xbb, 0x77, 0x25, 0x90, 0xb1, 0x20, ++ 0x87, 0x6b, 0x25, 0x46, 0xef, 0xfa, 0x8c, 0x92, 0x08, 0xeb, 0x96, 0x2a, ++ 0x77, 0xaa, 0x1c, 0xaa, 0xf2, 0x97, 0x51, 0x16, 0xe7, 0x8e, 0x74, 0x0f, ++ 0xf5, 0x33, 0x9b, 0x84, 0x72, 0x96, 0x57, 0x36, 0x44, 0x32, 0x80, 0xfc, ++ 0xec, 0x95, 0x30, 0xfc, 0xd5, 0xbe, 0x86, 0xe2, 0x75, 0x99, 0x75, 0xdb, ++ 0x47, 0xd6, 0xf4, 0x01, 0x7c, 0x3c, 0xcd, 0x9f, 0xe1, 0x7d, 0x32, 0x53, ++ 0x8b, 0xe4, 0x8a, 0x74, 0x4f, 0xe7, 0x61, 0x9b, 0x8d, 0xdd, 0x6f, 0x5c, ++ 0xe3, 0x5b, 0x0d, 0xf7, 0x46, 0x7e, 0x41, 0x95, 0x08, 0xec, 0x54, 0x86, ++ 0xa1, 0x3e, 0x2b, 0x12, 0x7c, 0x1f, 0xd9, 0x88, 0x7e, 0xe9, 0x5d, 0x36, ++ 0x07, 0x7b, 0xcf, 0xc4, 0xf3, 0x20, 0xc9, 0xf5, 0x19, 0x70, 0x9f, 0xa2, ++ 0xbd, 0x79, 0xd2, 0xe4, 0x75, 0x14, 0xcf, 0x27, 0xa8, 0x3e, 0xc0, 0x7a, ++ 0xb5, 0x49, 0x71, 0x22, 0xde, 0xbe, 0x2a, 0x42, 0xf0, 0x9e, 0x2c, 0x8f, ++ 0xd7, 0xf5, 0x9d, 0x46, 0xb6, 0x6c, 0x08, 0xf1, 0x7f, 0x37, 0xdb, 0x72, ++ 0x1b, 0x6d, 0x14, 0x5e, 0xa3, 0x8d, 0x7d, 0x6f, 0xd9, 0xcb, 0xed, 0x94, ++ 0x00, 0x6f, 0xe7, 0x7f, 0xfd, 0xc3, 0x06, 0xf0, 0x3b, 0x2e, 0x1a, 0x91, ++ 0x7f, 0xbd, 0xb9, 0xbf, 0xa9, 0xbe, 0x77, 0x80, 0xd3, 0x67, 0x5c, 0x82, ++ 0x6b, 0x2b, 0xbc, 0x4f, 0xe0, 0x97, 0x9f, 0x51, 0xe3, 0xe3, 0x74, 0xdb, ++ 0x9c, 0x8b, 0x46, 0x41, 0x5c, 0x9e, 0xd2, 0x3b, 0xc4, 0x0e, 0x06, 0xf9, ++ 0xe6, 0x63, 0xf9, 0x51, 0xdc, 0x04, 0xcf, 0x3f, 0x92, 0x2c, 0x3a, 0x94, ++ 0x43, 0xe2, 0x72, 0x39, 0xec, 0xc2, 0x7d, 0x76, 0x1f, 0xea, 0x8d, 0xaa, ++ 0x07, 0x24, 0x20, 0x11, 0xc8, 0x53, 0xa0, 0xda, 0x37, 0xa9, 0x45, 0x0a, ++ 0x58, 0xa9, 0xdc, 0x8f, 0x36, 0x59, 0x02, 0x70, 0x8f, 0x2e, 0xa9, 0x9c, ++ 0xce, 0x3b, 0x19, 0xf2, 0x9a, 0x98, 0x18, 0xbc, 0x56, 0xf9, 0x9c, 0x18, ++ 0xd7, 0xa2, 0xf2, 0x98, 0x03, 0xce, 0x3d, 0xc1, 0xab, 0xf3, 0x10, 0x48, ++ 0x05, 0xf8, 0xaa, 0xdd, 0x53, 0xed, 0xe5, 0xda, 0x44, 0x66, 0x8f, 0xd6, ++ 0x3e, 0x24, 0x63, 0x5e, 0xd4, 0xcd, 0x72, 0x9b, 0x19, 0xe2, 0xa9, 0x59, ++ 0x2e, 0x47, 0x1e, 0xa4, 0x88, 0x4c, 0x92, 0x1d, 0x78, 0xaf, 0xa6, 0x5f, ++ 0x39, 0x71, 0x52, 0x0c, 0x49, 0xfc, 0xc0, 0x5f, 0x27, 0x76, 0xfb, 0x01, ++ 0x54, 0xc9, 0xaf, 0xf9, 0x46, 0x3f, 0x2f, 0xd2, 0x77, 0x5b, 0x17, 0x6d, ++ 0xcc, 0xdf, 0x1e, 0x97, 0xe0, 0xfe, 0x33, 0xd0, 0x6b, 0xf8, 0xe1, 0xce, ++ 0xfd, 0xe0, 0x2e, 0x38, 0xcd, 0xa4, 0x17, 0xbb, 0xff, 0xc5, 0xed, 0x04, ++ 0xf7, 0x6b, 0x0a, 0xf9, 0x7a, 0x37, 0xee, 0x3f, 0x74, 0xec, 0x7b, 0xd1, ++ 0xc0, 0x0d, 0x24, 0xf4, 0x3b, 0x2a, 0xad, 0x9d, 0xd8, 0x64, 0x66, 0xeb, ++ 0xfc, 0xb8, 0xeb, 0xd9, 0xba, 0x37, 0xee, 0xbc, 0x05, 0xd7, 0xbd, 0x6e, ++ 0x3b, 0x51, 0x56, 0x88, 0xeb, 0xd4, 0xc8, 0x96, 0x51, 0x07, 0xe0, 0x9e, ++ 0xc5, 0xc8, 0x0f, 0x99, 0x7e, 0x12, 0x6e, 0x1f, 0xec, 0xf4, 0x0f, 0xd0, ++ 0x29, 0xe7, 0xb0, 0x4f, 0x0f, 0xf4, 0xf9, 0xb6, 0x76, 0x41, 0xcb, 0x6f, ++ 0x12, 0x30, 0x75, 0xd7, 0x87, 0xea, 0xe0, 0x1c, 0x86, 0xea, 0x5b, 0xc8, ++ 0xfb, 0x67, 0x35, 0x76, 0x64, 0xc5, 0xf4, 0x41, 0xb5, 0x18, 0x5e, 0xe6, ++ 0x72, 0xd4, 0xff, 0x1e, 0xa7, 0xde, 0x1d, 0x42, 0x47, 0xed, 0xfb, 0xdd, ++ 0x71, 0x4a, 0xc9, 0xd4, 0xfd, 0xdc, 0x31, 0x10, 0xec, 0xc8, 0x11, 0x3d, ++ 0xdc, 0x0b, 0xe9, 0xc8, 0xa5, 0xf3, 0xa3, 0xf3, 0xdf, 0xc8, 0xf5, 0x25, ++ 0xf1, 0x73, 0xff, 0x64, 0x98, 0xd7, 0xc6, 0x96, 0x1b, 0xcd, 0x20, 0xdf, ++ 0x6b, 0x03, 0x79, 0xf6, 0x62, 0xfa, 0x4e, 0xa2, 0xa9, 0x04, 0x99, 0x97, ++ 0x48, 0x5c, 0x18, 0xcf, 0x19, 0x49, 0x3d, 0x32, 0xc8, 0x8f, 0x51, 0x8b, ++ 0x42, 0x41, 0xfd, 0x41, 0xa5, 0x84, 0x24, 0xa4, 0xc0, 0x3d, 0xb4, 0x22, ++ 0x21, 0xde, 0x43, 0x2c, 0x49, 0x3c, 0xff, 0x4b, 0x00, 0xf9, 0xd2, 0x2d, ++ 0xa7, 0x54, 0x8e, 0x43, 0xef, 0xe5, 0xaa, 0xf2, 0xa9, 0x95, 0x47, 0x55, ++ 0x7e, 0x6b, 0xe1, 0xa0, 0x05, 0xce, 0x07, 0x21, 0x62, 0x4e, 0x4b, 0xbd, ++ 0xd4, 0x84, 0x87, 0x81, 0x46, 0xb2, 0xd9, 0x0e, 0xeb, 0xbb, 0xea, 0x5f, ++ 0xd6, 0x72, 0x7f, 0xae, 0xd6, 0x9c, 0xe9, 0xc7, 0xef, 0x97, 0x7c, 0x19, ++ 0xe8, 0x1f, 0xad, 0xe4, 0xfe, 0x51, 0xad, 0xa5, 0xd0, 0x84, 0xe6, 0x60, ++ 0x5f, 0x32, 0xae, 0xeb, 0x2b, 0x21, 0x7e, 0x42, 0xe9, 0xb0, 0x32, 0x85, ++ 0xd9, 0x79, 0x75, 0x3e, 0x5a, 0xb9, 0xf4, 0x5c, 0xd4, 0x13, 0x7f, 0xc8, ++ 0x3e, 0xc1, 0x23, 0x77, 0xe2, 0x7d, 0x44, 0xcf, 0x45, 0x03, 0x3e, 0x5f, ++ 0xa7, 0xb8, 0x07, 0xc0, 0xfc, 0x55, 0xfa, 0x5c, 0xc3, 0xe9, 0xa3, 0xa5, ++ 0x87, 0x94, 0xc0, 0xf7, 0x9d, 0x9c, 0x2e, 0x3d, 0xe3, 0x9b, 0x63, 0x87, ++ 0x7b, 0xc1, 0x89, 0x26, 0x17, 0x59, 0x8f, 0xf8, 0xe6, 0xe1, 0x3d, 0xee, ++ 0xa6, 0xc0, 0x48, 0x13, 0xac, 0xbf, 0xf7, 0x6a, 0xf0, 0x8d, 0x01, 0xcf, ++ 0x6b, 0x13, 0xc6, 0x84, 0xe3, 0x29, 0x5b, 0xa2, 0xe0, 0x99, 0xcc, 0xf0, ++ 0xbc, 0x8e, 0xb8, 0xff, 0xd8, 0x46, 0xe5, 0x37, 0x67, 0x45, 0x5d, 0x6d, ++ 0x3c, 0xea, 0x15, 0x79, 0x2b, 0x3d, 0x27, 0x5c, 0xaf, 0xb4, 0x7a, 0xa4, ++ 0xea, 0x8d, 0x1a, 0xe7, 0xbd, 0xb6, 0xb2, 0xfe, 0x00, 0x5e, 0xbb, 0xed, ++ 0x41, 0x6f, 0x3c, 0xf1, 0x8c, 0x2e, 0x4e, 0xa5, 0x04, 0xef, 0x57, 0x39, ++ 0xf7, 0xc4, 0xa3, 0x1d, 0xd1, 0xea, 0xd3, 0xe7, 0x7c, 0xfe, 0x9e, 0x78, ++ 0x46, 0xbf, 0x05, 0x8a, 0x7b, 0x06, 0xcc, 0xcf, 0xa3, 0xeb, 0xcc, 0x04, ++ 0x39, 0x19, 0xee, 0x20, 0xbd, 0x8a, 0x29, 0x92, 0xc3, 0x9b, 0xf5, 0xa8, ++ 0xe7, 0xa4, 0x35, 0xb6, 0x7b, 0xf8, 0xaa, 0x7f, 0xa5, 0xfa, 0x55, 0xda, ++ 0x7e, 0xaa, 0x5f, 0xa5, 0xda, 0x63, 0xf5, 0x1e, 0xfc, 0xda, 0x04, 0xf7, ++ 0x7c, 0x90, 0x03, 0xa9, 0x99, 0xca, 0x2d, 0xc5, 0xa7, 0xd6, 0xce, 0xf6, ++ 0x4b, 0x9b, 0x6d, 0xee, 0x45, 0x80, 0x57, 0x3c, 0xc5, 0x3d, 0x0e, 0xf6, ++ 0x8d, 0x43, 0x02, 0x59, 0xec, 0xfb, 0x5f, 0x51, 0x2f, 0xa2, 0xe9, 0x41, ++ 0xbc, 0x46, 0xce, 0x9b, 0x02, 0x32, 0xae, 0x0b, 0x3e, 0xba, 0x2e, 0x64, ++ 0x4b, 0xe1, 0x78, 0xa8, 0xe3, 0x0f, 0x4a, 0x48, 0x64, 0x7c, 0xa4, 0x5a, ++ 0x0e, 0xeb, 0x7d, 0xdf, 0x1c, 0xc2, 0x06, 0xab, 0x26, 0x98, 0x37, 0xa7, ++ 0xef, 0x70, 0xe2, 0x86, 0x75, 0xab, 0xef, 0x48, 0x76, 0x9f, 0x71, 0x4d, ++ 0x02, 0xb3, 0xbf, 0xb5, 0x09, 0x6c, 0xdd, 0x52, 0xcb, 0xcd, 0xb6, 0x92, ++ 0xbb, 0x51, 0xbf, 0x65, 0xe2, 0x33, 0x8e, 0xfc, 0xee, 0x78, 0x03, 0xaa, ++ 0x70, 0xdf, 0x7c, 0x6d, 0x82, 0xeb, 0x2e, 0xa0, 0x87, 0xa9, 0xc8, 0x85, ++ 0xf3, 0xe8, 0x63, 0x27, 0x4e, 0xf0, 0x4b, 0xfb, 0xc8, 0x4d, 0x12, 0x7c, ++ 0x37, 0x9a, 0x54, 0xe9, 0x90, 0xd8, 0x3d, 0x73, 0x12, 0xfc, 0x7e, 0x8b, ++ 0xc2, 0xeb, 0x53, 0xec, 0xc8, 0x05, 0x7d, 0xed, 0x03, 0xfb, 0x6b, 0xe8, ++ 0xdf, 0x12, 0x39, 0xcf, 0xd8, 0xa3, 0x09, 0xea, 0xfd, 0x5e, 0xe6, 0x7f, ++ 0x3a, 0x49, 0x77, 0x1e, 0xaf, 0x47, 0x13, 0x98, 0xff, 0x79, 0x08, 0x52, ++ 0x9f, 0xf4, 0x2a, 0x56, 0xf3, 0x82, 0xa9, 0xe7, 0x39, 0x4e, 0x09, 0xe8, ++ 0xd4, 0x6e, 0xbd, 0x0d, 0x91, 0x6e, 0xbf, 0x20, 0x31, 0x3f, 0x3d, 0x91, ++ 0xd1, 0x4b, 0xbb, 0x4f, 0x00, 0xc2, 0x87, 0xfe, 0xfe, 0xbd, 0x7b, 0x0d, ++ 0x44, 0x36, 0x27, 0x91, 0xe0, 0xef, 0x59, 0xd5, 0x99, 0xd0, 0xbf, 0x8f, ++ 0x27, 0xce, 0x26, 0xb0, 0x57, 0xbb, 0x12, 0x06, 0xf0, 0x73, 0x4c, 0x67, ++ 0x1d, 0xd4, 0x7f, 0x25, 0x77, 0x9a, 0x12, 0x87, 0x06, 0xe5, 0x5d, 0x95, ++ 0xe3, 0x07, 0x27, 0xcc, 0x70, 0x42, 0x2a, 0x52, 0xdb, 0xf5, 0x5d, 0xc3, ++ 0x61, 0x4f, 0x45, 0xe5, 0x7a, 0x27, 0xd0, 0xbf, 0x7d, 0x42, 0xd7, 0x60, ++ 0xcc, 0x41, 0x49, 0x3a, 0x33, 0x99, 0xfc, 0xb8, 0xf4, 0x42, 0xbe, 0x20, ++ 0x95, 0x0f, 0xcd, 0x8a, 0xc0, 0x07, 0x33, 0xec, 0xc3, 0x43, 0xed, 0xa4, ++ 0xd5, 0x30, 0x04, 0xfc, 0xd1, 0x76, 0x29, 0xce, 0x09, 0xf7, 0x2c, 0xda, ++ 0x97, 0x4a, 0x0c, 0x5f, 0xc9, 0xc4, 0xf3, 0x29, 0xc9, 0xc2, 0x3c, 0xd3, ++ 0xe3, 0x99, 0x7f, 0xdd, 0xc1, 0xed, 0xd5, 0x3b, 0x09, 0x59, 0x28, 0x27, ++ 0xaa, 0x3d, 0xa6, 0xf3, 0xab, 0x83, 0x52, 0x3b, 0x0f, 0x8f, 0x11, 0xef, ++ 0x74, 0x90, 0xce, 0x3d, 0xf1, 0xfe, 0xad, 0x70, 0x6e, 0xa5, 0xc9, 0x3f, ++ 0xa9, 0xcd, 0x4f, 0x39, 0x69, 0xa1, 0x05, 0xef, 0x7f, 0x6c, 0xdc, 0x63, ++ 0xc6, 0xfd, 0x6b, 0x57, 0x09, 0x3b, 0xc7, 0xef, 0x6a, 0x31, 0xa2, 0x7d, ++ 0x8e, 0xa6, 0xb7, 0x69, 0x6d, 0xe6, 0x88, 0x71, 0x1c, 0xb5, 0xa4, 0xf4, ++ 0x7b, 0x0b, 0xe8, 0x97, 0xa6, 0xd4, 0x24, 0x82, 0x3d, 0x4c, 0x9b, 0x7b, ++ 0xd2, 0x06, 0x7c, 0xd7, 0xd2, 0xa5, 0x43, 0xf2, 0x5d, 0x73, 0x08, 0xf6, ++ 0x45, 0xaf, 0x2b, 0x11, 0xbf, 0xbb, 0x55, 0xcb, 0xf4, 0xf4, 0x9b, 0x12, ++ 0x17, 0xd1, 0xfe, 0xe9, 0x19, 0x93, 0xb1, 0x54, 0x9f, 0x37, 0x58, 0xe4, ++ 0x88, 0xf7, 0xcd, 0x4f, 0x73, 0xbd, 0x52, 0xe5, 0xf1, 0x4a, 0x3a, 0x22, ++ 0xdf, 0x0f, 0x9d, 0x06, 0x79, 0x3c, 0xef, 0x7e, 0xf3, 0x1d, 0x17, 0x09, ++ 0xde, 0xdf, 0x6f, 0x88, 0x63, 0x74, 0x6c, 0x88, 0x63, 0x74, 0xec, 0x72, ++ 0x8f, 0x4f, 0x78, 0x1a, 0xe4, 0xcd, 0x97, 0x81, 0xfa, 0xb0, 0x58, 0x3d, ++ 0x07, 0xe5, 0xfb, 0x7f, 0x35, 0xcf, 0x94, 0x3a, 0xde, 0x46, 0xaf, 0x29, ++ 0x51, 0xa6, 0x2a, 0xd0, 0xb0, 0x60, 0x8a, 0x19, 0xd6, 0x89, 0x14, 0xe2, ++ 0x9a, 0x3c, 0x1b, 0x94, 0x75, 0xa3, 0x42, 0xe0, 0x3b, 0xa2, 0xc7, 0xbc, ++ 0x3b, 0x12, 0xf3, 0x31, 0x8e, 0x6d, 0x12, 0xef, 0xf9, 0xda, 0xd9, 0xbd, ++ 0xe1, 0xcf, 0x37, 0x16, 0xe0, 0x77, 0xde, 0xa9, 0x64, 0x8d, 0x79, 0x30, ++ 0xa5, 0x47, 0x59, 0x89, 0xce, 0x09, 0xf1, 0x83, 0xf3, 0x0b, 0xde, 0xb7, ++ 0xe9, 0xa8, 0x3c, 0x2d, 0xe8, 0xd3, 0x9a, 0x03, 0xf2, 0xfb, 0xba, 0xe2, ++ 0x26, 0xf6, 0x31, 0x18, 0xea, 0xc2, 0xfd, 0xc9, 0x92, 0x52, 0x83, 0x3f, ++ 0x40, 0xf9, 0x96, 0xdc, 0x40, 0x0d, 0x05, 0xa5, 0xcb, 0x7f, 0x03, 0xf4, ++ 0xa1, 0x54, 0x73, 0x00, 0x80, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xb5, 0x7d, 0x0b, 0x78, 0x54, 0xd5, ++ 0xb5, 0xf0, 0x3e, 0x73, 0xce, 0x3c, 0x92, 0x99, 0x24, 0x33, 0x79, 0x4e, ++ 0x1e, 0xc0, 0x09, 0xe1, 0x9d, 0x10, 0x87, 0x24, 0xbc, 0x1f, 0x4e, 0x9e, ++ 0x44, 0x88, 0x30, 0xbc, 0x04, 0x85, 0xea, 0x80, 0x28, 0xcf, 0x24, 0x88, ++ 0xd6, 0xdf, 0xb6, 0xde, 0xcb, 0xc4, 0x44, 0xf4, 0xa2, 0xb7, 0x45, 0xe9, ++ 0xaf, 0xf4, 0xd6, 0xdb, 0x7f, 0xb0, 0xa2, 0xa8, 0x20, 0x01, 0x82, 0x06, ++ 0x9a, 0xa4, 0x13, 0x40, 0xe4, 0x11, 0x34, 0x08, 0xa8, 0xa8, 0xad, 0x51, ++ 0x29, 0x62, 0x0b, 0xc9, 0x08, 0xea, 0xc5, 0xd6, 0x7b, 0xfd, 0xd7, 0x5a, ++ 0x7b, 0x9f, 0xcc, 0xcc, 0x49, 0x22, 0xd8, 0xde, 0x4e, 0x3e, 0xbf, 0xed, ++ 0x3e, 0x8f, 0xbd, 0xd7, 0x5e, 0xef, 0xb5, 0xf6, 0xda, 0x87, 0x2e, 0xc9, ++ 0x77, 0x13, 0x4b, 0x64, 0xcc, 0xb7, 0xd8, 0xc0, 0xb6, 0x4a, 0x8c, 0x7d, ++ 0x87, 0xbf, 0x1b, 0x43, 0xad, 0xd9, 0x6e, 0x60, 0x2c, 0x89, 0xb1, 0x96, ++ 0x38, 0x3b, 0xb5, 0x4e, 0xe7, 0x0c, 0xc7, 0xd2, 0x84, 0xf0, 0x7e, 0x85, ++ 0x63, 0x69, 0x3e, 0x63, 0xd5, 0xd6, 0xd8, 0x5c, 0x16, 0x87, 0x6d, 0x7f, ++ 0x3f, 0x8b, 0x85, 0xf1, 0x8a, 0x58, 0xea, 0xd2, 0x02, 0x68, 0x5b, 0xac, ++ 0xae, 0x5a, 0x95, 0xb1, 0x25, 0x46, 0xaf, 0xdd, 0x0e, 0xcf, 0x77, 0x4e, ++ 0xba, 0x3c, 0xa4, 0x8e, 0xe1, 0x2f, 0xd8, 0xdf, 0x33, 0x92, 0xb1, 0x2e, ++ 0x23, 0x6b, 0x94, 0xe2, 0xb0, 0x1f, 0x60, 0x6c, 0x0c, 0x43, 0x50, 0xf8, ++ 0xcf, 0xed, 0x56, 0xed, 0xd0, 0x97, 0xf0, 0xff, 0xe1, 0xfd, 0x44, 0x8b, ++ 0x2d, 0x20, 0xc3, 0xb8, 0xcc, 0xa3, 0x5c, 0xec, 0xb0, 0xf0, 0x47, 0xbe, ++ 0x1b, 0x28, 0x1e, 0x4d, 0x66, 0xcc, 0x28, 0x5e, 0x93, 0x9a, 0xde, 0xf8, ++ 0x46, 0xca, 0x65, 0x2c, 0x76, 0x72, 0x11, 0x63, 0x70, 0xdf, 0xca, 0x5c, ++ 0x8f, 0xb2, 0x2c, 0xb8, 0x31, 0x8c, 0xa9, 0x9e, 0x18, 0xc6, 0xa2, 0xd8, ++ 0x33, 0xf6, 0xf3, 0xd9, 0x8c, 0x19, 0xf0, 0x7d, 0x58, 0x47, 0x57, 0xf3, ++ 0xbb, 0xfd, 0x7c, 0x00, 0xc7, 0x1f, 0xfe, 0xe5, 0x4a, 0x0c, 0x83, 0xfb, ++ 0x1f, 0x29, 0xc1, 0x18, 0x57, 0x0e, 0x63, 0x17, 0x1e, 0x3c, 0x15, 0xe3, ++ 0xb6, 0xc1, 0xf5, 0x07, 0xe5, 0x72, 0x3f, 0xf4, 0x6f, 0x47, 0x40, 0xc6, ++ 0x87, 0xf0, 0x92, 0x6f, 0x87, 0x0b, 0xa3, 0x19, 0x7b, 0xc4, 0xee, 0x19, ++ 0x81, 0xeb, 0xba, 0x63, 0xdd, 0x7f, 0x8f, 0xf1, 0xda, 0x42, 0xf7, 0xd9, ++ 0x03, 0x70, 0x31, 0x95, 0xb1, 0x15, 0x7e, 0x19, 0xe7, 0xe6, 0xf0, 0xc2, ++ 0x7f, 0xab, 0xb6, 0x59, 0x19, 0xb3, 0x84, 0xfa, 0x95, 0xf5, 0x09, 0x11, ++ 0x7d, 0xc0, 0x18, 0xe1, 0xb5, 0xd2, 0xcc, 0xd6, 0xd4, 0xdb, 0x7a, 0xd2, ++ 0x63, 0x05, 0xd2, 0x03, 0xe6, 0x5d, 0xb1, 0x7d, 0x8b, 0x29, 0x5d, 0xc5, ++ 0xf9, 0xbd, 0x93, 0xec, 0xd0, 0xbf, 0xa0, 0xc0, 0xab, 0x80, 0xef, 0x0b, ++ 0x0d, 0x31, 0x7e, 0x5f, 0x66, 0x08, 0x9e, 0x25, 0xdb, 0x47, 0x99, 0xd2, ++ 0xe1, 0xd6, 0x47, 0x4d, 0x66, 0x16, 0x80, 0x75, 0x30, 0xa5, 0xdd, 0xc8, ++ 0x6c, 0x84, 0xb5, 0x0a, 0x09, 0xf0, 0xe6, 0x15, 0x78, 0xd3, 0xc3, 0x79, ++ 0xb8, 0xc5, 0x4a, 0xe3, 0xdd, 0xf5, 0x7f, 0x65, 0xbf, 0x19, 0x96, 0xba, ++ 0x18, 0xe6, 0x7a, 0x20, 0x1e, 0x9e, 0x6f, 0x5a, 0x51, 0xc1, 0x72, 0x7b, ++ 0xae, 0xe3, 0xae, 0x3f, 0xa8, 0x65, 0x29, 0x40, 0xbc, 0xbb, 0xfe, 0x4d, ++ 0x62, 0x3e, 0x95, 0x3f, 0xff, 0x60, 0x1e, 0x3c, 0xff, 0xc0, 0x23, 0x5f, ++ 0x20, 0xdd, 0xf4, 0xeb, 0x5c, 0xec, 0x33, 0x7e, 0xd2, 0x11, 0xb1, 0x6e, ++ 0x37, 0x63, 0x00, 0xcf, 0x32, 0x41, 0xef, 0x3b, 0x1f, 0x8d, 0xbc, 0xbf, ++ 0xac, 0xe9, 0x31, 0x1a, 0x67, 0x29, 0xf3, 0x9a, 0x90, 0x9e, 0x77, 0x6d, ++ 0xd4, 0xdf, 0xbf, 0xe9, 0x33, 0xe4, 0xbb, 0x65, 0x4c, 0x09, 0x5d, 0x07, ++ 0x3c, 0x5c, 0x3e, 0x92, 0x65, 0x45, 0x3c, 0xdc, 0x61, 0x8f, 0x49, 0x3c, ++ 0x0f, 0x20, 0x03, 0x8f, 0x8d, 0xfd, 0x0e, 0xde, 0xdf, 0x7d, 0x64, 0x60, ++ 0x9c, 0x37, 0xa7, 0x27, 0x7e, 0xb5, 0xf6, 0xe2, 0x3a, 0xe0, 0x6f, 0x33, ++ 0x63, 0x7f, 0x5e, 0x67, 0xa1, 0xf6, 0xc2, 0x3a, 0x46, 0xed, 0x08, 0xbb, ++ 0x4a, 0xf4, 0x59, 0xdd, 0x74, 0xf2, 0x7e, 0xe4, 0xaf, 0xaa, 0xc6, 0x5d, ++ 0x26, 0x1c, 0xa7, 0xc5, 0xff, 0xa7, 0x84, 0x09, 0xf0, 0x48, 0x61, 0xd3, ++ 0x37, 0x32, 0x32, 0x57, 0x21, 0x73, 0xdf, 0x7b, 0x0e, 0xf0, 0xf9, 0x23, ++ 0x26, 0xb3, 0xef, 0x00, 0x7f, 0xbb, 0x19, 0xe7, 0x9f, 0xf5, 0x46, 0xcf, ++ 0x3d, 0x48, 0xaf, 0x1b, 0xaf, 0x96, 0xd3, 0x7d, 0xfd, 0xfa, 0x17, 0x69, ++ 0xfc, 0x7f, 0x24, 0x9e, 0xf8, 0x67, 0x11, 0xae, 0x3b, 0x17, 0xaf, 0x2b, ++ 0x5f, 0xf6, 0xb6, 0xae, 0x9f, 0xe2, 0xba, 0x80, 0x9f, 0xd9, 0x58, 0x58, ++ 0x97, 0x7c, 0xfd, 0xeb, 0xd2, 0xd6, 0xa3, 0xad, 0x4f, 0xbb, 0x5f, 0x29, ++ 0x03, 0xdf, 0xf5, 0xf2, 0xbe, 0xc6, 0xef, 0x23, 0x84, 0x3e, 0x58, 0xfa, ++ 0xdc, 0xac, 0xf5, 0x69, 0x80, 0x8a, 0xda, 0xe6, 0xcf, 0xfa, 0x77, 0x10, ++ 0x3f, 0xb1, 0xd3, 0x28, 0xbf, 0x1a, 0x3f, 0x2d, 0x13, 0x74, 0xd2, 0xf3, ++ 0x8d, 0x46, 0xc7, 0x6e, 0xfe, 0x68, 0xfa, 0x77, 0x5a, 0x9f, 0x46, 0x3f, ++ 0xe0, 0x7f, 0xa7, 0xc1, 0x89, 0x6d, 0xc0, 0x69, 0x18, 0xd7, 0x93, 0x4f, ++ 0xf4, 0x7c, 0xa1, 0xe7, 0x83, 0x4e, 0x63, 0x47, 0x7f, 0x94, 0x5f, 0x3d, ++ 0x1f, 0x74, 0x4a, 0x6c, 0x41, 0x6f, 0xeb, 0xfa, 0x37, 0xfb, 0x40, 0x5a, ++ 0xd7, 0x52, 0xd5, 0x5d, 0x66, 0x87, 0xfb, 0x77, 0x31, 0xcf, 0x7a, 0x3b, ++ 0xad, 0x67, 0x23, 0x5d, 0xbf, 0xa0, 0x6c, 0x3c, 0xfc, 0x33, 0x94, 0xab, ++ 0xe7, 0x38, 0x5f, 0x77, 0xeb, 0x39, 0x33, 0x97, 0x37, 0x76, 0xdc, 0xe8, ++ 0x47, 0xbd, 0xb9, 0x36, 0x46, 0x4d, 0x71, 0xd8, 0x04, 0xfd, 0x80, 0xce, ++ 0x9d, 0xbb, 0xcc, 0x3e, 0x7c, 0x4e, 0x9b, 0xe7, 0xfc, 0x3a, 0xb7, 0x7b, ++ 0x90, 0x11, 0xf1, 0x5e, 0x4e, 0xed, 0x9f, 0xd7, 0x79, 0xdc, 0x83, 0x06, ++ 0x87, 0xee, 0xdf, 0xfd, 0xab, 0x2b, 0xb1, 0x2a, 0xbc, 0xdf, 0x35, 0x8c, ++ 0x95, 0xa3, 0xdc, 0x77, 0xc6, 0x44, 0xc2, 0xbb, 0xcf, 0x2e, 0x13, 0x3c, ++ 0xfb, 0x90, 0x0e, 0xc8, 0x7f, 0x4a, 0xfb, 0xff, 0x7c, 0x80, 0x3a, 0xe9, ++ 0xb9, 0xf6, 0x31, 0xa8, 0x47, 0xcf, 0x7f, 0xfb, 0x5f, 0xb1, 0x1e, 0x78, ++ 0xbe, 0xeb, 0x5b, 0x73, 0x79, 0x6f, 0xeb, 0x3c, 0x2d, 0xe8, 0x07, 0xea, ++ 0xe5, 0xb4, 0x13, 0xf8, 0xec, 0x76, 0x21, 0x67, 0xb7, 0x37, 0x55, 0x12, ++ 0x5d, 0x96, 0x3c, 0x33, 0xcb, 0x84, 0xfc, 0xcc, 0x1e, 0xe0, 0xf8, 0xb4, ++ 0xc0, 0x1f, 0xea, 0xd7, 0xb6, 0xa8, 0xd8, 0x67, 0x71, 0x1d, 0x8b, 0x1b, ++ 0x24, 0xd2, 0x23, 0x7a, 0x7a, 0xdc, 0xe5, 0x9a, 0xfa, 0x39, 0xea, 0xdb, ++ 0x3b, 0xfd, 0x85, 0xf4, 0x7e, 0x0f, 0xfa, 0xb0, 0xc7, 0x89, 0xbe, 0x77, ++ 0x21, 0x3d, 0x86, 0x85, 0xe8, 0x31, 0xd6, 0xa1, 0x72, 0x78, 0x54, 0xf8, ++ 0x03, 0xbe, 0xb9, 0x43, 0xf0, 0xcd, 0x79, 0x65, 0x8d, 0xc9, 0x00, 0x7a, ++ 0xe4, 0xfc, 0x33, 0x80, 0x6f, 0x00, 0x79, 0x95, 0xc2, 0xdc, 0xbd, 0xe9, ++ 0xc1, 0xfe, 0x0e, 0xce, 0x87, 0x7d, 0xad, 0x47, 0xbf, 0x8e, 0xbe, 0xe0, ++ 0x5f, 0xf6, 0x5c, 0xcd, 0xfa, 0x34, 0x86, 0xeb, 0x1f, 0x65, 0x4a, 0xeb, ++ 0x45, 0xef, 0x68, 0xeb, 0xbf, 0x8b, 0xb9, 0x62, 0x49, 0xef, 0x88, 0xf5, ++ 0xb2, 0x8e, 0x1b, 0x49, 0x5e, 0xab, 0x2d, 0x7c, 0x5e, 0x6d, 0x9d, 0x2b, ++ 0x9a, 0xee, 0x9c, 0x81, 0x7c, 0x51, 0xb5, 0x19, 0xe8, 0x95, 0xd9, 0x73, ++ 0xdd, 0xa8, 0x77, 0x17, 0xf7, 0x02, 0x6f, 0x99, 0x7c, 0xd1, 0x68, 0x81, ++ 0xf7, 0xba, 0x1e, 0x90, 0x5c, 0xa8, 0x6f, 0xfb, 0xa2, 0x83, 0xa6, 0x27, ++ 0xee, 0x12, 0xf8, 0x5a, 0xb9, 0x6d, 0xf1, 0x0c, 0x34, 0x9a, 0x8b, 0x61, ++ 0x3e, 0x39, 0x13, 0xf5, 0xd1, 0x17, 0x6f, 0xc6, 0x24, 0xa2, 0x5c, 0x41, ++ 0x5f, 0xfa, 0x1e, 0x7a, 0x35, 0xc9, 0x1f, 0x9b, 0x71, 0x1d, 0x8c, 0xe3, ++ 0x7b, 0x09, 0xe0, 0x7b, 0x83, 0x74, 0xfd, 0xf4, 0x5b, 0xb6, 0xb9, 0xd0, ++ 0x3d, 0x28, 0xec, 0xb9, 0x15, 0xfe, 0x9b, 0xdc, 0x83, 0xc2, 0xf5, 0x99, ++ 0x8e, 0xae, 0x6c, 0xdb, 0xac, 0xd0, 0xf3, 0x64, 0xb7, 0xdd, 0x26, 0xb4, ++ 0xc7, 0xf1, 0x0e, 0xa1, 0xbf, 0x84, 0x5e, 0xee, 0x5b, 0xbe, 0x60, 0xe1, ++ 0x00, 0xe7, 0xda, 0x1d, 0x0e, 0xb2, 0x6f, 0x6c, 0x8d, 0x83, 0xf4, 0x63, ++ 0x75, 0xd3, 0x16, 0x53, 0xb8, 0xdd, 0xd5, 0xe4, 0x4b, 0x93, 0xb7, 0xb1, ++ 0x0e, 0x3b, 0xf1, 0x59, 0x55, 0xe3, 0x13, 0xf4, 0x1c, 0xe8, 0x5f, 0xd5, ++ 0x01, 0xfd, 0x4a, 0x4b, 0xc7, 0xcf, 0x6f, 0x55, 0xc3, 0xf0, 0x39, 0x4e, ++ 0xd0, 0x51, 0xae, 0x30, 0xa1, 0xfe, 0xee, 0x4b, 0x7f, 0x82, 0xbe, 0xf9, ++ 0xb2, 0x23, 0x6c, 0x9d, 0x23, 0x1c, 0xc2, 0xae, 0x08, 0xfd, 0x7b, 0x2d, ++ 0xfd, 0xa0, 0xc1, 0xad, 0x1f, 0x57, 0xd3, 0x07, 0x1a, 0xdc, 0x1a, 0xdf, ++ 0x6b, 0xeb, 0xd1, 0xf3, 0x7d, 0x5f, 0xf0, 0xe9, 0xe9, 0xc2, 0x98, 0x9f, ++ 0xfb, 0x0b, 0x3a, 0xfa, 0xac, 0x42, 0x7a, 0x84, 0xf5, 0x11, 0x5e, 0x05, ++ 0xf0, 0xdb, 0xd6, 0x6c, 0xf5, 0x3f, 0x04, 0xf0, 0xb6, 0x49, 0x1c, 0x7e, ++ 0x5f, 0x73, 0x14, 0xc1, 0xdf, 0xe9, 0x2c, 0x76, 0x9f, 0x03, 0x3f, 0xaf, ++ 0x2a, 0x75, 0x21, 0xb5, 0x27, 0xf0, 0xc5, 0x54, 0xf4, 0xeb, 0x3c, 0xd3, ++ 0x10, 0x9f, 0x9a, 0x3f, 0xc7, 0x0a, 0x12, 0x22, 0xfc, 0x24, 0x7d, 0xab, ++ 0xf9, 0x37, 0x79, 0xc2, 0x9f, 0xda, 0x1b, 0xe5, 0xce, 0x07, 0x13, 0x09, ++ 0x3f, 0x4f, 0x02, 0xf2, 0xc3, 0x94, 0x9a, 0x8e, 0x39, 0x16, 0x20, 0xd9, ++ 0xad, 0x8e, 0xed, 0xe5, 0x0a, 0x8c, 0x3f, 0xe5, 0x89, 0x8e, 0x39, 0x51, ++ 0xd0, 0x5f, 0xe8, 0xd8, 0xc1, 0xfb, 0x5b, 0x3b, 0x4e, 0x59, 0x5c, 0x8c, ++ 0xd5, 0xb0, 0x57, 0xca, 0x4b, 0xa0, 0x7f, 0x3b, 0xa0, 0x13, 0xc7, 0xbb, ++ 0x56, 0x5b, 0x60, 0xf6, 0x2c, 0x44, 0xf9, 0x5d, 0x0d, 0x7e, 0x92, 0x05, ++ 0xec, 0xd1, 0xea, 0xd3, 0x43, 0x0e, 0xa1, 0xdc, 0xad, 0x6e, 0xaf, 0x28, ++ 0x97, 0xc0, 0xee, 0xac, 0x06, 0x83, 0x23, 0x81, 0x3d, 0xaa, 0x74, 0xc7, ++ 0x06, 0xac, 0xb9, 0xd4, 0x67, 0x13, 0xe0, 0xb9, 0xe7, 0xed, 0xde, 0x65, ++ 0xc4, 0x2f, 0x57, 0xeb, 0xc8, 0x6e, 0xad, 0x3e, 0xad, 0x70, 0xb9, 0x39, ++ 0x92, 0x48, 0xeb, 0x57, 0x00, 0xf6, 0x28, 0x78, 0xaf, 0x2e, 0x1a, 0xfc, ++ 0x55, 0xc0, 0x57, 0x5d, 0xbc, 0xc5, 0x55, 0x9b, 0x49, 0xd7, 0x7d, 0x51, ++ 0xf1, 0xd8, 0x77, 0xab, 0x6a, 0xd8, 0x75, 0x8d, 0x1e, 0xf8, 0x1e, 0xc2, ++ 0x51, 0x67, 0x60, 0x6e, 0x07, 0xb4, 0xad, 0x47, 0x87, 0xc4, 0x75, 0x7c, ++ 0x8f, 0xdd, 0x6e, 0x5d, 0xc7, 0x2a, 0x14, 0xe0, 0x83, 0x83, 0xeb, 0x2c, ++ 0xd4, 0xea, 0xef, 0x17, 0x9a, 0xec, 0x83, 0xd0, 0xee, 0x15, 0x1a, 0x98, ++ 0xb7, 0x37, 0x7d, 0xf9, 0xa4, 0x83, 0xfb, 0x8d, 0xc0, 0xe4, 0xe9, 0x48, ++ 0xe7, 0xaa, 0x23, 0x26, 0x92, 0x77, 0xfc, 0xa1, 0x1f, 0x58, 0x29, 0xf4, ++ 0x51, 0x15, 0x10, 0x28, 0x0e, 0xe0, 0xa9, 0x3c, 0xcd, 0x02, 0xd1, 0xb1, ++ 0xf8, 0x5c, 0xd9, 0xe7, 0x0a, 0xb6, 0x0d, 0x12, 0xfb, 0x24, 0xc2, 0x5f, ++ 0x61, 0xa1, 0xbe, 0xdc, 0x37, 0xdc, 0xd7, 0xdb, 0x56, 0xe1, 0x78, 0x83, ++ 0xc3, 0xf9, 0x84, 0xe3, 0xa9, 0x48, 0x91, 0x2a, 0x94, 0xb0, 0x79, 0x4b, ++ 0x6c, 0x51, 0x11, 0x7d, 0x39, 0xc5, 0x30, 0x0c, 0xd7, 0xc3, 0xe4, 0x68, ++ 0xd7, 0x56, 0xc0, 0xaf, 0x9c, 0x6e, 0x58, 0xb3, 0x1b, 0xd6, 0x2f, 0x0f, ++ 0x80, 0x16, 0xf0, 0xa1, 0xd8, 0x5d, 0xf2, 0x62, 0x68, 0x37, 0x16, 0x4f, ++ 0x91, 0x97, 0x40, 0x5b, 0x6b, 0xe4, 0x76, 0xb5, 0xd6, 0xc0, 0x96, 0x87, ++ 0xe3, 0xe9, 0x05, 0x81, 0x1f, 0xad, 0xfd, 0xc0, 0xe1, 0xd9, 0x8a, 0x74, ++ 0xbf, 0xf4, 0x56, 0xfb, 0x18, 0x2b, 0xe9, 0xab, 0x0c, 0x3b, 0xc9, 0xb9, ++ 0x58, 0x6f, 0xad, 0xe4, 0x0a, 0x50, 0xdc, 0xd4, 0xca, 0x5c, 0x5b, 0xe1, ++ 0x5a, 0x9d, 0xec, 0x61, 0x9c, 0x8f, 0xeb, 0x19, 0xf2, 0xf1, 0x1b, 0x62, ++ 0x1c, 0x97, 0xd9, 0xb0, 0x47, 0x05, 0x7e, 0x6d, 0x74, 0x7c, 0x40, 0xfc, ++ 0xeb, 0x8a, 0x33, 0xdc, 0x9b, 0x09, 0xfd, 0xc0, 0x13, 0x1f, 0xf1, 0x7e, ++ 0xba, 0xe1, 0x4a, 0x26, 0xf0, 0xf7, 0x81, 0x27, 0x3a, 0xca, 0x15, 0x90, ++ 0x07, 0x57, 0xb6, 0xe1, 0xca, 0x40, 0xe8, 0x1f, 0x7a, 0xe2, 0x63, 0x7e, ++ 0x7f, 0x22, 0x0c, 0x09, 0x06, 0xea, 0xf0, 0x13, 0x9f, 0x94, 0xfb, 0x6c, ++ 0x38, 0x2e, 0xd7, 0x67, 0x6c, 0xbb, 0x3b, 0x1b, 0xe7, 0x51, 0x0c, 0x12, ++ 0xc9, 0xa9, 0x72, 0xc0, 0xe4, 0xaf, 0x85, 0xff, 0xad, 0x8b, 0xe5, 0xfc, ++ 0x54, 0x07, 0x3c, 0x82, 0xfc, 0xf7, 0x86, 0xb0, 0xb3, 0xeb, 0x6b, 0x8a, ++ 0x5e, 0xb6, 0x02, 0xff, 0x2b, 0x45, 0x6e, 0x75, 0x0d, 0x8c, 0xe3, 0xc7, ++ 0x80, 0x69, 0xf4, 0xdf, 0xdf, 0x6a, 0x78, 0x94, 0xad, 0x06, 0x8a, 0x53, ++ 0xb0, 0x45, 0x7c, 0xbf, 0x29, 0xd6, 0xad, 0xd1, 0x81, 0x35, 0xb8, 0xb3, ++ 0x67, 0xa1, 0x5e, 0xa8, 0x77, 0x67, 0xcf, 0x8e, 0x41, 0xbc, 0x7a, 0x4f, ++ 0x22, 0x5e, 0xf3, 0xdb, 0xda, 0xa7, 0xa0, 0x3e, 0x6e, 0x78, 0xfb, 0xfd, ++ 0x31, 0xe8, 0xaf, 0x22, 0xbd, 0x70, 0x9c, 0xfc, 0x36, 0x88, 0xdd, 0x60, ++ 0x3d, 0x97, 0x5e, 0xeb, 0xb7, 0x45, 0x0e, 0x8b, 0x47, 0x3f, 0x70, 0x14, ++ 0xbe, 0xe3, 0x00, 0x39, 0x96, 0xdc, 0xdc, 0x9f, 0x94, 0x54, 0x3b, 0x5b, ++ 0x04, 0x72, 0x57, 0xeb, 0x66, 0xaa, 0x09, 0xd6, 0x95, 0xa2, 0x8b, 0xeb, ++ 0x1a, 0x18, 0xd7, 0x2f, 0xcf, 0xdb, 0x3d, 0x7f, 0xc4, 0xf7, 0x58, 0x46, ++ 0x80, 0xec, 0x4d, 0xa1, 0xc3, 0xfb, 0x31, 0xce, 0xaf, 0x8f, 0x57, 0x59, ++ 0x7b, 0x7c, 0xaf, 0x7a, 0x59, 0xaf, 0xb7, 0x4c, 0xb9, 0x0f, 0xc8, 0xe8, ++ 0xe7, 0xc4, 0xa7, 0x37, 0xbe, 0xb7, 0x04, 0xf5, 0xfb, 0xef, 0xcd, 0xae, ++ 0xc1, 0x2a, 0xc2, 0xe5, 0x66, 0x0f, 0x00, 0x3c, 0x3b, 0x0d, 0x4c, 0x61, ++ 0xf1, 0xc4, 0x26, 0xc3, 0x94, 0x02, 0x8c, 0x3f, 0xa3, 0x5d, 0x1b, 0x50, ++ 0xee, 0x5d, 0xcc, 0xe9, 0x03, 0x39, 0xc3, 0x30, 0x8d, 0x80, 0x84, 0x5f, ++ 0xe2, 0x98, 0xb0, 0xb8, 0x55, 0xac, 0x07, 0xde, 0x2f, 0x61, 0xd0, 0x8e, ++ 0x45, 0xf8, 0x6e, 0xa0, 0xf5, 0xc9, 0xc8, 0x57, 0xa3, 0x98, 0x47, 0x46, ++ 0xfd, 0x35, 0x86, 0xf9, 0xad, 0xd8, 0x76, 0x35, 0xbf, 0xe6, 0x44, 0xbc, ++ 0x3d, 0x19, 0xc5, 0xee, 0x40, 0xbf, 0xcf, 0xb2, 0x8d, 0xb9, 0xfd, 0x61, ++ 0xfa, 0x63, 0x40, 0x3c, 0xf7, 0xf7, 0x26, 0x25, 0x18, 0x09, 0xee, 0x68, ++ 0x63, 0xfd, 0x6c, 0xe4, 0xd7, 0xe8, 0x2f, 0x98, 0x1d, 0xfd, 0xaa, 0xae, ++ 0xff, 0x34, 0x29, 0x38, 0x3e, 0x08, 0xc8, 0x74, 0xbc, 0xee, 0x3a, 0x6c, ++ 0x60, 0x08, 0xe7, 0x0b, 0x46, 0xbf, 0x3d, 0x0e, 0xfa, 0xc1, 0xe1, 0x8a, ++ 0xfa, 0x2c, 0x0b, 0x8d, 0xd7, 0x25, 0xe8, 0xad, 0x8d, 0xfb, 0xa4, 0x49, ++ 0x1d, 0xee, 0x40, 0x7d, 0x93, 0xc0, 0xfb, 0x2f, 0x14, 0x72, 0xfb, 0x1c, ++ 0xfc, 0xdc, 0xe4, 0x7f, 0x36, 0x13, 0xf1, 0x63, 0x59, 0xe3, 0x0f, 0x93, ++ 0x2f, 0x67, 0x3c, 0xf7, 0x5b, 0xbd, 0x49, 0x45, 0xf1, 0xf1, 0xd0, 0xd6, ++ 0x37, 0x47, 0x33, 0x9c, 0x7f, 0x6c, 0x4b, 0xb4, 0x01, 0xe9, 0xf0, 0xf2, ++ 0xf6, 0xbc, 0x28, 0xe4, 0x87, 0x9d, 0x88, 0x1b, 0x58, 0x7f, 0xbc, 0xd9, ++ 0x7e, 0x0f, 0x8e, 0x17, 0x7f, 0x05, 0xe0, 0xcd, 0xa4, 0xeb, 0x6e, 0xc2, ++ 0xab, 0xa2, 0x8e, 0x8a, 0x03, 0xbc, 0x4e, 0x98, 0x66, 0x53, 0x37, 0x00, ++ 0xde, 0x5f, 0x88, 0xaa, 0x9f, 0x86, 0xfc, 0x1f, 0xdc, 0x61, 0x60, 0xcf, ++ 0xc2, 0x14, 0x3b, 0x4d, 0xae, 0x59, 0xd8, 0xdf, 0x79, 0x59, 0xb5, 0xa3, ++ 0xbe, 0x7d, 0x21, 0xb3, 0x3e, 0x9a, 0xd6, 0xb3, 0xc3, 0x40, 0xeb, 0xd9, ++ 0x19, 0x1d, 0x1c, 0xb1, 0x16, 0xe0, 0xde, 0x30, 0x4c, 0x29, 0x47, 0xf8, ++ 0x14, 0x2b, 0x53, 0x50, 0x0f, 0x2b, 0x86, 0x22, 0xf5, 0x1e, 0xb8, 0x3e, ++ 0x34, 0x9e, 0xdb, 0x57, 0x4d, 0x2f, 0x2f, 0x88, 0xe7, 0xf2, 0xf3, 0xa4, ++ 0x04, 0xf3, 0xe7, 0xe1, 0x73, 0x85, 0x24, 0x3f, 0xa5, 0xb2, 0x8d, 0xe4, ++ 0xae, 0x2b, 0xc8, 0xfc, 0x66, 0x98, 0x27, 0x69, 0x6e, 0xbb, 0x8c, 0xf4, ++ 0x88, 0x9e, 0x05, 0xac, 0x84, 0x7c, 0xaf, 0x04, 0x64, 0x06, 0xfd, 0x49, ++ 0x1e, 0x46, 0x49, 0x8d, 0x49, 0x36, 0xa3, 0x5f, 0x25, 0x7d, 0xeb, 0xb6, ++ 0x2d, 0x06, 0xba, 0x4f, 0x11, 0xfa, 0x76, 0xca, 0x87, 0xab, 0x2b, 0x78, ++ 0xdc, 0xe3, 0x3a, 0x3d, 0x11, 0xc6, 0x3b, 0x68, 0x33, 0x32, 0x5c, 0xd7, ++ 0x64, 0xd6, 0x21, 0xa3, 0x3f, 0x38, 0xf9, 0x2a, 0x73, 0x05, 0x90, 0x7f, ++ 0xae, 0xf2, 0x78, 0xc6, 0x0e, 0x7f, 0xe8, 0x3f, 0x3d, 0xaf, 0xf3, 0x07, ++ 0x4b, 0xc5, 0x78, 0xee, 0xa0, 0xbd, 0x04, 0x2f, 0x17, 0xb2, 0x48, 0x3f, ++ 0xae, 0x74, 0x73, 0xd9, 0xe7, 0x12, 0xcd, 0xa3, 0x2a, 0x68, 0xa7, 0x8b, ++ 0x2d, 0xba, 0xfb, 0xe8, 0xe7, 0xc5, 0x62, 0x1b, 0x19, 0x37, 0x95, 0xc5, ++ 0x0b, 0xff, 0xa6, 0x3f, 0xeb, 0xff, 0x1d, 0xe9, 0x37, 0xe0, 0x5e, 0x98, ++ 0xef, 0x3e, 0x3b, 0x9f, 0xaf, 0x54, 0xce, 0xf9, 0x15, 0xae, 0xaf, 0xab, ++ 0xdc, 0xe4, 0x42, 0x3c, 0xec, 0xb2, 0xb9, 0xdf, 0x9d, 0x88, 0x7a, 0xb1, ++ 0xdd, 0xc8, 0xb6, 0xb2, 0xbe, 0xe5, 0xe9, 0x79, 0x88, 0x3f, 0xfd, 0xe0, ++ 0x73, 0x0c, 0xbb, 0x6a, 0x65, 0xfe, 0x7c, 0xe2, 0x47, 0x1b, 0xae, 0x67, ++ 0xc4, 0xe6, 0x8d, 0xbe, 0x28, 0x58, 0xf7, 0x88, 0x41, 0x7c, 0x7c, 0xe4, ++ 0x3b, 0xd4, 0x23, 0x43, 0xff, 0x33, 0x31, 0x01, 0xf5, 0xf8, 0x55, 0xa1, ++ 0x5f, 0xb4, 0x56, 0xe3, 0x33, 0xe4, 0x27, 0x7b, 0x1c, 0xe7, 0x27, 0xfb, ++ 0x0d, 0x21, 0x39, 0xbc, 0x33, 0x3e, 0x93, 0x9e, 0xd3, 0xe4, 0x0a, 0xf9, ++ 0x0c, 0xc7, 0xd9, 0x6f, 0xf4, 0x2f, 0xf4, 0xf4, 0x62, 0x27, 0x81, 0x3f, ++ 0xef, 0x44, 0xfe, 0xdc, 0x65, 0x63, 0x14, 0x47, 0x3d, 0x96, 0x6a, 0x59, ++ 0x80, 0x72, 0xa5, 0xcd, 0xf3, 0xbc, 0xe0, 0x63, 0x7d, 0xbb, 0xbe, 0x66, ++ 0x6d, 0xab, 0x11, 0xd7, 0xfd, 0x15, 0xd8, 0x03, 0x80, 0xbb, 0x24, 0xed, ++ 0xaa, 0x29, 0xdc, 0x9e, 0xef, 0x49, 0xe2, 0x7c, 0x55, 0x2a, 0x7f, 0x4b, ++ 0xfe, 0x76, 0x67, 0x93, 0xc4, 0xd0, 0xcf, 0x4f, 0x6e, 0xe2, 0xfa, 0x3b, ++ 0x9c, 0x3f, 0x52, 0x7b, 0xe7, 0x8f, 0x5f, 0x22, 0x5e, 0xaf, 0xc5, 0x1f, ++ 0x5a, 0xbc, 0xb0, 0xfb, 0x87, 0xf2, 0xc7, 0x91, 0xbf, 0x8f, 0x3f, 0x36, ++ 0x5c, 0x93, 0x3f, 0xbe, 0x8d, 0x45, 0x3c, 0xdc, 0xd7, 0x5c, 0x9c, 0xc2, ++ 0xbe, 0xc7, 0xbf, 0x69, 0x14, 0xfc, 0xd0, 0xd7, 0xfd, 0xf1, 0x56, 0xae, ++ 0xe7, 0xf4, 0xd7, 0x5f, 0x11, 0x78, 0xdd, 0x67, 0xda, 0x38, 0x3d, 0x17, ++ 0xf5, 0xc0, 0xcd, 0x06, 0x17, 0xca, 0x39, 0x50, 0x3f, 0x7d, 0x36, 0xac, ++ 0x63, 0x5f, 0x34, 0x7f, 0x8f, 0x29, 0x6b, 0xb2, 0xb0, 0xbf, 0x4b, 0xe1, ++ 0x7a, 0x65, 0x57, 0x93, 0x99, 0xf4, 0xca, 0x2e, 0x9b, 0xd7, 0x4b, 0x76, ++ 0xdc, 0x69, 0x61, 0xe8, 0x3f, 0x30, 0xc5, 0xdb, 0xf1, 0x33, 0xd4, 0x87, ++ 0x69, 0x16, 0x75, 0x43, 0x18, 0xff, 0x2e, 0x8d, 0xe7, 0xfc, 0x56, 0x6f, ++ 0x0c, 0x8c, 0xff, 0x0c, 0xfd, 0xe2, 0xa3, 0x9c, 0xce, 0xe3, 0x6e, 0xce, ++ 0x93, 0x4d, 0xf0, 0x5c, 0xea, 0x52, 0x2e, 0xe7, 0x05, 0x17, 0x4c, 0x5b, ++ 0x30, 0x0e, 0x2b, 0x4d, 0x28, 0xdc, 0x81, 0x7c, 0x74, 0x02, 0x75, 0x16, ++ 0xb4, 0xd5, 0xe7, 0xe0, 0x29, 0x40, 0x7c, 0xd5, 0x39, 0x13, 0xe9, 0xbb, ++ 0xd7, 0x5a, 0x4e, 0x96, 0x61, 0x7e, 0x11, 0xfc, 0x1e, 0x37, 0xf2, 0xd9, ++ 0xd8, 0xfd, 0x27, 0xcb, 0x8a, 0x72, 0xf0, 0x79, 0xae, 0x4f, 0xf7, 0x8a, ++ 0x56, 0xeb, 0x8f, 0xc7, 0x35, 0xc5, 0xb3, 0xee, 0x78, 0xd7, 0x23, 0xec, ++ 0xc6, 0x78, 0xc6, 0xf5, 0x92, 0x07, 0xf9, 0x24, 0x37, 0xd4, 0x67, 0x6e, ++ 0x23, 0xc5, 0x6b, 0x1a, 0x3f, 0xd4, 0x47, 0x03, 0x3f, 0x80, 0x5c, 0xcc, ++ 0x67, 0xaa, 0x31, 0x16, 0x86, 0x9c, 0x73, 0xce, 0xf3, 0x30, 0x98, 0x43, ++ 0x36, 0xa7, 0x3c, 0x92, 0xce, 0xf3, 0x03, 0xd3, 0x28, 0x3e, 0x9c, 0x7b, ++ 0xba, 0xfd, 0x55, 0xd0, 0xcc, 0x6c, 0x9e, 0x47, 0x77, 0x5f, 0xf0, 0xc1, ++ 0x7c, 0x1d, 0x1f, 0x80, 0x9d, 0x3d, 0x1e, 0x8f, 0xfe, 0xd2, 0xf1, 0x80, ++ 0xc9, 0x80, 0xf3, 0x99, 0xd6, 0x64, 0x73, 0x7f, 0x68, 0x4d, 0x16, 0xf2, ++ 0x93, 0x26, 0x4f, 0xf4, 0x03, 0x3c, 0xd5, 0xff, 0x61, 0xd8, 0xb3, 0x1b, ++ 0xc2, 0xec, 0x7b, 0x6c, 0x02, 0x97, 0xa3, 0xc7, 0x5d, 0x0a, 0xdd, 0xf7, ++ 0x75, 0x98, 0xfc, 0x83, 0xe1, 0xd2, 0xbf, 0x33, 0xfe, 0x5e, 0xbd, 0xb0, ++ 0x3f, 0x9f, 0xa3, 0x3c, 0x63, 0xfc, 0x70, 0xdf, 0x2b, 0x0b, 0xd1, 0x8e, ++ 0xe6, 0x2f, 0x77, 0x1f, 0x44, 0xfc, 0x4f, 0x4f, 0x92, 0xe9, 0xfa, 0x2f, ++ 0x58, 0xc0, 0x92, 0x85, 0xf4, 0x71, 0x29, 0xe4, 0x97, 0xd5, 0x1b, 0xd5, ++ 0xe2, 0xcf, 0xa4, 0xd0, 0x73, 0x4c, 0xf1, 0x0c, 0xb3, 0xc1, 0xfd, 0xfd, ++ 0x49, 0xd1, 0xf9, 0x38, 0x7f, 0x69, 0x82, 0xf7, 0x22, 0xd2, 0x89, 0x29, ++ 0xc1, 0x23, 0xf8, 0xde, 0xd8, 0x09, 0x79, 0xf9, 0x28, 0x5f, 0xb6, 0x51, ++ 0x75, 0x09, 0x68, 0x8f, 0x34, 0xb8, 0x01, 0xae, 0xf2, 0xad, 0xb6, 0x10, ++ 0x1c, 0x1a, 0x5c, 0x67, 0x05, 0x5f, 0x94, 0x26, 0x2c, 0xbe, 0x88, 0xeb, ++ 0xc7, 0xf7, 0x50, 0xbf, 0x34, 0x7e, 0x7c, 0xde, 0x82, 0xef, 0x6b, 0x74, ++ 0xaf, 0x6f, 0xfe, 0x82, 0xd3, 0x3b, 0x8c, 0xfe, 0x48, 0xef, 0x10, 0xfd, ++ 0xa5, 0x3b, 0xb0, 0xaf, 0xe1, 0xe1, 0x2b, 0xa1, 0x57, 0xb4, 0xfe, 0x3f, ++ 0x4a, 0x7f, 0x2d, 0x7f, 0x70, 0x4d, 0xfa, 0x63, 0x7e, 0x20, 0xf6, 0xef, ++ 0xa2, 0xbf, 0x35, 0x21, 0x29, 0x44, 0x7f, 0xf0, 0xb3, 0xe2, 0xb1, 0xaf, ++ 0xf7, 0xb3, 0xea, 0x4d, 0xe0, 0x77, 0xe7, 0xf4, 0xbc, 0x5e, 0xe8, 0x28, ++ 0xa4, 0xe7, 0x5d, 0x26, 0x58, 0x21, 0xfa, 0x55, 0x2d, 0x10, 0x77, 0xa2, ++ 0x3c, 0x7a, 0x1d, 0xb4, 0x2f, 0xb0, 0xc7, 0xce, 0xe7, 0xea, 0xfa, 0xc3, ++ 0xf9, 0xfe, 0xe0, 0x22, 0xb2, 0xc1, 0x09, 0xf1, 0x84, 0xf7, 0x6a, 0x53, ++ 0x70, 0x08, 0xfa, 0x21, 0xa3, 0x02, 0x12, 0xf9, 0x85, 0xa3, 0x40, 0xf0, ++ 0x17, 0x91, 0xff, 0x95, 0x41, 0x7a, 0xcf, 0x25, 0xf0, 0xc4, 0xce, 0x4b, ++ 0xd2, 0xf9, 0x61, 0xdc, 0x45, 0xff, 0x2e, 0x1d, 0xfd, 0xc3, 0x40, 0x02, ++ 0xfa, 0x51, 0xa3, 0xcc, 0x15, 0x01, 0xe4, 0xf7, 0xdd, 0xd6, 0x29, 0xe9, ++ 0xe8, 0xd7, 0xe5, 0x59, 0x27, 0x65, 0x21, 0x5f, 0xbd, 0x3a, 0xec, 0xbe, ++ 0xe3, 0x68, 0x82, 0x5e, 0x4d, 0x5b, 0xbe, 0xe7, 0x39, 0x35, 0xe4, 0xff, ++ 0x68, 0xfa, 0xed, 0xa0, 0x18, 0x56, 0x9b, 0xbf, 0x20, 0x81, 0xeb, 0xa1, ++ 0x1b, 0x41, 0xdd, 0xa2, 0x1f, 0x88, 0x2e, 0x63, 0x38, 0x1c, 0x9a, 0x3e, ++ 0x47, 0xf2, 0x20, 0x1c, 0x52, 0x60, 0xbe, 0xe1, 0x3b, 0x2b, 0xe9, 0xe5, ++ 0xa6, 0x0e, 0xa0, 0xc7, 0x8d, 0x08, 0x07, 0xe0, 0xa1, 0x55, 0x62, 0x0d, ++ 0xa8, 0xcf, 0x0b, 0x0d, 0xee, 0xc4, 0x62, 0xf4, 0xd3, 0x92, 0x02, 0x0a, ++ 0xf7, 0xf7, 0xbe, 0xe9, 0x8f, 0xf9, 0xc1, 0x8a, 0xa6, 0x37, 0xde, 0x43, ++ 0x78, 0x2b, 0x70, 0x3f, 0x04, 0xe3, 0x50, 0x97, 0xf1, 0x62, 0x77, 0x3e, ++ 0x62, 0x60, 0x4f, 0x3f, 0x58, 0xf3, 0x57, 0xb4, 0xb8, 0x40, 0xf3, 0x67, ++ 0xb4, 0xf8, 0x13, 0xfd, 0x1e, 0xbc, 0x3f, 0x40, 0x5c, 0xb7, 0x9b, 0x01, ++ 0x40, 0xb4, 0x47, 0x01, 0x8b, 0xbf, 0x06, 0xe6, 0x7f, 0xf2, 0xb2, 0x3a, ++ 0xdc, 0x2d, 0xe4, 0x56, 0x81, 0x75, 0x54, 0x88, 0x75, 0xcc, 0x64, 0xed, ++ 0x04, 0x17, 0xfb, 0xf6, 0xbb, 0xef, 0x26, 0x01, 0x7d, 0x66, 0x08, 0x7c, ++ 0x54, 0x1c, 0x81, 0xb8, 0x31, 0x17, 0xef, 0x33, 0x76, 0x33, 0xe0, 0xe1, ++ 0x66, 0x85, 0xc7, 0x93, 0x37, 0xbb, 0x20, 0x7e, 0x0c, 0xe3, 0xa3, 0x99, ++ 0xe3, 0x22, 0xfb, 0xf8, 0x9b, 0x92, 0x1c, 0x1a, 0xe7, 0x5a, 0xcf, 0xeb, ++ 0xed, 0xc0, 0x44, 0xdd, 0xfe, 0xcc, 0x3f, 0xda, 0x1e, 0x01, 0x7b, 0xf4, ++ 0x09, 0xb8, 0xce, 0xc7, 0xd6, 0xf1, 0xb8, 0x74, 0xc2, 0x40, 0xd9, 0xa7, ++ 0xa0, 0xe1, 0x1c, 0x97, 0x69, 0x40, 0x7e, 0xac, 0x16, 0xf6, 0x0d, 0xc2, ++ 0xe8, 0x5e, 0xed, 0xd2, 0x4b, 0xc2, 0x2f, 0x9e, 0x60, 0xe8, 0xc8, 0x75, ++ 0x01, 0x7e, 0x5b, 0xf7, 0xff, 0x8d, 0xec, 0xe0, 0x81, 0xfd, 0x7f, 0x7b, ++ 0x07, 0xfd, 0xbc, 0xf1, 0x9f, 0x2b, 0xcc, 0x0c, 0xef, 0x4f, 0xf8, 0xbc, ++ 0x20, 0x0e, 0xf5, 0x04, 0x1b, 0xa7, 0x12, 0x5f, 0x69, 0xe3, 0x56, 0xff, ++ 0xa9, 0xc1, 0xca, 0xf8, 0x75, 0xe2, 0xff, 0x2a, 0xb1, 0xf6, 0xc3, 0x00, ++ 0x8f, 0x7b, 0x28, 0xc2, 0x67, 0xa1, 0xf6, 0x77, 0x17, 0x9f, 0xdc, 0x84, ++ 0xe3, 0x7d, 0x79, 0x4e, 0xe1, 0xbc, 0x2d, 0xe6, 0x2f, 0x33, 0x79, 0x07, ++ 0x61, 0x1e, 0xbb, 0xcc, 0xc4, 0xf3, 0x01, 0x87, 0x25, 0xee, 0xff, 0x68, ++ 0xf7, 0x0f, 0x1b, 0x01, 0x6e, 0xb8, 0xbe, 0x29, 0x41, 0xcb, 0x0b, 0xb4, ++ 0x93, 0xdd, 0xc7, 0x9f, 0x39, 0x8c, 0xce, 0x37, 0x63, 0x3e, 0x20, 0x2f, ++ 0x44, 0xd7, 0x9b, 0x2f, 0x94, 0x7f, 0xae, 0xe4, 0xf6, 0xa4, 0x0f, 0xfe, ++ 0xfe, 0x37, 0xf2, 0x01, 0x5a, 0x1e, 0x60, 0xab, 0xc0, 0x1f, 0x3b, 0x78, ++ 0xd6, 0xa4, 0x02, 0x5c, 0x53, 0x1b, 0xee, 0x51, 0xd0, 0xbf, 0x9e, 0xea, ++ 0x94, 0x99, 0x3b, 0x6c, 0xde, 0x9b, 0x54, 0x2b, 0x73, 0x87, 0xe5, 0x03, ++ 0x9e, 0x49, 0xd0, 0xf9, 0x23, 0x07, 0x5f, 0xdc, 0x34, 0x03, 0xec, 0x49, ++ 0x75, 0x9b, 0xec, 0x8a, 0x42, 0x79, 0x6d, 0xda, 0x75, 0x3c, 0x17, 0xfb, ++ 0xed, 0xb2, 0xcb, 0xda, 0x0b, 0x1f, 0xe9, 0xf1, 0x3b, 0xb5, 0xe9, 0x1e, ++ 0x05, 0xf9, 0xdf, 0x98, 0xa8, 0x92, 0x7c, 0x5f, 0x6b, 0xfe, 0x09, 0x23, ++ 0x80, 0x4f, 0x6e, 0x40, 0xba, 0x33, 0xf2, 0xeb, 0x3a, 0xc7, 0x48, 0x24, ++ 0x47, 0x7a, 0xfa, 0x1e, 0xd8, 0xff, 0xeb, 0x84, 0x8e, 0x9c, 0xbe, 0xf1, ++ 0xdd, 0x17, 0xfd, 0xf5, 0x74, 0xf8, 0xdd, 0xc5, 0x22, 0xda, 0xef, 0xb9, ++ 0x16, 0x3d, 0xf4, 0x7c, 0xdb, 0x02, 0xeb, 0xf4, 0xc1, 0xfa, 0x02, 0xb0, ++ 0x4e, 0x1f, 0xf8, 0x5d, 0x07, 0xd6, 0xd9, 0xa9, 0x7f, 0x68, 0x9d, 0x93, ++ 0xfa, 0x1a, 0xbf, 0x56, 0x37, 0xff, 0x36, 0x01, 0xfd, 0x36, 0x8d, 0x4f, ++ 0x4b, 0x13, 0x38, 0xdf, 0x8c, 0xdf, 0xb7, 0x29, 0x81, 0xd9, 0x42, 0xf4, ++ 0xd2, 0xf0, 0xf5, 0xa1, 0xb0, 0x57, 0x7b, 0xa3, 0x34, 0x7f, 0xc3, 0x35, ++ 0x6f, 0x06, 0x5c, 0x3a, 0x05, 0x76, 0x87, 0x18, 0xd4, 0xc7, 0xda, 0x9d, ++ 0x63, 0x42, 0xf6, 0x6b, 0xfe, 0xe9, 0x32, 0xf2, 0x37, 0x34, 0xfb, 0x35, ++ 0x5f, 0x5e, 0x54, 0x4a, 0x6a, 0x53, 0xd8, 0x2f, 0x4c, 0x23, 0xa3, 0x5e, ++ 0xd3, 0xdb, 0xa9, 0xb9, 0xea, 0x62, 0x23, 0xeb, 0xcd, 0x3e, 0x2d, 0x88, ++ 0xec, 0x97, 0xb7, 0x6d, 0x54, 0x62, 0xa8, 0x67, 0x20, 0x3a, 0x49, 0x92, ++ 0xc0, 0x87, 0xf0, 0xb3, 0x35, 0x38, 0xce, 0x30, 0x0f, 0xc1, 0xa9, 0xa7, ++ 0xa7, 0x06, 0x97, 0x1e, 0x1e, 0x6d, 0x7d, 0x9a, 0x7f, 0x3d, 0x5f, 0xd0, ++ 0x6f, 0xce, 0xa0, 0x4c, 0x23, 0xc2, 0xdf, 0xc3, 0xae, 0x8a, 0x75, 0xe2, ++ 0x40, 0x98, 0x87, 0xb8, 0x5e, 0xbb, 0xfa, 0xb5, 0x8e, 0x9f, 0xaf, 0x5c, ++ 0x28, 0x79, 0x2b, 0xb7, 0x17, 0xbe, 0xed, 0x8b, 0x7f, 0xf5, 0xf7, 0x35, ++ 0x7d, 0x50, 0x86, 0x13, 0xe4, 0x51, 0xeb, 0x43, 0xbf, 0xc2, 0x98, 0x98, ++ 0x4c, 0x74, 0x2b, 0xbb, 0x6a, 0x62, 0x6e, 0xb0, 0x1b, 0x2c, 0x23, 0x8a, ++ 0x7d, 0x1a, 0x66, 0x57, 0x58, 0xc5, 0x50, 0xe2, 0x9f, 0x7b, 0x85, 0x1d, ++ 0xee, 0x8b, 0x7f, 0xaa, 0xae, 0xca, 0xcc, 0x9b, 0x1f, 0xe2, 0x23, 0x63, ++ 0xe3, 0x13, 0x56, 0xe4, 0xa3, 0x7d, 0xca, 0x46, 0x2b, 0xe6, 0x27, 0x27, ++ 0xdb, 0x66, 0xd5, 0xc6, 0x01, 0x9e, 0x4a, 0xfe, 0x54, 0x34, 0x17, 0xfd, ++ 0xbc, 0xea, 0x0e, 0x03, 0xc3, 0x14, 0x56, 0x69, 0xd3, 0x17, 0x07, 0x31, ++ 0xae, 0xaf, 0x7e, 0x8f, 0xb9, 0x50, 0x2f, 0x16, 0x35, 0xb5, 0x16, 0x23, ++ 0xdf, 0x1d, 0x52, 0xda, 0x65, 0x8a, 0xb3, 0xbf, 0x64, 0xec, 0x89, 0x30, ++ 0x7f, 0xb1, 0xb1, 0xa9, 0xd6, 0x8a, 0xfe, 0x54, 0x63, 0xa2, 0x4c, 0x71, ++ 0xfc, 0x61, 0x07, 0xe7, 0x4b, 0xed, 0xfe, 0x96, 0x44, 0xae, 0x3f, 0x1a, ++ 0xcf, 0x5d, 0x9e, 0xe1, 0xee, 0xe5, 0xfe, 0x19, 0x71, 0xbf, 0xe4, 0xe3, ++ 0x3c, 0xe2, 0xa3, 0xb2, 0x47, 0x41, 0xae, 0x31, 0x0e, 0x4d, 0x8a, 0xa1, ++ 0xbc, 0x44, 0x89, 0x64, 0x9f, 0x53, 0x81, 0x7e, 0xc8, 0x4d, 0x46, 0xf2, ++ 0xf3, 0x21, 0x8e, 0xf9, 0x23, 0xee, 0x03, 0x5e, 0x6a, 0x34, 0xef, 0xc2, ++ 0xd4, 0x7e, 0x69, 0xe3, 0x23, 0xf7, 0xd8, 0x81, 0x10, 0xf5, 0xff, 0xfd, ++ 0x69, 0x8d, 0x19, 0xf3, 0x0b, 0xb3, 0x24, 0xd7, 0xb3, 0xf0, 0x5c, 0x99, ++ 0x1a, 0x6c, 0xc5, 0x7e, 0xd9, 0xdc, 0x4c, 0xaa, 0x7b, 0x18, 0xfb, 0x3f, ++ 0x32, 0xf9, 0xb3, 0xc1, 0x5b, 0x25, 0xca, 0x8b, 0x94, 0x01, 0xbb, 0x60, ++ 0xbf, 0x6c, 0x51, 0xa6, 0x1f, 0xf3, 0x13, 0xfb, 0x25, 0xde, 0xf7, 0x35, ++ 0xf3, 0x7d, 0x02, 0x66, 0xf7, 0x25, 0xcc, 0x80, 0x79, 0xde, 0xae, 0x48, ++ 0x18, 0xb5, 0x81, 0x78, 0x4a, 0xeb, 0x0f, 0xce, 0xdb, 0xc0, 0x04, 0x23, ++ 0x87, 0xc5, 0x57, 0xf7, 0xed, 0x95, 0x49, 0xcf, 0xdc, 0x57, 0x2a, 0xf9, ++ 0x71, 0xbf, 0xa9, 0xd4, 0x9e, 0xce, 0x7c, 0x61, 0x7c, 0x55, 0xf6, 0xa8, ++ 0x89, 0xd6, 0x35, 0xbb, 0x29, 0xa5, 0x08, 0xf9, 0x78, 0x4e, 0xb9, 0xcc, ++ 0xfc, 0x61, 0xfc, 0x1d, 0x10, 0x7e, 0xe1, 0x3c, 0x0f, 0xc4, 0xe1, 0x61, ++ 0xef, 0x1d, 0x8e, 0xe2, 0x70, 0x05, 0x17, 0x03, 0xdc, 0x52, 0x48, 0x6e, ++ 0xa7, 0x09, 0x3e, 0x9f, 0xc5, 0xb8, 0x9f, 0x38, 0x7f, 0x41, 0x42, 0xc4, ++ 0x7b, 0xf0, 0xc6, 0x2d, 0x68, 0x8f, 0x6e, 0x6d, 0x82, 0x38, 0x15, 0x7a, ++ 0xd3, 0x44, 0xfc, 0x7a, 0xab, 0x37, 0x3d, 0x62, 0x5e, 0x0f, 0xe3, 0x7e, ++ 0xcd, 0x09, 0x16, 0x2c, 0x89, 0x83, 0xf1, 0xfb, 0x25, 0x0d, 0x24, 0xfe, ++ 0x9b, 0x11, 0xb4, 0x8f, 0x0e, 0xa8, 0xa8, 0x77, 0xce, 0x24, 0xa2, 0x5e, ++ 0x63, 0xc3, 0xb8, 0x9c, 0x68, 0x72, 0x57, 0x2a, 0xaf, 0xae, 0x23, 0x7e, ++ 0x70, 0xf2, 0x7d, 0xb2, 0x79, 0x12, 0x48, 0x93, 0x8c, 0xfa, 0x2f, 0x52, ++ 0x9e, 0x66, 0x8e, 0x8b, 0xec, 0xcf, 0x72, 0xf7, 0xa8, 0x37, 0x88, 0x90, ++ 0x7f, 0xbd, 0x5e, 0xd7, 0xe4, 0x7e, 0x5e, 0xb3, 0x4c, 0xfb, 0x72, 0xf3, ++ 0x0a, 0x25, 0x17, 0xeb, 0x45, 0x3f, 0xe8, 0xfd, 0xec, 0xb1, 0xd1, 0x7d, ++ 0xe8, 0x85, 0x6f, 0xd5, 0x87, 0xe3, 0x7a, 0xd3, 0x0b, 0x1f, 0x96, 0xff, ++ 0x5d, 0x7a, 0xe1, 0x35, 0x08, 0x2b, 0xc6, 0x81, 0xfc, 0xfe, 0x34, 0x51, ++ 0xe8, 0x87, 0x7e, 0xac, 0x1f, 0xea, 0x87, 0x52, 0x79, 0xfb, 0x26, 0xe4, ++ 0x97, 0x2e, 0xb0, 0x77, 0xe6, 0x5e, 0xf8, 0x45, 0xb3, 0x17, 0x5a, 0x3c, ++ 0x5e, 0x06, 0xf2, 0x4a, 0xf2, 0x7e, 0x91, 0xef, 0x67, 0x94, 0x5e, 0x4d, ++ 0x65, 0xbe, 0xfc, 0x50, 0x3c, 0xde, 0xad, 0x2f, 0xc0, 0x9f, 0x70, 0xf5, ++ 0xe2, 0xe7, 0x3c, 0x9d, 0x98, 0x45, 0x72, 0xd4, 0xad, 0x5f, 0x34, 0xfd, ++ 0x11, 0xe6, 0x4f, 0x18, 0xc7, 0xfc, 0xe3, 0xfe, 0x44, 0x29, 0xf8, 0x91, ++ 0xa6, 0x3c, 0x84, 0x2f, 0x83, 0xe0, 0x2b, 0x63, 0x3c, 0x1f, 0x58, 0x86, ++ 0x85, 0x43, 0x98, 0x97, 0x73, 0x7e, 0x41, 0xf9, 0x96, 0x6a, 0x88, 0xf3, ++ 0x29, 0xde, 0x67, 0xbf, 0x25, 0xb8, 0x50, 0xcf, 0x49, 0xf1, 0x21, 0x39, ++ 0xd0, 0xfb, 0x19, 0x5a, 0x5e, 0xd7, 0x2a, 0xf2, 0x08, 0x7a, 0xbe, 0xe8, ++ 0xce, 0xf3, 0xcd, 0x35, 0x52, 0x1d, 0x8c, 0xc6, 0x17, 0x65, 0x76, 0x2e, ++ 0x1f, 0x65, 0x73, 0x65, 0xca, 0xbb, 0xeb, 0xf9, 0x44, 0x9b, 0x4f, 0xcf, ++ 0x1f, 0x01, 0x5d, 0x5e, 0xe6, 0x9a, 0xfc, 0x21, 0xe4, 0xec, 0x87, 0xf2, ++ 0x47, 0x73, 0xa2, 0xd8, 0x57, 0x1d, 0xc4, 0x06, 0x5d, 0x0f, 0x5f, 0x68, ++ 0xfc, 0xa0, 0xf1, 0x87, 0xde, 0x8e, 0x1c, 0xd3, 0xe5, 0x67, 0xfa, 0xb2, ++ 0x23, 0x6f, 0xa2, 0x1d, 0x19, 0xdd, 0xb7, 0x1d, 0x79, 0x7d, 0x98, 0x91, ++ 0xf4, 0xb5, 0xde, 0x7e, 0x68, 0xf6, 0xe2, 0x77, 0x49, 0x5c, 0x2f, 0x67, ++ 0x24, 0xf2, 0x7d, 0x8e, 0x69, 0xc3, 0xe7, 0xd9, 0xd0, 0xef, 0xb0, 0x26, ++ 0xf1, 0x3a, 0x0d, 0xcd, 0x0e, 0x75, 0xe7, 0x97, 0x36, 0x73, 0x7e, 0x78, ++ 0xbd, 0x63, 0x89, 0x22, 0xa1, 0x3d, 0x41, 0xbd, 0x90, 0x19, 0x86, 0x7f, ++ 0x91, 0x6f, 0xd5, 0xf8, 0xaf, 0xea, 0x51, 0x89, 0xf2, 0x8d, 0x15, 0x42, ++ 0x2f, 0x75, 0x36, 0xf3, 0xfc, 0x5b, 0x75, 0x89, 0xec, 0xb7, 0xc0, 0xff, ++ 0x16, 0x37, 0x3d, 0xb1, 0x89, 0xf7, 0x8d, 0x94, 0x9f, 0x2b, 0x54, 0x5a, ++ 0x15, 0x0b, 0x8c, 0x3b, 0xd3, 0x25, 0xb9, 0x30, 0xaf, 0xe3, 0x16, 0xf9, ++ 0xba, 0x19, 0x6e, 0x89, 0xe7, 0xeb, 0x5c, 0x91, 0xfb, 0xf4, 0x2d, 0x3a, ++ 0xfa, 0xce, 0x11, 0x7c, 0x34, 0x93, 0x05, 0xeb, 0xd0, 0x1f, 0xd7, 0xeb, ++ 0xa5, 0x39, 0x57, 0xb9, 0x5f, 0xa0, 0xd7, 0x4f, 0x73, 0xc4, 0xbe, 0xfb, ++ 0x1c, 0xdd, 0xbe, 0xfb, 0x55, 0x4d, 0xde, 0x07, 0xb0, 0x01, 0xff, 0x4c, ++ 0x7f, 0xc0, 0x9c, 0xf4, 0xfd, 0xfe, 0x80, 0xf6, 0xbe, 0x46, 0x47, 0x8d, ++ 0x7e, 0x2a, 0xee, 0xc5, 0xa1, 0x1c, 0x1d, 0xfc, 0xc6, 0xa4, 0xc6, 0x70, ++ 0xff, 0x19, 0xe9, 0x37, 0xf5, 0xaa, 0x42, 0xe3, 0xd8, 0x93, 0x04, 0x5f, ++ 0x0a, 0x7f, 0xe6, 0xcb, 0x8b, 0x79, 0xbf, 0xa0, 0x98, 0x4f, 0x3c, 0x5f, ++ 0xdd, 0xf4, 0x85, 0xc9, 0x3b, 0xb2, 0x6f, 0xf8, 0xaf, 0xe5, 0xb7, 0xc6, ++ 0xa2, 0x9f, 0x3e, 0x3a, 0xe4, 0xb7, 0x6b, 0xf3, 0x4e, 0x53, 0x18, 0x4b, ++ 0x47, 0xc7, 0x4c, 0x67, 0x4f, 0x66, 0x89, 0xeb, 0x3f, 0xd4, 0x7e, 0x0c, ++ 0xd7, 0xad, 0x43, 0xa3, 0x83, 0xa6, 0x47, 0x7b, 0xe0, 0x59, 0xe8, 0xd9, ++ 0xbe, 0xe8, 0x74, 0x2d, 0x3d, 0xab, 0xe9, 0xb3, 0x7f, 0xb6, 0x9e, 0xd5, ++ 0xc6, 0xd7, 0xec, 0x80, 0x36, 0xaf, 0x5e, 0xff, 0xf6, 0x15, 0xb7, 0x69, ++ 0xfa, 0x74, 0xfd, 0x16, 0x03, 0xe5, 0x4b, 0x26, 0x8b, 0xf8, 0x78, 0xb2, ++ 0xc8, 0xc3, 0xce, 0x4f, 0xe2, 0xf1, 0xc1, 0xad, 0x49, 0x3c, 0xee, 0xec, ++ 0xfa, 0xca, 0x62, 0x40, 0x7b, 0xb9, 0xb3, 0x85, 0xfb, 0x27, 0x2e, 0xb3, ++ 0xfd, 0x38, 0xfa, 0x05, 0xa1, 0x7c, 0x1f, 0xa7, 0xe7, 0xc3, 0x31, 0xcc, ++ 0x87, 0xfb, 0xec, 0x4c, 0x69, 0xb7, 0xd0, 0xbe, 0x67, 0x11, 0x90, 0x12, ++ 0xf7, 0x3d, 0xd3, 0xf8, 0xbe, 0xe7, 0x76, 0x25, 0xe0, 0x21, 0x3d, 0xed, ++ 0x52, 0x58, 0x0d, 0xc8, 0xc9, 0x39, 0x7c, 0x0f, 0xe6, 0x79, 0xf8, 0x80, ++ 0x6f, 0x21, 0xea, 0xe9, 0x87, 0x3f, 0x19, 0x62, 0xa0, 0xfd, 0x77, 0x25, ++ 0xd0, 0x8e, 0xfe, 0xc9, 0xd8, 0x3c, 0x85, 0xf6, 0x8f, 0x1c, 0x66, 0x95, ++ 0xf2, 0xc1, 0x9d, 0xcd, 0x66, 0x3b, 0xbe, 0xd7, 0xb5, 0xef, 0xff, 0xb4, ++ 0x1a, 0x71, 0x9c, 0xaf, 0x98, 0x0b, 0x43, 0xb8, 0x43, 0xcd, 0xe6, 0xee, ++ 0xfd, 0x1b, 0xd4, 0x07, 0xa5, 0x72, 0x9b, 0x8c, 0xf9, 0xfb, 0xae, 0x20, ++ 0xc8, 0x08, 0x3c, 0x3f, 0x69, 0x41, 0xa0, 0x18, 0xe3, 0xa0, 0xc9, 0xac, ++ 0xbd, 0x16, 0xe5, 0x7b, 0x02, 0xd2, 0xb1, 0x17, 0xfa, 0xfd, 0x2a, 0x49, ++ 0x8b, 0xb3, 0x7b, 0xcf, 0xef, 0x17, 0x37, 0x73, 0x3f, 0xae, 0x38, 0x46, ++ 0x26, 0x3f, 0x6e, 0x8a, 0xaf, 0xbd, 0x18, 0xf7, 0xad, 0xa6, 0x28, 0x92, ++ 0xab, 0x16, 0x9f, 0xd5, 0xe5, 0xf7, 0x5f, 0xd1, 0xc5, 0x1f, 0xa1, 0xfc, ++ 0xbe, 0xaa, 0xf0, 0xfa, 0x43, 0x5d, 0xfe, 0xbe, 0x91, 0xeb, 0x99, 0xeb, ++ 0xcd, 0xeb, 0x4f, 0x40, 0xdd, 0x06, 0x7c, 0xbc, 0x5e, 0xe3, 0x73, 0xa1, ++ 0x6f, 0x58, 0x1f, 0xf9, 0xfd, 0x9d, 0x26, 0xbe, 0xef, 0x13, 0x3c, 0x69, ++ 0x64, 0xe8, 0x07, 0xb3, 0x0b, 0x89, 0xbd, 0xe6, 0x63, 0xae, 0x95, 0xe7, ++ 0xdf, 0xd7, 0x12, 0xed, 0x56, 0x63, 0x71, 0x9f, 0x8e, 0xfb, 0xeb, 0xfb, ++ 0x5a, 0xd2, 0xdc, 0x6a, 0x6e, 0xdf, 0xcf, 0xe7, 0x76, 0x04, 0x8b, 0xd0, ++ 0x3c, 0xee, 0xdc, 0x3e, 0x5b, 0xa1, 0xfa, 0x35, 0x91, 0x1f, 0xed, 0xb1, ++ 0x7f, 0xd2, 0xc7, 0xfe, 0x88, 0xbb, 0xd1, 0x7e, 0x08, 0xd5, 0x69, 0x5f, ++ 0xfb, 0x21, 0xc5, 0x5f, 0xaa, 0x94, 0xf6, 0xb9, 0x5e, 0xbc, 0x69, 0x75, ++ 0x0b, 0x4c, 0xd4, 0x3f, 0xdd, 0xc8, 0xb4, 0x9f, 0x9b, 0xe4, 0x74, 0xe7, ++ 0xf9, 0x68, 0x37, 0xf2, 0xf9, 0xce, 0xf3, 0x69, 0x6e, 0x84, 0xeb, 0x79, ++ 0xc1, 0xa7, 0x1a, 0xdf, 0xef, 0x3b, 0x77, 0x39, 0x9a, 0xf6, 0x41, 0x4d, ++ 0x6e, 0x15, 0xf7, 0x8f, 0x83, 0x0e, 0x8b, 0xeb, 0x59, 0xe2, 0x5b, 0xce, ++ 0xef, 0xf5, 0xa9, 0x43, 0xfc, 0xb8, 0x4f, 0xfb, 0x1b, 0x21, 0x17, 0x3b, ++ 0xa3, 0x83, 0xc7, 0xb2, 0x13, 0xc3, 0xf7, 0x3d, 0xf8, 0x3e, 0x47, 0xcb, ++ 0xba, 0x47, 0x67, 0x9f, 0x33, 0xd2, 0x7e, 0xb9, 0x84, 0xf9, 0x48, 0x6d, ++ 0x7f, 0xd9, 0x07, 0x72, 0x43, 0x75, 0x3d, 0xf1, 0x8c, 0xe2, 0x0f, 0x23, ++ 0xab, 0x67, 0x38, 0x6f, 0xad, 0x9b, 0xfd, 0x1a, 0xdb, 0x29, 0x93, 0xd4, ++ 0x38, 0xc4, 0xfb, 0xe5, 0x44, 0x6d, 0x1f, 0x53, 0x8d, 0xa3, 0x3c, 0xc4, ++ 0xb7, 0x57, 0xa8, 0xce, 0x50, 0x8f, 0xff, 0xdd, 0xeb, 0x98, 0x07, 0xeb, ++ 0x51, 0x1a, 0xd6, 0x59, 0x3c, 0x0a, 0xc8, 0xff, 0xab, 0xeb, 0xec, 0xd4, ++ 0x6f, 0x5c, 0xe7, 0xa4, 0x76, 0xff, 0x3a, 0x95, 0xda, 0x87, 0x8e, 0xc7, ++ 0x3e, 0x80, 0x76, 0xbf, 0xda, 0x6d, 0xf2, 0x28, 0x61, 0xfa, 0xe3, 0x9d, ++ 0x64, 0xee, 0x77, 0xe5, 0x65, 0x7f, 0x52, 0x4c, 0xc5, 0xdf, 0x7f, 0x63, ++ 0x54, 0x87, 0x3e, 0xe5, 0xc1, 0x0e, 0x19, 0xf5, 0xc5, 0x8d, 0x57, 0x61, ++ 0x1d, 0x11, 0x75, 0x27, 0xca, 0x65, 0xc4, 0x37, 0xe5, 0x37, 0xb3, 0x42, ++ 0xfd, 0x4c, 0x69, 0x71, 0x0c, 0xf6, 0x6f, 0xbc, 0x0a, 0xfd, 0xb0, 0xe7, ++ 0xaf, 0x24, 0x39, 0xb8, 0x3d, 0xaa, 0x53, 0xea, 0x46, 0x27, 0x93, 0xb4, ++ 0x10, 0x5f, 0xfc, 0x2d, 0xc9, 0xdd, 0x91, 0x04, 0xd7, 0xef, 0x71, 0x78, ++ 0x3e, 0xc1, 0x76, 0xb7, 0x34, 0xff, 0xe0, 0x25, 0x46, 0xfd, 0x73, 0xbc, ++ 0x7f, 0xab, 0x7c, 0x09, 0x9e, 0xcb, 0x0f, 0x14, 0x52, 0x5e, 0x39, 0x1f, ++ 0xf3, 0xca, 0x79, 0x34, 0xec, 0x42, 0xc4, 0xdf, 0xe8, 0x56, 0x13, 0xed, ++ 0x97, 0x6b, 0xf9, 0xdd, 0x3c, 0x4d, 0xfe, 0xbe, 0x8e, 0xcc, 0x33, 0xe7, ++ 0x8b, 0xbc, 0xee, 0xab, 0xac, 0x83, 0xf2, 0xcd, 0x05, 0x16, 0x08, 0xb4, ++ 0x0c, 0x08, 0x17, 0xa7, 0x9f, 0x5b, 0x9a, 0xe7, 0x94, 0x30, 0x1f, 0x98, ++ 0x64, 0x72, 0x61, 0xbd, 0xc3, 0xe8, 0x2c, 0x4f, 0x3e, 0xe6, 0x63, 0x5b, ++ 0x93, 0x18, 0xc5, 0x47, 0xad, 0xad, 0xc9, 0x19, 0x6a, 0x0e, 0x72, 0x0f, ++ 0xcf, 0xfb, 0xba, 0xb5, 0xbc, 0x2f, 0xfb, 0xfe, 0xbc, 0xef, 0x91, 0x8f, ++ 0x62, 0x7d, 0xa4, 0xb7, 0xae, 0x9a, 0x68, 0x7f, 0xfa, 0xc8, 0xa9, 0x58, ++ 0x57, 0x80, 0xf6, 0x0b, 0x2d, 0xe4, 0xff, 0x69, 0xf5, 0xc8, 0x2d, 0xd1, ++ 0xbc, 0xce, 0x80, 0x65, 0x2c, 0xa0, 0x3c, 0xd3, 0x8d, 0xa2, 0x9e, 0xd1, ++ 0x62, 0xf6, 0x9a, 0x93, 0x49, 0x5f, 0x05, 0x0e, 0x9e, 0x80, 0xf7, 0x7e, ++ 0x7f, 0x99, 0xf1, 0x7d, 0xc7, 0xf6, 0x0f, 0x69, 0x5f, 0xbb, 0xd8, 0x30, ++ 0x3c, 0x05, 0xeb, 0x7e, 0x0f, 0x4a, 0x43, 0xe3, 0xb0, 0x7d, 0xea, 0xa3, ++ 0xd8, 0x1c, 0x6a, 0x4f, 0xc5, 0x5e, 0x44, 0xfc, 0xb4, 0x18, 0xac, 0x2a, ++ 0xce, 0x7b, 0x66, 0x9d, 0x5a, 0x82, 0x75, 0x6d, 0x27, 0xd6, 0xb1, 0x12, ++ 0xac, 0x63, 0x7b, 0x6b, 0x9d, 0x85, 0xda, 0x93, 0xeb, 0xec, 0xd4, 0x9e, ++ 0x5a, 0xe7, 0xa4, 0xf6, 0x75, 0xb8, 0x8e, 0xfc, 0x73, 0x1c, 0x9e, 0x47, ++ 0x7e, 0x71, 0xbf, 0x65, 0xa3, 0x7d, 0x92, 0x29, 0x6f, 0xd9, 0x14, 0x6c, ++ 0xf3, 0x16, 0xc6, 0x50, 0xbb, 0xfb, 0xb6, 0x18, 0x13, 0xc2, 0xdb, 0x12, ++ 0xcb, 0xb6, 0x6b, 0xf3, 0x60, 0xbd, 0x5a, 0x20, 0x3a, 0xd0, 0x80, 0xc9, ++ 0xfe, 0xd6, 0xa7, 0xbc, 0x8f, 0x59, 0xfa, 0x81, 0xdd, 0x33, 0x7b, 0x47, ++ 0x4a, 0xa3, 0x18, 0x6b, 0x7b, 0xca, 0x3b, 0x5d, 0x99, 0x0c, 0xe3, 0x4e, ++ 0xed, 0xff, 0x93, 0xaf, 0xe0, 0xfe, 0x9b, 0xc9, 0xcb, 0x1e, 0xb3, 0x00, ++ 0x5c, 0x73, 0x4f, 0xd9, 0x1a, 0xda, 0xa0, 0xff, 0x76, 0xf2, 0xf2, 0xc7, ++ 0x6c, 0xa8, 0x6f, 0x8f, 0x47, 0x83, 0xd2, 0xc3, 0xf5, 0xae, 0x38, 0xee, ++ 0x1e, 0x04, 0x74, 0x43, 0xa5, 0x90, 0xc6, 0x05, 0x97, 0x8d, 0x83, 0x7e, ++ 0x82, 0xd6, 0x5f, 0x31, 0xbd, 0x64, 0x12, 0x63, 0xb7, 0x14, 0x77, 0x64, ++ 0x33, 0x60, 0xad, 0xec, 0xe4, 0x95, 0xd3, 0x2d, 0x80, 0xc7, 0x5b, 0xac, ++ 0xde, 0x1f, 0x63, 0xdf, 0xe4, 0x4b, 0x9a, 0x5e, 0xd2, 0x0f, 0xfb, 0xcc, ++ 0x87, 0xf5, 0x60, 0x41, 0xc9, 0x48, 0x71, 0x3f, 0xcb, 0x90, 0x12, 0xb1, ++ 0xfe, 0x65, 0xa6, 0xc3, 0xfb, 0x46, 0x72, 0x58, 0xfd, 0x9e, 0x5b, 0xfa, ++ 0x13, 0xed, 0x33, 0x8d, 0x71, 0x4b, 0xcc, 0x41, 0x87, 0x1f, 0x8c, 0xb4, ++ 0xef, 0xc5, 0xec, 0x1f, 0x27, 0x84, 0xcb, 0xdb, 0x4c, 0x47, 0xe9, 0x1b, ++ 0x48, 0x8f, 0x89, 0xc9, 0xbc, 0x0e, 0x78, 0xf4, 0x24, 0xc9, 0x1d, 0x5e, ++ 0x5f, 0xa1, 0x7f, 0x6e, 0xf4, 0x39, 0xb5, 0x04, 0xe9, 0x34, 0xe6, 0x42, ++ 0x59, 0x1d, 0xb6, 0x33, 0xcb, 0x1d, 0xd4, 0xf7, 0x2c, 0x18, 0x5b, 0x87, ++ 0xf2, 0x5c, 0x62, 0xeb, 0xeb, 0xfd, 0x62, 0x7a, 0xbf, 0x3c, 0x99, 0xd7, ++ 0x8d, 0x14, 0x29, 0x52, 0x44, 0x5d, 0x89, 0xfe, 0xb9, 0x7c, 0x60, 0x26, ++ 0xf4, 0x8f, 0x83, 0x47, 0xa3, 0x29, 0x4f, 0x30, 0xfa, 0xb4, 0xb7, 0x16, ++ 0xeb, 0x4f, 0x4b, 0x9d, 0x99, 0x79, 0xb2, 0xa6, 0xfa, 0xa8, 0xef, 0xd8, ++ 0x82, 0xfb, 0x6d, 0xa3, 0x2b, 0xce, 0x94, 0x24, 0xa0, 0xfc, 0xd8, 0x24, ++ 0x17, 0x9a, 0x89, 0x31, 0xac, 0xa3, 0x2e, 0x01, 0xee, 0x17, 0xda, 0xb1, ++ 0xa0, 0x0a, 0xd7, 0xf5, 0x44, 0x31, 0xd6, 0xff, 0x8c, 0x56, 0x25, 0x17, ++ 0xa2, 0xad, 0xd0, 0xdd, 0xda, 0x80, 0xef, 0x17, 0xba, 0x62, 0x5c, 0x85, ++ 0xe8, 0x8f, 0x9f, 0x56, 0x4b, 0xd0, 0xf4, 0x9c, 0x52, 0x46, 0x9d, 0x28, ++ 0x80, 0xe7, 0xa6, 0x0e, 0x92, 0x5d, 0x16, 0x18, 0xe8, 0x54, 0xe0, 0xa6, ++ 0x89, 0x97, 0xa0, 0x5f, 0x38, 0x2c, 0x8e, 0xf2, 0xbc, 0x85, 0xca, 0x9a, ++ 0x2b, 0x27, 0xa8, 0x1f, 0xe3, 0xaa, 0x51, 0x71, 0x1d, 0x5b, 0x7e, 0x5d, ++ 0x45, 0xe3, 0x98, 0xc9, 0xae, 0xef, 0x9e, 0x51, 0xfc, 0x2f, 0xc8, 0x3f, ++ 0x45, 0x9e, 0x38, 0xca, 0x09, 0x02, 0x3e, 0x4a, 0xc2, 0xeb, 0xca, 0x60, ++ 0xdd, 0x04, 0x77, 0xa1, 0x5d, 0xf6, 0x47, 0x49, 0xc8, 0xdf, 0xff, 0x5a, ++ 0x62, 0x87, 0xfe, 0xee, 0xfe, 0x12, 0x96, 0xcb, 0xc3, 0x7c, 0xc3, 0xff, ++ 0x42, 0xf7, 0x8f, 0x44, 0xab, 0x51, 0x00, 0xe8, 0x6e, 0x93, 0xbd, 0x04, ++ 0xc7, 0xdb, 0x6d, 0x92, 0xec, 0x0f, 0x51, 0xdf, 0x53, 0x8c, 0xcf, 0xfb, ++ 0x86, 0x18, 0x55, 0xcc, 0x1f, 0x95, 0x25, 0x46, 0x45, 0x8c, 0x3f, 0xb5, ++ 0x44, 0x1a, 0x7f, 0x0e, 0xe1, 0xcf, 0x89, 0x1b, 0x85, 0xd7, 0xca, 0x33, ++ 0x1c, 0x11, 0xf7, 0xdb, 0x6e, 0xb3, 0x92, 0x9d, 0xa8, 0x78, 0x2b, 0x87, ++ 0xfc, 0xa2, 0xb6, 0xdb, 0xd2, 0xc9, 0x5e, 0x54, 0xbc, 0x35, 0xa9, 0x08, ++ 0xdb, 0x36, 0x03, 0xf7, 0xd3, 0x2b, 0xde, 0xaa, 0x28, 0xa7, 0xfb, 0x06, ++ 0x1e, 0x07, 0x57, 0x2c, 0xfc, 0x91, 0x5b, 0xf4, 0x29, 0xee, 0xad, 0x58, ++ 0x58, 0x49, 0xfd, 0x56, 0x29, 0xe5, 0x27, 0x38, 0xdf, 0x95, 0x9c, 0xb8, ++ 0x3c, 0xcc, 0xaf, 0x4d, 0x1b, 0x94, 0x5a, 0xa2, 0x44, 0xf8, 0x81, 0x03, ++ 0x49, 0xfe, 0xf3, 0x44, 0x7e, 0xaf, 0xd0, 0x30, 0x7c, 0xd3, 0x24, 0x80, ++ 0xff, 0xde, 0xa3, 0x7c, 0x9f, 0xa2, 0x22, 0x27, 0x33, 0xe2, 0xf9, 0x19, ++ 0x05, 0x52, 0x49, 0x78, 0xfd, 0xa8, 0x67, 0x52, 0x54, 0x44, 0x7f, 0x76, ++ 0x89, 0xa3, 0x24, 0xbc, 0x0e, 0x75, 0x6e, 0x45, 0x6a, 0x44, 0xff, 0x96, ++ 0xb9, 0x99, 0x11, 0xfd, 0x92, 0xa3, 0x05, 0x64, 0xbf, 0x41, 0x0f, 0x54, ++ 0x94, 0x80, 0x1e, 0x38, 0x0a, 0xed, 0x52, 0x60, 0xc1, 0x02, 0x51, 0x07, ++ 0xa5, 0xe5, 0x9f, 0x0a, 0x05, 0x4b, 0x15, 0xb6, 0x8b, 0xbc, 0xac, 0xc2, ++ 0xe3, 0xeb, 0x61, 0xf0, 0x87, 0x7a, 0xb0, 0xc4, 0x16, 0x69, 0xa7, 0x77, ++ 0x47, 0x73, 0x3b, 0x5f, 0xce, 0xd6, 0xd0, 0x06, 0x49, 0xf9, 0x11, 0xbe, ++ 0xbf, 0x5d, 0x96, 0x68, 0xfc, 0x24, 0xdc, 0x4e, 0x94, 0xcb, 0x15, 0x36, ++ 0x5e, 0x97, 0x15, 0x89, 0x87, 0xbc, 0xa3, 0x46, 0xb2, 0x97, 0x79, 0x31, ++ 0x92, 0x1f, 0xe3, 0xfa, 0x92, 0xa3, 0x4b, 0xeb, 0xd0, 0xf4, 0x96, 0x67, ++ 0x44, 0xbe, 0xaf, 0xf9, 0x61, 0xe5, 0x02, 0x3e, 0x6d, 0x5e, 0xe6, 0x73, ++ 0xb7, 0xa3, 0x3f, 0xa2, 0xc1, 0xad, 0xcd, 0xaf, 0xc1, 0x5f, 0x2e, 0x2f, ++ 0x2a, 0xa1, 0x7c, 0xf7, 0x35, 0xd6, 0xa1, 0x87, 0x97, 0xc1, 0x7a, 0x50, ++ 0x3f, 0xe8, 0xe1, 0x68, 0x4a, 0x16, 0xfe, 0x1a, 0xf8, 0x1f, 0xe4, 0xaf, ++ 0x89, 0x73, 0x24, 0xf0, 0x4b, 0xec, 0xcd, 0x7e, 0x6b, 0xfe, 0x7a, 0x05, ++ 0xe8, 0x2b, 0x47, 0xb8, 0xbe, 0xb2, 0x49, 0x89, 0x58, 0xb7, 0xd7, 0x97, ++ 0xbe, 0xd2, 0xc6, 0xed, 0xcb, 0x2f, 0xd3, 0xc6, 0x9d, 0xe9, 0xf0, 0xd0, ++ 0xfb, 0xee, 0x1d, 0x9f, 0x9e, 0x9a, 0x20, 0x87, 0xf5, 0x33, 0x3f, 0x4e, ++ 0x88, 0x0f, 0xef, 0xbf, 0xf8, 0xe9, 0xa6, 0x88, 0xfb, 0x49, 0x1f, 0xcf, ++ 0x71, 0x84, 0xf7, 0xb7, 0x7e, 0x3a, 0x07, 0xef, 0x4f, 0x51, 0xd4, 0x5a, ++ 0x1b, 0xf0, 0xe5, 0x31, 0x26, 0xb9, 0x7c, 0xc8, 0x07, 0x6d, 0xaa, 0x12, ++ 0x03, 0xf4, 0x28, 0x3e, 0xed, 0xae, 0xc3, 0xb6, 0xf4, 0x43, 0x2f, 0x96, ++ 0xab, 0xb2, 0xa9, 0xe7, 0x7c, 0x75, 0xd8, 0x4e, 0xbc, 0xe8, 0x6f, 0x33, ++ 0xc3, 0xba, 0x6e, 0x1a, 0x26, 0xab, 0x18, 0xbf, 0x6b, 0x7e, 0x88, 0x1e, ++ 0xde, 0xbf, 0x26, 0xf3, 0xbc, 0xc3, 0xb1, 0xab, 0xaa, 0x15, 0xf7, 0x59, ++ 0x77, 0xfb, 0x54, 0x2b, 0xfa, 0xf3, 0xbb, 0x1f, 0x54, 0xad, 0xe8, 0x87, ++ 0xec, 0x76, 0xf3, 0x73, 0x19, 0xee, 0x2c, 0x03, 0x9d, 0x8f, 0x71, 0x67, ++ 0xf3, 0x7a, 0xc5, 0xbf, 0x24, 0xf3, 0xba, 0x83, 0x4e, 0xf1, 0xbe, 0xd6, ++ 0xfa, 0x8d, 0xde, 0x4e, 0x84, 0x1b, 0xeb, 0xcc, 0xd1, 0x37, 0xa8, 0xfa, ++ 0x26, 0x48, 0x75, 0xe5, 0xc7, 0xd0, 0xbf, 0xca, 0xe9, 0xe9, 0x5f, 0x1d, ++ 0x53, 0xfc, 0x36, 0x9c, 0xef, 0xd8, 0x83, 0x7e, 0x5b, 0xf8, 0x7e, 0xe2, ++ 0xf5, 0xfa, 0x57, 0x7f, 0x04, 0x1e, 0x43, 0x38, 0x0a, 0x99, 0xe4, 0x09, ++ 0xd7, 0x23, 0xc5, 0x96, 0x28, 0x4f, 0xb8, 0xdc, 0x96, 0xda, 0x1d, 0x11, ++ 0xfd, 0x93, 0xc2, 0x0f, 0x99, 0xea, 0x4c, 0x8d, 0x78, 0xef, 0x26, 0x35, ++ 0x33, 0xe2, 0x39, 0xf0, 0x1b, 0x87, 0xa1, 0x5f, 0x52, 0x6b, 0x62, 0x54, ++ 0x6f, 0xeb, 0x33, 0xf0, 0x7a, 0x5b, 0x3d, 0x1e, 0x57, 0xa4, 0xf0, 0xf8, ++ 0xce, 0x65, 0xb3, 0xa3, 0x3b, 0x83, 0xfb, 0x66, 0x72, 0x6f, 0xe7, 0x91, ++ 0x5c, 0xc5, 0x86, 0x5e, 0xcf, 0xb7, 0xa5, 0xa4, 0x70, 0x7f, 0xf0, 0x3f, ++ 0x52, 0x18, 0xc1, 0x35, 0x2b, 0x85, 0xc3, 0xa7, 0xaf, 0xaf, 0xd5, 0xf7, ++ 0x6b, 0xf1, 0x7c, 0x0f, 0xe2, 0x93, 0xb9, 0x9c, 0xc8, 0xe7, 0x2e, 0xab, ++ 0xe1, 0x0a, 0xb8, 0xbc, 0xac, 0xe0, 0xe9, 0x27, 0xa6, 0x53, 0x5d, 0x6d, ++ 0xbe, 0xe1, 0xde, 0x2c, 0xe8, 0x57, 0x3c, 0xbd, 0x75, 0x3a, 0xaf, 0xab, ++ 0x35, 0xec, 0xc1, 0x3a, 0xdb, 0x19, 0x4f, 0x3f, 0xcf, 0xef, 0xdf, 0x60, ++ 0xc8, 0x37, 0x82, 0x3f, 0xb0, 0xcd, 0xf7, 0xc2, 0x74, 0xac, 0x2b, 0xaf, ++ 0x8a, 0xe2, 0xf5, 0x09, 0x55, 0x51, 0xa2, 0x3e, 0xb4, 0x6e, 0x74, 0x44, ++ 0xdc, 0xa3, 0x18, 0x3e, 0x7e, 0x6a, 0x21, 0xc6, 0x9f, 0xfb, 0x8d, 0x0c, ++ 0xf3, 0xfc, 0x8f, 0x99, 0xc0, 0x0e, 0xe6, 0x85, 0xf6, 0xd9, 0xad, 0x66, ++ 0x1e, 0xaf, 0x5a, 0x4d, 0xbc, 0x0e, 0x7c, 0x7d, 0xe6, 0xa9, 0xf5, 0xa8, ++ 0x3f, 0x3e, 0x8b, 0xf2, 0xe6, 0xa5, 0x50, 0x9e, 0xb1, 0x48, 0x45, 0x3c, ++ 0x5e, 0xb4, 0x5b, 0xa8, 0x3e, 0xf4, 0xbe, 0x7d, 0xa5, 0x29, 0xc8, 0x07, ++ 0xb3, 0x52, 0x78, 0xde, 0x2b, 0x7b, 0xcf, 0x44, 0x27, 0x9d, 0x2f, 0xfb, ++ 0xe7, 0xc1, 0x51, 0xfc, 0x7d, 0x70, 0x60, 0xfd, 0x30, 0x8e, 0x73, 0x71, ++ 0x77, 0x36, 0xf9, 0xe5, 0xd9, 0x03, 0x18, 0x9d, 0x27, 0xd1, 0xe8, 0x01, ++ 0xe1, 0x33, 0x5d, 0x8f, 0x82, 0xf0, 0x81, 0xce, 0x63, 0x30, 0xb7, 0x13, ++ 0xf3, 0x6f, 0xb5, 0x0e, 0x13, 0x8d, 0x33, 0x2b, 0x85, 0xf3, 0xe3, 0xf5, ++ 0xb6, 0x3d, 0xea, 0x89, 0xe3, 0x0c, 0x6b, 0x76, 0x41, 0xbb, 0x20, 0x85, ++ 0xc7, 0xcd, 0xb7, 0xe2, 0xbc, 0x04, 0x6f, 0xb0, 0xff, 0x2c, 0xdc, 0xd0, ++ 0xb3, 0x07, 0xfb, 0xcf, 0x1e, 0xc9, 0xfb, 0x48, 0x6f, 0x59, 0xce, 0x0b, ++ 0xa2, 0x7f, 0x1b, 0xfc, 0x51, 0x0c, 0xed, 0xc3, 0xbc, 0x1f, 0xcd, 0xf1, ++ 0xc6, 0x32, 0x82, 0xb4, 0x6f, 0xf3, 0xee, 0xa2, 0x6c, 0xd7, 0x06, 0xba, ++ 0xce, 0xf1, 0xb8, 0xc0, 0x3f, 0xb0, 0xb6, 0x43, 0xc5, 0xfa, 0x0f, 0x7f, ++ 0x3f, 0xac, 0xb7, 0x18, 0xe8, 0xf4, 0x2e, 0x45, 0x7c, 0xdc, 0x66, 0xf6, ++ 0x0f, 0x26, 0xbe, 0xb2, 0xad, 0x89, 0xc1, 0x79, 0xae, 0xb7, 0xde, 0xb8, ++ 0xef, 0xf9, 0x21, 0xe0, 0x04, 0x7b, 0x32, 0x7f, 0x3c, 0xa7, 0x97, 0x36, ++ 0x3f, 0xe0, 0xd8, 0x82, 0x74, 0x7c, 0x57, 0x9c, 0x3b, 0xd1, 0xe0, 0x01, ++ 0x38, 0x7e, 0x8c, 0x70, 0x68, 0x70, 0x75, 0xc3, 0xa3, 0xab, 0x3f, 0xef, ++ 0x14, 0x7e, 0x7b, 0x27, 0x8e, 0x97, 0x1b, 0xca, 0x53, 0x57, 0xff, 0xc9, ++ 0x40, 0x79, 0x8a, 0x6a, 0x09, 0xf4, 0x24, 0xf4, 0xf7, 0x7c, 0xc8, 0x5c, ++ 0x3e, 0x95, 0xe8, 0x43, 0x79, 0x50, 0xdc, 0xd2, 0xc2, 0xf9, 0xc6, 0x9f, ++ 0x58, 0x52, 0x6c, 0x83, 0xb6, 0xa0, 0x71, 0x15, 0x8f, 0x8f, 0xdb, 0x95, ++ 0x88, 0xbc, 0x98, 0x66, 0xcf, 0x26, 0x8a, 0xe7, 0xc7, 0xbe, 0xa7, 0x44, ++ 0xd8, 0xa3, 0x89, 0x22, 0xfe, 0x1d, 0xaf, 0xcb, 0x4f, 0x4e, 0x6c, 0x9c, ++ 0x4e, 0xe7, 0xf8, 0x26, 0xea, 0xe2, 0xe2, 0x5f, 0xa4, 0x88, 0xbc, 0x65, ++ 0x1a, 0x4b, 0x0b, 0xcf, 0x23, 0xac, 0x15, 0xf1, 0xc6, 0xe5, 0xb6, 0x81, ++ 0x71, 0xe8, 0x9f, 0x2a, 0x10, 0xe7, 0xca, 0x80, 0x6f, 0x93, 0x2a, 0xb3, ++ 0x71, 0xf1, 0x21, 0xbd, 0xd0, 0xb0, 0x8e, 0x45, 0x9c, 0x53, 0xd4, 0xf8, ++ 0x70, 0xe4, 0x69, 0xfb, 0x9d, 0x38, 0xdf, 0xc8, 0xd3, 0xec, 0x0e, 0xf2, ++ 0x07, 0xb4, 0x71, 0xbb, 0xf3, 0x13, 0x1c, 0x2f, 0x97, 0xdf, 0xe3, 0x78, ++ 0x19, 0xd5, 0x31, 0xec, 0xe9, 0x49, 0xd0, 0x37, 0x1e, 0x31, 0x32, 0xbf, ++ 0x1a, 0x5a, 0xe7, 0x04, 0x0e, 0x2a, 0x83, 0x30, 0x87, 0xe2, 0xa4, 0xcb, ++ 0x17, 0x6c, 0x64, 0x5f, 0xc6, 0x1c, 0x9d, 0x43, 0xf5, 0xde, 0x66, 0xa7, ++ 0x81, 0xa9, 0x61, 0xeb, 0x8f, 0x52, 0xa3, 0x99, 0x1a, 0xa6, 0x2f, 0xad, ++ 0xc3, 0xe2, 0x23, 0xfa, 0xb2, 0xa0, 0x4f, 0x5d, 0x54, 0xa4, 0x1f, 0x90, ++ 0x2f, 0xe6, 0x89, 0x71, 0xa5, 0x45, 0x8c, 0xb7, 0x3f, 0xbe, 0xec, 0x08, ++ 0xfa, 0x05, 0xf9, 0xb6, 0xe5, 0xe4, 0x17, 0xc4, 0x8d, 0x1b, 0x18, 0x31, ++ 0x1e, 0x6b, 0x53, 0x22, 0xfc, 0x83, 0x3c, 0xe6, 0x71, 0x63, 0xdc, 0xe8, ++ 0x02, 0xfa, 0xe2, 0x7e, 0xd9, 0x98, 0xd3, 0x4a, 0x84, 0x1f, 0x30, 0x2e, ++ 0xb0, 0x91, 0xce, 0xa1, 0x8e, 0xfb, 0x30, 0xf2, 0xfa, 0x84, 0x73, 0x91, ++ 0xfd, 0x03, 0x7d, 0xd1, 0xa5, 0x2f, 0xfc, 0xb1, 0xdc, 0xa7, 0xd1, 0x2f, ++ 0xfc, 0xa1, 0xf8, 0x73, 0xb8, 0x23, 0xf1, 0x97, 0x50, 0x1e, 0x89, 0xbf, ++ 0x24, 0x4f, 0x24, 0xfe, 0x52, 0x16, 0x44, 0xe2, 0x27, 0xd5, 0x1b, 0x89, ++ 0x8f, 0xf4, 0xe5, 0x23, 0x22, 0xee, 0xf7, 0x5b, 0x93, 0x17, 0xd1, 0x1f, ++ 0xf0, 0xc0, 0x84, 0x88, 0xe7, 0x33, 0xc1, 0x80, 0x85, 0xf7, 0xb3, 0x1e, ++ 0x9d, 0x16, 0xf1, 0xfc, 0xe0, 0x8d, 0xb3, 0x23, 0xfa, 0x43, 0x37, 0xdf, ++ 0x16, 0xf1, 0xfc, 0x70, 0xff, 0x92, 0x88, 0xfb, 0xd9, 0xdb, 0x56, 0xfe, ++ 0x20, 0x7a, 0x8f, 0xac, 0x5f, 0x1b, 0xf1, 0xbc, 0x9e, 0xde, 0x37, 0x34, ++ 0xfe, 0x34, 0x62, 0x7c, 0x8d, 0xde, 0x3e, 0xf8, 0xfb, 0xdf, 0xa4, 0x37, ++ 0x73, 0x0a, 0xff, 0x50, 0xd0, 0x3b, 0x51, 0xd8, 0x59, 0x87, 0x9b, 0xd7, ++ 0xad, 0x75, 0x19, 0x6d, 0x8f, 0xe2, 0x79, 0x7c, 0x3c, 0x36, 0x82, 0xfa, ++ 0xce, 0x81, 0xe7, 0xe9, 0x63, 0xd1, 0xfe, 0xab, 0x54, 0x97, 0xe7, 0x9b, ++ 0xc6, 0x68, 0x5f, 0xfb, 0x97, 0xb2, 0x47, 0x42, 0xbd, 0x94, 0x0e, 0xa8, ++ 0x35, 0x64, 0x51, 0xbd, 0x3c, 0xd5, 0xf5, 0xfd, 0xdc, 0x60, 0x88, 0xd8, ++ 0x67, 0xb7, 0x3b, 0xb9, 0x3f, 0x64, 0x77, 0x72, 0x3d, 0xfe, 0x6b, 0x13, ++ 0x3f, 0x2f, 0x95, 0x0e, 0xfe, 0x26, 0xd9, 0x29, 0x03, 0x0b, 0xc5, 0xd9, ++ 0x16, 0xac, 0x77, 0x64, 0x82, 0x99, 0xac, 0x8f, 0x63, 0x9c, 0x5d, 0xe7, ++ 0xe8, 0x18, 0xa6, 0x3a, 0x30, 0x6f, 0x07, 0xfd, 0xc9, 0x21, 0xbd, 0xaa, ++ 0xe9, 0xd1, 0xdb, 0xcc, 0x6a, 0x6d, 0x07, 0xe8, 0x97, 0x51, 0x32, 0xd7, ++ 0x93, 0xa0, 0x3f, 0xfb, 0x39, 0x61, 0x9e, 0xf7, 0xa5, 0x07, 0x8d, 0xdc, ++ 0xff, 0xf0, 0x19, 0xd1, 0xff, 0x48, 0xb7, 0x30, 0x5f, 0x6c, 0x1e, 0xd9, ++ 0x19, 0xca, 0x43, 0x3b, 0x58, 0xa2, 0x84, 0xe7, 0x00, 0xe2, 0x42, 0x7a, ++ 0x5c, 0xfd, 0x0e, 0x88, 0x75, 0x70, 0x65, 0x36, 0x9d, 0xc3, 0x7a, 0x13, ++ 0x41, 0x40, 0xbf, 0x59, 0x75, 0xd1, 0x7e, 0xd3, 0xad, 0x9a, 0x9e, 0x5a, ++ 0x3e, 0x9c, 0xf4, 0xd4, 0x65, 0x5b, 0xa4, 0xff, 0x76, 0x79, 0x69, 0x16, ++ 0x5d, 0x3f, 0x7b, 0xbb, 0x99, 0xea, 0x07, 0xce, 0x8a, 0x3a, 0x47, 0x0d, ++ 0x0f, 0xfa, 0xf3, 0xd6, 0xda, 0x39, 0x6c, 0xed, 0xfe, 0xf2, 0x2d, 0x9b, ++ 0x62, 0xd0, 0xef, 0x3c, 0x2b, 0xce, 0xff, 0x6a, 0xd7, 0x27, 0x0b, 0xfc, ++ 0x4d, 0x76, 0xca, 0xc2, 0xfe, 0x59, 0xd6, 0x60, 0x3e, 0x6c, 0x11, 0x18, ++ 0xf1, 0x38, 0xc0, 0x7b, 0xe5, 0x91, 0x8e, 0xd8, 0xdb, 0x18, 0xf9, 0x9b, ++ 0x93, 0x70, 0xdd, 0x55, 0x5b, 0xae, 0xdc, 0xfe, 0x2a, 0xf4, 0xab, 0x0d, ++ 0xc1, 0x64, 0x6e, 0x37, 0x7c, 0xf4, 0xde, 0xfc, 0x77, 0xf9, 0xb9, 0xee, ++ 0xf9, 0x7f, 0x8b, 0xfc, 0xae, 0x40, 0x85, 0x93, 0xc7, 0xf9, 0x15, 0x62, ++ 0xfc, 0x5b, 0xa0, 0xb1, 0x03, 0x9e, 0x6e, 0x01, 0x3a, 0x38, 0xb0, 0x7d, ++ 0x63, 0x52, 0x19, 0xf2, 0x27, 0x5c, 0xa7, 0xf3, 0x71, 0x33, 0x8f, 0x30, ++ 0x23, 0xca, 0xf3, 0x2c, 0x6f, 0x26, 0xd5, 0x4d, 0x9c, 0x62, 0xae, 0x33, ++ 0x7b, 0x01, 0xc4, 0xf9, 0x4e, 0x95, 0xe0, 0x9c, 0xcb, 0x3c, 0x46, 0xcc, ++ 0x5b, 0xbd, 0x73, 0x7b, 0x65, 0x0c, 0x3e, 0xd7, 0x3d, 0x9e, 0x36, 0x0e, ++ 0x30, 0x0c, 0xfa, 0x25, 0xef, 0x3a, 0x7c, 0xc6, 0x64, 0xcc, 0x1b, 0x4c, ++ 0xe6, 0x75, 0x13, 0x30, 0x9f, 0x05, 0xaf, 0x7b, 0x16, 0xa5, 0x3f, 0x8c, ++ 0x76, 0x49, 0x9b, 0xef, 0x1d, 0xe6, 0xbd, 0x74, 0x06, 0xe8, 0x3b, 0x9b, ++ 0xb9, 0x68, 0x5c, 0x6d, 0x7c, 0x86, 0xe9, 0xf9, 0x30, 0x3d, 0xb5, 0x7b, ++ 0xf9, 0xaa, 0x8f, 0x12, 0x60, 0xbe, 0xb5, 0x47, 0x0d, 0x94, 0x8f, 0x58, ++ 0xdb, 0x6c, 0xa6, 0x78, 0xad, 0x6b, 0xe5, 0x7f, 0xed, 0x78, 0x0a, 0xee, ++ 0xdf, 0x91, 0xde, 0xd1, 0x0f, 0xed, 0xf6, 0xfb, 0x2b, 0xff, 0x36, 0x04, ++ 0xf9, 0xe1, 0xd6, 0xcd, 0x32, 0x53, 0x81, 0xde, 0xaa, 0xdd, 0x7b, 0xa7, ++ 0x33, 0x6c, 0x5f, 0xe5, 0xec, 0xd2, 0x2b, 0x31, 0x78, 0x1f, 0xec, 0xee, ++ 0xd6, 0xa7, 0xd0, 0x58, 0xbe, 0x6c, 0xa6, 0x3a, 0xe2, 0xf7, 0x57, 0xbe, ++ 0x3c, 0x24, 0xdc, 0x8f, 0xad, 0x74, 0x16, 0x2e, 0xc7, 0xf7, 0xd8, 0xb8, ++ 0xeb, 0x3b, 0xef, 0x58, 0xfc, 0xd2, 0xf0, 0x14, 0xaa, 0xf7, 0x12, 0xfc, ++ 0xb4, 0x42, 0xf0, 0xd3, 0xda, 0x17, 0x87, 0x92, 0xbf, 0xb5, 0x36, 0xa6, ++ 0x9b, 0x9f, 0x78, 0x7f, 0x2b, 0xaf, 0x1b, 0xd1, 0xd6, 0x71, 0x46, 0xf0, ++ 0xe3, 0xca, 0x97, 0xbe, 0x89, 0xf8, 0xce, 0xc4, 0x6e, 0xe0, 0x23, 0xd5, ++ 0xcc, 0xf7, 0xc5, 0xd4, 0xa1, 0x60, 0xef, 0xdb, 0x2e, 0xe7, 0xd2, 0x77, ++ 0x1f, 0x8c, 0xde, 0x7f, 0x75, 0xc2, 0xbc, 0x2d, 0x57, 0x3f, 0x89, 0xc5, ++ 0xfe, 0x9e, 0x37, 0xff, 0x4a, 0xf0, 0xb3, 0xb9, 0xd7, 0x07, 0x2f, 0xca, ++ 0xa2, 0x6f, 0x4c, 0x68, 0x7f, 0x5a, 0x3b, 0xef, 0xb9, 0xa0, 0x29, 0x21, ++ 0x1f, 0xe9, 0x0e, 0x72, 0xb6, 0x01, 0xc7, 0xbf, 0xed, 0x77, 0x2f, 0x5e, ++ 0xfa, 0x00, 0xf1, 0xd3, 0xfc, 0xf2, 0xd6, 0x9f, 0xe1, 0x33, 0xd7, 0x79, ++ 0xfe, 0x73, 0x97, 0x96, 0x77, 0x14, 0xf6, 0xc6, 0x25, 0xf0, 0x01, 0xf6, ++ 0x86, 0xe2, 0x8b, 0x2e, 0x16, 0xcd, 0xcf, 0x93, 0x08, 0xff, 0x46, 0xc1, ++ 0x1d, 0xf9, 0x2c, 0xfa, 0x9e, 0x87, 0x4a, 0x7c, 0xed, 0x66, 0xc7, 0x71, ++ 0x1f, 0xa7, 0xb6, 0xd5, 0x40, 0x75, 0x26, 0xb1, 0xb8, 0x09, 0x14, 0x96, ++ 0xaf, 0x8b, 0x95, 0x0d, 0x9a, 0x51, 0x72, 0x5b, 0x9c, 0xa0, 0xaf, 0x85, ++ 0x9e, 0xf9, 0x7f, 0xce, 0xdb, 0x2a, 0xea, 0xa8, 0x3e, 0x20, 0xd2, 0x1f, ++ 0x2a, 0x38, 0xb4, 0x32, 0xc2, 0x0f, 0xf2, 0xc0, 0x5f, 0xaf, 0x7e, 0xd0, ++ 0x33, 0xde, 0x5a, 0xcc, 0x2f, 0xe9, 0xfd, 0xa1, 0xf1, 0x01, 0xc3, 0x62, ++ 0x53, 0xdc, 0xf7, 0xf8, 0x45, 0x87, 0xa6, 0xf5, 0xea, 0x17, 0x41, 0x40, ++ 0xed, 0x96, 0xc6, 0x88, 0xad, 0x21, 0xf8, 0x35, 0xe8, 0xf4, 0xf3, 0x7e, ++ 0x21, 0x57, 0xf5, 0x38, 0x16, 0xe6, 0xff, 0x03, 0xd1, 0xfc, 0xfc, 0x33, ++ 0x98, 0x0e, 0xf4, 0x7b, 0x7f, 0x9a, 0xca, 0xf5, 0xb7, 0x2d, 0x83, 0xf1, ++ 0xf3, 0x69, 0x52, 0xe7, 0x30, 0x0b, 0xe8, 0xcb, 0x16, 0xe7, 0xa2, 0xc7, ++ 0x1f, 0x85, 0x6b, 0x96, 0x41, 0x7c, 0xdd, 0xd8, 0xaf, 0xa5, 0x33, 0x35, ++ 0xf9, 0xc4, 0x7f, 0xdd, 0x7e, 0xd7, 0xa1, 0x11, 0xa4, 0xb7, 0xd8, 0xb7, ++ 0x30, 0x1b, 0xe2, 0x43, 0xe4, 0x3d, 0xf4, 0x74, 0x2b, 0xc0, 0xf3, 0xec, ++ 0xf9, 0x61, 0x72, 0x27, 0xde, 0x0f, 0x1c, 0xfe, 0x6b, 0x2c, 0xe6, 0x7d, ++ 0x77, 0xc4, 0xab, 0x6f, 0x21, 0x3d, 0x82, 0x47, 0x65, 0xda, 0xff, 0x89, ++ 0x52, 0x3a, 0x4c, 0x8e, 0x5e, 0xe2, 0xbb, 0x57, 0x51, 0x0f, 0x02, 0x9f, ++ 0xca, 0xa9, 0xdc, 0x1e, 0x58, 0x1a, 0x79, 0x7e, 0xd1, 0xa2, 0xba, 0x19, ++ 0xc6, 0x0f, 0x51, 0x76, 0xfb, 0xa8, 0xf0, 0x73, 0x7f, 0x8d, 0x4e, 0x1e, ++ 0x4f, 0x56, 0x1e, 0x7e, 0xbf, 0xbf, 0x09, 0xe8, 0x71, 0xc9, 0xd0, 0x16, ++ 0x9b, 0x03, 0xe3, 0xaf, 0xde, 0xbb, 0x3b, 0x16, 0xdd, 0xff, 0x0c, 0x93, ++ 0xf7, 0x03, 0xe4, 0xc3, 0x55, 0x67, 0xdf, 0x1e, 0x63, 0xa7, 0xfc, 0xcd, ++ 0x96, 0xfe, 0x18, 0x0f, 0xd6, 0x07, 0xf8, 0x77, 0x30, 0x46, 0x2a, 0xcc, ++ 0xa7, 0xe4, 0xf5, 0x84, 0xa3, 0x7a, 0x33, 0x2c, 0x26, 0x01, 0xcf, 0xe9, ++ 0x27, 0x50, 0x3b, 0xb2, 0x29, 0x7f, 0x19, 0xf2, 0x59, 0x75, 0x80, 0xaf, ++ 0x13, 0xc7, 0xc6, 0x42, 0xbe, 0xe1, 0x8d, 0x12, 0xf5, 0x3b, 0x1b, 0x6b, ++ 0xe3, 0x71, 0xbc, 0xea, 0xdf, 0x37, 0xa7, 0xa1, 0x3c, 0xbd, 0x9c, 0xc4, ++ 0xe3, 0xcd, 0x97, 0xae, 0x66, 0xf3, 0xf7, 0x15, 0xa6, 0xe0, 0xf3, 0x41, ++ 0xa7, 0x43, 0x10, 0xd3, 0x6f, 0xc0, 0xf8, 0xe4, 0x65, 0x11, 0xd7, 0x74, ++ 0x5e, 0x95, 0xe9, 0x39, 0x6d, 0xfe, 0x91, 0x8d, 0x85, 0xb2, 0x1d, 0xf8, ++ 0x21, 0x27, 0xb0, 0xf1, 0x00, 0xc5, 0x51, 0x4d, 0x66, 0x15, 0xe9, 0x1a, ++ 0xf5, 0x1c, 0xe3, 0x78, 0x68, 0x8a, 0x22, 0xb9, 0xaf, 0x6e, 0x99, 0xca, ++ 0xd0, 0xee, 0x77, 0x39, 0x98, 0x4b, 0x82, 0xfb, 0x3b, 0xa2, 0x83, 0x7f, ++ 0xa4, 0xf3, 0x6e, 0xcd, 0x66, 0x15, 0xf3, 0xad, 0x51, 0xf6, 0x8d, 0x2c, ++ 0x1e, 0xc6, 0xdf, 0x21, 0xf6, 0x59, 0x87, 0x03, 0x47, 0xe1, 0x79, 0x29, ++ 0xed, 0xba, 0x36, 0x5f, 0x54, 0xd3, 0xd3, 0x18, 0x73, 0x20, 0x3f, 0x50, ++ 0xde, 0x37, 0x4a, 0xd9, 0xc8, 0x26, 0xdb, 0xc2, 0xf1, 0x1c, 0x43, 0x78, ++ 0x76, 0xa4, 0x72, 0x3e, 0xda, 0x11, 0x1d, 0x30, 0x60, 0x9e, 0x25, 0x38, ++ 0x98, 0xb1, 0x67, 0x09, 0xae, 0x10, 0x9c, 0x8c, 0xe6, 0xd5, 0xe0, 0x1c, ++ 0xee, 0xc7, 0xf3, 0x84, 0x3b, 0x4c, 0xc1, 0xf3, 0x78, 0x6e, 0x06, 0xe0, ++ 0xb2, 0x23, 0xfd, 0x87, 0x33, 0x0e, 0x27, 0x6b, 0x1a, 0xaa, 0x62, 0x9e, ++ 0x20, 0xca, 0xee, 0xa6, 0x75, 0x44, 0xd9, 0x55, 0x97, 0x4f, 0xea, 0x09, ++ 0x57, 0x75, 0x2e, 0xf3, 0xa3, 0x5d, 0xff, 0xf9, 0x43, 0xac, 0x5b, 0x6e, ++ 0x51, 0x8e, 0xab, 0xa3, 0x43, 0x7d, 0x0b, 0xc8, 0xc0, 0x8e, 0x81, 0x4c, ++ 0xc8, 0xf9, 0xcf, 0x1f, 0x2f, 0xc9, 0x08, 0xef, 0x83, 0x62, 0x19, 0x17, ++ 0x7a, 0x7f, 0xc8, 0xaf, 0x36, 0x3e, 0x5e, 0x37, 0x89, 0xe2, 0x09, 0x9f, ++ 0x8c, 0xf1, 0x2f, 0xb4, 0x31, 0xf1, 0xb8, 0x4e, 0x95, 0xd6, 0xa7, 0x60, ++ 0x8a, 0x29, 0x8f, 0xe3, 0x01, 0xf7, 0xdb, 0xad, 0x16, 0x7e, 0xbf, 0xfb, ++ 0x79, 0xe0, 0x6f, 0x1b, 0xf6, 0x6d, 0xfc, 0x39, 0x57, 0x9c, 0xdd, 0x3a, ++ 0x4d, 0x22, 0x39, 0xe1, 0xf5, 0xb8, 0x42, 0x1f, 0xdc, 0x27, 0x05, 0xce, ++ 0xdf, 0x08, 0xa4, 0xfd, 0x2a, 0x70, 0x20, 0x57, 0x05, 0x58, 0x56, 0xbf, ++ 0xb1, 0x9f, 0xf8, 0x74, 0x95, 0xa1, 0xe9, 0xa9, 0x91, 0x70, 0xff, 0xee, ++ 0x28, 0xaf, 0x2b, 0x15, 0xe6, 0x7b, 0xed, 0x43, 0x03, 0x9d, 0x6b, 0xfd, ++ 0xf3, 0x8b, 0x51, 0xfe, 0x0a, 0xc0, 0xc7, 0xb0, 0x7d, 0x5b, 0x92, 0xdd, ++ 0xbd, 0xc8, 0x87, 0x7e, 0xfc, 0x47, 0xde, 0x7b, 0xe8, 0xc9, 0x74, 0xa4, ++ 0xff, 0x3e, 0x49, 0xc5, 0x3c, 0x6c, 0x97, 0x31, 0x48, 0xdf, 0x37, 0xa9, ++ 0x6a, 0xfa, 0xcc, 0x44, 0xf5, 0x0d, 0x8d, 0x1f, 0x53, 0xdd, 0xd3, 0x9b, ++ 0xa9, 0xde, 0x49, 0x38, 0xcf, 0xb8, 0xc6, 0x1a, 0xda, 0x8f, 0x1e, 0xcf, ++ 0x36, 0xd2, 0x7e, 0x74, 0xb6, 0x38, 0x0f, 0x5e, 0xef, 0xe4, 0xfa, 0xe3, ++ 0xf2, 0xe9, 0x21, 0xcf, 0xd6, 0x84, 0xe1, 0x7f, 0x49, 0x2a, 0x97, 0x2f, ++ 0x16, 0xf4, 0x0e, 0x40, 0xb9, 0x69, 0x12, 0xf2, 0xd9, 0x82, 0x7e, 0x0a, ++ 0xb4, 0x7b, 0x85, 0xbf, 0xb4, 0xb7, 0xf5, 0xd6, 0x2c, 0x35, 0x2c, 0x7f, ++ 0x58, 0xc3, 0x0e, 0xa4, 0x23, 0xbe, 0x1f, 0x62, 0x87, 0xa8, 0xd5, 0xae, ++ 0x77, 0xf9, 0xf9, 0xb9, 0xca, 0xec, 0x77, 0x2c, 0x77, 0xb8, 0xc3, 0xf8, ++ 0x6f, 0x91, 0x90, 0xf7, 0x45, 0xa9, 0x22, 0x4f, 0x96, 0xea, 0x9d, 0x8d, ++ 0xf0, 0xae, 0x6a, 0xfd, 0xc4, 0x14, 0xab, 0xe2, 0x39, 0x99, 0xfa, 0xfe, ++ 0x68, 0x57, 0xea, 0xc1, 0x9f, 0xb2, 0xf7, 0x82, 0x97, 0x6e, 0xb9, 0xd5, ++ 0xc9, 0x51, 0xb5, 0x12, 0x34, 0xe1, 0xf3, 0xd5, 0x17, 0xf8, 0xf9, 0x57, ++ 0xa0, 0x73, 0x1d, 0x9e, 0x37, 0x78, 0xf9, 0x9d, 0xc6, 0x11, 0x8b, 0xe1, ++ 0xfa, 0x5e, 0xc0, 0x35, 0xd6, 0x95, 0xfa, 0xce, 0x9a, 0xa9, 0xbe, 0x72, ++ 0xaf, 0xd1, 0x93, 0x8e, 0xcf, 0xd7, 0x9c, 0xf9, 0x3a, 0x17, 0xf5, 0x56, ++ 0x09, 0x02, 0x01, 0xf0, 0x7c, 0xdd, 0xbc, 0x6a, 0x00, 0xe2, 0x0d, 0xf8, ++ 0xbe, 0x28, 0x1a, 0xe5, 0x6b, 0x17, 0x23, 0x3d, 0xa6, 0xc9, 0x67, 0x0e, ++ 0xca, 0x27, 0xbc, 0x9f, 0x83, 0x7c, 0x5f, 0x80, 0xfd, 0xe1, 0xa4, 0x87, ++ 0x77, 0x98, 0xda, 0xf9, 0xf9, 0xd3, 0xbd, 0xfc, 0xfc, 0x29, 0xf0, 0x3d, ++ 0xc9, 0x01, 0xf0, 0xbd, 0x1d, 0xfd, 0x86, 0x1c, 0x3b, 0xc8, 0x01, 0xbd, ++ 0x3f, 0x94, 0xe4, 0x7b, 0x47, 0xbb, 0x81, 0xce, 0xc9, 0xfa, 0x40, 0x8f, ++ 0x0f, 0xa6, 0x7e, 0xd1, 0x1c, 0xec, 0xef, 0x68, 0x2f, 0xb1, 0x93, 0x7c, ++ 0x63, 0x5e, 0x3f, 0x0f, 0xe5, 0x34, 0x70, 0x80, 0xc6, 0xa9, 0x87, 0xd8, ++ 0x04, 0x49, 0x27, 0x31, 0x4f, 0xb8, 0x3f, 0xd9, 0xe8, 0x8c, 0x25, 0xba, ++ 0x69, 0xfa, 0xf1, 0xb0, 0x93, 0x09, 0x3b, 0xa1, 0xc6, 0xe1, 0x79, 0x03, ++ 0xab, 0x2c, 0x47, 0xc8, 0x45, 0x98, 0x3d, 0xe4, 0x7d, 0x61, 0x2f, 0x4f, ++ 0xfc, 0x2a, 0xf0, 0xf8, 0x2f, 0xd1, 0x76, 0xb8, 0x85, 0x5d, 0x10, 0xfe, ++ 0x14, 0xf3, 0xe6, 0x93, 0x9e, 0xbf, 0x57, 0xd8, 0xaa, 0xb5, 0xaf, 0x4f, ++ 0x98, 0xb9, 0x1d, 0xd6, 0xb9, 0xf6, 0x84, 0xdc, 0x5d, 0x3f, 0x8e, 0xfe, ++ 0x6b, 0x40, 0xf0, 0xc9, 0x01, 0xe1, 0xcf, 0xa2, 0x9d, 0x50, 0x13, 0x78, ++ 0x3d, 0x0e, 0x5e, 0x1f, 0xbd, 0x99, 0xd7, 0xd5, 0x8e, 0x71, 0xaf, 0x29, ++ 0xc6, 0xb3, 0xcf, 0xe3, 0xca, 0x37, 0x1e, 0xc4, 0x76, 0x82, 0xa7, 0xbe, ++ 0x18, 0xcf, 0x3e, 0x4f, 0x5a, 0xd0, 0x7e, 0x90, 0x9f, 0x81, 0xe6, 0xe7, ++ 0xd9, 0x1b, 0x0e, 0xdc, 0x94, 0x8d, 0xfb, 0xde, 0x5d, 0x67, 0xcd, 0x0c, ++ 0xf7, 0x5d, 0x1a, 0xfe, 0x1a, 0xfc, 0xe3, 0x4b, 0x80, 0x87, 0xfb, 0x5b, ++ 0x00, 0xff, 0xbd, 0xd8, 0x25, 0x58, 0x0e, 0xf1, 0x1f, 0x58, 0xec, 0x74, ++ 0xe6, 0xec, 0x79, 0xbf, 0x4b, 0xd2, 0xf4, 0xc7, 0xa9, 0x0a, 0xe4, 0xc7, ++ 0xce, 0x06, 0x39, 0xd4, 0x07, 0x40, 0xaa, 0x80, 0xc1, 0xb1, 0xff, 0xdb, ++ 0xd4, 0x93, 0x8f, 0xfb, 0xa0, 0x9f, 0x95, 0xe6, 0x7e, 0x3e, 0x15, 0xfd, ++ 0xed, 0x74, 0x2f, 0xb5, 0x5d, 0x27, 0xff, 0x9a, 0x8c, 0xb6, 0x60, 0xef, ++ 0x69, 0xee, 0x47, 0x35, 0x98, 0xdc, 0xd9, 0xc8, 0x3f, 0x0d, 0x03, 0x23, ++ 0xbf, 0x1f, 0xa0, 0xb5, 0x4f, 0xa6, 0x1a, 0x89, 0x0e, 0x05, 0x7d, 0x7c, ++ 0xbf, 0xeb, 0x48, 0x2a, 0xcf, 0x6f, 0x0e, 0xf1, 0xb1, 0xc7, 0x90, 0x8f, ++ 0xaa, 0x1a, 0x64, 0xbb, 0x1f, 0xe8, 0x7e, 0xa9, 0x41, 0x76, 0x9b, 0xc0, ++ 0x1f, 0x3a, 0xef, 0xf6, 0x26, 0xe3, 0xd9, 0x9c, 0x0b, 0xcc, 0x77, 0xcb, ++ 0x44, 0xb4, 0xf3, 0x22, 0x8e, 0xd4, 0xbe, 0xf7, 0x72, 0x17, 0xfa, 0x29, ++ 0x60, 0xa7, 0xee, 0xfe, 0x65, 0xef, 0xfb, 0x0f, 0xab, 0x99, 0xf6, 0x5b, ++ 0x63, 0x40, 0xbe, 0x5a, 0xd6, 0x24, 0xb1, 0xff, 0x00, 0x1c, 0x2c, 0x7f, ++ 0x26, 0xf2, 0xf9, 0xd5, 0xda, 0xf7, 0x6a, 0x1a, 0xb7, 0x1c, 0xc6, 0xef, ++ 0x88, 0xad, 0x7c, 0x4e, 0x77, 0x1f, 0xfd, 0x15, 0xfa, 0x0e, 0x46, 0xa4, ++ 0x1f, 0x73, 0x24, 0x55, 0xf8, 0x27, 0x59, 0x2c, 0x0b, 0xfd, 0x13, 0xe0, ++ 0x23, 0xd2, 0x0f, 0x46, 0x85, 0x1d, 0x31, 0x03, 0xdf, 0xae, 0x48, 0xf7, ++ 0xee, 0x43, 0x7b, 0xfc, 0xb2, 0xf8, 0xbe, 0x02, 0xe8, 0x51, 0x92, 0xc7, ++ 0x7d, 0x4e, 0x61, 0x57, 0x44, 0xfd, 0x41, 0x70, 0x07, 0xaf, 0x2b, 0x1e, ++ 0xbe, 0xcd, 0x2f, 0x1b, 0xe0, 0xfd, 0x09, 0x8a, 0x5f, 0x46, 0x7b, 0xc5, ++ 0xa0, 0xc5, 0x7d, 0x87, 0x71, 0x6e, 0x6f, 0x19, 0x7d, 0x87, 0xc9, 0xe7, ++ 0x3e, 0x8d, 0xfb, 0x3e, 0xcb, 0x85, 0x3e, 0x5c, 0xae, 0xf9, 0x69, 0x7e, ++ 0xbe, 0x3f, 0x02, 0x66, 0x37, 0xc2, 0x4f, 0xab, 0x16, 0xab, 0x1f, 0xcf, ++ 0xfc, 0xb5, 0xb1, 0xb8, 0xfe, 0x6d, 0x12, 0xc5, 0xcb, 0xab, 0xb6, 0x45, ++ 0xee, 0xa7, 0x54, 0x8b, 0xf5, 0xaf, 0xde, 0x7c, 0xf2, 0x30, 0x9a, 0xbc, ++ 0xca, 0x7a, 0xdd, 0x7d, 0xb1, 0xfe, 0x6a, 0xdd, 0xfa, 0xb5, 0x7d, 0xf3, ++ 0xcf, 0x53, 0x23, 0xeb, 0xbf, 0xae, 0x77, 0x3f, 0xe4, 0x2f, 0x46, 0xee, ++ 0x37, 0xbc, 0x2d, 0xc6, 0xd1, 0xee, 0x9b, 0xd2, 0xb8, 0x7e, 0xac, 0x82, ++ 0x65, 0x20, 0xdd, 0x56, 0xfb, 0x65, 0xbf, 0x9f, 0xfb, 0x79, 0x36, 0xfc, ++ 0x5e, 0xd0, 0x9d, 0x62, 0x5d, 0x77, 0x0a, 0xfa, 0xd3, 0x3a, 0xe1, 0xb9, ++ 0xca, 0x6d, 0x92, 0x3f, 0x80, 0x3c, 0xfe, 0x78, 0x64, 0x9d, 0xe9, 0x5d, ++ 0xf5, 0x8b, 0xcb, 0x90, 0xae, 0x7a, 0x3e, 0x59, 0x29, 0xd6, 0xbd, 0x7c, ++ 0xbb, 0x91, 0xfc, 0x55, 0xfc, 0xfe, 0x0f, 0xca, 0x9d, 0x9e, 0x3f, 0x56, ++ 0x8a, 0xf5, 0xaf, 0xd4, 0xad, 0xbf, 0xca, 0x2b, 0xe9, 0xe0, 0xe3, 0x7e, ++ 0x74, 0x4f, 0xf8, 0xea, 0x6f, 0x41, 0x3a, 0x57, 0x6e, 0x37, 0xb2, 0xde, ++ 0xe0, 0xd3, 0xe8, 0xb5, 0x52, 0xe3, 0xeb, 0x3e, 0xe0, 0xd5, 0xe0, 0xd4, ++ 0xe0, 0xfe, 0xa1, 0xf0, 0xf6, 0x4f, 0x13, 0xf9, 0xad, 0x11, 0x6c, 0x04, ++ 0xd1, 0xa9, 0x3c, 0xe1, 0xba, 0xe8, 0xa4, 0xf7, 0x73, 0x77, 0x1d, 0x1e, ++ 0x41, 0xdf, 0x5b, 0xbb, 0x7c, 0x64, 0x20, 0xc5, 0xfb, 0x1a, 0x1f, 0xe8, ++ 0xdf, 0x2f, 0x13, 0x7e, 0xf2, 0xd4, 0xcd, 0xdc, 0x6f, 0xbc, 0xd4, 0x58, ++ 0x6c, 0x1d, 0x89, 0xf1, 0x4c, 0x9b, 0xc1, 0x25, 0xa9, 0x14, 0x9f, 0xc5, ++ 0x8e, 0x04, 0xbc, 0xe4, 0x37, 0xcb, 0xac, 0x02, 0xfa, 0x5d, 0x4d, 0x59, ++ 0x9b, 0xf0, 0xfb, 0x83, 0x79, 0x27, 0x0a, 0xe6, 0x60, 0xfc, 0x9f, 0x7f, ++ 0xc2, 0x40, 0xe7, 0xef, 0xf6, 0x1c, 0x29, 0xa0, 0x7d, 0xe7, 0xfc, 0xa3, ++ 0x83, 0x12, 0xb2, 0x28, 0xcf, 0xed, 0xa2, 0xef, 0xe3, 0xc0, 0x38, 0x64, ++ 0x5f, 0xbb, 0xda, 0xf2, 0x36, 0xe1, 0xf9, 0x84, 0xae, 0xb6, 0x92, 0x02, ++ 0x1c, 0x57, 0x82, 0xe7, 0xd0, 0x0f, 0xc8, 0x13, 0x76, 0xa2, 0xa6, 0x2d, ++ 0xcf, 0x1a, 0x7e, 0xfe, 0x7c, 0x4c, 0x1a, 0x8f, 0xef, 0xd7, 0x3b, 0x3f, ++ 0xfd, 0x39, 0xfa, 0xe9, 0x53, 0x77, 0x19, 0xe9, 0x9c, 0xc5, 0x54, 0x63, ++ 0xf0, 0x4d, 0xac, 0xdb, 0xda, 0x73, 0x44, 0xa1, 0x7d, 0xf2, 0xd5, 0x27, ++ 0x96, 0x3c, 0x14, 0x85, 0xf4, 0x7d, 0x51, 0xa2, 0x7d, 0xf2, 0xc3, 0xed, ++ 0x6b, 0x13, 0x17, 0x22, 0x9f, 0x35, 0x19, 0xed, 0xb8, 0xef, 0xdd, 0xd5, ++ 0xf4, 0xe3, 0x03, 0x78, 0xdf, 0xb7, 0x5d, 0xa2, 0xef, 0x5e, 0x54, 0x37, ++ 0x97, 0x66, 0xef, 0x80, 0x7e, 0xde, 0x96, 0x7c, 0x57, 0xf8, 0xf9, 0xb3, ++ 0x3c, 0x87, 0x4a, 0xf0, 0xb1, 0x54, 0x2b, 0xc5, 0xcf, 0x53, 0xfb, 0x19, ++ 0xc9, 0x6e, 0x5e, 0x4c, 0xb3, 0xfe, 0x16, 0xfd, 0x9f, 0x95, 0xee, 0x2d, ++ 0x24, 0xdf, 0x17, 0xf7, 0xef, 0x31, 0x51, 0xdd, 0xde, 0x0e, 0x89, 0xa1, ++ 0x29, 0x3b, 0xec, 0x3c, 0xf8, 0x0a, 0xe2, 0xe3, 0xe2, 0xab, 0x27, 0x4d, ++ 0xe8, 0x84, 0x17, 0x37, 0x9c, 0x34, 0x75, 0x7c, 0x8f, 0x3f, 0x70, 0xc9, ++ 0x2f, 0xb3, 0x00, 0xc5, 0xcd, 0x1b, 0x4d, 0x18, 0xc7, 0x54, 0x6e, 0xd1, ++ 0xfa, 0x1d, 0x26, 0xa4, 0x93, 0x47, 0xf8, 0x47, 0x55, 0xcf, 0x7d, 0x4c, ++ 0xfd, 0x95, 0xe8, 0xcf, 0xc3, 0x7c, 0x2b, 0x9f, 0x91, 0xa9, 0x7e, 0xf7, ++ 0x60, 0xf3, 0x6b, 0x26, 0xe4, 0xe7, 0xaa, 0xed, 0x12, 0x4b, 0xc9, 0x0c, ++ 0xbb, 0xbf, 0x59, 0x8a, 0xf8, 0x5e, 0xc3, 0x12, 0xc6, 0xf9, 0x60, 0x89, ++ 0xd0, 0x3f, 0xab, 0x98, 0x7f, 0x7d, 0x1a, 0x3c, 0xb7, 0x6a, 0x23, 0xaf, ++ 0x5b, 0x60, 0x8f, 0x46, 0xd6, 0x01, 0x6b, 0xfc, 0xbd, 0x42, 0xf0, 0xf7, ++ 0xaa, 0xed, 0xb3, 0xe8, 0xfb, 0x53, 0x3d, 0xbe, 0x5b, 0x88, 0x71, 0xe3, ++ 0x0d, 0xf8, 0x1c, 0xe7, 0xef, 0x65, 0x9b, 0x23, 0xef, 0xaf, 0x10, 0x7c, ++ 0xbd, 0x42, 0xc7, 0xd7, 0x3f, 0x49, 0x13, 0xfa, 0x67, 0x38, 0x1b, 0x8e, ++ 0x7c, 0xfd, 0x75, 0xa1, 0x1a, 0x97, 0x03, 0xd7, 0xbf, 0x3e, 0xb9, 0x72, ++ 0x40, 0x6f, 0xe7, 0xec, 0xdb, 0x84, 0xbd, 0xd6, 0xec, 0xe5, 0xe5, 0x80, ++ 0x81, 0xec, 0x8d, 0xfe, 0xb9, 0xce, 0xc6, 0x2b, 0x04, 0x67, 0x75, 0xdb, ++ 0x65, 0x13, 0xfa, 0xa7, 0x65, 0x4d, 0x5f, 0x10, 0xfe, 0x2b, 0x9a, 0x5a, ++ 0xa9, 0x7e, 0xe4, 0x66, 0xe6, 0x5d, 0x8d, 0xf8, 0xba, 0xb9, 0xc9, 0x6a, ++ 0x47, 0xb9, 0xae, 0xe8, 0xe0, 0x7a, 0x68, 0x5a, 0x93, 0xd9, 0xef, 0x97, ++ 0xf0, 0x7e, 0x3d, 0xd5, 0x39, 0x77, 0xb5, 0xf0, 0xba, 0x49, 0xdf, 0x7e, ++ 0x89, 0xfc, 0x1c, 0x4d, 0x8f, 0x69, 0xdf, 0x77, 0x5c, 0x26, 0xf0, 0xb8, ++ 0x0c, 0x14, 0x78, 0x7a, 0x1e, 0xfa, 0xbb, 0x3c, 0x6e, 0xae, 0x12, 0x71, ++ 0xf2, 0x8a, 0x61, 0x5b, 0x0e, 0xe3, 0x3e, 0x7b, 0x95, 0xb8, 0xbf, 0xfa, ++ 0xe8, 0xc1, 0x58, 0xf4, 0x0f, 0xa7, 0xb1, 0x2f, 0x6e, 0x47, 0xfa, 0xc0, ++ 0x7c, 0x0c, 0xe7, 0x63, 0xcf, 0x44, 0xe2, 0x7d, 0xba, 0xd0, 0x8b, 0xd3, ++ 0xb7, 0x73, 0xbd, 0xa8, 0xb7, 0x6b, 0x5d, 0xa9, 0xd9, 0x33, 0x29, 0x8f, ++ 0x09, 0x71, 0x2a, 0xc2, 0xb5, 0x7a, 0x7b, 0x24, 0xbe, 0xab, 0x74, 0xf1, ++ 0xf9, 0x63, 0x69, 0x3c, 0x3f, 0xf6, 0x82, 0x0e, 0xdf, 0x15, 0x41, 0x66, ++ 0xcd, 0x41, 0x38, 0x54, 0xd9, 0xe5, 0xa7, 0xa7, 0xdb, 0x15, 0x9c, 0xf7, ++ 0x48, 0x2e, 0xd8, 0x5b, 0xb4, 0x93, 0x6a, 0xd6, 0xf7, 0x7e, 0x87, 0xf1, ++ 0x4d, 0xe1, 0x67, 0x6b, 0xfd, 0x99, 0xe2, 0x1c, 0x78, 0xbd, 0x7d, 0xa3, ++ 0x2d, 0x3c, 0x6e, 0x8e, 0x4a, 0xe7, 0xfe, 0xc2, 0xca, 0xf1, 0xb2, 0x0f, ++ 0xe9, 0xd5, 0x1d, 0x6f, 0x0c, 0x3a, 0x98, 0xab, 0x1a, 0x42, 0xf1, 0x06, ++ 0xc4, 0x19, 0xcd, 0x69, 0x49, 0x3c, 0xee, 0xc0, 0x82, 0x92, 0x37, 0x32, ++ 0x64, 0x96, 0x98, 0x18, 0x8a, 0x37, 0x1e, 0x71, 0x6e, 0xaa, 0xc8, 0x83, ++ 0x7e, 0xf5, 0x76, 0x2e, 0xf7, 0x9d, 0xe3, 0x60, 0x3c, 0x3c, 0x7f, 0xad, ++ 0x30, 0xf2, 0x47, 0xab, 0xb7, 0x9b, 0xe9, 0x9c, 0x62, 0x35, 0xd0, 0x9f, ++ 0xe2, 0x8a, 0x26, 0x7e, 0x9e, 0xc2, 0xd3, 0x24, 0x95, 0x22, 0xdd, 0xc1, ++ 0x5f, 0x3f, 0x9a, 0x86, 0xfb, 0xb1, 0x98, 0x52, 0x85, 0x75, 0xcf, 0x6a, ++ 0xe4, 0x7c, 0x3f, 0xab, 0xe4, 0x0b, 0xe2, 0x97, 0xa3, 0x83, 0xf8, 0x7a, ++ 0x2f, 0x2b, 0x6a, 0x4a, 0x6f, 0xfe, 0xbb, 0xe6, 0xb7, 0xe3, 0xf9, 0x30, ++ 0x35, 0xcc, 0x7f, 0xaf, 0x02, 0x39, 0xc5, 0xe7, 0xab, 0x9a, 0x78, 0x3d, ++ 0x52, 0xc3, 0x81, 0x6f, 0xfa, 0x67, 0xa2, 0x9e, 0x6b, 0xfe, 0xaf, 0xfe, ++ 0x8b, 0xa1, 0xfd, 0x5a, 0xd8, 0x45, 0xcd, 0x2f, 0x0c, 0x82, 0x5f, 0x38, ++ 0x90, 0xfb, 0x45, 0xf4, 0xbd, 0xc9, 0xbb, 0x85, 0x7c, 0x2d, 0xb3, 0xf3, ++ 0x7d, 0xba, 0xbb, 0x85, 0xfd, 0x61, 0x52, 0x1d, 0xf1, 0x79, 0x95, 0xb1, ++ 0xfe, 0x50, 0x3c, 0xfa, 0x59, 0x3b, 0x78, 0xbd, 0x00, 0xdb, 0x87, 0x1f, ++ 0x85, 0x03, 0xfd, 0xf8, 0xf6, 0x4b, 0x75, 0xf1, 0xb0, 0xee, 0xce, 0x97, ++ 0x24, 0xaa, 0x87, 0xc3, 0xf7, 0xf1, 0x7b, 0x94, 0x9d, 0x4b, 0xea, 0x3f, ++ 0x41, 0xbf, 0xfb, 0xeb, 0x1d, 0x16, 0xf2, 0x37, 0xef, 0x06, 0xbf, 0x65, ++ 0x4a, 0x5e, 0x4f, 0xb9, 0xd4, 0xe4, 0x5b, 0xfb, 0x6e, 0x56, 0x0d, 0x7b, ++ 0x88, 0xfc, 0xcf, 0x87, 0x58, 0x1d, 0xb5, 0x95, 0x82, 0x9f, 0x3b, 0x1b, ++ 0x6b, 0xe9, 0xfb, 0xa0, 0x9a, 0xbf, 0x42, 0xef, 0x0f, 0xec, 0xe9, 0x8f, ++ 0x54, 0x0a, 0xbe, 0xaf, 0xd4, 0xf1, 0x5f, 0x54, 0x7a, 0x24, 0xdf, 0xd5, ++ 0xbc, 0x1d, 0x4d, 0x7e, 0x63, 0xd7, 0x51, 0xd9, 0x8e, 0xfb, 0x31, 0x80, ++ 0xaf, 0xdf, 0xa4, 0x85, 0xe3, 0x45, 0xf8, 0x21, 0x0d, 0x07, 0xa2, 0x88, ++ 0xae, 0x5d, 0x27, 0x6d, 0x64, 0x47, 0xfe, 0x2c, 0xf8, 0xed, 0xa2, 0xc8, ++ 0x3f, 0xd7, 0x8c, 0x93, 0x09, 0x0f, 0x86, 0xf1, 0xbc, 0xcd, 0x6e, 0x79, ++ 0x6d, 0x20, 0xd2, 0x11, 0xf1, 0x8e, 0xf5, 0xf7, 0x2f, 0xb7, 0xbc, 0x36, ++ 0x82, 0x9f, 0xfb, 0xf6, 0x13, 0xfe, 0x57, 0x6d, 0x93, 0x23, 0xbe, 0x0f, ++ 0x5b, 0x59, 0x1f, 0xf9, 0xfd, 0xd7, 0x9a, 0xb7, 0x6f, 0xa3, 0xef, 0x08, ++ 0x55, 0xef, 0xef, 0x86, 0x6b, 0x88, 0x29, 0x31, 0x04, 0x57, 0x5f, 0x72, ++ 0x20, 0x49, 0x3c, 0x8e, 0x34, 0x48, 0x91, 0x71, 0x64, 0xf5, 0x3e, 0xd9, ++ 0x13, 0x5e, 0x77, 0x06, 0xeb, 0xb9, 0x03, 0xf5, 0x51, 0xba, 0x90, 0x07, ++ 0xa6, 0x04, 0x93, 0x31, 0xff, 0x35, 0x00, 0x9d, 0x06, 0x80, 0xaf, 0xa6, ++ 0x89, 0xd3, 0xd5, 0xd0, 0xcc, 0x5b, 0x98, 0xff, 0x16, 0x9e, 0x27, 0x31, ++ 0xd2, 0xfc, 0x3d, 0xee, 0x17, 0xf9, 0x56, 0xe3, 0xfd, 0xaf, 0x33, 0xad, ++ 0x7c, 0xff, 0xfa, 0xaa, 0xaf, 0x02, 0xfb, 0xf7, 0x0f, 0x94, 0xa9, 0xae, ++ 0xf3, 0xfe, 0xb7, 0x57, 0x0e, 0x0d, 0xd7, 0xa3, 0x0c, 0xe1, 0x04, 0xba, ++ 0x56, 0x1b, 0x83, 0xc9, 0x14, 0x6f, 0x9e, 0x34, 0x10, 0x7c, 0xd5, 0x27, ++ 0x2f, 0x27, 0x0f, 0xb2, 0xa1, 0x5e, 0xda, 0x52, 0x82, 0xdf, 0x0f, 0x9d, ++ 0x2e, 0xf4, 0xdf, 0xe1, 0x81, 0xd6, 0xe5, 0xc8, 0xcf, 0x3e, 0x9c, 0x37, ++ 0x25, 0x34, 0xce, 0xcb, 0x69, 0xbc, 0x7e, 0x8f, 0xe1, 0x7a, 0x9d, 0xe8, ++ 0x6d, 0xfc, 0x92, 0x8f, 0x2b, 0xd6, 0xfb, 0x10, 0x9b, 0x2d, 0xe2, 0x6a, ++ 0xce, 0x4f, 0x39, 0x69, 0x7c, 0xbd, 0x10, 0x8f, 0x8c, 0x4b, 0xef, 0x25, ++ 0x1e, 0xb9, 0x5e, 0xbf, 0x13, 0xec, 0xc3, 0xa9, 0x85, 0x12, 0xd6, 0x33, ++ 0x29, 0x3e, 0x8c, 0x87, 0xf7, 0xbc, 0xc7, 0xf5, 0x42, 0x4d, 0xf3, 0xb2, ++ 0x8f, 0x90, 0xdf, 0xab, 0xdf, 0x37, 0x53, 0x9d, 0xd7, 0xfd, 0x2d, 0xcb, ++ 0x86, 0x52, 0xbd, 0xaf, 0xd7, 0x7b, 0x03, 0xfa, 0x1b, 0x5f, 0xb7, 0xac, ++ 0xb8, 0x81, 0xf2, 0x83, 0xd2, 0x43, 0x04, 0x97, 0x0f, 0xe1, 0x73, 0xa2, ++ 0x5f, 0x73, 0x26, 0x19, 0xeb, 0x52, 0x2b, 0x9b, 0xcf, 0x24, 0x93, 0xdd, ++ 0xdd, 0x3b, 0x7a, 0x93, 0x2f, 0x06, 0xfd, 0x97, 0xbc, 0xe9, 0x78, 0x1d, ++ 0xfc, 0x09, 0xe2, 0x3f, 0xf0, 0x6b, 0x88, 0xff, 0xf6, 0xb4, 0x15, 0x68, ++ 0x7e, 0x8c, 0x15, 0xc7, 0xad, 0x3c, 0xaa, 0x78, 0x10, 0x3f, 0x95, 0x47, ++ 0x0b, 0x8e, 0x57, 0xa0, 0x7f, 0x71, 0xa2, 0xa8, 0x00, 0xd5, 0xb9, 0x74, ++ 0xa2, 0x80, 0xfc, 0x98, 0x7c, 0xf4, 0x63, 0x6c, 0x21, 0xbf, 0xa6, 0x5b, ++ 0x4f, 0xa6, 0x73, 0x3f, 0xa6, 0xab, 0x35, 0x8a, 0xf2, 0x0b, 0x12, 0x1b, ++ 0xc8, 0xf9, 0x87, 0x0d, 0x8a, 0xe0, 0x9f, 0xd5, 0x0d, 0xaf, 0x93, 0xbd, ++ 0x5f, 0xdd, 0x28, 0x47, 0xd4, 0x2f, 0x6a, 0xef, 0xdd, 0x99, 0xae, 0xd0, ++ 0x38, 0xcb, 0x34, 0xfe, 0xa9, 0x97, 0xdc, 0xc4, 0x1f, 0xbb, 0x78, 0xbb, ++ 0xba, 0x71, 0x0f, 0xad, 0x6f, 0x95, 0xb1, 0x9e, 0xe8, 0x5d, 0xb3, 0xdd, ++ 0xc8, 0xef, 0xef, 0xe0, 0xad, 0xf6, 0x7d, 0x58, 0x1f, 0x8b, 0xf7, 0x21, ++ 0x3e, 0x8e, 0xe3, 0x25, 0xa0, 0xc3, 0x34, 0x93, 0x3f, 0x03, 0xf3, 0xd3, ++ 0xc7, 0x32, 0xb9, 0x9f, 0xaf, 0xa7, 0xc7, 0xe7, 0xe9, 0x3c, 0xff, 0x71, ++ 0xec, 0xac, 0x77, 0x00, 0xf2, 0xcb, 0xb1, 0x42, 0xef, 0x50, 0x7b, 0x2f, ++ 0x76, 0xc2, 0xc7, 0x8a, 0x78, 0x5c, 0x2b, 0x09, 0x7c, 0x37, 0xf0, 0x73, ++ 0x53, 0xfa, 0xe7, 0x3e, 0x4b, 0x97, 0xc4, 0x77, 0x42, 0x22, 0xcf, 0xb7, ++ 0x6a, 0xed, 0xa9, 0x74, 0xae, 0x3f, 0xa7, 0x99, 0x7a, 0xff, 0x2e, 0xe0, ++ 0x6f, 0xd2, 0xb5, 0x73, 0x09, 0xec, 0x31, 0x43, 0x01, 0x46, 0xc5, 0x46, ++ 0xfb, 0x06, 0xe1, 0xd7, 0xa7, 0x86, 0x7d, 0xd7, 0x61, 0xce, 0xcd, 0x46, ++ 0xf2, 0x17, 0x4e, 0x31, 0xfb, 0xeb, 0x58, 0xef, 0x38, 0x43, 0xd3, 0xb3, ++ 0xe3, 0xb8, 0x7d, 0xd5, 0xe7, 0xcb, 0xe7, 0x89, 0xf7, 0x3c, 0x9b, 0x55, ++ 0xbe, 0x5f, 0xa4, 0x3b, 0x3f, 0x33, 0x4f, 0x3b, 0xdf, 0xa4, 0x3b, 0xef, ++ 0x36, 0x4f, 0xf8, 0x3b, 0xf3, 0x74, 0xfe, 0xce, 0xd3, 0xe9, 0xc2, 0x8f, ++ 0x1f, 0xc2, 0x86, 0xa0, 0x1e, 0xac, 0x17, 0xe7, 0xef, 0xd6, 0x0e, 0x8f, ++ 0xf2, 0x87, 0xe7, 0xb3, 0xf4, 0xed, 0x61, 0xb1, 0x2f, 0x82, 0xe7, 0x87, ++ 0xb0, 0xad, 0x19, 0xfe, 0x2e, 0xe5, 0x7d, 0x8e, 0xb5, 0x9e, 0x7d, 0x85, ++ 0xea, 0xdd, 0xce, 0x46, 0xb1, 0x81, 0x3c, 0xaf, 0x47, 0xf9, 0xef, 0xca, ++ 0x3e, 0xf2, 0xdf, 0x35, 0xdd, 0x72, 0x39, 0x37, 0x82, 0xcf, 0x34, 0xba, ++ 0x5c, 0x12, 0xdf, 0x83, 0xd1, 0xd3, 0x65, 0xb7, 0xa6, 0xaf, 0xc4, 0xbe, ++ 0x5d, 0xb4, 0xd8, 0xb7, 0xf3, 0x1b, 0xbd, 0xbb, 0x51, 0x9e, 0x2b, 0x2d, ++ 0x17, 0x4d, 0xbc, 0xee, 0x30, 0x68, 0x42, 0x7d, 0x56, 0x33, 0x9c, 0xfb, ++ 0x4d, 0x97, 0x4a, 0x25, 0xda, 0x6f, 0x07, 0x38, 0xfb, 0x9b, 0xc3, 0xf4, ++ 0xfb, 0xa5, 0x54, 0x1e, 0x7f, 0xdd, 0x7f, 0x8b, 0x44, 0x79, 0xd7, 0x56, ++ 0x7c, 0x1e, 0xe3, 0xac, 0x7a, 0x89, 0xea, 0xbc, 0x2b, 0x03, 0xed, 0x26, ++ 0xe4, 0xa7, 0x21, 0x0d, 0x8b, 0x1f, 0x26, 0xb9, 0xf5, 0xb1, 0xd3, 0x2c, ++ 0xec, 0xbb, 0x1a, 0x33, 0x2d, 0xdc, 0x4e, 0x76, 0xd3, 0x4f, 0x5b, 0x77, ++ 0xb7, 0x1d, 0x8b, 0xf7, 0x71, 0x7d, 0x9c, 0x48, 0x2d, 0x3e, 0x8f, 0x76, ++ 0x71, 0x86, 0xb0, 0x83, 0xfa, 0x73, 0x51, 0x43, 0x59, 0x7b, 0x59, 0x3a, ++ 0xc0, 0x33, 0xdf, 0x2d, 0xb9, 0xb0, 0x1e, 0xa0, 0x2f, 0x3a, 0xcf, 0x5e, ++ 0x30, 0xea, 0x75, 0x44, 0xc3, 0xf5, 0xd2, 0xbb, 0x33, 0xdd, 0xfb, 0x4e, ++ 0x3a, 0xca, 0x79, 0xfb, 0xe5, 0x5b, 0x30, 0x8f, 0x7a, 0x6c, 0xf8, 0x67, ++ 0xfd, 0xd1, 0x8e, 0x56, 0xf5, 0xc1, 0xc7, 0x1f, 0x0b, 0x3c, 0xeb, 0xbf, ++ 0x2b, 0xe3, 0x1a, 0xaa, 0xd6, 0xe2, 0xf7, 0x55, 0x6a, 0x9d, 0xde, 0x0e, ++ 0xd2, 0x9f, 0x86, 0x6f, 0x63, 0x47, 0x30, 0x1c, 0xa7, 0xe3, 0x37, 0x6b, ++ 0x25, 0xa4, 0x13, 0x23, 0xfe, 0xef, 0x4b, 0x7e, 0x3e, 0x13, 0xe3, 0x7e, ++ 0x96, 0xce, 0xbf, 0x77, 0x0f, 0xb8, 0xa7, 0x7d, 0x97, 0x55, 0xe9, 0xbc, ++ 0x4e, 0xeb, 0x98, 0xd1, 0x9f, 0x41, 0x79, 0x8a, 0x9c, 0xeb, 0xdb, 0xf7, ++ 0xaa, 0xd9, 0xf7, 0x46, 0x2e, 0xea, 0xb3, 0xce, 0xd6, 0xa3, 0xb9, 0xa6, ++ 0x30, 0xba, 0x5e, 0x5c, 0x0b, 0x7a, 0x00, 0xed, 0x4a, 0xf3, 0xc1, 0x64, ++ 0xd5, 0x16, 0xce, 0x77, 0x06, 0xe2, 0x37, 0x49, 0xd2, 0xf8, 0x4f, 0x11, ++ 0xf6, 0x32, 0x92, 0x0f, 0x2f, 0x22, 0x1f, 0xe6, 0x60, 0x7b, 0x26, 0x76, ++ 0x10, 0xea, 0xe3, 0x5d, 0xa7, 0x62, 0x07, 0xe3, 0x78, 0x7b, 0x79, 0xdb, ++ 0xcd, 0xaf, 0x4d, 0xfc, 0x7b, 0xf6, 0x10, 0x1f, 0x0d, 0x99, 0x17, 0x13, ++ 0x0e, 0xdf, 0xc3, 0x04, 0xdf, 0xa5, 0x7a, 0x3e, 0x0e, 0x63, 0x1d, 0x43, ++ 0xe6, 0x8c, 0x0c, 0xbf, 0x5f, 0xdb, 0x17, 0x1f, 0x5b, 0x33, 0x88, 0x8f, ++ 0x3b, 0x22, 0xf8, 0x58, 0x5b, 0x6f, 0x3d, 0x7e, 0xcf, 0x07, 0xe3, 0x80, ++ 0x16, 0x33, 0x7d, 0xcf, 0x07, 0xf3, 0xd7, 0x8e, 0x30, 0x39, 0x19, 0x9a, ++ 0xc1, 0xf5, 0xcf, 0x58, 0xf1, 0xfd, 0x9e, 0xf1, 0xcc, 0x47, 0xdf, 0x39, ++ 0x1c, 0x2b, 0xbe, 0xe3, 0x33, 0x5e, 0x61, 0x01, 0x25, 0x1e, 0xf7, 0xcd, ++ 0x02, 0x32, 0xdf, 0xf7, 0xe5, 0xe7, 0x2d, 0xc6, 0x08, 0x7e, 0x1e, 0xab, ++ 0x04, 0x5a, 0xb1, 0x8e, 0x62, 0xbc, 0xd8, 0xe7, 0x99, 0xc0, 0xda, 0xe9, ++ 0xb9, 0x29, 0x2c, 0x48, 0xad, 0x9b, 0xd9, 0xe9, 0x1c, 0x45, 0x11, 0x73, ++ 0x51, 0x3b, 0xce, 0x12, 0x98, 0x8e, 0xee, 0x54, 0x4e, 0x7d, 0x3d, 0xd5, ++ 0x25, 0x06, 0x92, 0x15, 0xc7, 0x79, 0x8b, 0x38, 0xaf, 0xd1, 0x0b, 0xdd, ++ 0x42, 0xeb, 0x57, 0xe8, 0xbb, 0x3d, 0xc4, 0x9f, 0x32, 0x9e, 0xd7, 0xe9, ++ 0xfd, 0xbb, 0x2f, 0xb3, 0x33, 0xb8, 0xdc, 0xd3, 0xc7, 0x45, 0x90, 0xbe, ++ 0x97, 0x18, 0xe5, 0xb9, 0xf0, 0x7b, 0x6d, 0x38, 0xc9, 0x44, 0x85, 0x95, ++ 0x63, 0x7d, 0xd3, 0x64, 0x85, 0x59, 0xa2, 0x01, 0xde, 0x5d, 0x87, 0x0c, ++ 0x24, 0xcf, 0x2d, 0x1d, 0xaa, 0x1f, 0xeb, 0x53, 0x5d, 0x09, 0xe2, 0xbd, ++ 0xcf, 0x19, 0xd5, 0xe1, 0x8e, 0x75, 0x73, 0x79, 0x45, 0x93, 0x83, 0xf5, ++ 0x18, 0xda, 0x7a, 0xf5, 0x78, 0x98, 0x00, 0xe3, 0x61, 0x9e, 0x6d, 0xac, ++ 0x02, 0x91, 0x28, 0xe1, 0x31, 0x40, 0xf3, 0xdd, 0xc8, 0xf8, 0x39, 0x92, ++ 0x42, 0xa6, 0x52, 0xfd, 0x73, 0x69, 0x46, 0xa6, 0xd0, 0xf7, 0x41, 0x8a, ++ 0xa3, 0x8a, 0x21, 0x8e, 0x42, 0x7d, 0x6f, 0xb0, 0xf8, 0x08, 0x1f, 0xd3, ++ 0x33, 0x54, 0xba, 0x8f, 0xfb, 0x25, 0xb1, 0x30, 0xce, 0x84, 0x8d, 0x12, ++ 0x7b, 0x0f, 0xf7, 0x3f, 0xb2, 0xf8, 0x7a, 0xb5, 0xf1, 0x27, 0x00, 0x23, ++ 0xe0, 0xf9, 0xc2, 0xe9, 0x19, 0xdc, 0x9e, 0x61, 0x4a, 0xf5, 0xbd, 0x78, ++ 0xbe, 0x8f, 0x12, 0x4b, 0x05, 0xcd, 0x25, 0x76, 0xfe, 0x9d, 0xa3, 0x64, ++ 0xfa, 0xce, 0xd1, 0xf5, 0xe2, 0xb5, 0x2b, 0x99, 0x7f, 0xef, 0x32, 0xf6, ++ 0xce, 0x60, 0xe7, 0xcf, 0x0a, 0x42, 0xfb, 0x49, 0x2e, 0xfc, 0xee, 0x51, ++ 0x6c, 0xe8, 0x3b, 0x9b, 0x2e, 0xed, 0xdf, 0x83, 0x08, 0x44, 0xfe, 0x7b, ++ 0x10, 0x77, 0x64, 0x2c, 0xf9, 0x11, 0xf2, 0xa3, 0x56, 0xaf, 0xc7, 0xbc, ++ 0xfc, 0xdf, 0x7d, 0xd0, 0xd7, 0xeb, 0x85, 0xd5, 0xe7, 0xb1, 0x0b, 0x61, ++ 0xe7, 0xb0, 0xb5, 0xba, 0x92, 0x6d, 0xfe, 0xd9, 0x2a, 0x9e, 0xf3, 0x5b, ++ 0x90, 0x68, 0xa1, 0x73, 0xbf, 0x79, 0x96, 0xfe, 0xf9, 0x68, 0xc7, 0x06, ++ 0x3a, 0xbd, 0x34, 0xfe, 0xfb, 0xd2, 0xf6, 0xc1, 0x34, 0x98, 0xe2, 0x1f, ++ 0xed, 0x89, 0x09, 0xf1, 0xbb, 0x95, 0xb9, 0xc7, 0x21, 0xbe, 0x43, 0x75, ++ 0x83, 0xfc, 0x3b, 0x50, 0xdd, 0xe7, 0xae, 0x92, 0x19, 0x9d, 0x57, 0xb4, ++ 0x9a, 0x79, 0x7d, 0xe5, 0x63, 0x20, 0x1f, 0xf8, 0x1d, 0x26, 0x90, 0x2e, ++ 0x15, 0xeb, 0x68, 0xd8, 0x83, 0xc5, 0x54, 0x8f, 0xb9, 0xde, 0x61, 0x71, ++ 0xe1, 0x79, 0x09, 0x33, 0xc2, 0x6d, 0x0d, 0xc1, 0x5d, 0x6b, 0x11, 0xdf, ++ 0x05, 0xb5, 0xf0, 0x7d, 0x71, 0x7d, 0x3d, 0x68, 0xad, 0xcd, 0x40, 0xdf, ++ 0x1d, 0xad, 0x65, 0xd1, 0x74, 0x0e, 0x3d, 0x29, 0xda, 0xbb, 0x2e, 0x03, ++ 0xe0, 0xba, 0x2f, 0xa6, 0x88, 0xce, 0x77, 0x67, 0xef, 0x9c, 0xe4, 0x44, ++ 0xbf, 0x31, 0x7c, 0xfd, 0x93, 0xb4, 0xf5, 0x1b, 0x7a, 0xd6, 0x47, 0xc2, ++ 0x7a, 0x1f, 0xc9, 0xe8, 0xa5, 0x1e, 0x51, 0x5b, 0xa7, 0xf6, 0xef, 0x76, ++ 0xd8, 0x05, 0xfe, 0xb4, 0x75, 0xdb, 0xb5, 0x73, 0x4a, 0x6e, 0x25, 0xe2, ++ 0x9c, 0x92, 0x86, 0x8f, 0xc7, 0xa2, 0xf9, 0xba, 0x8d, 0xb8, 0xf3, 0x9f, ++ 0x45, 0xef, 0xaa, 0xa8, 0x37, 0xf4, 0xeb, 0xfd, 0xff, 0xdc, 0x29, 0xbc, ++ 0x16, 0xa0, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 xsem_int_table_data_e1h[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xd3, 0xd7, ++ 0x66, 0x60, 0xf8, 0x51, 0x8f, 0xc0, 0x2e, 0x9a, 0x0c, 0x0c, 0x5d, 0xd2, ++ 0xa8, 0x62, 0xb4, 0xc4, 0x1d, 0x12, 0x0c, 0x0c, 0x97, 0x80, 0xf8, 0x0b, ++ 0x10, 0x67, 0x02, 0xed, 0xf5, 0x92, 0x64, 0x60, 0xf0, 0x06, 0xe2, 0x6d, ++ 0x40, 0xbc, 0x1d, 0x88, 0xc5, 0xa5, 0x18, 0x18, 0x02, 0x80, 0x38, 0x10, ++ 0x88, 0xfb, 0x80, 0xfc, 0x7e, 0x20, 0x4e, 0x07, 0xe2, 0x24, 0xa8, 0x1b, ++ 0xb3, 0x05, 0x19, 0x18, 0x72, 0x81, 0x38, 0x1f, 0x88, 0x0b, 0x81, 0x58, ++ 0x48, 0x80, 0x81, 0x41, 0x58, 0x80, 0x78, 0xfb, 0xcb, 0x15, 0x19, 0x18, ++ 0x5e, 0xab, 0x22, 0xf8, 0x5a, 0x6a, 0x0c, 0x0c, 0xc9, 0x1a, 0xf4, 0xf3, ++ 0xff, 0x60, 0xc3, 0x8e, 0xb6, 0xf4, 0xb5, 0xef, 0x14, 0xd0, 0xbe, 0xe5, ++ 0x6e, 0x08, 0xbe, 0x04, 0x90, 0xbd, 0xc2, 0x0d, 0x55, 0xcd, 0x4a, 0x37, ++ 0xfc, 0x66, 0xac, 0x42, 0x93, 0x5f, 0x8d, 0xc6, 0x5f, 0x83, 0x47, 0x7f, ++ 0xa2, 0x0d, 0x2a, 0x7f, 0x99, 0x29, 0x2a, 0x7f, 0x9d, 0x39, 0x03, 0xc3, ++ 0x43, 0x24, 0x35, 0xcb, 0x4d, 0xf1, 0xbb, 0x05, 0x1d, 0x0b, 0x02, 0xfd, ++ 0x27, 0x84, 0x27, 0x4c, 0x97, 0x30, 0xa2, 0xf2, 0x27, 0x32, 0xa1, 0xf2, ++ 0xf9, 0xa1, 0x7c, 0x00, 0xba, 0x0b, 0x80, 0x74, 0xa8, 0x03, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00 ++}; ++ ++static const u8 xsem_pram_data_e1h[] = { ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d, ++ 0x0d, 0x78, 0x54, 0xd5, 0x99, 0xf0, 0xb9, 0x3f, 0x73, 0x67, 0x26, 0x99, ++ 0x99, 0xdc, 0x24, 0x43, 0x32, 0x60, 0x12, 0x6e, 0x7e, 0xd0, 0xa0, 0x01, ++ 0x87, 0x98, 0x60, 0xb0, 0x58, 0x6e, 0x20, 0xe1, 0x47, 0xa3, 0x0e, 0x08, ++ 0x2c, 0xb4, 0x40, 0x26, 0x28, 0x88, 0x16, 0x6d, 0xc4, 0x9f, 0xc6, 0xdd, ++ 0x50, 0x06, 0x09, 0xbf, 0x09, 0x21, 0xe1, 0x4f, 0x70, 0xd1, 0x1d, 0x10, ++ 0x5d, 0xea, 0x63, 0xfb, 0xc5, 0x56, 0x5b, 0x75, 0xbb, 0x76, 0x82, 0xd6, ++ 0x46, 0xab, 0x35, 0x68, 0xd7, 0x87, 0x76, 0x77, 0x65, 0xa0, 0x15, 0xbf, ++ 0xba, 0x76, 0x1b, 0xd9, 0x6d, 0x97, 0x6e, 0xbb, 0xf5, 0x7b, 0xdf, 0xf7, ++ 0x9c, 0xcb, 0xcc, 0xbd, 0x99, 0x00, 0xfe, 0xec, 0xb7, 0xbb, 0xdf, 0xf3, ++ 0xc5, 0xc7, 0xe7, 0x70, 0xee, 0x3d, 0x3f, 0xef, 0x79, 0xcf, 0xfb, 0x7f, ++ 0xde, 0x73, 0xc7, 0xc5, 0x46, 0xb1, 0xe0, 0x58, 0xc6, 0x3e, 0xc6, 0xbf, ++ 0x69, 0x8c, 0x4d, 0xcc, 0x65, 0x8c, 0xd5, 0xa6, 0xca, 0x16, 0x0f, 0x8b, ++ 0x65, 0xe7, 0x30, 0x96, 0xdb, 0x21, 0x31, 0x56, 0xc3, 0xd8, 0xca, 0x76, ++ 0x25, 0x3e, 0x0b, 0xfe, 0x59, 0xd8, 0xd1, 0xf2, 0x0a, 0xd6, 0x97, 0xb7, ++ 0xb9, 0x0d, 0x77, 0x29, 0x63, 0xfd, 0x0f, 0xb8, 0xfd, 0x35, 0x50, 0x3f, ++ 0xbd, 0x5d, 0x09, 0xbb, 0xa1, 0x6b, 0xa3, 0xe2, 0xa3, 0xfa, 0xb2, 0x2e, ++ 0x57, 0xd8, 0x6d, 0xc0, 0xf3, 0xad, 0x1f, 0xbd, 0x9c, 0x8f, 0xef, 0x37, ++ 0x4a, 0x61, 0x06, 0x75, 0xc6, 0xee, 0x66, 0x6c, 0x32, 0x63, 0x6b, 0x3c, ++ 0xf0, 0x4f, 0xa8, 0x2f, 0xab, 0x48, 0x76, 0xe0, 0xfb, 0x77, 0xb7, 0x48, ++ 0xe1, 0x18, 0xbe, 0x66, 0xa6, 0x6f, 0x12, 0xbc, 0xbf, 0x95, 0xf1, 0xf7, ++ 0xcd, 0x0f, 0x28, 0x1a, 0x93, 0xa1, 0xbe, 0xef, 0xb6, 0x26, 0x36, 0x91, ++ 0xb1, 0x5b, 0x7a, 0x60, 0x16, 0x0f, 0x35, 0x64, 0x1f, 0xf3, 0xf6, 0x8c, ++ 0x15, 0x30, 0x16, 0xe1, 0x8f, 0x58, 0xcb, 0x16, 0x78, 0x5f, 0x99, 0x7a, ++ 0x1f, 0x61, 0x5d, 0x1f, 0x29, 0xd0, 0xaf, 0x39, 0xe6, 0x78, 0xbe, 0x6f, ++ 0xd6, 0xfb, 0x2c, 0x80, 0xef, 0xb5, 0xd4, 0x73, 0x58, 0xcf, 0x31, 0xfc, ++ 0xc7, 0x14, 0xc6, 0x2e, 0x65, 0xfe, 0xe0, 0xe9, 0x6c, 0xf8, 0x77, 0x98, ++ 0x85, 0x3f, 0x56, 0xa0, 0x6c, 0xc8, 0x67, 0x6c, 0x74, 0x0a, 0x5f, 0xce, ++ 0x92, 0x31, 0x80, 0x7e, 0x14, 0x63, 0x73, 0x19, 0x73, 0xb1, 0x72, 0x18, ++ 0xa7, 0xf6, 0x32, 0x17, 0x2b, 0x83, 0xf5, 0x59, 0x78, 0x6c, 0xe3, 0x78, ++ 0x5c, 0xd6, 0x24, 0x11, 0x1e, 0x97, 0xf9, 0x18, 0xd5, 0xdf, 0x9d, 0x2b, ++ 0xc5, 0x1f, 0x2c, 0xa5, 0x7e, 0x6c, 0x7a, 0x35, 0x94, 0xf0, 0xbc, 0x20, ++ 0x0f, 0xca, 0x20, 0x33, 0x0b, 0xa1, 0x8c, 0x78, 0x58, 0x22, 0x1b, 0xe0, ++ 0x9f, 0xdb, 0x76, 0xd9, 0x7b, 0xb8, 0xfe, 0x0d, 0x38, 0xd5, 0x68, 0x6a, ++ 0x9f, 0x08, 0xc0, 0xfb, 0x05, 0x2c, 0xea, 0x62, 0x00, 0xdf, 0x9f, 0xb1, ++ 0x18, 0x95, 0x8b, 0x59, 0x9c, 0xca, 0x2f, 0xb3, 0x04, 0xc1, 0xb1, 0x94, ++ 0x0d, 0x95, 0xa8, 0x50, 0xbf, 0x4b, 0x49, 0x6c, 0x62, 0x30, 0x4f, 0x38, ++ 0x14, 0x9d, 0x8e, 0xfb, 0xfb, 0xbb, 0xfa, 0x63, 0xef, 0x4a, 0xf0, 0xfe, ++ 0xfe, 0x6a, 0xa9, 0x76, 0x0a, 0x94, 0xcc, 0x97, 0x47, 0xeb, 0xbe, 0xd0, ++ 0xfa, 0xac, 0xf9, 0x55, 0x16, 0xb9, 0x0e, 0xc7, 0x61, 0x4c, 0x76, 0x45, ++ 0xfc, 0x8c, 0x8d, 0xb7, 0xd6, 0x79, 0x98, 0xc5, 0x2a, 0x82, 0x8c, 0xe9, ++ 0x3d, 0x3e, 0x4e, 0x2f, 0x87, 0x59, 0x3f, 0x83, 0xfa, 0xf8, 0x06, 0x41, ++ 0x2f, 0x8d, 0xef, 0xcb, 0x21, 0x58, 0x77, 0xcf, 0xf3, 0x2c, 0x8c, 0xf5, ++ 0x10, 0x6c, 0xe6, 0x14, 0xa8, 0x87, 0xba, 0xb2, 0xe2, 0x1b, 0xa0, 0xde, ++ 0xf3, 0x78, 0xac, 0x1e, 0xf1, 0x72, 0xac, 0x05, 0x30, 0x0f, 0xfd, 0x8f, ++ 0x35, 0xba, 0xa5, 0x68, 0x15, 0x94, 0x2e, 0xdd, 0x15, 0x81, 0x32, 0xa4, ++ 0x32, 0xa6, 0x00, 0x9e, 0xea, 0x1b, 0xd6, 0x4b, 0x0a, 0xb4, 0x9b, 0x1b, ++ 0xe5, 0xe3, 0x8c, 0x37, 0x35, 0x99, 0x5d, 0x09, 0xf5, 0xc3, 0x31, 0x49, ++ 0x15, 0xcf, 0xb1, 0xbf, 0xae, 0xc7, 0x24, 0x1d, 0xea, 0xe3, 0xa1, 0xfe, ++ 0xa0, 0x84, 0xef, 0x75, 0x17, 0x83, 0x71, 0x1a, 0x1a, 0x72, 0x5d, 0xc9, ++ 0x2a, 0xc4, 0x77, 0xcf, 0x18, 0x1d, 0xca, 0x8a, 0xc3, 0x5a, 0x42, 0x06, ++ 0xfc, 0xd6, 0x9b, 0x3a, 0x3d, 0x67, 0x6c, 0x11, 0xd1, 0xd5, 0x78, 0x41, ++ 0x6b, 0x73, 0x4d, 0xde, 0x6f, 0xee, 0xe1, 0x3c, 0x3f, 0xa3, 0xf7, 0xec, ++ 0x4f, 0x1f, 0x5b, 0xef, 0x01, 0xbf, 0x97, 0x14, 0xf1, 0x7d, 0x3b, 0x76, ++ 0xb8, 0x2c, 0x07, 0xe1, 0x65, 0x51, 0x7b, 0xff, 0x22, 0x95, 0xc5, 0x3c, ++ 0x79, 0x29, 0x3c, 0xef, 0x5c, 0x07, 0x2f, 0xdc, 0x29, 0xfc, 0xee, 0x3a, ++ 0x5c, 0xb6, 0x15, 0xf1, 0x76, 0xac, 0x4f, 0x0d, 0x0b, 0x52, 0xb6, 0x8d, ++ 0x0f, 0xe3, 0xf6, 0x36, 0xc0, 0xfb, 0x33, 0x55, 0x72, 0x58, 0x31, 0x90, ++ 0xcf, 0x8a, 0x38, 0xfc, 0x15, 0xba, 0x5f, 0xf7, 0xa5, 0xc6, 0xd9, 0xb9, ++ 0x0e, 0xda, 0x5f, 0x96, 0x82, 0xa3, 0x51, 0x99, 0xda, 0x4f, 0xf8, 0x30, ++ 0x19, 0xf1, 0xe3, 0xdc, 0x1a, 0x68, 0x5f, 0x95, 0x6a, 0xff, 0x04, 0xb6, ++ 0x07, 0x38, 0xf6, 0x20, 0x3c, 0xd4, 0x6f, 0xcd, 0x51, 0x2f, 0xce, 0x13, ++ 0x61, 0x34, 0xcf, 0x48, 0xf4, 0xf0, 0xc2, 0x3a, 0x9d, 0xfa, 0x0d, 0x8a, ++ 0x75, 0x5c, 0xf3, 0xbf, 0xc3, 0xb4, 0x4f, 0x73, 0x1b, 0x5a, 0x24, 0x3e, ++ 0xaf, 0x80, 0xaf, 0xc1, 0x0e, 0x9f, 0x55, 0x5a, 0xf0, 0x8d, 0x34, 0xfe, ++ 0x31, 0x01, 0x97, 0x35, 0xbe, 0x35, 0xdf, 0x13, 0xeb, 0x42, 0x54, 0x36, ++ 0x2a, 0x55, 0x8f, 0xdc, 0x8b, 0xeb, 0x3a, 0xa2, 0xf1, 0x75, 0xcd, 0x37, ++ 0x1e, 0xdf, 0x8d, 0xf8, 0x3b, 0xe2, 0x09, 0xc7, 0xa0, 0xfe, 0xe4, 0x75, ++ 0x7f, 0x33, 0xe6, 0x5e, 0x18, 0xe2, 0x8a, 0xe9, 0xcf, 0x5f, 0xfe, 0x0c, ++ 0xc3, 0xf9, 0x96, 0x3f, 0x7c, 0x3b, 0xae, 0xeb, 0xb9, 0x2c, 0x5a, 0xd7, ++ 0x53, 0x1f, 0x9e, 0x79, 0xed, 0x46, 0x36, 0x7c, 0xde, 0xb7, 0x04, 0x1e, ++ 0x7e, 0x7a, 0x6e, 0xfe, 0x10, 0xd5, 0xad, 0xf9, 0xe7, 0x9a, 0xd2, 0x18, ++ 0x09, 0xe8, 0xac, 0xd2, 0x94, 0x12, 0x2e, 0xa0, 0x97, 0x63, 0xf5, 0x5f, ++ 0x79, 0xf8, 0x5e, 0x03, 0xeb, 0xfd, 0x26, 0xca, 0x93, 0x4a, 0xf3, 0x98, ++ 0x29, 0x41, 0x39, 0x11, 0x86, 0xa1, 0xfd, 0x66, 0xea, 0x9f, 0x3e, 0x06, ++ 0x79, 0x56, 0x09, 0xdd, 0x91, 0x1f, 0x27, 0x35, 0x48, 0x2d, 0xd8, 0xee, ++ 0x89, 0x1b, 0x1f, 0xfa, 0xd2, 0x7d, 0xf0, 0xe8, 0xa7, 0x2e, 0x0e, 0xf7, ++ 0x15, 0x7f, 0xc9, 0xe1, 0xbe, 0xec, 0xfa, 0xb5, 0x4f, 0x22, 0xbc, 0x97, ++ 0xdd, 0xb8, 0xf6, 0xe7, 0xcf, 0x40, 0xfd, 0x0a, 0x14, 0x82, 0xc0, 0x77, ++ 0x97, 0xde, 0xb4, 0x7f, 0xcd, 0xdf, 0xc1, 0x3f, 0xbf, 0xb1, 0xf0, 0x2f, ++ 0x97, 0xef, 0x61, 0x24, 0x17, 0x62, 0xd9, 0x00, 0x47, 0xae, 0x29, 0x31, ++ 0xdc, 0xdf, 0x65, 0xdf, 0x77, 0xdb, 0xe4, 0xca, 0xb1, 0xe7, 0xfd, 0x24, ++ 0x57, 0x0a, 0xcd, 0xd2, 0x18, 0xf2, 0xdf, 0xb2, 0x3e, 0x89, 0xe4, 0x73, ++ 0x7f, 0xa3, 0x9b, 0x05, 0xf1, 0xfd, 0xcf, 0xdc, 0x71, 0x37, 0xf2, 0xd7, ++ 0x03, 0x92, 0x49, 0xed, 0x9f, 0x75, 0xc7, 0x51, 0x3e, 0x1c, 0x73, 0x31, ++ 0x86, 0xf2, 0x78, 0xd9, 0x71, 0x6f, 0x1c, 0xf9, 0x85, 0xad, 0x5a, 0x46, ++ 0xf2, 0x3a, 0x62, 0xc9, 0x6b, 0x33, 0x7f, 0xe9, 0xbd, 0x30, 0xde, 0xbb, ++ 0x0d, 0x96, 0x3c, 0xe7, 0x74, 0x4a, 0xef, 0x61, 0x7d, 0xef, 0x9a, 0xbf, ++ 0xd8, 0x7e, 0x35, 0xf4, 0x3f, 0x63, 0xba, 0xc2, 0x28, 0x36, 0x2d, 0x79, ++ 0xe1, 0xc4, 0xf3, 0xbb, 0x02, 0xbf, 0x91, 0xfa, 0x72, 0xa2, 0x83, 0x65, ++ 0x6a, 0xd2, 0x15, 0xce, 0x40, 0x0f, 0xcd, 0x6d, 0x8a, 0x4d, 0x6e, 0xd7, ++ 0x37, 0x9c, 0x24, 0xba, 0x5a, 0x06, 0x25, 0x4b, 0xe3, 0xd3, 0xb9, 0x82, ++ 0xcf, 0x96, 0x35, 0xfc, 0x42, 0xf0, 0xa7, 0x4e, 0x72, 0xc9, 0x09, 0xcf, ++ 0x1b, 0xb5, 0x85, 0xc5, 0x99, 0xe8, 0xee, 0x94, 0x80, 0x27, 0x29, 0xe8, ++ 0xed, 0x5d, 0xdc, 0xef, 0xcb, 0x10, 0x3e, 0xe8, 0x85, 0x74, 0xd3, 0xa5, ++ 0xc4, 0x95, 0x34, 0x39, 0x0d, 0x7f, 0xae, 0xc8, 0x04, 0xaa, 0xc7, 0x90, ++ 0xa5, 0x6f, 0xd9, 0x62, 0x87, 0xd3, 0x92, 0xdb, 0x2d, 0xb1, 0x6c, 0x9b, ++ 0xbe, 0x02, 0xf9, 0xfb, 0x2f, 0x28, 0x37, 0x9b, 0xdb, 0xf2, 0x6d, 0xcf, ++ 0xe7, 0xe6, 0xb0, 0xda, 0xa9, 0x9f, 0x4e, 0x0e, 0xff, 0x81, 0xe4, 0x70, ++ 0x52, 0x22, 0x78, 0x40, 0xff, 0xd2, 0xfe, 0x47, 0xe2, 0x52, 0x1c, 0xe5, ++ 0xa2, 0xb5, 0x3f, 0x77, 0x88, 0xfd, 0x89, 0x54, 0x30, 0x5a, 0xcf, 0xaf, ++ 0x0e, 0x48, 0xf1, 0x18, 0xec, 0xef, 0xaf, 0x8e, 0x88, 0xf5, 0xed, 0x93, ++ 0xe2, 0x8a, 0x44, 0xf4, 0x6a, 0x9e, 0xf6, 0xe0, 0xb8, 0x30, 0x67, 0x79, ++ 0x6a, 0xff, 0x6f, 0x17, 0xfb, 0x9f, 0xda, 0x3f, 0x8e, 0x1f, 0x0b, 0x5f, ++ 0x29, 0x3d, 0x97, 0xbb, 0x29, 0x09, 0x20, 0xb4, 0xf8, 0x22, 0x25, 0x28, ++ 0xaf, 0x2d, 0xfe, 0xb1, 0xf0, 0xdb, 0xbf, 0xe7, 0x47, 0x25, 0xb8, 0x7f, ++ 0x85, 0x6d, 0xa5, 0xdd, 0x75, 0x08, 0xe7, 0x01, 0x85, 0xf8, 0xf7, 0xc3, ++ 0xfa, 0x93, 0xc5, 0xb8, 0x6f, 0xef, 0xba, 0x00, 0xaf, 0xd0, 0x3f, 0x72, ++ 0xf8, 0xb1, 0x00, 0xf3, 0xa5, 0xe0, 0x6f, 0x11, 0x72, 0xf0, 0x83, 0x0e, ++ 0xa0, 0x17, 0x78, 0x2e, 0x21, 0x9c, 0x95, 0x69, 0x70, 0x0a, 0xb8, 0x5d, ++ 0x58, 0x87, 0x76, 0xb7, 0x37, 0x48, 0x7d, 0xc8, 0xa7, 0xbf, 0x14, 0xf3, ++ 0x5a, 0xfd, 0x7e, 0xb4, 0x65, 0xc6, 0x4c, 0xc4, 0xcf, 0x1d, 0x3d, 0x12, ++ 0x43, 0xfc, 0xdc, 0x7e, 0xa4, 0x77, 0xd9, 0x9f, 0xc3, 0xfa, 0x57, 0xc7, ++ 0xb3, 0xc3, 0x38, 0xc5, 0xaf, 0x1a, 0x8b, 0x03, 0x97, 0x00, 0x3c, 0x2b, ++ 0x7a, 0xec, 0xfb, 0x79, 0x6a, 0xcb, 0xcd, 0x01, 0xa4, 0x9b, 0x0f, 0xfb, ++ 0xf2, 0x0b, 0x70, 0x9c, 0xdb, 0xa7, 0x26, 0x34, 0x84, 0x73, 0x75, 0xe2, ++ 0x55, 0xcd, 0x00, 0x3a, 0x9b, 0x65, 0xf6, 0x6a, 0xc9, 0x0c, 0x74, 0xf5, ++ 0x61, 0xdf, 0x86, 0x00, 0xb6, 0xff, 0x50, 0xed, 0xb9, 0xf1, 0x1a, 0x9c, ++ 0x67, 0x9f, 0x12, 0x5e, 0x0f, 0xe3, 0xaf, 0x3e, 0x52, 0x3a, 0xd3, 0xe4, ++ 0x74, 0x4a, 0xf4, 0xbb, 0x5a, 0xe0, 0xf7, 0xa4, 0xda, 0x33, 0x73, 0x0c, ++ 0xc0, 0xd7, 0xf2, 0x8d, 0x72, 0x92, 0x07, 0xef, 0xf5, 0x29, 0xb3, 0xe3, ++ 0x19, 0xe4, 0xe7, 0xd7, 0x25, 0x85, 0xe8, 0x60, 0x75, 0x9b, 0x5b, 0xc6, ++ 0x75, 0x8e, 0x44, 0x2f, 0x1f, 0x76, 0xb8, 0x58, 0x02, 0xe7, 0x51, 0x13, ++ 0x84, 0xcf, 0x91, 0xda, 0x7d, 0xd0, 0xd7, 0x42, 0xef, 0xfb, 0x1f, 0x28, ++ 0xbc, 0x01, 0xed, 0xb7, 0xdb, 0xdb, 0x5d, 0x24, 0x2f, 0x6e, 0x6f, 0x73, ++ 0x13, 0x3d, 0xad, 0x6e, 0x90, 0xe2, 0x4c, 0x4a, 0xf1, 0xdb, 0x0a, 0x01, ++ 0xef, 0xea, 0xdd, 0x0a, 0xbd, 0x3f, 0x69, 0x4a, 0x24, 0x3f, 0xac, 0xfd, ++ 0xba, 0x5d, 0xd0, 0xdb, 0xc9, 0xc3, 0x57, 0xbd, 0x82, 0xfa, 0xfe, 0x0c, ++ 0xc8, 0x1f, 0x94, 0xbb, 0x33, 0x36, 0xfe, 0x50, 0xbb, 0x04, 0xf0, 0xb0, ++ 0x62, 0x0b, 0x97, 0x47, 0x27, 0x77, 0xe7, 0x2e, 0xbd, 0x07, 0xe5, 0x88, ++ 0xd0, 0x97, 0x77, 0x88, 0x71, 0x6f, 0x8b, 0x2b, 0x36, 0xfe, 0x58, 0xd9, ++ 0x9e, 0x6d, 0xdb, 0x8f, 0x68, 0x57, 0xbe, 0xad, 0x7e, 0xfa, 0x48, 0xfe, ++ 0x8d, 0x75, 0x48, 0xd7, 0x5d, 0x0a, 0xe9, 0xcf, 0x5b, 0x36, 0x3e, 0xa6, ++ 0x85, 0x48, 0x3e, 0xd9, 0xed, 0x4d, 0xe4, 0xb0, 0x49, 0x05, 0x29, 0xfb, ++ 0xf2, 0x04, 0x1b, 0x5a, 0x70, 0x8d, 0x94, 0xa2, 0x27, 0x8b, 0x7e, 0x6e, ++ 0x6d, 0x03, 0x7b, 0x33, 0x30, 0xdc, 0xde, 0x6c, 0x39, 0x22, 0x91, 0x3d, ++ 0x7a, 0xd1, 0x76, 0x66, 0x1b, 0xd8, 0x99, 0x13, 0x87, 0xdb, 0x99, 0x96, ++ 0x1c, 0x89, 0xa0, 0x7d, 0x56, 0x9e, 0x92, 0x23, 0x96, 0xdc, 0xb8, 0x4b, ++ 0x89, 0x8e, 0x0d, 0x02, 0x1c, 0xbf, 0x76, 0x45, 0x2f, 0xcb, 0x2f, 0x27, ++ 0xb9, 0xf1, 0x80, 0x54, 0x8b, 0x74, 0xa2, 0xff, 0x16, 0xed, 0x4a, 0x16, ++ 0x53, 0x6a, 0x51, 0xbe, 0x5d, 0xac, 0xbc, 0xa0, 0xc5, 0x5a, 0x7c, 0x04, ++ 0x7f, 0xef, 0x75, 0x00, 0x5d, 0x65, 0xa0, 0xd7, 0x19, 0x48, 0x57, 0x30, ++ 0xcf, 0xcc, 0x9e, 0xfe, 0x8c, 0xf4, 0x3c, 0x43, 0x32, 0x68, 0xbc, 0x14, ++ 0xdd, 0xdc, 0x12, 0x20, 0xbe, 0xc5, 0x41, 0x01, 0x8e, 0x66, 0x8f, 0xd9, ++ 0x85, 0x70, 0x5e, 0x02, 0x13, 0x7b, 0xab, 0xa9, 0x64, 0x4a, 0x1e, 0x2f, ++ 0x55, 0xa8, 0x6f, 0x46, 0x98, 0x81, 0x1e, 0x4e, 0xad, 0x95, 0xe2, 0x87, ++ 0x4a, 0x79, 0x3b, 0x1f, 0xca, 0x53, 0x80, 0xeb, 0x1a, 0x78, 0xde, 0xdc, ++ 0x75, 0x79, 0x7c, 0x9b, 0x84, 0x76, 0x21, 0xfc, 0xa1, 0xfe, 0x6c, 0xe3, ++ 0x76, 0x37, 0xb4, 0x33, 0xfd, 0x79, 0xf4, 0xdc, 0x94, 0xa0, 0x2c, 0x6a, ++ 0x2f, 0x7d, 0x19, 0xf7, 0xe7, 0x12, 0x10, 0x00, 0x5a, 0x35, 0x6f, 0x8f, ++ 0xf3, 0x80, 0x9d, 0x45, 0x28, 0x81, 0xf6, 0x09, 0x77, 0x35, 0x75, 0x8d, ++ 0x05, 0xa0, 0x2c, 0x86, 0x7e, 0x32, 0xef, 0x4f, 0xef, 0xb1, 0x5d, 0x80, ++ 0xe4, 0x78, 0x9c, 0xd6, 0x8b, 0xe3, 0xe3, 0x38, 0x15, 0x4a, 0x7c, 0x0d, ++ 0xca, 0x19, 0x8b, 0x8e, 0x97, 0x09, 0xb9, 0x03, 0x72, 0xb5, 0x52, 0x05, ++ 0xfa, 0x6a, 0x66, 0x59, 0x61, 0xd4, 0x9b, 0xcd, 0x6d, 0xe5, 0xe7, 0xb5, ++ 0x5f, 0x6e, 0x08, 0xdb, 0xe5, 0xc7, 0x4d, 0x75, 0x76, 0x3d, 0x30, 0xd7, ++ 0xb4, 0xcb, 0xff, 0x9b, 0x67, 0x5f, 0x62, 0x6b, 0xbf, 0x20, 0x52, 0x6e, ++ 0x7b, 0xff, 0x67, 0x8b, 0xae, 0xb0, 0xbd, 0x5f, 0x1c, 0xbd, 0xca, 0x56, ++ 0xff, 0xf2, 0xaa, 0x2f, 0xd8, 0xda, 0x2f, 0x6d, 0x9d, 0x61, 0xf7, 0x93, ++ 0x7e, 0x9a, 0x4b, 0xeb, 0x59, 0x23, 0xf8, 0x72, 0x24, 0xb8, 0x5f, 0x17, ++ 0xf2, 0xf2, 0x27, 0x0e, 0xfb, 0xd4, 0x2a, 0x9b, 0xae, 0x4f, 0xd4, 0xbc, ++ 0x0d, 0xfb, 0xc4, 0xd6, 0xb9, 0xc3, 0x8f, 0x43, 0x71, 0x62, 0x0e, 0x5b, ++ 0xd4, 0x97, 0x26, 0x57, 0x7c, 0xb2, 0x44, 0xf8, 0xfc, 0x0d, 0xb0, 0x09, ++ 0xf7, 0x0f, 0xfe, 0xf4, 0x31, 0xe1, 0x31, 0xc4, 0xe7, 0x6d, 0xfa, 0x0b, ++ 0x77, 0x6b, 0x26, 0xba, 0xd3, 0x44, 0x3f, 0x34, 0x97, 0xd0, 0x5e, 0x72, ++ 0xb6, 0x3f, 0xb1, 0x18, 0xe6, 0x49, 0xeb, 0xf7, 0x6f, 0x92, 0x44, 0x74, ++ 0x78, 0xae, 0x1f, 0xf3, 0xf4, 0xfc, 0x12, 0x40, 0x6e, 0x01, 0x4e, 0xce, ++ 0x01, 0xd4, 0xdf, 0xc9, 0x92, 0x25, 0xb8, 0x6f, 0xee, 0x5c, 0x83, 0xde, ++ 0xdf, 0x25, 0x27, 0x0b, 0xb0, 0xfe, 0x1b, 0x36, 0xb4, 0x37, 0x1f, 0xf7, ++ 0xd7, 0x97, 0x2c, 0x46, 0xfe, 0x69, 0x56, 0xd9, 0x73, 0x52, 0x0e, 0xf6, ++ 0x0b, 0x7b, 0xdc, 0x30, 0x1f, 0x58, 0x43, 0xac, 0x0d, 0xe8, 0xa3, 0xa5, ++ 0xed, 0x47, 0xc7, 0xd1, 0x8e, 0x93, 0x8c, 0x20, 0x5b, 0x82, 0x75, 0x8f, ++ 0x2f, 0x81, 0xfc, 0xcd, 0x3a, 0x5c, 0x1f, 0x26, 0x2d, 0xbc, 0x03, 0x1f, ++ 0xf6, 0x86, 0xa2, 0x1f, 0x4a, 0x00, 0x87, 0xd4, 0xde, 0xff, 0x7b, 0x09, ++ 0xdf, 0x7f, 0x9f, 0x19, 0xa8, 0x87, 0x59, 0xb2, 0x28, 0x17, 0xfd, 0x47, ++ 0x9c, 0x2a, 0x9d, 0x0f, 0x9b, 0x66, 0xb0, 0x56, 0xc4, 0xd7, 0x89, 0x46, ++ 0x3b, 0xde, 0xbc, 0x62, 0x1d, 0x3f, 0x97, 0x64, 0x6a, 0xf7, 0x1c, 0x33, ++ 0x7f, 0x8b, 0x7c, 0x74, 0x52, 0xd2, 0xf9, 0xfa, 0x04, 0xbc, 0xdb, 0x24, ++ 0xf3, 0x2c, 0xce, 0x67, 0xc1, 0xfd, 0x6e, 0xae, 0xae, 0xb1, 0x4f, 0x07, ++ 0xb7, 0x22, 0xd7, 0x22, 0xdc, 0x3f, 0x22, 0xb8, 0x37, 0xb4, 0xb2, 0x64, ++ 0xb6, 0x32, 0x32, 0xdc, 0x57, 0x30, 0xd3, 0x2d, 0x8f, 0x1a, 0x0e, 0xcf, ++ 0x59, 0x66, 0x66, 0x65, 0x7a, 0x3e, 0x0b, 0xd8, 0x35, 0xd3, 0xf3, 0xcb, ++ 0xdd, 0xac, 0x12, 0xed, 0xd5, 0x13, 0x52, 0x56, 0x78, 0x7d, 0x29, 0x96, ++ 0x43, 0xff, 0xf8, 0x35, 0xe0, 0xab, 0xd8, 0x37, 0x7c, 0xe1, 0xc7, 0x8d, ++ 0xe1, 0x74, 0x31, 0x55, 0xce, 0xa5, 0xf9, 0x9b, 0x85, 0xbd, 0x5b, 0xd8, ++ 0x2e, 0x25, 0xb2, 0xd1, 0x3e, 0x65, 0x1e, 0xb2, 0x5f, 0x59, 0xcf, 0x43, ++ 0xa6, 0x07, 0xe5, 0x9a, 0x10, 0x71, 0x2d, 0x6d, 0xd2, 0x49, 0x5c, 0x3f, ++ 0xeb, 0x68, 0x34, 0x93, 0x9e, 0xd4, 0x7a, 0x99, 0x21, 0xb1, 0xf4, 0x76, ++ 0xe7, 0xf6, 0xbd, 0xcd, 0x4d, 0xed, 0x2d, 0x79, 0x63, 0xc9, 0x2d, 0x0b, ++ 0x9f, 0x96, 0x5c, 0xb1, 0xe4, 0x97, 0x85, 0x57, 0xe7, 0xf8, 0x23, 0xc9, ++ 0x19, 0x1c, 0x4f, 0xcd, 0x43, 0xf8, 0xa3, 0x93, 0xe4, 0x74, 0x3a, 0xd1, ++ 0x01, 0x1f, 0x13, 0x10, 0x1e, 0xb3, 0x1a, 0xf7, 0xcf, 0xda, 0x37, 0x70, ++ 0x23, 0x63, 0x9e, 0xea, 0x91, 0xf7, 0xcd, 0x92, 0x53, 0xd0, 0x8e, 0xa1, ++ 0xff, 0x3f, 0xd2, 0x7e, 0x01, 0x9e, 0xc8, 0xae, 0x73, 0x85, 0x19, 0xe1, ++ 0xe9, 0xdd, 0xe0, 0xd0, 0xd2, 0xa7, 0x60, 0xdd, 0x03, 0x6d, 0x5c, 0x5f, ++ 0xbf, 0x5b, 0xc4, 0xc8, 0x3e, 0x3c, 0xd3, 0x76, 0xd5, 0x40, 0x0e, 0xe2, ++ 0xc7, 0xe3, 0xa9, 0x40, 0xfc, 0x14, 0xf2, 0xa9, 0x58, 0x61, 0x70, 0x68, ++ 0x1d, 0xca, 0x57, 0x9f, 0x9a, 0xe8, 0x47, 0xb8, 0x0a, 0x85, 0xfe, 0xf2, ++ 0x32, 0xae, 0xbf, 0x0a, 0x99, 0xb1, 0xe3, 0x6a, 0xf4, 0xef, 0xdb, 0x4f, ++ 0x2e, 0xc1, 0x76, 0xd6, 0xfe, 0xe4, 0x8a, 0xfd, 0x69, 0x86, 0xfd, 0x41, ++ 0x7f, 0xa4, 0xd9, 0x37, 0x54, 0x8c, 0x76, 0x92, 0x1b, 0xf5, 0x1a, 0xb4, ++ 0x73, 0x83, 0xdc, 0x45, 0xb9, 0x5c, 0xd8, 0xfe, 0xfe, 0x7f, 0xa0, 0x5e, ++ 0x2c, 0x74, 0xe8, 0x45, 0x84, 0x84, 0xa5, 0xc3, 0x91, 0x55, 0xb5, 0xe3, ++ 0x6a, 0x23, 0x7d, 0xfc, 0x8f, 0x36, 0xa2, 0x7d, 0x69, 0x8d, 0x4b, 0x1d, ++ 0xd2, 0xf7, 0x3f, 0xa8, 0x9d, 0x44, 0xfc, 0x16, 0xb6, 0x6f, 0xbe, 0x5b, ++ 0x09, 0xd8, 0xc6, 0x97, 0x3e, 0x46, 0x3c, 0x08, 0xb9, 0x8d, 0x66, 0xd7, ++ 0xb9, 0x79, 0x4a, 0xd1, 0x5e, 0x95, 0x13, 0xee, 0x40, 0x8a, 0x2e, 0x9c, ++ 0x70, 0x59, 0xfd, 0x46, 0xa2, 0x13, 0x96, 0x3e, 0x4f, 0xb9, 0xad, 0x4e, ++ 0xf6, 0x84, 0xb3, 0xee, 0x0e, 0x6b, 0x36, 0xf9, 0xfc, 0xee, 0x1f, 0xcb, ++ 0x73, 0x5a, 0x7d, 0xe7, 0xa1, 0x37, 0xe7, 0x78, 0x4e, 0xfa, 0x76, 0xf2, ++ 0x81, 0xc0, 0xc3, 0xa7, 0xa0, 0xd3, 0x4d, 0x9c, 0x4e, 0xb9, 0x5c, 0xb0, ++ 0xf8, 0xf6, 0x3f, 0x8b, 0x4e, 0xa3, 0xd6, 0xbe, 0xc6, 0x72, 0xef, 0x38, ++ 0x82, 0xfa, 0xb5, 0x4b, 0x0b, 0xcf, 0x32, 0xd0, 0x4e, 0x18, 0xfa, 0x21, ++ 0xb7, 0x13, 0xdc, 0xc6, 0x21, 0xa4, 0xb3, 0x98, 0x94, 0x55, 0x09, 0xef, ++ 0xa3, 0x1d, 0x2a, 0xd9, 0x8d, 0x96, 0x5d, 0xd1, 0xbf, 0xf6, 0xaf, 0xb7, ++ 0x94, 0xc1, 0xf3, 0x13, 0xb5, 0x32, 0xf9, 0x11, 0x27, 0xd6, 0x73, 0xba, ++ 0xdf, 0xf3, 0x00, 0xb7, 0x47, 0x2d, 0xbd, 0x1d, 0x15, 0x7a, 0x1b, 0xed, ++ 0x02, 0xc4, 0x2b, 0xd8, 0x0d, 0x03, 0x6e, 0x5e, 0x7a, 0x70, 0x1c, 0xff, ++ 0xfa, 0x9b, 0x4b, 0x25, 0x80, 0xdb, 0x63, 0x0c, 0xf5, 0xbb, 0xb1, 0x7d, ++ 0x9b, 0x41, 0xf6, 0x6a, 0x4e, 0x5d, 0x5c, 0x6f, 0x84, 0x32, 0x5e, 0x71, ++ 0xc8, 0x33, 0xce, 0x48, 0xc9, 0xa5, 0x64, 0x2c, 0x3f, 0x6f, 0x39, 0xec, ++ 0xd7, 0xb7, 0x72, 0x8d, 0x65, 0x11, 0xb2, 0xaf, 0xa3, 0xa3, 0xe7, 0xfa, ++ 0x53, 0xef, 0x7f, 0x2c, 0x73, 0xfd, 0x34, 0xad, 0x84, 0xe5, 0xcd, 0x86, ++ 0xf1, 0x92, 0x5b, 0xe5, 0xf0, 0x83, 0xd0, 0x3f, 0xe9, 0xb2, 0xeb, 0x31, ++ 0xab, 0x5c, 0xa3, 0x70, 0x7d, 0x99, 0xf4, 0xb2, 0x12, 0xf4, 0x83, 0x47, ++ 0x6a, 0x37, 0xa4, 0x58, 0x7a, 0x55, 0xd7, 0x68, 0x5f, 0xe6, 0x0f, 0x1c, ++ 0xc7, 0x7d, 0x1a, 0x69, 0x1f, 0x60, 0x07, 0x74, 0x8a, 0x63, 0x9e, 0xa3, ++ 0x43, 0x8e, 0x77, 0x98, 0x87, 0xc6, 0x4f, 0xfa, 0xed, 0x7a, 0xe8, 0xa4, ++ 0xd0, 0x43, 0x16, 0xfc, 0x9f, 0x40, 0xaf, 0x2e, 0x2c, 0x06, 0xfa, 0xd8, ++ 0x2b, 0x65, 0x86, 0xfb, 0x23, 0x31, 0x5e, 0xf4, 0x39, 0x00, 0x00, 0xf6, ++ 0x3b, 0xaa, 0x32, 0x33, 0x53, 0x3b, 0xe7, 0xba, 0xff, 0x41, 0xf4, 0x4b, ++ 0xc8, 0x2a, 0xcd, 0xb7, 0xa3, 0x62, 0xe7, 0x6c, 0xdc, 0xef, 0x58, 0x4c, ++ 0x09, 0xa7, 0xef, 0x87, 0x55, 0xfe, 0x85, 0xc2, 0xf5, 0x67, 0xce, 0xdc, ++ 0x86, 0xdc, 0x46, 0x68, 0xc7, 0xd6, 0x67, 0x6e, 0x97, 0x27, 0xda, 0x3d, ++ 0x76, 0x5f, 0xd6, 0x22, 0xf4, 0xaf, 0x00, 0x75, 0x2a, 0xc6, 0x6b, 0x42, ++ 0x31, 0x7d, 0xde, 0x6c, 0x8c, 0x47, 0x4e, 0xcd, 0x9b, 0x84, 0x3e, 0xf6, ++ 0x8f, 0x51, 0xff, 0xc0, 0xbc, 0xbb, 0x23, 0x67, 0xf4, 0x16, 0xdf, 0x27, ++ 0xc2, 0x47, 0x41, 0x48, 0x19, 0x19, 0x1f, 0x6f, 0xca, 0x32, 0xdf, 0x47, ++ 0x07, 0xdf, 0xee, 0x01, 0x77, 0x0d, 0xe5, 0x67, 0x52, 0xf2, 0x50, 0xfc, ++ 0xa5, 0x25, 0xe6, 0xce, 0xc8, 0xc7, 0x96, 0x9c, 0x72, 0xca, 0x23, 0xa7, ++ 0x9e, 0x93, 0x4c, 0x93, 0xb5, 0x55, 0x0f, 0x97, 0x2b, 0xd6, 0xb8, 0x9f, ++ 0x54, 0x9f, 0x81, 0x7c, 0xc8, 0x52, 0x46, 0xa5, 0xec, 0xf6, 0x73, 0xfa, ++ 0xec, 0x62, 0xe9, 0x71, 0x04, 0x39, 0x50, 0x22, 0xb3, 0x68, 0x5f, 0x06, ++ 0xff, 0xf4, 0x6a, 0x85, 0xe3, 0xa9, 0x3f, 0xc6, 0xe3, 0x14, 0xaa, 0x29, ++ 0x93, 0xde, 0x9a, 0xa9, 0x34, 0x31, 0x09, 0xf0, 0xb4, 0x21, 0xc8, 0x48, ++ 0x1e, 0xe4, 0xe1, 0x5e, 0x23, 0xdf, 0x36, 0xb0, 0x38, 0xa0, 0x80, 0xe5, ++ 0xb3, 0xf0, 0x80, 0x0f, 0xe5, 0x49, 0x50, 0x66, 0x09, 0xf2, 0x5b, 0x9d, ++ 0x7e, 0xa0, 0xd9, 0x84, 0x7e, 0x60, 0x90, 0x83, 0xc6, 0xf4, 0x51, 0x65, ++ 0xfd, 0x85, 0xf0, 0x3c, 0x38, 0x7f, 0x25, 0x9d, 0x33, 0xb0, 0x08, 0x97, ++ 0xb7, 0x3a, 0xfc, 0xc7, 0xf9, 0xc8, 0x24, 0x7d, 0xe1, 0x16, 0x78, 0x8d, ++ 0xc6, 0x26, 0x51, 0x9c, 0x33, 0xaf, 0xc9, 0x2e, 0xc7, 0xdd, 0xe8, 0x07, ++ 0x82, 0x7c, 0xd4, 0x1b, 0x1c, 0xcf, 0xe7, 0xcf, 0xa4, 0xf3, 0x06, 0x37, ++ 0x4b, 0x7b, 0x0e, 0xeb, 0xb8, 0x4a, 0xf1, 0x07, 0x4f, 0x83, 0x69, 0xcf, ++ 0xaa, 0x59, 0x0d, 0xf2, 0x67, 0xf5, 0xfe, 0xab, 0x76, 0x2d, 0x86, 0xf1, ++ 0x6b, 0x1e, 0xb9, 0xf9, 0x6d, 0x2c, 0x27, 0x1f, 0xbc, 0x27, 0xff, 0x4b, ++ 0x50, 0xd6, 0x3d, 0xbe, 0xeb, 0x66, 0x2c, 0x4b, 0x5e, 0x8b, 0x8e, 0xcd, ++ 0x14, 0x4f, 0xb5, 0x4a, 0xe0, 0x14, 0x26, 0xd7, 0x01, 0x7c, 0x3e, 0x66, ++ 0xb8, 0x73, 0x46, 0x6e, 0x67, 0xac, 0x57, 0x22, 0x68, 0x57, 0xc3, 0x3e, ++ 0x76, 0x20, 0x3d, 0x24, 0x63, 0xe5, 0x59, 0x48, 0xdf, 0xab, 0x14, 0xce, ++ 0xff, 0xfd, 0x0b, 0xb4, 0x00, 0xc6, 0x67, 0xd4, 0x2d, 0x5c, 0xae, 0xaa, ++ 0xf3, 0x01, 0x79, 0x44, 0xff, 0xdc, 0x4f, 0x6f, 0x4e, 0xf9, 0xd3, 0xe4, ++ 0x57, 0xa8, 0xc2, 0x4f, 0x52, 0xda, 0x15, 0x8a, 0x23, 0x24, 0xf5, 0x32, ++ 0x8a, 0xb7, 0x1c, 0xda, 0x22, 0x6b, 0x58, 0x82, 0x9c, 0x8d, 0xe1, 0x3c, ++ 0xd6, 0xfc, 0xbd, 0x22, 0x4e, 0xdd, 0x29, 0xe2, 0xad, 0x4e, 0xf8, 0x7a, ++ 0x4b, 0x86, 0x8a, 0x51, 0x0e, 0x9e, 0x58, 0xff, 0x11, 0xd9, 0x87, 0x8a, ++ 0x9e, 0x15, 0x9e, 0x0d, 0xf3, 0x75, 0xf9, 0x59, 0x09, 0xc1, 0x21, 0xe2, ++ 0x05, 0xcd, 0x62, 0xff, 0x92, 0x6b, 0xeb, 0x3d, 0xe9, 0xf1, 0x22, 0x45, ++ 0xf8, 0x39, 0x1d, 0x47, 0xe7, 0x0c, 0x18, 0x48, 0x07, 0x03, 0x4a, 0xd8, ++ 0x6b, 0x10, 0xdf, 0x68, 0x38, 0x6e, 0x74, 0xcb, 0x74, 0x86, 0xf1, 0x97, ++ 0x59, 0x7a, 0x98, 0xa1, 0x3d, 0xd1, 0x29, 0xfc, 0x1e, 0xc5, 0x67, 0x32, ++ 0xdc, 0xd7, 0x6c, 0x9d, 0xcd, 0x44, 0xbf, 0x16, 0x5e, 0x69, 0x21, 0xec, ++ 0x5f, 0xc5, 0xc2, 0x09, 0xec, 0xdf, 0xde, 0x8f, 0xb8, 0x85, 0xf5, 0x9a, ++ 0xb7, 0x23, 0x1f, 0xfc, 0xe0, 0x5a, 0x6e, 0x87, 0x9c, 0x28, 0xb5, 0xcb, ++ 0x6d, 0x20, 0xa1, 0x2e, 0xd8, 0x53, 0x36, 0xab, 0x68, 0xbd, 0x8a, 0xb4, ++ 0xd9, 0x14, 0x9c, 0x74, 0x15, 0xd2, 0xfc, 0xef, 0x95, 0x02, 0x21, 0x57, ++ 0x39, 0xbd, 0xbe, 0x51, 0x3b, 0xe5, 0xb1, 0x6d, 0x40, 0x07, 0xcf, 0xb9, ++ 0xcd, 0x7b, 0x94, 0x51, 0x9f, 0x80, 0x8f, 0x1c, 0x72, 0xfd, 0x07, 0xc0, ++ 0x26, 0xb8, 0x6f, 0x8f, 0x4a, 0x76, 0x79, 0x6e, 0x95, 0x07, 0x9d, 0x7c, ++ 0xd4, 0x26, 0x91, 0x5d, 0xa8, 0x9a, 0x7c, 0x9d, 0x33, 0x95, 0x0f, 0x1b, ++ 0x51, 0x4f, 0x6e, 0x04, 0xbb, 0xb1, 0xd0, 0x18, 0xce, 0x2f, 0x1b, 0x5f, ++ 0x67, 0x64, 0x37, 0x6e, 0x04, 0xfe, 0x8b, 0x95, 0x66, 0xe2, 0x9f, 0x6a, ++ 0x09, 0x65, 0xc4, 0xc5, 0xf2, 0x4f, 0x5e, 0x7b, 0xae, 0x84, 0x71, 0x8c, ++ 0xcf, 0xca, 0x3f, 0x7f, 0xa9, 0x88, 0x73, 0x3a, 0xc1, 0x3f, 0x40, 0x67, ++ 0x09, 0xb4, 0x63, 0x1e, 0x95, 0x8c, 0xce, 0x29, 0xb0, 0xbe, 0xef, 0xec, ++ 0x6b, 0xfc, 0xf1, 0x14, 0x78, 0xfd, 0xec, 0x81, 0x15, 0xd9, 0xd7, 0x40, ++ 0xf9, 0xbd, 0xf8, 0xc6, 0xeb, 0xaf, 0x81, 0xf9, 0x6f, 0x7f, 0x7c, 0x4f, ++ 0x36, 0xee, 0xf3, 0xa3, 0xaf, 0x02, 0x3f, 0x9d, 0xc7, 0x8f, 0xb7, 0xf8, ++ 0xa9, 0x19, 0x6d, 0xd8, 0xf3, 0xc4, 0xd9, 0x8c, 0xb5, 0x76, 0x7e, 0x32, ++ 0xd6, 0x57, 0x10, 0x3f, 0xbd, 0xa5, 0x70, 0xfd, 0xd5, 0xbf, 0xe0, 0x77, ++ 0x6f, 0x5c, 0xfd, 0xff, 0xf9, 0xe9, 0x7c, 0xfc, 0xf4, 0xb6, 0x02, 0xf4, ++ 0x39, 0xed, 0x4f, 0x67, 0x8b, 0xa3, 0xe7, 0x91, 0x6f, 0xcd, 0x45, 0x4c, ++ 0x43, 0x7b, 0x0b, 0xda, 0x98, 0x48, 0xe7, 0xd1, 0xa0, 0xbd, 0xf4, 0xa9, ++ 0x59, 0x84, 0xef, 0x75, 0x2e, 0x2e, 0xc7, 0xfc, 0x2e, 0x2f, 0xb7, 0x3b, ++ 0x42, 0xfc, 0xbd, 0x73, 0xbc, 0xbf, 0x51, 0x3f, 0x79, 0xfc, 0x60, 0x41, ++ 0xf9, 0x67, 0xe7, 0xd3, 0x75, 0x3e, 0xf3, 0xa3, 0xcf, 0x83, 0xdf, 0x41, ++ 0xee, 0x90, 0xbc, 0x39, 0x31, 0xce, 0xce, 0xf7, 0x9d, 0x2e, 0x4e, 0x77, ++ 0xbf, 0x72, 0x7d, 0xe2, 0xf5, 0xbd, 0xf3, 0x85, 0xcf, 0x61, 0x7d, 0x60, ++ 0xd7, 0x93, 0x7d, 0x77, 0x9d, 0xca, 0x0c, 0xf4, 0x03, 0x26, 0xbe, 0xe0, ++ 0x21, 0x61, 0xf1, 0xea, 0xb8, 0x8d, 0x47, 0x90, 0x25, 0xa6, 0xc1, 0xf3, ++ 0x50, 0x1e, 0x7f, 0xef, 0xce, 0x23, 0x79, 0x19, 0x47, 0x3b, 0x66, 0x48, ++ 0xa9, 0xa4, 0xfe, 0x26, 0xe3, 0x76, 0x7c, 0x53, 0xcd, 0xe6, 0x23, 0xfc, ++ 0x5c, 0x62, 0xb0, 0x62, 0x11, 0xf8, 0xcb, 0x73, 0xe0, 0x5f, 0x68, 0x8f, ++ 0x5c, 0xe7, 0xe3, 0x7e, 0x05, 0x8c, 0xc3, 0x42, 0x30, 0xfe, 0x6a, 0x6f, ++ 0xb4, 0x58, 0x1d, 0x45, 0xe3, 0x91, 0x7f, 0xf9, 0xea, 0xf3, 0xfb, 0x82, ++ 0x28, 0x5f, 0x5e, 0xf7, 0x98, 0x25, 0xf8, 0x9c, 0x25, 0xd5, 0x5c, 0x3c, ++ 0x1f, 0xb0, 0xec, 0x8e, 0x91, 0xf9, 0x5d, 0x65, 0xa7, 0xd3, 0xfc, 0xac, ++ 0xa7, 0x35, 0x46, 0x70, 0x9c, 0xba, 0x54, 0xa3, 0x78, 0x25, 0x8a, 0xb1, ++ 0x00, 0xd4, 0xb7, 0x96, 0x5e, 0x4a, 0x71, 0x4a, 0x16, 0x8e, 0x1d, 0x97, ++ 0xb0, 0x3e, 0x4a, 0x67, 0x28, 0xc7, 0x95, 0x60, 0x64, 0x31, 0xd9, 0x21, ++ 0x6d, 0x6e, 0x63, 0x16, 0xd4, 0xb7, 0x82, 0x01, 0x15, 0x0b, 0x12, 0xdd, ++ 0x92, 0xdc, 0x54, 0xda, 0x7b, 0x43, 0x01, 0x94, 0x03, 0x60, 0x97, 0xe0, ++ 0x7b, 0x35, 0x36, 0xd7, 0xa3, 0xa1, 0xff, 0x32, 0x4a, 0xc6, 0x20, 0x34, ++ 0x73, 0xb7, 0x7d, 0x44, 0x7e, 0xf7, 0x89, 0x62, 0x2e, 0x6f, 0x3b, 0xa6, ++ 0x30, 0x3a, 0xa7, 0x19, 0x78, 0xe0, 0xdf, 0x96, 0xca, 0x68, 0xef, 0xb4, ++ 0xbb, 0xe9, 0xdc, 0x02, 0xec, 0x46, 0xe2, 0xd7, 0xa8, 0x90, 0x1b, 0xc9, ++ 0xe0, 0xf4, 0x50, 0x0b, 0xfa, 0x19, 0x45, 0x5a, 0x58, 0x82, 0xfa, 0xa6, ++ 0xd8, 0x2f, 0x8e, 0x7f, 0x8d, 0xcb, 0x13, 0xd3, 0x33, 0x39, 0x3d, 0x3e, ++ 0xc2, 0xe3, 0x1d, 0x2d, 0x21, 0xee, 0xef, 0x3a, 0xed, 0xbe, 0xcd, 0x5f, ++ 0xbf, 0xec, 0x4d, 0x03, 0xc7, 0xfb, 0xe1, 0x6b, 0x5d, 0x97, 0x43, 0xf9, ++ 0xfa, 0x93, 0x3f, 0x7f, 0xfd, 0x72, 0x78, 0xf7, 0xc6, 0xb7, 0x5e, 0xab, ++ 0xc1, 0xb8, 0xb7, 0xbb, 0x4e, 0xb3, 0xc5, 0x1d, 0xdd, 0xcc, 0x78, 0x13, ++ 0xed, 0x2d, 0xf0, 0x99, 0x12, 0x1a, 0xca, 0xe7, 0xd8, 0xc9, 0x25, 0xb8, ++ 0x99, 0x29, 0xbf, 0x4e, 0x8a, 0x21, 0x7e, 0xa2, 0x35, 0xfe, 0x38, 0xae, ++ 0x17, 0x79, 0x1b, 0xf1, 0x93, 0x9c, 0xa2, 0xf0, 0xf3, 0x45, 0xf8, 0x0b, ++ 0x01, 0x7c, 0x01, 0x01, 0x5f, 0x77, 0xf0, 0x54, 0x15, 0xcd, 0x13, 0x7b, ++ 0xff, 0x3f, 0x32, 0xc9, 0x7b, 0xfa, 0x9b, 0x2c, 0xf4, 0x08, 0xb4, 0xdb, ++ 0x9c, 0x77, 0x7f, 0x1c, 0xe5, 0x48, 0x6a, 0xbe, 0x49, 0x24, 0x9f, 0xa2, ++ 0x20, 0x9f, 0xd0, 0x8f, 0x8c, 0xfa, 0x7a, 0x96, 0xac, 0xa1, 0xf9, 0xfc, ++ 0xe1, 0x07, 0xb1, 0xcf, 0x1f, 0x61, 0x57, 0x27, 0xa7, 0xce, 0x0b, 0x0f, ++ 0x6d, 0x99, 0xd7, 0x82, 0x78, 0x9e, 0xbb, 0xc0, 0xa3, 0x23, 0x9d, 0xb9, ++ 0x63, 0x9b, 0xef, 0x46, 0x3a, 0x77, 0xae, 0xf3, 0x8c, 0xef, 0xc1, 0x4b, ++ 0x31, 0x34, 0x67, 0x9b, 0x1f, 0xf8, 0xc4, 0x5d, 0xa1, 0x99, 0x5e, 0xb2, ++ 0x7f, 0xd9, 0x61, 0xda, 0x0f, 0xd1, 0xc4, 0x82, 0x5b, 0x07, 0x05, 0x82, ++ 0x71, 0x07, 0xe8, 0xbf, 0x6c, 0x05, 0xcb, 0xd0, 0xdf, 0x80, 0xfe, 0xb8, ++ 0x4e, 0x90, 0x67, 0x68, 0x6f, 0x5b, 0xfd, 0x80, 0x8c, 0x4d, 0x5c, 0xef, ++ 0x19, 0xdf, 0xf4, 0x4b, 0x29, 0xde, 0x2f, 0xe2, 0x15, 0x56, 0xbf, 0x9b, ++ 0x62, 0x12, 0x9d, 0x13, 0xdc, 0x54, 0x0e, 0x6c, 0x50, 0x3e, 0x1c, 0x4f, ++ 0x1b, 0x7c, 0xf2, 0x4f, 0xbe, 0x86, 0xe7, 0x2e, 0x31, 0x45, 0x57, 0x38, ++ 0x1d, 0x84, 0x2a, 0xd2, 0xf0, 0x86, 0x7f, 0xf6, 0xb8, 0x19, 0xa7, 0x8b, ++ 0xcb, 0xf6, 0xd9, 0xf5, 0x2e, 0xcc, 0xbf, 0xb0, 0x14, 0xdf, 0xc7, 0x14, ++ 0xa2, 0x17, 0x27, 0xbf, 0x8c, 0x8f, 0xdb, 0xdb, 0x6f, 0xf0, 0x9d, 0xff, ++ 0x5c, 0x7f, 0xf8, 0x7e, 0x72, 0x3c, 0x4f, 0x14, 0xfc, 0x66, 0xf5, 0xb7, ++ 0xe0, 0x23, 0x78, 0xa5, 0x4c, 0xf1, 0x75, 0xfb, 0xb9, 0xcc, 0x4d, 0x75, ++ 0xf6, 0xfa, 0xdc, 0x61, 0xf8, 0x38, 0x3f, 0x5c, 0xd3, 0x55, 0xfb, 0xb9, ++ 0x4d, 0x83, 0xcf, 0x3e, 0xde, 0xcc, 0xa0, 0xfd, 0xfd, 0xec, 0x22, 0x7b, ++ 0x7d, 0x03, 0xc6, 0x6f, 0x3e, 0xc9, 0xba, 0x1d, 0x7c, 0xf7, 0xf4, 0x18, ++ 0xf3, 0x3b, 0xea, 0x67, 0xf0, 0xeb, 0x2d, 0xb9, 0xfb, 0xbe, 0x27, 0xf2, ++ 0xb7, 0x34, 0x8e, 0x1a, 0x66, 0x38, 0x4e, 0xff, 0x82, 0xbd, 0xf3, 0xe7, ++ 0x01, 0x1d, 0x14, 0xea, 0xdc, 0xee, 0x28, 0x9c, 0xbf, 0xb0, 0x21, 0xb7, ++ 0x06, 0xe5, 0x14, 0x13, 0x79, 0x26, 0x99, 0xed, 0x8f, 0x42, 0xa1, 0xef, ++ 0x95, 0xf6, 0x97, 0x94, 0x1c, 0xf4, 0x47, 0x4d, 0xde, 0x3e, 0xb9, 0xe4, ++ 0xad, 0x19, 0x39, 0x78, 0x5e, 0x5c, 0xc7, 0xe8, 0x3c, 0x3d, 0xaa, 0xde, ++ 0x13, 0xcb, 0x31, 0x52, 0xf6, 0x48, 0xbf, 0x5a, 0x9e, 0x85, 0x78, 0xfe, ++ 0xfc, 0xed, 0x91, 0xbb, 0xbd, 0xe9, 0x79, 0x37, 0x29, 0x7b, 0xe4, 0x81, ++ 0x57, 0x8d, 0x9a, 0x0c, 0xf6, 0x88, 0x7a, 0x8f, 0x64, 0xc2, 0x38, 0xb3, ++ 0x96, 0x80, 0x3d, 0x52, 0x95, 0x6e, 0x8f, 0xb4, 0x4a, 0x28, 0x83, 0xb2, ++ 0x97, 0x80, 0x3d, 0x42, 0x76, 0x47, 0xf4, 0x3d, 0xc4, 0xd7, 0x48, 0x76, ++ 0xc9, 0x8f, 0x2d, 0xfb, 0xde, 0x9f, 0xd9, 0xae, 0xfe, 0x83, 0xca, 0xf5, ++ 0x2c, 0xe8, 0x99, 0x7f, 0xfa, 0x2c, 0x7a, 0x66, 0x9c, 0xd7, 0xfc, 0x17, ++ 0xf5, 0x73, 0xb0, 0x07, 0xa6, 0x95, 0x18, 0x2b, 0x23, 0x19, 0xe8, 0xf0, ++ 0x03, 0x95, 0xc7, 0x3b, 0x2c, 0xfd, 0xd9, 0x18, 0x4c, 0x28, 0x78, 0x76, ++ 0x0e, 0x7a, 0x53, 0x75, 0xc1, 0xf3, 0x6b, 0xeb, 0x92, 0x2f, 0xa1, 0x38, ++ 0xee, 0xd0, 0x77, 0x06, 0x71, 0xdd, 0xb0, 0x1e, 0x97, 0xab, 0xf6, 0xd3, ++ 0xaf, 0xe7, 0x8c, 0xca, 0xe1, 0x99, 0xa8, 0xf2, 0x3c, 0x98, 0x91, 0xfa, ++ 0x7d, 0x6b, 0x04, 0x7f, 0xc5, 0xab, 0x79, 0x85, 0xdd, 0x62, 0xdf, 0xef, ++ 0xfe, 0x05, 0xef, 0xe8, 0x32, 0xfa, 0x2f, 0xe0, 0xc7, 0xa0, 0xff, 0x92, ++ 0xf4, 0x95, 0x6d, 0xc3, 0xb8, 0xe0, 0x99, 0x98, 0x4a, 0xf1, 0x3a, 0x75, ++ 0xfe, 0xca, 0xdd, 0x73, 0x91, 0x9e, 0xc0, 0xce, 0xe6, 0xf4, 0x7c, 0x7e, ++ 0xfb, 0xfa, 0xda, 0x21, 0xd9, 0xc6, 0xc7, 0xd3, 0xce, 0x66, 0xd9, 0xf8, ++ 0xbe, 0x9e, 0xd9, 0xcf, 0xe9, 0x66, 0x78, 0xec, 0xe7, 0x74, 0x8d, 0xba, ++ 0xfd, 0x9c, 0x6e, 0x56, 0xc8, 0x7e, 0x4e, 0x37, 0xc7, 0xb0, 0x9f, 0xd3, ++ 0x5d, 0x5f, 0x69, 0x3f, 0xa7, 0x73, 0xda, 0xf7, 0x33, 0x47, 0xbb, 0xfe, ++ 0x7b, 0xda, 0xf7, 0xa1, 0x46, 0x46, 0xfc, 0x74, 0x01, 0xfb, 0x1e, 0xf8, ++ 0xe9, 0x26, 0xa4, 0xa7, 0x91, 0xf8, 0xe9, 0xba, 0x7c, 0xe3, 0xfe, 0x48, ++ 0x86, 0xfd, 0xae, 0xd6, 0xb8, 0x9d, 0xba, 0xda, 0x1b, 0x59, 0x80, 0x74, ++ 0x37, 0xcd, 0xe0, 0x76, 0x5d, 0x34, 0xb6, 0x9e, 0xf2, 0x01, 0xf3, 0xa2, ++ 0x20, 0x6f, 0x4a, 0x29, 0x6e, 0x48, 0x71, 0x2f, 0x2b, 0xae, 0x65, 0xc5, ++ 0xbd, 0xac, 0xbc, 0x40, 0x2b, 0x9e, 0xe5, 0x8c, 0x5f, 0x59, 0x71, 0x2f, ++ 0x2b, 0x8e, 0x25, 0xc5, 0x78, 0xdc, 0xaa, 0xd9, 0x13, 0x5d, 0x81, 0xf0, ++ 0x36, 0xb7, 0x9f, 0x94, 0x51, 0x8e, 0xe8, 0xcf, 0xc1, 0x3c, 0xc8, 0x08, ++ 0xd6, 0x39, 0xde, 0xb0, 0xf8, 0x1c, 0x97, 0x07, 0x2d, 0xed, 0x99, 0xe3, ++ 0x72, 0xce, 0xf8, 0xdb, 0x88, 0xed, 0x3e, 0x25, 0x5f, 0x7d, 0x0e, 0xfa, ++ 0x61, 0x3d, 0xae, 0xd7, 0xd2, 0x0f, 0xc0, 0xe7, 0x0f, 0x7e, 0x16, 0x3e, ++ 0x07, 0xb9, 0xb5, 0x0d, 0xc7, 0xfb, 0x17, 0xe4, 0xf7, 0x51, 0x24, 0x4f, ++ 0xba, 0x69, 0xff, 0x2a, 0x00, 0xd7, 0x68, 0xa7, 0xc3, 0x3e, 0x68, 0x18, ++ 0xa7, 0x5f, 0x70, 0x7a, 0x3f, 0xc6, 0xe3, 0xd4, 0xe3, 0x6e, 0xe2, 0xdb, ++ 0x8b, 0xf5, 0x7f, 0x31, 0xd1, 0x41, 0x86, 0x4d, 0x8b, 0x82, 0x0f, 0x8e, ++ 0xf1, 0xac, 0x68, 0xac, 0x94, 0xf4, 0x8b, 0xc5, 0x37, 0x16, 0x9f, 0x38, ++ 0xfd, 0xe3, 0x61, 0xfc, 0xf1, 0x5f, 0xcd, 0x3f, 0x17, 0xe9, 0x1f, 0x03, ++ 0xff, 0x7c, 0xcf, 0x75, 0x1e, 0x7d, 0x04, 0xfc, 0xf1, 0x3c, 0xe2, 0x7b, ++ 0x5a, 0x25, 0xc7, 0xaf, 0x93, 0x1f, 0x2c, 0xfa, 0x07, 0x92, 0x48, 0x48, ++ 0xd5, 0xb8, 0xdf, 0xd1, 0x04, 0xb6, 0xb7, 0xe8, 0x9d, 0xbd, 0x18, 0x36, ++ 0x11, 0xce, 0x89, 0xc2, 0xaf, 0x39, 0x31, 0x5a, 0x23, 0xff, 0xe2, 0xc4, ++ 0xf3, 0xff, 0xce, 0xcf, 0x61, 0x9f, 0xf7, 0x84, 0xc7, 0x89, 0x35, 0xe2, ++ 0xfb, 0x89, 0xdd, 0x05, 0xf1, 0x6d, 0xa5, 0x29, 0x3e, 0xb3, 0xf8, 0xa9, ++ 0xdd, 0x13, 0xfd, 0xb1, 0x2b, 0x2d, 0x0f, 0xc4, 0xca, 0x77, 0x3c, 0xec, ++ 0x31, 0x5f, 0xc7, 0xe7, 0x21, 0xb5, 0x2f, 0x81, 0xfe, 0x4a, 0x68, 0x36, ++ 0x0b, 0x6f, 0x30, 0x88, 0xcf, 0x8e, 0xf1, 0xe7, 0x9c, 0x4f, 0x7d, 0x61, ++ 0x46, 0xf1, 0xd3, 0xcf, 0xec, 0x97, 0xed, 0x75, 0xc5, 0xf1, 0x7c, 0xa8, ++ 0x45, 0x1a, 0x5a, 0xca, 0xc8, 0x6f, 0x65, 0x1a, 0xf2, 0xad, 0x2a, 0xe4, ++ 0xc9, 0x8b, 0x59, 0xd1, 0x93, 0x88, 0xcf, 0xe6, 0xe9, 0x91, 0x12, 0x4e, ++ 0x4f, 0x43, 0xe3, 0x7c, 0x00, 0xd7, 0x2f, 0x3a, 0x14, 0xf2, 0xd7, 0x3e, ++ 0x2b, 0x3f, 0x35, 0x8f, 0x84, 0xff, 0x73, 0xf8, 0x88, 0x0e, 0xb9, 0x6a, ++ 0x87, 0xe7, 0x07, 0xa4, 0xcb, 0x2d, 0x94, 0x6f, 0xa1, 0x90, 0x16, 0xdf, ++ 0x20, 0x65, 0x90, 0x57, 0x02, 0x5f, 0x71, 0x16, 0x1e, 0x83, 0xeb, 0x83, ++ 0xfd, 0xfc, 0x77, 0xc4, 0x63, 0x5e, 0x15, 0x93, 0x68, 0x39, 0x82, 0x8f, ++ 0x9b, 0x3d, 0xe6, 0x1f, 0x5c, 0x9f, 0xcd, 0xfe, 0x50, 0xb4, 0xda, 0x14, ++ 0x1f, 0x03, 0xde, 0x3c, 0x1a, 0xca, 0xc5, 0x6a, 0xc0, 0x5b, 0xf9, 0x70, ++ 0xbc, 0x9d, 0x74, 0xf1, 0xf5, 0x3b, 0xe9, 0x2f, 0xa4, 0x26, 0x65, 0xa4, ++ 0xff, 0x10, 0xc8, 0xd1, 0x0d, 0x52, 0xda, 0x39, 0xa9, 0xc0, 0x8b, 0xb5, ++ 0x9e, 0x91, 0xe4, 0xb3, 0x45, 0xa7, 0x69, 0xe7, 0x0d, 0x21, 0x2d, 0x7d, ++ 0xbd, 0xff, 0x8f, 0xca, 0x65, 0x4b, 0x5e, 0x5e, 0xee, 0x89, 0x4e, 0xc6, ++ 0x7d, 0x70, 0x9b, 0x11, 0x21, 0xff, 0x4c, 0xda, 0x5f, 0xa7, 0x9c, 0x19, ++ 0x6e, 0x07, 0xc9, 0x74, 0xce, 0x78, 0x06, 0xec, 0x1e, 0xec, 0x76, 0xb1, ++ 0xf2, 0x75, 0xda, 0x59, 0x2f, 0x1e, 0x96, 0xb0, 0xa9, 0x67, 0x15, 0x2a, ++ 0xaf, 0x3d, 0x4b, 0x87, 0x27, 0xec, 0x8b, 0x67, 0xb3, 0xa9, 0x34, 0xcf, ++ 0xe6, 0x53, 0x59, 0x7f, 0x36, 0x97, 0xca, 0xe9, 0x67, 0x2f, 0xa1, 0x72, ++ 0xc6, 0xd9, 0xd1, 0x54, 0x36, 0x9c, 0x05, 0x60, 0xc0, 0xc4, 0x69, 0x3c, ++ 0x5b, 0x4a, 0xe5, 0xcc, 0xb3, 0x57, 0x50, 0x39, 0xeb, 0xec, 0x78, 0x2a, ++ 0x67, 0x9f, 0xbd, 0x8a, 0xda, 0xcd, 0x39, 0x3b, 0x89, 0xca, 0xeb, 0xce, ++ 0x7e, 0x81, 0xca, 0xeb, 0xcf, 0x4e, 0xa1, 0xd2, 0x69, 0xff, 0x18, 0xeb, ++ 0x55, 0x92, 0xdf, 0x96, 0xfc, 0xb2, 0xe4, 0xbb, 0x53, 0x7e, 0x5b, 0xf2, ++ 0xef, 0xff, 0x9a, 0xfc, 0x8e, 0x35, 0x5c, 0x94, 0xfd, 0x03, 0xfa, 0xef, ++ 0xab, 0xda, 0x79, 0xe4, 0xf7, 0x48, 0xf2, 0x02, 0xf8, 0xfa, 0x3e, 0x2d, ++ 0x5d, 0x4e, 0xa4, 0xf4, 0xf3, 0xfd, 0xda, 0x67, 0xe0, 0xeb, 0xe3, 0x82, ++ 0x4f, 0x81, 0x7f, 0xdf, 0xc3, 0x38, 0x8c, 0x07, 0xbc, 0x38, 0x8a, 0x53, ++ 0x85, 0x79, 0x9c, 0x2a, 0x60, 0x68, 0x06, 0xe6, 0x69, 0xec, 0xc3, 0x26, ++ 0xb0, 0xa5, 0xfe, 0xd2, 0xc8, 0x49, 0x8c, 0x1b, 0x34, 0x2f, 0xf0, 0xe8, ++ 0x31, 0x80, 0x7b, 0xa0, 0x54, 0x23, 0xf9, 0xb4, 0x2d, 0xa8, 0xd1, 0xb9, ++ 0xdb, 0x66, 0x49, 0x1f, 0xcd, 0xe5, 0x41, 0x32, 0x81, 0xf4, 0xb7, 0x33, ++ 0xa4, 0xd1, 0x78, 0xdb, 0xfe, 0xa8, 0x78, 0x31, 0x7f, 0xe1, 0xa5, 0x51, ++ 0x05, 0x01, 0x9c, 0xa7, 0xdb, 0x2f, 0xeb, 0xd8, 0xfe, 0x5b, 0xb9, 0xc9, ++ 0x7d, 0xb7, 0xe0, 0x39, 0xfe, 0x14, 0x16, 0x3e, 0x04, 0xe3, 0xad, 0xd8, ++ 0xb3, 0xc7, 0x93, 0xee, 0x87, 0xef, 0x47, 0xe3, 0x00, 0xe0, 0x0b, 0xc4, ++ 0x9e, 0x66, 0x0c, 0xf8, 0x7a, 0xe3, 0xa8, 0xdf, 0x2d, 0xc5, 0xf9, 0x7c, ++ 0x53, 0x19, 0xc5, 0x63, 0xa0, 0x34, 0x33, 0xe5, 0x8b, 0x7d, 0xd3, 0x2d, ++ 0xce, 0xa7, 0xd5, 0xa1, 0x10, 0xe2, 0x69, 0xab, 0x4f, 0x26, 0x7d, 0xd0, ++ 0xad, 0x7b, 0x44, 0x1e, 0x6a, 0x72, 0xa0, 0x05, 0xfd, 0xdc, 0x3a, 0x99, ++ 0x6d, 0x83, 0x79, 0x37, 0x8c, 0x7e, 0x67, 0x0b, 0x82, 0xad, 0x8e, 0x2b, ++ 0xdb, 0x51, 0x06, 0xf5, 0x9d, 0x75, 0x65, 0x5e, 0xdc, 0xa4, 0xa7, 0x5f, ++ 0xf9, 0x20, 0x44, 0xf6, 0x04, 0xbc, 0x43, 0x50, 0xa0, 0x4c, 0x88, 0xd2, ++ 0xcc, 0x81, 0xfd, 0xe9, 0xf4, 0x86, 0x8d, 0xf3, 0x9d, 0xb7, 0x29, 0xc6, ++ 0xd0, 0x3a, 0x24, 0x56, 0xec, 0xef, 0xae, 0x1e, 0xb9, 0xdd, 0x26, 0xff, ++ 0x40, 0x08, 0xe9, 0xa3, 0x63, 0xd2, 0xe4, 0xca, 0x5b, 0x60, 0xfe, 0xde, ++ 0x49, 0x05, 0xa3, 0x71, 0xfe, 0xed, 0x35, 0x47, 0x6d, 0xf8, 0x50, 0x74, ++ 0x7b, 0x3c, 0x45, 0xc1, 0x80, 0x23, 0xfa, 0xe1, 0x75, 0x49, 0x8a, 0xab, ++ 0x6d, 0x90, 0x8d, 0x1d, 0x65, 0xb0, 0xbe, 0x80, 0xc8, 0xb7, 0x06, 0x30, ++ 0x2b, 0x23, 0x69, 0x79, 0x07, 0x16, 0x1c, 0x4a, 0x18, 0xd6, 0xc1, 0xe1, ++ 0x4a, 0x28, 0x7c, 0x3d, 0xac, 0x00, 0x9e, 0xe7, 0xd6, 0x25, 0x62, 0x49, ++ 0xbe, 0x5e, 0x13, 0xe3, 0xae, 0x3e, 0x5f, 0x32, 0x84, 0xfe, 0xa2, 0x52, ++ 0x77, 0x9a, 0xe2, 0x6d, 0x9d, 0xfe, 0xe4, 0x22, 0xaa, 0x3b, 0xe0, 0xb0, ++ 0xc6, 0xff, 0xad, 0x66, 0xe5, 0x05, 0x70, 0xbe, 0xf1, 0x09, 0xbe, 0x69, ++ 0x9e, 0xf4, 0xed, 0x45, 0x94, 0x47, 0x5e, 0xa5, 0xd1, 0xbe, 0x75, 0xbb, ++ 0x86, 0x16, 0x60, 0x3d, 0xb6, 0xd6, 0xc5, 0x1e, 0xcf, 0x10, 0xbf, 0xd9, ++ 0x20, 0xf8, 0x79, 0x5b, 0xe5, 0xf9, 0xe3, 0x32, 0xaa, 0xcf, 0x0e, 0x47, ++ 0xb7, 0xd7, 0xee, 0x2f, 0x5a, 0xf0, 0xbc, 0x2f, 0x4a, 0x27, 0x1c, 0xcd, ++ 0xae, 0xa1, 0x51, 0x99, 0xf6, 0xef, 0xd3, 0xce, 0x7f, 0xa1, 0x75, 0x7f, ++ 0xde, 0xf3, 0x75, 0x8e, 0x90, 0x3f, 0x70, 0xb9, 0xdb, 0xbe, 0x0f, 0x01, ++ 0x21, 0xcf, 0x9b, 0xa7, 0x7c, 0x3b, 0x84, 0xe7, 0xe2, 0x16, 0x3c, 0x9d, ++ 0x12, 0xec, 0x43, 0xcd, 0xe7, 0xbf, 0x0f, 0xcd, 0x53, 0xb8, 0xbc, 0xfe, ++ 0xbc, 0xd7, 0xfb, 0x3f, 0x6d, 0xdc, 0xdf, 0x6b, 0x3c, 0xae, 0x02, 0x7c, ++ 0x3a, 0xbb, 0x1c, 0xe3, 0x8c, 0x63, 0x26, 0x87, 0x30, 0x5e, 0xeb, 0xb3, ++ 0xe2, 0xd1, 0xe1, 0x38, 0xe5, 0x27, 0x05, 0x30, 0x1e, 0x4d, 0xbd, 0x0c, ++ 0xd2, 0x43, 0xaa, 0xce, 0xc7, 0x50, 0x54, 0x96, 0x40, 0x3e, 0x94, 0xb3, ++ 0x3f, 0x4c, 0xe0, 0x3e, 0x29, 0xd5, 0x9a, 0xa1, 0x90, 0x9c, 0xcd, 0xbc, ++ 0xef, 0x4a, 0x78, 0x13, 0xe5, 0xb5, 0x39, 0xf9, 0xd3, 0x82, 0x9b, 0xfe, ++ 0x26, 0x0b, 0xd3, 0x81, 0xce, 0x0f, 0xbd, 0x56, 0x7c, 0xda, 0x50, 0x27, ++ 0xf3, 0xfb, 0x12, 0x18, 0xff, 0x55, 0x98, 0x75, 0x3e, 0xcb, 0xe3, 0xd3, ++ 0x56, 0x7f, 0xb5, 0x42, 0xa6, 0x78, 0x34, 0x05, 0xb2, 0xd3, 0xc6, 0x51, ++ 0x41, 0x0f, 0xe3, 0x39, 0x8e, 0x82, 0x71, 0xea, 0xbc, 0xe1, 0xf3, 0x7f, ++ 0x37, 0x45, 0x8f, 0xf6, 0xf9, 0x8b, 0x78, 0x7c, 0x5c, 0x51, 0xb9, 0x1f, ++ 0xf8, 0x9e, 0xc4, 0xf1, 0x11, 0x7b, 0x55, 0xa1, 0x7c, 0xcf, 0xae, 0xe7, ++ 0xb9, 0x7c, 0x63, 0xc7, 0x19, 0xc9, 0xef, 0xae, 0x5a, 0x83, 0xce, 0x55, ++ 0x76, 0xc0, 0xff, 0xe8, 0x3f, 0xc4, 0x6a, 0x7d, 0x71, 0xa4, 0x5b, 0xc5, ++ 0x91, 0x8f, 0x77, 0xa6, 0x72, 0x7a, 0x08, 0xe5, 0xa8, 0x15, 0x17, 0xa7, ++ 0xf9, 0xf8, 0xf9, 0x00, 0xc5, 0xb9, 0x31, 0x4f, 0x91, 0xe2, 0xe6, 0x06, ++ 0xab, 0xc0, 0xf7, 0xdd, 0x02, 0x34, 0x6b, 0x1c, 0xd5, 0x8a, 0xcb, 0x57, ++ 0xae, 0x99, 0x84, 0xed, 0xfc, 0x06, 0xf3, 0x3c, 0x07, 0xeb, 0xf3, 0xd7, ++ 0xb1, 0xc4, 0x25, 0x00, 0x6f, 0xd0, 0xdd, 0xba, 0xf5, 0xf2, 0xd2, 0x0c, ++ 0xf1, 0xf0, 0xca, 0x35, 0xdf, 0x78, 0x12, 0xe6, 0xdd, 0xfd, 0xd4, 0xf4, ++ 0x5f, 0x3d, 0x09, 0xf5, 0x5d, 0x72, 0xf8, 0xd5, 0x3a, 0x68, 0x97, 0xff, ++ 0xe5, 0x3a, 0xc2, 0xab, 0x33, 0x1e, 0xbe, 0xad, 0x52, 0x36, 0x75, 0x94, ++ 0x0f, 0x3e, 0xdf, 0x21, 0xdc, 0x57, 0xb0, 0xa1, 0x89, 0x2e, 0x6e, 0xed, ++ 0x91, 0x62, 0xf8, 0x3c, 0xdb, 0xe7, 0x3b, 0xc8, 0xf7, 0xbb, 0x35, 0xa4, ++ 0x20, 0x5e, 0x40, 0x4f, 0x22, 0x5e, 0xbc, 0xce, 0xbc, 0xc8, 0x74, 0x7c, ++ 0x97, 0x21, 0x1c, 0x3b, 0x07, 0xe6, 0xc1, 0xbf, 0xbd, 0x5b, 0xe7, 0x2d, ++ 0xc3, 0x79, 0x11, 0x6e, 0xcc, 0xaf, 0x5c, 0xd1, 0x5b, 0xaf, 0xa1, 0x9e, ++ 0x09, 0x2e, 0xb1, 0x9f, 0x5f, 0xf8, 0x9b, 0xec, 0x75, 0x6f, 0x95, 0x1d, ++ 0xce, 0xad, 0x62, 0xff, 0x2e, 0x44, 0xff, 0xce, 0x3c, 0xc4, 0x1e, 0x73, ++ 0xde, 0x22, 0xa4, 0xdb, 0x33, 0x41, 0x8d, 0xa1, 0xbc, 0xd9, 0xb8, 0xf6, ++ 0xea, 0x1b, 0x49, 0xee, 0x6f, 0x57, 0xd8, 0xb8, 0xd2, 0x0c, 0xf4, 0xeb, ++ 0x58, 0x57, 0xa7, 0xe6, 0x22, 0xfd, 0xdf, 0x6d, 0xd4, 0xef, 0xad, 0x40, ++ 0xbd, 0xd1, 0xa0, 0x51, 0x5e, 0x4f, 0x77, 0xdc, 0x1b, 0xc7, 0x14, 0xef, ++ 0xed, 0x75, 0xa9, 0x73, 0x13, 0x9b, 0xfd, 0x6e, 0x68, 0xfc, 0x1c, 0xab, ++ 0x46, 0x4e, 0xb8, 0x33, 0xd9, 0xf1, 0xe2, 0x7c, 0x2c, 0x20, 0x9e, 0x31, ++ 0xc7, 0x39, 0x58, 0xf7, 0x6c, 0x99, 0xec, 0x9a, 0xee, 0x1e, 0x3e, 0x8f, ++ 0x35, 0x5e, 0x77, 0xdd, 0x5b, 0x1e, 0x94, 0x13, 0x23, 0x8d, 0xfb, 0xf4, ++ 0x18, 0xf3, 0x88, 0x1b, 0xed, 0xa9, 0x68, 0xde, 0x45, 0xdd, 0xbb, 0xb8, ++ 0x6f, 0xa3, 0x8b, 0xd3, 0xf5, 0x14, 0x2d, 0x2e, 0x95, 0xa2, 0x3d, 0xaa, ++ 0x2f, 0x5c, 0x04, 0xf5, 0xcd, 0xe3, 0x64, 0xb2, 0x87, 0x98, 0xf0, 0xff, ++ 0xba, 0xaf, 0xe5, 0xe7, 0x89, 0x0f, 0x6b, 0x86, 0xed, 0x7e, 0xc5, 0xa6, ++ 0x29, 0x2b, 0xc9, 0x6e, 0xb8, 0xc9, 0xad, 0x0b, 0xfe, 0x02, 0xbb, 0x70, ++ 0x42, 0xea, 0xbe, 0xc5, 0x01, 0xaf, 0xf9, 0x82, 0x1b, 0x9e, 0xab, 0xcf, ++ 0xc1, 0x48, 0x60, 0x0f, 0xbc, 0x97, 0x1b, 0xbe, 0x11, 0xe9, 0xa2, 0x31, ++ 0xf8, 0x11, 0xd9, 0x51, 0xb7, 0x16, 0xc9, 0x3a, 0xd2, 0xd7, 0x8a, 0x3d, ++ 0x8d, 0xb4, 0xae, 0xcd, 0xba, 0xcc, 0x12, 0x68, 0xf7, 0xaa, 0xad, 0x64, ++ 0xa4, 0x36, 0xb1, 0x56, 0x13, 0xcf, 0x03, 0x30, 0x51, 0x13, 0xe9, 0x6e, ++ 0x0e, 0xbc, 0x91, 0xe9, 0x5e, 0x44, 0xf2, 0x50, 0x27, 0xc0, 0x39, 0x67, ++ 0x5c, 0xe1, 0xa4, 0x6d, 0x50, 0x73, 0x17, 0xb5, 0x52, 0x1e, 0x4b, 0xa3, ++ 0x21, 0x91, 0x1f, 0x76, 0x1d, 0x60, 0x06, 0xe5, 0x41, 0x4b, 0x71, 0x44, ++ 0x95, 0xaa, 0xb0, 0xdf, 0xfc, 0x77, 0xd0, 0xee, 0x9b, 0x13, 0x2c, 0x95, ++ 0xd1, 0xdf, 0xbf, 0x4e, 0x65, 0x0d, 0x5a, 0x9a, 0x7d, 0x0e, 0x76, 0xf1, ++ 0x31, 0x77, 0xda, 0xba, 0x4e, 0x8c, 0xdb, 0x13, 0x94, 0xab, 0x70, 0x7e, ++ 0x98, 0x07, 0xe7, 0x5f, 0xe4, 0xa1, 0xfb, 0x04, 0x6e, 0xb4, 0x8f, 0xaf, ++ 0x4c, 0xd9, 0xc7, 0x13, 0x11, 0x91, 0x69, 0x76, 0xf2, 0xaf, 0xd1, 0xa8, ++ 0xc4, 0x78, 0x46, 0x51, 0xe2, 0xf7, 0x94, 0xe7, 0xfd, 0xfd, 0xa4, 0x8c, ++ 0xf3, 0xb2, 0x17, 0x58, 0xf5, 0x36, 0xe9, 0x93, 0xfb, 0xd5, 0xe0, 0x5f, ++ 0xfe, 0x12, 0xf7, 0x33, 0xce, 0x8c, 0x7e, 0x4c, 0x35, 0xfc, 0xac, 0x71, ++ 0x89, 0xaf, 0x6b, 0x62, 0x9f, 0xc4, 0xbd, 0x95, 0xc3, 0x9e, 0xc8, 0x6f, ++ 0x70, 0x7c, 0x2b, 0x1e, 0x30, 0x51, 0xe3, 0xf7, 0x9b, 0x37, 0xb7, 0xb0, ++ 0x70, 0x2c, 0x2d, 0xae, 0xb2, 0xf9, 0xf9, 0x3f, 0x3f, 0x8e, 0xf6, 0xaa, ++ 0x15, 0x7f, 0x39, 0x97, 0x77, 0x27, 0xe0, 0xb4, 0xe0, 0xde, 0x24, 0xb1, ++ 0x2c, 0xd2, 0xf3, 0x9e, 0xe8, 0x1f, 0xdc, 0xe9, 0x7e, 0x31, 0x4b, 0x96, ++ 0xcd, 0x9d, 0xf0, 0xf9, 0xc1, 0x9d, 0x21, 0x5f, 0xce, 0x57, 0x0b, 0xfc, ++ 0x34, 0x56, 0xf0, 0x4f, 0x5e, 0x6d, 0x85, 0x17, 0xe5, 0xe6, 0x58, 0xcc, ++ 0xf7, 0xc1, 0x7d, 0x68, 0xe7, 0xf2, 0xc4, 0x84, 0xff, 0xd2, 0xf3, 0x7d, ++ 0x14, 0xc1, 0x7c, 0xc1, 0x70, 0x6b, 0xbf, 0x6c, 0x0c, 0x97, 0x4b, 0x8a, ++ 0xb8, 0x37, 0x05, 0x74, 0x2d, 0xa1, 0x1d, 0xeb, 0xcc, 0x07, 0x52, 0x30, ++ 0xef, 0x67, 0xe2, 0x70, 0xb9, 0x71, 0x40, 0xd0, 0xff, 0x25, 0x1e, 0x91, ++ 0xff, 0x33, 0x99, 0x4d, 0xe6, 0x7e, 0xb8, 0xfd, 0xfc, 0xca, 0xbf, 0x94, ++ 0xeb, 0x7d, 0xd6, 0x9a, 0x97, 0xf1, 0x1e, 0xea, 0xf7, 0x85, 0xde, 0x7f, ++ 0x51, 0xf8, 0x95, 0x09, 0x71, 0xaf, 0xf1, 0xa8, 0xb8, 0xb7, 0xf8, 0xf2, ++ 0x3a, 0x83, 0xfc, 0xbc, 0x57, 0xd6, 0x55, 0x52, 0x39, 0xb0, 0x2e, 0x4c, ++ 0xcf, 0x5f, 0x5b, 0x57, 0x47, 0x65, 0xea, 0x7e, 0x15, 0x9f, 0x37, 0x5f, ++ 0xd8, 0x61, 0x2a, 0x06, 0xd5, 0xf0, 0x9c, 0xdf, 0xc7, 0xe2, 0x06, 0xc0, ++ 0xeb, 0x1f, 0xb5, 0x66, 0xa0, 0x14, 0xf9, 0xbc, 0x8e, 0xdf, 0xef, 0xee, ++ 0x6e, 0x3a, 0xb5, 0xa5, 0x9c, 0xec, 0x46, 0x7e, 0x6e, 0xb1, 0xb9, 0xa8, ++ 0x3a, 0x51, 0x88, 0xfe, 0x0b, 0xc0, 0x9a, 0x0f, 0x75, 0x97, 0xaf, 0xcf, ++ 0xc3, 0xef, 0x79, 0x99, 0x83, 0x95, 0x05, 0x5c, 0xcd, 0x21, 0xde, 0xff, ++ 0xab, 0xcf, 0x2b, 0x9c, 0x74, 0xa1, 0x5b, 0xfb, 0xef, 0xd8, 0x6f, 0x1f, ++ 0x6b, 0x65, 0x28, 0xef, 0x02, 0xa6, 0x7d, 0xbf, 0xb3, 0xc3, 0x4e, 0xff, ++ 0x86, 0xef, 0xbf, 0xab, 0xe8, 0xe2, 0xf6, 0xbd, 0x17, 0xff, 0x01, 0xfb, ++ 0xf8, 0x25, 0x6b, 0xdf, 0xaf, 0x66, 0x57, 0xf3, 0xef, 0x33, 0x5c, 0x9c, ++ 0x3c, 0x46, 0x3e, 0xaa, 0x14, 0x72, 0x60, 0x0c, 0xf0, 0xd3, 0x01, 0xf0, ++ 0xe7, 0xdd, 0x0a, 0xcf, 0x57, 0xcf, 0xe7, 0x79, 0xae, 0x66, 0x88, 0xf3, ++ 0x9b, 0xa9, 0xf2, 0x7a, 0x6c, 0xbc, 0x68, 0xef, 0xe2, 0x24, 0xc4, 0x06, ++ 0xf2, 0x78, 0x5e, 0x7b, 0x31, 0x3f, 0x4f, 0xa0, 0x7e, 0x98, 0x57, 0x8e, ++ 0xef, 0x31, 0x2c, 0xf9, 0x02, 0x8f, 0x6f, 0xb1, 0x1c, 0x91, 0xff, 0x3e, ++ 0x56, 0x8c, 0xb3, 0x5a, 0x8c, 0x3b, 0xb1, 0x9a, 0xee, 0xed, 0xf2, 0xf3, ++ 0x7f, 0xd6, 0xa7, 0x63, 0xe9, 0x63, 0x49, 0xaa, 0xe7, 0x02, 0x1f, 0x60, ++ 0x19, 0x64, 0xad, 0x12, 0x22, 0x73, 0x0c, 0x1b, 0x24, 0x7f, 0xbb, 0x58, ++ 0x1a, 0xa2, 0xba, 0x21, 0xe9, 0x59, 0x58, 0x2f, 0x93, 0xc2, 0x65, 0xdc, ++ 0x0f, 0x8f, 0x93, 0xfe, 0x2c, 0x57, 0xcc, 0x6f, 0x57, 0x10, 0xf2, 0x23, ++ 0x32, 0x8f, 0x17, 0x25, 0x17, 0x93, 0x3d, 0x09, 0x7a, 0x19, 0xe5, 0x62, ++ 0x5c, 0x8d, 0x2c, 0x42, 0xf9, 0xb2, 0xa1, 0x4d, 0x0b, 0x03, 0x26, 0xce, ++ 0xe5, 0xc9, 0xe1, 0xfd, 0x39, 0x2c, 0x37, 0xf4, 0xd5, 0x0c, 0xe0, 0xf9, ++ 0x47, 0x2c, 0x26, 0x93, 0xfc, 0x51, 0x9e, 0x63, 0x59, 0xfa, 0x95, 0x64, ++ 0xef, 0x91, 0xfe, 0xda, 0xb0, 0x3e, 0xef, 0x60, 0x36, 0xe5, 0x6b, 0x24, ++ 0x29, 0xcf, 0x7d, 0xbf, 0xa7, 0xd4, 0xa6, 0xa7, 0x26, 0xfa, 0x16, 0x5e, ++ 0xa7, 0xc3, 0x7e, 0x6d, 0x14, 0xf9, 0x74, 0x2e, 0xe8, 0xcf, 0x32, 0xe4, ++ 0x9f, 0x5a, 0xf9, 0x74, 0x30, 0x6e, 0x49, 0xa6, 0xf7, 0x56, 0xb9, 0xd1, ++ 0xaf, 0x2d, 0xca, 0xe4, 0xf7, 0x3f, 0xec, 0x91, 0x44, 0x3c, 0x23, 0x39, ++ 0x9a, 0xe2, 0x80, 0x62, 0x5f, 0xe3, 0x53, 0xe5, 0x8c, 0xf7, 0x19, 0xf7, ++ 0x79, 0xb8, 0x5d, 0xf3, 0x68, 0x69, 0x66, 0x7b, 0x9a, 0xb1, 0x07, 0x69, ++ 0xbc, 0xfd, 0x1e, 0xdd, 0x31, 0x6e, 0xb2, 0x85, 0xee, 0xcf, 0xe8, 0x3c, ++ 0xbe, 0x91, 0xe5, 0x32, 0x29, 0xbf, 0x66, 0x63, 0x1b, 0xbf, 0xa7, 0x6f, ++ 0xe1, 0x6f, 0x34, 0xd8, 0xb5, 0x68, 0x0f, 0x6f, 0xec, 0x9b, 0x3f, 0x1b, ++ 0xf9, 0x3b, 0x56, 0xa9, 0x52, 0xbe, 0x39, 0xac, 0xdf, 0x87, 0xf8, 0x73, ++ 0x89, 0xbc, 0xe4, 0x8d, 0xe3, 0x83, 0x07, 0xb3, 0x79, 0x5c, 0xa2, 0x14, ++ 0xe5, 0x74, 0x3f, 0xe2, 0xaf, 0x36, 0x0d, 0x7f, 0xc1, 0x95, 0x4d, 0x88, ++ 0xbf, 0x8e, 0x57, 0x79, 0x7e, 0x2f, 0xe8, 0x73, 0x1f, 0xcb, 0x90, 0x6f, ++ 0x68, 0xe1, 0xcf, 0xe5, 0x63, 0x5f, 0xcc, 0xf4, 0xde, 0x2a, 0x3b, 0x46, ++ 0x69, 0x8b, 0x32, 0xdd, 0x1b, 0x3e, 0xea, 0xb1, 0xec, 0xf4, 0x64, 0x29, ++ 0xa7, 0x13, 0x8e, 0xbf, 0xac, 0x6b, 0xd5, 0x48, 0xa6, 0xf6, 0x09, 0x81, ++ 0xef, 0x92, 0x32, 0x16, 0x3d, 0x1f, 0xfe, 0xfa, 0x3d, 0xba, 0x6d, 0x5c, ++ 0xeb, 0xdc, 0x57, 0x19, 0x21, 0xde, 0x25, 0xf9, 0x12, 0x14, 0xe7, 0x9a, ++ 0xa8, 0x71, 0x3b, 0x63, 0xc3, 0x62, 0x8e, 0xd7, 0x0d, 0xcf, 0x5f, 0x73, ++ 0x3c, 0x9a, 0x76, 0x0e, 0xf1, 0x4b, 0x1c, 0x72, 0x4a, 0x2a, 0x1e, 0x6c, ++ 0xc5, 0x8d, 0x2d, 0xbd, 0xd9, 0xee, 0x89, 0xfe, 0xa3, 0x67, 0x54, 0x4a, ++ 0x5f, 0xb2, 0xef, 0x33, 0x92, 0xbb, 0xec, 0x05, 0xcf, 0x41, 0xdc, 0xb7, ++ 0x0c, 0xe7, 0x10, 0xa7, 0x3c, 0xb5, 0x19, 0xce, 0x21, 0x7a, 0x2e, 0xee, ++ 0xfb, 0x2e, 0x63, 0x05, 0xdf, 0x1e, 0xda, 0x72, 0x74, 0x1e, 0xce, 0xf3, ++ 0x57, 0x75, 0x8c, 0xec, 0xab, 0xc0, 0x33, 0x7c, 0xde, 0x5c, 0x9d, 0xc5, ++ 0xe5, 0x52, 0xfc, 0x4e, 0x81, 0x29, 0x61, 0x9c, 0xe5, 0x9a, 0x88, 0x5e, ++ 0x8f, 0xf6, 0x9b, 0xab, 0x9d, 0x99, 0x98, 0x3f, 0x33, 0x56, 0xc4, 0x6d, ++ 0x0a, 0xdb, 0xfb, 0x14, 0xa4, 0x8b, 0x20, 0xec, 0x65, 0xa1, 0x84, 0xf7, ++ 0x9a, 0x92, 0x31, 0xfc, 0x9e, 0xc9, 0xd8, 0xdd, 0x8c, 0xfc, 0x44, 0xb5, ++ 0x70, 0xe6, 0xaa, 0xf5, 0x86, 0x10, 0xa5, 0x69, 0xf9, 0x51, 0x0a, 0x1b, ++ 0xea, 0xa7, 0xf5, 0xb5, 0x6b, 0xc6, 0xe3, 0xa5, 0x04, 0xd6, 0x4f, 0x51, ++ 0x3f, 0x8c, 0x11, 0xef, 0x03, 0xed, 0x33, 0x7f, 0x85, 0x72, 0x73, 0x4c, ++ 0x24, 0x4a, 0x79, 0xb8, 0xd0, 0x2f, 0xe6, 0x47, 0xfb, 0x42, 0xe0, 0xb1, ++ 0xc0, 0xcb, 0xf9, 0x76, 0x79, 0x43, 0x58, 0x92, 0xa0, 0x7d, 0x30, 0x98, ++ 0xa4, 0xf8, 0xa4, 0x53, 0xae, 0x8f, 0x01, 0xfc, 0x5c, 0x92, 0x66, 0xbf, ++ 0x05, 0x44, 0x9d, 0xad, 0xe2, 0x72, 0x5a, 0x86, 0xff, 0x50, 0xcf, 0xe7, ++ 0x47, 0xec, 0x72, 0x7b, 0x9c, 0xe3, 0x5e, 0x74, 0xc0, 0x91, 0xf7, 0x92, ++ 0xeb, 0x15, 0xf9, 0xee, 0x96, 0xdc, 0x2e, 0xe2, 0x9b, 0x3a, 0x41, 0x1d, ++ 0x94, 0x33, 0xf9, 0xe5, 0x29, 0xfd, 0xea, 0x80, 0x0f, 0x65, 0x58, 0x75, ++ 0xaa, 0x7f, 0xc0, 0xaa, 0x7f, 0x46, 0xf8, 0x80, 0x10, 0x88, 0x9e, 0x2d, ++ 0x78, 0xf0, 0x2a, 0x25, 0xca, 0xdd, 0x3d, 0x2e, 0xfd, 0x2b, 0x4f, 0xa1, ++ 0x7e, 0xae, 0xd7, 0x78, 0x1e, 0x99, 0xb8, 0x2f, 0x97, 0x2d, 0xf0, 0xee, ++ 0x43, 0x87, 0x19, 0xda, 0x0d, 0x4c, 0x79, 0xc5, 0xc4, 0x7d, 0xdd, 0x11, ++ 0xe6, 0xdf, 0xa5, 0x39, 0x33, 0x75, 0x1e, 0xf9, 0xa1, 0xd9, 0x75, 0xd6, ++ 0x7d, 0x3a, 0x7e, 0x5f, 0x19, 0xca, 0x18, 0xc6, 0xe9, 0xb2, 0xc5, 0xfc, ++ 0xd6, 0xbd, 0xba, 0x6c, 0x66, 0xbc, 0x59, 0x0e, 0xf4, 0x90, 0x6d, 0x26, ++ 0xe9, 0x5e, 0x9d, 0x6e, 0x7d, 0x57, 0xc1, 0x64, 0x09, 0xcc, 0xc3, 0xd1, ++ 0x7d, 0x32, 0xe5, 0xd1, 0xe9, 0xbe, 0x08, 0xc9, 0xa7, 0x9e, 0x05, 0x1e, ++ 0x1d, 0xbf, 0xf3, 0xa1, 0x89, 0x7b, 0x7a, 0x2e, 0x71, 0x7f, 0x3c, 0xdb, ++ 0x3c, 0x4d, 0xf7, 0xeb, 0xb2, 0x87, 0xad, 0x8f, 0xdf, 0xaf, 0xb3, 0xe0, ++ 0xce, 0xce, 0xaa, 0x7a, 0xb3, 0xdc, 0xb0, 0xcd, 0xb3, 0x1e, 0xe3, 0xdb, ++ 0xb0, 0xf6, 0xd1, 0x19, 0xef, 0xd7, 0xd5, 0x71, 0x3f, 0x29, 0xdb, 0xe4, ++ 0x71, 0x88, 0xb4, 0xf1, 0xe9, 0x7e, 0xdd, 0x8e, 0xa9, 0x65, 0xb6, 0xfb, ++ 0x75, 0x34, 0x0f, 0xfa, 0x71, 0x82, 0xfe, 0xac, 0x7b, 0x76, 0x4e, 0xb8, ++ 0xce, 0xf5, 0xab, 0xc9, 0x6c, 0xa7, 0x4d, 0x08, 0xdb, 0xed, 0x88, 0x0b, ++ 0xdd, 0xaf, 0x73, 0x85, 0xec, 0xed, 0x77, 0x5c, 0x20, 0x3f, 0xeb, 0x13, ++ 0xdf, 0xaf, 0x13, 0x78, 0x18, 0xd6, 0xce, 0x61, 0x0f, 0xba, 0x2c, 0x3b, ++ 0x74, 0x94, 0xcc, 0x70, 0xff, 0xce, 0x34, 0xc8, 0xf4, 0x1d, 0x91, 0xdc, ++ 0x8f, 0x92, 0x91, 0x19, 0x12, 0xc5, 0x25, 0x48, 0xdf, 0x5b, 0x76, 0x5e, ++ 0x1e, 0x1f, 0xea, 0xbf, 0x9d, 0x9d, 0x97, 0x67, 0xe5, 0xf5, 0x3b, 0xec, ++ 0x3c, 0xcb, 0x7e, 0xcb, 0x9d, 0x6d, 0xc7, 0xb7, 0xd3, 0xee, 0x73, 0x57, ++ 0x45, 0xa8, 0xcf, 0xc5, 0xda, 0x79, 0xbb, 0xf0, 0x1f, 0x40, 0x2f, 0x0f, ++ 0x79, 0x1d, 0x76, 0x5e, 0x53, 0x66, 0xfa, 0x70, 0xca, 0x8b, 0x7c, 0x36, ++ 0xb8, 0xfb, 0x4a, 0x18, 0xe7, 0x68, 0xed, 0x8f, 0x14, 0xcc, 0x57, 0xdb, ++ 0x95, 0xcb, 0xbf, 0x7f, 0xc4, 0x86, 0xf9, 0x07, 0x6f, 0xcd, 0xa0, 0x7d, ++ 0xf1, 0xf1, 0xef, 0x1d, 0xed, 0x9a, 0xd2, 0xaf, 0xe2, 0xf7, 0x6f, 0x7e, ++ 0xb7, 0x94, 0x91, 0x9d, 0x64, 0xc5, 0x11, 0xdc, 0x02, 0xe6, 0x5d, 0x45, ++ 0xf2, 0x7a, 0x0a, 0xbb, 0x77, 0x3d, 0x44, 0xf8, 0x09, 0x0a, 0x3c, 0x34, ++ 0xe1, 0x07, 0xc8, 0x6a, 0x08, 0x57, 0xf1, 0x71, 0xc4, 0x67, 0xa6, 0x17, ++ 0xf3, 0x16, 0xf2, 0x9b, 0x18, 0x35, 0x2a, 0xac, 0x08, 0xd3, 0xbe, 0xe3, ++ 0x67, 0x09, 0x64, 0xba, 0xb4, 0x15, 0x53, 0x51, 0x8f, 0xd7, 0x23, 0x56, ++ 0xd2, 0xf0, 0x34, 0xc3, 0x63, 0xff, 0x4e, 0x40, 0xa3, 0x9e, 0xef, 0xd8, ++ 0x47, 0xfb, 0x3e, 0x9f, 0x3b, 0x07, 0x7f, 0x90, 0x7f, 0x4f, 0x61, 0x8e, ++ 0x61, 0xdf, 0x77, 0xcb, 0x4f, 0x42, 0x73, 0x16, 0xe7, 0xbb, 0xbe, 0xd2, ++ 0x4e, 0x07, 0x27, 0xa4, 0xc8, 0xa0, 0x02, 0x5d, 0x9e, 0xce, 0x2a, 0x15, ++ 0xf6, 0xcf, 0xa0, 0x8e, 0xfa, 0xb2, 0x7b, 0xad, 0x8b, 0xec, 0xc6, 0x87, ++ 0x96, 0x94, 0x6d, 0xbd, 0x12, 0xfd, 0xd5, 0xa0, 0xac, 0xf3, 0xe3, 0xc8, ++ 0xa1, 0x71, 0x68, 0x1f, 0x35, 0x1f, 0x35, 0xbd, 0x68, 0xe7, 0x6d, 0x8f, ++ 0x4c, 0xf7, 0x8e, 0x83, 0xf7, 0x0f, 0x75, 0x28, 0x61, 0x34, 0x0f, 0x9f, ++ 0x5a, 0xb2, 0xe6, 0x55, 0xac, 0xc7, 0x76, 0xbb, 0xc8, 0x0e, 0x7a, 0xaa, ++ 0x6f, 0x5e, 0xc1, 0x8a, 0x34, 0xbe, 0xdb, 0xbc, 0x7b, 0xc1, 0xc2, 0xc5, ++ 0xf8, 0xbe, 0xc3, 0x45, 0xfa, 0x7d, 0xc5, 0x9e, 0xfb, 0x06, 0x4a, 0x83, ++ 0xd8, 0xdf, 0x55, 0x9b, 0xfe, 0xbd, 0xa9, 0x96, 0x8d, 0xf7, 0xe9, 0xe8, ++ 0xb7, 0xbd, 0x51, 0xeb, 0xcd, 0x68, 0xc7, 0x5c, 0x9d, 0xc5, 0xed, 0x92, ++ 0x8d, 0x5a, 0x92, 0xe2, 0x4f, 0x1b, 0xe7, 0x69, 0x0c, 0x5d, 0xae, 0x8d, ++ 0x25, 0xf5, 0xa3, 0x57, 0xa0, 0xfd, 0x70, 0x8d, 0x96, 0xf1, 0x3e, 0xf9, ++ 0x5d, 0x59, 0x6e, 0x7e, 0x9f, 0xcf, 0xd5, 0x2a, 0xa1, 0x7c, 0x2f, 0x8c, ++ 0x66, 0xbe, 0x17, 0x60, 0xb5, 0x1b, 0x5b, 0xf3, 0x5b, 0x3a, 0xc7, 0x08, ++ 0xce, 0x96, 0x19, 0xfa, 0x71, 0xae, 0xeb, 0xe7, 0xc9, 0x58, 0x7f, 0x08, ++ 0xf6, 0x55, 0x97, 0x52, 0xf4, 0x94, 0x27, 0xe8, 0x69, 0x63, 0xd1, 0xbd, ++ 0x5b, 0x2b, 0x70, 0x7d, 0x03, 0x99, 0xef, 0x1d, 0x5a, 0xe5, 0xda, 0xac, ++ 0x71, 0x9c, 0x4e, 0x23, 0x76, 0x3e, 0x77, 0x15, 0x36, 0x8d, 0xc6, 0x75, ++ 0xbb, 0xdc, 0x91, 0x81, 0x7a, 0x24, 0xae, 0x42, 0x59, 0xc7, 0xb8, 0x88, ++ 0xcb, 0xdd, 0x1a, 0xb9, 0x19, 0xed, 0xd1, 0xab, 0x5d, 0x48, 0xe1, 0x6c, ++ 0x73, 0xc7, 0x0f, 0x1b, 0x16, 0xe1, 0xbe, 0x84, 0x25, 0x5d, 0x82, 0x79, ++ 0x82, 0x6a, 0x64, 0x15, 0xd1, 0x59, 0x30, 0x8b, 0xa1, 0x3e, 0x68, 0x58, ++ 0x12, 0x69, 0x45, 0xbc, 0x14, 0x82, 0xfe, 0xc3, 0xd0, 0x5e, 0x61, 0xd1, ++ 0x2f, 0xe9, 0x9c, 0xa2, 0xb0, 0x4e, 0x63, 0x5e, 0xa8, 0x7b, 0x96, 0xf4, ++ 0x24, 0x5c, 0xf0, 0xde, 0x53, 0x11, 0xbd, 0x0a, 0xf1, 0xfe, 0xd2, 0x5a, ++ 0xfe, 0x9d, 0x97, 0xc2, 0xa0, 0x8f, 0xee, 0x05, 0x15, 0x46, 0xf8, 0x39, ++ 0x5c, 0x61, 0xbb, 0x9b, 0xa1, 0xc9, 0xb0, 0x11, 0x5c, 0x60, 0x17, 0xf9, ++ 0x07, 0x12, 0xc5, 0x89, 0x9c, 0x7c, 0x64, 0xad, 0xab, 0x79, 0x29, 0x97, ++ 0xe3, 0xbb, 0xd7, 0xfe, 0x76, 0x54, 0xa6, 0xef, 0xcd, 0x54, 0x64, 0x95, ++ 0x11, 0x5e, 0xbd, 0x86, 0x7d, 0xdd, 0x1e, 0xd4, 0xbb, 0x30, 0xce, 0x54, ++ 0x73, 0x70, 0x09, 0xe1, 0xbb, 0xc6, 0xcd, 0xe2, 0xc4, 0xbf, 0x6e, 0xa2, ++ 0xef, 0x5d, 0xb5, 0x2e, 0x82, 0x6b, 0xd7, 0x94, 0x93, 0x5f, 0x41, 0xb8, ++ 0x7e, 0xf7, 0xfb, 0x2c, 0xda, 0xef, 0x6b, 0x99, 0x29, 0x21, 0x5c, 0xf9, ++ 0x43, 0xfc, 0x9c, 0xd5, 0x9a, 0x27, 0xbf, 0x69, 0x50, 0xe1, 0xf1, 0x70, ++ 0xce, 0x87, 0x4e, 0xbe, 0xb3, 0xf8, 0xc1, 0x09, 0xdf, 0xce, 0xd9, 0xf3, ++ 0xe8, 0x3c, 0x6e, 0x33, 0x1b, 0x9c, 0x8f, 0xf8, 0x8e, 0x9d, 0x95, 0x89, ++ 0x8e, 0x36, 0x17, 0xad, 0xf1, 0xa6, 0xc7, 0x45, 0x5b, 0x05, 0xfd, 0xc1, ++ 0x3e, 0x90, 0x7c, 0x89, 0xe9, 0x8c, 0xf6, 0x5b, 0xf9, 0x57, 0xb6, 0x1e, ++ 0xf3, 0x61, 0x37, 0x7e, 0x31, 0x52, 0x89, 0xfc, 0xf1, 0xb6, 0x97, 0xdf, ++ 0x5b, 0xbd, 0x6f, 0xa9, 0x46, 0xeb, 0x78, 0x68, 0xae, 0x46, 0xf1, 0xc6, ++ 0x87, 0xfc, 0xad, 0x44, 0xf7, 0xa7, 0x36, 0xba, 0xc2, 0x87, 0x10, 0x1c, ++ 0x55, 0x5f, 0x88, 0xfb, 0xb9, 0xbb, 0xb8, 0x22, 0x8c, 0xf1, 0xb6, 0xbf, ++ 0xc3, 0xc3, 0xe7, 0x34, 0xff, 0x60, 0xf7, 0xa8, 0x2f, 0x55, 0x22, 0x3e, ++ 0xbf, 0xf8, 0x87, 0x2c, 0x3e, 0xce, 0x14, 0xd5, 0x1a, 0xe7, 0x67, 0x44, ++ 0xef, 0xb5, 0x5e, 0x82, 0x73, 0x86, 0xd2, 0xfe, 0xb3, 0x15, 0x68, 0x87, ++ 0x2e, 0x91, 0x27, 0x53, 0xee, 0xf4, 0xaa, 0x25, 0x24, 0xbf, 0x5c, 0x42, ++ 0x8e, 0xbf, 0xbc, 0x24, 0xaf, 0x1e, 0xfd, 0x94, 0xc0, 0x0d, 0xcb, 0x19, ++ 0x97, 0x87, 0x3c, 0x4e, 0x11, 0x58, 0x5b, 0xcd, 0xef, 0x33, 0x38, 0xe4, ++ 0x7e, 0xa2, 0x4e, 0xdd, 0x3d, 0x83, 0x76, 0x89, 0xc7, 0x7f, 0xea, 0x85, ++ 0xbc, 0x1b, 0x7b, 0xc3, 0xf4, 0x7a, 0x5c, 0x67, 0xbd, 0xd0, 0x0b, 0xa6, ++ 0x9a, 0xf9, 0xbb, 0x8c, 0xb9, 0xa2, 0x7d, 0xe1, 0x50, 0x04, 0x4d, 0xb2, ++ 0x61, 0xf1, 0x9f, 0x5c, 0xa1, 0x3f, 0xc6, 0xee, 0x76, 0x3c, 0x17, 0x7a, ++ 0x21, 0x77, 0x58, 0x1c, 0x7c, 0xb0, 0xe2, 0x66, 0x90, 0x3f, 0x5f, 0xca, ++ 0x12, 0x76, 0xe4, 0x08, 0x71, 0x9f, 0x5d, 0x4b, 0xe6, 0x11, 0x3f, 0x9c, ++ 0x01, 0x7e, 0xa0, 0xb8, 0x74, 0xc9, 0x49, 0xa2, 0xff, 0x18, 0xc8, 0x09, ++ 0xb4, 0x9b, 0xdf, 0x90, 0x92, 0xa1, 0x15, 0x69, 0xe7, 0x61, 0xd6, 0x77, ++ 0xe6, 0x7e, 0x22, 0xe2, 0x41, 0x11, 0xb3, 0x94, 0xf2, 0x84, 0xdf, 0x12, ++ 0xf1, 0xa0, 0x9f, 0x8a, 0xef, 0xce, 0xbd, 0x23, 0xe2, 0x41, 0xc7, 0x45, ++ 0x3c, 0xe8, 0xe7, 0x22, 0x1e, 0xf4, 0x0f, 0x18, 0x0f, 0xc2, 0xef, 0x87, ++ 0x79, 0x2f, 0xa7, 0x7d, 0x1b, 0x57, 0xf7, 0x51, 0x3f, 0xc6, 0x71, 0x76, ++ 0xd6, 0x2c, 0xf0, 0x18, 0x30, 0xce, 0x54, 0x7d, 0xf0, 0x25, 0x04, 0xf2, ++ 0x8b, 0xe6, 0xa0, 0x4f, 0xe4, 0xdf, 0x13, 0xbc, 0x41, 0x4b, 0x0f, 0xcd, ++ 0x3d, 0x7f, 0x9c, 0x2a, 0x81, 0x70, 0xb9, 0x31, 0x2e, 0xc5, 0xe1, 0x7c, ++ 0x59, 0x7c, 0x8f, 0xee, 0x15, 0x01, 0xd7, 0x80, 0x80, 0xeb, 0x35, 0x01, ++ 0x97, 0xa5, 0x07, 0x51, 0x6e, 0x20, 0x9d, 0xb1, 0xb1, 0xaa, 0x9e, 0x49, ++ 0x1e, 0x06, 0xd5, 0x56, 0x09, 0xcf, 0x7b, 0x51, 0x5e, 0xf4, 0x07, 0x49, ++ 0x5e, 0xf0, 0x3c, 0xf1, 0xe0, 0x1a, 0xc9, 0x98, 0x30, 0x5c, 0x4e, 0xc0, ++ 0x78, 0xa3, 0xd3, 0xed, 0x74, 0x8b, 0xfe, 0x4e, 0x8d, 0xf2, 0x11, 0x1d, ++ 0x3b, 0xc7, 0x7f, 0x34, 0x8b, 0xdf, 0x3b, 0x7c, 0x69, 0xed, 0xac, 0xfd, ++ 0x2c, 0x98, 0x26, 0x8f, 0x22, 0x0b, 0x57, 0x21, 0xdd, 0xe5, 0xc3, 0xfe, ++ 0xa0, 0x3c, 0x8a, 0x36, 0x71, 0x39, 0x1e, 0xc5, 0x7b, 0x17, 0x69, 0x72, ++ 0xd5, 0x8a, 0xa7, 0xc1, 0x8e, 0x84, 0x49, 0xef, 0xdc, 0xc0, 0xf1, 0x34, ++ 0x92, 0x7c, 0xb9, 0x90, 0x5c, 0x29, 0x74, 0xc8, 0x95, 0xdd, 0x28, 0x57, ++ 0xa0, 0xbe, 0x1b, 0xe5, 0x4a, 0x30, 0x5d, 0xae, 0xb4, 0xf6, 0xe3, 0xba, ++ 0x83, 0x28, 0x57, 0x58, 0x4a, 0x0f, 0x05, 0x23, 0x9f, 0x4c, 0xae, 0xfc, ++ 0xcc, 0x5b, 0x66, 0x8b, 0x93, 0x58, 0xf2, 0xe5, 0x6a, 0x60, 0x63, 0xb2, ++ 0x13, 0xc3, 0xa0, 0x4f, 0xfd, 0x9f, 0x5e, 0x9f, 0xbe, 0x2d, 0xe4, 0xc4, ++ 0x85, 0xf4, 0xaa, 0x95, 0xff, 0x11, 0x30, 0x19, 0xe9, 0xf5, 0x3d, 0x98, ++ 0x17, 0x82, 0xfe, 0xcc, 0x78, 0x46, 0xf7, 0x70, 0x14, 0x73, 0x90, 0xf2, ++ 0x89, 0x72, 0xdb, 0x5d, 0x0c, 0xf3, 0x41, 0xb6, 0x62, 0x97, 0xd1, 0xe8, ++ 0xcf, 0x2c, 0xa4, 0x7c, 0x90, 0x1d, 0xf3, 0x3d, 0x3a, 0xd2, 0xc5, 0xc3, ++ 0x52, 0x22, 0x84, 0xf8, 0xdc, 0x27, 0xf5, 0x78, 0xf9, 0xbe, 0xe8, 0xfd, ++ 0x68, 0x2f, 0x6c, 0x9b, 0xc0, 0xe3, 0x24, 0x3b, 0xfe, 0x78, 0x8f, 0x17, ++ 0xed, 0xec, 0x97, 0x6e, 0x2f, 0x08, 0xe0, 0x39, 0x4e, 0x6f, 0xae, 0x95, ++ 0x07, 0xa2, 0x2f, 0xbe, 0x15, 0xea, 0xa7, 0x1a, 0x19, 0xd1, 0xc9, 0x8a, ++ 0x3d, 0x2b, 0x6c, 0x79, 0x0f, 0x3f, 0xcf, 0xca, 0x23, 0x7c, 0xe4, 0xc6, ++ 0x40, 0xfe, 0x00, 0x3e, 0x1e, 0xbe, 0x9d, 0xeb, 0x1f, 0xdd, 0xe0, 0x79, ++ 0x20, 0x50, 0x66, 0xcc, 0x03, 0x71, 0xfb, 0x44, 0x3c, 0x48, 0x8d, 0x85, ++ 0x90, 0x3e, 0xb6, 0x49, 0x51, 0x0f, 0xc5, 0x61, 0x1a, 0x65, 0xd2, 0x53, ++ 0xbd, 0x61, 0x9e, 0xbf, 0xd2, 0x0b, 0x7e, 0x39, 0x9e, 0x0f, 0xf6, 0x36, ++ 0xec, 0x9c, 0x83, 0xfa, 0x79, 0xc3, 0xad, 0x32, 0xa3, 0x7c, 0xf1, 0xca, ++ 0x9e, 0x7b, 0x50, 0xce, 0x74, 0x4c, 0x58, 0x68, 0x20, 0x5f, 0xba, 0x46, ++ 0x97, 0xbd, 0x89, 0xe6, 0xf8, 0x06, 0x9f, 0xec, 0x4d, 0xcf, 0x23, 0xc5, ++ 0xe3, 0x04, 0xad, 0x9a, 0x9f, 0x1b, 0x8a, 0xd2, 0xcc, 0x01, 0x90, 0x37, ++ 0x7b, 0x4d, 0xe3, 0x7c, 0xf7, 0x47, 0x55, 0xe1, 0xf7, 0x61, 0x7f, 0xf7, ++ 0x79, 0xf2, 0xe0, 0x3b, 0x73, 0x43, 0xa3, 0x31, 0x4e, 0xd0, 0xdb, 0xb8, ++ 0x30, 0x84, 0xf3, 0xf6, 0x8e, 0x8a, 0x84, 0xf2, 0x28, 0x3f, 0x65, 0x0c, ++ 0xd9, 0x03, 0x1b, 0x47, 0x6d, 0x5a, 0x8c, 0xf1, 0xa7, 0x8e, 0xe5, 0x1a, ++ 0x4b, 0xb7, 0x93, 0x86, 0xcd, 0x17, 0xb4, 0xdb, 0xd7, 0x56, 0x9c, 0x51, ++ 0x6d, 0xe0, 0xf9, 0x23, 0x1d, 0x32, 0xf7, 0x2f, 0x73, 0xc5, 0xf9, 0x34, ++ 0xf0, 0x55, 0x25, 0xe2, 0x2d, 0x7d, 0x9d, 0x08, 0xa7, 0x6a, 0xf2, 0xfc, ++ 0x11, 0x5c, 0xaf, 0xc2, 0xd7, 0x4b, 0xdf, 0x37, 0xcd, 0x6d, 0x00, 0xff, ++ 0xb0, 0x8a, 0xaf, 0x1f, 0xfd, 0x57, 0xdd, 0xa7, 0x8f, 0x46, 0xf9, 0xa1, ++ 0x36, 0xf0, 0xfc, 0x91, 0xcd, 0x7e, 0x7d, 0x31, 0xfa, 0x8d, 0x4e, 0x38, ++ 0xac, 0xf1, 0xaf, 0xcd, 0x96, 0x6c, 0xfe, 0x91, 0x6e, 0xe5, 0x2d, 0xd4, ++ 0xaf, 0xe1, 0xe7, 0x88, 0x45, 0x3c, 0x6f, 0xa1, 0xd7, 0x75, 0xfe, 0xbc, ++ 0x85, 0x0e, 0x21, 0x0f, 0x2d, 0xbf, 0x71, 0x24, 0x7c, 0xb8, 0x1c, 0xe7, ++ 0xd4, 0xbd, 0x5e, 0x7b, 0x1c, 0xd0, 0x82, 0xe7, 0x4a, 0x51, 0x3a, 0xe1, ++ 0x18, 0x29, 0x5f, 0xe0, 0xd3, 0xce, 0x7f, 0xa1, 0x75, 0x7f, 0xde, 0xf3, ++ 0x8d, 0x94, 0x47, 0xb0, 0x26, 0x5b, 0xb2, 0xdd, 0xaf, 0xc8, 0xb5, 0xf2, ++ 0x59, 0x1a, 0xd7, 0x84, 0x50, 0x4e, 0x58, 0xf0, 0x6c, 0xbe, 0x40, 0xfe, ++ 0xc8, 0xa7, 0x85, 0xab, 0xb9, 0x91, 0xb7, 0xff, 0xbc, 0xd7, 0xfb, 0x3f, ++ 0x6d, 0xdc, 0xfa, 0x6c, 0xae, 0x1f, 0x81, 0x4f, 0x07, 0xf0, 0x1e, 0x65, ++ 0xc7, 0xc4, 0x99, 0x21, 0x94, 0x43, 0xa9, 0x78, 0xcc, 0xd0, 0x40, 0x39, ++ 0xda, 0x73, 0xe2, 0x3e, 0xa3, 0x95, 0x3f, 0xe2, 0xd2, 0xf9, 0x3f, 0x55, ++ 0x95, 0x7f, 0xe7, 0x4e, 0xce, 0x2e, 0xa2, 0xef, 0x2c, 0xab, 0xd3, 0x79, ++ 0xfe, 0x08, 0xfd, 0x65, 0xc8, 0x03, 0xd9, 0xc4, 0xd8, 0x6c, 0xf4, 0x77, ++ 0x54, 0x11, 0xbf, 0x71, 0xf2, 0xe9, 0x85, 0xe0, 0x77, 0xe6, 0x8d, 0xdc, ++ 0xec, 0x13, 0x7e, 0x63, 0xd4, 0x31, 0x9f, 0xc8, 0x13, 0x61, 0x8e, 0xbc, ++ 0x13, 0x35, 0xc4, 0xf3, 0x4b, 0xac, 0x7c, 0x92, 0x2e, 0x09, 0xd6, 0x17, ++ 0x4c, 0xe5, 0x83, 0x8c, 0x38, 0xaf, 0x03, 0x6f, 0xe3, 0x85, 0xdc, 0x7f, ++ 0xcf, 0xd1, 0x7f, 0xd8, 0xba, 0xc3, 0xfc, 0x7e, 0xa5, 0x95, 0x7f, 0x32, ++ 0x2c, 0x8f, 0x64, 0xaa, 0xbc, 0x1f, 0xb7, 0x60, 0x58, 0x1e, 0x89, 0xc8, ++ 0x47, 0xe9, 0xc9, 0x35, 0xe2, 0x3c, 0x4f, 0x9c, 0xe7, 0x95, 0xa0, 0xda, ++ 0xc4, 0x78, 0xde, 0xb0, 0x3c, 0x92, 0xa9, 0xd3, 0x43, 0xf8, 0x4d, 0xc9, ++ 0x69, 0x25, 0xa2, 0xdf, 0x0d, 0x8c, 0xbe, 0xbf, 0xdb, 0xe3, 0xe5, 0xf5, ++ 0xde, 0x39, 0x2c, 0x8e, 0xdf, 0x3b, 0xeb, 0xc5, 0x3a, 0xf2, 0x53, 0x2d, ++ 0xa3, 0xbc, 0x96, 0x61, 0xf9, 0x25, 0x53, 0xd7, 0x10, 0x9e, 0x34, 0x16, ++ 0x59, 0xc6, 0xcf, 0x77, 0xf8, 0x79, 0xbf, 0x85, 0x07, 0x67, 0x7e, 0xc9, ++ 0x05, 0xe9, 0xed, 0x02, 0x79, 0x24, 0x41, 0x9f, 0xf5, 0x3d, 0x8a, 0x08, ++ 0xcd, 0xd3, 0xe3, 0x0f, 0xff, 0xa4, 0x8e, 0xe0, 0x93, 0xe9, 0x3c, 0xbe, ++ 0xe0, 0x4b, 0xc7, 0xc3, 0xe9, 0xe3, 0x5f, 0xe2, 0xe3, 0x72, 0xb2, 0x47, ++ 0xe4, 0xe1, 0xf5, 0xe4, 0xda, 0xf3, 0xf1, 0xee, 0x13, 0xfb, 0x52, 0x21, ++ 0xda, 0x39, 0xf7, 0x57, 0x2f, 0xe2, 0x74, 0xdd, 0x55, 0xaf, 0x53, 0xdc, ++ 0xdd, 0xdd, 0xc0, 0xe3, 0x95, 0xc3, 0xbe, 0x03, 0x51, 0x63, 0xf7, 0x07, ++ 0x9c, 0xf1, 0xbc, 0x13, 0x42, 0x5e, 0x5f, 0x68, 0xfd, 0xce, 0xb8, 0xde, ++ 0xb6, 0x11, 0xee, 0x9b, 0x2d, 0xf0, 0xf1, 0x3c, 0xae, 0x87, 0x96, 0x1c, ++ 0xa2, 0xbc, 0xd8, 0x33, 0xab, 0x40, 0xcf, 0x02, 0xbe, 0x1e, 0xc6, 0x7c, ++ 0x96, 0x9a, 0x8b, 0xcf, 0x67, 0x79, 0x3d, 0x8b, 0xe7, 0xb3, 0xf4, 0x1a, ++ 0xf5, 0x0b, 0x2f, 0x45, 0x3d, 0x16, 0xd5, 0x18, 0xca, 0xd3, 0x5e, 0xcc, ++ 0x67, 0x81, 0xf7, 0x1b, 0x1a, 0x46, 0xc8, 0x67, 0x11, 0xf1, 0x44, 0x2b, ++ 0x3e, 0x3a, 0x52, 0x3e, 0x4b, 0xee, 0xb9, 0xf3, 0x78, 0x7b, 0x3e, 0x4b, ++ 0xef, 0xad, 0x3c, 0x9f, 0xa5, 0xb7, 0x87, 0xcf, 0x63, 0x8d, 0xd7, 0xdb, ++ 0x50, 0x4d, 0x76, 0xd6, 0x48, 0xe3, 0x3e, 0x3d, 0xc6, 0x94, 0x7d, 0xb8, ++ 0xff, 0x15, 0x17, 0x77, 0x7e, 0x3a, 0xad, 0x24, 0xf2, 0x67, 0x98, 0xbf, ++ 0xd2, 0x53, 0xaa, 0xe9, 0x0f, 0x1a, 0x48, 0x2f, 0x9c, 0x9e, 0xbb, 0x1a, ++ 0x35, 0xa2, 0xef, 0x2e, 0x17, 0xf7, 0x63, 0x63, 0xa3, 0xb9, 0xdf, 0xcc, ++ 0xd4, 0x78, 0x68, 0x21, 0xb4, 0xd9, 0xe2, 0x4f, 0x2c, 0xa2, 0x78, 0xb2, ++ 0xc8, 0xcb, 0xe8, 0x15, 0xf7, 0xe7, 0xff, 0x3e, 0xcb, 0xb0, 0xd9, 0xc7, ++ 0x9d, 0x8d, 0xdf, 0x0d, 0xa1, 0x5d, 0x0f, 0x74, 0xf8, 0xb2, 0xce, 0xf9, ++ 0x84, 0xc6, 0xc9, 0x57, 0x4b, 0xd7, 0x83, 0x0d, 0xc8, 0xdc, 0x7a, 0x8b, ++ 0x89, 0x3e, 0xe5, 0x40, 0x36, 0x8f, 0x23, 0xb8, 0x42, 0xc7, 0x06, 0xea, ++ 0xd2, 0xe8, 0x74, 0x8b, 0xd0, 0x77, 0x88, 0x1f, 0x19, 0xf0, 0x93, 0x2b, ++ 0x9d, 0xc3, 0x57, 0x54, 0x2e, 0xa0, 0xe8, 0x3e, 0xfd, 0xad, 0x11, 0xf4, ++ 0xf9, 0x46, 0x36, 0x9f, 0xdf, 0xa2, 0x43, 0xa6, 0x4e, 0x0a, 0xf3, 0xf3, ++ 0x3f, 0x56, 0x81, 0x72, 0xc4, 0xf2, 0x5f, 0x87, 0xb5, 0xf3, 0xf0, 0x76, ++ 0xc3, 0xe4, 0x8f, 0x43, 0x8e, 0xf4, 0x60, 0x7e, 0x1b, 0x56, 0x2c, 0x79, ++ 0x72, 0x83, 0x25, 0x4f, 0xec, 0x74, 0x69, 0xc9, 0x0f, 0xe6, 0x90, 0x33, ++ 0xe7, 0xe4, 0xc9, 0x1c, 0x6e, 0xa7, 0x9f, 0x93, 0x27, 0x20, 0x3f, 0xf0, ++ 0x53, 0x67, 0x4e, 0x39, 0xd4, 0xeb, 0xe5, 0xfa, 0xc2, 0x82, 0xc7, 0x8d, ++ 0x82, 0x19, 0xe4, 0xc8, 0x7b, 0xae, 0xb0, 0x2d, 0x4e, 0xe3, 0x94, 0x3b, ++ 0x17, 0xe2, 0xa3, 0xcf, 0x5b, 0xee, 0xbc, 0x94, 0x9d, 0x2f, 0xec, 0x0f, ++ 0x2e, 0x77, 0x82, 0x48, 0x1b, 0xc8, 0x37, 0xd9, 0xd6, 0x39, 0x22, 0xbf, ++ 0xf7, 0x70, 0x66, 0xea, 0x83, 0x24, 0x0f, 0x3d, 0x2a, 0x5f, 0xb7, 0x27, ++ 0xc2, 0xe8, 0x77, 0x02, 0xb0, 0x8e, 0xf2, 0xdc, 0x83, 0xe7, 0x28, 0x19, ++ 0xe5, 0x7a, 0xb5, 0x44, 0xf1, 0x06, 0x71, 0x2e, 0x92, 0x2f, 0xbe, 0x3f, ++ 0xf8, 0xb0, 0x2b, 0x4c, 0xf9, 0x69, 0x0f, 0x03, 0x3f, 0xa3, 0x9f, 0x37, ++ 0xc1, 0x70, 0xda, 0x67, 0xe7, 0x3f, 0x57, 0x70, 0x9e, 0x27, 0x3d, 0xbc, ++ 0xf6, 0x6b, 0xdc, 0x3f, 0x03, 0x7c, 0xa3, 0xdf, 0x75, 0xb1, 0x72, 0xc8, ++ 0x92, 0x13, 0x1f, 0x66, 0xf3, 0x75, 0x9f, 0xa3, 0x2f, 0x93, 0xc3, 0x69, ++ 0xd1, 0x57, 0x1a, 0x3d, 0xd3, 0xf7, 0x05, 0x2c, 0xfa, 0xb5, 0xc6, 0xb5, ++ 0xe8, 0x98, 0x21, 0x83, 0x16, 0x9c, 0x87, 0x5e, 0x05, 0x5d, 0x63, 0x38, ++ 0x9a, 0xe2, 0xd4, 0x31, 0x29, 0x8e, 0x71, 0x10, 0x2b, 0x8f, 0xcc, 0x1a, ++ 0xef, 0x0d, 0x1f, 0xb7, 0x47, 0x46, 0xba, 0x5f, 0x65, 0xb5, 0xfb, 0x8e, ++ 0xe5, 0x77, 0x9d, 0x8b, 0x07, 0xeb, 0x01, 0x9d, 0xf2, 0xc9, 0x7a, 0xe8, ++ 0xbe, 0x39, 0xeb, 0xe2, 0xf4, 0x37, 0x87, 0xed, 0x56, 0xd7, 0x54, 0x51, ++ 0x3e, 0x81, 0xca, 0x28, 0x9f, 0x20, 0x52, 0x82, 0xfe, 0xcc, 0x61, 0x9f, ++ 0xdd, 0x2f, 0xb6, 0xf2, 0xc1, 0xa6, 0x95, 0x84, 0x43, 0x28, 0x27, 0x36, ++ 0x08, 0x3b, 0xdd, 0xca, 0x23, 0xb3, 0xf2, 0xd2, 0x0e, 0xfb, 0x72, 0xad, ++ 0x73, 0x66, 0x5b, 0x7e, 0xda, 0x86, 0x11, 0xee, 0x67, 0xbf, 0x79, 0x0e, ++ 0x3f, 0x17, 0xff, 0xfd, 0x13, 0xfc, 0x6e, 0xdb, 0x6a, 0xaf, 0xf9, 0x38, ++ 0xca, 0x45, 0xc0, 0x97, 0x29, 0xbe, 0xe7, 0x44, 0x79, 0x68, 0xd6, 0xb8, ++ 0xdf, 0x15, 0x78, 0x7a, 0xdd, 0x63, 0x3e, 0xe9, 0xfb, 0x0c, 0xf7, 0x27, ++ 0x5f, 0xcc, 0xb2, 0xe7, 0x5d, 0x75, 0xfa, 0x0c, 0x47, 0x5c, 0x80, 0xe3, ++ 0x75, 0xa2, 0x1e, 0xab, 0xa7, 0xfb, 0x78, 0x51, 0x7e, 0xaf, 0xca, 0x79, ++ 0xae, 0x3e, 0xd2, 0xfd, 0x57, 0xe7, 0xbd, 0xbd, 0x73, 0xf7, 0x5f, 0xc5, ++ 0xf9, 0x7b, 0xb3, 0x27, 0xfa, 0x32, 0xc1, 0xff, 0x22, 0xcf, 0x7f, 0xd3, ++ 0xc3, 0xd1, 0x83, 0x9d, 0xec, 0xf3, 0x5b, 0xcf, 0x01, 0xaf, 0xf9, 0x13, ++ 0x1c, 0xbf, 0x53, 0xf0, 0xf7, 0xb4, 0x20, 0xbf, 0xb7, 0xf3, 0xbe, 0x27, ++ 0xfa, 0x36, 0x3e, 0xbf, 0x8e, 0x71, 0xbf, 0xda, 0xb2, 0x73, 0x0e, 0x63, ++ 0x3b, 0xe8, 0xef, 0x7f, 0x19, 0xa4, 0x36, 0xd0, 0xcb, 0xa6, 0x5a, 0x4e, ++ 0xaf, 0x45, 0x95, 0x8c, 0xbe, 0x3f, 0x3e, 0xbd, 0x95, 0xd7, 0x77, 0x2c, ++ 0xe5, 0xdf, 0x35, 0xed, 0x7f, 0x9d, 0xdf, 0xfb, 0xd8, 0x16, 0xe5, 0xdf, ++ 0x33, 0x85, 0x7e, 0x7d, 0x32, 0xe0, 0x65, 0xc7, 0x78, 0xae, 0x0f, 0xf7, ++ 0x57, 0xf1, 0x7e, 0xfb, 0xf1, 0x7e, 0x13, 0xf2, 0x69, 0x05, 0xb7, 0xbb, ++ 0xf2, 0x30, 0x7a, 0xaf, 0xa0, 0xb8, 0x8e, 0x52, 0x39, 0xbd, 0xa6, 0xc7, ++ 0x3b, 0x01, 0xde, 0x1f, 0x58, 0x2a, 0x53, 0x5c, 0x74, 0x8f, 0xe0, 0x8b, ++ 0x00, 0x33, 0x29, 0xce, 0xb1, 0xad, 0x92, 0xcf, 0xb3, 0xab, 0x42, 0x7e, ++ 0x42, 0x7c, 0x8f, 0x66, 0xd1, 0x2d, 0x50, 0xef, 0x9c, 0xbd, 0x72, 0x32, ++ 0xde, 0x2f, 0xd9, 0x2e, 0xe2, 0x29, 0xfb, 0x16, 0xaf, 0x7c, 0x02, 0xf3, ++ 0xfa, 0x3e, 0x08, 0x94, 0x0b, 0xba, 0x4b, 0xd0, 0xbd, 0xd7, 0x9e, 0xe3, ++ 0xb7, 0x51, 0x7c, 0xe4, 0xa1, 0x25, 0x79, 0xd2, 0x4a, 0x58, 0xe3, 0xbe, ++ 0x83, 0x99, 0xf3, 0x5b, 0xaa, 0xfc, 0xaa, 0xe8, 0x17, 0x73, 0x8b, 0x78, ++ 0x92, 0x28, 0x13, 0x1a, 0x96, 0x5b, 0x4d, 0x91, 0xb7, 0xda, 0xca, 0xc4, ++ 0xf7, 0xd8, 0x63, 0x1a, 0xc6, 0x9f, 0x9e, 0x19, 0xe4, 0x79, 0xab, 0xdd, ++ 0xab, 0x9f, 0x39, 0x36, 0x13, 0xf5, 0x71, 0xa5, 0x4c, 0x79, 0x66, 0x5d, ++ 0x83, 0x47, 0xbd, 0x97, 0xe1, 0xba, 0xeb, 0x78, 0x5e, 0x4f, 0x91, 0x9a, ++ 0x90, 0xd2, 0xfd, 0x17, 0xaf, 0xdf, 0xc5, 0xed, 0xb4, 0x9a, 0xa3, 0x1e, ++ 0xa3, 0x6a, 0x78, 0xfb, 0x67, 0x06, 0x8f, 0x12, 0xdd, 0x6d, 0x07, 0xbc, ++ 0x2b, 0x69, 0xfe, 0x9f, 0x2c, 0xe0, 0xec, 0x46, 0x7f, 0x02, 0xfa, 0xed, ++ 0x75, 0xf5, 0x0c, 0xcc, 0x84, 0x76, 0x7b, 0xc7, 0xe5, 0x49, 0x31, 0x23, ++ 0xd5, 0x6e, 0xb4, 0x9f, 0xf3, 0x5f, 0xf7, 0x12, 0x59, 0x7c, 0x87, 0x9e, ++ 0xd1, 0x77, 0x1c, 0x3a, 0xcd, 0x53, 0x1e, 0x94, 0x9b, 0x9d, 0x78, 0xfe, ++ 0x01, 0xed, 0xbb, 0x6b, 0xac, 0xbc, 0xd4, 0x1e, 0xba, 0x97, 0xb5, 0x77, ++ 0xce, 0xe4, 0x39, 0x98, 0x27, 0xbe, 0xed, 0x06, 0x1e, 0x2c, 0xed, 0x0a, ++ 0x1f, 0x22, 0x3f, 0xb9, 0x67, 0x36, 0xb7, 0xcb, 0xf6, 0x4a, 0xd0, 0x0e, ++ 0xf6, 0x65, 0x5f, 0x8b, 0x76, 0x3d, 0xdd, 0x63, 0x6a, 0xe5, 0x71, 0x22, ++ 0x28, 0x33, 0xc6, 0x89, 0x7a, 0x31, 0x11, 0x18, 0xf1, 0x2a, 0xce, 0xed, ++ 0x28, 0xf5, 0x05, 0xe6, 0xed, 0x6c, 0xe8, 0x1b, 0xc0, 0x79, 0x8a, 0xea, ++ 0xf8, 0xf7, 0x2d, 0x8a, 0x6a, 0x32, 0xf7, 0x7f, 0x21, 0xe0, 0xa6, 0xfe, ++ 0xfb, 0x5c, 0x31, 0x8a, 0x7f, 0x8e, 0xb4, 0x7f, 0xff, 0xea, 0xe3, 0xf8, ++ 0xec, 0xac, 0xe2, 0xe7, 0x05, 0x8c, 0xc5, 0x29, 0x2e, 0xb5, 0x5b, 0xf8, ++ 0x5d, 0x4c, 0x8d, 0x1a, 0xe9, 0xdf, 0x09, 0x6d, 0x09, 0x70, 0xfc, 0xec, ++ 0x74, 0x31, 0x13, 0xe3, 0x65, 0xbe, 0x3a, 0x8d, 0xf4, 0xba, 0x1c, 0x36, ++ 0xc8, 0x0e, 0xf5, 0x83, 0xfd, 0x88, 0xf1, 0xb8, 0x6d, 0x52, 0x6c, 0x31, ++ 0xe6, 0x87, 0xc4, 0x26, 0x69, 0xec, 0x71, 0xc2, 0x88, 0xe9, 0x1d, 0x87, ++ 0xf1, 0xbb, 0x09, 0x79, 0x61, 0xa4, 0xbf, 0x4d, 0x52, 0x22, 0x84, 0xdf, ++ 0x55, 0x8e, 0x8d, 0xe3, 0xf1, 0xed, 0xa3, 0x91, 0x9d, 0x74, 0xef, 0xea, ++ 0x00, 0xd8, 0xd1, 0x14, 0x0e, 0x66, 0x09, 0xd2, 0x53, 0xdd, 0xd1, 0x3c, ++ 0xba, 0x0f, 0x75, 0x34, 0x52, 0x3d, 0x48, 0xfd, 0x7d, 0x15, 0xba, 0xdb, ++ 0xd2, 0x28, 0x98, 0x37, 0x4f, 0x1f, 0x8a, 0x64, 0x6c, 0xd2, 0x65, 0x9b, ++ 0xb6, 0xa2, 0x5d, 0xd3, 0x39, 0x45, 0xd6, 0x31, 0x6f, 0xb3, 0x53, 0xaa, ++ 0x8f, 0xe2, 0x78, 0xb1, 0x5c, 0x0f, 0xc5, 0x91, 0x5d, 0x53, 0xe6, 0xd1, ++ 0xfe, 0xb9, 0x46, 0xe5, 0x49, 0xe9, 0xfa, 0xe8, 0x46, 0x3f, 0xd7, 0x0b, ++ 0x27, 0x27, 0x44, 0x6e, 0xf4, 0xc3, 0xba, 0x42, 0x53, 0x4e, 0xe5, 0x62, ++ 0xdc, 0x72, 0x7b, 0xed, 0x2b, 0xfb, 0x70, 0xff, 0x1e, 0xb9, 0xdf, 0x43, ++ 0x74, 0xf4, 0x48, 0xed, 0xe0, 0xdd, 0x38, 0xcf, 0xfe, 0xb3, 0x57, 0x1d, ++ 0x8f, 0x12, 0x5f, 0xf2, 0xf3, 0xba, 0x47, 0x6b, 0x4f, 0x97, 0xa2, 0xdd, ++ 0xb3, 0xab, 0xe9, 0x54, 0x2e, 0xe2, 0xaf, 0x18, 0xe3, 0x73, 0xa0, 0x0f, ++ 0x8b, 0x2b, 0x78, 0x1c, 0x0d, 0x35, 0x20, 0xd9, 0x67, 0x6a, 0x0f, 0xbb, ++ 0x19, 0xf0, 0x58, 0xdc, 0xa6, 0x31, 0x23, 0x4d, 0x1f, 0x7b, 0x19, 0x3f, ++ 0xcf, 0xc3, 0x3f, 0xdf, 0x64, 0x92, 0x7b, 0xf4, 0xf7, 0xcc, 0xe0, 0x29, ++ 0x4f, 0x0b, 0x8e, 0xb7, 0x84, 0x25, 0x2e, 0x0d, 0xd0, 0x73, 0x0f, 0xc6, ++ 0xb3, 0x2c, 0x39, 0x53, 0x5c, 0xc7, 0x12, 0x05, 0x20, 0x0f, 0xf7, 0xaf, ++ 0x78, 0x27, 0x86, 0x79, 0x72, 0x8f, 0x4c, 0x2c, 0xa0, 0x7b, 0x94, 0x45, ++ 0xe2, 0x3d, 0x49, 0x4e, 0x18, 0xaf, 0x44, 0x8c, 0xd7, 0xff, 0xc6, 0x2b, ++ 0xeb, 0xb1, 0xdd, 0xa3, 0xd5, 0x05, 0x06, 0xca, 0x8b, 0xe2, 0x81, 0xa1, ++ 0x79, 0xa8, 0x24, 0x8a, 0xab, 0x4e, 0x53, 0x9c, 0x2d, 0x64, 0xdd, 0xff, ++ 0x88, 0x1a, 0xfb, 0x6f, 0x25, 0xfa, 0x94, 0xe9, 0x3b, 0x95, 0xc5, 0xe1, ++ 0x77, 0xfe, 0x02, 0xd7, 0x11, 0xf0, 0xf5, 0x91, 0x9e, 0x83, 0xf6, 0x14, ++ 0x37, 0x73, 0xae, 0xe3, 0xe3, 0x09, 0xe6, 0x7d, 0x88, 0xbf, 0x6f, 0x4a, ++ 0xad, 0xaf, 0x8e, 0x0b, 0xa6, 0xfc, 0x31, 0xfa, 0x43, 0x7e, 0xbc, 0x97, ++ 0xdf, 0xcb, 0x2e, 0xce, 0xfa, 0x87, 0xb9, 0x4a, 0x5a, 0xbe, 0x6d, 0x89, ++ 0x88, 0x0b, 0x6c, 0x92, 0x06, 0x67, 0x93, 0x5d, 0xfa, 0x00, 0xb7, 0xc3, ++ 0xc7, 0xb2, 0x38, 0xc9, 0xb9, 0xe2, 0xaa, 0xd8, 0xdd, 0x3c, 0xdf, 0x36, ++ 0x4a, 0xf9, 0xb6, 0xce, 0x79, 0xb7, 0xfb, 0xcf, 0xe9, 0x57, 0x89, 0xee, ++ 0x51, 0xe7, 0x37, 0x89, 0x7b, 0x25, 0xfc, 0x77, 0x6c, 0x4a, 0xc4, 0xef, ++ 0xd8, 0x38, 0xe9, 0x3e, 0x14, 0xca, 0xaf, 0xea, 0xb8, 0x2a, 0x55, 0xdf, ++ 0x17, 0x3d, 0x45, 0xf4, 0xff, 0xb4, 0x66, 0xdc, 0x95, 0xe9, 0x7b, 0x0f, ++ 0xfb, 0x84, 0x5c, 0xd8, 0x24, 0xfc, 0x31, 0x6b, 0xfc, 0xb1, 0xb9, 0x7c, ++ 0x7c, 0xab, 0xfe, 0xa8, 0xce, 0xe9, 0xf1, 0xe9, 0x97, 0xf3, 0xae, 0xaf, ++ 0x82, 0xf5, 0xfc, 0x55, 0x5b, 0xd9, 0x24, 0x8c, 0x7f, 0xee, 0x18, 0xc1, ++ 0x8f, 0x5b, 0x19, 0xe0, 0xf4, 0x97, 0x3d, 0x00, 0x16, 0x0e, 0xe8, 0x81, ++ 0xfe, 0xd7, 0x5e, 0xf3, 0x62, 0x3e, 0xcb, 0xd3, 0x32, 0x5b, 0x85, 0x72, ++ 0xaa, 0xbe, 0x2a, 0xe1, 0x49, 0x56, 0x09, 0x3c, 0xc2, 0xf8, 0xe4, 0x8b, ++ 0xc1, 0xf8, 0x07, 0xc2, 0xdf, 0xf6, 0xa0, 0x5c, 0xfa, 0x6a, 0xa0, 0x92, ++ 0xe0, 0x5a, 0x31, 0x95, 0xc7, 0x0d, 0x3a, 0xab, 0x1e, 0xa4, 0x73, 0xa0, ++ 0x90, 0xce, 0xf5, 0x0e, 0xf2, 0x27, 0xca, 0x77, 0x5f, 0x28, 0x26, 0x61, ++ 0xdc, 0x7b, 0x79, 0x0d, 0xd3, 0x0f, 0x89, 0x78, 0x4b, 0x0c, 0xf0, 0x4f, ++ 0x77, 0xe7, 0x65, 0x96, 0xca, 0xeb, 0xdf, 0x9e, 0x4b, 0x7e, 0x0e, 0xf0, ++ 0x0a, 0xbf, 0x57, 0x83, 0xb9, 0x49, 0x93, 0xc5, 0xef, 0x4f, 0x94, 0xe3, ++ 0x39, 0xd1, 0xa6, 0xbb, 0x45, 0xfe, 0xac, 0x8c, 0xf8, 0xee, 0x14, 0xf3, ++ 0x00, 0xdf, 0xd2, 0x3c, 0x07, 0x8a, 0xc4, 0x38, 0xf7, 0x71, 0xfb, 0x1f, ++ 0xfd, 0x0b, 0xec, 0x5f, 0x2e, 0xe6, 0x29, 0xaf, 0xfb, 0xee, 0xd7, 0x50, ++ 0x8f, 0x17, 0xe9, 0x9c, 0x2e, 0x52, 0xf0, 0xf5, 0x79, 0x08, 0xbe, 0x56, ++ 0x99, 0x11, 0x7c, 0x6a, 0xe2, 0x55, 0xf4, 0x43, 0xb7, 0x4f, 0x2a, 0x30, ++ 0x90, 0x6e, 0x0e, 0x84, 0xc2, 0x6f, 0x37, 0x41, 0x7d, 0xf9, 0x22, 0x95, ++ 0xe2, 0xf1, 0xe5, 0x35, 0x1c, 0x8e, 0x03, 0xad, 0x32, 0xfd, 0x1e, 0x90, ++ 0xbf, 0x4e, 0x3b, 0x48, 0xf7, 0xc7, 0x4c, 0xd0, 0x17, 0x69, 0xf8, 0x32, ++ 0xc4, 0xbc, 0x45, 0x35, 0x09, 0x09, 0xcf, 0xb5, 0x8c, 0x56, 0xbe, 0x2e, ++ 0x68, 0xe7, 0x45, 0xb9, 0x68, 0x84, 0x01, 0x1e, 0xa8, 0x1b, 0x62, 0x5d, ++ 0xe7, 0xe0, 0x9f, 0xa4, 0x11, 0xfc, 0x45, 0x9e, 0x41, 0xcc, 0x2d, 0x3a, ++ 0x87, 0x87, 0x95, 0x38, 0x1e, 0xd0, 0xef, 0xca, 0x3a, 0xde, 0xcf, 0x1f, ++ 0xea, 0xdb, 0x82, 0x72, 0x6c, 0x79, 0x1d, 0x87, 0x1b, 0xf4, 0x3b, 0xc1, ++ 0x53, 0x14, 0xd6, 0x0e, 0xa2, 0xbe, 0x2f, 0x0a, 0xf1, 0xf1, 0x96, 0x03, ++ 0x7e, 0x0e, 0x49, 0x29, 0xb8, 0xb2, 0x2d, 0xb8, 0xea, 0x64, 0xca, 0xbf, ++ 0x2a, 0xaa, 0xd1, 0x0e, 0xa2, 0x1f, 0x9c, 0x2d, 0xe0, 0x5b, 0x19, 0xe6, ++ 0xf0, 0xf4, 0xbf, 0x7e, 0x6a, 0x40, 0xe2, 0xe3, 0x19, 0x38, 0x5e, 0xb6, ++ 0x80, 0x37, 0x5b, 0xac, 0x9f, 0x12, 0x76, 0x0b, 0x84, 0x7e, 0x80, 0xf1, ++ 0x9e, 0x72, 0x25, 0xea, 0xf1, 0x5e, 0xce, 0xa9, 0x29, 0xcc, 0x38, 0xc4, ++ 0x67, 0xa3, 0x78, 0x96, 0xf5, 0x7e, 0x57, 0x2b, 0xe0, 0x01, 0xf0, 0xe3, ++ 0x17, 0xf3, 0xb0, 0xdd, 0x6e, 0xe2, 0x27, 0x58, 0x62, 0xec, 0x63, 0x99, ++ 0xff, 0x7e, 0x88, 0x91, 0x16, 0xb7, 0xa8, 0xd8, 0xad, 0xd9, 0xea, 0x7e, ++ 0xb1, 0x7f, 0xac, 0x8b, 0x3f, 0x27, 0x3f, 0x8e, 0x54, 0x22, 0xaf, 0xcb, ++ 0xc2, 0xaf, 0x5b, 0x59, 0x65, 0xef, 0xc7, 0x6a, 0xd2, 0xea, 0x65, 0x78, ++ 0xbf, 0x8c, 0xd3, 0xfb, 0xfa, 0x6b, 0xf9, 0x79, 0xc7, 0x81, 0x09, 0xdc, ++ 0x3e, 0x42, 0xbf, 0xe3, 0x1c, 0x7f, 0x23, 0x9d, 0x4f, 0x31, 0x1e, 0xeb, ++ 0x0a, 0xe2, 0x7b, 0x8d, 0xf4, 0x5d, 0x49, 0xbb, 0x7d, 0xdc, 0xe2, 0xd6, ++ 0x82, 0xe9, 0x28, 0x1f, 0x8a, 0x07, 0x1e, 0x9e, 0x27, 0xc3, 0x7a, 0x8a, ++ 0xee, 0x65, 0xb2, 0x92, 0x43, 0xf4, 0x2c, 0x9d, 0x93, 0x7f, 0x30, 0xdf, ++ 0xb7, 0xd7, 0x24, 0xe8, 0xfe, 0x6c, 0xf6, 0x40, 0x24, 0x0f, 0xe5, 0x5d, ++ 0x49, 0x6b, 0xde, 0x74, 0xfc, 0xfe, 0x5b, 0xf6, 0x40, 0x94, 0xea, 0xd9, ++ 0x03, 0xad, 0x26, 0xcf, 0x3f, 0x03, 0x17, 0x26, 0x0f, 0xf3, 0xf5, 0xd2, ++ 0xe6, 0x29, 0x45, 0x39, 0xcd, 0xf3, 0xe9, 0x58, 0xab, 0xd6, 0x87, 0x72, ++ 0xad, 0x36, 0x1d, 0x4e, 0x78, 0x5f, 0xf2, 0x72, 0xcf, 0x5c, 0xec, 0xbf, ++ 0xf9, 0xee, 0x57, 0x46, 0x23, 0xff, 0x16, 0x38, 0xfa, 0x7b, 0x72, 0xb8, ++ 0xff, 0x50, 0xfc, 0x32, 0xb4, 0x0a, 0xe0, 0xfc, 0xa7, 0xd7, 0x62, 0x7b, ++ 0x2b, 0xbe, 0x93, 0x8d, 0x10, 0xe7, 0x51, 0xf9, 0x32, 0x96, 0xc5, 0x3e, ++ 0x90, 0xc7, 0x50, 0x96, 0x88, 0xfc, 0x3b, 0x4b, 0x5e, 0x74, 0x4e, 0x78, ++ 0x67, 0x52, 0xd4, 0x27, 0xe8, 0x87, 0xf2, 0xf1, 0x58, 0x22, 0xdd, 0xce, ++ 0x77, 0x96, 0xd0, 0x7e, 0xbc, 0x68, 0x1f, 0x93, 0xce, 0xdb, 0xee, 0x34, ++ 0xb5, 0x1b, 0x29, 0xde, 0x34, 0x10, 0xe0, 0xf1, 0xa6, 0x80, 0xb0, 0x57, ++ 0x7b, 0x98, 0xb1, 0x9f, 0xf4, 0x7b, 0x0d, 0xcf, 0xf7, 0xf0, 0xe1, 0x73, ++ 0xd0, 0x1f, 0x7d, 0x35, 0x47, 0xa7, 0xd3, 0x7e, 0xf6, 0xb1, 0x30, 0xd2, ++ 0x73, 0x71, 0xdb, 0x9f, 0xdc, 0xe9, 0xf2, 0xfa, 0xe6, 0x40, 0xa9, 0xb8, ++ 0x07, 0x9d, 0x20, 0xba, 0xd7, 0x4a, 0xb2, 0xe8, 0x7c, 0x0f, 0xf8, 0x98, ++ 0xbe, 0x6f, 0x7a, 0x40, 0x6d, 0xa5, 0x73, 0xd6, 0xbe, 0x22, 0x7e, 0xae, ++ 0x79, 0x74, 0xce, 0x2b, 0x12, 0xe2, 0xb3, 0xe8, 0x39, 0x9e, 0xa7, 0x6d, ++ 0xd9, 0xcb, 0xd3, 0x6b, 0x12, 0x21, 0x7c, 0xde, 0xf5, 0x6a, 0xf4, 0x32, ++ 0xe2, 0xcf, 0x11, 0xec, 0x4f, 0xcb, 0xde, 0x74, 0xae, 0xe7, 0x92, 0xfa, ++ 0x07, 0x49, 0x1e, 0x8c, 0x8d, 0x32, 0x2f, 0x9e, 0xaf, 0xf9, 0x57, 0xab, ++ 0x94, 0xc7, 0x5a, 0x12, 0x05, 0xb8, 0xaa, 0x50, 0x2e, 0x00, 0x49, 0x17, ++ 0x02, 0xfc, 0x35, 0xb1, 0xf5, 0x48, 0x37, 0x46, 0x94, 0xd7, 0x8d, 0xd5, ++ 0xa2, 0x5c, 0x05, 0xe5, 0xd5, 0x60, 0xdf, 0xae, 0x1b, 0x28, 0xff, 0xa5, ++ 0x2b, 0x35, 0xee, 0xd6, 0x0a, 0xb0, 0x6b, 0xd1, 0x7e, 0x1a, 0xdc, 0xed, ++ 0xb9, 0x01, 0xed, 0x95, 0x56, 0xb0, 0x46, 0x0c, 0xb4, 0x17, 0x4f, 0x79, ++ 0xf0, 0x7b, 0x2a, 0xdd, 0xad, 0xd3, 0xf3, 0x11, 0xcf, 0xcf, 0x44, 0x2c, ++ 0xfb, 0x32, 0x21, 0xe1, 0xf8, 0x45, 0x3f, 0x35, 0xc9, 0x5e, 0xac, 0xd5, ++ 0x35, 0x1d, 0xe3, 0x30, 0x13, 0xdc, 0x89, 0xd1, 0xe9, 0xe7, 0x74, 0x07, ++ 0xe6, 0xbc, 0x53, 0x4d, 0xdf, 0x13, 0x9b, 0x7f, 0x71, 0xf9, 0x64, 0x23, ++ 0xe9, 0x13, 0x84, 0x45, 0x4e, 0xd3, 0x23, 0xfd, 0x55, 0x47, 0x49, 0xbf, ++ 0x3c, 0xe1, 0x1f, 0x4f, 0x7a, 0xc8, 0xd2, 0x2b, 0x96, 0x1e, 0xa1, 0x11, ++ 0x41, 0xbe, 0xdc, 0x22, 0xf8, 0xa8, 0xcb, 0x48, 0x78, 0x24, 0x92, 0x57, ++ 0xc0, 0xbb, 0x00, 0xe7, 0x2d, 0x28, 0x47, 0x80, 0x8e, 0xfd, 0x45, 0x5c, ++ 0x9e, 0x83, 0x1c, 0xe6, 0x72, 0xce, 0xd2, 0x27, 0x77, 0x73, 0xbd, 0x6f, ++ 0xc9, 0xcf, 0x0a, 0x31, 0xce, 0x2d, 0x28, 0x6f, 0xa1, 0x5f, 0x77, 0xed, ++ 0x13, 0xb9, 0x37, 0xa0, 0x5c, 0x11, 0x72, 0xd6, 0x1f, 0x32, 0x66, 0xe2, ++ 0xf9, 0x5c, 0x85, 0x90, 0xaf, 0x4c, 0x8d, 0x49, 0x38, 0xdf, 0x81, 0x29, ++ 0xfc, 0x7b, 0x95, 0x01, 0x87, 0x3c, 0xad, 0x68, 0xe5, 0xe3, 0x74, 0x85, ++ 0x18, 0xd1, 0x13, 0xe8, 0xa1, 0x83, 0x48, 0x37, 0x07, 0x8a, 0x12, 0x74, ++ 0x4f, 0xfc, 0x40, 0xeb, 0x51, 0x29, 0xfd, 0x9e, 0xa9, 0xa5, 0xef, 0x02, ++ 0xad, 0x49, 0x86, 0xfb, 0x3f, 0xae, 0x8e, 0xcb, 0xc1, 0x71, 0x42, 0xae, ++ 0x7e, 0xc7, 0x6f, 0x70, 0xfa, 0xf4, 0x70, 0xb9, 0x7a, 0x4e, 0xef, 0x09, ++ 0x79, 0xbb, 0xd5, 0x3c, 0xca, 0xc4, 0x77, 0x61, 0x33, 0xe6, 0x61, 0xfd, ++ 0xbd, 0xd0, 0xe7, 0x3d, 0x15, 0x87, 0xc8, 0x2f, 0xd8, 0x76, 0xeb, 0x29, ++ 0xc2, 0xa7, 0x15, 0x0f, 0x0d, 0x89, 0x78, 0x68, 0x77, 0xd5, 0x5b, 0xf4, ++ 0x7e, 0x7b, 0x94, 0xdf, 0x03, 0xd8, 0x65, 0x4e, 0x9f, 0x43, 0xf0, 0x47, ++ 0x96, 0x6b, 0x94, 0x7f, 0x5a, 0x73, 0x74, 0x4e, 0x19, 0xfa, 0x1b, 0x4d, ++ 0xcb, 0x35, 0xb4, 0xeb, 0x4e, 0x06, 0x0a, 0xac, 0xf3, 0x2f, 0xef, 0x42, ++ 0xb4, 0x27, 0x5b, 0x57, 0x91, 0xfd, 0xeb, 0x13, 0xfb, 0xf8, 0x50, 0x98, ++ 0x09, 0xbf, 0x53, 0x23, 0x3f, 0xeb, 0xbe, 0xa5, 0xdf, 0x1e, 0xc0, 0xfe, ++ 0x21, 0xf0, 0x8b, 0x24, 0x03, 0x1b, 0xf5, 0x79, 0xdc, 0x48, 0xe7, 0xf8, ++ 0x3d, 0x05, 0xc4, 0x77, 0x74, 0x90, 0x3a, 0xfb, 0x6a, 0x0c, 0xfa, 0x0e, ++ 0x84, 0x73, 0x1d, 0xdf, 0x0b, 0xf0, 0xef, 0xd2, 0xfa, 0xa3, 0xc9, 0x81, ++ 0x71, 0xb4, 0xaf, 0x32, 0x5d, 0xe9, 0xf1, 0xd5, 0x30, 0xf2, 0x3b, 0x97, ++ 0x83, 0x5f, 0x87, 0xc3, 0xee, 0x56, 0xc3, 0xde, 0x09, 0xf0, 0x7e, 0x77, ++ 0x93, 0xac, 0xaf, 0x67, 0xa9, 0xfe, 0xff, 0x2b, 0xc0, 0xf3, 0xd1, 0x26, ++ 0xfa, 0xf9, 0x3d, 0x85, 0x9d, 0x8b, 0x4f, 0x6f, 0xc1, 0x38, 0xdf, 0xce, ++ 0xa5, 0xe2, 0x3b, 0x67, 0x0e, 0xf8, 0xef, 0x6b, 0xec, 0xf3, 0x28, 0x34, ++ 0x0f, 0xc6, 0x04, 0x28, 0x8f, 0x39, 0xe3, 0xf7, 0xf6, 0xab, 0xfc, 0x59, ++ 0xfc, 0xfb, 0x0b, 0x35, 0x7d, 0x03, 0x68, 0xcf, 0x07, 0xaa, 0x38, 0x5c, ++ 0x2f, 0x06, 0x0c, 0x8e, 0xf7, 0x41, 0x8e, 0xc7, 0x9e, 0x88, 0x4c, 0x7c, ++ 0xb4, 0x6b, 0xb0, 0xda, 0x8b, 0xfa, 0xce, 0x69, 0x37, 0x3e, 0x92, 0xfd, ++ 0xee, 0x24, 0x9e, 0xd7, 0x62, 0xd7, 0x37, 0x17, 0xaa, 0x17, 0x3b, 0xe4, ++ 0xfe, 0x04, 0x77, 0xdf, 0x75, 0x24, 0xef, 0xbe, 0x29, 0x93, 0xbc, 0x62, ++ 0x8c, 0xcb, 0x3b, 0x89, 0xc9, 0x06, 0xfe, 0xae, 0x46, 0x4b, 0x80, 0xd3, ++ 0x53, 0x95, 0x90, 0xd7, 0x1d, 0xae, 0xc4, 0x7e, 0xcc, 0x2b, 0xe8, 0x78, ++ 0xd6, 0xc7, 0xd6, 0x1b, 0x29, 0xba, 0x28, 0x12, 0x63, 0x76, 0xb6, 0xca, ++ 0x19, 0x7f, 0x3f, 0xed, 0x50, 0x40, 0xe1, 0xfb, 0x3f, 0x7c, 0xdf, 0xb9, ++ 0xfd, 0x20, 0xf6, 0xfd, 0x49, 0x81, 0x87, 0x0b, 0xed, 0x3f, 0x86, 0x59, ++ 0xd0, 0x9e, 0xee, 0x8b, 0x6f, 0x1a, 0x73, 0x07, 0xca, 0xf1, 0x56, 0xee, ++ 0x3f, 0xf7, 0x25, 0xde, 0xa2, 0xbc, 0xa3, 0xa2, 0xd9, 0x0b, 0xc9, 0xef, ++ 0x39, 0x72, 0xf0, 0x52, 0xf2, 0x07, 0x8a, 0xaa, 0x4c, 0xdb, 0xef, 0x6b, ++ 0x66, 0x8f, 0xe0, 0xb7, 0x56, 0xe4, 0x78, 0xce, 0x1b, 0x0f, 0x18, 0x49, ++ 0x1e, 0xef, 0x5b, 0xdd, 0x41, 0x7e, 0xf6, 0xbe, 0xc1, 0xcc, 0xf7, 0x62, ++ 0x0a, 0x72, 0x78, 0x5e, 0x5a, 0x1f, 0xc8, 0x4b, 0xfc, 0xbe, 0xc9, 0x48, ++ 0xf3, 0xeb, 0x39, 0x9c, 0xff, 0xfe, 0x29, 0x20, 0xe8, 0x6e, 0xce, 0x3b, ++ 0xf4, 0xbd, 0x8c, 0x34, 0x3d, 0xfb, 0xb2, 0xd0, 0xb3, 0xa4, 0x6f, 0x8b, ++ 0x55, 0x16, 0x53, 0xd2, 0xf2, 0x1c, 0x26, 0x08, 0xfc, 0x39, 0xf5, 0x27, ++ 0x53, 0xe3, 0x9e, 0x4b, 0x6b, 0x88, 0xce, 0x09, 0x7f, 0xfb, 0xc4, 0xf9, ++ 0xc5, 0x43, 0xa6, 0x4c, 0x78, 0xb7, 0xe8, 0x1c, 0xcf, 0x0f, 0x10, 0xaf, ++ 0xb0, 0x0e, 0x53, 0xd0, 0x21, 0x9d, 0x6f, 0xf4, 0xb0, 0xb8, 0x07, 0xf9, ++ 0x26, 0xd6, 0xc4, 0xf3, 0x3c, 0x9c, 0x70, 0x4f, 0xf0, 0xcb, 0x17, 0xb5, ++ 0xbe, 0x60, 0x0e, 0xf7, 0x43, 0xce, 0xcd, 0x27, 0xfc, 0xf5, 0x89, 0x7e, ++ 0x0e, 0xf7, 0xce, 0xda, 0xfb, 0xe9, 0x9e, 0x23, 0xcc, 0x17, 0x42, 0xfa, ++ 0x90, 0x7e, 0xf0, 0x1f, 0xa7, 0xe9, 0x3e, 0xd4, 0xb3, 0x2e, 0xfa, 0x3d, ++ 0xdb, 0x19, 0xcf, 0xba, 0x12, 0x18, 0xd3, 0xba, 0xf3, 0x20, 0xff, 0xbd, ++ 0x45, 0xf9, 0x45, 0x2f, 0xc1, 0xf9, 0xcf, 0x87, 0xf9, 0xf7, 0xd5, 0x13, ++ 0x7e, 0x6e, 0x8f, 0xfd, 0x5a, 0xe7, 0xbf, 0x57, 0xf4, 0x55, 0xf7, 0x60, ++ 0xf7, 0x17, 0xa0, 0x3e, 0xf4, 0xac, 0xc2, 0xc8, 0x9e, 0x8c, 0x83, 0xe2, ++ 0x02, 0x7a, 0x3d, 0x2d, 0xe8, 0x95, 0x3d, 0xc7, 0xeb, 0x2b, 0xbd, 0xbc, ++ 0x7a, 0xe7, 0xc1, 0xfe, 0x65, 0x38, 0xde, 0xaa, 0xe7, 0x78, 0x1e, 0xe6, ++ 0x9d, 0xcf, 0xdf, 0x76, 0xe3, 0x17, 0xa0, 0x7e, 0xdb, 0x80, 0x8b, 0xee, ++ 0x0c, 0xdc, 0xf9, 0xf8, 0x7a, 0x6d, 0x0c, 0xd4, 0x6f, 0x8f, 0x4b, 0x7d, ++ 0x58, 0xff, 0xcd, 0x74, 0x46, 0xbf, 0xf7, 0x19, 0xcb, 0xd3, 0x28, 0xce, ++ 0xf5, 0x9b, 0xc0, 0x60, 0xc1, 0x02, 0xc0, 0xf7, 0x07, 0xeb, 0x3c, 0xcc, ++ 0xb8, 0x0c, 0xe3, 0xa4, 0x83, 0x05, 0xf3, 0x01, 0x0f, 0x77, 0xc4, 0x9f, ++ 0x9e, 0x89, 0xfd, 0xee, 0x78, 0x4a, 0x0a, 0x23, 0xdb, 0xce, 0x78, 0xf6, ++ 0xf1, 0x57, 0x46, 0x03, 0x5c, 0x77, 0x7e, 0x43, 0xa2, 0xfc, 0xaf, 0xaf, ++ 0x1c, 0xc9, 0xb6, 0xd9, 0x85, 0xa7, 0x61, 0x29, 0xd3, 0xe0, 0xfd, 0x9a, ++ 0x83, 0xfc, 0x77, 0x23, 0x6f, 0x63, 0x3d, 0x33, 0x11, 0x1f, 0x77, 0x3e, ++ 0xde, 0x4b, 0xbf, 0x7f, 0x68, 0xe1, 0xf3, 0x83, 0x75, 0x95, 0xcc, 0x48, ++ 0xfb, 0xdd, 0xb0, 0x3b, 0xbf, 0xf1, 0x34, 0xfd, 0x9e, 0xe1, 0x5d, 0xdf, ++ 0x92, 0xe8, 0xf7, 0x15, 0xef, 0x92, 0xf9, 0x3d, 0xa2, 0x7f, 0x7e, 0xde, ++ 0xbb, 0xe8, 0x31, 0x1f, 0xae, 0x6f, 0xbd, 0x76, 0xa9, 0x1f, 0xd7, 0xb5, ++ 0x59, 0xc3, 0x76, 0xb7, 0xc5, 0x5b, 0xbe, 0x8b, 0x29, 0x4d, 0x77, 0xc4, ++ 0x0f, 0x6a, 0x33, 0xe1, 0xfd, 0x1d, 0x07, 0x0e, 0x6a, 0x2b, 0xd1, 0x2f, ++ 0x73, 0xb3, 0x66, 0xd4, 0x3f, 0x5f, 0x39, 0x72, 0x85, 0x4d, 0xee, 0x9c, ++ 0xde, 0xa7, 0x90, 0x7f, 0xb0, 0x26, 0xd7, 0x43, 0xf7, 0xeb, 0x99, 0xcf, ++ 0x0c, 0xcd, 0x9b, 0x30, 0x7c, 0x9f, 0x3f, 0x58, 0xc7, 0x6c, 0x70, 0xdd, ++ 0x61, 0xc5, 0x09, 0xd4, 0xb8, 0x36, 0x37, 0xad, 0xbd, 0x4b, 0xe7, 0xfe, ++ 0xef, 0x57, 0x8e, 0x28, 0xb6, 0x79, 0x2c, 0x3b, 0x20, 0x76, 0x8c, 0xeb, ++ 0x85, 0xd8, 0xdf, 0xfa, 0x29, 0x7e, 0x6e, 0xed, 0xdf, 0x1a, 0xe1, 0x77, ++ 0x5b, 0xfb, 0xb7, 0xc6, 0x0a, 0xc4, 0xab, 0x43, 0x93, 0x33, 0xc1, 0xd3, ++ 0x8d, 0xfb, 0x01, 0xf0, 0xf4, 0xac, 0xd3, 0xa9, 0xdc, 0xb9, 0x2e, 0x44, ++ 0xe5, 0xee, 0x75, 0x06, 0xed, 0xd3, 0x5e, 0xc4, 0x23, 0x94, 0x5d, 0x02, ++ 0xee, 0xc0, 0x54, 0x56, 0x8f, 0xdf, 0xe7, 0x0f, 0x98, 0x3c, 0xed, 0x38, ++ 0xaf, 0xc9, 0xac, 0xc7, 0xbb, 0x65, 0x79, 0x11, 0x5e, 0x2f, 0x58, 0x12, ++ 0x25, 0x3f, 0x64, 0x24, 0x3b, 0xc6, 0x2a, 0xf7, 0xba, 0xa2, 0x2d, 0xe8, ++ 0x43, 0x76, 0xee, 0xe8, 0x9f, 0xa5, 0x82, 0xdd, 0xb3, 0x57, 0x8b, 0xde, ++ 0x8d, 0x91, 0x2f, 0xbd, 0xe3, 0xd5, 0x59, 0x0d, 0x50, 0xff, 0x9b, 0x9c, ++ 0xc8, 0xc6, 0x1c, 0x92, 0x37, 0x61, 0x03, 0xf9, 0xce, 0xf2, 0xcf, 0xbf, ++ 0x9e, 0xc3, 0xe5, 0xee, 0xa6, 0xd1, 0x1a, 0xe1, 0x7b, 0xef, 0xd2, 0xc9, ++ 0x8f, 0x29, 0x96, 0xff, 0x85, 0x71, 0xbf, 0xa5, 0x2b, 0x9f, 0x40, 0x7b, ++ 0x02, 0xfa, 0x6f, 0xcf, 0x21, 0xbe, 0x0d, 0xd3, 0x77, 0xba, 0x46, 0xea, ++ 0x5f, 0xb0, 0xac, 0xce, 0xd6, 0xbf, 0x60, 0xd9, 0x2a, 0xab, 0xff, 0x1e, ++ 0xea, 0xef, 0x39, 0x7f, 0xff, 0xbd, 0xcb, 0xae, 0xb1, 0xcf, 0xbf, 0xec, ++ 0x0e, 0xab, 0xff, 0x23, 0x04, 0xbf, 0xef, 0xfc, 0xf0, 0x17, 0x34, 0x4f, ++ 0xb5, 0xcf, 0xdf, 0xbc, 0x9a, 0xfa, 0x7f, 0xd5, 0xcd, 0xf7, 0x77, 0x28, ++ 0xd7, 0x43, 0xf9, 0xf4, 0x1d, 0xde, 0x70, 0xc2, 0x45, 0xfe, 0x33, 0xa3, ++ 0xef, 0x73, 0xa8, 0x79, 0x97, 0x1e, 0xa2, 0xef, 0x27, 0x9d, 0x8b, 0x33, ++ 0x0d, 0x9a, 0xa8, 0x67, 0x7d, 0x4f, 0xe5, 0x56, 0xa3, 0x1c, 0x4b, 0xd1, ++ 0xd1, 0xf4, 0x6f, 0xe2, 0x3a, 0xfc, 0xc0, 0x5d, 0xe9, 0x74, 0x94, 0x53, ++ 0x97, 0x65, 0xe3, 0xab, 0x5c, 0x33, 0xcf, 0x56, 0xcf, 0x9f, 0x3d, 0xc6, ++ 0xd6, 0x7e, 0x54, 0xa4, 0xcc, 0xf6, 0xbe, 0x70, 0xd1, 0xe5, 0x0e, 0xba, ++ 0xf4, 0xe9, 0x94, 0x07, 0xcb, 0xb8, 0x3e, 0x35, 0x31, 0xce, 0x09, 0x70, ++ 0x6a, 0x63, 0xf8, 0xf7, 0x9a, 0xea, 0xc7, 0x78, 0x68, 0x7d, 0xf7, 0xbf, ++ 0xe8, 0xa5, 0xfa, 0xfd, 0xd7, 0xf0, 0xf5, 0xdd, 0x3f, 0xc6, 0x47, 0x7c, ++ 0x4c, 0xba, 0x0b, 0xf6, 0xfd, 0x7e, 0x2d, 0x7a, 0x65, 0xba, 0x7d, 0x0c, ++ 0xeb, 0x92, 0x30, 0xe4, 0xf5, 0x8c, 0x1e, 0x1d, 0xc8, 0xa9, 0x4d, 0x7f, ++ 0x6e, 0xc8, 0xf8, 0x3c, 0x4b, 0xe1, 0xbf, 0x63, 0x97, 0xe5, 0xe6, 0xfa, ++ 0x72, 0x73, 0xe9, 0xe4, 0xc7, 0x62, 0x69, 0xf8, 0xdc, 0x52, 0x0c, 0xf4, ++ 0x00, 0xf5, 0xb7, 0x73, 0x34, 0x5b, 0x9c, 0x67, 0x73, 0xf1, 0xca, 0x50, ++ 0x4b, 0xda, 0x3c, 0x9b, 0x8a, 0xb5, 0x45, 0x87, 0xaa, 0xf8, 0xf3, 0x5b, ++ 0xd0, 0x8e, 0xd7, 0x23, 0x7f, 0x87, 0xf3, 0x7d, 0x55, 0x1b, 0xba, 0x14, ++ 0xed, 0x57, 0xe7, 0x3c, 0xee, 0xb2, 0x3a, 0xdb, 0x3c, 0x9e, 0x92, 0x55, ++ 0x34, 0x4f, 0xd2, 0x31, 0x8f, 0xbb, 0x64, 0x95, 0x63, 0x1e, 0xcf, 0xa2, ++ 0x43, 0xe2, 0xb9, 0x98, 0xe7, 0x14, 0xd2, 0xc9, 0x48, 0xf3, 0x6c, 0x2e, ++ 0xbb, 0xc6, 0xbe, 0x9e, 0x92, 0x3b, 0x68, 0x9e, 0x5f, 0xe3, 0x3c, 0xb5, ++ 0x69, 0xeb, 0x29, 0xb9, 0xc3, 0x31, 0x4f, 0x16, 0x5f, 0x0f, 0x3c, 0x17, ++ 0xf3, 0xfc, 0xe6, 0xbc, 0xeb, 0x29, 0x9f, 0x6a, 0x5f, 0xcf, 0xd8, 0xd5, ++ 0x34, 0xcf, 0xbf, 0x3b, 0xe6, 0x71, 0x8f, 0x5d, 0xed, 0x98, 0xc7, 0x47, ++ 0xf3, 0xe0, 0x73, 0x9c, 0x87, 0x15, 0x71, 0x3f, 0x4a, 0x73, 0x0f, 0xad, ++ 0xa4, 0xfd, 0xff, 0x81, 0x97, 0x61, 0x1c, 0x48, 0x73, 0x47, 0xff, 0x9a, ++ 0x2e, 0xa9, 0xfc, 0xbd, 0x97, 0xe2, 0xc2, 0xd0, 0xca, 0xc4, 0x76, 0xff, ++ 0x07, 0xfe, 0x22, 0x63, 0x96, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xe5, 0x7d, ++ 0x09, 0x78, 0x54, 0x45, 0xb6, 0x70, 0xdd, 0xbe, 0x4b, 0x77, 0x27, 0xdd, ++ 0x9d, 0xce, 0xbe, 0x10, 0xc2, 0x0d, 0x28, 0x8b, 0x86, 0xd8, 0x81, 0x90, ++ 0x01, 0x5c, 0xa6, 0x59, 0xe4, 0xa1, 0x22, 0x06, 0x57, 0x70, 0x81, 0x0e, ++ 0x4b, 0xf6, 0xa4, 0xa3, 0xe2, 0x3c, 0x1c, 0x75, 0xd2, 0x10, 0x45, 0x54, ++ 0xd4, 0x46, 0x51, 0x83, 0x06, 0xa6, 0xc1, 0xa0, 0xe0, 0x80, 0x06, 0x26, ++ 0x68, 0x80, 0x80, 0x0d, 0xa8, 0x83, 0x33, 0x2e, 0x71, 0x9e, 0xe3, 0x32, ++ 0x0b, 0x36, 0x88, 0x04, 0x21, 0x26, 0x0d, 0xa2, 0xe2, 0x9b, 0xc5, 0xbf, ++ 0xce, 0xa9, 0xba, 0xe9, 0x7b, 0x3b, 0x1d, 0x60, 0xde, 0xcc, 0xff, 0xbf, ++ 0x79, 0xef, 0x8f, 0xdf, 0x4c, 0x51, 0xb7, 0xea, 0xd6, 0xad, 0x3a, 0xfb, ++ 0x39, 0x75, 0xaa, 0x9a, 0x0c, 0x4f, 0x22, 0x64, 0x1c, 0x21, 0xfb, 0x12, ++ 0x68, 0x39, 0x86, 0x90, 0x6f, 0xe3, 0x3c, 0x17, 0x39, 0x6d, 0x84, 0xfc, ++ 0x00, 0x7f, 0x3f, 0x26, 0xf4, 0xcf, 0x47, 0x48, 0x2a, 0x2f, 0xd3, 0x08, ++ 0x59, 0x40, 0xf8, 0x5f, 0x60, 0xa9, 0x40, 0x8a, 0x08, 0xa9, 0xb5, 0xb0, ++ 0xea, 0xfc, 0x4d, 0x33, 0x72, 0x16, 0x43, 0xd9, 0x36, 0x29, 0xa3, 0xa4, ++ 0x90, 0xfe, 0x63, 0xa5, 0xdd, 0x75, 0xbe, 0x4a, 0x48, 0x77, 0xdb, 0x24, ++ 0x65, 0x5e, 0x5e, 0x64, 0x3c, 0xad, 0x5c, 0xe0, 0x97, 0x8f, 0x84, 0x86, ++ 0xb3, 0x77, 0x7f, 0x20, 0x91, 0xef, 0xf8, 0x26, 0x92, 0xe1, 0x75, 0xf4, ++ 0xfb, 0x65, 0x09, 0x4e, 0x9c, 0x8f, 0x56, 0x3f, 0x52, 0x4f, 0xeb, 0x66, ++ 0x42, 0x0e, 0xd5, 0x13, 0x2c, 0x3b, 0x65, 0x32, 0xa7, 0x98, 0x3e, 0x3f, ++ 0x5c, 0x4f, 0x27, 0x30, 0x4c, 0x3f, 0xdf, 0xc5, 0xf8, 0xde, 0x11, 0x89, ++ 0xfe, 0x33, 0x85, 0x96, 0x4d, 0x42, 0xc0, 0x27, 0xd0, 0x75, 0xad, 0xf8, ++ 0x40, 0x26, 0x43, 0xf0, 0x33, 0x1f, 0x0e, 0xa7, 0xeb, 0xb8, 0x91, 0x2f, ++ 0x63, 0x81, 0x3f, 0x9e, 0x10, 0x4b, 0x64, 0x1e, 0x5e, 0x33, 0x71, 0xc3, ++ 0x7b, 0xe1, 0xed, 0xe6, 0xc0, 0x3a, 0x01, 0x9e, 0xba, 0x07, 0x98, 0x32, ++ 0x68, 0xd1, 0x98, 0x4c, 0x88, 0x36, 0xdf, 0xc1, 0x84, 0xfc, 0x69, 0xf7, ++ 0xd5, 0x6f, 0x09, 0x0e, 0xac, 0x0e, 0x30, 0x8d, 0x25, 0xe4, 0xe6, 0x65, ++ 0x5b, 0xde, 0x84, 0x6e, 0x1f, 0x09, 0x25, 0x03, 0xef, 0xa0, 0xeb, 0x9d, ++ 0xd9, 0xba, 0x42, 0x1e, 0x40, 0xeb, 0xdd, 0x72, 0x68, 0xb6, 0xcb, 0xa6, ++ 0x1b, 0x67, 0xa6, 0x7c, 0x08, 0xd6, 0x6d, 0xa1, 0xff, 0xc1, 0x38, 0xb3, ++ 0x3c, 0xb4, 0xae, 0xfb, 0xfe, 0x2d, 0xe5, 0xc6, 0xfa, 0x6d, 0x44, 0x8a, ++ 0xd4, 0x73, 0x09, 0xb9, 0xd0, 0x39, 0x98, 0xe3, 0x83, 0x7f, 0x57, 0x0d, ++ 0xc8, 0x80, 0xaf, 0x1b, 0xe9, 0x9a, 0x32, 0x29, 0x0a, 0x6f, 0x83, 0x72, ++ 0x14, 0x34, 0x3b, 0x11, 0x5f, 0xb3, 0x9d, 0xec, 0x5d, 0x6d, 0x3e, 0xde, ++ 0x7b, 0x64, 0x12, 0x84, 0xf9, 0x48, 0xa1, 0x54, 0x92, 0x07, 0x2d, 0xa9, ++ 0xd8, 0xcf, 0x03, 0xfd, 0xd4, 0xbe, 0xf3, 0x9b, 0x2d, 0x5b, 0xdc, 0xc5, ++ 0x14, 0x9f, 0xb3, 0xef, 0x16, 0x11, 0x8e, 0xd1, 0xf3, 0x0d, 0xed, 0x8e, ++ 0x77, 0x9b, 0xf2, 0x69, 0xd9, 0xf8, 0xb5, 0x4c, 0x06, 0x9f, 0x7d, 0xfe, ++ 0x73, 0x16, 0x19, 0xdb, 0x89, 0x8f, 0x7d, 0x4f, 0x83, 0xab, 0x46, 0x07, ++ 0x37, 0xcd, 0x9c, 0xf0, 0xe4, 0x61, 0x1d, 0x7d, 0xcc, 0xf2, 0x5c, 0xf1, ++ 0xe4, 0x61, 0x03, 0x9c, 0x66, 0x18, 0xea, 0xb7, 0xd5, 0xcd, 0x32, 0xf4, ++ 0x9f, 0xb3, 0xa8, 0xc4, 0xd0, 0x5e, 0xe2, 0xab, 0x30, 0xb4, 0xcf, 0x5b, ++ 0x76, 0xbb, 0xa1, 0xbe, 0xc0, 0x7f, 0xb7, 0xa1, 0x7f, 0x59, 0xe3, 0x62, ++ 0x43, 0x7b, 0x45, 0xe0, 0x21, 0x43, 0x7b, 0xd5, 0x86, 0x15, 0x86, 0x7a, ++ 0x4d, 0xcb, 0x2a, 0x43, 0x7f, 0x6f, 0xdb, 0x5a, 0x43, 0xbb, 0x69, 0xf7, ++ 0x88, 0x6b, 0x08, 0x85, 0x63, 0xc3, 0xef, 0x44, 0x62, 0xa6, 0x70, 0xfc, ++ 0xc6, 0x76, 0xe4, 0xb1, 0x8b, 0x53, 0xa0, 0x94, 0x5c, 0x00, 0xf7, 0xa3, ++ 0xf5, 0x19, 0x48, 0xd7, 0xc7, 0xea, 0x55, 0x2c, 0x6b, 0x81, 0xf6, 0xc6, ++ 0x01, 0xff, 0x8c, 0xb6, 0x78, 0x28, 0x9e, 0xbc, 0x71, 0xe1, 0x52, 0x92, ++ 0x48, 0xc8, 0x7d, 0xfe, 0x4b, 0x96, 0x2d, 0xbb, 0x84, 0xd6, 0x15, 0xda, ++ 0x3e, 0x9e, 0x52, 0xbb, 0x7f, 0xe2, 0x32, 0x5f, 0x36, 0x21, 0xcb, 0x9c, ++ 0x2a, 0xd2, 0xbd, 0xd8, 0xa8, 0x90, 0x20, 0x25, 0x55, 0x81, 0x24, 0xf5, ++ 0xd2, 0x75, 0x58, 0xd4, 0xb5, 0x87, 0xce, 0xd2, 0xde, 0x28, 0x91, 0xe0, ++ 0xe8, 0xbe, 0xed, 0x62, 0x28, 0xf6, 0xf3, 0x1e, 0x21, 0x3c, 0x34, 0x8b, ++ 0xae, 0xc3, 0xf7, 0xa9, 0x99, 0xac, 0x17, 0xfa, 0xf2, 0x79, 0x84, 0x2f, ++ 0xc9, 0x00, 0x92, 0xd1, 0x7f, 0x7b, 0x97, 0x89, 0x94, 0xb7, 0xe8, 0xe4, ++ 0xce, 0x7a, 0xa7, 0x09, 0xe7, 0x93, 0xea, 0x9c, 0xb8, 0xde, 0x49, 0xe9, ++ 0xa1, 0x5a, 0x61, 0xfc, 0x5e, 0xbd, 0x35, 0x73, 0x22, 0x71, 0x40, 0x3d, ++ 0x38, 0xb4, 0xce, 0x76, 0x86, 0xef, 0xb5, 0xd0, 0xc9, 0xa4, 0xc3, 0x38, ++ 0x8c, 0x5f, 0x2a, 0x02, 0x03, 0x22, 0xfc, 0x8b, 0xf8, 0x1b, 0x62, 0xe0, ++ 0xfb, 0x61, 0x09, 0x9e, 0x66, 0x27, 0xfd, 0x5e, 0xd7, 0x1e, 0x71, 0x26, ++ 0xcc, 0x83, 0x04, 0xf7, 0xe5, 0x5c, 0x37, 0x12, 0xbe, 0xef, 0x5e, 0x0f, ++ 0xcf, 0x49, 0x1b, 0x1d, 0x24, 0x93, 0xf2, 0x77, 0xbd, 0xfb, 0xc9, 0xc3, ++ 0xe7, 0x13, 0xf2, 0x49, 0xfd, 0x54, 0x2c, 0x7f, 0x5f, 0x5f, 0xfc, 0xe4, ++ 0x61, 0x99, 0x90, 0x3f, 0xd6, 0xcf, 0xc4, 0xfa, 0x81, 0x7a, 0x0f, 0x96, ++ 0xa1, 0xfa, 0x72, 0x2c, 0x0f, 0xd5, 0xd7, 0x61, 0xfb, 0xe1, 0xfa, 0x45, ++ 0x58, 0x3f, 0x52, 0xef, 0xc3, 0xf2, 0x68, 0xfd, 0x32, 0x2c, 0x8f, 0xd5, ++ 0xfb, 0xb1, 0xbd, 0xab, 0xbe, 0x11, 0xeb, 0xdd, 0xf5, 0x01, 0x2c, 0x35, ++ 0x3e, 0xa0, 0xf2, 0x68, 0x4e, 0x31, 0xf0, 0x69, 0x71, 0xb1, 0x09, 0xf8, ++ 0xf4, 0x0e, 0x2b, 0xe1, 0x7f, 0xac, 0x7e, 0x92, 0xaf, 0x41, 0xa4, 0xff, ++ 0xee, 0x40, 0xbe, 0x76, 0x65, 0x00, 0x5f, 0x9f, 0xb4, 0x7d, 0x3b, 0x34, ++ 0x8b, 0xd2, 0xdb, 0xc9, 0x4f, 0x28, 0x31, 0xe5, 0xf6, 0x0f, 0xa7, 0x68, ++ 0xba, 0xeb, 0x1f, 0x7f, 0x6e, 0x13, 0xe0, 0xaf, 0x34, 0x40, 0x89, 0x27, ++ 0xb9, 0x6f, 0xbb, 0x35, 0x8e, 0xe1, 0xc7, 0x6a, 0x22, 0x53, 0x09, 0x95, ++ 0x3f, 0x0f, 0x9d, 0xaf, 0x10, 0x89, 0x7e, 0x3f, 0xee, 0xf5, 0x0b, 0xd7, ++ 0x89, 0xb9, 0xf8, 0x5c, 0x02, 0xd2, 0xa1, 0x8a, 0xc3, 0x35, 0xc3, 0x1e, ++ 0x63, 0xfc, 0xf3, 0x08, 0xe2, 0xeb, 0x6c, 0x78, 0xd2, 0xfa, 0x1f, 0x79, ++ 0xf6, 0xcf, 0x45, 0x73, 0xf3, 0x00, 0x3f, 0x83, 0x91, 0x4e, 0xe2, 0xf6, ++ 0x89, 0x75, 0x0c, 0x6f, 0xcf, 0xbb, 0x00, 0x6f, 0x67, 0x83, 0x9f, 0xc4, ++ 0xf9, 0x2b, 0x1a, 0x8e, 0xc2, 0xeb, 0x7f, 0xca, 0x09, 0xd1, 0xfe, 0x5f, ++ 0xa5, 0x6a, 0xf0, 0xec, 0xc8, 0x21, 0xb4, 0xbc, 0xce, 0x59, 0x7c, 0x14, ++ 0xe8, 0xe0, 0x64, 0xab, 0x19, 0xd7, 0x75, 0xb2, 0x3d, 0x3e, 0x40, 0x60, ++ 0x0c, 0x67, 0x0a, 0xd2, 0x45, 0xff, 0x70, 0x63, 0xf3, 0xa8, 0xda, 0x60, ++ 0xf5, 0xeb, 0xe5, 0x43, 0x4d, 0x4b, 0xa2, 0xdf, 0x28, 0x2f, 0x32, 0xfd, ++ 0x7a, 0x79, 0x71, 0x72, 0xff, 0xf3, 0x0e, 0xe0, 0xfb, 0x3b, 0x32, 0x44, ++ 0xff, 0xe1, 0xd1, 0x40, 0x1f, 0x6e, 0x4e, 0x1f, 0x8c, 0xee, 0xb4, 0xf1, ++ 0x6b, 0x5a, 0x72, 0xfd, 0x36, 0xc3, 0x38, 0xc6, 0xfa, 0x49, 0xbf, 0x30, ++ 0xb5, 0x05, 0xe5, 0xbc, 0x9a, 0x70, 0xfd, 0xc8, 0xfe, 0xe7, 0x79, 0x47, ++ 0x86, 0x82, 0xdf, 0x39, 0xb6, 0x61, 0x48, 0x02, 0x7c, 0xf7, 0x58, 0xbd, ++ 0xc5, 0x0f, 0xdf, 0xe9, 0xaa, 0x77, 0xfa, 0xd9, 0x77, 0x33, 0xfc, 0x7a, ++ 0xba, 0xac, 0x5e, 0x14, 0xef, 0x3f, 0x9c, 0x1c, 0x99, 0x5f, 0x7f, 0xe3, ++ 0xfe, 0xb3, 0xe7, 0x47, 0x48, 0x2b, 0xf9, 0xdc, 0x42, 0x10, 0xf4, 0x3f, ++ 0x0c, 0xe9, 0xbf, 0x7f, 0xbf, 0xf8, 0x90, 0x4e, 0x29, 0xc5, 0x40, 0x1f, ++ 0xed, 0xf2, 0xb7, 0xa0, 0x77, 0xe2, 0x86, 0x6b, 0x7a, 0x47, 0xc2, 0xba, ++ 0x36, 0xae, 0xb7, 0x45, 0xf4, 0x99, 0x2f, 0x82, 0xe7, 0x9b, 0x0c, 0xdf, ++ 0xa3, 0xef, 0xa9, 0x47, 0x34, 0x3c, 0x0d, 0x3e, 0x13, 0xde, 0x25, 0x72, ++ 0x44, 0x5b, 0x27, 0x95, 0x93, 0x23, 0xa9, 0xec, 0x06, 0x3a, 0xa5, 0xc4, ++ 0x8c, 0x78, 0xf6, 0xd0, 0x11, 0x13, 0xe8, 0x78, 0x3d, 0x92, 0x6d, 0x99, ++ 0x40, 0xbf, 0x63, 0x4e, 0x54, 0xb1, 0xdd, 0x0b, 0x1f, 0xa2, 0xf4, 0x54, ++ 0x63, 0x09, 0x29, 0x1e, 0x15, 0xc1, 0xdd, 0x01, 0x76, 0xd6, 0xdc, 0xb1, ++ 0x1a, 0xdf, 0xab, 0x37, 0xfd, 0x81, 0x92, 0xdc, 0x97, 0xbf, 0x91, 0xc9, ++ 0xc3, 0xd0, 0xfe, 0x17, 0x3a, 0x3a, 0x6d, 0x97, 0x79, 0xeb, 0x7c, 0x52, ++ 0xec, 0x20, 0xf4, 0x7b, 0x73, 0x5b, 0xab, 0xa6, 0x81, 0x9c, 0xfc, 0xf2, ++ 0xd5, 0xab, 0xb8, 0x9d, 0xe2, 0x2f, 0x82, 0x75, 0x7f, 0x45, 0x4c, 0x53, ++ 0x81, 0x4f, 0xbe, 0x22, 0xbf, 0x75, 0x8c, 0xd6, 0xd9, 0x65, 0xd3, 0x13, ++ 0x15, 0x36, 0xbf, 0x65, 0x4c, 0x3f, 0xfb, 0xe8, 0x7f, 0xb0, 0x3e, 0x6a, ++ 0xa7, 0x19, 0xf4, 0x75, 0x59, 0xa3, 0xb1, 0x5e, 0x4a, 0xae, 0x4d, 0x03, ++ 0x7e, 0x28, 0x5d, 0x29, 0x93, 0x00, 0x9d, 0x7b, 0x05, 0xe8, 0x7b, 0x6d, ++ 0xdd, 0x94, 0xef, 0x2f, 0x4b, 0x64, 0x76, 0x5c, 0x19, 0xa9, 0x5b, 0x0a, ++ 0x76, 0xca, 0xc3, 0x32, 0x99, 0x09, 0xf8, 0x9e, 0xeb, 0x24, 0xd2, 0x00, ++ 0x2a, 0x27, 0x6a, 0x5e, 0x5b, 0x5d, 0x54, 0x42, 0xeb, 0x37, 0x24, 0x9a, ++ 0x90, 0xae, 0x8e, 0x51, 0xfb, 0x4e, 0xa5, 0x72, 0xa8, 0x22, 0x89, 0xd9, ++ 0x31, 0x95, 0x29, 0x01, 0xc5, 0x4d, 0xdb, 0x3f, 0x6f, 0x1d, 0x7d, 0xe3, ++ 0xc5, 0x04, 0xde, 0x0f, 0x2c, 0x05, 0xb9, 0xe6, 0xb3, 0x13, 0xd7, 0x7a, ++ 0xd2, 0x17, 0xee, 0xf3, 0x96, 0x19, 0xe7, 0x77, 0xb6, 0xf9, 0x47, 0xcf, ++ 0x97, 0x90, 0x25, 0x38, 0x5f, 0x6d, 0x1e, 0xda, 0xb8, 0xda, 0x3c, 0xc4, ++ 0x0d, 0x82, 0x3b, 0x10, 0xc3, 0x9e, 0x9d, 0x97, 0x28, 0x44, 0xec, 0x64, ++ 0x5a, 0xde, 0x99, 0x68, 0xb4, 0x5f, 0x17, 0x41, 0x5d, 0x67, 0xdf, 0xde, ++ 0x17, 0x55, 0x5f, 0x12, 0x55, 0xd7, 0xe8, 0x44, 0xe6, 0x74, 0x62, 0x4e, ++ 0xf4, 0x2c, 0x4a, 0x4c, 0x05, 0xba, 0x08, 0x4f, 0x41, 0x3b, 0x8d, 0x50, ++ 0xfa, 0xc8, 0x8b, 0xf4, 0x53, 0x22, 0xfd, 0xee, 0x3b, 0x53, 0x3f, 0x33, ++ 0xf4, 0x13, 0xb1, 0xdf, 0x92, 0x33, 0xf5, 0xb3, 0x46, 0xc6, 0x7b, 0x30, ++ 0x56, 0xbf, 0x9a, 0xd7, 0x36, 0xbf, 0xea, 0xa3, 0xf4, 0x54, 0xf9, 0xca, ++ 0x53, 0x0e, 0x42, 0xe5, 0xf9, 0x97, 0x92, 0x3f, 0xcd, 0x45, 0x9f, 0x57, ++ 0xaf, 0x7f, 0xc0, 0x01, 0x70, 0x3a, 0x2a, 0xf9, 0x1c, 0x80, 0xef, 0x2f, ++ 0x03, 0xe2, 0xd4, 0x58, 0xf0, 0xda, 0xdd, 0x0b, 0x2f, 0xb7, 0x4d, 0x00, ++ 0x3f, 0x02, 0x49, 0x9b, 0xc2, 0xfd, 0xa5, 0x47, 0xa6, 0x83, 0x9d, 0xf4, ++ 0xed, 0x7a, 0xd9, 0x29, 0xd2, 0x2e, 0xde, 0x0d, 0xe6, 0xa0, 0x99, 0xd2, ++ 0x6f, 0x6d, 0x6b, 0xc5, 0x34, 0x92, 0x8f, 0xf5, 0x83, 0xac, 0xfe, 0xe0, ++ 0x09, 0x11, 0xea, 0x6d, 0x46, 0x7c, 0x56, 0xbe, 0xf8, 0x54, 0x9a, 0x6a, ++ 0x47, 0x3c, 0x30, 0x7b, 0x9b, 0x04, 0xd1, 0xee, 0xa8, 0x6d, 0xfe, 0x62, ++ 0x0a, 0xc8, 0x71, 0x2f, 0x09, 0x23, 0x1d, 0x46, 0xbf, 0x07, 0xdf, 0x3f, ++ 0x9d, 0x84, 0x7c, 0x5f, 0xa2, 0x24, 0xf4, 0x6d, 0xa7, 0xf3, 0x44, 0x3b, ++ 0xd9, 0xcb, 0xf9, 0xcc, 0xdb, 0xfa, 0xc8, 0x09, 0xd1, 0x01, 0xe5, 0x15, ++ 0x9d, 0xc0, 0x67, 0xde, 0x28, 0x3a, 0x2a, 0xef, 0xd5, 0x2f, 0x21, 0xa5, ++ 0x98, 0xce, 0xe7, 0x95, 0x44, 0x7b, 0xca, 0x91, 0x0b, 0x69, 0xf5, 0x47, ++ 0xe4, 0x47, 0x20, 0x0f, 0x34, 0xb8, 0x90, 0x00, 0xb3, 0x2b, 0x1a, 0x36, ++ 0x3e, 0x93, 0x7f, 0x90, 0xce, 0xab, 0xab, 0xf9, 0x37, 0x0e, 0x21, 0x4f, ++ 0x2f, 0x47, 0x18, 0x3d, 0x9e, 0x6c, 0x99, 0xf7, 0xf3, 0x1d, 0x6a, 0xff, ++ 0xf2, 0xa6, 0x9b, 0xfb, 0x45, 0x91, 0xf7, 0x02, 0xf8, 0x9e, 0xda, 0xc6, ++ 0xec, 0x20, 0xd2, 0xce, 0xca, 0x6a, 0x39, 0xe8, 0x00, 0xbb, 0xb3, 0x7a, ++ 0xad, 0xec, 0xa2, 0x94, 0x4a, 0xaa, 0x37, 0x3f, 0xff, 0xc2, 0xb3, 0xe0, ++ 0xaf, 0x7d, 0x6a, 0x46, 0x7f, 0xad, 0x6a, 0xf3, 0x9b, 0x1f, 0x8d, 0xa7, ++ 0xf5, 0xaa, 0x2d, 0x72, 0xca, 0x34, 0xb6, 0x1c, 0x9b, 0x90, 0x16, 0xc1, ++ 0x8f, 0x97, 0xfe, 0x6f, 0xd1, 0xa8, 0x08, 0x3e, 0x2a, 0x7f, 0xf9, 0xa6, ++ 0xa2, 0x8e, 0x64, 0xcf, 0xef, 0x4d, 0x8a, 0xe0, 0xa5, 0x6a, 0xcb, 0x1e, ++ 0x85, 0x8c, 0xec, 0x0b, 0xc7, 0x49, 0x2d, 0x7b, 0x94, 0x90, 0x2d, 0x06, ++ 0x7e, 0x5a, 0x0e, 0x4e, 0x01, 0xbb, 0xa5, 0x61, 0xe3, 0x77, 0x0a, 0xf8, ++ 0x5f, 0x5f, 0xee, 0x16, 0x48, 0x7a, 0x6e, 0xdf, 0xf7, 0xcb, 0xd7, 0xbe, ++ 0x89, 0x7a, 0x11, 0xe0, 0x84, 0xf8, 0xe4, 0xf8, 0xea, 0xc5, 0x5f, 0x1f, ++ 0xbc, 0x05, 0xa7, 0xef, 0x28, 0xc4, 0x7e, 0x4e, 0x90, 0x97, 0x67, 0xc3, ++ 0x9b, 0x9f, 0xcb, 0xe9, 0x9a, 0xd7, 0xec, 0x24, 0x91, 0xce, 0xa3, 0xfc, ++ 0xf7, 0xe6, 0xc0, 0x34, 0xc0, 0xe7, 0xcb, 0x77, 0x3a, 0x60, 0x3d, 0x9d, ++ 0x52, 0x1d, 0xa3, 0xf3, 0xd5, 0x0f, 0xa4, 0xb9, 0xe9, 0xf7, 0xcb, 0x65, ++ 0x5f, 0x9a, 0x13, 0x4b, 0xf6, 0xbc, 0x7c, 0xcd, 0x5d, 0x48, 0x7f, 0x65, ++ 0x42, 0x5d, 0x9a, 0x13, 0xf9, 0xc9, 0x9d, 0x69, 0x42, 0xd9, 0xed, 0xcb, ++ 0x84, 0x75, 0x2e, 0x68, 0xba, 0x01, 0xd7, 0x59, 0x4a, 0x3c, 0x48, 0x87, ++ 0xe5, 0xab, 0xc5, 0xe2, 0x00, 0x2d, 0xbf, 0x91, 0xc8, 0xd4, 0x2d, 0x31, ++ 0xf8, 0xa4, 0x28, 0x89, 0xf1, 0x49, 0xe7, 0x3a, 0x8a, 0x5c, 0xba, 0xce, ++ 0x4e, 0xb0, 0xfb, 0xc1, 0xde, 0xfe, 0xad, 0x18, 0x58, 0x8f, 0xfe, 0xe9, ++ 0xed, 0x04, 0xe4, 0xff, 0x5d, 0x7c, 0xcd, 0x54, 0x53, 0x62, 0xfd, 0x1b, ++ 0x0b, 0xc3, 0x97, 0x2d, 0xc9, 0xa4, 0xf9, 0x8b, 0x16, 0x03, 0xfd, 0x36, ++ 0x3f, 0xd8, 0x01, 0x78, 0x3a, 0x36, 0xd0, 0x9d, 0x0e, 0xf3, 0xa4, 0x70, ++ 0xf0, 0x71, 0xb8, 0x09, 0x3f, 0xd0, 0x71, 0xc5, 0x0f, 0x2e, 0x4f, 0x67, ++ 0x78, 0x22, 0xaa, 0x54, 0xc4, 0xdf, 0xa3, 0xfa, 0x60, 0x12, 0x3c, 0x87, ++ 0xfe, 0x1d, 0xb2, 0xdb, 0x9a, 0x6f, 0x78, 0x8f, 0xcb, 0x4f, 0xf6, 0xfd, ++ 0x85, 0xfc, 0xfb, 0x74, 0xde, 0x71, 0xa0, 0xdf, 0x3a, 0xd3, 0xa8, 0x7d, ++ 0x1f, 0x63, 0x7d, 0x73, 0x61, 0x7d, 0xa8, 0x17, 0xa9, 0x9e, 0xd3, 0xd1, ++ 0x99, 0x8e, 0xdf, 0x19, 0xff, 0x37, 0x3f, 0xc4, 0xf8, 0x5d, 0xe3, 0xff, ++ 0xc0, 0x8c, 0xa9, 0xd0, 0x7e, 0xea, 0x43, 0xc6, 0x47, 0xf0, 0x1e, 0xe8, ++ 0x13, 0x3a, 0xaf, 0x60, 0x3a, 0xb6, 0xef, 0xb9, 0x5e, 0x40, 0xf9, 0x60, ++ 0x26, 0xc1, 0x58, 0x7c, 0xde, 0x2c, 0x73, 0x3e, 0x37, 0xb6, 0x7b, 0x29, ++ 0xbf, 0x42, 0x9c, 0x40, 0xa3, 0x13, 0x3a, 0x7f, 0x49, 0x48, 0xd0, 0xd3, ++ 0x0b, 0xfd, 0x4e, 0x12, 0xe2, 0x01, 0xfd, 0x95, 0xd2, 0x95, 0xf4, 0x7d, ++ 0xbd, 0x7d, 0x03, 0xdf, 0xc5, 0x7e, 0x4a, 0xe4, 0xb9, 0x4e, 0xaf, 0x94, ++ 0x71, 0xb9, 0x50, 0x90, 0x44, 0xe5, 0x41, 0x7c, 0x44, 0x1e, 0x90, 0xa6, ++ 0xd4, 0x73, 0xb2, 0x23, 0xab, 0x65, 0xe2, 0x03, 0x93, 0xb3, 0xfa, 0x53, ++ 0x33, 0xfa, 0xe3, 0xd5, 0x9b, 0xe5, 0x62, 0x58, 0xff, 0xf1, 0x4d, 0xfb, ++ 0x3e, 0xba, 0x99, 0xd2, 0xf9, 0xf1, 0x16, 0x8d, 0x6f, 0x8d, 0x72, 0x35, ++ 0x9a, 0x6f, 0xcb, 0xb7, 0xae, 0x17, 0x80, 0x4e, 0xa3, 0xf9, 0xf6, 0x78, ++ 0x39, 0xd5, 0xe2, 0xb1, 0xf8, 0x96, 0x3e, 0x8f, 0xc9, 0xb7, 0xe5, 0xa1, ++ 0xff, 0xa7, 0x72, 0x55, 0x83, 0xdf, 0xac, 0x24, 0xa3, 0x3c, 0xa5, 0xf2, ++ 0x71, 0x10, 0x98, 0x10, 0xfd, 0xc1, 0x31, 0x5a, 0x3e, 0x7e, 0x03, 0xf6, ++ 0x56, 0x6a, 0x5f, 0xf9, 0x48, 0xff, 0x3e, 0x24, 0x45, 0x7d, 0xe9, 0x50, ++ 0xa3, 0x3f, 0x8d, 0xee, 0xa8, 0x05, 0x37, 0x08, 0xe4, 0x7a, 0x2f, 0x7d, ++ 0x6a, 0xf4, 0xd7, 0x4b, 0x9f, 0x1a, 0xfd, 0x45, 0xaf, 0xd7, 0x08, 0xbf, ++ 0xe8, 0xf6, 0xc1, 0xe0, 0x23, 0x51, 0x3a, 0x29, 0xde, 0x4e, 0x2d, 0x3a, ++ 0x8a, 0xcf, 0xea, 0x76, 0x21, 0x60, 0x46, 0x3e, 0xf7, 0xbd, 0x35, 0xa0, ++ 0x10, 0xe1, 0xe4, 0x46, 0xf5, 0x46, 0xfc, 0x6f, 0x0d, 0x48, 0xd1, 0xd7, ++ 0x03, 0x51, 0xf5, 0x96, 0xa8, 0xfe, 0xee, 0xa8, 0x7a, 0x71, 0x54, 0x7f, ++ 0x4f, 0x54, 0xbd, 0xce, 0xd0, 0xbf, 0xba, 0x6d, 0x9f, 0x42, 0x10, 0xff, ++ 0x41, 0x43, 0x3f, 0xf3, 0xa2, 0xe7, 0xc8, 0xe7, 0x31, 0xfc, 0x41, 0x4d, ++ 0xff, 0x78, 0x5b, 0x4f, 0x28, 0x3e, 0xa0, 0x8b, 0xec, 0xb0, 0x02, 0x72, ++ 0x4f, 0x5e, 0x42, 0x4d, 0x37, 0x88, 0xaf, 0xed, 0x12, 0x31, 0xbe, 0xd6, ++ 0xa3, 0x86, 0x1d, 0x49, 0xf4, 0xf9, 0x03, 0x56, 0xe6, 0xa7, 0xf5, 0x38, ++ 0x79, 0x3d, 0x91, 0xd5, 0xc3, 0xa9, 0xca, 0x52, 0x90, 0x7b, 0xda, 0xf3, ++ 0xb0, 0x95, 0xa0, 0x7f, 0xde, 0x53, 0x1c, 0x76, 0x24, 0xea, 0xfc, 0xff, ++ 0x83, 0xed, 0xa2, 0x43, 0xa5, 0xed, 0xa1, 0x00, 0x99, 0xaa, 0x8f, 0x23, ++ 0x44, 0xe6, 0xd3, 0x80, 0xf8, 0x0e, 0x91, 0xfe, 0xda, 0x59, 0xdc, 0xb0, ++ 0x27, 0xce, 0x91, 0x8f, 0xdf, 0x8b, 0xcb, 0x09, 0x00, 0xfd, 0x5d, 0x2e, ++ 0xda, 0x72, 0x16, 0x81, 0xbf, 0xe7, 0x17, 0x5d, 0x94, 0x7c, 0xc8, 0xfc, ++ 0xc5, 0x37, 0x39, 0x08, 0xa5, 0xb3, 0x9e, 0xf6, 0x21, 0xd7, 0xcc, 0xa4, ++ 0xcf, 0x17, 0xbc, 0x2d, 0x82, 0xb9, 0x4d, 0xd1, 0xe3, 0x96, 0x32, 0x29, ++ 0xdd, 0xcc, 0xe3, 0x74, 0x7c, 0x94, 0xf8, 0x9e, 0xbe, 0x84, 0xae, 0x6f, ++ 0x5e, 0x3b, 0xb3, 0xc3, 0xe7, 0x2f, 0x8f, 0x4d, 0xf7, 0x95, 0xbc, 0x7f, ++ 0xa9, 0x6d, 0xa1, 0x02, 0xf2, 0x95, 0xda, 0xd1, 0x87, 0xf4, 0x71, 0xd1, ++ 0x4a, 0xb2, 0x1c, 0xe9, 0xae, 0xbc, 0x29, 0xea, 0x79, 0xfb, 0x55, 0xc8, ++ 0x1f, 0x95, 0x51, 0xfc, 0xe1, 0xe1, 0xfe, 0xc3, 0x2e, 0x8d, 0x3f, 0x0a, ++ 0x48, 0x01, 0xca, 0x17, 0x42, 0x98, 0xff, 0xcb, 0xe5, 0xf2, 0xe5, 0x62, ++ 0xde, 0x35, 0x33, 0x29, 0x1e, 0x7a, 0xf6, 0x8b, 0xc4, 0xac, 0x82, 0x3f, ++ 0x2b, 0x92, 0xa5, 0xb0, 0xce, 0x4d, 0x42, 0x00, 0xe2, 0x05, 0xc4, 0x97, ++ 0x8a, 0x7c, 0x56, 0x4b, 0xc2, 0x28, 0x0f, 0x35, 0x38, 0x75, 0x01, 0x1f, ++ 0x0d, 0xeb, 0x5f, 0x4e, 0x75, 0x6d, 0xfb, 0x53, 0xd1, 0x3d, 0x40, 0x2f, ++ 0xaf, 0xfe, 0x21, 0xff, 0x39, 0x5a, 0x76, 0xbd, 0xfa, 0xe9, 0xd0, 0x9d, ++ 0x50, 0x7f, 0xed, 0xe3, 0x9c, 0x3f, 0x90, 0xbe, 0xfd, 0x27, 0xed, 0xfe, ++ 0x7e, 0x36, 0xe8, 0xb3, 0x9e, 0xdd, 0x66, 0x8c, 0x8b, 0xf5, 0xec, 0xfe, ++ 0x55, 0xce, 0x3d, 0x50, 0xdf, 0x61, 0xc6, 0xb8, 0x58, 0xcf, 0x12, 0xb3, ++ 0x1b, 0xf8, 0xc0, 0xb7, 0xdb, 0x1e, 0x38, 0x1f, 0xda, 0x07, 0x32, 0xff, ++ 0xa1, 0x61, 0xd7, 0x77, 0xf9, 0x21, 0xd4, 0xaf, 0xf7, 0x23, 0xde, 0x8e, ++ 0x26, 0x31, 0xff, 0xe5, 0x64, 0xfb, 0x9f, 0x0f, 0x08, 0x29, 0x50, 0xd2, ++ 0x55, 0x81, 0xfd, 0xb0, 0x3b, 0x1e, 0xf9, 0xc8, 0xbb, 0xc3, 0x8a, 0xfe, ++ 0x7a, 0xcf, 0xae, 0xef, 0x8a, 0x3c, 0xb6, 0x7f, 0xde, 0x7a, 0x6a, 0x15, ++ 0xe2, 0x41, 0x7a, 0xb4, 0x93, 0x99, 0x5b, 0x81, 0x7e, 0x13, 0x59, 0xfc, ++ 0xd8, 0xbb, 0x73, 0xdc, 0xf3, 0x8b, 0xe9, 0xf7, 0x6b, 0x5a, 0xf7, 0x28, ++ 0xf3, 0x68, 0xfb, 0xa4, 0xd7, 0xff, 0x9a, 0x0f, 0xf2, 0xb3, 0x67, 0x2b, ++ 0xb3, 0x8b, 0xba, 0xe5, 0xd0, 0x1a, 0xe2, 0x22, 0xe4, 0xeb, 0xa4, 0xb2, ++ 0x87, 0x64, 0x88, 0xf3, 0x01, 0x33, 0x65, 0x11, 0xf2, 0x78, 0xf2, 0x86, ++ 0x2b, 0x7c, 0x79, 0xb1, 0xe0, 0xc2, 0xe0, 0xd0, 0x43, 0xe1, 0x00, 0xeb, ++ 0xa2, 0x70, 0x29, 0x07, 0xb9, 0xdf, 0x1f, 0x3c, 0xe2, 0x92, 0x15, 0xa4, ++ 0xf7, 0x7f, 0x3d, 0x78, 0x9c, 0x98, 0xcd, 0xe4, 0xda, 0x8f, 0x08, 0xc4, ++ 0x85, 0x22, 0x70, 0x11, 0xdc, 0xec, 0xb9, 0x3d, 0x60, 0x11, 0x70, 0xfd, ++ 0xec, 0xf9, 0xee, 0xef, 0xf2, 0x41, 0xee, 0x1c, 0x6f, 0x59, 0x8c, 0xf6, ++ 0xca, 0xd9, 0xd6, 0x3d, 0x22, 0xf9, 0x5f, 0x95, 0x0e, 0xfe, 0xab, 0xeb, ++ 0x16, 0x82, 0xe7, 0xb2, 0xee, 0xa9, 0xff, 0xb2, 0xf8, 0x66, 0xf4, 0xff, ++ 0x5e, 0x92, 0x8a, 0xf3, 0x8c, 0xe6, 0x83, 0xbe, 0x74, 0xfe, 0xda, 0x4f, ++ 0xb0, 0xfe, 0xb2, 0xdd, 0x85, 0xf3, 0x3d, 0x47, 0xfe, 0x2f, 0xff, 0xdf, ++ 0x86, 0xf7, 0xad, 0x14, 0xef, 0x8e, 0xb3, 0xe3, 0xfd, 0xc1, 0xff, 0xb1, ++ 0x78, 0x7f, 0x9b, 0xe3, 0xdd, 0xee, 0x34, 0x83, 0x3c, 0xdb, 0xf5, 0x57, ++ 0x8c, 0xb3, 0x6a, 0xeb, 0x3f, 0xdb, 0xba, 0x5f, 0xf8, 0x1f, 0xba, 0x6e, ++ 0xcd, 0x8e, 0xff, 0x95, 0x49, 0xfd, 0xb0, 0x80, 0xf6, 0x7f, 0x9b, 0xf8, ++ 0x3f, 0x1c, 0x4a, 0xe7, 0xd9, 0x94, 0xbd, 0xef, 0x83, 0x02, 0xda, 0x3a, ++ 0x51, 0x20, 0xc5, 0xb1, 0xec, 0x93, 0x8f, 0x92, 0x99, 0x1f, 0x38, 0x51, ++ 0x30, 0xa1, 0xff, 0x47, 0x12, 0x05, 0xee, 0xff, 0x31, 0xbf, 0x69, 0x00, ++ 0xb7, 0x23, 0x06, 0x2c, 0x2c, 0x45, 0x7b, 0x63, 0x40, 0xf6, 0xa3, 0x68, ++ 0x37, 0x10, 0x49, 0x5d, 0x09, 0xfb, 0x77, 0xbf, 0xca, 0x99, 0xe7, 0x7a, ++ 0x18, 0x7b, 0x8c, 0xfa, 0xc4, 0x03, 0x75, 0xe7, 0xa5, 0xbc, 0x6e, 0xf4, ++ 0x1f, 0x9f, 0x13, 0x88, 0x5b, 0xa0, 0x36, 0xe8, 0x80, 0x9c, 0xab, 0xf6, ++ 0x83, 0xfd, 0x9a, 0x9d, 0x2d, 0xa2, 0x7d, 0x4b, 0x4b, 0xb4, 0x6b, 0xdf, ++ 0x70, 0x4c, 0x65, 0xcf, 0xab, 0x15, 0x83, 0xdf, 0x74, 0x05, 0xd1, 0xd5, ++ 0xe9, 0xba, 0xa6, 0xa4, 0x18, 0xfd, 0xa2, 0xc9, 0x7c, 0xbc, 0xcb, 0xc9, ++ 0xe0, 0x0f, 0x0b, 0xe8, 0xfc, 0x2f, 0xb7, 0xc8, 0xce, 0x00, 0x05, 0xd1, ++ 0x15, 0x13, 0x3c, 0x12, 0xac, 0xe7, 0x8a, 0x4c, 0x81, 0xf8, 0x75, 0xfb, ++ 0x47, 0x93, 0xa3, 0xfc, 0xa7, 0xad, 0xd4, 0xc6, 0xd4, 0xc7, 0xd7, 0xfe, ++ 0x5e, 0xf8, 0x59, 0x52, 0x98, 0x9f, 0x39, 0x51, 0x18, 0xbc, 0xb2, 0x18, ++ 0xe0, 0x37, 0x50, 0xc4, 0xf8, 0xe1, 0x59, 0xe1, 0x07, 0xc6, 0x1e, 0xc2, ++ 0xab, 0x20, 0xf0, 0x30, 0xd8, 0x45, 0x92, 0x8b, 0xc1, 0x2f, 0xa9, 0xc6, ++ 0x85, 0xf1, 0x57, 0xee, 0x57, 0xc3, 0x76, 0x33, 0xd8, 0x2b, 0x92, 0x6d, ++ 0x69, 0x07, 0xf0, 0xad, 0x44, 0xa8, 0x5f, 0xcc, 0xe6, 0x8f, 0xfe, 0xb4, ++ 0xe6, 0x17, 0xf7, 0x07, 0x67, 0xc2, 0xfd, 0x6c, 0x89, 0x7f, 0x52, 0x83, ++ 0xbb, 0x94, 0x2d, 0xba, 0xad, 0xc6, 0xf1, 0x10, 0x1e, 0x1a, 0x3e, 0xfe, ++ 0x5e, 0x3c, 0x68, 0xf8, 0xfb, 0x47, 0xf1, 0xf1, 0x7b, 0xc0, 0xc7, 0x98, ++ 0x08, 0x3e, 0xb2, 0x4f, 0x39, 0x25, 0xe0, 0xcf, 0x49, 0xdc, 0x1f, 0x98, ++ 0x7c, 0xaa, 0x43, 0xc4, 0x7a, 0xb6, 0x4b, 0xc2, 0xfd, 0x17, 0xee, 0x0f, ++ 0x4c, 0xb0, 0x25, 0x4a, 0xe0, 0x0f, 0x5c, 0x2a, 0x7d, 0x20, 0x02, 0x5f, ++ 0x96, 0x59, 0xb6, 0x57, 0xc2, 0x3e, 0x82, 0xc5, 0x25, 0x20, 0x5d, 0x0f, ++ 0xeb, 0x32, 0xa1, 0xbf, 0x63, 0x29, 0x14, 0x10, 0xee, 0xc3, 0x1b, 0x25, ++ 0xac, 0x7f, 0x60, 0x72, 0x8e, 0x01, 0x43, 0x7b, 0xfa, 0xc5, 0xaf, 0x1d, ++ 0xbf, 0x9b, 0x40, 0x3c, 0xd9, 0xad, 0x30, 0xc3, 0xbb, 0x98, 0xc5, 0xf3, ++ 0xff, 0xf2, 0xc3, 0x0f, 0x97, 0x14, 0x41, 0x5c, 0x85, 0xfd, 0x95, 0xd1, ++ 0xff, 0x5d, 0x4d, 0xfd, 0xb1, 0xf9, 0x4d, 0x24, 0x18, 0x47, 0xe1, 0xb4, ++ 0x40, 0x22, 0x3e, 0x48, 0x71, 0x58, 0x40, 0x17, 0x75, 0xc8, 0x10, 0x0f, ++ 0x36, 0xd6, 0xe1, 0xef, 0xb2, 0xb4, 0xc8, 0x38, 0x67, 0xeb, 0xdf, 0x9f, ++ 0x1c, 0xf9, 0x67, 0x97, 0xaf, 0x51, 0xb9, 0x75, 0xe8, 0x7c, 0x42, 0xb6, ++ 0x43, 0xc9, 0x82, 0xfd, 0x92, 0xde, 0x6f, 0xfe, 0x51, 0x3b, 0x83, 0x97, ++ 0xf7, 0x1d, 0x12, 0x18, 0x8c, 0xf1, 0x06, 0xb7, 0x58, 0xac, 0xdb, 0x67, ++ 0xfb, 0xf7, 0x14, 0x26, 0x3f, 0x5e, 0xfb, 0xe3, 0xd6, 0xd1, 0x10, 0x3f, ++ 0x9b, 0xd0, 0x93, 0x97, 0xc0, 0xe4, 0x69, 0xa1, 0x09, 0xe8, 0xd2, 0xcb, ++ 0xfd, 0x82, 0x93, 0x44, 0x4d, 0x80, 0x7c, 0x85, 0x93, 0xed, 0x43, 0x12, ++ 0x70, 0x1f, 0x71, 0xbf, 0x68, 0xf7, 0xc4, 0x88, 0xdb, 0x6c, 0xe4, 0xfe, ++ 0xf4, 0x2f, 0xea, 0x31, 0xa8, 0x4c, 0x7a, 0x9a, 0x89, 0x5f, 0x04, 0xbf, ++ 0x89, 0x84, 0x31, 0x7e, 0xeb, 0x6b, 0xb6, 0xc4, 0xdc, 0x0f, 0x9e, 0x9b, ++ 0x62, 0xe2, 0x74, 0xc3, 0xf1, 0x46, 0xff, 0xc4, 0x22, 0xd8, 0xb7, 0x60, ++ 0xdf, 0x5f, 0x40, 0x5f, 0x4d, 0xd0, 0xe3, 0xad, 0x6b, 0xda, 0x97, 0x52, ++ 0x7e, 0x5f, 0x3c, 0xc0, 0xdf, 0x21, 0xdd, 0xfe, 0xca, 0x3f, 0x0a, 0x5f, ++ 0xf0, 0xdf, 0x01, 0xbe, 0x1b, 0xad, 0xa1, 0x29, 0xc5, 0x31, 0xe4, 0xc7, ++ 0x42, 0x0e, 0xbf, 0xe9, 0x7b, 0xbf, 0xc7, 0x78, 0xe7, 0x05, 0xed, 0x6b, ++ 0x4d, 0x40, 0xbf, 0x17, 0x34, 0x9b, 0x0c, 0xfb, 0x93, 0xd5, 0x29, 0xdc, ++ 0xef, 0x1a, 0x45, 0x46, 0xc1, 0xbc, 0xa6, 0xef, 0xb5, 0xda, 0x0b, 0x01, ++ 0x2f, 0xfb, 0x45, 0x97, 0x95, 0xae, 0xcf, 0xdb, 0x7e, 0x42, 0xf1, 0xc4, ++ 0xd8, 0xe7, 0x8a, 0x86, 0x27, 0x8c, 0x0f, 0x71, 0xf4, 0x97, 0x52, 0xd8, ++ 0xbe, 0xc0, 0x4e, 0xb9, 0x65, 0x1e, 0xc0, 0x75, 0xe7, 0x57, 0x16, 0xe2, ++ 0xa3, 0xf8, 0xdd, 0xae, 0xf8, 0xab, 0x62, 0xcd, 0x33, 0x25, 0x8d, 0xc9, ++ 0xb9, 0x05, 0xa4, 0xe5, 0xce, 0xfc, 0xdc, 0x7f, 0x3d, 0xf8, 0x4e, 0xe8, ++ 0xb1, 0x05, 0x27, 0x82, 0x9f, 0xd9, 0x4c, 0x78, 0x5c, 0x23, 0x9a, 0xfe, ++ 0x08, 0xd2, 0xf1, 0xc9, 0x0d, 0x24, 0x00, 0xfa, 0x14, 0xfc, 0x52, 0x90, ++ 0x0b, 0x27, 0x37, 0x11, 0xd4, 0xe7, 0x14, 0x24, 0x8f, 0x82, 0x5f, 0x4d, ++ 0xf9, 0xfd, 0xc7, 0xfa, 0x38, 0xcd, 0xb0, 0xb6, 0x2d, 0xbf, 0x00, 0x3b, ++ 0xa0, 0xb6, 0x5d, 0x70, 0x9a, 0x68, 0x7b, 0xad, 0x14, 0x52, 0x20, 0x1e, ++ 0xeb, 0x6d, 0x4b, 0x14, 0x41, 0xef, 0x16, 0xa8, 0xc4, 0x8d, 0xfb, 0xc3, ++ 0x92, 0x73, 0xe4, 0xf5, 0x3a, 0xbe, 0x78, 0x29, 0x45, 0x42, 0xf8, 0xee, ++ 0x1b, 0xbf, 0xf3, 0x16, 0xf8, 0xee, 0xd7, 0x5d, 0x0a, 0x01, 0x7b, 0xc4, ++ 0xfd, 0x46, 0xd8, 0x01, 0x7a, 0xfb, 0xeb, 0xf6, 0xd1, 0xc8, 0x07, 0xfd, ++ 0xad, 0xeb, 0x97, 0xf5, 0xa4, 0x72, 0xb2, 0x0c, 0xe3, 0x30, 0x79, 0x18, ++ 0x4d, 0x0f, 0x79, 0x9b, 0xe2, 0x0c, 0xf5, 0x8b, 0x45, 0x4f, 0x16, 0xf0, ++ 0xd7, 0x74, 0x73, 0x68, 0xa1, 0x2b, 0x06, 0xfe, 0xa6, 0xa5, 0x32, 0x3a, ++ 0x3b, 0x67, 0xf9, 0x16, 0xf8, 0xff, 0x4c, 0xbe, 0x7d, 0xa8, 0xc9, 0x37, ++ 0x8f, 0x58, 0xac, 0xe3, 0xa3, 0x94, 0x54, 0x46, 0xf7, 0x3a, 0xf9, 0x96, ++ 0x1e, 0x4b, 0xbe, 0xdd, 0x21, 0xa8, 0xe9, 0x00, 0xf7, 0x3b, 0x76, 0x0d, ++ 0x49, 0x07, 0xbc, 0xde, 0xf1, 0xb6, 0x9c, 0x1a, 0x4b, 0xbe, 0x6d, 0xae, ++ 0x67, 0xfb, 0x7f, 0xaf, 0x50, 0x7e, 0x84, 0xb2, 0xa7, 0x95, 0xca, 0xb7, ++ 0x8b, 0x74, 0xf2, 0xad, 0x95, 0xca, 0xb7, 0xdc, 0xbe, 0xef, 0xfd, 0xed, ++ 0x5c, 0xe5, 0x5b, 0xe0, 0xbf, 0x87, 0xff, 0x36, 0x83, 0x7c, 0x8b, 0xb1, ++ 0xde, 0x44, 0x0e, 0x3f, 0x4d, 0xbe, 0xe5, 0xb7, 0x1f, 0x44, 0xf9, 0x96, ++ 0xdf, 0x6a, 0x22, 0xaa, 0xce, 0x7e, 0xb0, 0xa4, 0x9e, 0x4d, 0xbe, 0x09, ++ 0xa9, 0xd7, 0x83, 0x3d, 0xbc, 0x5f, 0x76, 0xc5, 0xc7, 0xa0, 0x9f, 0xcd, ++ 0xdc, 0xfe, 0x7e, 0x85, 0xe7, 0xed, 0xc1, 0x77, 0x40, 0xce, 0xfd, 0x5b, ++ 0x2a, 0xdb, 0x2f, 0x3d, 0x57, 0x39, 0x97, 0x99, 0xc6, 0xf8, 0xe4, 0xac, ++ 0x72, 0xee, 0xbf, 0x09, 0xce, 0x9a, 0x9c, 0xbb, 0x63, 0x1b, 0x95, 0x73, ++ 0xb9, 0xb1, 0xe8, 0x90, 0xc9, 0xb9, 0x3b, 0xb6, 0x53, 0x39, 0x27, 0x00, ++ 0x3d, 0x32, 0x39, 0x77, 0xc7, 0x2e, 0xc2, 0xe2, 0x6f, 0x51, 0xf2, 0x6d, ++ 0x78, 0x1f, 0xf9, 0x46, 0xb0, 0x7f, 0x6d, 0x90, 0xbd, 0xef, 0x6d, 0xcb, ++ 0x7d, 0xe6, 0x56, 0x3a, 0xde, 0x28, 0xb7, 0xec, 0xb2, 0xd0, 0xfe, 0xa3, ++ 0x22, 0xf2, 0x6e, 0x8c, 0x5e, 0xde, 0xfd, 0x5b, 0xaa, 0x84, 0x70, 0xee, ++ 0x23, 0xef, 0xf6, 0x9f, 0x9b, 0xbc, 0xdb, 0xc6, 0xe5, 0x1d, 0x95, 0x63, ++ 0x83, 0x41, 0xbe, 0x46, 0xd3, 0x87, 0xab, 0x3d, 0xce, 0x50, 0xdf, 0x39, ++ 0xae, 0x73, 0xd3, 0x2f, 0x81, 0x5f, 0xde, 0x15, 0x71, 0x7f, 0xf1, 0x03, ++ 0x13, 0xdb, 0x07, 0x7a, 0x6f, 0x5c, 0x67, 0x21, 0xd0, 0xd7, 0x2a, 0x3e, ++ 0x1f, 0x2f, 0xa7, 0xbf, 0xee, 0x7a, 0x1f, 0x8e, 0x3f, 0xe9, 0x0d, 0xb6, ++ 0xbe, 0x9a, 0x4d, 0x2c, 0xfe, 0x5d, 0xdb, 0xca, 0xec, 0xc3, 0xda, 0x66, ++ 0x31, 0xa0, 0xd2, 0x7f, 0x4e, 0x19, 0xff, 0xbd, 0x02, 0xf3, 0xaf, 0xd8, ++ 0x25, 0x90, 0x74, 0x5a, 0x9f, 0x61, 0xf6, 0x3f, 0x6d, 0x03, 0x19, 0xfc, ++ 0xa2, 0x4c, 0xb8, 0x5f, 0x34, 0xad, 0x40, 0x47, 0x0f, 0xf3, 0xc7, 0x56, ++ 0x61, 0x1c, 0xbf, 0xc1, 0xea, 0x58, 0x47, 0x28, 0x1f, 0xcf, 0x97, 0x88, ++ 0x05, 0xe2, 0xf5, 0x55, 0xb6, 0x29, 0x5f, 0x82, 0x1d, 0x5c, 0x35, 0x96, ++ 0xc5, 0xf7, 0xab, 0xf8, 0x73, 0xc2, 0xf3, 0x06, 0xb4, 0x3c, 0xc8, 0xd2, ++ 0xb6, 0xdb, 0xdf, 0x1a, 0x40, 0xfa, 0xe6, 0x0f, 0x4c, 0x37, 0x33, 0x3c, ++ 0x4e, 0x7f, 0x5e, 0x08, 0xac, 0xcd, 0x85, 0xfc, 0x25, 0x63, 0x7b, 0x55, ++ 0x54, 0xfe, 0xe3, 0x63, 0x7c, 0x9d, 0x33, 0xc4, 0x10, 0xc2, 0x85, 0xbc, ++ 0x2f, 0xc6, 0xcc, 0x63, 0x78, 0x2c, 0x1a, 0x1e, 0xfb, 0x39, 0x3c, 0xe8, ++ 0xfa, 0x0d, 0xf0, 0x08, 0x08, 0x31, 0xe1, 0x41, 0x31, 0x3a, 0xad, 0x20, ++ 0x2d, 0xb2, 0xfe, 0x8a, 0x77, 0x43, 0x4b, 0x21, 0x9e, 0x5f, 0xb1, 0x4a, ++ 0xc0, 0x7d, 0x5f, 0x0d, 0x1e, 0xd1, 0xeb, 0xd4, 0xe0, 0xa3, 0xc5, 0xa7, ++ 0xab, 0xf8, 0xfb, 0xde, 0xf6, 0xdb, 0x71, 0xdf, 0x3f, 0x7a, 0xfd, 0x1a, ++ 0xfc, 0xfa, 0xac, 0x5b, 0x83, 0x67, 0xd4, 0xfa, 0xfd, 0xa9, 0x7c, 0xdf, ++ 0xab, 0x80, 0x8c, 0x86, 0x7c, 0x1a, 0x4a, 0x0f, 0x28, 0x3f, 0x7c, 0xbf, ++ 0xa6, 0x70, 0xa0, 0xdf, 0x29, 0x9e, 0x70, 0x7e, 0xba, 0x5e, 0x1e, 0x3f, ++ 0xcd, 0xe1, 0x30, 0xda, 0x3f, 0x61, 0x52, 0x26, 0x01, 0xb8, 0x91, 0x3a, ++ 0xa0, 0x9f, 0xd2, 0xc6, 0xdb, 0xdf, 0xca, 0xa4, 0xeb, 0x1f, 0xf3, 0x89, ++ 0x3a, 0x0a, 0xd4, 0xe4, 0xc5, 0xe3, 0xcd, 0x1e, 0xd8, 0x47, 0xdd, 0x68, ++ 0x0d, 0xa3, 0x7c, 0xd3, 0xe8, 0xab, 0x53, 0xa3, 0x77, 0x3e, 0xce, 0xce, ++ 0xac, 0xba, 0x89, 0xe8, 0xaf, 0xb7, 0x09, 0x4e, 0xb0, 0x2f, 0xbc, 0x41, ++ 0x2b, 0xc2, 0xd1, 0x4b, 0xe9, 0xcc, 0x4a, 0xbb, 0xec, 0x5b, 0xf5, 0xed, ++ 0x14, 0x0e, 0x47, 0xa7, 0x19, 0xf9, 0x8a, 0xeb, 0x1d, 0x0a, 0x77, 0x13, ++ 0xf8, 0x53, 0x9a, 0x1e, 0xa2, 0x70, 0x07, 0xbe, 0x19, 0xdd, 0x7e, 0x02, ++ 0xf7, 0x73, 0x0b, 0x49, 0x18, 0xf7, 0x4b, 0x6a, 0x1b, 0x05, 0x57, 0x90, ++ 0xae, 0xa3, 0xb6, 0x8d, 0xc1, 0x4b, 0x93, 0xb7, 0xf4, 0xcf, 0xa6, 0xc7, ++ 0x47, 0x0c, 0x7a, 0x94, 0x62, 0xd1, 0x23, 0x81, 0x20, 0x71, 0x51, 0x44, ++ 0x0f, 0x56, 0xf1, 0x7e, 0xd3, 0xcd, 0xfe, 0x8f, 0x60, 0x1f, 0x66, 0x3a, ++ 0xa5, 0xf7, 0xb5, 0x24, 0x82, 0xc7, 0xe1, 0xf4, 0x3f, 0xc0, 0x63, 0x34, ++ 0x9e, 0x34, 0x78, 0x9e, 0x8d, 0x3e, 0xbf, 0xe0, 0xf6, 0xc7, 0x66, 0x80, ++ 0xa3, 0x0d, 0xe0, 0x15, 0x66, 0x76, 0x54, 0x90, 0xea, 0x05, 0x7b, 0xa4, ++ 0xdd, 0x2b, 0xf9, 0x0c, 0x70, 0x9c, 0xf4, 0xec, 0x69, 0x46, 0x5f, 0xbb, ++ 0x04, 0x15, 0xf6, 0x13, 0x7a, 0xe1, 0x04, 0xf4, 0x4a, 0xdb, 0xc7, 0xb4, ++ 0x33, 0x7a, 0x05, 0xb8, 0xa9, 0x00, 0xf7, 0xf6, 0x12, 0x11, 0xea, 0xa5, ++ 0x14, 0xbe, 0xc9, 0xb9, 0x7d, 0xd7, 0x09, 0xfb, 0x97, 0x7a, 0xfe, 0xad, ++ 0xd8, 0x75, 0x90, 0x8d, 0xbf, 0x5a, 0x70, 0x91, 0x18, 0xf4, 0xab, 0xad, ++ 0xbb, 0x3f, 0xfa, 0xfd, 0x47, 0xe9, 0xb6, 0x33, 0x8a, 0x6e, 0xdf, 0xb3, ++ 0x86, 0xdf, 0x19, 0x0d, 0x74, 0xbb, 0x4b, 0x60, 0x71, 0x84, 0xf6, 0x44, ++ 0xc3, 0xbe, 0xa3, 0x39, 0x8d, 0xed, 0xbb, 0x6f, 0xb4, 0x52, 0xfa, 0x86, ++ 0xfd, 0xae, 0xb7, 0x65, 0xd7, 0x3a, 0xb5, 0x2f, 0x9f, 0x9f, 0xe6, 0xf0, ++ 0x04, 0xfb, 0x5f, 0xd5, 0xc5, 0xa5, 0x46, 0xc0, 0x02, 0x60, 0x2f, 0x70, ++ 0x83, 0x05, 0xf3, 0xcf, 0x70, 0x1e, 0x83, 0x99, 0x7d, 0xa9, 0x97, 0xaf, ++ 0x9b, 0xad, 0x24, 0xf5, 0xfa, 0xc2, 0xfe, 0xc7, 0x57, 0xb8, 0x3f, 0xd0, ++ 0x9f, 0x7d, 0xa3, 0xd5, 0x47, 0xc2, 0xf7, 0x40, 0xee, 0xb5, 0xd1, 0xef, ++ 0x0d, 0x8f, 0x7c, 0x2f, 0x5a, 0xbe, 0x6b, 0xfe, 0xfe, 0xd9, 0xd6, 0x95, ++ 0x9c, 0xf6, 0x8f, 0xad, 0xab, 0x37, 0x7f, 0x93, 0x74, 0xe0, 0xfe, 0x93, ++ 0x39, 0xd1, 0x73, 0x4f, 0x0a, 0xc6, 0x7f, 0x58, 0x7e, 0xd2, 0x8d, 0x3c, ++ 0x3f, 0x89, 0xce, 0x00, 0xed, 0x2c, 0x5d, 0xbf, 0x8c, 0xd4, 0x31, 0xfd, ++ 0xf7, 0x23, 0x19, 0x16, 0xd4, 0xc3, 0x77, 0xf2, 0xbc, 0xf8, 0xcb, 0x45, ++ 0x1b, 0xf1, 0xd1, 0x75, 0x7c, 0xed, 0x96, 0x91, 0x4e, 0xa9, 0x96, 0xfe, ++ 0xdd, 0x25, 0x20, 0x97, 0x27, 0x52, 0x3d, 0x42, 0x8b, 0xaf, 0xdf, 0x19, ++ 0xf3, 0xf1, 0xad, 0xd8, 0x2e, 0xe2, 0x7e, 0xd4, 0x35, 0xef, 0x26, 0xd7, ++ 0xc0, 0x3e, 0xdd, 0x35, 0x20, 0x8c, 0xe8, 0xf3, 0x6b, 0x0a, 0x04, 0xd4, ++ 0xbf, 0x1f, 0xc0, 0x60, 0xe3, 0xc0, 0x8e, 0xb5, 0x10, 0xb7, 0x99, 0x93, ++ 0x30, 0x6d, 0x1f, 0xfb, 0xa3, 0xc4, 0xc0, 0xc3, 0xb4, 0xbd, 0xa0, 0xd9, ++ 0x3f, 0x49, 0xa5, 0xfc, 0x34, 0x6a, 0x43, 0xa0, 0x01, 0x4a, 0xd7, 0xa4, ++ 0x70, 0xca, 0x7b, 0x00, 0xbf, 0x09, 0x22, 0x01, 0xf8, 0x75, 0xb8, 0x93, ++ 0x27, 0x81, 0xfe, 0xba, 0xf3, 0x0b, 0x52, 0x20, 0xaa, 0xa8, 0x67, 0x71, ++ 0x9c, 0x51, 0xfb, 0x49, 0x2a, 0xf4, 0x1b, 0xef, 0x4e, 0x45, 0x77, 0x60, ++ 0x5c, 0xeb, 0xca, 0x49, 0x10, 0x1f, 0x9d, 0xb1, 0xcf, 0x66, 0x03, 0x3a, ++ 0x1f, 0xde, 0x64, 0x22, 0x1e, 0x1d, 0xfd, 0x8e, 0x27, 0x81, 0x06, 0xd8, ++ 0x87, 0x1f, 0x77, 0xd8, 0x7d, 0x1d, 0xf0, 0x5f, 0x39, 0xb5, 0x17, 0x20, ++ 0xee, 0x5c, 0xde, 0xbe, 0xb6, 0xc1, 0x01, 0xf5, 0x26, 0xc1, 0xa5, 0xd2, ++ 0xf1, 0xbd, 0x3e, 0xcf, 0x14, 0x07, 0x9d, 0xd7, 0xe6, 0xc6, 0x13, 0x53, ++ 0x2e, 0x04, 0x3e, 0xa4, 0xfd, 0x60, 0x18, 0x6f, 0x13, 0xeb, 0xe7, 0x6d, ++ 0x16, 0x5c, 0x90, 0x2a, 0x5b, 0xda, 0xbe, 0x02, 0xf3, 0x71, 0x4a, 0x9b, ++ 0x05, 0xe2, 0x84, 0xfe, 0x01, 0x81, 0x58, 0xd8, 0xb8, 0x01, 0x0b, 0x1d, ++ 0x77, 0x73, 0x13, 0x7d, 0x9f, 0xd6, 0xcb, 0xe0, 0x7d, 0x18, 0xb7, 0xf9, ++ 0xc4, 0x87, 0xd7, 0x01, 0x9f, 0xbf, 0x23, 0xb2, 0xf7, 0x37, 0xb1, 0x7d, ++ 0xeb, 0x52, 0xfa, 0x9e, 0x0a, 0xf4, 0xda, 0x7c, 0x3b, 0x8e, 0x57, 0xd1, ++ 0x24, 0x90, 0x0c, 0x3a, 0x5e, 0xf9, 0x26, 0x26, 0xff, 0xcb, 0xdf, 0x91, ++ 0x5d, 0xd0, 0xde, 0xba, 0x67, 0x15, 0xea, 0xb1, 0x69, 0xf4, 0x7b, 0x99, ++ 0xb9, 0x20, 0xef, 0x83, 0x93, 0xa1, 0x4e, 0x46, 0x0b, 0x4e, 0xb0, 0xb7, ++ 0x49, 0xf6, 0xcd, 0xc8, 0xd7, 0x3d, 0x9c, 0xaf, 0x49, 0xd7, 0x4c, 0x26, ++ 0x37, 0x04, 0x5e, 0xe7, 0x7e, 0x83, 0x66, 0x37, 0xed, 0x4d, 0x63, 0xf9, ++ 0xc1, 0xa5, 0xae, 0xc5, 0x4a, 0x32, 0x1d, 0xe7, 0xbd, 0xb1, 0xa9, 0xb9, ++ 0x90, 0x26, 0xe0, 0x6d, 0x3b, 0x81, 0xfb, 0xd1, 0x87, 0x29, 0x9c, 0x3d, ++ 0x14, 0xce, 0x1f, 0xf0, 0x7c, 0x8e, 0x7d, 0x63, 0x3f, 0x57, 0x42, 0x3a, ++ 0xfd, 0xf3, 0x59, 0xda, 0x10, 0xa4, 0xc3, 0xf9, 0x6d, 0x13, 0x30, 0xcf, ++ 0x61, 0x01, 0x29, 0xc6, 0x3c, 0x87, 0xe9, 0xe3, 0x98, 0xbd, 0xf6, 0xfe, ++ 0xa5, 0xd6, 0x80, 0x40, 0xe7, 0xf5, 0xbe, 0x1c, 0xce, 0x86, 0xe7, 0xfb, ++ 0x2e, 0x35, 0xa3, 0xfd, 0xdb, 0xbd, 0x59, 0xc6, 0xfd, 0xe2, 0xee, 0x81, ++ 0x21, 0x8c, 0x4f, 0x77, 0x36, 0xc9, 0x04, 0xf2, 0x35, 0x1a, 0x9a, 0x44, ++ 0x94, 0x8b, 0x9d, 0x9b, 0x98, 0x1e, 0x17, 0x57, 0xdf, 0x30, 0x25, 0x13, ++ 0xe0, 0xb7, 0x5e, 0x70, 0x81, 0xdc, 0xdc, 0xd7, 0x34, 0x49, 0x01, 0xbd, ++ 0xd6, 0x19, 0x10, 0xf0, 0xfd, 0x49, 0xab, 0xef, 0x4a, 0x63, 0x7e, 0x0c, ++ 0x93, 0x87, 0x9a, 0xdf, 0x56, 0xea, 0xac, 0x30, 0xe8, 0x8f, 0x68, 0xf9, ++ 0xa6, 0xc9, 0xbf, 0x1a, 0x0e, 0x87, 0x68, 0x39, 0x57, 0xa3, 0xe9, 0x99, ++ 0x28, 0x39, 0x57, 0x03, 0xfb, 0xcd, 0x0e, 0x28, 0x8d, 0xcf, 0xbd, 0xc4, ++ 0xc6, 0xe4, 0x1f, 0xd8, 0xfd, 0x80, 0xf7, 0xe0, 0xf7, 0x48, 0xbf, 0xb5, ++ 0xef, 0xc8, 0x04, 0xec, 0x7e, 0xe1, 0xf3, 0xae, 0x29, 0x98, 0xb7, 0x05, ++ 0x7a, 0x93, 0xb6, 0x8f, 0x6b, 0x17, 0xdc, 0xb0, 0xcf, 0x5f, 0xfe, 0x89, ++ 0x39, 0x80, 0xf6, 0x6a, 0xa0, 0x64, 0xce, 0x4f, 0x41, 0x7e, 0x7f, 0x6a, ++ 0x26, 0x82, 0x0a, 0x79, 0xf0, 0x14, 0xee, 0x54, 0x2e, 0x8c, 0x35, 0x87, ++ 0xff, 0xf8, 0x24, 0x7d, 0xfe, 0xe5, 0x07, 0x16, 0xc8, 0x90, 0xa1, 0x74, ++ 0x52, 0x82, 0x70, 0xd6, 0xf2, 0x45, 0x0b, 0xd7, 0xb3, 0xfc, 0x96, 0xc2, ++ 0x0f, 0x56, 0xa6, 0x95, 0x02, 0x1c, 0x26, 0x27, 0xa3, 0x9c, 0x2d, 0x6b, ++ 0x14, 0x89, 0x47, 0x27, 0x2f, 0xbe, 0x14, 0xdc, 0xd7, 0xdd, 0xcc, 0xe4, ++ 0xb1, 0x73, 0xbd, 0x4e, 0x1e, 0x15, 0x2a, 0xfe, 0x52, 0xd0, 0x5f, 0xce, ++ 0x74, 0x26, 0x07, 0xd5, 0xf5, 0x32, 0xe4, 0x8c, 0x90, 0x6d, 0x5c, 0x3e, ++ 0x51, 0x7b, 0xda, 0x0d, 0x76, 0x43, 0xc5, 0xf6, 0x15, 0x69, 0x0a, 0xed, ++ 0xb7, 0x94, 0xe7, 0x83, 0x54, 0xec, 0x5a, 0x91, 0x46, 0x45, 0x03, 0x69, ++ 0x00, 0xbd, 0x45, 0xfb, 0x57, 0x28, 0x6c, 0xfc, 0x8a, 0xdd, 0x82, 0x73, ++ 0xad, 0x6e, 0x7c, 0xed, 0x7d, 0x6d, 0x3c, 0x6d, 0x1c, 0x65, 0xbb, 0x71, ++ 0x9c, 0x21, 0xbb, 0x78, 0xfd, 0x1c, 0xc7, 0xd1, 0xe6, 0xa1, 0x7d, 0xbf, ++ 0x3f, 0x7b, 0x7c, 0xec, 0x7f, 0x9c, 0x5e, 0x29, 0xd0, 0xf1, 0xc6, 0xbe, ++ 0x2f, 0x62, 0x92, 0xf2, 0xd8, 0xcf, 0xa7, 0x0d, 0xd1, 0xef, 0x77, 0x68, ++ 0xa5, 0x16, 0x7f, 0x2d, 0xfa, 0xd0, 0x44, 0xdc, 0x3a, 0xb8, 0x8d, 0xfd, ++ 0x63, 0x1c, 0x71, 0xeb, 0xe8, 0xa2, 0x75, 0x0c, 0xe5, 0x6f, 0x8a, 0xb7, ++ 0xab, 0xdb, 0x98, 0x3d, 0xd4, 0x3a, 0xe6, 0xa0, 0x52, 0x53, 0x88, 0x75, ++ 0x27, 0xf0, 0x73, 0x2d, 0x8f, 0xd3, 0xd6, 0x4e, 0x66, 0xfb, 0x56, 0xad, ++ 0x05, 0x1f, 0xdc, 0x0f, 0xfc, 0x3d, 0xad, 0x50, 0x40, 0x3a, 0x20, 0x3e, ++ 0x8f, 0x92, 0x9c, 0x82, 0x76, 0x90, 0x0a, 0xf1, 0xf1, 0xb2, 0x42, 0xf6, ++ 0x7e, 0x19, 0x7d, 0x1f, 0xf8, 0xae, 0x75, 0x15, 0xe3, 0x43, 0x2a, 0x0f, ++ 0x54, 0x90, 0x17, 0xb5, 0x4d, 0x2b, 0xa6, 0x60, 0xff, 0x66, 0x41, 0x85, ++ 0xf1, 0x5b, 0xd7, 0x96, 0xa0, 0x9e, 0x2f, 0x1f, 0x2b, 0x12, 0x6c, 0x6f, ++ 0x3e, 0x88, 0x76, 0x47, 0x79, 0xdb, 0xc1, 0x14, 0xe0, 0x57, 0xca, 0x9f, ++ 0x2b, 0x41, 0xef, 0xd6, 0x5e, 0x62, 0x76, 0x02, 0x7f, 0x68, 0x7c, 0xa7, ++ 0xf1, 0xf1, 0xfb, 0x32, 0xcb, 0x0f, 0x21, 0x16, 0xe7, 0x48, 0x38, 0x07, ++ 0x50, 0x96, 0xa6, 0xc6, 0xe4, 0x5f, 0xf1, 0x1d, 0xc2, 0xfc, 0xd4, 0x4d, ++ 0x32, 0xf2, 0x9d, 0x77, 0x2c, 0xe3, 0xcb, 0xf7, 0x37, 0x8b, 0xc8, 0xcf, ++ 0xfb, 0x2e, 0xbd, 0x69, 0x0a, 0xf0, 0x61, 0xf7, 0x7a, 0xa1, 0x1f, 0x3e, ++ 0xa6, 0x7c, 0x5a, 0x18, 0xe1, 0x53, 0x71, 0x35, 0xcb, 0xd7, 0x29, 0xdb, ++ 0xc8, 0xfc, 0x95, 0x7d, 0x4d, 0x4c, 0x3e, 0x74, 0xb6, 0x32, 0x3b, 0x71, ++ 0xd2, 0x6a, 0xf9, 0x6a, 0xa8, 0x97, 0xbd, 0x2b, 0x13, 0x16, 0xf7, 0x62, ++ 0xf6, 0xe0, 0xb9, 0xf2, 0x73, 0x1f, 0x3b, 0x65, 0x43, 0x6c, 0x7e, 0xee, ++ 0x8f, 0x7f, 0xa7, 0xcb, 0x2d, 0x1f, 0xdd, 0x49, 0xe7, 0x77, 0xcd, 0xcb, ++ 0x74, 0xfe, 0x6a, 0x04, 0x5e, 0x93, 0x2e, 0xbb, 0xdb, 0x81, 0x71, 0xfa, ++ 0xcb, 0x66, 0xe1, 0x7a, 0x35, 0x39, 0x54, 0x2a, 0xb1, 0x7c, 0xa6, 0xf9, ++ 0xfe, 0xc5, 0x2c, 0xdf, 0x57, 0x62, 0x79, 0x6f, 0x7f, 0xf7, 0xbc, 0xa2, ++ 0xe6, 0xf1, 0x60, 0x9a, 0x3d, 0x22, 0x47, 0x44, 0xa0, 0xf7, 0x44, 0x96, ++ 0x27, 0xdd, 0x2c, 0x23, 0xbd, 0x47, 0xf3, 0xe3, 0x3f, 0xca, 0x47, 0xff, ++ 0x2c, 0xbe, 0xde, 0xc6, 0xe9, 0x48, 0x9b, 0x8f, 0xb8, 0x8b, 0xbd, 0x0f, ++ 0x79, 0x65, 0x41, 0x0a, 0xc7, 0x5f, 0x6d, 0x7a, 0x1e, 0xf3, 0x5a, 0xbf, ++ 0x7a, 0xe9, 0xe0, 0x74, 0xc0, 0x73, 0xd5, 0x4e, 0x4a, 0xbf, 0x74, 0xbd, ++ 0xdd, 0x9b, 0xec, 0x24, 0x08, 0x72, 0x4b, 0x0a, 0xa0, 0xbe, 0xa9, 0x6c, ++ 0x15, 0x31, 0x7f, 0x9c, 0x48, 0xc1, 0xa2, 0xeb, 0xec, 0x7a, 0xfe, 0x64, ++ 0xf9, 0x49, 0x55, 0xaf, 0xd8, 0x91, 0x6e, 0x2a, 0xb7, 0xb2, 0xbc, 0xd3, ++ 0xca, 0x57, 0x3f, 0xcf, 0xc7, 0x7c, 0x91, 0x25, 0x61, 0xcc, 0xbb, 0xf2, ++ 0xbd, 0xc4, 0xed, 0x4d, 0x5f, 0x28, 0x1f, 0xe8, 0xbb, 0x52, 0x62, 0x79, ++ 0x52, 0xd1, 0xfc, 0x3e, 0x21, 0x9d, 0xd9, 0x9f, 0x5d, 0xdb, 0xe3, 0x67, ++ 0xc2, 0x3a, 0x84, 0x0d, 0x7b, 0x70, 0xbf, 0xb5, 0xb2, 0xe5, 0x26, 0x19, ++ 0xe8, 0xaf, 0x57, 0x7e, 0xa4, 0xcb, 0x5a, 0x3f, 0xdc, 0xc7, 0xf4, 0x51, ++ 0xfa, 0x85, 0x7d, 0x76, 0x98, 0xdf, 0x8c, 0x91, 0xfa, 0xf9, 0x2d, 0x46, ++ 0x3c, 0x75, 0x6d, 0x64, 0xfc, 0x5f, 0xd9, 0x26, 0x07, 0xac, 0x30, 0xbf, ++ 0x0d, 0x6b, 0x31, 0x9e, 0xed, 0xdd, 0x70, 0x02, 0xf3, 0xe3, 0x27, 0xbd, ++ 0xb2, 0x19, 0xe3, 0x08, 0xde, 0x36, 0xd1, 0x98, 0x17, 0xb9, 0x41, 0x0c, ++ 0x9a, 0x31, 0x7f, 0x53, 0x3c, 0x68, 0x46, 0xbf, 0xc6, 0x98, 0x9f, 0x58, ++ 0xdb, 0x5a, 0x83, 0xfb, 0x6e, 0xb5, 0x2d, 0x3c, 0xff, 0x2f, 0x2a, 0x2f, ++ 0xae, 0xea, 0x95, 0x5d, 0xaf, 0xfa, 0x28, 0x68, 0xaa, 0x7e, 0xf9, 0xa2, ++ 0x03, 0xe4, 0xc1, 0xb1, 0x8e, 0xf5, 0x0e, 0x80, 0x27, 0x1d, 0x0f, 0xf3, ++ 0x0a, 0x2f, 0x3b, 0x25, 0x19, 0xf2, 0xa3, 0xfa, 0xcf, 0x07, 0x76, 0x1b, ++ 0xf3, 0x0d, 0x5b, 0x1e, 0xe2, 0xf9, 0x86, 0x57, 0x77, 0x92, 0xfc, 0xbe, ++ 0xf9, 0x86, 0xc7, 0xe0, 0x1f, 0xa0, 0x6f, 0xd2, 0xa3, 0xf2, 0x35, 0x37, ++ 0x24, 0xf3, 0xfc, 0xee, 0x60, 0x51, 0x71, 0x8c, 0x78, 0x7e, 0xef, 0xb9, ++ 0x9f, 0xcd, 0xdf, 0xac, 0x81, 0x3c, 0xf9, 0xae, 0xad, 0xc7, 0xd7, 0xc0, ++ 0xfc, 0xab, 0xff, 0xf6, 0xf5, 0x1a, 0xc8, 0x6f, 0x22, 0xbb, 0xad, 0xa8, ++ 0xa7, 0xbc, 0x2f, 0xfd, 0x0e, 0xf3, 0x8a, 0xb5, 0xf7, 0x16, 0xa7, 0x33, ++ 0x7a, 0xeb, 0xde, 0xf8, 0x22, 0xe6, 0x65, 0x77, 0x7f, 0x6a, 0x46, 0x7f, ++ 0xa7, 0x7b, 0x57, 0x67, 0x0e, 0xe4, 0xb7, 0x75, 0x6f, 0xf9, 0x3e, 0x0d, ++ 0xe2, 0x73, 0x0b, 0x77, 0x5d, 0x8e, 0xf1, 0xcb, 0x85, 0xdb, 0x26, 0xa5, ++ 0x93, 0x18, 0xf2, 0x5e, 0x2b, 0x81, 0x3e, 0x03, 0xe7, 0x90, 0x17, 0x1e, ++ 0x8d, 0x8f, 0x7d, 0xad, 0xfb, 0x30, 0x0f, 0xeb, 0xab, 0x4f, 0xcc, 0x28, ++ 0xdf, 0x7a, 0xf3, 0x47, 0x5b, 0x6a, 0x58, 0x5e, 0xae, 0xca, 0xf3, 0x46, ++ 0x37, 0xc5, 0xce, 0xc3, 0xd7, 0xf2, 0x1c, 0x6b, 0x5b, 0xaf, 0xbb, 0xe6, ++ 0x52, 0x90, 0xd7, 0xad, 0xcc, 0xbe, 0xeb, 0xcd, 0x7b, 0x3c, 0x5b, 0xbe, ++ 0xe8, 0x87, 0x14, 0xaf, 0x17, 0x9d, 0x03, 0xfe, 0x36, 0xf1, 0xbc, 0xe0, ++ 0x96, 0xab, 0x63, 0xe6, 0x8b, 0x7e, 0x05, 0xff, 0xa0, 0x78, 0xfa, 0x79, ++ 0xba, 0x31, 0x5f, 0xf4, 0x9b, 0xd6, 0x05, 0x3f, 0x7f, 0x16, 0xda, 0x5a, ++ 0x93, 0xfb, 0xcd, 0x17, 0x0d, 0x9e, 0x03, 0xdc, 0xb4, 0x3c, 0xff, 0xea, ++ 0x74, 0xf7, 0x4b, 0xe9, 0xc0, 0x47, 0x5b, 0xe3, 0x7d, 0x19, 0x0c, 0x6f, ++ 0x81, 0x69, 0x02, 0xd8, 0x81, 0xdf, 0xe4, 0xc0, 0xf9, 0x88, 0xa3, 0x72, ++ 0x18, 0xf3, 0x40, 0xc2, 0xbb, 0xcc, 0x4e, 0xc8, 0x7b, 0xac, 0xdc, 0xf5, ++ 0x31, 0xf2, 0x4b, 0xf7, 0xb6, 0x0f, 0x30, 0xde, 0x4a, 0x78, 0x9e, 0x7d, ++ 0x37, 0xe9, 0xfd, 0x63, 0xf9, 0xd0, 0x02, 0x5f, 0x67, 0xb3, 0x9d, 0xe5, ++ 0x99, 0x72, 0xf8, 0x43, 0x1e, 0xaa, 0xea, 0xc0, 0xe7, 0x3c, 0xdf, 0x94, ++ 0xd1, 0xb1, 0x96, 0x87, 0xda, 0x5f, 0xfe, 0x69, 0x28, 0x9d, 0x9f, 0x1f, ++ 0xe6, 0xe7, 0x0e, 0x6a, 0xa8, 0xdf, 0xc4, 0xf2, 0xd4, 0x23, 0x79, 0xa9, ++ 0xc2, 0x58, 0xc0, 0xd7, 0x41, 0x43, 0x5e, 0xaf, 0xb6, 0xee, 0xe8, 0xf1, ++ 0x9c, 0x5c, 0x8e, 0x46, 0xf2, 0xaa, 0x63, 0xe7, 0xf9, 0x6a, 0x79, 0x84, ++ 0x7d, 0xf1, 0xc5, 0xf4, 0x8a, 0x96, 0x37, 0xdd, 0xbd, 0x96, 0xe7, 0x5b, ++ 0xd3, 0xe7, 0xd9, 0xa3, 0x20, 0x4f, 0x8e, 0xe9, 0x73, 0x6f, 0x40, 0xf8, ++ 0x38, 0x16, 0x7e, 0xb5, 0xbc, 0xea, 0x3f, 0x44, 0xe1, 0x57, 0x5b, 0x5f, ++ 0x7f, 0x7c, 0xa1, 0xf1, 0xe7, 0xd9, 0xe6, 0xfd, 0x5f, 0x85, 0xcb, 0xbb, ++ 0xe9, 0x2c, 0x9e, 0xad, 0xc1, 0xa7, 0xeb, 0x2f, 0xb1, 0xe5, 0xf4, 0xb7, ++ 0x9c, 0xdf, 0xa9, 0xdf, 0xfa, 0x4d, 0xba, 0xce, 0xbf, 0x9d, 0xc3, 0xfd, ++ 0x56, 0x0d, 0x6e, 0xda, 0x7c, 0x97, 0xb6, 0x30, 0xbb, 0xa2, 0x6b, 0x03, ++ 0xf3, 0x1f, 0xa2, 0xf9, 0x9b, 0xae, 0xc7, 0x1d, 0x2b, 0xcf, 0x5e, 0xca, ++ 0x60, 0xf6, 0x6f, 0x6d, 0xdb, 0x9e, 0x7c, 0x90, 0x43, 0x5d, 0x7b, 0xb7, ++ 0x73, 0xba, 0x63, 0x74, 0x5d, 0xbb, 0xe9, 0x20, 0xcb, 0xd3, 0xa5, 0x72, ++ 0x3b, 0xa0, 0x97, 0xdb, 0x84, 0xc5, 0x91, 0xa3, 0xc7, 0x73, 0xf0, 0xf1, ++ 0xbc, 0xed, 0xb1, 0xc7, 0xf3, 0x6e, 0x3a, 0x11, 0x73, 0xbc, 0x63, 0x92, ++ 0xfb, 0x26, 0x98, 0xff, 0xb1, 0x0e, 0x66, 0x47, 0x1d, 0x6b, 0x11, 0xa7, ++ 0x06, 0x62, 0x8c, 0x7f, 0x9a, 0xeb, 0xa5, 0xde, 0x75, 0xdb, 0x15, 0xcc, ++ 0x97, 0x12, 0x1d, 0x71, 0x68, 0x4f, 0x2d, 0xb4, 0x8f, 0xfd, 0x24, 0x21, ++ 0x05, 0x4a, 0x05, 0xf3, 0x7e, 0x1a, 0x16, 0xf3, 0x3c, 0xa1, 0xfb, 0x5c, ++ 0x19, 0x00, 0xe7, 0x06, 0xfb, 0x95, 0x04, 0xe6, 0xf3, 0x00, 0xc0, 0x47, ++ 0x17, 0x7f, 0x90, 0x9d, 0x1e, 0x02, 0x76, 0x9c, 0x9c, 0x51, 0x5c, 0x28, ++ 0xaa, 0x91, 0xf9, 0x6a, 0xed, 0x4a, 0x8a, 0x89, 0x04, 0xf4, 0xf8, 0x97, ++ 0x82, 0xd9, 0x20, 0xdf, 0x0f, 0x14, 0x74, 0xca, 0x30, 0xde, 0x67, 0x51, ++ 0x71, 0x93, 0xcf, 0x24, 0xb2, 0x34, 0x9d, 0xce, 0xeb, 0x33, 0x9f, 0xe0, ++ 0x5a, 0xac, 0xf6, 0x6f, 0x77, 0x6b, 0x75, 0xcf, 0xbd, 0xa2, 0x21, 0xce, ++ 0x51, 0x6b, 0x0e, 0x1f, 0x00, 0xfb, 0x9d, 0xbc, 0x6e, 0xc5, 0xb8, 0xb5, ++ 0xb8, 0xdb, 0xea, 0xc3, 0xb8, 0xd9, 0x1a, 0x2b, 0xae, 0x73, 0xdf, 0xb6, ++ 0xef, 0x5e, 0x00, 0x78, 0x75, 0xff, 0xdc, 0x4c, 0xd8, 0x3e, 0x02, 0x25, ++ 0x0c, 0x2a, 0x17, 0xca, 0x78, 0xfc, 0xa2, 0x73, 0xdb, 0x77, 0x6b, 0xfe, ++ 0x0c, 0x76, 0x26, 0xbc, 0x4c, 0xbf, 0x5f, 0xb6, 0x86, 0xf6, 0x07, 0xfb, ++ 0x7a, 0x53, 0x3c, 0xfa, 0x03, 0x3d, 0x5b, 0x13, 0xf2, 0xd1, 0x9e, 0x7c, ++ 0xfd, 0x9e, 0xe9, 0x20, 0x37, 0xca, 0x40, 0x87, 0x81, 0x9d, 0xf7, 0x4a, ++ 0x7a, 0xa0, 0x81, 0x8e, 0x77, 0x24, 0x95, 0xd5, 0x8f, 0x6c, 0x1e, 0x88, ++ 0xe7, 0x09, 0xaa, 0xb6, 0xda, 0x31, 0xdf, 0x70, 0xdf, 0xb6, 0xd7, 0x6a, ++ 0x41, 0xfe, 0x77, 0xbf, 0x12, 0x0f, 0xdb, 0xd1, 0xe4, 0x2b, 0x39, 0xf4, ++ 0x37, 0xa8, 0x7b, 0x77, 0x26, 0x90, 0xb5, 0x2a, 0xda, 0x81, 0xaa, 0x5e, ++ 0xdf, 0x56, 0x10, 0x49, 0xd5, 0xdb, 0x79, 0x55, 0x50, 0x37, 0xe4, 0xbf, ++ 0x10, 0xf4, 0xd3, 0x31, 0x1e, 0x47, 0xe9, 0xb9, 0xaa, 0x2d, 0x01, 0xcf, ++ 0x8f, 0xe8, 0xfa, 0x71, 0x7e, 0xf6, 0x65, 0xb1, 0xf3, 0x32, 0xc1, 0x2c, ++ 0xe0, 0x3b, 0x6a, 0x4f, 0x1a, 0xbe, 0xa3, 0xb5, 0x5f, 0x9f, 0x31, 0x98, ++ 0x9f, 0xef, 0x0d, 0xff, 0x84, 0xdd, 0xaf, 0xc0, 0xfa, 0x7b, 0x95, 0x70, ++ 0x29, 0xab, 0xfb, 0xb3, 0x18, 0xdf, 0x76, 0x60, 0xff, 0x12, 0x8d, 0x5e, ++ 0x79, 0x7b, 0xdf, 0x71, 0x59, 0xff, 0x39, 0x19, 0x83, 0x0d, 0xfd, 0xb4, ++ 0xf7, 0x6b, 0xcd, 0xa4, 0x2e, 0x16, 0x1f, 0x54, 0x67, 0x08, 0xfc, 0x7c, ++ 0xef, 0x5f, 0x87, 0xc5, 0xba, 0xcf, 0x22, 0xc6, 0xfc, 0xf1, 0xf9, 0x5d, ++ 0x02, 0xf1, 0x99, 0xc0, 0x0e, 0xd8, 0x62, 0x0d, 0x40, 0x5c, 0xa3, 0x5a, ++ 0x09, 0x0e, 0x85, 0xfc, 0xf6, 0x57, 0x15, 0xb6, 0x3f, 0x52, 0xed, 0x08, ++ 0x0e, 0x85, 0xfc, 0xf6, 0x9d, 0x5c, 0xfe, 0x55, 0xc7, 0xd1, 0x3a, 0x7d, ++ 0x9e, 0xc5, 0xe7, 0x01, 0xfd, 0xa1, 0x4e, 0x2c, 0xa1, 0x97, 0x01, 0xdf, ++ 0x35, 0xaf, 0x59, 0x09, 0xe4, 0x27, 0xd5, 0xbc, 0x6e, 0x77, 0x03, 0x9e, ++ 0x6b, 0x5e, 0xfd, 0xee, 0xc8, 0x73, 0x85, 0x90, 0xcf, 0x16, 0x8f, 0x71, ++ 0xab, 0x9a, 0xd7, 0xff, 0x1d, 0xf1, 0x5f, 0x63, 0x0e, 0xce, 0x06, 0xfa, ++ 0x0f, 0x6f, 0x31, 0x93, 0x75, 0xb4, 0x7f, 0xd7, 0x96, 0xb7, 0x73, 0xc0, ++ 0x8e, 0xe8, 0x92, 0x83, 0x39, 0x49, 0x67, 0xd8, 0xf7, 0xa9, 0x69, 0x31, ++ 0x1b, 0xf6, 0xb1, 0xb5, 0x75, 0x1c, 0xab, 0x0f, 0x9c, 0x07, 0xe7, 0xd7, ++ 0xb5, 0x73, 0x8b, 0x95, 0xfd, 0xc8, 0x8b, 0x5d, 0x19, 0xcc, 0x1e, 0x5d, ++ 0x91, 0xe1, 0x7e, 0x3c, 0x03, 0xf9, 0xda, 0xe6, 0x44, 0x79, 0x0d, 0xe3, ++ 0x89, 0x30, 0x4e, 0xdb, 0x10, 0xfd, 0xb9, 0xe6, 0x4a, 0x35, 0xb6, 0x1c, ++ 0x6b, 0xca, 0x90, 0x0d, 0xe7, 0x68, 0xc5, 0xc8, 0x39, 0xc5, 0x26, 0x18, ++ 0xf7, 0x2b, 0x12, 0x5a, 0x9a, 0x45, 0x51, 0x52, 0x23, 0x84, 0x71, 0xff, ++ 0xbc, 0x72, 0xc3, 0x89, 0x91, 0xe0, 0x0f, 0x7f, 0xf6, 0xb3, 0x0b, 0x71, ++ 0x5f, 0xeb, 0x33, 0x25, 0x3c, 0x12, 0xe4, 0xf6, 0x67, 0x39, 0xe1, 0x91, ++ 0x7a, 0x79, 0x7c, 0xb4, 0xde, 0xa2, 0x4a, 0x32, 0xc6, 0x25, 0xb0, 0xec, ++ 0x59, 0x7b, 0xa2, 0x34, 0x8b, 0x40, 0xfe, 0xa0, 0x75, 0x66, 0x2c, 0xf9, ++ 0xb4, 0x39, 0x23, 0x1e, 0xe7, 0x51, 0x79, 0x6f, 0x7c, 0xcc, 0xf3, 0xa0, ++ 0x3b, 0x38, 0xbd, 0xad, 0x06, 0x1a, 0x4c, 0x65, 0xdf, 0x85, 0x38, 0x84, ++ 0xf6, 0xdd, 0xcf, 0x94, 0x80, 0x02, 0xf3, 0xc8, 0xcb, 0x54, 0xb1, 0xbd, ++ 0x32, 0x3b, 0xa0, 0xc0, 0xf3, 0xaa, 0x0d, 0xdb, 0x87, 0x18, 0xee, 0x9d, ++ 0x90, 0xfc, 0xd8, 0x8f, 0xf2, 0x17, 0xc2, 0xa3, 0x82, 0xac, 0x54, 0x0a, ++ 0x6d, 0x7d, 0xe5, 0x4a, 0xc5, 0x22, 0x9b, 0x2a, 0xe1, 0xf9, 0x68, 0xe9, ++ 0x3f, 0x7b, 0xe9, 0x4d, 0x8c, 0xe0, 0x09, 0x83, 0x9c, 0x90, 0xa7, 0xc6, ++ 0x71, 0x48, 0x35, 0x13, 0xc6, 0x41, 0xb5, 0xf3, 0x00, 0x92, 0x5c, 0x6c, ++ 0x01, 0x78, 0x29, 0xa4, 0xd8, 0x29, 0x89, 0x80, 0x6a, 0x3f, 0xf2, 0x69, ++ 0x1c, 0x69, 0xc1, 0xd2, 0x46, 0xcd, 0x11, 0xa6, 0x87, 0xea, 0x08, 0xe4, ++ 0x15, 0x1d, 0xe5, 0xfb, 0xb7, 0x66, 0x49, 0x7d, 0x1c, 0xe4, 0x87, 0x79, ++ 0xbf, 0x88, 0xf2, 0xfc, 0x6c, 0x70, 0xfb, 0x55, 0x86, 0x03, 0xe7, 0x6d, ++ 0x96, 0xea, 0x88, 0x0b, 0xed, 0x8e, 0x69, 0x4e, 0xb0, 0xab, 0x05, 0x9f, ++ 0x87, 0xfc, 0x40, 0xe9, 0xa1, 0xa1, 0x7e, 0xc3, 0x90, 0xc3, 0x6c, 0xff, ++ 0xdf, 0x0d, 0xf9, 0x70, 0x0e, 0xc2, 0xe6, 0xe7, 0x70, 0xbe, 0xf5, 0x3d, ++ 0xd8, 0x07, 0x94, 0xce, 0xd0, 0xcf, 0xf6, 0x5d, 0x46, 0x02, 0x0d, 0xf4, ++ 0x7b, 0x92, 0xc2, 0xea, 0x64, 0x22, 0x09, 0xc4, 0xda, 0x8f, 0xef, 0xe2, ++ 0x78, 0x20, 0xbe, 0x3d, 0x28, 0x7f, 0x6c, 0x24, 0xf2, 0x17, 0xa6, 0xf5, ++ 0x78, 0x94, 0x50, 0xf4, 0xbb, 0x09, 0x7f, 0x1b, 0x0b, 0x7e, 0xae, 0xcd, ++ 0x49, 0x82, 0x60, 0x37, 0xc5, 0xdb, 0x48, 0x30, 0x9e, 0x96, 0xb6, 0x3c, ++ 0xe9, 0x98, 0x9e, 0x7f, 0x1d, 0x84, 0xd5, 0x07, 0x53, 0x72, 0x06, 0xb9, ++ 0xe6, 0xbc, 0xc4, 0xd8, 0x1e, 0x4d, 0xd7, 0xc4, 0x25, 0x9d, 0xea, 0x95, ++ 0x8b, 0x22, 0xbe, 0x7f, 0x2a, 0xea, 0xfd, 0x53, 0x67, 0x7a, 0x5f, 0x83, ++ 0x87, 0xd7, 0x32, 0x24, 0x97, 0x9d, 0x7f, 0x67, 0x70, 0x89, 0xe3, 0x6b, ++ 0xf0, 0x4d, 0x74, 0x9d, 0x0e, 0x01, 0x3c, 0xf2, 0x1d, 0xae, 0x06, 0xc0, ++ 0xa3, 0x12, 0x3e, 0x70, 0x0f, 0xc0, 0x23, 0xdf, 0xc6, 0xfc, 0xc4, 0x94, ++ 0x46, 0xa2, 0xf7, 0xe3, 0x86, 0x64, 0x32, 0x79, 0x75, 0xbf, 0xc0, 0xf4, ++ 0x25, 0xfd, 0x2b, 0xb6, 0xe9, 0xc6, 0x23, 0x4e, 0x0b, 0xc6, 0x4f, 0x1f, ++ 0xe2, 0x70, 0xef, 0xed, 0xaf, 0xc5, 0x55, 0xfa, 0xf4, 0xb7, 0x4a, 0x00, ++ 0xd7, 0x3e, 0xfd, 0xad, 0xfd, 0xf5, 0x8f, 0x8b, 0xdd, 0xdf, 0xde, 0xdf, ++ 0x7c, 0xe2, 0x63, 0xcf, 0x27, 0xb1, 0x9f, 0xf1, 0x7d, 0xb1, 0xfb, 0xd7, ++ 0xbe, 0xfe, 0xf1, 0x7b, 0x41, 0x15, 0x1e, 0x32, 0xb9, 0x21, 0x11, 0x93, ++ 0x76, 0x0e, 0x7a, 0x48, 0x26, 0xf8, 0x5b, 0x09, 0x07, 0xd2, 0x4a, 0x18, ++ 0x55, 0xb0, 0x7d, 0x82, 0x28, 0xbc, 0xc5, 0x01, 0xfd, 0x51, 0x7a, 0x88, ++ 0x3b, 0x4f, 0xf7, 0x1c, 0xfe, 0x2f, 0x4f, 0x87, 0xbf, 0xc1, 0x31, 0xf0, ++ 0x4f, 0x82, 0x48, 0x77, 0x25, 0x7c, 0x3e, 0xb4, 0x6e, 0xcb, 0xa4, 0xf3, ++ 0xbb, 0x99, 0x4f, 0x77, 0x72, 0x33, 0xdb, 0xc7, 0xbc, 0x75, 0x21, 0x8b, ++ 0x23, 0xdd, 0x7c, 0x2f, 0x3b, 0x2f, 0x74, 0xf0, 0x67, 0xec, 0xdc, 0xfe, ++ 0xad, 0x8d, 0xcc, 0xdf, 0xbe, 0x75, 0x11, 0xdb, 0x37, 0x23, 0xe5, 0xec, ++ 0x1c, 0x90, 0x93, 0xfe, 0x07, 0xdf, 0xbb, 0x0d, 0x06, 0xa1, 0xf8, 0xbe, ++ 0xcd, 0x2f, 0x04, 0x82, 0xb9, 0x70, 0x0f, 0x4e, 0x94, 0xfd, 0xda, 0x7b, ++ 0xdf, 0xce, 0x5d, 0x12, 0xf4, 0x2f, 0x89, 0x8a, 0xc7, 0x68, 0xf4, 0xa4, ++ 0x9d, 0x5b, 0x9a, 0xc7, 0xed, 0xeb, 0x5c, 0x4e, 0x9f, 0x0b, 0x48, 0xd8, ++ 0x0e, 0x7c, 0x1f, 0x7d, 0x8e, 0xbe, 0x35, 0x83, 0xe5, 0xa5, 0x51, 0x77, ++ 0xcc, 0x0d, 0xeb, 0xbb, 0x85, 0xaf, 0x4f, 0xd3, 0x03, 0xbe, 0x15, 0x64, ++ 0x38, 0xdc, 0x0b, 0x20, 0x9a, 0xe2, 0x5c, 0xb0, 0x3f, 0x22, 0xf2, 0x73, ++ 0xab, 0xc4, 0xa1, 0xb0, 0xbc, 0xe5, 0xeb, 0x93, 0x0c, 0xf2, 0xe7, 0xe4, ++ 0x70, 0x35, 0x01, 0xf4, 0x1d, 0x79, 0x83, 0x3f, 0xe7, 0xf7, 0x11, 0xdd, ++ 0x71, 0x85, 0x9a, 0xae, 0x3f, 0xe7, 0x25, 0x9d, 0x8e, 0xc7, 0xfb, 0x47, ++ 0x1a, 0x64, 0x57, 0x06, 0xc8, 0x45, 0xf9, 0xf4, 0x55, 0x44, 0xa5, 0x7c, ++ 0xa1, 0x9c, 0x1e, 0x42, 0x54, 0xdd, 0x39, 0x34, 0x6a, 0xdf, 0x21, 0xb3, ++ 0xcb, 0x4e, 0x82, 0x71, 0x1c, 0xc9, 0x59, 0x4c, 0xca, 0xc0, 0x2e, 0x4c, ++ 0xe4, 0x74, 0x96, 0x72, 0x65, 0xaf, 0x1d, 0xf6, 0x3e, 0x85, 0xcb, 0x1d, ++ 0x2b, 0x54, 0x3c, 0x07, 0x7b, 0x53, 0x26, 0xd3, 0x2f, 0x0f, 0x67, 0x15, ++ 0x2f, 0x00, 0xba, 0x10, 0x1d, 0x63, 0x5d, 0x1e, 0x5b, 0x5f, 0xbc, 0xfa, ++ 0xb6, 0xb1, 0xf5, 0x35, 0xc0, 0xfa, 0x72, 0xfb, 0xce, 0xbb, 0x41, 0x71, ++ 0xb9, 0xd0, 0x0e, 0xbd, 0x92, 0x5a, 0x10, 0x18, 0xef, 0x71, 0x59, 0x60, ++ 0x3e, 0xa2, 0x59, 0xfd, 0x58, 0x05, 0xfe, 0xfc, 0x8d, 0x4c, 0xc0, 0xff, ++ 0xef, 0x0b, 0x07, 0x86, 0xcf, 0x93, 0x29, 0x49, 0x01, 0xc8, 0x7f, 0x99, ++ 0xef, 0x78, 0xf8, 0x00, 0xd0, 0xed, 0xf2, 0x7a, 0x27, 0xee, 0xa3, 0x2d, ++ 0xab, 0x1f, 0x8e, 0xe5, 0xc3, 0xf5, 0x19, 0x68, 0x87, 0x2e, 0xad, 0x77, ++ 0x61, 0xa9, 0xc1, 0xc5, 0xe2, 0xf2, 0xbb, 0x45, 0x0a, 0x67, 0xcb, 0x79, ++ 0x6c, 0x3c, 0x8b, 0xd3, 0xc3, 0xec, 0x0c, 0xaa, 0x87, 0x20, 0xff, 0x42, ++ 0x72, 0xd6, 0x05, 0xa1, 0x6e, 0xc9, 0xae, 0x23, 0x60, 0xff, 0x5a, 0x7b, ++ 0xe1, 0xe3, 0x47, 0xf8, 0x28, 0xbd, 0x75, 0x0f, 0xd6, 0xcd, 0x50, 0xa7, ++ 0xa5, 0xdc, 0x38, 0x0d, 0xe1, 0x4b, 0xdf, 0x27, 0x65, 0x10, 0x47, 0xcd, ++ 0xf2, 0x2c, 0x07, 0xf8, 0x58, 0xd5, 0x0b, 0x88, 0xaa, 0xa3, 0x0b, 0x73, ++ 0xc6, 0x28, 0x43, 0xbd, 0x0f, 0xdc, 0x34, 0xfa, 0xd8, 0xcc, 0xe0, 0xf7, ++ 0xa8, 0xc0, 0xe8, 0x23, 0x1a, 0x7e, 0x8f, 0xca, 0x1d, 0x2a, 0xec, 0x3f, ++ 0x3f, 0x7a, 0x45, 0xef, 0xbd, 0x36, 0x08, 0x3f, 0x6a, 0xee, 0x33, 0xf8, ++ 0xfd, 0x9a, 0xed, 0xcf, 0xf5, 0x0b, 0x3f, 0x67, 0x12, 0xda, 0xb3, 0xf3, ++ 0x8b, 0x96, 0xce, 0x6e, 0xa0, 0x8f, 0x1e, 0xe1, 0xfb, 0x90, 0x0f, 0xd6, ++ 0x8f, 0x45, 0x78, 0x3d, 0x04, 0x79, 0x5d, 0xc3, 0xc0, 0x3f, 0x70, 0x63, ++ 0x29, 0x02, 0xfc, 0x28, 0x1d, 0x99, 0xf3, 0x7c, 0x44, 0xa4, 0xef, 0x9b, ++ 0x55, 0x36, 0x67, 0xb3, 0xad, 0xd8, 0x6d, 0x2a, 0x64, 0xb4, 0x0b, 0xf0, ++ 0x13, 0x6d, 0x0c, 0x9e, 0xe6, 0x8c, 0x3a, 0xdc, 0x8f, 0xb3, 0xd8, 0x18, ++ 0xbc, 0x44, 0x9b, 0x0f, 0xe1, 0x22, 0xdb, 0x18, 0xbc, 0x44, 0x1b, 0xa3, ++ 0x37, 0x85, 0xd7, 0x25, 0x80, 0xdf, 0x68, 0x7c, 0x1f, 0x9f, 0x53, 0xf8, ++ 0xb5, 0x66, 0x8e, 0x01, 0x3c, 0x8c, 0x37, 0xc0, 0x4b, 0x49, 0x99, 0x78, ++ 0x6e, 0xf0, 0x5b, 0x45, 0xe1, 0x47, 0xe7, 0x91, 0xc2, 0xf9, 0x2b, 0x1a, ++ 0x0e, 0x29, 0x70, 0x4e, 0x21, 0x2f, 0xc2, 0x57, 0xfd, 0xd9, 0x75, 0x4f, ++ 0xd1, 0xf5, 0x83, 0x1e, 0x7f, 0x86, 0xc2, 0x07, 0xca, 0xd4, 0x7e, 0xfc, ++ 0xc7, 0xd4, 0x2c, 0x26, 0x47, 0x53, 0x4c, 0x75, 0x7b, 0x64, 0x80, 0x47, ++ 0x12, 0xe1, 0xfa, 0xc5, 0x47, 0xb2, 0x8b, 0x08, 0x4b, 0x55, 0x84, 0xbf, ++ 0x0c, 0x1f, 0x51, 0xa1, 0x2e, 0xb0, 0x79, 0x90, 0x66, 0x23, 0x5e, 0x45, ++ 0xa7, 0x14, 0x75, 0xef, 0x9b, 0xfa, 0x0c, 0xd0, 0xc1, 0xca, 0xb7, 0x65, ++ 0x13, 0xec, 0x93, 0x8a, 0x8b, 0xae, 0x32, 0x9c, 0x27, 0x15, 0x67, 0xba, ++ 0x13, 0x55, 0x84, 0xa7, 0x47, 0x00, 0xfd, 0xfc, 0x48, 0xbd, 0x8a, 0xf8, ++ 0x5b, 0x01, 0x78, 0x1c, 0x06, 0xfa, 0x91, 0xf9, 0x63, 0x0f, 0x70, 0x7c, ++ 0x3e, 0x08, 0x7c, 0x82, 0xf8, 0x65, 0xfc, 0xf1, 0x28, 0xe7, 0x97, 0xc7, ++ 0x39, 0x9f, 0x34, 0xb8, 0xd8, 0xf9, 0x89, 0xe5, 0x53, 0x59, 0x5e, 0x56, ++ 0x4a, 0x81, 0x89, 0xdf, 0x87, 0x16, 0x24, 0xfa, 0xbc, 0xa7, 0x44, 0x57, ++ 0x0b, 0x51, 0xe8, 0xbc, 0xd0, 0xc6, 0x56, 0xb1, 0x0c, 0xa2, 0x9d, 0xf1, ++ 0x89, 0x39, 0x70, 0x3e, 0x7d, 0x2f, 0x3e, 0x8f, 0xb8, 0x81, 0x4e, 0x12, ++ 0x3f, 0xb9, 0x3b, 0x80, 0x6b, 0x25, 0xc5, 0x99, 0x60, 0x17, 0x25, 0x72, ++ 0xfb, 0x97, 0x5c, 0xa2, 0x26, 0xce, 0xc2, 0x83, 0xb4, 0x41, 0x89, 0xf9, ++ 0x21, 0x54, 0x14, 0xa2, 0x5f, 0xd3, 0x61, 0x8a, 0x75, 0x0f, 0x56, 0x83, ++ 0x6b, 0xaf, 0x05, 0xe2, 0xa6, 0xfd, 0xcd, 0x67, 0xcf, 0x8c, 0x57, 0x91, ++ 0x2e, 0x4b, 0x2f, 0xc2, 0xf4, 0x60, 0x92, 0xec, 0x29, 0x9e, 0xb5, 0x80, ++ 0xd6, 0x6d, 0x8d, 0xf1, 0x18, 0x1f, 0x8c, 0x77, 0x79, 0x8a, 0x1e, 0x00, ++ 0x3e, 0x6f, 0xb4, 0x23, 0x9d, 0xda, 0xe8, 0xfc, 0xcb, 0x74, 0x78, 0x8f, ++ 0xef, 0x07, 0xaf, 0xcf, 0x66, 0x5d, 0x61, 0xca, 0xa2, 0x74, 0x28, 0x82, ++ 0xd1, 0x46, 0xf1, 0xfb, 0x44, 0xe3, 0x10, 0x2b, 0xc0, 0xf9, 0x29, 0xb9, ++ 0x38, 0x13, 0xe4, 0xeb, 0x53, 0x5c, 0xcf, 0x52, 0x1c, 0xa8, 0xfa, 0x7d, ++ 0xa8, 0x2e, 0x2e, 0x27, 0x1d, 0x85, 0x17, 0x18, 0xfc, 0xd9, 0x95, 0xb2, ++ 0x1b, 0xdf, 0x73, 0x5e, 0x62, 0x94, 0x03, 0x2b, 0xb9, 0xdc, 0x4d, 0x9a, ++ 0x6c, 0xa4, 0x77, 0x4d, 0xee, 0x7e, 0xd4, 0x2b, 0x77, 0x3d, 0xa9, 0x30, ++ 0x9f, 0xb4, 0xd3, 0x93, 0x91, 0x1f, 0x53, 0xae, 0x8d, 0x2d, 0x7f, 0x1b, ++ 0x64, 0xc5, 0x07, 0xf7, 0x0a, 0x34, 0x8c, 0x64, 0xfc, 0xee, 0x2b, 0x51, ++ 0xd0, 0xfe, 0x8b, 0x21, 0x0f, 0x30, 0xae, 0x7d, 0xd2, 0x33, 0x74, 0x1d, ++ 0xc8, 0x53, 0x8d, 0xbe, 0x96, 0x10, 0x26, 0x7f, 0x7c, 0x24, 0xce, 0x85, ++ 0xfa, 0x88, 0xdf, 0xa3, 0xa3, 0xd9, 0xc7, 0xcb, 0xe0, 0xbe, 0x41, 0x2e, ++ 0x67, 0xa1, 0x14, 0xcf, 0x53, 0x90, 0x6e, 0xd2, 0x6e, 0x35, 0x61, 0x7e, ++ 0xde, 0x72, 0x7e, 0x5f, 0xd6, 0x63, 0x94, 0xbe, 0xa0, 0xf4, 0x53, 0xfa, ++ 0x82, 0xf2, 0xd2, 0x2c, 0xb6, 0x9f, 0xb1, 0xc4, 0x32, 0x0a, 0xef, 0x6d, ++ 0x6b, 0xb0, 0x99, 0x50, 0x5e, 0x48, 0x9f, 0x9a, 0x03, 0x36, 0xb0, 0x57, ++ 0xf7, 0x8c, 0x73, 0x42, 0x1c, 0x41, 0x92, 0x5d, 0x1d, 0x6e, 0x88, 0x07, ++ 0xda, 0xa5, 0x96, 0x75, 0x04, 0xfa, 0x15, 0x5a, 0xe0, 0x3e, 0x09, 0x21, ++ 0xb1, 0xd0, 0x09, 0x74, 0xf0, 0xad, 0x7d, 0xfe, 0xa0, 0x33, 0xe5, 0xe1, ++ 0x51, 0x74, 0x0a, 0x40, 0x47, 0xce, 0x94, 0x62, 0x72, 0x28, 0x0f, 0x77, ++ 0x0f, 0xf0, 0x5c, 0xb3, 0xec, 0xbc, 0x96, 0x40, 0x5c, 0xf1, 0x99, 0x94, ++ 0x3a, 0x2b, 0xc0, 0x2d, 0x2f, 0x8b, 0xf9, 0x5d, 0x8d, 0x25, 0x45, 0x08, ++ 0x47, 0x0a, 0xdf, 0x89, 0x59, 0xa9, 0x91, 0x71, 0xd2, 0x67, 0x5e, 0xd9, ++ 0x7b, 0xdf, 0x16, 0x0c, 0xfb, 0x4c, 0x3f, 0xe7, 0xa3, 0xa7, 0x67, 0x71, ++ 0x3b, 0x3a, 0xdb, 0x47, 0xce, 0xd3, 0xf1, 0x7b, 0xa3, 0xc0, 0xed, 0x30, ++ 0xd5, 0x47, 0x86, 0xeb, 0xf8, 0x7e, 0xc9, 0xf9, 0x53, 0x08, 0xec, 0x2b, ++ 0xf5, 0xe5, 0xf7, 0x7e, 0xe4, 0xd9, 0x7a, 0x26, 0xcf, 0xee, 0x17, 0x62, ++ 0xcb, 0x33, 0xcd, 0xfe, 0xd4, 0xe4, 0x99, 0x1c, 0x25, 0x27, 0xb4, 0x72, ++ 0xe9, 0xa0, 0xa9, 0x86, 0xf3, 0x5d, 0x4a, 0x8a, 0x0b, 0x68, 0x17, 0x4a, ++ 0x9f, 0x89, 0xa2, 0x48, 0xf2, 0x5d, 0xf4, 0xe8, 0x2d, 0x89, 0x08, 0x87, ++ 0x79, 0x00, 0x07, 0x92, 0x71, 0x65, 0xaf, 0x5f, 0xfb, 0xe3, 0xc1, 0x60, ++ 0x57, 0x16, 0xc5, 0xa4, 0xb7, 0x68, 0x39, 0x36, 0xbf, 0x57, 0xaf, 0xbb, ++ 0xd3, 0x00, 0x4f, 0x47, 0x65, 0x35, 0x7d, 0x16, 0xd0, 0xd3, 0xdb, 0xfd, ++ 0xe9, 0x75, 0x77, 0x29, 0xd2, 0xa1, 0x7f, 0x80, 0x0a, 0x7a, 0x69, 0xcf, ++ 0x13, 0x57, 0x61, 0x5c, 0xe7, 0xf0, 0x13, 0x76, 0x15, 0xe4, 0x50, 0xd9, ++ 0xe9, 0x87, 0x50, 0x3f, 0x94, 0x9e, 0x1e, 0x87, 0x65, 0x79, 0xe3, 0x15, ++ 0xa8, 0xcf, 0x85, 0x27, 0xaf, 0x2e, 0x02, 0x7a, 0xe8, 0x6c, 0xba, 0x3c, ++ 0xff, 0x53, 0x88, 0xf3, 0xf8, 0xed, 0xa8, 0xb7, 0x3b, 0x1b, 0x27, 0x0d, ++ 0xc5, 0xfd, 0x48, 0x7f, 0xbc, 0x0a, 0xf9, 0x1d, 0x9d, 0x8d, 0xb4, 0xbd, ++ 0x30, 0xd2, 0x0e, 0xf9, 0xe2, 0xa2, 0x2e, 0x5f, 0x80, 0x40, 0xf4, 0x5d, ++ 0x77, 0xfe, 0x9b, 0x14, 0xaa, 0x68, 0x97, 0x6a, 0xf7, 0x9e, 0x51, 0xbf, ++ 0xce, 0x31, 0x1e, 0xe2, 0x42, 0xab, 0x45, 0x3c, 0xd7, 0x54, 0xfa, 0xa4, ++ 0xdd, 0x0d, 0xf6, 0x67, 0x7f, 0xf4, 0x57, 0xda, 0x14, 0x3b, 0x1e, 0x00, ++ 0xba, 0x16, 0xe2, 0xae, 0xf4, 0x83, 0xc3, 0xc1, 0x8e, 0xde, 0xe3, 0x18, ++ 0x1f, 0x0e, 0xd2, 0x71, 0xe7, 0xaf, 0x63, 0xfb, 0x08, 0x0d, 0x8a, 0xfb, ++ 0x48, 0x10, 0xec, 0xa6, 0x27, 0xac, 0xb8, 0x0f, 0xd9, 0x90, 0x14, 0xfb, ++ 0x5e, 0x90, 0x05, 0x59, 0x97, 0x2f, 0x07, 0x39, 0xb0, 0x20, 0xcb, 0xfd, ++ 0x14, 0xe2, 0xc9, 0xc6, 0xee, 0x29, 0xed, 0x9f, 0x1f, 0xd8, 0xf7, 0x8f, ++ 0xc0, 0x26, 0x33, 0xec, 0x63, 0x3d, 0xcb, 0xef, 0x47, 0x91, 0x3c, 0x8e, ++ 0x19, 0x86, 0x7d, 0x36, 0xb6, 0x8f, 0x75, 0x84, 0xc7, 0x59, 0x88, 0xa5, ++ 0x9f, 0xf6, 0x38, 0xde, 0xae, 0xf6, 0xd3, 0xee, 0x60, 0xf9, 0x22, 0xc4, ++ 0x19, 0xbb, 0x5d, 0xf3, 0x33, 0xe2, 0x23, 0x7e, 0x46, 0x0b, 0xac, 0xa3, ++ 0xa6, 0xf1, 0xf8, 0xd2, 0x4f, 0x11, 0x5e, 0xdc, 0xcf, 0xe0, 0xf3, 0x3e, ++ 0x2a, 0xb3, 0x79, 0x1f, 0x7d, 0xc1, 0x1c, 0x58, 0x12, 0x83, 0xfe, 0x8f, ++ 0xf2, 0xfc, 0x94, 0x0a, 0x81, 0xc1, 0x57, 0xe3, 0x83, 0xa3, 0xbd, 0xf6, ++ 0x91, 0x07, 0xef, 0xc3, 0x89, 0xa6, 0x53, 0x61, 0xdd, 0x88, 0x67, 0xc6, ++ 0xd1, 0x71, 0xbf, 0xde, 0x2f, 0xa3, 0xde, 0xa8, 0xa6, 0xf4, 0x85, 0x74, ++ 0xb5, 0x6e, 0x1c, 0xe6, 0xc7, 0x0b, 0x4f, 0x8c, 0x7b, 0x1c, 0xf2, 0x86, ++ 0x4f, 0xbd, 0x23, 0x62, 0x7b, 0xe5, 0x69, 0x2b, 0xb6, 0x77, 0xdd, 0xe7, ++ 0x7a, 0x06, 0xf2, 0x9e, 0xc2, 0xef, 0xca, 0x04, 0xe4, 0xd3, 0xa9, 0xfd, ++ 0x97, 0x27, 0xb0, 0x38, 0x91, 0x31, 0x8e, 0x7d, 0xdb, 0x00, 0x26, 0x17, ++ 0x0e, 0x71, 0xf9, 0x50, 0x7a, 0xfa, 0x11, 0xa4, 0xdf, 0x5e, 0x3a, 0xf1, ++ 0x2f, 0x50, 0x80, 0xff, 0x4a, 0x4f, 0x3f, 0xc6, 0xe8, 0x7b, 0x83, 0x80, ++ 0xf7, 0x56, 0x12, 0x5f, 0xf5, 0xbb, 0x13, 0xce, 0xe3, 0xf4, 0x39, 0x1e, ++ 0xde, 0xaf, 0xb8, 0x7a, 0x09, 0xc0, 0xfb, 0x12, 0x3f, 0xee, 0x93, 0x94, ++ 0xad, 0x37, 0xbb, 0xc0, 0x1e, 0x88, 0xc6, 0xf3, 0xa1, 0x2c, 0xd5, 0x10, ++ 0xf7, 0x28, 0x0b, 0x2d, 0xc7, 0x71, 0x09, 0xb5, 0xbf, 0x52, 0x74, 0xfb, ++ 0xe9, 0x47, 0x79, 0x9e, 0x71, 0xd9, 0x69, 0x76, 0x5f, 0x21, 0x71, 0xfa, ++ 0x48, 0x06, 0xf0, 0x03, 0x97, 0x4f, 0x11, 0x3a, 0x36, 0xde, 0x43, 0xdb, ++ 0x65, 0x8d, 0x1d, 0xa7, 0x3f, 0xc9, 0xed, 0x9f, 0xd2, 0xd3, 0x17, 0x1b, ++ 0xfc, 0x8c, 0xc8, 0xfa, 0x2e, 0xc3, 0xe7, 0xa5, 0x5c, 0xff, 0x97, 0x85, ++ 0xc6, 0x61, 0x3d, 0xb2, 0x9e, 0x67, 0xc6, 0xc5, 0x5a, 0x4f, 0x64, 0x1d, ++ 0x97, 0x60, 0xff, 0xae, 0xc4, 0xd8, 0xdf, 0xcf, 0xe4, 0x70, 0x3e, 0x52, ++ 0x5f, 0x4e, 0xdc, 0x54, 0xbe, 0x95, 0x2b, 0xac, 0x5f, 0xa9, 0xff, 0x2e, ++ 0x05, 0xe4, 0x4e, 0x69, 0x53, 0x62, 0x92, 0xa0, 0x5b, 0x57, 0x59, 0x63, ++ 0x95, 0x21, 0xcf, 0xa3, 0xac, 0xa9, 0x44, 0x99, 0xab, 0x1b, 0x37, 0x82, ++ 0x87, 0xa5, 0xef, 0x4e, 0x90, 0x22, 0x78, 0xc8, 0x7c, 0x6e, 0xf1, 0xd5, ++ 0x4b, 0x6c, 0x60, 0x17, 0x14, 0xcb, 0x03, 0x80, 0x9f, 0xd6, 0x55, 0x14, ++ 0xfd, 0x54, 0x85, 0xf1, 0x98, 0x7c, 0xfa, 0x52, 0xf6, 0xe7, 0x80, 0xbc, ++ 0xee, 0x6c, 0xbc, 0xd3, 0x11, 0xeb, 0xdc, 0x44, 0xe6, 0x80, 0x28, 0xfc, ++ 0x34, 0x72, 0xfc, 0x50, 0xbb, 0xba, 0x50, 0x87, 0x1f, 0x0d, 0x2f, 0xd1, ++ 0xef, 0x1f, 0x59, 0x5b, 0x56, 0xf4, 0x53, 0x88, 0x47, 0xaf, 0x62, 0xb7, ++ 0x90, 0xf4, 0x2f, 0x7f, 0xa2, 0xf0, 0x96, 0x1b, 0x1b, 0x6e, 0xa3, 0x7a, ++ 0xe1, 0x36, 0x1c, 0xf3, 0x8d, 0xce, 0x0e, 0xb7, 0x0b, 0x0d, 0x79, 0x45, ++ 0x7d, 0xe0, 0xc6, 0xf1, 0xab, 0xc1, 0x45, 0x7b, 0x4e, 0xed, 0xa8, 0x0b, ++ 0x07, 0x8c, 0x81, 0xef, 0x11, 0x76, 0x7e, 0xa7, 0x91, 0xe1, 0xff, 0x6c, ++ 0xf0, 0x8a, 0x7c, 0x97, 0xe3, 0x7f, 0x42, 0xec, 0x75, 0xcc, 0xec, 0x5d, ++ 0xc7, 0x22, 0xe2, 0xa3, 0x8c, 0x3a, 0xff, 0xac, 0xeb, 0xb8, 0x87, 0xf8, ++ 0x2c, 0x67, 0x58, 0x87, 0x86, 0x7f, 0xf2, 0x82, 0x01, 0xff, 0x33, 0x9f, ++ 0x5b, 0x8b, 0x7c, 0xa8, 0xe1, 0x7b, 0xfe, 0xde, 0x55, 0x48, 0xbf, 0xf3, ++ 0x29, 0x3f, 0xc2, 0x7e, 0x7f, 0xa7, 0xff, 0x2e, 0x47, 0xac, 0xfc, 0xa2, ++ 0x99, 0xfd, 0xe1, 0xfd, 0x3c, 0x1f, 0xc9, 0x2b, 0xfa, 0xbf, 0x87, 0xf7, ++ 0x2f, 0x65, 0x5f, 0x0e, 0xe4, 0x95, 0xf9, 0x56, 0x58, 0xd1, 0x1f, 0x39, ++ 0xba, 0xee, 0x91, 0x1c, 0x3d, 0x9c, 0x17, 0x64, 0x4d, 0xb8, 0x0d, 0xf0, ++ 0x42, 0x9a, 0x53, 0xcf, 0x49, 0x7f, 0xf8, 0x26, 0xba, 0xf6, 0x83, 0x7f, ++ 0xe9, 0x7b, 0x42, 0xc6, 0x78, 0xda, 0x96, 0x2c, 0x4f, 0x19, 0xbc, 0x5f, ++ 0xce, 0xfd, 0xf0, 0xfb, 0x13, 0xa7, 0x0c, 0x8d, 0x65, 0x1f, 0x3c, 0x50, ++ 0xbf, 0x7f, 0x04, 0xc4, 0xe9, 0x1a, 0xea, 0x3b, 0xb0, 0x94, 0xb9, 0x7d, ++ 0x49, 0xc0, 0xbe, 0xcc, 0x45, 0x7b, 0xc9, 0x1d, 0xeb, 0x7e, 0xaf, 0x65, ++ 0x03, 0x98, 0x5c, 0x79, 0xa0, 0xbe, 0x83, 0xc5, 0x3d, 0x2d, 0x3e, 0xe2, ++ 0xd4, 0x9f, 0x27, 0x26, 0xcc, 0x7e, 0xfa, 0x4f, 0xc2, 0xe2, 0x35, 0xda, ++ 0x7b, 0x8a, 0xec, 0x71, 0x42, 0xfc, 0x54, 0xe1, 0xe7, 0x9d, 0x65, 0xc9, ++ 0xb3, 0x2c, 0xb7, 0x10, 0xe2, 0x1e, 0x29, 0x05, 0x3e, 0x1d, 0xfc, 0x96, ++ 0x0e, 0x60, 0xe7, 0x91, 0x96, 0x67, 0xec, 0x75, 0xc2, 0xb9, 0x62, 0x33, ++ 0x1d, 0x1f, 0xe2, 0x39, 0x96, 0x6c, 0xe9, 0xa4, 0x71, 0x9f, 0x93, 0xd5, ++ 0x0b, 0x84, 0x4f, 0x45, 0xc8, 0x6f, 0x96, 0x53, 0x5a, 0x08, 0xc6, 0x43, ++ 0xf3, 0xe8, 0x73, 0x1d, 0xbc, 0x95, 0x94, 0x0e, 0x43, 0x7c, 0x3a, 0x1a, ++ 0x0e, 0x92, 0xc5, 0x81, 0xfb, 0x4d, 0x12, 0x61, 0xf6, 0x9c, 0xb6, 0x7e, ++ 0xfa, 0x04, 0xf5, 0xd2, 0x83, 0x5c, 0x2f, 0xad, 0xe4, 0x71, 0xcd, 0xa7, ++ 0xeb, 0x5b, 0x30, 0xee, 0xbf, 0x24, 0xde, 0x81, 0xfa, 0x6f, 0xe9, 0x20, ++ 0x13, 0xf3, 0xa7, 0x2c, 0x12, 0xde, 0x57, 0x63, 0x4e, 0x64, 0xfd, 0x95, ++ 0x04, 0x36, 0x6f, 0x2b, 0xc4, 0xbd, 0x45, 0xd0, 0xab, 0x41, 0xac, 0xdb, ++ 0xe1, 0x46, 0x1f, 0x11, 0xaf, 0x46, 0x13, 0xa0, 0x9e, 0x48, 0x54, 0x01, ++ 0xea, 0xc9, 0x24, 0xb8, 0x14, 0xef, 0x49, 0x99, 0x10, 0xfa, 0x09, 0x3c, ++ 0x77, 0x65, 0x78, 0x02, 0x80, 0xc7, 0x6f, 0x33, 0x3b, 0x0e, 0x08, 0x10, ++ 0xc7, 0x2e, 0xf6, 0x0c, 0x03, 0xfd, 0xdb, 0x28, 0xfa, 0x0a, 0x54, 0xda, ++ 0xff, 0xe7, 0x62, 0xb8, 0x00, 0xfa, 0xe5, 0xd0, 0xa6, 0x4f, 0x92, 0x58, ++ 0x39, 0x08, 0xf2, 0xa1, 0x3d, 0xba, 0x7d, 0x2d, 0x76, 0x4f, 0xa8, 0xaa, ++ 0x8f, 0x0b, 0x46, 0xd7, 0x07, 0x2d, 0x92, 0xa2, 0xf6, 0x7b, 0xfe, 0x32, ++ 0x4c, 0xdf, 0xbe, 0x22, 0xc3, 0xfd, 0x0a, 0xcc, 0xa3, 0xc1, 0xca, 0xee, ++ 0x19, 0x4a, 0xf9, 0x5c, 0xc0, 0xfd, 0x9c, 0x06, 0x2b, 0xbb, 0x6f, 0xa8, ++ 0xc1, 0x7e, 0x63, 0x02, 0xe8, 0xf1, 0x5f, 0x0f, 0x60, 0x76, 0x3b, 0xd2, ++ 0x01, 0xd0, 0xd1, 0x7e, 0x66, 0xcf, 0x9c, 0x94, 0xd4, 0x84, 0x24, 0x16, ++ 0x27, 0x55, 0xdf, 0x30, 0xc4, 0xf9, 0x2d, 0xea, 0x1b, 0xba, 0xef, 0x48, ++ 0xdc, 0xdf, 0x6b, 0xa6, 0x74, 0x29, 0xe9, 0xf6, 0x55, 0xce, 0x93, 0xdc, ++ 0x26, 0xa0, 0x9b, 0xf3, 0xfd, 0xf4, 0xb9, 0x7e, 0x9e, 0x31, 0xe2, 0x71, ++ 0x49, 0x36, 0xbc, 0x96, 0x37, 0xe6, 0x7e, 0x8e, 0x36, 0x3f, 0xc8, 0xdb, ++ 0x07, 0x38, 0x8a, 0xa7, 0xa7, 0xa0, 0xbf, 0x16, 0x4d, 0x0f, 0x3b, 0x7b, ++ 0xe3, 0xcc, 0x3e, 0x11, 0xf0, 0x39, 0x4b, 0xbb, 0xbf, 0x58, 0xba, 0x9f, ++ 0xd5, 0x13, 0x89, 0xf6, 0x87, 0xfe, 0xd7, 0xa7, 0xbd, 0xf6, 0xe8, 0xfd, ++ 0xac, 0xce, 0xf7, 0x39, 0xbd, 0x73, 0xd9, 0x3e, 0x66, 0x43, 0x49, 0x02, ++ 0xe6, 0xc7, 0x69, 0xf3, 0x98, 0xd5, 0xfe, 0x60, 0x07, 0xd8, 0xa9, 0xb3, ++ 0xda, 0x33, 0xe7, 0xc1, 0xfe, 0xd6, 0x2c, 0xdb, 0xd0, 0x2f, 0xa0, 0xdc, ++ 0x29, 0x87, 0xf7, 0xc6, 0x83, 0x1d, 0x78, 0x97, 0x80, 0xe7, 0x4a, 0x6e, ++ 0xfe, 0xdd, 0x1b, 0x72, 0x3c, 0x2d, 0xb7, 0x7d, 0xb8, 0x0e, 0xcf, 0x33, ++ 0x7f, 0xc1, 0xe5, 0xe9, 0x6c, 0x12, 0xc6, 0x7b, 0xe1, 0x3d, 0xc4, 0xc9, ++ 0xf7, 0xd9, 0x03, 0xf8, 0x7c, 0x2e, 0x71, 0xf1, 0x7a, 0x8b, 0x0c, 0x7e, ++ 0xfd, 0xad, 0xc1, 0xc0, 0x0d, 0x57, 0xd3, 0xda, 0x6d, 0x6f, 0x04, 0xae, ++ 0x06, 0xb3, 0x6d, 0xf6, 0xfe, 0xf0, 0x9b, 0x20, 0x06, 0x3c, 0x2d, 0xce, ++ 0x29, 0xb8, 0x87, 0xa0, 0xbd, 0xd7, 0xe6, 0x7a, 0x8b, 0xd5, 0xd9, 0x7b, ++ 0xbd, 0xeb, 0x97, 0x2c, 0xb8, 0x9e, 0xc8, 0x7a, 0x2d, 0xb8, 0x7e, 0x6d, ++ 0x7d, 0x74, 0xa6, 0x08, 0xff, 0x5e, 0xf8, 0xf0, 0xfb, 0x9a, 0x34, 0x78, ++ 0x88, 0x73, 0xe9, 0xba, 0x29, 0xbd, 0xcc, 0x4a, 0xb8, 0xf1, 0x4a, 0x72, ++ 0x06, 0xbb, 0x7c, 0x96, 0x6d, 0xf8, 0x17, 0x6c, 0xd3, 0x84, 0xcd, 0x27, ++ 0x1a, 0x3e, 0xa7, 0xa0, 0x89, 0xda, 0x8f, 0x5d, 0x03, 0xdc, 0x24, 0x9b, ++ 0xe2, 0xef, 0x0f, 0x03, 0xdc, 0x02, 0x94, 0xd5, 0x96, 0x70, 0x8e, 0x34, ++ 0x18, 0xf9, 0x44, 0x86, 0x7a, 0xad, 0xe8, 0x19, 0x04, 0xa9, 0xcf, 0x5f, ++ 0x0d, 0xf4, 0x0c, 0x4b, 0x05, 0x38, 0x74, 0x24, 0x9f, 0x93, 0xfc, 0x3c, ++ 0x60, 0x65, 0xfc, 0x7f, 0x00, 0xe8, 0x19, 0xf2, 0xbc, 0x4e, 0xa7, 0xe0, ++ 0xba, 0xb4, 0x7b, 0xe8, 0xf7, 0xdd, 0xdd, 0x69, 0x07, 0xbb, 0x73, 0xe9, ++ 0xb6, 0x8f, 0xf1, 0x9e, 0xe5, 0x1a, 0x31, 0xf4, 0xe8, 0x4d, 0x18, 0x0f, ++ 0x15, 0xd1, 0x6f, 0x3a, 0xd9, 0x3a, 0xec, 0x8c, 0xe7, 0xcf, 0x0e, 0x40, ++ 0x9c, 0x8a, 0xea, 0xbf, 0x81, 0xd9, 0xda, 0x39, 0x4b, 0xb6, 0xce, 0x39, ++ 0x12, 0xe3, 0x93, 0x39, 0xad, 0xf1, 0x98, 0x8f, 0x3f, 0x67, 0x91, 0x68, ++ 0xb8, 0x47, 0x7a, 0xce, 0x22, 0x96, 0xcf, 0x47, 0xa4, 0x8e, 0xfc, 0xeb, ++ 0x0d, 0xf6, 0xfa, 0xfd, 0xfd, 0x8e, 0x03, 0xf1, 0x82, 0xe8, 0x71, 0xe6, ++ 0x2d, 0x9a, 0x44, 0x3e, 0x1f, 0x0d, 0xfb, 0xb4, 0xce, 0x09, 0x18, 0x3f, ++ 0x58, 0xc3, 0xe8, 0x6b, 0xde, 0x64, 0xb7, 0x08, 0xf9, 0xce, 0xe3, 0x97, ++ 0x09, 0xb8, 0xdf, 0x3a, 0xee, 0xb0, 0xda, 0x16, 0xa2, 0xf5, 0x79, 0x81, ++ 0x44, 0x17, 0xb0, 0xe7, 0xbc, 0xbb, 0xff, 0x63, 0x08, 0xdc, 0x73, 0x50, ++ 0xdb, 0xc1, 0xe2, 0x81, 0xe9, 0xe2, 0xed, 0x05, 0xf7, 0x41, 0x9c, 0x65, ++ 0x2f, 0xd3, 0xe3, 0x50, 0xbf, 0x1d, 0xe8, 0xc4, 0xe6, 0x56, 0x6d, 0xba, ++ 0xfd, 0x82, 0x2e, 0xb9, 0xae, 0x00, 0xee, 0xfb, 0xf3, 0xdd, 0x66, 0x73, ++ 0x03, 0xff, 0x97, 0x5c, 0xef, 0xfe, 0x14, 0xef, 0xf3, 0xe5, 0xf1, 0x0a, ++ 0x4d, 0xaf, 0xbe, 0xd6, 0x58, 0x82, 0x79, 0xb2, 0x25, 0xb7, 0xaa, 0x63, ++ 0x01, 0xff, 0x25, 0x2d, 0x56, 0x37, 0x96, 0x16, 0x22, 0xc5, 0x51, 0x39, ++ 0x56, 0x22, 0x11, 0x0b, 0x94, 0xe9, 0x0a, 0x91, 0xac, 0x50, 0xc6, 0x11, ++ 0x0b, 0x94, 0x45, 0x4b, 0xd8, 0xbd, 0xdd, 0xa5, 0x8d, 0x33, 0xd0, 0x3e, ++ 0x70, 0x8c, 0x2d, 0x56, 0xe0, 0x3e, 0xde, 0x92, 0xf6, 0x17, 0xbf, 0x81, ++ 0xf7, 0xcb, 0xa4, 0xe0, 0x1e, 0x76, 0x3f, 0x05, 0x83, 0x4f, 0x49, 0xfb, ++ 0xdb, 0xdf, 0x03, 0x5e, 0x17, 0xb8, 0x8b, 0x31, 0x9f, 0xf1, 0xc2, 0x0d, ++ 0x8a, 0xc1, 0x0f, 0x1c, 0xd9, 0x62, 0xac, 0x5f, 0xd4, 0x66, 0xac, 0x17, ++ 0x04, 0x8d, 0xf5, 0xd1, 0xfb, 0x8d, 0xf5, 0xf5, 0xd9, 0x04, 0xe9, 0x68, ++ 0xae, 0xe5, 0xba, 0x3c, 0x80, 0xd7, 0xde, 0x5d, 0x66, 0xaa, 0x8b, 0x20, ++ 0xff, 0xcf, 0x8c, 0xf9, 0x2e, 0x87, 0x04, 0x86, 0x1f, 0xdf, 0x46, 0x2b, ++ 0xca, 0xc3, 0x49, 0x55, 0xed, 0x45, 0xe0, 0x07, 0x1f, 0x7f, 0xd9, 0x6e, ++ 0x02, 0x3f, 0x7a, 0xe7, 0x5f, 0x7f, 0x89, 0xfb, 0xe1, 0xe1, 0xcd, 0xf1, ++ 0x04, 0xf2, 0xac, 0xf6, 0xfc, 0x3e, 0x8e, 0xc4, 0x41, 0xbe, 0xe2, 0x2b, ++ 0xd6, 0x75, 0xd0, 0x5e, 0x45, 0x71, 0x07, 0xf1, 0xcb, 0xaa, 0x57, 0xac, ++ 0x6b, 0xc1, 0x0f, 0x7f, 0xf5, 0x02, 0xcd, 0x8f, 0x0f, 0xe4, 0xc3, 0x7a, ++ 0x5e, 0xfd, 0x1b, 0xcb, 0xaf, 0x09, 0x6f, 0x34, 0x07, 0x60, 0x7f, 0xfc, ++ 0xf8, 0xf6, 0x17, 0x5f, 0x86, 0xfd, 0xb4, 0xe3, 0x1b, 0x07, 0xa0, 0x7d, ++ 0x75, 0x48, 0xf0, 0x99, 0xe2, 0xe0, 0xfb, 0x5f, 0xb2, 0xf8, 0x67, 0x88, ++ 0xdf, 0x17, 0x17, 0xe2, 0xf7, 0xc5, 0x55, 0x6d, 0x30, 0xfa, 0xc5, 0x77, ++ 0x64, 0x33, 0x39, 0x13, 0x5a, 0x72, 0x71, 0x42, 0x2c, 0xbb, 0x49, 0x2b, ++ 0x87, 0x67, 0x24, 0xe7, 0x4d, 0xa6, 0x73, 0xeb, 0x79, 0xc8, 0x3c, 0x07, ++ 0xe2, 0x40, 0xc3, 0x1a, 0x8d, 0x70, 0xd1, 0xfa, 0x8d, 0x08, 0x18, 0x9f, ++ 0xdf, 0xc3, 0xc7, 0x1f, 0x4f, 0x94, 0x08, 0x9d, 0xe6, 0x42, 0x9e, 0x40, ++ 0xa0, 0xc1, 0x01, 0xfa, 0xf7, 0xf9, 0xd8, 0xf7, 0x24, 0x2f, 0xe1, 0xfc, ++ 0xf3, 0xd2, 0x4b, 0xbd, 0xef, 0x89, 0xfc, 0x9e, 0x38, 0xa2, 0xea, 0xce, ++ 0x4d, 0x45, 0xe4, 0x37, 0x59, 0x38, 0x00, 0xf2, 0x37, 0x00, 0xfe, 0x83, ++ 0x23, 0xcf, 0xab, 0x88, 0x6e, 0x3e, 0x3a, 0xfb, 0x64, 0x2a, 0x1f, 0xff, ++ 0x6b, 0x0b, 0xcb, 0x67, 0x4e, 0xe1, 0xf7, 0xf7, 0x1f, 0xab, 0xdf, 0x8f, ++ 0x7a, 0xbf, 0xd7, 0xee, 0xab, 0x77, 0xbb, 0x27, 0xeb, 0xea, 0xa5, 0x8d, ++ 0x7b, 0xd2, 0x4a, 0xc0, 0x7f, 0x6a, 0xda, 0x93, 0x36, 0x57, 0x07, 0xaf, ++ 0xea, 0x8d, 0xfb, 0xd2, 0x6e, 0xc1, 0xbc, 0x27, 0x09, 0x22, 0xb8, 0xa4, ++ 0x7a, 0xd6, 0x0b, 0x8f, 0x41, 0xbc, 0xa2, 0x7a, 0xa3, 0xd8, 0x02, 0xf3, ++ 0x84, 0x76, 0x80, 0x5b, 0x57, 0xcb, 0x9b, 0x0e, 0xe8, 0x47, 0xed, 0xe1, ++ 0x51, 0x10, 0x07, 0x89, 0xd8, 0xa3, 0x97, 0xbb, 0x27, 0xeb, 0xf8, 0xf8, ++ 0xef, 0xa5, 0x5b, 0x8d, 0xdf, 0xaa, 0xb9, 0xfd, 0xf2, 0xda, 0xd8, 0x8e, ++ 0x29, 0x90, 0xa7, 0x5e, 0xd5, 0x28, 0xb8, 0xa0, 0x5b, 0x55, 0xcb, 0x0d, ++ 0xd7, 0x5d, 0x0d, 0xf0, 0x6e, 0x62, 0xe7, 0x5c, 0x8b, 0x24, 0x52, 0x2c, ++ 0x52, 0xfe, 0xaa, 0xde, 0x72, 0xc3, 0x55, 0x23, 0x21, 0x6f, 0x66, 0xf5, ++ 0x18, 0x17, 0xcc, 0x87, 0x0e, 0x71, 0x3d, 0x3c, 0xaf, 0xda, 0x74, 0x02, ++ 0xcf, 0x33, 0x3c, 0x1c, 0xf5, 0xbb, 0x07, 0x5a, 0xb9, 0x23, 0x9b, 0xd9, ++ 0x85, 0xb4, 0x7f, 0xd0, 0x44, 0xfb, 0x3f, 0x7c, 0xa3, 0xad, 0x1c, 0xe4, ++ 0x17, 0x1d, 0xf7, 0x0d, 0xa8, 0xef, 0x1d, 0xbe, 0x0e, 0xef, 0x57, 0x71, ++ 0x1c, 0x65, 0xfb, 0x0f, 0xf4, 0xf9, 0x27, 0x26, 0x6a, 0xb7, 0x1c, 0x9d, ++ 0xe8, 0x7b, 0xef, 0x16, 0xfa, 0xea, 0x71, 0xd2, 0xf2, 0xd1, 0xd5, 0x10, ++ 0x57, 0x6a, 0x34, 0xd2, 0x23, 0xa5, 0x6f, 0x01, 0xec, 0xb2, 0xf0, 0x7a, ++ 0xc1, 0xb5, 0x0e, 0x9f, 0x2e, 0x29, 0xba, 0x16, 0x4c, 0x6e, 0xf7, 0x62, ++ 0xcc, 0xf7, 0xa5, 0xed, 0x73, 0x62, 0x9d, 0xb7, 0xae, 0x08, 0x18, 0xc7, ++ 0x89, 0xc6, 0xfb, 0x47, 0x7c, 0xbe, 0xf4, 0x6f, 0xb8, 0x9e, 0x7e, 0xa2, ++ 0xfb, 0x25, 0x4f, 0xf3, 0x61, 0x3e, 0x79, 0xf5, 0x22, 0x2a, 0x0f, 0x75, ++ 0x71, 0x82, 0xea, 0xc3, 0x7e, 0xbc, 0x5f, 0x32, 0xfa, 0x3b, 0x44, 0x4f, ++ 0xd7, 0xcc, 0x9e, 0x20, 0x2a, 0xc8, 0xc3, 0xcd, 0x2c, 0x6f, 0x86, 0xfe, ++ 0x09, 0x96, 0x22, 0x9e, 0xa7, 0x3b, 0x84, 0xd5, 0xf1, 0x5e, 0x45, 0xa0, ++ 0x53, 0x4a, 0x28, 0x55, 0x17, 0x90, 0xc9, 0x2a, 0xc0, 0xfb, 0x5a, 0x32, ++ 0x15, 0xca, 0xf1, 0x20, 0x57, 0xe0, 0x3e, 0xfd, 0xb1, 0x2d, 0xf9, 0xd0, ++ 0x7f, 0x87, 0x10, 0x7a, 0xe1, 0x39, 0x1c, 0xcf, 0x8e, 0x72, 0xbc, 0xcb, ++ 0x19, 0xc4, 0x7b, 0x26, 0xb3, 0xf8, 0x39, 0xd3, 0x2e, 0x95, 0xd5, 0x7b, ++ 0x78, 0x9c, 0x53, 0x6b, 0xaf, 0x6c, 0xb7, 0x62, 0x9e, 0xcd, 0xf1, 0xaf, ++ 0x14, 0x94, 0xb3, 0x8b, 0x5b, 0xf6, 0x61, 0x1e, 0x7d, 0xd7, 0xcb, 0x56, ++ 0x93, 0x89, 0xca, 0x83, 0xe3, 0x5b, 0x92, 0x27, 0x42, 0x3e, 0x66, 0x57, ++ 0x0b, 0xbb, 0xa7, 0xf8, 0x58, 0x4b, 0xf2, 0x44, 0xe5, 0x0c, 0x7a, 0x3b, ++ 0x5a, 0x6e, 0x68, 0xfa, 0xf4, 0x20, 0xfc, 0x93, 0xea, 0xdd, 0x3f, 0x67, ++ 0xbb, 0xbf, 0xcd, 0x06, 0x3d, 0x75, 0x3f, 0xcb, 0x57, 0x4d, 0x4f, 0xae, ++ 0x2b, 0x88, 0xf5, 0xfb, 0x17, 0xda, 0x7b, 0x29, 0x4a, 0x5d, 0x01, 0xf8, ++ 0x31, 0xe1, 0xdb, 0x6c, 0xae, 0x75, 0x08, 0x27, 0x5f, 0xae, 0x84, 0x71, ++ 0xf0, 0x0c, 0x17, 0xe4, 0x09, 0x95, 0x08, 0x6c, 0xdc, 0xb8, 0x41, 0xc5, ++ 0xe2, 0x40, 0xda, 0xdf, 0x4e, 0xfb, 0x42, 0x3c, 0x3a, 0x69, 0xbf, 0x88, ++ 0xbf, 0xd7, 0xf0, 0xb9, 0xe8, 0xfa, 0x89, 0x73, 0x08, 0xde, 0x27, 0x8f, ++ 0x76, 0xd0, 0xfc, 0x42, 0x0f, 0xde, 0x4f, 0x49, 0xee, 0x67, 0x79, 0x95, ++ 0xf3, 0x24, 0x12, 0x94, 0x28, 0xbd, 0xcd, 0x03, 0x7d, 0x94, 0x8f, 0x75, ++ 0x94, 0xcb, 0xf3, 0x9a, 0x04, 0xcc, 0x2b, 0x9b, 0xbf, 0xdc, 0xb8, 0x1e, ++ 0xb8, 0x27, 0x57, 0xaf, 0x47, 0x2b, 0x48, 0x80, 0xdd, 0x6f, 0xa1, 0x8f, ++ 0x23, 0x0e, 0x86, 0x7c, 0x17, 0xaa, 0x6f, 0xe0, 0x5e, 0x4b, 0x0b, 0xcb, ++ 0xbf, 0xa8, 0x6c, 0x36, 0xbe, 0x57, 0x45, 0x82, 0x38, 0x9f, 0xea, 0x4d, ++ 0x3f, 0x98, 0x63, 0xc1, 0xeb, 0x1b, 0xa2, 0xad, 0xcb, 0x9d, 0x0d, 0xeb, ++ 0x12, 0xae, 0xb5, 0xe0, 0xbc, 0xee, 0x7c, 0x2a, 0x81, 0xed, 0xf7, 0x28, ++ 0xc4, 0x0d, 0xfa, 0x34, 0xfc, 0x94, 0x1d, 0xe5, 0x7b, 0x15, 0xf1, 0xe0, ++ 0x78, 0x37, 0x73, 0xbd, 0xee, 0xbd, 0xbb, 0xc4, 0x3d, 0x1f, 0xe4, 0xf0, ++ 0xa2, 0x79, 0xee, 0xf9, 0xc9, 0x70, 0xde, 0x96, 0xe9, 0x3f, 0x74, 0xf9, ++ 0x90, 0xbf, 0xd9, 0xbd, 0x5b, 0x55, 0x93, 0x49, 0x70, 0x20, 0xbb, 0x77, ++ 0x83, 0x80, 0x5e, 0xad, 0x6a, 0x17, 0x82, 0x23, 0xa1, 0x6e, 0x21, 0x3e, ++ 0xc7, 0x28, 0xf6, 0x1c, 0xee, 0x1f, 0x80, 0x75, 0xeb, 0xcf, 0xd7, 0x94, ++ 0x13, 0x3f, 0x7e, 0xaf, 0xbc, 0xc9, 0xf8, 0x9c, 0x7c, 0xc8, 0xf0, 0x5a, ++ 0xcd, 0xcf, 0x31, 0x92, 0x66, 0x5d, 0xfb, 0x60, 0xb0, 0xcf, 0x18, 0x3c, ++ 0xaa, 0x37, 0x99, 0x0d, 0x71, 0x9d, 0xf1, 0x9b, 0x04, 0x9f, 0x1d, 0xcf, ++ 0xbb, 0x06, 0x1a, 0xd2, 0xe8, 0xfc, 0x6a, 0x8f, 0x52, 0x59, 0x41, 0x20, ++ 0x4f, 0xf5, 0x07, 0xb3, 0x61, 0x7c, 0xc8, 0xe7, 0x19, 0x83, 0x7a, 0x9f, ++ 0x58, 0x29, 0xde, 0x9e, 0xea, 0x95, 0xeb, 0x81, 0x11, 0xb1, 0xf2, 0xfc, ++ 0x0f, 0x70, 0x38, 0x3e, 0x75, 0x43, 0x69, 0x26, 0xf0, 0xeb, 0xe3, 0x60, ++ 0xb7, 0x66, 0x71, 0x40, 0x8f, 0x45, 0xb9, 0xc5, 0xe3, 0x07, 0x24, 0x68, ++ 0xa1, 0xdf, 0x89, 0x1b, 0xdd, 0x5b, 0xc7, 0xf6, 0xa2, 0x25, 0xac, 0x3e, ++ 0x7d, 0xf5, 0x0b, 0xd3, 0x1b, 0x2f, 0xa1, 0x7e, 0x9e, 0xec, 0xc1, 0x7d, ++ 0xa1, 0x79, 0x62, 0xf1, 0x5b, 0x70, 0x1e, 0xec, 0xc5, 0x41, 0x9e, 0x6b, ++ 0x01, 0x3f, 0xf3, 0x4c, 0xee, 0x1c, 0x09, 0xf9, 0xd6, 0x3d, 0x14, 0xe3, ++ 0xa1, 0x8b, 0x18, 0x1c, 0x9e, 0x19, 0x55, 0x37, 0xa2, 0x2e, 0x86, 0x1d, ++ 0xa8, 0xe1, 0xf9, 0x69, 0xa1, 0x25, 0x08, 0xfb, 0xb2, 0xbe, 0xed, 0xcc, ++ 0xfe, 0xb2, 0x17, 0x86, 0x65, 0xbd, 0x7e, 0xad, 0x1e, 0xc8, 0xe4, 0x51, ++ 0xc2, 0xde, 0x10, 0x9e, 0x9b, 0x08, 0x6f, 0x13, 0xf0, 0x9c, 0xe5, 0x2a, ++ 0xe1, 0x20, 0x9e, 0x47, 0x5c, 0x75, 0x85, 0x4a, 0xc0, 0xbf, 0xcf, 0xa0, ++ 0x78, 0x02, 0x79, 0xbc, 0x4a, 0x20, 0xf7, 0xc3, 0x7d, 0x5c, 0x85, 0xad, ++ 0x33, 0x6e, 0x7f, 0x13, 0xf0, 0x5c, 0x18, 0xe7, 0x82, 0x9f, 0xbb, 0xa8, ++ 0x69, 0x9d, 0x20, 0xd6, 0xd8, 0x70, 0xfd, 0xcc, 0x4e, 0x8b, 0xaf, 0x5b, ++ 0x0b, 0xfb, 0x39, 0xe9, 0x73, 0x86, 0x8f, 0x02, 0x3a, 0xa7, 0xeb, 0x9e, ++ 0x73, 0x2d, 0x7d, 0x7e, 0xfb, 0x40, 0x15, 0xbf, 0x97, 0x69, 0x63, 0x78, ++ 0xcf, 0x58, 0xe2, 0xcb, 0x85, 0xdf, 0x81, 0x4a, 0xd8, 0x5b, 0x7c, 0xfb, ++ 0x9b, 0xc0, 0x87, 0x23, 0xe3, 0xf0, 0x9c, 0x6c, 0x3a, 0x85, 0x95, 0x3d, ++ 0x09, 0xcb, 0x65, 0x60, 0x7f, 0x65, 0x90, 0xc5, 0x02, 0xf4, 0x7b, 0xca, ++ 0xc1, 0xc6, 0x4f, 0x35, 0x89, 0x73, 0x66, 0x40, 0x7d, 0x14, 0xab, 0x27, ++ 0xdd, 0x2b, 0xb8, 0xd7, 0x21, 0xf1, 0xad, 0xc0, 0xf1, 0xd3, 0xcd, 0x64, ++ 0x2a, 0xcc, 0x13, 0x9e, 0x83, 0x1d, 0x69, 0x81, 0xb8, 0x02, 0xb6, 0x07, ++ 0x18, 0x7e, 0x27, 0xd5, 0x15, 0xc0, 0x78, 0xe9, 0x43, 0x58, 0x99, 0xa2, ++ 0x04, 0xb3, 0x61, 0x9c, 0x77, 0x7a, 0xf1, 0xed, 0x41, 0xbf, 0x62, 0x21, ++ 0xd7, 0x63, 0x0b, 0xb7, 0x4c, 0x48, 0x07, 0x3f, 0xef, 0x9d, 0x2e, 0xea, ++ 0x70, 0x53, 0xb9, 0xf5, 0x4e, 0x86, 0x66, 0x0f, 0x05, 0x6d, 0xf8, 0xfb, ++ 0x50, 0xe7, 0x0d, 0x67, 0xfd, 0xb9, 0x5f, 0xb8, 0xb0, 0x80, 0x9d, 0x37, ++ 0x48, 0xc9, 0x31, 0xf6, 0xeb, 0x91, 0xdd, 0x09, 0xa3, 0x41, 0x8e, 0x7e, ++ 0xc0, 0xec, 0xf8, 0x53, 0x36, 0x37, 0xc6, 0xa7, 0x2f, 0x56, 0x62, 0xc7, ++ 0xb3, 0x9e, 0x1b, 0xc8, 0xec, 0x16, 0xef, 0x69, 0x81, 0x04, 0x74, 0x7a, ++ 0xc0, 0x3b, 0xf3, 0x5b, 0xb4, 0x2b, 0xbd, 0xa7, 0x25, 0xc3, 0xf3, 0xae, ++ 0x7a, 0x8b, 0x21, 0xcf, 0xb9, 0xba, 0x7c, 0x2f, 0x9e, 0xbb, 0xaf, 0x21, ++ 0x1d, 0x98, 0x87, 0x5d, 0xd3, 0x12, 0x6f, 0xc8, 0xdb, 0xbd, 0x38, 0x2e, ++ 0xf6, 0x77, 0x35, 0xfa, 0xf6, 0x9e, 0x16, 0x89, 0x2f, 0xe6, 0x77, 0x15, ++ 0xe3, 0xf3, 0xd3, 0xc9, 0xc4, 0x97, 0x1c, 0xab, 0x5f, 0x9a, 0xf1, 0x39, ++ 0x5d, 0x87, 0xa1, 0xde, 0xf6, 0x5d, 0xef, 0x3a, 0xe0, 0x39, 0x19, 0x1b, ++ 0x72, 0x80, 0x3f, 0x38, 0x8d, 0xdb, 0xb5, 0x3d, 0x01, 0x93, 0x4f, 0xbe, ++ 0x28, 0x82, 0x97, 0x6e, 0x67, 0xc8, 0xa0, 0x77, 0xba, 0x55, 0x56, 0xef, ++ 0xe1, 0xfb, 0x71, 0x5a, 0xbb, 0x36, 0x7e, 0xf7, 0x4c, 0x85, 0x9f, 0x2b, ++ 0x62, 0xf7, 0x2a, 0x03, 0x7c, 0x7c, 0xc3, 0x08, 0x79, 0xb6, 0xfd, 0x04, ++ 0xc6, 0xa3, 0xab, 0xdb, 0xf7, 0x4c, 0x61, 0xbf, 0xef, 0xc5, 0xe8, 0x42, ++ 0x0f, 0x27, 0x9f, 0x4e, 0x7e, 0xa4, 0x35, 0x74, 0x04, 0x4d, 0x94, 0xb7, ++ 0x7f, 0x3b, 0xf0, 0xe8, 0x63, 0x79, 0x23, 0x28, 0x89, 0xed, 0xd5, 0xf8, ++ 0xf8, 0xd8, 0x63, 0x6e, 0xca, 0xb7, 0x69, 0xa2, 0xc9, 0xc0, 0xd7, 0xf1, ++ 0x85, 0xbd, 0x7c, 0x8e, 0xe2, 0xe5, 0x29, 0x93, 0xc8, 0xe5, 0xc2, 0xf1, ++ 0xc7, 0x26, 0x5f, 0xa2, 0xaf, 0xb3, 0xfe, 0x91, 0xf7, 0xbb, 0xa6, 0x4f, ++ 0xa6, 0xb6, 0x7d, 0x61, 0x1e, 0x7b, 0xff, 0x8f, 0x03, 0xbf, 0x7a, 0x6f, ++ 0xc9, 0x79, 0x11, 0xb9, 0x44, 0xd7, 0x91, 0x53, 0x6c, 0xd7, 0xd5, 0x2d, ++ 0x51, 0x75, 0x1b, 0xad, 0x8f, 0xd4, 0xd5, 0x9d, 0x51, 0xed, 0x29, 0x51, ++ 0xed, 0x19, 0x51, 0xf5, 0x6c, 0xd6, 0xbf, 0xcb, 0x1e, 0xcc, 0x11, 0x5d, ++ 0x84, 0x74, 0x0e, 0x3c, 0x31, 0x5d, 0x1a, 0x07, 0xfb, 0xd8, 0xc1, 0xd9, ++ 0x70, 0xa3, 0xc0, 0xf2, 0x86, 0xaf, 0xa7, 0x4f, 0xa6, 0xf5, 0x9a, 0xc2, ++ 0x0e, 0xcc, 0x9f, 0xa9, 0x6d, 0x17, 0x5c, 0xb8, 0xad, 0xaf, 0xe5, 0xc7, ++ 0xbb, 0x98, 0x9d, 0x65, 0x73, 0x85, 0xf0, 0xf7, 0xec, 0xe2, 0x0b, 0x3b, ++ 0xde, 0x02, 0x39, 0x50, 0xdd, 0x26, 0x38, 0x05, 0x4a, 0xef, 0xb6, 0x96, ++ 0x2d, 0x98, 0x57, 0x53, 0x0d, 0xef, 0xa9, 0xba, 0xf7, 0x5a, 0x98, 0xdf, ++ 0x59, 0xdd, 0x72, 0x10, 0xdf, 0xeb, 0x77, 0xfc, 0xe1, 0x26, 0xe4, 0xe7, ++ 0x87, 0x87, 0x1f, 0xc2, 0x7e, 0xda, 0xfe, 0xd1, 0x4d, 0xa4, 0xf7, 0xf7, ++ 0x3a, 0x4e, 0x0f, 0x04, 0x3c, 0xb6, 0x74, 0x32, 0x3d, 0x1c, 0xb5, 0x7f, ++ 0xd4, 0x9d, 0xe9, 0xde, 0x87, 0xf2, 0x30, 0xea, 0xfc, 0xab, 0x17, 0xc6, ++ 0xb5, 0x45, 0xe8, 0x5e, 0xeb, 0xff, 0x87, 0x91, 0xed, 0xbf, 0x83, 0x61, ++ 0xe2, 0x17, 0x9e, 0x58, 0x2c, 0xd1, 0xfe, 0x7f, 0xaa, 0xe9, 0x1c, 0x03, ++ 0xf6, 0x12, 0xdc, 0x71, 0x09, 0x72, 0xff, 0x69, 0x21, 0x30, 0x02, 0xf4, ++ 0xf3, 0xb3, 0xc4, 0x33, 0x02, 0xf4, 0xd1, 0x6d, 0x35, 0xe7, 0xef, 0x31, ++ 0xd1, 0x7e, 0x07, 0xe4, 0xd0, 0x6a, 0xb8, 0xaa, 0x61, 0x68, 0x8e, 0xf5, ++ 0x1a, 0x89, 0xca, 0xe9, 0x03, 0xf6, 0xd0, 0x40, 0x81, 0xca, 0x92, 0xe1, ++ 0x6b, 0x92, 0xaf, 0x01, 0x78, 0x1e, 0x48, 0x0d, 0xe1, 0x0d, 0x0d, 0x3f, ++ 0x5b, 0x93, 0xc2, 0xda, 0x07, 0x86, 0x06, 0xc2, 0xbe, 0x6b, 0x5e, 0xce, ++ 0x8f, 0x59, 0xfd, 0xfc, 0xd0, 0x6a, 0xa8, 0x5f, 0xbf, 0xe6, 0x02, 0x56, ++ 0x1f, 0x19, 0x1a, 0x28, 0xd2, 0xf7, 0x07, 0xfb, 0x2e, 0xbc, 0x06, 0xe0, ++ 0xbf, 0xde, 0x19, 0x9b, 0x6f, 0x07, 0xe6, 0x30, 0x79, 0xae, 0xcd, 0x6f, ++ 0x66, 0x81, 0x3b, 0x23, 0x07, 0xec, 0xcd, 0x6a, 0xa6, 0x2f, 0xe0, 0xf8, ++ 0xa5, 0x85, 0xca, 0xc5, 0xd9, 0x95, 0xc7, 0x36, 0xaf, 0xa7, 0x70, 0x98, ++ 0xfd, 0xd3, 0x78, 0x94, 0x57, 0xeb, 0xbb, 0xae, 0xbb, 0xb2, 0x18, 0xd7, ++ 0xef, 0x2b, 0x86, 0x3c, 0x37, 0x76, 0xc5, 0x3b, 0xd7, 0x67, 0x28, 0x97, ++ 0x25, 0xb4, 0x03, 0x32, 0x41, 0x87, 0x25, 0x45, 0xf0, 0x61, 0xcf, 0xe9, ++ 0x50, 0x51, 0xde, 0x5f, 0x50, 0xb7, 0x05, 0xf4, 0x7e, 0xfa, 0xec, 0x3c, ++ 0x94, 0xf7, 0xa7, 0xb2, 0xdd, 0xf5, 0x39, 0x63, 0x22, 0xe5, 0x9f, 0x87, ++ 0xb0, 0xb2, 0x3e, 0x87, 0x9d, 0xf7, 0x48, 0x17, 0x4d, 0x98, 0x6f, 0x90, ++ 0x7e, 0x8f, 0x1d, 0xed, 0xa0, 0xc7, 0xf9, 0x7e, 0x12, 0xe5, 0x1b, 0xc4, ++ 0xaf, 0x8d, 0xe3, 0x63, 0x54, 0x0e, 0x93, 0x7f, 0xa3, 0x72, 0x98, 0x9f, ++ 0x94, 0x35, 0xf0, 0xf2, 0x7a, 0x58, 0xcf, 0xcd, 0xdc, 0x3e, 0x5d, 0xf9, ++ 0x50, 0x60, 0xa3, 0x95, 0xc2, 0xff, 0xf7, 0x40, 0x24, 0x29, 0x18, 0xdf, ++ 0x46, 0x7b, 0xf7, 0x96, 0xb5, 0x54, 0x6e, 0x24, 0x40, 0x3e, 0x85, 0x3b, ++ 0x13, 0xe4, 0xc1, 0x2d, 0x10, 0xff, 0xcd, 0x8b, 0xd4, 0x35, 0xfb, 0x7d, ++ 0x65, 0x01, 0xad, 0xdb, 0x22, 0x7e, 0xda, 0xca, 0x19, 0xee, 0x4c, 0x7d, ++ 0x1e, 0xd0, 0xca, 0xb5, 0xac, 0x5d, 0x93, 0x37, 0x2b, 0x73, 0xd9, 0xfb, ++ 0x9a, 0xde, 0x49, 0x6f, 0x60, 0xf0, 0x49, 0x7f, 0x7c, 0xc4, 0x3a, 0x58, ++ 0x47, 0xbc, 0x44, 0xf0, 0xfc, 0xc5, 0x82, 0x99, 0x43, 0xd7, 0x2d, 0x46, ++ 0xfd, 0x7d, 0x2d, 0xae, 0x9b, 0xb8, 0xdd, 0x99, 0xe0, 0x7f, 0x1f, 0xae, ++ 0x18, 0x6c, 0x02, 0xbb, 0x52, 0xc3, 0xcf, 0xa2, 0x02, 0xf7, 0x34, 0x5c, ++ 0x8f, 0xc8, 0xf2, 0xd5, 0x35, 0x3c, 0x69, 0xdf, 0xaf, 0xe7, 0xeb, 0x9e, ++ 0x27, 0x52, 0xfd, 0x4f, 0xd7, 0x59, 0x3f, 0xc8, 0x83, 0xeb, 0xa7, 0xf6, ++ 0x40, 0x3e, 0x4b, 0x2e, 0x60, 0xf6, 0x40, 0x3d, 0x04, 0x62, 0x53, 0x23, ++ 0xf0, 0x25, 0x52, 0x68, 0x0c, 0x3c, 0xff, 0x5f, 0x04, 0xa7, 0xdb, 0xa1, ++ 0xfd, 0x1f, 0x85, 0x53, 0x0c, 0x79, 0xf1, 0x33, 0xe8, 0x57, 0xb3, 0x88, ++ 0xca, 0x0b, 0x93, 0x4e, 0x5e, 0x70, 0xf8, 0x3d, 0x2d, 0x04, 0xe5, 0xf4, ++ 0x42, 0xdd, 0xfd, 0x25, 0xf4, 0x39, 0xf8, 0x81, 0x37, 0x0d, 0xf4, 0x3c, ++ 0x90, 0xa3, 0xdb, 0xc7, 0x99, 0x7d, 0x4f, 0x0d, 0xda, 0x7f, 0xda, 0xbc, ++ 0xe2, 0xff, 0xfd, 0xb5, 0xa9, 0x37, 0x91, 0xbe, 0x7c, 0x16, 0x6d, 0x9f, ++ 0x1d, 0xf8, 0xbd, 0x65, 0x39, 0xc6, 0x01, 0x95, 0x16, 0x94, 0x8b, 0x07, ++ 0xae, 0x24, 0xae, 0xc5, 0x20, 0x3f, 0xf8, 0xbe, 0xac, 0x66, 0x5f, 0x16, ++ 0xfd, 0xb4, 0xea, 0x1d, 0xf0, 0xa3, 0x4e, 0xe6, 0x88, 0xf8, 0x9e, 0x55, ++ 0xc3, 0xab, 0x50, 0xbc, 0xa5, 0x94, 0xc2, 0xe9, 0x21, 0xaa, 0x56, 0xe1, ++ 0x3c, 0xba, 0x6f, 0x06, 0xcb, 0xef, 0xd1, 0xf4, 0xe6, 0x4a, 0x7e, 0xef, ++ 0xee, 0xca, 0xbb, 0x2f, 0xc4, 0x3c, 0xbf, 0x1e, 0x12, 0xc2, 0xdf, 0x65, ++ 0xf3, 0x8d, 0x25, 0x28, 0xff, 0x7a, 0xdb, 0x67, 0x0d, 0xc5, 0x76, 0x8a, ++ 0x6f, 0x9f, 0x15, 0xf8, 0xbd, 0x22, 0x0e, 0x7f, 0x77, 0x60, 0x65, 0x01, ++ 0xc1, 0x73, 0x36, 0x2b, 0x67, 0x5d, 0x80, 0xed, 0x3b, 0xb5, 0xb8, 0xd2, ++ 0x2c, 0x0b, 0x7e, 0x67, 0xe5, 0x0c, 0x46, 0x4f, 0x2b, 0x2b, 0x58, 0x1e, ++ 0x26, 0xe8, 0x11, 0x80, 0x5b, 0x7f, 0xf4, 0x90, 0xd6, 0xc0, 0xe2, 0x1b, ++ 0x44, 0x72, 0xe7, 0xeb, 0xf3, 0x01, 0xde, 0xe5, 0xf8, 0x8b, 0x2f, 0x0c, ++ 0x6d, 0xfb, 0x18, 0xec, 0xca, 0xe5, 0x56, 0xb4, 0x2b, 0x41, 0x77, 0xe2, ++ 0xfe, 0x88, 0x3f, 0x1d, 0xbf, 0x47, 0xf1, 0xba, 0x0d, 0xe5, 0x99, 0xe6, ++ 0x47, 0x3d, 0x99, 0xc9, 0xee, 0x9b, 0x25, 0x2e, 0xf4, 0xcf, 0x1f, 0xb4, ++ 0xbb, 0x4b, 0x50, 0x5e, 0xdd, 0x17, 0xaf, 0xc2, 0xfc, 0x9b, 0xac, 0x64, ++ 0x99, 0x65, 0x14, 0xb8, 0x23, 0xe4, 0x7e, 0x94, 0x7b, 0x7c, 0x3e, 0xc4, ++ 0xff, 0x0c, 0xe6, 0x79, 0xcc, 0xe1, 0xf6, 0xda, 0x67, 0xe5, 0x27, 0xed, ++ 0x60, 0x0f, 0xbc, 0xc1, 0xe5, 0x0d, 0x10, 0x0c, 0xf8, 0xcb, 0x73, 0x09, ++ 0x6b, 0x9f, 0x7b, 0x6f, 0xfc, 0x41, 0xf0, 0x6f, 0xe6, 0xde, 0xcb, 0xee, ++ 0x9b, 0x25, 0xcb, 0x2e, 0x77, 0x1b, 0xf7, 0x3b, 0xe8, 0x5c, 0xd3, 0x20, ++ 0x3e, 0xce, 0xff, 0x1a, 0xc3, 0x76, 0x80, 0x83, 0x07, 0xde, 0x73, 0xc0, ++ 0xf8, 0xff, 0x69, 0x87, 0xfb, 0x4c, 0x3c, 0xf7, 0xb2, 0xf3, 0xbd, 0xc4, ++ 0x47, 0xdf, 0xd7, 0xe5, 0x43, 0x7f, 0x0c, 0xfc, 0x0b, 0x71, 0x76, 0x91, ++ 0xcd, 0x9f, 0xd4, 0xc7, 0xab, 0xb1, 0xee, 0x05, 0xfd, 0x98, 0xcb, 0x77, ++ 0x3a, 0x7f, 0xb7, 0xfe, 0x7b, 0xda, 0x77, 0xa2, 0xc7, 0xa5, 0xfe, 0xdd, ++ 0x27, 0x40, 0xa7, 0x14, 0xee, 0x41, 0x38, 0x07, 0x16, 0xbe, 0x4f, 0xe4, ++ 0xbf, 0xd7, 0x6a, 0x9c, 0x6f, 0x8a, 0x12, 0x7e, 0xd4, 0x4a, 0xdb, 0x67, ++ 0xd7, 0x8b, 0x89, 0x4b, 0x28, 0x3c, 0x3d, 0x8b, 0xec, 0xb8, 0x5e, 0x6d, ++ 0xbe, 0x73, 0xd2, 0xc3, 0x97, 0xb2, 0xdf, 0x85, 0x35, 0x8e, 0x7f, 0x24, ++ 0xbe, 0xb6, 0x08, 0xe2, 0xe1, 0x9a, 0x3f, 0x42, 0xee, 0x35, 0xfa, 0x63, ++ 0x10, 0x97, 0xe8, 0xad, 0x8b, 0x98, 0x27, 0x8d, 0x7e, 0x4d, 0x9f, 0xe7, ++ 0xdc, 0x9f, 0x8d, 0xf6, 0x03, 0x09, 0xf9, 0x9b, 0x59, 0xdf, 0xaf, 0xf7, ++ 0x9c, 0x86, 0x2a, 0x44, 0xcd, 0x9f, 0xd3, 0x95, 0x2a, 0x48, 0x80, 0x37, ++ 0x0f, 0xcf, 0x5f, 0x50, 0x94, 0xf0, 0x6c, 0xbc, 0x57, 0x2a, 0x6a, 0xde, ++ 0x1a, 0x3c, 0x95, 0x41, 0x26, 0x0e, 0x77, 0x46, 0x17, 0xd1, 0xf0, 0x56, ++ 0x06, 0x71, 0x7a, 0x88, 0x82, 0x77, 0x8a, 0x12, 0x1a, 0x08, 0xe3, 0x7a, ++ 0x16, 0x99, 0x11, 0x4e, 0xd1, 0xe3, 0x6b, 0xfa, 0xf1, 0x19, 0x2b, 0xf1, ++ 0x81, 0x1f, 0xd9, 0x28, 0x08, 0x48, 0xaf, 0x8d, 0x77, 0xc7, 0xa3, 0xbe, ++ 0x23, 0x16, 0x86, 0x67, 0x6f, 0x65, 0x9c, 0x0a, 0xf4, 0xfb, 0xac, 0x12, ++ 0xc6, 0x3c, 0x27, 0xdf, 0x0e, 0xf6, 0xfb, 0xa0, 0x3d, 0xd6, 0xf0, 0xab, ++ 0x28, 0xb7, 0xce, 0x63, 0xf1, 0x86, 0x9e, 0xf7, 0xc4, 0xb5, 0xd0, 0xaf, ++ 0x3b, 0x95, 0xd1, 0x7d, 0xf7, 0x76, 0x99, 0xf3, 0x1b, 0x61, 0xf7, 0x4c, ++ 0xbc, 0x27, 0xae, 0xc3, 0x76, 0x81, 0x8d, 0xdb, 0xbd, 0x38, 0x1e, 0xf3, ++ 0xa7, 0xe0, 0x7c, 0xa8, 0x02, 0xe7, 0x36, 0x7d, 0x7f, 0xae, 0x87, 0xf8, ++ 0x8b, 0xe6, 0xe7, 0x7f, 0xfe, 0x2a, 0xbb, 0x6f, 0x01, 0x7e, 0xd7, 0x47, ++ 0xef, 0x27, 0xc3, 0xb9, 0xda, 0xf2, 0x51, 0x11, 0xf9, 0x81, 0xf7, 0xc7, ++ 0x00, 0xbf, 0xb7, 0xc5, 0xf3, 0x38, 0x92, 0xa7, 0x02, 0xbf, 0x77, 0x4b, ++ 0x1c, 0x81, 0x3c, 0x8d, 0x5a, 0x93, 0x80, 0x79, 0xbf, 0xb5, 0x95, 0x17, ++ 0xe0, 0x39, 0x13, 0xc2, 0xef, 0x79, 0xae, 0xe6, 0x53, 0xab, 0x35, 0x51, ++ 0x7f, 0x71, 0x54, 0x44, 0x0e, 0xd4, 0x9a, 0x0e, 0x0d, 0x05, 0x7f, 0xab, ++ 0xda, 0xb2, 0x1c, 0xef, 0x7f, 0xa6, 0xed, 0x6f, 0x80, 0x9f, 0x06, 0x3f, ++ 0xc3, 0xdb, 0xfb, 0x3b, 0x1f, 0xb9, 0x7d, 0xf1, 0x50, 0xbb, 0xfc, 0xf8, ++ 0x5f, 0xf1, 0xdc, 0x7b, 0xab, 0x91, 0x3e, 0xaa, 0x23, 0x74, 0x84, 0xe7, ++ 0xe7, 0x2a, 0xf5, 0x74, 0x95, 0x1b, 0xa1, 0x17, 0xb4, 0xc7, 0x41, 0x8e, ++ 0x4c, 0x26, 0x78, 0x6e, 0xdf, 0xce, 0xeb, 0xf1, 0x53, 0x3b, 0x02, 0x10, ++ 0xc7, 0xf1, 0xf2, 0xb8, 0x46, 0xea, 0x5e, 0x76, 0xaf, 0xad, 0xbd, 0xb0, ++ 0x85, 0x40, 0x5c, 0xd5, 0x7b, 0x94, 0xd9, 0x23, 0xe3, 0xdb, 0xd7, 0xee, ++ 0x03, 0xff, 0x38, 0x71, 0x6a, 0x07, 0x78, 0x64, 0xb4, 0x3f, 0x8b, 0xcb, ++ 0x45, 0x9f, 0x2f, 0x1a, 0xd7, 0xbe, 0x42, 0x04, 0xbf, 0x4f, 0xb3, 0x63, ++ 0x74, 0x7e, 0xe7, 0x88, 0x6b, 0x47, 0xea, 0x4b, 0x76, 0x1e, 0x17, 0xfc, ++ 0x58, 0xf8, 0x5e, 0x08, 0x1e, 0x01, 0xff, 0x48, 0x4c, 0xff, 0x3d, 0xcd, ++ 0xf5, 0x1f, 0xd5, 0x93, 0x28, 0xaf, 0x17, 0xf8, 0x87, 0xa1, 0x9e, 0x04, ++ 0x3d, 0x06, 0x72, 0x4e, 0xf3, 0x83, 0x41, 0xee, 0x81, 0x9c, 0x79, 0x71, ++ 0xd0, 0xc4, 0x5b, 0x07, 0xa5, 0xc2, 0x7d, 0x86, 0x13, 0x6f, 0x1a, 0xc4, ++ 0xf6, 0x69, 0x46, 0xa0, 0xdd, 0xef, 0x3b, 0xb7, 0xfd, 0x28, 0xad, 0x1f, ++ 0xf8, 0xc3, 0x67, 0x8e, 0x97, 0x31, 0xb8, 0x85, 0x57, 0x25, 0x30, 0x39, ++ 0x02, 0x3f, 0x10, 0x0a, 0x71, 0xe4, 0xdf, 0xc8, 0x6b, 0x1f, 0xc6, 0xf9, ++ 0x49, 0xec, 0xbe, 0xc6, 0xd5, 0xb9, 0x28, 0x97, 0xb5, 0x38, 0x4e, 0x35, ++ 0x8f, 0x63, 0x95, 0xf2, 0xb8, 0x4f, 0x29, 0x8f, 0xfb, 0x40, 0xdc, 0x55, ++ 0x9f, 0x17, 0x0b, 0x71, 0x4d, 0x7d, 0xbd, 0x9a, 0xcb, 0x85, 0x1a, 0xf8, ++ 0xbd, 0x29, 0xbc, 0x4f, 0xc0, 0x1c, 0xc9, 0x8b, 0x85, 0x78, 0xcf, 0x64, ++ 0x12, 0xb4, 0x43, 0x3b, 0xc4, 0x7d, 0x1c, 0xec, 0xfc, 0x9d, 0xfe, 0x7d, ++ 0x2f, 0x09, 0x4c, 0x92, 0x90, 0xce, 0x7f, 0x30, 0x1b, 0xee, 0xcd, 0x5a, ++ 0xc9, 0xd6, 0x3b, 0x87, 0xe3, 0x7d, 0x95, 0x95, 0xc5, 0x7b, 0xc6, 0xdf, ++ 0xbb, 0x56, 0x64, 0x41, 0x2c, 0xb6, 0xde, 0x84, 0x51, 0xee, 0xdc, 0x07, ++ 0x0a, 0x23, 0xf7, 0x77, 0x7d, 0xc1, 0xf1, 0xa4, 0xc1, 0x25, 0x6e, 0xd0, ++ 0xc4, 0x12, 0x80, 0x7b, 0x9c, 0xc8, 0xee, 0x3f, 0x0f, 0x3f, 0xc0, 0x7e, ++ 0x0f, 0xfb, 0x30, 0xd5, 0xdf, 0x5b, 0x78, 0x3c, 0xe4, 0x5a, 0x1b, 0x9e, ++ 0x3f, 0x76, 0x9f, 0x07, 0x79, 0x0b, 0x92, 0x33, 0xe7, 0xda, 0x18, 0xbf, ++ 0xeb, 0xfa, 0xf0, 0x0e, 0x2b, 0xde, 0xe3, 0xef, 0xe7, 0xf2, 0x48, 0x7b, ++ 0x3e, 0x65, 0x10, 0xcb, 0xf7, 0xc5, 0x38, 0x11, 0xc0, 0x7d, 0x71, 0x3c, ++ 0xda, 0xe1, 0x14, 0xcc, 0xf9, 0x40, 0x47, 0x45, 0x83, 0x35, 0x7d, 0x4a, ++ 0xf2, 0x21, 0x3e, 0x75, 0x90, 0xe7, 0x7f, 0xd6, 0xde, 0x68, 0xf3, 0xc0, ++ 0x78, 0x21, 0x1e, 0x37, 0x5f, 0x3d, 0x88, 0xe9, 0x8d, 0xd5, 0x83, 0xd8, ++ 0xef, 0x3f, 0x68, 0xf5, 0x5e, 0xbf, 0x8f, 0xd3, 0x8b, 0xb6, 0xcf, 0x05, ++ 0xf1, 0x1a, 0x7d, 0x7c, 0xbb, 0xb9, 0xb7, 0x3f, 0x8b, 0xaf, 0x68, 0xfa, ++ 0xf7, 0xe9, 0x8a, 0xb8, 0xb5, 0xec, 0xbe, 0x77, 0x8d, 0x6e, 0x4d, 0x78, ++ 0xbe, 0x32, 0x3e, 0xaf, 0x58, 0x81, 0x38, 0xd3, 0x0e, 0x2e, 0x47, 0x4a, ++ 0xb8, 0x3f, 0xbf, 0x03, 0x36, 0x70, 0x41, 0x9e, 0xb4, 0xf0, 0xb8, 0xb4, ++ 0xe4, 0x9c, 0x0d, 0xbf, 0x1b, 0xb4, 0xe3, 0x68, 0x1e, 0xe6, 0x53, 0xa6, ++ 0x28, 0x4c, 0xbe, 0xec, 0xb8, 0x39, 0x8e, 0x40, 0x7e, 0xdf, 0xfe, 0x63, ++ 0x2f, 0x3d, 0xf2, 0x1e, 0x6d, 0x3f, 0x79, 0x54, 0xc1, 0xfb, 0xf2, 0xe6, ++ 0xf3, 0x78, 0xec, 0x0e, 0xb8, 0x17, 0x1e, 0xe4, 0xe5, 0x36, 0x33, 0xc6, ++ 0x19, 0xab, 0x15, 0x66, 0x4f, 0x56, 0xef, 0x1e, 0xc9, 0xec, 0x18, 0xc5, ++ 0xb3, 0x0a, 0xf2, 0xbe, 0x7d, 0x5b, 0x65, 0x8c, 0x7b, 0x55, 0x3b, 0x02, ++ 0x1b, 0x5f, 0xc0, 0xf6, 0x4c, 0x17, 0xc5, 0x2c, 0x9c, 0x17, 0x65, 0x76, ++ 0xf0, 0xf6, 0x78, 0xf6, 0x7e, 0x5c, 0xe0, 0x17, 0x2f, 0x83, 0x5f, 0xba, ++ 0x3b, 0xdd, 0xe5, 0xa3, 0xfd, 0x17, 0x65, 0x78, 0xf6, 0x02, 0x1f, 0x65, ++ 0x99, 0xd5, 0x04, 0xa2, 0xed, 0xbb, 0x0a, 0x91, 0xf3, 0xa4, 0x87, 0x02, ++ 0xcc, 0x6e, 0x3e, 0x04, 0x82, 0x07, 0xbe, 0xd3, 0x6e, 0xe7, 0xbf, 0x33, ++ 0xe0, 0xce, 0x5c, 0x40, 0xc7, 0xf9, 0xfc, 0xa1, 0x74, 0x5c, 0x0f, 0x95, ++ 0xb7, 0x68, 0x5f, 0x7d, 0xfe, 0x98, 0x19, 0xf7, 0xd5, 0x9e, 0xee, 0xfd, ++ 0x2e, 0x8b, 0x8f, 0x1e, 0x92, 0x8b, 0xf1, 0x3e, 0x99, 0x43, 0xdb, 0x0a, ++ 0x5c, 0xd4, 0xf3, 0x24, 0x3d, 0xc5, 0x4a, 0x10, 0xe2, 0xdf, 0xde, 0xc7, ++ 0x99, 0xbd, 0x37, 0xcf, 0xa4, 0xae, 0x01, 0xf8, 0x90, 0xdd, 0xf1, 0x2e, ++ 0x83, 0xbf, 0xfa, 0x58, 0x19, 0xbb, 0x5f, 0xa2, 0xf2, 0xde, 0xe9, 0x67, ++ 0xda, 0xe7, 0x06, 0xf9, 0xae, 0x8f, 0xff, 0x76, 0x93, 0x70, 0x0e, 0xfa, ++ 0xab, 0xe5, 0x83, 0x5b, 0x20, 0xdf, 0xb4, 0xbb, 0x7d, 0x84, 0x8b, 0x6d, ++ 0x67, 0x65, 0xe0, 0x26, 0x4a, 0x2d, 0xdf, 0x7f, 0x3e, 0x2c, 0x33, 0xf8, ++ 0x86, 0x77, 0xc9, 0x48, 0xcf, 0xe7, 0x3a, 0x3e, 0xd0, 0x45, 0xef, 0xef, ++ 0xe0, 0x89, 0x04, 0x7f, 0xdf, 0x4d, 0xbf, 0xdf, 0x16, 0xbd, 0x4f, 0xd1, ++ 0xb7, 0xce, 0xf0, 0xe8, 0xdd, 0x91, 0xce, 0xed, 0x3a, 0x63, 0xfb, 0x75, ++ 0xd9, 0x9e, 0x53, 0xc0, 0x6f, 0xb5, 0x4f, 0x7c, 0x77, 0x60, 0x91, 0x0a, ++ 0xdf, 0x0b, 0xa3, 0x3c, 0x24, 0x7e, 0x16, 0x6f, 0x3f, 0x2c, 0xbb, 0x67, ++ 0x03, 0xdd, 0x26, 0x4e, 0x0e, 0x1a, 0xf2, 0xb8, 0x6c, 0x2a, 0xf7, 0x0f, ++ 0xcc, 0xdc, 0xfe, 0x23, 0x41, 0x45, 0xcf, 0x87, 0x5a, 0x7b, 0xd1, 0x44, ++ 0x12, 0x73, 0x5f, 0xe7, 0xff, 0x00, 0x2e, 0x3f, 0xe0, 0x29, 0x00, 0x80, ++ 0x00, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x0b, 0xc5, 0x7d, 0x0b, 0x78, 0x54, 0xd5, 0xb5, 0xf0, 0x3e, 0x73, ++ 0xce, 0xbc, 0x92, 0x99, 0x64, 0x66, 0x32, 0x09, 0x93, 0x17, 0x39, 0x79, ++ 0x07, 0x92, 0xc0, 0x10, 0x43, 0x44, 0x8b, 0x3a, 0x09, 0x01, 0x03, 0x46, ++ 0x9d, 0x00, 0x2a, 0x5a, 0x8b, 0xc3, 0x1b, 0x94, 0x3c, 0x04, 0x6d, 0x63, ++ 0x4b, 0x9b, 0x81, 0x44, 0x08, 0x88, 0x1a, 0x2e, 0x01, 0x01, 0x01, 0x27, ++ 0x08, 0x4a, 0xaf, 0xd8, 0x06, 0x2f, 0x20, 0xd6, 0x48, 0x07, 0x44, 0x8a, ++ 0xad, 0xde, 0x3f, 0x3e, 0xda, 0x8b, 0x7a, 0x2f, 0x5f, 0x50, 0x8a, 0x68, ++ 0x05, 0x22, 0x5a, 0x7e, 0xda, 0xab, 0xf5, 0x5f, 0x6b, 0xed, 0x7d, 0x92, ++ 0x39, 0x43, 0x22, 0xd8, 0xdb, 0xdb, 0x3f, 0x7c, 0xb0, 0xd9, 0x67, 0xbf, ++ 0xd6, 0x5e, 0x6b, 0xed, 0xb5, 0xd6, 0x5e, 0x7b, 0xed, 0x9d, 0x58, 0x55, ++ 0x62, 0x2c, 0x91, 0x31, 0x7b, 0x37, 0xf3, 0x85, 0x8a, 0x18, 0xfb, 0x06, ++ 0x7f, 0x6e, 0xe8, 0x4f, 0x63, 0x55, 0x03, 0x95, 0x33, 0x36, 0xc5, 0xcc, ++ 0x92, 0x18, 0xbb, 0x96, 0xf1, 0x9f, 0x8c, 0xd3, 0x50, 0xdf, 0xc6, 0x98, ++ 0x4d, 0x55, 0x19, 0x1b, 0x0d, 0xdf, 0x4f, 0x87, 0x4d, 0xb3, 0x20, 0x9f, ++ 0xb1, 0x24, 0x6c, 0x9a, 0x2b, 0xd2, 0x00, 0xa4, 0x27, 0x8d, 0x2c, 0x6c, ++ 0x29, 0x85, 0x74, 0xa3, 0x3d, 0xb4, 0x2d, 0x13, 0x5b, 0xfa, 0x18, 0xf6, ++ 0x33, 0x77, 0x0c, 0xfc, 0x17, 0x9a, 0xce, 0x95, 0x59, 0x8b, 0xa5, 0x04, ++ 0xbf, 0xab, 0xfb, 0x7b, 0xdc, 0x8c, 0x9d, 0xda, 0xeb, 0xf4, 0xae, 0x82, ++ 0xef, 0xec, 0xab, 0x6f, 0x64, 0x56, 0xc6, 0xd8, 0x0c, 0x26, 0xea, 0x99, ++ 0x59, 0xab, 0xc5, 0xc5, 0xd8, 0x8b, 0x2d, 0x52, 0xd8, 0x02, 0xf5, 0x66, ++ 0x6c, 0x30, 0x6f, 0xb3, 0x42, 0x7f, 0x65, 0xcb, 0x7c, 0xb2, 0x1d, 0xf2, ++ 0xbd, 0x5b, 0x24, 0xef, 0x36, 0xa8, 0x37, 0xa3, 0xa5, 0x3c, 0x6f, 0x23, ++ 0xe4, 0xef, 0xdd, 0x53, 0xec, 0x95, 0xa1, 0x69, 0x1c, 0x8e, 0x83, 0xf9, ++ 0x90, 0x33, 0x24, 0x43, 0xfd, 0x6b, 0x1b, 0xc7, 0xb1, 0x8f, 0xae, 0x62, ++ 0x6c, 0x96, 0x39, 0x64, 0x52, 0xe0, 0x3b, 0x7b, 0x4e, 0x62, 0x3b, 0x18, ++ 0xf5, 0xdf, 0x82, 0xfd, 0x2f, 0x84, 0x46, 0xc9, 0x25, 0x97, 0xe2, 0x61, ++ 0xde, 0x06, 0x33, 0x63, 0x16, 0x3e, 0xf7, 0x6f, 0xf0, 0x9f, 0x50, 0x44, ++ 0x3e, 0x0b, 0xfa, 0xed, 0xec, 0x90, 0x19, 0xcc, 0x97, 0xed, 0x84, 0xef, ++ 0x05, 0xfd, 0xdf, 0x17, 0x2a, 0xe1, 0x83, 0x52, 0x1c, 0x63, 0xb5, 0x9d, ++ 0x51, 0xed, 0xd9, 0xdf, 0xcc, 0x7d, 0xf5, 0x10, 0x50, 0x16, 0x24, 0x3c, ++ 0xbb, 0x4d, 0xec, 0x1e, 0xbf, 0x8d, 0x26, 0x3d, 0xa4, 0xa6, 0x98, 0xb1, ++ 0x3f, 0xe2, 0x7f, 0x93, 0x19, 0x8b, 0xc9, 0xf0, 0x5f, 0xad, 0x12, 0x1d, ++ 0x72, 0x86, 0x4c, 0xb6, 0xc3, 0xbc, 0x2b, 0xf8, 0xbc, 0x7a, 0x77, 0x4b, ++ 0x84, 0xd7, 0x5a, 0xd6, 0x60, 0x62, 0xd8, 0x4f, 0x7b, 0x02, 0x63, 0xd7, ++ 0x44, 0x8c, 0x6b, 0x61, 0xe1, 0x58, 0x48, 0x4f, 0xc9, 0x41, 0x2a, 0x9f, ++ 0x6b, 0x5e, 0x43, 0x69, 0xb5, 0x9a, 0x49, 0x74, 0xbb, 0x97, 0xf5, 0x98, ++ 0x58, 0x36, 0xf6, 0xdb, 0x6b, 0xf2, 0x17, 0x0f, 0xce, 0x07, 0xd5, 0x97, ++ 0xe1, 0x83, 0x9b, 0x05, 0x1f, 0x2c, 0x3c, 0xcd, 0xc2, 0xd7, 0xc1, 0x78, ++ 0x0b, 0x97, 0xb0, 0x70, 0xed, 0x08, 0x9e, 0xda, 0x21, 0x9d, 0xab, 0xb0, ++ 0x60, 0x1c, 0xe0, 0x75, 0x2e, 0xe0, 0x20, 0x5e, 0xa4, 0x31, 0x25, 0x1c, ++ 0xaf, 0x6a, 0x41, 0x3f, 0x5e, 0x16, 0x84, 0xf4, 0x79, 0xc4, 0xa7, 0x1a, ++ 0x81, 0x67, 0xc4, 0x63, 0x64, 0x79, 0xfd, 0xfe, 0x6f, 0xcc, 0x91, 0xf9, ++ 0x21, 0x26, 0xc6, 0xac, 0xae, 0x7e, 0x3a, 0x03, 0xa1, 0x08, 0xae, 0x21, ++ 0xe3, 0x1a, 0x46, 0x35, 0x00, 0x9c, 0xd7, 0x2e, 0x09, 0xc9, 0x0c, 0xe6, ++ 0x97, 0x92, 0xee, 0xbb, 0x31, 0x07, 0xbe, 0xc7, 0x96, 0xf2, 0xf9, 0xd6, ++ 0x1f, 0xb3, 0x58, 0xd4, 0x91, 0x98, 0xf7, 0xb3, 0x2c, 0xa8, 0xf7, 0x65, ++ 0x5a, 0xf9, 0x0b, 0xb9, 0x30, 0xdf, 0x7a, 0x85, 0xf9, 0x3a, 0xa1, 0x3c, ++ 0x16, 0xf0, 0xd2, 0x01, 0xdf, 0xb7, 0x58, 0x59, 0x10, 0xfb, 0x7f, 0x2a, ++ 0x97, 0xcf, 0xd7, 0x63, 0xe2, 0xfc, 0x6b, 0x54, 0xfc, 0x6c, 0x94, 0x0d, ++ 0xe9, 0xd2, 0x1d, 0x36, 0x20, 0x5d, 0x12, 0x99, 0x03, 0xf9, 0x51, 0xc3, ++ 0xe7, 0x16, 0x3b, 0xb4, 0x2b, 0xc1, 0x76, 0x12, 0xb5, 0xeb, 0x6b, 0x6f, ++ 0x61, 0x2d, 0x31, 0x11, 0xed, 0x2b, 0x7e, 0x65, 0x65, 0x0c, 0xd6, 0xcb, ++ 0x85, 0x97, 0xec, 0x21, 0x33, 0x54, 0x65, 0x4a, 0x20, 0xc3, 0x09, 0xfd, ++ 0x25, 0x7d, 0x60, 0x66, 0xab, 0x20, 0x7f, 0xf6, 0x57, 0xf6, 0xf9, 0xd8, ++ 0xdf, 0x59, 0x23, 0x9b, 0xd6, 0x09, 0xf5, 0xdd, 0x32, 0x6b, 0xe8, 0x24, ++ 0x7e, 0x59, 0x4e, 0xf4, 0xf9, 0x19, 0xd2, 0x35, 0x11, 0xb9, 0xa9, 0x22, ++ 0x95, 0x21, 0xef, 0x4b, 0x93, 0x52, 0x99, 0x07, 0xcb, 0x97, 0xd1, 0x78, ++ 0xb5, 0x4e, 0xe0, 0xaf, 0x01, 0xe8, 0xdb, 0x57, 0x9e, 0xd9, 0x7d, 0x3b, ++ 0xe7, 0x2b, 0xb3, 0xba, 0x0d, 0xc6, 0xbb, 0xe0, 0xec, 0xf9, 0x21, 0xe6, ++ 0x01, 0x1e, 0x16, 0x84, 0xfc, 0x0f, 0x91, 0xce, 0x88, 0x97, 0x3d, 0xe3, ++ 0x46, 0xfd, 0x04, 0xbe, 0xd7, 0xfb, 0x6d, 0x5e, 0x8e, 0xfd, 0xc0, 0x28, ++ 0xe4, 0x57, 0xb3, 0xfc, 0xc0, 0xed, 0x16, 0xe0, 0xaf, 0x09, 0xf2, 0x92, ++ 0xde, 0x87, 0x60, 0x1e, 0xb5, 0xe9, 0x36, 0x87, 0x19, 0x9a, 0x54, 0x66, ++ 0xfc, 0xe7, 0x1f, 0xee, 0x84, 0xfc, 0x27, 0x7b, 0x8c, 0xcc, 0x8c, 0x74, ++ 0xde, 0x31, 0x6e, 0x1a, 0xcb, 0xba, 0x14, 0x0e, 0x2d, 0x5d, 0x10, 0x32, ++ 0x7e, 0xd8, 0x13, 0xb1, 0x5e, 0xee, 0xdb, 0xa9, 0xcf, 0xd7, 0x76, 0xea, ++ 0xf3, 0xf5, 0x4c, 0xf9, 0xb0, 0x47, 0xe3, 0x03, 0x40, 0xc1, 0x16, 0xd5, ++ 0xee, 0x3e, 0x55, 0x48, 0xb2, 0xc3, 0xfb, 0x0d, 0xf0, 0xb7, 0xd9, 0xdc, ++ 0x70, 0xba, 0x03, 0xe0, 0x35, 0xbf, 0x6c, 0xf6, 0x2e, 0x85, 0xcf, 0x8b, ++ 0xd4, 0xc0, 0x36, 0x5c, 0x4f, 0x75, 0x86, 0xde, 0x23, 0x88, 0x67, 0x73, ++ 0xc6, 0x67, 0x23, 0x02, 0x80, 0x97, 0x8a, 0x8c, 0xaf, 0x8e, 0xa4, 0x22, ++ 0xfe, 0x7f, 0xca, 0xbc, 0x08, 0xf7, 0x05, 0x6b, 0xf9, 0x0c, 0xa2, 0xc7, ++ 0x46, 0xab, 0x1a, 0x8c, 0x90, 0x5f, 0xf5, 0x82, 0xff, 0xdb, 0x87, 0x56, ++ 0x53, 0x79, 0xfb, 0x26, 0xb3, 0x2a, 0xf1, 0xf2, 0xea, 0xd1, 0x20, 0xb7, ++ 0xe6, 0xd3, 0x12, 0xa6, 0x2a, 0x16, 0x03, 0xe0, 0xbf, 0x7e, 0xc3, 0xc4, ++ 0x4f, 0xa4, 0x11, 0x54, 0x6e, 0x41, 0x7a, 0xb4, 0x03, 0x9f, 0x52, 0xbb, ++ 0x17, 0xa4, 0xd0, 0x52, 0x68, 0x37, 0x7f, 0xc3, 0xbc, 0x6a, 0x06, 0xe5, ++ 0x67, 0x58, 0xc8, 0x64, 0x01, 0x78, 0x3e, 0xd1, 0xf0, 0x2c, 0x77, 0x4d, ++ 0xb0, 0xc0, 0x7f, 0xdb, 0x5d, 0x55, 0xc3, 0x50, 0xbe, 0x28, 0x5f, 0x2b, ++ 0x7e, 0xa4, 0xff, 0x0a, 0xec, 0xea, 0x9a, 0x7e, 0x7c, 0xfd, 0xba, 0x6f, ++ 0x7d, 0x5a, 0xda, 0x4e, 0x02, 0x5e, 0x6e, 0x62, 0x12, 0x8b, 0xc7, 0x79, ++ 0x3b, 0x03, 0xbf, 0xc6, 0x79, 0xd6, 0x5a, 0x7a, 0x4c, 0xe5, 0xd0, 0xcf, ++ 0x0d, 0x5f, 0x7f, 0x49, 0x72, 0x79, 0x5e, 0xe3, 0xab, 0xd9, 0x27, 0xaf, ++ 0x42, 0x79, 0xe3, 0x9b, 0x41, 0xf4, 0x86, 0xf9, 0xa1, 0x1c, 0x99, 0xf7, ++ 0xd0, 0x41, 0xfa, 0x2e, 0x4d, 0xb6, 0x10, 0x7c, 0xa7, 0xd2, 0x6d, 0x21, ++ 0x33, 0x7c, 0x7f, 0x75, 0xa3, 0x99, 0xe7, 0x9d, 0x26, 0xca, 0x9f, 0xda, ++ 0x22, 0x51, 0x7e, 0x5e, 0xa7, 0x14, 0xb2, 0x64, 0x62, 0xfd, 0x8b, 0x09, ++ 0xe5, 0x28, 0xbf, 0xb7, 0x18, 0x1d, 0x66, 0x76, 0x29, 0x9e, 0xa2, 0xf1, ++ 0xf2, 0xf1, 0xe6, 0xff, 0x88, 0x63, 0x00, 0xf2, 0xc7, 0x8c, 0x55, 0xe1, ++ 0xfa, 0x62, 0x8e, 0x86, 0x38, 0xbf, 0x1d, 0xcb, 0x1a, 0xe2, 0x26, 0x17, ++ 0x23, 0xbe, 0x6e, 0xfc, 0x04, 0xe5, 0xd7, 0xbc, 0x2d, 0xb2, 0x37, 0x8c, ++ 0x72, 0xfa, 0x15, 0xbb, 0x37, 0x97, 0x61, 0x7e, 0xfc, 0xb0, 0x39, 0x36, ++ 0x6c, 0xff, 0x45, 0x42, 0x39, 0xe2, 0x6f, 0xeb, 0x78, 0x87, 0x4c, 0xdf, ++ 0x65, 0x3f, 0xca, 0x21, 0xa6, 0xf8, 0xba, 0x6f, 0x80, 0xef, 0xca, 0xd6, ++ 0xab, 0x55, 0x5c, 0x2f, 0x87, 0xb7, 0x70, 0xb8, 0xe7, 0x39, 0x2d, 0xcf, ++ 0x20, 0x9d, 0x6f, 0xf8, 0x5a, 0x26, 0xfe, 0x57, 0x0c, 0x2c, 0xb0, 0xdb, ++ 0x86, 0x74, 0xf0, 0x0d, 0xc3, 0x75, 0xa7, 0x6e, 0xde, 0x31, 0x01, 0xf1, ++ 0xfb, 0x71, 0x4d, 0x8a, 0x81, 0xea, 0x3f, 0x2f, 0x31, 0x07, 0xe2, 0xc3, ++ 0xd9, 0x98, 0x84, 0xdf, 0xe7, 0x49, 0x8a, 0x1f, 0xd7, 0xd9, 0xfc, 0x0d, ++ 0x0b, 0xaa, 0x59, 0x5c, 0x3f, 0xde, 0x57, 0xa9, 0x32, 0xad, 0x9b, 0xf2, ++ 0x8c, 0x25, 0x49, 0x3d, 0x36, 0xe2, 0xfb, 0xdb, 0x51, 0xdf, 0xd5, 0x6e, ++ 0x01, 0x3e, 0xc7, 0xf1, 0x27, 0xbf, 0xff, 0x87, 0x3b, 0xdd, 0xfd, 0x7c, ++ 0x2f, 0x4d, 0xde, 0x70, 0xcb, 0xb5, 0xd8, 0xff, 0xb3, 0x46, 0xe2, 0x2f, ++ 0xad, 0x9f, 0xfa, 0xcd, 0x37, 0x0b, 0xfe, 0x60, 0x2c, 0x0c, 0x78, 0x9a, ++ 0x27, 0xf0, 0x64, 0xce, 0x58, 0x92, 0x87, 0xe3, 0x5f, 0x6e, 0x3d, 0xcc, ++ 0x5b, 0xd6, 0x90, 0xe7, 0xb0, 0x5d, 0x7e, 0x5d, 0xf4, 0xad, 0xf7, 0xcd, ++ 0x7c, 0x7d, 0x48, 0x99, 0x12, 0xc9, 0x55, 0x96, 0xe6, 0x22, 0x3d, 0x33, ++ 0xd8, 0x7a, 0xd4, 0xf4, 0x93, 0xad, 0xc0, 0x40, 0xf2, 0xde, 0xe2, 0x65, ++ 0xbe, 0x1d, 0x90, 0x0e, 0x31, 0x33, 0x9f, 0x04, 0xf2, 0x2b, 0x2f, 0x53, ++ 0x21, 0x3c, 0xe4, 0x65, 0x9a, 0xa8, 0x9e, 0xf2, 0x97, 0x45, 0x3b, 0xdf, ++ 0x04, 0xf8, 0xf7, 0xa9, 0x81, 0xf8, 0x4c, 0xf8, 0x9e, 0xc1, 0x7c, 0xa3, ++ 0x50, 0xcf, 0xa8, 0xbd, 0x8e, 0x8a, 0x78, 0xe8, 0xcd, 0x86, 0x0c, 0x52, ++ 0x8a, 0x70, 0x98, 0x43, 0x3b, 0x48, 0xce, 0x41, 0x1e, 0xf0, 0xb4, 0x3e, ++ 0x91, 0x3d, 0xb3, 0x2a, 0x02, 0xce, 0x2c, 0xec, 0x6f, 0x34, 0xad, 0x57, ++ 0x4f, 0x26, 0xf4, 0x7b, 0xf6, 0xbd, 0xaf, 0x8e, 0x20, 0x1e, 0xeb, 0x86, ++ 0x7e, 0x36, 0x02, 0xf5, 0x76, 0xfd, 0xc5, 0x2f, 0x4d, 0x2a, 0xd0, 0xd3, ++ 0xd6, 0x25, 0x91, 0x9c, 0xb5, 0x79, 0xfd, 0x0c, 0xf9, 0xa3, 0xbe, 0xab, ++ 0x86, 0xcd, 0x2e, 0xea, 0x97, 0x8f, 0xf5, 0x5e, 0x2e, 0xbf, 0xa3, 0xe7, ++ 0x55, 0x9b, 0x69, 0xe4, 0xeb, 0xcc, 0xdd, 0x4b, 0xfd, 0xdc, 0x9c, 0xc5, ++ 0xd7, 0x5d, 0xbb, 0x93, 0xaf, 0xcf, 0x4d, 0x8d, 0x31, 0x21, 0x94, 0x7b, ++ 0x9b, 0xdc, 0x21, 0x2b, 0x02, 0x1d, 0x5b, 0x1a, 0x64, 0x28, 0xdf, 0x6f, ++ 0x29, 0x95, 0xbd, 0x08, 0xb6, 0x66, 0xa7, 0xf8, 0x2d, 0x9c, 0x5e, 0x16, ++ 0xdf, 0xab, 0x4c, 0x46, 0x7e, 0xf5, 0xca, 0x5e, 0x14, 0xf1, 0xdd, 0xbe, ++ 0x8f, 0x5a, 0x12, 0x20, 0xff, 0x66, 0xe9, 0x78, 0xaf, 0x0c, 0x79, 0x9b, ++ 0xef, 0xe9, 0xd6, 0x2c, 0x9c, 0xb7, 0xd7, 0x28, 0xca, 0xb3, 0x83, 0x38, ++ 0xef, 0x37, 0xc6, 0x96, 0x93, 0xbd, 0x72, 0x8b, 0x4f, 0xa6, 0x71, 0xd9, ++ 0xfc, 0xb8, 0x10, 0xaa, 0x8a, 0x6e, 0xdf, 0x3b, 0xee, 0xd9, 0x30, 0xee, ++ 0xad, 0xcc, 0xb7, 0xf6, 0x24, 0xd0, 0xb1, 0x0a, 0x94, 0x37, 0xd2, 0xb1, ++ 0x1b, 0xc7, 0x06, 0x7a, 0x9d, 0x71, 0x04, 0xc6, 0x22, 0x5e, 0xb4, 0xf9, ++ 0xdc, 0xec, 0x9d, 0xb8, 0xf6, 0x64, 0xa4, 0x9d, 0xe1, 0xe3, 0xf6, 0x00, ++ 0x7c, 0xe2, 0x7a, 0xac, 0x74, 0x60, 0x3c, 0x94, 0xa8, 0xe5, 0x15, 0x48, ++ 0xa7, 0x1b, 0xae, 0xe7, 0x74, 0xf8, 0xf4, 0x79, 0x73, 0x68, 0x19, 0x8c, ++ 0xff, 0xa9, 0x15, 0xf4, 0x4c, 0x84, 0xbe, 0xf8, 0xd4, 0xce, 0xf5, 0xce, ++ 0xd4, 0x4c, 0xae, 0xc7, 0x18, 0xeb, 0x1c, 0x8a, 0x72, 0xbf, 0x2f, 0xaf, ++ 0x0c, 0x33, 0xe0, 0xba, 0x7f, 0xc0, 0xc1, 0xf1, 0xe1, 0x36, 0x75, 0x0e, ++ 0xc5, 0xf5, 0xf6, 0x27, 0x49, 0xdf, 0xcf, 0xbd, 0xad, 0x32, 0x0b, 0x81, ++ 0x9c, 0x59, 0xd0, 0x2a, 0xb1, 0x10, 0x80, 0xf8, 0xe9, 0xcf, 0x5f, 0x1c, ++ 0x8a, 0xf2, 0xf7, 0x93, 0x1d, 0x2f, 0x0e, 0x9d, 0x19, 0x01, 0x5f, 0x74, ++ 0x3b, 0x2d, 0x9d, 0xae, 0x8d, 0xd7, 0xf6, 0x84, 0xcf, 0x02, 0xe3, 0xcd, ++ 0x64, 0xda, 0x78, 0xe1, 0x34, 0x1c, 0x6f, 0xa6, 0xd7, 0x7c, 0x02, 0xe5, ++ 0x07, 0x6b, 0x1d, 0xef, 0xeb, 0x89, 0xb0, 0x1f, 0x48, 0x42, 0x46, 0xd4, ++ 0x67, 0x1b, 0x7c, 0x24, 0xbf, 0xcf, 0xc1, 0x6a, 0x44, 0xbe, 0xd3, 0xda, ++ 0x9d, 0x9b, 0x1f, 0xe3, 0x43, 0x3b, 0xf3, 0x1c, 0xb3, 0x84, 0x24, 0x18, ++ 0x6a, 0x66, 0x97, 0x1c, 0x36, 0x63, 0x7f, 0x3e, 0x5f, 0x8e, 0x1b, 0xe8, ++ 0x5d, 0xa7, 0xb5, 0x8f, 0xea, 0x7f, 0x03, 0xf2, 0x0f, 0xc0, 0x25, 0xed, ++ 0x97, 0xc2, 0x76, 0xa8, 0x1f, 0x5b, 0xd4, 0x4b, 0xf2, 0x76, 0x81, 0xc5, ++ 0x7f, 0x24, 0x15, 0x8a, 0x16, 0x20, 0x1d, 0xa1, 0xfe, 0x44, 0xa4, 0xa3, ++ 0x84, 0xfc, 0xea, 0x33, 0xe1, 0xbc, 0x15, 0x89, 0xcb, 0xf3, 0x33, 0x0e, ++ 0xff, 0x83, 0x48, 0x87, 0x39, 0x6d, 0x7a, 0x3a, 0x66, 0x66, 0x3a, 0xb8, ++ 0x7c, 0x77, 0xb8, 0x89, 0xee, 0xa6, 0x3a, 0x9b, 0x82, 0xfa, 0x22, 0xa9, ++ 0x99, 0x71, 0x3b, 0xf0, 0x41, 0x43, 0x08, 0xf5, 0xb5, 0x3b, 0x26, 0x6e, ++ 0x04, 0x03, 0x3b, 0xc6, 0x94, 0xe2, 0xb1, 0xa1, 0x9c, 0xba, 0x21, 0x2f, ++ 0xa6, 0xc5, 0x10, 0x8f, 0xdf, 0x87, 0x86, 0xb0, 0x7e, 0x7a, 0x4a, 0x01, ++ 0xb5, 0x0b, 0x56, 0x70, 0xfe, 0x0e, 0x26, 0xb1, 0x50, 0xb3, 0x84, 0x5d, ++ 0x36, 0x48, 0x64, 0x07, 0x3a, 0x7a, 0x98, 0x02, 0xdf, 0xd3, 0xc6, 0x30, ++ 0xc7, 0x2a, 0x94, 0x45, 0x99, 0xdc, 0x4e, 0xf4, 0x30, 0xef, 0x06, 0x99, ++ 0xec, 0xc4, 0x4e, 0x09, 0xed, 0x44, 0x0d, 0x0f, 0x9a, 0x7c, 0x47, 0xbe, ++ 0x41, 0xb9, 0xf7, 0xa9, 0x64, 0x21, 0xbe, 0x91, 0xba, 0x24, 0xb2, 0xfb, ++ 0x64, 0x43, 0xe7, 0x74, 0xec, 0x77, 0x30, 0x3e, 0xda, 0x12, 0xc5, 0x47, ++ 0x5b, 0xfe, 0xc9, 0x7c, 0xf4, 0xec, 0xa0, 0x7c, 0x14, 0x50, 0x89, 0x8f, ++ 0x3c, 0x96, 0x81, 0xf9, 0x08, 0xf6, 0x4d, 0xdf, 0xa9, 0x3e, 0x0b, 0xfa, ++ 0x15, 0xc0, 0xd7, 0x10, 0x81, 0xaf, 0xc7, 0x85, 0x7c, 0xe9, 0x7d, 0xd0, ++ 0x42, 0x74, 0x83, 0x1f, 0x09, 0xe7, 0x5b, 0x2d, 0xfa, 0xab, 0xb6, 0xd8, ++ 0xc2, 0xf2, 0x08, 0x92, 0x13, 0x9f, 0xf5, 0xc9, 0x6f, 0xe8, 0x67, 0x33, ++ 0xd8, 0x9f, 0xb8, 0x4f, 0x49, 0x46, 0xfb, 0x19, 0xd2, 0xd4, 0xe6, 0x19, ++ 0x2a, 0xb7, 0xdf, 0xbb, 0x7b, 0x24, 0xe8, 0x2f, 0xf6, 0x6a, 0x0b, 0xe9, ++ 0xbd, 0x47, 0x0c, 0xdd, 0x99, 0x68, 0xe7, 0x0f, 0x19, 0xde, 0xb0, 0x1b, ++ 0xf9, 0x63, 0xc8, 0xf4, 0xa2, 0x92, 0x66, 0xb2, 0x4f, 0xd2, 0x9c, 0x28, ++ 0xf7, 0x51, 0xd6, 0xe0, 0xfc, 0xeb, 0x1a, 0xc7, 0xf9, 0xb9, 0x1d, 0x00, ++ 0xfd, 0x22, 0x1f, 0xd5, 0x98, 0x68, 0x3f, 0x51, 0xf7, 0x50, 0xb9, 0x9f, ++ 0xdb, 0x01, 0x55, 0xb4, 0x3e, 0xea, 0x57, 0x5b, 0x55, 0xd4, 0x67, 0xe3, ++ 0xba, 0x32, 0x97, 0x22, 0x7f, 0xd4, 0x2f, 0x01, 0xfb, 0x08, 0xe5, 0xef, ++ 0xfe, 0x8e, 0x8d, 0x73, 0x21, 0x5f, 0x37, 0xd5, 0xe6, 0x45, 0x3b, 0xc5, ++ 0x6a, 0x99, 0x52, 0x84, 0xed, 0x58, 0xab, 0x7e, 0x9d, 0xad, 0x94, 0x3a, ++ 0xc9, 0x2e, 0x0e, 0x4e, 0x64, 0x5e, 0x94, 0xdb, 0xe7, 0x42, 0x86, 0xa0, ++ 0x71, 0x24, 0xca, 0xd9, 0x9e, 0xad, 0x3f, 0x41, 0x3d, 0xbe, 0xa0, 0xc8, ++ 0x1b, 0x54, 0x71, 0xbd, 0x09, 0xbe, 0xcc, 0x61, 0xa4, 0x17, 0xda, 0x9d, ++ 0xbe, 0x64, 0x17, 0xe0, 0x75, 0xdf, 0xdf, 0x64, 0xda, 0x17, 0xb5, 0x8f, ++ 0x82, 0x3c, 0xa4, 0x2f, 0x0b, 0x7a, 0xb6, 0xd7, 0xf8, 0x92, 0x9d, 0x90, ++ 0x9f, 0xb9, 0xda, 0x4a, 0x78, 0x6f, 0xef, 0xe0, 0xe5, 0xe7, 0xec, 0x80, ++ 0x20, 0xe8, 0x3f, 0x45, 0xe6, 0xfd, 0xb1, 0x78, 0x0b, 0xd7, 0x33, 0x97, ++ 0xca, 0x03, 0x0b, 0xe2, 0x3d, 0x69, 0x0c, 0xd3, 0x7e, 0x36, 0x60, 0x3e, ++ 0x45, 0xcb, 0xb7, 0x3d, 0x41, 0x76, 0x8c, 0xb6, 0xde, 0xdb, 0x33, 0x39, ++ 0x3c, 0xf6, 0x22, 0x7f, 0x26, 0x5a, 0xbe, 0x01, 0x75, 0x74, 0x77, 0x0c, ++ 0xf0, 0x4f, 0x92, 0x6c, 0xd0, 0x36, 0x45, 0x41, 0xb4, 0xbb, 0x63, 0x71, ++ 0x4c, 0x9e, 0xf7, 0xe1, 0x70, 0xeb, 0x0c, 0x00, 0x48, 0x0a, 0x66, 0xbf, ++ 0x5e, 0x53, 0x39, 0x36, 0x32, 0xcf, 0xeb, 0xf7, 0xb7, 0x7f, 0x64, 0x72, ++ 0x65, 0x1a, 0xe9, 0xd7, 0xbe, 0x72, 0x04, 0x1b, 0xf4, 0xae, 0x96, 0xf7, ++ 0x59, 0x01, 0x8e, 0x15, 0xf6, 0xfe, 0x72, 0x05, 0xec, 0x49, 0xcb, 0x7e, ++ 0x49, 0xb4, 0xbf, 0x76, 0xf2, 0xf8, 0x1c, 0x98, 0xbf, 0x24, 0xc6, 0x0f, ++ 0x9a, 0xd6, 0xf8, 0x00, 0xde, 0xc7, 0xad, 0x4c, 0x37, 0x5e, 0x24, 0x7c, ++ 0x4a, 0x54, 0xff, 0x46, 0x15, 0xf7, 0xf5, 0xa2, 0x7e, 0x70, 0xa4, 0x7f, ++ 0x3c, 0x54, 0x58, 0x57, 0xa2, 0xb5, 0x6f, 0x6e, 0xf3, 0x01, 0xfc, 0x8f, ++ 0x1b, 0xf5, 0xfd, 0x11, 0x4a, 0x45, 0x7b, 0xcc, 0x68, 0xe3, 0xfd, 0x2e, ++ 0xe7, 0x77, 0x6b, 0x56, 0x8f, 0xed, 0xd7, 0xff, 0x60, 0x0f, 0x38, 0xb3, ++ 0x46, 0xf7, 0xdb, 0x01, 0x2b, 0xde, 0xaf, 0x6e, 0x1b, 0x09, 0x63, 0xc5, ++ 0x3a, 0xbe, 0x30, 0xa1, 0x7e, 0xd5, 0xf4, 0x79, 0xbd, 0x5b, 0x22, 0x3b, ++ 0x23, 0x7a, 0xbd, 0xa6, 0x66, 0x71, 0x7f, 0x05, 0xd8, 0xb5, 0xa9, 0x59, ++ 0x11, 0xf6, 0x6e, 0x35, 0xda, 0xbb, 0x32, 0xd9, 0xb9, 0x13, 0x70, 0x69, ++ 0xd5, 0x2f, 0xf1, 0x33, 0xb4, 0x2f, 0xc1, 0x6e, 0xc8, 0xc0, 0xf1, 0xce, ++ 0xbe, 0xf7, 0xd9, 0xa9, 0x83, 0xf0, 0xbd, 0x7d, 0xf2, 0xa7, 0x64, 0xe7, ++ 0xd7, 0x5f, 0x54, 0xc8, 0xfe, 0xa8, 0x07, 0xfb, 0x03, 0xed, 0x76, 0x4b, ++ 0x17, 0xb7, 0x67, 0xd9, 0x7e, 0x23, 0xe9, 0x5d, 0x8d, 0xee, 0xf7, 0x0a, ++ 0xf9, 0xd3, 0xee, 0x04, 0xbd, 0x8f, 0x7c, 0xfa, 0x8a, 0x34, 0x1a, 0xf9, ++ 0x94, 0xb1, 0x86, 0xa1, 0xb7, 0x01, 0x0d, 0x9a, 0xb3, 0x7c, 0xc3, 0x10, ++ 0x0e, 0x6d, 0x3f, 0x16, 0x0d, 0x6f, 0x45, 0x16, 0xb7, 0xcb, 0xeb, 0x0b, ++ 0x2a, 0x36, 0xe6, 0x61, 0xff, 0xdb, 0x25, 0x86, 0x7a, 0x7f, 0x55, 0xc1, ++ 0x87, 0x49, 0x68, 0x9f, 0xd4, 0x77, 0x9d, 0x48, 0x9a, 0x13, 0xd1, 0x6e, ++ 0xc1, 0xfe, 0x75, 0x84, 0x87, 0x05, 0x3b, 0x8d, 0x03, 0xce, 0xbf, 0x22, ++ 0x8b, 0xdb, 0x9b, 0x75, 0x2f, 0xed, 0xf5, 0xe1, 0x7a, 0xff, 0x34, 0x24, ++ 0xd1, 0x5a, 0x9e, 0xaf, 0x84, 0x56, 0xa2, 0x5d, 0x39, 0x7f, 0xbe, 0x01, ++ 0x2d, 0x35, 0x56, 0x1a, 0x9a, 0x71, 0x27, 0xae, 0x7b, 0x36, 0xcd, 0xc4, ++ 0x72, 0x61, 0x7e, 0x05, 0xc2, 0xae, 0xa9, 0xdf, 0x39, 0x25, 0x78, 0x2d, ++ 0xee, 0xdb, 0xe0, 0xaf, 0x04, 0x9f, 0x36, 0xf9, 0xe7, 0xd2, 0xfa, 0xde, ++ 0x34, 0xcd, 0x62, 0x63, 0x99, 0x08, 0xe7, 0xcc, 0xfb, 0x09, 0x0f, 0x8e, ++ 0x18, 0x1f, 0xe2, 0x61, 0x55, 0x41, 0x45, 0x32, 0x8e, 0x53, 0x57, 0x33, ++ 0xc1, 0x81, 0xfe, 0x93, 0x7a, 0xb0, 0xb3, 0xb0, 0xbc, 0xee, 0xa1, 0xbb, ++ 0xc8, 0x9f, 0xd2, 0x67, 0x07, 0xef, 0x37, 0x56, 0xa1, 0xfd, 0x55, 0x06, ++ 0xf6, 0xd6, 0xbf, 0x01, 0xdc, 0xe9, 0xae, 0x49, 0x55, 0x5e, 0x58, 0x8f, ++ 0xa9, 0xf2, 0xee, 0x51, 0x8b, 0x21, 0xbf, 0x7e, 0x10, 0xf9, 0xfb, 0x5e, ++ 0x36, 0xa7, 0x67, 0x8b, 0xe4, 0x0f, 0xde, 0x8a, 0xeb, 0xfe, 0x25, 0x89, ++ 0xed, 0x50, 0xfb, 0xcb, 0x33, 0xf6, 0x73, 0xbb, 0xee, 0xae, 0x2c, 0x6e, ++ 0x07, 0x6a, 0xdf, 0xef, 0xca, 0x52, 0xa8, 0xdd, 0xd8, 0x60, 0xf7, 0x38, ++ 0xe4, 0xbd, 0x03, 0x4a, 0x4f, 0x2c, 0xda, 0xbf, 0xf5, 0xcc, 0xf7, 0x39, ++ 0xee, 0x3b, 0x99, 0xdf, 0xa6, 0xee, 0x20, 0x3a, 0x71, 0xb9, 0xe3, 0x6e, ++ 0x52, 0xc9, 0xaf, 0x64, 0x71, 0xf7, 0x3c, 0x32, 0x12, 0xcb, 0xc7, 0x2a, ++ 0xb4, 0x9f, 0x60, 0x4a, 0xcf, 0x5a, 0x1c, 0xf7, 0xec, 0x4a, 0xb7, 0x77, ++ 0x15, 0x13, 0xfc, 0x8b, 0xf9, 0x87, 0x8a, 0x42, 0x28, 0x47, 0x8f, 0x66, ++ 0x05, 0xe6, 0x21, 0xff, 0x94, 0x09, 0x3b, 0xf2, 0xec, 0x4b, 0x37, 0x8e, ++ 0x9a, 0x59, 0xd4, 0x6f, 0x27, 0xad, 0xec, 0xb0, 0x86, 0x96, 0x01, 0x1e, ++ 0x56, 0xda, 0xd5, 0x7f, 0xa9, 0x42, 0xf9, 0xf6, 0x17, 0x85, 0xe4, 0x1b, ++ 0xb3, 0xf4, 0x76, 0x8f, 0x43, 0x7a, 0xfc, 0xd5, 0x45, 0xfd, 0xae, 0xb4, ++ 0x86, 0x56, 0x22, 0xfd, 0x83, 0x6b, 0x8c, 0x54, 0xbe, 0x3b, 0x25, 0xb0, ++ 0x08, 0xf9, 0xe6, 0x74, 0x4d, 0x55, 0x1e, 0xee, 0x83, 0x99, 0x2d, 0x98, ++ 0x57, 0x03, 0xfc, 0x64, 0x74, 0xb7, 0x31, 0xb4, 0x17, 0x60, 0xfb, 0x40, ++ 0x7e, 0x06, 0x8b, 0xdb, 0xcf, 0x54, 0xc8, 0x8f, 0x0b, 0xce, 0x50, 0x24, ++ 0x94, 0xf3, 0x51, 0xf6, 0xc7, 0x38, 0xf4, 0xf3, 0xd0, 0xbe, 0x01, 0x06, ++ 0x87, 0xef, 0x15, 0x42, 0x6c, 0xe5, 0x02, 0x17, 0x9c, 0xb2, 0xd0, 0x12, ++ 0x68, 0xf9, 0x26, 0xa1, 0xdf, 0x1e, 0x39, 0xfa, 0xd5, 0x54, 0x05, 0x3f, ++ 0x6a, 0x76, 0x8a, 0xc1, 0x12, 0x58, 0x80, 0x4d, 0x2b, 0xa7, 0xc5, 0x30, ++ 0x19, 0xf9, 0x7e, 0x79, 0xef, 0x11, 0x03, 0xcc, 0x27, 0xd6, 0xdd, 0x4d, ++ 0x76, 0x6c, 0x6d, 0xa7, 0x44, 0xe3, 0xd4, 0x16, 0xbc, 0x60, 0x42, 0xbf, ++ 0xc9, 0x7d, 0x9d, 0x7c, 0x5d, 0xd6, 0x8b, 0x7d, 0x00, 0xe0, 0x6f, 0x28, ++ 0xda, 0x03, 0x8f, 0x64, 0xc5, 0x8a, 0xfd, 0x67, 0x0b, 0xf5, 0x5b, 0xcf, ++ 0xba, 0x69, 0x1f, 0xcd, 0x76, 0x71, 0x7a, 0x32, 0x06, 0xf5, 0xec, 0x91, ++ 0xfb, 0x89, 0xa5, 0x54, 0x4f, 0xeb, 0xcf, 0xb4, 0x8c, 0xfb, 0xbd, 0x6a, ++ 0x85, 0x3f, 0x06, 0x7a, 0xa4, 0xf2, 0xf5, 0x62, 0xbd, 0x6b, 0xfe, 0x09, ++ 0x58, 0x98, 0xc2, 0x3e, 0xe0, 0xe3, 0xae, 0x97, 0xba, 0x7d, 0x32, 0xe2, ++ 0x75, 0x94, 0xe4, 0x8d, 0xe4, 0x1b, 0x2d, 0x7d, 0x3e, 0x8b, 0xeb, 0xf7, ++ 0xf8, 0x43, 0xbd, 0x13, 0x70, 0xfd, 0xf6, 0x02, 0x7f, 0xa1, 0x5f, 0x66, ++ 0xa3, 0x54, 0x73, 0xff, 0x6b, 0x30, 0xbf, 0x8d, 0xa3, 0x87, 0x7b, 0xd1, ++ 0x84, 0xf2, 0x00, 0x3b, 0xc9, 0x25, 0xf8, 0x1d, 0x58, 0x11, 0xf0, 0x5e, ++ 0xba, 0xff, 0xf3, 0x09, 0xc8, 0x37, 0x60, 0x70, 0xd3, 0x7a, 0xad, 0xdb, ++ 0x5f, 0x2e, 0xd7, 0xda, 0x48, 0x6f, 0xd3, 0xfe, 0x71, 0x48, 0x6c, 0x43, ++ 0x07, 0x96, 0x0f, 0xb9, 0xa7, 0x80, 0xf4, 0x6a, 0xcc, 0x55, 0xec, 0x9e, ++ 0xc9, 0xf0, 0xfd, 0x05, 0xb1, 0xce, 0x92, 0x6d, 0xdc, 0xcf, 0xe5, 0x59, ++ 0x16, 0xcc, 0x5c, 0x54, 0x84, 0xe3, 0xfb, 0xef, 0x7f, 0x0d, 0xc7, 0x2f, ++ 0x8e, 0x21, 0x3f, 0xe5, 0x10, 0xa0, 0x8d, 0xdd, 0x45, 0x69, 0x2b, 0xfa, ++ 0x85, 0x3c, 0x6c, 0xa9, 0x84, 0xf5, 0xd6, 0xc5, 0xf1, 0xfe, 0x13, 0x0d, ++ 0xf2, 0x3d, 0x35, 0x45, 0x24, 0x77, 0x29, 0xef, 0xf2, 0x4a, 0xbe, 0x6d, ++ 0x90, 0x76, 0x65, 0x39, 0xa9, 0x7f, 0xd8, 0x77, 0x55, 0x21, 0x9c, 0xf8, ++ 0x9d, 0xf6, 0x63, 0xc0, 0x19, 0xb8, 0x9f, 0x45, 0x3f, 0x17, 0xf6, 0x33, ++ 0x24, 0x9b, 0xa7, 0x67, 0x93, 0xc3, 0x0a, 0x0a, 0x88, 0x4d, 0xac, 0x67, ++ 0xeb, 0x0e, 0xe4, 0xcf, 0xfd, 0x66, 0x07, 0xe2, 0xa9, 0x7a, 0xff, 0x6f, ++ 0x8e, 0xa1, 0xbe, 0xac, 0xb6, 0xb0, 0x4e, 0x19, 0xed, 0x95, 0x28, 0x3b, ++ 0x63, 0x49, 0xfa, 0x94, 0xd7, 0x90, 0x3f, 0xcf, 0x9d, 0x39, 0xb5, 0xf5, ++ 0x61, 0xf8, 0xb6, 0xee, 0xb6, 0x7d, 0xde, 0x00, 0xd1, 0x45, 0x6f, 0x3f, ++ 0x44, 0xef, 0x17, 0xb6, 0x61, 0x95, 0xe4, 0xc1, 0xed, 0xbd, 0x0f, 0xfa, ++ 0xe8, 0xc9, 0xed, 0xbd, 0xbe, 0xfc, 0x3f, 0xdc, 0xde, 0xe3, 0x76, 0x7d, ++ 0x70, 0x47, 0xac, 0xba, 0x23, 0x42, 0x9e, 0xd7, 0x8b, 0x7d, 0xda, 0xb9, ++ 0xf9, 0xe7, 0xe3, 0x50, 0xcf, 0x7c, 0xdc, 0x07, 0x0f, 0xe8, 0xe9, 0xb2, ++ 0x7e, 0x7b, 0x65, 0xe6, 0xf6, 0xd8, 0x13, 0xb8, 0xae, 0xfa, 0xec, 0xfe, ++ 0x28, 0xbb, 0xe1, 0xe8, 0x33, 0xb1, 0x41, 0xa4, 0xff, 0xf9, 0x4e, 0x2b, ++ 0xf9, 0xe9, 0x14, 0xb4, 0x7b, 0x00, 0x9e, 0x33, 0xf6, 0xde, 0x1f, 0x22, ++ 0x72, 0xdc, 0x26, 0xbf, 0x4f, 0xc2, 0xfd, 0xc3, 0x6e, 0xa3, 0x77, 0x19, ++ 0xf4, 0x57, 0x7f, 0xef, 0xa7, 0xbf, 0x30, 0xc0, 0xba, 0x53, 0x3a, 0xc0, ++ 0xee, 0x89, 0x47, 0x7b, 0x5f, 0x8d, 0x27, 0x39, 0xfb, 0xba, 0xcc, 0x76, ++ 0xa0, 0x5d, 0xa6, 0xf8, 0x1c, 0xe8, 0xf7, 0xd0, 0xe0, 0x57, 0x9c, 0x13, ++ 0x3c, 0xa8, 0xb7, 0x5b, 0xc4, 0xfc, 0x17, 0x9a, 0xc2, 0x79, 0x64, 0x07, ++ 0x99, 0xd8, 0x7c, 0xca, 0xc7, 0x85, 0xf3, 0xd0, 0xee, 0x79, 0x59, 0xe8, ++ 0x9d, 0x85, 0x31, 0x90, 0x87, 0xef, 0x8d, 0x9e, 0xc0, 0xd7, 0x48, 0xb7, ++ 0x14, 0x33, 0x97, 0x57, 0xd8, 0x0e, 0xbf, 0x77, 0x08, 0x7b, 0xab, 0x03, ++ 0x50, 0xe2, 0x40, 0xbc, 0x1c, 0x83, 0x7d, 0x77, 0xa6, 0xd0, 0xdf, 0xb8, ++ 0xff, 0x79, 0x34, 0x3d, 0xb4, 0x8a, 0xfc, 0x38, 0x16, 0xa2, 0xe7, 0x47, ++ 0x07, 0xcc, 0xdb, 0xd0, 0xcf, 0xf3, 0x51, 0x81, 0x21, 0x6c, 0xe2, 0x7e, ++ 0x09, 0xf2, 0x63, 0xa9, 0xad, 0x0a, 0x4b, 0x86, 0xfa, 0xea, 0x31, 0x6b, ++ 0x48, 0xe5, 0xfe, 0x2e, 0x8b, 0x01, 0xf4, 0xff, 0xac, 0xc7, 0xef, 0x7b, ++ 0x03, 0xf7, 0x15, 0xb3, 0x0e, 0x70, 0x3f, 0xd6, 0xac, 0x7b, 0x97, 0xdc, ++ 0x82, 0xfb, 0x8f, 0x8f, 0x26, 0x4f, 0x30, 0xa1, 0xbc, 0x99, 0xc3, 0x02, ++ 0xe4, 0x77, 0x9e, 0xc7, 0xb8, 0x1f, 0x7a, 0x01, 0x0b, 0x71, 0x7f, 0x35, ++ 0x73, 0x18, 0x70, 0xbc, 0xfb, 0x40, 0x6c, 0x6c, 0x42, 0x51, 0x13, 0x04, ++ 0xec, 0x5f, 0x0d, 0x9f, 0x25, 0x83, 0x84, 0x76, 0x85, 0xda, 0x02, 0x79, ++ 0x32, 0x9a, 0x7d, 0x6d, 0x55, 0x30, 0xee, 0xcc, 0x16, 0x03, 0xed, 0x4b, ++ 0x66, 0xb5, 0xea, 0xfd, 0xe9, 0x17, 0x56, 0xdd, 0x5f, 0x85, 0x7a, 0x7c, ++ 0x45, 0x8b, 0x81, 0xdb, 0x8f, 0xad, 0x12, 0xe9, 0xf1, 0x59, 0xcc, 0xe7, ++ 0x41, 0xbb, 0x43, 0xc3, 0x6b, 0x61, 0x76, 0x02, 0xc9, 0x83, 0x60, 0x8b, ++ 0xc1, 0x87, 0xe3, 0x8c, 0xcb, 0xe6, 0x7a, 0x05, 0x48, 0x14, 0xa2, 0xf9, ++ 0x89, 0xb4, 0xc5, 0x28, 0xfc, 0xf0, 0x02, 0x8e, 0xa5, 0xcc, 0x10, 0xc6, ++ 0xd4, 0x20, 0xf1, 0x74, 0x85, 0x43, 0xa9, 0x1a, 0x48, 0x3f, 0x6b, 0xfd, ++ 0xb5, 0x18, 0x1b, 0x2c, 0xe8, 0x0f, 0xeb, 0x4d, 0x37, 0x90, 0x1f, 0xf8, ++ 0x82, 0xc9, 0x37, 0x8d, 0xfc, 0xa8, 0xae, 0x3c, 0x86, 0x7e, 0xc4, 0x16, ++ 0x7b, 0x43, 0x6b, 0x15, 0x2f, 0xa7, 0x35, 0x73, 0xc1, 0xda, 0xeb, 0xa7, ++ 0xf2, 0xeb, 0x14, 0x6e, 0xf0, 0x31, 0xd5, 0x85, 0xf2, 0x32, 0x33, 0xdb, ++ 0x40, 0xfd, 0x45, 0xcf, 0x77, 0x4e, 0x9b, 0x3e, 0x1f, 0x7d, 0x3e, 0xb1, ++ 0x20, 0xa4, 0xcf, 0xcf, 0x62, 0x81, 0xfc, 0xe4, 0x6c, 0xf4, 0x1b, 0xe9, ++ 0xbf, 0x67, 0x66, 0x73, 0x3d, 0x70, 0x61, 0x55, 0xa6, 0x38, 0x07, 0xf0, ++ 0xd2, 0x39, 0x40, 0x8b, 0x51, 0x7d, 0x3b, 0x13, 0xe5, 0xd5, 0x4a, 0x85, ++ 0xe4, 0xe5, 0xd2, 0x34, 0x8e, 0x2f, 0x43, 0x3a, 0x4f, 0xb3, 0x9c, 0x95, ++ 0xd3, 0x88, 0x7f, 0x9d, 0x60, 0x5f, 0x10, 0xbc, 0x1c, 0xfe, 0xac, 0xeb, ++ 0xdc, 0x12, 0xea, 0xcd, 0x16, 0x27, 0xe7, 0xcb, 0xff, 0x29, 0xdc, 0xd1, ++ 0xf0, 0xde, 0x94, 0x9d, 0xc7, 0xf1, 0x8b, 0x46, 0x1e, 0x8c, 0xd7, 0xb2, ++ 0x52, 0x0a, 0x71, 0x7c, 0x71, 0xb8, 0xaf, 0xd4, 0x7f, 0xb1, 0x30, 0x5b, ++ 0xbf, 0xef, 0xec, 0xcb, 0xff, 0xe3, 0xf7, 0x9d, 0x9c, 0x1f, 0x57, 0xca, ++ 0x62, 0xbd, 0x39, 0x48, 0x0e, 0xcd, 0x74, 0xf0, 0x39, 0x7d, 0x24, 0x79, ++ 0x9f, 0x09, 0xe3, 0x77, 0x1b, 0xd8, 0x07, 0x00, 0xf7, 0xac, 0x95, 0x72, ++ 0x09, 0xda, 0x29, 0xe3, 0xa6, 0xd8, 0x68, 0x1e, 0x75, 0x07, 0xac, 0xe4, ++ 0x6f, 0xad, 0x5d, 0xd2, 0x33, 0x14, 0xd7, 0x51, 0x5d, 0x45, 0x4f, 0x5e, ++ 0xc3, 0x00, 0x78, 0x45, 0x68, 0x15, 0x4d, 0x7e, 0x41, 0xbd, 0x99, 0x6e, ++ 0xd8, 0x27, 0xe0, 0xba, 0x6d, 0xd5, 0x9f, 0x53, 0x81, 0xa6, 0x65, 0x91, ++ 0xe7, 0x4e, 0x53, 0xd2, 0x7c, 0x4b, 0xb3, 0x13, 0x71, 0x3f, 0xf2, 0xd1, ++ 0xee, 0xdf, 0x20, 0xbd, 0x77, 0x5b, 0x49, 0x3f, 0xc1, 0xff, 0x0e, 0x9a, ++ 0x51, 0x7e, 0xbd, 0x94, 0x49, 0x76, 0x53, 0x5e, 0x5a, 0x60, 0x65, 0x36, ++ 0xea, 0xf5, 0x98, 0xf0, 0xd6, 0x67, 0x33, 0xd1, 0x4e, 0xe1, 0x76, 0x52, ++ 0x6d, 0x97, 0xb9, 0x03, 0xed, 0xc0, 0x99, 0x2d, 0x11, 0xe7, 0x5e, 0xf8, ++ 0xcf, 0x6a, 0xfd, 0x39, 0x18, 0x6b, 0x75, 0x91, 0x7f, 0x83, 0xb5, 0xeb, ++ 0xbf, 0xcf, 0xdf, 0x1c, 0xd5, 0xee, 0x92, 0x73, 0x31, 0xae, 0xef, 0xd7, ++ 0x9b, 0x02, 0xc3, 0xd0, 0xbe, 0xbb, 0xe1, 0x7a, 0x5f, 0x32, 0xca, 0xd5, ++ 0x33, 0x0b, 0x0c, 0x0c, 0xe9, 0x3b, 0x4b, 0xf6, 0xce, 0x45, 0x39, 0x72, ++ 0xc6, 0xaa, 0xb7, 0xbf, 0xcf, 0xd8, 0x39, 0xbd, 0x76, 0x66, 0x6b, 0xf2, ++ 0xdd, 0x9b, 0x87, 0x74, 0xee, 0xcb, 0x5f, 0x42, 0x67, 0x6f, 0x1e, 0xd2, ++ 0x79, 0x96, 0x81, 0x05, 0x22, 0xfb, 0xa9, 0x45, 0x3a, 0x03, 0x7d, 0x17, ++ 0x0a, 0x3a, 0x9f, 0xd9, 0x7b, 0x75, 0x1e, 0xd2, 0xf9, 0xb3, 0xdd, 0x57, ++ 0xe7, 0x21, 0x9d, 0xd7, 0x1b, 0xdb, 0x7c, 0xb8, 0x6e, 0x9e, 0xcd, 0x08, ++ 0xec, 0x42, 0x3c, 0x9e, 0x1c, 0xef, 0x27, 0xfb, 0x09, 0xe4, 0x55, 0xde, ++ 0x77, 0xe1, 0xc7, 0x03, 0x51, 0xfc, 0x78, 0xe0, 0x7f, 0x8f, 0x1f, 0xa9, ++ 0xdd, 0x60, 0xfa, 0xf0, 0xb7, 0x7d, 0x70, 0xe8, 0xf5, 0xa1, 0xdb, 0xa4, ++ 0xa6, 0xa1, 0x3c, 0x9c, 0x69, 0x31, 0x7f, 0xab, 0x5e, 0xc4, 0x9f, 0x01, ++ 0xfd, 0x6b, 0x16, 0x33, 0xf9, 0x25, 0x0e, 0x7c, 0xf5, 0xc5, 0x63, 0xcf, ++ 0xa0, 0x1d, 0xd2, 0x25, 0x93, 0x1d, 0xa2, 0xf5, 0x77, 0x40, 0x09, 0x64, ++ 0xa3, 0x5f, 0xe1, 0xc0, 0x31, 0x8f, 0x37, 0x28, 0x0d, 0xde, 0xff, 0x83, ++ 0xc2, 0x6e, 0xf5, 0x58, 0x58, 0x10, 0xfd, 0x1f, 0x9a, 0xdd, 0xaf, 0xd9, ++ 0x8f, 0xd1, 0xf2, 0xf8, 0xb8, 0x98, 0xcf, 0xd9, 0x6c, 0x5f, 0x0d, 0xed, ++ 0x17, 0x85, 0xbf, 0x76, 0xbe, 0xe8, 0xd3, 0x12, 0xfa, 0x82, 0xdb, 0xa9, ++ 0xdb, 0x25, 0xf2, 0xc7, 0x5a, 0xd4, 0x4e, 0x1f, 0xda, 0xbd, 0x75, 0xaf, ++ 0xcc, 0x70, 0xa0, 0xbf, 0xf6, 0x74, 0x88, 0xfb, 0x67, 0xeb, 0xf6, 0x8e, ++ 0x22, 0xff, 0xed, 0x82, 0xd0, 0xab, 0xe1, 0x54, 0xb4, 0x0b, 0xbb, 0x24, ++ 0x07, 0xee, 0x1f, 0x16, 0x6c, 0x3f, 0x11, 0x87, 0xe7, 0xdd, 0xb0, 0x1f, ++ 0x3d, 0x93, 0x4d, 0x78, 0xe3, 0xfb, 0xd1, 0xf1, 0x62, 0x3f, 0x7a, 0x3a, ++ 0xf4, 0x51, 0x1c, 0x9e, 0x8b, 0xc3, 0xf8, 0x37, 0xe3, 0x3e, 0x22, 0xd6, ++ 0xdd, 0x6b, 0x42, 0xfe, 0xad, 0x83, 0x7d, 0x1a, 0x54, 0x61, 0x75, 0x4a, ++ 0xef, 0x11, 0xec, 0xaf, 0xce, 0xcd, 0xbc, 0x41, 0x14, 0x15, 0xfb, 0xf5, ++ 0xfb, 0x36, 0xed, 0xfc, 0x72, 0x93, 0xdf, 0x44, 0xf2, 0x6e, 0x53, 0x97, ++ 0x14, 0xc2, 0x7d, 0x5a, 0x92, 0x29, 0x90, 0x99, 0x86, 0xfa, 0x89, 0xa5, ++ 0x39, 0x4e, 0xc5, 0xf6, 0xaf, 0x97, 0xff, 0xce, 0xf6, 0xa5, 0xe0, 0xb9, ++ 0x66, 0xff, 0xb9, 0xb1, 0xef, 0x6b, 0x84, 0xcb, 0x8d, 0xe7, 0x4d, 0xd0, ++ 0xbe, 0x67, 0x63, 0x3c, 0xf1, 0x61, 0x8f, 0x91, 0xf9, 0xc8, 0x0e, 0xd8, ++ 0x68, 0x17, 0x72, 0x49, 0x21, 0x39, 0xf5, 0xe7, 0xcd, 0x4e, 0xda, 0xf7, ++ 0xd0, 0x0f, 0xd4, 0xff, 0x73, 0x28, 0x93, 0xf2, 0x9a, 0xbe, 0x9e, 0xab, ++ 0xb0, 0xb0, 0x02, 0x78, 0x9f, 0x3b, 0xd5, 0xf7, 0x1e, 0xd2, 0x0d, 0xe5, ++ 0x77, 0x38, 0x4a, 0x7e, 0x47, 0xe6, 0xfb, 0xce, 0xa3, 0x59, 0x37, 0xd7, ++ 0x2f, 0x20, 0xcf, 0xc3, 0x03, 0x9d, 0x8f, 0x8b, 0x73, 0x6a, 0x3c, 0xdf, ++ 0x8d, 0x6c, 0x5f, 0xc7, 0x7a, 0xa9, 0x1d, 0x9e, 0xf3, 0xea, 0xfa, 0xd5, ++ 0xf6, 0x01, 0xac, 0x61, 0x94, 0x0a, 0x70, 0xdf, 0x77, 0xb7, 0xcd, 0x8b, ++ 0xf6, 0x4b, 0x3d, 0xf0, 0x75, 0x63, 0x49, 0x3f, 0x1f, 0x2e, 0x14, 0x53, ++ 0xd1, 0xf8, 0xb0, 0x4e, 0xf8, 0x79, 0xeb, 0xe7, 0x7f, 0x48, 0xfb, 0x81, ++ 0xfa, 0xfd, 0x92, 0x03, 0xfd, 0xbb, 0x0b, 0xbd, 0x9c, 0x0f, 0x17, 0xc2, ++ 0x3e, 0xc9, 0x3c, 0xe2, 0xd2, 0x75, 0xcb, 0x3a, 0x81, 0x0f, 0x23, 0xe0, ++ 0x1e, 0x6c, 0x1d, 0x5f, 0x9d, 0xa3, 0x5f, 0xc7, 0x7d, 0xf9, 0x7f, 0x92, ++ 0x3f, 0xb3, 0x22, 0x47, 0x6f, 0xcf, 0x6a, 0xf3, 0xd7, 0xfc, 0xe2, 0x7d, ++ 0xf3, 0xec, 0x92, 0xf8, 0xfa, 0x8a, 0x9a, 0x57, 0xf4, 0xfe, 0x32, 0xda, ++ 0x9f, 0xad, 0xed, 0x0f, 0xaf, 0x54, 0xae, 0xdd, 0xd9, 0x07, 0x0f, 0xc7, ++ 0x47, 0x5f, 0xfe, 0x9f, 0x2c, 0xd7, 0xe6, 0x44, 0xe1, 0x65, 0xb0, 0xf3, ++ 0x82, 0xef, 0x2c, 0xd7, 0xa2, 0xcf, 0x0d, 0x72, 0xb8, 0x1f, 0x1c, 0xcf, ++ 0x0d, 0xf0, 0x5c, 0xf7, 0x7f, 0x7a, 0x6e, 0xf0, 0x89, 0xda, 0x96, 0x64, ++ 0x20, 0x3d, 0xe8, 0xd3, 0x9d, 0xa7, 0xa2, 0x9d, 0x8e, 0xe3, 0xb4, 0x6e, ++ 0x91, 0xc9, 0x3e, 0x98, 0x20, 0xf3, 0x73, 0xe8, 0x5a, 0xbb, 0x99, 0xfc, ++ 0xb4, 0xd1, 0xe7, 0xad, 0xf5, 0xea, 0x04, 0x71, 0xbe, 0xd8, 0xfd, 0x87, ++ 0x6b, 0x50, 0x7f, 0xee, 0x31, 0x32, 0xd4, 0xeb, 0xf3, 0x6d, 0xf3, 0xe8, ++ 0x3c, 0xb3, 0x5e, 0xde, 0x65, 0x72, 0xa8, 0x03, 0x9c, 0x33, 0x2a, 0x07, ++ 0xc9, 0x7e, 0xff, 0xae, 0xe7, 0xef, 0x8f, 0xe6, 0xf4, 0x9d, 0xbf, 0x67, ++ 0xe2, 0xf9, 0x7b, 0x59, 0x85, 0x5e, 0x3e, 0xbf, 0x6a, 0xfb, 0x22, 0x21, ++ 0x10, 0x41, 0xe7, 0x8a, 0x22, 0x30, 0xfc, 0x07, 0xe0, 0x67, 0x8b, 0x12, ++ 0x64, 0xae, 0x88, 0xef, 0x4f, 0xe6, 0x70, 0x7b, 0xf8, 0x55, 0x11, 0x27, ++ 0xe3, 0x31, 0xb1, 0x56, 0x8c, 0xbf, 0x78, 0xdc, 0x1e, 0xeb, 0xc3, 0x7d, ++ 0x87, 0xc7, 0xc0, 0xe3, 0x78, 0x9a, 0xb3, 0xfc, 0x5b, 0x50, 0x0e, 0x5a, ++ 0x54, 0x8e, 0xc7, 0xa7, 0x5e, 0xba, 0x83, 0x19, 0x60, 0x7e, 0x4f, 0x19, ++ 0x3b, 0x49, 0x5e, 0x04, 0x6b, 0x6d, 0x5e, 0x94, 0x7b, 0x9a, 0x9f, 0x45, ++ 0xeb, 0xdf, 0x2e, 0xfc, 0x05, 0x57, 0xca, 0xdf, 0x7b, 0xa3, 0xd6, 0xfb, ++ 0xde, 0x7f, 0xf2, 0x7a, 0xff, 0xb5, 0x36, 0xde, 0x77, 0x3d, 0x07, 0xdb, ++ 0x00, 0xb8, 0xd1, 0xad, 0x03, 0x46, 0xe7, 0x5d, 0x6f, 0xe0, 0xf9, 0x4d, ++ 0xe6, 0xa5, 0xfc, 0x3a, 0x58, 0x3f, 0x83, 0xf1, 0xed, 0xdb, 0x39, 0xfe, ++ 0x37, 0x73, 0x68, 0xbd, 0xf9, 0x46, 0xd0, 0xb9, 0xfe, 0x15, 0xca, 0x95, ++ 0xd8, 0xd2, 0xde, 0x8f, 0xd0, 0x9f, 0xc3, 0xf6, 0x98, 0x55, 0xdc, 0x57, ++ 0xa0, 0x5f, 0x83, 0xf4, 0xe1, 0xea, 0x64, 0xae, 0xa7, 0x14, 0x6f, 0x19, ++ 0xe2, 0x19, 0xec, 0xb9, 0x32, 0x8c, 0x83, 0x3a, 0x8e, 0xff, 0xbd, 0x66, ++ 0x70, 0xfb, 0xef, 0x74, 0xdf, 0xba, 0xe7, 0xf6, 0xdf, 0xe9, 0x41, 0xe5, ++ 0xcf, 0xdf, 0x67, 0xff, 0x35, 0x65, 0xf8, 0x3f, 0xc5, 0x79, 0x9e, 0x2c, ++ 0xf7, 0xe5, 0xa1, 0x7e, 0x5c, 0x61, 0x07, 0xf8, 0x71, 0x5f, 0xf7, 0x73, ++ 0x1e, 0x3f, 0xb3, 0xd9, 0xca, 0xf9, 0x73, 0xb3, 0xc4, 0xf9, 0x92, 0x35, ++ 0x26, 0x68, 0xfe, 0x11, 0x9a, 0x57, 0xf0, 0x79, 0x7e, 0xfe, 0x1d, 0xcd, ++ 0x57, 0x2c, 0x57, 0xcf, 0x57, 0x7d, 0xf9, 0x7f, 0xb2, 0xdc, 0xb4, 0xf5, ++ 0xc1, 0xf1, 0xbf, 0x2c, 0x37, 0xe7, 0xff, 0x35, 0x0e, 0xfd, 0x9c, 0x83, ++ 0xf7, 0x13, 0x24, 0xba, 0x95, 0x55, 0x74, 0x13, 0xde, 0x7a, 0x5f, 0x91, ++ 0xd8, 0xb6, 0x08, 0xff, 0x73, 0x7d, 0x37, 0x8f, 0x43, 0x4b, 0x17, 0xf0, ++ 0x6a, 0xdf, 0xff, 0x2a, 0xec, 0xbf, 0xb9, 0xb9, 0xbe, 0xa1, 0x18, 0xcf, ++ 0xf5, 0xd9, 0x7b, 0x16, 0x0b, 0x8b, 0x07, 0x53, 0x07, 0x79, 0x0c, 0xed, ++ 0x2e, 0xbf, 0x8d, 0xfc, 0xff, 0x75, 0x9d, 0x3c, 0x4e, 0xa4, 0x6e, 0x09, ++ 0xa3, 0xf3, 0xde, 0x3a, 0xf4, 0x6f, 0x16, 0xa1, 0xdf, 0xaf, 0x86, 0xa1, ++ 0x7d, 0xb7, 0x4f, 0x0d, 0x14, 0x60, 0xfb, 0x15, 0xef, 0xdb, 0x82, 0x72, ++ 0x3c, 0xfa, 0xc5, 0x27, 0x33, 0xb2, 0xeb, 0xde, 0xe3, 0xf9, 0x45, 0x6a, ++ 0xa0, 0x88, 0xe2, 0xc5, 0x96, 0xf4, 0xe8, 0xce, 0x19, 0xca, 0xbe, 0xf9, ++ 0x62, 0x39, 0xfa, 0x2d, 0x00, 0x5e, 0xf2, 0x03, 0xb8, 0xd1, 0x2f, 0x13, ++ 0x41, 0xa7, 0x69, 0xb9, 0xfc, 0x7c, 0x40, 0x4b, 0x6f, 0x8b, 0x82, 0x1f, ++ 0xfd, 0xf4, 0xc4, 0xff, 0x9d, 0x72, 0x08, 0xed, 0xc1, 0x58, 0xb5, 0x9b, ++ 0xfc, 0xfe, 0x75, 0x7b, 0xb8, 0x91, 0x56, 0x26, 0xfb, 0xc8, 0x3f, 0xcf, ++ 0xee, 0x73, 0x31, 0xe4, 0xa3, 0xba, 0x3d, 0xe5, 0xa3, 0x5e, 0xa3, 0xfa, ++ 0xd6, 0x51, 0x68, 0xcf, 0x96, 0x7d, 0x50, 0xed, 0x40, 0x3f, 0xc4, 0x67, ++ 0xd7, 0xb9, 0x29, 0xbe, 0x60, 0xa8, 0xdc, 0xb3, 0x00, 0xed, 0xa9, 0xa3, ++ 0x59, 0x81, 0x71, 0x08, 0xaf, 0xbd, 0x34, 0x34, 0x11, 0xed, 0xd1, 0x0c, ++ 0xb0, 0x47, 0xd1, 0xbe, 0xfd, 0x6c, 0xf7, 0xc4, 0x51, 0x08, 0xb7, 0x26, ++ 0xff, 0xd6, 0xa3, 0x7f, 0x1b, 0xfa, 0x5d, 0x6f, 0xd7, 0xfb, 0xaf, 0x99, ++ 0xc5, 0x97, 0xf9, 0x30, 0xfa, 0xb7, 0xb7, 0x0d, 0xa1, 0xfd, 0xe1, 0xee, ++ 0x94, 0xc0, 0xcd, 0xb9, 0xb8, 0x4f, 0xb3, 0x72, 0x78, 0x83, 0x6b, 0xac, ++ 0x7c, 0xbd, 0x0a, 0xbf, 0x76, 0xf4, 0xfa, 0xd7, 0xd6, 0xfd, 0x10, 0xd9, ++ 0x40, 0xe3, 0x0c, 0xf9, 0xbe, 0x85, 0xce, 0xa1, 0x35, 0xb9, 0xb0, 0xde, ++ 0xc8, 0x02, 0x96, 0xec, 0x7e, 0x79, 0x72, 0x95, 0x88, 0x97, 0x03, 0x7c, ++ 0xf0, 0x78, 0xbd, 0xae, 0x1a, 0x1e, 0xe7, 0x21, 0xf2, 0x36, 0xb7, 0x3e, ++ 0x6e, 0xf1, 0x6c, 0xf6, 0xf8, 0xab, 0x70, 0x7e, 0x57, 0xe5, 0xf2, 0xb8, ++ 0x94, 0x39, 0x96, 0x5e, 0x09, 0xfd, 0xec, 0x73, 0xc4, 0xf9, 0xfb, 0x8d, ++ 0x22, 0x8e, 0x42, 0x8b, 0xa3, 0x3a, 0xe3, 0xf0, 0xcf, 0xc6, 0xfa, 0x6c, ++ 0x49, 0x55, 0xff, 0xb9, 0x7b, 0x16, 0xb6, 0x77, 0x70, 0xfe, 0x17, 0xf1, ++ 0x31, 0xb1, 0x17, 0xb9, 0x9d, 0x9c, 0xe5, 0x30, 0x11, 0xdf, 0xd8, 0x5b, ++ 0x19, 0x3f, 0x37, 0x02, 0xbe, 0x41, 0xfa, 0x8c, 0xed, 0xed, 0x1e, 0x17, ++ 0x0f, 0xf3, 0xc9, 0x69, 0x0f, 0x8f, 0x45, 0x7c, 0x1e, 0xb8, 0x68, 0x20, ++ 0x7c, 0x28, 0x35, 0x6f, 0xd0, 0x79, 0x49, 0x3c, 0x92, 0x0d, 0xfa, 0xc9, ++ 0x5e, 0xdd, 0xb3, 0x32, 0x1f, 0xfd, 0x25, 0x8e, 0x77, 0xaf, 0x43, 0xba, ++ 0xa8, 0x6d, 0x8e, 0x0a, 0x44, 0xdd, 0x3e, 0xd5, 0xff, 0x00, 0xc1, 0xa1, ++ 0x34, 0x14, 0xe0, 0xfe, 0xb1, 0xe2, 0xf7, 0x46, 0x1e, 0x0f, 0xf8, 0x4a, ++ 0x2c, 0xe9, 0xf9, 0xf6, 0xa1, 0x0b, 0x29, 0x1e, 0xf0, 0xec, 0xfb, 0xc0, ++ 0xaf, 0x99, 0x97, 0xea, 0x03, 0x2d, 0x0d, 0xb2, 0x65, 0x14, 0xff, 0x97, ++ 0xb5, 0xff, 0x1d, 0xf2, 0xdb, 0xdb, 0xf7, 0x48, 0x03, 0xc6, 0x75, 0x3e, ++ 0x9e, 0x6b, 0xe3, 0xe7, 0x49, 0xc1, 0x6e, 0x8a, 0x33, 0x63, 0x63, 0xdd, ++ 0x84, 0x0f, 0xe5, 0x95, 0x0f, 0x82, 0x68, 0x5f, 0x28, 0x2b, 0x15, 0xf2, ++ 0x54, 0xb4, 0x18, 0x7d, 0x06, 0x2b, 0xd2, 0x75, 0x29, 0x23, 0x3f, 0x7b, ++ 0x6e, 0xbb, 0xc3, 0x80, 0x74, 0xc9, 0x10, 0x71, 0x25, 0xe7, 0x0e, 0xfc, ++ 0xf7, 0x88, 0x00, 0xed, 0x47, 0x34, 0x3f, 0x7d, 0x88, 0x52, 0xc5, 0xd8, ++ 0xb3, 0x1c, 0xf7, 0x57, 0xca, 0xd2, 0x9e, 0xeb, 0x61, 0x05, 0xb3, 0xda, ++ 0x3d, 0x4e, 0x43, 0x1d, 0xfa, 0x35, 0x8d, 0xbd, 0x75, 0xe4, 0x17, 0x79, ++ 0x25, 0x96, 0xfc, 0x9f, 0x19, 0xfb, 0xb3, 0x97, 0x7d, 0x0f, 0xf2, 0x19, ++ 0xad, 0x0e, 0x26, 0xa1, 0xfc, 0xf9, 0xd5, 0x7d, 0x19, 0xc8, 0xd7, 0x41, ++ 0x98, 0x67, 0xee, 0x00, 0xf3, 0x6c, 0xcc, 0xe5, 0x71, 0x3b, 0xca, 0x2b, ++ 0xb1, 0x06, 0xd4, 0x5b, 0xca, 0x1a, 0x46, 0x71, 0x88, 0x8a, 0x33, 0xa9, ++ 0x82, 0xe0, 0x5e, 0x07, 0x79, 0xe8, 0x67, 0x91, 0xe0, 0x1b, 0xed, 0xfc, ++ 0x11, 0xc0, 0xf5, 0xa0, 0x3e, 0x9a, 0x9b, 0x1b, 0xd8, 0x8e, 0x78, 0x8e, ++ 0x15, 0x72, 0x80, 0x35, 0xc6, 0x90, 0xbf, 0xd0, 0xae, 0x70, 0xbf, 0x86, ++ 0xbd, 0xf1, 0xfd, 0xe7, 0x97, 0x42, 0x7e, 0xab, 0xf0, 0xb7, 0x1e, 0x3a, ++ 0x50, 0x38, 0x99, 0xfc, 0x73, 0x2b, 0x15, 0x09, 0xe9, 0x70, 0xc1, 0x39, ++ 0x23, 0xc3, 0x01, 0xdf, 0x7f, 0x99, 0xcb, 0xed, 0x11, 0xbb, 0xd2, 0xcd, ++ 0x1c, 0xb6, 0x48, 0xfc, 0x1f, 0xa2, 0xb8, 0xcb, 0xac, 0x57, 0x78, 0x5c, ++ 0x9a, 0x62, 0xe4, 0x7c, 0xa2, 0xac, 0x74, 0x77, 0xa0, 0xff, 0xef, 0xcb, ++ 0xb4, 0x00, 0xc5, 0x97, 0x5e, 0xd7, 0x12, 0x96, 0xe9, 0xfc, 0xca, 0x71, ++ 0x72, 0x6d, 0x95, 0x1a, 0xb1, 0x7f, 0xd9, 0xc0, 0xf5, 0x48, 0xdd, 0x4e, ++ 0xbe, 0x6f, 0x8e, 0xde, 0xaf, 0x5c, 0x4e, 0x7f, 0x1c, 0xcd, 0xd5, 0xdb, ++ 0xdd, 0x7d, 0xf9, 0x7f, 0x92, 0x5d, 0xf2, 0x4e, 0xdf, 0xf8, 0x7f, 0xe7, ++ 0x3e, 0x84, 0xe9, 0xf7, 0x6f, 0xd1, 0xf6, 0x49, 0xf4, 0x7e, 0xed, 0x12, ++ 0xfb, 0x3a, 0xaa, 0xbf, 0xc1, 0xec, 0x14, 0x2d, 0x8e, 0xa3, 0xa2, 0x7f, ++ 0x1c, 0xe2, 0x87, 0x57, 0xed, 0x9a, 0x1d, 0x14, 0xd4, 0xc5, 0xb9, 0x54, ++ 0xd8, 0xf8, 0xb8, 0xcc, 0xa2, 0xef, 0xff, 0xf9, 0x4c, 0x2e, 0x27, 0xb4, ++ 0xb8, 0x97, 0xa4, 0x66, 0x75, 0x29, 0xc6, 0x97, 0xf7, 0xfe, 0x94, 0x91, ++ 0x3f, 0x4d, 0x8b, 0xcb, 0xd1, 0xe2, 0x70, 0x82, 0x15, 0x7c, 0x9f, 0x10, ++ 0x34, 0x80, 0xdc, 0xcb, 0xc4, 0xf3, 0x9f, 0x36, 0x8a, 0xbf, 0x49, 0x65, ++ 0x61, 0x49, 0x22, 0x7b, 0xbf, 0x87, 0x61, 0xfb, 0x21, 0x18, 0x87, 0x03, ++ 0xed, 0x7b, 0x72, 0xb3, 0xa8, 0xff, 0x2d, 0xcc, 0xdb, 0x2a, 0x93, 0x5c, ++ 0x54, 0x25, 0x84, 0xdf, 0x8a, 0xf1, 0x1b, 0x09, 0x08, 0x77, 0x68, 0xe3, ++ 0x5c, 0x1c, 0xef, 0x36, 0x1b, 0x8d, 0x67, 0xc5, 0xf8, 0x8d, 0x04, 0xda, ++ 0x27, 0xd0, 0x3a, 0x4e, 0xf1, 0xf3, 0xb8, 0xcd, 0x71, 0xf3, 0x79, 0xbc, ++ 0x67, 0x0a, 0xe8, 0x5f, 0xcc, 0xa7, 0xe4, 0x70, 0xbe, 0xb4, 0x4e, 0x33, ++ 0x51, 0x1c, 0xa7, 0x16, 0x97, 0xa1, 0xc5, 0x6f, 0x68, 0x78, 0xa9, 0x10, ++ 0xf8, 0x4e, 0xc9, 0x9f, 0x9b, 0x89, 0xfb, 0x01, 0x2d, 0xce, 0x63, 0x7d, ++ 0x4c, 0xe8, 0xe7, 0x56, 0x19, 0xe3, 0x3b, 0x84, 0xdc, 0x5f, 0x60, 0x20, ++ 0xb9, 0xaf, 0xc5, 0xcf, 0xb5, 0xe7, 0xaa, 0x21, 0xe4, 0xf7, 0x73, 0x18, ++ 0xe7, 0x69, 0xbb, 0xf2, 0x78, 0x8e, 0x68, 0xfc, 0x6a, 0x71, 0x1d, 0x37, ++ 0xa4, 0x07, 0x92, 0xf3, 0x46, 0x53, 0x5c, 0x07, 0xe9, 0x51, 0x2d, 0x1e, ++ 0x43, 0xe3, 0x97, 0x08, 0x3a, 0x06, 0xad, 0x30, 0xfe, 0xa6, 0x57, 0xb8, ++ 0xfd, 0x5e, 0x31, 0xdf, 0x44, 0xf0, 0x9f, 0x5b, 0x30, 0x89, 0xfc, 0x87, ++ 0xe7, 0x16, 0x18, 0x18, 0xae, 0xa3, 0x8a, 0x2e, 0x33, 0xe7, 0xbf, 0xa8, ++ 0xf1, 0x36, 0x4d, 0x33, 0xb1, 0x30, 0xf6, 0xab, 0x84, 0xac, 0x28, 0x3f, ++ 0x35, 0x3e, 0xb8, 0x9c, 0xfd, 0x0a, 0x74, 0x2d, 0x40, 0xff, 0xec, 0xa1, ++ 0xa6, 0x9d, 0xd9, 0x27, 0x61, 0xcd, 0x1f, 0x6e, 0xea, 0xa4, 0xf4, 0x9c, ++ 0x55, 0xea, 0x94, 0x47, 0x62, 0xda, 0x3b, 0x1d, 0x25, 0xd5, 0x88, 0x67, ++ 0x87, 0x4e, 0x51, 0xae, 0xc1, 0x38, 0x95, 0xde, 0xa1, 0x12, 0xb0, 0x4e, ++ 0xc9, 0xce, 0x9c, 0xa9, 0x94, 0x4f, 0xec, 0x3d, 0x8e, 0xf9, 0x49, 0xf9, ++ 0x37, 0x4f, 0x55, 0x40, 0x4f, 0x9c, 0xcb, 0xed, 0xdd, 0x2a, 0x61, 0x9c, ++ 0x49, 0xfe, 0x89, 0x29, 0x94, 0x47, 0x9e, 0x4c, 0x61, 0x6c, 0xcc, 0x33, ++ 0xbf, 0x9f, 0x12, 0xa4, 0x79, 0x73, 0x7f, 0xd3, 0x38, 0xe1, 0x6f, 0x32, ++ 0x3b, 0x03, 0xd7, 0xe5, 0x25, 0xe2, 0x7d, 0x80, 0x9e, 0xe5, 0xdd, 0xe4, ++ 0xd7, 0xe1, 0x71, 0xfd, 0x18, 0xf7, 0x87, 0xf4, 0xf0, 0xd8, 0x4c, 0x64, ++ 0xdf, 0x78, 0x44, 0xbc, 0x25, 0xab, 0x14, 0xf1, 0x97, 0x78, 0xf2, 0x02, ++ 0xf9, 0xe6, 0xe4, 0x51, 0x74, 0x5e, 0x6d, 0x63, 0xea, 0x9e, 0x6e, 0x2c, ++ 0x4f, 0x33, 0x73, 0x7d, 0xcf, 0x38, 0x3f, 0x37, 0xe7, 0x72, 0x7f, 0x30, ++ 0xa9, 0x48, 0x94, 0x9d, 0x69, 0x9a, 0xff, 0xa8, 0x27, 0x88, 0xf2, 0xaa, ++ 0x39, 0xd3, 0x49, 0xed, 0xfb, 0xe4, 0xea, 0x1e, 0x73, 0x88, 0xfb, 0xb1, ++ 0xf8, 0xf8, 0x6f, 0xed, 0x2d, 0xa6, 0x73, 0x26, 0x2d, 0x8e, 0x94, 0x31, ++ 0x47, 0xfa, 0xd4, 0x62, 0x8a, 0x37, 0xd1, 0xe5, 0x1f, 0xb7, 0xf2, 0x73, ++ 0x4f, 0xa6, 0x38, 0xd2, 0xd1, 0x7e, 0x68, 0x36, 0x0a, 0x3b, 0x55, 0xe4, ++ 0x63, 0xd2, 0x02, 0x77, 0xe5, 0x45, 0xd8, 0x49, 0x6f, 0x8d, 0xff, 0x51, ++ 0x11, 0xae, 0x87, 0x33, 0xfb, 0x7e, 0x92, 0x83, 0x72, 0xea, 0x46, 0x13, ++ 0xd8, 0xf1, 0x03, 0xc8, 0xa5, 0xd4, 0x02, 0x2e, 0x97, 0xce, 0x19, 0x6d, ++ 0xad, 0x12, 0xd8, 0x6d, 0x6f, 0xa4, 0x06, 0x66, 0x21, 0xbe, 0x8e, 0xc5, ++ 0x4e, 0x9f, 0xe0, 0x84, 0x79, 0x4d, 0x4b, 0x28, 0x37, 0x39, 0x11, 0xde, ++ 0xe0, 0xcf, 0x65, 0x94, 0x93, 0x89, 0x82, 0xde, 0xce, 0xa9, 0x1c, 0x3e, ++ 0x67, 0xa5, 0x5f, 0x9a, 0x03, 0xfd, 0x36, 0x5b, 0x61, 0x3d, 0x43, 0xfb, ++ 0xc4, 0x80, 0xe2, 0x23, 0x7b, 0x3d, 0x30, 0x55, 0xba, 0x0d, 0xe0, 0x6e, ++ 0x96, 0x84, 0xfd, 0xce, 0xd4, 0x78, 0xb2, 0xdb, 0x0b, 0xd4, 0x78, 0x3c, ++ 0xd7, 0x5b, 0xd8, 0xf8, 0x0e, 0xc5, 0x55, 0xcb, 0x42, 0x0e, 0xc8, 0x42, ++ 0x0e, 0xbc, 0xdd, 0xd4, 0x93, 0xa3, 0xe4, 0x82, 0xca, 0xed, 0x5c, 0x23, ++ 0xa3, 0xbd, 0xfd, 0x8e, 0x38, 0x5f, 0x7e, 0x27, 0x93, 0xdd, 0x53, 0x33, ++ 0x80, 0x3f, 0x73, 0x7d, 0x1e, 0xb7, 0x0f, 0x27, 0xcb, 0x6a, 0x31, 0xf2, ++ 0x91, 0xfb, 0xe1, 0xb1, 0xef, 0x54, 0x03, 0x5f, 0xc8, 0x26, 0x6f, 0x88, ++ 0xe8, 0x97, 0x6e, 0x57, 0x91, 0xdf, 0x0f, 0xda, 0xcb, 0x3c, 0x3d, 0xd0, ++ 0x8f, 0x94, 0xf1, 0xd3, 0x52, 0x8c, 0x4b, 0x6e, 0x4e, 0xff, 0x69, 0x29, ++ 0xc6, 0x95, 0xc8, 0x2e, 0xaf, 0xc7, 0x1f, 0x91, 0x5f, 0x9f, 0xc7, 0xf9, ++ 0xb8, 0x12, 0xeb, 0x21, 0xde, 0x62, 0x1b, 0x4a, 0x51, 0x8f, 0xfd, 0xc3, ++ 0xfa, 0x8b, 0x87, 0xfe, 0x8a, 0xfe, 0xfe, 0xfe, 0xfa, 0xfa, 0x31, 0x73, ++ 0xb8, 0x16, 0x5a, 0x7a, 0x87, 0x2a, 0xb0, 0x3e, 0xbd, 0x9e, 0xc0, 0x26, ++ 0xa4, 0xdb, 0x85, 0x19, 0x27, 0xe8, 0xbc, 0xf5, 0x87, 0x29, 0x6f, 0x1d, ++ 0xc7, 0xf8, 0x88, 0xb7, 0x8c, 0x6d, 0xe3, 0xe2, 0x50, 0x0e, 0x65, 0x4a, ++ 0x82, 0x6f, 0xb9, 0xbd, 0x76, 0x24, 0x5f, 0xf3, 0x6b, 0xf2, 0xb8, 0xf6, ++ 0x23, 0x85, 0xdc, 0xaf, 0x09, 0x72, 0x88, 0xc7, 0x4f, 0x16, 0xf3, 0x7b, ++ 0x34, 0xd5, 0x53, 0x19, 0xad, 0xe7, 0x6a, 0x11, 0x57, 0x31, 0xc1, 0xc1, ++ 0xef, 0x25, 0x4d, 0x28, 0xcd, 0xf4, 0x36, 0xc3, 0xd4, 0x6e, 0x61, 0xbd, ++ 0x0a, 0xca, 0xe9, 0x09, 0xc7, 0xfc, 0x71, 0x48, 0x3f, 0x36, 0x35, 0x50, ++ 0xea, 0x2f, 0x1e, 0xdc, 0x0e, 0x63, 0x1e, 0xa3, 0x1a, 0x29, 0x57, 0x26, ++ 0xaa, 0x11, 0x79, 0xf8, 0x7b, 0x53, 0x81, 0x3e, 0x7f, 0xb3, 0x57, 0x9f, ++ 0xbf, 0x75, 0xcc, 0xd7, 0xf9, 0x91, 0xf9, 0x35, 0x1e, 0xdf, 0x8b, 0x38, ++ 0xef, 0x97, 0x25, 0x1e, 0xa7, 0x19, 0xbc, 0x86, 0x39, 0x68, 0x9e, 0x6e, ++ 0x29, 0x88, 0xf6, 0x52, 0xe1, 0x8b, 0x29, 0x1d, 0xc2, 0x7f, 0x4b, 0xf1, ++ 0x84, 0xff, 0x2a, 0xf6, 0x73, 0x2f, 0x8e, 0x61, 0x54, 0x9e, 0xb4, 0xd3, ++ 0xb2, 0x0d, 0xef, 0x17, 0x68, 0x7e, 0x70, 0x59, 0x94, 0x17, 0x7a, 0x98, ++ 0x25, 0xc3, 0x45, 0xf8, 0x20, 0x3d, 0xdb, 0x2b, 0x89, 0xb8, 0x44, 0x37, ++ 0x9d, 0xf5, 0xb0, 0x7d, 0xf7, 0x3b, 0x38, 0xfe, 0xa0, 0xae, 0x09, 0xfa, ++ 0xd9, 0x37, 0x43, 0xa5, 0x75, 0x9c, 0x64, 0x33, 0xb0, 0xeb, 0x71, 0xad, ++ 0x97, 0x5a, 0xc8, 0x7e, 0xd2, 0xd6, 0x45, 0xb3, 0x15, 0xf8, 0x1b, 0xf0, ++ 0x58, 0x96, 0x6a, 0x89, 0x41, 0x7e, 0x6f, 0x36, 0x7a, 0x37, 0x60, 0x5f, ++ 0x72, 0x8c, 0x59, 0x45, 0xbd, 0x5a, 0x1e, 0x67, 0xa1, 0xbe, 0xe5, 0x9f, ++ 0x29, 0xa4, 0x97, 0x96, 0x5a, 0xcd, 0x14, 0xda, 0x7a, 0xe8, 0xd1, 0x18, ++ 0xca, 0x97, 0x29, 0xcc, 0x8f, 0xf1, 0x18, 0x00, 0xe2, 0x54, 0x4c, 0xdf, ++ 0x32, 0x7a, 0x43, 0x0d, 0x38, 0x5f, 0xa8, 0x87, 0xf3, 0x6d, 0x76, 0x32, ++ 0x92, 0x57, 0x72, 0x99, 0x89, 0xf4, 0x34, 0xf4, 0x4b, 0x74, 0x3d, 0xb4, ++ 0xc6, 0x10, 0x62, 0x34, 0xff, 0x72, 0x85, 0xe2, 0x2d, 0x05, 0xcc, 0xda, ++ 0xba, 0x83, 0x91, 0xe8, 0xfb, 0x13, 0x62, 0x5d, 0xcb, 0x06, 0x16, 0x26, ++ 0x39, 0x96, 0x62, 0x21, 0x39, 0x76, 0x18, 0xfa, 0xc7, 0x7e, 0x0f, 0xbd, ++ 0x2e, 0x77, 0x90, 0x1f, 0xad, 0x40, 0xbd, 0x1b, 0xcb, 0xcf, 0x5b, 0xf2, ++ 0xe9, 0xfe, 0x4d, 0x7d, 0xdf, 0xbd, 0x22, 0xc5, 0x80, 0xc0, 0x15, 0x08, ++ 0x3b, 0xca, 0xd9, 0xc5, 0xef, 0x7f, 0x69, 0xeb, 0x59, 0x93, 0x2f, 0xd1, ++ 0xeb, 0x19, 0xa4, 0x60, 0x8e, 0x3b, 0x89, 0x71, 0x10, 0x55, 0xfc, 0x07, ++ 0xa6, 0x91, 0x84, 0x7a, 0x9f, 0x91, 0x3d, 0xaf, 0x9d, 0x0f, 0xa6, 0x5b, ++ 0xb4, 0x72, 0xc5, 0x87, 0xe3, 0x24, 0xf7, 0xd5, 0xe7, 0xf7, 0xaf, 0x92, ++ 0x44, 0x3e, 0x35, 0x3f, 0x93, 0xd6, 0x1b, 0x54, 0x09, 0x1b, 0x4a, 0xd0, ++ 0xfe, 0xf8, 0xcd, 0x5f, 0x90, 0x6f, 0x35, 0xf9, 0xb0, 0x75, 0xc5, 0xcf, ++ 0x48, 0x3e, 0x5c, 0x8a, 0xff, 0x82, 0x07, 0x29, 0x3f, 0xc9, 0xee, 0xe0, ++ 0xf8, 0xcf, 0x4f, 0xc3, 0x75, 0x28, 0xc7, 0xe4, 0xa7, 0xa1, 0xbe, 0x6b, ++ 0x76, 0x7a, 0x55, 0x7f, 0x44, 0xbe, 0x00, 0x96, 0xd1, 0x34, 0x17, 0xe2, ++ 0x07, 0xea, 0x41, 0x7e, 0x4a, 0xd5, 0x89, 0x1c, 0x25, 0xc2, 0xff, 0x97, ++ 0x9a, 0xaf, 0x92, 0xb0, 0x84, 0x7a, 0xbe, 0x04, 0x80, 0xe3, 0x90, 0x55, ++ 0x4d, 0xc3, 0xf5, 0x3a, 0xc0, 0xb8, 0xb5, 0x7c, 0xdc, 0xd8, 0x7f, 0xec, ++ 0xb8, 0x1e, 0x18, 0x17, 0xea, 0x1d, 0xb2, 0xc3, 0xb8, 0x50, 0x6f, 0xbb, ++ 0xd5, 0x1c, 0x36, 0xc4, 0x0d, 0x34, 0xfe, 0x18, 0x15, 0xc7, 0xbb, 0xdc, ++ 0xb8, 0x80, 0x4e, 0x42, 0xea, 0x24, 0x81, 0x67, 0xe0, 0x8b, 0x20, 0xfa, ++ 0xa5, 0x0e, 0xd9, 0x0d, 0xc4, 0x9f, 0x93, 0x44, 0x7c, 0xee, 0xa1, 0x44, ++ 0x3e, 0x1e, 0x2b, 0xd0, 0xc7, 0xcf, 0xe4, 0xc4, 0xc0, 0xf8, 0xe4, 0x6f, ++ 0xd5, 0xc7, 0xcb, 0xdc, 0x28, 0x6d, 0x6e, 0x41, 0xbd, 0xfc, 0x84, 0x35, ++ 0x6e, 0x1b, 0xf2, 0xe3, 0x6f, 0x04, 0x9f, 0x1c, 0x89, 0xfd, 0x59, 0x0e, ++ 0xda, 0x55, 0xbf, 0x99, 0x9e, 0x77, 0x18, 0xe5, 0xca, 0x84, 0xf8, 0xa5, ++ 0x2d, 0xc8, 0x24, 0x93, 0x58, 0x27, 0xc9, 0x1b, 0x4d, 0xee, 0x5d, 0x48, ++ 0x3e, 0x51, 0x86, 0x79, 0x90, 0x7f, 0xd7, 0xe6, 0x03, 0xdd, 0x7f, 0x98, ++ 0xf5, 0xd6, 0x74, 0xec, 0xfc, 0xb0, 0xf3, 0x89, 0x1c, 0xd4, 0x7f, 0x20, ++ 0x1f, 0xbe, 0x97, 0x9f, 0x78, 0x29, 0xfc, 0x1a, 0x3f, 0x6a, 0x70, 0x23, ++ 0x1f, 0xe2, 0x3a, 0xe8, 0xe3, 0xc3, 0x28, 0xf8, 0x35, 0x3e, 0x62, 0xb7, ++ 0x74, 0x52, 0x80, 0xe1, 0x16, 0xb0, 0x4b, 0x31, 0xd5, 0xec, 0x54, 0xc6, ++ 0x1a, 0x78, 0x1c, 0xb8, 0x9a, 0xde, 0x3f, 0x3f, 0x60, 0xe2, 0x09, 0x96, ++ 0x06, 0x3e, 0x8f, 0xa5, 0x41, 0x82, 0xfb, 0x46, 0xe7, 0x5a, 0x8a, 0x37, ++ 0x1b, 0x31, 0x2c, 0xe0, 0x47, 0xb8, 0xa6, 0x8d, 0xfc, 0x7c, 0xa8, 0x82, ++ 0x95, 0x3d, 0x33, 0xf2, 0x71, 0x1f, 0x06, 0xf0, 0xd6, 0xfc, 0xff, 0x84, ++ 0x37, 0xda, 0x2e, 0xbf, 0x5c, 0x3c, 0xb4, 0x06, 0x57, 0xf4, 0x3a, 0xd6, ++ 0xc6, 0x97, 0x26, 0xef, 0xa4, 0x78, 0xe8, 0xfa, 0xa9, 0x36, 0x8a, 0x8f, ++ 0x1e, 0x27, 0xe2, 0x4a, 0xeb, 0xe7, 0x1b, 0x28, 0x4e, 0x08, 0xf6, 0x6f, ++ 0x64, 0xf7, 0xd7, 0x31, 0x4b, 0x08, 0xe5, 0xf0, 0xb5, 0xc2, 0x8e, 0xd6, ++ 0xe2, 0xf4, 0x7f, 0x25, 0x71, 0xff, 0x67, 0x70, 0xaf, 0x59, 0xdd, 0x11, ++ 0x61, 0x8f, 0x5f, 0x1a, 0x27, 0xad, 0x52, 0x1c, 0x76, 0x70, 0x09, 0x8f, ++ 0xa7, 0xee, 0xb3, 0xb7, 0x6b, 0xb9, 0xbd, 0xdd, 0xa7, 0xd7, 0xc4, 0xbd, ++ 0x80, 0xf6, 0x51, 0x5c, 0x96, 0xb7, 0xdf, 0xaf, 0x52, 0xbc, 0xc4, 0xcb, ++ 0x12, 0xaf, 0x1f, 0x9c, 0xc1, 0xb8, 0xbd, 0x5e, 0x23, 0xca, 0xe7, 0x38, ++ 0x44, 0x3c, 0x05, 0xcc, 0x25, 0xa9, 0x3f, 0x5e, 0xbd, 0xbd, 0x83, 0x11, ++ 0xff, 0xb7, 0xdb, 0xb3, 0xa8, 0x3c, 0x45, 0xe6, 0xfa, 0x87, 0x7d, 0x8f, ++ 0xeb, 0x9f, 0xf6, 0x4c, 0x6e, 0x4f, 0xb6, 0xdf, 0x99, 0x47, 0xe5, 0xb0, ++ 0x2f, 0x18, 0x86, 0x78, 0x9f, 0x25, 0x83, 0xfd, 0xcc, 0xcf, 0xe7, 0xf9, ++ 0xfe, 0x20, 0x97, 0x8f, 0x17, 0xed, 0xa7, 0x5d, 0x9f, 0xcf, 0xed, 0xb2, ++ 0x3e, 0x3b, 0x47, 0xe4, 0xa3, 0xfd, 0xb2, 0xcf, 0x66, 0x04, 0x36, 0x22, ++ 0xdf, 0xcf, 0x29, 0xf2, 0x0d, 0x95, 0x80, 0xaf, 0x66, 0x99, 0xb8, 0xdf, ++ 0x15, 0xf8, 0x6e, 0x33, 0xde, 0x89, 0xa9, 0x62, 0x0d, 0xdb, 0x95, 0x6c, ++ 0xbc, 0x5f, 0xd1, 0xf0, 0xae, 0x21, 0x9b, 0xf8, 0xee, 0x29, 0xe2, 0xbb, ++ 0x42, 0xe0, 0xbb, 0x6c, 0x1d, 0xdf, 0x85, 0xf2, 0x47, 0x73, 0xf9, 0x8b, ++ 0xc2, 0x54, 0xe3, 0xbb, 0x3e, 0x7e, 0x2b, 0x88, 0x8e, 0x87, 0x0b, 0xfc, ++ 0x1c, 0xfb, 0x69, 0x77, 0x76, 0x7e, 0x50, 0x87, 0xfb, 0x8a, 0x2e, 0x33, ++ 0xd1, 0x41, 0x8b, 0x6b, 0x8c, 0x5e, 0xe7, 0x11, 0xf0, 0x9c, 0x34, 0x72, ++ 0x78, 0xdc, 0xb2, 0x4c, 0xf0, 0xec, 0x1e, 0x08, 0x9e, 0x2b, 0xe1, 0xff, ++ 0x48, 0x7e, 0x1b, 0xc2, 0x38, 0x9f, 0x0f, 0xb6, 0x0e, 0x86, 0x28, 0x2c, ++ 0x68, 0x2f, 0xe9, 0x5f, 0x07, 0x6b, 0x3c, 0x81, 0x30, 0x8e, 0xdb, 0xb7, ++ 0x1e, 0x96, 0xf3, 0x7d, 0xe4, 0x25, 0x70, 0xcb, 0x36, 0xe2, 0x8b, 0xdb, ++ 0xef, 0x94, 0x39, 0xbf, 0xc6, 0x72, 0x7d, 0x8e, 0xe7, 0x49, 0xc9, 0x30, ++ 0x7e, 0x8d, 0x18, 0xff, 0xf6, 0x95, 0xfe, 0x4a, 0x27, 0xd6, 0xab, 0x91, ++ 0x08, 0x0f, 0x35, 0x5d, 0xb5, 0x14, 0xf7, 0xc5, 0x2a, 0xf9, 0xb9, 0x90, ++ 0x17, 0xfe, 0x20, 0x3c, 0xcd, 0x42, 0xce, 0x69, 0xe7, 0x57, 0xd3, 0x44, ++ 0xfb, 0x29, 0x8e, 0x1a, 0x23, 0xfa, 0xe3, 0xa6, 0x56, 0xeb, 0xcf, 0x91, ++ 0xa6, 0xd9, 0xf8, 0x39, 0xd5, 0xed, 0x53, 0x8d, 0x1f, 0x46, 0xda, 0x3d, ++ 0xd3, 0xd8, 0xea, 0xcf, 0x31, 0x4e, 0x71, 0x1a, 0x9e, 0x33, 0x69, 0xf5, ++ 0x81, 0x8f, 0xde, 0xcf, 0xb7, 0xbb, 0xe9, 0xfc, 0x5b, 0x65, 0xf9, 0x78, ++ 0xce, 0x74, 0x58, 0xf8, 0x59, 0xce, 0x01, 0x5f, 0x23, 0xdf, 0xbf, 0x96, ++ 0x38, 0x6f, 0xf3, 0xfd, 0xc0, 0x77, 0xf9, 0x4f, 0x16, 0x95, 0xa0, 0x3f, ++ 0x6e, 0x7c, 0xd2, 0x82, 0xed, 0x6b, 0x20, 0xff, 0xec, 0xa6, 0xe1, 0x94, ++ 0x7f, 0x2d, 0xe9, 0xfb, 0x0f, 0xbc, 0x85, 0xe5, 0x5b, 0xf3, 0x28, 0x5f, ++ 0x69, 0x90, 0x88, 0x4f, 0xcf, 0xd5, 0xf2, 0xf6, 0x05, 0x65, 0x77, 0x4e, ++ 0xca, 0x8c, 0x43, 0xf9, 0x2f, 0xfa, 0xc5, 0xf5, 0x84, 0xfb, 0xf5, 0x98, ++ 0x40, 0x7b, 0x0d, 0xd4, 0xf3, 0x8c, 0xc8, 0x2a, 0xc1, 0xf8, 0xd1, 0x4a, ++ 0xe1, 0x37, 0x38, 0x77, 0x3f, 0xa3, 0xf2, 0x9b, 0x46, 0xda, 0x79, 0x48, ++ 0xee, 0x3c, 0x95, 0xfc, 0x7e, 0x95, 0x31, 0xa2, 0xfc, 0x07, 0xbc, 0xdf, ++ 0x37, 0x46, 0xfd, 0x47, 0x09, 0xc6, 0x11, 0x57, 0x66, 0xf5, 0x4e, 0x47, ++ 0xfe, 0x7e, 0xa3, 0xe4, 0xe5, 0xe1, 0x98, 0x3f, 0x2c, 0x7d, 0x3e, 0x7d, ++ 0xa0, 0x38, 0x86, 0xc2, 0x02, 0x29, 0x3c, 0x0c, 0xf0, 0x52, 0xe9, 0xe2, ++ 0xf5, 0xab, 0x4b, 0x7e, 0x9e, 0x82, 0x7e, 0x98, 0xca, 0x0a, 0x9e, 0x2f, ++ 0xf4, 0x96, 0xaf, 0xcc, 0xc6, 0x72, 0xc3, 0xf9, 0xe9, 0x03, 0xdd, 0xef, ++ 0x8d, 0x11, 0xfb, 0x9e, 0xbe, 0xfb, 0x6a, 0x62, 0x5d, 0xbf, 0xe8, 0x3b, ++ 0x41, 0xf7, 0xd3, 0xfc, 0x16, 0xc9, 0x8b, 0x53, 0xf4, 0x8f, 0x39, 0x41, ++ 0x7e, 0x07, 0x66, 0x93, 0x1c, 0xe8, 0x3a, 0xf3, 0xfb, 0x32, 0x15, 0xf4, ++ 0x73, 0x8f, 0xf3, 0xf1, 0x38, 0xd3, 0x0a, 0xcb, 0xd2, 0x64, 0x94, 0x5f, ++ 0xb7, 0x04, 0x4c, 0xa5, 0x18, 0x2f, 0xec, 0xb0, 0x8c, 0x3a, 0x8c, 0x71, ++ 0x04, 0xf1, 0x63, 0xca, 0x47, 0x23, 0x5d, 0xc7, 0x59, 0x18, 0xd1, 0x15, ++ 0xf8, 0x3c, 0xae, 0x00, 0xd6, 0xd7, 0xb4, 0xab, 0x3f, 0x1f, 0x1a, 0x87, ++ 0xcc, 0x65, 0xd3, 0xf3, 0xb9, 0xc6, 0x47, 0x35, 0x1a, 0x7f, 0x57, 0xea, ++ 0xf9, 0x18, 0xd6, 0xa7, 0x1b, 0xdb, 0x5f, 0x4e, 0xde, 0x0e, 0xc6, 0xc7, ++ 0x30, 0xfe, 0xd0, 0x02, 0x5c, 0x67, 0xdf, 0xd3, 0xeb, 0x9b, 0xbe, 0xfe, ++ 0xa2, 0xd6, 0x5b, 0x74, 0xff, 0x83, 0xc9, 0x01, 0xfc, 0x89, 0x94, 0x8b, ++ 0xfd, 0x70, 0x74, 0xd2, 0xba, 0x4a, 0xc3, 0xe8, 0xbd, 0x6c, 0x5c, 0x77, ++ 0x6d, 0xda, 0xba, 0x1b, 0x89, 0xf3, 0x30, 0x19, 0xba, 0xe9, 0x9e, 0x4e, ++ 0x86, 0xe4, 0x1d, 0x4e, 0x17, 0x56, 0xc7, 0x78, 0x2d, 0xa4, 0x8f, 0xa2, ++ 0xe0, 0xd6, 0xe0, 0x4b, 0x07, 0xd9, 0xc6, 0x4a, 0x2e, 0x85, 0x0b, 0x7f, ++ 0x14, 0xcd, 0x5e, 0xe4, 0x3f, 0x6e, 0xf4, 0x4b, 0xa4, 0x89, 0x72, 0x68, ++ 0xe7, 0x63, 0xae, 0x7e, 0xb8, 0x60, 0xfc, 0x1b, 0x10, 0x0f, 0x6c, 0x39, ++ 0x87, 0x67, 0x8b, 0xd4, 0xc0, 0xe5, 0x86, 0xd8, 0x1f, 0x68, 0xfe, 0x8c, ++ 0x3a, 0x6d, 0xbe, 0xfb, 0xf5, 0xf3, 0x2d, 0x8b, 0xe1, 0xf7, 0xd6, 0x3d, ++ 0xe8, 0x77, 0xc2, 0x76, 0xee, 0x51, 0xc3, 0xbf, 0x0d, 0xee, 0x7a, 0xa1, ++ 0x4f, 0xa7, 0x5a, 0xfc, 0x8f, 0x9a, 0x61, 0x0e, 0xb7, 0x39, 0x67, 0x11, ++ 0x3f, 0xdc, 0x01, 0x1a, 0xcd, 0x09, 0xf3, 0xff, 0x5b, 0x6a, 0xa0, 0x06, ++ 0xf1, 0xd1, 0x2c, 0x05, 0x5f, 0xe9, 0xc9, 0x24, 0x7f, 0x3c, 0xc5, 0x77, ++ 0x00, 0xbd, 0x27, 0x17, 0x44, 0xd8, 0x01, 0x1a, 0x5c, 0xd1, 0xf8, 0xa8, ++ 0x1b, 0x44, 0x1e, 0x46, 0xc3, 0x1d, 0x8d, 0x87, 0x7e, 0xfa, 0x74, 0x27, ++ 0x63, 0xaa, 0xdd, 0x77, 0xeb, 0x9b, 0x57, 0xd4, 0x7c, 0xa2, 0xed, 0x02, ++ 0xb7, 0x49, 0xef, 0xcf, 0x73, 0x09, 0xbf, 0x9b, 0xab, 0xdf, 0xcf, 0x56, ++ 0x80, 0xe5, 0xd5, 0x2c, 0xc6, 0x4b, 0x7e, 0x36, 0xaf, 0x44, 0xfb, 0xa8, ++ 0x6a, 0xd0, 0xf3, 0x28, 0x47, 0xab, 0xab, 0x18, 0xf9, 0x47, 0x5c, 0x36, ++ 0x03, 0xf9, 0xd9, 0x34, 0x7d, 0x3f, 0x18, 0x7f, 0xdf, 0x70, 0x3d, 0x97, ++ 0x37, 0xd5, 0x0b, 0x99, 0xb8, 0x4f, 0xc7, 0xe7, 0x11, 0xcd, 0x5f, 0x43, ++ 0x58, 0xcf, 0x83, 0xf4, 0x9e, 0x83, 0x45, 0xdd, 0x38, 0x1b, 0xd7, 0xed, ++ 0x7c, 0x9b, 0x2e, 0x0e, 0xbe, 0xda, 0xc6, 0xfd, 0xf3, 0x2b, 0x0b, 0x24, ++ 0xe1, 0x97, 0xef, 0x19, 0x8d, 0x7e, 0x89, 0xbe, 0xfc, 0x25, 0xfe, 0xe0, ++ 0x9e, 0xd1, 0x28, 0x3f, 0xa6, 0xcb, 0xfa, 0x73, 0xaa, 0xea, 0x8b, 0xdc, ++ 0x1f, 0xec, 0xba, 0x28, 0x51, 0x5a, 0xed, 0x3d, 0x31, 0x1a, 0xfd, 0x2c, ++ 0xae, 0xaa, 0x9e, 0xd1, 0x28, 0x87, 0x1e, 0x19, 0xea, 0x5b, 0x85, 0x74, ++ 0x3d, 0x6e, 0xe0, 0xfe, 0xf2, 0x4b, 0xfc, 0x16, 0x05, 0x06, 0xcd, 0x1f, ++ 0x7c, 0x45, 0x7c, 0x17, 0x4d, 0x0f, 0xed, 0xfc, 0x2f, 0x26, 0xcd, 0xbf, ++ 0x01, 0xc7, 0x39, 0x23, 0x75, 0x97, 0x61, 0xe1, 0x86, 0x2c, 0x71, 0x3e, ++ 0xc3, 0x02, 0x99, 0xc8, 0x97, 0x4e, 0x47, 0x66, 0x39, 0xfa, 0x71, 0x40, ++ 0xce, 0x7d, 0xf3, 0x0d, 0x6e, 0x1e, 0xb1, 0x08, 0xf0, 0x35, 0x26, 0x23, ++ 0x10, 0xc2, 0x76, 0x77, 0x30, 0xff, 0x78, 0xbc, 0x6b, 0xe9, 0xaa, 0x0a, ++ 0x18, 0xf9, 0x79, 0x05, 0xa3, 0xf9, 0x2f, 0x12, 0xf3, 0x1f, 0x2f, 0xf4, ++ 0xdf, 0xf9, 0xcd, 0x3c, 0xae, 0xa2, 0xd2, 0x57, 0xf0, 0x04, 0x1e, 0x89, ++ 0xd4, 0x1f, 0x35, 0xb2, 0x10, 0xad, 0x3f, 0x1f, 0xe9, 0xb1, 0xfb, 0x04, ++ 0xfc, 0xe7, 0x41, 0xd5, 0x85, 0xb1, 0xfe, 0x2e, 0x3b, 0xe9, 0xc1, 0x79, ++ 0xaf, 0xcf, 0xa2, 0x78, 0x89, 0xfc, 0x0d, 0x86, 0xfe, 0x77, 0x2b, 0xe0, ++ 0xef, 0xb0, 0x50, 0x8c, 0xee, 0xdd, 0x8a, 0xc2, 0x9d, 0x2e, 0x5d, 0xbe, ++ 0xb8, 0x33, 0x45, 0x57, 0x7f, 0xe4, 0xfe, 0x2c, 0x5d, 0xf9, 0xa8, 0xf0, ++ 0x70, 0x5d, 0xf9, 0x55, 0x47, 0x4b, 0x74, 0xf9, 0xd1, 0xdd, 0xd7, 0xea, ++ 0xea, 0x5f, 0x7d, 0xac, 0x42, 0x97, 0xbf, 0xa6, 0x67, 0x92, 0xae, 0xfe, ++ 0xf7, 0x4e, 0x4f, 0xd6, 0xe5, 0xaf, 0xeb, 0xbd, 0x4b, 0x57, 0xff, 0xa3, ++ 0xbe, 0x7d, 0xbc, 0xd0, 0xdf, 0x41, 0x5f, 0x77, 0x01, 0xcc, 0x7b, 0xb6, ++ 0xc6, 0x9f, 0x17, 0x67, 0xea, 0xda, 0xff, 0x29, 0x6e, 0xc2, 0x51, 0xe4, ++ 0xcf, 0xd9, 0xab, 0x79, 0xfc, 0x77, 0x39, 0x60, 0x48, 0xf7, 0x8e, 0x47, ++ 0x1b, 0xd7, 0xf3, 0x0d, 0xf0, 0x07, 0xe9, 0x3b, 0x9e, 0xf5, 0x52, 0xdc, ++ 0x5d, 0x5d, 0x48, 0xf2, 0x86, 0x19, 0xc6, 0x91, 0xe9, 0xed, 0x80, 0x05, ++ 0xfb, 0x3b, 0x08, 0x8f, 0x97, 0xbb, 0xf7, 0x9e, 0xef, 0x9e, 0x61, 0x40, ++ 0xd3, 0xf7, 0x83, 0x02, 0x11, 0x6f, 0x72, 0x35, 0xbb, 0x9a, 0xc7, 0x8d, ++ 0x7e, 0x3b, 0x5d, 0xf3, 0x58, 0xce, 0xdf, 0x45, 0x57, 0xb3, 0x47, 0x4f, ++ 0x57, 0xab, 0xaa, 0xa7, 0x6b, 0x6c, 0x81, 0x9e, 0xae, 0x76, 0xaf, 0x9e, ++ 0xae, 0xf1, 0x63, 0xf4, 0x74, 0x75, 0xfa, 0xf4, 0x74, 0x4d, 0xa8, 0xd2, ++ 0xd3, 0x35, 0xd1, 0xaf, 0xa7, 0xeb, 0x90, 0x69, 0x7a, 0xba, 0x26, 0x07, ++ 0xf4, 0x74, 0x4d, 0x9d, 0xaf, 0xa7, 0x6b, 0x7a, 0x83, 0x9e, 0xae, 0x19, ++ 0x8d, 0x7a, 0xba, 0x65, 0x06, 0xef, 0xd5, 0x95, 0x0f, 0x46, 0x6f, 0x4d, ++ 0x1e, 0x66, 0xb7, 0x2e, 0xd2, 0xd5, 0xef, 0xa3, 0xbb, 0x7f, 0x3e, 0xc5, ++ 0x11, 0xe5, 0xb6, 0xfd, 0x58, 0xd7, 0xbf, 0x46, 0xf7, 0x20, 0xfc, 0x41, ++ 0xba, 0xe7, 0x33, 0x11, 0xef, 0xf8, 0x3f, 0xa4, 0x7b, 0xf2, 0x30, 0x3d, ++ 0xbd, 0x41, 0x7f, 0xa4, 0x0c, 0x1b, 0x4d, 0x7a, 0x3f, 0x1d, 0xd3, 0x69, ++ 0xf9, 0xc2, 0xbe, 0xf6, 0x0f, 0xac, 0xf7, 0x35, 0xf9, 0x13, 0xa9, 0x67, ++ 0x23, 0xf7, 0x97, 0x83, 0xc9, 0xa5, 0x4b, 0xf4, 0x8a, 0xd8, 0x6f, 0x0e, ++ 0xaa, 0x57, 0xa2, 0xf6, 0x9b, 0xef, 0x31, 0xd0, 0x7b, 0x34, 0xc8, 0x6a, ++ 0xf2, 0x1f, 0xdd, 0x29, 0xf8, 0xf3, 0x50, 0x0c, 0xc7, 0xfb, 0x17, 0x58, ++ 0x74, 0x0d, 0xd4, 0x83, 0x3a, 0x63, 0x00, 0xae, 0xf7, 0x10, 0x6e, 0x18, ++ 0xe7, 0xbd, 0x98, 0x42, 0xf2, 0x0b, 0xdc, 0xc5, 0x3a, 0x8d, 0xd8, 0xff, ++ 0xdd, 0xac, 0x9b, 0xd2, 0xe9, 0xac, 0x97, 0xd2, 0x00, 0x73, 0x90, 0x1e, ++ 0x9d, 0xc9, 0xbc, 0x94, 0xce, 0x66, 0x7e, 0x93, 0xf0, 0x13, 0xdc, 0x30, ++ 0x2c, 0x11, 0xfd, 0x07, 0x3d, 0x65, 0xa8, 0x87, 0x2f, 0xcc, 0x78, 0xeb, ++ 0x38, 0x9d, 0x2f, 0xbd, 0x91, 0x70, 0x45, 0xef, 0x3d, 0x7c, 0x88, 0xe7, ++ 0x18, 0xb9, 0x8c, 0x9d, 0x12, 0xf2, 0xe0, 0x24, 0x9e, 0x67, 0x40, 0xfe, ++ 0xac, 0x55, 0xf8, 0xd3, 0x7c, 0x4c, 0x75, 0x47, 0xe0, 0xed, 0x94, 0xf0, ++ 0xfb, 0xcd, 0x1c, 0x27, 0x91, 0x3e, 0x64, 0x72, 0x0c, 0xc5, 0x59, 0xcd, ++ 0xbc, 0x43, 0x22, 0x7d, 0x32, 0xf3, 0xff, 0xf2, 0xf4, 0x8e, 0x61, 0xdc, ++ 0x1e, 0x8d, 0x4e, 0x9b, 0x1b, 0x35, 0xfc, 0xf1, 0x7d, 0xca, 0xda, 0x61, ++ 0x2a, 0xc9, 0xf7, 0x34, 0xd6, 0x29, 0xf4, 0x1e, 0x0b, 0xd8, 0xb2, 0xa9, ++ 0x1f, 0x7e, 0xfe, 0xf0, 0xb4, 0x89, 0xf6, 0x93, 0x1e, 0x0b, 0x87, 0xef, ++ 0x79, 0x89, 0x29, 0x63, 0x5c, 0x74, 0xed, 0x8c, 0xe8, 0xea, 0xb1, 0x70, ++ 0x78, 0x9e, 0x37, 0x32, 0x0b, 0xe2, 0xf3, 0x39, 0x16, 0x50, 0x91, 0x18, ++ 0x8f, 0x28, 0x20, 0xa2, 0xf8, 0x7d, 0x87, 0xe1, 0xc8, 0x1f, 0x33, 0xff, ++ 0xef, 0x5b, 0x59, 0xe8, 0x2f, 0x8b, 0x59, 0xb5, 0x7b, 0x6a, 0xe5, 0x35, ++ 0x78, 0x3e, 0x12, 0x5c, 0x4a, 0xfe, 0xea, 0x1f, 0x30, 0xbd, 0xbf, 0xfa, ++ 0xee, 0x06, 0x89, 0xfc, 0xd5, 0x3f, 0x00, 0x38, 0x21, 0xf5, 0x38, 0xbc, ++ 0x1e, 0xd4, 0x97, 0x5a, 0x3e, 0x88, 0xf0, 0xc2, 0x3c, 0x2a, 0xb1, 0x1e, ++ 0x7c, 0x1f, 0xe2, 0x69, 0x90, 0xd0, 0x3f, 0xf4, 0x0f, 0xeb, 0x6f, 0xcf, ++ 0x8f, 0x79, 0xbd, 0xbf, 0xb3, 0xbf, 0xbe, 0x7e, 0x18, 0x87, 0x0b, 0x7f, ++ 0x90, 0x7e, 0x9a, 0xff, 0xb1, 0xc0, 0xc0, 0xe3, 0x15, 0x7a, 0xef, 0xe7, ++ 0xfb, 0x94, 0xed, 0x3f, 0x60, 0xdc, 0x8f, 0xd6, 0x18, 0x2c, 0x0f, 0xe2, ++ 0xf9, 0xa4, 0x0c, 0x1b, 0x4a, 0x8c, 0x67, 0x32, 0xf2, 0x7b, 0xe8, 0x6b, ++ 0x87, 0x65, 0xf2, 0xfb, 0x6e, 0xac, 0x9b, 0xf6, 0xf9, 0xec, 0x88, 0x66, ++ 0x5f, 0x06, 0x48, 0xfe, 0x16, 0x89, 0x7b, 0x0e, 0x67, 0xc5, 0xf9, 0xde, ++ 0xdc, 0x0e, 0x0b, 0xc3, 0x78, 0x99, 0xa2, 0xdd, 0x07, 0x5d, 0x78, 0x9e, ++ 0x37, 0x17, 0x78, 0xb0, 0x1b, 0xf5, 0xb0, 0x12, 0xa0, 0x77, 0x56, 0x8a, ++ 0x36, 0xbe, 0xe6, 0xe2, 0xfe, 0x37, 0xa3, 0x13, 0xef, 0x2f, 0x6a, 0xfa, ++ 0x7f, 0x70, 0x3e, 0x55, 0xd8, 0xa9, 0x88, 0xfb, 0x02, 0xc0, 0x77, 0x0d, ++ 0x03, 0xd9, 0x1f, 0x7b, 0x86, 0xf3, 0x73, 0xfa, 0xe6, 0xa6, 0xee, 0x61, ++ 0x78, 0x1e, 0xa7, 0xc1, 0xf3, 0x70, 0xd3, 0x51, 0xca, 0xcb, 0x8a, 0x97, ++ 0xe2, 0x0c, 0xf1, 0x1d, 0x26, 0x67, 0x44, 0x7b, 0x93, 0x1b, 0xca, 0x23, ++ 0xe4, 0x9d, 0x62, 0x83, 0xf6, 0x11, 0x72, 0xc8, 0x68, 0xf3, 0xd3, 0x63, ++ 0x26, 0xcb, 0x9b, 0xba, 0xe9, 0x9c, 0xcf, 0x28, 0xde, 0x8b, 0x5a, 0x91, ++ 0xb6, 0xc8, 0x11, 0x88, 0xd8, 0xc7, 0xbd, 0x30, 0x8c, 0x8f, 0xcf, 0x2c, ++ 0x41, 0xe6, 0x48, 0x62, 0xc2, 0x04, 0xc7, 0x54, 0x39, 0x85, 0x72, 0xed, ++ 0xaf, 0x8c, 0xef, 0x67, 0xcd, 0x1e, 0xe8, 0x27, 0x52, 0x7e, 0x5e, 0x4c, ++ 0x64, 0x91, 0x7e, 0xfa, 0xd6, 0xa6, 0x63, 0x04, 0xef, 0x72, 0x29, 0x10, ++ 0xc0, 0x4e, 0xcc, 0x39, 0x2c, 0x6c, 0x05, 0xfa, 0x98, 0x15, 0xbc, 0x73, ++ 0x0b, 0xdf, 0x37, 0xde, 0x78, 0x14, 0xe3, 0xa9, 0x4c, 0xf6, 0x45, 0xde, ++ 0xb0, 0x3a, 0x38, 0xde, 0xcc, 0x1e, 0xe5, 0x42, 0xa4, 0x3c, 0x7d, 0x75, ++ 0x98, 0xd8, 0x47, 0x0b, 0x79, 0xfa, 0x2f, 0x4d, 0xbd, 0x85, 0x38, 0x4e, ++ 0x73, 0x53, 0x8f, 0x86, 0x2f, 0x86, 0xe7, 0xa6, 0xc1, 0x64, 0x7e, 0x8f, ++ 0xbe, 0xb9, 0xe9, 0x13, 0xfa, 0x6e, 0xa8, 0x52, 0x89, 0xdf, 0x5e, 0xdd, ++ 0x98, 0x7f, 0x50, 0x85, 0xf2, 0xe3, 0xf0, 0x17, 0xdf, 0xb5, 0x31, 0xbb, ++ 0x39, 0x5c, 0xec, 0xa2, 0x9b, 0xf4, 0xea, 0x74, 0xc1, 0x07, 0xe8, 0x13, ++ 0x4b, 0x07, 0xfe, 0x39, 0xde, 0x68, 0x24, 0x3e, 0x5b, 0x9c, 0x6e, 0x23, ++ 0x7f, 0xfd, 0xe2, 0x37, 0x73, 0x0f, 0xfa, 0x60, 0x3d, 0x9b, 0x60, 0xba, ++ 0xf2, 0x77, 0x80, 0xbb, 0x7f, 0x1c, 0x8e, 0x27, 0x93, 0x90, 0xa7, 0xc0, ++ 0x4f, 0x7e, 0x94, 0x0f, 0xa6, 0x14, 0x85, 0xfc, 0xf6, 0x2e, 0xc7, 0x64, ++ 0xa2, 0xd3, 0xdf, 0xdb, 0x9f, 0x86, 0x5f, 0x93, 0x95, 0xd1, 0x7b, 0x44, ++ 0xa6, 0x74, 0x1b, 0xd9, 0x05, 0x57, 0x0a, 0xe7, 0xb9, 0x28, 0x7d, 0x05, ++ 0x78, 0x21, 0xf9, 0xbf, 0x58, 0xe0, 0x45, 0x7b, 0x5f, 0xe9, 0xf8, 0x03, ++ 0x8c, 0xf6, 0x0b, 0x8b, 0x1f, 0xe2, 0xfe, 0xbb, 0xc5, 0xb5, 0x8c, 0xe2, ++ 0xfd, 0x59, 0x23, 0xfc, 0x94, 0xf5, 0xf3, 0x8d, 0xa6, 0x67, 0x12, 0xf1, ++ 0x25, 0x18, 0xf8, 0xd8, 0xd6, 0x04, 0x2b, 0x0e, 0xba, 0x78, 0xac, 0xc9, ++ 0xc2, 0x02, 0xf9, 0x60, 0x87, 0x60, 0x7c, 0x7c, 0x76, 0x3f, 0x1d, 0xdb, ++ 0x7c, 0x8a, 0x13, 0x8f, 0xfa, 0xd7, 0x54, 0xba, 0x6b, 0x30, 0x7d, 0x6c, ++ 0xcc, 0xc9, 0x36, 0x14, 0x7f, 0x8f, 0x8f, 0xfd, 0xb2, 0x1b, 0x53, 0xf4, ++ 0xd5, 0xe3, 0xf8, 0x8e, 0x06, 0x16, 0x42, 0xfb, 0x98, 0xce, 0xe0, 0x61, ++ 0x7c, 0xe7, 0x7c, 0xc8, 0xc3, 0xf8, 0x71, 0xa2, 0x3c, 0x2e, 0xc0, 0xf3, ++ 0xf1, 0xa2, 0x3c, 0x7e, 0x1a, 0xcf, 0xa7, 0xfb, 0x5e, 0x90, 0x2a, 0x11, ++ 0xb0, 0xa8, 0x73, 0xa5, 0x74, 0x9b, 0x6b, 0x62, 0x0e, 0xca, 0xe9, 0xd9, ++ 0x8c, 0xdf, 0xb7, 0x16, 0xef, 0x2d, 0x6c, 0x11, 0xfa, 0x22, 0xd5, 0xe6, ++ 0xaa, 0xa9, 0xc4, 0xf2, 0xbb, 0x19, 0xdd, 0xbf, 0xd0, 0xca, 0x9f, 0x14, ++ 0xe5, 0xc9, 0xb6, 0x0f, 0x5b, 0xb3, 0x51, 0x8f, 0x4c, 0xd5, 0xb7, 0xdf, ++ 0x28, 0xf0, 0x30, 0xc4, 0xf6, 0x61, 0xdb, 0x38, 0x3a, 0x7f, 0xd2, 0x97, ++ 0x6b, 0xe7, 0x3b, 0x89, 0xb6, 0xf3, 0x47, 0xa9, 0x7d, 0x91, 0xbe, 0x7c, ++ 0x9d, 0x68, 0x6f, 0xb7, 0x9d, 0xef, 0x1e, 0x87, 0xe5, 0x39, 0xfa, 0xf1, ++ 0x1f, 0x15, 0xe5, 0xb1, 0x36, 0x2e, 0x0f, 0x99, 0x9f, 0xf1, 0x77, 0x01, ++ 0x44, 0xf9, 0x23, 0xa2, 0xdc, 0x8a, 0xe5, 0x38, 0xbe, 0x97, 0x97, 0xcb, ++ 0xda, 0xfb, 0x17, 0xa2, 0xde, 0x4a, 0x01, 0x07, 0xc6, 0xb6, 0x91, 0xff, ++ 0x73, 0x18, 0xf7, 0x7f, 0x6e, 0x6d, 0xb2, 0x14, 0x11, 0x5d, 0x9a, 0x2e, ++ 0x12, 0x7d, 0x1e, 0x6b, 0x62, 0x94, 0x9f, 0x34, 0xdc, 0xc5, 0xef, 0x65, ++ 0x57, 0x71, 0x7c, 0xbb, 0xdc, 0x9c, 0x1f, 0x1c, 0x8d, 0x6c, 0xc0, 0xf7, ++ 0x00, 0x26, 0x0d, 0xe7, 0xfb, 0xaa, 0x38, 0xb5, 0xc7, 0xe7, 0x1b, 0x40, ++ 0xee, 0x69, 0xe5, 0x2e, 0x07, 0x7f, 0xef, 0x40, 0xf6, 0x98, 0x88, 0x9f, ++ 0xcc, 0x36, 0x21, 0x37, 0xc4, 0x7a, 0xec, 0x93, 0x1b, 0x52, 0x83, 0x97, ++ 0x33, 0x19, 0xf7, 0x97, 0x5f, 0x8e, 0xaf, 0x61, 0xa1, 0x5d, 0x40, 0xfb, ++ 0x68, 0x28, 0xfc, 0x20, 0x5f, 0xa7, 0x3d, 0x60, 0x60, 0x81, 0x08, 0x79, ++ 0x99, 0xb2, 0x30, 0x86, 0x05, 0x22, 0xea, 0x7b, 0x66, 0xbb, 0x74, 0xf9, ++ 0xa4, 0xbb, 0x53, 0x74, 0xf5, 0xdd, 0x53, 0xb3, 0x74, 0xe5, 0xb6, 0xd2, ++ 0xe1, 0xba, 0x72, 0x36, 0xd5, 0x45, 0xeb, 0x66, 0x91, 0xe0, 0xaf, 0x98, ++ 0xa2, 0x12, 0x5d, 0xb9, 0xf6, 0x0e, 0x03, 0xdb, 0x2e, 0xea, 0x89, 0xf5, ++ 0x6b, 0xcc, 0xb9, 0x56, 0x57, 0xef, 0x7c, 0x81, 0x1a, 0x8f, 0x3c, 0x7e, ++ 0x6a, 0x22, 0xe8, 0x1f, 0x8a, 0x2b, 0xf0, 0x5a, 0x50, 0x3e, 0x2c, 0xb2, ++ 0x67, 0x0d, 0x41, 0xfd, 0xf3, 0x5c, 0xd3, 0x18, 0x42, 0xce, 0xf3, 0xb0, ++ 0xae, 0xc0, 0x68, 0x65, 0xbb, 0x9c, 0x3c, 0xde, 0x7c, 0x17, 0x9e, 0xe3, ++ 0x41, 0xf9, 0xbf, 0x36, 0xf9, 0xe8, 0xfb, 0x0e, 0x28, 0x57, 0x21, 0x7d, ++ 0x1a, 0xd6, 0x9d, 0x0a, 0xf5, 0x3b, 0x9a, 0x1c, 0x94, 0x7f, 0xaa, 0xc9, ++ 0x43, 0xe9, 0x96, 0x26, 0x95, 0xd2, 0x27, 0x9b, 0x0a, 0xa8, 0x7c, 0x63, ++ 0x93, 0x97, 0xf2, 0x4f, 0x40, 0xff, 0x98, 0xae, 0x83, 0x7e, 0xf0, 0xfb, ++ 0xda, 0xa6, 0x2a, 0xca, 0xaf, 0x69, 0xf2, 0x53, 0xfe, 0xf1, 0xa6, 0x69, ++ 0x94, 0x7f, 0xb4, 0x29, 0x40, 0xe9, 0x23, 0x4d, 0xf3, 0xe9, 0xfb, 0xca, ++ 0xa6, 0x06, 0xca, 0xaf, 0x68, 0x6a, 0xa4, 0xf4, 0xe1, 0xa6, 0x20, 0xa5, ++ 0xcd, 0x4d, 0xad, 0x54, 0x1e, 0x14, 0xf4, 0xde, 0x25, 0xee, 0xaf, 0xee, ++ 0x2a, 0xe7, 0xf7, 0xd2, 0xa3, 0xe9, 0xf8, 0xf0, 0x70, 0x49, 0xf7, 0x5e, ++ 0x9c, 0xbd, 0x3f, 0x7e, 0xe4, 0xe1, 0xe1, 0x18, 0x3f, 0xd2, 0xd9, 0x43, ++ 0x76, 0xb8, 0x16, 0x3f, 0x82, 0xf3, 0xa6, 0xfe, 0xac, 0x7c, 0xfe, 0xd1, ++ 0xfd, 0x6d, 0x1a, 0xce, 0xfd, 0x09, 0xc3, 0x59, 0xf7, 0xd2, 0x58, 0xbe, ++ 0x9e, 0xe9, 0x9c, 0x36, 0x77, 0xbf, 0x77, 0x59, 0x2c, 0xf0, 0x7d, 0x6a, ++ 0x03, 0xa7, 0x43, 0xe6, 0xfe, 0x5e, 0x2a, 0x4f, 0x9e, 0xcf, 0x69, 0xb1, ++ 0x49, 0xe8, 0x65, 0xe6, 0x0e, 0xb2, 0xb4, 0x32, 0x3a, 0xad, 0xa7, 0x7a, ++ 0x67, 0xa5, 0xee, 0x8a, 0x58, 0x7e, 0xbe, 0x4d, 0xfe, 0x0c, 0xe6, 0x81, ++ 0x79, 0x96, 0x89, 0x77, 0x92, 0x88, 0xed, 0x42, 0x06, 0x84, 0x4b, 0x19, ++ 0xc3, 0xf5, 0xa7, 0x46, 0xd7, 0xbe, 0x79, 0x3b, 0x39, 0x9c, 0x38, 0xff, ++ 0x81, 0xe0, 0xdd, 0x21, 0xe0, 0x95, 0x4b, 0x3b, 0xf9, 0xfb, 0x27, 0x55, ++ 0x6d, 0x61, 0x64, 0xfb, 0x18, 0x5f, 0x03, 0xbd, 0x7f, 0x62, 0x99, 0xe6, ++ 0x0f, 0x2b, 0x90, 0xba, 0xfd, 0x01, 0x7a, 0x8f, 0x61, 0xf8, 0xc5, 0x09, ++ 0xb0, 0x39, 0x03, 0x79, 0x73, 0xf1, 0x7a, 0xa6, 0x42, 0x9a, 0xb6, 0x50, ++ 0xbf, 0x6f, 0x4b, 0x99, 0x5d, 0xa2, 0xdb, 0x17, 0xc9, 0x17, 0x1f, 0x63, ++ 0x2a, 0xc8, 0x01, 0x5b, 0x91, 0x7e, 0x7f, 0x15, 0x93, 0xb3, 0x48, 0xd7, ++ 0xce, 0x92, 0xf6, 0x63, 0x5d, 0xb9, 0xc9, 0xbd, 0x4c, 0x57, 0x3e, 0xf3, ++ 0xbe, 0xcc, 0xe5, 0x1e, 0xc4, 0x67, 0x2a, 0x3f, 0xe7, 0x31, 0xaf, 0x5e, ++ 0xca, 0x92, 0x01, 0xae, 0x39, 0xed, 0x6b, 0x08, 0xae, 0x77, 0x04, 0x1d, ++ 0xcf, 0x4a, 0x2a, 0xdd, 0xe3, 0x0e, 0xee, 0xd6, 0xe2, 0x1e, 0xf8, 0xfe, ++ 0xe2, 0x59, 0xa1, 0x5f, 0x98, 0x65, 0x35, 0xd9, 0x63, 0xf9, 0x4e, 0x9e, ++ 0xcd, 0x8b, 0x0f, 0x1a, 0x50, 0x3f, 0x7c, 0xf6, 0x6f, 0xf1, 0x24, 0x97, ++ 0x9e, 0x79, 0xca, 0x10, 0x42, 0x7f, 0x2e, 0x88, 0x27, 0x03, 0xae, 0xff, ++ 0x42, 0x30, 0xfb, 0xb0, 0xbc, 0x98, 0xf5, 0x50, 0x1e, 0x43, 0x56, 0x30, ++ 0x3f, 0x8a, 0xa9, 0x32, 0xe6, 0xaf, 0x62, 0xbd, 0xb4, 0xbf, 0x82, 0xfd, ++ 0xc5, 0xef, 0x86, 0x63, 0xfc, 0xa8, 0x1c, 0x78, 0xca, 0x0a, 0xf9, 0x33, ++ 0xe9, 0x81, 0x67, 0x79, 0xfc, 0x5a, 0x98, 0xf4, 0x67, 0x9e, 0xa0, 0x67, ++ 0x9e, 0xb6, 0x9f, 0xda, 0xa0, 0x44, 0xfb, 0x79, 0xdf, 0x1a, 0x4e, 0x7c, ++ 0xa8, 0xbf, 0xc7, 0xd6, 0x22, 0xf6, 0x17, 0x2d, 0x56, 0xee, 0x7f, 0x5b, ++ 0xea, 0x2c, 0x1b, 0x82, 0x76, 0xeb, 0xd9, 0x41, 0xe2, 0x0d, 0xed, 0x9e, ++ 0x57, 0x8f, 0xcc, 0x06, 0x7c, 0xdb, 0x93, 0x0f, 0x52, 0xaa, 0x7d, 0x7f, ++ 0x54, 0x35, 0x0c, 0x78, 0x4f, 0xfb, 0x8f, 0x51, 0xfc, 0x3f, 0x0c, 0x98, ++ 0x5d, 0xf0, 0xff, 0x1f, 0x11, 0x9e, 0x33, 0xa5, 0x6f, 0x27, 0xa1, 0x1b, ++ 0xaa, 0x2e, 0xa7, 0x97, 0xd6, 0xc1, 0x59, 0xc9, 0xe7, 0x99, 0x81, 0xf8, ++ 0x7d, 0x5d, 0xe6, 0xfc, 0x08, 0x3b, 0x2e, 0x9c, 0x9f, 0x22, 0xf0, 0xab, ++ 0xec, 0x2e, 0xf7, 0xcc, 0x00, 0x3c, 0x2a, 0x6f, 0x66, 0x7b, 0x83, 0xac, ++ 0x7f, 0x9c, 0x67, 0x9a, 0x8e, 0x65, 0x63, 0x3c, 0x80, 0x96, 0xcf, 0x13, ++ 0xf1, 0xb2, 0x3b, 0x9b, 0x92, 0x73, 0x2a, 0x23, 0xbe, 0x3b, 0x0b, 0x39, ++ 0x3c, 0x05, 0xac, 0xbb, 0x0a, 0xf5, 0x55, 0x41, 0x91, 0xc1, 0x1b, 0xc2, ++ 0x8e, 0x7d, 0x0e, 0x9d, 0x1f, 0xc3, 0x9a, 0xd3, 0xe6, 0xc3, 0x77, 0x07, ++ 0x94, 0x12, 0xe6, 0x45, 0x31, 0x37, 0x8c, 0xb5, 0x2d, 0x43, 0xdd, 0xad, ++ 0xfc, 0x4d, 0xa6, 0x78, 0x27, 0xe5, 0xd0, 0x35, 0x4c, 0x85, 0xfd, 0x8c, ++ 0xcd, 0x16, 0x66, 0x18, 0x1f, 0xa6, 0xf5, 0xcb, 0x84, 0x3f, 0xe4, 0x01, ++ 0x21, 0x37, 0xbf, 0x74, 0x54, 0xc6, 0xd3, 0x7b, 0x92, 0x29, 0x7d, 0xf2, ++ 0x0f, 0x75, 0x24, 0xfb, 0xd2, 0xe6, 0xeb, 0x46, 0x3e, 0xfa, 0xb2, 0xdd, ++ 0xc8, 0xe7, 0x75, 0x48, 0x5f, 0x5e, 0x60, 0xe3, 0x71, 0x5c, 0x73, 0x0b, ++ 0x4c, 0x21, 0x55, 0xc2, 0xf7, 0xcb, 0xda, 0xe8, 0xbd, 0x44, 0x65, 0xab, ++ 0xc4, 0xd2, 0x32, 0x11, 0x8e, 0x71, 0x84, 0x07, 0xb6, 0x2f, 0x96, 0xf8, ++ 0x30, 0x76, 0xc3, 0x08, 0x16, 0x84, 0xf5, 0x52, 0xea, 0x0c, 0xfc, 0x05, ++ 0xf9, 0xe4, 0x4c, 0x58, 0xdd, 0x67, 0xc8, 0x16, 0x3c, 0x09, 0xf5, 0x6a, ++ 0x0b, 0x4d, 0xdb, 0xd0, 0x3e, 0xcb, 0x47, 0xbc, 0xd8, 0x10, 0x2f, 0x77, ++ 0xe6, 0x54, 0xe2, 0xd0, 0x39, 0x05, 0x84, 0xdf, 0x39, 0x62, 0xde, 0x79, ++ 0x85, 0x7c, 0xbd, 0xb6, 0xa4, 0x47, 0xc1, 0xc3, 0xbc, 0x3e, 0x7c, 0x57, ++ 0x74, 0x6e, 0xbb, 0xe6, 0xc7, 0xd1, 0xcf, 0xf3, 0xd1, 0xd2, 0x8a, 0x5b, ++ 0xf1, 0xfd, 0xc5, 0xe6, 0x6e, 0x99, 0xab, 0xb5, 0x28, 0x7c, 0xae, 0x32, ++ 0x76, 0x8f, 0x98, 0x01, 0x5d, 0x9f, 0xe9, 0x01, 0xb8, 0x64, 0x82, 0x33, ++ 0xaf, 0x10, 0xe5, 0xc2, 0x86, 0x32, 0x16, 0x24, 0x3d, 0xce, 0xe7, 0x57, ++ 0xfb, 0x94, 0xc4, 0x36, 0x65, 0x92, 0x5c, 0xaa, 0x22, 0x3d, 0x3e, 0xda, ++ 0xc0, 0x22, 0xcf, 0x31, 0xb5, 0xb4, 0xb8, 0x90, 0xcb, 0xdf, 0x97, 0x86, ++ 0xf3, 0xf7, 0xda, 0xec, 0x9e, 0x23, 0xc4, 0x8f, 0xfd, 0xf9, 0xc3, 0x47, ++ 0x66, 0x03, 0x3e, 0x9e, 0x33, 0xb0, 0x02, 0x3a, 0xbf, 0x35, 0xf0, 0xfd, ++ 0xb1, 0x16, 0x37, 0x23, 0xa3, 0x1f, 0x00, 0xd2, 0x9f, 0x14, 0x6a, 0xfe, ++ 0xd2, 0x16, 0x36, 0x09, 0xf5, 0xb6, 0xd3, 0x40, 0x71, 0xa0, 0x72, 0x47, ++ 0x0c, 0xdd, 0x4f, 0x95, 0x9d, 0x0a, 0xc5, 0x9f, 0xb7, 0xd8, 0x2a, 0x1d, ++ 0xf7, 0x62, 0x3f, 0x0e, 0x85, 0xce, 0x6b, 0x26, 0xc8, 0x63, 0xbb, 0xd1, ++ 0x8e, 0x36, 0x3b, 0x0d, 0x57, 0xa1, 0x1d, 0x7e, 0x78, 0xdb, 0x8f, 0xbb, ++ 0x31, 0x7e, 0x47, 0x4e, 0x57, 0x18, 0xfa, 0xbd, 0x5a, 0x1c, 0x0a, 0xb7, ++ 0x43, 0xd2, 0x0c, 0x14, 0x97, 0xa7, 0x38, 0x2b, 0x2d, 0x78, 0xbe, 0x93, ++ 0x67, 0x3b, 0x59, 0x8e, 0xf8, 0x3c, 0xd8, 0xf1, 0x43, 0x7a, 0x8f, 0x41, ++ 0x7e, 0x50, 0xc4, 0xce, 0x08, 0xbf, 0x98, 0x51, 0x90, 0xac, 0x85, 0x35, ++ 0x50, 0xff, 0xc1, 0x34, 0x45, 0xbc, 0xeb, 0xe2, 0xab, 0x1e, 0x95, 0x24, ++ 0x8e, 0x26, 0x54, 0xdc, 0x0f, 0x55, 0x7d, 0x82, 0xfb, 0xed, 0xc3, 0x8e, ++ 0xf3, 0x56, 0xdc, 0x17, 0xa8, 0xb6, 0xb9, 0xe4, 0x0f, 0xac, 0x2b, 0xe4, ++ 0xfb, 0x44, 0x23, 0x9e, 0xe3, 0x41, 0xfe, 0xa9, 0x25, 0xe7, 0x9d, 0x28, ++ 0xbf, 0x5e, 0xef, 0x58, 0xee, 0xca, 0x44, 0x7b, 0x3a, 0xa4, 0x90, 0x2d, ++ 0x52, 0xf0, 0x75, 0x73, 0x0a, 0xbd, 0x3b, 0xd0, 0x61, 0xa2, 0x77, 0x11, ++ 0x34, 0xbc, 0x66, 0x04, 0x15, 0xdd, 0x79, 0x60, 0x7a, 0xa3, 0x3e, 0x6f, ++ 0x8e, 0x3a, 0x17, 0x34, 0x46, 0xdd, 0x47, 0x9b, 0x85, 0xe3, 0x93, 0x9f, ++ 0x78, 0x1a, 0x0b, 0x47, 0xcc, 0xc7, 0xe8, 0xe1, 0xfb, 0x37, 0xe6, 0xb6, ++ 0xd1, 0xfe, 0xa7, 0xae, 0x50, 0xbc, 0x87, 0x29, 0xf2, 0x73, 0x30, 0x0f, ++ 0xa4, 0xd8, 0x69, 0x0c, 0xa6, 0x78, 0x01, 0x3f, 0x87, 0x3a, 0xe6, 0x66, ++ 0xe0, 0xbc, 0x2e, 0xbc, 0x14, 0xa0, 0xf8, 0xef, 0xc1, 0xec, 0xff, 0xd2, ++ 0x42, 0x55, 0x8c, 0x17, 0xb4, 0x1a, 0xe8, 0xfd, 0xdd, 0xb0, 0x15, 0xe3, ++ 0xc1, 0xb7, 0x37, 0x31, 0x2f, 0xda, 0x79, 0x96, 0x90, 0x42, 0xf1, 0xf8, ++ 0x3b, 0x84, 0x3c, 0xcb, 0xb1, 0x71, 0xfe, 0xf7, 0x17, 0x71, 0x3e, 0x8f, ++ 0x4e, 0x73, 0xda, 0xf8, 0xba, 0x53, 0x76, 0xc5, 0x84, 0x62, 0x91, 0x6e, ++ 0x8e, 0xce, 0x92, 0x20, 0xac, 0xf3, 0xc2, 0x57, 0x27, 0x32, 0x15, 0xf4, ++ 0x60, 0x8e, 0xc3, 0x67, 0x40, 0x7f, 0x7c, 0x4e, 0xa3, 0xc9, 0x8b, 0xf6, ++ 0xe7, 0x84, 0x5f, 0xda, 0x88, 0x4f, 0xce, 0xdb, 0x78, 0x3c, 0x95, 0xd2, ++ 0xf8, 0x88, 0x8a, 0xdf, 0x9b, 0xb7, 0x95, 0x15, 0x44, 0xde, 0xb3, 0x0b, ++ 0x35, 0x39, 0xbc, 0x28, 0x9f, 0xb6, 0x35, 0x59, 0xbc, 0x18, 0xa3, 0x1e, ++ 0x1a, 0x44, 0xbe, 0x66, 0x3b, 0x0d, 0x14, 0xc7, 0xae, 0x1a, 0x78, 0x5c, ++ 0x65, 0xbb, 0x58, 0x8f, 0xed, 0x85, 0xb1, 0x94, 0xae, 0x15, 0x72, 0xe6, ++ 0x69, 0x25, 0x38, 0x19, 0xe1, 0x7c, 0x1a, 0xe8, 0x89, 0xf1, 0xf3, 0x07, ++ 0x57, 0x73, 0xfb, 0x78, 0xd1, 0x52, 0x0b, 0xc1, 0xb1, 0xe8, 0xf5, 0x6c, ++ 0xb2, 0xaf, 0x06, 0xc3, 0xdb, 0x33, 0x4d, 0x1e, 0x6f, 0x0e, 0xc2, 0xb3, ++ 0xda, 0x90, 0x82, 0xfe, 0xaa, 0xf2, 0x95, 0x39, 0xab, 0xf0, 0x9d, 0x8c, ++ 0x45, 0x76, 0xfe, 0x8e, 0xb0, 0x1c, 0x3f, 0x9c, 0xfc, 0xb6, 0xec, 0x77, ++ 0x46, 0x86, 0xf6, 0x7c, 0x73, 0xdc, 0xb5, 0xde, 0x59, 0x11, 0xf2, 0x5d, ++ 0x8e, 0x1f, 0x5b, 0x80, 0x7c, 0x25, 0xcb, 0xc1, 0x14, 0xf4, 0xe7, 0xfc, ++ 0xbc, 0xf0, 0xdc, 0x6d, 0x18, 0x57, 0x0b, 0xf4, 0xdb, 0x84, 0xf9, 0xdd, ++ 0xcf, 0xfd, 0xe1, 0x36, 0x8c, 0xa3, 0xdd, 0x69, 0x0f, 0xa6, 0x60, 0x9c, ++ 0xed, 0x4b, 0xcf, 0xbd, 0xcf, 0xcb, 0x13, 0x83, 0x9b, 0x30, 0xce, 0xf6, ++ 0xe0, 0x73, 0xc7, 0x79, 0x79, 0x7a, 0x30, 0xc5, 0x00, 0xf9, 0xd7, 0x9f, ++ 0xfb, 0x90, 0x97, 0xe7, 0x06, 0x37, 0x61, 0xfe, 0xad, 0xe7, 0x4e, 0xf1, ++ 0x72, 0x3c, 0x03, 0x03, 0xd9, 0xf9, 0xde, 0x73, 0x9f, 0xde, 0x16, 0x44, ++ 0x7f, 0x8b, 0xc9, 0x3b, 0x1f, 0x05, 0xf2, 0x2f, 0x00, 0xfe, 0x22, 0x58, ++ 0x62, 0x9d, 0x22, 0xfd, 0x40, 0xe0, 0x45, 0x2b, 0x7f, 0x01, 0xbf, 0xc3, ++ 0x06, 0x6c, 0x8f, 0x48, 0xa3, 0xcb, 0xf7, 0x89, 0x76, 0xfb, 0x07, 0x29, ++ 0xff, 0x95, 0x28, 0xef, 0x1a, 0xa4, 0xff, 0x03, 0xa2, 0x5d, 0x78, 0x90, ++ 0xf6, 0x87, 0x44, 0xbb, 0xc3, 0x83, 0xb4, 0x3f, 0x22, 0xda, 0x1d, 0x1d, ++ 0xa4, 0xfc, 0xb7, 0xa2, 0xfc, 0x8d, 0x41, 0xfa, 0xff, 0x77, 0xd1, 0xae, ++ 0x7b, 0x90, 0xf6, 0x6f, 0x8b, 0x76, 0xef, 0x0e, 0xd2, 0xfe, 0x0f, 0xa2, ++ 0xdd, 0xb1, 0x41, 0xca, 0xdf, 0x17, 0xe5, 0xff, 0x19, 0xd5, 0xff, 0x71, ++ 0x51, 0xbf, 0x47, 0x7c, 0xcf, 0xb2, 0xaf, 0x7e, 0x1f, 0xfd, 0xf7, 0x59, ++ 0x20, 0x47, 0x50, 0x2e, 0x15, 0xd8, 0x57, 0xbb, 0x70, 0x9d, 0x6f, 0x6b, ++ 0x2d, 0x25, 0xfe, 0x6f, 0x2e, 0xe3, 0xe7, 0x54, 0x1a, 0xbf, 0x67, 0x49, ++ 0x8c, 0xde, 0xf7, 0xad, 0x2e, 0xe2, 0xef, 0x8a, 0x55, 0x17, 0x71, 0xf9, ++ 0xfb, 0x67, 0xd1, 0x3f, 0xf0, 0xe1, 0xe3, 0xc8, 0x77, 0x8b, 0xde, 0x94, ++ 0x29, 0xae, 0xa7, 0xd9, 0xe0, 0x3d, 0x1d, 0x42, 0x39, 0xba, 0xca, 0x40, ++ 0xf6, 0xc0, 0xa2, 0xd7, 0xf9, 0x7e, 0x7d, 0xd1, 0x4a, 0x25, 0x14, 0x79, ++ 0x2f, 0xe7, 0xcf, 0x51, 0xf0, 0x2f, 0x47, 0xf8, 0x80, 0x71, 0x5b, 0x30, ++ 0x85, 0xf5, 0x76, 0xa6, 0x90, 0xc7, 0xf5, 0x9b, 0x3d, 0x1e, 0x6f, 0x75, ++ 0x84, 0x3c, 0x33, 0x3a, 0xf4, 0x79, 0x90, 0x17, 0x0c, 0xe5, 0x2e, 0xc8, ++ 0x6f, 0x8a, 0xdf, 0x2e, 0x58, 0x59, 0xd1, 0x5a, 0x00, 0xf9, 0x54, 0x97, ++ 0x81, 0x2c, 0x10, 0xa5, 0xd6, 0x12, 0xc6, 0xf7, 0x3a, 0x14, 0xbb, 0xd0, ++ 0x0b, 0x8e, 0xd2, 0xb6, 0x02, 0x84, 0xcf, 0xa6, 0xd0, 0x3b, 0x05, 0x9a, ++ 0x9c, 0x67, 0x36, 0x8f, 0xce, 0xaf, 0xd1, 0x62, 0x53, 0xe8, 0xdd, 0x36, ++ 0xd9, 0xce, 0xcb, 0x27, 0xfc, 0x72, 0xac, 0x03, 0xed, 0xac, 0x16, 0x16, ++ 0xe8, 0xf6, 0x61, 0x7b, 0x8f, 0x42, 0x76, 0xfc, 0xc1, 0xd6, 0x12, 0x07, ++ 0xca, 0x3d, 0x93, 0x7d, 0xb6, 0x03, 0xd7, 0xef, 0xbb, 0xc5, 0x7c, 0x5e, ++ 0x95, 0x75, 0x05, 0x31, 0x28, 0xaf, 0xe5, 0x47, 0x0d, 0x24, 0xbf, 0x0f, ++ 0x3b, 0xf8, 0x7a, 0xdf, 0xea, 0xe1, 0xf1, 0x4e, 0xa0, 0x57, 0xe8, 0x9e, ++ 0x13, 0xc8, 0x6b, 0x2f, 0xea, 0x88, 0x7c, 0x16, 0x5e, 0x8a, 0x72, 0x73, ++ 0xe7, 0x63, 0xfb, 0x66, 0x70, 0x3f, 0x1f, 0xb3, 0x8f, 0x2a, 0xa3, 0x7b, ++ 0x44, 0xda, 0xf9, 0xb6, 0xa4, 0x44, 0xec, 0x03, 0xae, 0x2b, 0xe2, 0xf8, ++ 0xc9, 0x10, 0x7a, 0x44, 0x41, 0xfd, 0x02, 0xe9, 0xd3, 0xa5, 0xe2, 0xfe, ++ 0x4b, 0x90, 0xfb, 0xa3, 0x32, 0x14, 0xe6, 0x49, 0x8d, 0xb8, 0xc7, 0x7b, ++ 0x5d, 0x91, 0xcc, 0xef, 0x1f, 0x29, 0x88, 0x23, 0xe8, 0x4b, 0xae, 0xa6, ++ 0xf7, 0xab, 0x86, 0x2e, 0x51, 0x74, 0xe7, 0x08, 0x69, 0x0f, 0xe8, 0xf3, ++ 0xa6, 0x28, 0xbd, 0xa1, 0x44, 0xe9, 0x95, 0xec, 0x56, 0x90, 0x93, 0xba, ++ 0xf3, 0x13, 0x87, 0x2e, 0x5f, 0x54, 0x24, 0xfc, 0x3c, 0x5e, 0xe6, 0x45, ++ 0x3b, 0x76, 0xc2, 0x2f, 0x57, 0x93, 0x3c, 0x3c, 0x8f, 0xfa, 0x4d, 0x1a, ++ 0x5c, 0xee, 0xf5, 0xc9, 0x5f, 0x21, 0x8f, 0x9f, 0x46, 0x04, 0xa0, 0x1c, ++ 0x0d, 0xf2, 0x7b, 0xe4, 0x07, 0x57, 0x97, 0xfc, 0x16, 0xe9, 0xbd, 0x68, ++ 0xa5, 0x81, 0xde, 0x8d, 0xbe, 0x52, 0x39, 0xfa, 0x67, 0x84, 0x05, 0xf0, ++ 0x90, 0x1b, 0x90, 0x48, 0x2f, 0xc0, 0x84, 0x52, 0x70, 0xdf, 0x74, 0x39, ++ 0x3c, 0xe4, 0x1a, 0xfd, 0x2e, 0x7a, 0x57, 0xe3, 0x32, 0xf8, 0xc8, 0x5d, ++ 0x57, 0xea, 0x42, 0x79, 0x9b, 0x1b, 0x50, 0xa8, 0xff, 0x4b, 0xf4, 0xc6, ++ 0x65, 0xf0, 0xf5, 0xbc, 0xe4, 0x3d, 0x16, 0x40, 0x3a, 0x3a, 0x63, 0x84, ++ 0x5d, 0x0d, 0x0c, 0x80, 0x7e, 0x3b, 0x57, 0x4c, 0x07, 0xc6, 0x17, 0x9b, ++ 0x84, 0x3f, 0x45, 0x8b, 0x17, 0x56, 0x86, 0x28, 0xfc, 0x5d, 0x7c, 0x71, ++ 0x5f, 0x55, 0x16, 0x7c, 0xfc, 0x30, 0xf3, 0xa9, 0xae, 0x6c, 0x7c, 0x17, ++ 0xa8, 0x81, 0xfc, 0xfb, 0x8b, 0x77, 0x3f, 0xe0, 0x41, 0xbb, 0x7d, 0x85, ++ 0x21, 0xe0, 0xc0, 0xfc, 0x51, 0xd7, 0xa4, 0x5e, 0x1c, 0x67, 0x11, 0x6c, ++ 0xfa, 0x11, 0x7f, 0x3b, 0xb1, 0x0f, 0x7a, 0x1f, 0xf3, 0xb7, 0xb7, 0xfb, ++ 0x00, 0xfe, 0xce, 0x90, 0x49, 0x7b, 0xbf, 0x32, 0x8c, 0xff, 0xec, 0xc6, ++ 0x38, 0x20, 0xed, 0x7d, 0x4c, 0x0f, 0xd9, 0x6b, 0xa2, 0xfe, 0xb5, 0xb7, ++ 0x57, 0x02, 0xde, 0x3b, 0x15, 0x47, 0x21, 0x9a, 0xa0, 0x4b, 0x77, 0x5d, ++ 0xb7, 0xde, 0x78, 0x1d, 0xd4, 0x37, 0xb1, 0xbe, 0xfa, 0x78, 0xef, 0xee, ++ 0xb9, 0xc3, 0x06, 0xf1, 0x7e, 0xe6, 0xb8, 0xf5, 0x95, 0x20, 0x97, 0x76, ++ 0xc7, 0x30, 0xdd, 0xfb, 0xa0, 0xbb, 0xd1, 0xcf, 0x4e, 0xfd, 0x4d, 0x58, ++ 0x8f, 0xef, 0x81, 0xc2, 0x78, 0x37, 0xc9, 0xb0, 0x37, 0x5b, 0x5b, 0x74, ++ 0xf3, 0x7a, 0x5b, 0x72, 0x3f, 0x3c, 0xeb, 0x8a, 0xa7, 0xac, 0x5f, 0x8a, ++ 0x0e, 0x3b, 0xb1, 0x4f, 0x71, 0x32, 0xfe, 0xae, 0xfb, 0x19, 0xb5, 0x27, ++ 0x0e, 0x97, 0x0f, 0xec, 0x57, 0x7e, 0x52, 0x04, 0xf4, 0xad, 0xed, 0x38, ++ 0x99, 0x14, 0xb9, 0x5f, 0xd7, 0xea, 0xc7, 0x8b, 0xfa, 0x75, 0x5d, 0xbd, ++ 0x75, 0xbb, 0x54, 0xaa, 0xbf, 0x94, 0xea, 0xef, 0xef, 0x8d, 0x2b, 0x22, ++ 0x7c, 0xf7, 0x96, 0x45, 0xd6, 0x8f, 0x13, 0x7e, 0x80, 0x88, 0xfa, 0x2b, ++ 0xbe, 0xad, 0x7e, 0x81, 0x06, 0xcf, 0xae, 0xb7, 0x6f, 0x2f, 0xe2, 0xf5, ++ 0x1f, 0xc5, 0xfa, 0x67, 0xd5, 0x9e, 0x24, 0x8a, 0xad, 0x89, 0x82, 0x27, ++ 0xe1, 0xd2, 0xfe, 0xd7, 0x7e, 0x5b, 0xff, 0xc3, 0x45, 0xfd, 0x33, 0xe1, ++ 0xb7, 0xa9, 0xfe, 0x59, 0xd6, 0x93, 0x54, 0x9c, 0x49, 0xed, 0x36, 0x61, ++ 0xbb, 0x73, 0x6f, 0xbc, 0x5d, 0x26, 0xe6, 0x9d, 0x84, 0xe7, 0x38, 0xef, ++ 0xda, 0x7c, 0x4f, 0x16, 0x81, 0x5c, 0x6a, 0xc0, 0x3e, 0xd0, 0x7e, 0x56, ++ 0x1a, 0x54, 0xfc, 0xde, 0x69, 0x69, 0x73, 0xa0, 0xfd, 0x66, 0x35, 0xb6, ++ 0xf9, 0x51, 0x0e, 0xe7, 0xe0, 0x3b, 0x5f, 0x63, 0xfa, 0xd3, 0xad, 0xa8, ++ 0x3c, 0x46, 0x5f, 0xfa, 0x3d, 0x9a, 0x9f, 0x3b, 0x2d, 0x2c, 0xa1, 0x1a, ++ 0xf9, 0xb5, 0xd1, 0x40, 0xfb, 0x9b, 0xfd, 0x3d, 0x86, 0x47, 0x90, 0x2f, ++ 0xb7, 0xa6, 0x8d, 0x75, 0xe0, 0xfe, 0x79, 0xb7, 0xa9, 0xbb, 0xa4, 0x08, ++ 0xed, 0xd7, 0xbd, 0x36, 0xb2, 0x5f, 0x0d, 0x19, 0x9f, 0x59, 0xd1, 0x6f, ++ 0x6e, 0xce, 0xe7, 0xeb, 0xdf, 0xea, 0x6c, 0xf0, 0x16, 0x41, 0xde, 0x9a, ++ 0x5e, 0x44, 0xef, 0x74, 0xca, 0x0f, 0x2d, 0xea, 0xa4, 0xf7, 0xc2, 0x7f, ++ 0xca, 0xdf, 0xd1, 0x52, 0x7e, 0x66, 0x0a, 0x6c, 0x47, 0x7e, 0x0c, 0x2f, ++ 0x2a, 0x98, 0x13, 0xb1, 0xbe, 0xd7, 0x15, 0x1b, 0x09, 0xbe, 0x95, 0xaf, ++ 0xd9, 0x56, 0xe3, 0xfe, 0x60, 0xa5, 0xd1, 0xdb, 0x96, 0x8f, 0x76, 0xb8, ++ 0x5d, 0xa1, 0xf8, 0x4b, 0xe5, 0x67, 0xfb, 0x26, 0x91, 0x7d, 0xf8, 0x0b, ++ 0x03, 0x23, 0xf9, 0x0f, 0xf3, 0xac, 0x80, 0x7e, 0x5b, 0x66, 0x28, 0xf4, ++ 0xfb, 0x0e, 0x4e, 0x14, 0xcf, 0x3c, 0x58, 0x44, 0xf8, 0xf0, 0xfb, 0x2b, ++ 0xa0, 0xde, 0xd0, 0x44, 0x45, 0xc2, 0x7b, 0x3a, 0x0f, 0x2b, 0x7e, 0x0b, ++ 0x9e, 0x77, 0x98, 0x85, 0x5d, 0xb7, 0xd5, 0xcb, 0xef, 0x69, 0x69, 0xe3, ++ 0x7e, 0x2c, 0xec, 0xcf, 0x8f, 0x8b, 0xf8, 0xbb, 0xee, 0x5b, 0xd3, 0x2e, ++ 0xbc, 0x37, 0xcf, 0x8d, 0xef, 0x30, 0x98, 0xe8, 0x7e, 0xa5, 0x6d, 0xa1, ++ 0x21, 0x6c, 0x8a, 0xc3, 0xfb, 0x66, 0xdb, 0x4e, 0xcf, 0x43, 0x7a, 0xc6, ++ 0xf6, 0xac, 0xc4, 0xfb, 0xc6, 0x31, 0x29, 0x8a, 0x03, 0xe7, 0xf7, 0x64, ++ 0x35, 0x94, 0xd1, 0xb9, 0x5c, 0x27, 0x7d, 0x0f, 0xd6, 0x1a, 0x68, 0xdf, ++ 0x90, 0xb0, 0xd0, 0xe0, 0x43, 0xff, 0x63, 0x4c, 0x8e, 0x49, 0xe7, 0xef, ++ 0xb0, 0xc1, 0x38, 0x91, 0xfe, 0x90, 0x6f, 0x8a, 0x03, 0xc7, 0x10, 0xee, ++ 0xab, 0xde, 0x54, 0x6e, 0x42, 0x3c, 0x7b, 0xee, 0x37, 0xd0, 0x3b, 0xa4, ++ 0x8f, 0x7a, 0xde, 0xb5, 0x18, 0x00, 0xce, 0xb8, 0x52, 0x7d, 0x7b, 0xc7, ++ 0x58, 0x7d, 0x7b, 0x57, 0xa5, 0xbe, 0xdc, 0x5d, 0xad, 0x2f, 0x4f, 0x9a, ++ 0xaa, 0x2f, 0xf7, 0xdc, 0x6d, 0x8a, 0xf2, 0xeb, 0xe8, 0xf3, 0x33, 0x34, ++ 0xbe, 0x02, 0x99, 0x60, 0x03, 0x3d, 0x15, 0xc3, 0x8b, 0x58, 0x8c, 0xed, ++ 0x42, 0x13, 0xee, 0x7b, 0x56, 0xbc, 0x16, 0xc3, 0x88, 0x3e, 0x4b, 0xd6, ++ 0xb7, 0xe5, 0xe3, 0xfa, 0x8c, 0xed, 0x25, 0x7c, 0xc5, 0x0c, 0x8f, 0x21, ++ 0xbf, 0xc0, 0x8a, 0x64, 0x13, 0xc9, 0xf5, 0x15, 0xc5, 0xdc, 0xaf, 0x7f, ++ 0x28, 0xdd, 0x74, 0x13, 0xe5, 0x61, 0x5e, 0xc8, 0x1f, 0x5b, 0xd3, 0x8e, ++ 0xd0, 0x7e, 0xe4, 0x12, 0xbc, 0xd8, 0x4e, 0x7f, 0x8d, 0xfd, 0xdb, 0x58, ++ 0xc4, 0x77, 0xb4, 0x33, 0x8a, 0x7d, 0x7f, 0x29, 0x1a, 0xcd, 0xf3, 0x9e, ++ 0x32, 0xf4, 0xe3, 0x31, 0x92, 0x87, 0xcf, 0x4b, 0x3e, 0xef, 0x41, 0xc4, ++ 0xf7, 0x5b, 0xdc, 0x5f, 0xb1, 0xb5, 0x91, 0xfb, 0xb1, 0x1f, 0x9d, 0xca, ++ 0xe3, 0x11, 0x69, 0x06, 0x65, 0xb8, 0xde, 0x79, 0xfd, 0x38, 0xcb, 0xea, ++ 0x6e, 0xdc, 0x97, 0xc5, 0xd9, 0x5a, 0xef, 0xc7, 0x38, 0xcb, 0x68, 0xbc, ++ 0x26, 0x89, 0xf3, 0x86, 0xad, 0x78, 0xcb, 0x16, 0xf9, 0x2e, 0xc0, 0xdf, ++ 0x67, 0x5e, 0xae, 0xdd, 0x77, 0xc2, 0xef, 0x65, 0x74, 0x7b, 0x81, 0xde, ++ 0x1f, 0x1b, 0x3f, 0x82, 0xf3, 0x8b, 0x53, 0xd8, 0x09, 0xf1, 0x9e, 0x84, ++ 0xa2, 0x96, 0x88, 0x7b, 0x13, 0x49, 0xc2, 0x6f, 0xf2, 0xf8, 0xd8, 0x99, ++ 0x56, 0xd4, 0x1f, 0xbb, 0xc5, 0x7b, 0x1e, 0x7d, 0xfd, 0xa9, 0x34, 0x28, ++ 0x0f, 0x3d, 0x45, 0xbf, 0x72, 0xb1, 0x24, 0xf6, 0x53, 0xbc, 0xfd, 0x7a, ++ 0xed, 0x9c, 0x47, 0xe4, 0x13, 0x9d, 0x3c, 0xbf, 0xfb, 0xb0, 0xeb, 0x26, ++ 0x5c, 0x5f, 0xeb, 0xa7, 0xba, 0x4a, 0x70, 0xbf, 0xbf, 0x42, 0xd8, 0x77, ++ 0xf1, 0x69, 0x26, 0xdf, 0x30, 0x98, 0xd7, 0xda, 0xa3, 0xa6, 0xa0, 0x34, ++ 0x12, 0xf2, 0x0a, 0x3b, 0x6c, 0x04, 0xbb, 0x60, 0xb7, 0x8b, 0x8f, 0x6b, ++ 0x7a, 0x3d, 0x26, 0x88, 0xf7, 0xf3, 0xd6, 0x7a, 0x4a, 0xe9, 0xbe, 0xdf, ++ 0x75, 0x62, 0xbc, 0x17, 0xca, 0xbd, 0xef, 0xe0, 0x7a, 0xef, 0x85, 0x75, ++ 0x84, 0x71, 0x5f, 0x6b, 0xdd, 0x5e, 0x6b, 0x89, 0x38, 0x37, 0x0d, 0x02, ++ 0x7c, 0x68, 0x5a, 0xe0, 0x3e, 0xe5, 0x60, 0x75, 0x09, 0xed, 0x77, 0xd7, ++ 0xfa, 0xbc, 0x56, 0xd4, 0x9b, 0x6b, 0xd3, 0xbc, 0x56, 0x8c, 0x97, 0xb6, ++ 0x26, 0x2b, 0x0e, 0x8c, 0x07, 0x75, 0x79, 0x14, 0x7a, 0x8f, 0x6d, 0xad, ++ 0x25, 0xe0, 0x40, 0xfb, 0xc7, 0x05, 0x8a, 0xd4, 0x84, 0xe7, 0x49, 0xe9, ++ 0x6d, 0x13, 0xe9, 0x9e, 0x1b, 0xe0, 0xda, 0x50, 0xc6, 0x8f, 0x1a, 0x98, ++ 0x88, 0x33, 0xc4, 0x38, 0xbf, 0x04, 0x81, 0xcf, 0xad, 0x9e, 0xd9, 0x0e, ++ 0x7c, 0x1f, 0xc1, 0x9d, 0xb3, 0xe7, 0x47, 0xe8, 0xa7, 0x4f, 0xc0, 0xfe, ++ 0xe2, 0x78, 0x3b, 0xc4, 0x93, 0x53, 0xe0, 0x69, 0x7c, 0xb1, 0x4a, 0x70, ++ 0xbb, 0x45, 0xff, 0x09, 0xb3, 0x5f, 0xa0, 0xfa, 0xf8, 0xd3, 0x52, 0x16, ++ 0xd1, 0x9f, 0xa0, 0xa3, 0x69, 0x22, 0x0b, 0xe1, 0x3e, 0x4d, 0x1b, 0x5f, ++ 0xeb, 0xa7, 0xaf, 0x7f, 0xe6, 0xa3, 0x73, 0x80, 0xe5, 0xbf, 0xe5, 0x78, ++ 0x5b, 0x9a, 0xce, 0xdf, 0xa1, 0x32, 0xdd, 0xc7, 0x68, 0x3f, 0xf7, 0x42, ++ 0x79, 0x60, 0x27, 0xf2, 0x59, 0x6f, 0x72, 0x0c, 0xc9, 0xbb, 0x14, 0x4f, ++ 0x4a, 0x05, 0xf2, 0x51, 0xca, 0xd1, 0x4d, 0x93, 0xf1, 0xfe, 0xc3, 0xf2, ++ 0xdf, 0xc6, 0xf0, 0x71, 0xe6, 0x70, 0x7e, 0x4f, 0x51, 0x98, 0xe5, 0x7a, ++ 0x9c, 0x77, 0x62, 0xc0, 0x81, 0x78, 0x8c, 0x5e, 0xaf, 0xc9, 0x87, 0xdb, ++ 0x6a, 0x90, 0x29, 0x35, 0xba, 0x44, 0xaf, 0xdf, 0x64, 0x85, 0xb5, 0xca, ++ 0xae, 0x4b, 0xd7, 0x71, 0xb2, 0xc7, 0x5d, 0x91, 0x37, 0x62, 0x80, 0xf5, ++ 0x1c, 0xb5, 0x5e, 0x92, 0x8f, 0xf6, 0x3e, 0x88, 0xfd, 0x47, 0xaf, 0xeb, ++ 0x2d, 0xb1, 0xc7, 0x47, 0x71, 0x3d, 0x12, 0xf1, 0x5d, 0xbe, 0x7c, 0xbe, ++ 0x45, 0xea, 0x59, 0x49, 0x72, 0x38, 0x59, 0xa1, 0x75, 0x96, 0x1e, 0x35, ++ 0x1e, 0xbe, 0x67, 0x87, 0x79, 0x89, 0x19, 0x54, 0x8c, 0x4f, 0x5e, 0x57, ++ 0xec, 0xd4, 0xde, 0xad, 0x52, 0x11, 0xaf, 0xbb, 0x4d, 0x8e, 0x71, 0x36, ++ 0x7e, 0xde, 0x4e, 0xfc, 0x55, 0xf1, 0xe2, 0xea, 0xbb, 0x7e, 0x07, 0xf9, ++ 0x0b, 0xf8, 0x7b, 0x73, 0xa0, 0x56, 0xea, 0xd1, 0xb6, 0x6e, 0xd2, 0x8b, ++ 0xfb, 0x03, 0xf9, 0x58, 0x7f, 0xb3, 0x12, 0x78, 0x0a, 0xfd, 0xe9, 0x9b, ++ 0x8f, 0x0d, 0xa1, 0x77, 0x22, 0xcd, 0xb1, 0xfc, 0x9d, 0x4f, 0x53, 0xd4, ++ 0xbb, 0x25, 0x9a, 0xbe, 0x58, 0x57, 0xcc, 0xf7, 0x31, 0x6a, 0xd4, 0xfb, ++ 0x96, 0xdf, 0x35, 0xed, 0x4c, 0x4b, 0x2b, 0x74, 0x00, 0xcf, 0xac, 0x7b, ++ 0xfe, 0xb7, 0x7f, 0xb0, 0x24, 0xfe, 0xe3, 0xed, 0x9f, 0xb4, 0xc3, 0x9d, ++ 0x4b, 0x6d, 0xb0, 0xa6, 0xb7, 0xec, 0xba, 0x65, 0x3d, 0xc6, 0x47, 0x5a, ++ 0xdf, 0xe4, 0xe5, 0x9b, 0x21, 0x1f, 0x54, 0x10, 0x2f, 0x0b, 0xc9, 0xef, ++ 0x72, 0x68, 0xe8, 0xbd, 0x34, 0xff, 0xe6, 0xf7, 0xcc, 0xe4, 0xcf, 0x2a, ++ 0x96, 0xbd, 0x1b, 0x30, 0xcf, 0x3e, 0xb0, 0x92, 0x3f, 0x6e, 0xe7, 0xde, ++ 0xb1, 0xd3, 0x70, 0x9d, 0x34, 0xdb, 0xcb, 0x54, 0xb4, 0xf7, 0x9f, 0x11, ++ 0xf2, 0x67, 0xbb, 0x58, 0xcf, 0xd1, 0xf3, 0x92, 0x4d, 0xde, 0x00, 0xda, ++ 0x03, 0xd1, 0xdf, 0xb7, 0x16, 0x8b, 0x73, 0x09, 0xe6, 0x3d, 0xd6, 0x01, ++ 0xf4, 0x2d, 0x7e, 0xda, 0x44, 0xef, 0x25, 0xf5, 0xc5, 0x47, 0x74, 0x58, ++ 0xf9, 0xef, 0x33, 0x13, 0x76, 0xe8, 0x6c, 0x21, 0xcf, 0x66, 0xef, 0x5b, ++ 0x35, 0xf4, 0x20, 0xc3, 0xf7, 0x30, 0x6a, 0xf6, 0x15, 0xc3, 0xb8, 0xb3, ++ 0xed, 0x95, 0x49, 0x08, 0x4f, 0xea, 0x45, 0x89, 0x05, 0x40, 0xfe, 0x6d, ++ 0x16, 0xe7, 0xb3, 0xa9, 0xee, 0x17, 0x24, 0x94, 0x33, 0x69, 0xee, 0xc3, ++ 0xe5, 0x28, 0xef, 0xd3, 0x59, 0xf7, 0x52, 0x94, 0x1b, 0xe9, 0x0d, 0xfa, ++ 0xf3, 0xb2, 0xd4, 0x8b, 0x0a, 0xb5, 0xdb, 0x9d, 0xe2, 0xa3, 0xfe, 0xf0, ++ 0x07, 0xef, 0x39, 0x9b, 0x98, 0x58, 0xd3, 0xae, 0x00, 0x5b, 0x8a, 0x72, ++ 0x3e, 0x85, 0x9f, 0xb7, 0x98, 0x1c, 0x31, 0xfc, 0x7e, 0xba, 0xa7, 0x52, ++ 0x77, 0x9f, 0x59, 0x7b, 0x47, 0xf6, 0x55, 0x81, 0x0f, 0x13, 0xe0, 0xd4, ++ 0x58, 0x02, 0xa9, 0x4d, 0xe1, 0xf7, 0xe7, 0xa3, 0xea, 0x1f, 0x15, 0xf8, ++ 0x92, 0xd1, 0x6f, 0x8f, 0xce, 0x7f, 0xc7, 0x91, 0x63, 0xd4, 0xaf, 0x4d, ++ 0xf9, 0x2c, 0xf2, 0x5d, 0x16, 0xdc, 0x97, 0x92, 0xd0, 0x5a, 0xc8, 0xcf, ++ 0x3f, 0x01, 0x4f, 0x41, 0xdc, 0x87, 0xb2, 0x78, 0x17, 0x3f, 0x2f, 0xf5, ++ 0xf9, 0xd4, 0xc8, 0xb8, 0xd6, 0x54, 0x90, 0xbb, 0xe6, 0x12, 0x8c, 0x3f, ++ 0x09, 0x52, 0x9c, 0x48, 0xb2, 0xb8, 0x9f, 0xa0, 0xc5, 0xf5, 0x00, 0x06, ++ 0x9c, 0xe8, 0x77, 0xd3, 0xe2, 0x3e, 0xb6, 0x31, 0xbd, 0x3d, 0xa2, 0xa5, ++ 0xda, 0xfe, 0x3c, 0xa7, 0x51, 0xa6, 0x7d, 0x47, 0xe1, 0xab, 0x56, 0xbe, ++ 0x3f, 0x68, 0x65, 0x21, 0xab, 0x84, 0xfe, 0x30, 0x46, 0x72, 0x27, 0x67, ++ 0x35, 0x3f, 0x9f, 0xd6, 0xfc, 0x62, 0xd5, 0xb8, 0x98, 0x68, 0x3d, 0x38, ++ 0x0c, 0x3c, 0xfe, 0xa7, 0x93, 0xe2, 0x99, 0x35, 0xbb, 0x0a, 0xe8, 0x4b, ++ 0x72, 0x67, 0x65, 0xd4, 0x7b, 0x4f, 0xda, 0x7b, 0xd5, 0x5f, 0x88, 0xf5, ++ 0xb4, 0xb9, 0xc9, 0x41, 0x74, 0xd4, 0xca, 0xd3, 0x02, 0xd1, 0x74, 0xd4, ++ 0x9f, 0x73, 0x6a, 0xf5, 0x52, 0x2f, 0xa6, 0xb2, 0x40, 0x42, 0x64, 0xbf, ++ 0x21, 0xea, 0x37, 0xb5, 0x71, 0x0f, 0xf1, 0x43, 0xea, 0xc5, 0xa1, 0x54, ++ 0xbe, 0xb9, 0x49, 0xbd, 0x4c, 0xff, 0x59, 0x83, 0xf4, 0x9f, 0x4c, 0xfc, ++ 0x32, 0x78, 0xff, 0x69, 0x54, 0xbe, 0x25, 0xfc, 0xae, 0xf3, 0x16, 0x40, ++ 0xc5, 0x93, 0xbd, 0x7b, 0x9c, 0x7e, 0x15, 0xe5, 0x4a, 0x78, 0xa2, 0x77, ++ 0x00, 0x3c, 0xa7, 0x3e, 0xa0, 0x97, 0x93, 0x23, 0xf7, 0xeb, 0xe5, 0xae, ++ 0x86, 0x97, 0xcd, 0x8a, 0xcf, 0x5d, 0x03, 0xf8, 0xde, 0xfc, 0x80, 0xc1, ++ 0xdb, 0xc1, 0x30, 0xfe, 0x54, 0x5f, 0xaf, 0x2a, 0xf3, 0xf7, 0x4e, 0xfe, ++ 0x7e, 0xb4, 0x56, 0x3f, 0xec, 0x9e, 0x82, 0xf5, 0x17, 0xf2, 0xfa, 0xdf, ++ 0x3b, 0xad, 0xaf, 0xef, 0x2f, 0xdf, 0x1b, 0x5d, 0x9f, 0xe0, 0xbb, 0xe1, ++ 0x62, 0x94, 0x7d, 0x18, 0x45, 0x9f, 0x68, 0x78, 0x01, 0xae, 0xc4, 0xdb, ++ 0x22, 0xe0, 0x1a, 0x67, 0xd1, 0xff, 0xfe, 0xb8, 0x69, 0x33, 0x2e, 0x81, ++ 0x2b, 0xf1, 0x8e, 0x08, 0xb8, 0x6e, 0xf4, 0xe8, 0xeb, 0x07, 0x96, 0x0e, ++ 0x0c, 0xd7, 0x4d, 0x05, 0xe6, 0x6f, 0x85, 0x4b, 0xab, 0x77, 0xeb, 0x98, ++ 0x2b, 0xab, 0x17, 0x3d, 0x8f, 0x29, 0x55, 0xe6, 0x41, 0xf0, 0xce, 0xeb, ++ 0xdf, 0x31, 0xed, 0xca, 0xfa, 0xfd, 0xfe, 0xfc, 0x6f, 0xaf, 0x77, 0x4f, ++ 0x63, 0xf4, 0x38, 0x41, 0xed, 0xfc, 0x48, 0x67, 0x8f, 0x24, 0x34, 0x72, ++ 0xfb, 0xdd, 0xc1, 0x7a, 0x29, 0xce, 0x44, 0xb3, 0x3b, 0x5c, 0xcc, 0x21, ++ 0xe2, 0xbf, 0xb8, 0xdd, 0xf0, 0x0e, 0xfe, 0x17, 0xf6, 0xb3, 0x4b, 0x46, ++ 0xf8, 0x6f, 0x1d, 0x31, 0x1a, 0xf1, 0xef, 0xbb, 0x7b, 0x9d, 0x8a, 0xf7, ++ 0x54, 0xb8, 0xbe, 0x62, 0xd5, 0xfc, 0x7d, 0x48, 0xd8, 0x97, 0x14, 0x47, ++ 0xbe, 0x7f, 0xdd, 0x0f, 0xd7, 0x32, 0xea, 0xf7, 0x65, 0x8c, 0x77, 0x22, ++ 0x3d, 0x6b, 0xf1, 0xa2, 0xdd, 0x59, 0x98, 0xca, 0x2c, 0xc9, 0x68, 0x7c, ++ 0x79, 0x42, 0x59, 0xf8, 0x0e, 0xd8, 0xf4, 0x11, 0x9a, 0xbc, 0xe6, 0xf1, ++ 0xe5, 0xc3, 0x05, 0xee, 0x9e, 0x4f, 0xe9, 0x5c, 0xe4, 0xa4, 0x75, 0x1e, ++ 0x72, 0x21, 0x3c, 0xdf, 0x75, 0xdc, 0x7b, 0x47, 0xf8, 0xe6, 0x8c, 0x48, ++ 0xec, 0xaf, 0x3f, 0x98, 0xbf, 0x45, 0xc3, 0x93, 0xc9, 0xd4, 0x49, 0xbf, ++ 0x3f, 0xa1, 0xb7, 0xd6, 0xe6, 0x45, 0xfd, 0xf0, 0x2e, 0x16, 0x41, 0xbb, ++ 0xa7, 0x6f, 0x37, 0x87, 0xd1, 0xae, 0xd6, 0xe2, 0x50, 0x8f, 0xc5, 0x4e, ++ 0x3f, 0x92, 0xa8, 0xd2, 0xfb, 0x03, 0x8b, 0xb1, 0xff, 0x69, 0x77, 0x4c, ++ 0x5c, 0x8e, 0x79, 0xe9, 0x50, 0x82, 0xba, 0xc8, 0x86, 0xf7, 0x97, 0x7a, ++ 0xb4, 0x7b, 0x9e, 0x3f, 0x42, 0xbc, 0x2d, 0xb4, 0x04, 0x32, 0x92, 0x0c, ++ 0x74, 0xbe, 0x9a, 0x8f, 0xfb, 0x61, 0xe6, 0x4f, 0x10, 0x97, 0x82, 0xfd, ++ 0xc5, 0x03, 0xc5, 0x69, 0x68, 0xf0, 0x54, 0x4a, 0x1c, 0xff, 0x31, 0x69, ++ 0x81, 0x20, 0xf6, 0x53, 0x69, 0xe8, 0xde, 0xea, 0xc7, 0x6f, 0x4a, 0x37, ++ 0xdf, 0x67, 0x3b, 0x12, 0xf9, 0xfb, 0x47, 0xf8, 0xce, 0xcd, 0x00, 0xeb, ++ 0x5f, 0xc3, 0x43, 0x85, 0xe8, 0xe7, 0xa0, 0xd1, 0xfb, 0x55, 0x2f, 0xcc, ++ 0xef, 0xe0, 0x9a, 0x78, 0xba, 0x0f, 0x3f, 0x3b, 0xe1, 0x8e, 0xe9, 0xf8, ++ 0x36, 0xca, 0x1c, 0x83, 0x3f, 0x09, 0x0f, 0xd0, 0x23, 0xe0, 0x7e, 0x8c, ++ 0xe0, 0xb6, 0xcd, 0xc8, 0x48, 0x46, 0xb8, 0x8d, 0x02, 0x6e, 0x4b, 0xa2, ++ 0xc0, 0xbb, 0x2f, 0xe7, 0xdb, 0xe0, 0xee, 0x8b, 0x97, 0xf9, 0xa9, 0xa4, ++ 0xbd, 0x53, 0x4e, 0xf9, 0x17, 0x83, 0x4e, 0xba, 0x77, 0x6e, 0x36, 0x7c, ++ 0xf1, 0xee, 0x14, 0xd4, 0xc3, 0xc5, 0x06, 0x2f, 0xda, 0x9d, 0x9b, 0xc1, ++ 0xbe, 0xc0, 0x77, 0xd6, 0xfe, 0x8f, 0xc0, 0xf7, 0x16, 0x3c, 0x63, 0x71, ++ 0xd1, 0x77, 0x7a, 0x7f, 0xcd, 0x23, 0xee, 0x5f, 0x79, 0xd6, 0x1b, 0xe8, ++ 0xbd, 0x15, 0x7f, 0xc5, 0x4b, 0x44, 0xa7, 0xa7, 0xeb, 0x6c, 0x5e, 0xdc, ++ 0xb7, 0xcf, 0x60, 0x2a, 0xbd, 0x6f, 0x3a, 0x4b, 0xdc, 0x47, 0xf9, 0x63, ++ 0xf9, 0x7f, 0xbf, 0xd2, 0x03, 0xf3, 0xdb, 0x35, 0x22, 0xf0, 0x2c, 0xd2, ++ 0xe7, 0x9e, 0x04, 0xc3, 0xd0, 0x77, 0x09, 0x8e, 0x40, 0x21, 0xbd, 0x67, ++ 0x35, 0xf6, 0xca, 0xe2, 0x67, 0xb5, 0x73, 0xf8, 0xc9, 0xc2, 0x3e, 0x98, ++ 0x23, 0xf0, 0x38, 0x85, 0xf9, 0x28, 0x6e, 0xf7, 0x36, 0x16, 0x30, 0xe2, ++ 0xb8, 0x6f, 0x9f, 0x35, 0xf9, 0xd0, 0x2e, 0x7d, 0x5b, 0xc4, 0x23, 0xdf, ++ 0xc1, 0x82, 0xf4, 0xfd, 0x4e, 0x16, 0xa2, 0xf4, 0xfb, 0x2c, 0x4c, 0xf5, ++ 0x7f, 0x80, 0x2f, 0xb7, 0x42, 0xfe, 0xad, 0xd8, 0x11, 0xe9, 0x8d, 0x00, ++ 0x5f, 0xcd, 0x13, 0xf9, 0xb9, 0xb8, 0x1e, 0x23, 0xf0, 0xfe, 0x8a, 0xe0, ++ 0x97, 0x7b, 0xdc, 0x9c, 0x5f, 0x3e, 0x1e, 0x82, 0x78, 0x6f, 0x4f, 0xbc, ++ 0x22, 0xfe, 0xad, 0x91, 0x38, 0xfe, 0x96, 0x8c, 0x08, 0x1c, 0xc1, 0x79, ++ 0x8f, 0xb3, 0xa8, 0x6e, 0x2f, 0xc2, 0xe4, 0x18, 0x97, 0x86, 0x7e, 0x94, ++ 0xbe, 0xf5, 0x53, 0x99, 0xc8, 0xf9, 0x4f, 0x71, 0xe4, 0x7e, 0xdb, 0xfa, ++ 0xe9, 0x3e, 0xaf, 0xdd, 0xbb, 0xf7, 0xd9, 0x92, 0xcb, 0xf0, 0xdd, 0x2d, ++ 0xfe, 0x73, 0xa3, 0xef, 0x3e, 0x8a, 0x17, 0xc7, 0xb8, 0x7c, 0x37, 0xd0, ++ 0xa1, 0x5b, 0xe5, 0xf7, 0x0d, 0x41, 0x6c, 0xd8, 0x83, 0x40, 0xa7, 0xaa, ++ 0x72, 0x99, 0xe2, 0xf6, 0x56, 0x7c, 0x2e, 0xee, 0x49, 0xa3, 0x13, 0x03, ++ 0xea, 0xfd, 0x66, 0x94, 0x4c, 0xef, 0x84, 0x69, 0xe7, 0x92, 0xb7, 0x88, ++ 0xfe, 0x6e, 0x49, 0xe3, 0xf7, 0x06, 0xab, 0xcb, 0xa7, 0xb4, 0xc4, 0x03, ++ 0x5e, 0x26, 0x7c, 0xd5, 0x53, 0x1a, 0x86, 0xb4, 0x2a, 0x4d, 0x7f, 0x8f, ++ 0x70, 0xa2, 0xbb, 0x83, 0x9e, 0x0e, 0x9f, 0x94, 0xa3, 0xff, 0x7e, 0x13, ++ 0x6b, 0xa3, 0x03, 0xe2, 0xea, 0x22, 0x7d, 0x9c, 0xf9, 0x2d, 0x51, 0xfe, ++ 0xcf, 0x83, 0x38, 0x36, 0xf0, 0xd5, 0x27, 0x23, 0x44, 0xbc, 0xe4, 0x70, ++ 0x36, 0x3c, 0xf2, 0xbe, 0xc1, 0xad, 0xa2, 0xed, 0xf9, 0xea, 0x2f, 0x4c, ++ 0xe7, 0x60, 0xfc, 0xf4, 0x91, 0x81, 0x5e, 0xc4, 0xe3, 0xa2, 0x9b, 0xff, ++ 0x38, 0x9d, 0xf6, 0x75, 0x0a, 0x7b, 0xf3, 0x2a, 0x98, 0x5f, 0xdd, 0xbf, ++ 0xcb, 0x64, 0x4f, 0x7e, 0xd8, 0x04, 0x33, 0xc9, 0xc7, 0xb8, 0x6a, 0x0b, ++ 0xf3, 0x81, 0xc1, 0x7f, 0x0a, 0xec, 0x0a, 0xcc, 0x9f, 0x6e, 0xf2, 0x50, ++ 0xfa, 0x29, 0xd8, 0x01, 0x98, 0x7e, 0xd6, 0x54, 0x40, 0xe5, 0x67, 0x9b, ++ 0xbc, 0x94, 0x1f, 0x3f, 0xd2, 0xff, 0x17, 0xa4, 0xf3, 0xcc, 0xd6, 0xcf, ++ 0x15, 0xd4, 0x47, 0x2b, 0xb4, 0x78, 0x6c, 0x01, 0x87, 0x16, 0x57, 0xb8, ++ 0x42, 0xc4, 0x4f, 0x2c, 0xb6, 0x2f, 0x3a, 0x86, 0xf1, 0x0b, 0x8b, 0x29, ++ 0xe0, 0x9d, 0xc1, 0x62, 0x6f, 0x9b, 0x80, 0xe0, 0xdf, 0xbb, 0xbf, 0xf3, ++ 0x08, 0xa6, 0xf0, 0x5d, 0xc6, 0x7d, 0xc8, 0xe2, 0x35, 0x12, 0xf9, 0x75, ++ 0xe6, 0x1c, 0x0e, 0x2c, 0x47, 0x32, 0xcf, 0x7b, 0xa3, 0xe7, 0x16, 0x14, ++ 0x13, 0xa3, 0x7f, 0x7f, 0x32, 0x09, 0xf7, 0xe9, 0xb5, 0x68, 0xc7, 0x02, ++ 0xeb, 0x2f, 0x76, 0xf9, 0x2c, 0x23, 0x61, 0x7c, 0x5f, 0xd7, 0x89, 0x23, ++ 0x09, 0x50, 0xff, 0xe3, 0xa6, 0x31, 0x04, 0xdf, 0x27, 0x4d, 0x3e, 0x82, ++ 0xef, 0x4f, 0x4d, 0x55, 0x94, 0x4e, 0x1f, 0xe9, 0x8f, 0xa3, 0x7a, 0xec, ++ 0x73, 0x7a, 0x6f, 0xe9, 0xe6, 0x5d, 0x27, 0x14, 0xfc, 0x3d, 0x68, 0xe3, ++ 0x7d, 0x12, 0xf9, 0xef, 0xaf, 0xf7, 0xb1, 0x50, 0x08, 0xf0, 0xba, 0xc1, ++ 0xc8, 0xe5, 0xfb, 0x06, 0x90, 0xef, 0xb8, 0x3e, 0xcb, 0x8b, 0x27, 0x6f, ++ 0x79, 0x00, 0xe1, 0x1b, 0x11, 0xf0, 0x8c, 0x04, 0xfc, 0xdd, 0xe6, 0x9a, ++ 0x35, 0x3e, 0x01, 0xbe, 0xdf, 0x32, 0x66, 0x86, 0x82, 0xf5, 0xee, 0xf8, ++ 0x0a, 0x74, 0x50, 0x66, 0x3f, 0x1f, 0x5e, 0x8e, 0xaf, 0xcf, 0x1c, 0x90, ++ 0x08, 0x3f, 0x67, 0x0e, 0x38, 0x09, 0x1f, 0x1a, 0x9e, 0x6a, 0x05, 0xbd, ++ 0xce, 0xec, 0x2b, 0xbc, 0x15, 0xdf, 0x1f, 0x3b, 0x70, 0x54, 0xa6, 0xf8, ++ 0xd3, 0xf3, 0x17, 0x0d, 0x04, 0xdf, 0xf9, 0x63, 0x31, 0x14, 0x9f, 0x1a, ++ 0xdd, 0x7e, 0xd1, 0xde, 0xec, 0x21, 0x68, 0x8f, 0xfd, 0x09, 0xe8, 0x87, ++ 0x07, 0x1f, 0x8b, 0xf6, 0x16, 0x92, 0x3f, 0xfe, 0x4f, 0xcf, 0xff, 0x48, ++ 0x8d, 0x8c, 0xfb, 0xfd, 0x93, 0xab, 0xf3, 0xc2, 0xfb, 0x28, 0xa7, 0xfe, ++ 0x8b, 0xcb, 0x29, 0xb0, 0x37, 0x4f, 0x6d, 0x42, 0x39, 0x96, 0x96, 0x42, ++ 0xef, 0xe8, 0xf4, 0xc5, 0xab, 0xb1, 0x86, 0x58, 0xd4, 0x63, 0x75, 0x26, ++ 0xb1, 0xbe, 0x40, 0xce, 0x60, 0xfe, 0x4f, 0x31, 0x7c, 0x1f, 0x5c, 0xf6, ++ 0x8b, 0xd4, 0x0a, 0x5c, 0x2f, 0x38, 0x1e, 0xc6, 0x7b, 0x99, 0xc5, 0xef, ++ 0x9b, 0x80, 0xfe, 0x8e, 0xff, 0x18, 0xfa, 0xdb, 0xb7, 0xc9, 0x43, 0xef, ++ 0xee, 0x7c, 0xb6, 0xfb, 0x89, 0x2c, 0x1c, 0x7f, 0x67, 0xe7, 0x9c, 0xf7, ++ 0x37, 0x41, 0xff, 0x67, 0x42, 0xfc, 0xf7, 0x4d, 0x9c, 0x61, 0x9d, 0x67, ++ 0x7f, 0x85, 0xf2, 0x74, 0xbb, 0x8d, 0xfc, 0x96, 0x2b, 0x24, 0x80, 0x0b, ++ 0xf5, 0xe9, 0x8e, 0x14, 0xca, 0x17, 0x48, 0x4a, 0x4c, 0x23, 0x39, 0x33, ++ 0x42, 0xb4, 0x6e, 0x0b, 0x24, 0x55, 0xc1, 0x77, 0xc8, 0x16, 0xbe, 0xb0, ++ 0x31, 0x05, 0xf9, 0x0b, 0xef, 0x8b, 0x63, 0x5c, 0xfd, 0xcb, 0x6b, 0x62, ++ 0x49, 0x4e, 0xbd, 0x6c, 0xf4, 0x1e, 0x6f, 0xc4, 0xfe, 0xb6, 0xf0, 0xfe, ++ 0x9e, 0x7d, 0xec, 0xa1, 0x0f, 0xf7, 0x63, 0xfa, 0x68, 0x6d, 0xc9, 0x43, ++ 0x90, 0xde, 0x3e, 0xd2, 0x45, 0x78, 0x9f, 0xfd, 0x2f, 0x0b, 0x86, 0x63, ++ 0x7b, 0xd0, 0xd7, 0xf4, 0x7b, 0x95, 0x9f, 0x7b, 0x51, 0x0a, 0xa3, 0x1f, ++ 0xa4, 0xb8, 0xfd, 0xe0, 0x32, 0x8c, 0x63, 0x1a, 0xb9, 0xf9, 0x84, 0x21, ++ 0x05, 0xd2, 0x51, 0xdb, 0xa5, 0x66, 0x4c, 0x0b, 0xd3, 0x27, 0x1d, 0x45, ++ 0xff, 0xc1, 0xdd, 0x23, 0x55, 0x82, 0xe3, 0xaa, 0x5d, 0x99, 0x32, 0xc6, ++ 0xa6, 0x0f, 0x4f, 0x09, 0xbd, 0x7f, 0x03, 0x8f, 0x1b, 0xd1, 0xe9, 0xf7, ++ 0xa2, 0xf6, 0xcf, 0x2b, 0x70, 0x9b, 0xa9, 0xe9, 0xf9, 0xe1, 0x52, 0xe7, ++ 0xa7, 0x1d, 0xb8, 0x2f, 0x1e, 0x7a, 0xac, 0x84, 0xdf, 0xef, 0xe2, 0xef, ++ 0x44, 0xef, 0xed, 0x9a, 0xf2, 0xce, 0xf7, 0x19, 0xce, 0x03, 0x2c, 0x08, ++ 0x84, 0x7b, 0x86, 0x89, 0xe2, 0x2e, 0x58, 0x28, 0xd8, 0x81, 0x74, 0x3e, ++ 0x13, 0x28, 0xf0, 0xd2, 0xfb, 0x26, 0xfe, 0xe0, 0x46, 0xe4, 0xaf, 0x33, ++ 0x81, 0x24, 0x7a, 0x4f, 0x7a, 0x9f, 0x21, 0x18, 0x87, 0xbf, 0x2f, 0x29, ++ 0x78, 0x9c, 0xff, 0x5e, 0x9f, 0x17, 0xb7, 0xbf, 0x15, 0x87, 0xf1, 0x14, ++ 0xf1, 0x7b, 0x8c, 0x0c, 0x7f, 0xff, 0x74, 0xed, 0xa8, 0xde, 0x09, 0x14, ++ 0x1f, 0x92, 0xae, 0xd2, 0x7e, 0x3c, 0x7d, 0xeb, 0x8d, 0x55, 0x88, 0x9f, ++ 0xba, 0x3d, 0x7b, 0x3b, 0xa8, 0x9f, 0x85, 0x16, 0x2f, 0xfa, 0x63, 0xe7, ++ 0xef, 0xfd, 0x82, 0xee, 0xbd, 0xb0, 0x89, 0x3c, 0x0e, 0xf5, 0xcc, 0x1e, ++ 0x9e, 0x7f, 0xa4, 0xd2, 0x47, 0xef, 0x8a, 0xcf, 0xef, 0xf8, 0x33, 0xcf, ++ 0x77, 0xfb, 0x29, 0xef, 0x97, 0x83, 0x99, 0x74, 0x7f, 0x62, 0x16, 0xb7, ++ 0x77, 0x9e, 0x10, 0xfa, 0x8c, 0xf5, 0x8c, 0x60, 0x91, 0xef, 0x12, 0x69, ++ 0xf4, 0x7a, 0x04, 0x8a, 0xb1, 0x7c, 0x43, 0x66, 0x30, 0x19, 0xdf, 0x9f, ++ 0xd2, 0xf4, 0x20, 0xe8, 0xaf, 0x26, 0x5c, 0x7f, 0xe8, 0x76, 0xa4, 0xf6, ++ 0x8e, 0x29, 0xfc, 0xbe, 0xfa, 0x15, 0xea, 0x2f, 0x93, 0xd0, 0x47, 0x5a, ++ 0x7f, 0x4f, 0x98, 0xf8, 0x7b, 0xb9, 0x28, 0x46, 0xf0, 0xf7, 0xcf, 0x6c, ++ 0x36, 0x71, 0xbd, 0xbb, 0x03, 0xe4, 0x0d, 0xf2, 0x8b, 0xa6, 0x77, 0x61, ++ 0xdc, 0xc7, 0x71, 0x5c, 0x93, 0xb8, 0x2f, 0x93, 0x0a, 0x4a, 0x76, 0x14, ++ 0xcc, 0x27, 0xf5, 0x09, 0x33, 0x97, 0xdf, 0x57, 0x38, 0x7e, 0xf4, 0xbd, ++ 0x52, 0xcd, 0x0e, 0x99, 0x96, 0xd0, 0x4c, 0xf7, 0x47, 0x3f, 0x4b, 0x0d, ++ 0x3c, 0x89, 0xf2, 0x41, 0xbb, 0x47, 0xca, 0x14, 0x2f, 0xbd, 0xef, 0xf7, ++ 0x41, 0xaa, 0x6f, 0xf3, 0xc8, 0xd1, 0xfc, 0xdd, 0x0c, 0x9c, 0x03, 0xe8, ++ 0xc5, 0x10, 0xd6, 0xab, 0x93, 0xc1, 0x8e, 0xca, 0x8e, 0xb0, 0xa3, 0x2c, ++ 0x57, 0xa6, 0x17, 0xff, 0x96, 0xea, 0x7b, 0x06, 0xdb, 0x5f, 0x69, 0xfd, ++ 0x68, 0x39, 0x3c, 0x56, 0xc0, 0xbf, 0xd8, 0x6e, 0x20, 0x3c, 0x2c, 0x5e, ++ 0x67, 0x26, 0x7f, 0xd8, 0x58, 0x71, 0xbf, 0x74, 0xec, 0xf9, 0x63, 0xb1, ++ 0x28, 0x4f, 0x16, 0xff, 0xb9, 0x84, 0xe4, 0x4a, 0x33, 0x63, 0x03, 0xe2, ++ 0xe7, 0x95, 0x26, 0x1e, 0xe7, 0xfd, 0x6b, 0xf4, 0x23, 0x40, 0x7a, 0xdd, ++ 0x97, 0x3d, 0x32, 0xed, 0x47, 0x0e, 0x1b, 0x16, 0x1e, 0x01, 0xfd, 0x4a, ++ 0x20, 0x90, 0xff, 0xb0, 0xb7, 0x39, 0xbe, 0x94, 0xf2, 0x3e, 0x24, 0xf7, ++ 0xf5, 0x5f, 0x1a, 0x06, 0xdc, 0x2f, 0x6a, 0x29, 0xd0, 0xeb, 0x35, 0x9c, ++ 0x9f, 0xef, 0x2b, 0xbd, 0xff, 0xe1, 0x86, 0xaf, 0x1c, 0xf4, 0xfb, 0x29, ++ 0x99, 0xcd, 0x75, 0x45, 0xf3, 0xee, 0x7f, 0x67, 0x47, 0x3f, 0x7f, 0xed, ++ 0xbd, 0x2b, 0x98, 0x5f, 0x0f, 0xea, 0xf7, 0xc5, 0x9f, 0x1b, 0x88, 0x7f, ++ 0x17, 0x7f, 0x5e, 0x42, 0x72, 0xb3, 0xeb, 0x0a, 0xe7, 0x6b, 0x75, 0xfb, ++ 0xfe, 0x03, 0xe9, 0x1a, 0x3d, 0x1f, 0x80, 0xff, 0xbf, 0x06, 0x82, 0xbf, ++ 0x8f, 0xdf, 0x7b, 0xaf, 0x0c, 0xfe, 0x07, 0x25, 0x46, 0xbf, 0xd7, 0x07, ++ 0xd4, 0x15, 0xf9, 0xb7, 0xbb, 0xc4, 0x7b, 0x02, 0x5d, 0x0b, 0x8a, 0xe8, ++ 0x5d, 0x8b, 0x7d, 0xf8, 0x2e, 0x08, 0xca, 0xcd, 0xc9, 0xfc, 0xde, 0x51, ++ 0x17, 0xf6, 0x0d, 0xf5, 0xbb, 0x12, 0x1d, 0xf4, 0xee, 0xc6, 0xcb, 0x46, ++ 0x9e, 0x0f, 0xde, 0x29, 0xda, 0x8b, 0x77, 0x1a, 0xbb, 0xee, 0x4c, 0xe1, ++ 0xef, 0x66, 0x98, 0x1b, 0x7e, 0x57, 0x8c, 0xfd, 0x37, 0xf3, 0xf8, 0xb8, ++ 0x2e, 0x63, 0x88, 0x7e, 0x1f, 0x6c, 0xd7, 0x4f, 0x13, 0xe8, 0x3e, 0x81, ++ 0x16, 0x3f, 0x7e, 0x4c, 0xc8, 0xed, 0x66, 0x29, 0xfc, 0x7d, 0x7a, 0x0f, ++ 0xe4, 0x73, 0x13, 0xe3, 0xef, 0xea, 0x85, 0x53, 0xeb, 0x4b, 0xf1, 0x1d, ++ 0x90, 0xe1, 0x54, 0xff, 0x98, 0xf8, 0xfd, 0xc9, 0x57, 0xfa, 0xae, 0xde, ++ 0x5d, 0x82, 0x3e, 0xed, 0x1d, 0xa1, 0x1d, 0xeb, 0x01, 0x8e, 0xff, 0x07, ++ 0x35, 0x8a, 0x15, 0xa9, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d, ++ 0x0b, 0x78, 0x94, 0xd5, 0xb5, 0xe8, 0xfe, 0xe7, 0x9f, 0x99, 0xcc, 0x24, ++ 0x93, 0x64, 0x12, 0x42, 0x1e, 0x84, 0x84, 0xc9, 0x83, 0x10, 0x24, 0xe0, ++ 0xe4, 0x05, 0x01, 0x42, 0x18, 0x20, 0xa1, 0xa8, 0x68, 0x03, 0x08, 0x02, ++ 0xc6, 0x38, 0x21, 0x21, 0x84, 0xbc, 0x08, 0x48, 0xcf, 0x49, 0x2d, 0x35, ++ 0x83, 0x09, 0x0f, 0x15, 0x6b, 0x38, 0x46, 0x8d, 0x8a, 0x3a, 0x58, 0xa0, ++ 0xa0, 0x60, 0x07, 0x05, 0x44, 0x0d, 0x9e, 0x01, 0xd4, 0x52, 0x1f, 0x35, ++ 0xd5, 0xea, 0xb1, 0xda, 0x62, 0x02, 0x88, 0x0f, 0x1e, 0x09, 0x41, 0xfd, ++ 0xb0, 0xd7, 0xdb, 0xde, 0xb5, 0xd6, 0xde, 0x3b, 0x33, 0xff, 0x24, 0x51, ++ 0xdb, 0x73, 0xfd, 0xee, 0x77, 0xbe, 0xef, 0xa6, 0x5f, 0xdd, 0xec, 0x7f, ++ 0xbf, 0xd7, 0x5a, 0x7b, 0xed, 0xb5, 0xd7, 0x63, 0x4f, 0xdb, 0xbc, 0x74, ++ 0xbb, 0xcb, 0xc6, 0xd8, 0x08, 0x95, 0x35, 0x78, 0x32, 0x18, 0x6b, 0x4b, ++ 0x72, 0xc4, 0x45, 0x42, 0xfa, 0xa1, 0x81, 0x2d, 0xc6, 0xfc, 0x9f, 0x19, ++ 0xfc, 0xc5, 0x31, 0xf6, 0x98, 0x81, 0xb9, 0xcc, 0x91, 0x8c, 0x5d, 0x65, ++ 0x5f, 0x16, 0x6d, 0x1f, 0xce, 0x98, 0xf3, 0x86, 0x10, 0x3d, 0x0b, 0xc7, ++ 0x42, 0x47, 0x9c, 0x92, 0xc3, 0xd8, 0x23, 0x15, 0xa3, 0xd9, 0xdd, 0x0a, ++ 0x64, 0x5b, 0x1f, 0x62, 0x2c, 0x9a, 0xb1, 0xc5, 0x26, 0x46, 0x7f, 0x4b, ++ 0x83, 0xc3, 0x26, 0xb0, 0xab, 0xe9, 0x9f, 0x0e, 0xd3, 0x44, 0xc6, 0x16, ++ 0xf2, 0xcf, 0x6c, 0xc9, 0xf2, 0x9d, 0x66, 0xa7, 0x05, 0xf2, 0x55, 0xe6, ++ 0x6e, 0x65, 0x02, 0x63, 0x1f, 0x54, 0xdd, 0x19, 0x6a, 0x83, 0xf1, 0x16, ++ 0x3a, 0x55, 0x6f, 0x50, 0x18, 0x54, 0xb8, 0xb1, 0xc8, 0xd1, 0x95, 0xce, ++ 0xeb, 0xfe, 0x23, 0x19, 0xc7, 0x75, 0xd0, 0xb8, 0xac, 0x62, 0x18, 0x63, ++ 0x93, 0x21, 0xd5, 0x7b, 0xcb, 0x19, 0x8c, 0xfb, 0x72, 0xaf, 0x89, 0xdd, ++ 0x9d, 0x04, 0x75, 0xf0, 0x6f, 0xba, 0x2f, 0x65, 0xcc, 0xc5, 0x18, 0xd4, ++ 0xff, 0xcc, 0xcc, 0xc7, 0xaf, 0xf3, 0xcc, 0xb8, 0xff, 0x8c, 0xec, 0x0f, ++ 0xfe, 0x5f, 0x65, 0xb4, 0x6c, 0x56, 0xc2, 0xb1, 0x3c, 0xd1, 0xcd, 0x60, ++ 0xfc, 0xfd, 0x23, 0x9c, 0xa3, 0xed, 0xb9, 0x8c, 0xad, 0x3a, 0x7c, 0xcd, ++ 0xfd, 0x67, 0x4c, 0xbe, 0x7a, 0x15, 0xcb, 0x8b, 0xd2, 0x98, 0xce, 0x37, ++ 0x6e, 0xe0, 0x38, 0x81, 0xe3, 0x35, 0xbb, 0x75, 0x2e, 0x03, 0x8c, 0x37, ++ 0xca, 0xb4, 0x20, 0xe3, 0x0c, 0x34, 0x69, 0x86, 0x02, 0x1d, 0xcc, 0xd3, ++ 0xe5, 0x31, 0xbb, 0x77, 0x26, 0xe1, 0xbc, 0x7b, 0xff, 0xbc, 0x02, 0xf2, ++ 0xcd, 0x8b, 0xaf, 0xb2, 0xdf, 0x0d, 0xd9, 0x39, 0xf3, 0x4d, 0x0e, 0x25, ++ 0x8a, 0xb1, 0xbe, 0x03, 0x41, 0xee, 0x20, 0x05, 0xbf, 0x07, 0x3b, 0x70, ++ 0x5d, 0xcd, 0x47, 0x42, 0xdd, 0x3a, 0xc8, 0xdf, 0xaa, 0x70, 0xf8, 0x37, ++ 0x2b, 0x8c, 0xbe, 0xbb, 0xf6, 0x1b, 0xdc, 0x3b, 0xe1, 0x5b, 0xad, 0xd1, ++ 0xbd, 0x67, 0x17, 0xb4, 0xab, 0x7d, 0x79, 0xac, 0x1d, 0x46, 0x66, 0x87, ++ 0x8c, 0xf0, 0x1f, 0x2c, 0x7f, 0x31, 0x84, 0x97, 0x87, 0x39, 0x92, 0x36, ++ 0xe4, 0x60, 0x79, 0x0c, 0xe1, 0xf7, 0x25, 0x83, 0x2d, 0x9c, 0xca, 0x7f, ++ 0xaf, 0x32, 0x2a, 0x0f, 0xf6, 0xa6, 0x45, 0x00, 0xbc, 0x1b, 0x63, 0x9d, ++ 0xb3, 0x10, 0xae, 0x23, 0x82, 0x00, 0xff, 0x16, 0xec, 0x97, 0x7f, 0x3f, ++ 0x89, 0xeb, 0x00, 0xf8, 0x9c, 0x84, 0x6e, 0x11, 0xbf, 0xae, 0x86, 0x50, ++ 0xea, 0x97, 0x89, 0xbc, 0xf3, 0x17, 0xc3, 0xdc, 0x77, 0xd3, 0x7a, 0x1c, ++ 0x71, 0xcb, 0x31, 0x7f, 0xdb, 0x38, 0x5a, 0x8f, 0x13, 0xe7, 0x01, 0xf3, ++ 0x62, 0xf5, 0x0a, 0xad, 0xf7, 0xa4, 0xd5, 0x7d, 0x57, 0x1a, 0x94, 0x9f, ++ 0xec, 0x18, 0x4e, 0xf3, 0x88, 0x12, 0xf4, 0x70, 0xb2, 0xf8, 0xeb, 0xb7, ++ 0x26, 0x41, 0xbd, 0x93, 0x87, 0x55, 0x3b, 0xf6, 0xf9, 0x97, 0x46, 0xd5, ++ 0x6b, 0x0c, 0xc3, 0x72, 0x8e, 0x0f, 0x65, 0xbe, 0x29, 0xad, 0x1d, 0xda, ++ 0x9d, 0x7e, 0x31, 0xd4, 0x1e, 0x04, 0xe5, 0x25, 0xf7, 0xd5, 0xbc, 0x89, ++ 0xdf, 0x4b, 0xee, 0xac, 0x9b, 0x4b, 0x69, 0xf5, 0xba, 0x1b, 0x18, 0xd4, ++ 0xef, 0xba, 0xf3, 0xa3, 0x44, 0x67, 0xc6, 0x40, 0x7c, 0x94, 0xd4, 0x42, ++ 0x2b, 0x3f, 0x3c, 0xae, 0xb2, 0x3b, 0x4a, 0x11, 0xbf, 0xf7, 0xd8, 0x9d, ++ 0x65, 0xb8, 0xde, 0x55, 0x19, 0x5d, 0x95, 0x0c, 0xe8, 0xea, 0xa2, 0xb1, ++ 0xf3, 0x71, 0xa6, 0x32, 0xf6, 0xfe, 0x48, 0x67, 0x05, 0x7e, 0xef, 0x79, ++ 0xe1, 0xd3, 0x5d, 0xf8, 0x1d, 0xf0, 0x94, 0x56, 0x3c, 0x1e, 0x96, 0xa1, ++ 0x07, 0x3a, 0x41, 0xfa, 0xed, 0x9a, 0x40, 0x74, 0xbd, 0x4a, 0xd0, 0xef, ++ 0xb0, 0x4c, 0x67, 0x35, 0xf6, 0x07, 0x70, 0x2c, 0x65, 0x29, 0x8c, 0x85, ++ 0x64, 0x74, 0x1a, 0x71, 0x1e, 0x6c, 0xdd, 0xf0, 0x1f, 0x44, 0x27, 0x5f, ++ 0x74, 0xec, 0x3c, 0xa4, 0xc0, 0x38, 0x35, 0xc1, 0x1d, 0xf5, 0x94, 0xaa, ++ 0xee, 0x09, 0xd8, 0xcf, 0x39, 0xc5, 0x1b, 0xa6, 0xa4, 0x10, 0x1c, 0x9d, ++ 0xb8, 0xff, 0xce, 0x5b, 0xbd, 0x61, 0x88, 0x0f, 0xa7, 0x0e, 0xf2, 0x80, ++ 0x9f, 0x9a, 0xdd, 0xda, 0x75, 0xe1, 0x9f, 0x1e, 0xe6, 0x55, 0x83, 0xff, ++ 0x80, 0x76, 0x35, 0x1e, 0xd5, 0x61, 0xc6, 0xfd, 0xc3, 0xdc, 0x46, 0x9c, ++ 0x7f, 0x0d, 0x33, 0xfa, 0xea, 0x27, 0xf1, 0x7d, 0x88, 0x74, 0x00, 0xfd, ++ 0x3c, 0x49, 0xfb, 0xd5, 0xf2, 0x97, 0xd2, 0x5f, 0x00, 0x1e, 0xaa, 0xf7, ++ 0x8c, 0xcd, 0xba, 0x1b, 0xf0, 0x53, 0x13, 0x71, 0xf8, 0x57, 0x53, 0xa9, ++ 0x1e, 0xb4, 0x93, 0xfb, 0x45, 0x1d, 0x98, 0x97, 0xeb, 0x19, 0x38, 0x1f, ++ 0xbe, 0xbe, 0xf3, 0x62, 0x1f, 0x9c, 0x87, 0x2f, 0x06, 0xa4, 0x9f, 0xbd, ++ 0x41, 0x9c, 0xfe, 0x19, 0xa7, 0x8f, 0x8b, 0x7b, 0xe2, 0x04, 0xfd, 0x70, ++ 0xba, 0xbd, 0xb8, 0x67, 0x8c, 0x1b, 0xe7, 0x13, 0x2d, 0xf6, 0xcd, 0x45, ++ 0xc5, 0xa5, 0x0b, 0xc6, 0x76, 0xbf, 0x64, 0xf6, 0x9d, 0x30, 0x2f, 0x66, ++ 0xf7, 0x4c, 0x9c, 0x37, 0x1e, 0x67, 0xef, 0x99, 0x38, 0x3f, 0x94, 0xb1, ++ 0x07, 0x15, 0xce, 0x9f, 0x6a, 0x86, 0x79, 0x26, 0x22, 0xbf, 0x92, 0xfc, ++ 0x8b, 0x99, 0x3c, 0x13, 0xe6, 0x41, 0x39, 0x4b, 0xf7, 0x4c, 0x98, 0x0f, ++ 0xf5, 0x5f, 0x12, 0xf5, 0x58, 0xb1, 0x27, 0x8d, 0xbe, 0xbb, 0x3d, 0x69, ++ 0xd8, 0xfe, 0x90, 0x8e, 0x55, 0x21, 0x3c, 0xe5, 0x7c, 0xaa, 0x9f, 0x8e, ++ 0xdf, 0x4e, 0xf0, 0x30, 0xf1, 0xfd, 0x5a, 0xfd, 0xf4, 0x38, 0x82, 0x8f, ++ 0x1c, 0xa7, 0x19, 0xf9, 0x48, 0x38, 0xa6, 0x40, 0x9f, 0x61, 0x03, 0xd7, ++ 0xfd, 0x5b, 0xbb, 0xc2, 0xf7, 0x7f, 0xe8, 0xc4, 0x18, 0xe4, 0x6b, 0x43, ++ 0xe1, 0x3f, 0x3d, 0x76, 0x58, 0x06, 0xb2, 0x92, 0x8b, 0x4b, 0x8c, 0xb7, ++ 0x3a, 0xa0, 0xdf, 0x31, 0xed, 0x46, 0x4d, 0x3f, 0xb2, 0xde, 0x58, 0xb7, ++ 0xf6, 0xfb, 0x61, 0xd1, 0xff, 0xa8, 0x00, 0x7c, 0x8e, 0x50, 0x7b, 0x8f, ++ 0x06, 0xc1, 0x7c, 0xd9, 0xaf, 0x01, 0x4e, 0x6c, 0xe0, 0x78, 0xff, 0x89, ++ 0xed, 0x80, 0x4e, 0x9f, 0x7a, 0xaa, 0x1f, 0x7f, 0x2a, 0xc7, 0x27, 0x63, ++ 0x36, 0x49, 0x37, 0x36, 0x82, 0x13, 0xc7, 0xd3, 0x9f, 0x8d, 0x12, 0x4f, ++ 0x6b, 0xe3, 0x81, 0x5f, 0xd7, 0x20, 0x4c, 0x92, 0x7d, 0xf0, 0x3a, 0x94, ++ 0xe9, 0x8c, 0x8f, 0x84, 0xf4, 0x22, 0xe6, 0x61, 0xfe, 0x87, 0x22, 0x20, ++ 0x0f, 0x69, 0xbd, 0x80, 0xbf, 0xcc, 0x4b, 0xb8, 0x07, 0xd2, 0xdf, 0x9d, ++ 0x7f, 0xae, 0x8c, 0xef, 0x82, 0xf6, 0xe7, 0xed, 0x3a, 0x9a, 0x57, 0x20, ++ 0x5c, 0xd7, 0x03, 0xfc, 0xb0, 0xbc, 0xd9, 0xc0, 0x6e, 0x2d, 0x86, 0xf6, ++ 0x5f, 0x34, 0x9d, 0x48, 0x39, 0x63, 0xf0, 0xad, 0xe7, 0x6c, 0x93, 0xc3, ++ 0x01, 0x47, 0x4d, 0x7f, 0xbe, 0xb2, 0x3d, 0xd3, 0x84, 0xfb, 0x6e, 0xc5, ++ 0xb6, 0x4c, 0xd3, 0x32, 0x3f, 0xb8, 0x37, 0xef, 0xce, 0x3e, 0x61, 0x03, ++ 0xbc, 0x9e, 0xdf, 0xad, 0xc7, 0x91, 0x58, 0xb3, 0xde, 0xfd, 0xab, 0x29, ++ 0x51, 0xf8, 0x5d, 0xf5, 0xb8, 0x18, 0x95, 0x9b, 0x1c, 0x38, 0x0f, 0xcb, ++ 0xb1, 0x3f, 0x60, 0xbd, 0xca, 0x6d, 0x11, 0x59, 0xaa, 0xcd, 0xd7, 0x7e, ++ 0x45, 0x7b, 0x91, 0xa3, 0xc2, 0x0f, 0xfe, 0xe3, 0x76, 0x6b, 0xf1, 0x31, ++ 0xde, 0xa3, 0xcd, 0x5f, 0x7d, 0x58, 0x9b, 0xff, 0x1a, 0xb9, 0x5a, 0xee, ++ 0x3f, 0xdf, 0x2e, 0xd3, 0xab, 0xcd, 0x67, 0x9f, 0xd0, 0xe6, 0x3f, 0xfd, ++ 0xd3, 0xda, 0x45, 0xb8, 0x0d, 0x9e, 0xcf, 0xe3, 0xfb, 0xe6, 0x33, 0x77, ++ 0xa8, 0xdb, 0x04, 0x70, 0xad, 0xfa, 0x68, 0xf6, 0x09, 0x3c, 0x47, 0x3f, ++ 0x3b, 0xf4, 0x7c, 0x18, 0xe2, 0xab, 0xe6, 0xaf, 0x15, 0xaf, 0xc5, 0x33, ++ 0x5c, 0x87, 0x96, 0x4e, 0x01, 0x8f, 0x8a, 0x1e, 0xd6, 0xeb, 0xda, 0xa5, ++ 0x10, 0xbd, 0xac, 0x74, 0x07, 0xee, 0x5f, 0xc1, 0x37, 0x06, 0xec, 0xeb, ++ 0xf5, 0xb4, 0x1e, 0xdc, 0x59, 0xfe, 0x74, 0x13, 0x88, 0xdf, 0x73, 0xcc, ++ 0xb3, 0xc8, 0x01, 0xf4, 0x55, 0xdb, 0xf8, 0x6e, 0xca, 0x99, 0x6c, 0x98, ++ 0xd7, 0x5c, 0x20, 0x64, 0x98, 0xcf, 0x64, 0xcf, 0x56, 0x23, 0xb3, 0x0c, ++ 0x1c, 0x6f, 0x28, 0xfe, 0xc1, 0x2c, 0x0e, 0x1b, 0x03, 0xfa, 0x2b, 0xcb, ++ 0xe3, 0x65, 0x53, 0x1a, 0x67, 0xb1, 0xd3, 0xd0, 0x1f, 0xdb, 0xf2, 0xc7, ++ 0xd9, 0xb8, 0x5f, 0xcb, 0xee, 0x51, 0x48, 0xde, 0x28, 0x7b, 0x6e, 0xcc, ++ 0x2b, 0x48, 0x37, 0xdd, 0xfb, 0x97, 0x5c, 0x4b, 0xe9, 0xa2, 0x39, 0x04, ++ 0x87, 0x72, 0xe6, 0x30, 0x22, 0x3f, 0x5c, 0xd1, 0xa1, 0x78, 0x43, 0x21, ++ 0x6f, 0xcd, 0xb3, 0x1d, 0xee, 0x82, 0x76, 0xcb, 0xdd, 0x8a, 0x1d, 0xe7, ++ 0xbd, 0xac, 0x25, 0xc8, 0xc7, 0xcf, 0xe0, 0xff, 0x15, 0x5b, 0x02, 0xe6, ++ 0xd1, 0xe6, 0x57, 0x0e, 0xf3, 0x5f, 0x71, 0xf8, 0xe8, 0x37, 0x0a, 0xf4, ++ 0x5f, 0xb5, 0x4d, 0xdb, 0x6e, 0x25, 0xc0, 0x0b, 0xcf, 0x8f, 0xea, 0x1d, ++ 0xff, 0x08, 0xf2, 0xff, 0x0e, 0x82, 0x10, 0xc1, 0x6b, 0x4a, 0xc7, 0x76, ++ 0x15, 0xd7, 0xbd, 0x5c, 0xcc, 0x5f, 0x9e, 0x7f, 0xcc, 0x55, 0xc0, 0x70, ++ 0x7d, 0x53, 0x78, 0x13, 0x76, 0x06, 0xff, 0x03, 0xe7, 0x46, 0xf0, 0x28, ++ 0x67, 0x6e, 0x66, 0xae, 0xef, 0x1c, 0x9c, 0xd2, 0xc6, 0xdb, 0x03, 0xe3, ++ 0x2b, 0xc3, 0x75, 0xd7, 0x59, 0x8c, 0x36, 0x5c, 0x77, 0x9d, 0x89, 0x79, ++ 0x43, 0x60, 0x3e, 0x27, 0x42, 0x8d, 0x0e, 0x2b, 0x7c, 0xbf, 0xdc, 0x1e, ++ 0x4a, 0xf2, 0x43, 0x65, 0x10, 0x73, 0x99, 0xb2, 0x28, 0x65, 0xe6, 0x2c, ++ 0x6c, 0x67, 0x0f, 0xc7, 0x76, 0x67, 0xdf, 0x56, 0x49, 0x4e, 0xaa, 0x03, ++ 0xde, 0x43, 0xfd, 0x3c, 0xa1, 0xb8, 0x9b, 0xb1, 0x1f, 0x55, 0xe1, 0xf9, ++ 0x5f, 0xf3, 0xfc, 0x4a, 0xe6, 0xa5, 0xf5, 0x20, 0xdd, 0x38, 0xfc, 0xd7, ++ 0xe9, 0xd6, 0xe6, 0x59, 0xeb, 0x30, 0x92, 0x4b, 0x6a, 0xf5, 0xde, 0xa3, ++ 0x08, 0x97, 0x6a, 0xd6, 0x45, 0xf0, 0x66, 0x80, 0x4f, 0x87, 0x84, 0x23, ++ 0xc0, 0xad, 0x16, 0xd6, 0xf9, 0x41, 0x24, 0xca, 0x5f, 0xda, 0xf6, 0xab, ++ 0x98, 0x87, 0xea, 0xaf, 0x3a, 0xfc, 0x8f, 0x20, 0xff, 0xef, 0x20, 0x67, ++ 0x32, 0x13, 0xd4, 0xdf, 0x16, 0x0c, 0x29, 0xcd, 0xdf, 0x4d, 0x70, 0x54, ++ 0x8d, 0xcc, 0xa1, 0x83, 0x79, 0xaa, 0x77, 0x04, 0xbb, 0x5d, 0x24, 0x87, ++ 0x14, 0x07, 0x23, 0x9d, 0x1a, 0xf0, 0xbc, 0x00, 0xb8, 0xb6, 0xdd, 0xe5, ++ 0x48, 0xc3, 0x79, 0x6f, 0x50, 0x1c, 0x69, 0x56, 0xe4, 0x63, 0x5b, 0xcd, ++ 0x76, 0xe4, 0x63, 0x4b, 0xb7, 0xf3, 0x73, 0xa8, 0x2d, 0x02, 0xe4, 0x57, ++ 0x68, 0xdf, 0xb6, 0xf2, 0x2a, 0x6a, 0xbf, 0x14, 0xe5, 0x29, 0x94, 0x53, ++ 0x96, 0x70, 0x7e, 0xd7, 0x16, 0xe1, 0xf1, 0x22, 0xdf, 0x6f, 0x7b, 0x20, ++ 0x89, 0xcb, 0x53, 0x7f, 0x57, 0x09, 0x2e, 0xbd, 0xf7, 0x9a, 0xdd, 0x4f, ++ 0x42, 0xfd, 0xb6, 0x4c, 0x2e, 0xf7, 0xb4, 0x6d, 0x1d, 0x43, 0xed, 0x91, ++ 0x5f, 0x92, 0x3c, 0x75, 0x6f, 0x28, 0x6f, 0x3f, 0x8f, 0xc3, 0xb5, 0x6d, ++ 0xb8, 0xd5, 0xed, 0x82, 0xfc, 0x87, 0x38, 0x45, 0x80, 0x4f, 0xdb, 0x76, ++ 0x47, 0x9a, 0x89, 0xda, 0x81, 0x9c, 0x96, 0xe4, 0x3b, 0xa7, 0xa4, 0x3c, ++ 0xfd, 0x9b, 0x51, 0xce, 0xdb, 0x10, 0xdf, 0x72, 0xbd, 0x52, 0xfe, 0x66, ++ 0x55, 0x3f, 0x4c, 0xde, 0xdc, 0x29, 0xce, 0xcf, 0xde, 0xad, 0x30, 0x4f, ++ 0xe8, 0xff, 0x8c, 0x52, 0xfc, 0x9a, 0xce, 0x4f, 0x1e, 0x6e, 0xc9, 0xe4, ++ 0xfc, 0x7f, 0xe2, 0x4c, 0xc7, 0x2e, 0x51, 0xcf, 0x8e, 0xf5, 0x2a, 0x74, ++ 0xf3, 0xee, 0x9e, 0x0e, 0xf3, 0xad, 0x78, 0x50, 0x67, 0x6b, 0x4e, 0xf2, ++ 0xc1, 0x9d, 0x39, 0x1c, 0x69, 0x08, 0xe7, 0x33, 0x5b, 0xcd, 0x59, 0x48, ++ 0x67, 0x13, 0x67, 0x02, 0x1f, 0x06, 0xfa, 0x3b, 0x99, 0xc9, 0xf9, 0x79, ++ 0x48, 0x0e, 0x73, 0xb8, 0x21, 0xbd, 0x57, 0xf4, 0x7b, 0x6f, 0xa6, 0x4e, ++ 0x93, 0xc6, 0x06, 0x03, 0xfd, 0x41, 0x3f, 0x67, 0x8a, 0xbc, 0x06, 0xc4, ++ 0x6f, 0x68, 0x4e, 0xb1, 0x11, 0xcf, 0x43, 0x38, 0xc3, 0x89, 0x9f, 0x07, ++ 0xae, 0xe3, 0x61, 0xd1, 0x4f, 0x85, 0xb1, 0xf8, 0xf5, 0x69, 0x83, 0xcc, ++ 0xa7, 0x9f, 0x0e, 0x0a, 0xb9, 0xdc, 0x72, 0x66, 0xb5, 0xf2, 0x24, 0x9f, ++ 0x17, 0xc7, 0xf3, 0xc4, 0xff, 0x30, 0xdb, 0x9b, 0x69, 0xdd, 0x7c, 0x7e, ++ 0x12, 0xee, 0x40, 0x37, 0xb9, 0x74, 0xde, 0x0b, 0xbe, 0x15, 0xd1, 0x4f, ++ 0x27, 0xee, 0x3d, 0x66, 0x40, 0xed, 0x56, 0x29, 0x4f, 0x23, 0xfe, 0x15, ++ 0x0d, 0x9d, 0x10, 0x3c, 0xdb, 0xee, 0x1d, 0x4f, 0x78, 0x5c, 0x2a, 0xf0, ++ 0xcc, 0xee, 0x35, 0x0b, 0x3a, 0x61, 0xec, 0x6f, 0x58, 0x5e, 0x64, 0xa3, ++ 0x72, 0xa0, 0x13, 0x82, 0x4f, 0x5b, 0x26, 0xe0, 0xcd, 0xe2, 0x3b, 0xf7, ++ 0xda, 0xe6, 0x39, 0xe2, 0x22, 0xfc, 0xce, 0x23, 0xa0, 0x03, 0x2a, 0x07, ++ 0x7c, 0xef, 0xcf, 0x1c, 0x3e, 0xf0, 0xbe, 0x25, 0xf1, 0xcd, 0xf4, 0xee, ++ 0xdc, 0xe2, 0xd0, 0xa1, 0xf1, 0xbd, 0x2c, 0x2f, 0x62, 0xa2, 0x02, 0xa0, ++ 0x8e, 0xd7, 0x33, 0x57, 0x10, 0xc0, 0x05, 0xcf, 0x3c, 0x82, 0xcb, 0x5d, ++ 0x7a, 0xf7, 0x9d, 0x30, 0x9f, 0x91, 0x7a, 0x0e, 0xff, 0x04, 0x3d, 0xa7, ++ 0x2f, 0xe0, 0xce, 0xae, 0xe0, 0x2c, 0xaa, 0xef, 0x30, 0x42, 0xbe, 0xec, ++ 0xfe, 0x15, 0xcc, 0x01, 0xf5, 0xcb, 0xe2, 0x99, 0x5d, 0xe1, 0xf5, 0x59, ++ 0x38, 0xd6, 0x87, 0x6e, 0x54, 0x48, 0xf1, 0xcc, 0xc0, 0x76, 0x65, 0xe1, ++ 0xbc, 0xdf, 0xb2, 0x18, 0xe6, 0xbe, 0x53, 0xc8, 0xfd, 0xc8, 0xaf, 0x52, ++ 0x31, 0x4d, 0xa6, 0x7e, 0x1d, 0xba, 0x48, 0xde, 0x3e, 0x2c, 0x8b, 0xda, ++ 0xbb, 0x74, 0xbc, 0xbd, 0x43, 0x0f, 0xe9, 0xa8, 0x14, 0xbe, 0x5f, 0x7a, ++ 0x37, 0x04, 0xd1, 0xfe, 0x29, 0xdb, 0x94, 0x90, 0x86, 0x74, 0x30, 0x77, ++ 0xa6, 0x96, 0x0e, 0x52, 0xb3, 0x38, 0xdd, 0xc8, 0xb4, 0x35, 0xcb, 0x26, ++ 0xce, 0x19, 0x7b, 0x2c, 0xee, 0xef, 0x65, 0x2d, 0x63, 0xe9, 0xdc, 0x68, ++ 0x36, 0x17, 0xd7, 0x1d, 0x44, 0x7c, 0xed, 0x0b, 0x21, 0x79, 0xb0, 0x6c, ++ 0xe3, 0x2d, 0xd7, 0xe7, 0xe2, 0xfc, 0x9e, 0x19, 0x86, 0x12, 0x0e, 0xfb, ++ 0xe2, 0x86, 0xfd, 0x13, 0x91, 0xde, 0x96, 0xb5, 0x2c, 0xf9, 0xd9, 0x7b, ++ 0x78, 0x1f, 0xd9, 0x6d, 0xa6, 0xef, 0xfb, 0xb2, 0x9c, 0x1f, 0xe3, 0xfe, ++ 0xfa, 0x42, 0xb1, 0x95, 0x1e, 0x84, 0x0f, 0xcb, 0x16, 0x1e, 0x37, 0xc6, ++ 0x42, 0x7b, 0xa7, 0x67, 0xde, 0x85, 0x17, 0x21, 0xbd, 0xc1, 0xb5, 0xff, ++ 0x0f, 0x28, 0x17, 0xdc, 0x70, 0xa3, 0x4a, 0xf5, 0x6f, 0x60, 0x9e, 0xaf, ++ 0x3f, 0x44, 0xbe, 0xd0, 0xc2, 0xc7, 0xb9, 0xde, 0x75, 0x49, 0x1f, 0x0b, ++ 0xfd, 0x5d, 0x9f, 0xaf, 0x30, 0x2c, 0xef, 0x36, 0x5b, 0x13, 0x57, 0xc3, ++ 0xfc, 0xcb, 0x04, 0xfe, 0xce, 0x09, 0xfa, 0x6d, 0x36, 0xb3, 0xc5, 0xcf, ++ 0x5a, 0x70, 0x5e, 0x09, 0x69, 0xc9, 0xf0, 0xfd, 0x7a, 0x94, 0x54, 0x07, ++ 0x91, 0x03, 0xc7, 0x66, 0x09, 0x39, 0x71, 0x86, 0xb2, 0x0d, 0xe5, 0x9e, ++ 0x51, 0xb3, 0xf8, 0xfe, 0x92, 0xf5, 0xb1, 0x1f, 0xec, 0xf7, 0x6a, 0x84, ++ 0x07, 0xd4, 0xfb, 0x5a, 0xec, 0x2b, 0x99, 0x07, 0xb8, 0x52, 0xfd, 0x8a, ++ 0xcd, 0x41, 0xdd, 0x29, 0x61, 0x98, 0x1a, 0xbc, 0x63, 0x20, 0x5d, 0x94, ++ 0x33, 0xf3, 0x6f, 0xb8, 0xce, 0xb9, 0xc9, 0x6c, 0x36, 0xde, 0x9b, 0x7a, ++ 0x7f, 0xae, 0xb2, 0x27, 0x69, 0xbe, 0xbd, 0x65, 0xb4, 0xef, 0x43, 0xd3, ++ 0x6c, 0xb8, 0xef, 0x9d, 0x8c, 0x79, 0x89, 0xef, 0xb9, 0xc7, 0x12, 0xdd, ++ 0x77, 0xcf, 0xe8, 0xed, 0xde, 0x04, 0xf9, 0xee, 0xed, 0x63, 0xec, 0xcd, ++ 0xc4, 0xd7, 0xf9, 0xfd, 0x7d, 0xb9, 0x95, 0xd1, 0xf9, 0xde, 0x3d, 0x83, ++ 0xf3, 0x35, 0xc9, 0x5f, 0x4e, 0x5a, 0xbb, 0x42, 0x89, 0x5e, 0xc5, 0x7d, ++ 0xbe, 0x5c, 0x90, 0xc6, 0x27, 0x8d, 0xb3, 0x1e, 0x9c, 0x04, 0xf5, 0xcb, ++ 0x2d, 0xc6, 0x6e, 0x3c, 0x0f, 0x96, 0x3f, 0xb0, 0x20, 0xcc, 0x06, 0xf3, ++ 0x2c, 0x6f, 0x83, 0xfb, 0x3c, 0x9c, 0x63, 0x6c, 0x8b, 0xf6, 0x3e, 0x0f, ++ 0xf7, 0xed, 0xa8, 0xac, 0xdc, 0x81, 0xf7, 0xf2, 0xc0, 0xfb, 0x37, 0xd2, ++ 0x0c, 0xd2, 0x51, 0xc5, 0x16, 0x85, 0xe8, 0x70, 0x54, 0xb3, 0xdd, 0x18, ++ 0x47, 0x7c, 0x4c, 0xb1, 0xe2, 0xfa, 0x2a, 0x2c, 0xde, 0x54, 0x3c, 0xff, ++ 0x2a, 0xec, 0x66, 0x3b, 0x96, 0x9f, 0x6f, 0x72, 0xdc, 0x7f, 0x06, 0xe4, ++ 0xc3, 0x8b, 0x4d, 0x73, 0x28, 0x65, 0xdf, 0x02, 0xdc, 0x61, 0x9e, 0x57, ++ 0x21, 0xf2, 0x60, 0xdf, 0xa7, 0x67, 0x3b, 0x93, 0xb2, 0x00, 0x8e, 0x65, ++ 0xad, 0x65, 0x74, 0x9f, 0x0c, 0xc9, 0x70, 0x12, 0x7f, 0x72, 0x0a, 0xba, ++ 0x9b, 0x0b, 0x60, 0x56, 0x90, 0xdf, 0xe8, 0xbb, 0xe2, 0x70, 0x1f, 0xbe, ++ 0x93, 0x29, 0xbe, 0x47, 0x5a, 0xd3, 0x2c, 0x44, 0xcf, 0x66, 0x86, 0x70, ++ 0xe8, 0x36, 0x58, 0xd3, 0x70, 0x5e, 0xdd, 0x1b, 0xcc, 0x3a, 0x3c, 0x37, ++ 0xe7, 0xde, 0xc9, 0xe9, 0x1a, 0xf6, 0x99, 0x49, 0x0f, 0xed, 0xef, 0xd2, ++ 0xb3, 0x60, 0xdc, 0xef, 0x3d, 0xd8, 0x1e, 0xc6, 0x2b, 0x59, 0xaf, 0x2f, ++ 0xde, 0x0e, 0xf9, 0x91, 0x26, 0xa6, 0x0f, 0x8d, 0x44, 0xba, 0xca, 0x24, ++ 0xba, 0x6e, 0xcf, 0x71, 0x7e, 0x8d, 0xfc, 0xe0, 0xb3, 0x5f, 0xb2, 0x3c, ++ 0x94, 0x0b, 0xca, 0xb7, 0x6c, 0xa5, 0xf9, 0x48, 0xba, 0x60, 0xfa, 0xce, ++ 0xc2, 0x61, 0x28, 0xe7, 0xed, 0x4c, 0xca, 0xc2, 0xfb, 0xb5, 0xa4, 0xa3, ++ 0xf6, 0x9c, 0x99, 0x79, 0x08, 0xbf, 0x7e, 0x7a, 0xb8, 0x51, 0x21, 0x3a, ++ 0x80, 0xf4, 0x68, 0x0a, 0xd1, 0xc3, 0xfc, 0x69, 0x58, 0x3e, 0x77, 0xa6, ++ 0x37, 0x75, 0x0d, 0xcc, 0xab, 0x48, 0xad, 0x65, 0x0e, 0xd4, 0x33, 0xc4, ++ 0x32, 0x7b, 0x10, 0xcc, 0xbf, 0x8f, 0xf5, 0x92, 0x3c, 0xd1, 0x07, 0xf2, ++ 0x04, 0x9e, 0x67, 0x92, 0x9f, 0x48, 0xbe, 0x01, 0x74, 0xe0, 0x30, 0x45, ++ 0xfb, 0xf0, 0xbb, 0xab, 0x09, 0xa6, 0x02, 0x3c, 0x79, 0x77, 0x93, 0x89, ++ 0xd2, 0xa7, 0x9a, 0xac, 0x4c, 0x0f, 0xf0, 0xdd, 0xdb, 0x14, 0x4b, 0xf9, ++ 0x67, 0x9a, 0x6c, 0x94, 0x7a, 0x9a, 0xd2, 0xe9, 0xfb, 0xb3, 0x4d, 0x76, ++ 0xca, 0x1f, 0x68, 0xca, 0xa3, 0xfc, 0xa1, 0x26, 0x07, 0xe5, 0x0f, 0x37, ++ 0xcd, 0xa1, 0xf4, 0xc5, 0xa6, 0x62, 0xfa, 0x2e, 0xf9, 0x12, 0xc0, 0x85, ++ 0xf8, 0x90, 0xe4, 0x2b, 0x92, 0x1f, 0x49, 0x7a, 0x92, 0x7c, 0x29, 0x90, ++ 0x8e, 0x4a, 0x01, 0xbc, 0x05, 0x59, 0xd4, 0x9e, 0xf8, 0x9e, 0xe4, 0x77, ++ 0xb8, 0x0e, 0x5d, 0x96, 0x8f, 0x1f, 0x49, 0xfc, 0x26, 0x2b, 0xc5, 0xae, ++ 0xd8, 0x24, 0xe4, 0x63, 0x5d, 0x4b, 0x90, 0x5f, 0x14, 0xa9, 0xe7, 0xf7, ++ 0x3d, 0x0f, 0xf0, 0xed, 0xab, 0xb2, 0xd8, 0x83, 0x6c, 0x08, 0x17, 0xce, ++ 0xf7, 0xfa, 0x2c, 0x26, 0x3a, 0xe7, 0x13, 0x8d, 0xec, 0x30, 0xde, 0xff, ++ 0x9b, 0x57, 0x3b, 0xba, 0x37, 0xf9, 0x9d, 0xab, 0x37, 0x57, 0x29, 0x4c, ++ 0xef, 0x47, 0xb7, 0xb7, 0x34, 0x98, 0x99, 0xde, 0x8f, 0x6e, 0x6f, 0x6d, ++ 0x8c, 0xd0, 0xe4, 0x4b, 0x1a, 0xdf, 0x7d, 0x35, 0x06, 0xfa, 0xff, 0x47, ++ 0x82, 0x73, 0x35, 0xd2, 0xdf, 0xc9, 0x3b, 0xce, 0x3e, 0xf6, 0x5f, 0xf0, ++ 0xfd, 0x89, 0x3b, 0xbe, 0x18, 0x8d, 0xf8, 0x86, 0x79, 0xec, 0x7c, 0x08, ++ 0xc7, 0x5d, 0x17, 0xdc, 0x3f, 0x8f, 0x48, 0xcc, 0xb7, 0x18, 0xe8, 0x9c, ++ 0x19, 0x15, 0xcc, 0xef, 0x49, 0xa3, 0x82, 0xf9, 0x3d, 0x09, 0xff, 0x10, ++ 0x3f, 0xcb, 0x18, 0xdf, 0xa7, 0x4f, 0xdc, 0xf1, 0x37, 0xda, 0xe7, 0xdd, ++ 0x8d, 0x41, 0x36, 0x15, 0xe5, 0x0f, 0xc4, 0x17, 0xc0, 0xf7, 0x2f, 0x02, ++ 0x5f, 0xcb, 0x1a, 0x83, 0x08, 0x8e, 0x65, 0x1b, 0x4e, 0xef, 0x7b, 0x1e, ++ 0xf7, 0xfb, 0x3a, 0x23, 0xf1, 0xbb, 0x65, 0x2d, 0x62, 0x7f, 0x6e, 0x06, ++ 0xb8, 0xfa, 0xc9, 0x6d, 0xa7, 0xe2, 0x18, 0xc9, 0x67, 0x8a, 0x83, 0xb1, ++ 0x46, 0x80, 0xdf, 0xa9, 0x5f, 0x1a, 0xbd, 0x70, 0xf6, 0xb3, 0x53, 0x8a, ++ 0xc9, 0xad, 0x40, 0x43, 0x05, 0x2e, 0x4d, 0x25, 0x08, 0xd7, 0xcd, 0xbf, ++ 0xfb, 0x00, 0xe5, 0x6d, 0xa5, 0xf1, 0x04, 0xc9, 0xc7, 0x4e, 0x93, 0xc5, ++ 0xab, 0xe2, 0xfc, 0x5c, 0x86, 0xf3, 0xfe, 0xfd, 0x29, 0x8d, 0xaf, 0x51, ++ 0x3d, 0xd6, 0x35, 0x32, 0xe2, 0x6c, 0x08, 0x6d, 0x45, 0x86, 0x70, 0x0c, ++ 0xc9, 0x71, 0x18, 0x91, 0x4f, 0x20, 0x6d, 0x23, 0xfe, 0x96, 0xa5, 0x1f, ++ 0x63, 0xb8, 0xbf, 0x59, 0xab, 0x62, 0x1d, 0x0d, 0xeb, 0xaa, 0x10, 0xdf, ++ 0x2b, 0x36, 0x2b, 0x24, 0x77, 0x48, 0xf8, 0x3f, 0x92, 0xa5, 0xd2, 0xbe, ++ 0x7a, 0x2f, 0x53, 0x4f, 0x69, 0x36, 0xee, 0xd9, 0xe1, 0xc4, 0xc0, 0xe8, ++ 0x9c, 0x92, 0x74, 0x0b, 0x7c, 0xc3, 0xe1, 0xc6, 0xfd, 0xd1, 0x9a, 0x69, ++ 0xac, 0xf4, 0xe3, 0xc7, 0xcb, 0xc4, 0xf7, 0xf2, 0x74, 0x1d, 0xa5, 0xf2, ++ 0xfb, 0x7b, 0xb0, 0x2d, 0x91, 0x4e, 0xb2, 0x11, 0x49, 0x90, 0xde, 0x9d, ++ 0x9e, 0x6c, 0x5c, 0x4e, 0xfc, 0xce, 0x66, 0x44, 0x7e, 0x20, 0xeb, 0x2f, ++ 0x4b, 0xcf, 0xda, 0x98, 0x9c, 0x83, 0xfd, 0xcc, 0x88, 0x62, 0x7e, 0xfb, ++ 0x72, 0x57, 0x96, 0x9e, 0xda, 0xbd, 0x97, 0x69, 0xe5, 0xf3, 0x31, 0xc1, ++ 0x39, 0x06, 0xed, 0x6a, 0x87, 0x38, 0x0f, 0xa4, 0x7c, 0xf2, 0x19, 0xfe, ++ 0x73, 0x32, 0xcd, 0x9f, 0xee, 0x5f, 0xd5, 0xcf, 0x3c, 0xfd, 0xcc, 0x8b, ++ 0xa8, 0x97, 0xf8, 0x28, 0x88, 0xf0, 0x54, 0x7d, 0xb5, 0xd0, 0x6f, 0x64, ++ 0xb8, 0x27, 0x2e, 0x20, 0xb9, 0xc6, 0x61, 0x51, 0x60, 0x9d, 0xf5, 0x02, ++ 0xff, 0x85, 0x4f, 0xff, 0x35, 0xac, 0x0b, 0xca, 0x57, 0x1d, 0xe0, 0xfa, ++ 0x53, 0x48, 0xbb, 0x31, 0xad, 0x5f, 0x57, 0x45, 0xfa, 0xb2, 0x7a, 0xb8, ++ 0x8f, 0x16, 0x44, 0x22, 0x7f, 0x35, 0x9c, 0xea, 0xf2, 0xa3, 0xcb, 0x57, ++ 0x9e, 0xf9, 0x28, 0xac, 0x8b, 0xee, 0x17, 0xae, 0x78, 0x5d, 0x2c, 0xa6, ++ 0xde, 0x78, 0x06, 0x69, 0xfd, 0x81, 0xd3, 0xb3, 0x19, 0xf6, 0xc7, 0x7a, ++ 0x37, 0x5a, 0x2d, 0x03, 0xdb, 0xad, 0x52, 0xbe, 0xa5, 0x7b, 0xa6, 0x5c, ++ 0x47, 0xd1, 0x91, 0xaf, 0xa2, 0x69, 0x7c, 0xe5, 0x4a, 0x34, 0xd5, 0x3f, ++ 0xb2, 0x21, 0x7a, 0x30, 0x3d, 0xc8, 0x2a, 0xa6, 0x3f, 0xd5, 0xbf, 0x7f, ++ 0x49, 0xcf, 0xe0, 0xd0, 0xe8, 0xd5, 0x56, 0xb1, 0x2d, 0x97, 0x54, 0x98, ++ 0xef, 0xaa, 0x75, 0x73, 0x3e, 0x45, 0x3a, 0x0f, 0xac, 0xff, 0x41, 0x56, ++ 0x68, 0x14, 0xd2, 0x0f, 0x9b, 0xc4, 0x26, 0x91, 0x1e, 0x43, 0xcf, 0x74, ++ 0x88, 0xef, 0x35, 0x26, 0x0e, 0x87, 0x3e, 0xf7, 0xe8, 0x70, 0xf6, 0x1d, ++ 0xfa, 0x97, 0x55, 0xed, 0xd0, 0x08, 0x44, 0xad, 0x3e, 0xbd, 0x2d, 0xdc, ++ 0x0e, 0xf3, 0xed, 0x61, 0x6c, 0xce, 0x60, 0x78, 0x49, 0xc8, 0xe6, 0xe7, ++ 0xf4, 0x05, 0xd8, 0x47, 0x0c, 0xee, 0x52, 0x3d, 0x7b, 0x55, 0xba, 0x2f, ++ 0xf4, 0xec, 0x0d, 0x25, 0xfa, 0xaf, 0xdf, 0x7b, 0xff, 0x6b, 0x53, 0x21, ++ 0x5f, 0xbf, 0x43, 0xc1, 0x61, 0x59, 0x1d, 0xeb, 0x24, 0x38, 0xd5, 0x1f, ++ 0x50, 0x99, 0xc9, 0xff, 0x3c, 0x43, 0xfd, 0xce, 0xb0, 0xa1, 0xe7, 0x59, ++ 0xf3, 0x74, 0x68, 0x03, 0xd2, 0xd3, 0x4a, 0x8f, 0xe2, 0xd8, 0x09, 0xf3, ++ 0xe9, 0x33, 0xd9, 0xc2, 0x87, 0xfb, 0xcd, 0xe7, 0x6f, 0x82, 0x9e, 0x6a, ++ 0x82, 0x3c, 0x13, 0x09, 0xae, 0x62, 0xfe, 0xbd, 0x82, 0x9f, 0xc9, 0x7a, ++ 0x2b, 0x3b, 0xee, 0x37, 0x22, 0xbe, 0xa0, 0xde, 0x45, 0x92, 0x5f, 0x7e, ++ 0x1b, 0xc2, 0x48, 0x6f, 0xc6, 0x7a, 0xff, 0x80, 0xf3, 0x3c, 0xb7, 0x2d, ++ 0xdb, 0x8e, 0xfa, 0xbd, 0x95, 0x9e, 0xfd, 0xf5, 0x74, 0xfe, 0xef, 0x0d, ++ 0xb1, 0x8e, 0x86, 0x75, 0x7c, 0x21, 0xf4, 0xfc, 0xb2, 0x1f, 0x63, 0x36, ++ 0xdf, 0x4f, 0xc6, 0x6c, 0x2e, 0x6f, 0x9c, 0x13, 0xfa, 0xdc, 0x73, 0xcf, ++ 0xa8, 0xc4, 0x87, 0x70, 0x9e, 0xb8, 0x0f, 0xbf, 0x40, 0x39, 0xd7, 0x6f, ++ 0x9e, 0x16, 0xd1, 0xce, 0x22, 0xe0, 0xf6, 0x1c, 0xee, 0xc7, 0x5c, 0x5f, ++ 0xfd, 0x95, 0x9e, 0xee, 0xb0, 0x54, 0xa8, 0xff, 0xe9, 0xe1, 0x77, 0x29, ++ 0x8d, 0xce, 0xe6, 0xeb, 0x5a, 0x69, 0xe9, 0x9c, 0x80, 0xe7, 0xe6, 0xa7, ++ 0x07, 0x42, 0xe6, 0xb8, 0x29, 0x7d, 0x74, 0xf6, 0x4b, 0x30, 0xde, 0x05, ++ 0xcf, 0x8c, 0x28, 0xc5, 0x6f, 0x5f, 0xa5, 0x64, 0x1b, 0x38, 0x3e, 0xb6, ++ 0xa9, 0x73, 0x10, 0x5e, 0xcc, 0x3d, 0x4c, 0xc8, 0xf9, 0x1e, 0x5a, 0xcf, ++ 0xb9, 0xbd, 0xf1, 0x0a, 0xdd, 0x6f, 0x11, 0xde, 0x20, 0xe7, 0x9f, 0x3b, ++ 0xf0, 0x5c, 0x98, 0x8e, 0xf6, 0xad, 0x4b, 0x83, 0x47, 0x9d, 0x89, 0xeb, ++ 0x69, 0x83, 0x22, 0x6c, 0x42, 0xce, 0x34, 0xb5, 0xa2, 0xbc, 0xb1, 0x14, ++ 0xa4, 0xbb, 0x70, 0xe0, 0x77, 0x75, 0x07, 0x2e, 0xd1, 0xf9, 0x1b, 0xf8, ++ 0x5d, 0xd6, 0xa7, 0xfd, 0x16, 0x87, 0xf7, 0xef, 0x5e, 0xd2, 0x6b, 0xc0, ++ 0x9f, 0x0e, 0xe9, 0xb7, 0xce, 0xca, 0x71, 0x5e, 0xa4, 0x66, 0xc4, 0xe0, ++ 0x3e, 0x28, 0xbd, 0xda, 0x76, 0xd3, 0xcd, 0xc8, 0xc7, 0xde, 0x30, 0x70, ++ 0x3c, 0x8c, 0xb4, 0x3d, 0x84, 0xf7, 0xaa, 0xd2, 0xb7, 0x87, 0x91, 0xde, ++ 0x62, 0x8d, 0xc1, 0x16, 0x83, 0xf9, 0x2f, 0xdf, 0x84, 0x8b, 0x20, 0xcc, ++ 0xbb, 0x34, 0x5b, 0xec, 0xef, 0xd8, 0xae, 0x5c, 0xd4, 0x73, 0x76, 0x27, ++ 0xf1, 0x73, 0xbd, 0x76, 0x33, 0x5c, 0x54, 0x60, 0x3d, 0x23, 0x00, 0xef, ++ 0x2e, 0x58, 0x72, 0xad, 0x5b, 0x65, 0x4e, 0xc8, 0xab, 0xe2, 0x3e, 0x73, ++ 0x4d, 0x76, 0x32, 0xad, 0xef, 0x91, 0x2a, 0x9d, 0xc3, 0x48, 0x76, 0x16, ++ 0x6f, 0x1a, 0xea, 0x3d, 0x4f, 0x1a, 0x99, 0x4b, 0x45, 0x79, 0xf9, 0x59, ++ 0x33, 0xb7, 0x07, 0x24, 0x73, 0xbd, 0xfe, 0x23, 0x48, 0xef, 0x90, 0xd6, ++ 0x46, 0x7a, 0xd3, 0x86, 0xa1, 0xfe, 0x4b, 0xe0, 0xb1, 0x76, 0x3e, 0x94, ++ 0xfb, 0xe1, 0xb3, 0xf6, 0x49, 0x6f, 0x1a, 0xca, 0x2f, 0xe7, 0x8d, 0x5c, ++ 0xcf, 0x87, 0xe5, 0x56, 0x4c, 0xb3, 0x78, 0xbd, 0x66, 0x41, 0x37, 0xd8, ++ 0x0f, 0xf6, 0xdb, 0x9d, 0x64, 0xbd, 0x48, 0x72, 0xe6, 0xc1, 0x50, 0x86, ++ 0xf2, 0xbe, 0xee, 0xf9, 0x50, 0xae, 0x57, 0xf8, 0x8d, 0xf9, 0xc9, 0x20, ++ 0xbf, 0x73, 0x73, 0x89, 0xa0, 0x2b, 0x90, 0x99, 0x5c, 0xb8, 0x7e, 0xd7, ++ 0x4e, 0x3e, 0x3f, 0x9c, 0x17, 0xca, 0xcf, 0x2b, 0x8d, 0xad, 0x69, 0x28, ++ 0x5f, 0xca, 0x71, 0x57, 0x86, 0xb5, 0xd2, 0x78, 0xe7, 0xc5, 0x78, 0x2b, ++ 0x83, 0x5b, 0xb9, 0x7d, 0xc2, 0xc8, 0xf5, 0x91, 0x58, 0x9f, 0xc6, 0x37, ++ 0x30, 0xb2, 0xa3, 0xf4, 0xee, 0x09, 0x22, 0x39, 0xf5, 0x8b, 0xb8, 0xce, ++ 0x43, 0x38, 0xfe, 0x17, 0x7b, 0xc6, 0x32, 0x3c, 0xc7, 0xbb, 0x93, 0xdc, ++ 0x95, 0x87, 0xa9, 0x1c, 0xe4, 0x37, 0xc0, 0x47, 0xf5, 0x53, 0x41, 0x5e, ++ 0x9c, 0xef, 0xe7, 0x7b, 0x42, 0xdd, 0x0c, 0xea, 0x7f, 0x6e, 0xe0, 0xf2, ++ 0xd0, 0xe7, 0xa1, 0xd1, 0x24, 0x0f, 0x9d, 0x08, 0x7d, 0xb0, 0x94, 0xec, ++ 0x32, 0x3b, 0x82, 0x14, 0xd4, 0xab, 0x7c, 0xae, 0x30, 0x63, 0x2c, 0x96, ++ 0xef, 0xe4, 0x76, 0x8c, 0xea, 0xa6, 0x46, 0xb2, 0x3f, 0x54, 0xc3, 0x76, ++ 0x67, 0x59, 0x94, 0xce, 0x61, 0x91, 0x58, 0x3e, 0x96, 0xf4, 0x2d, 0x9f, ++ 0xff, 0x1e, 0xf6, 0xa9, 0x42, 0xdf, 0x37, 0xe3, 0x77, 0x27, 0x6b, 0x2d, ++ 0xbd, 0x1d, 0xf7, 0xdd, 0xee, 0x10, 0xd2, 0xbb, 0x7d, 0xf1, 0xd4, 0xff, ++ 0x1a, 0x3b, 0x98, 0xdd, 0xa2, 0x7a, 0x87, 0x56, 0xbf, 0x24, 0xe9, 0x40, ++ 0x96, 0xdf, 0x9e, 0xcd, 0xef, 0x1b, 0xb7, 0x67, 0xf3, 0x7b, 0xc1, 0x1d, ++ 0xd9, 0xfc, 0x9c, 0xa9, 0x0b, 0xf1, 0x3c, 0x98, 0x4c, 0xeb, 0xe4, 0xfb, ++ 0x15, 0xf0, 0x40, 0xf7, 0x2e, 0xd8, 0x1f, 0xd1, 0xa8, 0xef, 0x3e, 0xe9, ++ 0x79, 0x21, 0x5a, 0xb1, 0x20, 0x9c, 0xbd, 0x69, 0x8f, 0x22, 0xdc, 0x77, ++ 0xf3, 0xfb, 0xcd, 0x17, 0x7b, 0x0d, 0x64, 0x77, 0xa9, 0x7e, 0x3e, 0xd4, ++ 0x41, 0x7a, 0x9c, 0x4d, 0x93, 0x74, 0x78, 0x5e, 0x54, 0xab, 0x5c, 0x0e, ++ 0xae, 0xd6, 0x01, 0xf8, 0x20, 0x55, 0xee, 0xd8, 0x9d, 0x86, 0x72, 0x76, ++ 0xf3, 0x1e, 0x73, 0x16, 0xc2, 0x03, 0xe0, 0x4d, 0xf7, 0xc8, 0xde, 0x9d, ++ 0xaa, 0x18, 0x87, 0x8f, 0xfb, 0xf9, 0xae, 0x04, 0xae, 0xd7, 0xf7, 0x8a, ++ 0xfc, 0xa1, 0xf1, 0xa4, 0xd7, 0x9f, 0x1b, 0xc9, 0x6e, 0x9d, 0x4f, 0x72, ++ 0xce, 0xb6, 0x09, 0x08, 0xd7, 0xcb, 0x3b, 0x42, 0x74, 0x48, 0x17, 0x30, ++ 0x8e, 0x43, 0x01, 0xf8, 0x54, 0xdf, 0xfe, 0x0b, 0x0e, 0xcf, 0xf0, 0x4a, ++ 0x92, 0xcb, 0x61, 0xff, 0x11, 0xbf, 0xac, 0x15, 0xfc, 0xb2, 0x6e, 0xd3, ++ 0xd4, 0xf0, 0xa9, 0xb8, 0x9f, 0xde, 0x56, 0x19, 0xca, 0x05, 0x97, 0xf5, ++ 0xf6, 0x18, 0xe4, 0x87, 0x81, 0xf0, 0x7a, 0x4b, 0xf0, 0x95, 0x9a, 0x43, ++ 0x8f, 0x19, 0xd1, 0x6e, 0x57, 0x0b, 0xfb, 0xc6, 0x09, 0xfb, 0xa6, 0x46, ++ 0xd8, 0xc7, 0x6a, 0x9e, 0x52, 0x48, 0xae, 0xab, 0xd9, 0x38, 0xf5, 0x21, ++ 0xe2, 0x83, 0x7f, 0x30, 0xb0, 0xd1, 0x30, 0x8f, 0xf3, 0x9e, 0xfb, 0xc3, ++ 0xfc, 0xf1, 0xf1, 0xbc, 0xe0, 0x67, 0xbe, 0xf6, 0x76, 0xaa, 0x5f, 0x03, ++ 0xf5, 0x79, 0xfb, 0x37, 0xc2, 0x68, 0x3e, 0xbb, 0x0c, 0x76, 0x9c, 0x4f, ++ 0x20, 0x1e, 0x7f, 0x70, 0xfb, 0xa7, 0xd4, 0x1f, 0xd4, 0xbe, 0x9f, 0x3e, ++ 0x3c, 0x70, 0xae, 0x4f, 0x18, 0xb8, 0xee, 0xcb, 0xac, 0xf3, 0xdf, 0x3e, ++ 0x42, 0x7e, 0xb2, 0xd7, 0x4c, 0xfa, 0x2b, 0xc0, 0x7b, 0x22, 0xca, 0x1d, ++ 0xe7, 0x0c, 0x9e, 0x4a, 0x5c, 0xf7, 0xb9, 0x7d, 0x66, 0xe2, 0x33, 0xe7, ++ 0x22, 0xf8, 0x7e, 0xff, 0x14, 0xf8, 0xa1, 0x6b, 0x0c, 0xce, 0xe3, 0xba, ++ 0xfb, 0x48, 0xbf, 0xf1, 0xce, 0x02, 0x86, 0xe7, 0xc1, 0x0a, 0xb7, 0xb6, ++ 0x5f, 0x39, 0x6e, 0x87, 0xe0, 0xbf, 0x75, 0xc3, 0xec, 0xe1, 0xa8, 0x27, ++ 0xab, 0x03, 0x3c, 0x60, 0x7f, 0x80, 0x97, 0x9f, 0x52, 0xfb, 0xb7, 0x0d, ++ 0xd4, 0x3e, 0x70, 0x1d, 0x8f, 0x8a, 0x76, 0xfd, 0xfb, 0x73, 0x5f, 0x08, ++ 0xd1, 0xcb, 0xb9, 0x11, 0x1c, 0x1f, 0xe7, 0x9e, 0x19, 0x43, 0xe7, 0x4a, ++ 0x77, 0x04, 0xa7, 0x73, 0x98, 0x6f, 0x22, 0xde, 0x57, 0xce, 0x45, 0xf0, ++ 0x94, 0xa1, 0x30, 0x02, 0x74, 0x50, 0x2d, 0xee, 0xa3, 0xe7, 0x66, 0x78, ++ 0xe8, 0xfe, 0x7d, 0x4e, 0xd9, 0x4f, 0x69, 0xb7, 0x81, 0xb7, 0xab, 0x6e, ++ 0x14, 0x76, 0x63, 0xa0, 0xbb, 0x58, 0xa4, 0x1b, 0xa4, 0x49, 0xb4, 0x87, ++ 0x99, 0xb6, 0x74, 0xa2, 0x3c, 0x81, 0xfa, 0xea, 0x89, 0x59, 0x94, 0x7a, ++ 0x83, 0x22, 0x07, 0xea, 0x9d, 0x91, 0x3e, 0xf1, 0x1c, 0x8a, 0xca, 0xe1, ++ 0xfb, 0x8b, 0xe1, 0x78, 0xd1, 0xc2, 0xfe, 0x41, 0x72, 0x8a, 0xc7, 0x88, ++ 0x7c, 0xd9, 0x29, 0xe4, 0xb8, 0xda, 0xbd, 0x03, 0xed, 0x70, 0x88, 0xdf, ++ 0xda, 0xbd, 0x0a, 0xd9, 0x91, 0x2e, 0x8b, 0x73, 0x10, 0x67, 0x1d, 0x25, ++ 0xf5, 0xe5, 0x40, 0x8f, 0x35, 0x2e, 0xc5, 0x61, 0xc6, 0xf9, 0xb4, 0xac, ++ 0x5e, 0x49, 0x76, 0xa4, 0x86, 0xad, 0x37, 0x23, 0xbd, 0xcb, 0x75, 0xd4, ++ 0xe8, 0xd9, 0x1c, 0xbc, 0x0f, 0x75, 0x2b, 0x2a, 0xcd, 0xa7, 0xdb, 0x0c, ++ 0xfb, 0x06, 0xe1, 0xe0, 0x3f, 0x9e, 0x9f, 0xdc, 0xf5, 0x77, 0xc1, 0x0f, ++ 0xf0, 0xcf, 0x1a, 0x4d, 0x72, 0x26, 0x09, 0xd7, 0xba, 0x1c, 0x1b, 0xa7, ++ 0x1f, 0xc8, 0xb6, 0x42, 0x7f, 0xb5, 0x2d, 0xca, 0x16, 0x1a, 0x27, 0x49, ++ 0xde, 0x2b, 0xf9, 0xfa, 0x24, 0x9c, 0x00, 0x2c, 0x46, 0xd4, 0x97, 0xc1, ++ 0x7d, 0x9f, 0x97, 0x0f, 0xb1, 0x7e, 0x39, 0xcf, 0xc0, 0xf5, 0xcb, 0xf9, ++ 0x44, 0xe7, 0x70, 0xfe, 0xde, 0x9d, 0x64, 0xbb, 0x2f, 0x1f, 0xf1, 0xfd, ++ 0x96, 0x6a, 0xc7, 0x7b, 0xfa, 0xe5, 0x6f, 0xb3, 0xc3, 0x23, 0xbf, 0x43, ++ 0x2e, 0xc3, 0x9b, 0x5b, 0xbf, 0xde, 0x18, 0xe6, 0x9f, 0x82, 0x34, 0x05, ++ 0xeb, 0x3a, 0x8b, 0xfc, 0x0d, 0xf7, 0x33, 0xea, 0xa5, 0x61, 0x9e, 0x69, ++ 0xdb, 0xb4, 0xf6, 0x90, 0xf4, 0x1d, 0xda, 0xfc, 0x55, 0x7b, 0xb5, 0xf9, ++ 0x8c, 0x03, 0xda, 0xfc, 0x84, 0x0e, 0x6d, 0xde, 0xfe, 0x8a, 0x36, 0x1f, ++ 0x22, 0xc6, 0x95, 0x70, 0xc2, 0x7b, 0xaf, 0x6d, 0x0c, 0xbf, 0xf7, 0x62, ++ 0x8a, 0xf7, 0x5e, 0x5b, 0x10, 0xbf, 0xf7, 0x62, 0x1e, 0xef, 0xbd, 0x98, ++ 0xe2, 0xbd, 0x17, 0xbf, 0xe3, 0xbd, 0x17, 0xf3, 0x78, 0xef, 0xc5, 0x3c, ++ 0xde, 0x7b, 0x31, 0x8f, 0xf7, 0x5e, 0x4c, 0xf1, 0xde, 0x8b, 0xdf, 0x6f, ++ 0x14, 0x70, 0xaa, 0x15, 0x7a, 0x47, 0xc4, 0x03, 0xda, 0x65, 0xd8, 0x0b, ++ 0x66, 0x69, 0x67, 0xa7, 0xfd, 0xd2, 0xb3, 0x24, 0x9a, 0xf8, 0xa7, 0xb4, ++ 0x93, 0xf6, 0xac, 0xcc, 0xa0, 0x7c, 0xbf, 0x5e, 0x67, 0x9e, 0x89, 0xf4, ++ 0x3a, 0xa4, 0xbb, 0x01, 0xb9, 0x64, 0xc1, 0x48, 0x67, 0x41, 0xce, 0x70, ++ 0xb4, 0x9f, 0x76, 0x6e, 0x8c, 0x43, 0xbc, 0xe9, 0xbb, 0x48, 0x9f, 0xbb, ++ 0xea, 0x45, 0xae, 0xcf, 0xad, 0xcd, 0x32, 0x5b, 0x50, 0xcf, 0xd0, 0xb5, ++ 0xe1, 0xd3, 0x8d, 0x28, 0x3e, 0xa5, 0x8d, 0x74, 0xce, 0xca, 0x81, 0xf5, ++ 0xf6, 0x18, 0x7a, 0x77, 0x11, 0x1d, 0xe8, 0xbd, 0xc4, 0x37, 0xba, 0xd6, ++ 0xdb, 0xde, 0x9e, 0xce, 0xf1, 0x47, 0xfa, 0x0e, 0x66, 0x89, 0xa4, 0xfb, ++ 0x49, 0x19, 0x9e, 0x77, 0x91, 0x43, 0xe3, 0x31, 0xd0, 0xae, 0xc2, 0xb6, ++ 0x68, 0xed, 0x28, 0x81, 0x76, 0x95, 0x40, 0x7b, 0x4a, 0x20, 0x1d, 0x48, ++ 0x3b, 0xca, 0x13, 0x86, 0xde, 0x38, 0xe4, 0xf7, 0xa7, 0xf7, 0x98, 0xb6, ++ 0xe0, 0xfc, 0x4f, 0x0b, 0x3d, 0x19, 0x5b, 0x6c, 0x22, 0xf9, 0x4b, 0xca, ++ 0xd5, 0x45, 0xaa, 0x85, 0xe0, 0xb4, 0xe6, 0x5e, 0xe5, 0x49, 0x3c, 0xa7, ++ 0x2a, 0x72, 0x22, 0xa9, 0x7d, 0xdf, 0x09, 0x90, 0xb7, 0x07, 0x39, 0x6f, ++ 0x65, 0x5a, 0x7e, 0x25, 0x9b, 0xe4, 0xea, 0xfe, 0xfc, 0x16, 0x45, 0x47, ++ 0x76, 0x1a, 0xa7, 0x83, 0xce, 0xa1, 0xdb, 0xc4, 0x9c, 0x12, 0x95, 0xde, ++ 0xee, 0x4d, 0x48, 0x23, 0xa1, 0x3a, 0x3a, 0xc7, 0x2f, 0x5b, 0x74, 0x74, ++ 0x2f, 0xb8, 0xfc, 0x27, 0x95, 0xe4, 0x88, 0x31, 0xed, 0x3a, 0xcd, 0x7a, ++ 0xc6, 0xba, 0x83, 0x35, 0xf4, 0x35, 0x6e, 0x77, 0x64, 0x80, 0x3d, 0x70, ++ 0x84, 0xa6, 0xfe, 0xd5, 0x87, 0x93, 0x03, 0xec, 0x81, 0x57, 0x69, 0xed, ++ 0x54, 0x37, 0xae, 0x3f, 0x8a, 0xf7, 0xeb, 0x05, 0x5b, 0xb2, 0x35, 0xf5, ++ 0x2a, 0x8a, 0xa7, 0x06, 0xc0, 0x51, 0xcc, 0x5b, 0xc8, 0xa5, 0xcd, 0xeb, ++ 0xda, 0x13, 0x91, 0xff, 0xdc, 0x16, 0xda, 0x47, 0xf3, 0xbf, 0xed, 0xa0, ++ 0x99, 0xfc, 0x2e, 0x2a, 0xe0, 0x7c, 0x71, 0xc0, 0xba, 0xab, 0x30, 0x03, ++ 0xfc, 0xb1, 0xca, 0xe4, 0xb8, 0x01, 0xe1, 0x57, 0xe5, 0x31, 0x44, 0xa0, ++ 0x5e, 0xab, 0x5c, 0x9c, 0x3f, 0xac, 0x51, 0x7b, 0x1e, 0x57, 0xe9, 0x99, ++ 0xcb, 0x1a, 0xe9, 0xa3, 0xbb, 0x2a, 0x2b, 0x73, 0x44, 0x40, 0xfb, 0x0b, ++ 0x99, 0xad, 0xbb, 0x74, 0x80, 0xb7, 0x0b, 0xba, 0x6d, 0x0f, 0xe6, 0xdb, ++ 0xd0, 0xbe, 0xb4, 0x3d, 0xd1, 0x0a, 0x74, 0xb5, 0x56, 0xf1, 0x44, 0x4f, ++ 0x86, 0xfe, 0x4e, 0x47, 0x38, 0xff, 0x03, 0xe9, 0x33, 0xd1, 0xe0, 0xfd, ++ 0x55, 0x09, 0xf2, 0xcb, 0xfd, 0x29, 0x6c, 0x3d, 0xd4, 0x3b, 0xbd, 0xe5, ++ 0xb9, 0x30, 0x92, 0xbb, 0x05, 0x9d, 0x25, 0x1a, 0xac, 0xc1, 0x88, 0xef, ++ 0xed, 0xad, 0x2a, 0xdd, 0x0b, 0x50, 0x3f, 0x85, 0xfa, 0x20, 0x49, 0x0f, ++ 0xdb, 0x5b, 0x87, 0x05, 0xa7, 0x5a, 0x7c, 0xeb, 0xf4, 0xe1, 0xff, 0x5b, ++ 0x5a, 0x1f, 0xe0, 0x85, 0xfc, 0x46, 0xfa, 0x2c, 0xc7, 0x46, 0xde, 0x86, ++ 0x72, 0x9c, 0x87, 0xaf, 0xb7, 0x6a, 0x86, 0xe2, 0x22, 0x39, 0x59, 0xac, ++ 0x67, 0x8d, 0x38, 0x57, 0x58, 0x0b, 0xef, 0x67, 0xad, 0xc8, 0x9f, 0x11, ++ 0xf7, 0x05, 0xb9, 0xbe, 0xf3, 0x63, 0x8f, 0x4e, 0xb0, 0xa1, 0x5d, 0xb3, ++ 0xe9, 0x70, 0xa2, 0x8a, 0x7c, 0x5c, 0xb7, 0x77, 0x57, 0x1c, 0xca, 0x17, ++ 0x31, 0xce, 0x7d, 0xb8, 0x7f, 0xaa, 0xb6, 0x8f, 0xfe, 0xaf, 0x7c, 0x18, ++ 0xb7, 0xfa, 0x3d, 0x95, 0xa1, 0x1d, 0xf9, 0x93, 0xb6, 0x59, 0x61, 0x93, ++ 0x51, 0xfe, 0xdc, 0x67, 0xb0, 0xcf, 0x85, 0xfc, 0xa6, 0xd6, 0x5f, 0x1b, ++ 0xf1, 0x5e, 0x50, 0xad, 0x77, 0x1b, 0xf1, 0xde, 0x59, 0xb5, 0x67, 0xbb, ++ 0x11, 0xed, 0xff, 0x3f, 0xd9, 0xbd, 0x9d, 0xbe, 0x57, 0xee, 0x2e, 0xa3, ++ 0xfb, 0xf6, 0x0a, 0xd6, 0x40, 0xf7, 0xc8, 0xcf, 0x0c, 0xfc, 0x9c, 0x96, ++ 0xf0, 0xa8, 0x9a, 0xa9, 0x6c, 0xb3, 0xc2, 0xbc, 0x87, 0xe7, 0x72, 0xb9, ++ 0xaf, 0x2a, 0x98, 0xfb, 0x83, 0x14, 0xa9, 0xf9, 0xaf, 0x46, 0xe1, 0x7a, ++ 0x77, 0x2b, 0x99, 0xb8, 0xde, 0x1b, 0x8b, 0xf7, 0x1b, 0xcb, 0xe0, 0xfb, ++ 0xef, 0x04, 0x7f, 0x09, 0xdc, 0x1f, 0x7d, 0x6f, 0x2e, 0x28, 0x1a, 0x8e, ++ 0x7a, 0x25, 0x0f, 0xb7, 0x83, 0x0e, 0xb5, 0x1f, 0x16, 0x7a, 0xc7, 0xd2, ++ 0x7e, 0x58, 0x70, 0x25, 0x89, 0xd2, 0x1b, 0xaf, 0x8c, 0xa3, 0x7b, 0xd5, ++ 0x7b, 0xac, 0x78, 0x3c, 0xf1, 0x89, 0x8c, 0x80, 0xfb, 0xec, 0x9b, 0x2a, ++ 0xd7, 0x9b, 0x75, 0xf0, 0x7d, 0x50, 0x65, 0xf4, 0x46, 0x2d, 0xc0, 0x7d, ++ 0xf2, 0xb2, 0x81, 0xf6, 0x49, 0x1d, 0xf0, 0xaf, 0xbc, 0x2c, 0xbc, 0x27, ++ 0x33, 0x36, 0x05, 0xd2, 0xe2, 0x7c, 0x55, 0x43, 0xaf, 0xab, 0x0a, 0x43, ++ 0x34, 0xf4, 0xbc, 0x98, 0x45, 0x6a, 0xec, 0xca, 0x8b, 0xd8, 0x08, 0x4d, ++ 0xfe, 0xc6, 0xb9, 0x29, 0x9a, 0xfa, 0x37, 0xdd, 0x38, 0x2e, 0x80, 0xfe, ++ 0xb3, 0x7c, 0xe5, 0xc4, 0x47, 0xa6, 0x68, 0xfc, 0x57, 0xea, 0xd6, 0xb9, ++ 0x6c, 0x0a, 0xe9, 0xd1, 0x66, 0x6a, 0xbf, 0x43, 0xba, 0x8e, 0xe8, 0xec, ++ 0x5a, 0x4d, 0xfb, 0x3a, 0x36, 0xdf, 0x57, 0x0f, 0xef, 0xc1, 0x3b, 0xfe, ++ 0x48, 0x70, 0x66, 0xac, 0xd3, 0x88, 0xf7, 0xad, 0x2a, 0x1d, 0xf7, 0xd7, ++ 0x59, 0xec, 0xec, 0x16, 0xdf, 0xbb, 0xe8, 0x3b, 0x2c, 0x44, 0xb3, 0x0f, ++ 0x47, 0xa5, 0xd8, 0xff, 0x8b, 0x9f, 0x8b, 0x06, 0xd2, 0xcf, 0x4b, 0xfd, ++ 0xf4, 0x62, 0xfc, 0x77, 0xca, 0x60, 0xe7, 0x22, 0x20, 0x5a, 0x8c, 0x1b, ++ 0xae, 0x72, 0xfd, 0x82, 0x53, 0x2b, 0x77, 0x74, 0xd2, 0xfd, 0x93, 0x71, ++ 0x3c, 0xd4, 0x09, 0x7d, 0x4f, 0x5d, 0x3a, 0xd7, 0xf7, 0xd4, 0xb9, 0x3a, ++ 0x8d, 0x0d, 0x16, 0x82, 0xbf, 0x3e, 0x1e, 0x40, 0x52, 0xdf, 0xaa, 0x90, ++ 0x3e, 0x0f, 0xea, 0x9b, 0xe2, 0x23, 0x79, 0x7e, 0x1d, 0x7e, 0x3f, 0x60, ++ 0xf0, 0xe9, 0x59, 0x18, 0xef, 0xef, 0x0a, 0x96, 0x9f, 0x50, 0xcb, 0x70, ++ 0xbf, 0x04, 0x96, 0xd7, 0xc3, 0xba, 0x51, 0xce, 0xa8, 0x47, 0x7d, 0x0d, ++ 0xe9, 0x99, 0xe6, 0x7c, 0x4a, 0x7a, 0x26, 0x39, 0x8e, 0xe8, 0x5f, 0xd2, ++ 0xe9, 0x8a, 0x76, 0xad, 0xfe, 0xa8, 0x1e, 0xf5, 0x3a, 0x7e, 0xf8, 0x5c, ++ 0x9a, 0x6b, 0x23, 0x7a, 0xad, 0xde, 0xbd, 0xff, 0xb5, 0x11, 0x00, 0x9f, ++ 0x05, 0xc5, 0x11, 0x99, 0xb8, 0x8f, 0x6a, 0x3d, 0xf3, 0x0c, 0x65, 0x19, ++ 0x03, 0xe9, 0x4d, 0xf2, 0xf9, 0xcb, 0x55, 0x3a, 0xb2, 0x7b, 0xf7, 0xbd, ++ 0x79, 0x9c, 0xe8, 0xad, 0xaf, 0x4a, 0x4f, 0x74, 0xfd, 0x7d, 0x70, 0xa9, ++ 0x77, 0x70, 0xbd, 0x66, 0x20, 0x1d, 0x56, 0xc2, 0xba, 0x4c, 0x30, 0x7e, ++ 0xe5, 0x01, 0xc5, 0xee, 0x56, 0x78, 0x3d, 0x84, 0xcf, 0x08, 0xa4, 0xcf, ++ 0x00, 0xf8, 0xc4, 0x0f, 0x02, 0x37, 0x09, 0xaf, 0x7e, 0xf8, 0x05, 0x94, ++ 0xaf, 0xc0, 0x7f, 0xe4, 0xa0, 0x3f, 0x81, 0xe2, 0xf6, 0x26, 0x0d, 0x06, ++ 0x97, 0x00, 0x78, 0xca, 0x71, 0x02, 0xe0, 0xc5, 0xf2, 0xb4, 0xf0, 0xa8, ++ 0x74, 0xda, 0xde, 0x46, 0xfe, 0x53, 0x79, 0x42, 0x65, 0xee, 0x1f, 0xb0, ++ 0xfe, 0x15, 0xb8, 0x4e, 0x9c, 0x07, 0xac, 0x13, 0xe7, 0x31, 0xff, 0x0a, ++ 0xd7, 0x9b, 0x48, 0x7b, 0xc2, 0xa2, 0x2b, 0x7a, 0xca, 0xf7, 0xd3, 0x4d, ++ 0x31, 0xc0, 0x2b, 0x0b, 0xf7, 0x9d, 0x76, 0x9f, 0xf6, 0xd3, 0x51, 0x31, ++ 0xdf, 0x37, 0x0b, 0xaf, 0x44, 0x53, 0xbb, 0x1f, 0x8b, 0x9e, 0xbe, 0x8f, ++ 0x8e, 0xe4, 0xfc, 0x25, 0xdf, 0xf6, 0xed, 0xa3, 0x3b, 0x89, 0x6f, 0x3a, ++ 0x73, 0x43, 0xa3, 0xce, 0x02, 0xab, 0x80, 0x7f, 0xe7, 0x12, 0x5f, 0x10, ++ 0xfc, 0x75, 0x68, 0xb9, 0xd4, 0xc5, 0xf9, 0xa8, 0x53, 0x7b, 0xce, 0x8c, ++ 0xba, 0x23, 0x8f, 0xfc, 0x8e, 0xfa, 0x2c, 0xc9, 0x24, 0x57, 0xf4, 0x9f, ++ 0x43, 0x56, 0x6d, 0xf9, 0x9a, 0xd0, 0xe4, 0x18, 0x2c, 0x77, 0x0a, 0xbd, ++ 0x9d, 0xe4, 0xc7, 0x4e, 0x51, 0x4f, 0x8e, 0x53, 0x06, 0xe5, 0xb6, 0x61, ++ 0x48, 0xd7, 0x23, 0xa3, 0x51, 0x1f, 0xbb, 0xb1, 0x25, 0x25, 0xb1, 0xcb, ++ 0x4f, 0x5e, 0x71, 0x6e, 0x30, 0x44, 0xa3, 0xbe, 0x30, 0x71, 0xfd, 0x30, ++ 0x4a, 0xcb, 0xcc, 0xd6, 0x68, 0x3c, 0x47, 0xca, 0xd6, 0xab, 0xc5, 0x78, ++ 0x3e, 0x9e, 0xba, 0x2b, 0x26, 0x3a, 0x0f, 0xf5, 0xf3, 0x1b, 0x0c, 0x51, ++ 0x73, 0xa1, 0xeb, 0x53, 0x3f, 0xcf, 0x49, 0x64, 0xe3, 0x31, 0x5f, 0x44, ++ 0xe9, 0xe9, 0xad, 0x41, 0x8b, 0xfd, 0xf5, 0xdc, 0x32, 0xbd, 0x4b, 0x9c, ++ 0x27, 0x75, 0x77, 0x7c, 0x40, 0xe7, 0xda, 0x05, 0xdd, 0x9b, 0x61, 0x8b, ++ 0x71, 0xdf, 0x6d, 0x38, 0x18, 0x86, 0xae, 0x37, 0x35, 0x1b, 0xde, 0x9d, ++ 0x68, 0x05, 0x91, 0x64, 0x53, 0x84, 0x73, 0x73, 0x2e, 0xd9, 0x51, 0xb7, ++ 0xef, 0xb2, 0x22, 0xdc, 0xac, 0xdb, 0x27, 0xa0, 0x9e, 0xba, 0x1d, 0xef, ++ 0x1e, 0xc3, 0x7d, 0xf2, 0x43, 0xf5, 0x86, 0xa2, 0x18, 0xd4, 0x8b, 0xd5, ++ 0xfe, 0xfd, 0xf8, 0xe3, 0x78, 0xee, 0x3b, 0xd7, 0x1b, 0xa2, 0x51, 0xfe, ++ 0xfc, 0xfc, 0x4f, 0x70, 0x2e, 0x2a, 0x74, 0xae, 0x91, 0xdc, 0xf0, 0x99, ++ 0x99, 0xd1, 0x7d, 0xe9, 0xb3, 0x9d, 0x21, 0x6e, 0xb4, 0xdf, 0x7f, 0xa6, ++ 0x30, 0x07, 0xda, 0x77, 0x56, 0xaa, 0x47, 0x27, 0x58, 0x35, 0xe7, 0x6c, ++ 0xc7, 0x22, 0x9c, 0xc7, 0xee, 0x18, 0x67, 0x3b, 0x1f, 0xdf, 0xbd, 0x2b, ++ 0x16, 0xc7, 0xb7, 0xbb, 0xc8, 0x3f, 0xd3, 0xb9, 0x7e, 0x74, 0xf8, 0x60, ++ 0x7a, 0x14, 0x99, 0xae, 0x6a, 0xe7, 0x72, 0xdd, 0x2e, 0xa9, 0xc7, 0x15, ++ 0xfa, 0x5e, 0x94, 0xe7, 0x31, 0x8f, 0xf2, 0x3c, 0x1b, 0xc3, 0xe5, 0x79, ++ 0xcc, 0xa3, 0x3c, 0x8f, 0x29, 0xca, 0xf3, 0xf8, 0xfd, 0x90, 0xd0, 0xe3, ++ 0x8f, 0x6a, 0xee, 0xcd, 0xc4, 0xfb, 0xa8, 0x6b, 0x26, 0x4b, 0x6f, 0xa0, ++ 0x73, 0xd7, 0x92, 0x8e, 0xf2, 0xfa, 0x6d, 0x4a, 0xb0, 0x1d, 0xf9, 0xcf, ++ 0x6d, 0x8a, 0x3d, 0x06, 0xf5, 0x63, 0xec, 0x4f, 0x11, 0xfc, 0xbc, 0x0d, ++ 0xc0, 0xaf, 0x4c, 0xa7, 0xf5, 0x82, 0xcc, 0xe5, 0x47, 0xf7, 0xd3, 0xaf, ++ 0x98, 0x98, 0xbf, 0x9f, 0xd9, 0x0c, 0x16, 0xa1, 0xc9, 0xcf, 0x32, 0xc5, ++ 0x69, 0xea, 0x17, 0x59, 0x93, 0x34, 0xe5, 0x3f, 0x89, 0x1d, 0xab, 0x29, ++ 0xbf, 0xc6, 0x96, 0xa9, 0xc9, 0x5f, 0x97, 0x3e, 0x59, 0x53, 0xff, 0x7a, ++ 0xfb, 0x0c, 0x4d, 0xfe, 0xa7, 0x79, 0xd7, 0x68, 0xea, 0xcf, 0x73, 0xcc, ++ 0xd3, 0xe4, 0x17, 0xcc, 0x59, 0xa2, 0xa9, 0xbf, 0xb0, 0xb8, 0x4c, 0x53, ++ 0x7e, 0xd3, 0xe2, 0x95, 0x9a, 0xf2, 0x25, 0xce, 0xd5, 0x9a, 0xfc, 0xcd, ++ 0x55, 0x3f, 0xd7, 0xd4, 0xbf, 0xa5, 0x61, 0xbd, 0xa6, 0xdc, 0xc1, 0xac, ++ 0x7a, 0x3c, 0xf7, 0x3a, 0xf0, 0x9e, 0x05, 0x70, 0x7f, 0x19, 0xef, 0x59, ++ 0x90, 0xde, 0xf6, 0xd6, 0x68, 0x8b, 0x3f, 0x5e, 0xf3, 0x67, 0xe9, 0x1a, ++ 0x06, 0xd3, 0xd3, 0x7f, 0x2c, 0xe8, 0x37, 0x63, 0x92, 0xe3, 0x43, 0xa4, ++ 0x8f, 0x04, 0x1d, 0xa7, 0x43, 0x48, 0x1d, 0x28, 0x42, 0x5c, 0x10, 0xe7, ++ 0x4a, 0x3c, 0xf3, 0x2a, 0xfc, 0x9e, 0xdb, 0x19, 0x87, 0x74, 0x13, 0x58, ++ 0x2f, 0xb0, 0x3c, 0x3f, 0xe4, 0xd8, 0x65, 0x1b, 0xe0, 0xf0, 0xa6, 0x89, ++ 0x21, 0x37, 0xeb, 0x81, 0x3f, 0xe4, 0x4f, 0x3a, 0x96, 0x9d, 0x02, 0xf9, ++ 0x27, 0x0e, 0xcd, 0xe3, 0xf9, 0xa9, 0xc7, 0x9e, 0x4b, 0x86, 0xfc, 0x6f, ++ 0x26, 0xde, 0xc7, 0xf3, 0x57, 0x1f, 0xbb, 0x8c, 0xe5, 0xa3, 0x9e, 0x5f, ++ 0x74, 0xb3, 0x1e, 0xf8, 0x4e, 0xfe, 0x02, 0x46, 0x22, 0xc7, 0x73, 0x87, ++ 0xbe, 0x5e, 0xea, 0x82, 0x75, 0xe4, 0x4f, 0x4f, 0xde, 0x62, 0xe7, 0x7a, ++ 0x92, 0x41, 0xfd, 0x34, 0xfb, 0xf5, 0x2c, 0x00, 0x07, 0xf4, 0x6f, 0x44, ++ 0x38, 0x60, 0xea, 0x05, 0xfa, 0xc4, 0xf4, 0x18, 0xd0, 0x27, 0xa6, 0xaf, ++ 0x00, 0x7d, 0x56, 0x18, 0x18, 0x7b, 0x0d, 0xe8, 0x13, 0xd3, 0x13, 0x70, ++ 0xdf, 0xc4, 0xef, 0xaf, 0xc3, 0x7d, 0x13, 0xd3, 0x37, 0xe1, 0xbe, 0x89, ++ 0xe9, 0x1f, 0xe0, 0xbe, 0x89, 0x69, 0x27, 0xdc, 0x37, 0x31, 0x7d, 0xa7, ++ 0x69, 0x31, 0xa5, 0x7f, 0x6a, 0x72, 0x52, 0xbb, 0xf7, 0x9b, 0xaa, 0x28, ++ 0xfd, 0xa0, 0xa9, 0x81, 0xbe, 0x7f, 0xd8, 0xd4, 0x48, 0xe9, 0x5f, 0x9a, ++ 0x5c, 0xf4, 0xdd, 0x3c, 0x51, 0xea, 0x2f, 0xbc, 0xa4, 0x7f, 0x91, 0x76, ++ 0xa6, 0x7a, 0xb4, 0xef, 0xa1, 0x7e, 0xee, 0xb0, 0xe1, 0xbc, 0xbf, 0x1d, ++ 0x56, 0xda, 0x09, 0xa5, 0x5d, 0xb0, 0xb9, 0x81, 0x75, 0x85, 0xe0, 0x3e, ++ 0xed, 0xd2, 0x47, 0x9c, 0x35, 0xf9, 0xec, 0x7d, 0x43, 0xf3, 0x59, 0x3d, ++ 0x3b, 0xeb, 0x27, 0x87, 0x6d, 0x8d, 0x75, 0x44, 0x4d, 0x24, 0xbd, 0xc6, ++ 0x48, 0x2b, 0xd9, 0x7b, 0xc4, 0xf7, 0x99, 0xca, 0x82, 0x04, 0x34, 0xfd, ++ 0xcd, 0x9d, 0xe0, 0x1c, 0x81, 0xe5, 0x0b, 0xb3, 0xca, 0x37, 0x84, 0x03, ++ 0xff, 0x98, 0xfe, 0x6d, 0x83, 0x01, 0xe9, 0xe5, 0x3d, 0xe1, 0xa7, 0x1a, ++ 0xd8, 0xff, 0x85, 0x5c, 0x2e, 0x0f, 0x1b, 0x26, 0x39, 0x46, 0x4d, 0x84, ++ 0xb4, 0xc0, 0xc4, 0xfd, 0xf0, 0x0a, 0x4c, 0xdc, 0xcf, 0xae, 0x40, 0xdf, ++ 0xd5, 0x8c, 0xfc, 0xa8, 0xf9, 0x2b, 0x66, 0x43, 0x3f, 0x9a, 0xa3, 0xa1, ++ 0x46, 0xe2, 0x4f, 0xcd, 0x77, 0xe9, 0xdd, 0xa8, 0xa7, 0x54, 0xbe, 0x64, ++ 0x94, 0x9f, 0x16, 0xc5, 0x28, 0xdf, 0xfc, 0x55, 0x27, 0xf9, 0xe5, 0x15, ++ 0x58, 0xed, 0xb1, 0x74, 0xde, 0x88, 0x7c, 0xbf, 0xfd, 0x1c, 0xff, 0xfc, ++ 0xfc, 0x65, 0xa4, 0x3d, 0x5b, 0xfa, 0xc9, 0x14, 0x7e, 0xd9, 0x35, 0x0b, ++ 0xe5, 0x80, 0x69, 0x16, 0xa3, 0x2d, 0x28, 0xc0, 0xfe, 0x8e, 0x76, 0xeb, ++ 0xa3, 0xa1, 0xef, 0xcb, 0xf9, 0x30, 0x1c, 0x4f, 0xda, 0xc9, 0x77, 0x7c, ++ 0xc5, 0xbc, 0xba, 0x09, 0x3e, 0x7b, 0x78, 0x81, 0xa9, 0x33, 0x09, 0xf5, ++ 0x04, 0xd3, 0xd6, 0x9a, 0xec, 0xfe, 0xfe, 0x3f, 0xd2, 0xee, 0xad, 0x7c, ++ 0xd9, 0xa9, 0xe2, 0x79, 0x22, 0xfd, 0x7c, 0xe4, 0x38, 0x72, 0xbe, 0xa1, ++ 0x7a, 0xe8, 0x2f, 0xcb, 0xe7, 0xc7, 0x53, 0x60, 0xf5, 0x64, 0xa2, 0x5f, ++ 0x43, 0x73, 0x9d, 0x85, 0xfa, 0x8b, 0x81, 0xef, 0xc6, 0x2c, 0xaa, 0xe7, ++ 0x50, 0xa9, 0x9d, 0x27, 0x13, 0xf5, 0xc0, 0xd3, 0x6a, 0x2d, 0x76, 0xd4, ++ 0x6f, 0x4b, 0x7b, 0x7b, 0x8c, 0x58, 0x37, 0xd4, 0xa3, 0x75, 0x16, 0x7e, ++ 0xe9, 0x24, 0x7f, 0x83, 0x69, 0xc2, 0xdf, 0x00, 0xfb, 0x31, 0xf1, 0x72, ++ 0x17, 0xf6, 0x33, 0x2d, 0xca, 0x1b, 0xa7, 0xc7, 0xf5, 0x37, 0x18, 0xed, ++ 0xa8, 0x0f, 0x7d, 0x4c, 0x81, 0xf6, 0x59, 0x3e, 0xfb, 0x3f, 0xd6, 0x0f, ++ 0xf1, 0xdb, 0xbf, 0x38, 0x4f, 0xec, 0x37, 0xf5, 0x6b, 0x98, 0x2f, 0xca, ++ 0xed, 0x0e, 0x07, 0xc1, 0x77, 0x81, 0xbc, 0xbf, 0xd9, 0x44, 0x5e, 0x9c, ++ 0xcf, 0xcc, 0x34, 0x93, 0xf4, 0x57, 0xaa, 0xc8, 0x1f, 0x9b, 0xe0, 0x74, ++ 0x22, 0xde, 0x8b, 0x83, 0xac, 0x7f, 0x0d, 0xa1, 0x7d, 0x9e, 0x92, 0x80, ++ 0x7a, 0x8e, 0x79, 0x42, 0x6e, 0xff, 0x0e, 0x7a, 0x59, 0x8e, 0x74, 0xf6, ++ 0xdf, 0xa7, 0x17, 0x07, 0xc7, 0xf7, 0x48, 0x46, 0xfa, 0xb4, 0x40, 0xba, ++ 0x91, 0x78, 0x91, 0x78, 0x1e, 0x8a, 0x8e, 0x24, 0xde, 0xfd, 0xfc, 0xb5, ++ 0x08, 0xcf, 0xfd, 0xfe, 0x57, 0xa2, 0x9f, 0x40, 0xfa, 0x1a, 0x8a, 0xae, ++ 0x24, 0x3d, 0x15, 0x98, 0x38, 0xde, 0x11, 0xaf, 0xe8, 0x47, 0x23, 0xe9, ++ 0x48, 0xf9, 0xd2, 0xb3, 0x9d, 0xd6, 0x51, 0x6b, 0xa2, 0x73, 0x4e, 0xd2, ++ 0x51, 0x20, 0x1d, 0x0c, 0xa4, 0x23, 0x4e, 0x97, 0xcd, 0x3f, 0x33, 0x51, ++ 0x7f, 0x03, 0xe9, 0xc8, 0x87, 0x7f, 0x84, 0xc7, 0xbf, 0x4e, 0x47, 0x9d, ++ 0x2a, 0x9e, 0xbb, 0xff, 0x2c, 0xfd, 0xdc, 0xda, 0xcb, 0x66, 0x87, 0x43, ++ 0xd1, 0x2f, 0xae, 0x76, 0x5e, 0xc8, 0x45, 0x7f, 0xa0, 0x2b, 0xb6, 0xd7, ++ 0x30, 0x5f, 0xce, 0x66, 0xcc, 0x46, 0x92, 0x92, 0xe5, 0x2d, 0x43, 0x94, ++ 0x07, 0xd2, 0x97, 0xac, 0xff, 0x34, 0xd6, 0xcf, 0x1d, 0x58, 0xdf, 0xf9, ++ 0x65, 0xaf, 0x21, 0xdc, 0x8f, 0x2e, 0xa7, 0x89, 0x33, 0xf0, 0xf5, 0x21, ++ 0xfa, 0x7f, 0x43, 0xf8, 0xc5, 0xbf, 0x61, 0x96, 0xfe, 0x1e, 0x0e, 0x4b, ++ 0x26, 0xd0, 0xc1, 0x2c, 0xc1, 0x87, 0x6f, 0x2b, 0xe2, 0xf4, 0x35, 0x27, ++ 0x49, 0x25, 0x7b, 0xc6, 0xac, 0x8c, 0x15, 0x24, 0xdf, 0x33, 0x0b, 0x97, ++ 0x8f, 0x6d, 0xf0, 0x3f, 0xd2, 0xb7, 0x09, 0xfb, 0xfa, 0xb5, 0xa2, 0xdd, ++ 0xec, 0x6f, 0x8b, 0x5b, 0x70, 0x9c, 0xd9, 0x51, 0x5a, 0xf9, 0xfb, 0x5a, ++ 0x21, 0x77, 0xcf, 0x09, 0xb0, 0xb7, 0x5f, 0x9b, 0xf1, 0x13, 0x92, 0xc3, ++ 0xaf, 0x0d, 0x90, 0xb3, 0x7f, 0x3f, 0x51, 0xc8, 0xd1, 0x49, 0x2c, 0x89, ++ 0xdf, 0xaf, 0xb7, 0x90, 0xfc, 0x5b, 0x28, 0xf6, 0x63, 0xbc, 0xc0, 0x77, ++ 0x8a, 0x4d, 0x65, 0xf9, 0x00, 0xf7, 0x22, 0xe6, 0xd4, 0xe3, 0x21, 0xf0, ++ 0xca, 0x45, 0xa3, 0x03, 0xfb, 0xfb, 0x09, 0x73, 0x51, 0xfe, 0x1a, 0xe6, ++ 0xa6, 0xf4, 0x3a, 0xe6, 0x25, 0x39, 0xe0, 0x7a, 0x38, 0x30, 0x30, 0xff, ++ 0x53, 0xd8, 0x7a, 0x98, 0x3f, 0x1e, 0x72, 0x43, 0xc9, 0x2a, 0xe8, 0x6f, ++ 0x56, 0xf6, 0xac, 0x54, 0xfc, 0x5e, 0x6b, 0xea, 0x4d, 0x34, 0xea, 0xd0, ++ 0x3b, 0xd0, 0xf9, 0x21, 0xee, 0xe7, 0x7a, 0xd5, 0xf9, 0x31, 0xca, 0x99, ++ 0x17, 0x12, 0x9c, 0x63, 0xf0, 0x7e, 0x7c, 0xac, 0xd0, 0x46, 0x72, 0xd8, ++ 0x31, 0x53, 0x0a, 0xc9, 0x85, 0xb8, 0x9f, 0x0c, 0x7e, 0xfa, 0xca, 0xdf, ++ 0xc3, 0x39, 0x9a, 0x0a, 0xe7, 0xdc, 0x71, 0x38, 0x67, 0x31, 0x7d, 0x15, ++ 0xce, 0xd9, 0x54, 0x38, 0xef, 0x7e, 0x07, 0xe7, 0x2c, 0xe6, 0xaf, 0x4d, ++ 0x5f, 0xcf, 0xb0, 0xdd, 0x6c, 0x9b, 0xd6, 0xbf, 0x47, 0xb6, 0xbf, 0xce, ++ 0x3a, 0x8b, 0xe9, 0x87, 0x0d, 0x7d, 0x8e, 0x5d, 0x37, 0xe1, 0x85, 0x91, ++ 0xa8, 0xc7, 0x7a, 0x23, 0x62, 0x4c, 0x21, 0xe2, 0xed, 0x8d, 0x88, 0x49, ++ 0x85, 0xb8, 0xde, 0x37, 0x22, 0x62, 0x74, 0x3c, 0x0d, 0x32, 0x52, 0x3a, ++ 0xfe, 0xf9, 0xd4, 0xc1, 0xe4, 0x56, 0x49, 0xaf, 0xbe, 0xf1, 0x66, 0xd3, ++ 0x78, 0x81, 0xf0, 0x95, 0xf0, 0x0c, 0x84, 0xa3, 0x84, 0xef, 0xbf, 0x00, ++ 0x4f, 0xfd, 0xa4, 0xdc, 0x81, 0xf0, 0xbc, 0x80, 0x67, 0x30, 0xea, 0x4f, ++ 0x4d, 0xef, 0x86, 0xc5, 0x26, 0xa3, 0x9d, 0x51, 0xc4, 0xd3, 0x85, 0x70, ++ 0x3e, 0x58, 0xf7, 0xfc, 0xf8, 0x18, 0x5c, 0x47, 0xad, 0x89, 0xc3, 0x65, ++ 0x5a, 0xe3, 0x54, 0x4a, 0x0b, 0x1a, 0x27, 0x33, 0x7d, 0x36, 0xd9, 0x99, ++ 0x5c, 0x08, 0xdf, 0xcf, 0x71, 0x09, 0xa8, 0x70, 0x0e, 0xd0, 0xb3, 0x31, ++ 0xfd, 0x4c, 0xca, 0xff, 0x4c, 0xd0, 0x56, 0x7a, 0x8c, 0x33, 0x1a, 0xe7, ++ 0x71, 0x3e, 0xcb, 0x9b, 0x06, 0x12, 0x19, 0xfb, 0x74, 0x5b, 0x73, 0x18, ++ 0xfa, 0x67, 0x5e, 0x78, 0x46, 0xb5, 0xe3, 0xbd, 0xa6, 0x56, 0xb5, 0x6d, ++ 0xb1, 0xa3, 0x9e, 0xfc, 0x0d, 0x95, 0xc7, 0x05, 0x7d, 0x7b, 0x3c, 0x11, ++ 0xed, 0x9b, 0x6c, 0xc7, 0xe0, 0xfe, 0xd2, 0xb5, 0x26, 0x09, 0x3f, 0x17, ++ 0xc1, 0xb5, 0xed, 0x6a, 0x07, 0xed, 0x37, 0x86, 0xd6, 0xd9, 0x68, 0x9f, ++ 0x5c, 0x33, 0x32, 0x88, 0xfb, 0x19, 0x93, 0x79, 0x21, 0x6b, 0x68, 0x39, ++ 0x67, 0x62, 0x30, 0xe7, 0x33, 0x23, 0x83, 0x38, 0x7f, 0x94, 0xf8, 0x82, ++ 0x76, 0xfc, 0xdc, 0x85, 0x7e, 0x26, 0x02, 0x5f, 0x8b, 0xbf, 0x2f, 0x98, ++ 0xee, 0x35, 0x79, 0xa3, 0x1c, 0xe3, 0x71, 0x3d, 0xac, 0x90, 0x69, 0xee, ++ 0x05, 0x52, 0x7f, 0xd1, 0x17, 0xa5, 0xd2, 0xf9, 0x50, 0xc0, 0xd2, 0x1e, ++ 0xc2, 0xfb, 0x7b, 0xe1, 0x09, 0x03, 0xdd, 0xdf, 0xfb, 0x0a, 0x19, 0x2f, ++ 0x8f, 0xe5, 0xf6, 0xca, 0xbe, 0x13, 0x97, 0x55, 0xdc, 0xef, 0x45, 0xa1, ++ 0x0a, 0x1b, 0x96, 0xe4, 0x8b, 0x9b, 0x09, 0x8a, 0xd5, 0x31, 0x9b, 0x9f, ++ 0x3c, 0x6d, 0xb6, 0x05, 0x33, 0x9b, 0x1f, 0xdd, 0x86, 0xa4, 0x47, 0x6a, ++ 0xf2, 0xa1, 0xf6, 0x11, 0x9a, 0xfa, 0xe1, 0x79, 0xc9, 0x9a, 0xf2, 0x08, ++ 0xc7, 0x55, 0x9a, 0xf2, 0x61, 0x73, 0xb2, 0x34, 0xf9, 0xe1, 0xc5, 0x53, ++ 0x34, 0xf5, 0x63, 0x16, 0xcf, 0xd4, 0xe4, 0xe3, 0x9c, 0xd7, 0x6a, 0xea, ++ 0xc7, 0x57, 0xcd, 0xd7, 0xe4, 0x25, 0x3f, 0x8a, 0xe7, 0x9f, 0x58, 0x42, ++ 0xc3, 0x52, 0x4d, 0xfb, 0x51, 0x8d, 0xcb, 0x34, 0xf5, 0x93, 0x5c, 0xd5, ++ 0x9a, 0x72, 0x35, 0x38, 0xec, 0x49, 0x8a, 0x3b, 0x75, 0x39, 0x3a, 0xd3, ++ 0xa3, 0x91, 0x5f, 0xf1, 0xbf, 0x94, 0xcd, 0x6b, 0x34, 0xf5, 0x1e, 0x0d, ++ 0xe3, 0x71, 0x20, 0x73, 0x2c, 0x95, 0x73, 0x71, 0x1f, 0x8e, 0x6e, 0xbd, ++ 0x5d, 0x3b, 0x2f, 0xf5, 0x4d, 0x85, 0xe2, 0x3a, 0x6d, 0x9c, 0x0f, 0xba, ++ 0xe0, 0x7f, 0x88, 0xdf, 0xa2, 0x58, 0x2d, 0x5f, 0x9c, 0x65, 0xd5, 0xea, ++ 0x1b, 0xe2, 0x1b, 0xf4, 0x9a, 0x7c, 0xf5, 0x24, 0xe1, 0x8f, 0x34, 0x81, ++ 0x4d, 0x20, 0x3e, 0xf8, 0x7d, 0x78, 0x76, 0x5e, 0xa5, 0xc1, 0x73, 0x20, ++ 0x3c, 0x00, 0xef, 0x76, 0x2f, 0xd6, 0x87, 0x73, 0xd5, 0x05, 0xf9, 0xa2, ++ 0xdf, 0x97, 0xeb, 0xf1, 0xdc, 0x47, 0xbb, 0x82, 0xff, 0xfc, 0xd1, 0xae, ++ 0xe0, 0xbf, 0x5e, 0xb4, 0x2b, 0xf8, 0xe7, 0xd1, 0xae, 0xe0, 0x5f, 0x1f, ++ 0xed, 0x0a, 0xfe, 0xe5, 0x68, 0x57, 0xf0, 0x2f, 0xcf, 0x3e, 0xa1, 0xc5, ++ 0x73, 0x6e, 0xa7, 0x16, 0xcf, 0x93, 0x3e, 0xd0, 0xe2, 0x59, 0xd2, 0xdf, ++ 0x50, 0xf8, 0x98, 0xdc, 0xa5, 0xa5, 0x83, 0x40, 0x7c, 0x4c, 0xfd, 0x2c, ++ 0x80, 0x2e, 0x04, 0x1e, 0x16, 0xc3, 0xff, 0x06, 0xc3, 0x03, 0x5d, 0x11, ++ 0x80, 0xfe, 0x67, 0x35, 0x30, 0xd2, 0x9b, 0x7d, 0x1f, 0x5e, 0x1e, 0x9b, ++ 0x24, 0xce, 0x27, 0x81, 0x17, 0xc0, 0x03, 0xc5, 0xf5, 0xf5, 0x8d, 0x0c, ++ 0x25, 0x3c, 0x3c, 0x26, 0xe6, 0x5f, 0xe0, 0x1d, 0x47, 0x71, 0xb1, 0x45, ++ 0xa8, 0x37, 0x4b, 0xf2, 0xad, 0xe7, 0x31, 0x71, 0xee, 0xfe, 0x76, 0x98, ++ 0x73, 0xf7, 0x24, 0xd8, 0xdf, 0xbf, 0xb3, 0x65, 0xc5, 0x22, 0x3f, 0x9a, ++ 0xce, 0xb8, 0x5d, 0x73, 0x76, 0xad, 0xce, 0xee, 0x85, 0xee, 0x9f, 0x0a, ++ 0xc0, 0xff, 0x84, 0xb1, 0xce, 0x7d, 0x58, 0x7f, 0xf1, 0xb0, 0xcb, 0x89, ++ 0x46, 0xa4, 0x87, 0x5e, 0xe7, 0x18, 0xbc, 0x4f, 0x7e, 0x28, 0xf4, 0x24, ++ 0x81, 0x7e, 0x9c, 0x2e, 0x10, 0x07, 0x28, 0x0e, 0xe1, 0x76, 0x95, 0xe2, ++ 0x6f, 0x4e, 0xea, 0x5a, 0x15, 0xe4, 0xcb, 0xde, 0x04, 0xe7, 0x21, 0xe4, ++ 0x1b, 0xb7, 0x66, 0x34, 0x10, 0x9d, 0xc6, 0xb2, 0xe2, 0xfd, 0x95, 0x30, ++ 0xbf, 0xd2, 0xff, 0x0c, 0x22, 0x3b, 0x4e, 0xe9, 0x28, 0x1e, 0xaf, 0xcb, ++ 0x32, 0xba, 0x28, 0xce, 0x41, 0xf2, 0xbb, 0xd2, 0x78, 0xee, 0x47, 0xf4, ++ 0xf2, 0x24, 0x61, 0x17, 0xb6, 0x73, 0x7f, 0xa2, 0xa3, 0x93, 0xb8, 0x3c, ++ 0x1b, 0x6a, 0xb7, 0x92, 0xdf, 0x71, 0x59, 0x06, 0x8f, 0xe3, 0x80, 0x6b, ++ 0x57, 0x62, 0xe9, 0x78, 0x84, 0xcf, 0x9b, 0xe6, 0x31, 0x08, 0x9f, 0x36, ++ 0x6e, 0x37, 0xe9, 0xc2, 0x78, 0xe1, 0x28, 0x5f, 0xbc, 0x30, 0xca, 0x9b, ++ 0x28, 0xdf, 0x25, 0x08, 0xf9, 0xaa, 0xf9, 0xcf, 0x26, 0x13, 0xae, 0x63, ++ 0x4c, 0x3b, 0xd3, 0x9c, 0x93, 0x63, 0xdd, 0x26, 0x8d, 0xdf, 0xeb, 0xb8, ++ 0xdd, 0x56, 0x4d, 0x7e, 0xbc, 0x27, 0x56, 0x53, 0xff, 0xea, 0xc3, 0x36, ++ 0x4d, 0x79, 0xa6, 0x37, 0x5d, 0x53, 0x9e, 0x7d, 0xc2, 0xae, 0xc9, 0xe7, ++ 0x76, 0xe6, 0x69, 0xea, 0x4f, 0xfa, 0xc0, 0xa1, 0xc9, 0x4f, 0xee, 0x9a, ++ 0xa3, 0xa9, 0x3f, 0xf5, 0xb3, 0x62, 0x4d, 0x3e, 0x9e, 0xf5, 0x3e, 0x8c, ++ 0xf0, 0x1d, 0xa5, 0xf0, 0xfb, 0xfe, 0x37, 0x93, 0xb8, 0xff, 0x14, 0xec, ++ 0x55, 0xb2, 0xe3, 0x95, 0x6e, 0x8a, 0xe0, 0x71, 0xa0, 0x42, 0x0f, 0x20, ++ 0xe5, 0x69, 0xe9, 0x0f, 0xed, 0x14, 0xf4, 0x1d, 0x28, 0xa7, 0x8f, 0x32, ++ 0x72, 0x39, 0xb5, 0x39, 0x8e, 0xf1, 0x7b, 0x98, 0x49, 0xdc, 0xb7, 0x98, ++ 0x56, 0x5e, 0x77, 0x0a, 0x7f, 0x66, 0x29, 0xa7, 0x32, 0x97, 0xd6, 0x9f, ++ 0x59, 0xfa, 0x31, 0xf7, 0xcb, 0xf5, 0x42, 0x6e, 0x97, 0xf2, 0xb1, 0x9f, ++ 0x1f, 0xb3, 0xc3, 0xdf, 0x8f, 0xb9, 0x54, 0xc4, 0x6f, 0x07, 0x9e, 0x7f, ++ 0x86, 0x3c, 0xae, 0x1f, 0x09, 0x9c, 0xff, 0x28, 0x23, 0x5f, 0x6f, 0xf3, ++ 0xcf, 0x8d, 0x14, 0x37, 0x22, 0xe7, 0x15, 0x38, 0x1f, 0x67, 0x16, 0xa7, ++ 0xdb, 0x9d, 0xa6, 0xc1, 0xe3, 0x77, 0x86, 0xe5, 0x71, 0x3d, 0xc1, 0xf8, ++ 0xcc, 0xe2, 0x90, 0x3c, 0x48, 0x1f, 0x37, 0xd8, 0xdd, 0xa4, 0x47, 0x19, ++ 0x30, 0x9e, 0xbd, 0xcb, 0x85, 0xf7, 0xca, 0x5f, 0x1a, 0xed, 0x77, 0xda, ++ 0xbe, 0x7f, 0xbc, 0xd2, 0xab, 0xf9, 0x7a, 0x4a, 0x74, 0xba, 0x5b, 0xe7, ++ 0x65, 0x90, 0xbf, 0xd8, 0xe2, 0x67, 0xfd, 0xc6, 0x4f, 0x11, 0xe3, 0x06, ++ 0x4d, 0x51, 0x06, 0x5d, 0x5f, 0x69, 0x38, 0xf7, 0xe7, 0x62, 0xe1, 0x46, ++ 0x1b, 0xd2, 0xef, 0xd0, 0xe3, 0x71, 0x78, 0xc6, 0x1a, 0x59, 0x0b, 0xc5, ++ 0x19, 0x09, 0xbf, 0xff, 0x5b, 0xb6, 0x78, 0xee, 0x1d, 0x03, 0x45, 0x25, ++ 0xc6, 0x56, 0x03, 0x29, 0x2f, 0x98, 0xdb, 0x80, 0xf4, 0x30, 0x77, 0x26, ++ 0xc8, 0x53, 0x99, 0x8c, 0x1d, 0xda, 0xff, 0xec, 0x23, 0x16, 0x90, 0x67, ++ 0x1e, 0x6f, 0xd4, 0x93, 0x9e, 0xe7, 0xaa, 0xc3, 0x31, 0x25, 0xae, 0x54, ++ 0x5f, 0x1c, 0xc7, 0x28, 0xb8, 0x6f, 0x20, 0x7d, 0xa0, 0xcc, 0x82, 0xf7, ++ 0x94, 0x47, 0x27, 0x73, 0x7f, 0xe5, 0xeb, 0xf2, 0xf8, 0xfa, 0x8a, 0xd4, ++ 0x6f, 0xfb, 0xfd, 0xef, 0xc9, 0x7e, 0xc1, 0x98, 0x38, 0x27, 0x18, 0xf9, ++ 0xc3, 0x0c, 0x42, 0x6f, 0x44, 0x87, 0x72, 0x1d, 0x3f, 0x96, 0x3f, 0xbe, ++ 0xa4, 0xdb, 0x40, 0x38, 0xc9, 0xfb, 0x25, 0x13, 0xfe, 0x8e, 0xa9, 0x62, ++ 0x5e, 0x12, 0x7e, 0x72, 0x3f, 0x48, 0xf8, 0xc9, 0x78, 0x08, 0xdb, 0x6a, ++ 0x43, 0xf1, 0x93, 0x16, 0x8a, 0xab, 0x98, 0x83, 0x7e, 0x64, 0x12, 0x7f, ++ 0xbf, 0x9d, 0xcc, 0xf9, 0xd1, 0x2f, 0x05, 0x3c, 0xb0, 0x1e, 0xf2, 0xa3, ++ 0xa1, 0xea, 0x15, 0xa9, 0x19, 0xe1, 0xa8, 0x0f, 0xef, 0x63, 0xb6, 0x70, ++ 0xeb, 0x77, 0xe8, 0x7b, 0x7f, 0xc4, 0x38, 0x05, 0x82, 0xff, 0x50, 0xf1, ++ 0x55, 0x43, 0xf1, 0x87, 0x01, 0x7c, 0x61, 0x88, 0x78, 0xab, 0xa1, 0xe8, ++ 0x93, 0xfe, 0xfe, 0x89, 0xb8, 0x2b, 0x3f, 0xfe, 0xc0, 0xfd, 0x7a, 0x04, ++ 0x3e, 0xdc, 0xa9, 0x3a, 0xb2, 0xa3, 0x6f, 0x0a, 0xd5, 0xee, 0xe3, 0xa7, ++ 0x04, 0x7f, 0x98, 0x27, 0xf6, 0x13, 0x9c, 0xe3, 0x96, 0x4c, 0x2d, 0x9f, ++ 0x60, 0xa8, 0xbf, 0x6f, 0xde, 0xa0, 0x0a, 0x3e, 0xc1, 0xcf, 0x6f, 0x94, ++ 0x6b, 0xf0, 0xfb, 0xf2, 0x0d, 0x06, 0x3a, 0x4f, 0x19, 0x2b, 0x7e, 0x10, ++ 0xe3, 0x88, 0x3e, 0x69, 0x33, 0x90, 0x7f, 0x6b, 0x81, 0xc3, 0x36, 0xdb, ++ 0xce, 0xed, 0xf3, 0x24, 0xdf, 0x90, 0xdd, 0x0b, 0xa6, 0x56, 0xe6, 0xd2, ++ 0x9e, 0xdb, 0x20, 0x47, 0x3c, 0x89, 0xf7, 0x89, 0xe9, 0xcc, 0xbe, 0x11, ++ 0xed, 0x19, 0xe5, 0x9b, 0xb5, 0xe5, 0x2b, 0x2c, 0xb3, 0x3f, 0x47, 0xb9, ++ 0x61, 0x79, 0xc0, 0xbd, 0x74, 0x85, 0xb8, 0xaf, 0xae, 0x08, 0xb8, 0x97, ++ 0x6e, 0xcb, 0x13, 0xe7, 0xb1, 0x9d, 0xd9, 0x49, 0x1e, 0x13, 0x76, 0xfe, ++ 0x2a, 0x51, 0xa7, 0x9f, 0x8e, 0xdc, 0x29, 0xe1, 0x42, 0xef, 0x42, 0xfb, ++ 0x13, 0x52, 0xf2, 0x0b, 0x93, 0x70, 0xb1, 0xa1, 0xbd, 0x26, 0xdb, 0x97, ++ 0x07, 0xf8, 0x05, 0xa7, 0xe3, 0x39, 0xdd, 0xa2, 0x1f, 0xd4, 0x5f, 0xaf, ++ 0x1f, 0x7e, 0x43, 0xf8, 0x23, 0x9c, 0x47, 0x7f, 0x04, 0x1b, 0xee, 0xf7, ++ 0x3e, 0x8a, 0xb7, 0xea, 0x3b, 0x60, 0xe6, 0x76, 0x4a, 0x69, 0x0f, 0x12, ++ 0xf5, 0xcf, 0xbb, 0x2e, 0x53, 0x39, 0xd6, 0xc7, 0xde, 0x2e, 0x64, 0x76, ++ 0x4e, 0x40, 0x79, 0xa7, 0xdf, 0x7e, 0x14, 0x60, 0x87, 0xea, 0xb3, 0xe8, ++ 0xc2, 0xf2, 0xb0, 0xbf, 0xbd, 0x06, 0xea, 0x4f, 0xfa, 0x5b, 0x54, 0xff, ++ 0xcd, 0x3d, 0xc1, 0xea, 0x67, 0x4f, 0x76, 0x76, 0xa9, 0x1a, 0xff, 0x96, ++ 0xc0, 0xd4, 0xb9, 0xfe, 0x20, 0xf9, 0x5f, 0x6c, 0x8a, 0x70, 0xbe, 0x8a, ++ 0x7c, 0xfc, 0x9c, 0xde, 0x6e, 0x42, 0xfc, 0xdd, 0x65, 0x39, 0x16, 0x8d, ++ 0x71, 0xf2, 0x73, 0x85, 0xde, 0x26, 0x70, 0xbe, 0xfd, 0xf2, 0x6d, 0xbe, ++ 0xc2, 0xed, 0xb0, 0x2e, 0x1e, 0x37, 0xdb, 0x37, 0x47, 0x21, 0x3f, 0x00, ++ 0xe0, 0x83, 0x0c, 0xf7, 0x8d, 0xf4, 0x1b, 0x98, 0xc7, 0xbc, 0x51, 0x98, ++ 0x4a, 0x7b, 0x8c, 0x73, 0xf3, 0x64, 0x82, 0xb3, 0xb4, 0xc7, 0x94, 0x79, ++ 0x27, 0xd3, 0x3c, 0x17, 0x36, 0xaf, 0x30, 0x04, 0x43, 0x95, 0xae, 0x87, ++ 0xd7, 0x15, 0x05, 0xdb, 0x7c, 0x76, 0x9a, 0xae, 0x04, 0xee, 0xf7, 0x33, ++ 0x94, 0xbd, 0x66, 0xc1, 0x95, 0x4c, 0xea, 0xef, 0xc6, 0x2b, 0x53, 0xa9, ++ 0x9f, 0x33, 0x79, 0x49, 0x5c, 0xee, 0x6a, 0xb9, 0x77, 0x35, 0xd2, 0xd1, ++ 0x55, 0xbb, 0x99, 0x01, 0xd7, 0xd9, 0x15, 0xe0, 0xf7, 0x2e, 0xd3, 0x1b, ++ 0x27, 0xf3, 0xfd, 0xb0, 0x1a, 0x63, 0x31, 0x72, 0xfd, 0xfc, 0x89, 0xd6, ++ 0x2b, 0x44, 0xe7, 0x6b, 0x14, 0x26, 0xfd, 0x8b, 0x88, 0x4f, 0xcb, 0xfc, ++ 0xe5, 0x56, 0x91, 0x2f, 0xe2, 0xf9, 0xdb, 0x36, 0xf0, 0x7c, 0x97, 0x81, ++ 0xbf, 0x33, 0xb3, 0x4b, 0xe8, 0x1b, 0x70, 0x9d, 0x98, 0xe2, 0x7a, 0xf0, ++ 0x5e, 0xbc, 0x57, 0xe8, 0x23, 0x70, 0x1d, 0x98, 0xe2, 0x3a, 0xf0, 0x3b, ++ 0xf2, 0x25, 0xcc, 0x23, 0x5f, 0xc2, 0x3c, 0xf2, 0x25, 0xcc, 0x23, 0x5f, ++ 0xc2, 0x14, 0xf9, 0x12, 0x7e, 0x5f, 0xc6, 0x8a, 0x13, 0x33, 0x55, 0x6e, ++ 0x57, 0x2a, 0xf4, 0xdb, 0x37, 0x68, 0x57, 0x2a, 0xf4, 0x93, 0x7b, 0xd0, ++ 0xae, 0xe4, 0x9f, 0x47, 0xbb, 0x92, 0x7f, 0x7d, 0xb4, 0x2b, 0xf9, 0x97, ++ 0xa3, 0x5d, 0xc9, 0xbf, 0x1c, 0xed, 0x4a, 0xfe, 0x79, 0xb4, 0x2b, 0xf9, ++ 0xd7, 0x47, 0xbb, 0x92, 0x7f, 0x9e, 0xe5, 0x5d, 0xe3, 0xcb, 0x23, 0x1f, ++ 0x73, 0xcc, 0xd3, 0xe4, 0x17, 0x80, 0x9c, 0x5f, 0xe8, 0xb7, 0x6f, 0xd1, ++ 0xae, 0xe4, 0xdf, 0x3f, 0xda, 0x95, 0x34, 0xfd, 0x39, 0x57, 0x6b, 0xda, ++ 0xdf, 0xcc, 0x1a, 0x35, 0xed, 0xd1, 0xae, 0xe4, 0x5f, 0xff, 0xd6, 0x46, ++ 0x45, 0x63, 0x77, 0xba, 0x55, 0xbc, 0x07, 0x50, 0xde, 0x3e, 0x8c, 0xe8, ++ 0x63, 0xef, 0x84, 0xe2, 0xa4, 0xc9, 0x80, 0xdf, 0x8f, 0x43, 0xfe, 0xfe, ++ 0x33, 0x03, 0xde, 0x37, 0xd4, 0x8e, 0x95, 0x48, 0xb7, 0x6b, 0xea, 0x82, ++ 0xed, 0x1c, 0xcf, 0xad, 0x73, 0x38, 0xde, 0x75, 0x8c, 0xe3, 0xb9, 0x77, ++ 0x09, 0xe1, 0x79, 0x9d, 0x91, 0xe7, 0x8b, 0xb8, 0xff, 0xf1, 0x60, 0xf6, ++ 0x9b, 0x42, 0x03, 0xb7, 0xdf, 0x60, 0x8a, 0xf6, 0x1b, 0x4c, 0xd1, 0x7e, ++ 0x83, 0x29, 0xda, 0x6f, 0x0a, 0x47, 0x73, 0xfb, 0x0d, 0xa6, 0x68, 0xbf, ++ 0xc1, 0xef, 0x68, 0xbf, 0xc1, 0x14, 0xed, 0x37, 0x98, 0xa2, 0xfd, 0x06, ++ 0x53, 0xb4, 0xdf, 0x60, 0x8a, 0xf6, 0x1b, 0x4c, 0xd1, 0x7e, 0x83, 0xed, ++ 0xd0, 0x7e, 0x83, 0x29, 0xda, 0x6f, 0xf0, 0x3b, 0xda, 0x6f, 0x30, 0x45, ++ 0xfb, 0x0d, 0x7e, 0x3f, 0x89, 0x76, 0x24, 0xbf, 0x77, 0x33, 0x50, 0x4e, ++ 0x4f, 0xd5, 0xdc, 0x1f, 0x81, 0x0e, 0x35, 0xf7, 0x47, 0xab, 0x26, 0x8f, ++ 0x72, 0xba, 0x7f, 0x7d, 0x94, 0xd3, 0xfd, 0xcb, 0x51, 0x4e, 0xf7, 0x2f, ++ 0x47, 0x39, 0xdd, 0x3f, 0x8f, 0x72, 0xba, 0x7f, 0x7d, 0x94, 0xd3, 0xfd, ++ 0xf3, 0xcb, 0xf3, 0x6c, 0xb4, 0xbf, 0x50, 0x5e, 0xf7, 0x6f, 0x87, 0xf2, ++ 0xba, 0x7f, 0x7e, 0x7c, 0xab, 0xeb, 0x55, 0xd4, 0x1d, 0x5d, 0xbf, 0xed, ++ 0xe2, 0x2b, 0x98, 0x76, 0x85, 0x2a, 0x8f, 0x2b, 0xc0, 0x0a, 0x96, 0x4d, ++ 0xde, 0x57, 0x82, 0x76, 0xb6, 0x2e, 0xb3, 0x92, 0x18, 0x01, 0x9c, 0xd2, ++ 0xb0, 0xfe, 0xd9, 0x92, 0x42, 0xd8, 0xb3, 0x4e, 0xe1, 0xc7, 0x37, 0x81, ++ 0xf5, 0xea, 0x10, 0xdf, 0x64, 0x67, 0x07, 0xbc, 0x39, 0xbd, 0x8c, 0xfc, ++ 0x8e, 0xc7, 0x7f, 0x13, 0x47, 0xe5, 0xd2, 0xae, 0x4b, 0x7f, 0x80, 0xf7, ++ 0xcc, 0x03, 0x8c, 0xe4, 0xfe, 0x43, 0x22, 0x5e, 0x53, 0xb6, 0xb7, 0x33, ++ 0xab, 0x8a, 0xa9, 0xac, 0xef, 0xcb, 0x0f, 0x5e, 0x2f, 0x70, 0x7c, 0x59, ++ 0x8f, 0xf8, 0xa5, 0xdf, 0x3c, 0xe0, 0x62, 0x98, 0x89, 0x7e, 0x26, 0x99, ++ 0xeb, 0x2c, 0x59, 0xe8, 0x2f, 0xbf, 0x4b, 0xa7, 0x70, 0x7f, 0xd3, 0x3b, ++ 0xb9, 0xbf, 0x6f, 0x20, 0x5d, 0x3d, 0x28, 0xe4, 0xa0, 0x5d, 0xba, 0xfd, ++ 0xc7, 0x82, 0xd1, 0x7f, 0xa8, 0x4c, 0xb1, 0x63, 0x1c, 0x43, 0x9a, 0x9e, ++ 0x9d, 0x30, 0x64, 0x21, 0x9c, 0x1a, 0xb2, 0x50, 0x3e, 0xb8, 0x63, 0x72, ++ 0x84, 0xf0, 0x07, 0x6e, 0x98, 0x82, 0xfe, 0x47, 0x72, 0xde, 0x52, 0x0f, ++ 0x08, 0x7c, 0x82, 0xe2, 0xd7, 0xf2, 0x7b, 0x99, 0xb1, 0x02, 0xc6, 0x99, ++ 0xf6, 0x25, 0x33, 0x2e, 0x47, 0xfe, 0x6e, 0xe4, 0x72, 0x01, 0xb6, 0xc3, ++ 0xfb, 0xe2, 0x38, 0x97, 0xe2, 0x78, 0xd2, 0x8f, 0xbe, 0x37, 0x4f, 0xe6, ++ 0xe7, 0x9b, 0xd3, 0xb5, 0x7a, 0x4a, 0x05, 0x7c, 0x1f, 0xb7, 0xb7, 0x61, ++ 0x0a, 0xc6, 0xc5, 0xcd, 0x0d, 0xe6, 0xed, 0x7e, 0xf3, 0x44, 0x18, 0xc1, ++ 0xf1, 0x86, 0x16, 0xe5, 0x49, 0x8c, 0x3f, 0xcc, 0xdf, 0xcb, 0x1c, 0x18, ++ 0xef, 0xba, 0x55, 0xf0, 0xd3, 0x71, 0x7b, 0xad, 0xc6, 0x0a, 0x1a, 0xd7, ++ 0x4a, 0xf1, 0x74, 0xb2, 0xdf, 0xb2, 0x6d, 0x89, 0x14, 0xff, 0x57, 0xc6, ++ 0xba, 0x0a, 0x31, 0xbe, 0x82, 0xe5, 0x28, 0x0c, 0xed, 0xa3, 0x12, 0x6e, ++ 0xb0, 0xbe, 0x57, 0x70, 0x7d, 0x69, 0xb0, 0x55, 0x0c, 0x24, 0x7f, 0xf2, ++ 0xb8, 0x9c, 0x60, 0x11, 0x97, 0x23, 0xe3, 0x71, 0x82, 0x22, 0x8a, 0x17, ++ 0xe6, 0xe5, 0xfa, 0xe2, 0x72, 0xa6, 0xe5, 0x44, 0x14, 0xa1, 0x5f, 0x1c, ++ 0xeb, 0x60, 0x76, 0x0c, 0x03, 0xbe, 0x3e, 0xa7, 0x6c, 0xc3, 0x70, 0xe8, ++ 0xdf, 0xe9, 0x76, 0xd8, 0xd1, 0xaf, 0x68, 0xda, 0x97, 0x0d, 0xaf, 0x52, ++ 0x7e, 0x47, 0x31, 0xe5, 0x89, 0x0c, 0x26, 0xd2, 0x38, 0x74, 0xae, 0x8d, ++ 0x71, 0x29, 0xf4, 0xbe, 0xc6, 0x0d, 0xae, 0xed, 0xba, 0x28, 0x1b, 0xc6, ++ 0xeb, 0xae, 0x37, 0x44, 0x63, 0xfd, 0xbd, 0xcc, 0x8e, 0xe2, 0x0e, 0x1c, ++ 0x35, 0x14, 0x77, 0x2a, 0xe7, 0x97, 0xc1, 0x3a, 0x75, 0x66, 0x05, 0xf1, ++ 0xce, 0x8e, 0x0f, 0xf3, 0xa3, 0x23, 0xe0, 0x00, 0x37, 0x22, 0xde, 0x33, ++ 0xed, 0x06, 0x7a, 0x7f, 0x63, 0x9e, 0xde, 0x6a, 0x40, 0xbe, 0x11, 0x78, ++ 0x8e, 0x0f, 0xf4, 0x5b, 0x0c, 0x90, 0x13, 0x02, 0xfc, 0x4b, 0x9a, 0xd7, ++ 0x7d, 0x90, 0xa8, 0x26, 0xa3, 0x7f, 0x89, 0xce, 0xee, 0x45, 0xbe, 0x75, ++ 0x30, 0x84, 0xe4, 0x05, 0x29, 0xef, 0x94, 0x09, 0x7f, 0xb3, 0xcb, 0x2d, ++ 0xaf, 0x0e, 0xbf, 0x09, 0xca, 0xcb, 0xf6, 0x73, 0xf9, 0xc0, 0xd9, 0xae, ++ 0x10, 0xff, 0x93, 0xfe, 0x26, 0x75, 0x29, 0xee, 0x44, 0x1d, 0xca, 0x0b, ++ 0x23, 0xb6, 0x4f, 0x88, 0x54, 0xf9, 0xf9, 0x8f, 0x7c, 0xf1, 0x9c, 0xeb, ++ 0xb9, 0x45, 0xb8, 0x45, 0xcb, 0x36, 0xbc, 0x4a, 0x71, 0x11, 0x65, 0x1b, ++ 0x72, 0xc3, 0x79, 0x5c, 0x14, 0xb7, 0x43, 0x54, 0x08, 0x38, 0x55, 0x08, ++ 0xbf, 0x22, 0x96, 0x61, 0x8d, 0x46, 0x39, 0xf3, 0x14, 0xf0, 0x1d, 0xc7, ++ 0x18, 0xf2, 0x4b, 0x0c, 0xa7, 0xb8, 0xc2, 0x56, 0x2e, 0xcf, 0x49, 0xbd, ++ 0x8e, 0x94, 0x07, 0xe5, 0xfb, 0x31, 0x65, 0x6f, 0x65, 0xbf, 0x86, 0x78, ++ 0x2f, 0x7b, 0x4c, 0xbc, 0xcb, 0xb2, 0xb9, 0x8c, 0xe2, 0xaf, 0x02, 0xfd, ++ 0x7c, 0x6a, 0x84, 0xbc, 0xb7, 0xb2, 0xc5, 0x40, 0xfe, 0x43, 0x2b, 0x03, ++ 0xe4, 0xc1, 0x1a, 0xe1, 0x2f, 0x54, 0x13, 0x20, 0x0f, 0x9e, 0x9c, 0x2c, ++ 0xf4, 0x40, 0x52, 0x1e, 0x14, 0xf7, 0x17, 0xe9, 0xcf, 0x5b, 0xf6, 0xd6, ++ 0xf1, 0x85, 0x24, 0xaf, 0x34, 0x18, 0xc8, 0x2e, 0x57, 0xb2, 0x9e, 0xcb, ++ 0x2f, 0x6c, 0x3f, 0x73, 0x63, 0x3c, 0x43, 0xc9, 0xfa, 0x59, 0x3a, 0x7c, ++ 0x37, 0xa4, 0xe4, 0xa0, 0xc3, 0xae, 0x0c, 0x42, 0x27, 0x6f, 0x0b, 0x39, ++ 0x66, 0x6e, 0x97, 0x99, 0xe0, 0x3a, 0xff, 0x4a, 0x3c, 0xa5, 0x8b, 0xae, ++ 0xc4, 0x51, 0x7a, 0xd3, 0x15, 0xee, 0x47, 0x89, 0xb1, 0x2f, 0x48, 0x07, ++ 0x5d, 0x2f, 0x30, 0x92, 0xa3, 0xdf, 0x15, 0x72, 0xcb, 0x42, 0xf4, 0xab, ++ 0xc4, 0x78, 0x44, 0x57, 0x90, 0xf0, 0x9f, 0x64, 0x24, 0x37, 0x65, 0x32, ++ 0x6b, 0x11, 0xf2, 0x8f, 0xab, 0x1c, 0xca, 0x71, 0x14, 0xfb, 0xe6, 0x1a, ++ 0x9c, 0x1b, 0xd0, 0x6f, 0x73, 0xee, 0x76, 0x46, 0xf1, 0x47, 0xd7, 0xa3, ++ 0x7c, 0x03, 0xfd, 0x2f, 0x46, 0x79, 0x07, 0xf5, 0xee, 0x39, 0x49, 0x45, ++ 0x14, 0x87, 0x31, 0x47, 0xa1, 0x78, 0x96, 0xeb, 0x73, 0x56, 0x0b, 0xfa, ++ 0x06, 0x7a, 0x67, 0x48, 0xef, 0x2e, 0x41, 0xbf, 0xc5, 0x94, 0xef, 0x3f, ++ 0x17, 0x04, 0x9d, 0x3b, 0x5d, 0xdd, 0x7a, 0x84, 0xfb, 0xf5, 0x2e, 0xc5, ++ 0x88, 0xef, 0xf0, 0x39, 0xc5, 0x3d, 0x56, 0xd2, 0x71, 0x20, 0xbd, 0x97, ++ 0x86, 0x08, 0xfd, 0x93, 0x85, 0xeb, 0x97, 0xfa, 0xf5, 0x4f, 0x38, 0x59, ++ 0x7a, 0xd4, 0xc6, 0x74, 0x0b, 0xfa, 0xb7, 0x96, 0xa2, 0x6e, 0x70, 0x04, ++ 0xe3, 0x88, 0x07, 0x98, 0x87, 0x66, 0xf0, 0xf2, 0xd8, 0x29, 0xa6, 0x5b, ++ 0x5a, 0xf0, 0x52, 0xf3, 0xdf, 0xd4, 0x4b, 0x94, 0xe8, 0x74, 0x3c, 0xde, ++ 0x09, 0xe4, 0x2d, 0xe4, 0xab, 0xb7, 0xac, 0xcd, 0x34, 0x2e, 0xf3, 0xe3, ++ 0x2f, 0x9f, 0x4c, 0x9d, 0x39, 0x69, 0x6a, 0xae, 0x0f, 0xef, 0xcb, 0x02, ++ 0xe2, 0xf4, 0xd6, 0xdc, 0x35, 0x3a, 0xe6, 0xbb, 0xe2, 0x45, 0xcb, 0x01, ++ 0xce, 0xb8, 0x4f, 0x4a, 0xc3, 0xbb, 0x7e, 0x06, 0x14, 0xca, 0xf2, 0xa6, ++ 0x30, 0x47, 0x21, 0x88, 0x9e, 0x4b, 0x98, 0x5c, 0x27, 0xf3, 0xa2, 0x5f, ++ 0xe0, 0x52, 0x91, 0x5f, 0x3e, 0x25, 0xf3, 0xaf, 0x9b, 0x33, 0x08, 0x3e, ++ 0x94, 0xcf, 0x79, 0x31, 0xfa, 0x16, 0x17, 0xf1, 0x55, 0xce, 0xb7, 0x6e, ++ 0x46, 0xbe, 0xa5, 0x22, 0xbf, 0x72, 0x66, 0x4d, 0x21, 0x7e, 0xd5, 0x35, ++ 0x1b, 0xf1, 0x11, 0x92, 0xd1, 0x2b, 0xde, 0x21, 0xe0, 0xf1, 0x0e, 0x81, ++ 0x7a, 0x88, 0xe5, 0x53, 0x38, 0x1e, 0x02, 0xf5, 0x11, 0xe5, 0x19, 0x9c, ++ 0x9f, 0x33, 0xbd, 0x2d, 0xf1, 0x66, 0x8a, 0x0b, 0xb6, 0x91, 0x3e, 0x4f, ++ 0xce, 0xff, 0x94, 0x41, 0x1b, 0xa7, 0x29, 0xd3, 0x5b, 0xa6, 0x70, 0xbe, ++ 0xfc, 0x63, 0xc5, 0x37, 0xfc, 0xaf, 0x14, 0xe7, 0x0d, 0xb8, 0xbe, 0x07, ++ 0x75, 0x3c, 0x6e, 0x7e, 0x84, 0xda, 0xca, 0x84, 0x5e, 0x88, 0xf6, 0xbf, ++ 0xe4, 0x1f, 0x4c, 0xbc, 0x23, 0xe1, 0xc3, 0x3f, 0xc8, 0x69, 0x64, 0x47, ++ 0x57, 0xac, 0xfe, 0xf8, 0x77, 0x6e, 0x56, 0x78, 0x9c, 0xfa, 0x10, 0xfa, ++ 0x1b, 0x96, 0xde, 0xfb, 0xf0, 0x4e, 0xd4, 0xdf, 0x35, 0x19, 0x19, 0xc6, ++ 0xb9, 0x3e, 0x91, 0xc6, 0xe9, 0xe8, 0x89, 0xdb, 0x8d, 0x24, 0x87, 0x97, ++ 0x18, 0x3b, 0x5f, 0xc5, 0x77, 0xb2, 0x24, 0x1c, 0x3f, 0x6a, 0xfc, 0x0f, ++ 0x03, 0xe9, 0xff, 0x99, 0x77, 0x34, 0xbe, 0xff, 0xb5, 0xb4, 0xc1, 0x6c, ++ 0x47, 0xfe, 0xfc, 0xc9, 0xd4, 0xe2, 0x8a, 0x29, 0xc3, 0x11, 0x1f, 0x76, ++ 0xc2, 0xc7, 0x24, 0xd8, 0x66, 0xd8, 0xff, 0xc9, 0x84, 0xe2, 0x15, 0xf8, ++ 0xbd, 0x6e, 0xcb, 0xd1, 0xc7, 0x31, 0x6e, 0x7f, 0x55, 0x47, 0x12, 0xc5, ++ 0x91, 0x96, 0x1d, 0xce, 0xdc, 0x88, 0xef, 0x89, 0x7c, 0x32, 0xd5, 0x59, ++ 0x8b, 0xeb, 0x2d, 0xb3, 0x58, 0x8d, 0x78, 0x8e, 0xd7, 0xb7, 0x44, 0xd0, ++ 0xb9, 0x56, 0x1a, 0x23, 0xe2, 0x3a, 0x59, 0x2f, 0xd9, 0xa9, 0x24, 0xfc, ++ 0x5b, 0xa6, 0xf0, 0xf3, 0x74, 0x4a, 0x3e, 0xef, 0xbf, 0x47, 0xdc, 0x47, ++ 0x90, 0x61, 0xce, 0xd3, 0xd4, 0x13, 0x7e, 0xdc, 0x01, 0xfb, 0x44, 0xea, ++ 0x05, 0x03, 0xf5, 0x0b, 0x81, 0xef, 0x38, 0x0c, 0xb5, 0x7f, 0xa4, 0x1e, ++ 0x01, 0xf5, 0x06, 0x46, 0x3f, 0xbd, 0xa2, 0xd4, 0x4b, 0x18, 0xd2, 0x4f, ++ 0x2d, 0xc1, 0x73, 0xb4, 0xc4, 0xa8, 0x8d, 0x3f, 0x94, 0xe9, 0x41, 0xa9, ++ 0x77, 0x13, 0xf7, 0xc1, 0xe5, 0xfd, 0xe7, 0x58, 0xc6, 0xec, 0x18, 0x94, ++ 0x9b, 0xb7, 0x2a, 0x56, 0x3c, 0xc7, 0x2a, 0x2c, 0xb6, 0x9b, 0x26, 0x43, ++ 0xbe, 0xe2, 0x84, 0x01, 0x3d, 0x30, 0xd9, 0xdc, 0x48, 0x1b, 0x7f, 0xbf, ++ 0xe3, 0x2e, 0xfe, 0x7e, 0xc7, 0x32, 0xd8, 0xaf, 0xc8, 0x6f, 0x4a, 0x84, ++ 0x3f, 0x56, 0x45, 0xfb, 0x64, 0xda, 0x6f, 0x15, 0x6e, 0x48, 0xb3, 0x87, ++ 0xde, 0x97, 0x37, 0x6f, 0x3d, 0x9e, 0xf0, 0x02, 0xd2, 0x8f, 0xd7, 0x41, ++ 0x71, 0xf9, 0x15, 0x56, 0x87, 0x31, 0xd2, 0x6f, 0xdf, 0x97, 0xb7, 0x2a, ++ 0x9a, 0xb8, 0x7e, 0x99, 0xdf, 0x39, 0x45, 0xa5, 0x79, 0x97, 0x80, 0x98, ++ 0x8e, 0xf0, 0xbb, 0x65, 0x6d, 0x92, 0x11, 0xdf, 0xd0, 0x29, 0x01, 0xf1, ++ 0x02, 0xfd, 0xfb, 0x0e, 0x4e, 0xb1, 0x69, 0xe2, 0xaa, 0xa1, 0x1e, 0xf9, ++ 0x35, 0xcc, 0x4d, 0x66, 0xaf, 0xf1, 0xf7, 0x93, 0x60, 0xde, 0x49, 0x7c, ++ 0xbc, 0x2c, 0xbf, 0xfe, 0x97, 0xb5, 0x6a, 0xdf, 0x27, 0x80, 0xfa, 0x24, ++ 0x17, 0xfd, 0x76, 0x4a, 0x28, 0xe1, 0xaf, 0xcc, 0x0a, 0xeb, 0x4e, 0xc2, ++ 0xd4, 0x4a, 0xf3, 0x04, 0x38, 0x10, 0x9c, 0x7a, 0xef, 0x85, 0xfe, 0x6c, ++ 0x34, 0x0e, 0xe1, 0xa3, 0xdc, 0xeb, 0x36, 0xe0, 0xbd, 0xbb, 0x04, 0xfd, ++ 0x29, 0x20, 0xbf, 0xd4, 0xea, 0x36, 0xe0, 0x38, 0xcb, 0x5a, 0xf8, 0x7b, ++ 0x21, 0xce, 0x2d, 0x7c, 0x1c, 0xe7, 0xe6, 0x08, 0xe3, 0x78, 0x94, 0x9b, ++ 0xf4, 0x56, 0x63, 0x02, 0xc2, 0x0f, 0x2f, 0xcb, 0x51, 0x34, 0x3f, 0xe2, ++ 0x83, 0x15, 0x00, 0x17, 0x8c, 0xb7, 0x92, 0x71, 0x97, 0x81, 0xf0, 0x29, ++ 0x13, 0xf3, 0xad, 0x68, 0x8d, 0xd0, 0xca, 0x63, 0xad, 0x5b, 0x0d, 0x88, ++ 0x8f, 0x25, 0x43, 0xbc, 0x57, 0xd0, 0x2d, 0xe8, 0x76, 0x59, 0xcb, 0x0c, ++ 0x8a, 0x37, 0xaf, 0xd0, 0x3b, 0x28, 0x9e, 0xc1, 0x29, 0xe0, 0xfb, 0xc9, ++ 0x6a, 0xf3, 0xdd, 0x68, 0x17, 0x58, 0xd2, 0xf6, 0x90, 0x21, 0x09, 0xf2, ++ 0x7f, 0x14, 0xf4, 0xdb, 0x2d, 0xf6, 0xdd, 0xdc, 0x64, 0xef, 0x68, 0x7a, ++ 0x17, 0x68, 0xb5, 0xd9, 0x8e, 0xf3, 0x5c, 0x62, 0x6d, 0xa5, 0xf5, 0xf5, ++ 0xc3, 0xf7, 0x01, 0x80, 0x87, 0x82, 0xef, 0xcf, 0x14, 0x13, 0x7c, 0x81, ++ 0x2e, 0x5c, 0xe8, 0x9f, 0x57, 0xd1, 0xa6, 0xc5, 0xa7, 0x6f, 0x3e, 0x1c, ++ 0xbe, 0x15, 0x6d, 0x65, 0xb4, 0xdf, 0x2a, 0xf5, 0x4e, 0xa3, 0xd5, 0x7f, ++ 0x1e, 0xed, 0x47, 0x47, 0xa3, 0x1f, 0xca, 0x12, 0xd8, 0xdf, 0xf8, 0xde, ++ 0x11, 0xb3, 0x3a, 0x29, 0xbe, 0xe9, 0xec, 0x03, 0x37, 0x25, 0xd2, 0x3a, ++ 0x61, 0x9e, 0xe4, 0x07, 0x65, 0xb7, 0xcd, 0xc6, 0x77, 0x7e, 0x80, 0x4e, ++ 0x88, 0x8e, 0x25, 0xbd, 0xc8, 0xb8, 0x6c, 0x39, 0xde, 0x37, 0x53, 0x78, ++ 0x5c, 0xe6, 0x37, 0xdf, 0xbb, 0x2f, 0x1d, 0x24, 0xd7, 0x34, 0x03, 0x7e, ++ 0x51, 0xdf, 0x3d, 0xd4, 0xbe, 0x34, 0x62, 0x60, 0x17, 0x8c, 0x6b, 0xac, ++ 0xe0, 0xef, 0xaf, 0x05, 0xee, 0x53, 0xb9, 0x3f, 0xfb, 0xed, 0x07, 0x62, ++ 0x9f, 0xca, 0xfd, 0xfb, 0xb8, 0xa1, 0xd8, 0x1b, 0xab, 0xf8, 0xf8, 0x0c, ++ 0x9c, 0xb7, 0x0d, 0xcf, 0x0e, 0x02, 0xa7, 0x49, 0x53, 0xf9, 0x7c, 0x97, ++ 0x0a, 0xbc, 0x02, 0x5c, 0x5f, 0xf1, 0x8f, 0xe3, 0xb2, 0x4d, 0xe5, 0x78, ++ 0x2d, 0x49, 0xd6, 0xee, 0x77, 0xec, 0x0f, 0xfb, 0x0d, 0x93, 0xe5, 0x33, ++ 0xbd, 0xa3, 0x31, 0xee, 0x52, 0xd6, 0x97, 0xe3, 0x96, 0x44, 0xf2, 0x76, ++ 0x48, 0xf7, 0x48, 0x6f, 0x61, 0x62, 0x3c, 0xac, 0xbf, 0x86, 0xea, 0x6b, ++ 0xe3, 0x51, 0xca, 0xfb, 0xf9, 0xc5, 0xde, 0x0d, 0xd1, 0xc8, 0x2f, 0xf6, ++ 0x2b, 0x24, 0xf7, 0xae, 0xb9, 0xf7, 0x78, 0xc2, 0xbf, 0xa3, 0x3c, 0xbb, ++ 0x8f, 0xcb, 0xb3, 0xe7, 0x6a, 0x77, 0xd6, 0xc7, 0xa1, 0xdc, 0xa8, 0x77, ++ 0x27, 0xfa, 0xbf, 0x8b, 0x55, 0xe1, 0xe5, 0xfc, 0x61, 0x39, 0xc8, 0x3f, ++ 0xc8, 0x2f, 0x2a, 0xc5, 0x39, 0xbd, 0x2f, 0xcb, 0x99, 0x30, 0xd5, 0xcf, ++ 0x7f, 0xa2, 0xe2, 0xfe, 0x7d, 0x69, 0x4e, 0xce, 0x5f, 0xbc, 0xc8, 0x5f, ++ 0xfe, 0xb2, 0xef, 0xa5, 0xf7, 0xa6, 0xd8, 0x7c, 0xe7, 0xa7, 0x9c, 0xff, ++ 0xb2, 0xcd, 0x7f, 0x34, 0x94, 0x59, 0xfc, 0xe1, 0xc5, 0xd7, 0x77, 0x77, ++ 0x7a, 0x1f, 0xc5, 0xd9, 0x95, 0x5b, 0x8c, 0x36, 0xf4, 0x5f, 0x2e, 0x6f, ++ 0x29, 0x23, 0x7e, 0xcb, 0x62, 0xe1, 0x5e, 0xa1, 0xf8, 0xf0, 0x1d, 0x48, ++ 0x07, 0x65, 0x2d, 0x0a, 0xbd, 0x2f, 0x56, 0xde, 0x38, 0xd1, 0xad, 0xfe, ++ 0x5f, 0xe4, 0xcb, 0xe5, 0x5b, 0xe6, 0xd1, 0x9b, 0x48, 0x12, 0x4f, 0xf2, ++ 0xbd, 0x13, 0x79, 0x9e, 0xca, 0xf9, 0x3b, 0xc4, 0xfc, 0x97, 0x0a, 0x3a, ++ 0x9e, 0x35, 0x95, 0xef, 0xbf, 0xa5, 0x55, 0x49, 0xc6, 0x4a, 0xda, 0xf7, ++ 0x49, 0xc6, 0x72, 0xa4, 0x7f, 0x51, 0xbe, 0xa4, 0x42, 0xfb, 0xbd, 0x1f, ++ 0x4f, 0xfd, 0x76, 0xec, 0x8c, 0x8d, 0xb8, 0x3f, 0x30, 0x6e, 0x88, 0xee, ++ 0x27, 0x5b, 0x0c, 0x5c, 0xcf, 0xb7, 0x37, 0x94, 0xe4, 0xd5, 0x73, 0x6b, ++ 0x9e, 0xff, 0xc3, 0x22, 0xa8, 0xf7, 0xc5, 0x83, 0xdb, 0x13, 0x51, 0x3e, ++ 0x91, 0xf3, 0x58, 0x21, 0xf4, 0x79, 0xcb, 0x85, 0x5e, 0xae, 0x52, 0xc8, ++ 0xad, 0x80, 0xa7, 0xf9, 0x53, 0xfd, 0xf8, 0xec, 0x8a, 0x27, 0x38, 0x9e, ++ 0xca, 0x9f, 0x79, 0xeb, 0xaf, 0xf8, 0x2e, 0x57, 0x49, 0xb2, 0xe0, 0x67, ++ 0xf7, 0xf2, 0x78, 0xfe, 0x65, 0x9e, 0xfd, 0x84, 0xb7, 0x25, 0x9b, 0xb7, ++ 0x1a, 0x92, 0x10, 0x5f, 0xf8, 0x48, 0xad, 0x5f, 0xfb, 0xf2, 0x06, 0xb8, ++ 0xe8, 0x02, 0x3c, 0x97, 0x6e, 0xde, 0x6e, 0x40, 0x3e, 0xb0, 0x4c, 0xae, ++ 0x37, 0x80, 0xde, 0x4b, 0x84, 0xbf, 0xaf, 0x84, 0x2b, 0x9e, 0x3b, 0x8a, ++ 0x9f, 0xdd, 0x42, 0xd6, 0x47, 0xfe, 0xb7, 0x1f, 0xc6, 0x59, 0xbb, 0xda, ++ 0x1c, 0x86, 0xfa, 0x69, 0x39, 0xce, 0x3d, 0x53, 0xb9, 0xdc, 0x54, 0xde, ++ 0x10, 0x11, 0x89, 0xe3, 0x95, 0x37, 0x94, 0xfd, 0x0a, 0xef, 0x1d, 0x92, ++ 0xdf, 0x07, 0xee, 0xbb, 0xd3, 0x66, 0xbe, 0x1f, 0x96, 0x41, 0x7f, 0xb8, ++ 0x2f, 0x4f, 0xcf, 0xb0, 0x53, 0x5c, 0x33, 0xda, 0xb5, 0x06, 0x3b, 0x57, ++ 0xef, 0x9c, 0xca, 0xcf, 0xd5, 0x47, 0x0d, 0xfc, 0xfd, 0xc6, 0xf8, 0x10, ++ 0xcf, 0x1e, 0x84, 0x43, 0xfc, 0xaa, 0x60, 0x3b, 0xf2, 0x87, 0xd4, 0xd4, ++ 0x2e, 0xb2, 0x1b, 0x23, 0x3d, 0xe3, 0xbc, 0x8d, 0x3a, 0xfe, 0xde, 0x63, ++ 0x6a, 0x6d, 0xd7, 0x25, 0x9c, 0x07, 0x88, 0xd4, 0xe4, 0x9f, 0x82, 0x29, ++ 0xbe, 0x33, 0x85, 0x22, 0x76, 0x34, 0xe4, 0x9f, 0xd4, 0xf1, 0xf8, 0xab, ++ 0x64, 0x95, 0xa7, 0xbb, 0x05, 0x7c, 0xa0, 0xdc, 0x8b, 0xe5, 0x2c, 0xaa, ++ 0x8b, 0xde, 0x9d, 0xeb, 0x7f, 0x37, 0x29, 0x80, 0x5e, 0x8d, 0x6c, 0xc7, ++ 0x66, 0x7c, 0xef, 0xc6, 0x18, 0xc5, 0xec, 0xcd, 0x36, 0x1f, 0x7d, 0xca, ++ 0x7e, 0x24, 0x7d, 0x4a, 0xfa, 0x1d, 0x6a, 0x7d, 0xee, 0x1f, 0xb8, 0xbe, ++ 0xd3, 0x49, 0x42, 0x1f, 0x91, 0x6e, 0x4f, 0xc4, 0x38, 0x95, 0xd2, 0xfb, ++ 0xc6, 0xd8, 0x51, 0x3f, 0xf3, 0x7d, 0xeb, 0x34, 0x8a, 0xf7, 0x07, 0xfb, ++ 0xd7, 0x0b, 0xc4, 0x9a, 0x17, 0x39, 0xc8, 0x7a, 0x53, 0xf9, 0xbd, 0x65, ++ 0xe8, 0xf5, 0xb6, 0x15, 0x45, 0x0f, 0xb2, 0xde, 0xc0, 0x75, 0xca, 0x7d, ++ 0x22, 0x7d, 0xda, 0xfb, 0xed, 0x0b, 0xad, 0xdc, 0xbe, 0x70, 0x5a, 0x81, ++ 0xf3, 0x0b, 0xda, 0x9d, 0x5e, 0x6d, 0x26, 0xff, 0x2f, 0xb9, 0x2e, 0xa9, ++ 0xff, 0xfe, 0xa1, 0x71, 0x08, 0xaf, 0x4c, 0x8d, 0x14, 0x7a, 0x9d, 0xae, ++ 0x50, 0x94, 0x23, 0x4b, 0x82, 0xc5, 0xfe, 0xf7, 0xf2, 0x3c, 0x7e, 0x9f, ++ 0xe7, 0xf7, 0x5d, 0x9e, 0xfb, 0xf2, 0xbd, 0x36, 0xc9, 0x9f, 0xcf, 0x34, ++ 0x88, 0x73, 0x91, 0x75, 0xdd, 0x8b, 0xfb, 0x99, 0x35, 0xa6, 0xd0, 0xfb, ++ 0x24, 0x27, 0x5b, 0x4f, 0x87, 0xe2, 0x7b, 0x29, 0xa7, 0x67, 0xf0, 0xf9, ++ 0xc9, 0x76, 0x6b, 0x0d, 0x3c, 0xce, 0x98, 0x85, 0x1a, 0x6d, 0xf8, 0xfe, ++ 0x21, 0xdc, 0xaf, 0x4e, 0x36, 0xa2, 0xdd, 0xa7, 0x25, 0x86, 0xee, 0x91, ++ 0xb7, 0x34, 0xa6, 0x10, 0x5f, 0xb8, 0xc5, 0x15, 0xc1, 0xf5, 0x0f, 0x42, ++ 0xbe, 0xaf, 0x14, 0x7c, 0x30, 0x64, 0x6d, 0xd9, 0x46, 0x7c, 0xe7, 0x7b, ++ 0x79, 0x7b, 0x92, 0x55, 0x81, 0x71, 0x96, 0x5b, 0xec, 0x67, 0xdb, 0xa9, ++ 0xfd, 0x38, 0x3b, 0xca, 0x83, 0x21, 0x6d, 0xf3, 0x8c, 0xc9, 0x24, 0xf7, ++ 0xf2, 0x7b, 0x80, 0xb4, 0x13, 0xad, 0x55, 0x58, 0x31, 0xc5, 0x8d, 0x21, ++ 0x9f, 0xc4, 0xfd, 0xa5, 0x3b, 0x9a, 0x8a, 0xe7, 0xce, 0x8a, 0x76, 0x7e, ++ 0x0f, 0x98, 0xab, 0x63, 0x9b, 0xd1, 0x4e, 0x38, 0xaa, 0xb9, 0x78, 0x76, ++ 0x1c, 0xf2, 0x89, 0x87, 0x15, 0x8a, 0x33, 0x67, 0xdb, 0xb4, 0xef, 0x58, ++ 0xa5, 0x67, 0x17, 0x7f, 0x4c, 0xf7, 0xbf, 0x80, 0x77, 0xe0, 0xd6, 0x1a, ++ 0x3c, 0x8e, 0x18, 0xe4, 0xe3, 0x20, 0x6f, 0xa0, 0xbe, 0x69, 0xb9, 0xa5, ++ 0x98, 0xe4, 0xf6, 0x52, 0x41, 0x27, 0x27, 0xdb, 0xba, 0xe9, 0x3d, 0x7a, ++ 0x09, 0xd7, 0x01, 0xf1, 0x3f, 0x46, 0x1e, 0x07, 0xdc, 0x1b, 0xaa, 0x23, ++ 0x3d, 0xdc, 0x0f, 0x8d, 0x03, 0xaa, 0x10, 0x76, 0x25, 0x49, 0x37, 0xd2, ++ 0x2e, 0xf5, 0x08, 0xfe, 0x67, 0x32, 0xc2, 0x49, 0xa5, 0x73, 0xad, 0x48, ++ 0x2d, 0xa1, 0xf7, 0x94, 0x36, 0xb6, 0xcd, 0xa2, 0xb4, 0x62, 0x6b, 0xd1, ++ 0x83, 0xae, 0xf1, 0x18, 0x7f, 0x5c, 0x1c, 0x3d, 0x85, 0xe6, 0x6d, 0x20, ++ 0x3d, 0x59, 0x45, 0xdd, 0x2c, 0x1e, 0xaf, 0xfb, 0x64, 0x50, 0x04, 0xde, ++ 0x6f, 0x12, 0x0d, 0xae, 0x44, 0x7f, 0xb9, 0xb4, 0x62, 0xfb, 0x26, 0x8a, ++ 0xff, 0xf9, 0x6c, 0xbb, 0x99, 0xe2, 0x7f, 0x0a, 0xad, 0xf3, 0x0a, 0x23, ++ 0xa2, 0xe8, 0xbd, 0x63, 0x8a, 0xaf, 0x93, 0xf5, 0xc2, 0xf3, 0xf9, 0x79, ++ 0x51, 0x5d, 0x37, 0x4b, 0x13, 0xbf, 0xb3, 0x1c, 0xfa, 0xc4, 0x77, 0x36, ++ 0xbf, 0xf2, 0x84, 0x90, 0x1f, 0x9a, 0x8c, 0xcb, 0xa9, 0x8d, 0x71, 0x06, ++ 0xe7, 0xe7, 0xf2, 0xf8, 0x9c, 0xc9, 0x36, 0x1e, 0x97, 0x13, 0x47, 0xf5, ++ 0x6d, 0x83, 0xea, 0xc5, 0x65, 0x7a, 0xb6, 0x89, 0xc7, 0x79, 0xf8, 0xc5, ++ 0x1b, 0xdd, 0xb0, 0x04, 0xda, 0xd7, 0xd6, 0x3d, 0x17, 0x86, 0xfd, 0xd4, ++ 0x3c, 0xf0, 0xee, 0x44, 0xab, 0x8e, 0xf4, 0x50, 0xd1, 0xf9, 0xc3, 0xfd, ++ 0xe2, 0x8d, 0xda, 0x79, 0xbc, 0x51, 0x8c, 0xb8, 0x2f, 0xcd, 0x8d, 0x2c, ++ 0x5e, 0xb4, 0x04, 0xe1, 0xff, 0x7b, 0x95, 0xe0, 0x3f, 0xd4, 0x78, 0x55, ++ 0x87, 0x15, 0x8d, 0x1d, 0xef, 0x16, 0x77, 0x38, 0xc9, 0xad, 0x4e, 0x2f, ++ 0x33, 0xa2, 0x1d, 0xd9, 0x69, 0x65, 0x24, 0x17, 0x7f, 0xa6, 0xb2, 0x46, ++ 0x94, 0x03, 0xa4, 0xfc, 0x22, 0xbf, 0x5f, 0x95, 0xcf, 0xf9, 0xd5, 0x67, ++ 0xe1, 0xad, 0x89, 0x48, 0x1f, 0x2b, 0x77, 0x3d, 0x94, 0x88, 0xe7, 0xcb, ++ 0xe7, 0xa1, 0x3c, 0x5f, 0xb2, 0xeb, 0xa6, 0xd7, 0x91, 0x5f, 0x39, 0x77, ++ 0x04, 0x71, 0xf9, 0x5c, 0xcf, 0x48, 0x1e, 0x2e, 0x77, 0x71, 0xf9, 0x9a, ++ 0x55, 0x45, 0xca, 0xf7, 0x48, 0xcd, 0xa5, 0x40, 0x47, 0x39, 0xf9, 0x21, ++ 0xfc, 0xdd, 0xa3, 0x76, 0x6d, 0xbc, 0xb9, 0x7c, 0xe7, 0xf6, 0x73, 0x3d, ++ 0x7f, 0x9f, 0x07, 0xe3, 0x8d, 0x90, 0xde, 0x3f, 0xd2, 0x7b, 0x97, 0x23, ++ 0x7e, 0x3f, 0x02, 0xf9, 0x15, 0xef, 0xb1, 0xe1, 0xf9, 0x9c, 0x3e, 0x3f, ++ 0x6a, 0x55, 0x67, 0x93, 0xdf, 0x10, 0x6c, 0x14, 0x94, 0x43, 0x3e, 0x6a, ++ 0x7d, 0x2e, 0x14, 0xe3, 0xa1, 0xa5, 0xbc, 0x56, 0xa4, 0xfe, 0xc5, 0x81, ++ 0xef, 0xff, 0xac, 0x39, 0xc8, 0xe3, 0x82, 0xf1, 0x7d, 0x7a, 0x7a, 0x2b, ++ 0x54, 0xe8, 0x41, 0xea, 0x85, 0x1e, 0x64, 0xcd, 0x0b, 0x86, 0xd9, 0xf1, ++ 0x51, 0x24, 0x7f, 0xd1, 0x97, 0x5a, 0xbd, 0xd7, 0x38, 0x18, 0xfe, 0xaa, ++ 0x85, 0x7c, 0xd5, 0x9f, 0x3f, 0xb0, 0x9f, 0xee, 0x6d, 0xb5, 0x7b, 0xb9, ++ 0xfc, 0x50, 0xeb, 0xe9, 0x26, 0xf9, 0x41, 0xca, 0x23, 0x32, 0xee, 0xb0, ++ 0x66, 0x6f, 0x37, 0xc9, 0x13, 0xb2, 0x5d, 0xfd, 0x01, 0x0e, 0x97, 0xba, ++ 0x03, 0xfc, 0x7b, 0x59, 0xba, 0x4e, 0xea, 0x51, 0x1c, 0x4a, 0x2a, 0xde, ++ 0xa7, 0x15, 0xca, 0xaf, 0x9e, 0x92, 0x51, 0xba, 0x5e, 0x93, 0x1f, 0x57, ++ 0xba, 0x5e, 0x8f, 0xa9, 0xd0, 0xdb, 0xeb, 0x7b, 0x49, 0x1e, 0xbc, 0x3b, ++ 0xfd, 0x1d, 0xba, 0x87, 0xd7, 0xb5, 0x88, 0x7e, 0x21, 0x6f, 0xf0, 0x1b, ++ 0x6f, 0x09, 0x12, 0xd1, 0x70, 0xfe, 0x3d, 0xc5, 0x82, 0xed, 0x6d, 0x1a, ++ 0xff, 0xda, 0xba, 0x03, 0x11, 0xd4, 0xde, 0x5b, 0x17, 0xbc, 0x19, 0xcf, ++ 0x79, 0x47, 0xbd, 0x45, 0x8f, 0x69, 0x73, 0x9d, 0x85, 0xce, 0xfd, 0x6d, ++ 0x0d, 0xba, 0x74, 0xf4, 0x53, 0x77, 0x28, 0xc1, 0x76, 0x94, 0xe3, 0x3a, ++ 0x84, 0xff, 0xd6, 0xf0, 0x9a, 0xf7, 0xcd, 0xa8, 0x3f, 0x88, 0x63, 0xbd, ++ 0xc7, 0xf1, 0xbd, 0x5d, 0x6f, 0x82, 0xb3, 0x16, 0xf7, 0x43, 0x0c, 0xbe, ++ 0xee, 0xa2, 0xfa, 0xe2, 0x89, 0x7a, 0x8e, 0x7c, 0x9a, 0x8d, 0xfd, 0x17, ++ 0x8c, 0xea, 0xba, 0x8c, 0x6f, 0x6a, 0x18, 0xd6, 0x4f, 0x2a, 0x45, 0x3b, ++ 0xc5, 0xda, 0x7c, 0xb1, 0x8e, 0x8c, 0xae, 0x6c, 0xa4, 0xeb, 0xe1, 0xc7, ++ 0x38, 0x7f, 0x7e, 0xcc, 0xc0, 0x36, 0xd3, 0xbb, 0xcd, 0xfa, 0x62, 0x86, ++ 0xfa, 0x7b, 0xaf, 0xb0, 0x2f, 0xba, 0xbe, 0xd1, 0xd1, 0xfb, 0xb3, 0x1d, ++ 0x8a, 0xf7, 0xd7, 0xfe, 0xf2, 0xd5, 0x1e, 0xb1, 0x6f, 0x8b, 0x83, 0xb8, ++ 0x9d, 0xf1, 0xfe, 0x09, 0xce, 0x5f, 0xe2, 0x3c, 0x7e, 0xaa, 0x18, 0xc6, ++ 0x67, 0x92, 0x7f, 0xa3, 0x3a, 0x1a, 0xfb, 0xef, 0x11, 0x76, 0x48, 0x29, ++ 0xa7, 0xce, 0x14, 0xfc, 0x39, 0x41, 0xdc, 0xaf, 0x8c, 0x23, 0x62, 0x2d, ++ 0x48, 0xc7, 0xd2, 0xaf, 0x4f, 0x71, 0x38, 0x28, 0xde, 0xf3, 0xce, 0x8c, ++ 0x63, 0xe5, 0x78, 0x3e, 0xdf, 0xd3, 0x6b, 0xa2, 0x78, 0x81, 0x99, 0xbd, ++ 0xc1, 0x24, 0xb7, 0x26, 0x8c, 0x98, 0x43, 0xe7, 0x99, 0x7c, 0xb7, 0x5d, ++ 0xb1, 0xe9, 0x59, 0x09, 0xd4, 0x3f, 0x96, 0xa1, 0xf3, 0x62, 0x5c, 0xdc, ++ 0x3d, 0xcc, 0xc4, 0xfd, 0x02, 0x4c, 0x01, 0xf2, 0xad, 0xce, 0x4c, 0xfe, ++ 0xc9, 0x4a, 0xc7, 0xef, 0xbe, 0x41, 0xbe, 0x1e, 0xaf, 0x5e, 0x3a, 0x1e, ++ 0x8e, 0xfe, 0xb2, 0xff, 0xae, 0xd0, 0xfb, 0xa3, 0xa5, 0x7d, 0x67, 0x1f, ++ 0x7b, 0x9b, 0xe1, 0x7d, 0xd8, 0x9d, 0x49, 0xf1, 0xd0, 0x09, 0xce, 0x87, ++ 0x10, 0x85, 0x27, 0xfb, 0xe6, 0x74, 0x3b, 0x01, 0x75, 0xf7, 0x58, 0x3d, ++ 0x26, 0x3b, 0x3f, 0x2f, 0x98, 0xff, 0x3a, 0x3a, 0x7e, 0xfe, 0x4d, 0x58, ++ 0xa4, 0xce, 0x37, 0xbf, 0x9e, 0xde, 0xb3, 0xf4, 0xae, 0x63, 0x4f, 0xaf, ++ 0x89, 0xf4, 0xb6, 0x33, 0x3b, 0xc4, 0x3b, 0x87, 0x01, 0xf3, 0xe9, 0x89, ++ 0xb5, 0x91, 0x9f, 0x34, 0xd4, 0x23, 0x79, 0xb3, 0xc7, 0xa2, 0xa3, 0xf7, ++ 0xdd, 0x66, 0x76, 0x1c, 0xa7, 0xf7, 0x0a, 0x67, 0xca, 0xf7, 0x0c, 0x4d, ++ 0xda, 0xf7, 0x0c, 0x99, 0x2d, 0x21, 0x02, 0xf5, 0xca, 0xa4, 0x4b, 0x05, ++ 0xe1, 0x20, 0xba, 0x99, 0xe3, 0xaf, 0x20, 0x5c, 0x7b, 0x5f, 0xec, 0xc8, ++ 0xe7, 0xf2, 0x62, 0x87, 0xe0, 0x23, 0x81, 0xef, 0xdd, 0xcb, 0xb8, 0x15, ++ 0x79, 0xae, 0xbc, 0x6c, 0xd9, 0x75, 0x0b, 0xd7, 0x4b, 0xf1, 0x7d, 0xba, ++ 0x4a, 0xda, 0xf9, 0xaf, 0x24, 0x93, 0x3c, 0xd1, 0xd7, 0x91, 0xf2, 0x9d, ++ 0xef, 0x58, 0xbc, 0x8b, 0x72, 0x05, 0xc8, 0x0b, 0xa7, 0xae, 0x76, 0xbc, ++ 0x92, 0x3f, 0xdc, 0x77, 0xae, 0x2e, 0x14, 0x70, 0x92, 0xe7, 0xb3, 0x8c, ++ 0x5b, 0x58, 0x28, 0xe0, 0xb5, 0xd0, 0xa2, 0xe3, 0xf0, 0x09, 0xf8, 0xdd, ++ 0x15, 0x49, 0x37, 0x81, 0x74, 0xe1, 0xc3, 0x3b, 0x8f, 0xf7, 0x92, 0xf8, ++ 0x64, 0xb7, 0x77, 0xbe, 0x8a, 0xf1, 0x58, 0x80, 0xc7, 0xf1, 0xf7, 0x31, ++ 0xc2, 0xdf, 0xdb, 0x48, 0x8f, 0x27, 0xbf, 0x79, 0x73, 0x03, 0x3e, 0xbb, ++ 0x30, 0x42, 0x75, 0x74, 0x3b, 0x93, 0x7e, 0x14, 0xfc, 0xd1, 0xfb, 0xdd, ++ 0x3f, 0x18, 0x7f, 0x9d, 0x81, 0xf8, 0xf3, 0x9a, 0xc7, 0xa0, 0x1c, 0xf1, ++ 0x80, 0x8e, 0xe4, 0x08, 0xe9, 0xef, 0xe8, 0x14, 0xef, 0xb5, 0x4b, 0xbf, ++ 0x47, 0x96, 0xce, 0x88, 0x1f, 0x94, 0xaa, 0xc1, 0xa4, 0x2f, 0x74, 0x8a, ++ 0x77, 0xda, 0x81, 0x0f, 0xbc, 0x8a, 0x7c, 0x40, 0xee, 0xff, 0x51, 0x73, ++ 0xba, 0xc6, 0xe3, 0x39, 0x7a, 0x12, 0xae, 0xe8, 0x38, 0xbf, 0x2e, 0x9d, ++ 0x87, 0xbe, 0x87, 0x4f, 0xe3, 0xfe, 0x86, 0x23, 0x59, 0x67, 0x9c, 0xf0, ++ 0xcf, 0xc9, 0x45, 0xf9, 0x4d, 0xf5, 0xbd, 0x4f, 0x4d, 0x74, 0xdf, 0xac, ++ 0xb8, 0x1f, 0xae, 0x44, 0xff, 0xcb, 0x85, 0x16, 0xf2, 0x73, 0xef, 0x71, ++ 0x07, 0xbc, 0x4f, 0x2d, 0xde, 0x31, 0xef, 0x61, 0x82, 0x3f, 0x2c, 0x96, ++ 0xef, 0x98, 0xc3, 0x7e, 0x86, 0x76, 0x6d, 0x4b, 0x78, 0x79, 0xff, 0x3b, ++ 0xe6, 0xa3, 0x19, 0xdd, 0xa3, 0xda, 0x32, 0x59, 0x1a, 0xca, 0x5f, 0x6d, ++ 0xe2, 0x77, 0x7f, 0x86, 0x7c, 0xc7, 0x7c, 0x65, 0x24, 0xe9, 0x4d, 0x1f, ++ 0x79, 0xc4, 0x3d, 0x16, 0xcf, 0x03, 0xf9, 0x7e, 0xf5, 0xf4, 0x04, 0xa7, ++ 0x79, 0xda, 0xf0, 0x81, 0xef, 0x57, 0x3f, 0xa8, 0x14, 0x2f, 0xc1, 0xdf, ++ 0x81, 0x71, 0x8d, 0xe7, 0xf3, 0xed, 0x5a, 0x12, 0xfc, 0xcc, 0x2e, 0x0e, ++ 0x6e, 0x2f, 0xea, 0x7b, 0x4e, 0x36, 0x86, 0xd2, 0xbb, 0xdd, 0x92, 0x4e, ++ 0xa5, 0x9e, 0x7b, 0x94, 0xab, 0xfb, 0x61, 0x84, 0x93, 0x8c, 0xab, 0xfd, ++ 0x58, 0xd0, 0x9b, 0x84, 0xbf, 0x8c, 0x2b, 0x8c, 0x0a, 0xc0, 0x83, 0xa4, ++ 0xbb, 0xfe, 0xdf, 0x8b, 0x59, 0xc7, 0xe9, 0xaf, 0xdf, 0x9f, 0xb6, 0x9e, ++ 0x91, 0x3e, 0x65, 0x24, 0x4c, 0x25, 0x84, 0xfc, 0x23, 0xed, 0x36, 0x84, ++ 0xeb, 0x3d, 0x89, 0xce, 0x24, 0x9c, 0x7f, 0xf3, 0x6a, 0x80, 0x33, 0xe9, ++ 0xd1, 0xb9, 0x9f, 0xe7, 0x49, 0xf1, 0x7b, 0x16, 0x81, 0xfb, 0x29, 0x63, ++ 0x9a, 0x4e, 0xda, 0x89, 0x29, 0x5e, 0xa0, 0x54, 0x9c, 0x6b, 0xa5, 0x32, ++ 0x3e, 0xa0, 0x51, 0x1b, 0x1f, 0x10, 0xf8, 0xbe, 0x69, 0xf0, 0xc8, 0xe2, ++ 0x09, 0xd3, 0x60, 0x9d, 0x17, 0x94, 0x77, 0x27, 0xe2, 0xc7, 0x37, 0xff, ++ 0xb7, 0x3a, 0xa8, 0xdf, 0xc9, 0xa4, 0x69, 0x9c, 0x8f, 0xa7, 0xc6, 0x3a, ++ 0x27, 0x4e, 0xa3, 0xf3, 0x6d, 0xa6, 0x46, 0x8e, 0x7c, 0x33, 0xf3, 0xd3, ++ 0x04, 0xfa, 0x7d, 0x99, 0x6f, 0x8f, 0x8f, 0xc4, 0x73, 0xef, 0xa6, 0x84, ++ 0xe2, 0xc9, 0xd8, 0xaf, 0x39, 0x95, 0xdb, 0x0d, 0x3e, 0x8e, 0xeb, 0xa2, ++ 0xf8, 0x8e, 0x8f, 0x97, 0xfc, 0x2d, 0x81, 0xf4, 0xce, 0xeb, 0xf8, 0xbb, ++ 0xac, 0x3f, 0x74, 0x9e, 0x03, 0xe3, 0x99, 0x39, 0x1d, 0xdc, 0xb6, 0x9c, ++ 0xfb, 0x23, 0xc6, 0xb3, 0x06, 0xa2, 0xdf, 0x58, 0x5f, 0x9c, 0xac, 0x19, ++ 0xe7, 0xf1, 0x3f, 0x2d, 0x9e, 0xd9, 0x17, 0x6f, 0xbc, 0x9b, 0x7e, 0x57, ++ 0xe4, 0xe5, 0x26, 0x4f, 0xca, 0x99, 0xd1, 0x03, 0xf1, 0x91, 0x1f, 0x74, ++ 0xec, 0x39, 0x1b, 0xdc, 0x68, 0x1a, 0x8e, 0x1c, 0x2a, 0xa5, 0xf8, 0xde, ++ 0xf0, 0x63, 0xb7, 0x25, 0x41, 0xbe, 0xf1, 0xc8, 0x4b, 0x3c, 0x1f, 0x7f, ++ 0xec, 0x72, 0x12, 0xe0, 0xe6, 0xf6, 0x23, 0x1d, 0x3c, 0x3f, 0xee, 0xd8, ++ 0x65, 0x8c, 0x07, 0x5e, 0x77, 0xe4, 0x48, 0x29, 0xc5, 0xff, 0xa2, 0xdd, ++ 0x60, 0x04, 0x63, 0x77, 0x1c, 0x79, 0xb9, 0xd4, 0x05, 0xf8, 0xa8, 0x9e, ++ 0xe0, 0x6c, 0x42, 0x7c, 0x2d, 0xba, 0xd2, 0xf0, 0x2a, 0x1e, 0xc3, 0xef, ++ 0xad, 0x9f, 0xbf, 0x3c, 0x89, 0xe2, 0x59, 0xe7, 0x25, 0xa4, 0xf3, 0x78, ++ 0xd6, 0xb5, 0x58, 0xbe, 0x30, 0x7a, 0xd9, 0x86, 0x70, 0xc5, 0x17, 0xcf, ++ 0xba, 0x6d, 0x1a, 0xb4, 0x03, 0x7a, 0xe8, 0xb9, 0xc4, 0xe9, 0xbf, 0xe7, ++ 0x12, 0xa7, 0xf7, 0x20, 0xe4, 0x03, 0xc3, 0xff, 0xf5, 0x54, 0xc6, 0xf5, ++ 0x4a, 0xfe, 0x3b, 0x14, 0x9f, 0x94, 0xfb, 0xef, 0xc7, 0x8a, 0x4b, 0x96, ++ 0xfb, 0x98, 0xed, 0xb2, 0x6f, 0x36, 0x20, 0x31, 0xba, 0xfe, 0xe5, 0x78, ++ 0xe1, 0x47, 0x68, 0xdf, 0x04, 0xc4, 0x0b, 0xf7, 0x18, 0x7a, 0x1f, 0x27, ++ 0x7b, 0xd2, 0x25, 0x66, 0xc3, 0x38, 0xc4, 0xa3, 0xa1, 0xef, 0xdb, 0xf0, ++ 0x9c, 0x68, 0xce, 0xe5, 0xf1, 0x8c, 0x4a, 0x6f, 0xa7, 0x0d, 0xfd, 0x30, ++ 0xf2, 0x73, 0x78, 0xbe, 0xf9, 0x52, 0xa7, 0x0d, 0xf9, 0x3b, 0xe6, 0x51, ++ 0xaf, 0xd5, 0x13, 0xc1, 0xe3, 0x1c, 0x65, 0x3c, 0x6c, 0xf3, 0x25, 0x6f, ++ 0x1c, 0xee, 0x93, 0x7c, 0x8c, 0x5b, 0x84, 0xfa, 0x85, 0xbd, 0xbd, 0xa5, ++ 0xc8, 0x6f, 0xf2, 0xd1, 0x8f, 0x37, 0x09, 0xfb, 0x7f, 0xed, 0xb8, 0x18, ++ 0x8f, 0x61, 0x7f, 0x3b, 0x2e, 0xf1, 0x78, 0xc3, 0x1e, 0x73, 0xa7, 0xcd, ++ 0x2a, 0xc6, 0xc1, 0x7e, 0x60, 0xdc, 0x24, 0xe4, 0x8b, 0xf9, 0x6b, 0x4d, ++ 0xe4, 0x6f, 0xd4, 0x7c, 0xa9, 0x61, 0x35, 0xf5, 0x53, 0x62, 0xe9, 0x1f, ++ 0x57, 0x09, 0x18, 0xd7, 0xf4, 0xdd, 0xe3, 0xce, 0x52, 0xfc, 0xc6, 0x4d, ++ 0xed, 0xe3, 0x71, 0x9d, 0x38, 0xae, 0x4d, 0x33, 0xae, 0x97, 0xe2, 0x81, ++ 0xa1, 0x3f, 0x8a, 0x3b, 0xed, 0x89, 0xb0, 0xc7, 0xe2, 0x7d, 0x5f, 0xe6, ++ 0x0b, 0xb1, 0x1c, 0xf2, 0x0f, 0x89, 0xdf, 0xa7, 0xc8, 0xb7, 0x79, 0x55, ++ 0xe4, 0xff, 0x32, 0x3e, 0x2a, 0xc6, 0x28, 0xde, 0xe1, 0x16, 0xf7, 0x15, ++ 0xa8, 0x47, 0xf1, 0x98, 0x3b, 0xfa, 0xf8, 0x3a, 0x2f, 0x36, 0x79, 0xab, ++ 0x71, 0x3f, 0x15, 0x0a, 0x7e, 0x5d, 0x68, 0xe4, 0xe7, 0x25, 0xd3, 0x05, ++ 0xdb, 0xd1, 0x0f, 0xbb, 0x48, 0xfd, 0xf6, 0xb5, 0x78, 0xbc, 0x97, 0xbc, ++ 0xc0, 0xef, 0x25, 0x85, 0x41, 0xc5, 0xdb, 0x70, 0x3f, 0xd6, 0xeb, 0x39, ++ 0xbf, 0x61, 0x51, 0xf2, 0x77, 0xd2, 0x3a, 0x57, 0xfe, 0x06, 0xea, 0xbd, ++ 0x13, 0x1d, 0x4f, 0xbf, 0x2b, 0x36, 0x32, 0xf6, 0x10, 0x4b, 0xc5, 0x7b, ++ 0xf1, 0xaa, 0x39, 0x19, 0x78, 0x5e, 0x80, 0xbc, 0xfd, 0x11, 0xe2, 0xfb, ++ 0x1d, 0xd6, 0xaa, 0xf0, 0xdf, 0xdf, 0xe2, 0xed, 0x17, 0xcc, 0x09, 0x21, ++ 0xff, 0x93, 0x9e, 0x23, 0x63, 0x72, 0x71, 0xff, 0xcc, 0x0f, 0xb2, 0x1d, ++ 0x64, 0xb0, 0x6f, 0x4f, 0x4d, 0xbb, 0x44, 0xfb, 0x74, 0x7e, 0xb8, 0x2d, ++ 0x17, 0x6f, 0x3a, 0xa7, 0x8e, 0x5c, 0xe6, 0xf9, 0x18, 0xdb, 0x41, 0xb4, ++ 0xeb, 0x9a, 0xd8, 0xa5, 0xd2, 0x42, 0xba, 0xa7, 0x71, 0x3b, 0xed, 0x4d, ++ 0x3e, 0x3b, 0xed, 0xa7, 0xb8, 0x2f, 0xeb, 0xe6, 0x5c, 0x30, 0x72, 0xb9, ++ 0xac, 0x97, 0xde, 0x67, 0x3e, 0x37, 0x8d, 0x9f, 0x5f, 0x20, 0xb7, 0x93, ++ 0xdc, 0xd1, 0x7b, 0x8d, 0x78, 0x6f, 0x33, 0xc3, 0x96, 0x8b, 0xe5, 0x89, ++ 0x86, 0xde, 0x30, 0x84, 0x5b, 0xcf, 0xb7, 0x7a, 0xfe, 0x5e, 0x2d, 0xeb, ++ 0x0d, 0xbb, 0xd1, 0xcf, 0x2e, 0xfb, 0x78, 0x07, 0x7f, 0xc7, 0x36, 0x90, ++ 0xae, 0xf7, 0x15, 0xf0, 0x73, 0x60, 0x55, 0xaa, 0x85, 0xde, 0x39, 0xab, ++ 0x8f, 0x35, 0x99, 0x28, 0xed, 0xb8, 0x34, 0x9b, 0x7e, 0x07, 0x46, 0x5f, ++ 0x9c, 0x8a, 0xf7, 0x02, 0x87, 0x71, 0x70, 0x7d, 0xe3, 0x13, 0x05, 0x5c, ++ 0xde, 0x4c, 0xda, 0x68, 0xf4, 0xd9, 0xdd, 0xe1, 0xfc, 0x70, 0x04, 0x33, ++ 0x99, 0x77, 0xb1, 0x3c, 0xc6, 0xb6, 0xff, 0x5b, 0x70, 0xff, 0xbd, 0x0b, ++ 0x8f, 0x18, 0xe3, 0x68, 0x71, 0x0f, 0x73, 0x59, 0x9f, 0x28, 0x4c, 0xd5, ++ 0xd4, 0x77, 0x60, 0xfd, 0xfe, 0x72, 0xc6, 0x9f, 0x67, 0x93, 0xed, 0x47, ++ 0xbe, 0xac, 0x7f, 0x02, 0xed, 0xf8, 0x34, 0x1e, 0xe2, 0xb9, 0x92, 0xfb, ++ 0x4d, 0x04, 0x9e, 0x17, 0xa5, 0xd3, 0x23, 0x35, 0xfe, 0x56, 0x8f, 0x45, ++ 0x99, 0xc9, 0xdf, 0x2a, 0x55, 0x15, 0x7a, 0x3c, 0xa8, 0x6b, 0x25, 0x7d, ++ 0x20, 0xb7, 0xdb, 0xc6, 0xff, 0xa7, 0x99, 0xe2, 0xe7, 0x76, 0x98, 0x39, ++ 0x1d, 0xa6, 0xea, 0x78, 0xba, 0x43, 0x27, 0xe2, 0x7c, 0x85, 0x9e, 0x4f, ++ 0xde, 0x5f, 0x7e, 0x31, 0xdd, 0x39, 0x7e, 0x7a, 0x2e, 0xf5, 0xe3, 0xa5, ++ 0x7e, 0xd4, 0xfd, 0x99, 0x28, 0x4f, 0xc4, 0x31, 0x0f, 0x8d, 0x2f, 0xe5, ++ 0x32, 0x59, 0x0f, 0xe4, 0x2f, 0x33, 0x31, 0x19, 0xf1, 0x3b, 0x6f, 0xf9, ++ 0xaa, 0x6e, 0x50, 0x78, 0xbe, 0x52, 0x30, 0xc3, 0x51, 0x90, 0x8b, 0x74, ++ 0xed, 0x62, 0x9f, 0xf8, 0x9d, 0x13, 0x17, 0x43, 0xc2, 0x1a, 0xfd, 0xf1, ++ 0x57, 0xaf, 0x6a, 0xf5, 0x9d, 0xaf, 0x14, 0xcc, 0xa4, 0x76, 0xb2, 0x7d, ++ 0x5d, 0xe3, 0x2c, 0xf6, 0x09, 0xc5, 0x21, 0x7a, 0x89, 0x7e, 0xea, 0x52, ++ 0x75, 0x74, 0x5f, 0xad, 0x57, 0xd9, 0x2b, 0xf4, 0x7b, 0x03, 0xac, 0x93, ++ 0xec, 0x98, 0xb2, 0xdd, 0xfb, 0xc0, 0x27, 0x3f, 0xa1, 0xf7, 0x1a, 0x1c, ++ 0x94, 0x7e, 0x00, 0xfc, 0xf2, 0x13, 0xf2, 0xf3, 0x5b, 0x4c, 0xe9, 0x5f, ++ 0x9a, 0x9c, 0xf4, 0xfd, 0x64, 0x53, 0x15, 0xa5, 0x5d, 0x4d, 0x0d, 0xf4, ++ 0xfd, 0x54, 0x53, 0x23, 0xa5, 0x8b, 0x6e, 0x0e, 0xcd, 0x41, 0xfa, 0x5f, ++ 0x75, 0x78, 0x3d, 0xfb, 0xc4, 0xef, 0x7c, 0xac, 0xf3, 0x18, 0x9c, 0xfe, ++ 0x7e, 0x35, 0xef, 0xcf, 0x18, 0x9c, 0x8e, 0x2a, 0x05, 0x1d, 0xbd, 0x9f, ++ 0x34, 0x78, 0x79, 0x53, 0x01, 0x97, 0x8b, 0xde, 0x2f, 0xe0, 0xf8, 0xec, ++ 0x59, 0xce, 0xe5, 0x4b, 0xa0, 0xcb, 0x16, 0x6b, 0xe4, 0xd0, 0xf2, 0x42, ++ 0x4f, 0x28, 0xf7, 0x47, 0x78, 0x69, 0x26, 0xa7, 0xf3, 0x9e, 0x38, 0x9e, ++ 0x77, 0x16, 0xf0, 0x77, 0x42, 0x1d, 0x3a, 0xd6, 0x8e, 0xed, 0x5f, 0x9a, ++ 0xc9, 0xdf, 0x61, 0x7f, 0x3f, 0x59, 0x47, 0xef, 0x39, 0x38, 0x22, 0x79, ++ 0xbf, 0xef, 0xa7, 0xe9, 0x48, 0x4e, 0xbb, 0x76, 0xf6, 0x8c, 0x52, 0x84, ++ 0x93, 0x23, 0x1a, 0xbe, 0x67, 0xf9, 0xf2, 0xef, 0x5f, 0xc5, 0xcb, 0x1d, ++ 0x23, 0xf8, 0x77, 0x39, 0x5f, 0x59, 0x3e, 0x7e, 0x7a, 0xbf, 0xfe, 0x20, ++ 0x8d, 0xdf, 0x8b, 0xb9, 0xdd, 0x1d, 0xe8, 0x9d, 0xfa, 0xef, 0xc7, 0x6f, ++ 0x21, 0x9f, 0x5f, 0x60, 0x7d, 0xe9, 0x47, 0x1f, 0x08, 0x8f, 0xa3, 0x62, ++ 0xdf, 0xd2, 0xbe, 0x40, 0xb9, 0x1d, 0xf7, 0x41, 0x92, 0xdf, 0xbe, 0xa8, ++ 0xb7, 0xd1, 0xbe, 0x90, 0x74, 0x28, 0xe9, 0xaf, 0x74, 0x3a, 0x87, 0x73, ++ 0x6a, 0x90, 0xa0, 0x73, 0x38, 0xbb, 0x08, 0x7e, 0x78, 0x86, 0xe1, 0xbd, ++ 0x38, 0xc6, 0x4c, 0x72, 0xac, 0x03, 0xed, 0x16, 0xb0, 0x9e, 0x1d, 0x22, ++ 0xce, 0x7d, 0xc0, 0x7e, 0x10, 0x76, 0x00, 0xb9, 0x1f, 0xe4, 0x3e, 0x90, ++ 0xf4, 0x1e, 0x0f, 0xfb, 0x8c, 0xdb, 0x39, 0xf8, 0x3a, 0xa6, 0xa9, 0x83, ++ 0xeb, 0xe7, 0x37, 0x15, 0xf0, 0x7b, 0x6a, 0x67, 0x74, 0xe8, 0xcf, 0x08, ++ 0xaf, 0x1d, 0x06, 0x2b, 0x9e, 0x37, 0xd3, 0x54, 0x6e, 0x6f, 0xe8, 0xe9, ++ 0x58, 0x98, 0x83, 0xfe, 0xe0, 0x45, 0x9b, 0x2c, 0x0d, 0x83, 0xf1, 0xaf, ++ 0x97, 0x45, 0xfb, 0x7f, 0x19, 0x0e, 0x92, 0x1f, 0x0c, 0x01, 0x87, 0x01, ++ 0xeb, 0x37, 0x0a, 0x7d, 0xfd, 0x3f, 0xb9, 0x7e, 0xe2, 0x6f, 0xc8, 0xb7, ++ 0x97, 0x73, 0x7f, 0xcc, 0x40, 0x7a, 0xdd, 0x5b, 0x20, 0xf9, 0x15, 0xa7, ++ 0xdb, 0x57, 0x0a, 0x1c, 0xbb, 0x90, 0x7e, 0x7a, 0x14, 0xb3, 0x1e, 0xef, ++ 0x27, 0x3d, 0xe6, 0xc1, 0xfd, 0xc7, 0x5f, 0x9a, 0xc9, 0xf7, 0x85, 0xa4, ++ 0x9f, 0xd2, 0xe9, 0x4c, 0xbc, 0x3f, 0x03, 0xeb, 0x4c, 0x19, 0xc8, 0xef, ++ 0xe4, 0x7a, 0xfa, 0xd7, 0xb9, 0x82, 0x11, 0xdf, 0x4b, 0x15, 0x71, 0xc6, ++ 0x81, 0xf8, 0x95, 0xeb, 0xf2, 0xe3, 0x7b, 0x1d, 0x05, 0x7e, 0x7a, 0x27, ++ 0xc6, 0x40, 0x5e, 0x81, 0x7e, 0x46, 0xd6, 0x5a, 0xe8, 0x7e, 0x2a, 0xe9, ++ 0xf7, 0xe2, 0xf0, 0x6f, 0x2a, 0xf1, 0xfc, 0x9a, 0x53, 0x60, 0xe3, 0xf6, ++ 0x17, 0x9d, 0x2a, 0xde, 0x81, 0xe5, 0xe7, 0x49, 0xff, 0x77, 0x45, 0xa5, ++ 0x78, 0x2b, 0xbf, 0x73, 0x86, 0xa1, 0xdc, 0xd2, 0x7b, 0x84, 0xdb, 0xe1, ++ 0xbc, 0x70, 0x4f, 0x42, 0x3b, 0x16, 0xea, 0x9e, 0xfd, 0xe3, 0xad, 0xbf, ++ 0x16, 0xfc, 0xa2, 0x6f, 0x71, 0xae, 0x0e, 0xf5, 0x03, 0x17, 0xbf, 0xb6, ++ 0xb8, 0xf0, 0xdc, 0xba, 0x38, 0xa2, 0xf7, 0x24, 0xca, 0x25, 0x17, 0xdb, ++ 0xf9, 0x3b, 0xe7, 0xd0, 0xe3, 0x5c, 0x05, 0xfd, 0x45, 0x30, 0xee, 0xc7, ++ 0x86, 0xbf, 0xd7, 0xc2, 0xed, 0x1f, 0xea, 0xc3, 0x5f, 0x9d, 0x44, 0x79, ++ 0xa8, 0xf2, 0x61, 0x95, 0xe4, 0x97, 0x8b, 0x78, 0x5d, 0x86, 0x76, 0xab, ++ 0x1e, 0xe0, 0xbf, 0x6f, 0x27, 0xfd, 0x06, 0x6b, 0x45, 0xbb, 0xe6, 0xf6, ++ 0xcb, 0x8b, 0xe8, 0x77, 0xcd, 0x80, 0x3e, 0x51, 0xfe, 0xf9, 0xc4, 0x5c, ++ 0x9f, 0x8c, 0x72, 0xf1, 0xac, 0x87, 0x1f, 0x38, 0x81, 0xef, 0xae, 0x57, ++ 0x1e, 0x54, 0x50, 0xcd, 0xcc, 0x8e, 0xa3, 0xbe, 0x1d, 0xf2, 0x67, 0x77, ++ 0xab, 0xfc, 0xf7, 0x55, 0x45, 0xbc, 0xc9, 0x6c, 0xe1, 0xd7, 0x5f, 0xbd, ++ 0x93, 0xfb, 0xf5, 0xd7, 0x62, 0x9c, 0x09, 0xca, 0x2f, 0x07, 0xb6, 0x3f, ++ 0x88, 0xbf, 0x3b, 0x59, 0xb7, 0xdb, 0xc0, 0xcc, 0xf0, 0x7d, 0x36, 0xbe, ++ 0x8f, 0x06, 0xe3, 0xac, 0xf0, 0x84, 0xc2, 0x05, 0x12, 0xfa, 0x6d, 0xd3, ++ 0xc6, 0xa5, 0xfe, 0x84, 0xb9, 0x36, 0xa2, 0x1e, 0xb9, 0x6a, 0x9b, 0xf6, ++ 0x7b, 0xf5, 0x0e, 0x6d, 0xbe, 0x36, 0xc0, 0x5f, 0xf1, 0x52, 0x81, 0xf0, ++ 0x4b, 0x1c, 0xcb, 0x32, 0xc9, 0x2f, 0xb1, 0x8d, 0xeb, 0x89, 0x25, 0xdf, ++ 0x1e, 0x28, 0xef, 0xba, 0x38, 0x7f, 0x5c, 0x23, 0xfd, 0x74, 0xbf, 0xa4, ++ 0x77, 0xbd, 0xd5, 0x23, 0x5f, 0x25, 0x9e, 0xb2, 0xf0, 0xfc, 0x3c, 0x91, ++ 0xef, 0x86, 0xfc, 0x85, 0xaf, 0x38, 0xfc, 0x25, 0xdc, 0xea, 0x05, 0xcf, ++ 0xbf, 0x10, 0xc7, 0x72, 0x3c, 0xb0, 0xbe, 0xfa, 0x23, 0x66, 0x2b, 0xde, ++ 0xff, 0xeb, 0x5f, 0xe0, 0xfa, 0x81, 0x8b, 0x9e, 0x70, 0x82, 0xf3, 0xaa, ++ 0xe0, 0x2e, 0xb2, 0x27, 0xb0, 0x17, 0x55, 0x2b, 0xca, 0x61, 0x77, 0x1d, ++ 0x56, 0x49, 0x9f, 0x50, 0xd7, 0x61, 0xfe, 0x35, 0xfe, 0x1e, 0x6d, 0xfd, ++ 0x41, 0x85, 0xde, 0xa9, 0xad, 0x3b, 0x1c, 0xe4, 0xe6, 0xf0, 0xb9, 0x54, ++ 0x89, 0xe5, 0x2b, 0x0e, 0x9b, 0xad, 0x36, 0x2c, 0x7f, 0x31, 0x88, 0xa1, ++ 0xde, 0xf9, 0x22, 0xe0, 0x0d, 0xfd, 0x61, 0x2f, 0x26, 0x74, 0x11, 0xfe, ++ 0x11, 0xaf, 0xa8, 0x8f, 0x80, 0xbf, 0xb9, 0xf8, 0xbb, 0x15, 0x12, 0xff, ++ 0xea, 0xc3, 0xdc, 0x8e, 0x5c, 0xb9, 0x47, 0xe0, 0xa7, 0xfd, 0x36, 0x3d, ++ 0xe1, 0xd5, 0xad, 0xb0, 0x98, 0xa4, 0x81, 0x78, 0x92, 0x78, 0xfe, 0x9d, ++ 0xee, 0xe9, 0x7e, 0x3c, 0x61, 0xbb, 0x59, 0x0f, 0xbf, 0xf7, 0x9a, 0xc0, ++ 0x3b, 0xc3, 0x38, 0x9b, 0xe3, 0xed, 0xe5, 0xf4, 0x7b, 0x18, 0x12, 0xdf, ++ 0xc6, 0x23, 0x9f, 0x24, 0xa2, 0xdc, 0x2b, 0xf1, 0xac, 0x02, 0x9e, 0x7f, ++ 0x21, 0xdb, 0xdb, 0xc4, 0x3b, 0x78, 0xdf, 0x81, 0xe7, 0x2a, 0xc4, 0xb3, ++ 0xe5, 0x9f, 0xc7, 0xf3, 0xeb, 0x05, 0x4c, 0xc6, 0xfb, 0x9d, 0x7d, 0x14, ++ 0xe5, 0xde, 0x50, 0x23, 0xd9, 0xcf, 0xa5, 0x3e, 0x43, 0xea, 0x2f, 0x86, ++ 0xd7, 0xbc, 0xff, 0x6a, 0x14, 0x0c, 0x3c, 0x3a, 0xf6, 0x39, 0x92, 0x73, ++ 0x4b, 0x23, 0xcf, 0xd5, 0xad, 0x66, 0xa4, 0x3f, 0x9b, 0x34, 0x1d, 0xf5, ++ 0x9f, 0xd7, 0xbc, 0x85, 0x3f, 0xe7, 0xcb, 0xde, 0xb9, 0xf6, 0xe9, 0x4c, ++ 0xa4, 0x8f, 0x66, 0x43, 0x17, 0xfd, 0x5e, 0x8c, 0x2b, 0x82, 0xbf, 0x27, ++ 0xdf, 0x93, 0x34, 0x6f, 0xdb, 0xf3, 0x30, 0x5e, 0x61, 0xe4, 0x37, 0x89, ++ 0xfb, 0x71, 0xdf, 0xbc, 0x1c, 0x44, 0x66, 0x93, 0x59, 0x82, 0xaf, 0xe2, ++ 0x9f, 0xc9, 0xff, 0x3d, 0xc0, 0x0e, 0x33, 0xe9, 0xd9, 0xea, 0x3a, 0x82, ++ 0xb8, 0x5e, 0xed, 0x80, 0xd6, 0x6e, 0xd6, 0x13, 0xc7, 0x7f, 0x9f, 0xaf, ++ 0xc8, 0xd8, 0x5b, 0xba, 0x1a, 0xe5, 0x72, 0xe8, 0x0f, 0xc7, 0x91, 0xf7, ++ 0xc1, 0x9a, 0x0e, 0xf1, 0xbb, 0x2f, 0xe2, 0xfe, 0x56, 0x23, 0xf5, 0x0c, ++ 0x7b, 0x03, 0xde, 0x85, 0xb2, 0xbe, 0x45, 0xf5, 0x4a, 0xa6, 0x27, 0xd3, ++ 0x3c, 0x52, 0x62, 0xa6, 0xd9, 0x90, 0x0f, 0x35, 0x2f, 0x61, 0xce, 0xe0, ++ 0x94, 0xef, 0xe2, 0xf7, 0x5c, 0x7f, 0x23, 0x7f, 0x27, 0x6f, 0x48, 0x39, ++ 0x70, 0x08, 0xbe, 0x2f, 0xe5, 0x3f, 0xe6, 0xd2, 0xea, 0x39, 0x24, 0xff, ++ 0x59, 0x21, 0x7e, 0x57, 0xb2, 0x7f, 0x7f, 0x88, 0x7c, 0xd5, 0x7a, 0x57, ++ 0x98, 0x49, 0x25, 0xba, 0xa3, 0x78, 0xf1, 0xda, 0xc7, 0xf8, 0xef, 0x2a, ++ 0x7e, 0x8a, 0x74, 0x17, 0xe6, 0xa3, 0xa7, 0x7a, 0x11, 0x97, 0xf6, 0xea, ++ 0xbf, 0xbd, 0xae, 0xc7, 0xdf, 0x67, 0xea, 0xd9, 0xc1, 0xfd, 0x22, 0x80, ++ 0x43, 0x3e, 0x88, 0xfe, 0xf9, 0xe7, 0x3d, 0x3c, 0x0e, 0xae, 0x3a, 0xa7, ++ 0x7b, 0xa2, 0xd7, 0x86, 0xbf, 0xcf, 0xc1, 0xf9, 0xd0, 0xca, 0xbd, 0x8a, ++ 0xdb, 0x96, 0x34, 0x08, 0x1d, 0x31, 0xf7, 0x46, 0xfe, 0x9e, 0x7d, 0x00, ++ 0x3d, 0xed, 0xfd, 0xee, 0xf7, 0x0e, 0x6f, 0x9f, 0x2e, 0xe2, 0xdd, 0xc6, ++ 0xb2, 0xf1, 0xff, 0x00, 0x78, 0x6e, 0xc7, 0xf8, 0xa3, 0x5c, 0x1f, 0xbf, ++ 0x08, 0x8c, 0x9b, 0xec, 0x3f, 0xbf, 0x02, 0x7e, 0xbf, 0xe3, 0x7f, 0x5a, ++ 0x1c, 0x77, 0x5f, 0x06, 0xac, 0xe7, 0x3b, 0xec, 0x8c, 0x3f, 0x89, 0xd5, ++ 0xbe, 0xdf, 0x72, 0x8d, 0x4d, 0xfb, 0xfb, 0x4c, 0xd7, 0xa5, 0x6b, 0x7f, ++ 0x9f, 0xa9, 0xcf, 0x22, 0xe0, 0x23, 0xe4, 0x41, 0x29, 0xa7, 0xee, 0x9e, ++ 0xce, 0xe5, 0x99, 0xc0, 0x54, 0xc2, 0xf7, 0x7a, 0xbb, 0x76, 0x1c, 0x79, ++ 0x2f, 0xfe, 0x69, 0x9e, 0x76, 0xbc, 0x79, 0x0e, 0xed, 0x78, 0x3f, 0x14, ++ 0x2f, 0x3f, 0x56, 0x3c, 0xeb, 0xf7, 0xc1, 0xef, 0x35, 0x31, 0xee, 0x09, ++ 0x31, 0xee, 0xeb, 0x62, 0xdc, 0x7f, 0x15, 0x4e, 0x32, 0x1d, 0x6a, 0xbc, ++ 0xff, 0x9f, 0xfe, 0xbf, 0x49, 0xff, 0x0f, 0x42, 0x61, 0x39, 0x64, 0x00, ++ 0x80, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x0b, 0xb5, 0x5b, 0x0b, 0x7c, 0x94, 0xd5, 0x95, 0xbf, 0xdf, 0x7c, ++ 0xf3, 0xcc, 0x73, 0x08, 0x21, 0x09, 0x04, 0xc2, 0x24, 0x24, 0x21, 0x60, ++ 0x88, 0x03, 0x24, 0x54, 0x2b, 0x96, 0xc9, 0xd3, 0x00, 0xd6, 0x06, 0x5c, ++ 0x2d, 0x68, 0x84, 0x01, 0x52, 0xc8, 0x3b, 0x80, 0xb5, 0xd2, 0x16, 0x7f, ++ 0x19, 0x04, 0x11, 0x10, 0x5b, 0xa8, 0xd1, 0xa2, 0x22, 0x4e, 0x82, 0xe1, ++ 0xa1, 0x61, 0x9d, 0x08, 0xc1, 0x44, 0x43, 0x1d, 0x14, 0xb2, 0x88, 0xd6, ++ 0x8d, 0x74, 0x8b, 0xfd, 0xfd, 0x56, 0xdc, 0xf8, 0x28, 0xf2, 0x32, 0x13, ++ 0xa3, 0x74, 0xe5, 0x57, 0x2d, 0x7b, 0xfe, 0xe7, 0x7e, 0x1f, 0x99, 0x0c, ++ 0xa1, 0xda, 0xee, 0x6e, 0xf2, 0xd3, 0x93, 0x73, 0x5f, 0xdf, 0xb9, 0xe7, ++ 0x7d, 0xcf, 0xbd, 0xd4, 0x14, 0xe7, 0x18, 0xbe, 0x9a, 0x22, 0x44, 0x6e, ++ 0xcc, 0x59, 0x73, 0x4f, 0x84, 0x10, 0xae, 0x95, 0x3d, 0x45, 0x89, 0xd9, ++ 0x42, 0xf4, 0xbd, 0xa9, 0x8a, 0x26, 0x87, 0x10, 0xc2, 0xed, 0x3d, 0x56, ++ 0x1f, 0x2b, 0x44, 0x6d, 0xc7, 0x70, 0xb1, 0x29, 0x99, 0xf0, 0x92, 0xbe, ++ 0xb7, 0x0c, 0xc0, 0xdb, 0xc6, 0xd9, 0x37, 0x51, 0xff, 0xc6, 0xf6, 0x3f, ++ 0xbc, 0x83, 0xfe, 0xde, 0x03, 0xaa, 0xc3, 0x42, 0xfd, 0xaf, 0xb7, 0x7f, ++ 0x1c, 0x85, 0x75, 0x2e, 0x7c, 0x15, 0x2e, 0xc4, 0x70, 0xcc, 0xfb, 0x38, ++ 0x4a, 0x10, 0x5e, 0x7d, 0x49, 0x61, 0x7c, 0x13, 0xf5, 0x3b, 0x08, 0x9f, ++ 0xd9, 0xaa, 0x0a, 0x7f, 0x26, 0xad, 0x67, 0xf4, 0x99, 0xd1, 0x7f, 0x21, ++ 0x55, 0xc7, 0xbd, 0x66, 0x41, 0xb0, 0xa4, 0xa5, 0xd5, 0xdc, 0x43, 0xb0, ++ 0x6a, 0x4f, 0x2b, 0xf7, 0xbf, 0xe9, 0x33, 0x0d, 0xee, 0xdf, 0xd3, 0x38, ++ 0xa8, 0xdf, 0x8e, 0xf1, 0x04, 0xab, 0x8c, 0xde, 0x28, 0x3b, 0xc1, 0x73, ++ 0xed, 0xfa, 0x7a, 0x7e, 0x1e, 0x5f, 0x9d, 0xaa, 0xb8, 0xbc, 0x68, 0xdf, ++ 0xf3, 0x87, 0xb8, 0xa5, 0x18, 0xd7, 0xf2, 0x6e, 0xdc, 0x12, 0x82, 0x97, ++ 0xf1, 0x33, 0xe3, 0x6a, 0xf8, 0xd9, 0xc1, 0x17, 0x32, 0xdd, 0x34, 0xaf, ++ 0xa6, 0x83, 0xd6, 0x89, 0x18, 0x58, 0xa7, 0xa6, 0xc3, 0xa4, 0xe1, 0x92, ++ 0xee, 0xea, 0xd4, 0xd6, 0xa2, 0x18, 0xe2, 0x97, 0x68, 0x51, 0x44, 0x1a, ++ 0x81, 0x0b, 0x62, 0x8b, 0x58, 0x45, 0xfc, 0xac, 0x6a, 0x6f, 0xae, 0x16, ++ 0xd4, 0x5e, 0x95, 0x71, 0xb7, 0x49, 0x10, 0x5f, 0x02, 0x3e, 0xb5, 0x18, ++ 0xdf, 0xa7, 0x1f, 0x83, 0x88, 0xa3, 0x79, 0x76, 0xfa, 0x8b, 0xf8, 0x77, ++ 0xc1, 0xf7, 0x45, 0xd4, 0x12, 0x5a, 0xf7, 0x35, 0xdf, 0xd1, 0xdb, 0x5c, ++ 0x04, 0x03, 0x9d, 0x6f, 0x44, 0xe1, 0xbb, 0x81, 0x03, 0x34, 0x3e, 0x73, ++ 0x80, 0x9e, 0xe9, 0x2e, 0xe2, 0x5f, 0x0e, 0xa0, 0x59, 0x88, 0x11, 0x34, ++ 0xef, 0xc0, 0x1b, 0x51, 0x0e, 0xea, 0xdf, 0xe8, 0x7b, 0x43, 0xf2, 0xdb, ++ 0xe8, 0xe7, 0x7d, 0xbf, 0xae, 0xe1, 0x01, 0x82, 0xcc, 0xe7, 0x76, 0x95, ++ 0xf7, 0x5d, 0xf1, 0x95, 0xca, 0xfc, 0xd7, 0xd7, 0xbb, 0xc5, 0xa5, 0xf2, ++ 0x3a, 0x33, 0xdb, 0xd3, 0x22, 0xb1, 0xaf, 0x13, 0x3e, 0xf9, 0xbd, 0x39, ++ 0x2e, 0x87, 0x6c, 0x4f, 0x5d, 0x54, 0x06, 0xfa, 0x8f, 0x27, 0xcc, 0xcf, ++ 0x51, 0x93, 0x99, 0x6e, 0x17, 0xf0, 0xc0, 0xc4, 0xd9, 0xcd, 0x9b, 0x88, ++ 0x94, 0x2a, 0x1f, 0xad, 0x9b, 0x79, 0x35, 0xdf, 0x96, 0x68, 0xeb, 0x76, ++ 0x99, 0xc4, 0x3c, 0x1f, 0xe4, 0x96, 0xba, 0xbf, 0x6b, 0x14, 0xe9, 0xc7, ++ 0xf1, 0xe2, 0xe1, 0x93, 0xa9, 0xe7, 0xca, 0xb8, 0xbb, 0x5d, 0x06, 0x1e, ++ 0x57, 0x64, 0x76, 0xa7, 0x2e, 0xa7, 0x71, 0x27, 0x22, 0x1c, 0x91, 0x76, ++ 0x5a, 0xef, 0xc1, 0xe2, 0x71, 0x91, 0x90, 0xeb, 0xeb, 0x80, 0x68, 0x2f, ++ 0xde, 0x69, 0x76, 0x13, 0xac, 0x3c, 0x20, 0xbf, 0x77, 0xc2, 0xde, 0x1d, ++ 0x05, 0x7d, 0x3b, 0x71, 0x60, 0xaa, 0xea, 0x51, 0x06, 0xd6, 0xbb, 0x43, ++ 0xfb, 0xae, 0x10, 0x1e, 0x86, 0x03, 0x72, 0xf3, 0xb0, 0x9c, 0xca, 0xbd, ++ 0x8d, 0x11, 0x58, 0x67, 0x40, 0x7e, 0xb2, 0x7d, 0x8e, 0xcb, 0xce, 0xe3, ++ 0x8f, 0x7b, 0xdf, 0xbd, 0xf3, 0x6e, 0xda, 0xdf, 0x89, 0x8c, 0x70, 0x27, ++ 0xe4, 0xd2, 0x65, 0x16, 0xe5, 0x3e, 0xd6, 0x13, 0xfa, 0x08, 0xbe, 0xd7, ++ 0x99, 0xd8, 0x08, 0x3e, 0xe8, 0xdf, 0x9b, 0x03, 0x79, 0xd0, 0xbc, 0x40, ++ 0x86, 0x81, 0xe5, 0xda, 0xdb, 0x6e, 0xd2, 0xc6, 0xdd, 0xdd, 0x2c, 0x06, ++ 0x8d, 0x33, 0xb1, 0xdc, 0x2e, 0x3c, 0x37, 0x98, 0x1e, 0xbb, 0xf7, 0xc3, ++ 0x5f, 0xdd, 0x4d, 0xe3, 0xab, 0x9f, 0x51, 0x85, 0x85, 0x9a, 0xab, 0x4d, ++ 0xcb, 0xe3, 0xb0, 0xff, 0x4f, 0xb7, 0x0f, 0xa6, 0xaf, 0x5c, 0xe3, 0x73, ++ 0xb5, 0xc9, 0x1f, 0x17, 0x17, 0xa4, 0xaf, 0xd5, 0x1d, 0x57, 0xec, 0x25, ++ 0x82, 0xf5, 0xbb, 0x43, 0xb7, 0x0f, 0x07, 0xcb, 0x53, 0x97, 0xe3, 0x89, ++ 0x0c, 0x55, 0xd2, 0x95, 0x60, 0xf1, 0x0a, 0x22, 0xb9, 0xba, 0xb5, 0x99, ++ 0xf5, 0x9a, 0xcc, 0xcd, 0x63, 0x9b, 0xc2, 0x50, 0xd8, 0x09, 0x26, 0x86, ++ 0x77, 0x27, 0x2b, 0xb4, 0xff, 0xc4, 0xfb, 0xad, 0xce, 0xb5, 0x44, 0xff, ++ 0x73, 0x8a, 0xd6, 0x6f, 0x20, 0x18, 0x43, 0xb8, 0x41, 0xe2, 0x66, 0x82, ++ 0x56, 0x82, 0xcf, 0x98, 0x64, 0x3b, 0xcc, 0x16, 0xf3, 0xc7, 0x90, 0x38, ++ 0x15, 0xc2, 0x4d, 0xc5, 0xe3, 0x72, 0x0c, 0x29, 0xb4, 0x8e, 0xda, 0x3a, ++ 0x19, 0x72, 0x7d, 0x71, 0x86, 0xeb, 0x51, 0x17, 0xed, 0xff, 0x97, 0x33, ++ 0x4a, 0x26, 0xcd, 0x20, 0x78, 0x42, 0xf4, 0x2d, 0x15, 0xf4, 0xcd, 0x9a, ++ 0x8b, 0x11, 0x1e, 0x11, 0x2d, 0x44, 0xa1, 0xfa, 0xfe, 0x13, 0xf8, 0x6e, ++ 0xff, 0x01, 0x93, 0x80, 0xff, 0xa8, 0xb1, 0x76, 0x54, 0x7e, 0x42, 0x7a, ++ 0xda, 0xef, 0x24, 0x43, 0x21, 0xba, 0xfb, 0xb7, 0x9b, 0xbc, 0x1e, 0xd6, ++ 0x3f, 0x57, 0x84, 0x32, 0x4d, 0x88, 0xa5, 0x37, 0x48, 0xbb, 0xf9, 0xd4, ++ 0xe1, 0x9e, 0xa6, 0x8e, 0xa3, 0xf1, 0x6b, 0x0c, 0xbc, 0xbf, 0xea, 0x16, ++ 0xd5, 0x6b, 0xa3, 0x71, 0xbd, 0xf5, 0xc4, 0x02, 0x62, 0xf9, 0x67, 0xad, ++ 0xc9, 0x3f, 0x82, 0xbe, 0x56, 0x1f, 0x53, 0xed, 0x56, 0xda, 0x77, 0xbe, ++ 0x2f, 0xf9, 0xd7, 0xd3, 0x81, 0xb7, 0x98, 0x9c, 0x16, 0x9a, 0x5f, 0xeb, ++ 0xa3, 0x46, 0xc2, 0x6b, 0xf7, 0x28, 0x5e, 0x87, 0x5c, 0x5f, 0xc0, 0x2e, ++ 0x6b, 0x6e, 0x60, 0x5d, 0x17, 0xa7, 0x6d, 0xb5, 0x29, 0x22, 0x8b, 0xe0, ++ 0x9a, 0x3e, 0x33, 0xc6, 0x9d, 0x3e, 0xa4, 0x88, 0xc7, 0x68, 0xdc, 0x23, ++ 0x61, 0x51, 0x4d, 0xa0, 0xbb, 0x26, 0x73, 0xd6, 0x59, 0x25, 0x8a, 0xa0, ++ 0xba, 0x79, 0x7d, 0x22, 0xad, 0xb7, 0x6c, 0x9b, 0xe9, 0xa3, 0x1e, 0xab, ++ 0x9c, 0x7b, 0x99, 0xfe, 0xab, 0xeb, 0xdc, 0xca, 0x7a, 0x5b, 0xe1, 0x1d, ++ 0xdc, 0x5e, 0xb5, 0x67, 0x30, 0x5e, 0x23, 0x8c, 0x03, 0x38, 0xad, 0xdf, ++ 0x8c, 0x3f, 0x6e, 0x14, 0xa2, 0xcd, 0x15, 0x19, 0x7b, 0xfa, 0x3a, 0xfa, ++ 0x7b, 0x82, 0x98, 0x70, 0x59, 0x05, 0x9f, 0xa6, 0xc7, 0xc3, 0x1e, 0x8e, ++ 0x43, 0xae, 0xc4, 0x47, 0xd1, 0x40, 0xcc, 0x1e, 0x29, 0xc4, 0xbd, 0x93, ++ 0x9c, 0xf1, 0xb0, 0xfb, 0x8d, 0x46, 0xc7, 0x2c, 0xf0, 0x21, 0xd0, 0x69, ++ 0xb2, 0x83, 0x5f, 0x75, 0x87, 0xf6, 0x57, 0x80, 0x6e, 0x6f, 0x75, 0x98, ++ 0xd3, 0x40, 0x5b, 0xad, 0x5d, 0xf5, 0x2a, 0xf3, 0x35, 0xf0, 0x25, 0xf1, ++ 0xfd, 0x7a, 0x82, 0x09, 0x82, 0xf7, 0x1f, 0x10, 0x92, 0xbf, 0x81, 0x76, ++ 0xa9, 0xe7, 0x75, 0x26, 0xc5, 0x6b, 0xc5, 0x7c, 0xe2, 0x21, 0xaf, 0x67, ++ 0x55, 0xbc, 0x6b, 0xa8, 0x2b, 0xe0, 0xe9, 0x8f, 0x62, 0xff, 0x24, 0x44, ++ 0x31, 0xec, 0x62, 0xe5, 0xfc, 0x1c, 0x03, 0xfc, 0x1c, 0xcc, 0x58, 0x10, ++ 0x29, 0xbf, 0xd6, 0xed, 0x41, 0xb1, 0x19, 0x95, 0x68, 0x40, 0x69, 0xff, ++ 0x3f, 0x30, 0xf6, 0xa8, 0xc3, 0x82, 0xfc, 0xc4, 0x7f, 0xb9, 0x52, 0x98, ++ 0xfe, 0x02, 0xb3, 0x70, 0xfb, 0xa8, 0xfd, 0xde, 0x48, 0x67, 0x34, 0xf4, ++ 0x7e, 0xac, 0x35, 0x2a, 0x0b, 0x74, 0x8d, 0xb5, 0x26, 0x79, 0xc1, 0xf7, ++ 0xb1, 0xc6, 0xbe, 0x35, 0xf8, 0xfe, 0x23, 0xa3, 0x14, 0xc7, 0x83, 0xb4, ++ 0xf4, 0xe1, 0xac, 0x57, 0x26, 0x2b, 0xc0, 0x6b, 0x23, 0x9c, 0xd0, 0x13, ++ 0x25, 0x61, 0x91, 0x11, 0xfc, 0x78, 0x64, 0xd4, 0x22, 0x23, 0xf4, 0x7d, ++ 0xac, 0xdd, 0x97, 0x51, 0x92, 0x39, 0x80, 0x17, 0xa0, 0x1f, 0xf6, 0x20, ++ 0xbc, 0xfc, 0xbd, 0xa2, 0x08, 0xb7, 0x11, 0xdf, 0x79, 0x6e, 0xa4, 0xe2, ++ 0x37, 0xd0, 0xfa, 0x01, 0x1b, 0xd1, 0x07, 0x3b, 0x31, 0xda, 0x4d, 0xa0, ++ 0x2f, 0x60, 0x92, 0xb8, 0x10, 0x6b, 0x06, 0xd1, 0x47, 0x1e, 0x89, 0xf1, ++ 0xff, 0x77, 0xfa, 0xec, 0x44, 0x5f, 0xc4, 0x00, 0x7d, 0x24, 0xef, 0x68, ++ 0xcc, 0xff, 0x22, 0x9b, 0xf8, 0x43, 0x30, 0x69, 0x8e, 0x10, 0xdd, 0xec, ++ 0x17, 0x96, 0xb3, 0x5f, 0xd0, 0xf9, 0x79, 0x81, 0xf4, 0xbd, 0x80, 0x64, ++ 0x95, 0xa6, 0x48, 0xbd, 0xa9, 0xde, 0x7e, 0xb8, 0x08, 0xfd, 0x35, 0xa2, ++ 0x7b, 0x3d, 0xe6, 0x15, 0x45, 0xc9, 0x7d, 0x14, 0x61, 0x3f, 0xc0, 0xc3, ++ 0x24, 0x54, 0x73, 0xa5, 0xbc, 0x72, 0x35, 0x78, 0x5f, 0xae, 0x8c, 0x2f, ++ 0xba, 0xff, 0xec, 0xc8, 0x75, 0x19, 0x73, 0x09, 0x6e, 0xcb, 0x2d, 0x31, ++ 0x03, 0x16, 0xaa, 0x99, 0xf1, 0x3d, 0x43, 0xf8, 0xfb, 0x95, 0x8a, 0x95, ++ 0xf5, 0xe4, 0x0b, 0xb2, 0x3f, 0xf8, 0xe3, 0x7b, 0x96, 0x2b, 0xf6, 0xd4, ++ 0x8c, 0x01, 0xfd, 0xd6, 0xed, 0xaa, 0x4e, 0x36, 0x5d, 0xb1, 0x9f, 0xaa, ++ 0xdf, 0xef, 0x34, 0x8b, 0x14, 0x7c, 0xce, 0xd5, 0x9d, 0x41, 0xfd, 0xe5, ++ 0x42, 0xda, 0xf5, 0xc2, 0x55, 0x36, 0x7b, 0x6a, 0xb0, 0x1d, 0xc1, 0xce, ++ 0x88, 0x1f, 0xe5, 0xf6, 0x8a, 0x5b, 0x05, 0xd9, 0x9b, 0x7b, 0x55, 0x9c, ++ 0x3d, 0x75, 0x2a, 0xb5, 0xab, 0x17, 0xcc, 0x02, 0xba, 0xa7, 0xd9, 0x57, ++ 0x2c, 0xfd, 0x5e, 0x4e, 0x19, 0xc2, 0xbe, 0x7c, 0x21, 0x76, 0xd9, 0x3e, ++ 0x18, 0xf7, 0xdb, 0xa4, 0x9e, 0xfb, 0x23, 0x15, 0xef, 0x5a, 0xa2, 0x3f, ++ 0x35, 0x77, 0xb0, 0xdd, 0x25, 0x69, 0x76, 0xd0, 0xe8, 0x56, 0x78, 0x7f, ++ 0x8d, 0x5f, 0x1b, 0x19, 0xf7, 0x94, 0x2a, 0x5e, 0xf0, 0xfc, 0x0e, 0x6a, ++ 0x5c, 0x15, 0xa3, 0x6d, 0x0e, 0xe3, 0xca, 0x73, 0xbd, 0x88, 0x8f, 0x77, ++ 0x10, 0x5a, 0x8a, 0xf6, 0x86, 0x58, 0xb6, 0x53, 0xee, 0x24, 0xff, 0xf5, ++ 0x2f, 0xda, 0x3e, 0xef, 0x30, 0xfa, 0x0f, 0xc3, 0x7f, 0x1c, 0x35, 0xf9, ++ 0x92, 0xed, 0xd4, 0x75, 0xb4, 0xc6, 0xea, 0xc4, 0xfa, 0xf3, 0x05, 0x25, ++ 0x3a, 0xe4, 0xd7, 0x4a, 0x45, 0x37, 0xc3, 0x93, 0xe1, 0xb5, 0x6d, 0x7e, ++ 0x5e, 0xdc, 0x33, 0x06, 0xfa, 0xf5, 0x9e, 0xdb, 0xe2, 0x44, 0x1e, 0xd6, ++ 0xb8, 0xae, 0x29, 0x12, 0x7e, 0x3c, 0x4b, 0xac, 0xb3, 0x9f, 0xce, 0x40, ++ 0x52, 0x21, 0xf6, 0x5c, 0x9e, 0x7a, 0xed, 0x7c, 0x86, 0x14, 0x47, 0x9c, ++ 0xd6, 0xe5, 0x82, 0x40, 0x4c, 0x79, 0x0a, 0xe4, 0xad, 0xcb, 0x75, 0x5b, ++ 0xae, 0x2b, 0x2f, 0x37, 0xe7, 0xda, 0xf3, 0xab, 0xfe, 0xd8, 0x76, 0xdb, ++ 0xf7, 0xe0, 0xbf, 0xee, 0x6b, 0x36, 0xc7, 0x4b, 0x35, 0xe9, 0xce, 0x98, ++ 0x36, 0x20, 0x37, 0x5d, 0xae, 0x75, 0xc2, 0xc3, 0x74, 0xeb, 0xf2, 0xba, ++ 0x22, 0x3f, 0xa2, 0x7d, 0x34, 0xf8, 0xa1, 0x5e, 0x98, 0xc3, 0x7e, 0xe6, ++ 0x59, 0x55, 0x70, 0x5e, 0xa1, 0xc9, 0xcf, 0x4a, 0xbf, 0x43, 0xc9, 0x4f, ++ 0xe7, 0xef, 0x0c, 0x4d, 0x0e, 0xcb, 0x3a, 0xa4, 0x3f, 0x0a, 0x95, 0xab, ++ 0xce, 0xef, 0x1f, 0xd3, 0x82, 0xf8, 0x3e, 0xc5, 0xd1, 0xed, 0x2c, 0x0f, ++ 0x61, 0x61, 0xff, 0x17, 0x2a, 0xf7, 0x6f, 0x93, 0x0b, 0x65, 0x98, 0xa5, ++ 0xe8, 0xca, 0x8f, 0xb5, 0x08, 0xc8, 0x33, 0xd1, 0x20, 0xfd, 0x63, 0xe2, ++ 0x52, 0xd2, 0x13, 0xa2, 0xfb, 0x6e, 0xe1, 0x3e, 0xd4, 0x43, 0xf0, 0xce, ++ 0xf0, 0xb7, 0x4d, 0xac, 0x87, 0x9a, 0x7c, 0xee, 0x81, 0x7c, 0x68, 0xe8, ++ 0x7b, 0xc2, 0xfb, 0xc3, 0x8c, 0xe4, 0xff, 0x3b, 0xf9, 0x74, 0xe4, 0x96, ++ 0xdc, 0x1f, 0x6c, 0x87, 0xa1, 0x76, 0x77, 0x2d, 0x3b, 0xab, 0x76, 0x38, ++ 0xff, 0x5d, 0x8f, 0x7b, 0xe4, 0x69, 0xc8, 0xbe, 0x42, 0xec, 0x33, 0xc4, ++ 0xfe, 0x74, 0x79, 0xb9, 0x57, 0x45, 0xb1, 0x9d, 0x5d, 0x91, 0xa3, 0xda, ++ 0x22, 0xed, 0x55, 0x93, 0x57, 0x04, 0xfd, 0x0e, 0x69, 0x6f, 0xf8, 0x83, ++ 0xbe, 0x57, 0xd3, 0xae, 0x78, 0xfd, 0xc9, 0xdf, 0xc1, 0xfe, 0x14, 0x22, ++ 0x9c, 0xe4, 0xf6, 0x58, 0x88, 0xdd, 0xe9, 0xf2, 0xb9, 0x96, 0xdf, 0xd1, ++ 0xfd, 0xd4, 0x29, 0xe1, 0x3f, 0x6a, 0xa7, 0xfd, 0x9f, 0x4c, 0x91, 0x79, ++ 0x80, 0xe7, 0x67, 0x16, 0x6f, 0x33, 0xf0, 0x74, 0x43, 0x39, 0xfc, 0xde, ++ 0xc9, 0x89, 0x12, 0xee, 0xd7, 0xfc, 0x5b, 0x28, 0x3c, 0x45, 0x79, 0x8e, ++ 0x42, 0x71, 0x6c, 0x53, 0xc6, 0x89, 0x11, 0x88, 0xd7, 0x27, 0xcd, 0xfa, ++ 0x3a, 0x36, 0x6f, 0x33, 0xd1, 0x7f, 0x6a, 0x4d, 0xf7, 0x98, 0x15, 0x34, ++ 0xff, 0x54, 0xae, 0x84, 0x27, 0x91, 0x17, 0x06, 0xe1, 0xae, 0x30, 0xb1, ++ 0x10, 0x7e, 0xfd, 0xd4, 0x48, 0x8b, 0x07, 0x7c, 0x3a, 0xa5, 0x4c, 0xc8, ++ 0x43, 0x7c, 0x38, 0xa5, 0xdc, 0x7f, 0x9b, 0xc4, 0xe3, 0xcd, 0x0e, 0xe0, ++ 0xf3, 0xe3, 0xf3, 0xec, 0x84, 0x9f, 0x34, 0xc9, 0xf1, 0x7a, 0x5c, 0xd1, ++ 0xfd, 0xff, 0xa9, 0xf9, 0xdf, 0x2b, 0xe0, 0x71, 0x8a, 0x38, 0x02, 0x7e, ++ 0x38, 0x14, 0x51, 0xc2, 0xdf, 0x51, 0x94, 0x98, 0x62, 0xa2, 0xe7, 0xd4, ++ 0x7d, 0x69, 0x53, 0xd6, 0x8a, 0x81, 0xfd, 0x37, 0xe5, 0x1a, 0x78, 0x9e, ++ 0x57, 0xf3, 0xdf, 0x44, 0x07, 0xf3, 0xbd, 0xef, 0xe7, 0x8a, 0xb7, 0x89, ++ 0x9a, 0x16, 0x22, 0xa4, 0x10, 0xfd, 0xc9, 0x79, 0xbf, 0x2d, 0x4e, 0xa1, ++ 0xf6, 0x0f, 0x7e, 0x31, 0x6e, 0x32, 0xe4, 0xeb, 0x5a, 0x39, 0xf8, 0xfb, ++ 0x88, 0xd7, 0xc9, 0xd7, 0x03, 0xdf, 0xca, 0xeb, 0xfc, 0xe0, 0xab, 0x3e, ++ 0xd3, 0xa2, 0xa0, 0xb8, 0x74, 0x25, 0x4e, 0x16, 0x7c, 0x2e, 0xdb, 0xcb, ++ 0x72, 0x0c, 0xb0, 0x97, 0x72, 0x4d, 0x86, 0xae, 0x98, 0x09, 0xd1, 0x90, ++ 0x4f, 0xbf, 0x77, 0x5c, 0x34, 0xe2, 0x8e, 0x1e, 0x87, 0xfa, 0x8f, 0xed, ++ 0x8f, 0x70, 0x07, 0xc9, 0xed, 0x2c, 0xc5, 0x29, 0x31, 0x3e, 0x08, 0x9f, ++ 0xf0, 0x68, 0x52, 0x70, 0x1c, 0x3b, 0xbc, 0xeb, 0x91, 0x74, 0xac, 0x53, ++ 0x6e, 0xf6, 0x64, 0x39, 0xa9, 0xfd, 0x4c, 0xe3, 0xd3, 0x49, 0xc8, 0x37, ++ 0xca, 0x77, 0x3d, 0x9c, 0xce, 0x79, 0xf0, 0xae, 0x8d, 0xe9, 0x38, 0xcf, ++ 0x94, 0x37, 0x3d, 0x92, 0xee, 0x62, 0x3c, 0xdc, 0xcd, 0xe7, 0x29, 0xa3, ++ 0xdc, 0xf7, 0xf9, 0x7d, 0x37, 0xee, 0xdc, 0x14, 0x94, 0x77, 0x57, 0xe5, ++ 0xab, 0x4c, 0x7f, 0xa9, 0xf5, 0x70, 0x21, 0xe2, 0xed, 0xac, 0xeb, 0x3e, ++ 0x7b, 0xc8, 0x4e, 0xe3, 0xd2, 0x7e, 0xa1, 0xd8, 0xa1, 0x5e, 0xf7, 0x88, ++ 0xee, 0x87, 0x10, 0x1f, 0x17, 0x20, 0x3f, 0xc6, 0xf9, 0xad, 0xc1, 0xca, ++ 0xfe, 0x9c, 0xd6, 0x73, 0x41, 0xfe, 0xcd, 0x13, 0x7e, 0xf8, 0x1c, 0xec, ++ 0xf8, 0x78, 0xc6, 0xc7, 0xa6, 0x32, 0x1a, 0x77, 0x29, 0xd7, 0xc8, 0xfc, ++ 0x59, 0x20, 0xbc, 0x9b, 0xe3, 0xa9, 0x5f, 0x6c, 0x50, 0xec, 0xcd, 0x22, ++ 0x78, 0xfc, 0x98, 0x46, 0x8c, 0x5f, 0xb4, 0x4e, 0x31, 0x27, 0xc0, 0x0f, ++ 0x2c, 0x1f, 0x36, 0x59, 0x75, 0x60, 0xde, 0x30, 0xa6, 0x63, 0xf1, 0x86, ++ 0xc9, 0x5d, 0x68, 0x5f, 0xb0, 0x5a, 0xb6, 0xcf, 0xb2, 0x78, 0x0f, 0x9c, ++ 0xc0, 0x3a, 0xbf, 0x35, 0x3b, 0x9b, 0x1d, 0xec, 0x6f, 0x52, 0x4a, 0x26, ++ 0x0d, 0xd0, 0x7f, 0x29, 0xd7, 0xcc, 0xf3, 0x16, 0x6e, 0x56, 0x38, 0xff, ++ 0xd7, 0xbf, 0x93, 0xf6, 0x44, 0x5c, 0x63, 0xf0, 0x3e, 0x2f, 0x69, 0xf2, ++ 0x17, 0x5f, 0x5b, 0x14, 0xc8, 0xe5, 0x47, 0x9a, 0x5c, 0x6e, 0x5d, 0xfd, ++ 0xee, 0x91, 0x04, 0x5a, 0xd7, 0x1e, 0xeb, 0xbe, 0x0c, 0xbf, 0xf1, 0xce, ++ 0xe3, 0xa7, 0x53, 0xfd, 0xd4, 0x5e, 0x10, 0x73, 0x36, 0x13, 0x7a, 0x9e, ++ 0x66, 0x76, 0x3f, 0x55, 0x81, 0x7d, 0x37, 0x59, 0x9c, 0xd8, 0x47, 0x76, ++ 0x56, 0xa2, 0x1a, 0x4f, 0xe3, 0xa7, 0xfc, 0x34, 0xf7, 0x31, 0xc0, 0x85, ++ 0xab, 0x17, 0x3d, 0x55, 0x01, 0x7f, 0xbb, 0xcd, 0xca, 0xe7, 0x36, 0x9d, ++ 0xbe, 0x95, 0x8a, 0xd3, 0x00, 0x7f, 0xfc, 0x46, 0xe3, 0x8f, 0x17, 0x83, ++ 0x6f, 0x67, 0x1e, 0xb7, 0x72, 0xde, 0xbe, 0xb2, 0x71, 0x7c, 0xbc, 0x18, ++ 0xc2, 0x4e, 0x75, 0xb8, 0x9b, 0xe4, 0xef, 0xa0, 0x83, 0xce, 0xde, 0x7a, ++ 0x2b, 0xc3, 0x17, 0xea, 0xed, 0xc2, 0x41, 0xfa, 0xb0, 0xaf, 0x3e, 0x81, ++ 0xf1, 0x17, 0xeb, 0x1d, 0x0c, 0xc5, 0x3c, 0xa9, 0x5f, 0x2b, 0xb5, 0xf3, ++ 0xf1, 0xb5, 0xd6, 0x9b, 0xfa, 0x55, 0xb8, 0x70, 0x50, 0x3e, 0x9b, 0xbd, ++ 0xc1, 0x26, 0x1c, 0xe4, 0xa7, 0x92, 0xe2, 0x5c, 0xa3, 0xf2, 0x68, 0x9f, ++ 0x69, 0x13, 0x6b, 0x9a, 0x36, 0x6a, 0xfb, 0x4a, 0xa3, 0xf9, 0x93, 0x3d, ++ 0xc9, 0xf9, 0xe0, 0x43, 0xf6, 0xc6, 0x15, 0x5d, 0x48, 0x79, 0xcd, 0x79, ++ 0xf2, 0x3c, 0xf6, 0xd6, 0x89, 0x0d, 0x49, 0x70, 0xca, 0xcb, 0x56, 0x7f, ++ 0xb8, 0xa3, 0x82, 0xfa, 0xe7, 0xe4, 0x95, 0x8c, 0xcb, 0xa3, 0x76, 0xeb, ++ 0xf6, 0xcf, 0xb9, 0xae, 0xf0, 0x46, 0xc7, 0xc3, 0x0b, 0xc0, 0xef, 0xf2, ++ 0x26, 0x8b, 0xdc, 0x9f, 0xb6, 0xef, 0x33, 0x8f, 0xa7, 0xc7, 0x3f, 0x45, ++ 0xeb, 0x7b, 0xde, 0x34, 0xf1, 0x79, 0xbf, 0x6e, 0xfb, 0x87, 0x3b, 0x36, ++ 0x12, 0x5c, 0xb2, 0x79, 0x85, 0x39, 0x58, 0xdf, 0xbf, 0xeb, 0x7e, 0x93, ++ 0x35, 0x7a, 0xbe, 0xcd, 0xae, 0xae, 0xc5, 0x87, 0x7f, 0xdc, 0xae, 0x1e, ++ 0x49, 0x62, 0xfb, 0x69, 0x22, 0xbb, 0xca, 0xfc, 0xe7, 0xed, 0xaa, 0x6e, ++ 0xf5, 0x1a, 0xe6, 0xdf, 0xfd, 0x79, 0x25, 0xb3, 0xc0, 0xf7, 0x33, 0x26, ++ 0x4f, 0x12, 0xec, 0xe9, 0xcc, 0x84, 0x9b, 0x59, 0xcf, 0x3d, 0x87, 0x14, ++ 0xe6, 0xbf, 0xee, 0xc7, 0xf5, 0xf9, 0xc5, 0xda, 0x7e, 0xab, 0x0c, 0xbe, ++ 0xcd, 0xd3, 0x93, 0x07, 0xfc, 0xf8, 0x45, 0x91, 0xcd, 0xfc, 0x3d, 0xdc, ++ 0xf1, 0x69, 0x3a, 0xf2, 0xde, 0x8b, 0xed, 0xf3, 0xff, 0xee, 0xbe, 0x0f, ++ 0xd2, 0xbe, 0xfd, 0xb4, 0xef, 0x76, 0xe2, 0xaf, 0x7f, 0xfc, 0xd5, 0xfd, ++ 0xd3, 0xcc, 0xee, 0x71, 0x4e, 0xda, 0xdf, 0x34, 0x83, 0xcc, 0x77, 0xaf, ++ 0xca, 0x5b, 0xf3, 0x0c, 0x5a, 0xbd, 0xa0, 0xdb, 0x5c, 0x12, 0x29, 0x79, ++ 0xae, 0xa0, 0x2e, 0xa3, 0xc5, 0x4f, 0x8a, 0x63, 0x9e, 0x68, 0xa2, 0xa7, ++ 0xba, 0x53, 0xf1, 0x87, 0x65, 0x21, 0x9e, 0xdd, 0x72, 0xd6, 0x88, 0xf3, ++ 0x1e, 0x9d, 0x1b, 0x3f, 0x0a, 0xce, 0x23, 0xe8, 0xe7, 0xa3, 0xa0, 0xb8, ++ 0x7d, 0x2d, 0x7a, 0xbf, 0x0d, 0xd6, 0x62, 0x9d, 0xb4, 0x01, 0xbf, 0xfb, ++ 0xbd, 0x3f, 0x19, 0x84, 0x3f, 0x28, 0x4e, 0xdf, 0xd8, 0x13, 0x26, 0xfc, ++ 0x41, 0xdf, 0xbd, 0x72, 0x3e, 0xa1, 0x36, 0x33, 0xc9, 0xa9, 0xb7, 0x63, ++ 0x24, 0xfb, 0x05, 0xc8, 0xcd, 0x88, 0x7a, 0x5c, 0xc7, 0x84, 0x26, 0xe0, ++ 0x67, 0xcd, 0x52, 0x8e, 0xbd, 0x07, 0x29, 0x6f, 0x92, 0x75, 0x1c, 0xa1, ++ 0x4e, 0x1b, 0xd8, 0xe7, 0xd9, 0x8e, 0xf3, 0x59, 0xf0, 0xb3, 0xa1, 0xfb, ++ 0xad, 0x7d, 0xe5, 0x3c, 0xeb, 0x47, 0x75, 0xfb, 0xc3, 0x9f, 0x2b, 0xbc, ++ 0xff, 0x99, 0x67, 0x8d, 0x59, 0xdf, 0xbe, 0xff, 0xc3, 0xbb, 0xce, 0x67, ++ 0x41, 0x7e, 0x67, 0x4d, 0x3d, 0xd3, 0x70, 0xde, 0xea, 0x35, 0xf7, 0x64, ++ 0x41, 0x0e, 0xb5, 0xaf, 0x4a, 0x7f, 0xfe, 0x8f, 0xf2, 0x41, 0x6f, 0xaf, ++ 0xd8, 0x40, 0x1b, 0x21, 0x3b, 0xaf, 0x55, 0xac, 0xac, 0x27, 0x85, 0xea, ++ 0x05, 0xae, 0x1b, 0xf4, 0x1e, 0x93, 0x75, 0x83, 0xda, 0x8e, 0x9d, 0xec, ++ 0x4f, 0xfb, 0x3b, 0x65, 0xfd, 0xa6, 0xce, 0xd0, 0x5d, 0x14, 0x8f, 0x7a, ++ 0xc7, 0xf2, 0x0f, 0xbb, 0xe0, 0xcf, 0xfa, 0x13, 0xe4, 0x39, 0x8a, 0xd6, ++ 0x77, 0x81, 0x6f, 0xd3, 0xc7, 0x69, 0x71, 0xd0, 0xd8, 0x97, 0x34, 0x87, ++ 0xfc, 0xda, 0x4b, 0x57, 0xf4, 0x41, 0x9e, 0xff, 0xce, 0xc0, 0x7e, 0xc7, ++ 0x63, 0x1d, 0x5f, 0x35, 0xfc, 0x80, 0xc8, 0x0a, 0x17, 0xc8, 0x2b, 0xce, ++ 0xc1, 0x9e, 0xa9, 0x7d, 0xc1, 0xaa, 0xe4, 0xf5, 0xd0, 0xf3, 0x33, 0xde, ++ 0x11, 0x53, 0xe0, 0x1f, 0xdf, 0xca, 0xfa, 0x6b, 0x2d, 0xd7, 0xfb, 0x5e, ++ 0x0b, 0xb7, 0xab, 0x9c, 0xf7, 0x50, 0x6b, 0x90, 0xfc, 0xae, 0xec, 0xc3, ++ 0xab, 0x0a, 0xd7, 0xa0, 0x7a, 0x40, 0xb8, 0x70, 0x05, 0x8d, 0xab, 0x33, ++ 0x3b, 0x7e, 0xc4, 0xf9, 0xf1, 0x71, 0x55, 0x20, 0xaf, 0xab, 0x9b, 0x28, ++ 0xed, 0x49, 0xbc, 0x22, 0xed, 0xa9, 0x66, 0xdd, 0x61, 0x73, 0x42, 0xd0, ++ 0x7a, 0x3b, 0x60, 0x4f, 0x4c, 0xb7, 0xcc, 0x17, 0x67, 0xbd, 0xf6, 0x57, ++ 0xb6, 0xcb, 0xd5, 0x33, 0x5c, 0x9d, 0xb0, 0xcb, 0x70, 0xf8, 0x42, 0xac, ++ 0x97, 0x10, 0xed, 0x55, 0x14, 0x6d, 0x1c, 0xc9, 0xbf, 0x56, 0xa3, 0x21, ++ 0xa2, 0x53, 0x3b, 0xf7, 0x17, 0xab, 0xdc, 0x5f, 0xd7, 0xae, 0x8a, 0x91, ++ 0x98, 0x93, 0x10, 0xe9, 0x4d, 0xa3, 0x7d, 0x14, 0x8b, 0x2d, 0x46, 0xe4, ++ 0xd3, 0xb3, 0x84, 0x6f, 0x3a, 0xea, 0x36, 0xc2, 0xd8, 0xf3, 0xab, 0x9b, ++ 0xa8, 0x7f, 0xf6, 0x6b, 0xea, 0xd4, 0x4d, 0x82, 0xcf, 0x4f, 0x0b, 0x4b, ++ 0xf8, 0x5c, 0xe9, 0x4e, 0x5d, 0x89, 0xfc, 0xc8, 0xa0, 0x68, 0x7c, 0xf5, ++ 0x65, 0xcf, 0x09, 0x8e, 0x67, 0x79, 0x32, 0x4e, 0x4d, 0x57, 0x15, 0x8e, ++ 0x63, 0x7d, 0x23, 0xc3, 0x39, 0x4f, 0x99, 0x39, 0xaf, 0xa6, 0x14, 0xf4, ++ 0xea, 0xe3, 0xb2, 0x86, 0xc9, 0x71, 0xb4, 0x0e, 0xe7, 0x59, 0xc2, 0xdb, ++ 0x97, 0x35, 0x07, 0xf6, 0xe9, 0xef, 0xcb, 0x9a, 0x1b, 0x39, 0x30, 0xee, ++ 0xce, 0xd7, 0xc2, 0x97, 0x73, 0x5c, 0x14, 0xbe, 0xec, 0x3b, 0x83, 0xbe, ++ 0x13, 0x96, 0x2f, 0xeb, 0xa3, 0x5f, 0x50, 0x1c, 0x81, 0x9e, 0xd4, 0x5d, ++ 0x94, 0xf5, 0x8e, 0x42, 0xf5, 0xeb, 0x27, 0x90, 0x9f, 0xaf, 0x3c, 0x44, ++ 0xfa, 0x82, 0xfc, 0xd0, 0x90, 0xfc, 0x9e, 0x01, 0x7e, 0x9c, 0xf8, 0x0c, ++ 0xb9, 0x9e, 0x27, 0xb9, 0xba, 0x10, 0x7f, 0xdc, 0xc2, 0xe5, 0x82, 0xfd, ++ 0x4c, 0x1a, 0xe1, 0x85, 0xfd, 0xd4, 0xed, 0x53, 0x84, 0x11, 0x75, 0xa2, ++ 0x0e, 0x4b, 0x13, 0xea, 0x48, 0xb5, 0xa6, 0x9e, 0x38, 0xe8, 0xf3, 0xc6, ++ 0xf6, 0x3f, 0x9a, 0xa1, 0xcf, 0x75, 0x6d, 0xef, 0x9a, 0x1d, 0x93, 0x30, ++ 0x5f, 0xd6, 0x9d, 0xc8, 0x20, 0xd9, 0x8f, 0xd7, 0x69, 0xf1, 0xab, 0xa6, ++ 0x7d, 0xfc, 0x7b, 0xa8, 0xf3, 0xd5, 0x1c, 0x93, 0x51, 0xb4, 0xc6, 0xf8, ++ 0x2e, 0x9f, 0xdf, 0xab, 0x0e, 0xb4, 0xf2, 0x39, 0xbd, 0x5a, 0xf8, 0xf9, ++ 0x9c, 0x5e, 0xdd, 0x32, 0x58, 0x5f, 0xfa, 0x13, 0x1c, 0x5c, 0x17, 0x09, ++ 0xb5, 0x8f, 0xb0, 0x7c, 0xc7, 0x20, 0xbb, 0x98, 0xb9, 0x4d, 0xda, 0xc5, ++ 0x9d, 0xaa, 0x58, 0x0e, 0x3f, 0x27, 0xb4, 0x3a, 0xed, 0xcc, 0x84, 0x78, ++ 0xce, 0x47, 0x06, 0xe6, 0xc9, 0x7c, 0xd7, 0xa5, 0x9e, 0x7f, 0x08, 0xf9, ++ 0x4b, 0x20, 0x45, 0x71, 0x2a, 0xb4, 0x54, 0x20, 0xcc, 0xb3, 0x0e, 0x79, ++ 0x91, 0x27, 0x5d, 0xe6, 0x33, 0x81, 0xdf, 0xbd, 0x90, 0xbd, 0x94, 0xfd, ++ 0x8a, 0x37, 0xfb, 0x76, 0xda, 0x57, 0x40, 0xcb, 0x77, 0x67, 0x6e, 0xd8, ++ 0x6a, 0x54, 0x83, 0xe8, 0x99, 0xd9, 0x29, 0xeb, 0x92, 0x81, 0x30, 0x51, ++ 0x7e, 0x90, 0xe5, 0xed, 0x1e, 0x0d, 0x39, 0x08, 0x57, 0x49, 0x44, 0x7e, ++ 0x0e, 0xdb, 0x55, 0x16, 0xfc, 0x6a, 0xc0, 0x20, 0xeb, 0xa8, 0xa1, 0xfb, ++ 0xa8, 0xd7, 0xea, 0x45, 0xc7, 0x51, 0x4f, 0xca, 0x1c, 0xa0, 0x7b, 0x76, ++ 0x62, 0xa2, 0xf4, 0x63, 0xc2, 0xcb, 0xfa, 0xd3, 0x65, 0x90, 0xdf, 0x77, ++ 0x19, 0xa8, 0x7f, 0xca, 0xc0, 0xfc, 0xc5, 0xf9, 0x72, 0xfe, 0xc0, 0x79, ++ 0x48, 0xd6, 0xc1, 0xae, 0xe5, 0x57, 0x76, 0x91, 0x7c, 0xca, 0x48, 0x3e, ++ 0x7b, 0x48, 0xce, 0x80, 0xcf, 0x53, 0x3c, 0x2e, 0x23, 0x3f, 0xd3, 0x42, ++ 0xf1, 0x18, 0xf8, 0xbf, 0x52, 0x3c, 0x06, 0xf4, 0xd5, 0x67, 0x70, 0xfb, ++ 0x4b, 0xf5, 0x4e, 0xc6, 0x0f, 0xd4, 0xdf, 0xc0, 0xf8, 0xc1, 0x7a, 0x17, ++ 0xe3, 0xed, 0xf5, 0xc5, 0x0c, 0x5f, 0xa9, 0x2f, 0xe1, 0xf6, 0xe3, 0x20, ++ 0xf5, 0xfb, 0xf8, 0xdf, 0xd3, 0x8d, 0xd0, 0x87, 0x2e, 0xd8, 0xd8, 0xa8, ++ 0x01, 0xfc, 0x64, 0x4c, 0x08, 0x3e, 0x6a, 0xf0, 0xf8, 0x93, 0x31, 0xca, ++ 0x60, 0x7c, 0x94, 0xc2, 0xe3, 0xb3, 0xf3, 0x9f, 0x6e, 0xf4, 0x64, 0xa2, ++ 0x6e, 0x6a, 0xd7, 0xec, 0xdb, 0x11, 0x89, 0xfc, 0xeb, 0x8c, 0x4d, 0xd6, ++ 0xa1, 0xce, 0xd8, 0x64, 0x1d, 0xaa, 0x75, 0x94, 0xfb, 0xa6, 0x7c, 0xea, ++ 0x2f, 0x9b, 0xb9, 0x76, 0x97, 0x3c, 0x87, 0xba, 0xd2, 0x31, 0xae, 0x20, ++ 0x66, 0x3e, 0x9f, 0x5f, 0xfb, 0xe9, 0xfc, 0x0a, 0x7f, 0xb4, 0x22, 0xdf, ++ 0x9d, 0x07, 0xb9, 0x1c, 0x3b, 0x96, 0x9f, 0xba, 0x95, 0xfd, 0xa4, 0x8d, ++ 0xeb, 0xa0, 0x27, 0xef, 0xba, 0x2e, 0x9a, 0xeb, 0x80, 0x6f, 0xd2, 0x79, ++ 0x9c, 0x3e, 0x9d, 0x9b, 0x31, 0x75, 0x5d, 0x36, 0xe1, 0xb9, 0x11, 0x0a, ++ 0xeb, 0x2f, 0xf9, 0x8b, 0xeb, 0x4b, 0xf4, 0x73, 0x25, 0xad, 0x93, 0xdf, ++ 0x29, 0xef, 0x51, 0x0a, 0xd5, 0xea, 0x32, 0xac, 0xbf, 0x72, 0xa4, 0x6d, ++ 0x2a, 0xfc, 0xef, 0x17, 0x2e, 0xf7, 0xad, 0xa0, 0x43, 0xe7, 0x77, 0xd1, ++ 0xa8, 0x65, 0xa9, 0xc8, 0x87, 0xba, 0x4c, 0x8e, 0xf7, 0x50, 0xc7, 0xf5, ++ 0xfc, 0xde, 0x24, 0x70, 0x9e, 0xd2, 0xeb, 0x7d, 0xfa, 0xb8, 0x0e, 0x57, ++ 0xee, 0x5d, 0x98, 0x37, 0x33, 0x63, 0xdc, 0xba, 0x29, 0xf0, 0x3b, 0x64, ++ 0x64, 0xf0, 0x73, 0x2e, 0xb3, 0x68, 0x01, 0x5d, 0x2e, 0x43, 0xb8, 0xb2, ++ 0x96, 0xfd, 0x96, 0xc3, 0x08, 0x3f, 0x70, 0x97, 0xa6, 0xc7, 0x79, 0x0e, ++ 0x99, 0x17, 0xfb, 0xcd, 0x0e, 0x63, 0x0c, 0xea, 0x37, 0x61, 0xb9, 0xb1, ++ 0x1e, 0x9a, 0xd7, 0xa5, 0xc9, 0xf9, 0x98, 0x26, 0xe7, 0xe3, 0x9a, 0x9c, ++ 0xdf, 0x46, 0x9d, 0x8c, 0xe0, 0x3b, 0xd4, 0x0e, 0xd8, 0x4d, 0xed, 0x80, ++ 0x93, 0x74, 0xfe, 0x1a, 0xfb, 0x98, 0x6f, 0x4f, 0xe4, 0x95, 0x94, 0xb1, ++ 0xfe, 0x8a, 0xbe, 0x24, 0xe0, 0x7a, 0x5d, 0x70, 0x16, 0xec, 0x4b, 0xfa, ++ 0x9b, 0x24, 0xe8, 0xf5, 0x66, 0x4d, 0x7f, 0x13, 0x34, 0x7f, 0xd3, 0x95, ++ 0x5b, 0x52, 0x25, 0xe7, 0xf9, 0x78, 0x9d, 0x2a, 0xad, 0xde, 0x76, 0x5e, ++ 0xbb, 0x07, 0xd1, 0xf7, 0xab, 0xcf, 0x1b, 0x98, 0x2f, 0x18, 0xce, 0xbd, ++ 0x5e, 0x78, 0xac, 0xf0, 0xf3, 0x2f, 0xcb, 0x73, 0xa7, 0x18, 0x4d, 0xf9, ++ 0x08, 0xe1, 0x73, 0x5f, 0x8e, 0x67, 0x3f, 0xa4, 0x5a, 0x6f, 0xcf, 0xfc, ++ 0x84, 0xec, 0x7c, 0xee, 0x54, 0x79, 0x0e, 0x10, 0xfb, 0x2d, 0x72, 0x5c, ++ 0x82, 0x23, 0x07, 0x76, 0xb2, 0x56, 0xab, 0xb7, 0xf6, 0x7a, 0x0d, 0x1e, ++ 0x13, 0xea, 0xd3, 0x31, 0xdd, 0xe9, 0x31, 0x88, 0xbf, 0x9a, 0x7d, 0xe9, ++ 0xf8, 0xc1, 0xbf, 0xa9, 0xec, 0xaf, 0x6b, 0xa6, 0x10, 0x4e, 0xf0, 0x55, ++ 0x45, 0xee, 0xaf, 0x66, 0x6e, 0x77, 0xfa, 0x30, 0xcc, 0x57, 0x6c, 0x06, ++ 0xae, 0x6f, 0x37, 0xc9, 0xfe, 0x13, 0x9a, 0xfd, 0xd5, 0xa4, 0x68, 0xeb, ++ 0x69, 0xfb, 0x11, 0x56, 0x5f, 0x12, 0xe4, 0x11, 0x38, 0xf4, 0x72, 0xd2, ++ 0x62, 0xc2, 0x37, 0x45, 0xf8, 0x97, 0x4a, 0xbf, 0xef, 0x4f, 0x67, 0x7f, ++ 0x2d, 0xfc, 0xe9, 0x73, 0xe1, 0x17, 0x15, 0xdf, 0x07, 0xc2, 0x49, 0x79, ++ 0x65, 0xc1, 0xd4, 0xc5, 0xc6, 0x91, 0xe0, 0x87, 0x6f, 0x07, 0xf0, 0xea, ++ 0x82, 0x9c, 0xc5, 0xc6, 0x1b, 0xd1, 0xdf, 0xfa, 0x81, 0x3d, 0xb8, 0x7f, ++ 0x84, 0x2f, 0x49, 0xb1, 0x03, 0xcf, 0x96, 0xfd, 0x23, 0x5a, 0x77, 0x0c, ++ 0x73, 0x06, 0xe1, 0xa6, 0x97, 0x3e, 0x40, 0xbf, 0xd9, 0x90, 0xb3, 0xb8, ++ 0x80, 0xf0, 0xd9, 0x16, 0xef, 0xb1, 0x7a, 0xe8, 0xcd, 0x8b, 0x52, 0xbf, ++ 0x6c, 0xfb, 0xda, 0x4e, 0x83, 0x6f, 0x55, 0x1d, 0x32, 0x6f, 0xcf, 0xdb, ++ 0xd7, 0x76, 0xe1, 0x25, 0xc4, 0xe5, 0xb6, 0x48, 0x27, 0xdc, 0xfb, 0xde, ++ 0xfc, 0x64, 0xe6, 0xf7, 0xda, 0x8e, 0xdd, 0x9b, 0xa1, 0x6f, 0xbd, 0xad, ++ 0xf2, 0x3e, 0x60, 0x53, 0xcb, 0x1f, 0x77, 0xfc, 0x92, 0xc7, 0x59, 0x70, ++ 0x4d, 0x42, 0xeb, 0xfa, 0xb2, 0x05, 0x7d, 0x67, 0xc5, 0x91, 0xff, 0x58, ++ 0x04, 0xba, 0x66, 0x87, 0xfb, 0xbe, 0x04, 0xfe, 0xe0, 0x91, 0x19, 0x4c, ++ 0xe7, 0xec, 0xe1, 0xd2, 0xae, 0x1f, 0x3e, 0x92, 0xb7, 0x18, 0x76, 0xda, ++ 0xdb, 0xb6, 0xef, 0x67, 0xb0, 0xbf, 0xd9, 0xd1, 0x94, 0xd0, 0x82, 0x9e, ++ 0x17, 0x6c, 0x5c, 0x87, 0xa8, 0xdc, 0x3f, 0xa1, 0x00, 0x76, 0xda, 0x1b, ++ 0xd9, 0xbd, 0x00, 0xeb, 0xd7, 0x3e, 0x6f, 0x71, 0x42, 0x4f, 0x2b, 0xf7, ++ 0xc7, 0xe7, 0xa1, 0x3e, 0x70, 0x30, 0x5f, 0xd6, 0xc3, 0x2b, 0x26, 0x6e, ++ 0x49, 0x42, 0x9c, 0x35, 0xbc, 0xb2, 0x77, 0xd7, 0x2f, 0x71, 0xbf, 0xfa, ++ 0xbc, 0x8d, 0xef, 0x85, 0xea, 0x62, 0x64, 0x9e, 0x57, 0xa9, 0x36, 0x4e, ++ 0x5b, 0xc1, 0xf2, 0xdb, 0xb9, 0xeb, 0x69, 0xd0, 0xbd, 0xd7, 0xc6, 0xf7, ++ 0xb3, 0x15, 0xa8, 0x55, 0x11, 0x5e, 0xb1, 0x2b, 0x8d, 0xeb, 0xf8, 0xaf, ++ 0x7e, 0xf3, 0xf1, 0x02, 0xc8, 0xa1, 0x50, 0xdd, 0xbe, 0x0b, 0xed, 0x5f, ++ 0x3e, 0x67, 0x33, 0x80, 0x0f, 0x27, 0xcc, 0xae, 0xe8, 0x9b, 0x61, 0x87, ++ 0x27, 0x4c, 0x7c, 0xde, 0xac, 0xd0, 0xf0, 0x8a, 0x93, 0xc3, 0x25, 0x3d, ++ 0xe1, 0x3d, 0x45, 0x2c, 0xbf, 0xd8, 0x2d, 0x49, 0x88, 0xb3, 0x95, 0xc3, ++ 0x7f, 0x7e, 0x1b, 0xe8, 0x9e, 0xad, 0x6e, 0xd9, 0x81, 0xf3, 0x8e, 0xd8, ++ 0x6d, 0xe1, 0xbb, 0x89, 0xb3, 0x7b, 0x89, 0x6f, 0x34, 0xef, 0x6c, 0xb3, ++ 0x69, 0x0a, 0xa4, 0xdc, 0xbb, 0x37, 0xd2, 0x08, 0x7d, 0x39, 0xaf, 0x6c, ++ 0x59, 0xf0, 0x14, 0xd6, 0x6f, 0x96, 0xe3, 0xce, 0xdb, 0xb6, 0x30, 0x3f, ++ 0x3d, 0xcd, 0xe3, 0x05, 0xbe, 0x47, 0xe3, 0x04, 0xfc, 0xd6, 0x79, 0x65, ++ 0xeb, 0xa0, 0xf6, 0xb3, 0xcd, 0xbb, 0xb3, 0x70, 0x1e, 0x3d, 0xf7, 0xfc, ++ 0x6c, 0x3e, 0x97, 0xea, 0xfa, 0xab, 0xdb, 0x4b, 0xe5, 0x73, 0x96, 0x41, ++ 0x71, 0x91, 0x3d, 0x01, 0xf9, 0xa3, 0x4a, 0xed, 0x6f, 0x61, 0xf7, 0x88, ++ 0x08, 0x8a, 0xb7, 0x15, 0x1a, 0x7a, 0xee, 0xe0, 0x93, 0xbd, 0x4f, 0x89, ++ 0x81, 0xf9, 0xe7, 0x5a, 0x4c, 0x7e, 0x33, 0xf1, 0xa8, 0xc2, 0x22, 0xd6, ++ 0x59, 0x63, 0x06, 0xec, 0xa1, 0x32, 0xf1, 0x96, 0x62, 0xec, 0xaf, 0xd2, ++ 0xd0, 0x98, 0x8e, 0xbc, 0xa5, 0x62, 0x6a, 0xcf, 0x02, 0xd8, 0xc5, 0x59, ++ 0x9b, 0xb0, 0x26, 0xd0, 0xb8, 0xb7, 0xb4, 0xb8, 0x55, 0x79, 0x60, 0xcd, ++ 0x1c, 0xe4, 0xbf, 0xd7, 0xa2, 0xe7, 0xb2, 0xe6, 0x8f, 0x2e, 0x26, 0xc8, ++ 0xf8, 0x75, 0xb1, 0xdd, 0xe6, 0x0d, 0xbe, 0x97, 0x0c, 0x85, 0xef, 0xd7, ++ 0x0b, 0xfb, 0xdb, 0x69, 0x03, 0xf8, 0x3d, 0xcb, 0x2d, 0x9c, 0xc3, 0xeb, ++ 0xeb, 0xbd, 0x65, 0xf6, 0x55, 0xe3, 0x9c, 0x56, 0x1b, 0x23, 0xfd, 0xc7, ++ 0x07, 0x34, 0xbe, 0x85, 0xfc, 0xd8, 0x37, 0x5a, 0xbc, 0x5b, 0xb8, 0x6a, ++ 0xf0, 0xf8, 0xfe, 0xfc, 0x18, 0xfe, 0x7e, 0xad, 0xb9, 0x27, 0x1d, 0xf1, ++ 0x4f, 0x5f, 0x3f, 0x90, 0xaf, 0xfb, 0xb5, 0x9e, 0x74, 0xf8, 0xab, 0xd0, ++ 0x79, 0xb3, 0x91, 0x8e, 0xc0, 0x8f, 0xbc, 0xa0, 0xb0, 0x1f, 0xa9, 0x3c, ++ 0xa0, 0x7c, 0xa8, 0x12, 0x9f, 0x2a, 0xad, 0x1e, 0xaf, 0x0a, 0xbe, 0x08, ++ 0xb3, 0xbe, 0x4f, 0xe3, 0x65, 0x45, 0xce, 0x4b, 0x98, 0xa6, 0xf1, 0x9d, ++ 0xe6, 0x6e, 0x28, 0x48, 0xe6, 0xef, 0x56, 0xb6, 0xd8, 0x5c, 0x36, 0x9a, ++ 0x57, 0x15, 0xd6, 0x13, 0x85, 0xbc, 0xa8, 0x3a, 0xb2, 0x27, 0x0a, 0xf9, ++ 0x4e, 0xef, 0x2b, 0xaa, 0x68, 0xd2, 0xc4, 0x15, 0x1b, 0xa7, 0xc9, 0x27, ++ 0x45, 0x13, 0x59, 0x50, 0xbd, 0xb1, 0xc2, 0x67, 0x72, 0xd9, 0xb2, 0x86, ++ 0x90, 0x33, 0xf2, 0x27, 0x1a, 0xb7, 0x0c, 0x7f, 0xd3, 0xf7, 0x9f, 0x29, ++ 0x48, 0xe1, 0xfd, 0x94, 0xb7, 0x87, 0xf3, 0xf7, 0x84, 0xbd, 0x67, 0x1a, ++ 0xf4, 0xb4, 0x7c, 0xfb, 0xe0, 0x79, 0xd8, 0x97, 0x3d, 0xc8, 0xfe, 0x7a, ++ 0xdb, 0x77, 0xc6, 0x05, 0x9f, 0xcb, 0x53, 0x34, 0xba, 0x03, 0xca, 0x87, ++ 0x6c, 0x27, 0x81, 0x6f, 0x3e, 0x4a, 0x82, 0xdc, 0x2b, 0x0d, 0x62, 0x1d, ++ 0xee, 0x2f, 0xcf, 0xd1, 0x1c, 0xdc, 0x6b, 0x12, 0x2e, 0xac, 0x12, 0xe7, ++ 0x7b, 0xcf, 0xca, 0xbf, 0x44, 0x84, 0x41, 0x5f, 0xce, 0x5d, 0xac, 0x66, ++ 0xbb, 0xed, 0x55, 0x7a, 0xd8, 0xaf, 0xbd, 0x53, 0x30, 0x87, 0xfd, 0x52, ++ 0xaf, 0xa9, 0x87, 0xfd, 0xda, 0x1b, 0x47, 0xee, 0x64, 0xff, 0xd0, 0x3b, ++ 0xac, 0x67, 0x01, 0xfc, 0xd4, 0x3b, 0x05, 0xcb, 0x64, 0xff, 0xc8, 0x9e, ++ 0x05, 0x0e, 0xea, 0xdf, 0xa7, 0xe3, 0x63, 0x04, 0xc7, 0xfd, 0xf7, 0x8f, ++ 0xd4, 0xb0, 0xff, 0x98, 0xad, 0xca, 0x77, 0x15, 0x62, 0xa7, 0xc9, 0x2e, ++ 0xeb, 0x41, 0x1b, 0x4e, 0xd6, 0xf3, 0xf9, 0xc2, 0xe4, 0x08, 0x3e, 0x7f, ++ 0x9f, 0x2a, 0xd0, 0xea, 0x3d, 0x03, 0xf2, 0xe1, 0x73, 0x97, 0x6e, 0x37, ++ 0xbd, 0xc2, 0xb1, 0xef, 0x00, 0xec, 0xb0, 0x3c, 0x82, 0xeb, 0x3a, 0x94, ++ 0x47, 0xb5, 0xbc, 0x84, 0x7c, 0x6f, 0x7e, 0x9c, 0x13, 0xef, 0x35, 0xca, ++ 0x31, 0x4f, 0xea, 0x81, 0x39, 0xf8, 0xbe, 0x31, 0x36, 0xe6, 0xd2, 0x52, ++ 0xc8, 0xe7, 0xf6, 0xd1, 0xee, 0xa2, 0x82, 0x1c, 0xdc, 0x6f, 0xf6, 0xf0, ++ 0x39, 0x82, 0xb4, 0x9a, 0xe3, 0x4d, 0xed, 0xef, 0x2c, 0x7c, 0x9e, 0x0c, ++ 0x98, 0xfa, 0x76, 0xc1, 0x4f, 0xa5, 0x8f, 0x76, 0xcf, 0x2a, 0x20, 0x3a, ++ 0xaa, 0xcd, 0xdd, 0xeb, 0xb3, 0x89, 0xa4, 0x0b, 0xa6, 0x9e, 0x2e, 0x94, ++ 0xc8, 0x67, 0xa9, 0xd2, 0x1f, 0x89, 0xdd, 0x52, 0xaf, 0x7a, 0x33, 0x77, ++ 0xca, 0x7b, 0x1a, 0xed, 0xbe, 0xf2, 0x2e, 0x8d, 0xff, 0x82, 0x0e, 0x31, ++ 0x8d, 0xd0, 0x0b, 0x45, 0xca, 0xf7, 0x8d, 0xf6, 0xfd, 0x6f, 0xc3, 0xaf, ++ 0xf4, 0x76, 0x8f, 0x63, 0x7f, 0x1c, 0x6a, 0x37, 0x67, 0xdb, 0x1f, 0x8b, ++ 0x82, 0x7f, 0xf8, 0x13, 0xc5, 0x71, 0x4f, 0xd0, 0x79, 0xff, 0x4f, 0x8b, ++ 0x76, 0xf3, 0x3d, 0xeb, 0x3c, 0xbc, 0x07, 0x21, 0xb8, 0x78, 0xdd, 0x60, ++ 0x7d, 0xe8, 0xff, 0xfa, 0x76, 0x3e, 0xf7, 0x89, 0xcd, 0x41, 0xed, 0xd0, ++ 0xc3, 0x86, 0xc1, 0x78, 0xa8, 0x1e, 0x41, 0x1f, 0xfd, 0x83, 0xfc, 0x8e, ++ 0x87, 0xf9, 0xbe, 0x4d, 0xb3, 0xab, 0xaa, 0xbc, 0xee, 0x5a, 0xf0, 0xe1, ++ 0x0a, 0x3e, 0x97, 0x70, 0x35, 0x08, 0x7f, 0x3d, 0x04, 0x0f, 0x19, 0x2f, ++ 0x4a, 0x64, 0x9e, 0xb0, 0x0d, 0xf1, 0x9f, 0xf8, 0x51, 0x3d, 0xc6, 0x7f, ++ 0x92, 0xcf, 0xe9, 0xfb, 0x4c, 0x02, 0x7e, 0x7c, 0x2d, 0xc5, 0x2f, 0xc6, ++ 0xdb, 0xc2, 0xbd, 0x38, 0xaf, 0x18, 0xf6, 0x51, 0x7c, 0x8a, 0x95, 0xf1, ++ 0x09, 0x71, 0xa1, 0x2a, 0xaa, 0x9b, 0xeb, 0x53, 0xbd, 0x6d, 0x16, 0xbe, ++ 0xef, 0x7d, 0xb0, 0xe3, 0xd3, 0x24, 0xec, 0x9f, 0xf4, 0x90, 0xeb, 0x30, ++ 0x55, 0x1d, 0x2f, 0xc7, 0xe1, 0xfc, 0xbe, 0x57, 0x3b, 0x2f, 0x50, 0x1c, ++ 0x8c, 0xe3, 0xf7, 0x31, 0x6d, 0x1d, 0x71, 0x38, 0x77, 0xe8, 0xed, 0xd5, ++ 0x06, 0x5f, 0x3a, 0xe8, 0xa2, 0x8c, 0x88, 0xf3, 0x75, 0xbd, 0xbd, 0x46, ++ 0xf5, 0xa7, 0x83, 0xfe, 0x2a, 0xa5, 0x3b, 0x0b, 0xfd, 0x7b, 0x41, 0x37, ++ 0x8f, 0x27, 0x5c, 0x05, 0x2e, 0x78, 0x1f, 0xd5, 0x8a, 0xb4, 0x77, 0xd1, ++ 0xa1, 0xb2, 0x3f, 0x0f, 0x95, 0xdb, 0x93, 0x9a, 0xbe, 0x92, 0x5f, 0xc8, ++ 0xe2, 0xf7, 0x1d, 0xaf, 0xc8, 0xfa, 0x80, 0xee, 0x07, 0x2a, 0x34, 0x7f, ++ 0xf2, 0x3a, 0xda, 0x33, 0xa5, 0xdd, 0xdb, 0xf5, 0x7b, 0x25, 0x9a, 0x5a, ++ 0x01, 0x7b, 0x1f, 0xc2, 0x3f, 0x24, 0x14, 0xe8, 0x79, 0xf1, 0x72, 0xae, ++ 0xdf, 0x3c, 0x5e, 0xe0, 0x90, 0xb8, 0x36, 0x9f, 0xd7, 0x95, 0xf5, 0x25, ++ 0xee, 0xaf, 0x7d, 0xf5, 0x7c, 0x56, 0x4a, 0x26, 0xe6, 0x69, 0xe3, 0x82, ++ 0xfd, 0xd0, 0xb8, 0x01, 0xbf, 0x02, 0xfb, 0x4f, 0x60, 0xfb, 0x7f, 0xd0, ++ 0x14, 0x47, 0xfb, 0xaa, 0xdc, 0xa1, 0x38, 0xd7, 0xc2, 0x4f, 0x95, 0xae, ++ 0x29, 0xa2, 0xe1, 0x62, 0x99, 0x71, 0x45, 0x11, 0xd7, 0xcd, 0x84, 0x87, ++ 0xcf, 0x6d, 0xa1, 0x74, 0x85, 0xea, 0xd1, 0xe4, 0x02, 0xc9, 0xa7, 0x4a, ++ 0xc3, 0xb0, 0xc2, 0xd8, 0xa0, 0xf5, 0xce, 0x91, 0x4f, 0x4f, 0x98, 0xc2, ++ 0x7e, 0xc6, 0x0f, 0xbf, 0xf3, 0x93, 0xd8, 0x47, 0x8b, 0x50, 0xa7, 0xf8, ++ 0x71, 0xa9, 0x7c, 0x37, 0x70, 0x25, 0xde, 0x04, 0xdb, 0x39, 0xf6, 0xb3, ++ 0x5d, 0xfa, 0x71, 0x98, 0xcd, 0x65, 0xc3, 0xd5, 0x7a, 0xbc, 0x6c, 0x79, ++ 0xe3, 0xfa, 0xf8, 0x21, 0xe8, 0x08, 0xa5, 0xb3, 0xc2, 0xdd, 0x58, 0x14, ++ 0xe7, 0xb8, 0xba, 0x5d, 0xa7, 0xf7, 0x9c, 0x4d, 0xa7, 0x2f, 0xcf, 0x34, ++ 0x22, 0x98, 0x0f, 0xf3, 0xd6, 0x14, 0x8d, 0x20, 0xb8, 0xcc, 0xfa, 0xcf, ++ 0xf2, 0x41, 0xee, 0xf7, 0x5c, 0x87, 0xc5, 0x8f, 0xb8, 0x5a, 0x51, 0xba, ++ 0x62, 0x7d, 0xf4, 0x10, 0x7a, 0x73, 0x55, 0x3c, 0xd8, 0x1e, 0x14, 0xbf, ++ 0x52, 0x20, 0x5f, 0x2f, 0xdf, 0x6f, 0x5c, 0x8b, 0xfe, 0x50, 0x58, 0xad, ++ 0xf8, 0x4f, 0xa2, 0x5e, 0x24, 0xc8, 0xae, 0x9a, 0xd9, 0xbe, 0xc8, 0x5e, ++ 0x82, 0xe2, 0xc2, 0x8d, 0x05, 0x21, 0x75, 0x87, 0xf2, 0x45, 0x63, 0x91, ++ 0x57, 0x0b, 0xf7, 0xa2, 0xb1, 0x88, 0x33, 0x64, 0x57, 0x0b, 0x9c, 0x43, ++ 0x9c, 0x2f, 0xc9, 0x41, 0x8e, 0x32, 0xf0, 0x9b, 0x11, 0x0f, 0xc3, 0x50, ++ 0x7a, 0xfe, 0x5c, 0x20, 0xdf, 0x25, 0xdd, 0x58, 0x20, 0xed, 0x7c, 0xf5, ++ 0x0c, 0x57, 0x00, 0x7e, 0xf3, 0x66, 0xd5, 0xc0, 0x79, 0x78, 0xe8, 0x7a, ++ 0x5f, 0x15, 0xc8, 0x7c, 0xa2, 0x3b, 0x2e, 0xf2, 0x3e, 0xfd, 0x3d, 0x07, ++ 0x84, 0x7d, 0xb3, 0x2a, 0xf9, 0x96, 0x68, 0xe8, 0x7f, 0x07, 0xf6, 0x96, ++ 0x18, 0x17, 0xe9, 0xc0, 0x7d, 0x50, 0x61, 0x7e, 0xb8, 0x1c, 0x77, 0xc8, ++ 0x66, 0x47, 0xfd, 0x26, 0x70, 0xe8, 0x12, 0xd7, 0x77, 0x03, 0x0f, 0x45, ++ 0xcc, 0x93, 0xf7, 0x06, 0x11, 0x62, 0x24, 0xf5, 0x77, 0x25, 0x4c, 0x6a, ++ 0x0a, 0x8e, 0x23, 0xbf, 0x29, 0x94, 0xfb, 0x0d, 0xcf, 0x96, 0x79, 0x4b, ++ 0x5d, 0x86, 0xe9, 0xef, 0xd7, 0x87, 0x32, 0x23, 0xaf, 0xd4, 0x87, 0x38, ++ 0x6f, 0xc8, 0x0c, 0xe7, 0xfb, 0x92, 0xde, 0xf6, 0x2f, 0x38, 0x6e, 0x05, ++ 0x3a, 0x73, 0xec, 0xb8, 0xd7, 0xe8, 0xed, 0xa6, 0xd3, 0x21, 0xd9, 0x53, ++ 0xdd, 0x37, 0xff, 0x1d, 0x87, 0xf8, 0xda, 0xdb, 0xf9, 0x67, 0x7e, 0x87, ++ 0xd6, 0xfb, 0xf5, 0xa7, 0xfc, 0x3e, 0x6d, 0xa3, 0xf6, 0x3e, 0xf0, 0xf5, ++ 0x76, 0xed, 0x7d, 0x57, 0xb7, 0x23, 0x12, 0xed, 0x81, 0xe2, 0x8f, 0x8b, ++ 0x30, 0x6e, 0x93, 0x06, 0x07, 0xea, 0x04, 0xb2, 0x5e, 0xac, 0x43, 0xfd, ++ 0xfc, 0xab, 0xd7, 0x03, 0x82, 0xce, 0xc1, 0xa3, 0x0b, 0x87, 0x3e, 0x07, ++ 0xc7, 0xb8, 0x23, 0x82, 0xeb, 0x04, 0x8e, 0xf8, 0xa1, 0xea, 0x2a, 0xc1, ++ 0x75, 0x82, 0xd4, 0x34, 0x59, 0x27, 0x00, 0x44, 0x9d, 0x20, 0xd5, 0x24, ++ 0xeb, 0x04, 0xc0, 0x51, 0x27, 0x00, 0x44, 0x9d, 0x00, 0xed, 0xa8, 0x13, ++ 0x00, 0x47, 0x9d, 0x00, 0x38, 0xea, 0x04, 0xc0, 0x51, 0x27, 0x00, 0x44, ++ 0x9d, 0x00, 0xed, 0x5f, 0xce, 0x93, 0xef, 0x65, 0x02, 0xa4, 0xc4, 0xb2, ++ 0x7e, 0x19, 0xc1, 0xfe, 0xfd, 0xde, 0x66, 0xd5, 0x8b, 0xfc, 0xfc, 0xde, ++ 0x43, 0xf2, 0x1e, 0xea, 0xde, 0x46, 0x85, 0xdf, 0x69, 0x5d, 0xa0, 0xef, ++ 0x23, 0xce, 0x5d, 0xf5, 0x5e, 0xe7, 0x80, 0xf6, 0x5e, 0xc7, 0xb7, 0x95, ++ 0xef, 0xf5, 0xea, 0xda, 0x54, 0x27, 0x44, 0x55, 0x67, 0xea, 0x3b, 0x8a, ++ 0xba, 0x4e, 0x5d, 0xab, 0xe2, 0x5c, 0x03, 0xff, 0x52, 0x3f, 0x8f, 0xbf, ++ 0xbf, 0xb1, 0x33, 0xe7, 0xbd, 0x52, 0xb4, 0x37, 0x9b, 0x9c, 0x06, 0x07, ++ 0xe4, 0x74, 0x31, 0x0e, 0xf5, 0xaa, 0xca, 0xce, 0x66, 0xae, 0x3f, 0x15, ++ 0xc4, 0x1f, 0x32, 0xb3, 0x7c, 0x5b, 0x14, 0x81, 0x7a, 0xe9, 0x9d, 0x16, ++ 0x79, 0xce, 0xad, 0x51, 0xa9, 0x75, 0x0a, 0xdf, 0x87, 0x72, 0x1e, 0x5c, ++ 0x63, 0xe9, 0xe6, 0xf3, 0x47, 0xd5, 0x1e, 0xc5, 0x5e, 0x16, 0x7c, 0x9f, ++ 0x7b, 0xc3, 0xe7, 0xec, 0x07, 0xd6, 0xda, 0xa2, 0x9a, 0x40, 0x67, 0x8d, ++ 0xcf, 0x66, 0x2f, 0x1b, 0xe2, 0xfd, 0x07, 0xdf, 0x0b, 0x3b, 0xc4, 0x95, ++ 0xfb, 0xe6, 0xa5, 0x72, 0x88, 0xa8, 0x89, 0x28, 0xe2, 0xfb, 0xe6, 0xa5, ++ 0xb8, 0x67, 0x26, 0x28, 0xd4, 0xaf, 0x8d, 0x7c, 0x7f, 0x4c, 0x07, 0xd3, ++ 0xe1, 0xd0, 0x47, 0xbc, 0xab, 0xca, 0x80, 0x5b, 0xb7, 0x4b, 0xbb, 0x0f, ++ 0x79, 0x4f, 0x55, 0xd9, 0xd9, 0xba, 0x3e, 0x51, 0x5c, 0x7d, 0x0f, 0x8d, ++ 0xca, 0x00, 0xe4, 0x1f, 0x7a, 0xff, 0xec, 0x2e, 0x8c, 0x8c, 0x3d, 0x1d, ++ 0x0e, 0x47, 0x21, 0x26, 0x23, 0x6f, 0x2a, 0x7e, 0xbc, 0x6c, 0x5f, 0x1b, ++ 0x7d, 0xaf, 0x7f, 0x8b, 0x85, 0xf3, 0x8e, 0x15, 0xf9, 0xee, 0x65, 0xd0, ++ 0xa3, 0xa3, 0x26, 0x17, 0xd7, 0x49, 0x8e, 0x1e, 0xb2, 0xf1, 0xf9, 0xe8, ++ 0x93, 0xad, 0xe3, 0x07, 0xd5, 0x49, 0xbe, 0x70, 0xb9, 0xab, 0x0b, 0xf9, ++ 0x7e, 0x7e, 0x34, 0xd7, 0x2d, 0x56, 0x9a, 0x14, 0x8e, 0xcb, 0xf9, 0xc5, ++ 0xe3, 0xe2, 0xf9, 0xdd, 0xc0, 0x31, 0x13, 0xc7, 0x9f, 0x0e, 0x57, 0x49, ++ 0x2d, 0xc6, 0xad, 0x9c, 0xe4, 0xe0, 0xfa, 0x54, 0xa1, 0x45, 0xdc, 0xc7, ++ 0xeb, 0x68, 0xef, 0xb4, 0x08, 0xb2, 0x3d, 0x15, 0xae, 0x55, 0xbc, 0x06, ++ 0xc2, 0x17, 0x09, 0xa7, 0x19, 0xf6, 0xb3, 0x90, 0xd8, 0xc6, 0xfa, 0x62, ++ 0x8a, 0xd8, 0x80, 0xf7, 0x54, 0x0b, 0x85, 0x7c, 0xdf, 0xa0, 0xeb, 0xcd, ++ 0xca, 0xad, 0x0a, 0xe7, 0x05, 0x5c, 0x28, 0x88, 0xc3, 0xbd, 0xa4, 0xe4, ++ 0xef, 0xc2, 0xce, 0x7f, 0xbb, 0x84, 0xf7, 0x0b, 0x4b, 0x2c, 0x32, 0x7f, ++ 0x4d, 0x34, 0xc8, 0xfb, 0xec, 0xc4, 0x4d, 0xf2, 0x7d, 0xcb, 0x4f, 0x84, ++ 0xdb, 0x8c, 0x78, 0xbb, 0x8c, 0xe2, 0x22, 0x20, 0xc5, 0xc9, 0xdf, 0xf5, ++ 0x50, 0xbb, 0x3b, 0x7c, 0x74, 0x92, 0xcc, 0xcf, 0x1d, 0xf1, 0x58, 0x7f, ++ 0xd1, 0x71, 0x13, 0xbf, 0xf7, 0x2d, 0x8c, 0xff, 0x61, 0xba, 0x9b, 0xe3, ++ 0x75, 0x01, 0xbf, 0x63, 0x50, 0xfc, 0x77, 0xab, 0x97, 0xaf, 0xbb, 0xb6, ++ 0xfd, 0x84, 0xbe, 0x63, 0x38, 0x6a, 0x92, 0xfe, 0x85, 0xf8, 0xc8, 0xe7, ++ 0xa2, 0x2e, 0xe8, 0x25, 0xd7, 0x67, 0xdc, 0x0c, 0x8f, 0xd7, 0x97, 0x33, ++ 0x9c, 0x34, 0x43, 0xfa, 0xc7, 0x2b, 0xef, 0x12, 0x49, 0x46, 0x76, 0xd0, ++ 0x1f, 0xde, 0xf7, 0x01, 0xce, 0x8b, 0x89, 0xf1, 0x91, 0x4e, 0xf8, 0x3b, ++ 0xdd, 0xee, 0xaf, 0x7a, 0x9f, 0x18, 0x26, 0xa1, 0xfe, 0x3e, 0x71, 0x0c, ++ 0x41, 0x11, 0xf4, 0x3e, 0x71, 0xb3, 0xcb, 0xc1, 0xfe, 0x2e, 0xd1, 0x70, ++ 0x62, 0xaa, 0x03, 0xfc, 0xf8, 0x4b, 0x84, 0x13, 0xfc, 0xd0, 0xdf, 0x29, ++ 0xae, 0x9e, 0x51, 0xb2, 0x13, 0x72, 0x72, 0x45, 0x09, 0x0f, 0xbe, 0x8b, ++ 0x7b, 0x94, 0x2d, 0xc4, 0xd7, 0x22, 0x6c, 0x44, 0x41, 0x9d, 0xdb, 0xe7, ++ 0x52, 0x51, 0xb7, 0x3e, 0xa4, 0xd8, 0xf9, 0x5d, 0xf4, 0x55, 0x7e, 0x72, ++ 0xeb, 0x43, 0x78, 0xc7, 0x53, 0x97, 0xaa, 0xd8, 0x15, 0x07, 0xea, 0xe1, ++ 0x5b, 0x0a, 0xe3, 0x88, 0xee, 0xa2, 0x94, 0x64, 0xa6, 0xbb, 0xae, 0x5d, ++ 0xd6, 0x4b, 0x99, 0x43, 0x71, 0xa8, 0xa7, 0x6b, 0xf6, 0xe0, 0x72, 0xb7, ++ 0x15, 0x8e, 0x18, 0x68, 0x9f, 0xad, 0xd9, 0x45, 0x2f, 0x8d, 0x97, 0x7a, ++ 0x72, 0x93, 0x17, 0xfa, 0xf6, 0x1d, 0xea, 0xa8, 0xcf, 0x61, 0xbc, 0x47, ++ 0xd8, 0x9c, 0xcd, 0xda, 0x79, 0x0d, 0x72, 0x9f, 0x7d, 0xdd, 0x18, 0xae, ++ 0xa7, 0xea, 0x7a, 0xd3, 0xdf, 0x12, 0xdf, 0x04, 0xbd, 0x79, 0xb3, 0x50, ++ 0xc6, 0x99, 0xd2, 0xd2, 0x77, 0x4d, 0xc8, 0x03, 0xba, 0x72, 0xdd, 0x47, ++ 0xb0, 0xff, 0x05, 0x65, 0x9f, 0x3f, 0x14, 0xc7, 0xfb, 0x1b, 0xba, 0x8e, ++ 0x45, 0x7e, 0x94, 0xef, 0x25, 0x43, 0xeb, 0x58, 0xba, 0x5f, 0xde, 0xa5, ++ 0xd5, 0xc1, 0xe1, 0x3f, 0x8d, 0x5a, 0x9d, 0xd5, 0xa8, 0xd5, 0x59, 0x8d, ++ 0x5a, 0x9d, 0xd5, 0xa8, 0xd5, 0x59, 0x8d, 0x5a, 0x9d, 0xd5, 0xa8, 0xd5, ++ 0x59, 0x8d, 0x5a, 0x9d, 0xd5, 0xa8, 0xd5, 0x59, 0x8d, 0x5a, 0x9d, 0xd5, ++ 0xc8, 0xf5, 0xbb, 0xe5, 0x0c, 0xdf, 0xa9, 0x5f, 0xc5, 0xb0, 0xbb, 0xde, ++ 0xc3, 0xfd, 0x41, 0xfe, 0xff, 0xfd, 0x6b, 0xf8, 0xff, 0xd0, 0x3a, 0xe8, ++ 0xc7, 0x18, 0x17, 0x5a, 0x07, 0x15, 0x56, 0x47, 0x34, 0xc7, 0x51, 0xb2, ++ 0x6f, 0x59, 0x7f, 0x0e, 0xa9, 0x7b, 0x16, 0x0f, 0x5f, 0xbc, 0x81, 0xf8, ++ 0x97, 0xdf, 0x60, 0x76, 0xa2, 0x49, 0xaf, 0x83, 0xe2, 0xfd, 0xf2, 0xbd, ++ 0x11, 0xec, 0x0f, 0x2e, 0x14, 0x0e, 0x59, 0xff, 0xd4, 0xf9, 0x16, 0xc1, ++ 0xf5, 0xd2, 0x7e, 0x61, 0x9b, 0x02, 0xfe, 0xe7, 0x65, 0x8c, 0x33, 0x1a, ++ 0xa8, 0xff, 0x2f, 0x9a, 0x1c, 0xf4, 0xfa, 0x23, 0xec, 0x03, 0xfb, 0x83, ++ 0x7d, 0x00, 0xc2, 0x3e, 0x8c, 0x69, 0x03, 0xf6, 0xf1, 0x8c, 0x99, 0x4c, ++ 0x38, 0x5b, 0xc6, 0x7b, 0x0f, 0xc7, 0x7b, 0x1b, 0xcb, 0x75, 0xfd, 0x1a, ++ 0xf2, 0x1f, 0x84, 0x2f, 0x11, 0xf6, 0x41, 0xfe, 0xe3, 0x42, 0x88, 0xff, ++ 0xa0, 0x83, 0xc7, 0x5d, 0xa0, 0x63, 0x69, 0xa7, 0x7c, 0xd7, 0xa4, 0xbf, ++ 0xdf, 0xcc, 0x23, 0xf0, 0xd5, 0x94, 0x21, 0xfc, 0x89, 0x4f, 0xfa, 0x93, ++ 0x31, 0x61, 0xbe, 0xbd, 0xf8, 0xce, 0x98, 0xda, 0x30, 0x7e, 0x1f, 0x7c, ++ 0x54, 0x7b, 0x8f, 0x75, 0x74, 0xa3, 0x7c, 0x17, 0x57, 0x26, 0x4a, 0xf8, ++ 0xbb, 0x43, 0xf8, 0x95, 0x28, 0xc8, 0x63, 0xc9, 0xf0, 0xbe, 0x0f, 0x9e, ++ 0xa6, 0xf1, 0x4b, 0x1e, 0x89, 0xe0, 0xbc, 0x65, 0xfd, 0xc8, 0xa5, 0xd3, ++ 0xfe, 0x37, 0x7e, 0xe5, 0xf3, 0x42, 0xc9, 0x8f, 0xdf, 0xd6, 0xfb, 0x2b, ++ 0x3f, 0x21, 0x5a, 0x0a, 0xc2, 0xa4, 0xfe, 0x15, 0x98, 0x45, 0x06, 0xee, ++ 0x6b, 0x84, 0x21, 0x8c, 0xed, 0xa0, 0x50, 0xdd, 0xac, 0xe0, 0x7e, 0x74, ++ 0xe5, 0x3d, 0x62, 0x32, 0xe4, 0x5c, 0x60, 0x29, 0xd9, 0x0e, 0x3a, 0xe3, ++ 0xb5, 0xfb, 0x6d, 0x11, 0xab, 0xd5, 0x5b, 0x8d, 0xdd, 0x15, 0xbb, 0x09, ++ 0x3f, 0x11, 0x97, 0xe8, 0xc4, 0xbd, 0xd6, 0xe8, 0x84, 0x83, 0x02, 0xef, ++ 0x9f, 0x0a, 0xeb, 0x8a, 0x33, 0xe1, 0x17, 0xfd, 0x63, 0xdc, 0x13, 0x8a, ++ 0x72, 0xf0, 0x7e, 0x79, 0x8b, 0x82, 0xf9, 0xe1, 0x99, 0x72, 0xff, 0xb7, ++ 0x17, 0x87, 0x37, 0x41, 0xaf, 0x02, 0x87, 0xc6, 0xe7, 0x40, 0xde, 0x73, ++ 0x2d, 0x8e, 0x36, 0xd4, 0x01, 0x9c, 0x45, 0x09, 0x4b, 0x70, 0xce, 0x9f, ++ 0x1b, 0xed, 0xc8, 0x41, 0x1d, 0xc0, 0xd9, 0x35, 0x4a, 0xe2, 0xf1, 0x8e, ++ 0x36, 0xc5, 0x89, 0x54, 0x36, 0x61, 0x49, 0x01, 0xbf, 0x3f, 0xb3, 0x6e, ++ 0xf9, 0xc4, 0x8a, 0x77, 0x6b, 0x8a, 0x88, 0xa6, 0x7d, 0x59, 0x86, 0xb9, ++ 0x73, 0xf0, 0x9d, 0x9a, 0xe2, 0xcf, 0xe4, 0xb9, 0x59, 0xf4, 0x71, 0x1c, ++ 0xbb, 0xb1, 0x48, 0x9e, 0xbf, 0x46, 0xbc, 0x2e, 0xfc, 0xb8, 0xb7, 0xea, ++ 0x9b, 0x19, 0xc9, 0xf7, 0x67, 0x22, 0xd3, 0x91, 0x83, 0x7e, 0xca, 0x2b, ++ 0xbf, 0x5f, 0x44, 0xfa, 0x77, 0xe4, 0x07, 0xae, 0x9b, 0x00, 0x13, 0x35, ++ 0x3a, 0xe3, 0x71, 0x8b, 0xa8, 0x42, 0xaa, 0xdd, 0x36, 0xc0, 0xe3, 0xda, ++ 0x7d, 0x5e, 0x97, 0xc1, 0x5d, 0x0a, 0x58, 0x14, 0xe5, 0x31, 0x72, 0xbb, ++ 0xc1, 0x9b, 0x0d, 0xf8, 0x96, 0xc1, 0xf7, 0x53, 0xb4, 0x93, 0x3e, 0x17, ++ 0x61, 0x9d, 0xa2, 0xc7, 0x26, 0x4f, 0xcc, 0x20, 0x3c, 0xd1, 0xe2, 0x63, ++ 0x3f, 0xd9, 0xe1, 0x72, 0xdd, 0x02, 0xfa, 0x5e, 0x9c, 0xe1, 0x2a, 0x06, ++ 0x0c, 0xad, 0x9f, 0x43, 0xb6, 0x38, 0xe7, 0x13, 0x3d, 0xb7, 0xa2, 0x3f, ++ 0xf4, 0x1d, 0x96, 0x2e, 0xcf, 0x25, 0x45, 0x52, 0xef, 0xcb, 0x8a, 0xa4, ++ 0xff, 0x98, 0xbe, 0x56, 0xde, 0xc7, 0x86, 0xca, 0xbd, 0xac, 0xc8, 0xa0, ++ 0xf9, 0xb7, 0xbf, 0x4f, 0x37, 0xd1, 0x5b, 0x8a, 0xef, 0xe9, 0xf4, 0x8b, ++ 0x2d, 0x8b, 0xb2, 0x41, 0x0f, 0xd1, 0x7b, 0x0f, 0xf6, 0x41, 0xf4, 0x2e, ++ 0x00, 0x14, 0x11, 0x31, 0x5c, 0xef, 0xb8, 0xb6, 0x9e, 0x79, 0xf8, 0x7b, ++ 0x65, 0x45, 0x52, 0xbf, 0xc8, 0x9f, 0x55, 0x7d, 0x22, 0xfd, 0x19, 0xc3, ++ 0x74, 0xa3, 0x77, 0x18, 0xf2, 0xc7, 0x51, 0x0f, 0x78, 0x87, 0x81, 0xde, ++ 0x51, 0x8d, 0x7d, 0x36, 0xfc, 0x3b, 0x8c, 0x67, 0x3d, 0x7d, 0x36, 0xc4, ++ 0xf7, 0x67, 0x57, 0xf7, 0xd9, 0xd0, 0xfe, 0xac, 0x4b, 0xbe, 0x93, 0x0e, ++ 0x5d, 0xbf, 0xb1, 0x48, 0xbe, 0x9f, 0x48, 0x9f, 0xde, 0xc7, 0xf3, 0xc7, ++ 0xd2, 0xb7, 0xba, 0x39, 0x4f, 0xef, 0x1b, 0x86, 0x3c, 0x2a, 0xbd, 0xfc, ++ 0x93, 0xf5, 0xf2, 0xde, 0x25, 0x83, 0xe3, 0xcb, 0x58, 0x2d, 0xbe, 0x8c, ++ 0x7d, 0x20, 0xa5, 0xbd, 0x87, 0xf4, 0x6d, 0xec, 0x93, 0xd1, 0x7c, 0xbf, ++ 0x2d, 0x0a, 0x62, 0xb9, 0xbf, 0xd2, 0x2a, 0xed, 0xb4, 0xf2, 0x81, 0xb2, ++ 0x83, 0x6d, 0x04, 0xc7, 0x6f, 0x23, 0x7a, 0x83, 0xf2, 0xaf, 0x09, 0x5e, ++ 0xa2, 0x7b, 0x50, 0x5e, 0x64, 0xec, 0x97, 0xef, 0x2d, 0x09, 0x07, 0x9f, ++ 0xf6, 0x98, 0x18, 0x87, 0xce, 0x22, 0xbf, 0xaa, 0x11, 0xf2, 0xbd, 0xe5, ++ 0x28, 0xcd, 0x6f, 0x20, 0x6f, 0x2b, 0x25, 0xbf, 0x50, 0x53, 0x7e, 0xe4, ++ 0x12, 0xbf, 0x03, 0xc0, 0x7c, 0xac, 0x8f, 0x3b, 0x5b, 0xe8, 0x5f, 0xbb, ++ 0x49, 0xe2, 0x14, 0xae, 0x71, 0x1e, 0x5d, 0x36, 0x6f, 0x4d, 0x17, 0x9f, ++ 0x0f, 0xb7, 0x5d, 0x69, 0xd7, 0xce, 0x9b, 0xad, 0xeb, 0x71, 0x7e, 0xa6, ++ 0xfc, 0x6d, 0x50, 0x7b, 0x65, 0xd9, 0xe1, 0x2e, 0xc4, 0x9b, 0xaa, 0x3d, ++ 0x83, 0xdb, 0x6b, 0x96, 0x7f, 0xce, 0xe7, 0x58, 0xca, 0xdf, 0x06, 0xb5, ++ 0xdf, 0xf3, 0xd3, 0x0f, 0xf9, 0x9d, 0x4d, 0x5d, 0xfb, 0xe0, 0x76, 0x92, ++ 0xef, 0x53, 0x90, 0xbf, 0x2e, 0xdf, 0xa3, 0x26, 0xdf, 0x04, 0x9c, 0xf7, ++ 0x8e, 0xd6, 0x84, 0x39, 0xe5, 0xbf, 0x1f, 0xf0, 0xad, 0x80, 0xbd, 0x37, ++ 0x55, 0x47, 0xf0, 0xfb, 0xd9, 0x9d, 0xbf, 0xc9, 0x63, 0xbd, 0xd1, 0xe5, ++ 0x4d, 0xf3, 0x9b, 0xbe, 0x9b, 0x7e, 0xac, 0xe5, 0xf1, 0x9e, 0x3c, 0x91, ++ 0x01, 0x7b, 0xf8, 0x36, 0xd8, 0x0b, 0xff, 0x94, 0x36, 0xc8, 0x3f, 0x79, ++ 0xb8, 0xce, 0x37, 0x2b, 0x92, 0xfd, 0x4e, 0x9d, 0x76, 0xbe, 0xaa, 0x2d, ++ 0xb3, 0x73, 0x9c, 0x4f, 0xac, 0xb5, 0xb2, 0xff, 0x2a, 0x54, 0xc3, 0x9c, ++ 0xc0, 0x6b, 0x8d, 0xd2, 0xcf, 0x88, 0x62, 0x55, 0xf3, 0x53, 0x3e, 0xb6, ++ 0xff, 0x13, 0xb7, 0x0d, 0xe3, 0x7a, 0x1e, 0x6f, 0x00, 0x78, 0xcc, 0x24, ++ 0x7e, 0x77, 0x1c, 0xb7, 0x56, 0xe2, 0x7d, 0x23, 0x2c, 0xec, 0x1f, 0x0a, ++ 0x0d, 0x25, 0xd5, 0xbb, 0x09, 0x1e, 0x31, 0x2c, 0x67, 0x3f, 0x90, 0x80, ++ 0x17, 0x97, 0x24, 0xf7, 0x67, 0xe0, 0x1f, 0x54, 0xd8, 0xaf, 0xbc, 0x7f, ++ 0xa8, 0x33, 0xfb, 0x14, 0x79, 0xbf, 0xef, 0xc8, 0xc1, 0x79, 0x57, 0xbf, ++ 0x6f, 0x6a, 0xd8, 0xe8, 0x6d, 0x3d, 0x80, 0xf3, 0xb2, 0xe2, 0x7d, 0x72, ++ 0x29, 0xea, 0x8a, 0x77, 0x44, 0xf0, 0xfd, 0x41, 0x00, 0xf5, 0x46, 0xda, ++ 0x4f, 0xc3, 0x30, 0xe9, 0x47, 0x1b, 0xe6, 0xa7, 0x73, 0x1c, 0x08, 0x88, ++ 0x92, 0xd2, 0x15, 0xc8, 0x43, 0xe6, 0x85, 0x71, 0xfd, 0xb1, 0x61, 0x98, ++ 0xe3, 0x51, 0xdc, 0x27, 0x36, 0x54, 0x4c, 0xe4, 0x3c, 0xfa, 0xe0, 0xdf, ++ 0x64, 0xdc, 0xed, 0x9b, 0x63, 0x75, 0x22, 0x8f, 0x6a, 0x98, 0xec, 0x58, ++ 0x83, 0xf7, 0x2a, 0x0d, 0x0f, 0x38, 0xb8, 0xff, 0x55, 0x45, 0xae, 0xe7, ++ 0x79, 0x54, 0xf2, 0xa7, 0x61, 0x8e, 0xdc, 0x7f, 0x43, 0x45, 0x0c, 0x9f, ++ 0x7b, 0x74, 0x39, 0x34, 0x34, 0xba, 0x46, 0xe2, 0x7e, 0x6a, 0xc6, 0x18, ++ 0xf7, 0x7f, 0x42, 0x6e, 0xa3, 0xb4, 0xfb, 0xb9, 0x86, 0x64, 0x6a, 0x27, ++ 0xf8, 0x84, 0x52, 0x32, 0xff, 0x27, 0x58, 0x67, 0x92, 0xa4, 0x77, 0xd2, ++ 0x0c, 0x07, 0xcb, 0xed, 0xe8, 0xfc, 0x89, 0x8f, 0xee, 0x72, 0x70, 0x38, ++ 0xf1, 0xe3, 0x9e, 0xa8, 0x6e, 0x56, 0xe4, 0xa0, 0x73, 0xf1, 0xff, 0x00, ++ 0x87, 0x51, 0xd9, 0xf6, 0x10, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++}; ++ ++void bnx2x_init_e1h_firmware(struct bnx2x *bp) ++{ ++ INIT_OPS(bp) = (struct raw_op *)init_ops_e1h; ++ INIT_DATA(bp) = (u32 *)init_data_e1h; ++ INIT_OPS_OFFSETS(bp) = (u16 *)init_ops_offsets_e1h; ++ INIT_TSEM_INT_TABLE_DATA(bp) = tsem_int_table_data_e1h; ++ INIT_TSEM_PRAM_DATA(bp) = tsem_pram_data_e1h; ++ INIT_USEM_INT_TABLE_DATA(bp) = usem_int_table_data_e1h; ++ INIT_USEM_PRAM_DATA(bp) = usem_pram_data_e1h; ++ INIT_XSEM_INT_TABLE_DATA(bp) = xsem_int_table_data_e1h; ++ INIT_XSEM_PRAM_DATA(bp) = xsem_pram_data_e1h; ++ INIT_CSEM_INT_TABLE_DATA(bp) = csem_int_table_data_e1h; ++ INIT_CSEM_PRAM_DATA(bp) = csem_pram_data_e1h; ++} ++ +diff -r e67cb9a8e847 drivers/net/bnx2x_link.c +--- a/drivers/net/bnx2x_link.c Wed Aug 05 10:50:39 2009 +0100 ++++ b/drivers/net/bnx2x_link.c Wed Aug 05 10:51:03 2009 +0100 +@@ -20,28 +20,48 @@ + #include + #include + #include ++#ifdef __LINUX_MUTEX_H /* BNX2X_UPSTREAM */ + #include +- +-#include "bnx2x_reg.h" +-#include "bnx2x_fw_defs.h" +-#include "bnx2x_hsi.h" +-#include "bnx2x_link.h" ++#endif ++#include ++ + #include "bnx2x.h" + ++ ++#define E2_PHASE0 1 ++#define CHIP_IS_E2_NOT_PHASE0(_chip_id) (CHIP_IS_E2(bp) && \ ++ !(E2_PHASE0)) + /********************************************************/ +-#define SUPPORT_CL73 0 /* Currently no */ +-#define ETH_HLEN 14 ++#define ETH_HLEN 14 + #define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/ +-#define ETH_MIN_PACKET_SIZE 60 +-#define ETH_MAX_PACKET_SIZE 1500 ++#define ETH_MIN_PACKET_SIZE 60 ++#define ETH_MAX_PACKET_SIZE 1500 + #define ETH_MAX_JUMBO_PACKET_SIZE 9600 +-#define MDIO_ACCESS_TIMEOUT 1000 ++#define MDIO_ACCESS_TIMEOUT 1000 + #define BMAC_CONTROL_RX_ENABLE 2 + ++struct bnx2x_image_header { ++ u32 magic; ++ #define FILE_MAGIC 0x669955aa ++ u32 version; ++ #define FORMAT_VERSION_2 0x2 ++ u32 type; ++ #define IMAGE_HDR_TYPE_BCM8073 0x33373038 ++ #define IMAGE_HDR_TYPE_BCM8726 0x36323738 ++ #define IMAGE_HDR_TYPE_BCM8727 0x37323738 ++ #define IMAGE_HDR_TYPE_BCM8481 0x31383438 ++ #define IMAGE_HDR_TYPE_SFX7101 0x68706673 ++ u32 image_info; ++ u32 byte_cnt; ++}; + /***********************************************************/ +-/* Shortcut definitions */ ++/* Shortcut definitions */ + /***********************************************************/ + ++#define NIG_LATCH_BC_ENABLE_MI_INT 0 ++ ++#define NIG_STATUS_EMAC0_MI_INT \ ++ NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT + #define NIG_STATUS_XGXS0_LINK10G \ + NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G + #define NIG_STATUS_XGXS0_LINK_STATUS \ +@@ -79,11 +99,11 @@ + #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 + #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 + #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM +-#define AUTONEG_PARALLEL \ ++#define AUTONEG_PARALLEL \ + SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION + #define AUTONEG_SGMII_FIBER_AUTODET \ + SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT +-#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY ++#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY + + #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ + MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE +@@ -91,10 +111,10 @@ + MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE + #define GP_STATUS_SPEED_MASK \ + MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK +-#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M +-#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M ++#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M ++#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M + #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G +-#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G ++#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G + #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G + #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G + #define GP_STATUS_10G_HIG \ +@@ -104,17 +124,17 @@ + #define GP_STATUS_12G_HIG \ + MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG + #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G +-#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G +-#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G +-#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G ++#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G ++#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G ++#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G + #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX + #define GP_STATUS_10G_KX4 \ + MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 + +-#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD +-#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD ++#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD ++#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD + #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD +-#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 ++#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 + #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD + #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD + #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD +@@ -122,25 +142,83 @@ + #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD + #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD + #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD +-#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD +-#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD +-#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD +-#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD +-#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD +-#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD +-#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD +-#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD +-#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD +-#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD +-#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD +-#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD +- +-#define PHY_XGXS_FLAG 0x1 +-#define PHY_SGMII_FLAG 0x2 +-#define PHY_SERDES_FLAG 0x4 ++#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD ++#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD ++#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD ++#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD ++#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD ++#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD ++#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD ++#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD ++#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD ++#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD ++#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD ++#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD ++ ++#define PHY_XGXS_FLAG 0x1 ++#define PHY_SGMII_FLAG 0x2 ++#define PHY_SERDES_FLAG 0x4 ++ ++/* */ ++#define SFP_EEPROM_CON_TYPE_ADDR 0x2 ++ #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 ++ #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 ++ ++ ++#define SFP_EEPROM_COMP_CODE_ADDR 0x3 ++ #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) ++ #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) ++ #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) ++ ++#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 ++ #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 ++ #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 ++ ++#define SFP_EEPROM_OPTIONS_ADDR 0x40 ++ #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 ++#define SFP_EEPROM_OPTIONS_SIZE 2 ++ ++#define EDC_MODE_LINEAR 0x0022 ++#define EDC_MODE_LIMITING 0x0044 ++#define EDC_MODE_PASSIVE_DAC 0x0055 ++ + + /**********************************************************/ +-/* INTERFACE */ ++/* 8073 Download definitions */ ++/**********************************************************/ ++/* spi Parameters.*/ ++#define SPI_CTRL_1_L 0xC000 ++#define SPI_CTRL_1_H 0xC002 ++#define SPI_CTRL_2_L 0xC400 ++#define SPI_CTRL_2_H 0xC402 ++#define SPI_TXFIFO 0xD000 ++#define SPI_RXFIFO 0xD400 ++ ++/* Input Command Messages.*/ ++#define WR_CPU_CTRL_REGS 0x11 /* Write CPU/SPI Control Regs, followed ++ by Count And CPU/SPI Controller Reg add/data pairs.*/ ++#define RD_CPU_CTRL_REGS 0xEE /* Read CPU/SPI Control Regs, followed ++by Count and CPU/SPI Controller Register Add.*/ ++#define WR_CPU_CTRL_FIFO 0x66 /* Write CPU/SPI Control Regs ++Continously, followed by Count and CPU/SPI Controller Reg addr and data's.*/ ++/* Output Command Messages.*/ ++#define DONE 0x4321 ++ ++/* SPI Controller Commands (known As messages).*/ ++#define MSGTYPE_HWR 0x40 ++#define MSGTYPE_HRD 0x80 ++#define WRSR_OPCODE 0x01 ++#define WR_OPCODE 0x02 ++#define RD_OPCODE 0x03 ++#define WRDI_OPCODE 0x04 ++#define RDSR_OPCODE 0x05 ++#define WREN_OPCODE 0x06 ++#define WR_BLOCK_SIZE 0x40 /* Maximum 64 Bytes Writes.*/ ++ ++#define BUF_SIZE_BCM 0x4000 /* Code Size is 16k bytes.*/ ++#define UPGRADE_TIMEOUT_BCM 1000 ++/**********************************************************/ ++/* INTERFACE */ + /**********************************************************/ + #define CL45_WR_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \ + bnx2x_cl45_write(_bp, _port, 0, _phy_addr, \ +@@ -154,13 +232,36 @@ + (_bank + (_addr & 0xf)), \ + _val) + +-static void bnx2x_set_phy_mdio(struct link_params *params) +-{ +- struct bnx2x *bp = params->bp; +- REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + +- params->port*0x18, 0); +- REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, +- DEFAULT_PHY_DEV_ADDR); ++static void bnx2x_set_serdes_access(struct link_params *params) ++{ ++ struct bnx2x *bp = params->bp; ++ u32 emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; ++ ++ /* Set Clause 22 */ ++ REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 1); ++ REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); ++ udelay(500); ++ REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); ++ udelay(500); ++ /* Set Clause 45 */ ++ REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 0); ++} ++static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags) ++{ ++ struct bnx2x *bp = params->bp; ++ ++ if (phy_flags & PHY_XGXS_FLAG) { ++ REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + ++ params->port*0x18, 0); ++ REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, ++ DEFAULT_PHY_DEV_ADDR); ++ } else { ++ bnx2x_set_serdes_access(params); ++ ++ REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + ++ params->port*0x10, ++ DEFAULT_PHY_DEV_ADDR); ++ } + } + + static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) +@@ -247,7 +348,6 @@ + } + /* for fpga */ + else +- + if (CHIP_REV_IS_FPGA(bp)) { + /* Use lane 1 (of lanes 0-3) */ + DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n"); +@@ -277,8 +377,10 @@ + port*4, 0); + } + +- /* enable emac */ +- REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); ++ bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, ++ EMAC_RX_MODE_RESET); ++ bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, ++ EMAC_TX_MODE_RESET); + + if (CHIP_REV_IS_SLOW(bp)) { + /* config GMII mode */ +@@ -289,7 +391,7 @@ + /* pause enable/disable */ + bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, + EMAC_RX_MODE_FLOW_EN); +- if (vars->flow_ctrl & FLOW_CTRL_RX) ++ if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) + bnx2x_bits_en(bp, emac_base + + EMAC_REG_EMAC_RX_MODE, + EMAC_RX_MODE_FLOW_EN); +@@ -297,7 +399,7 @@ + bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, + (EMAC_TX_MODE_EXT_PAUSE_EN | + EMAC_TX_MODE_FLOW_EN)); +- if (vars->flow_ctrl & FLOW_CTRL_TX) ++ if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) + bnx2x_bits_en(bp, emac_base + + EMAC_REG_EMAC_TX_MODE, + (EMAC_TX_MODE_EXT_PAUSE_EN | +@@ -336,7 +438,7 @@ + /* enable the NIG in/out to the emac */ + REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); + val = 0; +- if (vars->flow_ctrl & FLOW_CTRL_TX) ++ if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) + val = 1; + + REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); +@@ -357,8 +459,7 @@ + } + + +- +-static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars, ++static u8 bnx2x_bmac1_enable(struct link_params *params, struct link_vars *vars, + u8 is_lb) + { + struct bnx2x *bp = params->bp; +@@ -368,17 +469,7 @@ + u32 wb_data[2]; + u32 val; + +- DP(NETIF_MSG_LINK, "Enabling BigMAC\n"); +- /* reset and unreset the BigMac */ +- REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, +- (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); +- msleep(1); +- +- REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, +- (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); +- +- /* enable access for bmac registers */ +- REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); ++ DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); + + /* XGXS control */ + wb_data[0] = 0x3c; +@@ -399,7 +490,7 @@ + + /* tx control */ + val = 0xc0; +- if (vars->flow_ctrl & FLOW_CTRL_TX) ++ if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) + val |= 0x800000; + wb_data[0] = val; + wb_data[1] = 0; +@@ -417,7 +508,6 @@ + REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, + wb_data, 2); + +- + /* set rx mtu */ + wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; + wb_data[1] = 0; +@@ -426,7 +516,7 @@ + + /* rx control set to don't strip crc */ + val = 0x14; +- if (vars->flow_ctrl & FLOW_CTRL_RX) ++ if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) + val |= 0x20; + wb_data[0] = val; + wb_data[1] = 0; +@@ -459,11 +549,143 @@ + wb_data, 2); + } + ++ ++ return 0; ++} ++ ++static u8 bnx2x_bmac2_enable(struct link_params *params, struct link_vars *vars, ++ u8 is_lb) ++{ ++ struct bnx2x *bp = params->bp; ++ u8 port = params->port; ++ u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : ++ NIG_REG_INGRESS_BMAC0_MEM; ++ u32 wb_data[2]; ++ u32 val; ++ ++ DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); ++ ++ wb_data[0] = 0; ++ wb_data[1] = 0; ++ REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, ++ wb_data, 2); ++ udelay(30); ++ ++ /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ ++ wb_data[0] = 0x3c; ++ wb_data[1] = 0; ++ REG_WR_DMAE(bp, bmac_addr + ++ BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, ++ wb_data, 2); ++ ++ udelay(30); ++ ++ /* tx MAC SA */ ++ wb_data[0] = ((params->mac_addr[2] << 24) | ++ (params->mac_addr[3] << 16) | ++ (params->mac_addr[4] << 8) | ++ params->mac_addr[5]); ++ wb_data[1] = ((params->mac_addr[0] << 8) | ++ params->mac_addr[1]); ++ REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, ++ wb_data, 2); ++ ++ udelay(30); ++ ++ /* Tx control */ ++ val = 0xc0; ++ if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) ++ val |= 0x800000; ++ wb_data[0] = val; ++ wb_data[1] = 0; ++ REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, ++ wb_data, 2); ++ ++ /* Configure SAFC */ ++ wb_data[0] = 0x1000200; ++ wb_data[1] = 0; ++ REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, ++ wb_data, 2); ++ udelay(30); ++ ++ /* set rx mtu */ ++ wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; ++ wb_data[1] = 0; ++ REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, ++ wb_data, 2); ++ udelay(30); ++ ++ /* set tx mtu */ ++ wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; ++ wb_data[1] = 0; ++ REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, ++ wb_data, 2); ++ udelay(30); ++ ++ /* Set rx control: Strip CRC and enable BigMAC to relay ++ control packets to the system as well*/ ++ val = 0x54; ++ if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) ++ val |= 0x20; ++ wb_data[0] = val; ++ wb_data[1] = 0; ++ REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, ++ wb_data, 2); ++ udelay(30); ++ ++ if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { ++ wb_data[0] = 0xb; /* Enable RFC RX & TX and set 8 COS */ ++ wb_data[1] = 0; ++ REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, ++ wb_data, 2); ++ } ++ ++ /* mac control */ ++ val = 0x3; /* Enable RX and TX */ ++ if (is_lb) { ++ val |= 0x4; /* Local loopback */ ++ DP(NETIF_MSG_LINK, "enable bmac loopback\n"); ++ } ++ /* When PFC enabled, Pass pause frames towards the NIG. */ ++ if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) ++ val |= (1<<6); ++ ++ wb_data[0] = val; ++ wb_data[1] = 0; ++ REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, ++ wb_data, 2); ++ ++ return 0; ++} ++ ++static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars, ++ u8 is_lb) ++{ ++ u8 rc, port = params->port; ++ struct bnx2x *bp = params->bp; ++ u32 val; ++ /* reset and unreset the BigMac */ ++ REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, ++ (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); ++ msleep(1); ++ ++ REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, ++ (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); ++ ++ /* enable access for bmac registers */ ++ REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); ++ ++ /* Enable BMAC according to BMAC type*/ ++ if (CHIP_IS_E2_NOT_PHASE0(params->chip_id)) ++ rc = bnx2x_bmac2_enable(params, vars, is_lb); ++ else ++ rc = bnx2x_bmac1_enable(params, vars, is_lb); ++ + REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); + REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); + REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); + val = 0; +- if (vars->flow_ctrl & FLOW_CTRL_TX) ++ if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) + val = 1; + REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); + REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); +@@ -473,7 +695,7 @@ + REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); + + vars->mac_type = MAC_TYPE_BMAC; +- return 0; ++ return rc; + } + + static void bnx2x_phy_deassert(struct link_params *params, u8 phy_flags) +@@ -498,11 +720,11 @@ + udelay(500); + REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, + val); +- bnx2x_set_phy_mdio(params); ++ bnx2x_set_phy_mdio(params, phy_flags); + } + + void bnx2x_link_status_update(struct link_params *params, +- struct link_vars *vars) ++ struct link_vars *vars) + { + struct bnx2x *bp = params->bp; + u8 link_10g; +@@ -583,14 +805,14 @@ + } + + if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) +- vars->flow_ctrl |= FLOW_CTRL_TX; +- else +- vars->flow_ctrl &= ~FLOW_CTRL_TX; ++ vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; ++ else ++ vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_TX; + + if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) +- vars->flow_ctrl |= FLOW_CTRL_RX; +- else +- vars->flow_ctrl &= ~FLOW_CTRL_RX; ++ vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; ++ else ++ vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_RX; + + if (vars->phy_flags & PHY_XGXS_FLAG) { + if (vars->line_speed && +@@ -621,7 +843,7 @@ + + vars->line_speed = 0; + vars->duplex = DUPLEX_FULL; +- vars->flow_ctrl = FLOW_CTRL_NONE; ++ vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; + + /* indicate no mac active */ + vars->mac_type = MAC_TYPE_NONE; +@@ -636,31 +858,45 @@ + static void bnx2x_update_mng(struct link_params *params, u32 link_status) + { + struct bnx2x *bp = params->bp; ++ + REG_WR(bp, params->shmem_base + + offsetof(struct shmem_region, + port_mb[params->port].link_status), + link_status); + } + +-static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port) ++static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u32 chip_id, u8 port) + { + u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : +- NIG_REG_INGRESS_BMAC0_MEM; ++ NIG_REG_INGRESS_BMAC0_MEM; + u32 wb_data[2]; +- u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); ++ u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + ++ port*4); + + /* Only if the bmac is out of reset */ + if (REG_RD(bp, MISC_REG_RESET_REG_2) & + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && + nig_bmac_enable) { + +- /* Clear Rx Enable bit in BMAC_CONTROL register */ +- REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, +- wb_data, 2); +- wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; +- REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, +- wb_data, 2); +- ++ if (CHIP_IS_E2_NOT_PHASE0(chip_id)) { ++ /* Clear Rx Enable bit in BMAC_CONTROL register */ ++ REG_RD_DMAE(bp, bmac_addr + ++ BIGMAC2_REGISTER_BMAC_CONTROL, ++ wb_data, 2); ++ wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; ++ REG_WR_DMAE(bp, bmac_addr + ++ BIGMAC2_REGISTER_BMAC_CONTROL, ++ wb_data, 2); ++ } else { ++ /* Clear Rx Enable bit in BMAC_CONTROL register */ ++ REG_RD_DMAE(bp, bmac_addr + ++ BIGMAC_REGISTER_BMAC_CONTROL, ++ wb_data, 2); ++ wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; ++ REG_WR_DMAE(bp, bmac_addr + ++ BIGMAC_REGISTER_BMAC_CONTROL, ++ wb_data, 2); ++ } + msleep(1); + } + } +@@ -694,7 +930,7 @@ + return -EINVAL; + } + +- if (flow_ctrl & FLOW_CTRL_RX || ++ if (flow_ctrl & BNX2X_FLOW_CTRL_RX || + line_speed == SPEED_10 || + line_speed == SPEED_100 || + line_speed == SPEED_1000 || +@@ -732,7 +968,6 @@ + DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", + line_speed); + return -EINVAL; +- break; + } + } + REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); +@@ -749,12 +984,19 @@ + return 0; + } + +-static u32 bnx2x_get_emac_base(u32 ext_phy_type, u8 port) ++static u32 bnx2x_get_emac_base(struct bnx2x *bp, u32 ext_phy_type, u8 port) + { + u32 emac_base; ++ + switch (ext_phy_type) { + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: +- emac_base = GRCBASE_EMAC0; ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: ++ /* All MDC/MDIO is directed through single EMAC */ ++ if (REG_RD(bp, NIG_REG_PORT_SWAP)) ++ emac_base = GRCBASE_EMAC0; ++ else ++ emac_base = GRCBASE_EMAC1; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: + emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; +@@ -772,11 +1014,12 @@ + { + u32 tmp, saved_mode; + u8 i, rc = 0; +- u32 mdio_ctrl = bnx2x_get_emac_base(ext_phy_type, port); ++ u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port); + + /* set clause 45 mode, slow down the MDIO clock to 2.5MHz + * (a value of 49==0x31) and make sure that the AUTO poll is off + */ ++ + saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); + tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL | + EMAC_MDIO_MODE_CLOCK_CNT); +@@ -841,15 +1084,16 @@ + u16 i; + u8 rc = 0; + +- u32 mdio_ctrl = bnx2x_get_emac_base(ext_phy_type, port); ++ u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port); + /* set clause 45 mode, slow down the MDIO clock to 2.5MHz + * (a value of 49==0x31) and make sure that the AUTO poll is off + */ ++ + saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); + val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL | + EMAC_MDIO_MODE_CLOCK_CNT)); + val |= (EMAC_MDIO_MODE_CLAUSE_45 | +- (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT)); ++ (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT)); + REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val); + REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); + udelay(40); +@@ -907,7 +1151,7 @@ + } + + static void bnx2x_set_aer_mmd(struct link_params *params, +- struct link_vars *vars) ++ struct link_vars *vars) + { + struct bnx2x *bp = params->bp; + u32 ser_lane; +@@ -966,6 +1210,8 @@ + MDIO_COMBO_IEEE0_MII_CONTROL, + (mii_control | + MDIO_COMBO_IEEO_MII_CONTROL_RESET)); ++ if (params->switch_cfg == SWITCH_CFG_1G) ++ bnx2x_set_serdes_access(params); + + /* wait for the reset to self clear */ + for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { +@@ -1037,7 +1283,7 @@ + } + + static void bnx2x_set_parallel_detection(struct link_params *params, +- u8 phy_flags) ++ u8 phy_flags) + { + struct bnx2x *bp = params->bp; + u16 control2; +@@ -1094,7 +1340,8 @@ + } + + static void bnx2x_set_autoneg(struct link_params *params, +- struct link_vars *vars) ++ struct link_vars *vars, ++ u8 enable_cl73) + { + struct bnx2x *bp = params->bp; + u16 reg_val; +@@ -1156,18 +1403,27 @@ + MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, + reg_val); + +- /* Enable Clause 73 Aneg */ +- if ((vars->line_speed == SPEED_AUTO_NEG) && +- (SUPPORT_CL73)) { +- /* Enable BAM Station Manager */ +- +- CL45_WR_OVER_CL22(bp, params->port, ++ if (enable_cl73) { ++ ++ /* Enable BAM Station Manager*/ ++ CL45_RD_OVER_CL22(bp, params->port, + params->phy_addr, + MDIO_REG_BANK_CL73_USERB0, +- MDIO_CL73_USERB0_CL73_BAM_CTRL1, +- (MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | ++ 0x10, ++ ®_val); ++ CL45_WR_OVER_CL22(bp, params->port, ++ params->phy_addr, ++ MDIO_REG_BANK_CL73_USERB0, ++ 0x10, ++ reg_val | 0x2); ++ ++ CL45_WR_OVER_CL22(bp, params->port, ++ params->phy_addr, ++ MDIO_REG_BANK_CL73_USERB0, ++ MDIO_CL73_USERB0_CL73_BAM_CTRL1, ++ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | + MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | +- MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN)); ++ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); + + /* Merge CL73 and CL37 aneg resolution */ + CL45_RD_OVER_CL22(bp, params->port, +@@ -1176,42 +1432,26 @@ + MDIO_CL73_USERB0_CL73_BAM_CTRL3, + ®_val); + +- CL45_WR_OVER_CL22(bp, params->port, +- params->phy_addr, +- MDIO_REG_BANK_CL73_USERB0, +- MDIO_CL73_USERB0_CL73_BAM_CTRL3, +- (reg_val | +- MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR)); + + /* Set the CL73 AN speed */ +- + CL45_RD_OVER_CL22(bp, params->port, + params->phy_addr, + MDIO_REG_BANK_CL73_IEEEB1, +- MDIO_CL73_IEEEB1_AN_ADV2, ®_val); +- /* In the SerDes we support only the 1G. +- In the XGXS we support the 10G KX4 +- but we currently do not support the KR */ +- if (vars->phy_flags & PHY_XGXS_FLAG) { +- DP(NETIF_MSG_LINK, "XGXS\n"); +- /* 10G KX4 */ +- reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; +- } else { +- DP(NETIF_MSG_LINK, "SerDes\n"); +- /* 1000M KX */ +- reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; +- } +- CL45_WR_OVER_CL22(bp, params->port, +- params->phy_addr, +- MDIO_REG_BANK_CL73_IEEEB1, +- MDIO_CL73_IEEEB1_AN_ADV2, reg_val); ++ MDIO_CL73_IEEEB1_AN_ADV2, ++ ®_val); ++ ++ CL45_WR_OVER_CL22(bp, params->port, ++ params->phy_addr, ++ MDIO_REG_BANK_CL73_IEEEB1, ++ MDIO_CL73_IEEEB1_AN_ADV2, ++ reg_val | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4); + + /* CL73 Autoneg Enabled */ + reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; +- } else { +- /* CL73 Autoneg Disabled */ ++ ++ } else /* CL73 Autoneg Disabled */ + reg_val = 0; +- } ++ + CL45_WR_OVER_CL22(bp, params->port, + params->phy_addr, + MDIO_REG_BANK_CL73_IEEEB0, +@@ -1296,15 +1536,15 @@ + MDIO_OVER_1G_UP3, 0); + } + +-static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc) ++static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u16 *ieee_fc) + { + *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; + /* resolve pause mode and advertisement + * Please refer to Table 28B-3 of the 802.3ab-1999 spec */ + + switch (params->req_flow_ctrl) { +- case FLOW_CTRL_AUTO: +- if (params->req_fc_auto_adv == FLOW_CTRL_BOTH) { ++ case BNX2X_FLOW_CTRL_AUTO: ++ if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) { + *ieee_fc |= + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; + } else { +@@ -1312,17 +1552,17 @@ + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; + } + break; +- case FLOW_CTRL_TX: ++ case BNX2X_FLOW_CTRL_TX: + *ieee_fc |= + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; + break; + +- case FLOW_CTRL_RX: +- case FLOW_CTRL_BOTH: ++ case BNX2X_FLOW_CTRL_RX: ++ case BNX2X_FLOW_CTRL_BOTH: + *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; + break; + +- case FLOW_CTRL_NONE: ++ case BNX2X_FLOW_CTRL_NONE: + default: + *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; + break; +@@ -1330,7 +1570,7 @@ + } + + static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params, +- u32 ieee_fc) ++ u16 ieee_fc) + { + struct bnx2x *bp = params->bp; + /* for AN, we are always publishing full duplex */ +@@ -1338,33 +1578,32 @@ + CL45_WR_OVER_CL22(bp, params->port, + params->phy_addr, + MDIO_REG_BANK_COMBO_IEEE0, +- MDIO_COMBO_IEEE0_AUTO_NEG_ADV, (u16)ieee_fc); +-} +- +-static void bnx2x_restart_autoneg(struct link_params *params) +-{ +- struct bnx2x *bp = params->bp; ++ MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); ++} ++ ++static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73) ++{ ++ struct bnx2x *bp = params->bp; ++ u16 mii_control; ++ + DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); +- if (SUPPORT_CL73) { +- /* enable and restart clause 73 aneg */ +- u16 an_ctrl; +- ++ /* Enable and restart BAM/CL37 aneg */ ++ ++ if (enable_cl73) { + CL45_RD_OVER_CL22(bp, params->port, + params->phy_addr, + MDIO_REG_BANK_CL73_IEEEB0, + MDIO_CL73_IEEEB0_CL73_AN_CONTROL, +- &an_ctrl); +- CL45_WR_OVER_CL22(bp, params->port, +- params->phy_addr, ++ &mii_control); ++ ++ CL45_WR_OVER_CL22(bp, params->port, ++ params->phy_addr, + MDIO_REG_BANK_CL73_IEEEB0, + MDIO_CL73_IEEEB0_CL73_AN_CONTROL, +- (an_ctrl | ++ (mii_control | + MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | + MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); +- +- } else { +- /* Enable and restart BAM/CL37 aneg */ +- u16 mii_control; ++ } else { + + CL45_RD_OVER_CL22(bp, params->port, + params->phy_addr, +@@ -1379,8 +1618,8 @@ + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_MII_CONTROL, + (mii_control | +- MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | +- MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); ++ MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | ++ MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); + } + } + +@@ -1453,7 +1692,7 @@ + + } else { /* AN mode */ + /* enable and restart AN */ +- bnx2x_restart_autoneg(params); ++ bnx2x_restart_autoneg(params, 0); + } + } + +@@ -1466,18 +1705,18 @@ + { /* LD LP */ + switch (pause_result) { /* ASYM P ASYM P */ + case 0xb: /* 1 0 1 1 */ +- vars->flow_ctrl = FLOW_CTRL_TX; ++ vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; + break; + + case 0xe: /* 1 1 1 0 */ +- vars->flow_ctrl = FLOW_CTRL_RX; ++ vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; + break; + + case 0x5: /* 0 1 0 1 */ + case 0x7: /* 0 1 1 1 */ + case 0xd: /* 1 1 0 1 */ + case 0xf: /* 1 1 1 1 */ +- vars->flow_ctrl = FLOW_CTRL_BOTH; ++ vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; + break; + + default: +@@ -1490,17 +1729,14 @@ + { + struct bnx2x *bp = params->bp; + u8 ext_phy_addr; +- u16 ld_pause; /* local */ +- u16 lp_pause; /* link partner */ ++ u16 ld_pause; /* local */ ++ u16 lp_pause; /* link partner */ + u16 an_complete; /* AN complete */ + u16 pause_result; + u8 ret = 0; + u32 ext_phy_type; + u8 port = params->port; +- ext_phy_addr = ((params->ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); +- ++ ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); + ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); + /* read twice */ + +@@ -1534,7 +1770,7 @@ + DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n", + pause_result); + bnx2x_pause_resolve(vars, pause_result); +- if (vars->flow_ctrl == FLOW_CTRL_NONE && ++ if (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE && + ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { + bnx2x_cl45_read(bp, port, + ext_phy_type, +@@ -1570,10 +1806,10 @@ + u16 lp_pause; /* link partner */ + u16 pause_result; + +- vars->flow_ctrl = FLOW_CTRL_NONE; ++ vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; + + /* resolve from gp_status in case of AN complete and not sgmii */ +- if ((params->req_flow_ctrl == FLOW_CTRL_AUTO) && ++ if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) && + (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && + (!(vars->phy_flags & PHY_SGMII_FLAG)) && + (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == +@@ -1594,11 +1830,11 @@ + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; + DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result); + bnx2x_pause_resolve(vars, pause_result); +- } else if ((params->req_flow_ctrl == FLOW_CTRL_AUTO) && ++ } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) && + (bnx2x_ext_phy_resove_fc(params, vars))) { + return; + } else { +- if (params->req_flow_ctrl == FLOW_CTRL_AUTO) ++ if (params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) + vars->flow_ctrl = params->req_fc_auto_adv; + else + vars->flow_ctrl = params->req_flow_ctrl; +@@ -1608,8 +1844,8 @@ + + + static u8 bnx2x_link_settings_status(struct link_params *params, +- struct link_vars *vars, +- u32 gp_status) ++ struct link_vars *vars, ++ u32 gp_status) + { + struct bnx2x *bp = params->bp; + u16 new_line_speed; +@@ -1670,7 +1906,7 @@ + "link speed unsupported gp_status 0x%x\n", + gp_status); + return -EINVAL; +- break; ++ + case GP_STATUS_10G_KX4: + case GP_STATUS_10G_HIG: + case GP_STATUS_10G_CX4: +@@ -1707,8 +1943,7 @@ + DP(NETIF_MSG_LINK, + "link speed unsupported gp_status 0x%x\n", + gp_status); +- return -EINVAL; +- break; ++ return -EINVAL; + } + + /* Upon link speed change set the NIG into drain mode. +@@ -1726,7 +1961,9 @@ + ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) || + (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705))) { ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) || ++ (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) { + vars->autoneg = AUTO_NEG_ENABLED; + + if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) { +@@ -1740,11 +1977,11 @@ + LINK_STATUS_PARALLEL_DETECTION_USED; + + } +- if (vars->flow_ctrl & FLOW_CTRL_TX) ++ if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) + vars->link_status |= + LINK_STATUS_TX_FLOW_CONTROL_ENABLED; + +- if (vars->flow_ctrl & FLOW_CTRL_RX) ++ if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) + vars->link_status |= + LINK_STATUS_RX_FLOW_CONTROL_ENABLED; + +@@ -1754,7 +1991,7 @@ + vars->phy_link_up = 0; + + vars->duplex = DUPLEX_FULL; +- vars->flow_ctrl = FLOW_CTRL_NONE; ++ vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; + vars->autoneg = AUTO_NEG_DISABLED; + vars->mac_type = MAC_TYPE_NONE; + } +@@ -1770,38 +2007,44 @@ + return rc; + } + +-static void bnx2x_set_sgmii_tx_driver(struct link_params *params) ++static void bnx2x_set_gmii_tx_driver(struct link_params *params) + { + struct bnx2x *bp = params->bp; + u16 lp_up2; + u16 tx_driver; ++ u16 bank; + + /* read precomp */ +- + CL45_RD_OVER_CL22(bp, params->port, + params->phy_addr, + MDIO_REG_BANK_OVER_1G, + MDIO_OVER_1G_LP_UP2, &lp_up2); +- +- CL45_RD_OVER_CL22(bp, params->port, +- params->phy_addr, +- MDIO_REG_BANK_TX0, +- MDIO_TX0_TX_DRIVER, &tx_driver); + + /* bits [10:7] at lp_up2, positioned at [15:12] */ + lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> + MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << + MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); + +- if ((lp_up2 != 0) && +- (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK))) { ++ if (lp_up2 == 0) ++ return; ++ ++ for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; ++ bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { ++ CL45_RD_OVER_CL22(bp, params->port, ++ params->phy_addr, ++ bank, ++ MDIO_TX0_TX_DRIVER, &tx_driver); ++ + /* replace tx_driver bits [15:12] */ +- tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; +- tx_driver |= lp_up2; +- CL45_WR_OVER_CL22(bp, params->port, +- params->phy_addr, +- MDIO_REG_BANK_TX0, +- MDIO_TX0_TX_DRIVER, tx_driver); ++ if (lp_up2 != ++ (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { ++ tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; ++ tx_driver |= lp_up2; ++ CL45_WR_OVER_CL22(bp, params->port, ++ params->phy_addr, ++ bank, ++ MDIO_TX0_TX_DRIVER, tx_driver); ++ } + } + } + +@@ -1855,23 +2098,22 @@ + /*****************************************************************************/ + /* External Phy section */ + /*****************************************************************************/ +-static void bnx2x_hw_reset(struct bnx2x *bp, u8 port) ++void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) + { + bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, +- MISC_REGISTERS_GPIO_OUTPUT_LOW, port); ++ MISC_REGISTERS_GPIO_OUTPUT_LOW, port); + msleep(1); + bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, +- MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); ++ MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); + } + + static void bnx2x_ext_phy_reset(struct link_params *params, +- struct link_vars *vars) +-{ +- struct bnx2x *bp = params->bp; +- u32 ext_phy_type; +- u8 ext_phy_addr = ((params->ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); ++ struct link_vars *vars) ++{ ++ struct bnx2x *bp = params->bp; ++ u32 ext_phy_type; ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); ++ + DP(NETIF_MSG_LINK, "Port %x: bnx2x_ext_phy_reset\n", params->port); + ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); + /* The PHY reset is controled by GPIO 1 +@@ -1890,11 +2132,11 @@ + + /* Restore normal power mode*/ + bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, +- MISC_REGISTERS_GPIO_OUTPUT_HIGH, ++ MISC_REGISTERS_GPIO_OUTPUT_HIGH, + params->port); + + /* HW reset */ +- bnx2x_hw_reset(bp, params->port); ++ bnx2x_ext_phy_hw_reset(bp, params->port); + + bnx2x_cl45_write(bp, params->port, + ext_phy_type, +@@ -1902,14 +2144,38 @@ + MDIO_PMA_DEVAD, + MDIO_PMA_REG_CTRL, 0xa040); + break; ++ ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: ++ break; ++ ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: ++ ++ /* Restore normal power mode*/ ++ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, ++ MISC_REGISTERS_GPIO_OUTPUT_HIGH, ++ params->port); ++ ++ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, ++ MISC_REGISTERS_GPIO_OUTPUT_HIGH, ++ params->port); ++ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_CTRL, ++ 1<<15); ++ break; ++ + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: ++ DP(NETIF_MSG_LINK, "XGXS 8072\n"); ++ + /* Unset Low Power Mode and SW reset */ + /* Restore normal power mode*/ + bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_HIGH, + params->port); + +- DP(NETIF_MSG_LINK, "XGXS 8072\n"); + bnx2x_cl45_write(bp, params->port, + ext_phy_type, + ext_phy_addr, +@@ -1917,23 +2183,18 @@ + MDIO_PMA_REG_CTRL, + 1<<15); + break; ++ + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: +- { +- u16 emac_base; +- emac_base = (params->port) ? GRCBASE_EMAC0 : +- GRCBASE_EMAC1; ++ DP(NETIF_MSG_LINK, "XGXS 8073\n"); + + /* Restore normal power mode*/ + bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, +- MISC_REGISTERS_GPIO_OUTPUT_HIGH, ++ MISC_REGISTERS_GPIO_OUTPUT_HIGH, + params->port); + + bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, +- MISC_REGISTERS_GPIO_OUTPUT_HIGH, +- params->port); +- +- DP(NETIF_MSG_LINK, "XGXS 8073\n"); +- } ++ MISC_REGISTERS_GPIO_OUTPUT_HIGH, ++ params->port); + break; + + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: +@@ -1941,21 +2202,36 @@ + + /* Restore normal power mode*/ + bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, +- MISC_REGISTERS_GPIO_OUTPUT_HIGH, ++ MISC_REGISTERS_GPIO_OUTPUT_HIGH, + params->port); + + /* HW reset */ +- bnx2x_hw_reset(bp, params->port); +- +- break; +- ++ bnx2x_ext_phy_hw_reset(bp, params->port); ++ break; ++ ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: ++ /* Restore normal power mode*/ ++ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, ++ MISC_REGISTERS_GPIO_OUTPUT_HIGH, ++ params->port); ++ ++ /* HW reset */ ++ bnx2x_ext_phy_hw_reset(bp, params->port); ++ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_CTRL, ++ 1<<15); ++ break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: + DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n"); + break; + + default: + DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n", +- params->ext_phy_config); ++ params->ext_phy_config); + break; + } + +@@ -1968,27 +2244,153 @@ + + case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482: + DP(NETIF_MSG_LINK, "SerDes 5482\n"); +- bnx2x_hw_reset(bp, params->port); +- break; +- +- default: +- DP(NETIF_MSG_LINK, +- "BAD SerDes ext_phy_config 0x%x\n", ++ bnx2x_ext_phy_hw_reset(bp, params->port); ++ break; ++ ++ default: ++ DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n", + params->ext_phy_config); + break; + } + } + } + ++static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, ++ u32 shmem_base, u32 spirom_ver) ++{ ++ DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x\n", ++ (u16)(spirom_ver>>16), (u16)spirom_ver); ++ REG_WR(bp, shmem_base + ++ offsetof(struct shmem_region, ++ port_mb[port].ext_phy_fw_version), ++ spirom_ver); ++} ++ ++static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, u8 port, ++ u32 ext_phy_type, u8 ext_phy_addr, ++ u32 shmem_base) ++{ ++ u16 fw_ver1, fw_ver2; ++ ++ bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_ROM_VER1, &fw_ver1); ++ bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_ROM_VER2, &fw_ver2); ++ bnx2x_save_spirom_version(bp, port, shmem_base, ++ (u32)(fw_ver1<<16 | fw_ver2)); ++} ++ ++ ++static void bnx2x_save_8481_spirom_version(struct bnx2x *bp, u8 port, ++ u8 ext_phy_addr, u32 shmem_base) ++{ ++ u16 val, fw_ver1, fw_ver2, cnt; ++ /* For the 32 bits registers in 8481, access via MDIO2ARM interface.*/ ++ /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ 0xA819, 0x0014); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ 0xA81A, ++ 0xc200); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ 0xA81B, ++ 0x0000); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ 0xA81C, ++ 0x0300); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ 0xA817, ++ 0x0009); ++ ++ for (cnt = 0; cnt < 100; cnt++) { ++ bnx2x_cl45_read(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ 0xA818, ++ &val); ++ if (val & 1) ++ break; ++ udelay(5); ++ } ++ if (cnt == 100) { ++ DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(1)\n"); ++ bnx2x_save_spirom_version(bp, port, ++ shmem_base, 0); ++ return; ++ } ++ ++ ++ /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ 0xA819, 0x0000); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ 0xA81A, 0xc200); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ 0xA817, 0x000A); ++ for (cnt = 0; cnt < 100; cnt++) { ++ bnx2x_cl45_read(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ 0xA818, ++ &val); ++ if (val & 1) ++ break; ++ udelay(5); ++ } ++ if (cnt == 100) { ++ DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(2)\n"); ++ bnx2x_save_spirom_version(bp, port, ++ shmem_base, 0); ++ return; ++ } ++ ++ /* lower 16 bits of the register SPI_FW_STATUS */ ++ bnx2x_cl45_read(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ 0xA81B, ++ &fw_ver1); ++ /* upper 16 bits of register SPI_FW_STATUS */ ++ bnx2x_cl45_read(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ 0xA81C, ++ &fw_ver2); ++ ++ bnx2x_save_spirom_version(bp, port, ++ shmem_base, (fw_ver2<<16) | fw_ver1); ++} ++ + static void bnx2x_bcm8072_external_rom_boot(struct link_params *params) + { + struct bnx2x *bp = params->bp; + u8 port = params->port; +- u8 ext_phy_addr = ((params->ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); +- u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); +- u16 fw_ver1, fw_ver2; ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); ++ u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); + + /* Need to wait 200ms after reset */ + msleep(200); +@@ -1996,42 +2398,38 @@ + * Set ser_boot_ctl bit in the MISC_CTRL1 register + */ + bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_MISC_CTRL1, 0x0001); ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_MISC_CTRL1, 0x0001); + + /* Reset internal microprocessor */ + bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_GEN_CTRL, +- MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_GEN_CTRL, ++ MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); + /* set micro reset = 0 */ + bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_GEN_CTRL, +- MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_GEN_CTRL, ++ MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); + /* Reset internal microprocessor */ + bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_GEN_CTRL, +- MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_GEN_CTRL, ++ MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); + /* wait for 100ms for code download via SPI port */ + msleep(100); + + /* Clear ser_boot_ctl bit */ + bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_MISC_CTRL1, 0x0000); ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_MISC_CTRL1, 0x0000); + /* Wait 100ms */ + msleep(100); + +- /* Print the PHY FW version */ +- bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_ROM_VER1, &fw_ver1); +- bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_ROM_VER2, &fw_ver2); +- DP(NETIF_MSG_LINK, "8072 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2); ++ bnx2x_save_bcm_spirom_ver(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ params->shmem_base); + } + + static u8 bnx2x_8073_is_snr_needed(struct link_params *params) +@@ -2039,9 +2437,7 @@ + /* This is only required for 8073A1, version 102 only */ + + struct bnx2x *bp = params->bp; +- u8 ext_phy_addr = ((params->ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); + u16 val; + + /* Read 8073 HW revision*/ +@@ -2049,7 +2445,7 @@ + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, + MDIO_PMA_DEVAD, +- 0xc801, &val); ++ MDIO_PMA_REG_8073_CHIP_REV, &val); + + if (val != 1) { + /* No need to workaround in 8073 A1 */ +@@ -2072,16 +2468,14 @@ + static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params) + { + struct bnx2x *bp = params->bp; +- u8 ext_phy_addr = ((params->ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); + u16 val, cnt, cnt1 ; + + bnx2x_cl45_read(bp, params->port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, + MDIO_PMA_DEVAD, +- 0xc801, &val); ++ MDIO_PMA_REG_8073_CHIP_REV, &val); + + if (val > 0) { + /* No need to workaround in 8073 A1 */ +@@ -2097,7 +2491,8 @@ + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, + MDIO_PMA_DEVAD, +- 0xc820, &val); ++ MDIO_PMA_REG_8073_SPEED_LINK_STATUS, ++ &val); + /* If bit [14] = 0 or bit [13] = 0, continue on with + system initialization (XAUI work-around not required, + as these bits indicate 2.5G or 1G link up). */ +@@ -2115,7 +2510,7 @@ + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, + MDIO_PMA_DEVAD, +- 0xc841, &val); ++ MDIO_PMA_REG_8073_XAUI_WA, &val); + if (val & (1<<15)) { + DP(NETIF_MSG_LINK, + "XAUI workaround has completed\n"); +@@ -2129,17 +2524,17 @@ + } + DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); + return -EINVAL; +- +-} +- +-static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port, +- u8 ext_phy_addr) +-{ +- u16 fw_ver1, fw_ver2; ++} ++ ++static void bnx2x_bcm8073_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port, ++ u8 ext_phy_addr, ++ u32 ext_phy_type, ++ u32 shmem_base) ++{ + /* Boot port from external ROM */ + /* EDC grst */ + bnx2x_cl45_write(bp, port, +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ++ ext_phy_type, + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_GEN_CTRL, +@@ -2147,21 +2542,21 @@ + + /* ucode reboot and rst */ + bnx2x_cl45_write(bp, port, +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ++ ext_phy_type, + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_GEN_CTRL, + 0x008c); + + bnx2x_cl45_write(bp, port, +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ++ ext_phy_type, + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_MISC_CTRL1, 0x0001); + + /* Reset internal microprocessor */ + bnx2x_cl45_write(bp, port, +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ++ ext_phy_type, + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_GEN_CTRL, +@@ -2169,7 +2564,7 @@ + + /* Release srst bit */ + bnx2x_cl45_write(bp, port, +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ++ ext_phy_type, + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_GEN_CTRL, +@@ -2180,31 +2575,750 @@ + + /* Clear ser_boot_ctl bit */ + bnx2x_cl45_write(bp, port, +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ++ ext_phy_type, + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_MISC_CTRL1, 0x0000); + +- bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_ROM_VER1, &fw_ver1); +- bnx2x_cl45_read(bp, port, +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_ROM_VER2, &fw_ver2); +- DP(NETIF_MSG_LINK, "8073 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2); +- ++ bnx2x_save_bcm_spirom_ver(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ shmem_base); ++} ++ ++static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port, ++ u8 ext_phy_addr, ++ u32 shmem_base) ++{ ++ bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ++ shmem_base); ++} ++ ++static void bnx2x_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port, ++ u8 ext_phy_addr, ++ u32 shmem_base) ++{ ++ bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ shmem_base); ++ ++} ++ ++static void bnx2x_bcm8726_external_rom_boot(struct link_params *params) ++{ ++ struct bnx2x *bp = params->bp; ++ u8 port = params->port; ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); ++ u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); ++ ++ /* Need to wait 100ms after reset */ ++ msleep(100); ++ ++ /* Set serial boot control for external load */ ++ bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_MISC_CTRL1, 0x0001); ++ ++ /* Micro controller re-boot */ ++ bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_GEN_CTRL, ++ MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); ++ ++ /* Set soft reset */ ++ bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_GEN_CTRL, ++ MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); ++ ++ /* Set PLL register value to be same like in P13 ver */ ++ bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PLL_CTRL, ++ 0x73A0); ++ ++ /* Clear soft reset. ++ Will automatically reset micro-controller re-boot */ ++ bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_GEN_CTRL, ++ MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); ++ ++ /* wait for 150ms for microcode load */ ++ msleep(150); ++ ++ /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ ++ bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_MISC_CTRL1, 0x0000); ++ ++ msleep(200); ++ bnx2x_save_bcm_spirom_ver(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ params->shmem_base); ++} ++ ++static void bnx2x_sfp_set_transmitter(struct bnx2x *bp, u8 port, ++ u32 ext_phy_type, u8 ext_phy_addr, ++ u8 tx_en) ++{ ++ u16 val; ++ ++ DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n", ++ tx_en, port); ++ /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, ++ &val); ++ ++ if (tx_en) ++ val &= ~(1<<15); ++ else ++ val |= (1<<15); ++ ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, ++ val); ++} ++ ++static u8 bnx2x_8726_read_sfp_module_eeprom(struct link_params *params, ++ u16 addr, u8 byte_cnt, u8 *o_buf) ++{ ++ struct bnx2x *bp = params->bp; ++ u16 val = 0; ++ u16 i; ++ u8 port = params->port; ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); ++ u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); ++ ++ if (byte_cnt > 16) { ++ DP(NETIF_MSG_LINK, "Reading from eeprom is" ++ " is limited to 0xf\n"); ++ return -EINVAL; ++ } ++ /* Set the read command byte count */ ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, ++ (byte_cnt | 0xa000)); ++ ++ /* Set the read command address */ ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, ++ addr); ++ ++ /* Activate read command */ ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, ++ 0x2c0f); ++ ++ /* Wait up to 500us for command complete status */ ++ for (i = 0; i < 100; i++) { ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); ++ if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == ++ MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) ++ break; ++ udelay(5); ++ } ++ ++ if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != ++ MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { ++ DP(NETIF_MSG_LINK, ++ "Got bad status 0x%x when reading from SFP+ EEPROM\n", ++ (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); ++ return -EINVAL; ++ } ++ ++ /* Read the buffer */ ++ for (i = 0; i < byte_cnt; i++) { ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); ++ o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); ++ } ++ ++ for (i = 0; i < 100; i++) { ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); ++ if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == ++ MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) ++ return 0;; ++ msleep(1); ++ } ++ return -EINVAL; ++} ++ ++static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params, ++ u16 addr, u8 byte_cnt, u8 *o_buf) ++{ ++ struct bnx2x *bp = params->bp; ++ u16 val, i; ++ u8 port = params->port; ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); ++ u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); ++ ++ if (byte_cnt > 16) { ++ DP(NETIF_MSG_LINK, "Reading from eeprom is" ++ " is limited to 0xf\n"); ++ return -EINVAL; ++ } ++ ++ /* Need to read from 1.8000 to clear it */ ++ bnx2x_cl45_read(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, ++ &val); ++ ++ /* Set the read command byte count */ ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, ++ ((byte_cnt < 2) ? 2 : byte_cnt)); ++ ++ /* Set the read command address */ ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, ++ addr); ++ /* Set the destination address */ ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ 0x8004, ++ MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); ++ ++ /* Activate read command */ ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, ++ 0x8002); ++ /* Wait appropriate time for two-wire command to finish before ++ polling the status register */ ++ msleep(1); ++ ++ /* Wait up to 500us for command complete status */ ++ for (i = 0; i < 100; i++) { ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); ++ if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == ++ MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) ++ break; ++ udelay(5); ++ } ++ ++ if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != ++ MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { ++ DP(NETIF_MSG_LINK, ++ "Got bad status 0x%x when reading from SFP+ EEPROM\n", ++ (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); ++ return -EINVAL; ++ } ++ ++ /* Read the buffer */ ++ for (i = 0; i < byte_cnt; i++) { ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); ++ o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); ++ } ++ ++ for (i = 0; i < 100; i++) { ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); ++ if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == ++ MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) ++ return 0;; ++ msleep(1); ++ } ++ ++ return -EINVAL; ++} ++ ++u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr, ++ u8 byte_cnt, u8 *o_buf) ++{ ++ u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); ++ ++ if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ++ return bnx2x_8726_read_sfp_module_eeprom(params, addr, ++ byte_cnt, o_buf); ++ else if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ++ return bnx2x_8727_read_sfp_module_eeprom(params, addr, ++ byte_cnt, o_buf); ++ return -EINVAL; ++} ++ ++static u8 bnx2x_get_edc_mode(struct link_params *params, ++ u16 *edc_mode) ++{ ++ struct bnx2x *bp = params->bp; ++ u8 val, check_limiting_mode = 0; ++ *edc_mode = EDC_MODE_LIMITING; ++ ++ /* First check for copper cable */ ++ if (bnx2x_read_sfp_module_eeprom(params, ++ SFP_EEPROM_CON_TYPE_ADDR, ++ 1, ++ &val) != 0) { ++ DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); ++ return -EINVAL; ++ } ++ ++ switch (val) { ++ case SFP_EEPROM_CON_TYPE_VAL_COPPER: ++ { ++ u8 copper_module_type; ++ ++ /* Check if its active cable( includes SFP+ module) ++ of passive cable*/ ++ if (bnx2x_read_sfp_module_eeprom(params, ++ SFP_EEPROM_FC_TX_TECH_ADDR, ++ 1, ++ &copper_module_type) != ++ 0) { ++ DP(NETIF_MSG_LINK, ++ "Failed to read copper-cable-type" ++ " from SFP+ EEPROM\n"); ++ return -EINVAL; ++ } ++ ++ if (copper_module_type & ++ SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { ++ DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); ++ check_limiting_mode = 1; ++ } else if (copper_module_type & ++ SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { ++ DP(NETIF_MSG_LINK, "Passive Copper" ++ " cable detected\n"); ++ *edc_mode = ++ EDC_MODE_PASSIVE_DAC; ++ } else { ++ DP(NETIF_MSG_LINK, "Unknown copper-cable-" ++ "type 0x%x !!!\n", copper_module_type); ++ return -EINVAL; ++ } ++ break; ++ } ++ case SFP_EEPROM_CON_TYPE_VAL_LC: ++ DP(NETIF_MSG_LINK, "Optic module detected\n"); ++ check_limiting_mode = 1; ++ break; ++ default: ++ DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", ++ val); ++ return -EINVAL; ++ } ++ ++ if (check_limiting_mode) { ++ u8 options[SFP_EEPROM_OPTIONS_SIZE]; ++ if (bnx2x_read_sfp_module_eeprom(params, ++ SFP_EEPROM_OPTIONS_ADDR, ++ SFP_EEPROM_OPTIONS_SIZE, ++ options) != 0) { ++ DP(NETIF_MSG_LINK, "Failed to read Option" ++ " field from module EEPROM\n"); ++ return -EINVAL; ++ } ++ if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) ++ *edc_mode = EDC_MODE_LINEAR; ++ else ++ *edc_mode = EDC_MODE_LIMITING; ++ } ++ DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); ++ return 0; ++} ++ ++/* This function read the relevant field from the module ( SFP+ ), ++ and verify it is compliant with this board */ ++static u8 bnx2x_verify_sfp_module(struct link_params *params) ++{ ++ struct bnx2x *bp = params->bp; ++ u32 val; ++ u32 fw_resp; ++ char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; ++ char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; ++ ++ val = REG_RD(bp, params->shmem_base + ++ offsetof(struct shmem_region, dev_info. ++ port_feature_config[params->port].config)); ++ if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == ++ PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { ++ DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); ++ return 0; ++ } ++ ++ /* Ask the FW to validate the module */ ++ if (!(params->feature_config_flags & ++ FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY)) { ++ DP(NETIF_MSG_LINK, "FW does not support OPT MDL " ++ "verification\n"); ++ return -EINVAL; ++ } ++ ++ fw_resp = bnx2x_fw_command(bp, DRV_MSG_CODE_VRFY_OPT_MDL); ++ if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { ++ DP(NETIF_MSG_LINK, "Approved module\n"); ++ return 0; ++ } ++ ++ /* format the warning message */ ++ if (bnx2x_read_sfp_module_eeprom(params, ++ SFP_EEPROM_VENDOR_NAME_ADDR, ++ SFP_EEPROM_VENDOR_NAME_SIZE, ++ (u8 *)vendor_name)) ++ vendor_name[0] = '\0'; ++ else ++ vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; ++ if (bnx2x_read_sfp_module_eeprom(params, ++ SFP_EEPROM_PART_NO_ADDR, ++ SFP_EEPROM_PART_NO_SIZE, ++ (u8 *)vendor_pn)) ++ vendor_pn[0] = '\0'; ++ else ++ vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; ++ ++ printk(KERN_INFO PFX "Warning: " ++ "Unqualified SFP+ module " ++ "detected on %s, Port %d from %s part number %s\n" ++ , bp->dev->name, params->port, ++ vendor_name, vendor_pn); ++ return -EINVAL; ++} ++ ++static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params, ++ u16 edc_mode) ++{ ++ struct bnx2x *bp = params->bp; ++ u8 port = params->port; ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); ++ u16 cur_limiting_mode; ++ ++ bnx2x_cl45_read(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_ROM_VER2, ++ &cur_limiting_mode); ++ DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", ++ cur_limiting_mode); ++ ++ if (edc_mode == EDC_MODE_LIMITING) { ++ DP(NETIF_MSG_LINK, ++ "Setting LIMITING MODE\n"); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_ROM_VER2, ++ EDC_MODE_LIMITING); ++ } else { /* LRM mode ( default )*/ ++ ++ DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); ++ ++ /* Changing to LRM mode takes quite few seconds. ++ So do it only if current mode is limiting ++ ( default is LRM )*/ ++ if (cur_limiting_mode != EDC_MODE_LIMITING) ++ return 0; ++ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_LRM_MODE, ++ 0); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_ROM_VER2, ++ 0x128); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_MISC_CTRL0, ++ 0x4008); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_LRM_MODE, ++ 0xaaaa); ++ } ++ return 0; ++} ++ ++static u8 bnx2x_bcm8727_set_limiting_mode(struct link_params *params, ++ u16 edc_mode) ++{ ++ struct bnx2x *bp = params->bp; ++ u8 port = params->port; ++ u16 phy_identifier; ++ u16 rom_ver2_val; ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); ++ ++ bnx2x_cl45_read(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, ++ &phy_identifier); ++ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, ++ (phy_identifier & ~(1<<9))); ++ ++ bnx2x_cl45_read(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_ROM_VER2, ++ &rom_ver2_val); ++ /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_ROM_VER2, ++ (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); ++ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, ++ (phy_identifier | (1<<9))); ++ ++ return 0; ++} ++ ++ ++static u8 bnx2x_wait_for_sfp_module_initialized(struct link_params *params) ++{ ++ u8 val; ++ struct bnx2x *bp = params->bp; ++ u16 timeout; ++ /* Initialization time after hot-plug may take up to 300ms for some ++ phys type ( e.g. JDSU ) */ ++ for (timeout = 0; timeout < 60; timeout++) { ++ if (bnx2x_read_sfp_module_eeprom(params, 1, 1, &val) ++ == 0) { ++ DP(NETIF_MSG_LINK, "SFP+ module initialization " ++ "took %d ms\n", timeout * 5); ++ return 0; ++ } ++ msleep(5); ++ } ++ return -EINVAL; ++} ++ ++static void bnx2x_8727_power_module(struct bnx2x *bp, ++ struct link_params *params, ++ u8 ext_phy_addr, u8 is_power_up) { ++ /* Make sure GPIOs are not using for LED mode */ ++ u16 val; ++ u8 port = params->port; ++ /* ++ * In the GPIO register, bit 4 is use to detemine if the GPIOs are ++ * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for ++ * output ++ * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0 ++ * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1 ++ * where the 1st bit is the over-current(only input), and 2nd bit is ++ * for power( only output ) ++ */ ++ ++ /* ++ * In case of NOC feature is disabled and power is up, set GPIO control ++ * as input to enable listening of over-current indication ++ */ ++ ++ if (!(params->feature_config_flags & ++ FEATURE_CONFIG_BCM8727_NOC) && is_power_up) ++ val = (1<<4); ++ else ++ /* ++ * Set GPIO control to OUTPUT, and set the power bit ++ * to according to the is_power_up ++ */ ++ val = ((!(is_power_up)) << 1); ++ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8727_GPIO_CTRL, ++ val); ++} ++ ++static u8 bnx2x_sfp_module_detection(struct link_params *params) ++{ ++ struct bnx2x *bp = params->bp; ++ u16 edc_mode; ++ u8 rc = 0; ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); ++ u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); ++ u32 val = REG_RD(bp, params->shmem_base + ++ offsetof(struct shmem_region, dev_info. ++ port_feature_config[params->port].config)); ++ ++ DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", ++ params->port); ++ ++ if (bnx2x_get_edc_mode(params, &edc_mode) != 0) { ++ DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); ++ return -EINVAL; ++ } else if (bnx2x_verify_sfp_module(params) != ++ 0) { ++ /* check SFP+ module compatibility */ ++ DP(NETIF_MSG_LINK, "Module verification failed!!\n"); ++ rc = -EINVAL; ++ /* Turn on fault module-detected led */ ++ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, ++ MISC_REGISTERS_GPIO_HIGH, ++ params->port); ++ if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) && ++ ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == ++ PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) { ++ /* Shutdown SFP+ module */ ++ DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); ++ bnx2x_8727_power_module(bp, params, ++ ext_phy_addr, 0); ++ return rc; ++ } ++ } else { ++ /* Turn off fault module-detected led */ ++ DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n"); ++ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, ++ MISC_REGISTERS_GPIO_LOW, ++ params->port); ++ } ++ ++ /* power up the SFP module */ ++ if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ++ bnx2x_8727_power_module(bp, params, ext_phy_addr, 1); ++ ++ /* Check and set limiting mode / LRM mode on 8726. ++ On 8727 it is done automatically */ ++ if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ++ bnx2x_bcm8726_set_limiting_mode(params, edc_mode); ++ else ++ bnx2x_bcm8727_set_limiting_mode(params, edc_mode); ++ /* ++ * Enable transmit for this module if the module is approved, or ++ * if unapproved modules should also enable the Tx laser ++ */ ++ if (rc == 0 || ++ (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != ++ PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ++ bnx2x_sfp_set_transmitter(bp, params->port, ++ ext_phy_type, ext_phy_addr, 1); ++ else ++ bnx2x_sfp_set_transmitter(bp, params->port, ++ ext_phy_type, ext_phy_addr, 0); ++ ++ return rc; ++} ++ ++void bnx2x_handle_module_detect_int(struct link_params *params) ++{ ++ struct bnx2x *bp = params->bp; ++ u32 gpio_val; ++ u8 port = params->port; ++ ++ /* Set valid module led off */ ++ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, ++ MISC_REGISTERS_GPIO_HIGH, ++ params->port); ++ ++ /* Get current gpio val refelecting module plugged in / out*/ ++ gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port); ++ ++ /* Call the handling function in case module is detected */ ++ if (gpio_val == 0) { ++ ++ bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3, ++ MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, ++ port); ++ ++ if (bnx2x_wait_for_sfp_module_initialized(params) == ++ 0) ++ bnx2x_sfp_module_detection(params); ++ else ++ DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); ++ } else { ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); ++ ++ u32 ext_phy_type = ++ XGXS_EXT_PHY_TYPE(params->ext_phy_config); ++ u32 val = REG_RD(bp, params->shmem_base + ++ offsetof(struct shmem_region, dev_info. ++ port_feature_config[params->port]. ++ config)); ++ ++ bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3, ++ MISC_REGISTERS_GPIO_INT_OUTPUT_SET, ++ port); ++ /* Module was plugged out. */ ++ /* Disable transmit for this module */ ++ if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == ++ PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ++ bnx2x_sfp_set_transmitter(bp, params->port, ++ ext_phy_type, ext_phy_addr, 0); ++ } + } + + static void bnx2x_bcm807x_force_10G(struct link_params *params) + { + struct bnx2x *bp = params->bp; + u8 port = params->port; +- u8 ext_phy_addr = ((params->ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); + u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); + + /* Force KR or KX */ +@@ -2225,21 +3339,20 @@ + MDIO_AN_REG_CTRL, + 0x0000); + } ++ + static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params) + { + struct bnx2x *bp = params->bp; + u8 port = params->port; + u16 val; +- u8 ext_phy_addr = ((params->ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); + u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); + + bnx2x_cl45_read(bp, params->port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, + MDIO_PMA_DEVAD, +- 0xc801, &val); ++ MDIO_PMA_REG_8073_CHIP_REV, &val); + + if (val == 0) { + /* Mustn't set low power mode in 8073 A0 */ +@@ -2284,22 +3397,19 @@ + + /* Enable PLL sequencer (use read-modify-write to set bit 13) */ + bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, +- MDIO_XS_DEVAD, +- MDIO_XS_PLL_SEQUENCER, &val); ++ MDIO_XS_DEVAD, ++ MDIO_XS_PLL_SEQUENCER, &val); + val |= (1<<13); + bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, + MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val); + } + + static void bnx2x_8073_set_pause_cl37(struct link_params *params, +- struct link_vars *vars) +-{ +- ++ struct link_vars *vars) ++{ + struct bnx2x *bp = params->bp; + u16 cl37_val; +- u8 ext_phy_addr = ((params->ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); + u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); + + bnx2x_cl45_read(bp, params->port, +@@ -2342,9 +3452,7 @@ + { + struct bnx2x *bp = params->bp; + u16 val; +- u8 ext_phy_addr = ((params->ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); + u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); + + /* read modify write pause advertizing */ +@@ -2377,38 +3485,49 @@ + MDIO_AN_DEVAD, + MDIO_AN_REG_ADV_PAUSE, val); + } +- ++static void bnx2x_set_preemphasis(struct link_params *params) ++{ ++ u16 bank, i = 0; ++ struct bnx2x *bp = params->bp; ++ ++ for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; ++ bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { ++ CL45_WR_OVER_CL22(bp, params->port, ++ params->phy_addr, ++ bank, ++ MDIO_RX0_RX_EQ_BOOST, ++ params->xgxs_config_rx[i]); ++ } ++ ++ for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; ++ bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { ++ CL45_WR_OVER_CL22(bp, params->port, ++ params->phy_addr, ++ bank, ++ MDIO_TX0_TX_DRIVER, ++ params->xgxs_config_tx[i]); ++ } ++} + + static void bnx2x_init_internal_phy(struct link_params *params, +- struct link_vars *vars) +-{ +- struct bnx2x *bp = params->bp; +- u8 port = params->port; ++ struct link_vars *vars, ++ u8 enable_cl73) ++{ ++ struct bnx2x *bp = params->bp; ++ + if (!(vars->phy_flags & PHY_SGMII_FLAG)) { +- u16 bank, rx_eq; +- +- rx_eq = ((params->serdes_config & +- PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >> +- PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT); +- +- DP(NETIF_MSG_LINK, "setting rx eq to 0x%x\n", rx_eq); +- for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL; +- bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0)) { +- CL45_WR_OVER_CL22(bp, port, +- params->phy_addr, +- bank , +- MDIO_RX0_RX_EQ_BOOST, +- ((rx_eq & +- MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) | +- MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL)); +- } ++ if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) == ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && ++ (params->feature_config_flags & ++ FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) ++ bnx2x_set_preemphasis(params); + + /* forced speed requested? */ + if (vars->line_speed != SPEED_AUTO_NEG) { + DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); + + /* disable autoneg */ +- bnx2x_set_autoneg(params, vars); ++ bnx2x_set_autoneg(params, vars, 0); + + /* program speed and duplex */ + bnx2x_program_serdes(params, vars); +@@ -2424,10 +3543,10 @@ + vars->ieee_fc); + + /* enable autoneg */ +- bnx2x_set_autoneg(params, vars); ++ bnx2x_set_autoneg(params, vars, enable_cl73); + + /* enable and restart AN */ +- bnx2x_restart_autoneg(params); ++ bnx2x_restart_autoneg(params, enable_cl73); + } + + } else { /* SGMII mode */ +@@ -2446,10 +3565,9 @@ + u16 ctrl = 0; + u16 val = 0; + u8 rc = 0; ++ + if (vars->phy_flags & PHY_XGXS_FLAG) { +- ext_phy_addr = ((params->ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); ++ ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); + + ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); + /* Make sure that the soft reset is off (expect for the 8072: +@@ -2506,12 +3624,53 @@ + ext_phy_addr, + MDIO_WIS_DEVAD, + MDIO_WIS_REG_LASI_CNTL, 0x1); ++ ++ /* BCM8705 doesn't have microcode, hence the 0 */ ++ bnx2x_save_spirom_version(bp, params->port, ++ params->shmem_base, 0); + break; + + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: +- DP(NETIF_MSG_LINK, "XGXS 8706\n"); +- +- msleep(10); ++ /* Wait until fw is loaded */ ++ for (cnt = 0; cnt < 100; cnt++) { ++ bnx2x_cl45_read(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_ROM_VER1, &val); ++ if (val) ++ break; ++ msleep(10); ++ } ++ DP(NETIF_MSG_LINK, "XGXS 8706 is initialized " ++ "after %d ms\n", cnt); ++ if ((params->feature_config_flags & ++ FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { ++ u8 i; ++ u16 reg; ++ for (i = 0; i < 4; i++) { ++ reg = MDIO_XS_8706_REG_BANK_RX0 + ++ i*(MDIO_XS_8706_REG_BANK_RX1 - ++ MDIO_XS_8706_REG_BANK_RX0); ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_XS_DEVAD, ++ reg, &val); ++ /* Clear first 3 bits of the control */ ++ val &= ~0x7; ++ /* Set control bits according to ++ configuation */ ++ val |= (params->xgxs_config_rx[i] & ++ 0x7); ++ DP(NETIF_MSG_LINK, "Setting RX" ++ "Equalizer to BCM8706 reg 0x%x" ++ " <-- val 0x%x\n", reg, val); ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_XS_DEVAD, ++ reg, val); ++ } ++ } + /* Force speed */ + /* First enable LASI */ + bnx2x_cl45_write(bp, params->port, +@@ -2534,7 +3693,7 @@ + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_DIGITAL_CTRL, +- 0x400); ++ 0x400); + } else { + /* Force 1Gbps using autoneg with 1G + advertisment */ +@@ -2578,9 +3737,98 @@ + 0x1200); + + } +- +- break; +- ++ bnx2x_save_bcm_spirom_ver(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ params->shmem_base); ++ break; ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: ++ DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); ++ bnx2x_bcm8726_external_rom_boot(params); ++ ++ /* Need to call module detected on initialization since ++ the module detection triggered by actual module ++ insertion might occur before driver is loaded, and when ++ driver is loaded, it reset all registers, including the ++ transmitter */ ++ bnx2x_sfp_module_detection(params); ++ ++ /* Set Flow control */ ++ bnx2x_ext_phy_set_pause(params, vars); ++ if (params->req_line_speed == SPEED_1000) { ++ DP(NETIF_MSG_LINK, "Setting 1G force\n"); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_CTRL, 0x40); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_10G_CTRL2, 0xD); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_LASI_CTRL, 0x5); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM_CTRL, ++ 0x400); ++ } else if ((params->req_line_speed == ++ SPEED_AUTO_NEG) && ++ ((params->speed_cap_mask & ++ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) { ++ DP(NETIF_MSG_LINK, "Setting 1G clause37 \n"); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_AN_DEVAD, ++ MDIO_AN_REG_ADV, 0x20); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_AN_DEVAD, ++ MDIO_AN_REG_CL37_CL73, 0x040c); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_AN_DEVAD, ++ MDIO_AN_REG_CL37_FC_LD, 0x0020); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_AN_DEVAD, ++ MDIO_AN_REG_CL37_AN, 0x1000); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_AN_DEVAD, ++ MDIO_AN_REG_CTRL, 0x1200); ++ ++ /* Enable RX-ALARM control to receive ++ interrupt for 1G speed change */ ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_LASI_CTRL, 0x4); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM_CTRL, ++ 0x400); ++ ++ } else { /* Default 10G. Set only LASI control */ ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_LASI_CTRL, 1); ++ } ++ ++ /* Set TX PreEmphasis if needed */ ++ if ((params->feature_config_flags & ++ FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { ++ DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x," ++ "TX_CTRL2 0x%x\n", ++ params->xgxs_config_tx[0], ++ params->xgxs_config_tx[1]); ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8726_TX_CTRL1, ++ params->xgxs_config_tx[0]); ++ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8726_TX_CTRL2, ++ params->xgxs_config_tx[1]); ++ } ++ break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: + { +@@ -2598,11 +3846,11 @@ + + /* enable LASI */ + bnx2x_cl45_write(bp, params->port, +- ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_RX_ALARM_CTRL, +- rx_alarm_ctrl_val); ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM_CTRL, ++ rx_alarm_ctrl_val); + + bnx2x_cl45_write(bp, params->port, + ext_phy_type, +@@ -2614,20 +3862,18 @@ + bnx2x_8073_set_pause_cl37(params, vars); + + if (ext_phy_type == +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){ ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) + bnx2x_bcm8072_external_rom_boot(params); +- } else { +- ++ else + /* In case of 8073 with long xaui lines, + don't set the 8073 xaui low power*/ + bnx2x_bcm8073_set_xaui_low_power_mode(params); +- } +- +- bnx2x_cl45_read(bp, params->port, +- ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- 0xca13, ++ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_M8051_MSGOUT_REG, + &tmp1); + + bnx2x_cl45_read(bp, params->port, +@@ -2686,15 +3932,13 @@ + ext_phy_addr, + MDIO_AN_DEVAD, + MDIO_AN_REG_ADV, val); +- + if (ext_phy_type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { +- +- bnx2x_cl45_read(bp, params->port, +- ext_phy_type, +- ext_phy_addr, +- MDIO_AN_DEVAD, +- 0x8329, &tmp1); ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_8073_2_5G, &tmp1); + + if (((params->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && +@@ -2708,7 +3952,7 @@ + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, + MDIO_PMA_DEVAD, +- 0xc801, &phy_ver); ++ MDIO_PMA_REG_8073_CHIP_REV, &phy_ver); + DP(NETIF_MSG_LINK, "Add 2.5G\n"); + if (phy_ver > 0) + tmp1 |= 1; +@@ -2723,7 +3967,7 @@ + ext_phy_type, + ext_phy_addr, + MDIO_AN_DEVAD, +- 0x8329, tmp1); ++ MDIO_AN_REG_8073_2_5G, tmp1); + } + + /* Add support for CL37 (passive mode) II */ +@@ -2797,7 +4041,190 @@ + ((val & (1<<7)) > 0)); + break; + } ++ ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: ++ { ++ u16 tmp1; ++ u16 rx_alarm_ctrl_val; ++ u16 lasi_ctrl_val; ++ ++ /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ ++ ++ u16 mod_abs; ++ rx_alarm_ctrl_val = (1<<2) | (1<<5) ; ++ lasi_ctrl_val = 0x0004; ++ ++ DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); ++ /* enable LASI */ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM_CTRL, ++ rx_alarm_ctrl_val); ++ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_LASI_CTRL, ++ lasi_ctrl_val); ++ ++ /* Initially configure MOD_ABS to interrupt when ++ module is presence( bit 8) */ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); ++ /* Set EDC off by setting OPTXLOS signal input to low ++ (bit 9). ++ When the EDC is off it locks onto a reference clock and ++ avoids becoming 'lost'.*/ ++ mod_abs &= ~((1<<8) | (1<<9)); ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); ++ ++ /* Make MOD_ABS give interrupt on change */ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8727_PCS_OPT_CTRL, ++ &val); ++ val |= (1<<12); ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8727_PCS_OPT_CTRL, ++ val); ++ ++ /* Set 8727 GPIOs to input to allow reading from the ++ 8727 GPIO0 status which reflect SFP+ module ++ over-current */ ++ ++ bnx2x_cl45_read(bp, params->port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8727_PCS_OPT_CTRL, ++ &val); ++ val &= 0xff8f; /* Reset bits 4-6 */ ++ bnx2x_cl45_write(bp, params->port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8727_PCS_OPT_CTRL, ++ val); ++ ++ bnx2x_8727_power_module(bp, params, ext_phy_addr, 1); ++ bnx2x_bcm8073_set_xaui_low_power_mode(params); ++ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_M8051_MSGOUT_REG, ++ &tmp1); ++ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM, &tmp1); ++ ++ /* Set option 1G speed */ ++ if (params->req_line_speed == SPEED_1000) { ++ ++ DP(NETIF_MSG_LINK, "Setting 1G force\n"); ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_CTRL, 0x40); ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_10G_CTRL2, 0xD); ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_10G_CTRL2, &tmp1); ++ DP(NETIF_MSG_LINK, "1.7 = 0x%x \n", tmp1); ++ ++ } else if ((params->req_line_speed == ++ SPEED_AUTO_NEG) && ++ ((params->speed_cap_mask & ++ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) { ++ ++ DP(NETIF_MSG_LINK, "Setting 1G clause37 \n"); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_AN_DEVAD, ++ MDIO_PMA_REG_8727_MISC_CTRL, 0); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_AN_DEVAD, ++ MDIO_AN_REG_CL37_AN, 0x1300); ++ } else { ++ /* Since the 8727 has only single reset pin, ++ need to set the 10G registers although it is ++ default */ ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_AN_DEVAD, ++ MDIO_AN_REG_CTRL, 0x0020); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_AN_DEVAD, ++ 0x7, 0x0100); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_CTRL, 0x2040); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_10G_CTRL2, 0x0008); ++ } ++ ++ /* Set 2-wire transfer rate to 400Khz since 100Khz ++ is not operational */ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, ++ 0xa101); ++ ++ /* Set TX PreEmphasis if needed */ ++ if ((params->feature_config_flags & ++ FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { ++ DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x," ++ "TX_CTRL2 0x%x\n", ++ params->xgxs_config_tx[0], ++ params->xgxs_config_tx[1]); ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8727_TX_CTRL1, ++ params->xgxs_config_tx[0]); ++ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8727_TX_CTRL2, ++ params->xgxs_config_tx[1]); ++ } ++ ++ break; ++ } ++ + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: ++ { ++ u16 fw_ver1, fw_ver2; + DP(NETIF_MSG_LINK, + "Setting the SFX7101 LASI indication\n"); + +@@ -2827,6 +4254,248 @@ + ext_phy_addr, + MDIO_AN_DEVAD, + MDIO_AN_REG_CTRL, val); ++ ++ /* Save spirom version */ ++ bnx2x_cl45_read(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_7101_VER1, &fw_ver1); ++ ++ bnx2x_cl45_read(bp, params->port, ext_phy_type, ++ ext_phy_addr, MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_7101_VER2, &fw_ver2); ++ ++ bnx2x_save_spirom_version(params->bp, params->port, ++ params->shmem_base, ++ (u32)(fw_ver1<<16 | fw_ver2)); ++ break; ++ } ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: ++ DP(NETIF_MSG_LINK, ++ "Setting the BCM8481 LASI control\n"); ++ /* This phy uses the NIG latch mechanism since link ++ indication arrives through its LED4 and not via ++ its LASI signal, so we get steady signal ++ instead of clear on read */ ++ bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, ++ 1 << NIG_LATCH_BC_ENABLE_MI_INT); ++ ++ /* Enable LED4 when link speed is 10/100/1000 */ ++ /* Bit 15 enables write to the shadow reg */ ++ /* Bits 10..14 sets the shadow reg to LED selector 2 */ ++ /* Bits 4..7 Set the LED2 selector itself to LED4 */ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_8481_LEGACY_SHADOW, ++ (1<<15) | (0xe << 10) | (0xc << 4)); ++ /* Enable continous signal to go active on link */ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8481_LINK_SIGNAL, &val); ++ val &= ~(1<<11); ++ val |= (2<<9); ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8481_LINK_SIGNAL, val); ++ /* Unmask LED4 for 10G link */ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8481_SIGNAL_MASK, &val); ++ val |= (1<<7); ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8481_SIGNAL_MASK, val); ++ ++ if (params->req_line_speed == SPEED_AUTO_NEG) { ++ ++ u16 autoneg_val, an_1000_val, an_10_100_val; ++ /* set 1000 speed advertisement */ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_8481_1000T_CTRL, ++ &an_1000_val); ++ ++ if (params->speed_cap_mask & ++ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) { ++ an_1000_val |= (1<<8); ++ if (params->req_duplex == DUPLEX_FULL) ++ an_1000_val |= (1<<9); ++ DP(NETIF_MSG_LINK, "Advertising 1G\n"); ++ } else ++ an_1000_val &= ~((1<<8) | (1<<9)); ++ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_8481_1000T_CTRL, ++ an_1000_val); ++ ++ /* set 100 speed advertisement */ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_8481_LEGACY_AN_ADV, ++ &an_10_100_val); ++ ++ if (params->speed_cap_mask & ++ (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | ++ PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) { ++ an_10_100_val |= (1<<7); ++ if (params->req_duplex == DUPLEX_FULL) ++ an_10_100_val |= (1<<8); ++ DP(NETIF_MSG_LINK, ++ "Advertising 100M\n"); ++ } else ++ an_10_100_val &= ~((1<<7) | (1<<8)); ++ ++ /* set 10 speed advertisement */ ++ if (params->speed_cap_mask & ++ (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | ++ PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) { ++ an_10_100_val |= (1<<5); ++ if (params->req_duplex == DUPLEX_FULL) ++ an_10_100_val |= (1<<6); ++ DP(NETIF_MSG_LINK, "Advertising 10M\n"); ++ } ++ else ++ an_10_100_val &= ~((1<<5) | (1<<6)); ++ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_8481_LEGACY_AN_ADV, ++ an_10_100_val); ++ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_8481_LEGACY_MII_CTRL, ++ &autoneg_val); ++ ++ /* Disable forced speed */ ++ autoneg_val &= ~(1<<6|1<<13); ++ ++ /* Enable autoneg and restart autoneg ++ for legacy speeds */ ++ autoneg_val |= (1<<9|1<<12); ++ ++ if (params->req_duplex == DUPLEX_FULL) ++ autoneg_val |= (1<<8); ++ else ++ autoneg_val &= ~(1<<8); ++ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_8481_LEGACY_MII_CTRL, ++ autoneg_val); ++ ++ if (params->speed_cap_mask & ++ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) { ++ DP(NETIF_MSG_LINK, "Advertising 10G\n"); ++ /* Restart autoneg for 10G*/ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_CTRL, &val); ++ val |= 0x200; ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_CTRL, val); ++ } ++ } else { ++ /* Force speed */ ++ u16 autoneg_ctrl, pma_ctrl; ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_8481_LEGACY_MII_CTRL, ++ &autoneg_ctrl); ++ ++ /* Disable autoneg */ ++ autoneg_ctrl &= ~(1<<12); ++ ++ /* Set 1000 force */ ++ switch (params->req_line_speed) { ++ case SPEED_10000: ++ DP(NETIF_MSG_LINK, ++ "Unable to set 10G force !\n"); ++ break; ++ case SPEED_1000: ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_CTRL, ++ &pma_ctrl); ++ autoneg_ctrl &= ~(1<<13); ++ autoneg_ctrl |= (1<<6); ++ pma_ctrl &= ~(1<<13); ++ pma_ctrl |= (1<<6); ++ DP(NETIF_MSG_LINK, ++ "Setting 1000M force\n"); ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_CTRL, ++ pma_ctrl); ++ break; ++ case SPEED_100: ++ autoneg_ctrl |= (1<<13); ++ autoneg_ctrl &= ~(1<<6); ++ DP(NETIF_MSG_LINK, ++ "Setting 100M force\n"); ++ break; ++ case SPEED_10: ++ autoneg_ctrl &= ~(1<<13); ++ autoneg_ctrl &= ~(1<<6); ++ DP(NETIF_MSG_LINK, ++ "Setting 10M force\n"); ++ break; ++ } ++ ++ /* Duplex mode */ ++ if (params->req_duplex == DUPLEX_FULL) { ++ autoneg_ctrl |= (1<<8); ++ DP(NETIF_MSG_LINK, ++ "Setting full duplex\n"); ++ } else ++ autoneg_ctrl &= ~(1<<8); ++ ++ /* Update autoneg ctrl and pma ctrl */ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_8481_LEGACY_MII_CTRL, ++ autoneg_ctrl); ++ } ++ ++ /* Save spirom version */ ++ bnx2x_save_8481_spirom_version(bp, params->port, ++ ext_phy_addr, ++ params->shmem_base); + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: + DP(NETIF_MSG_LINK, +@@ -2860,6 +4529,97 @@ + } + } + return rc; ++} ++ ++static void bnx2x_8727_handle_mod_abs(struct link_params *params) ++{ ++ struct bnx2x *bp = params->bp; ++ u16 mod_abs, rx_alarm_status; ++ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); ++ u32 val = REG_RD(bp, params->shmem_base + ++ offsetof(struct shmem_region, dev_info. ++ port_feature_config[params->port]. ++ config)); ++ bnx2x_cl45_read(bp, params->port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); ++ if (mod_abs & (1<<8)) { ++ ++ /* Module is absent */ ++ DP(NETIF_MSG_LINK, "MOD_ABS indication " ++ "show module is absent\n"); ++ ++ /* 1. Set mod_abs to detect next module ++ presence event ++ 2. Set EDC off by setting OPTXLOS signal input to low ++ (bit 9). ++ When the EDC is off it locks onto a reference clock and ++ avoids becoming 'lost'.*/ ++ mod_abs &= ~((1<<8)|(1<<9)); ++ bnx2x_cl45_write(bp, params->port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); ++ ++ /* Clear RX alarm since it stays up as long as ++ the mod_abs wasn't changed */ ++ bnx2x_cl45_read(bp, params->port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); ++ ++ } else { ++ /* Module is present */ ++ DP(NETIF_MSG_LINK, "MOD_ABS indication " ++ "show module is present\n"); ++ /* First thing, disable transmitter, ++ and if the module is ok, the ++ module_detection will enable it*/ ++ ++ /* 1. Set mod_abs to detect next module ++ absent event ( bit 8) ++ 2. Restore the default polarity of the OPRXLOS signal and ++ this signal will then correctly indicate the presence or ++ absence of the Rx signal. (bit 9) */ ++ mod_abs |= ((1<<8)|(1<<9)); ++ bnx2x_cl45_write(bp, params->port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); ++ ++ /* Clear RX alarm since it stays up as long as ++ the mod_abs wasn't changed. This is need to be done ++ before calling the module detection, otherwise it will clear ++ the link update alarm */ ++ bnx2x_cl45_read(bp, params->port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); ++ ++ ++ if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == ++ PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ++ bnx2x_sfp_set_transmitter(bp, params->port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, 0); ++ ++ if (bnx2x_wait_for_sfp_module_initialized(params) ++ == 0) ++ bnx2x_sfp_module_detection(params); ++ else ++ DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); ++ } ++ ++ DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", ++ rx_alarm_status); ++ /* No need to check link status in case of ++ module plugged in/out */ + } + + +@@ -2873,11 +4633,9 @@ + u16 rx_sd, pcs_status; + u8 ext_phy_link_up = 0; + u8 port = params->port; ++ + if (vars->phy_flags & PHY_XGXS_FLAG) { +- ext_phy_addr = ((params->ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); +- ++ ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); + ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); + switch (ext_phy_type) { + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: +@@ -2903,45 +4661,61 @@ + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_RX_SD, &rx_sd); +- DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd); +- ext_phy_link_up = (rx_sd & 0x1); ++ ++ bnx2x_cl45_read(bp, params->port, ext_phy_type, ++ ext_phy_addr, ++ 1, ++ 0xc809, &val1); ++ bnx2x_cl45_read(bp, params->port, ext_phy_type, ++ ext_phy_addr, ++ 1, ++ 0xc809, &val1); ++ ++ DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); ++ ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) ++ && ((val1 & (1<<8)) == 0)); + if (ext_phy_link_up) + vars->line_speed = SPEED_10000; + break; + + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: +- DP(NETIF_MSG_LINK, "XGXS 8706\n"); +- bnx2x_cl45_read(bp, params->port, ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_LASI_STATUS, &val1); +- DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1); +- +- bnx2x_cl45_read(bp, params->port, ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_LASI_STATUS, &val1); +- DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1); +- +- bnx2x_cl45_read(bp, params->port, ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_RX_SD, &rx_sd); +- bnx2x_cl45_read(bp, params->port, ext_phy_type, +- ext_phy_addr, +- MDIO_PCS_DEVAD, +- MDIO_PCS_REG_STATUS, &pcs_status); +- +- bnx2x_cl45_read(bp, params->port, ext_phy_type, +- ext_phy_addr, +- MDIO_AN_DEVAD, +- MDIO_AN_REG_LINK_STATUS, &val2); +- bnx2x_cl45_read(bp, params->port, ext_phy_type, +- ext_phy_addr, +- MDIO_AN_DEVAD, +- MDIO_AN_REG_LINK_STATUS, &val2); +- +- DP(NETIF_MSG_LINK, "8706 rx_sd 0x%x" ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: ++ DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); ++ /* Clear RX Alarm*/ ++ bnx2x_cl45_read(bp, params->port, ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, ++ &val2); ++ /* clear LASI indication*/ ++ bnx2x_cl45_read(bp, params->port, ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, ++ &val1); ++ bnx2x_cl45_read(bp, params->port, ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, ++ &val2); ++ DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x-->" ++ "0x%x\n", val1, val2); ++ ++ bnx2x_cl45_read(bp, params->port, ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, ++ &rx_sd); ++ bnx2x_cl45_read(bp, params->port, ext_phy_type, ++ ext_phy_addr, ++ MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, ++ &pcs_status); ++ bnx2x_cl45_read(bp, params->port, ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, ++ &val2); ++ bnx2x_cl45_read(bp, params->port, ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, ++ &val2); ++ ++ DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x" + " pcs_status 0x%x 1Gbps link_status 0x%x\n", + rx_sd, pcs_status, val2); + /* link is up if both bit 0 of pmd_rx_sd and +@@ -2951,40 +4725,203 @@ + ext_phy_link_up = ((rx_sd & pcs_status & 0x1) || + (val2 & (1<<1))); + if (ext_phy_link_up) { ++ if (ext_phy_type == ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { ++ /* If transmitter is disabled, ++ ignore false link up indication */ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, ++ &val1); ++ if (val1 & (1<<15)) { ++ DP(NETIF_MSG_LINK, "Tx is " ++ "disabled\n"); ++ ext_phy_link_up = 0; ++ break; ++ } ++ } + if (val2 & (1<<1)) + vars->line_speed = SPEED_1000; + else + vars->line_speed = SPEED_10000; + } +- +- /* clear LASI indication*/ +- bnx2x_cl45_read(bp, params->port, ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_RX_ALARM, &val2); +- break; ++ break; ++ ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: ++ { ++ u16 link_status = 0; ++ u16 rx_alarm_status; ++ /* Check the LASI */ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); ++ ++ DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", ++ rx_alarm_status); ++ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_LASI_STATUS, &val1); ++ ++ DP(NETIF_MSG_LINK, ++ "8727 LASI status 0x%x\n", ++ val1); ++ ++ /* Clear MSG-OUT */ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_M8051_MSGOUT_REG, ++ &val1); ++ ++ /* ++ * If a module is present and there is need to check ++ * for over current ++ */ ++ if (!(params->feature_config_flags & ++ FEATURE_CONFIG_BCM8727_NOC) && ++ !(rx_alarm_status & (1<<5))) { ++ /* Check over-current using 8727 GPIO0 input*/ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8727_GPIO_CTRL, ++ &val1); ++ ++ if ((val1 & (1<<8)) == 0) { ++ DP(NETIF_MSG_LINK, "8727 Power fault has" ++ " been detected on port %d\n", ++ params->port); ++ printk(KERN_ERR PFX "Error: Power" ++ " fault on %s Port %d has" ++ " been detected and the" ++ " power to that SFP+ module" ++ " has been removed to prevent" ++ " failure of the card. Please" ++ " remove the SFP+ module and" ++ " restart the system to clear" ++ " this error.\n" ++ , bp->dev->name, params->port); ++ /* ++ * Disable all RX_ALARMs except for ++ * mod_abs ++ */ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM_CTRL, ++ (1<<5)); ++ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, ++ &val1); ++ /* Wait for module_absent_event */ ++ val1 |= (1<<8); ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, ++ val1); ++ /* Clear RX alarm */ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM, ++ &rx_alarm_status); ++ break; ++ } ++ } /* Over current check */ ++ ++ /* When module absent bit is set, check module */ ++ if (rx_alarm_status & (1<<5)) { ++ bnx2x_8727_handle_mod_abs(params); ++ /* Enable all mod_abs and link detection bits */ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM_CTRL, ++ ((1<<5) | (1<<2))); ++ } ++ ++ /* If transmitter is disabled, ++ ignore false link up indication */ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_PHY_IDENTIFIER, ++ &val1); ++ if (val1 & (1<<15)) { ++ DP(NETIF_MSG_LINK, "Tx is disabled\n"); ++ ext_phy_link_up = 0; ++ break; ++ } ++ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8073_SPEED_LINK_STATUS, ++ &link_status); ++ ++ /* Bits 0..2 --> speed detected, ++ bits 13..15--> link is down */ ++ if ((link_status & (1<<2)) && ++ (!(link_status & (1<<15)))) { ++ ext_phy_link_up = 1; ++ vars->line_speed = SPEED_10000; ++ } else if ((link_status & (1<<0)) && ++ (!(link_status & (1<<13)))) { ++ ext_phy_link_up = 1; ++ vars->line_speed = SPEED_1000; ++ DP(NETIF_MSG_LINK, ++ "port %x: External link" ++ " up in 1G\n", params->port); ++ } else { ++ ext_phy_link_up = 0; ++ DP(NETIF_MSG_LINK, ++ "port %x: External link" ++ " is down\n", params->port); ++ } ++ break; ++ } + + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: + { + u16 link_status = 0; + u16 an1000_status = 0; ++ + if (ext_phy_type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) { + bnx2x_cl45_read(bp, params->port, +- ext_phy_type, +- ext_phy_addr, +- MDIO_PCS_DEVAD, +- MDIO_PCS_REG_LASI_STATUS, &val1); +- bnx2x_cl45_read(bp, params->port, +- ext_phy_type, +- ext_phy_addr, +- MDIO_PCS_DEVAD, +- MDIO_PCS_REG_LASI_STATUS, &val2); +- DP(NETIF_MSG_LINK, +- "870x LASI status 0x%x->0x%x\n", +- val1, val2); +- ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PCS_DEVAD, ++ MDIO_PCS_REG_LASI_STATUS, &val1); ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PCS_DEVAD, ++ MDIO_PCS_REG_LASI_STATUS, &val2); ++ DP(NETIF_MSG_LINK, ++ "870x LASI status 0x%x->0x%x\n", ++ val1, val2); + } else { + /* In 8073, port1 is directed through emac0 and + * port0 is directed through emac1 +@@ -3012,13 +4949,13 @@ + MDIO_PCS_DEVAD, + MDIO_PCS_REG_STATUS, &val1); + DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", +- val2, val1); ++ val2, val1); + /* Clear MSG-OUT */ + bnx2x_cl45_read(bp, params->port, + ext_phy_type, + ext_phy_addr, + MDIO_PMA_DEVAD, +- 0xca13, ++ MDIO_PMA_REG_M8051_MSGOUT_REG, + &val1); + + /* Check the LASI */ +@@ -3063,17 +5000,17 @@ + } + } + bnx2x_cl45_read(bp, params->port, +- ext_phy_type, +- ext_phy_addr, +- MDIO_AN_DEVAD, +- 0x8304, +- &an1000_status); +- bnx2x_cl45_read(bp, params->port, +- ext_phy_type, +- ext_phy_addr, +- MDIO_AN_DEVAD, +- 0x8304, +- &an1000_status); ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_LINK_STATUS, ++ &an1000_status); ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_LINK_STATUS, ++ &an1000_status); + + /* Check the link status on 1.1.2 */ + bnx2x_cl45_read(bp, params->port, +@@ -3090,7 +5027,7 @@ + "an_link_status=0x%x\n", + val2, val1, an1000_status); + +- ext_phy_link_up = (((val1 & 4) == 4) || ++ ext_phy_link_up = (((val1 & 4) == 4) || + (an1000_status & (1<<1))); + if (ext_phy_link_up && + bnx2x_8073_is_snr_needed(params)) { +@@ -3110,19 +5047,17 @@ + /* Change CDR Bandwidth in EDC + register */ + bnx2x_cl45_write(bp, port, ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_CDR_BANDWIDTH, +- 0x0333); +- +- +- } +- bnx2x_cl45_read(bp, params->port, +- ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- 0xc820, +- &link_status); ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_CDR_BANDWIDTH, ++ 0x0333); ++ } ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8073_SPEED_LINK_STATUS, ++ &link_status); + + /* Bits 0..2 --> speed detected, + bits 13..15--> link is down */ +@@ -3156,17 +5091,17 @@ + } else { + /* See if 1G link is up for the 8072 */ + bnx2x_cl45_read(bp, params->port, +- ext_phy_type, +- ext_phy_addr, +- MDIO_AN_DEVAD, +- 0x8304, +- &an1000_status); +- bnx2x_cl45_read(bp, params->port, +- ext_phy_type, +- ext_phy_addr, +- MDIO_AN_DEVAD, +- 0x8304, +- &an1000_status); ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_LINK_STATUS, ++ &an1000_status); ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_LINK_STATUS, ++ &an1000_status); + if (an1000_status & (1<<1)) { + ext_phy_link_up = 1; + vars->line_speed = SPEED_1000; +@@ -3226,7 +5161,74 @@ + (val2 & (1<<14))); + } + break; +- ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: ++ /* Clear LASI interrupt. (Obsolete) */ ++ ++ DP(NETIF_MSG_LINK, "8481 LASI status reg = 0x%x\n", ++ val1); ++ ++ /* Check 10G-BaseT link status */ ++ /* Check PMD signal ok */ ++ bnx2x_cl45_read(bp, params->port, ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_8481_PMD_SIGNAL, ++ &val2); ++ ++ /* Check link 10G */ ++ if (val2 & (1<<11)) { ++ vars->line_speed = SPEED_10000; ++ ext_phy_link_up = 1; ++ } else { /* Check Legacy speed link */ ++ u16 legacy_status, legacy_speed; ++ ++ /* Enable expansion register 0x42 ++ (Operation mode status) */ ++ bnx2x_cl45_write(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, ++ 0xf42); ++ ++ /* Get legacy speed operation status */ ++ bnx2x_cl45_read(bp, params->port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, ++ &legacy_status); ++ ++ DP(NETIF_MSG_LINK, "Legacy speed status" ++ " = 0x%x\n", legacy_status); ++ ext_phy_link_up = ((legacy_status & (1<<11)) ++ == (1<<11)); ++ if (ext_phy_link_up) { ++ legacy_speed = (legacy_status & (3<<9)); ++ if (legacy_speed == (0<<9)) ++ vars->line_speed = SPEED_10; ++ else if (legacy_speed == (1<<9)) ++ vars->line_speed = ++ SPEED_100; ++ else if (legacy_speed == (2<<9)) ++ vars->line_speed = ++ SPEED_1000; ++ else /* Should not happen */ ++ vars->line_speed = 0; ++ ++ if (legacy_status & (1<<8)) ++ vars->duplex = DUPLEX_FULL; ++ else ++ vars->duplex = DUPLEX_HALF; ++ ++ DP(NETIF_MSG_LINK, "Link is up " ++ "in %dMbps, is_duplex_full" ++ "= %d\n", ++ vars->line_speed, ++ (vars->duplex == DUPLEX_FULL)); ++ } ++ } ++ break; + default: + DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n", + params->ext_phy_config); +@@ -3265,6 +5267,7 @@ + u32 ext_phy_type; + u32 mask; + struct bnx2x *bp = params->bp; ++ + /* setting the status to report on link up + for either XGXS or SerDes */ + +@@ -3294,27 +5297,62 @@ + } + } + bnx2x_bits_en(bp, +- NIG_REG_MASK_INTERRUPT_PORT0 + port*4, +- mask); +- DP(NETIF_MSG_LINK, "port %x, is_xgxs=%x, int_status 0x%x\n", port, ++ NIG_REG_MASK_INTERRUPT_PORT0 + port*4, ++ mask); ++ ++ DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, + (params->switch_cfg == SWITCH_CFG_10G), + REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); +- + DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", + REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), + REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), + REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); + DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", +- REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), +- REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); +-} +- +- ++ REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), ++ REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); ++} ++ ++static void bnx2x_8481_rearm_latch_signal(struct bnx2x *bp, u8 port, ++ u8 is_mi_int) ++{ ++ u32 latch_status = 0, is_mi_int_status; ++ /* Disable the MI INT ( external phy int ) ++ * by writing 1 to the status register. Link down indication ++ * is high-active-signal, so in this case we need to write the ++ * status to clear the XOR ++ */ ++ /* Read Latched signals */ ++ latch_status = REG_RD(bp, ++ NIG_REG_LATCH_STATUS_0 + port*8); ++ is_mi_int_status = REG_RD(bp, ++ NIG_REG_STATUS_INTERRUPT_PORT0 + port*4); ++ DP(NETIF_MSG_LINK, "original_signal = 0x%x, nig_status = 0x%x," ++ "latch_status = 0x%x\n", ++ is_mi_int, is_mi_int_status, latch_status); ++ /* Handle only those with latched-signal=up.*/ ++ if (latch_status & 1) { ++ /* For all latched-signal=up,Write original_signal to status */ ++ if (is_mi_int) ++ bnx2x_bits_en(bp, ++ NIG_REG_STATUS_INTERRUPT_PORT0 ++ + port*4, ++ NIG_STATUS_EMAC0_MI_INT); ++ else ++ bnx2x_bits_dis(bp, ++ NIG_REG_STATUS_INTERRUPT_PORT0 ++ + port*4, ++ NIG_STATUS_EMAC0_MI_INT); ++ /* For all latched-signal=up : Re-Arm Latch signals */ ++ REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, ++ (latch_status & 0xfffe) | (latch_status & 1)); ++ } ++} + /* + * link management + */ + static void bnx2x_link_int_ack(struct link_params *params, +- struct link_vars *vars, u8 is_10g) ++ struct link_vars *vars, u8 is_10g, ++ u8 is_mi_int) + { + struct bnx2x *bp = params->bp; + u8 port = params->port; +@@ -3325,6 +5363,10 @@ + (NIG_STATUS_XGXS0_LINK10G | + NIG_STATUS_XGXS0_LINK_STATUS | + NIG_STATUS_SERDES0_LINK_STATUS)); ++ if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ++ == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) { ++ bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int); ++ } + if (vars->phy_link_up) { + if (is_10g) { + /* Disable the 10G link interrupt +@@ -3332,8 +5374,8 @@ + */ + DP(NETIF_MSG_LINK, "10G XGXS phy link up\n"); + bnx2x_bits_en(bp, +- NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, +- NIG_STATUS_XGXS0_LINK10G); ++ NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, ++ NIG_STATUS_XGXS0_LINK10G); + + } else if (params->switch_cfg == SWITCH_CFG_10G) { + /* Disable the link interrupt +@@ -3344,11 +5386,12 @@ + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); + +- DP(NETIF_MSG_LINK, "1G XGXS phy link up\n"); ++ DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n", ++ vars->line_speed); + bnx2x_bits_en(bp, +- NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, +- ((1 << ser_lane) << +- NIG_STATUS_XGXS0_LINK_STATUS_SIZE)); ++ NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, ++ ((1 << ser_lane) << ++ NIG_STATUS_XGXS0_LINK_STATUS_SIZE)); + + } else { /* SerDes */ + DP(NETIF_MSG_LINK, "SerDes phy link up\n"); +@@ -3356,8 +5399,8 @@ + * by writing 1 to the status register + */ + bnx2x_bits_en(bp, +- NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, +- NIG_STATUS_SERDES0_LINK_STATUS); ++ NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, ++ NIG_STATUS_SERDES0_LINK_STATUS); + } + + } else { /* link_down */ +@@ -3394,12 +5437,12 @@ + return 0; + } + +- + static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr, + u32 ext_phy_type) + { + u32 cnt = 0; + u16 ctrl = 0; ++ + /* Enable EMAC0 in to enable MDIO */ + REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, + (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); +@@ -3426,7 +5469,7 @@ + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_CTRL, +- &ctrl); ++ &ctrl); + if (!(ctrl & (1<<15))) { + DP(NETIF_MSG_LINK, "Reset completed\n\n"); + break; +@@ -3452,91 +5495,44 @@ + { + struct bnx2x *bp = params->bp; + u32 ext_phy_type = 0; +- u16 val = 0; +- u8 ext_phy_addr = 0 ; +- u8 status = 0 ; +- u32 ver_num; ++ u32 spirom_ver = 0; ++ u8 status = 0; + + if (version == NULL || params == NULL) + return -EINVAL; ++ ++ spirom_ver = REG_RD(bp, params->shmem_base + ++ offsetof(struct shmem_region, ++ port_mb[params->port].ext_phy_fw_version)); + + /* reset the returned value to zero */ + ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); +- ext_phy_addr = ((params->ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); +- + switch (ext_phy_type) { + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: + + if (len < 5) + return -EINVAL; + +- /* Take ext phy out of reset */ +- if (!driver_loaded) +- bnx2x_turn_on_ef(bp, params->port, ext_phy_addr, +- ext_phy_type); +- +- /* wait for 1ms */ +- msleep(1); +- +- bnx2x_cl45_read(bp, params->port, +- ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_7101_VER1, &val); +- version[2] = (val & 0xFF); +- version[3] = ((val & 0xFF00)>>8); +- +- bnx2x_cl45_read(bp, params->port, +- ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, +- &val); +- version[0] = (val & 0xFF); +- version[1] = ((val & 0xFF00)>>8); ++ version[0] = (spirom_ver & 0xFF); ++ version[1] = (spirom_ver & 0xFF00) >> 8; ++ version[2] = (spirom_ver & 0xFF0000) >> 16; ++ version[3] = (spirom_ver & 0xFF000000) >> 24; + version[4] = '\0'; + +- if (!driver_loaded) +- bnx2x_turn_off_sf(bp, params->port); + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: +- { +- /* Take ext phy out of reset */ +- if (!driver_loaded) +- bnx2x_turn_on_ef(bp, params->port, ext_phy_addr, +- ext_phy_type); +- +- bnx2x_cl45_read(bp, params->port, ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_ROM_VER1, &val); +- ver_num = val<<16; +- bnx2x_cl45_read(bp, params->port, ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_ROM_VER2, &val); +- ver_num |= val; +- status = bnx2x_format_ver(ver_num, version, len); +- break; +- } ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: +- +- bnx2x_cl45_read(bp, params->port, ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_ROM_VER1, &val); +- ver_num = val<<16; +- bnx2x_cl45_read(bp, params->port, ext_phy_type, +- ext_phy_addr, +- MDIO_PMA_DEVAD, +- MDIO_PMA_REG_ROM_VER2, &val); +- ver_num |= val; +- status = bnx2x_format_ver(ver_num, version, len); +- break; +- ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: ++ status = bnx2x_format_ver(spirom_ver, version, len); ++ break; ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: ++ spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 | ++ (spirom_ver & 0x7F); ++ status = bnx2x_format_ver(spirom_ver, version, len); ++ break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: + break; + +@@ -3620,10 +5616,8 @@ + + if (params->switch_cfg == SWITCH_CFG_10G) { + ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); ++ ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); + /* CL37 Autoneg Enabled */ +- ext_phy_addr = ((params->ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); + switch (ext_phy_type) { + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN: +@@ -3635,6 +5629,14 @@ + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: + DP(NETIF_MSG_LINK, "ext_phy_loopback: 8706\n"); ++ break; ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: ++ DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); ++ bnx2x_cl45_write(bp, params->port, ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_CTRL, ++ 0x0001); + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: + /* SFX7101_XGXS_TEST1 */ +@@ -3782,6 +5784,7 @@ + u8 rc = 0; + u32 tmp; + u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; ++ + DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); + DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", + speed, hw_led_mode); +@@ -3808,7 +5811,7 @@ + EMAC_WR(bp, EMAC_REG_EMAC_LED, + (tmp & (~EMAC_LED_OVERRIDE))); + +- if (!CHIP_IS_E1H(bp) && ++ if (CHIP_IS_E1(bp) && + ((speed == SPEED_2500) || + (speed == SPEED_1000) || + (speed == SPEED_100) || +@@ -3860,6 +5863,7 @@ + u8 rc = 0; + u8 non_ext_phy; + u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); ++ + /* Activate the external PHY */ + bnx2x_ext_phy_reset(params, vars); + +@@ -3906,14 +5910,15 @@ + + /* init ext phy and enable link state int */ + non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) || +- (params->loopback_mode == LOOPBACK_XGXS_10) || +- (params->loopback_mode == LOOPBACK_EXT_PHY)); ++ (params->loopback_mode == LOOPBACK_XGXS_10)); + + if (non_ext_phy || +- (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705)) { ++ (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) || ++ (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) || ++ (params->loopback_mode == LOOPBACK_EXT_PHY)) { + if (params->req_line_speed == SPEED_AUTO_NEG) + bnx2x_set_parallel_detection(params, vars->phy_flags); +- bnx2x_init_internal_phy(params, vars); ++ bnx2x_init_internal_phy(params, vars, 0); + } + + if (!non_ext_phy) +@@ -3932,24 +5937,23 @@ + u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars) + { + struct bnx2x *bp = params->bp; +- +- u32 val; +- DP(NETIF_MSG_LINK, "Phy Initialization started \n"); +- DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n", +- params->req_line_speed, params->req_flow_ctrl); ++ u32 val; ++ ++ DP(NETIF_MSG_LINK, "Phy Initialization started\n"); ++ DP(NETIF_MSG_LINK, "req_speed %d, req_flowctrl %d\n", ++ params->req_line_speed, params->req_flow_ctrl); + vars->link_status = 0; + vars->phy_link_up = 0; + vars->link_up = 0; + vars->line_speed = 0; + vars->duplex = DUPLEX_FULL; +- vars->flow_ctrl = FLOW_CTRL_NONE; ++ vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; + vars->mac_type = MAC_TYPE_NONE; + + if (params->switch_cfg == SWITCH_CFG_1G) + vars->phy_flags = PHY_SERDES_FLAG; + else + vars->phy_flags = PHY_XGXS_FLAG; +- + + /* disable attentions */ + bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, +@@ -3961,25 +5965,28 @@ + bnx2x_emac_init(params, vars); + + if (CHIP_REV_IS_FPGA(bp)) { ++ + vars->link_up = 1; + vars->line_speed = SPEED_10000; + vars->duplex = DUPLEX_FULL; +- vars->flow_ctrl = FLOW_CTRL_NONE; ++ vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; + vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD); + /* enable on E1.5 FPGA */ +- if (CHIP_IS_E1H(bp)) { ++ if (!CHIP_IS_E1(bp)) { + vars->flow_ctrl |= +- (FLOW_CTRL_TX | FLOW_CTRL_RX); ++ (BNX2X_FLOW_CTRL_TX | ++ BNX2X_FLOW_CTRL_RX); + vars->link_status |= + (LINK_STATUS_TX_FLOW_CONTROL_ENABLED | + LINK_STATUS_RX_FLOW_CONTROL_ENABLED); + } + + bnx2x_emac_enable(params, vars, 0); +- bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed); ++ if (!(CHIP_IS_E2_NOT_PHASE0(params->chip_id))) ++ bnx2x_pbf_update(params, vars->flow_ctrl, ++ vars->line_speed); + /* disable drain */ +- REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +- + params->port*4, 0); ++ REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); + + /* update shared memory */ + bnx2x_update_mng(params, vars->link_status); +@@ -3992,12 +5999,14 @@ + vars->link_up = 1; + vars->line_speed = SPEED_10000; + vars->duplex = DUPLEX_FULL; +- vars->flow_ctrl = FLOW_CTRL_NONE; ++ vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; + vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD); + + bnx2x_bmac_enable(params, vars, 0); + +- bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed); ++ if (!(CHIP_IS_E2_NOT_PHASE0(params->chip_id))) ++ bnx2x_pbf_update(params, vars->flow_ctrl, ++ vars->line_speed); + /* Disable drain */ + REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + + params->port*4, 0); +@@ -4009,10 +6018,11 @@ + + } else + if (params->loopback_mode == LOOPBACK_BMAC) { ++ + vars->link_up = 1; + vars->line_speed = SPEED_10000; + vars->duplex = DUPLEX_FULL; +- vars->flow_ctrl = FLOW_CTRL_NONE; ++ vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; + vars->mac_type = MAC_TYPE_BMAC; + + vars->phy_flags = PHY_XGXS_FLAG; +@@ -4022,12 +6032,14 @@ + bnx2x_bmac_enable(params, vars, 1); + + REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + +- params->port*4, 0); ++ params->port*4, 0); ++ + } else if (params->loopback_mode == LOOPBACK_EMAC) { ++ + vars->link_up = 1; + vars->line_speed = SPEED_1000; + vars->duplex = DUPLEX_FULL; +- vars->flow_ctrl = FLOW_CTRL_NONE; ++ vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; + vars->mac_type = MAC_TYPE_EMAC; + + vars->phy_flags = PHY_XGXS_FLAG; +@@ -4038,13 +6050,15 @@ + bnx2x_emac_program(params, vars->line_speed, + vars->duplex); + REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + +- params->port*4, 0); ++ params->port*4, 0); ++ + } else if ((params->loopback_mode == LOOPBACK_XGXS_10) || +- (params->loopback_mode == LOOPBACK_EXT_PHY)) { ++ (params->loopback_mode == LOOPBACK_EXT_PHY)) { ++ + vars->link_up = 1; + vars->line_speed = SPEED_10000; + vars->duplex = DUPLEX_FULL; +- vars->flow_ctrl = FLOW_CTRL_NONE; ++ vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; + + vars->phy_flags = PHY_XGXS_FLAG; + +@@ -4069,10 +6083,14 @@ + } + REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + + params->port*4, 0); ++ ++ bnx2x_set_led(bp, params->port, LED_MODE_OPER, ++ vars->line_speed, params->hw_led_mode, ++ params->chip_id); ++ + } else + /* No loopback */ + { +- + bnx2x_phy_deassert(params, vars->phy_flags); + switch (params->switch_cfg) { + case SWITCH_CFG_1G: +@@ -4080,8 +6098,7 @@ + if ((params->ext_phy_config & + PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) == + PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482) { +- vars->phy_flags |= +- PHY_SGMII_FLAG; ++ vars->phy_flags |= PHY_SGMII_FLAG; + } + + val = REG_RD(bp, +@@ -4102,8 +6119,8 @@ + default: + DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); + return -EINVAL; +- break; +- } ++ } ++ DP(NETIF_MSG_LINK, "Phy address = 0x%x\n", params->phy_addr); + + bnx2x_link_initialize(params, vars); + msleep(30); +@@ -4112,17 +6129,32 @@ + return 0; + } + +-u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars) +-{ +- ++static void bnx2x_8726_reset_phy(struct bnx2x *bp, u8 port, u8 ext_phy_addr) ++{ ++ DP(NETIF_MSG_LINK, "bnx2x_8726_reset_phy port %d\n", port); ++ ++ /* Set serial boot control for external load */ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_GEN_CTRL, 0x0001); ++} ++ ++u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars, ++ u8 reset_ext_phy) ++{ + struct bnx2x *bp = params->bp; + u32 ext_phy_config = params->ext_phy_config; + u16 hw_led_mode = params->hw_led_mode; + u32 chip_id = params->chip_id; + u8 port = params->port; + u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); ++ u32 val = REG_RD(bp, params->shmem_base + ++ offsetof(struct shmem_region, dev_info. ++ port_feature_config[params->port]. ++ config)); ++ + /* disable attentions */ +- + vars->link_status = 0; + bnx2x_update_mng(params, vars->link_status); + bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, +@@ -4139,7 +6171,7 @@ + REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); + + /* Stop BigMac rx */ +- bnx2x_bmac_rx_disable(bp, port); ++ bnx2x_bmac_rx_disable(bp, params->chip_id, port); + + /* disable emac */ + REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); +@@ -4150,28 +6182,50 @@ + */ + /* clear link led */ + bnx2x_set_led(bp, port, LED_MODE_OFF, 0, hw_led_mode, chip_id); +- if (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { +- if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) && +- (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) { ++ if (reset_ext_phy) { ++ switch (ext_phy_type) { ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: ++ break; ++ ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: ++ { ++ ++ /* Disable Transmitter */ ++ u8 ext_phy_addr = ++ XGXS_EXT_PHY_ADDR(params->ext_phy_config); ++ if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == ++ PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ++ bnx2x_sfp_set_transmitter(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr, 0); ++ break; ++ } ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: ++ DP(NETIF_MSG_LINK, "Setting 8073 port %d into " ++ "low power mode\n", ++ port); ++ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, ++ MISC_REGISTERS_GPIO_OUTPUT_LOW, ++ port); ++ break; ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: ++ { ++ u8 ext_phy_addr = ++ XGXS_EXT_PHY_ADDR(params->ext_phy_config); ++ /* Set soft reset */ ++ bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr); ++ break; ++ } ++ default: + /* HW reset */ +- + bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, + MISC_REGISTERS_GPIO_OUTPUT_LOW, + port); +- + bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_LOW, + port); +- + DP(NETIF_MSG_LINK, "reset external PHY\n"); +- } else if (ext_phy_type == +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { +- DP(NETIF_MSG_LINK, "Setting 8073 port %d into " +- "low power mode\n", +- port); +- bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, +- MISC_REGISTERS_GPIO_OUTPUT_LOW, +- port); + } + } + /* reset the SerDes/XGXS */ +@@ -4196,6 +6250,7 @@ + { + struct bnx2x *bp = params->bp; + u8 port = params->port; ++ + DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); + bnx2x_set_led(bp, port, LED_MODE_OFF, + 0, params->hw_led_mode, +@@ -4218,7 +6273,7 @@ + msleep(10); + + /* reset BigMac */ +- bnx2x_bmac_rx_disable(bp, params->port); ++ bnx2x_bmac_rx_disable(bp, params->chip_id, params->port); + REG_WR(bp, GRCBASE_MISC + + MISC_REGISTERS_RESET_REG_2_CLEAR, + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); +@@ -4232,6 +6287,7 @@ + struct bnx2x *bp = params->bp; + u8 port = params->port; + u8 rc = 0; ++ + vars->link_status |= LINK_STATUS_LINK_UP; + if (link_10g) { + bnx2x_bmac_enable(params, vars, 0); +@@ -4248,13 +6304,14 @@ + if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) { + if (!(vars->phy_flags & + PHY_SGMII_FLAG)) +- bnx2x_set_sgmii_tx_driver(params); ++ bnx2x_set_gmii_tx_driver(params); + } + } + + /* PBF - link up */ +- rc |= bnx2x_pbf_update(params, vars->flow_ctrl, +- vars->line_speed); ++ if (!(CHIP_IS_E2_NOT_PHASE0(params->chip_id))) ++ rc |= bnx2x_pbf_update(params, vars->flow_ctrl, ++ vars->line_speed); + + /* disable drain */ + REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); +@@ -4285,20 +6342,23 @@ + u8 link_10g; + u8 ext_phy_link_up, rc = 0; + u32 ext_phy_type; ++ u8 is_mi_int = 0; + + DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", +- port, +- (vars->phy_flags & PHY_XGXS_FLAG), +- REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); +- ++ port, (vars->phy_flags & PHY_XGXS_FLAG), ++ REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); ++ ++ is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + ++ port*0x18) > 0); + DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", +- REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), +- REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), +- REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); ++ REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), ++ is_mi_int, ++ REG_RD(bp, ++ NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); + + DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", +- REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), +- REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); ++ REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), ++ REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); + + /* disable emac */ + REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); +@@ -4326,7 +6386,7 @@ + (vars->line_speed == SPEED_15000) || + (vars->line_speed == SPEED_16000)); + +- bnx2x_link_int_ack(params, vars, link_10g); ++ bnx2x_link_int_ack(params, vars, link_10g, is_mi_int); + + /* In case external phy link is up, and internal link is down + ( not initialized yet probably after link initialization, it needs +@@ -4337,8 +6397,14 @@ + + if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) && + (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) && +- (ext_phy_link_up && !vars->phy_link_up)) +- bnx2x_init_internal_phy(params, vars); ++ (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) && ++ (ext_phy_link_up && !vars->phy_link_up)) { ++ if (vars->line_speed < SPEED_1000) ++ vars->phy_flags |= PHY_SGMII_FLAG; ++ else ++ vars->phy_flags &= ~PHY_SGMII_FLAG; ++ bnx2x_init_internal_phy(params, vars, 0); ++ } + + /* link is up only if both local phy and external phy are up */ + vars->link_up = (ext_phy_link_up && vars->phy_link_up); +@@ -4371,10 +6437,7 @@ + NIG_MASK_SERDES0_LINK_STATUS | + NIG_MASK_MI_INT)); + +- ext_phy_addr[port] = +- ((ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); ++ ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config); + + /* Need to take the phy out of low power mode in order + to write to access its registers */ +@@ -4398,7 +6461,7 @@ + u16 fw_ver1; + + bnx2x_bcm8073_external_rom_boot(bp, port, +- ext_phy_addr[port]); ++ ext_phy_addr[port], shmem_base); + + bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr[port], +@@ -4434,7 +6497,7 @@ + + /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ + for (port = PORT_MAX - 1; port >= PORT_0; port--) { +- /* Phase2 of POWER_DOWN_RESET*/ ++ /* Phase2 of POWER_DOWN_RESET */ + /* Release bit 10 (Release Tx power down) */ + bnx2x_cl45_read(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, +@@ -4457,7 +6520,7 @@ + MDIO_PMA_REG_EDC_FFE_MAIN, &val); + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, +- ext_phy_addr[port], ++ ext_phy_addr[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); + +@@ -4469,12 +6532,115 @@ + + } + ++static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base) ++{ ++ u8 ext_phy_addr[PORT_MAX]; ++ s8 port; ++ u32 swap_val, swap_override; ++ DP(NETIF_MSG_LINK, "Executing BCM8727 common init\n"); ++ swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); ++ swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); ++ ++ bnx2x_ext_phy_hw_reset(bp, 1 ^ (swap_val && swap_override)); ++ msleep(5); ++ ++ /* PART1 - Reset both phys */ ++ for (port = PORT_MAX - 1; port >= PORT_0; port--) { ++ /* Extract the ext phy address for the port */ ++ u32 ext_phy_config = REG_RD(bp, shmem_base + ++ offsetof(struct shmem_region, ++ dev_info.port_hw_config[port].external_phy_config)); ++ ++ /* disable attentions */ ++ bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, ++ (NIG_MASK_XGXS0_LINK_STATUS | ++ NIG_MASK_XGXS0_LINK10G | ++ NIG_MASK_SERDES0_LINK_STATUS | ++ NIG_MASK_MI_INT)); ++ ++ ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config); ++ ++ /* Reset the phy */ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr[port], ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_CTRL, ++ 1<<15); ++ } ++ ++ /* Add delay of 150ms after reset */ ++ msleep(150); ++ ++ /* PART2 - Download firmware to both phys */ ++ for (port = PORT_MAX - 1; port >= PORT_0; port--) { ++ u16 fw_ver1; ++ ++ bnx2x_bcm8727_external_rom_boot(bp, port, ++ ext_phy_addr[port], shmem_base); ++ ++ bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ++ ext_phy_addr[port], ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_ROM_VER1, &fw_ver1); ++ if (fw_ver1 == 0 || fw_ver1 == 0x4321) { ++ DP(NETIF_MSG_LINK, ++ "bnx2x_8073_common_init_phy port %x:" ++ "Download failed. fw version = 0x%x\n", ++ port, fw_ver1); ++ return -EINVAL; ++ } ++ ++ } ++ ++ ++ ++ return 0; ++} ++ ++ ++static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base) ++{ ++ u8 ext_phy_addr; ++ u32 val; ++ s8 port; ++ ++ /* Use port1 because of the static port-swap */ ++ /* Enable the module detection interrupt */ ++ val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); ++ val |= ((1<type, header->image_info, ++ header->byte_cnt); ++ ++ if ((header->magic != FILE_MAGIC) || ++ (header->version != FORMAT_VERSION_2) || ++ (header->type != image_hdr_type)) { ++ DP(NETIF_MSG_LINK, "Invalid image header: Magic = 0x%x," ++ " version = 0x%x, phy_type = 0x%x\n", ++ header->magic, header->version, header->type); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr) + { + u16 val, cnt; + +@@ -4530,6 +6743,7 @@ + break; + } + } ++ + #define RESERVED_SIZE 256 + /* max application is 160K bytes - data at end of RAM */ + #define MAX_APP_SIZE (160*1024 - RESERVED_SIZE) +@@ -4543,6 +6757,571 @@ + ext_phy_addr, \ + MDIO_PCS_DEVAD, \ + MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 1) ++ ++/************************************************************************/ ++/* Function: bnx2x_bcm_flash_download */ ++/* Description : Load SPI EEPROM through BCM8073. */ ++/* */ ++/************************************************************************/ ++ ++#define WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wrdata, rddata) \ ++ {if (write_message_bcm(bp, port, ext_phy_addr, \ ++ ext_phy_type, wrdata, rddata) != 0) \ ++ return -EINVAL; } ++ ++static u8 write_message_bcm(struct bnx2x *bp, u8 port, ++ u8 ext_phy_addr, u32 ext_phy_type, ++ u16 wrdata, u16 *rddata) ++{ ++ u16 tmp_data = 0; ++ u16 i = 0; ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp_data); ++ ++ /* Write SPI Control Register Write Command.*/ ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_M8051_MSGIN_REG, wrdata); ++ ++ /* Wait For LASI To be asserted when M8051 writes Next Parameter To ++ MSG_OUT Register TBD wait (xlasi_ch1 === 1'b0); ++ Above wait can also be done by polling 9005, bit 2 As bellow. */ ++ ++ for (i = 0; i < UPGRADE_TIMEOUT_BCM; i++) { ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_LASI_STATUS, &tmp_data); ++ if ((tmp_data & (1<<2)) != 0) {/* bit 2 is Rx Alarm for LASI.*/ ++ break; ++ } ++ msleep(6); ++ } ++ ++ if (i == UPGRADE_TIMEOUT_BCM) { ++ DP(NETIF_MSG_LINK, "Failed to get LASI indication. Aborting\n"); ++ return -EINVAL; ++ } ++ ++ /* Read Message out register. 1.CA13 */ ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp_data); ++ *rddata = tmp_data; ++ ++ /* Clear LASI Message Out Status. 1.9003*/ ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM, &tmp_data); ++ return 0; ++} ++ ++ ++static u8 bnx2x_phy_bcm_rom_wait(struct bnx2x *bp, u8 port, ++ u8 ext_phy_addr, u32 ext_phy_type) ++{ ++ /* Wait For WRSR Command To be written.*/ ++ u8 spi_ready = 0, count; ++ ++ u16 rd_data = 0, wr_data = 0 ; ++ u16 retry_count = 0; ++ while ((rd_data & 0x0100) == 0 && (++retry_count < 1000)) { ++ /* Write SPI Control Register Read Command.*/ ++ count = 1; ++ wr_data = ((RD_CPU_CTRL_REGS * 0x0100) | count); ++ count = 2; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Address.*/ ++ wr_data = SPI_CTRL_1_L; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ } ++ if (retry_count == 1000) { ++ DP(NETIF_MSG_LINK, ++ "Failed writing SPI Write SPI Control Register\n"); ++ return -EINVAL; ++ } ++ DP(NETIF_MSG_LINK, "SPI Controller Wrote WRSR Command.\n" ++ " Checking SPI Status Now "); ++ spi_ready = 1; ++ retry_count = 0; ++ while (spi_ready == 1 && (++retry_count < 1000)) { ++ /* Set-up SPI Controller To Receive SPI EEPROM Status.*/ ++ /* Write SPI Control Register Write Command.*/ ++ count = 1; ++ wr_data = ((WR_CPU_CTRL_REGS * 0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -2 Register Address.*/ ++ wr_data = SPI_CTRL_2_H; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -2 Register Word-2.*/ ++ wr_data = 0x0100; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Fill-up SPI Transmit Fifo To check SPI Status.*/ ++ /* Write SPI Control Register Write Command.*/ ++ count = 2; ++ wr_data = ((WR_CPU_CTRL_FIFO*0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write Tx Fifo Register Address.*/ ++ wr_data = SPI_TXFIFO; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Tx Fifo Control Word-1.*/ ++ wr_data = ((1 * 0x0100) | MSGTYPE_HRD); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Tx Fifo Control Word-2.*/ ++ wr_data = RDSR_OPCODE; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control Register Write Command.*/ ++ count = 2; ++ wr_data = ((WR_CPU_CTRL_FIFO * 0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Address.*/ ++ wr_data = SPI_CTRL_1_L; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Word-1.*/ ++ wr_data = 0x0101; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Word-2.*/ ++ wr_data = 0x0100; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control Register Write Command.*/ ++ count = 1; ++ wr_data = ((WR_CPU_CTRL_REGS * 0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Address.*/ ++ wr_data = SPI_CTRL_1_H; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Word-2.*/ ++ wr_data = 0x0103; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ DP(NETIF_MSG_LINK, "**Wait for Status Register to be written "); ++ ++ /* Wait For 64 bytes To be written.*/ ++ rd_data = 0x0000; ++ while ((rd_data & 0x0100) == 0) { ++ /* Write SPI Control Register Read Command.*/ ++ count = 1; ++ wr_data = ((RD_CPU_CTRL_REGS * 0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, ++ wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Address.*/ ++ wr_data = SPI_CTRL_1_L; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, ++ wr_data, &rd_data); ++ } ++ DP(NETIF_MSG_LINK, "**Write SPI CTRl Read command "); ++ ++ /* Write SPI Control Register Read Command.*/ ++ count = 1; /* Read from SPI Controller register C000.*/ ++ wr_data = ((RD_CPU_CTRL_REGS * 0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Address.*/ ++ wr_data = SPI_RXFIFO; ++ if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 || ++ ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) { ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, ++ wr_data, &rd_data); ++ } else { ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_M8051_MSGIN_REG, wr_data); ++ ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_M8051_MSGOUT_REG, &rd_data); ++ ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM, &wr_data); ++ } ++ ++ if ((rd_data & 0x1) == 0) ++ spi_ready = 0; ++ } /* spi_ready */ ++ if (retry_count == 1000) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++ ++static u8 bnx2x_phy_bcm_rom_write_enable(struct bnx2x *bp, u8 port, ++ u8 ext_phy_addr, u32 ext_phy_type, ++ u8 enable) ++{ ++ u8 count = 0, wrsr_data; ++ u16 rd_data = 0, wr_data = 0; ++ ++ /* De-assert SPI EEPROM Block Protection.*/ ++ DP(NETIF_MSG_LINK, "*** De-assert SPI Block Protect\n"); ++ ++ /* Write SPI Control Register Write Command.*/ ++ count = 2; ++ wr_data = ((WR_CPU_CTRL_FIFO * 0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ DP(NETIF_MSG_LINK, "First write succeeded\n"); ++ /* Write SPI Control -2 Register Address.*/ ++ wr_data = SPI_CTRL_2_L; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -2 Register Word-1.*/ ++ wr_data = 0x8200; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -2 Register Word-2.*/ ++ wr_data = 0x0100; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Fill-up SPI Transmit Fifo With SPI EEPROM Messages.*/ ++ /* Write SPI Control Register Write Command.*/ ++ count = 4; ++ wr_data = ((WR_CPU_CTRL_FIFO * 0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write Tx Fifo Register Address.*/ ++ wr_data = SPI_TXFIFO; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Tx Fifo Control Word-1.*/ ++ wr_data = ((1 * 0x0100) | MSGTYPE_HWR); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Tx Fifo Control Word-2.*/ ++ wr_data = ((MSGTYPE_HWR * 0x0100) | WREN_OPCODE); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Tx Fifo Control Word-3.*/ ++ wr_data = ((WRSR_OPCODE * 0x0100) | 0x02); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Tx Fifo Control Word-4.*/ ++ ++ wrsr_data = enable ? 0x2 : 0xc; ++ wr_data = ((wrsr_data * 0x0100) | wrsr_data); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control Register Write Command.*/ ++ wr_data = ((WR_CPU_CTRL_FIFO * 0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Address.*/ ++ wr_data = SPI_CTRL_1_L; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Word-1.*/ ++ wr_data = 0x0101; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Word-2.*/ ++ wr_data = 0x0003; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ return bnx2x_phy_bcm_rom_wait(bp, port, ext_phy_addr, ext_phy_type); ++ ++} ++ ++/* Programs an image to DSP's flash via the SPI port*/ ++static u8 bnx2x_bcm_flash_download(struct bnx2x *bp, u8 port, ++ u8 ext_phy_addr, u32 ext_phy_type, ++ char *code_ptr, u32 size) { ++ u16 tmp, rd_data, wr_data = 4; ++ u8 count, rc = 0; ++ u32 i, data_index; ++ u16 misc_ctrl; ++ ++ DP(NETIF_MSG_LINK, "bnx2x_bcm_flash_download: size=0x%x\n", size); ++ ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_AN_DEVAD, ++ MDIO_AN_REG_CTRL, 0); ++ ++ /* Enable the LASI For Message out */ ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_MISC_CTRL1, &misc_ctrl); ++ ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_MISC_CTRL1, (misc_ctrl | (1<<0))); ++ ++ /* Read LASI Status registers To clear initial Failure status. */ ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM, &tmp); ++ ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_TX_ALARM, &tmp); ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_LASI_STATUS, &tmp); ++ ++ /* Enable the LASI For Message out */ ++ ++ switch (ext_phy_type) { ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: ++ wr_data = 0x0004; ++ break; ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: ++ wr_data = 0x0400; ++ break; ++ } ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM_CTRL, wr_data); ++ ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_LASI_CTRL, 0x4); ++ ++ ++ /* Read Any Residual Message out register.1.CA13*/ ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_M8051_MSGOUT_REG, &rd_data); ++ ++ /* Clear LASI Message Out Status. 1.9003 */ ++ bnx2x_cl45_read(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_RX_ALARM, &rd_data); ++ ++ if (bnx2x_phy_bcm_rom_write_enable(bp, port, ext_phy_addr, ++ ext_phy_type, 1) != 0) ++ return -EINVAL; ++ ++ for (data_index = 0; data_index < BUF_SIZE_BCM; ++ data_index += WR_BLOCK_SIZE) { ++ /* Setup SPI Controller ++ Write SPI Control Register Write Command. */ ++ ++ count = 2;/* Write to C400, C401, C402, C403 Registers.*/ ++ wr_data = ((WR_CPU_CTRL_FIFO * 0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -2 Register Address.*/ ++ wr_data = SPI_CTRL_2_L; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -2 Register Word-1 */ ++ /* C400 = 0 for 0 Fill Byte. C401 = 02 for SPI Clcok to ++ be divide by 2 and little endian fifo.*/ ++ wr_data = 0x8200; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -2 Register Word-2.*/ ++ /* C402 = 0, clear all status. C403 = 1, ++ to enable Done Status.*/ ++ wr_data = 0x0100; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Fill-up SPI Transmit Fifo.*/ ++ /* Write SPI Control Register Write Command. */ ++ /* Write To Transmit Fifo D000-onwards.*/ ++ count = 4 + (WR_BLOCK_SIZE/2); ++ wr_data = ((WR_CPU_CTRL_FIFO*0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write Tx Fifo Register Address.*/ ++ wr_data = SPI_TXFIFO; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Tx Fifo Control Word-1.*/ ++ /* {8'h1, MSGTYPE_HWR}; ++ ( 1byte to transmit for WREN opcode).*/ ++ wr_data = ((1*0x0100) | MSGTYPE_HWR); ++ /* D001 = Write Message And Higher byte of Transfer Size */ ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ /* Write SPI Tx Fifo Control Word-2.*/ ++ /* D002 = WREN Opcode For transmit.*/ ++ wr_data = ((MSGTYPE_HWR * 0x0100) | WREN_OPCODE); ++ /* D003 = Total byte To be transmited ++ (64 + 3 For command, And address).*/ ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Tx Fifo Control Word-3.*/ ++ /* D004 = Second Message is also WRITE Message.*/ ++ wr_data = ((WR_OPCODE * 0x0100) | ++ (0x3 + WR_BLOCK_SIZE)); ++ /* D005 = Write Opcode.*/ ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Tx Fifo Control Word-4. */ ++ /* D006 = SPI EEPROM Dest Addr (higher byte sent out first).*/ ++ /* D007 = SPI EEPROM Dest Addr (lower byte sent out later).*/ ++ wr_data = (((data_index & 0x00FF)*0x0100) | ++ ((data_index & 0xFF00)/0x0100)); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ for (i = 0; i < WR_BLOCK_SIZE; i += 2) { ++ /* Write SPI Tx Fifo Data Word-4.*/ ++ /* D008 = Low Byte. D009 = High Byte.*/ ++ wr_data = (u16)((code_ptr[i+data_index+1]*0x0100) | ++ (code_ptr[i+data_index] & 0x00FF)); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, ++ &rd_data); ++ } ++ ++ DP(NETIF_MSG_LINK, " 64bytes filled in SPIfifo 0x%x\n", ++ data_index); ++ ++ /* Let the user know something's going on every 1024 bytes.*/ ++ if ((data_index % 1024) == 0) ++ DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size); ++ ++ /* Set-up SPI Controller To Transmit.*/ ++ /* Write SPI Control Register Write Command.*/ ++ /* Write to SPI Control Register C000 onwards.*/ ++ count = 2; ++ /* {CLC_WR_CPU_CTRL_FIFO, count};*/ ++ wr_data = ((WR_CPU_CTRL_FIFO*0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Address.*/ ++ wr_data = SPI_CTRL_1_L; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Word-1.*/ ++ /* C000 = 1 to clear CMD Done Status. C001 = 1 to clear CMD Done ++ INT Status.*/ ++ wr_data = 0x0501; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Word-2.*/ ++ /* C002 = 3, Start Immidiate Command. C003 = 0, No Prepend byte ++ for Write.*/ ++ wr_data = 0x0003; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ if (bnx2x_phy_bcm_rom_wait(bp, port, ext_phy_addr, ext_phy_type) ++ != 0) ++ return -EINVAL; ++ } ++ DP(NETIF_MSG_LINK, "*** SPI_READ and WRITE COMPLETE 0x%x\n", ++ data_index); ++ ++ if (bnx2x_phy_bcm_rom_write_enable(bp, port, ext_phy_addr, ++ ext_phy_type, 0) != 0) ++ return -EINVAL; ++ ++ /* Disable SPI EEPROM.*/ ++ /* Write SPI Control Register Write Command.*/ ++ count = 2; /* Write to C400, C401, C402, C403 Registers.*/ ++ wr_data = ((WR_CPU_CTRL_FIFO*0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -2 Register Address.*/ ++ wr_data = SPI_CTRL_2_L; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -2 Register Word-1.*/ ++ wr_data = 0x8200; /* C400 = 0 for 0 Fill Byte. C401 = 02 for ++ SPI Clcok to be divide by 2 and little endian fifo.*/ ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -2 Register Word-2.*/ ++ wr_data = 0x0100; /* C402 = 0, clear all status. C403 = 1, to ++ enable Done Status.*/ ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Fill-up SPI Transmit Fifo With SPI EEPROM Messages.*/ ++ /* Write SPI Control Register Write Command.*/ ++ count = 2; /* Write to Transmit Fifo D000-onwards.*/ ++ wr_data = ((WR_CPU_CTRL_FIFO*0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /*Write Tx Fifo Register Address.*/ ++ wr_data = SPI_TXFIFO; /* D000.*/ ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Tx Fifo Control Word-1.*/ ++ wr_data = ((0x1*0x0100) | MSGTYPE_HWR); /* D000 = Only 1 ++ byte Message ( 1byte to transmit for WRDI opcode).*/ ++ ++ /* D001 = Write Message And Higher byte of Transfer Size.*/ ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Tx Fifo Control Word-2.*/ ++ wr_data = WRDI_OPCODE; /* D002 = WRDI Opcode for transmit.*/ ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /*Write SPI Control Register Write Command.*/ ++ count = 2; /* Write to SPI Control Register C000 onwards.*/ ++ wr_data = ((WR_CPU_CTRL_FIFO*0x0100) | count); ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ /* Write SPI Control -1 Register Address.*/ ++ wr_data = SPI_CTRL_1_L; ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Word-1.*/ ++ wr_data = 0x0101; /* C000 = 1 to clear CMD Done Status. ++ C001 = 1 to clear CMD Done INT Status.*/ ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ ++ /* Write SPI Control -1 Register Word-2.*/ ++ wr_data = 0x0003; /* C002 = 3, Start Immidiate Command. ++ C003 = 0, No Prepend byte for Write.*/ ++ WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data); ++ bnx2x_cl45_write(bp, port, ++ ext_phy_type, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, ++ MDIO_PMA_REG_MISC_CTRL1, (misc_ctrl & ~(1<<0))); ++ DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size); ++ return rc; ++} + + /* Programs an image to DSP's flash via the SPI port*/ + static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port, +@@ -4630,7 +7409,7 @@ + ext_phy_addr, + MDIO_PCS_DEVAD, + MDIO_PCS_REG_7101_SPI_FIFO_ADDR, +- MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD); ++ MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD); + + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, +@@ -4645,7 +7424,7 @@ + ext_phy_addr, + MDIO_PCS_DEVAD, + MDIO_PCS_REG_7101_SPI_FIFO_ADDR, +- MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD); ++ MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD); + + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, +@@ -4664,7 +7443,7 @@ + data_index = 0; + for (trans_cnt = 0; trans_cnt < num_trans; trans_cnt++) { + bnx2x_cl45_write(bp, port, +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, + ext_phy_addr, + MDIO_PCS_DEVAD, + MDIO_PCS_REG_7101_SPI_FIFO_ADDR, +@@ -4679,10 +7458,10 @@ + SPI_START_TRANSFER(bp, port, ext_phy_addr); + + bnx2x_cl45_write(bp, port, +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, +- ext_phy_addr, +- MDIO_PCS_DEVAD, +- MDIO_PCS_REG_7101_SPI_FIFO_ADDR, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, ++ ext_phy_addr, ++ MDIO_PCS_DEVAD, ++ MDIO_PCS_REG_7101_SPI_FIFO_ADDR, + MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD); + + /* Bits 23-16 of address */ +@@ -4713,9 +7492,9 @@ + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, + ext_phy_addr, +- MDIO_PCS_DEVAD, +- MDIO_PCS_REG_7101_SPI_FIFO_ADDR, +- data[data_index++]); ++ MDIO_PCS_DEVAD, ++ MDIO_PCS_REG_7101_SPI_FIFO_ADDR, ++ data[data_index++]); + byte_cnt++; + } + +@@ -4788,11 +7567,11 @@ + while (byte_cnt < last_trans_size && data_index < size) { + /* Bits 7-0 of address */ + bnx2x_cl45_write(bp, port, +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, +- ext_phy_addr, +- MDIO_PCS_DEVAD, +- MDIO_PCS_REG_7101_SPI_FIFO_ADDR, +- data[data_index++]); ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, ++ ext_phy_addr, ++ MDIO_PCS_DEVAD, ++ MDIO_PCS_REG_7101_SPI_FIFO_ADDR, ++ data[data_index++]); + byte_cnt++; + } + +@@ -4816,7 +7595,7 @@ + for (cnt = 0; cnt < 100; cnt++) + msleep(5); + +- bnx2x_hw_reset(bp, port); ++ bnx2x_ext_phy_hw_reset(bp, port); + + for (cnt = 0; cnt < 100; cnt++) + msleep(5); +@@ -4863,26 +7642,218 @@ + return 0; + } + ++ ++ ++u8 bnx2x_bcm8481_flash_download(struct bnx2x *bp, u8 port, ++ u8 ext_phy_addr, ++ char data[], u32 size) ++{ ++ u32 data_index; ++ u16 val, cnt; ++ ++ /* Disable interrupts */ ++ bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, ++ (NIG_MASK_XGXS0_LINK_STATUS | ++ NIG_MASK_XGXS0_LINK10G | ++ NIG_MASK_SERDES0_LINK_STATUS | ++ NIG_MASK_MI_INT)); ++ ++ /* Step 1: Halt system */ ++ DP(NETIF_MSG_LINK, "Step 1: Halt system\n"); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ 0x1e, 0x4186, 0x8000); ++ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ 0x1e, 0x4181, 0x017c); ++ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ 0x1e, 0x4181, 0x0040); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA819, 0x0000); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA81A, 0xc300); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA81B, 0x001e); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA81C, 0x0000); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA817, 0x0009); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA819, 0x0000); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA81A, 0xffff); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA81B, 0xfffe); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA81C, 0xeaff); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA817, 0x0009); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ 0x1e, 0x4181, 0x0000); ++ ++ /* Step 2: Download code into memory*/ ++ DP(NETIF_MSG_LINK, "Step 2: Download code into memory\n"); ++ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA817, 0x0039); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA81A, 0x0000); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA819, 0x0000); ++ ++ for (data_index = 0; data_index < size; data_index += 4) { ++ /* File is in Little Endian */ ++ /* Write upper 16-bits(x)*/ ++ val = data[data_index+2] | (data[data_index+3] << 8); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA81C, val); ++ /* Write lower 16-bits(x)*/ ++ val = data[data_index+0] | (data[data_index+1] << 8); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA81B, val); ++ /* Wait for complete status for upto 5 ms*/ ++ for (cnt = 0; cnt < 1000; cnt++) { ++ bnx2x_cl45_read(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA818, &val); ++ if (val & 0x1) ++ break; ++ /* Wait 50 microSec*/ ++ udelay(50); ++ } ++ if (cnt == 1000) { ++ DP(NETIF_MSG_LINK, "Failed to download image\n"); ++ return -EINVAL; ++ } ++ if ((data_index % 1024) == 0) ++ DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size); ++ } ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA817, 0x0000); ++ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA819, 0x0000); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA81A, 0xc300); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA81B, 0x000c); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA81C, 0x0000); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ MDIO_PMA_DEVAD, 0xA817, 0x0009); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ 0x1e, 0x4181, 0x0040); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ 0x1e, 0x4181, 0x0000); ++ DP(NETIF_MSG_LINK, "Step 3: Waiting for the Programming" ++ "phase to be completed (5 seconds).\n"); ++ for (cnt = 0; cnt < 1000; cnt++) ++ msleep(5); ++ /* Step 3: Restart system */ ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ 0x1e, 0x4181, 0x017c); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ 0x1e, 0x4181, 0x0040); ++ bnx2x_cl45_write(bp, port, ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ++ ext_phy_addr, ++ 0x1e, 0x4181, 0x0000); ++ DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size); ++ return 0; ++} + u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config, + u8 driver_loaded, char data[], u32 size) + { + u8 rc = 0; + u32 ext_phy_type; + u8 ext_phy_addr; +- ext_phy_addr = ((ext_phy_config & +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> +- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); +- ++ ext_phy_addr = XGXS_EXT_PHY_ADDR(ext_phy_config); + ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); ++ ++ /* Verify image header */ ++ if (bnx2x_verify_image_header(bp, ++ (struct bnx2x_image_header *)data, ++ ext_phy_type) != 0) ++ return -EINVAL; ++ data += sizeof(struct bnx2x_image_header); ++ size -= sizeof(struct bnx2x_image_header); + + switch (ext_phy_type) { + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: +- case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: + DP(NETIF_MSG_LINK, + "Flash download not supported for this ext phy\n"); + rc = -EINVAL; ++ break; ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: ++ if (!driver_loaded) ++ bnx2x_turn_on_ef(bp, port, ext_phy_addr, ext_phy_type); ++ ++ rc = bnx2x_bcm_flash_download(bp, port, ext_phy_addr, ++ ext_phy_type, ++ data, size); + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: + /* Take ext phy out of reset */ +@@ -4893,6 +7864,10 @@ + if (!driver_loaded) + bnx2x_turn_off_sf(bp, port); + break; ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: ++ rc = bnx2x_bcm8481_flash_download(bp, port, ext_phy_addr, ++ data, size); ++ break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN: +diff -r e67cb9a8e847 drivers/net/bnx2x_link.h +--- a/drivers/net/bnx2x_link.h Wed Aug 05 10:50:39 2009 +0100 ++++ b/drivers/net/bnx2x_link.h Wed Aug 05 10:51:03 2009 +0100 +@@ -1,4 +1,4 @@ +-/* Copyright 2008 Broadcom Corporation ++/* Copyright 2008-2009 Broadcom Corporation + * + * Unless you and Broadcom execute a separate written software license + * agreement governing use of this software, this software is licensed to you +@@ -22,24 +22,30 @@ + /***********************************************************/ + /* Defines */ + /***********************************************************/ +-#define DEFAULT_PHY_DEV_ADDR 3 ++#define DEFAULT_PHY_DEV_ADDR 3 + + + +-#define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO +-#define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX +-#define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX +-#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH +-#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE ++#define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO ++#define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX ++#define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX ++#define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH ++#define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE + +-#define SPEED_AUTO_NEG 0 +-#define SPEED_12000 12000 +-#define SPEED_12500 12500 +-#define SPEED_13000 13000 +-#define SPEED_15000 15000 +-#define SPEED_16000 16000 ++#define SPEED_AUTO_NEG 0 ++#define SPEED_12000 12000 ++#define SPEED_12500 12500 ++#define SPEED_13000 13000 ++#define SPEED_15000 15000 ++#define SPEED_16000 16000 + +- ++#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14 ++#define SFP_EEPROM_VENDOR_NAME_SIZE 16 ++#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25 ++#define SFP_EEPROM_VENDOR_OUI_SIZE 3 ++#define SFP_EEPROM_PART_NO_ADDR 0x28 ++#define SFP_EEPROM_PART_NO_SIZE 16 ++#define PWR_FLT_ERR_MSG_LEN 250 + /***********************************************************/ + /* Structs */ + /***********************************************************/ +@@ -50,12 +56,12 @@ + + /* Default / User Configuration */ + u8 loopback_mode; +-#define LOOPBACK_NONE 0 +-#define LOOPBACK_EMAC 1 +-#define LOOPBACK_BMAC 2 +-#define LOOPBACK_XGXS_10 3 +-#define LOOPBACK_EXT_PHY 4 +-#define LOOPBACK_EXT 5 ++#define LOOPBACK_NONE 0 ++#define LOOPBACK_EMAC 1 ++#define LOOPBACK_BMAC 2 ++#define LOOPBACK_XGXS_10 3 ++#define LOOPBACK_EXT_PHY 4 ++#define LOOPBACK_EXT 5 + + u16 req_duplex; + u16 req_flow_ctrl; +@@ -66,8 +72,6 @@ + /* Device parameters */ + u8 mac_addr[6]; + +- +- + /* shmem parameters */ + u32 shmem_base; + u32 speed_cap_mask; +@@ -77,42 +81,60 @@ + #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT + + u16 hw_led_mode; /* part of the hw_config read from the shmem */ +- u32 serdes_config; ++ ++ /* phy_addr populated by the CLC */ ++ u8 phy_addr; ++ /*u8 reserved1;*/ ++ + u32 lane_config; + u32 ext_phy_config; +-#define XGXS_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \ +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) +-#define SERDES_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \ +- PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) ++#define XGXS_EXT_PHY_TYPE(ext_phy_config) \ ++ ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) ++#define XGXS_EXT_PHY_ADDR(ext_phy_config) \ ++ (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \ ++ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT) ++#define SERDES_EXT_PHY_TYPE(ext_phy_config) \ ++ ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) ++ + /* Phy register parameter */ + u32 chip_id; + +- /* phy_addr populated by the CLC */ +- u8 phy_addr; ++ u16 xgxs_config_rx[4]; /* preemphasis values for the rx side */ ++ u16 xgxs_config_tx[4]; /* preemphasis values for the tx side */ ++ ++ u32 feature_config_flags; ++#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) ++#define FEATURE_CONFIG_PFC_ENABLED (1<<1) ++#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) ++#define FEATURE_CONFIG_BCM8727_NOC (1<<3) ++ + /* Device pointer passed to all callback functions */ + struct bnx2x *bp; + }; + + /* Output parameters */ + struct link_vars { ++ u8 phy_flags; ++ ++ u8 mac_type; ++#define MAC_TYPE_NONE 0 ++#define MAC_TYPE_EMAC 1 ++#define MAC_TYPE_BMAC 2 ++ + u8 phy_link_up; /* internal phy link indication */ + u8 link_up; ++ ++ u16 line_speed; + u16 duplex; ++ + u16 flow_ctrl; +- u32 ieee_fc; +- u8 mac_type; ++ u16 ieee_fc; + +-#define MAC_TYPE_NONE 0 +-#define MAC_TYPE_EMAC 1 +-#define MAC_TYPE_BMAC 2 +- u16 line_speed; + u32 autoneg; + #define AUTO_NEG_DISABLED 0x0 + #define AUTO_NEG_ENABLED 0x1 + #define AUTO_NEG_COMPLETE 0x2 +-#define AUTO_NEG_PARALLEL_DETECTION_USED 0x3 +- +- u8 phy_flags; ++#define AUTO_NEG_PARALLEL_DETECTION_USED 0x3 + + /* The same definitions as the shmem parameter */ + u32 link_status; +@@ -125,8 +147,11 @@ + /* Initialize the phy */ + u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output); + +-/* Reset the link. Should be called when driver or interface goes down */ +-u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars); ++/* Reset the link. Should be called when driver or interface goes down ++ Before calling phy firmware upgrade, the reset_ext_phy should be set ++ to 0 */ ++u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars, ++ u8 reset_ext_phy); + + /* bnx2x_link_update should be called upon link interrupt */ + u8 bnx2x_link_update(struct link_params *input, struct link_vars *output); +@@ -163,6 +188,10 @@ + + u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config, + u8 driver_loaded, char data[], u32 size); ++/* bnx2x_handle_module_detect_int should be called upon module detection ++ interrupt */ ++void bnx2x_handle_module_detect_int(struct link_params *params); ++ + /* Get the actual link status. In case it returns 0, link is up, + otherwise link is down*/ + u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars); +@@ -170,4 +199,12 @@ + /* One-time initialization for external phy after power up */ + u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base); + ++/* Reset the external PHY using GPIO */ ++void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port); ++ ++void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr); ++ ++u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr, ++ u8 byte_cnt, u8 *o_buf); ++ + #endif /* BNX2X_LINK_H */ +diff -r e67cb9a8e847 drivers/net/bnx2x_main.c +--- a/drivers/net/bnx2x_main.c Wed Aug 05 10:50:39 2009 +0100 ++++ b/drivers/net/bnx2x_main.c Wed Aug 05 10:51:03 2009 +0100 +@@ -10,15 +10,20 @@ + * Written by: Eliezer Tamir + * Based on code from Michael Chan's bnx2 driver + * UDP CSUM errata workaround by Arik Gendelman +- * Slowpath rework by Vladislav Zolotarov ++ * Slowpath and fastpath rework by Vladislav Zolotarov + * Statistics and Link management by Yitchak Gertner + * + */ + ++#include + #include ++#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */ + #include ++#endif + #include ++#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */ + #include /* for dev_info() */ ++#endif + #include + #include + #include +@@ -30,7 +35,9 @@ + #include + #include + #include ++#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */ + #include ++#endif + #include + #include + #include +@@ -40,26 +47,55 @@ + #include + #include + #include ++#if (LINUX_VERSION_CODE < 0x020600) /* ! BNX2X_UPSTREAM */ ++#include ++#endif + #include + #include ++#if (LINUX_VERSION_CODE > 0x020607) /* BNX2X_UPSTREAM */ + #include ++#endif ++#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */ + #include ++#endif + #include ++#if (LINUX_VERSION_CODE >= 0x02061b) && !defined(BNX2X_DRIVER_DISK) && !defined(__VMKLNX__) /* BNX2X_UPSTREAM */ + #include ++#endif + #include + #include ++#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */ + #include +- +-#include "bnx2x_reg.h" +-#include "bnx2x_fw_defs.h" +-#include "bnx2x_hsi.h" +-#include "bnx2x_link.h" ++#else ++#include ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x020600) /* ! BNX2X_UPSTREAM */ ++#define __NO_TPA__ 1 ++#endif ++ + #include "bnx2x.h" + #include "bnx2x_init.h" +- +-#define DRV_MODULE_VERSION "1.45.27" +-#define DRV_MODULE_RELDATE "2009/01/26" ++#include "bnx2x_init_ops.h" ++#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ ++#include "bnx2x_self_test.h" ++#endif ++#include "bnx2x_dump.h" ++ ++#define DRV_MODULE_VERSION "1.50.13" ++#define DRV_MODULE_RELDATE "$DateTime: 2009/07/22 07:22:59 $" + #define BNX2X_BC_VER 0x040200 ++ ++#if defined(BNX2X_UPSTREAM) && !defined(BNX2X_USE_INIT_VALUES) /* BNX2X_UPSTREAM */ ++#include ++#include "bnx2x_fw_file_hdr.h" ++/* FW files */ ++#define FW_FILE_PREFIX_E1 "bnx2x-e1-" ++#define FW_FILE_PREFIX_E1H "bnx2x-e1h-" ++#else ++void bnx2x_init_e1_firmware(struct bnx2x *bp); ++void bnx2x_init_e1h_firmware(struct bnx2x *bp); ++#endif + + /* Time in jiffies before concluding the transmitter is hung */ + #define TX_TIMEOUT (5*HZ) +@@ -72,27 +108,93 @@ + MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710/57711/57711E Driver"); + MODULE_LICENSE("GPL"); + MODULE_VERSION(DRV_MODULE_VERSION); +- ++#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ ++#if (LINUX_VERSION_CODE >= 0x020600) /* ! BNX2X_UPSTREAM */ ++MODULE_INFO(cvs_version, "$Revision: #18 $"); ++#endif ++#endif ++ ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ ++static int multi_mode = 1; ++module_param(multi_mode, int, 0); ++#ifdef BNX2X_SAFC ++MODULE_PARM_DESC(multi_mode, " Multi queue mode " ++ "(0 Disable; 1 Enable (default);" ++ " 2 VLAN PRI; 3 E1HOV PRI; 4 IP DSCP)"); ++ ++static int pri_map; ++module_param(pri_map, int, 0); ++MODULE_PARM_DESC(pri_map, " Priority to HW queue mapping"); ++ ++static int qs_per_cos; ++module_param(qs_per_cos, int, 0); ++MODULE_PARM_DESC(qs_per_cos, " Number of queues per HW queue"); ++ ++static int cos_min_rate; ++module_param(cos_min_rate, int, 0); ++MODULE_PARM_DESC(cos_min_rate, " Weight for RR between HW queues"); ++#else /* BNX2X_UPSTREAM */ ++MODULE_PARM_DESC(multi_mode, " Multi queue mode " ++ "(0 Disable; 1 Enable (default))"); ++#endif /* not BNX2X_SAFC */ ++#else /* not BNX2X_NEW_NAPI */ ++static int multi_mode; ++#endif ++ ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ ++static int num_rx_queues; ++module_param(num_rx_queues, int, 0); ++MODULE_PARM_DESC(num_rx_queues, " Number of Rx queues for multi_mode=1" ++ " (default is half number of CPUs)"); ++#endif ++ ++#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */ ++static int num_tx_queues; ++module_param(num_tx_queues, int, 0); ++MODULE_PARM_DESC(num_tx_queues, " Number of Tx queues for multi_mode=1" ++ " (default is half number of CPUs)"); ++#endif ++ ++#if defined(__NO_TPA__) ++static int disable_tpa = 1; ++#else /* BNX2X_UPSTREAM */ + static int disable_tpa; +-static int use_inta; ++module_param(disable_tpa, int, 0); ++MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); ++#endif ++ ++static int int_mode; ++#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */ ++module_param(int_mode, int, 0); ++MODULE_PARM_DESC(int_mode, " Force interrupt mode (1 INT#x; 2 MSI)"); ++#endif ++ ++static int dropless_fc; ++#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */ ++module_param(dropless_fc, int, 0); ++MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); ++#endif ++ + static int poll; ++#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */ ++module_param(poll, int, 0); ++MODULE_PARM_DESC(poll, " Use polling (for debug)"); ++#endif ++ ++static int mrrs = -1; ++#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */ ++module_param(mrrs, int, 0); ++MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); ++#endif ++ + static int debug; ++#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */ ++module_param(debug, int, 0); ++MODULE_PARM_DESC(debug, " Default debug msglevel"); ++#endif ++ + static int load_count[3]; /* 0-common, 1-port0, 2-port1 */ +-static int use_multi; +- +-module_param(disable_tpa, int, 0); +-module_param(use_inta, int, 0); +-module_param(poll, int, 0); +-module_param(debug, int, 0); +-MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature"); +-MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X"); +-MODULE_PARM_DESC(poll, "use polling (for debug)"); +-MODULE_PARM_DESC(debug, "default debug msglevel"); +- +-#ifdef BNX2X_MULTI +-module_param(use_multi, int, 0); +-MODULE_PARM_DESC(use_multi, "use per-CPU queues"); +-#endif ++ + static struct workqueue_struct *bnx2x_wq; + + enum bnx2x_board_type { +@@ -110,18 +212,30 @@ + { "Broadcom NetXtreme II BCM57711E XGb" } + }; + ++#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ ++#ifndef PCI_DEVICE_ID_NX2_57710 ++#define PCI_DEVICE_ID_NX2_57710 0x164e ++#endif ++#ifndef PCI_DEVICE_ID_NX2_57711 ++#define PCI_DEVICE_ID_NX2_57711 0x164f ++#endif ++#ifndef PCI_DEVICE_ID_NX2_57711E ++#define PCI_DEVICE_ID_NX2_57711E 0x1650 ++#endif ++#endif + + static const struct pci_device_id bnx2x_pci_tbl[] = { +- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710, +- PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 }, +- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711, +- PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711 }, +- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711E, +- PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711E }, ++ { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, ++ { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, ++ { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, + { 0 } + }; + + MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */ ++static int bnx2x_netqueue_ops(vmknetddi_queueops_op_t op, void *args); ++#endif + + /**************************************************************************** + * General service functions +@@ -130,7 +244,7 @@ + /* used only at init + * locking is done by mcp + */ +-static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) ++void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) + { + pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); + pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); +@@ -177,7 +291,7 @@ + void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, + u32 len32) + { +- struct dmae_command *dmae = &bp->init_dmae; ++ struct dmae_command dmae; + u32 *wb_comp = bnx2x_sp(bp, wb_comp); + int cnt = 200; + +@@ -190,43 +304,43 @@ + return; + } + +- mutex_lock(&bp->dmae_mutex); +- +- memset(dmae, 0, sizeof(struct dmae_command)); +- +- dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC | +- DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE | +- DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | ++ memset(&dmae, 0, sizeof(struct dmae_command)); ++ ++ dmae.opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC | ++ DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE | ++ DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | + #ifdef __BIG_ENDIAN +- DMAE_CMD_ENDIANITY_B_DW_SWAP | +-#else +- DMAE_CMD_ENDIANITY_DW_SWAP | +-#endif +- (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | +- (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); +- dmae->src_addr_lo = U64_LO(dma_addr); +- dmae->src_addr_hi = U64_HI(dma_addr); +- dmae->dst_addr_lo = dst_addr >> 2; +- dmae->dst_addr_hi = 0; +- dmae->len = len32; +- dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); +- dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); +- dmae->comp_val = DMAE_COMP_VAL; +- +- DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n" ++ DMAE_CMD_ENDIANITY_B_DW_SWAP | ++#else ++ DMAE_CMD_ENDIANITY_DW_SWAP | ++#endif ++ (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | ++ (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); ++ dmae.src_addr_lo = U64_LO(dma_addr); ++ dmae.src_addr_hi = U64_HI(dma_addr); ++ dmae.dst_addr_lo = dst_addr >> 2; ++ dmae.dst_addr_hi = 0; ++ dmae.len = len32; ++ dmae.comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); ++ dmae.comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); ++ dmae.comp_val = DMAE_COMP_VAL; ++ ++ DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n" + DP_LEVEL "src_addr [%x:%08x] len [%d *4] " + "dst_addr [%x:%08x (%08x)]\n" + DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n", +- dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, +- dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr, +- dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val); ++ dmae.opcode, dmae.src_addr_hi, dmae.src_addr_lo, ++ dmae.len, dmae.dst_addr_hi, dmae.dst_addr_lo, dst_addr, ++ dmae.comp_addr_hi, dmae.comp_addr_lo, dmae.comp_val); + DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n", + bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], + bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); + ++ mutex_lock(&bp->dmae_mutex); ++ + *wb_comp = 0; + +- bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); ++ bnx2x_post_dmae(bp, &dmae, INIT_DMAE_C(bp)); + + udelay(5); + +@@ -234,7 +348,7 @@ + DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); + + if (!cnt) { +- BNX2X_ERR("dmae timeout!\n"); ++ BNX2X_ERR("DMAE timeout!\n"); + break; + } + cnt--; +@@ -250,7 +364,7 @@ + + void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) + { +- struct dmae_command *dmae = &bp->init_dmae; ++ struct dmae_command dmae; + u32 *wb_comp = bnx2x_sp(bp, wb_comp); + int cnt = 200; + +@@ -265,48 +379,48 @@ + return; + } + +- mutex_lock(&bp->dmae_mutex); +- +- memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4); +- memset(dmae, 0, sizeof(struct dmae_command)); +- +- dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI | +- DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE | +- DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | ++ memset(&dmae, 0, sizeof(struct dmae_command)); ++ ++ dmae.opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI | ++ DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE | ++ DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | + #ifdef __BIG_ENDIAN +- DMAE_CMD_ENDIANITY_B_DW_SWAP | +-#else +- DMAE_CMD_ENDIANITY_DW_SWAP | +-#endif +- (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | +- (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); +- dmae->src_addr_lo = src_addr >> 2; +- dmae->src_addr_hi = 0; +- dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); +- dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); +- dmae->len = len32; +- dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); +- dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); +- dmae->comp_val = DMAE_COMP_VAL; +- +- DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n" ++ DMAE_CMD_ENDIANITY_B_DW_SWAP | ++#else ++ DMAE_CMD_ENDIANITY_DW_SWAP | ++#endif ++ (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | ++ (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); ++ dmae.src_addr_lo = src_addr >> 2; ++ dmae.src_addr_hi = 0; ++ dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); ++ dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); ++ dmae.len = len32; ++ dmae.comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); ++ dmae.comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); ++ dmae.comp_val = DMAE_COMP_VAL; ++ ++ DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n" + DP_LEVEL "src_addr [%x:%08x] len [%d *4] " + "dst_addr [%x:%08x (%08x)]\n" + DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n", +- dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, +- dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr, +- dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val); +- ++ dmae.opcode, dmae.src_addr_hi, dmae.src_addr_lo, ++ dmae.len, dmae.dst_addr_hi, dmae.dst_addr_lo, src_addr, ++ dmae.comp_addr_hi, dmae.comp_addr_lo, dmae.comp_val); ++ ++ mutex_lock(&bp->dmae_mutex); ++ ++ memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4); + *wb_comp = 0; + +- bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); ++ bnx2x_post_dmae(bp, &dmae, INIT_DMAE_C(bp)); + + udelay(5); + + while (*wb_comp != DMAE_COMP_VAL) { + + if (!cnt) { +- BNX2X_ERR("dmae timeout!\n"); ++ BNX2X_ERR("DMAE timeout!\n"); + break; + } + cnt--; +@@ -321,6 +435,21 @@ + bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); + + mutex_unlock(&bp->dmae_mutex); ++} ++ ++void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, ++ u32 addr, u32 len) ++{ ++ int offset = 0; ++ ++ while (len > DMAE_LEN32_WR_MAX) { ++ bnx2x_write_dmae(bp, phys_addr + offset, ++ addr + offset, DMAE_LEN32_WR_MAX); ++ offset += DMAE_LEN32_WR_MAX * 4; ++ len -= DMAE_LEN32_WR_MAX; ++ } ++ ++ bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); + } + + /* used only for slowpath so not inlined */ +@@ -468,7 +597,7 @@ + static void bnx2x_fw_dump(struct bnx2x *bp) + { + u32 mark, offset; +- u32 data[9]; ++ __be32 data[9]; + int word; + + mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104); +@@ -502,84 +631,111 @@ + + BNX2X_ERR("begin crash dump -----------------\n"); + +- for_each_queue(bp, i) { +- struct bnx2x_fastpath *fp = &bp->fp[i]; +- struct eth_tx_db_data *hw_prods = fp->hw_tx_prods; +- +- BNX2X_ERR("queue[%d]: tx_pkt_prod(%x) tx_pkt_cons(%x)" +- " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)\n", +- i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod, +- fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb)); +- BNX2X_ERR(" rx_bd_prod(%x) rx_bd_cons(%x)" +- " *rx_bd_cons_sb(%x) rx_comp_prod(%x)" +- " rx_comp_cons(%x) *rx_cons_sb(%x)\n", +- fp->rx_bd_prod, fp->rx_bd_cons, +- le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod, +- fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); +- BNX2X_ERR(" rx_sge_prod(%x) last_max_sge(%x)" +- " fp_c_idx(%x) *sb_c_idx(%x) fp_u_idx(%x)" +- " *sb_u_idx(%x) bd data(%x,%x)\n", +- fp->rx_sge_prod, fp->last_max_sge, fp->fp_c_idx, +- fp->status_blk->c_status_block.status_block_index, +- fp->fp_u_idx, +- fp->status_blk->u_status_block.status_block_index, +- hw_prods->packets_prod, hw_prods->bds_prod); +- +- start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10); +- end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245); +- for (j = start; j < end; j++) { +- struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j]; +- +- BNX2X_ERR("packet[%x]=[%p,%x]\n", j, +- sw_bd->skb, sw_bd->first_bd); +- } +- +- start = TX_BD(fp->tx_bd_cons - 10); +- end = TX_BD(fp->tx_bd_cons + 254); +- for (j = start; j < end; j++) { +- u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j]; +- +- BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n", +- j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]); +- } +- +- start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); +- end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); +- for (j = start; j < end; j++) { +- u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; +- struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; +- +- BNX2X_ERR("rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", +- j, rx_bd[1], rx_bd[0], sw_bd->skb); +- } +- +- start = RX_SGE(fp->rx_sge_prod); +- end = RX_SGE(fp->last_max_sge); +- for (j = start; j < end; j++) { +- u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; +- struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; +- +- BNX2X_ERR("rx_sge[%x]=[%x:%x] sw_page=[%p]\n", +- j, rx_sge[1], rx_sge[0], sw_page->page); +- } +- +- start = RCQ_BD(fp->rx_comp_cons - 10); +- end = RCQ_BD(fp->rx_comp_cons + 503); +- for (j = start; j < end; j++) { +- u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; +- +- BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n", +- j, cqe[0], cqe[1], cqe[2], cqe[3]); +- } +- } +- ++ /* Indices */ ++ /* Common */ + BNX2X_ERR("def_c_idx(%u) def_u_idx(%u) def_x_idx(%u)" + " def_t_idx(%u) def_att_idx(%u) attn_state(%u)" + " spq_prod_idx(%u)\n", + bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx, + bp->def_att_idx, bp->attn_state, bp->spq_prod_idx); + ++ /* Rx */ ++ for_each_rx_queue(bp, i) { ++ struct bnx2x_fastpath *fp = &bp->fp[i]; ++ ++ BNX2X_ERR("fp%d: rx_bd_prod(%x) rx_bd_cons(%x)" ++ " *rx_bd_cons_sb(%x) rx_comp_prod(%x)" ++ " rx_comp_cons(%x) *rx_cons_sb(%x)\n", ++ i, fp->rx_bd_prod, fp->rx_bd_cons, ++ le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod, ++ fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); ++ BNX2X_ERR(" rx_sge_prod(%x) last_max_sge(%x)" ++ " fp_u_idx(%x) *sb_u_idx(%x)\n", ++ fp->rx_sge_prod, fp->last_max_sge, ++ le16_to_cpu(fp->fp_u_idx), ++ fp->status_blk->u_status_block.status_block_index); ++ } ++ ++ /* Tx */ ++ for_each_tx_queue(bp, i) { ++ struct bnx2x_fastpath *fp = &bp->fp[i]; ++ ++ BNX2X_ERR("fp%d: tx_pkt_prod(%x) tx_pkt_cons(%x)" ++ " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)\n", ++ i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod, ++ fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb)); ++ BNX2X_ERR(" fp_c_idx(%x) *sb_c_idx(%x)" ++ " tx_db_prod(%x)\n", le16_to_cpu(fp->fp_c_idx), ++ fp->status_blk->c_status_block.status_block_index, ++ fp->tx_db.data.prod); ++ } ++ ++ /* Rings */ ++ /* Rx */ ++ for_each_rx_queue(bp, i) { ++ struct bnx2x_fastpath *fp = &bp->fp[i]; ++ ++ start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); ++ end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); ++ for (j = start; j != end; j = RX_BD(j + 1)) { ++ u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; ++ struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; ++ ++ BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", ++ i, j, rx_bd[1], rx_bd[0], sw_bd->skb); ++ } ++ ++ start = RX_SGE(fp->rx_sge_prod); ++ end = RX_SGE(fp->last_max_sge); ++ for (j = start; j != end; j = RX_SGE(j + 1)) { ++ u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; ++ struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; ++ ++ BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", ++ i, j, rx_sge[1], rx_sge[0], sw_page->page); ++ } ++ ++ start = RCQ_BD(fp->rx_comp_cons - 10); ++ end = RCQ_BD(fp->rx_comp_cons + 503); ++ for (j = start; j != end; j = RCQ_BD(j + 1)) { ++ u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; ++ ++ BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", ++ i, j, cqe[0], cqe[1], cqe[2], cqe[3]); ++ } ++ } ++ ++ /* Tx */ ++ for_each_tx_queue(bp, i) { ++ struct bnx2x_fastpath *fp = &bp->fp[i]; ++ ++ start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10); ++ end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245); ++ for (j = start; j != end; j = TX_BD(j + 1)) { ++ struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j]; ++ ++ BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n", ++ i, j, sw_bd->skb, sw_bd->first_bd); ++ } ++ ++ start = TX_BD(fp->tx_bd_cons - 10); ++ end = TX_BD(fp->tx_bd_cons + 254); ++ for (j = start; j != end; j = TX_BD(j + 1)) { ++ u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j]; ++ ++ BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n", ++ i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]); ++ } ++ } ++ + bnx2x_fw_dump(bp); ++#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ ++ bp->msglevel |= NETIF_MSG_PROBE; ++ BNX2X_ERR("Idle check (1st round) ----------\n"); ++ bnx2x_idle_chk(bp); ++ BNX2X_ERR("Idle check (2nd round) ----------\n"); ++ bnx2x_idle_chk(bp); ++#endif + bnx2x_mc_assert(bp); + BNX2X_ERR("end crash dump -----------------\n"); + } +@@ -590,10 +746,17 @@ + u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; + u32 val = REG_RD(bp, addr); + int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; ++ int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; + + if (msix) { +- val &= ~HC_CONFIG_0_REG_SINGLE_ISR_EN_0; ++ val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | ++ HC_CONFIG_0_REG_INT_LINE_EN_0); + val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | ++ HC_CONFIG_0_REG_ATTN_BIT_EN_0); ++ } else if (msi) { ++ val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; ++ val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | ++ HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | + HC_CONFIG_0_REG_ATTN_BIT_EN_0); + } else { + val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | +@@ -601,32 +764,36 @@ + HC_CONFIG_0_REG_INT_LINE_EN_0 | + HC_CONFIG_0_REG_ATTN_BIT_EN_0); + +- DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n", +- val, port, addr, msix); ++ DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", ++ val, port, addr); + + REG_WR(bp, addr, val); + + val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; + } + +- DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n", +- val, port, addr, msix); ++ DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", ++ val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); + + REG_WR(bp, addr, val); ++ barrier(); + + if (CHIP_IS_E1H(bp)) { + /* init leading/trailing edge */ + if (IS_E1HMF(bp)) { +- val = (0xfe0f | (1 << (BP_E1HVN(bp) + 4))); ++ val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); + if (bp->port.pmf) +- /* enable nig attention */ +- val |= 0x0100; ++ /* enable nig and gpio3 attention */ ++ val |= 0x1100; + } else + val = 0xffff; + + REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); + REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); + } ++ ++ /* Make sure that interrupts are indeed enabled from here on */ ++ mmiowb(); + } + + static void bnx2x_int_disable(struct bnx2x *bp) +@@ -643,6 +810,9 @@ + DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", + val, port, addr); + ++ /* flush all outstanding writes */ ++ mmiowb(); ++ + REG_WR(bp, addr, val); + if (REG_RD(bp, addr) != val) + BNX2X_ERR("BUG! proper val not read from IGU!\n"); +@@ -650,28 +820,50 @@ + + static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) + { ++#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */ + int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; +- int i; ++ int i, offset; ++#endif ++#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */ ++ int j; ++#endif + + /* disable interrupt handling */ + atomic_inc(&bp->intr_sem); ++ smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */ ++ + if (disable_hw) + /* prevent the HW from sending interrupts */ + bnx2x_int_disable(bp); + + /* make sure all ISRs are done */ ++#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */ + if (msix) { ++ synchronize_irq(bp->msix_table[0].vector); ++ offset = 1; ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ offset++; ++#endif + for_each_queue(bp, i) +- synchronize_irq(bp->msix_table[i].vector); +- +- /* one more for the Slow Path IRQ */ +- synchronize_irq(bp->msix_table[i].vector); ++ synchronize_irq(bp->msix_table[i + offset].vector); + } else ++#endif + synchronize_irq(bp->pdev->irq); + + /* make sure sp_task is not running */ ++#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */ + cancel_delayed_work(&bp->sp_task); + flush_workqueue(bnx2x_wq); ++#else ++ j = 0; ++ smp_mb(); /* sp_running is set by sp_task */ ++ while (bp->sp_running) { ++ if (!(++j % 1000)) ++ BNX2X_ERR("sp_running (j %d)\n", j); ++ msleep(1); ++ smp_mb(); ++ } ++#endif + } + + /* fast path */ +@@ -694,9 +886,17 @@ + (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | + (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); + ++#if (LINUX_VERSION_CODE < 0x020600) /* ! BNX2X_UPSTREAM */ ++ /* x86's writel() in 2.4.x does not have barrier(). */ ++ barrier(); ++#endif + DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n", + (*(u32 *)&igu_ack), hc_addr); + REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); ++ ++ /* Make sure that ACK is written */ ++ mmiowb(); ++ barrier(); + } + + static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) +@@ -733,22 +933,11 @@ + * fast path service functions + */ + +-static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp) +-{ +- u16 tx_cons_sb; +- +- /* Tell compiler that status block fields can change */ +- barrier(); +- tx_cons_sb = le16_to_cpu(*fp->tx_cons_sb); +- return (fp->tx_pkt_cons != tx_cons_sb); +-} +- + static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp) + { + /* Tell compiler that consumer and producer can change */ + barrier(); + return (fp->tx_pkt_prod != fp->tx_pkt_cons); +- + } + + /* free skb in the packet ring at pos idx +@@ -758,61 +947,60 @@ + u16 idx) + { + struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx]; +- struct eth_tx_bd *tx_bd; ++ struct eth_tx_start_bd *tx_start_bd; ++ struct eth_tx_bd *tx_data_bd; + struct sk_buff *skb = tx_buf->skb; + u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons; + int nbd; + ++ /* prefetch skb end pointer to speedup dev_kfree_skb() */ ++ prefetch(&skb->end); ++ + DP(BNX2X_MSG_OFF, "pkt_idx %d buff @(%p)->skb %p\n", + idx, tx_buf, skb); + + /* unmap first bd */ + DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx); +- tx_bd = &fp->tx_desc_ring[bd_idx]; +- pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd), +- BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE); +- +- nbd = le16_to_cpu(tx_bd->nbd) - 1; +- new_cons = nbd + tx_buf->first_bd; +-#ifdef BNX2X_STOP_ON_ERROR +- if (nbd > (MAX_SKB_FRAGS + 2)) { ++ tx_start_bd = &fp->tx_desc_ring[bd_idx].start_bd; ++ pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_start_bd), ++ BD_UNMAP_LEN(tx_start_bd), PCI_DMA_TODEVICE); ++ ++ nbd = le16_to_cpu(tx_start_bd->nbd) - 1; ++#ifdef BNX2X_STOP_ON_ERROR ++ if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) { + BNX2X_ERR("BAD nbd!\n"); + bnx2x_panic(); + } + #endif +- +- /* Skip a parse bd and the TSO split header bd +- since they have no mapping */ +- if (nbd) ++ new_cons = nbd + tx_buf->first_bd; ++ ++ /* Get the next bd */ ++ bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); ++ ++ /* Skip a parse bd... */ ++ --nbd; ++ bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); ++ ++ /* ...and the TSO split header bd since they have no mapping */ ++ if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) { ++ --nbd; + bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); +- +- if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM | +- ETH_TX_BD_FLAGS_TCP_CSUM | +- ETH_TX_BD_FLAGS_SW_LSO)) { ++ } ++ ++ /* now free frags */ ++ while (nbd > 0) { ++ ++ DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx); ++ tx_data_bd = &fp->tx_desc_ring[bd_idx].reg_bd; ++ pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_data_bd), ++ BD_UNMAP_LEN(tx_data_bd), PCI_DMA_TODEVICE); + if (--nbd) + bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); +- tx_bd = &fp->tx_desc_ring[bd_idx]; +- /* is this a TSO split header bd? */ +- if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) { +- if (--nbd) +- bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); +- } +- } +- +- /* now free frags */ +- while (nbd > 0) { +- +- DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx); +- tx_bd = &fp->tx_desc_ring[bd_idx]; +- pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd), +- BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE); +- if (--nbd) +- bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); + } + + /* release skb */ + WARN_ON(!skb); +- dev_kfree_skb(skb); ++ dev_kfree_skb_any(skb); + tx_buf->first_bd = 0; + tx_buf->skb = NULL; + +@@ -842,9 +1030,12 @@ + return (s16)(fp->bp->tx_ring_size) - used; + } + +-static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work) ++static void bnx2x_tx_int(struct bnx2x_fastpath *fp) + { + struct bnx2x *bp = fp->bp; ++#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */ ++ struct netdev_queue *txq; ++#endif + u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons; + int done = 0; + +@@ -853,6 +1044,9 @@ + return; + #endif + ++#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */ ++ txq = netdev_get_tx_queue(bp->dev, fp->index - bp->num_rx_queues); ++#endif + hw_cons = le16_to_cpu(*fp->tx_cons_sb); + sw_cons = fp->tx_pkt_cons; + +@@ -874,35 +1068,45 @@ + bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons); + sw_cons++; + done++; +- +- if (done == work) +- break; + } + + fp->tx_pkt_cons = sw_cons; + fp->tx_bd_cons = bd_cons; + +- /* Need to make the tx_cons update visible to start_xmit() +- * before checking for netif_queue_stopped(). Without the +- * memory barrier, there is a small possibility that start_xmit() +- * will miss it and cause the queue to be stopped forever. +- */ +- smp_mb(); +- + /* TBD need a thresh? */ ++#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */ ++ if (unlikely(netif_tx_queue_stopped(txq))) { ++ ++ /* Need to make the tx_bd_cons update visible to start_xmit() ++ * before checking for netif_tx_queue_stopped(). Without the ++ * memory barrier, there is a small possibility that ++ * start_xmit() will miss it and cause the queue to be stopped ++ * forever. ++ */ ++ smp_mb(); ++ ++ if ((netif_tx_queue_stopped(txq)) && ++ (bp->state == BNX2X_STATE_OPEN) && ++ (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)) ++ netif_tx_wake_queue(txq); ++ } ++#else + if (unlikely(netif_queue_stopped(bp->dev))) { + +- netif_tx_lock(bp->dev); ++ /* See above */ ++ smp_mb(); + + if (netif_queue_stopped(bp->dev) && + (bp->state == BNX2X_STATE_OPEN) && + (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)) + netif_wake_queue(bp->dev); +- +- netif_tx_unlock(bp->dev); +- } +-} +- ++ } ++#endif ++} ++ ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid); ++#endif + + static void bnx2x_sp_event(struct bnx2x_fastpath *fp, + union eth_rx_cqe *rr_cqe) +@@ -913,12 +1117,12 @@ + + DP(BNX2X_MSG_SP, + "fp %d cid %d got ramrod #%d state is %x type is %d\n", +- FP_IDX(fp), cid, command, bp->state, ++ fp->index, cid, command, bp->state, + rr_cqe->ramrod_cqe.ramrod_type); + + bp->spq_left++; + +- if (FP_IDX(fp)) { ++ if (fp->index) { + switch (command | fp->state) { + case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | + BNX2X_FP_STATE_OPENING): +@@ -959,6 +1163,12 @@ + bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED; + break; + ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_OPEN): ++ DP(NETIF_MSG_IFDOWN, "got delete ramrod for CID %d\n", cid); ++ bnx2x_cnic_cfc_comp(bp, cid); ++ break; ++#endif + + case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN): + case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG): +@@ -967,6 +1177,7 @@ + break; + + case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT): ++ case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DISABLED): + DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n"); + break; + +@@ -1020,7 +1231,11 @@ + + mapping = pci_map_page(bp->pdev, page, 0, SGE_PAGE_SIZE*PAGES_PER_SGE, + PCI_DMA_FROMDEVICE); ++#if (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */ + if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { ++#else ++ if (unlikely(dma_mapping_error(mapping))) { ++#endif + __free_pages(page, PAGES_PER_SGE_SHIFT); + return -ENOMEM; + } +@@ -1048,7 +1263,11 @@ + + mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_size, + PCI_DMA_FROMDEVICE); ++#if (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */ + if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { ++#else ++ if (unlikely(dma_mapping_error(mapping))) { ++#endif + dev_kfree_skb(skb); + return -ENOMEM; + } +@@ -1078,8 +1297,7 @@ + + pci_dma_sync_single_for_device(bp->pdev, + pci_unmap_addr(cons_rx_buf, mapping), +- bp->rx_offset + RX_COPY_THRESH, +- PCI_DMA_FROMDEVICE); ++ RX_COPY_THRESH, PCI_DMA_FROMDEVICE); + + prod_rx_buf->skb = cons_rx_buf->skb; + pci_unmap_addr_set(prod_rx_buf, mapping, +@@ -1087,6 +1305,7 @@ + *prod_bd = *cons_bd; + } + ++#if !defined(__NO_TPA__) /* BNX2X_UPSTREAM */ + static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp, + u16 idx) + { +@@ -1206,10 +1425,18 @@ + + #ifdef BNX2X_STOP_ON_ERROR + fp->tpa_queue_used |= (1 << queue); +-#ifdef __powerpc64__ ++#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */ ++#ifdef _ASM_GENERIC_INT_L64_H + DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n", + #else + DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n", ++#endif ++#else ++#if defined(__powerpc64__) || defined(_ASM_IA64_TYPES_H) ++ DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n", ++#else ++ DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n", ++#endif + #endif + fp->tpa_queue_used); + #endif +@@ -1260,7 +1487,7 @@ + where we are and drop the whole packet */ + err = bnx2x_alloc_rx_sge(bp, fp, sge_idx); + if (unlikely(err)) { +- bp->eth_stats.rx_skb_alloc_failed++; ++ fp->eth_q_stats.rx_skb_alloc_failed++; + return err; + } + +@@ -1357,7 +1584,9 @@ + dev_kfree_skb(skb); + } + ++#if (LINUX_VERSION_CODE < 0x02061b) /* ! BNX2X_UPSTREAM */ + bp->dev->last_rx = jiffies; ++#endif + + /* put new skb in bin */ + fp->tpa_pool[queue].skb = new_skb; +@@ -1366,18 +1595,19 @@ + /* else drop the packet and keep the buffer in the bin */ + DP(NETIF_MSG_RX_STATUS, + "Failed to allocate new skb - dropping packet!\n"); +- bp->eth_stats.rx_skb_alloc_failed++; ++ fp->eth_q_stats.rx_skb_alloc_failed++; + } + + fp->tpa_state[queue] = BNX2X_TPA_STOP; + } ++#endif + + static inline void bnx2x_update_rx_prod(struct bnx2x *bp, + struct bnx2x_fastpath *fp, + u16 bd_prod, u16 rx_comp_prod, + u16 rx_sge_prod) + { +- struct tstorm_eth_rx_producers rx_prods = {0}; ++ struct ustorm_eth_rx_producers rx_prods = {0}; + int i; + + /* Update producers */ +@@ -1395,16 +1625,16 @@ + */ + wmb(); + +- for (i = 0; i < sizeof(struct tstorm_eth_rx_producers)/4; i++) +- REG_WR(bp, BAR_TSTRORM_INTMEM + +- TSTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4, ++ for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++) ++ REG_WR(bp, BAR_USTRORM_INTMEM + ++ USTORM_RX_PRODS_OFFSET(BP_PORT(bp), fp->cl_id) + i*4, + ((u32 *)&rx_prods)[i]); + + mmiowb(); /* keep prod updates ordered */ + + DP(NETIF_MSG_RX_STATUS, +- "Wrote: bd_prod %u cqe_prod %u sge_prod %u\n", +- bd_prod, rx_comp_prod, rx_sge_prod); ++ "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", ++ fp->index, bd_prod, rx_comp_prod, rx_sge_prod); + } + + static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget) +@@ -1438,7 +1668,7 @@ + + DP(NETIF_MSG_RX_STATUS, + "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n", +- FP_IDX(fp), hw_comp_cons, sw_comp_cons); ++ fp->index, hw_comp_cons, sw_comp_cons); + + while (sw_comp_cons != hw_comp_cons) { + struct sw_rx_bd *rx_buf = NULL; +@@ -1451,6 +1681,13 @@ + bd_prod = RX_BD(bd_prod); + bd_cons = RX_BD(bd_cons); + ++ /* Prefetch the page containing the BD descriptor ++ at producer's index. It will be needed when new skb is ++ allocated */ ++ prefetch((void *)(PAGE_ALIGN((unsigned long) ++ (&fp->rx_desc_ring[bd_prod])) - ++ PAGE_SIZE + 1)); ++ + cqe = &fp->rx_comp_ring[comp_ring_cons]; + cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; + +@@ -1473,6 +1710,7 @@ + len = le16_to_cpu(cqe->fast_path_cqe.pkt_len); + pad = cqe->fast_path_cqe.placement_offset; + ++#if !defined(__NO_TPA__) /* BNX2X_UPSTREAM */ + /* If CQE is marked both TPA_START and TPA_END + it is a non-TPA CQE */ + if ((!fp->disable_tpa) && +@@ -1507,7 +1745,7 @@ + len, cqe, comp_ring_cons); + #ifdef BNX2X_STOP_ON_ERROR + if (bp->panic) +- return -EINVAL; ++ return 0; + #endif + + bnx2x_update_sge_prod(fp, +@@ -1515,6 +1753,7 @@ + goto next_cqe; + } + } ++#endif + + pci_dma_sync_single_for_device(bp->pdev, + pci_unmap_addr(rx_buf, mapping), +@@ -1528,7 +1767,7 @@ + DP(NETIF_MSG_RX_ERR, + "ERROR flags %x rx packet %u\n", + cqe_fp_flags, sw_comp_cons); +- bp->eth_stats.rx_err_discard_pkt++; ++ fp->eth_q_stats.rx_err_discard_pkt++; + goto reuse_rx; + } + +@@ -1545,7 +1784,7 @@ + DP(NETIF_MSG_RX_ERR, + "ERROR packet dropped " + "because of alloc failure\n"); +- bp->eth_stats.rx_skb_alloc_failed++; ++ fp->eth_q_stats.rx_skb_alloc_failed++; + goto reuse_rx; + } + +@@ -1559,7 +1798,8 @@ + + skb = new_skb; + +- } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) { ++ } else ++ if (likely(bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0)) { + pci_unmap_single(bp->pdev, + pci_unmap_addr(rx_buf, mapping), + bp->rx_buf_size, +@@ -1571,7 +1811,7 @@ + DP(NETIF_MSG_RX_ERR, + "ERROR packet dropped because " + "of alloc failure\n"); +- bp->eth_stats.rx_skb_alloc_failed++; ++ fp->eth_q_stats.rx_skb_alloc_failed++; + reuse_rx: + bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod); + goto next_rx; +@@ -1584,9 +1824,16 @@ + if (likely(BNX2X_RX_CSUM_OK(cqe))) + skb->ip_summed = CHECKSUM_UNNECESSARY; + else +- bp->eth_stats.hw_csum_err++; +- } +- } ++ fp->eth_q_stats.hw_csum_err++; ++ } ++ } ++ ++ skb_record_rx_queue(skb, fp->index); ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */ ++ vmknetddi_queueops_set_skb_queueid(skb, ++ VMKNETDDI_QUEUEOPS_MK_RX_QUEUEID(fp->index)); ++#endif + + #ifdef BCM_VLAN + if ((bp->vlgrp != NULL) && (bp->flags & HW_VLAN_RX_FLAG) && +@@ -1598,7 +1845,9 @@ + #endif + netif_receive_skb(skb); + ++#if (LINUX_VERSION_CODE < 0x02061b) /* ! BNX2X_UPSTREAM */ + bp->dev->last_rx = jiffies; ++#endif + + next_rx: + rx_buf->skb = NULL; +@@ -1630,12 +1879,16 @@ + return rx_pkt; + } + ++#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */ ++#if (LINUX_VERSION_CODE < 0x020613) && (VMWARE_ESX_DDK_VERSION < 4000) ++static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie, ++ struct pt_regs *regs) ++#else /* BNX2X_UPSTREAM */ + static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie) ++#endif + { + struct bnx2x_fastpath *fp = fp_cookie; + struct bnx2x *bp = fp->bp; +- struct net_device *dev = bp->dev; +- int index = FP_IDX(fp); + + /* Return here if interrupt is disabled */ + if (unlikely(atomic_read(&bp->intr_sem) != 0)) { +@@ -1644,37 +1897,57 @@ + } + + DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n", +- index, FP_SB_ID(fp)); +- bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0); ++ fp->index, fp->sb_id); ++ bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); + + #ifdef BNX2X_STOP_ON_ERROR + if (unlikely(bp->panic)) + return IRQ_HANDLED; + #endif +- +- prefetch(fp->rx_cons_sb); +- prefetch(fp->tx_cons_sb); +- prefetch(&fp->status_blk->c_status_block.status_block_index); +- prefetch(&fp->status_blk->u_status_block.status_block_index); +- +- netif_rx_schedule(dev, &bnx2x_fp(bp, index, napi)); ++ /* Handle Rx or Tx according to MSI-X vector */ ++ if (fp->is_rx_queue) { ++ prefetch(fp->rx_cons_sb); ++ prefetch(&fp->status_blk->u_status_block.status_block_index); ++ ++ napi_schedule(&bnx2x_fp(bp, fp->index, napi)); ++ ++ } else { ++ prefetch(fp->tx_cons_sb); ++ prefetch(&fp->status_blk->c_status_block.status_block_index); ++ ++ bnx2x_update_fpsb_idx(fp); ++ rmb(); ++ bnx2x_tx_int(fp); ++ ++ /* Re-enable interrupts */ ++ bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID, ++ le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1); ++ bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID, ++ le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1); ++ } + + return IRQ_HANDLED; + } +- ++#endif ++ ++#if (LINUX_VERSION_CODE < 0x020613) && (VMWARE_ESX_DDK_VERSION < 40000) ++static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance, ++ struct pt_regs *regs) ++#else /* BNX2X_UPSTREAM */ + static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) +-{ +- struct net_device *dev = dev_instance; +- struct bnx2x *bp = netdev_priv(dev); ++#endif ++{ ++ struct bnx2x *bp = netdev_priv(dev_instance); + u16 status = bnx2x_ack_int(bp); + u16 mask; ++ int i; + + /* Return here if interrupt is shared and it's not for us */ + if (unlikely(status == 0)) { + DP(NETIF_MSG_INTR, "not our interrupt!\n"); + return IRQ_NONE; + } +- DP(NETIF_MSG_INTR, "got an interrupt status %u\n", status); ++ DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); + + /* Return here if interrupt is disabled */ + if (unlikely(atomic_read(&bp->intr_sem) != 0)) { +@@ -1687,23 +1960,61 @@ + return IRQ_HANDLED; + #endif + +- mask = 0x2 << bp->fp[0].sb_id; ++ for (i = 0; i < BNX2X_NUM_QUEUES(bp); i++) { ++ struct bnx2x_fastpath *fp = &bp->fp[i]; ++ ++ mask = 0x2 << fp->sb_id; ++ if (status & mask) { ++ /* Handle Rx or Tx according to SB id */ ++ if (fp->is_rx_queue) { ++ prefetch(fp->rx_cons_sb); ++ prefetch(&fp->status_blk->u_status_block. ++ status_block_index); ++ ++ napi_schedule(&bnx2x_fp(bp, fp->index, napi)); ++ ++ } else { ++ prefetch(fp->tx_cons_sb); ++ prefetch(&fp->status_blk->c_status_block. ++ status_block_index); ++ ++ bnx2x_update_fpsb_idx(fp); ++ rmb(); ++ bnx2x_tx_int(fp); ++ ++ /* Re-enable interrupts */ ++ bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID, ++ le16_to_cpu(fp->fp_u_idx), ++ IGU_INT_NOP, 1); ++ bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID, ++ le16_to_cpu(fp->fp_c_idx), ++ IGU_INT_ENABLE, 1); ++ } ++ status &= ~mask; ++ } ++ } ++ ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ mask = 0x2 << CNIC_SB_ID(bp); + if (status & mask) { +- struct bnx2x_fastpath *fp = &bp->fp[0]; +- +- prefetch(fp->rx_cons_sb); +- prefetch(fp->tx_cons_sb); +- prefetch(&fp->status_blk->c_status_block.status_block_index); +- prefetch(&fp->status_blk->u_status_block.status_block_index); +- +- netif_rx_schedule(dev, &bnx2x_fp(bp, 0, napi)); ++ struct cnic_ops *c_ops = NULL; ++ ++ rcu_read_lock(); ++ c_ops = rcu_dereference(bp->cnic_ops); ++ if (c_ops) ++ c_ops->cnic_handler(bp->cnic_data, NULL); ++ rcu_read_unlock(); + + status &= ~mask; + } +- ++#endif + + if (unlikely(status & 0x1)) { ++#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */ + queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); ++#else ++ queue_work(bnx2x_wq, &bp->sp_task); ++#endif + + status &= ~0x1; + if (!status) +@@ -1809,27 +2120,21 @@ + /* HW Lock for shared dual port PHYs */ + static void bnx2x_acquire_phy_lock(struct bnx2x *bp) + { +- u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); +- + mutex_lock(&bp->port.phy_mutex); + +- if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) || +- (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) +- bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO); ++ if (bp->port.need_hw_lock) ++ bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO); + } + + static void bnx2x_release_phy_lock(struct bnx2x *bp) + { +- u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); +- +- if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) || +- (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) +- bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO); ++ if (bp->port.need_hw_lock) ++ bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO); + + mutex_unlock(&bp->port.phy_mutex); + } + +-int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) ++int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) + { + /* The GPIO should be swapped if swap register is set and active */ + int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && +@@ -1838,6 +2143,36 @@ + (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); + u32 gpio_mask = (1 << gpio_shift); + u32 gpio_reg; ++ int value; ++ ++ if (gpio_num > MISC_REGISTERS_GPIO_3) { ++ BNX2X_ERR("Invalid GPIO %d\n", gpio_num); ++ return -EINVAL; ++ } ++ ++ /* read GPIO value */ ++ gpio_reg = REG_RD(bp, MISC_REG_GPIO); ++ ++ /* get the requested pin value */ ++ if ((gpio_reg & gpio_mask) == gpio_mask) ++ value = 1; ++ else ++ value = 0; ++ ++ DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); ++ ++ return value; ++} ++ ++int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) ++{ ++ /* The GPIO should be swapped if swap register is set and active */ ++ int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && ++ REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; ++ int gpio_shift = gpio_num + ++ (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); ++ u32 gpio_mask = (1 << gpio_shift); ++ u32 gpio_reg; + + if (gpio_num > MISC_REGISTERS_GPIO_3) { + BNX2X_ERR("Invalid GPIO %d\n", gpio_num); +@@ -1882,6 +2217,52 @@ + return 0; + } + ++int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) ++{ ++ /* The GPIO should be swapped if swap register is set and active */ ++ int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && ++ REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; ++ int gpio_shift = gpio_num + ++ (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); ++ u32 gpio_mask = (1 << gpio_shift); ++ u32 gpio_reg; ++ ++ if (gpio_num > MISC_REGISTERS_GPIO_3) { ++ BNX2X_ERR("Invalid GPIO %d\n", gpio_num); ++ return -EINVAL; ++ } ++ ++ bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); ++ /* read GPIO int */ ++ gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); ++ ++ switch (mode) { ++ case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: ++ DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " ++ "output low\n", gpio_num, gpio_shift); ++ /* clear SET and set CLR */ ++ gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); ++ gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); ++ break; ++ ++ case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: ++ DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " ++ "output high\n", gpio_num, gpio_shift); ++ /* clear CLR and set SET */ ++ gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); ++ gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); ++ break; ++ ++ default: ++ break; ++ } ++ ++ REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); ++ bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); ++ ++ return 0; ++} ++ + static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) + { + u32 spio_mask = (1 << spio_num); +@@ -1936,13 +2317,16 @@ + bp->port.advertising &= ~(ADVERTISED_Asym_Pause | + ADVERTISED_Pause); + break; ++ + case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: + bp->port.advertising |= (ADVERTISED_Asym_Pause | + ADVERTISED_Pause); + break; ++ + case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: + bp->port.advertising |= ADVERTISED_Asym_Pause; + break; ++ + default: + bp->port.advertising &= ~(ADVERTISED_Asym_Pause | + ADVERTISED_Pause); +@@ -1952,6 +2336,12 @@ + + static void bnx2x_link_report(struct bnx2x *bp) + { ++ if (bp->state == BNX2X_STATE_DISABLED) { ++ netif_carrier_off(bp->dev); ++ printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name); ++ return; ++ } ++ + if (bp->link_vars.link_up) { + if (bp->state == BNX2X_STATE_OPEN) + netif_carrier_on(bp->dev); +@@ -1964,10 +2354,11 @@ + else + printk("half duplex"); + +- if (bp->link_vars.flow_ctrl != FLOW_CTRL_NONE) { +- if (bp->link_vars.flow_ctrl & FLOW_CTRL_RX) { ++ if (bp->link_vars.flow_ctrl != BNX2X_FLOW_CTRL_NONE) { ++ if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) { + printk(", receive "); +- if (bp->link_vars.flow_ctrl & FLOW_CTRL_TX) ++ if (bp->link_vars.flow_ctrl & ++ BNX2X_FLOW_CTRL_TX) + printk("& transmit "); + } else { + printk(", transmit "); +@@ -1982,7 +2373,7 @@ + } + } + +-static u8 bnx2x_initial_phy_init(struct bnx2x *bp) ++static u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) + { + if (!BP_NOMCP(bp)) { + u8 rc; +@@ -1990,26 +2381,30 @@ + /* Initialize link parameters structure variables */ + /* It is recommended to turn off RX FC for jumbo frames + for better performance */ +- if (IS_E1HMF(bp)) +- bp->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH; +- else if (bp->dev->mtu > 5000) +- bp->link_params.req_fc_auto_adv = FLOW_CTRL_TX; +- else +- bp->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH; ++ if (bp->dev->mtu > 5000) ++ bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; ++ else ++ bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; + + bnx2x_acquire_phy_lock(bp); ++ ++ if (load_mode == LOAD_DIAG) ++ bp->link_params.loopback_mode = LOOPBACK_XGXS_10; ++ + rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); ++ + bnx2x_release_phy_lock(bp); + + bnx2x_calc_fc_adv(bp); + +- if (bp->link_vars.link_up) ++ if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { ++ bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); + bnx2x_link_report(bp); +- ++ } + + return rc; + } +- BNX2X_ERR("Bootcode is missing -not initializing link\n"); ++ BNX2X_ERR("Bootcode is missing - can not initialize link\n"); + return -EINVAL; + } + +@@ -2022,17 +2417,17 @@ + + bnx2x_calc_fc_adv(bp); + } else +- BNX2X_ERR("Bootcode is missing -not setting link\n"); ++ BNX2X_ERR("Bootcode is missing - can not set link\n"); + } + + static void bnx2x__link_reset(struct bnx2x *bp) + { + if (!BP_NOMCP(bp)) { + bnx2x_acquire_phy_lock(bp); +- bnx2x_link_reset(&bp->link_params, &bp->link_vars); ++ bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); + bnx2x_release_phy_lock(bp); + } else +- BNX2X_ERR("Bootcode is missing -not resetting link\n"); ++ BNX2X_ERR("Bootcode is missing - can not reset link\n"); + } + + static u8 bnx2x_link_test(struct bnx2x *bp) +@@ -2046,119 +2441,82 @@ + return rc; + } + ++static void bnx2x_init_port_minmax(struct bnx2x *bp) ++{ ++ u32 r_param = bp->link_vars.line_speed / 8; ++ u32 fair_periodic_timeout_usec; ++ u32 t_fair; ++ ++ memset(&(bp->cmng.rs_vars), 0, ++ sizeof(struct rate_shaping_vars_per_port)); ++ memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); ++ ++ /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ ++ bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; ++ ++ /* this is the threshold below which no timer arming will occur ++ 1.25 coefficient is for the threshold to be a little bigger ++ than the real time, to compensate for timer in-accuracy */ ++ bp->cmng.rs_vars.rs_threshold = ++ (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; ++ ++ /* resolution of fairness timer */ ++ fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; ++ /* for 10G it is 1000usec. for 1G it is 10000usec. */ ++ t_fair = T_FAIR_COEF / bp->link_vars.line_speed; ++ ++ /* this is the threshold below which we won't arm the timer anymore */ ++ bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; ++ ++ /* we multiply by 1e3/8 to get bytes/msec. ++ We don't want the credits to pass a credit ++ of the t_fair*FAIR_MEM (algorithm resolution) */ ++ bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; ++ /* since each tick is 4 usec */ ++ bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; ++} ++ + /* Calculates the sum of vn_min_rates. + It's needed for further normalizing of the min_rates. +- + Returns: +- sum of vn_min_rates ++ sum of vn_min_rates. + or + 0 - if all the min_rates are 0. +- In the later case fairness algorithm should be deactivated. +- If not all min_rates are zero then those that are zeroes will +- be set to 1. +- */ +-static u32 bnx2x_calc_vn_wsum(struct bnx2x *bp) +-{ +- int i, port = BP_PORT(bp); +- u32 wsum = 0; ++ In the later case fainess algorithm should be deactivated. ++ If not all min_rates are zero then those that are zeroes will be set to 1. ++ */ ++static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) ++{ + int all_zero = 1; +- +- for (i = 0; i < E1HVN_MAX; i++) { +- u32 vn_cfg = +- SHMEM_RD(bp, mf_cfg.func_mf_config[2*i + port].config); ++ int port = BP_PORT(bp); ++ int vn; ++ ++ bp->vn_weight_sum = 0; ++ for (vn = VN_0; vn < E1HVN_MAX; vn++) { ++ int func = 2*vn + port; ++ u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config); + u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> +- FUNC_MF_CFG_MIN_BW_SHIFT) * 100; +- if (!(vn_cfg & FUNC_MF_CFG_FUNC_HIDE)) { +- /* If min rate is zero - set it to 1 */ +- if (!vn_min_rate) +- vn_min_rate = DEF_MIN_RATE; +- else +- all_zero = 0; +- +- wsum += vn_min_rate; +- } +- } +- +- /* ... only if all min rates are zeros - disable FAIRNESS */ ++ FUNC_MF_CFG_MIN_BW_SHIFT) * 100; ++ ++ /* Skip hidden vns */ ++ if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) ++ continue; ++ ++ /* If min rate is zero - set it to 1 */ ++ if (!vn_min_rate) ++ vn_min_rate = DEF_MIN_RATE; ++ else ++ all_zero = 0; ++ ++ bp->vn_weight_sum += vn_min_rate; ++ } ++ ++ /* ... only if all min rates are zeros - disable fairness */ + if (all_zero) +- return 0; +- +- return wsum; +-} +- +-static void bnx2x_init_port_minmax(struct bnx2x *bp, +- int en_fness, +- u16 port_rate, +- struct cmng_struct_per_port *m_cmng_port) +-{ +- u32 r_param = port_rate / 8; +- int port = BP_PORT(bp); +- int i; +- +- memset(m_cmng_port, 0, sizeof(struct cmng_struct_per_port)); +- +- /* Enable minmax only if we are in e1hmf mode */ +- if (IS_E1HMF(bp)) { +- u32 fair_periodic_timeout_usec; +- u32 t_fair; +- +- /* Enable rate shaping and fairness */ +- m_cmng_port->flags.cmng_vn_enable = 1; +- m_cmng_port->flags.fairness_enable = en_fness ? 1 : 0; +- m_cmng_port->flags.rate_shaping_enable = 1; +- +- if (!en_fness) +- DP(NETIF_MSG_IFUP, "All MIN values are zeroes" +- " fairness will be disabled\n"); +- +- /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ +- m_cmng_port->rs_vars.rs_periodic_timeout = +- RS_PERIODIC_TIMEOUT_USEC / 4; +- +- /* this is the threshold below which no timer arming will occur +- 1.25 coefficient is for the threshold to be a little bigger +- than the real time, to compensate for timer in-accuracy */ +- m_cmng_port->rs_vars.rs_threshold = +- (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; +- +- /* resolution of fairness timer */ +- fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; +- /* for 10G it is 1000usec. for 1G it is 10000usec. */ +- t_fair = T_FAIR_COEF / port_rate; +- +- /* this is the threshold below which we won't arm +- the timer anymore */ +- m_cmng_port->fair_vars.fair_threshold = QM_ARB_BYTES; +- +- /* we multiply by 1e3/8 to get bytes/msec. +- We don't want the credits to pass a credit +- of the T_FAIR*FAIR_MEM (algorithm resolution) */ +- m_cmng_port->fair_vars.upper_bound = +- r_param * t_fair * FAIR_MEM; +- /* since each tick is 4 usec */ +- m_cmng_port->fair_vars.fairness_timeout = +- fair_periodic_timeout_usec / 4; +- +- } else { +- /* Disable rate shaping and fairness */ +- m_cmng_port->flags.cmng_vn_enable = 0; +- m_cmng_port->flags.fairness_enable = 0; +- m_cmng_port->flags.rate_shaping_enable = 0; +- +- DP(NETIF_MSG_IFUP, +- "Single function mode minmax will be disabled\n"); +- } +- +- /* Store it to internal memory */ +- for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++) +- REG_WR(bp, BAR_XSTRORM_INTMEM + +- XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4, +- ((u32 *)(m_cmng_port))[i]); +-} +- +-static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func, +- u32 wsum, u16 port_rate, +- struct cmng_struct_per_port *m_cmng_port) ++ bp->vn_weight_sum = 0; ++} ++ ++static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func) + { + struct rate_shaping_vars_per_vn m_rs_vn; + struct fairness_vars_per_vn m_fair_vn; +@@ -2174,17 +2532,18 @@ + } else { + vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> + FUNC_MF_CFG_MIN_BW_SHIFT) * 100; +- /* If FAIRNESS is enabled (not all min rates are zeroes) and ++ /* If fairness is enabled (not all min rates are zeroes) and + if current min rate is zero - set it to 1. + This is a requirement of the algorithm. */ +- if ((vn_min_rate == 0) && wsum) ++ if (bp->vn_weight_sum && (vn_min_rate == 0)) + vn_min_rate = DEF_MIN_RATE; + vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> + FUNC_MF_CFG_MAX_BW_SHIFT) * 100; + } + +- DP(NETIF_MSG_IFUP, "func %d: vn_min_rate=%d vn_max_rate=%d " +- "wsum=%d\n", func, vn_min_rate, vn_max_rate, wsum); ++ DP(NETIF_MSG_IFUP, ++ "func %d: vn_min_rate=%d vn_max_rate=%d vn_weight_sum=%d\n", ++ func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); + + memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); + memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); +@@ -2196,54 +2555,19 @@ + m_rs_vn.vn_counter.quota = + (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; + +-#ifdef BNX2X_PER_PROT_QOS +- /* per protocol counter */ +- for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++) { +- /* maximal Mbps for this protocol */ +- m_rs_vn.protocol_counters[protocol].rate = +- protocol_max_rate[protocol]; +- /* the quota in each timer period - +- number of bytes transmitted in this period */ +- m_rs_vn.protocol_counters[protocol].quota = +- (u32)(rs_periodic_timeout_usec * +- ((double)m_rs_vn. +- protocol_counters[protocol].rate/8)); +- } +-#endif +- +- if (wsum) { ++ if (bp->vn_weight_sum) { + /* credit for each period of the fairness algorithm: + number of bytes in T_FAIR (the vn share the port rate). +- wsum should not be larger than 10000, thus +- T_FAIR_COEF / (8 * wsum) will always be grater than zero */ ++ vn_weight_sum should not be larger than 10000, thus ++ T_FAIR_COEF / (8 * vn_weight_sum) will always be greater ++ than zero */ + m_fair_vn.vn_credit_delta = +- max((u64)(vn_min_rate * (T_FAIR_COEF / (8 * wsum))), +- (u64)(m_cmng_port->fair_vars.fair_threshold * 2)); ++ max((u32)(vn_min_rate * (T_FAIR_COEF / ++ (8 * bp->vn_weight_sum))), ++ (u32)(bp->cmng.fair_vars.fair_threshold * 2)); + DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n", + m_fair_vn.vn_credit_delta); + } +- +-#ifdef BNX2X_PER_PROT_QOS +- do { +- u32 protocolWeightSum = 0; +- +- for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++) +- protocolWeightSum += +- drvInit.protocol_min_rate[protocol]; +- /* per protocol counter - +- NOT NEEDED IF NO PER-PROTOCOL CONGESTION MANAGEMENT */ +- if (protocolWeightSum > 0) { +- for (protocol = 0; +- protocol < NUM_OF_PROTOCOLS; protocol++) +- /* credit for each period of the +- fairness algorithm - number of bytes in +- T_FAIR (the protocol share the vn rate) */ +- m_fair_vn.protocol_credit_delta[protocol] = +- (u32)((vn_min_rate / 8) * t_fair * +- protocol_min_rate / protocolWeightSum); +- } +- } while (0); +-#endif + + /* Store it to internal memory */ + for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) +@@ -2257,17 +2581,60 @@ + ((u32 *)(&m_fair_vn))[i]); + } + ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++static void bnx2x_init_cos_credit(struct bnx2x *bp) ++{ ++ struct fairness_vars_per_vn m_fair_vn; ++ int func = BP_FUNC(bp); ++ int i, cos; ++ ++ memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); ++ ++ for (cos = 0; cos < BNX2X_MAX_COS; cos++) { ++ if (bp->cos_min_rate[cos]) { ++ m_fair_vn.cos_credit_delta[cos] = ++ max((u32)(bp->cos_min_rate[cos] * ++ (T_FAIR_COEF / (8 * bp->cos_weight_sum))), ++ (u32)(bp->cmng.fair_vars.fair_threshold * 2)); ++ } ++ DP(NETIF_MSG_IFUP, "cos_credit_delta[%d] = %d\n", ++ cos, m_fair_vn.cos_credit_delta[cos]); ++ } ++ ++ for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) ++ REG_WR(bp, BAR_XSTRORM_INTMEM + ++ XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, ++ ((u32 *)(&m_fair_vn))[i]); ++} ++#endif ++ + /* This function is called upon link interrupt */ + static void bnx2x_link_attn(struct bnx2x *bp) + { +- int vn; +- + /* Make sure that we are synced with the current statistics */ + bnx2x_stats_handle(bp, STATS_EVENT_STOP); + + bnx2x_link_update(&bp->link_params, &bp->link_vars); + + if (bp->link_vars.link_up) { ++ ++ /* dropless flow control */ ++ if (CHIP_IS_E1H(bp) && bp->dropless_fc) { ++ int port = BP_PORT(bp); ++ u32 pause_enabled = 0; ++ ++#ifdef BNX2X_SAFC ++ if ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) || ++ (bp->flags & SAFC_TX_FLAG)) ++#else /* BNX2X_UPSTREAM */ ++ if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ++#endif ++ pause_enabled = 1; ++ ++ REG_WR(bp, BAR_USTRORM_INTMEM + ++ USTORM_ETH_PAUSE_ENABLED_OFFSET(port), ++ pause_enabled); ++ } + + if (bp->link_vars.mac_type == MAC_TYPE_BMAC) { + struct host_port_stats *pstats; +@@ -2286,41 +2653,62 @@ + bnx2x_link_report(bp); + + if (IS_E1HMF(bp)) { ++ int port = BP_PORT(bp); + int func; +- ++ int vn; ++ ++ /* Set the attention towards other drivers on the same port */ + for (vn = VN_0; vn < E1HVN_MAX; vn++) { + if (vn == BP_E1HVN(bp)) + continue; + +- func = ((vn << 1) | BP_PORT(bp)); +- +- /* Set the attention towards other drivers +- on the same port */ ++ func = ((vn << 1) | port); + REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + + (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); + } +- } +- +- if (CHIP_IS_E1H(bp) && (bp->link_vars.line_speed > 0)) { +- struct cmng_struct_per_port m_cmng_port; +- u32 wsum; +- int port = BP_PORT(bp); +- +- /* Init RATE SHAPING and FAIRNESS contexts */ +- wsum = bnx2x_calc_vn_wsum(bp); +- bnx2x_init_port_minmax(bp, (int)wsum, +- bp->link_vars.line_speed, +- &m_cmng_port); +- if (IS_E1HMF(bp)) ++ ++ if (bp->link_vars.link_up) { ++ int i; ++ ++ /* Init rate shaping and fairness contexts */ ++ bnx2x_init_port_minmax(bp); ++ + for (vn = VN_0; vn < E1HVN_MAX; vn++) +- bnx2x_init_vn_minmax(bp, 2*vn + port, +- wsum, bp->link_vars.line_speed, +- &m_cmng_port); ++ bnx2x_init_vn_minmax(bp, 2*vn + port); ++ ++ /* Store it to internal memory */ ++ for (i = 0; ++ i < sizeof(struct cmng_struct_per_port) / 4; i++) ++ REG_WR(bp, BAR_XSTRORM_INTMEM + ++ XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4, ++ ((u32 *)(&bp->cmng))[i]); ++ } ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ } else { ++ if (bp->link_vars.link_up && bp->cos_weight_sum) { ++ int port = BP_PORT(bp); ++ int i; ++ ++ /* Init fairness context */ ++ bnx2x_init_port_minmax(bp); ++ ++ bnx2x_init_cos_credit(bp); ++ ++ /* Store it to internal memory */ ++ for (i = 0; ++ i < sizeof(struct cmng_struct_per_port) / 4; i++) ++ REG_WR(bp, BAR_XSTRORM_INTMEM + ++ XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4, ++ ((u32 *)(&bp->cmng))[i]); ++ } ++#endif + } + } + + static void bnx2x__link_status_update(struct bnx2x *bp) + { ++ int func = BP_FUNC(bp); ++ + if (bp->state != BNX2X_STATE_OPEN) + return; + +@@ -2330,6 +2718,9 @@ + bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); + else + bnx2x_stats_handle(bp, STATS_EVENT_STOP); ++ ++ bp->mf_config = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config); ++ bnx2x_calc_vn_weight_sum(bp); + + /* indicate link status */ + bnx2x_link_report(bp); +@@ -2358,6 +2749,152 @@ + /* + * General service functions + */ ++ ++/* send the MCP a request, block until there is a reply */ ++u32 bnx2x_fw_command(struct bnx2x *bp, u32 command) ++{ ++ int func = BP_FUNC(bp); ++ u32 seq = ++bp->fw_seq; ++ u32 rc = 0; ++ u32 cnt = 1; ++ u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; ++ ++ SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq)); ++ DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq)); ++ ++ do { ++ /* let the FW do it's magic ... */ ++ msleep(delay); ++ ++ rc = SHMEM_RD(bp, func_mb[func].fw_mb_header); ++ ++ /* Give the FW up to 2 second (200*10ms) */ ++ } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200)); ++ ++ DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", ++ cnt*delay, rc, seq); ++ ++ /* is this a reply to our command? */ ++ if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) ++ rc &= FW_MSG_CODE_MASK; ++ else { ++ /* FW BUG! */ ++ BNX2X_ERR("FW failed to respond!\n"); ++ bnx2x_fw_dump(bp); ++ rc = 0; ++ } ++ ++ return rc; ++} ++ ++static void bnx2x_set_storm_rx_mode(struct bnx2x *bp); ++static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set); ++static void bnx2x_set_rx_mode(struct net_device *dev); ++ ++static void bnx2x_e1h_disable(struct bnx2x *bp) ++{ ++ int port = BP_PORT(bp); ++ int i; ++ ++ bp->rx_mode = BNX2X_RX_MODE_NONE; ++ bnx2x_set_storm_rx_mode(bp); ++ ++ netif_tx_disable(bp->dev); ++ bp->dev->trans_start = jiffies; /* prevent tx timeout */ ++ ++ REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); ++ ++ bnx2x_set_mac_addr_e1h(bp, 0); ++ ++ for (i = 0; i < MC_HASH_SIZE; i++) ++ REG_WR(bp, MC_HASH_OFFSET(bp, i), 0); ++ ++ netif_carrier_off(bp->dev); ++} ++ ++static void bnx2x_e1h_enable(struct bnx2x *bp) ++{ ++ int port = BP_PORT(bp); ++ ++ REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); ++ ++ bnx2x_set_mac_addr_e1h(bp, 1); ++ ++ /* Tx queue should be only reenabled */ ++ netif_tx_wake_all_queues(bp->dev); ++ ++ /* Initialize the receive filter. */ ++ bnx2x_set_rx_mode(bp->dev); ++} ++ ++static void bnx2x_update_min_max(struct bnx2x *bp) ++{ ++ int port = BP_PORT(bp); ++ int vn, i; ++ ++ /* Init rate shaping and fairness contexts */ ++ bnx2x_init_port_minmax(bp); ++ ++ bnx2x_calc_vn_weight_sum(bp); ++ ++ for (vn = VN_0; vn < E1HVN_MAX; vn++) ++ bnx2x_init_vn_minmax(bp, 2*vn + port); ++ ++ if (bp->port.pmf) { ++ int func; ++ ++ /* Set the attention towards other drivers on the same port */ ++ for (vn = VN_0; vn < E1HVN_MAX; vn++) { ++ if (vn == BP_E1HVN(bp)) ++ continue; ++ ++ func = ((vn << 1) | port); ++ REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + ++ (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); ++ } ++ ++ /* Store it to internal memory */ ++ for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++) ++ REG_WR(bp, BAR_XSTRORM_INTMEM + ++ XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4, ++ ((u32 *)(&bp->cmng))[i]); ++ } ++} ++ ++static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) ++{ ++ int func = BP_FUNC(bp); ++ ++ DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); ++ bp->mf_config = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config); ++ ++ if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { ++ ++ if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) { ++ DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); ++ bp->state = BNX2X_STATE_DISABLED; ++ ++ bnx2x_e1h_disable(bp); ++ } else { ++ DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); ++ bp->state = BNX2X_STATE_OPEN; ++ ++ bnx2x_e1h_enable(bp); ++ } ++ dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; ++ } ++ if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { ++ ++ bnx2x_update_min_max(bp); ++ dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; ++ } ++ ++ /* Report results to MCP */ ++ if (dcc_event) ++ bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE); ++ else ++ bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK); ++} + + /* the slow path queue is odd since completions arrive on the fastpath ring */ + static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, +@@ -2409,8 +2946,13 @@ + bp->spq_prod_idx++; + } + ++ /* Make sure that BD data is updated before writing the producer */ ++ wmb(); ++ + REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), + bp->spq_prod_idx); ++ ++ mmiowb(); + + spin_unlock_bh(&bp->spq_lock); + return 0; +@@ -2492,6 +3034,7 @@ + u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : + NIG_REG_MASK_INTERRUPT_PORT0; + u32 aeu_mask; ++ u32 nig_mask = 0; + + if (bp->attn_state & asserted) + BNX2X_ERR("IGU ERROR\n"); +@@ -2517,7 +3060,7 @@ + bnx2x_acquire_phy_lock(bp); + + /* save nig interrupt mask */ +- bp->nig_mask = REG_RD(bp, nig_int_mask_addr); ++ nig_mask = REG_RD(bp, nig_int_mask_addr); + REG_WR(bp, nig_int_mask_addr, 0); + + bnx2x_link_attn(bp); +@@ -2572,16 +3115,33 @@ + + /* now set back the mask */ + if (asserted & ATTN_NIG_FOR_FUNC) { +- REG_WR(bp, nig_int_mask_addr, bp->nig_mask); ++ REG_WR(bp, nig_int_mask_addr, nig_mask); + bnx2x_release_phy_lock(bp); + } + } + ++static inline void bnx2x_fan_failure(struct bnx2x *bp) ++{ ++ int port = BP_PORT(bp); ++ ++ /* mark the failure */ ++ bp->link_params.ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; ++ bp->link_params.ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; ++ SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, ++ bp->link_params.ext_phy_config); ++ ++ /* log the failure */ ++ printk(KERN_ERR PFX "Fan Failure on Network Controller %s has caused" ++ " the driver to shutdown the card to prevent permanent" ++ " damage. Please contact Dell Support for assistance\n", ++ bp->dev->name); ++} ++ + static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) + { + int port = BP_PORT(bp); + int reg_offset; +- u32 val; ++ u32 val, swap_val, swap_override; + + reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : + MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); +@@ -2594,37 +3154,39 @@ + + BNX2X_ERR("SPIO5 hw attention\n"); + +- switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) { +- case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G: +- case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: +- /* Fan failure attention */ +- ++ /* Fan failure attention */ ++ switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) { ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: ++ /* Low power mode is controlled by GPIO 2 */ ++ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, ++ MISC_REGISTERS_GPIO_OUTPUT_LOW, port); + /* The PHY reset is controlled by GPIO 1 */ + bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, + MISC_REGISTERS_GPIO_OUTPUT_LOW, port); +- /* Low power mode is controlled by GPIO 2 */ +- bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, ++ break; ++ ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: ++ /* The PHY reset is controlled by GPIO 1 */ ++ /* fake the port number to cancel the swap done in ++ set_gpio() */ ++ swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); ++ swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); ++ port = (swap_val && swap_override) ^ 1; ++ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, + MISC_REGISTERS_GPIO_OUTPUT_LOW, port); +- /* mark the failure */ +- bp->link_params.ext_phy_config &= +- ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; +- bp->link_params.ext_phy_config |= +- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; +- SHMEM_WR(bp, +- dev_info.port_hw_config[port]. +- external_phy_config, +- bp->link_params.ext_phy_config); +- /* log the failure */ +- printk(KERN_ERR PFX "Fan Failure on Network" +- " Controller %s has caused the driver to" +- " shutdown the card to prevent permanent" +- " damage. Please contact Dell Support for" +- " assistance\n", bp->dev->name); + break; + + default: + break; + } ++ bnx2x_fan_failure(bp); ++ } ++ ++ if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 | ++ AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) { ++ bnx2x_acquire_phy_lock(bp); ++ bnx2x_handle_module_detect_int(&bp->link_params); ++ bnx2x_release_phy_lock(bp); + } + + if (attn & HW_INTERRUT_ASSERT_SET_0) { +@@ -2634,7 +3196,7 @@ + REG_WR(bp, reg_offset, val); + + BNX2X_ERR("FATAL HW block attention set0 0x%x\n", +- (attn & HW_INTERRUT_ASSERT_SET_0)); ++ (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); + bnx2x_panic(); + } + } +@@ -2643,7 +3205,7 @@ + { + u32 val; + +- if (attn & BNX2X_DOORQ_ASSERT) { ++ if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { + + val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); + BNX2X_ERR("DB hw attention 0x%x\n", val); +@@ -2665,7 +3227,7 @@ + REG_WR(bp, reg_offset, val); + + BNX2X_ERR("FATAL HW block attention set1 0x%x\n", +- (attn & HW_INTERRUT_ASSERT_SET_1)); ++ (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); + bnx2x_panic(); + } + } +@@ -2705,7 +3267,7 @@ + REG_WR(bp, reg_offset, val); + + BNX2X_ERR("FATAL HW block attention set2 0x%x\n", +- (attn & HW_INTERRUT_ASSERT_SET_2)); ++ (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); + bnx2x_panic(); + } + } +@@ -2720,9 +3282,12 @@ + int func = BP_FUNC(bp); + + REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); ++ val = SHMEM_RD(bp, func_mb[func].drv_status); ++ if (val & DRV_STATUS_DCC_EVENT_MASK) ++ bnx2x_dcc_event(bp, ++ (val & DRV_STATUS_DCC_EVENT_MASK)); + bnx2x__link_status_update(bp); +- if (SHMEM_RD(bp, func_mb[func].drv_status) & +- DRV_STATUS_PMF) ++ if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) + bnx2x_pmf_update(bp); + + } else if (attn & BNX2X_MC_ASSERT_BITS) { +@@ -2867,16 +3432,34 @@ + bnx2x_attn_int_deasserted(bp, deasserted); + } + ++#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) || (VMWARE_ESX_DDK_VERSION >= 40000) /* BNX2X_UPSTREAM */ + static void bnx2x_sp_task(struct work_struct *work) + { ++#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */ + struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); ++#else ++ struct bnx2x *bp = container_of(work, struct bnx2x, sp_task); ++#endif ++#else ++static void bnx2x_sp_task(void *data) ++{ ++ struct bnx2x *bp = (struct bnx2x *)data; ++#endif + u16 status; + ++#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */ ++ bp->sp_running = 1; ++ smp_mb(); /* make sure close can see this */ ++#endif + + /* Return here if interrupt is disabled */ + if (unlikely(atomic_read(&bp->intr_sem) != 0)) { + DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n"); +- return; ++#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */ ++ return; ++#else ++ goto sp_task_exit; ++#endif + } + + status = bnx2x_update_dsb_idx(bp); +@@ -2888,10 +3471,6 @@ + /* HW attentions */ + if (status & 0x1) + bnx2x_attn_int(bp); +- +- /* CStorm events: query_stats, port delete ramrod */ +- if (status & 0x2) +- bp->stats_pending = 0; + + bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, le16_to_cpu(bp->def_att_idx), + IGU_INT_NOP, 1); +@@ -2904,9 +3483,20 @@ + bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx), + IGU_INT_ENABLE, 1); + +-} +- ++#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */ ++sp_task_exit: ++ bp->sp_running = 0; ++ smp_mb(); /* make sure close can see this */ ++#endif ++} ++ ++#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */ ++#if (LINUX_VERSION_CODE < 0x020613) && (VMWARE_ESX_DDK_VERSION < 40000) ++static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance, ++ struct pt_regs *regs) ++#else /* BNX2X_UPSTREAM */ + static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) ++#endif + { + struct net_device *dev = dev_instance; + struct bnx2x *bp = netdev_priv(dev); +@@ -2917,17 +3507,22 @@ + return IRQ_HANDLED; + } + +- bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, 0, IGU_INT_DISABLE, 0); ++ bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0); + + #ifdef BNX2X_STOP_ON_ERROR + if (unlikely(bp->panic)) + return IRQ_HANDLED; + #endif + ++#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */ + queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); ++#else ++ queue_work(bnx2x_wq, &bp->sp_task); ++#endif + + return IRQ_HANDLED; + } ++#endif + + /* end of slow path */ + +@@ -3006,16 +3601,41 @@ + + #define UPDATE_EXTEND_TSTAT(s, t) \ + do { \ +- diff = le32_to_cpu(tclient->s) - old_tclient->s; \ +- old_tclient->s = le32_to_cpu(tclient->s); \ +- ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \ ++ diff = le32_to_cpu(tclient->s) - le32_to_cpu(old_tclient->s); \ ++ old_tclient->s = tclient->s; \ ++ ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \ ++ } while (0) ++ ++#define UPDATE_EXTEND_USTAT(s, t) \ ++ do { \ ++ diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \ ++ old_uclient->s = uclient->s; \ ++ ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \ + } while (0) + + #define UPDATE_EXTEND_XSTAT(s, t) \ + do { \ +- diff = le32_to_cpu(xclient->s) - old_xclient->s; \ +- old_xclient->s = le32_to_cpu(xclient->s); \ +- ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \ ++ diff = le32_to_cpu(xclient->s) - le32_to_cpu(old_xclient->s); \ ++ old_xclient->s = xclient->s; \ ++ ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \ ++ } while (0) ++ ++/* minuend -= subtrahend */ ++#define SUB_64(m_hi, s_hi, m_lo, s_lo) \ ++ do { \ ++ DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \ ++ } while (0) ++ ++/* minuend[hi:lo] -= subtrahend */ ++#define SUB_EXTEND_64(m_hi, m_lo, s) \ ++ do { \ ++ SUB_64(m_hi, 0, m_lo, s); \ ++ } while (0) ++ ++#define SUB_EXTEND_USTAT(s, t) \ ++ do { \ ++ diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \ ++ SUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \ + } while (0) + + /* +@@ -3042,11 +3662,12 @@ + { + if (!bp->stats_pending) { + struct eth_query_ramrod_data ramrod_data = {0}; +- int rc; ++ int i, rc; + + ramrod_data.drv_counter = bp->stats_counter++; +- ramrod_data.collect_port_1b = bp->port.pmf ? 1 : 0; +- ramrod_data.ctr_id_vector = (1 << BP_CL_ID(bp)); ++ ramrod_data.collect_port = bp->port.pmf ? 1 : 0; ++ for_each_queue(bp, i) ++ ramrod_data.ctr_id_vector |= (1 << bp->fp[i].cl_id); + + rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0, + ((u32 *)&ramrod_data)[1], +@@ -3059,47 +3680,14 @@ + } + } + +-static void bnx2x_stats_init(struct bnx2x *bp) +-{ +- int port = BP_PORT(bp); +- +- bp->executer_idx = 0; +- bp->stats_counter = 0; +- +- /* port stats */ +- if (!BP_NOMCP(bp)) +- bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx); +- else +- bp->port.port_stx = 0; +- DP(BNX2X_MSG_STATS, "port_stx 0x%x\n", bp->port.port_stx); +- +- memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats)); +- bp->port.old_nig_stats.brb_discard = +- REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38); +- bp->port.old_nig_stats.brb_truncate = +- REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38); +- REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50, +- &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2); +- REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50, +- &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2); +- +- /* function stats */ +- memset(&bp->dev->stats, 0, sizeof(struct net_device_stats)); +- memset(&bp->old_tclient, 0, sizeof(struct tstorm_per_client_stats)); +- memset(&bp->old_xclient, 0, sizeof(struct xstorm_per_client_stats)); +- memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats)); +- +- bp->stats_state = STATS_STATE_DISABLED; +- if (IS_E1HMF(bp) && bp->port.pmf && bp->port.port_stx) +- bnx2x_stats_handle(bp, STATS_EVENT_PMF); +-} +- + static void bnx2x_hw_stats_post(struct bnx2x *bp) + { + struct dmae_command *dmae = &bp->stats_dmae; + u32 *stats_comp = bnx2x_sp(bp, stats_comp); + + *stats_comp = DMAE_COMP_VAL; ++ if (CHIP_REV_IS_SLOW(bp)) ++ return; + + /* loader */ + if (bp->executer_idx) { +@@ -3489,7 +4077,11 @@ + { + struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats); + struct host_port_stats *pstats = bnx2x_sp(bp, port_stats); +- struct regpair diff; ++ struct bnx2x_eth_stats *estats = &bp->eth_stats; ++ struct { ++ u32 lo; ++ u32 hi; ++ } diff; + + UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets); + UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors); +@@ -3499,7 +4091,7 @@ + UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers); + UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived); + UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered); +- UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffpauseframesreceived); ++ UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf); + UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent); + UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone); + UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets); +@@ -3520,12 +4112,23 @@ + UPDATE_STAT64(tx_stat_gterr, + tx_stat_dot3statsinternalmactransmiterrors); + UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl); ++ ++ estats->pause_frames_received_hi = ++ pstats->mac_stx[1].rx_stat_bmac_xpf_hi; ++ estats->pause_frames_received_lo = ++ pstats->mac_stx[1].rx_stat_bmac_xpf_lo; ++ ++ estats->pause_frames_sent_hi = ++ pstats->mac_stx[1].tx_stat_outxoffsent_hi; ++ estats->pause_frames_sent_lo = ++ pstats->mac_stx[1].tx_stat_outxoffsent_lo; + } + + static void bnx2x_emac_stats_update(struct bnx2x *bp) + { + struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats); + struct host_port_stats *pstats = bnx2x_sp(bp, port_stats); ++ struct bnx2x_eth_stats *estats = &bp->eth_stats; + + UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets); + UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets); +@@ -3558,6 +4161,24 @@ + UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets); + UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets); + UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors); ++ ++ estats->pause_frames_received_hi = ++ pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi; ++ estats->pause_frames_received_lo = ++ pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo; ++ ADD_64(estats->pause_frames_received_hi, ++ pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi, ++ estats->pause_frames_received_lo, ++ pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo); ++ ++ estats->pause_frames_sent_hi = ++ pstats->mac_stx[1].tx_stat_outxonsent_hi; ++ estats->pause_frames_sent_lo = ++ pstats->mac_stx[1].tx_stat_outxonsent_lo; ++ ADD_64(estats->pause_frames_sent_hi, ++ pstats->mac_stx[1].tx_stat_outxoffsent_hi, ++ estats->pause_frames_sent_lo, ++ pstats->mac_stx[1].tx_stat_outxoffsent_lo); + } + + static int bnx2x_hw_stats_update(struct bnx2x *bp) +@@ -3566,7 +4187,11 @@ + struct nig_stats *old = &(bp->port.old_nig_stats); + struct host_port_stats *pstats = bnx2x_sp(bp, port_stats); + struct bnx2x_eth_stats *estats = &bp->eth_stats; +- struct regpair diff; ++ struct { ++ u32 lo; ++ u32 hi; ++ } diff; ++ u32 nig_timer_max; + + if (bp->link_vars.mac_type == MAC_TYPE_BMAC) + bnx2x_bmac_stats_update(bp); +@@ -3575,7 +4200,7 @@ + bnx2x_emac_stats_update(bp); + + else { /* unreached */ +- BNX2X_ERR("stats updated by dmae but no MAC active\n"); ++ BNX2X_ERR("stats updated by DMAE but no MAC active\n"); + return -1; + } + +@@ -3597,134 +4222,239 @@ + + pstats->host_port_stats_start = ++pstats->host_port_stats_end; + ++ nig_timer_max = SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer); ++ if (nig_timer_max != estats->nig_timer_max) { ++ estats->nig_timer_max = nig_timer_max; ++ BNX2X_ERR("NIG timer max (%u)\n", estats->nig_timer_max); ++ } ++ + return 0; + } + + static int bnx2x_storm_stats_update(struct bnx2x *bp) + { + struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats); +- int cl_id = BP_CL_ID(bp); + struct tstorm_per_port_stats *tport = +- &stats->tstorm_common.port_statistics; +- struct tstorm_per_client_stats *tclient = +- &stats->tstorm_common.client_statistics[cl_id]; +- struct tstorm_per_client_stats *old_tclient = &bp->old_tclient; +- struct xstorm_per_client_stats *xclient = +- &stats->xstorm_common.client_statistics[cl_id]; +- struct xstorm_per_client_stats *old_xclient = &bp->old_xclient; ++ &stats->tstorm_common.port_statistics; + struct host_func_stats *fstats = bnx2x_sp(bp, func_stats); + struct bnx2x_eth_stats *estats = &bp->eth_stats; +- u32 diff; +- +- /* are storm stats valid? */ +- if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) != ++ int i; ++ ++ memcpy(&(fstats->total_bytes_received_hi), ++ &(bnx2x_sp(bp, func_stats_base)->total_bytes_received_hi), ++ sizeof(struct host_func_stats) - 2*sizeof(u32)); ++ estats->error_bytes_received_hi = 0; ++ estats->error_bytes_received_lo = 0; ++ estats->etherstatsoverrsizepkts_hi = 0; ++ estats->etherstatsoverrsizepkts_lo = 0; ++ estats->no_buff_discard_hi = 0; ++ estats->no_buff_discard_lo = 0; ++ ++ for_each_rx_queue(bp, i) { ++ struct bnx2x_fastpath *fp = &bp->fp[i]; ++ int cl_id = fp->cl_id; ++ struct tstorm_per_client_stats *tclient = ++ &stats->tstorm_common.client_statistics[cl_id]; ++ struct tstorm_per_client_stats *old_tclient = &fp->old_tclient; ++ struct ustorm_per_client_stats *uclient = ++ &stats->ustorm_common.client_statistics[cl_id]; ++ struct ustorm_per_client_stats *old_uclient = &fp->old_uclient; ++ struct xstorm_per_client_stats *xclient = ++ &stats->xstorm_common.client_statistics[cl_id]; ++ struct xstorm_per_client_stats *old_xclient = &fp->old_xclient; ++ struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats; ++ u32 diff; ++ ++ /* are storm stats valid? */ ++ if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) != + bp->stats_counter) { +- DP(BNX2X_MSG_STATS, "stats not updated by tstorm" +- " tstorm counter (%d) != stats_counter (%d)\n", +- tclient->stats_counter, bp->stats_counter); +- return -1; +- } +- if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) != ++ DP(BNX2X_MSG_STATS, "[%d] stats not updated by xstorm" ++ " xstorm counter (%d) != stats_counter (%d)\n", ++ i, xclient->stats_counter, bp->stats_counter); ++ return -1; ++ } ++ if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) != + bp->stats_counter) { +- DP(BNX2X_MSG_STATS, "stats not updated by xstorm" +- " xstorm counter (%d) != stats_counter (%d)\n", +- xclient->stats_counter, bp->stats_counter); +- return -2; +- } +- +- fstats->total_bytes_received_hi = +- fstats->valid_bytes_received_hi = +- le32_to_cpu(tclient->total_rcv_bytes.hi); +- fstats->total_bytes_received_lo = +- fstats->valid_bytes_received_lo = +- le32_to_cpu(tclient->total_rcv_bytes.lo); +- +- estats->error_bytes_received_hi = ++ DP(BNX2X_MSG_STATS, "[%d] stats not updated by tstorm" ++ " tstorm counter (%d) != stats_counter (%d)\n", ++ i, tclient->stats_counter, bp->stats_counter); ++ return -2; ++ } ++ if ((u16)(le16_to_cpu(uclient->stats_counter) + 1) != ++ bp->stats_counter) { ++ DP(BNX2X_MSG_STATS, "[%d] stats not updated by ustorm" ++ " ustorm counter (%d) != stats_counter (%d)\n", ++ i, uclient->stats_counter, bp->stats_counter); ++ return -4; ++ } ++ ++ qstats->total_bytes_received_hi = ++ le32_to_cpu(tclient->rcv_broadcast_bytes.hi); ++ qstats->total_bytes_received_lo = ++ le32_to_cpu(tclient->rcv_broadcast_bytes.lo); ++ ++ ADD_64(qstats->total_bytes_received_hi, ++ le32_to_cpu(tclient->rcv_multicast_bytes.hi), ++ qstats->total_bytes_received_lo, ++ le32_to_cpu(tclient->rcv_multicast_bytes.lo)); ++ ++ ADD_64(qstats->total_bytes_received_hi, ++ le32_to_cpu(tclient->rcv_unicast_bytes.hi), ++ qstats->total_bytes_received_lo, ++ le32_to_cpu(tclient->rcv_unicast_bytes.lo)); ++ ++ qstats->valid_bytes_received_hi = ++ qstats->total_bytes_received_hi; ++ qstats->valid_bytes_received_lo = ++ qstats->total_bytes_received_lo; ++ ++ qstats->error_bytes_received_hi = + le32_to_cpu(tclient->rcv_error_bytes.hi); +- estats->error_bytes_received_lo = ++ qstats->error_bytes_received_lo = + le32_to_cpu(tclient->rcv_error_bytes.lo); ++ ++ ADD_64(qstats->total_bytes_received_hi, ++ qstats->error_bytes_received_hi, ++ qstats->total_bytes_received_lo, ++ qstats->error_bytes_received_lo); ++ ++ UPDATE_EXTEND_TSTAT(rcv_unicast_pkts, ++ total_unicast_packets_received); ++ UPDATE_EXTEND_TSTAT(rcv_multicast_pkts, ++ total_multicast_packets_received); ++ UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts, ++ total_broadcast_packets_received); ++ UPDATE_EXTEND_TSTAT(packets_too_big_discard, ++ etherstatsoverrsizepkts); ++ UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard); ++ ++ SUB_EXTEND_USTAT(ucast_no_buff_pkts, ++ total_unicast_packets_received); ++ SUB_EXTEND_USTAT(mcast_no_buff_pkts, ++ total_multicast_packets_received); ++ SUB_EXTEND_USTAT(bcast_no_buff_pkts, ++ total_broadcast_packets_received); ++ UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard); ++ UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard); ++ UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard); ++ ++ qstats->total_bytes_transmitted_hi = ++ le32_to_cpu(xclient->unicast_bytes_sent.hi); ++ qstats->total_bytes_transmitted_lo = ++ le32_to_cpu(xclient->unicast_bytes_sent.lo); ++ ++ ADD_64(qstats->total_bytes_transmitted_hi, ++ le32_to_cpu(xclient->multicast_bytes_sent.hi), ++ qstats->total_bytes_transmitted_lo, ++ le32_to_cpu(xclient->multicast_bytes_sent.lo)); ++ ++ ADD_64(qstats->total_bytes_transmitted_hi, ++ le32_to_cpu(xclient->broadcast_bytes_sent.hi), ++ qstats->total_bytes_transmitted_lo, ++ le32_to_cpu(xclient->broadcast_bytes_sent.lo)); ++ ++ UPDATE_EXTEND_XSTAT(unicast_pkts_sent, ++ total_unicast_packets_transmitted); ++ UPDATE_EXTEND_XSTAT(multicast_pkts_sent, ++ total_multicast_packets_transmitted); ++ UPDATE_EXTEND_XSTAT(broadcast_pkts_sent, ++ total_broadcast_packets_transmitted); ++ ++ old_tclient->checksum_discard = tclient->checksum_discard; ++ old_tclient->ttl0_discard = tclient->ttl0_discard; ++ ++ ADD_64(fstats->total_bytes_received_hi, ++ qstats->total_bytes_received_hi, ++ fstats->total_bytes_received_lo, ++ qstats->total_bytes_received_lo); ++ ADD_64(fstats->total_bytes_transmitted_hi, ++ qstats->total_bytes_transmitted_hi, ++ fstats->total_bytes_transmitted_lo, ++ qstats->total_bytes_transmitted_lo); ++ ADD_64(fstats->total_unicast_packets_received_hi, ++ qstats->total_unicast_packets_received_hi, ++ fstats->total_unicast_packets_received_lo, ++ qstats->total_unicast_packets_received_lo); ++ ADD_64(fstats->total_multicast_packets_received_hi, ++ qstats->total_multicast_packets_received_hi, ++ fstats->total_multicast_packets_received_lo, ++ qstats->total_multicast_packets_received_lo); ++ ADD_64(fstats->total_broadcast_packets_received_hi, ++ qstats->total_broadcast_packets_received_hi, ++ fstats->total_broadcast_packets_received_lo, ++ qstats->total_broadcast_packets_received_lo); ++ ADD_64(fstats->total_unicast_packets_transmitted_hi, ++ qstats->total_unicast_packets_transmitted_hi, ++ fstats->total_unicast_packets_transmitted_lo, ++ qstats->total_unicast_packets_transmitted_lo); ++ ADD_64(fstats->total_multicast_packets_transmitted_hi, ++ qstats->total_multicast_packets_transmitted_hi, ++ fstats->total_multicast_packets_transmitted_lo, ++ qstats->total_multicast_packets_transmitted_lo); ++ ADD_64(fstats->total_broadcast_packets_transmitted_hi, ++ qstats->total_broadcast_packets_transmitted_hi, ++ fstats->total_broadcast_packets_transmitted_lo, ++ qstats->total_broadcast_packets_transmitted_lo); ++ ADD_64(fstats->valid_bytes_received_hi, ++ qstats->valid_bytes_received_hi, ++ fstats->valid_bytes_received_lo, ++ qstats->valid_bytes_received_lo); ++ ++ ADD_64(estats->error_bytes_received_hi, ++ qstats->error_bytes_received_hi, ++ estats->error_bytes_received_lo, ++ qstats->error_bytes_received_lo); ++ ADD_64(estats->etherstatsoverrsizepkts_hi, ++ qstats->etherstatsoverrsizepkts_hi, ++ estats->etherstatsoverrsizepkts_lo, ++ qstats->etherstatsoverrsizepkts_lo); ++ ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi, ++ estats->no_buff_discard_lo, qstats->no_buff_discard_lo); ++ } ++ ++ ADD_64(fstats->total_bytes_received_hi, ++ estats->rx_stat_ifhcinbadoctets_hi, ++ fstats->total_bytes_received_lo, ++ estats->rx_stat_ifhcinbadoctets_lo); ++ ++ memcpy(estats, &(fstats->total_bytes_received_hi), ++ sizeof(struct host_func_stats) - 2*sizeof(u32)); ++ ++ ADD_64(estats->etherstatsoverrsizepkts_hi, ++ estats->rx_stat_dot3statsframestoolong_hi, ++ estats->etherstatsoverrsizepkts_lo, ++ estats->rx_stat_dot3statsframestoolong_lo); + ADD_64(estats->error_bytes_received_hi, + estats->rx_stat_ifhcinbadoctets_hi, + estats->error_bytes_received_lo, + estats->rx_stat_ifhcinbadoctets_lo); + +- ADD_64(fstats->total_bytes_received_hi, +- estats->error_bytes_received_hi, +- fstats->total_bytes_received_lo, +- estats->error_bytes_received_lo); +- +- UPDATE_EXTEND_TSTAT(rcv_unicast_pkts, total_unicast_packets_received); +- UPDATE_EXTEND_TSTAT(rcv_multicast_pkts, +- total_multicast_packets_received); +- UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts, +- total_broadcast_packets_received); +- +- fstats->total_bytes_transmitted_hi = +- le32_to_cpu(xclient->total_sent_bytes.hi); +- fstats->total_bytes_transmitted_lo = +- le32_to_cpu(xclient->total_sent_bytes.lo); +- +- UPDATE_EXTEND_XSTAT(unicast_pkts_sent, +- total_unicast_packets_transmitted); +- UPDATE_EXTEND_XSTAT(multicast_pkts_sent, +- total_multicast_packets_transmitted); +- UPDATE_EXTEND_XSTAT(broadcast_pkts_sent, +- total_broadcast_packets_transmitted); +- +- memcpy(estats, &(fstats->total_bytes_received_hi), +- sizeof(struct host_func_stats) - 2*sizeof(u32)); +- +- estats->mac_filter_discard = le32_to_cpu(tport->mac_filter_discard); +- estats->xxoverflow_discard = le32_to_cpu(tport->xxoverflow_discard); +- estats->brb_truncate_discard = ++ if (bp->port.pmf) { ++ estats->mac_filter_discard = ++ le32_to_cpu(tport->mac_filter_discard); ++ estats->xxoverflow_discard = ++ le32_to_cpu(tport->xxoverflow_discard); ++ estats->brb_truncate_discard = + le32_to_cpu(tport->brb_truncate_discard); +- estats->mac_discard = le32_to_cpu(tport->mac_discard); +- +- old_tclient->rcv_unicast_bytes.hi = +- le32_to_cpu(tclient->rcv_unicast_bytes.hi); +- old_tclient->rcv_unicast_bytes.lo = +- le32_to_cpu(tclient->rcv_unicast_bytes.lo); +- old_tclient->rcv_broadcast_bytes.hi = +- le32_to_cpu(tclient->rcv_broadcast_bytes.hi); +- old_tclient->rcv_broadcast_bytes.lo = +- le32_to_cpu(tclient->rcv_broadcast_bytes.lo); +- old_tclient->rcv_multicast_bytes.hi = +- le32_to_cpu(tclient->rcv_multicast_bytes.hi); +- old_tclient->rcv_multicast_bytes.lo = +- le32_to_cpu(tclient->rcv_multicast_bytes.lo); +- old_tclient->total_rcv_pkts = le32_to_cpu(tclient->total_rcv_pkts); +- +- old_tclient->checksum_discard = le32_to_cpu(tclient->checksum_discard); +- old_tclient->packets_too_big_discard = +- le32_to_cpu(tclient->packets_too_big_discard); +- estats->no_buff_discard = +- old_tclient->no_buff_discard = le32_to_cpu(tclient->no_buff_discard); +- old_tclient->ttl0_discard = le32_to_cpu(tclient->ttl0_discard); +- +- old_xclient->total_sent_pkts = le32_to_cpu(xclient->total_sent_pkts); +- old_xclient->unicast_bytes_sent.hi = +- le32_to_cpu(xclient->unicast_bytes_sent.hi); +- old_xclient->unicast_bytes_sent.lo = +- le32_to_cpu(xclient->unicast_bytes_sent.lo); +- old_xclient->multicast_bytes_sent.hi = +- le32_to_cpu(xclient->multicast_bytes_sent.hi); +- old_xclient->multicast_bytes_sent.lo = +- le32_to_cpu(xclient->multicast_bytes_sent.lo); +- old_xclient->broadcast_bytes_sent.hi = +- le32_to_cpu(xclient->broadcast_bytes_sent.hi); +- old_xclient->broadcast_bytes_sent.lo = +- le32_to_cpu(xclient->broadcast_bytes_sent.lo); ++ estats->mac_discard = le32_to_cpu(tport->mac_discard); ++ } + + fstats->host_func_stats_start = ++fstats->host_func_stats_end; + ++ bp->stats_pending = 0; ++ + return 0; + } + + static void bnx2x_net_stats_update(struct bnx2x *bp) + { +- struct tstorm_per_client_stats *old_tclient = &bp->old_tclient; + struct bnx2x_eth_stats *estats = &bp->eth_stats; ++#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */ + struct net_device_stats *nstats = &bp->dev->stats; ++#else ++ struct net_device_stats *nstats = &bp->net_stats; ++#endif ++ int i; + + nstats->rx_packets = + bnx2x_hilo(&estats->total_unicast_packets_received_hi) + +@@ -3736,34 +4466,33 @@ + bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) + + bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi); + +- nstats->rx_bytes = bnx2x_hilo(&estats->valid_bytes_received_hi); ++ nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi); + + nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi); + +- nstats->rx_dropped = old_tclient->checksum_discard + +- estats->mac_discard; ++ nstats->rx_dropped = estats->mac_discard; ++ for_each_rx_queue(bp, i) ++ nstats->rx_dropped += ++ le32_to_cpu(bp->fp[i].old_tclient.checksum_discard); ++ + nstats->tx_dropped = 0; + + nstats->multicast = +- bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi); ++ bnx2x_hilo(&estats->total_multicast_packets_received_hi); + + nstats->collisions = +- estats->tx_stat_dot3statssinglecollisionframes_lo + +- estats->tx_stat_dot3statsmultiplecollisionframes_lo + +- estats->tx_stat_dot3statslatecollisions_lo + +- estats->tx_stat_dot3statsexcessivecollisions_lo; +- +- estats->jabber_packets_received = +- old_tclient->packets_too_big_discard + +- estats->rx_stat_dot3statsframestoolong_lo; ++ bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi); + + nstats->rx_length_errors = +- estats->rx_stat_etherstatsundersizepkts_lo + +- estats->jabber_packets_received; +- nstats->rx_over_errors = estats->brb_drop_lo + estats->brb_truncate_lo; +- nstats->rx_crc_errors = estats->rx_stat_dot3statsfcserrors_lo; +- nstats->rx_frame_errors = estats->rx_stat_dot3statsalignmenterrors_lo; +- nstats->rx_fifo_errors = old_tclient->no_buff_discard; ++ bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) + ++ bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi); ++ nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) + ++ bnx2x_hilo(&estats->brb_truncate_hi); ++ nstats->rx_crc_errors = ++ bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi); ++ nstats->rx_frame_errors = ++ bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi); ++ nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi); + nstats->rx_missed_errors = estats->xxoverflow_discard; + + nstats->rx_errors = nstats->rx_length_errors + +@@ -3774,74 +4503,97 @@ + nstats->rx_missed_errors; + + nstats->tx_aborted_errors = +- estats->tx_stat_dot3statslatecollisions_lo + +- estats->tx_stat_dot3statsexcessivecollisions_lo; +- nstats->tx_carrier_errors = estats->rx_stat_falsecarriererrors_lo; ++ bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) + ++ bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi); ++ nstats->tx_carrier_errors = ++ bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi); + nstats->tx_fifo_errors = 0; + nstats->tx_heartbeat_errors = 0; + nstats->tx_window_errors = 0; + + nstats->tx_errors = nstats->tx_aborted_errors + +- nstats->tx_carrier_errors; ++ nstats->tx_carrier_errors + ++ bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi); ++} ++ ++static void bnx2x_drv_stats_update(struct bnx2x *bp) ++{ ++ struct bnx2x_eth_stats *estats = &bp->eth_stats; ++ int i; ++ ++ estats->driver_xoff = 0; ++ estats->rx_err_discard_pkt = 0; ++ estats->rx_skb_alloc_failed = 0; ++ estats->hw_csum_err = 0; ++ for_each_rx_queue(bp, i) { ++ struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats; ++ ++ estats->driver_xoff += qstats->driver_xoff; ++ estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt; ++ estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed; ++ estats->hw_csum_err += qstats->hw_csum_err; ++ } + } + + static void bnx2x_stats_update(struct bnx2x *bp) + { + u32 *stats_comp = bnx2x_sp(bp, stats_comp); +- int update = 0; + + if (*stats_comp != DMAE_COMP_VAL) + return; + + if (bp->port.pmf) +- update = (bnx2x_hw_stats_update(bp) == 0); +- +- update |= (bnx2x_storm_stats_update(bp) == 0); +- +- if (update) +- bnx2x_net_stats_update(bp); +- +- else { +- if (bp->stats_pending) { +- bp->stats_pending++; +- if (bp->stats_pending == 3) { +- BNX2X_ERR("stats not updated for 3 times\n"); +- bnx2x_panic(); +- return; +- } +- } +- } ++ bnx2x_hw_stats_update(bp); ++ ++ if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) { ++ BNX2X_ERR("storm stats were not updated for 3 times\n"); ++ bnx2x_panic(); ++ return; ++ } ++ ++ bnx2x_net_stats_update(bp); ++ bnx2x_drv_stats_update(bp); + + if (bp->msglevel & NETIF_MSG_TIMER) { +- struct tstorm_per_client_stats *old_tclient = &bp->old_tclient; ++ struct bnx2x_fastpath *fp0_rx = bp->fp; ++ struct bnx2x_fastpath *fp0_tx = &(bp->fp[bp->num_rx_queues]); ++ struct tstorm_per_client_stats *old_tclient = ++ &bp->fp->old_tclient; ++ struct bnx2x_eth_q_stats *qstats = &bp->fp->eth_q_stats; + struct bnx2x_eth_stats *estats = &bp->eth_stats; ++#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */ + struct net_device_stats *nstats = &bp->dev->stats; ++#else ++ struct net_device_stats *nstats = &bp->net_stats; ++#endif + int i; + + printk(KERN_DEBUG "%s:\n", bp->dev->name); + printk(KERN_DEBUG " tx avail (%4x) tx hc idx (%x)" + " tx pkt (%lx)\n", +- bnx2x_tx_avail(bp->fp), +- le16_to_cpu(*bp->fp->tx_cons_sb), nstats->tx_packets); ++ bnx2x_tx_avail(fp0_tx), ++ le16_to_cpu(*fp0_tx->tx_cons_sb), nstats->tx_packets); + printk(KERN_DEBUG " rx usage (%4x) rx hc idx (%x)" + " rx pkt (%lx)\n", +- (u16)(le16_to_cpu(*bp->fp->rx_cons_sb) - +- bp->fp->rx_comp_cons), +- le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets); +- printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u\n", +- netif_queue_stopped(bp->dev) ? "Xoff" : "Xon", +- estats->driver_xoff, estats->brb_drop_lo); ++ (u16)(le16_to_cpu(*fp0_rx->rx_cons_sb) - ++ fp0_rx->rx_comp_cons), ++ le16_to_cpu(*fp0_rx->rx_cons_sb), nstats->rx_packets); ++ printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u " ++ "brb truncate %u\n", ++ (netif_queue_stopped(bp->dev) ? "Xoff" : "Xon"), ++ qstats->driver_xoff, ++ estats->brb_drop_lo, estats->brb_truncate_lo); + printk(KERN_DEBUG "tstats: checksum_discard %u " +- "packets_too_big_discard %u no_buff_discard %u " ++ "packets_too_big_discard %lu no_buff_discard %lu " + "mac_discard %u mac_filter_discard %u " + "xxovrflow_discard %u brb_truncate_discard %u " + "ttl0_discard %u\n", +- old_tclient->checksum_discard, +- old_tclient->packets_too_big_discard, +- old_tclient->no_buff_discard, estats->mac_discard, +- estats->mac_filter_discard, estats->xxoverflow_discard, +- estats->brb_truncate_discard, +- old_tclient->ttl0_discard); ++ le32_to_cpu(old_tclient->checksum_discard), ++ bnx2x_hilo(&qstats->etherstatsoverrsizepkts_hi), ++ bnx2x_hilo(&qstats->no_buff_discard_hi), ++ estats->mac_discard, estats->mac_filter_discard, ++ estats->xxoverflow_discard, estats->brb_truncate_discard, ++ le32_to_cpu(old_tclient->ttl0_discard)); + + for_each_queue(bp, i) { + printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i, +@@ -3976,6 +4728,177 @@ + state, event, bp->stats_state); + } + ++static void bnx2x_port_stats_base_init(struct bnx2x *bp) ++{ ++ struct dmae_command *dmae; ++ u32 *stats_comp = bnx2x_sp(bp, stats_comp); ++ ++ /* sanity */ ++ if (!bp->port.pmf || !bp->port.port_stx) { ++ BNX2X_ERR("BUG!\n"); ++ return; ++ } ++ ++ bp->executer_idx = 0; ++ ++ dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); ++ dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC | ++ DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE | ++ DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | ++#ifdef __BIG_ENDIAN ++ DMAE_CMD_ENDIANITY_B_DW_SWAP | ++#else ++ DMAE_CMD_ENDIANITY_DW_SWAP | ++#endif ++ (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | ++ (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); ++ dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats)); ++ dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats)); ++ dmae->dst_addr_lo = bp->port.port_stx >> 2; ++ dmae->dst_addr_hi = 0; ++ dmae->len = sizeof(struct host_port_stats) >> 2; ++ dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp)); ++ dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp)); ++ dmae->comp_val = DMAE_COMP_VAL; ++ ++ *stats_comp = 0; ++ bnx2x_hw_stats_post(bp); ++ bnx2x_stats_comp(bp); ++} ++ ++static void bnx2x_func_stats_base_init(struct bnx2x *bp) ++{ ++ int vn, vn_max = IS_E1HMF(bp) ? E1HVN_MAX : E1VN_MAX; ++ int port = BP_PORT(bp); ++ int func; ++ u32 func_stx; ++ ++ /* sanity */ ++ if (!bp->port.pmf || !bp->func_stx) { ++ BNX2X_ERR("BUG!\n"); ++ return; ++ } ++ ++ /* save our func_stx */ ++ func_stx = bp->func_stx; ++ ++ for (vn = VN_0; vn < vn_max; vn++) { ++ func = 2*vn + port; ++ ++ bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param); ++ bnx2x_func_stats_init(bp); ++ bnx2x_hw_stats_post(bp); ++ bnx2x_stats_comp(bp); ++ } ++ ++ /* restore our func_stx */ ++ bp->func_stx = func_stx; ++} ++ ++static void bnx2x_func_stats_base_update(struct bnx2x *bp) ++{ ++ struct dmae_command *dmae = &bp->stats_dmae; ++ u32 *stats_comp = bnx2x_sp(bp, stats_comp); ++ ++ /* sanity */ ++ if (!bp->func_stx) { ++ BNX2X_ERR("BUG!\n"); ++ return; ++ } ++ ++ bp->executer_idx = 0; ++ memset(dmae, 0, sizeof(struct dmae_command)); ++ ++ dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI | ++ DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE | ++ DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | ++#ifdef __BIG_ENDIAN ++ DMAE_CMD_ENDIANITY_B_DW_SWAP | ++#else ++ DMAE_CMD_ENDIANITY_DW_SWAP | ++#endif ++ (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | ++ (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); ++ dmae->src_addr_lo = bp->func_stx >> 2; ++ dmae->src_addr_hi = 0; ++ dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats_base)); ++ dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats_base)); ++ dmae->len = sizeof(struct host_func_stats) >> 2; ++ dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp)); ++ dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp)); ++ dmae->comp_val = DMAE_COMP_VAL; ++ ++ *stats_comp = 0; ++ bnx2x_hw_stats_post(bp); ++ bnx2x_stats_comp(bp); ++} ++ ++static void bnx2x_stats_init(struct bnx2x *bp) ++{ ++ int port = BP_PORT(bp); ++ int func = BP_FUNC(bp); ++ int i; ++ ++ bp->stats_pending = 0; ++ bp->executer_idx = 0; ++ bp->stats_counter = 0; ++ ++ /* port and func stats for management */ ++ if (!BP_NOMCP(bp)) { ++ bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx); ++ bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param); ++ ++ } else { ++ bp->port.port_stx = 0; ++ bp->func_stx = 0; ++ } ++ DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n", ++ bp->port.port_stx, bp->func_stx); ++ ++ /* port stats */ ++ memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats)); ++ bp->port.old_nig_stats.brb_discard = ++ REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38); ++ bp->port.old_nig_stats.brb_truncate = ++ REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38); ++ REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50, ++ &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2); ++ REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50, ++ &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2); ++ ++ /* function stats */ ++ for_each_queue(bp, i) { ++ struct bnx2x_fastpath *fp = &bp->fp[i]; ++ ++ memset(&fp->old_tclient, 0, ++ sizeof(struct tstorm_per_client_stats)); ++ memset(&fp->old_uclient, 0, ++ sizeof(struct ustorm_per_client_stats)); ++ memset(&fp->old_xclient, 0, ++ sizeof(struct xstorm_per_client_stats)); ++ memset(&fp->eth_q_stats, 0, sizeof(struct bnx2x_eth_q_stats)); ++ } ++ ++#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */ ++ memset(&bp->dev->stats, 0, sizeof(struct net_device_stats)); ++#else ++ memset(&bp->net_stats, 0, sizeof(struct net_device_stats)); ++#endif ++ memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats)); ++ ++ bp->stats_state = STATS_STATE_DISABLED; ++ ++ if (bp->port.pmf) { ++ if (bp->port.port_stx) ++ bnx2x_port_stats_base_init(bp); ++ ++ if (bp->func_stx) ++ bnx2x_func_stats_base_init(bp); ++ ++ } else if (bp->func_stx) ++ bnx2x_func_stats_base_update(bp); ++} ++ + static void bnx2x_timer(unsigned long data) + { + struct bnx2x *bp = (struct bnx2x *) data; +@@ -3990,7 +4913,7 @@ + struct bnx2x_fastpath *fp = &bp->fp[0]; + int rc; + +- bnx2x_tx_int(fp, 1000); ++ bnx2x_tx_int(fp); + rc = bnx2x_rx_int(fp, 1000); + } + +@@ -4038,12 +4961,13 @@ + { + int port = BP_PORT(bp); + +- bnx2x_init_fill(bp, USTORM_INTMEM_ADDR + +- USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, +- sizeof(struct ustorm_status_block)/4); +- bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR + +- CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, +- sizeof(struct cstorm_status_block)/4); ++ /* "CSTORM" */ ++ bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY + ++ CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), 0, ++ CSTORM_SB_STATUS_BLOCK_U_SIZE / 4); ++ bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY + ++ CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), 0, ++ CSTORM_SB_STATUS_BLOCK_C_SIZE / 4); + } + + static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb, +@@ -4059,17 +4983,17 @@ + u_status_block); + sb->u_status_block.status_block_id = sb_id; + +- REG_WR(bp, BAR_USTRORM_INTMEM + +- USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section)); +- REG_WR(bp, BAR_USTRORM_INTMEM + +- ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4), ++ REG_WR(bp, BAR_CSTRORM_INTMEM + ++ CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id), U64_LO(section)); ++ REG_WR(bp, BAR_CSTRORM_INTMEM + ++ ((CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id)) + 4), + U64_HI(section)); +- REG_WR8(bp, BAR_USTRORM_INTMEM + FP_USB_FUNC_OFF + +- USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func); ++ REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_USB_FUNC_OFF + ++ CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), func); + + for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++) +- REG_WR16(bp, BAR_USTRORM_INTMEM + +- USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1); ++ REG_WR16(bp, BAR_CSTRORM_INTMEM + ++ CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id, index), 1); + + /* CSTORM */ + section = ((u64)mapping) + offsetof(struct host_status_block, +@@ -4077,16 +5001,16 @@ + sb->c_status_block.status_block_id = sb_id; + + REG_WR(bp, BAR_CSTRORM_INTMEM + +- CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section)); ++ CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id), U64_LO(section)); + REG_WR(bp, BAR_CSTRORM_INTMEM + +- ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4), ++ ((CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id)) + 4), + U64_HI(section)); + REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF + +- CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func); ++ CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), func); + + for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++) + REG_WR16(bp, BAR_CSTRORM_INTMEM + +- CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1); ++ CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id, index), 1); + + bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0); + } +@@ -4095,16 +5019,16 @@ + { + int func = BP_FUNC(bp); + +- bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR + ++ bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY + + TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, + sizeof(struct tstorm_def_status_block)/4); +- bnx2x_init_fill(bp, USTORM_INTMEM_ADDR + +- USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, +- sizeof(struct ustorm_def_status_block)/4); +- bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR + +- CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, +- sizeof(struct cstorm_def_status_block)/4); +- bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR + ++ bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY + ++ CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), 0, ++ sizeof(struct cstorm_def_status_block_u)/4); ++ bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY + ++ CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), 0, ++ sizeof(struct cstorm_def_status_block_c)/4); ++ bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY + + XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, + sizeof(struct xstorm_def_status_block)/4); + } +@@ -4156,17 +5080,17 @@ + u_def_status_block); + def_sb->u_def_status_block.status_block_id = sb_id; + +- REG_WR(bp, BAR_USTRORM_INTMEM + +- USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); +- REG_WR(bp, BAR_USTRORM_INTMEM + +- ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), ++ REG_WR(bp, BAR_CSTRORM_INTMEM + ++ CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func), U64_LO(section)); ++ REG_WR(bp, BAR_CSTRORM_INTMEM + ++ ((CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func)) + 4), + U64_HI(section)); +- REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF + +- USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); ++ REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_USB_FUNC_OFF + ++ CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), func); + + for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++) +- REG_WR16(bp, BAR_USTRORM_INTMEM + +- USTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1); ++ REG_WR16(bp, BAR_CSTRORM_INTMEM + ++ CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(func, index), 1); + + /* CSTORM */ + section = ((u64)mapping) + offsetof(struct host_def_status_block, +@@ -4174,16 +5098,16 @@ + def_sb->c_def_status_block.status_block_id = sb_id; + + REG_WR(bp, BAR_CSTRORM_INTMEM + +- CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); ++ CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func), U64_LO(section)); + REG_WR(bp, BAR_CSTRORM_INTMEM + +- ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), ++ ((CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func)) + 4), + U64_HI(section)); + REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF + +- CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); ++ CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), func); + + for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++) + REG_WR16(bp, BAR_CSTRORM_INTMEM + +- CSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1); ++ CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(func, index), 1); + + /* TSTORM */ + section = ((u64)mapping) + offsetof(struct host_def_status_block, +@@ -4234,28 +5158,24 @@ + int sb_id = bp->fp[i].sb_id; + + /* HC_INDEX_U_ETH_RX_CQ_CONS */ +- REG_WR8(bp, BAR_USTRORM_INTMEM + +- USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id, +- U_SB_ETH_RX_CQ_INDEX), ++ REG_WR8(bp, BAR_CSTRORM_INTMEM + ++ CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, sb_id, ++ U_SB_ETH_RX_CQ_INDEX), + bp->rx_ticks/12); +- REG_WR16(bp, BAR_USTRORM_INTMEM + +- USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, +- U_SB_ETH_RX_CQ_INDEX), +- bp->rx_ticks ? 0 : 1); +- REG_WR16(bp, BAR_USTRORM_INTMEM + +- USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, +- U_SB_ETH_RX_BD_INDEX), +- bp->rx_ticks ? 0 : 1); ++ REG_WR16(bp, BAR_CSTRORM_INTMEM + ++ CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id, ++ U_SB_ETH_RX_CQ_INDEX), ++ (bp->rx_ticks/12) ? 0 : 1); + + /* HC_INDEX_C_ETH_TX_CQ_CONS */ + REG_WR8(bp, BAR_CSTRORM_INTMEM + +- CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id, +- C_SB_ETH_TX_CQ_INDEX), ++ CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id, ++ C_SB_ETH_TX_CQ_INDEX), + bp->tx_ticks/12); + REG_WR16(bp, BAR_CSTRORM_INTMEM + +- CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, +- C_SB_ETH_TX_CQ_INDEX), +- bp->tx_ticks ? 0 : 1); ++ CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id, ++ C_SB_ETH_TX_CQ_INDEX), ++ (bp->tx_ticks/12) ? 0 : 1); + } + } + +@@ -4276,8 +5196,7 @@ + if (fp->tpa_state[i] == BNX2X_TPA_START) + pci_unmap_single(bp->pdev, + pci_unmap_addr(rx_buf, mapping), +- bp->rx_buf_size, +- PCI_DMA_FROMDEVICE); ++ bp->rx_buf_size, PCI_DMA_FROMDEVICE); + + dev_kfree_skb(skb); + rx_buf->skb = NULL; +@@ -4292,16 +5211,13 @@ + u16 ring_prod, cqe_ring_prod; + int i, j; + +- bp->rx_buf_size = bp->dev->mtu; +- bp->rx_buf_size += bp->rx_offset + ETH_OVREHEAD + +- BCM_RX_ETH_PAYLOAD_ALIGN; ++ bp->rx_buf_size = bp->dev->mtu + ETH_OVREHEAD + BNX2X_RX_ALIGN; ++ DP(NETIF_MSG_IFUP, ++ "mtu %d rx_buf_size %d\n", bp->dev->mtu, bp->rx_buf_size); + + if (bp->flags & TPA_ENABLE_FLAG) { +- DP(NETIF_MSG_IFUP, +- "rx_buf_size %d effective_mtu %d\n", +- bp->rx_buf_size, bp->dev->mtu + ETH_OVREHEAD); +- +- for_each_queue(bp, j) { ++ ++ for_each_rx_queue(bp, j) { + struct bnx2x_fastpath *fp = &bp->fp[j]; + + for (i = 0; i < max_agg_queues; i++) { +@@ -4324,13 +5240,19 @@ + } + } + +- for_each_queue(bp, j) { ++ for_each_rx_queue(bp, j) { + struct bnx2x_fastpath *fp = &bp->fp[j]; + + fp->rx_bd_cons = 0; + fp->rx_cons_sb = BNX2X_RX_SB_INDEX; + fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX; + ++ /* Mark queue as Rx */ ++ fp->is_rx_queue = 1; ++ ++#if defined(__NO_TPA__) ++ fp->disable_tpa = 1; ++#else /* BNX2X_UPSTREAM */ + /* "next page" elements initialization */ + /* SGE ring */ + for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { +@@ -4346,6 +5268,7 @@ + } + + bnx2x_init_sge_ring_bit_mask(fp); ++#endif + + /* RX BD ring */ + for (i = 1; i <= NUM_RX_RINGS; i++) { +@@ -4374,6 +5297,7 @@ + BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); + } + ++#if !defined(__NO_TPA__) /* BNX2X_UPSTREAM */ + /* Allocate SGEs and initialize the ring elements */ + for (i = 0, ring_prod = 0; + i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) { +@@ -4392,6 +5316,7 @@ + ring_prod = NEXT_SGE_IDX(ring_prod); + } + fp->rx_sge_prod = ring_prod; ++#endif + + /* Allocate BDs and initialize BD ring */ + fp->rx_comp_cons = 0; +@@ -4399,8 +5324,8 @@ + for (i = 0; i < bp->rx_ring_size; i++) { + if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) { + BNX2X_ERR("was only able to allocate " +- "%d rx skbs\n", i); +- bp->eth_stats.rx_skb_alloc_failed++; ++ "%d rx skbs on queue[%d]\n", i, j); ++ fp->eth_q_stats.rx_skb_alloc_failed++; + break; + } + ring_prod = NEXT_RX_IDX(ring_prod); +@@ -4436,20 +5361,24 @@ + { + int i, j; + +- for_each_queue(bp, j) { ++ for_each_tx_queue(bp, j) { + struct bnx2x_fastpath *fp = &bp->fp[j]; + + for (i = 1; i <= NUM_TX_RINGS; i++) { +- struct eth_tx_bd *tx_bd = +- &fp->tx_desc_ring[TX_DESC_CNT * i - 1]; +- +- tx_bd->addr_hi = ++ struct eth_tx_next_bd *tx_next_bd = ++ &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; ++ ++ tx_next_bd->addr_hi = + cpu_to_le32(U64_HI(fp->tx_desc_mapping + + BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); +- tx_bd->addr_lo = ++ tx_next_bd->addr_lo = + cpu_to_le32(U64_LO(fp->tx_desc_mapping + + BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); + } ++ ++ fp->tx_db.data.header.header = DOORBELL_HDR_DB_TYPE; ++ fp->tx_db.data.zero_fill1 = 0; ++ fp->tx_db.data.prod = 0; + + fp->tx_pkt_prod = 0; + fp->tx_pkt_cons = 0; +@@ -4458,6 +5387,10 @@ + fp->tx_cons_sb = BNX2X_TX_SB_INDEX; + fp->tx_pkt = 0; + } ++ ++ /* clean tx statistics */ ++ for_each_rx_queue(bp, i) ++ bnx2x_fp(bp, i, tx_pkt) = 0; + } + + static void bnx2x_init_sp_ring(struct bnx2x *bp) +@@ -4486,30 +5419,22 @@ + { + int i; + +- for_each_queue(bp, i) { ++ for_each_rx_queue(bp, i) { + struct eth_context *context = bnx2x_sp(bp, context[i].eth); + struct bnx2x_fastpath *fp = &bp->fp[i]; +- u8 sb_id = FP_SB_ID(fp); +- +- context->xstorm_st_context.tx_bd_page_base_hi = +- U64_HI(fp->tx_desc_mapping); +- context->xstorm_st_context.tx_bd_page_base_lo = +- U64_LO(fp->tx_desc_mapping); +- context->xstorm_st_context.db_data_addr_hi = +- U64_HI(fp->tx_prods_mapping); +- context->xstorm_st_context.db_data_addr_lo = +- U64_LO(fp->tx_prods_mapping); +- context->xstorm_st_context.statistics_data = (BP_CL_ID(bp) | +- XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE); ++ u8 cl_id = fp->cl_id; + + context->ustorm_st_context.common.sb_index_numbers = + BNX2X_RX_SB_INDEX_NUM; +- context->ustorm_st_context.common.clientId = FP_CL_ID(fp); +- context->ustorm_st_context.common.status_block_id = sb_id; ++ context->ustorm_st_context.common.clientId = cl_id; ++ context->ustorm_st_context.common.status_block_id = fp->sb_id; + context->ustorm_st_context.common.flags = +- USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT; +- context->ustorm_st_context.common.mc_alignment_size = +- BCM_RX_ETH_PAYLOAD_ALIGN; ++ (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT | ++ USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS); ++ context->ustorm_st_context.common.statistics_counter_id = ++ cl_id; ++ context->ustorm_st_context.common.mc_alignment_log_size = ++ BNX2X_RX_ALIGN_SHIFT; + context->ustorm_st_context.common.bd_buff_size = + bp->rx_buf_size; + context->ustorm_st_context.common.bd_page_base_hi = +@@ -4518,8 +5443,7 @@ + U64_LO(fp->rx_desc_mapping); + if (!fp->disable_tpa) { + context->ustorm_st_context.common.flags |= +- (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA | +- USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING); ++ USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA; + context->ustorm_st_context.common.sge_buff_size = + (u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE, + (u32)0xffff); +@@ -4527,36 +5451,90 @@ + U64_HI(fp->rx_sge_mapping); + context->ustorm_st_context.common.sge_page_base_lo = + U64_LO(fp->rx_sge_mapping); +- } +- +- context->cstorm_st_context.sb_index_number = +- C_SB_ETH_TX_CQ_INDEX; +- context->cstorm_st_context.status_block_id = sb_id; +- ++ ++ context->ustorm_st_context.common.max_sges_for_packet = ++ SGE_PAGE_ALIGN(bp->dev->mtu) >> SGE_PAGE_SHIFT; ++ context->ustorm_st_context.common.max_sges_for_packet = ++ ((context->ustorm_st_context.common. ++ max_sges_for_packet + PAGES_PER_SGE - 1) & ++ (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT; ++ } ++ ++ context->ustorm_ag_context.cdu_usage = ++ CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i), ++ CDU_REGION_NUMBER_UCM_AG, ++ ETH_CONNECTION_TYPE); ++ ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ switch (bp->multi_mode) { ++ case ETH_RSS_MODE_DISABLED: ++ case ETH_RSS_MODE_REGULAR: ++ break; ++ ++ case ETH_RSS_MODE_VLAN_PRI: ++ case ETH_RSS_MODE_E1HOV_PRI: ++ case ETH_RSS_MODE_IP_DSCP: ++ context->xstorm_st_context.safc_group_en = 1; ++ context->xstorm_st_context.safc_group_num = fp->cos; ++ break; ++ ++ default: ++ break; ++ } ++#endif + context->xstorm_ag_context.cdu_reserved = + CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i), + CDU_REGION_NUMBER_XCM_AG, + ETH_CONNECTION_TYPE); +- context->ustorm_ag_context.cdu_usage = +- CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i), +- CDU_REGION_NUMBER_UCM_AG, +- ETH_CONNECTION_TYPE); ++ } ++ ++ for_each_tx_queue(bp, i) { ++ struct bnx2x_fastpath *fp = &bp->fp[i]; ++ struct eth_context *context = ++ bnx2x_sp(bp, context[i - bp->num_rx_queues].eth); ++ ++ context->cstorm_st_context.sb_index_number = ++ C_SB_ETH_TX_CQ_INDEX; ++ context->cstorm_st_context.status_block_id = fp->sb_id; ++ ++ context->xstorm_st_context.tx_bd_page_base_hi = ++ U64_HI(fp->tx_desc_mapping); ++ context->xstorm_st_context.tx_bd_page_base_lo = ++ U64_LO(fp->tx_desc_mapping); ++ context->xstorm_st_context.statistics_data = (fp->cl_id | ++ XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE); + } + } + + static void bnx2x_init_ind_table(struct bnx2x *bp) + { + int func = BP_FUNC(bp); +- int i; +- +- if (!is_multi(bp)) +- return; +- +- DP(NETIF_MSG_IFUP, "Initializing indirection table\n"); ++#ifdef BNX2X_SAFC ++ int i, cos; ++ u8 val; ++#else /* BNX2X_UPSTREAM */ ++ int i; ++#endif ++ ++ if (bp->multi_mode == ETH_RSS_MODE_DISABLED) ++ return; ++ ++ DP(NETIF_MSG_IFUP, ++ "Initializing indirection table multi_mode %d\n", bp->multi_mode); ++#ifdef BNX2X_SAFC ++ for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++) { ++ cos = bp->pri_map[i / BNX2X_MAX_ENTRIES_PER_PRI]; ++ val = bp->fp->cl_id + bp->cos_map[cos] + ++ (i % bp->qs_per_cos[cos]); ++ REG_WR8(bp, BAR_TSTRORM_INTMEM + ++ TSTORM_INDIRECTION_TABLE_OFFSET(func) + i, val); ++ } ++#else /* BNX2X_UPSTREAM */ + for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++) + REG_WR8(bp, BAR_TSTRORM_INTMEM + + TSTORM_INDIRECTION_TABLE_OFFSET(func) + i, +- BP_CL_ID(bp) + (i % bp->num_queues)); ++ bp->fp->cl_id + (i % bp->num_rx_queues)); ++#endif + } + + static void bnx2x_set_client_config(struct bnx2x *bp) +@@ -4566,30 +5544,20 @@ + int i; + + tstorm_client.mtu = bp->dev->mtu; +- tstorm_client.statistics_counter_id = BP_CL_ID(bp); + tstorm_client.config_flags = +- TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE; ++ (TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE | ++ TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE); + #ifdef BCM_VLAN + if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) { + tstorm_client.config_flags |= +- TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE; ++ TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE; + DP(NETIF_MSG_IFUP, "vlan removal enabled\n"); + } + #endif + +- if (bp->flags & TPA_ENABLE_FLAG) { +- tstorm_client.max_sges_for_packet = +- SGE_PAGE_ALIGN(tstorm_client.mtu) >> SGE_PAGE_SHIFT; +- tstorm_client.max_sges_for_packet = +- ((tstorm_client.max_sges_for_packet + +- PAGES_PER_SGE - 1) & (~(PAGES_PER_SGE - 1))) >> +- PAGES_PER_SGE_SHIFT; +- +- tstorm_client.config_flags |= +- TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING; +- } +- + for_each_queue(bp, i) { ++ tstorm_client.statistics_counter_id = bp->fp[i].cl_id; ++ + REG_WR(bp, BAR_TSTRORM_INTMEM + + TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id), + ((u32 *)&tstorm_client)[0]); +@@ -4618,18 +5586,22 @@ + tstorm_mac_filter.mcast_drop_all = mask; + tstorm_mac_filter.bcast_drop_all = mask; + break; ++ + case BNX2X_RX_MODE_NORMAL: + tstorm_mac_filter.bcast_accept_all = mask; + break; ++ + case BNX2X_RX_MODE_ALLMULTI: + tstorm_mac_filter.mcast_accept_all = mask; + tstorm_mac_filter.bcast_accept_all = mask; + break; ++ + case BNX2X_RX_MODE_PROMISC: + tstorm_mac_filter.ucast_accept_all = mask; + tstorm_mac_filter.mcast_accept_all = mask; + tstorm_mac_filter.bcast_accept_all = mask; + break; ++ + default: + BNX2X_ERR("BAD rx mode (%d)\n", mode); + break; +@@ -4651,31 +5623,33 @@ + static void bnx2x_init_internal_common(struct bnx2x *bp) + { + int i; +- +- if (bp->flags & TPA_ENABLE_FLAG) { +- struct tstorm_eth_tpa_exist tpa = {0}; +- +- tpa.tpa_exist = 1; +- +- REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET, +- ((u32 *)&tpa)[0]); +- REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET + 4, +- ((u32 *)&tpa)[1]); +- } + + /* Zero this manually as its initialization is + currently missing in the initTool */ + for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) + REG_WR(bp, BAR_USTRORM_INTMEM + + USTORM_AGG_DATA_OFFSET + i * 4, 0); ++ ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ if (bp->flags & SAFC_TX_FLAG) { ++ REG_WR(bp, BAR_TSTRORM_INTMEM + ++ TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET, 1); ++ REG_WR(bp, BAR_TSTRORM_INTMEM + ++ TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET, 10); ++ REG_WR(bp, MISC_REG_SW_TIMER_VAL + 0xc, 10); ++ REG_WR(bp, MISC_REG_SW_TIMER_RELOAD_VAL_4, 10); ++ } ++#endif + } + + static void bnx2x_init_internal_port(struct bnx2x *bp) + { + int port = BP_PORT(bp); + +- REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR); +- REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR); ++ REG_WR(bp, ++ BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_U_OFFSET(port), BNX2X_BTR); ++ REG_WR(bp, ++ BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_C_OFFSET(port), BNX2X_BTR); + REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR); + REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR); + } +@@ -4686,13 +5660,29 @@ + struct stats_indication_flags stats_flags = {0}; + int port = BP_PORT(bp); + int func = BP_FUNC(bp); +- int i; ++ int i, j; ++ u32 offset; + u16 max_agg_size; + + if (is_multi(bp)) { +- tstorm_config.config_flags = MULTI_FLAGS; ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ /* enable queue 0 as the default queue */ ++ tstorm_config.config_flags = ++ TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE; ++#else /* BNX2X_UPSTREAM */ ++ tstorm_config.config_flags = MULTI_FLAGS(bp); + tstorm_config.rss_result_mask = MULTI_MASK; +- } ++#endif ++ } ++ ++ /* Enable TPA if needed */ ++ if (bp->flags & TPA_ENABLE_FLAG) ++ tstorm_config.config_flags |= ++ TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA; ++ ++ if (IS_E1HMF(bp)) ++ tstorm_config.config_flags |= ++ TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM; + + tstorm_config.leading_client_id = BP_L_ID(bp); + +@@ -4703,17 +5693,29 @@ + bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */ + bnx2x_set_storm_rx_mode(bp); + +- /* reset xstorm per client statistics */ +- for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++) { +- REG_WR(bp, BAR_XSTRORM_INTMEM + +- XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) + +- i*4, 0); +- } +- /* reset tstorm per client statistics */ +- for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++) { +- REG_WR(bp, BAR_TSTRORM_INTMEM + +- TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) + +- i*4, 0); ++ for_each_queue(bp, i) { ++ u8 cl_id = bp->fp[i].cl_id; ++ ++ /* reset xstorm per client statistics */ ++ offset = BAR_XSTRORM_INTMEM + ++ XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id); ++ for (j = 0; ++ j < sizeof(struct xstorm_per_client_stats) / 4; j++) ++ REG_WR(bp, offset + j*4, 0); ++ ++ /* reset tstorm per client statistics */ ++ offset = BAR_TSTRORM_INTMEM + ++ TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id); ++ for (j = 0; ++ j < sizeof(struct tstorm_per_client_stats) / 4; j++) ++ REG_WR(bp, offset + j*4, 0); ++ ++ /* reset ustorm per client statistics */ ++ offset = BAR_USTRORM_INTMEM + ++ USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id); ++ for (j = 0; ++ j < sizeof(struct ustorm_per_client_stats) / 4; j++) ++ REG_WR(bp, offset + j*4, 0); + } + + /* Init statistics related context */ +@@ -4727,6 +5729,11 @@ + REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func), + ((u32 *)&stats_flags)[0]); + REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4, ++ ((u32 *)&stats_flags)[1]); ++ ++ REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func), ++ ((u32 *)&stats_flags)[0]); ++ REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func) + 4, + ((u32 *)&stats_flags)[1]); + + REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func), +@@ -4746,6 +5753,13 @@ + U64_LO(bnx2x_sp_mapping(bp, fw_stats))); + REG_WR(bp, BAR_TSTRORM_INTMEM + + TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4, ++ U64_HI(bnx2x_sp_mapping(bp, fw_stats))); ++ ++ REG_WR(bp, BAR_USTRORM_INTMEM + ++ USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func), ++ U64_LO(bnx2x_sp_mapping(bp, fw_stats))); ++ REG_WR(bp, BAR_USTRORM_INTMEM + ++ USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4, + U64_HI(bnx2x_sp_mapping(bp, fw_stats))); + + if (CHIP_IS_E1H(bp)) { +@@ -4767,20 +5781,143 @@ + min((u32)(min((u32)8, (u32)MAX_SKB_FRAGS) * + SGE_PAGE_SIZE * PAGES_PER_SGE), + (u32)0xffff); +- for_each_queue(bp, i) { ++ for_each_rx_queue(bp, i) { + struct bnx2x_fastpath *fp = &bp->fp[i]; + + REG_WR(bp, BAR_USTRORM_INTMEM + +- USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)), ++ USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id), + U64_LO(fp->rx_comp_mapping)); + REG_WR(bp, BAR_USTRORM_INTMEM + +- USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4, ++ USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id) + 4, + U64_HI(fp->rx_comp_mapping)); + ++ /* Next page */ ++ REG_WR(bp, BAR_USTRORM_INTMEM + ++ USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id), ++ U64_LO(fp->rx_comp_mapping + BCM_PAGE_SIZE)); ++ REG_WR(bp, BAR_USTRORM_INTMEM + ++ USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id) + 4, ++ U64_HI(fp->rx_comp_mapping + BCM_PAGE_SIZE)); ++ + REG_WR16(bp, BAR_USTRORM_INTMEM + +- USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)), ++ USTORM_MAX_AGG_SIZE_OFFSET(port, fp->cl_id), + max_agg_size); + } ++ ++ /* dropless flow control */ ++ if (CHIP_IS_E1H(bp)) { ++ struct ustorm_eth_rx_pause_data_e1h rx_pause = {0}; ++ ++ rx_pause.bd_thr_low = 250; ++ rx_pause.cqe_thr_low = 250; ++ rx_pause.cos = 1; ++ rx_pause.sge_thr_low = 0; ++ rx_pause.bd_thr_high = 350; ++ rx_pause.cqe_thr_high = 350; ++ rx_pause.sge_thr_high = 0; ++ ++ for_each_rx_queue(bp, i) { ++ struct bnx2x_fastpath *fp = &bp->fp[i]; ++ ++ if (!fp->disable_tpa) { ++ rx_pause.sge_thr_low = 150; ++ rx_pause.sge_thr_high = 250; ++ } ++ ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ if (bp->flags & SAFC_TX_FLAG) { ++ rx_pause.cos = 0; ++ for (j = 0; j < BNX2X_MAX_PRIORITY; j++) ++ if (bp->pri_map[j] == fp->cos) ++ rx_pause.cos |= (1 << j); ++ } ++#endif ++ ++ offset = BAR_USTRORM_INTMEM + ++ USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, ++ fp->cl_id); ++ for (j = 0; ++ j < sizeof(struct ustorm_eth_rx_pause_data_e1h)/4; ++ j++) ++ REG_WR(bp, offset + j*4, ++ ((u32 *)&rx_pause)[j]); ++ } ++ } ++ ++ memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); ++ ++ /* Init rate shaping and fairness contexts */ ++ if (IS_E1HMF(bp)) { ++ int vn; ++ ++ /* During init there is no active link ++ Until link is up, set link rate to 10Gbps */ ++ bp->link_vars.line_speed = SPEED_10000; ++ bnx2x_init_port_minmax(bp); ++ ++ bnx2x_calc_vn_weight_sum(bp); ++ ++ for (vn = VN_0; vn < E1HVN_MAX; vn++) ++ bnx2x_init_vn_minmax(bp, 2*vn + port); ++ ++ /* Enable rate shaping and fairness */ ++ bp->cmng.flags.cmng_enables = ++ CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; ++ if (bp->vn_weight_sum) ++ bp->cmng.flags.cmng_enables |= ++ CMNG_FLAGS_PER_PORT_FAIRNESS_VN; ++ else ++ DP(NETIF_MSG_IFUP, "All MIN values are zeroes" ++ " fairness will be disabled\n"); ++ } else { ++#ifdef BNX2X_SAFC ++ if (bp->cos_weight_sum) { ++ /* During init there is no active link ++ Until link is up, set link rate to 10Gbps */ ++ bp->link_vars.line_speed = SPEED_10000; ++ bnx2x_init_port_minmax(bp); ++ ++ bnx2x_init_cos_credit(bp); ++ ++ /* Enable fairness */ ++ bp->cmng.flags.cmng_enables = ++ CMNG_FLAGS_PER_PORT_FAIRNESS_COS; ++ } else ++ DP(NETIF_MSG_IFUP, "All MIN values are zeroes" ++ " fairness will be disabled\n"); ++#else /* BNX2X_UPSTREAM */ ++ /* rate shaping and fairness are disabled */ ++ DP(NETIF_MSG_IFUP, ++ "single function mode minmax will be disabled\n"); ++#endif ++ } ++ ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ switch (bp->multi_mode) { ++ case ETH_RSS_MODE_DISABLED: ++ case ETH_RSS_MODE_REGULAR: ++ break; ++ ++ case ETH_RSS_MODE_VLAN_PRI: ++ case ETH_RSS_MODE_E1HOV_PRI: ++ case ETH_RSS_MODE_IP_DSCP: ++ bp->cmng.safc_vars.safc_timeout_usec = 200; ++ for (i = 0; i < BNX2X_MAX_PRIORITY; i++) ++ bp->cmng.safc_vars.cos_to_pause_mask[i] = ++ (1 << bp->pri_map[i]); ++ break; ++ ++ default: ++ break; ++ } ++#endif ++ ++ /* Store it to internal memory */ ++ if (bp->port.pmf) ++ for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++) ++ REG_WR(bp, BAR_XSTRORM_INTMEM + ++ XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4, ++ ((u32 *)(&bp->cmng))[i]); + } + + static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) +@@ -4807,6 +5944,9 @@ + static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) + { + int i; ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ int cos, num_queues; ++#endif + + for_each_queue(bp, i) { + struct bnx2x_fastpath *fp = &bp->fp[i]; +@@ -4815,14 +5955,51 @@ + fp->state = BNX2X_FP_STATE_CLOSED; + fp->index = i; + fp->cl_id = BP_L_ID(bp) + i; ++#ifdef BCM_CNIC ++ fp->sb_id = fp->cl_id + 1; ++#else/* BNX2X_UPSTREAM */ + fp->sb_id = fp->cl_id; ++#endif ++ /* Suitable Rx and Tx SBs are served by the same client */ ++ if (i >= bp->num_rx_queues) ++ fp->cl_id -= bp->num_rx_queues; ++#ifdef BNX2X_SAFC ++ num_queues = 0; ++ for (cos = 0; cos < BNX2X_MAX_COS; cos++) { ++ if (i < (num_queues + bp->qs_per_cos[cos])) { ++ fp->cos = cos; ++ break; ++ } else ++ num_queues += bp->qs_per_cos[cos]; ++ } ++ DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " ++ "cl_id %d sb %d cos %d\n", ++ i, bp, fp->status_blk, fp->cl_id, fp->sb_id, fp->cos); ++#else /* BNX2X_UPSTREAM */ + DP(NETIF_MSG_IFUP, +- "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n", +- bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp)); ++ "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d sb %d\n", ++ i, bp, fp->status_blk, fp->cl_id, fp->sb_id); ++#endif + bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping, +- FP_SB_ID(fp)); ++ fp->sb_id); + bnx2x_update_fpsb_idx(fp); + } ++ ++ /* ensure status block indices were read */ ++ rmb(); ++ ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ for (cos = 0; cos < BNX2X_MAX_COS; cos++) { ++ bp->cos_map[cos] = 0; ++ for_each_queue(bp, i) { ++ /* take the 1st queue that belongs to this cos */ ++ if (bp->fp[i].cos == cos) { ++ bp->cos_map[cos] = i; ++ break; ++ } ++ } ++ } ++#endif + + bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping, + DEF_SB_ID); +@@ -4844,6 +6021,11 @@ + mmiowb(); + + bnx2x_int_enable(bp); ++ ++ /* Check for SPIO5 */ ++ bnx2x_attn_int_deasserted0(bp, ++ REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & ++ AEU_INPUTS_ATTN_BITS_SPIO5); + } + + /* end of nic init */ +@@ -4899,13 +6081,15 @@ + } + } + +-static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len) ++static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) + { + int n, rc; + + /* check gzip header */ +- if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) +- return -EINVAL; ++ if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { ++ BNX2X_ERR("Bad gzip header\n"); ++ return -EINVAL; ++ } + + n = 10; + +@@ -4914,7 +6098,7 @@ + if (zbuf[3] & FNAME) + while ((zbuf[n++] != 0) && (n < len)); + +- bp->strm->next_in = zbuf + n; ++ bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; + bp->strm->avail_in = len - n; + bp->strm->next_out = bp->gunzip_buf; + bp->strm->avail_out = FW_BUF_SIZE; +@@ -5036,8 +6220,8 @@ + msleep(50); + REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); + msleep(50); +- bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END); +- bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END); ++ bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE); + + DP(NETIF_MSG_HW, "part2\n"); + +@@ -5101,9 +6285,9 @@ + msleep(50); + REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); + msleep(50); +- bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END); +- bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END); +-#ifndef BCM_ISCSI ++ bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE); ++#ifndef BCM_CNIC /* BNX2X_UPSTREAM */ + /* set NIC mode */ + REG_WR(bp, PRS_REG_NIC_MODE, 1); + #endif +@@ -5158,6 +6342,39 @@ + REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18); /* bit 3,4 masked */ + } + ++#ifdef BNX2X_EXTRA_DEBUG /* ! BNX2X_UPSTREAM */ ++static void enable_blocks_parity(struct bnx2x *bp) ++{ ++ REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); /* bit 19 masked */ ++ REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020);/* bit 5,18,20-31 */ ++ REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); /* bit 5 */ ++ REG_WR(bp, QM_REG_QM_PRTY_MASK, 0x0); ++ REG_WR(bp, DORQ_REG_DORQ_PRTY_MASK, 0x0); ++ REG_WR(bp, GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 0x0); ++ REG_WR(bp, GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 0x0); ++ REG_WR(bp, SRC_REG_SRC_PRTY_MASK, 0x4); /* bit 2 */ ++ REG_WR(bp, CDU_REG_CDU_PRTY_MASK, 0x0); ++ REG_WR(bp, CFC_REG_CFC_PRTY_MASK, 0x0); ++ REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); ++ REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); ++ REG_WR(bp, DBG_REG_DBG_PRTY_MASK, 0x0); ++ REG_WR(bp, DMAE_REG_DMAE_PRTY_MASK, 0x0); ++ REG_WR(bp, BRB1_REG_BRB1_PRTY_MASK, 0x0); ++ REG_WR(bp, PRS_REG_PRS_PRTY_MASK, (1<<6)); /* bit 6 */ ++ REG_WR(bp, TSDM_REG_TSDM_PRTY_MASK, 0x8); /* bit 3 */ ++ REG_WR(bp, CSDM_REG_CSDM_PRTY_MASK, 0x8); /* bit 3 */ ++ REG_WR(bp, USDM_REG_USDM_PRTY_MASK, 0x28); /* bit 3,5 */ ++ REG_WR(bp, XSDM_REG_XSDM_PRTY_MASK, 0x8); /* bit 3 */ ++ REG_WR(bp, TSEM_REG_TSEM_PRTY_MASK_0, 0x0); ++ REG_WR(bp, TSEM_REG_TSEM_PRTY_MASK_1, 0x0); ++ REG_WR(bp, USEM_REG_USEM_PRTY_MASK_0, 0x0); ++ REG_WR(bp, USEM_REG_USEM_PRTY_MASK_1, 0x0); ++ REG_WR(bp, CSEM_REG_CSEM_PRTY_MASK_0, 0x0); ++ REG_WR(bp, CSEM_REG_CSEM_PRTY_MASK_1, 0x0); ++ REG_WR(bp, XSEM_REG_XSEM_PRTY_MASK_0, 0x0); ++ REG_WR(bp, XSEM_REG_XSEM_PRTY_MASK_1, 0x0); ++} ++#endif + + static void bnx2x_reset_common(struct bnx2x *bp) + { +@@ -5167,9 +6384,84 @@ + REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403); + } + ++static void bnx2x_init_pxp(struct bnx2x *bp) ++{ ++ u16 devctl; ++ int r_order, w_order; ++ ++ pci_read_config_word(bp->pdev, ++ bp->pcie_cap + PCI_EXP_DEVCTL, &devctl); ++ DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); ++ w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); ++ if (bp->mrrs == -1) ++ r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); ++ else { ++ DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); ++ r_order = bp->mrrs; ++ } ++ ++ bnx2x_init_pxp_arb(bp, r_order, w_order); ++} ++ ++static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) ++{ ++ u32 val; ++ u8 port; ++ u8 is_required = 0; ++ ++ val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & ++ SHARED_HW_CFG_FAN_FAILURE_MASK; ++ ++ if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) ++ is_required = 1; ++ ++ /* ++ * The fan failure mechanism is usually related to the PHY type since ++ * the power consumption of the board is affected by the PHY. Currently, ++ * fan is required for most designs with SFX7101, BCM8727 and BCM8481. ++ */ ++ else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) ++ for (port = PORT_0; port < PORT_MAX; port++) { ++ u32 phy_type = ++ SHMEM_RD(bp, dev_info.port_hw_config[port]. ++ external_phy_config) & ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; ++ is_required |= ++ ((phy_type == ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) || ++ (phy_type == ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || ++ (phy_type == ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481)); ++ } ++ ++ DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); ++ ++ if (is_required == 0) ++ return; ++ ++ /* Fan failure is indicated by SPIO 5 */ ++ bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, ++ MISC_REGISTERS_SPIO_INPUT_HI_Z); ++ ++ /* set to active low mode */ ++ val = REG_RD(bp, MISC_REG_SPIO_INT); ++ val |= ((1 << MISC_REGISTERS_SPIO_5) << ++ MISC_REGISTERS_SPIO_INT_OLD_SET_POS); ++ REG_WR(bp, MISC_REG_SPIO_INT, val); ++ ++ /* enable interrupt to signal the IGU */ ++ val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); ++ val |= (1 << MISC_REGISTERS_SPIO_5); ++ REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); ++} ++ + static int bnx2x_init_common(struct bnx2x *bp) + { + u32 val, i; ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ u32 wb_write[2]; ++#endif + + DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_FUNC(bp)); + +@@ -5177,7 +6469,7 @@ + REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); + REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc); + +- bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END); ++ bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE); + if (CHIP_IS_E1H(bp)) + REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp)); + +@@ -5185,14 +6477,14 @@ + msleep(30); + REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0); + +- bnx2x_init_block(bp, PXP_COMMON_START, PXP_COMMON_END); ++ bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE); + if (CHIP_IS_E1(bp)) { + /* enable HW interrupt from PXP on USDM overflow + bit 16 on INT_MASK_0 */ + REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); + } + +- bnx2x_init_block(bp, PXP2_COMMON_START, PXP2_COMMON_END); ++ bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE); + bnx2x_init_pxp(bp); + + #ifdef __BIG_ENDIAN +@@ -5201,6 +6493,8 @@ + REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); + REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); + REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); ++ /* make sure this value is 0 */ ++ REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); + + /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ + REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); +@@ -5210,7 +6504,7 @@ + #endif + + REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2); +-#ifdef BCM_ISCSI ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ + REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5); + REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5); + REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5); +@@ -5236,95 +6530,100 @@ + REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); + REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); + +- bnx2x_init_block(bp, DMAE_COMMON_START, DMAE_COMMON_END); ++ bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE); + + /* clean the DMAE memory */ + bp->dmae_ready = 1; + bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8); + +- bnx2x_init_block(bp, TCM_COMMON_START, TCM_COMMON_END); +- bnx2x_init_block(bp, UCM_COMMON_START, UCM_COMMON_END); +- bnx2x_init_block(bp, CCM_COMMON_START, CCM_COMMON_END); +- bnx2x_init_block(bp, XCM_COMMON_START, XCM_COMMON_END); ++ bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE); + + bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); + bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); + bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); + bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); + +- bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END); ++ bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE); ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ switch (bp->multi_mode) { ++ case ETH_RSS_MODE_DISABLED: ++ case ETH_RSS_MODE_REGULAR: ++ break; ++ ++ case ETH_RSS_MODE_VLAN_PRI: ++ case ETH_RSS_MODE_E1HOV_PRI: ++ case ETH_RSS_MODE_IP_DSCP: ++ REG_WR(bp, QM_REG_BYTECRDINITVAL, 0x5dc0); ++ break; ++ ++ default: ++ break; ++ } ++#endif ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ wb_write[0] = 0; ++ wb_write[1] = 0; ++ for (i = 0; i < 64; i++) { ++ REG_WR(bp, QM_REG_BASEADDR + i*4, 1024 * 4 * (i%16)); ++ bnx2x_init_ind_wr(bp, QM_REG_PTRTBL + i*8, wb_write, 2); ++ ++ if (CHIP_IS_E1H(bp)) { ++ REG_WR(bp, QM_REG_BASEADDR_EXT_A + i*4, 1024*4*(i%16)); ++ bnx2x_init_ind_wr(bp, QM_REG_PTRTBL_EXT_A + i*8, ++ wb_write, 2); ++ } ++ } ++#endif + /* soft reset pulse */ + REG_WR(bp, QM_REG_SOFT_RESET, 1); + REG_WR(bp, QM_REG_SOFT_RESET, 0); + +-#ifdef BCM_ISCSI +- bnx2x_init_block(bp, TIMERS_COMMON_START, TIMERS_COMMON_END); +-#endif +- +- bnx2x_init_block(bp, DQ_COMMON_START, DQ_COMMON_END); ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE); ++#endif ++ ++ bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE); + REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT); + if (!CHIP_REV_IS_SLOW(bp)) { + /* enable hw interrupt from doorbell Q */ + REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); + } + +- bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END); +- if (CHIP_REV_IS_SLOW(bp)) { +- /* fix for emulation and FPGA for no pause */ +- REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 513); +- REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 513); +- REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0); +- REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0); +- } +- +- bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END); ++ bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE); + REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); ++#ifndef BCM_CNIC /* BNX2X_UPSTREAM */ + /* set NIC mode */ + REG_WR(bp, PRS_REG_NIC_MODE, 1); ++#endif ++#ifdef BNX2X_SAFC ++ if (CHIP_IS_E1H(bp)) { ++ val = (IS_E1HMF(bp) || ++ (bp->multi_mode == ETH_RSS_MODE_E1HOV_PRI)) ? 1 : 0; ++ REG_WR(bp, PRS_REG_E1HOV_MODE, val); ++ } ++#else /* BNX2X_UPSTREAM */ + if (CHIP_IS_E1H(bp)) + REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp)); +- +- bnx2x_init_block(bp, TSDM_COMMON_START, TSDM_COMMON_END); +- bnx2x_init_block(bp, CSDM_COMMON_START, CSDM_COMMON_END); +- bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END); +- bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END); +- +- if (CHIP_IS_E1H(bp)) { +- bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, +- STORM_INTMEM_SIZE_E1H/2); +- bnx2x_init_fill(bp, +- TSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2, +- 0, STORM_INTMEM_SIZE_E1H/2); +- bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0, +- STORM_INTMEM_SIZE_E1H/2); +- bnx2x_init_fill(bp, +- CSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2, +- 0, STORM_INTMEM_SIZE_E1H/2); +- bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0, +- STORM_INTMEM_SIZE_E1H/2); +- bnx2x_init_fill(bp, +- XSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2, +- 0, STORM_INTMEM_SIZE_E1H/2); +- bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0, +- STORM_INTMEM_SIZE_E1H/2); +- bnx2x_init_fill(bp, +- USTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2, +- 0, STORM_INTMEM_SIZE_E1H/2); +- } else { /* E1 */ +- bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, +- STORM_INTMEM_SIZE_E1); +- bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0, +- STORM_INTMEM_SIZE_E1); +- bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0, +- STORM_INTMEM_SIZE_E1); +- bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0, +- STORM_INTMEM_SIZE_E1); +- } +- +- bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END); +- bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END); +- bnx2x_init_block(bp, CSEM_COMMON_START, CSEM_COMMON_END); +- bnx2x_init_block(bp, XSEM_COMMON_START, XSEM_COMMON_END); ++#endif ++ ++ bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE); ++ ++ bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp)); ++ bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp)); ++ bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp)); ++ bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp)); ++ ++ bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE); + + /* sync semi rtc */ + REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, +@@ -5332,17 +6631,28 @@ + REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, + 0x80000000); + +- bnx2x_init_block(bp, UPB_COMMON_START, UPB_COMMON_END); +- bnx2x_init_block(bp, XPB_COMMON_START, XPB_COMMON_END); +- bnx2x_init_block(bp, PBF_COMMON_START, PBF_COMMON_END); ++ bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE); + + REG_WR(bp, SRC_REG_SOFT_RST, 1); + for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) { + REG_WR(bp, i, 0xc0cac01a); + /* TODO: replace with something meaningful */ + } +- if (CHIP_IS_E1H(bp)) +- bnx2x_init_block(bp, SRCH_COMMON_START, SRCH_COMMON_END); ++ bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE); ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); ++ REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); ++ REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); ++ REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); ++ REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); ++ REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); ++ REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); ++ REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); ++ REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); ++ REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); ++#endif + REG_WR(bp, SRC_REG_SOFT_RST, 0); + + if (sizeof(union cdu_context) != 1024) +@@ -5350,32 +6660,32 @@ + printk(KERN_ALERT PFX "please adjust the size of" + " cdu_context(%ld)\n", (long)sizeof(union cdu_context)); + +- bnx2x_init_block(bp, CDU_COMMON_START, CDU_COMMON_END); ++ bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE); + val = (4 << 24) + (0 << 12) + 1024; + REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); +- if (CHIP_IS_E1(bp)) { +- /* !!! fix pxp client crdit until excel update */ +- REG_WR(bp, CDU_REG_CDU_DEBUG, 0x264); +- REG_WR(bp, CDU_REG_CDU_DEBUG, 0); +- } +- +- bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END); ++ ++ bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE); + REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); +- +- bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END); +- bnx2x_init_block(bp, MISC_AEU_COMMON_START, MISC_AEU_COMMON_END); +- +- /* PXPCS COMMON comes here */ ++ /* enable context validation interrupt from CFC */ ++ REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); ++ ++ /* set the thresholds to prevent CFC/CDU race */ ++ REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); ++ ++ bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE); ++ ++ bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE); + /* Reset PCIE errors for debug */ + REG_WR(bp, 0x2814, 0xffffffff); + REG_WR(bp, 0x3820, 0xffffffff); + +- /* EMAC0 COMMON comes here */ +- /* EMAC1 COMMON comes here */ +- /* DBU COMMON comes here */ +- /* DBG COMMON comes here */ +- +- bnx2x_init_block(bp, NIG_COMMON_START, NIG_COMMON_END); ++ bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE); ++ bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE); ++ ++ bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE); + if (CHIP_IS_E1H(bp)) { + REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp)); + REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp)); +@@ -5413,33 +6723,27 @@ + return -EBUSY; + } + +- switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) { +- case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G: +- case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: +- /* Fan failure is indicated by SPIO 5 */ +- bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, +- MISC_REGISTERS_SPIO_INPUT_HI_Z); +- +- /* set to active low mode */ +- val = REG_RD(bp, MISC_REG_SPIO_INT); +- val |= ((1 << MISC_REGISTERS_SPIO_5) << +- MISC_REGISTERS_SPIO_INT_OLD_SET_POS); +- REG_WR(bp, MISC_REG_SPIO_INT, val); +- +- /* enable interrupt to signal the IGU */ +- val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); +- val |= (1 << MISC_REGISTERS_SPIO_5); +- REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); +- break; +- +- default: +- break; +- } ++ switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) { ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: ++ bp->port.need_hw_lock = 1; ++ break; ++ ++ default: ++ break; ++ } ++ ++ bnx2x_setup_fan_failure_detection(bp); + + /* clear PXP2 attentions */ + REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); + + enable_blocks_attention(bp); ++#ifdef BNX2X_EXTRA_DEBUG /* ! BNX2X_UPSTREAM */ ++ enable_blocks_parity(bp); ++#endif + + if (!BP_NOMCP(bp)) { + bnx2x_acquire_phy_lock(bp); +@@ -5454,69 +6758,83 @@ + static int bnx2x_init_port(struct bnx2x *bp) + { + int port = BP_PORT(bp); +- u32 val; ++ int init_stage = port ? PORT1_STAGE : PORT0_STAGE; ++ u32 low, high; ++ u32 val; ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ int i; ++#endif + + DP(BNX2X_MSG_MCP, "starting port init port %x\n", port); + + REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); + +- /* Port PXP comes here */ +- /* Port PXP2 comes here */ +-#ifdef BCM_ISCSI +- /* Port0 1 +- * Port1 385 */ +- i++; +- wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping); +- wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping); +- REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2); +- REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i)); +- +- /* Port0 2 +- * Port1 386 */ +- i++; +- wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping); +- wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping); +- REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2); +- REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i)); +- +- /* Port0 3 +- * Port1 387 */ +- i++; +- wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping); +- wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping); +- REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2); +- REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i)); +-#endif +- /* Port CMs come here */ +- +- /* Port QM comes here */ +-#ifdef BCM_ISCSI +- REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20); +- REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31); +- +- bnx2x_init_block(bp, func ? TIMERS_PORT1_START : TIMERS_PORT0_START, +- func ? TIMERS_PORT1_END : TIMERS_PORT0_END); +-#endif +- /* Port DQ comes here */ +- /* Port BRB1 comes here */ +- /* Port PRS comes here */ +- /* Port TSDM comes here */ +- /* Port CSDM comes here */ +- /* Port USDM comes here */ +- /* Port XSDM comes here */ +- bnx2x_init_block(bp, port ? TSEM_PORT1_START : TSEM_PORT0_START, +- port ? TSEM_PORT1_END : TSEM_PORT0_END); +- bnx2x_init_block(bp, port ? USEM_PORT1_START : USEM_PORT0_START, +- port ? USEM_PORT1_END : USEM_PORT0_END); +- bnx2x_init_block(bp, port ? CSEM_PORT1_START : CSEM_PORT0_START, +- port ? CSEM_PORT1_END : CSEM_PORT0_END); +- bnx2x_init_block(bp, port ? XSEM_PORT1_START : XSEM_PORT0_START, +- port ? XSEM_PORT1_END : XSEM_PORT0_END); +- /* Port UPB comes here */ +- /* Port XPB comes here */ +- +- bnx2x_init_block(bp, port ? PBF_PORT1_START : PBF_PORT0_START, +- port ? PBF_PORT1_END : PBF_PORT0_END); ++ bnx2x_init_block(bp, PXP_BLOCK, init_stage); ++ bnx2x_init_block(bp, PXP2_BLOCK, init_stage); ++ ++ bnx2x_init_block(bp, TCM_BLOCK, init_stage); ++ bnx2x_init_block(bp, UCM_BLOCK, init_stage); ++ bnx2x_init_block(bp, CCM_BLOCK, init_stage); ++ bnx2x_init_block(bp, XCM_BLOCK, init_stage); ++ ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ REG_WR(bp, QM_REG_CONNNUM_0 + port*4, 1024/16 - 1); ++ ++ bnx2x_init_block(bp, TIMERS_BLOCK, init_stage); ++ REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); ++ REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); ++#endif ++ ++ bnx2x_init_block(bp, DQ_BLOCK, init_stage); ++ ++ bnx2x_init_block(bp, BRB1_BLOCK, init_stage); ++ if (CHIP_REV_IS_SLOW(bp) && !CHIP_IS_E1H(bp)) { ++ /* no pause for emulation and FPGA */ ++ low = 0; ++ high = 513; ++ } else { ++ if (IS_E1HMF(bp)) ++ low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); ++ else if (bp->dev->mtu > 4096) { ++ if (bp->flags & ONE_PORT_FLAG) ++ low = 160; ++ else { ++ val = bp->dev->mtu; ++ /* (24*1024 + val*4)/256 */ ++ low = 96 + (val/64) + ((val % 64) ? 1 : 0); ++ } ++ } else ++ low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); ++ high = low + 56; /* 14*1024/256 */ ++ } ++ REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); ++ REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); ++ ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ if (bp->flags & SAFC_TX_FLAG) { ++ REG_WR(bp, BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 + port*4, 0xa0); ++ REG_WR(bp, BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 + port*4, 0xd8); ++ REG_WR(bp, BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 + port*4, 0xa0); ++ REG_WR(bp, BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 + port*4, 0xd8); ++ } ++#endif ++ ++ bnx2x_init_block(bp, PRS_BLOCK, init_stage); ++ ++ bnx2x_init_block(bp, TSDM_BLOCK, init_stage); ++ bnx2x_init_block(bp, CSDM_BLOCK, init_stage); ++ bnx2x_init_block(bp, USDM_BLOCK, init_stage); ++ bnx2x_init_block(bp, XSDM_BLOCK, init_stage); ++ ++ bnx2x_init_block(bp, TSEM_BLOCK, init_stage); ++ bnx2x_init_block(bp, USEM_BLOCK, init_stage); ++ bnx2x_init_block(bp, CSEM_BLOCK, init_stage); ++ bnx2x_init_block(bp, XSEM_BLOCK, init_stage); ++ ++ bnx2x_init_block(bp, UPB_BLOCK, init_stage); ++ bnx2x_init_block(bp, XPB_BLOCK, init_stage); ++ ++ bnx2x_init_block(bp, PBF_BLOCK, init_stage); + + /* configure PBF to work without PAUSE mtu 9000 */ + REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); +@@ -5531,33 +6849,19 @@ + msleep(5); + REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); + +-#ifdef BCM_ISCSI +- /* tell the searcher where the T2 table is */ +- REG_WR(bp, SRC_REG_COUNTFREE0 + func*4, 16*1024/64); +- +- wb_write[0] = U64_LO(bp->t2_mapping); +- wb_write[1] = U64_HI(bp->t2_mapping); +- REG_WR_DMAE(bp, SRC_REG_FIRSTFREE0 + func*4, wb_write, 2); +- wb_write[0] = U64_LO((u64)bp->t2_mapping + 16*1024 - 64); +- wb_write[1] = U64_HI((u64)bp->t2_mapping + 16*1024 - 64); +- REG_WR_DMAE(bp, SRC_REG_LASTFREE0 + func*4, wb_write, 2); +- +- REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + func*4, 10); +- /* Port SRCH comes here */ +-#endif +- /* Port CDU comes here */ +- /* Port CFC comes here */ ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ bnx2x_init_block(bp, SRCH_BLOCK, init_stage); ++#endif ++ bnx2x_init_block(bp, CDU_BLOCK, init_stage); ++ bnx2x_init_block(bp, CFC_BLOCK, init_stage); + + if (CHIP_IS_E1(bp)) { + REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); + REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); + } +- bnx2x_init_block(bp, port ? HC_PORT1_START : HC_PORT0_START, +- port ? HC_PORT1_END : HC_PORT0_END); +- +- bnx2x_init_block(bp, port ? MISC_AEU_PORT1_START : +- MISC_AEU_PORT0_START, +- port ? MISC_AEU_PORT1_END : MISC_AEU_PORT0_END); ++ bnx2x_init_block(bp, HC_BLOCK, init_stage); ++ ++ bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage); + /* init aeu_mask_attn_func_0/1: + * - SF mode: bits 3-7 are masked. only bits 0-2 are in use + * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF +@@ -5565,45 +6869,96 @@ + REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, + (IS_E1HMF(bp) ? 0xF7 : 0x7)); + +- /* Port PXPCS comes here */ +- /* Port EMAC0 comes here */ +- /* Port EMAC1 comes here */ +- /* Port DBU comes here */ +- /* Port DBG comes here */ +- bnx2x_init_block(bp, port ? NIG_PORT1_START : NIG_PORT0_START, +- port ? NIG_PORT1_END : NIG_PORT0_END); ++ bnx2x_init_block(bp, PXPCS_BLOCK, init_stage); ++ bnx2x_init_block(bp, EMAC0_BLOCK, init_stage); ++ bnx2x_init_block(bp, EMAC1_BLOCK, init_stage); ++ bnx2x_init_block(bp, DBU_BLOCK, init_stage); ++ bnx2x_init_block(bp, DBG_BLOCK, init_stage); ++ ++ bnx2x_init_block(bp, NIG_BLOCK, init_stage); + + REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); + + if (CHIP_IS_E1H(bp)) { +- u32 wsum; +- struct cmng_struct_per_port m_cmng_port; +- int vn; +- + /* 0x2 disable e1hov, 0x1 enable */ + REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, + (IS_E1HMF(bp) ? 0x1 : 0x2)); + +- /* Init RATE SHAPING and FAIRNESS contexts. +- Initialize as if there is 10G link. */ +- wsum = bnx2x_calc_vn_wsum(bp); +- bnx2x_init_port_minmax(bp, (int)wsum, 10000, &m_cmng_port); +- if (IS_E1HMF(bp)) +- for (vn = VN_0; vn < E1HVN_MAX; vn++) +- bnx2x_init_vn_minmax(bp, 2*vn + port, +- wsum, 10000, &m_cmng_port); +- } +- +- /* Port MCP comes here */ +- /* Port DMAE comes here */ +- +- switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) { +- case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G: +- case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: ++#ifdef BNX2X_SAFC ++ if (bp->flags & SAFC_TX_FLAG) { ++ high = 0; ++ for (i = 0; i < BNX2X_MAX_PRIORITY; i++) ++ if (bp->pri_map[i] == 1) ++ high |= (1 << i); ++ REG_WR(bp, ++ NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 + port*4, ++ high); ++ low = 0; ++ for (i = 0; i < BNX2X_MAX_PRIORITY; i++) ++ if (bp->pri_map[i] == 0) ++ low |= (1 << i); ++ REG_WR(bp, ++ NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 + port*4, ++ low); ++ ++ REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 0); ++ REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 1); ++ REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 1); ++ } else { ++#else /* BNX2X_UPSTREAM */ ++ { ++#endif ++ REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); ++ REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); ++ REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); ++ } ++ } ++ ++ bnx2x_init_block(bp, MCP_BLOCK, init_stage); ++ bnx2x_init_block(bp, DMAE_BLOCK, init_stage); ++ ++ switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) { ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: ++ { ++ u32 swap_val, swap_override, aeu_gpio_mask, offset; ++ ++ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, ++ MISC_REGISTERS_GPIO_INPUT_HI_Z, port); ++ ++ /* The GPIO should be swapped if the swap register is ++ set and active */ ++ swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); ++ swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); ++ ++ /* Select function upon port-swap configuration */ ++ if (port == 0) { ++ offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; ++ aeu_gpio_mask = (swap_val && swap_override) ? ++ AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 : ++ AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0; ++ } else { ++ offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; ++ aeu_gpio_mask = (swap_val && swap_override) ? ++ AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 : ++ AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1; ++ } ++ val = REG_RD(bp, offset); ++ /* add GPIO3 to group */ ++ val |= aeu_gpio_mask; ++ REG_WR(bp, offset, val); ++ } ++ break; ++ ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: + /* add SPIO 5 to group 0 */ +- val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); ++ { ++ u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : ++ MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); ++ val = REG_RD(bp, reg_addr); + val |= AEU_INPUTS_ATTN_BITS_SPIO5; +- REG_WR(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, val); ++ REG_WR(bp, reg_addr, val); ++ } + break; + + default: +@@ -5627,7 +6982,12 @@ + #define PXP_ONE_ILT(x) (((x) << 10) | x) + #define PXP_ILT_RANGE(f, l) (((l) << 10) | f) + ++#ifdef BCM_CNIC ++#define CNIC_ILT_LINES 127 ++#define CNIC_CTX_PER_ILT 16 ++#else /* BNX2X_UPSTREAM */ + #define CNIC_ILT_LINES 0 ++#endif + + static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) + { +@@ -5645,9 +7005,16 @@ + { + int port = BP_PORT(bp); + int func = BP_FUNC(bp); ++ u32 addr, val; + int i; + + DP(BNX2X_MSG_MCP, "starting func init func %x\n", func); ++ ++ /* set MSI reconfigure capability */ ++ addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); ++ val = REG_RD(bp, addr); ++ val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; ++ REG_WR(bp, addr, val); + + i = FUNC_ILT_BASE(func); + +@@ -5659,11 +7026,54 @@ + REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4, + PXP_ILT_RANGE(i, i + CNIC_ILT_LINES)); + +- ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ i += 1 + CNIC_ILT_LINES; ++ bnx2x_ilt_wr(bp, i, bp->timers_mapping); + if (CHIP_IS_E1H(bp)) { +- for (i = 0; i < 9; i++) +- bnx2x_init_block(bp, +- cm_start[func][i], cm_end[func][i]); ++ REG_WR(bp, PXP2_REG_RQ_TM_FIRST_ILT, i); ++ REG_WR(bp, PXP2_REG_RQ_TM_LAST_ILT, i); ++ } else /* E1 */ ++ REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i)); ++ ++ i++; ++ bnx2x_ilt_wr(bp, i, bp->qm_mapping); ++ if (CHIP_IS_E1H(bp)) { ++ REG_WR(bp, PXP2_REG_RQ_QM_FIRST_ILT, i); ++ REG_WR(bp, PXP2_REG_RQ_QM_LAST_ILT, i); ++ } else /* E1 */ ++ REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i)); ++ ++ i++; ++ bnx2x_ilt_wr(bp, i, bp->t1_mapping); ++ if (CHIP_IS_E1H(bp)) { ++ REG_WR(bp, PXP2_REG_RQ_SRC_FIRST_ILT, i); ++ REG_WR(bp, PXP2_REG_RQ_SRC_LAST_ILT, i); ++ } else /* E1 */ ++ REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i)); ++ ++ /* tell the searcher where the T2 table is */ ++ REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, 16*1024/64); ++ ++ bnx2x_wb_wr(bp, SRC_REG_FIRSTFREE0 + port*16, ++ U64_LO(bp->t2_mapping), U64_HI(bp->t2_mapping)); ++ ++ bnx2x_wb_wr(bp, SRC_REG_LASTFREE0 + port*16, ++ U64_LO((u64)bp->t2_mapping + 16*1024 - 64), ++ U64_HI((u64)bp->t2_mapping + 16*1024 - 64)); ++ ++ REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, 10); ++#endif ++ ++ if (CHIP_IS_E1H(bp)) { ++ bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func); ++ bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func); ++ bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func); ++ bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func); ++ bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func); ++ bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func); ++ bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func); ++ bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func); ++ bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func); + + REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); + REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov); +@@ -5676,10 +7086,7 @@ + REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); + REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); + } +- bnx2x_init_block(bp, hc_limits[func][0], hc_limits[func][1]); +- +- if (CHIP_IS_E1H(bp)) +- REG_WR(bp, HC_REG_FUNC_NUM_P0 + port*4, func); ++ bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func); + + /* Reset PCIE errors for debug */ + REG_WR(bp, 0x2114, 0xffffffff); +@@ -5697,7 +7104,9 @@ + + bp->dmae_ready = 0; + mutex_init(&bp->dmae_mutex); +- bnx2x_gunzip_init(bp); ++ rc = bnx2x_gunzip_init(bp); ++ if (rc) ++ return rc; + + switch (load_code) { + case FW_MSG_CODE_DRV_LOAD_COMMON: +@@ -5731,57 +7140,19 @@ + bp->fw_drv_pulse_wr_seq = + (SHMEM_RD(bp, func_mb[func].drv_pulse_mb) & + DRV_PULSE_SEQ_MASK); +- bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param); +- DP(BNX2X_MSG_MCP, "drv_pulse 0x%x func_stx 0x%x\n", +- bp->fw_drv_pulse_wr_seq, bp->func_stx); +- } else +- bp->func_stx = 0; ++ DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq); ++ } + + /* this needs to be done before gunzip end */ + bnx2x_zero_def_sb(bp); + for_each_queue(bp, i) + bnx2x_zero_sb(bp, BP_L_ID(bp) + i); ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ bnx2x_zero_sb(bp, BP_L_ID(bp) + i); ++#endif + + init_hw_err: + bnx2x_gunzip_end(bp); +- +- return rc; +-} +- +-/* send the MCP a request, block until there is a reply */ +-static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command) +-{ +- int func = BP_FUNC(bp); +- u32 seq = ++bp->fw_seq; +- u32 rc = 0; +- u32 cnt = 1; +- u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; +- +- SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq)); +- DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq)); +- +- do { +- /* let the FW do it's magic ... */ +- msleep(delay); +- +- rc = SHMEM_RD(bp, func_mb[func].fw_mb_header); +- +- /* Give the FW up to 2 second (200*10ms) */ +- } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200)); +- +- DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", +- cnt*delay, rc, seq); +- +- /* is this a reply to our command? */ +- if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) { +- rc &= FW_MSG_CODE_MASK; +- +- } else { +- /* FW BUG! */ +- BNX2X_ERR("FW failed to respond!\n"); +- bnx2x_fw_dump(bp); +- rc = 0; +- } + + return rc; + } +@@ -5809,20 +7180,18 @@ + int i; + + /* fastpath */ ++ /* Common */ + for_each_queue(bp, i) { + +- /* Status blocks */ ++ /* status blocks */ + BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk), + bnx2x_fp(bp, i, status_blk_mapping), +- sizeof(struct host_status_block) + +- sizeof(struct eth_tx_db_data)); +- +- /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */ +- BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring)); +- BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring), +- bnx2x_fp(bp, i, tx_desc_mapping), +- sizeof(struct eth_tx_bd) * NUM_TX_BD); +- ++ sizeof(struct host_status_block)); ++ } ++ /* Rx */ ++ for_each_rx_queue(bp, i) { ++ ++ /* fastpath rx rings: rx_buf rx_desc rx_comp */ + BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring)); + BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring), + bnx2x_fp(bp, i, rx_desc_mapping), +@@ -5839,6 +7208,15 @@ + bnx2x_fp(bp, i, rx_sge_mapping), + BCM_PAGE_SIZE * NUM_RX_SGE_PAGES); + } ++ /* Tx */ ++ for_each_tx_queue(bp, i) { ++ ++ /* fastpath tx rings: tx_buf tx_desc */ ++ BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring)); ++ BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring), ++ bnx2x_fp(bp, i, tx_desc_mapping), ++ sizeof(union eth_tx_bd_types) * NUM_TX_BD); ++ } + /* end of fastpath */ + + BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, +@@ -5847,11 +7225,13 @@ + BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, + sizeof(struct bnx2x_slowpath)); + +-#ifdef BCM_ISCSI ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ + BNX2X_PCI_FREE(bp->t1, bp->t1_mapping, 64*1024); + BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, 16*1024); + BNX2X_PCI_FREE(bp->timers, bp->timers_mapping, 8*1024); + BNX2X_PCI_FREE(bp->qm, bp->qm_mapping, 128*1024); ++ BNX2X_PCI_FREE(bp->cnic_sb, bp->cnic_sb_mapping, ++ sizeof(struct host_status_block)); + #endif + BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); + +@@ -5881,29 +7261,19 @@ + int i; + + /* fastpath */ ++ /* Common */ + for_each_queue(bp, i) { + bnx2x_fp(bp, i, bp) = bp; + +- /* Status blocks */ ++ /* status blocks */ + BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk), + &bnx2x_fp(bp, i, status_blk_mapping), +- sizeof(struct host_status_block) + +- sizeof(struct eth_tx_db_data)); +- +- bnx2x_fp(bp, i, hw_tx_prods) = +- (void *)(bnx2x_fp(bp, i, status_blk) + 1); +- +- bnx2x_fp(bp, i, tx_prods_mapping) = +- bnx2x_fp(bp, i, status_blk_mapping) + +- sizeof(struct host_status_block); +- +- /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */ +- BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring), +- sizeof(struct sw_tx_bd) * NUM_TX_BD); +- BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring), +- &bnx2x_fp(bp, i, tx_desc_mapping), +- sizeof(struct eth_tx_bd) * NUM_TX_BD); +- ++ sizeof(struct host_status_block)); ++ } ++ /* Rx */ ++ for_each_rx_queue(bp, i) { ++ ++ /* fastpath rx rings: rx_buf rx_desc rx_comp */ + BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring), + sizeof(struct sw_rx_bd) * NUM_RX_BD); + BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring), +@@ -5922,6 +7292,16 @@ + &bnx2x_fp(bp, i, rx_sge_mapping), + BCM_PAGE_SIZE * NUM_RX_SGE_PAGES); + } ++ /* Tx */ ++ for_each_tx_queue(bp, i) { ++ ++ /* fastpath tx rings: tx_buf tx_desc */ ++ BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring), ++ sizeof(struct sw_tx_bd) * NUM_TX_BD); ++ BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring), ++ &bnx2x_fp(bp, i, tx_desc_mapping), ++ sizeof(union eth_tx_bd_types) * NUM_TX_BD); ++ } + /* end of fastpath */ + + BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, +@@ -5930,32 +7310,26 @@ + BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, + sizeof(struct bnx2x_slowpath)); + +-#ifdef BCM_ISCSI ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ + BNX2X_PCI_ALLOC(bp->t1, &bp->t1_mapping, 64*1024); +- +- /* Initialize T1 */ +- for (i = 0; i < 64*1024; i += 64) { +- *(u64 *)((char *)bp->t1 + i + 56) = 0x0UL; +- *(u64 *)((char *)bp->t1 + i + 3) = 0x0UL; +- } + + /* allocate searcher T2 table + we allocate 1/4 of alloc num for T2 + (which is not entered into the ILT) */ + BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, 16*1024); + +- /* Initialize T2 */ ++ /* Initialize T2 (for 1024 connections) */ + for (i = 0; i < 16*1024; i += 64) +- * (u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64; +- +- /* now fixup the last line in the block to point to the next block */ +- *(u64 *)((char *)bp->t2 + 1024*16-8) = bp->t2_mapping; +- +- /* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */ ++ *(u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64; ++ ++ /* Timer block array (8*MAX_CONN) phys uncached for now 1024 conns */ + BNX2X_PCI_ALLOC(bp->timers, &bp->timers_mapping, 8*1024); + + /* QM queues (128*MAX_CONN) */ + BNX2X_PCI_ALLOC(bp->qm, &bp->qm_mapping, 128*1024); ++ ++ BNX2X_PCI_ALLOC(bp->cnic_sb, &bp->cnic_sb_mapping, ++ sizeof(struct host_status_block)); + #endif + + /* Slow path ring */ +@@ -5975,7 +7349,7 @@ + { + int i; + +- for_each_queue(bp, i) { ++ for_each_tx_queue(bp, i) { + struct bnx2x_fastpath *fp = &bp->fp[i]; + + u16 bd_cons = fp->tx_bd_cons; +@@ -5993,7 +7367,7 @@ + { + int i, j; + +- for_each_queue(bp, j) { ++ for_each_rx_queue(bp, j) { + struct bnx2x_fastpath *fp = &bp->fp[j]; + + for (i = 0; i < NUM_RX_BD; i++) { +@@ -6005,8 +7379,7 @@ + + pci_unmap_single(bp->pdev, + pci_unmap_addr(rx_buf, mapping), +- bp->rx_buf_size, +- PCI_DMA_FROMDEVICE); ++ bp->rx_buf_size, PCI_DMA_FROMDEVICE); + + rx_buf->skb = NULL; + dev_kfree_skb(skb); +@@ -6024,6 +7397,7 @@ + bnx2x_free_rx_skbs(bp); + } + ++#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */ + static void bnx2x_free_msix_irqs(struct bnx2x *bp) + { + int i, offset = 1; +@@ -6032,57 +7406,75 @@ + DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n", + bp->msix_table[0].vector); + ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ offset++; ++#endif + for_each_queue(bp, i) { + DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq " + "state %x\n", i, bp->msix_table[i + offset].vector, + bnx2x_fp(bp, i, state)); + +- if (bnx2x_fp(bp, i, state) != BNX2X_FP_STATE_CLOSED) +- BNX2X_ERR("IRQ of fp #%d being freed while " +- "state != closed\n", i); +- + free_irq(bp->msix_table[i + offset].vector, &bp->fp[i]); + } + } ++#endif + + static void bnx2x_free_irq(struct bnx2x *bp) + { ++#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */ + if (bp->flags & USING_MSIX_FLAG) { + bnx2x_free_msix_irqs(bp); + pci_disable_msix(bp->pdev); + bp->flags &= ~USING_MSIX_FLAG; + ++ } else if (bp->flags & USING_MSI_FLAG) { ++ free_irq(bp->pdev->irq, bp->dev); ++ pci_disable_msi(bp->pdev); ++ bp->flags &= ~USING_MSI_FLAG; ++ + } else ++#endif + free_irq(bp->pdev->irq, bp->dev); + } + + static int bnx2x_enable_msix(struct bnx2x *bp) + { +- int i, rc, offset; +- +- bp->msix_table[0].entry = 0; +- offset = 1; +- DP(NETIF_MSG_IFUP, "msix_table[0].entry = 0 (slowpath)\n"); +- ++#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */ ++ int i, rc, offset = 1; ++ int igu_vec = 0; ++ ++ bp->msix_table[0].entry = igu_vec; ++ DP(NETIF_MSG_IFUP, "msix_table[0].entry = %d (slowpath)\n", igu_vec); ++ ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ igu_vec = BP_L_ID(bp) + offset; ++ bp->msix_table[1].entry = igu_vec; ++ DP(NETIF_MSG_IFUP, "msix_table[1].entry = %d (CNIC)\n", igu_vec); ++ offset++; ++#endif + for_each_queue(bp, i) { +- int igu_vec = offset + i + BP_L_ID(bp); +- ++ igu_vec = BP_L_ID(bp) + offset + i; + bp->msix_table[i + offset].entry = igu_vec; + DP(NETIF_MSG_IFUP, "msix_table[%d].entry = %d " + "(fastpath #%u)\n", i + offset, igu_vec, i); + } + + rc = pci_enable_msix(bp->pdev, &bp->msix_table[0], +- bp->num_queues + offset); ++ BNX2X_NUM_QUEUES(bp) + offset); + if (rc) { +- DP(NETIF_MSG_IFUP, "MSI-X is not attainable\n"); +- return -1; +- } ++ DP(NETIF_MSG_IFUP, "MSI-X is not attainable rc %d\n", rc); ++ return rc; ++ } ++ + bp->flags |= USING_MSIX_FLAG; + + return 0; +-} +- ++#else ++ return -1; ++#endif ++} ++ ++#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */ + static int bnx2x_req_msix_irqs(struct bnx2x *bp) + { + int i, rc, offset = 1; +@@ -6094,28 +7486,65 @@ + return -EBUSY; + } + ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ offset++; ++#endif + for_each_queue(bp, i) { ++ struct bnx2x_fastpath *fp = &bp->fp[i]; ++ ++ if (i < bp->num_rx_queues) ++ sprintf(fp->name, "%s-rx-%d", bp->dev->name, i); ++ else ++ sprintf(fp->name, "%s-tx-%d", ++ bp->dev->name, i - bp->num_rx_queues); ++ + rc = request_irq(bp->msix_table[i + offset].vector, +- bnx2x_msix_fp_int, 0, +- bp->dev->name, &bp->fp[i]); ++ bnx2x_msix_fp_int, 0, fp->name, fp); + if (rc) { +- BNX2X_ERR("request fp #%d irq failed rc -%d\n", +- i + offset, -rc); ++ BNX2X_ERR("request fp #%d irq failed rc %d\n", i, rc); + bnx2x_free_msix_irqs(bp); + return -EBUSY; + } + +- bnx2x_fp(bp, i, state) = BNX2X_FP_STATE_IRQ; +- } +- +- return 0; +-} ++ fp->state = BNX2X_FP_STATE_IRQ; ++ } ++ ++ i = BNX2X_NUM_QUEUES(bp); ++ printk(KERN_INFO PFX "%s: using MSI-X IRQs: sp %d fp[%d] %d" ++ " ... fp[%d] %d\n", ++ bp->dev->name, bp->msix_table[0].vector, ++ 0, bp->msix_table[offset].vector, ++ i - 1, bp->msix_table[offset + i - 1].vector); ++ ++ return 0; ++} ++ ++static int bnx2x_enable_msi(struct bnx2x *bp) ++{ ++ int rc; ++ ++ rc = pci_enable_msi(bp->pdev); ++ if (rc) { ++ DP(NETIF_MSG_IFUP, "MSI is not attainable\n"); ++ return -1; ++ } ++ bp->flags |= USING_MSI_FLAG; ++ ++ return 0; ++} ++#endif + + static int bnx2x_req_irq(struct bnx2x *bp) + { +- int rc; +- +- rc = request_irq(bp->pdev->irq, bnx2x_interrupt, IRQF_SHARED, ++ unsigned long flags; ++ int rc; ++ ++ if (bp->flags & USING_MSI_FLAG) ++ flags = 0; ++ else ++ flags = IRQF_SHARED; ++ ++ rc = request_irq(bp->pdev->irq, bnx2x_interrupt, flags, + bp->dev->name, bp->dev); + if (!rc) + bnx2x_fp(bp, 0, state) = BNX2X_FP_STATE_IRQ; +@@ -6125,28 +7554,41 @@ + + static void bnx2x_napi_enable(struct bnx2x *bp) + { +- int i; +- +- for_each_queue(bp, i) ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ ++ int i; ++ ++ for_each_rx_queue(bp, i) + napi_enable(&bnx2x_fp(bp, i, napi)); ++#else ++ netif_poll_enable(bp->dev); ++#endif + } + + static void bnx2x_napi_disable(struct bnx2x *bp) + { +- int i; +- +- for_each_queue(bp, i) ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ ++ int i; ++ ++ for_each_rx_queue(bp, i) + napi_disable(&bnx2x_fp(bp, i, napi)); ++#else ++ netif_poll_disable(bp->dev); ++#endif + } + + static void bnx2x_netif_start(struct bnx2x *bp) + { +- if (atomic_dec_and_test(&bp->intr_sem)) { ++ int intr_sem; ++ ++ intr_sem = atomic_dec_and_test(&bp->intr_sem); ++ smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */ ++ ++ if (intr_sem) { + if (netif_running(bp->dev)) { +- if (bp->state == BNX2X_STATE_OPEN) +- netif_wake_queue(bp->dev); + bnx2x_napi_enable(bp); + bnx2x_int_enable(bp); ++ if (bp->state == BNX2X_STATE_OPEN) ++ netif_tx_wake_all_queues(bp->dev); + } + } + } +@@ -6154,11 +7596,14 @@ + static void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw) + { + bnx2x_int_disable_sync(bp, disable_hw); ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ + bnx2x_napi_disable(bp); +- if (netif_running(bp->dev)) { +- netif_tx_disable(bp->dev); +- bp->dev->trans_start = jiffies; /* prevent tx timeout */ +- } ++#else ++ if (netif_running(bp->dev)) ++ bnx2x_napi_disable(bp); ++#endif ++ netif_tx_disable(bp->dev); ++ bp->dev->trans_start = jiffies; /* prevent tx timeout */ + } + + /* +@@ -6174,9 +7619,9 @@ + * unicasts 0-31:port0 32-63:port1 + * multicast 64-127:port0 128-191:port1 + */ +- config->hdr.length_6b = 2; ++ config->hdr.length = 2; + config->hdr.offset = port ? 32 : 0; +- config->hdr.client_id = BP_CL_ID(bp); ++ config->hdr.client_id = bp->fp->cl_id; + config->hdr.reserved1 = 0; + + /* primary MAC */ +@@ -6191,7 +7636,8 @@ + config->config_table[0].target_table_entry.flags = 0; + else + CAM_INVALIDATE(config->config_table[0]); +- config->config_table[0].target_table_entry.client_id = 0; ++ config->config_table[0].target_table_entry.clients_bit_vector = ++ cpu_to_le32(1 << BP_L_ID(bp)); + config->config_table[0].target_table_entry.vlan_id = 0; + + DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n", +@@ -6201,16 +7647,17 @@ + config->config_table[0].cam_entry.lsb_mac_addr); + + /* broadcast */ +- config->config_table[1].cam_entry.msb_mac_addr = 0xffff; +- config->config_table[1].cam_entry.middle_mac_addr = 0xffff; +- config->config_table[1].cam_entry.lsb_mac_addr = 0xffff; ++ config->config_table[1].cam_entry.msb_mac_addr = cpu_to_le16(0xffff); ++ config->config_table[1].cam_entry.middle_mac_addr = cpu_to_le16(0xffff); ++ config->config_table[1].cam_entry.lsb_mac_addr = cpu_to_le16(0xffff); + config->config_table[1].cam_entry.flags = cpu_to_le16(port); + if (set) + config->config_table[1].target_table_entry.flags = + TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST; + else + CAM_INVALIDATE(config->config_table[1]); +- config->config_table[1].target_table_entry.client_id = 0; ++ config->config_table[1].target_table_entry.clients_bit_vector = ++ cpu_to_le32(1 << BP_L_ID(bp)); + config->config_table[1].target_table_entry.vlan_id = 0; + + bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, +@@ -6222,19 +7669,14 @@ + { + struct mac_configuration_cmd_e1h *config = + (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config); +- +- if (set && (bp->state != BNX2X_STATE_OPEN)) { +- DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); +- return; +- } + + /* CAM allocation for E1H + * unicasts: by func number + * multicast: 20+FUNC*20, 20 each + */ +- config->hdr.length_6b = 1; ++ config->hdr.length = 1; + config->hdr.offset = BP_FUNC(bp); +- config->hdr.client_id = BP_CL_ID(bp); ++ config->hdr.client_id = bp->fp->cl_id; + config->hdr.reserved1 = 0; + + /* primary MAC */ +@@ -6244,7 +7686,8 @@ + swab16(*(u16 *)&bp->dev->dev_addr[2]); + config->config_table[0].lsb_mac_addr = + swab16(*(u16 *)&bp->dev->dev_addr[4]); +- config->config_table[0].client_id = BP_L_ID(bp); ++ config->config_table[0].clients_bit_vector = ++ cpu_to_le32(1 << BP_L_ID(bp)); + config->config_table[0].vlan_id = 0; + config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov); + if (set) +@@ -6268,7 +7711,7 @@ + int *state_p, int poll) + { + /* can take a while if any port is running */ +- int cnt = 500; ++ int cnt = 5000; + + DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n", + poll ? "polling" : "waiting", state, idx); +@@ -6286,10 +7729,17 @@ + } + + mb(); /* state is changed by bnx2x_sp_event() */ +- if (*state_p == state) ++ if (*state_p == state) { ++#ifdef BNX2X_STOP_ON_ERROR ++ DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt); ++#endif + return 0; ++ } + + msleep(1); ++ ++ if (bp->panic) ++ return -EIO; + } + + /* timeout! */ +@@ -6320,49 +7770,115 @@ + + static int bnx2x_setup_multi(struct bnx2x *bp, int index) + { ++ struct bnx2x_fastpath *fp = &bp->fp[index]; ++ + /* reset IGU state */ +- bnx2x_ack_sb(bp, bp->fp[index].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0); ++ bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0); + + /* SETUP ramrod */ +- bp->fp[index].state = BNX2X_FP_STATE_OPENING; +- bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0, index, 0); ++ fp->state = BNX2X_FP_STATE_OPENING; ++ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0, ++ fp->cl_id, 0); + + /* Wait for completion */ + return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index, +- &(bp->fp[index].state), 0); +-} +- ++ &(fp->state), 0); ++} ++ ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ + static int bnx2x_poll(struct napi_struct *napi, int budget); +-static void bnx2x_set_rx_mode(struct net_device *dev); +- +-/* must be called with rtnl_lock */ +-static int bnx2x_nic_load(struct bnx2x *bp, int load_mode) +-{ +- u32 load_code; +- int i, rc = 0; +-#ifdef BNX2X_STOP_ON_ERROR +- if (unlikely(bp->panic)) +- return -EPERM; +-#endif +- +- bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD; +- +- if (use_inta) { +- bp->num_queues = 1; +- +- } else { +- if ((use_multi > 1) && (use_multi <= BP_MAX_QUEUES(bp))) +- /* user requested number */ +- bp->num_queues = use_multi; +- +- else if (use_multi) +- bp->num_queues = min_t(u32, num_online_cpus(), +- BP_MAX_QUEUES(bp)); +- else +- bp->num_queues = 1; +- +- DP(NETIF_MSG_IFUP, +- "set number of queues to %d\n", bp->num_queues); ++#else ++static int bnx2x_poll(struct net_device *dev, int *budget); ++#endif ++ ++static void bnx2x_set_int_mode_msix(struct bnx2x *bp, int *num_rx_queues_out, ++ int *num_tx_queues_out) ++{ ++ int _num_rx_queues = 0, _num_tx_queues = 0; ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ int i; ++#endif ++ ++ switch (bp->multi_mode) { ++ case ETH_RSS_MODE_DISABLED: ++ _num_rx_queues = 1; ++ _num_tx_queues = 1; ++ break; ++ ++ case ETH_RSS_MODE_REGULAR: ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ ++ if (num_rx_queues) ++ _num_rx_queues = min_t(u32, num_rx_queues, ++ BNX2X_MAX_QUEUES(bp)); ++ else ++ _num_rx_queues = min_t(u32, num_online_cpus(), ++ BNX2X_MAX_QUEUES(bp)); ++#else ++ _num_rx_queues = 1; ++#endif ++ ++#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */ ++ if (num_tx_queues) ++ _num_tx_queues = min_t(u32, num_tx_queues, ++ BNX2X_MAX_QUEUES(bp)); ++ else ++ _num_tx_queues = min_t(u32, num_online_cpus(), ++ BNX2X_MAX_QUEUES(bp)); ++ ++ /* There must be not more Tx queues than Rx queues */ ++ if (_num_tx_queues > _num_rx_queues) { ++ BNX2X_ERR("number of tx queues (%d) > " ++ "number of rx queues (%d)" ++ " defaulting to %d\n", ++ _num_tx_queues, _num_rx_queues, ++ _num_rx_queues); ++ _num_tx_queues = _num_rx_queues; ++ } ++#else ++ _num_tx_queues = 1; ++#endif ++ break; ++ ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ case ETH_RSS_MODE_VLAN_PRI: ++ case ETH_RSS_MODE_E1HOV_PRI: ++ case ETH_RSS_MODE_IP_DSCP: ++ _num_rx_queues = 0; ++ for (i = 0; i < BNX2X_MAX_COS; i++) ++ _num_rx_queues += bp->qs_per_cos[i]; ++ _num_tx_queues = _num_rx_queues; ++ break; ++#endif ++ ++ default: ++ _num_rx_queues = 1; ++ _num_tx_queues = 1; ++ break; ++ } ++ ++ *num_rx_queues_out = _num_rx_queues; ++ *num_tx_queues_out = _num_tx_queues; ++} ++ ++static int bnx2x_set_int_mode(struct bnx2x *bp) ++{ ++ int rc = 0; ++ ++ switch (int_mode) { ++ case INT_MODE_INTx: ++ case INT_MODE_MSI: ++ bp->num_rx_queues = 1; ++ bp->num_tx_queues = 1; ++ DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); ++ break; ++ ++ case INT_MODE_MSIX: ++ default: ++ /* Set interrupt mode according to bp->multi_mode value */ ++ bnx2x_set_int_mode_msix(bp, &bp->num_rx_queues, &bp->num_tx_queues); ++ ++ DP(NETIF_MSG_IFUP, "set number of queues to: rx %d tx %d\n", ++ bp->num_rx_queues, bp->num_tx_queues); + + /* if we can't use MSI-X we only need one fp, + * so try to enable MSI-X with the requested number of fp's +@@ -6371,50 +7887,86 @@ + rc = bnx2x_enable_msix(bp); + if (rc) { + /* failed to enable MSI-X */ +- bp->num_queues = 1; +- if (use_multi) +- BNX2X_ERR("Multi requested but failed" +- " to enable MSI-X\n"); +- } +- } ++ if (bp->multi_mode) ++ BNX2X_ERR("Multi requested but failed to " ++ "enable MSI-X (rx %d tx %d), " ++ "set number of queues to 1\n", ++ bp->num_rx_queues, bp->num_tx_queues); ++ bp->num_rx_queues = 1; ++ bp->num_tx_queues = 1; ++ } ++ break; ++ } ++#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */ ++ bp->dev->real_num_tx_queues = bp->num_tx_queues; ++#endif ++ return rc; ++} ++ ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++static int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); ++static void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); ++#endif ++ ++/* must be called with rtnl_lock */ ++static int bnx2x_nic_load(struct bnx2x *bp, int load_mode) ++{ ++ u32 load_code; ++ int i, rc; ++ ++#ifdef BNX2X_STOP_ON_ERROR ++ if (unlikely(bp->panic)) ++ return -EPERM; ++#endif ++ ++ bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD; ++ ++ rc = bnx2x_set_int_mode(bp); + + if (bnx2x_alloc_mem(bp)) + return -ENOMEM; + +- for_each_queue(bp, i) ++ for_each_rx_queue(bp, i) + bnx2x_fp(bp, i, disable_tpa) = + ((bp->flags & TPA_ENABLE_FLAG) == 0); + +- for_each_queue(bp, i) ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ ++ for_each_rx_queue(bp, i) + netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), + bnx2x_poll, 128); +- +-#ifdef BNX2X_STOP_ON_ERROR +- for_each_queue(bp, i) { +- struct bnx2x_fastpath *fp = &bp->fp[i]; +- +- fp->poll_no_work = 0; +- fp->poll_calls = 0; +- fp->poll_max_calls = 0; +- fp->poll_complete = 0; +- fp->poll_exit = 0; +- } +-#endif ++#endif ++ + bnx2x_napi_enable(bp); + ++#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */ + if (bp->flags & USING_MSIX_FLAG) { + rc = bnx2x_req_msix_irqs(bp); + if (rc) { + pci_disable_msix(bp->pdev); + goto load_error1; + } +- printk(KERN_INFO PFX "%s: using MSI-X\n", bp->dev->name); +- } else { ++ } else { ++ /* Fall to INTx if failed to enable MSI-X due to lack of ++ memory (in bnx2x_set_int_mode()) */ ++ if ((rc != -ENOMEM) && (int_mode != INT_MODE_INTx)) ++ bnx2x_enable_msi(bp); ++#else ++ { ++#endif + bnx2x_ack_int(bp); + rc = bnx2x_req_irq(bp); + if (rc) { + BNX2X_ERR("IRQ request failed rc %d, aborting\n", rc); ++#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */ ++ if (bp->flags & USING_MSI_FLAG) ++ pci_disable_msi(bp->pdev); ++#endif + goto load_error1; ++ } ++ if (bp->flags & USING_MSI_FLAG) { ++ bp->dev->irq = bp->pdev->irq; ++ printk(KERN_INFO PFX "%s: using MSI IRQ %d\n", ++ bp->dev->name, bp->pdev->irq); + } + } + +@@ -6438,11 +7990,11 @@ + } else { + int port = BP_PORT(bp); + +- DP(NETIF_MSG_IFUP, "NO MCP load counts before us %d, %d, %d\n", ++ DP(NETIF_MSG_IFUP, "NO MCP - load counts %d, %d, %d\n", + load_count[0], load_count[1], load_count[2]); + load_count[0]++; + load_count[1 + port]++; +- DP(NETIF_MSG_IFUP, "NO MCP new load counts %d, %d, %d\n", ++ DP(NETIF_MSG_IFUP, "NO MCP - new load counts %d, %d, %d\n", + load_count[0], load_count[1], load_count[2]); + if (load_count[0] == 1) + load_code = FW_MSG_CODE_DRV_LOAD_COMMON; +@@ -6468,6 +8020,12 @@ + + /* Setup NIC internals and enable interrupts */ + bnx2x_nic_init(bp, load_code); ++ ++ if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) && ++ (bp->common.shmem2_base)) ++ SHMEM2_WR(bp, dcc_support, ++ (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV | ++ SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV)); + + /* Send LOAD_DONE command to MCP */ + if (!BP_NOMCP(bp)) { +@@ -6484,41 +8042,59 @@ + rc = bnx2x_setup_leading(bp); + if (rc) { + BNX2X_ERR("Setup leading failed!\n"); ++#ifndef BNX2X_STOP_ON_ERROR + goto load_error3; ++#else ++ bp->panic = 1; ++ return -EBUSY; ++#endif + } + + if (CHIP_IS_E1H(bp)) + if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) { +- BNX2X_ERR("!!! mf_cfg function disabled\n"); ++ DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); + bp->state = BNX2X_STATE_DISABLED; + } + +- if (bp->state == BNX2X_STATE_OPEN) ++ if (bp->state == BNX2X_STATE_OPEN) { ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ /* Enable Timer scan */ ++ REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + BP_PORT(bp)*4, 1); ++#endif + for_each_nondefault_queue(bp, i) { + rc = bnx2x_setup_multi(bp, i); + if (rc) ++#ifdef BCM_CNIC ++ goto load_error4; ++#else /* BNX2X_UPSTREAM */ + goto load_error3; +- } +- +- if (CHIP_IS_E1(bp)) +- bnx2x_set_mac_addr_e1(bp, 1); +- else +- bnx2x_set_mac_addr_e1h(bp, 1); ++#endif ++ } ++ ++ if (CHIP_IS_E1(bp)) ++ bnx2x_set_mac_addr_e1(bp, 1); ++ else ++ bnx2x_set_mac_addr_e1h(bp, 1); ++ } + + if (bp->port.pmf) +- bnx2x_initial_phy_init(bp); ++ bnx2x_initial_phy_init(bp, load_mode); + + /* Start fast path */ + switch (load_mode) { + case LOAD_NORMAL: +- /* Tx queue should be only reenabled */ +- netif_wake_queue(bp->dev); ++ if (bp->state == BNX2X_STATE_OPEN) { ++ /* Tx queue should be only reenabled */ ++ netif_tx_wake_all_queues(bp->dev); ++ } + /* Initialize the receive filter. */ + bnx2x_set_rx_mode(bp->dev); + break; + + case LOAD_OPEN: +- netif_start_queue(bp->dev); ++ netif_tx_start_all_queues(bp->dev); ++ if (bp->state != BNX2X_STATE_OPEN) ++ netif_tx_disable(bp->dev); + /* Initialize the receive filter. */ + bnx2x_set_rx_mode(bp->dev); + break; +@@ -6539,9 +8115,34 @@ + /* start the timer */ + mod_timer(&bp->timer, jiffies + bp->current_interval); + +- +- return 0; +- ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */ ++ for_each_queue(bp, i) { ++ struct bnx2x_fastpath *fp = &bp->fp[i]; ++ ++ fp->netq_flags &= ~(BNX2X_NETQ_RX_QUEUE_ALLOCATED | ++ BNX2X_NETQ_TX_QUEUE_ALLOCATED); ++ } ++ bp->n_rx_queues_allocated = 0; ++ bp->n_tx_queues_allocated = 0; ++ if (bp->netq_enabled) { ++ /* workaround for packets duplicated issue when NetQ enabled */ ++ bp->rx_mode = BNX2X_RX_MODE_NORMAL; ++ bnx2x_set_storm_rx_mode(bp); ++ } ++#endif ++ ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ bnx2x_setup_cnic_irq_info(bp); ++ if (bp->state == BNX2X_STATE_OPEN) ++ bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD); ++#endif ++ return 0; ++ ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++load_error4: ++ /* Disable Timer scan */ ++ REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + BP_PORT(bp)*4, 0); ++#endif + load_error3: + bnx2x_int_disable_sync(bp, 1); + if (!BP_NOMCP(bp)) { +@@ -6551,33 +8152,34 @@ + bp->port.pmf = 0; + /* Free SKBs, SGEs, TPA pool and driver internals */ + bnx2x_free_skbs(bp); +- for_each_queue(bp, i) ++ for_each_rx_queue(bp, i) + bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); + load_error2: + /* Release IRQs */ + bnx2x_free_irq(bp); + load_error1: + bnx2x_napi_disable(bp); +- for_each_queue(bp, i) ++#if defined(BNX2X_NEW_NAPI) && (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */ ++ for_each_rx_queue(bp, i) + netif_napi_del(&bnx2x_fp(bp, i, napi)); ++#endif + bnx2x_free_mem(bp); + +- /* TBD we really need to reset the chip +- if we want to recover from this */ + return rc; + } + + static int bnx2x_stop_multi(struct bnx2x *bp, int index) + { ++ struct bnx2x_fastpath *fp = &bp->fp[index]; + int rc; + + /* halt the connection */ +- bp->fp[index].state = BNX2X_FP_STATE_HALTING; +- bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, index, 0); ++ fp->state = BNX2X_FP_STATE_HALTING; ++ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, fp->cl_id, 0); + + /* Wait for completion */ + rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index, +- &(bp->fp[index].state), 1); ++ &(fp->state), 1); + if (rc) /* timeout */ + return rc; + +@@ -6586,13 +8188,13 @@ + + /* Wait for completion */ + rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, index, +- &(bp->fp[index].state), 1); ++ &(fp->state), 1); + return rc; + } + + static int bnx2x_stop_leading(struct bnx2x *bp) + { +- u16 dsb_sp_prod_idx; ++ __le16 dsb_sp_prod_idx; + /* if the other port is handling traffic, + this can take a lot of time */ + int cnt = 500; +@@ -6602,7 +8204,7 @@ + + /* Send HALT ramrod */ + bp->fp[0].state = BNX2X_FP_STATE_HALTING; +- bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, BP_CL_ID(bp), 0); ++ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, bp->fp->cl_id, 0); + + /* Wait for completion */ + rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0, +@@ -6621,14 +8223,13 @@ + */ + while (dsb_sp_prod_idx == *bp->dsb_sp_prod) { + if (!cnt) { +- DP(NETIF_MSG_IFDOWN, "timeout waiting for port del " ++ DP(NETIF_MSG_IFDOWN, "timeout waiting for port del " + "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n", + *bp->dsb_sp_prod, dsb_sp_prod_idx); + #ifdef BNX2X_STOP_ON_ERROR + bnx2x_panic(); +-#else ++#endif + rc = -EBUSY; +-#endif + break; + } + cnt--; +@@ -6651,8 +8252,19 @@ + REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); + REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); + +- REG_WR(bp, HC_REG_CONFIG_0 + port*4, 0x1000); +- ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ /* Disable Timer scan */ ++ REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); ++ /* ++ * Wait for at least 10ms and up to 2 second for the timers scan to ++ * complete ++ */ ++ for (i = 0; i < 200; i++) { ++ msleep(10); ++ if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) ++ break; ++ } ++#endif + /* Clear ILT */ + base = FUNC_ILT_BASE(func); + for (i = base; i < base + ILT_PER_FUNC; i++) +@@ -6719,11 +8331,16 @@ + u32 reset_code = 0; + int i, cnt, rc; + ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); ++#endif + bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; + ++ /* Set "drop all" */ + bp->rx_mode = BNX2X_RX_MODE_NONE; + bnx2x_set_storm_rx_mode(bp); + ++ /* Disable HW interrupts, NAPI and Tx */ + bnx2x_netif_stop(bp, 1); + + del_timer_sync(&bp->timer); +@@ -6734,15 +8351,14 @@ + /* Release IRQs */ + bnx2x_free_irq(bp); + +- /* Wait until tx fast path tasks complete */ +- for_each_queue(bp, i) { ++ /* Wait until tx fastpath tasks complete */ ++ for_each_tx_queue(bp, i) { + struct bnx2x_fastpath *fp = &bp->fp[i]; + + cnt = 1000; +- smp_rmb(); + while (bnx2x_has_tx_work_unload(fp)) { + +- bnx2x_tx_int(fp, 1000); ++ bnx2x_tx_int(fp); + if (!cnt) { + BNX2X_ERR("timeout waiting for queue[%d]\n", + i); +@@ -6755,7 +8371,6 @@ + } + cnt--; + msleep(1); +- smp_rmb(); + } + } + /* Give HW time to discard old tx messages */ +@@ -6767,15 +8382,15 @@ + + bnx2x_set_mac_addr_e1(bp, 0); + +- for (i = 0; i < config->hdr.length_6b; i++) ++ for (i = 0; i < config->hdr.length; i++) + CAM_INVALIDATE(config->config_table[i]); + +- config->hdr.length_6b = i; ++ config->hdr.length = i; + if (CHIP_REV_IS_SLOW(bp)) + config->hdr.offset = BNX2X_MAX_EMUL_MULTI*(1 + port); + else + config->hdr.offset = BNX2X_MAX_MULTICAST*(1 + port); +- config->hdr.client_id = BP_CL_ID(bp); ++ config->hdr.client_id = bp->fp->cl_id; + config->hdr.reserved1 = 0; + + bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, +@@ -6789,17 +8404,17 @@ + + for (i = 0; i < MC_HASH_SIZE; i++) + REG_WR(bp, MC_HASH_OFFSET(bp, i), 0); ++ ++ REG_WR(bp, MISC_REG_E1HMF_MODE, 0); + } + + if (unload_mode == UNLOAD_NORMAL) + reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; + +- else if (bp->flags & NO_WOL_FLAG) { ++ else if (bp->flags & NO_WOL_FLAG) + reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; +- if (CHIP_IS_E1H(bp)) +- REG_WR(bp, MISC_REG_E1HMF_MODE, 0); +- +- } else if (bp->wol) { ++ ++ else if (bp->wol) { + u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; + u8 *mac_addr = bp->dev->dev_addr; + u32 val; +@@ -6839,11 +8454,11 @@ + if (!BP_NOMCP(bp)) + reset_code = bnx2x_fw_command(bp, reset_code); + else { +- DP(NETIF_MSG_IFDOWN, "NO MCP load counts %d, %d, %d\n", ++ DP(NETIF_MSG_IFDOWN, "NO MCP - load counts %d, %d, %d\n", + load_count[0], load_count[1], load_count[2]); + load_count[0]--; + load_count[1 + port]--; +- DP(NETIF_MSG_IFDOWN, "NO MCP new load counts %d, %d, %d\n", ++ DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts %d, %d, %d\n", + load_count[0], load_count[1], load_count[2]); + if (load_count[0] == 0) + reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; +@@ -6863,14 +8478,17 @@ + /* Report UNLOAD_DONE to MCP */ + if (!BP_NOMCP(bp)) + bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE); ++ + bp->port.pmf = 0; + + /* Free SKBs, SGEs, TPA pool and driver internals */ + bnx2x_free_skbs(bp); +- for_each_queue(bp, i) ++ for_each_rx_queue(bp, i) + bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); +- for_each_queue(bp, i) ++#if defined(BNX2X_NEW_NAPI) && (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */ ++ for_each_rx_queue(bp, i) + netif_napi_del(&bnx2x_fp(bp, i, napi)); ++#endif + bnx2x_free_mem(bp); + + bp->state = BNX2X_STATE_CLOSED; +@@ -6880,9 +8498,15 @@ + return 0; + } + ++#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) || (VMWARE_ESX_DDK_VERSION >= 40000) /* BNX2X_UPSTREAM */ + static void bnx2x_reset_task(struct work_struct *work) + { + struct bnx2x *bp = container_of(work, struct bnx2x, reset_task); ++#else ++static void bnx2x_reset_task(void *data) ++{ ++ struct bnx2x *bp = (struct bnx2x *)data; ++#endif + + #ifdef BNX2X_STOP_ON_ERROR + BNX2X_ERR("reset task called but STOP_ON_ERROR defined" +@@ -6910,6 +8534,64 @@ + /* + * Init service functions + */ ++ ++static inline u32 bnx2x_get_pretend_reg(struct bnx2x *bp, int func) ++{ ++ switch (func) { ++ case 0: return PXP2_REG_PGL_PRETEND_FUNC_F0; ++ case 1: return PXP2_REG_PGL_PRETEND_FUNC_F1; ++ case 2: return PXP2_REG_PGL_PRETEND_FUNC_F2; ++ case 3: return PXP2_REG_PGL_PRETEND_FUNC_F3; ++ case 4: return PXP2_REG_PGL_PRETEND_FUNC_F4; ++ case 5: return PXP2_REG_PGL_PRETEND_FUNC_F5; ++ case 6: return PXP2_REG_PGL_PRETEND_FUNC_F6; ++ case 7: return PXP2_REG_PGL_PRETEND_FUNC_F7; ++ default: ++ BNX2X_ERR("Unsupported function index: %d\n", func); ++ return (u32)(-1); ++ } ++} ++ ++static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp, int orig_func) ++{ ++ u32 reg = bnx2x_get_pretend_reg(bp, orig_func), new_val; ++ ++ /* Flush all outstanding writes */ ++ mmiowb(); ++ ++ /* Pretend to be function 0 */ ++ REG_WR(bp, reg, 0); ++ /* Flush the GRC transaction (in the chip) */ ++ new_val = REG_RD(bp, reg); ++ if (new_val != 0) { ++ BNX2X_ERR("Hmmm... Pretend register wasn't updated: (0,%d)!\n", ++ new_val); ++ BUG(); ++ } ++ ++ /* From now we are in the "like-E1" mode */ ++ bnx2x_int_disable(bp); ++ ++ /* Flush all outstanding writes */ ++ mmiowb(); ++ ++ /* Restore the original funtion settings */ ++ REG_WR(bp, reg, orig_func); ++ new_val = REG_RD(bp, reg); ++ if (new_val != orig_func) { ++ BNX2X_ERR("Hmmm... Pretend register wasn't updated: (%d,%d)!\n", ++ orig_func, new_val); ++ BUG(); ++ } ++} ++ ++static inline void bnx2x_undi_int_disable(struct bnx2x *bp, int func) ++{ ++ if (CHIP_IS_E1H(bp)) ++ bnx2x_undi_int_disable_e1h(bp, func); ++ else ++ bnx2x_int_disable(bp); ++} + + static void __devinit bnx2x_undi_unload(struct bnx2x *bp) + { +@@ -6961,8 +8643,7 @@ + /* now it's safe to release the lock */ + bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); + +- REG_WR(bp, (BP_PORT(bp) ? HC_REG_CONFIG_1 : +- HC_REG_CONFIG_0), 0x1000); ++ bnx2x_undi_int_disable(bp, func); + + /* close input traffic and wait for it */ + /* Do not rcv packets to BRB */ +@@ -7030,6 +8711,13 @@ + bp->link_params.chip_id = bp->common.chip_id; + BNX2X_DEV_INFO("chip ID is 0x%x\n", id); + ++ val = (REG_RD(bp, 0x2874) & 0x55); ++ if ((bp->common.chip_id & 0x1) || ++ (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { ++ bp->flags |= ONE_PORT_FLAG; ++ BNX2X_DEV_INFO("single port device\n"); ++ } ++ + val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); + bp->common.flash_size = (NVRAM_1MB_SIZE << + (val & MCPR_NVM_CFG4_FLASH_SIZE)); +@@ -7037,8 +8725,10 @@ + bp->common.flash_size, bp->common.flash_size); + + bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); ++ bp->common.shmem2_base = REG_RD(bp, MISC_REG_GENERIC_CR_0); + bp->link_params.shmem_base = bp->common.shmem_base; +- BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base); ++ BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", ++ bp->common.shmem_base, bp->common.shmem2_base); + + if (!bp->common.shmem_base || + (bp->common.shmem_base < 0xA0000) || +@@ -7054,14 +8744,20 @@ + BNX2X_ERR("BAD MCP validity signature\n"); + + bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); +- bp->common.board = SHMEM_RD(bp, dev_info.shared_hw_config.board); +- +- BNX2X_DEV_INFO("hw_config 0x%08x board 0x%08x\n", +- bp->common.hw_config, bp->common.board); ++ BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); + + bp->link_params.hw_led_mode = ((bp->common.hw_config & + SHARED_HW_CFG_LED_MODE_MASK) >> + SHARED_HW_CFG_LED_MODE_SHIFT); ++ ++ bp->link_params.feature_config_flags = 0; ++ val = SHMEM_RD(bp, dev_info.shared_feature_config.config); ++ if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) ++ bp->link_params.feature_config_flags |= ++ FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; ++ else ++ bp->link_params.feature_config_flags &= ++ ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; + + val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; + bp->common.bc_ver = val; +@@ -7072,6 +8768,9 @@ + BNX2X_ERR("This driver needs bc_ver %X but found %X," + " please upgrade BC\n", BNX2X_BC_VER, val); + } ++ bp->link_params.feature_config_flags |= ++ (val >= REQ_BC_VER_4_VRFY_OPT_MDL) ? ++ FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; + + if (BP_E1HVN(bp) == 0) { + pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); +@@ -7081,7 +8780,7 @@ + bp->flags |= NO_WOL_FLAG; + } + BNX2X_DEV_INFO("%sWoL capable\n", +- (bp->flags & NO_WOL_FLAG) ? "Not " : ""); ++ (bp->flags & NO_WOL_FLAG) ? "not " : ""); + + val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); + val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); +@@ -7174,27 +8873,6 @@ + SUPPORTED_Asym_Pause); + break; + +- case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: +- BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n", +- ext_phy_type); +- +- bp->port.supported |= (SUPPORTED_10000baseT_Full | +- SUPPORTED_FIBRE | +- SUPPORTED_Pause | +- SUPPORTED_Asym_Pause); +- break; +- +- case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: +- BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n", +- ext_phy_type); +- +- bp->port.supported |= (SUPPORTED_10000baseT_Full | +- SUPPORTED_1000baseT_Full | +- SUPPORTED_FIBRE | +- SUPPORTED_Pause | +- SUPPORTED_Asym_Pause); +- break; +- + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: + BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n", + ext_phy_type); +@@ -7220,11 +8898,72 @@ + SUPPORTED_Asym_Pause); + break; + ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: ++ BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n", ++ ext_phy_type); ++ ++ bp->port.supported |= (SUPPORTED_10000baseT_Full | ++ SUPPORTED_FIBRE | ++ SUPPORTED_Pause | ++ SUPPORTED_Asym_Pause); ++ break; ++ ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: ++ BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n", ++ ext_phy_type); ++ ++ bp->port.supported |= (SUPPORTED_10000baseT_Full | ++ SUPPORTED_1000baseT_Full | ++ SUPPORTED_FIBRE | ++ SUPPORTED_Pause | ++ SUPPORTED_Asym_Pause); ++ break; ++ ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: ++ BNX2X_DEV_INFO("ext_phy_type 0x%x (8726)\n", ++ ext_phy_type); ++ ++ bp->port.supported |= (SUPPORTED_10000baseT_Full | ++ SUPPORTED_1000baseT_Full | ++ SUPPORTED_Autoneg | ++ SUPPORTED_FIBRE | ++ SUPPORTED_Pause | ++ SUPPORTED_Asym_Pause); ++ break; ++ ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: ++ BNX2X_DEV_INFO("ext_phy_type 0x%x (8727)\n", ++ ext_phy_type); ++ ++ bp->port.supported |= (SUPPORTED_10000baseT_Full | ++ SUPPORTED_1000baseT_Full | ++ SUPPORTED_Autoneg | ++ SUPPORTED_FIBRE | ++ SUPPORTED_Pause | ++ SUPPORTED_Asym_Pause); ++ break; ++ + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: + BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n", + ext_phy_type); + + bp->port.supported |= (SUPPORTED_10000baseT_Full | ++ SUPPORTED_TP | ++ SUPPORTED_Autoneg | ++ SUPPORTED_Pause | ++ SUPPORTED_Asym_Pause); ++ break; ++ ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: ++ BNX2X_DEV_INFO("ext_phy_type 0x%x (BCM8481)\n", ++ ext_phy_type); ++ ++ bp->port.supported |= (SUPPORTED_10baseT_Half | ++ SUPPORTED_10baseT_Full | ++ SUPPORTED_100baseT_Half | ++ SUPPORTED_100baseT_Full | ++ SUPPORTED_1000baseT_Full | ++ SUPPORTED_10000baseT_Full | + SUPPORTED_TP | + SUPPORTED_Autoneg | + SUPPORTED_Pause | +@@ -7441,9 +9180,9 @@ + + bp->link_params.req_flow_ctrl = (bp->port.link_config & + PORT_FEATURE_FLOW_CONTROL_MASK); +- if ((bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) && ++ if ((bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) && + !(bp->port.supported & SUPPORTED_Autoneg)) +- bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE; ++ bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; + + BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x" + " advertising 0x%x\n", +@@ -7456,17 +9195,29 @@ + { + int port = BP_PORT(bp); + u32 val, val2; ++ u32 config; ++ u16 i; ++ u32 ext_phy_type; + + bp->link_params.bp = bp; + bp->link_params.port = port; + +- bp->link_params.serdes_config = +- SHMEM_RD(bp, dev_info.port_hw_config[port].serdes_config); + bp->link_params.lane_config = + SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); + bp->link_params.ext_phy_config = + SHMEM_RD(bp, + dev_info.port_hw_config[port].external_phy_config); ++ /* BCM8727_NOC => BCM8727 no over current */ ++ if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) == ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC) { ++ bp->link_params.ext_phy_config &= ++ ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; ++ bp->link_params.ext_phy_config |= ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727; ++ bp->link_params.feature_config_flags |= ++ FEATURE_CONFIG_BCM8727_NOC; ++ } ++ + bp->link_params.speed_cap_mask = + SHMEM_RD(bp, + dev_info.port_hw_config[port].speed_capability_mask); +@@ -7474,19 +9225,51 @@ + bp->port.link_config = + SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); + +- BNX2X_DEV_INFO("serdes_config 0x%08x lane_config 0x%08x\n" +- KERN_INFO " ext_phy_config 0x%08x speed_cap_mask 0x%08x" +- " link_config 0x%08x\n", +- bp->link_params.serdes_config, ++ /* Get the 4 lanes xgxs config rx and tx */ ++ for (i = 0; i < 2; i++) { ++ val = SHMEM_RD(bp, ++ dev_info.port_hw_config[port].xgxs_config_rx[i<<1]); ++ bp->link_params.xgxs_config_rx[i << 1] = ((val>>16) & 0xffff); ++ bp->link_params.xgxs_config_rx[(i << 1) + 1] = (val & 0xffff); ++ ++ val = SHMEM_RD(bp, ++ dev_info.port_hw_config[port].xgxs_config_tx[i<<1]); ++ bp->link_params.xgxs_config_tx[i << 1] = ((val>>16) & 0xffff); ++ bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff); ++ } ++ ++ /* If the device is capable of WoL, set the default state according ++ * to the HW ++ */ ++ config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); ++ bp->wol = (!(bp->flags & NO_WOL_FLAG) && ++ (config & PORT_FEATURE_WOL_ENABLED)); ++ ++ BNX2X_DEV_INFO("lane_config 0x%08x ext_phy_config 0x%08x" ++ " speed_cap_mask 0x%08x link_config 0x%08x\n", + bp->link_params.lane_config, + bp->link_params.ext_phy_config, + bp->link_params.speed_cap_mask, bp->port.link_config); + +- bp->link_params.switch_cfg = (bp->port.link_config & +- PORT_FEATURE_CONNECTED_SWITCH_MASK); ++ bp->link_params.switch_cfg |= (bp->port.link_config & ++ PORT_FEATURE_CONNECTED_SWITCH_MASK); + bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); + + bnx2x_link_settings_requested(bp); ++ ++ /* ++ * If connected directly, work with the internal PHY, otherwise, work ++ * with the external PHY ++ */ ++ ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); ++ if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ++ bp->mdio.prtad = bp->link_params.phy_addr; ++ ++ else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && ++ (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) { ++ bp->mdio.prtad = ++ XGXS_EXT_PHY_ADDR(bp->link_params.ext_phy_config); ++ } + + val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); + val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); +@@ -7497,7 +9280,9 @@ + bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff); + bp->dev->dev_addr[5] = (u8)(val & 0xff); + memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); ++#ifdef ETHTOOL_GPERMADDR /* BNX2X_UPSTREAM */ + memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); ++#endif + } + + static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) +@@ -7514,20 +9299,31 @@ + bp->mf_config = + SHMEM_RD(bp, mf_cfg.func_mf_config[func].config); + +- val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) & ++ val = (SHMEM_RD(bp, mf_cfg.func_mf_config[FUNC_0].e1hov_tag) & + FUNC_MF_CFG_E1HOV_TAG_MASK); +- if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { +- +- bp->e1hov = val; ++ if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) + bp->e1hmf = 1; +- BNX2X_DEV_INFO("MF mode E1HOV for func %d is %d " +- "(0x%04x)\n", +- func, bp->e1hov, bp->e1hov); +- } else { +- BNX2X_DEV_INFO("Single function mode\n"); +- if (BP_E1HVN(bp)) { ++ BNX2X_DEV_INFO("%s function mode\n", ++ IS_E1HMF(bp) ? "multi" : "single"); ++ ++ if (IS_E1HMF(bp)) { ++ val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func]. ++ e1hov_tag) & ++ FUNC_MF_CFG_E1HOV_TAG_MASK); ++ if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { ++ bp->e1hov = val; ++ BNX2X_DEV_INFO("E1HOV for func %d is %d " ++ "(0x%04x)\n", ++ func, bp->e1hov, bp->e1hov); ++ } else { + BNX2X_ERR("!!! No valid E1HOV for func %d," + " aborting\n", func); ++ rc = -EPERM; ++ } ++ } else { ++ if (BP_E1HVN(bp)) { ++ BNX2X_ERR("!!! VN %d in single function mode," ++ " aborting\n", BP_E1HVN(bp)); + rc = -EPERM; + } + } +@@ -7554,8 +9350,10 @@ + bp->dev->dev_addr[5] = (u8)(val & 0xff); + memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, + ETH_ALEN); ++#ifdef ETHTOOL_GPERMADDR /* BNX2X_UPSTREAM */ + memcpy(bp->dev->perm_addr, bp->dev->dev_addr, + ETH_ALEN); ++#endif + } + + return rc; +@@ -7563,26 +9361,189 @@ + + if (BP_NOMCP(bp)) { + /* only supposed to happen on emulation/FPGA */ ++#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */ + BNX2X_ERR("warning random MAC workaround active\n"); + random_ether_addr(bp->dev->dev_addr); ++#else ++ BNX2X_ERR("warning constant MAC workaround active\n"); ++ bp->dev->dev_addr[0] = 0; ++ bp->dev->dev_addr[1] = 0x50; ++ bp->dev->dev_addr[2] = 0xc2; ++ bp->dev->dev_addr[3] = 0x2c; ++ bp->dev->dev_addr[4] = (func + 1) * 0x10; ++ bp->dev->dev_addr[5] = 0x00; ++ memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); ++#endif ++#ifdef ETHTOOL_GPERMADDR /* BNX2X_UPSTREAM */ + memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); +- } +- +- return rc; +-} ++#endif ++ } ++ ++ return rc; ++} ++ ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++static u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); ++ ++static void __devinit bnx2x_init_safc(struct bnx2x *bp) ++{ ++ int i, cos, max_cos, max_queues; ++ ++ bp->flags &= ~SAFC_TX_FLAG; ++ ++ for (i = 0; i < BNX2X_MAX_PRIORITY; i++) ++ bp->pri_map[i] = 0; ++ ++ max_cos = BNX2X_MAX_COS; ++ bp->cos_weight_sum = 0; ++ for (cos = 0; cos < BNX2X_MAX_COS; cos++) { ++ bp->qs_per_cos[cos] = 0; ++ bp->cos_min_rate[cos] = 0; ++ } ++ ++ switch (bp->multi_mode) { ++ case ETH_RSS_MODE_DISABLED: ++ bp->qs_per_cos[0] = 1; ++ break; ++ ++ case ETH_RSS_MODE_REGULAR: ++ bp->qs_per_cos[0] = min_t(u32, num_online_cpus(), ++ BNX2X_MAX_QUEUES(bp)); ++ break; ++ ++ case ETH_RSS_MODE_VLAN_PRI: ++ case ETH_RSS_MODE_E1HOV_PRI: ++ if (CHIP_IS_E1H(bp)) { ++ bp->flags |= SAFC_TX_FLAG; ++ max_cos = BNX2X_MAX_TX_COS; ++ } ++ ++ /* fallthrough */ ++ ++ case ETH_RSS_MODE_IP_DSCP: ++ /* COS 0 must have at least 1 queue */ ++ if (BNX2X_COS_QUEUES(0) == 0) { ++ printk(KERN_ERR PFX ++ "Illegal number of queues per COS 0 " ++ "defaulting to 1\n"); ++ qs_per_cos |= 0x1; ++ } ++ ++ for (i = 0; i < BNX2X_MAX_PRIORITY; i++) { ++ cos = ((pri_map & (0xf << i*4)) >> i*4); ++ if (cos < max_cos) { ++ bp->pri_map[i] = cos; ++ if (BNX2X_COS_QUEUES(cos) == 0) { ++ printk(KERN_ERR PFX ++ "Illegal number of queues per " ++ "COS %d defaulting to 1\n", ++ cos); ++ qs_per_cos |= (0x1 << cos*8); ++ } ++ } else { ++ printk(KERN_ERR PFX ++ "Illegal COS (%d) for priority %d " ++ "defaulting to 0\n", cos, i); ++ pri_map &= ~(0xf << i*4); ++ bp->pri_map[i] = 0; ++ } ++ } ++ ++ max_queues = BNX2X_MAX_QUEUES(bp); ++ for (cos = 0; cos < BNX2X_MAX_COS; cos++) { ++ i = BNX2X_COS_QUEUES(cos); ++ if (i <= max_queues) { ++ bp->qs_per_cos[cos] = i; ++ max_queues -= i; ++ } else { ++ bp->qs_per_cos[cos] = max_queues; ++ max_queues = 0; ++ } ++ if (bp->qs_per_cos[cos] == 0) ++ for (i = 0; i < BNX2X_MAX_PRIORITY; i++) ++ if (bp->pri_map[i] == cos) { ++ printk(KERN_ERR PFX ++ "Illegal COS (%d) for " ++ "priority %d " ++ "defaulting to 0\n", ++ cos, i); ++ pri_map &= ~(0xf << i*4); ++ bp->pri_map[i] = 0; ++ } ++ } ++ ++ bp->dev->select_queue = bnx2x_select_queue; ++ ++ if (cos_min_rate == 0) ++ break; ++ ++ for (cos = 0; cos < BNX2X_MAX_COS; cos++) { ++ i = BNX2X_COS_RATE(cos); ++ if (i > 100) { ++ printk(KERN_ERR PFX ++ "Illegal rate (%d) for COS %d " ++ "defaulting to 100\n", i, cos); ++ i = 100; ++ cos_min_rate |= (i << cos*8); ++ } ++ i *= 100; ++ if (bp->qs_per_cos[cos]) { ++ if (i == 0) { ++ printk(KERN_ERR PFX ++ "Illegal rate for COS %d " ++ "defaulting to 1\n", cos); ++ i = DEF_MIN_RATE; ++ cos_min_rate |= (i << cos*8); ++ } ++ } else { ++ if (i) { ++ printk(KERN_ERR PFX ++ "Illegal rate (%d) for COS %d " ++ "with no queues " ++ "defaulting to 0\n", i, cos); ++ i = 0; ++ cos_min_rate &= ~(0xff << cos*8); ++ } ++ } ++ bp->cos_min_rate[cos] = i; ++ bp->cos_weight_sum += i; ++ } ++ break; ++ ++ default: ++ bp->multi_mode = ETH_RSS_MODE_DISABLED; ++ bp->qs_per_cos[0] = 1; ++ break; ++ } ++} ++#endif + + static int __devinit bnx2x_init_bp(struct bnx2x *bp) + { + int func = BP_FUNC(bp); ++ int timer_interval; + int rc; + + /* Disable interrupt handling until HW is initialized */ + atomic_set(&bp->intr_sem, 1); ++ smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */ + + mutex_init(&bp->port.phy_mutex); + ++#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) || (VMWARE_ESX_DDK_VERSION >= 40000) /* BNX2X_UPSTREAM */ ++#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */ + INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); ++#else ++ INIT_WORK(&bp->sp_task, bnx2x_sp_task); ++#endif + INIT_WORK(&bp->reset_task, bnx2x_reset_task); ++#else ++ INIT_WORK(&bp->sp_task, bnx2x_sp_task, bp); ++ INIT_WORK(&bp->reset_task, bnx2x_reset_task, bp); ++#endif ++#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */ ++ bp->sp_running = 0; ++#endif + + rc = bnx2x_get_hwinfo(bp); + +@@ -7597,27 +9558,65 @@ + printk(KERN_ERR PFX + "MCP disabled, must load devices in order!\n"); + ++ /* Set multi queue mode and priority mapping */ ++ if ((multi_mode != ETH_RSS_MODE_DISABLED) && ++ ((int_mode == INT_MODE_INTx) || (int_mode == INT_MODE_MSI))) { ++ printk(KERN_ERR PFX ++ "Multi disabled since int_mode requested is not MSI-X\n"); ++ multi_mode = ETH_RSS_MODE_DISABLED; ++ } ++ bp->multi_mode = multi_mode; ++ ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++ bnx2x_init_safc(bp); ++#endif ++ + /* Set TPA flags */ + if (disable_tpa) { + bp->flags &= ~TPA_ENABLE_FLAG; ++#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */ + bp->dev->features &= ~NETIF_F_LRO; ++#endif + } else { + bp->flags |= TPA_ENABLE_FLAG; ++#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */ + bp->dev->features |= NETIF_F_LRO; +- } +- +- ++#endif ++ } ++ ++ if (CHIP_IS_E1(bp)) ++ bp->dropless_fc = 0; ++ else ++ bp->dropless_fc = dropless_fc; ++ ++ bp->mrrs = mrrs; ++ ++#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */ ++ /* MCP workaround */ ++ if (BP_NOMCP(bp)) { ++ /* [0x24c0]table size: ++ PCI_REG_GRC_PTR(func)->pci_msix_control = 0x10; */ ++ REG_WR(bp, 0x24c0, 0x10); ++ /* [0x24c4]table pointer: ++ PCI_REG_GRC_PTR(func)->pci_msix_tbl_off_bir = ++ 0x440000 + 0x2000*func; */ ++ REG_WR(bp, 0x24c4, 0x440000 + 0x2000*func); ++ /* [0x24c8]PBA pointer: ++ PCI_REG_GRC_PTR(func)->pci_msix_pba_off_bir = ++ 0x441800 + 0x2000*func; */ ++ REG_WR(bp, 0x24c8, 0x441800 + 0x2000*func); ++ } ++#endif + bp->tx_ring_size = MAX_TX_AVAIL; + bp->rx_ring_size = MAX_RX_AVAIL; + + bp->rx_csum = 1; +- bp->rx_offset = 0; + + bp->tx_ticks = 50; + bp->rx_ticks = 25; + +- bp->timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); +- bp->current_interval = (poll ? poll : bp->timer_interval); ++ timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); ++ bp->current_interval = (poll ? poll : timer_interval); + + init_timer(&bp->timer); + bp->timer.expires = jiffies + bp->current_interval; +@@ -7662,14 +9661,17 @@ + + switch (ext_phy_type) { + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: +- case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: +- case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: + cmd->port = PORT_FIBRE; + break; + + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: ++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: + cmd->port = PORT_TP; + break; + +@@ -7686,7 +9688,7 @@ + } else + cmd->port = PORT_TP; + +- cmd->phy_address = bp->port.phy_addr; ++ cmd->phy_address = bp->mdio.prtad; + cmd->transceiver = XCVR_INTERNAL; + + if (bp->link_params.req_line_speed == SPEED_AUTO_NEG) +@@ -7859,6 +9861,81 @@ + return 0; + } + ++#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE) ++#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE) ++ ++static int bnx2x_get_regs_len(struct net_device *dev) ++{ ++ struct bnx2x *bp = netdev_priv(dev); ++ int regdump_len = 0; ++ int i; ++ ++ if (CHIP_IS_E1(bp)) { ++ for (i = 0; i < REGS_COUNT; i++) ++ if (IS_E1_ONLINE(reg_addrs[i].info)) ++ regdump_len += reg_addrs[i].size; ++ ++ for (i = 0; i < WREGS_COUNT_E1; i++) ++ if (IS_E1_ONLINE(wreg_addrs_e1[i].info)) ++ regdump_len += wreg_addrs_e1[i].size * ++ (1 + wreg_addrs_e1[i].read_regs_count); ++ ++ } else { /* E1H */ ++ for (i = 0; i < REGS_COUNT; i++) ++ if (IS_E1H_ONLINE(reg_addrs[i].info)) ++ regdump_len += reg_addrs[i].size; ++ ++ for (i = 0; i < WREGS_COUNT_E1H; i++) ++ if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info)) ++ regdump_len += wreg_addrs_e1h[i].size * ++ (1 + wreg_addrs_e1h[i].read_regs_count); ++ } ++ regdump_len *= 4; ++ regdump_len += sizeof(struct dump_hdr); ++ ++ return regdump_len; ++} ++ ++static void bnx2x_get_regs(struct net_device *dev, ++ struct ethtool_regs *regs, void *_p) ++{ ++ u32 *p = _p, i, j; ++ struct bnx2x *bp = netdev_priv(dev); ++ struct dump_hdr dump_hdr = {0}; ++ ++ regs->version = 0; ++ memset(p, 0, regs->len); ++ ++ if (!netif_running(bp->dev)) ++ return; ++ ++ dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1; ++ dump_hdr.dump_sign = dump_sign_all; ++ dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR); ++ dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR); ++ dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR); ++ dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR); ++ dump_hdr.info = CHIP_IS_E1(bp) ? RI_E1_ONLINE : RI_E1H_ONLINE; ++ ++ memcpy(p, &dump_hdr, sizeof(struct dump_hdr)); ++ p += dump_hdr.hdr_size + 1; ++ ++ if (CHIP_IS_E1(bp)) { ++ for (i = 0; i < REGS_COUNT; i++) ++ if (IS_E1_ONLINE(reg_addrs[i].info)) ++ for (j = 0; j < reg_addrs[i].size; j++) ++ *p++ = REG_RD(bp, ++ reg_addrs[i].addr + j*4); ++ ++ } else { /* E1H */ ++ for (i = 0; i < REGS_COUNT; i++) ++ if (IS_E1H_ONLINE(reg_addrs[i].info)) ++ for (j = 0; j < reg_addrs[i].size; j++) ++ *p++ = REG_RD(bp, ++ reg_addrs[i].addr + j*4); ++ } ++} ++ + #define PHY_FW_VER_LEN 10 + + static void bnx2x_get_drvinfo(struct net_device *dev, +@@ -7888,7 +9965,7 @@ + info->n_stats = BNX2X_NUM_STATS; + info->testinfo_len = BNX2X_NUM_TESTS; + info->eedump_len = bp->common.flash_size; +- info->regdump_len = 0; ++ info->regdump_len = bnx2x_get_regs_len(dev); + } + + static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) +@@ -7956,12 +10033,21 @@ + return 0; + } + ++static u32 bnx2x_get_link(struct net_device *dev) ++{ ++ struct bnx2x *bp = netdev_priv(dev); ++ ++ return bp->link_vars.link_up; ++} ++ ++#if (LINUX_VERSION_CODE >= 0x020418) /* BNX2X_UPSTREAM */ + static int bnx2x_get_eeprom_len(struct net_device *dev) + { + struct bnx2x *bp = netdev_priv(dev); + + return bp->common.flash_size; + } ++#endif + + static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) + { +@@ -8049,7 +10135,7 @@ + MCPR_NVM_ACCESS_ENABLE_WR_EN))); + } + +-static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, u32 *ret_val, ++static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, + u32 cmd_flags) + { + int count, i, rc; +@@ -8085,8 +10171,7 @@ + /* we read nvram data in cpu order + * but ethtool sees it as an array of bytes + * converting to big-endian will do the work */ +- val = cpu_to_be32(val); +- *ret_val = val; ++ *ret_val = cpu_to_be32(val); + rc = 0; + break; + } +@@ -8100,7 +10185,7 @@ + { + int rc; + u32 cmd_flags; +- u32 val; ++ __be32 val; + + if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { + DP(BNX2X_MSG_NVM, +@@ -8219,7 +10304,7 @@ + int rc; + u32 cmd_flags; + u32 align_offset; +- u32 val; ++ __be32 val; + + if (offset + buf_size > bp->common.flash_size) { + DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" +@@ -8324,7 +10409,8 @@ + struct ethtool_eeprom *eeprom, u8 *eebuf) + { + struct bnx2x *bp = netdev_priv(dev); +- int rc; ++ int port = BP_PORT(bp); ++ int rc = 0; + + if (!netif_running(dev)) + return -EAGAIN; +@@ -8336,27 +10422,60 @@ + + /* parameters already validated in ethtool_set_eeprom */ + +- /* If the magic number is PHY (0x00504859) upgrade the PHY FW */ +- if (eeprom->magic == 0x00504859) +- if (bp->port.pmf) { +- ++ /* PHY eeprom can be accessed only by the PMF */ ++ if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && ++ !bp->port.pmf) ++ return -EINVAL; ++ ++ if (eeprom->magic == 0x50485950) { ++ /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ ++ bnx2x_stats_handle(bp, STATS_EVENT_STOP); ++ ++ bnx2x_acquire_phy_lock(bp); ++ rc |= bnx2x_link_reset(&bp->link_params, ++ &bp->link_vars, 0); ++ if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) == ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) ++ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, ++ MISC_REGISTERS_GPIO_HIGH, port); ++ bnx2x_release_phy_lock(bp); ++ bnx2x_link_report(bp); ++ ++ } else if (eeprom->magic == 0x50485952) { ++ /* 'PHYR' (0x50485952): re-init link after FW upgrade */ ++ if ((bp->state == BNX2X_STATE_OPEN) || ++ (bp->state == BNX2X_STATE_DISABLED)) { + bnx2x_acquire_phy_lock(bp); +- rc = bnx2x_flash_download(bp, BP_PORT(bp), +- bp->link_params.ext_phy_config, +- (bp->state != BNX2X_STATE_CLOSED), +- eebuf, eeprom->len); +- if ((bp->state == BNX2X_STATE_OPEN) || +- (bp->state == BNX2X_STATE_DISABLED)) { +- rc |= bnx2x_link_reset(&bp->link_params, +- &bp->link_vars); +- rc |= bnx2x_phy_init(&bp->link_params, +- &bp->link_vars); +- } ++ rc |= bnx2x_link_reset(&bp->link_params, ++ &bp->link_vars, 1); ++ ++ rc |= bnx2x_phy_init(&bp->link_params, ++ &bp->link_vars); + bnx2x_release_phy_lock(bp); +- +- } else /* Only the PMF can access the PHY */ +- return -EINVAL; +- else ++ bnx2x_calc_fc_adv(bp); ++ } ++ } else if (eeprom->magic == 0x53985943) { ++ /* 'PHYC' (0x53985943): PHY FW upgrade completed */ ++ if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) == ++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { ++ u8 ext_phy_addr = ++ XGXS_EXT_PHY_ADDR(bp->link_params.ext_phy_config); ++ ++ /* DSP Remove Download Mode */ ++ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, ++ MISC_REGISTERS_GPIO_LOW, port); ++ ++ bnx2x_acquire_phy_lock(bp); ++ ++ bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr); ++ ++ /* wait 0.5 sec to allow it to run */ ++ msleep(500); ++ bnx2x_ext_phy_hw_reset(bp, port); ++ msleep(500); ++ bnx2x_release_phy_lock(bp); ++ } ++ } else + rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); + + return rc; +@@ -8375,18 +10494,19 @@ + return 0; + } + ++#define BNX2X_MAX_COALES_TOUT (0xf0*12) /* Maximal coalescing timeout in us */ + static int bnx2x_set_coalesce(struct net_device *dev, + struct ethtool_coalesce *coal) + { + struct bnx2x *bp = netdev_priv(dev); + + bp->rx_ticks = (u16) coal->rx_coalesce_usecs; +- if (bp->rx_ticks > 3000) +- bp->rx_ticks = 3000; ++ if (bp->rx_ticks > BNX2X_MAX_COALES_TOUT) ++ bp->rx_ticks = BNX2X_MAX_COALES_TOUT; + + bp->tx_ticks = (u16) coal->tx_coalesce_usecs; +- if (bp->tx_ticks > 0x3000) +- bp->tx_ticks = 0x3000; ++ if (bp->tx_ticks > BNX2X_MAX_COALES_TOUT) ++ bp->tx_ticks = BNX2X_MAX_COALES_TOUT; + + if (netif_running(dev)) + bnx2x_update_coalesce(bp); +@@ -8438,13 +10558,14 @@ + { + struct bnx2x *bp = netdev_priv(dev); + +- epause->autoneg = (bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) && ++ epause->autoneg = (bp->link_params.req_flow_ctrl == ++ BNX2X_FLOW_CTRL_AUTO) && + (bp->link_params.req_line_speed == SPEED_AUTO_NEG); + +- epause->rx_pause = ((bp->link_vars.flow_ctrl & FLOW_CTRL_RX) == +- FLOW_CTRL_RX); +- epause->tx_pause = ((bp->link_vars.flow_ctrl & FLOW_CTRL_TX) == +- FLOW_CTRL_TX); ++ epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) == ++ BNX2X_FLOW_CTRL_RX); ++ epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) == ++ BNX2X_FLOW_CTRL_TX); + + DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n" + DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n", +@@ -8463,16 +10584,16 @@ + DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n", + epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); + +- bp->link_params.req_flow_ctrl = FLOW_CTRL_AUTO; ++ bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; + + if (epause->rx_pause) +- bp->link_params.req_flow_ctrl |= FLOW_CTRL_RX; ++ bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_RX; + + if (epause->tx_pause) +- bp->link_params.req_flow_ctrl |= FLOW_CTRL_TX; +- +- if (bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) +- bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE; ++ bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_TX; ++ ++ if (bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) ++ bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; + + if (epause->autoneg) { + if (!(bp->port.supported & SUPPORTED_Autoneg)) { +@@ -8481,7 +10602,7 @@ + } + + if (bp->link_params.req_line_speed == SPEED_AUTO_NEG) +- bp->link_params.req_flow_ctrl = FLOW_CTRL_AUTO; ++ bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; + } + + DP(NETIF_MSG_LINK, +@@ -8495,6 +10616,7 @@ + return 0; + } + ++#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */ + static int bnx2x_set_flags(struct net_device *dev, u32 data) + { + struct bnx2x *bp = netdev_priv(dev); +@@ -8522,6 +10644,7 @@ + + return rc; + } ++#endif + + static u32 bnx2x_get_rx_csum(struct net_device *dev) + { +@@ -8540,26 +10663,52 @@ + /* Disable TPA, when Rx CSUM is disabled. Otherwise all + TPA'ed packets will be discarded due to wrong TCP CSUM */ + if (!data) { ++#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */ + u32 flags = ethtool_op_get_flags(dev); + + rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO)); +- } +- +- return rc; +-} +- ++#else ++ bp->flags &= ~TPA_ENABLE_FLAG; ++ if (netif_running(dev)) { ++ bnx2x_nic_unload(bp, UNLOAD_NORMAL); ++ rc = bnx2x_nic_load(bp, LOAD_NORMAL); ++ } ++#endif ++ } ++ ++ return rc; ++} ++ ++#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */ + static int bnx2x_set_tso(struct net_device *dev, u32 data) + { + if (data) { + dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN); ++#ifdef NETIF_F_TSO6 /* BNX2X_UPSTREAM */ + dev->features |= NETIF_F_TSO6; ++#endif ++#ifdef BCM_VLAN ++#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */ ++ dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN); ++ dev->vlan_features |= NETIF_F_TSO6; ++#endif ++#endif + } else { + dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN); ++#ifdef NETIF_F_TSO6 /* BNX2X_UPSTREAM */ + dev->features &= ~NETIF_F_TSO6; +- } +- +- return 0; +-} ++#endif ++#ifdef BCM_VLAN ++#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */ ++ dev->vlan_features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN); ++ dev->vlan_features &= ~NETIF_F_TSO6; ++#endif ++#endif ++ } ++ ++ return 0; ++} ++#endif + + static const struct { + char string[ETH_GSTRING_LEN]; +@@ -8570,8 +10719,7 @@ + { "nvram_test (online)" }, + { "interrupt_test (online)" }, + { "link_test (online)" }, +- { "idle check (online)" }, +- { "MC errors (online)" } ++ { "idle check (online)" } + }; + + static int bnx2x_self_test_count(struct net_device *dev) +@@ -8607,10 +10755,9 @@ + { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, + { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, + { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, +- { NIG_REG_EGRESS_MNG0_FIFO, 20, 0xffffffff }, + { NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, +-/* 20 */ { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, +- { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, ++ { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, ++/* 20 */ { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, + { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, + { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, + { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, +@@ -8619,8 +10766,8 @@ + { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, + { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, + { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, +-/* 30 */ { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, +- { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, ++ { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, ++/* 30 */ { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, + { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, + { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, + { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 }, +@@ -8746,12 +10893,14 @@ + unsigned int pkt_size, num_pkts, i; + struct sk_buff *skb; + unsigned char *packet; +- struct bnx2x_fastpath *fp = &bp->fp[0]; ++ struct bnx2x_fastpath *fp_rx = &bp->fp[0]; ++ struct bnx2x_fastpath *fp_tx = &bp->fp[bp->num_rx_queues]; + u16 tx_start_idx, tx_idx; + u16 rx_start_idx, rx_idx; +- u16 pkt_prod; ++ u16 pkt_prod, bd_prod; + struct sw_tx_bd *tx_buf; +- struct eth_tx_bd *tx_bd; ++ struct eth_tx_start_bd *tx_start_bd; ++ struct eth_tx_parse_bd *pbd = NULL; + dma_addr_t mapping; + union eth_rx_cqe *cqe; + u8 cqe_fp_flags; +@@ -8759,23 +10908,23 @@ + u16 len; + int rc = -ENODEV; + +- if (loopback_mode == BNX2X_MAC_LOOPBACK) { ++ /* check the loopback mode */ ++ switch (loopback_mode) { ++ case BNX2X_PHY_LOOPBACK: ++ if (bp->link_params.loopback_mode != LOOPBACK_XGXS_10) ++ return -EINVAL; ++ break; ++ case BNX2X_MAC_LOOPBACK: + bp->link_params.loopback_mode = LOOPBACK_BMAC; + bnx2x_phy_init(&bp->link_params, &bp->link_vars); +- +- } else if (loopback_mode == BNX2X_PHY_LOOPBACK) { +- u16 cnt = 1000; +- bp->link_params.loopback_mode = LOOPBACK_XGXS_10; +- bnx2x_phy_init(&bp->link_params, &bp->link_vars); +- /* wait until link state is restored */ +- if (link_up) +- while (cnt-- && bnx2x_test_link(&bp->link_params, +- &bp->link_vars)) +- msleep(10); +- } else +- return -EINVAL; +- +- pkt_size = 1514; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* prepare the loopback packet */ ++ pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? ++ bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); + skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size); + if (!skb) { + rc = -ENOMEM; +@@ -8783,58 +10932,64 @@ + } + packet = skb_put(skb, pkt_size); + memcpy(packet, bp->dev->dev_addr, ETH_ALEN); +- memset(packet + ETH_ALEN, 0, (ETH_HLEN - ETH_ALEN)); ++ memset(packet + ETH_ALEN, 0, ETH_ALEN); ++ memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); + for (i = ETH_HLEN; i < pkt_size; i++) + packet[i] = (unsigned char) (i & 0xff); + ++ /* send the loopback packet */ + num_pkts = 0; +- tx_start_idx = le16_to_cpu(*fp->tx_cons_sb); +- rx_start_idx = le16_to_cpu(*fp->rx_cons_sb); +- +- pkt_prod = fp->tx_pkt_prod++; +- tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)]; +- tx_buf->first_bd = fp->tx_bd_prod; ++ tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb); ++ rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); ++ ++ pkt_prod = fp_tx->tx_pkt_prod++; ++ tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)]; ++ tx_buf->first_bd = fp_tx->tx_bd_prod; + tx_buf->skb = skb; +- +- tx_bd = &fp->tx_desc_ring[TX_BD(fp->tx_bd_prod)]; ++ tx_buf->flags = 0; ++ ++ bd_prod = TX_BD(fp_tx->tx_bd_prod); ++ tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd; + mapping = pci_map_single(bp->pdev, skb->data, + skb_headlen(skb), PCI_DMA_TODEVICE); +- tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); +- tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); +- tx_bd->nbd = cpu_to_le16(1); +- tx_bd->nbytes = cpu_to_le16(skb_headlen(skb)); +- tx_bd->vlan = cpu_to_le16(pkt_prod); +- tx_bd->bd_flags.as_bitfield = (ETH_TX_BD_FLAGS_START_BD | +- ETH_TX_BD_FLAGS_END_BD); +- tx_bd->general_data = ((UNICAST_ADDRESS << +- ETH_TX_BD_ETH_ADDR_TYPE_SHIFT) | 1); ++ tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); ++ tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); ++ tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ ++ tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); ++ tx_start_bd->vlan = cpu_to_le16(pkt_prod); ++ tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; ++ tx_start_bd->general_data = ((UNICAST_ADDRESS << ++ ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT) | 1); ++ ++ /* turn on parsing and get a BD */ ++ bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); ++ pbd = &fp_tx->tx_desc_ring[bd_prod].parse_bd; ++ ++ memset(pbd, 0, sizeof(struct eth_tx_parse_bd)); + + wmb(); + +- fp->hw_tx_prods->bds_prod = +- cpu_to_le16(le16_to_cpu(fp->hw_tx_prods->bds_prod) + 1); +- mb(); /* FW restriction: must not reorder writing nbd and packets */ +- fp->hw_tx_prods->packets_prod = +- cpu_to_le32(le32_to_cpu(fp->hw_tx_prods->packets_prod) + 1); +- DOORBELL(bp, FP_IDX(fp), 0); ++ fp_tx->tx_db.data.prod += 2; ++ barrier(); ++ DOORBELL(bp, fp_tx->index - bp->num_rx_queues, fp_tx->tx_db.raw); + + mmiowb(); + + num_pkts++; +- fp->tx_bd_prod++; ++ fp_tx->tx_bd_prod += 2; /* start + pbd */ + bp->dev->trans_start = jiffies; + + udelay(100); + +- tx_idx = le16_to_cpu(*fp->tx_cons_sb); ++ tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb); + if (tx_idx != tx_start_idx + num_pkts) + goto test_loopback_exit; + +- rx_idx = le16_to_cpu(*fp->rx_cons_sb); ++ rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); + if (rx_idx != rx_start_idx + num_pkts) + goto test_loopback_exit; + +- cqe = &fp->rx_comp_ring[RCQ_BD(fp->rx_comp_cons)]; ++ cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; + cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; + if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) + goto test_loopback_rx_exit; +@@ -8843,7 +10998,7 @@ + if (len != pkt_size) + goto test_loopback_rx_exit; + +- rx_buf = &fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)]; ++ rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; + skb = rx_buf->skb; + skb_reserve(skb, cqe->fast_path_cqe.placement_offset); + for (i = ETH_HLEN; i < pkt_size; i++) +@@ -8853,16 +11008,18 @@ + rc = 0; + + test_loopback_rx_exit: ++#if (LINUX_VERSION_CODE < 0x02061b) /* ! BNX2X_UPSTREAM */ + bp->dev->last_rx = jiffies; +- +- fp->rx_bd_cons = NEXT_RX_IDX(fp->rx_bd_cons); +- fp->rx_bd_prod = NEXT_RX_IDX(fp->rx_bd_prod); +- fp->rx_comp_cons = NEXT_RCQ_IDX(fp->rx_comp_cons); +- fp->rx_comp_prod = NEXT_RCQ_IDX(fp->rx_comp_prod); ++#endif ++ ++ fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); ++ fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); ++ fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); ++ fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); + + /* Update producers */ +- bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod, +- fp->rx_sge_prod); ++ bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, ++ fp_rx->rx_sge_prod); + + test_loopback_exit: + bp->link_params.loopback_mode = LOOPBACK_NONE; +@@ -8872,7 +11029,7 @@ + + static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up) + { +- int rc = 0; ++ int rc = 0, res; + + if (!netif_running(bp->dev)) + return BNX2X_LOOPBACK_FAILED; +@@ -8880,14 +11037,16 @@ + bnx2x_netif_stop(bp, 1); + bnx2x_acquire_phy_lock(bp); + +- if (bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up)) { +- DP(NETIF_MSG_PROBE, "MAC loopback failed\n"); ++ res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up); ++ if (res) { ++ DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res); ++ rc |= BNX2X_PHY_LOOPBACK_FAILED; ++ } ++ ++ res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up); ++ if (res) { ++ DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res); + rc |= BNX2X_MAC_LOOPBACK_FAILED; +- } +- +- if (bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up)) { +- DP(NETIF_MSG_PROBE, "PHY loopback failed\n"); +- rc |= BNX2X_PHY_LOOPBACK_FAILED; + } + + bnx2x_release_phy_lock(bp); +@@ -8914,14 +11073,14 @@ + { 0x778, 0x70 }, + { 0, 0 } + }; +- u32 buf[0x350 / 4]; ++ __be32 buf[0x350 / 4]; + u8 *data = (u8 *)buf; + int i, rc; +- u32 magic, csum; ++ u32 magic, crc; + + rc = bnx2x_nvram_read(bp, 0, data, 4); + if (rc) { +- DP(NETIF_MSG_PROBE, "magic value read (rc -%d)\n", -rc); ++ DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc); + goto test_nvram_exit; + } + +@@ -8938,14 +11097,14 @@ + nvram_tbl[i].size); + if (rc) { + DP(NETIF_MSG_PROBE, +- "nvram_tbl[%d] read data (rc -%d)\n", i, -rc); ++ "nvram_tbl[%d] read data (rc %d)\n", i, rc); + goto test_nvram_exit; + } + +- csum = ether_crc_le(nvram_tbl[i].size, data); +- if (csum != CRC32_RESIDUAL) { ++ crc = ether_crc_le(nvram_tbl[i].size, data); ++ if (crc != CRC32_RESIDUAL) { + DP(NETIF_MSG_PROBE, +- "nvram_tbl[%d] csum value (0x%08x)\n", i, csum); ++ "nvram_tbl[%d] crc value (0x%08x)\n", i, crc); + rc = -ENODEV; + goto test_nvram_exit; + } +@@ -8963,12 +11122,12 @@ + if (!netif_running(bp->dev)) + return -ENODEV; + +- config->hdr.length_6b = 0; ++ config->hdr.length = 0; + if (CHIP_IS_E1(bp)) + config->hdr.offset = (BP_PORT(bp) ? 32 : 0); + else + config->hdr.offset = BP_FUNC(bp); +- config->hdr.client_id = BP_CL_ID(bp); ++ config->hdr.client_id = bp->fp->cl_id; + config->hdr.reserved1 = 0; + + rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, +@@ -9003,7 +11162,14 @@ + etest->flags &= ~ETH_TEST_FL_OFFLINE; + + if (etest->flags & ETH_TEST_FL_OFFLINE) { ++ int port = BP_PORT(bp); ++ u32 val; + u8 link_up; ++ ++ /* save current value of input enable for TX port IF */ ++ val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); ++ /* disable input for TX port IF */ ++ REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); + + link_up = bp->link_vars.link_up; + bnx2x_nic_unload(bp, UNLOAD_NORMAL); +@@ -9024,6 +11190,10 @@ + etest->flags |= ETH_TEST_FL_FAILED; + + bnx2x_nic_unload(bp, UNLOAD_NORMAL); ++ ++ /* restore input for TX port IF */ ++ REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); ++ + bnx2x_nic_load(bp, LOAD_NORMAL); + /* wait until link state is restored */ + bnx2x_wait_for_link(bp, link_up); +@@ -9041,14 +11211,44 @@ + buf[5] = 1; + etest->flags |= ETH_TEST_FL_FAILED; + } +- buf[7] = bnx2x_mc_assert(bp); +- if (buf[7] != 0) ++#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ ++ /* run the idle check twice */ ++ bnx2x_idle_chk(bp); ++ buf[6] = bnx2x_idle_chk(bp); ++ if (buf[6] != 0) + etest->flags |= ETH_TEST_FL_FAILED; ++#endif + + #ifdef BNX2X_EXTRA_DEBUG + bnx2x_panic_dump(bp); + #endif + } ++ ++static const struct { ++ long offset; ++ int size; ++ u8 string[ETH_GSTRING_LEN]; ++} bnx2x_q_stats_arr[BNX2X_NUM_Q_STATS] = { ++/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%d]: rx_bytes" }, ++ { Q_STATS_OFFSET32(error_bytes_received_hi), ++ 8, "[%d]: rx_error_bytes" }, ++ { Q_STATS_OFFSET32(total_unicast_packets_received_hi), ++ 8, "[%d]: rx_ucast_packets" }, ++ { Q_STATS_OFFSET32(total_multicast_packets_received_hi), ++ 8, "[%d]: rx_mcast_packets" }, ++ { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), ++ 8, "[%d]: rx_bcast_packets" }, ++ { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%d]: rx_discards" }, ++ { Q_STATS_OFFSET32(rx_err_discard_pkt), ++ 4, "[%d]: rx_phy_ip_err_discards"}, ++ { Q_STATS_OFFSET32(rx_skb_alloc_failed), ++ 4, "[%d]: rx_skb_alloc_discard" }, ++ { Q_STATS_OFFSET32(hw_csum_err), 4, "[%d]: rx_csum_offload_errors" }, ++ ++/* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%d]: tx_bytes" }, ++ { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), ++ 8, "[%d]: tx_packets" } ++}; + + static const struct { + long offset; +@@ -9056,37 +11256,69 @@ + u32 flags; + #define STATS_FLAGS_PORT 1 + #define STATS_FLAGS_FUNC 2 ++#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) + u8 string[ETH_GSTRING_LEN]; + } bnx2x_stats_arr[BNX2X_NUM_STATS] = { +-/* 1 */ { STATS_OFFSET32(valid_bytes_received_hi), +- 8, STATS_FLAGS_FUNC, "rx_bytes" }, ++/* 1 */ { STATS_OFFSET32(total_bytes_received_hi), ++ 8, STATS_FLAGS_BOTH, "rx_bytes" }, + { STATS_OFFSET32(error_bytes_received_hi), +- 8, STATS_FLAGS_FUNC, "rx_error_bytes" }, +- { STATS_OFFSET32(total_bytes_transmitted_hi), +- 8, STATS_FLAGS_FUNC, "tx_bytes" }, +- { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), +- 8, STATS_FLAGS_PORT, "tx_error_bytes" }, ++ 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, + { STATS_OFFSET32(total_unicast_packets_received_hi), +- 8, STATS_FLAGS_FUNC, "rx_ucast_packets" }, ++ 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, + { STATS_OFFSET32(total_multicast_packets_received_hi), +- 8, STATS_FLAGS_FUNC, "rx_mcast_packets" }, ++ 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, + { STATS_OFFSET32(total_broadcast_packets_received_hi), +- 8, STATS_FLAGS_FUNC, "rx_bcast_packets" }, +- { STATS_OFFSET32(total_unicast_packets_transmitted_hi), +- 8, STATS_FLAGS_FUNC, "tx_packets" }, +- { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), +- 8, STATS_FLAGS_PORT, "tx_mac_errors" }, +-/* 10 */{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), +- 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, ++ 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, + { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), + 8, STATS_FLAGS_PORT, "rx_crc_errors" }, + { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), + 8, STATS_FLAGS_PORT, "rx_align_errors" }, ++ { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), ++ 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, ++ { STATS_OFFSET32(etherstatsoverrsizepkts_hi), ++ 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, ++/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), ++ 8, STATS_FLAGS_PORT, "rx_fragments" }, ++ { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), ++ 8, STATS_FLAGS_PORT, "rx_jabbers" }, ++ { STATS_OFFSET32(no_buff_discard_hi), ++ 8, STATS_FLAGS_BOTH, "rx_discards" }, ++ { STATS_OFFSET32(mac_filter_discard), ++ 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, ++ { STATS_OFFSET32(xxoverflow_discard), ++ 4, STATS_FLAGS_PORT, "rx_fw_discards" }, ++ { STATS_OFFSET32(brb_drop_hi), ++ 8, STATS_FLAGS_PORT, "rx_brb_discard" }, ++ { STATS_OFFSET32(brb_truncate_hi), ++ 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, ++ { STATS_OFFSET32(pause_frames_received_hi), ++ 8, STATS_FLAGS_PORT, "rx_pause_frames" }, ++ { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), ++ 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, ++ { STATS_OFFSET32(nig_timer_max), ++ 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, ++/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), ++ 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, ++ { STATS_OFFSET32(rx_skb_alloc_failed), ++ 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, ++ { STATS_OFFSET32(hw_csum_err), ++ 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, ++ ++ { STATS_OFFSET32(total_bytes_transmitted_hi), ++ 8, STATS_FLAGS_BOTH, "tx_bytes" }, ++ { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), ++ 8, STATS_FLAGS_PORT, "tx_error_bytes" }, ++ { STATS_OFFSET32(total_unicast_packets_transmitted_hi), ++ 8, STATS_FLAGS_BOTH, "tx_packets" }, ++ { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), ++ 8, STATS_FLAGS_PORT, "tx_mac_errors" }, ++ { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), ++ 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, + { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), + 8, STATS_FLAGS_PORT, "tx_single_collisions" }, + { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), + 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, +- { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), ++/* 30 */{ STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), + 8, STATS_FLAGS_PORT, "tx_deferred" }, + { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), + 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, +@@ -9094,14 +11326,6 @@ + 8, STATS_FLAGS_PORT, "tx_late_collisions" }, + { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), + 8, STATS_FLAGS_PORT, "tx_total_collisions" }, +- { STATS_OFFSET32(rx_stat_etherstatsfragments_hi), +- 8, STATS_FLAGS_PORT, "rx_fragments" }, +-/* 20 */{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), +- 8, STATS_FLAGS_PORT, "rx_jabbers" }, +- { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), +- 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, +- { STATS_OFFSET32(jabber_packets_received), +- 4, STATS_FLAGS_FUNC, "rx_oversize_packets" }, + { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), + 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, + { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), +@@ -9114,52 +11338,46 @@ + 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, + { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), + 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, +- { STATS_OFFSET32(etherstatspktsover1522octets_hi), ++/* 40 */{ STATS_OFFSET32(etherstatspktsover1522octets_hi), + 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, +-/* 30 */{ STATS_OFFSET32(rx_stat_xonpauseframesreceived_hi), +- 8, STATS_FLAGS_PORT, "rx_xon_frames" }, +- { STATS_OFFSET32(rx_stat_xoffpauseframesreceived_hi), +- 8, STATS_FLAGS_PORT, "rx_xoff_frames" }, +- { STATS_OFFSET32(tx_stat_outxonsent_hi), +- 8, STATS_FLAGS_PORT, "tx_xon_frames" }, +- { STATS_OFFSET32(tx_stat_outxoffsent_hi), +- 8, STATS_FLAGS_PORT, "tx_xoff_frames" }, +- { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), +- 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, +- { STATS_OFFSET32(mac_filter_discard), +- 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, +- { STATS_OFFSET32(no_buff_discard), +- 4, STATS_FLAGS_FUNC, "rx_discards" }, +- { STATS_OFFSET32(xxoverflow_discard), +- 4, STATS_FLAGS_PORT, "rx_fw_discards" }, +- { STATS_OFFSET32(brb_drop_hi), +- 8, STATS_FLAGS_PORT, "brb_discard" }, +- { STATS_OFFSET32(brb_truncate_hi), +- 8, STATS_FLAGS_PORT, "brb_truncate" }, +-/* 40 */{ STATS_OFFSET32(rx_err_discard_pkt), +- 4, STATS_FLAGS_FUNC, "rx_phy_ip_err_discards"}, +- { STATS_OFFSET32(rx_skb_alloc_failed), +- 4, STATS_FLAGS_FUNC, "rx_skb_alloc_discard" }, +-/* 42 */{ STATS_OFFSET32(hw_csum_err), +- 4, STATS_FLAGS_FUNC, "rx_csum_offload_errors" } ++ { STATS_OFFSET32(pause_frames_sent_hi), ++ 8, STATS_FLAGS_PORT, "tx_pause_frames" } + }; + +-#define IS_NOT_E1HMF_STAT(bp, i) \ +- (IS_E1HMF(bp) && (bnx2x_stats_arr[i].flags & STATS_FLAGS_PORT)) ++#define IS_PORT_STAT(i) \ ++ ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) ++#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) ++#define IS_E1HMF_MODE_STAT(bp) \ ++ (IS_E1HMF(bp) && !(bp->msglevel & BNX2X_MSG_STATS)) + + static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) + { + struct bnx2x *bp = netdev_priv(dev); +- int i, j; ++ int i, j, k; + + switch (stringset) { + case ETH_SS_STATS: +- for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { +- if (IS_NOT_E1HMF_STAT(bp, i)) +- continue; +- strcpy(buf + j*ETH_GSTRING_LEN, +- bnx2x_stats_arr[i].string); +- j++; ++ if (is_multi(bp)) { ++ k = 0; ++ for_each_rx_queue(bp, i) { ++ for (j = 0; j < BNX2X_NUM_Q_STATS; j++) ++ sprintf(buf + (k + j)*ETH_GSTRING_LEN, ++ bnx2x_q_stats_arr[j].string, i); ++ k += BNX2X_NUM_Q_STATS; ++ } ++ if (IS_E1HMF_MODE_STAT(bp)) ++ break; ++ for (j = 0; j < BNX2X_NUM_STATS; j++) ++ strcpy(buf + (k + j)*ETH_GSTRING_LEN, ++ bnx2x_stats_arr[j].string); ++ } else { ++ for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { ++ if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i)) ++ continue; ++ strcpy(buf + j*ETH_GSTRING_LEN, ++ bnx2x_stats_arr[i].string); ++ j++; ++ } + } + break; + +@@ -9172,13 +11390,22 @@ + static int bnx2x_get_stats_count(struct net_device *dev) + { + struct bnx2x *bp = netdev_priv(dev); +- int i, num_stats = 0; +- +- for (i = 0; i < BNX2X_NUM_STATS; i++) { +- if (IS_NOT_E1HMF_STAT(bp, i)) +- continue; +- num_stats++; +- } ++ int i, num_stats; ++ ++ if (is_multi(bp)) { ++ num_stats = BNX2X_NUM_Q_STATS * bp->num_rx_queues; ++ if (!IS_E1HMF_MODE_STAT(bp)) ++ num_stats += BNX2X_NUM_STATS; ++ } else { ++ if (IS_E1HMF_MODE_STAT(bp)) { ++ num_stats = 0; ++ for (i = 0; i < BNX2X_NUM_STATS; i++) ++ if (IS_FUNC_STAT(i)) ++ num_stats++; ++ } else ++ num_stats = BNX2X_NUM_STATS; ++ } ++ + return num_stats; + } + +@@ -9186,29 +11413,71 @@ + struct ethtool_stats *stats, u64 *buf) + { + struct bnx2x *bp = netdev_priv(dev); +- u32 *hw_stats = (u32 *)&bp->eth_stats; +- int i, j; +- +- for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { +- if (IS_NOT_E1HMF_STAT(bp, i)) +- continue; +- +- if (bnx2x_stats_arr[i].size == 0) { +- /* skip this counter */ +- buf[j] = 0; ++ u32 *hw_stats, *offset; ++ int i, j, k; ++ ++ if (is_multi(bp)) { ++ k = 0; ++ for_each_rx_queue(bp, i) { ++ hw_stats = (u32 *)&bp->fp[i].eth_q_stats; ++ for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { ++ if (bnx2x_q_stats_arr[j].size == 0) { ++ /* skip this counter */ ++ buf[k + j] = 0; ++ continue; ++ } ++ offset = (hw_stats + ++ bnx2x_q_stats_arr[j].offset); ++ if (bnx2x_q_stats_arr[j].size == 4) { ++ /* 4-byte counter */ ++ buf[k + j] = (u64) *offset; ++ continue; ++ } ++ /* 8-byte counter */ ++ buf[k + j] = HILO_U64(*offset, *(offset + 1)); ++ } ++ k += BNX2X_NUM_Q_STATS; ++ } ++ if (IS_E1HMF_MODE_STAT(bp)) ++ return; ++ hw_stats = (u32 *)&bp->eth_stats; ++ for (j = 0; j < BNX2X_NUM_STATS; j++) { ++ if (bnx2x_stats_arr[j].size == 0) { ++ /* skip this counter */ ++ buf[k + j] = 0; ++ continue; ++ } ++ offset = (hw_stats + bnx2x_stats_arr[j].offset); ++ if (bnx2x_stats_arr[j].size == 4) { ++ /* 4-byte counter */ ++ buf[k + j] = (u64) *offset; ++ continue; ++ } ++ /* 8-byte counter */ ++ buf[k + j] = HILO_U64(*offset, *(offset + 1)); ++ } ++ } else { ++ hw_stats = (u32 *)&bp->eth_stats; ++ for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { ++ if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i)) ++ continue; ++ if (bnx2x_stats_arr[i].size == 0) { ++ /* skip this counter */ ++ buf[j] = 0; ++ j++; ++ continue; ++ } ++ offset = (hw_stats + bnx2x_stats_arr[i].offset); ++ if (bnx2x_stats_arr[i].size == 4) { ++ /* 4-byte counter */ ++ buf[j] = (u64) *offset; ++ j++; ++ continue; ++ } ++ /* 8-byte counter */ ++ buf[j] = HILO_U64(*offset, *(offset + 1)); + j++; +- continue; +- } +- if (bnx2x_stats_arr[i].size == 4) { +- /* 4-byte counter */ +- buf[j] = (u64) *(hw_stats + bnx2x_stats_arr[i].offset); +- j++; +- continue; +- } +- /* 8-byte counter */ +- buf[j] = HILO_U64(*(hw_stats + bnx2x_stats_arr[i].offset), +- *(hw_stats + bnx2x_stats_arr[i].offset + 1)); +- j++; ++ } + } + } + +@@ -9255,13 +11524,17 @@ + .get_settings = bnx2x_get_settings, + .set_settings = bnx2x_set_settings, + .get_drvinfo = bnx2x_get_drvinfo, ++ .get_regs_len = bnx2x_get_regs_len, ++ .get_regs = bnx2x_get_regs, + .get_wol = bnx2x_get_wol, + .set_wol = bnx2x_set_wol, + .get_msglevel = bnx2x_get_msglevel, + .set_msglevel = bnx2x_set_msglevel, + .nway_reset = bnx2x_nway_reset, +- .get_link = ethtool_op_get_link, ++ .get_link = bnx2x_get_link, ++#if (LINUX_VERSION_CODE >= 0x020418) /* BNX2X_UPSTREAM */ + .get_eeprom_len = bnx2x_get_eeprom_len, ++#endif + .get_eeprom = bnx2x_get_eeprom, + .set_eeprom = bnx2x_set_eeprom, + .get_coalesce = bnx2x_get_coalesce, +@@ -9273,19 +11546,32 @@ + .get_rx_csum = bnx2x_get_rx_csum, + .set_rx_csum = bnx2x_set_rx_csum, + .get_tx_csum = ethtool_op_get_tx_csum, ++#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */ + .set_tx_csum = ethtool_op_set_tx_hw_csum, ++#else ++ .set_tx_csum = bnx2x_set_tx_hw_csum, ++#endif ++#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */ + .set_flags = bnx2x_set_flags, + .get_flags = ethtool_op_get_flags, ++#endif + .get_sg = ethtool_op_get_sg, + .set_sg = ethtool_op_set_sg, ++#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */ + .get_tso = ethtool_op_get_tso, + .set_tso = bnx2x_set_tso, ++#endif + .self_test_count = bnx2x_self_test_count, + .self_test = bnx2x_self_test, + .get_strings = bnx2x_get_strings, + .phys_id = bnx2x_phys_id, + .get_stats_count = bnx2x_get_stats_count, + .get_ethtool_stats = bnx2x_get_ethtool_stats, ++#ifdef ETHTOOL_GPERMADDR /* ! BNX2X_UPSTREAM */ ++#if (LINUX_VERSION_CODE < 0x020617) ++ .get_perm_addr = ethtool_op_get_perm_addr ++#endif ++#endif + }; + + /* end of ethtool_ops */ +@@ -9348,48 +11634,96 @@ + * net_device service functions + */ + ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ + static int bnx2x_poll(struct napi_struct *napi, int budget) +-{ ++#else ++static int bnx2x_poll(struct net_device *dev, int *budget) ++#endif ++{ ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ + struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath, + napi); + struct bnx2x *bp = fp->bp; + int work_done = 0; ++#else ++ struct bnx2x *bp = netdev_priv(dev); ++ struct bnx2x_fastpath *fp = &bp->fp[0]; ++ int orig_budget = min(*budget, dev->quota); ++ int work_done; ++#endif + + #ifdef BNX2X_STOP_ON_ERROR + if (unlikely(bp->panic)) + goto poll_panic; + #endif + +- prefetch(fp->tx_buf_ring[TX_BD(fp->tx_pkt_cons)].skb); + prefetch(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb); + prefetch((char *)(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb) + 256); + + bnx2x_update_fpsb_idx(fp); + +- if (bnx2x_has_tx_work(fp)) +- bnx2x_tx_int(fp, budget); +- +- if (bnx2x_has_rx_work(fp)) ++ if (bnx2x_has_rx_work(fp)) { ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ + work_done = bnx2x_rx_int(fp, budget); +- rmb(); /* BNX2X_HAS_WORK() reads the status block */ +- +- /* must not complete if we consumed full budget */ +- if ((work_done < budget) && !BNX2X_HAS_WORK(fp)) { +- ++ ++ /* must not complete if we consumed full budget */ ++ if (work_done >= budget) ++ goto poll_again; ++#else ++ work_done = bnx2x_rx_int(fp, orig_budget); ++ ++ *budget -= work_done; ++ dev->quota -= work_done; ++ if (dev->quota <= 0) ++ goto poll_again; ++#endif ++ } ++ ++ /* bnx2x_has_rx_work() reads the status block, thus we need to ++ * ensure that status block indices have been actually read ++ * (bnx2x_update_fpsb_idx) prior to this check (bnx2x_has_rx_work) ++ * so that we won't write the "newer" value of the status block to IGU ++ * (if there was a DMA right after bnx2x_has_rx_work and ++ * if there is no rmb, the memory reading (bnx2x_update_fpsb_idx) ++ * may be postponed to right before bnx2x_ack_sb). In this case ++ * there will never be another interrupt until there is another update ++ * of the status block, while there is still unhandled work. ++ */ ++ rmb(); ++ ++ if (!bnx2x_has_rx_work(fp)) { + #ifdef BNX2X_STOP_ON_ERROR + poll_panic: + #endif +- netif_rx_complete(bp->dev, napi); +- +- bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, ++ napi_complete(napi); ++ ++ bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID, + le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1); +- bnx2x_ack_sb(bp, FP_SB_ID(fp), CSTORM_ID, ++ bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID, + le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1); +- } ++#ifndef BNX2X_NEW_NAPI /* ! BNX2X_UPSTREAM */ ++ return 0; ++#endif ++ } ++ ++poll_again: ++#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */ + return work_done; +-} +- +- ++#else ++ return 1; ++#endif ++} ++ ++#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */ ++static struct net_device_stats *bnx2x_get_stats(struct net_device *dev) ++{ ++ struct bnx2x *bp = netdev_priv(dev); ++ ++ return &bp->net_stats; ++} ++#endif ++ ++#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */ + /* we split the first BD into headers and data BDs + * to ease the pain of our fellow microcode engineers + * we use one mapping for both BDs +@@ -9398,10 +11732,11 @@ + */ + static noinline u16 bnx2x_tx_split(struct bnx2x *bp, + struct bnx2x_fastpath *fp, +- struct eth_tx_bd **tx_bd, u16 hlen, ++ struct sw_tx_bd *tx_buf, ++ struct eth_tx_start_bd **tx_bd, u16 hlen, + u16 bd_prod, int nbd) + { +- struct eth_tx_bd *h_tx_bd = *tx_bd; ++ struct eth_tx_start_bd *h_tx_bd = *tx_bd; + struct eth_tx_bd *d_tx_bd; + dma_addr_t mapping; + int old_len = le16_to_cpu(h_tx_bd->nbytes); +@@ -9417,7 +11752,7 @@ + /* now get a new data BD + * (after the pbd) and fill it */ + bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); +- d_tx_bd = &fp->tx_desc_ring[bd_prod]; ++ d_tx_bd = &fp->tx_desc_ring[bd_prod].reg_bd; + + mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi), + le32_to_cpu(h_tx_bd->addr_lo)) + hlen; +@@ -9425,20 +11760,20 @@ + d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); + d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); + d_tx_bd->nbytes = cpu_to_le16(old_len - hlen); +- d_tx_bd->vlan = 0; +- /* this marks the BD as one that has no individual mapping +- * the FW ignores this flag in a BD not marked start +- */ +- d_tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_SW_LSO; ++ ++ /* this marks the BD as one that has no individual mapping */ ++ tx_buf->flags |= BNX2X_TSO_SPLIT_BD; ++ + DP(NETIF_MSG_TX_QUEUED, + "TSO split data size is %d (%x:%x)\n", + d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo); + +- /* update tx_bd for marking the last BD flag */ +- *tx_bd = d_tx_bd; ++ /* update tx_bd */ ++ *tx_bd = (struct eth_tx_start_bd *)d_tx_bd; + + return bd_prod; + } ++#endif + + static inline u16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix) + { +@@ -9461,7 +11796,7 @@ + rc = XMIT_PLAIN; + + else { +- if (skb->protocol == ntohs(ETH_P_IPV6)) { ++ if (skb->protocol == htons(ETH_P_IPV6)) { + rc = XMIT_CSUM_V6; + if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) + rc |= XMIT_CSUM_TCP; +@@ -9473,17 +11808,27 @@ + } + } + ++#ifdef NETIF_F_GSO /* BNX2X_UPSTREAM */ + if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) + rc |= XMIT_GSO_V4; + ++#ifdef NETIF_F_TSO6 /* BNX2X_UPSTREAM */ + else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) + rc |= XMIT_GSO_V6; ++#endif ++#elif defined(NETIF_F_TSO) /* ! BNX2X_UPSTREAM */ ++ if ((skb_shinfo(skb)->gso_size) && ++ (skb->len > (bp->dev->mtu + ETH_HLEN))) ++ rc |= XMIT_GSO_V4; ++#endif + + return rc; + } + + #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3) +-/* check if packet requires linearization (packet is too fragmented) */ ++/* check if packet requires linearization (packet is too fragmented) ++ no need to check fragmentation if page size > 8K (there will be no ++ violation to FW restrictions) */ + static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb, + u32 xmit_type) + { +@@ -9495,6 +11840,7 @@ + if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - 3)) { + + if (xmit_type & XMIT_GSO) { ++#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */ + unsigned short lso_mss = skb_shinfo(skb)->gso_size; + /* Check if LSO packet needs to be copied: + 3 = 1 (for headers BD) + 2 (for PBD and last BD) */ +@@ -9542,7 +11888,7 @@ + wnd_sum -= + skb_shinfo(skb)->frags[wnd_idx].size; + } +- ++#endif + } else { + /* in non-LSO too fragmented packet should always + be linearized */ +@@ -9550,7 +11896,9 @@ + } + } + ++#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */ + exit_lbl: ++#endif + if (unlikely(to_copy)) + DP(NETIF_MSG_TX_QUEUED, + "Linearization IS REQUIRED for %s packet. " +@@ -9562,6 +11910,36 @@ + } + #endif + ++#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */ ++static u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb) ++{ ++ struct bnx2x *bp = netdev_priv(dev); ++ int i, fp_index = 0; ++ ++ /* Determine which tx ring we will be placed on */ ++ switch (bp->multi_mode) { ++ case ETH_RSS_MODE_VLAN_PRI: ++ case ETH_RSS_MODE_E1HOV_PRI: ++#ifdef BCM_VLAN ++ if ((bp->vlgrp != NULL) && vlan_tx_tag_present(skb)) { ++ i = ((vlan_tx_tag_get(skb) >> 13) & 0x7); ++ fp_index = bp->cos_map[bp->pri_map[i]]; ++ } ++#endif ++ break; ++ ++ case ETH_RSS_MODE_IP_DSCP: ++ if (skb->protocol == htons(ETH_P_IP)) { ++ i = ((ip_hdr(skb)->tos >> 2) & 0x7); ++ fp_index = bp->cos_map[bp->pri_map[i]]; ++ } ++ break; ++ } ++ ++ return fp_index; ++} ++#endif ++ + /* called with netif_tx_lock + * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call + * netif_wake_queue() +@@ -9569,45 +11947,73 @@ + static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) + { + struct bnx2x *bp = netdev_priv(dev); +- struct bnx2x_fastpath *fp; ++ struct bnx2x_fastpath *fp, *fp_stat; ++#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */ ++ struct netdev_queue *txq; ++#endif + struct sw_tx_bd *tx_buf; +- struct eth_tx_bd *tx_bd; ++ struct eth_tx_start_bd *tx_start_bd; ++ struct eth_tx_bd *tx_data_bd, *total_pkt_bd = NULL; + struct eth_tx_parse_bd *pbd = NULL; + u16 pkt_prod, bd_prod; + int nbd, fp_index; + dma_addr_t mapping; + u32 xmit_type = bnx2x_xmit_type(bp, skb); +- int vlan_off = (bp->e1hov ? 4 : 0); + int i; + u8 hlen = 0; ++ __le16 pkt_size = 0; + + #ifdef BNX2X_STOP_ON_ERROR + if (unlikely(bp->panic)) + return NETDEV_TX_BUSY; + #endif + +- fp_index = (smp_processor_id() % bp->num_queues); +- fp = &bp->fp[fp_index]; ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) ++ VMK_ASSERT(skb->queue_mapping < BNX2X_NUM_QUEUES(bp)); ++ fp_index = skb->queue_mapping; ++ txq = netdev_get_tx_queue(dev, fp_index); ++#else /* BNX2X_UPSTREAM */ ++#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */ ++ fp_index = skb_get_queue_mapping(skb); ++ txq = netdev_get_tx_queue(dev, fp_index); ++#else ++ fp_index = 0; ++#endif ++#endif ++ ++ fp = &bp->fp[fp_index + bp->num_rx_queues]; ++ fp_stat = &bp->fp[fp_index]; + + if (unlikely(bnx2x_tx_avail(fp) < (skb_shinfo(skb)->nr_frags + 3))) { +- bp->eth_stats.driver_xoff++, ++ fp_stat->eth_q_stats.driver_xoff++; ++#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */ ++ netif_tx_stop_queue(txq); ++#else + netif_stop_queue(dev); ++#endif + BNX2X_ERR("BUG! Tx ring full when queue awake!\n"); + return NETDEV_TX_BUSY; + } + ++#ifdef NETIF_F_GSO /* BNX2X_UPSTREAM */ + DP(NETIF_MSG_TX_QUEUED, "SKB: summed %x protocol %x protocol(%x,%x)" + " gso type %x xmit_type %x\n", + skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr, + ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type); ++#endif + + #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3) +- /* First, check if we need to linearize the skb +- (due to FW restrictions) */ ++ /* First, check if we need to linearize the skb (due to FW ++ restrictions). No need to check fragmentation if page size > 8K ++ (there will be no violation to FW restrictions) */ + if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) { + /* Statistics of linearization */ + bp->lin_cnt++; ++#if (LINUX_VERSION_CODE > 0x020611) || defined(SLE_VERSION_CODE) /* BNX2X_UPSTREAM */ + if (skb_linearize(skb) != 0) { ++#else ++ if (skb_linearize(skb, GFP_ATOMIC) != 0) { ++#endif + DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - " + "silently dropping this SKB\n"); + dev_kfree_skb_any(skb); +@@ -9618,7 +12024,7 @@ + + /* + Please read carefully. First we use one BD which we mark as start, +- then for TSO or xsum we have a parsing info BD, ++ then we have a parsing info BD (used for TSO or xsum), + and only then we have the rest of the TSO BDs. + (don't forget to mark the last one as last, + and to unmap only AFTER you write to the BD ...) +@@ -9630,47 +12036,45 @@ + + /* get a tx_buf and first BD */ + tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)]; +- tx_bd = &fp->tx_desc_ring[bd_prod]; +- +- tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; +- tx_bd->general_data = (UNICAST_ADDRESS << +- ETH_TX_BD_ETH_ADDR_TYPE_SHIFT); ++ tx_start_bd = &fp->tx_desc_ring[bd_prod].start_bd; ++ ++ tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; ++ tx_start_bd->general_data = (UNICAST_ADDRESS << ++ ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT); + /* header nbd */ +- tx_bd->general_data |= (1 << ETH_TX_BD_HDR_NBDS_SHIFT); ++ tx_start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT); + + /* remember the first BD of the packet */ + tx_buf->first_bd = fp->tx_bd_prod; + tx_buf->skb = skb; ++ tx_buf->flags = 0; + + DP(NETIF_MSG_TX_QUEUED, + "sending pkt %u @%p next_idx %u bd %u @%p\n", +- pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_bd); ++ pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd); + + #ifdef BCM_VLAN + if ((bp->vlgrp != NULL) && vlan_tx_tag_present(skb) && + (bp->flags & HW_VLAN_TX_FLAG)) { +- tx_bd->vlan = cpu_to_le16(vlan_tx_tag_get(skb)); +- tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG; +- vlan_off += 4; ++ tx_start_bd->vlan = cpu_to_le16(vlan_tx_tag_get(skb)); ++ tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG; + } else + #endif +- tx_bd->vlan = cpu_to_le16(pkt_prod); +- +- if (xmit_type) { +- /* turn on parsing and get a BD */ +- bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); +- pbd = (void *)&fp->tx_desc_ring[bd_prod]; +- +- memset(pbd, 0, sizeof(struct eth_tx_parse_bd)); +- } ++ tx_start_bd->vlan = cpu_to_le16(pkt_prod); ++ ++ /* turn on parsing and get a BD */ ++ bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); ++ pbd = &fp->tx_desc_ring[bd_prod].parse_bd; ++ ++ memset(pbd, 0, sizeof(struct eth_tx_parse_bd)); + + if (xmit_type & XMIT_CSUM) { +- hlen = (skb_network_header(skb) - skb->data + vlan_off) / 2; ++ hlen = (skb_network_header(skb) - skb->data) / 2; + + /* for now NS flag is not used in Linux */ +- pbd->global_data = (hlen | +- ((skb->protocol == ntohs(ETH_P_8021Q)) << +- ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT)); ++ pbd->global_data = ++ (hlen | ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) << ++ ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT)); + + pbd->ip_hlen = (skb_transport_header(skb) - + skb_network_header(skb)) / 2; +@@ -9678,15 +12082,15 @@ + hlen += pbd->ip_hlen + tcp_hdrlen(skb) / 2; + + pbd->total_hlen = cpu_to_le16(hlen); +- hlen = hlen*2 - vlan_off; +- +- tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_TCP_CSUM; ++ hlen = hlen*2; ++ ++ tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM; + + if (xmit_type & XMIT_CSUM_V4) +- tx_bd->bd_flags.as_bitfield |= ++ tx_start_bd->bd_flags.as_bitfield |= + ETH_TX_BD_FLAGS_IP_CSUM; + else +- tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IPV6; ++ tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IPV6; + + if (xmit_type & XMIT_CSUM_TCP) { + pbd->tcp_pseudo_csum = swab16(tcp_hdr(skb)->check); +@@ -9694,13 +12098,11 @@ + } else { + s8 fix = SKB_CS_OFF(skb); /* signed! */ + +- pbd->global_data |= ETH_TX_PARSE_BD_CS_ANY_FLG; +- pbd->cs_offset = fix / 2; ++ pbd->global_data |= ETH_TX_PARSE_BD_UDP_CS_FLG; + + DP(NETIF_MSG_TX_QUEUED, +- "hlen %d offset %d fix %d csum before fix %x\n", +- le16_to_cpu(pbd->total_hlen), pbd->cs_offset, fix, +- SKB_CS(skb)); ++ "hlen %d fix %d csum before fix %x\n", ++ le16_to_cpu(pbd->total_hlen), fix, SKB_CS(skb)); + + /* HW bug: fixup the CSUM */ + pbd->tcp_pseudo_csum = +@@ -9715,18 +12117,20 @@ + mapping = pci_map_single(bp->pdev, skb->data, + skb_headlen(skb), PCI_DMA_TODEVICE); + +- tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); +- tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); +- nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL) ? 1 : 2); +- tx_bd->nbd = cpu_to_le16(nbd); +- tx_bd->nbytes = cpu_to_le16(skb_headlen(skb)); ++ tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); ++ tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); ++ nbd = skb_shinfo(skb)->nr_frags + 2; /* start_bd + pbd + frags */ ++ tx_start_bd->nbd = cpu_to_le16(nbd); ++ tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); ++ pkt_size = tx_start_bd->nbytes; + + DP(NETIF_MSG_TX_QUEUED, "first bd @%p addr (%x:%x) nbd %d" + " nbytes %d flags %x vlan %x\n", +- tx_bd, tx_bd->addr_hi, tx_bd->addr_lo, le16_to_cpu(tx_bd->nbd), +- le16_to_cpu(tx_bd->nbytes), tx_bd->bd_flags.as_bitfield, +- le16_to_cpu(tx_bd->vlan)); +- ++ tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo, ++ le16_to_cpu(tx_start_bd->nbd), le16_to_cpu(tx_start_bd->nbytes), ++ tx_start_bd->bd_flags.as_bitfield, le16_to_cpu(tx_start_bd->vlan)); ++ ++#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */ + if (xmit_type & XMIT_GSO) { + + DP(NETIF_MSG_TX_QUEUED, +@@ -9734,11 +12138,11 @@ + skb->len, hlen, skb_headlen(skb), + skb_shinfo(skb)->gso_size); + +- tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO; ++ tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO; + + if (unlikely(skb_headlen(skb) > hlen)) +- bd_prod = bnx2x_tx_split(bp, fp, &tx_bd, hlen, +- bd_prod, ++nbd); ++ bd_prod = bnx2x_tx_split(bp, fp, tx_buf, &tx_start_bd, ++ hlen, bd_prod, ++nbd); + + pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size); + pbd->tcp_send_seq = swab32(tcp_hdr(skb)->seq); +@@ -9759,33 +12163,32 @@ + + pbd->global_data |= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN; + } ++#endif ++ tx_data_bd = (struct eth_tx_bd *)tx_start_bd; + + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { + skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; + + bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); +- tx_bd = &fp->tx_desc_ring[bd_prod]; ++ tx_data_bd = &fp->tx_desc_ring[bd_prod].reg_bd; ++ if (total_pkt_bd == NULL) ++ total_pkt_bd = &fp->tx_desc_ring[bd_prod].reg_bd; + + mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset, + frag->size, PCI_DMA_TODEVICE); + +- tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); +- tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); +- tx_bd->nbytes = cpu_to_le16(frag->size); +- tx_bd->vlan = cpu_to_le16(pkt_prod); +- tx_bd->bd_flags.as_bitfield = 0; ++ tx_data_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); ++ tx_data_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); ++ tx_data_bd->nbytes = cpu_to_le16(frag->size); ++ le16_add_cpu(&pkt_size, frag->size); + + DP(NETIF_MSG_TX_QUEUED, +- "frag %d bd @%p addr (%x:%x) nbytes %d flags %x\n", +- i, tx_bd, tx_bd->addr_hi, tx_bd->addr_lo, +- le16_to_cpu(tx_bd->nbytes), tx_bd->bd_flags.as_bitfield); +- } +- +- /* now at last mark the BD as the last BD */ +- tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_END_BD; +- +- DP(NETIF_MSG_TX_QUEUED, "last bd @%p flags %x\n", +- tx_bd, tx_bd->bd_flags.as_bitfield); ++ "frag %d bd @%p addr (%x:%x) nbytes %d\n", ++ i, tx_data_bd, tx_data_bd->addr_hi, tx_data_bd->addr_lo, ++ le16_to_cpu(tx_data_bd->nbytes)); ++ } ++ ++ DP(NETIF_MSG_TX_QUEUED, "last bd @%p\n", tx_data_bd); + + bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); + +@@ -9794,6 +12197,9 @@ + */ + if (TX_BD_POFF(bd_prod) < nbd) + nbd++; ++ ++ if (total_pkt_bd != NULL) ++ total_pkt_bd->total_pkt_bytes = pkt_size; + + if (pbd) + DP(NETIF_MSG_TX_QUEUED, +@@ -9814,28 +12220,36 @@ + */ + wmb(); + +- fp->hw_tx_prods->bds_prod = +- cpu_to_le16(le16_to_cpu(fp->hw_tx_prods->bds_prod) + nbd); +- mb(); /* FW restriction: must not reorder writing nbd and packets */ +- fp->hw_tx_prods->packets_prod = +- cpu_to_le32(le32_to_cpu(fp->hw_tx_prods->packets_prod) + 1); +- DOORBELL(bp, FP_IDX(fp), 0); ++ fp->tx_db.data.prod += nbd; ++ barrier(); ++ DOORBELL(bp, fp->index - bp->num_rx_queues, fp->tx_db.raw); + + mmiowb(); + + fp->tx_bd_prod += nbd; ++#if (LINUX_VERSION_CODE < 0x02061f) /* ! BNX2X_UPSTREAM */ ++ /* In kernels starting from 2.6.31 netdev layer does this */ + dev->trans_start = jiffies; ++#endif + + if (unlikely(bnx2x_tx_avail(fp) < MAX_SKB_FRAGS + 3)) { ++#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */ ++ netif_tx_stop_queue(txq); ++#else ++ netif_stop_queue(dev); ++#endif + /* We want bnx2x_tx_int to "see" the updated tx_bd_prod + if we put Tx into XOFF state. */ + smp_mb(); +- netif_stop_queue(dev); +- bp->eth_stats.driver_xoff++; ++ fp_stat->eth_q_stats.driver_xoff++; + if (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3) ++#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */ ++ netif_tx_wake_queue(txq); ++#else + netif_wake_queue(dev); +- } +- fp->tx_pkt++; ++#endif ++ } ++ fp_stat->tx_pkt++; + + return NETDEV_TX_OK; + } +@@ -9859,14 +12273,16 @@ + + /* Unload the driver, release IRQs */ + bnx2x_nic_unload(bp, UNLOAD_CLOSE); ++#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */ + if (atomic_read(&bp->pdev->enable_cnt) == 1) ++#endif + if (!CHIP_REV_IS_SLOW(bp)) + bnx2x_set_power_state(bp, PCI_D3hot); + + return 0; + } + +-/* called with netif_tx_lock from set_multicast */ ++/* called with netif_tx_lock from dev_mcast.c */ + static void bnx2x_set_rx_mode(struct net_device *dev) + { + struct bnx2x *bp = netdev_priv(dev); +@@ -9911,8 +12327,9 @@ + cpu_to_le16(port); + config->config_table[i]. + target_table_entry.flags = 0; +- config->config_table[i]. +- target_table_entry.client_id = 0; ++ config->config_table[i].target_table_entry. ++ clients_bit_vector = ++ cpu_to_le32(1 << BP_L_ID(bp)); + config->config_table[i]. + target_table_entry.vlan_id = 0; + +@@ -9925,7 +12342,7 @@ + config->config_table[i]. + cam_entry.lsb_mac_addr); + } +- old = config->hdr.length_6b; ++ old = config->hdr.length; + if (old > i) { + for (; i < old; i++) { + if (CAM_IS_INVALID(config-> +@@ -9944,9 +12361,9 @@ + else + offset = BNX2X_MAX_MULTICAST*(1 + port); + +- config->hdr.length_6b = i; ++ config->hdr.length = i; + config->hdr.offset = offset; +- config->hdr.client_id = BP_CL_ID(bp); ++ config->hdr.client_id = bp->fp->cl_id; + config->hdr.reserved1 = 0; + + bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, +@@ -9966,11 +12383,16 @@ + mclist && (i < dev->mc_count); + i++, mclist = mclist->next) { + ++#if (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */ ++ DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n", ++ mclist->dmi_addr); ++#else + DP(NETIF_MSG_IFUP, "Adding mcast MAC: " + "%02x:%02x:%02x:%02x:%02x:%02x\n", + mclist->dmi_addr[0], mclist->dmi_addr[1], + mclist->dmi_addr[2], mclist->dmi_addr[3], + mclist->dmi_addr[4], mclist->dmi_addr[5]); ++#endif + + crc = crc32c_le(0, mclist->dmi_addr, ETH_ALEN); + bit = (crc >> 24) & 0xff; +@@ -10010,54 +12432,77 @@ + } + + /* called with rtnl_lock */ ++static int bnx2x_mdio_read(struct net_device *netdev, int prtad, ++ int devad, u16 addr) ++{ ++ struct bnx2x *bp = netdev_priv(netdev); ++ u16 value; ++ int rc; ++ u32 phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); ++ ++ DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", ++ prtad, devad, addr); ++ ++ if (prtad != bp->mdio.prtad) { ++ DP(NETIF_MSG_LINK, "prtad missmatch (cmd:0x%x != bp:0x%x)\n", ++ prtad, bp->mdio.prtad); ++ return -EINVAL; ++ } ++ ++ /* The HW expects different devad if CL22 is used */ ++ devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; ++ ++ bnx2x_acquire_phy_lock(bp); ++ rc = bnx2x_cl45_read(bp, BP_PORT(bp), phy_type, prtad, ++ devad, addr, &value); ++ bnx2x_release_phy_lock(bp); ++ DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); ++ ++ if (!rc) ++ rc = value; ++ return rc; ++} ++ ++/* called with rtnl_lock */ ++static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, ++ u16 addr, u16 value) ++{ ++ struct bnx2x *bp = netdev_priv(netdev); ++ u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); ++ int rc; ++ ++ DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," ++ " value 0x%x\n", prtad, devad, addr, value); ++ ++ if (prtad != bp->mdio.prtad) { ++ DP(NETIF_MSG_LINK, "prtad missmatch (cmd:0x%x != bp:0x%x)\n", ++ prtad, bp->mdio.prtad); ++ return -EINVAL; ++ } ++ ++ /* The HW expects different devad if CL22 is used */ ++ devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; ++ ++ bnx2x_acquire_phy_lock(bp); ++ rc = bnx2x_cl45_write(bp, BP_PORT(bp), ext_phy_type, prtad, ++ devad, addr, value); ++ bnx2x_release_phy_lock(bp); ++ return rc; ++} ++ ++/* called with rtnl_lock */ + static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) + { +- struct mii_ioctl_data *data = if_mii(ifr); +- struct bnx2x *bp = netdev_priv(dev); +- int port = BP_PORT(bp); +- int err; +- +- switch (cmd) { +- case SIOCGMIIPHY: +- data->phy_id = bp->port.phy_addr; +- +- /* fallthrough */ +- +- case SIOCGMIIREG: { +- u16 mii_regval; +- +- if (!netif_running(dev)) +- return -EAGAIN; +- +- mutex_lock(&bp->port.phy_mutex); +- err = bnx2x_cl45_read(bp, port, 0, bp->port.phy_addr, +- DEFAULT_PHY_DEV_ADDR, +- (data->reg_num & 0x1f), &mii_regval); +- data->val_out = mii_regval; +- mutex_unlock(&bp->port.phy_mutex); +- return err; +- } +- +- case SIOCSMIIREG: +- if (!capable(CAP_NET_ADMIN)) +- return -EPERM; +- +- if (!netif_running(dev)) +- return -EAGAIN; +- +- mutex_lock(&bp->port.phy_mutex); +- err = bnx2x_cl45_write(bp, port, 0, bp->port.phy_addr, +- DEFAULT_PHY_DEV_ADDR, +- (data->reg_num & 0x1f), data->val_in); +- mutex_unlock(&bp->port.phy_mutex); +- return err; +- +- default: +- /* do nothing */ +- break; +- } +- +- return -EOPNOTSUPP; ++ struct bnx2x *bp = netdev_priv(dev); ++ struct mii_ioctl_data *mdio = if_mii(ifr); ++ ++ DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", ++ mdio->phy_id, mdio->reg_num, mdio->val_in); ++ ++ if (!netif_running(dev)) ++ return -EAGAIN; ++ ++ return mdio_mii_ioctl(&bp->mdio, mdio, cmd); + } + + /* called with rtnl_lock */ +@@ -10118,6 +12563,15 @@ + bnx2x_set_client_config(bp); + } + ++#if (LINUX_VERSION_CODE < 0x020616) /* ! BNX2X_UPSTREAM */ ++static void bnx2x_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid) ++{ ++ struct bnx2x *bp = netdev_priv(dev); ++ ++ if (bp->vlgrp) ++ vlan_group_set_device(bp->vlgrp, vid, NULL); ++} ++#endif + #endif + + #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) +@@ -10126,9 +12580,33 @@ + struct bnx2x *bp = netdev_priv(dev); + + disable_irq(bp->pdev->irq); ++#if (LINUX_VERSION_CODE < 0x020613) && (VMWARE_ESX_DDK_VERSION < 40000) ++ bnx2x_interrupt(bp->pdev->irq, dev, NULL); ++#else /* BNX2X_UPSTREAM */ + bnx2x_interrupt(bp->pdev->irq, dev); ++#endif + enable_irq(bp->pdev->irq); + } ++#endif ++ ++#if (LINUX_VERSION_CODE >= 0x02061e) /* BNX2X_UPSTREAM */ ++static const struct net_device_ops bnx2x_netdev_ops = { ++ .ndo_open = bnx2x_open, ++ .ndo_stop = bnx2x_close, ++ .ndo_start_xmit = bnx2x_start_xmit, ++ .ndo_set_multicast_list = bnx2x_set_rx_mode, ++ .ndo_set_mac_address = bnx2x_change_mac_addr, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_do_ioctl = bnx2x_ioctl, ++ .ndo_change_mtu = bnx2x_change_mtu, ++ .ndo_tx_timeout = bnx2x_tx_timeout, ++#ifdef BCM_VLAN ++ .ndo_vlan_rx_register = bnx2x_vlan_rx_register, ++#endif ++#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) ++ .ndo_poll_controller = poll_bnx2x, ++#endif ++}; + #endif + + static int __devinit bnx2x_init_dev(struct pci_dev *pdev, +@@ -10137,7 +12615,12 @@ + struct bnx2x *bp; + int rc; + ++#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */ ++ SET_MODULE_OWNER(dev); ++#endif ++#if (LINUX_VERSION_CODE >= 0x020419) /* BNX2X_UPSTREAM */ + SET_NETDEV_DEV(dev, &pdev->dev); ++#endif + bp = netdev_priv(dev); + + bp->dev = dev; +@@ -10165,7 +12648,9 @@ + goto err_out_disable; + } + ++#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */ + if (atomic_read(&pdev->enable_cnt) == 1) { ++#endif + rc = pci_request_regions(pdev, DRV_MODULE_NAME); + if (rc) { + printk(KERN_ERR PFX "Cannot obtain PCI resources," +@@ -10174,8 +12659,14 @@ + } + + pci_set_master(pdev); ++#if (LINUX_VERSION_CODE >= 0x02060b) /* BNX2X_UPSTREAM */ + pci_save_state(pdev); +- } ++#else ++ pci_save_state(pdev, bp->pci_state); ++#endif ++#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */ ++ } ++#endif + + bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); + if (bp->pm_cap == 0) { +@@ -10193,16 +12684,16 @@ + goto err_out_release; + } + +- if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) { ++ if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) { + bp->flags |= USING_DAC_FLAG; +- if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) { ++ if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) { + printk(KERN_ERR PFX "pci_set_consistent_dma_mask" + " failed, aborting\n"); + rc = -EIO; + goto err_out_release; + } + +- } else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) { ++ } else if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) { + printk(KERN_ERR PFX "System does not support DMA," + " aborting\n"); + rc = -EIO; +@@ -10215,8 +12706,12 @@ + + dev->irq = pdev->irq; + ++#if (LINUX_VERSION_CODE >= 0x02061c) /* BNX2X_UPSTREAM */ ++ bp->regview = pci_ioremap_bar(pdev, 0); ++#else + bp->regview = ioremap_nocache(dev->base_addr, + pci_resource_len(pdev, 0)); ++#endif + if (!bp->regview) { + printk(KERN_ERR PFX "Cannot map register space, aborting\n"); + rc = -ENOMEM; +@@ -10242,10 +12737,23 @@ + REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0); + REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0); + ++#if (LINUX_VERSION_CODE < 0x02061e) /* ! BNX2X_UPSTREAM */ ++#ifndef BNX2X_NEW_NAPI /* ! BNX2X_UPSTREAM */ ++ dev->poll = bnx2x_poll; ++ dev->weight = 128*4; ++#endif ++#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */ ++ dev->get_stats = bnx2x_get_stats; ++#endif + dev->hard_start_xmit = bnx2x_start_xmit; ++#endif + dev->watchdog_timeo = TX_TIMEOUT; + ++#if (LINUX_VERSION_CODE >= 0x02061e) /* BNX2X_UPSTREAM */ ++ dev->netdev_ops = &bnx2x_netdev_ops; ++#endif + dev->ethtool_ops = &bnx2x_ethtool_ops; ++#if (LINUX_VERSION_CODE < 0x02061e) /* ! BNX2X_UPSTREAM */ + dev->open = bnx2x_open; + dev->stop = bnx2x_close; + dev->set_multicast_list = bnx2x_set_rx_mode; +@@ -10255,20 +12763,45 @@ + dev->tx_timeout = bnx2x_tx_timeout; + #ifdef BCM_VLAN + dev->vlan_rx_register = bnx2x_vlan_rx_register; ++#if (LINUX_VERSION_CODE < 0x020616) /* ! BNX2X_UPSTREAM */ ++ dev->vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid; ++#endif + #endif + #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) + dev->poll_controller = poll_bnx2x; ++#endif + #endif + dev->features |= NETIF_F_SG; + dev->features |= NETIF_F_HW_CSUM; + if (bp->flags & USING_DAC_FLAG) + dev->features |= NETIF_F_HIGHDMA; ++#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */ ++ dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN); ++#endif ++#ifdef NETIF_F_TSO6 /* BNX2X_UPSTREAM */ ++ dev->features |= NETIF_F_TSO6; ++#endif + #ifdef BCM_VLAN + dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX); + bp->flags |= (HW_VLAN_RX_FLAG | HW_VLAN_TX_FLAG); +-#endif +- dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN); +- dev->features |= NETIF_F_TSO6; ++ ++#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */ ++ dev->vlan_features |= NETIF_F_SG; ++ dev->vlan_features |= NETIF_F_HW_CSUM; ++ if (bp->flags & USING_DAC_FLAG) ++ dev->vlan_features |= NETIF_F_HIGHDMA; ++ dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN); ++ dev->vlan_features |= NETIF_F_TSO6; ++#endif ++#endif ++ ++ /* get_port_hwinfo() will set prtad and mmds properly */ ++ bp->mdio.prtad = MDIO_PRTAD_NONE; ++ bp->mdio.mmds = 0; ++ bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; ++ bp->mdio.dev = dev; ++ bp->mdio.mdio_read = bnx2x_mdio_read; ++ bp->mdio.mdio_write = bnx2x_mdio_write; + + return 0; + +@@ -10283,7 +12816,9 @@ + } + + err_out_release: ++#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */ + if (atomic_read(&pdev->enable_cnt) == 1) ++#endif + pci_release_regions(pdev); + + err_out_disable: +@@ -10294,37 +12829,239 @@ + return rc; + } + +-static int __devinit bnx2x_get_pcie_width(struct bnx2x *bp) ++static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, ++ int *width, int *speed) + { + u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); + +- val = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; +- return val; +-} +- +-/* return value of 1=2.5GHz 2=5GHz */ +-static int __devinit bnx2x_get_pcie_speed(struct bnx2x *bp) +-{ +- u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); +- +- val = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; +- return val; +-} ++ *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; ++ ++ /* return value of 1=2.5GHz 2=5GHz */ ++ *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; ++} ++ ++#if defined(BNX2X_UPSTREAM) && !defined(BNX2X_USE_INIT_VALUES) /* BNX2X_UPSTREAM */ ++static int __devinit bnx2x_check_firmware(struct bnx2x *bp) ++{ ++ const struct firmware *firmware = bp->firmware; ++ struct bnx2x_fw_file_hdr *fw_hdr; ++ struct bnx2x_fw_file_section *sections; ++ u32 offset, len, num_ops; ++ u16 *ops_offsets; ++ int i; ++ const u8 *fw_ver; ++ ++ if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) ++ return -EINVAL; ++ ++ fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; ++ sections = (struct bnx2x_fw_file_section *)fw_hdr; ++ ++ /* Make sure none of the offsets and sizes make us read beyond ++ * the end of the firmware data */ ++ for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { ++ offset = be32_to_cpu(sections[i].offset); ++ len = be32_to_cpu(sections[i].len); ++ if (offset + len > firmware->size) { ++ printk(KERN_ERR PFX "Section %d length is out of " ++ "bounds\n", i); ++ return -EINVAL; ++ } ++ } ++ ++ /* Likewise for the init_ops offsets */ ++ offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); ++ ops_offsets = (u16 *)(firmware->data + offset); ++ num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); ++ ++ for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { ++ if (be16_to_cpu(ops_offsets[i]) > num_ops) { ++ printk(KERN_ERR PFX "Section offset %d is out of " ++ "bounds\n", i); ++ return -EINVAL; ++ } ++ } ++ ++ /* Check FW version */ ++ offset = be32_to_cpu(fw_hdr->fw_version.offset); ++ fw_ver = firmware->data + offset; ++ if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || ++ (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || ++ (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || ++ (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { ++ printk(KERN_ERR PFX "Bad FW version:%d.%d.%d.%d." ++ " Should be %d.%d.%d.%d\n", ++ fw_ver[0], fw_ver[1], fw_ver[2], ++ fw_ver[3], BCM_5710_FW_MAJOR_VERSION, ++ BCM_5710_FW_MINOR_VERSION, ++ BCM_5710_FW_REVISION_VERSION, ++ BCM_5710_FW_ENGINEERING_VERSION); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) ++{ ++ const __be32 *source = (const __be32 *)_source; ++ u32 *target = (u32 *)_target; ++ u32 i; ++ ++ for (i = 0; i < n/4; i++) ++ target[i] = be32_to_cpu(source[i]); ++} ++ ++/* ++ Ops array is stored in the following format: ++ {op(8bit), offset(24bit, big endian), data(32bit, big endian)} ++ */ ++static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) ++{ ++ const __be32 *source = (const __be32 *)_source; ++ struct raw_op *target = (struct raw_op *)_target; ++ u32 i, j, tmp; ++ ++ for (i = 0, j = 0; i < n/8; i++, j += 2) { ++ tmp = be32_to_cpu(source[j]); ++ target[i].op = (tmp >> 24) & 0xff; ++ target[i].offset = tmp & 0xffffff; ++ target[i].raw_data = be32_to_cpu(source[j+1]); ++ } ++} ++ ++static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) ++{ ++ const __be16 *source = (const __be16 *)_source; ++ u16 *target = (u16 *)_target; ++ u32 i; ++ ++ for (i = 0; i < n/2; i++) ++ target[i] = be16_to_cpu(source[i]); ++} ++ ++#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ ++ do { \ ++ u32 len = be32_to_cpu(fw_hdr->arr.len); \ ++ bp->arr = kmalloc(len, GFP_KERNEL); \ ++ if (!bp->arr) { \ ++ printk(KERN_ERR PFX "Failed to allocate %d bytes " \ ++ "for "#arr"\n", len); \ ++ goto lbl; \ ++ } \ ++ func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ ++ (u8 *)bp->arr, len); \ ++ } while (0) ++ ++static int __devinit bnx2x_init_firmware(struct bnx2x *bp, struct device *dev) ++{ ++ char fw_file_name[40] = {0}; ++ struct bnx2x_fw_file_hdr *fw_hdr; ++ int rc, offset; ++ ++ /* Create a FW file name */ ++ if (CHIP_IS_E1(bp)) ++ offset = sprintf(fw_file_name, FW_FILE_PREFIX_E1); ++ else ++ offset = sprintf(fw_file_name, FW_FILE_PREFIX_E1H); ++ ++ sprintf(fw_file_name + offset, "%d.%d.%d.%d.fw", ++ BCM_5710_FW_MAJOR_VERSION, ++ BCM_5710_FW_MINOR_VERSION, ++ BCM_5710_FW_REVISION_VERSION, ++ BCM_5710_FW_ENGINEERING_VERSION); ++ ++ printk(KERN_INFO PFX "Loading %s\n", fw_file_name); ++ ++ rc = request_firmware(&bp->firmware, fw_file_name, dev); ++ if (rc) { ++ printk(KERN_ERR PFX "Can't load firmware file %s\n", ++ fw_file_name); ++ goto request_firmware_exit; ++ } ++ ++ rc = bnx2x_check_firmware(bp); ++ if (rc) { ++ printk(KERN_ERR PFX "Corrupt firmware file %s\n", fw_file_name); ++ goto request_firmware_exit; ++ } ++ ++ fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; ++ ++ /* Initialize the pointers to the init arrays */ ++ /* Blob */ ++ BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); ++ ++ /* Opcodes */ ++ BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); ++ ++ /* Offsets */ ++ BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, ++ be16_to_cpu_n); ++ ++ /* STORMs firmware */ ++ INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + ++ be32_to_cpu(fw_hdr->tsem_int_table_data.offset); ++ INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + ++ be32_to_cpu(fw_hdr->tsem_pram_data.offset); ++ INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + ++ be32_to_cpu(fw_hdr->usem_int_table_data.offset); ++ INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + ++ be32_to_cpu(fw_hdr->usem_pram_data.offset); ++ INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + ++ be32_to_cpu(fw_hdr->xsem_int_table_data.offset); ++ INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + ++ be32_to_cpu(fw_hdr->xsem_pram_data.offset); ++ INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + ++ be32_to_cpu(fw_hdr->csem_int_table_data.offset); ++ INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + ++ be32_to_cpu(fw_hdr->csem_pram_data.offset); ++ ++ return 0; ++ ++init_offsets_alloc_err: ++ kfree(bp->init_ops); ++init_ops_alloc_err: ++ kfree(bp->init_data); ++request_firmware_exit: ++ release_firmware(bp->firmware); ++ ++ return rc; ++} ++ ++#else ++ ++static int __devinit bnx2x_init_firmware(struct bnx2x *bp, struct device *dev) ++{ ++ if (CHIP_IS_E1(bp)) ++ bnx2x_init_e1_firmware(bp); ++ ++ else if (CHIP_IS_E1H(bp)) ++ bnx2x_init_e1h_firmware(bp); ++ ++ else { ++ printk(KERN_ERR PFX "Unsupported chip revision\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++#endif + + static int __devinit bnx2x_init_one(struct pci_dev *pdev, + const struct pci_device_id *ent) + { +- static int version_printed; + struct net_device *dev = NULL; + struct bnx2x *bp; +- int rc; +- DECLARE_MAC_BUF(mac); +- +- if (version_printed++ == 0) +- printk(KERN_INFO "%s", version); ++ int pcie_width, pcie_speed; ++ int rc; + + /* dev zeroed in init_etherdev */ ++#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */ ++ dev = alloc_etherdev_mq(sizeof(*bp), MAX_CONTEXT); ++#else + dev = alloc_etherdev(sizeof(*bp)); ++#endif + if (!dev) { + printk(KERN_ERR PFX "Cannot allocate net device\n"); + return -ENOMEM; +@@ -10332,6 +13069,8 @@ + + bp = netdev_priv(dev); + bp->msglevel = debug; ++ ++ pci_set_drvdata(pdev, dev); + + rc = bnx2x_init_dev(pdev, dev); + if (rc < 0) { +@@ -10339,11 +13078,16 @@ + return rc; + } + +- pci_set_drvdata(pdev, dev); +- + rc = bnx2x_init_bp(bp); + if (rc) + goto init_one_exit; ++ ++ /* Set init arrays */ ++ rc = bnx2x_init_firmware(bp, &pdev->dev); ++ if (rc) { ++ printk(KERN_ERR PFX "Error loading firmware\n"); ++ goto init_one_exit; ++ } + + rc = register_netdev(dev); + if (rc) { +@@ -10351,14 +13095,29 @@ + goto init_one_exit; + } + +- bp->common.name = board_info[ent->driver_data].name; ++ bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); + printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx," +- " IRQ %d, ", dev->name, bp->common.name, ++ " IRQ %d, ", dev->name, board_info[ent->driver_data].name, + (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), +- bnx2x_get_pcie_width(bp), +- (bnx2x_get_pcie_speed(bp) == 2) ? "5GHz (Gen2)" : "2.5GHz", ++ pcie_width, (pcie_speed == 2) ? "5GHz (Gen2)" : "2.5GHz", + dev->base_addr, bp->pdev->irq); +- printk(KERN_CONT "node addr %s\n", print_mac(mac, dev->dev_addr)); ++#if (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */ ++ printk(KERN_CONT "node addr %pM\n", dev->dev_addr); ++#else ++ printk(KERN_CONT "node addr "); ++ { ++ int i; ++ ++ for (i = 0; i < ETH_ALEN; i++) ++ printk(KERN_CONT "%2.2x", dev->dev_addr[i]); ++ } ++ printk(KERN_CONT "\n"); ++#endif ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */ ++ VMKNETDDI_REGISTER_QUEUEOPS(dev, bnx2x_netqueue_ops); ++ printk(KERN_INFO "VMware NetQueue Ops is registered for bnx2x\n"); ++#endif ++ + return 0; + + init_one_exit: +@@ -10370,7 +13129,9 @@ + + free_netdev(dev); + ++#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */ + if (atomic_read(&pdev->enable_cnt) == 1) ++#endif + pci_release_regions(pdev); + + pci_disable_device(pdev); +@@ -10390,7 +13151,17 @@ + } + bp = netdev_priv(dev); + ++#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */ ++ flush_scheduled_work(); ++#endif + unregister_netdev(dev); ++ ++#if defined(BNX2X_UPSTREAM) && !defined(BNX2X_USE_INIT_VALUES) /* BNX2X_UPSTREAM */ ++ kfree(bp->init_ops_offsets); ++ kfree(bp->init_ops); ++ kfree(bp->init_data); ++ release_firmware(bp->firmware); ++#endif + + if (bp->regview) + iounmap(bp->regview); +@@ -10400,7 +13171,9 @@ + + free_netdev(dev); + ++#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */ + if (atomic_read(&pdev->enable_cnt) == 1) ++#endif + pci_release_regions(pdev); + + pci_disable_device(pdev); +@@ -10420,13 +13193,20 @@ + + rtnl_lock(); + ++#if (LINUX_VERSION_CODE >= 0x02060b) /* BNX2X_UPSTREAM */ + pci_save_state(pdev); ++#else ++ pci_save_state(pdev, bp->pci_state); ++#endif + + if (!netif_running(dev)) { + rtnl_unlock(); + return 0; + } + ++#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */ ++ flush_scheduled_work(); ++#endif + netif_device_detach(dev); + + bnx2x_nic_unload(bp, UNLOAD_CLOSE); +@@ -10452,7 +13232,11 @@ + + rtnl_lock(); + ++#if (LINUX_VERSION_CODE >= 0x02060b) /* BNX2X_UPSTREAM */ + pci_restore_state(pdev); ++#else ++ pci_restore_state(pdev, bp->pci_state); ++#endif + + if (!netif_running(dev)) { + rtnl_unlock(); +@@ -10469,6 +13253,7 @@ + return rc; + } + ++#if (LINUX_VERSION_CODE >= 0x02060b) && !defined(__VMKLNX__) /* BNX2X_UPSTREAM */ + static int bnx2x_eeh_nic_unload(struct bnx2x *bp) + { + int i; +@@ -10490,16 +13275,18 @@ + struct mac_configuration_cmd *config = + bnx2x_sp(bp, mcast_config); + +- for (i = 0; i < config->hdr.length_6b; i++) ++ for (i = 0; i < config->hdr.length; i++) + CAM_INVALIDATE(config->config_table[i]); + } + + /* Free SKBs, SGEs, TPA pool and driver internals */ + bnx2x_free_skbs(bp); +- for_each_queue(bp, i) ++ for_each_rx_queue(bp, i) + bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); +- for_each_queue(bp, i) ++#if defined(BNX2X_NEW_NAPI) && (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */ ++ for_each_rx_queue(bp, i) + netif_napi_del(&bnx2x_fp(bp, i, napi)); ++#endif + bnx2x_free_mem(bp); + + bp->state = BNX2X_STATE_CLOSED; +@@ -10625,9 +13412,10 @@ + + static struct pci_error_handlers bnx2x_err_handler = { + .error_detected = bnx2x_io_error_detected, +- .slot_reset = bnx2x_io_slot_reset, +- .resume = bnx2x_io_resume, ++ .slot_reset = bnx2x_io_slot_reset, ++ .resume = bnx2x_io_resume, + }; ++#endif + + static struct pci_driver bnx2x_pci_driver = { + .name = DRV_MODULE_NAME, +@@ -10636,18 +13424,35 @@ + .remove = __devexit_p(bnx2x_remove_one), + .suspend = bnx2x_suspend, + .resume = bnx2x_resume, ++#if (LINUX_VERSION_CODE >= 0x02060b) && !defined(__VMKLNX__) /* BNX2X_UPSTREAM */ + .err_handler = &bnx2x_err_handler, ++#endif + }; + + static int __init bnx2x_init(void) + { ++ int rc; ++ ++ printk(KERN_INFO "%s", version); ++ + bnx2x_wq = create_singlethread_workqueue("bnx2x"); + if (bnx2x_wq == NULL) { + printk(KERN_ERR PFX "Cannot create workqueue\n"); + return -ENOMEM; + } + +- return pci_register_driver(&bnx2x_pci_driver); ++#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */ ++ rc = pci_register_driver(&bnx2x_pci_driver); ++#else ++ rc = pci_module_init(&bnx2x_pci_driver); ++#endif ++#if (LINUX_VERSION_CODE >= 0x02060a) /* BNX2X_UPSTREAM */ ++ if (rc) { ++ printk(KERN_ERR PFX "Cannot register driver\n"); ++ destroy_workqueue(bnx2x_wq); ++ } ++#endif ++ return rc; + } + + static void __exit bnx2x_cleanup(void) +@@ -10660,3 +13465,727 @@ + module_init(bnx2x_init); + module_exit(bnx2x_cleanup); + ++#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */ ++ ++/* count denotes the number of new completions we have seen */ ++static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) ++{ ++ int func = BP_FUNC(bp); ++ ++#ifdef BNX2X_STOP_ON_ERROR ++ if (unlikely(bp->panic)) ++ return; ++#endif ++ ++ spin_lock_bh(&bp->spq_lock); ++ bp->cnic_spq_pending -= count; ++ ++ for (; bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending; ++ bp->cnic_spq_pending++) { ++ ++ if (!bp->cnic_kwq_pending) ++ break; ++ ++ *bp->spq_prod_bd = *bp->cnic_kwq_cons; ++ ++ bp->cnic_kwq_pending--; ++ ++ DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", ++ bp->cnic_spq_pending, bp->cnic_kwq_pending, count); ++ ++ if (bp->spq_prod_bd == bp->spq_last_bd) { ++ bp->spq_prod_bd = bp->spq; ++ bp->spq_prod_idx = 0; ++ DP(NETIF_MSG_TIMER, "end of spq\n"); ++ ++ } else { ++ bp->spq_prod_bd++; ++ bp->spq_prod_idx++; ++ } ++ ++ if (bp->cnic_kwq_cons == bp->cnic_kwq_last) ++ bp->cnic_kwq_cons = bp->cnic_kwq; ++ else ++ bp->cnic_kwq_cons++; ++ } ++ ++ REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), ++ bp->spq_prod_idx); ++ ++ spin_unlock_bh(&bp->spq_lock); ++} ++ ++static int bnx2x_cnic_sp_queue(struct net_device *dev, ++ struct kwqe_16 *kwqes[], u32 count) ++{ ++ struct bnx2x *bp = netdev_priv(dev); ++ int i; ++ ++#ifdef BNX2X_STOP_ON_ERROR ++ if (unlikely(bp->panic)) ++ return -EIO; ++#endif ++ ++ spin_lock_bh(&bp->spq_lock); ++ ++ for (i = 0; i < count; i++) { ++ struct eth_spe *spe = (struct eth_spe *)kwqes[i]; ++ ++ if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) ++ break; ++ ++ *bp->cnic_kwq_prod = *spe; ++ ++ bp->cnic_kwq_pending++; ++ ++ DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", ++ spe->hdr.conn_and_cmd_data, spe->hdr.type, ++ spe->data.mac_config_addr.hi, ++ spe->data.mac_config_addr.lo, ++ bp->cnic_kwq_pending); ++ ++ if (bp->cnic_kwq_prod == bp->cnic_kwq_last) ++ bp->cnic_kwq_prod = bp->cnic_kwq; ++ else ++ bp->cnic_kwq_prod++; ++ } ++ ++ spin_unlock_bh(&bp->spq_lock); ++ ++ if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) ++ bnx2x_cnic_sp_post(bp, 0); ++ ++ return i; ++} ++ ++static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) ++{ ++ struct cnic_ops *c_ops; ++ int rc = 0; ++ ++ rcu_read_lock(); ++ c_ops = rcu_dereference(bp->cnic_ops); ++ if (c_ops) ++ rc = c_ops->cnic_ctl(bp->cnic_data, ctl); ++ rcu_read_unlock(); ++ ++ /* since for now we don't handle send failure just tell the user */ ++ if (rc) ++ BNX2X_ERR("sending cmd %x returned %d\n", ctl->cmd, rc); ++ ++ return rc; ++} ++ ++/* ++ * for commands that have no data ++ */ ++static int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) ++{ ++ struct cnic_ctl_info ctl = {0}; ++ ++ ctl.cmd = cmd; ++ ++ return bnx2x_cnic_ctl_send(bp, &ctl); ++} ++ ++static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid) ++{ ++ struct cnic_ctl_info ctl; ++ ++ /* first we tell CNIC and only then we count this as a completion */ ++ ctl.cmd = CNIC_CTL_COMPLETION_CMD; ++ ctl.data.comp.cid = cid; ++ ++ bnx2x_cnic_ctl_send(bp, &ctl); ++ bnx2x_cnic_sp_post(bp, 1); ++} ++ ++static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) ++{ ++ struct bnx2x *bp = netdev_priv(dev); ++ ++ switch (ctl->cmd) { ++ case DRV_CTL_CTXTBL_WR_CMD: ++ { ++ u32 index = ctl->data.io.offset; ++ dma_addr_t addr = ctl->data.io.dma_addr; ++ ++ bnx2x_ilt_wr(bp, index, addr); ++ return 0; ++ } ++ break; ++ ++ case DRV_CTL_COMPLETION_CMD: ++ { ++ int count = ctl->data.comp.comp_count; ++ ++ bnx2x_cnic_sp_post(bp, count); ++ return 0; ++ } ++ break; ++ ++ default: ++ BNX2X_ERR("unknown command %x\n", ctl->cmd); ++ return -EINVAL; ++ } ++} ++ ++static void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) ++{ ++ struct cnic_eth_dev *cp = &bp->cnic_eth_dev; ++ ++#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */ ++ if (bp->flags & USING_MSIX_FLAG) { ++ cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; ++ cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; ++ cp->irq_arr[0].vector = bp->msix_table[1].vector; ++ } else { ++#else ++ { ++#endif ++ cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; ++ cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; ++ } ++ cp->irq_arr[0].status_blk = bp->cnic_sb; ++ cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp); ++ ++ cp->num_irq = 1; ++} ++ ++static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, ++ void *data) ++{ ++ struct bnx2x *bp = netdev_priv(dev); ++ struct cnic_eth_dev *cp = &bp->cnic_eth_dev; ++ ++ if (ops == NULL) ++ return -EINVAL; ++ ++#if !defined(__VMKLNX__) ++ if (!try_module_get(ops->cnic_owner)) ++ return -EBUSY; ++#endif ++ ++ if (atomic_read(&bp->intr_sem) != 0) ++ return -EBUSY; ++ ++ bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); ++ if (!bp->cnic_kwq) ++ return -ENOMEM; ++ ++ bp->cnic_kwq_cons = bp->cnic_kwq; ++ bp->cnic_kwq_prod = bp->cnic_kwq; ++ bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; ++ ++ bp->cnic_spq_pending = 0; ++ bp->cnic_kwq_pending = 0; ++ ++ bp->cnic_data = data; ++ rcu_assign_pointer(bp->cnic_ops, ops); ++ ++ cp->num_irq = 0; ++ cp->drv_state = CNIC_DRV_STATE_REGD; ++ ++ bnx2x_init_sb(bp, bp->cnic_sb, bp->cnic_sb_mapping, CNIC_SB_ID(bp)); ++ ++ bnx2x_setup_cnic_irq_info(bp); ++ ++ return 0; ++} ++ ++static int bnx2x_unregister_cnic(struct net_device *dev) ++{ ++ struct bnx2x *bp = netdev_priv(dev); ++ struct cnic_eth_dev *cp = &bp->cnic_eth_dev; ++ ++ cp->drv_state = 0; ++#if !defined(__VMKLNX__) ++ module_put(bp->cnic_ops->cnic_owner); ++#endif ++ rcu_assign_pointer(bp->cnic_ops, NULL); ++#if !defined(__VMKLNX__) ++ synchronize_rcu(); ++#endif ++ kfree(bp->cnic_kwq); ++ ++ return 0; ++} ++ ++struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) ++{ ++ struct bnx2x *bp = netdev_priv(dev); ++ struct cnic_eth_dev *cp = &bp->cnic_eth_dev; ++ ++ cp->drv_owner = THIS_MODULE; ++ cp->chip_id = CHIP_ID(bp); ++ cp->pdev = bp->pdev; ++ cp->io_base = bp->regview; ++ cp->max_kwqe_pending = 8; ++ cp->ctx_blk_size = CNIC_CTX_PER_ILT * sizeof(union cdu_context); ++ cp->ctx_tbl_offset = FUNC_ILT_BASE(bp->func) + 1; ++ cp->ctx_tbl_len = CNIC_ILT_LINES; ++ cp->starting_cid = 16; ++ cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; ++ cp->drv_ctl = bnx2x_drv_ctl; ++ cp->drv_register_cnic = bnx2x_register_cnic; ++ cp->drv_unregister_cnic = bnx2x_unregister_cnic; ++ ++ return cp; ++} ++EXPORT_SYMBOL(bnx2x_cnic_probe); ++ ++#endif /* BCM_CNIC */ ++ ++#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */ ++ ++static int bnx2x_get_netqueue_features(vmknetddi_queueop_get_features_args_t *args) ++{ ++ args->features = VMKNETDDI_QUEUEOPS_FEATURE_NONE; ++ args->features |= VMKNETDDI_QUEUEOPS_FEATURE_RXQUEUES; ++ args->features |= VMKNETDDI_QUEUEOPS_FEATURE_TXQUEUES; ++ return VMKNETDDI_QUEUEOPS_OK; ++} ++ ++static int bnx2x_get_queue_count(vmknetddi_queueop_get_queue_count_args_t *args) ++{ ++ struct bnx2x *bp = netdev_priv(args->netdev); ++ ++ /* workaround for packets duplicated */ ++ if (is_multi(bp)) { ++ bp->rx_mode = BNX2X_RX_MODE_NORMAL; ++ bnx2x_set_storm_rx_mode(bp); ++ bp->netq_enabled = 1; ++ } ++ if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_RX) { ++ args->count = max_t(u16, BNX2X_NUM_QUEUES(bp) - 1, 0); ++ return VMKNETDDI_QUEUEOPS_OK; ++ ++ } else if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_TX) { ++ args->count = max_t(u16, BNX2X_NUM_QUEUES(bp) - 1, 0); ++ return VMKNETDDI_QUEUEOPS_OK; ++ ++ } else { ++ printk("bnx2x_get_queue_count: invalid queue type\n"); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++} ++ ++static int bnx2x_get_filter_count(vmknetddi_queueop_get_filter_count_args_t *args) ++{ ++ /* Only support 1 Mac filter per queue */ ++ args->count = 1; ++ return VMKNETDDI_QUEUEOPS_OK; ++} ++ ++static int bnx2x_alloc_rx_queue(struct net_device *netdev, ++ vmknetddi_queueops_queueid_t *p_qid, ++ struct napi_struct **napi_p) ++{ ++ struct bnx2x *bp = netdev_priv(netdev); ++ int i; ++ ++ if (bp->n_rx_queues_allocated >= BNX2X_NUM_QUEUES(bp)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ for_each_nondefault_queue(bp, i) { ++ struct bnx2x_fastpath *fp = &bp->fp[i]; ++ ++ if (!BNX2X_IS_NETQ_RX_QUEUE_ALLOCATED(fp)) { ++ fp->netq_flags |= BNX2X_NETQ_RX_QUEUE_ALLOCATED; ++ bp->n_rx_queues_allocated++; ++ *p_qid = VMKNETDDI_QUEUEOPS_MK_RX_QUEUEID(fp->index); ++ *napi_p = &fp->napi; ++ return VMKNETDDI_QUEUEOPS_OK; ++ } ++ } ++ BNX2X_ERR("bnx2x_alloc_rx_queue: no free rx queues found!\n"); ++ return VMKNETDDI_QUEUEOPS_ERR; ++} ++ ++static int bnx2x_alloc_tx_queue(struct net_device *netdev, ++ vmknetddi_queueops_queueid_t *p_qid, ++ u16 *queue_mapping) ++{ ++ struct bnx2x *bp = netdev_priv(netdev); ++ int i; ++ ++ if (bp->n_tx_queues_allocated >= BNX2X_NUM_QUEUES(bp)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ for_each_nondefault_queue(bp, i) { ++ struct bnx2x_fastpath *fp = &bp->fp[i]; ++ ++ if (!BNX2X_IS_NETQ_TX_QUEUE_ALLOCATED(fp)) { ++ fp->netq_flags |= BNX2X_NETQ_TX_QUEUE_ALLOCATED; ++ bp->n_tx_queues_allocated++; ++ *p_qid = VMKNETDDI_QUEUEOPS_MK_TX_QUEUEID(fp->index); ++ *queue_mapping = fp->index; ++ return VMKNETDDI_QUEUEOPS_OK; ++ } ++ } ++ BNX2X_ERR("bnx2x_alloc_tx_queue: no free tx queues found!\n"); ++ return VMKNETDDI_QUEUEOPS_ERR; ++} ++ ++static int bnx2x_alloc_queue(vmknetddi_queueop_alloc_queue_args_t *args) ++{ ++ if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_TX) ++ return bnx2x_alloc_tx_queue(args->netdev, &args->queueid, ++ &args->queue_mapping); ++ ++ else if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_RX) ++ return bnx2x_alloc_rx_queue(args->netdev, &args->queueid, ++ &args->napi); ++ else { ++ printk("bnx2x_alloc_queue: invalid queue type\n"); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++} ++ ++static int bnx2x_free_tx_queue(struct net_device *netdev, ++ vmknetddi_queueops_queueid_t qid) ++{ ++ struct bnx2x *bp = netdev_priv(netdev); ++ u16 index = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(qid); ++ ++ if (index > BNX2X_NUM_QUEUES(bp)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ struct bnx2x_fastpath *fp = &bp->fp[index]; ++ ++ if (!BNX2X_IS_NETQ_TX_QUEUE_ALLOCATED(fp)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ fp->netq_flags &= ~BNX2X_NETQ_TX_QUEUE_ALLOCATED; ++ bp->n_tx_queues_allocated--; ++ ++ return VMKNETDDI_QUEUEOPS_OK; ++} ++ ++static int bnx2x_free_rx_queue(struct net_device *netdev, ++ vmknetddi_queueops_queueid_t qid) ++{ ++ struct bnx2x *bp = netdev_priv(netdev); ++ u16 index = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(qid); ++ ++ if (index > BNX2X_NUM_QUEUES(bp)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ struct bnx2x_fastpath *fp = &bp->fp[index]; ++ ++ if (!BNX2X_IS_NETQ_RX_QUEUE_ALLOCATED(fp)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ fp->netq_flags &= ~BNX2X_NETQ_RX_QUEUE_ALLOCATED; ++ bp->n_rx_queues_allocated--; ++ ++ return VMKNETDDI_QUEUEOPS_OK; ++} ++ ++static int bnx2x_free_queue(vmknetddi_queueop_free_queue_args_t *args) ++{ ++ if (VMKNETDDI_QUEUEOPS_IS_TX_QUEUEID(args->queueid)) ++ return bnx2x_free_tx_queue(args->netdev, args->queueid); ++ ++ else if (VMKNETDDI_QUEUEOPS_IS_RX_QUEUEID(args->queueid)) ++ return bnx2x_free_rx_queue(args->netdev, args->queueid); ++ ++ else { ++ printk("bnx2x_free_queue: invalid queue type\n"); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++} ++ ++static int bnx2x_get_queue_vector(vmknetddi_queueop_get_queue_vector_args_t *args) ++{ ++ struct net_device *netdev = args->netdev; ++ struct bnx2x *bp = netdev_priv(netdev); ++ int qid; ++ ++ qid = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(args->queueid); ++ if (qid > BNX2X_NUM_QUEUES(bp)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++#ifdef CONFIG_PCI_MSI ++ args->vector = bp->msix_table[qid].vector; ++#endif ++ return VMKNETDDI_QUEUEOPS_OK; ++} ++ ++static int bnx2x_get_default_queue(vmknetddi_queueop_get_default_queue_args_t *args) ++{ ++ struct net_device *netdev = args->netdev; ++ struct bnx2x *bp = netdev_priv(netdev); ++ ++ if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_RX) { ++ args->queueid = VMKNETDDI_QUEUEOPS_MK_RX_QUEUEID(0); ++ args->napi = &bp->fp[0].napi; ++ return VMKNETDDI_QUEUEOPS_OK; ++ ++ } else if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_TX) { ++ args->queueid = VMKNETDDI_QUEUEOPS_MK_TX_QUEUEID(0); ++ args->queue_mapping = 0; ++ return VMKNETDDI_QUEUEOPS_OK; ++ ++ } else ++ return VMKNETDDI_QUEUEOPS_ERR; ++} ++ ++static void bnx2x_remove_rx_filter_e1h(struct bnx2x *bp, u16 qid) ++{ ++ struct bnx2x_fastpath *fp = &bp->fp[qid]; ++ struct mac_configuration_cmd_e1h *config = ++ (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config); ++ ++ /* CAM allocation for E1H ++ * unicasts: by func number ++ * multicast: 20+FUNC*20, 20 each ++ */ ++ config->hdr.length = 1; ++ config->hdr.offset = BP_FUNC(bp) + (qid << (IS_E1HMF(bp) ? 3 : 1)); ++ config->hdr.client_id = bp->fp[0].cl_id; ++ config->hdr.reserved1 = 0; ++ ++ /* primary MAC */ ++ config->config_table[0].msb_mac_addr = ++ swab16(*(u16 *)&fp->mac_filter_addr[0]); ++ config->config_table[0].middle_mac_addr = ++ swab16(*(u16 *)&fp->mac_filter_addr[2]); ++ config->config_table[0].lsb_mac_addr = ++ swab16(*(u16 *)&fp->mac_filter_addr[4]); ++ config->config_table[0].client_id = BP_L_ID(bp) + qid; ++ config->config_table[0].vlan_id = 0; ++ config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov); ++ config->config_table[0].flags = MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE; ++ ++ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, ++ U64_HI(bnx2x_sp_mapping(bp, mac_config)), ++ U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0); ++ ++ memset(fp->mac_filter_addr, 0, 6); ++ fp->netq_flags &= ~BNX2X_NETQ_RX_QUEUE_ACTIVE; ++} ++ ++static void bnx2x_remove_rx_filter_e1(struct bnx2x *bp, u16 qid) ++{ ++ struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config); ++ struct bnx2x_fastpath *fp = &bp->fp[qid]; ++ ++ config->hdr.length = 1; ++ config->hdr.offset = (BP_PORT(bp) ? 32 : 0) + qid; ++ config->hdr.client_id = bp->fp[0].cl_id; ++ config->hdr.reserved1 = 0; ++ ++ config->config_table[0].cam_entry.msb_mac_addr = ++ swab16(*(u16 *)&fp->mac_filter_addr[0]); ++ config->config_table[0].cam_entry.middle_mac_addr = ++ swab16(*(u16 *)&fp->mac_filter_addr[2]); ++ config->config_table[0].cam_entry.lsb_mac_addr = ++ swab16(*(u16 *)&fp->mac_filter_addr[4]); ++ config->config_table[0].cam_entry.flags = cpu_to_le16(BP_PORT(bp)); ++ config->config_table[0].target_table_entry.flags = ++ TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE; ++ config->config_table[0].target_table_entry.client_id = qid; ++ config->config_table[0].target_table_entry.vlan_id = 0; ++ ++ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, ++ U64_HI(bnx2x_sp_mapping(bp, mac_config)), ++ U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0); ++ ++ memset(fp->mac_filter_addr, 0, 6); ++ fp->netq_flags &= ~BNX2X_NETQ_RX_QUEUE_ACTIVE; ++} ++ ++static int bnx2x_remove_rx_filter(vmknetddi_queueop_remove_rx_filter_args_t *args) ++{ ++ struct bnx2x *bp = netdev_priv(args->netdev); ++ u16 qid = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(args->queueid); ++ u16 fid = VMKNETDDI_QUEUEOPS_FILTERID_VAL(args->filterid); ++ struct bnx2x_fastpath *fp = &bp->fp[qid]; ++ ++ if (!VMKNETDDI_QUEUEOPS_IS_RX_QUEUEID(args->queueid)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ if (qid > BNX2X_NUM_QUEUES(bp)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ /* Only support one Mac filter per queue */ ++ if ((fid != 0) || !BNX2X_IS_NETQ_RX_QUEUE_ACTIVE(fp)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ if (CHIP_IS_E1H(bp)) ++ bnx2x_remove_rx_filter_e1h(bp, qid); ++ else ++ bnx2x_remove_rx_filter_e1(bp, qid); ++ ++ return VMKNETDDI_QUEUEOPS_OK; ++} ++ ++static void bnx2x_apply_rx_filter_e1h(struct bnx2x *bp, u16 queueid) ++{ ++ struct mac_configuration_cmd_e1h *config = ++ (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config); ++ struct bnx2x_fastpath *fp = &bp->fp[queueid]; ++ ++ config->hdr.length = 1; ++ config->hdr.offset = BP_FUNC(bp) + (queueid << (IS_E1HMF(bp) ? 3 : 1)); ++ config->hdr.client_id = bp->fp[0].cl_id; ++ config->hdr.reserved1 = 0; ++ ++ config->config_table[0].msb_mac_addr = ++ swab16(*(u16 *)&fp->mac_filter_addr[0]); ++ config->config_table[0].middle_mac_addr = ++ swab16(*(u16 *)&fp->mac_filter_addr[2]); ++ config->config_table[0].lsb_mac_addr = ++ swab16(*(u16 *)&fp->mac_filter_addr[4]); ++ config->config_table[0].client_id = BP_L_ID(bp) + queueid; ++ config->config_table[0].vlan_id = 0; ++ config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov); ++ config->config_table[0].flags = BP_PORT(bp); ++ ++ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, ++ U64_HI(bnx2x_sp_mapping(bp, mac_config)), ++ U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0); ++ ++ fp->netq_flags |= BNX2X_NETQ_RX_QUEUE_ACTIVE; ++} ++ ++static void bnx2x_apply_rx_filter_e1(struct bnx2x *bp, u16 queueid) ++{ ++ struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config); ++ struct bnx2x_fastpath *fp = &bp->fp[queueid]; ++ ++ config->hdr.length = 1; ++ config->hdr.offset = (BP_PORT(bp) ? 32 : 0) + queueid; ++ config->hdr.client_id = bp->fp[0].cl_id; ++ config->hdr.reserved1 = 0; ++ ++ config->config_table[0].cam_entry.msb_mac_addr = ++ swab16(*(u16 *)&fp->mac_filter_addr[0]); ++ config->config_table[0].cam_entry.middle_mac_addr = ++ swab16(*(u16 *)&fp->mac_filter_addr[2]); ++ config->config_table[0].cam_entry.lsb_mac_addr = ++ swab16(*(u16 *)&fp->mac_filter_addr[4]); ++ config->config_table[0].cam_entry.flags = cpu_to_le16(BP_PORT(bp)); ++ config->config_table[0].target_table_entry.flags = 0; ++ config->config_table[0].target_table_entry.client_id = queueid; ++ config->config_table[0].target_table_entry.vlan_id = 0; ++ ++ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, ++ U64_HI(bnx2x_sp_mapping(bp, mac_config)), ++ U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0); ++ ++ fp->netq_flags |= BNX2X_NETQ_RX_QUEUE_ACTIVE; ++} ++ ++static int bnx2x_apply_rx_filter(vmknetddi_queueop_apply_rx_filter_args_t *args) ++{ ++ struct bnx2x *bp = netdev_priv(args->netdev); ++ struct bnx2x_fastpath *fp; ++ u16 queueid = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(args->queueid); ++ u8 *macaddr; ++ ++ if (!VMKNETDDI_QUEUEOPS_IS_RX_QUEUEID(args->queueid)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ if (vmknetddi_queueops_get_filter_class(&args->filter) ++ != VMKNETDDI_QUEUEOPS_FILTER_MACADDR) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ if (queueid > BNX2X_NUM_QUEUES(bp)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ fp = &bp->fp[queueid]; ++ ++ if (BNX2X_IS_NETQ_RX_QUEUE_ACTIVE(fp) || ++ !BNX2X_IS_NETQ_RX_QUEUE_ALLOCATED(fp)) ++ return VMKNETDDI_QUEUEOPS_ERR; ++ ++ macaddr = (void *)vmknetddi_queueops_get_filter_macaddr(&args->filter); ++ memcpy(fp->mac_filter_addr, macaddr, 6); ++ if (CHIP_IS_E1H(bp)) ++ bnx2x_apply_rx_filter_e1h(bp, queueid); ++ else ++ bnx2x_apply_rx_filter_e1(bp, queueid); ++ args->filterid = VMKNETDDI_QUEUEOPS_MK_FILTERID(0); ++ ++ return VMKNETDDI_QUEUEOPS_OK; ++} ++ ++static int bnx2x_get_queue_stats(vmknetddi_queueop_get_stats_args_t *args) ++{ ++ return VMKNETDDI_QUEUEOPS_ERR; ++} ++ ++static int bnx2x_get_netqueue_version(vmknetddi_queueop_get_version_args_t *args) ++{ ++ return vmknetddi_queueops_version(args); ++} ++ ++static int bnx2x_netqueue_ops(vmknetddi_queueops_op_t op, void *args) ++{ ++ switch (op) { ++ case VMKNETDDI_QUEUEOPS_OP_GET_VERSION: ++ return bnx2x_get_netqueue_version( ++ (vmknetddi_queueop_get_version_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_GET_FEATURES: ++ return bnx2x_get_netqueue_features( ++ (vmknetddi_queueop_get_features_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_GET_QUEUE_COUNT: ++ return bnx2x_get_queue_count( ++ (vmknetddi_queueop_get_queue_count_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_GET_FILTER_COUNT: ++ return bnx2x_get_filter_count( ++ (vmknetddi_queueop_get_filter_count_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_ALLOC_QUEUE: ++ return bnx2x_alloc_queue( ++ (vmknetddi_queueop_alloc_queue_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_FREE_QUEUE: ++ return bnx2x_free_queue( ++ (vmknetddi_queueop_free_queue_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_GET_QUEUE_VECTOR: ++ return bnx2x_get_queue_vector( ++ (vmknetddi_queueop_get_queue_vector_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_GET_DEFAULT_QUEUE: ++ return bnx2x_get_default_queue( ++ (vmknetddi_queueop_get_default_queue_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_APPLY_RX_FILTER: ++ return bnx2x_apply_rx_filter( ++ (vmknetddi_queueop_apply_rx_filter_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_REMOVE_RX_FILTER: ++ return bnx2x_remove_rx_filter( ++ (vmknetddi_queueop_remove_rx_filter_args_t *)args); ++ break; ++ ++ case VMKNETDDI_QUEUEOPS_OP_GET_STATS: ++ return bnx2x_get_queue_stats( ++ (vmknetddi_queueop_get_stats_args_t *)args); ++ break; ++ ++ default: ++ printk("Unhandled NETQUEUE OP %d\n", op); ++ return VMKNETDDI_QUEUEOPS_ERR; ++ } ++ ++ return VMKNETDDI_QUEUEOPS_ERR; ++} ++ ++#endif /* defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) */ +diff -r e67cb9a8e847 drivers/net/bnx2x_reg.h +--- a/drivers/net/bnx2x_reg.h Wed Aug 05 10:50:39 2009 +0100 ++++ b/drivers/net/bnx2x_reg.h Wed Aug 05 10:51:03 2009 +0100 +@@ -30,8 +30,20 @@ + address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address + BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */ + #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200 ++/* [RW 10] The number of free blocks above which the High_llfc signal to ++ interface #n is de-asserted. */ ++#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c ++/* [RW 10] The number of free blocks below which the High_llfc signal to ++ interface #n is asserted. */ ++#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c + /* [RW 23] LL RAM data. */ + #define BRB1_REG_LL_RAM 0x61000 ++/* [RW 10] The number of free blocks above which the Low_llfc signal to ++ interface #n is de-asserted. */ ++#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c ++/* [RW 10] The number of free blocks below which the Low_llfc signal to ++ interface #n is asserted. */ ++#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c + /* [R 24] The number of full blocks. */ + #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090 + /* [ST 32] The number of cycles that the write_full signal towards MAC #0 +@@ -125,6 +137,10 @@ + stands for weight 8 (the most prioritised); 1 stands for weight 1(least + prioritised); 2 stands for weight 2; tc. */ + #define CCM_REG_CQM_P_WEIGHT 0xd00b8 ++/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 ++ stands for weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define CCM_REG_CQM_S_WEIGHT 0xd00bc + /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; + acknowledge output is deasserted; all other signals are treated as usual; + if 1 - normal activity. */ +@@ -132,6 +148,10 @@ + /* [RC 1] Set when the message length mismatch (relative to last indication) + at the SDM interface is detected. */ + #define CCM_REG_CSDM_LENGTH_MIS 0xd0170 ++/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for ++ weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define CCM_REG_CSDM_WEIGHT 0xd00b4 + /* [RW 28] The CM header for QM formatting in case of an error in the QM + inputs. */ + #define CCM_REG_ERR_CCM_HDR 0xd0094 +@@ -170,12 +190,6 @@ + _(0..15) stands for the connection type (one of 16). */ + #define CCM_REG_N_SM_CTX_LD_0 0xd004c + #define CCM_REG_N_SM_CTX_LD_1 0xd0050 +-#define CCM_REG_N_SM_CTX_LD_10 0xd0074 +-#define CCM_REG_N_SM_CTX_LD_11 0xd0078 +-#define CCM_REG_N_SM_CTX_LD_12 0xd007c +-#define CCM_REG_N_SM_CTX_LD_13 0xd0080 +-#define CCM_REG_N_SM_CTX_LD_14 0xd0084 +-#define CCM_REG_N_SM_CTX_LD_15 0xd0088 + #define CCM_REG_N_SM_CTX_LD_2 0xd0054 + #define CCM_REG_N_SM_CTX_LD_3 0xd0058 + #define CCM_REG_N_SM_CTX_LD_4 0xd005c +@@ -211,6 +225,11 @@ + /* [RC 1] Set when the message length mismatch (relative to last indication) + at the STORM interface is detected. */ + #define CCM_REG_STORM_LENGTH_MIS 0xd016c ++/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin) ++ mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for ++ weight 1(least prioritised); 2 stands for weight 2 (more prioritised); ++ tc. */ ++#define CCM_REG_STORM_WEIGHT 0xd009c + /* [RW 1] Input tsem Interface enable. If 0 - the valid input is + disregarded; acknowledge output is deasserted; all other signals are + treated as usual; if 1 - normal activity. */ +@@ -323,7 +342,11 @@ + set one of these bits. the bit description can be found in CFC + specifications */ + #define CFC_REG_ERROR_VECTOR 0x10403c ++/* [WB 93] LCID info ram access */ ++#define CFC_REG_INFO_RAM 0x105000 ++#define CFC_REG_INFO_RAM_SIZE 1024 + #define CFC_REG_INIT_REG 0x10404c ++#define CFC_REG_INTERFACES 0x104058 + /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this + field allows changing the priorities of the weighted-round-robin arbiter + which selects which CFC load client should be served next */ +@@ -337,13 +360,10 @@ + #define CFC_REG_NUM_LCIDS_ALLOC 0x104020 + /* [R 9] Number of Arriving LCIDs in Link List Block */ + #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004 +-/* [R 9] Number of Inside LCIDs in Link List Block */ +-#define CFC_REG_NUM_LCIDS_INSIDE 0x104008 + /* [R 9] Number of Leaving LCIDs in Link List Block */ + #define CFC_REG_NUM_LCIDS_LEAVING 0x104018 + /* [RW 8] The event id for aggregated interrupt 0 */ + #define CSDM_REG_AGG_INT_EVENT_0 0xc2038 +-#define CSDM_REG_AGG_INT_EVENT_1 0xc203c + #define CSDM_REG_AGG_INT_EVENT_10 0xc2060 + #define CSDM_REG_AGG_INT_EVENT_11 0xc2064 + #define CSDM_REG_AGG_INT_EVENT_12 0xc2068 +@@ -351,37 +371,27 @@ + #define CSDM_REG_AGG_INT_EVENT_14 0xc2070 + #define CSDM_REG_AGG_INT_EVENT_15 0xc2074 + #define CSDM_REG_AGG_INT_EVENT_16 0xc2078 +-#define CSDM_REG_AGG_INT_EVENT_17 0xc207c +-#define CSDM_REG_AGG_INT_EVENT_18 0xc2080 +-#define CSDM_REG_AGG_INT_EVENT_19 0xc2084 + #define CSDM_REG_AGG_INT_EVENT_2 0xc2040 +-#define CSDM_REG_AGG_INT_EVENT_20 0xc2088 +-#define CSDM_REG_AGG_INT_EVENT_21 0xc208c +-#define CSDM_REG_AGG_INT_EVENT_22 0xc2090 +-#define CSDM_REG_AGG_INT_EVENT_23 0xc2094 +-#define CSDM_REG_AGG_INT_EVENT_24 0xc2098 +-#define CSDM_REG_AGG_INT_EVENT_25 0xc209c +-#define CSDM_REG_AGG_INT_EVENT_26 0xc20a0 +-#define CSDM_REG_AGG_INT_EVENT_27 0xc20a4 +-#define CSDM_REG_AGG_INT_EVENT_28 0xc20a8 +-#define CSDM_REG_AGG_INT_EVENT_29 0xc20ac + #define CSDM_REG_AGG_INT_EVENT_3 0xc2044 +-#define CSDM_REG_AGG_INT_EVENT_30 0xc20b0 +-#define CSDM_REG_AGG_INT_EVENT_31 0xc20b4 + #define CSDM_REG_AGG_INT_EVENT_4 0xc2048 +-/* [RW 1] The T bit for aggregated interrupt 0 */ +-#define CSDM_REG_AGG_INT_T_0 0xc20b8 +-#define CSDM_REG_AGG_INT_T_1 0xc20bc +-#define CSDM_REG_AGG_INT_T_10 0xc20e0 +-#define CSDM_REG_AGG_INT_T_11 0xc20e4 +-#define CSDM_REG_AGG_INT_T_12 0xc20e8 +-#define CSDM_REG_AGG_INT_T_13 0xc20ec +-#define CSDM_REG_AGG_INT_T_14 0xc20f0 +-#define CSDM_REG_AGG_INT_T_15 0xc20f4 +-#define CSDM_REG_AGG_INT_T_16 0xc20f8 +-#define CSDM_REG_AGG_INT_T_17 0xc20fc +-#define CSDM_REG_AGG_INT_T_18 0xc2100 +-#define CSDM_REG_AGG_INT_T_19 0xc2104 ++#define CSDM_REG_AGG_INT_EVENT_5 0xc204c ++#define CSDM_REG_AGG_INT_EVENT_6 0xc2050 ++#define CSDM_REG_AGG_INT_EVENT_7 0xc2054 ++#define CSDM_REG_AGG_INT_EVENT_8 0xc2058 ++#define CSDM_REG_AGG_INT_EVENT_9 0xc205c ++/* [RW 1] For each aggregated interrupt index whether the mode is normal (0) ++ or auto-mask-mode (1) */ ++#define CSDM_REG_AGG_INT_MODE_10 0xc21e0 ++#define CSDM_REG_AGG_INT_MODE_11 0xc21e4 ++#define CSDM_REG_AGG_INT_MODE_12 0xc21e8 ++#define CSDM_REG_AGG_INT_MODE_13 0xc21ec ++#define CSDM_REG_AGG_INT_MODE_14 0xc21f0 ++#define CSDM_REG_AGG_INT_MODE_15 0xc21f4 ++#define CSDM_REG_AGG_INT_MODE_16 0xc21f8 ++#define CSDM_REG_AGG_INT_MODE_6 0xc21d0 ++#define CSDM_REG_AGG_INT_MODE_7 0xc21d4 ++#define CSDM_REG_AGG_INT_MODE_8 0xc21d8 ++#define CSDM_REG_AGG_INT_MODE_9 0xc21dc + /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ + #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008 + /* [RW 16] The maximum value of the competion counter #0 */ +@@ -604,24 +614,6 @@ + #define DMAE_REG_GO_C0 0x102080 + /* [RW 1] Command 1 go. */ + #define DMAE_REG_GO_C1 0x102084 +-/* [RW 1] Command 10 go. */ +-#define DMAE_REG_GO_C10 0x102088 +-#define DMAE_REG_GO_C10_SIZE 1 +-/* [RW 1] Command 11 go. */ +-#define DMAE_REG_GO_C11 0x10208c +-#define DMAE_REG_GO_C11_SIZE 1 +-/* [RW 1] Command 12 go. */ +-#define DMAE_REG_GO_C12 0x102090 +-#define DMAE_REG_GO_C12_SIZE 1 +-/* [RW 1] Command 13 go. */ +-#define DMAE_REG_GO_C13 0x102094 +-#define DMAE_REG_GO_C13_SIZE 1 +-/* [RW 1] Command 14 go. */ +-#define DMAE_REG_GO_C14 0x102098 +-#define DMAE_REG_GO_C14_SIZE 1 +-/* [RW 1] Command 15 go. */ +-#define DMAE_REG_GO_C15 0x10209c +-#define DMAE_REG_GO_C15_SIZE 1 + /* [RW 1] Command 10 go. */ + #define DMAE_REG_GO_C10 0x102088 + /* [RW 1] Command 11 go. */ +@@ -730,6 +722,7 @@ + #define DORQ_REG_SHRT_CMHEAD 0x170054 + #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4) + #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3) ++#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7) + #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2) + #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) + #define HC_REG_AGG_INT_0 0x108050 +@@ -772,7 +765,6 @@ + #define MCP_REG_MCPR_NVM_READ 0x86410 + #define MCP_REG_MCPR_NVM_SW_ARB 0x86420 + #define MCP_REG_MCPR_NVM_WRITE 0x86408 +-#define MCP_REG_MCPR_NVM_WRITE1 0x86428 + #define MCP_REG_MCPR_SCRATCH 0xa0000 + /* [R 32] read first 32 bit after inversion of function 0. mapped as + follows: [0] NIG attention for function0; [1] NIG attention for +@@ -1158,19 +1150,7 @@ + #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 + #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c + #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 +-#define MISC_REG_AEU_GENERAL_ATTN_13 0xa034 +-#define MISC_REG_AEU_GENERAL_ATTN_14 0xa038 +-#define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c +-#define MISC_REG_AEU_GENERAL_ATTN_16 0xa040 +-#define MISC_REG_AEU_GENERAL_ATTN_17 0xa044 +-#define MISC_REG_AEU_GENERAL_ATTN_18 0xa048 +-#define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c +-#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 +-#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c +-#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 + #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 +-#define MISC_REG_AEU_GENERAL_ATTN_20 0xa050 +-#define MISC_REG_AEU_GENERAL_ATTN_21 0xa054 + #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c + #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010 + #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014 +@@ -1262,137 +1242,13 @@ + set. if the appropriate bit is clear (the driver request to free a client + it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will + be asserted). */ +-#define MISC_REG_DRIVER_CONTROL_10 0xa3e0 +-#define MISC_REG_DRIVER_CONTROL_10_SIZE 2 +-/* [RW 32] The following driver registers(1...16) represent 16 drivers and +- 32 clients. Each client can be controlled by one driver only. One in each +- bit represent that this driver control the appropriate client (Ex: bit 5 +- is set means this driver control client number 5). addr1 = set; addr0 = +- clear; read from both addresses will give the same result = status. write +- to address 1 will set a request to control all the clients that their +- appropriate bit (in the write command) is set. if the client is free (the +- appropriate bit in all the other drivers is clear) one will be written to +- that driver register; if the client isn't free the bit will remain zero. +- if the appropriate bit is set (the driver request to gain control on a +- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW +- interrupt will be asserted). write to address 0 will set a request to +- free all the clients that their appropriate bit (in the write command) is +- set. if the appropriate bit is clear (the driver request to free a client +- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will +- be asserted). */ +-#define MISC_REG_DRIVER_CONTROL_11 0xa3e8 +-#define MISC_REG_DRIVER_CONTROL_11_SIZE 2 +-/* [RW 32] The following driver registers(1...16) represent 16 drivers and +- 32 clients. Each client can be controlled by one driver only. One in each +- bit represent that this driver control the appropriate client (Ex: bit 5 +- is set means this driver control client number 5). addr1 = set; addr0 = +- clear; read from both addresses will give the same result = status. write +- to address 1 will set a request to control all the clients that their +- appropriate bit (in the write command) is set. if the client is free (the +- appropriate bit in all the other drivers is clear) one will be written to +- that driver register; if the client isn't free the bit will remain zero. +- if the appropriate bit is set (the driver request to gain control on a +- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW +- interrupt will be asserted). write to address 0 will set a request to +- free all the clients that their appropriate bit (in the write command) is +- set. if the appropriate bit is clear (the driver request to free a client +- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will +- be asserted). */ +-#define MISC_REG_DRIVER_CONTROL_12 0xa3f0 +-#define MISC_REG_DRIVER_CONTROL_12_SIZE 2 +-/* [RW 32] The following driver registers(1...16) represent 16 drivers and +- 32 clients. Each client can be controlled by one driver only. One in each +- bit represent that this driver control the appropriate client (Ex: bit 5 +- is set means this driver control client number 5). addr1 = set; addr0 = +- clear; read from both addresses will give the same result = status. write +- to address 1 will set a request to control all the clients that their +- appropriate bit (in the write command) is set. if the client is free (the +- appropriate bit in all the other drivers is clear) one will be written to +- that driver register; if the client isn't free the bit will remain zero. +- if the appropriate bit is set (the driver request to gain control on a +- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW +- interrupt will be asserted). write to address 0 will set a request to +- free all the clients that their appropriate bit (in the write command) is +- set. if the appropriate bit is clear (the driver request to free a client +- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will +- be asserted). */ +-#define MISC_REG_DRIVER_CONTROL_13 0xa3f8 +-#define MISC_REG_DRIVER_CONTROL_13_SIZE 2 +-/* [RW 32] The following driver registers(1...16) represent 16 drivers and +- 32 clients. Each client can be controlled by one driver only. One in each +- bit represent that this driver control the appropriate client (Ex: bit 5 +- is set means this driver control client number 5). addr1 = set; addr0 = +- clear; read from both addresses will give the same result = status. write +- to address 1 will set a request to control all the clients that their +- appropriate bit (in the write command) is set. if the client is free (the +- appropriate bit in all the other drivers is clear) one will be written to +- that driver register; if the client isn't free the bit will remain zero. +- if the appropriate bit is set (the driver request to gain control on a +- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW +- interrupt will be asserted). write to address 0 will set a request to +- free all the clients that their appropriate bit (in the write command) is +- set. if the appropriate bit is clear (the driver request to free a client +- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will +- be asserted). */ + #define MISC_REG_DRIVER_CONTROL_1 0xa510 +-#define MISC_REG_DRIVER_CONTROL_14 0xa5e0 +-#define MISC_REG_DRIVER_CONTROL_14_SIZE 2 +-/* [RW 32] The following driver registers(1...16) represent 16 drivers and +- 32 clients. Each client can be controlled by one driver only. One in each +- bit represent that this driver control the appropriate client (Ex: bit 5 +- is set means this driver control client number 5). addr1 = set; addr0 = +- clear; read from both addresses will give the same result = status. write +- to address 1 will set a request to control all the clients that their +- appropriate bit (in the write command) is set. if the client is free (the +- appropriate bit in all the other drivers is clear) one will be written to +- that driver register; if the client isn't free the bit will remain zero. +- if the appropriate bit is set (the driver request to gain control on a +- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW +- interrupt will be asserted). write to address 0 will set a request to +- free all the clients that their appropriate bit (in the write command) is +- set. if the appropriate bit is clear (the driver request to free a client +- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will +- be asserted). */ +-#define MISC_REG_DRIVER_CONTROL_15 0xa5e8 +-#define MISC_REG_DRIVER_CONTROL_15_SIZE 2 +-/* [RW 32] The following driver registers(1...16) represent 16 drivers and +- 32 clients. Each client can be controlled by one driver only. One in each +- bit represent that this driver control the appropriate client (Ex: bit 5 +- is set means this driver control client number 5). addr1 = set; addr0 = +- clear; read from both addresses will give the same result = status. write +- to address 1 will set a request to control all the clients that their +- appropriate bit (in the write command) is set. if the client is free (the +- appropriate bit in all the other drivers is clear) one will be written to +- that driver register; if the client isn't free the bit will remain zero. +- if the appropriate bit is set (the driver request to gain control on a +- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW +- interrupt will be asserted). write to address 0 will set a request to +- free all the clients that their appropriate bit (in the write command) is +- set. if the appropriate bit is clear (the driver request to free a client +- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will +- be asserted). */ +-#define MISC_REG_DRIVER_CONTROL_16 0xa5f0 +-#define MISC_REG_DRIVER_CONTROL_16_SIZE 2 +-/* [RW 32] The following driver registers(1...16) represent 16 drivers and +- 32 clients. Each client can be controlled by one driver only. One in each +- bit represent that this driver control the appropriate client (Ex: bit 5 +- is set means this driver control client number 5). addr1 = set; addr0 = +- clear; read from both addresses will give the same result = status. write +- to address 1 will set a request to control all the clients that their +- appropriate bit (in the write command) is set. if the client is free (the +- appropriate bit in all the other drivers is clear) one will be written to +- that driver register; if the client isn't free the bit will remain zero. +- if the appropriate bit is set (the driver request to gain control on a +- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW +- interrupt will be asserted). write to address 0 will set a request to +- free all the clients that their appropriate bit (in the write command) is +- set. if the appropriate bit is clear (the driver request to free a client +- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will +- be asserted). */ + #define MISC_REG_DRIVER_CONTROL_7 0xa3c8 + /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 + only. */ + #define MISC_REG_E1HMF_MODE 0xa5f8 ++/* [RW 32] Debug only: spare RW register reset by core reset */ ++#define MISC_REG_GENERIC_CR_0 0xa460 + /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of + these bits is written as a '1'; the corresponding SPIO bit will turn off + it's drivers and become an input. This is the reset state of all GPIO +@@ -1410,6 +1266,29 @@ + This is the result value of the pin; not the drive value. Writing these + bits will have not effect. */ + #define MISC_REG_GPIO 0xa490 ++/* [RW 8] These bits enable the GPIO_INTs to signals event to the ++ IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2] ++ p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2; ++ [7] p1_gpio_3; */ ++#define MISC_REG_GPIO_EVENT_EN 0xa2bc ++/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a ++ '1' to these bit clears the corresponding bit in the #OLD_VALUE register. ++ This will acknowledge an interrupt on the falling edge of corresponding ++ GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0; ++ Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE ++ register. This will acknowledge an interrupt on the rising edge of ++ corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1; ++ OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input ++ value. When the ~INT_STATE bit is set; this bit indicates the OLD value ++ of the pin such that if ~INT_STATE is set and this bit is '0'; then the ++ interrupt is due to a low to high edge. If ~INT_STATE is set and this bit ++ is '1'; then the interrupt is due to a high to low edge (reset value 0). ++ [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the ++ current GPIO interrupt state for each GPIO pin. This bit is cleared when ++ the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is ++ set when the GPIO input does not match the current value in #OLD_VALUE ++ (reset value 0). */ ++#define MISC_REG_GPIO_INT 0xa494 + /* [R 28] this field hold the last information that caused reserved + attention. bits [19:0] - address; [22:20] function; [23] reserved; + [27:24] the master that caused the attention - according to the following +@@ -1554,6 +1433,14 @@ + command bit is written. This bit is set when the SPIO input does not + match the current value in #OLD_VALUE (reset value 0). */ + #define MISC_REG_SPIO_INT 0xa500 ++/* [RW 32] reload value for counter 4 if reload; the value will be reload if ++ the counter reached zero and the reload bit ++ (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */ ++#define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc ++/* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses ++ in this register. addres 0 - timer 1; address - timer 2�address 7 - ++ timer 8 */ ++#define MISC_REG_SW_TIMER_VAL 0xa5c0 + /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are + loaded; 0-prepare; -unprepare */ + #define MISC_REG_UNPREPARED 0xa424 +@@ -1595,12 +1482,12 @@ + /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs + to emac for port0; other way to bmac for port0 */ + #define NIG_REG_EGRESS_EMAC0_PORT 0x10058 +-/* [RW 32] TX_MNG_FIFO in NIG_TX_PORT0; data[31:0] written in FIFO order. */ +-#define NIG_REG_EGRESS_MNG0_FIFO 0x1045c + /* [RW 1] Input enable for TX PBF user packet port0 IF */ + #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc + /* [RW 1] Input enable for TX PBF user packet port1 IF */ + #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0 ++/* [RW 1] Input enable for TX UMP management packet port0 IF */ ++#define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4 + /* [RW 1] Input enable for RX_EMAC0 IF */ + #define NIG_REG_EMAC0_IN_EN 0x100a4 + /* [RW 1] output enable for TX EMAC pause port 0 IF */ +@@ -1624,6 +1511,24 @@ + /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data + packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */ + #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4 ++/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch ++ logic for interrupts must be used. Enable per bit of interrupt of ++ ~latch_status.latch_status */ ++#define NIG_REG_LATCH_BC_0 0x16210 ++/* [RW 27] Latch for each interrupt from Unicore.b[0] ++ status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete; ++ b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status; ++ b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn; ++ b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete; ++ b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status; ++ b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete; ++ b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet; ++ b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g; ++ b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact; ++ b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx; ++ b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx; ++ b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */ ++#define NIG_REG_LATCH_STATUS_0 0x18000 + /* [RW 1] led 10g for port 0 */ + #define NIG_REG_LED_10G_P0 0x10320 + /* [RW 1] led 10g for port 1 */ +@@ -1660,6 +1565,20 @@ + /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; + 9-11PHY7; 12 MAC4; 13-15 PHY10; */ + #define NIG_REG_LED_MODE_P0 0x102f0 ++/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1- ++ tsdm enable; b2- usdm enable */ ++#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070 ++#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074 ++/* [RW 1] SAFC enable for port0. This register may get 1 only when ++ ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same ++ port */ ++#define NIG_REG_LLFC_ENABLE_0 0x16208 ++/* [RW 16] classes are high-priority for port0 */ ++#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058 ++/* [RW 16] classes are low-priority for port0 */ ++#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060 ++/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */ ++#define NIG_REG_LLFC_OUT_EN_0 0x160c8 + #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c + #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154 + #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244 +@@ -1730,6 +1649,10 @@ + #define NIG_REG_NIG_INT_STS_1 0x103c0 + /* [R 32] Parity register #0 read */ + #define NIG_REG_NIG_PRTY_STS 0x103d0 ++/* [RW 1] Pause enable for port0. This register may get 1 only when ++ ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same ++ port */ ++#define NIG_REG_PAUSE_ENABLE_0 0x160c0 + /* [RW 1] Input enable for RX PBF LP IF */ + #define NIG_REG_PBF_LB_IN_EN 0x100b4 + /* [RW 1] Value of this register will be transmitted to port swap when +@@ -1739,6 +1662,10 @@ + #define NIG_REG_PRS_EOP_OUT_EN 0x10104 + /* [RW 1] Input enable for RX parser request IF */ + #define NIG_REG_PRS_REQ_IN_EN 0x100b8 ++/* [RW 5] control to serdes - CL45 DEVAD */ ++#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370 ++/* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */ ++#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c + /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */ + #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374 + /* [R 1] status from serdes0 that inputs to interrupt logic of link status */ +@@ -1792,6 +1719,7 @@ + #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8 + /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */ + #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0 ++#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0) + #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9) + #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15) + #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18) +@@ -1885,6 +1813,7 @@ + #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4 + #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8 + #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec ++#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0 + /* [RW 32] The CM header for flush message where 'load existed' bit in CFC + load response is set and packet type is 0. Used in packet start message + to TCM. */ +@@ -1893,6 +1822,7 @@ + #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4 + #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8 + #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc ++#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0 + /* [RW 32] The CM header for a match and packet type 1 for loopback port. + Used in packet start message to TCM. */ + #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c +@@ -1990,6 +1920,7 @@ + #define PXP2_REG_PGL_ADDR_94_F0 0x120540 + #define PXP2_REG_PGL_CONTROL0 0x120490 + #define PXP2_REG_PGL_CONTROL1 0x120514 ++#define PXP2_REG_PGL_DEBUG 0x120520 + /* [RW 32] third dword data of expansion rom request. this register is + special. reading from it provides a vector outstanding read requests. if + a bit is zero it means that a read request on the corresponding tag did +@@ -2035,6 +1966,54 @@ + #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8 + #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec + #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0 ++/* [RW 3] this field allows one function to pretend being another function ++ when accessing any BAR mapped resource within the device. the value of ++ the field is the number of the function that will be accessed ++ effectively. after software write to this bit it must read it in order to ++ know that the new value is updated */ ++#define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674 ++/* [RW 3] this field allows one function to pretend being another function ++ when accessing any BAR mapped resource within the device. the value of ++ the field is the number of the function that will be accessed ++ effectively. after software write to this bit it must read it in order to ++ know that the new value is updated */ ++#define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678 ++/* [RW 3] this field allows one function to pretend being another function ++ when accessing any BAR mapped resource within the device. the value of ++ the field is the number of the function that will be accessed ++ effectively. after software write to this bit it must read it in order to ++ know that the new value is updated */ ++#define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c ++/* [RW 3] this field allows one function to pretend being another function ++ when accessing any BAR mapped resource within the device. the value of ++ the field is the number of the function that will be accessed ++ effectively. after software write to this bit it must read it in order to ++ know that the new value is updated */ ++#define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680 ++/* [RW 3] this field allows one function to pretend being another function ++ when accessing any BAR mapped resource within the device. the value of ++ the field is the number of the function that will be accessed ++ effectively. after software write to this bit it must read it in order to ++ know that the new value is updated */ ++#define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684 ++/* [RW 3] this field allows one function to pretend being another function ++ when accessing any BAR mapped resource within the device. the value of ++ the field is the number of the function that will be accessed ++ effectively. after software write to this bit it must read it in order to ++ know that the new value is updated */ ++#define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688 ++/* [RW 3] this field allows one function to pretend being another function ++ when accessing any BAR mapped resource within the device. the value of ++ the field is the number of the function that will be accessed ++ effectively. after software write to this bit it must read it in order to ++ know that the new value is updated */ ++#define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c ++/* [RW 3] this field allows one function to pretend being another function ++ when accessing any BAR mapped resource within the device. the value of ++ the field is the number of the function that will be accessed ++ effectively. after software write to this bit it must read it in order to ++ know that the new value is updated */ ++#define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690 + /* [R 1] this bit indicates that a read request was blocked because of + bus_master_en was deasserted */ + #define PXP2_REG_PGL_READ_BLOCKED 0x120568 +@@ -2047,10 +2026,7 @@ + #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0 + #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4 + #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8 +-#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4 +-#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8 + #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4 +-#define PXP2_REG_PSWRQ_BW_ADD28 0x120228 + #define PXP2_REG_PSWRQ_BW_ADD28 0x120228 + #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8 + #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4 +@@ -2061,10 +2037,7 @@ + #define PXP2_REG_PSWRQ_BW_L1 0x1202b0 + #define PXP2_REG_PSWRQ_BW_L10 0x1202d4 + #define PXP2_REG_PSWRQ_BW_L11 0x1202d8 +-#define PXP2_REG_PSWRQ_BW_L10 0x1202d4 +-#define PXP2_REG_PSWRQ_BW_L11 0x1202d8 + #define PXP2_REG_PSWRQ_BW_L2 0x1202b4 +-#define PXP2_REG_PSWRQ_BW_L28 0x120318 + #define PXP2_REG_PSWRQ_BW_L28 0x120318 + #define PXP2_REG_PSWRQ_BW_L3 0x1202b8 + #define PXP2_REG_PSWRQ_BW_L6 0x1202c4 +@@ -2075,10 +2048,7 @@ + #define PXP2_REG_PSWRQ_BW_UB1 0x120238 + #define PXP2_REG_PSWRQ_BW_UB10 0x12025c + #define PXP2_REG_PSWRQ_BW_UB11 0x120260 +-#define PXP2_REG_PSWRQ_BW_UB10 0x12025c +-#define PXP2_REG_PSWRQ_BW_UB11 0x120260 + #define PXP2_REG_PSWRQ_BW_UB2 0x12023c +-#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0 + #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0 + #define PXP2_REG_PSWRQ_BW_UB3 0x120240 + #define PXP2_REG_PSWRQ_BW_UB6 0x12024c +@@ -2136,6 +2106,9 @@ + /* [RW 8] The maximum number of blocks in Tetris Buffer that can be + allocated for vq22 */ + #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0 ++/* [RW 8] The maximum number of blocks in Tetris Buffer that can be ++ allocated for vq25 */ ++#define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc + /* [RW 8] The maximum number of blocks in Tetris Buffer that can be + allocated for vq6 */ + #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390 +@@ -2498,6 +2471,11 @@ + considered zero so practically there are only 20 bits in this register; + queues 63-0 */ + #define QM_REG_BASEADDR 0x168900 ++/* [RW 32] The base logical address (in bytes) of each physical queue. The ++ index I represents the physical queue number. The 12 lsbs are ignore and ++ considered zero so practically there are only 20 bits in this register; ++ queues 127-64 */ ++#define QM_REG_BASEADDR_EXT_A 0x16e100 + /* [RW 16] The byte credit cost for each task. This value is for both ports */ + #define QM_REG_BYTECRDCOST 0x168234 + /* [RW 16] The initial byte credit value for both ports. */ +@@ -2662,16 +2640,6 @@ + #define QM_REG_QVOQIDX_107 0x16e4b8 + #define QM_REG_QVOQIDX_108 0x16e4bc + #define QM_REG_QVOQIDX_109 0x16e4c0 +-#define QM_REG_QVOQIDX_100 0x16e49c +-#define QM_REG_QVOQIDX_101 0x16e4a0 +-#define QM_REG_QVOQIDX_102 0x16e4a4 +-#define QM_REG_QVOQIDX_103 0x16e4a8 +-#define QM_REG_QVOQIDX_104 0x16e4ac +-#define QM_REG_QVOQIDX_105 0x16e4b0 +-#define QM_REG_QVOQIDX_106 0x16e4b4 +-#define QM_REG_QVOQIDX_107 0x16e4b8 +-#define QM_REG_QVOQIDX_108 0x16e4bc +-#define QM_REG_QVOQIDX_109 0x16e4c0 + #define QM_REG_QVOQIDX_11 0x168120 + #define QM_REG_QVOQIDX_110 0x16e4c4 + #define QM_REG_QVOQIDX_111 0x16e4c8 +@@ -2683,25 +2651,7 @@ + #define QM_REG_QVOQIDX_117 0x16e4e0 + #define QM_REG_QVOQIDX_118 0x16e4e4 + #define QM_REG_QVOQIDX_119 0x16e4e8 +-#define QM_REG_QVOQIDX_110 0x16e4c4 +-#define QM_REG_QVOQIDX_111 0x16e4c8 +-#define QM_REG_QVOQIDX_112 0x16e4cc +-#define QM_REG_QVOQIDX_113 0x16e4d0 +-#define QM_REG_QVOQIDX_114 0x16e4d4 +-#define QM_REG_QVOQIDX_115 0x16e4d8 +-#define QM_REG_QVOQIDX_116 0x16e4dc +-#define QM_REG_QVOQIDX_117 0x16e4e0 +-#define QM_REG_QVOQIDX_118 0x16e4e4 +-#define QM_REG_QVOQIDX_119 0x16e4e8 + #define QM_REG_QVOQIDX_12 0x168124 +-#define QM_REG_QVOQIDX_120 0x16e4ec +-#define QM_REG_QVOQIDX_121 0x16e4f0 +-#define QM_REG_QVOQIDX_122 0x16e4f4 +-#define QM_REG_QVOQIDX_123 0x16e4f8 +-#define QM_REG_QVOQIDX_124 0x16e4fc +-#define QM_REG_QVOQIDX_125 0x16e500 +-#define QM_REG_QVOQIDX_126 0x16e504 +-#define QM_REG_QVOQIDX_127 0x16e508 + #define QM_REG_QVOQIDX_120 0x16e4ec + #define QM_REG_QVOQIDX_121 0x16e4f0 + #define QM_REG_QVOQIDX_122 0x16e4f4 +@@ -2755,27 +2705,7 @@ + #define QM_REG_QVOQIDX_57 0x1681d8 + #define QM_REG_QVOQIDX_58 0x1681dc + #define QM_REG_QVOQIDX_59 0x1681e0 +-#define QM_REG_QVOQIDX_50 0x1681bc +-#define QM_REG_QVOQIDX_51 0x1681c0 +-#define QM_REG_QVOQIDX_52 0x1681c4 +-#define QM_REG_QVOQIDX_53 0x1681c8 +-#define QM_REG_QVOQIDX_54 0x1681cc +-#define QM_REG_QVOQIDX_55 0x1681d0 +-#define QM_REG_QVOQIDX_56 0x1681d4 +-#define QM_REG_QVOQIDX_57 0x1681d8 +-#define QM_REG_QVOQIDX_58 0x1681dc +-#define QM_REG_QVOQIDX_59 0x1681e0 + #define QM_REG_QVOQIDX_6 0x16810c +-#define QM_REG_QVOQIDX_60 0x1681e4 +-#define QM_REG_QVOQIDX_61 0x1681e8 +-#define QM_REG_QVOQIDX_62 0x1681ec +-#define QM_REG_QVOQIDX_63 0x1681f0 +-#define QM_REG_QVOQIDX_64 0x16e40c +-#define QM_REG_QVOQIDX_65 0x16e410 +-#define QM_REG_QVOQIDX_66 0x16e414 +-#define QM_REG_QVOQIDX_67 0x16e418 +-#define QM_REG_QVOQIDX_68 0x16e41c +-#define QM_REG_QVOQIDX_69 0x16e420 + #define QM_REG_QVOQIDX_60 0x1681e4 + #define QM_REG_QVOQIDX_61 0x1681e8 + #define QM_REG_QVOQIDX_62 0x1681ec +@@ -2794,27 +2724,7 @@ + #define QM_REG_QVOQIDX_77 0x16e440 + #define QM_REG_QVOQIDX_78 0x16e444 + #define QM_REG_QVOQIDX_79 0x16e448 +-#define QM_REG_QVOQIDX_70 0x16e424 +-#define QM_REG_QVOQIDX_71 0x16e428 +-#define QM_REG_QVOQIDX_72 0x16e42c +-#define QM_REG_QVOQIDX_73 0x16e430 +-#define QM_REG_QVOQIDX_74 0x16e434 +-#define QM_REG_QVOQIDX_75 0x16e438 +-#define QM_REG_QVOQIDX_76 0x16e43c +-#define QM_REG_QVOQIDX_77 0x16e440 +-#define QM_REG_QVOQIDX_78 0x16e444 +-#define QM_REG_QVOQIDX_79 0x16e448 + #define QM_REG_QVOQIDX_8 0x168114 +-#define QM_REG_QVOQIDX_80 0x16e44c +-#define QM_REG_QVOQIDX_81 0x16e450 +-#define QM_REG_QVOQIDX_82 0x16e454 +-#define QM_REG_QVOQIDX_83 0x16e458 +-#define QM_REG_QVOQIDX_84 0x16e45c +-#define QM_REG_QVOQIDX_85 0x16e460 +-#define QM_REG_QVOQIDX_86 0x16e464 +-#define QM_REG_QVOQIDX_87 0x16e468 +-#define QM_REG_QVOQIDX_88 0x16e46c +-#define QM_REG_QVOQIDX_89 0x16e470 + #define QM_REG_QVOQIDX_80 0x16e44c + #define QM_REG_QVOQIDX_81 0x16e450 + #define QM_REG_QVOQIDX_85 0x16e460 +@@ -2833,23 +2743,11 @@ + #define QM_REG_QVOQIDX_97 0x16e490 + #define QM_REG_QVOQIDX_98 0x16e494 + #define QM_REG_QVOQIDX_99 0x16e498 +-#define QM_REG_QVOQIDX_90 0x16e474 +-#define QM_REG_QVOQIDX_91 0x16e478 +-#define QM_REG_QVOQIDX_92 0x16e47c +-#define QM_REG_QVOQIDX_93 0x16e480 +-#define QM_REG_QVOQIDX_94 0x16e484 +-#define QM_REG_QVOQIDX_95 0x16e488 +-#define QM_REG_QVOQIDX_96 0x16e48c +-#define QM_REG_QVOQIDX_97 0x16e490 +-#define QM_REG_QVOQIDX_98 0x16e494 +-#define QM_REG_QVOQIDX_99 0x16e498 + /* [RW 1] Initialization bit command */ + #define QM_REG_SOFT_RESET 0x168428 + /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */ + #define QM_REG_TASKCRDCOST_0 0x16809c + #define QM_REG_TASKCRDCOST_1 0x1680a0 +-#define QM_REG_TASKCRDCOST_10 0x1680c4 +-#define QM_REG_TASKCRDCOST_11 0x1680c8 + #define QM_REG_TASKCRDCOST_2 0x1680a4 + #define QM_REG_TASKCRDCOST_4 0x1680ac + #define QM_REG_TASKCRDCOST_5 0x1680b0 +@@ -2862,24 +2760,18 @@ + /* [R 16] The credit value for each VOQ */ + #define QM_REG_VOQCREDIT_0 0x1682d0 + #define QM_REG_VOQCREDIT_1 0x1682d4 +-#define QM_REG_VOQCREDIT_10 0x1682f8 +-#define QM_REG_VOQCREDIT_11 0x1682fc + #define QM_REG_VOQCREDIT_4 0x1682e0 + /* [RW 16] The credit value that if above the QM is considered almost full */ + #define QM_REG_VOQCREDITAFULLTHR 0x168090 + /* [RW 16] The init and maximum credit for each VoQ */ + #define QM_REG_VOQINITCREDIT_0 0x168060 + #define QM_REG_VOQINITCREDIT_1 0x168064 +-#define QM_REG_VOQINITCREDIT_10 0x168088 +-#define QM_REG_VOQINITCREDIT_11 0x16808c + #define QM_REG_VOQINITCREDIT_2 0x168068 + #define QM_REG_VOQINITCREDIT_4 0x168070 + #define QM_REG_VOQINITCREDIT_5 0x168074 + /* [RW 1] The port of which VOQ belongs */ + #define QM_REG_VOQPORT_0 0x1682a0 + #define QM_REG_VOQPORT_1 0x1682a4 +-#define QM_REG_VOQPORT_10 0x1682c8 +-#define QM_REG_VOQPORT_11 0x1682cc + #define QM_REG_VOQPORT_2 0x1682a8 + /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ + #define QM_REG_VOQQMASK_0_LSB 0x168240 +@@ -2976,36 +2868,6 @@ + /* [RW 32] Wrr weights */ + #define QM_REG_WRRWEIGHTS_0 0x16880c + #define QM_REG_WRRWEIGHTS_1 0x168810 +-#define QM_REG_WRRWEIGHTS_10 0x168814 +-#define QM_REG_WRRWEIGHTS_10_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_11 0x168818 +-#define QM_REG_WRRWEIGHTS_11_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_12 0x16881c +-#define QM_REG_WRRWEIGHTS_12_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_13 0x168820 +-#define QM_REG_WRRWEIGHTS_13_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_14 0x168824 +-#define QM_REG_WRRWEIGHTS_14_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_15 0x168828 +-#define QM_REG_WRRWEIGHTS_15_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_16 0x16e000 +-#define QM_REG_WRRWEIGHTS_16_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_17 0x16e004 +-#define QM_REG_WRRWEIGHTS_17_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_18 0x16e008 +-#define QM_REG_WRRWEIGHTS_18_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_19 0x16e00c +-#define QM_REG_WRRWEIGHTS_19_SIZE 1 +-/* [RW 32] Wrr weights */ + #define QM_REG_WRRWEIGHTS_10 0x168814 + #define QM_REG_WRRWEIGHTS_11 0x168818 + #define QM_REG_WRRWEIGHTS_12 0x16881c +@@ -3018,36 +2880,6 @@ + #define QM_REG_WRRWEIGHTS_19 0x16e00c + #define QM_REG_WRRWEIGHTS_2 0x16882c + #define QM_REG_WRRWEIGHTS_20 0x16e010 +-#define QM_REG_WRRWEIGHTS_20_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_21 0x16e014 +-#define QM_REG_WRRWEIGHTS_21_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_22 0x16e018 +-#define QM_REG_WRRWEIGHTS_22_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_23 0x16e01c +-#define QM_REG_WRRWEIGHTS_23_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_24 0x16e020 +-#define QM_REG_WRRWEIGHTS_24_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_25 0x16e024 +-#define QM_REG_WRRWEIGHTS_25_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_26 0x16e028 +-#define QM_REG_WRRWEIGHTS_26_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_27 0x16e02c +-#define QM_REG_WRRWEIGHTS_27_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_28 0x16e030 +-#define QM_REG_WRRWEIGHTS_28_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_29 0x16e034 +-#define QM_REG_WRRWEIGHTS_29_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_20 0x16e010 + #define QM_REG_WRRWEIGHTS_21 0x16e014 + #define QM_REG_WRRWEIGHTS_22 0x16e018 + #define QM_REG_WRRWEIGHTS_23 0x16e01c +@@ -3059,12 +2891,6 @@ + #define QM_REG_WRRWEIGHTS_29 0x16e034 + #define QM_REG_WRRWEIGHTS_3 0x168830 + #define QM_REG_WRRWEIGHTS_30 0x16e038 +-#define QM_REG_WRRWEIGHTS_30_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_31 0x16e03c +-#define QM_REG_WRRWEIGHTS_31_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_30 0x16e038 + #define QM_REG_WRRWEIGHTS_31 0x16e03c + #define QM_REG_WRRWEIGHTS_4 0x168834 + #define QM_REG_WRRWEIGHTS_5 0x168838 +@@ -3074,362 +2900,6 @@ + #define QM_REG_WRRWEIGHTS_9 0x168848 + /* [R 6] Keep the fill level of the fifo from write client 1 */ + #define QM_REG_XQM_WRC_FIFOLVL 0x168000 +-#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) +-#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 +-#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) +-#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 +-#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) +-#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 +-#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) +-#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 +-#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define HC_HC_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define HC_HC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) +-#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 +-#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) +-#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 +-#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define PB_PB_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define PB_PB_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) +-#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 +-#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) +-#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 +-#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) +-#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 +-#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) +-#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 +-#define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define QM_QM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define QM_QM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define TM_TM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define TM_TM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) +-#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 +-#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) +-#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 +-#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) +-#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 +-#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) +-#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 +-#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) +-#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 +-#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) +-#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 +-#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) +-#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 +-#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) +-#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 +-#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) +-#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 +-#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) +-#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 +-#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) +-#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 +-#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) +-#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 +-#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) +-#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 +-#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) +-#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 +-#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) +-#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 +-#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) +-#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 +-#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) +-#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 +-#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4) +-#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4 +-/* [R 1] debug only: This bit indicates whether indicates that external +- buffer was wrapped (oldest data was thrown); Relevant only when +- ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */ +-#define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124 +-#define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1 +-/* [R 1] debug only: This bit indicates whether the internal buffer was +- wrapped (oldest data was thrown) Relevant only when +- ~dbg_registers_debug_target=0 (internal buffer) */ +-#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128 +-#define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1 +-#define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8) +-#define QM_QM_PRTY_STS_REG_WRBUFF_SIZE 8 +-#define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8) +-#define QM_QM_PRTY_STS_CLR_REG_WRBUFF_SIZE 8 +-#define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8) +-#define QM_QM_PRTY_STS_WR_REG_WRBUFF_SIZE 8 +-#define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8) +-#define QM_QM_PRTY_MASK_REG_WRBUFF_SIZE 8 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_0 0x16880c +-#define QM_REG_WRRWEIGHTS_0_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_1 0x168810 +-#define QM_REG_WRRWEIGHTS_1_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_10 0x168814 +-#define QM_REG_WRRWEIGHTS_10_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_11 0x168818 +-#define QM_REG_WRRWEIGHTS_11_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_12 0x16881c +-#define QM_REG_WRRWEIGHTS_12_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_13 0x168820 +-#define QM_REG_WRRWEIGHTS_13_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_14 0x168824 +-#define QM_REG_WRRWEIGHTS_14_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_15 0x168828 +-#define QM_REG_WRRWEIGHTS_15_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_2 0x16882c +-#define QM_REG_WRRWEIGHTS_2_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_3 0x168830 +-#define QM_REG_WRRWEIGHTS_3_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_4 0x168834 +-#define QM_REG_WRRWEIGHTS_4_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_5 0x168838 +-#define QM_REG_WRRWEIGHTS_5_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_6 0x16883c +-#define QM_REG_WRRWEIGHTS_6_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_7 0x168840 +-#define QM_REG_WRRWEIGHTS_7_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_8 0x168844 +-#define QM_REG_WRRWEIGHTS_8_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_9 0x168848 +-#define QM_REG_WRRWEIGHTS_9_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_16 0x16e000 +-#define QM_REG_WRRWEIGHTS_16_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_17 0x16e004 +-#define QM_REG_WRRWEIGHTS_17_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_18 0x16e008 +-#define QM_REG_WRRWEIGHTS_18_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_19 0x16e00c +-#define QM_REG_WRRWEIGHTS_19_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_20 0x16e010 +-#define QM_REG_WRRWEIGHTS_20_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_21 0x16e014 +-#define QM_REG_WRRWEIGHTS_21_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_22 0x16e018 +-#define QM_REG_WRRWEIGHTS_22_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_23 0x16e01c +-#define QM_REG_WRRWEIGHTS_23_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_24 0x16e020 +-#define QM_REG_WRRWEIGHTS_24_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_25 0x16e024 +-#define QM_REG_WRRWEIGHTS_25_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_26 0x16e028 +-#define QM_REG_WRRWEIGHTS_26_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_27 0x16e02c +-#define QM_REG_WRRWEIGHTS_27_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_28 0x16e030 +-#define QM_REG_WRRWEIGHTS_28_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_29 0x16e034 +-#define QM_REG_WRRWEIGHTS_29_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_30 0x16e038 +-#define QM_REG_WRRWEIGHTS_30_SIZE 1 +-/* [RW 32] Wrr weights */ +-#define QM_REG_WRRWEIGHTS_31 0x16e03c +-#define QM_REG_WRRWEIGHTS_31_SIZE 1 + #define SRC_REG_COUNTFREE0 0x40500 + /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two + ports. If set the searcher support 8 functions. */ +@@ -3438,6 +2908,16 @@ + #define SRC_REG_KEYRSS0_0 0x40408 + #define SRC_REG_KEYRSS0_7 0x40424 + #define SRC_REG_KEYRSS1_9 0x40454 ++#define SRC_REG_KEYSEARCH_0 0x40458 ++#define SRC_REG_KEYSEARCH_1 0x4045c ++#define SRC_REG_KEYSEARCH_2 0x40460 ++#define SRC_REG_KEYSEARCH_3 0x40464 ++#define SRC_REG_KEYSEARCH_4 0x40468 ++#define SRC_REG_KEYSEARCH_5 0x4046c ++#define SRC_REG_KEYSEARCH_6 0x40470 ++#define SRC_REG_KEYSEARCH_7 0x40474 ++#define SRC_REG_KEYSEARCH_8 0x40478 ++#define SRC_REG_KEYSEARCH_9 0x4047c + #define SRC_REG_LASTFREE0 0x40530 + #define SRC_REG_NUMBER_HASH_BITS0 0x40400 + /* [RW 1] Reset internal state machines. */ +@@ -3481,6 +2961,10 @@ + /* [RC 1] Message length mismatch (relative to last indication) at the In#9 + interface. */ + #define TCM_REG_CSEM_LENGTH_MIS 0x50174 ++/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for ++ weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define TCM_REG_CSEM_WEIGHT 0x500bc + /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */ + #define TCM_REG_ERR_EVNT_ID 0x500a0 + /* [RW 28] The CM erroneous header for QM and Timers formatting. */ +@@ -3515,15 +2999,10 @@ + type (one of 16). */ + #define TCM_REG_N_SM_CTX_LD_0 0x50050 + #define TCM_REG_N_SM_CTX_LD_1 0x50054 +-#define TCM_REG_N_SM_CTX_LD_10 0x50078 +-#define TCM_REG_N_SM_CTX_LD_11 0x5007c +-#define TCM_REG_N_SM_CTX_LD_12 0x50080 +-#define TCM_REG_N_SM_CTX_LD_13 0x50084 +-#define TCM_REG_N_SM_CTX_LD_14 0x50088 +-#define TCM_REG_N_SM_CTX_LD_15 0x5008c + #define TCM_REG_N_SM_CTX_LD_2 0x50058 + #define TCM_REG_N_SM_CTX_LD_3 0x5005c + #define TCM_REG_N_SM_CTX_LD_4 0x50060 ++#define TCM_REG_N_SM_CTX_LD_5 0x50064 + /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; + acknowledge output is deasserted; all other signals are treated as usual; + if 1 - normal activity. */ +@@ -3563,6 +3042,10 @@ + disregarded; acknowledge output is deasserted; all other signals are + treated as usual; if 1 - normal activity. */ + #define TCM_REG_STORM_TCM_IFEN 0x50010 ++/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for ++ weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define TCM_REG_STORM_WEIGHT 0x500ac + /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; + acknowledge output is deasserted; all other signals are treated as usual; + if 1 - normal activity. */ +@@ -3598,10 +3081,22 @@ + disregarded; acknowledge output is deasserted; all other signals are + treated as usual; if 1 - normal activity. */ + #define TCM_REG_TM_TCM_IFEN 0x5001c ++/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for ++ weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define TCM_REG_TM_WEIGHT 0x500d0 + /* [RW 6] QM output initial credit. Max credit available - 32.Write writes + the initial credit value; read returns the current value of the credit + counter. Must be initialized to 32 at start-up. */ + #define TCM_REG_TQM_INIT_CRD 0x5021c ++/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 ++ stands for weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define TCM_REG_TQM_P_WEIGHT 0x500c8 ++/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 ++ stands for weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define TCM_REG_TQM_S_WEIGHT 0x500cc + /* [RW 28] The CM header value for QM request (primary). */ + #define TCM_REG_TQM_TCM_HDR_P 0x50090 + /* [RW 28] The CM header value for QM request (secondary). */ +@@ -3628,6 +3123,10 @@ + /* [RC 1] Message length mismatch (relative to last indication) at the In#8 + interface. */ + #define TCM_REG_USEM_LENGTH_MIS 0x50170 ++/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for ++ weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define TCM_REG_USEM_WEIGHT 0x500b8 + /* [RW 21] Indirect access to the descriptor table of the XX protection + mechanism. The fields are: [5:0] - length of the message; 15:6] - message + pointer; 20:16] - next pointer. */ +@@ -3677,6 +3176,7 @@ + #define TM_REG_EN_CL1_INPUT 0x16400c + /* [RW 1] Enable client2 input. */ + #define TM_REG_EN_CL2_INPUT 0x164010 ++#define TM_REG_EN_LINEAR0_TIMER 0x164014 + /* [RW 1] Enable real time counter. */ + #define TM_REG_EN_REAL_TIME_CNT 0x1640d8 + /* [RW 1] Enable for Timers state machines. */ +@@ -3684,20 +3184,27 @@ + /* [RW 4] Load value for expiration credit cnt. CFC max number of + outstanding load requests for timers (expiration) context loading. */ + #define TM_REG_EXP_CRDCNT_VAL 0x164238 ++/* [RW 32] Linear0 logic address. */ ++#define TM_REG_LIN0_LOGIC_ADDR 0x164240 + /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */ + #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048 + /* [WB 64] Linear0 phy address. */ + #define TM_REG_LIN0_PHY_ADDR 0x164270 ++/* [RW 1] Linear0 physical address valid. */ ++#define TM_REG_LIN0_PHY_ADDR_VALID 0x164248 ++#define TM_REG_LIN0_SCAN_ON 0x1640d0 + /* [RW 24] Linear0 array scan timeout. */ + #define TM_REG_LIN0_SCAN_TIME 0x16403c ++/* [RW 32] Linear1 logic address. */ ++#define TM_REG_LIN1_LOGIC_ADDR 0x164250 + /* [WB 64] Linear1 phy address. */ + #define TM_REG_LIN1_PHY_ADDR 0x164280 ++/* [RW 1] Linear1 physical address valid. */ ++#define TM_REG_LIN1_PHY_ADDR_VALID 0x164258 + /* [RW 6] Linear timer set_clear fifo threshold. */ + #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070 + /* [RW 2] Load value for pci arbiter credit cnt. */ + #define TM_REG_PCIARB_CRDCNT_VAL 0x164260 +-/* [RW 1] Timer software reset - active high. */ +-#define TM_REG_TIMER_SOFT_RST 0x164004 + /* [RW 20] The amount of hardware cycles for each timer tick. */ + #define TM_REG_TIMER_TICK_SIZE 0x16401c + /* [RW 8] Timers Context region. */ +@@ -3708,21 +3215,13 @@ + #define TM_REG_TM_INT_STS 0x1640f0 + /* [RW 8] The event id for aggregated interrupt 0 */ + #define TSDM_REG_AGG_INT_EVENT_0 0x42038 ++#define TSDM_REG_AGG_INT_EVENT_1 0x4203c + #define TSDM_REG_AGG_INT_EVENT_2 0x42040 +-#define TSDM_REG_AGG_INT_EVENT_20 0x42088 +-#define TSDM_REG_AGG_INT_EVENT_21 0x4208c +-#define TSDM_REG_AGG_INT_EVENT_22 0x42090 +-#define TSDM_REG_AGG_INT_EVENT_23 0x42094 +-#define TSDM_REG_AGG_INT_EVENT_24 0x42098 +-#define TSDM_REG_AGG_INT_EVENT_25 0x4209c +-#define TSDM_REG_AGG_INT_EVENT_26 0x420a0 +-#define TSDM_REG_AGG_INT_EVENT_27 0x420a4 +-#define TSDM_REG_AGG_INT_EVENT_28 0x420a8 +-#define TSDM_REG_AGG_INT_EVENT_29 0x420ac + #define TSDM_REG_AGG_INT_EVENT_3 0x42044 +-#define TSDM_REG_AGG_INT_EVENT_30 0x420b0 +-#define TSDM_REG_AGG_INT_EVENT_31 0x420b4 + #define TSDM_REG_AGG_INT_EVENT_4 0x42048 ++/* [RW 1] The T bit for aggregated interrupt 0 */ ++#define TSDM_REG_AGG_INT_T_0 0x420b8 ++#define TSDM_REG_AGG_INT_T_1 0x420bc + /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ + #define TSDM_REG_CFC_RSP_START_ADDR 0x42008 + /* [RW 16] The maximum value of the competion counter #0 */ +@@ -3967,6 +3466,10 @@ + /* [RC 1] Set when the message length mismatch (relative to last indication) + at the dorq interface is detected. */ + #define UCM_REG_DORQ_LENGTH_MIS 0xe0168 ++/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for ++ weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define UCM_REG_DORQ_WEIGHT 0xe00c0 + /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */ + #define UCM_REG_ERR_EVNT_ID 0xe00a4 + /* [RW 28] The CM erroneous header for QM and Timers formatting. */ +@@ -4003,12 +3506,6 @@ + connection type (one of 16). */ + #define UCM_REG_N_SM_CTX_LD_0 0xe0054 + #define UCM_REG_N_SM_CTX_LD_1 0xe0058 +-#define UCM_REG_N_SM_CTX_LD_10 0xe007c +-#define UCM_REG_N_SM_CTX_LD_11 0xe0080 +-#define UCM_REG_N_SM_CTX_LD_12 0xe0084 +-#define UCM_REG_N_SM_CTX_LD_13 0xe0088 +-#define UCM_REG_N_SM_CTX_LD_14 0xe008c +-#define UCM_REG_N_SM_CTX_LD_15 0xe0090 + #define UCM_REG_N_SM_CTX_LD_2 0xe005c + #define UCM_REG_N_SM_CTX_LD_3 0xe0060 + #define UCM_REG_N_SM_CTX_LD_4 0xe0064 +@@ -4030,6 +3527,10 @@ + disregarded; acknowledge output is deasserted; all other signals are + treated as usual; if 1 - normal activity. */ + #define UCM_REG_STORM_UCM_IFEN 0xe0010 ++/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for ++ weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define UCM_REG_STORM_WEIGHT 0xe00b0 + /* [RW 4] Timers output initial credit. Max credit available - 15.Write + writes the initial credit value; read returns the current value of the + credit counter. Must be initialized to 4 at start-up. */ +@@ -4040,6 +3541,10 @@ + disregarded; acknowledge output is deasserted; all other signals are + treated as usual; if 1 - normal activity. */ + #define UCM_REG_TM_UCM_IFEN 0xe001c ++/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for ++ weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define UCM_REG_TM_WEIGHT 0xe00d4 + /* [RW 1] Input tsem Interface enable. If 0 - the valid input is + disregarded; acknowledge output is deasserted; all other signals are + treated as usual; if 1 - normal activity. */ +@@ -4092,6 +3597,10 @@ + stands for weight 8 (the most prioritised); 1 stands for weight 1(least + prioritised); 2 stands for weight 2; tc. */ + #define UCM_REG_UQM_P_WEIGHT 0xe00cc ++/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 ++ stands for weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define UCM_REG_UQM_S_WEIGHT 0xe00d0 + /* [RW 28] The CM header value for QM request (primary). */ + #define UCM_REG_UQM_UCM_HDR_P 0xe0094 + /* [RW 28] The CM header value for QM request (secondary). */ +@@ -4107,6 +3616,10 @@ + /* [RC 1] Set when the message length mismatch (relative to last indication) + at the SDM interface is detected. */ + #define UCM_REG_USDM_LENGTH_MIS 0xe0158 ++/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for ++ weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define UCM_REG_USDM_WEIGHT 0xe00c8 + /* [RW 1] Input xsem Interface enable. If 0 - the valid input is + disregarded; acknowledge output is deasserted; all other signals are + treated as usual; if 1 - normal activity. */ +@@ -4114,6 +3627,10 @@ + /* [RC 1] Set when the message length mismatch (relative to last indication) + at the xsem interface isdetected. */ + #define UCM_REG_XSEM_LENGTH_MIS 0xe0164 ++/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for ++ weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define UCM_REG_XSEM_WEIGHT 0xe00bc + /* [RW 20] Indirect access to the descriptor table of the XX protection + mechanism. The fields are:[5:0] - message length; 14:6] - message + pointer; 19:15] - next pointer. */ +@@ -4138,45 +3655,20 @@ + /* [RW 8] The event id for aggregated interrupt 0 */ + #define USDM_REG_AGG_INT_EVENT_0 0xc4038 + #define USDM_REG_AGG_INT_EVENT_1 0xc403c +-#define USDM_REG_AGG_INT_EVENT_10 0xc4060 +-#define USDM_REG_AGG_INT_EVENT_11 0xc4064 +-#define USDM_REG_AGG_INT_EVENT_12 0xc4068 +-#define USDM_REG_AGG_INT_EVENT_13 0xc406c +-#define USDM_REG_AGG_INT_EVENT_14 0xc4070 +-#define USDM_REG_AGG_INT_EVENT_15 0xc4074 +-#define USDM_REG_AGG_INT_EVENT_16 0xc4078 +-#define USDM_REG_AGG_INT_EVENT_17 0xc407c +-#define USDM_REG_AGG_INT_EVENT_18 0xc4080 +-#define USDM_REG_AGG_INT_EVENT_19 0xc4084 + #define USDM_REG_AGG_INT_EVENT_2 0xc4040 +-#define USDM_REG_AGG_INT_EVENT_20 0xc4088 +-#define USDM_REG_AGG_INT_EVENT_21 0xc408c +-#define USDM_REG_AGG_INT_EVENT_22 0xc4090 +-#define USDM_REG_AGG_INT_EVENT_23 0xc4094 +-#define USDM_REG_AGG_INT_EVENT_24 0xc4098 +-#define USDM_REG_AGG_INT_EVENT_25 0xc409c +-#define USDM_REG_AGG_INT_EVENT_26 0xc40a0 +-#define USDM_REG_AGG_INT_EVENT_27 0xc40a4 +-#define USDM_REG_AGG_INT_EVENT_28 0xc40a8 +-#define USDM_REG_AGG_INT_EVENT_29 0xc40ac +-#define USDM_REG_AGG_INT_EVENT_3 0xc4044 +-#define USDM_REG_AGG_INT_EVENT_30 0xc40b0 +-#define USDM_REG_AGG_INT_EVENT_31 0xc40b4 + #define USDM_REG_AGG_INT_EVENT_4 0xc4048 ++#define USDM_REG_AGG_INT_EVENT_5 0xc404c ++#define USDM_REG_AGG_INT_EVENT_6 0xc4050 + /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) + or auto-mask-mode (1) */ + #define USDM_REG_AGG_INT_MODE_0 0xc41b8 + #define USDM_REG_AGG_INT_MODE_1 0xc41bc +-#define USDM_REG_AGG_INT_MODE_10 0xc41e0 +-#define USDM_REG_AGG_INT_MODE_11 0xc41e4 +-#define USDM_REG_AGG_INT_MODE_12 0xc41e8 +-#define USDM_REG_AGG_INT_MODE_13 0xc41ec +-#define USDM_REG_AGG_INT_MODE_14 0xc41f0 +-#define USDM_REG_AGG_INT_MODE_15 0xc41f4 +-#define USDM_REG_AGG_INT_MODE_16 0xc41f8 +-#define USDM_REG_AGG_INT_MODE_17 0xc41fc +-#define USDM_REG_AGG_INT_MODE_18 0xc4200 +-#define USDM_REG_AGG_INT_MODE_19 0xc4204 ++#define USDM_REG_AGG_INT_MODE_4 0xc41c8 ++#define USDM_REG_AGG_INT_MODE_5 0xc41cc ++#define USDM_REG_AGG_INT_MODE_6 0xc41d0 ++/* [RW 1] The T bit for aggregated interrupt 5 */ ++#define USDM_REG_AGG_INT_T_5 0xc40cc ++#define USDM_REG_AGG_INT_T_6 0xc40d0 + /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ + #define USDM_REG_CFC_RSP_START_ADDR 0xc4008 + /* [RW 16] The maximum value of the competion counter #0 */ +@@ -4427,6 +3919,10 @@ + /* [RC 1] Set at message length mismatch (relative to last indication) at + the dorq interface. */ + #define XCM_REG_DORQ_LENGTH_MIS 0x20230 ++/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for ++ weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define XCM_REG_DORQ_WEIGHT 0x200cc + /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */ + #define XCM_REG_ERR_EVNT_ID 0x200b0 + /* [RW 28] The CM erroneous header for QM and Timers formatting. */ +@@ -4465,6 +3961,10 @@ + /* [RC 1] Set at message length mismatch (relative to last indication) at + the nig0 interface. */ + #define XCM_REG_NIG0_LENGTH_MIS 0x20238 ++/* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for ++ weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define XCM_REG_NIG0_WEIGHT 0x200d4 + /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is + disregarded; acknowledge output is deasserted; all other signals are + treated as usual; if 1 - normal activity. */ +@@ -4472,10 +3972,6 @@ + /* [RC 1] Set at message length mismatch (relative to last indication) at + the nig1 interface. */ + #define XCM_REG_NIG1_LENGTH_MIS 0x2023c +-/* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for +- weight 8 (the most prioritised); 1 stands for weight 1(least +- prioritised); 2 stands for weight 2; tc. */ +-#define XCM_REG_NIG1_WEIGHT 0x200d8 + /* [RW 5] The number of double REG-pairs; loaded from the STORM context and + sent to STORM; for a specific connection type. The double REG-pairs are + used in order to align to STORM context row size of 128 bits. The offset +@@ -4483,12 +3979,6 @@ + connection type (one of 16). */ + #define XCM_REG_N_SM_CTX_LD_0 0x20060 + #define XCM_REG_N_SM_CTX_LD_1 0x20064 +-#define XCM_REG_N_SM_CTX_LD_10 0x20088 +-#define XCM_REG_N_SM_CTX_LD_11 0x2008c +-#define XCM_REG_N_SM_CTX_LD_12 0x20090 +-#define XCM_REG_N_SM_CTX_LD_13 0x20094 +-#define XCM_REG_N_SM_CTX_LD_14 0x20098 +-#define XCM_REG_N_SM_CTX_LD_15 0x2009c + #define XCM_REG_N_SM_CTX_LD_2 0x20068 + #define XCM_REG_N_SM_CTX_LD_3 0x2006c + #define XCM_REG_N_SM_CTX_LD_4 0x20070 +@@ -4523,6 +4013,10 @@ + writes the initial credit value; read returns the current value of the + credit counter. Must be initialized to 4 at start-up. */ + #define XCM_REG_TM_INIT_CRD 0x2041c ++/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for ++ weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define XCM_REG_TM_WEIGHT 0x200ec + /* [RW 28] The CM header for Timers expiration command. */ + #define XCM_REG_TM_XCM_HDR 0x200a8 + /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is +@@ -4608,6 +4102,10 @@ + stands for weight 8 (the most prioritised); 1 stands for weight 1(least + prioritised); 2 stands for weight 2; tc. */ + #define XCM_REG_XQM_P_WEIGHT 0x200e4 ++/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 ++ stands for weight 8 (the most prioritised); 1 stands for weight 1(least ++ prioritised); 2 stands for weight 2; tc. */ ++#define XCM_REG_XQM_S_WEIGHT 0x200e8 + /* [RW 28] The CM header value for QM request (primary). */ + #define XCM_REG_XQM_XCM_HDR_P 0x200a0 + /* [RW 28] The CM header value for QM request (secondary). */ +@@ -4657,28 +4155,8 @@ + #define XSDM_REG_AGG_INT_EVENT_12 0x166068 + #define XSDM_REG_AGG_INT_EVENT_13 0x16606c + #define XSDM_REG_AGG_INT_EVENT_14 0x166070 +-#define XSDM_REG_AGG_INT_EVENT_15 0x166074 +-#define XSDM_REG_AGG_INT_EVENT_16 0x166078 +-#define XSDM_REG_AGG_INT_EVENT_17 0x16607c +-#define XSDM_REG_AGG_INT_EVENT_18 0x166080 +-#define XSDM_REG_AGG_INT_EVENT_19 0x166084 +-#define XSDM_REG_AGG_INT_EVENT_10 0x166060 +-#define XSDM_REG_AGG_INT_EVENT_11 0x166064 +-#define XSDM_REG_AGG_INT_EVENT_12 0x166068 + #define XSDM_REG_AGG_INT_EVENT_2 0x166040 +-#define XSDM_REG_AGG_INT_EVENT_20 0x166088 +-#define XSDM_REG_AGG_INT_EVENT_21 0x16608c +-#define XSDM_REG_AGG_INT_EVENT_22 0x166090 +-#define XSDM_REG_AGG_INT_EVENT_23 0x166094 +-#define XSDM_REG_AGG_INT_EVENT_24 0x166098 +-#define XSDM_REG_AGG_INT_EVENT_25 0x16609c +-#define XSDM_REG_AGG_INT_EVENT_26 0x1660a0 +-#define XSDM_REG_AGG_INT_EVENT_27 0x1660a4 +-#define XSDM_REG_AGG_INT_EVENT_28 0x1660a8 +-#define XSDM_REG_AGG_INT_EVENT_29 0x1660ac + #define XSDM_REG_AGG_INT_EVENT_3 0x166044 +-#define XSDM_REG_AGG_INT_EVENT_30 0x1660b0 +-#define XSDM_REG_AGG_INT_EVENT_31 0x1660b4 + #define XSDM_REG_AGG_INT_EVENT_4 0x166048 + #define XSDM_REG_AGG_INT_EVENT_5 0x16604c + #define XSDM_REG_AGG_INT_EVENT_6 0x166050 +@@ -4689,16 +4167,6 @@ + or auto-mask-mode (1) */ + #define XSDM_REG_AGG_INT_MODE_0 0x1661b8 + #define XSDM_REG_AGG_INT_MODE_1 0x1661bc +-#define XSDM_REG_AGG_INT_MODE_10 0x1661e0 +-#define XSDM_REG_AGG_INT_MODE_11 0x1661e4 +-#define XSDM_REG_AGG_INT_MODE_12 0x1661e8 +-#define XSDM_REG_AGG_INT_MODE_13 0x1661ec +-#define XSDM_REG_AGG_INT_MODE_14 0x1661f0 +-#define XSDM_REG_AGG_INT_MODE_15 0x1661f4 +-#define XSDM_REG_AGG_INT_MODE_16 0x1661f8 +-#define XSDM_REG_AGG_INT_MODE_17 0x1661fc +-#define XSDM_REG_AGG_INT_MODE_18 0x166200 +-#define XSDM_REG_AGG_INT_MODE_19 0x166204 + /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ + #define XSDM_REG_CFC_RSP_START_ADDR 0x166008 + /* [RW 16] The maximum value of the competion counter #0 */ +@@ -4906,10 +4374,6 @@ + #define MCPR_NVM_COMMAND_FIRST (1L<<7) + #define MCPR_NVM_COMMAND_LAST (1L<<8) + #define MCPR_NVM_COMMAND_WR (1L<<5) +-#define MCPR_NVM_COMMAND_WREN (1L<<16) +-#define MCPR_NVM_COMMAND_WREN_BITSHIFT 16 +-#define MCPR_NVM_COMMAND_WRDI (1L<<17) +-#define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17 + #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9) + #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) + #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) +@@ -4927,6 +4391,15 @@ + #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) + #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) + #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) ++#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3) ++#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) ++#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3) ++#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3) ++#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3) ++#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3) ++#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3) ++#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3) ++#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3) + #define EMAC_LED_1000MB_OVERRIDE (1L<<1) + #define EMAC_LED_100MB_OVERRIDE (1L<<2) + #define EMAC_LED_10MB_OVERRIDE (1L<<3) +@@ -4939,7 +4412,7 @@ + #define EMAC_MDIO_COMM_DATA (0xffffL<<0) + #define EMAC_MDIO_COMM_START_BUSY (1L<<29) + #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) +-#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) ++#define EMAC_MDIO_MODE_CLAUSE_45 (1<<31) + #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16) + #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 + #define EMAC_MODE_25G_MODE (1L<<5) +@@ -4964,9 +4437,11 @@ + #define EMAC_RX_MODE_FLOW_EN (1L<<2) + #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) + #define EMAC_RX_MODE_PROMISCUOUS (1L<<8) +-#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) ++#define EMAC_RX_MODE_RESET (1L<<0) ++#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1<<31) + #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) + #define EMAC_TX_MODE_FLOW_EN (1L<<4) ++#define EMAC_TX_MODE_RESET (1L<<0) + #define MISC_REGISTERS_GPIO_0 0 + #define MISC_REGISTERS_GPIO_1 1 + #define MISC_REGISTERS_GPIO_2 2 +@@ -4976,6 +4451,10 @@ + #define MISC_REGISTERS_GPIO_FLOAT_POS 24 + #define MISC_REGISTERS_GPIO_HIGH 1 + #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 ++#define MISC_REGISTERS_GPIO_INT_CLR_POS 24 ++#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0 ++#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1 ++#define MISC_REGISTERS_GPIO_INT_SET_POS 16 + #define MISC_REGISTERS_GPIO_LOW 0 + #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 + #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 +@@ -5004,10 +4483,6 @@ + #define MISC_REGISTERS_SPIO_7 7 + #define MISC_REGISTERS_SPIO_CLR_POS 16 + #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24) +-#define GRC_MISC_REGISTERS_SPIO_FLOAT7 0x80000000 +-#define GRC_MISC_REGISTERS_SPIO_FLOAT6 0x40000000 +-#define GRC_MISC_REGISTERS_SPIO_FLOAT5 0x20000000 +-#define GRC_MISC_REGISTERS_SPIO_FLOAT4 0x10000000 + #define MISC_REGISTERS_SPIO_FLOAT_POS 24 + #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2 + #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16 +@@ -5015,58 +4490,61 @@ + #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0 + #define MISC_REGISTERS_SPIO_SET_POS 8 + #define HW_LOCK_MAX_RESOURCE_VALUE 31 +-#define HW_LOCK_RESOURCE_8072_MDIO 0 + #define HW_LOCK_RESOURCE_GPIO 1 ++#define HW_LOCK_RESOURCE_MDIO 0 + #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 + #define HW_LOCK_RESOURCE_SPIO 2 + #define HW_LOCK_RESOURCE_UNDI 5 +-#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) +-#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) +-#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) +-#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8) +-#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7) +-#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6) +-#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29) +-#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28) +-#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1) +-#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0) +-#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18) +-#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11) +-#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13) +-#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12) +-#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12) +-#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15) +-#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14) +-#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20) +-#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0) +-#define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31) +-#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3) +-#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2) +-#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5) +-#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4) +-#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3) +-#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2) +-#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22) +-#define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15) +-#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27) +-#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5) +-#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25) +-#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24) +-#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29) +-#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28) +-#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23) +-#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27) +-#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26) +-#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21) +-#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20) +-#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25) +-#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24) +-#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16) +-#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9) +-#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7) +-#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6) +-#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11) +-#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10) ++#define PRS_FLAG_OVERETH_IPV4 1 ++#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1UL<<18) ++#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1UL<<31) ++#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1UL<<9) ++#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1UL<<8) ++#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1UL<<7) ++#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1UL<<6) ++#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1UL<<29) ++#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1UL<<28) ++#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1UL<<1) ++#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1UL<<0) ++#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1UL<<18) ++#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1UL<<11) ++#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1UL<<13) ++#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1UL<<12) ++#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1UL<<5) ++#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1UL<<9) ++#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1UL<<12) ++#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1UL<<15) ++#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1UL<<14) ++#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1UL<<20) ++#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1UL<<0) ++#define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1UL<<31) ++#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1UL<<3) ++#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1UL<<2) ++#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1UL<<5) ++#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1UL<<4) ++#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1UL<<3) ++#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1UL<<2) ++#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1UL<<22) ++#define AEU_INPUTS_ATTN_BITS_SPIO5 (1UL<<15) ++#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1UL<<27) ++#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1UL<<5) ++#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1UL<<25) ++#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1UL<<24) ++#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1UL<<29) ++#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1UL<<28) ++#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1UL<<23) ++#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1UL<<27) ++#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1UL<<26) ++#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1UL<<21) ++#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1UL<<20) ++#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1UL<<25) ++#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1UL<<24) ++#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1UL<<16) ++#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1UL<<9) ++#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1UL<<7) ++#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1UL<<6) ++#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1UL<<11) ++#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1UL<<10) + #define RESERVED_GENERAL_ATTENTION_BIT_0 0 + + #define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0 +@@ -5122,7 +4600,8 @@ + #define LATCHED_ATTN_SCPAD_PARITY_MCP 33 + + #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32) +-#define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32)) ++#define GENERAL_ATTEN_OFFSET(atten_name)\ ++ (1UL << ((94 + atten_name) % 32)) + /* + * This file defines GRC base address for every block. + * This file is included by chipsim, asm microcode and cpp microcode. +@@ -5188,7 +4667,7 @@ + #define PCICFG_COMMAND_INT_DISABLE (1<<10) + #define PCICFG_COMMAND_RESERVED (0x1f<<11) + #define PCICFG_STATUS_OFFSET 0x06 +-#define PCICFG_REVESION_ID 0x08 ++#define PCICFG_REVESION_ID_OFFSET 0x08 + #define PCICFG_CACHE_LINE_SIZE 0x0c + #define PCICFG_LATENCY_TIMER 0x0d + #define PCICFG_BAR_1_LOW 0x10 +@@ -5216,9 +4695,28 @@ + #define PCICFG_PM_CSR_STATE (0x3<<0) + #define PCICFG_PM_CSR_PME_ENABLE (1<<8) + #define PCICFG_PM_CSR_PME_STATUS (1<<15) ++#define PCICFG_MSI_CAP_ID_OFFSET 0x58 ++#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) ++#define PCICFG_MSI_CONTROL_MCAP (0x7<<17) ++#define PCICFG_MSI_CONTROL_MENA (0x7<<20) ++#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) ++#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) + #define PCICFG_GRC_ADDRESS 0x78 + #define PCICFG_GRC_DATA 0x80 ++#define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 ++#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) ++#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) ++#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) ++#define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) ++ + #define PCICFG_DEVICE_CONTROL 0xb4 ++#define PCICFG_DEVICE_STATUS 0xb6 ++#define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) ++#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) ++#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) ++#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) ++#define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) ++#define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) + #define PCICFG_LINK_CONTROL 0xbc + + +@@ -5233,6 +4731,11 @@ + #define BAR_DOORBELL_OFFSET 0x800000 + + #define BAR_ME_REGISTER 0x450000 ++#define ME_REG_PF_NUM (7L<<0) /* Relative PF Num */ ++#define ME_REG_PF_NUM_SHIFT 0 ++#define ME_REG_ABS_PF_NUM (7L<<16) /* Absolute PF Num */ ++#define ME_REG_ABS_PF_NUM_SHIFT 16 ++ + + /* config_2 offset */ + #define GRC_CONFIG_2_SIZE_REG 0x408 +@@ -5279,12 +4782,12 @@ + + /* config_3 offset */ + #define GRC_CONFIG_3_SIZE_REG 0x40c +-#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) ++#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) + #define PCI_CONFIG_3_FORCE_PME (1L<<24) + #define PCI_CONFIG_3_PME_STATUS (1L<<25) + #define PCI_CONFIG_3_PME_ENABLE (1L<<26) + #define PCI_CONFIG_3_PM_STATE (0x3L<<27) +-#define PCI_CONFIG_3_VAUX_PRESET (1L<<30) ++#define PCI_CONFIG_3_VAUX_PRESET (1L<<30) + #define PCI_CONFIG_3_PCI_POWER (1L<<31) + + #define GRC_BAR2_CONFIG 0x4e0 +@@ -5353,6 +4856,42 @@ + + #define MDIO_REG_BANK_TX0 0x8060 + #define MDIO_TX0_TX_DRIVER 0x17 ++#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 ++#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 ++#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 ++#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 ++#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 ++#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 ++#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e ++#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 ++#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 ++ ++#define MDIO_REG_BANK_TX1 0x8070 ++#define MDIO_TX1_TX_DRIVER 0x17 ++#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 ++#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 ++#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 ++#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 ++#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 ++#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 ++#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e ++#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 ++#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 ++ ++#define MDIO_REG_BANK_TX2 0x8080 ++#define MDIO_TX2_TX_DRIVER 0x17 ++#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 ++#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 ++#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 ++#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 ++#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 ++#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 ++#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e ++#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 ++#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 ++ ++#define MDIO_REG_BANK_TX3 0x8090 ++#define MDIO_TX3_TX_DRIVER 0x17 + #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 + #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 + #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 +@@ -5566,13 +5105,46 @@ + #define MDIO_PMA_REG_ROM_VER2 0xca1a + #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b + #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d ++#define MDIO_PMA_REG_PLL_CTRL 0xca1e ++#define MDIO_PMA_REG_MISC_CTRL0 0xca23 ++#define MDIO_PMA_REG_LRM_MODE 0xca3f + #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 + #define MDIO_PMA_REG_MISC_CTRL1 0xca85 ++ ++#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000 ++#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c ++#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 ++#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 ++#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 ++#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c ++#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002 ++#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003 ++#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 ++#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff ++#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 ++#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 ++ ++#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005 ++#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007 ++#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff ++#define MDIO_PMA_REG_8727_MISC_CTRL 0x8309 ++#define MDIO_PMA_REG_8727_TX_CTRL1 0xca02 ++#define MDIO_PMA_REG_8727_TX_CTRL2 0xca05 ++#define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808 ++#define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e ++ ++#define MDIO_PMA_REG_8073_CHIP_REV 0xc801 ++#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 ++#define MDIO_PMA_REG_8073_XAUI_WA 0xc841 + + #define MDIO_PMA_REG_7101_RESET 0xc000 + #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 + #define MDIO_PMA_REG_7101_VER1 0xc026 + #define MDIO_PMA_REG_7101_VER2 0xc027 ++ ++#define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811 ++#define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835 ++#define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b + + + #define MDIO_WIS_DEVAD 0x2 +@@ -5597,6 +5169,12 @@ + #define MDIO_XS_DEVAD 0x4 + #define MDIO_XS_PLL_SEQUENCER 0x8000 + #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a ++ ++#define MDIO_XS_8706_REG_BANK_RX0 0x80bc ++#define MDIO_XS_8706_REG_BANK_RX1 0x80cc ++#define MDIO_XS_8706_REG_BANK_RX2 0x80dc ++#define MDIO_XS_8706_REG_BANK_RX3 0x80ec ++#define MDIO_XS_8706_REG_BANK_RXA 0x80fc + + #define MDIO_AN_DEVAD 0x7 + /*ieee*/ +@@ -5619,6 +5197,14 @@ + #define MDIO_AN_REG_CL37_FC_LD 0xffe4 + #define MDIO_AN_REG_CL37_FC_LP 0xffe5 + ++#define MDIO_AN_REG_8073_2_5G 0x8329 ++ ++#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 ++#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 ++#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 ++#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 ++#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 ++#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc + + #define IGU_FUNC_BASE 0x0400 + +@@ -5651,3 +5237,114 @@ + #define COMMAND_REG_SIMD_NOMASK 0x1c + + ++#define IGU_MEM_BASE 0x0000 ++ ++#define IGU_MEM_MSIX_BASE 0x0000 ++#define IGU_MEM_MSIX_UPPER 0x007f ++#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff ++ ++#define IGU_MEM_PBA_MSIX_BASE 0x0200 ++#define IGU_MEM_PBA_MSIX_UPPER 0x0200 ++ ++#define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201 ++#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff ++ ++#define IGU_CMD_INT_ACK_BASE 0x0400 ++#define IGU_CMD_INT_ACK_UPPER\ ++ (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1) ++#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff ++ ++#define IGU_CMD_E2_PROD_UPD_BASE 0x0500 ++#define IGU_CMD_E2_PROD_UPD_UPPER\ ++ (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1) ++#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f ++ ++#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0 ++#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1 ++#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2 ++ ++#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3 ++#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4 ++#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5 ++#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6 ++ ++#define IGU_REG_RESERVED_UPPER 0x05ff ++ ++ ++#define CDU_REGION_NUMBER_XCM_AG 2 ++#define CDU_REGION_NUMBER_UCM_AG 4 ++ ++ ++/** ++ * String-to-compress [31:8] = CID (all 24 bits) ++ * String-to-compress [7:4] = Region ++ * String-to-compress [3:0] = Type ++ */ ++#define CDU_VALID_DATA(_cid, _region, _type)\ ++ (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf))) ++#define CDU_CRC8(_cid, _region, _type)\ ++ (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)) ++#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\ ++ (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f)) ++#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\ ++ (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7)) ++#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) ++ ++/****************************************************************************** ++ * Description: ++ * Calculates crc 8 on a word value: polynomial 0-1-2-8 ++ * Code was translated from Verilog. ++ * Return: ++ *****************************************************************************/ ++static inline u8 calc_crc8(u32 data, u8 crc) ++{ ++ u8 D[32]; ++ u8 NewCRC[8]; ++ u8 C[8]; ++ u8 crc_res; ++ u8 i; ++ ++ /* split the data into 31 bits */ ++ for (i = 0; i < 32; i++) { ++ D[i] = (u8)(data & 1); ++ data = data >> 1; ++ } ++ ++ /* split the crc into 8 bits */ ++ for (i = 0; i < 8; i++ ) { ++ C[i] = crc & 1; ++ crc = crc >> 1; ++ } ++ ++ NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ ++ D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ ++ C[6] ^ C[7]; ++ NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^ ++ D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ ++ D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6]; ++ NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^ ++ D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ ++ C[0] ^ C[1] ^ C[4] ^ C[5]; ++ NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ ++ D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ ++ C[1] ^ C[2] ^ C[5] ^ C[6]; ++ NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^ ++ D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ ++ C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; ++ NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^ ++ D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ ++ C[3] ^ C[4] ^ C[7]; ++ NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^ ++ D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ C[5]; ++ NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^ ++ D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ C[6]; ++ ++ crc_res = 0; ++ for (i = 0; i < 8; i++) { ++ crc_res |= (NewCRC[i] << i); ++ } ++ ++ return crc_res; ++} ++ ++ +diff -r e67cb9a8e847 drivers/net/bnx2x_self_test.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/bnx2x_self_test.h Wed Aug 05 10:51:03 2009 +0100 +@@ -0,0 +1,1004 @@ ++/* bnx2x_self_test.h: Broadcom Everest network driver. ++ * ++ * Copyright (c) 2007-2009 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation. ++ * ++ * Maintained by: Eilon Greenstein ++ * Written by: Yitchak Gertner ++ */ ++ ++/* self test */ ++ ++static int idle_chk_errors; ++static int idle_chk_warnings; ++ ++ ++#define IDLE_CHK_E1 0x1 ++#define IDLE_CHK_E1H 0x2 ++ ++#define IDLE_CHK_ERROR 1 ++#define IDLE_CHK_ERROR_NO_TRAFFIC 2 ++#define IDLE_CHK_WARNING 3 ++ ++ ++#define CHIP_MASK_CHK(chip_mask) \ ++ (((((chip_mask) & IDLE_CHK_E1) && is_e1) || \ ++ (((chip_mask) & IDLE_CHK_E1H) && is_e1h)) ? 1 : 0) ++ ++#define CONDITION_CHK(condition, severity, fail_msg, arg_list...) \ ++ do { \ ++ if (condition) { \ ++ switch (severity) { \ ++ case IDLE_CHK_ERROR: \ ++ BNX2X_DBG_ERR("ERROR " fail_msg, ##arg_list); \ ++ idle_chk_errors++; \ ++ break; \ ++ case IDLE_CHK_ERROR_NO_TRAFFIC: \ ++ BNX2X_DBG_ERR("INFO " fail_msg, ##arg_list); \ ++ break; \ ++ case IDLE_CHK_WARNING: \ ++ BNX2X_DBG_ERR("WARNING " fail_msg, \ ++ ##arg_list); \ ++ idle_chk_warnings++; \ ++ break; \ ++ } \ ++ } \ ++ } while (0); ++ ++ ++static void bnx2x_idle_chk6(struct bnx2x *bp, u32 chip_mask, u32 offset, ++ int loop, int inc, int severity) ++{ ++ int is_e1 = CHIP_IS_E1(bp); ++ int is_e1h = CHIP_IS_E1H(bp); ++ int i; ++ u32 val1, val2; ++ u32 rd_ptr, wr_ptr, rd_bank, wr_bank; ++ ++ if (!CHIP_MASK_CHK(chip_mask)) ++ return; ++ ++ for (i = 0; i < loop; i++) { ++ val1 = REG_RD(bp, offset + i*inc); ++ val2 = REG_RD(bp, offset + i*inc + 4); ++ rd_ptr = ((val1 & 0x3FFFFFC0) >> 6); ++ wr_ptr = ((((val1 & 0xC0000000) >> 30) & 0x3) | ++ ((val2 & 0x3FFFFF) << 2)); ++ CONDITION_CHK((rd_ptr != wr_ptr), severity, ++ "QM: PTRTBL entry %d - rd_ptr is not" ++ " equal to wr_ptr. Values are 0x%x 0x%x\n", ++ i, rd_ptr, wr_ptr); ++ rd_bank = ((val1 & 0x30) >> 4); ++ wr_bank = (val1 & 0x03); ++ CONDITION_CHK((rd_bank != wr_bank), severity, ++ "QM: PTRTBL entry %d - rd_bank is not" ++ " equal to wr_bank. Values are 0x%x 0x%x\n", ++ i, rd_bank, wr_bank); ++ } ++} ++ ++static int bnx2x_idle_chk(struct bnx2x *bp) ++{ ++ ++/* read one reg and check the condition */ ++#define IDLE_CHK_1(chip_mask, offset, condition, severity, fail_msg) \ ++ do { \ ++ if (CHIP_MASK_CHK(chip_mask)) { \ ++ val = REG_RD(bp, offset); \ ++ CONDITION_CHK(condition, severity, \ ++ fail_msg ". Value is 0x%x\n", val); \ ++ } \ ++ } while (0); ++ ++/* loop to read one reg and check the condition */ ++#define IDLE_CHK_2(chip_mask, offset, loop, inc, condition, severity, \ ++ fail_msg) \ ++ do { \ ++ if (CHIP_MASK_CHK(chip_mask)) \ ++ for (i = 0; i < (loop); i++) { \ ++ val = REG_RD(bp, offset + i*(inc)); \ ++ CONDITION_CHK(condition, severity, \ ++ fail_msg ". Value is 0x%x\n", \ ++ i, val); \ ++ } \ ++ } while (0); ++ ++/* read two regs and check the condition */ ++#define IDLE_CHK_3(chip_mask, offset1, offset2, condition, severity, \ ++ fail_msg) \ ++ do { \ ++ if (CHIP_MASK_CHK(chip_mask)) { \ ++ val1 = REG_RD(bp, offset1); \ ++ val2 = REG_RD(bp, offset2); \ ++ CONDITION_CHK(condition, severity, \ ++ fail_msg ". Values are 0x%x 0x%x\n", \ ++ val1, val2); \ ++ } \ ++ } while (0); ++ ++/* loop to read two regs and check the condition */ ++#define IDLE_CHK_4(chip_mask, offset1, offset2, loop, inc, condition, \ ++ severity, fail_msg) \ ++ do { \ ++ if (CHIP_MASK_CHK(chip_mask)) \ ++ for (i = 0; i < (loop); i++) { \ ++ val1 = REG_RD(bp, offset1 + i*(inc)); \ ++ val2 = (REG_RD(bp, offset2 + i*(inc)) >> 1); \ ++ CONDITION_CHK(condition, severity, fail_msg \ ++ " - LCID %d CID_CAM 0x%x" \ ++ " Value is 0x%x\n", \ ++ i, val2, val1); \ ++ } \ ++ } while (0); ++ ++/* read one reg and check according to another reg */ ++#define IDLE_CHK_5(chip_mask, offset, offset1, offset2, condition, severity, \ ++ fail_msg) \ ++ do { \ ++ if (CHIP_MASK_CHK(chip_mask)) \ ++ if (!REG_RD(bp, offset)) \ ++ IDLE_CHK_3(chip_mask, offset1, offset2, \ ++ condition, severity, fail_msg); \ ++ } while (0); ++ ++/* read wide-bus reg and check sub-fields */ ++#define IDLE_CHK_6(chip_mask, offset, loop, inc, severity) \ ++ bnx2x_idle_chk6(bp, chip_mask, offset, loop, inc, severity) ++ ++/* loop to read wide-bus reg and check according to another reg */ ++#define IDLE_CHK_7(chip_mask, offset, offset1, offset2, loop, inc, condition, \ ++ severity, fail_msg) \ ++ do { \ ++ if (CHIP_MASK_CHK(chip_mask)) \ ++ for (i = 0; i < (loop); i++) { \ ++ if (REG_RD(bp, offset + i*4) == 1) { \ ++ val1 = REG_RD(bp, offset1 + i*(inc)); \ ++ val1 = REG_RD(bp, offset1 + i*(inc) + \ ++ 4); \ ++ val1 = ((REG_RD(bp, offset1 + i*(inc) \ ++ + 8) & 0x00000078) >> 3); \ ++ val2 = (REG_RD(bp, offset2 + i*4)>>1); \ ++ CONDITION_CHK(condition, severity, \ ++ fail_msg " - LCID %d " \ ++ "CID_CAM 0x%x" \ ++ " Value is 0x%x\n", \ ++ i, val2, val1); \ ++ } \ ++ } \ ++ } while (0); ++ ++ ++ int is_e1 = CHIP_IS_E1(bp); ++ int is_e1h = CHIP_IS_E1H(bp); ++ int i; ++ u32 val, val1, val2; ++ ++ idle_chk_errors = 0; ++ idle_chk_warnings = 0; ++ ++ if (!netif_running(bp->dev)) ++ return idle_chk_errors; ++ ++ IDLE_CHK_1(0x7, 0x2114, ((val & 0x0ff010) != 0), IDLE_CHK_ERROR, ++ "PCIE: ucorr_err_status is not 0"); ++ IDLE_CHK_1(0x7, 0x2114, ((val & 0x100000) != 0), IDLE_CHK_WARNING, ++ "PCIE: ucorr_err_status - Unsupported request error"); ++ IDLE_CHK_1(0x7, 0x2120, ++ (((val & 0x31c1) != 0x2000) && ((val & 0x31c1) != 0)), ++ IDLE_CHK_WARNING, "PCIE: corr_err_status is not 0x2000"); ++ IDLE_CHK_1(0x7, 0x2814, ((val & ~0x40100) != 0), IDLE_CHK_ERROR, ++ "PCIE: attentions register is not 0x40100"); ++ IDLE_CHK_1(0x6, 0x281c, ((val & ~0x40040100) != 0), IDLE_CHK_ERROR, ++ "PCIE: attentions register is not 0x40040100"); ++ IDLE_CHK_1(0x6, 0x2820, ((val & ~0x40040100) != 0), IDLE_CHK_ERROR, ++ "PCIE: attentions register is not 0x40040100"); ++ IDLE_CHK_1(0x1, PXP2_REG_PGL_EXP_ROM2, (val != 0xffffffff), ++ IDLE_CHK_WARNING, ++ "PXP2: There are outstanding read requests. Not all" ++ " completions have arrived for read requests on tags that" ++ " are marked with 0"); ++ IDLE_CHK_2(0x7, 0x212c, 4, 4, ((val != 0) && (idle_chk_errors > 0)), ++ IDLE_CHK_WARNING, "PCIE: error packet header %d is not 0"); ++ ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ0_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ0 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ1_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ1 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ2_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ2 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ3_ENTRY_CNT, (val > 2), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ3 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ4_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ4 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ5_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ5 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ6_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ6 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ7_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ7 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ8_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ8 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ9_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ9 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ10_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ10 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ11_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ11 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ12_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ12 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ13_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ13 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ14_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ14 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ15_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ15 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ16_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ16 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ17_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ17 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ18_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ18 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ19_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ19 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ20_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ20 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ21_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ21 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ22_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ22 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ23_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ23 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ24_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ24 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ25_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ25 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ26_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ26 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ27_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ27 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ28_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ28 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ29_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ29 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ30_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ30 is not empty"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ31_ENTRY_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ31 is not empty"); ++ ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY, (val != 0), ++ IDLE_CHK_ERROR, "PXP2: rq_ufifo_num_of_entry is not 0"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_RBC_DONE, (val != 1), IDLE_CHK_ERROR, ++ "PXP2: rq_rbc_done is not 1"); ++ IDLE_CHK_1(0x7, PXP2_REG_RQ_CFG_DONE, (val != 1), IDLE_CHK_ERROR, ++ "PXP2: rq_cfg_done is not 1"); ++ IDLE_CHK_1(0x7, PXP2_REG_PSWRQ_BW_CREDIT, (val != 0x1b), ++ IDLE_CHK_ERROR, ++ "PXP2: rq_read_credit and rq_write_credit are not 3"); ++ IDLE_CHK_1(0x7, PXP2_REG_RD_START_INIT, (val != 1), IDLE_CHK_ERROR, ++ "PXP2: rd_start_init is not 1"); ++ IDLE_CHK_1(0x7, PXP2_REG_RD_INIT_DONE, (val != 1), IDLE_CHK_ERROR, ++ "PXP2: rd_init_done is not 1"); ++ ++ IDLE_CHK_3(0x7, PXP2_REG_RD_SR_CNT, PXP2_REG_RD_SR_NUM_CFG, ++ (val1 != (val2-1)), IDLE_CHK_WARNING, ++ "PXP2: rd_sr_cnt is not equal to rd_sr_num_cfg"); ++ IDLE_CHK_3(0x7, PXP2_REG_RD_BLK_CNT, PXP2_REG_RD_BLK_NUM_CFG, ++ (val1 != val2), IDLE_CHK_WARNING, ++ "PXP2: rd_blk_cnt is not equal to rd_blk_num_cfg"); ++ ++ IDLE_CHK_3(0x7, PXP2_REG_RD_SR_CNT, PXP2_REG_RD_SR_NUM_CFG, ++ (val1 < (val2-3)), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PXP2: There are more than two unused SRs"); ++ IDLE_CHK_3(0x7, PXP2_REG_RD_BLK_CNT, PXP2_REG_RD_BLK_NUM_CFG, ++ (val1 < (val2-2)), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PXP2: There are more than two unused blocks"); ++ ++ IDLE_CHK_1(0x7, PXP2_REG_RD_PORT_IS_IDLE_0, (val != 1), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PXP2: P0 All delivery ports are not idle"); ++ IDLE_CHK_1(0x7, PXP2_REG_RD_PORT_IS_IDLE_1, (val != 1), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PXP2: P1 All delivery ports are not idle"); ++ ++ IDLE_CHK_2(0x7, PXP2_REG_RD_ALMOST_FULL_0, 11, 4, (val != 0), ++ IDLE_CHK_ERROR, "PXP2: rd_almost_full_%d is not 0"); ++ ++ IDLE_CHK_1(0x7, PXP2_REG_RD_DISABLE_INPUTS, (val != 0), ++ IDLE_CHK_ERROR, "PXP2: PSWRD inputs are disabled"); ++ IDLE_CHK_1(0x7, PXP2_REG_HST_HEADER_FIFO_STATUS, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PXP2: HST header FIFO status is not 0"); ++ IDLE_CHK_1(0x7, PXP2_REG_HST_DATA_FIFO_STATUS, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PXP2: HST data FIFO status is not 0"); ++ IDLE_CHK_1(0x7, PXP2_REG_PGL_WRITE_BLOCKED, (val != 0), ++ IDLE_CHK_ERROR, "PXP2: pgl_write_blocked is not 0"); ++ IDLE_CHK_1(0x7, PXP2_REG_PGL_READ_BLOCKED, (val != 0), IDLE_CHK_ERROR, ++ "PXP2: pgl_read_blocked is not 0"); ++ IDLE_CHK_1(0x7, PXP2_REG_PGL_TXW_CDTS, (((val >> 17) & 1) != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PXP2: There is data which is ready"); ++ ++ IDLE_CHK_1(0x7, PXP_REG_HST_ARB_IS_IDLE, (val != 1), IDLE_CHK_WARNING, ++ "PXP: HST arbiter is not idle"); ++ IDLE_CHK_1(0x7, PXP_REG_HST_CLIENTS_WAITING_TO_ARB, (val != 0), ++ IDLE_CHK_WARNING, ++ "PXP: HST one of the clients is waiting for delivery"); ++ IDLE_CHK_1(0x6, PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS, ++ (val != 0), IDLE_CHK_WARNING, ++ "PXP: HST Close the gates: Discarding internal writes"); ++ IDLE_CHK_1(0x6, PXP_REG_HST_DISCARD_DOORBELLS_STATUS, (val != 0), ++ IDLE_CHK_WARNING, ++ "PXP: HST Close the gates: Discarding doorbells"); ++ ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C0, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "DMAE: command 0 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C1, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "DMAE: command 1 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C2, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "DMAE: command 2 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C3, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "DMAE: command 3 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "DMAE: command 4 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C5, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "DMAE: command 5 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C6, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "DMAE: command 6 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C7, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "DMAE: command 7 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C8, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "DMAE: command 8 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C9, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "DMAE: command 9 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C10, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 10 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C11, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 11 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C12, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 12 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C13, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 13 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C14, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 14 go is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_GO_C15, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 15 go is not 0"); ++ ++ IDLE_CHK_1(0x7, CFC_REG_ERROR_VECTOR, (val != 0), IDLE_CHK_ERROR, ++ "CFC: error vector is not 0"); ++ IDLE_CHK_1(0x7, CFC_REG_NUM_LCIDS_ARRIVING, (val != 0), ++ IDLE_CHK_ERROR, "CFC: number of arriving LCIDs is not 0"); ++ IDLE_CHK_1(0x7, CFC_REG_NUM_LCIDS_ALLOC, (val != 0), IDLE_CHK_ERROR, ++ "CFC: number of alloc LCIDs is not 0"); ++ IDLE_CHK_1(0x7, CFC_REG_NUM_LCIDS_LEAVING, (val != 0), IDLE_CHK_ERROR, ++ "CFC: number of leaving LCIDs is not 0"); ++ ++ IDLE_CHK_4(0x7, CFC_REG_ACTIVITY_COUNTER, CFC_REG_CID_CAM, ++ (CFC_REG_ACTIVITY_COUNTER_SIZE >> 2), 4, (val1 > 1), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "CFC: AC > 1"); ++ IDLE_CHK_7(0x7, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM, ++ CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, ++ (val1 == 3), IDLE_CHK_WARNING, ++ "CFC: AC is 1, connType is 3"); ++ IDLE_CHK_7(0x7, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM, ++ CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, ++ ((val1 != 0) && (val1 != 3)), IDLE_CHK_ERROR, ++ "CFC: AC is 1, connType is not 0 nor 3"); ++ ++ IDLE_CHK_2(0x7, QM_REG_QTASKCTR_0, 64, 4, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Q_%d, queue is not empty"); ++ ++ IDLE_CHK_3(0x7, QM_REG_VOQCREDIT_0, QM_REG_VOQINITCREDIT_0, ++ (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "QM: VOQ_0, VOQ credit is not equal to initial credit"); ++ IDLE_CHK_3(0x7, QM_REG_VOQCREDIT_1, QM_REG_VOQINITCREDIT_1, ++ (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "QM: VOQ_1, VOQ credit is not equal to initial credit"); ++ IDLE_CHK_3(0x7, QM_REG_VOQCREDIT_4, QM_REG_VOQINITCREDIT_4, ++ (val1 != val2), IDLE_CHK_ERROR, ++ "QM: VOQ_4, VOQ credit is not equal to initial credit"); ++ ++ IDLE_CHK_3(0x3, QM_REG_PORT0BYTECRD, QM_REG_BYTECRDINITVAL, ++ (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "QM: P0 Byte credit is not equal to initial credit"); ++ IDLE_CHK_3(0x3, QM_REG_PORT1BYTECRD, QM_REG_BYTECRDINITVAL, ++ (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, ++ "QM: P1 Byte credit is not equal to initial credit"); ++ ++ IDLE_CHK_1(0x7, CCM_REG_CAM_OCCUP, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "CCM: XX protection CAM is not empty"); ++ IDLE_CHK_1(0x7, TCM_REG_CAM_OCCUP, (val != 0), IDLE_CHK_ERROR, ++ "TCM: XX protection CAM is not empty"); ++ IDLE_CHK_1(0x7, UCM_REG_CAM_OCCUP, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "UCM: XX protection CAM is not empty"); ++ IDLE_CHK_1(0x7, XCM_REG_CAM_OCCUP, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "XCM: XX protection CAM is not empty"); ++ ++ IDLE_CHK_1(0x7, BRB1_REG_NUM_OF_FULL_BLOCKS, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "BRB1: BRB is not empty"); ++ ++ IDLE_CHK_1(0x7, CSEM_REG_SLEEP_THREADS_VALID, (val != 0), ++ IDLE_CHK_ERROR, "CSEM: There are sleeping threads"); ++ IDLE_CHK_1(0x7, TSEM_REG_SLEEP_THREADS_VALID, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "TSEM: There are sleeping threads"); ++ IDLE_CHK_1(0x7, USEM_REG_SLEEP_THREADS_VALID, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "USEM: There are sleeping threads"); ++ IDLE_CHK_1(0x7, XSEM_REG_SLEEP_THREADS_VALID, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "XSEM: There are sleeping threads"); ++ ++ IDLE_CHK_1(0x7, CSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1), ++ IDLE_CHK_ERROR, "CSEM: External store FIFO is not empty"); ++ IDLE_CHK_1(0x7, TSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "TSEM: External store FIFO is not empty"); ++ IDLE_CHK_1(0x7, USEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "USEM: External store FIFO is not empty"); ++ IDLE_CHK_1(0x7, XSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "XSEM: External store FIFO is not empty"); ++ ++ IDLE_CHK_1(0x7, CSDM_REG_SYNC_PARSER_EMPTY, (val != 1), ++ IDLE_CHK_ERROR, "CSDM: Parser serial FIFO is not empty"); ++ IDLE_CHK_1(0x7, TSDM_REG_SYNC_PARSER_EMPTY, (val != 1), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "TSDM: Parser serial FIFO is not empty"); ++ IDLE_CHK_1(0x7, USDM_REG_SYNC_PARSER_EMPTY, (val != 1), ++ IDLE_CHK_ERROR, "USDM: Parser serial FIFO is not empty"); ++ IDLE_CHK_1(0x7, XSDM_REG_SYNC_PARSER_EMPTY, (val != 1), ++ IDLE_CHK_ERROR, "XSDM: Parser serial FIFO is not empty"); ++ ++ IDLE_CHK_1(0x7, CSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR, ++ "CSDM: Parser SYNC serial FIFO is not empty"); ++ IDLE_CHK_1(0x7, TSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR, ++ "TSDM: Parser SYNC serial FIFO is not empty"); ++ IDLE_CHK_1(0x7, USDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR, ++ "USDM: Parser SYNC serial FIFO is not empty"); ++ IDLE_CHK_1(0x7, XSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR, ++ "XSDM: Parser SYNC serial FIFO is not empty"); ++ ++ IDLE_CHK_1(0x7, CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1), ++ IDLE_CHK_ERROR, ++ "CSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp" ++ " block"); ++ IDLE_CHK_1(0x7, TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1), ++ IDLE_CHK_ERROR, ++ "TSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp" ++ " block"); ++ IDLE_CHK_1(0x7, USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "USDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp" ++ " block"); ++ IDLE_CHK_1(0x7, XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "XSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp" ++ " block"); ++ ++ IDLE_CHK_1(0x7, DORQ_REG_DQ_FILL_LVLF, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "DQ: DORQ queue is not empty"); ++ ++ IDLE_CHK_1(0x7, CFC_REG_CFC_INT_STS, (val != 0), IDLE_CHK_ERROR, ++ "CFC: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, CDU_REG_CDU_INT_STS, (val != 0), IDLE_CHK_ERROR, ++ "CDU: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, CCM_REG_CCM_INT_STS, (val != 0), IDLE_CHK_ERROR, ++ "CCM: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, TCM_REG_TCM_INT_STS, (val != 0), IDLE_CHK_ERROR, ++ "TCM: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, UCM_REG_UCM_INT_STS, (val != 0), IDLE_CHK_ERROR, ++ "UCM: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, XCM_REG_XCM_INT_STS, (val != 0), IDLE_CHK_ERROR, ++ "XCM: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, PBF_REG_PBF_INT_STS, (val != 0), IDLE_CHK_ERROR, ++ "PBF: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, TM_REG_TM_INT_STS, (val != 0), IDLE_CHK_ERROR, ++ "TIMERS: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, DORQ_REG_DORQ_INT_STS, (val != 0), IDLE_CHK_ERROR, ++ "DQ: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, SRC_REG_SRC_INT_STS, (val != 0), IDLE_CHK_ERROR, ++ "SRCH: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, PRS_REG_PRS_INT_STS, (val != 0), IDLE_CHK_ERROR, ++ "PRS: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, BRB1_REG_BRB1_INT_STS, ((val & ~0xfc00) != 0), ++ IDLE_CHK_ERROR, "BRB1: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, GRCBASE_XPB + PB_REG_PB_INT_STS, (val != 0), ++ IDLE_CHK_ERROR, "XPB: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, GRCBASE_UPB + PB_REG_PB_INT_STS, (val != 0), ++ IDLE_CHK_ERROR, "UPB: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, PXP2_REG_PXP2_INT_STS_0, (val != 0), IDLE_CHK_WARNING, ++ "PXP2: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x6, PXP2_REG_PXP2_INT_STS_1, (val != 0), IDLE_CHK_WARNING, ++ "PXP2: interrupt status 1 is not 0"); ++ IDLE_CHK_1(0x7, QM_REG_QM_INT_STS, (val != 0), IDLE_CHK_ERROR, ++ "QM: interrupt status is not 0"); ++ IDLE_CHK_1(0x7, PXP_REG_PXP_INT_STS_0, (val != 0), IDLE_CHK_ERROR, ++ "PXP: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, PXP_REG_PXP_INT_STS_1, (val != 0), IDLE_CHK_ERROR, ++ "PXP: interrupt status 1 is not 0"); ++ ++ IDLE_CHK_1(0x7, DORQ_REG_RSPA_CRD_CNT, (val != 2), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "DQ: Credit to XCM is not full"); ++ IDLE_CHK_1(0x7, DORQ_REG_RSPB_CRD_CNT, (val != 2), IDLE_CHK_ERROR, ++ "DQ: Credit to UCM is not full"); ++ ++ IDLE_CHK_1(0x3, QM_REG_VOQCRDERRREG, (val != 0), IDLE_CHK_ERROR, ++ "QM: Credit error register is not 0 (byte or credit" ++ " overflow/underflow)"); ++ IDLE_CHK_1(0x7, DORQ_REG_DQ_FULL_ST, (val != 0), IDLE_CHK_ERROR, ++ "DQ: DORQ queue is full"); ++ ++ IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0, ++ ((val & ~0xcffc) != 0), IDLE_CHK_WARNING, ++ "AEU: P0 AFTER_INVERT_1 is not 0"); ++ IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0, (val != 0), ++ IDLE_CHK_ERROR, "AEU: P0 AFTER_INVERT_2 is not 0"); ++ IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0, ++ ((val & ~0xc21b0000) != 0), IDLE_CHK_ERROR, ++ "AEU: P0 AFTER_INVERT_3 is not 0"); ++ IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0, ++ ((val & ~0x801fffff) != 0), IDLE_CHK_ERROR, ++ "AEU: P0 AFTER_INVERT_4 is not 0"); ++ ++ IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_1_FUNC_1, ++ ((val & ~0xcffc) != 0), IDLE_CHK_WARNING, ++ "AEU: P1 AFTER_INVERT_1 is not 0"); ++ IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_2_FUNC_1, (val != 0), ++ IDLE_CHK_ERROR, "AEU: P1 AFTER_INVERT_2 is not 0"); ++ IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_3_FUNC_1, ++ ((val & ~0xc21b0000) != 0), IDLE_CHK_ERROR, ++ "AEU: P1 AFTER_INVERT_3 is not 0"); ++ IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1, ++ ((val & ~0x801fffff) != 0), IDLE_CHK_ERROR, ++ "AEU: P1 AFTER_INVERT_4 is not 0"); ++ ++ IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_1_MCP, ++ ((val & ~0xcffc) != 0), IDLE_CHK_WARNING, ++ "AEU: MCP AFTER_INVERT_1 is not 0"); ++ IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_2_MCP, (val != 0), ++ IDLE_CHK_ERROR, "AEU: MCP AFTER_INVERT_2 is not 0"); ++ IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_3_MCP, ++ ((val & ~0xc21b0000) != 0), IDLE_CHK_ERROR, ++ "AEU: MCP AFTER_INVERT_3 is not 0"); ++ IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_4_MCP, ++ ((val & ~0x801fffff) != 0), IDLE_CHK_ERROR, ++ "AEU: MCP AFTER_INVERT_4 is not 0"); ++ ++ IDLE_CHK_5(0x7, PBF_REG_DISABLE_NEW_TASK_PROC_P0, PBF_REG_P0_CREDIT, ++ PBF_REG_P0_INIT_CRD, (val1 != val2), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PBF: P0 credit is not equal to init_crd"); ++ IDLE_CHK_5(0x7, PBF_REG_DISABLE_NEW_TASK_PROC_P1, PBF_REG_P1_CREDIT, ++ PBF_REG_P1_INIT_CRD, (val1 != val2), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PBF: P1 credit is not equal to init_crd"); ++ IDLE_CHK_3(0x7, PBF_REG_P4_CREDIT, PBF_REG_P4_INIT_CRD, ++ (val1 != val2), IDLE_CHK_ERROR, ++ "PBF: P4 credit is not equal to init_crd"); ++ ++ IDLE_CHK_1(0x7, PBF_REG_P0_TASK_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P0 task_cnt is not 0"); ++ IDLE_CHK_1(0x7, PBF_REG_P1_TASK_CNT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P1 task_cnt is not 0"); ++ IDLE_CHK_1(0x7, PBF_REG_P4_TASK_CNT, (val != 0), IDLE_CHK_ERROR, ++ "PBF: P4 task_cnt is not 0"); ++ ++ IDLE_CHK_1(0x7, XCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR, ++ "XCM: CFC_INIT_CRD is not 1"); ++ IDLE_CHK_1(0x7, UCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR, ++ "UCM: CFC_INIT_CRD is not 1"); ++ IDLE_CHK_1(0x7, TCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR, ++ "TCM: CFC_INIT_CRD is not 1"); ++ IDLE_CHK_1(0x7, CCM_REG_CFC_INIT_CRD, (val != 1), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: CFC_INIT_CRD is not 1"); ++ ++ IDLE_CHK_1(0x7, XCM_REG_XQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR, ++ "XCM: XQM_INIT_CRD is not 32"); ++ IDLE_CHK_1(0x7, UCM_REG_UQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR, ++ "UCM: UQM_INIT_CRD is not 32"); ++ IDLE_CHK_1(0x7, TCM_REG_TQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR, ++ "TCM: TQM_INIT_CRD is not 32"); ++ IDLE_CHK_1(0x7, CCM_REG_CQM_INIT_CRD, (val != 32), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: CQM_INIT_CRD is not 32"); ++ ++ IDLE_CHK_1(0x7, XCM_REG_TM_INIT_CRD, (val != 4), IDLE_CHK_ERROR, ++ "XCM: TM_INIT_CRD is not 4"); ++ IDLE_CHK_1(0x7, UCM_REG_TM_INIT_CRD, (val != 4), IDLE_CHK_ERROR, ++ "UCM: TM_INIT_CRD is not 4"); ++ ++ IDLE_CHK_1(0x7, XCM_REG_FIC0_INIT_CRD, (val != 64), IDLE_CHK_WARNING, ++ "XCM: FIC0_INIT_CRD is not 64"); ++ IDLE_CHK_1(0x7, UCM_REG_FIC0_INIT_CRD, (val != 64), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: FIC0_INIT_CRD is not 64"); ++ IDLE_CHK_1(0x7, TCM_REG_FIC0_INIT_CRD, (val != 64), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: FIC0_INIT_CRD is not 64"); ++ IDLE_CHK_1(0x7, CCM_REG_FIC0_INIT_CRD, (val != 64), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: FIC0_INIT_CRD is not 64"); ++ ++ IDLE_CHK_1(0x7, XCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR, ++ "XCM: FIC1_INIT_CRD is not 64"); ++ IDLE_CHK_1(0x7, UCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR, ++ "UCM: FIC1_INIT_CRD is not 64"); ++ IDLE_CHK_1(0x7, TCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR, ++ "TCM: FIC1_INIT_CRD is not 64"); ++ IDLE_CHK_1(0x7, CCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR, ++ "CCM: FIC1_INIT_CRD is not 64"); ++ ++ IDLE_CHK_1(0x1, XCM_REG_XX_FREE, (val != 31), IDLE_CHK_ERROR, ++ "XCM: XX_FREE is not 31"); ++ IDLE_CHK_1(0x6, XCM_REG_XX_FREE, (val != 32), IDLE_CHK_ERROR, ++ "XCM: XX_FREE is not 32"); ++ IDLE_CHK_1(0x7, UCM_REG_XX_FREE, (val != 27), ++ IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: XX_FREE is not 27"); ++ IDLE_CHK_1(0x7, TCM_REG_XX_FREE, (val != 32), IDLE_CHK_ERROR, ++ "TCM: XX_FREE is not 32"); ++ IDLE_CHK_1(0x7, CCM_REG_XX_FREE, (val != 24), IDLE_CHK_ERROR, ++ "CCM: XX_FREE is not 24"); ++ ++ IDLE_CHK_1(0x7, XSEM_REG_FAST_MEMORY + 0x18000, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "XSEM: FOC0 credit less than initial credit"); ++ IDLE_CHK_1(0x7, XSEM_REG_FAST_MEMORY + 0x18040, (val != 24), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "XSEM: FOC1 credit less than initial credit"); ++ IDLE_CHK_1(0x7, XSEM_REG_FAST_MEMORY + 0x18080, (val != 12), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "XSEM: FOC2 credit less than initial credit"); ++ IDLE_CHK_1(0x7, XSEM_REG_FAST_MEMORY + 0x180C0, (val != 102), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "XSEM: FOC3 credit less than initial credit"); ++ ++ IDLE_CHK_1(0x7, USEM_REG_FAST_MEMORY + 0x18000, (val != 26), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "USEM: FOC0 credit less than initial credit"); ++ IDLE_CHK_1(0x7, USEM_REG_FAST_MEMORY + 0x18040, (val != 78), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "USEM: FOC1 credit less than initial credit"); ++ IDLE_CHK_1(0x7, USEM_REG_FAST_MEMORY + 0x18080, (val != 16), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "USEM: FOC2 credit less than initial credit"); ++ IDLE_CHK_1(0x7, USEM_REG_FAST_MEMORY + 0x180C0, (val != 32), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "USEM: FOC3 credit less than initial credit"); ++ ++ IDLE_CHK_1(0x7, TSEM_REG_FAST_MEMORY + 0x18000, (val != 52), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "TSEM: FOC0 credit less than initial credit"); ++ IDLE_CHK_1(0x7, TSEM_REG_FAST_MEMORY + 0x18040, (val != 24), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "TSEM: FOC1 credit less than initial credit"); ++ IDLE_CHK_1(0x7, TSEM_REG_FAST_MEMORY + 0x18080, (val != 12), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "TSEM: FOC2 credit less than initial credit"); ++ IDLE_CHK_1(0x7, TSEM_REG_FAST_MEMORY + 0x180C0, (val != 32), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "TSEM: FOC3 credit less than initial credit"); ++ ++ IDLE_CHK_1(0x7, CSEM_REG_FAST_MEMORY + 0x18000, (val != 16), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "CSEM: FOC0 credit less than initial credit"); ++ IDLE_CHK_1(0x7, CSEM_REG_FAST_MEMORY + 0x18040, (val != 18), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "CSEM: FOC1 credit less than initial credit"); ++ IDLE_CHK_1(0x7, CSEM_REG_FAST_MEMORY + 0x18080, (val != 48), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "CSEM: FOC2 credit less than initial credit"); ++ IDLE_CHK_1(0x7, CSEM_REG_FAST_MEMORY + 0x180C0, (val != 14), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "CSEM: FOC3 credit less than initial credit"); ++ ++ IDLE_CHK_1(0x7, PRS_REG_TSDM_CURRENT_CREDIT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PRS: TSDM current credit is not 0"); ++ IDLE_CHK_1(0x7, PRS_REG_TCM_CURRENT_CREDIT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PRS: TCM current credit is not 0"); ++ IDLE_CHK_1(0x7, PRS_REG_CFC_LD_CURRENT_CREDIT, (val != 0), ++ IDLE_CHK_ERROR, "PRS: CFC_LD current credit is not 0"); ++ IDLE_CHK_1(0x7, PRS_REG_CFC_SEARCH_CURRENT_CREDIT, (val != 0), ++ IDLE_CHK_ERROR, "PRS: CFC_SEARCH current credit is not 0"); ++ IDLE_CHK_1(0x7, PRS_REG_SRC_CURRENT_CREDIT, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PRS: SRCH current credit is not 0"); ++ ++ IDLE_CHK_1(0x7, PRS_REG_PENDING_BRB_PRS_RQ, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PRS: PENDING_BRB_PRS_RQ is not 0"); ++ IDLE_CHK_2(0x7, PRS_REG_PENDING_BRB_CAC0_RQ, 5, 4, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PRS: PENDING_BRB_CAC%d_RQ is not 0"); ++ ++ IDLE_CHK_1(0x7, PRS_REG_SERIAL_NUM_STATUS_LSB, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PRS: SERIAL_NUM_STATUS_LSB is not 0"); ++ IDLE_CHK_1(0x7, PRS_REG_SERIAL_NUM_STATUS_MSB, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "PRS: SERIAL_NUM_STATUS_MSB is not 0"); ++ ++ IDLE_CHK_1(0x7, CDU_REG_ERROR_DATA, (val != 0), IDLE_CHK_ERROR, ++ "CDU: ERROR_DATA is not 0"); ++ ++ IDLE_CHK_1(0x7, CCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "CCM: STORM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, CCM_REG_CSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "CCM: CSDM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, CCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "CCM: TSEM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, CCM_REG_XSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "CCM: XSEM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, CCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "CCM: USEM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, CCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "CCM: PBF declared message length unequal to actual"); ++ ++ IDLE_CHK_1(0x7, TCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "TCM: STORM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, TCM_REG_TSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "TCM: TSDM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, TCM_REG_PRS_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "TCM: PRS declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, TCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "TCM: PBF declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, TCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "TCM: USEM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, TCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "TCM: CSEM declared message length unequal to actual"); ++ ++ IDLE_CHK_1(0x7, UCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "UCM: STORM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, UCM_REG_USDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "UCM: USDM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, UCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "UCM: TSEM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, UCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "UCM: CSEM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, UCM_REG_XSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "UCM: XSEM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, UCM_REG_DORQ_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "UCM: DORQ declared message length unequal to actual"); ++ ++ IDLE_CHK_1(0x7, XCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "XCM: STORM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, XCM_REG_XSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "XCM: XSDM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, XCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "XCM: TSEM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, XCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "XCM: CSEM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, XCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "XCM: USEM declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, XCM_REG_DORQ_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "XCM: DORQ declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, XCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "XCM: PBF declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, XCM_REG_NIG0_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "XCM: NIG0 declared message length unequal to actual"); ++ IDLE_CHK_1(0x7, XCM_REG_NIG1_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, ++ "XCM: NIG1 declared message length unequal to actual"); ++ ++ IDLE_CHK_1(0x7, QM_REG_XQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR, ++ "QM: XQM wrc_fifolvl is not 0"); ++ IDLE_CHK_1(0x7, QM_REG_UQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR, ++ "QM: UQM wrc_fifolvl is not 0"); ++ IDLE_CHK_1(0x7, QM_REG_TQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR, ++ "QM: TQM wrc_fifolvl is not 0"); ++ IDLE_CHK_1(0x7, QM_REG_CQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR, ++ "QM: CQM wrc_fifolvl is not 0"); ++ IDLE_CHK_1(0x7, QM_REG_QSTATUS_LOW, (val != 0), IDLE_CHK_ERROR, ++ "QM: QSTATUS_LOW is not 0"); ++ IDLE_CHK_1(0x7, QM_REG_QSTATUS_HIGH, (val != 0), IDLE_CHK_ERROR, ++ "QM: QSTATUS_HIGH is not 0"); ++ IDLE_CHK_1(0x7, QM_REG_PAUSESTATE0, (val != 0), IDLE_CHK_ERROR, ++ "QM: PAUSESTATE0 is not 0"); ++ IDLE_CHK_1(0x7, QM_REG_PAUSESTATE1, (val != 0), IDLE_CHK_ERROR, ++ "QM: PAUSESTATE1 is not 0"); ++ IDLE_CHK_1(0x7, QM_REG_OVFQNUM, (val != 0), IDLE_CHK_ERROR, ++ "QM: OVFQNUM is not 0"); ++ IDLE_CHK_1(0x7, QM_REG_OVFERROR, (val != 0), IDLE_CHK_ERROR, ++ "QM: OVFERROR is not 0"); ++ ++ IDLE_CHK_6(0x7, QM_REG_PTRTBL, 64, 8, IDLE_CHK_ERROR_NO_TRAFFIC); ++ ++ IDLE_CHK_1(0x7, BRB1_REG_BRB1_PRTY_STS, ((val & ~0x8) != 0), ++ IDLE_CHK_WARNING, "BRB1: parity status is not 0"); ++ IDLE_CHK_1(0x7, CDU_REG_CDU_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "CDU: parity status is not 0"); ++ IDLE_CHK_1(0x7, CFC_REG_CFC_PRTY_STS, ((val & ~0x2) != 0), ++ IDLE_CHK_WARNING, "CFC: parity status is not 0"); ++ IDLE_CHK_1(0x7, CSDM_REG_CSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "CSDM: parity status is not 0"); ++ IDLE_CHK_1(0x7, DBG_REG_DBG_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "DBG: parity status is not 0"); ++ IDLE_CHK_1(0x7, DMAE_REG_DMAE_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "DMAE: parity status is not 0"); ++ IDLE_CHK_1(0x7, DORQ_REG_DORQ_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "DQ: parity status is not 0"); ++ IDLE_CHK_1(0x1, TCM_REG_TCM_PRTY_STS, ((val & ~0x3ffc0) != 0), ++ IDLE_CHK_WARNING, "TCM: parity status is not 0"); ++ IDLE_CHK_1(0x6, TCM_REG_TCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "TCM: parity status is not 0"); ++ IDLE_CHK_1(0x1, CCM_REG_CCM_PRTY_STS, ((val & ~0x3ffc0) != 0), ++ IDLE_CHK_WARNING, "CCM: parity status is not 0"); ++ IDLE_CHK_1(0x6, CCM_REG_CCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "CCM: parity status is not 0"); ++ IDLE_CHK_1(0x1, UCM_REG_UCM_PRTY_STS, ((val & ~0x3ffc0) != 0), ++ IDLE_CHK_WARNING, "UCM: parity status is not 0"); ++ IDLE_CHK_1(0x6, UCM_REG_UCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "UCM: parity status is not 0"); ++ IDLE_CHK_1(0x1, XCM_REG_XCM_PRTY_STS, ((val & ~0x3ffc0) != 0), ++ IDLE_CHK_WARNING, "XCM: parity status is not 0"); ++ IDLE_CHK_1(0x6, XCM_REG_XCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "XCM: parity status is not 0"); ++ IDLE_CHK_1(0x1, HC_REG_HC_PRTY_STS, ((val & ~0x1) != 0), ++ IDLE_CHK_WARNING, "HC: parity status is not 0"); ++ IDLE_CHK_1(0x1, MISC_REG_MISC_PRTY_STS, ((val & ~0x1) != 0), ++ IDLE_CHK_WARNING, "MISC: parity status is not 0"); ++ IDLE_CHK_1(0x7, PRS_REG_PRS_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "PRS: parity status is not 0"); ++ IDLE_CHK_1(0x7, PXP_REG_PXP_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "PXP: parity status is not 0"); ++ IDLE_CHK_1(0x7, QM_REG_QM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "QM: parity status is not 0"); ++ IDLE_CHK_1(0x1, SRC_REG_SRC_PRTY_STS, ((val & ~0x4) != 0), ++ IDLE_CHK_WARNING, "SRCH: parity status is not 0"); ++ IDLE_CHK_1(0x7, TSDM_REG_TSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "TSDM: parity status is not 0"); ++ IDLE_CHK_1(0x7, USDM_REG_USDM_PRTY_STS, ((val & ~0x20) != 0), ++ IDLE_CHK_WARNING, "USDM: parity status is not 0"); ++ IDLE_CHK_1(0x7, XSDM_REG_XSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "XSDM: parity status is not 0"); ++ IDLE_CHK_1(0x7, GRCBASE_XPB + PB_REG_PB_PRTY_STS, (val != 0), ++ IDLE_CHK_WARNING, "XPB: parity status is not 0"); ++ IDLE_CHK_1(0x7, GRCBASE_UPB + PB_REG_PB_PRTY_STS, (val != 0), ++ IDLE_CHK_WARNING, "UPB: parity status is not 0"); ++ ++ IDLE_CHK_1(0x7, CSEM_REG_CSEM_PRTY_STS_0, (val != 0), ++ IDLE_CHK_WARNING, "CSEM: parity status 0 is not 0"); ++ IDLE_CHK_1(0x1, PXP2_REG_PXP2_PRTY_STS_0, ((val & ~0xfff40020) != 0), ++ IDLE_CHK_WARNING, "PXP2: parity status 0 is not 0"); ++ IDLE_CHK_1(0x6, PXP2_REG_PXP2_PRTY_STS_0, ((val & ~0x20) != 0), ++ IDLE_CHK_WARNING, "PXP2: parity status 0 is not 0"); ++ IDLE_CHK_1(0x7, TSEM_REG_TSEM_PRTY_STS_0, (val != 0), ++ IDLE_CHK_WARNING, "TSEM: parity status 0 is not 0"); ++ IDLE_CHK_1(0x7, USEM_REG_USEM_PRTY_STS_0, (val != 0), ++ IDLE_CHK_WARNING, "USEM: parity status 0 is not 0"); ++ IDLE_CHK_1(0x7, XSEM_REG_XSEM_PRTY_STS_0, (val != 0), ++ IDLE_CHK_WARNING, "XSEM: parity status 0 is not 0"); ++ ++ IDLE_CHK_1(0x7, CSEM_REG_CSEM_PRTY_STS_1, (val != 0), ++ IDLE_CHK_WARNING, "CSEM: parity status 1 is not 0"); ++ IDLE_CHK_1(0x1, PXP2_REG_PXP2_PRTY_STS_1, ((val & ~0x20) != 0), ++ IDLE_CHK_WARNING, "PXP2: parity status 1 is not 0"); ++ IDLE_CHK_1(0x6, PXP2_REG_PXP2_PRTY_STS_1, (val != 0), ++ IDLE_CHK_WARNING, "PXP2: parity status 1 is not 0"); ++ IDLE_CHK_1(0x7, TSEM_REG_TSEM_PRTY_STS_1, (val != 0), ++ IDLE_CHK_WARNING, "TSEM: parity status 1 is not 0"); ++ IDLE_CHK_1(0x7, USEM_REG_USEM_PRTY_STS_1, (val != 0), ++ IDLE_CHK_WARNING, "USEM: parity status 1 is not 0"); ++ IDLE_CHK_1(0x7, XSEM_REG_XSEM_PRTY_STS_1, (val != 0), ++ IDLE_CHK_WARNING, "XSEM: parity status 1 is not 0"); ++ ++ IDLE_CHK_2(0x2, QM_REG_QTASKCTR_EXT_A_0, 64, 4, (val != 0), ++ IDLE_CHK_ERROR_NO_TRAFFIC, ++ "QM: Q_EXT_A_%d, queue is not empty"); ++ IDLE_CHK_1(0x2, QM_REG_QSTATUS_LOW_EXT_A, (val != 0), IDLE_CHK_ERROR, ++ "QM: QSTATUS_LOW_EXT_A is not 0"); ++ IDLE_CHK_1(0x2, QM_REG_QSTATUS_HIGH_EXT_A, (val != 0), IDLE_CHK_ERROR, ++ "QM: QSTATUS_HIGH_EXT_A is not 0"); ++ IDLE_CHK_1(0x6, QM_REG_PAUSESTATE2, (val != 0), IDLE_CHK_ERROR, ++ "QM: PAUSESTATE2 is not 0"); ++ IDLE_CHK_1(0x6, QM_REG_PAUSESTATE3, (val != 0), IDLE_CHK_ERROR, ++ "QM: PAUSESTATE3 is not 0"); ++ IDLE_CHK_1(0x2, QM_REG_PAUSESTATE4, (val != 0), IDLE_CHK_ERROR, ++ "QM: PAUSESTATE4 is not 0"); ++ IDLE_CHK_1(0x2, QM_REG_PAUSESTATE5, (val != 0), IDLE_CHK_ERROR, ++ "QM: PAUSESTATE5 is not 0"); ++ IDLE_CHK_1(0x2, QM_REG_PAUSESTATE6, (val != 0), IDLE_CHK_ERROR, ++ "QM: PAUSESTATE6 is not 0"); ++ IDLE_CHK_1(0x2, QM_REG_PAUSESTATE7, (val != 0), IDLE_CHK_ERROR, ++ "QM: PAUSESTATE7 is not 0"); ++ IDLE_CHK_6(0x2, QM_REG_PTRTBL_EXT_A, 64, 8, ++ IDLE_CHK_ERROR_NO_TRAFFIC); ++ ++ IDLE_CHK_1(0x6, MISC_REG_AEU_SYS_KILL_OCCURRED, (val != 0), ++ IDLE_CHK_ERROR, "MISC: system kill occurd;"); ++ IDLE_CHK_1(0x6, MISC_REG_AEU_SYS_KILL_STATUS_0, (val != 0), ++ IDLE_CHK_ERROR, ++ "MISC: system kill occurd; status_0 register"); ++ IDLE_CHK_1(0x6, MISC_REG_AEU_SYS_KILL_STATUS_1, (val != 0), ++ IDLE_CHK_ERROR, ++ "MISC: system kill occurd; status_1 register"); ++ IDLE_CHK_1(0x6, MISC_REG_AEU_SYS_KILL_STATUS_2, (val != 0), ++ IDLE_CHK_ERROR, ++ "MISC: system kill occurd; status_2 register"); ++ IDLE_CHK_1(0x6, MISC_REG_AEU_SYS_KILL_STATUS_3, (val != 0), ++ IDLE_CHK_ERROR, ++ "MISC: system kill occurd; status_3 register"); ++ IDLE_CHK_1(0x6, MISC_REG_PCIE_HOT_RESET, (val != 0), IDLE_CHK_WARNING, ++ "MISC: pcie_rst_b was asserted without perst assertion"); ++ ++ IDLE_CHK_1(0x7, NIG_REG_NIG_INT_STS_0, ((val & ~0x300) != 0), ++ IDLE_CHK_ERROR, "NIG: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, NIG_REG_NIG_INT_STS_0, (val == 0x300), ++ IDLE_CHK_WARNING, ++ "NIG: Access to BMAC while not active. If tested on FPGA," ++ " ignore this warning."); ++ IDLE_CHK_1(0x7, NIG_REG_NIG_INT_STS_1, (val != 0), IDLE_CHK_ERROR, ++ "NIG: interrupt status 1 is not 0"); ++ IDLE_CHK_1(0x6, NIG_REG_NIG_PRTY_STS, ((val & ~0xffc00000) != 0), ++ IDLE_CHK_WARNING, "NIG: parity status is not 0"); ++ ++ IDLE_CHK_1(0x7, TSEM_REG_TSEM_INT_STS_0, ((val & ~0x10000000) != 0), ++ IDLE_CHK_ERROR, "TSEM: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, TSEM_REG_TSEM_INT_STS_0, (val == 0x10000000), ++ IDLE_CHK_WARNING, "TSEM: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, TSEM_REG_TSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, ++ "TSEM: interrupt status 1 is not 0"); ++ ++ IDLE_CHK_1(0x7, CSEM_REG_CSEM_INT_STS_0, ((val & ~0x10000000) != 0), ++ IDLE_CHK_ERROR, "CSEM: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, CSEM_REG_CSEM_INT_STS_0, (val == 0x10000000), ++ IDLE_CHK_WARNING, "CSEM: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, CSEM_REG_CSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, ++ "CSEM: interrupt status 1 is not 0"); ++ ++ IDLE_CHK_1(0x7, USEM_REG_USEM_INT_STS_0, ((val & ~0x10000000) != 0), ++ IDLE_CHK_ERROR, "USEM: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, USEM_REG_USEM_INT_STS_0, (val == 0x10000000), ++ IDLE_CHK_WARNING, "USEM: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, USEM_REG_USEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, ++ "USEM: interrupt status 1 is not 0"); ++ ++ IDLE_CHK_1(0x7, XSEM_REG_XSEM_INT_STS_0, ((val & ~0x10000000) != 0), ++ IDLE_CHK_ERROR, "XSEM: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, XSEM_REG_XSEM_INT_STS_0, (val == 0x10000000), ++ IDLE_CHK_WARNING, "XSEM: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, XSEM_REG_XSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, ++ "XSEM: interrupt status 1 is not 0"); ++ ++ IDLE_CHK_1(0x7, TSDM_REG_TSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR, ++ "TSDM: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, TSDM_REG_TSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, ++ "TSDM: interrupt status 1 is not 0"); ++ ++ IDLE_CHK_1(0x7, CSDM_REG_CSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR, ++ "CSDM: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, CSDM_REG_CSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, ++ "CSDM: interrupt status 1 is not 0"); ++ ++ IDLE_CHK_1(0x7, USDM_REG_USDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR, ++ "USDM: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, USDM_REG_USDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, ++ "USDM: interrupt status 1 is not 0"); ++ ++ IDLE_CHK_1(0x7, XSDM_REG_XSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR, ++ "XSDM: interrupt status 0 is not 0"); ++ IDLE_CHK_1(0x7, XSDM_REG_XSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, ++ "XSDM: interrupt status 1 is not 0"); ++ ++ IDLE_CHK_1(0x6, HC_REG_HC_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "HC: parity status is not 0"); ++ IDLE_CHK_1(0x6, MISC_REG_MISC_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "MISC: parity status is not 0"); ++ IDLE_CHK_1(0x6, SRC_REG_SRC_PRTY_STS, (val != 0), IDLE_CHK_WARNING, ++ "SRCH: parity status is not 0"); ++ ++ if (idle_chk_errors == 0) { ++ BNX2X_DBG_ERR("completed successfully (with %d warnings)\n", ++ idle_chk_warnings); ++ } else { ++ BNX2X_DBG_ERR("failed (with %d errors, %d warnings)\n", ++ idle_chk_errors, idle_chk_warnings); ++ } ++ return idle_chk_errors; ++} ++ diff --git a/master/bonding-balance-slb-fixes.patch b/master/bonding-balance-slb-fixes.patch index 352de5b..fb4eb22 100644 --- a/master/bonding-balance-slb-fixes.patch +++ b/master/bonding-balance-slb-fixes.patch @@ -124,10 +124,11 @@ diff -r 4f66025924a6 drivers/net/bonding/bond_alb.c } write_lock_bh(&bond->curr_slave_lock); -@@ -1791,7 +1802,10 @@ +@@ -1791,8 +1802,11 @@ alb_set_slave_mac_addr(bond->curr_active_slave, bond_dev->dev_addr, bond->alb_info.rlb_enabled); + read_lock(&bond->lock); - alb_send_learning_packets(bond->curr_active_slave, bond_dev->dev_addr); + if (bond->alb_info.slb_enabled) + slb_send_learning_packets(bond); @@ -139,16 +140,15 @@ diff -r 4f66025924a6 drivers/net/bonding/bond_alb.c diff -r 4f66025924a6 drivers/net/bonding/bond_main.c --- a/drivers/net/bonding/bond_main.c Wed Feb 11 15:53:37 2009 +0000 +++ b/drivers/net/bonding/bond_main.c Wed Feb 11 16:00:15 2009 +0000 -@@ -827,7 +827,8 @@ - */ - static void bond_mc_add(struct bonding *bond, void *addr, int alen) +@@ -794,7 +794,7 @@ + static int bond_set_promiscuity(struct bonding *bond, int inc) { + int err = 0; - if (USES_PRIMARY(bond->params.mode)) { -+ + if (USES_PRIMARY(bond->params.mode) && bond->params.mode != BOND_MODE_SLB) { /* write lock already acquired */ if (bond->curr_active_slave) { - dev_mc_add(bond->curr_active_slave->dev, addr, alen, 0); + err = dev_set_promiscuity(bond->curr_active_slave->dev, @@ -1580,6 +1581,11 @@ dev_mc_add (slave_dev, dmi->dmi_addr, dmi->dmi_addrlen, 0); } diff --git a/master/bonding-balance-slb.patch b/master/bonding-balance-slb.patch index 0a710b4..1c40a64 100644 --- a/master/bonding-balance-slb.patch +++ b/master/bonding-balance-slb.patch @@ -328,6 +328,14 @@ diff -r 8e9d114ca60a drivers/net/bonding/bond_main.c /* Must be called only after all * slaves have been released */ +@@ -3897,6 +3908,7 @@ + break; + case BOND_MODE_TLB: + case BOND_MODE_ALB: ++ case BOND_MODE_SLB: + cancel_delayed_work(&bond->alb_work); + break; + default: @@ -4472,6 +4492,7 @@ case BOND_MODE_ALB: bond_set_master_alb_flags(bond); diff --git a/master/cifs-no-tcp-sharing.patch b/master/cifs-no-tcp-sharing.patch new file mode 100644 index 0000000..ea9b8a8 --- /dev/null +++ b/master/cifs-no-tcp-sharing.patch @@ -0,0 +1,37 @@ +diff -r 765457bd1063 fs/cifs/connect.c +--- a/fs/cifs/connect.c Tue May 19 20:49:21 2009 +0000 ++++ b/fs/cifs/connect.c Wed May 20 18:38:30 2009 +0000 +@@ -70,6 +70,7 @@ extern mempool_t *cifs_req_poolp; + #define PAGEVEC_SIZE 14 + #endif + #endif ++#define TCPSESS_NOSHARING 1 + + struct smb_vol { + char *username; +@@ -1348,6 +1349,17 @@ cifs_parse_mount_options(char *options, + + return 0; + } ++#ifdef TCPSESS_NOSHARING ++/* not sharing existing TCP connections */ ++static inline struct cifsSesInfo * ++cifs_find_tcp_session(struct in_addr *target_ip_addr, ++ struct in6_addr *target_ip6_addr, ++ char *userName, struct TCP_Server_Info **psrvTcp) ++{ ++ return NULL; ++} ++ ++#else + + static struct cifsSesInfo * + cifs_find_tcp_session(struct in_addr *target_ip_addr, +@@ -1389,6 +1401,7 @@ cifs_find_tcp_session(struct in_addr *ta + read_unlock(&GlobalSMBSeslock); + return NULL; + } ++#endif //TCPSESS_NOSHARING + + static struct cifsTconInfo * + find_unc(__be32 new_target_ip_addr, char *uncName, char *userName) diff --git a/master/cleanup-linux-2.6.18-xen.hg-918.71a61b393cdf.diff b/master/cleanup-linux-2.6.18-xen.hg-918.71a61b393cdf.diff new file mode 100644 index 0000000..79731a8 --- /dev/null +++ b/master/cleanup-linux-2.6.18-xen.hg-918.71a61b393cdf.diff @@ -0,0 +1,36 @@ +Cleanup: Simplify linux-2.6.18-xen.hg-918.71a61b393cdf a bit. + +diff -r 3cae20017616 drivers/xen/blkback/blkback.c +--- a/drivers/xen/blkback/blkback.c Mon Jul 20 10:03:44 2009 +0100 ++++ b/drivers/xen/blkback/blkback.c Fri Sep 04 14:57:24 2009 -0700 +@@ -560,23 +560,20 @@ + DPRINTK("invalid buffer -- could not remap it\n"); + map[i].handle = BLKBACK_INVALID_HANDLE; + ret |= 1; +- } else { +- blkback_pagemap_set(vaddr_pagenr(pending_req, i), +- virt_to_page(vaddr(pending_req, i)), +- blkif->domid, req->handle, +- req->seg[i].gref); ++ continue; + } + +- pending_handle(pending_req, i) = map[i].handle; +- +- if (ret) +- continue; +- + set_phys_to_machine(__pa(vaddr( + pending_req, i)) >> PAGE_SHIFT, + FOREIGN_FRAME(map[i].dev_bus_addr >> PAGE_SHIFT)); + seg[i].buf = map[i].dev_bus_addr | + (req->seg[i].first_sect << 9); ++ blkback_pagemap_set(vaddr_pagenr(pending_req, i), ++ virt_to_page(vaddr(pending_req, i)), ++ blkif->domid, req->handle, ++ req->seg[i].gref); ++ ++ pending_handle(pending_req, i) = map[i].handle; + } + + if (ret) diff --git a/master/clear-ts_usedfpu-on-new-threads b/master/clear-ts_usedfpu-on-new-threads new file mode 100644 index 0000000..799761e --- /dev/null +++ b/master/clear-ts_usedfpu-on-new-threads @@ -0,0 +1,53 @@ +Make sure that newly forked threads don't have TS_USEDFPU set, +since they clearly can't have any FPU state yet. + +This avoids a kernel deadlock where, when scheduling _away_ from a new +thread for the first time, we: + - turn off interrupts; + - take the runqueue lock; + - see TS_USEDFPU and try to save the FPU regs; + - take an #NP exception because CR0.TS is still set; + - turn on interrupts in the #NP handler while we allocate FPU space; (!) + - take an interrupt; + - try to wake a task that's waiting for that interrupt; + - try to take the runqueue lock, which we already have. + +This deadlock can be triggered from user space by using the FPU and then +forking, and not using the FPU after the fork. + +Signed-off-by: Tim Deegan + +diff -r 36031e0895b1 include/asm-x86/thread_info.h +--- a/include/asm-x86/thread_info.h Tue Sep 15 14:26:00 2009 +0100 ++++ b/include/asm-x86/thread_info.h Fri Sep 18 11:48:45 2009 +0100 +@@ -257,6 +257,11 @@ + + #define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING) + ++/* A new thread can't possibly have FPU state in any CPU. */ ++#define arch_setup_thread_stack(thread) \ ++ do { (thread)->status &= ~TS_USEDFPU; } while (0) ++ ++ + #ifndef __ASSEMBLY__ + #define HAVE_SET_RESTORE_SIGMASK 1 + static inline void set_restore_sigmask(void) +diff -r 36031e0895b1 include/linux/sched.h +--- a/include/linux/sched.h Tue Sep 15 14:26:00 2009 +0100 ++++ b/include/linux/sched.h Fri Sep 18 11:48:45 2009 +0100 +@@ -1977,10 +1977,15 @@ + #define task_thread_info(task) ((struct thread_info *)(task)->stack) + #define task_stack_page(task) ((task)->stack) + ++#ifndef arch_setup_thread_stack ++#define arch_setup_thread_stack(thread) do {} while(0) ++#endif ++ + static inline void setup_thread_stack(struct task_struct *p, struct task_struct *org) + { + *task_thread_info(p) = *task_thread_info(org); + task_thread_info(p)->task = p; ++ arch_setup_thread_stack(task_thread_info(p)); + } + + static inline unsigned long *end_of_stack(struct task_struct *p) diff --git a/master/clts-when-calling-math_state_restore b/master/clts-when-calling-math_state_restore new file mode 100644 index 0000000..a97fde7 --- /dev/null +++ b/master/clts-when-calling-math_state_restore @@ -0,0 +1,18 @@ +Direct callers of math_state_restore need to CLTS first, because the +Xenified version assumes that Xen cleared CR0.TS in the trap handler. + +diff -r 36031e0895b1 arch/x86/kernel/process_32-xen.c +--- a/arch/x86/kernel/process_32-xen.c Tue Sep 15 14:26:00 2009 +0100 ++++ b/arch/x86/kernel/process_32-xen.c Fri Sep 18 11:48:45 2009 +0100 +@@ -637,8 +644,10 @@ + * tsk_used_math() checks prevent calling math_state_restore(), + * which can sleep in the case of !tsk_used_math() + */ +- if (tsk_used_math(next_p) && next_p->fpu_counter > 5) ++ if (tsk_used_math(next_p) && next_p->fpu_counter > 5) { ++ clts(); /* Xenified math_state_restore() doesn't do this */ + math_state_restore(); ++ } + + /* + * Restore %gs if needed (which is common) diff --git a/master/cxgb3-1.3.1.7.patch b/master/cxgb3-1.3.1.7.patch new file mode 100644 index 0000000..0aec14e --- /dev/null +++ b/master/cxgb3-1.3.1.7.patch @@ -0,0 +1,32310 @@ +diff -r c6413c34aa41 drivers/net/cxgb3/Makefile +--- a/drivers/net/cxgb3/Makefile Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/Makefile Tue Oct 06 09:37:59 2009 +0100 +@@ -5,4 +5,29 @@ + obj-$(CONFIG_CHELSIO_T3) += cxgb3.o + + cxgb3-objs := cxgb3_main.o ael1002.o vsc8211.o t3_hw.o mc5.o \ +- xgmac.o sge.o l2t.o cxgb3_offload.o ++ xgmac.o sge.o l2t.o cxgb3_offload.o \ ++ mv88e1xxx.o trace.o vsc7323.o tn1010.o aq100x.o ++ ++EXTRA_CFLAGS += -DARP_HDR ++EXTRA_CFLAGS += -DATOMIC_ADD_RETURN ++EXTRA_CFLAGS += -DCONFIG_CHELSIO_T3_CORE ++EXTRA_CFLAGS += -DCONFIG_TCP_OFFLOAD_MODULE ++EXTRA_CFLAGS += -DGSO_SIZE ++EXTRA_CFLAGS += -DGSO_TYPE ++EXTRA_CFLAGS += -DHAS_EEH ++EXTRA_CFLAGS += -DIRQF ++EXTRA_CFLAGS += -DI_PRIVATE ++EXTRA_CFLAGS += -DKZALLOC ++EXTRA_CFLAGS += -DNAPI_UPDATE ++EXTRA_CFLAGS += -DNETEVENT ++EXTRA_CFLAGS += -DNEW_SKB_COPY ++EXTRA_CFLAGS += -DNEW_SKB_OFFSET ++EXTRA_CFLAGS += -DPDEV_MAPPING ++EXTRA_CFLAGS += -DRTNL_TRYLOCK ++EXTRA_CFLAGS += -DSPIN_TRYLOCK_IRQSAVE ++EXTRA_CFLAGS += -DT3_IP_HDR ++EXTRA_CFLAGS += -DT3_SKB_TRANSPORT_OFFSET ++EXTRA_CFLAGS += -DT3_TCP_HDR ++EXTRA_CFLAGS += -DTRANSPORT_HEADER ++EXTRA_CFLAGS += -DVLANGRP ++EXTRA_CFLAGS += -DVLAN_DEV_API +diff -r c6413c34aa41 drivers/net/cxgb3/adapter.h +--- a/drivers/net/cxgb3/adapter.h Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/adapter.h Tue Oct 06 09:37:59 2009 +0100 +@@ -1,33 +1,12 @@ + /* +- * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved. ++ * This file is part of the Chelsio T3 Ethernet driver for Linux. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. + * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ + + /* This file should not be included directly. Include common.h instead. */ +@@ -40,21 +19,23 @@ + #include + #include + #include +-#include +-#include +-#include + #include "t3cdev.h" ++#include + #include + ++#ifdef T3_TRACE ++# include "trace.h" ++#endif ++ + struct vlan_group; +-struct adapter; +-struct sge_qset; + + struct port_info { + struct adapter *adapter; + struct vlan_group *vlan_grp; + struct sge_qset *qs; + u8 port_id; ++ u8 tx_chan; ++ u8 txpkt_intf; + u8 rx_csum_offload; + u8 nqsets; + u8 first_qset; +@@ -64,15 +45,20 @@ + struct net_device_stats netstats; + int activity; + __be32 iscsi_ipv4addr; ++ int max_ofld_bw; ++ int link_fault; + }; + +-enum { /* adapter flags */ +- FULL_INIT_DONE = (1 << 0), +- USING_MSI = (1 << 1), +- USING_MSIX = (1 << 2), +- QUEUES_BOUND = (1 << 3), +- TP_PARITY_INIT = (1 << 4), +- NAPI_INIT = (1 << 5), ++struct work_struct; ++struct dentry; ++ ++enum { /* adapter flags */ ++ FULL_INIT_DONE = (1 << 0), ++ USING_MSI = (1 << 1), ++ USING_MSIX = (1 << 2), ++ QUEUES_BOUND = (1 << 3), ++ TP_PARITY_INIT = (1 << 4), ++ NAPI_INIT = (1 << 5), + }; + + struct fl_pg_chunk { +@@ -87,19 +73,40 @@ + struct sge_fl { /* SGE per free-buffer list state */ + unsigned int buf_size; /* size of each Rx buffer */ + unsigned int credits; /* # of available Rx buffers */ ++ unsigned int pend_cred; /* new buffers since last FL DB ring */ + unsigned int size; /* capacity of free list */ + unsigned int cidx; /* consumer index */ + unsigned int pidx; /* producer index */ + unsigned int gen; /* free list generation */ + struct fl_pg_chunk pg_chunk;/* page chunk cache */ + unsigned int use_pages; /* whether FL uses pages or sk_buffs */ +- unsigned int order; /* order of page allocations */ ++ unsigned int order; /* order of page allocations */ + struct rx_desc *desc; /* address of HW Rx descriptor ring */ + struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ + dma_addr_t phys_addr; /* physical address of HW ring start */ + unsigned int cntxt_id; /* SGE context id for the free list */ + unsigned long empty; /* # of times queue ran out of buffers */ + unsigned long alloc_failed; /* # of times buffer allocation failed */ ++}; ++ ++/* max concurrent LRO sessions per queue set */ ++#define MAX_LRO_SES 8 ++ ++struct lro_session { ++ struct sk_buff *head; ++ struct sk_buff *tail; ++ u32 seq; ++ u16 iplen; ++ u16 mss; ++ __be16 vlan; ++ u8 npkts; ++}; ++ ++struct lro_state { ++ unsigned short enabled; ++ unsigned short active_idx; /* index of most recently added session */ ++ unsigned int nactive; /* # of active sessions */ ++ struct lro_session sess[MAX_LRO_SES]; + }; + + /* +@@ -110,103 +117,107 @@ + + struct rsp_desc; + +-struct sge_rspq { /* state for an SGE response queue */ +- unsigned int credits; /* # of pending response credits */ +- unsigned int size; /* capacity of response queue */ +- unsigned int cidx; /* consumer index */ +- unsigned int gen; /* current generation bit */ +- unsigned int polling; /* is the queue serviced through NAPI? */ +- unsigned int holdoff_tmr; /* interrupt holdoff timer in 100ns */ +- unsigned int next_holdoff; /* holdoff time for next interrupt */ +- unsigned int rx_recycle_buf; /* whether recycling occurred +- within current sop-eop */ +- struct rsp_desc *desc; /* address of HW response ring */ +- dma_addr_t phys_addr; /* physical address of the ring */ +- unsigned int cntxt_id; /* SGE context id for the response q */ +- spinlock_t lock; /* guards response processing */ +- struct sk_buff *rx_head; /* offload packet receive queue head */ +- struct sk_buff *rx_tail; /* offload packet receive queue tail */ +- struct sk_buff *pg_skb; /* used to build frag list in napi handler */ +- ++struct sge_rspq { /* state for an SGE response queue */ ++ unsigned int credits; /* # of pending response credits */ ++ unsigned int size; /* capacity of response queue */ ++ unsigned int cidx; /* consumer index */ ++ unsigned int gen; /* current generation bit */ ++ unsigned int polling; /* is the queue serviced through NAPI? */ ++ unsigned int holdoff_tmr; /* interrupt holdoff timer in 100ns */ ++ unsigned int next_holdoff; /* holdoff time for next interrupt */ ++ unsigned int rx_recycle_buf; /* whether recycling occurred within current sop-eop */ ++ struct rsp_desc *desc; /* address of HW response ring */ ++ dma_addr_t phys_addr; /* physical address of the ring */ ++ unsigned int cntxt_id; /* SGE context id for the response q */ ++ spinlock_t lock; /* guards response processing */ ++ struct sk_buff *rx_head; /* offload packet receive queue head */ ++ struct sk_buff *rx_tail; /* offload packet receive queue tail */ ++ struct sk_buff *pg_skb; /* skb for building frag list in napi response handler */ + unsigned long offload_pkts; + unsigned long offload_bundles; +- unsigned long eth_pkts; /* # of ethernet packets */ +- unsigned long pure_rsps; /* # of pure (non-data) responses */ +- unsigned long imm_data; /* responses with immediate data */ +- unsigned long rx_drops; /* # of packets dropped due to no mem */ +- unsigned long async_notif; /* # of asynchronous notification events */ +- unsigned long empty; /* # of times queue ran out of credits */ +- unsigned long nomem; /* # of responses deferred due to no mem */ +- unsigned long unhandled_irqs; /* # of spurious intrs */ ++ unsigned long eth_pkts; /* # of ethernet packets */ ++ unsigned long pure_rsps; /* # of pure (non-data) responses */ ++ unsigned long imm_data; /* responses with immediate data */ ++ unsigned long rx_drops; /* # of packets dropped due to no mem */ ++ unsigned long async_notif; /* # of asynchronous notification events */ ++ unsigned long empty; /* # of times queue ran out of credits */ ++ unsigned long nomem; /* # of responses deferred due to no mem */ ++ unsigned long unhandled_irqs; /* # of spurious intrs */ + unsigned long starved; + unsigned long restarted; + }; + + struct tx_desc; + struct tx_sw_desc; ++struct eth_coalesce_sw_desc; + +-struct sge_txq { /* state for an SGE Tx queue */ +- unsigned long flags; /* HW DMA fetch status */ +- unsigned int in_use; /* # of in-use Tx descriptors */ +- unsigned int size; /* # of descriptors */ +- unsigned int processed; /* total # of descs HW has processed */ +- unsigned int cleaned; /* total # of descs SW has reclaimed */ +- unsigned int stop_thres; /* SW TX queue suspend threshold */ +- unsigned int cidx; /* consumer index */ +- unsigned int pidx; /* producer index */ +- unsigned int gen; /* current value of generation bit */ +- unsigned int unacked; /* Tx descriptors used since last COMPL */ +- struct tx_desc *desc; /* address of HW Tx descriptor ring */ +- struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ +- spinlock_t lock; /* guards enqueueing of new packets */ +- unsigned int token; /* WR token */ +- dma_addr_t phys_addr; /* physical address of the ring */ +- struct sk_buff_head sendq; /* List of backpressured offload packets */ +- struct tasklet_struct qresume_tsk; /* restarts the queue */ +- unsigned int cntxt_id; /* SGE context id for the Tx q */ +- unsigned long stops; /* # of times q has been stopped */ +- unsigned long restarts; /* # of queue restarts */ ++struct sge_txq { /* state for an SGE Tx queue */ ++ unsigned long flags; /* HW DMA fetch status */ ++ unsigned int in_use; /* # of in-use Tx descriptors */ ++ unsigned int size; /* # of descriptors */ ++ unsigned int processed; /* total # of descs HW has processed */ ++ unsigned int cleaned; /* total # of descs SW has reclaimed */ ++ unsigned int stop_thres; /* SW TX queue suspend threshold */ ++ unsigned int cidx; /* consumer index */ ++ unsigned int pidx; /* producer index */ ++ unsigned int gen; /* current value of generation bit */ ++ unsigned int unacked; /* Tx descriptors used since last COMPL */ ++ struct tx_desc *desc; /* address of HW Tx descriptor ring */ ++ struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ ++ unsigned int eth_coalesce_idx; /* idx of the next coalesce pkt */ ++ unsigned int eth_coalesce_bytes; /* total lentgh of coalesced pkts */ ++ struct eth_coalesce_sw_desc *eth_coalesce_sdesc; ++ spinlock_t lock; /* guards enqueueing of new packets */ ++ unsigned int token; /* WR token */ ++ dma_addr_t phys_addr; /* physical address of the ring */ ++ struct sk_buff_head sendq; /* List of backpressured offload packets */ ++ struct tasklet_struct qresume_tsk; /* restarts the queue */ ++ unsigned int cntxt_id; /* SGE context id for the Tx q */ ++ unsigned long stops; /* # of times q has been stopped */ ++ unsigned long restarts; /* # of queue restarts */ + }; + +-enum { /* per port SGE statistics */ +- SGE_PSTAT_TSO, /* # of TSO requests */ +- SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */ +- SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */ +- SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */ +- SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */ +- SGE_PSTAT_LRO_AGGR, /* # of page chunks added to LRO sessions */ +- SGE_PSTAT_LRO_FLUSHED, /* # of flushed LRO sessions */ +- SGE_PSTAT_LRO_NO_DESC, /* # of overflown LRO sessions */ ++enum { /* per port SGE statistics */ ++ SGE_PSTAT_TSO, /* # of TSO requests */ ++ SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */ ++ SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */ ++ SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */ ++ SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */ ++ SGE_PSTAT_TX_COALESCE_WR, /* # of TX Coalesce Work Requests */ ++ SGE_PSTAT_TX_COALESCE_PKT, /* # of TX Coalesced packets */ ++ SGE_PSTAT_LRO, /* # of completed LRO packets */ ++ SGE_PSTAT_LRO_SKB, /* # of sk_buffs added to LRO sessions */ ++ SGE_PSTAT_LRO_PG, /* # of page chunks added to LRO sessions */ ++ SGE_PSTAT_LRO_ACK, /* # of pure ACKs fully merged by LRO */ ++ SGE_PSTAT_LRO_OVFLOW, /* # of LRO session overflows */ ++ SGE_PSTAT_LRO_COLSN, /* # of LRO hash collisions */ + +- SGE_PSTAT_MAX /* must be last */ ++ SGE_PSTAT_MAX /* must be last */ + }; + +-#define T3_MAX_LRO_SES 8 +-#define T3_MAX_LRO_MAX_PKTS 64 +- +-struct sge_qset { /* an SGE queue set */ ++struct sge_qset { /* an SGE queue set */ + struct adapter *adap; ++#if defined(NAPI_UPDATE) + struct napi_struct napi; ++#endif + struct sge_rspq rspq; +- struct sge_fl fl[SGE_RXQ_PER_SET]; +- struct sge_txq txq[SGE_TXQ_PER_SET]; +- struct net_lro_mgr lro_mgr; +- struct net_lro_desc lro_desc[T3_MAX_LRO_SES]; +- struct skb_frag_struct *lro_frag_tbl; +- int lro_nfrags; +- int lro_enabled; +- int lro_frag_len; +- void *lro_va; +- struct net_device *netdev; +- unsigned long txq_stopped; /* which Tx queues are stopped */ +- struct timer_list tx_reclaim_timer; /* reclaims TX buffers */ ++ struct sge_fl fl[SGE_RXQ_PER_SET]; ++ struct lro_state lro; ++ struct sge_txq txq[SGE_TXQ_PER_SET]; ++ struct net_device *netdev; /* associated net device */ ++ unsigned long txq_stopped; /* which Tx queues are stopped */ ++ struct timer_list tx_reclaim_timer; /* reclaims TX buffers */ ++ struct timer_list rx_reclaim_timer; + unsigned long port_stats[SGE_PSTAT_MAX]; + } ____cacheline_aligned; + + struct sge { + struct sge_qset qs[SGE_QSETS]; +- spinlock_t reg_lock; /* guards non-atomic SGE registers (eg context) */ ++ unsigned int nqsets; /* # of active queue sets */ ++ spinlock_t reg_lock; /* guards non-atomic SGE registers (eg context) */ + }; ++ ++struct filter_info; + + struct adapter { + struct t3cdev tdev; +@@ -230,6 +241,10 @@ + char desc[22]; + } msix_info[SGE_QSETS + 1]; + ++#ifdef T3_TRACE ++ struct trace_buf *tb[SGE_QSETS]; ++#endif ++ + /* T3 modules */ + struct sge sge; + struct mc7 pmrx; +@@ -238,32 +253,188 @@ + struct mc5 mc5; + + struct net_device *port[MAX_NPORTS]; ++ u8 rxpkt_map[8]; /* maps RX_PKT interface values to port ids */ ++ u8 rrss_map[SGE_QSETS]; /* reverse RSS map table */ ++ ++ atomic_t filter_toe_mode; /* filter / TOE exclusion switch */ ++ struct filter_info *filters; /* software copy of hardware filters */ ++ + unsigned int check_task_cnt; + struct delayed_work adap_check_task; + struct work_struct ext_intr_handler_task; + struct work_struct fatal_error_handler_task; ++ struct work_struct link_fault_handler_task; ++ ++#if !defined(NAPI_UPDATE) ++ /* ++ * Dummy netdevices are needed when using multiple receive queues with ++ * NAPI as each netdevice can service only one queue. ++ */ ++ struct net_device *dummy_netdev[SGE_QSETS - 1]; ++#endif ++ u32 t3_config_space[16]; /* For old kernels only */ + + struct dentry *debugfs_root; + +- struct mutex mdio_lock; ++ spinlock_t mdio_lock; ++ spinlock_t elmer_lock; + spinlock_t stats_lock; + spinlock_t work_lock; + }; + +-static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr) ++/* values for filter_toe_mode interlock */ ++enum { ++ CXGB3_FTM_NONE = 0, /* no filters or TOE activated */ ++ CXGB3_FTM_FILTER = 1, /* filters used */ ++ CXGB3_FTM_TOE = 2, /* TOE activated */ ++}; ++ ++int cxgb3_filter_toe_mode(struct adapter *, int); ++ ++#include "cxgb3_compat.h" ++ ++#define MDIO_LOCK(adapter) spin_lock(&(adapter)->mdio_lock) ++#define MDIO_UNLOCK(adapter) spin_unlock(&(adapter)->mdio_lock) ++ ++#define ELMR_LOCK(adapter) spin_lock(&(adapter)->elmer_lock) ++#define ELMR_UNLOCK(adapter) spin_unlock(&(adapter)->elmer_lock) ++ ++/** ++ * t3_read_reg - read a HW register ++ * @adapter: the adapter ++ * @reg_addr: the register address ++ * ++ * Returns the 32-bit value of the given HW register. ++ */ ++static inline u32 t3_read_reg(adapter_t *adapter, u32 reg_addr) + { + u32 val = readl(adapter->regs + reg_addr); + +- CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val); ++ CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, ++ val); + return val; + } + +-static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) ++/** ++ * t3_write_reg - write a HW register ++ * @adapter: the adapter ++ * @reg_addr: the register address ++ * @val: the value to write ++ * ++ * Write a 32-bit value into the given HW register. ++ */ ++static inline void t3_write_reg(adapter_t *adapter, u32 reg_addr, u32 val) + { +- CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val); ++ CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, ++ val); + writel(val, adapter->regs + reg_addr); + } + ++/** ++ * t3_os_pci_write_config_4 - 32-bit write to PCI config space ++ * @adapter: the adapter ++ * @reg: the register address ++ * @val: the value to write ++ * ++ * Write a 32-bit value into the given register in PCI config space. ++ */ ++static inline void t3_os_pci_write_config_4(adapter_t *adapter, int reg, ++ u32 val) ++{ ++ pci_write_config_dword(adapter->pdev, reg, val); ++} ++ ++/** ++ * t3_os_pci_read_config_4 - read a 32-bit value from PCI config space ++ * @adapter: the adapter ++ * @reg: the register address ++ * @val: where to store the value read ++ * ++ * Read a 32-bit value from the given register in PCI config space. ++ */ ++static inline void t3_os_pci_read_config_4(adapter_t *adapter, int reg, ++ u32 *val) ++{ ++ pci_read_config_dword(adapter->pdev, reg, val); ++} ++ ++/** ++ * t3_os_pci_write_config_2 - 16-bit write to PCI config space ++ * @adapter: the adapter ++ * @reg: the register address ++ * @val: the value to write ++ * ++ * Write a 16-bit value into the given register in PCI config space. ++ */ ++static inline void t3_os_pci_write_config_2(adapter_t *adapter, int reg, ++ u16 val) ++{ ++ pci_write_config_word(adapter->pdev, reg, val); ++} ++ ++/** ++ * t3_os_pci_read_config_2 - read a 16-bit value from PCI config space ++ * @adapter: the adapter ++ * @reg: the register address ++ * @val: where to store the value read ++ * ++ * Read a 16-bit value from the given register in PCI config space. ++ */ ++static inline void t3_os_pci_read_config_2(adapter_t *adapter, int reg, ++ u16 *val) ++{ ++ pci_read_config_word(adapter->pdev, reg, val); ++} ++ ++/** ++ * t3_os_find_pci_capability - lookup a capability in the PCI capability list ++ * @adapter: the adapter ++ * @cap: the capability ++ * ++ * Return the address of the given capability within the PCI capability list. ++ */ ++static inline int t3_os_find_pci_capability(adapter_t *adapter, int cap) ++{ ++ return pci_find_capability(adapter->pdev, cap); ++} ++ ++/** ++ * port_name - return the string name of a port ++ * @adapter: the adapter ++ * @port_idx: the port index ++ * ++ * Return the string name of the selected port. ++ */ ++static inline const char *port_name(adapter_t *adapter, unsigned int port_idx) ++{ ++ return adapter->port[port_idx]->name; ++} ++ ++/** ++ * t3_os_set_hw_addr - store a port's MAC address in SW ++ * @adapter: the adapter ++ * @port_idx: the port index ++ * @hw_addr: the Ethernet address ++ * ++ * Store the Ethernet address of the given port in SW. Called by the common ++ * code when it retrieves a port's Ethernet address from EEPROM. ++ */ ++static inline void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, ++ u8 hw_addr[]) ++{ ++ memcpy(adapter->port[port_idx]->dev_addr, hw_addr, ETH_ALEN); ++#ifdef ETHTOOL_GPERMADDR ++ memcpy(adapter->port[port_idx]->perm_addr, hw_addr, ETH_ALEN); ++#endif ++} ++ ++/** ++ * adap2pinfo - return the port_info of a port ++ * @adap: the adapter ++ * @idx: the port index ++ * ++ * Return the port_info structure for the port of the given index. ++ */ + static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) + { + return netdev_priv(adap->port[idx]); +@@ -273,32 +444,33 @@ + + #define tdev2adap(d) container_of(d, struct adapter, tdev) + +-static inline int offload_running(struct adapter *adapter) ++static inline int offload_running(adapter_t *adapter) + { + return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map); + } + + int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb); + +-void t3_os_ext_intr_handler(struct adapter *adapter); +-void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status, ++void t3_os_ext_intr_handler(adapter_t *adapter); ++void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, + int speed, int duplex, int fc); + void t3_os_phymod_changed(struct adapter *adap, int port_id); ++void t3_os_link_fault(adapter_t *adapter, int port_id, int state); ++void t3_os_link_fault_handler(adapter_t *adapter, int port_id); + +-void t3_sge_start(struct adapter *adap); +-void t3_sge_stop(struct adapter *adap); ++void t3_sge_start(adapter_t *adap); ++void t3_sge_stop(adapter_t *adap); ++void t3_start_sge_timers(struct adapter *adap); + void t3_stop_sge_timers(struct adapter *adap); +-void t3_free_sge_resources(struct adapter *adap); +-void t3_sge_err_intr_handler(struct adapter *adapter); +-irq_handler_t t3_intr_handler(struct adapter *adap, int polling); ++void t3_free_sge_resources(adapter_t *adap); ++void t3_sge_err_intr_handler(adapter_t *adapter); + int t3_eth_xmit(struct sk_buff *skb, struct net_device *dev); +-int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb); ++int t3_mgmt_tx(adapter_t *adap, struct sk_buff *skb); + void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p); +-int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports, +- int irq_vec_idx, const struct qset_params *p, +- int ntxq, struct net_device *dev); ++int t3_sge_alloc_qset(adapter_t *adapter, unsigned int id, int nports, ++ int irq_vec_idx, const struct qset_params *p, ++ int ntxq, struct net_device *netdev); + int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx, + unsigned char *data); +-irqreturn_t t3_sge_intr_msix(int irq, void *cookie); + +-#endif /* __T3_ADAPTER_H__ */ ++#endif /* __T3_ADAPTER_H__ */ +diff -r c6413c34aa41 drivers/net/cxgb3/ael1002.c +--- a/drivers/net/cxgb3/ael1002.c Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/ael1002.c Tue Oct 06 09:37:59 2009 +0100 +@@ -1,34 +1,14 @@ + /* +- * Copyright (c) 2005-2007 Chelsio, Inc. All rights reserved. ++ * This file is part of the Chelsio T3 Ethernet driver. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: ++ * Copyright (C) 2005-2009 Chelsio Communications. All rights reserved. + * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ ++ + #include "common.h" + #include "regs.h" + +@@ -40,24 +20,56 @@ + }; + + enum { +- AEL100X_TX_DISABLE = 9, +- AEL100X_TX_CONFIG1 = 0xc002, ++ AEL100X_TX_DISABLE = 9, ++ AEL100X_TX_CONFIG1 = 0xc002, ++ + AEL1002_PWR_DOWN_HI = 0xc011, + AEL1002_PWR_DOWN_LO = 0xc012, +- AEL1002_XFI_EQL = 0xc015, +- AEL1002_LB_EN = 0xc017, +- AEL_OPT_SETTINGS = 0xc017, +- AEL_I2C_CTRL = 0xc30a, +- AEL_I2C_DATA = 0xc30b, +- AEL_I2C_STAT = 0xc30c, +- AEL2005_GPIO_CTRL = 0xc214, +- AEL2005_GPIO_STAT = 0xc215, ++ AEL1002_XFI_EQL = 0xc015, ++ AEL1002_LB_EN = 0xc017, ++ ++ AEL_OPT_SETTINGS = 0xc017, ++ AEL_I2C_CTRL = 0xc30a, ++ AEL_I2C_DATA = 0xc30b, ++ AEL_I2C_STAT = 0xc30c, ++ ++ AEL2005_GPIO_CTRL = 0xc214, ++ AEL2005_GPIO_STAT = 0xc215, ++ ++ AEL2020_GPIO_INTR = 0xc103, /* Latch High (LH) */ ++ AEL2020_GPIO_CTRL = 0xc108, /* Store Clear (SC) */ ++ AEL2020_GPIO_STAT = 0xc10c, /* Read Only (RO) */ ++ AEL2020_GPIO_CFG = 0xc110, /* Read Write (RW) */ ++ ++ /* there are four GPIO pins per PHY channel */ ++ /* ++ * Erratum: GPIO "ports" 2 & 3 are swapped relative to the ++ * documentation. "port 2" was supposed to manage GPIO X_0 ++ * and "port 3" was supposed to manage GPIO X_1. Instead ++ * port 2 manages GPIO X_1 and port 3 manages GPIO X_0 ... ++ */ ++ /* name/function port default at reset */ ++ AEL2020_GPIO_SDA = 0, /* IN: i2c serial data */ ++ AEL2020_GPIO_MODDET = 1, /* IN: Module Detect */ ++ AEL2020_GPIO_0 = 3, /* IN: unassigned */ ++ AEL2020_GPIO_1 = 2, /* OUT: unassigned */ ++ AEL2020_GPIO_LSTAT = AEL2020_GPIO_1, /* wired to link status LED */ + }; + + enum { edc_none, edc_sr, edc_twinax }; + + /* PHY module I2C device address */ +-#define MODULE_DEV_ADDR 0xa0 ++enum { ++ MODULE_DEV_ADDR = 0xa0, ++ SFF_DEV_ADDR = 0xa2, ++}; ++ ++/* PHY transceiver type */ ++enum { ++ phy_transtype_unknown = 0, ++ phy_transtype_sfp = 3, ++ phy_transtype_xfp = 6, ++}; + + #define AEL2005_MODDET_IRQ 4 + +@@ -91,6 +103,116 @@ + msleep(100); + t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio); + msleep(30); ++} ++ ++/* ++ * Read an 8-bit word from a device attached to the PHY's i2c bus. ++ */ ++static int ael_i2c_rd(struct cphy *phy, int dev_addr, int word_addr) ++{ ++ int i, err; ++ unsigned int stat, data; ++ ++ err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL, ++ (dev_addr << 8) | (1 << 8) | word_addr); ++ if (err) ++ return err; ++ ++ for (i = 0; i < 200; i++) { ++ msleep(1); ++ err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat); ++ if (err) ++ return err; ++ if ((stat & 3) == 1) { ++ err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_DATA, ++ &data); ++ if (err) ++ return err; ++ return data >> 8; ++ } ++ } ++ CH_WARN(phy->adapter, "PHY %u i2c read of dev.addr %#x.%#x timed out\n", ++ phy->addr, dev_addr, word_addr); ++ return -ETIMEDOUT; ++} ++ ++/* ++ * Write an 8-bit word to a device attached to the PHY's i2c bus. ++ */ ++static int ael_i2c_wr(struct cphy *phy, int dev_addr, int word_addr, int data) ++{ ++ int i, err; ++ unsigned int stat; ++ ++ err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_DATA, data); ++ if (err) ++ return err; ++ ++ err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL, ++ (dev_addr << 8) | (0 << 8) | word_addr); ++ if (err) ++ return err; ++ ++ for (i = 0; i < 200; i++) { ++ msleep(1); ++ err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat); ++ if (err) ++ return err; ++ if ((stat & 3) == 1) ++ return 0; ++ } ++ CH_WARN(phy->adapter, "PHY %u i2c Write of dev.addr %#x.%#x = %#x timed out\n", ++ phy->addr, dev_addr, word_addr, data); ++ return -ETIMEDOUT; ++} ++ ++static int get_phytrans_type(struct cphy *phy) ++{ ++ int v; ++ ++ v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0); ++ if (v < 0) ++ return phy_transtype_unknown; ++ ++ return v; ++} ++ ++static int ael_laser_down(struct cphy *phy, int enable) ++{ ++ int v, dev_addr; ++ ++ v = get_phytrans_type(phy); ++ if (v < 0) ++ return v; ++ ++ if (v == phy_transtype_sfp) { ++ /* Check SFF Soft TX disable is supported */ ++ v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 93); ++ if (v < 0) ++ return v; ++ ++ v &= 0x40; ++ if (!v) ++ return v; ++ ++ dev_addr = SFF_DEV_ADDR; ++ } else if (v == phy_transtype_xfp) ++ dev_addr = MODULE_DEV_ADDR; ++ else ++ return v; ++ ++ v = ael_i2c_rd(phy, dev_addr, 110); ++ if (v < 0) ++ return v; ++ ++ if (enable) ++ v |= 0x40; ++ else ++ v &= ~0x40; ++ ++ v = ael_i2c_wr(phy, dev_addr, 110, v); ++ ++ return v; + } + + static int ael1002_power_down(struct cphy *phy, int enable) +@@ -149,57 +271,167 @@ + return 0; + } + ++#ifdef C99_NOT_SUPPORTED + static struct cphy_ops ael1002_ops = { +- .reset = ael1002_reset, +- .intr_enable = ael1002_intr_noop, +- .intr_disable = ael1002_intr_noop, +- .intr_clear = ael1002_intr_noop, +- .intr_handler = ael1002_intr_noop, ++ ael1002_reset, ++ ael1002_intr_noop, ++ ael1002_intr_noop, ++ ael1002_intr_noop, ++ ael1002_intr_noop, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ get_link_status_r, ++ ael1002_power_down, ++}; ++#else ++static struct cphy_ops ael1002_ops = { ++ .reset = ael1002_reset, ++ .intr_enable = ael1002_intr_noop, ++ .intr_disable = ael1002_intr_noop, ++ .intr_clear = ael1002_intr_noop, ++ .intr_handler = ael1002_intr_noop, + .get_link_status = get_link_status_r, +- .power_down = ael1002_power_down, ++ .power_down = ael1002_power_down, + }; ++#endif + +-int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter, +- int phy_addr, const struct mdio_ops *mdio_ops) ++int t3_ael1002_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops) + { +- cphy_init(phy, adapter, phy_addr, &ael1002_ops, mdio_ops, ++ struct cphy *phy = &pinfo->phy; ++ ++ cphy_init(phy, pinfo->adapter, pinfo, phy_addr, &ael1002_ops, mdio_ops, + SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE, +- "10GBASE-R"); ++ "10GBASE-R"); + ael100x_txon(phy); ++ ael_laser_down(phy, 0); ++ + return 0; + } + + static int ael1006_reset(struct cphy *phy, int wait) + { +- return t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait); ++ int err; ++ ++ err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait); ++ if (err) ++ return err; ++ ++ t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, ++ F_GPIO6_OUT_VAL, 0); ++ ++ msleep(125); ++ ++ t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, ++ F_GPIO6_OUT_VAL, F_GPIO6_OUT_VAL); ++ ++ msleep(125); ++ ++ err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait); ++ if (err) ++ return err; ++ ++ msleep(125); ++ ++ err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, 1, 1); ++ if (err) ++ return err; ++ ++ msleep(125); ++ ++ err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, 1, 0); ++ ++ return err; ++ + } + +-static int ael1006_power_down(struct cphy *phy, int enable) ++#ifdef C99_NOT_SUPPORTED ++static struct cphy_ops ael1006_ops = { ++ ael1006_reset, ++ t3_phy_lasi_intr_enable, ++ t3_phy_lasi_intr_disable, ++ t3_phy_lasi_intr_clear, ++ t3_phy_lasi_intr_handler, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ get_link_status_r, ++ ael1002_power_down, ++}; ++#else ++static struct cphy_ops ael1006_ops = { ++ .reset = ael1006_reset, ++ .intr_enable = t3_phy_lasi_intr_enable, ++ .intr_disable = t3_phy_lasi_intr_disable, ++ .intr_clear = t3_phy_lasi_intr_clear, ++ .intr_handler = t3_phy_lasi_intr_handler, ++ .get_link_status = get_link_status_r, ++ .power_down = ael1002_power_down, ++}; ++#endif ++ ++int t3_ael1006_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops) + { +- return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, +- BMCR_PDOWN, enable ? BMCR_PDOWN : 0); +-} ++ struct cphy *phy = &pinfo->phy; + +-static struct cphy_ops ael1006_ops = { +- .reset = ael1006_reset, +- .intr_enable = t3_phy_lasi_intr_enable, +- .intr_disable = t3_phy_lasi_intr_disable, +- .intr_clear = t3_phy_lasi_intr_clear, +- .intr_handler = t3_phy_lasi_intr_handler, +- .get_link_status = get_link_status_r, +- .power_down = ael1006_power_down, +-}; +- +-int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter, +- int phy_addr, const struct mdio_ops *mdio_ops) +-{ +- cphy_init(phy, adapter, phy_addr, &ael1006_ops, mdio_ops, ++ cphy_init(phy, pinfo->adapter, pinfo, phy_addr, &ael1006_ops, mdio_ops, + SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE, +- "10GBASE-SR"); ++ "10GBASE-SR"); + ael100x_txon(phy); + return 0; + } + ++/* ++ * Decode our module type. ++ */ ++static int ael2xxx_get_module_type(struct cphy *phy, int delay_ms) ++{ ++ int v; ++ ++ if (delay_ms) ++ msleep(delay_ms); ++ ++ /* see SFF-8472 for below */ ++ v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 3); ++ if (v < 0) ++ return v; ++ ++ if (v == 0x10) ++ return phy_modtype_sr; ++ if (v == 0x20) ++ return phy_modtype_lr; ++ if (v == 0x40) ++ return phy_modtype_lrm; ++ ++ v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 6); ++ if (v < 0) ++ return v; ++ if (v != 4) ++ goto unknown; ++ ++ v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 10); ++ if (v < 0) ++ return v; ++ ++ if (v & 0x80) { ++ v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0x12); ++ if (v < 0) ++ return v; ++ return v > 10 ? phy_modtype_twinax_long : phy_modtype_twinax; ++ } ++unknown: ++ return phy_modtype_unknown; ++} ++ ++/* ++ * Code to support the Aeluros/NetLogic 2005 10Gb PHY. ++ */ + static int ael2005_setup_sr_edc(struct cphy *phy) + { + static struct reg_val regs[] = { +@@ -894,35 +1126,7 @@ + return err; + } + +-static int ael2005_i2c_rd(struct cphy *phy, int dev_addr, int word_addr) +-{ +- int i, err; +- unsigned int stat, data; +- +- err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL, +- (dev_addr << 8) | (1 << 8) | word_addr); +- if (err) +- return err; +- +- for (i = 0; i < 5; i++) { +- msleep(1); +- err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat); +- if (err) +- return err; +- if ((stat & 3) == 1) { +- err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_DATA, +- &data); +- if (err) +- return err; +- return data >> 8; +- } +- } +- CH_WARN(phy->adapter, "PHY %u I2C read of addr %u timed out\n", +- phy->addr, word_addr); +- return -ETIMEDOUT; +-} +- +-static int get_module_type(struct cphy *phy, int delay_ms) ++static int ael2005_get_module_type(struct cphy *phy, int delay_ms) + { + int v; + unsigned int stat; +@@ -934,39 +1138,7 @@ + if (stat & (1 << 8)) /* module absent */ + return phy_modtype_none; + +- if (delay_ms) +- msleep(delay_ms); +- +- /* see SFF-8472 for below */ +- v = ael2005_i2c_rd(phy, MODULE_DEV_ADDR, 3); +- if (v < 0) +- return v; +- +- if (v == 0x10) +- return phy_modtype_sr; +- if (v == 0x20) +- return phy_modtype_lr; +- if (v == 0x40) +- return phy_modtype_lrm; +- +- v = ael2005_i2c_rd(phy, MODULE_DEV_ADDR, 6); +- if (v < 0) +- return v; +- if (v != 4) +- goto unknown; +- +- v = ael2005_i2c_rd(phy, MODULE_DEV_ADDR, 10); +- if (v < 0) +- return v; +- +- if (v & 0x80) { +- v = ael2005_i2c_rd(phy, MODULE_DEV_ADDR, 0x12); +- if (v < 0) +- return v; +- return v > 10 ? phy_modtype_twinax_long : phy_modtype_twinax; +- } +-unknown: +- return phy_modtype_unknown; ++ return ael2xxx_get_module_type(phy, delay_ms); + } + + static int ael2005_intr_enable(struct cphy *phy) +@@ -1023,10 +1195,10 @@ + + msleep(50); + +- err = get_module_type(phy, 0); ++ err = ael2005_get_module_type(phy, 0); + if (err < 0) + return err; +- phy->modtype = err; ++ phy->modtype = (u8)err; + + if (err == phy_modtype_twinax || err == phy_modtype_twinax_long) + err = ael2005_setup_twinax_edc(phy, err); +@@ -1061,11 +1233,11 @@ + return ret; + + /* modules have max 300 ms init time after hot plug */ +- ret = get_module_type(phy, 300); ++ ret = ael2005_get_module_type(phy, 300); + if (ret < 0) + return ret; + +- phy->modtype = ret; ++ phy->modtype = (u8)ret; + if (ret == phy_modtype_none) + edc_needed = phy->priv; /* on unplug retain EDC */ + else if (ret == phy_modtype_twinax || +@@ -1086,10 +1258,26 @@ + return ret; + + ret |= cause; +- return ret ? ret : cphy_cause_link_change; ++ if (!ret) ++ ret |= cphy_cause_link_change; ++ return ret; + } + + static struct cphy_ops ael2005_ops = { ++#ifdef C99_NOT_SUPPORTED ++ ael2005_reset, ++ ael2005_intr_enable, ++ ael2005_intr_disable, ++ ael2005_intr_clear, ++ ael2005_intr_handler, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ get_link_status_r, ++ ael1002_power_down, ++#else + .reset = ael2005_reset, + .intr_enable = ael2005_intr_enable, + .intr_disable = ael2005_intr_disable, +@@ -1097,17 +1285,788 @@ + .intr_handler = ael2005_intr_handler, + .get_link_status = get_link_status_r, + .power_down = ael1002_power_down, ++#endif + }; + +-int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter, +- int phy_addr, const struct mdio_ops *mdio_ops) ++int t3_ael2005_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops) + { +- cphy_init(phy, adapter, phy_addr, &ael2005_ops, mdio_ops, ++ struct cphy *phy = &pinfo->phy; ++ ++ cphy_init(phy, pinfo->adapter, pinfo, phy_addr, &ael2005_ops, mdio_ops, + SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE | + SUPPORTED_IRQ, "10GBASE-R"); + msleep(125); ++ ael_laser_down(phy, 0); + return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, AEL_OPT_SETTINGS, 0, + 1 << 5); ++} ++ ++/* ++ * The Aeluros/NetLogic AEL2020 is nearly identical to the AEL2005. It's ++ * basically two AEL2005's packaged up into a single die. There are some ++ * small differences which we account for here: ++ * ++ * 1. AEL2020 Errata. See in particular erratum #2 concerning a "CDRLOL ++ * signal being asserted under all conditions" resulting in "PMD link ++ * status to be down all the time." ++ * ++ * 2. The Link Status LED is controlled by the AEL2020 GPIO configuration ++ * for AEL2020 GPIO pins 0_1 and 1_1. See comments regarding Traffic ++ * Indicator Mode on pages 18-20 of the AEL2020 datasheet. ++ * ++ * 3. Different GPIO logic used to enable, mask and detect interrupts, ++ * and detect module types. ++ * ++ * 4. The EDC logic can be turned off for optical modules resulting in ++ * significant power savings. ++ * ++ * 5. Slightly different reset logic and uP firmware. ++ * ++ * Unfortunately, despite the high degree of similarity between the AEL2005 ++ * and the AEL2020 PHYs, we need to duplicate the vast majority of the code ++ * because of the differences and the small size of the code base. ++ */ ++ ++/* ++ * Setup EDC and other parameters for operation with an optical module. ++ */ ++static int ael2020_setup_sr_edc(struct cphy *phy) ++{ ++ static struct reg_val regs[] = { ++ /* set CDR offset to 10 */ ++ { MDIO_DEV_PMA_PMD, 0xcc01, 0xffff, 0x488a }, ++ ++ /* adjust 10G RX bias current */ ++ { MDIO_DEV_PMA_PMD, 0xcb1b, 0xffff, 0x0200 }, ++ { MDIO_DEV_PMA_PMD, 0xcb1c, 0xffff, 0x00f0 }, ++ { MDIO_DEV_PMA_PMD, 0xcc06, 0xffff, 0x00e0 }, ++ ++ /* end */ ++ { 0, 0, 0, 0 } ++ }; ++ int err; ++ ++ err = set_phy_regs(phy, regs); ++ msleep(50); ++ if (err) ++ return err; ++ ++ phy->priv = edc_sr; ++ return 0; ++} ++ ++/* ++ * Setup EDC and other parameters for operation with an TWINAX module. ++ */ ++static int ael2020_setup_twinax_edc(struct cphy *phy, int modtype) ++{ ++ /* set uC to 40MHz */ ++ static struct reg_val uCclock40MHz[] = { ++ { MDIO_DEV_PMA_PMD, 0xff28, 0xffff, 0x4001 }, ++ { MDIO_DEV_PMA_PMD, 0xff2a, 0xffff, 0x0002 }, ++ { 0, 0, 0, 0 } ++ }; ++ ++ /* activate uC clock */ ++ static struct reg_val uCclockActivate[] = { ++ { MDIO_DEV_PMA_PMD, 0xd000, 0xffff, 0x5200 }, ++ { 0, 0, 0, 0 } ++ }; ++ ++ /* set PC to start of SRAM and activate uC */ ++ static struct reg_val uCactivate[] = { ++ { MDIO_DEV_PMA_PMD, 0xd080, 0xffff, 0x0100 }, ++ { MDIO_DEV_PMA_PMD, 0xd092, 0xffff, 0x0000 }, ++ { 0, 0, 0, 0 } ++ }; ++ ++ /* TWINAX EDC firmware */ ++ static u16 twinax_edc[] = { ++ 0xd800, 0x4009, ++ 0xd801, 0x2fff, ++ 0xd802, 0x300f, ++ 0xd803, 0x40aa, ++ 0xd804, 0x401c, ++ 0xd805, 0x401e, ++ 0xd806, 0x2ff4, ++ 0xd807, 0x3dc4, ++ 0xd808, 0x2035, ++ 0xd809, 0x3035, ++ 0xd80a, 0x6524, ++ 0xd80b, 0x2cb2, ++ 0xd80c, 0x3012, ++ 0xd80d, 0x1002, ++ 0xd80e, 0x26e2, ++ 0xd80f, 0x3022, ++ 0xd810, 0x1002, ++ 0xd811, 0x27d2, ++ 0xd812, 0x3022, ++ 0xd813, 0x1002, ++ 0xd814, 0x2822, ++ 0xd815, 0x3012, ++ 0xd816, 0x1002, ++ 0xd817, 0x2492, ++ 0xd818, 0x3022, ++ 0xd819, 0x1002, ++ 0xd81a, 0x2772, ++ 0xd81b, 0x3012, ++ 0xd81c, 0x1002, ++ 0xd81d, 0x23d2, ++ 0xd81e, 0x3022, ++ 0xd81f, 0x1002, ++ 0xd820, 0x22cd, ++ 0xd821, 0x301d, ++ 0xd822, 0x27f2, ++ 0xd823, 0x3022, ++ 0xd824, 0x1002, ++ 0xd825, 0x5553, ++ 0xd826, 0x0307, ++ 0xd827, 0x2522, ++ 0xd828, 0x3022, ++ 0xd829, 0x1002, ++ 0xd82a, 0x2142, ++ 0xd82b, 0x3012, ++ 0xd82c, 0x1002, ++ 0xd82d, 0x4016, ++ 0xd82e, 0x5e63, ++ 0xd82f, 0x0344, ++ 0xd830, 0x2142, ++ 0xd831, 0x3012, ++ 0xd832, 0x1002, ++ 0xd833, 0x400e, ++ 0xd834, 0x2522, ++ 0xd835, 0x3022, ++ 0xd836, 0x1002, ++ 0xd837, 0x2b52, ++ 0xd838, 0x3012, ++ 0xd839, 0x1002, ++ 0xd83a, 0x2742, ++ 0xd83b, 0x3022, ++ 0xd83c, 0x1002, ++ 0xd83d, 0x25e2, ++ 0xd83e, 0x3022, ++ 0xd83f, 0x1002, ++ 0xd840, 0x2fa4, ++ 0xd841, 0x3dc4, ++ 0xd842, 0x6624, ++ 0xd843, 0x414b, ++ 0xd844, 0x56b3, ++ 0xd845, 0x03c6, ++ 0xd846, 0x866b, ++ 0xd847, 0x400c, ++ 0xd848, 0x2712, ++ 0xd849, 0x3012, ++ 0xd84a, 0x1002, ++ 0xd84b, 0x2c4b, ++ 0xd84c, 0x309b, ++ 0xd84d, 0x56b3, ++ 0xd84e, 0x03c3, ++ 0xd84f, 0x866b, ++ 0xd850, 0x400c, ++ 0xd851, 0x2272, ++ 0xd852, 0x3022, ++ 0xd853, 0x1002, ++ 0xd854, 0x2742, ++ 0xd855, 0x3022, ++ 0xd856, 0x1002, ++ 0xd857, 0x25e2, ++ 0xd858, 0x3022, ++ 0xd859, 0x1002, ++ 0xd85a, 0x2fb4, ++ 0xd85b, 0x3dc4, ++ 0xd85c, 0x6624, ++ 0xd85d, 0x56b3, ++ 0xd85e, 0x03c3, ++ 0xd85f, 0x866b, ++ 0xd860, 0x401c, ++ 0xd861, 0x2c45, ++ 0xd862, 0x3095, ++ 0xd863, 0x5b53, ++ 0xd864, 0x2372, ++ 0xd865, 0x3012, ++ 0xd866, 0x13c2, ++ 0xd867, 0x5cc3, ++ 0xd868, 0x2712, ++ 0xd869, 0x3012, ++ 0xd86a, 0x1312, ++ 0xd86b, 0x2b52, ++ 0xd86c, 0x3012, ++ 0xd86d, 0x1002, ++ 0xd86e, 0x2742, ++ 0xd86f, 0x3022, ++ 0xd870, 0x1002, ++ 0xd871, 0x2582, ++ 0xd872, 0x3022, ++ 0xd873, 0x1002, ++ 0xd874, 0x2142, ++ 0xd875, 0x3012, ++ 0xd876, 0x1002, ++ 0xd877, 0x628f, ++ 0xd878, 0x2985, ++ 0xd879, 0x33a5, ++ 0xd87a, 0x25e2, ++ 0xd87b, 0x3022, ++ 0xd87c, 0x1002, ++ 0xd87d, 0x5653, ++ 0xd87e, 0x03d2, ++ 0xd87f, 0x401e, ++ 0xd880, 0x6f72, ++ 0xd881, 0x1002, ++ 0xd882, 0x628f, ++ 0xd883, 0x2304, ++ 0xd884, 0x3c84, ++ 0xd885, 0x6436, ++ 0xd886, 0xdff4, ++ 0xd887, 0x6436, ++ 0xd888, 0x2ff5, ++ 0xd889, 0x3005, ++ 0xd88a, 0x8656, ++ 0xd88b, 0xdfba, ++ 0xd88c, 0x56a3, ++ 0xd88d, 0xd05a, ++ 0xd88e, 0x2972, ++ 0xd88f, 0x3012, ++ 0xd890, 0x1392, ++ 0xd891, 0xd05a, ++ 0xd892, 0x56a3, ++ 0xd893, 0xdfba, ++ 0xd894, 0x0383, ++ 0xd895, 0x6f72, ++ 0xd896, 0x1002, ++ 0xd897, 0x2b45, ++ 0xd898, 0x3005, ++ 0xd899, 0x4178, ++ 0xd89a, 0x5653, ++ 0xd89b, 0x0384, ++ 0xd89c, 0x2a62, ++ 0xd89d, 0x3012, ++ 0xd89e, 0x1002, ++ 0xd89f, 0x2f05, ++ 0xd8a0, 0x3005, ++ 0xd8a1, 0x41c8, ++ 0xd8a2, 0x5653, ++ 0xd8a3, 0x0382, ++ 0xd8a4, 0x0002, ++ 0xd8a5, 0x4218, ++ 0xd8a6, 0x2474, ++ 0xd8a7, 0x3c84, ++ 0xd8a8, 0x6437, ++ 0xd8a9, 0xdff4, ++ 0xd8aa, 0x6437, ++ 0xd8ab, 0x2ff5, ++ 0xd8ac, 0x3c05, ++ 0xd8ad, 0x8757, ++ 0xd8ae, 0xb888, ++ 0xd8af, 0x9787, ++ 0xd8b0, 0xdff4, ++ 0xd8b1, 0x6724, ++ 0xd8b2, 0x866a, ++ 0xd8b3, 0x6f72, ++ 0xd8b4, 0x1002, ++ 0xd8b5, 0x2641, ++ 0xd8b6, 0x3021, ++ 0xd8b7, 0x1001, ++ 0xd8b8, 0xc620, ++ 0xd8b9, 0x0000, ++ 0xd8ba, 0xc621, ++ 0xd8bb, 0x0000, ++ 0xd8bc, 0xc622, ++ 0xd8bd, 0x00ce, ++ 0xd8be, 0xc623, ++ 0xd8bf, 0x007f, ++ 0xd8c0, 0xc624, ++ 0xd8c1, 0x0032, ++ 0xd8c2, 0xc625, ++ 0xd8c3, 0x0000, ++ 0xd8c4, 0xc627, ++ 0xd8c5, 0x0000, ++ 0xd8c6, 0xc628, ++ 0xd8c7, 0x0000, ++ 0xd8c8, 0xc62c, ++ 0xd8c9, 0x0000, ++ 0xd8ca, 0x0000, ++ 0xd8cb, 0x2641, ++ 0xd8cc, 0x3021, ++ 0xd8cd, 0x1001, ++ 0xd8ce, 0xc502, ++ 0xd8cf, 0x53ac, ++ 0xd8d0, 0xc503, ++ 0xd8d1, 0x2cd3, ++ 0xd8d2, 0xc600, ++ 0xd8d3, 0x2a6e, ++ 0xd8d4, 0xc601, ++ 0xd8d5, 0x2a2c, ++ 0xd8d6, 0xc605, ++ 0xd8d7, 0x5557, ++ 0xd8d8, 0xc60c, ++ 0xd8d9, 0x5400, ++ 0xd8da, 0xc710, ++ 0xd8db, 0x0700, ++ 0xd8dc, 0xc711, ++ 0xd8dd, 0x0f06, ++ 0xd8de, 0xc718, ++ 0xd8df, 0x0700, ++ 0xd8e0, 0xc719, ++ 0xd8e1, 0x0f06, ++ 0xd8e2, 0xc720, ++ 0xd8e3, 0x4700, ++ 0xd8e4, 0xc721, ++ 0xd8e5, 0x0f06, ++ 0xd8e6, 0xc728, ++ 0xd8e7, 0x0700, ++ 0xd8e8, 0xc729, ++ 0xd8e9, 0x1207, ++ 0xd8ea, 0xc801, ++ 0xd8eb, 0x7f50, ++ 0xd8ec, 0xc802, ++ 0xd8ed, 0x7760, ++ 0xd8ee, 0xc803, ++ 0xd8ef, 0x7fce, ++ 0xd8f0, 0xc804, ++ 0xd8f1, 0x520e, ++ 0xd8f2, 0xc805, ++ 0xd8f3, 0x5c11, ++ 0xd8f4, 0xc806, ++ 0xd8f5, 0x3c51, ++ 0xd8f6, 0xc807, ++ 0xd8f7, 0x4061, ++ 0xd8f8, 0xc808, ++ 0xd8f9, 0x49c1, ++ 0xd8fa, 0xc809, ++ 0xd8fb, 0x3840, ++ 0xd8fc, 0xc80a, ++ 0xd8fd, 0x0000, ++ 0xd8fe, 0xc821, ++ 0xd8ff, 0x0002, ++ 0xd900, 0xc822, ++ 0xd901, 0x0046, ++ 0xd902, 0xc844, ++ 0xd903, 0x182f, ++ 0xd904, 0xc013, ++ 0xd905, 0xf341, ++ 0xd906, 0xc084, ++ 0xd907, 0x0030, ++ 0xd908, 0xc904, ++ 0xd909, 0x1401, ++ 0xd90a, 0xcb0c, ++ 0xd90b, 0x0004, ++ 0xd90c, 0xcb0e, ++ 0xd90d, 0xa00a, ++ 0xd90e, 0xcb0f, ++ 0xd90f, 0xc0c0, ++ 0xd910, 0xcb10, ++ 0xd911, 0xc0c0, ++ 0xd912, 0xcb11, ++ 0xd913, 0x00a0, ++ 0xd914, 0xcb12, ++ 0xd915, 0x0007, ++ 0xd916, 0xc241, ++ 0xd917, 0xa000, ++ 0xd918, 0xc243, ++ 0xd919, 0x7fe0, ++ 0xd91a, 0xc604, ++ 0xd91b, 0x000e, ++ 0xd91c, 0xc609, ++ 0xd91d, 0x00f5, ++ 0xd91e, 0xc611, ++ 0xd91f, 0x000e, ++ 0xd920, 0xc660, ++ 0xd921, 0x9600, ++ 0xd922, 0xc687, ++ 0xd923, 0x0004, ++ 0xd924, 0xc60a, ++ 0xd925, 0x04f5, ++ 0xd926, 0x0000, ++ 0xd927, 0x2641, ++ 0xd928, 0x3021, ++ 0xd929, 0x1001, ++ 0xd92a, 0xc620, ++ 0xd92b, 0x14e5, ++ 0xd92c, 0xc621, ++ 0xd92d, 0xc53d, ++ 0xd92e, 0xc622, ++ 0xd92f, 0x3cbe, ++ 0xd930, 0xc623, ++ 0xd931, 0x4452, ++ 0xd932, 0xc624, ++ 0xd933, 0xc5c5, ++ 0xd934, 0xc625, ++ 0xd935, 0xe01e, ++ 0xd936, 0xc627, ++ 0xd937, 0x0000, ++ 0xd938, 0xc628, ++ 0xd939, 0x0000, ++ 0xd93a, 0xc62c, ++ 0xd93b, 0x0000, ++ 0xd93c, 0x0000, ++ 0xd93d, 0x2b84, ++ 0xd93e, 0x3c74, ++ 0xd93f, 0x6435, ++ 0xd940, 0xdff4, ++ 0xd941, 0x6435, ++ 0xd942, 0x2806, ++ 0xd943, 0x3006, ++ 0xd944, 0x8565, ++ 0xd945, 0x2b24, ++ 0xd946, 0x3c24, ++ 0xd947, 0x6436, ++ 0xd948, 0x1002, ++ 0xd949, 0x2b24, ++ 0xd94a, 0x3c24, ++ 0xd94b, 0x6436, ++ 0xd94c, 0x4045, ++ 0xd94d, 0x8656, ++ 0xd94e, 0x5663, ++ 0xd94f, 0x0302, ++ 0xd950, 0x401e, ++ 0xd951, 0x1002, ++ 0xd952, 0x2807, ++ 0xd953, 0x31a7, ++ 0xd954, 0x20c4, ++ 0xd955, 0x3c24, ++ 0xd956, 0x6724, ++ 0xd957, 0x1002, ++ 0xd958, 0x2807, ++ 0xd959, 0x3187, ++ 0xd95a, 0x20c4, ++ 0xd95b, 0x3c24, ++ 0xd95c, 0x6724, ++ 0xd95d, 0x1002, ++ 0xd95e, 0x24f4, ++ 0xd95f, 0x3c64, ++ 0xd960, 0x6436, ++ 0xd961, 0xdff4, ++ 0xd962, 0x6436, ++ 0xd963, 0x1002, ++ 0xd964, 0x2006, ++ 0xd965, 0x3d76, ++ 0xd966, 0xc161, ++ 0xd967, 0x6134, ++ 0xd968, 0x6135, ++ 0xd969, 0x5443, ++ 0xd96a, 0x0303, ++ 0xd96b, 0x6524, ++ 0xd96c, 0x00fb, ++ 0xd96d, 0x1002, ++ 0xd96e, 0x20d4, ++ 0xd96f, 0x3c24, ++ 0xd970, 0x2025, ++ 0xd971, 0x3005, ++ 0xd972, 0x6524, ++ 0xd973, 0x1002, ++ 0xd974, 0xd019, ++ 0xd975, 0x2104, ++ 0xd976, 0x3c24, ++ 0xd977, 0x2105, ++ 0xd978, 0x3805, ++ 0xd979, 0x6524, ++ 0xd97a, 0xdff4, ++ 0xd97b, 0x4005, ++ 0xd97c, 0x6524, ++ 0xd97d, 0x2e8d, ++ 0xd97e, 0x303d, ++ 0xd97f, 0x2408, ++ 0xd980, 0x35d8, ++ 0xd981, 0x5dd3, ++ 0xd982, 0x0307, ++ 0xd983, 0x8887, ++ 0xd984, 0x63a7, ++ 0xd985, 0x8887, ++ 0xd986, 0x63a7, ++ 0xd987, 0xdffd, ++ 0xd988, 0x00f9, ++ 0xd989, 0x1002, ++ 0xd98a, 0x0000, ++ }; ++ int i, err; ++ ++ /* set uC clock and activate it */ ++ err = set_phy_regs(phy, uCclock40MHz); ++ msleep(500); ++ if (err) ++ return err; ++ err = set_phy_regs(phy, uCclockActivate); ++ msleep(500); ++ if (err) ++ return err; ++ ++ /* write TWINAX EDC firmware into PHY */ ++ for (i = 0; i < ARRAY_SIZE(twinax_edc) && !err; i += 2) ++ err = mdio_write(phy, MDIO_DEV_PMA_PMD, twinax_edc[i], ++ twinax_edc[i + 1]); ++ /* activate uC */ ++ err = set_phy_regs(phy, uCactivate); ++ if (!err) ++ phy->priv = edc_twinax; ++ return err; ++} ++ ++/* ++ * Return Module Type. ++ */ ++static int ael2020_get_module_type(struct cphy *phy, int delay_ms) ++{ ++ int v; ++ unsigned int stat; ++ ++ v = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2020_GPIO_STAT, &stat); ++ if (v) ++ return v; ++ ++ if (stat & (0x1 << (AEL2020_GPIO_MODDET*4))) { ++ /* module absent */ ++ return phy_modtype_none; ++ } ++ ++ return ael2xxx_get_module_type(phy, delay_ms); ++} ++ ++/* ++ * Note that on the AEL2005 putting the PHY into low power mode also asserts ++ * the LOS_OUT pin on that PHY. On the AEL2020 the internal "LOS" signal ++ * which we route to the "link status" LED is _not_ affected by putting the ++ * PHY into low power mode. So we change the GPIO configuration for the link ++ * status LED in the interrupt enable/disable functions in order to cause it ++ * to go off when the interface is brought down. ++ */ ++ ++/* ++ * Enable PHY interrupts. We enable "Module Detection" interrupts (on any ++ * state transition) and then generic Link Alarm Status Interrupt (LASI). ++ */ ++static int ael2020_intr_enable(struct cphy *phy) ++{ ++ struct reg_val regs[] = { ++ /* output Module's Loss Of Signal (LOS) to LED */ ++ { MDIO_DEV_PMA_PMD, AEL2020_GPIO_CFG+AEL2020_GPIO_LSTAT, ++ 0xffff, 0x4 }, ++ { MDIO_DEV_PMA_PMD, AEL2020_GPIO_CTRL, ++ 0xffff, 0x8 << (AEL2020_GPIO_LSTAT*4) }, ++ ++ /* enable module detect status change interrupts */ ++ { MDIO_DEV_PMA_PMD, AEL2020_GPIO_CTRL, ++ 0xffff, 0x2 << (AEL2020_GPIO_MODDET*4) }, ++ ++ /* end */ ++ { 0, 0, 0, 0 } ++ }; ++ int err, link_ok = 0; ++ ++ /* set up "link status" LED and enable module change interrupts */ ++ err = set_phy_regs(phy, regs); ++ if (err) ++ return err; ++ ++ /* ++ * The AEL2020 doesn't seem to send an interrupt when a link is ++ * already establish and you enable interrupts. So we check the ++ * link status here and if it's established, we fake out a link ++ * status change (which is what a normal interrupt would do). ++ */ ++ err = get_link_status_r(phy, &link_ok, NULL, NULL, NULL); ++ if (err) ++ return err; ++ if (link_ok) ++ t3_link_changed(phy->adapter, phy->pinfo->port_id); ++ ++ /* enable standard Link Alarm Status Interrupts */ ++ err = t3_phy_lasi_intr_enable(phy); ++ if (err) ++ return err; ++ ++ return 0; ++} ++ ++/* ++ * Disable PHY interrupts. The mirror of the above ... ++ */ ++static int ael2020_intr_disable(struct cphy *phy) ++{ ++ struct reg_val regs[] = { ++ /* reset "link status" LED to "off" */ ++ { MDIO_DEV_PMA_PMD, AEL2020_GPIO_CTRL, ++ 0xffff, 0xb << (AEL2020_GPIO_LSTAT*4) }, ++ ++ /* disable module detect status change interrupts */ ++ { MDIO_DEV_PMA_PMD, AEL2020_GPIO_CTRL, ++ 0xffff, 0x1 << (AEL2020_GPIO_MODDET*4) }, ++ ++ /* end */ ++ { 0, 0, 0, 0 } ++ }; ++ int err; ++ ++ /* turn off "link status" LED and disable module change interrupts */ ++ err = set_phy_regs(phy, regs); ++ if (err) ++ return err; ++ ++ /* disable standard Link Alarm Status Interrupts */ ++ return t3_phy_lasi_intr_disable(phy); ++} ++ ++/* ++ * Clear PHY interrupt state. ++ */ ++static int ael2020_intr_clear(struct cphy *phy) ++{ ++ /* ++ * The GPIO Interrupt register on the AEL2020 is a "Latching High" ++ * (LH) register which is cleared to the current state when it's read. ++ * Thus, we simply read the register and discard the result. ++ */ ++ unsigned int stat; ++ int err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2020_GPIO_INTR, &stat); ++ return err ? err : t3_phy_lasi_intr_clear(phy); ++} ++ ++/* ++ * Common register settings for the AEL2020 when it comes out of reset. ++ */ ++static struct reg_val ael2020_reset_regs[] = { ++ /* Erratum #2: CDRLOL asserted, causing PMA link down status */ ++ { MDIO_DEV_PMA_PMD, 0xc003, 0xffff, 0x3101 }, ++ ++ /* force XAUI to send LF when RX_LOS is asserted */ ++ { MDIO_DEV_PMA_PMD, 0xcd40, 0xffff, 0x0001 }, ++ ++ /* allow writes to transceiver module EEPROM on i2c bus */ ++ { MDIO_DEV_PMA_PMD, 0xff02, 0xffff, 0x0023 }, ++ { MDIO_DEV_PMA_PMD, 0xff03, 0xffff, 0x0000 }, ++ { MDIO_DEV_PMA_PMD, 0xff04, 0xffff, 0x0000 }, ++ ++ /* end */ ++ { 0, 0, 0, 0 } ++}; ++ ++/* ++ * Reset the PHY and put it into a canonical operating state. ++ */ ++static int ael2020_reset(struct cphy *phy, int wait) ++{ ++ int err; ++ unsigned int lasi_ctrl; ++ ++ /* grab current interrupt state */ ++ err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, &lasi_ctrl); ++ if (err) ++ return err; ++ ++ err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, 125); ++ if (err) ++ return err; ++ msleep(100); ++ ++ /* basic initialization for all module types */ ++ phy->priv = edc_none; ++ err = set_phy_regs(phy, ael2020_reset_regs); ++ if (err) ++ return err; ++ ++ /* determine module type and perform appropriate initialization */ ++ err = ael2020_get_module_type(phy, 0); ++ if (err < 0) ++ return err; ++ phy->modtype = (u8)err; ++ if (err == phy_modtype_twinax || err == phy_modtype_twinax_long) ++ err = ael2020_setup_twinax_edc(phy, err); ++ else ++ err = ael2020_setup_sr_edc(phy); ++ if (err) ++ return err; ++ ++ /* reset wipes out interrupts, reenable them if they were on */ ++ if (lasi_ctrl & 1) ++ err = ael2020_intr_enable(phy); ++ return err; ++} ++ ++/* ++ * Handle a PHY interrupt. ++ */ ++static int ael2020_intr_handler(struct cphy *phy) ++{ ++ unsigned int stat; ++ int ret, edc_needed, cause = 0; ++ ++ ret = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2020_GPIO_INTR, &stat); ++ if (ret) ++ return ret; ++ ++ if (stat & (0x1 << AEL2020_GPIO_MODDET)) { ++ /* modules have max 300 ms init time after hot plug */ ++ ret = ael2020_get_module_type(phy, 300); ++ if (ret < 0) ++ return ret; ++ ++ phy->modtype = (u8)ret; ++ if (ret == phy_modtype_none) ++ edc_needed = phy->priv; /* on unplug retain EDC */ ++ else if (ret == phy_modtype_twinax || ++ ret == phy_modtype_twinax_long) ++ edc_needed = edc_twinax; ++ else ++ edc_needed = edc_sr; ++ ++ if (edc_needed != phy->priv) { ++ ret = ael2020_reset(phy, 0); ++ return ret ? ret : cphy_cause_module_change; ++ } ++ cause = cphy_cause_module_change; ++ } ++ ++ ret = t3_phy_lasi_intr_handler(phy); ++ if (ret < 0) ++ return ret; ++ ++ ret |= cause; ++ if (!ret) ++ ret |= cphy_cause_link_change; ++ return ret; ++} ++ ++static struct cphy_ops ael2020_ops = { ++#ifdef C99_NOT_SUPPORTED ++ ael2020_reset, ++ ael2020_intr_enable, ++ ael2020_intr_disable, ++ ael2020_intr_clear, ++ ael2020_intr_handler, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ get_link_status_r, ++ ael1002_power_down, ++#else ++ .reset = ael2020_reset, ++ .intr_enable = ael2020_intr_enable, ++ .intr_disable = ael2020_intr_disable, ++ .intr_clear = ael2020_intr_clear, ++ .intr_handler = ael2020_intr_handler, ++ .get_link_status = get_link_status_r, ++ .power_down = ael1002_power_down, ++#endif ++}; ++ ++int t3_ael2020_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops) ++{ ++ int err; ++ struct cphy *phy = &pinfo->phy; ++ ++ cphy_init(phy, pinfo->adapter, pinfo, phy_addr, &ael2020_ops, mdio_ops, ++ SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE | ++ SUPPORTED_IRQ, "10GBASE-R"); ++ msleep(125); ++ ++ err = set_phy_regs(phy, ael2020_reset_regs); ++ if (err) ++ return err; ++ ael_laser_down(phy, 0); ++ return 0; + } + + /* +@@ -1135,22 +2094,40 @@ + return 0; + } + ++#ifdef C99_NOT_SUPPORTED + static struct cphy_ops qt2045_ops = { +- .reset = ael1006_reset, +- .intr_enable = t3_phy_lasi_intr_enable, +- .intr_disable = t3_phy_lasi_intr_disable, +- .intr_clear = t3_phy_lasi_intr_clear, +- .intr_handler = t3_phy_lasi_intr_handler, ++ ael1006_reset, ++ t3_phy_lasi_intr_enable, ++ t3_phy_lasi_intr_disable, ++ t3_phy_lasi_intr_clear, ++ t3_phy_lasi_intr_handler, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ get_link_status_x, ++ ael1002_power_down, ++}; ++#else ++static struct cphy_ops qt2045_ops = { ++ .reset = ael1006_reset, ++ .intr_enable = t3_phy_lasi_intr_enable, ++ .intr_disable = t3_phy_lasi_intr_disable, ++ .intr_clear = t3_phy_lasi_intr_clear, ++ .intr_handler = t3_phy_lasi_intr_handler, + .get_link_status = get_link_status_x, +- .power_down = ael1006_power_down, ++ .power_down = ael1002_power_down, + }; ++#endif + +-int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, +- int phy_addr, const struct mdio_ops *mdio_ops) ++int t3_qt2045_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops) + { + unsigned int stat; ++ struct cphy *phy = &pinfo->phy; + +- cphy_init(phy, adapter, phy_addr, &qt2045_ops, mdio_ops, ++ cphy_init(phy, pinfo->adapter, pinfo, phy_addr, &qt2045_ops, mdio_ops, + SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP, + "10GBASE-CX4"); + +@@ -1174,15 +2151,16 @@ + { + if (link_ok) { + unsigned int status; ++ adapter_t *adapter = phy->adapter; + +- status = t3_read_reg(phy->adapter, ++ status = t3_read_reg(adapter, + XGM_REG(A_XGM_SERDES_STAT0, phy->addr)) | +- t3_read_reg(phy->adapter, +- XGM_REG(A_XGM_SERDES_STAT1, phy->addr)) | +- t3_read_reg(phy->adapter, +- XGM_REG(A_XGM_SERDES_STAT2, phy->addr)) | +- t3_read_reg(phy->adapter, +- XGM_REG(A_XGM_SERDES_STAT3, phy->addr)); ++ t3_read_reg(adapter, ++ XGM_REG(A_XGM_SERDES_STAT1, phy->addr)) | ++ t3_read_reg(adapter, ++ XGM_REG(A_XGM_SERDES_STAT2, phy->addr)) | ++ t3_read_reg(adapter, ++ XGM_REG(A_XGM_SERDES_STAT3, phy->addr)); + *link_ok = !(status & F_LOWSIG0); + } + if (speed) +@@ -1197,20 +2175,37 @@ + return 0; + } + ++#ifdef C99_NOT_SUPPORTED + static struct cphy_ops xaui_direct_ops = { +- .reset = xaui_direct_reset, +- .intr_enable = ael1002_intr_noop, +- .intr_disable = ael1002_intr_noop, +- .intr_clear = ael1002_intr_noop, +- .intr_handler = ael1002_intr_noop, ++ xaui_direct_reset, ++ ael1002_intr_noop, ++ ael1002_intr_noop, ++ ael1002_intr_noop, ++ ael1002_intr_noop, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ xaui_direct_get_link_status, ++ xaui_direct_power_down, ++}; ++#else ++static struct cphy_ops xaui_direct_ops = { ++ .reset = xaui_direct_reset, ++ .intr_enable = ael1002_intr_noop, ++ .intr_disable = ael1002_intr_noop, ++ .intr_clear = ael1002_intr_noop, ++ .intr_handler = ael1002_intr_noop, + .get_link_status = xaui_direct_get_link_status, +- .power_down = xaui_direct_power_down, ++ .power_down = xaui_direct_power_down, + }; ++#endif + +-int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter, +- int phy_addr, const struct mdio_ops *mdio_ops) ++int t3_xaui_direct_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops) + { +- cphy_init(phy, adapter, phy_addr, &xaui_direct_ops, mdio_ops, ++ cphy_init(&pinfo->phy, pinfo->adapter, pinfo, phy_addr, &xaui_direct_ops, mdio_ops, + SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP, + "10GBASE-CX4"); + return 0; +diff -r c6413c34aa41 drivers/net/cxgb3/aq100x.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cxgb3/aq100x.c Tue Oct 06 09:37:59 2009 +0100 +@@ -0,0 +1,404 @@ ++/* ++ * This file is part of the Chelsio T3 Ethernet driver. ++ * ++ * Copyright (C) 2009 Chelsio Communications. All rights reserved. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. ++ */ ++ ++#include "common.h" ++#include "regs.h" ++ ++/* ++ * Search for this in the entire file and fix each code block before release. ++ */ ++ ++#undef AQ_USE_INTERRUPTS ++ ++enum { ++ /* MDIO_DEV_PMA_PMD registers */ ++ AQ_LINK_STAT = 0xe800, ++ AQ_IMASK_PMA = 0xf000, ++ ++ /* MDIO_DEV_XGXS registers */ ++ AQ_XAUI_RX_CFG = 0xc400, ++ AQ_XAUI_TX_CFG = 0xe400, ++ ++ /* MDIO_DEV_ANEG registers */ ++ AQ_100M_CTRL = 0x0010, ++ AQ_10G_CTRL = 0x0020, ++ AQ_1G_CTRL = 0xc400, ++ AQ_ANEG_STAT = 0xc800, ++ ++ /* MDIO_DEV_VEND1 registers */ ++ AQ_FW_VERSION = 0x0020, ++ AQ_THERMAL1 = 0xc820, ++ AQ_THERMAL2 = 0xc821, ++ AQ_IFLAG_GLOBAL = 0xfc00, ++ AQ_IMASK_GLOBAL = 0xff00, ++}; ++ ++#define AQBIT(x) (1 << (x)) ++#define IMASK_PMA AQBIT(0x2) ++#define IMASK_GLOBAL AQBIT(0xf) ++#define ADV_1G_FULL AQBIT(0xf) ++#define ADV_1G_HALF AQBIT(0xe) ++#define ADV_10G_FULL AQBIT(0xc) ++#define AQ_RESET (AQBIT(0xe) | AQBIT(0xf)) ++#define AQ_LOWPOWER AQBIT(0xb) ++ ++#if 0 ++/* ++ * Return value is temperature in celcius, 0xffff for error or don't know. ++ */ ++static int ++aq100x_temperature(struct cphy *phy) ++{ ++ int v; ++ ++ if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL2, &v) || ++ v == 0xffff || (v & 1) != 1) ++ return (0xffff); ++ ++ if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL1, &v)) ++ return (0xffff); ++ ++ return ((int)((signed char)(v >> 8))); ++} ++#endif ++ ++static int ++aq100x_reset(struct cphy *phy, int wait) ++{ ++ int err; ++ ++#ifdef AQ_USE_INTERRUPTS ++ unsigned int imask = 0; ++ ++ err = mdio_read(phy, MDIO_DEV_VEND1, AQ_IMASK_GLOBAL, &imask); ++ if (err) ++ return (err); ++#endif ++ ++ /* ++ * Ignore the caller specified wait time; always wait for the reset to ++ * complete. Can take upto 3s. ++ */ ++ err = t3_phy_reset(phy, MDIO_DEV_VEND1, 3000); ++ if (err) { ++ CH_WARN(phy->adapter, "PHY%d: reset failed (0x%x).\n", ++ phy->addr, err); ++ return (err); ++ } ++ ++#ifdef AQ_USE_INTERRUPTS ++ if (imask && imask != 0xffff) ++ err = mdio_write(phy, MDIO_DEV_VEND1, AQ_IMASK_GLOBAL, imask); ++#endif ++ ++ return (err); ++} ++ ++static int ++aq100x_intr_enable(struct cphy *phy) ++{ ++ int err; ++ ++ err = mdio_write(phy, MDIO_DEV_PMA_PMD, AQ_IMASK_PMA, IMASK_PMA); ++ if (err) ++ return (err); ++ ++ err = mdio_write(phy, MDIO_DEV_VEND1, AQ_IMASK_GLOBAL, IMASK_GLOBAL); ++ return (err); ++} ++ ++static int ++aq100x_intr_disable(struct cphy *phy) ++{ ++ return mdio_write(phy, MDIO_DEV_VEND1, AQ_IMASK_GLOBAL, 0); ++} ++ ++static int ++aq100x_intr_clear(struct cphy *phy) ++{ ++ unsigned int v; ++ ++ (void) mdio_read(phy, MDIO_DEV_VEND1, AQ_IFLAG_GLOBAL, &v); ++ (void) mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR, &v); ++ ++ return (0); ++} ++ ++static int ++aq100x_intr_handler(struct cphy *phy) ++{ ++ int err; ++ unsigned int cause, v; ++ ++ err = mdio_read(phy, MDIO_DEV_VEND1, AQ_IFLAG_GLOBAL, &cause); ++ if (err) ++ return (err); ++ ++ /* Read (and reset) the latching version of the status */ ++ (void) mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR, &v); ++ ++ return (cphy_cause_link_change); ++} ++ ++static int ++aq100x_power_down(struct cphy *phy, int off) ++{ ++ return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, BMCR_PDOWN, ++ off ? BMCR_PDOWN : 0); ++} ++ ++static int ++aq100x_autoneg_enable(struct cphy *phy) ++{ ++ int err; ++ unsigned int clr = 0; ++ ++#ifdef AQ_USE_INTERRUPTS ++ /* ++ * Not sure why, but interrupt masks are cleared if this bit is 1 when ++ * we write to mmd 7 ++ */ ++ clr = BMCR_RESET; ++#endif ++ ++ err = aq100x_power_down(phy, 0); ++ if (!err) ++ err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR, clr, ++ BMCR_ANENABLE | BMCR_ANRESTART); ++ ++ return (err); ++} ++ ++static int ++aq100x_autoneg_restart(struct cphy *phy) ++{ ++ int err; ++ unsigned int clr = 0; ++ ++#ifdef AQ_USE_INTERRUPTS ++ /* ++ * Not sure why, but interrupt masks are cleared if this bit is 1 when ++ * we write to mmd 7 ++ */ ++ clr = BMCR_RESET; ++#endif ++ err = aq100x_power_down(phy, 0); ++ if (!err) ++ err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR, ++ clr, BMCR_ANRESTART); ++ ++ return (err); ++} ++ ++static int ++aq100x_advertise(struct cphy *phy, unsigned int advertise_map) ++{ ++ unsigned int adv; ++ int err; ++ ++ /* 10G advertisement */ ++ adv = 0; ++ if (advertise_map & ADVERTISED_10000baseT_Full) ++ adv |= ADV_10G_FULL; ++ err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, AQ_10G_CTRL, ++ ADV_10G_FULL, adv); ++ if (err) ++ return (err); ++ ++ /* 1G advertisement */ ++ adv = 0; ++ if (advertise_map & ADVERTISED_1000baseT_Full) ++ adv |= ADV_1G_FULL; ++ if (advertise_map & ADVERTISED_1000baseT_Half) ++ adv |= ADV_1G_HALF; ++ err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, AQ_1G_CTRL, ++ ADV_1G_FULL | ADV_1G_HALF, adv); ++ if (err) ++ return (err); ++ ++ /* 100M, pause advertisement */ ++ adv = 0; ++ if (advertise_map & ADVERTISED_100baseT_Half) ++ adv |= ADVERTISE_100HALF; ++ if (advertise_map & ADVERTISED_100baseT_Full) ++ adv |= ADVERTISE_100FULL; ++ if (advertise_map & ADVERTISED_Pause) ++ adv |= ADVERTISE_PAUSE_CAP; ++ if (advertise_map & ADVERTISED_Asym_Pause) ++ adv |= ADVERTISE_PAUSE_ASYM; ++ err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, AQ_100M_CTRL, 0xfe0, adv); ++ ++ return (err); ++} ++ ++static int ++aq100x_set_loopback(struct cphy *phy, int mmd, int dir, int enable) ++{ ++ return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, ++ BMCR_LOOPBACK, enable ? BMCR_LOOPBACK : 0); ++} ++ ++static int ++aq100x_set_speed_duplex(struct cphy *phy, int speed, int duplex) ++{ ++ /* no can do */ ++ return (-1); ++} ++ ++static int ++aq100x_get_link_status(struct cphy *phy, int *link_ok, int *speed, int *duplex, ++ int *fc) ++{ ++ int err; ++ unsigned int v; ++ ++ if (link_ok) { ++ err = mdio_read(phy, MDIO_DEV_PMA_PMD, AQ_LINK_STAT, &v); ++ if (err) ++ return (err); ++ ++ *link_ok = v & 1; ++ if (!*link_ok) ++ return (0); ++ } ++ ++ err = mdio_read(phy, MDIO_DEV_ANEG, AQ_ANEG_STAT, &v); ++ if (err) ++ return (err); ++ ++ if (speed) { ++ switch (v & 0x6) { ++ case 0x6: *speed = SPEED_10000; ++ break; ++ case 0x4: *speed = SPEED_1000; ++ break; ++ case 0x2: *speed = SPEED_100; ++ break; ++ case 0x0: *speed = SPEED_10; ++ break; ++ } ++ } ++ ++ if (duplex) ++ *duplex = v & 1 ? DUPLEX_FULL : DUPLEX_HALF; ++ ++ return (0); ++} ++ ++static struct cphy_ops aq100x_ops = { ++ .reset = aq100x_reset, ++ .intr_enable = aq100x_intr_enable, ++ .intr_disable = aq100x_intr_disable, ++ .intr_clear = aq100x_intr_clear, ++ .intr_handler = aq100x_intr_handler, ++ .autoneg_enable = aq100x_autoneg_enable, ++ .autoneg_restart = aq100x_autoneg_restart, ++ .advertise = aq100x_advertise, ++ .set_loopback = aq100x_set_loopback, ++ .set_speed_duplex = aq100x_set_speed_duplex, ++ .get_link_status = aq100x_get_link_status, ++ .power_down = aq100x_power_down, ++}; ++ ++int ++t3_aq100x_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops) ++{ ++ struct cphy *phy = &pinfo->phy; ++ unsigned int v, v2, gpio, wait; ++ int err; ++ adapter_t *adapter = pinfo->adapter; ++ ++ cphy_init(&pinfo->phy, adapter, pinfo, phy_addr, &aq100x_ops, mdio_ops, ++ SUPPORTED_1000baseT_Full | SUPPORTED_10000baseT_Full | ++ SUPPORTED_TP | SUPPORTED_Autoneg | SUPPORTED_AUI | ++ SUPPORTED_MISC_IRQ, "1000/10GBASE-T"); ++ ++ /* ++ * The PHY has been out of reset ever since the system powered up. So ++ * we do a hard reset over here. ++ */ ++ gpio = phy_addr ? F_GPIO10_OUT_VAL : F_GPIO6_OUT_VAL; ++ t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, gpio, 0); ++ msleep(1); ++ t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, gpio, gpio); ++ ++#ifdef AQ_USE_INTERRUPTS ++ phy->caps |= SUPPORTED_IRQ; ++#endif ++ ++ /* ++ * Give it enough time to load the firmware and get ready for mdio. ++ */ ++ msleep(1000); ++ wait = 500; /* in 10ms increments */ ++ do { ++ err = mdio_read(phy, MDIO_DEV_VEND1, MII_BMCR, &v); ++ if (err || v == 0xffff) { ++ ++ /* Allow prep_adapter to succeed when ffff is read */ ++ ++ CH_WARN(adapter, "PHY%d: reset failed (0x%x, 0x%x).\n", ++ phy_addr, err, v); ++ goto done; ++ } ++ ++ v &= AQ_RESET; ++ if (v) ++ msleep(10); ++ } while (v && --wait); ++ if (v) { ++ CH_WARN(adapter, "PHY%d: reset timed out (0x%x).\n", ++ phy_addr, v); ++ ++ goto done; /* let prep_adapter succeed */ ++ } ++ ++ /* Datasheet says 3s max but this has been observed */ ++ wait = (500 - wait) * 10 + 1000; ++ if (wait > 3000) ++ CH_WARN(adapter, "PHY%d: reset took %ums\n", phy_addr, wait); ++ ++ /* Firmware version check. */ ++ (void) mdio_read(phy, MDIO_DEV_VEND1, AQ_FW_VERSION, &v); ++ if (v != 0x101) ++ CH_WARN(adapter, "PHY%d: unknown firmware %d\n", phy_addr, v); ++ ++ /* ++ * The PHY should start in really-low-power mode. Prepare it for normal ++ * operations. ++ */ ++ err = mdio_read(phy, MDIO_DEV_VEND1, MII_BMCR, &v); ++ if (err) ++ return (err); ++ if (v & AQ_LOWPOWER) { ++ err = t3_mdio_change_bits(phy, MDIO_DEV_VEND1, MII_BMCR, ++ AQ_LOWPOWER, 0); ++ if (err) ++ return (err); ++ msleep(10); ++ } else ++ CH_WARN(adapter, "PHY%d does not start in low power mode.\n", ++ phy_addr); ++ ++ /* ++ * Verify XAUI settings, but let prep succeed no matter what. ++ */ ++ v = v2 = 0; ++ (void) mdio_read(phy, MDIO_DEV_XGXS, AQ_XAUI_RX_CFG, &v); ++ (void) mdio_read(phy, MDIO_DEV_XGXS, AQ_XAUI_TX_CFG, &v2); ++ if (v != 0x1b || v2 != 0x1b) ++ CH_WARN(adapter, "PHY%d: incorrect XAUI settings (0x%x, 0x%x).\n", ++ phy_addr, v, v2); ++ ++done: ++ return (err); ++} +diff -r c6413c34aa41 drivers/net/cxgb3/common.h +--- a/drivers/net/cxgb3/common.h Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/common.h Tue Oct 06 09:37:59 2009 +0100 +@@ -1,128 +1,53 @@ + /* +- * Copyright (c) 2005-2007 Chelsio, Inc. All rights reserved. ++ * This file is part of the Chelsio T3 Ethernet driver. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: ++ * Copyright (C) 2005-2009 Chelsio Communications. All rights reserved. + * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ ++ + #ifndef __CHELSIO_COMMON_H + #define __CHELSIO_COMMON_H + +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include "version.h" +- +-#define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__) +-#define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ## __VA_ARGS__) +-#define CH_ALERT(adap, fmt, ...) \ +- dev_printk(KERN_ALERT, &adap->pdev->dev, fmt, ## __VA_ARGS__) +- +-/* +- * More powerful macro that selectively prints messages based on msg_enable. +- * For info and debugging messages. +- */ +-#define CH_MSG(adapter, level, category, fmt, ...) do { \ +- if ((adapter)->msg_enable & NETIF_MSG_##category) \ +- dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \ +- ## __VA_ARGS__); \ +-} while (0) +- +-#ifdef DEBUG +-# define CH_DBG(adapter, category, fmt, ...) \ +- CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__) +-#else +-# define CH_DBG(adapter, category, fmt, ...) +-#endif +- +-/* Additional NETIF_MSG_* categories */ +-#define NETIF_MSG_MMIO 0x8000000 +- +-struct t3_rx_mode { +- struct net_device *dev; +- struct dev_mc_list *mclist; +- unsigned int idx; +-}; +- +-static inline void init_rx_mode(struct t3_rx_mode *p, struct net_device *dev, +- struct dev_mc_list *mclist) +-{ +- p->dev = dev; +- p->mclist = mclist; +- p->idx = 0; +-} +- +-static inline u8 *t3_get_next_mcaddr(struct t3_rx_mode *rm) +-{ +- u8 *addr = NULL; +- +- if (rm->mclist && rm->idx < rm->dev->mc_count) { +- addr = rm->mclist->dmi_addr; +- rm->mclist = rm->mclist->next; +- rm->idx++; +- } +- return addr; +-} ++#include "osdep.h" + + enum { +- MAX_NPORTS = 2, /* max # of ports */ +- MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */ +- EEPROMSIZE = 8192, /* Serial EEPROM size */ ++ MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */ ++ EEPROMSIZE = 8192, /* Serial EEPROM size */ + SERNUM_LEN = 16, /* Serial # length */ +- RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ +- TCB_SIZE = 128, /* TCB size */ +- NMTUS = 16, /* size of MTU table */ +- NCCTRL_WIN = 32, /* # of congestion control windows */ +- PROTO_SRAM_LINES = 128, /* size of TP sram */ ++ ECNUM_LEN = 16, /* EC # length */ ++ RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ ++ TCB_SIZE = 128, /* TCB size */ ++ NMTUS = 16, /* size of MTU table */ ++ NCCTRL_WIN = 32, /* # of congestion control windows */ ++ NTX_SCHED = 8, /* # of HW Tx scheduling queues */ ++ PROTO_SRAM_LINES = 128, /* size of protocol sram */ ++ EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */ + }; + + #define MAX_RX_COALESCING_LEN 12288U + + enum { +- PAUSE_RX = 1 << 0, +- PAUSE_TX = 1 << 1, ++ PAUSE_RX = 1 << 0, ++ PAUSE_TX = 1 << 1, + PAUSE_AUTONEG = 1 << 2 + }; + + enum { +- SUPPORTED_IRQ = 1 << 24 ++ SUPPORTED_LINK_IRQ = 1 << 24, ++ SUPPORTED_MISC_IRQ = 1 << 26, ++ SUPPORTED_IRQ = (SUPPORTED_LINK_IRQ | SUPPORTED_MISC_IRQ) + }; + +-enum { /* adapter interrupt-maintained statistics */ ++enum { /* adapter interrupt-maintained statistics */ + STAT_ULP_CH0_PBL_OOB, + STAT_ULP_CH1_PBL_OOB, + STAT_PCI_CORR_ECC, + +- IRQ_NUM_STATS /* keep last */ ++ IRQ_NUM_STATS /* keep last */ + }; + + enum { +@@ -150,24 +75,47 @@ + (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) + + enum { +- SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ +- SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ +- SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ ++ FW_VERSION_MAJOR = 7, ++ FW_VERSION_MINOR = 7, ++ FW_VERSION_MICRO = 0 + }; + +-enum sge_context_type { /* SGE egress context types */ ++enum { ++ LA_CTRL = 0x80, ++ LA_DATA = 0x84, ++ LA_ENTRIES = 512 ++}; ++ ++enum { ++ IOQ_ENTRIES = 7 ++}; ++ ++struct t3_ioq_entry { ++ u32 ioq_cp; ++ u32 ioq_pp; ++ u32 ioq_alen; ++ u32 ioq_stats; ++}; ++ ++enum { ++ SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ ++ SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ ++ SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ ++}; ++ ++enum sge_context_type { /* SGE egress context types */ + SGE_CNTXT_RDMA = 0, +- SGE_CNTXT_ETH = 2, ++ SGE_CNTXT_ETH = 2, + SGE_CNTXT_OFLD = 4, + SGE_CNTXT_CTRL = 5 + }; + + enum { +- AN_PKT_SIZE = 32, /* async notification packet size */ +- IMMED_PKT_SIZE = 48 /* packet size for immediate data */ ++ AN_PKT_SIZE = 32, /* async notification packet size */ ++ IMMED_PKT_SIZE = 48 /* packet size for immediate data */ + }; + +-struct sg_ent { /* SGE scatter/gather entry */ ++struct sg_ent { /* SGE scatter/gather entry */ + __be32 len[2]; + __be64 addr[2]; + }; +@@ -180,24 +128,26 @@ + #define TX_DESC_FLITS 16U + #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) + ++#define MAX_PHYINTRS 4 ++ + struct cphy; +-struct adapter; + + struct mdio_ops { +- int (*read)(struct adapter *adapter, int phy_addr, int mmd_addr, +- int reg_addr, unsigned int *val); +- int (*write)(struct adapter *adapter, int phy_addr, int mmd_addr, +- int reg_addr, unsigned int val); ++ int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr, ++ int reg_addr, unsigned int *val); ++ int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr, ++ int reg_addr, unsigned int val); + }; + + struct adapter_info { +- unsigned char nports; /* # of ports */ +- unsigned char phy_base_addr; /* MDIO PHY base address */ +- unsigned int gpio_out; /* GPIO output settings */ +- unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */ +- unsigned long caps; /* adapter capabilities */ +- const struct mdio_ops *mdio_ops; /* MDIO operations */ +- const char *desc; /* product description */ ++ unsigned char nports0; /* # of ports on channel 0 */ ++ unsigned char nports1; /* # of ports on channel 1 */ ++ unsigned char phy_base_addr; /* MDIO PHY base address */ ++ unsigned int gpio_out; /* GPIO output settings */ ++ unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */ ++ unsigned long caps; /* adapter capabilities */ ++ const struct mdio_ops *mdio_ops; /* MDIO operations */ ++ const char *desc; /* product description */ + }; + + struct mc5_stats { +@@ -218,23 +168,23 @@ + }; + + struct mac_stats { +- u64 tx_octets; /* total # of octets in good frames */ +- u64 tx_octets_bad; /* total # of octets in error frames */ +- u64 tx_frames; /* all good frames */ +- u64 tx_mcast_frames; /* good multicast frames */ +- u64 tx_bcast_frames; /* good broadcast frames */ +- u64 tx_pause; /* # of transmitted pause frames */ +- u64 tx_deferred; /* frames with deferred transmissions */ +- u64 tx_late_collisions; /* # of late collisions */ +- u64 tx_total_collisions; /* # of total collisions */ +- u64 tx_excess_collisions; /* frame errors from excessive collissions */ +- u64 tx_underrun; /* # of Tx FIFO underruns */ +- u64 tx_len_errs; /* # of Tx length errors */ +- u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ +- u64 tx_excess_deferral; /* # of frames with excessive deferral */ +- u64 tx_fcs_errs; /* # of frames with bad FCS */ ++ u64 tx_octets; /* total # of octets in good frames */ ++ u64 tx_octets_bad; /* total # of octets in error frames */ ++ u64 tx_frames; /* all good frames */ ++ u64 tx_mcast_frames; /* good multicast frames */ ++ u64 tx_bcast_frames; /* good broadcast frames */ ++ u64 tx_pause; /* # of transmitted pause frames */ ++ u64 tx_deferred; /* frames with deferred transmissions */ ++ u64 tx_late_collisions; /* # of late collisions */ ++ u64 tx_total_collisions; /* # of total collisions */ ++ u64 tx_excess_collisions; /* frame errors from excessive collissions */ ++ u64 tx_underrun; /* # of Tx FIFO underruns */ ++ u64 tx_len_errs; /* # of Tx length errors */ ++ u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ ++ u64 tx_excess_deferral; /* # of frames with excessive deferral */ ++ u64 tx_fcs_errs; /* # of frames with bad FCS */ + +- u64 tx_frames_64; /* # of Tx frames in a particular range */ ++ u64 tx_frames_64; /* # of Tx frames in a particular range */ + u64 tx_frames_65_127; + u64 tx_frames_128_255; + u64 tx_frames_256_511; +@@ -242,24 +192,24 @@ + u64 tx_frames_1024_1518; + u64 tx_frames_1519_max; + +- u64 rx_octets; /* total # of octets in good frames */ +- u64 rx_octets_bad; /* total # of octets in error frames */ +- u64 rx_frames; /* all good frames */ +- u64 rx_mcast_frames; /* good multicast frames */ +- u64 rx_bcast_frames; /* good broadcast frames */ +- u64 rx_pause; /* # of received pause frames */ +- u64 rx_fcs_errs; /* # of received frames with bad FCS */ +- u64 rx_align_errs; /* alignment errors */ +- u64 rx_symbol_errs; /* symbol errors */ +- u64 rx_data_errs; /* data errors */ +- u64 rx_sequence_errs; /* sequence errors */ +- u64 rx_runt; /* # of runt frames */ +- u64 rx_jabber; /* # of jabber frames */ +- u64 rx_short; /* # of short frames */ +- u64 rx_too_long; /* # of oversized frames */ +- u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ ++ u64 rx_octets; /* total # of octets in good frames */ ++ u64 rx_octets_bad; /* total # of octets in error frames */ ++ u64 rx_frames; /* all good frames */ ++ u64 rx_mcast_frames; /* good multicast frames */ ++ u64 rx_bcast_frames; /* good broadcast frames */ ++ u64 rx_pause; /* # of received pause frames */ ++ u64 rx_fcs_errs; /* # of received frames with bad FCS */ ++ u64 rx_align_errs; /* alignment errors */ ++ u64 rx_symbol_errs; /* symbol errors */ ++ u64 rx_data_errs; /* data errors */ ++ u64 rx_sequence_errs; /* sequence errors */ ++ u64 rx_runt; /* # of runt frames */ ++ u64 rx_jabber; /* # of jabber frames */ ++ u64 rx_short; /* # of short frames */ ++ u64 rx_too_long; /* # of oversized frames */ ++ u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ + +- u64 rx_frames_64; /* # of Rx frames in a particular range */ ++ u64 rx_frames_64; /* # of Rx frames in a particular range */ + u64 rx_frames_65_127; + u64 rx_frames_128_255; + u64 rx_frames_256_511; +@@ -267,7 +217,7 @@ + u64 rx_frames_1024_1518; + u64 rx_frames_1519_max; + +- u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ ++ u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ + + unsigned long tx_fifo_parity_err; + unsigned long rx_fifo_parity_err; +@@ -280,6 +230,7 @@ + unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ + unsigned long num_resets; /* # times reset due to stuck TX */ + ++ unsigned long link_faults; /* # detected link faults */ + }; + + struct tp_mib_stats { +@@ -327,41 +278,43 @@ + }; + + struct tp_params { +- unsigned int nchan; /* # of channels */ +- unsigned int pmrx_size; /* total PMRX capacity */ +- unsigned int pmtx_size; /* total PMTX capacity */ +- unsigned int cm_size; /* total CM capacity */ +- unsigned int chan_rx_size; /* per channel Rx size */ +- unsigned int chan_tx_size; /* per channel Tx size */ +- unsigned int rx_pg_size; /* Rx page size */ +- unsigned int tx_pg_size; /* Tx page size */ +- unsigned int rx_num_pgs; /* # of Rx pages */ +- unsigned int tx_num_pgs; /* # of Tx pages */ +- unsigned int ntimer_qs; /* # of timer queues */ ++ unsigned int nchan; /* # of channels */ ++ unsigned int pmrx_size; /* total PMRX capacity */ ++ unsigned int pmtx_size; /* total PMTX capacity */ ++ unsigned int cm_size; /* total CM capacity */ ++ unsigned int chan_rx_size; /* per channel Rx size */ ++ unsigned int chan_tx_size; /* per channel Tx size */ ++ unsigned int rx_pg_size; /* Rx page size */ ++ unsigned int tx_pg_size; /* Tx page size */ ++ unsigned int rx_num_pgs; /* # of Rx pages */ ++ unsigned int tx_num_pgs; /* # of Tx pages */ ++ unsigned int ntimer_qs; /* # of timer queues */ ++ unsigned int tre; /* log2 of core clocks per TP tick */ ++ unsigned int dack_re; /* DACK timer resolution */ + }; + +-struct qset_params { /* SGE queue set parameters */ +- unsigned int polling; /* polling/interrupt service for rspq */ +- unsigned int lro; /* large receive offload */ +- unsigned int coalesce_usecs; /* irq coalescing timer */ +- unsigned int rspq_size; /* # of entries in response queue */ +- unsigned int fl_size; /* # of entries in regular free list */ +- unsigned int jumbo_size; /* # of entries in jumbo free list */ +- unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ +- unsigned int cong_thres; /* FL congestion threshold */ +- unsigned int vector; /* Interrupt (line or vector) number */ ++struct qset_params { /* SGE queue set parameters */ ++ unsigned int polling; /* polling/interrupt service for rspq */ ++ unsigned int lro; /* large receive offload */ ++ unsigned int coalesce_usecs; /* irq coalescing timer */ ++ unsigned int rspq_size; /* # of entries in response queue */ ++ unsigned int fl_size; /* # of entries in regular free list */ ++ unsigned int jumbo_size; /* # of entries in jumbo free list */ ++ unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ ++ unsigned int cong_thres; /* FL congestion threshold */ ++ unsigned int vector; /* Interrupt (line or vector) number */ + }; + + struct sge_params { +- unsigned int max_pkt_size; /* max offload pkt size */ ++ unsigned int max_pkt_size; /* max offload pkt size */ + struct qset_params qset[SGE_QSETS]; + }; + + struct mc5_params { +- unsigned int mode; /* selects MC5 width */ +- unsigned int nservers; /* size of server region */ +- unsigned int nfilters; /* size of filter region */ +- unsigned int nroutes; /* size of routing region */ ++ unsigned int mode; /* selects MC5 width */ ++ unsigned int nservers; /* size of server region */ ++ unsigned int nfilters; /* size of filter region */ ++ unsigned int nroutes; /* size of routing region */ + }; + + /* Default MC5 region sizes */ +@@ -373,7 +326,7 @@ + /* MC5 modes, these must be non-0 */ + enum { + MC5_MODE_144_BIT = 1, +- MC5_MODE_72_BIT = 2 ++ MC5_MODE_72_BIT = 2 + }; + + /* MC5 min active region size */ +@@ -386,17 +339,26 @@ + unsigned int mdc; + unsigned int mem_timing; + u8 sn[SERNUM_LEN + 1]; ++ u8 ec[ECNUM_LEN + 1]; + u8 eth_base[6]; + u8 port_type[MAX_NPORTS]; + unsigned short xauicfg[2]; + }; + ++struct generic_vpd { ++ u32 offset; ++ u32 len; ++ u8 *data; ++}; ++ ++enum { MAX_VPD_BYTES = 32000 }; ++ + struct pci_params { +- unsigned int vpd_cap_addr; +- unsigned int pcie_cap_addr; ++ unsigned int vpd_cap_addr; ++ unsigned int pcie_cap_addr; + unsigned short speed; +- unsigned char width; +- unsigned char variant; ++ unsigned char width; ++ unsigned char variant; + }; + + enum { +@@ -410,21 +372,23 @@ + struct adapter_params { + struct sge_params sge; + struct mc5_params mc5; +- struct tp_params tp; ++ struct tp_params tp; + struct vpd_params vpd; + struct pci_params pci; + + const struct adapter_info *info; + ++#ifdef CONFIG_CHELSIO_T3_CORE + unsigned short mtus[NMTUS]; + unsigned short a_wnd[NCCTRL_WIN]; + unsigned short b_wnd[NCCTRL_WIN]; +- +- unsigned int nports; /* # of ethernet ports */ +- unsigned int stats_update_period; /* MAC stats accumulation period */ +- unsigned int linkpoll_period; /* link poll period in 0.1s */ +- unsigned int rev; /* chip revision */ +- unsigned int offload; ++#endif ++ unsigned int nports; /* # of ethernet ports */ ++ unsigned int chan_map; /* bitmap of in-use Tx channels */ ++ unsigned int stats_update_period; /* MAC stats accumulation period */ ++ unsigned int linkpoll_period; /* link poll period in 0.1s */ ++ unsigned int rev; /* chip revision */ ++ unsigned int offload; + }; + + enum { /* chip revisions */ +@@ -447,28 +411,28 @@ + u32 vlan_mask:12; + u32 intf:4; + u32 intf_mask:4; +- u8 proto; +- u8 proto_mask; ++ u8 proto; ++ u8 proto_mask; + }; + + struct link_config { +- unsigned int supported; /* link capabilities */ +- unsigned int advertising; /* advertised capabilities */ +- unsigned short requested_speed; /* speed user has requested */ +- unsigned short speed; /* actual link speed */ +- unsigned char requested_duplex; /* duplex user has requested */ +- unsigned char duplex; /* actual link duplex */ +- unsigned char requested_fc; /* flow control user has requested */ +- unsigned char fc; /* actual link flow control */ +- unsigned char autoneg; /* autonegotiating? */ +- unsigned int link_ok; /* link up? */ ++ unsigned int supported; /* link capabilities */ ++ unsigned int advertising; /* advertised capabilities */ ++ unsigned short requested_speed; /* speed user has requested */ ++ unsigned short speed; /* actual link speed */ ++ unsigned char requested_duplex; /* duplex user has requested */ ++ unsigned char duplex; /* actual link duplex */ ++ unsigned char requested_fc; /* flow control user has requested */ ++ unsigned char fc; /* actual link flow control */ ++ unsigned char autoneg; /* autonegotiating? */ ++ unsigned int link_ok; /* link up? */ + }; + + #define SPEED_INVALID 0xffff + #define DUPLEX_INVALID 0xff + + struct mc5 { +- struct adapter *adapter; ++ adapter_t *adapter; + unsigned int tcam_size; + unsigned char part_type; + unsigned char parity_enabled; +@@ -482,12 +446,12 @@ + } + + struct mc7 { +- struct adapter *adapter; /* backpointer to adapter */ +- unsigned int size; /* memory size in bytes */ +- unsigned int width; /* MC7 interface width */ +- unsigned int offset; /* register address offset for MC7 instance */ +- const char *name; /* name of MC7 instance */ +- struct mc7_stats stats; /* MC7 statistics */ ++ adapter_t *adapter; /* backpointer to adapter */ ++ unsigned int size; /* memory size in bytes */ ++ unsigned int width; /* MC7 interface width */ ++ unsigned int offset; /* register address offset for MC7 instance */ ++ const char *name; /* name of MC7 instance */ ++ struct mc7_stats stats; /* MC7 statistics */ + }; + + static inline unsigned int t3_mc7_size(const struct mc7 *p) +@@ -496,9 +460,12 @@ + } + + struct cmac { +- struct adapter *adapter; ++ adapter_t *adapter; + unsigned int offset; +- unsigned int nucast; /* # of address filters for unicast MACs */ ++ unsigned char nucast; /* # of address filters for unicast MACs */ ++ unsigned char multiport; /* multiple ports connected to this MAC */ ++ unsigned char ext_port; /* external MAC port */ ++ unsigned char promisc_map; /* which external ports are promiscuous */ + unsigned int tx_tcnt; + unsigned int tx_xcnt; + u64 tx_mcnt; +@@ -514,28 +481,28 @@ + enum { + MAC_DIRECTION_RX = 1, + MAC_DIRECTION_TX = 2, +- MAC_RXFIFO_SIZE = 32768 ++ MAC_RXFIFO_SIZE = 32768 + }; + + /* IEEE 802.3 specified MDIO devices */ + enum { + MDIO_DEV_PMA_PMD = 1, +- MDIO_DEV_WIS = 2, +- MDIO_DEV_PCS = 3, +- MDIO_DEV_XGXS = 4, +- MDIO_DEV_ANEG = 7, +- MDIO_DEV_VEND1 = 30, +- MDIO_DEV_VEND2 = 31 ++ MDIO_DEV_WIS = 2, ++ MDIO_DEV_PCS = 3, ++ MDIO_DEV_XGXS = 4, ++ MDIO_DEV_ANEG = 7, ++ MDIO_DEV_VEND1 = 30, ++ MDIO_DEV_VEND2 = 31 + }; + + /* LASI control and status registers */ + enum { + RX_ALARM_CTRL = 0x9000, + TX_ALARM_CTRL = 0x9001, +- LASI_CTRL = 0x9002, ++ LASI_CTRL = 0x9002, + RX_ALARM_STAT = 0x9003, + TX_ALARM_STAT = 0x9004, +- LASI_STAT = 0x9005 ++ LASI_STAT = 0x9005 + }; + + /* PHY loopback direction */ +@@ -584,17 +551,18 @@ + + /* A PHY instance */ + struct cphy { +- u8 addr; /* PHY address */ +- u8 modtype; /* PHY module type */ +- short priv; /* scratch pad */ +- unsigned int caps; /* PHY capabilities */ +- struct adapter *adapter; /* associated adapter */ +- const char *desc; /* PHY description */ +- unsigned long fifo_errors; /* FIFO over/under-flows */ +- const struct cphy_ops *ops; /* PHY operations */ +- int (*mdio_read)(struct adapter *adapter, int phy_addr, int mmd_addr, ++ u8 addr; /* PHY address */ ++ u8 modtype; /* PHY module type */ ++ unsigned int priv; /* scratch pad */ ++ unsigned int caps; /* PHY capabilities */ ++ adapter_t *adapter; /* associated adapter */ ++ pinfo_t *pinfo; /* associated port */ ++ const char *desc; /* PHY description */ ++ unsigned long fifo_errors; /* FIFO over/under-flows */ ++ const struct cphy_ops *ops; /* PHY operations */ ++ int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, + int reg_addr, unsigned int *val); +- int (*mdio_write)(struct adapter *adapter, int phy_addr, int mmd_addr, ++ int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr, + int reg_addr, unsigned int val); + }; + +@@ -612,24 +580,28 @@ + } + + /* Convenience initializer */ +-static inline void cphy_init(struct cphy *phy, struct adapter *adapter, ++static inline void cphy_init(struct cphy *phy, adapter_t *adapter, pinfo_t *pinfo, + int phy_addr, struct cphy_ops *phy_ops, +- const struct mdio_ops *mdio_ops, +- unsigned int caps, const char *desc) ++ const struct mdio_ops *mdio_ops, unsigned int caps, ++ const char *desc) + { +- phy->addr = phy_addr; +- phy->caps = caps; ++ phy->addr = (u8)phy_addr; ++ phy->caps = caps; + phy->adapter = adapter; +- phy->desc = desc; +- phy->ops = phy_ops; ++ phy->pinfo = pinfo; ++ phy->desc = desc; ++ phy->ops = phy_ops; + if (mdio_ops) { +- phy->mdio_read = mdio_ops->read; ++ phy->mdio_read = mdio_ops->read; + phy->mdio_write = mdio_ops->write; + } + } + + /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ + #define MAC_STATS_ACCUM_SECS 180 ++ ++/* The external MAC needs accumulation every 30 seconds */ ++#define VSC_STATS_ACCUM_SECS 30 + + #define XGM_REG(reg_addr, idx) \ + ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) +@@ -650,43 +622,54 @@ + + #define adapter_info(adap) ((adap)->params.info) + +-static inline int uses_xaui(const struct adapter *adap) ++static inline int uses_xaui(const adapter_t *adap) + { + return adapter_info(adap)->caps & SUPPORTED_AUI; + } + +-static inline int is_10G(const struct adapter *adap) ++static inline int is_10G(const adapter_t *adap) + { + return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; + } + +-static inline int is_offload(const struct adapter *adap) ++static inline int is_offload(const adapter_t *adap) + { ++#if defined(CONFIG_CHELSIO_T3_CORE) + return adap->params.offload; ++#else ++ return 0; ++#endif + } + +-static inline unsigned int core_ticks_per_usec(const struct adapter *adap) ++static inline unsigned int core_ticks_per_usec(const adapter_t *adap) + { + return adap->params.vpd.cclk / 1000; + } + +-static inline unsigned int is_pcie(const struct adapter *adap) ++static inline unsigned int dack_ticks_to_usec(const adapter_t *adap, ++ unsigned int ticks) ++{ ++ return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); ++} ++ ++static inline unsigned int is_pcie(const adapter_t *adap) + { + return adap->params.pci.variant == PCI_VARIANT_PCIE; + } + +-void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, +- u32 val); +-void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p, +- int n, unsigned int offset); +-int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, +- int polarity, int attempts, int delay, u32 *valp); +-static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask, ++void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val); ++void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, ++ unsigned int offset); ++int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, ++ int attempts, int delay, u32 *valp); ++ ++static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask, + int polarity, int attempts, int delay) + { + return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, + delay, NULL); + } ++ + int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, + unsigned int set); + int t3_phy_reset(struct cphy *phy, int mmd, int wait); +@@ -698,121 +681,171 @@ + int t3_phy_lasi_intr_clear(struct cphy *phy); + int t3_phy_lasi_intr_handler(struct cphy *phy); + +-void t3_intr_enable(struct adapter *adapter); +-void t3_intr_disable(struct adapter *adapter); +-void t3_intr_clear(struct adapter *adapter); +-void t3_port_intr_enable(struct adapter *adapter, int idx); +-void t3_port_intr_disable(struct adapter *adapter, int idx); +-void t3_port_intr_clear(struct adapter *adapter, int idx); +-int t3_slow_intr_handler(struct adapter *adapter); +-int t3_phy_intr_handler(struct adapter *adapter); ++void t3_intr_enable(adapter_t *adapter); ++void t3_intr_disable(adapter_t *adapter); ++void t3_intr_clear(adapter_t *adapter); ++void t3_xgm_intr_enable(adapter_t *adapter, int idx); ++void t3_xgm_intr_disable(adapter_t *adapter, int idx); ++void t3_port_intr_enable(adapter_t *adapter, int idx); ++void t3_port_intr_disable(adapter_t *adapter, int idx); ++void t3_port_intr_clear(adapter_t *adapter, int idx); ++int t3_slow_intr_handler(adapter_t *adapter); ++int t3_phy_intr_handler(adapter_t *adapter); + +-void t3_link_changed(struct adapter *adapter, int port_id); ++void t3_link_changed(adapter_t *adapter, int port_id); ++void t3_link_fault(adapter_t *adapter, int port_id); + int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); + const struct adapter_info *t3_get_adapter_info(unsigned int board_id); +-int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data); +-int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data); +-int t3_seeprom_wp(struct adapter *adapter, int enable); +-int t3_get_tp_version(struct adapter *adapter, u32 *vers); +-int t3_check_tpsram_version(struct adapter *adapter, int *must_load); +-int t3_check_tpsram(struct adapter *adapter, const u8 *tp_ram, +- unsigned int size); +-int t3_set_proto_sram(struct adapter *adap, const u8 *data); +-int t3_read_flash(struct adapter *adapter, unsigned int addr, +- unsigned int nwords, u32 *data, int byte_oriented); +-int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size); +-int t3_get_fw_version(struct adapter *adapter, u32 *vers); +-int t3_check_fw_version(struct adapter *adapter, int *must_load); +-int t3_init_hw(struct adapter *adapter, u32 fw_params); +-void mac_prep(struct cmac *mac, struct adapter *adapter, int index); +-void early_hw_init(struct adapter *adapter, const struct adapter_info *ai); +-int t3_reset_adapter(struct adapter *adapter); +-int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai, +- int reset); +-int t3_replay_prep_adapter(struct adapter *adapter); +-void t3_led_ready(struct adapter *adapter); +-void t3_fatal_err(struct adapter *adapter); +-void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on); +-void t3_config_rss(struct adapter *adapter, unsigned int rss_config, +- const u8 * cpus, const u16 *rspq); +-int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map); +-int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); +-int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr, +- unsigned int n, unsigned int *valp); ++int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data); ++int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data); ++int t3_seeprom_wp(adapter_t *adapter, int enable); ++int t3_get_vpd_len(adapter_t *adapter, struct generic_vpd *vpd); ++int t3_read_vpd(adapter_t *adapter, struct generic_vpd *vpd); ++int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, ++ u32 *data, int byte_oriented); ++int t3_get_tp_version(adapter_t *adapter, u32 *vers); ++int t3_check_tpsram_version(adapter_t *adapter); ++int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size); ++int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size); ++int t3_get_fw_version(adapter_t *adapter, u32 *vers); ++int t3_check_fw_version(adapter_t *adapter); ++int t3_load_boot(adapter_t *adapter, const u8 *fw_data, unsigned int size); ++int t3_init_hw(adapter_t *adapter, u32 fw_params); ++void mac_prep(struct cmac *mac, adapter_t *adapter, int index); ++void early_hw_init(adapter_t *adapter, const struct adapter_info *ai); ++int t3_reset_adapter(adapter_t *adapter); ++int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset); ++int t3_reinit_adapter(adapter_t *adap); ++void t3_led_ready(adapter_t *adapter); ++void t3_fatal_err(adapter_t *adapter); ++void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on); ++void t3_enable_filters(adapter_t *adap); ++void t3_disable_filters(adapter_t *adap); ++void t3_tp_set_offload_mode(adapter_t *adap, int enable); ++void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, ++ const u16 *rspq); ++int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map); ++int t3_set_proto_sram(adapter_t *adap, const u8 *data); ++int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask); ++void t3_port_failover(adapter_t *adapter, int port); ++void t3_failover_done(adapter_t *adapter, int port); ++void t3_failover_clear(adapter_t *adapter); ++int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n, ++ unsigned int *valp); + int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, + u64 *buf); + + int t3_mac_reset(struct cmac *mac); + void t3b_pcs_reset(struct cmac *mac); ++void t3_mac_disable_exact_filters(struct cmac *mac); ++void t3_mac_enable_exact_filters(struct cmac *mac); + int t3_mac_enable(struct cmac *mac, int which); + int t3_mac_disable(struct cmac *mac, int which); + int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); + int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); + int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); +-int t3_mac_set_num_ucast(struct cmac *mac, int n); ++int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n); + const struct mac_stats *t3_mac_update_stats(struct cmac *mac); +-int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc); ++int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, ++ int fc); + int t3b2_mac_watchdog_task(struct cmac *mac); + +-void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode); ++void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode); + int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, + unsigned int nroutes); + void t3_mc5_intr_handler(struct mc5 *mc5); + int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, + u32 *buf); + +-int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh); +-void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size); +-void t3_tp_set_offload_mode(struct adapter *adap, int enable); +-void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps); +-void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS], ++#ifdef CONFIG_CHELSIO_T3_CORE ++int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh); ++void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size); ++void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps); ++void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS], + unsigned short alpha[NCCTRL_WIN], + unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); +-void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS]); +-void t3_get_cong_cntl_tab(struct adapter *adap, ++void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]); ++void t3_get_cong_cntl_tab(adapter_t *adap, + unsigned short incr[NMTUS][NCCTRL_WIN]); +-void t3_config_trace_filter(struct adapter *adapter, +- const struct trace_params *tp, int filter_index, +- int invert, int enable); +-int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched); ++void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, ++ int filter_index, int invert, int enable); ++void t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp, ++ int filter_index, int *inverted, int *enabled); ++int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched); ++int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg); ++void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps, ++ unsigned int *ipg); ++void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]); ++void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals, ++ unsigned int start, unsigned int n); ++#endif + +-void t3_sge_prep(struct adapter *adap, struct sge_params *p); +-void t3_sge_init(struct adapter *adap, struct sge_params *p); +-int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable, ++int t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index, ++ u32 *size, void *data); ++int t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data); ++ ++void t3_sge_prep(adapter_t *adap, struct sge_params *p); ++void t3_sge_init(adapter_t *adap, struct sge_params *p); ++int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, + enum sge_context_type type, int respq, u64 base_addr, + unsigned int size, unsigned int token, int gen, + unsigned int cidx); +-int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id, +- int gts_enable, u64 base_addr, unsigned int size, +- unsigned int esize, unsigned int cong_thres, int gen, +- unsigned int cidx); +-int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id, +- int irq_vec_idx, u64 base_addr, unsigned int size, ++int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, ++ u64 base_addr, unsigned int size, unsigned int esize, ++ unsigned int cong_thres, int gen, unsigned int cidx); ++int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, ++ u64 base_addr, unsigned int size, + unsigned int fl_thres, int gen, unsigned int cidx); +-int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr, +- unsigned int size, int rspq, int ovfl_mode, ++int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, ++ unsigned int size, int rspq, int ovfl_mode, + unsigned int credits, unsigned int credit_thres); +-int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable); +-int t3_sge_disable_fl(struct adapter *adapter, unsigned int id); +-int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id); +-int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id); +-int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4]); +-int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4]); +-int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4]); +-int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4]); +-int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op, ++int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable); ++int t3_sge_disable_fl(adapter_t *adapter, unsigned int id); ++int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id); ++int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id); ++int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]); ++int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]); ++int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]); ++int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]); ++int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, + unsigned int credits); + +-int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter, +- int phy_addr, const struct mdio_ops *mdio_ops); +-int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter, +- int phy_addr, const struct mdio_ops *mdio_ops); +-int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter, +- int phy_addr, const struct mdio_ops *mdio_ops); +-int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter, +- int phy_addr, const struct mdio_ops *mdio_ops); +-int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr, ++int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n); ++int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n); ++int t3_vsc7323_init(adapter_t *adap, int nports); ++int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port); ++int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port); ++int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port); ++int t3_vsc7323_enable(adapter_t *adap, int port, int which); ++int t3_vsc7323_disable(adapter_t *adap, int port, int which); ++const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac); ++ ++int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, ++ unsigned int *valp); ++int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, ++ unsigned int val); ++ ++int t3_mv88e1xxx_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops); ++int t3_vsc8211_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops); ++int t3_vsc8211_fifo_depth(adapter_t *adap, unsigned int mtu, int port); ++int t3_ael1002_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops); ++int t3_ael1006_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops); ++int t3_ael2005_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops); ++int t3_ael2020_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops); ++int t3_qt2045_phy_prep(pinfo_t *pinfo, int phy_addr, + const struct mdio_ops *mdio_ops); +-int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter, +- int phy_addr, const struct mdio_ops *mdio_ops); +-#endif /* __CHELSIO_COMMON_H */ ++int t3_tn1010_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops); ++int t3_xaui_direct_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops); ++int t3_aq100x_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops); ++ ++int is_demo_bt(adapter_t *adap); ++#endif /* __CHELSIO_COMMON_H */ +diff -r c6413c34aa41 drivers/net/cxgb3/cxgb3_compat.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cxgb3/cxgb3_compat.h Tue Oct 06 09:37:59 2009 +0100 +@@ -0,0 +1,641 @@ ++/* ++ * This file is part of the Chelsio T3 Ethernet driver. ++ * ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. ++ */ ++#ifndef __CXGB3_COMPAT_H ++#define __CXGB3_COMPAT_H ++ ++#include ++#include "common.h" ++#include ++ ++/* XXX Verify OS version */ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13) && \ ++ LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,5) ++ ++#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,5) ++ ++struct msix_entry { ++ u16 vector; /* kernel uses to write allocated vector */ ++ u16 entry; /* driver uses to specify entry, OS writes */ ++}; ++ ++static inline void pci_disable_msi(struct pci_dev *dev) ++{} ++ ++static inline int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, ++ int nvec) ++{ ++ return -1; ++} ++ ++static inline void pci_disable_msix(struct pci_dev* dev) ++{} ++ ++static inline struct mii_ioctl_data *if_mii(struct ifreq *rq) ++ ++{ ++ return (struct mii_ioctl_data *) &rq->ifr_ifru; ++} ++ ++#define _spin_trylock spin_trylock ++ ++#endif /* KERNEL_VERSION(2.6.5) */ ++ ++#ifndef ATOMIC_ADD_RETURN ++#if defined(CONFIG_X86_64) ++static __inline__ int atomic_add_return(int i, atomic_t *v) ++{ ++ int __i = i; ++ __asm__ __volatile__( ++ LOCK "xaddl %0, %1;" ++ :"=r"(i) ++ :"m"(v->counter), "0"(i)); ++ return i + __i; ++} ++ ++#elif defined(CONFIG_X86) ++static __inline__ int atomic_add_return(int i, atomic_t *v) ++{ ++ int __i; ++#ifdef CONFIG_M386 ++ if(unlikely(boot_cpu_data.x86==3)) ++ goto no_xadd; ++#endif ++ /* Modern 486+ processor */ ++ __i = i; ++ __asm__ __volatile__( ++ LOCK "xaddl %0, %1;" ++ :"=r"(i) ++ :"m"(v->counter), "0"(i)); ++ return i + __i; ++ ++#ifdef CONFIG_M386 ++no_xadd: /* Legacy 386 processor */ ++ local_irq_disable(); ++ __i = atomic_read(v); ++ atomic_set(v, i + __i); ++ local_irq_enable(); ++ return i + __i; ++#endif ++} ++ ++#elif defined(CONFIG_IA64) ++#define atomic_add_return(i,v) \ ++({ \ ++ int __ia64_aar_i = (i); \ ++ (__builtin_constant_p(i) \ ++ && ( (__ia64_aar_i == 1) || (__ia64_aar_i == 4) \ ++ || (__ia64_aar_i == 8) || (__ia64_aar_i == 16) \ ++ || (__ia64_aar_i == -1) || (__ia64_aar_i == -4) \ ++ || (__ia64_aar_i == -8) || (__ia64_aar_i == -16))) \ ++ ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \ ++ : ia64_atomic_add(__ia64_aar_i, v); \ ++}) ++ ++#elif defined(CONFIG_PPC64) ++static __inline__ int atomic_add_return(int a, atomic_t *v) ++{ ++ int t; ++ ++ __asm__ __volatile__( ++ EIEIO_ON_SMP ++"1: lwarx %0,0,%2 # atomic_add_return\n\ ++ add %0,%1,%0\n\ ++ stwcx. %0,0,%2\n\ ++ bne- 1b" ++ ISYNC_ON_SMP ++ : "=&r" (t) ++ : "r" (a), "r" (&v->counter) ++ : "cc", "memory"); ++ ++ return t; ++} ++ ++#elif defined(CONFIG_PPC) ++static __inline__ int atomic_add_return(int a, atomic_t *v) ++{ ++ int t; ++ ++ __asm__ __volatile__( ++"1: lwarx %0,0,%2 # atomic_add_return\n\ ++ add %0,%1,%0\n" ++ PPC405_ERR77(0,%2) ++" stwcx. %0,0,%2 \n\ ++ bne- 1b" ++ SMP_ISYNC ++ : "=&r" (t) ++ : "r" (a), "r" (&v->counter) ++ : "cc", "memory"); ++ ++ return t; ++} ++#endif ++#endif /* ATOMIC_ADD_RETURN */ ++ ++#ifndef SPIN_TRYLOCK_IRQSAVE ++#define spin_trylock_irqsave(lock, flags) \ ++({ \ ++ local_irq_save(flags); \ ++ _spin_trylock(lock) ? \ ++ 1 : ({ local_irq_restore(flags); 0; }); \ ++}) ++#endif ++ ++ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,11) ++static inline int t3_os_pci_save_state(struct adapter *adapter) ++{ ++ return pci_save_state(adapter->pdev, adapter->t3_config_space); ++} ++ ++static inline int t3_os_pci_restore_state(struct adapter *adapter) ++{ ++ return pci_restore_state(adapter->pdev, adapter->t3_config_space); ++} ++ ++static ++inline void cancel_rearming_delayed_workqueue(struct workqueue_struct *wq, ++ struct work_struct *work) ++{ ++ while (!cancel_delayed_work(work)) ++ flush_workqueue(wq); ++} ++ ++#else ++static inline int t3_os_pci_save_state(adapter_t *adapter) ++{ ++ return pci_save_state(adapter->pdev); ++} ++ ++static inline int t3_os_pci_restore_state(adapter_t *adapter) ++{ ++ return pci_restore_state(adapter->pdev); ++} ++#endif ++ ++static inline int __netif_rx_schedule_prep(struct net_device *dev) ++{ ++ return !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state); ++} ++ ++#ifndef CONFIG_DEBUG_FS ++#include ++/* Adapted from debugfs.h */ ++static inline struct dentry *debugfs_create_dir(const char *name, ++ struct dentry *parent) ++{ ++ return ERR_PTR(-ENODEV); ++} ++ ++static inline void debugfs_remove(struct dentry *dentry) ++{} ++#else ++#include ++#endif ++ ++static inline void setup_timer(struct timer_list * timer, ++ void (*function)(unsigned long), ++ unsigned long data) ++{ ++ timer->function = function; ++ timer->data = data; ++ init_timer(timer); ++} ++ ++#define DEFINE_MUTEX DECLARE_MUTEX ++#define mutex_lock down ++#define mutex_unlock up ++ ++#undef DEFINE_RWLOCK /* broken RH4u3 definition, rw_lock_t does not exist */ ++#define DEFINE_RWLOCK(x) rwlock_t x = RW_LOCK_UNLOCKED ++ ++#define gfp_t unsigned ++ ++/* 2.6.14 and above */ ++#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) ++#include ++ ++static inline int t3_os_pci_save_state(adapter_t *adapter) ++{ ++ return pci_save_state(adapter->pdev); ++} ++ ++static inline int t3_os_pci_restore_state(adapter_t *adapter) ++{ ++ return pci_restore_state(adapter->pdev); ++} ++ ++#endif /* LINUX_VERSION_CODE */ ++ ++#if !defined(NETEVENT) ++struct notifier_block; ++ ++static inline void register_netevent_notifier(struct notifier_block *nb) ++{} ++ ++static inline void unregister_netevent_notifier(struct notifier_block *nb) ++{} ++ ++#if defined(CONFIG_TCP_OFFLOAD_MODULE) && defined(CONFIG_X86) ++#define OFLD_USE_KPROBES ++#endif ++ ++#else ++extern int netdev_nit; ++#endif ++ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ++ ++typedef irqreturn_t (*intr_handler_t)(int, void *, struct pt_regs *); ++#define DECLARE_INTR_HANDLER(handler, irq, cookie, regs) \ ++ static irqreturn_t handler(int irq, void *cookie, struct pt_regs *regs) ++ ++intr_handler_t t3_intr_handler(struct adapter *adap, int polling); ++static inline void t3_poll_handler(struct adapter *adapter, ++ struct sge_qset *qs) ++{ ++ t3_intr_handler(adapter, qs->rspq.polling) (0, ++ (adapter->flags & USING_MSIX) ? (void *)qs : (void *)adapter, ++ NULL); ++} ++ ++#define CHECKSUM_PARTIAL CHECKSUM_HW ++#define CHECKSUM_COMPLETE CHECKSUM_HW ++ ++#ifndef I_PRIVATE ++#define i_private u.generic_ip ++#endif ++ ++#else /* 2.6.19 */ ++typedef irqreturn_t (*intr_handler_t)(int, void *); ++#define DECLARE_INTR_HANDLER(handler, irq, cookie, regs) \ ++ static irqreturn_t handler(int irq, void *cookie) ++ ++intr_handler_t t3_intr_handler(struct adapter *adap, int polling); ++static inline void t3_poll_handler(struct adapter *adapter, ++ struct sge_qset *qs) ++{ ++ t3_intr_handler(adapter, qs->rspq.polling) (0, ++ (adapter->flags & USING_MSIX) ? (void *)qs : (void *)adapter); ++} ++ ++#endif /* 2.6.19 */ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++#define DECLARE_TASK_FUNC(task, task_param) \ ++ static void task(void *task_param) ++ ++#define WORK2ADAP(task_param, task) task_param ++#define DELWORK2ADAP(task_param, task) task_param ++#define WORK2T3CDATA(task_param, task) task_param ++ ++#define delayed_work work_struct ++ ++#define T3_INIT_WORK INIT_WORK ++#define T3_INIT_DELAYED_WORK INIT_WORK ++ ++#else /* 2.6.20 */ ++ ++#define DECLARE_TASK_FUNC(task, task_param) \ ++ static void task(struct work_struct *task_param) ++ ++#define WORK2ADAP(task_param, task) \ ++ container_of(task_param, struct adapter, task) ++ ++#define DELWORK2ADAP(task_param, task) \ ++ container_of(task_param, struct adapter, task.work) ++ ++#define WORK2T3CDATA(task_param, task) \ ++ container_of(task_param, struct t3c_data, task) ++ ++#define T3_INIT_WORK(task_handler, task, adapter) \ ++ INIT_WORK(task_handler, task) ++ ++#define T3_INIT_DELAYED_WORK(task_handler, task, adapter) \ ++ INIT_DELAYED_WORK(task_handler, task) ++ ++#endif /* 2.6.20 */ ++ ++#if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE) ++#include ++#else ++struct firmware { ++ size_t size; ++ u8 *data; ++}; ++ ++struct device; ++ ++static inline int request_firmware(const struct firmware **firmware_p, ++ char *name, ++ struct device *device) ++{ ++ printk(KERN_WARNING ++ "FW_LOADER not set in this kernel. FW upgrade aborted.\n"); ++ return -1; ++} ++ ++static inline void release_firmware(const struct firmware *fw) ++{} ++#endif /* FW_LOADER */ ++ ++#if !defined(RTNL_TRYLOCK) ++#include ++static inline int rtnl_trylock(void) ++{ ++ return !rtnl_shlock_nowait(); ++} ++#endif /* RTNL_TRYLOCK */ ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ++#ifndef KZALLOC ++static inline void *kzalloc(size_t size, int flags) ++{ ++ void *ret = kmalloc(size, flags); ++ if (ret) ++ memset(ret, 0, size); ++ return ret; ++} ++#endif /* KZALLOC */ ++#endif ++ ++#ifndef GSO_SIZE ++#define gso_size tso_size ++#endif /* GSO_SIZE */ ++ ++#ifndef NIPQUAD_FMT ++#define NIPQUAD_FMT "%u.%u.%u.%u" ++#endif ++ ++/* sysfs compatibility */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) ++ ++#define to_net_dev(class) container_of(class, struct net_device, class_dev) ++ ++#define cxgb3_compat_device class_device ++ ++#define CXGB3_SHOW_FUNC(func, d, attr, buf) \ ++ static ssize_t func(struct cxgb3_compat_device *d, \ ++ char *buf) \ ++ ++#define CXGB3_STORE_FUNC(func, d, attr, buf, len) \ ++ static ssize_t func(struct cxgb3_compat_device *d, \ ++ const char *buf, \ ++ size_t len) ++ ++#ifndef __ATTR ++#define __ATTR(_name,_mode,_show,_store) { \ ++ .attr = {.name = __stringify(_name), .mode = _mode, .owner = THIS_MODULE }, \ ++ .show = _show, \ ++ .store = _store, \ ++} ++#endif ++ ++#define CXGB3_DEVICE_ATTR(_name,_mode,_show,_store) \ ++struct class_device_attribute dev_attr_##_name = \ ++ __ATTR(_name,_mode,_show,_store) ++ ++#ifndef LINUX_2_4 ++static inline struct kobject *net2kobj(struct net_device *dev) ++{ ++ return &dev->class_dev.kobj; ++} ++#endif ++ ++#else /* sysfs compatibility */ ++ ++#define cxgb3_compat_device device ++ ++#define CXGB3_SHOW_FUNC(func, d, attr, buf) \ ++ static ssize_t func(struct cxgb3_compat_device *d, \ ++ struct device_attribute *attr, \ ++ char *buf) \ ++ ++#define CXGB3_STORE_FUNC(func, d, attr, buf, len) \ ++ static ssize_t func(struct cxgb3_compat_device *d, \ ++ struct device_attribute *attr, \ ++ const char *buf, \ ++ size_t len) ++ ++#define CXGB3_DEVICE_ATTR DEVICE_ATTR ++ ++static inline struct kobject *net2kobj(struct net_device *dev) ++{ ++ return &dev->dev.kobj; ++} ++ ++#endif /* sysfs compatibility */ ++ ++#if !defined(IRQF) ++#define IRQF_SHARED SA_SHIRQ ++#endif /* IRQF */ ++ ++#if !defined(VLANGRP) ++#include ++static inline struct net_device *vlan_group_get_device(struct vlan_group *vg, ++ int vlan_id) ++{ ++ return vg->vlan_devices[vlan_id]; ++} ++#endif /* VLANGRP */ ++ ++#if !defined(for_each_netdev) ++#define for_each_netdev(d) \ ++ for (d = dev_base; d; d = d->next) ++#endif ++ ++#include ++ ++#if !defined(NEW_SKB_COPY) ++static inline void skb_copy_from_linear_data(const struct sk_buff *skb, ++ void *to, ++ const unsigned int len) ++{ ++ memcpy(to, skb->data, len); ++} ++ ++static inline void skb_copy_from_linear_data_offset(const struct sk_buff *skb, ++ const int offset, void *to, ++ const unsigned int len) ++{ ++ memcpy(to, skb->data + offset, len); ++} ++ ++static inline void skb_copy_to_linear_data(struct sk_buff *skb, ++ const void *from, ++ const unsigned int len) ++{ ++ memcpy(skb->data, from, len); ++} ++ ++static inline void skb_copy_to_linear_data_offset(struct sk_buff *skb, ++ const int offset, ++ const void *from, ++ const unsigned int len) ++{ ++ memcpy(skb->data + offset, from, len); ++} ++ ++#endif ++ ++#if defined(NEW_SKB_OFFSET) ++static inline void cxgb3_set_skb_header(struct sk_buff *skb, ++ struct iphdr *ip_hdr, ++ int offset) ++{ ++ skb_set_network_header(skb, offset); ++} ++ ++#else /* NEW_SKB_OFFSET */ ++static inline int skb_network_offset(struct sk_buff *skb) ++{ ++ return skb->nh.raw - skb->data; ++} ++ ++static inline unsigned char *skb_transport_header(const struct sk_buff *skb) ++{ ++ return skb->h.raw; ++} ++ ++#if !defined(T3_SKB_TRANSPORT_OFFSET) ++static inline int skb_transport_offset(const struct sk_buff *skb) ++{ ++ return skb->h.raw - skb->data; ++} ++#endif ++ ++#if !defined(T3_IP_HDR) ++static inline struct iphdr *ip_hdr(const struct sk_buff *skb) ++{ ++ return skb->nh.iph; ++} ++#endif ++ ++#if !defined(T3_TCP_HDR) ++static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb) ++{ ++ return skb->h.th; ++} ++#endif ++ ++static inline void skb_reset_mac_header(struct sk_buff *skb) ++{ ++ skb->mac.raw = skb->data; ++} ++ ++static inline void skb_reset_network_header(struct sk_buff *skb) ++{ ++ skb->nh.raw = skb->data; ++} ++ ++static inline void skb_reset_transport_header(struct sk_buff *skb) ++{ ++ skb->h.raw = skb->data; ++} ++ ++static inline void cxgb3_set_skb_header(struct sk_buff *skb, ++ struct iphdr *ip_hdr, ++ int offset) ++{ ++ skb->nh.iph = ip_hdr; ++} ++ ++#endif /* NEW_SKB_OFFSET */ ++ ++#if !defined(ARP_HDR) ++static inline struct arphdr *arp_hdr(const struct sk_buff *skb) ++{ ++ return (struct arphdr *)skb->nh.arph; ++} ++#endif /* !ARP_HDR */ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++#if defined(ETHTOOL_GPERMADDR) ++#define CXGB3_ETHTOOL_GPERMADDR ETHTOOL_GPERMADDR ++#endif ++#endif ++ ++#if !defined(TRANSPORT_HEADER) ++#define transport_header h.raw ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) ++#define SET_MODULE_OWNER(module) ++#define INET_PROC_DIR init_net.proc_net ++#else ++#define INET_PROC_DIR proc_net ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ++#define SET_PROC_NODE_OWNER(_p, _owner) \ ++ do { (_p)->owner = (_owner); } while (0) ++#else ++#define SET_PROC_NODE_OWNER(_p, _owner) \ ++ do { } while (0) ++#endif ++ ++#if defined(NAPI_UPDATE) ++#define SGE_GET_OFLD_QS(napi, dev) \ ++ container_of(napi, struct sge_qset, napi) ++ ++#define DECLARE_OFLD_POLL(napi, dev, budget) \ ++ static int ofld_poll(struct napi_struct *napi, int budget) ++ ++#define DECLARE_NAPI_RX_HANDLER(napi, dev, budget) \ ++ static int napi_rx_handler(struct napi_struct *napi, int budget) ++ ++#else ++#define SGE_GET_OFLD_QS(napi, dev) \ ++ ((struct port_info *)netdev_priv(dev))->qs ++ ++#define DECLARE_OFLD_POLL(napi, dev, budget) \ ++ static int ofld_poll(struct net_device *dev, int *budget) ++ ++#define DECLARE_NAPI_RX_HANDLER(napi, dev, budget) \ ++ static int napi_rx_handler(struct net_device *dev, int *budget) ++ ++#endif /* NAPI_UPDATE */ ++ ++ ++#if !defined(VLAN_DEV_API) ++#include ++#if defined(VLAN_DEV_INFO) ++static inline struct vlan_dev_info *vlan_dev_info(const struct net_device *dev) ++{ ++ return VLAN_DEV_INFO(dev); ++} ++#endif ++ ++static inline u16 vlan_dev_vlan_id(const struct net_device *dev) ++{ ++ return vlan_dev_info(dev)->vlan_id; ++} ++ ++static inline struct net_device *vlan_dev_real_dev(const struct net_device *dev) ++{ ++ return vlan_dev_info(dev)->real_dev; ++} ++#endif /* VLAN_DEV_API */ ++ ++#if defined(PDEV_MAPPING) ++static inline int t3_pci_dma_mapping_error(struct pci_dev *pdev, ++ dma_addr_t dma_addr) ++{ ++ return pci_dma_mapping_error(pdev, dma_addr); ++} ++#else ++static inline int t3_pci_dma_mapping_error(struct pci_dev *pdev, ++ dma_addr_t dma_addr) ++{ ++ return pci_dma_mapping_error(dma_addr); ++} ++#endif ++#endif +diff -r c6413c34aa41 drivers/net/cxgb3/cxgb3_ctl_defs.h +--- a/drivers/net/cxgb3/cxgb3_ctl_defs.h Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/cxgb3_ctl_defs.h Tue Oct 06 09:37:59 2009 +0100 +@@ -1,39 +1,19 @@ + /* +- * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved. ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: +- * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ ++ + #ifndef _CXGB3_OFFLOAD_CTL_DEFS_H + #define _CXGB3_OFFLOAD_CTL_DEFS_H + ++#include ++ + enum { +- GET_MAX_OUTSTANDING_WR = 0, ++ GET_MAX_OUTSTANDING_WR = 0, + GET_TX_MAX_CHUNK = 1, + GET_TID_RANGE = 2, + GET_STID_RANGE = 3, +@@ -56,26 +36,41 @@ + RDMA_GET_MEM = 18, + RDMA_GET_MIB = 19, + ++ FAILOVER = 30, ++ FAILOVER_DONE = 31, ++ FAILOVER_CLEAR = 32, ++ FAILOVER_ACTIVE_SLAVE = 33, ++ FAILOVER_PORT_DOWN = 34, ++ FAILOVER_PORT_UP = 35, ++ FAILOVER_PORT_RELEASE = 36, ++ ++ GET_CPUIDX_OF_QSET = 40, ++ GET_PORT_SCHED = 41, ++ GET_PORT_ARRAY = 42, ++ GET_NUM_QUEUES = 43, ++ + GET_RX_PAGE_INFO = 50, + + GET_ISCSI_IPV4ADDR = 51, + SET_ISCSI_IPV4ADDR = 52, ++ ++ GET_EMBEDDED_INFO = 70, + }; + + /* + * Structure used to describe a TID range. Valid TIDs are [base, base+num). + */ + struct tid_range { +- unsigned int base; /* first TID */ +- unsigned int num; /* number of TIDs in range */ ++ unsigned int base; /* first TID */ ++ unsigned int num; /* number of TIDs in range */ + }; + + /* + * Structure used to request the size and contents of the MTU table. + */ + struct mtutab { +- unsigned int size; /* # of entries in the MTU table */ +- const unsigned short *mtus; /* the MTU table values */ ++ unsigned int size; /* # of entries in the MTU table */ ++ const unsigned short *mtus; /* the MTU table values */ + }; + + struct net_device; +@@ -84,15 +79,21 @@ + * Structure used to request the adapter net_device owning a given MAC address. + */ + struct iff_mac { +- struct net_device *dev; /* the net_device */ +- const unsigned char *mac_addr; /* MAC address to lookup */ ++ struct net_device *dev; /* the net_device */ ++ const unsigned char *mac_addr; /* MAC address to lookup */ + u16 vlan_tag; ++}; ++ ++/* Structure used to request a port's offload scheduler */ ++struct port_sched { ++ struct net_device *dev; /* the net_device */ ++ int sched; /* associated scheduler */ + }; + + /* Structure used to request a port's iSCSI IPv4 address */ + struct iscsi_ipv4addr { +- struct net_device *dev; /* the net_device */ +- __be32 ipv4addr; /* the return iSCSI IPv4 address */ ++ struct net_device *dev; /* the net_device */ ++ __be32 ipv4addr; /* the returned iSCSI IPv4 address */ + }; + + struct pci_dev; +@@ -101,45 +102,64 @@ + * Structure used to request the TCP DDP parameters. + */ + struct ddp_params { +- unsigned int llimit; /* TDDP region start address */ +- unsigned int ulimit; /* TDDP region end address */ +- unsigned int tag_mask; /* TDDP tag mask */ ++ unsigned int llimit; /* TDDP region start address */ ++ unsigned int ulimit; /* TDDP region end address */ ++ unsigned int tag_mask; /* TDDP tag mask */ + struct pci_dev *pdev; + }; + + struct adap_ports { +- unsigned int nports; /* number of ports on this adapter */ +- struct net_device *lldevs[2]; ++ unsigned int nports; /* number of ports on this adapter */ ++ struct net_device *lldevs[4]; /* Max number of ports is 4 */ ++}; ++ ++struct port_array { ++ unsigned int nports; /* number of ports on this adapter */ ++ struct net_device **lldevs; /* points to array of net_devices */ ++}; ++ ++struct bond_ports { ++ unsigned int port; ++ unsigned int nports; /* number of ports on this adapter */ ++ unsigned int ports[4]; /* Max number of ports is 4 */ + }; + + /* + * Structure used to return information to the iscsi layer. + */ + struct ulp_iscsi_info { +- unsigned int offset; +- unsigned int llimit; +- unsigned int ulimit; +- unsigned int tagmask; +- u8 pgsz_factor[4]; +- unsigned int max_rxsz; +- unsigned int max_txsz; +- struct pci_dev *pdev; ++ unsigned int offset; ++ unsigned int llimit; ++ unsigned int ulimit; ++ unsigned int tagmask; ++ u8 pgsz_factor[4]; ++ unsigned int max_rxsz; ++ unsigned int max_txsz; ++ struct pci_dev *pdev; ++}; ++ ++/* ++ * Offload TX/RX page information. ++ */ ++struct ofld_page_info { ++ unsigned int page_size; /* Page size, should be a power of 2 */ ++ unsigned int num; /* Number of pages */ + }; + + /* + * Structure used to return information to the RDMA layer. + */ + struct rdma_info { +- unsigned int tpt_base; /* TPT base address */ +- unsigned int tpt_top; /* TPT last entry address */ +- unsigned int pbl_base; /* PBL base address */ +- unsigned int pbl_top; /* PBL last entry address */ +- unsigned int rqt_base; /* RQT base address */ +- unsigned int rqt_top; /* RQT last entry address */ +- unsigned int udbell_len; /* user doorbell region length */ +- unsigned long udbell_physbase; /* user doorbell physical start addr */ +- void __iomem *kdb_addr; /* kernel doorbell register address */ +- struct pci_dev *pdev; /* associated PCI device */ ++ unsigned int tpt_base; /* TPT base address */ ++ unsigned int tpt_top; /* TPT last entry address */ ++ unsigned int pbl_base; /* PBL base address */ ++ unsigned int pbl_top; /* PBL last entry address */ ++ unsigned int rqt_base; /* RQT base address */ ++ unsigned int rqt_top; /* RQT last entry address */ ++ unsigned int udbell_len; /* user doorbell region length */ ++ unsigned long udbell_physbase; /* user doorbell physical start addr */ ++ void __iomem *kdb_addr; /* kernel doorbell register address */ ++ struct pci_dev *pdev; /* associated PCI device */ + }; + + /* +@@ -172,10 +192,10 @@ + }; + + /* +- * Offload TX/RX page information. ++ * Structure used to get firmware and protocol engine versions. + */ +-struct ofld_page_info { +- unsigned int page_size; /* Page size, should be a power of 2 */ +- unsigned int num; /* Number of pages */ ++struct ch_embedded_info { ++ u32 fw_vers; ++ u32 tp_vers; + }; +-#endif /* _CXGB3_OFFLOAD_CTL_DEFS_H */ ++#endif /* _CXGB3_OFFLOAD_CTL_DEFS_H */ +diff -r c6413c34aa41 drivers/net/cxgb3/cxgb3_defs.h +--- a/drivers/net/cxgb3/cxgb3_defs.h Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/cxgb3_defs.h Tue Oct 06 09:37:59 2009 +0100 +@@ -1,33 +1,11 @@ + /* +- * Copyright (c) 2006-2007 Chelsio, Inc. All rights reserved. ++ * Copyright (c) 2005-2009 Chelsio, Inc. All rights reserved. ++ * Copyright (c) 2005-2009 Open Grid Computing, Inc. All rights reserved. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: +- * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ + #ifndef _CHELSIO_DEFS_H + #define _CHELSIO_DEFS_H +@@ -45,6 +23,11 @@ + void cxgb_free_mem(void *addr); + void cxgb_neigh_update(struct neighbour *neigh); + void cxgb_redirect(struct dst_entry *old, struct dst_entry *new); ++#ifndef LINUX_2_4 ++int req_set_offload_policy(struct net_device *, ++ const struct ofld_policy_file *, ++ size_t); ++#endif + + /* + * Map an ATID or STID to their entries in the corresponding TID tables. +@@ -54,6 +37,7 @@ + { + return &t->atid_tab[atid - t->atid_base]; + } ++ + + static inline union listen_entry *stid2entry(const struct tid_info *t, + unsigned int stid) +@@ -68,7 +52,7 @@ + unsigned int tid) + { + struct t3c_tid_entry *t3c_tid = tid < t->ntids ? +- &(t->tid_tab[tid]) : NULL; ++ &(t->tid_tab[tid]) : NULL; + + return (t3c_tid && t3c_tid->client) ? t3c_tid : NULL; + } +diff -r c6413c34aa41 drivers/net/cxgb3/cxgb3_ioctl.h +--- a/drivers/net/cxgb3/cxgb3_ioctl.h Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/cxgb3_ioctl.h Tue Oct 06 09:37:59 2009 +0100 +@@ -1,54 +1,69 @@ + /* +- * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved. ++ * This file is part of the Chelsio T3 Ethernet driver for Linux. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. + * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ ++ + #ifndef __CHIOCTL_H__ + #define __CHIOCTL_H__ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif + + /* + * Ioctl commands specific to this driver. + */ + enum { ++ CHELSIO_SETREG = 1024, ++ CHELSIO_GETREG = 1025, ++ CHELSIO_SETTPI = 1026, ++ CHELSIO_GETTPI = 1027, ++ CHELSIO_DEVUP = 1028, + CHELSIO_GETMTUTAB = 1029, + CHELSIO_SETMTUTAB = 1030, ++ CHELSIO_GETMTU = 1031, + CHELSIO_SET_PM = 1032, + CHELSIO_GET_PM = 1033, ++ CHELSIO_GET_TCAM = 1034, ++ CHELSIO_SET_TCAM = 1035, ++ CHELSIO_GET_TCB = 1036, ++ CHELSIO_READ_TCAM_WORD = 1037, + CHELSIO_GET_MEM = 1038, ++ CHELSIO_GET_SGE_CONTEXT = 1039, ++ CHELSIO_GET_SGE_DESC = 1040, + CHELSIO_LOAD_FW = 1041, ++ CHELSIO_GET_PROTO = 1042, ++ CHELSIO_SET_PROTO = 1043, + CHELSIO_SET_TRACE_FILTER = 1044, + CHELSIO_SET_QSET_PARAMS = 1045, + CHELSIO_GET_QSET_PARAMS = 1046, + CHELSIO_SET_QSET_NUM = 1047, + CHELSIO_GET_QSET_NUM = 1048, ++ CHELSIO_SET_PKTSCHED = 1049, ++ CHELSIO_SET_HW_SCHED = 1051, ++ CHELSIO_LOAD_BOOT = 1054, ++ CHELSIO_CLEAR_STATS = 1055, ++ CHELSIO_GET_UP_LA = 1056, ++ CHELSIO_GET_UP_IOQS = 1057, ++ CHELSIO_GET_TRACE_FILTER = 1058, ++ ++ CHELSIO_SET_FILTER = 1060, ++ CHELSIO_DEL_FILTER = 1061, ++ CHELSIO_SET_OFLD_POLICY = 1062, + }; + ++/* statistics categories */ ++enum { ++ STATS_PORT = 1 << 1, ++ STATS_QUEUE = 1 << 2, ++}; ++ + struct ch_reg { + uint32_t cmd; + uint32_t addr; +@@ -70,7 +85,7 @@ + uint32_t queue_num; + uint32_t idx; + uint32_t size; +- uint8_t data[128]; ++ uint8_t data[128]; + }; + + struct ch_mem_range { +@@ -79,30 +94,66 @@ + uint32_t addr; + uint32_t len; + uint32_t version; +- uint8_t buf[0]; ++ uint8_t buf[0]; + }; ++ ++enum { MEM_CM, MEM_PMRX, MEM_PMTX }; /* ch_mem_range.mem_id values */ + + struct ch_qset_params { + uint32_t cmd; + uint32_t qset_idx; +- int32_t txq_size[3]; +- int32_t rspq_size; +- int32_t fl_size[2]; +- int32_t intr_lat; +- int32_t polling; +- int32_t lro; +- int32_t cong_thres; ++ int32_t txq_size[3]; ++ int32_t rspq_size; ++ int32_t fl_size[2]; ++ int32_t intr_lat; ++ int32_t polling; ++ int32_t lro; ++ int32_t cong_thres; + int32_t vector; + int32_t qnum; + }; + + struct ch_pktsched_params { + uint32_t cmd; +- uint8_t sched; +- uint8_t idx; +- uint8_t min; +- uint8_t max; +- uint8_t binding; ++ uint8_t sched; ++ uint8_t idx; ++ uint8_t min; ++ uint8_t max; ++ uint8_t binding; ++}; ++ ++struct ch_hw_sched { ++ uint32_t cmd; ++ uint8_t sched; ++ int8_t mode; ++ int8_t channel; ++ int32_t kbps; /* rate in Kbps */ ++ int32_t class_ipg; /* tenths of nanoseconds */ ++ int32_t flow_ipg; /* usec */ ++}; ++ ++struct ch_filter_tuple { ++ uint32_t sip; ++ uint32_t dip; ++ uint16_t sport; ++ uint16_t dport; ++ uint16_t vlan:12; ++ uint16_t vlan_prio:3; ++}; ++ ++struct ch_filter { ++ uint32_t cmd; ++ uint32_t filter_id; ++ struct ch_filter_tuple val; ++ struct ch_filter_tuple mask; ++ uint16_t mac_addr_idx; ++ uint8_t mac_hit:1; ++ uint8_t proto:2; ++ ++ uint8_t want_filter_id:1; /* report filter TID instead of RSS hash */ ++ uint8_t pass:1; /* whether to pass or drop packets */ ++ uint8_t rss:1; /* use RSS or specified qset */ ++ uint8_t qset; + }; + + #ifndef TCB_SIZE +@@ -111,8 +162,6 @@ + + /* TCB size in 32-bit words */ + #define TCB_WORDS (TCB_SIZE / 4) +- +-enum { MEM_CM, MEM_PMRX, MEM_PMTX }; /* ch_mem_range.mem_id values */ + + struct ch_mtus { + uint32_t cmd; +@@ -163,13 +212,31 @@ + uint32_t vlan_mask:12; + uint32_t intf:4; + uint32_t intf_mask:4; +- uint8_t proto; +- uint8_t proto_mask; +- uint8_t invert_match:1; +- uint8_t config_tx:1; +- uint8_t config_rx:1; +- uint8_t trace_tx:1; +- uint8_t trace_rx:1; ++ uint8_t proto; ++ uint8_t proto_mask; ++ uint8_t invert_match:1; ++ uint8_t config_tx:1; ++ uint8_t config_rx:1; ++ uint8_t trace_tx:1; ++ uint8_t trace_rx:1; ++}; ++ ++struct ch_up_la { ++ uint32_t cmd; ++ uint32_t stopped; ++ uint32_t idx; ++ uint32_t bufsize; ++ u8 *data; ++}; ++ ++struct ch_up_ioqs { ++ uint32_t cmd; ++ uint32_t ioq_rx_enable; ++ uint32_t ioq_tx_enable; ++ uint32_t ioq_rx_status; ++ uint32_t ioq_tx_status; ++ uint32_t bufsize; ++ u8 *data; + }; + + #define SIOCCHIOCTL SIOCDEVPRIVATE +diff -r c6413c34aa41 drivers/net/cxgb3/cxgb3_main.c +--- a/drivers/net/cxgb3/cxgb3_main.c Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/cxgb3_main.c Tue Oct 06 09:37:59 2009 +0100 +@@ -1,39 +1,24 @@ + /* +- * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved. +- * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: +- * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- */ ++ * This file is part of the Chelsio T3 Ethernet driver for Linux. ++ * ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. ++ */ ++ + #include ++#ifndef LINUX_2_4 + #include ++#endif /* LINUX_2_4 */ + #include + #include ++#ifndef LINUX_2_4 + #include ++#endif /* LINUX_2_4 */ ++#include + #include + #include + #include +@@ -41,10 +26,10 @@ + #include + #include + #include ++#include + #include +-#include +-#include +-#include ++#include ++#include + #include + + #include "common.h" +@@ -53,21 +38,52 @@ + #include "cxgb3_offload.h" + #include "version.h" + ++#include "cxgb3_defs.h" + #include "cxgb3_ctl_defs.h" + #include "t3_cpl.h" + #include "firmware_exports.h" + + enum { +- MAX_TXQ_ENTRIES = 16384, ++ MAX_TXQ_ENTRIES = 16384, + MAX_CTRL_TXQ_ENTRIES = 1024, +- MAX_RSPQ_ENTRIES = 16384, +- MAX_RX_BUFFERS = 16384, ++ MAX_RSPQ_ENTRIES = 16384, ++ MAX_RX_BUFFERS = 16384, + MAX_RX_JUMBO_BUFFERS = 16384, +- MIN_TXQ_ENTRIES = 4, ++ MIN_TXQ_ENTRIES = 4, + MIN_CTRL_TXQ_ENTRIES = 4, +- MIN_RSPQ_ENTRIES = 32, +- MIN_FL_ENTRIES = 32 +-}; ++ MIN_RSPQ_ENTRIES = 32, ++ MIN_FL_ENTRIES = 32, ++ MIN_FL_JUMBO_ENTRIES = 32 ++}; ++ ++/* ++ * Local host copy of filter information. This is used to program the ++ * hardware filters. In general, non-zero fields indicate that the associated ++ * packet element should be compared for a match with the value. ++ */ ++struct filter_info { ++ u32 sip; /* Source IP address */ ++ u32 sip_mask; /* Source IP mask */ ++ u32 dip; /* Destination IP address */ ++ u16 sport; /* Source port */ ++ u16 dport; /* Desination port */ ++ u32 vlan:12; /* VLAN ID */ ++ u32 vlan_prio:3; /* VLAN Priority: FILTER_NO_VLAN_PRI => none */ ++ u32 mac_hit:1; /* Match MAC address at MAC Index */ ++ u32 mac_idx:4; /* Index of Exact MAC Address entry */ ++ /* (Port ID << 3) | MAC Index */ ++ u32 mac_vld:1; /* Port ID and MAC Index are valid */ ++ u32 pkt_type:2; /* Packet type: */ ++ /* {0..3} => {Any, TCP, UDP, IP Fragment} */ ++ u32 report_filter_id:1; /* Report filter ID in CPL Response Message */ ++ u32 pass:1; /* Pass packet: 0 => drop, 1 => pass */ ++ u32 rss:1; /* Use RSS: 0 => use Qset, 1 => RSS */ ++ u32 qset:3; /* Qset to which packet should be appended */ ++ u32 locked:1; /* filter used by software; unavailable to user */ ++ u32 valid:1; /* filter is valid */ ++}; ++ ++enum { FILTER_NO_VLAN_PRI = 7 }; + + #define PORT_MASK ((1 << MAX_NPORTS) - 1) + +@@ -78,25 +94,35 @@ + #define EEPROM_MAGIC 0x38E2F10C + + #define CH_DEVICE(devid, idx) \ +- { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, PCI_ANY_ID, 0, 0, idx } +- +-static const struct pci_device_id cxgb3_pci_tbl[] = { +- CH_DEVICE(0x20, 0), /* PE9000 */ +- CH_DEVICE(0x21, 1), /* T302E */ +- CH_DEVICE(0x22, 2), /* T310E */ +- CH_DEVICE(0x23, 3), /* T320X */ +- CH_DEVICE(0x24, 1), /* T302X */ +- CH_DEVICE(0x25, 3), /* T320E */ +- CH_DEVICE(0x26, 2), /* T310X */ +- CH_DEVICE(0x30, 2), /* T3B10 */ +- CH_DEVICE(0x31, 3), /* T3B20 */ +- CH_DEVICE(0x32, 1), /* T3B02 */ +- {0,} ++ { \ ++ .vendor = PCI_VENDOR_ID_CHELSIO, \ ++ .device = (devid), \ ++ .subvendor = PCI_ANY_ID, \ ++ .subdevice = PCI_ANY_ID, \ ++ .driver_data = (idx) \ ++ } ++ ++static struct pci_device_id cxgb3_pci_tbl[] = { ++ CH_DEVICE(0x20, 0), /* PE9000 */ ++ CH_DEVICE(0x21, 1), /* T302E */ ++ CH_DEVICE(0x22, 2), /* T310E */ ++ CH_DEVICE(0x23, 3), /* T320X */ ++ CH_DEVICE(0x24, 1), /* T302X */ ++ CH_DEVICE(0x25, 3), /* T320E */ ++ CH_DEVICE(0x26, 2), /* T310X */ ++ CH_DEVICE(0x30, 2), /* T3B10 */ ++ CH_DEVICE(0x31, 3), /* T3B20 */ ++ CH_DEVICE(0x32, 1), /* T3B02 */ ++ CH_DEVICE(0x33, 4), /* T3B04 */ ++ CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */ ++ CH_DEVICE(0x36, 3), /* S320E-CR */ ++ CH_DEVICE(0x37, 7), /* N320E-G2 */ ++ { 0, } + }; + + MODULE_DESCRIPTION(DRV_DESC); + MODULE_AUTHOR("Chelsio Communications"); +-MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_LICENSE("GPL"); + MODULE_VERSION(DRV_VERSION); + MODULE_DEVICE_TABLE(pci, cxgb3_pci_tbl); + +@@ -104,6 +130,7 @@ + + module_param(dflt_msg_enable, int, 0644); + MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T3 default message enable bitmap"); ++ + + /* + * The driver uses the best interrupt scheme available on a platform in the +@@ -117,7 +144,7 @@ + static int msi = 2; + + module_param(msi, int, 0644); +-MODULE_PARM_DESC(msi, "whether to use MSI or MSI-X"); ++MODULE_PARM_DESC(msi, "whether to use MSI-X (2), MSI (1) or Legacy INTx (0)"); + + /* + * The driver enables offload as a default. +@@ -128,6 +155,16 @@ + + module_param(ofld_disable, int, 0644); + MODULE_PARM_DESC(ofld_disable, "whether to enable offload at init time or not"); ++ ++/* ++ * The driver uses an auto-queue algorithm by default. ++ * To disable it and force a single queue-set per port, use singleq = 1. ++ */ ++ ++static int singleq = 0; ++ ++module_param(singleq, int, 0644); ++MODULE_PARM_DESC(singleq, "use a single queue-set per port"); + + /* + * We have work elements that we need to cancel when an interface is taken +@@ -137,11 +174,19 @@ + * will block keventd as it needs the rtnl lock, and we'll deadlock waiting + * for our work to complete. Get our own work queue to solve this. + */ ++#ifdef LINUX_2_4 ++struct workqueue_struct *cxgb3_wq; ++#else + static struct workqueue_struct *cxgb3_wq; ++#endif /* LINUX_2_4 */ ++ ++#ifndef LINUX_2_4 ++static struct dentry *cxgb3_debugfs_root; ++#endif /* LINUX_2_4 */ + + /** + * link_report - show link status and link speed/duplex +- * @p: the port whose settings are to be reported ++ * @dev: the port whose settings are to be reported + * + * Shows the link status, speed, and duplex of a port. + */ +@@ -150,6 +195,8 @@ + if (!netif_carrier_ok(dev)) + printk(KERN_INFO "%s: link down\n", dev->name); + else { ++ static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; ++ + const char *s = "10Mbps"; + const struct port_info *p = netdev_priv(dev); + +@@ -165,15 +212,79 @@ + break; + } + +- printk(KERN_INFO "%s: link up, %s, %s-duplex\n", dev->name, s, +- p->link_config.duplex == DUPLEX_FULL ? "full" : "half"); +- } +-} +- ++ printk(KERN_INFO "%s: link up, %s, %s-duplex, %s PAUSE\n", ++ dev->name, s, ++ p->link_config.duplex == DUPLEX_FULL ? "full" : "half", ++ fc[p->link_config.fc]); ++ } ++} ++ ++static void enable_tx_fifo_drain(struct adapter *adapter, ++ struct port_info *pi) ++{ ++ t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, 0, ++ F_ENDROPPKT); ++ t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, 0); ++ t3_write_reg(adapter, A_XGM_TX_CTRL + pi->mac.offset, F_TXEN); ++ t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, F_RXEN); ++} ++ ++static void disable_tx_fifo_drain(struct adapter *adapter, ++ struct port_info *pi) ++{ ++ t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, ++ F_ENDROPPKT, 0); ++} ++ ++void t3_os_link_fault(struct adapter *adap, int port_id, int state) ++{ ++ struct net_device *dev = adap->port[port_id]; ++ struct port_info *pi = netdev_priv(dev); ++ ++ if (state == netif_carrier_ok(dev)) ++ return; ++ ++ if (state) { ++ netif_carrier_on(dev); ++ if (adap->params.nports <= 2) { ++ struct cmac *mac = &pi->mac; ++ ++ disable_tx_fifo_drain(adap, pi); ++ ++ /* Clear local faults */ ++ t3_xgm_intr_disable(adap, pi->port_id); ++ t3_read_reg(adap, A_XGM_INT_STATUS + ++ pi->mac.offset); ++ t3_write_reg(adap, ++ A_XGM_INT_CAUSE + pi->mac.offset, ++ F_XGM_INT); ++ ++ t3_set_reg_field(adap, ++ A_XGM_INT_ENABLE + ++ pi->mac.offset, ++ F_XGM_INT, F_XGM_INT); ++ t3_xgm_intr_enable(adap, pi->port_id); ++ t3_mac_enable(mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); ++ /* Clear errors created by MAC enable */ ++ t3_set_reg_field(adap, ++ A_XGM_STAT_CTRL + pi->mac.offset, ++ F_CLRSTATS, 1); ++ ++ } ++ } else { ++ netif_carrier_off(dev); ++ ++ /* Flush Tx FIFO */ ++ enable_tx_fifo_drain(adap, pi); ++ } ++ ++ link_report(dev); ++} ++ + /** + * t3_os_link_changed - handle link status changes + * @adapter: the adapter associated with the link change +- * @port_id: the port index whose limk status has changed ++ * @port_id: the port index whose link status has changed + * @link_stat: the new status of the link + * @speed: the new speed setting + * @duplex: the new duplex setting +@@ -196,15 +307,59 @@ + + if (link_stat != netif_carrier_ok(dev)) { + if (link_stat) { +- t3_mac_enable(mac, MAC_DIRECTION_RX); ++ msleep(10); ++ ++ disable_tx_fifo_drain(adapter, pi); ++ ++ t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); ++ /* Clear errors created by MAC enable */ ++ t3_set_reg_field(adapter, ++ A_XGM_STAT_CTRL + pi->mac.offset, ++ F_CLRSTATS, 1); ++ ++ if (adapter->params.nports > 2) { ++ pi->max_ofld_bw = speed * 940; ++ t3_config_sched(adapter, ++ pi->max_ofld_bw, port_id); ++ } ++ if (adapter->params.nports <= 2) { ++ /* Clear local faults */ ++ t3_xgm_intr_disable(adapter, pi->port_id); ++ t3_read_reg(adapter, A_XGM_INT_STATUS + ++ pi->mac.offset); ++ t3_write_reg(adapter, ++ A_XGM_INT_CAUSE + pi->mac.offset, ++ F_XGM_INT); ++ ++ t3_set_reg_field(adapter, ++ A_XGM_INT_ENABLE + ++ pi->mac.offset, ++ F_XGM_INT, F_XGM_INT); ++ t3_xgm_intr_enable(adapter, pi->port_id); ++ } + netif_carrier_on(dev); + } else { +- netif_carrier_off(dev); +- pi->phy.ops->power_down(&pi->phy, 1); ++ t3_xgm_intr_disable(adapter, pi->port_id); ++ t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset); ++ if (adapter->params.nports <= 2) { ++ t3_set_reg_field(adapter, ++ A_XGM_INT_ENABLE + ++ pi->mac.offset, ++ F_XGM_INT, 0); ++ } ++ ++ /* PR 5666. We shouldn't power down 1G phys */ ++ if (is_10G(adapter)) ++ pi->phy.ops->power_down(&pi->phy, 1); ++ ++ t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset); + t3_mac_disable(mac, MAC_DIRECTION_RX); + t3_link_start(&pi->phy, mac, &pi->link_config); +- } +- ++ netif_carrier_off(dev); ++ ++ /* Flush Tx FIFO */ ++ enable_tx_fifo_drain(adapter, pi); ++ } + link_report(dev); + } + } +@@ -224,8 +379,8 @@ + NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown" + }; + +- const struct net_device *dev = adap->port[port_id]; +- const struct port_info *pi = netdev_priv(dev); ++ struct net_device *dev = adap->port[port_id]; ++ struct port_info *pi = netdev_priv(dev); + + if (pi->phy.modtype == phy_modtype_none) + printk(KERN_INFO "%s: PHY module unplugged\n", dev->name); +@@ -234,37 +389,56 @@ + mod_str[pi->phy.modtype]); + } + ++#ifndef LINUX_2_4 ++static ssize_t cxgb_set_nfilters(struct net_device *dev, unsigned int nfilters) ++{ ++ struct port_info *pi = netdev_priv(dev); ++ struct adapter *adap = pi->adapter; ++ int min_tids = is_offload(adap) ? MC5_MIN_TIDS : 0; ++ ++ if (adap->flags & FULL_INIT_DONE) ++ return -EBUSY; ++ if (nfilters && adap->params.rev == 0) ++ return -EINVAL; ++ if (nfilters > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers - ++ min_tids) ++ return -EINVAL; ++ adap->params.mc5.nfilters = nfilters; ++ return 0; ++} ++#endif ++ + static void cxgb_set_rxmode(struct net_device *dev) + { + struct t3_rx_mode rm; + struct port_info *pi = netdev_priv(dev); ++ struct cmac *mac = &pi->mac; + + init_rx_mode(&rm, dev, dev->mc_list); +- t3_mac_set_rx_mode(&pi->mac, &rm); ++ t3_mac_set_rx_mode(mac, &rm); ++ + } + + /** + * link_start - enable a port +- * @dev: the device to enable ++ * @dev: the port to enable + * + * Performs the MAC and PHY actions needed to enable a port. + */ + static void link_start(struct net_device *dev) + { +- struct t3_rx_mode rm; + struct port_info *pi = netdev_priv(dev); + struct cmac *mac = &pi->mac; + +- init_rx_mode(&rm, dev, dev->mc_list); +- t3_mac_reset(mac); ++ if (!mac->multiport) ++ t3_mac_reset(mac); + t3_mac_set_mtu(mac, dev->mtu); + t3_mac_set_address(mac, 0, dev->dev_addr); +- t3_mac_set_rx_mode(mac, &rm); ++ cxgb_set_rxmode(dev); + t3_link_start(&pi->phy, mac, &pi->link_config); +- t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); +-} +- +-static inline void cxgb_disable_msi(struct adapter *adapter) ++} ++ ++static void cxgb_disable_msi(struct adapter *adapter) + { + if (adapter->flags & USING_MSIX) { + pci_disable_msix(adapter->pdev); +@@ -278,7 +452,7 @@ + /* + * Interrupt handler for asynchronous events used with MSI-X. + */ +-static irqreturn_t t3_async_intr_handler(int irq, void *cookie) ++DECLARE_INTR_HANDLER(t3_async_intr_handler, irq, cookie, regs) + { + t3_slow_intr_handler(cookie); + return IRQ_HANDLED; +@@ -300,33 +474,28 @@ + + for (i = 0; i < pi->nqsets; i++, msi_idx++) { + snprintf(adap->msix_info[msi_idx].desc, n, +- "%s-%d", d->name, pi->first_qset + i); ++ "%s (queue %d)", d->name, ++ pi->first_qset + i); + adap->msix_info[msi_idx].desc[n] = 0; + } +- } +-} +- +-static int request_msix_data_irqs(struct adapter *adap) +-{ +- int i, j, err, qidx = 0; +- +- for_each_port(adap, i) { +- int nqsets = adap2pinfo(adap, i)->nqsets; +- +- for (j = 0; j < nqsets; ++j) { +- err = request_irq(adap->msix_info[qidx + 1].vec, +- t3_intr_handler(adap, +- adap->sge.qs[qidx]. +- rspq.polling), 0, +- adap->msix_info[qidx + 1].desc, +- &adap->sge.qs[qidx]); +- if (err) { +- while (--qidx >= 0) +- free_irq(adap->msix_info[qidx + 1].vec, +- &adap->sge.qs[qidx]); +- return err; +- } +- qidx++; ++ } ++} ++ ++static int request_msix_data_irqs(adapter_t *adap) ++{ ++ int err, qidx; ++ ++ for (qidx = 0; qidx < adap->sge.nqsets; ++qidx) { ++ err = request_irq(adap->msix_info[qidx + 1].vec, ++ t3_intr_handler(adap, ++ adap->sge.qs[qidx].rspq.polling), ++ 0, adap->msix_info[qidx + 1].desc, ++ &adap->sge.qs[qidx]); ++ if (err) { ++ while (--qidx >= 0) ++ free_irq(adap->msix_info[qidx + 1].vec, ++ &adap->sge.qs[qidx]); ++ return err; + } + } + return 0; +@@ -335,13 +504,10 @@ + static void free_irq_resources(struct adapter *adapter) + { + if (adapter->flags & USING_MSIX) { +- int i, n = 0; ++ int i; + + free_irq(adapter->msix_info[0].vec, adapter); +- for_each_port(adapter, i) +- n += adap2pinfo(adapter, i)->nqsets; +- +- for (i = 0; i < n; ++i) ++ for (i = 0; i < adapter->sge.nqsets; ++i) + free_irq(adapter->msix_info[i + 1].vec, + &adapter->sge.qs[i]); + } else +@@ -378,6 +544,7 @@ + memset(req, 0, sizeof(*req)); + req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); + OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i)); ++ req->mtu_idx = NMTUS - 1; + req->iff = i; + t3_mgmt_tx(adap, skb); + } +@@ -430,28 +597,87 @@ + * We always configure the RSS mapping for two ports since the mapping + * table has plenty of entries. + */ +-static void setup_rss(struct adapter *adap) +-{ +- int i; +- unsigned int nq0 = adap2pinfo(adap, 0)->nqsets; +- unsigned int nq1 = adap->port[1] ? adap2pinfo(adap, 1)->nqsets : 1; ++static void setup_rss(adapter_t *adap) ++{ ++ int i; ++ unsigned int nq[2]; + u8 cpus[SGE_QSETS + 1]; + u16 rspq_map[RSS_TABLE_SIZE]; + + for (i = 0; i < SGE_QSETS; ++i) + cpus[i] = i; +- cpus[SGE_QSETS] = 0xff; /* terminator */ ++ cpus[SGE_QSETS] = 0xff; /* terminator */ ++ ++ nq[0] = nq[1] = 0; ++ for_each_port(adap, i) { ++ const struct port_info *pi = adap2pinfo(adap, i); ++ ++ nq[pi->tx_chan] += pi->nqsets; ++ } + + for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { +- rspq_map[i] = i % nq0; +- rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq1) + nq0; +- } ++ rspq_map[i] = nq[0] ? i % nq[0] : 0; ++ rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0; ++ } ++ ++ /* Calculate the reverse RSS map table */ ++ for (i = 0; i < RSS_TABLE_SIZE; ++i) ++ if (adap->rrss_map[rspq_map[i]] == 0xff) ++ adap->rrss_map[rspq_map[i]] = i; + + t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | +- F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | +- V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, cpus, rspq_map); +-} +- ++ F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | ++ F_RRCPLMAPEN | V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, ++ cpus, rspq_map); ++} ++#if !defined(NAPI_UPDATE) ++/* ++ * If we have multiple receive queues per port serviced by NAPI we need one ++ * netdevice per queue as NAPI operates on netdevices. We already have one ++ * netdevice, namely the one associated with the interface, so we use dummy ++ * ones for any additional queues. Note that these netdevices exist purely ++ * so that NAPI has something to work with, they do not represent network ++ * ports and are not registered. ++ */ ++static int init_dummy_netdevs(struct adapter *adap) ++{ ++ int i, j, dummy_idx = 0; ++ struct net_device *nd; ++ ++ for_each_port(adap, i) { ++ struct net_device *dev = adap->port[i]; ++ const struct port_info *pi = netdev_priv(dev); ++ ++ for (j = 0; j < pi->nqsets - 1; j++) { ++ if (!adap->dummy_netdev[dummy_idx]) { ++ struct port_info *p; ++ ++ nd = alloc_netdev(sizeof(*p), "", ether_setup); ++ if (!nd) ++ goto free_all; ++ ++ p = netdev_priv(nd); ++ p->adapter = adap; ++ nd->weight = 64; ++ set_bit(__LINK_STATE_START, &nd->state); ++ adap->dummy_netdev[dummy_idx] = nd; ++ } ++ strcpy(adap->dummy_netdev[dummy_idx]->name, dev->name); ++ dummy_idx++; ++ } ++ } ++ return 0; ++ ++free_all: ++ while (--dummy_idx >= 0) { ++ free_netdev(adap->dummy_netdev[dummy_idx]); ++ adap->dummy_netdev[dummy_idx] = NULL; ++ } ++ return -ENOMEM; ++} ++#endif ++ ++#if defined(NAPI_UPDATE) + static void init_napi(struct adapter *adap) + { + int i; +@@ -469,60 +695,248 @@ + * adds each new napi_struct to a list. Be careful not to call it a + * second time, e.g., during EEH recovery, by making a note of it. + */ +- adap->flags |= NAPI_INIT; +-} ++ adap->flags |= NAPI_INIT; ++ ++} ++#endif + + /* + * Wait until all NAPI handlers are descheduled. This includes the handlers of + * both netdevices representing interfaces and the dummy ones for the extra + * queues. + */ +-static void quiesce_rx(struct adapter *adap) +-{ +- int i; +- +- for (i = 0; i < SGE_QSETS; i++) +- if (adap->sge.qs[i].adap) +- napi_disable(&adap->sge.qs[i].napi); ++static void quiesce_rx(adapter_t *adap) ++{ ++ int i; ++ ++#if defined(NAPI_UPDATE) ++ for (i = 0; i < SGE_QSETS; i++) { ++ struct sge_qset *qs = &adap->sge.qs[i]; ++ ++ if (qs->adap) ++ napi_disable(&qs->napi); ++ } ++#else ++ struct net_device *dev; ++ ++ for_each_port(adap, i) { ++ dev = adap->port[i]; ++ while (test_bit(__LINK_STATE_RX_SCHED, &dev->state)) ++ msleep(1); ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(adap->dummy_netdev); i++) { ++ dev = adap->dummy_netdev[i]; ++ if (dev) ++ while (test_bit(__LINK_STATE_RX_SCHED, &dev->state)) ++ msleep(1); ++ } ++#endif + } + + static void enable_all_napi(struct adapter *adap) + { ++#if defined(NAPI_UPDATE) + int i; + for (i = 0; i < SGE_QSETS; i++) + if (adap->sge.qs[i].adap) + napi_enable(&adap->sge.qs[i].napi); +-} +- +-/** +- * set_qset_lro - Turn a queue set's LRO capability on and off +- * @dev: the device the qset is attached to +- * @qset_idx: the queue set index +- * @val: the LRO switch +- * +- * Sets LRO on or off for a particular queue set. +- * the device's features flag is updated to reflect the LRO +- * capability when all queues belonging to the device are +- * in the same state. +- */ +-static void set_qset_lro(struct net_device *dev, int qset_idx, int val) +-{ +- struct port_info *pi = netdev_priv(dev); +- struct adapter *adapter = pi->adapter; +- int i, lro_on = 1; +- +- adapter->params.sge.qset[qset_idx].lro = !!val; +- adapter->sge.qs[qset_idx].lro_enabled = !!val; +- +- /* let ethtool report LRO on only if all queues are LRO enabled */ +- for (i = pi->first_qset; i < pi->first_qset + pi->nqsets; ++i) +- lro_on &= adapter->params.sge.qset[i].lro; +- +- if (lro_on) +- dev->features |= NETIF_F_LRO; +- else +- dev->features &= ~NETIF_F_LRO; +-} ++#endif ++} ++ ++/* ++ * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc. ++ * The allocated memory is cleared. ++ */ ++static void *alloc_mem(unsigned long size) ++{ ++ void *p = kmalloc(size, GFP_KERNEL); ++ ++ if (!p) ++ p = vmalloc(size); ++ if (p) ++ memset(p, 0, size); ++ return p; ++} ++ ++/* ++ * Free memory allocated through alloc_mem(). ++ */ ++static void free_mem(void *addr) ++{ ++ unsigned long p = (unsigned long) addr; ++ ++ if (p >= VMALLOC_START && p < VMALLOC_END) ++ vfree(addr); ++ else ++ kfree(addr); ++} ++ ++static int alloc_filters(struct adapter *adap) ++{ ++ struct filter_info *p; ++ ++ if (!adap->params.mc5.nfilters) /* no filters requested */ ++ return 0; ++ ++ adap->filters = alloc_mem(adap->params.mc5.nfilters * sizeof(*p)); ++ if (!adap->filters) ++ return -ENOMEM; ++ ++ /* Set the default filters, only need to set non-0 fields here. */ ++ p = &adap->filters[adap->params.mc5.nfilters - 1]; ++ p->vlan = 0xfff; ++ p->vlan_prio = FILTER_NO_VLAN_PRI; ++ p->pass = p->rss = p->valid = p->locked = 1; ++ ++ return 0; ++} ++ ++static void mk_set_tcb_field(struct cpl_set_tcb_field *req, unsigned int tid, ++ unsigned int word, u64 mask, u64 val) ++{ ++ OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid)); ++ req->reply = V_NO_REPLY(1); ++ req->cpu_idx = 0; ++ req->word = htons(word); ++ req->mask = cpu_to_be64(mask); ++ req->val = cpu_to_be64(val); ++} ++ ++static inline void set_tcb_field_ulp(struct cpl_set_tcb_field *req, ++ unsigned int tid, unsigned int word, ++ u64 mask, u64 val) ++{ ++ struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req; ++ ++ txpkt->cmd_dest = htonl(V_ULPTX_CMD(ULP_TXPKT)); ++ txpkt->len = htonl(V_ULPTX_NFLITS(sizeof(*req) / 8)); ++ mk_set_tcb_field(req, tid, word, mask, val); ++} ++ ++static int set_filter(struct adapter *adap, int id, const struct filter_info *f) ++{ ++ int len; ++ struct sk_buff *skb; ++ struct ulp_txpkt *txpkt; ++ struct work_request_hdr *wr; ++ struct cpl_pass_open_req *oreq; ++ struct cpl_set_tcb_field *sreq; ++ ++ len = sizeof(*wr) + sizeof(*oreq) + 2 * sizeof(*sreq); ++ id += t3_mc5_size(&adap->mc5) - adap->params.mc5.nroutes - ++ adap->params.mc5.nfilters; ++ ++ skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL); ++ ++ wr = (struct work_request_hdr *)__skb_put(skb, len); ++ wr->wr_hi = htonl(V_WR_OP(FW_WROPCODE_BYPASS) | F_WR_ATOMIC); ++ ++ oreq = (struct cpl_pass_open_req *)(wr + 1); ++ txpkt = (struct ulp_txpkt *)oreq; ++ txpkt->cmd_dest = htonl(V_ULPTX_CMD(ULP_TXPKT)); ++ txpkt->len = htonl(V_ULPTX_NFLITS(sizeof(*oreq) / 8)); ++ OPCODE_TID(oreq) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, id)); ++ oreq->local_port = htons(f->dport); ++ oreq->peer_port = htons(f->sport); ++ oreq->local_ip = htonl(f->dip); ++ oreq->peer_ip = htonl(f->sip); ++ oreq->peer_netmask = htonl(f->sip_mask); ++ oreq->opt0h = 0; ++ oreq->opt0l = htonl(F_NO_OFFLOAD); ++ oreq->opt1 = htonl(V_MAC_MATCH_VALID(f->mac_vld) | ++ V_CONN_POLICY(CPL_CONN_POLICY_FILTER) | ++ V_VLAN_PRI(f->vlan_prio >> 1) | ++ V_VLAN_PRI_VALID(f->vlan_prio != FILTER_NO_VLAN_PRI) | ++ V_PKT_TYPE(f->pkt_type) | V_OPT1_VLAN(f->vlan) | ++ V_MAC_MATCH(f->mac_idx | (f->mac_hit << 4))); ++ ++ sreq = (struct cpl_set_tcb_field *)(oreq + 1); ++ set_tcb_field_ulp(sreq, id, 1, 0x1800808000ULL, ++ (f->report_filter_id << 15) | (1 << 23) | ++ ((u64)f->pass << 35) | ((u64)!f->rss << 36)); ++ set_tcb_field_ulp(sreq + 1, id, 0, 0xffffffff, (2 << 19) | 1); ++ t3_mgmt_tx(adap, skb); ++ ++ if (f->pass && !f->rss) { ++ len = sizeof(*sreq); ++ skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL); ++ ++ sreq = (struct cpl_set_tcb_field *)__skb_put(skb, len); ++ sreq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); ++ mk_set_tcb_field(sreq, id, 25, 0x3f80000, ++ (u64)adap->rrss_map[f->qset] << 19); ++ t3_mgmt_tx(adap, skb); ++ } ++ return 0; ++} ++ ++static int setup_hw_filters(struct adapter *adap) ++{ ++ int i, err = 0; ++ ++ if (!adap->filters || ++ atomic_read(&adap->filter_toe_mode) == CXGB3_FTM_TOE) ++ return 0; ++ ++ t3_enable_filters(adap); ++ ++ for (i = err = 0; i < adap->params.mc5.nfilters && !err; i++) ++ if (adap->filters[i].locked) { ++ int ret = set_filter(adap, i, &adap->filters[i]); ++ if (ret) ++ err = ret; ++ } ++ return err; ++} ++ ++/* ++ * Atomically determine/set the filter/TOE mode exclusion switch to the ++ * desired mode and return the success state. The first time this is called ++ * the filter/TOE mode of the adapter will be set permanently to the selected ++ * mode. ++ */ ++int cxgb3_filter_toe_mode(struct adapter *adapter, int mode) ++{ ++ static spinlock_t cxgb3_filter_toe_lock = SPIN_LOCK_UNLOCKED; ++ int cur_mode; ++ ++ /* ++ * It would be much easier to do all of this if we could use ++ * atomic_cmpxchg() but that primitive isn't available on all ++ * platforms so we're essentially faking it here via a spinlock. We ++ * do an optimization here of reading the interlock without taking the ++ * spinlock and returning success/failure if the interlock has already ++ * been set. We can do this because the interlock is one-shot and ++ * once set is never changed. With this optimization, a single global ++ * spinlock is fine for protecting the critical section. ++ */ ++ cur_mode = atomic_read(&adapter->filter_toe_mode); ++ if (cur_mode != CXGB3_FTM_NONE) ++ return cur_mode == mode; ++ ++ spin_lock(&cxgb3_filter_toe_lock); ++ ++ cur_mode = atomic_read(&adapter->filter_toe_mode); ++ if (cur_mode != CXGB3_FTM_NONE) { ++ /* got changed while we were taking the lock ... */ ++ spin_unlock(&cxgb3_filter_toe_lock); ++ return cur_mode == mode; ++ } ++ ++ /* ++ * If we're successfully setting TOE mode for the adapter, disable ++ * the adapter's filter capabilities. ++ */ ++ if (mode == CXGB3_FTM_TOE) ++ t3_disable_filters(adapter); ++ ++ atomic_set(&adapter->filter_toe_mode, mode); ++ spin_unlock(&cxgb3_filter_toe_lock); ++ ++ return 1; ++} ++ + + /** + * setup_sge_qsets - configure SGE Tx/Rx/response queues +@@ -534,12 +948,13 @@ + */ + static int setup_sge_qsets(struct adapter *adap) + { +- int i, j, err, irq_idx = 0, qset_idx = 0; ++ int i, j, err, irq_idx = 0, qset_idx = 0, dummy_dev_idx; + unsigned int ntxq = SGE_TXQ_PER_SET; + + if (adap->params.rev > 0 && !(adap->flags & USING_MSI)) + irq_idx = -1; + ++ dummy_dev_idx = 0; + for_each_port(adap, i) { + struct net_device *dev = adap->port[i]; + struct port_info *pi = netdev_priv(dev); +@@ -547,13 +962,20 @@ + pi->qs = &adap->sge.qs[pi->first_qset]; + for (j = pi->first_qset; j < pi->first_qset + pi->nqsets; + ++j, ++qset_idx) { +- set_qset_lro(dev, qset_idx, pi->rx_csum_offload); ++ if (!pi->rx_csum_offload) ++ adap->params.sge.qset[qset_idx].lro = 0; + err = t3_sge_alloc_qset(adap, qset_idx, 1, + (adap->flags & USING_MSIX) ? qset_idx + 1 : + irq_idx, +- &adap->params.sge.qset[qset_idx], ntxq, dev); ++ &adap->params.sge.qset[qset_idx], ntxq, ++#if defined(NAPI_UPDATE) ++ dev); ++#else ++ j == pi->first_qset ? dev : ++ adap->dummy_netdev[dummy_dev_idx++]); ++#endif ++ + if (err) { +- t3_stop_sge_timers(adap); + t3_free_sge_resources(adap); + return err; + } +@@ -563,21 +985,22 @@ + return 0; + } + +-static ssize_t attr_show(struct device *d, char *buf, +- ssize_t(*format) (struct net_device *, char *)) ++#ifndef LINUX_2_4 ++static ssize_t attr_show(struct cxgb3_compat_device *d, char *buf, ++ ssize_t (*format)(struct net_device *, char *)) + { + ssize_t len; + + /* Synchronize with ioctls that may shut down the device */ + rtnl_lock(); +- len = (*format) (to_net_dev(d), buf); +- rtnl_unlock(); +- return len; +-} +- +-static ssize_t attr_store(struct device *d, ++ len = (*format)(to_net_dev(d), buf); ++ rtnl_unlock(); ++ return len; ++} ++ ++static ssize_t attr_store(struct cxgb3_compat_device *d, + const char *buf, size_t len, +- ssize_t(*set) (struct net_device *, unsigned int), ++ ssize_t (*set)(struct net_device *, unsigned int), + unsigned int min_val, unsigned int max_val) + { + char *endp; +@@ -592,7 +1015,7 @@ + return -EINVAL; + + rtnl_lock(); +- ret = (*set) (to_net_dev(d), val); ++ ret = (*set)(to_net_dev(d), val); + if (!ret) + ret = len; + rtnl_unlock(); +@@ -606,31 +1029,17 @@ + struct adapter *adap = pi->adapter; \ + return sprintf(buf, "%u\n", val_expr); \ + } \ +-static ssize_t show_##name(struct device *d, struct device_attribute *attr, \ +- char *buf) \ ++CXGB3_SHOW_FUNC(show_##name, d, attr, buf) \ + { \ + return attr_show(d, buf, format_##name); \ + } + + static ssize_t set_nfilters(struct net_device *dev, unsigned int val) + { +- struct port_info *pi = netdev_priv(dev); +- struct adapter *adap = pi->adapter; +- int min_tids = is_offload(adap) ? MC5_MIN_TIDS : 0; +- +- if (adap->flags & FULL_INIT_DONE) +- return -EBUSY; +- if (val && adap->params.rev == 0) +- return -EINVAL; +- if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers - +- min_tids) +- return -EINVAL; +- adap->params.mc5.nfilters = val; +- return 0; +-} +- +-static ssize_t store_nfilters(struct device *d, struct device_attribute *attr, +- const char *buf, size_t len) ++ return cxgb_set_nfilters(dev, val); ++} ++ ++CXGB3_STORE_FUNC(store_nfilters, d, attr, buf, len) + { + return attr_store(d, buf, len, set_nfilters, 0, ~0); + } +@@ -649,19 +1058,18 @@ + return 0; + } + +-static ssize_t store_nservers(struct device *d, struct device_attribute *attr, +- const char *buf, size_t len) ++CXGB3_STORE_FUNC(store_nservers, d, attr, buf, len) + { + return attr_store(d, buf, len, set_nservers, 0, ~0); + } + + #define CXGB3_ATTR_R(name, val_expr) \ + CXGB3_SHOW(name, val_expr) \ +-static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL) ++static CXGB3_DEVICE_ATTR(name, S_IRUGO, show_##name, NULL) + + #define CXGB3_ATTR_RW(name, val_expr, store_method) \ + CXGB3_SHOW(name, val_expr) \ +-static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_method) ++static CXGB3_DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_method) + + CXGB3_ATTR_R(cam_size, t3_mc5_size(&adap->mc5)); + CXGB3_ATTR_RW(nfilters, adap->params.mc5.nfilters, store_nfilters); +@@ -674,42 +1082,159 @@ + NULL + }; + +-static struct attribute_group cxgb3_attr_group = {.attrs = cxgb3_attrs }; +- +-static ssize_t tm_attr_show(struct device *d, +- char *buf, int sched) +-{ +- struct port_info *pi = netdev_priv(to_net_dev(d)); +- struct adapter *adap = pi->adapter; +- unsigned int v, addr, bpt, cpt; ++static struct attribute_group cxgb3_attr_group = { .attrs = cxgb3_attrs }; ++ ++static ssize_t reg_attr_show(struct cxgb3_compat_device *d, char *buf, int reg, ++ int shift, unsigned int mask) ++{ ++ struct port_info *pi = netdev_priv(to_net_dev(d)); ++ struct adapter *adap = pi->adapter; + ssize_t len; +- +- addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; +- rtnl_lock(); +- t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr); +- v = t3_read_reg(adap, A_TP_TM_PIO_DATA); +- if (sched & 1) +- v >>= 16; +- bpt = (v >> 8) & 0xff; +- cpt = v & 0xff; +- if (!cpt) ++ unsigned int v; ++ ++ /* Synchronize with ioctls that may shut down the device */ ++ rtnl_lock(); ++ v = t3_read_reg(adap, reg); ++ len = sprintf(buf, "%u\n", (v >> shift) & mask); ++ rtnl_unlock(); ++ return len; ++} ++ ++static ssize_t reg_attr_store(struct cxgb3_compat_device *d, const char *buf, ++ size_t len, int reg, int shift, ++ unsigned int mask, unsigned int min_val, ++ unsigned int max_val) ++{ ++ struct port_info *pi = netdev_priv(to_net_dev(d)); ++ struct adapter *adap = pi->adapter; ++ char *endp; ++ unsigned int val; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++ val = simple_strtoul(buf, &endp, 0); ++ if (endp == buf || val < min_val || val > max_val) ++ return -EINVAL; ++ ++ rtnl_lock(); ++ t3_set_reg_field(adap, reg, mask << shift, ++ val << shift); ++ rtnl_unlock(); ++ return len; ++} ++ ++#define T3_REG_SHOW(name, reg, shift, mask) \ ++CXGB3_SHOW_FUNC(show_##name, d, attr, buf) \ ++{ \ ++ return reg_attr_show(d, buf, reg, shift, mask); \ ++} ++ ++#define T3_REG_STORE(name, reg, shift, mask, min_val, max_val) \ ++CXGB3_STORE_FUNC(store_##name, d, attr, buf, len) \ ++{ \ ++ return reg_attr_store(d, buf, len, reg, shift, mask, min_val, max_val); \ ++} ++ ++#define T3_ATTR(name, reg, shift, mask, min_val, max_val) \ ++T3_REG_SHOW(name, reg, shift, mask) \ ++T3_REG_STORE(name, reg, shift, mask, min_val, max_val) \ ++static CXGB3_DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name) ++ ++T3_ATTR(tcp_retries1, A_TP_SHIFT_CNT, S_RXTSHIFTMAXR1, M_RXTSHIFTMAXR1, 3, 15); ++T3_ATTR(tcp_retries2, A_TP_SHIFT_CNT, S_RXTSHIFTMAXR2, M_RXTSHIFTMAXR2, 0, 15); ++T3_ATTR(tcp_syn_retries, A_TP_SHIFT_CNT, S_SYNSHIFTMAX, M_SYNSHIFTMAX, 0, 15); ++T3_ATTR(tcp_keepalive_probes, A_TP_SHIFT_CNT, S_KEEPALIVEMAX, M_KEEPALIVEMAX, ++ 1, 15); ++T3_ATTR(tcp_sack, A_TP_TCP_OPTIONS, S_SACKMODE, M_SACKMODE, 0, 1); ++T3_ATTR(tcp_timestamps, A_TP_TCP_OPTIONS, S_TIMESTAMPSMODE, M_TIMESTAMPSMODE, ++ 0, 1); ++ ++static ssize_t timer_attr_show(struct cxgb3_compat_device *d, char *buf, int reg) ++{ ++ struct port_info *pi = netdev_priv(to_net_dev(d)); ++ struct adapter *adap = pi->adapter; ++ unsigned int v, tps; ++ ssize_t len; ++ ++ /* Synchronize with ioctls that may shut down the device */ ++ rtnl_lock(); ++ v = t3_read_reg(adap, reg); ++ tps = (adap->params.vpd.cclk * 1000) >> adap->params.tp.tre; ++ len = sprintf(buf, "%u\n", v / tps); ++ rtnl_unlock(); ++ return len; ++} ++ ++static ssize_t timer_attr_store(struct cxgb3_compat_device *d, const char *buf, ++ size_t len, int reg, unsigned int min_val, ++ unsigned int max_val) ++{ ++ struct port_info *pi = netdev_priv(to_net_dev(d)); ++ struct adapter *adap = pi->adapter; ++ char *endp; ++ unsigned int val, tps; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++ tps = (adap->params.vpd.cclk * 1000) >> adap->params.tp.tre; ++ val = simple_strtoul(buf, &endp, 0); ++ if (endp == buf || val * tps < min_val || val * tps > max_val) ++ return -EINVAL; ++ ++ rtnl_lock(); ++ t3_write_reg(adap, reg, val * tps); ++ rtnl_unlock(); ++ return len; ++} ++ ++#define T3_TIMER_REG_SHOW(name, reg) \ ++CXGB3_SHOW_FUNC(show_##name, d, attr, buf) \ ++{ \ ++ return timer_attr_show(d, buf, reg); \ ++} ++ ++#define T3_TIMER_REG_STORE(name, reg, min_val, max_val) \ ++CXGB3_STORE_FUNC(store_##name, d, attr, buf, len) \ ++{ \ ++ return timer_attr_store(d, buf, len, reg, min_val, max_val); \ ++} ++ ++#define T3_TIMER_ATTR(name, reg, min_val, max_val) \ ++T3_TIMER_REG_SHOW(name, reg) \ ++T3_TIMER_REG_STORE(name, reg, min_val, max_val) \ ++static CXGB3_DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name) ++ ++T3_TIMER_ATTR(tcp_keepalive_time, A_TP_KEEP_IDLE, 0, M_KEEPALIVEIDLE); ++T3_TIMER_ATTR(tcp_keepalive_intvl, A_TP_KEEP_INTVL, 0, M_KEEPALIVEINTVL); ++T3_TIMER_ATTR(tcp_finwait2_timeout, A_TP_FINWAIT2_TIMER, 0, M_FINWAIT2TIME); ++ ++static ssize_t tm_attr_show(struct cxgb3_compat_device *d, char *buf, int sched) ++{ ++ struct port_info *pi = netdev_priv(to_net_dev(d)); ++ struct adapter *adap = pi->adapter; ++ ssize_t len; ++ unsigned int rate; ++ ++ rtnl_lock(); ++ t3_get_tx_sched(adap, sched, &rate, NULL); ++ if (!rate) + len = sprintf(buf, "disabled\n"); +- else { +- v = (adap->params.vpd.cclk * 1000) / cpt; +- len = sprintf(buf, "%u Kbps\n", (v * bpt) / 125); +- } +- rtnl_unlock(); +- return len; +-} +- +-static ssize_t tm_attr_store(struct device *d, +- const char *buf, size_t len, int sched) +-{ +- struct port_info *pi = netdev_priv(to_net_dev(d)); +- struct adapter *adap = pi->adapter; +- unsigned int val; ++ else ++ len = sprintf(buf, "%u Kbps\n", rate); ++ rtnl_unlock(); ++ return len; ++} ++ ++static ssize_t tm_attr_store(struct cxgb3_compat_device *d, const char *buf, ++ size_t len, int sched) ++{ ++ struct port_info *pi = netdev_priv(to_net_dev(d)); ++ struct adapter *adap = pi->adapter; + char *endp; + ssize_t ret; ++ unsigned int val; + + if (!capable(CAP_NET_ADMIN)) + return -EPERM; +@@ -727,17 +1252,15 @@ + } + + #define TM_ATTR(name, sched) \ +-static ssize_t show_##name(struct device *d, struct device_attribute *attr, \ +- char *buf) \ ++CXGB3_SHOW_FUNC(show_##name, d, attr, buf) \ + { \ + return tm_attr_show(d, buf, sched); \ + } \ +-static ssize_t store_##name(struct device *d, struct device_attribute *attr, \ +- const char *buf, size_t len) \ ++CXGB3_STORE_FUNC(store_##name, d, attr, buf, len) \ + { \ + return tm_attr_store(d, buf, len, sched); \ + } \ +-static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name) ++static CXGB3_DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name) + + TM_ATTR(sched0, 0); + TM_ATTR(sched1, 1); +@@ -749,6 +1272,15 @@ + TM_ATTR(sched7, 7); + + static struct attribute *offload_attrs[] = { ++ &dev_attr_tcp_retries1.attr, ++ &dev_attr_tcp_retries2.attr, ++ &dev_attr_tcp_syn_retries.attr, ++ &dev_attr_tcp_keepalive_probes.attr, ++ &dev_attr_tcp_sack.attr, ++ &dev_attr_tcp_timestamps.attr, ++ &dev_attr_tcp_keepalive_time.attr, ++ &dev_attr_tcp_keepalive_intvl.attr, ++ &dev_attr_tcp_finwait2_timeout.attr, + &dev_attr_sched0.attr, + &dev_attr_sched1.attr, + &dev_attr_sched2.attr, +@@ -760,18 +1292,18 @@ + NULL + }; + +-static struct attribute_group offload_attr_group = {.attrs = offload_attrs }; +- +-static ssize_t iscsi_ipv4addr_attr_show(struct device *d, char *buf) +-{ +- struct port_info *pi = netdev_priv(to_net_dev(d)); +- ++static struct attribute_group offload_attr_group = { .attrs = offload_attrs }; ++ ++static ssize_t iscsi_ipv4addr_attr_show(struct cxgb3_compat_device *d, char *buf) ++{ ++ struct port_info *pi = netdev_priv(to_net_dev(d)); + __be32 a = pi->iscsi_ipv4addr; ++ + return sprintf(buf, NIPQUAD_FMT "\n", NIPQUAD(a)); + } + +-static ssize_t iscsi_ipv4addr_attr_store(struct device *d, +- const char *buf, size_t len) ++static ssize_t iscsi_ipv4addr_attr_store(struct cxgb3_compat_device *d, ++ const char *buf, size_t len) + { + struct port_info *pi = netdev_priv(to_net_dev(d)); + +@@ -780,17 +1312,15 @@ + } + + #define ISCSI_IPADDR_ATTR(name) \ +-static ssize_t show_##name(struct device *d, struct device_attribute *attr, \ +- char *buf) \ ++CXGB3_SHOW_FUNC(show_##name, d, attr, buf) \ + { \ + return iscsi_ipv4addr_attr_show(d, buf); \ + } \ +-static ssize_t store_##name(struct device *d, struct device_attribute *attr, \ +- const char *buf, size_t len) \ ++CXGB3_STORE_FUNC(store_##name, d, attr, buf, len) \ + { \ + return iscsi_ipv4addr_attr_store(d, buf, len); \ + } \ +-static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name) ++static CXGB3_DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name) + + ISCSI_IPADDR_ATTR(iscsi_ipv4addr); + +@@ -802,6 +1332,7 @@ + static struct attribute_group iscsi_offload_attr_group = { + .attrs = iscsi_offload_attrs + }; ++#endif /* ! LINUX_2_4 */ + + /* + * Sends an sk_buff to an offload queue driver +@@ -822,13 +1353,12 @@ + struct cpl_smt_write_req *req; + struct sk_buff *skb = alloc_skb(sizeof(*req), GFP_KERNEL); + +- if (!skb) +- return -ENOMEM; ++ if (!skb) return -ENOMEM; + + req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req)); + req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); + OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx)); +- req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ ++ req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ + req->iff = idx; + memset(req->src_mac1, 0, sizeof(req->src_mac1)); + memcpy(req->src_mac0, adapter->port[idx]->dev_addr, ETH_ALEN); +@@ -842,7 +1372,7 @@ + int i; + + for_each_port(adapter, i) +- write_smt_entry(adapter, i); ++ write_smt_entry(adapter, i); + return 0; + } + +@@ -860,7 +1390,6 @@ + { + struct sk_buff *skb; + struct mngt_pktsched_wr *req; +- int ret; + + skb = alloc_skb(sizeof(*req), GFP_KERNEL | __GFP_NOFAIL); + req = (struct mngt_pktsched_wr *)skb_put(skb, sizeof(*req)); +@@ -871,9 +1400,9 @@ + req->min = lo; + req->max = hi; + req->binding = port; +- ret = t3_mgmt_tx(adap, skb); +- +- return ret; ++ t3_mgmt_tx(adap, skb); ++ ++ return 0; + } + + static int bind_qsets(struct adapter *adap) +@@ -885,8 +1414,8 @@ + + for (j = 0; j < pi->nqsets; ++j) { + int ret = send_pktsched_cmd(adap, 1, +- pi->first_qset + j, -1, +- -1, i); ++ pi->first_qset + j, -1, -1, ++ pi->tx_chan); + if (ret) + err = ret; + } +@@ -895,7 +1424,9 @@ + return err; + } + ++#if !defined(LINUX_2_4) + #define FW_FNAME "t3fw-%d.%d.%d.bin" ++#define TPEEPROM_NAME "t3%c_tp_eeprom-%d.%d.%d.bin" + #define TPSRAM_NAME "t3%c_protocol_sram-%d.%d.%d.bin" + + static int upgrade_fw(struct adapter *adap) +@@ -917,8 +1448,8 @@ + release_firmware(fw); + + if (ret == 0) +- dev_info(dev, "successful upgrade to firmware %d.%d.%d\n", +- FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); ++ dev_warn(dev, "successful upgrade to firmware %d.%d.%d\n", ++ FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); + else + dev_err(dev, "failed to upgrade to firmware %d.%d.%d\n", + FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); +@@ -926,11 +1457,17 @@ + return ret; + } + ++static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, ++ u8 *data); ++ + static inline char t3rev2char(struct adapter *adapter) + { +- char rev = 0; ++ char rev = 'z'; + + switch(adapter->params.rev) { ++ case T3_REV_A: ++ rev = 'a'; ++ break; + case T3_REV_B: + case T3_REV_B2: + rev = 'b'; +@@ -970,7 +1507,7 @@ + + ret = t3_set_proto_sram(adap, tpsram->data); + if (ret == 0) +- dev_info(dev, ++ dev_warn(dev, + "successful update of protocol engine " + "to %d.%d.%d\n", + TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); +@@ -985,10 +1522,16 @@ + + return ret; + } ++#endif /* ! LINUX_2_4 */ ++ ++static inline int is_in_filter_mode(struct adapter *adapter) ++{ ++ return adapter->params.mc5.nfilters; ++} + + /** + * cxgb_up - enable the adapter +- * @adapter: adapter being enabled ++ * @adap: adapter being enabled + * + * Called when the first port is enabled, this function performs the + * actions necessary to make an adapter operational, such as completing +@@ -998,24 +1541,38 @@ + */ + static int cxgb_up(struct adapter *adap) + { +- int err; +- int must_load; ++ int err = 0; + + if (!(adap->flags & FULL_INIT_DONE)) { +- err = t3_check_fw_version(adap, &must_load); ++ err = t3_check_fw_version(adap); ++#if !defined(LINUX_2_4) + if (err == -EINVAL) { + err = upgrade_fw(adap); +- if (err && must_load) +- goto out; +- } +- +- err = t3_check_tpsram_version(adap, &must_load); ++ CH_WARN(adap, "FW upgrade to %d.%d.%d %s\n", ++ FW_VERSION_MAJOR, FW_VERSION_MINOR, ++ FW_VERSION_MICRO, err ? "failed" : "succeeded"); ++ } ++#endif ++ ++ err = t3_check_tpsram_version(adap); ++#if !defined(LINUX_2_4) + if (err == -EINVAL) { + err = update_tpsram(adap); +- if (err && must_load) +- goto out; +- } +- ++ CH_WARN(adap, "TP upgrade to %d.%d.%d %s\n", ++ TP_VERSION_MAJOR, TP_VERSION_MINOR, ++ TP_VERSION_MICRO, err ? "failed" : "succeeded"); ++ } ++#endif ++ ++ /* PR 6487. TOE and filtering are mutually exclusive */ ++ cxgb3_filter_toe_mode(adap, is_in_filter_mode(adap) ? ++ CXGB3_FTM_FILTER : CXGB3_FTM_TOE); ++ ++#if !defined(NAPI_UPDATE) ++ err = init_dummy_netdevs(adap); ++ if (err) ++ goto out; ++#endif + /* + * Clear interrupts now to catch errors if t3_init_hw fails. + * We clear them again later as initialization may trigger +@@ -1028,15 +1585,31 @@ + goto out; + + t3_set_reg_field(adap, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT); ++ ++/* T3 has a lookup table for 4 different page sizes with the default 4K page size using HPZ0 ++ * Use the upper register HPZ3 for TCP DPP to support huge pages ++ */ ++ ++#if defined(CONFIG_T3_ZCOPY_HUGEPAGES) && defined(CONFIG_HUGETLB_PAGE) ++#define T3_HPAGE_SHIFT (HPAGE_SHIFT > 27 ? 27 : HPAGE_SHIFT) ++ t3_write_reg(adap, A_ULPRX_TDDP_PSZ, ++ V_HPZ0(PAGE_SHIFT - 12) | ++ V_HPZ3(T3_HPAGE_SHIFT - 12)); ++#else + t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); ++#endif + + err = setup_sge_qsets(adap); + if (err) + goto out; + ++ alloc_filters(adap); + setup_rss(adap); ++#if defined(NAPI_UPDATE) + if (!(adap->flags & NAPI_INIT)) + init_napi(adap); ++#endif ++ t3_start_sge_timers(adap); + adap->flags |= FULL_INIT_DONE; + } + +@@ -1056,12 +1629,10 @@ + goto irq_err; + } + } else if ((err = request_irq(adap->pdev->irq, +- t3_intr_handler(adap, +- adap->sge.qs[0].rspq. +- polling), +- (adap->flags & USING_MSI) ? +- 0 : IRQF_SHARED, +- adap->name, adap))) ++ t3_intr_handler(adap, ++ adap->sge.qs[0].rspq.polling), ++ (adap->flags & USING_MSI) ? 0 : IRQF_SHARED, ++ adap->name, adap))) + goto irq_err; + + enable_all_napi(adap); +@@ -1074,7 +1645,7 @@ + + if (adap->flags & TP_PARITY_INIT) { + t3_write_reg(adap, A_TP_INT_CAUSE, +- F_CMCACHEPERR | F_ARPLUTPERR); ++ F_CMCACHEPERR | F_ARPLUTPERR); + t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff); + } + +@@ -1086,9 +1657,9 @@ + free_irq_resources(adap); + goto out; + } ++ setup_hw_filters(adap); + adap->flags |= QUEUES_BOUND; + } +- + out: + return err; + irq_err: +@@ -1101,10 +1672,14 @@ + */ + static void cxgb_down(struct adapter *adapter) + { ++ unsigned long flags; ++ + t3_sge_stop(adapter); +- spin_lock_irq(&adapter->work_lock); /* sync with PHY intr task */ ++ ++ /* sync with PHY intr task */ ++ spin_lock_irqsave(&adapter->work_lock, flags); + t3_intr_disable(adapter); +- spin_unlock_irq(&adapter->work_lock); ++ spin_unlock_irqrestore(&adapter->work_lock, flags); + + free_irq_resources(adapter); + flush_workqueue(cxgb3_wq); /* wait for external IRQ handler */ +@@ -1116,8 +1691,8 @@ + unsigned int timeo; + + timeo = adap->params.linkpoll_period ? +- (HZ * adap->params.linkpoll_period) / 10 : +- adap->params.stats_update_period * HZ; ++ (HZ * adap->params.linkpoll_period) / 10 : ++ adap->params.stats_update_period * HZ; + if (timeo) + queue_delayed_work(cxgb3_wq, &adap->adap_check_task, timeo); + } +@@ -1128,10 +1703,18 @@ + struct adapter *adapter = pi->adapter; + struct t3cdev *tdev = dev2t3cdev(dev); + int adap_up = adapter->open_device_map & PORT_MASK; +- int err; ++ int err = 0; + + if (test_and_set_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) + return 0; ++ ++ /* PR 6487. Filtering and TOE mutually exclusive */ ++ if (!cxgb3_filter_toe_mode(adapter, CXGB3_FTM_TOE)) { ++ printk(KERN_WARNING ++ "%s: filtering on. Offload disabled\n", dev->name); ++ err = -1; ++ goto out; ++ } + + if (!adap_up && (err = cxgb_up(adapter)) < 0) + goto out; +@@ -1146,11 +1729,13 @@ + t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd, + adapter->params.b_wnd, + adapter->params.rev == 0 ? +- adapter->port[0]->mtu : 0xffff); ++ adapter->port[0]->mtu : 0xffff); + init_smt(adapter); + +- if (sysfs_create_group(&tdev->lldev->dev.kobj, &offload_attr_group)) +- dev_dbg(&dev->dev, "cannot create sysfs group\n"); ++#ifndef LINUX_2_4 ++ /* Never mind if the next step fails */ ++ sysfs_create_group(net2kobj(tdev->lldev), &offload_attr_group); ++#endif /* LINUX_2_4 */ + + /* Call back all registered clients */ + cxgb3_add_clients(tdev); +@@ -1174,9 +1759,9 @@ + + /* Call back all registered clients */ + cxgb3_remove_clients(tdev); +- +- sysfs_remove_group(&tdev->lldev->dev.kobj, &offload_attr_group); +- ++#ifndef LINUX_2_4 ++ sysfs_remove_group(net2kobj(tdev->lldev), &offload_attr_group); ++#endif + tdev->lldev = NULL; + cxgb3_set_dummy_ops(tdev); + t3_tp_set_offload_mode(adapter, 0); +@@ -1200,12 +1785,15 @@ + return err; + + set_bit(pi->port_id, &adapter->open_device_map); ++ + if (is_offload(adapter) && !ofld_disable) { + err = offload_open(dev); + if (err) + printk(KERN_WARNING + "Could not initialize offload capabilities\n"); +- sysfs_create_group(&dev->dev.kobj, &iscsi_offload_attr_group); ++#ifndef LINUX_2_4 ++ sysfs_create_group(net2kobj(dev), &iscsi_offload_attr_group); ++#endif + } + + link_start(dev); +@@ -1222,17 +1810,26 @@ + struct port_info *pi = netdev_priv(dev); + struct adapter *adapter = pi->adapter; + +- if (!adapter->open_device_map) +- return 0; ++ /* Stop link fault interrupts */ ++ t3_xgm_intr_disable(adapter, pi->port_id); ++ t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset); + + t3_port_intr_disable(adapter, pi->port_id); + netif_stop_queue(dev); +- pi->phy.ops->power_down(&pi->phy, 1); + netif_carrier_off(dev); +- t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); +- ++ ++ /* disable pause frames */ ++ t3_set_reg_field(adapter, A_XGM_TX_CFG + pi->mac.offset, ++ F_TXPAUSEEN, 0); ++ ++ /* Reset RX FIFO HWM */ ++ t3_set_reg_field(adapter, A_XGM_RXFIFO_CFG + pi->mac.offset, ++ V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM), 0); ++ ++#ifndef LINUX_2_4 + if (is_offload(adapter) && !ofld_disable) +- sysfs_remove_group(&dev->dev.kobj, &iscsi_offload_attr_group); ++ sysfs_remove_group(net2kobj(dev), &iscsi_offload_attr_group); ++#endif + + spin_lock_irq(&adapter->work_lock); /* sync with update task */ + clear_bit(pi->port_id, &adapter->open_device_map); +@@ -1245,6 +1842,17 @@ + if (!adapter->open_device_map) + cxgb_down(adapter); + ++ msleep(100); ++ ++ /* Wait for TXFIFO empty */ ++ t3_wait_op_done(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, ++ F_TXFIFO_EMPTY, 1, 20, 5); ++ ++ msleep(100); ++ t3_mac_disable(&pi->mac, MAC_DIRECTION_RX); ++ ++ pi->phy.ops->power_down(&pi->phy, 1); ++ + return 0; + } + +@@ -1253,11 +1861,13 @@ + struct port_info *pi = netdev_priv(dev); + struct adapter *adapter = pi->adapter; + struct net_device_stats *ns = &pi->netstats; +- const struct mac_stats *pstats; +- +- spin_lock(&adapter->stats_lock); +- pstats = t3_mac_update_stats(&pi->mac); +- spin_unlock(&adapter->stats_lock); ++ const struct mac_stats *pstats = &pi->mac.stats; ++ ++ if (adapter->flags & FULL_INIT_DONE) { ++ spin_lock(&adapter->stats_lock); ++ t3_mac_update_stats(&pi->mac); ++ spin_unlock(&adapter->stats_lock); ++ } + + ns->tx_bytes = pstats->tx_octets; + ns->tx_packets = pstats->tx_frames; +@@ -1267,8 +1877,8 @@ + + ns->tx_errors = pstats->tx_underrun; + ns->rx_errors = pstats->rx_symbol_errs + pstats->rx_fcs_errs + +- pstats->rx_too_long + pstats->rx_jabber + pstats->rx_short + +- pstats->rx_fifo_ovfl; ++ pstats->rx_too_long + pstats->rx_jabber + pstats->rx_short + ++ pstats->rx_fifo_ovfl; + + /* detailed rx_errors */ + ns->rx_length_errors = pstats->rx_jabber + pstats->rx_too_long; +@@ -1345,25 +1955,24 @@ + "VLANextractions ", + "VLANinsertions ", + "TxCsumOffload ", ++ "TXCoalesceWR ", ++ "TXCoalescePkt ", + "RxCsumGood ", +- "LroAggregated ", ++ "RxDrops ", ++ ++ "LroQueued ", + "LroFlushed ", +- "LroNoDesc ", +- "RxDrops ", ++ "LroExceededSessions", + + "CheckTXEnToggled ", + "CheckResets ", + +-}; +- +-static int get_sset_count(struct net_device *dev, int sset) +-{ +- switch (sset) { +- case ETH_SS_STATS: +- return ARRAY_SIZE(stats_strings); +- default: +- return -EOPNOTSUPP; +- } ++ "LinkFaults ", ++}; ++ ++static int get_stats_count(struct net_device *dev) ++{ ++ return ARRAY_SIZE(stats_strings); + } + + #define T3_REGMAP_SIZE (3 * 1024) +@@ -1373,17 +1982,18 @@ + return T3_REGMAP_SIZE; + } + ++#ifndef LINUX_2_4 + static int get_eeprom_len(struct net_device *dev) + { + return EEPROMSIZE; + } ++#endif /* LINUX_2_4 */ + + static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) + { + struct port_info *pi = netdev_priv(dev); + struct adapter *adapter = pi->adapter; +- u32 fw_vers = 0; +- u32 tp_vers = 0; ++ u32 fw_vers = 0, tp_vers = 0; + + spin_lock(&adapter->stats_lock); + t3_get_fw_version(adapter, &fw_vers); +@@ -1408,7 +2018,7 @@ + } + } + +-static void get_strings(struct net_device *dev, u32 stringset, u8 * data) ++static void get_strings(struct net_device *dev, u32 stringset, u8 *data) + { + if (stringset == ETH_SS_STATS) + memcpy(data, stats_strings, sizeof(stats_strings)); +@@ -1425,16 +2035,27 @@ + return tot; + } + ++static void clear_sge_port_stats(struct adapter *adapter, struct port_info *p) ++{ ++ int i; ++ struct sge_qset *qs = &adapter->sge.qs[p->first_qset]; ++ ++ for (i = 0; i < p->nqsets; i++, qs++) ++ memset(qs->port_stats, 0, sizeof(qs->port_stats)); ++} ++ + static void get_stats(struct net_device *dev, struct ethtool_stats *stats, + u64 *data) + { + struct port_info *pi = netdev_priv(dev); + struct adapter *adapter = pi->adapter; +- const struct mac_stats *s; +- +- spin_lock(&adapter->stats_lock); +- s = t3_mac_update_stats(&pi->mac); +- spin_unlock(&adapter->stats_lock); ++ const struct mac_stats *s = &pi->mac.stats; ++ ++ if (adapter->flags & FULL_INIT_DONE) { ++ spin_lock(&adapter->stats_lock); ++ t3_mac_update_stats(&pi->mac); ++ spin_unlock(&adapter->stats_lock); ++ } + + *data++ = s->tx_octets; + *data++ = s->tx_frames; +@@ -1478,14 +2099,20 @@ + *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANEX); + *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS); + *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM); ++ *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_COALESCE_WR); ++ *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_COALESCE_PKT); + *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD); +- *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_LRO_AGGR); +- *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_LRO_FLUSHED); +- *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_LRO_NO_DESC); + *data++ = s->rx_cong_drops; ++ *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_LRO_SKB) + ++ collect_sge_port_stats(adapter, pi, SGE_PSTAT_LRO_PG) + ++ collect_sge_port_stats(adapter, pi, SGE_PSTAT_LRO_ACK); ++ *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_LRO); ++ *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_LRO_OVFLOW); + + *data++ = s->num_toggled; + *data++ = s->num_resets; ++ ++ *data++ = s->link_faults; + } + + static inline void reg_block_dump(struct adapter *ap, void *buf, +@@ -1493,7 +2120,7 @@ + { + u32 *p = buf + start; + +- for (; start <= end; start += sizeof(u32)) ++ for ( ; start <= end; start += sizeof(u32)) + *p++ = t3_read_reg(ap, start); + } + +@@ -1502,7 +2129,6 @@ + { + struct port_info *pi = netdev_priv(dev); + struct adapter *ap = pi->adapter; +- + /* + * Version scheme: + * bits 0..9: chip version +@@ -1639,9 +2265,10 @@ + } + + if (cmd->autoneg == AUTONEG_DISABLE) { +- int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex); +- +- if (!(lc->supported & cap) || cmd->speed == SPEED_1000) ++ cap = speed_duplex_to_caps(cmd->speed, cmd->duplex); ++ ++ if (!(lc->supported & cap) || cmd->speed == SPEED_1000 || ++ cmd->speed == SPEED_10000) + return -EINVAL; + lc->requested_speed = cmd->speed; + lc->requested_duplex = cmd->duplex; +@@ -1712,18 +2339,21 @@ + + p->rx_csum_offload = data; + if (!data) { +- int i; +- +- for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) +- set_qset_lro(dev, i, 0); ++ struct adapter *adap = p->adapter; ++ int i; ++ ++ for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) { ++ adap->params.sge.qset[i].lro = 0; ++ adap->sge.qs[i].lro.enabled = 0; ++ } + } + return 0; + } + + static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e) + { +- struct port_info *pi = netdev_priv(dev); +- struct adapter *adapter = pi->adapter; ++ const struct port_info *pi = netdev_priv(dev); ++ const struct adapter *adapter = pi->adapter; + const struct qset_params *q = &adapter->params.sge.qset[pi->first_qset]; + + e->rx_max_pending = MAX_RX_BUFFERS; +@@ -1750,7 +2380,7 @@ + e->rx_mini_pending > MAX_RSPQ_ENTRIES || + e->rx_mini_pending < MIN_RSPQ_ENTRIES || + e->rx_pending < MIN_FL_ENTRIES || +- e->rx_jumbo_pending < MIN_FL_ENTRIES || ++ e->rx_jumbo_pending < MIN_FL_JUMBO_ENTRIES || + e->tx_pending < adapter->params.nports * MIN_TXQ_ENTRIES) + return -EINVAL; + +@@ -1795,7 +2425,7 @@ + } + + static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e, +- u8 * data) ++ u8 *data) + { + struct port_info *pi = netdev_priv(dev); + struct adapter *adapter = pi->adapter; +@@ -1807,7 +2437,7 @@ + + e->magic = EEPROM_MAGIC; + for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4) +- err = t3_seeprom_read(adapter, i, (__le32 *) & buf[i]); ++ err = t3_seeprom_read(adapter, i, (u32 *)&buf[i]); + + if (!err) + memcpy(data, buf + e->offset, e->len); +@@ -1816,14 +2446,14 @@ + } + + static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, +- u8 * data) +-{ +- struct port_info *pi = netdev_priv(dev); +- struct adapter *adapter = pi->adapter; +- u32 aligned_offset, aligned_len; +- __le32 *p; ++ u8 *data) ++{ ++ struct port_info *pi = netdev_priv(dev); ++ struct adapter *adapter = pi->adapter; ++ u32 aligned_offset, aligned_len, *p; + u8 *buf; +- int err; ++ int err = 0; ++ + + if (eeprom->magic != EEPROM_MAGIC) + return -EINVAL; +@@ -1835,11 +2465,11 @@ + buf = kmalloc(aligned_len, GFP_KERNEL); + if (!buf) + return -ENOMEM; +- err = t3_seeprom_read(adapter, aligned_offset, (__le32 *) buf); ++ err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf); + if (!err && aligned_len > 4) + err = t3_seeprom_read(adapter, + aligned_offset + aligned_len - 4, +- (__le32 *) & buf[aligned_len - 4]); ++ (u32 *)&buf[aligned_len - 4]); + if (err) + goto out; + memcpy(buf + (eeprom->offset & 3), data, eeprom->len); +@@ -1850,7 +2480,7 @@ + if (err) + goto out; + +- for (p = (__le32 *) buf; !err && aligned_len; aligned_len -= 4, p++) { ++ for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { + err = t3_seeprom_write(adapter, aligned_offset, *p); + aligned_offset += 4; + } +@@ -1870,57 +2500,637 @@ + memset(&wol->sopass, 0, sizeof(wol->sopass)); + } + +-static int cxgb3_set_flags(struct net_device *dev, u32 data) +-{ +- struct port_info *pi = netdev_priv(dev); +- int i; +- +- if (data & ETH_FLAG_LRO) { +- if (!pi->rx_csum_offload) +- return -EINVAL; +- +- for (i = pi->first_qset; i < pi->first_qset + pi->nqsets; i++) +- set_qset_lro(dev, i, 1); +- +- } else +- for (i = pi->first_qset; i < pi->first_qset + pi->nqsets; i++) +- set_qset_lro(dev, i, 0); +- +- return 0; +-} +- +-static const struct ethtool_ops cxgb_ethtool_ops = { +- .get_settings = get_settings, +- .set_settings = set_settings, +- .get_drvinfo = get_drvinfo, +- .get_msglevel = get_msglevel, +- .set_msglevel = set_msglevel, +- .get_ringparam = get_sge_param, +- .set_ringparam = set_sge_param, +- .get_coalesce = get_coalesce, +- .set_coalesce = set_coalesce, +- .get_eeprom_len = get_eeprom_len, +- .get_eeprom = get_eeprom, +- .set_eeprom = set_eeprom, +- .get_pauseparam = get_pauseparam, +- .set_pauseparam = set_pauseparam, +- .get_rx_csum = get_rx_csum, +- .set_rx_csum = set_rx_csum, +- .set_tx_csum = ethtool_op_set_tx_csum, +- .set_sg = ethtool_op_set_sg, +- .get_link = ethtool_op_get_link, +- .get_strings = get_strings, +- .phys_id = cxgb3_phys_id, +- .nway_reset = restart_autoneg, +- .get_sset_count = get_sset_count, ++static struct ethtool_ops cxgb_ethtool_ops = { ++ .get_settings = get_settings, ++ .set_settings = set_settings, ++ .get_drvinfo = get_drvinfo, ++ .get_msglevel = get_msglevel, ++ .set_msglevel = set_msglevel, ++ .get_ringparam = get_sge_param, ++ .set_ringparam = set_sge_param, ++ .get_coalesce = get_coalesce, ++ .set_coalesce = set_coalesce, ++#ifndef LINUX_2_4 ++ .get_eeprom_len = get_eeprom_len, ++#endif /* LINUX_2_4 */ ++ .get_eeprom = get_eeprom, ++ .set_eeprom = set_eeprom, ++ .get_pauseparam = get_pauseparam, ++ .set_pauseparam = set_pauseparam, ++ .get_rx_csum = get_rx_csum, ++ .set_rx_csum = set_rx_csum, ++ .get_tx_csum = ethtool_op_get_tx_csum, ++#ifndef LINUX_2_4 ++ .set_tx_csum = ethtool_op_set_tx_csum, ++#endif /* LINUX_2_4 */ ++ .get_sg = ethtool_op_get_sg, ++ .set_sg = ethtool_op_set_sg, ++ .get_link = ethtool_op_get_link, ++ .get_strings = get_strings, ++ .phys_id = cxgb3_phys_id, ++ .nway_reset = restart_autoneg, ++ .get_stats_count = get_stats_count, + .get_ethtool_stats = get_stats, +- .get_regs_len = get_regs_len, +- .get_regs = get_regs, +- .get_wol = get_wol, +- .set_tso = ethtool_op_set_tso, +- .get_flags = ethtool_op_get_flags, +- .set_flags = cxgb3_set_flags, +-}; ++ .get_regs_len = get_regs_len, ++ .get_regs = get_regs, ++ .get_wol = get_wol, ++#ifndef LINUX_2_4 ++ .get_tso = ethtool_op_get_tso, ++ .set_tso = ethtool_op_set_tso, ++#endif /* LINUX_2_4 */ ++#ifdef CXGB3_ETHTOOL_GPERMADDR ++ .get_perm_addr = ethtool_op_get_perm_addr ++#endif ++}; ++ ++ ++#define adjust_proc_metrics() \ ++ if (len <= offset + count) *eof = 1; \ ++ *start = buf + offset; \ ++ len -= offset; \ ++ if (len > count) len = count; \ ++ if (len < 0) len = 0; ++ ++static int snmp_read_proc(char *buf, char **start, off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct adapter *adapter = data; ++ struct tp_mib_stats m; ++ int len = 0; ++ ++ spin_lock(&adapter->stats_lock); ++ t3_tp_get_mib_stats(adapter, &m); ++ spin_unlock(&adapter->stats_lock); ++ ++#define MIB32(s, field) len += sprintf(buf + len, "%-18s %u\n", s, m.field) ++#define MIB64(s, hi, lo) \ ++ len += sprintf(buf + len, "%-18s %llu\n", s, \ ++ ((unsigned long long)m.hi << 32) + m.lo) ++ ++ MIB64("IPInReceives:", ipInReceive_hi, ipInReceive_lo); ++ MIB64("IPInHdrErrors:", ipInHdrErrors_hi, ipInHdrErrors_lo); ++ MIB64("IPInAddrErrors:", ipInAddrErrors_hi, ipInAddrErrors_lo); ++ MIB64("IPInUnknownProtos:", ipInUnknownProtos_hi, ++ ipInUnknownProtos_lo); ++ MIB64("IPInDiscards:", ipInDiscards_hi, ipInDiscards_lo); ++ MIB64("IPInDelivers:", ipInDelivers_hi, ipInDelivers_lo); ++ MIB64("IPOutRequests:", ipOutRequests_hi, ipOutRequests_lo); ++ MIB64("IPOutDiscards:", ipOutDiscards_hi, ipOutDiscards_lo); ++ MIB64("IPOutNoRoutes:", ipOutNoRoutes_hi, ipOutNoRoutes_lo); ++ MIB32("IPReasmTimeout:", ipReasmTimeout); ++ MIB32("IPReasmReqds:", ipReasmReqds); ++ MIB32("IPReasmOKs:", ipReasmOKs); ++ MIB32("IPReasmFails:", ipReasmFails); ++ MIB32("TCPActiveOpens:", tcpActiveOpens); ++ MIB32("TCPPassiveOpens:", tcpPassiveOpens); ++ MIB32("TCPAttemptFails:", tcpAttemptFails); ++ MIB32("TCPEstabResets:", tcpEstabResets); ++ MIB32("TCPOutRsts:", tcpOutRsts); ++ MIB32("TCPCurrEstab:", tcpCurrEstab); ++ MIB64("TCPInSegs:", tcpInSegs_hi, tcpInSegs_lo); ++ MIB64("TCPOutSegs:", tcpOutSegs_hi, tcpOutSegs_lo); ++ MIB64("TCPRetransSeg:", tcpRetransSeg_hi, tcpRetransSeg_lo); ++ MIB64("TCPInErrs:", tcpInErrs_hi, tcpInErrs_lo); ++ MIB32("TCPRtoMin:", tcpRtoMin); ++ MIB32("TCPRtoMax:", tcpRtoMax); ++ ++#undef MIB32 ++#undef MIB64 ++ ++ adjust_proc_metrics(); ++ return len; ++} ++ ++static int mtus_read_proc(char *buf, char **start, off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct adapter *adapter = data; ++ unsigned short hw_mtus[NMTUS]; ++ int i, len = 0; ++ ++ spin_lock(&adapter->stats_lock); ++ t3_read_hw_mtus(adapter, hw_mtus); ++ spin_unlock(&adapter->stats_lock); ++ ++ len += sprintf(buf, "Soft MTU\tEffective MTU\n"); ++ for (i = 0; i < NMTUS; ++i) ++ len += sprintf(buf + len, "%8u\t\t%5u\n", ++ adapter->params.mtus[i], hw_mtus[i]); ++ ++ adjust_proc_metrics(); ++ return len; ++} ++ ++static int cong_ctrl_read_proc(char *buf, char **start, off_t offset, ++ int count, int *eof, void *data) ++{ ++ static const char *dec_fac[] = { ++ "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", ++ "0.9375" }; ++ ++ unsigned short incr[NMTUS][NCCTRL_WIN]; ++ struct adapter *adapter = data; ++ int i, len = 0; ++ ++ t3_get_cong_cntl_tab(adapter, incr); ++ ++ for (i = 0; i < NCCTRL_WIN; ++i) { ++ int j; ++ ++ for (j = 0; j < NMTUS; ++j) ++ len += sprintf(buf + len, "%5u ", incr[j][i]); ++ ++ len += sprintf(buf + len, "%5u %s\n", adapter->params.a_wnd[i], ++ dec_fac[adapter->params.b_wnd[i]]); ++ } ++ ++ adjust_proc_metrics(); ++ return len; ++} ++ ++static int rss_read_proc(char *buf, char **start, off_t offset, int count, ++ int *eof, void *data) ++{ ++ u8 lkup_tab[2 * RSS_TABLE_SIZE]; ++ u16 map_tab[RSS_TABLE_SIZE]; ++ struct adapter *adapter = data; ++ int i, len; ++ ++ i = t3_read_rss(adapter, lkup_tab, map_tab); ++ if (i < 0) ++ return i; ++ ++ len = sprintf(buf, "Idx\tLookup\tMap\n"); ++ for (i = 0; i < RSS_TABLE_SIZE; ++i) ++ len += sprintf(buf + len, "%3u\t %3u\t %u\n", i, lkup_tab[i], ++ map_tab[i]); ++ for (; i < 2 * RSS_TABLE_SIZE; ++i) ++ len += sprintf(buf + len, "%3u\t %3u\n", i, lkup_tab[i]); ++ ++ adjust_proc_metrics(); ++ return len; ++} ++ ++static int sched_read_proc(char *buf, char **start, off_t offset, int count, ++ int *eof, void *data) ++{ ++ int i, len; ++ unsigned int map, kbps, ipg; ++ unsigned int pace_tab[NTX_SCHED]; ++ struct adapter *adap = data; ++ ++ map = t3_read_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP); ++ t3_read_pace_tbl(adap, pace_tab); ++ ++ len = sprintf(buf, "Scheduler Mode Channel Rate (Kbps) " ++ "Class IPG (0.1 ns) Flow IPG (us)\n"); ++ for (i = 0; i < NTX_SCHED; ++i) { ++ t3_get_tx_sched(adap, i, &kbps, &ipg); ++ len += sprintf(buf + len, " %u %-5s %u ", i, ++ (map & (1 << (S_TX_MOD_TIMER_MODE + i))) ? ++ "flow" : "class", !!(map & (1 << i))); ++ if (kbps) ++ len += sprintf(buf + len, "%9u ", kbps); ++ else ++ len += sprintf(buf + len, " disabled "); ++ ++ if (ipg) ++ len += sprintf(buf + len, "%13u ", ipg); ++ else ++ len += sprintf(buf + len, " disabled "); ++ ++ if (pace_tab[i]) ++ len += sprintf(buf + len, "%10u\n", pace_tab[i] / 1000); ++ else ++ len += sprintf(buf + len, " disabled\n"); ++ } ++ ++ adjust_proc_metrics(); ++ return len; ++} ++ ++static int stats_read_proc(char *buf, char **start, off_t offset, ++ int count, int *eof, void *data) ++{ ++ int i, len = 0; ++ struct adapter *adapter = data; ++ ++ len += sprintf(buf + len, "Interface: "); ++ for (i = 0; i < SGE_QSETS; ++i) ++ len += sprintf(buf + len, " %10s", ++ adapter->sge.qs[i].netdev ? ++ adapter->sge.qs[i].netdev->name : "N/A"); ++ ++#define C(s, v) \ ++ len += sprintf(buf + len, "\n%-18s", s); \ ++ for (i = 0; i < SGE_QSETS; ++i) \ ++ len += sprintf(buf + len, " %10lu", adapter->sge.qs[i].v); \ ++ ++ C("RspQEmpty:", rspq.empty); ++ C("FL0Empty:", fl[0].empty); ++ C("FL0AllocFailed:", fl[0].alloc_failed); ++ C("FL1Empty:", fl[1].empty); ++ C("FL1AllocFailed:", fl[1].alloc_failed); ++ C("TxQ0Full:", txq[0].stops); ++ C("TxQ0Restarts:", txq[0].restarts); ++ C("TxQ1Full:", txq[1].stops); ++ C("TxQ1Restarts:", txq[1].restarts); ++ C("TxQ2Full:", txq[2].stops); ++ C("TxQ2Restarts:", txq[2].restarts); ++ C("RxEthPackets:", rspq.eth_pkts); ++ C("TXCoalesceWR:", port_stats[SGE_PSTAT_TX_COALESCE_WR]); ++ C("TXCoalescePkt:", port_stats[SGE_PSTAT_TX_COALESCE_PKT]); ++ C("LROcompleted:", port_stats[SGE_PSTAT_LRO]); ++ C("LROpages:", port_stats[SGE_PSTAT_LRO_PG]); ++ C("LROpackets:", port_stats[SGE_PSTAT_LRO_SKB]); ++ C("LROmergedACKs:", port_stats[SGE_PSTAT_LRO_ACK]); ++ C("LROoverflow:", port_stats[SGE_PSTAT_LRO_OVFLOW]); ++ C("LROcollisions:", port_stats[SGE_PSTAT_LRO_COLSN]); ++ C("RxOffloadPackets:", rspq.offload_pkts); ++ C("RxOffloadBundles:", rspq.offload_bundles); ++ C("PureRepsonses:", rspq.pure_rsps); ++ C("RxImmediateData:", rspq.imm_data); ++ C("ANE:", rspq.async_notif); ++ C("RxDrops:", rspq.rx_drops); ++ C("RspDeferred:", rspq.nomem); ++ C("UnhandledIntr:", rspq.unhandled_irqs); ++ C("RspStarved:", rspq.starved); ++ C("RspRestarted:", rspq.restarted); ++#undef C ++ ++ len += sprintf(buf + len, "\n%-18s %lu\n", "RxCorrectableErr:", ++ adapter->pmrx.stats.corr_err); ++ len += sprintf(buf + len, "%-18s %lu\n", "TxCorrectableErr:", ++ adapter->pmtx.stats.corr_err); ++ len += sprintf(buf + len, "%-18s %lu\n", "CMCorrectableErr:", ++ adapter->cm.stats.corr_err); ++ ++ len += sprintf(buf + len, "\n%-18s %lu\n", "ActiveRegionFull:", ++ adapter->mc5.stats.active_rgn_full); ++ len += sprintf(buf + len, "%-18s %lu\n", "NFASearchErr:", ++ adapter->mc5.stats.nfa_srch_err); ++ len += sprintf(buf + len, "%-18s %lu\n", "MC5UnknownCmd:", ++ adapter->mc5.stats.unknown_cmd); ++ len += sprintf(buf + len, "%-18s %lu\n", "MC5DelActEmpty:", ++ adapter->mc5.stats.del_act_empty); ++ ++ len += sprintf(buf + len, "\n%-18s %lu\n", "ULPCh0PBLOOB:", ++ adapter->irq_stats[STAT_ULP_CH0_PBL_OOB]); ++ len += sprintf(buf + len, "%-18s %lu\n", "ULPCh1PBLOOB:", ++ adapter->irq_stats[STAT_ULP_CH1_PBL_OOB]); ++ len += sprintf(buf + len, "%-18s %lu\n", "PCICorrectableErr:", ++ adapter->irq_stats[STAT_PCI_CORR_ECC]); ++ ++ adjust_proc_metrics(); ++ return len; ++} ++ ++static void *filter_get_idx(struct seq_file *seq, loff_t pos) ++{ ++ int i; ++ struct adapter *adap = seq->private; ++ struct filter_info *p = adap->filters; ++ ++ if (!p) ++ return NULL; ++ ++ for (i = 0; i < adap->params.mc5.nfilters; i++, p++) ++ if (p->valid) { ++ if (!pos) ++ return p; ++ pos--; ++ } ++ return NULL; ++} ++ ++static void *filter_get_nxt_idx(struct seq_file *seq, struct filter_info *p) ++{ ++ struct adapter *adap = seq->private; ++ struct filter_info *end = &adap->filters[adap->params.mc5.nfilters]; ++ ++ while (++p < end && !p->valid) ++ ; ++ return p < end ? p : NULL; ++} ++ ++static void *filter_seq_start(struct seq_file *seq, loff_t *pos) ++{ ++ return *pos ? filter_get_idx(seq, *pos - 1) : SEQ_START_TOKEN; ++} ++ ++static void *filter_seq_next(struct seq_file *seq, void *v, loff_t *pos) ++{ ++ v = *pos ? filter_get_nxt_idx(seq, v) : filter_get_idx(seq, 0); ++ if (v) ++ ++*pos; ++ return v; ++} ++ ++static void filter_seq_stop(struct seq_file *seq, void *v) ++{ ++} ++ ++static int filter_seq_show(struct seq_file *seq, void *v) ++{ ++ static const char *pkt_type[] = { "*", "tcp", "udp", "frag" }; ++ ++ if (v == SEQ_START_TOKEN) ++ seq_puts(seq, "index SIP DIP sport " ++ "dport VLAN PRI P/MAC type Q\n"); ++ else { ++ char sip[20], dip[20]; ++ struct filter_info *f = v; ++ struct adapter *adap = seq->private; ++ u32 nsip = htonl(f->sip); ++ u32 ndip = htonl(f->dip); ++ ++ sprintf(sip, NIPQUAD_FMT "/%-2u", NIPQUAD(nsip), ++ f->sip_mask ? 33 - ffs(f->sip_mask) : 0); ++ sprintf(dip, NIPQUAD_FMT, NIPQUAD(ndip)); ++ seq_printf(seq, "%5zu %18s %15s ", f - adap->filters, sip, dip); ++ seq_printf(seq, f->sport ? "%5u " : " * ", f->sport); ++ seq_printf(seq, f->dport ? "%5u " : " * ", f->dport); ++ seq_printf(seq, f->vlan != 0xfff ? "%4u " : " * ", f->vlan); ++ seq_printf(seq, f->vlan_prio == FILTER_NO_VLAN_PRI ? ++ " * " : "%1u/%1u ", f->vlan_prio, f->vlan_prio | 1); ++ if (!f->mac_vld) ++ seq_printf(seq, "*/* "); ++ else if (f->mac_hit) ++ seq_printf(seq, "%1u/%3u ", ++ (f->mac_idx >> 3) & 0x1, ++ (f->mac_idx) & 0x7); ++ else ++ seq_printf(seq, "%1u/ * ", ++ (f->mac_idx >> 3) & 0x1); ++ seq_printf(seq, "%4s ", pkt_type[f->pkt_type]); ++ if (!f->pass) ++ seq_printf(seq, "-\n"); ++ else if (f->rss) ++ seq_printf(seq, "*\n"); ++ else ++ seq_printf(seq, "%1u\n", f->qset); ++ } ++ return 0; ++} ++ ++static struct seq_operations filter_seq_ops = { ++ .start = filter_seq_start, ++ .next = filter_seq_next, ++ .stop = filter_seq_stop, ++ .show = filter_seq_show ++}; ++ ++static int filter_seq_open(struct inode *inode, struct file *file) ++{ ++ int rc = seq_open(file, &filter_seq_ops); ++ ++ if (!rc) { ++ struct proc_dir_entry *dp = PDE(inode); ++ struct seq_file *seq = file->private_data; ++ ++ seq->private = dp->data; ++ } ++ return rc; ++} ++ ++static struct file_operations filter_seq_fops = { ++ .owner = THIS_MODULE, ++ .open = filter_seq_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = seq_release ++}; ++ ++struct cxgb3_proc_entry { ++ const char *name; ++ read_proc_t *fn; ++}; ++ ++static struct cxgb3_proc_entry proc_files[] = { ++ { "snmp", snmp_read_proc }, ++ { "congestion_control", cong_ctrl_read_proc }, ++ { "mtus", mtus_read_proc }, ++ { "rss", rss_read_proc }, ++ { "sched", sched_read_proc }, ++ { "stats", stats_read_proc }, ++}; ++ ++static int __devinit cxgb_proc_setup(struct adapter *adapter, ++ struct proc_dir_entry *dir) ++{ ++ int i, created; ++ struct proc_dir_entry *p; ++ ++ if (!dir) ++ return -EINVAL; ++ ++ /* If we can create any of the entries we do. */ ++ for (created = i = 0; i < ARRAY_SIZE(proc_files); ++i) { ++ p = create_proc_read_entry(proc_files[i].name, 0, dir, ++ proc_files[i].fn, adapter); ++ if (p) { ++ SET_PROC_NODE_OWNER(p, THIS_MODULE); ++ created++; ++ } ++ } ++ p = create_proc_entry("filters", S_IRUGO, dir); ++ if (p) { ++ p->proc_fops = &filter_seq_fops; ++ p->data = adapter; ++ created++; ++ } ++ ++ return created ? 0 : -ENOMEM; ++} ++ ++static void cxgb_proc_cleanup(struct proc_dir_entry *dir) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(proc_files); ++i) ++ remove_proc_entry(proc_files[i].name, dir); ++ remove_proc_entry("filters", dir); ++} ++ ++static void clear_qset_stats(struct sge_qset *qs) ++{ ++ qs->rspq.empty = 0; ++ qs->fl[0].empty = 0; ++ qs->fl[1].empty = 0; ++ qs->txq[0].stops = 0; ++ qs->txq[0].restarts = 0; ++ qs->txq[1].stops = 0; ++ qs->txq[1].restarts = 0; ++ qs->txq[2].stops = 0; ++ qs->txq[2].restarts = 0; ++ qs->rspq.eth_pkts = 0; ++ qs->port_stats[SGE_PSTAT_TX_COALESCE_WR] = 0; ++ qs->port_stats[SGE_PSTAT_TX_COALESCE_PKT] = 0; ++ qs->port_stats[SGE_PSTAT_LRO] = 0; ++ qs->port_stats[SGE_PSTAT_LRO_PG] = 0; ++ qs->port_stats[SGE_PSTAT_LRO_SKB] = 0; ++ qs->port_stats[SGE_PSTAT_LRO_ACK] = 0; ++ qs->port_stats[SGE_PSTAT_LRO_OVFLOW] = 0; ++ qs->port_stats[SGE_PSTAT_LRO_COLSN] = 0; ++ qs->rspq.offload_pkts = 0; ++ qs->rspq.offload_bundles = 0; ++ qs->rspq.pure_rsps = 0; ++ qs->rspq.imm_data = 0; ++ qs->rspq.async_notif = 0; ++ qs->rspq.rx_drops = 0; ++ qs->rspq.nomem = 0; ++ qs->fl[0].alloc_failed = 0; ++ qs->fl[1].alloc_failed = 0; ++ qs->rspq.unhandled_irqs = 0; ++ qs->rspq.starved = 0; ++ qs->rspq.restarted = 0; ++} ++ ++static void clear_port_qset_stats(struct adapter *adap, ++ const struct port_info *pi) ++{ ++ int i; ++ struct sge_qset *qs = &adap->sge.qs[pi->first_qset]; ++ ++ for (i = 0; i < pi->nqsets; i++) ++ clear_qset_stats(qs++); ++} ++ ++#ifndef LINUX_2_4 ++ ++#define ERR(fmt, ...) do {\ ++ printk(KERN_ERR "%s: " fmt "\n", dev->name, ## __VA_ARGS__); \ ++ return -EINVAL; \ ++} while (0) ++ ++/* ++ * Perform device independent validation of offload policy. ++ */ ++static int validate_offload_policy(const struct net_device *dev, ++ const struct ofld_policy_file *f, ++ size_t len) ++{ ++ int i, inst; ++ const u32 *p; ++ const struct ofld_prog_inst *pi; ++ ++ /* ++ * We validate the following: ++ * - Program sizes match what's in the header ++ * - Branch targets are within the program ++ * - Offsets do not step outside struct offload_req ++ * - Outputs are valid ++ */ ++ printk(KERN_DEBUG "version %u, program length %zu bytes, alternate " ++ "program length %zu bytes\n", f->vers, ++ f->prog_size * sizeof(*pi), f->opt_prog_size * sizeof(*p)); ++ ++ if (sizeof(*f) + (f->nrules + 1) * sizeof(struct offload_settings) + ++ f->prog_size * sizeof(*pi) + f->opt_prog_size * sizeof(*p) != len) ++ ERR("bad offload policy length %zu", len); ++ ++ if (f->output_everything >= 0 && f->output_everything > f->nrules) ++ ERR("illegal output_everything %d in header", ++ f->output_everything); ++ ++ pi = f->prog; ++ ++ for (i = 0; i < f->prog_size; i++, pi++) { ++ if (pi->offset < 0 || ++ pi->offset >= sizeof(struct offload_req) / 4) ++ ERR("illegal offset %d at instruction %d", pi->offset, ++ i); ++ if (pi->next[0] < 0 && -pi->next[0] > f->nrules) ++ ERR("illegal output %d at instruction %d", ++ -pi->next[0], i); ++ if (pi->next[1] < 0 && -pi->next[1] > f->nrules) ++ ERR("illegal output %d at instruction %d", ++ -pi->next[1], i); ++ if (pi->next[0] > 0 && pi->next[0] >= f->prog_size) ++ ERR("illegal branch target %d at instruction %d", ++ pi->next[0], i); ++ if (pi->next[1] > 0 && pi->next[1] >= f->prog_size) ++ ERR("illegal branch target %d at instruction %d", ++ pi->next[1], i); ++ } ++ ++ p = (const u32 *)pi; ++ ++ for (inst = i = 0; i < f->opt_prog_size; inst++) { ++ unsigned int off = *p & 0xffff, nvals = *p >> 16; ++ ++ if (off >= sizeof(struct offload_req) / 4) ++ ERR("illegal offset %u at opt instruction %d", ++ off, inst); ++ if ((int32_t)p[1] < 0 && -p[1] > f->nrules) ++ ERR("illegal output %d at opt instruction %d", ++ -p[1], inst); ++ if ((int32_t)p[2] < 0 && -p[2] > f->nrules) ++ ERR("illegal output %d at opt instruction %d", ++ -p[2], inst); ++ if ((int32_t)p[1] > 0 && p[1] >= f->opt_prog_size) ++ ERR("illegal branch target %d at opt instruction %d", ++ p[1], inst); ++ if ((int32_t)p[2] > 0 && p[2] >= f->opt_prog_size) ++ ERR("illegal branch target %d at opt instruction %d", ++ p[2], inst); ++ p += 4 + nvals; ++ i += 4 + nvals; ++ if (i > f->opt_prog_size) ++ ERR("too many values %u for opt instruction %d", ++ nvals, inst); ++ } ++ ++ return 0; ++} ++ ++#undef ERR ++ ++/* ++ * Perform T3-specific validation of offload policy settings. ++ */ ++static int validate_policy_settings(const struct net_device *dev, ++ struct adapter *adap, ++ const struct ofld_policy_file *f) ++{ ++ int i, nqsets = 0, nclasses = 8 / adap->params.tp.nchan; ++ const u32 *op = (const u32 *)&f->prog[f->prog_size]; ++ const struct offload_settings *s = (void *)&op[f->opt_prog_size]; ++ ++ for_each_port(adap, i) ++ nqsets += adap2pinfo(adap, i)->nqsets; ++ ++ for (i = 0; i <= f->nrules; i++, s++) { ++ if (s->cong_algo > 3) { ++ printk(KERN_ERR "%s: illegal congestion algorithm %d\n", ++ dev->name, s->cong_algo); ++ return -EINVAL; ++ } ++ if (s->rssq >= nqsets) { ++ printk(KERN_ERR "%s: illegal RSS queue %d\n", dev->name, ++ s->rssq); ++ return -EINVAL; ++ } ++ if (s->sched_class >= nclasses) { ++ printk(KERN_ERR "%s: illegal scheduling class %d\n", ++ dev->name, s->sched_class); ++ return -EINVAL; ++ } ++ if (s->tstamp >= 0) { ++ printk(KERN_ERR "%s: policy rules specifying timestamps" ++ " not supported\n", dev->name); ++ return -EINVAL; ++ } ++ if (s->sack >= 0) { ++ printk(KERN_ERR "%s: policy rules specifying SACK not " ++ "supported\n", dev->name); ++ return -EINVAL; ++ } ++ } ++ return 0; ++} ++ ++#endif /* !LINUX_2_4 */ + + static int in_range(int val, int lo, int hi) + { +@@ -1938,7 +3148,103 @@ + return -EFAULT; + + switch (cmd) { +- case CHELSIO_SET_QSET_PARAMS:{ ++ case CHELSIO_SETREG: { ++ struct ch_reg edata; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ if ((edata.addr & 3) != 0 || edata.addr >= adapter->mmio_len) ++ return -EINVAL; ++ writel(edata.val, adapter->regs + edata.addr); ++ break; ++ } ++ case CHELSIO_GETREG: { ++ struct ch_reg edata; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ if ((edata.addr & 3) != 0 || edata.addr >= adapter->mmio_len) ++ return -EINVAL; ++ edata.val = readl(adapter->regs + edata.addr); ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ break; ++ } ++ case CHELSIO_GETTPI: { ++ struct ch_reg edata; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ret = t3_elmr_blk_read(adapter, edata.addr, &edata.val, 1); ++ if (ret) ++ return ret; ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ break; ++ } ++ case CHELSIO_SETTPI: { ++ struct ch_reg edata; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ret = t3_elmr_blk_write(adapter, edata.addr, &edata.val, 1); ++ if (ret) ++ return ret; ++ break; ++ } ++ case CHELSIO_GET_SGE_CONTEXT: { ++ struct ch_cntxt ecntxt; ++ ++ if (copy_from_user(&ecntxt, useraddr, sizeof(ecntxt))) ++ return -EFAULT; ++ ++ spin_lock_irq(&adapter->sge.reg_lock); ++ if (ecntxt.cntxt_type == CNTXT_TYPE_EGRESS) ++ ret = t3_sge_read_ecntxt(adapter, ecntxt.cntxt_id, ++ ecntxt.data); ++ else if (ecntxt.cntxt_type == CNTXT_TYPE_FL) ++ ret = t3_sge_read_fl(adapter, ecntxt.cntxt_id, ++ ecntxt.data); ++ else if (ecntxt.cntxt_type == CNTXT_TYPE_RSP) ++ ret = t3_sge_read_rspq(adapter, ecntxt.cntxt_id, ++ ecntxt.data); ++ else if (ecntxt.cntxt_type == CNTXT_TYPE_CQ) ++ ret = t3_sge_read_cq(adapter, ecntxt.cntxt_id, ++ ecntxt.data); ++ else ++ ret = -EINVAL; ++ spin_unlock_irq(&adapter->sge.reg_lock); ++ ++ if (ret) ++ return ret; ++ if (copy_to_user(useraddr, &ecntxt, sizeof(ecntxt))) ++ return -EFAULT; ++ break; ++ } ++ case CHELSIO_GET_SGE_DESC: { ++ struct ch_desc edesc; ++ ++ if (copy_from_user(&edesc, useraddr, sizeof(edesc))) ++ return -EFAULT; ++ ++ if (edesc.queue_num >= SGE_QSETS * 6) ++ return -EINVAL; ++ ++ ret = t3_get_desc(&adapter->sge.qs[edesc.queue_num / 6], ++ edesc.queue_num % 6, edesc.idx, edesc.data); ++ if (ret < 0) ++ return ret; ++ edesc.size = ret; ++ ++ if (copy_to_user(useraddr, &edesc, sizeof(edesc))) ++ return -EFAULT; ++ break; ++ } ++ case CHELSIO_SET_QSET_PARAMS: { + int i; + struct qset_params *q; + struct ch_qset_params t; +@@ -1952,20 +3258,18 @@ + if (t.qset_idx >= SGE_QSETS) + return -EINVAL; + if (!in_range(t.intr_lat, 0, M_NEWTIMER) || +- !in_range(t.cong_thres, 0, 255) || +- !in_range(t.txq_size[0], MIN_TXQ_ENTRIES, +- MAX_TXQ_ENTRIES) || +- !in_range(t.txq_size[1], MIN_TXQ_ENTRIES, +- MAX_TXQ_ENTRIES) || +- !in_range(t.txq_size[2], MIN_CTRL_TXQ_ENTRIES, +- MAX_CTRL_TXQ_ENTRIES) || +- !in_range(t.fl_size[0], MIN_FL_ENTRIES, +- MAX_RX_BUFFERS) +- || !in_range(t.fl_size[1], MIN_FL_ENTRIES, +- MAX_RX_JUMBO_BUFFERS) +- || !in_range(t.rspq_size, MIN_RSPQ_ENTRIES, +- MAX_RSPQ_ENTRIES)) +- return -EINVAL; ++ !in_range(t.cong_thres, 0, 255) || ++ !in_range(t.txq_size[0], MIN_TXQ_ENTRIES, ++ MAX_TXQ_ENTRIES) || ++ !in_range(t.txq_size[1], MIN_TXQ_ENTRIES, ++ MAX_TXQ_ENTRIES) || ++ !in_range(t.txq_size[2], MIN_CTRL_TXQ_ENTRIES, ++ MAX_CTRL_TXQ_ENTRIES) || ++ !in_range(t.fl_size[0], MIN_FL_ENTRIES, MAX_RX_BUFFERS) || ++ !in_range(t.fl_size[1], MIN_FL_ENTRIES, ++ MAX_RX_JUMBO_BUFFERS) || ++ !in_range(t.rspq_size, MIN_RSPQ_ENTRIES, MAX_RSPQ_ENTRIES)) ++ return -EINVAL; + + if ((adapter->flags & FULL_INIT_DONE) && t.lro > 0) + for_each_port(adapter, i) { +@@ -1977,10 +3281,10 @@ + } + + if ((adapter->flags & FULL_INIT_DONE) && +- (t.rspq_size >= 0 || t.fl_size[0] >= 0 || +- t.fl_size[1] >= 0 || t.txq_size[0] >= 0 || +- t.txq_size[1] >= 0 || t.txq_size[2] >= 0 || +- t.polling >= 0 || t.cong_thres >= 0)) ++ (t.rspq_size >= 0 || t.fl_size[0] >= 0 || ++ t.fl_size[1] >= 0 || t.txq_size[0] >= 0 || ++ t.txq_size[1] >= 0 || t.txq_size[2] >= 0 || ++ t.polling >= 0 || t.cong_thres >= 0)) + return -EBUSY; + + /* Allow setting of any available qset when offload enabled */ +@@ -1988,7 +3292,7 @@ + q1 = 0; + for_each_port(adapter, i) { + pi = adap2pinfo(adapter, i); +- nqsets += pi->first_qset + pi->nqsets; ++ nqsets = pi->first_qset + pi->nqsets; + } + } + +@@ -2014,8 +3318,7 @@ + if (t.cong_thres >= 0) + q->cong_thres = t.cong_thres; + if (t.intr_lat >= 0) { +- struct sge_qset *qs = +- &adapter->sge.qs[t.qset_idx]; ++ struct sge_qset *qs = &adapter->sge.qs[t.qset_idx]; + + q->coalesce_usecs = t.intr_lat; + t3_update_qset_coalesce(qs, q); +@@ -2026,22 +3329,24 @@ + else { + /* No polling with INTx for T3A */ + if (adapter->params.rev == 0 && +- !(adapter->flags & USING_MSI)) ++ !(adapter->flags & USING_MSI)) + t.polling = 0; + + for (i = 0; i < SGE_QSETS; i++) { +- q = &adapter->params.sge. +- qset[i]; ++ q = &adapter->params.sge.qset[i]; + q->polling = t.polling; + } + } + } +- if (t.lro >= 0) +- set_qset_lro(dev, t.qset_idx, t.lro); +- +- break; +- } +- case CHELSIO_GET_QSET_PARAMS:{ ++ if (t.lro >= 0) { ++ struct sge_qset *qs = &adapter->sge.qs[t.qset_idx]; ++ ++ q->lro = t.lro; ++ qs->lro.enabled = t.lro; ++ } ++ break; ++ } ++ case CHELSIO_GET_QSET_PARAMS: { + struct qset_params *q; + struct ch_qset_params t; + int q1 = pi->first_qset; +@@ -2064,17 +3369,17 @@ + return -EINVAL; + + q = &adapter->params.sge.qset[q1 + t.qset_idx]; +- t.rspq_size = q->rspq_size; ++ t.rspq_size = q->rspq_size; + t.txq_size[0] = q->txq_size[0]; + t.txq_size[1] = q->txq_size[1]; + t.txq_size[2] = q->txq_size[2]; +- t.fl_size[0] = q->fl_size; +- t.fl_size[1] = q->jumbo_size; +- t.polling = q->polling; +- t.lro = q->lro; +- t.intr_lat = q->coalesce_usecs; +- t.cong_thres = q->cong_thres; +- t.qnum = q1; ++ t.fl_size[0] = q->fl_size; ++ t.fl_size[1] = q->jumbo_size; ++ t.polling = q->polling; ++ t.lro = q->lro; ++ t.intr_lat = q->coalesce_usecs; ++ t.cong_thres = q->cong_thres; ++ t.qnum = q1; + + if (adapter->flags & USING_MSIX) + t.vector = adapter->msix_info[q1 + t.qset_idx + 1].vec; +@@ -2085,9 +3390,9 @@ + return -EFAULT; + break; + } +- case CHELSIO_SET_QSET_NUM:{ +- struct ch_reg edata; +- unsigned int i, first_qset = 0, other_qsets = 0; ++ case CHELSIO_SET_QSET_NUM: { ++ struct ch_reg edata; ++ unsigned int i, first_qset = 0, other_qsets; + + if (!capable(CAP_NET_ADMIN)) + return -EPERM; +@@ -2096,17 +3401,15 @@ + if (copy_from_user(&edata, useraddr, sizeof(edata))) + return -EFAULT; + if (edata.val < 1 || +- (edata.val > 1 && !(adapter->flags & USING_MSIX))) +- return -EINVAL; +- +- for_each_port(adapter, i) +- if (adapter->port[i] && adapter->port[i] != dev) +- other_qsets += adap2pinfo(adapter, i)->nqsets; +- ++ (edata.val > 1 && !(adapter->flags & USING_MSIX))) ++ return -EINVAL; ++ ++ other_qsets = adapter->sge.nqsets - pi->nqsets; + if (edata.val + other_qsets > SGE_QSETS) + return -EINVAL; + + pi->nqsets = edata.val; ++ adapter->sge.nqsets = other_qsets + pi->nqsets; + + for_each_port(adapter, i) + if (adapter->port[i]) { +@@ -2116,7 +3419,7 @@ + } + break; + } +- case CHELSIO_GET_QSET_NUM:{ ++ case CHELSIO_GET_QSET_NUM: { + struct ch_reg edata; + + edata.cmd = CHELSIO_GET_QSET_NUM; +@@ -2125,21 +3428,22 @@ + return -EFAULT; + break; + } +- case CHELSIO_LOAD_FW:{ ++ case CHELSIO_LOAD_FW: { + u8 *fw_data; + struct ch_mem_range t; + +- if (!capable(CAP_SYS_RAWIO)) +- return -EPERM; +- if (copy_from_user(&t, useraddr, sizeof(t))) +- return -EFAULT; +- /* Check t.len sanity ? */ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (copy_from_user(&t, useraddr, sizeof(t))) ++ return -EFAULT; ++ if (!t.len) ++ return -EINVAL; ++ + fw_data = kmalloc(t.len, GFP_KERNEL); + if (!fw_data) + return -ENOMEM; + +- if (copy_from_user +- (fw_data, useraddr + sizeof(t), t.len)) { ++ if (copy_from_user(fw_data, useraddr + sizeof(t), t.len)) { + kfree(fw_data); + return -EFAULT; + } +@@ -2150,7 +3454,157 @@ + return ret; + break; + } +- case CHELSIO_SETMTUTAB:{ ++ case CHELSIO_LOAD_BOOT: { ++ u8 *boot_data; ++ struct ch_mem_range t; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (copy_from_user(&t, useraddr, sizeof(t))) ++ return -EFAULT; ++ ++ boot_data = kmalloc(t.len, GFP_KERNEL); ++ if (!boot_data) ++ return -ENOMEM; ++ ++ if (copy_from_user(boot_data, useraddr + sizeof(t), t.len)) { ++ kfree(boot_data); ++ return -EFAULT; ++ } ++ ++ ret = t3_load_boot(adapter, boot_data, t.len); ++ kfree(boot_data); ++ if (ret) ++ return ret; ++ break; ++ } ++ case CHELSIO_SET_FILTER: { ++ struct ch_filter f; ++ struct filter_info *p; ++ ++ if (!adapter->params.mc5.nfilters) ++ return -EOPNOTSUPP; ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (!(adapter->flags & FULL_INIT_DONE)) ++ return -EAGAIN; /* can still change nfilters */ ++ if (!adapter->filters) ++ return -ENOMEM; ++ if (!cxgb3_filter_toe_mode(adapter, CXGB3_FTM_FILTER)) ++ return -EBUSY; ++ if (copy_from_user(&f, useraddr, sizeof(f))) ++ return -EFAULT; ++ ++ if (f.filter_id >= adapter->params.mc5.nfilters || ++ (f.val.dip && f.mask.dip != 0xffffffff) || ++ (f.val.sport && f.mask.sport != 0xffff) || ++ (f.val.dport && f.mask.dport != 0xffff) || ++ (f.mask.vlan && f.mask.vlan != 0xfff) || ++ (f.mask.vlan_prio && f.mask.vlan_prio != FILTER_NO_VLAN_PRI) || ++ (f.mac_addr_idx != 0xffff && f.mac_addr_idx > 15) || ++ f.qset >= SGE_QSETS || ++ adapter->rrss_map[f.qset] >= RSS_TABLE_SIZE) ++ return -EINVAL; ++ ++ p = &adapter->filters[f.filter_id]; ++ if (p->locked) ++ return -EPERM; ++ ++ p->sip = f.val.sip; ++ p->sip_mask = f.mask.sip; ++ p->dip = f.val.dip; ++ p->sport = f.val.sport; ++ p->dport = f.val.dport; ++ p->vlan = f.mask.vlan ? f.val.vlan : 0xfff; ++ p->vlan_prio = f.mask.vlan_prio ? (f.val.vlan_prio & 6) : ++ FILTER_NO_VLAN_PRI; ++ p->mac_hit = f.mac_hit; ++ p->mac_vld = f.mac_addr_idx != 0xffff; ++ p->mac_idx = f.mac_addr_idx; ++ p->pkt_type = f.proto; ++ p->report_filter_id = f.want_filter_id; ++ p->pass = f.pass; ++ p->rss = f.rss; ++ p->qset = f.qset; ++ ++ ret = set_filter(adapter, f.filter_id, p); ++ if (ret) ++ return ret; ++ p->valid = 1; ++ break; ++ } ++ case CHELSIO_DEL_FILTER: { ++ struct ch_filter f; ++ struct filter_info *p; ++ ++ if (!adapter->params.mc5.nfilters) ++ return -EOPNOTSUPP; ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (!(adapter->flags & FULL_INIT_DONE)) ++ return -EAGAIN; /* can still change nfilters */ ++ if (!adapter->filters) ++ return -ENOMEM; ++ if (!cxgb3_filter_toe_mode(adapter, CXGB3_FTM_FILTER)) ++ return -EBUSY; ++ if (copy_from_user(&f, useraddr, sizeof(f))) ++ return -EFAULT; ++ if (f.filter_id >= adapter->params.mc5.nfilters) ++ return -EINVAL; ++ ++ p = &adapter->filters[f.filter_id]; ++ if (p->locked) ++ return -EPERM; ++ memset(p, 0, sizeof(*p)); ++ p->sip = p->sip_mask = 0xffffffff; ++ p->vlan = 0xfff; ++ p->vlan_prio = FILTER_NO_VLAN_PRI; ++ p->pkt_type = 1; ++ return set_filter(adapter, f.filter_id, p); ++ } ++ ++ case CHELSIO_CLEAR_STATS: { ++ struct ch_reg edata; ++ struct port_info *pi = netdev_priv(dev); ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (!(adapter->flags & FULL_INIT_DONE)) ++ return -EAGAIN; ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ if ((edata.val & STATS_QUEUE) && edata.addr != -1 && ++ edata.addr >= pi->nqsets) ++ return -EINVAL; ++ if (edata.val & STATS_PORT) { ++ spin_lock(&adapter->stats_lock); ++ t3_mac_update_stats(&pi->mac); ++ spin_unlock(&adapter->stats_lock); ++ memset(&pi->mac.stats, 0, sizeof(pi->mac.stats)); ++ clear_sge_port_stats(adapter, pi); ++ } ++ if (edata.val & STATS_QUEUE) { ++ if (edata.addr == -1) ++ clear_port_qset_stats(adapter, pi); ++ else ++ clear_qset_stats(&adapter->sge.qs[edata.addr + ++ pi->first_qset]); ++ } ++ break; ++ } ++ ++ case CHELSIO_DEVUP: ++ if (!is_offload(adapter)) ++ return -EOPNOTSUPP; ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ret = offload_open(dev); ++ if (ret) ++ return ret; ++ ++ break; ++#ifdef CONFIG_CHELSIO_T3_CORE ++ case CHELSIO_SETMTUTAB: { + struct ch_mtus m; + int i; + +@@ -2164,34 +3618,49 @@ + return -EFAULT; + if (m.nmtus != NMTUS) + return -EINVAL; +- if (m.mtus[0] < 81) /* accommodate SACK */ +- return -EINVAL; +- +- /* MTUs must be in ascending order */ ++ if (m.mtus[0] < 81) /* accommodate SACK */ ++ return -EINVAL; ++ ++ // MTUs must be in ascending order + for (i = 1; i < NMTUS; ++i) + if (m.mtus[i] < m.mtus[i - 1]) + return -EINVAL; + + memcpy(adapter->params.mtus, m.mtus, +- sizeof(adapter->params.mtus)); +- break; +- } +- case CHELSIO_GET_PM:{ ++ sizeof(adapter->params.mtus)); ++ break; ++ } ++ case CHELSIO_GETMTUTAB: { ++ struct ch_mtus m; ++ ++ if (!is_offload(adapter)) ++ return -EOPNOTSUPP; ++ ++ memcpy(m.mtus, adapter->params.mtus, sizeof(m.mtus)); ++ m.nmtus = NMTUS; ++ ++ if (copy_to_user(useraddr, &m, sizeof(m))) ++ return -EFAULT; ++ break; ++ } ++#endif /* CONFIG_CHELSIO_T3_CORE */ ++ ++ case CHELSIO_GET_PM: { + struct tp_params *p = &adapter->params.tp; +- struct ch_pm m = {.cmd = CHELSIO_GET_PM }; +- +- if (!is_offload(adapter)) +- return -EOPNOTSUPP; +- m.tx_pg_sz = p->tx_pg_size; ++ struct ch_pm m = { .cmd = CHELSIO_GET_PM }; ++ ++ if (!is_offload(adapter)) ++ return -EOPNOTSUPP; ++ m.tx_pg_sz = p->tx_pg_size; + m.tx_num_pg = p->tx_num_pgs; +- m.rx_pg_sz = p->rx_pg_size; ++ m.rx_pg_sz = p->rx_pg_size; + m.rx_num_pg = p->rx_num_pgs; +- m.pm_total = p->pmtx_size + p->chan_rx_size * p->nchan; ++ m.pm_total = p->pmtx_size + p->chan_rx_size * p->nchan; + if (copy_to_user(useraddr, &m, sizeof(m))) + return -EFAULT; + break; + } +- case CHELSIO_SET_PM:{ ++ case CHELSIO_SET_PM: { + struct ch_pm m; + struct tp_params *p = &adapter->params.tp; + +@@ -2203,11 +3672,11 @@ + return -EBUSY; + if (copy_from_user(&m, useraddr, sizeof(m))) + return -EFAULT; +- if (!is_power_of_2(m.rx_pg_sz) || +- !is_power_of_2(m.tx_pg_sz)) +- return -EINVAL; /* not power of 2 */ ++ if (!m.rx_pg_sz || (m.rx_pg_sz & (m.rx_pg_sz - 1)) || ++ !m.tx_pg_sz || (m.tx_pg_sz & (m.tx_pg_sz - 1))) ++ return -EINVAL; /* not power of 2 */ + if (!(m.rx_pg_sz & 0x14000)) +- return -EINVAL; /* not 16KB or 64KB */ ++ return -EINVAL; /* not 16KB or 64KB */ + if (!(m.tx_pg_sz & 0x1554000)) + return -EINVAL; + if (m.tx_num_pg == -1) +@@ -2217,7 +3686,7 @@ + if (m.tx_num_pg % 24 || m.rx_num_pg % 24) + return -EINVAL; + if (m.rx_num_pg * m.rx_pg_sz > p->chan_rx_size || +- m.tx_num_pg * m.tx_pg_sz > p->chan_tx_size) ++ m.tx_num_pg * m.tx_pg_sz > p->chan_tx_size) + return -EINVAL; + p->rx_pg_size = m.rx_pg_sz; + p->tx_pg_size = m.tx_pg_sz; +@@ -2225,7 +3694,23 @@ + p->tx_num_pgs = m.tx_num_pg; + break; + } +- case CHELSIO_GET_MEM:{ ++ case CHELSIO_READ_TCAM_WORD: { ++ struct ch_tcam_word t; ++ ++ if (!is_offload(adapter)) ++ return -EOPNOTSUPP; ++ if (!(adapter->flags & FULL_INIT_DONE)) ++ return -EIO; /* need MC5 */ ++ if (copy_from_user(&t, useraddr, sizeof(t))) ++ return -EFAULT; ++ ret = t3_read_mc5_range(&adapter->mc5, t.addr, 1, t.buf); ++ if (ret) ++ return ret; ++ if (copy_to_user(useraddr, &t, sizeof(t))) ++ return -EFAULT; ++ break; ++ } ++ case CHELSIO_GET_MEM: { + struct ch_mem_range t; + struct mc7 *mem; + u64 buf[32]; +@@ -2233,7 +3718,7 @@ + if (!is_offload(adapter)) + return -EOPNOTSUPP; + if (!(adapter->flags & FULL_INIT_DONE)) +- return -EIO; /* need the memory controllers */ ++ return -EIO; /* need the memory controllers */ + if (copy_from_user(&t, useraddr, sizeof(t))) + return -EFAULT; + if ((t.addr & 7) || (t.len & 7)) +@@ -2260,14 +3745,12 @@ + * Read 256 bytes at a time as len can be large and we don't + * want to use huge intermediate buffers. + */ +- useraddr += sizeof(t); /* advance to start of buffer */ ++ useraddr += sizeof(t); /* advance to start of buffer */ + while (t.len) { +- unsigned int chunk = +- min_t(unsigned int, t.len, sizeof(buf)); +- +- ret = +- t3_mc7_bd_read(mem, t.addr / 8, chunk / 8, +- buf); ++ unsigned int chunk = min_t(unsigned int, t.len, ++ sizeof(buf)); ++ ++ ret = t3_mc7_bd_read(mem, t.addr / 8, chunk / 8, buf); + if (ret) + return ret; + if (copy_to_user(useraddr, buf, chunk)) +@@ -2278,7 +3761,8 @@ + } + break; + } +- case CHELSIO_SET_TRACE_FILTER:{ ++#ifdef CONFIG_CHELSIO_T3_CORE ++ case CHELSIO_SET_TRACE_FILTER: { + struct ch_trace t; + const struct trace_params *tp; + +@@ -2291,14 +3775,239 @@ + + tp = (const struct trace_params *)&t.sip; + if (t.config_tx) +- t3_config_trace_filter(adapter, tp, 0, +- t.invert_match, +- t.trace_tx); ++ t3_config_trace_filter(adapter, tp, 0, t.invert_match, ++ t.trace_tx); + if (t.config_rx) +- t3_config_trace_filter(adapter, tp, 1, +- t.invert_match, +- t.trace_rx); +- break; ++ t3_config_trace_filter(adapter, tp, 1, t.invert_match, ++ t.trace_rx); ++ break; ++ } ++ case CHELSIO_GET_TRACE_FILTER: { ++ struct ch_trace t; ++ struct ch_trace t1; ++ struct trace_params *tp; ++ int inverted=0, enabled=0; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (!offload_running(adapter)) ++ return -EAGAIN; ++ if (copy_from_user(&t, useraddr, sizeof(t))) ++ return -EFAULT; ++ ++ /* ++ * read the filters into t. ++ */ ++ tp = (struct trace_params *)&t.sip; ++ if (t.config_tx) { ++ t3_query_trace_filter(adapter, tp, 0, &inverted, &enabled); ++ if (inverted) ++ t.invert_match = 1; ++ if (enabled) ++ t.trace_tx = 1; ++ } ++ if (t.config_rx) { ++ if (enabled) ++ tp = (struct trace_params *)&t1.sip; ++ t3_query_trace_filter(adapter, tp, 1, &inverted, &enabled); ++ if (inverted) ++ t.invert_match = 1; ++ if (enabled) ++ t.trace_rx = 1; ++ } ++ if (copy_to_user(useraddr, &t, sizeof(t))) ++ return -EFAULT; ++ break; ++ } ++#endif ++ case CHELSIO_SET_PKTSCHED: { ++ struct ch_pktsched_params p; ++ int port; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (!adapter->open_device_map) ++ return -EAGAIN; /* uP and SGE must be running */ ++ if (copy_from_user(&p, useraddr, sizeof(p))) ++ return -EFAULT; ++ if (!in_range(p.idx, 0, SGE_QSETS-1)) ++ return -EINVAL; ++ ++ /* ++ * Find the port corresponding to the queue set so we can ++ * determine the right transmit channel to use for the ++ * schedule binding. ++ */ ++ ret = -EINVAL; ++ for_each_port(adapter, port) { ++ struct port_info *pi = netdev_priv(adapter->port[port]); ++ if (p.idx >= pi->first_qset && ++ p.idx < pi->first_qset + pi->nqsets) { ++ ret = send_pktsched_cmd(adapter, p.sched, ++ p.idx, p.min, p.max, ++ pi->tx_chan); ++ break; ++ } ++ } ++ if (ret) ++ return ret; ++ break; ++ } ++#ifdef CONFIG_CHELSIO_T3_CORE ++ case CHELSIO_SET_HW_SCHED: { ++ struct ch_hw_sched t; ++ unsigned int ticks_per_usec = core_ticks_per_usec(adapter); ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (!(adapter->flags & FULL_INIT_DONE)) ++ return -EAGAIN; /* need TP to be initialized */ ++ if (copy_from_user(&t, useraddr, sizeof(t))) ++ return -EFAULT; ++ if (t.sched >= NTX_SCHED || !in_range(t.mode, 0, 1) || ++ !in_range(t.channel, 0, 1) || ++ !in_range(t.kbps, 0, 10000000) || ++ !in_range(t.class_ipg, 0, 10000 * 65535 / ticks_per_usec) || ++ !in_range(t.flow_ipg, 0, ++ dack_ticks_to_usec(adapter, 0x7ff))) ++ return -EINVAL; ++ ++ if (t.kbps >= 0) { ++ ret = t3_config_sched(adapter, t.kbps, t.sched); ++ if (ret < 0) ++ return ret; ++ } ++ if (t.class_ipg >= 0) ++ t3_set_sched_ipg(adapter, t.sched, t.class_ipg); ++ if (t.flow_ipg >= 0) { ++ t.flow_ipg *= 1000; /* us -> ns */ ++ t3_set_pace_tbl(adapter, &t.flow_ipg, t.sched, 1); ++ } ++ if (t.mode >= 0) { ++ int bit = 1 << (S_TX_MOD_TIMER_MODE + t.sched); ++ ++ t3_set_reg_field(adapter, A_TP_TX_MOD_QUEUE_REQ_MAP, ++ bit, t.mode ? bit : 0); ++ } ++ if (t.channel >= 0) ++ t3_set_reg_field(adapter, A_TP_TX_MOD_QUEUE_REQ_MAP, ++ 1 << t.sched, t.channel << t.sched); ++ break; ++ } ++#endif /* CONFIG_CHELSIO_T3_CORE */ ++ case CHELSIO_GET_UP_LA: { ++ struct ch_up_la t; ++ int bufsize = LA_ENTRIES * 4; ++ void *labuf; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (copy_from_user(&t, useraddr, sizeof(t))) ++ return -EFAULT; ++ ++ labuf = kmalloc(bufsize, GFP_USER); ++ if (!labuf) ++ return -ENOMEM; ++ ++ ret = t3_get_up_la(adapter, &t.stopped, &t.idx, ++ &t.bufsize, labuf); ++ if (ret) ++ goto out_la; ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &t, sizeof(t))) ++ goto out_la; ++ useraddr += offsetof(struct ch_up_la, data); ++ if (copy_to_user(useraddr, labuf, bufsize)) ++ goto out_la; ++ ret = 0; ++out_la: ++ kfree(labuf); ++ if (ret) ++ return ret; ++ ++ break; ++ } ++ case CHELSIO_GET_UP_IOQS: { ++ struct ch_up_ioqs t; ++ int bufsize = IOQ_ENTRIES * sizeof(struct t3_ioq_entry); ++ void *ioqbuf; ++ u32 *v; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (copy_from_user(&t, useraddr, sizeof(t))) ++ return -EFAULT; ++ ++ bufsize += 4 * 4; /* add room for rx/tx enable/status */ ++ ioqbuf = kmalloc(bufsize, GFP_USER); ++ if (!ioqbuf) ++ return -ENOMEM; ++ ++ ret = t3_get_up_ioqs(adapter, &t.bufsize, ioqbuf); ++ if (ret) ++ goto out_ioq; ++ ++ v = ioqbuf; ++ t.ioq_rx_enable = *v++; ++ t.ioq_tx_enable = *v++; ++ t.ioq_rx_status = *v++; ++ t.ioq_tx_status = *v++; ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &t, sizeof(t))) ++ goto out_ioq; ++ useraddr += offsetof(struct ch_up_ioqs, data); ++ bufsize -= 4 * 4; ++ if (copy_to_user(useraddr, v, bufsize)) ++ goto out_ioq; ++ ret = 0; ++out_ioq: ++ kfree(ioqbuf); ++ if (ret) ++ return ret; ++ ++ break; ++ } ++ case CHELSIO_SET_OFLD_POLICY: { ++#ifdef LINUX_2_4 ++ return -EOPNOTSUPP; ++#else ++ struct ch_mem_range t; ++ struct ofld_policy_file *opf; ++ ++ if (!test_bit(OFFLOAD_DEVMAP_BIT, ++ &adapter->registered_device_map)) ++ return -EOPNOTSUPP; ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (copy_from_user(&t, useraddr, sizeof(t))) ++ return -EFAULT; ++ ++ /* len == 0 removes any existing policy */ ++ if (t.len == 0) { ++ req_set_offload_policy(dev, NULL, 0); ++ break; ++ } ++ ++ opf = kmalloc(t.len, GFP_KERNEL); ++ if (!opf) ++ return -ENOMEM; ++ ++ if (copy_from_user(opf, useraddr + sizeof(t), t.len)) { ++ kfree(opf); ++ return -EFAULT; ++ } ++ ++ ret = validate_offload_policy(dev, opf, t.len); ++ if (!ret) { ++ ret = validate_policy_settings(dev, adapter, opf); ++ if (!ret) ++ ret = req_set_offload_policy(dev, opf, t.len); ++ } ++ kfree(opf); ++ return ret; ++#endif + } + default: + return -EOPNOTSUPP; +@@ -2317,7 +4026,7 @@ + case SIOCGMIIPHY: + data->phy_id = pi->phy.addr; + /* FALLTHRU */ +- case SIOCGMIIREG:{ ++ case SIOCGMIIREG: { + u32 val; + struct cphy *phy = &pi->phy; + +@@ -2330,19 +4039,16 @@ + else if (mmd > MDIO_DEV_VEND2) + return -EINVAL; + +- ret = +- phy->mdio_read(adapter, data->phy_id & 0x1f, +- mmd, data->reg_num, &val); ++ ret = phy->mdio_read(adapter, data->phy_id & 0x1f, mmd, ++ data->reg_num, &val); + } else +- ret = +- phy->mdio_read(adapter, data->phy_id & 0x1f, +- 0, data->reg_num & 0x1f, +- &val); ++ ret = phy->mdio_read(adapter, data->phy_id & 0x1f, 0, ++ data->reg_num & 0x1f, &val); + if (!ret) + data->val_out = val; + break; + } +- case SIOCSMIIREG:{ ++ case SIOCSMIIREG: { + struct cphy *phy = &pi->phy; + + if (!capable(CAP_NET_ADMIN)) +@@ -2356,21 +4062,16 @@ + else if (mmd > MDIO_DEV_VEND2) + return -EINVAL; + +- ret = +- phy->mdio_write(adapter, +- data->phy_id & 0x1f, mmd, +- data->reg_num, +- data->val_in); ++ ret = phy->mdio_write(adapter, data->phy_id & 0x1f, ++ mmd, data->reg_num, data->val_in); + } else +- ret = +- phy->mdio_write(adapter, +- data->phy_id & 0x1f, 0, +- data->reg_num & 0x1f, +- data->val_in); ++ ret = phy->mdio_write(adapter, data->phy_id & 0x1f, 0, ++ data->reg_num & 0x1f, ++ data->val_in); + break; + } + case SIOCCHIOCTL: +- return cxgb_extension_ioctl(dev, req->ifr_data); ++ return cxgb_extension_ioctl(dev, (void *)req->ifr_data); + default: + return -EOPNOTSUPP; + } +@@ -2379,20 +4080,22 @@ + + static int cxgb_change_mtu(struct net_device *dev, int new_mtu) + { +- struct port_info *pi = netdev_priv(dev); +- struct adapter *adapter = pi->adapter; +- int ret; +- +- if (new_mtu < 81) /* accommodate SACK */ ++ struct port_info *pi = netdev_priv(dev); ++ struct adapter *adapter = pi->adapter; ++ int ret; ++ ++ if (new_mtu < 81) /* accommodate SACK */ + return -EINVAL; + if ((ret = t3_mac_set_mtu(&pi->mac, new_mtu))) + return ret; ++ + dev->mtu = new_mtu; + init_port_mtus(adapter); + if (adapter->params.rev == 0 && offload_running(adapter)) + t3_load_mtus(adapter, adapter->params.mtus, + adapter->params.a_wnd, adapter->params.b_wnd, + adapter->port[0]->mtu); ++ + return 0; + } + +@@ -2409,6 +4112,7 @@ + t3_mac_set_address(&pi->mac, 0, dev->dev_addr); + if (offload_running(adapter)) + write_smt_entry(adapter, pi->port_id); ++ + return 0; + } + +@@ -2427,9 +4131,10 @@ + + for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) { + struct sge_rspq *q = &adap->sge.qs[i].rspq; +- +- spin_lock_irq(&q->lock); +- spin_unlock_irq(&q->lock); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&q->lock, flags); ++ spin_unlock_irqrestore(&q->lock, flags); + } + } + +@@ -2439,8 +4144,9 @@ + struct adapter *adapter = pi->adapter; + + pi->vlan_grp = grp; ++ + if (adapter->params.rev > 0) +- t3_set_vlan_accel(adapter, 1 << pi->port_id, grp != NULL); ++ t3_set_vlan_accel(adapter, 1 << pi->tx_chan, grp != NULL); + else { + /* single control for all ports */ + unsigned int i, have_vlans = 0; +@@ -2452,30 +4158,30 @@ + t3_synchronize_rx(adapter, pi); + } + ++static void vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) ++{ ++ /* nothing */ ++} ++ + #ifdef CONFIG_NET_POLL_CONTROLLER + static void cxgb_netpoll(struct net_device *dev) + { + struct port_info *pi = netdev_priv(dev); + struct adapter *adapter = pi->adapter; ++ unsigned long flags; + int qidx; + +- for (qidx = pi->first_qset; qidx < pi->first_qset + pi->nqsets; qidx++) { +- struct sge_qset *qs = &adapter->sge.qs[qidx]; +- void *source; +- +- if (adapter->flags & USING_MSIX) +- source = qs; +- else +- source = adapter; +- +- t3_intr_handler(adapter, qs->rspq.polling) (0, source); +- } ++ local_irq_save(flags); ++ for (qidx = pi->first_qset; qidx < pi->first_qset + pi->nqsets; qidx++) ++ t3_poll_handler(adapter, &adapter->sge.qs[qidx]); ++ local_irq_restore(flags); + } + #endif + + /* + * Periodic accumulation of MAC statistics. + */ ++ + static void mac_stats_update(struct adapter *adapter) + { + int i; +@@ -2499,9 +4205,25 @@ + for_each_port(adapter, i) { + struct net_device *dev = adapter->port[i]; + struct port_info *p = netdev_priv(dev); +- +- if (!(p->phy.caps & SUPPORTED_IRQ) && netif_running(dev)) ++ int link_fault; ++ ++ spin_lock_irq(&adapter->work_lock); ++ link_fault = p->link_fault; ++ spin_unlock_irq(&adapter->work_lock); ++ ++ if (link_fault) { ++ t3_link_fault(adapter, i); ++ continue; ++ } ++ ++ if (!(p->phy.caps & SUPPORTED_LINK_IRQ) && netif_running(dev)) { ++ t3_xgm_intr_disable(adapter, i); ++ t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset); ++ + t3_link_changed(adapter, i); ++ t3_xgm_intr_enable(adapter, i); ++ ++ } + } + } + +@@ -2509,7 +4231,7 @@ + { + int i; + +- if (!rtnl_trylock()) /* synchronize with ifdown */ ++ if (!rtnl_trylock()) /* synchronize with ifdown */ + return; + + for_each_port(adapter, i) { +@@ -2540,29 +4262,79 @@ + rtnl_unlock(); + } + +- +-static void t3_adap_check_task(struct work_struct *work) +-{ +- struct adapter *adapter = container_of(work, struct adapter, +- adap_check_task.work); ++DECLARE_TASK_FUNC(t3_adap_check_task, task_param) ++{ ++ struct adapter *adapter = DELWORK2ADAP(task_param, adap_check_task); + const struct adapter_params *p = &adapter->params; ++ int port; ++ unsigned int v, status, reset; + + adapter->check_task_cnt++; + +- /* Check link status for PHYs without interrupts */ +- if (p->linkpoll_period) +- check_link_status(adapter); ++ check_link_status(adapter); + + /* Accumulate MAC stats if needed */ + if (!p->linkpoll_period || + (adapter->check_task_cnt * p->linkpoll_period) / 10 >= +- p->stats_update_period) { ++ p->stats_update_period) { + mac_stats_update(adapter); + adapter->check_task_cnt = 0; + } + +- if (p->rev == T3_REV_B2) ++ if (p->rev == T3_REV_B2 && p->nports < 4) + check_t3b2_mac(adapter); ++ ++ /* ++ * Scan the XGMAC's to check for various conditions which we want to ++ * monitor in a periodic polling manner rather than via an interrupt ++ * condition. This is used for condions which would otherwise flood ++ * the system with interrupts and we only really need to know that the ++ * conditions are "happening" ... For each condition we count the ++ * detection of the condition and reset it for the next polling loop. ++ */ ++ for_each_port(adapter, port) { ++ struct cmac *mac = &adap2pinfo(adapter, port)->mac; ++ u32 cause; ++ ++ if (mac->multiport) ++ continue; ++ ++ cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset); ++ reset = 0; ++ if (cause & F_RXFIFO_OVERFLOW) { ++ mac->stats.rx_fifo_ovfl++; ++ reset |= F_RXFIFO_OVERFLOW; ++ } ++ ++ t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, reset); ++ } ++ ++ /* ++ * We do the same as above for FL_EMPTY interrupts. ++ */ ++ status = t3_read_reg(adapter, A_SG_INT_CAUSE); ++ reset = 0; ++ ++ if (status & F_FLEMPTY) { ++ int i = 0; ++ struct sge_qset *qs = &adapter->sge.qs[0]; ++ ++ reset |= F_FLEMPTY; ++ ++ v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) & ++ 0xffff; ++ ++ while (v) { ++ qs->fl[i].empty += (v & 1); ++ if (i) ++ qs++; ++ i ^= 1; ++ v >>= 1; ++ } ++ ++ } ++ ++ t3_write_reg(adapter, A_SG_INT_CAUSE, reset); + + /* Schedule the next check update if any port is active. */ + spin_lock_irq(&adapter->work_lock); +@@ -2574,22 +4346,39 @@ + /* + * Processes external (PHY) interrupts in process context. + */ +-static void ext_intr_task(struct work_struct *work) +-{ +- struct adapter *adapter = container_of(work, struct adapter, +- ext_intr_handler_task); +- ++DECLARE_TASK_FUNC(ext_intr_task, task_param) ++{ ++ struct adapter *adapter = WORK2ADAP(task_param, ext_intr_handler_task); ++ unsigned long flags; ++ int i; ++ ++ /* Disable link fault interrupts */ ++ if (adapter->params.nports < 4) { ++ for_each_port(adapter, i) { ++ struct net_device *dev = adapter->port[i]; ++ struct port_info *p = netdev_priv(dev); ++ ++ t3_xgm_intr_disable(adapter, i); ++ t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset); ++ } ++ } + t3_phy_intr_handler(adapter); + ++ /* Re-enable link fault interrupts */ ++ if (adapter->params.nports < 4) { ++ for_each_port(adapter, i) ++ t3_xgm_intr_enable(adapter, i); ++ } ++ + /* Now reenable external interrupts */ +- spin_lock_irq(&adapter->work_lock); ++ spin_lock_irqsave(&adapter->work_lock, flags); + if (adapter->slow_intr_mask) { + adapter->slow_intr_mask |= F_T3DBG; + t3_write_reg(adapter, A_PL_INT_CAUSE0, F_T3DBG); + t3_write_reg(adapter, A_PL_INT_ENABLE0, + adapter->slow_intr_mask); + } +- spin_unlock_irq(&adapter->work_lock); ++ spin_unlock_irqrestore(&adapter->work_lock, flags); + } + + /* +@@ -2613,9 +4402,25 @@ + spin_unlock(&adapter->work_lock); + } + ++void t3_os_link_fault_handler(struct adapter *adapter, int port_id) ++{ ++ struct net_device *netdev = adapter->port[port_id]; ++ struct port_info *pi = netdev_priv(netdev); ++ ++ spin_lock(&adapter->work_lock); ++ pi->link_fault = 1; ++ spin_unlock(&adapter->work_lock); ++} ++ + static int t3_adapter_error(struct adapter *adapter, int reset) + { + int i, ret = 0; ++ ++ if (is_offload(adapter) && ++ test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) { ++ cxgb3_err_notify(&adapter->tdev, OFFLOAD_STATUS_DOWN, 0); ++ offload_close(&adapter->tdev); ++ } + + /* Stop all ports */ + for_each_port(adapter, i) { +@@ -2624,10 +4429,6 @@ + if (netif_running(netdev)) + cxgb_close(netdev); + } +- +- if (is_offload(adapter) && +- test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) +- offload_close(&adapter->tdev); + + /* Stop SGE timers */ + t3_stop_sge_timers(adapter); +@@ -2650,12 +4451,12 @@ + goto err; + } + pci_set_master(adapter->pdev); +- pci_restore_state(adapter->pdev); ++ t3_os_pci_restore_state(adapter); + + /* Free sge resources */ + t3_free_sge_resources(adapter); + +- if (t3_replay_prep_adapter(adapter)) ++ if (t3_reinit_adapter(adapter)) + goto err; + + return 0; +@@ -2680,27 +4481,26 @@ + } + } + } +-} +- +-/* +- * processes a fatal error. +- * Bring the ports down, reset the chip, bring the ports back up. +- */ +-static void fatal_error_task(struct work_struct *work) +-{ +- struct adapter *adapter = container_of(work, struct adapter, +- fatal_error_handler_task); ++ ++ if (is_offload(adapter) && !ofld_disable) ++ cxgb3_err_notify(&adapter->tdev, OFFLOAD_STATUS_UP, 0); ++} ++ ++DECLARE_TASK_FUNC(fatal_error_task, task_param) ++{ ++ struct adapter *adapter = WORK2ADAP(task_param, fatal_error_handler_task); + int err = 0; + + rtnl_lock(); +- err = t3_adapter_error(adapter, 1); +- if (!err) +- err = t3_reenable_adapter(adapter); +- if (!err) +- t3_resume_ports(adapter); ++ if (t3_adapter_error(adapter, 1)) ++ err = 1; ++ else if (t3_reenable_adapter(adapter)) ++ err = 1; ++ else t3_resume_ports(adapter); + + CH_ALERT(adapter, "adapter reset %s\n", err ? "failed" : "succeeded"); + rtnl_unlock(); ++ + } + + void t3_fatal_err(struct adapter *adapter) +@@ -2724,9 +4524,9 @@ + CH_ALERT(adapter, "FW status: 0x%x, 0x%x, 0x%x, 0x%x\n", + fw_status[0], fw_status[1], + fw_status[2], fw_status[3]); +- +-} +- ++} ++ ++#if defined(HAS_EEH) + /** + * t3_io_error_detected - called when PCI error is detected + * @pdev: Pointer to PCI device +@@ -2740,9 +4540,6 @@ + { + struct adapter *adapter = pci_get_drvdata(pdev); + int ret; +- +- if (state == pci_channel_io_perm_failure) +- return PCI_ERS_RESULT_DISCONNECT; + + ret = t3_adapter_error(adapter, 0); + +@@ -2785,27 +4582,30 @@ + .slot_reset = t3_io_slot_reset, + .resume = t3_io_resume, + }; +- +-/* +- * Set the number of qsets based on the number of CPUs and the number of ports, ++#endif ++ ++/* Set the number of qsets based on the number of CPUs and the number of ports, + * not to exceed the number of available qsets, assuming there are enough qsets + * per port in HW. + */ +-static void set_nqsets(struct adapter *adap) ++static inline void set_nqsets(struct adapter *adap) + { + int i, j = 0; + int num_cpus = num_online_cpus(); + int hwports = adap->params.nports; + int nqsets = SGE_QSETS; + +- if (adap->params.rev > 0 && adap->flags & USING_MSIX) { ++ if (!(adap->flags & USING_MSIX)) { ++ /* for now, only support 1 queue set/port in non-MSIX mode */ ++ nqsets = 1; ++ } else if (adap->params.rev > 0 && !singleq && hwports <= 2) { + if (hwports == 2 && + (hwports * nqsets > SGE_QSETS || +- num_cpus >= nqsets / hwports)) ++ num_cpus >= nqsets/hwports)) + nqsets /= hwports; + if (nqsets > num_cpus) + nqsets = num_cpus; +- if (nqsets < 1 || hwports == 4) ++ if (nqsets < 1) + nqsets = 1; + } else + nqsets = 1; +@@ -2815,10 +4615,50 @@ + + pi->first_qset = j; + pi->nqsets = nqsets; +- j = pi->first_qset + nqsets; ++ j += nqsets; + + dev_info(&adap->pdev->dev, + "Port %d using %d queue sets.\n", i, nqsets); ++ } ++ ++ adap->sge.nqsets = j; ++} ++ ++/* ++ * Interrupt handler used to check if MSI/MSI-X works on this platform. ++ */ ++DECLARE_INTR_HANDLER(check_intr_handler, irq, adap, regs) ++{ ++ t3_set_reg_field(adap, A_PL_INT_ENABLE0, F_MI1, 0); ++ return IRQ_HANDLED; ++} ++ ++static void __devinit check_msi(struct adapter *adap) ++{ ++ int vec, mi1; ++ ++ if (!(t3_read_reg(adap, A_PL_INT_CAUSE0) & F_MI1)) ++ return; ++ ++ vec = (adap->flags & USING_MSI) ? adap->pdev->irq : ++ adap->msix_info[0].vec; ++ ++ if (request_irq(vec, check_intr_handler, 0, adap->name, adap)) ++ return; ++ ++ t3_set_reg_field(adap, A_PL_INT_ENABLE0, 0, F_MI1); ++ msleep(10); ++ mi1 = t3_read_reg(adap, A_PL_INT_ENABLE0) & F_MI1; ++ if (mi1) ++ t3_set_reg_field(adap, A_PL_INT_ENABLE0, F_MI1, 0); ++ free_irq(vec, adap); ++ ++ if (mi1) { ++ cxgb_disable_msi(adap); ++ dev_info(&adap->pdev->dev, ++ "the kernel believes that MSI is available on this " ++ "platform\nbut the driver's MSI test has failed. " ++ "Proceeding with INTx interrupts.\n"); + } + } + +@@ -2836,11 +4676,35 @@ + adap->msix_info[i].vec = entries[i].vector; + } else if (err > 0) + dev_info(&adap->pdev->dev, +- "only %d MSI-X vectors left, not using MSI-X\n", err); +- return err; +-} +- +-static void __devinit print_port_info(struct adapter *adap, ++ "only %d MSI-X vectors left, not using MSI-X\n", err); ++ return err; ++} ++ ++#ifdef T3_TRACE ++static void __devinit alloc_trace_bufs(adapter_t *adap) ++{ ++ int i; ++ char s[32]; ++ ++ for (i = 0; i < SGE_QSETS; ++i) { ++ sprintf(s, "sge_q%d", i); ++ adap->tb[i] = t3_trace_alloc(adap->debugfs_root, s, 512); ++ } ++} ++ ++static void free_trace_bufs(adapter_t *adap) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(adap->tb); ++i) ++ t3_trace_free(adap->tb[i]); ++} ++#else ++# define alloc_trace_bufs(adapter) ++# define free_trace_bufs(adapter) ++#endif ++ ++static void __devinit print_port_info(adapter_t *adap, + const struct adapter_info *ai) + { + static const char *pci_variant[] = { +@@ -2864,21 +4728,42 @@ + const struct port_info *pi = netdev_priv(dev); + + if (!test_bit(i, &adap->registered_device_map)) +- continue; ++ continue; + printk(KERN_INFO "%s: %s %s %sNIC (rev %d) %s%s\n", + dev->name, ai->desc, pi->phy.desc, + is_offload(adap) ? "R" : "", adap->params.rev, buf, + (adap->flags & USING_MSIX) ? " MSI-X" : + (adap->flags & USING_MSI) ? " MSI" : ""); +- if (adap->name == dev->name && adap->params.vpd.mclk) ++ if (adap->name == dev->name && adap->params.vpd.mclk) { + printk(KERN_INFO +- "%s: %uMB CM, %uMB PMTX, %uMB PMRX, S/N: %s\n", ++ "%s: %uMB CM, %uMB PMTX, %uMB PMRX\n", + adap->name, t3_mc7_size(&adap->cm) >> 20, + t3_mc7_size(&adap->pmtx) >> 20, +- t3_mc7_size(&adap->pmrx) >> 20, +- adap->params.vpd.sn); +- } +-} ++ t3_mc7_size(&adap->pmrx) >> 20); ++ printk(KERN_INFO ++ "%s: S/N: %s E/C: %s\n", ++ adap->name, adap->params.vpd.sn, ++ adap->params.vpd.ec); ++ } ++ } ++} ++ ++static void touch_bars(struct pci_dev *pdev) ++{ ++#if BITS_PER_LONG < 64 ++ u32 v; ++ ++ pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v); ++ pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v); ++ pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v); ++ pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v); ++ pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v); ++ pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v); ++#endif ++} ++ ++#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | NETIF_F_TSO6 |\ ++ NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) + + static int __devinit init_one(struct pci_dev *pdev, + const struct pci_device_id *ent) +@@ -2889,7 +4774,6 @@ + unsigned long mmio_start, mmio_len; + const struct adapter_info *ai; + struct adapter *adapter = NULL; +- struct port_info *pi; + + if (!version_printed) { + printk(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); +@@ -2905,17 +4789,27 @@ + } + } + +- err = pci_request_regions(pdev, DRV_NAME); +- if (err) { +- /* Just info, some other driver may have claimed the device. */ +- dev_info(&pdev->dev, "cannot obtain PCI resources\n"); +- return err; +- } +- + err = pci_enable_device(pdev); + if (err) { + dev_err(&pdev->dev, "cannot enable PCI device\n"); +- goto out_release_regions; ++ return err; ++ } ++ ++ /* ++ * Can't use pci_request_regions() here because some kernels want to ++ * request the MSI-X BAR in pci_enable_msix. Also no need to request ++ * the doorbell BAR if we are not doing user-space RDMA. ++ * So only request BAR0. ++ */ ++ err = pci_request_region(pdev, 0, DRV_NAME); ++ if (err) { ++ /* ++ * Some other driver may have already claimed the device. ++ * Report the event but do not disable the device. ++ */ ++ printk(KERN_INFO "%s: cannot obtain PCI resources\n", ++ pci_name(pdev)); ++ return err; + } + + if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { +@@ -2924,15 +4818,15 @@ + if (err) { + dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " + "coherent allocations\n"); +- goto out_disable_device; ++ goto out_release_regions; + } + } else if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) { + dev_err(&pdev->dev, "no usable DMA configuration\n"); +- goto out_disable_device; +- } +- ++ goto out_release_regions; ++ } ++ ++ touch_bars(pdev); + pci_set_master(pdev); +- pci_save_state(pdev); + + mmio_start = pci_resource_start(pdev, 0); + mmio_len = pci_resource_len(pdev, 0); +@@ -2941,32 +4835,42 @@ + adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); + if (!adapter) { + err = -ENOMEM; +- goto out_disable_device; +- } ++ goto out_release_regions; ++ } ++ ++ adapter->pdev = pdev; ++ t3_os_pci_save_state(adapter); + + adapter->regs = ioremap_nocache(mmio_start, mmio_len); + if (!adapter->regs) { +- dev_err(&pdev->dev, "cannot map device registers\n"); ++ dev_err(&pdev->dev, ++ "cannot map device registers\n"); + err = -ENOMEM; + goto out_free_adapter; + } + +- adapter->pdev = pdev; + adapter->name = pci_name(pdev); + adapter->msg_enable = dflt_msg_enable; + adapter->mmio_len = mmio_len; +- +- mutex_init(&adapter->mdio_lock); ++ atomic_set(&adapter->filter_toe_mode, CXGB3_FTM_NONE); ++ memset(adapter->rrss_map, 0xff, sizeof(adapter->rrss_map)); ++ INIT_LIST_HEAD(&adapter->adapter_list); ++ spin_lock_init(&adapter->mdio_lock); ++ spin_lock_init(&adapter->elmer_lock); + spin_lock_init(&adapter->work_lock); + spin_lock_init(&adapter->stats_lock); + +- INIT_LIST_HEAD(&adapter->adapter_list); +- INIT_WORK(&adapter->ext_intr_handler_task, ext_intr_task); +- INIT_WORK(&adapter->fatal_error_handler_task, fatal_error_task); +- INIT_DELAYED_WORK(&adapter->adap_check_task, t3_adap_check_task); +- +- for (i = 0; i < ai->nports; ++i) { ++ T3_INIT_WORK(&adapter->ext_intr_handler_task, ++ ext_intr_task, adapter); ++ T3_INIT_WORK(&adapter->fatal_error_handler_task, ++ fatal_error_task, adapter); ++ T3_INIT_DELAYED_WORK(&adapter->adap_check_task, ++ t3_adap_check_task, ++ adapter); ++ ++ for (i = 0; i < ai->nports0 + ai->nports1; ++i) { + struct net_device *netdev; ++ struct port_info *pi; + + netdev = alloc_etherdev(sizeof(struct port_info)); + if (!netdev) { +@@ -2974,6 +4878,7 @@ + goto out_free_dev; + } + ++ SET_MODULE_OWNER(netdev); + SET_NETDEV_DEV(netdev, &pdev->dev); + + adapter->port[i] = netdev; +@@ -2981,21 +4886,31 @@ + pi->adapter = adapter; + pi->rx_csum_offload = 1; + pi->port_id = i; ++ pi->tx_chan = i >= ai->nports0; ++ pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : ++ 2 * i; ++ pi->iscsi_ipv4addr = 0; ++ adapter->rxpkt_map[pi->txpkt_intf] = i; + netif_carrier_off(netdev); + netdev->irq = pdev->irq; + netdev->mem_start = mmio_start; + netdev->mem_end = mmio_start + mmio_len - 1; +- netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; ++ netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; + netdev->features |= NETIF_F_LLTX; + if (pci_using_dac) + netdev->features |= NETIF_F_HIGHDMA; + ++ if (ai->nports0 + ai->nports1 <= 2) // disable TSO on T304 ++ netdev->features |= NETIF_F_TSO; ++ + netdev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; + netdev->vlan_rx_register = vlan_rx_register; ++ netdev->vlan_rx_kill_vid = vlan_rx_kill_vid; + + netdev->open = cxgb_open; + netdev->stop = cxgb_close; + netdev->hard_start_xmit = t3_eth_xmit; ++ netdev->tx_queue_len = 10000; + netdev->get_stats = cxgb_get_stats; + netdev->set_multicast_list = cxgb_set_rxmode; + netdev->do_ioctl = cxgb_ioctl; +@@ -3004,9 +4919,18 @@ + #ifdef CONFIG_NET_POLL_CONTROLLER + netdev->poll_controller = cxgb_netpoll; + #endif +- ++#if !defined(NAPI_UPDATE) ++ netdev->weight = 64; ++#endif + SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops); +- } ++ ++#ifdef GSO_MAX_SIZE ++ netdev->vlan_features = netdev->features & VLAN_FEAT; ++ if (adapter->params.nports > 2) ++ netif_set_gso_max_size(netdev, 32768); ++#endif ++ } ++ adapter->sge.nqsets = i; + + pci_set_drvdata(pdev, adapter); + if (t3_prep_adapter(adapter, ai, 1) < 0) { +@@ -3045,9 +4969,19 @@ + /* Driver's ready. Reflect it on LEDs */ + t3_led_ready(adapter); + ++#ifndef LINUX_2_4 ++ if (cxgb3_debugfs_root) { ++ adapter->debugfs_root = debugfs_create_dir(adapter->name, ++ cxgb3_debugfs_root); ++ if (adapter->debugfs_root) ++ alloc_trace_bufs(adapter); ++ } ++#endif /* LINUX_2_4 */ ++ + if (is_offload(adapter)) { + __set_bit(OFFLOAD_DEVMAP_BIT, &adapter->registered_device_map); + cxgb3_adapter_ofld(adapter); ++ cxgb_proc_setup(adapter, adapter->tdev.proc_dir); + } + + /* See what interrupts we'll be using */ +@@ -3055,28 +4989,31 @@ + adapter->flags |= USING_MSIX; + else if (msi > 0 && pci_enable_msi(pdev) == 0) + adapter->flags |= USING_MSI; ++ if (adapter->flags & (USING_MSIX | USING_MSI)) ++ check_msi(adapter); + + set_nqsets(adapter); + +- err = sysfs_create_group(&adapter->port[0]->dev.kobj, +- &cxgb3_attr_group); ++#ifndef LINUX_2_4 ++ sysfs_create_group(net2kobj(adapter->port[0]), ++ &cxgb3_attr_group); ++#endif /* LINUX_2_4 */ + + print_port_info(adapter, ai); + return 0; + + out_free_dev: + iounmap(adapter->regs); +- for (i = ai->nports - 1; i >= 0; --i) ++ for (i = ai->nports0 + ai->nports1 - 1; i >= 0; --i) + if (adapter->port[i]) + free_netdev(adapter->port[i]); + + out_free_adapter: + kfree(adapter); + +-out_disable_device: ++ out_release_regions: ++ pci_release_region(pdev, 0); + pci_disable_device(pdev); +-out_release_regions: +- pci_release_regions(pdev); + pci_set_drvdata(pdev, NULL); + return err; + } +@@ -3089,59 +5026,105 @@ + int i; + + t3_sge_stop(adapter); +- sysfs_remove_group(&adapter->port[0]->dev.kobj, ++#ifndef LINUX_2_4 ++ sysfs_remove_group(net2kobj(adapter->port[0]), + &cxgb3_attr_group); ++#endif /* LINUX_2_4 */ + + if (is_offload(adapter)) { +- cxgb3_adapter_unofld(adapter); ++ cxgb_proc_cleanup(adapter->tdev.proc_dir); + if (test_bit(OFFLOAD_DEVMAP_BIT, + &adapter->open_device_map)) + offload_close(&adapter->tdev); +- } +- +- for_each_port(adapter, i) +- if (test_bit(i, &adapter->registered_device_map)) +- unregister_netdev(adapter->port[i]); ++ cxgb3_adapter_unofld(adapter); ++ } ++ ++ for_each_port(adapter, i) { ++ if (test_bit(i, &adapter->registered_device_map)) { ++ unregister_netdev(adapter->port[i]); ++ } ++ } + + t3_stop_sge_timers(adapter); + t3_free_sge_resources(adapter); ++ if (adapter->filters) ++ free_mem(adapter->filters); + cxgb_disable_msi(adapter); + ++ if (adapter->debugfs_root) { ++ free_trace_bufs(adapter); ++#ifndef LINUX_2_4 ++ debugfs_remove(adapter->debugfs_root); ++#endif /* LINUX_2_4 */ ++ } ++ ++#if !defined(NAPI_UPDATE) ++ for (i = 0; i < ARRAY_SIZE(adapter->dummy_netdev); i++) ++ if (adapter->dummy_netdev[i]) { ++ free_netdev(adapter->dummy_netdev[i]); ++ adapter->dummy_netdev[i] = NULL; ++ } ++#endif + for_each_port(adapter, i) + if (adapter->port[i]) + free_netdev(adapter->port[i]); + + iounmap(adapter->regs); + kfree(adapter); +- pci_release_regions(pdev); ++ pci_release_region(pdev, 0); + pci_disable_device(pdev); + pci_set_drvdata(pdev, NULL); + } + } + + static struct pci_driver driver = { +- .name = DRV_NAME, ++ .name = DRV_NAME, + .id_table = cxgb3_pci_tbl, +- .probe = init_one, +- .remove = __devexit_p(remove_one), ++ .probe = init_one, ++ .remove = __devexit_p(remove_one), ++#if defined(HAS_EEH) + .err_handler = &t3_err_handler, ++#endif ++ + }; + + static int __init cxgb3_init_module(void) + { + int ret; + ++#ifndef LINUX_2_4 ++ /* Debugfs support is optional, just warn if this fails */ ++ cxgb3_debugfs_root = debugfs_create_dir(DRV_NAME, NULL); ++ if (!cxgb3_debugfs_root) ++ printk(KERN_WARNING DRV_NAME ++ ": could not create debugfs entry, continuing\n"); ++#endif /* LINUX_2_4 */ ++ + cxgb3_offload_init(); + + ret = pci_register_driver(&driver); ++ ++#ifndef LINUX_2_4 ++ if (ret < 0) ++ debugfs_remove(cxgb3_debugfs_root); ++#else ++ if (ret > 0) ++ ret = 0; ++#endif /* LINUX_2_4 */ + return ret; + } + + static void __exit cxgb3_cleanup_module(void) + { + pci_unregister_driver(&driver); +- if (cxgb3_wq) ++ if (cxgb3_wq) { + destroy_workqueue(cxgb3_wq); ++ cxgb3_wq = NULL; ++ } ++#ifndef LINUX_2_4 ++ debugfs_remove(cxgb3_debugfs_root); /* NULL ok */ ++#endif /* LINUX_2_4 */ ++ cxgb3_offload_exit(); + } + + module_init(cxgb3_init_module); +diff -r c6413c34aa41 drivers/net/cxgb3/cxgb3_offload.c +--- a/drivers/net/cxgb3/cxgb3_offload.c Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/cxgb3_offload.c Tue Oct 06 09:37:59 2009 +0100 +@@ -1,44 +1,27 @@ + /* +- * Copyright (c) 2006-2007 Chelsio, Inc. All rights reserved. ++ * This file is part of the Chelsio T3 Ethernet driver for Linux. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. + * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ + + #include +-#include + #include + #include + #include + #include +-#include + #include + #include ++#include ++#include ++ ++#if defined(CONFIG_XEN) && defined(CONFIG_XEN_TOE) ++#include ++#endif + + #include "common.h" + #include "regs.h" +@@ -49,6 +32,11 @@ + #include "firmware_exports.h" + #include "cxgb3_offload.h" + ++#include "cxgb3_compat.h" ++#if defined(NETEVENT) ++#include ++#endif ++ + static LIST_HEAD(client_list); + static LIST_HEAD(ofld_dev_list); + static DEFINE_MUTEX(cxgb3_db_lock); +@@ -56,15 +44,76 @@ + static DEFINE_RWLOCK(adapter_list_lock); + static LIST_HEAD(adapter_list); + ++#ifndef RAW_NOTIFIER_HEAD ++# define RAW_NOTIFIER_HEAD(name) struct notifier_block *name ++# define raw_notifier_call_chain notifier_call_chain ++# define raw_notifier_chain_register notifier_chain_register ++# define raw_notifier_chain_unregister notifier_chain_unregister ++#endif ++ ++static RAW_NOTIFIER_HEAD(offload_error_notify_list); ++static DEFINE_MUTEX(notify_mutex); ++ ++int register_offload_error_notifier(struct notifier_block *nb) ++{ ++ int err; ++ ++ mutex_lock(¬ify_mutex); ++ err = raw_notifier_chain_register(&offload_error_notify_list, nb); ++ mutex_unlock(¬ify_mutex); ++ return err; ++} ++EXPORT_SYMBOL(register_offload_error_notifier); ++ ++int unregister_offload_error_notifier(struct notifier_block *nb) ++{ ++ int err; ++ ++ mutex_lock(¬ify_mutex); ++ err = raw_notifier_chain_unregister(&offload_error_notify_list, nb); ++ mutex_unlock(¬ify_mutex); ++ return err; ++} ++EXPORT_SYMBOL(unregister_offload_error_notifier); ++ ++#ifdef LINUX_2_4 ++static unsigned int MAX_ATIDS = 64 * 1024; ++#else + static const unsigned int MAX_ATIDS = 64 * 1024; ++#endif /* LINUX_2_4 */ + static const unsigned int ATID_BASE = 0x10000; ++ ++static struct proc_dir_entry *cxgb3_proc_root; + + static inline int offload_activated(struct t3cdev *tdev) + { +- const struct adapter *adapter = tdev2adap(tdev); ++ struct adapter *adapter = tdev2adap(tdev); + ++ if (!cxgb3_filter_toe_mode(adapter, CXGB3_FTM_TOE)) { ++ int i; ++ printk(KERN_WARNING "Offload services disabled for adapter %s:" ++ " filters in use; ports:\n", tdev->name); ++ for_each_port(adapter, i) { ++ struct net_device *dev = adapter->port[i]; ++ printk(KERN_WARNING " %d: %s\n", i, dev->name); ++ } ++ return 0; ++ } + return (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)); + } ++ ++int offload_error_notification(struct net_device *netdev, unsigned long error) ++{ ++ struct t3cdev *tdev = dev2t3cdev(netdev); ++ ++ if (offload_activated(tdev)) { ++ mutex_lock(¬ify_mutex); ++ raw_notifier_call_chain(&offload_error_notify_list, error, tdev); ++ mutex_unlock(¬ify_mutex); ++ } ++ return 0; ++} ++EXPORT_SYMBOL(offload_error_notification); + + /** + * cxgb3_register_client - register an offload client +@@ -88,7 +137,6 @@ + } + mutex_unlock(&cxgb3_db_lock); + } +- + EXPORT_SYMBOL(cxgb3_register_client); + + /** +@@ -113,11 +161,19 @@ + } + mutex_unlock(&cxgb3_db_lock); + } +- + EXPORT_SYMBOL(cxgb3_unregister_client); + ++/* Get the t3cdev associated with a net_device */ ++struct t3cdev *dev2t3cdev(struct net_device *dev) ++{ ++ const struct port_info *pi = netdev_priv(dev); ++ ++ return (struct t3cdev *)pi->adapter; ++} ++EXPORT_SYMBOL(dev2t3cdev); ++ + /** +- * cxgb3_add_clients - activate registered clients for an offload device ++ * cxgb3_add_clients - activate register clients for an offload device + * @tdev: the offload device + * + * Call backs all registered clients once a offload device is activated +@@ -135,8 +191,7 @@ + } + + /** +- * cxgb3_remove_clients - deactivates registered clients +- * for an offload device ++ * cxgb3_remove_clients - activate register clients for an offload device + * @tdev: the offload device + * + * Call backs all registered clients once a offload device is deactivated +@@ -153,7 +208,118 @@ + mutex_unlock(&cxgb3_db_lock); + } + +-static struct net_device *get_iff_from_mac(struct adapter *adapter, ++/** ++ * cxgb3_err_notify - notifies a device failure to the registered clients ++ * @tdev: the offload device ++ * @status: H/W status: up or down ++ * @error: error identifier ++ * ++ * Call backs all registered clients if the ASIC gets reset on a fatal error ++ */ ++void cxgb3_err_notify(struct t3cdev *tdev, u32 status, u32 error) ++{ ++ struct cxgb3_client *client; ++ ++ mutex_lock(&cxgb3_db_lock); ++ list_for_each_entry(client, &client_list, client_list) { ++ /* ++ * restricted to TOM at this point, ++ * until iSCSI and iWARP catch up ++ */ ++ if (client->name && strcmp(client->name, "tom_cxgb3") == 0 && ++ client->err_handler) ++ client->err_handler(tdev, status, error); ++ } ++ mutex_unlock(&cxgb3_db_lock); ++} ++ ++#if defined(CONFIG_XEN) && defined(CONFIG_XEN_TOE) ++/** ++ * is_vif - return TRUE if a device is a Xen virtual interface (VIF) ++ * @dev: the device to test for VIF status ... ++ * ++ * N.B. Xen virtual interfaces (VIFs) have a few distinguishing ++ * features that we can use to try to determine whether we're ++ * looking at one. Unfortunately there's noting _really_ defined ++ * for them so this is just a hueristic and we probably ought to ++ * think about a better predicate. For right now we look for a ++ * name of "vif*" and a MAC address of fe:ff:ff:ff:ff:ff ... ++ */ ++static int is_vif(struct net_device *dev) ++{ ++ const char vifname[3] = "vif"; ++ const char vifmac[ETH_ALEN] = { 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff }; ++ ++ return (memcmp(dev->name, vifname, sizeof(vifname)) == 0 && ++ memcmp(dev->dev_addr, vifmac, ETH_ALEN) == 0); ++} ++ ++/** ++ * is_xenbrpif - return TRUE if we have the pysical interface (PIF) ++ * for a Xen bridge (XENBR) ++ * ++ * @xenbr: the Xen bridge net device ++ * @pif: the physical interface net device ++ * ++ * Search a Xen bridge's port interface list for the specified ++ * physical interface (PIF). Return TRUE if found, FALSE ++ * otherwise. There should be only a single PIF in a Xen bridge; ++ * if we find more than one we're not looking at a standard Xen ++ * bridge used to proxy for a PIF and we return FALSE. ++ */ ++static int is_xenbrpif(struct net_device *xenbr, ++ struct net_device *pif) ++{ ++ struct net_bridge *br = netdev_priv(xenbr); ++ struct net_bridge_port *port; ++ ++ list_for_each_entry(port, &br->port_list, list) { ++ struct net_device *portdev = port->dev; ++ if (!is_vif(portdev)) ++ return (portdev == pif); ++ } ++ return 0; ++} ++#endif ++ ++#if defined(NETEVENT) || defined(OFLD_USE_KPROBES) ++static struct t3cdev * dev2tdev(struct net_device *dev) ++{ ++ struct adapter *adapter; ++ int port, found = 0; ++ struct net_device *curdev = NULL; ++ ++ if (!dev) ++ return NULL; ++ ++ read_lock(&adapter_list_lock); ++ list_for_each_entry(adapter, &adapter_list, adapter_list) { ++ for_each_port(adapter, port) { ++ curdev = adapter->port[port]; ++ if (dev->flags & IFF_MASTER && ++ curdev->flags & IFF_SLAVE) ++ found = curdev->master == dev; ++#if defined(CONFIG_XEN) && defined(CONFIG_XEN_TOE) ++ else if (dev->priv_flags & IFF_EBRIDGE) ++ found = is_xenbrpif(dev, curdev); ++#endif ++ else if (dev->priv_flags & IFF_802_1Q_VLAN) ++ found = vlan_dev_real_dev(dev) == curdev; ++ else ++ found = dev == curdev; ++ ++ if (found) ++ goto out; ++ } ++ } ++out: ++ read_unlock(&adapter_list_lock); ++ ++ return found ? dev2t3cdev(curdev) : NULL; ++} ++#endif ++ ++static struct net_device *get_iff_from_mac(adapter_t *adapter, + const unsigned char *mac, + unsigned int vlan) + { +@@ -167,10 +333,14 @@ + if (!memcmp(dev->dev_addr, mac, ETH_ALEN)) { + if (vlan && vlan != VLAN_VID_MASK) { + grp = p->vlan_grp; +- dev = NULL; +- if (grp) +- dev = vlan_group_get_device(grp, vlan); +- } else ++ dev = grp ? vlan_group_get_device(grp, vlan) : ++ NULL; ++ } ++#if defined(CONFIG_XEN) && defined(CONFIG_XEN_TOE) ++ else if (dev->br_port) ++ dev = dev->br_port->br->dev; ++#endif ++ else + while (dev->master) + dev = dev->master; + return dev; +@@ -179,8 +349,123 @@ + return NULL; + } + +-static int cxgb_ulp_iscsi_ctl(struct adapter *adapter, unsigned int req, +- void *data) ++static inline void failover_fixup(adapter_t *adapter, int port) ++{ ++ struct net_device *dev = adapter->port[port]; ++ struct port_info *p = netdev_priv(dev); ++ struct cmac *mac = &p->mac; ++ ++ if (!netif_running(dev)) { ++ /* Failover triggered by the interface ifdown */ ++ t3_write_reg(adapter, A_XGM_TX_CTRL + mac->offset, ++ F_TXEN); ++ t3_read_reg(adapter, A_XGM_TX_CTRL + mac->offset); ++ } else { ++ /* Failover triggered by the interface link down */ ++ t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); ++ t3_read_reg(adapter, A_XGM_RX_CTRL + mac->offset); ++ t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, ++ F_RXEN); ++ } ++} ++ ++static inline int in_bond(int port, struct bond_ports *bond_ports) ++{ ++ int i; ++ ++ for (i = 0; i < bond_ports->nports; i++) ++ if (port == bond_ports->ports[i]) ++ break; ++ ++ return (i < bond_ports->nports); ++} ++ ++static int t3_4ports_failover(struct adapter *adapter, int event, ++ struct bond_ports *bond_ports) ++{ ++ int port = bond_ports->port; ++ struct t3cdev *tdev = &adapter->tdev; ++ struct l2t_data *d = L2DATA(tdev); ++ struct l2t_entry *e, *end; ++ int nports = 0, port_idx; ++ ++ /* Reassign L2T entries */ ++ switch (event) { ++ case FAILOVER_PORT_RELEASE: ++ case FAILOVER_PORT_DOWN: ++ read_lock_bh(&d->lock); ++ port_idx = 0; ++ nports = bond_ports->nports; ++ for (e = &d->l2tab[1], end = d->rover; ++ e != end; ++e) { ++ int newport; ++ ++ if (e->smt_idx == port) { ++ newport = bond_ports->ports[port_idx]; ++ spin_lock_bh(&e->lock); ++ e->smt_idx = newport; ++ if (e->state == L2T_STATE_VALID) ++ t3_l2t_update_l2e(tdev, e); ++ spin_unlock_bh(&e->lock); ++ port_idx = port_idx < nports ? ++ port_idx + 1 : 0; ++ } ++ /* ++ * If the port is released, update orig_smt_idx ++ * to failed over port. ++ * There are 2 situations: ++ * 1. Port X is the original port and is released. ++ * {orig_smt_idx, smt_idx} follows these steps. ++ * {X, X} -> {X, Y} -> {Y, Y} ++ * 2. Port Z is released, a failover from port X ++ * had happened previously. ++ * {orig_smt_idx, smt_idx} follows these steps: ++ * {X, Z} -> {Z, Z} ++ */ ++ if (event == FAILOVER_PORT_RELEASE && ++ e->orig_smt_idx == port) { ++ spin_lock_bh(&e->lock); ++ e->orig_smt_idx = e->smt_idx; ++ spin_unlock_bh(&e->lock); ++ } ++ } ++ read_unlock_bh(&d->lock); ++ break; ++ case FAILOVER_PORT_UP: ++ read_lock_bh(&d->lock); ++ for (e = &d->l2tab[1], end = d->rover; ++ e != end; ++e) { ++ if (e->orig_smt_idx == port && ++ in_bond(e->smt_idx, bond_ports)) { ++ spin_lock_bh(&e->lock); ++ e->smt_idx = port; ++ if (e->state == L2T_STATE_VALID) ++ t3_l2t_update_l2e(tdev, e); ++ spin_unlock_bh(&e->lock); ++ } ++ } ++ read_unlock_bh(&d->lock); ++ break; ++ case FAILOVER_ACTIVE_SLAVE: ++ read_lock_bh(&d->lock); ++ for (e = &d->l2tab[1], end = d->rover; ++ e != end; ++e) { ++ if (e->smt_idx != port && ++ in_bond(e->smt_idx, bond_ports)) { ++ spin_lock_bh(&e->lock); ++ e->smt_idx = port; ++ if (e->state == L2T_STATE_VALID) ++ t3_l2t_update_l2e(tdev, e); ++ spin_unlock_bh(&e->lock); ++ } ++ } ++ read_unlock_bh(&d->lock); ++ break; ++ } ++ return 0; ++} ++ ++static int cxgb_ulp_iscsi_ctl(adapter_t *adapter, unsigned int req, void *data) + { + int i; + int ret = 0; +@@ -193,37 +478,56 @@ + uiip->llimit = t3_read_reg(adapter, A_ULPRX_ISCSI_LLIMIT); + uiip->ulimit = t3_read_reg(adapter, A_ULPRX_ISCSI_ULIMIT); + uiip->tagmask = t3_read_reg(adapter, A_ULPRX_ISCSI_TAGMASK); ++ + val = t3_read_reg(adapter, A_ULPRX_ISCSI_PSZ); + for (i = 0; i < 4; i++, val >>= 8) + uiip->pgsz_factor[i] = val & 0xFF; ++ ++ val = t3_read_reg(adapter, A_TP_PARA_REG7); ++ uiip->max_txsz = ++ uiip->max_rxsz = min((val >> S_PMMAXXFERLEN0)&M_PMMAXXFERLEN0, ++ (val >> S_PMMAXXFERLEN1)&M_PMMAXXFERLEN1); ++ + /* + * On tx, the iscsi pdu has to be <= tx page size and has to + * fit into the Tx PM FIFO. + */ +- uiip->max_txsz = min(adapter->params.tp.tx_pg_size, +- t3_read_reg(adapter, A_PM1_TX_CFG) >> 17); ++ val = min(adapter->params.tp.tx_pg_size, ++ t3_read_reg(adapter, A_PM1_TX_CFG) >> 17); ++ uiip->max_txsz = min(val, uiip->max_txsz); ++ ++ /* set max. pdu size (MaxRxData) to 16224 */ ++ val = t3_read_reg(adapter, A_TP_PARA_REG2); ++ if ((val >> S_MAXRXDATA) != 0x3f60) { ++ val &= (M_RXCOALESCESIZE << S_RXCOALESCESIZE); ++ val |= V_MAXRXDATA(0x3f60); ++ printk(KERN_INFO ++ "%s, iscsi set MaxRxData to 16224 (0x%x).\n", ++ adapter->name, val); ++ t3_write_reg(adapter, A_TP_PARA_REG2, val); ++ } ++ + /* + * on rx, the iscsi pdu has to be < rx page size and the + * the max rx data length programmed in TP + */ +- uiip->max_rxsz = min(adapter->params.tp.rx_pg_size, +- ((t3_read_reg(adapter, A_TP_PARA_REG2)) +- >> S_MAXRXDATA) & M_MAXRXDATA); ++ val = min(adapter->params.tp.rx_pg_size, ++ ((t3_read_reg(adapter, A_TP_PARA_REG2)) >> ++ S_MAXRXDATA) & M_MAXRXDATA); ++ uiip->max_rxsz = min(val, uiip->max_rxsz); + break; + case ULP_ISCSI_SET_PARAMS: + t3_write_reg(adapter, A_ULPRX_ISCSI_TAGMASK, uiip->tagmask); +- /* set MaxRxData and MaxCoalesceSize to 16224 */ +- t3_write_reg(adapter, A_TP_PARA_REG2, 0x3f603f60); + /* program the ddp page sizes */ + for (val = 0, i = 0; i < 4; i++) + val |= (uiip->pgsz_factor[i] & 0xF) << (8 * i); + if (val && (val != t3_read_reg(adapter, A_ULPRX_ISCSI_PSZ))) { + printk(KERN_INFO +- "%s, setting iscsi pgsz 0x%x, %u,%u,%u,%u.\n", ++ "%s, setting iscsi pgsz 0x%x, %u,%u,%u,%u.\n", + adapter->name, val, uiip->pgsz_factor[0], + uiip->pgsz_factor[1], uiip->pgsz_factor[2], + uiip->pgsz_factor[3]); +- t3_write_reg(adapter, A_ULPRX_ISCSI_PSZ, val); ++ t3_write_reg(adapter, A_ULPRX_ISCSI_PSZ, val); + } + break; + default: +@@ -235,41 +539,39 @@ + /* Response queue used for RDMA events. */ + #define ASYNC_NOTIF_RSPQ 0 + +-static int cxgb_rdma_ctl(struct adapter *adapter, unsigned int req, void *data) ++static int cxgb_rdma_ctl(adapter_t *adapter, unsigned int req, void *data) + { + int ret = 0; + + switch (req) { + case RDMA_GET_PARAMS: { +- struct rdma_info *rdma = data; ++ struct rdma_info *req = data; + struct pci_dev *pdev = adapter->pdev; + +- rdma->udbell_physbase = pci_resource_start(pdev, 2); +- rdma->udbell_len = pci_resource_len(pdev, 2); +- rdma->tpt_base = +- t3_read_reg(adapter, A_ULPTX_TPT_LLIMIT); +- rdma->tpt_top = t3_read_reg(adapter, A_ULPTX_TPT_ULIMIT); +- rdma->pbl_base = +- t3_read_reg(adapter, A_ULPTX_PBL_LLIMIT); +- rdma->pbl_top = t3_read_reg(adapter, A_ULPTX_PBL_ULIMIT); +- rdma->rqt_base = t3_read_reg(adapter, A_ULPRX_RQ_LLIMIT); +- rdma->rqt_top = t3_read_reg(adapter, A_ULPRX_RQ_ULIMIT); +- rdma->kdb_addr = adapter->regs + A_SG_KDOORBELL; +- rdma->pdev = pdev; ++ req->udbell_physbase = pci_resource_start(pdev, 2); ++ req->udbell_len = pci_resource_len(pdev, 2); ++ req->tpt_base = t3_read_reg(adapter, A_ULPTX_TPT_LLIMIT); ++ req->tpt_top = t3_read_reg(adapter, A_ULPTX_TPT_ULIMIT); ++ req->pbl_base = t3_read_reg(adapter, A_ULPTX_PBL_LLIMIT); ++ req->pbl_top = t3_read_reg(adapter, A_ULPTX_PBL_ULIMIT); ++ req->rqt_base = t3_read_reg(adapter, A_ULPRX_RQ_LLIMIT); ++ req->rqt_top = t3_read_reg(adapter, A_ULPRX_RQ_ULIMIT); ++ req->kdb_addr = adapter->regs + A_SG_KDOORBELL; ++ req->pdev = pdev; + break; + } +- case RDMA_CQ_OP:{ ++ case RDMA_CQ_OP: { + unsigned long flags; +- struct rdma_cq_op *rdma = data; ++ struct rdma_cq_op *req = data; + + /* may be called in any context */ + spin_lock_irqsave(&adapter->sge.reg_lock, flags); +- ret = t3_sge_cqcntxt_op(adapter, rdma->id, rdma->op, +- rdma->credits); ++ ret = t3_sge_cqcntxt_op(adapter, req->id, req->op, ++ req->credits); + spin_unlock_irqrestore(&adapter->sge.reg_lock, flags); + break; + } +- case RDMA_GET_MEM:{ ++ case RDMA_GET_MEM: { + struct ch_mem_range *t = data; + struct mc7 *mem; + +@@ -284,41 +586,41 @@ + else + return -EINVAL; + +- ret = +- t3_mc7_bd_read(mem, t->addr / 8, t->len / 8, +- (u64 *) t->buf); ++ ret = t3_mc7_bd_read(mem, t->addr/8, t->len/8, (u64 *)t->buf); + if (ret) + return ret; + break; + } +- case RDMA_CQ_SETUP:{ +- struct rdma_cq_setup *rdma = data; ++ case RDMA_CQ_SETUP: { ++ struct rdma_cq_setup *req = data; ++ unsigned long flags; + +- spin_lock_irq(&adapter->sge.reg_lock); +- ret = +- t3_sge_init_cqcntxt(adapter, rdma->id, +- rdma->base_addr, rdma->size, +- ASYNC_NOTIF_RSPQ, +- rdma->ovfl_mode, rdma->credits, +- rdma->credit_thres); +- spin_unlock_irq(&adapter->sge.reg_lock); ++ spin_lock_irqsave(&adapter->sge.reg_lock, flags); ++ ret = t3_sge_init_cqcntxt(adapter, req->id, req->base_addr, ++ req->size, ASYNC_NOTIF_RSPQ, ++ req->ovfl_mode, req->credits, ++ req->credit_thres); ++ spin_unlock_irqrestore(&adapter->sge.reg_lock, flags); + break; + } +- case RDMA_CQ_DISABLE: +- spin_lock_irq(&adapter->sge.reg_lock); ++ case RDMA_CQ_DISABLE: { ++ unsigned long flags; ++ ++ spin_lock_irqsave(&adapter->sge.reg_lock, flags); + ret = t3_sge_disable_cqcntxt(adapter, *(unsigned int *)data); +- spin_unlock_irq(&adapter->sge.reg_lock); ++ spin_unlock_irqrestore(&adapter->sge.reg_lock, flags); + break; +- case RDMA_CTRL_QP_SETUP:{ +- struct rdma_ctrlqp_setup *rdma = data; ++ } ++ case RDMA_CTRL_QP_SETUP: { ++ struct rdma_ctrlqp_setup *req = data; ++ unsigned long flags; + +- spin_lock_irq(&adapter->sge.reg_lock); ++ spin_lock_irqsave(&adapter->sge.reg_lock, flags); + ret = t3_sge_init_ecntxt(adapter, FW_RI_SGEEC_START, 0, +- SGE_CNTXT_RDMA, +- ASYNC_NOTIF_RSPQ, +- rdma->base_addr, rdma->size, +- FW_RI_TID_START, 1, 0); +- spin_unlock_irq(&adapter->sge.reg_lock); ++ SGE_CNTXT_RDMA, ASYNC_NOTIF_RSPQ, ++ req->base_addr, req->size, ++ FW_RI_TID_START, 1, 0); ++ spin_unlock_irqrestore(&adapter->sge.reg_lock, flags); + break; + } + case RDMA_GET_MIB: { +@@ -341,9 +643,11 @@ + struct iff_mac *iffmacp; + struct ddp_params *ddpp; + struct adap_ports *ports; ++ struct port_array *pap; + struct ofld_page_info *rx_page_info; + struct tp_params *tp = &adapter->params.tp; +- int i; ++ struct bond_ports *bond_ports; ++ int port; + + switch (req) { + case GET_MAX_OUTSTANDING_WR: +@@ -353,23 +657,47 @@ + *(unsigned int *)data = WR_FLITS; + break; + case GET_TX_MAX_CHUNK: +- *(unsigned int *)data = 1 << 20; /* 1MB */ ++ *(unsigned int *)data = 1 << 20; /* 1MB */ + break; + case GET_TID_RANGE: + tid = data; + tid->num = t3_mc5_size(&adapter->mc5) - +- adapter->params.mc5.nroutes - +- adapter->params.mc5.nfilters - adapter->params.mc5.nservers; ++ adapter->params.mc5.nroutes - ++ adapter->params.mc5.nfilters - ++ adapter->params.mc5.nservers; + tid->base = 0; + break; + case GET_STID_RANGE: + tid = data; + tid->num = adapter->params.mc5.nservers; + tid->base = t3_mc5_size(&adapter->mc5) - tid->num - +- adapter->params.mc5.nfilters - adapter->params.mc5.nroutes; ++ adapter->params.mc5.nfilters - ++ adapter->params.mc5.nroutes; + break; + case GET_L2T_CAPACITY: + *(unsigned int *)data = 2048; ++ break; ++ case GET_CPUIDX_OF_QSET: { ++ unsigned int qset = *(unsigned int *)data; ++ ++ if (qset >= SGE_QSETS || ++ adapter->rrss_map[qset] >= RSS_TABLE_SIZE) ++ return -EINVAL; ++ *(unsigned int *)data = adapter->rrss_map[qset]; ++ break; ++ } ++ case GET_PORT_SCHED: { ++ struct port_sched *p = data; ++ ++ if (adapter->params.nports > 2) { ++ const struct port_info *pi = netdev_priv(p->dev); ++ p->sched = pi->port_id; ++ } else ++ p->sched = -1; ++ break; ++ } ++ case GET_NUM_QUEUES: ++ *(unsigned int *)data = adapter->sge.nqsets; + break; + case GET_MTUS: + mtup = data; +@@ -379,36 +707,45 @@ + case GET_IFF_FROM_MAC: + iffmacp = data; + iffmacp->dev = get_iff_from_mac(adapter, iffmacp->mac_addr, +- iffmacp->vlan_tag & +- VLAN_VID_MASK); ++ iffmacp->vlan_tag & VLAN_VID_MASK); + break; + case GET_DDP_PARAMS: + ddpp = data; + ddpp->llimit = t3_read_reg(adapter, A_ULPRX_TDDP_LLIMIT); + ddpp->ulimit = t3_read_reg(adapter, A_ULPRX_TDDP_ULIMIT); + ddpp->tag_mask = t3_read_reg(adapter, A_ULPRX_TDDP_TAGMASK); ++ ddpp->pdev = adapter->pdev; + break; + case GET_PORTS: + ports = data; +- ports->nports = adapter->params.nports; +- for_each_port(adapter, i) +- ports->lldevs[i] = adapter->port[i]; ++ ports->nports = adapter->params.nports; ++ for_each_port(adapter, port) ++ ports->lldevs[port] = adapter->port[port]; + break; +- case ULP_ISCSI_GET_PARAMS: +- case ULP_ISCSI_SET_PARAMS: +- if (!offload_running(adapter)) +- return -EAGAIN; +- return cxgb_ulp_iscsi_ctl(adapter, req, data); +- case RDMA_GET_PARAMS: +- case RDMA_CQ_OP: +- case RDMA_CQ_SETUP: +- case RDMA_CQ_DISABLE: +- case RDMA_CTRL_QP_SETUP: +- case RDMA_GET_MEM: +- case RDMA_GET_MIB: +- if (!offload_running(adapter)) +- return -EAGAIN; +- return cxgb_rdma_ctl(adapter, req, data); ++ case GET_PORT_ARRAY: ++ pap = data; ++ pap->nports = adapter->params.nports; ++ pap->lldevs = adapter->port; ++ break; ++ case FAILOVER: ++ port = *(int *)data; ++ t3_port_failover(adapter, port); ++ failover_fixup(adapter, !port); ++ break; ++ case FAILOVER_DONE: ++ port = *(int *)data; ++ t3_failover_done(adapter, port); ++ break; ++ case FAILOVER_CLEAR: ++ t3_failover_clear(adapter); ++ break; ++ case FAILOVER_ACTIVE_SLAVE: ++ case FAILOVER_PORT_DOWN: ++ case FAILOVER_PORT_UP: ++ case FAILOVER_PORT_RELEASE: ++ bond_ports = data; ++ t3_4ports_failover(adapter, req, bond_ports); ++ break; + case GET_RX_PAGE_INFO: + rx_page_info = data; + rx_page_info->page_size = tp->rx_pg_size; +@@ -426,6 +763,31 @@ + pi->iscsi_ipv4addr = p->ipv4addr; + break; + } ++ case ULP_ISCSI_GET_PARAMS: ++ case ULP_ISCSI_SET_PARAMS: ++ if (!offload_running(adapter)) ++ return -EAGAIN; ++ return cxgb_ulp_iscsi_ctl(adapter, req, data); ++ case RDMA_GET_PARAMS: ++ case RDMA_CQ_OP: ++ case RDMA_CQ_SETUP: ++ case RDMA_CQ_DISABLE: ++ case RDMA_CTRL_QP_SETUP: ++ case RDMA_GET_MEM: ++ case RDMA_GET_MIB: ++ if (!offload_running(adapter)) ++ return -EAGAIN; ++ return cxgb_rdma_ctl(adapter, req, data); ++ case GET_EMBEDDED_INFO: { ++ struct ch_embedded_info *e = data; ++ ++ spin_lock(&adapter->stats_lock); ++ t3_get_fw_version(adapter, &e->fw_vers); ++ t3_get_tp_version(adapter, &e->tp_vers); ++ spin_unlock(&adapter->stats_lock); ++ ++ break; ++} + default: + return -EOPNOTSUPP; + } +@@ -441,7 +803,7 @@ + int n) + { + while (n--) +- dev_kfree_skb_any(skbs[n]); ++ kfree_skb(skbs[n]); + return 0; + } + +@@ -451,7 +813,7 @@ + + void cxgb3_set_dummy_ops(struct t3cdev *dev) + { +- dev->recv = rx_offload_blackhole; ++ dev->recv = rx_offload_blackhole; + dev->neigh_update = dummy_neigh_update; + } + +@@ -465,6 +827,8 @@ + void *ctx = p->t3c_tid.ctx; + + spin_lock_bh(&t->atid_lock); ++ p->t3c_tid.ctx = NULL; ++ p->t3c_tid.client = NULL; + p->next = t->afree; + t->afree = p; + t->atids_in_use--; +@@ -472,7 +836,6 @@ + + return ctx; + } +- + EXPORT_SYMBOL(cxgb3_free_atid); + + /* +@@ -484,16 +847,17 @@ + union listen_entry *p = stid2entry(t, stid); + + spin_lock_bh(&t->stid_lock); ++ p->t3c_tid.ctx = NULL; ++ p->t3c_tid.client = NULL; + p->next = t->sfree; + t->sfree = p; + t->stids_in_use--; + spin_unlock_bh(&t->stid_lock); + } +- + EXPORT_SYMBOL(cxgb3_free_stid); + + void cxgb3_insert_tid(struct t3cdev *tdev, struct cxgb3_client *client, +- void *ctx, unsigned int tid) ++ void *ctx, unsigned int tid) + { + struct tid_info *t = &(T3C_DATA(tdev))->tid_maps; + +@@ -501,7 +865,6 @@ + t->tid_tab[tid].ctx = ctx; + atomic_inc(&t->tids_in_use); + } +- + EXPORT_SYMBOL(cxgb3_insert_tid); + + /* +@@ -517,13 +880,11 @@ + OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); + } + +-static void t3_process_tid_release_list(struct work_struct *work) ++DECLARE_TASK_FUNC(t3_process_tid_release_list, task_param) + { +- struct t3c_data *td = container_of(work, struct t3c_data, +- tid_release_task); + struct sk_buff *skb; ++ struct t3c_data *td = WORK2T3CDATA(task_param, tid_release_task); + struct t3cdev *tdev = td->dev; +- + + spin_lock_bh(&td->tid_release_lock); + while (td->tid_release_list) { +@@ -534,6 +895,7 @@ + + skb = alloc_skb(sizeof(struct cpl_tid_release), + GFP_KERNEL | __GFP_NOFAIL); ++ + mk_tid_release(skb, p - td->tid_maps.tid_tab); + cxgb3_ofld_send(tdev, skb); + p->ctx = NULL; +@@ -556,7 +918,6 @@ + schedule_work(&td->tid_release_task); + spin_unlock_bh(&td->tid_release_lock); + } +- + EXPORT_SYMBOL(cxgb3_queue_tid_release); + + /* +@@ -577,7 +938,7 @@ + struct sk_buff *skb; + + skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); +- if (likely(skb)) { ++ if (likely(skb != NULL)) { + mk_tid_release(skb, tid); + cxgb3_ofld_send(tdev, skb); + t->tid_tab[tid].ctx = NULL; +@@ -586,7 +947,6 @@ + } + atomic_dec(&t->tids_in_use); + } +- + EXPORT_SYMBOL(cxgb3_remove_tid); + + int cxgb3_alloc_atid(struct t3cdev *tdev, struct cxgb3_client *client, +@@ -610,7 +970,6 @@ + spin_unlock_bh(&t->atid_lock); + return atid; + } +- + EXPORT_SYMBOL(cxgb3_alloc_atid); + + int cxgb3_alloc_stid(struct t3cdev *tdev, struct cxgb3_client *client, +@@ -632,18 +991,7 @@ + spin_unlock_bh(&t->stid_lock); + return stid; + } +- + EXPORT_SYMBOL(cxgb3_alloc_stid); +- +-/* Get the t3cdev associated with a net_device */ +-struct t3cdev *dev2t3cdev(struct net_device *dev) +-{ +- const struct port_info *pi = netdev_priv(dev); +- +- return (struct t3cdev *)pi->adapter; +-} +- +-EXPORT_SYMBOL(dev2t3cdev); + + static int do_smt_write_rpl(struct t3cdev *dev, struct sk_buff *skb) + { +@@ -692,11 +1040,11 @@ + t3c_tid->client->handlers && + t3c_tid->client->handlers[CPL_ACT_OPEN_RPL]) { + return t3c_tid->client->handlers[CPL_ACT_OPEN_RPL] (dev, skb, +- t3c_tid-> +- ctx); ++ t3c_tid->ctx); + } else { +- printk(KERN_ERR "%s: received clientless CPL command 0x%x\n", +- dev->name, CPL_ACT_OPEN_RPL); ++ CH_MSG(tdev2adap(dev), DEBUG, OFLD, ++ "%s: received clientless CPL command 0x%x\n", ++ dev->name, CPL_ACT_OPEN_RPL); + return CPL_RET_BUF_DONE | CPL_RET_BAD_MSG; + } + } +@@ -706,15 +1054,23 @@ + union opcode_tid *p = cplhdr(skb); + unsigned int stid = G_TID(ntohl(p->opcode_tid)); + struct t3c_tid_entry *t3c_tid; ++ const struct tid_info *t = &(T3C_DATA(dev))->tid_maps; + +- t3c_tid = lookup_stid(&(T3C_DATA(dev))->tid_maps, stid); ++ /* ++ * We get these messages also when setting up HW filters. Throw ++ * those away silently. ++ */ ++ if (stid >= t->stid_base + t->nstids) ++ return CPL_RET_BUF_DONE; ++ ++ t3c_tid = lookup_stid(t, stid); + if (t3c_tid && t3c_tid->ctx && t3c_tid->client->handlers && + t3c_tid->client->handlers[p->opcode]) { +- return t3c_tid->client->handlers[p->opcode] (dev, skb, +- t3c_tid->ctx); ++ return t3c_tid->client->handlers[p->opcode] (dev, skb, t3c_tid->ctx); + } else { +- printk(KERN_ERR "%s: received clientless CPL command 0x%x\n", +- dev->name, p->opcode); ++ CH_MSG(tdev2adap(dev), DEBUG, OFLD, ++ "%s: received clientless CPL command 0x%x\n", ++ dev->name, p->opcode); + return CPL_RET_BUF_DONE | CPL_RET_BAD_MSG; + } + } +@@ -727,12 +1083,13 @@ + + t3c_tid = lookup_tid(&(T3C_DATA(dev))->tid_maps, hwtid); + if (t3c_tid && t3c_tid->ctx && t3c_tid->client->handlers && +- t3c_tid->client->handlers[p->opcode]) { ++ t3c_tid->client->handlers[p->opcode]) { + return t3c_tid->client->handlers[p->opcode] +- (dev, skb, t3c_tid->ctx); ++ (dev, skb, t3c_tid->ctx); + } else { +- printk(KERN_ERR "%s: received clientless CPL command 0x%x\n", +- dev->name, p->opcode); ++ CH_MSG(tdev2adap(dev), DEBUG, OFLD, ++ "%s: received clientless CPL command 0x%x\n", ++ dev->name, p->opcode); + return CPL_RET_BUF_DONE | CPL_RET_BAD_MSG; + } + } +@@ -756,10 +1113,11 @@ + if (t3c_tid && t3c_tid->ctx && t3c_tid->client->handlers && + t3c_tid->client->handlers[CPL_PASS_ACCEPT_REQ]) { + return t3c_tid->client->handlers[CPL_PASS_ACCEPT_REQ] +- (dev, skb, t3c_tid->ctx); ++ (dev, skb, t3c_tid->ctx); + } else { +- printk(KERN_ERR "%s: received clientless CPL command 0x%x\n", +- dev->name, CPL_PASS_ACCEPT_REQ); ++ CH_MSG(tdev2adap(dev), DEBUG, OFLD, ++ "%s: received clientless CPL command 0x%x\n", ++ dev->name, CPL_PASS_ACCEPT_REQ); + return CPL_RET_BUF_DONE | CPL_RET_BAD_MSG; + } + } +@@ -772,7 +1130,7 @@ + * the buffer. + */ + static struct sk_buff *cxgb3_get_cpl_reply_skb(struct sk_buff *skb, size_t len, +- gfp_t gfp) ++ int gfp) + { + if (likely(!skb_cloned(skb))) { + BUG_ON(skb->len < len); +@@ -794,9 +1152,9 @@ + + t3c_tid = lookup_tid(&(T3C_DATA(dev))->tid_maps, hwtid); + if (t3c_tid && t3c_tid->ctx && t3c_tid->client->handlers && +- t3c_tid->client->handlers[p->opcode]) { ++ t3c_tid->client->handlers[p->opcode]) { + return t3c_tid->client->handlers[p->opcode] +- (dev, skb, t3c_tid->ctx); ++ (dev, skb, t3c_tid->ctx); + } else { + struct cpl_abort_req_rss *req = cplhdr(skb); + struct cpl_abort_rpl *rpl; +@@ -804,13 +1162,14 @@ + unsigned int tid = GET_TID(req); + u8 cmd = req->status; + ++ WARN_ON(dev->type == T3B); ++ + if (req->status == CPL_ERR_RTX_NEG_ADVICE || + req->status == CPL_ERR_PERSIST_NEG_ADVICE) + goto out; + + reply_skb = cxgb3_get_cpl_reply_skb(skb, +- sizeof(struct +- cpl_abort_rpl), ++ sizeof(struct cpl_abort_rpl), + GFP_ATOMIC); + + if (!reply_skb) { +@@ -818,15 +1177,15 @@ + goto out; + } + reply_skb->priority = CPL_PRIORITY_DATA; +- __skb_put(reply_skb, sizeof(struct cpl_abort_rpl)); + rpl = cplhdr(reply_skb); + rpl->wr.wr_hi = +- htonl(V_WR_OP(FW_WROPCODE_OFLD_HOST_ABORT_CON_RPL)); ++ htonl(V_WR_OP(FW_WROPCODE_OFLD_HOST_ABORT_CON_RPL)); + rpl->wr.wr_lo = htonl(V_WR_TID(tid)); +- OPCODE_TID(rpl) = htonl(MK_OPCODE_TID(CPL_ABORT_RPL, tid)); ++ OPCODE_TID(rpl) = ++ htonl(MK_OPCODE_TID(CPL_ABORT_RPL, tid)); + rpl->cmd = cmd; + cxgb3_ofld_send(dev, reply_skb); +-out: ++ out: + return CPL_RET_BUF_DONE; + } + } +@@ -850,10 +1209,11 @@ + if (t3c_tid && t3c_tid->ctx && t3c_tid->client->handlers && + t3c_tid->client->handlers[CPL_ACT_ESTABLISH]) { + return t3c_tid->client->handlers[CPL_ACT_ESTABLISH] +- (dev, skb, t3c_tid->ctx); ++ (dev, skb, t3c_tid->ctx); + } else { +- printk(KERN_ERR "%s: received clientless CPL command 0x%x\n", +- dev->name, CPL_ACT_ESTABLISH); ++ CH_MSG(tdev2adap(dev), DEBUG, OFLD, ++ "%s: received clientless CPL command 0x%x\n", ++ dev->name, CPL_ACT_ESTABLISH); + return CPL_RET_BUF_DONE | CPL_RET_BAD_MSG; + } + } +@@ -861,74 +1221,279 @@ + static int do_trace(struct t3cdev *dev, struct sk_buff *skb) + { + struct cpl_trace_pkt *p = cplhdr(skb); ++ struct adapter *adapter = tdev2adap(dev); + + skb->protocol = htons(0xffff); + skb->dev = dev->lldev; +- skb_pull(skb, sizeof(*p)); ++ if (adapter->params.nports > 2) ++ skb_pull(skb, sizeof(*p) + 8); /* pull CPL + preamble */ ++ else ++ skb_pull(skb, sizeof(*p)); /* pull CPL */ + skb_reset_mac_header(skb); + netif_receive_skb(skb); + return 0; + } + +-/* +- * That skb would better have come from process_responses() where we abuse +- * ->priority and ->csum to carry our data. NB: if we get to per-arch +- * ->csum, the things might get really interesting here. +- */ +- +-static inline u32 get_hwtid(struct sk_buff *skb) +-{ +- return ntohl((__force __be32)skb->priority) >> 8 & 0xfffff; +-} +- +-static inline u32 get_opcode(struct sk_buff *skb) +-{ +- return G_OPCODE(ntohl((__force __be32)skb->csum)); +-} +- + static int do_term(struct t3cdev *dev, struct sk_buff *skb) + { +- unsigned int hwtid = get_hwtid(skb); +- unsigned int opcode = get_opcode(skb); ++ unsigned int hwtid = ntohl(skb->priority) >> 8 & 0xfffff; ++ unsigned int opcode = G_OPCODE(ntohl(skb->csum)); + struct t3c_tid_entry *t3c_tid; + + t3c_tid = lookup_tid(&(T3C_DATA(dev))->tid_maps, hwtid); + if (t3c_tid && t3c_tid->ctx && t3c_tid->client->handlers && +- t3c_tid->client->handlers[opcode]) { +- return t3c_tid->client->handlers[opcode] (dev, skb, +- t3c_tid->ctx); ++ t3c_tid->client->handlers[opcode]) { ++ return t3c_tid->client->handlers[opcode](dev,skb,t3c_tid->ctx); + } else { +- printk(KERN_ERR "%s: received clientless CPL command 0x%x\n", +- dev->name, opcode); ++ CH_MSG(tdev2adap(dev), DEBUG, OFLD, ++ "%s: received clientless CPL command 0x%x\n", ++ dev->name, opcode); + return CPL_RET_BUF_DONE | CPL_RET_BAD_MSG; + } + } + ++#if defined(NETEVENT) + static int nb_callback(struct notifier_block *self, unsigned long event, +- void *ctx) ++ void *ctx) + { + switch (event) { +- case (NETEVENT_NEIGH_UPDATE):{ +- cxgb_neigh_update((struct neighbour *)ctx); +- break; +- } +- case (NETEVENT_PMTU_UPDATE): +- break; +- case (NETEVENT_REDIRECT):{ +- struct netevent_redirect *nr = ctx; +- cxgb_redirect(nr->old, nr->new); +- cxgb_neigh_update(nr->new->neighbour); +- break; +- } +- default: +- break; ++ case (NETEVENT_NEIGH_UPDATE): { ++ cxgb_neigh_update((struct neighbour *)ctx); ++ break; ++ } ++#ifdef DIVY /* XXX Divy no NETEVENT_ROUTE_UPDATE definition */ ++ case (NETEVENT_ROUTE_UPDATE): ++ break; ++#endif ++ case (NETEVENT_PMTU_UPDATE): ++ break; ++ case (NETEVENT_REDIRECT): { ++ struct netevent_redirect *nr = ctx; ++ cxgb_redirect(nr->old, nr->new); ++ cxgb_neigh_update(nr->new->neighbour); ++ break; ++ } ++ default: ++ break; + } + return 0; + } + ++#elif defined(OFLD_USE_KPROBES) ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++ ++static int (*orig_arp_constructor)(struct neighbour *); ++ ++static void neigh_suspect(struct neighbour *neigh) ++{ ++ struct hh_cache *hh; ++ ++ neigh->output = neigh->ops->output; ++ ++ for (hh = neigh->hh; hh; hh = hh->hh_next) ++ hh->hh_output = neigh->ops->output; ++} ++ ++static void neigh_connect(struct neighbour *neigh) ++{ ++ struct hh_cache *hh; ++ ++ neigh->output = neigh->ops->connected_output; ++ ++ for (hh = neigh->hh; hh; hh = hh->hh_next) ++ hh->hh_output = neigh->ops->hh_output; ++} ++ ++static inline int neigh_max_probes(const struct neighbour *n) ++{ ++ const struct neigh_parms *p = n->parms; ++ return (n->nud_state & NUD_PROBE ? ++ p->ucast_probes : ++ p->ucast_probes + p->app_probes + p->mcast_probes); ++} ++ ++static void neigh_timer_handler_offload(unsigned long arg) ++{ ++ unsigned long now, next; ++ struct neighbour *neigh = (struct neighbour *)arg; ++ unsigned state; ++ int notify = 0; ++ ++ write_lock(&neigh->lock); ++ ++ state = neigh->nud_state; ++ now = jiffies; ++ next = now + HZ; ++ ++ if (!(state & NUD_IN_TIMER)) { ++#ifndef CONFIG_SMP ++ printk(KERN_WARNING "neigh: timer & !nud_in_timer\n"); ++#endif ++ goto out; ++ } ++ ++ if (state & NUD_REACHABLE) { ++ if (time_before_eq(now, ++ neigh->confirmed + ++ neigh->parms->reachable_time)) { ++ next = neigh->confirmed + neigh->parms->reachable_time; ++ } else if (time_before_eq(now, ++ neigh->used + ++ neigh->parms->delay_probe_time)) { ++ neigh->nud_state = NUD_DELAY; ++ neigh->updated = jiffies; ++ neigh_suspect(neigh); ++ next = now + neigh->parms->delay_probe_time; ++ } else { ++ neigh->nud_state = NUD_STALE; ++ neigh->updated = jiffies; ++ neigh_suspect(neigh); ++ cxgb_neigh_update(neigh); ++ } ++ } else if (state & NUD_DELAY) { ++ if (time_before_eq(now, ++ neigh->confirmed + ++ neigh->parms->delay_probe_time)) { ++ neigh->nud_state = NUD_REACHABLE; ++ neigh->updated = jiffies; ++ neigh_connect(neigh); ++ cxgb_neigh_update(neigh); ++ next = neigh->confirmed + neigh->parms->reachable_time; ++ } else { ++ neigh->nud_state = NUD_PROBE; ++ neigh->updated = jiffies; ++ atomic_set(&neigh->probes, 0); ++ next = now + neigh->parms->retrans_time; ++ } ++ } else { ++ /* NUD_PROBE|NUD_INCOMPLETE */ ++ next = now + neigh->parms->retrans_time; ++ } ++ ++ if ((neigh->nud_state & (NUD_INCOMPLETE | NUD_PROBE)) && ++ atomic_read(&neigh->probes) >= neigh_max_probes(neigh)) { ++ struct sk_buff *skb; ++ ++ neigh->nud_state = NUD_FAILED; ++ neigh->updated = jiffies; ++ notify = 1; ++ cxgb_neigh_update(neigh); ++ NEIGH_CACHE_STAT_INC(neigh->tbl, res_failed); ++ ++ /* It is very thin place. report_unreachable is very ++ complicated routine. Particularly, it can hit the same ++ neighbour entry! ++ So that, we try to be accurate and avoid dead loop. --ANK ++ */ ++ while (neigh->nud_state == NUD_FAILED && ++ (skb = __skb_dequeue(&neigh->arp_queue)) != NULL) { ++ write_unlock(&neigh->lock); ++ neigh->ops->error_report(neigh, skb); ++ write_lock(&neigh->lock); ++ } ++ skb_queue_purge(&neigh->arp_queue); ++ } ++ ++ if (neigh->nud_state & NUD_IN_TIMER) { ++ if (time_before(next, jiffies + HZ/2)) ++ next = jiffies + HZ/2; ++ if (!mod_timer(&neigh->timer, next)) ++ neigh_hold(neigh); ++ } ++ if (neigh->nud_state & (NUD_INCOMPLETE | NUD_PROBE)) { ++ struct sk_buff *skb = skb_peek(&neigh->arp_queue); ++ /* keep skb alive even if arp_queue overflows */ ++ if (skb) ++ skb_get(skb); ++ write_unlock(&neigh->lock); ++ neigh->ops->solicit(neigh, skb); ++ atomic_inc(&neigh->probes); ++ if (skb) ++ kfree_skb(skb); ++ } else { ++out: ++ write_unlock(&neigh->lock); ++ } ++ ++#ifdef CONFIG_ARPD ++ if (notify && neigh->parms->app_probes) ++ neigh_app_notify(neigh); ++#endif ++ neigh_release(neigh); ++} ++ ++static int arp_constructor_offload(struct neighbour *neigh) ++{ ++ if (dev2tdev(neigh->dev)) ++ neigh->timer.function = neigh_timer_handler_offload; ++ return orig_arp_constructor(neigh); ++} ++ ++/* ++ * This must match exactly the signature of neigh_update for jprobes to work. ++ * It runs from a trap handler with interrupts off so don't disable BH. ++ */ ++static int neigh_update_offload(struct neighbour *neigh, const u8 *lladdr, ++ u8 new, u32 flags) ++{ ++ write_lock(&neigh->lock); ++ cxgb_neigh_update(neigh); ++ write_unlock(&neigh->lock); ++ jprobe_return(); ++ /* NOTREACHED */ ++ return 0; ++} ++ ++static struct jprobe neigh_update_jprobe = { ++ .entry = (kprobe_opcode_t *) neigh_update_offload, ++ .kp.addr = (kprobe_opcode_t *) neigh_update ++}; ++ ++static int prepare_arp_with_t3core(void) ++{ ++ int err; ++ ++ err = register_jprobe(&neigh_update_jprobe); ++ if (err) { ++ printk(KERN_ERR "Could not install neigh_update jprobe, " ++ "error %d\n", err); ++ return err; ++ } ++ ++ orig_arp_constructor = arp_tbl.constructor; ++ arp_tbl.constructor = arp_constructor_offload; ++ ++ return 0; ++} ++ ++static void restore_arp_sans_t3core(void) ++{ ++ arp_tbl.constructor = orig_arp_constructor; ++ unregister_jprobe(&neigh_update_jprobe); ++} ++ ++#else /* Module suport */ ++ ++static inline int prepare_arp_with_t3core(void) ++{ ++ return 0; ++} ++ ++static inline void restore_arp_sans_t3core(void) ++{} ++#endif ++ ++#if defined(NETEVENT) + static struct notifier_block nb = { + .notifier_call = nb_callback + }; ++#endif + + /* + * Process a received packet with an unknown/unexpected CPL opcode. +@@ -957,7 +1522,6 @@ + printk(KERN_ERR "T3C: handler registration for " + "opcode %x failed\n", opcode); + } +- + EXPORT_SYMBOL(t3_register_cpl_handler); + + /* +@@ -967,7 +1531,7 @@ + { + while (n--) { + struct sk_buff *skb = *skbs++; +- unsigned int opcode = get_opcode(skb); ++ unsigned int opcode = G_OPCODE(ntohl(skb->csum)); + int ret = cpl_handlers[opcode] (dev, skb); + + #if VALIDATE_TID +@@ -993,43 +1557,61 @@ + int r; + + local_bh_disable(); ++#if defined(CONFIG_CHELSIO_T3) ++ if (unlikely(netdev_nit)) { /* deal with active taps */ ++ skb->nh.raw = skb->data; ++ if (!skb->dev) ++ skb->dev = dev->lldev; ++ dev_queue_xmit_nit(skb, skb->dev); ++ } ++#endif + r = dev->send(dev, skb); ++ + local_bh_enable(); + return r; + } +- + EXPORT_SYMBOL(cxgb3_ofld_send); + +-static int is_offloading(struct net_device *dev) ++/** ++ * cxgb3_ofld_skb - process n received offload packets ++ * @dev: the offload device ++ * @skb: an array of offload packets ++ * @n: the number of offload packets ++ * ++ * Process an array of ingress offload packets. Each packet is forwarded ++ * to any active network taps and then passed to the offload device's receive ++ * method. We optimize passing packets to the receive method by passing ++ * it the whole array at once except when there are active taps. ++ */ ++int cxgb3_ofld_recv(struct t3cdev *dev, struct sk_buff **skb, int n) + { +- struct adapter *adapter; +- int i; ++#if defined(CONFIG_CHELSIO_T3) ++ if (likely(!netdev_nit)) ++ return dev->recv(dev, skb, n); + +- read_lock_bh(&adapter_list_lock); +- list_for_each_entry(adapter, &adapter_list, adapter_list) { +- for_each_port(adapter, i) { +- if (dev == adapter->port[i]) { +- read_unlock_bh(&adapter_list_lock); +- return 1; +- } +- } ++ for ( ; n; n--, skb++) { ++ skb[0]->dev = dev->lldev; ++ dev_queue_xmit_nit(skb[0], dev->lldev); ++ skb[0]->dev = NULL; ++ dev->recv(dev, skb, 1); + } +- read_unlock_bh(&adapter_list_lock); + return 0; ++#else ++ return dev->recv(dev, skb, n); ++#endif + } + ++#if defined(NETEVENT) || defined(OFLD_USE_KPROBES) + void cxgb_neigh_update(struct neighbour *neigh) + { +- struct net_device *dev = neigh->dev; ++ struct t3cdev *tdev = dev2tdev(neigh->dev); + +- if (dev && (is_offloading(dev))) { +- struct t3cdev *tdev = dev2t3cdev(dev); ++ if (tdev) ++ t3_l2t_update(tdev, neigh); ++} ++#endif + +- BUG_ON(!tdev); +- t3_l2t_update(tdev, neigh); +- } +-} +- ++#if defined(NETEVENT) + static void set_l2t_ix(struct t3cdev *tdev, u32 tid, struct l2t_entry *e) + { + struct sk_buff *skb; +@@ -1044,7 +1626,7 @@ + req = (struct cpl_set_tcb_field *)skb_put(skb, sizeof(*req)); + req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); + OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid)); +- req->reply = 0; ++ req->reply = V_NO_REPLY(1); + req->cpu_idx = 0; + req->word = htons(W_TCB_L2T_IX); + req->mask = cpu_to_be64(V_TCB_L2T_IX(M_TCB_L2T_IX)); +@@ -1054,33 +1636,32 @@ + + void cxgb_redirect(struct dst_entry *old, struct dst_entry *new) + { +- struct net_device *olddev, *newdev; + struct tid_info *ti; +- struct t3cdev *tdev; ++ struct t3cdev *old_tdev, *new_tdev; + u32 tid; + int update_tcb; + struct l2t_entry *e; + struct t3c_tid_entry *te; + +- olddev = old->neighbour->dev; +- newdev = new->neighbour->dev; +- if (!is_offloading(olddev)) ++ old_tdev = dev2tdev(old->neighbour->dev); ++ new_tdev = dev2tdev(new->neighbour->dev); ++ ++ if (!old_tdev) + return; +- if (!is_offloading(newdev)) { +- printk(KERN_WARNING "%s: Redirect to non-offload " ++ if (new_tdev) { ++ printk(KERN_WARNING "%s: Redirect to non-offload" + "device ignored.\n", __FUNCTION__); + return; + } +- tdev = dev2t3cdev(olddev); +- BUG_ON(!tdev); +- if (tdev != dev2t3cdev(newdev)) { ++ ++ if (old_tdev != new_tdev) { + printk(KERN_WARNING "%s: Redirect to different " + "offload device ignored.\n", __FUNCTION__); + return; + } + + /* Add new L2T entry */ +- e = t3_l2t_get(tdev, new->neighbour, newdev); ++ e = t3_l2t_get(new_tdev, new->neighbour, new->neighbour->dev); + if (!e) { + printk(KERN_ERR "%s: couldn't allocate new l2t entry!\n", + __FUNCTION__); +@@ -1088,20 +1669,61 @@ + } + + /* Walk tid table and notify clients of dst change. */ +- ti = &(T3C_DATA(tdev))->tid_maps; ++ ti = &(T3C_DATA(new_tdev))->tid_maps; + for (tid = 0; tid < ti->ntids; tid++) { + te = lookup_tid(ti, tid); + BUG_ON(!te); + if (te && te->ctx && te->client && te->client->redirect) { +- update_tcb = te->client->redirect(te->ctx, old, new, e); +- if (update_tcb) { +- l2t_hold(L2DATA(tdev), e); +- set_l2t_ix(tdev, tid, e); ++ update_tcb = te->client->redirect(te->ctx, old, new, ++ e); ++ if (update_tcb) { ++ l2t_hold(L2DATA(new_tdev), e); ++ set_l2t_ix(new_tdev, tid, e); + } + } + } +- l2t_release(L2DATA(tdev), e); ++ l2t_release(L2DATA(new_tdev), e); + } ++#endif ++ ++#ifndef LINUX_2_4 ++/* ++ * An administrator has requested that a set of offload policies be attached ++ * to the interface. This functionality is actually managed by toecore and ++ * the new policy will be hung off this net_device's corresponding toedev but ++ * we don't have access to call toecore code. Thus, we need to have one of ++ * our clients -- which can call toecore code -- proxy the call for us. ++ */ ++int req_set_offload_policy(struct net_device *dev, ++ const struct ofld_policy_file *opf, ++ size_t len) ++{ ++ struct cxgb3_client *client; ++ int found = 0; ++ int ret = -EINVAL; ++ ++ mutex_lock(&cxgb3_db_lock); ++ list_for_each_entry(client, &client_list, client_list) { ++ /* ++ * We want to restrict ourself to t3_tom module in order to ++ * request our proxy service since A. it talks to toecore and ++ * B. it's the only module which supports the extended ++ * cxgb3_client data structure and has a set_offload_policy ++ * structure element. ++ */ ++ if (client->name && strcmp(client->name, "tom_cxgb3") == 0 && ++ client->set_offload_policy) { ++ found = 1; ++ ret = client->set_offload_policy(dev, opf, len); ++ break; ++ } ++ } ++ mutex_unlock(&cxgb3_db_lock); ++ if (!found) ++ printk(KERN_ERR "req_set_offload_policy: no proxy found\n"); ++ return ret; ++} ++#endif /* !LINUX_2_4 */ + + /* + * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc. +@@ -1119,14 +1741,71 @@ + } + + /* +- * Free memory allocated through t3_alloc_mem(). ++ * Free memory allocated through cxgb3_alloc_mem(). + */ + void cxgb_free_mem(void *addr) + { +- if (is_vmalloc_addr(addr)) ++ unsigned long p = (unsigned long) addr; ++ ++ if (p >= VMALLOC_START && p < VMALLOC_END) + vfree(addr); + else + kfree(addr); ++} ++ ++static int offload_info_read_proc(char *buf, char **start, off_t offset, ++ int length, int *eof, void *data) ++{ ++ struct t3c_data *d = data; ++ struct tid_info *t = &d->tid_maps; ++ int len; ++ ++ len = sprintf(buf, "TID range: 0..%d, in use: %u\n" ++ "STID range: %d..%d, in use: %u\n" ++ "ATID range: %d..%d, in use: %u\n" ++ "MSS: %u\n", ++ t->ntids - 1, atomic_read(&t->tids_in_use), t->stid_base, ++ t->stid_base + t->nstids - 1, t->stids_in_use, ++ t->atid_base, t->atid_base + t->natids - 1, ++ t->atids_in_use, d->tx_max_chunk); ++ if (len > length) ++ len = length; ++ *eof = 1; ++ return len; ++} ++ ++static int offload_info_proc_setup(struct proc_dir_entry *dir, ++ struct t3c_data *d) ++{ ++ struct proc_dir_entry *p; ++ ++ if (!dir) ++ return -EINVAL; ++ ++ p = create_proc_read_entry("info", 0, dir, offload_info_read_proc, d); ++ if (!p) ++ return -ENOMEM; ++ ++ SET_PROC_NODE_OWNER(p, THIS_MODULE); ++ return 0; ++} ++ ++static void offload_proc_dev_setup(struct t3cdev *dev) ++{ ++ t3_l2t_proc_setup(dev->proc_dir, L2DATA(dev)); ++ offload_info_proc_setup(dev->proc_dir, T3C_DATA(dev)); ++} ++ ++static void offload_info_proc_free(struct proc_dir_entry *dir) ++{ ++ if (dir) ++ remove_proc_entry("info", dir); ++} ++ ++static void offload_proc_dev_cleanup(struct t3cdev *dev) ++{ ++ t3_l2t_proc_free(dev->proc_dir); ++ offload_info_proc_free(dev->proc_dir); + } + + /* +@@ -1178,14 +1857,14 @@ + cxgb_free_mem(t->tid_tab); + } + +-static inline void add_adapter(struct adapter *adap) ++static inline void add_adapter(adapter_t *adap) + { + write_lock_bh(&adapter_list_lock); + list_add_tail(&adap->adapter_list, &adapter_list); + write_unlock_bh(&adapter_list_lock); + } + +-static inline void remove_adapter(struct adapter *adap) ++static inline void remove_adapter(adapter_t *adap) + { + write_lock_bh(&adapter_list_lock); + list_del(&adap->adapter_list); +@@ -1228,19 +1907,29 @@ + t->mtus = mtutab.mtus; + t->nmtus = mtutab.size; + +- INIT_WORK(&t->tid_release_task, t3_process_tid_release_list); + spin_lock_init(&t->tid_release_lock); + INIT_LIST_HEAD(&t->list_node); + t->dev = dev; + + T3C_DATA(dev) = t; + dev->recv = process_rx; ++#if defined(NETEVENT) + dev->neigh_update = t3_l2t_update; ++#endif ++ ++ T3_INIT_WORK(&t->tid_release_task, t3_process_tid_release_list, t); ++ ++ offload_proc_dev_setup(dev); + + /* Register netevent handler once */ +- if (list_empty(&adapter_list)) ++ if (list_empty(&adapter_list)) { ++#if defined(NETEVENT) + register_netevent_notifier(&nb); +- ++#elif defined(OFLD_USE_KPROBES) ++ if (prepare_arp_with_t3core()) ++ printk(KERN_ERR "Unable to set offload capabilities\n"); ++#endif ++ } + add_adapter(adapter); + return 0; + +@@ -1257,15 +1946,44 @@ + struct t3cdev *tdev = &adapter->tdev; + struct t3c_data *t = T3C_DATA(tdev); + ++ offload_proc_dev_cleanup(tdev); + remove_adapter(adapter); +- if (list_empty(&adapter_list)) ++ if (list_empty(&adapter_list)) { ++#if defined(NETEVENT) + unregister_netevent_notifier(&nb); +- ++#else ++#if defined(OFLD_USE_KPROBES) ++ restore_arp_sans_t3core(); ++#endif ++#endif ++ } + free_tid_maps(&t->tid_maps); + T3C_DATA(tdev) = NULL; + t3_free_l2t(L2DATA(tdev)); + L2DATA(tdev) = NULL; + kfree(t); ++} ++ ++static void __devexit offload_proc_dev_exit(struct t3cdev *tdev) ++{ ++ remove_proc_entry(tdev->name, cxgb3_proc_root); ++ tdev->proc_dir = NULL; ++} ++ ++static void __devinit offload_proc_dev_init(struct t3cdev *tdev) ++{ ++ if (!cxgb3_proc_root) { ++ printk("%s: root proc idr is null\n", __func__); ++ return; ++ } ++ ++ tdev->proc_dir = proc_mkdir(tdev->name, cxgb3_proc_root); ++ if (!tdev->proc_dir) { ++ printk(KERN_WARNING "Unable to create /proc/net/cxgb3/%s dir\n", ++ tdev->name); ++ return; ++ } ++ SET_PROC_NODE_OWNER(tdev->proc_dir, THIS_MODULE); + } + + static inline void register_tdev(struct t3cdev *tdev) +@@ -1303,7 +2021,7 @@ + } + return type; + } +- ++ + void __devinit cxgb3_adapter_ofld(struct adapter *adapter) + { + struct t3cdev *tdev = &adapter->tdev; +@@ -1316,16 +2034,77 @@ + tdev->type = adap2type(adapter); + + register_tdev(tdev); ++ offload_proc_dev_init(tdev); + } + + void __devexit cxgb3_adapter_unofld(struct adapter *adapter) + { + struct t3cdev *tdev = &adapter->tdev; + +- tdev->recv = NULL; +- tdev->neigh_update = NULL; ++ offload_proc_dev_exit(tdev); ++ cxgb3_set_dummy_ops(tdev); + + unregister_tdev(tdev); ++} ++ ++static int offload_devices_read_proc(char *buf, char **start, off_t offset, ++ int length, int *eof, void *data) ++{ ++ int i, len = 0; ++ struct t3cdev *tdev; ++ struct net_device *ndev; ++ struct adapter *adapter; ++ ++ len += sprintf(buf, "Device Interfaces\n"); ++ ++ mutex_lock(&cxgb3_db_lock); ++ list_for_each_entry(tdev, &ofld_dev_list, ofld_dev_list) { ++ len += sprintf(buf + len, "%-16s", tdev->name); ++ adapter = tdev2adap(tdev); ++ for (i = 0; i < adapter->params.nports; i++) { ++ ndev = adapter->port[i]; ++ len += sprintf(buf + len, " %s", ndev->name); ++ } ++ len += sprintf(buf + len, "\n"); ++ if (len >= length) ++ break; ++ } ++ mutex_unlock(&cxgb3_db_lock); ++ ++ if (len > length) ++ len = length; ++ *eof = 1; ++ return len; ++} ++ ++static void offload_proc_cleanup(void) ++{ ++ remove_proc_entry("devices", cxgb3_proc_root); ++ remove_proc_entry("cxgb3", INET_PROC_DIR); ++ cxgb3_proc_root = NULL; ++ ++} ++ ++static int offload_proc_init(void) ++{ ++ struct proc_dir_entry *d; ++ ++ cxgb3_proc_root = proc_mkdir("cxgb3", INET_PROC_DIR); ++ if (!cxgb3_proc_root) ++ return -ENOMEM; ++ SET_PROC_NODE_OWNER(cxgb3_proc_root, THIS_MODULE); ++ ++ d = create_proc_read_entry("devices", 0, cxgb3_proc_root, ++ offload_devices_read_proc, NULL); ++ ++ if (!d) ++ goto cleanup; ++ SET_PROC_NODE_OWNER(d, THIS_MODULE); ++ return 0; ++ ++cleanup: ++ offload_proc_cleanup(); ++ return -ENOMEM; + } + + void __init cxgb3_offload_init(void) +@@ -1353,12 +2132,21 @@ + t3_register_cpl_handler(CPL_CLOSE_CON_RPL, do_hwtid_rpl); + t3_register_cpl_handler(CPL_ABORT_REQ_RSS, do_abort_req_rss); + t3_register_cpl_handler(CPL_ACT_ESTABLISH, do_act_establish); +- t3_register_cpl_handler(CPL_SET_TCB_RPL, do_hwtid_rpl); +- t3_register_cpl_handler(CPL_GET_TCB_RPL, do_hwtid_rpl); + t3_register_cpl_handler(CPL_RDMA_TERMINATE, do_term); + t3_register_cpl_handler(CPL_RDMA_EC_STATUS, do_hwtid_rpl); + t3_register_cpl_handler(CPL_TRACE_PKT, do_trace); + t3_register_cpl_handler(CPL_RX_DATA_DDP, do_hwtid_rpl); + t3_register_cpl_handler(CPL_RX_DDP_COMPLETE, do_hwtid_rpl); ++ /* for iSCSI */ + t3_register_cpl_handler(CPL_ISCSI_HDR, do_hwtid_rpl); ++ t3_register_cpl_handler(CPL_GET_TCB_RPL, do_hwtid_rpl); ++ t3_register_cpl_handler(CPL_SET_TCB_RPL, do_hwtid_rpl); ++ ++ if (offload_proc_init()) ++ printk(KERN_WARNING "Unable to create /proc/net/cxgb3 dir\n"); + } ++ ++void __exit cxgb3_offload_exit(void) ++{ ++ offload_proc_cleanup(); ++} +diff -r c6413c34aa41 drivers/net/cxgb3/cxgb3_offload.h +--- a/drivers/net/cxgb3/cxgb3_offload.h Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/cxgb3_offload.h Tue Oct 06 09:37:59 2009 +0100 +@@ -1,40 +1,24 @@ + /* +- * Copyright (c) 2006-2007 Chelsio, Inc. All rights reserved. ++ * This file is part of the Chelsio T3 Ethernet driver for Linux. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. + * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ ++ + #ifndef _CXGB3_OFFLOAD_H + #define _CXGB3_OFFLOAD_H + + #include + #include ++// XXX offload.h not installed into build include directory ++// #include ++#include "offload.h" + ++#include "tcb.h" + #include "l2t.h" + + #include "t3cdev.h" +@@ -43,11 +27,14 @@ + struct adapter; + + void cxgb3_offload_init(void); ++void cxgb3_offload_exit(void); + + void cxgb3_adapter_ofld(struct adapter *adapter); + void cxgb3_adapter_unofld(struct adapter *adapter); + int cxgb3_offload_activate(struct adapter *adapter); + void cxgb3_offload_deactivate(struct adapter *adapter); ++ ++int cxgb3_ofld_recv(struct t3cdev *dev, struct sk_buff **skb, int n); + + void cxgb3_set_dummy_ops(struct t3cdev *dev); + +@@ -64,18 +51,41 @@ + void cxgb3_unregister_client(struct cxgb3_client *client); + void cxgb3_add_clients(struct t3cdev *tdev); + void cxgb3_remove_clients(struct t3cdev *tdev); ++void cxgb3_err_notify(struct t3cdev *tdev, u32 status, u32 error); + + typedef int (*cxgb3_cpl_handler_func)(struct t3cdev *dev, + struct sk_buff *skb, void *ctx); ++enum { ++ OFFLOAD_STATUS_UP, ++ OFFLOAD_STATUS_DOWN ++}; + + struct cxgb3_client { +- char *name; +- void (*add) (struct t3cdev *); +- void (*remove) (struct t3cdev *); +- cxgb3_cpl_handler_func *handlers; +- int (*redirect)(void *ctx, struct dst_entry *old, +- struct dst_entry *new, struct l2t_entry *l2t); +- struct list_head client_list; ++ char *name; ++ void (*add) (struct t3cdev *); ++ void (*remove) (struct t3cdev *); ++ cxgb3_cpl_handler_func *handlers; ++ int (*redirect)(void *ctx, struct dst_entry *old, ++ struct dst_entry *new, ++ struct l2t_entry *l2t); ++ struct list_head client_list; ++ ++ /* ++ * End of legacy cxgb3_client data structure. No part of the above ++ * may be changed. ++ */ ++ ++ /* ++ * Start of t3_tom-extended cxgb3_client data structure. Only t3_tom ++ * has these fields ... ++ */ ++ /* Added in kernel.org */ ++ void (*err_handler)(struct t3cdev *tdev, u32 status, u32 error); ++#ifndef LINUX_2_4 ++ int (*set_offload_policy)(struct net_device *, ++ const struct ofld_policy_file *, ++ size_t); ++#endif + }; + + /* +@@ -88,30 +98,31 @@ + void *cxgb3_free_atid(struct t3cdev *dev, int atid); + void cxgb3_free_stid(struct t3cdev *dev, int stid); + void cxgb3_insert_tid(struct t3cdev *dev, struct cxgb3_client *client, +- void *ctx, unsigned int tid); ++ void *ctx, ++ unsigned int tid); + void cxgb3_queue_tid_release(struct t3cdev *dev, unsigned int tid); + void cxgb3_remove_tid(struct t3cdev *dev, void *ctx, unsigned int tid); + + struct t3c_tid_entry { +- struct cxgb3_client *client; +- void *ctx; ++ struct cxgb3_client *client; ++ void *ctx; + }; + + /* CPL message priority levels */ + enum { +- CPL_PRIORITY_DATA = 0, /* data messages */ +- CPL_PRIORITY_SETUP = 1, /* connection setup messages */ +- CPL_PRIORITY_TEARDOWN = 0, /* connection teardown messages */ +- CPL_PRIORITY_LISTEN = 1, /* listen start/stop messages */ +- CPL_PRIORITY_ACK = 1, /* RX ACK messages */ +- CPL_PRIORITY_CONTROL = 1 /* offload control messages */ ++ CPL_PRIORITY_DATA = 0, /* data messages */ ++ CPL_PRIORITY_SETUP = 1, /* connection setup messages */ ++ CPL_PRIORITY_TEARDOWN = 0, /* connection teardown messages */ ++ CPL_PRIORITY_LISTEN = 1, /* listen start/stop messages */ ++ CPL_PRIORITY_ACK = 1, /* RX ACK messages */ ++ CPL_PRIORITY_CONTROL = 1 /* offload control messages */ + }; + + /* Flags for return value of CPL message handlers */ + enum { +- CPL_RET_BUF_DONE = 1, /* buffer processing done, buffer may be freed */ +- CPL_RET_BAD_MSG = 2, /* bad CPL message (e.g., unknown opcode) */ +- CPL_RET_UNKNOWN_TID = 4 /* unexpected unknown TID */ ++ CPL_RET_BUF_DONE = 1, // buffer processing done, buffer may be freed ++ CPL_RET_BAD_MSG = 2, // bad CPL message (e.g., unknown opcode) ++ CPL_RET_UNKNOWN_TID = 4 // unexpected unknown TID + }; + + typedef int (*cpl_handler_func)(struct t3cdev *dev, struct sk_buff *skb); +@@ -175,8 +186,8 @@ + struct t3c_data { + struct list_head list_node; + struct t3cdev *dev; +- unsigned int tx_max_chunk; /* max payload for TX_DATA */ +- unsigned int max_wrs; /* max in-flight WRs per connection */ ++ unsigned int tx_max_chunk; /* max payload for TX_DATA */ ++ unsigned int max_wrs; /* max in-flight WRs per connection */ + unsigned int nmtus; + const unsigned short *mtus; + struct tid_info tid_maps; +diff -r c6413c34aa41 drivers/net/cxgb3/firmware_exports.h +--- a/drivers/net/cxgb3/firmware_exports.h Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/firmware_exports.h Tue Oct 06 09:37:59 2009 +0100 +@@ -1,33 +1,27 @@ +-/* +- * Copyright (c) 2004-2007 Chelsio, Inc. All rights reserved. ++/* ++ * ---------------------------------------------------------------------------- ++ * >>>>>>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<< ++ * ---------------------------------------------------------------------------- ++ * Copyright 2004-2009 (C) Chelsio Communications, Inc. (Chelsio) + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: ++ * Chelsio Communications, Inc. owns the sole copyright to this software. ++ * You may not make a copy, you may not derive works herefrom, and you may ++ * not distribute this work to others. Other restrictions of rights may apply ++ * as well. This is unpublished, confidential information. All rights reserved. ++ * This software contains confidential information and trade secrets of Chelsio ++ * Communications, Inc. Use, disclosure, or reproduction is prohibited without ++ * the prior express written permission of Chelsio Communications, Inc. ++ * ---------------------------------------------------------------------------- ++ * >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> Warranty <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< ++ * ---------------------------------------------------------------------------- ++ * CHELSIO MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THE USE OF THIS ++ * SOFTWARE, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. ++ * ---------------------------------------------------------------------------- + * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: ++ * This is the firmware_exports.h header file, firmware interface defines. + * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * Written January 2005 by felix marti (felix@chelsio.com) + */ + #ifndef _FIRMWARE_EXPORTS_H_ + #define _FIRMWARE_EXPORTS_H_ +@@ -75,15 +69,18 @@ + + #define FW_WROPCODE_MNGT 0x1D + #define FW_MNGTOPCODE_PKTSCHED_SET 0x00 ++#define FW_MNGTOPCODE_WRC_SET 0x01 ++#define FW_MNGTOPCODE_TUNNEL_CR_FLUSH 0x02 + +-/* Maximum size of a WR sent from the host, limited by the SGE. ++ ++/* Maximum size of a WR sent from the host, limited by the SGE. + * +- * Note: WR coming from ULP or TP are only limited by CIM. ++ * Note: WR coming from ULP or TP are only limited by CIM. + */ + #define FW_WR_SIZE 128 + + /* Maximum number of outstanding WRs sent from the host. Value must be +- * programmed in the CTRL/TUNNEL/QP SGE Egress Context and used by ++ * programmed in the CTRL/TUNNEL/QP SGE Egress Context and used by + * offload modules to limit the number of WRs per connection. + */ + #define FW_T3_WR_NUM 16 +@@ -99,27 +96,28 @@ + * queues must start at SGE Egress Context FW_TUNNEL_SGEEC_START and must + * start at 'TID' (or 'uP Token') FW_TUNNEL_TID_START. + * +- * Ingress Traffic (e.g. DMA completion credit) for TUNNEL Queue[i] is sent ++ * Ingress Traffic (e.g. DMA completion credit) for TUNNEL Queue[i] is sent + * to RESP Queue[i]. + */ + #define FW_TUNNEL_NUM 8 + #define FW_TUNNEL_SGEEC_START 8 + #define FW_TUNNEL_TID_START 65544 + ++ + /* FW_CTRL_NUM corresponds to the number of supported CTRL Queues. These queues + * must start at SGE Egress Context FW_CTRL_SGEEC_START and must start at 'TID' + * (or 'uP Token') FW_CTRL_TID_START. + * + * Ingress Traffic for CTRL Queue[i] is sent to RESP Queue[i]. +- */ ++ */ + #define FW_CTRL_NUM 8 + #define FW_CTRL_SGEEC_START 65528 + #define FW_CTRL_TID_START 65536 + +-/* FW_OFLD_NUM corresponds to the number of supported OFFLOAD Queues. These +- * queues must start at SGE Egress Context FW_OFLD_SGEEC_START. +- * +- * Note: the 'uP Token' in the SGE Egress Context fields is irrelevant for ++/* FW_OFLD_NUM corresponds to the number of supported OFFLOAD Queues. These ++ * queues must start at SGE Egress Context FW_OFLD_SGEEC_START. ++ * ++ * Note: the 'uP Token' in the SGE Egress Context fields is irrelevant for + * OFFLOAD Queues, as the host is responsible for providing the correct TID in + * every WR. + * +@@ -136,7 +134,7 @@ + #define FW_RI_TID_START 65552 + + /* +- * The RX_PKT_TID ++ * The RX_PKT_TID + */ + #define FW_RX_PKT_NUM 1 + #define FW_RX_PKT_TID_START 65553 +@@ -174,4 +172,4 @@ + #define G_FW_VERSION_MICRO(x) \ + (((x) >> S_FW_VERSION_MICRO) & M_FW_VERSION_MICRO) + +-#endif /* _FIRMWARE_EXPORTS_H_ */ ++#endif /* _FIRMWARE_EXPORTS_H_ */ +diff -r c6413c34aa41 drivers/net/cxgb3/l2t.c +--- a/drivers/net/cxgb3/l2t.c Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/l2t.c Tue Oct 06 09:38:00 2009 +0100 +@@ -1,41 +1,21 @@ + /* +- * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved. ++ * This file is part of the Chelsio T3 Ethernet driver for Linux. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. + * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ ++ + #include + #include + #include + #include + #include + #include +-#include "common.h" ++#include "cxgb3_compat.h" + #include "t3cdev.h" + #include "cxgb3_defs.h" + #include "l2t.h" +@@ -77,6 +57,23 @@ + e->neigh = n; + } + ++static void setup_l2e(struct t3cdev *dev, struct sk_buff *skb, ++ struct l2t_entry *e) ++{ ++ struct cpl_l2t_write_req *req; ++ ++ req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req)); ++ req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); ++ OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, e->idx)); ++ req->params = htonl(V_L2T_W_IDX(e->idx) | V_L2T_W_IFF(e->smt_idx) | ++ V_L2T_W_VLAN(e->vlan & VLAN_VID_MASK) | ++ V_L2T_W_PRIO(vlan_prio(e))); ++ req->port_idx = e->smt_idx; ++ memcpy(req->dst_mac, e->dmac, sizeof(req->dst_mac)); ++ skb->priority = CPL_PRIORITY_CONTROL; ++ cxgb3_ofld_send(dev, skb); ++} ++ + /* + * Set up an L2T entry and send any packets waiting in the arp queue. The + * supplied skb is used for the CPL_L2T_WRITE_REQ. Must be called with the +@@ -85,24 +82,16 @@ + static int setup_l2e_send_pending(struct t3cdev *dev, struct sk_buff *skb, + struct l2t_entry *e) + { +- struct cpl_l2t_write_req *req; + + if (!skb) { +- skb = alloc_skb(sizeof(*req), GFP_ATOMIC); ++ skb = alloc_skb(sizeof(struct cpl_l2t_write_req), GFP_ATOMIC); + if (!skb) + return -ENOMEM; + } + +- req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req)); +- req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); +- OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, e->idx)); +- req->params = htonl(V_L2T_W_IDX(e->idx) | V_L2T_W_IFF(e->smt_idx) | +- V_L2T_W_VLAN(e->vlan & VLAN_VID_MASK) | +- V_L2T_W_PRIO(vlan_prio(e))); + memcpy(e->dmac, e->neigh->ha, sizeof(e->dmac)); +- memcpy(req->dst_mac, e->dmac, sizeof(req->dst_mac)); +- skb->priority = CPL_PRIORITY_CONTROL; +- cxgb3_ofld_send(dev, skb); ++ setup_l2e(dev, skb, e); ++ + while (e->arpq_head) { + skb = e->arpq_head; + e->arpq_head = skb->next; +@@ -111,6 +100,22 @@ + } + e->arpq_tail = NULL; + e->state = L2T_STATE_VALID; ++ ++ return 0; ++} ++ ++/* ++ * Update an L2T entry. ++ * Must be called with the entry locked. ++ */ ++int t3_l2t_update_l2e(struct t3cdev *dev, struct l2t_entry *e) ++{ ++ struct sk_buff * skb = alloc_skb(sizeof(struct cpl_l2t_write_req), ++ GFP_ATOMIC); ++ if (!skb) ++ return -ENOMEM; ++ ++ setup_l2e(dev, skb, e); + + return 0; + } +@@ -134,18 +139,17 @@ + { + again: + switch (e->state) { +- case L2T_STATE_STALE: /* entry is stale, kick off revalidation */ ++ case L2T_STATE_STALE: /* entry is stale, kick off revalidation */ + neigh_event_send(e->neigh, NULL); + spin_lock_bh(&e->lock); + if (e->state == L2T_STATE_STALE) + e->state = L2T_STATE_VALID; + spin_unlock_bh(&e->lock); +- case L2T_STATE_VALID: /* fast-path, send the packet on */ ++ case L2T_STATE_VALID: /* fast-path, send the packet on */ + return cxgb3_ofld_send(dev, skb); + case L2T_STATE_RESOLVING: + spin_lock_bh(&e->lock); +- if (e->state != L2T_STATE_RESOLVING) { +- /* ARP already completed */ ++ if (e->state != L2T_STATE_RESOLVING) { // ARP already completed + spin_unlock_bh(&e->lock); + goto again; + } +@@ -169,21 +173,20 @@ + spin_lock_bh(&e->lock); + if (e->arpq_head) + setup_l2e_send_pending(dev, skb, e); +- else /* we lost the race */ ++ else /* we lost the race */ + __kfree_skb(skb); + spin_unlock_bh(&e->lock); + } + } + return 0; + } +- + EXPORT_SYMBOL(t3_l2t_send_slow); + + void t3_l2t_send_event(struct t3cdev *dev, struct l2t_entry *e) + { + again: + switch (e->state) { +- case L2T_STATE_STALE: /* entry is stale, kick off revalidation */ ++ case L2T_STATE_STALE: /* entry is stale, kick off revalidation */ + neigh_event_send(e->neigh, NULL); + spin_lock_bh(&e->lock); + if (e->state == L2T_STATE_STALE) { +@@ -191,12 +194,11 @@ + } + spin_unlock_bh(&e->lock); + return; +- case L2T_STATE_VALID: /* fast-path, send the packet on */ ++ case L2T_STATE_VALID: /* fast-path, send the packet on */ + return; + case L2T_STATE_RESOLVING: + spin_lock_bh(&e->lock); +- if (e->state != L2T_STATE_RESOLVING) { +- /* ARP already completed */ ++ if (e->state != L2T_STATE_RESOLVING) { // ARP already completed + spin_unlock_bh(&e->lock); + goto again; + } +@@ -214,7 +216,6 @@ + } + return; + } +- + EXPORT_SYMBOL(t3_l2t_send_event); + + /* +@@ -268,7 +269,7 @@ + void t3_l2e_free(struct l2t_data *d, struct l2t_entry *e) + { + spin_lock_bh(&e->lock); +- if (atomic_read(&e->refcnt) == 0) { /* hasn't been recycled */ ++ if (atomic_read(&e->refcnt) == 0) { /* hasn't been recycled */ + if (e->neigh) { + neigh_release(e->neigh); + e->neigh = NULL; +@@ -277,7 +278,6 @@ + spin_unlock_bh(&e->lock); + atomic_inc(&d->nfree); + } +- + EXPORT_SYMBOL(t3_l2e_free); + + /* +@@ -288,7 +288,7 @@ + { + unsigned int nud_state; + +- spin_lock(&e->lock); /* avoid race with t3_l2t_free */ ++ spin_lock(&e->lock); /* avoid race with t3_l2t_free */ + + if (neigh != e->neigh) + neigh_replace(e, neigh); +@@ -327,13 +327,15 @@ + /* Need to allocate a new entry */ + e = alloc_l2e(d); + if (e) { +- spin_lock(&e->lock); /* avoid race with t3_l2t_free */ ++ spin_lock(&e->lock); /* avoid race with t3_l2t_free */ + e->next = d->l2tab[hash].first; + d->l2tab[hash].first = e; + e->state = L2T_STATE_RESOLVING; + e->addr = addr; + e->ifindex = ifidx; + e->smt_idx = smt_idx; ++ e->orig_smt_idx = smt_idx; ++ e->chan_idx = p->txpkt_intf & 1; + atomic_set(&e->refcnt, 1); + neigh_replace(e, neigh); + if (neigh->dev->priv_flags & IFF_802_1Q_VLAN) +@@ -346,7 +348,6 @@ + write_unlock_bh(&d->lock); + return e; + } +- + EXPORT_SYMBOL(t3_l2t_get); + + /* +@@ -372,6 +373,7 @@ + } + } + ++#if defined(NETEVENT) || !defined(OFLD_USE_KPROBES) + /* + * Called when the host's ARP layer makes a change to some entry that is + * loaded into the HW L2 table. +@@ -408,7 +410,7 @@ + setup_l2e_send_pending(dev, NULL, e); + } else { + e->state = neigh->nud_state & NUD_CONNECTED ? +- L2T_STATE_VALID : L2T_STATE_STALE; ++ L2T_STATE_VALID : L2T_STATE_STALE; + if (memcmp(e->dmac, neigh->ha, 6)) + setup_l2e_send_pending(dev, NULL, e); + } +@@ -418,6 +420,76 @@ + if (arpq) + handle_failed_resolution(dev, arpq); + } ++#else ++/* ++ * Called from a kprobe, interrupts are off. ++ */ ++void t3_l2t_update(struct t3cdev *dev, struct neighbour *neigh) ++{ ++ struct l2t_entry *e; ++ struct l2t_data *d = L2DATA(dev); ++ u32 addr = *(u32 *) neigh->primary_key; ++ int ifidx = neigh->dev->ifindex; ++ int hash = arp_hash(addr, ifidx, d); ++ ++ read_lock(&d->lock); ++ for (e = d->l2tab[hash].first; e; e = e->next) ++ if (e->addr == addr && e->ifindex == ifidx) { ++ spin_lock(&e->lock); ++ if (atomic_read(&e->refcnt)) { ++ if (neigh != e->neigh) ++ neigh_replace(e, neigh); ++ e->tdev = dev; ++ mod_timer(&e->update_timer, jiffies + 1); ++ } ++ spin_unlock(&e->lock); ++ break; ++ } ++ read_unlock(&d->lock); ++} ++ ++static void update_timer_cb(unsigned long data) ++{ ++ struct sk_buff *arpq = NULL; ++ struct l2t_entry *e = (struct l2t_entry *)data; ++ struct neighbour *neigh; ++ struct t3cdev *dev = e->tdev; ++ ++ spin_lock(&e->lock); ++ neigh = e->neigh; ++ if (neigh) ++ neigh_hold(neigh); ++ spin_unlock(&e->lock); ++ ++ if (!neigh) ++ return; ++ ++ read_lock(&neigh->lock); ++ spin_lock(&e->lock); ++ ++ if (atomic_read(&e->refcnt) && neigh == e->neigh) { ++ if (e->state == L2T_STATE_RESOLVING) { ++ if (neigh->nud_state & NUD_FAILED) { ++ arpq = e->arpq_head; ++ e->arpq_head = e->arpq_tail = NULL; ++ } else if ((neigh->nud_state & ++ (NUD_CONNECTED|NUD_STALE)) && e->arpq_head) ++ setup_l2e_send_pending(dev, NULL, e); ++ } else { ++ e->state = neigh->nud_state & NUD_CONNECTED ? ++ L2T_STATE_VALID : L2T_STATE_STALE; ++ if (memcmp(e->dmac, neigh->ha, sizeof(e->dmac))) ++ setup_l2e_send_pending(dev, NULL, e); ++ } ++ } ++ spin_unlock(&e->lock); ++ read_unlock(&neigh->lock); ++ neigh_release(neigh); ++ ++ if (arpq) ++ handle_failed_resolution(dev, arpq); ++} ++#endif + + struct l2t_data *t3_init_l2t(unsigned int l2t_capacity) + { +@@ -438,12 +510,144 @@ + d->l2tab[i].state = L2T_STATE_UNUSED; + spin_lock_init(&d->l2tab[i].lock); + atomic_set(&d->l2tab[i].refcnt, 0); ++#ifndef NETEVENT ++#ifdef OFLD_USE_KPROBES ++ setup_timer(&d->l2tab[i].update_timer, update_timer_cb, ++ (unsigned long)&d->l2tab[i]); ++#endif ++#endif + } + return d; + } + + void t3_free_l2t(struct l2t_data *d) + { ++#ifndef NETEVENT ++#ifdef OFLD_USE_KPROBES ++ int i; ++ ++ /* Stop all L2T timers */ ++ for (i = 0; i < d->nentries; ++i) ++ del_timer_sync(&d->l2tab[i].update_timer); ++#endif ++#endif + cxgb_free_mem(d); + } + ++#ifdef CONFIG_PROC_FS ++#include ++#include ++#include ++ ++static inline void *l2t_get_idx(struct seq_file *seq, loff_t pos) ++{ ++ struct l2t_data *d = seq->private; ++ ++ return pos >= d->nentries ? NULL : &d->l2tab[pos]; ++} ++ ++static void *l2t_seq_start(struct seq_file *seq, loff_t *pos) ++{ ++ return *pos ? l2t_get_idx(seq, *pos) : SEQ_START_TOKEN; ++} ++ ++static void *l2t_seq_next(struct seq_file *seq, void *v, loff_t *pos) ++{ ++ v = l2t_get_idx(seq, *pos + 1); ++ if (v) ++ ++*pos; ++ return v; ++} ++ ++static void l2t_seq_stop(struct seq_file *seq, void *v) ++{ ++} ++ ++static char l2e_state(const struct l2t_entry *e) ++{ ++ switch (e->state) { ++ case L2T_STATE_VALID: return 'V'; /* valid, fast-path entry */ ++ case L2T_STATE_STALE: return 'S'; /* needs revalidation, but usable */ ++ case L2T_STATE_RESOLVING: ++ return e->arpq_head ? 'A' : 'R'; ++ default: ++ return 'U'; ++ } ++} ++ ++static int l2t_seq_show(struct seq_file *seq, void *v) ++{ ++ if (v == SEQ_START_TOKEN) ++ seq_puts(seq, "Index IP address Ethernet address VLAN " ++ "Prio State Users SMTIDX Port\n"); ++ else { ++ char ip[20]; ++ struct l2t_entry *e = v; ++ ++ spin_lock_bh(&e->lock); ++ sprintf(ip, "%u.%u.%u.%u", NIPQUAD(e->addr)); ++ seq_printf(seq, "%-5u %-15s %02x:%02x:%02x:%02x:%02x:%02x %4d" ++ " %3u %c %7u %4u %s\n", ++ e->idx, ip, e->dmac[0], e->dmac[1], e->dmac[2], ++ e->dmac[3], e->dmac[4], e->dmac[5], ++ e->vlan & VLAN_VID_MASK, vlan_prio(e), ++ l2e_state(e), atomic_read(&e->refcnt), e->smt_idx, ++ e->neigh ? e->neigh->dev->name : ""); ++ spin_unlock_bh(&e->lock); ++ } ++ return 0; ++} ++ ++static struct seq_operations l2t_seq_ops = { ++ .start = l2t_seq_start, ++ .next = l2t_seq_next, ++ .stop = l2t_seq_stop, ++ .show = l2t_seq_show ++}; ++ ++static int l2t_seq_open(struct inode *inode, struct file *file) ++{ ++ int rc = seq_open(file, &l2t_seq_ops); ++ ++ if (!rc) { ++ struct proc_dir_entry *dp = PDE(inode); ++ struct seq_file *seq = file->private_data; ++ ++ seq->private = dp->data; ++ } ++ return rc; ++} ++ ++static struct file_operations l2t_seq_fops = { ++ .owner = THIS_MODULE, ++ .open = l2t_seq_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = seq_release, ++}; ++ ++/* ++ * Create the proc entries for the L2 table under dir. ++ */ ++int t3_l2t_proc_setup(struct proc_dir_entry *dir, struct l2t_data *d) ++{ ++ struct proc_dir_entry *p; ++ ++ if (!dir) ++ return -EINVAL; ++ ++ p = create_proc_entry("l2t", S_IRUGO, dir); ++ if (!p) ++ return -ENOMEM; ++ ++ p->proc_fops = &l2t_seq_fops; ++ p->data = d; ++ return 0; ++} ++ ++void t3_l2t_proc_free(struct proc_dir_entry *dir) ++{ ++ if (dir) ++ remove_proc_entry("l2t", dir); ++} ++#endif +diff -r c6413c34aa41 drivers/net/cxgb3/l2t.h +--- a/drivers/net/cxgb3/l2t.h Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/l2t.h Tue Oct 06 09:38:00 2009 +0100 +@@ -1,46 +1,29 @@ + /* +- * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved. ++ * This file is part of the Chelsio T3 Ethernet driver for Linux. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. + * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ ++ + #ifndef _CHELSIO_L2T_H + #define _CHELSIO_L2T_H + ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif + #include + #include "t3cdev.h" + #include + + enum { +- L2T_STATE_VALID, /* entry is up to date */ +- L2T_STATE_STALE, /* entry may be used but needs revalidation */ +- L2T_STATE_RESOLVING, /* entry needs address resolution */ +- L2T_STATE_UNUSED /* entry not in use */ ++ L2T_STATE_VALID, /* entry is up to date */ ++ L2T_STATE_STALE, /* entry may be used but needs revalidation */ ++ L2T_STATE_RESOLVING, /* entry needs address resolution */ ++ L2T_STATE_UNUSED /* entry not in use */ + }; + + struct neighbour; +@@ -55,32 +38,40 @@ + * first element in its chain through its first pointer. + */ + struct l2t_entry { +- u16 state; /* entry state */ +- u16 idx; /* entry index */ +- u32 addr; /* dest IP address */ +- int ifindex; /* neighbor's net_device's ifindex */ +- u16 smt_idx; /* SMT index */ +- u16 vlan; /* VLAN TCI (id: bits 0-11, prio: 13-15 */ +- struct neighbour *neigh; /* associated neighbour */ +- struct l2t_entry *first; /* start of hash chain */ +- struct l2t_entry *next; /* next l2t_entry on chain */ +- struct sk_buff *arpq_head; /* queue of packets awaiting resolution */ ++ u16 state; /* entry state */ ++ u16 idx; /* entry index */ ++ u32 addr; /* dest IP address */ ++ int ifindex; /* neighbor's net_device's ifindex */ ++ u16 smt_idx; /* SMT index */ ++ u16 vlan; /* VLAN TCI (id: bits 0-11, prio: 13-15 */ ++ struct neighbour *neigh; /* associated neighbour */ ++ struct l2t_entry *first; /* start of hash chain */ ++ struct l2t_entry *next; /* next l2t_entry on chain */ ++ struct sk_buff *arpq_head; /* queue of packets awaiting resolution */ + struct sk_buff *arpq_tail; + spinlock_t lock; +- atomic_t refcnt; /* entry reference count */ +- u8 dmac[6]; /* neighbour's MAC address */ ++ atomic_t refcnt; /* entry reference count */ ++ u8 dmac[6]; /* neighbour's MAC address */ ++ u8 chan_idx; /* channel index */ ++ u16 orig_smt_idx; /* original SMT index in a bond */ ++#ifndef NETEVENT ++#ifdef OFLD_USE_KPROBES ++ struct timer_list update_timer; ++ struct t3cdev *tdev; ++#endif ++#endif + }; + + struct l2t_data { +- unsigned int nentries; /* number of entries */ +- struct l2t_entry *rover; /* starting point for next allocation */ +- atomic_t nfree; /* number of free entries */ ++ unsigned int nentries; /* number of entries */ ++ struct l2t_entry *rover; /* starting point for next allocation */ ++ atomic_t nfree; /* number of free entries */ + rwlock_t lock; + struct l2t_entry l2tab[0]; + }; + +-typedef void (*arp_failure_handler_func)(struct t3cdev * dev, +- struct sk_buff * skb); ++typedef void (*arp_failure_handler_func)(struct t3cdev *dev, ++ struct sk_buff *skb); + + /* + * Callback stored in an skb to handle address resolution failure. +@@ -102,11 +93,6 @@ + */ + #define L2DATA(dev) ((dev)->l2opt) + +-#define W_TCB_L2T_IX 0 +-#define S_TCB_L2T_IX 7 +-#define M_TCB_L2T_IX 0x7ffULL +-#define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX) +- + void t3_l2e_free(struct l2t_data *d, struct l2t_entry *e); + void t3_l2t_update(struct t3cdev *dev, struct neighbour *neigh); + struct l2t_entry *t3_l2t_get(struct t3cdev *cdev, struct neighbour *neigh, +@@ -116,6 +102,15 @@ + void t3_l2t_send_event(struct t3cdev *dev, struct l2t_entry *e); + struct l2t_data *t3_init_l2t(unsigned int l2t_capacity); + void t3_free_l2t(struct l2t_data *d); ++int t3_l2t_update_l2e(struct t3cdev *dev, struct l2t_entry *e); ++ ++#ifdef CONFIG_PROC_FS ++int t3_l2t_proc_setup(struct proc_dir_entry *dir, struct l2t_data *d); ++void t3_l2t_proc_free(struct proc_dir_entry *dir); ++#else ++#define l2t_proc_setup(dir, d) 0 ++#define l2t_proc_free(dir) ++#endif + + int cxgb3_ofld_send(struct t3cdev *dev, struct sk_buff *skb); + +@@ -135,7 +130,7 @@ + + static inline void l2t_hold(struct l2t_data *d, struct l2t_entry *e) + { +- if (atomic_add_return(1, &e->refcnt) == 1) /* 0 -> 1 transition */ ++ if (atomic_add_return(1, &e->refcnt) == 1) /* 0 -> 1 transition */ + atomic_dec(&d->nfree); + } + +diff -r c6413c34aa41 drivers/net/cxgb3/mc5.c +--- a/drivers/net/cxgb3/mc5.c Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/mc5.c Tue Oct 06 09:38:00 2009 +0100 +@@ -1,34 +1,14 @@ + /* +- * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved. ++ * This file is part of the Chelsio T3 Ethernet driver. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. + * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ ++ + #include "common.h" + #include "regs.h" + +@@ -90,31 +70,28 @@ + * Issue a command to the TCAM and wait for its completion. The address and + * any data required by the command must have been setup by the caller. + */ +-static int mc5_cmd_write(struct adapter *adapter, u32 cmd) ++static int mc5_cmd_write(adapter_t *adapter, u32 cmd) + { + t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_CMD, cmd); + return t3_wait_op_done(adapter, A_MC5_DB_DBGI_RSP_STATUS, + F_DBGIRSPVALID, 1, MAX_WRITE_ATTEMPTS, 1); + } + +-static inline void dbgi_wr_addr3(struct adapter *adapter, u32 v1, u32 v2, +- u32 v3) ++static inline void dbgi_wr_addr3(adapter_t *adapter, u32 v1, u32 v2, u32 v3) + { + t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, v1); + t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR1, v2); + t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR2, v3); + } + +-static inline void dbgi_wr_data3(struct adapter *adapter, u32 v1, u32 v2, +- u32 v3) ++static inline void dbgi_wr_data3(adapter_t *adapter, u32 v1, u32 v2, u32 v3) + { + t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA0, v1); + t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA1, v2); + t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA2, v3); + } + +-static inline void dbgi_rd_rsp3(struct adapter *adapter, u32 *v1, u32 *v2, +- u32 *v3) ++static inline void dbgi_rd_rsp3(adapter_t *adapter, u32 *v1, u32 *v2, u32 *v3) + { + *v1 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA0); + *v2 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA1); +@@ -126,22 +103,21 @@ + * command cmd. The data to be written must have been set up by the caller. + * Returns -1 on failure, 0 on success. + */ +-static int mc5_write(struct adapter *adapter, u32 addr_lo, u32 cmd) ++static int mc5_write(adapter_t *adapter, u32 addr_lo, u32 cmd) + { + t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, addr_lo); + if (mc5_cmd_write(adapter, cmd) == 0) + return 0; +- CH_ERR(adapter, "MC5 timeout writing to TCAM address 0x%x\n", +- addr_lo); ++ CH_ERR(adapter, "MC5 timeout writing to TCAM address 0x%x\n", addr_lo); + return -1; + } + + static int init_mask_data_array(struct mc5 *mc5, u32 mask_array_base, + u32 data_array_base, u32 write_cmd, +- int addr_shift) ++ int addr_shift) + { + unsigned int i; +- struct adapter *adap = mc5->adapter; ++ adapter_t *adap = mc5->adapter; + + /* + * We need the size of the TCAM data and mask arrays in terms of +@@ -151,7 +127,7 @@ + unsigned int server_base = t3_read_reg(adap, A_MC5_DB_SERVER_INDEX); + + if (mc5->mode == MC5_MODE_144_BIT) { +- size72 *= 2; /* 1 144-bit entry is 2 72-bit entries */ ++ size72 *= 2; /* 1 144-bit entry is 2 72-bit entries */ + server_base *= 2; + } + +@@ -163,23 +139,33 @@ + return -1; + + /* Initialize the mask array. */ +- dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff); +- for (i = 0; i < size72; i++) { +- if (i == server_base) /* entering server or routing region */ +- t3_write_reg(adap, A_MC5_DB_DBGI_REQ_DATA0, +- mc5->mode == MC5_MODE_144_BIT ? +- 0xfffffff9 : 0xfffffffd); ++ for (i = 0; i < server_base; i++) { ++ dbgi_wr_data3(adap, 0x3fffffff, 0xfff80000, 0xff); ++ if (mc5_write(adap, mask_array_base + (i << addr_shift), ++ write_cmd)) ++ return -1; ++ i++; ++ dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff); + if (mc5_write(adap, mask_array_base + (i << addr_shift), + write_cmd)) + return -1; + } ++ ++ dbgi_wr_data3(adap, ++ mc5->mode == MC5_MODE_144_BIT ? 0xfffffff9 : 0xfffffffd, ++ 0xffffffff, 0xff); ++ for (; i < size72; i++) ++ if (mc5_write(adap, mask_array_base + (i << addr_shift), ++ write_cmd)) ++ return -1; ++ + return 0; + } + + static int init_idt52100(struct mc5 *mc5) + { + int i; +- struct adapter *adap = mc5->adapter; ++ adapter_t *adap = mc5->adapter; + + t3_write_reg(adap, A_MC5_DB_RSP_LATENCY, + V_RDLAT(0x15) | V_LRNLAT(0x15) | V_SRCHLAT(0x15)); +@@ -236,18 +222,18 @@ + + return init_mask_data_array(mc5, IDT_MSKARY_BASE_ADR0, + IDT_DATARY_BASE_ADR0, IDT_CMD_WRITE, 0); +-err: ++ err: + return -EIO; + } + + static int init_idt43102(struct mc5 *mc5) + { + int i; +- struct adapter *adap = mc5->adapter; ++ adapter_t *adap = mc5->adapter; + + t3_write_reg(adap, A_MC5_DB_RSP_LATENCY, + adap->params.rev == 0 ? V_RDLAT(0xd) | V_SRCHLAT(0x11) : +- V_RDLAT(0xd) | V_SRCHLAT(0x12)); ++ V_RDLAT(0xd) | V_SRCHLAT(0x12)); + + /* + * Use GMRs 24-25 for ELOOKUP, GMRs 20-21 for SYN lookups, and no mask +@@ -296,37 +282,42 @@ + + return init_mask_data_array(mc5, IDT4_MSKARY_BASE_ADR0, + IDT4_DATARY_BASE_ADR0, IDT4_CMD_WRITE, 1); +-err: ++ err: + return -EIO; + } + + /* Put MC5 in DBGI mode. */ + static inline void mc5_dbgi_mode_enable(const struct mc5 *mc5) + { +- t3_write_reg(mc5->adapter, A_MC5_DB_CONFIG, +- V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | F_DBGIEN); ++ t3_set_reg_field(mc5->adapter, A_MC5_DB_CONFIG, F_PRTYEN | F_MBUSEN, ++ F_DBGIEN); + } + + /* Put MC5 in M-Bus mode. */ + static void mc5_dbgi_mode_disable(const struct mc5 *mc5) + { +- t3_write_reg(mc5->adapter, A_MC5_DB_CONFIG, +- V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | +- V_COMPEN(mc5->mode == MC5_MODE_72_BIT) | +- V_PRTYEN(mc5->parity_enabled) | F_MBUSEN); ++ t3_set_reg_field(mc5->adapter, A_MC5_DB_CONFIG, F_DBGIEN, ++ V_PRTYEN(mc5->parity_enabled) | F_MBUSEN); + } + +-/* +- * Initialization that requires the OS and protocol layers to already +- * be intialized goes here. ++/** ++ * t3_mc5_init - initialize MC5 and the TCAM ++ * @mc5: the MC5 handle ++ * @nservers: desired number the TCP servers (listening ports) ++ * @nfilters: desired number of HW filters (classifiers) ++ * @nroutes: desired number of routes ++ * ++ * Initialize MC5 and the TCAM and partition the TCAM for the requested ++ * number of servers, filters, and routes. The number of routes is ++ * typically 0 except for specialized uses of the T3 adapters. + */ + int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, + unsigned int nroutes) + { +- u32 cfg; + int err; + unsigned int tcam_size = mc5->tcam_size; +- struct adapter *adap = mc5->adapter; ++ unsigned int mode72 = mc5->mode == MC5_MODE_72_BIT; ++ adapter_t *adap = mc5->adapter; + + if (!tcam_size) + return 0; +@@ -334,10 +325,12 @@ + if (nroutes > MAX_ROUTES || nroutes + nservers + nfilters > tcam_size) + return -EINVAL; + ++ if (nfilters) ++ mc5->parity_enabled = 0; ++ + /* Reset the TCAM */ +- cfg = t3_read_reg(adap, A_MC5_DB_CONFIG) & ~F_TMMODE; +- cfg |= V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | F_TMRST; +- t3_write_reg(adap, A_MC5_DB_CONFIG, cfg); ++ t3_set_reg_field(adap, A_MC5_DB_CONFIG, F_TMMODE | F_COMPEN, ++ V_COMPEN(mode72) | V_TMMODE(mode72) | F_TMRST); + if (t3_wait_op_done(adap, A_MC5_DB_CONFIG, F_TMRDY, 1, 500, 0)) { + CH_ERR(adap, "TCAM reset timed out\n"); + return -1; +@@ -348,8 +341,6 @@ + tcam_size - nroutes - nfilters); + t3_write_reg(adap, A_MC5_DB_SERVER_INDEX, + tcam_size - nroutes - nfilters - nservers); +- +- mc5->parity_enabled = 1; + + /* All the TCAM addresses we access have only the low 32 bits non 0 */ + t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR1, 0); +@@ -374,7 +365,7 @@ + return err; + } + +-/* ++/** + * read_mc5_range - dump a part of the memory managed by MC5 + * @mc5: the MC5 handle + * @start: the start address for the dump +@@ -388,7 +379,7 @@ + { + u32 read_cmd; + int err = 0; +- struct adapter *adap = mc5->adapter; ++ adapter_t *adap = mc5->adapter; + + if (mc5->part_type == IDT75P52100) + read_cmd = IDT_CMD_READ; +@@ -410,17 +401,20 @@ + } + + mc5_dbgi_mode_disable(mc5); +- return 0; ++ return err; + } + + #define MC5_INT_FATAL (F_PARITYERR | F_REQQPARERR | F_DISPQPARERR) + +-/* +- * MC5 interrupt handler ++/** ++ * t3_mc5_intr_handler - MC5 interrupt handler ++ * @mc5: the MC5 handle ++ * ++ * The MC5 interrupt handler. + */ + void t3_mc5_intr_handler(struct mc5 *mc5) + { +- struct adapter *adap = mc5->adapter; ++ adapter_t *adap = mc5->adapter; + u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE); + + if ((cause & F_PARITYERR) && mc5->parity_enabled) { +@@ -452,11 +446,20 @@ + t3_write_reg(adap, A_MC5_DB_INT_CAUSE, cause); + } + +-void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode) ++/** ++ * t3_mc5_prep - initialize the SW state for MC5 ++ * @adapter: the adapter ++ * @mc5: the MC5 handle ++ * @mode: whether the TCAM will be in 72- or 144-bit mode ++ * ++ * Initialize the SW state associated with MC5. Among other things ++ * this determines the size of the attached TCAM. ++ */ ++void __devinit t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode) + { + #define K * 1024 + +- static unsigned int tcam_part_size[] = { /* in K 72-bit entries */ ++ static unsigned int tcam_part_size[] = { /* in K 72-bit entries */ + 64 K, 128 K, 256 K, 32 K + }; + +@@ -465,8 +468,9 @@ + u32 cfg = t3_read_reg(adapter, A_MC5_DB_CONFIG); + + mc5->adapter = adapter; +- mc5->mode = (unsigned char)mode; +- mc5->part_type = (unsigned char)G_TMTYPE(cfg); ++ mc5->parity_enabled = 1; ++ mc5->mode = (unsigned char) mode; ++ mc5->part_type = (unsigned char) G_TMTYPE(cfg); + if (cfg & F_TMTYPEHI) + mc5->part_type |= 4; + +diff -r c6413c34aa41 drivers/net/cxgb3/mv88e1xxx.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cxgb3/mv88e1xxx.c Tue Oct 06 09:38:00 2009 +0100 +@@ -0,0 +1,295 @@ ++/* ++ * This file is part of the Chelsio T3 Ethernet driver. ++ * ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. ++ */ ++ ++#include "common.h" ++ ++/* Marvell PHY interrupt status bits. */ ++#define MV_INTR_JABBER 0x0001 ++#define MV_INTR_POLARITY_CHNG 0x0002 ++#define MV_INTR_ENG_DETECT_CHNG 0x0010 ++#define MV_INTR_DOWNSHIFT 0x0020 ++#define MV_INTR_MDI_XOVER_CHNG 0x0040 ++#define MV_INTR_FIFO_OVER_UNDER 0x0080 ++#define MV_INTR_FALSE_CARRIER 0x0100 ++#define MV_INTR_SYMBOL_ERROR 0x0200 ++#define MV_INTR_LINK_CHNG 0x0400 ++#define MV_INTR_AUTONEG_DONE 0x0800 ++#define MV_INTR_PAGE_RECV 0x1000 ++#define MV_INTR_DUPLEX_CHNG 0x2000 ++#define MV_INTR_SPEED_CHNG 0x4000 ++#define MV_INTR_AUTONEG_ERR 0x8000 ++ ++/* Marvell PHY specific registers. */ ++#define MV88E1XXX_SPECIFIC_CNTRL 16 ++#define MV88E1XXX_SPECIFIC_STATUS 17 ++#define MV88E1XXX_INTR_ENABLE 18 ++#define MV88E1XXX_INTR_STATUS 19 ++#define MV88E1XXX_EXT_SPECIFIC_CNTRL 20 ++#define MV88E1XXX_RECV_ERR 21 ++#define MV88E1XXX_EXT_ADDR 22 ++#define MV88E1XXX_GLOBAL_STATUS 23 ++#define MV88E1XXX_LED_CNTRL 24 ++#define MV88E1XXX_LED_OVERRIDE 25 ++#define MV88E1XXX_EXT_SPECIFIC_CNTRL2 26 ++#define MV88E1XXX_EXT_SPECIFIC_STATUS 27 ++#define MV88E1XXX_VIRTUAL_CABLE_TESTER 28 ++#define MV88E1XXX_EXTENDED_ADDR 29 ++#define MV88E1XXX_EXTENDED_DATA 30 ++ ++/* PHY specific control register fields */ ++#define S_PSCR_MDI_XOVER_MODE 5 ++#define M_PSCR_MDI_XOVER_MODE 0x3 ++#define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE) ++ ++/* Extended PHY specific control register fields */ ++#define S_DOWNSHIFT_ENABLE 8 ++#define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE) ++ ++#define S_DOWNSHIFT_CNT 9 ++#define M_DOWNSHIFT_CNT 0x7 ++#define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT) ++ ++/* PHY specific status register fields */ ++#define S_PSSR_JABBER 0 ++#define V_PSSR_JABBER (1 << S_PSSR_JABBER) ++ ++#define S_PSSR_POLARITY 1 ++#define V_PSSR_POLARITY (1 << S_PSSR_POLARITY) ++ ++#define S_PSSR_RX_PAUSE 2 ++#define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE) ++ ++#define S_PSSR_TX_PAUSE 3 ++#define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE) ++ ++#define S_PSSR_ENERGY_DETECT 4 ++#define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT) ++ ++#define S_PSSR_DOWNSHIFT_STATUS 5 ++#define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS) ++ ++#define S_PSSR_MDI 6 ++#define V_PSSR_MDI (1 << S_PSSR_MDI) ++ ++#define S_PSSR_CABLE_LEN 7 ++#define M_PSSR_CABLE_LEN 0x7 ++#define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN) ++#define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN) ++ ++#define S_PSSR_LINK 10 ++#define V_PSSR_LINK (1 << S_PSSR_LINK) ++ ++#define S_PSSR_STATUS_RESOLVED 11 ++#define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED) ++ ++#define S_PSSR_PAGE_RECEIVED 12 ++#define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED) ++ ++#define S_PSSR_DUPLEX 13 ++#define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX) ++ ++#define S_PSSR_SPEED 14 ++#define M_PSSR_SPEED 0x3 ++#define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED) ++#define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED) ++ ++/* MV88E1XXX MDI crossover register values */ ++#define CROSSOVER_MDI 0 ++#define CROSSOVER_MDIX 1 ++#define CROSSOVER_AUTO 3 ++ ++#define INTR_ENABLE_MASK (MV_INTR_SPEED_CHNG | MV_INTR_DUPLEX_CHNG | \ ++ MV_INTR_AUTONEG_DONE | MV_INTR_LINK_CHNG | MV_INTR_FIFO_OVER_UNDER | \ ++ MV_INTR_ENG_DETECT_CHNG) ++ ++/* ++ * Reset the PHY. If 'wait' is set wait until the reset completes. ++ */ ++static int mv88e1xxx_reset(struct cphy *cphy, int wait) ++{ ++ return t3_phy_reset(cphy, 0, wait); ++} ++ ++static int mv88e1xxx_intr_enable(struct cphy *cphy) ++{ ++ return mdio_write(cphy, 0, MV88E1XXX_INTR_ENABLE, INTR_ENABLE_MASK); ++} ++ ++static int mv88e1xxx_intr_disable(struct cphy *cphy) ++{ ++ return mdio_write(cphy, 0, MV88E1XXX_INTR_ENABLE, 0); ++} ++ ++static int mv88e1xxx_intr_clear(struct cphy *cphy) ++{ ++ u32 val; ++ ++ /* Clear PHY interrupts by reading the register. */ ++ return mdio_read(cphy, 0, MV88E1XXX_INTR_STATUS, &val); ++} ++ ++static int mv88e1xxx_crossover_set(struct cphy *cphy, int crossover) ++{ ++ return t3_mdio_change_bits(cphy, 0, MV88E1XXX_SPECIFIC_CNTRL, ++ V_PSCR_MDI_XOVER_MODE(M_PSCR_MDI_XOVER_MODE), ++ V_PSCR_MDI_XOVER_MODE(crossover)); ++} ++ ++static int mv88e1xxx_autoneg_enable(struct cphy *cphy) ++{ ++ mv88e1xxx_crossover_set(cphy, CROSSOVER_AUTO); ++ ++ /* restart autoneg for change to take effect */ ++ return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, ++ BMCR_ANENABLE | BMCR_ANRESTART); ++} ++ ++static int mv88e1xxx_autoneg_restart(struct cphy *cphy) ++{ ++ return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, ++ BMCR_ANRESTART); ++} ++ ++static int mv88e1xxx_set_loopback(struct cphy *cphy, int mmd, int dir, int on) ++{ ++ return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_LOOPBACK, ++ on ? BMCR_LOOPBACK : 0); ++} ++ ++static int mv88e1xxx_get_link_status(struct cphy *cphy, int *link_ok, ++ int *speed, int *duplex, int *fc) ++{ ++ u32 status; ++ int sp = -1, dplx = -1, pause = 0; ++ ++ mdio_read(cphy, 0, MV88E1XXX_SPECIFIC_STATUS, &status); ++ if ((status & V_PSSR_STATUS_RESOLVED) != 0) { ++ if (status & V_PSSR_RX_PAUSE) ++ pause |= PAUSE_RX; ++ if (status & V_PSSR_TX_PAUSE) ++ pause |= PAUSE_TX; ++ dplx = (status & V_PSSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; ++ sp = G_PSSR_SPEED(status); ++ if (sp == 0) ++ sp = SPEED_10; ++ else if (sp == 1) ++ sp = SPEED_100; ++ else ++ sp = SPEED_1000; ++ } ++ if (link_ok) ++ *link_ok = (status & V_PSSR_LINK) != 0; ++ if (speed) ++ *speed = sp; ++ if (duplex) ++ *duplex = dplx; ++ if (fc) ++ *fc = pause; ++ return 0; ++} ++ ++static int mv88e1xxx_set_speed_duplex(struct cphy *phy, int speed, int duplex) ++{ ++ int err = t3_set_phy_speed_duplex(phy, speed, duplex); ++ ++ /* PHY needs reset for new settings to take effect */ ++ if (!err) ++ err = mv88e1xxx_reset(phy, 0); ++ return err; ++} ++ ++static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable) ++{ ++ /* ++ * Set the downshift counter to 2 so we try to establish Gb link ++ * twice before downshifting. ++ */ ++ return t3_mdio_change_bits(cphy, 0, MV88E1XXX_EXT_SPECIFIC_CNTRL, ++ V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(M_DOWNSHIFT_CNT), ++ downshift_enable ? V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(2) : 0); ++} ++ ++static int mv88e1xxx_power_down(struct cphy *cphy, int enable) ++{ ++ return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN, ++ enable ? BMCR_PDOWN : 0); ++} ++ ++static int mv88e1xxx_intr_handler(struct cphy *cphy) ++{ ++ const u32 link_change_intrs = MV_INTR_LINK_CHNG | ++ MV_INTR_AUTONEG_DONE | MV_INTR_DUPLEX_CHNG | ++ MV_INTR_SPEED_CHNG | MV_INTR_DOWNSHIFT; ++ ++ u32 cause; ++ int cphy_cause = 0; ++ ++ mdio_read(cphy, 0, MV88E1XXX_INTR_STATUS, &cause); ++ cause &= INTR_ENABLE_MASK; ++ if (cause & link_change_intrs) ++ cphy_cause |= cphy_cause_link_change; ++ if (cause & MV_INTR_FIFO_OVER_UNDER) ++ cphy_cause |= cphy_cause_fifo_error; ++ return cphy_cause; ++} ++ ++#ifdef C99_NOT_SUPPORTED ++static struct cphy_ops mv88e1xxx_ops = { ++ mv88e1xxx_reset, ++ mv88e1xxx_intr_enable, ++ mv88e1xxx_intr_disable, ++ mv88e1xxx_intr_clear, ++ mv88e1xxx_intr_handler, ++ mv88e1xxx_autoneg_enable, ++ mv88e1xxx_autoneg_restart, ++ t3_phy_advertise, ++ mv88e1xxx_set_loopback, ++ mv88e1xxx_set_speed_duplex, ++ mv88e1xxx_get_link_status, ++ mv88e1xxx_power_down, ++}; ++#else ++static struct cphy_ops mv88e1xxx_ops = { ++ .reset = mv88e1xxx_reset, ++ .intr_enable = mv88e1xxx_intr_enable, ++ .intr_disable = mv88e1xxx_intr_disable, ++ .intr_clear = mv88e1xxx_intr_clear, ++ .intr_handler = mv88e1xxx_intr_handler, ++ .autoneg_enable = mv88e1xxx_autoneg_enable, ++ .autoneg_restart = mv88e1xxx_autoneg_restart, ++ .advertise = t3_phy_advertise, ++ .set_loopback = mv88e1xxx_set_loopback, ++ .set_speed_duplex = mv88e1xxx_set_speed_duplex, ++ .get_link_status = mv88e1xxx_get_link_status, ++ .power_down = mv88e1xxx_power_down, ++}; ++#endif ++ ++int t3_mv88e1xxx_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops) ++{ ++ struct cphy *phy = &pinfo->phy; ++ int err; ++ ++ cphy_init(phy, pinfo->adapter, pinfo, phy_addr, &mv88e1xxx_ops, mdio_ops, ++ SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full | ++ SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_MII | ++ SUPPORTED_TP | SUPPORTED_IRQ, "10/100/1000BASE-T"); ++ ++ /* Configure copper PHY transmitter as class A to reduce EMI. */ ++ err = mdio_write(phy, 0, MV88E1XXX_EXTENDED_ADDR, 0xb); ++ if (!err) ++ err = mdio_write(phy, 0, MV88E1XXX_EXTENDED_DATA, 0x8004); ++ ++ if (!err) ++ err = mv88e1xxx_downshift_set(phy, 1); /* Enable downshift */ ++ return err; ++} +diff -r c6413c34aa41 drivers/net/cxgb3/offload.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cxgb3/offload.h Tue Oct 06 09:38:00 2009 +0100 +@@ -0,0 +1,161 @@ ++/* ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. ++ * ++ * Written by Dimitris Michailidis (dm@chelsio.com) ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. ++ */ ++ ++#ifndef _NET_OFFLOAD_H ++#define _NET_OFFLOAD_H ++ ++#include ++ ++#if defined(CONFIG_TCP_OFFLOAD_MODULE) ++# define SOCK_OFFLOADED (31) // connected socket is offloaded ++# define SOCK_NO_DDP (30) // socket should not do DDP ++#endif ++ ++enum { ++ OFFLOAD_LISTEN_START, ++ OFFLOAD_LISTEN_STOP ++}; ++ ++struct sock; ++struct sk_buff; ++struct toedev; ++struct notifier_block; ++struct pipe_inode_info; ++ ++/* ++ * Extended 'struct proto' with additional members used by offloaded ++ * connections. ++ */ ++struct sk_ofld_proto { ++ struct proto proto; /* keep this first */ ++ int (*read_sock)(struct sock *sk, read_descriptor_t *desc, ++ sk_read_actor_t recv_actor); ++ ssize_t (*splice_read)(struct sock *sk, loff_t *ppos, ++ struct pipe_inode_info *pipe, size_t len, ++ unsigned int flags); ++}; ++ ++/* Per-skb backlog handler. Run when a socket's backlog is processed. */ ++struct blog_skb_cb { ++ void (*backlog_rcv) (struct sock *sk, struct sk_buff *skb); ++ struct toedev *dev; ++}; ++ ++#define BLOG_SKB_CB(skb) ((struct blog_skb_cb *)(skb)->cb) ++ ++#ifndef LINUX_2_4 ++struct offload_req { ++ __be32 sip[4]; ++ __be32 dip[4]; ++ __be16 sport; ++ __be16 dport; ++ __u8 ipvers_opentype; ++ __u8 tos; ++ __be16 vlan; ++ __u32 mark; ++}; ++ ++enum { OPEN_TYPE_LISTEN, OPEN_TYPE_ACTIVE, OPEN_TYPE_PASSIVE }; ++ ++struct offload_settings { ++ __u8 offload; ++ __s8 ddp; ++ __s8 rx_coalesce; ++ __s8 cong_algo; ++ __s32 rssq; ++ __s16 sched_class; ++ __s8 tstamp; ++ __s8 sack; ++ ++}; ++ ++struct ofld_prog_inst { /* offload policy program "instructions" */ ++ s32 offset; ++ u32 mask; ++ u32 value; ++ s32 next[2]; ++}; ++ ++struct offload_policy { ++ struct rcu_head rcu_head; ++ int match_all; ++ int use_opt; ++ const struct offload_settings *settings; ++ const u32 *opt_prog_start; ++ struct ofld_prog_inst prog[0]; ++}; ++ ++struct ofld_policy_file { ++ unsigned int vers; ++ int output_everything; ++ unsigned int nrules; ++ unsigned int prog_size; ++ unsigned int opt_prog_size; ++ unsigned int nsettings; ++ const struct ofld_prog_inst prog[0]; ++}; ++#endif /* !LINUX_2_4 */ ++ ++#if defined(CONFIG_TCP_OFFLOAD) || \ ++ (defined(CONFIG_TCP_OFFLOAD_MODULE) && defined(MODULE)) ++extern int register_listen_offload_notifier(struct notifier_block *nb); ++extern int unregister_listen_offload_notifier(struct notifier_block *nb); ++extern int start_listen_offload(struct sock *sk); ++extern int stop_listen_offload(struct sock *sk); ++extern int tcp_connect_offload(struct sock *sk); ++extern int set_offload_policy(struct toedev *dev, ++ const struct ofld_policy_file *f); ++extern void offload_req_from_sk(struct offload_req *req, struct sock *sk, ++ int otype); ++extern const struct offload_settings * ++lookup_ofld_policy(const struct toedev *dev, const struct offload_req *req, ++ int cop_default); ++extern void security_inet_conn_estab(struct sock *sk, struct sk_buff *skb); ++extern void walk_listens(struct toedev *dev, ++ int (*func)(struct toedev *dev, struct sock *sk)); ++#else ++static inline int tcp_connect_offload(struct sock *sk) ++{ ++ return 0; ++} ++ ++static inline int start_listen_offload(struct sock *sk) ++{ ++ return -EPROTONOSUPPORT; ++} ++ ++static inline int stop_listen_offload(struct sock *sk) ++{ ++ return -EPROTONOSUPPORT; ++} ++#endif ++ ++#if defined(CONFIG_TCP_OFFLOAD_MODULE) ++extern int install_special_data_ready(struct sock *sk); ++extern void restore_special_data_ready(struct sock *sk); ++extern int skb_splice_bits_pub(struct sk_buff *skb, unsigned int offset, ++ struct pipe_inode_info *pipe, unsigned int len, ++ unsigned int flags); ++#else ++static inline int install_special_data_ready(struct sock *sk) { return 0; } ++static inline void restore_special_data_ready(struct sock *sk) {} ++#define skb_splice_bits_pub skb_splice_bits ++#endif ++ ++#if defined(CONFIG_DEBUG_RODATA) && defined(CONFIG_TCP_OFFLOAD_MODULE) ++extern void offload_socket_ops(struct sock *sk); ++extern void restore_socket_ops(struct sock *sk); ++#else ++static inline void offload_socket_ops(struct sock *sk) {} ++static inline void restore_socket_ops(struct sock *sk) {} ++#endif ++ ++#endif /* !_NET_OFFLOAD_H */ +diff -r c6413c34aa41 drivers/net/cxgb3/osdep.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cxgb3/osdep.h Tue Oct 06 09:38:00 2009 +0100 +@@ -0,0 +1,198 @@ ++/* ++ * This file is part of the Chelsio T3 Ethernet driver. ++ * ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. ++ */ ++ ++#ifndef __CHELSIO_OSDEP_H ++#define __CHELSIO_OSDEP_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "version.h" ++ ++#define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__) ++#define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ## __VA_ARGS__) ++#define CH_ALERT(adap, fmt, ...) \ ++ dev_printk(KERN_ALERT, &adap->pdev->dev, fmt, ## __VA_ARGS__) ++ ++/* ++ * More powerful macro that selectively prints messages based on msg_enable. ++ * For info and debugging messages. ++ */ ++#define CH_MSG(adapter, level, category, fmt, ...) do { \ ++ if ((adapter)->msg_enable & NETIF_MSG_##category) \ ++ dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \ ++ ## __VA_ARGS__); \ ++} while (0) ++ ++#ifdef DEBUG ++# define CH_DBG(adapter, category, fmt, ...) \ ++ CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__) ++#else ++# define CH_DBG(adapter, category, fmt, ...) ++#endif ++ ++/* Additional NETIF_MSG_* categories */ ++#define NETIF_MSG_OFLD 0x4000000 ++#define NETIF_MSG_MMIO 0x8000000 ++ ++#define IFF_FILTER_ETH_P_SLOW 0x4 ++ ++typedef struct adapter adapter_t; ++typedef struct port_info pinfo_t; ++ ++/** ++ * struct t3_rx_mode - encapsulates the Rx mode for a port ++ * @dev: the net_device associated with the port ++ * @mclist: the multicast address list for the port ++ * @idx: current position within the multicast list ++ * ++ * This structure is passed to the MAC routines that configure the Rx mode ++ * of a port. The structure is opaque to the common code. It invokes a few ++ * functions on this structure including promisc_rx_mode() ++ * that returns whether the port should be in promiscuous mode, ++ * allmulti_rx_mode() to check if the port should be in ALLMULTI mode, ++ * and t3_get_next_mcaddr() that returns the multicast addresses for the ++ * port one at a time. ++ */ ++struct t3_rx_mode { ++ struct net_device *dev; ++ struct dev_mc_list *mclist; ++ unsigned int idx; ++}; ++ ++static inline void init_rx_mode(struct t3_rx_mode *p, struct net_device *dev, ++ struct dev_mc_list *mclist) ++{ ++ p->dev = dev; ++ p->mclist = mclist; ++ p->idx = 0; ++} ++ ++#define promisc_rx_mode(rm) ((rm)->dev->flags & IFF_PROMISC) ++#define allmulti_rx_mode(rm) ((rm)->dev->flags & IFF_ALLMULTI) ++ ++/** ++ * t3_get_next_mcaddr - return the next L2 multicast address for a port ++ * @rm: the Rx mode info ++ * ++ * Returns the next Ethernet multicast address for a port or %NULL if there are ++ * no more. ++ */ ++static inline u8 *t3_get_next_mcaddr(struct t3_rx_mode *rm) ++{ ++ u8 *addr = NULL; ++ ++ if (rm->mclist && rm->idx < rm->dev->mc_count) { ++ addr = rm->mclist->dmi_addr; ++ rm->mclist = rm->mclist->next; ++ rm->idx++; ++ } ++ return addr; ++} ++ ++enum { ++ TP_TMR_RES = 200, /* TP timer resolution in usec */ ++ MAX_NPORTS = 4, /* max # of ports */ ++ TP_SRAM_OFFSET = 4096, /* TP SRAM content offset in eeprom */ ++ TP_SRAM_LEN = 2112, /* TP SRAM content offset in eeprom */ ++}; ++ ++/* compatibility stuff for older kernels */ ++#ifndef PCI_EXP_LNKSTA ++#define PCI_EXP_LNKSTA 18 /* Link Status */ ++#endif ++ ++#ifndef PCI_EXP_LNKCTL ++#define PCI_EXP_LNKCTL 16 /* Link Control */ ++#endif ++ ++#ifndef PCI_EXP_LNKCAP ++#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ ++#endif ++ ++#ifndef PCI_EXP_DEVCTL ++#define PCI_EXP_DEVCTL 8 /* Device Control */ ++#endif ++ ++#ifndef PCI_EXP_DEVCTL_PAYLOAD ++#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ ++#endif ++ ++#ifndef PCI_EXP_DEVCTL_READRQ ++#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ ++#endif ++ ++#ifndef BMCR_SPEED1000 ++#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ ++#endif ++ ++#ifndef MII_CTRL1000 ++#define MII_CTRL1000 0x09 /* 1000BASE-T control */ ++#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ ++#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ ++#endif ++ ++#ifndef ADVERTISE_PAUSE_CAP ++#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ ++#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ ++#endif ++ ++#ifndef ADVERTISED_Pause ++#define ADVERTISED_Pause (1 << 13) ++#define ADVERTISED_Asym_Pause (1 << 14) ++#endif ++ ++#ifndef NETDEV_TX_OK ++#define NETDEV_TX_OK 0 /* driver took care of packet */ ++#define NETDEV_TX_BUSY 1 /* driver tx path was busy*/ ++#define NETDEV_TX_LOCKED -1 /* driver tx lock was already taken */ ++#endif ++ ++#ifndef ADVERTISE_1000XFULL ++#define ADVERTISE_1000XFULL 0x0020 ++#endif ++ ++#ifndef ADVERTISE_1000XHALF ++#define ADVERTISE_1000XHALF 0x0040 ++#endif ++ ++#ifndef ADVERTISE_1000XPAUSE ++#define ADVERTISE_1000XPAUSE 0x0080 ++#endif ++ ++#ifndef ADVERTISE_1000XPSE_ASYM ++#define ADVERTISE_1000XPSE_ASYM 0x0100 ++#endif ++ ++/* Note: cxgb3_compat.h assumes that struct adapter is already defined. ++ * delayed_work is used in struct adapter definition, hence backporting ++ * its definition here. ++ */ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++#define delayed_work work_struct ++#endif ++ ++#ifdef LINUX_2_4 ++#include "linux_2_4_compat.h" ++#include "linux_2_4_compat_workqueue.h" ++#endif ++ ++#ifdef CONFIG_XEN ++#define CHELSIO_FREE_TXBUF_ASAP 1 /* VMs need TX bufs freed ASAP */ ++#endif ++ ++#endif /* !__CHELSIO_OSDEP_H */ +diff -r c6413c34aa41 drivers/net/cxgb3/regs.h +--- a/drivers/net/cxgb3/regs.h Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/regs.h Tue Oct 06 09:38:00 2009 +0100 +@@ -1,3 +1,8 @@ ++/* This file is automatically generated --- do not edit */ ++ ++/* registers for module SGE3 */ ++#define SGE3_BASE_ADDR 0x0 ++ + #define A_SG_CONTROL 0x0 + + #define S_CONGMODE 29 +@@ -12,6 +17,30 @@ + #define V_FATLPERREN(x) ((x) << S_FATLPERREN) + #define F_FATLPERREN V_FATLPERREN(1U) + ++#define S_URGTNL 26 ++#define V_URGTNL(x) ((x) << S_URGTNL) ++#define F_URGTNL V_URGTNL(1U) ++ ++#define S_NEWNOTIFY 25 ++#define V_NEWNOTIFY(x) ((x) << S_NEWNOTIFY) ++#define F_NEWNOTIFY V_NEWNOTIFY(1U) ++ ++#define S_AVOIDCQOVFL 24 ++#define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL) ++#define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U) ++ ++#define S_OPTONEINTMULTQ 23 ++#define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ) ++#define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U) ++ ++#define S_CQCRDTCTRL 22 ++#define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL) ++#define F_CQCRDTCTRL V_CQCRDTCTRL(1U) ++ ++#define S_EGRENUPBP 21 ++#define V_EGRENUPBP(x) ((x) << S_EGRENUPBP) ++#define F_EGRENUPBP V_EGRENUPBP(1U) ++ + #define S_DROPPKT 20 + #define V_DROPPKT(x) ((x) << S_DROPPKT) + #define F_DROPPKT V_DROPPKT(1U) +@@ -23,10 +52,16 @@ + #define S_USERSPACESIZE 14 + #define M_USERSPACESIZE 0x1f + #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE) ++#define G_USERSPACESIZE(x) (((x) >> S_USERSPACESIZE) & M_USERSPACESIZE) + + #define S_HOSTPAGESIZE 11 + #define M_HOSTPAGESIZE 0x7 + #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE) ++#define G_HOSTPAGESIZE(x) (((x) >> S_HOSTPAGESIZE) & M_HOSTPAGESIZE) ++ ++#define S_PCIRELAX 10 ++#define V_PCIRELAX(x) ((x) << S_PCIRELAX) ++#define F_PCIRELAX V_PCIRELAX(1U) + + #define S_FLMODE 9 + #define V_FLMODE(x) ((x) << S_FLMODE) +@@ -35,11 +70,20 @@ + #define S_PKTSHIFT 6 + #define M_PKTSHIFT 0x7 + #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) ++#define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT) + + #define S_ONEINTMULTQ 5 + #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ) + #define F_ONEINTMULTQ V_ONEINTMULTQ(1U) + ++#define S_FLPICKAVAIL 4 ++#define V_FLPICKAVAIL(x) ((x) << S_FLPICKAVAIL) ++#define F_FLPICKAVAIL V_FLPICKAVAIL(1U) ++ ++#define S_BIGENDIANEGRESS 3 ++#define V_BIGENDIANEGRESS(x) ((x) << S_BIGENDIANEGRESS) ++#define F_BIGENDIANEGRESS V_BIGENDIANEGRESS(1U) ++ + #define S_BIGENDIANINGRESS 2 + #define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS) + #define F_BIGENDIANINGRESS V_BIGENDIANINGRESS(1U) +@@ -52,18 +96,6 @@ + #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE) + #define F_GLOBALENABLE V_GLOBALENABLE(1U) + +-#define S_AVOIDCQOVFL 24 +-#define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL) +-#define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U) +- +-#define S_OPTONEINTMULTQ 23 +-#define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ) +-#define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U) +- +-#define S_CQCRDTCTRL 22 +-#define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL) +-#define F_CQCRDTCTRL V_CQCRDTCTRL(1U) +- + #define A_SG_KDOORBELL 0x4 + + #define S_SELEGRCNTX 31 +@@ -73,6 +105,7 @@ + #define S_EGRCNTX 0 + #define M_EGRCNTX 0xffff + #define V_EGRCNTX(x) ((x) << S_EGRCNTX) ++#define G_EGRCNTX(x) (((x) >> S_EGRCNTX) & M_EGRCNTX) + + #define A_SG_GTS 0x8 + +@@ -84,31 +117,30 @@ + #define S_NEWTIMER 16 + #define M_NEWTIMER 0x1fff + #define V_NEWTIMER(x) ((x) << S_NEWTIMER) ++#define G_NEWTIMER(x) (((x) >> S_NEWTIMER) & M_NEWTIMER) + + #define S_NEWINDEX 0 + #define M_NEWINDEX 0xffff + #define V_NEWINDEX(x) ((x) << S_NEWINDEX) ++#define G_NEWINDEX(x) (((x) >> S_NEWINDEX) & M_NEWINDEX) + + #define A_SG_CONTEXT_CMD 0xc + + #define S_CONTEXT_CMD_OPCODE 28 + #define M_CONTEXT_CMD_OPCODE 0xf + #define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE) ++#define G_CONTEXT_CMD_OPCODE(x) (((x) >> S_CONTEXT_CMD_OPCODE) & M_CONTEXT_CMD_OPCODE) + + #define S_CONTEXT_CMD_BUSY 27 + #define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY) + #define F_CONTEXT_CMD_BUSY V_CONTEXT_CMD_BUSY(1U) + + #define S_CQ_CREDIT 20 +- + #define M_CQ_CREDIT 0x7f +- + #define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT) +- + #define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT) + + #define S_CQ 19 +- + #define V_CQ(x) ((x) << S_CQ) + #define F_CQ V_CQ(1U) + +@@ -127,30 +159,22 @@ + #define S_CONTEXT 0 + #define M_CONTEXT 0xffff + #define V_CONTEXT(x) ((x) << S_CONTEXT) +- + #define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT) + + #define A_SG_CONTEXT_DATA0 0x10 +- + #define A_SG_CONTEXT_DATA1 0x14 +- + #define A_SG_CONTEXT_DATA2 0x18 +- + #define A_SG_CONTEXT_DATA3 0x1c +- + #define A_SG_CONTEXT_MASK0 0x20 +- + #define A_SG_CONTEXT_MASK1 0x24 +- + #define A_SG_CONTEXT_MASK2 0x28 +- + #define A_SG_CONTEXT_MASK3 0x2c +- + #define A_SG_RSPQ_CREDIT_RETURN 0x30 + + #define S_CREDITS 0 + #define M_CREDITS 0xffff + #define V_CREDITS(x) ((x) << S_CREDITS) ++#define G_CREDITS(x) (((x) >> S_CREDITS) & M_CREDITS) + + #define A_SG_DATA_INTR 0x34 + +@@ -158,29 +182,210 @@ + #define V_ERRINTR(x) ((x) << S_ERRINTR) + #define F_ERRINTR V_ERRINTR(1U) + ++#define S_DATAINTR 0 ++#define M_DATAINTR 0xff ++#define V_DATAINTR(x) ((x) << S_DATAINTR) ++#define G_DATAINTR(x) (((x) >> S_DATAINTR) & M_DATAINTR) ++ + #define A_SG_HI_DRB_HI_THRSH 0x38 + ++#define S_HIDRBHITHRSH 0 ++#define M_HIDRBHITHRSH 0x3ff ++#define V_HIDRBHITHRSH(x) ((x) << S_HIDRBHITHRSH) ++#define G_HIDRBHITHRSH(x) (((x) >> S_HIDRBHITHRSH) & M_HIDRBHITHRSH) ++ + #define A_SG_HI_DRB_LO_THRSH 0x3c + ++#define S_HIDRBLOTHRSH 0 ++#define M_HIDRBLOTHRSH 0x3ff ++#define V_HIDRBLOTHRSH(x) ((x) << S_HIDRBLOTHRSH) ++#define G_HIDRBLOTHRSH(x) (((x) >> S_HIDRBLOTHRSH) & M_HIDRBLOTHRSH) ++ + #define A_SG_LO_DRB_HI_THRSH 0x40 + ++#define S_LODRBHITHRSH 0 ++#define M_LODRBHITHRSH 0x3ff ++#define V_LODRBHITHRSH(x) ((x) << S_LODRBHITHRSH) ++#define G_LODRBHITHRSH(x) (((x) >> S_LODRBHITHRSH) & M_LODRBHITHRSH) ++ + #define A_SG_LO_DRB_LO_THRSH 0x44 + ++#define S_LODRBLOTHRSH 0 ++#define M_LODRBLOTHRSH 0x3ff ++#define V_LODRBLOTHRSH(x) ((x) << S_LODRBLOTHRSH) ++#define G_LODRBLOTHRSH(x) (((x) >> S_LODRBLOTHRSH) & M_LODRBLOTHRSH) ++ ++#define A_SG_ONE_INT_MULT_Q_COALESCING_TIMER 0x48 + #define A_SG_RSPQ_FL_STATUS 0x4c + ++#define S_RSPQ0STARVED 0 ++#define V_RSPQ0STARVED(x) ((x) << S_RSPQ0STARVED) ++#define F_RSPQ0STARVED V_RSPQ0STARVED(1U) ++ ++#define S_RSPQ1STARVED 1 ++#define V_RSPQ1STARVED(x) ((x) << S_RSPQ1STARVED) ++#define F_RSPQ1STARVED V_RSPQ1STARVED(1U) ++ ++#define S_RSPQ2STARVED 2 ++#define V_RSPQ2STARVED(x) ((x) << S_RSPQ2STARVED) ++#define F_RSPQ2STARVED V_RSPQ2STARVED(1U) ++ ++#define S_RSPQ3STARVED 3 ++#define V_RSPQ3STARVED(x) ((x) << S_RSPQ3STARVED) ++#define F_RSPQ3STARVED V_RSPQ3STARVED(1U) ++ ++#define S_RSPQ4STARVED 4 ++#define V_RSPQ4STARVED(x) ((x) << S_RSPQ4STARVED) ++#define F_RSPQ4STARVED V_RSPQ4STARVED(1U) ++ ++#define S_RSPQ5STARVED 5 ++#define V_RSPQ5STARVED(x) ((x) << S_RSPQ5STARVED) ++#define F_RSPQ5STARVED V_RSPQ5STARVED(1U) ++ ++#define S_RSPQ6STARVED 6 ++#define V_RSPQ6STARVED(x) ((x) << S_RSPQ6STARVED) ++#define F_RSPQ6STARVED V_RSPQ6STARVED(1U) ++ ++#define S_RSPQ7STARVED 7 ++#define V_RSPQ7STARVED(x) ((x) << S_RSPQ7STARVED) ++#define F_RSPQ7STARVED V_RSPQ7STARVED(1U) ++ + #define S_RSPQ0DISABLED 8 ++#define V_RSPQ0DISABLED(x) ((x) << S_RSPQ0DISABLED) ++#define F_RSPQ0DISABLED V_RSPQ0DISABLED(1U) ++ ++#define S_RSPQ1DISABLED 9 ++#define V_RSPQ1DISABLED(x) ((x) << S_RSPQ1DISABLED) ++#define F_RSPQ1DISABLED V_RSPQ1DISABLED(1U) ++ ++#define S_RSPQ2DISABLED 10 ++#define V_RSPQ2DISABLED(x) ((x) << S_RSPQ2DISABLED) ++#define F_RSPQ2DISABLED V_RSPQ2DISABLED(1U) ++ ++#define S_RSPQ3DISABLED 11 ++#define V_RSPQ3DISABLED(x) ((x) << S_RSPQ3DISABLED) ++#define F_RSPQ3DISABLED V_RSPQ3DISABLED(1U) ++ ++#define S_RSPQ4DISABLED 12 ++#define V_RSPQ4DISABLED(x) ((x) << S_RSPQ4DISABLED) ++#define F_RSPQ4DISABLED V_RSPQ4DISABLED(1U) ++ ++#define S_RSPQ5DISABLED 13 ++#define V_RSPQ5DISABLED(x) ((x) << S_RSPQ5DISABLED) ++#define F_RSPQ5DISABLED V_RSPQ5DISABLED(1U) ++ ++#define S_RSPQ6DISABLED 14 ++#define V_RSPQ6DISABLED(x) ((x) << S_RSPQ6DISABLED) ++#define F_RSPQ6DISABLED V_RSPQ6DISABLED(1U) ++ ++#define S_RSPQ7DISABLED 15 ++#define V_RSPQ7DISABLED(x) ((x) << S_RSPQ7DISABLED) ++#define F_RSPQ7DISABLED V_RSPQ7DISABLED(1U) ++ ++#define S_FL0EMPTY 16 ++#define V_FL0EMPTY(x) ((x) << S_FL0EMPTY) ++#define F_FL0EMPTY V_FL0EMPTY(1U) ++ ++#define S_FL1EMPTY 17 ++#define V_FL1EMPTY(x) ((x) << S_FL1EMPTY) ++#define F_FL1EMPTY V_FL1EMPTY(1U) ++ ++#define S_FL2EMPTY 18 ++#define V_FL2EMPTY(x) ((x) << S_FL2EMPTY) ++#define F_FL2EMPTY V_FL2EMPTY(1U) ++ ++#define S_FL3EMPTY 19 ++#define V_FL3EMPTY(x) ((x) << S_FL3EMPTY) ++#define F_FL3EMPTY V_FL3EMPTY(1U) ++ ++#define S_FL4EMPTY 20 ++#define V_FL4EMPTY(x) ((x) << S_FL4EMPTY) ++#define F_FL4EMPTY V_FL4EMPTY(1U) ++ ++#define S_FL5EMPTY 21 ++#define V_FL5EMPTY(x) ((x) << S_FL5EMPTY) ++#define F_FL5EMPTY V_FL5EMPTY(1U) ++ ++#define S_FL6EMPTY 22 ++#define V_FL6EMPTY(x) ((x) << S_FL6EMPTY) ++#define F_FL6EMPTY V_FL6EMPTY(1U) ++ ++#define S_FL7EMPTY 23 ++#define V_FL7EMPTY(x) ((x) << S_FL7EMPTY) ++#define F_FL7EMPTY V_FL7EMPTY(1U) ++ ++#define S_FL8EMPTY 24 ++#define V_FL8EMPTY(x) ((x) << S_FL8EMPTY) ++#define F_FL8EMPTY V_FL8EMPTY(1U) ++ ++#define S_FL9EMPTY 25 ++#define V_FL9EMPTY(x) ((x) << S_FL9EMPTY) ++#define F_FL9EMPTY V_FL9EMPTY(1U) ++ ++#define S_FL10EMPTY 26 ++#define V_FL10EMPTY(x) ((x) << S_FL10EMPTY) ++#define F_FL10EMPTY V_FL10EMPTY(1U) ++ ++#define S_FL11EMPTY 27 ++#define V_FL11EMPTY(x) ((x) << S_FL11EMPTY) ++#define F_FL11EMPTY V_FL11EMPTY(1U) ++ ++#define S_FL12EMPTY 28 ++#define V_FL12EMPTY(x) ((x) << S_FL12EMPTY) ++#define F_FL12EMPTY V_FL12EMPTY(1U) ++ ++#define S_FL13EMPTY 29 ++#define V_FL13EMPTY(x) ((x) << S_FL13EMPTY) ++#define F_FL13EMPTY V_FL13EMPTY(1U) ++ ++#define S_FL14EMPTY 30 ++#define V_FL14EMPTY(x) ((x) << S_FL14EMPTY) ++#define F_FL14EMPTY V_FL14EMPTY(1U) ++ ++#define S_FL15EMPTY 31 ++#define V_FL15EMPTY(x) ((x) << S_FL15EMPTY) ++#define F_FL15EMPTY V_FL15EMPTY(1U) ++ ++#define A_SG_EGR_PRI_CNT 0x50 ++ ++#define S_EGRERROPCODE 24 ++#define M_EGRERROPCODE 0xff ++#define V_EGRERROPCODE(x) ((x) << S_EGRERROPCODE) ++#define G_EGRERROPCODE(x) (((x) >> S_EGRERROPCODE) & M_EGRERROPCODE) ++ ++#define S_EGRHIOPCODE 16 ++#define M_EGRHIOPCODE 0xff ++#define V_EGRHIOPCODE(x) ((x) << S_EGRHIOPCODE) ++#define G_EGRHIOPCODE(x) (((x) >> S_EGRHIOPCODE) & M_EGRHIOPCODE) ++ ++#define S_EGRLOOPCODE 8 ++#define M_EGRLOOPCODE 0xff ++#define V_EGRLOOPCODE(x) ((x) << S_EGRLOOPCODE) ++#define G_EGRLOOPCODE(x) (((x) >> S_EGRLOOPCODE) & M_EGRLOOPCODE) ++ ++#define S_EGRPRICNT 0 ++#define M_EGRPRICNT 0x1f ++#define V_EGRPRICNT(x) ((x) << S_EGRPRICNT) ++#define G_EGRPRICNT(x) (((x) >> S_EGRPRICNT) & M_EGRPRICNT) + + #define A_SG_EGR_RCQ_DRB_THRSH 0x54 + + #define S_HIRCQDRBTHRSH 16 + #define M_HIRCQDRBTHRSH 0x7ff + #define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH) ++#define G_HIRCQDRBTHRSH(x) (((x) >> S_HIRCQDRBTHRSH) & M_HIRCQDRBTHRSH) + + #define S_LORCQDRBTHRSH 0 + #define M_LORCQDRBTHRSH 0x7ff + #define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH) ++#define G_LORCQDRBTHRSH(x) (((x) >> S_LORCQDRBTHRSH) & M_LORCQDRBTHRSH) + + #define A_SG_EGR_CNTX_BADDR 0x58 ++ ++#define S_EGRCNTXBADDR 5 ++#define M_EGRCNTXBADDR 0x7ffffff ++#define V_EGRCNTXBADDR(x) ((x) << S_EGRCNTXBADDR) ++#define G_EGRCNTXBADDR(x) (((x) >> S_EGRCNTXBADDR) & M_EGRCNTXBADDR) + + #define A_SG_INT_CAUSE 0x5c + +@@ -250,6 +455,30 @@ + #define V_LOPIODRBDROPERR(x) ((x) << S_LOPIODRBDROPERR) + #define F_LOPIODRBDROPERR V_LOPIODRBDROPERR(1U) + ++#define S_HICRDTUNDFLOWERR 9 ++#define V_HICRDTUNDFLOWERR(x) ((x) << S_HICRDTUNDFLOWERR) ++#define F_HICRDTUNDFLOWERR V_HICRDTUNDFLOWERR(1U) ++ ++#define S_LOCRDTUNDFLOWERR 8 ++#define V_LOCRDTUNDFLOWERR(x) ((x) << S_LOCRDTUNDFLOWERR) ++#define F_LOCRDTUNDFLOWERR V_LOCRDTUNDFLOWERR(1U) ++ ++#define S_HIPRIORITYDBFULL 7 ++#define V_HIPRIORITYDBFULL(x) ((x) << S_HIPRIORITYDBFULL) ++#define F_HIPRIORITYDBFULL V_HIPRIORITYDBFULL(1U) ++ ++#define S_HIPRIORITYDBEMPTY 6 ++#define V_HIPRIORITYDBEMPTY(x) ((x) << S_HIPRIORITYDBEMPTY) ++#define F_HIPRIORITYDBEMPTY V_HIPRIORITYDBEMPTY(1U) ++ ++#define S_LOPRIORITYDBFULL 5 ++#define V_LOPRIORITYDBFULL(x) ((x) << S_LOPRIORITYDBFULL) ++#define F_LOPRIORITYDBFULL V_LOPRIORITYDBFULL(1U) ++ ++#define S_LOPRIORITYDBEMPTY 4 ++#define V_LOPRIORITYDBEMPTY(x) ((x) << S_LOPRIORITYDBEMPTY) ++#define F_LOPRIORITYDBEMPTY V_LOPRIORITYDBEMPTY(1U) ++ + #define S_RSPQDISABLED 3 + #define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED) + #define F_RSPQDISABLED V_RSPQDISABLED(1U) +@@ -258,51 +487,81 @@ + #define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW) + #define F_RSPQCREDITOVERFOW V_RSPQCREDITOVERFOW(1U) + ++#define S_FLEMPTY 1 ++#define V_FLEMPTY(x) ((x) << S_FLEMPTY) ++#define F_FLEMPTY V_FLEMPTY(1U) ++ ++#define S_RSPQSTARVE 0 ++#define V_RSPQSTARVE(x) ((x) << S_RSPQSTARVE) ++#define F_RSPQSTARVE V_RSPQSTARVE(1U) ++ + #define A_SG_INT_ENABLE 0x60 +- + #define A_SG_CMDQ_CREDIT_TH 0x64 + + #define S_TIMEOUT 8 + #define M_TIMEOUT 0xffffff + #define V_TIMEOUT(x) ((x) << S_TIMEOUT) ++#define G_TIMEOUT(x) (((x) >> S_TIMEOUT) & M_TIMEOUT) + + #define S_THRESHOLD 0 + #define M_THRESHOLD 0xff + #define V_THRESHOLD(x) ((x) << S_THRESHOLD) ++#define G_THRESHOLD(x) (((x) >> S_THRESHOLD) & M_THRESHOLD) + + #define A_SG_TIMER_TICK 0x68 +- + #define A_SG_CQ_CONTEXT_BADDR 0x6c ++ ++#define S_BASEADDR 5 ++#define M_BASEADDR 0x7ffffff ++#define V_BASEADDR(x) ((x) << S_BASEADDR) ++#define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR) + + #define A_SG_OCO_BASE 0x70 + + #define S_BASE1 16 + #define M_BASE1 0xffff + #define V_BASE1(x) ((x) << S_BASE1) ++#define G_BASE1(x) (((x) >> S_BASE1) & M_BASE1) ++ ++#define S_BASE0 0 ++#define M_BASE0 0xffff ++#define V_BASE0(x) ((x) << S_BASE0) ++#define G_BASE0(x) (((x) >> S_BASE0) & M_BASE0) + + #define A_SG_DRB_PRI_THRESH 0x74 ++ ++#define S_DRBPRITHRSH 0 ++#define M_DRBPRITHRSH 0xffff ++#define V_DRBPRITHRSH(x) ((x) << S_DRBPRITHRSH) ++#define G_DRBPRITHRSH(x) (((x) >> S_DRBPRITHRSH) & M_DRBPRITHRSH) ++ ++#define A_SG_DEBUG_INDEX 0x78 ++#define A_SG_DEBUG_DATA 0x7c ++ ++/* registers for module PCIX1 */ ++#define PCIX1_BASE_ADDR 0x80 + + #define A_PCIX_INT_ENABLE 0x80 + + #define S_MSIXPARERR 22 + #define M_MSIXPARERR 0x7 +- + #define V_MSIXPARERR(x) ((x) << S_MSIXPARERR) ++#define G_MSIXPARERR(x) (((x) >> S_MSIXPARERR) & M_MSIXPARERR) + + #define S_CFPARERR 18 + #define M_CFPARERR 0xf +- + #define V_CFPARERR(x) ((x) << S_CFPARERR) ++#define G_CFPARERR(x) (((x) >> S_CFPARERR) & M_CFPARERR) + + #define S_RFPARERR 14 + #define M_RFPARERR 0xf +- + #define V_RFPARERR(x) ((x) << S_RFPARERR) ++#define G_RFPARERR(x) (((x) >> S_RFPARERR) & M_RFPARERR) + + #define S_WFPARERR 12 + #define M_WFPARERR 0x3 +- + #define V_WFPARERR(x) ((x) << S_WFPARERR) ++#define G_WFPARERR(x) (((x) >> S_WFPARERR) & M_WFPARERR) + + #define S_PIOPARERR 11 + #define V_PIOPARERR(x) ((x) << S_PIOPARERR) +@@ -353,7 +612,6 @@ + #define F_MSTDETPARERR V_MSTDETPARERR(1U) + + #define A_PCIX_INT_CAUSE 0x84 +- + #define A_PCIX_CFG 0x88 + + #define S_DMASTOPEN 19 +@@ -363,6 +621,46 @@ + #define S_CLIDECEN 18 + #define V_CLIDECEN(x) ((x) << S_CLIDECEN) + #define F_CLIDECEN V_CLIDECEN(1U) ++ ++#define S_LATTMRDIS 17 ++#define V_LATTMRDIS(x) ((x) << S_LATTMRDIS) ++#define F_LATTMRDIS V_LATTMRDIS(1U) ++ ++#define S_LOWPWREN 16 ++#define V_LOWPWREN(x) ((x) << S_LOWPWREN) ++#define F_LOWPWREN V_LOWPWREN(1U) ++ ++#define S_ASYNCINTVEC 11 ++#define M_ASYNCINTVEC 0x1f ++#define V_ASYNCINTVEC(x) ((x) << S_ASYNCINTVEC) ++#define G_ASYNCINTVEC(x) (((x) >> S_ASYNCINTVEC) & M_ASYNCINTVEC) ++ ++#define S_MAXSPLTRNC 8 ++#define M_MAXSPLTRNC 0x7 ++#define V_MAXSPLTRNC(x) ((x) << S_MAXSPLTRNC) ++#define G_MAXSPLTRNC(x) (((x) >> S_MAXSPLTRNC) & M_MAXSPLTRNC) ++ ++#define S_MAXSPLTRNR 5 ++#define M_MAXSPLTRNR 0x7 ++#define V_MAXSPLTRNR(x) ((x) << S_MAXSPLTRNR) ++#define G_MAXSPLTRNR(x) (((x) >> S_MAXSPLTRNR) & M_MAXSPLTRNR) ++ ++#define S_MAXWRBYTECNT 3 ++#define M_MAXWRBYTECNT 0x3 ++#define V_MAXWRBYTECNT(x) ((x) << S_MAXWRBYTECNT) ++#define G_MAXWRBYTECNT(x) (((x) >> S_MAXWRBYTECNT) & M_MAXWRBYTECNT) ++ ++#define S_WRREQATOMICEN 2 ++#define V_WRREQATOMICEN(x) ((x) << S_WRREQATOMICEN) ++#define F_WRREQATOMICEN V_WRREQATOMICEN(1U) ++ ++#define S_RSTWRMMODE 1 ++#define V_RSTWRMMODE(x) ((x) << S_RSTWRMMODE) ++#define F_RSTWRMMODE V_RSTWRMMODE(1U) ++ ++#define S_PIOACK64EN 0 ++#define V_PIOACK64EN(x) ((x) << S_PIOACK64EN) ++#define F_PIOACK64EN V_PIOACK64EN(1U) + + #define A_PCIX_MODE 0x8c + +@@ -376,16 +674,241 @@ + #define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT) + #define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT) + ++#define S_66MHZ 1 ++#define V_66MHZ(x) ((x) << S_66MHZ) ++#define F_66MHZ V_66MHZ(1U) ++ + #define S_64BIT 0 + #define V_64BIT(x) ((x) << S_64BIT) + #define F_64BIT V_64BIT(1U) + ++#define A_PCIX_CAL 0x90 ++ ++#define S_BUSY 31 ++#define V_BUSY(x) ((x) << S_BUSY) ++#define F_BUSY V_BUSY(1U) ++ ++#define S_PERCALDIV 22 ++#define M_PERCALDIV 0xff ++#define V_PERCALDIV(x) ((x) << S_PERCALDIV) ++#define G_PERCALDIV(x) (((x) >> S_PERCALDIV) & M_PERCALDIV) ++ ++#define S_PERCALEN 21 ++#define V_PERCALEN(x) ((x) << S_PERCALEN) ++#define F_PERCALEN V_PERCALEN(1U) ++ ++#define S_SGLCALEN 20 ++#define V_SGLCALEN(x) ((x) << S_SGLCALEN) ++#define F_SGLCALEN V_SGLCALEN(1U) ++ ++#define S_ZINUPDMODE 19 ++#define V_ZINUPDMODE(x) ((x) << S_ZINUPDMODE) ++#define F_ZINUPDMODE V_ZINUPDMODE(1U) ++ ++#define S_ZINSEL 18 ++#define V_ZINSEL(x) ((x) << S_ZINSEL) ++#define F_ZINSEL V_ZINSEL(1U) ++ ++#define S_ZPDMAN 15 ++#define M_ZPDMAN 0x7 ++#define V_ZPDMAN(x) ((x) << S_ZPDMAN) ++#define G_ZPDMAN(x) (((x) >> S_ZPDMAN) & M_ZPDMAN) ++ ++#define S_ZPUMAN 12 ++#define M_ZPUMAN 0x7 ++#define V_ZPUMAN(x) ((x) << S_ZPUMAN) ++#define G_ZPUMAN(x) (((x) >> S_ZPUMAN) & M_ZPUMAN) ++ ++#define S_ZPDOUT 9 ++#define M_ZPDOUT 0x7 ++#define V_ZPDOUT(x) ((x) << S_ZPDOUT) ++#define G_ZPDOUT(x) (((x) >> S_ZPDOUT) & M_ZPDOUT) ++ ++#define S_ZPUOUT 6 ++#define M_ZPUOUT 0x7 ++#define V_ZPUOUT(x) ((x) << S_ZPUOUT) ++#define G_ZPUOUT(x) (((x) >> S_ZPUOUT) & M_ZPUOUT) ++ ++#define S_ZPDIN 3 ++#define M_ZPDIN 0x7 ++#define V_ZPDIN(x) ((x) << S_ZPDIN) ++#define G_ZPDIN(x) (((x) >> S_ZPDIN) & M_ZPDIN) ++ ++#define S_ZPUIN 0 ++#define M_ZPUIN 0x7 ++#define V_ZPUIN(x) ((x) << S_ZPUIN) ++#define G_ZPUIN(x) (((x) >> S_ZPUIN) & M_ZPUIN) ++ ++#define A_PCIX_WOL 0x94 ++ ++#define S_WAKEUP1 3 ++#define V_WAKEUP1(x) ((x) << S_WAKEUP1) ++#define F_WAKEUP1 V_WAKEUP1(1U) ++ ++#define S_WAKEUP0 2 ++#define V_WAKEUP0(x) ((x) << S_WAKEUP0) ++#define F_WAKEUP0 V_WAKEUP0(1U) ++ ++#define S_SLEEPMODE1 1 ++#define V_SLEEPMODE1(x) ((x) << S_SLEEPMODE1) ++#define F_SLEEPMODE1 V_SLEEPMODE1(1U) ++ ++#define S_SLEEPMODE0 0 ++#define V_SLEEPMODE0(x) ((x) << S_SLEEPMODE0) ++#define F_SLEEPMODE0 V_SLEEPMODE0(1U) ++ ++#define A_PCIX_STAT0 0x98 ++ ++#define S_PIOREQFIFOLEVEL 26 ++#define M_PIOREQFIFOLEVEL 0x3f ++#define V_PIOREQFIFOLEVEL(x) ((x) << S_PIOREQFIFOLEVEL) ++#define G_PIOREQFIFOLEVEL(x) (((x) >> S_PIOREQFIFOLEVEL) & M_PIOREQFIFOLEVEL) ++ ++#define S_RFINIST 24 ++#define M_RFINIST 0x3 ++#define V_RFINIST(x) ((x) << S_RFINIST) ++#define G_RFINIST(x) (((x) >> S_RFINIST) & M_RFINIST) ++ ++#define S_RFRESPRDST 22 ++#define M_RFRESPRDST 0x3 ++#define V_RFRESPRDST(x) ((x) << S_RFRESPRDST) ++#define G_RFRESPRDST(x) (((x) >> S_RFRESPRDST) & M_RFRESPRDST) ++ ++#define S_TARCST 19 ++#define M_TARCST 0x7 ++#define V_TARCST(x) ((x) << S_TARCST) ++#define G_TARCST(x) (((x) >> S_TARCST) & M_TARCST) ++ ++#define S_TARXST 16 ++#define M_TARXST 0x7 ++#define V_TARXST(x) ((x) << S_TARXST) ++#define G_TARXST(x) (((x) >> S_TARXST) & M_TARXST) ++ ++#define S_WFREQWRST 13 ++#define M_WFREQWRST 0x7 ++#define V_WFREQWRST(x) ((x) << S_WFREQWRST) ++#define G_WFREQWRST(x) (((x) >> S_WFREQWRST) & M_WFREQWRST) ++ ++#define S_WFRESPFIFOEMPTY 12 ++#define V_WFRESPFIFOEMPTY(x) ((x) << S_WFRESPFIFOEMPTY) ++#define F_WFRESPFIFOEMPTY V_WFRESPFIFOEMPTY(1U) ++ ++#define S_WFREQFIFOEMPTY 11 ++#define V_WFREQFIFOEMPTY(x) ((x) << S_WFREQFIFOEMPTY) ++#define F_WFREQFIFOEMPTY V_WFREQFIFOEMPTY(1U) ++ ++#define S_RFRESPFIFOEMPTY 10 ++#define V_RFRESPFIFOEMPTY(x) ((x) << S_RFRESPFIFOEMPTY) ++#define F_RFRESPFIFOEMPTY V_RFRESPFIFOEMPTY(1U) ++ ++#define S_RFREQFIFOEMPTY 9 ++#define V_RFREQFIFOEMPTY(x) ((x) << S_RFREQFIFOEMPTY) ++#define F_RFREQFIFOEMPTY V_RFREQFIFOEMPTY(1U) ++ ++#define S_PIORESPFIFOLEVEL 7 ++#define M_PIORESPFIFOLEVEL 0x3 ++#define V_PIORESPFIFOLEVEL(x) ((x) << S_PIORESPFIFOLEVEL) ++#define G_PIORESPFIFOLEVEL(x) (((x) >> S_PIORESPFIFOLEVEL) & M_PIORESPFIFOLEVEL) ++ ++#define S_CFRESPFIFOEMPTY 6 ++#define V_CFRESPFIFOEMPTY(x) ((x) << S_CFRESPFIFOEMPTY) ++#define F_CFRESPFIFOEMPTY V_CFRESPFIFOEMPTY(1U) ++ ++#define S_CFREQFIFOEMPTY 5 ++#define V_CFREQFIFOEMPTY(x) ((x) << S_CFREQFIFOEMPTY) ++#define F_CFREQFIFOEMPTY V_CFREQFIFOEMPTY(1U) ++ ++#define S_VPDRESPFIFOEMPTY 4 ++#define V_VPDRESPFIFOEMPTY(x) ((x) << S_VPDRESPFIFOEMPTY) ++#define F_VPDRESPFIFOEMPTY V_VPDRESPFIFOEMPTY(1U) ++ ++#define S_VPDREQFIFOEMPTY 3 ++#define V_VPDREQFIFOEMPTY(x) ((x) << S_VPDREQFIFOEMPTY) ++#define F_VPDREQFIFOEMPTY V_VPDREQFIFOEMPTY(1U) ++ ++#define S_PIO_RSPPND 2 ++#define V_PIO_RSPPND(x) ((x) << S_PIO_RSPPND) ++#define F_PIO_RSPPND V_PIO_RSPPND(1U) ++ ++#define S_DLYTRNPND 1 ++#define V_DLYTRNPND(x) ((x) << S_DLYTRNPND) ++#define F_DLYTRNPND V_DLYTRNPND(1U) ++ ++#define S_SPLTRNPND 0 ++#define V_SPLTRNPND(x) ((x) << S_SPLTRNPND) ++#define F_SPLTRNPND V_SPLTRNPND(1U) ++ ++#define A_PCIX_STAT1 0x9c ++ ++#define S_WFINIST 26 ++#define M_WFINIST 0xf ++#define V_WFINIST(x) ((x) << S_WFINIST) ++#define G_WFINIST(x) (((x) >> S_WFINIST) & M_WFINIST) ++ ++#define S_ARBST 23 ++#define M_ARBST 0x7 ++#define V_ARBST(x) ((x) << S_ARBST) ++#define G_ARBST(x) (((x) >> S_ARBST) & M_ARBST) ++ ++#define S_PMIST 21 ++#define M_PMIST 0x3 ++#define V_PMIST(x) ((x) << S_PMIST) ++#define G_PMIST(x) (((x) >> S_PMIST) & M_PMIST) ++ ++#define S_CALST 19 ++#define M_CALST 0x3 ++#define V_CALST(x) ((x) << S_CALST) ++#define G_CALST(x) (((x) >> S_CALST) & M_CALST) ++ ++#define S_CFREQRDST 17 ++#define M_CFREQRDST 0x3 ++#define V_CFREQRDST(x) ((x) << S_CFREQRDST) ++#define G_CFREQRDST(x) (((x) >> S_CFREQRDST) & M_CFREQRDST) ++ ++#define S_CFINIST 15 ++#define M_CFINIST 0x3 ++#define V_CFINIST(x) ((x) << S_CFINIST) ++#define G_CFINIST(x) (((x) >> S_CFINIST) & M_CFINIST) ++ ++#define S_CFRESPRDST 13 ++#define M_CFRESPRDST 0x3 ++#define V_CFRESPRDST(x) ((x) << S_CFRESPRDST) ++#define G_CFRESPRDST(x) (((x) >> S_CFRESPRDST) & M_CFRESPRDST) ++ ++#define S_INICST 10 ++#define M_INICST 0x7 ++#define V_INICST(x) ((x) << S_INICST) ++#define G_INICST(x) (((x) >> S_INICST) & M_INICST) ++ ++#define S_INIXST 7 ++#define M_INIXST 0x7 ++#define V_INIXST(x) ((x) << S_INIXST) ++#define G_INIXST(x) (((x) >> S_INIXST) & M_INIXST) ++ ++#define S_INTST 4 ++#define M_INTST 0x7 ++#define V_INTST(x) ((x) << S_INTST) ++#define G_INTST(x) (((x) >> S_INTST) & M_INTST) ++ ++#define S_PIOST 2 ++#define M_PIOST 0x3 ++#define V_PIOST(x) ((x) << S_PIOST) ++#define G_PIOST(x) (((x) >> S_PIOST) & M_PIOST) ++ ++#define S_RFREQRDST 0 ++#define M_RFREQRDST 0x3 ++#define V_RFREQRDST(x) ((x) << S_RFREQRDST) ++#define G_RFREQRDST(x) (((x) >> S_RFREQRDST) & M_RFREQRDST) ++ ++/* registers for module PCIE0 */ ++#define PCIE0_BASE_ADDR 0x80 ++ + #define A_PCIE_INT_ENABLE 0x80 + +-#define S_BISTERR 15 ++#define S_BISTERR 19 + #define M_BISTERR 0xff +- + #define V_BISTERR(x) ((x) << S_BISTERR) ++#define G_BISTERR(x) (((x) >> S_BISTERR) & M_BISTERR) + + #define S_TXPARERR 18 + #define V_TXPARERR(x) ((x) << S_TXPARERR) +@@ -405,8 +928,8 @@ + + #define S_PCIE_MSIXPARERR 12 + #define M_PCIE_MSIXPARERR 0x7 +- + #define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR) ++#define G_PCIE_MSIXPARERR(x) (((x) >> S_PCIE_MSIXPARERR) & M_PCIE_MSIXPARERR) + + #define S_PCIE_CFPARERR 11 + #define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR) +@@ -432,17 +955,44 @@ + #define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR) + #define F_UNXSPLCPLERRR V_UNXSPLCPLERRR(1U) + ++#define S_VPDADDRCHNG 5 ++#define V_VPDADDRCHNG(x) ((x) << S_VPDADDRCHNG) ++#define F_VPDADDRCHNG V_VPDADDRCHNG(1U) ++ ++#define S_BUSMSTREN 4 ++#define V_BUSMSTREN(x) ((x) << S_BUSMSTREN) ++#define F_BUSMSTREN V_BUSMSTREN(1U) ++ ++#define S_PMSTCHNG 3 ++#define V_PMSTCHNG(x) ((x) << S_PMSTCHNG) ++#define F_PMSTCHNG V_PMSTCHNG(1U) ++ ++#define S_PEXMSG 2 ++#define V_PEXMSG(x) ((x) << S_PEXMSG) ++#define F_PEXMSG V_PEXMSG(1U) ++ ++#define S_ZEROLENRD 1 ++#define V_ZEROLENRD(x) ((x) << S_ZEROLENRD) ++#define F_ZEROLENRD V_ZEROLENRD(1U) ++ + #define S_PEXERR 0 + #define V_PEXERR(x) ((x) << S_PEXERR) + #define F_PEXERR V_PEXERR(1U) + + #define A_PCIE_INT_CAUSE 0x84 ++#define A_PCIE_CFG 0x88 + + #define S_PCIE_DMASTOPEN 24 + #define V_PCIE_DMASTOPEN(x) ((x) << S_PCIE_DMASTOPEN) + #define F_PCIE_DMASTOPEN V_PCIE_DMASTOPEN(1U) + +-#define A_PCIE_CFG 0x88 ++#define S_PRIORITYINTA 23 ++#define V_PRIORITYINTA(x) ((x) << S_PRIORITYINTA) ++#define F_PRIORITYINTA V_PRIORITYINTA(1U) ++ ++#define S_INIFULLPKT 22 ++#define V_INIFULLPKT(x) ((x) << S_INIFULLPKT) ++#define F_INIFULLPKT V_INIFULLPKT(1U) + + #define S_ENABLELINKDWNDRST 21 + #define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST) +@@ -452,22 +1002,212 @@ + #define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST) + #define F_ENABLELINKDOWNRST V_ENABLELINKDOWNRST(1U) + ++#define S_ENABLEHOTRST 19 ++#define V_ENABLEHOTRST(x) ((x) << S_ENABLEHOTRST) ++#define F_ENABLEHOTRST V_ENABLEHOTRST(1U) ++ ++#define S_INIWAITFORGNT 18 ++#define V_INIWAITFORGNT(x) ((x) << S_INIWAITFORGNT) ++#define F_INIWAITFORGNT V_INIWAITFORGNT(1U) ++ ++#define S_INIBEDIS 17 ++#define V_INIBEDIS(x) ((x) << S_INIBEDIS) ++#define F_INIBEDIS V_INIBEDIS(1U) ++ + #define S_PCIE_CLIDECEN 16 + #define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN) + #define F_PCIE_CLIDECEN V_PCIE_CLIDECEN(1U) + ++#define S_PCIE_MAXSPLTRNC 7 ++#define M_PCIE_MAXSPLTRNC 0xf ++#define V_PCIE_MAXSPLTRNC(x) ((x) << S_PCIE_MAXSPLTRNC) ++#define G_PCIE_MAXSPLTRNC(x) (((x) >> S_PCIE_MAXSPLTRNC) & M_PCIE_MAXSPLTRNC) ++ ++#define S_PCIE_MAXSPLTRNR 1 ++#define M_PCIE_MAXSPLTRNR 0x3f ++#define V_PCIE_MAXSPLTRNR(x) ((x) << S_PCIE_MAXSPLTRNR) ++#define G_PCIE_MAXSPLTRNR(x) (((x) >> S_PCIE_MAXSPLTRNR) & M_PCIE_MAXSPLTRNR) ++ + #define S_CRSTWRMMODE 0 + #define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE) + #define F_CRSTWRMMODE V_CRSTWRMMODE(1U) + + #define A_PCIE_MODE 0x8c ++ ++#define S_TAR_STATE 29 ++#define M_TAR_STATE 0x7 ++#define V_TAR_STATE(x) ((x) << S_TAR_STATE) ++#define G_TAR_STATE(x) (((x) >> S_TAR_STATE) & M_TAR_STATE) ++ ++#define S_RF_STATEINI 26 ++#define M_RF_STATEINI 0x7 ++#define V_RF_STATEINI(x) ((x) << S_RF_STATEINI) ++#define G_RF_STATEINI(x) (((x) >> S_RF_STATEINI) & M_RF_STATEINI) ++ ++#define S_CF_STATEINI 23 ++#define M_CF_STATEINI 0x7 ++#define V_CF_STATEINI(x) ((x) << S_CF_STATEINI) ++#define G_CF_STATEINI(x) (((x) >> S_CF_STATEINI) & M_CF_STATEINI) ++ ++#define S_PIO_STATEPL 20 ++#define M_PIO_STATEPL 0x7 ++#define V_PIO_STATEPL(x) ((x) << S_PIO_STATEPL) ++#define G_PIO_STATEPL(x) (((x) >> S_PIO_STATEPL) & M_PIO_STATEPL) ++ ++#define S_PIO_STATEISC 18 ++#define M_PIO_STATEISC 0x3 ++#define V_PIO_STATEISC(x) ((x) << S_PIO_STATEISC) ++#define G_PIO_STATEISC(x) (((x) >> S_PIO_STATEISC) & M_PIO_STATEISC) + + #define S_NUMFSTTRNSEQRX 10 + #define M_NUMFSTTRNSEQRX 0xff + #define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX) + #define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX) + ++#define S_LNKCNTLSTATE 2 ++#define M_LNKCNTLSTATE 0xff ++#define V_LNKCNTLSTATE(x) ((x) << S_LNKCNTLSTATE) ++#define G_LNKCNTLSTATE(x) (((x) >> S_LNKCNTLSTATE) & M_LNKCNTLSTATE) ++ ++#define S_VC0UP 1 ++#define V_VC0UP(x) ((x) << S_VC0UP) ++#define F_VC0UP V_VC0UP(1U) ++ ++#define S_LNKINITIAL 0 ++#define V_LNKINITIAL(x) ((x) << S_LNKINITIAL) ++#define F_LNKINITIAL V_LNKINITIAL(1U) ++ ++#define A_PCIE_STAT 0x90 ++ ++#define S_INI_STATE 28 ++#define M_INI_STATE 0xf ++#define V_INI_STATE(x) ((x) << S_INI_STATE) ++#define G_INI_STATE(x) (((x) >> S_INI_STATE) & M_INI_STATE) ++ ++#define S_WF_STATEINI 24 ++#define M_WF_STATEINI 0xf ++#define V_WF_STATEINI(x) ((x) << S_WF_STATEINI) ++#define G_WF_STATEINI(x) (((x) >> S_WF_STATEINI) & M_WF_STATEINI) ++ ++#define S_PLM_REQFIFOCNT 22 ++#define M_PLM_REQFIFOCNT 0x3 ++#define V_PLM_REQFIFOCNT(x) ((x) << S_PLM_REQFIFOCNT) ++#define G_PLM_REQFIFOCNT(x) (((x) >> S_PLM_REQFIFOCNT) & M_PLM_REQFIFOCNT) ++ ++#define S_ER_REQFIFOEMPTY 21 ++#define V_ER_REQFIFOEMPTY(x) ((x) << S_ER_REQFIFOEMPTY) ++#define F_ER_REQFIFOEMPTY V_ER_REQFIFOEMPTY(1U) ++ ++#define S_WF_RSPFIFOEMPTY 20 ++#define V_WF_RSPFIFOEMPTY(x) ((x) << S_WF_RSPFIFOEMPTY) ++#define F_WF_RSPFIFOEMPTY V_WF_RSPFIFOEMPTY(1U) ++ ++#define S_WF_REQFIFOEMPTY 19 ++#define V_WF_REQFIFOEMPTY(x) ((x) << S_WF_REQFIFOEMPTY) ++#define F_WF_REQFIFOEMPTY V_WF_REQFIFOEMPTY(1U) ++ ++#define S_RF_RSPFIFOEMPTY 18 ++#define V_RF_RSPFIFOEMPTY(x) ((x) << S_RF_RSPFIFOEMPTY) ++#define F_RF_RSPFIFOEMPTY V_RF_RSPFIFOEMPTY(1U) ++ ++#define S_RF_REQFIFOEMPTY 17 ++#define V_RF_REQFIFOEMPTY(x) ((x) << S_RF_REQFIFOEMPTY) ++#define F_RF_REQFIFOEMPTY V_RF_REQFIFOEMPTY(1U) ++ ++#define S_RF_ACTEMPTY 16 ++#define V_RF_ACTEMPTY(x) ((x) << S_RF_ACTEMPTY) ++#define F_RF_ACTEMPTY V_RF_ACTEMPTY(1U) ++ ++#define S_PIO_RSPFIFOCNT 11 ++#define M_PIO_RSPFIFOCNT 0x1f ++#define V_PIO_RSPFIFOCNT(x) ((x) << S_PIO_RSPFIFOCNT) ++#define G_PIO_RSPFIFOCNT(x) (((x) >> S_PIO_RSPFIFOCNT) & M_PIO_RSPFIFOCNT) ++ ++#define S_PIO_REQFIFOCNT 5 ++#define M_PIO_REQFIFOCNT 0x3f ++#define V_PIO_REQFIFOCNT(x) ((x) << S_PIO_REQFIFOCNT) ++#define G_PIO_REQFIFOCNT(x) (((x) >> S_PIO_REQFIFOCNT) & M_PIO_REQFIFOCNT) ++ ++#define S_CF_RSPFIFOEMPTY 4 ++#define V_CF_RSPFIFOEMPTY(x) ((x) << S_CF_RSPFIFOEMPTY) ++#define F_CF_RSPFIFOEMPTY V_CF_RSPFIFOEMPTY(1U) ++ ++#define S_CF_REQFIFOEMPTY 3 ++#define V_CF_REQFIFOEMPTY(x) ((x) << S_CF_REQFIFOEMPTY) ++#define F_CF_REQFIFOEMPTY V_CF_REQFIFOEMPTY(1U) ++ ++#define S_CF_ACTEMPTY 2 ++#define V_CF_ACTEMPTY(x) ((x) << S_CF_ACTEMPTY) ++#define F_CF_ACTEMPTY V_CF_ACTEMPTY(1U) ++ ++#define S_VPD_RSPFIFOEMPTY 1 ++#define V_VPD_RSPFIFOEMPTY(x) ((x) << S_VPD_RSPFIFOEMPTY) ++#define F_VPD_RSPFIFOEMPTY V_VPD_RSPFIFOEMPTY(1U) ++ ++#define S_VPD_REQFIFOEMPTY 0 ++#define V_VPD_REQFIFOEMPTY(x) ((x) << S_VPD_REQFIFOEMPTY) ++#define F_VPD_REQFIFOEMPTY V_VPD_REQFIFOEMPTY(1U) ++ ++#define A_PCIE_CAL 0x90 ++ ++#define S_CALBUSY 31 ++#define V_CALBUSY(x) ((x) << S_CALBUSY) ++#define F_CALBUSY V_CALBUSY(1U) ++ ++#define S_CALFAULT 30 ++#define V_CALFAULT(x) ((x) << S_CALFAULT) ++#define F_CALFAULT V_CALFAULT(1U) ++ ++#define S_PCIE_ZINSEL 11 ++#define V_PCIE_ZINSEL(x) ((x) << S_PCIE_ZINSEL) ++#define F_PCIE_ZINSEL V_PCIE_ZINSEL(1U) ++ ++#define S_ZMAN 8 ++#define M_ZMAN 0x7 ++#define V_ZMAN(x) ((x) << S_ZMAN) ++#define G_ZMAN(x) (((x) >> S_ZMAN) & M_ZMAN) ++ ++#define S_ZOUT 3 ++#define M_ZOUT 0x1f ++#define V_ZOUT(x) ((x) << S_ZOUT) ++#define G_ZOUT(x) (((x) >> S_ZOUT) & M_ZOUT) ++ ++#define S_ZIN 0 ++#define M_ZIN 0x7 ++#define V_ZIN(x) ((x) << S_ZIN) ++#define G_ZIN(x) (((x) >> S_ZIN) & M_ZIN) ++ ++#define A_PCIE_WOL 0x94 ++ ++#define S_CF_RSPSTATE 12 ++#define M_CF_RSPSTATE 0x3 ++#define V_CF_RSPSTATE(x) ((x) << S_CF_RSPSTATE) ++#define G_CF_RSPSTATE(x) (((x) >> S_CF_RSPSTATE) & M_CF_RSPSTATE) ++ ++#define S_RF_RSPSTATE 10 ++#define M_RF_RSPSTATE 0x3 ++#define V_RF_RSPSTATE(x) ((x) << S_RF_RSPSTATE) ++#define G_RF_RSPSTATE(x) (((x) >> S_RF_RSPSTATE) & M_RF_RSPSTATE) ++ ++#define S_PME_STATE 7 ++#define M_PME_STATE 0x7 ++#define V_PME_STATE(x) ((x) << S_PME_STATE) ++#define G_PME_STATE(x) (((x) >> S_PME_STATE) & M_PME_STATE) ++ ++#define S_INT_STATE 4 ++#define M_INT_STATE 0x7 ++#define V_INT_STATE(x) ((x) << S_INT_STATE) ++#define G_INT_STATE(x) (((x) >> S_INT_STATE) & M_INT_STATE) ++ + #define A_PCIE_PEX_CTRL0 0x98 ++ ++#define S_CPLTIMEOUTRETRY 31 ++#define V_CPLTIMEOUTRETRY(x) ((x) << S_CPLTIMEOUTRETRY) ++#define F_CPLTIMEOUTRETRY V_CPLTIMEOUTRETRY(1U) ++ ++#define S_STRICTTSMN 30 ++#define V_STRICTTSMN(x) ((x) << S_STRICTTSMN) ++#define F_STRICTTSMN V_STRICTTSMN(1U) + + #define S_NUMFSTTRNSEQ 22 + #define M_NUMFSTTRNSEQ 0xff +@@ -476,23 +1216,854 @@ + + #define S_REPLAYLMT 2 + #define M_REPLAYLMT 0xfffff +- + #define V_REPLAYLMT(x) ((x) << S_REPLAYLMT) ++#define G_REPLAYLMT(x) (((x) >> S_REPLAYLMT) & M_REPLAYLMT) ++ ++#define S_TXPNDCHKEN 1 ++#define V_TXPNDCHKEN(x) ((x) << S_TXPNDCHKEN) ++#define F_TXPNDCHKEN V_TXPNDCHKEN(1U) ++ ++#define S_CPLPNDCHKEN 0 ++#define V_CPLPNDCHKEN(x) ((x) << S_CPLPNDCHKEN) ++#define F_CPLPNDCHKEN V_CPLPNDCHKEN(1U) + + #define A_PCIE_PEX_CTRL1 0x9c ++ ++#define S_RXPHYERREN 31 ++#define V_RXPHYERREN(x) ((x) << S_RXPHYERREN) ++#define F_RXPHYERREN V_RXPHYERREN(1U) ++ ++#define S_DLLPTIMEOUTLMT 13 ++#define M_DLLPTIMEOUTLMT 0x3ffff ++#define V_DLLPTIMEOUTLMT(x) ((x) << S_DLLPTIMEOUTLMT) ++#define G_DLLPTIMEOUTLMT(x) (((x) >> S_DLLPTIMEOUTLMT) & M_DLLPTIMEOUTLMT) ++ ++#define S_ACKLAT 0 ++#define M_ACKLAT 0x1fff ++#define V_ACKLAT(x) ((x) << S_ACKLAT) ++#define G_ACKLAT(x) (((x) >> S_ACKLAT) & M_ACKLAT) ++ ++#define S_T3A_DLLPTIMEOUTLMT 11 ++#define M_T3A_DLLPTIMEOUTLMT 0xfffff ++#define V_T3A_DLLPTIMEOUTLMT(x) ((x) << S_T3A_DLLPTIMEOUTLMT) ++#define G_T3A_DLLPTIMEOUTLMT(x) (((x) >> S_T3A_DLLPTIMEOUTLMT) & M_T3A_DLLPTIMEOUTLMT) + + #define S_T3A_ACKLAT 0 + #define M_T3A_ACKLAT 0x7ff +- + #define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT) +- +-#define S_ACKLAT 0 +-#define M_ACKLAT 0x1fff +- +-#define V_ACKLAT(x) ((x) << S_ACKLAT) ++#define G_T3A_ACKLAT(x) (((x) >> S_T3A_ACKLAT) & M_T3A_ACKLAT) ++ ++#define A_PCIE_PEX_CTRL2 0xa0 ++ ++#define S_LNKCNTLDETDIR 30 ++#define V_LNKCNTLDETDIR(x) ((x) << S_LNKCNTLDETDIR) ++#define F_LNKCNTLDETDIR V_LNKCNTLDETDIR(1U) ++ ++#define S_ENTERL1REN 29 ++#define V_ENTERL1REN(x) ((x) << S_ENTERL1REN) ++#define F_ENTERL1REN V_ENTERL1REN(1U) ++ ++#define S_PMEXITL1REQ 28 ++#define V_PMEXITL1REQ(x) ((x) << S_PMEXITL1REQ) ++#define F_PMEXITL1REQ V_PMEXITL1REQ(1U) ++ ++#define S_PMTXIDLE 27 ++#define V_PMTXIDLE(x) ((x) << S_PMTXIDLE) ++#define F_PMTXIDLE V_PMTXIDLE(1U) ++ ++#define S_PCIMODELOOP 26 ++#define V_PCIMODELOOP(x) ((x) << S_PCIMODELOOP) ++#define F_PCIMODELOOP V_PCIMODELOOP(1U) ++ ++#define S_L1ASPMTXRXL0STIME 14 ++#define M_L1ASPMTXRXL0STIME 0xfff ++#define V_L1ASPMTXRXL0STIME(x) ((x) << S_L1ASPMTXRXL0STIME) ++#define G_L1ASPMTXRXL0STIME(x) (((x) >> S_L1ASPMTXRXL0STIME) & M_L1ASPMTXRXL0STIME) ++ ++#define S_L0SIDLETIME 3 ++#define M_L0SIDLETIME 0x7ff ++#define V_L0SIDLETIME(x) ((x) << S_L0SIDLETIME) ++#define G_L0SIDLETIME(x) (((x) >> S_L0SIDLETIME) & M_L0SIDLETIME) ++ ++#define S_ENTERL1ASPMEN 2 ++#define V_ENTERL1ASPMEN(x) ((x) << S_ENTERL1ASPMEN) ++#define F_ENTERL1ASPMEN V_ENTERL1ASPMEN(1U) ++ ++#define S_ENTERL1EN 1 ++#define V_ENTERL1EN(x) ((x) << S_ENTERL1EN) ++#define F_ENTERL1EN V_ENTERL1EN(1U) ++ ++#define S_ENTERL0SEN 0 ++#define V_ENTERL0SEN(x) ((x) << S_ENTERL0SEN) ++#define F_ENTERL0SEN V_ENTERL0SEN(1U) ++ ++#define S_ENTERL23 3 ++#define V_ENTERL23(x) ((x) << S_ENTERL23) ++#define F_ENTERL23 V_ENTERL23(1U) + + #define A_PCIE_PEX_ERR 0xa4 + ++#define S_CPLTIMEOUTID 18 ++#define M_CPLTIMEOUTID 0x7f ++#define V_CPLTIMEOUTID(x) ((x) << S_CPLTIMEOUTID) ++#define G_CPLTIMEOUTID(x) (((x) >> S_CPLTIMEOUTID) & M_CPLTIMEOUTID) ++ ++#define S_FLOWCTLOFLOWERR 17 ++#define V_FLOWCTLOFLOWERR(x) ((x) << S_FLOWCTLOFLOWERR) ++#define F_FLOWCTLOFLOWERR V_FLOWCTLOFLOWERR(1U) ++ ++#define S_REPLAYTIMEOUT 16 ++#define V_REPLAYTIMEOUT(x) ((x) << S_REPLAYTIMEOUT) ++#define F_REPLAYTIMEOUT V_REPLAYTIMEOUT(1U) ++ ++#define S_REPLAYROLLOVER 15 ++#define V_REPLAYROLLOVER(x) ((x) << S_REPLAYROLLOVER) ++#define F_REPLAYROLLOVER V_REPLAYROLLOVER(1U) ++ ++#define S_BADDLLP 14 ++#define V_BADDLLP(x) ((x) << S_BADDLLP) ++#define F_BADDLLP V_BADDLLP(1U) ++ ++#define S_DLLPERR 13 ++#define V_DLLPERR(x) ((x) << S_DLLPERR) ++#define F_DLLPERR V_DLLPERR(1U) ++ ++#define S_FLOWCTLPROTERR 12 ++#define V_FLOWCTLPROTERR(x) ((x) << S_FLOWCTLPROTERR) ++#define F_FLOWCTLPROTERR V_FLOWCTLPROTERR(1U) ++ ++#define S_CPLTIMEOUT 11 ++#define V_CPLTIMEOUT(x) ((x) << S_CPLTIMEOUT) ++#define F_CPLTIMEOUT V_CPLTIMEOUT(1U) ++ ++#define S_PHYRCVERR 10 ++#define V_PHYRCVERR(x) ((x) << S_PHYRCVERR) ++#define F_PHYRCVERR V_PHYRCVERR(1U) ++ ++#define S_DISTLP 9 ++#define V_DISTLP(x) ((x) << S_DISTLP) ++#define F_DISTLP V_DISTLP(1U) ++ ++#define S_BADECRC 8 ++#define V_BADECRC(x) ((x) << S_BADECRC) ++#define F_BADECRC V_BADECRC(1U) ++ ++#define S_BADTLP 7 ++#define V_BADTLP(x) ((x) << S_BADTLP) ++#define F_BADTLP V_BADTLP(1U) ++ ++#define S_MALTLP 6 ++#define V_MALTLP(x) ((x) << S_MALTLP) ++#define F_MALTLP V_MALTLP(1U) ++ ++#define S_UNXCPL 5 ++#define V_UNXCPL(x) ((x) << S_UNXCPL) ++#define F_UNXCPL V_UNXCPL(1U) ++ ++#define S_UNSREQ 4 ++#define V_UNSREQ(x) ((x) << S_UNSREQ) ++#define F_UNSREQ V_UNSREQ(1U) ++ ++#define S_PSNREQ 3 ++#define V_PSNREQ(x) ((x) << S_PSNREQ) ++#define F_PSNREQ V_PSNREQ(1U) ++ ++#define S_UNSCPL 2 ++#define V_UNSCPL(x) ((x) << S_UNSCPL) ++#define F_UNSCPL V_UNSCPL(1U) ++ ++#define S_CPLABT 1 ++#define V_CPLABT(x) ((x) << S_CPLABT) ++#define F_CPLABT V_CPLABT(1U) ++ ++#define S_PSNCPL 0 ++#define V_PSNCPL(x) ((x) << S_PSNCPL) ++#define F_PSNCPL V_PSNCPL(1U) ++ ++#define A_PCIE_SERDES_CTRL 0xa8 ++ ++#define S_PMASEL 3 ++#define V_PMASEL(x) ((x) << S_PMASEL) ++#define F_PMASEL V_PMASEL(1U) ++ ++#define S_LANE 0 ++#define M_LANE 0x7 ++#define V_LANE(x) ((x) << S_LANE) ++#define G_LANE(x) (((x) >> S_LANE) & M_LANE) ++ ++#define A_PCIE_PIPE_CTRL 0xa8 ++ ++#define S_RECDETUSEC 19 ++#define M_RECDETUSEC 0x7 ++#define V_RECDETUSEC(x) ((x) << S_RECDETUSEC) ++#define G_RECDETUSEC(x) (((x) >> S_RECDETUSEC) & M_RECDETUSEC) ++ ++#define S_PLLLCKCYC 6 ++#define M_PLLLCKCYC 0x1fff ++#define V_PLLLCKCYC(x) ((x) << S_PLLLCKCYC) ++#define G_PLLLCKCYC(x) (((x) >> S_PLLLCKCYC) & M_PLLLCKCYC) ++ ++#define S_ELECIDLEDETCYC 3 ++#define M_ELECIDLEDETCYC 0x7 ++#define V_ELECIDLEDETCYC(x) ((x) << S_ELECIDLEDETCYC) ++#define G_ELECIDLEDETCYC(x) (((x) >> S_ELECIDLEDETCYC) & M_ELECIDLEDETCYC) ++ ++#define S_USECDRLOS 2 ++#define V_USECDRLOS(x) ((x) << S_USECDRLOS) ++#define F_USECDRLOS V_USECDRLOS(1U) ++ ++#define S_PCLKREQINP1 1 ++#define V_PCLKREQINP1(x) ((x) << S_PCLKREQINP1) ++#define F_PCLKREQINP1 V_PCLKREQINP1(1U) ++ ++#define S_PCLKOFFINP1 0 ++#define V_PCLKOFFINP1(x) ((x) << S_PCLKOFFINP1) ++#define F_PCLKOFFINP1 V_PCLKOFFINP1(1U) ++ ++#define A_PCIE_SERDES_QUAD_CTRL0 0xac ++ ++#define S_TESTSIG 10 ++#define M_TESTSIG 0x7ffff ++#define V_TESTSIG(x) ((x) << S_TESTSIG) ++#define G_TESTSIG(x) (((x) >> S_TESTSIG) & M_TESTSIG) ++ ++#define S_OFFSET 2 ++#define M_OFFSET 0xff ++#define V_OFFSET(x) ((x) << S_OFFSET) ++#define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET) ++ ++#define S_OFFSETEN 1 ++#define V_OFFSETEN(x) ((x) << S_OFFSETEN) ++#define F_OFFSETEN V_OFFSETEN(1U) ++ ++#define S_IDDQB 0 ++#define V_IDDQB(x) ((x) << S_IDDQB) ++#define F_IDDQB V_IDDQB(1U) ++ ++#define S_MANMODE 31 ++#define V_MANMODE(x) ((x) << S_MANMODE) ++#define F_MANMODE V_MANMODE(1U) ++ ++#define S_MANLPBKEN 29 ++#define M_MANLPBKEN 0x3 ++#define V_MANLPBKEN(x) ((x) << S_MANLPBKEN) ++#define G_MANLPBKEN(x) (((x) >> S_MANLPBKEN) & M_MANLPBKEN) ++ ++#define S_MANTXRECDETEN 28 ++#define V_MANTXRECDETEN(x) ((x) << S_MANTXRECDETEN) ++#define F_MANTXRECDETEN V_MANTXRECDETEN(1U) ++ ++#define S_MANTXBEACON 27 ++#define V_MANTXBEACON(x) ((x) << S_MANTXBEACON) ++#define F_MANTXBEACON V_MANTXBEACON(1U) ++ ++#define S_MANTXEI 26 ++#define V_MANTXEI(x) ((x) << S_MANTXEI) ++#define F_MANTXEI V_MANTXEI(1U) ++ ++#define S_MANRXPOLARITY 25 ++#define V_MANRXPOLARITY(x) ((x) << S_MANRXPOLARITY) ++#define F_MANRXPOLARITY V_MANRXPOLARITY(1U) ++ ++#define S_MANTXRST 24 ++#define V_MANTXRST(x) ((x) << S_MANTXRST) ++#define F_MANTXRST V_MANTXRST(1U) ++ ++#define S_MANRXRST 23 ++#define V_MANRXRST(x) ((x) << S_MANRXRST) ++#define F_MANRXRST V_MANRXRST(1U) ++ ++#define S_MANTXEN 22 ++#define V_MANTXEN(x) ((x) << S_MANTXEN) ++#define F_MANTXEN V_MANTXEN(1U) ++ ++#define S_MANRXEN 21 ++#define V_MANRXEN(x) ((x) << S_MANRXEN) ++#define F_MANRXEN V_MANRXEN(1U) ++ ++#define S_MANEN 20 ++#define V_MANEN(x) ((x) << S_MANEN) ++#define F_MANEN V_MANEN(1U) ++ ++#define S_PCIE_CMURANGE 17 ++#define M_PCIE_CMURANGE 0x7 ++#define V_PCIE_CMURANGE(x) ((x) << S_PCIE_CMURANGE) ++#define G_PCIE_CMURANGE(x) (((x) >> S_PCIE_CMURANGE) & M_PCIE_CMURANGE) ++ ++#define S_PCIE_BGENB 16 ++#define V_PCIE_BGENB(x) ((x) << S_PCIE_BGENB) ++#define F_PCIE_BGENB V_PCIE_BGENB(1U) ++ ++#define S_PCIE_ENSKPDROP 15 ++#define V_PCIE_ENSKPDROP(x) ((x) << S_PCIE_ENSKPDROP) ++#define F_PCIE_ENSKPDROP V_PCIE_ENSKPDROP(1U) ++ ++#define S_PCIE_ENCOMMA 14 ++#define V_PCIE_ENCOMMA(x) ((x) << S_PCIE_ENCOMMA) ++#define F_PCIE_ENCOMMA V_PCIE_ENCOMMA(1U) ++ ++#define S_PCIE_EN8B10B 13 ++#define V_PCIE_EN8B10B(x) ((x) << S_PCIE_EN8B10B) ++#define F_PCIE_EN8B10B V_PCIE_EN8B10B(1U) ++ ++#define S_PCIE_ENELBUF 12 ++#define V_PCIE_ENELBUF(x) ((x) << S_PCIE_ENELBUF) ++#define F_PCIE_ENELBUF V_PCIE_ENELBUF(1U) ++ ++#define S_PCIE_GAIN 7 ++#define M_PCIE_GAIN 0x1f ++#define V_PCIE_GAIN(x) ((x) << S_PCIE_GAIN) ++#define G_PCIE_GAIN(x) (((x) >> S_PCIE_GAIN) & M_PCIE_GAIN) ++ ++#define S_PCIE_BANDGAP 3 ++#define M_PCIE_BANDGAP 0xf ++#define V_PCIE_BANDGAP(x) ((x) << S_PCIE_BANDGAP) ++#define G_PCIE_BANDGAP(x) (((x) >> S_PCIE_BANDGAP) & M_PCIE_BANDGAP) ++ ++#define S_RXCOMADJ 2 ++#define V_RXCOMADJ(x) ((x) << S_RXCOMADJ) ++#define F_RXCOMADJ V_RXCOMADJ(1U) ++ ++#define S_PREEMPH 0 ++#define M_PREEMPH 0x3 ++#define V_PREEMPH(x) ((x) << S_PREEMPH) ++#define G_PREEMPH(x) (((x) >> S_PREEMPH) & M_PREEMPH) ++ ++#define A_PCIE_SERDES_QUAD_CTRL1 0xb0 ++ ++#define S_FASTINIT 28 ++#define V_FASTINIT(x) ((x) << S_FASTINIT) ++#define F_FASTINIT V_FASTINIT(1U) ++ ++#define S_CTCDISABLE 27 ++#define V_CTCDISABLE(x) ((x) << S_CTCDISABLE) ++#define F_CTCDISABLE V_CTCDISABLE(1U) ++ ++#define S_MANRESETPLL 26 ++#define V_MANRESETPLL(x) ((x) << S_MANRESETPLL) ++#define F_MANRESETPLL V_MANRESETPLL(1U) ++ ++#define S_MANL2PWRDN 25 ++#define V_MANL2PWRDN(x) ((x) << S_MANL2PWRDN) ++#define F_MANL2PWRDN V_MANL2PWRDN(1U) ++ ++#define S_MANQUADEN 24 ++#define V_MANQUADEN(x) ((x) << S_MANQUADEN) ++#define F_MANQUADEN V_MANQUADEN(1U) ++ ++#define S_RXEQCTL 22 ++#define M_RXEQCTL 0x3 ++#define V_RXEQCTL(x) ((x) << S_RXEQCTL) ++#define G_RXEQCTL(x) (((x) >> S_RXEQCTL) & M_RXEQCTL) ++ ++#define S_HIVMODE 21 ++#define V_HIVMODE(x) ((x) << S_HIVMODE) ++#define F_HIVMODE V_HIVMODE(1U) ++ ++#define S_REFSEL 19 ++#define M_REFSEL 0x3 ++#define V_REFSEL(x) ((x) << S_REFSEL) ++#define G_REFSEL(x) (((x) >> S_REFSEL) & M_REFSEL) ++ ++#define S_RXTERMADJ 17 ++#define M_RXTERMADJ 0x3 ++#define V_RXTERMADJ(x) ((x) << S_RXTERMADJ) ++#define G_RXTERMADJ(x) (((x) >> S_RXTERMADJ) & M_RXTERMADJ) ++ ++#define S_TXTERMADJ 15 ++#define M_TXTERMADJ 0x3 ++#define V_TXTERMADJ(x) ((x) << S_TXTERMADJ) ++#define G_TXTERMADJ(x) (((x) >> S_TXTERMADJ) & M_TXTERMADJ) ++ ++#define S_DEQ 11 ++#define M_DEQ 0xf ++#define V_DEQ(x) ((x) << S_DEQ) ++#define G_DEQ(x) (((x) >> S_DEQ) & M_DEQ) ++ ++#define S_DTX 7 ++#define M_DTX 0xf ++#define V_DTX(x) ((x) << S_DTX) ++#define G_DTX(x) (((x) >> S_DTX) & M_DTX) ++ ++#define S_LODRV 6 ++#define V_LODRV(x) ((x) << S_LODRV) ++#define F_LODRV V_LODRV(1U) ++ ++#define S_HIDRV 5 ++#define V_HIDRV(x) ((x) << S_HIDRV) ++#define F_HIDRV V_HIDRV(1U) ++ ++#define S_INTPARRESET 4 ++#define V_INTPARRESET(x) ((x) << S_INTPARRESET) ++#define F_INTPARRESET V_INTPARRESET(1U) ++ ++#define S_INTPARLPBK 3 ++#define V_INTPARLPBK(x) ((x) << S_INTPARLPBK) ++#define F_INTPARLPBK V_INTPARLPBK(1U) ++ ++#define S_INTSERLPBKWDRV 2 ++#define V_INTSERLPBKWDRV(x) ((x) << S_INTSERLPBKWDRV) ++#define F_INTSERLPBKWDRV V_INTSERLPBKWDRV(1U) ++ ++#define S_PW 1 ++#define V_PW(x) ((x) << S_PW) ++#define F_PW V_PW(1U) ++ ++#define S_PCLKDETECT 0 ++#define V_PCLKDETECT(x) ((x) << S_PCLKDETECT) ++#define F_PCLKDETECT V_PCLKDETECT(1U) ++ ++#define A_PCIE_SERDES_STATUS0 0xb0 ++ ++#define S_RXERRLANE7 21 ++#define M_RXERRLANE7 0x7 ++#define V_RXERRLANE7(x) ((x) << S_RXERRLANE7) ++#define G_RXERRLANE7(x) (((x) >> S_RXERRLANE7) & M_RXERRLANE7) ++ ++#define S_RXERRLANE6 18 ++#define M_RXERRLANE6 0x7 ++#define V_RXERRLANE6(x) ((x) << S_RXERRLANE6) ++#define G_RXERRLANE6(x) (((x) >> S_RXERRLANE6) & M_RXERRLANE6) ++ ++#define S_RXERRLANE5 15 ++#define M_RXERRLANE5 0x7 ++#define V_RXERRLANE5(x) ((x) << S_RXERRLANE5) ++#define G_RXERRLANE5(x) (((x) >> S_RXERRLANE5) & M_RXERRLANE5) ++ ++#define S_RXERRLANE4 12 ++#define M_RXERRLANE4 0x7 ++#define V_RXERRLANE4(x) ((x) << S_RXERRLANE4) ++#define G_RXERRLANE4(x) (((x) >> S_RXERRLANE4) & M_RXERRLANE4) ++ ++#define S_PCIE_RXERRLANE3 9 ++#define M_PCIE_RXERRLANE3 0x7 ++#define V_PCIE_RXERRLANE3(x) ((x) << S_PCIE_RXERRLANE3) ++#define G_PCIE_RXERRLANE3(x) (((x) >> S_PCIE_RXERRLANE3) & M_PCIE_RXERRLANE3) ++ ++#define S_PCIE_RXERRLANE2 6 ++#define M_PCIE_RXERRLANE2 0x7 ++#define V_PCIE_RXERRLANE2(x) ((x) << S_PCIE_RXERRLANE2) ++#define G_PCIE_RXERRLANE2(x) (((x) >> S_PCIE_RXERRLANE2) & M_PCIE_RXERRLANE2) ++ ++#define S_PCIE_RXERRLANE1 3 ++#define M_PCIE_RXERRLANE1 0x7 ++#define V_PCIE_RXERRLANE1(x) ((x) << S_PCIE_RXERRLANE1) ++#define G_PCIE_RXERRLANE1(x) (((x) >> S_PCIE_RXERRLANE1) & M_PCIE_RXERRLANE1) ++ ++#define S_PCIE_RXERRLANE0 0 ++#define M_PCIE_RXERRLANE0 0x7 ++#define V_PCIE_RXERRLANE0(x) ((x) << S_PCIE_RXERRLANE0) ++#define G_PCIE_RXERRLANE0(x) (((x) >> S_PCIE_RXERRLANE0) & M_PCIE_RXERRLANE0) ++ ++#define A_PCIE_SERDES_LANE_CTRL 0xb4 ++ ++#define S_EXTBISTCHKERRCLR 22 ++#define V_EXTBISTCHKERRCLR(x) ((x) << S_EXTBISTCHKERRCLR) ++#define F_EXTBISTCHKERRCLR V_EXTBISTCHKERRCLR(1U) ++ ++#define S_EXTBISTCHKEN 21 ++#define V_EXTBISTCHKEN(x) ((x) << S_EXTBISTCHKEN) ++#define F_EXTBISTCHKEN V_EXTBISTCHKEN(1U) ++ ++#define S_EXTBISTGENEN 20 ++#define V_EXTBISTGENEN(x) ((x) << S_EXTBISTGENEN) ++#define F_EXTBISTGENEN V_EXTBISTGENEN(1U) ++ ++#define S_EXTBISTPAT 17 ++#define M_EXTBISTPAT 0x7 ++#define V_EXTBISTPAT(x) ((x) << S_EXTBISTPAT) ++#define G_EXTBISTPAT(x) (((x) >> S_EXTBISTPAT) & M_EXTBISTPAT) ++ ++#define S_EXTPARRESET 16 ++#define V_EXTPARRESET(x) ((x) << S_EXTPARRESET) ++#define F_EXTPARRESET V_EXTPARRESET(1U) ++ ++#define S_EXTPARLPBK 15 ++#define V_EXTPARLPBK(x) ((x) << S_EXTPARLPBK) ++#define F_EXTPARLPBK V_EXTPARLPBK(1U) ++ ++#define S_MANRXTERMEN 14 ++#define V_MANRXTERMEN(x) ((x) << S_MANRXTERMEN) ++#define F_MANRXTERMEN V_MANRXTERMEN(1U) ++ ++#define S_MANBEACONTXEN 13 ++#define V_MANBEACONTXEN(x) ((x) << S_MANBEACONTXEN) ++#define F_MANBEACONTXEN V_MANBEACONTXEN(1U) ++ ++#define S_MANRXDETECTEN 12 ++#define V_MANRXDETECTEN(x) ((x) << S_MANRXDETECTEN) ++#define F_MANRXDETECTEN V_MANRXDETECTEN(1U) ++ ++#define S_MANTXIDLEEN 11 ++#define V_MANTXIDLEEN(x) ((x) << S_MANTXIDLEEN) ++#define F_MANTXIDLEEN V_MANTXIDLEEN(1U) ++ ++#define S_MANRXIDLEEN 10 ++#define V_MANRXIDLEEN(x) ((x) << S_MANRXIDLEEN) ++#define F_MANRXIDLEEN V_MANRXIDLEEN(1U) ++ ++#define S_MANL1PWRDN 9 ++#define V_MANL1PWRDN(x) ((x) << S_MANL1PWRDN) ++#define F_MANL1PWRDN V_MANL1PWRDN(1U) ++ ++#define S_MANRESET 8 ++#define V_MANRESET(x) ((x) << S_MANRESET) ++#define F_MANRESET V_MANRESET(1U) ++ ++#define S_MANFMOFFSET 3 ++#define M_MANFMOFFSET 0x1f ++#define V_MANFMOFFSET(x) ((x) << S_MANFMOFFSET) ++#define G_MANFMOFFSET(x) (((x) >> S_MANFMOFFSET) & M_MANFMOFFSET) ++ ++#define S_MANFMOFFSETEN 2 ++#define V_MANFMOFFSETEN(x) ((x) << S_MANFMOFFSETEN) ++#define F_MANFMOFFSETEN V_MANFMOFFSETEN(1U) ++ ++#define S_MANLANEEN 1 ++#define V_MANLANEEN(x) ((x) << S_MANLANEEN) ++#define F_MANLANEEN V_MANLANEEN(1U) ++ ++#define S_INTSERLPBK 0 ++#define V_INTSERLPBK(x) ((x) << S_INTSERLPBK) ++#define F_INTSERLPBK V_INTSERLPBK(1U) ++ ++#define A_PCIE_SERDES_STATUS1 0xb4 ++ ++#define S_CMULOCK 31 ++#define V_CMULOCK(x) ((x) << S_CMULOCK) ++#define F_CMULOCK V_CMULOCK(1U) ++ ++#define S_RXKLOCKLANE7 23 ++#define V_RXKLOCKLANE7(x) ((x) << S_RXKLOCKLANE7) ++#define F_RXKLOCKLANE7 V_RXKLOCKLANE7(1U) ++ ++#define S_RXKLOCKLANE6 22 ++#define V_RXKLOCKLANE6(x) ((x) << S_RXKLOCKLANE6) ++#define F_RXKLOCKLANE6 V_RXKLOCKLANE6(1U) ++ ++#define S_RXKLOCKLANE5 21 ++#define V_RXKLOCKLANE5(x) ((x) << S_RXKLOCKLANE5) ++#define F_RXKLOCKLANE5 V_RXKLOCKLANE5(1U) ++ ++#define S_RXKLOCKLANE4 20 ++#define V_RXKLOCKLANE4(x) ((x) << S_RXKLOCKLANE4) ++#define F_RXKLOCKLANE4 V_RXKLOCKLANE4(1U) ++ ++#define S_PCIE_RXKLOCKLANE3 19 ++#define V_PCIE_RXKLOCKLANE3(x) ((x) << S_PCIE_RXKLOCKLANE3) ++#define F_PCIE_RXKLOCKLANE3 V_PCIE_RXKLOCKLANE3(1U) ++ ++#define S_PCIE_RXKLOCKLANE2 18 ++#define V_PCIE_RXKLOCKLANE2(x) ((x) << S_PCIE_RXKLOCKLANE2) ++#define F_PCIE_RXKLOCKLANE2 V_PCIE_RXKLOCKLANE2(1U) ++ ++#define S_PCIE_RXKLOCKLANE1 17 ++#define V_PCIE_RXKLOCKLANE1(x) ((x) << S_PCIE_RXKLOCKLANE1) ++#define F_PCIE_RXKLOCKLANE1 V_PCIE_RXKLOCKLANE1(1U) ++ ++#define S_PCIE_RXKLOCKLANE0 16 ++#define V_PCIE_RXKLOCKLANE0(x) ((x) << S_PCIE_RXKLOCKLANE0) ++#define F_PCIE_RXKLOCKLANE0 V_PCIE_RXKLOCKLANE0(1U) ++ ++#define S_RXUFLOWLANE7 15 ++#define V_RXUFLOWLANE7(x) ((x) << S_RXUFLOWLANE7) ++#define F_RXUFLOWLANE7 V_RXUFLOWLANE7(1U) ++ ++#define S_RXUFLOWLANE6 14 ++#define V_RXUFLOWLANE6(x) ((x) << S_RXUFLOWLANE6) ++#define F_RXUFLOWLANE6 V_RXUFLOWLANE6(1U) ++ ++#define S_RXUFLOWLANE5 13 ++#define V_RXUFLOWLANE5(x) ((x) << S_RXUFLOWLANE5) ++#define F_RXUFLOWLANE5 V_RXUFLOWLANE5(1U) ++ ++#define S_RXUFLOWLANE4 12 ++#define V_RXUFLOWLANE4(x) ((x) << S_RXUFLOWLANE4) ++#define F_RXUFLOWLANE4 V_RXUFLOWLANE4(1U) ++ ++#define S_PCIE_RXUFLOWLANE3 11 ++#define V_PCIE_RXUFLOWLANE3(x) ((x) << S_PCIE_RXUFLOWLANE3) ++#define F_PCIE_RXUFLOWLANE3 V_PCIE_RXUFLOWLANE3(1U) ++ ++#define S_PCIE_RXUFLOWLANE2 10 ++#define V_PCIE_RXUFLOWLANE2(x) ((x) << S_PCIE_RXUFLOWLANE2) ++#define F_PCIE_RXUFLOWLANE2 V_PCIE_RXUFLOWLANE2(1U) ++ ++#define S_PCIE_RXUFLOWLANE1 9 ++#define V_PCIE_RXUFLOWLANE1(x) ((x) << S_PCIE_RXUFLOWLANE1) ++#define F_PCIE_RXUFLOWLANE1 V_PCIE_RXUFLOWLANE1(1U) ++ ++#define S_PCIE_RXUFLOWLANE0 8 ++#define V_PCIE_RXUFLOWLANE0(x) ((x) << S_PCIE_RXUFLOWLANE0) ++#define F_PCIE_RXUFLOWLANE0 V_PCIE_RXUFLOWLANE0(1U) ++ ++#define S_RXOFLOWLANE7 7 ++#define V_RXOFLOWLANE7(x) ((x) << S_RXOFLOWLANE7) ++#define F_RXOFLOWLANE7 V_RXOFLOWLANE7(1U) ++ ++#define S_RXOFLOWLANE6 6 ++#define V_RXOFLOWLANE6(x) ((x) << S_RXOFLOWLANE6) ++#define F_RXOFLOWLANE6 V_RXOFLOWLANE6(1U) ++ ++#define S_RXOFLOWLANE5 5 ++#define V_RXOFLOWLANE5(x) ((x) << S_RXOFLOWLANE5) ++#define F_RXOFLOWLANE5 V_RXOFLOWLANE5(1U) ++ ++#define S_RXOFLOWLANE4 4 ++#define V_RXOFLOWLANE4(x) ((x) << S_RXOFLOWLANE4) ++#define F_RXOFLOWLANE4 V_RXOFLOWLANE4(1U) ++ ++#define S_PCIE_RXOFLOWLANE3 3 ++#define V_PCIE_RXOFLOWLANE3(x) ((x) << S_PCIE_RXOFLOWLANE3) ++#define F_PCIE_RXOFLOWLANE3 V_PCIE_RXOFLOWLANE3(1U) ++ ++#define S_PCIE_RXOFLOWLANE2 2 ++#define V_PCIE_RXOFLOWLANE2(x) ((x) << S_PCIE_RXOFLOWLANE2) ++#define F_PCIE_RXOFLOWLANE2 V_PCIE_RXOFLOWLANE2(1U) ++ ++#define S_PCIE_RXOFLOWLANE1 1 ++#define V_PCIE_RXOFLOWLANE1(x) ((x) << S_PCIE_RXOFLOWLANE1) ++#define F_PCIE_RXOFLOWLANE1 V_PCIE_RXOFLOWLANE1(1U) ++ ++#define S_PCIE_RXOFLOWLANE0 0 ++#define V_PCIE_RXOFLOWLANE0(x) ((x) << S_PCIE_RXOFLOWLANE0) ++#define F_PCIE_RXOFLOWLANE0 V_PCIE_RXOFLOWLANE0(1U) ++ ++#define A_PCIE_SERDES_LANE_STAT 0xb8 ++ ++#define S_EXTBISTCHKERRCNT 8 ++#define M_EXTBISTCHKERRCNT 0xffffff ++#define V_EXTBISTCHKERRCNT(x) ((x) << S_EXTBISTCHKERRCNT) ++#define G_EXTBISTCHKERRCNT(x) (((x) >> S_EXTBISTCHKERRCNT) & M_EXTBISTCHKERRCNT) ++ ++#define S_EXTBISTCHKFMD 7 ++#define V_EXTBISTCHKFMD(x) ((x) << S_EXTBISTCHKFMD) ++#define F_EXTBISTCHKFMD V_EXTBISTCHKFMD(1U) ++ ++#define S_BEACONDETECTCHG 6 ++#define V_BEACONDETECTCHG(x) ((x) << S_BEACONDETECTCHG) ++#define F_BEACONDETECTCHG V_BEACONDETECTCHG(1U) ++ ++#define S_RXDETECTCHG 5 ++#define V_RXDETECTCHG(x) ((x) << S_RXDETECTCHG) ++#define F_RXDETECTCHG V_RXDETECTCHG(1U) ++ ++#define S_TXIDLEDETECTCHG 4 ++#define V_TXIDLEDETECTCHG(x) ((x) << S_TXIDLEDETECTCHG) ++#define F_TXIDLEDETECTCHG V_TXIDLEDETECTCHG(1U) ++ ++#define S_BEACONDETECT 2 ++#define V_BEACONDETECT(x) ((x) << S_BEACONDETECT) ++#define F_BEACONDETECT V_BEACONDETECT(1U) ++ ++#define S_RXDETECT 1 ++#define V_RXDETECT(x) ((x) << S_RXDETECT) ++#define F_RXDETECT V_RXDETECT(1U) ++ ++#define S_TXIDLEDETECT 0 ++#define V_TXIDLEDETECT(x) ((x) << S_TXIDLEDETECT) ++#define F_TXIDLEDETECT V_TXIDLEDETECT(1U) ++ ++#define A_PCIE_SERDES_STATUS2 0xb8 ++ ++#define S_TXRECDETLANE7 31 ++#define V_TXRECDETLANE7(x) ((x) << S_TXRECDETLANE7) ++#define F_TXRECDETLANE7 V_TXRECDETLANE7(1U) ++ ++#define S_TXRECDETLANE6 30 ++#define V_TXRECDETLANE6(x) ((x) << S_TXRECDETLANE6) ++#define F_TXRECDETLANE6 V_TXRECDETLANE6(1U) ++ ++#define S_TXRECDETLANE5 29 ++#define V_TXRECDETLANE5(x) ((x) << S_TXRECDETLANE5) ++#define F_TXRECDETLANE5 V_TXRECDETLANE5(1U) ++ ++#define S_TXRECDETLANE4 28 ++#define V_TXRECDETLANE4(x) ((x) << S_TXRECDETLANE4) ++#define F_TXRECDETLANE4 V_TXRECDETLANE4(1U) ++ ++#define S_TXRECDETLANE3 27 ++#define V_TXRECDETLANE3(x) ((x) << S_TXRECDETLANE3) ++#define F_TXRECDETLANE3 V_TXRECDETLANE3(1U) ++ ++#define S_TXRECDETLANE2 26 ++#define V_TXRECDETLANE2(x) ((x) << S_TXRECDETLANE2) ++#define F_TXRECDETLANE2 V_TXRECDETLANE2(1U) ++ ++#define S_TXRECDETLANE1 25 ++#define V_TXRECDETLANE1(x) ((x) << S_TXRECDETLANE1) ++#define F_TXRECDETLANE1 V_TXRECDETLANE1(1U) ++ ++#define S_TXRECDETLANE0 24 ++#define V_TXRECDETLANE0(x) ((x) << S_TXRECDETLANE0) ++#define F_TXRECDETLANE0 V_TXRECDETLANE0(1U) ++ ++#define S_RXEIDLANE7 23 ++#define V_RXEIDLANE7(x) ((x) << S_RXEIDLANE7) ++#define F_RXEIDLANE7 V_RXEIDLANE7(1U) ++ ++#define S_RXEIDLANE6 22 ++#define V_RXEIDLANE6(x) ((x) << S_RXEIDLANE6) ++#define F_RXEIDLANE6 V_RXEIDLANE6(1U) ++ ++#define S_RXEIDLANE5 21 ++#define V_RXEIDLANE5(x) ((x) << S_RXEIDLANE5) ++#define F_RXEIDLANE5 V_RXEIDLANE5(1U) ++ ++#define S_RXEIDLANE4 20 ++#define V_RXEIDLANE4(x) ((x) << S_RXEIDLANE4) ++#define F_RXEIDLANE4 V_RXEIDLANE4(1U) ++ ++#define S_RXEIDLANE3 19 ++#define V_RXEIDLANE3(x) ((x) << S_RXEIDLANE3) ++#define F_RXEIDLANE3 V_RXEIDLANE3(1U) ++ ++#define S_RXEIDLANE2 18 ++#define V_RXEIDLANE2(x) ((x) << S_RXEIDLANE2) ++#define F_RXEIDLANE2 V_RXEIDLANE2(1U) ++ ++#define S_RXEIDLANE1 17 ++#define V_RXEIDLANE1(x) ((x) << S_RXEIDLANE1) ++#define F_RXEIDLANE1 V_RXEIDLANE1(1U) ++ ++#define S_RXEIDLANE0 16 ++#define V_RXEIDLANE0(x) ((x) << S_RXEIDLANE0) ++#define F_RXEIDLANE0 V_RXEIDLANE0(1U) ++ ++#define S_RXREMSKIPLANE7 15 ++#define V_RXREMSKIPLANE7(x) ((x) << S_RXREMSKIPLANE7) ++#define F_RXREMSKIPLANE7 V_RXREMSKIPLANE7(1U) ++ ++#define S_RXREMSKIPLANE6 14 ++#define V_RXREMSKIPLANE6(x) ((x) << S_RXREMSKIPLANE6) ++#define F_RXREMSKIPLANE6 V_RXREMSKIPLANE6(1U) ++ ++#define S_RXREMSKIPLANE5 13 ++#define V_RXREMSKIPLANE5(x) ((x) << S_RXREMSKIPLANE5) ++#define F_RXREMSKIPLANE5 V_RXREMSKIPLANE5(1U) ++ ++#define S_RXREMSKIPLANE4 12 ++#define V_RXREMSKIPLANE4(x) ((x) << S_RXREMSKIPLANE4) ++#define F_RXREMSKIPLANE4 V_RXREMSKIPLANE4(1U) ++ ++#define S_PCIE_RXREMSKIPLANE3 11 ++#define V_PCIE_RXREMSKIPLANE3(x) ((x) << S_PCIE_RXREMSKIPLANE3) ++#define F_PCIE_RXREMSKIPLANE3 V_PCIE_RXREMSKIPLANE3(1U) ++ ++#define S_PCIE_RXREMSKIPLANE2 10 ++#define V_PCIE_RXREMSKIPLANE2(x) ((x) << S_PCIE_RXREMSKIPLANE2) ++#define F_PCIE_RXREMSKIPLANE2 V_PCIE_RXREMSKIPLANE2(1U) ++ ++#define S_PCIE_RXREMSKIPLANE1 9 ++#define V_PCIE_RXREMSKIPLANE1(x) ((x) << S_PCIE_RXREMSKIPLANE1) ++#define F_PCIE_RXREMSKIPLANE1 V_PCIE_RXREMSKIPLANE1(1U) ++ ++#define S_PCIE_RXREMSKIPLANE0 8 ++#define V_PCIE_RXREMSKIPLANE0(x) ((x) << S_PCIE_RXREMSKIPLANE0) ++#define F_PCIE_RXREMSKIPLANE0 V_PCIE_RXREMSKIPLANE0(1U) ++ ++#define S_RXADDSKIPLANE7 7 ++#define V_RXADDSKIPLANE7(x) ((x) << S_RXADDSKIPLANE7) ++#define F_RXADDSKIPLANE7 V_RXADDSKIPLANE7(1U) ++ ++#define S_RXADDSKIPLANE6 6 ++#define V_RXADDSKIPLANE6(x) ((x) << S_RXADDSKIPLANE6) ++#define F_RXADDSKIPLANE6 V_RXADDSKIPLANE6(1U) ++ ++#define S_RXADDSKIPLANE5 5 ++#define V_RXADDSKIPLANE5(x) ((x) << S_RXADDSKIPLANE5) ++#define F_RXADDSKIPLANE5 V_RXADDSKIPLANE5(1U) ++ ++#define S_RXADDSKIPLANE4 4 ++#define V_RXADDSKIPLANE4(x) ((x) << S_RXADDSKIPLANE4) ++#define F_RXADDSKIPLANE4 V_RXADDSKIPLANE4(1U) ++ ++#define S_PCIE_RXADDSKIPLANE3 3 ++#define V_PCIE_RXADDSKIPLANE3(x) ((x) << S_PCIE_RXADDSKIPLANE3) ++#define F_PCIE_RXADDSKIPLANE3 V_PCIE_RXADDSKIPLANE3(1U) ++ ++#define S_PCIE_RXADDSKIPLANE2 2 ++#define V_PCIE_RXADDSKIPLANE2(x) ((x) << S_PCIE_RXADDSKIPLANE2) ++#define F_PCIE_RXADDSKIPLANE2 V_PCIE_RXADDSKIPLANE2(1U) ++ ++#define S_PCIE_RXADDSKIPLANE1 1 ++#define V_PCIE_RXADDSKIPLANE1(x) ((x) << S_PCIE_RXADDSKIPLANE1) ++#define F_PCIE_RXADDSKIPLANE1 V_PCIE_RXADDSKIPLANE1(1U) ++ ++#define S_PCIE_RXADDSKIPLANE0 0 ++#define V_PCIE_RXADDSKIPLANE0(x) ((x) << S_PCIE_RXADDSKIPLANE0) ++#define F_PCIE_RXADDSKIPLANE0 V_PCIE_RXADDSKIPLANE0(1U) ++ ++#define A_PCIE_PEX_WMARK 0xbc ++ ++#define S_P_WMARK 18 ++#define M_P_WMARK 0x7ff ++#define V_P_WMARK(x) ((x) << S_P_WMARK) ++#define G_P_WMARK(x) (((x) >> S_P_WMARK) & M_P_WMARK) ++ ++#define S_NP_WMARK 11 ++#define M_NP_WMARK 0x7f ++#define V_NP_WMARK(x) ((x) << S_NP_WMARK) ++#define G_NP_WMARK(x) (((x) >> S_NP_WMARK) & M_NP_WMARK) ++ ++#define S_CPL_WMARK 0 ++#define M_CPL_WMARK 0x7ff ++#define V_CPL_WMARK(x) ((x) << S_CPL_WMARK) ++#define G_CPL_WMARK(x) (((x) >> S_CPL_WMARK) & M_CPL_WMARK) ++ ++#define A_PCIE_SERDES_BIST 0xbc ++ ++#define S_PCIE_BISTDONE 24 ++#define M_PCIE_BISTDONE 0xff ++#define V_PCIE_BISTDONE(x) ((x) << S_PCIE_BISTDONE) ++#define G_PCIE_BISTDONE(x) (((x) >> S_PCIE_BISTDONE) & M_PCIE_BISTDONE) ++ ++#define S_PCIE_BISTCYCLETHRESH 3 ++#define M_PCIE_BISTCYCLETHRESH 0xffff ++#define V_PCIE_BISTCYCLETHRESH(x) ((x) << S_PCIE_BISTCYCLETHRESH) ++#define G_PCIE_BISTCYCLETHRESH(x) (((x) >> S_PCIE_BISTCYCLETHRESH) & M_PCIE_BISTCYCLETHRESH) ++ ++#define S_BISTMODE 0 ++#define M_BISTMODE 0x7 ++#define V_BISTMODE(x) ((x) << S_BISTMODE) ++#define G_BISTMODE(x) (((x) >> S_BISTMODE) & M_BISTMODE) ++ ++/* registers for module T3DBG */ ++#define T3DBG_BASE_ADDR 0xc0 ++ ++#define A_T3DBG_DBG0_CFG 0xc0 ++ ++#define S_REGSELECT 9 ++#define M_REGSELECT 0xff ++#define V_REGSELECT(x) ((x) << S_REGSELECT) ++#define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT) ++ ++#define S_MODULESELECT 4 ++#define M_MODULESELECT 0x1f ++#define V_MODULESELECT(x) ((x) << S_MODULESELECT) ++#define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT) ++ ++#define S_CLKSELECT 0 ++#define M_CLKSELECT 0xf ++#define V_CLKSELECT(x) ((x) << S_CLKSELECT) ++#define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT) ++ ++#define A_T3DBG_DBG0_EN 0xc4 ++ ++#define S_SDRBYTE0 8 ++#define V_SDRBYTE0(x) ((x) << S_SDRBYTE0) ++#define F_SDRBYTE0 V_SDRBYTE0(1U) ++ ++#define S_DDREN 4 ++#define V_DDREN(x) ((x) << S_DDREN) ++#define F_DDREN V_DDREN(1U) ++ ++#define S_PORTEN 0 ++#define V_PORTEN(x) ((x) << S_PORTEN) ++#define F_PORTEN V_PORTEN(1U) ++ ++#define A_T3DBG_DBG1_CFG 0xc8 ++#define A_T3DBG_DBG1_EN 0xcc + #define A_T3DBG_GPIO_EN 0xd0 + + #define S_GPIO11_OEN 27 +@@ -503,6 +2074,14 @@ + #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN) + #define F_GPIO10_OEN V_GPIO10_OEN(1U) + ++#define S_GPIO9_OEN 25 ++#define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN) ++#define F_GPIO9_OEN V_GPIO9_OEN(1U) ++ ++#define S_GPIO8_OEN 24 ++#define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN) ++#define F_GPIO8_OEN V_GPIO8_OEN(1U) ++ + #define S_GPIO7_OEN 23 + #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN) + #define F_GPIO7_OEN V_GPIO7_OEN(1U) +@@ -519,6 +2098,10 @@ + #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN) + #define F_GPIO4_OEN V_GPIO4_OEN(1U) + ++#define S_GPIO3_OEN 19 ++#define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN) ++#define F_GPIO3_OEN V_GPIO3_OEN(1U) ++ + #define S_GPIO2_OEN 18 + #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN) + #define F_GPIO2_OEN V_GPIO2_OEN(1U) +@@ -531,10 +2114,22 @@ + #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN) + #define F_GPIO0_OEN V_GPIO0_OEN(1U) + ++#define S_GPIO11_OUT_VAL 11 ++#define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL) ++#define F_GPIO11_OUT_VAL V_GPIO11_OUT_VAL(1U) ++ + #define S_GPIO10_OUT_VAL 10 + #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL) + #define F_GPIO10_OUT_VAL V_GPIO10_OUT_VAL(1U) + ++#define S_GPIO9_OUT_VAL 9 ++#define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL) ++#define F_GPIO9_OUT_VAL V_GPIO9_OUT_VAL(1U) ++ ++#define S_GPIO8_OUT_VAL 8 ++#define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL) ++#define F_GPIO8_OUT_VAL V_GPIO8_OUT_VAL(1U) ++ + #define S_GPIO7_OUT_VAL 7 + #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL) + #define F_GPIO7_OUT_VAL V_GPIO7_OUT_VAL(1U) +@@ -551,6 +2146,10 @@ + #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL) + #define F_GPIO4_OUT_VAL V_GPIO4_OUT_VAL(1U) + ++#define S_GPIO3_OUT_VAL 3 ++#define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL) ++#define F_GPIO3_OUT_VAL V_GPIO3_OUT_VAL(1U) ++ + #define S_GPIO2_OUT_VAL 2 + #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL) + #define F_GPIO2_OUT_VAL V_GPIO2_OUT_VAL(1U) +@@ -563,7 +2162,125 @@ + #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL) + #define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U) + ++#define A_T3DBG_GPIO_IN 0xd4 ++ ++#define S_GPIO11_CHG_DET 27 ++#define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET) ++#define F_GPIO11_CHG_DET V_GPIO11_CHG_DET(1U) ++ ++#define S_GPIO10_CHG_DET 26 ++#define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET) ++#define F_GPIO10_CHG_DET V_GPIO10_CHG_DET(1U) ++ ++#define S_GPIO9_CHG_DET 25 ++#define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET) ++#define F_GPIO9_CHG_DET V_GPIO9_CHG_DET(1U) ++ ++#define S_GPIO8_CHG_DET 24 ++#define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET) ++#define F_GPIO8_CHG_DET V_GPIO8_CHG_DET(1U) ++ ++#define S_GPIO7_CHG_DET 23 ++#define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET) ++#define F_GPIO7_CHG_DET V_GPIO7_CHG_DET(1U) ++ ++#define S_GPIO6_CHG_DET 22 ++#define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET) ++#define F_GPIO6_CHG_DET V_GPIO6_CHG_DET(1U) ++ ++#define S_GPIO5_CHG_DET 21 ++#define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET) ++#define F_GPIO5_CHG_DET V_GPIO5_CHG_DET(1U) ++ ++#define S_GPIO4_CHG_DET 20 ++#define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET) ++#define F_GPIO4_CHG_DET V_GPIO4_CHG_DET(1U) ++ ++#define S_GPIO3_CHG_DET 19 ++#define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET) ++#define F_GPIO3_CHG_DET V_GPIO3_CHG_DET(1U) ++ ++#define S_GPIO2_CHG_DET 18 ++#define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET) ++#define F_GPIO2_CHG_DET V_GPIO2_CHG_DET(1U) ++ ++#define S_GPIO1_CHG_DET 17 ++#define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET) ++#define F_GPIO1_CHG_DET V_GPIO1_CHG_DET(1U) ++ ++#define S_GPIO0_CHG_DET 16 ++#define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET) ++#define F_GPIO0_CHG_DET V_GPIO0_CHG_DET(1U) ++ ++#define S_GPIO11_IN 11 ++#define V_GPIO11_IN(x) ((x) << S_GPIO11_IN) ++#define F_GPIO11_IN V_GPIO11_IN(1U) ++ ++#define S_GPIO10_IN 10 ++#define V_GPIO10_IN(x) ((x) << S_GPIO10_IN) ++#define F_GPIO10_IN V_GPIO10_IN(1U) ++ ++#define S_GPIO9_IN 9 ++#define V_GPIO9_IN(x) ((x) << S_GPIO9_IN) ++#define F_GPIO9_IN V_GPIO9_IN(1U) ++ ++#define S_GPIO8_IN 8 ++#define V_GPIO8_IN(x) ((x) << S_GPIO8_IN) ++#define F_GPIO8_IN V_GPIO8_IN(1U) ++ ++#define S_GPIO7_IN 7 ++#define V_GPIO7_IN(x) ((x) << S_GPIO7_IN) ++#define F_GPIO7_IN V_GPIO7_IN(1U) ++ ++#define S_GPIO6_IN 6 ++#define V_GPIO6_IN(x) ((x) << S_GPIO6_IN) ++#define F_GPIO6_IN V_GPIO6_IN(1U) ++ ++#define S_GPIO5_IN 5 ++#define V_GPIO5_IN(x) ((x) << S_GPIO5_IN) ++#define F_GPIO5_IN V_GPIO5_IN(1U) ++ ++#define S_GPIO4_IN 4 ++#define V_GPIO4_IN(x) ((x) << S_GPIO4_IN) ++#define F_GPIO4_IN V_GPIO4_IN(1U) ++ ++#define S_GPIO3_IN 3 ++#define V_GPIO3_IN(x) ((x) << S_GPIO3_IN) ++#define F_GPIO3_IN V_GPIO3_IN(1U) ++ ++#define S_GPIO2_IN 2 ++#define V_GPIO2_IN(x) ((x) << S_GPIO2_IN) ++#define F_GPIO2_IN V_GPIO2_IN(1U) ++ ++#define S_GPIO1_IN 1 ++#define V_GPIO1_IN(x) ((x) << S_GPIO1_IN) ++#define F_GPIO1_IN V_GPIO1_IN(1U) ++ ++#define S_GPIO0_IN 0 ++#define V_GPIO0_IN(x) ((x) << S_GPIO0_IN) ++#define F_GPIO0_IN V_GPIO0_IN(1U) ++ + #define A_T3DBG_INT_ENABLE 0xd8 ++ ++#define S_C_LOCK 21 ++#define V_C_LOCK(x) ((x) << S_C_LOCK) ++#define F_C_LOCK V_C_LOCK(1U) ++ ++#define S_M_LOCK 20 ++#define V_M_LOCK(x) ((x) << S_M_LOCK) ++#define F_M_LOCK V_M_LOCK(1U) ++ ++#define S_U_LOCK 19 ++#define V_U_LOCK(x) ((x) << S_U_LOCK) ++#define F_U_LOCK V_U_LOCK(1U) ++ ++#define S_R_LOCK 18 ++#define V_R_LOCK(x) ((x) << S_R_LOCK) ++#define F_R_LOCK V_R_LOCK(1U) ++ ++#define S_PX_LOCK 17 ++#define V_PX_LOCK(x) ((x) << S_PX_LOCK) ++#define F_PX_LOCK V_PX_LOCK(1U) + + #define S_GPIO11 11 + #define V_GPIO11(x) ((x) << S_GPIO11) +@@ -577,6 +2294,10 @@ + #define V_GPIO9(x) ((x) << S_GPIO9) + #define F_GPIO9 V_GPIO9(1U) + ++#define S_GPIO8 8 ++#define V_GPIO8(x) ((x) << S_GPIO8) ++#define F_GPIO8 V_GPIO8(1U) ++ + #define S_GPIO7 7 + #define V_GPIO7(x) ((x) << S_GPIO7) + #define F_GPIO7 V_GPIO7(1U) +@@ -609,17 +2330,336 @@ + #define V_GPIO0(x) ((x) << S_GPIO0) + #define F_GPIO0 V_GPIO0(1U) + ++#define S_PE_LOCK 16 ++#define V_PE_LOCK(x) ((x) << S_PE_LOCK) ++#define F_PE_LOCK V_PE_LOCK(1U) ++ + #define A_T3DBG_INT_CAUSE 0xdc ++#define A_T3DBG_DBG0_RST_VALUE 0xe0 ++ ++#define S_DEBUGDATA 0 ++#define M_DEBUGDATA 0xff ++#define V_DEBUGDATA(x) ((x) << S_DEBUGDATA) ++#define G_DEBUGDATA(x) (((x) >> S_DEBUGDATA) & M_DEBUGDATA) ++ ++#define A_T3DBG_PLL_OCLK_PAD_EN 0xe4 ++ ++#define S_PCIE_OCLK_EN 20 ++#define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN) ++#define F_PCIE_OCLK_EN V_PCIE_OCLK_EN(1U) ++ ++#define S_PCLKTREE_DBG_EN 17 ++#define V_PCLKTREE_DBG_EN(x) ((x) << S_PCLKTREE_DBG_EN) ++#define F_PCLKTREE_DBG_EN V_PCLKTREE_DBG_EN(1U) ++ ++#define S_PCIX_OCLK_EN 16 ++#define V_PCIX_OCLK_EN(x) ((x) << S_PCIX_OCLK_EN) ++#define F_PCIX_OCLK_EN V_PCIX_OCLK_EN(1U) ++ ++#define S_U_OCLK_EN 12 ++#define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN) ++#define F_U_OCLK_EN V_U_OCLK_EN(1U) ++ ++#define S_R_OCLK_EN 8 ++#define V_R_OCLK_EN(x) ((x) << S_R_OCLK_EN) ++#define F_R_OCLK_EN V_R_OCLK_EN(1U) ++ ++#define S_M_OCLK_EN 4 ++#define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN) ++#define F_M_OCLK_EN V_M_OCLK_EN(1U) ++ ++#define S_C_OCLK_EN 0 ++#define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN) ++#define F_C_OCLK_EN V_C_OCLK_EN(1U) ++ ++#define A_T3DBG_PLL_LOCK 0xe8 ++ ++#define S_PCIX_LOCK 16 ++#define V_PCIX_LOCK(x) ((x) << S_PCIX_LOCK) ++#define F_PCIX_LOCK V_PCIX_LOCK(1U) ++ ++#define S_PLL_U_LOCK 12 ++#define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK) ++#define F_PLL_U_LOCK V_PLL_U_LOCK(1U) ++ ++#define S_PLL_R_LOCK 8 ++#define V_PLL_R_LOCK(x) ((x) << S_PLL_R_LOCK) ++#define F_PLL_R_LOCK V_PLL_R_LOCK(1U) ++ ++#define S_PLL_M_LOCK 4 ++#define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK) ++#define F_PLL_M_LOCK V_PLL_M_LOCK(1U) ++ ++#define S_PLL_C_LOCK 0 ++#define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK) ++#define F_PLL_C_LOCK V_PLL_C_LOCK(1U) ++ ++#define S_PCIE_LOCK 20 ++#define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK) ++#define F_PCIE_LOCK V_PCIE_LOCK(1U) ++ ++#define A_T3DBG_SERDES_RBC_CFG 0xec ++ ++#define S_X_RBC_LANE_SEL 16 ++#define M_X_RBC_LANE_SEL 0x3 ++#define V_X_RBC_LANE_SEL(x) ((x) << S_X_RBC_LANE_SEL) ++#define G_X_RBC_LANE_SEL(x) (((x) >> S_X_RBC_LANE_SEL) & M_X_RBC_LANE_SEL) ++ ++#define S_X_RBC_DBG_EN 12 ++#define V_X_RBC_DBG_EN(x) ((x) << S_X_RBC_DBG_EN) ++#define F_X_RBC_DBG_EN V_X_RBC_DBG_EN(1U) ++ ++#define S_X_SERDES_SEL 8 ++#define V_X_SERDES_SEL(x) ((x) << S_X_SERDES_SEL) ++#define F_X_SERDES_SEL V_X_SERDES_SEL(1U) ++ ++#define S_PE_RBC_LANE_SEL 4 ++#define M_PE_RBC_LANE_SEL 0x7 ++#define V_PE_RBC_LANE_SEL(x) ((x) << S_PE_RBC_LANE_SEL) ++#define G_PE_RBC_LANE_SEL(x) (((x) >> S_PE_RBC_LANE_SEL) & M_PE_RBC_LANE_SEL) ++ ++#define S_PE_RBC_DBG_EN 0 ++#define V_PE_RBC_DBG_EN(x) ((x) << S_PE_RBC_DBG_EN) ++#define F_PE_RBC_DBG_EN V_PE_RBC_DBG_EN(1U) + + #define A_T3DBG_GPIO_ACT_LOW 0xf0 + ++#define S_C_LOCK_ACT_LOW 21 ++#define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW) ++#define F_C_LOCK_ACT_LOW V_C_LOCK_ACT_LOW(1U) ++ ++#define S_M_LOCK_ACT_LOW 20 ++#define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW) ++#define F_M_LOCK_ACT_LOW V_M_LOCK_ACT_LOW(1U) ++ ++#define S_U_LOCK_ACT_LOW 19 ++#define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW) ++#define F_U_LOCK_ACT_LOW V_U_LOCK_ACT_LOW(1U) ++ ++#define S_R_LOCK_ACT_LOW 18 ++#define V_R_LOCK_ACT_LOW(x) ((x) << S_R_LOCK_ACT_LOW) ++#define F_R_LOCK_ACT_LOW V_R_LOCK_ACT_LOW(1U) ++ ++#define S_PX_LOCK_ACT_LOW 17 ++#define V_PX_LOCK_ACT_LOW(x) ((x) << S_PX_LOCK_ACT_LOW) ++#define F_PX_LOCK_ACT_LOW V_PX_LOCK_ACT_LOW(1U) ++ ++#define S_GPIO11_ACT_LOW 11 ++#define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW) ++#define F_GPIO11_ACT_LOW V_GPIO11_ACT_LOW(1U) ++ ++#define S_GPIO10_ACT_LOW 10 ++#define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW) ++#define F_GPIO10_ACT_LOW V_GPIO10_ACT_LOW(1U) ++ ++#define S_GPIO9_ACT_LOW 9 ++#define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW) ++#define F_GPIO9_ACT_LOW V_GPIO9_ACT_LOW(1U) ++ ++#define S_GPIO8_ACT_LOW 8 ++#define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW) ++#define F_GPIO8_ACT_LOW V_GPIO8_ACT_LOW(1U) ++ ++#define S_GPIO7_ACT_LOW 7 ++#define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW) ++#define F_GPIO7_ACT_LOW V_GPIO7_ACT_LOW(1U) ++ ++#define S_GPIO6_ACT_LOW 6 ++#define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW) ++#define F_GPIO6_ACT_LOW V_GPIO6_ACT_LOW(1U) ++ ++#define S_GPIO5_ACT_LOW 5 ++#define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW) ++#define F_GPIO5_ACT_LOW V_GPIO5_ACT_LOW(1U) ++ ++#define S_GPIO4_ACT_LOW 4 ++#define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW) ++#define F_GPIO4_ACT_LOW V_GPIO4_ACT_LOW(1U) ++ ++#define S_GPIO3_ACT_LOW 3 ++#define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW) ++#define F_GPIO3_ACT_LOW V_GPIO3_ACT_LOW(1U) ++ ++#define S_GPIO2_ACT_LOW 2 ++#define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW) ++#define F_GPIO2_ACT_LOW V_GPIO2_ACT_LOW(1U) ++ ++#define S_GPIO1_ACT_LOW 1 ++#define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW) ++#define F_GPIO1_ACT_LOW V_GPIO1_ACT_LOW(1U) ++ ++#define S_GPIO0_ACT_LOW 0 ++#define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW) ++#define F_GPIO0_ACT_LOW V_GPIO0_ACT_LOW(1U) ++ ++#define S_PE_LOCK_ACT_LOW 16 ++#define V_PE_LOCK_ACT_LOW(x) ((x) << S_PE_LOCK_ACT_LOW) ++#define F_PE_LOCK_ACT_LOW V_PE_LOCK_ACT_LOW(1U) ++ ++#define A_T3DBG_PMON_CFG 0xf4 ++ ++#define S_PMON_DONE 29 ++#define V_PMON_DONE(x) ((x) << S_PMON_DONE) ++#define F_PMON_DONE V_PMON_DONE(1U) ++ ++#define S_PMON_FAIL 28 ++#define V_PMON_FAIL(x) ((x) << S_PMON_FAIL) ++#define F_PMON_FAIL V_PMON_FAIL(1U) ++ ++#define S_PMON_FDEL_AUTO 22 ++#define M_PMON_FDEL_AUTO 0x3f ++#define V_PMON_FDEL_AUTO(x) ((x) << S_PMON_FDEL_AUTO) ++#define G_PMON_FDEL_AUTO(x) (((x) >> S_PMON_FDEL_AUTO) & M_PMON_FDEL_AUTO) ++ ++#define S_PMON_CDEL_AUTO 16 ++#define M_PMON_CDEL_AUTO 0x3f ++#define V_PMON_CDEL_AUTO(x) ((x) << S_PMON_CDEL_AUTO) ++#define G_PMON_CDEL_AUTO(x) (((x) >> S_PMON_CDEL_AUTO) & M_PMON_CDEL_AUTO) ++ ++#define S_PMON_FDEL_MANUAL 10 ++#define M_PMON_FDEL_MANUAL 0x3f ++#define V_PMON_FDEL_MANUAL(x) ((x) << S_PMON_FDEL_MANUAL) ++#define G_PMON_FDEL_MANUAL(x) (((x) >> S_PMON_FDEL_MANUAL) & M_PMON_FDEL_MANUAL) ++ ++#define S_PMON_CDEL_MANUAL 4 ++#define M_PMON_CDEL_MANUAL 0x3f ++#define V_PMON_CDEL_MANUAL(x) ((x) << S_PMON_CDEL_MANUAL) ++#define G_PMON_CDEL_MANUAL(x) (((x) >> S_PMON_CDEL_MANUAL) & M_PMON_CDEL_MANUAL) ++ ++#define S_PMON_MANUAL 1 ++#define V_PMON_MANUAL(x) ((x) << S_PMON_MANUAL) ++#define F_PMON_MANUAL V_PMON_MANUAL(1U) ++ ++#define S_PMON_AUTO 0 ++#define V_PMON_AUTO(x) ((x) << S_PMON_AUTO) ++#define F_PMON_AUTO V_PMON_AUTO(1U) ++ ++#define A_T3DBG_SERDES_REFCLK_CFG 0xf8 ++ ++#define S_PE_REFCLK_DBG_EN 12 ++#define V_PE_REFCLK_DBG_EN(x) ((x) << S_PE_REFCLK_DBG_EN) ++#define F_PE_REFCLK_DBG_EN V_PE_REFCLK_DBG_EN(1U) ++ ++#define S_X_REFCLK_DBG_EN 8 ++#define V_X_REFCLK_DBG_EN(x) ((x) << S_X_REFCLK_DBG_EN) ++#define F_X_REFCLK_DBG_EN V_X_REFCLK_DBG_EN(1U) ++ ++#define S_PE_REFCLK_TERMADJ 5 ++#define M_PE_REFCLK_TERMADJ 0x3 ++#define V_PE_REFCLK_TERMADJ(x) ((x) << S_PE_REFCLK_TERMADJ) ++#define G_PE_REFCLK_TERMADJ(x) (((x) >> S_PE_REFCLK_TERMADJ) & M_PE_REFCLK_TERMADJ) ++ ++#define S_PE_REFCLK_PD 4 ++#define V_PE_REFCLK_PD(x) ((x) << S_PE_REFCLK_PD) ++#define F_PE_REFCLK_PD V_PE_REFCLK_PD(1U) ++ ++#define S_X_REFCLK_TERMADJ 1 ++#define M_X_REFCLK_TERMADJ 0x3 ++#define V_X_REFCLK_TERMADJ(x) ((x) << S_X_REFCLK_TERMADJ) ++#define G_X_REFCLK_TERMADJ(x) (((x) >> S_X_REFCLK_TERMADJ) & M_X_REFCLK_TERMADJ) ++ ++#define S_X_REFCLK_PD 0 ++#define V_X_REFCLK_PD(x) ((x) << S_X_REFCLK_PD) ++#define F_X_REFCLK_PD V_X_REFCLK_PD(1U) ++ ++#define A_T3DBG_PCIE_PMA_BSPIN_CFG 0xfc ++ ++#define S_BSMODEQUAD1 31 ++#define V_BSMODEQUAD1(x) ((x) << S_BSMODEQUAD1) ++#define F_BSMODEQUAD1 V_BSMODEQUAD1(1U) ++ ++#define S_BSINSELLANE7 29 ++#define M_BSINSELLANE7 0x3 ++#define V_BSINSELLANE7(x) ((x) << S_BSINSELLANE7) ++#define G_BSINSELLANE7(x) (((x) >> S_BSINSELLANE7) & M_BSINSELLANE7) ++ ++#define S_BSENLANE7 28 ++#define V_BSENLANE7(x) ((x) << S_BSENLANE7) ++#define F_BSENLANE7 V_BSENLANE7(1U) ++ ++#define S_BSINSELLANE6 25 ++#define M_BSINSELLANE6 0x3 ++#define V_BSINSELLANE6(x) ((x) << S_BSINSELLANE6) ++#define G_BSINSELLANE6(x) (((x) >> S_BSINSELLANE6) & M_BSINSELLANE6) ++ ++#define S_BSENLANE6 24 ++#define V_BSENLANE6(x) ((x) << S_BSENLANE6) ++#define F_BSENLANE6 V_BSENLANE6(1U) ++ ++#define S_BSINSELLANE5 21 ++#define M_BSINSELLANE5 0x3 ++#define V_BSINSELLANE5(x) ((x) << S_BSINSELLANE5) ++#define G_BSINSELLANE5(x) (((x) >> S_BSINSELLANE5) & M_BSINSELLANE5) ++ ++#define S_BSENLANE5 20 ++#define V_BSENLANE5(x) ((x) << S_BSENLANE5) ++#define F_BSENLANE5 V_BSENLANE5(1U) ++ ++#define S_BSINSELLANE4 17 ++#define M_BSINSELLANE4 0x3 ++#define V_BSINSELLANE4(x) ((x) << S_BSINSELLANE4) ++#define G_BSINSELLANE4(x) (((x) >> S_BSINSELLANE4) & M_BSINSELLANE4) ++ ++#define S_BSENLANE4 16 ++#define V_BSENLANE4(x) ((x) << S_BSENLANE4) ++#define F_BSENLANE4 V_BSENLANE4(1U) ++ ++#define S_BSMODEQUAD0 15 ++#define V_BSMODEQUAD0(x) ((x) << S_BSMODEQUAD0) ++#define F_BSMODEQUAD0 V_BSMODEQUAD0(1U) ++ ++#define S_BSINSELLANE3 13 ++#define M_BSINSELLANE3 0x3 ++#define V_BSINSELLANE3(x) ((x) << S_BSINSELLANE3) ++#define G_BSINSELLANE3(x) (((x) >> S_BSINSELLANE3) & M_BSINSELLANE3) ++ ++#define S_BSENLANE3 12 ++#define V_BSENLANE3(x) ((x) << S_BSENLANE3) ++#define F_BSENLANE3 V_BSENLANE3(1U) ++ ++#define S_BSINSELLANE2 9 ++#define M_BSINSELLANE2 0x3 ++#define V_BSINSELLANE2(x) ((x) << S_BSINSELLANE2) ++#define G_BSINSELLANE2(x) (((x) >> S_BSINSELLANE2) & M_BSINSELLANE2) ++ ++#define S_BSENLANE2 8 ++#define V_BSENLANE2(x) ((x) << S_BSENLANE2) ++#define F_BSENLANE2 V_BSENLANE2(1U) ++ ++#define S_BSINSELLANE1 5 ++#define M_BSINSELLANE1 0x3 ++#define V_BSINSELLANE1(x) ((x) << S_BSINSELLANE1) ++#define G_BSINSELLANE1(x) (((x) >> S_BSINSELLANE1) & M_BSINSELLANE1) ++ ++#define S_BSENLANE1 4 ++#define V_BSENLANE1(x) ((x) << S_BSENLANE1) ++#define F_BSENLANE1 V_BSENLANE1(1U) ++ ++#define S_BSINSELLANE0 1 ++#define M_BSINSELLANE0 0x3 ++#define V_BSINSELLANE0(x) ((x) << S_BSINSELLANE0) ++#define G_BSINSELLANE0(x) (((x) >> S_BSINSELLANE0) & M_BSINSELLANE0) ++ ++#define S_BSENLANE0 0 ++#define V_BSENLANE0(x) ((x) << S_BSENLANE0) ++#define F_BSENLANE0 V_BSENLANE0(1U) ++ ++/* registers for module MC7_PMRX */ + #define MC7_PMRX_BASE_ADDR 0x100 + + #define A_MC7_CFG 0x100 ++ ++#define S_IMPSETUPDATE 14 ++#define V_IMPSETUPDATE(x) ((x) << S_IMPSETUPDATE) ++#define F_IMPSETUPDATE V_IMPSETUPDATE(1U) + + #define S_IFEN 13 + #define V_IFEN(x) ((x) << S_IFEN) + #define F_IFEN V_IFEN(1U) ++ ++#define S_TERM300 12 ++#define V_TERM300(x) ((x) << S_TERM300) ++#define F_TERM300 V_TERM300(1U) + + #define S_TERM150 11 + #define V_TERM150(x) ((x) << S_TERM150) +@@ -634,6 +2674,10 @@ + #define V_WIDTH(x) ((x) << S_WIDTH) + #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH) + ++#define S_ODTEN 7 ++#define V_ODTEN(x) ((x) << S_ODTEN) ++#define F_ODTEN V_ODTEN(1U) ++ + #define S_BKS 6 + #define V_BKS(x) ((x) << S_BKS) + #define F_BKS V_BKS(1U) +@@ -657,93 +2701,233 @@ + + #define A_MC7_MODE 0x104 + ++#define S_MODE 0 ++#define M_MODE 0xffff ++#define V_MODE(x) ((x) << S_MODE) ++#define G_MODE(x) (((x) >> S_MODE) & M_MODE) ++ ++#define A_MC7_EXT_MODE1 0x108 ++ ++#define S_OCDADJUSTMODE 20 ++#define V_OCDADJUSTMODE(x) ((x) << S_OCDADJUSTMODE) ++#define F_OCDADJUSTMODE V_OCDADJUSTMODE(1U) ++ ++#define S_OCDCODE 16 ++#define M_OCDCODE 0xf ++#define V_OCDCODE(x) ((x) << S_OCDCODE) ++#define G_OCDCODE(x) (((x) >> S_OCDCODE) & M_OCDCODE) ++ ++#define S_EXTMODE1 0 ++#define M_EXTMODE1 0xffff ++#define V_EXTMODE1(x) ((x) << S_EXTMODE1) ++#define G_EXTMODE1(x) (((x) >> S_EXTMODE1) & M_EXTMODE1) ++ ++#define A_MC7_EXT_MODE2 0x10c ++ ++#define S_EXTMODE2 0 ++#define M_EXTMODE2 0xffff ++#define V_EXTMODE2(x) ((x) << S_EXTMODE2) ++#define G_EXTMODE2(x) (((x) >> S_EXTMODE2) & M_EXTMODE2) ++ ++#define A_MC7_EXT_MODE3 0x110 ++ ++#define S_EXTMODE3 0 ++#define M_EXTMODE3 0xffff ++#define V_EXTMODE3(x) ((x) << S_EXTMODE3) ++#define G_EXTMODE3(x) (((x) >> S_EXTMODE3) & M_EXTMODE3) ++ ++#define A_MC7_PRE 0x114 ++#define A_MC7_REF 0x118 ++ ++#define S_PREREFDIV 1 ++#define M_PREREFDIV 0x3fff ++#define V_PREREFDIV(x) ((x) << S_PREREFDIV) ++#define G_PREREFDIV(x) (((x) >> S_PREREFDIV) & M_PREREFDIV) ++ ++#define S_PERREFEN 0 ++#define V_PERREFEN(x) ((x) << S_PERREFEN) ++#define F_PERREFEN V_PERREFEN(1U) ++ ++#define A_MC7_DLL 0x11c ++ ++#define S_DLLLOCK 31 ++#define V_DLLLOCK(x) ((x) << S_DLLLOCK) ++#define F_DLLLOCK V_DLLLOCK(1U) ++ ++#define S_DLLDELTA 24 ++#define M_DLLDELTA 0x7f ++#define V_DLLDELTA(x) ((x) << S_DLLDELTA) ++#define G_DLLDELTA(x) (((x) >> S_DLLDELTA) & M_DLLDELTA) ++ ++#define S_MANDELTA 3 ++#define M_MANDELTA 0x7f ++#define V_MANDELTA(x) ((x) << S_MANDELTA) ++#define G_MANDELTA(x) (((x) >> S_MANDELTA) & M_MANDELTA) ++ ++#define S_DLLDELTASEL 2 ++#define V_DLLDELTASEL(x) ((x) << S_DLLDELTASEL) ++#define F_DLLDELTASEL V_DLLDELTASEL(1U) ++ ++#define S_DLLENB 1 ++#define V_DLLENB(x) ((x) << S_DLLENB) ++#define F_DLLENB V_DLLENB(1U) ++ ++#define S_DLLRST 0 ++#define V_DLLRST(x) ((x) << S_DLLRST) ++#define F_DLLRST V_DLLRST(1U) ++ ++#define A_MC7_PARM 0x120 ++ ++#define S_ACTTOPREDLY 26 ++#define M_ACTTOPREDLY 0xf ++#define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY) ++#define G_ACTTOPREDLY(x) (((x) >> S_ACTTOPREDLY) & M_ACTTOPREDLY) ++ ++#define S_ACTTORDWRDLY 23 ++#define M_ACTTORDWRDLY 0x7 ++#define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY) ++#define G_ACTTORDWRDLY(x) (((x) >> S_ACTTORDWRDLY) & M_ACTTORDWRDLY) ++ ++#define S_PRECYC 20 ++#define M_PRECYC 0x7 ++#define V_PRECYC(x) ((x) << S_PRECYC) ++#define G_PRECYC(x) (((x) >> S_PRECYC) & M_PRECYC) ++ ++#define S_REFCYC 13 ++#define M_REFCYC 0x7f ++#define V_REFCYC(x) ((x) << S_REFCYC) ++#define G_REFCYC(x) (((x) >> S_REFCYC) & M_REFCYC) ++ ++#define S_BKCYC 8 ++#define M_BKCYC 0x1f ++#define V_BKCYC(x) ((x) << S_BKCYC) ++#define G_BKCYC(x) (((x) >> S_BKCYC) & M_BKCYC) ++ ++#define S_WRTORDDLY 4 ++#define M_WRTORDDLY 0xf ++#define V_WRTORDDLY(x) ((x) << S_WRTORDDLY) ++#define G_WRTORDDLY(x) (((x) >> S_WRTORDDLY) & M_WRTORDDLY) ++ ++#define S_RDTOWRDLY 0 ++#define M_RDTOWRDLY 0xf ++#define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY) ++#define G_RDTOWRDLY(x) (((x) >> S_RDTOWRDLY) & M_RDTOWRDLY) ++ ++#define A_MC7_HWM_WRR 0x124 ++ ++#define S_MEM_HWM 26 ++#define M_MEM_HWM 0x3f ++#define V_MEM_HWM(x) ((x) << S_MEM_HWM) ++#define G_MEM_HWM(x) (((x) >> S_MEM_HWM) & M_MEM_HWM) ++ ++#define S_ULP_HWM 22 ++#define M_ULP_HWM 0xf ++#define V_ULP_HWM(x) ((x) << S_ULP_HWM) ++#define G_ULP_HWM(x) (((x) >> S_ULP_HWM) & M_ULP_HWM) ++ ++#define S_TOT_RLD_WT 14 ++#define M_TOT_RLD_WT 0xff ++#define V_TOT_RLD_WT(x) ((x) << S_TOT_RLD_WT) ++#define G_TOT_RLD_WT(x) (((x) >> S_TOT_RLD_WT) & M_TOT_RLD_WT) ++ ++#define S_MEM_RLD_WT 7 ++#define M_MEM_RLD_WT 0x7f ++#define V_MEM_RLD_WT(x) ((x) << S_MEM_RLD_WT) ++#define G_MEM_RLD_WT(x) (((x) >> S_MEM_RLD_WT) & M_MEM_RLD_WT) ++ ++#define S_ULP_RLD_WT 0 ++#define M_ULP_RLD_WT 0x7f ++#define V_ULP_RLD_WT(x) ((x) << S_ULP_RLD_WT) ++#define G_ULP_RLD_WT(x) (((x) >> S_ULP_RLD_WT) & M_ULP_RLD_WT) ++ ++#define A_MC7_CAL 0x128 ++ + #define S_BUSY 31 + #define V_BUSY(x) ((x) << S_BUSY) + #define F_BUSY V_BUSY(1U) + +-#define S_BUSY 31 +-#define V_BUSY(x) ((x) << S_BUSY) +-#define F_BUSY V_BUSY(1U) +- +-#define A_MC7_EXT_MODE1 0x108 +- +-#define A_MC7_EXT_MODE2 0x10c +- +-#define A_MC7_EXT_MODE3 0x110 +- +-#define A_MC7_PRE 0x114 +- +-#define A_MC7_REF 0x118 +- +-#define S_PREREFDIV 1 +-#define M_PREREFDIV 0x3fff +-#define V_PREREFDIV(x) ((x) << S_PREREFDIV) +- +-#define S_PERREFEN 0 +-#define V_PERREFEN(x) ((x) << S_PERREFEN) +-#define F_PERREFEN V_PERREFEN(1U) +- +-#define A_MC7_DLL 0x11c +- +-#define S_DLLENB 1 +-#define V_DLLENB(x) ((x) << S_DLLENB) +-#define F_DLLENB V_DLLENB(1U) +- +-#define S_DLLRST 0 +-#define V_DLLRST(x) ((x) << S_DLLRST) +-#define F_DLLRST V_DLLRST(1U) +- +-#define A_MC7_PARM 0x120 +- +-#define S_ACTTOPREDLY 26 +-#define M_ACTTOPREDLY 0xf +-#define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY) +- +-#define S_ACTTORDWRDLY 23 +-#define M_ACTTORDWRDLY 0x7 +-#define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY) +- +-#define S_PRECYC 20 +-#define M_PRECYC 0x7 +-#define V_PRECYC(x) ((x) << S_PRECYC) +- +-#define S_REFCYC 13 +-#define M_REFCYC 0x7f +-#define V_REFCYC(x) ((x) << S_REFCYC) +- +-#define S_BKCYC 8 +-#define M_BKCYC 0x1f +-#define V_BKCYC(x) ((x) << S_BKCYC) +- +-#define S_WRTORDDLY 4 +-#define M_WRTORDDLY 0xf +-#define V_WRTORDDLY(x) ((x) << S_WRTORDDLY) +- +-#define S_RDTOWRDLY 0 +-#define M_RDTOWRDLY 0xf +-#define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY) +- +-#define A_MC7_CAL 0x128 +- +-#define S_BUSY 31 +-#define V_BUSY(x) ((x) << S_BUSY) +-#define F_BUSY V_BUSY(1U) +- +-#define S_BUSY 31 +-#define V_BUSY(x) ((x) << S_BUSY) +-#define F_BUSY V_BUSY(1U) +- + #define S_CAL_FAULT 30 + #define V_CAL_FAULT(x) ((x) << S_CAL_FAULT) + #define F_CAL_FAULT V_CAL_FAULT(1U) + ++#define S_PER_CAL_DIV 22 ++#define M_PER_CAL_DIV 0xff ++#define V_PER_CAL_DIV(x) ((x) << S_PER_CAL_DIV) ++#define G_PER_CAL_DIV(x) (((x) >> S_PER_CAL_DIV) & M_PER_CAL_DIV) ++ ++#define S_PER_CAL_EN 21 ++#define V_PER_CAL_EN(x) ((x) << S_PER_CAL_EN) ++#define F_PER_CAL_EN V_PER_CAL_EN(1U) ++ + #define S_SGL_CAL_EN 20 + #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN) + #define F_SGL_CAL_EN V_SGL_CAL_EN(1U) + ++#define S_IMP_UPD_MODE 19 ++#define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE) ++#define F_IMP_UPD_MODE V_IMP_UPD_MODE(1U) ++ ++#define S_IMP_SEL 18 ++#define V_IMP_SEL(x) ((x) << S_IMP_SEL) ++#define F_IMP_SEL V_IMP_SEL(1U) ++ ++#define S_IMP_MAN_PD 15 ++#define M_IMP_MAN_PD 0x7 ++#define V_IMP_MAN_PD(x) ((x) << S_IMP_MAN_PD) ++#define G_IMP_MAN_PD(x) (((x) >> S_IMP_MAN_PD) & M_IMP_MAN_PD) ++ ++#define S_IMP_MAN_PU 12 ++#define M_IMP_MAN_PU 0x7 ++#define V_IMP_MAN_PU(x) ((x) << S_IMP_MAN_PU) ++#define G_IMP_MAN_PU(x) (((x) >> S_IMP_MAN_PU) & M_IMP_MAN_PU) ++ ++#define S_IMP_CAL_PD 9 ++#define M_IMP_CAL_PD 0x7 ++#define V_IMP_CAL_PD(x) ((x) << S_IMP_CAL_PD) ++#define G_IMP_CAL_PD(x) (((x) >> S_IMP_CAL_PD) & M_IMP_CAL_PD) ++ ++#define S_IMP_CAL_PU 6 ++#define M_IMP_CAL_PU 0x7 ++#define V_IMP_CAL_PU(x) ((x) << S_IMP_CAL_PU) ++#define G_IMP_CAL_PU(x) (((x) >> S_IMP_CAL_PU) & M_IMP_CAL_PU) ++ ++#define S_IMP_SET_PD 3 ++#define M_IMP_SET_PD 0x7 ++#define V_IMP_SET_PD(x) ((x) << S_IMP_SET_PD) ++#define G_IMP_SET_PD(x) (((x) >> S_IMP_SET_PD) & M_IMP_SET_PD) ++ ++#define S_IMP_SET_PU 0 ++#define M_IMP_SET_PU 0x7 ++#define V_IMP_SET_PU(x) ((x) << S_IMP_SET_PU) ++#define G_IMP_SET_PU(x) (((x) >> S_IMP_SET_PU) & M_IMP_SET_PU) ++ + #define A_MC7_ERR_ADDR 0x12c + ++#define S_ERRADDRESS 3 ++#define M_ERRADDRESS 0x1fffffff ++#define V_ERRADDRESS(x) ((x) << S_ERRADDRESS) ++#define G_ERRADDRESS(x) (((x) >> S_ERRADDRESS) & M_ERRADDRESS) ++ ++#define S_ERRAGENT 1 ++#define M_ERRAGENT 0x3 ++#define V_ERRAGENT(x) ((x) << S_ERRAGENT) ++#define G_ERRAGENT(x) (((x) >> S_ERRAGENT) & M_ERRAGENT) ++ ++#define S_ERROP 0 ++#define V_ERROP(x) ((x) << S_ERROP) ++#define F_ERROP V_ERROP(1U) ++ + #define A_MC7_ECC 0x130 ++ ++#define S_UECNT 10 ++#define M_UECNT 0xff ++#define V_UECNT(x) ((x) << S_UECNT) ++#define G_UECNT(x) (((x) >> S_UECNT) & M_UECNT) ++ ++#define S_CECNT 2 ++#define M_CECNT 0xff ++#define V_CECNT(x) ((x) << S_CECNT) ++#define G_CECNT(x) (((x) >> S_CECNT) & M_CECNT) + + #define S_ECCCHKEN 1 + #define V_ECCCHKEN(x) ((x) << S_ECCCHKEN) +@@ -754,59 +2938,65 @@ + #define F_ECCGENEN V_ECCGENEN(1U) + + #define A_MC7_CE_ADDR 0x134 +- + #define A_MC7_CE_DATA0 0x138 +- + #define A_MC7_CE_DATA1 0x13c +- + #define A_MC7_CE_DATA2 0x140 + + #define S_DATA 0 + #define M_DATA 0xff +- ++#define V_DATA(x) ((x) << S_DATA) + #define G_DATA(x) (((x) >> S_DATA) & M_DATA) + + #define A_MC7_UE_ADDR 0x144 +- + #define A_MC7_UE_DATA0 0x148 +- + #define A_MC7_UE_DATA1 0x14c +- + #define A_MC7_UE_DATA2 0x150 +- + #define A_MC7_BD_ADDR 0x154 + + #define S_ADDR 3 +- + #define M_ADDR 0x1fffffff ++#define V_ADDR(x) ((x) << S_ADDR) ++#define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR) + + #define A_MC7_BD_DATA0 0x158 +- + #define A_MC7_BD_DATA1 0x15c +- ++#define A_MC7_BD_DATA2 0x160 + #define A_MC7_BD_OP 0x164 + + #define S_OP 0 +- + #define V_OP(x) ((x) << S_OP) + #define F_OP V_OP(1U) + +-#define F_OP V_OP(1U) +-#define A_SF_OP 0x6dc +- + #define A_MC7_BIST_ADDR_BEG 0x168 + ++#define S_ADDRBEG 5 ++#define M_ADDRBEG 0x7ffffff ++#define V_ADDRBEG(x) ((x) << S_ADDRBEG) ++#define G_ADDRBEG(x) (((x) >> S_ADDRBEG) & M_ADDRBEG) ++ + #define A_MC7_BIST_ADDR_END 0x16c + ++#define S_ADDREND 5 ++#define M_ADDREND 0x7ffffff ++#define V_ADDREND(x) ((x) << S_ADDREND) ++#define G_ADDREND(x) (((x) >> S_ADDREND) & M_ADDREND) ++ + #define A_MC7_BIST_DATA 0x170 +- + #define A_MC7_BIST_OP 0x174 ++ ++#define S_GAP 4 ++#define M_GAP 0x1f ++#define V_GAP(x) ((x) << S_GAP) ++#define G_GAP(x) (((x) >> S_GAP) & M_GAP) + + #define S_CONT 3 + #define V_CONT(x) ((x) << S_CONT) + #define F_CONT V_CONT(1U) + +-#define F_CONT V_CONT(1U) ++#define S_DATAPAT 1 ++#define M_DATAPAT 0x3 ++#define V_DATAPAT(x) ((x) << S_DATAPAT) ++#define G_DATAPAT(x) (((x) >> S_DATAPAT) & M_DATAPAT) + + #define A_MC7_INT_ENABLE 0x178 + +@@ -816,9 +3006,7 @@ + + #define S_PE 2 + #define M_PE 0x7fff +- + #define V_PE(x) ((x) << S_PE) +- + #define G_PE(x) (((x) >> S_PE) & M_PE) + + #define S_UE 1 +@@ -831,19 +3019,64 @@ + + #define A_MC7_INT_CAUSE 0x17c + ++/* registers for module MC7_PMTX */ + #define MC7_PMTX_BASE_ADDR 0x180 + ++/* registers for module MC7_CM */ + #define MC7_CM_BASE_ADDR 0x200 ++ ++/* registers for module CIM */ ++#define CIM_BASE_ADDR 0x280 + + #define A_CIM_BOOT_CFG 0x280 + + #define S_BOOTADDR 2 + #define M_BOOTADDR 0x3fffffff + #define V_BOOTADDR(x) ((x) << S_BOOTADDR) ++#define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR) ++ ++#define S_BOOTSDRAM 1 ++#define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM) ++#define F_BOOTSDRAM V_BOOTSDRAM(1U) ++ ++#define S_UPCRST 0 ++#define V_UPCRST(x) ((x) << S_UPCRST) ++#define F_UPCRST V_UPCRST(1U) ++ ++#define A_CIM_FLASH_BASE_ADDR 0x284 ++ ++#define S_FLASHBASEADDR 2 ++#define M_FLASHBASEADDR 0x3fffff ++#define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR) ++#define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR) ++ ++#define A_CIM_FLASH_ADDR_SIZE 0x288 ++ ++#define S_FLASHADDRSIZE 2 ++#define M_FLASHADDRSIZE 0x3fffff ++#define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE) ++#define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE) + + #define A_CIM_SDRAM_BASE_ADDR 0x28c + ++#define S_SDRAMBASEADDR 2 ++#define M_SDRAMBASEADDR 0x3fffffff ++#define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR) ++#define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR) ++ + #define A_CIM_SDRAM_ADDR_SIZE 0x290 ++ ++#define S_SDRAMADDRSIZE 2 ++#define M_SDRAMADDRSIZE 0x3fffffff ++#define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE) ++#define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE) ++ ++#define A_CIM_UP_SPARE_INT 0x294 ++ ++#define S_UPSPAREINT 0 ++#define M_UPSPAREINT 0x7 ++#define V_UPSPAREINT(x) ((x) << S_UPSPAREINT) ++#define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT) + + #define A_CIM_HOST_INT_ENABLE 0x298 + +@@ -895,7 +3128,83 @@ + #define V_DRAMPARERR(x) ((x) << S_DRAMPARERR) + #define F_DRAMPARERR V_DRAMPARERR(1U) + ++#define S_TIMER1INTEN 15 ++#define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN) ++#define F_TIMER1INTEN V_TIMER1INTEN(1U) ++ ++#define S_TIMER0INTEN 14 ++#define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN) ++#define F_TIMER0INTEN V_TIMER0INTEN(1U) ++ ++#define S_PREFDROPINTEN 13 ++#define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN) ++#define F_PREFDROPINTEN V_PREFDROPINTEN(1U) ++ ++#define S_BLKWRPLINTEN 12 ++#define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN) ++#define F_BLKWRPLINTEN V_BLKWRPLINTEN(1U) ++ ++#define S_BLKRDPLINTEN 11 ++#define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN) ++#define F_BLKRDPLINTEN V_BLKRDPLINTEN(1U) ++ ++#define S_BLKWRCTLINTEN 10 ++#define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN) ++#define F_BLKWRCTLINTEN V_BLKWRCTLINTEN(1U) ++ ++#define S_BLKRDCTLINTEN 9 ++#define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN) ++#define F_BLKRDCTLINTEN V_BLKRDCTLINTEN(1U) ++ ++#define S_BLKWRFLASHINTEN 8 ++#define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN) ++#define F_BLKWRFLASHINTEN V_BLKWRFLASHINTEN(1U) ++ ++#define S_BLKRDFLASHINTEN 7 ++#define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN) ++#define F_BLKRDFLASHINTEN V_BLKRDFLASHINTEN(1U) ++ ++#define S_SGLWRFLASHINTEN 6 ++#define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN) ++#define F_SGLWRFLASHINTEN V_SGLWRFLASHINTEN(1U) ++ ++#define S_WRBLKFLASHINTEN 5 ++#define V_WRBLKFLASHINTEN(x) ((x) << S_WRBLKFLASHINTEN) ++#define F_WRBLKFLASHINTEN V_WRBLKFLASHINTEN(1U) ++ ++#define S_BLKWRBOOTINTEN 4 ++#define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN) ++#define F_BLKWRBOOTINTEN V_BLKWRBOOTINTEN(1U) ++ ++#define S_BLKRDBOOTINTEN 3 ++#define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN) ++#define F_BLKRDBOOTINTEN V_BLKRDBOOTINTEN(1U) ++ ++#define S_FLASHRANGEINTEN 2 ++#define V_FLASHRANGEINTEN(x) ((x) << S_FLASHRANGEINTEN) ++#define F_FLASHRANGEINTEN V_FLASHRANGEINTEN(1U) ++ ++#define S_SDRAMRANGEINTEN 1 ++#define V_SDRAMRANGEINTEN(x) ((x) << S_SDRAMRANGEINTEN) ++#define F_SDRAMRANGEINTEN V_SDRAMRANGEINTEN(1U) ++ ++#define S_RSVDSPACEINTEN 0 ++#define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN) ++#define F_RSVDSPACEINTEN V_RSVDSPACEINTEN(1U) ++ + #define A_CIM_HOST_INT_CAUSE 0x29c ++ ++#define S_TIMER1INT 15 ++#define V_TIMER1INT(x) ((x) << S_TIMER1INT) ++#define F_TIMER1INT V_TIMER1INT(1U) ++ ++#define S_TIMER0INT 14 ++#define V_TIMER0INT(x) ((x) << S_TIMER0INT) ++#define F_TIMER0INT V_TIMER0INT(1U) ++ ++#define S_PREFDROPINT 13 ++#define V_PREFDROPINT(x) ((x) << S_PREFDROPINT) ++#define F_PREFDROPINT V_PREFDROPINT(1U) + + #define S_BLKWRPLINT 12 + #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT) +@@ -933,6 +3242,10 @@ + #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT) + #define F_BLKWRBOOTINT V_BLKWRBOOTINT(1U) + ++#define S_BLKRDBOOTINT 3 ++#define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT) ++#define F_BLKRDBOOTINT V_BLKRDBOOTINT(1U) ++ + #define S_FLASHRANGEINT 2 + #define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT) + #define F_FLASHRANGEINT V_FLASHRANGEINT(1U) +@@ -945,14 +3258,58 @@ + #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT) + #define F_RSVDSPACEINT V_RSVDSPACEINT(1U) + ++#define A_CIM_UP_INT_ENABLE 0x2a0 ++ ++#define S_MSTPLINTEN 16 ++#define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN) ++#define F_MSTPLINTEN V_MSTPLINTEN(1U) ++ ++#define A_CIM_UP_INT_CAUSE 0x2a4 ++ ++#define S_MSTPLINT 16 ++#define V_MSTPLINT(x) ((x) << S_MSTPLINT) ++#define F_MSTPLINT V_MSTPLINT(1U) ++ ++#define A_CIM_IBQ_FULLA_THRSH 0x2a8 ++ ++#define S_IBQ0FULLTHRSH 0 ++#define M_IBQ0FULLTHRSH 0x1ff ++#define V_IBQ0FULLTHRSH(x) ((x) << S_IBQ0FULLTHRSH) ++#define G_IBQ0FULLTHRSH(x) (((x) >> S_IBQ0FULLTHRSH) & M_IBQ0FULLTHRSH) ++ ++#define S_IBQ1FULLTHRSH 16 ++#define M_IBQ1FULLTHRSH 0x1ff ++#define V_IBQ1FULLTHRSH(x) ((x) << S_IBQ1FULLTHRSH) ++#define G_IBQ1FULLTHRSH(x) (((x) >> S_IBQ1FULLTHRSH) & M_IBQ1FULLTHRSH) ++ ++#define A_CIM_IBQ_FULLB_THRSH 0x2ac ++ ++#define S_IBQ2FULLTHRSH 0 ++#define M_IBQ2FULLTHRSH 0x1ff ++#define V_IBQ2FULLTHRSH(x) ((x) << S_IBQ2FULLTHRSH) ++#define G_IBQ2FULLTHRSH(x) (((x) >> S_IBQ2FULLTHRSH) & M_IBQ2FULLTHRSH) ++ ++#define S_IBQ3FULLTHRSH 16 ++#define M_IBQ3FULLTHRSH 0x1ff ++#define V_IBQ3FULLTHRSH(x) ((x) << S_IBQ3FULLTHRSH) ++#define G_IBQ3FULLTHRSH(x) (((x) >> S_IBQ3FULLTHRSH) & M_IBQ3FULLTHRSH) ++ + #define A_CIM_HOST_ACC_CTRL 0x2b0 + + #define S_HOSTBUSY 17 + #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY) + #define F_HOSTBUSY V_HOSTBUSY(1U) + ++#define S_HOSTWRITE 16 ++#define V_HOSTWRITE(x) ((x) << S_HOSTWRITE) ++#define F_HOSTWRITE V_HOSTWRITE(1U) ++ ++#define S_HOSTADDR 0 ++#define M_HOSTADDR 0xffff ++#define V_HOSTADDR(x) ((x) << S_HOSTADDR) ++#define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR) ++ + #define A_CIM_HOST_ACC_DATA 0x2b4 +- + #define A_CIM_IBQ_DBG_CFG 0x2c0 + + #define S_IBQDBGADDR 16 +@@ -977,7 +3334,87 @@ + #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN) + #define F_IBQDBGEN V_IBQDBGEN(1U) + ++#define A_CIM_OBQ_DBG_CFG 0x2c4 ++ ++#define S_OBQDBGADDR 16 ++#define M_OBQDBGADDR 0x1ff ++#define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR) ++#define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR) ++ ++#define S_OBQDBGQID 3 ++#define M_OBQDBGQID 0x3 ++#define V_OBQDBGQID(x) ((x) << S_OBQDBGQID) ++#define G_OBQDBGQID(x) (((x) >> S_OBQDBGQID) & M_OBQDBGQID) ++ ++#define S_OBQDBGWR 2 ++#define V_OBQDBGWR(x) ((x) << S_OBQDBGWR) ++#define F_OBQDBGWR V_OBQDBGWR(1U) ++ ++#define S_OBQDBGBUSY 1 ++#define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY) ++#define F_OBQDBGBUSY V_OBQDBGBUSY(1U) ++ ++#define S_OBQDBGEN 0 ++#define V_OBQDBGEN(x) ((x) << S_OBQDBGEN) ++#define F_OBQDBGEN V_OBQDBGEN(1U) ++ + #define A_CIM_IBQ_DBG_DATA 0x2c8 ++#define A_CIM_OBQ_DBG_DATA 0x2cc ++#define A_CIM_CDEBUGDATA 0x2d0 ++ ++#define S_CDEBUGDATAH 16 ++#define M_CDEBUGDATAH 0xffff ++#define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH) ++#define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH) ++ ++#define S_CDEBUGDATAL 0 ++#define M_CDEBUGDATAL 0xffff ++#define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL) ++#define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL) ++ ++#define A_CIM_DEBUGCFG 0x2e0 ++ ++#define S_POLADBGRDPTR 23 ++#define M_POLADBGRDPTR 0x1ff ++#define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR) ++#define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR) ++ ++#define S_PILADBGRDPTR 14 ++#define M_PILADBGRDPTR 0x1ff ++#define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR) ++#define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR) ++ ++#define S_CIM_LADBGEN 12 ++#define V_CIM_LADBGEN(x) ((x) << S_CIM_LADBGEN) ++#define F_CIM_LADBGEN V_CIM_LADBGEN(1U) ++ ++#define S_DEBUGSELHI 5 ++#define M_DEBUGSELHI 0x1f ++#define V_DEBUGSELHI(x) ((x) << S_DEBUGSELHI) ++#define G_DEBUGSELHI(x) (((x) >> S_DEBUGSELHI) & M_DEBUGSELHI) ++ ++#define S_DEBUGSELLO 0 ++#define M_DEBUGSELLO 0x1f ++#define V_DEBUGSELLO(x) ((x) << S_DEBUGSELLO) ++#define G_DEBUGSELLO(x) (((x) >> S_DEBUGSELLO) & M_DEBUGSELLO) ++ ++#define A_CIM_DEBUGSTS 0x2e4 ++ ++#define S_POLADBGWRPTR 16 ++#define M_POLADBGWRPTR 0x1ff ++#define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR) ++#define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR) ++ ++#define S_PILADBGWRPTR 0 ++#define M_PILADBGWRPTR 0x1ff ++#define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR) ++#define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR) ++ ++#define A_CIM_PO_LA_DEBUGDATA 0x2e8 ++#define A_CIM_PI_LA_DEBUGDATA 0x2ec ++ ++/* registers for module TP1 */ ++#define TP1_BASE_ADDR 0x300 + + #define A_TP_IN_CONFIG 0x300 + +@@ -989,30 +3426,153 @@ + #define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO) + #define F_TXFBARBPRIO V_TXFBARBPRIO(1U) + ++#define S_DBMAXOPCNT 16 ++#define M_DBMAXOPCNT 0xff ++#define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT) ++#define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT) ++ ++#define S_IPV6ENABLE 15 ++#define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE) ++#define F_IPV6ENABLE V_IPV6ENABLE(1U) ++ + #define S_NICMODE 14 + #define V_NICMODE(x) ((x) << S_NICMODE) + #define F_NICMODE V_NICMODE(1U) + +-#define F_NICMODE V_NICMODE(1U) +- +-#define S_IPV6ENABLE 15 +-#define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE) +-#define F_IPV6ENABLE V_IPV6ENABLE(1U) ++#define S_ECHECKSUMCHECKTCP 13 ++#define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP) ++#define F_ECHECKSUMCHECKTCP V_ECHECKSUMCHECKTCP(1U) ++ ++#define S_ECHECKSUMCHECKIP 12 ++#define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP) ++#define F_ECHECKSUMCHECKIP V_ECHECKSUMCHECKIP(1U) ++ ++#define S_ECPL 10 ++#define V_ECPL(x) ((x) << S_ECPL) ++#define F_ECPL V_ECPL(1U) ++ ++#define S_EETHERNET 8 ++#define V_EETHERNET(x) ((x) << S_EETHERNET) ++#define F_EETHERNET V_EETHERNET(1U) ++ ++#define S_ETUNNEL 7 ++#define V_ETUNNEL(x) ((x) << S_ETUNNEL) ++#define F_ETUNNEL V_ETUNNEL(1U) ++ ++#define S_CCHECKSUMCHECKTCP 6 ++#define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP) ++#define F_CCHECKSUMCHECKTCP V_CCHECKSUMCHECKTCP(1U) ++ ++#define S_CCHECKSUMCHECKIP 5 ++#define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP) ++#define F_CCHECKSUMCHECKIP V_CCHECKSUMCHECKIP(1U) ++ ++#define S_CCPL 3 ++#define V_CCPL(x) ((x) << S_CCPL) ++#define F_CCPL V_CCPL(1U) ++ ++#define S_CETHERNET 1 ++#define V_CETHERNET(x) ((x) << S_CETHERNET) ++#define F_CETHERNET V_CETHERNET(1U) ++ ++#define S_CTUNNEL 0 ++#define V_CTUNNEL(x) ((x) << S_CTUNNEL) ++#define F_CTUNNEL V_CTUNNEL(1U) + + #define A_TP_OUT_CONFIG 0x304 + ++#define S_IPIDSPLITMODE 16 ++#define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE) ++#define F_IPIDSPLITMODE V_IPIDSPLITMODE(1U) ++ ++#define S_VLANEXTRACTIONENABLE2NDPORT 13 ++#define V_VLANEXTRACTIONENABLE2NDPORT(x) ((x) << S_VLANEXTRACTIONENABLE2NDPORT) ++#define F_VLANEXTRACTIONENABLE2NDPORT V_VLANEXTRACTIONENABLE2NDPORT(1U) ++ + #define S_VLANEXTRACTIONENABLE 12 ++#define V_VLANEXTRACTIONENABLE(x) ((x) << S_VLANEXTRACTIONENABLE) ++#define F_VLANEXTRACTIONENABLE V_VLANEXTRACTIONENABLE(1U) ++ ++#define S_ECHECKSUMGENERATETCP 11 ++#define V_ECHECKSUMGENERATETCP(x) ((x) << S_ECHECKSUMGENERATETCP) ++#define F_ECHECKSUMGENERATETCP V_ECHECKSUMGENERATETCP(1U) ++ ++#define S_ECHECKSUMGENERATEIP 10 ++#define V_ECHECKSUMGENERATEIP(x) ((x) << S_ECHECKSUMGENERATEIP) ++#define F_ECHECKSUMGENERATEIP V_ECHECKSUMGENERATEIP(1U) ++ ++#define S_OUT_ECPL 8 ++#define V_OUT_ECPL(x) ((x) << S_OUT_ECPL) ++#define F_OUT_ECPL V_OUT_ECPL(1U) ++ ++#define S_OUT_EETHERNET 6 ++#define V_OUT_EETHERNET(x) ((x) << S_OUT_EETHERNET) ++#define F_OUT_EETHERNET V_OUT_EETHERNET(1U) ++ ++#define S_CCHECKSUMGENERATETCP 5 ++#define V_CCHECKSUMGENERATETCP(x) ((x) << S_CCHECKSUMGENERATETCP) ++#define F_CCHECKSUMGENERATETCP V_CCHECKSUMGENERATETCP(1U) ++ ++#define S_CCHECKSUMGENERATEIP 4 ++#define V_CCHECKSUMGENERATEIP(x) ((x) << S_CCHECKSUMGENERATEIP) ++#define F_CCHECKSUMGENERATEIP V_CCHECKSUMGENERATEIP(1U) ++ ++#define S_OUT_CCPL 2 ++#define V_OUT_CCPL(x) ((x) << S_OUT_CCPL) ++#define F_OUT_CCPL V_OUT_CCPL(1U) ++ ++#define S_OUT_CETHERNET 0 ++#define V_OUT_CETHERNET(x) ((x) << S_OUT_CETHERNET) ++#define F_OUT_CETHERNET V_OUT_CETHERNET(1U) + + #define A_TP_GLOBAL_CONFIG 0x308 ++ ++#define S_SYNCOOKIEPARAMS 26 ++#define M_SYNCOOKIEPARAMS 0x3f ++#define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS) ++#define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS) ++ ++#define S_RXFLOWCONTROLDISABLE 25 ++#define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE) ++#define F_RXFLOWCONTROLDISABLE V_RXFLOWCONTROLDISABLE(1U) + + #define S_TXPACINGENABLE 24 + #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE) + #define F_TXPACINGENABLE V_TXPACINGENABLE(1U) + ++#define S_ATTACKFILTERENABLE 23 ++#define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE) ++#define F_ATTACKFILTERENABLE V_ATTACKFILTERENABLE(1U) ++ ++#define S_SYNCOOKIENOOPTIONS 22 ++#define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS) ++#define F_SYNCOOKIENOOPTIONS V_SYNCOOKIENOOPTIONS(1U) ++ ++#define S_PROTECTEDMODE 21 ++#define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE) ++#define F_PROTECTEDMODE V_PROTECTEDMODE(1U) ++ ++#define S_PINGDROP 20 ++#define V_PINGDROP(x) ((x) << S_PINGDROP) ++#define F_PINGDROP V_PINGDROP(1U) ++ ++#define S_FRAGMENTDROP 19 ++#define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP) ++#define F_FRAGMENTDROP V_FRAGMENTDROP(1U) ++ ++#define S_FIVETUPLELOOKUP 17 ++#define M_FIVETUPLELOOKUP 0x3 ++#define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP) ++#define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP) ++ + #define S_PATHMTU 15 + #define V_PATHMTU(x) ((x) << S_PATHMTU) + #define F_PATHMTU V_PATHMTU(1U) + ++#define S_IPIDENTSPLIT 14 ++#define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT) ++#define F_IPIDENTSPLIT V_IPIDENTSPLIT(1U) ++ + #define S_IPCHECKSUMOFFLOAD 13 + #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD) + #define F_IPCHECKSUMOFFLOAD V_IPCHECKSUMOFFLOAD(1U) +@@ -1025,83 +3585,133 @@ + #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD) + #define F_TCPCHECKSUMOFFLOAD V_TCPCHECKSUMOFFLOAD(1U) + ++#define S_QOSMAPPING 10 ++#define V_QOSMAPPING(x) ((x) << S_QOSMAPPING) ++#define F_QOSMAPPING V_QOSMAPPING(1U) ++ ++#define S_TCAMSERVERUSE 8 ++#define M_TCAMSERVERUSE 0x3 ++#define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE) ++#define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE) ++ + #define S_IPTTL 0 + #define M_IPTTL 0xff + #define V_IPTTL(x) ((x) << S_IPTTL) ++#define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL) ++ ++#define A_TP_GLOBAL_RX_CREDIT 0x30c ++#define A_TP_CMM_SIZE 0x310 ++ ++#define S_CMMEMMGRSIZE 0 ++#define M_CMMEMMGRSIZE 0xfffffff ++#define V_CMMEMMGRSIZE(x) ((x) << S_CMMEMMGRSIZE) ++#define G_CMMEMMGRSIZE(x) (((x) >> S_CMMEMMGRSIZE) & M_CMMEMMGRSIZE) + + #define A_TP_CMM_MM_BASE 0x314 ++ ++#define S_CMMEMMGRBASE 0 ++#define M_CMMEMMGRBASE 0xfffffff ++#define V_CMMEMMGRBASE(x) ((x) << S_CMMEMMGRBASE) ++#define G_CMMEMMGRBASE(x) (((x) >> S_CMMEMMGRBASE) & M_CMMEMMGRBASE) + + #define A_TP_CMM_TIMER_BASE 0x318 + + #define S_CMTIMERMAXNUM 28 + #define M_CMTIMERMAXNUM 0x3 + #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM) ++#define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM) ++ ++#define S_CMTIMERBASE 0 ++#define M_CMTIMERBASE 0xfffffff ++#define V_CMTIMERBASE(x) ((x) << S_CMTIMERBASE) ++#define G_CMTIMERBASE(x) (((x) >> S_CMTIMERBASE) & M_CMTIMERBASE) + + #define A_TP_PMM_SIZE 0x31c + ++#define S_PMSIZE 0 ++#define M_PMSIZE 0xfffffff ++#define V_PMSIZE(x) ((x) << S_PMSIZE) ++#define G_PMSIZE(x) (((x) >> S_PMSIZE) & M_PMSIZE) ++ + #define A_TP_PMM_TX_BASE 0x320 +- ++#define A_TP_PMM_DEFRAG_BASE 0x324 + #define A_TP_PMM_RX_BASE 0x328 +- + #define A_TP_PMM_RX_PAGE_SIZE 0x32c +- + #define A_TP_PMM_RX_MAX_PAGE 0x330 + ++#define S_PMRXMAXPAGE 0 ++#define M_PMRXMAXPAGE 0x1fffff ++#define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE) ++#define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE) ++ + #define A_TP_PMM_TX_PAGE_SIZE 0x334 +- + #define A_TP_PMM_TX_MAX_PAGE 0x338 ++ ++#define S_PMTXMAXPAGE 0 ++#define M_PMTXMAXPAGE 0x1fffff ++#define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE) ++#define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE) + + #define A_TP_TCP_OPTIONS 0x340 + + #define S_MTUDEFAULT 16 + #define M_MTUDEFAULT 0xffff + #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT) ++#define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT) + + #define S_MTUENABLE 10 + #define V_MTUENABLE(x) ((x) << S_MTUENABLE) + #define F_MTUENABLE V_MTUENABLE(1U) + ++#define S_SACKTX 9 ++#define V_SACKTX(x) ((x) << S_SACKTX) ++#define F_SACKTX V_SACKTX(1U) ++ + #define S_SACKRX 8 + #define V_SACKRX(x) ((x) << S_SACKRX) + #define F_SACKRX V_SACKRX(1U) + + #define S_SACKMODE 4 +- + #define M_SACKMODE 0x3 +- + #define V_SACKMODE(x) ((x) << S_SACKMODE) ++#define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE) + + #define S_WINDOWSCALEMODE 2 + #define M_WINDOWSCALEMODE 0x3 + #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE) ++#define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE) + + #define S_TIMESTAMPSMODE 0 +- + #define M_TIMESTAMPSMODE 0x3 +- + #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE) ++#define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE) + + #define A_TP_DACK_CONFIG 0x344 + + #define S_AUTOSTATE3 30 + #define M_AUTOSTATE3 0x3 + #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3) ++#define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3) + + #define S_AUTOSTATE2 28 + #define M_AUTOSTATE2 0x3 + #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2) ++#define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2) + + #define S_AUTOSTATE1 26 + #define M_AUTOSTATE1 0x3 + #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1) ++#define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1) + + #define S_BYTETHRESHOLD 5 + #define M_BYTETHRESHOLD 0xfffff + #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD) ++#define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD) + + #define S_MSSTHRESHOLD 3 + #define M_MSSTHRESHOLD 0x3 + #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD) ++#define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD) + + #define S_AUTOCAREFUL 2 + #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL) +@@ -1117,10 +3727,38 @@ + + #define A_TP_PC_CONFIG 0x348 + ++#define S_CMCACHEDISABLE 31 ++#define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE) ++#define F_CMCACHEDISABLE V_CMCACHEDISABLE(1U) ++ ++#define S_ENABLEOCSPIFULL 30 ++#define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL) ++#define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U) ++ ++#define S_ENABLEFLMERRORDDP 29 ++#define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP) ++#define F_ENABLEFLMERRORDDP V_ENABLEFLMERRORDDP(1U) ++ ++#define S_LOCKTID 28 ++#define V_LOCKTID(x) ((x) << S_LOCKTID) ++#define F_LOCKTID V_LOCKTID(1U) ++ ++#define S_FIXRCVWND 27 ++#define V_FIXRCVWND(x) ((x) << S_FIXRCVWND) ++#define F_FIXRCVWND V_FIXRCVWND(1U) ++ + #define S_TXTOSQUEUEMAPMODE 26 + #define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE) + #define F_TXTOSQUEUEMAPMODE V_TXTOSQUEUEMAPMODE(1U) + ++#define S_RDDPCONGEN 25 ++#define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN) ++#define F_RDDPCONGEN V_RDDPCONGEN(1U) ++ ++#define S_ENABLEONFLYPDU 24 ++#define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU) ++#define F_ENABLEONFLYPDU V_ENABLEONFLYPDU(1U) ++ + #define S_ENABLEEPCMDAFULL 23 + #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL) + #define F_ENABLEEPCMDAFULL V_ENABLEEPCMDAFULL(1U) +@@ -1129,6 +3767,10 @@ + #define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE) + #define F_MODULATEUNIONMODE V_MODULATEUNIONMODE(1U) + ++#define S_TXDATAACKRATEENABLE 21 ++#define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE) ++#define F_TXDATAACKRATEENABLE V_TXDATAACKRATEENABLE(1U) ++ + #define S_TXDEFERENABLE 20 + #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE) + #define F_TXDEFERENABLE V_TXDEFERENABLE(1U) +@@ -1137,6 +3779,14 @@ + #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE) + #define F_RXCONGESTIONMODE V_RXCONGESTIONMODE(1U) + ++#define S_HEARBEATONCEDACK 18 ++#define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK) ++#define F_HEARBEATONCEDACK V_HEARBEATONCEDACK(1U) ++ ++#define S_HEARBEATONCEHEAP 17 ++#define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP) ++#define F_HEARBEATONCEHEAP V_HEARBEATONCEHEAP(1U) ++ + #define S_HEARBEATDACK 16 + #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK) + #define F_HEARBEATDACK V_HEARBEATDACK(1U) +@@ -1145,19 +3795,54 @@ + #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE) + #define F_TXCONGESTIONMODE V_TXCONGESTIONMODE(1U) + +-#define S_ENABLEOCSPIFULL 30 +-#define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL) +-#define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U) +- +-#define S_LOCKTID 28 +-#define V_LOCKTID(x) ((x) << S_LOCKTID) +-#define F_LOCKTID V_LOCKTID(1U) ++#define S_ACCEPTLATESTRCVADV 14 ++#define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV) ++#define F_ACCEPTLATESTRCVADV V_ACCEPTLATESTRCVADV(1U) ++ ++#define S_DISABLESYNDATA 13 ++#define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA) ++#define F_DISABLESYNDATA V_DISABLESYNDATA(1U) ++ ++#define S_DISABLEWINDOWPSH 12 ++#define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH) ++#define F_DISABLEWINDOWPSH V_DISABLEWINDOWPSH(1U) ++ ++#define S_DISABLEFINOLDDATA 11 ++#define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA) ++#define F_DISABLEFINOLDDATA V_DISABLEFINOLDDATA(1U) ++ ++#define S_ENABLEFLMERROR 10 ++#define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR) ++#define F_ENABLEFLMERROR V_ENABLEFLMERROR(1U) ++ ++#define S_DISABLENEXTMTU 9 ++#define V_DISABLENEXTMTU(x) ((x) << S_DISABLENEXTMTU) ++#define F_DISABLENEXTMTU V_DISABLENEXTMTU(1U) ++ ++#define S_FILTERPEERFIN 8 ++#define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN) ++#define F_FILTERPEERFIN V_FILTERPEERFIN(1U) ++ ++#define S_ENABLEFEEDBACKSEND 7 ++#define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND) ++#define F_ENABLEFEEDBACKSEND V_ENABLEFEEDBACKSEND(1U) ++ ++#define S_ENABLERDMAERROR 6 ++#define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR) ++#define F_ENABLERDMAERROR V_ENABLERDMAERROR(1U) ++ ++#define S_ENABLEDDPFLOWCONTROL 5 ++#define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL) ++#define F_ENABLEDDPFLOWCONTROL V_ENABLEDDPFLOWCONTROL(1U) ++ ++#define S_DISABLEHELDFIN 4 ++#define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN) ++#define F_DISABLEHELDFIN V_DISABLEHELDFIN(1U) + + #define S_TABLELATENCYDELTA 0 + #define M_TABLELATENCYDELTA 0xf + #define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA) +-#define G_TABLELATENCYDELTA(x) \ +- (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA) ++#define G_TABLELATENCYDELTA(x) (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA) + + #define A_TP_PC_CONFIG2 0x34c + +@@ -1177,34 +3862,201 @@ + #define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS) + #define F_ENABLEIPV6RSS V_ENABLEIPV6RSS(1U) + ++#define S_ENABLEDROPRQEMPTYPKT 10 ++#define V_ENABLEDROPRQEMPTYPKT(x) ((x) << S_ENABLEDROPRQEMPTYPKT) ++#define F_ENABLEDROPRQEMPTYPKT V_ENABLEDROPRQEMPTYPKT(1U) ++ ++#define S_ENABLETXPORTFROMDA2 9 ++#define V_ENABLETXPORTFROMDA2(x) ((x) << S_ENABLETXPORTFROMDA2) ++#define F_ENABLETXPORTFROMDA2 V_ENABLETXPORTFROMDA2(1U) ++ ++#define S_ENABLERXPKTTMSTPRSS 8 ++#define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS) ++#define F_ENABLERXPKTTMSTPRSS V_ENABLERXPKTTMSTPRSS(1U) ++ ++#define S_ENABLESNDUNAINRXDATA 7 ++#define V_ENABLESNDUNAINRXDATA(x) ((x) << S_ENABLESNDUNAINRXDATA) ++#define F_ENABLESNDUNAINRXDATA V_ENABLESNDUNAINRXDATA(1U) ++ ++#define S_ENABLERXPORTFROMADDR 6 ++#define V_ENABLERXPORTFROMADDR(x) ((x) << S_ENABLERXPORTFROMADDR) ++#define F_ENABLERXPORTFROMADDR V_ENABLERXPORTFROMADDR(1U) ++ ++#define S_ENABLETXPORTFROMDA 5 ++#define V_ENABLETXPORTFROMDA(x) ((x) << S_ENABLETXPORTFROMDA) ++#define F_ENABLETXPORTFROMDA V_ENABLETXPORTFROMDA(1U) ++ ++#define S_ENABLECHDRAFULL 4 ++#define V_ENABLECHDRAFULL(x) ((x) << S_ENABLECHDRAFULL) ++#define F_ENABLECHDRAFULL V_ENABLECHDRAFULL(1U) ++ ++#define S_ENABLENONOFDSCBBIT 3 ++#define V_ENABLENONOFDSCBBIT(x) ((x) << S_ENABLENONOFDSCBBIT) ++#define F_ENABLENONOFDSCBBIT V_ENABLENONOFDSCBBIT(1U) ++ ++#define S_ENABLENONOFDTIDRSS 2 ++#define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS) ++#define F_ENABLENONOFDTIDRSS V_ENABLENONOFDTIDRSS(1U) ++ ++#define S_ENABLENONOFDTCBRSS 1 ++#define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS) ++#define F_ENABLENONOFDTCBRSS V_ENABLENONOFDTCBRSS(1U) ++ ++#define S_ENABLEOLDRXFORWARD 0 ++#define V_ENABLEOLDRXFORWARD(x) ((x) << S_ENABLEOLDRXFORWARD) ++#define F_ENABLEOLDRXFORWARD V_ENABLEOLDRXFORWARD(1U) ++ + #define S_CHDRAFULL 4 + #define V_CHDRAFULL(x) ((x) << S_CHDRAFULL) + #define F_CHDRAFULL V_CHDRAFULL(1U) + + #define A_TP_TCP_BACKOFF_REG0 0x350 + ++#define S_TIMERBACKOFFINDEX3 24 ++#define M_TIMERBACKOFFINDEX3 0xff ++#define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3) ++#define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3) ++ ++#define S_TIMERBACKOFFINDEX2 16 ++#define M_TIMERBACKOFFINDEX2 0xff ++#define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2) ++#define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2) ++ ++#define S_TIMERBACKOFFINDEX1 8 ++#define M_TIMERBACKOFFINDEX1 0xff ++#define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1) ++#define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1) ++ ++#define S_TIMERBACKOFFINDEX0 0 ++#define M_TIMERBACKOFFINDEX0 0xff ++#define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0) ++#define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0) ++ + #define A_TP_TCP_BACKOFF_REG1 0x354 + ++#define S_TIMERBACKOFFINDEX7 24 ++#define M_TIMERBACKOFFINDEX7 0xff ++#define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7) ++#define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7) ++ ++#define S_TIMERBACKOFFINDEX6 16 ++#define M_TIMERBACKOFFINDEX6 0xff ++#define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6) ++#define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6) ++ ++#define S_TIMERBACKOFFINDEX5 8 ++#define M_TIMERBACKOFFINDEX5 0xff ++#define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5) ++#define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5) ++ ++#define S_TIMERBACKOFFINDEX4 0 ++#define M_TIMERBACKOFFINDEX4 0xff ++#define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4) ++#define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4) ++ + #define A_TP_TCP_BACKOFF_REG2 0x358 + ++#define S_TIMERBACKOFFINDEX11 24 ++#define M_TIMERBACKOFFINDEX11 0xff ++#define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11) ++#define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11) ++ ++#define S_TIMERBACKOFFINDEX10 16 ++#define M_TIMERBACKOFFINDEX10 0xff ++#define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10) ++#define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10) ++ ++#define S_TIMERBACKOFFINDEX9 8 ++#define M_TIMERBACKOFFINDEX9 0xff ++#define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9) ++#define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9) ++ ++#define S_TIMERBACKOFFINDEX8 0 ++#define M_TIMERBACKOFFINDEX8 0xff ++#define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8) ++#define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8) ++ + #define A_TP_TCP_BACKOFF_REG3 0x35c ++ ++#define S_TIMERBACKOFFINDEX15 24 ++#define M_TIMERBACKOFFINDEX15 0xff ++#define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15) ++#define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15) ++ ++#define S_TIMERBACKOFFINDEX14 16 ++#define M_TIMERBACKOFFINDEX14 0xff ++#define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14) ++#define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14) ++ ++#define S_TIMERBACKOFFINDEX13 8 ++#define M_TIMERBACKOFFINDEX13 0xff ++#define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13) ++#define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13) ++ ++#define S_TIMERBACKOFFINDEX12 0 ++#define M_TIMERBACKOFFINDEX12 0xff ++#define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12) ++#define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12) ++ ++#define A_TP_PARA_REG0 0x360 ++ ++#define S_INITCWND 24 ++#define M_INITCWND 0x7 ++#define V_INITCWND(x) ((x) << S_INITCWND) ++#define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND) ++ ++#define S_DUPACKTHRESH 20 ++#define M_DUPACKTHRESH 0xf ++#define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH) ++#define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH) ++ ++#define A_TP_PARA_REG1 0x364 ++ ++#define S_INITRWND 16 ++#define M_INITRWND 0xffff ++#define V_INITRWND(x) ((x) << S_INITRWND) ++#define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND) ++ ++#define S_INITIALSSTHRESH 0 ++#define M_INITIALSSTHRESH 0xffff ++#define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH) ++#define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH) + + #define A_TP_PARA_REG2 0x368 + + #define S_MAXRXDATA 16 + #define M_MAXRXDATA 0xffff + #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA) ++#define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA) + + #define S_RXCOALESCESIZE 0 + #define M_RXCOALESCESIZE 0xffff + #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE) ++#define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE) + + #define A_TP_PARA_REG3 0x36c ++ ++#define S_TUNNELCNGDROP1 21 ++#define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1) ++#define F_TUNNELCNGDROP1 V_TUNNELCNGDROP1(1U) ++ ++#define S_TUNNELCNGDROP0 20 ++#define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0) ++#define F_TUNNELCNGDROP0 V_TUNNELCNGDROP0(1U) + + #define S_TXDATAACKIDX 16 + #define M_TXDATAACKIDX 0xf +- + #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX) ++#define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX) ++ ++#define S_RXFRAGENABLE 12 ++#define M_RXFRAGENABLE 0x7 ++#define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE) ++#define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE) ++ ++#define S_TXPACEFIXEDSTRICT 11 ++#define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT) ++#define F_TXPACEFIXEDSTRICT V_TXPACEFIXEDSTRICT(1U) + + #define S_TXPACEAUTOSTRICT 10 + #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT) +@@ -1218,6 +4070,23 @@ + #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO) + #define F_TXPACEAUTO V_TXPACEAUTO(1U) + ++#define S_RXURGTUNNEL 6 ++#define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL) ++#define F_RXURGTUNNEL V_RXURGTUNNEL(1U) ++ ++#define S_RXURGMODE 5 ++#define V_RXURGMODE(x) ((x) << S_RXURGMODE) ++#define F_RXURGMODE V_RXURGMODE(1U) ++ ++#define S_TXURGMODE 4 ++#define V_TXURGMODE(x) ((x) << S_TXURGMODE) ++#define F_TXURGMODE V_TXURGMODE(1U) ++ ++#define S_CNGCTRLMODE 2 ++#define M_CNGCTRLMODE 0x3 ++#define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE) ++#define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE) ++ + #define S_RXCOALESCEENABLE 1 + #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE) + #define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U) +@@ -1228,110 +4097,336 @@ + + #define A_TP_PARA_REG4 0x370 + ++#define S_HIGHSPEEDCFG 24 ++#define M_HIGHSPEEDCFG 0xff ++#define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG) ++#define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG) ++ ++#define S_NEWRENOCFG 16 ++#define M_NEWRENOCFG 0xff ++#define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG) ++#define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG) ++ ++#define S_TAHOECFG 8 ++#define M_TAHOECFG 0xff ++#define V_TAHOECFG(x) ((x) << S_TAHOECFG) ++#define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG) ++ ++#define S_RENOCFG 0 ++#define M_RENOCFG 0xff ++#define V_RENOCFG(x) ((x) << S_RENOCFG) ++#define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG) ++ + #define A_TP_PARA_REG5 0x374 ++ ++#define S_INDICATESIZE 16 ++#define M_INDICATESIZE 0xffff ++#define V_INDICATESIZE(x) ((x) << S_INDICATESIZE) ++#define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE) ++ ++#define S_SCHDENABLE 8 ++#define V_SCHDENABLE(x) ((x) << S_SCHDENABLE) ++#define F_SCHDENABLE V_SCHDENABLE(1U) + + #define S_RXDDPOFFINIT 3 + #define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT) + #define F_RXDDPOFFINIT V_RXDDPOFFINIT(1U) + ++#define S_ONFLYDDPENABLE 2 ++#define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE) ++#define F_ONFLYDDPENABLE V_ONFLYDDPENABLE(1U) ++ ++#define S_DACKTIMERSPIN 1 ++#define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN) ++#define F_DACKTIMERSPIN V_DACKTIMERSPIN(1U) ++ ++#define S_PUSHTIMERENABLE 0 ++#define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE) ++#define F_PUSHTIMERENABLE V_PUSHTIMERENABLE(1U) ++ + #define A_TP_PARA_REG6 0x378 ++ ++#define S_TXPDUSIZEADJ 16 ++#define M_TXPDUSIZEADJ 0xff ++#define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ) ++#define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ) ++ ++#define S_ENABLEDEFERACK 12 ++#define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK) ++#define F_ENABLEDEFERACK V_ENABLEDEFERACK(1U) ++ ++#define S_ENABLEESND 11 ++#define V_ENABLEESND(x) ((x) << S_ENABLEESND) ++#define F_ENABLEESND V_ENABLEESND(1U) ++ ++#define S_ENABLECSND 10 ++#define V_ENABLECSND(x) ((x) << S_ENABLECSND) ++#define F_ENABLECSND V_ENABLECSND(1U) ++ ++#define S_ENABLEPDUE 9 ++#define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE) ++#define F_ENABLEPDUE V_ENABLEPDUE(1U) ++ ++#define S_ENABLEPDUC 8 ++#define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC) ++#define F_ENABLEPDUC V_ENABLEPDUC(1U) ++ ++#define S_ENABLEBUFI 7 ++#define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI) ++#define F_ENABLEBUFI V_ENABLEBUFI(1U) ++ ++#define S_ENABLEBUFE 6 ++#define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE) ++#define F_ENABLEBUFE V_ENABLEBUFE(1U) ++ ++#define S_ENABLEDEFER 5 ++#define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER) ++#define F_ENABLEDEFER V_ENABLEDEFER(1U) ++ ++#define S_ENABLECLEARRXMTOOS 4 ++#define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS) ++#define F_ENABLECLEARRXMTOOS V_ENABLECLEARRXMTOOS(1U) ++ ++#define S_DISABLEPDUCNG 3 ++#define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG) ++#define F_DISABLEPDUCNG V_DISABLEPDUCNG(1U) ++ ++#define S_DISABLEPDUTIMEOUT 2 ++#define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT) ++#define F_DISABLEPDUTIMEOUT V_DISABLEPDUTIMEOUT(1U) ++ ++#define S_DISABLEPDURXMT 1 ++#define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT) ++#define F_DISABLEPDURXMT V_DISABLEPDURXMT(1U) ++ ++#define S_DISABLEPDUXMT 0 ++#define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT) ++#define F_DISABLEPDUXMT V_DISABLEPDUXMT(1U) ++ ++#define S_ENABLEEPDU 14 ++#define V_ENABLEEPDU(x) ((x) << S_ENABLEEPDU) ++#define F_ENABLEEPDU V_ENABLEEPDU(1U) + + #define S_T3A_ENABLEESND 13 + #define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND) + #define F_T3A_ENABLEESND V_T3A_ENABLEESND(1U) + +-#define S_ENABLEESND 11 +-#define V_ENABLEESND(x) ((x) << S_ENABLEESND) +-#define F_ENABLEESND V_ENABLEESND(1U) ++#define S_T3A_ENABLECSND 12 ++#define V_T3A_ENABLECSND(x) ((x) << S_T3A_ENABLECSND) ++#define F_T3A_ENABLECSND V_T3A_ENABLECSND(1U) ++ ++#define S_T3A_ENABLEDEFERACK 9 ++#define V_T3A_ENABLEDEFERACK(x) ((x) << S_T3A_ENABLEDEFERACK) ++#define F_T3A_ENABLEDEFERACK V_T3A_ENABLEDEFERACK(1U) ++ ++#define S_ENABLEPDUI 7 ++#define V_ENABLEPDUI(x) ((x) << S_ENABLEPDUI) ++#define F_ENABLEPDUI V_ENABLEPDUI(1U) ++ ++#define S_T3A_ENABLEPDUE 6 ++#define V_T3A_ENABLEPDUE(x) ((x) << S_T3A_ENABLEPDUE) ++#define F_T3A_ENABLEPDUE V_T3A_ENABLEPDUE(1U) + + #define A_TP_PARA_REG7 0x37c + + #define S_PMMAXXFERLEN1 16 + #define M_PMMAXXFERLEN1 0xffff + #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1) ++#define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1) + + #define S_PMMAXXFERLEN0 0 + #define M_PMMAXXFERLEN0 0xffff + #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0) ++#define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0) + + #define A_TP_TIMER_RESOLUTION 0x390 + + #define S_TIMERRESOLUTION 16 + #define M_TIMERRESOLUTION 0xff + #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION) ++#define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION) + + #define S_TIMESTAMPRESOLUTION 8 + #define M_TIMESTAMPRESOLUTION 0xff + #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION) ++#define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION) + + #define S_DELAYEDACKRESOLUTION 0 + #define M_DELAYEDACKRESOLUTION 0xff + #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION) ++#define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION) + + #define A_TP_MSL 0x394 + ++#define S_MSL 0 ++#define M_MSL 0x3fffffff ++#define V_MSL(x) ((x) << S_MSL) ++#define G_MSL(x) (((x) >> S_MSL) & M_MSL) ++ + #define A_TP_RXT_MIN 0x398 + ++#define S_RXTMIN 0 ++#define M_RXTMIN 0x3fffffff ++#define V_RXTMIN(x) ((x) << S_RXTMIN) ++#define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN) ++ + #define A_TP_RXT_MAX 0x39c + ++#define S_RXTMAX 0 ++#define M_RXTMAX 0x3fffffff ++#define V_RXTMAX(x) ((x) << S_RXTMAX) ++#define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX) ++ + #define A_TP_PERS_MIN 0x3a0 + ++#define S_PERSMIN 0 ++#define M_PERSMIN 0x3fffffff ++#define V_PERSMIN(x) ((x) << S_PERSMIN) ++#define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN) ++ + #define A_TP_PERS_MAX 0x3a4 + ++#define S_PERSMAX 0 ++#define M_PERSMAX 0x3fffffff ++#define V_PERSMAX(x) ((x) << S_PERSMAX) ++#define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX) ++ + #define A_TP_KEEP_IDLE 0x3a8 + ++#define S_KEEPALIVEIDLE 0 ++#define M_KEEPALIVEIDLE 0x3fffffff ++#define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE) ++#define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE) ++ + #define A_TP_KEEP_INTVL 0x3ac + ++#define S_KEEPALIVEINTVL 0 ++#define M_KEEPALIVEINTVL 0x3fffffff ++#define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL) ++#define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL) ++ + #define A_TP_INIT_SRTT 0x3b0 + ++#define S_INITSRTT 0 ++#define M_INITSRTT 0xffff ++#define V_INITSRTT(x) ((x) << S_INITSRTT) ++#define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT) ++ + #define A_TP_DACK_TIMER 0x3b4 + ++#define S_DACKTIME 0 ++#define M_DACKTIME 0xfff ++#define V_DACKTIME(x) ((x) << S_DACKTIME) ++#define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME) ++ + #define A_TP_FINWAIT2_TIMER 0x3b8 + ++#define S_FINWAIT2TIME 0 ++#define M_FINWAIT2TIME 0x3fffffff ++#define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME) ++#define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME) ++ ++#define A_TP_FAST_FINWAIT2_TIMER 0x3bc ++ ++#define S_FASTFINWAIT2TIME 0 ++#define M_FASTFINWAIT2TIME 0x3fffffff ++#define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME) ++#define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME) ++ + #define A_TP_SHIFT_CNT 0x3c0 + + #define S_SYNSHIFTMAX 24 +- + #define M_SYNSHIFTMAX 0xff +- + #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX) ++#define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX) + + #define S_RXTSHIFTMAXR1 20 +- + #define M_RXTSHIFTMAXR1 0xf +- + #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1) ++#define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1) + + #define S_RXTSHIFTMAXR2 16 +- + #define M_RXTSHIFTMAXR2 0xf +- + #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2) ++#define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2) + + #define S_PERSHIFTBACKOFFMAX 12 + #define M_PERSHIFTBACKOFFMAX 0xf + #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX) ++#define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX) + + #define S_PERSHIFTMAX 8 + #define M_PERSHIFTMAX 0xf + #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX) ++#define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX) + + #define S_KEEPALIVEMAX 0 +- + #define M_KEEPALIVEMAX 0xff +- + #define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX) +- ++#define G_KEEPALIVEMAX(x) (((x) >> S_KEEPALIVEMAX) & M_KEEPALIVEMAX) ++ ++#define A_TP_TIME_HI 0x3c8 ++#define A_TP_TIME_LO 0x3cc + #define A_TP_MTU_PORT_TABLE 0x3d0 + ++#define S_PORT1MTUVALUE 16 ++#define M_PORT1MTUVALUE 0xffff ++#define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE) ++#define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE) ++ ++#define S_PORT0MTUVALUE 0 ++#define M_PORT0MTUVALUE 0xffff ++#define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE) ++#define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE) ++ ++#define A_TP_ULP_TABLE 0x3d4 ++ ++#define S_ULPTYPE7FIELD 28 ++#define M_ULPTYPE7FIELD 0xf ++#define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD) ++#define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD) ++ ++#define S_ULPTYPE6FIELD 24 ++#define M_ULPTYPE6FIELD 0xf ++#define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD) ++#define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD) ++ ++#define S_ULPTYPE5FIELD 20 ++#define M_ULPTYPE5FIELD 0xf ++#define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD) ++#define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD) ++ ++#define S_ULPTYPE4FIELD 16 ++#define M_ULPTYPE4FIELD 0xf ++#define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD) ++#define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD) ++ ++#define S_ULPTYPE3FIELD 12 ++#define M_ULPTYPE3FIELD 0xf ++#define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD) ++#define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD) ++ ++#define S_ULPTYPE2FIELD 8 ++#define M_ULPTYPE2FIELD 0xf ++#define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD) ++#define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD) ++ ++#define S_ULPTYPE1FIELD 4 ++#define M_ULPTYPE1FIELD 0xf ++#define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD) ++#define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD) ++ ++#define S_ULPTYPE0FIELD 0 ++#define M_ULPTYPE0FIELD 0xf ++#define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD) ++#define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD) ++ ++#define A_TP_PACE_TABLE 0x3d8 + #define A_TP_CCTRL_TABLE 0x3dc +- ++#define A_TP_TOS_TABLE 0x3e0 + #define A_TP_MTU_TABLE 0x3e4 +- + #define A_TP_RSS_MAP_TABLE 0x3e8 +- + #define A_TP_RSS_LKP_TABLE 0x3ec +- + #define A_TP_RSS_CONFIG 0x3f0 + + #define S_TNL4TUPEN 29 +@@ -1354,6 +4449,38 @@ + #define V_TNLLKPEN(x) ((x) << S_TNLLKPEN) + #define F_TNLLKPEN V_TNLLKPEN(1U) + ++#define S_OFD4TUPEN 21 ++#define V_OFD4TUPEN(x) ((x) << S_OFD4TUPEN) ++#define F_OFD4TUPEN V_OFD4TUPEN(1U) ++ ++#define S_OFD2TUPEN 20 ++#define V_OFD2TUPEN(x) ((x) << S_OFD2TUPEN) ++#define F_OFD2TUPEN V_OFD2TUPEN(1U) ++ ++#define S_OFDMAPEN 17 ++#define V_OFDMAPEN(x) ((x) << S_OFDMAPEN) ++#define F_OFDMAPEN V_OFDMAPEN(1U) ++ ++#define S_OFDLKPEN 16 ++#define V_OFDLKPEN(x) ((x) << S_OFDLKPEN) ++#define F_OFDLKPEN V_OFDLKPEN(1U) ++ ++#define S_SYN4TUPEN 13 ++#define V_SYN4TUPEN(x) ((x) << S_SYN4TUPEN) ++#define F_SYN4TUPEN V_SYN4TUPEN(1U) ++ ++#define S_SYN2TUPEN 12 ++#define V_SYN2TUPEN(x) ((x) << S_SYN2TUPEN) ++#define F_SYN2TUPEN V_SYN2TUPEN(1U) ++ ++#define S_SYNMAPEN 9 ++#define V_SYNMAPEN(x) ((x) << S_SYNMAPEN) ++#define F_SYNMAPEN V_SYNMAPEN(1U) ++ ++#define S_SYNLKPEN 8 ++#define V_SYNLKPEN(x) ((x) << S_SYNLKPEN) ++#define F_SYNLKPEN V_SYNLKPEN(1U) ++ + #define S_RRCPLMAPEN 7 + #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN) + #define F_RRCPLMAPEN V_RRCPLMAPEN(1U) +@@ -1361,6 +4488,7 @@ + #define S_RRCPLCPUSIZE 4 + #define M_RRCPLCPUSIZE 0x7 + #define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE) ++#define G_RRCPLCPUSIZE(x) (((x) >> S_RRCPLCPUSIZE) & M_RRCPLCPUSIZE) + + #define S_RQFEEDBACKENABLE 3 + #define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE) +@@ -1370,34 +4498,179 @@ + #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ) + #define F_HASHTOEPLITZ V_HASHTOEPLITZ(1U) + ++#define S_HASHSAVE 1 ++#define V_HASHSAVE(x) ((x) << S_HASHSAVE) ++#define F_HASHSAVE V_HASHSAVE(1U) ++ + #define S_DISABLE 0 +- ++#define V_DISABLE(x) ((x) << S_DISABLE) ++#define F_DISABLE V_DISABLE(1U) ++ ++#define A_TP_RSS_CONFIG_TNL 0x3f4 ++ ++#define S_MASKSIZE 28 ++#define M_MASKSIZE 0x7 ++#define V_MASKSIZE(x) ((x) << S_MASKSIZE) ++#define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE) ++ ++#define S_DEFAULTCPUBASE 22 ++#define M_DEFAULTCPUBASE 0x3f ++#define V_DEFAULTCPUBASE(x) ((x) << S_DEFAULTCPUBASE) ++#define G_DEFAULTCPUBASE(x) (((x) >> S_DEFAULTCPUBASE) & M_DEFAULTCPUBASE) ++ ++#define S_DEFAULTCPU 16 ++#define M_DEFAULTCPU 0x3f ++#define V_DEFAULTCPU(x) ((x) << S_DEFAULTCPU) ++#define G_DEFAULTCPU(x) (((x) >> S_DEFAULTCPU) & M_DEFAULTCPU) ++ ++#define S_DEFAULTQUEUE 0 ++#define M_DEFAULTQUEUE 0xffff ++#define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE) ++#define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE) ++ ++#define A_TP_RSS_CONFIG_OFD 0x3f8 ++#define A_TP_RSS_CONFIG_SYN 0x3fc ++#define A_TP_RSS_SECRET_KEY0 0x400 ++#define A_TP_RSS_SECRET_KEY1 0x404 ++#define A_TP_RSS_SECRET_KEY2 0x408 ++#define A_TP_RSS_SECRET_KEY3 0x40c + #define A_TP_TM_PIO_ADDR 0x418 +- + #define A_TP_TM_PIO_DATA 0x41c +- + #define A_TP_TX_MOD_QUE_TABLE 0x420 +- + #define A_TP_TX_RESOURCE_LIMIT 0x424 + ++#define S_TX_RESOURCE_LIMIT_CH1_PC 24 ++#define M_TX_RESOURCE_LIMIT_CH1_PC 0xff ++#define V_TX_RESOURCE_LIMIT_CH1_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_PC) ++#define G_TX_RESOURCE_LIMIT_CH1_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_PC) & M_TX_RESOURCE_LIMIT_CH1_PC) ++ ++#define S_TX_RESOURCE_LIMIT_CH1_NON_PC 16 ++#define M_TX_RESOURCE_LIMIT_CH1_NON_PC 0xff ++#define V_TX_RESOURCE_LIMIT_CH1_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_NON_PC) ++#define G_TX_RESOURCE_LIMIT_CH1_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_NON_PC) & M_TX_RESOURCE_LIMIT_CH1_NON_PC) ++ ++#define S_TX_RESOURCE_LIMIT_CH0_PC 8 ++#define M_TX_RESOURCE_LIMIT_CH0_PC 0xff ++#define V_TX_RESOURCE_LIMIT_CH0_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_PC) ++#define G_TX_RESOURCE_LIMIT_CH0_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_PC) & M_TX_RESOURCE_LIMIT_CH0_PC) ++ ++#define S_TX_RESOURCE_LIMIT_CH0_NON_PC 0 ++#define M_TX_RESOURCE_LIMIT_CH0_NON_PC 0xff ++#define V_TX_RESOURCE_LIMIT_CH0_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_NON_PC) ++#define G_TX_RESOURCE_LIMIT_CH0_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_NON_PC) & M_TX_RESOURCE_LIMIT_CH0_NON_PC) ++ + #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428 ++ ++#define S_RX_MOD_WEIGHT 24 ++#define M_RX_MOD_WEIGHT 0xff ++#define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT) ++#define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT) ++ ++#define S_TX_MOD_WEIGHT 16 ++#define M_TX_MOD_WEIGHT 0xff ++#define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT) ++#define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT) ++ ++#define S_TX_MOD_TIMER_MODE 8 ++#define M_TX_MOD_TIMER_MODE 0xff ++#define V_TX_MOD_TIMER_MODE(x) ((x) << S_TX_MOD_TIMER_MODE) ++#define G_TX_MOD_TIMER_MODE(x) (((x) >> S_TX_MOD_TIMER_MODE) & M_TX_MOD_TIMER_MODE) + + #define S_TX_MOD_QUEUE_REQ_MAP 0 + #define M_TX_MOD_QUEUE_REQ_MAP 0xff + #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP) ++#define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP) + + #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c + ++#define S_TP_TX_MODQ_WGHT7 24 ++#define M_TP_TX_MODQ_WGHT7 0xff ++#define V_TP_TX_MODQ_WGHT7(x) ((x) << S_TP_TX_MODQ_WGHT7) ++#define G_TP_TX_MODQ_WGHT7(x) (((x) >> S_TP_TX_MODQ_WGHT7) & M_TP_TX_MODQ_WGHT7) ++ ++#define S_TP_TX_MODQ_WGHT6 16 ++#define M_TP_TX_MODQ_WGHT6 0xff ++#define V_TP_TX_MODQ_WGHT6(x) ((x) << S_TP_TX_MODQ_WGHT6) ++#define G_TP_TX_MODQ_WGHT6(x) (((x) >> S_TP_TX_MODQ_WGHT6) & M_TP_TX_MODQ_WGHT6) ++ ++#define S_TP_TX_MODQ_WGHT5 8 ++#define M_TP_TX_MODQ_WGHT5 0xff ++#define V_TP_TX_MODQ_WGHT5(x) ((x) << S_TP_TX_MODQ_WGHT5) ++#define G_TP_TX_MODQ_WGHT5(x) (((x) >> S_TP_TX_MODQ_WGHT5) & M_TP_TX_MODQ_WGHT5) ++ ++#define S_TP_TX_MODQ_WGHT4 0 ++#define M_TP_TX_MODQ_WGHT4 0xff ++#define V_TP_TX_MODQ_WGHT4(x) ((x) << S_TP_TX_MODQ_WGHT4) ++#define G_TP_TX_MODQ_WGHT4(x) (((x) >> S_TP_TX_MODQ_WGHT4) & M_TP_TX_MODQ_WGHT4) ++ + #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430 + ++#define S_TP_TX_MODQ_WGHT3 24 ++#define M_TP_TX_MODQ_WGHT3 0xff ++#define V_TP_TX_MODQ_WGHT3(x) ((x) << S_TP_TX_MODQ_WGHT3) ++#define G_TP_TX_MODQ_WGHT3(x) (((x) >> S_TP_TX_MODQ_WGHT3) & M_TP_TX_MODQ_WGHT3) ++ ++#define S_TP_TX_MODQ_WGHT2 16 ++#define M_TP_TX_MODQ_WGHT2 0xff ++#define V_TP_TX_MODQ_WGHT2(x) ((x) << S_TP_TX_MODQ_WGHT2) ++#define G_TP_TX_MODQ_WGHT2(x) (((x) >> S_TP_TX_MODQ_WGHT2) & M_TP_TX_MODQ_WGHT2) ++ ++#define S_TP_TX_MODQ_WGHT1 8 ++#define M_TP_TX_MODQ_WGHT1 0xff ++#define V_TP_TX_MODQ_WGHT1(x) ((x) << S_TP_TX_MODQ_WGHT1) ++#define G_TP_TX_MODQ_WGHT1(x) (((x) >> S_TP_TX_MODQ_WGHT1) & M_TP_TX_MODQ_WGHT1) ++ ++#define S_TP_TX_MODQ_WGHT0 0 ++#define M_TP_TX_MODQ_WGHT0 0xff ++#define V_TP_TX_MODQ_WGHT0(x) ((x) << S_TP_TX_MODQ_WGHT0) ++#define G_TP_TX_MODQ_WGHT0(x) (((x) >> S_TP_TX_MODQ_WGHT0) & M_TP_TX_MODQ_WGHT0) ++ + #define A_TP_MOD_CHANNEL_WEIGHT 0x434 + ++#define S_RX_MOD_CHANNEL_WEIGHT1 24 ++#define M_RX_MOD_CHANNEL_WEIGHT1 0xff ++#define V_RX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT1) ++#define G_RX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT1) & M_RX_MOD_CHANNEL_WEIGHT1) ++ ++#define S_RX_MOD_CHANNEL_WEIGHT0 16 ++#define M_RX_MOD_CHANNEL_WEIGHT0 0xff ++#define V_RX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT0) ++#define G_RX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT0) & M_RX_MOD_CHANNEL_WEIGHT0) ++ ++#define S_TX_MOD_CHANNEL_WEIGHT1 8 ++#define M_TX_MOD_CHANNEL_WEIGHT1 0xff ++#define V_TX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT1) ++#define G_TX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT1) & M_TX_MOD_CHANNEL_WEIGHT1) ++ ++#define S_TX_MOD_CHANNEL_WEIGHT0 0 ++#define M_TX_MOD_CHANNEL_WEIGHT0 0xff ++#define V_TX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT0) ++#define G_TX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT0) & M_TX_MOD_CHANNEL_WEIGHT0) ++ + #define A_TP_MOD_RATE_LIMIT 0x438 + ++#define S_RX_MOD_RATE_LIMIT_INC 24 ++#define M_RX_MOD_RATE_LIMIT_INC 0xff ++#define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC) ++#define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC) ++ ++#define S_RX_MOD_RATE_LIMIT_TICK 16 ++#define M_RX_MOD_RATE_LIMIT_TICK 0xff ++#define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK) ++#define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK) ++ ++#define S_TX_MOD_RATE_LIMIT_INC 8 ++#define M_TX_MOD_RATE_LIMIT_INC 0xff ++#define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC) ++#define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC) ++ ++#define S_TX_MOD_RATE_LIMIT_TICK 0 ++#define M_TX_MOD_RATE_LIMIT_TICK 0xff ++#define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK) ++#define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK) ++ + #define A_TP_PIO_ADDR 0x440 +- + #define A_TP_PIO_DATA 0x444 +- + #define A_TP_RESET 0x44c + + #define S_FLSTINITENABLE 1 +@@ -1408,17 +4681,37 @@ + #define V_TPRESET(x) ((x) << S_TPRESET) + #define F_TPRESET V_TPRESET(1U) + ++#define A_TP_MIB_INDEX 0x450 ++#define A_TP_MIB_RDATA 0x454 ++#define A_TP_SYNC_TIME_HI 0x458 ++#define A_TP_SYNC_TIME_LO 0x45c + #define A_TP_CMM_MM_RX_FLST_BASE 0x460 + ++#define S_CMRXFLSTBASE 0 ++#define M_CMRXFLSTBASE 0xfffffff ++#define V_CMRXFLSTBASE(x) ((x) << S_CMRXFLSTBASE) ++#define G_CMRXFLSTBASE(x) (((x) >> S_CMRXFLSTBASE) & M_CMRXFLSTBASE) ++ + #define A_TP_CMM_MM_TX_FLST_BASE 0x464 + ++#define S_CMTXFLSTBASE 0 ++#define M_CMTXFLSTBASE 0xfffffff ++#define V_CMTXFLSTBASE(x) ((x) << S_CMTXFLSTBASE) ++#define G_CMTXFLSTBASE(x) (((x) >> S_CMTXFLSTBASE) & M_CMTXFLSTBASE) ++ + #define A_TP_CMM_MM_PS_FLST_BASE 0x468 + +-#define A_TP_MIB_INDEX 0x450 +- +-#define A_TP_MIB_RDATA 0x454 ++#define S_CMPSFLSTBASE 0 ++#define M_CMPSFLSTBASE 0xfffffff ++#define V_CMPSFLSTBASE(x) ((x) << S_CMPSFLSTBASE) ++#define G_CMPSFLSTBASE(x) (((x) >> S_CMPSFLSTBASE) & M_CMPSFLSTBASE) + + #define A_TP_CMM_MM_MAX_PSTRUCT 0x46c ++ ++#define S_CMMAXPSTRUCT 0 ++#define M_CMMAXPSTRUCT 0x1fffff ++#define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT) ++#define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT) + + #define A_TP_INT_ENABLE 0x470 + +@@ -1430,55 +4723,629 @@ + #define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY) + #define F_FLMRXFLSTEMPTY V_FLMRXFLSTEMPTY(1U) + ++#define S_FLMPERRSET 28 ++#define V_FLMPERRSET(x) ((x) << S_FLMPERRSET) ++#define F_FLMPERRSET V_FLMPERRSET(1U) ++ ++#define S_PROTOCOLSRAMPERR 27 ++#define V_PROTOCOLSRAMPERR(x) ((x) << S_PROTOCOLSRAMPERR) ++#define F_PROTOCOLSRAMPERR V_PROTOCOLSRAMPERR(1U) ++ + #define S_ARPLUTPERR 26 + #define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR) + #define F_ARPLUTPERR V_ARPLUTPERR(1U) + ++#define S_CMRCFOPPERR 25 ++#define V_CMRCFOPPERR(x) ((x) << S_CMRCFOPPERR) ++#define F_CMRCFOPPERR V_CMRCFOPPERR(1U) ++ + #define S_CMCACHEPERR 24 + #define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR) + #define F_CMCACHEPERR V_CMCACHEPERR(1U) + ++#define S_CMRCFDATAPERR 23 ++#define V_CMRCFDATAPERR(x) ((x) << S_CMRCFDATAPERR) ++#define F_CMRCFDATAPERR V_CMRCFDATAPERR(1U) ++ ++#define S_DBL2TLUTPERR 22 ++#define V_DBL2TLUTPERR(x) ((x) << S_DBL2TLUTPERR) ++#define F_DBL2TLUTPERR V_DBL2TLUTPERR(1U) ++ ++#define S_DBTXTIDPERR 21 ++#define V_DBTXTIDPERR(x) ((x) << S_DBTXTIDPERR) ++#define F_DBTXTIDPERR V_DBTXTIDPERR(1U) ++ ++#define S_DBEXTPERR 20 ++#define V_DBEXTPERR(x) ((x) << S_DBEXTPERR) ++#define F_DBEXTPERR V_DBEXTPERR(1U) ++ ++#define S_DBOPPERR 19 ++#define V_DBOPPERR(x) ((x) << S_DBOPPERR) ++#define F_DBOPPERR V_DBOPPERR(1U) ++ ++#define S_TMCACHEPERR 18 ++#define V_TMCACHEPERR(x) ((x) << S_TMCACHEPERR) ++#define F_TMCACHEPERR V_TMCACHEPERR(1U) ++ ++#define S_ETPOUTCPLFIFOPERR 17 ++#define V_ETPOUTCPLFIFOPERR(x) ((x) << S_ETPOUTCPLFIFOPERR) ++#define F_ETPOUTCPLFIFOPERR V_ETPOUTCPLFIFOPERR(1U) ++ ++#define S_ETPOUTTCPFIFOPERR 16 ++#define V_ETPOUTTCPFIFOPERR(x) ((x) << S_ETPOUTTCPFIFOPERR) ++#define F_ETPOUTTCPFIFOPERR V_ETPOUTTCPFIFOPERR(1U) ++ ++#define S_ETPOUTIPFIFOPERR 15 ++#define V_ETPOUTIPFIFOPERR(x) ((x) << S_ETPOUTIPFIFOPERR) ++#define F_ETPOUTIPFIFOPERR V_ETPOUTIPFIFOPERR(1U) ++ ++#define S_ETPOUTETHFIFOPERR 14 ++#define V_ETPOUTETHFIFOPERR(x) ((x) << S_ETPOUTETHFIFOPERR) ++#define F_ETPOUTETHFIFOPERR V_ETPOUTETHFIFOPERR(1U) ++ ++#define S_ETPINCPLFIFOPERR 13 ++#define V_ETPINCPLFIFOPERR(x) ((x) << S_ETPINCPLFIFOPERR) ++#define F_ETPINCPLFIFOPERR V_ETPINCPLFIFOPERR(1U) ++ ++#define S_ETPINTCPOPTFIFOPERR 12 ++#define V_ETPINTCPOPTFIFOPERR(x) ((x) << S_ETPINTCPOPTFIFOPERR) ++#define F_ETPINTCPOPTFIFOPERR V_ETPINTCPOPTFIFOPERR(1U) ++ ++#define S_ETPINTCPFIFOPERR 11 ++#define V_ETPINTCPFIFOPERR(x) ((x) << S_ETPINTCPFIFOPERR) ++#define F_ETPINTCPFIFOPERR V_ETPINTCPFIFOPERR(1U) ++ ++#define S_ETPINIPFIFOPERR 10 ++#define V_ETPINIPFIFOPERR(x) ((x) << S_ETPINIPFIFOPERR) ++#define F_ETPINIPFIFOPERR V_ETPINIPFIFOPERR(1U) ++ ++#define S_ETPINETHFIFOPERR 9 ++#define V_ETPINETHFIFOPERR(x) ((x) << S_ETPINETHFIFOPERR) ++#define F_ETPINETHFIFOPERR V_ETPINETHFIFOPERR(1U) ++ ++#define S_CTPOUTCPLFIFOPERR 8 ++#define V_CTPOUTCPLFIFOPERR(x) ((x) << S_CTPOUTCPLFIFOPERR) ++#define F_CTPOUTCPLFIFOPERR V_CTPOUTCPLFIFOPERR(1U) ++ ++#define S_CTPOUTTCPFIFOPERR 7 ++#define V_CTPOUTTCPFIFOPERR(x) ((x) << S_CTPOUTTCPFIFOPERR) ++#define F_CTPOUTTCPFIFOPERR V_CTPOUTTCPFIFOPERR(1U) ++ ++#define S_CTPOUTIPFIFOPERR 6 ++#define V_CTPOUTIPFIFOPERR(x) ((x) << S_CTPOUTIPFIFOPERR) ++#define F_CTPOUTIPFIFOPERR V_CTPOUTIPFIFOPERR(1U) ++ ++#define S_CTPOUTETHFIFOPERR 5 ++#define V_CTPOUTETHFIFOPERR(x) ((x) << S_CTPOUTETHFIFOPERR) ++#define F_CTPOUTETHFIFOPERR V_CTPOUTETHFIFOPERR(1U) ++ ++#define S_CTPINCPLFIFOPERR 4 ++#define V_CTPINCPLFIFOPERR(x) ((x) << S_CTPINCPLFIFOPERR) ++#define F_CTPINCPLFIFOPERR V_CTPINCPLFIFOPERR(1U) ++ ++#define S_CTPINTCPOPFIFOPERR 3 ++#define V_CTPINTCPOPFIFOPERR(x) ((x) << S_CTPINTCPOPFIFOPERR) ++#define F_CTPINTCPOPFIFOPERR V_CTPINTCPOPFIFOPERR(1U) ++ ++#define S_CTPINTCPFIFOPERR 2 ++#define V_CTPINTCPFIFOPERR(x) ((x) << S_CTPINTCPFIFOPERR) ++#define F_CTPINTCPFIFOPERR V_CTPINTCPFIFOPERR(1U) ++ ++#define S_CTPINIPFIFOPERR 1 ++#define V_CTPINIPFIFOPERR(x) ((x) << S_CTPINIPFIFOPERR) ++#define F_CTPINIPFIFOPERR V_CTPINIPFIFOPERR(1U) ++ ++#define S_CTPINETHFIFOPERR 0 ++#define V_CTPINETHFIFOPERR(x) ((x) << S_CTPINETHFIFOPERR) ++#define F_CTPINETHFIFOPERR V_CTPINETHFIFOPERR(1U) ++ + #define A_TP_INT_CAUSE 0x474 +- +-#define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8 +- +-#define A_TP_TX_DROP_CFG_CH0 0x12b +- +-#define A_TP_TX_DROP_MODE 0x12f +- +-#define A_TP_EGRESS_CONFIG 0x145 +- +-#define S_REWRITEFORCETOSIZE 0 +-#define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE) +-#define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U) +- +-#define A_TP_TX_TRC_KEY0 0x20 +- +-#define A_TP_RX_TRC_KEY0 0x120 +- +-#define A_TP_TX_DROP_CNT_CH0 0x12d +- +-#define S_TXDROPCNTCH0RCVD 0 +-#define M_TXDROPCNTCH0RCVD 0xffff +-#define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD) +-#define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & \ +- M_TXDROPCNTCH0RCVD) ++#define A_TP_FLM_FREE_PS_CNT 0x480 ++ ++#define S_FREEPSTRUCTCOUNT 0 ++#define M_FREEPSTRUCTCOUNT 0x1fffff ++#define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT) ++#define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT) ++ ++#define A_TP_FLM_FREE_RX_CNT 0x484 ++ ++#define S_FREERXPAGECOUNT 0 ++#define M_FREERXPAGECOUNT 0x1fffff ++#define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT) ++#define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT) ++ ++#define A_TP_FLM_FREE_TX_CNT 0x488 ++ ++#define S_FREETXPAGECOUNT 0 ++#define M_FREETXPAGECOUNT 0x1fffff ++#define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT) ++#define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT) ++ ++#define A_TP_TM_HEAP_PUSH_CNT 0x48c ++#define A_TP_TM_HEAP_POP_CNT 0x490 ++#define A_TP_TM_DACK_PUSH_CNT 0x494 ++#define A_TP_TM_DACK_POP_CNT 0x498 ++#define A_TP_TM_MOD_PUSH_CNT 0x49c ++#define A_TP_MOD_POP_CNT 0x4a0 ++#define A_TP_TIMER_SEPARATOR 0x4a4 ++#define A_TP_DEBUG_SEL 0x4a8 ++#define A_TP_DEBUG_FLAGS 0x4ac ++ ++#define S_RXTIMERDACKFIRST 26 ++#define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST) ++#define F_RXTIMERDACKFIRST V_RXTIMERDACKFIRST(1U) ++ ++#define S_RXTIMERDACK 25 ++#define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK) ++#define F_RXTIMERDACK V_RXTIMERDACK(1U) ++ ++#define S_RXTIMERHEARTBEAT 24 ++#define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT) ++#define F_RXTIMERHEARTBEAT V_RXTIMERHEARTBEAT(1U) ++ ++#define S_RXPAWSDROP 23 ++#define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP) ++#define F_RXPAWSDROP V_RXPAWSDROP(1U) ++ ++#define S_RXURGDATADROP 22 ++#define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP) ++#define F_RXURGDATADROP V_RXURGDATADROP(1U) ++ ++#define S_RXFUTUREDATA 21 ++#define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA) ++#define F_RXFUTUREDATA V_RXFUTUREDATA(1U) ++ ++#define S_RXRCVRXMDATA 20 ++#define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA) ++#define F_RXRCVRXMDATA V_RXRCVRXMDATA(1U) ++ ++#define S_RXRCVOOODATAFIN 19 ++#define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN) ++#define F_RXRCVOOODATAFIN V_RXRCVOOODATAFIN(1U) ++ ++#define S_RXRCVOOODATA 18 ++#define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA) ++#define F_RXRCVOOODATA V_RXRCVOOODATA(1U) ++ ++#define S_RXRCVWNDZERO 17 ++#define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO) ++#define F_RXRCVWNDZERO V_RXRCVWNDZERO(1U) ++ ++#define S_RXRCVWNDLTMSS 16 ++#define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS) ++#define F_RXRCVWNDLTMSS V_RXRCVWNDLTMSS(1U) ++ ++#define S_TXDUPACKINC 11 ++#define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC) ++#define F_TXDUPACKINC V_TXDUPACKINC(1U) ++ ++#define S_TXRXMURG 10 ++#define V_TXRXMURG(x) ((x) << S_TXRXMURG) ++#define F_TXRXMURG V_TXRXMURG(1U) ++ ++#define S_TXRXMFIN 9 ++#define V_TXRXMFIN(x) ((x) << S_TXRXMFIN) ++#define F_TXRXMFIN V_TXRXMFIN(1U) ++ ++#define S_TXRXMSYN 8 ++#define V_TXRXMSYN(x) ((x) << S_TXRXMSYN) ++#define F_TXRXMSYN V_TXRXMSYN(1U) ++ ++#define S_TXRXMNEWRENO 7 ++#define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO) ++#define F_TXRXMNEWRENO V_TXRXMNEWRENO(1U) ++ ++#define S_TXRXMFAST 6 ++#define V_TXRXMFAST(x) ((x) << S_TXRXMFAST) ++#define F_TXRXMFAST V_TXRXMFAST(1U) ++ ++#define S_TXRXMTIMER 5 ++#define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER) ++#define F_TXRXMTIMER V_TXRXMTIMER(1U) ++ ++#define S_TXRXMTIMERKEEPALIVE 4 ++#define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE) ++#define F_TXRXMTIMERKEEPALIVE V_TXRXMTIMERKEEPALIVE(1U) ++ ++#define S_TXRXMTIMERPERSIST 3 ++#define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST) ++#define F_TXRXMTIMERPERSIST V_TXRXMTIMERPERSIST(1U) ++ ++#define S_TXRCVADVSHRUNK 2 ++#define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK) ++#define F_TXRCVADVSHRUNK V_TXRCVADVSHRUNK(1U) ++ ++#define S_TXRCVADVZERO 1 ++#define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO) ++#define F_TXRCVADVZERO V_TXRCVADVZERO(1U) ++ ++#define S_TXRCVADVLTMSS 0 ++#define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS) ++#define F_TXRCVADVLTMSS V_TXRCVADVLTMSS(1U) ++ ++#define S_RXDEBUGFLAGS 16 ++#define M_RXDEBUGFLAGS 0xffff ++#define V_RXDEBUGFLAGS(x) ((x) << S_RXDEBUGFLAGS) ++#define G_RXDEBUGFLAGS(x) (((x) >> S_RXDEBUGFLAGS) & M_RXDEBUGFLAGS) ++ ++#define S_TXDEBUGFLAGS 0 ++#define M_TXDEBUGFLAGS 0xffff ++#define V_TXDEBUGFLAGS(x) ((x) << S_TXDEBUGFLAGS) ++#define G_TXDEBUGFLAGS(x) (((x) >> S_TXDEBUGFLAGS) & M_TXDEBUGFLAGS) + + #define A_TP_PROXY_FLOW_CNTL 0x4b0 +- ++#define A_TP_CM_FLOW_CNTL_MODE 0x4b0 ++ ++#define S_CMFLOWCACHEDISABLE 0 ++#define V_CMFLOWCACHEDISABLE(x) ((x) << S_CMFLOWCACHEDISABLE) ++#define F_CMFLOWCACHEDISABLE V_CMFLOWCACHEDISABLE(1U) ++ ++#define A_TP_PC_CONGESTION_CNTL 0x4b4 ++ ++#define S_EDROPTUNNEL 19 ++#define V_EDROPTUNNEL(x) ((x) << S_EDROPTUNNEL) ++#define F_EDROPTUNNEL V_EDROPTUNNEL(1U) ++ ++#define S_CDROPTUNNEL 18 ++#define V_CDROPTUNNEL(x) ((x) << S_CDROPTUNNEL) ++#define F_CDROPTUNNEL V_CDROPTUNNEL(1U) ++ ++#define S_ETHRESHOLD 12 ++#define M_ETHRESHOLD 0x3f ++#define V_ETHRESHOLD(x) ((x) << S_ETHRESHOLD) ++#define G_ETHRESHOLD(x) (((x) >> S_ETHRESHOLD) & M_ETHRESHOLD) ++ ++#define S_CTHRESHOLD 6 ++#define M_CTHRESHOLD 0x3f ++#define V_CTHRESHOLD(x) ((x) << S_CTHRESHOLD) ++#define G_CTHRESHOLD(x) (((x) >> S_CTHRESHOLD) & M_CTHRESHOLD) ++ ++#define S_TXTHRESHOLD 0 ++#define M_TXTHRESHOLD 0x3f ++#define V_TXTHRESHOLD(x) ((x) << S_TXTHRESHOLD) ++#define G_TXTHRESHOLD(x) (((x) >> S_TXTHRESHOLD) & M_TXTHRESHOLD) ++ ++#define A_TP_TX_DROP_COUNT 0x4bc ++#define A_TP_CLEAR_DEBUG 0x4c0 ++ ++#define S_CLRDEBUG 0 ++#define V_CLRDEBUG(x) ((x) << S_CLRDEBUG) ++#define F_CLRDEBUG V_CLRDEBUG(1U) ++ ++#define A_TP_DEBUG_VEC 0x4c4 ++#define A_TP_DEBUG_VEC2 0x4c8 ++#define A_TP_DEBUG_REG_SEL 0x4cc ++#define A_TP_DEBUG 0x4d0 ++#define A_TP_DBG_LA_CONFIG 0x4d4 ++#define A_TP_DBG_LA_DATAH 0x4d8 ++#define A_TP_DBG_LA_DATAL 0x4dc + #define A_TP_EMBED_OP_FIELD0 0x4e8 + #define A_TP_EMBED_OP_FIELD1 0x4ec + #define A_TP_EMBED_OP_FIELD2 0x4f0 + #define A_TP_EMBED_OP_FIELD3 0x4f4 + #define A_TP_EMBED_OP_FIELD4 0x4f8 + #define A_TP_EMBED_OP_FIELD5 0x4fc ++#define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0 ++#define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1 ++#define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2 ++#define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3 ++#define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4 ++#define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5 ++#define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6 ++#define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7 ++#define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8 ++#define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9 ++#define A_TP_TX_TRC_KEY0 0x20 ++#define A_TP_TX_TRC_MASK0 0x21 ++#define A_TP_TX_TRC_KEY1 0x22 ++#define A_TP_TX_TRC_MASK1 0x23 ++#define A_TP_TX_TRC_KEY2 0x24 ++#define A_TP_TX_TRC_MASK2 0x25 ++#define A_TP_TX_TRC_KEY3 0x26 ++#define A_TP_TX_TRC_MASK3 0x27 ++#define A_TP_IPMI_CFG1 0x28 ++ ++#define S_VLANENABLE 31 ++#define V_VLANENABLE(x) ((x) << S_VLANENABLE) ++#define F_VLANENABLE V_VLANENABLE(1U) ++ ++#define S_PRIMARYPORTENABLE 30 ++#define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE) ++#define F_PRIMARYPORTENABLE V_PRIMARYPORTENABLE(1U) ++ ++#define S_SECUREPORTENABLE 29 ++#define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE) ++#define F_SECUREPORTENABLE V_SECUREPORTENABLE(1U) ++ ++#define S_ARPENABLE 28 ++#define V_ARPENABLE(x) ((x) << S_ARPENABLE) ++#define F_ARPENABLE V_ARPENABLE(1U) ++ ++#define S_VLAN 0 ++#define M_VLAN 0xffff ++#define V_VLAN(x) ((x) << S_VLAN) ++#define G_VLAN(x) (((x) >> S_VLAN) & M_VLAN) ++ ++#define A_TP_IPMI_CFG2 0x29 ++ ++#define S_SECUREPORT 16 ++#define M_SECUREPORT 0xffff ++#define V_SECUREPORT(x) ((x) << S_SECUREPORT) ++#define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT) ++ ++#define S_PRIMARYPORT 0 ++#define M_PRIMARYPORT 0xffff ++#define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT) ++#define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT) ++ ++#define A_TP_RX_TRC_KEY0 0x120 ++#define A_TP_RX_TRC_MASK0 0x121 ++#define A_TP_RX_TRC_KEY1 0x122 ++#define A_TP_RX_TRC_MASK1 0x123 ++#define A_TP_RX_TRC_KEY2 0x124 ++#define A_TP_RX_TRC_MASK2 0x125 ++#define A_TP_RX_TRC_KEY3 0x126 ++#define A_TP_RX_TRC_MASK3 0x127 ++#define A_TP_QOS_RX_TOS_MAP_H 0x128 ++#define A_TP_QOS_RX_TOS_MAP_L 0x129 ++#define A_TP_QOS_RX_MAP_MODE 0x12a ++ ++#define S_DEFAULTCH 11 ++#define V_DEFAULTCH(x) ((x) << S_DEFAULTCH) ++#define F_DEFAULTCH V_DEFAULTCH(1U) ++ ++#define S_RXMAPMODE 8 ++#define M_RXMAPMODE 0x7 ++#define V_RXMAPMODE(x) ((x) << S_RXMAPMODE) ++#define G_RXMAPMODE(x) (((x) >> S_RXMAPMODE) & M_RXMAPMODE) ++ ++#define S_RXVLANMAP 7 ++#define V_RXVLANMAP(x) ((x) << S_RXVLANMAP) ++#define F_RXVLANMAP V_RXVLANMAP(1U) ++ ++#define A_TP_TX_DROP_CFG_CH0 0x12b ++ ++#define S_TIMERENABLED 31 ++#define V_TIMERENABLED(x) ((x) << S_TIMERENABLED) ++#define F_TIMERENABLED V_TIMERENABLED(1U) ++ ++#define S_TIMERERRORENABLE 30 ++#define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE) ++#define F_TIMERERRORENABLE V_TIMERERRORENABLE(1U) ++ ++#define S_TIMERTHRESHOLD 4 ++#define M_TIMERTHRESHOLD 0x3ffffff ++#define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD) ++#define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD) ++ ++#define S_PACKETDROPS 0 ++#define M_PACKETDROPS 0xf ++#define V_PACKETDROPS(x) ((x) << S_PACKETDROPS) ++#define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS) ++ ++#define A_TP_TX_DROP_CFG_CH1 0x12c ++#define A_TP_TX_DROP_CNT_CH0 0x12d ++ ++#define S_TXDROPCNTCH0SENT 16 ++#define M_TXDROPCNTCH0SENT 0xffff ++#define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT) ++#define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT) ++ ++#define S_TXDROPCNTCH0RCVD 0 ++#define M_TXDROPCNTCH0RCVD 0xffff ++#define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD) ++#define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD) ++ ++#define A_TP_TX_DROP_CNT_CH1 0x12e ++ ++#define S_TXDROPCNTCH1SENT 16 ++#define M_TXDROPCNTCH1SENT 0xffff ++#define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT) ++#define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT) ++ ++#define S_TXDROPCNTCH1RCVD 0 ++#define M_TXDROPCNTCH1RCVD 0xffff ++#define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD) ++#define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD) ++ ++#define A_TP_TX_DROP_MODE 0x12f ++ ++#define S_TXDROPMODECH1 1 ++#define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1) ++#define F_TXDROPMODECH1 V_TXDROPMODECH1(1U) ++ ++#define S_TXDROPMODECH0 0 ++#define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0) ++#define F_TXDROPMODECH0 V_TXDROPMODECH0(1U) ++ ++#define A_TP_VLAN_PRI_MAP 0x137 ++ ++#define S_VLANPRIMAP7 14 ++#define M_VLANPRIMAP7 0x3 ++#define V_VLANPRIMAP7(x) ((x) << S_VLANPRIMAP7) ++#define G_VLANPRIMAP7(x) (((x) >> S_VLANPRIMAP7) & M_VLANPRIMAP7) ++ ++#define S_VLANPRIMAP6 12 ++#define M_VLANPRIMAP6 0x3 ++#define V_VLANPRIMAP6(x) ((x) << S_VLANPRIMAP6) ++#define G_VLANPRIMAP6(x) (((x) >> S_VLANPRIMAP6) & M_VLANPRIMAP6) ++ ++#define S_VLANPRIMAP5 10 ++#define M_VLANPRIMAP5 0x3 ++#define V_VLANPRIMAP5(x) ((x) << S_VLANPRIMAP5) ++#define G_VLANPRIMAP5(x) (((x) >> S_VLANPRIMAP5) & M_VLANPRIMAP5) ++ ++#define S_VLANPRIMAP4 8 ++#define M_VLANPRIMAP4 0x3 ++#define V_VLANPRIMAP4(x) ((x) << S_VLANPRIMAP4) ++#define G_VLANPRIMAP4(x) (((x) >> S_VLANPRIMAP4) & M_VLANPRIMAP4) ++ ++#define S_VLANPRIMAP3 6 ++#define M_VLANPRIMAP3 0x3 ++#define V_VLANPRIMAP3(x) ((x) << S_VLANPRIMAP3) ++#define G_VLANPRIMAP3(x) (((x) >> S_VLANPRIMAP3) & M_VLANPRIMAP3) ++ ++#define S_VLANPRIMAP2 4 ++#define M_VLANPRIMAP2 0x3 ++#define V_VLANPRIMAP2(x) ((x) << S_VLANPRIMAP2) ++#define G_VLANPRIMAP2(x) (((x) >> S_VLANPRIMAP2) & M_VLANPRIMAP2) ++ ++#define S_VLANPRIMAP1 2 ++#define M_VLANPRIMAP1 0x3 ++#define V_VLANPRIMAP1(x) ((x) << S_VLANPRIMAP1) ++#define G_VLANPRIMAP1(x) (((x) >> S_VLANPRIMAP1) & M_VLANPRIMAP1) ++ ++#define S_VLANPRIMAP0 0 ++#define M_VLANPRIMAP0 0x3 ++#define V_VLANPRIMAP0(x) ((x) << S_VLANPRIMAP0) ++#define G_VLANPRIMAP0(x) (((x) >> S_VLANPRIMAP0) & M_VLANPRIMAP0) ++ ++#define A_TP_MAC_MATCH_MAP0 0x138 ++ ++#define S_MACMATCHMAP7 21 ++#define M_MACMATCHMAP7 0x7 ++#define V_MACMATCHMAP7(x) ((x) << S_MACMATCHMAP7) ++#define G_MACMATCHMAP7(x) (((x) >> S_MACMATCHMAP7) & M_MACMATCHMAP7) ++ ++#define S_MACMATCHMAP6 18 ++#define M_MACMATCHMAP6 0x7 ++#define V_MACMATCHMAP6(x) ((x) << S_MACMATCHMAP6) ++#define G_MACMATCHMAP6(x) (((x) >> S_MACMATCHMAP6) & M_MACMATCHMAP6) ++ ++#define S_MACMATCHMAP5 15 ++#define M_MACMATCHMAP5 0x7 ++#define V_MACMATCHMAP5(x) ((x) << S_MACMATCHMAP5) ++#define G_MACMATCHMAP5(x) (((x) >> S_MACMATCHMAP5) & M_MACMATCHMAP5) ++ ++#define S_MACMATCHMAP4 12 ++#define M_MACMATCHMAP4 0x7 ++#define V_MACMATCHMAP4(x) ((x) << S_MACMATCHMAP4) ++#define G_MACMATCHMAP4(x) (((x) >> S_MACMATCHMAP4) & M_MACMATCHMAP4) ++ ++#define S_MACMATCHMAP3 9 ++#define M_MACMATCHMAP3 0x7 ++#define V_MACMATCHMAP3(x) ((x) << S_MACMATCHMAP3) ++#define G_MACMATCHMAP3(x) (((x) >> S_MACMATCHMAP3) & M_MACMATCHMAP3) ++ ++#define S_MACMATCHMAP2 6 ++#define M_MACMATCHMAP2 0x7 ++#define V_MACMATCHMAP2(x) ((x) << S_MACMATCHMAP2) ++#define G_MACMATCHMAP2(x) (((x) >> S_MACMATCHMAP2) & M_MACMATCHMAP2) ++ ++#define S_MACMATCHMAP1 3 ++#define M_MACMATCHMAP1 0x7 ++#define V_MACMATCHMAP1(x) ((x) << S_MACMATCHMAP1) ++#define G_MACMATCHMAP1(x) (((x) >> S_MACMATCHMAP1) & M_MACMATCHMAP1) ++ ++#define S_MACMATCHMAP0 0 ++#define M_MACMATCHMAP0 0x7 ++#define V_MACMATCHMAP0(x) ((x) << S_MACMATCHMAP0) ++#define G_MACMATCHMAP0(x) (((x) >> S_MACMATCHMAP0) & M_MACMATCHMAP0) ++ ++#define A_TP_MAC_MATCH_MAP1 0x139 ++#define A_TP_INGRESS_CONFIG 0x141 ++ ++#define S_LOOKUPEVERYPKT 28 ++#define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT) ++#define F_LOOKUPEVERYPKT V_LOOKUPEVERYPKT(1U) ++ ++#define S_ENABLEINSERTIONSFD 27 ++#define V_ENABLEINSERTIONSFD(x) ((x) << S_ENABLEINSERTIONSFD) ++#define F_ENABLEINSERTIONSFD V_ENABLEINSERTIONSFD(1U) ++ ++#define S_ENABLEINSERTION 26 ++#define V_ENABLEINSERTION(x) ((x) << S_ENABLEINSERTION) ++#define F_ENABLEINSERTION V_ENABLEINSERTION(1U) ++ ++#define S_ENABLEEXTRACTIONSFD 25 ++#define V_ENABLEEXTRACTIONSFD(x) ((x) << S_ENABLEEXTRACTIONSFD) ++#define F_ENABLEEXTRACTIONSFD V_ENABLEEXTRACTIONSFD(1U) ++ ++#define S_ENABLEEXTRACT 24 ++#define V_ENABLEEXTRACT(x) ((x) << S_ENABLEEXTRACT) ++#define F_ENABLEEXTRACT V_ENABLEEXTRACT(1U) ++ ++#define S_BITPOS3 18 ++#define M_BITPOS3 0x3f ++#define V_BITPOS3(x) ((x) << S_BITPOS3) ++#define G_BITPOS3(x) (((x) >> S_BITPOS3) & M_BITPOS3) ++ ++#define S_BITPOS2 12 ++#define M_BITPOS2 0x3f ++#define V_BITPOS2(x) ((x) << S_BITPOS2) ++#define G_BITPOS2(x) (((x) >> S_BITPOS2) & M_BITPOS2) ++ ++#define S_BITPOS1 6 ++#define M_BITPOS1 0x3f ++#define V_BITPOS1(x) ((x) << S_BITPOS1) ++#define G_BITPOS1(x) (((x) >> S_BITPOS1) & M_BITPOS1) ++ ++#define S_BITPOS0 0 ++#define M_BITPOS0 0x3f ++#define V_BITPOS0(x) ((x) << S_BITPOS0) ++#define G_BITPOS0(x) (((x) >> S_BITPOS0) & M_BITPOS0) ++ ++#define A_TP_PREAMBLE_MSB 0x142 ++#define A_TP_PREAMBLE_LSB 0x143 ++#define A_TP_EGRESS_CONFIG 0x145 ++ ++#define S_REWRITEFORCETOSIZE 0 ++#define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE) ++#define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U) ++ ++#define A_TP_INTF_FROM_TX_PKT 0x244 ++ ++#define S_INTFFROMTXPKT 0 ++#define V_INTFFROMTXPKT(x) ((x) << S_INTFFROMTXPKT) ++#define F_INTFFROMTXPKT V_INTFFROMTXPKT(1U) ++ ++#define A_TP_FIFO_CONFIG 0x8c0 ++ ++#define S_RXFIFOCONFIG 10 ++#define M_RXFIFOCONFIG 0x3f ++#define V_RXFIFOCONFIG(x) ((x) << S_RXFIFOCONFIG) ++#define G_RXFIFOCONFIG(x) (((x) >> S_RXFIFOCONFIG) & M_RXFIFOCONFIG) ++ ++#define S_TXFIFOCONFIG 2 ++#define M_TXFIFOCONFIG 0x3f ++#define V_TXFIFOCONFIG(x) ((x) << S_TXFIFOCONFIG) ++#define G_TXFIFOCONFIG(x) (((x) >> S_TXFIFOCONFIG) & M_TXFIFOCONFIG) ++ ++/* registers for module ULP2_RX */ ++#define ULP2_RX_BASE_ADDR 0x500 + + #define A_ULPRX_CTL 0x500 ++ ++#define S_PCMD1THRESHOLD 24 ++#define M_PCMD1THRESHOLD 0xff ++#define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD) ++#define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD) ++ ++#define S_PCMD0THRESHOLD 16 ++#define M_PCMD0THRESHOLD 0xff ++#define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD) ++#define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD) + + #define S_ROUND_ROBIN 4 + #define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN) + #define F_ROUND_ROBIN V_ROUND_ROBIN(1U) + ++#define S_RDMA_PERMISSIVE_MODE 3 ++#define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE) ++#define F_RDMA_PERMISSIVE_MODE V_RDMA_PERMISSIVE_MODE(1U) ++ ++#define S_PAGEPODME 2 ++#define V_PAGEPODME(x) ((x) << S_PAGEPODME) ++#define F_PAGEPODME V_PAGEPODME(1U) ++ ++#define S_ISCSITAGTCB 1 ++#define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB) ++#define F_ISCSITAGTCB V_ISCSITAGTCB(1U) ++ ++#define S_TDDPTAGTCB 0 ++#define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB) ++#define F_TDDPTAGTCB V_TDDPTAGTCB(1U) ++ + #define A_ULPRX_INT_ENABLE 0x504 + + #define S_DATASELFRAMEERR0 7 +@@ -1513,51 +5380,85 @@ + #define V_PARERRDATA(x) ((x) << S_PARERRDATA) + #define F_PARERRDATA V_PARERRDATA(1U) + ++#define S_PARERR 0 ++#define V_PARERR(x) ((x) << S_PARERR) ++#define F_PARERR V_PARERR(1U) ++ + #define A_ULPRX_INT_CAUSE 0x508 +- + #define A_ULPRX_ISCSI_LLIMIT 0x50c + ++#define S_ISCSILLIMIT 6 ++#define M_ISCSILLIMIT 0x3ffffff ++#define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT) ++#define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT) ++ + #define A_ULPRX_ISCSI_ULIMIT 0x510 + ++#define S_ISCSIULIMIT 6 ++#define M_ISCSIULIMIT 0x3ffffff ++#define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT) ++#define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT) ++ + #define A_ULPRX_ISCSI_TAGMASK 0x514 + ++#define S_ISCSITAGMASK 6 ++#define M_ISCSITAGMASK 0x3ffffff ++#define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK) ++#define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK) ++ + #define A_ULPRX_ISCSI_PSZ 0x518 + +-#define A_ULPRX_TDDP_LLIMIT 0x51c +- +-#define A_ULPRX_TDDP_ULIMIT 0x520 +-#define A_ULPRX_TDDP_PSZ 0x528 ++#define S_HPZ3 24 ++#define M_HPZ3 0xf ++#define V_HPZ3(x) ((x) << S_HPZ3) ++#define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3) ++ ++#define S_HPZ2 16 ++#define M_HPZ2 0xf ++#define V_HPZ2(x) ((x) << S_HPZ2) ++#define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2) ++ ++#define S_HPZ1 8 ++#define M_HPZ1 0xf ++#define V_HPZ1(x) ((x) << S_HPZ1) ++#define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1) + + #define S_HPZ0 0 + #define M_HPZ0 0xf + #define V_HPZ0(x) ((x) << S_HPZ0) + #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0) + ++#define A_ULPRX_TDDP_LLIMIT 0x51c ++ ++#define S_TDDPLLIMIT 6 ++#define M_TDDPLLIMIT 0x3ffffff ++#define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT) ++#define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT) ++ ++#define A_ULPRX_TDDP_ULIMIT 0x520 ++ ++#define S_TDDPULIMIT 6 ++#define M_TDDPULIMIT 0x3ffffff ++#define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT) ++#define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT) ++ ++#define A_ULPRX_TDDP_TAGMASK 0x524 ++ ++#define S_TDDPTAGMASK 6 ++#define M_TDDPTAGMASK 0x3ffffff ++#define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK) ++#define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK) ++ ++#define A_ULPRX_TDDP_PSZ 0x528 + #define A_ULPRX_STAG_LLIMIT 0x52c +- + #define A_ULPRX_STAG_ULIMIT 0x530 +- + #define A_ULPRX_RQ_LLIMIT 0x534 +-#define A_ULPRX_RQ_LLIMIT 0x534 +- + #define A_ULPRX_RQ_ULIMIT 0x538 +-#define A_ULPRX_RQ_ULIMIT 0x538 +- + #define A_ULPRX_PBL_LLIMIT 0x53c +- + #define A_ULPRX_PBL_ULIMIT 0x540 +-#define A_ULPRX_PBL_ULIMIT 0x540 +- +-#define A_ULPRX_TDDP_TAGMASK 0x524 +- +-#define A_ULPRX_RQ_LLIMIT 0x534 +-#define A_ULPRX_RQ_LLIMIT 0x534 +- +-#define A_ULPRX_RQ_ULIMIT 0x538 +-#define A_ULPRX_RQ_ULIMIT 0x538 +- +-#define A_ULPRX_PBL_ULIMIT 0x540 +-#define A_ULPRX_PBL_ULIMIT 0x540 ++ ++/* registers for module ULP2_TX */ ++#define ULP2_TX_BASE_ADDR 0x580 + + #define A_ULPTX_CONFIG 0x580 + +@@ -1571,6 +5472,30 @@ + + #define A_ULPTX_INT_ENABLE 0x584 + ++#define S_CMD_FIFO_PERR_SET1 7 ++#define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1) ++#define F_CMD_FIFO_PERR_SET1 V_CMD_FIFO_PERR_SET1(1U) ++ ++#define S_CMD_FIFO_PERR_SET0 6 ++#define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0) ++#define F_CMD_FIFO_PERR_SET0 V_CMD_FIFO_PERR_SET0(1U) ++ ++#define S_LSO_HDR_SRAM_PERR_SET1 5 ++#define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1) ++#define F_LSO_HDR_SRAM_PERR_SET1 V_LSO_HDR_SRAM_PERR_SET1(1U) ++ ++#define S_LSO_HDR_SRAM_PERR_SET0 4 ++#define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0) ++#define F_LSO_HDR_SRAM_PERR_SET0 V_LSO_HDR_SRAM_PERR_SET0(1U) ++ ++#define S_IMM_DATA_PERR_SET_CH1 3 ++#define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1) ++#define F_IMM_DATA_PERR_SET_CH1 V_IMM_DATA_PERR_SET_CH1(1U) ++ ++#define S_IMM_DATA_PERR_SET_CH0 2 ++#define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0) ++#define F_IMM_DATA_PERR_SET_CH0 V_IMM_DATA_PERR_SET_CH0(1U) ++ + #define S_PBL_BOUND_ERR_CH1 1 + #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1) + #define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U) +@@ -1580,28 +5505,70 @@ + #define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U) + + #define A_ULPTX_INT_CAUSE 0x588 +- + #define A_ULPTX_TPT_LLIMIT 0x58c +- + #define A_ULPTX_TPT_ULIMIT 0x590 +- + #define A_ULPTX_PBL_LLIMIT 0x594 +- + #define A_ULPTX_PBL_ULIMIT 0x598 ++#define A_ULPTX_CPL_ERR_OFFSET 0x59c ++#define A_ULPTX_CPL_ERR_MASK 0x5a0 ++#define A_ULPTX_CPL_ERR_VALUE 0x5a4 ++#define A_ULPTX_CPL_PACK_SIZE 0x5a8 ++ ++#define S_VALUE 24 ++#define M_VALUE 0xff ++#define V_VALUE(x) ((x) << S_VALUE) ++#define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE) ++ ++#define S_CH1SIZE2 24 ++#define M_CH1SIZE2 0xff ++#define V_CH1SIZE2(x) ((x) << S_CH1SIZE2) ++#define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2) ++ ++#define S_CH1SIZE1 16 ++#define M_CH1SIZE1 0xff ++#define V_CH1SIZE1(x) ((x) << S_CH1SIZE1) ++#define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1) ++ ++#define S_CH0SIZE2 8 ++#define M_CH0SIZE2 0xff ++#define V_CH0SIZE2(x) ((x) << S_CH0SIZE2) ++#define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2) ++ ++#define S_CH0SIZE1 0 ++#define M_CH0SIZE1 0xff ++#define V_CH0SIZE1(x) ((x) << S_CH0SIZE1) ++#define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1) + + #define A_ULPTX_DMA_WEIGHT 0x5ac + + #define S_D1_WEIGHT 16 + #define M_D1_WEIGHT 0xffff + #define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT) ++#define G_D1_WEIGHT(x) (((x) >> S_D1_WEIGHT) & M_D1_WEIGHT) + + #define S_D0_WEIGHT 0 + #define M_D0_WEIGHT 0xffff + #define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT) ++#define G_D0_WEIGHT(x) (((x) >> S_D0_WEIGHT) & M_D0_WEIGHT) ++ ++/* registers for module PM1_RX */ ++#define PM1_RX_BASE_ADDR 0x5c0 + + #define A_PM1_RX_CFG 0x5c0 + #define A_PM1_RX_MODE 0x5c4 + ++#define S_STAT_CHANNEL 1 ++#define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL) ++#define F_STAT_CHANNEL V_STAT_CHANNEL(1U) ++ ++#define S_PRIORITY_CH 0 ++#define V_PRIORITY_CH(x) ((x) << S_PRIORITY_CH) ++#define F_PRIORITY_CH V_PRIORITY_CH(1U) ++ ++#define A_PM1_RX_STAT_CONFIG 0x5c8 ++#define A_PM1_RX_STAT_COUNT 0x5cc ++#define A_PM1_RX_STAT_MSB 0x5d0 ++#define A_PM1_RX_STAT_LSB 0x5d4 + #define A_PM1_RX_INT_ENABLE 0x5d8 + + #define S_ZERO_E_CMD_ERROR 18 +@@ -1658,19 +5625,25 @@ + + #define S_IESPI_PAR_ERROR 3 + #define M_IESPI_PAR_ERROR 0x7 +- + #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR) ++#define G_IESPI_PAR_ERROR(x) (((x) >> S_IESPI_PAR_ERROR) & M_IESPI_PAR_ERROR) + + #define S_OCSPI_PAR_ERROR 0 + #define M_OCSPI_PAR_ERROR 0x7 +- + #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR) ++#define G_OCSPI_PAR_ERROR(x) (((x) >> S_OCSPI_PAR_ERROR) & M_OCSPI_PAR_ERROR) + + #define A_PM1_RX_INT_CAUSE 0x5dc ++ ++/* registers for module PM1_TX */ ++#define PM1_TX_BASE_ADDR 0x5e0 + + #define A_PM1_TX_CFG 0x5e0 + #define A_PM1_TX_MODE 0x5e4 +- ++#define A_PM1_TX_STAT_CONFIG 0x5e8 ++#define A_PM1_TX_STAT_COUNT 0x5ec ++#define A_PM1_TX_STAT_MSB 0x5f0 ++#define A_PM1_TX_STAT_LSB 0x5f4 + #define A_PM1_TX_INT_ENABLE 0x5f8 + + #define S_ZERO_C_CMD_ERROR 18 +@@ -1727,17 +5700,41 @@ + + #define S_ICSPI_PAR_ERROR 3 + #define M_ICSPI_PAR_ERROR 0x7 +- + #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR) ++#define G_ICSPI_PAR_ERROR(x) (((x) >> S_ICSPI_PAR_ERROR) & M_ICSPI_PAR_ERROR) + + #define S_OESPI_PAR_ERROR 0 + #define M_OESPI_PAR_ERROR 0x7 +- + #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR) ++#define G_OESPI_PAR_ERROR(x) (((x) >> S_OESPI_PAR_ERROR) & M_OESPI_PAR_ERROR) + + #define A_PM1_TX_INT_CAUSE 0x5fc + ++/* registers for module MPS0 */ ++#define MPS0_BASE_ADDR 0x600 ++ + #define A_MPS_CFG 0x600 ++ ++#define S_ENFORCEPKT 11 ++#define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT) ++#define F_ENFORCEPKT V_ENFORCEPKT(1U) ++ ++#define S_SGETPQID 8 ++#define M_SGETPQID 0x7 ++#define V_SGETPQID(x) ((x) << S_SGETPQID) ++#define G_SGETPQID(x) (((x) >> S_SGETPQID) & M_SGETPQID) ++ ++#define S_TPRXPORTSIZE 7 ++#define V_TPRXPORTSIZE(x) ((x) << S_TPRXPORTSIZE) ++#define F_TPRXPORTSIZE V_TPRXPORTSIZE(1U) ++ ++#define S_TPTXPORT1SIZE 6 ++#define V_TPTXPORT1SIZE(x) ((x) << S_TPTXPORT1SIZE) ++#define F_TPTXPORT1SIZE V_TPTXPORT1SIZE(1U) ++ ++#define S_TPTXPORT0SIZE 5 ++#define V_TPTXPORT0SIZE(x) ((x) << S_TPTXPORT0SIZE) ++#define F_TPTXPORT0SIZE V_TPTXPORT0SIZE(1U) + + #define S_TPRXPORTEN 4 + #define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN) +@@ -1759,55 +5756,161 @@ + #define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE) + #define F_PORT0ACTIVE V_PORT0ACTIVE(1U) + +-#define S_ENFORCEPKT 11 +-#define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT) +-#define F_ENFORCEPKT V_ENFORCEPKT(1U) ++#define A_MPS_DRR_CFG1 0x604 ++ ++#define S_RLDWTTPD1 11 ++#define M_RLDWTTPD1 0x7ff ++#define V_RLDWTTPD1(x) ((x) << S_RLDWTTPD1) ++#define G_RLDWTTPD1(x) (((x) >> S_RLDWTTPD1) & M_RLDWTTPD1) ++ ++#define S_RLDWTTPD0 0 ++#define M_RLDWTTPD0 0x7ff ++#define V_RLDWTTPD0(x) ((x) << S_RLDWTTPD0) ++#define G_RLDWTTPD0(x) (((x) >> S_RLDWTTPD0) & M_RLDWTTPD0) ++ ++#define A_MPS_DRR_CFG2 0x608 ++ ++#define S_RLDWTTOTAL 0 ++#define M_RLDWTTOTAL 0xfff ++#define V_RLDWTTOTAL(x) ((x) << S_RLDWTTOTAL) ++#define G_RLDWTTOTAL(x) (((x) >> S_RLDWTTOTAL) & M_RLDWTTOTAL) ++ ++#define A_MPS_MCA_STATUS 0x60c ++ ++#define S_MCAPKTCNT 12 ++#define M_MCAPKTCNT 0xfffff ++#define V_MCAPKTCNT(x) ((x) << S_MCAPKTCNT) ++#define G_MCAPKTCNT(x) (((x) >> S_MCAPKTCNT) & M_MCAPKTCNT) ++ ++#define S_MCADEPTH 0 ++#define M_MCADEPTH 0xfff ++#define V_MCADEPTH(x) ((x) << S_MCADEPTH) ++#define G_MCADEPTH(x) (((x) >> S_MCADEPTH) & M_MCADEPTH) ++ ++#define A_MPS_TX0_TP_CNT 0x610 ++ ++#define S_TX0TPDISCNT 24 ++#define M_TX0TPDISCNT 0xff ++#define V_TX0TPDISCNT(x) ((x) << S_TX0TPDISCNT) ++#define G_TX0TPDISCNT(x) (((x) >> S_TX0TPDISCNT) & M_TX0TPDISCNT) ++ ++#define S_TX0TPCNT 0 ++#define M_TX0TPCNT 0xffffff ++#define V_TX0TPCNT(x) ((x) << S_TX0TPCNT) ++#define G_TX0TPCNT(x) (((x) >> S_TX0TPCNT) & M_TX0TPCNT) ++ ++#define A_MPS_TX1_TP_CNT 0x614 ++ ++#define S_TX1TPDISCNT 24 ++#define M_TX1TPDISCNT 0xff ++#define V_TX1TPDISCNT(x) ((x) << S_TX1TPDISCNT) ++#define G_TX1TPDISCNT(x) (((x) >> S_TX1TPDISCNT) & M_TX1TPDISCNT) ++ ++#define S_TX1TPCNT 0 ++#define M_TX1TPCNT 0xffffff ++#define V_TX1TPCNT(x) ((x) << S_TX1TPCNT) ++#define G_TX1TPCNT(x) (((x) >> S_TX1TPCNT) & M_TX1TPCNT) ++ ++#define A_MPS_RX_TP_CNT 0x618 ++ ++#define S_RXTPDISCNT 24 ++#define M_RXTPDISCNT 0xff ++#define V_RXTPDISCNT(x) ((x) << S_RXTPDISCNT) ++#define G_RXTPDISCNT(x) (((x) >> S_RXTPDISCNT) & M_RXTPDISCNT) ++ ++#define S_RXTPCNT 0 ++#define M_RXTPCNT 0xffffff ++#define V_RXTPCNT(x) ((x) << S_RXTPCNT) ++#define G_RXTPCNT(x) (((x) >> S_RXTPCNT) & M_RXTPCNT) + + #define A_MPS_INT_ENABLE 0x61c + + #define S_MCAPARERRENB 6 + #define M_MCAPARERRENB 0x7 +- + #define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB) ++#define G_MCAPARERRENB(x) (((x) >> S_MCAPARERRENB) & M_MCAPARERRENB) + + #define S_RXTPPARERRENB 4 + #define M_RXTPPARERRENB 0x3 +- + #define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB) ++#define G_RXTPPARERRENB(x) (((x) >> S_RXTPPARERRENB) & M_RXTPPARERRENB) + + #define S_TX1TPPARERRENB 2 + #define M_TX1TPPARERRENB 0x3 +- + #define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB) ++#define G_TX1TPPARERRENB(x) (((x) >> S_TX1TPPARERRENB) & M_TX1TPPARERRENB) + + #define S_TX0TPPARERRENB 0 + #define M_TX0TPPARERRENB 0x3 +- + #define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB) ++#define G_TX0TPPARERRENB(x) (((x) >> S_TX0TPPARERRENB) & M_TX0TPPARERRENB) + + #define A_MPS_INT_CAUSE 0x620 + + #define S_MCAPARERR 6 + #define M_MCAPARERR 0x7 +- + #define V_MCAPARERR(x) ((x) << S_MCAPARERR) ++#define G_MCAPARERR(x) (((x) >> S_MCAPARERR) & M_MCAPARERR) + + #define S_RXTPPARERR 4 + #define M_RXTPPARERR 0x3 +- + #define V_RXTPPARERR(x) ((x) << S_RXTPPARERR) ++#define G_RXTPPARERR(x) (((x) >> S_RXTPPARERR) & M_RXTPPARERR) + + #define S_TX1TPPARERR 2 + #define M_TX1TPPARERR 0x3 +- + #define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR) ++#define G_TX1TPPARERR(x) (((x) >> S_TX1TPPARERR) & M_TX1TPPARERR) + + #define S_TX0TPPARERR 0 + #define M_TX0TPPARERR 0x3 +- + #define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR) ++#define G_TX0TPPARERR(x) (((x) >> S_TX0TPPARERR) & M_TX0TPPARERR) ++ ++/* registers for module CPL_SWITCH */ ++#define CPL_SWITCH_BASE_ADDR 0x640 + + #define A_CPL_SWITCH_CNTRL 0x640 ++ ++#define S_CPL_PKT_TID 8 ++#define M_CPL_PKT_TID 0xffffff ++#define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID) ++#define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID) ++ ++#define S_CIM_TO_UP_FULL_SIZE 4 ++#define V_CIM_TO_UP_FULL_SIZE(x) ((x) << S_CIM_TO_UP_FULL_SIZE) ++#define F_CIM_TO_UP_FULL_SIZE V_CIM_TO_UP_FULL_SIZE(1U) ++ ++#define S_CPU_NO_3F_CIM_ENABLE 3 ++#define V_CPU_NO_3F_CIM_ENABLE(x) ((x) << S_CPU_NO_3F_CIM_ENABLE) ++#define F_CPU_NO_3F_CIM_ENABLE V_CPU_NO_3F_CIM_ENABLE(1U) ++ ++#define S_SWITCH_TABLE_ENABLE 2 ++#define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE) ++#define F_SWITCH_TABLE_ENABLE V_SWITCH_TABLE_ENABLE(1U) ++ ++#define S_SGE_ENABLE 1 ++#define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE) ++#define F_SGE_ENABLE V_SGE_ENABLE(1U) ++ ++#define S_CIM_ENABLE 0 ++#define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE) ++#define F_CIM_ENABLE V_CIM_ENABLE(1U) ++ ++#define A_CPL_SWITCH_TBL_IDX 0x644 ++ ++#define S_SWITCH_TBL_IDX 0 ++#define M_SWITCH_TBL_IDX 0xf ++#define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX) ++#define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX) ++ ++#define A_CPL_SWITCH_TBL_DATA 0x648 ++#define A_CPL_SWITCH_ZERO_ERROR 0x64c ++ ++#define S_ZERO_CMD 0 ++#define M_ZERO_CMD 0xff ++#define V_ZERO_CMD(x) ((x) << S_ZERO_CMD) ++#define G_ZERO_CMD(x) (((x) >> S_ZERO_CMD) & M_ZERO_CMD) + + #define A_CPL_INTR_ENABLE 0x650 + +@@ -1836,29 +5939,289 @@ + #define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U) + + #define A_CPL_INTR_CAUSE 0x654 ++#define A_CPL_MAP_TBL_IDX 0x658 ++ ++#define S_CPL_MAP_TBL_IDX 0 ++#define M_CPL_MAP_TBL_IDX 0xff ++#define V_CPL_MAP_TBL_IDX(x) ((x) << S_CPL_MAP_TBL_IDX) ++#define G_CPL_MAP_TBL_IDX(x) (((x) >> S_CPL_MAP_TBL_IDX) & M_CPL_MAP_TBL_IDX) + + #define A_CPL_MAP_TBL_DATA 0x65c + ++#define S_CPL_MAP_TBL_DATA 0 ++#define M_CPL_MAP_TBL_DATA 0xff ++#define V_CPL_MAP_TBL_DATA(x) ((x) << S_CPL_MAP_TBL_DATA) ++#define G_CPL_MAP_TBL_DATA(x) (((x) >> S_CPL_MAP_TBL_DATA) & M_CPL_MAP_TBL_DATA) ++ ++/* registers for module SMB0 */ ++#define SMB0_BASE_ADDR 0x660 ++ + #define A_SMB_GLOBAL_TIME_CFG 0x660 ++ ++#define S_LADBGWRPTR 24 ++#define M_LADBGWRPTR 0xff ++#define V_LADBGWRPTR(x) ((x) << S_LADBGWRPTR) ++#define G_LADBGWRPTR(x) (((x) >> S_LADBGWRPTR) & M_LADBGWRPTR) ++ ++#define S_LADBGRDPTR 16 ++#define M_LADBGRDPTR 0xff ++#define V_LADBGRDPTR(x) ((x) << S_LADBGRDPTR) ++#define G_LADBGRDPTR(x) (((x) >> S_LADBGRDPTR) & M_LADBGRDPTR) ++ ++#define S_LADBGEN 13 ++#define V_LADBGEN(x) ((x) << S_LADBGEN) ++#define F_LADBGEN V_LADBGEN(1U) ++ ++#define S_MACROCNTCFG 8 ++#define M_MACROCNTCFG 0x1f ++#define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG) ++#define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG) ++ ++#define S_MICROCNTCFG 0 ++#define M_MICROCNTCFG 0xff ++#define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG) ++#define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG) ++ ++#define A_SMB_MST_TIMEOUT_CFG 0x664 ++ ++#define S_DEBUGSELH 28 ++#define M_DEBUGSELH 0xf ++#define V_DEBUGSELH(x) ((x) << S_DEBUGSELH) ++#define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH) ++ ++#define S_DEBUGSELL 24 ++#define M_DEBUGSELL 0xf ++#define V_DEBUGSELL(x) ((x) << S_DEBUGSELL) ++#define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL) ++ ++#define S_MSTTIMEOUTCFG 0 ++#define M_MSTTIMEOUTCFG 0xffffff ++#define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG) ++#define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG) ++ ++#define A_SMB_MST_CTL_CFG 0x668 ++ ++#define S_MSTFIFODBG 31 ++#define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG) ++#define F_MSTFIFODBG V_MSTFIFODBG(1U) ++ ++#define S_MSTFIFODBGCLR 30 ++#define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR) ++#define F_MSTFIFODBGCLR V_MSTFIFODBGCLR(1U) ++ ++#define S_MSTRXBYTECFG 12 ++#define M_MSTRXBYTECFG 0x3f ++#define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG) ++#define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG) ++ ++#define S_MSTTXBYTECFG 6 ++#define M_MSTTXBYTECFG 0x3f ++#define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG) ++#define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG) ++ ++#define S_MSTRESET 1 ++#define V_MSTRESET(x) ((x) << S_MSTRESET) ++#define F_MSTRESET V_MSTRESET(1U) ++ ++#define S_MSTCTLEN 0 ++#define V_MSTCTLEN(x) ((x) << S_MSTCTLEN) ++#define F_MSTCTLEN V_MSTCTLEN(1U) ++ ++#define A_SMB_MST_CTL_STS 0x66c ++ ++#define S_MSTRXBYTECNT 12 ++#define M_MSTRXBYTECNT 0x3f ++#define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT) ++#define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT) ++ ++#define S_MSTTXBYTECNT 6 ++#define M_MSTTXBYTECNT 0x3f ++#define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT) ++#define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT) ++ ++#define S_MSTBUSYSTS 0 ++#define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS) ++#define F_MSTBUSYSTS V_MSTBUSYSTS(1U) ++ ++#define A_SMB_MST_TX_FIFO_RDWR 0x670 ++#define A_SMB_MST_RX_FIFO_RDWR 0x674 ++#define A_SMB_SLV_TIMEOUT_CFG 0x678 ++ ++#define S_SLVTIMEOUTCFG 0 ++#define M_SLVTIMEOUTCFG 0xffffff ++#define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG) ++#define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG) ++ ++#define A_SMB_SLV_CTL_CFG 0x67c ++ ++#define S_SLVFIFODBG 31 ++#define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG) ++#define F_SLVFIFODBG V_SLVFIFODBG(1U) ++ ++#define S_SLVFIFODBGCLR 30 ++#define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR) ++#define F_SLVFIFODBGCLR V_SLVFIFODBGCLR(1U) ++ ++#define S_SLVADDRCFG 4 ++#define M_SLVADDRCFG 0x7f ++#define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG) ++#define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG) ++ ++#define S_SLVALRTSET 2 ++#define V_SLVALRTSET(x) ((x) << S_SLVALRTSET) ++#define F_SLVALRTSET V_SLVALRTSET(1U) ++ ++#define S_SLVRESET 1 ++#define V_SLVRESET(x) ((x) << S_SLVRESET) ++#define F_SLVRESET V_SLVRESET(1U) ++ ++#define S_SLVCTLEN 0 ++#define V_SLVCTLEN(x) ((x) << S_SLVCTLEN) ++#define F_SLVCTLEN V_SLVCTLEN(1U) ++ ++#define A_SMB_SLV_CTL_STS 0x680 ++ ++#define S_SLVFIFOTXCNT 12 ++#define M_SLVFIFOTXCNT 0x3f ++#define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT) ++#define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT) ++ ++#define S_SLVFIFOCNT 6 ++#define M_SLVFIFOCNT 0x3f ++#define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT) ++#define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT) ++ ++#define S_SLVALRTSTS 2 ++#define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS) ++#define F_SLVALRTSTS V_SLVALRTSTS(1U) ++ ++#define S_SLVBUSYSTS 0 ++#define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS) ++#define F_SLVBUSYSTS V_SLVBUSYSTS(1U) ++ ++#define A_SMB_SLV_FIFO_RDWR 0x684 ++#define A_SMB_SLV_CMD_FIFO_RDWR 0x688 ++#define A_SMB_INT_ENABLE 0x68c ++ ++#define S_SLVTIMEOUTINTEN 7 ++#define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN) ++#define F_SLVTIMEOUTINTEN V_SLVTIMEOUTINTEN(1U) ++ ++#define S_SLVERRINTEN 6 ++#define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN) ++#define F_SLVERRINTEN V_SLVERRINTEN(1U) ++ ++#define S_SLVDONEINTEN 5 ++#define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN) ++#define F_SLVDONEINTEN V_SLVDONEINTEN(1U) ++ ++#define S_SLVRXRDYINTEN 4 ++#define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN) ++#define F_SLVRXRDYINTEN V_SLVRXRDYINTEN(1U) ++ ++#define S_MSTTIMEOUTINTEN 3 ++#define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN) ++#define F_MSTTIMEOUTINTEN V_MSTTIMEOUTINTEN(1U) ++ ++#define S_MSTNACKINTEN 2 ++#define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN) ++#define F_MSTNACKINTEN V_MSTNACKINTEN(1U) ++ ++#define S_MSTLOSTARBINTEN 1 ++#define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN) ++#define F_MSTLOSTARBINTEN V_MSTLOSTARBINTEN(1U) ++ ++#define S_MSTDONEINTEN 0 ++#define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN) ++#define F_MSTDONEINTEN V_MSTDONEINTEN(1U) ++ ++#define A_SMB_INT_CAUSE 0x690 ++ ++#define S_SLVTIMEOUTINT 7 ++#define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT) ++#define F_SLVTIMEOUTINT V_SLVTIMEOUTINT(1U) ++ ++#define S_SLVERRINT 6 ++#define V_SLVERRINT(x) ((x) << S_SLVERRINT) ++#define F_SLVERRINT V_SLVERRINT(1U) ++ ++#define S_SLVDONEINT 5 ++#define V_SLVDONEINT(x) ((x) << S_SLVDONEINT) ++#define F_SLVDONEINT V_SLVDONEINT(1U) ++ ++#define S_SLVRXRDYINT 4 ++#define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT) ++#define F_SLVRXRDYINT V_SLVRXRDYINT(1U) ++ ++#define S_MSTTIMEOUTINT 3 ++#define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT) ++#define F_MSTTIMEOUTINT V_MSTTIMEOUTINT(1U) ++ ++#define S_MSTNACKINT 2 ++#define V_MSTNACKINT(x) ((x) << S_MSTNACKINT) ++#define F_MSTNACKINT V_MSTNACKINT(1U) ++ ++#define S_MSTLOSTARBINT 1 ++#define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT) ++#define F_MSTLOSTARBINT V_MSTLOSTARBINT(1U) ++ ++#define S_MSTDONEINT 0 ++#define V_MSTDONEINT(x) ((x) << S_MSTDONEINT) ++#define F_MSTDONEINT V_MSTDONEINT(1U) ++ ++#define A_SMB_DEBUG_DATA 0x694 ++ ++#define S_DEBUGDATAH 16 ++#define M_DEBUGDATAH 0xffff ++#define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH) ++#define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH) ++ ++#define S_DEBUGDATAL 0 ++#define M_DEBUGDATAL 0xffff ++#define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL) ++#define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL) ++ ++#define A_SMB_DEBUG_LA 0x69c ++ ++#define S_DEBUGLAREQADDR 0 ++#define M_DEBUGLAREQADDR 0x3ff ++#define V_DEBUGLAREQADDR(x) ((x) << S_DEBUGLAREQADDR) ++#define G_DEBUGLAREQADDR(x) (((x) >> S_DEBUGLAREQADDR) & M_DEBUGLAREQADDR) ++ ++/* registers for module I2CM0 */ ++#define I2CM0_BASE_ADDR 0x6a0 + + #define A_I2C_CFG 0x6a0 + + #define S_I2C_CLKDIV 0 + #define M_I2C_CLKDIV 0xfff + #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV) ++#define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV) ++ ++#define A_I2C_DATA 0x6a4 ++#define A_I2C_OP 0x6a8 ++ ++#define S_ACK 30 ++#define V_ACK(x) ((x) << S_ACK) ++#define F_ACK V_ACK(1U) ++ ++#define S_I2C_CONT 1 ++#define V_I2C_CONT(x) ((x) << S_I2C_CONT) ++#define F_I2C_CONT V_I2C_CONT(1U) ++ ++/* registers for module MI1 */ ++#define MI1_BASE_ADDR 0x6b0 + + #define A_MI1_CFG 0x6b0 + + #define S_CLKDIV 5 + #define M_CLKDIV 0xff + #define V_CLKDIV(x) ((x) << S_CLKDIV) ++#define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV) + + #define S_ST 3 +- + #define M_ST 0x3 +- + #define V_ST(x) ((x) << S_ST) +- + #define G_ST(x) (((x) >> S_ST) & M_ST) + + #define S_PREEN 2 +@@ -1878,28 +6241,81 @@ + #define S_PHYADDR 5 + #define M_PHYADDR 0x1f + #define V_PHYADDR(x) ((x) << S_PHYADDR) ++#define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR) + + #define S_REGADDR 0 + #define M_REGADDR 0x1f + #define V_REGADDR(x) ((x) << S_REGADDR) ++#define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR) + + #define A_MI1_DATA 0x6b8 + ++#define S_MDI_DATA 0 ++#define M_MDI_DATA 0xffff ++#define V_MDI_DATA(x) ((x) << S_MDI_DATA) ++#define G_MDI_DATA(x) (((x) >> S_MDI_DATA) & M_MDI_DATA) ++ + #define A_MI1_OP 0x6bc ++ ++#define S_INC 2 ++#define V_INC(x) ((x) << S_INC) ++#define F_INC V_INC(1U) + + #define S_MDI_OP 0 + #define M_MDI_OP 0x3 + #define V_MDI_OP(x) ((x) << S_MDI_OP) ++#define G_MDI_OP(x) (((x) >> S_MDI_OP) & M_MDI_OP) ++ ++/* registers for module JM1 */ ++#define JM1_BASE_ADDR 0x6c0 ++ ++#define A_JM_CFG 0x6c0 ++ ++#define S_JM_CLKDIV 2 ++#define M_JM_CLKDIV 0xff ++#define V_JM_CLKDIV(x) ((x) << S_JM_CLKDIV) ++#define G_JM_CLKDIV(x) (((x) >> S_JM_CLKDIV) & M_JM_CLKDIV) ++ ++#define S_TRST 1 ++#define V_TRST(x) ((x) << S_TRST) ++#define F_TRST V_TRST(1U) ++ ++#define S_EN 0 ++#define V_EN(x) ((x) << S_EN) ++#define F_EN V_EN(1U) ++ ++#define A_JM_MODE 0x6c4 ++#define A_JM_DATA 0x6c8 ++#define A_JM_OP 0x6cc ++ ++#define S_CNT 0 ++#define M_CNT 0x1f ++#define V_CNT(x) ((x) << S_CNT) ++#define G_CNT(x) (((x) >> S_CNT) & M_CNT) ++ ++/* registers for module SF1 */ ++#define SF1_BASE_ADDR 0x6d8 + + #define A_SF_DATA 0x6d8 +- + #define A_SF_OP 0x6dc + + #define S_BYTECNT 1 + #define M_BYTECNT 0x3 + #define V_BYTECNT(x) ((x) << S_BYTECNT) ++#define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT) ++ ++/* registers for module PL3 */ ++#define PL3_BASE_ADDR 0x6e0 + + #define A_PL_INT_ENABLE0 0x6e0 ++ ++#define S_SW 25 ++#define V_SW(x) ((x) << S_SW) ++#define F_SW V_SW(1U) ++ ++#define S_EXT 24 ++#define V_EXT(x) ((x) << S_EXT) ++#define F_EXT V_EXT(1U) + + #define S_T3DBG 23 + #define V_T3DBG(x) ((x) << S_T3DBG) +@@ -1917,6 +6333,22 @@ + #define V_MC5A(x) ((x) << S_MC5A) + #define F_MC5A V_MC5A(1U) + ++#define S_SF1 17 ++#define V_SF1(x) ((x) << S_SF1) ++#define F_SF1 V_SF1(1U) ++ ++#define S_SMB0 15 ++#define V_SMB0(x) ((x) << S_SMB0) ++#define F_SMB0 V_SMB0(1U) ++ ++#define S_I2CM0 14 ++#define V_I2CM0(x) ((x) << S_I2CM0) ++#define F_I2CM0 V_I2CM0(1U) ++ ++#define S_MI1 13 ++#define V_MI1(x) ((x) << S_MI1) ++#define F_MI1 V_MI1(1U) ++ + #define S_CPL_SWITCH 12 + #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH) + #define F_CPL_SWITCH V_CPL_SWITCH(1U) +@@ -1970,8 +6402,21 @@ + #define F_SGE3 V_SGE3(1U) + + #define A_PL_INT_CAUSE0 0x6e4 +- ++#define A_PL_INT_ENABLE1 0x6e8 ++#define A_PL_INT_CAUSE1 0x6ec + #define A_PL_RST 0x6f0 ++ ++#define S_FATALPERREN 4 ++#define V_FATALPERREN(x) ((x) << S_FATALPERREN) ++#define F_FATALPERREN V_FATALPERREN(1U) ++ ++#define S_SWINT1 3 ++#define V_SWINT1(x) ((x) << S_SWINT1) ++#define F_SWINT1 V_SWINT1(1U) ++ ++#define S_SWINT0 2 ++#define V_SWINT0(x) ((x) << S_SWINT0) ++#define F_SWINT0 V_SWINT0(1U) + + #define S_CRSTWRM 1 + #define V_CRSTWRM(x) ((x) << S_CRSTWRM) +@@ -1979,9 +6424,119 @@ + + #define A_PL_REV 0x6f4 + ++#define S_REV 0 ++#define M_REV 0xf ++#define V_REV(x) ((x) << S_REV) ++#define G_REV(x) (((x) >> S_REV) & M_REV) ++ + #define A_PL_CLI 0x6f8 ++#define A_PL_LCK 0x6fc ++ ++#define S_LCK 0 ++#define M_LCK 0x3 ++#define V_LCK(x) ((x) << S_LCK) ++#define G_LCK(x) (((x) >> S_LCK) & M_LCK) ++ ++/* registers for module MC5A */ ++#define MC5A_BASE_ADDR 0x700 ++ ++#define A_MC5_BUF_CONFIG 0x700 ++ ++#define S_TERM300_240 31 ++#define V_TERM300_240(x) ((x) << S_TERM300_240) ++#define F_TERM300_240 V_TERM300_240(1U) ++ ++#define S_MC5_TERM150 30 ++#define V_MC5_TERM150(x) ((x) << S_MC5_TERM150) ++#define F_MC5_TERM150 V_MC5_TERM150(1U) ++ ++#define S_TERM60 29 ++#define V_TERM60(x) ((x) << S_TERM60) ++#define F_TERM60 V_TERM60(1U) ++ ++#define S_GDDRIII 28 ++#define V_GDDRIII(x) ((x) << S_GDDRIII) ++#define F_GDDRIII V_GDDRIII(1U) ++ ++#define S_GDDRII 27 ++#define V_GDDRII(x) ((x) << S_GDDRII) ++#define F_GDDRII V_GDDRII(1U) ++ ++#define S_GDDRI 26 ++#define V_GDDRI(x) ((x) << S_GDDRI) ++#define F_GDDRI V_GDDRI(1U) ++ ++#define S_READ 25 ++#define V_READ(x) ((x) << S_READ) ++#define F_READ V_READ(1U) ++ ++#define S_IMP_SET_UPDATE 24 ++#define V_IMP_SET_UPDATE(x) ((x) << S_IMP_SET_UPDATE) ++#define F_IMP_SET_UPDATE V_IMP_SET_UPDATE(1U) ++ ++#define S_CAL_UPDATE 23 ++#define V_CAL_UPDATE(x) ((x) << S_CAL_UPDATE) ++#define F_CAL_UPDATE V_CAL_UPDATE(1U) ++ ++#define S_CAL_BUSY 22 ++#define V_CAL_BUSY(x) ((x) << S_CAL_BUSY) ++#define F_CAL_BUSY V_CAL_BUSY(1U) ++ ++#define S_CAL_ERROR 21 ++#define V_CAL_ERROR(x) ((x) << S_CAL_ERROR) ++#define F_CAL_ERROR V_CAL_ERROR(1U) ++ ++#define S_SGL_CAL_EN 20 ++#define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN) ++#define F_SGL_CAL_EN V_SGL_CAL_EN(1U) ++ ++#define S_IMP_UPD_MODE 19 ++#define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE) ++#define F_IMP_UPD_MODE V_IMP_UPD_MODE(1U) ++ ++#define S_IMP_SEL 18 ++#define V_IMP_SEL(x) ((x) << S_IMP_SEL) ++#define F_IMP_SEL V_IMP_SEL(1U) ++ ++#define S_MAN_PU 15 ++#define M_MAN_PU 0x7 ++#define V_MAN_PU(x) ((x) << S_MAN_PU) ++#define G_MAN_PU(x) (((x) >> S_MAN_PU) & M_MAN_PU) ++ ++#define S_MAN_PD 12 ++#define M_MAN_PD 0x7 ++#define V_MAN_PD(x) ((x) << S_MAN_PD) ++#define G_MAN_PD(x) (((x) >> S_MAN_PD) & M_MAN_PD) ++ ++#define S_CAL_PU 9 ++#define M_CAL_PU 0x7 ++#define V_CAL_PU(x) ((x) << S_CAL_PU) ++#define G_CAL_PU(x) (((x) >> S_CAL_PU) & M_CAL_PU) ++ ++#define S_CAL_PD 6 ++#define M_CAL_PD 0x7 ++#define V_CAL_PD(x) ((x) << S_CAL_PD) ++#define G_CAL_PD(x) (((x) >> S_CAL_PD) & M_CAL_PD) ++ ++#define S_SET_PU 3 ++#define M_SET_PU 0x7 ++#define V_SET_PU(x) ((x) << S_SET_PU) ++#define G_SET_PU(x) (((x) >> S_SET_PU) & M_SET_PU) ++ ++#define S_SET_PD 0 ++#define M_SET_PD 0x7 ++#define V_SET_PD(x) ((x) << S_SET_PD) ++#define G_SET_PD(x) (((x) >> S_SET_PD) & M_SET_PD) ++ ++#define S_CAL_IMP_UPD 23 ++#define V_CAL_IMP_UPD(x) ((x) << S_CAL_IMP_UPD) ++#define F_CAL_IMP_UPD V_CAL_IMP_UPD(1U) + + #define A_MC5_DB_CONFIG 0x704 ++ ++#define S_TMCFGWRLOCK 31 ++#define V_TMCFGWRLOCK(x) ((x) << S_TMCFGWRLOCK) ++#define F_TMCFGWRLOCK V_TMCFGWRLOCK(1U) + + #define S_TMTYPEHI 30 + #define V_TMTYPEHI(x) ((x) << S_TMTYPEHI) +@@ -1997,10 +6552,41 @@ + #define V_TMTYPE(x) ((x) << S_TMTYPE) + #define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE) + ++#define S_TMPARTCOUNT 24 ++#define M_TMPARTCOUNT 0x3 ++#define V_TMPARTCOUNT(x) ((x) << S_TMPARTCOUNT) ++#define G_TMPARTCOUNT(x) (((x) >> S_TMPARTCOUNT) & M_TMPARTCOUNT) ++ ++#define S_NLIP 18 ++#define M_NLIP 0x3f ++#define V_NLIP(x) ((x) << S_NLIP) ++#define G_NLIP(x) (((x) >> S_NLIP) & M_NLIP) ++ + #define S_COMPEN 17 + #define V_COMPEN(x) ((x) << S_COMPEN) + #define F_COMPEN V_COMPEN(1U) + ++#define S_BUILD 16 ++#define V_BUILD(x) ((x) << S_BUILD) ++#define F_BUILD V_BUILD(1U) ++ ++#define S_FILTEREN 11 ++#define V_FILTEREN(x) ((x) << S_FILTEREN) ++#define F_FILTEREN V_FILTEREN(1U) ++ ++#define S_CLIPUPDATE 10 ++#define V_CLIPUPDATE(x) ((x) << S_CLIPUPDATE) ++#define F_CLIPUPDATE V_CLIPUPDATE(1U) ++ ++#define S_TM_IO_PDOWN 9 ++#define V_TM_IO_PDOWN(x) ((x) << S_TM_IO_PDOWN) ++#define F_TM_IO_PDOWN V_TM_IO_PDOWN(1U) ++ ++#define S_SYNMODE 7 ++#define M_SYNMODE 0x3 ++#define V_SYNMODE(x) ((x) << S_SYNMODE) ++#define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE) ++ + #define S_PRTYEN 6 + #define V_PRTYEN(x) ((x) << S_PRTYEN) + #define F_PRTYEN V_PRTYEN(1U) +@@ -2013,6 +6599,10 @@ + #define V_DBGIEN(x) ((x) << S_DBGIEN) + #define F_DBGIEN V_DBGIEN(1U) + ++#define S_TCMCFGOVR 3 ++#define V_TCMCFGOVR(x) ((x) << S_TCMCFGOVR) ++#define F_TCMCFGOVR V_TCMCFGOVR(1U) ++ + #define S_TMRDY 2 + #define V_TMRDY(x) ((x) << S_TMRDY) + #define F_TMRDY V_TMRDY(1U) +@@ -2025,31 +6615,122 @@ + #define V_TMMODE(x) ((x) << S_TMMODE) + #define F_TMMODE V_TMMODE(1U) + +-#define F_TMMODE V_TMMODE(1U) ++#define A_MC5_MISC 0x708 ++ ++#define S_LIP_CMP_UNAVAILABLE 0 ++#define M_LIP_CMP_UNAVAILABLE 0xf ++#define V_LIP_CMP_UNAVAILABLE(x) ((x) << S_LIP_CMP_UNAVAILABLE) ++#define G_LIP_CMP_UNAVAILABLE(x) (((x) >> S_LIP_CMP_UNAVAILABLE) & M_LIP_CMP_UNAVAILABLE) + + #define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c + ++#define S_RTINDX 0 ++#define M_RTINDX 0x3fffff ++#define V_RTINDX(x) ((x) << S_RTINDX) ++#define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX) ++ + #define A_MC5_DB_FILTER_TABLE 0x710 + ++#define S_SRINDX 0 ++#define M_SRINDX 0x3fffff ++#define V_SRINDX(x) ((x) << S_SRINDX) ++#define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX) ++ + #define A_MC5_DB_SERVER_INDEX 0x714 +- ++#define A_MC5_DB_LIP_RAM_ADDR 0x718 ++ ++#define S_RAMWR 8 ++#define V_RAMWR(x) ((x) << S_RAMWR) ++#define F_RAMWR V_RAMWR(1U) ++ ++#define S_RAMADDR 0 ++#define M_RAMADDR 0x3f ++#define V_RAMADDR(x) ((x) << S_RAMADDR) ++#define G_RAMADDR(x) (((x) >> S_RAMADDR) & M_RAMADDR) ++ ++#define A_MC5_DB_LIP_RAM_DATA 0x71c + #define A_MC5_DB_RSP_LATENCY 0x720 + + #define S_RDLAT 16 + #define M_RDLAT 0x1f + #define V_RDLAT(x) ((x) << S_RDLAT) ++#define G_RDLAT(x) (((x) >> S_RDLAT) & M_RDLAT) + + #define S_LRNLAT 8 + #define M_LRNLAT 0x1f + #define V_LRNLAT(x) ((x) << S_LRNLAT) ++#define G_LRNLAT(x) (((x) >> S_LRNLAT) & M_LRNLAT) + + #define S_SRCHLAT 0 + #define M_SRCHLAT 0x1f + #define V_SRCHLAT(x) ((x) << S_SRCHLAT) ++#define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT) ++ ++#define A_MC5_DB_PARITY_LATENCY 0x724 ++ ++#define S_PARLAT 0 ++#define M_PARLAT 0xf ++#define V_PARLAT(x) ((x) << S_PARLAT) ++#define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT) ++ ++#define A_MC5_DB_WR_LRN_VERIFY 0x728 ++ ++#define S_VWVEREN 2 ++#define V_VWVEREN(x) ((x) << S_VWVEREN) ++#define F_VWVEREN V_VWVEREN(1U) ++ ++#define S_LRNVEREN 1 ++#define V_LRNVEREN(x) ((x) << S_LRNVEREN) ++#define F_LRNVEREN V_LRNVEREN(1U) ++ ++#define S_POVEREN 0 ++#define V_POVEREN(x) ((x) << S_POVEREN) ++#define F_POVEREN V_POVEREN(1U) + + #define A_MC5_DB_PART_ID_INDEX 0x72c + ++#define S_IDINDEX 0 ++#define M_IDINDEX 0xf ++#define V_IDINDEX(x) ((x) << S_IDINDEX) ++#define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX) ++ ++#define A_MC5_DB_RESET_MAX 0x730 ++ ++#define S_RSTMAX 0 ++#define M_RSTMAX 0xf ++#define V_RSTMAX(x) ((x) << S_RSTMAX) ++#define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX) ++ ++#define A_MC5_DB_ACT_CNT 0x734 ++ ++#define S_ACTCNT 0 ++#define M_ACTCNT 0xfffff ++#define V_ACTCNT(x) ((x) << S_ACTCNT) ++#define G_ACTCNT(x) (((x) >> S_ACTCNT) & M_ACTCNT) ++ ++#define A_MC5_DB_CLIP_MAP 0x738 ++ ++#define S_CLIPMAPOP 31 ++#define V_CLIPMAPOP(x) ((x) << S_CLIPMAPOP) ++#define F_CLIPMAPOP V_CLIPMAPOP(1U) ++ ++#define S_CLIPMAPVAL 16 ++#define M_CLIPMAPVAL 0x3f ++#define V_CLIPMAPVAL(x) ((x) << S_CLIPMAPVAL) ++#define G_CLIPMAPVAL(x) (((x) >> S_CLIPMAPVAL) & M_CLIPMAPVAL) ++ ++#define S_CLIPMAPADDR 0 ++#define M_CLIPMAPADDR 0x3f ++#define V_CLIPMAPADDR(x) ((x) << S_CLIPMAPADDR) ++#define G_CLIPMAPADDR(x) (((x) >> S_CLIPMAPADDR) & M_CLIPMAPADDR) ++ ++#define A_MC5_DB_SIZE 0x73c + #define A_MC5_DB_INT_ENABLE 0x740 ++ ++#define S_MSGSEL 28 ++#define M_MSGSEL 0xf ++#define V_MSGSEL(x) ((x) << S_MSGSEL) ++#define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL) + + #define S_DELACTEMPTY 18 + #define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY) +@@ -2067,6 +6748,18 @@ + #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD) + #define F_UNKNOWNCMD V_UNKNOWNCMD(1U) + ++#define S_SYNCOOKIEOFF 11 ++#define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF) ++#define F_SYNCOOKIEOFF V_SYNCOOKIEOFF(1U) ++ ++#define S_SYNCOOKIEBAD 10 ++#define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD) ++#define F_SYNCOOKIEBAD V_SYNCOOKIEBAD(1U) ++ ++#define S_SYNCOOKIE 9 ++#define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE) ++#define F_SYNCOOKIE V_SYNCOOKIE(1U) ++ + #define S_NFASRCHFAIL 8 + #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL) + #define F_NFASRCHFAIL V_NFASRCHFAIL(1U) +@@ -2079,63 +6772,269 @@ + #define V_PARITYERR(x) ((x) << S_PARITYERR) + #define F_PARITYERR V_PARITYERR(1U) + ++#define S_LIPMISS 5 ++#define V_LIPMISS(x) ((x) << S_LIPMISS) ++#define F_LIPMISS V_LIPMISS(1U) ++ ++#define S_LIP0 4 ++#define V_LIP0(x) ((x) << S_LIP0) ++#define F_LIP0 V_LIP0(1U) ++ ++#define S_MISS 3 ++#define V_MISS(x) ((x) << S_MISS) ++#define F_MISS V_MISS(1U) ++ ++#define S_ROUTINGHIT 2 ++#define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT) ++#define F_ROUTINGHIT V_ROUTINGHIT(1U) ++ ++#define S_ACTIVEHIT 1 ++#define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT) ++#define F_ACTIVEHIT V_ACTIVEHIT(1U) ++ ++#define S_ACTIVEOUTHIT 0 ++#define V_ACTIVEOUTHIT(x) ((x) << S_ACTIVEOUTHIT) ++#define F_ACTIVEOUTHIT V_ACTIVEOUTHIT(1U) ++ + #define A_MC5_DB_INT_CAUSE 0x744 ++#define A_MC5_DB_INT_TID 0x748 ++ ++#define S_INTTID 0 ++#define M_INTTID 0xfffff ++#define V_INTTID(x) ((x) << S_INTTID) ++#define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID) ++ ++#define A_MC5_DB_INT_PTID 0x74c ++ ++#define S_INTPTID 0 ++#define M_INTPTID 0xfffff ++#define V_INTPTID(x) ((x) << S_INTPTID) ++#define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID) + + #define A_MC5_DB_DBGI_CONFIG 0x774 + ++#define S_WRREQSIZE 22 ++#define M_WRREQSIZE 0x3ff ++#define V_WRREQSIZE(x) ((x) << S_WRREQSIZE) ++#define G_WRREQSIZE(x) (((x) >> S_WRREQSIZE) & M_WRREQSIZE) ++ ++#define S_SADRSEL 4 ++#define V_SADRSEL(x) ((x) << S_SADRSEL) ++#define F_SADRSEL V_SADRSEL(1U) ++ ++#define S_CMDMODE 0 ++#define M_CMDMODE 0x7 ++#define V_CMDMODE(x) ((x) << S_CMDMODE) ++#define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE) ++ + #define A_MC5_DB_DBGI_REQ_CMD 0x778 + ++#define S_MBUSCMD 0 ++#define M_MBUSCMD 0xf ++#define V_MBUSCMD(x) ((x) << S_MBUSCMD) ++#define G_MBUSCMD(x) (((x) >> S_MBUSCMD) & M_MBUSCMD) ++ ++#define S_IDTCMDHI 11 ++#define M_IDTCMDHI 0x7 ++#define V_IDTCMDHI(x) ((x) << S_IDTCMDHI) ++#define G_IDTCMDHI(x) (((x) >> S_IDTCMDHI) & M_IDTCMDHI) ++ ++#define S_IDTCMDLO 0 ++#define M_IDTCMDLO 0xf ++#define V_IDTCMDLO(x) ((x) << S_IDTCMDLO) ++#define G_IDTCMDLO(x) (((x) >> S_IDTCMDLO) & M_IDTCMDLO) ++ ++#define S_IDTCMD 0 ++#define M_IDTCMD 0xfffff ++#define V_IDTCMD(x) ((x) << S_IDTCMD) ++#define G_IDTCMD(x) (((x) >> S_IDTCMD) & M_IDTCMD) ++ ++#define S_LCMDB 16 ++#define M_LCMDB 0x7ff ++#define V_LCMDB(x) ((x) << S_LCMDB) ++#define G_LCMDB(x) (((x) >> S_LCMDB) & M_LCMDB) ++ ++#define S_LCMDA 0 ++#define M_LCMDA 0x7ff ++#define V_LCMDA(x) ((x) << S_LCMDA) ++#define G_LCMDA(x) (((x) >> S_LCMDA) & M_LCMDA) ++ + #define A_MC5_DB_DBGI_REQ_ADDR0 0x77c +- + #define A_MC5_DB_DBGI_REQ_ADDR1 0x780 +- + #define A_MC5_DB_DBGI_REQ_ADDR2 0x784 + ++#define S_DBGIREQADRHI 0 ++#define M_DBGIREQADRHI 0xff ++#define V_DBGIREQADRHI(x) ((x) << S_DBGIREQADRHI) ++#define G_DBGIREQADRHI(x) (((x) >> S_DBGIREQADRHI) & M_DBGIREQADRHI) ++ + #define A_MC5_DB_DBGI_REQ_DATA0 0x788 +- + #define A_MC5_DB_DBGI_REQ_DATA1 0x78c +- + #define A_MC5_DB_DBGI_REQ_DATA2 0x790 ++#define A_MC5_DB_DBGI_REQ_DATA3 0x794 ++#define A_MC5_DB_DBGI_REQ_DATA4 0x798 ++ ++#define S_DBGIREQDATA4 0 ++#define M_DBGIREQDATA4 0xffff ++#define V_DBGIREQDATA4(x) ((x) << S_DBGIREQDATA4) ++#define G_DBGIREQDATA4(x) (((x) >> S_DBGIREQDATA4) & M_DBGIREQDATA4) ++ ++#define A_MC5_DB_DBGI_REQ_MASK0 0x79c ++#define A_MC5_DB_DBGI_REQ_MASK1 0x7a0 ++#define A_MC5_DB_DBGI_REQ_MASK2 0x7a4 ++#define A_MC5_DB_DBGI_REQ_MASK3 0x7a8 ++#define A_MC5_DB_DBGI_REQ_MASK4 0x7ac ++ ++#define S_DBGIREQMSK4 0 ++#define M_DBGIREQMSK4 0xffff ++#define V_DBGIREQMSK4(x) ((x) << S_DBGIREQMSK4) ++#define G_DBGIREQMSK4(x) (((x) >> S_DBGIREQMSK4) & M_DBGIREQMSK4) + + #define A_MC5_DB_DBGI_RSP_STATUS 0x7b0 ++ ++#define S_DBGIRSPMSG 8 ++#define M_DBGIRSPMSG 0xf ++#define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG) ++#define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG) ++ ++#define S_DBGIRSPMSGVLD 2 ++#define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD) ++#define F_DBGIRSPMSGVLD V_DBGIRSPMSGVLD(1U) ++ ++#define S_DBGIRSPHIT 1 ++#define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT) ++#define F_DBGIRSPHIT V_DBGIRSPHIT(1U) + + #define S_DBGIRSPVALID 0 + #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID) + #define F_DBGIRSPVALID V_DBGIRSPVALID(1U) + + #define A_MC5_DB_DBGI_RSP_DATA0 0x7b4 +- + #define A_MC5_DB_DBGI_RSP_DATA1 0x7b8 +- + #define A_MC5_DB_DBGI_RSP_DATA2 0x7bc ++#define A_MC5_DB_DBGI_RSP_DATA3 0x7c0 ++#define A_MC5_DB_DBGI_RSP_DATA4 0x7c4 ++ ++#define S_DBGIRSPDATA3 0 ++#define M_DBGIRSPDATA3 0xffff ++#define V_DBGIRSPDATA3(x) ((x) << S_DBGIRSPDATA3) ++#define G_DBGIRSPDATA3(x) (((x) >> S_DBGIRSPDATA3) & M_DBGIRSPDATA3) ++ ++#define A_MC5_DB_DBGI_RSP_LAST_CMD 0x7c8 ++ ++#define S_LASTCMDB 16 ++#define M_LASTCMDB 0x7ff ++#define V_LASTCMDB(x) ((x) << S_LASTCMDB) ++#define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB) ++ ++#define S_LASTCMDA 0 ++#define M_LASTCMDA 0x7ff ++#define V_LASTCMDA(x) ((x) << S_LASTCMDA) ++#define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA) + + #define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc + ++#define S_PO_DWR 0 ++#define M_PO_DWR 0xfffff ++#define V_PO_DWR(x) ((x) << S_PO_DWR) ++#define G_PO_DWR(x) (((x) >> S_PO_DWR) & M_PO_DWR) ++ + #define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0 + ++#define S_PO_MWR 0 ++#define M_PO_MWR 0xfffff ++#define V_PO_MWR(x) ((x) << S_PO_MWR) ++#define G_PO_MWR(x) (((x) >> S_PO_MWR) & M_PO_MWR) ++ + #define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4 + ++#define S_AO_SRCH 0 ++#define M_AO_SRCH 0xfffff ++#define V_AO_SRCH(x) ((x) << S_AO_SRCH) ++#define G_AO_SRCH(x) (((x) >> S_AO_SRCH) & M_AO_SRCH) ++ + #define A_MC5_DB_AOPEN_LRN_CMD 0x7d8 + ++#define S_AO_LRN 0 ++#define M_AO_LRN 0xfffff ++#define V_AO_LRN(x) ((x) << S_AO_LRN) ++#define G_AO_LRN(x) (((x) >> S_AO_LRN) & M_AO_LRN) ++ + #define A_MC5_DB_SYN_SRCH_CMD 0x7dc + ++#define S_SYN_SRCH 0 ++#define M_SYN_SRCH 0xfffff ++#define V_SYN_SRCH(x) ((x) << S_SYN_SRCH) ++#define G_SYN_SRCH(x) (((x) >> S_SYN_SRCH) & M_SYN_SRCH) ++ + #define A_MC5_DB_SYN_LRN_CMD 0x7e0 + ++#define S_SYN_LRN 0 ++#define M_SYN_LRN 0xfffff ++#define V_SYN_LRN(x) ((x) << S_SYN_LRN) ++#define G_SYN_LRN(x) (((x) >> S_SYN_LRN) & M_SYN_LRN) ++ + #define A_MC5_DB_ACK_SRCH_CMD 0x7e4 + ++#define S_ACK_SRCH 0 ++#define M_ACK_SRCH 0xfffff ++#define V_ACK_SRCH(x) ((x) << S_ACK_SRCH) ++#define G_ACK_SRCH(x) (((x) >> S_ACK_SRCH) & M_ACK_SRCH) ++ + #define A_MC5_DB_ACK_LRN_CMD 0x7e8 + ++#define S_ACK_LRN 0 ++#define M_ACK_LRN 0xfffff ++#define V_ACK_LRN(x) ((x) << S_ACK_LRN) ++#define G_ACK_LRN(x) (((x) >> S_ACK_LRN) & M_ACK_LRN) ++ + #define A_MC5_DB_ILOOKUP_CMD 0x7ec + ++#define S_I_SRCH 0 ++#define M_I_SRCH 0xfffff ++#define V_I_SRCH(x) ((x) << S_I_SRCH) ++#define G_I_SRCH(x) (((x) >> S_I_SRCH) & M_I_SRCH) ++ + #define A_MC5_DB_ELOOKUP_CMD 0x7f0 + ++#define S_E_SRCH 0 ++#define M_E_SRCH 0xfffff ++#define V_E_SRCH(x) ((x) << S_E_SRCH) ++#define G_E_SRCH(x) (((x) >> S_E_SRCH) & M_E_SRCH) ++ + #define A_MC5_DB_DATA_WRITE_CMD 0x7f4 + ++#define S_WRITE 0 ++#define M_WRITE 0xfffff ++#define V_WRITE(x) ((x) << S_WRITE) ++#define G_WRITE(x) (((x) >> S_WRITE) & M_WRITE) ++ + #define A_MC5_DB_DATA_READ_CMD 0x7f8 + ++#define S_READCMD 0 ++#define M_READCMD 0xfffff ++#define V_READCMD(x) ((x) << S_READCMD) ++#define G_READCMD(x) (((x) >> S_READCMD) & M_READCMD) ++ ++#define A_MC5_DB_MASK_WRITE_CMD 0x7fc ++ ++#define S_MASKWR 0 ++#define M_MASKWR 0xffff ++#define V_MASKWR(x) ((x) << S_MASKWR) ++#define G_MASKWR(x) (((x) >> S_MASKWR) & M_MASKWR) ++ ++/* registers for module XGMAC0_0 */ + #define XGMAC0_0_BASE_ADDR 0x800 + + #define A_XGM_TX_CTRL 0x800 ++ ++#define S_SENDPAUSE 2 ++#define V_SENDPAUSE(x) ((x) << S_SENDPAUSE) ++#define F_SENDPAUSE V_SENDPAUSE(1U) ++ ++#define S_SENDZEROPAUSE 1 ++#define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE) ++#define F_SENDZEROPAUSE V_SENDZEROPAUSE(1U) + + #define S_TXEN 0 + #define V_TXEN(x) ((x) << S_TXEN) +@@ -2143,12 +7042,26 @@ + + #define A_XGM_TX_CFG 0x804 + ++#define S_CFGCLKSPEED 2 ++#define M_CFGCLKSPEED 0x7 ++#define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED) ++#define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED) ++ ++#define S_STRETCHMODE 1 ++#define V_STRETCHMODE(x) ((x) << S_STRETCHMODE) ++#define F_STRETCHMODE V_STRETCHMODE(1U) ++ + #define S_TXPAUSEEN 0 + #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN) + #define F_TXPAUSEEN V_TXPAUSEEN(1U) + + #define A_XGM_TX_PAUSE_QUANTA 0x808 + ++#define S_TXPAUSEQUANTA 0 ++#define M_TXPAUSEQUANTA 0xffff ++#define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA) ++#define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA) ++ + #define A_XGM_RX_CTRL 0x80c + + #define S_RXEN 0 +@@ -2157,6 +7070,18 @@ + + #define A_XGM_RX_CFG 0x810 + ++#define S_CON802_3PREAMBLE 12 ++#define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE) ++#define F_CON802_3PREAMBLE V_CON802_3PREAMBLE(1U) ++ ++#define S_ENNON802_3PREAMBLE 11 ++#define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE) ++#define F_ENNON802_3PREAMBLE V_ENNON802_3PREAMBLE(1U) ++ ++#define S_COPYPREAMBLE 10 ++#define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE) ++#define F_COPYPREAMBLE V_COPYPREAMBLE(1U) ++ + #define S_DISPAUSEFRAMES 9 + #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES) + #define F_DISPAUSEFRAMES V_DISPAUSEFRAMES(1U) +@@ -2173,65 +7098,177 @@ + #define V_RMFCS(x) ((x) << S_RMFCS) + #define F_RMFCS V_RMFCS(1U) + ++#define S_DISNONVLAN 5 ++#define V_DISNONVLAN(x) ((x) << S_DISNONVLAN) ++#define F_DISNONVLAN V_DISNONVLAN(1U) ++ ++#define S_ENEXTMATCH 4 ++#define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH) ++#define F_ENEXTMATCH V_ENEXTMATCH(1U) ++ ++#define S_ENHASHUCAST 3 ++#define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST) ++#define F_ENHASHUCAST V_ENHASHUCAST(1U) ++ + #define S_ENHASHMCAST 2 + #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST) + #define F_ENHASHMCAST V_ENHASHMCAST(1U) + ++#define S_DISBCAST 1 ++#define V_DISBCAST(x) ((x) << S_DISBCAST) ++#define F_DISBCAST V_DISBCAST(1U) ++ + #define S_COPYALLFRAMES 0 + #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES) + #define F_COPYALLFRAMES V_COPYALLFRAMES(1U) + +-#define S_DISBCAST 1 +-#define V_DISBCAST(x) ((x) << S_DISBCAST) +-#define F_DISBCAST V_DISBCAST(1U) +- + #define A_XGM_RX_HASH_LOW 0x814 +- + #define A_XGM_RX_HASH_HIGH 0x818 +- + #define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c +- + #define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820 + ++#define S_ADDRESS_HIGH 0 ++#define M_ADDRESS_HIGH 0xffff ++#define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH) ++#define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH) ++ + #define A_XGM_RX_EXACT_MATCH_LOW_2 0x824 +- ++#define A_XGM_RX_EXACT_MATCH_HIGH_2 0x828 + #define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c +- ++#define A_XGM_RX_EXACT_MATCH_HIGH_3 0x830 + #define A_XGM_RX_EXACT_MATCH_LOW_4 0x834 +- ++#define A_XGM_RX_EXACT_MATCH_HIGH_4 0x838 + #define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c +- ++#define A_XGM_RX_EXACT_MATCH_HIGH_5 0x840 + #define A_XGM_RX_EXACT_MATCH_LOW_6 0x844 +- ++#define A_XGM_RX_EXACT_MATCH_HIGH_6 0x848 + #define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c +- ++#define A_XGM_RX_EXACT_MATCH_HIGH_7 0x850 + #define A_XGM_RX_EXACT_MATCH_LOW_8 0x854 ++#define A_XGM_RX_EXACT_MATCH_HIGH_8 0x858 ++#define A_XGM_RX_TYPE_MATCH_1 0x85c ++ ++#define S_ENTYPEMATCH 31 ++#define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH) ++#define F_ENTYPEMATCH V_ENTYPEMATCH(1U) ++ ++#define S_TYPE 0 ++#define M_TYPE 0xffff ++#define V_TYPE(x) ((x) << S_TYPE) ++#define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE) ++ ++#define A_XGM_RX_TYPE_MATCH_2 0x860 ++#define A_XGM_RX_TYPE_MATCH_3 0x864 ++#define A_XGM_RX_TYPE_MATCH_4 0x868 ++#define A_XGM_INT_STATUS 0x86c ++ ++#define S_XGMIIEXTINT 10 ++#define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT) ++#define F_XGMIIEXTINT V_XGMIIEXTINT(1U) ++ ++#define S_LINKFAULTCHANGE 9 ++#define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE) ++#define F_LINKFAULTCHANGE V_LINKFAULTCHANGE(1U) ++ ++#define S_PHYFRAMECOMPLETE 8 ++#define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE) ++#define F_PHYFRAMECOMPLETE V_PHYFRAMECOMPLETE(1U) ++ ++#define S_PAUSEFRAMETXMT 7 ++#define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT) ++#define F_PAUSEFRAMETXMT V_PAUSEFRAMETXMT(1U) ++ ++#define S_PAUSECNTRTIMEOUT 6 ++#define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT) ++#define F_PAUSECNTRTIMEOUT V_PAUSECNTRTIMEOUT(1U) ++ ++#define S_NON0PAUSERCVD 5 ++#define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD) ++#define F_NON0PAUSERCVD V_NON0PAUSERCVD(1U) ++ ++#define S_STATOFLOW 4 ++#define V_STATOFLOW(x) ((x) << S_STATOFLOW) ++#define F_STATOFLOW V_STATOFLOW(1U) ++ ++#define S_TXERRFIFO 3 ++#define V_TXERRFIFO(x) ((x) << S_TXERRFIFO) ++#define F_TXERRFIFO V_TXERRFIFO(1U) ++ ++#define S_TXUFLOW 2 ++#define V_TXUFLOW(x) ((x) << S_TXUFLOW) ++#define F_TXUFLOW V_TXUFLOW(1U) ++ ++#define S_FRAMETXMT 1 ++#define V_FRAMETXMT(x) ((x) << S_FRAMETXMT) ++#define F_FRAMETXMT V_FRAMETXMT(1U) ++ ++#define S_FRAMERCVD 0 ++#define V_FRAMERCVD(x) ((x) << S_FRAMERCVD) ++#define F_FRAMERCVD V_FRAMERCVD(1U) ++ ++#define A_XGM_XGM_INT_MASK 0x870 ++#define A_XGM_XGM_INT_ENABLE 0x874 ++#define A_XGM_XGM_INT_DISABLE 0x878 ++#define A_XGM_TX_PAUSE_TIMER 0x87c ++ ++#define S_CURPAUSETIMER 0 ++#define M_CURPAUSETIMER 0xffff ++#define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER) ++#define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER) + + #define A_XGM_STAT_CTRL 0x880 ++ ++#define S_READSNPSHOT 4 ++#define V_READSNPSHOT(x) ((x) << S_READSNPSHOT) ++#define F_READSNPSHOT V_READSNPSHOT(1U) ++ ++#define S_TAKESNPSHOT 3 ++#define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT) ++#define F_TAKESNPSHOT V_TAKESNPSHOT(1U) + + #define S_CLRSTATS 2 + #define V_CLRSTATS(x) ((x) << S_CLRSTATS) + #define F_CLRSTATS V_CLRSTATS(1U) + ++#define S_INCRSTATS 1 ++#define V_INCRSTATS(x) ((x) << S_INCRSTATS) ++#define F_INCRSTATS V_INCRSTATS(1U) ++ ++#define S_ENTESTMODEWR 0 ++#define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR) ++#define F_ENTESTMODEWR V_ENTESTMODEWR(1U) ++ + #define A_XGM_RXFIFO_CFG 0x884 + + #define S_RXFIFO_EMPTY 31 + #define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY) + #define F_RXFIFO_EMPTY V_RXFIFO_EMPTY(1U) + ++#define S_RXFIFO_FULL 30 ++#define V_RXFIFO_FULL(x) ((x) << S_RXFIFO_FULL) ++#define F_RXFIFO_FULL V_RXFIFO_FULL(1U) ++ + #define S_RXFIFOPAUSEHWM 17 + #define M_RXFIFOPAUSEHWM 0xfff +- + #define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM) +- + #define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM) + + #define S_RXFIFOPAUSELWM 5 + #define M_RXFIFOPAUSELWM 0xfff +- + #define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM) +- + #define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM) ++ ++#define S_FORCEDPAUSE 4 ++#define V_FORCEDPAUSE(x) ((x) << S_FORCEDPAUSE) ++#define F_FORCEDPAUSE V_FORCEDPAUSE(1U) ++ ++#define S_EXTERNLOOPBACK 3 ++#define V_EXTERNLOOPBACK(x) ((x) << S_EXTERNLOOPBACK) ++#define F_EXTERNLOOPBACK V_EXTERNLOOPBACK(1U) ++ ++#define S_RXBYTESWAP 2 ++#define V_RXBYTESWAP(x) ((x) << S_RXBYTESWAP) ++#define F_RXBYTESWAP V_RXBYTESWAP(1U) + + #define S_RXSTRFRWRD 1 + #define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD) +@@ -2243,9 +7280,21 @@ + + #define A_XGM_TXFIFO_CFG 0x888 + ++#define S_TXFIFO_EMPTY 31 ++#define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY) ++#define F_TXFIFO_EMPTY V_TXFIFO_EMPTY(1U) ++ ++#define S_TXFIFO_FULL 30 ++#define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL) ++#define F_TXFIFO_FULL V_TXFIFO_FULL(1U) ++ + #define S_UNDERUNFIX 22 + #define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX) + #define F_UNDERUNFIX V_UNDERUNFIX(1U) ++ ++#define S_ENDROPPKT 21 ++#define V_ENDROPPKT(x) ((x) << S_ENDROPPKT) ++#define F_ENDROPPKT V_ENDROPPKT(1U) + + #define S_TXIPG 13 + #define M_TXIPG 0xff +@@ -2254,20 +7303,93 @@ + + #define S_TXFIFOTHRESH 4 + #define M_TXFIFOTHRESH 0x1ff +- + #define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH) +- +-#define S_ENDROPPKT 21 +-#define V_ENDROPPKT(x) ((x) << S_ENDROPPKT) +-#define F_ENDROPPKT V_ENDROPPKT(1U) ++#define G_TXFIFOTHRESH(x) (((x) >> S_TXFIFOTHRESH) & M_TXFIFOTHRESH) ++ ++#define S_INTERNLOOPBACK 3 ++#define V_INTERNLOOPBACK(x) ((x) << S_INTERNLOOPBACK) ++#define F_INTERNLOOPBACK V_INTERNLOOPBACK(1U) ++ ++#define S_TXBYTESWAP 2 ++#define V_TXBYTESWAP(x) ((x) << S_TXBYTESWAP) ++#define F_TXBYTESWAP V_TXBYTESWAP(1U) ++ ++#define S_DISCRC 1 ++#define V_DISCRC(x) ((x) << S_DISCRC) ++#define F_DISCRC V_DISCRC(1U) ++ ++#define S_DISPREAMBLE 0 ++#define V_DISPREAMBLE(x) ((x) << S_DISPREAMBLE) ++#define F_DISPREAMBLE V_DISPREAMBLE(1U) ++ ++#define A_XGM_SLOW_TIMER 0x88c ++ ++#define S_PAUSESLOWTIMEREN 31 ++#define V_PAUSESLOWTIMEREN(x) ((x) << S_PAUSESLOWTIMEREN) ++#define F_PAUSESLOWTIMEREN V_PAUSESLOWTIMEREN(1U) ++ ++#define S_PAUSESLOWTIMER 0 ++#define M_PAUSESLOWTIMER 0xfffff ++#define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER) ++#define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER) ++ ++#define A_XGM_PAUSE_TIMER 0x890 ++ ++#define S_PAUSETIMER 0 ++#define M_PAUSETIMER 0xfffff ++#define V_PAUSETIMER(x) ((x) << S_PAUSETIMER) ++#define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER) + + #define A_XGM_SERDES_CTRL 0x890 +-#define A_XGM_SERDES_CTRL0 0x8e0 ++ ++#define S_SERDESEN 25 ++#define V_SERDESEN(x) ((x) << S_SERDESEN) ++#define F_SERDESEN V_SERDESEN(1U) + + #define S_SERDESRESET_ 24 + #define V_SERDESRESET_(x) ((x) << S_SERDESRESET_) + #define F_SERDESRESET_ V_SERDESRESET_(1U) + ++#define S_CMURANGE 21 ++#define M_CMURANGE 0x7 ++#define V_CMURANGE(x) ((x) << S_CMURANGE) ++#define G_CMURANGE(x) (((x) >> S_CMURANGE) & M_CMURANGE) ++ ++#define S_BGENB 20 ++#define V_BGENB(x) ((x) << S_BGENB) ++#define F_BGENB V_BGENB(1U) ++ ++#define S_ENSKPDROP 19 ++#define V_ENSKPDROP(x) ((x) << S_ENSKPDROP) ++#define F_ENSKPDROP V_ENSKPDROP(1U) ++ ++#define S_ENCOMMA 18 ++#define V_ENCOMMA(x) ((x) << S_ENCOMMA) ++#define F_ENCOMMA V_ENCOMMA(1U) ++ ++#define S_EN8B10B 17 ++#define V_EN8B10B(x) ((x) << S_EN8B10B) ++#define F_EN8B10B V_EN8B10B(1U) ++ ++#define S_ENELBUF 16 ++#define V_ENELBUF(x) ((x) << S_ENELBUF) ++#define F_ENELBUF V_ENELBUF(1U) ++ ++#define S_GAIN 11 ++#define M_GAIN 0x1f ++#define V_GAIN(x) ((x) << S_GAIN) ++#define G_GAIN(x) (((x) >> S_GAIN) & M_GAIN) ++ ++#define S_BANDGAP 7 ++#define M_BANDGAP 0xf ++#define V_BANDGAP(x) ((x) << S_BANDGAP) ++#define G_BANDGAP(x) (((x) >> S_BANDGAP) & M_BANDGAP) ++ ++#define S_LPBKEN 5 ++#define M_LPBKEN 0x3 ++#define V_LPBKEN(x) ((x) << S_LPBKEN) ++#define G_LPBKEN(x) (((x) >> S_LPBKEN) & M_LPBKEN) ++ + #define S_RXENABLE 4 + #define V_RXENABLE(x) ((x) << S_RXENABLE) + #define F_RXENABLE V_RXENABLE(1U) +@@ -2276,9 +7398,37 @@ + #define V_TXENABLE(x) ((x) << S_TXENABLE) + #define F_TXENABLE V_TXENABLE(1U) + +-#define A_XGM_PAUSE_TIMER 0x890 ++#define A_XGM_XAUI_PCS_TEST 0x894 ++ ++#define S_TESTPATTERN 1 ++#define M_TESTPATTERN 0x3 ++#define V_TESTPATTERN(x) ((x) << S_TESTPATTERN) ++#define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN) ++ ++#define S_ENTEST 0 ++#define V_ENTEST(x) ((x) << S_ENTEST) ++#define F_ENTEST V_ENTEST(1U) ++ ++#define A_XGM_RGMII_CTRL 0x898 ++ ++#define S_PHALIGNFIFOTHRESH 1 ++#define M_PHALIGNFIFOTHRESH 0x3 ++#define V_PHALIGNFIFOTHRESH(x) ((x) << S_PHALIGNFIFOTHRESH) ++#define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH) ++ ++#define S_TXCLK90SHIFT 0 ++#define V_TXCLK90SHIFT(x) ((x) << S_TXCLK90SHIFT) ++#define F_TXCLK90SHIFT V_TXCLK90SHIFT(1U) + + #define A_XGM_RGMII_IMP 0x89c ++ ++#define S_CALRESET 8 ++#define V_CALRESET(x) ((x) << S_CALRESET) ++#define F_CALRESET V_CALRESET(1U) ++ ++#define S_CALUPDATE 7 ++#define V_CALUPDATE(x) ((x) << S_CALUPDATE) ++#define F_CALUPDATE V_CALUPDATE(1U) + + #define S_XGM_IMPSETUPDATE 6 + #define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE) +@@ -2287,24 +7437,14 @@ + #define S_RGMIIIMPPD 3 + #define M_RGMIIIMPPD 0x7 + #define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD) ++#define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD) + + #define S_RGMIIIMPPU 0 + #define M_RGMIIIMPPU 0x7 + #define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU) +- +-#define S_CALRESET 8 +-#define V_CALRESET(x) ((x) << S_CALRESET) +-#define F_CALRESET V_CALRESET(1U) +- +-#define S_CALUPDATE 7 +-#define V_CALUPDATE(x) ((x) << S_CALUPDATE) +-#define F_CALUPDATE V_CALUPDATE(1U) ++#define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU) + + #define A_XGM_XAUI_IMP 0x8a0 +- +-#define S_CALBUSY 31 +-#define V_CALBUSY(x) ((x) << S_CALBUSY) +-#define F_CALBUSY V_CALBUSY(1U) + + #define S_XGM_CALFAULT 29 + #define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT) +@@ -2318,6 +7458,19 @@ + #define S_XAUIIMP 0 + #define M_XAUIIMP 0x7 + #define V_XAUIIMP(x) ((x) << S_XAUIIMP) ++#define G_XAUIIMP(x) (((x) >> S_XAUIIMP) & M_XAUIIMP) ++ ++#define A_XGM_SERDES_BIST 0x8a4 ++ ++#define S_BISTDONE 28 ++#define M_BISTDONE 0xf ++#define V_BISTDONE(x) ((x) << S_BISTDONE) ++#define G_BISTDONE(x) (((x) >> S_BISTDONE) & M_BISTDONE) ++ ++#define S_BISTCYCLETHRESH 3 ++#define M_BISTCYCLETHRESH 0x1ffff ++#define V_BISTCYCLETHRESH(x) ((x) << S_BISTCYCLETHRESH) ++#define G_BISTCYCLETHRESH(x) (((x) >> S_BISTCYCLETHRESH) & M_BISTCYCLETHRESH) + + #define A_XGM_RX_MAX_PKT_SIZE 0x8a8 + +@@ -2326,6 +7479,14 @@ + #define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE) + #define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE) + ++#define S_RXENERRORGATHER 16 ++#define V_RXENERRORGATHER(x) ((x) << S_RXENERRORGATHER) ++#define F_RXENERRORGATHER V_RXENERRORGATHER(1U) ++ ++#define S_RXENSINGLEFLIT 15 ++#define V_RXENSINGLEFLIT(x) ((x) << S_RXENSINGLEFLIT) ++#define F_RXENSINGLEFLIT V_RXENSINGLEFLIT(1U) ++ + #define S_RXENFRAMER 14 + #define V_RXENFRAMER(x) ((x) << S_RXENFRAMER) + #define F_RXENFRAMER V_RXENFRAMER(1U) +@@ -2357,7 +7518,34 @@ + #define V_MAC_RESET_(x) ((x) << S_MAC_RESET_) + #define F_MAC_RESET_ V_MAC_RESET_(1U) + ++#define A_XGM_XAUI1G_CTRL 0x8b0 ++ ++#define S_XAUI1GLINKID 0 ++#define M_XAUI1GLINKID 0x3 ++#define V_XAUI1GLINKID(x) ((x) << S_XAUI1GLINKID) ++#define G_XAUI1GLINKID(x) (((x) >> S_XAUI1GLINKID) & M_XAUI1GLINKID) ++ ++#define A_XGM_SERDES_LANE_CTRL 0x8b4 ++ ++#define S_LANEREVERSAL 8 ++#define V_LANEREVERSAL(x) ((x) << S_LANEREVERSAL) ++#define F_LANEREVERSAL V_LANEREVERSAL(1U) ++ ++#define S_TXPOLARITY 4 ++#define M_TXPOLARITY 0xf ++#define V_TXPOLARITY(x) ((x) << S_TXPOLARITY) ++#define G_TXPOLARITY(x) (((x) >> S_TXPOLARITY) & M_TXPOLARITY) ++ ++#define S_RXPOLARITY 0 ++#define M_RXPOLARITY 0xf ++#define V_RXPOLARITY(x) ((x) << S_RXPOLARITY) ++#define G_RXPOLARITY(x) (((x) >> S_RXPOLARITY) & M_RXPOLARITY) ++ + #define A_XGM_PORT_CFG 0x8b8 ++ ++#define S_SAFESPEEDCHANGE 4 ++#define V_SAFESPEEDCHANGE(x) ((x) << S_SAFESPEEDCHANGE) ++#define F_SAFESPEEDCHANGE V_SAFESPEEDCHANGE(1U) + + #define S_CLKDIVRESET_ 3 + #define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_) +@@ -2365,24 +7553,63 @@ + + #define S_PORTSPEED 1 + #define M_PORTSPEED 0x3 +- + #define V_PORTSPEED(x) ((x) << S_PORTSPEED) ++#define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED) + + #define S_ENRGMII 0 + #define V_ENRGMII(x) ((x) << S_ENRGMII) + #define F_ENRGMII V_ENRGMII(1U) + ++#define A_XGM_EPIO_DATA0 0x8c0 ++#define A_XGM_EPIO_DATA1 0x8c4 ++#define A_XGM_EPIO_DATA2 0x8c8 ++#define A_XGM_EPIO_DATA3 0x8cc ++#define A_XGM_EPIO_OP 0x8d0 ++ ++#define S_PIO_READY 31 ++#define V_PIO_READY(x) ((x) << S_PIO_READY) ++#define F_PIO_READY V_PIO_READY(1U) ++ ++#define S_PIO_WRRD 24 ++#define V_PIO_WRRD(x) ((x) << S_PIO_WRRD) ++#define F_PIO_WRRD V_PIO_WRRD(1U) ++ ++#define S_PIO_ADDRESS 0 ++#define M_PIO_ADDRESS 0xff ++#define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS) ++#define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS) ++ + #define A_XGM_INT_ENABLE 0x8d4 ++ ++#define S_XAUIPCSDECERR 24 ++#define V_XAUIPCSDECERR(x) ((x) << S_XAUIPCSDECERR) ++#define F_XAUIPCSDECERR V_XAUIPCSDECERR(1U) ++ ++#define S_RGMIIRXFIFOOVERFLOW 23 ++#define V_RGMIIRXFIFOOVERFLOW(x) ((x) << S_RGMIIRXFIFOOVERFLOW) ++#define F_RGMIIRXFIFOOVERFLOW V_RGMIIRXFIFOOVERFLOW(1U) ++ ++#define S_RGMIIRXFIFOUNDERFLOW 22 ++#define V_RGMIIRXFIFOUNDERFLOW(x) ((x) << S_RGMIIRXFIFOUNDERFLOW) ++#define F_RGMIIRXFIFOUNDERFLOW V_RGMIIRXFIFOUNDERFLOW(1U) ++ ++#define S_RXPKTSIZEERROR 21 ++#define V_RXPKTSIZEERROR(x) ((x) << S_RXPKTSIZEERROR) ++#define F_RXPKTSIZEERROR V_RXPKTSIZEERROR(1U) ++ ++#define S_WOLPATDETECTED 20 ++#define V_WOLPATDETECTED(x) ((x) << S_WOLPATDETECTED) ++#define F_WOLPATDETECTED V_WOLPATDETECTED(1U) + + #define S_TXFIFO_PRTY_ERR 17 + #define M_TXFIFO_PRTY_ERR 0x7 +- + #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR) ++#define G_TXFIFO_PRTY_ERR(x) (((x) >> S_TXFIFO_PRTY_ERR) & M_TXFIFO_PRTY_ERR) + + #define S_RXFIFO_PRTY_ERR 14 + #define M_RXFIFO_PRTY_ERR 0x7 +- + #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR) ++#define G_RXFIFO_PRTY_ERR(x) (((x) >> S_RXFIFO_PRTY_ERR) & M_RXFIFO_PRTY_ERR) + + #define S_TXFIFO_UNDERRUN 13 + #define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN) +@@ -2392,10 +7619,15 @@ + #define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW) + #define F_RXFIFO_OVERFLOW V_RXFIFO_OVERFLOW(1U) + +-#define S_SERDES_LOS 4 +-#define M_SERDES_LOS 0xf +- +-#define V_SERDES_LOS(x) ((x) << S_SERDES_LOS) ++#define S_SERDESBISTERR 8 ++#define M_SERDESBISTERR 0xf ++#define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR) ++#define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR) ++ ++#define S_SERDESLOWSIGCHANGE 4 ++#define M_SERDESLOWSIGCHANGE 0xf ++#define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE) ++#define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE) + + #define S_XAUIPCSCTCERR 3 + #define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR) +@@ -2405,8 +7637,29 @@ + #define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE) + #define F_XAUIPCSALIGNCHANGE V_XAUIPCSALIGNCHANGE(1U) + ++#define S_RGMIILINKSTSCHANGE 1 ++#define V_RGMIILINKSTSCHANGE(x) ((x) << S_RGMIILINKSTSCHANGE) ++#define F_RGMIILINKSTSCHANGE V_RGMIILINKSTSCHANGE(1U) ++ ++#define S_XGM_INT 0 ++#define V_XGM_INT(x) ((x) << S_XGM_INT) ++#define F_XGM_INT V_XGM_INT(1U) ++ ++#define S_SERDESCMULOCK_LOSS 24 ++#define V_SERDESCMULOCK_LOSS(x) ((x) << S_SERDESCMULOCK_LOSS) ++#define F_SERDESCMULOCK_LOSS V_SERDESCMULOCK_LOSS(1U) ++ ++#define S_SERDESBIST_ERR 8 ++#define M_SERDESBIST_ERR 0xf ++#define V_SERDESBIST_ERR(x) ((x) << S_SERDESBIST_ERR) ++#define G_SERDESBIST_ERR(x) (((x) >> S_SERDESBIST_ERR) & M_SERDESBIST_ERR) ++ ++#define S_SERDES_LOS 4 ++#define M_SERDES_LOS 0xf ++#define V_SERDES_LOS(x) ((x) << S_SERDES_LOS) ++#define G_SERDES_LOS(x) (((x) >> S_SERDES_LOS) & M_SERDES_LOS) ++ + #define A_XGM_INT_CAUSE 0x8d8 +- + #define A_XGM_XAUI_ACT_CTRL 0x8dc + + #define S_TXACTENABLE 1 +@@ -2415,6 +7668,22 @@ + + #define A_XGM_SERDES_CTRL0 0x8e0 + ++#define S_INTSERLPBK3 27 ++#define V_INTSERLPBK3(x) ((x) << S_INTSERLPBK3) ++#define F_INTSERLPBK3 V_INTSERLPBK3(1U) ++ ++#define S_INTSERLPBK2 26 ++#define V_INTSERLPBK2(x) ((x) << S_INTSERLPBK2) ++#define F_INTSERLPBK2 V_INTSERLPBK2(1U) ++ ++#define S_INTSERLPBK1 25 ++#define V_INTSERLPBK1(x) ((x) << S_INTSERLPBK1) ++#define F_INTSERLPBK1 V_INTSERLPBK1(1U) ++ ++#define S_INTSERLPBK0 24 ++#define V_INTSERLPBK0(x) ((x) << S_INTSERLPBK0) ++#define F_INTSERLPBK0 V_INTSERLPBK0(1U) ++ + #define S_RESET3 23 + #define V_RESET3(x) ((x) << S_RESET3) + #define F_RESET3 V_RESET3(1U) +@@ -2455,96 +7724,582 @@ + #define V_RESETPLL01(x) ((x) << S_RESETPLL01) + #define F_RESETPLL01 V_RESETPLL01(1U) + ++#define S_PW23 12 ++#define M_PW23 0x3 ++#define V_PW23(x) ((x) << S_PW23) ++#define G_PW23(x) (((x) >> S_PW23) & M_PW23) ++ ++#define S_PW01 10 ++#define M_PW01 0x3 ++#define V_PW01(x) ((x) << S_PW01) ++#define G_PW01(x) (((x) >> S_PW01) & M_PW01) ++ ++#define S_XGM_DEQ 6 ++#define M_XGM_DEQ 0xf ++#define V_XGM_DEQ(x) ((x) << S_XGM_DEQ) ++#define G_XGM_DEQ(x) (((x) >> S_XGM_DEQ) & M_XGM_DEQ) ++ ++#define S_XGM_DTX 2 ++#define M_XGM_DTX 0xf ++#define V_XGM_DTX(x) ((x) << S_XGM_DTX) ++#define G_XGM_DTX(x) (((x) >> S_XGM_DTX) & M_XGM_DTX) ++ ++#define S_XGM_LODRV 1 ++#define V_XGM_LODRV(x) ((x) << S_XGM_LODRV) ++#define F_XGM_LODRV V_XGM_LODRV(1U) ++ ++#define S_XGM_HIDRV 0 ++#define V_XGM_HIDRV(x) ((x) << S_XGM_HIDRV) ++#define F_XGM_HIDRV V_XGM_HIDRV(1U) ++ ++#define A_XGM_SERDES_CTRL1 0x8e4 ++ ++#define S_FMOFFSET3 19 ++#define M_FMOFFSET3 0x1f ++#define V_FMOFFSET3(x) ((x) << S_FMOFFSET3) ++#define G_FMOFFSET3(x) (((x) >> S_FMOFFSET3) & M_FMOFFSET3) ++ ++#define S_FMOFFSETEN3 18 ++#define V_FMOFFSETEN3(x) ((x) << S_FMOFFSETEN3) ++#define F_FMOFFSETEN3 V_FMOFFSETEN3(1U) ++ ++#define S_FMOFFSET2 13 ++#define M_FMOFFSET2 0x1f ++#define V_FMOFFSET2(x) ((x) << S_FMOFFSET2) ++#define G_FMOFFSET2(x) (((x) >> S_FMOFFSET2) & M_FMOFFSET2) ++ ++#define S_FMOFFSETEN2 12 ++#define V_FMOFFSETEN2(x) ((x) << S_FMOFFSETEN2) ++#define F_FMOFFSETEN2 V_FMOFFSETEN2(1U) ++ ++#define S_FMOFFSET1 7 ++#define M_FMOFFSET1 0x1f ++#define V_FMOFFSET1(x) ((x) << S_FMOFFSET1) ++#define G_FMOFFSET1(x) (((x) >> S_FMOFFSET1) & M_FMOFFSET1) ++ ++#define S_FMOFFSETEN1 6 ++#define V_FMOFFSETEN1(x) ((x) << S_FMOFFSETEN1) ++#define F_FMOFFSETEN1 V_FMOFFSETEN1(1U) ++ ++#define S_FMOFFSET0 1 ++#define M_FMOFFSET0 0x1f ++#define V_FMOFFSET0(x) ((x) << S_FMOFFSET0) ++#define G_FMOFFSET0(x) (((x) >> S_FMOFFSET0) & M_FMOFFSET0) ++ ++#define S_FMOFFSETEN0 0 ++#define V_FMOFFSETEN0(x) ((x) << S_FMOFFSETEN0) ++#define F_FMOFFSETEN0 V_FMOFFSETEN0(1U) ++ ++#define A_XGM_SERDES_CTRL2 0x8e8 ++ ++#define S_DNIN3 11 ++#define V_DNIN3(x) ((x) << S_DNIN3) ++#define F_DNIN3 V_DNIN3(1U) ++ ++#define S_UPIN3 10 ++#define V_UPIN3(x) ((x) << S_UPIN3) ++#define F_UPIN3 V_UPIN3(1U) ++ ++#define S_RXSLAVE3 9 ++#define V_RXSLAVE3(x) ((x) << S_RXSLAVE3) ++#define F_RXSLAVE3 V_RXSLAVE3(1U) ++ ++#define S_DNIN2 8 ++#define V_DNIN2(x) ((x) << S_DNIN2) ++#define F_DNIN2 V_DNIN2(1U) ++ ++#define S_UPIN2 7 ++#define V_UPIN2(x) ((x) << S_UPIN2) ++#define F_UPIN2 V_UPIN2(1U) ++ ++#define S_RXSLAVE2 6 ++#define V_RXSLAVE2(x) ((x) << S_RXSLAVE2) ++#define F_RXSLAVE2 V_RXSLAVE2(1U) ++ ++#define S_DNIN1 5 ++#define V_DNIN1(x) ((x) << S_DNIN1) ++#define F_DNIN1 V_DNIN1(1U) ++ ++#define S_UPIN1 4 ++#define V_UPIN1(x) ((x) << S_UPIN1) ++#define F_UPIN1 V_UPIN1(1U) ++ ++#define S_RXSLAVE1 3 ++#define V_RXSLAVE1(x) ((x) << S_RXSLAVE1) ++#define F_RXSLAVE1 V_RXSLAVE1(1U) ++ ++#define S_DNIN0 2 ++#define V_DNIN0(x) ((x) << S_DNIN0) ++#define F_DNIN0 V_DNIN0(1U) ++ ++#define S_UPIN0 1 ++#define V_UPIN0(x) ((x) << S_UPIN0) ++#define F_UPIN0 V_UPIN0(1U) ++ ++#define S_RXSLAVE0 0 ++#define V_RXSLAVE0(x) ((x) << S_RXSLAVE0) ++#define F_RXSLAVE0 V_RXSLAVE0(1U) ++ ++#define A_XGM_SERDES_CTRL3 0x8ec ++ ++#define S_EXTBISTCHKERRCLR3 31 ++#define V_EXTBISTCHKERRCLR3(x) ((x) << S_EXTBISTCHKERRCLR3) ++#define F_EXTBISTCHKERRCLR3 V_EXTBISTCHKERRCLR3(1U) ++ ++#define S_EXTBISTCHKEN3 30 ++#define V_EXTBISTCHKEN3(x) ((x) << S_EXTBISTCHKEN3) ++#define F_EXTBISTCHKEN3 V_EXTBISTCHKEN3(1U) ++ ++#define S_EXTBISTGENEN3 29 ++#define V_EXTBISTGENEN3(x) ((x) << S_EXTBISTGENEN3) ++#define F_EXTBISTGENEN3 V_EXTBISTGENEN3(1U) ++ ++#define S_EXTBISTPAT3 26 ++#define M_EXTBISTPAT3 0x7 ++#define V_EXTBISTPAT3(x) ((x) << S_EXTBISTPAT3) ++#define G_EXTBISTPAT3(x) (((x) >> S_EXTBISTPAT3) & M_EXTBISTPAT3) ++ ++#define S_EXTPARRESET3 25 ++#define V_EXTPARRESET3(x) ((x) << S_EXTPARRESET3) ++#define F_EXTPARRESET3 V_EXTPARRESET3(1U) ++ ++#define S_EXTPARLPBK3 24 ++#define V_EXTPARLPBK3(x) ((x) << S_EXTPARLPBK3) ++#define F_EXTPARLPBK3 V_EXTPARLPBK3(1U) ++ ++#define S_EXTBISTCHKERRCLR2 23 ++#define V_EXTBISTCHKERRCLR2(x) ((x) << S_EXTBISTCHKERRCLR2) ++#define F_EXTBISTCHKERRCLR2 V_EXTBISTCHKERRCLR2(1U) ++ ++#define S_EXTBISTCHKEN2 22 ++#define V_EXTBISTCHKEN2(x) ((x) << S_EXTBISTCHKEN2) ++#define F_EXTBISTCHKEN2 V_EXTBISTCHKEN2(1U) ++ ++#define S_EXTBISTGENEN2 21 ++#define V_EXTBISTGENEN2(x) ((x) << S_EXTBISTGENEN2) ++#define F_EXTBISTGENEN2 V_EXTBISTGENEN2(1U) ++ ++#define S_EXTBISTPAT2 18 ++#define M_EXTBISTPAT2 0x7 ++#define V_EXTBISTPAT2(x) ((x) << S_EXTBISTPAT2) ++#define G_EXTBISTPAT2(x) (((x) >> S_EXTBISTPAT2) & M_EXTBISTPAT2) ++ ++#define S_EXTPARRESET2 17 ++#define V_EXTPARRESET2(x) ((x) << S_EXTPARRESET2) ++#define F_EXTPARRESET2 V_EXTPARRESET2(1U) ++ ++#define S_EXTPARLPBK2 16 ++#define V_EXTPARLPBK2(x) ((x) << S_EXTPARLPBK2) ++#define F_EXTPARLPBK2 V_EXTPARLPBK2(1U) ++ ++#define S_EXTBISTCHKERRCLR1 15 ++#define V_EXTBISTCHKERRCLR1(x) ((x) << S_EXTBISTCHKERRCLR1) ++#define F_EXTBISTCHKERRCLR1 V_EXTBISTCHKERRCLR1(1U) ++ ++#define S_EXTBISTCHKEN1 14 ++#define V_EXTBISTCHKEN1(x) ((x) << S_EXTBISTCHKEN1) ++#define F_EXTBISTCHKEN1 V_EXTBISTCHKEN1(1U) ++ ++#define S_EXTBISTGENEN1 13 ++#define V_EXTBISTGENEN1(x) ((x) << S_EXTBISTGENEN1) ++#define F_EXTBISTGENEN1 V_EXTBISTGENEN1(1U) ++ ++#define S_EXTBISTPAT1 10 ++#define M_EXTBISTPAT1 0x7 ++#define V_EXTBISTPAT1(x) ((x) << S_EXTBISTPAT1) ++#define G_EXTBISTPAT1(x) (((x) >> S_EXTBISTPAT1) & M_EXTBISTPAT1) ++ ++#define S_EXTPARRESET1 9 ++#define V_EXTPARRESET1(x) ((x) << S_EXTPARRESET1) ++#define F_EXTPARRESET1 V_EXTPARRESET1(1U) ++ ++#define S_EXTPARLPBK1 8 ++#define V_EXTPARLPBK1(x) ((x) << S_EXTPARLPBK1) ++#define F_EXTPARLPBK1 V_EXTPARLPBK1(1U) ++ ++#define S_EXTBISTCHKERRCLR0 7 ++#define V_EXTBISTCHKERRCLR0(x) ((x) << S_EXTBISTCHKERRCLR0) ++#define F_EXTBISTCHKERRCLR0 V_EXTBISTCHKERRCLR0(1U) ++ ++#define S_EXTBISTCHKEN0 6 ++#define V_EXTBISTCHKEN0(x) ((x) << S_EXTBISTCHKEN0) ++#define F_EXTBISTCHKEN0 V_EXTBISTCHKEN0(1U) ++ ++#define S_EXTBISTGENEN0 5 ++#define V_EXTBISTGENEN0(x) ((x) << S_EXTBISTGENEN0) ++#define F_EXTBISTGENEN0 V_EXTBISTGENEN0(1U) ++ ++#define S_EXTBISTPAT0 2 ++#define M_EXTBISTPAT0 0x7 ++#define V_EXTBISTPAT0(x) ((x) << S_EXTBISTPAT0) ++#define G_EXTBISTPAT0(x) (((x) >> S_EXTBISTPAT0) & M_EXTBISTPAT0) ++ ++#define S_EXTPARRESET0 1 ++#define V_EXTPARRESET0(x) ((x) << S_EXTPARRESET0) ++#define F_EXTPARRESET0 V_EXTPARRESET0(1U) ++ ++#define S_EXTPARLPBK0 0 ++#define V_EXTPARLPBK0(x) ((x) << S_EXTPARLPBK0) ++#define F_EXTPARLPBK0 V_EXTPARLPBK0(1U) ++ + #define A_XGM_SERDES_STAT0 0x8f0 +-#define A_XGM_SERDES_STAT1 0x8f4 +-#define A_XGM_SERDES_STAT2 0x8f8 ++ ++#define S_EXTBISTCHKERRCNT0 4 ++#define M_EXTBISTCHKERRCNT0 0xffffff ++#define V_EXTBISTCHKERRCNT0(x) ((x) << S_EXTBISTCHKERRCNT0) ++#define G_EXTBISTCHKERRCNT0(x) (((x) >> S_EXTBISTCHKERRCNT0) & M_EXTBISTCHKERRCNT0) ++ ++#define S_EXTBISTCHKFMD0 3 ++#define V_EXTBISTCHKFMD0(x) ((x) << S_EXTBISTCHKFMD0) ++#define F_EXTBISTCHKFMD0 V_EXTBISTCHKFMD0(1U) ++ ++#define S_LOWSIGFORCEEN0 2 ++#define V_LOWSIGFORCEEN0(x) ((x) << S_LOWSIGFORCEEN0) ++#define F_LOWSIGFORCEEN0 V_LOWSIGFORCEEN0(1U) ++ ++#define S_LOWSIGFORCEVALUE0 1 ++#define V_LOWSIGFORCEVALUE0(x) ((x) << S_LOWSIGFORCEVALUE0) ++#define F_LOWSIGFORCEVALUE0 V_LOWSIGFORCEVALUE0(1U) + + #define S_LOWSIG0 0 + #define V_LOWSIG0(x) ((x) << S_LOWSIG0) + #define F_LOWSIG0 V_LOWSIG0(1U) + ++#define A_XGM_SERDES_STAT1 0x8f4 ++ ++#define S_EXTBISTCHKERRCNT1 4 ++#define M_EXTBISTCHKERRCNT1 0xffffff ++#define V_EXTBISTCHKERRCNT1(x) ((x) << S_EXTBISTCHKERRCNT1) ++#define G_EXTBISTCHKERRCNT1(x) (((x) >> S_EXTBISTCHKERRCNT1) & M_EXTBISTCHKERRCNT1) ++ ++#define S_EXTBISTCHKFMD1 3 ++#define V_EXTBISTCHKFMD1(x) ((x) << S_EXTBISTCHKFMD1) ++#define F_EXTBISTCHKFMD1 V_EXTBISTCHKFMD1(1U) ++ ++#define S_LOWSIGFORCEEN1 2 ++#define V_LOWSIGFORCEEN1(x) ((x) << S_LOWSIGFORCEEN1) ++#define F_LOWSIGFORCEEN1 V_LOWSIGFORCEEN1(1U) ++ ++#define S_LOWSIGFORCEVALUE1 1 ++#define V_LOWSIGFORCEVALUE1(x) ((x) << S_LOWSIGFORCEVALUE1) ++#define F_LOWSIGFORCEVALUE1 V_LOWSIGFORCEVALUE1(1U) ++ ++#define S_LOWSIG1 0 ++#define V_LOWSIG1(x) ((x) << S_LOWSIG1) ++#define F_LOWSIG1 V_LOWSIG1(1U) ++ ++#define A_XGM_SERDES_STAT2 0x8f8 ++ ++#define S_EXTBISTCHKERRCNT2 4 ++#define M_EXTBISTCHKERRCNT2 0xffffff ++#define V_EXTBISTCHKERRCNT2(x) ((x) << S_EXTBISTCHKERRCNT2) ++#define G_EXTBISTCHKERRCNT2(x) (((x) >> S_EXTBISTCHKERRCNT2) & M_EXTBISTCHKERRCNT2) ++ ++#define S_EXTBISTCHKFMD2 3 ++#define V_EXTBISTCHKFMD2(x) ((x) << S_EXTBISTCHKFMD2) ++#define F_EXTBISTCHKFMD2 V_EXTBISTCHKFMD2(1U) ++ ++#define S_LOWSIGFORCEEN2 2 ++#define V_LOWSIGFORCEEN2(x) ((x) << S_LOWSIGFORCEEN2) ++#define F_LOWSIGFORCEEN2 V_LOWSIGFORCEEN2(1U) ++ ++#define S_LOWSIGFORCEVALUE2 1 ++#define V_LOWSIGFORCEVALUE2(x) ((x) << S_LOWSIGFORCEVALUE2) ++#define F_LOWSIGFORCEVALUE2 V_LOWSIGFORCEVALUE2(1U) ++ ++#define S_LOWSIG2 0 ++#define V_LOWSIG2(x) ((x) << S_LOWSIG2) ++#define F_LOWSIG2 V_LOWSIG2(1U) ++ + #define A_XGM_SERDES_STAT3 0x8fc + ++#define S_EXTBISTCHKERRCNT3 4 ++#define M_EXTBISTCHKERRCNT3 0xffffff ++#define V_EXTBISTCHKERRCNT3(x) ((x) << S_EXTBISTCHKERRCNT3) ++#define G_EXTBISTCHKERRCNT3(x) (((x) >> S_EXTBISTCHKERRCNT3) & M_EXTBISTCHKERRCNT3) ++ ++#define S_EXTBISTCHKFMD3 3 ++#define V_EXTBISTCHKFMD3(x) ((x) << S_EXTBISTCHKFMD3) ++#define F_EXTBISTCHKFMD3 V_EXTBISTCHKFMD3(1U) ++ ++#define S_LOWSIGFORCEEN3 2 ++#define V_LOWSIGFORCEEN3(x) ((x) << S_LOWSIGFORCEEN3) ++#define F_LOWSIGFORCEEN3 V_LOWSIGFORCEEN3(1U) ++ ++#define S_LOWSIGFORCEVALUE3 1 ++#define V_LOWSIGFORCEVALUE3(x) ((x) << S_LOWSIGFORCEVALUE3) ++#define F_LOWSIGFORCEVALUE3 V_LOWSIGFORCEVALUE3(1U) ++ ++#define S_LOWSIG3 0 ++#define V_LOWSIG3(x) ((x) << S_LOWSIG3) ++#define F_LOWSIG3 V_LOWSIG3(1U) ++ + #define A_XGM_STAT_TX_BYTE_LOW 0x900 +- + #define A_XGM_STAT_TX_BYTE_HIGH 0x904 + ++#define S_TXBYTES_HIGH 0 ++#define M_TXBYTES_HIGH 0x1fff ++#define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH) ++#define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH) ++ + #define A_XGM_STAT_TX_FRAME_LOW 0x908 +- + #define A_XGM_STAT_TX_FRAME_HIGH 0x90c + ++#define S_TXFRAMES_HIGH 0 ++#define M_TXFRAMES_HIGH 0xf ++#define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH) ++#define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH) ++ + #define A_XGM_STAT_TX_BCAST 0x910 +- + #define A_XGM_STAT_TX_MCAST 0x914 +- + #define A_XGM_STAT_TX_PAUSE 0x918 +- + #define A_XGM_STAT_TX_64B_FRAMES 0x91c +- + #define A_XGM_STAT_TX_65_127B_FRAMES 0x920 +- + #define A_XGM_STAT_TX_128_255B_FRAMES 0x924 +- + #define A_XGM_STAT_TX_256_511B_FRAMES 0x928 +- + #define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c +- + #define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930 +- + #define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934 +- + #define A_XGM_STAT_TX_ERR_FRAMES 0x938 +- + #define A_XGM_STAT_RX_BYTES_LOW 0x93c +- + #define A_XGM_STAT_RX_BYTES_HIGH 0x940 + ++#define S_RXBYTES_HIGH 0 ++#define M_RXBYTES_HIGH 0x1fff ++#define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH) ++#define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH) ++ + #define A_XGM_STAT_RX_FRAMES_LOW 0x944 +- + #define A_XGM_STAT_RX_FRAMES_HIGH 0x948 + ++#define S_RXFRAMES_HIGH 0 ++#define M_RXFRAMES_HIGH 0xf ++#define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH) ++#define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH) ++ + #define A_XGM_STAT_RX_BCAST_FRAMES 0x94c +- + #define A_XGM_STAT_RX_MCAST_FRAMES 0x950 +- + #define A_XGM_STAT_RX_PAUSE_FRAMES 0x954 + ++#define S_RXPAUSEFRAMES 0 ++#define M_RXPAUSEFRAMES 0xffff ++#define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES) ++#define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES) ++ + #define A_XGM_STAT_RX_64B_FRAMES 0x958 +- + #define A_XGM_STAT_RX_65_127B_FRAMES 0x95c +- + #define A_XGM_STAT_RX_128_255B_FRAMES 0x960 +- + #define A_XGM_STAT_RX_256_511B_FRAMES 0x964 +- + #define A_XGM_STAT_RX_512_1023B_FRAMES 0x968 +- + #define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c +- + #define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970 +- + #define A_XGM_STAT_RX_SHORT_FRAMES 0x974 + ++#define S_RXSHORTFRAMES 0 ++#define M_RXSHORTFRAMES 0xffff ++#define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES) ++#define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES) ++ + #define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978 + ++#define S_RXOVERSIZEFRAMES 0 ++#define M_RXOVERSIZEFRAMES 0xffff ++#define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES) ++#define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES) ++ + #define A_XGM_STAT_RX_JABBER_FRAMES 0x97c + ++#define S_RXJABBERFRAMES 0 ++#define M_RXJABBERFRAMES 0xffff ++#define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES) ++#define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES) ++ + #define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980 + ++#define S_RXCRCERRFRAMES 0 ++#define M_RXCRCERRFRAMES 0xffff ++#define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES) ++#define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES) ++ + #define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984 + ++#define S_RXLENGTHERRFRAMES 0 ++#define M_RXLENGTHERRFRAMES 0xffff ++#define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES) ++#define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES) ++ + #define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988 + ++#define S_RXSYMCODEERRFRAMES 0 ++#define M_RXSYMCODEERRFRAMES 0xffff ++#define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES) ++#define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES) ++ + #define A_XGM_SERDES_STATUS0 0x98c + ++#define S_RXERRLANE3 9 ++#define M_RXERRLANE3 0x7 ++#define V_RXERRLANE3(x) ((x) << S_RXERRLANE3) ++#define G_RXERRLANE3(x) (((x) >> S_RXERRLANE3) & M_RXERRLANE3) ++ ++#define S_RXERRLANE2 6 ++#define M_RXERRLANE2 0x7 ++#define V_RXERRLANE2(x) ((x) << S_RXERRLANE2) ++#define G_RXERRLANE2(x) (((x) >> S_RXERRLANE2) & M_RXERRLANE2) ++ ++#define S_RXERRLANE1 3 ++#define M_RXERRLANE1 0x7 ++#define V_RXERRLANE1(x) ((x) << S_RXERRLANE1) ++#define G_RXERRLANE1(x) (((x) >> S_RXERRLANE1) & M_RXERRLANE1) ++ ++#define S_RXERRLANE0 0 ++#define M_RXERRLANE0 0x7 ++#define V_RXERRLANE0(x) ((x) << S_RXERRLANE0) ++#define G_RXERRLANE0(x) (((x) >> S_RXERRLANE0) & M_RXERRLANE0) ++ + #define A_XGM_SERDES_STATUS1 0x990 + +-#define S_CMULOCK 31 +-#define V_CMULOCK(x) ((x) << S_CMULOCK) +-#define F_CMULOCK V_CMULOCK(1U) ++#define S_RXKLOCKLANE3 11 ++#define V_RXKLOCKLANE3(x) ((x) << S_RXKLOCKLANE3) ++#define F_RXKLOCKLANE3 V_RXKLOCKLANE3(1U) ++ ++#define S_RXKLOCKLANE2 10 ++#define V_RXKLOCKLANE2(x) ((x) << S_RXKLOCKLANE2) ++#define F_RXKLOCKLANE2 V_RXKLOCKLANE2(1U) ++ ++#define S_RXKLOCKLANE1 9 ++#define V_RXKLOCKLANE1(x) ((x) << S_RXKLOCKLANE1) ++#define F_RXKLOCKLANE1 V_RXKLOCKLANE1(1U) ++ ++#define S_RXKLOCKLANE0 8 ++#define V_RXKLOCKLANE0(x) ((x) << S_RXKLOCKLANE0) ++#define F_RXKLOCKLANE0 V_RXKLOCKLANE0(1U) ++ ++#define S_RXUFLOWLANE3 7 ++#define V_RXUFLOWLANE3(x) ((x) << S_RXUFLOWLANE3) ++#define F_RXUFLOWLANE3 V_RXUFLOWLANE3(1U) ++ ++#define S_RXUFLOWLANE2 6 ++#define V_RXUFLOWLANE2(x) ((x) << S_RXUFLOWLANE2) ++#define F_RXUFLOWLANE2 V_RXUFLOWLANE2(1U) ++ ++#define S_RXUFLOWLANE1 5 ++#define V_RXUFLOWLANE1(x) ((x) << S_RXUFLOWLANE1) ++#define F_RXUFLOWLANE1 V_RXUFLOWLANE1(1U) ++ ++#define S_RXUFLOWLANE0 4 ++#define V_RXUFLOWLANE0(x) ((x) << S_RXUFLOWLANE0) ++#define F_RXUFLOWLANE0 V_RXUFLOWLANE0(1U) ++ ++#define S_RXOFLOWLANE3 3 ++#define V_RXOFLOWLANE3(x) ((x) << S_RXOFLOWLANE3) ++#define F_RXOFLOWLANE3 V_RXOFLOWLANE3(1U) ++ ++#define S_RXOFLOWLANE2 2 ++#define V_RXOFLOWLANE2(x) ((x) << S_RXOFLOWLANE2) ++#define F_RXOFLOWLANE2 V_RXOFLOWLANE2(1U) ++ ++#define S_RXOFLOWLANE1 1 ++#define V_RXOFLOWLANE1(x) ((x) << S_RXOFLOWLANE1) ++#define F_RXOFLOWLANE1 V_RXOFLOWLANE1(1U) ++ ++#define S_RXOFLOWLANE0 0 ++#define V_RXOFLOWLANE0(x) ((x) << S_RXOFLOWLANE0) ++#define F_RXOFLOWLANE0 V_RXOFLOWLANE0(1U) ++ ++#define A_XGM_SERDES_STATUS2 0x994 ++ ++#define S_XGM_RXEIDLANE3 11 ++#define V_XGM_RXEIDLANE3(x) ((x) << S_XGM_RXEIDLANE3) ++#define F_XGM_RXEIDLANE3 V_XGM_RXEIDLANE3(1U) ++ ++#define S_XGM_RXEIDLANE2 10 ++#define V_XGM_RXEIDLANE2(x) ((x) << S_XGM_RXEIDLANE2) ++#define F_XGM_RXEIDLANE2 V_XGM_RXEIDLANE2(1U) ++ ++#define S_XGM_RXEIDLANE1 9 ++#define V_XGM_RXEIDLANE1(x) ((x) << S_XGM_RXEIDLANE1) ++#define F_XGM_RXEIDLANE1 V_XGM_RXEIDLANE1(1U) ++ ++#define S_XGM_RXEIDLANE0 8 ++#define V_XGM_RXEIDLANE0(x) ((x) << S_XGM_RXEIDLANE0) ++#define F_XGM_RXEIDLANE0 V_XGM_RXEIDLANE0(1U) ++ ++#define S_RXREMSKIPLANE3 7 ++#define V_RXREMSKIPLANE3(x) ((x) << S_RXREMSKIPLANE3) ++#define F_RXREMSKIPLANE3 V_RXREMSKIPLANE3(1U) ++ ++#define S_RXREMSKIPLANE2 6 ++#define V_RXREMSKIPLANE2(x) ((x) << S_RXREMSKIPLANE2) ++#define F_RXREMSKIPLANE2 V_RXREMSKIPLANE2(1U) ++ ++#define S_RXREMSKIPLANE1 5 ++#define V_RXREMSKIPLANE1(x) ((x) << S_RXREMSKIPLANE1) ++#define F_RXREMSKIPLANE1 V_RXREMSKIPLANE1(1U) ++ ++#define S_RXREMSKIPLANE0 4 ++#define V_RXREMSKIPLANE0(x) ((x) << S_RXREMSKIPLANE0) ++#define F_RXREMSKIPLANE0 V_RXREMSKIPLANE0(1U) ++ ++#define S_RXADDSKIPLANE3 3 ++#define V_RXADDSKIPLANE3(x) ((x) << S_RXADDSKIPLANE3) ++#define F_RXADDSKIPLANE3 V_RXADDSKIPLANE3(1U) ++ ++#define S_RXADDSKIPLANE2 2 ++#define V_RXADDSKIPLANE2(x) ((x) << S_RXADDSKIPLANE2) ++#define F_RXADDSKIPLANE2 V_RXADDSKIPLANE2(1U) ++ ++#define S_RXADDSKIPLANE1 1 ++#define V_RXADDSKIPLANE1(x) ((x) << S_RXADDSKIPLANE1) ++#define F_RXADDSKIPLANE1 V_RXADDSKIPLANE1(1U) ++ ++#define S_RXADDSKIPLANE0 0 ++#define V_RXADDSKIPLANE0(x) ((x) << S_RXADDSKIPLANE0) ++#define F_RXADDSKIPLANE0 V_RXADDSKIPLANE0(1U) ++ ++#define A_XGM_XAUI_PCS_ERR 0x998 ++ ++#define S_PCS_SYNCSTATUS 5 ++#define M_PCS_SYNCSTATUS 0xf ++#define V_PCS_SYNCSTATUS(x) ((x) << S_PCS_SYNCSTATUS) ++#define G_PCS_SYNCSTATUS(x) (((x) >> S_PCS_SYNCSTATUS) & M_PCS_SYNCSTATUS) ++ ++#define S_PCS_CTCFIFOERR 1 ++#define M_PCS_CTCFIFOERR 0xf ++#define V_PCS_CTCFIFOERR(x) ((x) << S_PCS_CTCFIFOERR) ++#define G_PCS_CTCFIFOERR(x) (((x) >> S_PCS_CTCFIFOERR) & M_PCS_CTCFIFOERR) ++ ++#define S_PCS_NOTALIGNED 0 ++#define V_PCS_NOTALIGNED(x) ((x) << S_PCS_NOTALIGNED) ++#define F_PCS_NOTALIGNED V_PCS_NOTALIGNED(1U) ++ ++#define A_XGM_RGMII_STATUS 0x99c ++ ++#define S_GMIIDUPLEX 3 ++#define V_GMIIDUPLEX(x) ((x) << S_GMIIDUPLEX) ++#define F_GMIIDUPLEX V_GMIIDUPLEX(1U) ++ ++#define S_GMIISPEED 1 ++#define M_GMIISPEED 0x3 ++#define V_GMIISPEED(x) ((x) << S_GMIISPEED) ++#define G_GMIISPEED(x) (((x) >> S_GMIISPEED) & M_GMIISPEED) ++ ++#define S_GMIILINKSTATUS 0 ++#define V_GMIILINKSTATUS(x) ((x) << S_GMIILINKSTATUS) ++#define F_GMIILINKSTATUS V_GMIILINKSTATUS(1U) ++ ++#define A_XGM_WOL_STATUS 0x9a0 ++ ++#define S_PATDETECTED 31 ++#define V_PATDETECTED(x) ((x) << S_PATDETECTED) ++#define F_PATDETECTED V_PATDETECTED(1U) ++ ++#define S_MATCHEDFILTER 0 ++#define M_MATCHEDFILTER 0x7 ++#define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER) ++#define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER) + + #define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4 +- + #define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8 + + #define S_TXSPI4SOPCNT 16 +@@ -2552,6 +8307,22 @@ + #define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT) + #define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT) + ++#define S_TXSPI4EOPCNT 0 ++#define M_TXSPI4EOPCNT 0xffff ++#define V_TXSPI4EOPCNT(x) ((x) << S_TXSPI4EOPCNT) ++#define G_TXSPI4EOPCNT(x) (((x) >> S_TXSPI4EOPCNT) & M_TXSPI4EOPCNT) ++ + #define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac + ++#define S_RXSPI4SOPCNT 16 ++#define M_RXSPI4SOPCNT 0xffff ++#define V_RXSPI4SOPCNT(x) ((x) << S_RXSPI4SOPCNT) ++#define G_RXSPI4SOPCNT(x) (((x) >> S_RXSPI4SOPCNT) & M_RXSPI4SOPCNT) ++ ++#define S_RXSPI4EOPCNT 0 ++#define M_RXSPI4EOPCNT 0xffff ++#define V_RXSPI4EOPCNT(x) ((x) << S_RXSPI4EOPCNT) ++#define G_RXSPI4EOPCNT(x) (((x) >> S_RXSPI4EOPCNT) & M_RXSPI4EOPCNT) ++ ++/* registers for module XGMAC0_1 */ + #define XGMAC0_1_BASE_ADDR 0xa00 +diff -r c6413c34aa41 drivers/net/cxgb3/sge.c +--- a/drivers/net/cxgb3/sge.c Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/sge.c Tue Oct 06 09:38:00 2009 +0100 +@@ -1,52 +1,40 @@ + /* +- * Copyright (c) 2005-2007 Chelsio, Inc. All rights reserved. +- * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: +- * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- */ ++ * This file is part of the Chelsio T3 Ethernet driver. ++ * ++ * Copyright (C) 2005-2009 Chelsio Communications. All rights reserved. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. ++ */ ++ ++#include + #include + #include + #include + #include + #include + #include ++ ++#include ++ ++#ifndef LINUX_2_4 + #include + #include ++#endif + #include "common.h" + #include "regs.h" + #include "sge_defs.h" + #include "t3_cpl.h" ++#include "cxgb3_offload.h" + #include "firmware_exports.h" + ++#include "cxgb3_compat.h" ++ + #define USE_GTS 0 + + #define SGE_RX_SM_BUF_SIZE 1536 +- + #define SGE_RX_COPY_THRES 256 + #define SGE_RX_PULL_LEN 128 + +@@ -55,18 +43,34 @@ + * It must be a divisor of PAGE_SIZE. If set to 0 FL0 will use sk_buffs + * directly. + */ +-#define FL0_PG_CHUNK_SIZE 2048 ++#define FL0_PG_CHUNK_SIZE 2048 + #define FL0_PG_ORDER 0 ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) ++#define FL_GFP_FLAGS __GFP_COMP + #define FL1_PG_CHUNK_SIZE (PAGE_SIZE > 8192 ? 16384 : 8192) + #define FL1_PG_ORDER (PAGE_SIZE > 8192 ? 0 : 1) ++#else ++#define FL1_PG_CHUNK_SIZE 0 ++#define FL1_PG_ORDER 0 ++#define FL_GFP_FLAGS 0 ++#endif + + #define SGE_RX_DROP_THRES 16 ++#define RX_RECLAIM_PERIOD (HZ/4) ++ ++/* ++ * Max number of Rx buffers we replenish at a time. ++ */ ++#define MAX_RX_REFILL 16U + + /* + * Period of the Tx buffer reclaim timer. This timer does not need to run + * frequently as Tx buffers are usually reclaimed by new Tx packets. + */ + #define TX_RECLAIM_PERIOD (HZ / 4) ++#define TX_RECLAIM_TIMER_CHUNK 64U ++#define TX_RECLAIM_CHUNK 16U + + /* WR size in bytes */ + #define WR_LEN (WR_FLITS * 8) +@@ -78,12 +82,12 @@ + + /* Values for sge_txq.flags */ + enum { +- TXQ_RUNNING = 1 << 0, /* fetch engine is running */ +- TXQ_LAST_PKT_DB = 1 << 1, /* last packet rang the doorbell */ ++ TXQ_RUNNING = 1 << 0, /* fetch engine is running */ ++ TXQ_LAST_PKT_DB = 1 << 1, /* last packet rang the doorbell */ + }; + + struct tx_desc { +- __be64 flit[TX_DESC_FLITS]; ++ u64 flit[TX_DESC_FLITS]; + }; + + struct rx_desc { +@@ -93,12 +97,28 @@ + __be32 addr_hi; + }; + +-struct tx_sw_desc { /* SW state per Tx descriptor */ ++/* ++ * A single WR can reference up to 7 wire packets when we coalesce egress ++ * packets. Instead of growing the shared tx sw desc we allocate a seperate ++ * coalesce sw descriptor queue. The generic tx sw desc indicates if the new ++ * software descriptor is valid or not. ++ */ ++#define ETH_COALESCE_PKT_NUM 7 ++#define ETH_COALESCE_DUMMY_SKB ((struct sk_buff*)1) ++ ++enum { LAST_PKT_DESC = 1, PKT_COALESCE_WR = 2 }; ++ ++struct tx_sw_desc { /* SW state per Tx descriptor */ + struct sk_buff *skb; +- u8 eop; /* set if last descriptor for packet */ +- u8 addr_idx; /* buffer index of first SGL entry in descriptor */ ++ u8 eop_coalesce; /* 1 if last descriptor for pkt, 2 if coalesce wr */ ++ u8 addr_idx_coalesce_num; /* buffer index of first SGL entry in ++ descriptor, # of coalesced pkts */ + u8 fragidx; /* first page fragment associated with descriptor */ + s8 sflit; /* start flit of first SGL entry in descriptor */ ++}; ++ ++struct eth_coalesce_sw_desc { /* SW state for a Coalesce WR descriptor */ ++ struct sk_buff *skb[ETH_COALESCE_PKT_NUM]; + }; + + struct rx_sw_desc { /* SW state per Rx descriptor */ +@@ -109,7 +129,7 @@ + DECLARE_PCI_UNMAP_ADDR(dma_addr); + }; + +-struct rsp_desc { /* response queue descriptor */ ++struct rsp_desc { /* response queue descriptor */ + struct rss_header rss_hdr; + __be32 flags; + __be32 len_cq; +@@ -175,10 +195,9 @@ + * Replenishes a response queue by making the supplied number of responses + * available to HW. + */ +-static inline void refill_rspq(struct adapter *adapter, +- const struct sge_rspq *q, unsigned int credits) +-{ +- rmb(); ++static inline void refill_rspq(adapter_t *adapter, const struct sge_rspq *q, ++ unsigned int credits) ++{ + t3_write_reg(adapter, A_SG_RSPQ_CREDIT_RETURN, + V_RSPQ(q->cntxt_id) | V_CREDITS(credits)); + } +@@ -229,7 +248,7 @@ + { + const struct sg_ent *sgp; + struct tx_sw_desc *d = &q->sdesc[cidx]; +- int nfrags, frag_idx, curflit, j = d->addr_idx; ++ int nfrags, frag_idx, curflit, j = d->addr_idx_coalesce_num; + + sgp = (struct sg_ent *)&q->desc[cidx].flit[d->sflit]; + frag_idx = d->fragidx; +@@ -244,8 +263,18 @@ + nfrags = skb_shinfo(skb)->nr_frags; + + while (frag_idx < nfrags && curflit < WR_FLITS) { +- pci_unmap_page(pdev, be64_to_cpu(sgp->addr[j]), +- skb_shinfo(skb)->frags[frag_idx].size, ++ /* ++ * frag->size might be a 16 bit integer, which is a problem ++ * for 64K page size configurations. Assuming the current ++ * page is valid, fix up a zeroed size to the page size. ++ */ ++ int size = skb_shinfo(skb)->frags[frag_idx].size; ++ ++ if (PAGE_SIZE == 65536) ++ if (!size) ++ size = PAGE_SIZE; ++ ++ pci_unmap_page(pdev, be64_to_cpu(sgp->addr[j]), size, + PCI_DMA_TODEVICE); + j ^= 1; + if (j == 0) { +@@ -259,8 +288,31 @@ + if (frag_idx < nfrags) { /* SGL continues into next Tx descriptor */ + d = cidx + 1 == q->size ? q->sdesc : d + 1; + d->fragidx = frag_idx; +- d->addr_idx = j; ++ d->addr_idx_coalesce_num = j; + d->sflit = curflit - WR_FLITS - j; /* sflit can be -1 */ ++ } ++} ++ ++static inline void unmap_tx_pkt_coalesce_wr(struct sge_txq *q, ++ unsigned int cidx, ++ unsigned int num, ++ struct pci_dev *pdev) ++{ ++ struct eth_coalesce_sw_desc *csd = &q->eth_coalesce_sdesc[cidx]; ++ struct tx_pkt_coalesce_wr *wr = ++ (struct tx_pkt_coalesce_wr *)&q->desc[cidx]; ++ int i; ++ ++ for (i = 0; i < num; i++) { ++ struct cpl_tx_pkt_coalesce *cpl = &wr->cpl[i]; ++ unsigned int len = csd->skb[i]->len; ++ ++ if (skb_headlen(csd->skb[i])) ++ pci_unmap_single(pdev, be64_to_cpu(cpl->addr), ++ len, PCI_DMA_TODEVICE); ++ else ++ pci_unmap_page(pdev, be64_to_cpu(cpl->addr), len, ++ PCI_DMA_TODEVICE); + } + } + +@@ -273,23 +325,48 @@ + * Reclaims Tx descriptors from an SGE Tx queue and frees the associated + * Tx buffers. Called with the Tx queue lock held. + */ +-static void free_tx_desc(struct adapter *adapter, struct sge_txq *q, +- unsigned int n) ++static void free_tx_desc(adapter_t *adapter, struct sge_txq *q, unsigned int n) + { + struct tx_sw_desc *d; + struct pci_dev *pdev = adapter->pdev; +- unsigned int cidx = q->cidx; ++ unsigned int cidx = q->cidx, i; + + const int need_unmap = need_skb_unmap() && + q->cntxt_id >= FW_TUNNEL_SGEEC_START; + ++#ifdef T3_TRACE ++ T3_TRACE3(adapter->tb[q->cntxt_id & 7], ++ "reclaiming %u Tx descriptors at cidx %u (used %u)", n, ++ cidx, q->in_use - n); ++#endif + d = &q->sdesc[cidx]; + while (n--) { +- if (d->skb) { /* an SGL is present */ +- if (need_unmap) +- unmap_skb(d->skb, q, cidx, pdev); +- if (d->eop) +- kfree_skb(d->skb); ++ if (d->skb) { /* an SGL is present */ ++ if (need_unmap) { ++ if (d->eop_coalesce == PKT_COALESCE_WR) ++ unmap_tx_pkt_coalesce_wr(q, cidx, ++ d->addr_idx_coalesce_num, pdev); ++ else ++ unmap_skb(d->skb, q, cidx, pdev); ++ } ++ ++ if (d->eop_coalesce == PKT_COALESCE_WR) ++ for (i = 0; i < d->addr_idx_coalesce_num; i++) { ++ struct eth_coalesce_sw_desc *csd = ++ &q->eth_coalesce_sdesc[cidx]; ++ ++ /* ++ * We can be called from interrupt and ++ * TX buffers may have implicit ++ * "destructor" code associated with ++ * them to free up memory tied down in ++ * virtual machines ... ++ */ ++ dev_kfree_skb_any(csd->skb[i]); ++ } ++ else if (d->eop_coalesce) ++ /* see above: can be called from interrupt */ ++ dev_kfree_skb_any(d->skb); + } + ++d; + if (++cidx == q->size) { +@@ -309,16 +386,18 @@ + * and frees the associated buffers if possible. Called with the Tx + * queue's lock held. + */ +-static inline void reclaim_completed_tx(struct adapter *adapter, +- struct sge_txq *q) ++static inline unsigned int reclaim_completed_tx(adapter_t *adapter, struct sge_txq *q, unsigned int chunk) + { + unsigned int reclaim = q->processed - q->cleaned; ++ ++ reclaim = min(chunk, reclaim); + + if (reclaim) { + free_tx_desc(adapter, q, reclaim); + q->cleaned += reclaim; + q->in_use -= reclaim; + } ++ return (q->processed - q->cleaned); + } + + /** +@@ -332,12 +411,24 @@ + unsigned int r = q->processed - q->cleaned; + + return q->in_use - r < (q->size >> 1); ++} ++ ++static void clear_rx_desc(const struct sge_fl *q, struct rx_sw_desc *d) ++{ ++ if (q->use_pages) { ++ if (d->pg_chunk.page) ++ put_page(d->pg_chunk.page); ++ d->pg_chunk.page = NULL; ++ } else { ++ kfree_skb(d->skb); ++ d->skb = NULL; ++ } + } + + /** + * free_rx_bufs - free the Rx buffers on an SGE free list + * @pdev: the PCI device associated with the adapter +- * @rxq: the SGE free list to clean up ++ * @q: the SGE free list to clean up + * + * Release the buffers on an SGE free-buffer Rx queue. HW fetching from + * this queue should be stopped before calling this function. +@@ -351,14 +442,7 @@ + + pci_unmap_single(pdev, pci_unmap_addr(d, dma_addr), + q->buf_size, PCI_DMA_FROMDEVICE); +- if (q->use_pages) { +- if (d->pg_chunk.page) +- put_page(d->pg_chunk.page); +- d->pg_chunk.page = NULL; +- } else { +- kfree_skb(d->skb); +- d->skb = NULL; +- } ++ clear_rx_desc(q, d); + if (++cidx == q->size) + cidx = 0; + } +@@ -371,7 +455,7 @@ + + /** + * add_one_rx_buf - add a packet buffer to a free-buffer list +- * @va: buffer start VA ++ * @va: buffer start VA + * @len: the buffer length + * @d: the HW Rx descriptor to write + * @sd: the SW Rx descriptor to write +@@ -382,27 +466,26 @@ + * descriptors. + */ + static inline int add_one_rx_buf(void *va, unsigned int len, +- struct rx_desc *d, struct rx_sw_desc *sd, +- unsigned int gen, struct pci_dev *pdev) ++ struct rx_desc *d, struct rx_sw_desc *sd, ++ unsigned int gen, adapter_t *adapter) + { + dma_addr_t mapping; + +- mapping = pci_map_single(pdev, va, len, PCI_DMA_FROMDEVICE); +- if (unlikely(pci_dma_mapping_error(pdev, mapping))) ++ mapping = pci_map_single(adapter->pdev, va, len, PCI_DMA_FROMDEVICE); ++ if (unlikely(t3_pci_dma_mapping_error(adapter->pdev, mapping))) + return -ENOMEM; + + pci_unmap_addr_set(sd, dma_addr, mapping); + + d->addr_lo = cpu_to_be32(mapping); +- d->addr_hi = cpu_to_be32((u64) mapping >> 32); ++ d->addr_hi = cpu_to_be32((u64)mapping >> 32); + wmb(); + d->len_gen = cpu_to_be32(V_FLD_GEN1(gen)); + d->gen2 = cpu_to_be32(V_FLD_GEN2(gen)); + return 0; + } + +-static int alloc_pg_chunk(struct sge_fl *q, struct rx_sw_desc *sd, gfp_t gfp, +- unsigned int order) ++static int alloc_pg_chunk(struct sge_fl *q, struct rx_sw_desc *sd, gfp_t gfp, unsigned int order) + { + if (!q->pg_chunk.page) { + q->pg_chunk.page = alloc_pages(gfp, order); +@@ -423,18 +506,27 @@ + return 0; + } + ++static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q) ++{ ++ if (q->pend_cred >= q->credits / 4) { ++ q->pend_cred = 0; ++ t3_write_reg(adap, A_SG_KDOORBELL, V_EGRCNTX(q->cntxt_id)); ++ } ++} ++ + /** + * refill_fl - refill an SGE free-buffer list +- * @adapter: the adapter ++ * @adap: the adapter + * @q: the free-list to refill + * @n: the number of new buffers to allocate + * @gfp: the gfp flags for allocating new buffers + * + * (Re)populate an SGE free-buffer list with up to @n new packet buffers, + * allocated with the supplied gfp flags. The caller must assure that +- * @n does not exceed the queue's capacity. +- */ +-static int refill_fl(struct adapter *adap, struct sge_fl *q, int n, gfp_t gfp) ++ * @n does not exceed the queue's capacity. Returns the number of buffers ++ * allocated. ++ */ ++static unsigned int refill_fl(adapter_t *adap, struct sge_fl *q, int n, gfp_t gfp) + { + void *buf_start; + struct rx_sw_desc *sd = &q->sdesc[q->pidx]; +@@ -460,13 +552,10 @@ + buf_start = skb->data; + } + +- err = add_one_rx_buf(buf_start, q->buf_size, d, sd, q->gen, +- adap->pdev); ++ err = add_one_rx_buf(buf_start, q->buf_size, d, sd, q->gen, ++ adap); + if (unlikely(err)) { +- if (!q->use_pages) { +- kfree_skb(sd->skb); +- sd->skb = NULL; +- } ++ clear_rx_desc(q, sd); + break; + } + +@@ -478,50 +567,49 @@ + sd = q->sdesc; + d = q->desc; + } +- q->credits++; + count++; + } +- wmb(); +- if (likely(count)) +- t3_write_reg(adap, A_SG_KDOORBELL, V_EGRCNTX(q->cntxt_id)); +- ++ ++ q->credits += count; ++ q->pend_cred += count; ++ ring_fl_db(adap, q); + return count; + } + +-static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl) +-{ +- refill_fl(adap, fl, min(16U, fl->size - fl->credits), +- GFP_ATOMIC | __GFP_COMP); ++static inline void __refill_fl(adapter_t *adap, struct sge_fl *fl) ++{ ++ refill_fl(adap, fl, min(MAX_RX_REFILL, fl->size - fl->credits), GFP_ATOMIC | FL_GFP_FLAGS); + } + + /** + * recycle_rx_buf - recycle a receive buffer +- * @adapter: the adapter ++ * @adap: the adapter + * @q: the SGE free list + * @idx: index of buffer to recycle + * + * Recycles the specified buffer on the given free list by adding it at + * the next available slot on the list. + */ +-static void recycle_rx_buf(struct adapter *adap, struct sge_fl *q, +- unsigned int idx) ++static void recycle_rx_buf(adapter_t *adap, struct sge_fl *q, unsigned int idx) + { + struct rx_desc *from = &q->desc[idx]; +- struct rx_desc *to = &q->desc[q->pidx]; ++ struct rx_desc *to = &q->desc[q->pidx]; + + q->sdesc[q->pidx] = q->sdesc[idx]; +- to->addr_lo = from->addr_lo; /* already big endian */ +- to->addr_hi = from->addr_hi; /* likewise */ ++ to->addr_lo = from->addr_lo; // already big endian ++ to->addr_hi = from->addr_hi; // likewise + wmb(); + to->len_gen = cpu_to_be32(V_FLD_GEN1(q->gen)); + to->gen2 = cpu_to_be32(V_FLD_GEN2(q->gen)); +- q->credits++; + + if (++q->pidx == q->size) { + q->pidx = 0; + q->gen ^= 1; + } +- t3_write_reg(adap, A_SG_KDOORBELL, V_EGRCNTX(q->cntxt_id)); ++ ++ q->credits++; ++ q->pend_cred++; ++ ring_fl_db(adap, q); + } + + /** +@@ -542,11 +630,24 @@ + * of the SW ring. + */ + static void *alloc_ring(struct pci_dev *pdev, size_t nelem, size_t elem_size, +- size_t sw_size, dma_addr_t * phys, void *metadata) ++ size_t sw_size, dma_addr_t *phys, void *metadata) + { + size_t len = nelem * elem_size; + void *s = NULL; +- void *p = dma_alloc_coherent(&pdev->dev, len, phys, GFP_KERNEL); ++ void *p; ++ ++ /* ++ * On some systems we disable jumbo packets and nelem comes in as zero ++ * ... ++ */ ++ if (nelem == 0) ++ return NULL; ++ ++#ifndef LINUX_2_4 ++ p = dma_alloc_coherent(&pdev->dev, len, phys, GFP_KERNEL); ++#else ++ p = pci_alloc_consistent(pdev, len, phys); ++#endif + + if (!p) + return NULL; +@@ -554,7 +655,11 @@ + s = kcalloc(nelem, sw_size, GFP_KERNEL); + + if (!s) { ++#ifndef LINUX_2_4 + dma_free_coherent(&pdev->dev, len, p, *phys); ++#else ++ pci_free_consistent(pdev, len, p, *phys); ++#endif + return NULL; + } + } +@@ -574,6 +679,7 @@ + */ + static void t3_reset_qset(struct sge_qset *q) + { ++#if defined(NAPI_UPDATE) + if (q->adap && + !(q->adap->flags & NAPI_INIT)) { + memset(q, 0, sizeof(*q)); +@@ -586,10 +692,11 @@ + memset(q->txq, 0, sizeof(struct sge_txq) * SGE_TXQ_PER_SET); + q->txq_stopped = 0; + q->tx_reclaim_timer.function = NULL; /* for t3_stop_sge_timers() */ +- kfree(q->lro_frag_tbl); +- q->lro_nfrags = q->lro_frag_len = 0; +-} +- ++ q->rx_reclaim_timer.function = NULL; ++#else ++ memset(q, 0, sizeof(*q)); ++#endif ++} + + /** + * free_qset - free the resources of an SGE queue set +@@ -600,46 +707,63 @@ + * as HW contexts, packet buffers, and descriptor rings. Traffic to the + * queue set must be quiesced prior to calling this. + */ +-static void t3_free_qset(struct adapter *adapter, struct sge_qset *q) ++void t3_free_qset(adapter_t *adapter, struct sge_qset *q) + { + int i; + struct pci_dev *pdev = adapter->pdev; ++ ++ if (q->tx_reclaim_timer.function) ++ del_timer_sync(&q->tx_reclaim_timer); ++ if (q->rx_reclaim_timer.function) ++ del_timer_sync(&q->rx_reclaim_timer); + + for (i = 0; i < SGE_RXQ_PER_SET; ++i) + if (q->fl[i].desc) { +- spin_lock_irq(&adapter->sge.reg_lock); ++ spin_lock(&adapter->sge.reg_lock); + t3_sge_disable_fl(adapter, q->fl[i].cntxt_id); +- spin_unlock_irq(&adapter->sge.reg_lock); ++ spin_unlock(&adapter->sge.reg_lock); + free_rx_bufs(pdev, &q->fl[i]); + kfree(q->fl[i].sdesc); ++#ifndef LINUX_2_4 + dma_free_coherent(&pdev->dev, +- q->fl[i].size * +- sizeof(struct rx_desc), q->fl[i].desc, +- q->fl[i].phys_addr); ++#else ++ pci_free_consistent(pdev, ++#endif ++ q->fl[i].size * sizeof(struct rx_desc), ++ q->fl[i].desc, q->fl[i].phys_addr); + } + + for (i = 0; i < SGE_TXQ_PER_SET; ++i) + if (q->txq[i].desc) { +- spin_lock_irq(&adapter->sge.reg_lock); ++ spin_lock(&adapter->sge.reg_lock); + t3_sge_enable_ecntxt(adapter, q->txq[i].cntxt_id, 0); +- spin_unlock_irq(&adapter->sge.reg_lock); ++ spin_unlock(&adapter->sge.reg_lock); + if (q->txq[i].sdesc) { + free_tx_desc(adapter, &q->txq[i], + q->txq[i].in_use); + kfree(q->txq[i].sdesc); + } ++#ifndef LINUX_2_4 + dma_free_coherent(&pdev->dev, +- q->txq[i].size * +- sizeof(struct tx_desc), +- q->txq[i].desc, q->txq[i].phys_addr); ++#else ++ pci_free_consistent(pdev, ++#endif ++ q->txq[i].size * sizeof(struct tx_desc), ++ q->txq[i].desc, q->txq[i].phys_addr); + __skb_queue_purge(&q->txq[i].sendq); + } + ++ kfree(q->txq[TXQ_ETH].eth_coalesce_sdesc); ++ + if (q->rspq.desc) { +- spin_lock_irq(&adapter->sge.reg_lock); ++ spin_lock(&adapter->sge.reg_lock); + t3_sge_disable_rspcntxt(adapter, q->rspq.cntxt_id); +- spin_unlock_irq(&adapter->sge.reg_lock); ++ spin_unlock(&adapter->sge.reg_lock); ++#ifndef LINUX_2_4 + dma_free_coherent(&pdev->dev, ++#else ++ pci_free_consistent(pdev, ++#endif + q->rspq.size * sizeof(struct rsp_desc), + q->rspq.desc, q->rspq.phys_addr); + } +@@ -675,7 +799,7 @@ + */ + static inline unsigned int sgl_len(unsigned int n) + { +- /* alternatively: 3 * (n / 2) + 2 * (n & 1) */ ++ // alternatively: 3 * (n / 2) + 2 * (n & 1) + return (3 * n) / 2 + (n & 1); + } + +@@ -707,7 +831,7 @@ + * threshold and the packet is too big to copy, or (b) the packet should + * be copied but there is no memory for the copy. + */ +-static struct sk_buff *get_packet(struct adapter *adap, struct sge_fl *fl, ++static struct sk_buff *get_packet(adapter_t *adap, struct sge_fl *fl, + unsigned int len, unsigned int drop_thres) + { + struct sk_buff *skb = NULL; +@@ -723,7 +847,7 @@ + pci_dma_sync_single_for_cpu(adap->pdev, + pci_unmap_addr(sd, dma_addr), len, + PCI_DMA_FROMDEVICE); +- memcpy(skb->data, sd->skb->data, len); ++ skb_copy_from_linear_data(sd->skb, skb->data, len); + pci_dma_sync_single_for_device(adap->pdev, + pci_unmap_addr(sd, dma_addr), len, + PCI_DMA_FROMDEVICE); +@@ -734,7 +858,9 @@ + return skb; + } + +- if (unlikely(fl->credits < drop_thres)) ++ if (unlikely(fl->credits < drop_thres) && ++ refill_fl(adap, fl, min(MAX_RX_REFILL, fl->size - fl->credits - 1), ++ GFP_ATOMIC | FL_GFP_FLAGS) == 0) + goto recycle; + + use_orig_buf: +@@ -764,13 +890,11 @@ + * Note: this function is similar to @get_packet but deals with Rx buffers + * that are page chunks rather than sk_buffs. + */ +-static struct sk_buff *get_packet_pg(struct adapter *adap, struct sge_fl *fl, +- struct sge_rspq *q, unsigned int len, +- unsigned int drop_thres) ++static struct sk_buff *get_packet_pg(adapter_t *adap, struct sge_fl *fl, struct sge_rspq *q, ++ unsigned int len, unsigned int drop_thres) + { + struct sk_buff *newskb, *skb; + struct rx_sw_desc *sd = &fl->sdesc[fl->cidx]; +- + newskb = skb = q->pg_skb; + + if (!skb && (len <= SGE_RX_COPY_THRES)) { +@@ -793,11 +917,12 @@ + return newskb; + } + +- if (unlikely(q->rx_recycle_buf || (!skb && fl->credits <= drop_thres))) ++ if (q->rx_recycle_buf || (!skb && unlikely(fl->credits <= drop_thres))) + goto recycle; + + if (!skb) + newskb = alloc_skb(SGE_RX_PULL_LEN, GFP_ATOMIC); ++ + if (unlikely(!newskb)) { + if (!drop_thres) + return NULL; +@@ -810,18 +935,18 @@ + __skb_put(newskb, SGE_RX_PULL_LEN); + memcpy(newskb->data, sd->pg_chunk.va, SGE_RX_PULL_LEN); + skb_fill_page_desc(newskb, 0, sd->pg_chunk.page, +- sd->pg_chunk.offset + SGE_RX_PULL_LEN, +- len - SGE_RX_PULL_LEN); ++ sd->pg_chunk.offset + SGE_RX_PULL_LEN, ++ len - SGE_RX_PULL_LEN); + newskb->len = len; + newskb->data_len = len - SGE_RX_PULL_LEN; +- } else { +- skb_fill_page_desc(newskb, skb_shinfo(newskb)->nr_frags, +- sd->pg_chunk.page, +- sd->pg_chunk.offset, len); ++ newskb->truesize += newskb->data_len; ++ } else { ++ skb_fill_page_desc(newskb, skb_shinfo(newskb)->nr_frags, sd->pg_chunk.page, ++ sd->pg_chunk.offset, len); + newskb->len += len; + newskb->data_len += len; +- } +- newskb->truesize += newskb->data_len; ++ newskb->truesize += len; ++ } + + fl->credits--; + /* +@@ -863,8 +988,11 @@ + return 1; + + flits = sgl_len(skb_shinfo(skb)->nr_frags + 1) + 2; ++#ifndef NETIF_F_TSO_FAKE ++ /* TSO supported */ + if (skb_shinfo(skb)->gso_size) + flits++; ++#endif + return flits_to_desc(flits); + } + +@@ -897,10 +1025,20 @@ + nfrags = skb_shinfo(skb)->nr_frags; + for (i = 0; i < nfrags; i++) { + skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ int size = frag->size; ++ ++ /* ++ * frag->size might be a 16 bit integer, which is a problem ++ * for 64K page size configurations. Assuming the current ++ * page is valid, fix up a zeroed size to the page size. ++ */ ++ if (PAGE_SIZE == 65536) ++ if (!size) ++ size = PAGE_SIZE; + + mapping = pci_map_page(pdev, frag->page, frag->page_offset, +- frag->size, PCI_DMA_TODEVICE); +- sgp->len[j] = cpu_to_be32(frag->size); ++ size, PCI_DMA_TODEVICE); ++ sgp->len[j] = cpu_to_be32(size); + sgp->addr[j] = cpu_to_be64(mapping); + j ^= 1; + if (j == 0) +@@ -923,17 +1061,21 @@ + * + * When GTS is disabled we unconditionally ring the doorbell. + */ +-static inline void check_ring_tx_db(struct adapter *adap, struct sge_txq *q) ++static inline void check_ring_tx_db(adapter_t *adap, struct sge_txq *q) + { + #if USE_GTS + clear_bit(TXQ_LAST_PKT_DB, &q->flags); + if (test_and_set_bit(TXQ_RUNNING, &q->flags) == 0) { + set_bit(TXQ_LAST_PKT_DB, &q->flags); ++#ifdef T3_TRACE ++ T3_TRACE1(adap->tb[q->cntxt_id & 7], "doorbell Tx, cntxt %d", ++ q->cntxt_id); ++#endif + t3_write_reg(adap, A_SG_KDOORBELL, + F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id)); + } + #else +- wmb(); /* write descriptors before telling HW */ ++ wmb(); /* write descriptors before telling HW */ + t3_write_reg(adap, A_SG_KDOORBELL, + F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id)); + #endif +@@ -970,8 +1112,8 @@ + const struct sge_txq *q, + const struct sg_ent *sgl, + unsigned int flits, unsigned int sgl_flits, +- unsigned int gen, __be32 wr_hi, +- __be32 wr_lo) ++ unsigned int gen, unsigned int wr_hi, ++ unsigned int wr_lo) + { + struct work_request_hdr *wrp = (struct work_request_hdr *)d; + struct tx_sw_desc *sd = &q->sdesc[pidx]; +@@ -979,12 +1121,12 @@ + sd->skb = skb; + if (need_skb_unmap()) { + sd->fragidx = 0; +- sd->addr_idx = 0; ++ sd->addr_idx_coalesce_num = 0; + sd->sflit = flits; + } + + if (likely(ndesc == 1)) { +- sd->eop = 1; ++ sd->eop_coalesce = LAST_PKT_DESC; + wrp->wr_hi = htonl(F_WR_SOP | F_WR_EOP | V_WR_DATATYPE(1) | + V_WR_SGLSFLT(flits)) | wr_hi; + wmb(); +@@ -1012,7 +1154,7 @@ + + fp += avail; + d++; +- sd->eop = 0; ++ sd->eop_coalesce = 0; + sd++; + if (++pidx == q->size) { + pidx = 0; +@@ -1031,7 +1173,7 @@ + wr_gen2(d, gen); + flits = 1; + } +- sd->eop = 1; ++ sd->eop_coalesce = LAST_PKT_DESC; + wrp->wr_hi |= htonl(F_WR_EOP); + wmb(); + wp->wr_lo = htonl(V_WR_LEN(WR_FLITS) | V_WR_GEN(ogen)) | wr_lo; +@@ -1044,7 +1186,7 @@ + * write_tx_pkt_wr - write a TX_PKT work request + * @adap: the adapter + * @skb: the packet to send +- * @pi: the egress interface ++ * @pi: the egress interface port structure + * @pidx: index of the first Tx descriptor to write + * @gen: the generation value to use + * @q: the Tx queue +@@ -1053,41 +1195,52 @@ + * + * Generate a TX_PKT work request to send the supplied packet. + */ +-static void write_tx_pkt_wr(struct adapter *adap, struct sk_buff *skb, ++static void write_tx_pkt_wr(adapter_t *adap, struct sk_buff *skb, + const struct port_info *pi, + unsigned int pidx, unsigned int gen, + struct sge_txq *q, unsigned int ndesc, + unsigned int compl) + { +- unsigned int flits, sgl_flits, cntrl, tso_info; ++ unsigned int flits, sgl_flits, cntrl, tso_info, obey_port; + struct sg_ent *sgp, sgl[MAX_SKB_FRAGS / 2 + 1]; + struct tx_desc *d = &q->desc[pidx]; + struct cpl_tx_pkt *cpl = (struct cpl_tx_pkt *)d; + +- cpl->len = htonl(skb->len | 0x80000000); +- cntrl = V_TXPKT_INTF(pi->port_id); ++ if (adap->params.chan_map == 3 && adap->port[pi->port_id]->master) ++ obey_port = 0x80000000; ++ else ++ obey_port = 0; ++ cpl->len = htonl(skb->len | obey_port); ++ ++ cntrl = V_TXPKT_INTF(pi->txpkt_intf); + + if (vlan_tx_tag_present(skb) && pi->vlan_grp) + cntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(vlan_tx_tag_get(skb)); + ++#ifdef NETIF_F_TSO_FAKE ++ /* TSO not supported */ ++ tso_info = 0; ++#else ++ /* TSO supported */ + tso_info = V_LSO_MSS(skb_shinfo(skb)->gso_size); ++#endif + if (tso_info) { + int eth_type; +- struct cpl_tx_pkt_lso *hdr = (struct cpl_tx_pkt_lso *)cpl; ++ struct cpl_tx_pkt_lso *hdr = (struct cpl_tx_pkt_lso *) cpl; + + d->flit[2] = 0; + cntrl |= V_TXPKT_OPCODE(CPL_TX_PKT_LSO); + hdr->cntrl = htonl(cntrl); + eth_type = skb_network_offset(skb) == ETH_HLEN ? +- CPL_ETH_II : CPL_ETH_II_VLAN; ++ CPL_ETH_II : CPL_ETH_II_VLAN; + tso_info |= V_LSO_ETH_TYPE(eth_type) | +- V_LSO_IPHDR_WORDS(ip_hdr(skb)->ihl) | +- V_LSO_TCPHDR_WORDS(tcp_hdr(skb)->doff); ++ V_LSO_IPHDR_WORDS(ip_hdr(skb)->ihl) | ++ V_LSO_TCPHDR_WORDS(tcp_hdr(skb)->doff); + hdr->lso_info = htonl(tso_info); + flits = 3; + } else { + cntrl |= V_TXPKT_OPCODE(CPL_TX_PKT); +- cntrl |= F_TXPKT_IPCSUM_DIS; /* SW calculates IP csum */ ++ cntrl |= F_TXPKT_IPCSUM_DIS; /* SW calculates IP csum */ + cntrl |= V_TXPKT_L4CSUM_DIS(skb->ip_summed != CHECKSUM_PARTIAL); + cpl->cntrl = htonl(cntrl); + +@@ -1101,8 +1254,8 @@ + + flits = (skb->len + 7) / 8 + 2; + cpl->wr.wr_hi = htonl(V_WR_BCNTLFLT(skb->len & 7) | +- V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) +- | F_WR_SOP | F_WR_EOP | compl); ++ V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | ++ F_WR_SOP | F_WR_EOP | compl); + wmb(); + cpl->wr.wr_lo = htonl(V_WR_LEN(flits) | V_WR_GEN(gen) | + V_WR_TID(q->token)); +@@ -1115,19 +1268,138 @@ + } + + sgp = ndesc == 1 ? (struct sg_ent *)&d->flit[flits] : sgl; +- sgl_flits = make_sgl(skb, sgp, skb->data, skb_headlen(skb), adap->pdev); ++ sgl_flits = make_sgl(skb, sgp, skb->data, skb_headlen(skb), ++ adap->pdev); + + write_wr_hdr_sgl(ndesc, skb, d, pidx, q, sgl, flits, sgl_flits, gen, + htonl(V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | compl), + htonl(V_WR_TID(q->token))); + } + +-static inline void t3_stop_queue(struct net_device *dev, struct sge_qset *qs, +- struct sge_txq *q) +-{ +- netif_stop_queue(dev); +- set_bit(TXQ_ETH, &qs->txq_stopped); +- q->stops++; ++/** ++ * finalize_tx_pkt_coalesce_wr - complete a tx pkt coalesce wr ++ * @q: the Tx queue ++ */ ++static inline void finalize_tx_pkt_coalesce_wr(struct sge_txq *q) ++{ ++ ++ struct work_request_hdr *wrp = ++ (struct work_request_hdr *)&q->desc[q->pidx]; ++ ++ wmb(); ++ wrp->wr_lo = ++ htonl(V_WR_GEN(q->gen) | V_WR_TID(q->token) | ++ V_WR_LEN(1 + (q->eth_coalesce_idx << 1))); ++ wr_gen2((struct tx_desc *)wrp, q->gen); ++} ++ ++/** ++ * ship_tx_pkt_coalesce_wr - ship a tx pkt coalesce wr ++ * @adap: the adapter ++ * @q: the Tx queue ++ */ ++static inline void ship_tx_pkt_coalesce_wr(adapter_t *adap, struct sge_txq *q) ++{ ++ finalize_tx_pkt_coalesce_wr(q); ++ check_ring_tx_db(adap, q); ++ ++ q->eth_coalesce_idx = 0; ++ q->eth_coalesce_bytes = 0; ++ ++ q->pidx++; ++ if (q->pidx >= q->size) { ++ q->pidx -= q->size; ++ q->gen ^= 1; ++ } ++} ++ ++/** ++ * try_finalize_tx_pkt_coalesce_wr - try sending a pend. tx pkt coalesce wr ++ * @adap: the adapter ++ * @q: the Tx queue ++ */ ++static void try_finalize_tx_pkt_coalesce_wr(adapter_t *adap, struct sge_txq *q) ++{ ++ if (spin_trylock(&q->lock)) { ++ ++ if (q->eth_coalesce_idx) ++ ship_tx_pkt_coalesce_wr(adap, q); ++ ++ spin_unlock(&q->lock); ++ } ++} ++ ++/** ++ * should_finalize_tx_pkt_coalescing - is it time to stop coalescing ++ * @q: the Tx queue ++ */ ++static inline int should_finalize_tx_pkt_coalescing(const struct sge_txq *q) ++{ ++ unsigned int r = q->processed - q->cleaned; ++ ++ return q->in_use - r < (q->size >> 3); ++} ++ ++/** ++ * write_tx_pkt_coalesce_wr - write a TX_PKT coalesce work request ++ * @adap: the adapter ++ * @skb: the packet to send ++ * @pi: the egress interface port structure ++ * @pidx: index of the first Tx descriptor to write ++ * @gen: the generation value to use ++ * @q: the Tx queue ++ * @compl: the value of the COMPL bit to use ++ * @coalesce_idx: idx in the coalesce WR ++ * ++ * Generate a TX_PKT work request to send the supplied packet. ++ */ ++static inline void write_tx_pkt_coalesce_wr(adapter_t *adap, ++ struct sk_buff *skb, ++ const struct port_info *pi, ++ unsigned int pidx, ++ unsigned int gen, ++ struct sge_txq *q, ++ unsigned int compl, ++ unsigned int coalesce_idx) ++{ ++ struct tx_pkt_coalesce_wr *wr = ++ (struct tx_pkt_coalesce_wr *)&q->desc[pidx]; ++ struct cpl_tx_pkt_coalesce *cpl = &wr->cpl[coalesce_idx]; ++ struct tx_sw_desc *sd = &q->sdesc[pidx]; ++ unsigned int cntrl, len = skb->len; ++ ++ if (!coalesce_idx) { ++ wr->wr.wr_hi = ++ htonl(V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | F_WR_SOP | F_WR_EOP | ++ V_WR_DATATYPE(1) | compl); ++ sd->eop_coalesce = PKT_COALESCE_WR; ++ sd->skb = ETH_COALESCE_DUMMY_SKB; ++ } ++ sd->addr_idx_coalesce_num = coalesce_idx + 1; ++ q->eth_coalesce_sdesc[pidx].skb[coalesce_idx] = skb; ++ ++ cntrl = ++ V_TXPKT_OPCODE(CPL_TX_PKT) | V_TXPKT_INTF(pi->txpkt_intf) | ++ F_TXPKT_IPCSUM_DIS | ++ V_TXPKT_L4CSUM_DIS(skb->ip_summed != CHECKSUM_PARTIAL); ++ ++ if (vlan_tx_tag_present(skb) && pi->vlan_grp) ++ cntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(vlan_tx_tag_get(skb)); ++ ++ cpl->cntrl = htonl(cntrl); ++ cpl->len = htonl(len | 0x81000000); ++ ++ if (skb_headlen(skb)) { ++ cpl->addr = ++ cpu_to_be64(pci_map_single(adap->pdev, skb->data, len, ++ PCI_DMA_TODEVICE)); ++ } else { ++ skb_frag_t *frag = skb_shinfo(skb)->frags; ++ ++ cpl->addr = ++ cpu_to_be64(pci_map_page(adap->pdev, frag->page, ++ frag->page_offset, len, PCI_DMA_TODEVICE)); ++ } + } + + /** +@@ -1139,7 +1411,9 @@ + */ + int t3_eth_xmit(struct sk_buff *skb, struct net_device *dev) + { +- unsigned int ndesc, pidx, credits, gen, compl; ++ unsigned int ndesc, pidx, pidx_ndesc, credits, gen, compl, ++ len = skb->len; ++ int coalesce_idx = -1; + const struct port_info *pi = netdev_priv(dev); + struct adapter *adap = pi->adapter; + struct sge_qset *qs = pi->qs; +@@ -1149,58 +1423,136 @@ + * The chip min packet length is 9 octets but play safe and reject + * anything shorter than an Ethernet header. + */ +- if (unlikely(skb->len < ETH_HLEN)) { ++ if (unlikely(len < ETH_HLEN)) { + dev_kfree_skb(skb); + return NETDEV_TX_OK; + } + +- spin_lock(&q->lock); +- reclaim_completed_tx(adap, q); ++ if (spin_trylock(&q->lock)) ++ reclaim_completed_tx(adap, q, TX_RECLAIM_CHUNK); ++ else ++ return NETDEV_TX_LOCKED; + + credits = q->size - q->in_use; +- ndesc = calc_tx_descs(skb); ++ ++#ifdef T3_TRACE ++ T3_TRACE5(adap->tb[q->cntxt_id & 7], ++ "t3_eth_xmit: len %u headlen %u frags %u idx %u bytes %u", ++ len, skb_headlen(skb), skb_shinfo(skb)->nr_frags, ++ q->eth_coalesce_idx, q->eth_coalesce_bytes); ++#endif ++ /* If the Tx descriptor ring is filling up we try to coalesce small ++ * outgoing packets into a single WR. The coalesce WR format doesn't ++ * handle fragmented skbs but that is unlikely anyway for small pkts. ++ * The benefit of coalescing are manifold, including more efficiency ++ * on the IO bus as well as more efficient processing in the T3 ++ * silicon. ++ */ ++ if ((skb_shinfo(skb)->nr_frags < 2) && ++ ((skb_shinfo(skb)->nr_frags == 1) ^ !!skb_headlen(skb)) && ++ ((q->eth_coalesce_idx || credits < (q->size >> 1)) && ++ (q->eth_coalesce_bytes + len < 11000))) { ++ ++ q->eth_coalesce_bytes += len; ++ coalesce_idx = q->eth_coalesce_idx++; ++ ++ if (!coalesce_idx) { ++ ndesc = 1; ++ qs->port_stats[SGE_PSTAT_TX_COALESCE_WR]++; ++ } else ++ ndesc = 0; ++ ++ qs->port_stats[SGE_PSTAT_TX_COALESCE_PKT]++; ++ pidx_ndesc = 0; ++ } else { ++ if (q->eth_coalesce_idx) ++ ship_tx_pkt_coalesce_wr(adap, q); ++ ++ ndesc = pidx_ndesc = calc_tx_descs(skb); ++ } + + if (unlikely(credits < ndesc)) { +- t3_stop_queue(dev, qs, q); +- dev_err(&adap->pdev->dev, +- "%s: Tx ring %u full while queue awake!\n", +- dev->name, q->cntxt_id & 7); ++ q->eth_coalesce_idx = 0; ++ q->eth_coalesce_bytes = 0; ++ ++ if (!netif_queue_stopped(dev)) { ++ netif_stop_queue(dev); ++ set_bit(TXQ_ETH, &qs->txq_stopped); ++ q->stops++; ++ dev_err(&adap->pdev->dev, ++ "%s: Tx ring %u full while queue awake!\n", ++ dev->name, q->cntxt_id & 7); ++ } + spin_unlock(&q->lock); + return NETDEV_TX_BUSY; + } + + q->in_use += ndesc; + if (unlikely(credits - ndesc < q->stop_thres)) { +- t3_stop_queue(dev, qs, q); +- ++ q->stops++; ++ netif_stop_queue(dev); ++ set_bit(TXQ_ETH, &qs->txq_stopped); ++#if !USE_GTS + if (should_restart_tx(q) && + test_and_clear_bit(TXQ_ETH, &qs->txq_stopped)) { + q->restarts++; + netif_wake_queue(dev); + } ++#endif + } + + gen = q->gen; + q->unacked += ndesc; +- compl = (q->unacked & 8) << (S_WR_COMPL - 3); +- q->unacked &= 7; ++#ifdef CHELSIO_FREE_TXBUF_ASAP ++ /* ++ * Some Guest OS clients get terrible performance when they have bad ++ * message size / socket send buffer space parameters. For instance, ++ * if an application selects an 8KB message size and an 8KB send ++ * socket buffer size. This forces the application into a single ++ * packet stop-and-go mode where it's only willing to have a single ++ * message outstanding. The next message is only sent when the ++ * previous message is noted as having been sent. Until we issue a ++ * kfree_skb() against the TX skb, the skb is charged against the ++ * application's send buffer space. We only free up TX skbs when we ++ * get a TX credit return from the hardware / firmware which is fairly ++ * lazy about this. So we request a TX WR Completion Notification on ++ * every TX descriptor in order to accellerate TX credit returns. See ++ * also the change in handle_rsp_cntrl_info() to free up TX skb's when ++ * we receive the TX WR Completion Notifications ... ++ */ ++ compl = F_WR_COMPL; ++#else ++ compl = (q->unacked & 32) << (S_WR_COMPL - 5); ++#endif ++ q->unacked &= 31; ++ + pidx = q->pidx; +- q->pidx += ndesc; ++ q->pidx += pidx_ndesc; + if (q->pidx >= q->size) { + q->pidx -= q->size; + q->gen ^= 1; + } + ++#ifdef T3_TRACE ++// T3_TRACE5(adap->tb[q->cntxt_id & 7], ++// "eth_xmit: ndesc %u, credits %u, pidx %u, len %u, frags %u", ++// ndesc, credits, pidx, skb->len, skb_shinfo(skb)->nr_frags); ++#endif + /* update port statistics */ +- if (skb->ip_summed == CHECKSUM_COMPLETE) ++ if (skb->ip_summed == CHECKSUM_PARTIAL) + qs->port_stats[SGE_PSTAT_TX_CSUM]++; ++#ifndef NETIF_F_TSO_FAKE ++ /* TSO supported */ + if (skb_shinfo(skb)->gso_size) + qs->port_stats[SGE_PSTAT_TSO]++; ++#endif + if (vlan_tx_tag_present(skb) && pi->vlan_grp) + qs->port_stats[SGE_PSTAT_VLANINS]++; + + dev->trans_start = jiffies; +- spin_unlock(&q->lock); ++ ++ if (coalesce_idx < 0) ++ spin_unlock(&q->lock); + + /* + * We do not use Tx completion interrupts to free DMAd Tx packets. +@@ -1228,9 +1580,18 @@ + */ + if (likely(!skb_shared(skb))) + skb_orphan(skb); +- +- write_tx_pkt_wr(adap, skb, pi, pidx, gen, q, ndesc, compl); +- check_ring_tx_db(adap, q); ++ if (coalesce_idx >= 0) { ++ write_tx_pkt_coalesce_wr(adap, skb, pi, pidx, gen, q, ++ compl, coalesce_idx); ++ ++ if (coalesce_idx == ETH_COALESCE_PKT_NUM - 1) ++ ship_tx_pkt_coalesce_wr(adap, q); ++ ++ spin_unlock(&q->lock); ++ } else { ++ write_tx_pkt_wr(adap, skb, pi, pidx, gen, q, ndesc, compl); ++ check_ring_tx_db(adap, q); ++ } + return NETDEV_TX_OK; + } + +@@ -1284,12 +1645,12 @@ + * needs to retry because there weren't enough descriptors at the + * beginning of the call but some freed up in the mean time. + */ +-static inline int check_desc_avail(struct adapter *adap, struct sge_txq *q, ++static inline int check_desc_avail(adapter_t *adap, struct sge_txq *q, + struct sk_buff *skb, unsigned int ndesc, + unsigned int qid) + { + if (unlikely(!skb_queue_empty(&q->sendq))) { +- addq_exit:__skb_queue_tail(&q->sendq, skb); ++addq_exit: __skb_queue_tail(&q->sendq, skb); + return 1; + } + if (unlikely(q->size - q->in_use < ndesc)) { +@@ -1324,6 +1685,13 @@ + q->cleaned += reclaim; + } + ++/** ++ * immediate - check whether a packet can be sent as immediate data ++ * @skb: the packet ++ * ++ * Returns true if a packet can be sent as a WR with immediate data. ++ * Currently this happens if the packet fits in one Tx descriptor. ++ */ + static inline int immediate(const struct sk_buff *skb) + { + return skb->len <= WR_LEN; +@@ -1339,8 +1707,7 @@ + * a control queue must fit entirely as immediate data in a single Tx + * descriptor and have no page fragments. + */ +-static int ctrl_xmit(struct adapter *adap, struct sge_txq *q, +- struct sk_buff *skb) ++static int ctrl_xmit(adapter_t *adap, struct sge_txq *q, struct sk_buff *skb) + { + int ret; + struct work_request_hdr *wrp = (struct work_request_hdr *)skb->data; +@@ -1355,7 +1722,7 @@ + wrp->wr_lo = htonl(V_WR_TID(q->token)); + + spin_lock(&q->lock); +- again:reclaim_completed_tx_imm(q); ++again: reclaim_completed_tx_imm(q); + + ret = check_desc_avail(adap, q, skb, 1, TXQ_CTRL); + if (unlikely(ret)) { +@@ -1382,7 +1749,7 @@ + + /** + * restart_ctrlq - restart a suspended control queue +- * @qs: the queue set cotaining the control queue ++ * @data: the queue set cotaining the control queue + * + * Resumes transmission on a suspended Tx control queue. + */ +@@ -1393,7 +1760,7 @@ + struct sge_txq *q = &qs->txq[TXQ_CTRL]; + + spin_lock(&q->lock); +- again:reclaim_completed_tx_imm(q); ++again: reclaim_completed_tx_imm(q); + + while (q->in_use < q->size && + (skb = __skb_dequeue(&q->sendq)) != NULL) { +@@ -1423,16 +1790,20 @@ + F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id)); + } + +-/* +- * Send a management message through control queue 0 ++/** ++ * t3_mgmt_tx - send a management message ++ * @adap: the adapter ++ * @skb: the packet containing the management message ++ * ++ * Send a management message through control queue 0. + */ + int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb) + { + int ret; ++ + local_bh_disable(); + ret = ctrl_xmit(adap, &adap->sge.qs[0].txq[TXQ_CTRL], skb); + local_bh_enable(); +- + return ret; + } + +@@ -1460,9 +1831,21 @@ + PCI_DMA_TODEVICE); + + si = skb_shinfo(skb); +- for (i = 0; i < si->nr_frags; i++) +- pci_unmap_page(dui->pdev, *p++, si->frags[i].size, ++ for (i = 0; i < si->nr_frags; i++) { ++ /* ++ * frag->size might be a 16 bit integer, which is a problem ++ * for 64K page size configurations. Assuming the current ++ * page is valid, fix up a zeroed size to the page size. ++ */ ++ int size = si->frags[i].size; ++ ++ if (PAGE_SIZE == 65536) ++ if (!size) ++ size = PAGE_SIZE; ++ ++ pci_unmap_page(dui->pdev, *p++, size, + PCI_DMA_TODEVICE); ++ } + } + + static void setup_deferred_unmapping(struct sk_buff *skb, struct pci_dev *pdev, +@@ -1493,7 +1876,7 @@ + * Write an offload work request to send the supplied packet. The packet + * data already carry the work request with most fields populated. + */ +-static void write_ofld_wr(struct adapter *adap, struct sk_buff *skb, ++static void write_ofld_wr(adapter_t *adap, struct sk_buff *skb, + struct sge_txq *q, unsigned int pidx, + unsigned int gen, unsigned int ndesc) + { +@@ -1518,12 +1901,11 @@ + sgp = ndesc == 1 ? (struct sg_ent *)&d->flit[flits] : sgl; + sgl_flits = make_sgl(skb, sgp, skb_transport_header(skb), + skb->tail - skb->transport_header, +- adap->pdev); ++ adap->pdev); + if (need_skb_unmap()) { + setup_deferred_unmapping(skb, adap->pdev, sgp, sgl_flits); + skb->destructor = deferred_unmap_destructor; + } +- + write_wr_hdr_sgl(ndesc, skb, d, pidx, q, sgl, flits, sgl_flits, + gen, from->wr_hi, from->wr_lo); + } +@@ -1540,9 +1922,9 @@ + unsigned int flits, cnt; + + if (skb->len <= WR_LEN) +- return 1; /* packet fits as immediate data */ +- +- flits = skb_transport_offset(skb) / 8; /* headers */ ++ return 1; /* packet fits as immediate data */ ++ ++ flits = skb_transport_offset(skb) / 8; /* headers */ + cnt = skb_shinfo(skb)->nr_frags; + if (skb->tail != skb->transport_header) + cnt++; +@@ -1557,19 +1939,18 @@ + * + * Send an offload packet through an SGE offload queue. + */ +-static int ofld_xmit(struct adapter *adap, struct sge_txq *q, +- struct sk_buff *skb) ++static int ofld_xmit(adapter_t *adap, struct sge_txq *q, struct sk_buff *skb) + { + int ret; + unsigned int ndesc = calc_tx_descs_ofld(skb), pidx, gen; + + spin_lock(&q->lock); +- again:reclaim_completed_tx(adap, q); ++again: reclaim_completed_tx(adap, q, TX_RECLAIM_CHUNK); + + ret = check_desc_avail(adap, q, skb, ndesc, TXQ_OFLD); + if (unlikely(ret)) { + if (ret == 1) { +- skb->priority = ndesc; /* save for restart */ ++ skb->priority = ndesc; /* save for restart */ + spin_unlock(&q->lock); + return NET_XMIT_CN; + } +@@ -1584,6 +1965,12 @@ + q->pidx -= q->size; + q->gen ^= 1; + } ++#ifdef T3_TRACE ++ T3_TRACE5(adap->tb[q->cntxt_id & 7], ++ "ofld_xmit: ndesc %u, pidx %u, len %u, main %u, frags %u", ++ ndesc, pidx, skb->len, skb->len - skb->data_len, ++ skb_shinfo(skb)->nr_frags); ++#endif + spin_unlock(&q->lock); + + write_ofld_wr(adap, skb, q, pidx, gen, ndesc); +@@ -1593,7 +1980,7 @@ + + /** + * restart_offloadq - restart a suspended offload queue +- * @qs: the queue set cotaining the offload queue ++ * @data: the queue set cotaining the offload queue + * + * Resumes transmission on a suspended Tx offload queue. + */ +@@ -1602,11 +1989,9 @@ + struct sk_buff *skb; + struct sge_qset *qs = (struct sge_qset *)data; + struct sge_txq *q = &qs->txq[TXQ_OFLD]; +- const struct port_info *pi = netdev_priv(qs->netdev); +- struct adapter *adap = pi->adapter; +- +- spin_lock(&q->lock); +- again:reclaim_completed_tx(adap, q); ++ ++ spin_lock(&q->lock); ++again: reclaim_completed_tx(qs->adap, q, TX_RECLAIM_CHUNK); + + while ((skb = skb_peek(&q->sendq)) != NULL) { + unsigned int gen, pidx; +@@ -1634,7 +2019,7 @@ + __skb_unlink(skb, &q->sendq); + spin_unlock(&q->lock); + +- write_ofld_wr(adap, skb, q, pidx, gen, ndesc); ++ write_ofld_wr(qs->adap, skb, q, pidx, gen, ndesc); + spin_lock(&q->lock); + } + spin_unlock(&q->lock); +@@ -1644,7 +2029,7 @@ + set_bit(TXQ_LAST_PKT_DB, &q->flags); + #endif + wmb(); +- t3_write_reg(adap, A_SG_KDOORBELL, ++ t3_write_reg(qs->adap, A_SG_KDOORBELL, + F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id)); + } + +@@ -1683,7 +2068,7 @@ + */ + int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb) + { +- struct adapter *adap = tdev2adap(tdev); ++ adapter_t *adap = tdev2adap(tdev); + struct sge_qset *qs = &adap->sge.qs[queue_set(skb)]; + + if (unlikely(is_ctrl_pkt(skb))) +@@ -1708,8 +2093,12 @@ + q->rx_tail->next = skb; + else { + struct sge_qset *qs = rspq_to_qset(q); +- ++#if defined(NAPI_UPDATE) + napi_schedule(&qs->napi); ++#else ++ if (__netif_rx_schedule_prep(qs->netdev)) ++ __netif_rx_schedule(qs->netdev); ++#endif + q->rx_head = skb; + } + q->rx_tail = skb; +@@ -1730,7 +2119,7 @@ + { + if (n) { + q->offload_bundles++; +- tdev->recv(tdev, skbs, n); ++ cxgb3_ofld_recv(tdev, skbs, n); + } + } + +@@ -1745,53 +2134,78 @@ + * receive handler. Batches need to be of modest size as we do prefetches + * on the packets in each. + */ +-static int ofld_poll(struct napi_struct *napi, int budget) +-{ +- struct sge_qset *qs = container_of(napi, struct sge_qset, napi); ++DECLARE_OFLD_POLL(napi, dev, budget) ++{ ++ struct sge_qset *qs = SGE_GET_OFLD_QS(napi, dev); + struct sge_rspq *q = &qs->rspq; + struct adapter *adapter = qs->adap; +- int work_done = 0; +- +- while (work_done < budget) { ++ ++#if defined(NAPI_UPDATE) ++ int limit = budget; ++#else ++ int limit = min(*budget, dev->quota); ++#endif ++ int work_done, avail = limit; ++ ++ while (avail) { + struct sk_buff *head, *tail, *skbs[RX_BUNDLE_SIZE]; + int ngathered; +- +- spin_lock_irq(&q->lock); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&q->lock, flags); + head = q->rx_head; + if (!head) { ++ work_done = limit - avail; ++#if defined(NAPI_UPDATE) + napi_complete(napi); +- spin_unlock_irq(&q->lock); ++#else ++ *budget -= work_done; ++ dev->quota -= work_done; ++ __netif_rx_complete(dev); ++#endif ++ spin_unlock_irqrestore(&q->lock, flags); ++#if defined(NAPI_UPDATE) + return work_done; ++#else ++ return 0; ++#endif + } + + tail = q->rx_tail; + q->rx_head = q->rx_tail = NULL; +- spin_unlock_irq(&q->lock); +- +- for (ngathered = 0; work_done < budget && head; work_done++) { ++ spin_unlock_irqrestore(&q->lock, flags); ++ ++ for (ngathered = 0; avail && head; avail--) { + prefetch(head->data); + skbs[ngathered] = head; + head = head->next; + skbs[ngathered]->next = NULL; + if (++ngathered == RX_BUNDLE_SIZE) { + q->offload_bundles++; +- adapter->tdev.recv(&adapter->tdev, skbs, +- ngathered); ++ cxgb3_ofld_recv(&adapter->tdev, skbs, ++ ngathered); + ngathered = 0; + } + } +- if (head) { /* splice remaining packets back onto Rx queue */ +- spin_lock_irq(&q->lock); ++ if (head) { /* splice remaining packets back onto Rx queue */ ++ spin_lock_irqsave(&q->lock, flags); + tail->next = q->rx_head; + if (!q->rx_head) + q->rx_tail = tail; + q->rx_head = head; +- spin_unlock_irq(&q->lock); ++ spin_unlock_irqrestore(&q->lock, flags); + } + deliver_partial_bundle(&adapter->tdev, q, skbs, ngathered); + } + ++ work_done = limit - avail; ++#if defined(NAPI_UPDATE) + return work_done; ++#else ++ *budget -= work_done; ++ dev->quota -= work_done; ++ return 1; ++#endif + } + + /** +@@ -1816,7 +2230,7 @@ + if (rq->polling) { + rx_gather[gather_idx++] = skb; + if (gather_idx == RX_BUNDLE_SIZE) { +- tdev->recv(tdev, rx_gather, RX_BUNDLE_SIZE); ++ cxgb3_ofld_recv(tdev, rx_gather, RX_BUNDLE_SIZE); + gather_idx = 0; + rq->offload_bundles++; + } +@@ -1897,6 +2311,7 @@ + + arp_send(ARPOP_REPLY, ETH_P_ARP, sip, dev, tip, sha, + dev->dev_addr, sha); ++ + } + + static inline int is_arp(struct sk_buff *skb) +@@ -1910,25 +2325,31 @@ + * @rq: the response queue that received the packet + * @skb: the packet + * @pad: amount of padding at the start of the buffer ++ * @npkts: number of packets aggregated in the skb (>= 1 for LRO) + * + * Process an ingress ethernet pakcet and deliver it to the stack. + * The padding is 2 if the packet was delivered in an Rx buffer and 0 +- * if it was immediate data in a response. +- */ +-static void rx_eth(struct adapter *adap, struct sge_rspq *rq, +- struct sk_buff *skb, int pad, int lro) ++ * if it was immediate data in a response. @npkts represents the number ++ * of Ethernet packets as seen by the device that have been collected in ++ * the @skb; it's > 1 only in the case of LRO. ++ */ ++static void rx_eth(adapter_t *adap, struct sge_rspq *rq, ++ struct sk_buff *skb, int pad, int npkts) + { + struct cpl_rx_pkt *p = (struct cpl_rx_pkt *)(skb->data + pad); + struct sge_qset *qs = rspq_to_qset(rq); + struct port_info *pi; + ++ rq->eth_pkts += npkts; + skb_pull(skb, sizeof(*p) + pad); +- skb->protocol = eth_type_trans(skb, adap->port[p->iff]); ++ skb->dev = adap->port[adap->rxpkt_map[p->iff]]; + skb->dev->last_rx = jiffies; ++ skb->protocol = eth_type_trans(skb, skb->dev); + pi = netdev_priv(skb->dev); +- if (pi->rx_csum_offload && p->csum_valid && p->csum == htons(0xffff) && ++ ++ if (pi->rx_csum_offload && p->csum_valid && p->csum == 0xffff && + !p->fragment) { +- qs->port_stats[SGE_PSTAT_RX_CSUM_GOOD]++; ++ qs->port_stats[SGE_PSTAT_RX_CSUM_GOOD] += npkts; + skb->ip_summed = CHECKSUM_UNNECESSARY; + } else + skb->ip_summed = CHECKSUM_NONE; +@@ -1936,35 +2357,23 @@ + if (unlikely(p->vlan_valid)) { + struct vlan_group *grp = pi->vlan_grp; + +- qs->port_stats[SGE_PSTAT_VLANEX]++; +- if (likely(grp)) +- if (lro) +- lro_vlan_hwaccel_receive_skb(&qs->lro_mgr, skb, +- grp, +- ntohs(p->vlan), +- p); +- else { +- if (unlikely(pi->iscsi_ipv4addr && +- is_arp(skb))) { +- unsigned short vtag = ntohs(p->vlan) & +- VLAN_VID_MASK; +- skb->dev = vlan_group_get_device(grp, +- vtag); +- cxgb3_arp_process(adap, skb); +- } +- __vlan_hwaccel_rx(skb, grp, ntohs(p->vlan), +- rq->polling); +- } +- else ++ qs->port_stats[SGE_PSTAT_VLANEX] += npkts; ++ if (likely(grp != NULL)) { ++ if (unlikely(pi->iscsi_ipv4addr && is_arp(skb))) { ++ unsigned short vtag = ntohs(p->vlan) & ++ VLAN_VID_MASK; ++ skb->dev = vlan_group_get_device(grp, ++ vtag); ++ cxgb3_arp_process(adap, skb); ++ } ++ __vlan_hwaccel_rx(skb, grp, ntohs(p->vlan), ++ rq->polling); ++ } else + dev_kfree_skb_any(skb); + } else if (rq->polling) { +- if (lro) +- lro_receive_skb(&qs->lro_mgr, skb, p); +- else { +- if (unlikely(pi->iscsi_ipv4addr && is_arp(skb))) +- cxgb3_arp_process(adap, skb); +- netif_receive_skb(skb); +- } ++ if (unlikely(pi->iscsi_ipv4addr && is_arp(skb))) ++ cxgb3_arp_process(adap, skb); ++ netif_receive_skb(skb); + } else + netif_rx(skb); + } +@@ -1972,6 +2381,176 @@ + static inline int is_eth_tcp(u32 rss) + { + return G_HASHTYPE(ntohl(rss)) == RSS_HASH_4_TUPLE; ++} ++ ++static inline int lro_active(const struct lro_session *s) ++{ ++ return s->head != NULL; ++} ++ ++/** ++ * lro_match - check if a new packet matches an existing LRO packet ++ * @skb: LRO packet ++ * @iph: pointer to IP header of new packet ++ * ++ * Determine whether a new packet with the given IP header belongs ++ * to the same connection as an existing LRO packet by checking that the ++ * two packets have the same 4-tuple. Note that LRO assumes no IP options. ++ */ ++static inline int lro_match(const struct sk_buff *skb, const struct iphdr *iph) ++{ ++ const struct iphdr *s_iph = ip_hdr(skb); ++ const struct tcphdr *s_tcph = (const struct tcphdr *)(s_iph + 1); ++ const struct tcphdr *tcph = (const struct tcphdr *)(iph + 1); ++ ++ return *(u32 *)&tcph->source == *(u32 *)&s_tcph->source && ++ iph->saddr == s_iph->saddr && iph->daddr == s_iph->daddr; ++} ++ ++/** ++ * lro_lookup - find an LRO session ++ * @p: the LRO state ++ * @idx: index of first session to try ++ * @iph: IP header supplying the session information to look up ++ * ++ * Return an exitsing LRO session that matches the TCP/IP information in ++ * the supplied IP header. @idx is a hint suggesting the first session ++ * to try. If no matching session is found %NULL is returned. ++ */ ++static struct lro_session *lro_lookup(struct lro_state *p, int idx, ++ const struct iphdr *iph) ++{ ++ struct lro_session *s = NULL; ++ unsigned int active = p->nactive; ++ ++ while (active) { ++ s = &p->sess[idx]; ++ if (s->head) { ++ if (lro_match(s->head, iph)) ++ break; ++ active--; ++ } ++ idx = (idx + 1) & (MAX_LRO_SES - 1); ++ } ++ return s; ++} ++ ++#define IPH_OFFSET (2 + ETH_HLEN + sizeof(struct cpl_rx_pkt)) ++ ++/** ++ * lro_init_session - initialize an LRO session ++ * @s: LRO session to initialize ++ * @skb: first packet for the session ++ * @iph: pointer to start of IP header ++ * @vlan: session vlan ++ * @plen: TCP payload length ++ * ++ * Initialize an LRO session with the given packet. ++ */ ++static void lro_init_session(struct lro_session *s, struct sk_buff *skb, ++ struct iphdr *iph, __be32 vlan, int plen) ++{ ++ const struct tcphdr *tcph = (struct tcphdr *)(iph + 1); ++ ++ cxgb3_set_skb_header(skb, iph, IPH_OFFSET); ++ s->head = s->tail = skb; ++ s->iplen = ntohs(iph->tot_len); ++ s->mss = plen; ++ s->seq = ntohl(tcph->seq) + plen; ++ s->vlan = vlan; ++ s->npkts = 1; ++} ++ ++/** ++ * lro_flush_session - complete an LRO session ++ * @adap: the adapter ++ * @qs: the queue set associated with the LRO session ++ * @s: the LRO session ++ * ++ * Complete an active LRO session and send the packet it has been building ++ * upstream. ++ */ ++static void lro_flush_session(struct adapter *adap, struct sge_qset *qs, ++ struct lro_session *s) ++{ ++ struct iphdr *iph = ip_hdr(s->head); ++ ++ if (iph->tot_len != htons(s->iplen)) { ++ /* IP length has changed, fix up IP header */ ++ iph->tot_len = htons(s->iplen); ++ iph->check = 0; ++ iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl); ++#ifndef NETIF_F_TSO_FAKE ++ /* TSO supported */ ++ /* tcp_measure_rcv_mss in recent kernels looks at gso_size */ ++ skb_shinfo(s->head)->gso_size = s->mss; ++#ifdef GSO_TYPE ++ skb_shinfo(s->head)->gso_type = SKB_GSO_TCPV4; ++#endif ++#endif ++ } ++ ++ qs->port_stats[SGE_PSTAT_LRO]++; ++ rx_eth(adap, &qs->rspq, s->head, 2, s->npkts); ++ s->head = NULL; ++ qs->lro.nactive--; ++} ++ ++/** ++ * lro_flush - flush all active LRO sessions ++ * @adap: the adapter ++ * @qs: associated queue set ++ * @state: the LRO state ++ * ++ * Flush all active LRO sessions and reset the LRO state. ++ */ ++static void lro_flush(struct adapter *adap, struct sge_qset *qs, ++ struct lro_state *state) ++{ ++ unsigned int idx = state->active_idx; ++ ++ while (state->nactive) { ++ struct lro_session *s = &state->sess[idx]; ++ ++ if (s->head) ++ lro_flush_session(adap, qs, s); ++ idx = (idx + 1) & (MAX_LRO_SES - 1); ++ } ++} ++ ++/** ++ * lro_alloc_session - allocate a new LRO session ++ * @adap: the adapter ++ * @qs: associated queue set ++ * @hash: hash value for the connection to be associated with the session ++ * ++ * Allocate a new LRO session. If there are no more session slots one of ++ * the existing active sessions is completed and taken over. ++ */ ++static struct lro_session *lro_alloc_session(struct adapter *adap, ++ struct sge_qset *qs, unsigned int hash) ++{ ++ struct lro_state *state = &qs->lro; ++ unsigned int idx = hash & (MAX_LRO_SES - 1); ++ struct lro_session *s = &state->sess[idx]; ++ ++ if (likely(!s->head)) /* session currently inactive, use it */ ++ goto done; ++ ++ if (unlikely(state->nactive == MAX_LRO_SES)) { ++ lro_flush_session(adap, qs, s); ++ qs->port_stats[SGE_PSTAT_LRO_OVFLOW]++; ++ } else { ++ qs->port_stats[SGE_PSTAT_LRO_COLSN]++; ++ do { ++ idx = (idx + 1) & (MAX_LRO_SES - 1); ++ s = &state->sess[idx]; ++ } while (s->head); ++ } ++ ++done: state->nactive++; ++ state->active_idx = idx; ++ return s; + } + + /** +@@ -1992,122 +2571,244 @@ + const struct iphdr *ih = (struct iphdr *)(eh + 1); + + return (*((u8 *)p + 1) & 0x90) == 0x10 && p->csum == htons(0xffff) && +- eh->h_proto == htons(ETH_P_IP) && ih->ihl == (sizeof(*ih) >> 2); +-} +- +-static int t3_get_lro_header(void **eh, void **iph, void **tcph, +- u64 *hdr_flags, void *priv) +-{ +- const struct cpl_rx_pkt *cpl = priv; +- +- if (!lro_frame_ok(cpl)) +- return -1; +- +- *eh = (struct ethhdr *)(cpl + 1); +- *iph = (struct iphdr *)((struct ethhdr *)*eh + 1); +- *tcph = (struct tcphdr *)((struct iphdr *)*iph + 1); +- +- *hdr_flags = LRO_IPV4 | LRO_TCP; +- return 0; +-} +- +-static int t3_get_skb_header(struct sk_buff *skb, +- void **iph, void **tcph, u64 *hdr_flags, +- void *priv) +-{ +- void *eh; +- +- return t3_get_lro_header(&eh, iph, tcph, hdr_flags, priv); +-} +- +-static int t3_get_frag_header(struct skb_frag_struct *frag, void **eh, +- void **iph, void **tcph, u64 *hdr_flags, +- void *priv) +-{ +- return t3_get_lro_header(eh, iph, tcph, hdr_flags, priv); +-} ++ eh->h_proto == htons(ETH_P_IP) && ih->ihl == (sizeof(*ih) >> 2); ++} ++ ++#define TCP_FLAG_MASK (TCP_FLAG_CWR | TCP_FLAG_ECE | TCP_FLAG_URG |\ ++ TCP_FLAG_ACK | TCP_FLAG_PSH | TCP_FLAG_RST |\ ++ TCP_FLAG_SYN | TCP_FLAG_FIN) ++#define TSTAMP_WORD ((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |\ ++ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP) ++ ++/** ++ * lro_segment_ok - check if a TCP segment is eligible for LRO ++ * @tcph: the TCP header of the packet ++ * ++ * Returns true if a TCP packet is eligible for LRO. This requires that ++ * the packet have only the ACK flag set and no TCP options besides ++ * time stamps. ++ */ ++static inline int lro_segment_ok(const struct tcphdr *tcph) ++{ ++ int optlen; ++ ++ if (unlikely((tcp_flag_word(tcph) & TCP_FLAG_MASK) != TCP_FLAG_ACK)) ++ return 0; ++ ++ optlen = (tcph->doff << 2) - sizeof(*tcph); ++ if (optlen) { ++ const u32 *opt = (const u32 *)(tcph + 1); ++ ++ if (optlen != TCPOLEN_TSTAMP_ALIGNED || ++ *opt != htonl(TSTAMP_WORD) || !opt[2]) ++ return 0; ++ } ++ return 1; ++} ++ ++static int lro_update_session(struct lro_session *s, ++ const struct iphdr *iph, __be16 vlan, int plen) ++{ ++ struct sk_buff *skb; ++ const struct tcphdr *tcph; ++ struct tcphdr *s_tcph; ++ ++ if (unlikely(vlan != s->vlan)) ++ return -1; ++ ++ tcph = (const struct tcphdr *)(iph + 1); ++ if (unlikely(ntohl(tcph->seq) != s->seq || plen > 65535 - s->iplen)) ++ return -1; ++ ++ skb = s->head; ++ s_tcph = (struct tcphdr *)(ip_hdr(skb) + 1); ++ ++ if (tcph->doff != sizeof(*tcph) / 4) { /* TCP options present */ ++ const u32 *opt = (u32 *)(tcph + 1); ++ u32 *s_opt = (u32 *)(s_tcph + 1); ++ ++ if (unlikely(ntohl(s_opt[1]) > ntohl(opt[1]))) ++ return -1; ++ s_opt[1] = opt[1]; ++ s_opt[2] = opt[2]; ++ } ++ s_tcph->ack_seq = tcph->ack_seq; ++ s_tcph->window = tcph->window; ++ ++ s->seq += plen; ++ s->iplen += plen; ++ if (plen > s->mss) ++ s->mss = plen; ++ s->npkts++; ++ skb->len += plen; ++ skb->data_len += plen; ++ return 0; ++} ++ ++/* ++ * Length of a packet buffer examined by LRO, it extends up to and including TCP ++ * timestamps. This part of the packet must be made memory coherent for CPU ++ * accesses. ++ */ ++#define LRO_PEEK_LEN (IPH_OFFSET + sizeof(struct iphdr) + \ ++ sizeof(struct tcphdr) + 12) + + /** + * lro_add_page - add a page chunk to an LRO session + * @adap: the adapter + * @qs: the associated queue set + * @fl: the free list containing the page chunk to add +- * @len: packet length +- * @complete: Indicates the last fragment of a frame ++ * @flags: response queue flags for RX buffer ++ * @hash: hash value for the packet + * + * Add a received packet contained in a page chunk to an existing LRO +- * session. +- */ +-static void lro_add_page(struct adapter *adap, struct sge_qset *qs, +- struct sge_fl *fl, int len, int complete) +-{ ++ * session. There are four possible outcomes: ++ * - packet is not eligible for LRO; return -1 ++ * - packet is eligible but there's no appropriate session; return 1 ++ * - packet is added and the page chunk consumed; return 0 ++ * - packet is added but the page chunk isn't needed; return 0 ++ */ ++static int lro_add_page(struct adapter *adap, struct sge_qset *qs, ++ struct sge_fl *fl, u32 flags, u32 hash) ++{ ++ int tcpiplen, plen, ret; ++ struct lro_session *s; ++ const struct iphdr *iph; ++ const struct tcphdr *tcph; + struct rx_sw_desc *sd = &fl->sdesc[fl->cidx]; +- struct cpl_rx_pkt *cpl; +- struct skb_frag_struct *rx_frag = qs->lro_frag_tbl; +- int nr_frags = qs->lro_nfrags, frag_len = qs->lro_frag_len; +- int offset = 0; +- +- if (!nr_frags) { +- offset = 2 + sizeof(struct cpl_rx_pkt); +- qs->lro_va = cpl = sd->pg_chunk.va + 2; ++ const struct cpl_rx_pkt *cpl = sd->pg_chunk.va + 2; ++ ++ pci_dma_sync_single_for_cpu(adap->pdev, pci_unmap_addr(sd, dma_addr), ++ LRO_PEEK_LEN, PCI_DMA_FROMDEVICE); ++ ++ if ((flags & (F_RSPD_SOP|F_RSPD_EOP)) != (F_RSPD_SOP|F_RSPD_EOP) || ++ !lro_frame_ok(cpl)) { ++ret_1: ret = -1; ++sync: pci_dma_sync_single_for_device(adap->pdev, ++ pci_unmap_addr(sd, dma_addr), ++ LRO_PEEK_LEN, PCI_DMA_FROMDEVICE); ++ return ret; ++ } ++ ++ iph = (const struct iphdr *)(sd->pg_chunk.va + IPH_OFFSET); ++ s = lro_lookup(&qs->lro, hash & (MAX_LRO_SES - 1), iph); ++ if (!s) { ++ ret = 1; ++ goto sync; ++ } ++ ++ tcph = (const struct tcphdr *)(iph + 1); ++ tcpiplen = sizeof(*iph) + (tcph->doff << 2); ++ plen = ntohs(iph->tot_len) - tcpiplen; ++ ++ if (!lro_segment_ok(tcph) || ++ lro_update_session(s, iph, ++ cpl->vlan_valid ? cpl->vlan : htons(0xffff), ++ plen)) { ++ lro_flush_session(adap, qs, s); ++ goto ret_1; + } + + fl->credits--; +- +- len -= offset; +- pci_unmap_single(adap->pdev, pci_unmap_addr(sd, dma_addr), +- fl->buf_size, PCI_DMA_FROMDEVICE); +- +- rx_frag += nr_frags; +- rx_frag->page = sd->pg_chunk.page; +- rx_frag->page_offset = sd->pg_chunk.offset + offset; +- rx_frag->size = len; +- frag_len += len; +- qs->lro_nfrags++; +- qs->lro_frag_len = frag_len; +- +- if (!complete) +- return; +- +- qs->lro_nfrags = qs->lro_frag_len = 0; +- cpl = qs->lro_va; +- +- if (unlikely(cpl->vlan_valid)) { +- struct net_device *dev = qs->netdev; +- struct port_info *pi = netdev_priv(dev); +- struct vlan_group *grp = pi->vlan_grp; +- +- if (likely(grp != NULL)) { +- lro_vlan_hwaccel_receive_frags(&qs->lro_mgr, +- qs->lro_frag_tbl, +- frag_len, frag_len, +- grp, ntohs(cpl->vlan), +- cpl, 0); +- return; +- } +- } +- lro_receive_frags(&qs->lro_mgr, qs->lro_frag_tbl, +- frag_len, frag_len, cpl, 0); +-} +- +-/** +- * init_lro_mgr - initialize a LRO manager object +- * @lro_mgr: the LRO manager object +- */ +-static void init_lro_mgr(struct sge_qset *qs, struct net_lro_mgr *lro_mgr) +-{ +- lro_mgr->dev = qs->netdev; +- lro_mgr->features = LRO_F_NAPI; +- lro_mgr->frag_align_pad = NET_IP_ALIGN; +- lro_mgr->ip_summed = CHECKSUM_UNNECESSARY; +- lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY; +- lro_mgr->max_desc = T3_MAX_LRO_SES; +- lro_mgr->lro_arr = qs->lro_desc; +- lro_mgr->get_frag_header = t3_get_frag_header; +- lro_mgr->get_skb_header = t3_get_skb_header; +- lro_mgr->max_aggr = T3_MAX_LRO_MAX_PKTS; +- if (lro_mgr->max_aggr > MAX_SKB_FRAGS) +- lro_mgr->max_aggr = MAX_SKB_FRAGS; ++ if (plen) { ++ struct sk_buff *tskb = s->tail; ++ struct skb_shared_info *shinfo = skb_shinfo(tskb); ++ ++ pci_unmap_single(adap->pdev, pci_unmap_addr(sd, dma_addr), ++ fl->buf_size, PCI_DMA_FROMDEVICE); ++ skb_fill_page_desc(tskb, shinfo->nr_frags, sd->pg_chunk.page, ++ sd->pg_chunk.offset + IPH_OFFSET + tcpiplen, ++ plen); ++ s->head->truesize += plen; ++ if (s->head != tskb) { ++ /* ++ * lro_update_session updates the sizes of the head skb, ++ * do the same here for the component skb the fragment ++ * was actually added to. ++ */ ++ tskb->len += plen; ++ tskb->data_len += plen; ++ tskb->truesize += plen; ++ } ++ if (unlikely(shinfo->nr_frags == MAX_SKB_FRAGS)) ++ lro_flush_session(adap, qs, s); ++ /* No refill, caller does it. */ ++ qs->port_stats[SGE_PSTAT_LRO_PG]++; ++ } else { ++ pci_dma_sync_single_for_device(adap->pdev, ++ pci_unmap_addr(sd, dma_addr), ++ LRO_PEEK_LEN, PCI_DMA_FROMDEVICE); ++ recycle_rx_buf(adap, fl, fl->cidx); ++ qs->port_stats[SGE_PSTAT_LRO_ACK]++; ++ } ++ ++ return 0; ++} ++ ++/** ++ * lro_add_skb - add an sk_buff to an LRO session ++ * @adap: the adapter ++ * @qs: the associated queue set ++ * @skb: the sk_buff to add ++ * @hash: hash value for the packet ++ * ++ * Add a received packet contained in an sk_buff to an existing LRO ++ * session. Returns -1 if the packet is not eligible for LRO, and 0 ++ * if it is added successfully. ++ */ ++static int lro_add_skb(struct adapter *adap, struct sge_qset *qs, ++ struct sk_buff *skb, u32 hash) ++{ ++ __be16 vlan; ++ int tcpiplen, plen; ++ struct lro_session *s; ++ struct iphdr *iph; ++ const struct tcphdr *tcph; ++ const struct cpl_rx_pkt *cpl = (struct cpl_rx_pkt *)(skb->data + 2); ++ ++ if (!lro_frame_ok(cpl)) ++ return -1; ++ ++ iph = (struct iphdr *)(skb->data + IPH_OFFSET); ++ s = lro_lookup(&qs->lro, hash & (MAX_LRO_SES - 1), iph); ++ ++ tcph = (struct tcphdr *)(iph + 1); ++ if (!lro_segment_ok(tcph)) { ++ if (s) ++ lro_flush_session(adap, qs, s); ++ return -1; ++ } ++ ++ tcpiplen = sizeof(*iph) + (tcph->doff << 2); ++ plen = ntohs(iph->tot_len) - tcpiplen; ++ vlan = cpl->vlan_valid ? cpl->vlan : htons(0xffff); ++ if (likely(s && !lro_update_session(s, iph, vlan, plen))) { ++ /* ++ * Pure ACKs have nothing useful left and can be freed. ++ */ ++ if (plen) { ++ skb_pull(skb, IPH_OFFSET + tcpiplen); ++ s->head->truesize += skb->truesize; ++ ++ /* TP trims IP packets, no skb_trim needed */ ++ if (s->head == s->tail) ++ skb_shinfo(s->head)->frag_list = skb; ++ else ++ s->tail->next = skb; ++ s->tail = skb; ++ qs->port_stats[SGE_PSTAT_LRO_SKB]++; ++ } else { ++ __kfree_skb(skb); /* no destructors, ok from irq */ ++ qs->port_stats[SGE_PSTAT_LRO_ACK]++; ++ } ++ } else { ++ if (s) ++ lro_flush_session(adap, qs, s); ++ s = lro_alloc_session(adap, qs, hash); ++ lro_init_session(s, skb, iph, vlan, plen); ++ qs->port_stats[SGE_PSTAT_LRO_SKB]++; ++ } ++ return 0; + } + + /** +@@ -2129,8 +2830,38 @@ + #endif + + credits = G_RSPD_TXQ0_CR(flags); +- if (credits) ++ if (credits) { + qs->txq[TXQ_ETH].processed += credits; ++#ifdef CHELSIO_FREE_TXBUF_ASAP ++ /* ++ * In the normal Linux driver t3_eth_xmit() routine, we call ++ * skb_orphan() on unshared TX skb. This results in a call to ++ * the destructor for the skb which frees up the send buffer ++ * space it was holding down. This, in turn, allows the ++ * application to make forward progress generating more data ++ * which is important at 10Gb/s. For Virtual Machine Guest ++ * Operating Systems this doesn't work since the send buffer ++ * space is being held down in the Virtual Machine. Thus we ++ * need to get the TX skb's freed up as soon as possible in ++ * order to prevent applications from stalling. ++ * ++ * This code is largely copied from the corresponding code in ++ * sge_timer_tx() and should probably be kept in sync with any ++ * changes there. ++ */ ++ if (spin_trylock(&qs->txq[TXQ_ETH].lock)) { ++ struct sge_txq *q = &qs->txq[TXQ_ETH]; ++ struct port_info *pi = netdev_priv(qs->netdev); ++ struct adapter *adap = pi->adapter; ++ ++ if (q->eth_coalesce_idx) ++ ship_tx_pkt_coalesce_wr(adap, q); ++ ++ reclaim_completed_tx(adap, &qs->txq[TXQ_ETH], TX_RECLAIM_CHUNK); ++ spin_unlock(&qs->txq[TXQ_ETH].lock); ++ } ++#endif ++ } + + credits = G_RSPD_TXQ2_CR(flags); + if (credits) +@@ -2147,7 +2878,7 @@ + + /** + * check_ring_db - check if we need to ring any doorbells +- * @adapter: the adapter ++ * @adap: the adapter + * @qs: the queue set whose Tx queues are to be examined + * @sleeping: indicates which Tx queue sent GTS + * +@@ -2155,7 +2886,7 @@ + * to resume transmission after idling while they still have unprocessed + * descriptors. + */ +-static void check_ring_db(struct adapter *adap, struct sge_qset *qs, ++static void check_ring_db(adapter_t *adap, struct sge_qset *qs, + unsigned int sleeping) + { + if (sleeping & F_RSPD_TXQ0_GTS) { +@@ -2164,6 +2895,9 @@ + if (txq->cleaned + txq->in_use != txq->processed && + !test_and_set_bit(TXQ_LAST_PKT_DB, &txq->flags)) { + set_bit(TXQ_RUNNING, &txq->flags); ++#ifdef T3_TRACE ++ T3_TRACE0(adap->tb[txq->cntxt_id & 7], "doorbell ETH"); ++#endif + t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | + V_EGRCNTX(txq->cntxt_id)); + } +@@ -2175,6 +2909,10 @@ + if (txq->cleaned + txq->in_use != txq->processed && + !test_and_set_bit(TXQ_LAST_PKT_DB, &txq->flags)) { + set_bit(TXQ_RUNNING, &txq->flags); ++#ifdef T3_TRACE ++ T3_TRACE0(adap->tb[txq->cntxt_id & 7], ++ "doorbell offload"); ++#endif + t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | + V_EGRCNTX(txq->cntxt_id)); + } +@@ -2225,8 +2963,7 @@ + * on this queue. If the system is under memory shortage use a fairly + * long delay to help recovery. + */ +-static int process_responses(struct adapter *adap, struct sge_qset *qs, +- int budget) ++static int process_responses(adapter_t *adap, struct sge_qset *qs, int budget) + { + struct sge_rspq *q = &qs->rspq; + struct rsp_desc *r = &q->desc[q->cidx]; +@@ -2238,11 +2975,17 @@ + q->next_holdoff = q->holdoff_tmr; + + while (likely(budget_left && is_new_response(r, q))) { +- int packet_complete, eth, ethpad = 2, lro = qs->lro_enabled; ++ int packet_complete, eth, ethpad = 2, lro = qs->lro.enabled; ++ u32 len, flags = ntohl(r->flags); ++ u32 rss_hi = *(const u32 *)r, rss_lo = r->rss_hdr.rss_hash_val; + struct sk_buff *skb = NULL; +- u32 len, flags = ntohl(r->flags); +- __be32 rss_hi = *(const __be32 *)r, +- rss_lo = r->rss_hdr.rss_hash_val; ++ ++#ifdef T3_TRACE ++ T3_TRACE5(adap->tb[q->cntxt_id], ++ "response: RSS 0x%x flags 0x%x len %u, type 0x%x rss hash 0x%x", ++ ntohl(rss_hi), flags, ntohl(r->len_cq), ++ r->rss_hdr.hash_type, ntohl(rss_lo)); ++#endif + + eth = r->rss_hdr.opcode == CPL_RX_PKT; + +@@ -2270,7 +3013,8 @@ + } else if ((len = ntohl(r->len_cq)) != 0) { + struct sge_fl *fl; + +- lro &= eth && is_eth_tcp(rss_hi); ++ if (eth) ++ lro = qs->lro.enabled && is_eth_tcp(rss_hi); + + fl = (len & F_RSPD_FLQ) ? &qs->fl[1] : &qs->fl[0]; + if (fl->use_pages) { +@@ -2281,18 +3025,16 @@ + prefetch(addr + L1_CACHE_BYTES); + #endif + __refill_fl(adap, fl); ++ + if (lro > 0) { +- lro_add_page(adap, qs, fl, +- G_RSPD_LEN(len), +- flags & F_RSPD_EOP); +- goto next_fl; ++ lro = lro_add_page(adap, qs, fl, ++ flags, rss_lo); ++ if (!lro) ++ goto next_fl; + } + +- skb = get_packet_pg(adap, fl, q, +- G_RSPD_LEN(len), +- eth ? +- SGE_RX_DROP_THRES : 0); +- q->pg_skb = skb; ++ skb = q->pg_skb = get_packet_pg(adap, fl, q, G_RSPD_LEN(len), ++ eth ? SGE_RX_DROP_THRES : 0); + } else + skb = get_packet(adap, fl, G_RSPD_LEN(len), + eth ? SGE_RX_DROP_THRES : 0); +@@ -2326,14 +3068,15 @@ + q->credits = 0; + } + +- packet_complete = flags & +- (F_RSPD_EOP | F_RSPD_IMM_DATA_VALID | +- F_RSPD_ASYNC_NOTIF); +- +- if (skb != NULL && packet_complete) { +- if (eth) +- rx_eth(adap, q, skb, ethpad, lro); +- else { ++ packet_complete = flags & ++ (F_RSPD_EOP | F_RSPD_IMM_DATA_VALID | F_RSPD_ASYNC_NOTIF); ++ ++ if ((skb != NULL) && packet_complete) { ++ if (eth) { ++ if (lro <= 0 || ++ lro_add_skb(adap, qs, skb, rss_lo)) ++ rx_eth(adap, q, skb, ethpad, 1); ++ } else { + q->offload_pkts++; + /* Preserve the RSS info in csum & priority */ + skb->csum = rss_hi; +@@ -2342,27 +3085,34 @@ + offload_skbs, + ngathered); + } +- ++ + if (flags & F_RSPD_EOP) + clear_rspq_bufstate(q); + } ++ + --budget_left; + } + + deliver_partial_bundle(&adap->tdev, q, offload_skbs, ngathered); +- lro_flush_all(&qs->lro_mgr); +- qs->port_stats[SGE_PSTAT_LRO_AGGR] = qs->lro_mgr.stats.aggregated; +- qs->port_stats[SGE_PSTAT_LRO_FLUSHED] = qs->lro_mgr.stats.flushed; +- qs->port_stats[SGE_PSTAT_LRO_NO_DESC] = qs->lro_mgr.stats.no_desc; ++ lro_flush(adap, qs, &qs->lro); + + if (sleeping) + check_ring_db(adap, qs, sleeping); + +- smp_mb(); /* commit Tx queue .processed updates */ ++ smp_mb(); /* commit Tx queue .processed updates */ + if (unlikely(qs->txq_stopped != 0)) + restart_tx(qs); + ++ if (qs->txq[TXQ_ETH].eth_coalesce_idx && ++ should_finalize_tx_pkt_coalescing(&qs->txq[TXQ_ETH])) ++ try_finalize_tx_pkt_coalesce_wr(adap, &qs->txq[TXQ_ETH]); ++ + budget -= budget_left; ++#ifdef T3_TRACE ++ T3_TRACE4(adap->tb[q->cntxt_id], ++ "process_responses: <- cidx %u gen %u ret %u credit %u", ++ q->cidx, q->gen, budget, q->credits); ++#endif + return budget; + } + +@@ -2375,47 +3125,73 @@ + + /** + * napi_rx_handler - the NAPI handler for Rx processing +- * @napi: the napi instance ++ * @dev: the net device + * @budget: how many packets we can process in this round + * +- * Handler for new data events when using NAPI. +- */ +-static int napi_rx_handler(struct napi_struct *napi, int budget) +-{ +- struct sge_qset *qs = container_of(napi, struct sge_qset, napi); ++ * Handler for new data events when using NAPI. This does not need any ++ * locking or protection from interrupts as data interrupts are off at ++ * this point and other adapter interrupts do not interfere (the latter ++ * in not a concern at all with MSI-X as non-data interrupts then have ++ * a separate handler). ++ */ ++DECLARE_NAPI_RX_HANDLER(napi, dev, budget) ++{ ++ struct sge_qset *qs = SGE_GET_OFLD_QS(napi, dev); + struct adapter *adap = qs->adap; +- int work_done = process_responses(adap, qs, budget); +- +- if (likely(work_done < budget)) { ++#if defined(NAPI_UPDATE) ++ int effective_budget = budget; ++#else ++ int effective_budget = min(*budget, dev->quota); ++#endif ++ int work_done = process_responses(adap, qs, effective_budget); ++ ++#if !defined(NAPI_UPDATE) ++ *budget -= work_done; ++ dev->quota -= work_done; ++#endif ++ if (likely(work_done < effective_budget)) { ++ ++#if defined(NAPI_UPDATE) + napi_complete(napi); +- +- /* +- * Because we don't atomically flush the following +- * write it is possible that in very rare cases it can +- * reach the device in a way that races with a new +- * response being written plus an error interrupt +- * causing the NAPI interrupt handler below to return +- * unhandled status to the OS. To protect against +- * this would require flushing the write and doing +- * both the write and the flush with interrupts off. +- * Way too expensive and unjustifiable given the +- * rarity of the race. ++#else ++ netif_rx_complete(dev); ++#endif ++ /* ++ * Because we don't atomically flush the following write it is ++ * possible that in very rare cases it can reach the device ++ * in a way that races with a new response being written ++ * plus an error interrupt causing the NAPI interrupt handler ++ * below to return unhandled status to the OS. ++ * To protect against this would require flushing the write ++ * and doing both the write and the flush with interrupts off. ++ * Way too expensive and unjustifiable given the rarity ++ * of the race. + * + * The race cannot happen at all with MSI-X. + */ + t3_write_reg(adap, A_SG_GTS, V_RSPQ(qs->rspq.cntxt_id) | +- V_NEWTIMER(qs->rspq.next_holdoff) | +- V_NEWINDEX(qs->rspq.cidx)); +- } ++ V_NEWTIMER(qs->rspq.next_holdoff) | ++ V_NEWINDEX(qs->rspq.cidx)); ++ } ++#if defined(NAPI_UPDATE) + return work_done; ++#else ++ return (work_done >= effective_budget); ++#endif + } + + /* + * Returns true if the device is already scheduled for polling. + */ +-static inline int napi_is_scheduled(struct napi_struct *napi) +-{ ++static inline int napi_is_scheduled(struct sge_qset *qs) ++{ ++#if defined(NAPI_UPDATE) ++ struct napi_struct *napi = &qs->napi; + return test_bit(NAPI_STATE_SCHED, &napi->state); ++#else ++ struct net_device *dev = qs->netdev; ++ return test_bit(__LINK_STATE_RX_SCHED, &dev->state); ++#endif + } + + /** +@@ -2432,7 +3208,7 @@ + * + * Returns 1 if it encounters a valid data-carrying response, 0 otherwise. + */ +-static int process_pure_responses(struct adapter *adap, struct sge_qset *qs, ++static int process_pure_responses(adapter_t *adap, struct sge_qset *qs, + struct rsp_desc *r) + { + struct sge_rspq *q = &qs->rspq; +@@ -2441,6 +3217,11 @@ + do { + u32 flags = ntohl(r->flags); + ++#ifdef T3_TRACE ++ T3_TRACE2(adap->tb[q->cntxt_id], ++ "pure response: RSS 0x%x flags 0x%x", ++ ntohl(*(u32 *)r), flags); ++#endif + r++; + if (unlikely(++q->cidx == q->size)) { + q->cidx = 0; +@@ -2464,9 +3245,13 @@ + if (sleeping) + check_ring_db(adap, qs, sleeping); + +- smp_mb(); /* commit Tx queue .processed updates */ ++ smp_mb(); /* commit Tx queue .processed updates */ + if (unlikely(qs->txq_stopped != 0)) + restart_tx(qs); ++ ++ if (qs->txq[TXQ_ETH].eth_coalesce_idx && ++ should_finalize_tx_pkt_coalescing(&qs->txq[TXQ_ETH])) ++ try_finalize_tx_pkt_coalesce_wr(adap, &qs->txq[TXQ_ETH]); + + return is_new_response(r, q); + } +@@ -2495,10 +3280,16 @@ + return -1; + if (is_pure_response(r) && process_pure_responses(adap, qs, r) == 0) { + t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) | +- V_NEWTIMER(q->holdoff_tmr) | V_NEWINDEX(q->cidx)); ++ V_NEWTIMER(q->holdoff_tmr) | ++ V_NEWINDEX(q->cidx)); + return 0; + } ++#if defined(NAPI_UPDATE) + napi_schedule(&qs->napi); ++#else ++ if (likely(__netif_rx_schedule_prep(qs->netdev))) ++ __netif_rx_schedule(qs->netdev); ++#endif + return 1; + } + +@@ -2506,16 +3297,15 @@ + * The MSI-X interrupt handler for an SGE response queue for the non-NAPI case + * (i.e., response queue serviced in hard interrupt). + */ +-irqreturn_t t3_sge_intr_msix(int irq, void *cookie) ++DECLARE_INTR_HANDLER(t3_sge_intr_msix, irq, cookie, regs) + { + struct sge_qset *qs = cookie; +- struct adapter *adap = qs->adap; +- struct sge_rspq *q = &qs->rspq; +- +- spin_lock(&q->lock); +- if (process_responses(adap, qs, -1) == 0) ++ struct sge_rspq *q = &qs->rspq; ++ ++ spin_lock(&q->lock); ++ if (process_responses(qs->adap, qs, -1) == 0) + q->unhandled_irqs++; +- t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) | ++ t3_write_reg(qs->adap, A_SG_GTS, V_RSPQ(q->cntxt_id) | + V_NEWTIMER(q->next_holdoff) | V_NEWINDEX(q->cidx)); + spin_unlock(&q->lock); + return IRQ_HANDLED; +@@ -2525,13 +3315,12 @@ + * The MSI-X interrupt handler for an SGE response queue for the NAPI case + * (i.e., response queue serviced by NAPI polling). + */ +-static irqreturn_t t3_sge_intr_msix_napi(int irq, void *cookie) ++DECLARE_INTR_HANDLER(t3_sge_intr_msix_napi, irq, cookie, regs) + { + struct sge_qset *qs = cookie; + struct sge_rspq *q = &qs->rspq; + + spin_lock(&q->lock); +- + if (handle_responses(qs->adap, q) < 0) + q->unhandled_irqs++; + spin_unlock(&q->lock); +@@ -2544,79 +3333,70 @@ + * the same MSI vector. We use one SGE response queue per port in this mode + * and protect all response queues with queue 0's lock. + */ +-static irqreturn_t t3_intr_msi(int irq, void *cookie) +-{ +- int new_packets = 0; +- struct adapter *adap = cookie; ++DECLARE_INTR_HANDLER(t3_intr_msi, irq, cookie, regs) ++{ ++ int i, qset = 0; ++ adapter_t *adap = cookie; + struct sge_rspq *q = &adap->sge.qs[0].rspq; + +- spin_lock(&q->lock); +- +- if (process_responses(adap, &adap->sge.qs[0], -1)) { +- t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) | +- V_NEWTIMER(q->next_holdoff) | V_NEWINDEX(q->cidx)); +- new_packets = 1; +- } +- +- if (adap->params.nports == 2 && +- process_responses(adap, &adap->sge.qs[1], -1)) { +- struct sge_rspq *q1 = &adap->sge.qs[1].rspq; +- +- t3_write_reg(adap, A_SG_GTS, V_RSPQ(q1->cntxt_id) | +- V_NEWTIMER(q1->next_holdoff) | +- V_NEWINDEX(q1->cidx)); +- new_packets = 1; +- } +- +- if (!new_packets && t3_slow_intr_handler(adap) == 0) +- q->unhandled_irqs++; +- +- spin_unlock(&q->lock); ++ for_each_port(adap, i) { ++ int j; ++ struct port_info *p = adap2pinfo(adap, i); ++ ++ for (j = p->first_qset; j < p->first_qset + p->nqsets; j++, qset++) { ++ ++ struct sge_rspq *q1 = &adap->sge.qs[qset].rspq; ++ ++ spin_lock(&q1->lock); ++ (void)handle_responses(adap, q1); ++ spin_unlock(&q1->lock); ++ } ++ } ++ ++ spin_lock(&q->lock); ++ (void)t3_slow_intr_handler(adap); ++ spin_unlock(&q->lock); ++ + return IRQ_HANDLED; +-} +- +-static int rspq_check_napi(struct sge_qset *qs) +-{ +- struct sge_rspq *q = &qs->rspq; +- +- if (!napi_is_scheduled(&qs->napi) && +- is_new_response(&q->desc[q->cidx], q)) { +- napi_schedule(&qs->napi); +- return 1; +- } +- return 0; + } + + /* + * The MSI interrupt handler for the NAPI case (i.e., response queues serviced + * by NAPI polling). Handles data events from SGE response queues as well as + * error and other async events as they all use the same MSI vector. We use +- * one SGE response queue per port in this mode and protect all response +- * queues with queue 0's lock. +- */ +-static irqreturn_t t3_intr_msi_napi(int irq, void *cookie) +-{ +- int new_packets; +- struct adapter *adap = cookie; ++ * queue 0's lock for handling non-data events. ++ */ ++DECLARE_INTR_HANDLER(t3_intr_msi_napi, irq, cookie, regs) ++{ ++ int i, qset = 0; ++ adapter_t *adap = cookie; + struct sge_rspq *q = &adap->sge.qs[0].rspq; + +- spin_lock(&q->lock); +- +- new_packets = rspq_check_napi(&adap->sge.qs[0]); +- if (adap->params.nports == 2) +- new_packets += rspq_check_napi(&adap->sge.qs[1]); +- if (!new_packets && t3_slow_intr_handler(adap) == 0) +- q->unhandled_irqs++; +- +- spin_unlock(&q->lock); ++ for_each_port(adap, i) { ++ int j; ++ struct port_info *p = adap2pinfo(adap, i); ++ ++ for (j = p->first_qset; j < p->first_qset + p->nqsets; j++, qset++) { ++ struct sge_rspq *q1 = &adap->sge.qs[qset].rspq; ++ ++ spin_lock(&q1->lock); ++ if (!napi_is_scheduled(&adap->sge.qs[qset])) ++ (void)handle_responses(adap, q1); ++ spin_unlock(&q1->lock); ++ } ++ } ++ ++ spin_lock(&q->lock); ++ (void)t3_slow_intr_handler(adap); ++ spin_unlock(&q->lock); ++ + return IRQ_HANDLED; + } + + /* + * A helper function that processes responses and issues GTS. + */ +-static inline int process_responses_gts(struct adapter *adap, +- struct sge_rspq *rq) ++static inline int process_responses_gts(adapter_t *adap, struct sge_rspq *rq) + { + int work; + +@@ -2632,10 +3412,10 @@ + * the same interrupt pin. We use one SGE response queue per port in this mode + * and protect all response queues with queue 0's lock. + */ +-static irqreturn_t t3_intr(int irq, void *cookie) ++DECLARE_INTR_HANDLER(t3_intr, irq, cookie, regs) + { + int work_done, w0, w1; +- struct adapter *adap = cookie; ++ adapter_t *adap = cookie; + struct sge_rspq *q0 = &adap->sge.qs[0].rspq; + struct sge_rspq *q1 = &adap->sge.qs[1].rspq; + +@@ -2643,11 +3423,11 @@ + + w0 = is_new_response(&q0->desc[q0->cidx], q0); + w1 = adap->params.nports == 2 && +- is_new_response(&q1->desc[q1->cidx], q1); ++ is_new_response(&q1->desc[q1->cidx], q1); + + if (likely(w0 | w1)) { + t3_write_reg(adap, A_PL_CLI, 0); +- t3_read_reg(adap, A_PL_CLI); /* flush */ ++ (void) t3_read_reg(adap, A_PL_CLI); /* flush */ + + if (likely(w0)) + process_responses_gts(adap, q0); +@@ -2666,70 +3446,87 @@ + /* + * Interrupt handler for legacy INTx interrupts for T3B-based cards. + * Handles data events from SGE response queues as well as error and other +- * async events as they all use the same interrupt pin. We use one SGE +- * response queue per port in this mode and protect all response queues with +- * queue 0's lock. +- */ +-static irqreturn_t t3b_intr(int irq, void *cookie) +-{ +- u32 map; +- struct adapter *adap = cookie; ++ * async events as they all use the same interrupt pin. ++ */ ++DECLARE_INTR_HANDLER(t3b_intr, irq, cookie, regs) ++{ ++ u32 i, map; ++ adapter_t *adap = cookie; + struct sge_rspq *q0 = &adap->sge.qs[0].rspq; ++ int qset = 0; + + t3_write_reg(adap, A_PL_CLI, 0); + map = t3_read_reg(adap, A_SG_DATA_INTR); + +- if (unlikely(!map)) /* shared interrupt, most likely */ ++ if (unlikely(!map)) /* shared interrupt, most likely */ + return IRQ_NONE; + +- spin_lock(&q0->lock); +- +- if (unlikely(map & F_ERRINTR)) +- t3_slow_intr_handler(adap); +- +- if (likely(map & 1)) +- process_responses_gts(adap, q0); +- +- if (map & 2) +- process_responses_gts(adap, &adap->sge.qs[1].rspq); +- +- spin_unlock(&q0->lock); +- return IRQ_HANDLED; ++ if (unlikely(map & F_ERRINTR)) { ++ spin_lock(&q0->lock); ++ (void)t3_slow_intr_handler(adap); ++ spin_unlock(&q0->lock); ++ } ++ ++ for_each_port(adap, i) { ++ struct port_info *p = adap2pinfo(adap, i); ++ int j; ++ ++ for (j = p->first_qset; j < p->first_qset + p->nqsets; j++, qset++) { ++ if (map & (1 << qset)) { ++ spin_lock(&adap->sge.qs[qset].rspq.lock); ++ process_responses_gts(adap, &adap->sge.qs[qset].rspq); ++ spin_unlock(&adap->sge.qs[qset].rspq.lock); ++ } ++ } ++ } ++ return IRQ_HANDLED; + } + + /* + * NAPI interrupt handler for legacy INTx interrupts for T3B-based cards. + * Handles data events from SGE response queues as well as error and other +- * async events as they all use the same interrupt pin. We use one SGE +- * response queue per port in this mode and protect all response queues with +- * queue 0's lock. +- */ +-static irqreturn_t t3b_intr_napi(int irq, void *cookie) +-{ +- u32 map; +- struct adapter *adap = cookie; +- struct sge_qset *qs0 = &adap->sge.qs[0]; +- struct sge_rspq *q0 = &qs0->rspq; ++ * async events as they all use the same interrupt pin. ++ */ ++DECLARE_INTR_HANDLER(t3b_intr_napi, irq, cookie, regs) ++{ ++ u32 i, map; ++ adapter_t *adap = cookie; ++ struct sge_rspq *q0 = &adap->sge.qs[0].rspq; ++ int qset = 0; + + t3_write_reg(adap, A_PL_CLI, 0); + map = t3_read_reg(adap, A_SG_DATA_INTR); + +- if (unlikely(!map)) /* shared interrupt, most likely */ ++ if (unlikely(!map)) /* shared interrupt, most likely */ + return IRQ_NONE; + +- spin_lock(&q0->lock); +- +- if (unlikely(map & F_ERRINTR)) +- t3_slow_intr_handler(adap); +- +- if (likely(map & 1)) +- napi_schedule(&qs0->napi); +- +- if (map & 2) +- napi_schedule(&adap->sge.qs[1].napi); +- +- spin_unlock(&q0->lock); +- return IRQ_HANDLED; ++ if (unlikely(map & F_ERRINTR)) { ++ spin_lock(&q0->lock); ++ (void)t3_slow_intr_handler(adap); ++ spin_unlock(&q0->lock); ++ } ++ ++ for_each_port(adap, i) { ++ struct port_info *p = adap2pinfo(adap, i); ++ int j; ++ ++ for (j = p->first_qset; j < p->first_qset + p->nqsets; j++, qset++) { ++ if (map & (1 << qset)) { ++ struct net_device *dev = adap->sge.qs[qset].netdev; ++ ++ spin_lock(&adap->sge.qs[qset].rspq.lock); ++#if defined(NAPI_UPDATE) ++ napi_schedule(&adap->sge.qs[qset].napi); ++#else ++ ++ if (likely(__netif_rx_schedule_prep(dev))) ++ __netif_rx_schedule(dev); ++#endif ++ spin_unlock(&adap->sge.qs[qset].rspq.lock); ++ } ++ } ++ } ++ return IRQ_HANDLED; + } + + /** +@@ -2741,7 +3538,7 @@ + * (MSI-X, MSI, or legacy) and whether NAPI will be used to service the + * response queues. + */ +-irq_handler_t t3_intr_handler(struct adapter *adap, int polling) ++intr_handler_t t3_intr_handler(adapter_t *adap, int polling) + { + if (adap->flags & USING_MSIX) + return polling ? t3_sge_intr_msix_napi : t3_sge_intr_msix; +@@ -2767,9 +3564,10 @@ + * + * Interrupt handler for SGE asynchronous (non-data) events. + */ +-void t3_sge_err_intr_handler(struct adapter *adapter) +-{ +- unsigned int v, status = t3_read_reg(adapter, A_SG_INT_CAUSE); ++void t3_sge_err_intr_handler(adapter_t *adapter) ++{ ++ unsigned int v, status = (t3_read_reg(adapter, A_SG_INT_CAUSE) ++ & ~(F_FLEMPTY)); + + if (status & SGE_PARERR) + CH_ALERT(adapter, "SGE parity error (0x%x)\n", +@@ -2777,7 +3575,6 @@ + if (status & SGE_FRAMINGERR) + CH_ALERT(adapter, "SGE framing error (0x%x)\n", + status & SGE_FRAMINGERR); +- + if (status & F_RSPQCREDITOVERFOW) + CH_ALERT(adapter, "SGE response queue credit overflow\n"); + +@@ -2785,8 +3582,8 @@ + v = t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS); + + CH_ALERT(adapter, +- "packet delivered to disabled response queue " +- "(0x%x)\n", (v >> S_RSPQ0DISABLED) & 0xff); ++ "packet delivered to disabled response queue (0x%x)\n", ++ (v >> S_RSPQ0DISABLED) & 0xff); + } + + if (status & (F_HIPIODRBDROPERR | F_LOPIODRBDROPERR)) +@@ -2794,12 +3591,43 @@ + status & F_HIPIODRBDROPERR ? "high" : "lo"); + + t3_write_reg(adapter, A_SG_INT_CAUSE, status); +- if (status & SGE_FATALERR) ++ if (status & SGE_FATALERR) + t3_fatal_err(adapter); + } + +-/** +- * sge_timer_cb - perform periodic maintenance of an SGE qset ++/* Update offload traffic scheduler for a particular port */ ++static void update_max_bw(struct sge_qset *qs, struct port_info *pi) ++{ ++ struct sge_txq *q = &qs->txq[TXQ_ETH]; ++ int max_bw, update_bw; ++ ++ if (!netif_carrier_ok(qs->netdev)) ++ return; ++ ++ if ((q->cntxt_id - FW_TUNNEL_SGEEC_START) != pi->first_qset) ++ return; ++ ++ max_bw = pi->link_config.speed * 940; ++ ++ /* use q->in_use as an indicator of ongoing NIC traffic */ ++ update_bw = ((q->in_use && pi->max_ofld_bw == max_bw) || ++ (!q->in_use && pi->max_ofld_bw < max_bw)); ++ ++ if (update_bw) { ++ pi->max_ofld_bw = q->in_use ? ++ pi->link_config.speed * 470 : ++ pi->link_config.speed * 940; ++ t3_config_sched(pi->adapter, pi->max_ofld_bw, pi->port_id); ++#ifdef T3_TRACE ++ T3_TRACE3(pi->adapter->tb[q->cntxt_id & 7], ++ "%s: updating max bw to %d for port %d", ++ __func__, pi->max_ofld_bw, pi->port_id); ++#endif ++ } ++} ++ ++/** ++ * sge_timer_tx - perform periodic maintenance of an SGE qset + * @data: the SGE queue set to maintain + * + * Runs periodically from a timer to perform maintenance of an SGE queue +@@ -2815,51 +3643,105 @@ + * up). Since control queues use immediate data exclusively we don't + * bother cleaning them up here. + * +- * b) Replenishes Rx queues that have run out due to memory shortage. +- * Normally new Rx buffers are added when existing ones are consumed but +- * when out of memory a queue can become empty. We try to add only a few +- * buffers here, the queue will be replenished fully as these new buffers +- * are used up if memory shortage has subsided. +- */ +-static void sge_timer_cb(unsigned long data) +-{ +- spinlock_t *lock; ++ * b) Ring doorbells for T304 tunnel queues since we have seen doorbell ++ * fifo overflows and the FW doesn't implement any recovery scheme yet. ++ */ ++static void sge_timer_tx(unsigned long data) ++{ + struct sge_qset *qs = (struct sge_qset *)data; +- struct adapter *adap = qs->adap; ++ struct port_info *pi = netdev_priv(qs->netdev); ++ struct adapter *adap = pi->adapter; ++ unsigned int tbd[SGE_TXQ_PER_SET] = {0, 0}; ++ unsigned long next_period; + + if (spin_trylock(&qs->txq[TXQ_ETH].lock)) { +- reclaim_completed_tx(adap, &qs->txq[TXQ_ETH]); ++ struct sge_txq *q = &qs->txq[TXQ_ETH]; ++ ++ if (q->eth_coalesce_idx) ++ ship_tx_pkt_coalesce_wr(adap, q); ++ ++ tbd[TXQ_ETH] = reclaim_completed_tx(adap, &qs->txq[TXQ_ETH], TX_RECLAIM_TIMER_CHUNK); + spin_unlock(&qs->txq[TXQ_ETH].lock); + } + if (spin_trylock(&qs->txq[TXQ_OFLD].lock)) { +- reclaim_completed_tx(adap, &qs->txq[TXQ_OFLD]); ++ tbd[TXQ_OFLD] = reclaim_completed_tx(adap, &qs->txq[TXQ_OFLD], TX_RECLAIM_TIMER_CHUNK); + spin_unlock(&qs->txq[TXQ_OFLD].lock); + } +- lock = (adap->flags & USING_MSIX) ? &qs->rspq.lock : +- &adap->sge.qs[0].rspq.lock; +- if (spin_trylock_irq(lock)) { +- if (!napi_is_scheduled(&qs->napi)) { +- u32 status = t3_read_reg(adap, A_SG_RSPQ_FL_STATUS); +- +- if (qs->fl[0].credits < qs->fl[0].size) +- __refill_fl(adap, &qs->fl[0]); +- if (qs->fl[1].credits < qs->fl[1].size) +- __refill_fl(adap, &qs->fl[1]); +- +- if (status & (1 << qs->rspq.cntxt_id)) { +- qs->rspq.starved++; +- if (qs->rspq.credits) { +- refill_rspq(adap, &qs->rspq, 1); +- qs->rspq.credits--; +- qs->rspq.restarted++; +- t3_write_reg(adap, A_SG_RSPQ_FL_STATUS, +- 1 << qs->rspq.cntxt_id); +- } +- } +- } +- spin_unlock_irq(lock); +- } +- mod_timer(&qs->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); ++ ++ if (adap->params.nports > 2) ++ update_max_bw(qs, pi); ++ ++ if (adap->params.nports > 2) { ++ int i; ++ ++ for_each_port(adap, i) { ++ struct net_device *dev = adap->port[i]; ++ const struct port_info *pi = netdev_priv(dev); ++ ++ t3_write_reg(adap, A_SG_KDOORBELL, ++ F_SELEGRCNTX | ++ (FW_TUNNEL_SGEEC_START + pi->first_qset)); ++ } ++ } ++ next_period = TX_RECLAIM_PERIOD >> (max(tbd[TXQ_ETH], tbd[TXQ_OFLD]) / TX_RECLAIM_TIMER_CHUNK); ++ mod_timer(&qs->tx_reclaim_timer, jiffies + next_period); ++} ++ ++/* ++ * sge_timer_rx - perform periodic maintenance of an SGE qset ++ * @data: the SGE queue set to maintain ++ * ++ * a) Replenishes Rx queues that have run out due to memory shortage. ++ * Normally new Rx buffers are added when existing ones are consumed but ++ * when out of memory a queue can become empty. We try to add only a few ++ * buffers here, the queue will be replenished fully as these new buffers ++ * are used up if memory shortage has subsided. ++ * ++ * b) Return coalesced response queue credits in case a response queue is ++ * starved. ++ * ++ */ ++static void sge_timer_rx(unsigned long data) ++{ ++ spinlock_t *lock; ++ struct sge_qset *qs = (struct sge_qset *)data; ++ struct port_info *pi = netdev_priv(qs->netdev); ++ struct adapter *adap = pi->adapter; ++ u32 status; ++ ++ lock = adap->params.rev > 0 ? ++ &qs->rspq.lock : &adap->sge.qs[0].rspq.lock; ++ ++ if (!spin_trylock_irq(lock)) ++ goto out; ++ ++ if (napi_is_scheduled(qs)) ++ goto unlock; ++ ++ if (adap->params.rev < 4) { ++ status = t3_read_reg(adap, A_SG_RSPQ_FL_STATUS); ++ ++ if (status & (1 << qs->rspq.cntxt_id)) { ++ qs->rspq.starved++; ++ if (qs->rspq.credits) { ++ qs->rspq.credits--; ++ refill_rspq(adap, &qs->rspq, 1); ++ qs->rspq.restarted++; ++ t3_write_reg(adap, A_SG_RSPQ_FL_STATUS, ++ 1 << qs->rspq.cntxt_id); ++ } ++ } ++ } ++ ++ if (qs->fl[0].credits < qs->fl[0].size) ++ __refill_fl(adap, &qs->fl[0]); ++ if (qs->fl[1].credits < qs->fl[1].size) ++ __refill_fl(adap, &qs->fl[1]); ++ ++unlock: ++ spin_unlock_irq(lock); ++out: ++ mod_timer(&qs->rx_reclaim_timer, jiffies + RX_RECLAIM_PERIOD); + } + + /** +@@ -2872,9 +3754,17 @@ + */ + void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p) + { +- qs->rspq.holdoff_tmr = max(p->coalesce_usecs * 10, 1U);/* can't be 0 */ ++ if (!qs->netdev) ++ return; ++ ++ qs->rspq.holdoff_tmr = max(p->coalesce_usecs * 10, 1U); // can't be 0 + qs->rspq.polling = p->polling; +- qs->napi.poll = p->polling ? napi_rx_handler : ofld_poll; ++#if defined(NAPI_UPDATE) ++ qs->napi.poll = ++#else ++ qs->netdev->poll = ++#endif ++ p->polling ? napi_rx_handler : ofld_poll; + } + + /** +@@ -2892,35 +3782,41 @@ + * Tx queues. The Tx queues are assigned roles in the order Ethernet + * queue, offload queue, and control queue. + */ +-int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports, +- int irq_vec_idx, const struct qset_params *p, +- int ntxq, struct net_device *dev) +-{ +- int i, avail, ret = -ENOMEM; ++int t3_sge_alloc_qset(adapter_t *adapter, unsigned int id, int nports, ++ int irq_vec_idx, const struct qset_params *p, ++ int ntxq, struct net_device *netdev) ++{ ++#if !defined(NAPI_UPDATE) ++ struct port_info *pi = netdev_priv(netdev); ++#endif ++ int i, ret = -ENOMEM; + struct sge_qset *q = &adapter->sge.qs[id]; +- struct net_lro_mgr *lro_mgr = &q->lro_mgr; + + init_qset_cntxt(q, id); +- setup_timer(&q->tx_reclaim_timer, sge_timer_cb, (unsigned long)q); ++ init_timer(&q->tx_reclaim_timer); ++ init_timer(&q->rx_reclaim_timer); ++ q->tx_reclaim_timer.data = q->rx_reclaim_timer.data = (unsigned long)q; ++ q->tx_reclaim_timer.function = sge_timer_tx; ++ q->rx_reclaim_timer.function = sge_timer_rx; + + q->fl[0].desc = alloc_ring(adapter->pdev, p->fl_size, + sizeof(struct rx_desc), + sizeof(struct rx_sw_desc), + &q->fl[0].phys_addr, &q->fl[0].sdesc); +- if (!q->fl[0].desc) ++ if (!q->fl[0].desc && p->fl_size) + goto err; + + q->fl[1].desc = alloc_ring(adapter->pdev, p->jumbo_size, + sizeof(struct rx_desc), + sizeof(struct rx_sw_desc), + &q->fl[1].phys_addr, &q->fl[1].sdesc); +- if (!q->fl[1].desc) ++ if (!q->fl[1].desc && p->jumbo_size) + goto err; + + q->rspq.desc = alloc_ring(adapter->pdev, p->rspq_size, + sizeof(struct rsp_desc), 0, + &q->rspq.phys_addr, NULL); +- if (!q->rspq.desc) ++ if (!q->rspq.desc && p->rspq_size) + goto err; + + for (i = 0; i < ntxq; ++i) { +@@ -2943,6 +3839,11 @@ + skb_queue_head_init(&q->txq[i].sendq); + } + ++ q->txq[TXQ_ETH].eth_coalesce_sdesc = kcalloc(p->txq_size[TXQ_ETH], ++ sizeof(struct eth_coalesce_sw_desc), GFP_KERNEL); ++ if (!q->txq[TXQ_ETH].eth_coalesce_sdesc) ++ goto err; ++ + tasklet_init(&q->txq[TXQ_OFLD].qresume_tsk, restart_offloadq, + (unsigned long)q); + tasklet_init(&q->txq[TXQ_CTRL].qresume_tsk, restart_ctrlq, +@@ -2957,7 +3858,7 @@ + spin_lock_init(&q->rspq.lock); + + q->txq[TXQ_ETH].stop_thres = nports * +- flits_to_desc(sgl_len(MAX_SKB_FRAGS + 1) + 3); ++ flits_to_desc(sgl_len(MAX_SKB_FRAGS + 1) + 3); + + #if FL0_PG_CHUNK_SIZE > 0 + q->fl[0].buf_size = FL0_PG_CHUNK_SIZE; +@@ -2967,7 +3868,13 @@ + #if FL1_PG_CHUNK_SIZE > 0 + q->fl[1].buf_size = FL1_PG_CHUNK_SIZE; + #else +- q->fl[1].buf_size = is_offload(adapter) ? ++ q->fl[1].buf_size = ++ /* ++ * For versions of the driver which can support TOE, the hardware ++ * can drop up to 16KB into memory. This really ought to be ++ * covered by a different predicate ... ++ */ ++ is_offload(adapter) ? + (16 * 1024) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : + MAX_FRAME_SIZE + 2 + sizeof(struct cpl_rx_pkt); + #endif +@@ -2977,11 +3884,7 @@ + q->fl[0].order = FL0_PG_ORDER; + q->fl[1].order = FL1_PG_ORDER; + +- q->lro_frag_tbl = kcalloc(MAX_FRAME_SIZE / FL1_PG_CHUNK_SIZE + 1, +- sizeof(struct skb_frag_struct), +- GFP_KERNEL); +- q->lro_nfrags = q->lro_frag_len = 0; +- spin_lock_irq(&adapter->sge.reg_lock); ++ spin_lock(&adapter->sge.reg_lock); + + /* FL threshold comparison uses < */ + ret = t3_sge_init_rspcntxt(adapter, q->rspq.cntxt_id, irq_vec_idx, +@@ -3025,45 +3928,68 @@ + goto err_unlock; + } + +- spin_unlock_irq(&adapter->sge.reg_lock); ++ spin_unlock(&adapter->sge.reg_lock); + + q->adap = adapter; +- q->netdev = dev; ++ q->netdev = netdev; + t3_update_qset_coalesce(q, p); +- +- init_lro_mgr(q, lro_mgr); +- +- avail = refill_fl(adapter, &q->fl[0], q->fl[0].size, +- GFP_KERNEL | __GFP_COMP); +- if (!avail) { ++ q->lro.enabled = p->lro; ++ ++#if !defined(NAPI_UPDATE) ++ /* Link the current queue to the corresponding dummy netdevice */ ++ pi->qs = q; ++#endif ++ ++ refill_fl(adapter, &q->fl[0], q->fl[0].size, GFP_KERNEL | FL_GFP_FLAGS); ++ if (!q->fl[0].credits) { + CH_ALERT(adapter, "free list queue 0 initialization failed\n"); + goto err; + } +- if (avail < q->fl[0].size) ++ if (q->fl[0].credits < q->fl[0].size) + CH_WARN(adapter, "free list queue 0 enabled with %d credits\n", +- avail); +- +- avail = refill_fl(adapter, &q->fl[1], q->fl[1].size, +- GFP_KERNEL | __GFP_COMP); +- if (avail < q->fl[1].size) ++ q->fl[0].credits); ++ ++ refill_fl(adapter, &q->fl[1], q->fl[1].size, GFP_KERNEL | FL_GFP_FLAGS); ++ if (q->fl[1].credits < q->fl[1].size) + CH_WARN(adapter, "free list queue 1 enabled with %d credits\n", +- avail); ++ q->fl[1].credits); + refill_rspq(adapter, &q->rspq, q->rspq.size - 1); + + t3_write_reg(adapter, A_SG_GTS, V_RSPQ(q->rspq.cntxt_id) | + V_NEWTIMER(q->rspq.holdoff_tmr)); + +- mod_timer(&q->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); + return 0; + + err_unlock: +- spin_unlock_irq(&adapter->sge.reg_lock); ++ spin_unlock(&adapter->sge.reg_lock); + err: + t3_free_qset(adapter, q); + return ret; + } + + /** ++ * t3_start_sge_timers - start SGE timer call backs ++ * @adap: the adapter ++ * ++ * Starts each SGE queue set's timer call back ++ */ ++void t3_start_sge_timers(struct adapter *adap) ++{ ++ int i; ++ ++ for (i = 0; i < SGE_QSETS; ++i) { ++ struct sge_qset *q = &adap->sge.qs[i]; ++ ++ if (q->tx_reclaim_timer.function) ++ mod_timer(&q->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); ++ ++ if (q->rx_reclaim_timer.function) ++ mod_timer(&q->rx_reclaim_timer, jiffies + RX_RECLAIM_PERIOD); ++ ++ } ++} ++ ++/** + * t3_stop_sge_timers - stop SGE timer call backs + * @adap: the adapter + * +@@ -3078,16 +4004,19 @@ + + if (q->tx_reclaim_timer.function) + del_timer_sync(&q->tx_reclaim_timer); +- } +-} +- ++ ++ if (q->rx_reclaim_timer.function) ++ del_timer_sync(&q->rx_reclaim_timer); ++ } ++} ++ + /** + * t3_free_sge_resources - free SGE resources + * @adap: the adapter + * + * Frees resources used by the SGE queue sets. + */ +-void t3_free_sge_resources(struct adapter *adap) ++void t3_free_sge_resources(adapter_t *adap) + { + int i; + +@@ -3102,7 +4031,7 @@ + * Enables the SGE for DMAs. This is the last step in starting packet + * transfers. + */ +-void t3_sge_start(struct adapter *adap) ++void t3_sge_start(adapter_t *adap) + { + t3_set_reg_field(adap, A_SG_CONTROL, F_GLOBALENABLE, F_GLOBALENABLE); + } +@@ -3120,7 +4049,7 @@ + * later from process context, at which time the tasklets will be stopped + * if they are still running. + */ +-void t3_sge_stop(struct adapter *adap) ++void t3_sge_stop(adapter_t *adap) + { + t3_set_reg_field(adap, A_SG_CONTROL, F_GLOBALENABLE, 0); + if (!in_interrupt()) { +@@ -3145,14 +4074,14 @@ + * top-level must request those individually. We also do not enable DMA + * here, that should be done after the queues have been set up. + */ +-void t3_sge_init(struct adapter *adap, struct sge_params *p) ++void t3_sge_init(adapter_t *adap, struct sge_params *p) + { + unsigned int ctrl, ups = ffs(pci_resource_len(adap->pdev, 2) >> 12); + + ctrl = F_DROPPKT | V_PKTSHIFT(2) | F_FLMODE | F_AVOIDCQOVFL | +- F_CQCRDTCTRL | F_CONGMODE | F_TNLFLMODE | F_FATLPERREN | +- V_HOSTPAGESIZE(PAGE_SHIFT - 11) | F_BIGENDIANINGRESS | +- V_USERSPACESIZE(ups ? ups - 1 : 0) | F_ISCSICOALESCING; ++ F_CQCRDTCTRL | F_CONGMODE | F_TNLFLMODE | F_FATLPERREN | ++ V_HOSTPAGESIZE(PAGE_SHIFT - 11) | F_BIGENDIANINGRESS | ++ V_USERSPACESIZE(ups ? ups - 1 : 0) | F_ISCSICOALESCING; + #if SGE_NUM_GENBITS == 1 + ctrl |= F_EGRGENCTRL; + #endif +@@ -3184,21 +4113,26 @@ + * defaults for the assorted SGE parameters, which admins can change until + * they are used to initialize the SGE. + */ +-void t3_sge_prep(struct adapter *adap, struct sge_params *p) ++void __devinit t3_sge_prep(adapter_t *adap, struct sge_params *p) + { + int i; + + p->max_pkt_size = (16 * 1024) - sizeof(struct cpl_rx_data) - +- SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); ++ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); + + for (i = 0; i < SGE_QSETS; ++i) { + struct qset_params *q = p->qset + i; + ++ if (adap->params.nports > 2) ++ q->coalesce_usecs = 50; ++ else ++ q->coalesce_usecs = 5; ++ + q->polling = adap->params.rev > 0; +- q->coalesce_usecs = 5; ++ q->lro = 1; + q->rspq_size = 1024; + q->fl_size = 1024; +- q->jumbo_size = 512; ++ q->jumbo_size = 512; + q->txq_size[TXQ_ETH] = 1024; + q->txq_size[TXQ_OFLD] = 1024; + q->txq_size[TXQ_CTRL] = 256; +diff -r c6413c34aa41 drivers/net/cxgb3/sge_defs.h +--- a/drivers/net/cxgb3/sge_defs.h Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/sge_defs.h Tue Oct 06 09:38:00 2009 +0100 +@@ -252,4 +252,4 @@ + #define V_RSPD_INR_VEC(x) ((x) << S_RSPD_INR_VEC) + #define G_RSPD_INR_VEC(x) (((x) >> S_RSPD_INR_VEC) & M_RSPD_INR_VEC) + +-#endif /* _SGE_DEFS_H */ ++#endif /* _SGE_DEFS_H */ +diff -r c6413c34aa41 drivers/net/cxgb3/t3_cpl.h +--- a/drivers/net/cxgb3/t3_cpl.h Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/t3_cpl.h Tue Oct 06 09:38:00 2009 +0100 +@@ -1,34 +1,16 @@ + /* +- * Copyright (c) 2004-2007 Chelsio, Inc. All rights reserved. ++ * Definitions of the CPL 5 commands and status codes. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: ++ * Copyright (C) 2004-2009 Chelsio Communications. All rights reserved. + * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: ++ * Written by Dimitris Michailidis (dm@chelsio.com) + * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ ++ + #ifndef T3_CPL_H + #define T3_CPL_H + +@@ -37,121 +19,125 @@ + #endif + + enum CPL_opcode { +- CPL_PASS_OPEN_REQ = 0x1, +- CPL_PASS_ACCEPT_RPL = 0x2, +- CPL_ACT_OPEN_REQ = 0x3, +- CPL_SET_TCB = 0x4, +- CPL_SET_TCB_FIELD = 0x5, +- CPL_GET_TCB = 0x6, +- CPL_PCMD = 0x7, +- CPL_CLOSE_CON_REQ = 0x8, ++ CPL_PASS_OPEN_REQ = 0x1, ++ CPL_PASS_ACCEPT_RPL = 0x2, ++ CPL_ACT_OPEN_REQ = 0x3, ++ CPL_SET_TCB = 0x4, ++ CPL_SET_TCB_FIELD = 0x5, ++ CPL_GET_TCB = 0x6, ++ CPL_PCMD = 0x7, ++ CPL_CLOSE_CON_REQ = 0x8, + CPL_CLOSE_LISTSRV_REQ = 0x9, +- CPL_ABORT_REQ = 0xA, +- CPL_ABORT_RPL = 0xB, +- CPL_TX_DATA = 0xC, +- CPL_RX_DATA_ACK = 0xD, +- CPL_TX_PKT = 0xE, +- CPL_RTE_DELETE_REQ = 0xF, +- CPL_RTE_WRITE_REQ = 0x10, +- CPL_RTE_READ_REQ = 0x11, +- CPL_L2T_WRITE_REQ = 0x12, +- CPL_L2T_READ_REQ = 0x13, +- CPL_SMT_WRITE_REQ = 0x14, +- CPL_SMT_READ_REQ = 0x15, +- CPL_TX_PKT_LSO = 0x16, +- CPL_PCMD_READ = 0x17, +- CPL_BARRIER = 0x18, +- CPL_TID_RELEASE = 0x1A, ++ CPL_ABORT_REQ = 0xA, ++ CPL_ABORT_RPL = 0xB, ++ CPL_TX_DATA = 0xC, ++ CPL_RX_DATA_ACK = 0xD, ++ CPL_TX_PKT = 0xE, ++ CPL_RTE_DELETE_REQ = 0xF, ++ CPL_RTE_WRITE_REQ = 0x10, ++ CPL_RTE_READ_REQ = 0x11, ++ CPL_L2T_WRITE_REQ = 0x12, ++ CPL_L2T_READ_REQ = 0x13, ++ CPL_SMT_WRITE_REQ = 0x14, ++ CPL_SMT_READ_REQ = 0x15, ++ CPL_TX_PKT_LSO = 0x16, ++ CPL_PCMD_READ = 0x17, ++ CPL_BARRIER = 0x18, ++ CPL_TID_RELEASE = 0x1A, + + CPL_CLOSE_LISTSRV_RPL = 0x20, +- CPL_ERROR = 0x21, +- CPL_GET_TCB_RPL = 0x22, +- CPL_L2T_WRITE_RPL = 0x23, +- CPL_PCMD_READ_RPL = 0x24, +- CPL_PCMD_RPL = 0x25, +- CPL_PEER_CLOSE = 0x26, +- CPL_RTE_DELETE_RPL = 0x27, +- CPL_RTE_WRITE_RPL = 0x28, +- CPL_RX_DDP_COMPLETE = 0x29, +- CPL_RX_PHYS_ADDR = 0x2A, +- CPL_RX_PKT = 0x2B, +- CPL_RX_URG_NOTIFY = 0x2C, +- CPL_SET_TCB_RPL = 0x2D, +- CPL_SMT_WRITE_RPL = 0x2E, +- CPL_TX_DATA_ACK = 0x2F, ++ CPL_ERROR = 0x21, ++ CPL_GET_TCB_RPL = 0x22, ++ CPL_L2T_WRITE_RPL = 0x23, ++ CPL_PCMD_READ_RPL = 0x24, ++ CPL_PCMD_RPL = 0x25, ++ CPL_PEER_CLOSE = 0x26, ++ CPL_RTE_DELETE_RPL = 0x27, ++ CPL_RTE_WRITE_RPL = 0x28, ++ CPL_RX_DDP_COMPLETE = 0x29, ++ CPL_RX_PHYS_ADDR = 0x2A, ++ CPL_RX_PKT = 0x2B, ++ CPL_RX_URG_NOTIFY = 0x2C, ++ CPL_SET_TCB_RPL = 0x2D, ++ CPL_SMT_WRITE_RPL = 0x2E, ++ CPL_TX_DATA_ACK = 0x2F, + +- CPL_ABORT_REQ_RSS = 0x30, +- CPL_ABORT_RPL_RSS = 0x31, +- CPL_CLOSE_CON_RPL = 0x32, +- CPL_ISCSI_HDR = 0x33, +- CPL_L2T_READ_RPL = 0x34, +- CPL_RDMA_CQE = 0x35, ++ CPL_ABORT_REQ_RSS = 0x30, ++ CPL_ABORT_RPL_RSS = 0x31, ++ CPL_CLOSE_CON_RPL = 0x32, ++ CPL_ISCSI_HDR = 0x33, ++ CPL_L2T_READ_RPL = 0x34, ++ CPL_RDMA_CQE = 0x35, + CPL_RDMA_CQE_READ_RSP = 0x36, +- CPL_RDMA_CQE_ERR = 0x37, +- CPL_RTE_READ_RPL = 0x38, +- CPL_RX_DATA = 0x39, ++ CPL_RDMA_CQE_ERR = 0x37, ++ CPL_RTE_READ_RPL = 0x38, ++ CPL_RX_DATA = 0x39, + +- CPL_ACT_OPEN_RPL = 0x40, +- CPL_PASS_OPEN_RPL = 0x41, +- CPL_RX_DATA_DDP = 0x42, +- CPL_SMT_READ_RPL = 0x43, ++ CPL_ACT_OPEN_RPL = 0x40, ++ CPL_PASS_OPEN_RPL = 0x41, ++ CPL_RX_DATA_DDP = 0x42, ++ CPL_SMT_READ_RPL = 0x43, + +- CPL_ACT_ESTABLISH = 0x50, +- CPL_PASS_ESTABLISH = 0x51, ++ CPL_ACT_ESTABLISH = 0x50, ++ CPL_PASS_ESTABLISH = 0x51, + +- CPL_PASS_ACCEPT_REQ = 0x70, ++ CPL_PASS_ACCEPT_REQ = 0x70, + +- CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */ ++ CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */ + +- CPL_TX_DMA_ACK = 0xA0, +- CPL_RDMA_READ_REQ = 0xA1, +- CPL_RDMA_TERMINATE = 0xA2, +- CPL_TRACE_PKT = 0xA3, +- CPL_RDMA_EC_STATUS = 0xA5, ++ CPL_TX_DMA_ACK = 0xA0, ++ CPL_RDMA_READ_REQ = 0xA1, ++ CPL_RDMA_TERMINATE = 0xA2, ++ CPL_TRACE_PKT = 0xA3, ++ CPL_RDMA_EC_STATUS = 0xA5, ++ CPL_SGE_EC_CR_RETURN = 0xA6, + +- NUM_CPL_CMDS /* must be last and previous entries must be sorted */ ++ NUM_CPL_CMDS /* must be last and previous entries must be sorted */ + }; + + enum CPL_error { +- CPL_ERR_NONE = 0, +- CPL_ERR_TCAM_PARITY = 1, +- CPL_ERR_TCAM_FULL = 3, +- CPL_ERR_CONN_RESET = 20, +- CPL_ERR_CONN_EXIST = 22, +- CPL_ERR_ARP_MISS = 23, +- CPL_ERR_BAD_SYN = 24, +- CPL_ERR_CONN_TIMEDOUT = 30, +- CPL_ERR_XMIT_TIMEDOUT = 31, +- CPL_ERR_PERSIST_TIMEDOUT = 32, +- CPL_ERR_FINWAIT2_TIMEDOUT = 33, ++ CPL_ERR_NONE = 0, ++ CPL_ERR_TCAM_PARITY = 1, ++ CPL_ERR_TCAM_FULL = 3, ++ CPL_ERR_CONN_RESET = 20, ++ CPL_ERR_CONN_EXIST = 22, ++ CPL_ERR_ARP_MISS = 23, ++ CPL_ERR_BAD_SYN = 24, ++ CPL_ERR_CONN_TIMEDOUT = 30, ++ CPL_ERR_XMIT_TIMEDOUT = 31, ++ CPL_ERR_PERSIST_TIMEDOUT = 32, ++ CPL_ERR_FINWAIT2_TIMEDOUT = 33, + CPL_ERR_KEEPALIVE_TIMEDOUT = 34, +- CPL_ERR_RTX_NEG_ADVICE = 35, ++ CPL_ERR_RTX_NEG_ADVICE = 35, + CPL_ERR_PERSIST_NEG_ADVICE = 36, +- CPL_ERR_ABORT_FAILED = 42, +- CPL_ERR_GENERAL = 99 ++ CPL_ERR_ABORT_FAILED = 42, ++ CPL_ERR_GENERAL = 99 + }; + + enum { + CPL_CONN_POLICY_AUTO = 0, +- CPL_CONN_POLICY_ASK = 1, ++ CPL_CONN_POLICY_ASK = 1, ++ CPL_CONN_POLICY_FILTER = 2, + CPL_CONN_POLICY_DENY = 3 + }; + + enum { +- ULP_MODE_NONE = 0, +- ULP_MODE_ISCSI = 2, +- ULP_MODE_RDMA = 4, +- ULP_MODE_TCPDDP = 5 ++ ULP_MODE_NONE = 0, ++ ULP_MODE_TCP_DDP = 1, ++ ULP_MODE_ISCSI = 2, ++ ULP_MODE_RDMA = 4, ++ ULP_MODE_TCPDDP = 5 + }; + + enum { + ULP_CRC_HEADER = 1 << 0, +- ULP_CRC_DATA = 1 << 1 ++ ULP_CRC_DATA = 1 << 1 + }; + + enum { + CPL_PASS_OPEN_ACCEPT, +- CPL_PASS_OPEN_REJECT ++ CPL_PASS_OPEN_REJECT, ++ CPL_PASS_OPEN_ACCEPT_TNL + }; + + enum { +@@ -160,21 +146,21 @@ + CPL_ABORT_POST_CLOSE_REQ = 2 + }; + +-enum { /* TX_PKT_LSO ethernet types */ ++enum { /* TX_PKT_LSO ethernet types */ + CPL_ETH_II, + CPL_ETH_II_VLAN, + CPL_ETH_802_3, + CPL_ETH_802_3_VLAN + }; + +-enum { /* TCP congestion control algorithms */ ++enum { /* TCP congestion control algorithms */ + CONG_ALG_RENO, + CONG_ALG_TAHOE, + CONG_ALG_NEWRENO, + CONG_ALG_HIGHSPEED + }; + +-enum { /* RSS hash type */ ++enum { /* RSS hash type */ + RSS_HASH_NONE = 0, + RSS_HASH_2_TUPLE = 1, + RSS_HASH_4_TUPLE = 2, +@@ -191,13 +177,6 @@ + #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) + #define G_TID(x) ((x) & 0xFFFFFF) + +-#define S_QNUM 0 +-#define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF) +- +-#define S_HASHTYPE 22 +-#define M_HASHTYPE 0x3 +-#define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) +- + /* tid is assumed to be 24-bits */ + #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid)) + +@@ -210,7 +189,7 @@ + __be16 mss; + __u8 wsf; + #if defined(__LITTLE_ENDIAN_BITFIELD) +- __u8:5; ++ __u8 :5; + __u8 ecn:1; + __u8 sack:1; + __u8 tstamp:1; +@@ -218,7 +197,7 @@ + __u8 tstamp:1; + __u8 sack:1; + __u8 ecn:1; +- __u8:5; ++ __u8 :5; + #endif + }; + +@@ -234,6 +213,14 @@ + __be16 cq_idx; + __be32 rss_hash_val; + }; ++ ++#define S_HASHTYPE 22 ++#define M_HASHTYPE 0x3 ++#define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) ++ ++#define S_QNUM 0 ++#define M_QNUM 0xFFFF ++#define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) + + #ifndef CHELSIO_FW + struct work_request_hdr { +@@ -256,6 +243,30 @@ + #define M_WR_BCNTLFLT 0xF + #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT) + #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT) ++ ++/* ++ * Applicable to BYPASS WRs only: the uP will add a CPL_BARRIER before ++ * and after the BYPASS WR if the ATOMIC bit is set. ++ */ ++#define S_WR_ATOMIC 16 ++#define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC) ++#define F_WR_ATOMIC V_WR_ATOMIC(1U) ++ ++/* ++ * Applicable to BYPASS WRs only: the uP will flush buffered non abort ++ * related WRs. ++ */ ++#define S_WR_FLUSH 17 ++#define V_WR_FLUSH(x) ((x) << S_WR_FLUSH) ++#define F_WR_FLUSH V_WR_FLUSH(1U) ++ ++#define S_WR_CHN 18 ++#define V_WR_CHN(x) ((x) << S_WR_CHN) ++#define F_WR_CHN V_WR_CHN(1U) ++ ++#define S_WR_CHN_VLD 19 ++#define V_WR_CHN_VLD(x) ((x) << S_WR_CHN_VLD) ++#define F_WR_CHN_VLD V_WR_CHN_VLD(1U) + + #define S_WR_DATATYPE 20 + #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE) +@@ -402,6 +413,11 @@ + #define V_CPU_IDX(x) ((x) << S_CPU_IDX) + #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX) + ++#define S_OPT1_VLAN 6 ++#define M_OPT1_VLAN 0xFFF ++#define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN) ++#define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN) ++ + #define S_MAC_MATCH_VALID 18 + #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID) + #define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U) +@@ -489,7 +505,8 @@ + }; + + struct cpl_pass_open_rpl { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be16 local_port; + __be16 peer_port; + __be32 local_ip; +@@ -499,7 +516,8 @@ + }; + + struct cpl_pass_establish { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be16 local_port; + __be16 peer_port; + __be32 local_ip; +@@ -536,28 +554,29 @@ + #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) + + struct cpl_pass_accept_req { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be16 local_port; + __be16 peer_port; + __be32 local_ip; + __be32 peer_ip; + __be32 tos_tid; + struct tcp_options tcp_options; +- __u8 dst_mac[6]; ++ __u8 dst_mac[6]; + __be16 vlan_tag; +- __u8 src_mac[6]; ++ __u8 src_mac[6]; + #if defined(__LITTLE_ENDIAN_BITFIELD) +- __u8:3; +- __u8 addr_idx:3; +- __u8 port_idx:1; +- __u8 exact_match:1; ++ __u8 :3; ++ __u8 addr_idx:3; ++ __u8 port_idx:1; ++ __u8 exact_match:1; + #else +- __u8 exact_match:1; +- __u8 port_idx:1; +- __u8 addr_idx:3; +- __u8:3; ++ __u8 exact_match:1; ++ __u8 port_idx:1; ++ __u8 addr_idx:3; ++ __u8 :3; + #endif +- __u8 rsvd; ++ __u8 rsvd; + __be32 rcv_isn; + __be32 rsvd2; + }; +@@ -615,18 +634,20 @@ + #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN) + + struct cpl_act_open_rpl { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be16 local_port; + __be16 peer_port; + __be32 local_ip; + __be32 peer_ip; + __be32 atid; +- __u8 rsvd[3]; +- __u8 status; ++ __u8 rsvd[3]; ++ __u8 status; + }; + + struct cpl_act_establish { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be16 local_port; + __be16 peer_port; + __be32 local_ip; +@@ -646,7 +667,8 @@ + }; + + struct cpl_get_tcb_rpl { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __u8 rsvd; + __u8 status; + __be16 len; +@@ -655,8 +677,8 @@ + struct cpl_set_tcb { + WR_HDR; + union opcode_tid ot; +- __u8 reply; +- __u8 cpu_idx; ++ __u8 reply; ++ __u8 cpu_idx; + __be16 len; + }; + +@@ -668,15 +690,16 @@ + struct cpl_set_tcb_field { + WR_HDR; + union opcode_tid ot; +- __u8 reply; +- __u8 cpu_idx; ++ __u8 reply; ++ __u8 cpu_idx; + __be16 word; + __be64 mask; + __be64 val; + }; + + struct cpl_set_tcb_rpl { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __u8 rsvd[3]; + __u8 status; + }; +@@ -689,9 +712,9 @@ + __u8 src:1; + __u8 bundle:1; + __u8 channel:1; +- __u8:5; ++ __u8 :5; + #else +- __u8:5; ++ __u8 :5; + __u8 channel:1; + __u8 bundle:1; + __u8 src:1; +@@ -700,9 +723,10 @@ + }; + + struct cpl_pcmd_reply { +- RSS_HDR union opcode_tid ot; +- __u8 status; +- __u8 rsvd; ++ RSS_HDR ++ union opcode_tid ot; ++ __u8 status; ++ __u8 rsvd; + __be16 len; + }; + +@@ -713,9 +737,10 @@ + }; + + struct cpl_close_con_rpl { +- RSS_HDR union opcode_tid ot; +- __u8 rsvd[3]; +- __u8 status; ++ RSS_HDR ++ union opcode_tid ot; ++ __u8 rsvd[3]; ++ __u8 status; + __be32 snd_nxt; + __be32 rcv_nxt; + }; +@@ -723,53 +748,57 @@ + struct cpl_close_listserv_req { + WR_HDR; + union opcode_tid ot; +- __u8 rsvd0; +- __u8 cpu_idx; ++ __u8 rsvd0; ++ __u8 cpu_idx; + __be16 rsvd1; + }; + + struct cpl_close_listserv_rpl { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __u8 rsvd[3]; + __u8 status; + }; + + struct cpl_abort_req_rss { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be32 rsvd0; +- __u8 rsvd1; +- __u8 status; +- __u8 rsvd2[6]; ++ __u8 rsvd1; ++ __u8 status; ++ __u8 rsvd2[6]; + }; + + struct cpl_abort_req { + WR_HDR; + union opcode_tid ot; + __be32 rsvd0; +- __u8 rsvd1; +- __u8 cmd; +- __u8 rsvd2[6]; ++ __u8 rsvd1; ++ __u8 cmd; ++ __u8 rsvd2[6]; + }; + + struct cpl_abort_rpl_rss { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be32 rsvd0; +- __u8 rsvd1; +- __u8 status; +- __u8 rsvd2[6]; ++ __u8 rsvd1; ++ __u8 status; ++ __u8 rsvd2[6]; + }; + + struct cpl_abort_rpl { + WR_HDR; + union opcode_tid ot; + __be32 rsvd0; +- __u8 rsvd1; +- __u8 cmd; +- __u8 rsvd2[6]; ++ __u8 rsvd1; ++ __u8 cmd; ++ __u8 rsvd2[6]; + }; + + struct cpl_peer_close { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be32 rcv_nxt; + }; + +@@ -783,8 +812,8 @@ + }; + + /* tx_data_wr.flags fields */ +-#define S_TX_ACK_PAGES 21 +-#define M_TX_ACK_PAGES 0x7 ++#define S_TX_ACK_PAGES 21 ++#define M_TX_ACK_PAGES 0x7 + #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) + #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) + +@@ -863,45 +892,57 @@ + #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) + + struct cpl_tx_data_ack { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be32 ack_seq; + }; + + struct cpl_wr_ack { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be16 credits; + __be16 rsvd; + __be32 snd_nxt; + __be32 snd_una; + }; + ++struct cpl_sge_ec_cr_return { ++ RSS_HDR ++ union opcode_tid ot; ++ __be16 sge_ec_id; ++ __u8 cr; ++ __u8 rsvd; ++}; ++ + struct cpl_rdma_ec_status { +- RSS_HDR union opcode_tid ot; +- __u8 rsvd[3]; +- __u8 status; ++ RSS_HDR ++ union opcode_tid ot; ++ __u8 rsvd[3]; ++ __u8 status; + }; + + struct mngt_pktsched_wr { + __be32 wr_hi; + __be32 wr_lo; +- __u8 mngt_opcode; +- __u8 rsvd[7]; +- __u8 sched; +- __u8 idx; +- __u8 min; +- __u8 max; +- __u8 binding; +- __u8 rsvd1[3]; ++ __u8 mngt_opcode; ++ __u8 rsvd[7]; ++ __u8 sched; ++ __u8 idx; ++ __u8 min; ++ __u8 max; ++ __u8 binding; ++ __u8 rsvd1[3]; + }; + + struct cpl_iscsi_hdr { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be16 pdu_len_ddp; + __be16 len; + __be32 seq; + __be16 urg; +- __u8 rsvd; +- __u8 status; ++ __u8 rsvd; ++ __u8 status; + }; + + /* cpl_iscsi_hdr.pdu_len_ddp fields */ +@@ -915,23 +956,26 @@ + #define F_ISCSI_DDP V_ISCSI_DDP(1U) + + struct cpl_rx_data { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be16 rsvd; + __be16 len; + __be32 seq; + __be16 urg; + #if defined(__LITTLE_ENDIAN_BITFIELD) +- __u8 dack_mode:2; +- __u8 psh:1; +- __u8 heartbeat:1; +- __u8:4; ++ __u8 dack_mode:2; ++ __u8 psh:1; ++ __u8 heartbeat:1; ++ __u8 ddp_off:1; ++ __u8 :3; + #else +- __u8:4; +- __u8 heartbeat:1; +- __u8 psh:1; +- __u8 dack_mode:2; ++ __u8 :3; ++ __u8 ddp_off:1; ++ __u8 heartbeat:1; ++ __u8 psh:1; ++ __u8 dack_mode:2; + #endif +- __u8 status; ++ __u8 status; + }; + + struct cpl_rx_data_ack { +@@ -964,17 +1008,20 @@ + #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) + + struct cpl_rx_urg_notify { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be32 seq; + }; + + struct cpl_rx_ddp_complete { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be32 ddp_report; + }; + + struct cpl_rx_data_ddp { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be16 urg; + __be16 len; + __be32 seq; +@@ -1060,6 +1107,11 @@ + #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) + #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) + ++#define S_DDP_DACK_MODE 22 ++#define M_DDP_DACK_MODE 0x3 ++#define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) ++#define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) ++ + #define S_DDP_URG 24 + #define V_DDP_URG(x) ((x) << S_DDP_URG) + #define F_DDP_URG V_DDP_URG(1U) +@@ -1084,6 +1136,17 @@ + WR_HDR; + __be32 cntrl; + __be32 len; ++}; ++ ++struct cpl_tx_pkt_coalesce { ++ __be32 cntrl; ++ __be32 len; ++ __be64 addr; ++}; ++ ++struct tx_pkt_coalesce_wr { ++ WR_HDR; ++ struct cpl_tx_pkt_coalesce cpl[0]; + }; + + struct cpl_tx_pkt_lso { +@@ -1157,36 +1220,37 @@ + __u8 rss_opcode; + #if defined(__LITTLE_ENDIAN_BITFIELD) + __u8 err:1; +- __u8:7; ++ __u8 :7; + #else +- __u8:7; ++ __u8 :7; + __u8 err:1; + #endif + __u8 rsvd0; + #if defined(__LITTLE_ENDIAN_BITFIELD) + __u8 qid:4; +- __u8:4; ++ __u8 :4; + #else +- __u8:4; ++ __u8 :4; + __u8 qid:4; + #endif + __be32 tstamp; +-#endif /* CHELSIO_FW */ ++#endif /* CHELSIO_FW */ + +- __u8 opcode; ++ __u8 opcode; + #if defined(__LITTLE_ENDIAN_BITFIELD) +- __u8 iff:4; +- __u8:4; ++ __u8 iff:4; ++ __u8 :4; + #else +- __u8:4; +- __u8 iff:4; ++ __u8 :4; ++ __u8 iff:4; + #endif +- __u8 rsvd[4]; ++ __u8 rsvd[4]; + __be16 len; + }; + + struct cpl_rx_pkt { +- RSS_HDR __u8 opcode; ++ RSS_HDR ++ __u8 opcode; + #if defined(__LITTLE_ENDIAN_BITFIELD) + __u8 iff:4; + __u8 csum_valid:1; +@@ -1209,8 +1273,9 @@ + WR_HDR; + union opcode_tid ot; + __be32 params; +- __u8 rsvd[2]; +- __u8 dst_mac[6]; ++ __u8 rsvd; ++ __u8 port_idx; ++ __u8 dst_mac[6]; + }; + + /* cpl_l2t_write_req.params fields */ +@@ -1235,7 +1300,8 @@ + #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO) + + struct cpl_l2t_write_rpl { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __u8 status; + __u8 rsvd[3]; + }; +@@ -1248,7 +1314,8 @@ + }; + + struct cpl_l2t_read_rpl { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __be32 params; + __u8 rsvd[2]; + __u8 dst_mac[6]; +@@ -1288,13 +1355,14 @@ + #endif + __be16 rsvd2; + __be16 rsvd3; +- __u8 src_mac1[6]; ++ __u8 src_mac1[6]; + __be16 rsvd4; +- __u8 src_mac0[6]; ++ __u8 src_mac0[6]; + }; + + struct cpl_smt_write_rpl { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __u8 status; + __u8 rsvd[3]; + }; +@@ -1304,30 +1372,31 @@ + union opcode_tid ot; + __u8 rsvd0; + #if defined(__LITTLE_ENDIAN_BITFIELD) +- __u8:4; ++ __u8 :4; + __u8 iff:4; + #else + __u8 iff:4; +- __u8:4; ++ __u8 :4; + #endif + __be16 rsvd2; + }; + + struct cpl_smt_read_rpl { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __u8 status; + #if defined(__LITTLE_ENDIAN_BITFIELD) + __u8 mtu_idx:4; +- __u8:4; ++ __u8 :4; + #else +- __u8:4; ++ __u8 :4; + __u8 mtu_idx:4; + #endif + __be16 rsvd2; + __be16 rsvd3; +- __u8 src_mac1[6]; ++ __u8 src_mac1[6]; + __be16 rsvd4; +- __u8 src_mac0[6]; ++ __u8 src_mac0[6]; + }; + + struct cpl_rte_delete_req { +@@ -1352,7 +1421,8 @@ + #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) + + struct cpl_rte_delete_rpl { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __u8 status; + __u8 rsvd[3]; + }; +@@ -1361,13 +1431,13 @@ + WR_HDR; + union opcode_tid ot; + #if defined(__LITTLE_ENDIAN_BITFIELD) +- __u8:6; ++ __u8 :6; + __u8 write_tcam:1; + __u8 write_l2t_lut:1; + #else + __u8 write_l2t_lut:1; + __u8 write_tcam:1; +- __u8:6; ++ __u8 :6; + #endif + __u8 rsvd[3]; + __be32 lut_params; +@@ -1389,7 +1459,8 @@ + #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE) + + struct cpl_rte_write_rpl { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __u8 status; + __u8 rsvd[3]; + }; +@@ -1401,16 +1472,17 @@ + }; + + struct cpl_rte_read_rpl { +- RSS_HDR union opcode_tid ot; ++ RSS_HDR ++ union opcode_tid ot; + __u8 status; + __u8 rsvd0; + __be16 l2t_idx; + #if defined(__LITTLE_ENDIAN_BITFIELD) +- __u8:7; ++ __u8 :7; + __u8 select:1; + #else + __u8 select:1; +- __u8:7; ++ __u8 :7; + #endif + __u8 rsvd2[3]; + __be32 addr; +@@ -1439,16 +1511,16 @@ + __u8 rsvd[2]; + #if defined(__LITTLE_ENDIAN_BITFIELD) + __u8 rspq:3; +- __u8:5; ++ __u8 :5; + #else +- __u8:5; ++ __u8 :5; + __u8 rspq:3; + #endif + __be32 tid_len; + #endif + __be32 msn; + __be32 mo; +- __u8 data[0]; ++ __u8 data[0]; + }; + + /* cpl_rdma_terminate.tid_len fields */ +@@ -1465,12 +1537,12 @@ + /* ULP_TX opcodes */ + enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 }; + +-#define S_ULPTX_CMD 28 +-#define M_ULPTX_CMD 0xF +-#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) ++#define S_ULPTX_CMD 28 ++#define M_ULPTX_CMD 0xF ++#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) + +-#define S_ULPTX_NFLITS 0 +-#define M_ULPTX_NFLITS 0xFF ++#define S_ULPTX_NFLITS 0 ++#define M_ULPTX_NFLITS 0xFF + #define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS) + + struct ulp_mem_io { +@@ -1480,16 +1552,27 @@ + }; + + /* ulp_mem_io.cmd_lock_addr fields */ +-#define S_ULP_MEMIO_ADDR 0 +-#define M_ULP_MEMIO_ADDR 0x7FFFFFF +-#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) +-#define S_ULP_MEMIO_LOCK 27 +-#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) +-#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) ++#define S_ULP_MEMIO_ADDR 0 ++#define M_ULP_MEMIO_ADDR 0x7FFFFFF ++#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) ++ ++#define S_ULP_MEMIO_LOCK 27 ++#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) ++#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) + + /* ulp_mem_io.len fields */ +-#define S_ULP_MEMIO_DATA_LEN 28 +-#define M_ULP_MEMIO_DATA_LEN 0xF +-#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) ++#define S_ULP_MEMIO_DATA_LEN 28 ++#define M_ULP_MEMIO_DATA_LEN 0xF ++#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) + +-#endif /* T3_CPL_H */ ++struct ulp_txpkt { ++ __be32 cmd_dest; ++ __be32 len; ++}; ++ ++/* ulp_txpkt.cmd_dest fields */ ++#define S_ULP_TXPKT_DEST 24 ++#define M_ULP_TXPKT_DEST 0xF ++#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) ++ ++#endif /* T3_CPL_H */ +diff -r c6413c34aa41 drivers/net/cxgb3/t3_hw.c +--- a/drivers/net/cxgb3/t3_hw.c Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/t3_hw.c Tue Oct 06 09:38:00 2009 +0100 +@@ -1,34 +1,14 @@ + /* +- * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved. +- * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: +- * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- */ ++ * This file is part of the Chelsio T3 Ethernet driver. ++ * ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. ++ */ ++ + #include "common.h" + #include "regs.h" + #include "sge_defs.h" +@@ -47,11 +27,10 @@ + * Wait until an operation is completed by checking a bit in a register + * up to @attempts times. If @valp is not NULL the value of the register + * at the time it indicated completion is stored there. Returns 0 if the +- * operation completes and -EAGAIN otherwise. +- */ +- +-int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, +- int polarity, int attempts, int delay, u32 *valp) ++ * operation completes and -EAGAIN otherwise. ++ */ ++int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, ++ int attempts, int delay, u32 *valp) + { + while (1) { + u32 val = t3_read_reg(adapter, reg); +@@ -79,8 +58,8 @@ + * value to the corresponding register. Register addresses are adjusted + * by the supplied offset. + */ +-void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p, +- int n, unsigned int offset) ++void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, ++ unsigned int offset) + { + while (n--) { + t3_write_reg(adapter, p->reg_addr + offset, p->val); +@@ -98,13 +77,12 @@ + * Sets a register field specified by the supplied mask to the + * given value. + */ +-void t3_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, +- u32 val) ++void t3_set_reg_field(adapter_t *adapter, unsigned int addr, u32 mask, u32 val) + { + u32 v = t3_read_reg(adapter, addr) & ~mask; + + t3_write_reg(adapter, addr, v | val); +- t3_read_reg(adapter, addr); /* flush */ ++ (void) t3_read_reg(adapter, addr); /* flush */ + } + + /** +@@ -119,9 +97,9 @@ + * Reads registers that are accessed indirectly through an address/data + * register pair. + */ +-static void t3_read_indirect(struct adapter *adap, unsigned int addr_reg, +- unsigned int data_reg, u32 *vals, +- unsigned int nregs, unsigned int start_idx) ++void t3_read_indirect(adapter_t *adap, unsigned int addr_reg, ++ unsigned int data_reg, u32 *vals, unsigned int nregs, ++ unsigned int start_idx) + { + while (nregs--) { + t3_write_reg(adap, addr_reg, start_idx); +@@ -141,13 +119,13 @@ + * accesses. + */ + int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, +- u64 *buf) +-{ +- static const int shift[] = { 0, 0, 16, 24 }; +- static const int step[] = { 0, 32, 16, 8 }; +- +- unsigned int size64 = mc7->size / 8; /* # of 64-bit words */ +- struct adapter *adap = mc7->adapter; ++ u64 *buf) ++{ ++ static int shift[] = { 0, 0, 16, 24 }; ++ static int step[] = { 0, 32, 16, 8 }; ++ ++ unsigned int size64 = mc7->size / 8; /* # of 64-bit words */ ++ adapter_t *adap = mc7->adapter; + + if (start >= size64 || start + n > size64) + return -EINVAL; +@@ -161,7 +139,8 @@ + int attempts = 10; + u32 val; + +- t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, start); ++ t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, ++ start); + t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0); + val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP); + while ((val & F_BUSY) && attempts--) +@@ -173,13 +152,12 @@ + val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1); + if (mc7->width == 0) { + val64 = t3_read_reg(adap, +- mc7->offset + +- A_MC7_BD_DATA0); +- val64 |= (u64) val << 32; ++ mc7->offset + A_MC7_BD_DATA0); ++ val64 |= (u64)val << 32; + } else { + if (mc7->width > 1) + val >>= shift[mc7->width]; +- val64 |= (u64) val << (step[mc7->width] * i); ++ val64 |= (u64)val << (step[mc7->width] * i); + } + start += 8; + } +@@ -191,12 +169,12 @@ + /* + * Initialize MI1. + */ +-static void mi1_init(struct adapter *adap, const struct adapter_info *ai) +-{ +- u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1; +- u32 val = F_PREEN | V_CLKDIV(clkdiv); +- +- t3_write_reg(adap, A_MI1_CFG, val); ++static void mi1_init(adapter_t *adap, const struct adapter_info *ai) ++{ ++ u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1; ++ u32 val = F_PREEN | V_CLKDIV(clkdiv); ++ ++ t3_write_reg(adap, A_MI1_CFG, val); + } + + #define MDIO_ATTEMPTS 20 +@@ -204,8 +182,8 @@ + /* + * MI1 read/write operations for clause 22 PHYs. + */ +-static int t3_mi1_read(struct adapter *adapter, int phy_addr, int mmd_addr, +- int reg_addr, unsigned int *valp) ++int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, ++ int reg_addr, unsigned int *valp) + { + int ret; + u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr); +@@ -213,19 +191,19 @@ + if (mmd_addr) + return -EINVAL; + +- mutex_lock(&adapter->mdio_lock); ++ MDIO_LOCK(adapter); + t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1)); + t3_write_reg(adapter, A_MI1_ADDR, addr); + t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2)); + ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); + if (!ret) + *valp = t3_read_reg(adapter, A_MI1_DATA); +- mutex_unlock(&adapter->mdio_lock); +- return ret; +-} +- +-static int t3_mi1_write(struct adapter *adapter, int phy_addr, int mmd_addr, +- int reg_addr, unsigned int val) ++ MDIO_UNLOCK(adapter); ++ return ret; ++} ++ ++int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, ++ int reg_addr, unsigned int val) + { + int ret; + u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr); +@@ -233,48 +211,36 @@ + if (mmd_addr) + return -EINVAL; + +- mutex_lock(&adapter->mdio_lock); ++ MDIO_LOCK(adapter); + t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1)); + t3_write_reg(adapter, A_MI1_ADDR, addr); + t3_write_reg(adapter, A_MI1_DATA, val); + t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1)); + ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); +- mutex_unlock(&adapter->mdio_lock); +- return ret; +-} +- +-static const struct mdio_ops mi1_mdio_ops = { ++ MDIO_UNLOCK(adapter); ++ return ret; ++} ++ ++static struct mdio_ops mi1_mdio_ops = { + t3_mi1_read, + t3_mi1_write + }; + + /* +- * Performs the address cycle for clause 45 PHYs. +- * Must be called with the MDIO_LOCK held. +- */ +-static int mi1_wr_addr(struct adapter *adapter, int phy_addr, int mmd_addr, +- int reg_addr) +-{ ++ * MI1 read/write operations for clause 45 PHYs. ++ */ ++static int mi1_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr, ++ int reg_addr, unsigned int *valp) ++{ ++ int ret; + u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr); + ++ MDIO_LOCK(adapter); + t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0); + t3_write_reg(adapter, A_MI1_ADDR, addr); + t3_write_reg(adapter, A_MI1_DATA, reg_addr); + t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0)); +- return t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, +- MDIO_ATTEMPTS, 10); +-} +- +-/* +- * MI1 read/write operations for indirect-addressed PHYs. +- */ +-static int mi1_ext_read(struct adapter *adapter, int phy_addr, int mmd_addr, +- int reg_addr, unsigned int *valp) +-{ +- int ret; +- +- mutex_lock(&adapter->mdio_lock); +- ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr); ++ ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); + if (!ret) { + t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3)); + ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, +@@ -282,28 +248,33 @@ + if (!ret) + *valp = t3_read_reg(adapter, A_MI1_DATA); + } +- mutex_unlock(&adapter->mdio_lock); +- return ret; +-} +- +-static int mi1_ext_write(struct adapter *adapter, int phy_addr, int mmd_addr, ++ MDIO_UNLOCK(adapter); ++ return ret; ++} ++ ++static int mi1_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr, + int reg_addr, unsigned int val) + { + int ret; +- +- mutex_lock(&adapter->mdio_lock); +- ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr); ++ u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr); ++ ++ MDIO_LOCK(adapter); ++ t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0); ++ t3_write_reg(adapter, A_MI1_ADDR, addr); ++ t3_write_reg(adapter, A_MI1_DATA, reg_addr); ++ t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0)); ++ ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); + if (!ret) { + t3_write_reg(adapter, A_MI1_DATA, val); + t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1)); + ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, + MDIO_ATTEMPTS, 10); + } +- mutex_unlock(&adapter->mdio_lock); +- return ret; +-} +- +-static const struct mdio_ops mi1_mdio_ext_ops = { ++ MDIO_UNLOCK(adapter); ++ return ret; ++} ++ ++static struct mdio_ops mi1_mdio_ext_ops = { + mi1_ext_read, + mi1_ext_write + }; +@@ -460,7 +431,7 @@ + if (duplex == DUPLEX_FULL) + ctl |= BMCR_FULLDPLX; + } +- if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */ ++ if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */ + ctl |= BMCR_ANENABLE; + return mdio_write(phy, 0, MII_BMCR, ctl); + } +@@ -492,26 +463,42 @@ + return (status & 1) ? cphy_cause_link_change : 0; + } + +-static const struct adapter_info t3_adap_info[] = { +- {2, 0, +- F_GPIO2_OEN | F_GPIO4_OEN | +- F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0, +- &mi1_mdio_ops, "Chelsio PE9000"}, +- {2, 0, +- F_GPIO2_OEN | F_GPIO4_OEN | +- F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0, +- &mi1_mdio_ops, "Chelsio T302"}, +- {1, 0, +- F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN | +- F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, +- { 0 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, +- &mi1_mdio_ext_ops, "Chelsio T310"}, +- {2, 0, +- F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN | +- F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL | +- F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, +- { S_GPIO9, S_GPIO3 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, +- &mi1_mdio_ext_ops, "Chelsio T320"}, ++static struct adapter_info t3_adap_info[] = { ++ { 1, 1, 0, ++ F_GPIO2_OEN | F_GPIO4_OEN | ++ F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0, ++ &mi1_mdio_ops, "Chelsio PE9000" }, ++ { 1, 1, 0, ++ F_GPIO2_OEN | F_GPIO4_OEN | ++ F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0, ++ &mi1_mdio_ops, "Chelsio T302" }, ++ { 1, 0, 0, ++ F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN | ++ F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, ++ { 0 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, ++ &mi1_mdio_ext_ops, "Chelsio T310" }, ++ { 1, 1, 0, ++ F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN | ++ F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL | ++ F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, ++ { S_GPIO9, S_GPIO3 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, ++ &mi1_mdio_ext_ops, "Chelsio T320" }, ++ { 4, 0, 0, ++ F_GPIO5_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO5_OUT_VAL | ++ F_GPIO6_OUT_VAL | F_GPIO7_OUT_VAL, ++ { S_GPIO1, S_GPIO2, S_GPIO3, S_GPIO4 }, SUPPORTED_AUI, ++ &mi1_mdio_ops, "Chelsio T304" }, ++ { }, ++ { 1, 0, 0, ++ F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO6_OEN | F_GPIO7_OEN | ++ F_GPIO10_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, ++ { S_GPIO9 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, ++ &mi1_mdio_ext_ops, "Chelsio T310" }, ++ { 1, 0, 0, ++ F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | ++ F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL, ++ { S_GPIO9 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, ++ &mi1_mdio_ext_ops, "Chelsio N320E-G2" }, + }; + + /* +@@ -524,20 +511,22 @@ + } + + struct port_type_info { +- int (*phy_prep)(struct cphy *phy, struct adapter *adapter, +- int phy_addr, const struct mdio_ops *ops); +-}; +- +-static const struct port_type_info port_types[] = { ++ int (*phy_prep)(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *ops); ++}; ++ ++static struct port_type_info port_types[] = { + { NULL }, + { t3_ael1002_phy_prep }, + { t3_vsc8211_phy_prep }, +- { NULL}, ++ { t3_mv88e1xxx_phy_prep }, + { t3_xaui_direct_phy_prep }, + { t3_ael2005_phy_prep }, + { t3_qt2045_phy_prep }, + { t3_ael1006_phy_prep }, +- { NULL }, ++ { t3_tn1010_phy_prep }, ++ { t3_aq100x_phy_prep }, ++ { t3_ael2020_phy_prep }, + }; + + #define VPD_ENTRY(name, len) \ +@@ -548,28 +537,28 @@ + * VPD-R sections. + */ + struct t3_vpd { +- u8 id_tag; +- u8 id_len[2]; +- u8 id_data[16]; +- u8 vpdr_tag; +- u8 vpdr_len[2]; +- VPD_ENTRY(pn, 16); /* part number */ +- VPD_ENTRY(ec, 16); /* EC level */ +- VPD_ENTRY(sn, SERNUM_LEN); /* serial number */ +- VPD_ENTRY(na, 12); /* MAC address base */ +- VPD_ENTRY(cclk, 6); /* core clock */ +- VPD_ENTRY(mclk, 6); /* mem clock */ +- VPD_ENTRY(uclk, 6); /* uP clk */ +- VPD_ENTRY(mdc, 6); /* MDIO clk */ +- VPD_ENTRY(mt, 2); /* mem timing */ +- VPD_ENTRY(xaui0cfg, 6); /* XAUI0 config */ +- VPD_ENTRY(xaui1cfg, 6); /* XAUI1 config */ +- VPD_ENTRY(port0, 2); /* PHY0 complex */ +- VPD_ENTRY(port1, 2); /* PHY1 complex */ +- VPD_ENTRY(port2, 2); /* PHY2 complex */ +- VPD_ENTRY(port3, 2); /* PHY3 complex */ +- VPD_ENTRY(rv, 1); /* csum */ +- u32 pad; /* for multiple-of-4 sizing and alignment */ ++ u8 id_tag; ++ u8 id_len[2]; ++ u8 id_data[16]; ++ u8 vpdr_tag; ++ u8 vpdr_len[2]; ++ VPD_ENTRY(pn, 16); /* part number */ ++ VPD_ENTRY(ec, ECNUM_LEN); /* EC level */ ++ VPD_ENTRY(sn, SERNUM_LEN); /* serial number */ ++ VPD_ENTRY(na, 12); /* MAC address base */ ++ VPD_ENTRY(cclk, 6); /* core clock */ ++ VPD_ENTRY(mclk, 6); /* mem clock */ ++ VPD_ENTRY(uclk, 6); /* uP clk */ ++ VPD_ENTRY(mdc, 6); /* MDIO clk */ ++ VPD_ENTRY(mt, 2); /* mem timing */ ++ VPD_ENTRY(xaui0cfg, 6); /* XAUI0 config */ ++ VPD_ENTRY(xaui1cfg, 6); /* XAUI1 config */ ++ VPD_ENTRY(port0, 2); /* PHY0 complex */ ++ VPD_ENTRY(port1, 2); /* PHY1 complex */ ++ VPD_ENTRY(port2, 2); /* PHY2 complex */ ++ VPD_ENTRY(port3, 2); /* PHY3 complex */ ++ VPD_ENTRY(rv, 1); /* csum */ ++ u32 pad; /* for multiple-of-4 sizing and alignment */ + }; + + #define EEPROM_MAX_POLL 40 +@@ -587,28 +576,27 @@ + * addres is written to the control register. The hardware device will + * set the flag to 1 when 4 bytes have been read into the data register. + */ +-int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data) ++int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data) + { + u16 val; + int attempts = EEPROM_MAX_POLL; +- u32 v; + unsigned int base = adapter->params.pci.vpd_cap_addr; + + if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3)) + return -EINVAL; + +- pci_write_config_word(adapter->pdev, base + PCI_VPD_ADDR, addr); ++ t3_os_pci_write_config_2(adapter, base + PCI_VPD_ADDR, (u16)addr); + do { + udelay(10); +- pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val); ++ t3_os_pci_read_config_2(adapter, base + PCI_VPD_ADDR, &val); + } while (!(val & PCI_VPD_ADDR_F) && --attempts); + + if (!(val & PCI_VPD_ADDR_F)) { + CH_ERR(adapter, "reading EEPROM address 0x%x failed\n", addr); + return -EIO; + } +- pci_read_config_dword(adapter->pdev, base + PCI_VPD_DATA, &v); +- *data = cpu_to_le32(v); ++ t3_os_pci_read_config_4(adapter, base + PCI_VPD_DATA, data); ++ *data = le32_to_cpu(*data); + return 0; + } + +@@ -621,7 +609,7 @@ + * Write a 32-bit word to a location in VPD EEPROM using the card's PCI + * VPD ROM capability. + */ +-int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data) ++int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data) + { + u16 val; + int attempts = EEPROM_MAX_POLL; +@@ -630,13 +618,13 @@ + if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3)) + return -EINVAL; + +- pci_write_config_dword(adapter->pdev, base + PCI_VPD_DATA, +- le32_to_cpu(data)); +- pci_write_config_word(adapter->pdev,base + PCI_VPD_ADDR, +- addr | PCI_VPD_ADDR_F); ++ t3_os_pci_write_config_4(adapter, base + PCI_VPD_DATA, ++ cpu_to_le32(data)); ++ t3_os_pci_write_config_2(adapter, base + PCI_VPD_ADDR, ++ (u16)addr | PCI_VPD_ADDR_F); + do { + msleep(1); +- pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val); ++ t3_os_pci_read_config_2(adapter, base + PCI_VPD_ADDR, &val); + } while ((val & PCI_VPD_ADDR_F) && --attempts); + + if (val & PCI_VPD_ADDR_F) { +@@ -653,7 +641,7 @@ + * + * Enables or disables write protection on the serial EEPROM. + */ +-int t3_seeprom_wp(struct adapter *adapter, int enable) ++int t3_seeprom_wp(adapter_t *adapter, int enable) + { + return t3_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); + } +@@ -665,6 +653,125 @@ + { + return isdigit(c) ? c - '0' : toupper(c) - 'A' + 10; + } ++ ++/** ++ * get_desc_len - get the length of a vpd descriptor. ++ * @adapter: the adapter ++ * @offset: first byte offset of the vpd descriptor ++ * ++ * Retrieves the length of the small/large resource ++ * data type starting at offset. ++ */ ++static int get_desc_len(adapter_t *adapter, u32 offset) ++{ ++ u32 read_offset, tmp, shift, len = 0; ++ u8 tag, buf[8]; ++ int ret; ++ ++ read_offset = offset & 0xfffffffc; ++ shift = offset & 0x03; ++ ++ ret = t3_seeprom_read(adapter, read_offset, &tmp); ++ if (ret < 0) ++ return ret; ++ ++ *((u32 *)buf) = cpu_to_le32(tmp); ++ ++ tag = buf[shift]; ++ if (tag & 0x80) { ++ ret = t3_seeprom_read(adapter, read_offset + 4, &tmp); ++ if (ret < 0) ++ return ret; ++ ++ *((u32 *)(&buf[4])) = cpu_to_le32(tmp); ++ len = (buf[shift + 1] & 0xff) + ++ ((buf[shift+2] << 8) & 0xff00) + 3; ++ } else ++ len = (tag & 0x07) + 1; ++ ++ return len; ++} ++ ++/** ++ * is_end_tag - Check if a vpd tag is the end tag. ++ * @adapter: the adapter ++ * @offset: first byte offset of the tag ++ * ++ * Checks if the tag located at offset is the end tag. ++ */ ++static int is_end_tag(adapter_t * adapter, u32 offset) ++{ ++ u32 read_offset, shift, ret, tmp; ++ u8 buf[4]; ++ ++ read_offset = offset & 0xfffffffc; ++ shift = offset & 0x03; ++ ++ ret = t3_seeprom_read(adapter, read_offset, &tmp); ++ if (ret) ++ return ret; ++ *((u32 *)buf) = cpu_to_le32(tmp); ++ ++ if (buf[shift] == 0x78) ++ return 1; ++ else ++ return 0; ++} ++ ++/** ++ * t3_get_vpd_len - computes the length of a vpd structure ++ * @adapter: the adapter ++ * @vpd: contains the offset of first byte of vpd ++ * ++ * Computes the lentgh of the vpd structure starting at vpd->offset. ++ */ ++ ++int t3_get_vpd_len(adapter_t * adapter, struct generic_vpd *vpd) ++{ ++ u32 len=0, offset; ++ int inc, ret; ++ ++ offset = vpd->offset; ++ ++ while (offset < (vpd->offset + MAX_VPD_BYTES)) { ++ ret = is_end_tag(adapter, offset); ++ if (ret < 0) ++ return ret; ++ else if (ret == 1) ++ break; ++ ++ inc = get_desc_len(adapter, offset); ++ if (inc < 0) ++ return inc; ++ len += inc; ++ offset += inc; ++ } ++ return (len + 1); ++} ++ ++/** ++ * t3_read_vpd - reads the stream of bytes containing a vpd structure ++ * @adapter: the adapter ++ * @vpd: contains a buffer that would hold the stream of bytes ++ * ++ * Reads the vpd structure starting at vpd->offset into vpd->data, ++ * the length of the byte stream to read is vpd->len. ++ */ ++ ++int t3_read_vpd(adapter_t *adapter, struct generic_vpd *vpd) ++{ ++ u32 i, ret; ++ ++ for (i = 0; i < vpd->len; i += 4) { ++ ret = t3_seeprom_read(adapter, vpd->offset + i, ++ (u32 *) &(vpd->data[i])); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ + + /** + * get_vpd_params - read VPD parameters from VPD EEPROM +@@ -673,7 +780,7 @@ + * + * Reads card parameters stored in VPD EEPROM. + */ +-static int get_vpd_params(struct adapter *adapter, struct vpd_params *p) ++static int get_vpd_params(adapter_t *adapter, struct vpd_params *p) + { + int i, addr, ret; + struct t3_vpd vpd; +@@ -682,14 +789,14 @@ + * Card information is normally at VPD_BASE but some early cards had + * it at 0. + */ +- ret = t3_seeprom_read(adapter, VPD_BASE, (__le32 *)&vpd); ++ ret = t3_seeprom_read(adapter, VPD_BASE, (u32 *)&vpd); + if (ret) + return ret; + addr = vpd.id_tag == 0x82 ? VPD_BASE : 0; + + for (i = 0; i < sizeof(vpd); i += 4) { + ret = t3_seeprom_read(adapter, addr + i, +- (__le32 *)((u8 *)&vpd + i)); ++ (u32 *)((u8 *)&vpd + i)); + if (ret) + return ret; + } +@@ -700,14 +807,17 @@ + p->mdc = simple_strtoul(vpd.mdc_data, NULL, 10); + p->mem_timing = simple_strtoul(vpd.mt_data, NULL, 10); + memcpy(p->sn, vpd.sn_data, SERNUM_LEN); ++ memcpy(p->ec, vpd.ec_data, ECNUM_LEN); + + /* Old eeproms didn't have port information */ + if (adapter->params.rev == 0 && !vpd.port0_data[0]) { + p->port_type[0] = uses_xaui(adapter) ? 1 : 2; + p->port_type[1] = uses_xaui(adapter) ? 6 : 2; + } else { +- p->port_type[0] = hex2int(vpd.port0_data[0]); +- p->port_type[1] = hex2int(vpd.port1_data[0]); ++ p->port_type[0] = (u8)hex2int(vpd.port0_data[0]); ++ p->port_type[1] = (u8)hex2int(vpd.port1_data[0]); ++ p->port_type[2] = (u8)hex2int(vpd.port2_data[0]); ++ p->port_type[3] = (u8)hex2int(vpd.port3_data[0]); + p->xauicfg[0] = simple_strtoul(vpd.xaui0cfg_data, NULL, 16); + p->xauicfg[1] = simple_strtoul(vpd.xaui1cfg_data, NULL, 16); + } +@@ -718,23 +828,41 @@ + return 0; + } + ++/* BIOS boot header */ ++typedef struct boot_header_s { ++ u8 signature[2]; /* signature */ ++ u8 length; /* image length (include header) */ ++ u8 offset[4]; /* initialization vector */ ++ u8 reserved[19]; /* reserved */ ++ u8 exheader[2]; /* offset to expansion header */ ++} boot_header_t; ++ + /* serial flash and firmware constants */ + enum { +- SF_ATTEMPTS = 5, /* max retries for SF1 operations */ +- SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ +- SF_SIZE = SF_SEC_SIZE * 8, /* serial flash size */ ++ SF_ATTEMPTS = 5, /* max retries for SF1 operations */ ++ SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ ++ SF_SIZE = SF_SEC_SIZE * 8, /* serial flash size */ + + /* flash command opcodes */ +- SF_PROG_PAGE = 2, /* program page */ +- SF_WR_DISABLE = 4, /* disable writes */ +- SF_RD_STATUS = 5, /* read status register */ +- SF_WR_ENABLE = 6, /* enable writes */ +- SF_RD_DATA_FAST = 0xb, /* read flash */ +- SF_ERASE_SECTOR = 0xd8, /* erase sector */ +- +- FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */ ++ SF_PROG_PAGE = 2, /* program page */ ++ SF_WR_DISABLE = 4, /* disable writes */ ++ SF_RD_STATUS = 5, /* read status register */ ++ SF_WR_ENABLE = 6, /* enable writes */ ++ SF_RD_DATA_FAST = 0xb, /* read flash */ ++ SF_ERASE_SECTOR = 0xd8, /* erase sector */ ++ ++ FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */ + FW_VERS_ADDR = 0x7fffc, /* flash address holding FW version */ +- FW_MIN_SIZE = 8 /* at least version and csum */ ++ FW_VERS_ADDR_PRE8 = 0x77ffc,/* flash address holding FW version pre8 */ ++ FW_MIN_SIZE = 8, /* at least version and csum */ ++ FW_MAX_SIZE = FW_VERS_ADDR - FW_FLASH_BOOT_ADDR, ++ FW_MAX_SIZE_PRE8 = FW_VERS_ADDR_PRE8 - FW_FLASH_BOOT_ADDR, ++ ++ BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ ++ BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ ++ BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ ++ BOOT_MIN_SIZE = sizeof(boot_header_t), /* at least basic header */ ++ BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC /* 1 byte * length increment */ + }; + + /** +@@ -748,7 +876,7 @@ + * the read needs to be specified prior to calling this by issuing the + * appropriate commands to the serial flash. + */ +-static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, ++static int sf1_read(adapter_t *adapter, unsigned int byte_cnt, int cont, + u32 *valp) + { + int ret; +@@ -775,7 +903,7 @@ + * the write needs to be specified prior to calling this by issuing the + * appropriate commands to the serial flash. + */ +-static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, ++static int sf1_write(adapter_t *adapter, unsigned int byte_cnt, int cont, + u32 val) + { + if (!byte_cnt || byte_cnt > 4) +@@ -796,7 +924,7 @@ + * + * Wait for a flash operation to complete by polling the status register. + */ +-static int flash_wait_op(struct adapter *adapter, int attempts, int delay) ++static int flash_wait_op(adapter_t *adapter, int attempts, int delay) + { + int ret; + u32 status; +@@ -827,8 +955,8 @@ + * (i.e., big-endian), otherwise as 32-bit words in the platform's + * natural endianess. + */ +-int t3_read_flash(struct adapter *adapter, unsigned int addr, +- unsigned int nwords, u32 *data, int byte_oriented) ++int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, ++ u32 *data, int byte_oriented) + { + int ret; + +@@ -841,7 +969,7 @@ + (ret = sf1_read(adapter, 1, 1, data)) != 0) + return ret; + +- for (; nwords; nwords--, data++) { ++ for ( ; nwords; nwords--, data++) { + ret = sf1_read(adapter, 4, nwords > 1, data); + if (ret) + return ret; +@@ -857,16 +985,21 @@ + * @addr: the start address to write + * @n: length of data to write + * @data: the data to write ++ * @byte_oriented: whether to store data as bytes or as words + * + * Writes up to a page of data (256 bytes) to the serial flash starting + * at the given address. +- */ +-static int t3_write_flash(struct adapter *adapter, unsigned int addr, +- unsigned int n, const u8 *data) ++ * If @byte_oriented is set the write data is stored as a 32-bit ++ * big-endian array, otherwise in the processor's native endianess. ++ * ++ */ ++static int t3_write_flash(adapter_t *adapter, unsigned int addr, ++ unsigned int n, const u8 *data, ++ int byte_oriented) + { + int ret; + u32 buf[64]; +- unsigned int i, c, left, val, offset = addr & 0xff; ++ unsigned int c, left, val, offset = addr & 0xff; + + if (addr + n > SF_SIZE || offset + n > 256) + return -EINVAL; +@@ -879,8 +1012,10 @@ + + for (left = n; left; left -= c) { + c = min(left, 4U); +- for (val = 0, i = 0; i < c; ++i) +- val = (val << 8) + *data++; ++ val = *(u32*)data; ++ data += c; ++ if (byte_oriented) ++ val = htonl(val); + + ret = sf1_write(adapter, c, c != left, val); + if (ret) +@@ -890,11 +1025,12 @@ + return ret; + + /* Read the page to verify the write succeeded */ +- ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); +- if (ret) +- return ret; +- +- if (memcmp(data - n, (u8 *) buf + offset, n)) ++ ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, ++ byte_oriented); ++ if (ret) ++ return ret; ++ ++ if (memcmp(data - n, (u8 *)buf + offset, n)) + return -EIO; + return 0; + } +@@ -906,7 +1042,7 @@ + * + * Reads the protocol sram version from sram. + */ +-int t3_get_tp_version(struct adapter *adapter, u32 *vers) ++int t3_get_tp_version(adapter_t *adapter, u32 *vers) + { + int ret; + +@@ -925,11 +1061,9 @@ + /** + * t3_check_tpsram_version - read the tp sram version + * @adapter: the adapter +- * @must_load: set to 1 if loading a new microcode image is required +- * +- * Reads the protocol sram version from flash. +- */ +-int t3_check_tpsram_version(struct adapter *adapter, int *must_load) ++ * ++ */ ++int t3_check_tpsram_version(adapter_t *adapter) + { + int ret; + u32 vers; +@@ -938,24 +1072,19 @@ + if (adapter->params.rev == T3_REV_A) + return 0; + +- *must_load = 1; + + ret = t3_get_tp_version(adapter, &vers); + if (ret) + return ret; ++ ++ vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1); + + major = G_TP_VERSION_MAJOR(vers); + minor = G_TP_VERSION_MINOR(vers); + + if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR) + return 0; +- +- if (major != TP_VERSION_MAJOR) +- CH_ERR(adapter, "found wrong TP version (%u.%u), " +- "driver needs version %d.%d\n", major, minor, +- TP_VERSION_MAJOR, TP_VERSION_MINOR); + else { +- *must_load = 0; + CH_ERR(adapter, "found wrong TP version (%u.%u), " + "driver compiled for version %d.%d\n", major, minor, + TP_VERSION_MAJOR, TP_VERSION_MINOR); +@@ -973,12 +1102,11 @@ + * Checks if an adapter's tp sram is compatible with the driver. + * Returns 0 if the versions are compatible, a negative error otherwise. + */ +-int t3_check_tpsram(struct adapter *adapter, const u8 *tp_sram, +- unsigned int size) ++int t3_check_tpsram(adapter_t *adapter, const u8 *tp_sram, unsigned int size) + { + u32 csum; + unsigned int i; +- const __be32 *p = (const __be32 *)tp_sram; ++ const u32 *p = (const u32 *)tp_sram; + + /* Verify checksum */ + for (csum = 0, i = 0; i < size / sizeof(csum); i++) +@@ -1002,28 +1130,32 @@ + * @adapter: the adapter + * @vers: where to place the version + * +- * Reads the FW version from flash. +- */ +-int t3_get_fw_version(struct adapter *adapter, u32 *vers) +-{ +- return t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0); ++ * Reads the FW version from flash. Note that we had to move the version ++ * due to FW size. If we don't find a valid FW version in the new location ++ * we fall back and read the old location. ++ */ ++int t3_get_fw_version(adapter_t *adapter, u32 *vers) ++{ ++ int ret = t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0); ++ if (!ret && *vers != 0xffffffff) ++ return 0; ++ else ++ return t3_read_flash(adapter, 0x77ffc, 1, vers, 0); + } + + /** + * t3_check_fw_version - check if the FW is compatible with this driver + * @adapter: the adapter +- * @must_load: set to 1 if loading a new FW image is required +- ++ * + * Checks if an adapter's FW is compatible with the driver. Returns 0 + * if the versions are compatible, a negative error otherwise. + */ +-int t3_check_fw_version(struct adapter *adapter, int *must_load) ++int t3_check_fw_version(adapter_t *adapter) + { + int ret; + u32 vers; + unsigned int type, major, minor; + +- *must_load = 1; + ret = t3_get_fw_version(adapter, &vers); + if (ret) + return ret; +@@ -1036,16 +1168,11 @@ + minor == FW_VERSION_MINOR) + return 0; + +- if (major != FW_VERSION_MAJOR) +- CH_ERR(adapter, "found wrong FW version(%u.%u), " +- "driver needs version %u.%u\n", major, minor, +- FW_VERSION_MAJOR, FW_VERSION_MINOR); +- else if (minor < FW_VERSION_MINOR) { +- *must_load = 0; ++ else if (major != FW_VERSION_MAJOR || minor < FW_VERSION_MINOR) + CH_WARN(adapter, "found old FW minor version(%u.%u), " + "driver compiled for version %u.%u\n", major, minor, + FW_VERSION_MAJOR, FW_VERSION_MINOR); +- } else { ++ else { + CH_WARN(adapter, "found newer FW version(%u.%u), " + "driver compiled for version %u.%u\n", major, minor, + FW_VERSION_MAJOR, FW_VERSION_MINOR); +@@ -1062,7 +1189,7 @@ + * + * Erases the sectors in the given range. + */ +-static int t3_flash_erase_sectors(struct adapter *adapter, int start, int end) ++static int t3_flash_erase_sectors(adapter_t *adapter, int start, int end) + { + while (start <= end) { + int ret; +@@ -1088,17 +1215,27 @@ + * data, followed by 4 bytes of FW version, followed by the 32-bit + * 1's complement checksum of the whole image. + */ +-int t3_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size) +-{ +- u32 csum; ++int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size) ++{ ++ u32 version, csum, fw_version_addr; + unsigned int i; +- const __be32 *p = (const __be32 *)fw_data; ++ const u32 *p = (const u32 *)fw_data; + int ret, addr, fw_sector = FW_FLASH_BOOT_ADDR >> 16; + + if ((size & 3) || size < FW_MIN_SIZE) + return -EINVAL; +- if (size > FW_VERS_ADDR + 8 - FW_FLASH_BOOT_ADDR) ++ if (size - 8 > FW_MAX_SIZE) + return -EFBIG; ++ ++ version = ntohl(*(u32 *)(fw_data + size - 8)); ++ if (G_FW_VERSION_MAJOR(version) < 8) { ++ ++ fw_version_addr = FW_VERS_ADDR_PRE8; ++ ++ if (size - 8 > FW_MAX_SIZE_PRE8) ++ return -EFBIG; ++ } else ++ fw_version_addr = FW_VERS_ADDR; + + for (csum = 0, i = 0; i < size / sizeof(csum); i++) + csum += ntohl(p[i]); +@@ -1112,11 +1249,11 @@ + if (ret) + goto out; + +- size -= 8; /* trim off version and checksum */ +- for (addr = FW_FLASH_BOOT_ADDR; size;) { ++ size -= 8; /* trim off version and checksum */ ++ for (addr = FW_FLASH_BOOT_ADDR; size; ) { + unsigned int chunk_size = min(size, 256U); + +- ret = t3_write_flash(adapter, addr, chunk_size, fw_data); ++ ret = t3_write_flash(adapter, addr, chunk_size, fw_data, 1); + if (ret) + goto out; + +@@ -1125,27 +1262,84 @@ + size -= chunk_size; + } + +- ret = t3_write_flash(adapter, FW_VERS_ADDR, 4, fw_data); ++ ret = t3_write_flash(adapter, fw_version_addr, 4, fw_data, 1); + out: + if (ret) + CH_ERR(adapter, "firmware download failed, error %d\n", ret); + return ret; + } + ++/* ++ * t3_load_boot - download boot flash ++ * @adapter: the adapter ++ * @boot_data: the boot image to write ++ * @size: image size ++ * ++ * Write the supplied boot image to the card's serial flash. ++ * The boot image has the following sections: a 28-byte header and the ++ * boot image. ++ */ ++int t3_load_boot(adapter_t *adapter, const u8 *boot_data, unsigned int size) ++{ ++ boot_header_t *header = (boot_header_t *)boot_data; ++ int ret; ++ unsigned int addr; ++ unsigned int boot_sector = BOOT_FLASH_BOOT_ADDR >> 16; ++ unsigned int boot_end = (BOOT_FLASH_BOOT_ADDR + size - 1) >> 16; ++ ++ /* ++ * Perform some primitive sanity testing to avoid accidentally ++ * writing garbage over the boot sectors. We ought to check for ++ * more but it's not worth it for now ... ++ */ ++ if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { ++ CH_ERR(adapter, "boot image too small/large\n"); ++ return -EFBIG; ++ } ++ if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE) { ++ CH_ERR(adapter, "boot image missing signature\n"); ++ return -EINVAL; ++ } ++ if (header->length * BOOT_SIZE_INC != size) { ++ CH_ERR(adapter, "boot image header length != image length\n"); ++ return -EINVAL; ++ } ++ ++ ret = t3_flash_erase_sectors(adapter, boot_sector, boot_end); ++ if (ret) ++ goto out; ++ ++ for (addr = BOOT_FLASH_BOOT_ADDR; size; ) { ++ unsigned int chunk_size = min(size, 256U); ++ ++ ret = t3_write_flash(adapter, addr, chunk_size, boot_data, 0); ++ if (ret) ++ goto out; ++ ++ addr += chunk_size; ++ boot_data += chunk_size; ++ size -= chunk_size; ++ } ++ ++out: ++ if (ret) ++ CH_ERR(adapter, "boot image download failed, error %d\n", ret); ++ return ret; ++} ++ + #define CIM_CTL_BASE 0x2000 + + /** +- * t3_cim_ctl_blk_read - read a block from CIM control region +- * +- * @adap: the adapter +- * @addr: the start address within the CIM control region +- * @n: number of words to read +- * @valp: where to store the result +- * +- * Reads a block of 4-byte words from the CIM control region. +- */ +-int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr, +- unsigned int n, unsigned int *valp) ++ * t3_cim_ctl_blk_read - read a block from CIM control region ++ * @adap: the adapter ++ * @addr: the start address within the CIM control region ++ * @n: number of words to read ++ * @valp: where to store the result ++ * ++ * Reads a block of 4-byte words from the CIM control region. ++ */ ++int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n, ++ unsigned int *valp) + { + int ret = 0; + +@@ -1162,6 +1356,38 @@ + return ret; + } + ++static void t3_gate_rx_traffic(struct cmac *mac, u32 *rx_cfg, ++ u32 *rx_hash_high, u32 *rx_hash_low) ++{ ++ /* stop Rx unicast traffic */ ++ t3_mac_disable_exact_filters(mac); ++ ++ /* stop broadcast, multicast, promiscuous mode traffic */ ++ *rx_cfg = t3_read_reg(mac->adapter, A_XGM_RX_CFG); ++ t3_set_reg_field(mac->adapter, A_XGM_RX_CFG, ++ F_ENHASHMCAST | F_DISBCAST | F_COPYALLFRAMES, ++ F_DISBCAST); ++ ++ *rx_hash_high = t3_read_reg(mac->adapter, A_XGM_RX_HASH_HIGH); ++ t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, 0); ++ ++ *rx_hash_low = t3_read_reg(mac->adapter, A_XGM_RX_HASH_LOW); ++ t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, 0); ++ ++ /* Leave time to drain max RX fifo */ ++ msleep(1); ++} ++ ++static void t3_open_rx_traffic(struct cmac *mac, u32 rx_cfg, ++ u32 rx_hash_high, u32 rx_hash_low) ++{ ++ t3_mac_enable_exact_filters(mac); ++ t3_set_reg_field(mac->adapter, A_XGM_RX_CFG, ++ F_ENHASHMCAST | F_DISBCAST | F_COPYALLFRAMES, ++ rx_cfg); ++ t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, rx_hash_high); ++ t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, rx_hash_low); ++} + + /** + * t3_link_changed - handle interface link changes +@@ -1172,7 +1398,7 @@ + * to the associated PHY and MAC. After performing the common tasks it + * invokes an OS-specific handler. + */ +-void t3_link_changed(struct adapter *adapter, int port_id) ++void t3_link_changed(adapter_t *adapter, int port_id) + { + int link_ok, speed, duplex, fc; + struct port_info *pi = adap2pinfo(adapter, port_id); +@@ -1181,6 +1407,28 @@ + struct link_config *lc = &pi->link_config; + + phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc); ++ ++ if (!lc->link_ok && link_ok && adapter->params.nports <= 2) { ++ u32 rx_cfg, rx_hash_high, rx_hash_low; ++ u32 status; ++ ++ t3_xgm_intr_enable(adapter, port_id); ++ t3_gate_rx_traffic(mac, &rx_cfg, &rx_hash_high, &rx_hash_low); ++ t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); ++ t3_mac_enable(mac, MAC_DIRECTION_RX); ++ ++ status = t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset); ++ if (status & F_LINKFAULTCHANGE) { ++ mac->stats.link_faults++; ++ /* ++ * Link fault intrs are enabled only after the phy ++ * reports a link up - no intr enabled here, ++ * it is safe to update the port link fault state ++ */ ++ pi->link_fault = 1; ++ } ++ t3_open_rx_traffic(mac, rx_cfg, rx_hash_high, rx_hash_low); ++ } + + if (lc->requested_fc & PAUSE_AUTONEG) + fc &= lc->requested_fc; +@@ -1198,17 +1446,70 @@ + t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, + link_ok ? F_TXACTENABLE | F_RXEN : 0); + } +- lc->link_ok = link_ok; ++ lc->link_ok = (unsigned char)link_ok; + lc->speed = speed < 0 ? SPEED_INVALID : speed; + lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex; + + if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) { + /* Set MAC speed, duplex, and flow control to match PHY. */ + t3_mac_set_speed_duplex_fc(mac, speed, duplex, fc); +- lc->fc = fc; ++ lc->fc = (unsigned char)fc; + } + + t3_os_link_changed(adapter, port_id, link_ok, speed, duplex, fc); ++} ++ ++void t3_link_fault(adapter_t *adapter, int port_id) ++{ ++ struct port_info *pi = adap2pinfo(adapter, port_id); ++ struct cmac *mac = &pi->mac; ++ struct cphy *phy = &pi->phy; ++ struct link_config *lc = &pi->link_config; ++ int link_ok, speed, duplex, fc, link_fault; ++ u32 rx_cfg, rx_hash_high, rx_hash_low; ++ ++ link_ok = lc->link_ok; ++ speed = lc->speed; ++ duplex = lc->duplex; ++ fc = lc->fc; ++ ++ t3_gate_rx_traffic(mac, &rx_cfg, &rx_hash_high, &rx_hash_low); ++ ++ if (adapter->params.rev > 0 && uses_xaui(adapter)) ++ t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, 0); ++ ++ t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); ++ t3_mac_enable(mac, MAC_DIRECTION_RX); ++ ++ t3_open_rx_traffic(mac, rx_cfg, rx_hash_high, rx_hash_low); ++ ++ link_fault = t3_read_reg(adapter, ++ A_XGM_INT_STATUS + mac->offset); ++ link_fault &= F_LINKFAULTCHANGE; ++ ++ phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc); ++ ++ if (link_fault) { ++ lc->link_ok = 0; ++ lc->speed = SPEED_INVALID; ++ lc->duplex = DUPLEX_INVALID; ++ ++ t3_os_link_fault(adapter, port_id, 0); ++ ++ /* Account link faults only when the phy reports a link up */ ++ if (link_ok) ++ mac->stats.link_faults++; ++ } else { ++ if (link_ok) ++ t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, ++ F_TXACTENABLE | F_RXEN); ++ ++ pi->link_fault = 0; ++ lc->link_ok = (unsigned char)link_ok; ++ lc->speed = speed < 0 ? SPEED_INVALID : speed; ++ lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex; ++ t3_os_link_fault(adapter, port_id, link_ok); ++ } + } + + /** +@@ -1246,6 +1547,9 @@ + fc); + /* Also disables autoneg */ + phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex); ++ /* PR 5666. Power phy up when doing an ifup */ ++ if (!is_10G(phy->adapter)) ++ phy->ops->power_down(phy, 0); + } else + phy->ops->autoneg_enable(phy); + } else { +@@ -1264,7 +1568,7 @@ + * + * Enables or disables HW extraction of VLAN tags for the given port. + */ +-void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on) ++void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on) + { + t3_set_reg_field(adapter, A_TP_OUT_CONFIG, + ports << S_VLANEXTRACTIONENABLE, +@@ -1272,10 +1576,10 @@ + } + + struct intr_info { +- unsigned int mask; /* bits to check in interrupt status */ +- const char *msg; /* message to print or NULL */ +- short stat_idx; /* stat counter to increment or -1 */ +- unsigned short fatal; /* whether the condition reported is fatal */ ++ unsigned int mask; /* bits to check in interrupt status */ ++ const char *msg; /* message to print or NULL */ ++ short stat_idx; /* stat counter to increment or -1 */ ++ unsigned short fatal; /* whether the condition reported is fatal */ + }; + + /** +@@ -1293,7 +1597,7 @@ + * incrementing a stat counter. The table is terminated by an entry + * specifying mask 0. Returns the number of fatal interrupt conditions. + */ +-static int t3_handle_intr_status(struct adapter *adapter, unsigned int reg, ++static int t3_handle_intr_status(adapter_t *adapter, unsigned int reg, + unsigned int mask, + const struct intr_info *acts, + unsigned long *stats) +@@ -1301,9 +1605,8 @@ + int fatal = 0; + unsigned int status = t3_read_reg(adapter, reg) & mask; + +- for (; acts->mask; ++acts) { +- if (!(status & acts->mask)) +- continue; ++ for ( ; acts->mask; ++acts) { ++ if (!(status & acts->mask)) continue; + if (acts->fatal) { + fatal++; + CH_ALERT(adapter, "%s (0x%x)\n", +@@ -1314,7 +1617,7 @@ + if (acts->stat_idx >= 0) + stats[acts->stat_idx]++; + } +- if (status) /* clear processed interrupts */ ++ if (status) /* clear processed interrupts */ + t3_write_reg(adapter, reg, status); + return fatal; + } +@@ -1332,7 +1635,7 @@ + #define MC7_INTR_MASK (F_AE | F_UE | F_CE | V_PE(M_PE)) + #define XGM_INTR_MASK (V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR) | \ + V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR) | \ +- F_TXFIFO_UNDERRUN | F_RXFIFO_OVERFLOW) ++ F_TXFIFO_UNDERRUN) + #define PCIX_INTR_MASK (F_MSTDETPARERR | F_SIGTARABT | F_RCVTARABT | \ + F_RCVMSTABT | F_SIGSYSERR | F_DETPARERR | \ + F_SPLCMPDIS | F_UNXSPLCMP | F_RCVSPLCMPERR | \ +@@ -1369,40 +1672,40 @@ + V_TX1TPPARERRENB(M_TX1TPPARERRENB) | \ + V_RXTPPARERRENB(M_RXTPPARERRENB) | \ + V_MCAPARERRENB(M_MCAPARERRENB)) ++#define XGM_EXTRA_INTR_MASK (F_LINKFAULTCHANGE) + #define PL_INTR_MASK (F_T3DBG | F_XGMAC0_0 | F_XGMAC0_1 | F_MC5A | F_PM1_TX | \ + F_PM1_RX | F_ULP2_TX | F_ULP2_RX | F_TP1 | F_CIM | \ + F_MC7_CM | F_MC7_PMTX | F_MC7_PMRX | F_SGE3 | F_PCIM0 | \ + F_MPS0 | F_CPL_SWITCH) +- + /* + * Interrupt handler for the PCIX1 module. + */ +-static void pci_intr_handler(struct adapter *adapter) +-{ +- static const struct intr_info pcix1_intr_info[] = { +- {F_MSTDETPARERR, "PCI master detected parity error", -1, 1}, +- {F_SIGTARABT, "PCI signaled target abort", -1, 1}, +- {F_RCVTARABT, "PCI received target abort", -1, 1}, +- {F_RCVMSTABT, "PCI received master abort", -1, 1}, +- {F_SIGSYSERR, "PCI signaled system error", -1, 1}, +- {F_DETPARERR, "PCI detected parity error", -1, 1}, +- {F_SPLCMPDIS, "PCI split completion discarded", -1, 1}, +- {F_UNXSPLCMP, "PCI unexpected split completion error", -1, 1}, +- {F_RCVSPLCMPERR, "PCI received split completion error", -1, +- 1}, +- {F_DETCORECCERR, "PCI correctable ECC error", +- STAT_PCI_CORR_ECC, 0}, +- {F_DETUNCECCERR, "PCI uncorrectable ECC error", -1, 1}, +- {F_PIOPARERR, "PCI PIO FIFO parity error", -1, 1}, +- {V_WFPARERR(M_WFPARERR), "PCI write FIFO parity error", -1, +- 1}, +- {V_RFPARERR(M_RFPARERR), "PCI read FIFO parity error", -1, +- 1}, +- {V_CFPARERR(M_CFPARERR), "PCI command FIFO parity error", -1, +- 1}, +- {V_MSIXPARERR(M_MSIXPARERR), "PCI MSI-X table/PBA parity " +- "error", -1, 1}, +- {0} ++static void pci_intr_handler(adapter_t *adapter) ++{ ++ static struct intr_info pcix1_intr_info[] = { ++ { F_MSTDETPARERR, "PCI master detected parity error", -1, 1 }, ++ { F_SIGTARABT, "PCI signaled target abort", -1, 1 }, ++ { F_RCVTARABT, "PCI received target abort", -1, 1 }, ++ { F_RCVMSTABT, "PCI received master abort", -1, 1 }, ++ { F_SIGSYSERR, "PCI signaled system error", -1, 1 }, ++ { F_DETPARERR, "PCI detected parity error", -1, 1 }, ++ { F_SPLCMPDIS, "PCI split completion discarded", -1, 1 }, ++ { F_UNXSPLCMP, "PCI unexpected split completion error", -1, 1 }, ++ { F_RCVSPLCMPERR, "PCI received split completion error", -1, ++ 1 }, ++ { F_DETCORECCERR, "PCI correctable ECC error", ++ STAT_PCI_CORR_ECC, 0 }, ++ { F_DETUNCECCERR, "PCI uncorrectable ECC error", -1, 1 }, ++ { F_PIOPARERR, "PCI PIO FIFO parity error", -1, 1 }, ++ { V_WFPARERR(M_WFPARERR), "PCI write FIFO parity error", -1, ++ 1 }, ++ { V_RFPARERR(M_RFPARERR), "PCI read FIFO parity error", -1, ++ 1 }, ++ { V_CFPARERR(M_CFPARERR), "PCI command FIFO parity error", -1, ++ 1 }, ++ { V_MSIXPARERR(M_MSIXPARERR), "PCI MSI-X table/PBA parity " ++ "error", -1, 1 }, ++ { 0 } + }; + + if (t3_handle_intr_status(adapter, A_PCIX_INT_CAUSE, PCIX_INTR_MASK, +@@ -1413,26 +1716,26 @@ + /* + * Interrupt handler for the PCIE module. + */ +-static void pcie_intr_handler(struct adapter *adapter) +-{ +- static const struct intr_info pcie_intr_info[] = { +- {F_PEXERR, "PCI PEX error", -1, 1}, +- {F_UNXSPLCPLERRR, +- "PCI unexpected split completion DMA read error", -1, 1}, +- {F_UNXSPLCPLERRC, +- "PCI unexpected split completion DMA command error", -1, 1}, +- {F_PCIE_PIOPARERR, "PCI PIO FIFO parity error", -1, 1}, +- {F_PCIE_WFPARERR, "PCI write FIFO parity error", -1, 1}, +- {F_PCIE_RFPARERR, "PCI read FIFO parity error", -1, 1}, +- {F_PCIE_CFPARERR, "PCI command FIFO parity error", -1, 1}, +- {V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR), +- "PCI MSI-X table/PBA parity error", -1, 1}, +- {F_RETRYBUFPARERR, "PCI retry buffer parity error", -1, 1}, +- {F_RETRYLUTPARERR, "PCI retry LUT parity error", -1, 1}, +- {F_RXPARERR, "PCI Rx parity error", -1, 1}, +- {F_TXPARERR, "PCI Tx parity error", -1, 1}, +- {V_BISTERR(M_BISTERR), "PCI BIST error", -1, 1}, +- {0} ++static void pcie_intr_handler(adapter_t *adapter) ++{ ++ static struct intr_info pcie_intr_info[] = { ++ { F_PEXERR, "PCI PEX error", -1, 1 }, ++ { F_UNXSPLCPLERRR, ++ "PCI unexpected split completion DMA read error", -1, 1 }, ++ { F_UNXSPLCPLERRC, ++ "PCI unexpected split completion DMA command error", -1, 1 }, ++ { F_PCIE_PIOPARERR, "PCI PIO FIFO parity error", -1, 1 }, ++ { F_PCIE_WFPARERR, "PCI write FIFO parity error", -1, 1 }, ++ { F_PCIE_RFPARERR, "PCI read FIFO parity error", -1, 1 }, ++ { F_PCIE_CFPARERR, "PCI command FIFO parity error", -1, 1 }, ++ { V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR), ++ "PCI MSI-X table/PBA parity error", -1, 1 }, ++ { F_RETRYBUFPARERR, "PCI retry buffer parity error", -1, 1 }, ++ { F_RETRYLUTPARERR, "PCI retry LUT parity error", -1, 1 }, ++ { F_RXPARERR, "PCI Rx parity error", -1, 1 }, ++ { F_TXPARERR, "PCI Tx parity error", -1, 1 }, ++ { V_BISTERR(M_BISTERR), "PCI BIST error", -1, 1 }, ++ { 0 } + }; + + if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR) +@@ -1447,62 +1750,61 @@ + /* + * TP interrupt handler. + */ +-static void tp_intr_handler(struct adapter *adapter) +-{ +- static const struct intr_info tp_intr_info[] = { +- {0xffffff, "TP parity error", -1, 1}, +- {0x1000000, "TP out of Rx pages", -1, 1}, +- {0x2000000, "TP out of Tx pages", -1, 1}, +- {0} +- }; +- ++static void tp_intr_handler(adapter_t *adapter) ++{ ++ static struct intr_info tp_intr_info[] = { ++ { 0xffffff, "TP parity error", -1, 1 }, ++ { 0x1000000, "TP out of Rx pages", -1, 1 }, ++ { 0x2000000, "TP out of Tx pages", -1, 1 }, ++ { 0 } ++ }; + static struct intr_info tp_intr_info_t3c[] = { +- {0x1fffffff, "TP parity error", -1, 1}, +- {F_FLMRXFLSTEMPTY, "TP out of Rx pages", -1, 1}, +- {F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1}, +- {0} ++ { 0x1fffffff, "TP parity error", -1, 1 }, ++ { F_FLMRXFLSTEMPTY, "TP out of Rx pages", -1, 1 }, ++ { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, ++ { 0 } + }; + + if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff, + adapter->params.rev < T3_REV_C ? +- tp_intr_info : tp_intr_info_t3c, NULL)) ++ tp_intr_info : tp_intr_info_t3c, NULL)) + t3_fatal_err(adapter); + } + + /* + * CIM interrupt handler. + */ +-static void cim_intr_handler(struct adapter *adapter) +-{ +- static const struct intr_info cim_intr_info[] = { +- {F_RSVDSPACEINT, "CIM reserved space write", -1, 1}, +- {F_SDRAMRANGEINT, "CIM SDRAM address out of range", -1, 1}, +- {F_FLASHRANGEINT, "CIM flash address out of range", -1, 1}, +- {F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1}, +- {F_WRBLKFLASHINT, "CIM write to cached flash space", -1, 1}, +- {F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1}, +- {F_BLKRDFLASHINT, "CIM block read from flash space", -1, 1}, +- {F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1}, +- {F_BLKRDCTLINT, "CIM block read from CTL space", -1, 1}, +- {F_BLKWRCTLINT, "CIM block write to CTL space", -1, 1}, +- {F_BLKRDPLINT, "CIM block read from PL space", -1, 1}, +- {F_BLKWRPLINT, "CIM block write to PL space", -1, 1}, +- {F_DRAMPARERR, "CIM DRAM parity error", -1, 1}, +- {F_ICACHEPARERR, "CIM icache parity error", -1, 1}, +- {F_DCACHEPARERR, "CIM dcache parity error", -1, 1}, +- {F_OBQSGEPARERR, "CIM OBQ SGE parity error", -1, 1}, +- {F_OBQULPHIPARERR, "CIM OBQ ULPHI parity error", -1, 1}, +- {F_OBQULPLOPARERR, "CIM OBQ ULPLO parity error", -1, 1}, +- {F_IBQSGELOPARERR, "CIM IBQ SGELO parity error", -1, 1}, +- {F_IBQSGEHIPARERR, "CIM IBQ SGEHI parity error", -1, 1}, +- {F_IBQULPPARERR, "CIM IBQ ULP parity error", -1, 1}, +- {F_IBQTPPARERR, "CIM IBQ TP parity error", -1, 1}, +- {F_ITAGPARERR, "CIM itag parity error", -1, 1}, +- {F_DTAGPARERR, "CIM dtag parity error", -1, 1}, +- {0} +- }; +- +- if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 0xffffffff, ++static void cim_intr_handler(adapter_t *adapter) ++{ ++ static struct intr_info cim_intr_info[] = { ++ { F_RSVDSPACEINT, "CIM reserved space write", -1, 1 }, ++ { F_SDRAMRANGEINT, "CIM SDRAM address out of range", -1, 1 }, ++ { F_FLASHRANGEINT, "CIM flash address out of range", -1, 1 }, ++ { F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 }, ++ { F_WRBLKFLASHINT, "CIM write to cached flash space", -1, 1 }, ++ { F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 }, ++ { F_BLKRDFLASHINT, "CIM block read from flash space", -1, 1 }, ++ { F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 }, ++ { F_BLKRDCTLINT, "CIM block read from CTL space", -1, 1 }, ++ { F_BLKWRCTLINT, "CIM block write to CTL space", -1, 1 }, ++ { F_BLKRDPLINT, "CIM block read from PL space", -1, 1 }, ++ { F_BLKWRPLINT, "CIM block write to PL space", -1, 1 }, ++ { F_DRAMPARERR, "CIM DRAM parity error", -1, 1 }, ++ { F_ICACHEPARERR, "CIM icache parity error", -1, 1 }, ++ { F_DCACHEPARERR, "CIM dcache parity error", -1, 1 }, ++ { F_OBQSGEPARERR, "CIM OBQ SGE parity error", -1, 1 }, ++ { F_OBQULPHIPARERR, "CIM OBQ ULPHI parity error", -1, 1 }, ++ { F_OBQULPLOPARERR, "CIM OBQ ULPLO parity error", -1, 1 }, ++ { F_IBQSGELOPARERR, "CIM IBQ SGELO parity error", -1, 1 }, ++ { F_IBQSGEHIPARERR, "CIM IBQ SGEHI parity error", -1, 1 }, ++ { F_IBQULPPARERR, "CIM IBQ ULP parity error", -1, 1 }, ++ { F_IBQTPPARERR, "CIM IBQ TP parity error", -1, 1 }, ++ { F_ITAGPARERR, "CIM itag parity error", -1, 1 }, ++ { F_DTAGPARERR, "CIM dtag parity error", -1, 1 }, ++ { 0 } ++ }; ++ ++ if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, CIM_INTR_MASK, + cim_intr_info, NULL)) + t3_fatal_err(adapter); + } +@@ -1510,19 +1812,19 @@ + /* + * ULP RX interrupt handler. + */ +-static void ulprx_intr_handler(struct adapter *adapter) +-{ +- static const struct intr_info ulprx_intr_info[] = { +- {F_PARERRDATA, "ULP RX data parity error", -1, 1}, +- {F_PARERRPCMD, "ULP RX command parity error", -1, 1}, +- {F_ARBPF1PERR, "ULP RX ArbPF1 parity error", -1, 1}, +- {F_ARBPF0PERR, "ULP RX ArbPF0 parity error", -1, 1}, +- {F_ARBFPERR, "ULP RX ArbF parity error", -1, 1}, +- {F_PCMDMUXPERR, "ULP RX PCMDMUX parity error", -1, 1}, +- {F_DATASELFRAMEERR1, "ULP RX frame error", -1, 1}, +- {F_DATASELFRAMEERR0, "ULP RX frame error", -1, 1}, +- {0} +- }; ++static void ulprx_intr_handler(adapter_t *adapter) ++{ ++ static struct intr_info ulprx_intr_info[] = { ++ { F_PARERRDATA, "ULP RX data parity error", -1, 1 }, ++ { F_PARERRPCMD, "ULP RX command parity error", -1, 1 }, ++ { F_ARBPF1PERR, "ULP RX ArbPF1 parity error", -1, 1 }, ++ { F_ARBPF0PERR, "ULP RX ArbPF0 parity error", -1, 1 }, ++ { F_ARBFPERR, "ULP RX ArbF parity error", -1, 1 }, ++ { F_PCMDMUXPERR, "ULP RX PCMDMUX parity error", -1, 1 }, ++ { F_DATASELFRAMEERR1, "ULP RX frame error", -1, 1 }, ++ { F_DATASELFRAMEERR0, "ULP RX frame error", -1, 1 }, ++ { 0 } ++ }; + + if (t3_handle_intr_status(adapter, A_ULPRX_INT_CAUSE, 0xffffffff, + ulprx_intr_info, NULL)) +@@ -1532,16 +1834,16 @@ + /* + * ULP TX interrupt handler. + */ +-static void ulptx_intr_handler(struct adapter *adapter) +-{ +- static const struct intr_info ulptx_intr_info[] = { +- {F_PBL_BOUND_ERR_CH0, "ULP TX channel 0 PBL out of bounds", +- STAT_ULP_CH0_PBL_OOB, 0}, +- {F_PBL_BOUND_ERR_CH1, "ULP TX channel 1 PBL out of bounds", +- STAT_ULP_CH1_PBL_OOB, 0}, +- {0xfc, "ULP TX parity error", -1, 1}, +- {0} +- }; ++static void ulptx_intr_handler(adapter_t *adapter) ++{ ++ static struct intr_info ulptx_intr_info[] = { ++ { F_PBL_BOUND_ERR_CH0, "ULP TX channel 0 PBL out of bounds", ++ STAT_ULP_CH0_PBL_OOB, 0 }, ++ { F_PBL_BOUND_ERR_CH1, "ULP TX channel 1 PBL out of bounds", ++ STAT_ULP_CH1_PBL_OOB, 0 }, ++ { 0xfc, "ULP TX parity error", -1, 1 }, ++ { 0 } ++ }; + + if (t3_handle_intr_status(adapter, A_ULPTX_INT_CAUSE, 0xffffffff, + ulptx_intr_info, adapter->irq_stats)) +@@ -1560,18 +1862,18 @@ + /* + * PM TX interrupt handler. + */ +-static void pmtx_intr_handler(struct adapter *adapter) +-{ +- static const struct intr_info pmtx_intr_info[] = { +- {F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1}, +- {ICSPI_FRM_ERR, "PMTX ispi framing error", -1, 1}, +- {OESPI_FRM_ERR, "PMTX ospi framing error", -1, 1}, +- {V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR), +- "PMTX ispi parity error", -1, 1}, +- {V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR), +- "PMTX ospi parity error", -1, 1}, +- {0} +- }; ++static void pmtx_intr_handler(adapter_t *adapter) ++{ ++ static struct intr_info pmtx_intr_info[] = { ++ { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, ++ { ICSPI_FRM_ERR, "PMTX ispi framing error", -1, 1 }, ++ { OESPI_FRM_ERR, "PMTX ospi framing error", -1, 1 }, ++ { V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR), ++ "PMTX ispi parity error", -1, 1 }, ++ { V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR), ++ "PMTX ospi parity error", -1, 1 }, ++ { 0 } ++ }; + + if (t3_handle_intr_status(adapter, A_PM1_TX_INT_CAUSE, 0xffffffff, + pmtx_intr_info, NULL)) +@@ -1590,18 +1892,18 @@ + /* + * PM RX interrupt handler. + */ +-static void pmrx_intr_handler(struct adapter *adapter) +-{ +- static const struct intr_info pmrx_intr_info[] = { +- {F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1}, +- {IESPI_FRM_ERR, "PMRX ispi framing error", -1, 1}, +- {OCSPI_FRM_ERR, "PMRX ospi framing error", -1, 1}, +- {V_IESPI_PAR_ERROR(M_IESPI_PAR_ERROR), +- "PMRX ispi parity error", -1, 1}, +- {V_OCSPI_PAR_ERROR(M_OCSPI_PAR_ERROR), +- "PMRX ospi parity error", -1, 1}, +- {0} +- }; ++static void pmrx_intr_handler(adapter_t *adapter) ++{ ++ static struct intr_info pmrx_intr_info[] = { ++ { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, ++ { IESPI_FRM_ERR, "PMRX ispi framing error", -1, 1 }, ++ { OCSPI_FRM_ERR, "PMRX ospi framing error", -1, 1 }, ++ { V_IESPI_PAR_ERROR(M_IESPI_PAR_ERROR), ++ "PMRX ispi parity error", -1, 1 }, ++ { V_OCSPI_PAR_ERROR(M_OCSPI_PAR_ERROR), ++ "PMRX ospi parity error", -1, 1 }, ++ { 0 } ++ }; + + if (t3_handle_intr_status(adapter, A_PM1_RX_INT_CAUSE, 0xffffffff, + pmrx_intr_info, NULL)) +@@ -1611,17 +1913,17 @@ + /* + * CPL switch interrupt handler. + */ +-static void cplsw_intr_handler(struct adapter *adapter) +-{ +- static const struct intr_info cplsw_intr_info[] = { +- {F_CIM_OP_MAP_PERR, "CPL switch CIM parity error", -1, 1}, +- {F_CIM_OVFL_ERROR, "CPL switch CIM overflow", -1, 1}, +- {F_TP_FRAMING_ERROR, "CPL switch TP framing error", -1, 1}, +- {F_SGE_FRAMING_ERROR, "CPL switch SGE framing error", -1, 1}, +- {F_CIM_FRAMING_ERROR, "CPL switch CIM framing error", -1, 1}, +- {F_ZERO_SWITCH_ERROR, "CPL switch no-switch error", -1, 1}, +- {0} +- }; ++static void cplsw_intr_handler(adapter_t *adapter) ++{ ++ static struct intr_info cplsw_intr_info[] = { ++ { F_CIM_OP_MAP_PERR, "CPL switch CIM parity error", -1, 1 }, ++ { F_CIM_OVFL_ERROR, "CPL switch CIM overflow", -1, 1 }, ++ { F_TP_FRAMING_ERROR, "CPL switch TP framing error", -1, 1 }, ++ { F_SGE_FRAMING_ERROR, "CPL switch SGE framing error", -1, 1 }, ++ { F_CIM_FRAMING_ERROR, "CPL switch CIM framing error", -1, 1 }, ++ { F_ZERO_SWITCH_ERROR, "CPL switch no-switch error", -1, 1 }, ++ { 0 } ++ }; + + if (t3_handle_intr_status(adapter, A_CPL_INTR_CAUSE, 0xffffffff, + cplsw_intr_info, NULL)) +@@ -1631,11 +1933,11 @@ + /* + * MPS interrupt handler. + */ +-static void mps_intr_handler(struct adapter *adapter) +-{ +- static const struct intr_info mps_intr_info[] = { +- {0x1ff, "MPS parity error", -1, 1}, +- {0} ++static void mps_intr_handler(adapter_t *adapter) ++{ ++ static struct intr_info mps_intr_info[] = { ++ { 0x1ff, "MPS parity error", -1, 1 }, ++ { 0 } + }; + + if (t3_handle_intr_status(adapter, A_MPS_INT_CAUSE, 0xffffffff, +@@ -1650,7 +1952,7 @@ + */ + static void mc7_intr_handler(struct mc7 *mc7) + { +- struct adapter *adapter = mc7->adapter; ++ adapter_t *adapter = mc7->adapter; + u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE); + + if (cause & F_CE) { +@@ -1701,10 +2003,22 @@ + /* + * XGMAC interrupt handler. + */ +-static int mac_intr_handler(struct adapter *adap, unsigned int idx) +-{ +- struct cmac *mac = &adap2pinfo(adap, idx)->mac; +- u32 cause = t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset); ++static int mac_intr_handler(adapter_t *adap, unsigned int idx) ++{ ++ u32 cause; ++ struct cmac *mac; ++ ++ idx = idx == 0 ? 0 : adapter_info(adap)->nports0; /* MAC idx -> port */ ++ mac = &adap2pinfo(adap, idx)->mac; ++ ++ /* ++ * We mask out interrupt causes for which we're not taking interrupts. ++ * This allows us to use polling logic to monitor some of the other ++ * conditions when taking interrupts would impose too much load on the ++ * system. ++ */ ++ cause = (t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset) ++ & ~(F_RXFIFO_OVERFLOW)); + + if (cause & V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR)) { + mac->stats.tx_fifo_parity_err++; +@@ -1724,17 +2038,28 @@ + mac->stats.xaui_pcs_ctc_err++; + if (cause & F_XAUIPCSALIGNCHANGE) + mac->stats.xaui_pcs_align_change++; ++ if (cause & F_XGM_INT) { ++ t3_set_reg_field(adap, ++ A_XGM_INT_ENABLE + mac->offset, ++ F_XGM_INT, 0); ++ mac->stats.link_faults++; ++ ++ t3_os_link_fault_handler(adap, idx); ++ } + + t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause); ++ + if (cause & XGM_INTR_FATAL) + t3_fatal_err(adap); ++ ++ + return cause != 0; + } + + /* + * Interrupt handler for PHY events. + */ +-int t3_phy_intr_handler(struct adapter *adapter) ++int t3_phy_intr_handler(adapter_t *adapter) + { + u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE); + +@@ -1760,10 +2085,15 @@ + return 0; + } + +-/* +- * T3 slow path (non-data) interrupt handler. +- */ +-int t3_slow_intr_handler(struct adapter *adapter) ++/** ++ * t3_slow_intr_handler - control path interrupt handler ++ * @adapter: the adapter ++ * ++ * T3 interrupt handler for non-data interrupt events, e.g., errors. ++ * The designation 'slow' is because it involves register reads, while ++ * data interrupts typically don't involve any MMIOs. ++ */ ++int t3_slow_intr_handler(adapter_t *adapter) + { + u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0); + +@@ -1811,11 +2141,11 @@ + + /* Clear the interrupts just processed. */ + t3_write_reg(adapter, A_PL_INT_CAUSE0, cause); +- t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ ++ (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ + return 1; + } + +-static unsigned int calc_gpio_intr(struct adapter *adap) ++static unsigned int calc_gpio_intr(adapter_t *adap) + { + unsigned int i, gpi_intr = 0; + +@@ -1834,21 +2164,20 @@ + * various HW modules and then enabling the top-level interrupt + * concentrator. + */ +-void t3_intr_enable(struct adapter *adapter) +-{ +- static const struct addr_val_pair intr_en_avp[] = { +- {A_SG_INT_ENABLE, SGE_INTR_MASK}, +- {A_MC7_INT_ENABLE, MC7_INTR_MASK}, +- {A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR, +- MC7_INTR_MASK}, +- {A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR, +- MC7_INTR_MASK}, +- {A_MC5_DB_INT_ENABLE, MC5_INTR_MASK}, +- {A_ULPRX_INT_ENABLE, ULPRX_INTR_MASK}, +- {A_PM1_TX_INT_ENABLE, PMTX_INTR_MASK}, +- {A_PM1_RX_INT_ENABLE, PMRX_INTR_MASK}, +- {A_CIM_HOST_INT_ENABLE, CIM_INTR_MASK}, +- {A_MPS_INT_ENABLE, MPS_INTR_MASK}, ++void t3_intr_enable(adapter_t *adapter) ++{ ++ static struct addr_val_pair intr_en_avp[] = { ++ { A_MC7_INT_ENABLE, MC7_INTR_MASK }, ++ { A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR, ++ MC7_INTR_MASK }, ++ { A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR, ++ MC7_INTR_MASK }, ++ { A_MC5_DB_INT_ENABLE, MC5_INTR_MASK }, ++ { A_ULPRX_INT_ENABLE, ULPRX_INTR_MASK }, ++ { A_PM1_TX_INT_ENABLE, PMTX_INTR_MASK }, ++ { A_PM1_RX_INT_ENABLE, PMRX_INTR_MASK }, ++ { A_CIM_HOST_INT_ENABLE, CIM_INTR_MASK }, ++ { A_MPS_INT_ENABLE, MPS_INTR_MASK }, + }; + + adapter->slow_intr_mask = PL_INTR_MASK; +@@ -1856,6 +2185,7 @@ + t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0); + t3_write_reg(adapter, A_TP_INT_ENABLE, + adapter->params.rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff); ++ t3_write_reg(adapter, A_SG_INT_ENABLE, SGE_INTR_MASK); + + if (adapter->params.rev > 0) { + t3_write_reg(adapter, A_CPL_INTR_ENABLE, +@@ -1875,7 +2205,7 @@ + else + t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK); + t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask); +- t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */ ++ (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */ + } + + /** +@@ -1885,10 +2215,10 @@ + * Disable interrupts. We only disable the top-level interrupt + * concentrator and the SGE data interrupts. + */ +-void t3_intr_disable(struct adapter *adapter) ++void t3_intr_disable(adapter_t *adapter) + { + t3_write_reg(adapter, A_PL_INT_ENABLE0, 0); +- t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */ ++ (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */ + adapter->slow_intr_mask = 0; + } + +@@ -1898,7 +2228,7 @@ + * + * Clears all interrupts. + */ +-void t3_intr_clear(struct adapter *adapter) ++void t3_intr_clear(adapter_t *adapter) + { + static const unsigned int cause_reg_addr[] = { + A_SG_INT_CAUSE, +@@ -1922,7 +2252,7 @@ + + /* Clear PHY and MAC interrupts for each port. */ + for_each_port(adapter, i) +- t3_port_intr_clear(adapter, i); ++ t3_port_intr_clear(adapter, i); + + for (i = 0; i < ARRAY_SIZE(cause_reg_addr); ++i) + t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff); +@@ -1930,7 +2260,23 @@ + if (is_pcie(adapter)) + t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff); + t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff); +- t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ ++ (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ ++} ++ ++void t3_xgm_intr_enable(adapter_t *adapter, int idx) ++{ ++ struct port_info *pi = adap2pinfo(adapter, idx); ++ ++ t3_write_reg(adapter, A_XGM_XGM_INT_ENABLE + pi->mac.offset, ++ XGM_EXTRA_INTR_MASK); ++} ++ ++void t3_xgm_intr_disable(adapter_t *adapter, int idx) ++{ ++ struct port_info *pi = adap2pinfo(adapter, idx); ++ ++ t3_write_reg(adapter, A_XGM_XGM_INT_DISABLE + pi->mac.offset, ++ 0x7ff); + } + + /** +@@ -1941,13 +2287,12 @@ + * Enable port-specific (i.e., MAC and PHY) interrupts for the given + * adapter port. + */ +-void t3_port_intr_enable(struct adapter *adapter, int idx) +-{ +- struct cphy *phy = &adap2pinfo(adapter, idx)->phy; +- +- t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), XGM_INTR_MASK); +- t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */ +- phy->ops->intr_enable(phy); ++void t3_port_intr_enable(adapter_t *adapter, int idx) ++{ ++ struct port_info *pi = adap2pinfo(adapter, idx); ++ ++ t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, XGM_INTR_MASK); ++ pi->phy.ops->intr_enable(&pi->phy); + } + + /** +@@ -1958,13 +2303,12 @@ + * Disable port-specific (i.e., MAC and PHY) interrupts for the given + * adapter port. + */ +-void t3_port_intr_disable(struct adapter *adapter, int idx) +-{ +- struct cphy *phy = &adap2pinfo(adapter, idx)->phy; +- +- t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), 0); +- t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */ +- phy->ops->intr_disable(phy); ++void t3_port_intr_disable(adapter_t *adapter, int idx) ++{ ++ struct port_info *pi = adap2pinfo(adapter, idx); ++ ++ t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, 0); ++ pi->phy.ops->intr_disable(&pi->phy); + } + + /** +@@ -1975,13 +2319,12 @@ + * Clear port-specific (i.e., MAC and PHY) interrupts for the given + * adapter port. + */ +-void t3_port_intr_clear(struct adapter *adapter, int idx) +-{ +- struct cphy *phy = &adap2pinfo(adapter, idx)->phy; +- +- t3_write_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx), 0xffffffff); +- t3_read_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx)); /* flush */ +- phy->ops->intr_clear(phy); ++void t3_port_intr_clear(adapter_t *adapter, int idx) ++{ ++ struct port_info *pi = adap2pinfo(adapter, idx); ++ ++ t3_write_reg(adapter, A_XGM_INT_CAUSE + pi->mac.offset, 0xffffffff); ++ pi->phy.ops->intr_clear(&pi->phy); + } + + #define SG_CONTEXT_CMD_ATTEMPTS 100 +@@ -1995,27 +2338,57 @@ + * Program an SGE context with the values already loaded in the + * CONTEXT_DATA? registers. + */ +-static int t3_sge_write_context(struct adapter *adapter, unsigned int id, ++static int t3_sge_write_context(adapter_t *adapter, unsigned int id, + unsigned int type) + { +- t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff); +- t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff); +- t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff); +- t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff); ++ if (type == F_RESPONSEQ) { ++ /* ++ * Can't write the Response Queue Context bits for ++ * Interrupt Armed or the Reserve bits after the chip ++ * has been initialized out of reset. Writing to these ++ * bits can confuse the hardware. ++ */ ++ t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff); ++ t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff); ++ t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0x17ffffff); ++ t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff); ++ } else { ++ t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff); ++ t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff); ++ t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff); ++ t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff); ++ } + t3_write_reg(adapter, A_SG_CONTEXT_CMD, + V_CONTEXT_CMD_OPCODE(1) | type | V_CONTEXT(id)); + return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, + 0, SG_CONTEXT_CMD_ATTEMPTS, 1); + } + +-static int clear_sge_ctxt(struct adapter *adap, unsigned int id, +- unsigned int type) ++/** ++ * clear_sge_ctxt - completely clear an SGE context ++ * @adapter: the adapter ++ * @id: the context id ++ * @type: the context type ++ * ++ * Completely clear an SGE context. Used predominantly at post-reset ++ * initialization. Note in particular that we don't skip writing to any ++ * "sensitive bits" in the contexts the way that t3_sge_write_context() ++ * does ... ++ */ ++static int clear_sge_ctxt(adapter_t *adap, unsigned int id, unsigned int type) + { + t3_write_reg(adap, A_SG_CONTEXT_DATA0, 0); + t3_write_reg(adap, A_SG_CONTEXT_DATA1, 0); + t3_write_reg(adap, A_SG_CONTEXT_DATA2, 0); + t3_write_reg(adap, A_SG_CONTEXT_DATA3, 0); +- return t3_sge_write_context(adap, id, type); ++ t3_write_reg(adap, A_SG_CONTEXT_MASK0, 0xffffffff); ++ t3_write_reg(adap, A_SG_CONTEXT_MASK1, 0xffffffff); ++ t3_write_reg(adap, A_SG_CONTEXT_MASK2, 0xffffffff); ++ t3_write_reg(adap, A_SG_CONTEXT_MASK3, 0xffffffff); ++ t3_write_reg(adap, A_SG_CONTEXT_CMD, ++ V_CONTEXT_CMD_OPCODE(1) | type | V_CONTEXT(id)); ++ return t3_wait_op_done(adap, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, ++ 0, SG_CONTEXT_CMD_ATTEMPTS, 1); + } + + /** +@@ -2035,14 +2408,14 @@ + * platform allows concurrent context operations, the caller is + * responsible for appropriate locking. + */ +-int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable, ++int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, + enum sge_context_type type, int respq, u64 base_addr, + unsigned int size, unsigned int token, int gen, + unsigned int cidx) + { + unsigned int credits = type == SGE_CNTXT_OFLD ? 0 : FW_WR_NUM; + +- if (base_addr & 0xfff) /* must be 4K aligned */ ++ if (base_addr & 0xfff) /* must be 4K aligned */ + return -EINVAL; + if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) + return -EBUSY; +@@ -2051,12 +2424,12 @@ + t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) | + V_EC_CREDITS(credits) | V_EC_GTS(gts_enable)); + t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) | +- V_EC_BASE_LO(base_addr & 0xffff)); ++ V_EC_BASE_LO((u32)base_addr & 0xffff)); + base_addr >>= 16; +- t3_write_reg(adapter, A_SG_CONTEXT_DATA2, base_addr); ++ t3_write_reg(adapter, A_SG_CONTEXT_DATA2, (u32)base_addr); + base_addr >>= 32; + t3_write_reg(adapter, A_SG_CONTEXT_DATA3, +- V_EC_BASE_HI(base_addr & 0xf) | V_EC_RESPQ(respq) | ++ V_EC_BASE_HI((u32)base_addr & 0xf) | V_EC_RESPQ(respq) | + V_EC_TYPE(type) | V_EC_GEN(gen) | V_EC_UP_TOKEN(token) | + F_EC_VALID); + return t3_sge_write_context(adapter, id, F_EGRESS); +@@ -2078,21 +2451,20 @@ + * caller is responsible for ensuring only one context operation occurs + * at a time. + */ +-int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id, +- int gts_enable, u64 base_addr, unsigned int size, +- unsigned int bsize, unsigned int cong_thres, int gen, +- unsigned int cidx) +-{ +- if (base_addr & 0xfff) /* must be 4K aligned */ ++int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, ++ u64 base_addr, unsigned int size, unsigned int bsize, ++ unsigned int cong_thres, int gen, unsigned int cidx) ++{ ++ if (base_addr & 0xfff) /* must be 4K aligned */ + return -EINVAL; + if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) + return -EBUSY; + + base_addr >>= 12; +- t3_write_reg(adapter, A_SG_CONTEXT_DATA0, base_addr); ++ t3_write_reg(adapter, A_SG_CONTEXT_DATA0, (u32)base_addr); + base_addr >>= 32; + t3_write_reg(adapter, A_SG_CONTEXT_DATA1, +- V_FL_BASE_HI((u32) base_addr) | ++ V_FL_BASE_HI((u32)base_addr) | + V_FL_INDEX_LO(cidx & M_FL_INDEX_LO)); + t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) | + V_FL_GEN(gen) | V_FL_INDEX_HI(cidx >> 12) | +@@ -2118,13 +2490,13 @@ + * The caller is responsible for ensuring only one context operation + * occurs at a time. + */ +-int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id, +- int irq_vec_idx, u64 base_addr, unsigned int size, ++int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, ++ u64 base_addr, unsigned int size, + unsigned int fl_thres, int gen, unsigned int cidx) + { +- unsigned int intr = 0; +- +- if (base_addr & 0xfff) /* must be 4K aligned */ ++ unsigned int ctrl, intr = 0; ++ ++ if (base_addr & 0xfff) /* must be 4K aligned */ + return -EINVAL; + if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) + return -EBUSY; +@@ -2132,12 +2504,16 @@ + base_addr >>= 12; + t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) | + V_CQ_INDEX(cidx)); +- t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr); ++ t3_write_reg(adapter, A_SG_CONTEXT_DATA1, (u32)base_addr); + base_addr >>= 32; +- if (irq_vec_idx >= 0) +- intr = V_RQ_MSI_VEC(irq_vec_idx) | F_RQ_INTR_EN; ++ ctrl = t3_read_reg(adapter, A_SG_CONTROL); ++ if ((irq_vec_idx > 0) || ++ ((irq_vec_idx == 0) && !(ctrl & F_ONEINTMULTQ))) ++ intr = F_RQ_INTR_EN; ++ if (irq_vec_idx >= 0) ++ intr |= V_RQ_MSI_VEC(irq_vec_idx); + t3_write_reg(adapter, A_SG_CONTEXT_DATA2, +- V_CQ_BASE_HI((u32) base_addr) | intr | V_RQ_GEN(gen)); ++ V_CQ_BASE_HI((u32)base_addr) | intr | V_RQ_GEN(gen)); + t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres); + return t3_sge_write_context(adapter, id, F_RESPONSEQ); + } +@@ -2157,21 +2533,21 @@ + * The caller is responsible for ensuring only one context operation + * occurs at a time. + */ +-int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr, ++int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, + unsigned int size, int rspq, int ovfl_mode, + unsigned int credits, unsigned int credit_thres) + { +- if (base_addr & 0xfff) /* must be 4K aligned */ ++ if (base_addr & 0xfff) /* must be 4K aligned */ + return -EINVAL; + if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) + return -EBUSY; + + base_addr >>= 12; + t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size)); +- t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr); ++ t3_write_reg(adapter, A_SG_CONTEXT_DATA1, (u32)base_addr); + base_addr >>= 32; + t3_write_reg(adapter, A_SG_CONTEXT_DATA2, +- V_CQ_BASE_HI((u32) base_addr) | V_CQ_RSPQ(rspq) | ++ V_CQ_BASE_HI((u32)base_addr) | V_CQ_RSPQ(rspq) | + V_CQ_GEN(1) | V_CQ_OVERFLOW_MODE(ovfl_mode) | + V_CQ_ERR(ovfl_mode)); + t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) | +@@ -2188,7 +2564,7 @@ + * Enable or disable an SGE egress context. The caller is responsible for + * ensuring only one context operation occurs at a time. + */ +-int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable) ++int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable) + { + if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) + return -EBUSY; +@@ -2212,7 +2588,7 @@ + * Disable an SGE free-buffer list. The caller is responsible for + * ensuring only one context operation occurs at a time. + */ +-int t3_sge_disable_fl(struct adapter *adapter, unsigned int id) ++int t3_sge_disable_fl(adapter_t *adapter, unsigned int id) + { + if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) + return -EBUSY; +@@ -2236,7 +2612,7 @@ + * Disable an SGE response queue. The caller is responsible for + * ensuring only one context operation occurs at a time. + */ +-int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id) ++int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id) + { + if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) + return -EBUSY; +@@ -2260,7 +2636,7 @@ + * Disable an SGE completion queue. The caller is responsible for + * ensuring only one context operation occurs at a time. + */ +-int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id) ++int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id) + { + if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) + return -EBUSY; +@@ -2281,12 +2657,16 @@ + * @adapter: the adapter + * @id: the context id + * @op: the operation to perform ++ * @credits: credits to return to the CQ + * + * Perform the selected operation on an SGE completion queue context. + * The caller is responsible for ensuring only one context operation + * occurs at a time. +- */ +-int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op, ++ * ++ * For most operations the function returns the current HW position in ++ * the completion queue. ++ */ ++int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, + unsigned int credits) + { + u32 val; +@@ -2326,7 +2706,7 @@ + * Read an SGE egress context. The caller is responsible for ensuring + * only one context operation occurs at a time. + */ +-static int t3_sge_read_context(unsigned int type, struct adapter *adapter, ++static int t3_sge_read_context(unsigned int type, adapter_t *adapter, + unsigned int id, u32 data[4]) + { + if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) +@@ -2353,7 +2733,7 @@ + * Read an SGE egress context. The caller is responsible for ensuring + * only one context operation occurs at a time. + */ +-int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4]) ++int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]) + { + if (id >= 65536) + return -EINVAL; +@@ -2369,7 +2749,7 @@ + * Read an SGE CQ context. The caller is responsible for ensuring + * only one context operation occurs at a time. + */ +-int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4]) ++int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]) + { + if (id >= 65536) + return -EINVAL; +@@ -2385,7 +2765,7 @@ + * Read an SGE free-list context. The caller is responsible for ensuring + * only one context operation occurs at a time. + */ +-int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4]) ++int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]) + { + if (id >= SGE_QSETS * 2) + return -EINVAL; +@@ -2401,7 +2781,7 @@ + * Read an SGE response queue context. The caller is responsible for + * ensuring only one context operation occurs at a time. + */ +-int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4]) ++int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]) + { + if (id >= SGE_QSETS) + return -EINVAL; +@@ -2420,8 +2800,8 @@ + * provide fewer values than the size of the tables the supplied values + * are used repeatedly until the tables are fully populated. + */ +-void t3_config_rss(struct adapter *adapter, unsigned int rss_config, +- const u8 * cpus, const u16 *rspq) ++void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, ++ const u16 *rspq) + { + int i, j, cpu_idx = 0, q_idx = 0; + +@@ -2456,7 +2836,7 @@ + * + * Reads the contents of the receive packet steering tables. + */ +-int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map) ++int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map) + { + int i; + u32 val; +@@ -2468,8 +2848,8 @@ + val = t3_read_reg(adapter, A_TP_RSS_LKP_TABLE); + if (!(val & 0x80000000)) + return -EAGAIN; +- *lkup++ = val; +- *lkup++ = (val >> 8); ++ *lkup++ = (u8)val; ++ *lkup++ = (u8)(val >> 8); + } + + if (map) +@@ -2479,7 +2859,7 @@ + val = t3_read_reg(adapter, A_TP_RSS_MAP_TABLE); + if (!(val & 0x80000000)) + return -EAGAIN; +- *map++ = val; ++ *map++ = (u16)val; + } + return 0; + } +@@ -2491,7 +2871,7 @@ + * + * Switches TP to NIC/offload mode. + */ +-void t3_tp_set_offload_mode(struct adapter *adap, int enable) ++void t3_tp_set_offload_mode(adapter_t *adap, int enable) + { + if (is_offload(adap) || !enable) + t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE, +@@ -2499,6 +2879,52 @@ + } + + /** ++ * tp_wr_bits_indirect - set/clear bits in an indirect TP register ++ * @adap: the adapter ++ * @addr: the indirect TP register address ++ * @mask: specifies the field within the register to modify ++ * @val: new value for the field ++ * ++ * Sets a field of an indirect TP register to the given value. ++ */ ++static void tp_wr_bits_indirect(adapter_t *adap, unsigned int addr, ++ unsigned int mask, unsigned int val) ++{ ++ t3_write_reg(adap, A_TP_PIO_ADDR, addr); ++ val |= t3_read_reg(adap, A_TP_PIO_DATA) & ~mask; ++ t3_write_reg(adap, A_TP_PIO_DATA, val); ++} ++ ++/** ++ * t3_enable_filters - enable the HW filters ++ * @adap: the adapter ++ * ++ * Enables the HW filters for NIC traffic. ++ */ ++void t3_enable_filters(adapter_t *adap) ++{ ++ t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE, 0); ++ t3_set_reg_field(adap, A_MC5_DB_CONFIG, 0, F_FILTEREN); ++ t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG, 0, V_FIVETUPLELOOKUP(3)); ++ tp_wr_bits_indirect(adap, A_TP_INGRESS_CONFIG, 0, F_LOOKUPEVERYPKT); ++} ++ ++/** ++ * t3_disable_filters - disable the HW filters ++ * @adap: the adapter ++ * ++ * Disables the HW filters for NIC traffic. ++ */ ++void t3_disable_filters(adapter_t *adap) ++{ ++ /* note that we don't want to revert to NIC-only mode */ ++ t3_set_reg_field(adap, A_MC5_DB_CONFIG, F_FILTEREN, 0); ++ t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG, ++ V_FIVETUPLELOOKUP(M_FIVETUPLELOOKUP), 0); ++ tp_wr_bits_indirect(adap, A_TP_INGRESS_CONFIG, F_LOOKUPEVERYPKT, 0); ++} ++ ++/** + * pm_num_pages - calculate the number of pages of the payload memory + * @mem_size: the size of the payload memory + * @pg_size: the size of each payload memory page +@@ -2527,7 +2953,7 @@ + * Partitions context and payload memory and configures TP's memory + * registers. + */ +-static void partition_mem(struct adapter *adap, const struct tp_params *p) ++static void partition_mem(adapter_t *adap, const struct tp_params *p) + { + unsigned int m, pstructs, tids = t3_mc5_size(&adap->mc5); + unsigned int timers = 0, timers_shift = 22; +@@ -2585,24 +3011,29 @@ + adap->params.mc5.nservers += m - tids; + } + +-static inline void tp_wr_indirect(struct adapter *adap, unsigned int addr, +- u32 val) ++static inline void tp_wr_indirect(adapter_t *adap, unsigned int addr, u32 val) + { + t3_write_reg(adap, A_TP_PIO_ADDR, addr); + t3_write_reg(adap, A_TP_PIO_DATA, val); + } + +-static void tp_config(struct adapter *adap, const struct tp_params *p) ++static inline u32 tp_rd_indirect(adapter_t *adap, unsigned int addr) ++{ ++ t3_write_reg(adap, A_TP_PIO_ADDR, addr); ++ return t3_read_reg(adap, A_TP_PIO_DATA); ++} ++ ++static void tp_config(adapter_t *adap, const struct tp_params *p) + { + t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU | + F_IPCHECKSUMOFFLOAD | F_UDPCHECKSUMOFFLOAD | + F_TCPCHECKSUMOFFLOAD | V_IPTTL(64)); + t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) | + F_MTUENABLE | V_WINDOWSCALEMODE(1) | +- V_TIMESTAMPSMODE(0) | V_SACKMODE(1) | V_SACKRX(1)); ++ V_TIMESTAMPSMODE(1) | V_SACKMODE(1) | V_SACKRX(1)); + t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) | + V_AUTOSTATE2(1) | V_AUTOSTATE1(0) | +- V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) | ++ V_BYTETHRESHOLD(26880) | V_MSSTHRESHOLD(2) | + F_AUTOCAREFUL | F_AUTOENABLE | V_DACK_MODE(1)); + t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO, + F_IPV6ENABLE | F_NICMODE); +@@ -2610,8 +3041,7 @@ + t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105); + t3_set_reg_field(adap, A_TP_PARA_REG6, 0, + adap->params.rev > 0 ? F_ENABLEESND : +- F_T3A_ENABLEESND); +- ++ F_T3A_ENABLEESND); + t3_set_reg_field(adap, A_TP_PC_CONFIG, + F_ENABLEEPCMDAFULL, + F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK | +@@ -2624,10 +3054,12 @@ + + if (adap->params.rev > 0) { + tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE); +- t3_set_reg_field(adap, A_TP_PARA_REG3, F_TXPACEAUTO, +- F_TXPACEAUTO); ++ t3_set_reg_field(adap, A_TP_PARA_REG3, 0, ++ F_TXPACEAUTO | F_TXPACEAUTOSTRICT); + t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID); +- t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEAUTOSTRICT); ++ tp_wr_indirect(adap, A_TP_VLAN_PRI_MAP, 0xfa50); ++ tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP0, 0xfac688); ++ tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP1, 0xfac688); + } else + t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED); + +@@ -2640,10 +3072,22 @@ + t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0); + t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0); + t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000); +-} +- +-/* Desired TP timer resolution in usec */ +-#define TP_TMR_RES 50 ++ ++ if (adap->params.nports > 2) { ++ t3_set_reg_field(adap, A_TP_PC_CONFIG2, 0, ++ F_ENABLETXPORTFROMDA2 | F_ENABLETXPORTFROMDA | ++ F_ENABLERXPORTFROMADDR); ++ tp_wr_bits_indirect(adap, A_TP_QOS_RX_MAP_MODE, ++ V_RXMAPMODE(M_RXMAPMODE), 0); ++ tp_wr_indirect(adap, A_TP_INGRESS_CONFIG, V_BITPOS0(48) | ++ V_BITPOS1(49) | V_BITPOS2(50) | V_BITPOS3(51) | ++ F_ENABLEEXTRACT | F_ENABLEEXTRACTIONSFD | ++ F_ENABLEINSERTION | F_ENABLEINSERTIONSFD); ++ tp_wr_indirect(adap, A_TP_PREAMBLE_MSB, 0xfb000000); ++ tp_wr_indirect(adap, A_TP_PREAMBLE_LSB, 0xd5); ++ tp_wr_indirect(adap, A_TP_INTF_FROM_TX_PKT, F_INTFFROMTXPKT); ++ } ++} + + /* TCP timer values in ms */ + #define TP_DACK_TIMER 50 +@@ -2657,11 +3101,11 @@ + * Set TP's timing parameters, such as the various timer resolutions and + * the TCP timer values. + */ +-static void tp_set_timers(struct adapter *adap, unsigned int core_clk) +-{ +- unsigned int tre = fls(core_clk / (1000000 / TP_TMR_RES)) - 1; +- unsigned int dack_re = fls(core_clk / 5000) - 1; /* 200us */ +- unsigned int tstamp_re = fls(core_clk / 1000); /* 1ms, at least */ ++static void tp_set_timers(adapter_t *adap, unsigned int core_clk) ++{ ++ unsigned int tre = adap->params.tp.tre; ++ unsigned int dack_re = adap->params.tp.dack_re; ++ unsigned int tstamp_re = fls(core_clk / 1000); /* 1ms, at least */ + unsigned int tps = core_clk >> tre; + + t3_write_reg(adap, A_TP_TIMER_RESOLUTION, V_TIMERRESOLUTION(tre) | +@@ -2680,7 +3124,8 @@ + + #define SECONDS * tps + +- t3_write_reg(adap, A_TP_MSL, adap->params.rev > 0 ? 0 : 2 SECONDS); ++ t3_write_reg(adap, A_TP_MSL, ++ adap->params.rev > 0 ? 0 : 2 SECONDS); + t3_write_reg(adap, A_TP_RXT_MIN, tps / (1000 / TP_RTO_MIN)); + t3_write_reg(adap, A_TP_RXT_MAX, 64 SECONDS); + t3_write_reg(adap, A_TP_PERS_MIN, 5 SECONDS); +@@ -2693,6 +3138,7 @@ + #undef SECONDS + } + ++#ifdef CONFIG_CHELSIO_T3_CORE + /** + * t3_tp_set_coalescing_size - set receive coalescing size + * @adap: the adapter +@@ -2701,7 +3147,7 @@ + * + * Set the receive coalescing size and PSH bit handling. + */ +-int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh) ++int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh) + { + u32 val; + +@@ -2731,13 +3177,13 @@ + * Set TP's max receive size. This is the limit that applies when + * receive coalescing is disabled. + */ +-void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size) ++void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size) + { + t3_write_reg(adap, A_TP_PARA_REG7, + V_PMMAXXFERLEN0(size) | V_PMMAXXFERLEN1(size)); + } + +-static void init_mtus(unsigned short mtus[]) ++static void __devinit init_mtus(unsigned short mtus[]) + { + /* + * See draft-mathis-plpmtud-00.txt for the values. The min is 88 so +@@ -2762,10 +3208,14 @@ + mtus[15] = 9600; + } + +-/* +- * Initial congestion control parameters. +- */ +-static void init_cong_ctrl(unsigned short *a, unsigned short *b) ++/** ++ * init_cong_ctrl - initialize congestion control parameters ++ * @a: the alpha values for congestion control ++ * @b: the beta values for congestion control ++ * ++ * Initialize the congestion control parameters. ++ */ ++static void __devinit init_cong_ctrl(unsigned short *a, unsigned short *b) + { + a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; + a[9] = 2; +@@ -2809,7 +3259,7 @@ + * t3_load_mtus - write the MTU and congestion control HW tables + * @adap: the adapter + * @mtus: the unrestricted values for the MTU table +- * @alphs: the values for the congestion control alpha parameter ++ * @alpha: the values for the congestion control alpha parameter + * @beta: the values for the congestion control beta parameter + * @mtu_cap: the maximum permitted effective MTU + * +@@ -2817,15 +3267,14 @@ + * Update the high-speed congestion control table with the supplied alpha, + * beta, and MTUs. + */ +-void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS], ++void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS], + unsigned short alpha[NCCTRL_WIN], + unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap) + { + static const unsigned int avg_pkts[NCCTRL_WIN] = { + 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, + 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, +- 28672, 40960, 57344, 81920, 114688, 163840, 229376 +- }; ++ 28672, 40960, 57344, 81920, 114688, 163840, 229376 }; + + unsigned int i, w; + +@@ -2833,7 +3282,7 @@ + unsigned int mtu = min(mtus[i], mtu_cap); + unsigned int log2 = fls(mtu); + +- if (!(mtu & ((1 << log2) >> 2))) /* round */ ++ if (!(mtu & ((1 << log2) >> 2))) /* round */ + log2--; + t3_write_reg(adap, A_TP_MTU_TABLE, + (i << 24) | (log2 << 16) | mtu); +@@ -2857,7 +3306,7 @@ + * + * Reads the HW MTU table. + */ +-void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS]) ++void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]) + { + int i; + +@@ -2878,7 +3327,7 @@ + * Reads the additive increments programmed into the HW congestion + * control table. + */ +-void t3_get_cong_cntl_tab(struct adapter *adap, ++void t3_get_cong_cntl_tab(adapter_t *adap, + unsigned short incr[NMTUS][NCCTRL_WIN]) + { + unsigned int mtu, w; +@@ -2887,8 +3336,8 @@ + for (w = 0; w < NCCTRL_WIN; ++w) { + t3_write_reg(adap, A_TP_CCTRL_TABLE, + 0xffff0000 | (mtu << 5) | w); +- incr[mtu][w] = t3_read_reg(adap, A_TP_CCTRL_TABLE) & +- 0x1fff; ++ incr[mtu][w] = (unsigned short)t3_read_reg(adap, ++ A_TP_CCTRL_TABLE) & 0x1fff; + } + } + +@@ -2899,10 +3348,46 @@ + * + * Returns the values of TP's MIB counters. + */ +-void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps) +-{ +- t3_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_RDATA, (u32 *) tps, ++void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps) ++{ ++ t3_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_RDATA, (u32 *)tps, + sizeof(*tps) / sizeof(u32), 0); ++} ++ ++/** ++ * t3_read_pace_tbl - read the pace table ++ * @adap: the adapter ++ * @pace_vals: holds the returned values ++ * ++ * Returns the values of TP's pace table in nanoseconds. ++ */ ++void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]) ++{ ++ unsigned int i, tick_ns = dack_ticks_to_usec(adap, 1000); ++ ++ for (i = 0; i < NTX_SCHED; i++) { ++ t3_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); ++ pace_vals[i] = t3_read_reg(adap, A_TP_PACE_TABLE) * tick_ns; ++ } ++} ++ ++/** ++ * t3_set_pace_tbl - set the pace table ++ * @adap: the adapter ++ * @pace_vals: the pace values in nanoseconds ++ * @start: index of the first entry in the HW pace table to set ++ * @n: how many entries to set ++ * ++ * Sets (a subset of the) HW pace table. ++ */ ++void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals, ++ unsigned int start, unsigned int n) ++{ ++ unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); ++ ++ for ( ; n; n--, start++, pace_vals++) ++ t3_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | ++ ((*pace_vals + tick_ns / 2) / tick_ns)); + } + + #define ulp_region(adap, name, start, len) \ +@@ -2916,7 +3401,7 @@ + t3_write_reg((adap), A_ULPTX_ ## name ## _ULIMIT, \ + (start) + (len) - 1) + +-static void ulp_config(struct adapter *adap, const struct tp_params *p) ++static void ulp_config(adapter_t *adap, const struct tp_params *p) + { + unsigned int m = p->chan_rx_size; + +@@ -2930,6 +3415,7 @@ + t3_write_reg(adap, A_ULPRX_TDDP_TAGMASK, 0xffffffff); + } + ++ + /** + * t3_set_proto_sram - set the contents of the protocol sram + * @adapter: the adapter +@@ -2937,30 +3423,38 @@ + * + * Write the contents of the protocol SRAM. + */ +-int t3_set_proto_sram(struct adapter *adap, const u8 *data) ++int t3_set_proto_sram(adapter_t *adap, const u8 *data) + { + int i; +- const __be32 *buf = (const __be32 *)data; ++ u32 *buf = (u32 *)data; + + for (i = 0; i < PROTO_SRAM_LINES; i++) { +- t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, be32_to_cpu(*buf++)); +- t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, be32_to_cpu(*buf++)); +- t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, be32_to_cpu(*buf++)); +- t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, be32_to_cpu(*buf++)); +- t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, be32_to_cpu(*buf++)); ++ t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, cpu_to_be32(*buf++)); ++ t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, cpu_to_be32(*buf++)); ++ t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, cpu_to_be32(*buf++)); ++ t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, cpu_to_be32(*buf++)); ++ t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, cpu_to_be32(*buf++)); + + t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31); + if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1)) + return -EIO; + } +- t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, 0); +- +- return 0; +-} +- +-void t3_config_trace_filter(struct adapter *adapter, +- const struct trace_params *tp, int filter_index, +- int invert, int enable) ++ return 0; ++} ++#endif ++ ++/** ++ * t3_config_trace_filter - configure one of the tracing filters ++ * @adapter: the adapter ++ * @tp: the desired trace filter parameters ++ * @filter_index: which filter to configure ++ * @invert: if set non-matching packets are traced instead of matching ones ++ * @enable: whether to enable or disable the filter ++ * ++ * Configures one of the tracing filters available in HW. ++ */ ++void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, ++ int filter_index, int invert, int enable) + { + u32 addr, key[4], mask[4]; + +@@ -2987,8 +3481,53 @@ + tp_wr_indirect(adapter, addr++, key[2]); + tp_wr_indirect(adapter, addr++, mask[2]); + tp_wr_indirect(adapter, addr++, key[3]); +- tp_wr_indirect(adapter, addr, mask[3]); +- t3_read_reg(adapter, A_TP_PIO_DATA); ++ tp_wr_indirect(adapter, addr, mask[3]); ++ (void) t3_read_reg(adapter, A_TP_PIO_DATA); ++} ++ ++/** ++ * t3_query_trace_filter - query a tracing filter ++ * @adapter: the adapter ++ * @tp: the current trace filter parameters ++ * @filter_index: which filter to query ++ * @inverted: non-zero if the filter is inverted ++ * @enabled: non-zero if the filter is enabled ++ * ++ * Returns the current settings of the specified HW tracing filter. ++ */ ++void t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp, ++ int filter_index, int *inverted, int *enabled) ++{ ++ u32 addr, key[4], mask[4]; ++ ++ addr = filter_index ? A_TP_RX_TRC_KEY0 : A_TP_TX_TRC_KEY0; ++ key[0] = tp_rd_indirect(adapter, addr++); ++ mask[0] = tp_rd_indirect(adapter, addr++); ++ key[1] = tp_rd_indirect(adapter, addr++); ++ mask[1] = tp_rd_indirect(adapter, addr++); ++ key[2] = tp_rd_indirect(adapter, addr++); ++ mask[2] = tp_rd_indirect(adapter, addr++); ++ key[3] = tp_rd_indirect(adapter, addr++); ++ mask[3] = tp_rd_indirect(adapter, addr); ++ ++ tp->sport = key[0] & 0xffff; ++ tp->sip = (key[0] >> 16) | ((key[1] & 0xffff) << 16); ++ tp->dport = key[1] >> 16; ++ tp->dip = key[2]; ++ tp->proto = key[3] & 0xff; ++ tp->vlan = key[3] >> 8; ++ tp->intf = key[3] >> 20; ++ ++ tp->sport_mask = mask[0] & 0xffff; ++ tp->sip_mask = (mask[0] >> 16) | ((mask[1] & 0xffff) << 16); ++ tp->dport_mask = mask[1] >> 16; ++ tp->dip_mask = mask[2]; ++ tp->proto_mask = mask[3] & 0xff; ++ tp->vlan_mask = mask[3] >> 8; ++ tp->intf_mask = mask[3] >> 20; ++ ++ *inverted = key[3] & (1 << 29); ++ *enabled = key[3] & (1 << 28); + } + + /** +@@ -2997,23 +3536,23 @@ + * @kbps: target rate in Kbps + * @sched: the scheduler index + * +- * Configure a HW scheduler for the target rate +- */ +-int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched) ++ * Configure a Tx HW scheduler for the target rate. ++ */ ++int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched) + { + unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; + unsigned int clk = adap->params.vpd.cclk * 1000; + unsigned int selected_cpt = 0, selected_bpt = 0; + + if (kbps > 0) { +- kbps *= 125; /* -> bytes */ ++ kbps *= 125; /* -> bytes */ + for (cpt = 1; cpt <= 255; cpt++) { + tps = clk / cpt; + bpt = (kbps + tps / 2) / tps; + if (bpt > 0 && bpt <= 255) { + v = bpt * tps; + delta = v >= kbps ? v - kbps : kbps - v; +- if (delta <= mindelta) { ++ if (delta < mindelta) { + mindelta = delta; + selected_cpt = cpt; + selected_bpt = bpt; +@@ -3035,7 +3574,83 @@ + return 0; + } + +-static int tp_init(struct adapter *adap, const struct tp_params *p) ++/** ++ * t3_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler ++ * @adap: the adapter ++ * @sched: the scheduler index ++ * @ipg: the interpacket delay in tenths of nanoseconds ++ * ++ * Set the interpacket delay for a HW packet rate scheduler. ++ */ ++int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg) ++{ ++ unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; ++ ++ /* convert ipg to nearest number of core clocks */ ++ ipg *= core_ticks_per_usec(adap); ++ ipg = (ipg + 5000) / 10000; ++ if (ipg > 0xffff) ++ return -EINVAL; ++ ++ t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr); ++ v = t3_read_reg(adap, A_TP_TM_PIO_DATA); ++ if (sched & 1) ++ v = (v & 0xffff) | (ipg << 16); ++ else ++ v = (v & 0xffff0000) | ipg; ++ t3_write_reg(adap, A_TP_TM_PIO_DATA, v); ++ t3_read_reg(adap, A_TP_TM_PIO_DATA); ++ return 0; ++} ++ ++/** ++ * t3_get_tx_sched - get the configuration of a Tx HW traffic scheduler ++ * @adap: the adapter ++ * @sched: the scheduler index ++ * @kbps: the byte rate in Kbps ++ * @ipg: the interpacket delay in tenths of nanoseconds ++ * ++ * Return the current configuration of a HW Tx scheduler. ++ */ ++void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps, ++ unsigned int *ipg) ++{ ++ unsigned int v, addr, bpt, cpt; ++ ++ if (kbps) { ++ addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; ++ t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr); ++ v = t3_read_reg(adap, A_TP_TM_PIO_DATA); ++ if (sched & 1) ++ v >>= 16; ++ bpt = (v >> 8) & 0xff; ++ cpt = v & 0xff; ++ if (!cpt) ++ *kbps = 0; /* scheduler disabled */ ++ else { ++ v = (adap->params.vpd.cclk * 1000) / cpt; ++ *kbps = (v * bpt) / 125; ++ } ++ } ++ if (ipg) { ++ addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; ++ t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr); ++ v = t3_read_reg(adap, A_TP_TM_PIO_DATA); ++ if (sched & 1) ++ v >>= 16; ++ v &= 0xffff; ++ *ipg = (10000 * v) / core_ticks_per_usec(adap); ++ } ++} ++ ++/** ++ * tp_init - configure TP ++ * @adap: the adapter ++ * @p: TP configuration parameters ++ * ++ * Initializes the TP HW module. ++ */ ++static int tp_init(adapter_t *adap, const struct tp_params *p) + { + int busy = 0; + +@@ -3056,7 +3671,14 @@ + return busy; + } + +-int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask) ++/** ++ * t3_mps_set_active_ports - configure port failover ++ * @adap: the adapter ++ * @port_mask: bitmap of active ports ++ * ++ * Sets the active ports according to the supplied bitmap. ++ */ ++int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask) + { + if (port_mask & ~((1 << adap->params.nports) - 1)) + return -EINVAL; +@@ -3065,21 +3687,32 @@ + return 0; + } + +-/* +- * Perform the bits of HW initialization that are dependent on the number +- * of available ports. +- */ +-static void init_hw_for_avail_ports(struct adapter *adap, int nports) ++/** ++ * chan_init_hw - channel-dependent HW initialization ++ * @adap: the adapter ++ * @chan_map: bitmap of Tx channels being used ++ * ++ * Perform the bits of HW initialization that are dependent on the Tx ++ * channels being used. ++ */ ++static void chan_init_hw(adapter_t *adap, unsigned int chan_map) + { + int i; + +- if (nports == 1) { ++ if (chan_map != 3) { /* one channel */ + t3_set_reg_field(adap, A_ULPRX_CTL, F_ROUND_ROBIN, 0); + t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0); +- t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_TPTXPORT0EN | +- F_PORT0ACTIVE | F_ENFORCEPKT); +- t3_write_reg(adap, A_PM1_TX_CFG, 0xffffffff); +- } else { ++ t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_ENFORCEPKT | ++ (chan_map == 1 ? F_TPTXPORT0EN | F_PORT0ACTIVE : ++ F_TPTXPORT1EN | F_PORT1ACTIVE)); ++ t3_write_reg(adap, A_PM1_TX_CFG, ++ chan_map == 1 ? 0xffffffff : 0); ++ if (chan_map == 2) ++ t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP, ++ V_TX_MOD_QUEUE_REQ_MAP(0xff)); ++ t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (12 << 16) | 0xd9c8); ++ t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (13 << 16) | 0xfbea); ++ } else { /* two channels */ + t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN); + t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB); + t3_write_reg(adap, A_ULPTX_DMA_WEIGHT, +@@ -3094,17 +3727,19 @@ + for (i = 0; i < 16; i++) + t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, + (i << 16) | 0x1010); +- } +-} +- +-static int calibrate_xgm(struct adapter *adapter) ++ t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (12 << 16) | 0xba98); ++ t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (13 << 16) | 0xfedc); ++ } ++} ++ ++static int calibrate_xgm(adapter_t *adapter) + { + if (uses_xaui(adapter)) { + unsigned int v, i; + + for (i = 0; i < 5; ++i) { + t3_write_reg(adapter, A_XGM_XAUI_IMP, 0); +- t3_read_reg(adapter, A_XGM_XAUI_IMP); ++ (void) t3_read_reg(adapter, A_XGM_XAUI_IMP); + msleep(1); + v = t3_read_reg(adapter, A_XGM_XAUI_IMP); + if (!(v & (F_XGM_CALFAULT | F_CALBUSY))) { +@@ -3124,7 +3759,7 @@ + return 0; + } + +-static void calibrate_xgm_t3b(struct adapter *adapter) ++static void calibrate_xgm_t3b(adapter_t *adapter) + { + if (!uses_xaui(adapter)) { + t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET | +@@ -3154,10 +3789,10 @@ + * writes normally complete in a cycle or two, so one read should suffice. + * The very first read exists to flush the posted write to the device. + */ +-static int wrreg_wait(struct adapter *adapter, unsigned int addr, u32 val) +-{ +- t3_write_reg(adapter, addr, val); +- t3_read_reg(adapter, addr); /* flush */ ++static int wrreg_wait(adapter_t *adapter, unsigned int addr, u32 val) ++{ ++ t3_write_reg(adapter, addr, val); ++ (void) t3_read_reg(adapter, addr); /* flush */ + if (!(t3_read_reg(adapter, addr) & F_BUSY)) + return 0; + CH_ERR(adapter, "write to MC7 register 0x%x timed out\n", addr); +@@ -3170,16 +3805,16 @@ + 0x632, 0x642, 0x652, 0x432, 0x442 + }; + static const struct mc7_timing_params mc7_timings[] = { +- {12, 3, 4, {20, 28, 34, 52, 0}, 15, 6, 4}, +- {12, 4, 5, {20, 28, 34, 52, 0}, 16, 7, 4}, +- {12, 5, 6, {20, 28, 34, 52, 0}, 17, 8, 4}, +- {9, 3, 4, {15, 21, 26, 39, 0}, 12, 6, 4}, +- {9, 4, 5, {15, 21, 26, 39, 0}, 13, 7, 4} ++ { 12, 3, 4, { 20, 28, 34, 52, 0 }, 15, 6, 4 }, ++ { 12, 4, 5, { 20, 28, 34, 52, 0 }, 16, 7, 4 }, ++ { 12, 5, 6, { 20, 28, 34, 52, 0 }, 17, 8, 4 }, ++ { 9, 3, 4, { 15, 21, 26, 39, 0 }, 12, 6, 4 }, ++ { 9, 4, 5, { 15, 21, 26, 39, 0 }, 13, 7, 4 } + }; + + u32 val; + unsigned int width, density, slow, attempts; +- struct adapter *adapter = mc7->adapter; ++ adapter_t *adapter = mc7->adapter; + const struct mc7_timing_params *p = &mc7_timings[mem_type]; + + if (!mc7->size) +@@ -3191,12 +3826,12 @@ + density = G_DEN(val); + + t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN); +- val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ ++ val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ + msleep(1); + + if (!slow) { + t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN); +- t3_read_reg(adapter, mc7->offset + A_MC7_CAL); ++ (void) t3_read_reg(adapter, mc7->offset + A_MC7_CAL); + msleep(1); + if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) & + (F_BUSY | F_SGL_CAL_EN | F_CAL_FAULT)) { +@@ -3214,7 +3849,7 @@ + + t3_write_reg(adapter, mc7->offset + A_MC7_CFG, + val | F_CLKEN | F_TERM150); +- t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ ++ (void) t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ + + if (!slow) + t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB, +@@ -3230,7 +3865,8 @@ + + if (!slow) { + t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100); +- t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLRST, 0); ++ t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, ++ F_DLLRST, 0); + udelay(5); + } + +@@ -3244,20 +3880,21 @@ + goto out_fail; + + /* clock value is in KHz */ +- mc7_clock = mc7_clock * 7812 + mc7_clock / 2; /* ns */ +- mc7_clock /= 1000000; /* KHz->MHz, ns->us */ ++ mc7_clock = mc7_clock * 7812 + mc7_clock / 2; /* ns */ ++ mc7_clock /= 1000000; /* KHz->MHz, ns->us */ + + t3_write_reg(adapter, mc7->offset + A_MC7_REF, + F_PERREFEN | V_PREREFDIV(mc7_clock)); +- t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */ +- +- t3_write_reg(adapter, mc7->offset + A_MC7_ECC, F_ECCGENEN | F_ECCCHKEN); ++ (void) t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */ ++ ++ t3_write_reg(adapter, mc7->offset + A_MC7_ECC, ++ F_ECCGENEN | F_ECCCHKEN); + t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0); + t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0); + t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END, + (mc7->size << width) - 1); + t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1)); +- t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */ ++ (void) t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */ + + attempts = 50; + do { +@@ -3273,43 +3910,56 @@ + t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY); + return 0; + +-out_fail: ++ out_fail: + return -1; + } + +-static void config_pcie(struct adapter *adap) ++static void config_pcie(adapter_t *adap) + { + static const u16 ack_lat[4][6] = { +- {237, 416, 559, 1071, 2095, 4143}, +- {128, 217, 289, 545, 1057, 2081}, +- {73, 118, 154, 282, 538, 1050}, +- {67, 107, 86, 150, 278, 534} ++ { 237, 416, 559, 1071, 2095, 4143 }, ++ { 128, 217, 289, 545, 1057, 2081 }, ++ { 73, 118, 154, 282, 538, 1050 }, ++ { 67, 107, 86, 150, 278, 534 } + }; + static const u16 rpl_tmr[4][6] = { +- {711, 1248, 1677, 3213, 6285, 12429}, +- {384, 651, 867, 1635, 3171, 6243}, +- {219, 354, 462, 846, 1614, 3150}, +- {201, 321, 258, 450, 834, 1602} +- }; +- +- u16 val; ++ { 711, 1248, 1677, 3213, 6285, 12429 }, ++ { 384, 651, 867, 1635, 3171, 6243 }, ++ { 219, 354, 462, 846, 1614, 3150 }, ++ { 201, 321, 258, 450, 834, 1602 } ++ }; ++ ++ u16 val, devid; + unsigned int log2_width, pldsize; + unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt; + +- pci_read_config_word(adap->pdev, +- adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL, +- &val); ++ t3_os_pci_read_config_2(adap, ++ adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL, ++ &val); + pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5; +- pci_read_config_word(adap->pdev, +- adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL, +- &val); ++ ++ /* ++ * Gen2 adapter pcie bridge compatibility requires minimum Max_Read_Request_size ++ * ++ */ ++ t3_os_pci_read_config_2(adap, 0x2, &devid); ++ if (devid == 0x37) { ++ t3_os_pci_write_config_2(adap, ++ adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL, ++ val & ~PCI_EXP_DEVCTL_READRQ & ~PCI_EXP_DEVCTL_PAYLOAD); ++ pldsize = 0; ++ } ++ ++ t3_os_pci_read_config_2(adap, ++ adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL, ++ &val); + + fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0)); + fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx : +- G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE)); ++ G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE)); + log2_width = fls(adap->params.pci.width) - 1; + acklat = ack_lat[log2_width][pldsize]; +- if (val & 1) /* check LOsEnable */ ++ if (val & 1) /* check LOsEnable */ + acklat += fst_trn_tx * 4; + rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4; + +@@ -3330,15 +3980,20 @@ + F_PCIE_DMASTOPEN | F_PCIE_CLIDECEN); + } + +-/* +- * Initialize and configure T3 HW modules. This performs the +- * initialization steps that need to be done once after a card is reset. +- * MAC and PHY initialization is handled separarely whenever a port is enabled. +- * +- * fw_params are passed to FW and their value is platform dependent. Only the +- * top 8 bits are available for use, the rest must be 0. +- */ +-int t3_init_hw(struct adapter *adapter, u32 fw_params) ++/** ++ * t3_init_hw - initialize and configure T3 HW modules ++ * @adapter: the adapter ++ * @fw_params: initial parameters to pass to firmware (optional) ++ * ++ * Initialize and configure T3 HW modules. This performs the ++ * initialization steps that need to be done once after a card is reset. ++ * MAC and PHY initialization is handled separarely whenever a port is ++ * enabled. ++ * ++ * @fw_params are passed to FW and their value is platform dependent. ++ * Only the top 8 bits are available for use, the rest must be 0. ++ */ ++int t3_init_hw(adapter_t *adapter, u32 fw_params) + { + int err = -EIO, attempts, i; + const struct vpd_params *vpd = &adapter->params.vpd; +@@ -3348,6 +4003,9 @@ + else if (calibrate_xgm(adapter)) + goto out_err; + ++ if (adapter->params.nports > 2) ++ t3_mac_reset(&adap2pinfo(adapter, 0)->mac); ++ + if (vpd->mclk) { + partition_mem(adapter, &adapter->params.tp); + +@@ -3355,8 +4013,8 @@ + mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) || + mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) || + t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers, +- adapter->params.mc5.nfilters, +- adapter->params.mc5.nroutes)) ++ adapter->params.mc5.nfilters, ++ adapter->params.mc5.nroutes)) + goto out_err; + + for (i = 0; i < 32; i++) +@@ -3367,13 +4025,14 @@ + if (tp_init(adapter, &adapter->params.tp)) + goto out_err; + ++#ifdef CONFIG_CHELSIO_T3_CORE + t3_tp_set_coalescing_size(adapter, + min(adapter->params.sge.max_pkt_size, + MAX_RX_COALESCING_LEN), 1); + t3_tp_set_max_rxsize(adapter, + min(adapter->params.sge.max_pkt_size, 16384U)); + ulp_config(adapter, &adapter->params.tp); +- ++#endif + if (is_pcie(adapter)) + config_pcie(adapter); + else +@@ -3387,7 +4046,7 @@ + t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff); + t3_write_reg(adapter, A_PM1_RX_MODE, 0); + t3_write_reg(adapter, A_PM1_TX_MODE, 0); +- init_hw_for_avail_ports(adapter, adapter->params.nports); ++ chan_init_hw(adapter, adapter->params.chan_map); + t3_sge_init(adapter, &adapter->params.sge); + + t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter)); +@@ -3395,10 +4054,10 @@ + t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params); + t3_write_reg(adapter, A_CIM_BOOT_CFG, + V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2)); +- t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */ ++ (void) t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */ + + attempts = 100; +- do { /* wait for uP to initialize */ ++ do { /* wait for uP to initialize */ + msleep(20); + } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts); + if (!attempts) { +@@ -3407,7 +4066,7 @@ + } + + err = 0; +-out_err: ++ out_err: + return err; + } + +@@ -3419,18 +4078,18 @@ + * Determines a card's PCI mode and associated parameters, such as speed + * and width. + */ +-static void get_pci_mode(struct adapter *adapter, struct pci_params *p) ++static void __devinit get_pci_mode(adapter_t *adapter, struct pci_params *p) + { + static unsigned short speed_map[] = { 33, 66, 100, 133 }; + u32 pci_mode, pcie_cap; + +- pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); ++ pcie_cap = t3_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); + if (pcie_cap) { + u16 val; + + p->variant = PCI_VARIANT_PCIE; + p->pcie_cap_addr = pcie_cap; +- pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA, ++ t3_os_pci_read_config_2(adapter, pcie_cap + PCI_EXP_LNKSTA, + &val); + p->width = (val >> 4) & 0x3f; + return; +@@ -3453,13 +4112,14 @@ + /** + * init_link_config - initialize a link's SW state + * @lc: structure holding the link state +- * @ai: information about the current card ++ * @caps: link capabilities + * + * Initializes the SW state maintained for each link, including the link's + * capabilities and default speed/duplex/flow-control/autonegotiation + * settings. + */ +-static void init_link_config(struct link_config *lc, unsigned int caps) ++static void __devinit init_link_config(struct link_config *lc, ++ unsigned int caps) + { + lc->supported = caps; + lc->requested_speed = lc->speed = SPEED_INVALID; +@@ -3482,7 +4142,7 @@ + * Calculates the size of an MC7 memory in bytes from the value of its + * configuration register. + */ +-static unsigned int mc7_calc_size(u32 cfg) ++static unsigned int __devinit mc7_calc_size(u32 cfg) + { + unsigned int width = G_WIDTH(cfg); + unsigned int banks = !!(cfg & F_BKS) + 1; +@@ -3493,8 +4153,8 @@ + return MBs << 20; + } + +-static void mc7_prep(struct adapter *adapter, struct mc7 *mc7, +- unsigned int base_addr, const char *name) ++static void __devinit mc7_prep(adapter_t *adapter, struct mc7 *mc7, ++ unsigned int base_addr, const char *name) + { + u32 cfg; + +@@ -3502,15 +4162,32 @@ + mc7->name = name; + mc7->offset = base_addr - MC7_PMRX_BASE_ADDR; + cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); +- mc7->size = mc7->size = G_DEN(cfg) == M_DEN ? 0 : mc7_calc_size(cfg); ++ mc7->size = G_DEN(cfg) == M_DEN ? 0 : mc7_calc_size(cfg); + mc7->width = G_WIDTH(cfg); + } + +-void mac_prep(struct cmac *mac, struct adapter *adapter, int index) +-{ ++void mac_prep(struct cmac *mac, adapter_t *adapter, int index) ++{ ++ u16 devid; ++ + mac->adapter = adapter; ++ mac->multiport = adapter->params.nports > 2; ++ if (mac->multiport) { ++ mac->ext_port = (unsigned char)index; ++ mac->nucast = 8; ++ } else ++ mac->nucast = 1; ++ ++ /* Gen2 adapter uses VPD xauicfg[] to notify driver which MAC ++ is connected to each port, its suppose to be using xgmac0 for both ports ++ */ ++ t3_os_pci_read_config_2(adapter, 0x2, &devid); ++ ++ if (mac->multiport || ++ (!adapter->params.vpd.xauicfg[1] && (devid==0x37))) ++ index = 0; ++ + mac->offset = (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR) * index; +- mac->nucast = 1; + + if (adapter->params.rev == 0 && uses_xaui(adapter)) { + t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset, +@@ -3520,15 +4197,47 @@ + } + } + +-void early_hw_init(struct adapter *adapter, const struct adapter_info *ai) +-{ +- u32 val = V_PORTSPEED(is_10G(adapter) ? 3 : 2); ++/* ++ * First stash of BT adapters have GPIO6 polarity inverted. ++ * Apply this ugly patch to get them working. ++ * This does not guarantee any forward compatibility. ++ */ ++int is_demo_bt(adapter_t *adap) ++{ ++ const struct port_type_info *pti; ++ int j = -1; ++ ++ while (!adap->params.vpd.port_type[++j]) ++ j++; ++ pti = &port_types[adap->params.vpd.port_type[j]]; ++ ++ return (pti->phy_prep == t3_tn1010_phy_prep); ++} ++ ++/** ++ * early_hw_init - HW initialization done at card detection time ++ * @adapter: the adapter ++ * @ai: contains information about the adapter type and properties ++ * ++ * Perfoms the part of HW initialization that is done early on when the ++ * driver first detecs the card. Most of the HW state is initialized ++ * lazily later on when a port or an offload function are first used. ++ */ ++void early_hw_init(adapter_t *adapter, const struct adapter_info *ai) ++{ ++ u32 val = V_PORTSPEED(is_10G(adapter) || adapter->params.nports > 2 ? ++ 3 : 2); ++ u32 gpio_out = ai->gpio_out; + + mi1_init(adapter, ai); +- t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */ ++ t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */ + V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1)); ++ ++ if (is_demo_bt(adapter)) ++ gpio_out &= ~F_GPIO6_OUT_VAL; ++ + t3_write_reg(adapter, A_T3DBG_GPIO_EN, +- ai->gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL); ++ gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL); + t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0); + t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff)); + +@@ -3537,37 +4246,38 @@ + + /* Enable MAC clocks so we can access the registers */ + t3_write_reg(adapter, A_XGM_PORT_CFG, val); +- t3_read_reg(adapter, A_XGM_PORT_CFG); ++ (void) t3_read_reg(adapter, A_XGM_PORT_CFG); + + val |= F_CLKDIVRESET_; + t3_write_reg(adapter, A_XGM_PORT_CFG, val); +- t3_read_reg(adapter, A_XGM_PORT_CFG); ++ (void) t3_read_reg(adapter, A_XGM_PORT_CFG); + t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val); +- t3_read_reg(adapter, A_XGM_PORT_CFG); +-} +- +-/* +- * Reset the adapter. +- * Older PCIe cards lose their config space during reset, PCI-X +- * ones don't. +- */ +-int t3_reset_adapter(struct adapter *adapter) ++ (void) t3_read_reg(adapter, A_XGM_PORT_CFG); ++} ++ ++/** ++ * t3_reset_adapter - reset the adapter ++ * @adapter: the adapter ++ * ++ * Reset the adapter. ++ */ ++int t3_reset_adapter(adapter_t *adapter) + { + int i, save_and_restore_pcie = + adapter->params.rev < T3_REV_B2 && is_pcie(adapter); + uint16_t devid = 0; + + if (save_and_restore_pcie) +- pci_save_state(adapter->pdev); ++ t3_os_pci_save_state(adapter); + t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE); + +- /* ++ /* + * Delay. Give Some time to device to reset fully. + * XXX The delay time should be modified. + */ + for (i = 0; i < 10; i++) { + msleep(50); +- pci_read_config_word(adapter->pdev, 0x00, &devid); ++ t3_os_pci_read_config_2(adapter, 0x00, &devid); + if (devid == 0x1425) + break; + } +@@ -3576,13 +4286,13 @@ + return -1; + + if (save_and_restore_pcie) +- pci_restore_state(adapter->pdev); +- return 0; +-} +- +-static int init_parity(struct adapter *adap) +-{ +- int i, err, addr; ++ t3_os_pci_restore_state(adapter); ++ return 0; ++} ++ ++static int init_parity(adapter_t *adap) ++{ ++ int i, err, addr; + + if (t3_read_reg(adap, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) + return -EBUSY; +@@ -3610,27 +4320,46 @@ + return 0; + } + +-/* +- * Initialize adapter SW state for the various HW modules, set initial values +- * for some adapter tunables, take PHYs out of reset, and initialize the MDIO +- * interface. +- */ +-int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai, +- int reset) +-{ +- int ret; +- unsigned int i, j = -1; ++/** ++ * t3_prep_adapter - prepare SW and HW for operation ++ * @adapter: the adapter ++ * @ai: contains information about the adapter type and properties ++ * ++ * Initialize adapter SW state for the various HW modules, set initial ++ * values for some adapter tunables, take PHYs out of reset, and ++ * initialize the MDIO interface. ++ */ ++int __devinit t3_prep_adapter(adapter_t *adapter, ++ const struct adapter_info *ai, int reset) ++{ ++ int ret; ++ unsigned int i, j = 0; + + get_pci_mode(adapter, &adapter->params.pci); + + adapter->params.info = ai; +- adapter->params.nports = ai->nports; ++ adapter->params.nports = ai->nports0 + ai->nports1; ++ adapter->params.chan_map = !!ai->nports0 | (!!ai->nports1 << 1); + adapter->params.rev = t3_read_reg(adapter, A_PL_REV); +- adapter->params.linkpoll_period = 0; +- adapter->params.stats_update_period = is_10G(adapter) ? +- MAC_STATS_ACCUM_SECS : (MAC_STATS_ACCUM_SECS * 10); ++ ++ /* ++ * We used to only run the "adapter check task" once a second if ++ * we had PHYs which didn't support interrupts (we would check ++ * their link status once a second). Now we check other conditions ++ * in that routine which would [potentially] impose a very high ++ * interrupt load on the system. As such, we now always scan the ++ * adapter state once a second ... ++ */ ++ adapter->params.linkpoll_period = 10; ++ ++ if (adapter->params.nports > 2) ++ adapter->params.stats_update_period = VSC_STATS_ACCUM_SECS; ++ else ++ adapter->params.stats_update_period = is_10G(adapter) ? ++ MAC_STATS_ACCUM_SECS : (MAC_STATS_ACCUM_SECS * 10); + adapter->params.pci.vpd_cap_addr = +- pci_find_capability(adapter->pdev, PCI_CAP_ID_VPD); ++ t3_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); ++ + ret = get_vpd_params(adapter, &adapter->params.vpd); + if (ret < 0) + return ret; +@@ -3647,18 +4376,21 @@ + mc7_prep(adapter, &adapter->pmtx, MC7_PMTX_BASE_ADDR, "PMTX"); + mc7_prep(adapter, &adapter->cm, MC7_CM_BASE_ADDR, "CM"); + +- p->nchan = ai->nports; ++ p->nchan = adapter->params.chan_map == 3 ? 2 : 1; + p->pmrx_size = t3_mc7_size(&adapter->pmrx); + p->pmtx_size = t3_mc7_size(&adapter->pmtx); + p->cm_size = t3_mc7_size(&adapter->cm); +- p->chan_rx_size = p->pmrx_size / 2; /* only 1 Rx channel */ ++ p->chan_rx_size = p->pmrx_size / 2; /* only 1 Rx channel */ + p->chan_tx_size = p->pmtx_size / p->nchan; + p->rx_pg_size = 64 * 1024; + p->tx_pg_size = is_10G(adapter) ? 64 * 1024 : 16 * 1024; + p->rx_num_pgs = pm_num_pages(p->chan_rx_size, p->rx_pg_size); + p->tx_num_pgs = pm_num_pages(p->chan_tx_size, p->tx_pg_size); + p->ntimer_qs = p->cm_size >= (128 << 20) || +- adapter->params.rev > 0 ? 12 : 6; ++ adapter->params.rev > 0 ? 12 : 6; ++ p->tre = fls(adapter->params.vpd.cclk / (1000 / TP_TMR_RES)) - ++ 1; ++ p->dack_re = fls(adapter->params.vpd.cclk / 10) - 1; /* 100us */ + } + + adapter->params.offload = t3_mc7_size(&adapter->pmrx) && +@@ -3667,18 +4399,24 @@ + + if (is_offload(adapter)) { + adapter->params.mc5.nservers = DEFAULT_NSERVERS; +- adapter->params.mc5.nfilters = adapter->params.rev > 0 ? +- DEFAULT_NFILTERS : 0; ++ /* PR 6487. TOE and filtering are mutually exclusive */ ++ adapter->params.mc5.nfilters = 0; + adapter->params.mc5.nroutes = 0; + t3_mc5_prep(adapter, &adapter->mc5, MC5_MODE_144_BIT); + ++#ifdef CONFIG_CHELSIO_T3_CORE + init_mtus(adapter->params.mtus); + init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); ++#endif + } + + early_hw_init(adapter, ai); + ret = init_parity(adapter); + if (ret) ++ return ret; ++ ++ if (adapter->params.nports > 2 && ++ (ret = t3_vsc7323_init(adapter, adapter->params.nports))) + return ret; + + for_each_port(adapter, i) { +@@ -3686,21 +4424,25 @@ + const struct port_type_info *pti; + struct port_info *p = adap2pinfo(adapter, i); + +- while (!adapter->params.vpd.port_type[++j]) +- ; +- +- pti = &port_types[adapter->params.vpd.port_type[j]]; +- if (!pti->phy_prep) { +- CH_ALERT(adapter, "Invalid port type index %d\n", +- adapter->params.vpd.port_type[j]); +- return -EINVAL; +- } +- +- ret = pti->phy_prep(&p->phy, adapter, ai->phy_base_addr + j, ++ for (;;) { ++ unsigned port_type = adapter->params.vpd.port_type[j]; ++ if (port_type) { ++ if (port_type < ARRAY_SIZE(port_types)) { ++ pti = &port_types[port_type]; ++ break; ++ } else ++ return -EINVAL; ++ } ++ j++; ++ if (j >= ARRAY_SIZE(adapter->params.vpd.port_type)) ++ return -EINVAL; ++ } ++ ret = pti->phy_prep(p, ai->phy_base_addr + j, + ai->mdio_ops); + if (ret) + return ret; + mac_prep(&p->mac, adapter, j); ++ ++j; + + /* + * The VPD EEPROM stores the base Ethernet address for the +@@ -3710,50 +4452,221 @@ + memcpy(hw_addr, adapter->params.vpd.eth_base, 5); + hw_addr[5] = adapter->params.vpd.eth_base[5] + i; + +- memcpy(adapter->port[i]->dev_addr, hw_addr, +- ETH_ALEN); +- memcpy(adapter->port[i]->perm_addr, hw_addr, +- ETH_ALEN); ++ t3_os_set_hw_addr(adapter, i, hw_addr); + init_link_config(&p->link_config, p->phy.caps); + p->phy.ops->power_down(&p->phy, 1); +- if (!(p->phy.caps & SUPPORTED_IRQ)) ++ ++ /* ++ * If the PHY doesn't support interrupts for link status ++ * changes, schedule a scan of the adapter links at least ++ * once a second. ++ */ ++ if (!(p->phy.caps & SUPPORTED_IRQ) && ++ adapter->params.linkpoll_period > 10) + adapter->params.linkpoll_period = 10; + } + + return 0; + } + +-void t3_led_ready(struct adapter *adapter) ++/** ++ * t3_reinit_adapter - prepare HW for operation again ++ * @adapter: the adapter ++ * ++ * Put HW in the same state as @t3_prep_adapter without any changes to ++ * SW state. This is a cut down version of @t3_prep_adapter intended ++ * to be used after events that wipe out HW state but preserve SW state, ++ * e.g., EEH. The device must be reset before calling this. ++ */ ++int t3_reinit_adapter(adapter_t *adap) ++{ ++ unsigned int i; ++ int ret, j = 0; ++ ++ early_hw_init(adap, adap->params.info); ++ ret = init_parity(adap); ++ if (ret) ++ return ret; ++ ++ if (adap->params.nports > 2 && ++ (ret = t3_vsc7323_init(adap, adap->params.nports))) ++ return ret; ++ ++ for_each_port(adap, i) { ++ const struct port_type_info *pti; ++ struct port_info *p = adap2pinfo(adap, i); ++ ++ for (;;) { ++ unsigned port_type = adap->params.vpd.port_type[j]; ++ if (port_type) { ++ if (port_type < ARRAY_SIZE(port_types)) { ++ pti = &port_types[port_type]; ++ break; ++ } else ++ return -EINVAL; ++ } ++ j++; ++ if (j >= ARRAY_SIZE(adap->params.vpd.port_type)) ++ return -EINVAL; ++ } ++ ret = pti->phy_prep(p, p->phy.addr, NULL); ++ if (ret) ++ return ret; ++ p->phy.ops->power_down(&p->phy, 1); ++ } ++ return 0; ++} ++ ++void t3_led_ready(adapter_t *adapter) + { + t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL, + F_GPIO0_OUT_VAL); + } + +-int t3_replay_prep_adapter(struct adapter *adapter) +-{ +- const struct adapter_info *ai = adapter->params.info; +- unsigned int i, j = -1; +- int ret; +- +- early_hw_init(adapter, ai); +- ret = init_parity(adapter); +- if (ret) +- return ret; +- +- for_each_port(adapter, i) { +- const struct port_type_info *pti; +- struct port_info *p = adap2pinfo(adapter, i); +- +- while (!adapter->params.vpd.port_type[++j]) +- ; +- +- pti = &port_types[adapter->params.vpd.port_type[j]]; +- ret = pti->phy_prep(&p->phy, adapter, p->phy.addr, NULL); +- if (ret) +- return ret; +- p->phy.ops->power_down(&p->phy, 1); +- } +- +-return 0; +-} +- ++void t3_port_failover(adapter_t *adapter, int port) ++{ ++ u32 val; ++ ++ val = port ? F_PORT1ACTIVE : F_PORT0ACTIVE; ++ t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE, ++ val); ++} ++ ++void t3_failover_done(adapter_t *adapter, int port) ++{ ++ t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE, ++ F_PORT0ACTIVE | F_PORT1ACTIVE); ++} ++ ++void t3_failover_clear(adapter_t *adapter) ++{ ++ t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE, ++ F_PORT0ACTIVE | F_PORT1ACTIVE); ++} ++ ++static int t3_cim_hac_read(adapter_t *adapter, u32 addr, u32 *val) ++{ ++ u32 v; ++ ++ t3_write_reg(adapter, A_CIM_HOST_ACC_CTRL, addr); ++ if (t3_wait_op_done_val(adapter, A_CIM_HOST_ACC_CTRL, ++ F_HOSTBUSY, 0, 10, 10, &v)) ++ return -EIO; ++ ++ *val = t3_read_reg(adapter, A_CIM_HOST_ACC_DATA); ++ ++ return 0; ++} ++ ++static int t3_cim_hac_write(adapter_t *adapter, u32 addr, u32 val) ++{ ++ u32 v; ++ ++ t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, val); ++ ++ addr |= F_HOSTWRITE; ++ t3_write_reg(adapter, A_CIM_HOST_ACC_CTRL, addr); ++ ++ if (t3_wait_op_done_val(adapter, A_CIM_HOST_ACC_CTRL, ++ F_HOSTBUSY, 0, 10, 5, &v)) ++ return -EIO; ++ return 0; ++} ++ ++int t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index, ++ u32 *size, void *data) ++{ ++ u32 v, *buf = data; ++ int i, cnt, ret; ++ ++ if (*size < LA_ENTRIES * 4) ++ return -EINVAL; ++ ++ ret = t3_cim_hac_read(adapter, LA_CTRL, &v); ++ if (ret) ++ goto out; ++ ++ *stopped = !(v & 1); ++ ++ /* Freeze LA */ ++ if (!*stopped) { ++ ret = t3_cim_hac_write(adapter, LA_CTRL, 0); ++ if (ret) ++ goto out; ++ } ++ ++ for (i = 0; i < LA_ENTRIES; i++) { ++ v = (i << 2) | (1 << 1); ++ ret = t3_cim_hac_write(adapter, LA_CTRL, v); ++ if (ret) ++ goto out; ++ ++ ret = t3_cim_hac_read(adapter, LA_CTRL, &v); ++ if (ret) ++ goto out; ++ ++ cnt = 20; ++ while ((v & (1 << 1)) && cnt) { ++ udelay(5); ++ --cnt; ++ ret = t3_cim_hac_read(adapter, LA_CTRL, &v); ++ if (ret) ++ goto out; ++ } ++ ++ if (v & (1 << 1)) ++ return -EIO; ++ ++ ret = t3_cim_hac_read(adapter, LA_DATA, &v); ++ if (ret) ++ goto out; ++ ++ *buf++ = v; ++ } ++ ++ ret = t3_cim_hac_read(adapter, LA_CTRL, &v); ++ if (ret) ++ goto out; ++ ++ *index = (v >> 16) + 4; ++ *size = LA_ENTRIES * 4; ++out: ++ /* Unfreeze LA */ ++ t3_cim_hac_write(adapter, LA_CTRL, 1); ++ return ret; ++} ++ ++int t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data) ++{ ++ u32 v, *buf = data; ++ int i, j, ret; ++ ++ if (*size < IOQ_ENTRIES * sizeof(struct t3_ioq_entry)) ++ return -EINVAL; ++ ++ for (i = 0; i < 4; i++) { ++ ret = t3_cim_hac_read(adapter, (4 * i), &v); ++ if (ret) ++ goto out; ++ ++ *buf++ = v; ++ } ++ ++ for (i = 0; i < IOQ_ENTRIES; i++) { ++ u32 base_addr = 0x10 * (i + 1); ++ ++ for (j = 0; j < 4; j++) { ++ ret = t3_cim_hac_read(adapter, base_addr + 4 * j, &v); ++ if (ret) ++ goto out; ++ ++ *buf++ = v; ++ } ++ } ++ ++ *size = IOQ_ENTRIES * sizeof(struct t3_ioq_entry); ++ ++out: ++ return ret; ++} ++ +diff -r c6413c34aa41 drivers/net/cxgb3/t3cdev.h +--- a/drivers/net/cxgb3/t3cdev.h Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/t3cdev.h Tue Oct 06 09:38:00 2009 +0100 +@@ -1,33 +1,10 @@ + /* +- * Copyright (C) 2006-2007 Chelsio Communications. All rights reserved. ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: +- * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ + #ifndef _T3CDEV_H_ + #define _T3CDEV_H_ +@@ -50,21 +27,21 @@ + }; + + struct t3cdev { +- char name[T3CNAMSIZ]; /* T3C device name */ ++ char name[T3CNAMSIZ]; /* T3C device name */ + enum t3ctype type; +- struct list_head ofld_dev_list; /* for list linking */ +- struct net_device *lldev; /* LL dev associated with T3C messages */ +- struct proc_dir_entry *proc_dir; /* root of proc dir for this T3C */ ++ struct list_head ofld_dev_list; /* for list linking */ ++ struct net_device *lldev; /* LL dev associated with T3C messages */ ++ struct proc_dir_entry *proc_dir; /* root of proc dir for this T3C */ + int (*send)(struct t3cdev *dev, struct sk_buff *skb); + int (*recv)(struct t3cdev *dev, struct sk_buff **skb, int n); + int (*ctl)(struct t3cdev *dev, unsigned int req, void *data); + void (*neigh_update)(struct t3cdev *dev, struct neighbour *neigh); +- void *priv; /* driver private data */ +- void *l2opt; /* optional layer 2 data */ +- void *l3opt; /* optional layer 3 data */ +- void *l4opt; /* optional layer 4 data */ +- void *ulp; /* ulp stuff */ +- void *ulp_iscsi; /* ulp iscsi */ ++ void *priv; /* driver private data */ ++ void *l2opt; /* optional layer 2 data */ ++ void *l3opt; /* optional layer 3 data */ ++ void *l4opt; /* optional layer 4 data */ ++ void *ulp; /* ulp stuff */ ++ void *ulp_iscsi; /* ulp iscsi */ + }; + +-#endif /* _T3CDEV_H_ */ ++#endif /* _T3CDEV_H_ */ +diff -r c6413c34aa41 drivers/net/cxgb3/tcb.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cxgb3/tcb.h Tue Oct 06 09:38:00 2009 +0100 +@@ -0,0 +1,646 @@ ++/* This file is automatically generated --- do not edit */ ++ ++#ifndef _TCB_DEFS_H ++#define _TCB_DEFS_H ++ ++#define W_TCB_T_STATE 0 ++#define S_TCB_T_STATE 0 ++#define M_TCB_T_STATE 0xfULL ++#define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE) ++ ++#define W_TCB_TIMER 0 ++#define S_TCB_TIMER 4 ++#define M_TCB_TIMER 0x1ULL ++#define V_TCB_TIMER(x) ((x) << S_TCB_TIMER) ++ ++#define W_TCB_DACK_TIMER 0 ++#define S_TCB_DACK_TIMER 5 ++#define M_TCB_DACK_TIMER 0x1ULL ++#define V_TCB_DACK_TIMER(x) ((x) << S_TCB_DACK_TIMER) ++ ++#define W_TCB_DEL_FLAG 0 ++#define S_TCB_DEL_FLAG 6 ++#define M_TCB_DEL_FLAG 0x1ULL ++#define V_TCB_DEL_FLAG(x) ((x) << S_TCB_DEL_FLAG) ++ ++#define W_TCB_L2T_IX 0 ++#define S_TCB_L2T_IX 7 ++#define M_TCB_L2T_IX 0x7ffULL ++#define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX) ++ ++#define W_TCB_SMAC_SEL 0 ++#define S_TCB_SMAC_SEL 18 ++#define M_TCB_SMAC_SEL 0x3ULL ++#define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL) ++ ++#define W_TCB_TOS 0 ++#define S_TCB_TOS 20 ++#define M_TCB_TOS 0x3fULL ++#define V_TCB_TOS(x) ((x) << S_TCB_TOS) ++ ++#define W_TCB_MAX_RT 0 ++#define S_TCB_MAX_RT 26 ++#define M_TCB_MAX_RT 0xfULL ++#define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT) ++ ++#define W_TCB_T_RXTSHIFT 0 ++#define S_TCB_T_RXTSHIFT 30 ++#define M_TCB_T_RXTSHIFT 0xfULL ++#define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT) ++ ++#define W_TCB_T_DUPACKS 1 ++#define S_TCB_T_DUPACKS 2 ++#define M_TCB_T_DUPACKS 0xfULL ++#define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS) ++ ++#define W_TCB_T_MAXSEG 1 ++#define S_TCB_T_MAXSEG 6 ++#define M_TCB_T_MAXSEG 0xfULL ++#define V_TCB_T_MAXSEG(x) ((x) << S_TCB_T_MAXSEG) ++ ++#define W_TCB_T_FLAGS1 1 ++#define S_TCB_T_FLAGS1 10 ++#define M_TCB_T_FLAGS1 0xffffffffULL ++#define V_TCB_T_FLAGS1(x) ((x) << S_TCB_T_FLAGS1) ++ ++#define W_TCB_T_FLAGS2 2 ++#define S_TCB_T_FLAGS2 10 ++#define M_TCB_T_FLAGS2 0x7fULL ++#define V_TCB_T_FLAGS2(x) ((x) << S_TCB_T_FLAGS2) ++ ++#define W_TCB_SND_SCALE 2 ++#define S_TCB_SND_SCALE 17 ++#define M_TCB_SND_SCALE 0xfULL ++#define V_TCB_SND_SCALE(x) ((x) << S_TCB_SND_SCALE) ++ ++#define W_TCB_RCV_SCALE 2 ++#define S_TCB_RCV_SCALE 21 ++#define M_TCB_RCV_SCALE 0xfULL ++#define V_TCB_RCV_SCALE(x) ((x) << S_TCB_RCV_SCALE) ++ ++#define W_TCB_SND_UNA_RAW 2 ++#define S_TCB_SND_UNA_RAW 25 ++#define M_TCB_SND_UNA_RAW 0x7ffffffULL ++#define V_TCB_SND_UNA_RAW(x) ((x) << S_TCB_SND_UNA_RAW) ++ ++#define W_TCB_SND_NXT_RAW 3 ++#define S_TCB_SND_NXT_RAW 20 ++#define M_TCB_SND_NXT_RAW 0x7ffffffULL ++#define V_TCB_SND_NXT_RAW(x) ((x) << S_TCB_SND_NXT_RAW) ++ ++#define W_TCB_RCV_NXT 4 ++#define S_TCB_RCV_NXT 15 ++#define M_TCB_RCV_NXT 0xffffffffULL ++#define V_TCB_RCV_NXT(x) ((x) << S_TCB_RCV_NXT) ++ ++#define W_TCB_RCV_ADV 5 ++#define S_TCB_RCV_ADV 15 ++#define M_TCB_RCV_ADV 0xffffULL ++#define V_TCB_RCV_ADV(x) ((x) << S_TCB_RCV_ADV) ++ ++#define W_TCB_SND_MAX_RAW 5 ++#define S_TCB_SND_MAX_RAW 31 ++#define M_TCB_SND_MAX_RAW 0x7ffffffULL ++#define V_TCB_SND_MAX_RAW(x) ((x) << S_TCB_SND_MAX_RAW) ++ ++#define W_TCB_SND_CWND 6 ++#define S_TCB_SND_CWND 26 ++#define M_TCB_SND_CWND 0x7ffffffULL ++#define V_TCB_SND_CWND(x) ((x) << S_TCB_SND_CWND) ++ ++#define W_TCB_SND_SSTHRESH 7 ++#define S_TCB_SND_SSTHRESH 21 ++#define M_TCB_SND_SSTHRESH 0x7ffffffULL ++#define V_TCB_SND_SSTHRESH(x) ((x) << S_TCB_SND_SSTHRESH) ++ ++#define W_TCB_T_RTT_TS_RECENT_AGE 8 ++#define S_TCB_T_RTT_TS_RECENT_AGE 16 ++#define M_TCB_T_RTT_TS_RECENT_AGE 0xffffffffULL ++#define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE) ++ ++#define W_TCB_T_RTSEQ_RECENT 9 ++#define S_TCB_T_RTSEQ_RECENT 16 ++#define M_TCB_T_RTSEQ_RECENT 0xffffffffULL ++#define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT) ++ ++#define W_TCB_T_SRTT 10 ++#define S_TCB_T_SRTT 16 ++#define M_TCB_T_SRTT 0xffffULL ++#define V_TCB_T_SRTT(x) ((x) << S_TCB_T_SRTT) ++ ++#define W_TCB_T_RTTVAR 11 ++#define S_TCB_T_RTTVAR 0 ++#define M_TCB_T_RTTVAR 0xffffULL ++#define V_TCB_T_RTTVAR(x) ((x) << S_TCB_T_RTTVAR) ++ ++#define W_TCB_TS_LAST_ACK_SENT_RAW 11 ++#define S_TCB_TS_LAST_ACK_SENT_RAW 16 ++#define M_TCB_TS_LAST_ACK_SENT_RAW 0x7ffffffULL ++#define V_TCB_TS_LAST_ACK_SENT_RAW(x) ((x) << S_TCB_TS_LAST_ACK_SENT_RAW) ++ ++#define W_TCB_DIP 12 ++#define S_TCB_DIP 11 ++#define M_TCB_DIP 0xffffffffULL ++#define V_TCB_DIP(x) ((x) << S_TCB_DIP) ++ ++#define W_TCB_SIP 13 ++#define S_TCB_SIP 11 ++#define M_TCB_SIP 0xffffffffULL ++#define V_TCB_SIP(x) ((x) << S_TCB_SIP) ++ ++#define W_TCB_DP 14 ++#define S_TCB_DP 11 ++#define M_TCB_DP 0xffffULL ++#define V_TCB_DP(x) ((x) << S_TCB_DP) ++ ++#define W_TCB_SP 14 ++#define S_TCB_SP 27 ++#define M_TCB_SP 0xffffULL ++#define V_TCB_SP(x) ((x) << S_TCB_SP) ++ ++#define W_TCB_TIMESTAMP 15 ++#define S_TCB_TIMESTAMP 11 ++#define M_TCB_TIMESTAMP 0xffffffffULL ++#define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP) ++ ++#define W_TCB_TIMESTAMP_OFFSET 16 ++#define S_TCB_TIMESTAMP_OFFSET 11 ++#define M_TCB_TIMESTAMP_OFFSET 0xfULL ++#define V_TCB_TIMESTAMP_OFFSET(x) ((x) << S_TCB_TIMESTAMP_OFFSET) ++ ++#define W_TCB_TX_MAX 16 ++#define S_TCB_TX_MAX 15 ++#define M_TCB_TX_MAX 0xffffffffULL ++#define V_TCB_TX_MAX(x) ((x) << S_TCB_TX_MAX) ++ ++#define W_TCB_TX_HDR_PTR_RAW 17 ++#define S_TCB_TX_HDR_PTR_RAW 15 ++#define M_TCB_TX_HDR_PTR_RAW 0x1ffffULL ++#define V_TCB_TX_HDR_PTR_RAW(x) ((x) << S_TCB_TX_HDR_PTR_RAW) ++ ++#define W_TCB_TX_LAST_PTR_RAW 18 ++#define S_TCB_TX_LAST_PTR_RAW 0 ++#define M_TCB_TX_LAST_PTR_RAW 0x1ffffULL ++#define V_TCB_TX_LAST_PTR_RAW(x) ((x) << S_TCB_TX_LAST_PTR_RAW) ++ ++#define W_TCB_TX_COMPACT 18 ++#define S_TCB_TX_COMPACT 17 ++#define M_TCB_TX_COMPACT 0x1ULL ++#define V_TCB_TX_COMPACT(x) ((x) << S_TCB_TX_COMPACT) ++ ++#define W_TCB_RX_COMPACT 18 ++#define S_TCB_RX_COMPACT 18 ++#define M_TCB_RX_COMPACT 0x1ULL ++#define V_TCB_RX_COMPACT(x) ((x) << S_TCB_RX_COMPACT) ++ ++#define W_TCB_RCV_WND 18 ++#define S_TCB_RCV_WND 19 ++#define M_TCB_RCV_WND 0x7ffffffULL ++#define V_TCB_RCV_WND(x) ((x) << S_TCB_RCV_WND) ++ ++#define W_TCB_RX_HDR_OFFSET 19 ++#define S_TCB_RX_HDR_OFFSET 14 ++#define M_TCB_RX_HDR_OFFSET 0x7ffffffULL ++#define V_TCB_RX_HDR_OFFSET(x) ((x) << S_TCB_RX_HDR_OFFSET) ++ ++#define W_TCB_RX_FRAG0_START_IDX_RAW 20 ++#define S_TCB_RX_FRAG0_START_IDX_RAW 9 ++#define M_TCB_RX_FRAG0_START_IDX_RAW 0x7ffffffULL ++#define V_TCB_RX_FRAG0_START_IDX_RAW(x) ((x) << S_TCB_RX_FRAG0_START_IDX_RAW) ++ ++#define W_TCB_RX_FRAG1_START_IDX_OFFSET 21 ++#define S_TCB_RX_FRAG1_START_IDX_OFFSET 4 ++#define M_TCB_RX_FRAG1_START_IDX_OFFSET 0x7ffffffULL ++#define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) ((x) << S_TCB_RX_FRAG1_START_IDX_OFFSET) ++ ++#define W_TCB_RX_FRAG0_LEN 21 ++#define S_TCB_RX_FRAG0_LEN 31 ++#define M_TCB_RX_FRAG0_LEN 0x7ffffffULL ++#define V_TCB_RX_FRAG0_LEN(x) ((x) << S_TCB_RX_FRAG0_LEN) ++ ++#define W_TCB_RX_FRAG1_LEN 22 ++#define S_TCB_RX_FRAG1_LEN 26 ++#define M_TCB_RX_FRAG1_LEN 0x7ffffffULL ++#define V_TCB_RX_FRAG1_LEN(x) ((x) << S_TCB_RX_FRAG1_LEN) ++ ++#define W_TCB_NEWRENO_RECOVER 23 ++#define S_TCB_NEWRENO_RECOVER 21 ++#define M_TCB_NEWRENO_RECOVER 0x7ffffffULL ++#define V_TCB_NEWRENO_RECOVER(x) ((x) << S_TCB_NEWRENO_RECOVER) ++ ++#define W_TCB_PDU_HAVE_LEN 24 ++#define S_TCB_PDU_HAVE_LEN 16 ++#define M_TCB_PDU_HAVE_LEN 0x1ULL ++#define V_TCB_PDU_HAVE_LEN(x) ((x) << S_TCB_PDU_HAVE_LEN) ++ ++#define W_TCB_PDU_LEN 24 ++#define S_TCB_PDU_LEN 17 ++#define M_TCB_PDU_LEN 0xffffULL ++#define V_TCB_PDU_LEN(x) ((x) << S_TCB_PDU_LEN) ++ ++#define W_TCB_RX_QUIESCE 25 ++#define S_TCB_RX_QUIESCE 1 ++#define M_TCB_RX_QUIESCE 0x1ULL ++#define V_TCB_RX_QUIESCE(x) ((x) << S_TCB_RX_QUIESCE) ++ ++#define W_TCB_RX_PTR_RAW 25 ++#define S_TCB_RX_PTR_RAW 2 ++#define M_TCB_RX_PTR_RAW 0x1ffffULL ++#define V_TCB_RX_PTR_RAW(x) ((x) << S_TCB_RX_PTR_RAW) ++ ++#define W_TCB_CPU_NO 25 ++#define S_TCB_CPU_NO 19 ++#define M_TCB_CPU_NO 0x7fULL ++#define V_TCB_CPU_NO(x) ((x) << S_TCB_CPU_NO) ++ ++#define W_TCB_ULP_TYPE 25 ++#define S_TCB_ULP_TYPE 26 ++#define M_TCB_ULP_TYPE 0xfULL ++#define V_TCB_ULP_TYPE(x) ((x) << S_TCB_ULP_TYPE) ++ ++#define W_TCB_RX_FRAG1_PTR_RAW 25 ++#define S_TCB_RX_FRAG1_PTR_RAW 30 ++#define M_TCB_RX_FRAG1_PTR_RAW 0x1ffffULL ++#define V_TCB_RX_FRAG1_PTR_RAW(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW) ++ ++#define W_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 26 ++#define S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 15 ++#define M_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 0x7ffffffULL ++#define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW) ++ ++#define W_TCB_RX_FRAG2_PTR_RAW 27 ++#define S_TCB_RX_FRAG2_PTR_RAW 10 ++#define M_TCB_RX_FRAG2_PTR_RAW 0x1ffffULL ++#define V_TCB_RX_FRAG2_PTR_RAW(x) ((x) << S_TCB_RX_FRAG2_PTR_RAW) ++ ++#define W_TCB_RX_FRAG2_LEN_RAW 27 ++#define S_TCB_RX_FRAG2_LEN_RAW 27 ++#define M_TCB_RX_FRAG2_LEN_RAW 0x7ffffffULL ++#define V_TCB_RX_FRAG2_LEN_RAW(x) ((x) << S_TCB_RX_FRAG2_LEN_RAW) ++ ++#define W_TCB_RX_FRAG3_PTR_RAW 28 ++#define S_TCB_RX_FRAG3_PTR_RAW 22 ++#define M_TCB_RX_FRAG3_PTR_RAW 0x1ffffULL ++#define V_TCB_RX_FRAG3_PTR_RAW(x) ((x) << S_TCB_RX_FRAG3_PTR_RAW) ++ ++#define W_TCB_RX_FRAG3_LEN_RAW 29 ++#define S_TCB_RX_FRAG3_LEN_RAW 7 ++#define M_TCB_RX_FRAG3_LEN_RAW 0x7ffffffULL ++#define V_TCB_RX_FRAG3_LEN_RAW(x) ((x) << S_TCB_RX_FRAG3_LEN_RAW) ++ ++#define W_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 30 ++#define S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 2 ++#define M_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 0x7ffffffULL ++#define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW) ++ ++#define W_TCB_PDU_HDR_LEN 30 ++#define S_TCB_PDU_HDR_LEN 29 ++#define M_TCB_PDU_HDR_LEN 0xffULL ++#define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN) ++ ++#define W_TCB_SLUSH1 31 ++#define S_TCB_SLUSH1 5 ++#define M_TCB_SLUSH1 0x7ffffULL ++#define V_TCB_SLUSH1(x) ((x) << S_TCB_SLUSH1) ++ ++#define W_TCB_ULP_RAW 31 ++#define S_TCB_ULP_RAW 24 ++#define M_TCB_ULP_RAW 0xffULL ++#define V_TCB_ULP_RAW(x) ((x) << S_TCB_ULP_RAW) ++ ++#define W_TCB_DDP_RDMAP_VERSION 25 ++#define S_TCB_DDP_RDMAP_VERSION 30 ++#define M_TCB_DDP_RDMAP_VERSION 0x1ULL ++#define V_TCB_DDP_RDMAP_VERSION(x) ((x) << S_TCB_DDP_RDMAP_VERSION) ++ ++#define W_TCB_MARKER_ENABLE_RX 25 ++#define S_TCB_MARKER_ENABLE_RX 31 ++#define M_TCB_MARKER_ENABLE_RX 0x1ULL ++#define V_TCB_MARKER_ENABLE_RX(x) ((x) << S_TCB_MARKER_ENABLE_RX) ++ ++#define W_TCB_MARKER_ENABLE_TX 26 ++#define S_TCB_MARKER_ENABLE_TX 0 ++#define M_TCB_MARKER_ENABLE_TX 0x1ULL ++#define V_TCB_MARKER_ENABLE_TX(x) ((x) << S_TCB_MARKER_ENABLE_TX) ++ ++#define W_TCB_CRC_ENABLE 26 ++#define S_TCB_CRC_ENABLE 1 ++#define M_TCB_CRC_ENABLE 0x1ULL ++#define V_TCB_CRC_ENABLE(x) ((x) << S_TCB_CRC_ENABLE) ++ ++#define W_TCB_IRS_ULP 26 ++#define S_TCB_IRS_ULP 2 ++#define M_TCB_IRS_ULP 0x1ffULL ++#define V_TCB_IRS_ULP(x) ((x) << S_TCB_IRS_ULP) ++ ++#define W_TCB_ISS_ULP 26 ++#define S_TCB_ISS_ULP 11 ++#define M_TCB_ISS_ULP 0x1ffULL ++#define V_TCB_ISS_ULP(x) ((x) << S_TCB_ISS_ULP) ++ ++#define W_TCB_TX_PDU_LEN 26 ++#define S_TCB_TX_PDU_LEN 20 ++#define M_TCB_TX_PDU_LEN 0x3fffULL ++#define V_TCB_TX_PDU_LEN(x) ((x) << S_TCB_TX_PDU_LEN) ++ ++#define W_TCB_TX_PDU_OUT 27 ++#define S_TCB_TX_PDU_OUT 2 ++#define M_TCB_TX_PDU_OUT 0x1ULL ++#define V_TCB_TX_PDU_OUT(x) ((x) << S_TCB_TX_PDU_OUT) ++ ++#define W_TCB_CQ_IDX_SQ 27 ++#define S_TCB_CQ_IDX_SQ 3 ++#define M_TCB_CQ_IDX_SQ 0xffffULL ++#define V_TCB_CQ_IDX_SQ(x) ((x) << S_TCB_CQ_IDX_SQ) ++ ++#define W_TCB_CQ_IDX_RQ 27 ++#define S_TCB_CQ_IDX_RQ 19 ++#define M_TCB_CQ_IDX_RQ 0xffffULL ++#define V_TCB_CQ_IDX_RQ(x) ((x) << S_TCB_CQ_IDX_RQ) ++ ++#define W_TCB_QP_ID 28 ++#define S_TCB_QP_ID 3 ++#define M_TCB_QP_ID 0xffffULL ++#define V_TCB_QP_ID(x) ((x) << S_TCB_QP_ID) ++ ++#define W_TCB_PD_ID 28 ++#define S_TCB_PD_ID 19 ++#define M_TCB_PD_ID 0xffffULL ++#define V_TCB_PD_ID(x) ((x) << S_TCB_PD_ID) ++ ++#define W_TCB_STAG 29 ++#define S_TCB_STAG 3 ++#define M_TCB_STAG 0xffffffffULL ++#define V_TCB_STAG(x) ((x) << S_TCB_STAG) ++ ++#define W_TCB_RQ_START 30 ++#define S_TCB_RQ_START 3 ++#define M_TCB_RQ_START 0x3ffffffULL ++#define V_TCB_RQ_START(x) ((x) << S_TCB_RQ_START) ++ ++#define W_TCB_RQ_MSN 30 ++#define S_TCB_RQ_MSN 29 ++#define M_TCB_RQ_MSN 0x3ffULL ++#define V_TCB_RQ_MSN(x) ((x) << S_TCB_RQ_MSN) ++ ++#define W_TCB_RQ_MAX_OFFSET 31 ++#define S_TCB_RQ_MAX_OFFSET 7 ++#define M_TCB_RQ_MAX_OFFSET 0xfULL ++#define V_TCB_RQ_MAX_OFFSET(x) ((x) << S_TCB_RQ_MAX_OFFSET) ++ ++#define W_TCB_RQ_WRITE_PTR 31 ++#define S_TCB_RQ_WRITE_PTR 11 ++#define M_TCB_RQ_WRITE_PTR 0x3ffULL ++#define V_TCB_RQ_WRITE_PTR(x) ((x) << S_TCB_RQ_WRITE_PTR) ++ ++#define W_TCB_INB_WRITE_PERM 31 ++#define S_TCB_INB_WRITE_PERM 21 ++#define M_TCB_INB_WRITE_PERM 0x1ULL ++#define V_TCB_INB_WRITE_PERM(x) ((x) << S_TCB_INB_WRITE_PERM) ++ ++#define W_TCB_INB_READ_PERM 31 ++#define S_TCB_INB_READ_PERM 22 ++#define M_TCB_INB_READ_PERM 0x1ULL ++#define V_TCB_INB_READ_PERM(x) ((x) << S_TCB_INB_READ_PERM) ++ ++#define W_TCB_ORD_L_BIT_VLD 31 ++#define S_TCB_ORD_L_BIT_VLD 23 ++#define M_TCB_ORD_L_BIT_VLD 0x1ULL ++#define V_TCB_ORD_L_BIT_VLD(x) ((x) << S_TCB_ORD_L_BIT_VLD) ++ ++#define W_TCB_RDMAP_OPCODE 31 ++#define S_TCB_RDMAP_OPCODE 24 ++#define M_TCB_RDMAP_OPCODE 0xfULL ++#define V_TCB_RDMAP_OPCODE(x) ((x) << S_TCB_RDMAP_OPCODE) ++ ++#define W_TCB_TX_FLUSH 31 ++#define S_TCB_TX_FLUSH 28 ++#define M_TCB_TX_FLUSH 0x1ULL ++#define V_TCB_TX_FLUSH(x) ((x) << S_TCB_TX_FLUSH) ++ ++#define W_TCB_TX_OOS_RXMT 31 ++#define S_TCB_TX_OOS_RXMT 29 ++#define M_TCB_TX_OOS_RXMT 0x1ULL ++#define V_TCB_TX_OOS_RXMT(x) ((x) << S_TCB_TX_OOS_RXMT) ++ ++#define W_TCB_TX_OOS_TXMT 31 ++#define S_TCB_TX_OOS_TXMT 30 ++#define M_TCB_TX_OOS_TXMT 0x1ULL ++#define V_TCB_TX_OOS_TXMT(x) ((x) << S_TCB_TX_OOS_TXMT) ++ ++#define W_TCB_SLUSH_AUX2 31 ++#define S_TCB_SLUSH_AUX2 31 ++#define M_TCB_SLUSH_AUX2 0x1ULL ++#define V_TCB_SLUSH_AUX2(x) ((x) << S_TCB_SLUSH_AUX2) ++ ++#define W_TCB_RX_FRAG1_PTR_RAW2 25 ++#define S_TCB_RX_FRAG1_PTR_RAW2 30 ++#define M_TCB_RX_FRAG1_PTR_RAW2 0x1ffffULL ++#define V_TCB_RX_FRAG1_PTR_RAW2(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW2) ++ ++#define W_TCB_RX_DDP_FLAGS 26 ++#define S_TCB_RX_DDP_FLAGS 15 ++#define M_TCB_RX_DDP_FLAGS 0xffffULL ++#define V_TCB_RX_DDP_FLAGS(x) ((x) << S_TCB_RX_DDP_FLAGS) ++ ++#define W_TCB_SLUSH_AUX3 26 ++#define S_TCB_SLUSH_AUX3 31 ++#define M_TCB_SLUSH_AUX3 0x1ffULL ++#define V_TCB_SLUSH_AUX3(x) ((x) << S_TCB_SLUSH_AUX3) ++ ++#define W_TCB_RX_DDP_BUF0_OFFSET 27 ++#define S_TCB_RX_DDP_BUF0_OFFSET 8 ++#define M_TCB_RX_DDP_BUF0_OFFSET 0x3fffffULL ++#define V_TCB_RX_DDP_BUF0_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF0_OFFSET) ++ ++#define W_TCB_RX_DDP_BUF0_LEN 27 ++#define S_TCB_RX_DDP_BUF0_LEN 30 ++#define M_TCB_RX_DDP_BUF0_LEN 0x3fffffULL ++#define V_TCB_RX_DDP_BUF0_LEN(x) ((x) << S_TCB_RX_DDP_BUF0_LEN) ++ ++#define W_TCB_RX_DDP_BUF1_OFFSET 28 ++#define S_TCB_RX_DDP_BUF1_OFFSET 20 ++#define M_TCB_RX_DDP_BUF1_OFFSET 0x3fffffULL ++#define V_TCB_RX_DDP_BUF1_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF1_OFFSET) ++ ++#define W_TCB_RX_DDP_BUF1_LEN 29 ++#define S_TCB_RX_DDP_BUF1_LEN 10 ++#define M_TCB_RX_DDP_BUF1_LEN 0x3fffffULL ++#define V_TCB_RX_DDP_BUF1_LEN(x) ((x) << S_TCB_RX_DDP_BUF1_LEN) ++ ++#define W_TCB_RX_DDP_BUF0_TAG 30 ++#define S_TCB_RX_DDP_BUF0_TAG 0 ++#define M_TCB_RX_DDP_BUF0_TAG 0xffffffffULL ++#define V_TCB_RX_DDP_BUF0_TAG(x) ((x) << S_TCB_RX_DDP_BUF0_TAG) ++ ++#define W_TCB_RX_DDP_BUF1_TAG 31 ++#define S_TCB_RX_DDP_BUF1_TAG 0 ++#define M_TCB_RX_DDP_BUF1_TAG 0xffffffffULL ++#define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG) ++ ++#define S_TF_DACK 10 ++#define V_TF_DACK(x) ((x) << S_TF_DACK) ++ ++#define S_TF_NAGLE 11 ++#define V_TF_NAGLE(x) ((x) << S_TF_NAGLE) ++ ++#define S_TF_RECV_SCALE 12 ++#define V_TF_RECV_SCALE(x) ((x) << S_TF_RECV_SCALE) ++ ++#define S_TF_RECV_TSTMP 13 ++#define V_TF_RECV_TSTMP(x) ((x) << S_TF_RECV_TSTMP) ++ ++#define S_TF_RECV_SACK 14 ++#define V_TF_RECV_SACK(x) ((x) << S_TF_RECV_SACK) ++ ++#define S_TF_TURBO 15 ++#define V_TF_TURBO(x) ((x) << S_TF_TURBO) ++ ++#define S_TF_KEEPALIVE 16 ++#define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE) ++ ++#define S_TF_TCAM_BYPASS 17 ++#define V_TF_TCAM_BYPASS(x) ((x) << S_TF_TCAM_BYPASS) ++ ++#define S_TF_CORE_FIN 18 ++#define V_TF_CORE_FIN(x) ((x) << S_TF_CORE_FIN) ++ ++#define S_TF_CORE_MORE 19 ++#define V_TF_CORE_MORE(x) ((x) << S_TF_CORE_MORE) ++ ++#define S_TF_MIGRATING 20 ++#define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING) ++ ++#define S_TF_ACTIVE_OPEN 21 ++#define V_TF_ACTIVE_OPEN(x) ((x) << S_TF_ACTIVE_OPEN) ++ ++#define S_TF_ASK_MODE 22 ++#define V_TF_ASK_MODE(x) ((x) << S_TF_ASK_MODE) ++ ++#define S_TF_NON_OFFLOAD 23 ++#define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD) ++ ++#define S_TF_MOD_SCHD 24 ++#define V_TF_MOD_SCHD(x) ((x) << S_TF_MOD_SCHD) ++ ++#define S_TF_MOD_SCHD_REASON0 25 ++#define V_TF_MOD_SCHD_REASON0(x) ((x) << S_TF_MOD_SCHD_REASON0) ++ ++#define S_TF_MOD_SCHD_REASON1 26 ++#define V_TF_MOD_SCHD_REASON1(x) ((x) << S_TF_MOD_SCHD_REASON1) ++ ++#define S_TF_MOD_SCHD_RX 27 ++#define V_TF_MOD_SCHD_RX(x) ((x) << S_TF_MOD_SCHD_RX) ++ ++#define S_TF_CORE_PUSH 28 ++#define V_TF_CORE_PUSH(x) ((x) << S_TF_CORE_PUSH) ++ ++#define S_TF_RCV_COALESCE_ENABLE 29 ++#define V_TF_RCV_COALESCE_ENABLE(x) ((x) << S_TF_RCV_COALESCE_ENABLE) ++ ++#define S_TF_RCV_COALESCE_PUSH 30 ++#define V_TF_RCV_COALESCE_PUSH(x) ((x) << S_TF_RCV_COALESCE_PUSH) ++ ++#define S_TF_RCV_COALESCE_LAST_PSH 31 ++#define V_TF_RCV_COALESCE_LAST_PSH(x) ((x) << S_TF_RCV_COALESCE_LAST_PSH) ++ ++#define S_TF_RCV_COALESCE_HEARTBEAT 32 ++#define V_TF_RCV_COALESCE_HEARTBEAT(x) ((x) << S_TF_RCV_COALESCE_HEARTBEAT) ++ ++#define S_TF_LOCK_TID 33 ++#define V_TF_LOCK_TID(x) ((x) << S_TF_LOCK_TID) ++ ++#define S_TF_DACK_MSS 34 ++#define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS) ++ ++#define S_TF_CCTRL_SEL0 35 ++#define V_TF_CCTRL_SEL0(x) ((x) << S_TF_CCTRL_SEL0) ++ ++#define S_TF_CCTRL_SEL1 36 ++#define V_TF_CCTRL_SEL1(x) ((x) << S_TF_CCTRL_SEL1) ++ ++#define S_TF_TCP_NEWRENO_FAST_RECOVERY 37 ++#define V_TF_TCP_NEWRENO_FAST_RECOVERY(x) ((x) << S_TF_TCP_NEWRENO_FAST_RECOVERY) ++ ++#define S_TF_TX_PACE_AUTO 38 ++#define V_TF_TX_PACE_AUTO(x) ((x) << S_TF_TX_PACE_AUTO) ++ ++#define S_TF_PEER_FIN_HELD 39 ++#define V_TF_PEER_FIN_HELD(x) ((x) << S_TF_PEER_FIN_HELD) ++ ++#define S_TF_CORE_URG 40 ++#define V_TF_CORE_URG(x) ((x) << S_TF_CORE_URG) ++ ++#define S_TF_RDMA_ERROR 41 ++#define V_TF_RDMA_ERROR(x) ((x) << S_TF_RDMA_ERROR) ++ ++#define S_TF_SSWS_DISABLED 42 ++#define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED) ++ ++#define S_TF_DUPACK_COUNT_ODD 43 ++#define V_TF_DUPACK_COUNT_ODD(x) ((x) << S_TF_DUPACK_COUNT_ODD) ++ ++#define S_TF_TX_CHANNEL 44 ++#define V_TF_TX_CHANNEL(x) ((x) << S_TF_TX_CHANNEL) ++ ++#define S_TF_RX_CHANNEL 45 ++#define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL) ++ ++#define S_TF_TX_PACE_FIXED 46 ++#define V_TF_TX_PACE_FIXED(x) ((x) << S_TF_TX_PACE_FIXED) ++ ++#define S_TF_RDMA_FLM_ERROR 47 ++#define V_TF_RDMA_FLM_ERROR(x) ((x) << S_TF_RDMA_FLM_ERROR) ++ ++#define S_TF_RX_FLOW_CONTROL_DISABLE 48 ++#define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE) ++ ++#define S_TF_DDP_INDICATE_OUT 15 ++#define V_TF_DDP_INDICATE_OUT(x) ((x) << S_TF_DDP_INDICATE_OUT) ++ ++#define S_TF_DDP_ACTIVE_BUF 16 ++#define V_TF_DDP_ACTIVE_BUF(x) ((x) << S_TF_DDP_ACTIVE_BUF) ++ ++#define S_TF_DDP_BUF0_VALID 17 ++#define V_TF_DDP_BUF0_VALID(x) ((x) << S_TF_DDP_BUF0_VALID) ++ ++#define S_TF_DDP_BUF1_VALID 18 ++#define V_TF_DDP_BUF1_VALID(x) ((x) << S_TF_DDP_BUF1_VALID) ++ ++#define S_TF_DDP_BUF0_INDICATE 19 ++#define V_TF_DDP_BUF0_INDICATE(x) ((x) << S_TF_DDP_BUF0_INDICATE) ++ ++#define S_TF_DDP_BUF1_INDICATE 20 ++#define V_TF_DDP_BUF1_INDICATE(x) ((x) << S_TF_DDP_BUF1_INDICATE) ++ ++#define S_TF_DDP_PUSH_DISABLE_0 21 ++#define V_TF_DDP_PUSH_DISABLE_0(x) ((x) << S_TF_DDP_PUSH_DISABLE_0) ++ ++#define S_TF_DDP_PUSH_DISABLE_1 22 ++#define V_TF_DDP_PUSH_DISABLE_1(x) ((x) << S_TF_DDP_PUSH_DISABLE_1) ++ ++#define S_TF_DDP_OFF 23 ++#define V_TF_DDP_OFF(x) ((x) << S_TF_DDP_OFF) ++ ++#define S_TF_DDP_WAIT_FRAG 24 ++#define V_TF_DDP_WAIT_FRAG(x) ((x) << S_TF_DDP_WAIT_FRAG) ++ ++#define S_TF_DDP_BUF_INF 25 ++#define V_TF_DDP_BUF_INF(x) ((x) << S_TF_DDP_BUF_INF) ++ ++#define S_TF_DDP_RX2TX 26 ++#define V_TF_DDP_RX2TX(x) ((x) << S_TF_DDP_RX2TX) ++ ++#define S_TF_DDP_BUF0_FLUSH 27 ++#define V_TF_DDP_BUF0_FLUSH(x) ((x) << S_TF_DDP_BUF0_FLUSH) ++ ++#define S_TF_DDP_BUF1_FLUSH 28 ++#define V_TF_DDP_BUF1_FLUSH(x) ((x) << S_TF_DDP_BUF1_FLUSH) ++ ++#define S_TF_DDP_PSH_NO_INVALIDATE0 29 ++#define V_TF_DDP_PSH_NO_INVALIDATE0(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE0) ++ ++#define S_TF_DDP_PSH_NO_INVALIDATE1 30 ++#define V_TF_DDP_PSH_NO_INVALIDATE1(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE1) ++ ++#endif /* _TCB_DEFS_H */ +diff -r c6413c34aa41 drivers/net/cxgb3/tn1010.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cxgb3/tn1010.c Tue Oct 06 09:38:00 2009 +0100 +@@ -0,0 +1,197 @@ ++/* ++ * This file is part of the Chelsio T3 Ethernet driver. ++ * ++ * Copyright (C) 2009 Chelsio Communications. All rights reserved. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. ++ */ ++ ++#include "common.h" ++ ++/* TN1010 PHY specific registers. */ ++enum { ++ TN1010_VEND1_STAT = 1, ++}; ++ ++/* IEEE auto-negotiation 10GBASE-T registers */ ++enum { ++ ANEG_ADVER = 16, ++ ANEG_LPA = 19, ++ ANEG_10G_CTRL = 32, ++ ANEG_10G_STAT = 33 ++}; ++ ++#define ADVERTISE_ENPAGE (1 << 12) ++#define ADVERTISE_10000FULL (1 << 12) ++#define ADVERTISE_LOOP_TIMING (1 << 0) ++ ++/* vendor specific status register fields */ ++#define F_XS_LANE_ALIGN_STAT (1 << 0) ++#define F_PCS_BLK_LOCK (1 << 1) ++#define F_PMD_SIGNAL_OK (1 << 2) ++#define F_LINK_STAT (1 << 3) ++#define F_ANEG_SPEED_1G (1 << 4) ++#define F_ANEG_MASTER (1 << 5) ++ ++#define S_ANEG_STAT 6 ++#define M_ANEG_STAT 0x3 ++#define G_ANEG_STAT(x) (((x) >> S_ANEG_STAT) & M_ANEG_STAT) ++ ++enum { /* autonegotiation status */ ++ ANEG_IN_PROGR = 0, ++ ANEG_COMPLETE = 1, ++ ANEG_FAILED = 3 ++}; ++ ++/* ++ * Reset the PHY. May take up to 500ms to complete. ++ */ ++static int tn1010_reset(struct cphy *phy, int wait) ++{ ++ int err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait); ++ msleep(500); ++ return err; ++} ++ ++static int tn1010_power_down(struct cphy *phy, int enable) ++{ ++ return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, ++ BMCR_PDOWN, enable ? BMCR_PDOWN : 0); ++} ++ ++static int tn1010_autoneg_enable(struct cphy *phy) ++{ ++ int err; ++ ++ err = tn1010_power_down(phy, 0); ++ if (!err) ++ err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR, 0, ++ BMCR_ANENABLE | BMCR_ANRESTART); ++ return err; ++} ++ ++static int tn1010_autoneg_restart(struct cphy *phy) ++{ ++ int err; ++ ++ err = tn1010_power_down(phy, 0); ++ if (!err) ++ err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR, 0, ++ BMCR_ANRESTART); ++ return err; ++} ++ ++static int tn1010_advertise(struct cphy *phy, unsigned int advert) ++{ ++ int err, val; ++ ++ if (!(advert & ADVERTISED_1000baseT_Full)) ++ return -EINVAL; /* PHY can't disable 1000BASE-T */ ++ ++ val = ADVERTISE_CSMA | ADVERTISE_ENPAGE | ADVERTISE_NPAGE; ++ if (advert & ADVERTISED_Pause) ++ val |= ADVERTISE_PAUSE_CAP; ++ if (advert & ADVERTISED_Asym_Pause) ++ val |= ADVERTISE_PAUSE_ASYM; ++ err = mdio_write(phy, MDIO_DEV_ANEG, ANEG_ADVER, val); ++ if (err) ++ return err; ++ ++ val = (advert & ADVERTISED_10000baseT_Full) ? ADVERTISE_10000FULL : 0; ++ return mdio_write(phy, MDIO_DEV_ANEG, ANEG_10G_CTRL, val | ++ ADVERTISE_LOOP_TIMING); ++} ++ ++static int tn1010_get_link_status(struct cphy *phy, int *link_ok, ++ int *speed, int *duplex, int *fc) ++{ ++ unsigned int status, lpa, adv; ++ int err, sp = -1, pause = 0; ++ ++ err = mdio_read(phy, MDIO_DEV_VEND1, TN1010_VEND1_STAT, &status); ++ if (err) ++ return err; ++ ++ if (link_ok) ++ *link_ok = (status & F_LINK_STAT) != 0; ++ ++ if (G_ANEG_STAT(status) == ANEG_COMPLETE) { ++ sp = (status & F_ANEG_SPEED_1G) ? SPEED_1000 : SPEED_10000; ++ ++ if (fc) { ++ err = mdio_read(phy, MDIO_DEV_ANEG, ANEG_LPA, &lpa); ++ if (!err) ++ err = mdio_read(phy, MDIO_DEV_ANEG, ANEG_ADVER, ++ &adv); ++ if (err) ++ return err; ++ ++ if (lpa & adv & ADVERTISE_PAUSE_CAP) ++ pause = PAUSE_RX | PAUSE_TX; ++ else if ((lpa & ADVERTISE_PAUSE_CAP) && ++ (lpa & ADVERTISE_PAUSE_ASYM) && ++ (adv & ADVERTISE_PAUSE_ASYM)) ++ pause = PAUSE_TX; ++ else if ((lpa & ADVERTISE_PAUSE_ASYM) && ++ (adv & ADVERTISE_PAUSE_CAP)) ++ pause = PAUSE_RX; ++ } ++ } ++ if (speed) ++ *speed = sp; ++ if (duplex) ++ *duplex = DUPLEX_FULL; ++ if (fc) ++ *fc = pause; ++ return 0; ++} ++ ++int tn1010_set_speed_duplex(struct cphy *phy, int speed, int duplex) ++{ ++ return -EINVAL; /* require autoneg */ ++} ++ ++#ifdef C99_NOT_SUPPORTED ++static struct cphy_ops tn1010_ops = { ++ tn1010_reset, ++ t3_phy_lasi_intr_enable, ++ t3_phy_lasi_intr_disable, ++ t3_phy_lasi_intr_clear, ++ t3_phy_lasi_intr_handler, ++ tn1010_autoneg_enable, ++ tn1010_autoneg_restart, ++ tn1010_advertise, ++ NULL, ++ tn1010_set_speed_duplex, ++ tn1010_get_link_status, ++ tn1010_power_down, ++}; ++#else ++static struct cphy_ops tn1010_ops = { ++ .reset = tn1010_reset, ++ .intr_enable = t3_phy_lasi_intr_enable, ++ .intr_disable = t3_phy_lasi_intr_disable, ++ .intr_clear = t3_phy_lasi_intr_clear, ++ .intr_handler = t3_phy_lasi_intr_handler, ++ .autoneg_enable = tn1010_autoneg_enable, ++ .autoneg_restart = tn1010_autoneg_restart, ++ .advertise = tn1010_advertise, ++ .set_speed_duplex = tn1010_set_speed_duplex, ++ .get_link_status = tn1010_get_link_status, ++ .power_down = tn1010_power_down, ++}; ++#endif ++ ++int t3_tn1010_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops) ++{ ++ cphy_init(&pinfo->phy, pinfo->adapter, pinfo, phy_addr, &tn1010_ops, mdio_ops, ++ SUPPORTED_1000baseT_Full | SUPPORTED_10000baseT_Full | ++ SUPPORTED_Autoneg | SUPPORTED_AUI | SUPPORTED_TP, ++ "1000/10GBASE-T"); ++ msleep(500); /* PHY needs up to 500ms to start responding to MDIO */ ++ return 0; ++} +diff -r c6413c34aa41 drivers/net/cxgb3/trace.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cxgb3/trace.c Tue Oct 06 09:38:00 2009 +0100 +@@ -0,0 +1,161 @@ ++/* ++ * This file is part of the Chelsio T3 Ethernet driver for Linux. ++ * ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. ++ */ ++ ++/* ++ * Routines to allocate and free T3 trace buffers. ++ * ++ * Authors: ++ * Felix Marti ++ * ++ * The code suffers from a trace buffer count increment race, which might ++ * lead to entries being overwritten. I don't really care about this, ++ * because the trace buffer is a simple debug/perfomance tuning aid. ++ * ++ * Trace buffers are created in /proc, which needs to be fixed. ++ */ ++ ++#include "trace.h" ++ ++#ifdef T3_TRACE ++#include ++#include ++#include ++#include ++#include "cxgb3_compat.h" ++ ++/* ++ * SEQ OPS ++ */ ++static void *t3_trace_seq_start(struct seq_file *seq, loff_t *pos) ++{ ++ struct trace_buf *tb = seq->private; ++ struct trace_entry *e = NULL; ++ unsigned int start, count; ++ ++ if (tb->idx > tb->capacity) { ++ start = tb->idx & (tb->capacity - 1); ++ count = tb->capacity; ++ } else { ++ start = 0; ++ count = tb->idx; ++ } ++ ++ if (*pos < count) ++ e = &tb->ep[(start + *pos) & (tb->capacity - 1)]; ++ ++ return e; ++} ++ ++static void *t3_trace_seq_next(struct seq_file *seq, void *v, loff_t *pos) ++{ ++ struct trace_buf *tb = seq->private; ++ struct trace_entry *e = v; ++ unsigned int count = min(tb->idx, tb->capacity); ++ ++ if (++*pos < count) { ++ e++; ++ if (e >= &tb->ep[tb->capacity]) ++ e = tb->ep; ++ } else ++ e = NULL; ++ ++ return e; ++} ++ ++static void t3_trace_seq_stop(struct seq_file *seq, void *v) ++{ ++} ++ ++static int t3_trace_seq_show(struct seq_file *seq, void *v) ++{ ++ struct trace_entry *ep = v; ++ ++ seq_printf(seq, "%016llx ", (unsigned long long) ep->tsc); ++ seq_printf(seq, ep->fmt, ep->param[0], ep->param[1], ep->param[2], ++ ep->param[3], ep->param[4], ep->param[5]); ++ seq_printf(seq, "\n"); ++ ++ return 0; ++} ++ ++static struct seq_operations t3_trace_seq_ops = { ++ .start = t3_trace_seq_start, ++ .next = t3_trace_seq_next, ++ .stop = t3_trace_seq_stop, ++ .show = t3_trace_seq_show ++}; ++ ++/* ++ * FILE OPS ++ */ ++static int t3_trace_seq_open(struct inode *inode, struct file *file) ++{ ++ int rc = seq_open(file, &t3_trace_seq_ops); ++ ++ if (!rc) { ++ struct seq_file *seq = file->private_data; ++ ++ seq->private = inode->i_private; ++ } ++ ++ return rc; ++} ++ ++static struct file_operations t3_trace_seq_fops = { ++ .owner = THIS_MODULE, ++ .open = t3_trace_seq_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = seq_release ++}; ++ ++/* ++ * TRACEBUFFER API ++ */ ++struct trace_buf *t3_trace_alloc(struct dentry *root, const char *name, ++ unsigned int capacity) ++{ ++ struct trace_buf *tb; ++ unsigned int size; ++ ++ if (!name || !capacity) ++ return NULL; ++ if (capacity & (capacity - 1)) /* require power of 2 */ ++ return NULL; ++ ++ size = sizeof(*tb) + sizeof(struct trace_entry) * capacity; ++ tb = kmalloc(size, GFP_KERNEL); ++ if (!tb) ++ return NULL; ++ ++ memset(tb, 0, size); ++ tb->capacity = capacity; ++ tb->debugfs_dentry = debugfs_create_file(name, S_IFREG | S_IRUGO, root, ++ tb, &t3_trace_seq_fops); ++ if (!tb->debugfs_dentry) { ++ kfree(tb); ++ return NULL; ++ } ++ ++ return tb; ++} ++ ++void t3_trace_free(struct trace_buf *tb) ++{ ++ if (tb) { ++ if (tb->debugfs_dentry) ++ debugfs_remove(tb->debugfs_dentry); ++ kfree(tb); ++ } ++} ++EXPORT_SYMBOL(t3_trace_alloc); ++EXPORT_SYMBOL(t3_trace_free); ++#endif /* T3_TRACE */ +diff -r c6413c34aa41 drivers/net/cxgb3/trace.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cxgb3/trace.h Tue Oct 06 09:38:00 2009 +0100 +@@ -0,0 +1,122 @@ ++/* ++ * This file is part of the Chelsio T3 Ethernet driver for Linux. ++ * ++ * Copyright (C) 2003-2009 Chelsio Communications. All rights reserved. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. ++ */ ++ ++/* ++ * Definitions and inline functions for the T3 trace buffers. ++ * ++ * Authors: ++ * Felix Marti ++ */ ++ ++#ifndef __T3_TRACE_H__ ++#define __T3_TRACE_H__ ++ ++#if defined(T3_TRACE) || defined(T3_TRACE_TOM) ++ ++#include ++#include ++ ++#define T3_TRACE_NUM_PARAM 6 ++ ++typedef unsigned long tracearg_t; ++ ++#define T3_TRACE0(b, s) \ ++ if ((b) != NULL) \ ++ (void) t3_trace((b), (s)); ++#define T3_TRACE1(b, s, p0) \ ++ if ((b) != NULL) { \ ++ tracearg_t *_p = t3_trace((b), (s)); \ ++ _p[0] = (tracearg_t) (p0); \ ++ } ++#define T3_TRACE2(b, s, p0, p1) \ ++ if ((b) != NULL) { \ ++ tracearg_t *_p = t3_trace((b), (s)); \ ++ _p[0] = (tracearg_t) (p0); \ ++ _p[1] = (tracearg_t) (p1); \ ++ } ++#define T3_TRACE3(b, s, p0, p1, p2) \ ++ if ((b) != NULL) { \ ++ tracearg_t *_p = t3_trace((b), (s)); \ ++ _p[0] = (tracearg_t) (p0); \ ++ _p[1] = (tracearg_t) (p1); \ ++ _p[2] = (tracearg_t) (p2); \ ++ } ++#define T3_TRACE4(b, s, p0, p1, p2, p3) \ ++ if ((b) != NULL) { \ ++ tracearg_t *_p = t3_trace((b), (s)); \ ++ _p[0] = (tracearg_t) (p0); \ ++ _p[1] = (tracearg_t) (p1); \ ++ _p[2] = (tracearg_t) (p2); \ ++ _p[3] = (tracearg_t) (p3); \ ++ } ++#define T3_TRACE5(b, s, p0, p1, p2, p3, p4) \ ++ if ((b) != NULL) { \ ++ tracearg_t *_p = t3_trace((b), (s)); \ ++ _p[0] = (tracearg_t) (p0); \ ++ _p[1] = (tracearg_t) (p1); \ ++ _p[2] = (tracearg_t) (p2); \ ++ _p[3] = (tracearg_t) (p3); \ ++ _p[4] = (tracearg_t) (p4); \ ++ } ++#define T3_TRACE6(b, s, p0, p1, p2, p3, p4, p5) \ ++ if ((b) != NULL) { \ ++ tracearg_t *_p = t3_trace((b), (s)); \ ++ _p[0] = (tracearg_t) (p0); \ ++ _p[1] = (tracearg_t) (p1); \ ++ _p[2] = (tracearg_t) (p2); \ ++ _p[3] = (tracearg_t) (p3); \ ++ _p[4] = (tracearg_t) (p4); \ ++ _p[5] = (tracearg_t) (p5); \ ++ } ++ ++struct trace_entry { ++ cycles_t tsc; ++ char *fmt; ++ tracearg_t param[T3_TRACE_NUM_PARAM]; ++}; ++ ++struct dentry; ++ ++struct trace_buf { ++ unsigned int capacity; /* size of ring buffer */ ++ unsigned int idx; /* index of next entry to write */ ++ struct dentry *debugfs_dentry; ++ struct trace_entry ep[0]; /* the ring buffer */ ++}; ++ ++static inline unsigned long *t3_trace(struct trace_buf *tb, char *fmt) ++{ ++ struct trace_entry *ep = &tb->ep[tb->idx++ & (tb->capacity - 1)]; ++ ++ ep->fmt = fmt; ++ ep->tsc = get_cycles(); ++ ++ return (unsigned long *) &ep->param[0]; ++} ++ ++struct trace_buf *t3_trace_alloc(struct dentry *root, const char *name, ++ unsigned int capacity); ++void t3_trace_free(struct trace_buf *tb); ++ ++#else ++#define T3_TRACE0(b, s) ++#define T3_TRACE1(b, s, p0) ++#define T3_TRACE2(b, s, p0, p1) ++#define T3_TRACE3(b, s, p0, p1, p2) ++#define T3_TRACE4(b, s, p0, p1, p2, p3) ++#define T3_TRACE5(b, s, p0, p1, p2, p3, p4) ++#define T3_TRACE6(b, s, p0, p1, p2, p3, p4, p5) ++ ++#define t3_trace_alloc(root, name, capacity) NULL ++#define t3_trace_free(tb) ++#endif ++ ++#endif /* __T3_TRACE_H__ */ +diff -r c6413c34aa41 drivers/net/cxgb3/version.h +--- a/drivers/net/cxgb3/version.h Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/version.h Tue Oct 06 09:38:00 2009 +0100 +@@ -1,44 +1,26 @@ +-/* +- * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved. +- * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: +- * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- */ +-/* $Date: 2006/10/31 18:57:51 $ $RCSfile: version.h,v $ $Revision: 1.3 $ */ ++/***************************************************************************** ++ * * ++ * File: * ++ * version.h * ++ * * ++ * Description: * ++ * Chelsio driver version defines. * ++ * * ++ * Copyright (c) 2003 - 2009 Chelsio Communications, Inc. * ++ * All rights reserved. * ++ * * ++ * Maintainers: maintainers@chelsio.com * ++ * * ++ * http://www.chelsio.com * ++ * * ++ ****************************************************************************/ ++/* $Date: 2008/08/07 02:39:03 $ $RCSfile: version.h,v $ $Revision: 1.5.4.1 $ */ + #ifndef __CHELSIO_VERSION_H + #define __CHELSIO_VERSION_H + #define DRV_DESC "Chelsio T3 Network Driver" + #define DRV_NAME "cxgb3" +-/* Driver version */ +-#define DRV_VERSION "1.1.0-ko" +- +-/* Firmware version */ +-#define FW_VERSION_MAJOR 7 +-#define FW_VERSION_MINOR 0 +-#define FW_VERSION_MICRO 0 +-#endif /* __CHELSIO_VERSION_H */ ++// Driver version ++#ifndef DRV_VERSION ++#define DRV_VERSION "1.3.1.7" ++#endif ++#endif //__CHELSIO_VERSION_H +diff -r c6413c34aa41 drivers/net/cxgb3/vsc7323.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/cxgb3/vsc7323.c Tue Oct 06 09:38:00 2009 +0100 +@@ -0,0 +1,339 @@ ++/* ++ * This file is part of the Chelsio T3 Ethernet driver. ++ * ++ * Copyright (C) 2007-2009 Chelsio Communications. All rights reserved. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. ++ */ ++ ++#include "common.h" ++ ++enum { ++ ELMR_ADDR = 0, ++ ELMR_STAT = 1, ++ ELMR_DATA_LO = 2, ++ ELMR_DATA_HI = 3, ++ ++ ELMR_THRES0 = 0xe000, ++ ELMR_BW = 0xe00c, ++ ELMR_FIFO_SZ = 0xe00d, ++ ELMR_STATS = 0xf000, ++ ++ ELMR_MDIO_ADDR = 10 ++}; ++ ++#define VSC_REG(block, subblock, reg) \ ++ ((reg) | ((subblock) << 8) | ((block) << 12)) ++ ++int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n) ++{ ++ int ret; ++ const struct mdio_ops *mo = adapter_info(adap)->mdio_ops; ++ ++ ELMR_LOCK(adap); ++ ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_ADDR, start); ++ for ( ; !ret && n; n--, vals++) { ++ ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_LO, ++ *vals & 0xffff); ++ if (!ret) ++ ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_HI, ++ *vals >> 16); ++ } ++ ELMR_UNLOCK(adap); ++ return ret; ++} ++ ++static int elmr_write(adapter_t *adap, int addr, u32 val) ++{ ++ return t3_elmr_blk_write(adap, addr, &val, 1); ++} ++ ++int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n) ++{ ++ int i, ret; ++ unsigned int v; ++ const struct mdio_ops *mo = adapter_info(adap)->mdio_ops; ++ ++ ELMR_LOCK(adap); ++ ++ ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_ADDR, start); ++ if (ret) ++ goto out; ++ ++ for (i = 0; i < 5; i++) { ++ ret = mo->read(adap, ELMR_MDIO_ADDR, 0, ELMR_STAT, &v); ++ if (ret) ++ goto out; ++ if (v == 1) ++ break; ++ udelay(5); ++ } ++ if (v != 1) { ++ ret = -ETIME; ++ goto out; ++ } ++ ++ for ( ; !ret && n; n--, vals++) { ++ ret = mo->read(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_LO, vals); ++ if (!ret) { ++ ret = mo->read(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_HI, ++ &v); ++ *vals |= v << 16; ++ } ++ } ++out: ELMR_UNLOCK(adap); ++ return ret; ++} ++ ++int t3_vsc7323_init(adapter_t *adap, int nports) ++{ ++ static struct addr_val_pair sys_avp[] = { ++ { VSC_REG(7, 15, 0xf), 2 }, ++ { VSC_REG(7, 15, 0x19), 0xd6 }, ++ { VSC_REG(7, 15, 7), 0xc }, ++ { VSC_REG(7, 1, 0), 0x220 }, ++ }; ++ static struct addr_val_pair fifo_avp[] = { ++ { VSC_REG(2, 0, 0x2f), 0 }, ++ { VSC_REG(2, 0, 0xf), 0xa0010291 }, ++ { VSC_REG(2, 1, 0x2f), 1 }, ++ { VSC_REG(2, 1, 0xf), 0xa026301 } ++ }; ++ static struct addr_val_pair xg_avp[] = { ++ { VSC_REG(1, 10, 0), 0x600b }, ++ { VSC_REG(1, 10, 1), 0x70600 }, //QUANTA = 96*1024*8/512 ++ { VSC_REG(1, 10, 2), 0x2710 }, ++ { VSC_REG(1, 10, 5), 0x65 }, ++ { VSC_REG(1, 10, 7), 0x23 }, ++ { VSC_REG(1, 10, 0x23), 0x800007bf }, ++ { VSC_REG(1, 10, 0x23), 0x000007bf }, ++ { VSC_REG(1, 10, 0x23), 0x800007bf }, ++ { VSC_REG(1, 10, 0x24), 4 } ++ }; ++ ++ int i, ret, ing_step, egr_step, ing_bot, egr_bot; ++ ++ for (i = 0; i < ARRAY_SIZE(sys_avp); i++) ++ if ((ret = t3_elmr_blk_write(adap, sys_avp[i].reg_addr, ++ &sys_avp[i].val, 1))) ++ return ret; ++ ++ ing_step = 0xc0 / nports; ++ egr_step = 0x40 / nports; ++ ing_bot = egr_bot = 0; ++// ing_wm = ing_step * 64; ++// egr_wm = egr_step * 64; ++ ++ /* {ING,EGR}_CONTROL.CLR = 1 here */ ++ for (i = 0; i < nports; i++) { ++ if ( ++ (ret = elmr_write(adap, VSC_REG(2, 0, 0x10 + i), ++ ((ing_bot + ing_step) << 16) | ing_bot)) || ++ (ret = elmr_write(adap, VSC_REG(2, 0, 0x40 + i), ++ 0x6000bc0)) || ++ (ret = elmr_write(adap, VSC_REG(2, 0, 0x50 + i), 1)) || ++ (ret = elmr_write(adap, VSC_REG(2, 1, 0x10 + i), ++ ((egr_bot + egr_step) << 16) | egr_bot)) || ++ (ret = elmr_write(adap, VSC_REG(2, 1, 0x40 + i), ++ 0x2000280)) || ++ (ret = elmr_write(adap, VSC_REG(2, 1, 0x50 + i), 0))) ++ return ret; ++ ing_bot += ing_step; ++ egr_bot += egr_step; ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(fifo_avp); i++) ++ if ((ret = t3_elmr_blk_write(adap, fifo_avp[i].reg_addr, ++ &fifo_avp[i].val, 1))) ++ return ret; ++ ++ for (i = 0; i < ARRAY_SIZE(xg_avp); i++) ++ if ((ret = t3_elmr_blk_write(adap, xg_avp[i].reg_addr, ++ &xg_avp[i].val, 1))) ++ return ret; ++ ++ for (i = 0; i < nports; i++) ++ if ((ret = elmr_write(adap, VSC_REG(1, i, 0), 0xa59c)) || ++ (ret = elmr_write(adap, VSC_REG(1, i, 5), ++ (i << 12) | 0x63)) || ++ (ret = elmr_write(adap, VSC_REG(1, i, 0xb), 0x96)) || ++ (ret = elmr_write(adap, VSC_REG(1, i, 0x15), 0x21)) || ++ (ret = elmr_write(adap, ELMR_THRES0 + i, 768))) ++ return ret; ++ ++ if ((ret = elmr_write(adap, ELMR_BW, 7))) ++ return ret; ++ ++ return ret; ++} ++ ++int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port) ++{ ++ int mode, clk, r; ++ ++ if (speed >= 0) { ++ if (speed == SPEED_10) ++ mode = clk = 1; ++ else if (speed == SPEED_100) ++ mode = 1, clk = 2; ++ else if (speed == SPEED_1000) ++ mode = clk = 3; ++ else ++ return -EINVAL; ++ ++ if ((r = elmr_write(adap, VSC_REG(1, port, 0), ++ 0xa590 | (mode << 2))) || ++ (r = elmr_write(adap, VSC_REG(1, port, 0xb), ++ 0x91 | (clk << 1))) || ++ (r = elmr_write(adap, VSC_REG(1, port, 0xb), ++ 0x90 | (clk << 1))) || ++ (r = elmr_write(adap, VSC_REG(1, port, 0), ++ 0xa593 | (mode << 2)))) ++ return r; ++ } ++ ++ r = (fc & PAUSE_RX) ? 0x60200 : 0x20200; //QUANTA = 32*1024*8/512 ++ if (fc & PAUSE_TX) ++ r |= (1 << 19); ++ return elmr_write(adap, VSC_REG(1, port, 1), r); ++} ++ ++int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port) ++{ ++ return elmr_write(adap, VSC_REG(1, port, 2), mtu); ++} ++ ++int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port) ++{ ++ int ret; ++ ++ ret = elmr_write(adap, VSC_REG(1, port, 3), ++ (addr[0] << 16) | (addr[1] << 8) | addr[2]); ++ if (!ret) ++ ret = elmr_write(adap, VSC_REG(1, port, 4), ++ (addr[3] << 16) | (addr[4] << 8) | addr[5]); ++ return ret; ++} ++ ++int t3_vsc7323_enable(adapter_t *adap, int port, int which) ++{ ++ int ret; ++ unsigned int v, orig; ++ ++ ret = t3_elmr_blk_read(adap, VSC_REG(1, port, 0), &v, 1); ++ if (!ret) { ++ orig = v; ++ if (which & MAC_DIRECTION_TX) ++ v |= 1; ++ if (which & MAC_DIRECTION_RX) ++ v |= 2; ++ if (v != orig) ++ ret = elmr_write(adap, VSC_REG(1, port, 0), v); ++ } ++ return ret; ++} ++ ++int t3_vsc7323_disable(adapter_t *adap, int port, int which) ++{ ++ int ret; ++ unsigned int v, orig; ++ ++ ret = t3_elmr_blk_read(adap, VSC_REG(1, port, 0), &v, 1); ++ if (!ret) { ++ orig = v; ++ if (which & MAC_DIRECTION_TX) ++ v &= ~1; ++ if (which & MAC_DIRECTION_RX) ++ v &= ~2; ++ if (v != orig) ++ ret = elmr_write(adap, VSC_REG(1, port, 0), v); ++ } ++ return ret; ++} ++ ++#define STATS0_START 1 ++#define STATS1_START 0x24 ++#define NSTATS0 (0x1d - STATS0_START + 1) ++#define NSTATS1 (0x2a - STATS1_START + 1) ++ ++#define ELMR_STAT(port, reg) (ELMR_STATS + port * 0x40 + reg) ++ ++const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac) ++{ ++ int ret; ++ u64 rx_ucast, tx_ucast; ++ u32 stats0[NSTATS0], stats1[NSTATS1]; ++ ++ ret = t3_elmr_blk_read(mac->adapter, ++ ELMR_STAT(mac->ext_port, STATS0_START), ++ stats0, NSTATS0); ++ if (!ret) ++ ret = t3_elmr_blk_read(mac->adapter, ++ ELMR_STAT(mac->ext_port, STATS1_START), ++ stats1, NSTATS1); ++ if (ret) ++ goto out; ++ ++ /* ++ * HW counts Rx/Tx unicast frames but we want all the frames. ++ */ ++ rx_ucast = mac->stats.rx_frames - mac->stats.rx_mcast_frames - ++ mac->stats.rx_bcast_frames; ++ rx_ucast += (u64)(stats0[6 - STATS0_START] - (u32)rx_ucast); ++ tx_ucast = mac->stats.tx_frames - mac->stats.tx_mcast_frames - ++ mac->stats.tx_bcast_frames; ++ tx_ucast += (u64)(stats0[27 - STATS0_START] - (u32)tx_ucast); ++ ++#define RMON_UPDATE(mac, name, hw_stat) \ ++ mac->stats.name += (u64)((hw_stat) - (u32)(mac->stats.name)) ++ ++ RMON_UPDATE(mac, rx_octets, stats0[4 - STATS0_START]); ++ RMON_UPDATE(mac, rx_frames, stats0[6 - STATS0_START]); ++ RMON_UPDATE(mac, rx_frames, stats0[7 - STATS0_START]); ++ RMON_UPDATE(mac, rx_frames, stats0[8 - STATS0_START]); ++ RMON_UPDATE(mac, rx_mcast_frames, stats0[7 - STATS0_START]); ++ RMON_UPDATE(mac, rx_bcast_frames, stats0[8 - STATS0_START]); ++ RMON_UPDATE(mac, rx_fcs_errs, stats0[9 - STATS0_START]); ++ RMON_UPDATE(mac, rx_pause, stats0[2 - STATS0_START]); ++ RMON_UPDATE(mac, rx_jabber, stats0[16 - STATS0_START]); ++ RMON_UPDATE(mac, rx_short, stats0[11 - STATS0_START]); ++ RMON_UPDATE(mac, rx_symbol_errs, stats0[1 - STATS0_START]); ++ RMON_UPDATE(mac, rx_too_long, stats0[15 - STATS0_START]); ++ ++ RMON_UPDATE(mac, rx_frames_64, stats0[17 - STATS0_START]); ++ RMON_UPDATE(mac, rx_frames_65_127, stats0[18 - STATS0_START]); ++ RMON_UPDATE(mac, rx_frames_128_255, stats0[19 - STATS0_START]); ++ RMON_UPDATE(mac, rx_frames_256_511, stats0[20 - STATS0_START]); ++ RMON_UPDATE(mac, rx_frames_512_1023, stats0[21 - STATS0_START]); ++ RMON_UPDATE(mac, rx_frames_1024_1518, stats0[22 - STATS0_START]); ++ RMON_UPDATE(mac, rx_frames_1519_max, stats0[23 - STATS0_START]); ++ ++ RMON_UPDATE(mac, tx_octets, stats0[26 - STATS0_START]); ++ RMON_UPDATE(mac, tx_frames, stats0[27 - STATS0_START]); ++ RMON_UPDATE(mac, tx_frames, stats0[28 - STATS0_START]); ++ RMON_UPDATE(mac, tx_frames, stats0[29 - STATS0_START]); ++ RMON_UPDATE(mac, tx_mcast_frames, stats0[28 - STATS0_START]); ++ RMON_UPDATE(mac, tx_bcast_frames, stats0[29 - STATS0_START]); ++ RMON_UPDATE(mac, tx_pause, stats0[25 - STATS0_START]); ++ ++ RMON_UPDATE(mac, tx_underrun, 0); ++ ++ RMON_UPDATE(mac, tx_frames_64, stats1[36 - STATS1_START]); ++ RMON_UPDATE(mac, tx_frames_65_127, stats1[37 - STATS1_START]); ++ RMON_UPDATE(mac, tx_frames_128_255, stats1[38 - STATS1_START]); ++ RMON_UPDATE(mac, tx_frames_256_511, stats1[39 - STATS1_START]); ++ RMON_UPDATE(mac, tx_frames_512_1023, stats1[40 - STATS1_START]); ++ RMON_UPDATE(mac, tx_frames_1024_1518, stats1[41 - STATS1_START]); ++ RMON_UPDATE(mac, tx_frames_1519_max, stats1[42 - STATS1_START]); ++ ++#undef RMON_UPDATE ++ ++ mac->stats.rx_frames = rx_ucast + mac->stats.rx_mcast_frames + ++ mac->stats.rx_bcast_frames; ++ mac->stats.tx_frames = tx_ucast + mac->stats.tx_mcast_frames + ++ mac->stats.tx_bcast_frames; ++out: return &mac->stats; ++} +diff -r c6413c34aa41 drivers/net/cxgb3/vsc8211.c +--- a/drivers/net/cxgb3/vsc8211.c Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/vsc8211.c Tue Oct 06 09:38:00 2009 +0100 +@@ -1,63 +1,44 @@ + /* +- * Copyright (c) 2005-2007 Chelsio, Inc. All rights reserved. ++ * This file is part of the Chelsio T3 Ethernet driver. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: ++ * Copyright (C) 2005-2009 Chelsio Communications. All rights reserved. + * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ ++ + #include "common.h" + + /* VSC8211 PHY specific registers. */ + enum { +- VSC8211_SIGDET_CTRL = 19, +- VSC8211_EXT_CTRL = 23, +- VSC8211_INTR_ENABLE = 25, +- VSC8211_INTR_STATUS = 26, +- VSC8211_LED_CTRL = 27, ++ VSC8211_SIGDET_CTRL = 19, ++ VSC8211_EXT_CTRL = 23, ++ VSC8211_PHY_CTRL = 24, ++ VSC8211_INTR_ENABLE = 25, ++ VSC8211_INTR_STATUS = 26, ++ VSC8211_LED_CTRL = 27, + VSC8211_AUX_CTRL_STAT = 28, +- VSC8211_EXT_PAGE_AXS = 31, ++ VSC8211_EXT_PAGE_AXS = 31, + }; + + enum { +- VSC_INTR_RX_ERR = 1 << 0, +- VSC_INTR_MS_ERR = 1 << 1, /* master/slave resolution error */ +- VSC_INTR_CABLE = 1 << 2, /* cable impairment */ ++ VSC_INTR_RX_ERR = 1 << 0, ++ VSC_INTR_MS_ERR = 1 << 1, /* master/slave resolution error */ ++ VSC_INTR_CABLE = 1 << 2, /* cable impairment */ + VSC_INTR_FALSE_CARR = 1 << 3, /* false carrier */ +- VSC_INTR_MEDIA_CHG = 1 << 4, /* AMS media change */ +- VSC_INTR_RX_FIFO = 1 << 5, /* Rx FIFO over/underflow */ +- VSC_INTR_TX_FIFO = 1 << 6, /* Tx FIFO over/underflow */ +- VSC_INTR_DESCRAMBL = 1 << 7, /* descrambler lock-lost */ ++ VSC_INTR_MEDIA_CHG = 1 << 4, /* AMS media change */ ++ VSC_INTR_RX_FIFO = 1 << 5, /* Rx FIFO over/underflow */ ++ VSC_INTR_TX_FIFO = 1 << 6, /* Tx FIFO over/underflow */ ++ VSC_INTR_DESCRAMBL = 1 << 7, /* descrambler lock-lost */ + VSC_INTR_SYMBOL_ERR = 1 << 8, /* symbol error */ +- VSC_INTR_NEG_DONE = 1 << 10, /* autoneg done */ +- VSC_INTR_NEG_ERR = 1 << 11, /* autoneg error */ +- VSC_INTR_DPLX_CHG = 1 << 12, /* duplex change */ +- VSC_INTR_LINK_CHG = 1 << 13, /* link change */ +- VSC_INTR_SPD_CHG = 1 << 14, /* speed change */ +- VSC_INTR_ENABLE = 1 << 15, /* interrupt enable */ ++ VSC_INTR_NEG_DONE = 1 << 10, /* autoneg done */ ++ VSC_INTR_NEG_ERR = 1 << 11, /* autoneg error */ ++ VSC_INTR_DPLX_CHG = 1 << 12, /* duplex change */ ++ VSC_INTR_LINK_CHG = 1 << 13, /* link change */ ++ VSC_INTR_SPD_CHG = 1 << 14, /* speed change */ ++ VSC_INTR_ENABLE = 1 << 15, /* interrupt enable */ + }; + + enum { +@@ -125,7 +106,7 @@ + } + + static int vsc8211_get_link_status(struct cphy *cphy, int *link_ok, +- int *speed, int *duplex, int *fc) ++ int *speed, int *duplex, int *fc) + { + unsigned int bmcr, status, lpa, adv; + int err, sp = -1, dplx = -1, pause = 0; +@@ -269,26 +250,12 @@ + { + int err; + +- err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0x52b5); +- if (err) ++ if ((err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0x52b5)) != 0 || ++ (err = mdio_write(phy, 0, 18, 0x12)) != 0 || ++ (err = mdio_write(phy, 0, 17, enable ? 0x2803 : 0x3003)) != 0 || ++ (err = mdio_write(phy, 0, 16, 0x87fa)) != 0 || ++ (err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0)) != 0) + return err; +- +- err = mdio_write(phy, 0, 18, 0x12); +- if (err) +- return err; +- +- err = mdio_write(phy, 0, 17, enable ? 0x2803 : 0x3003); +- if (err) +- return err; +- +- err = mdio_write(phy, 0, 16, 0x87fa); +- if (err) +- return err; +- +- err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0); +- if (err) +- return err; +- + return 0; + } + +@@ -325,41 +292,122 @@ + return cphy_cause; + } + ++#ifdef C99_NOT_SUPPORTED + static struct cphy_ops vsc8211_ops = { +- .reset = vsc8211_reset, +- .intr_enable = vsc8211_intr_enable, +- .intr_disable = vsc8211_intr_disable, +- .intr_clear = vsc8211_intr_clear, +- .intr_handler = vsc8211_intr_handler, +- .autoneg_enable = vsc8211_autoneg_enable, +- .autoneg_restart = vsc8211_autoneg_restart, +- .advertise = t3_phy_advertise, +- .set_speed_duplex = t3_set_phy_speed_duplex, +- .get_link_status = vsc8211_get_link_status, +- .power_down = vsc8211_power_down, ++ vsc8211_reset, ++ vsc8211_intr_enable, ++ vsc8211_intr_disable, ++ vsc8211_intr_clear, ++ vsc8211_intr_handler, ++ vsc8211_autoneg_enable, ++ vsc8211_autoneg_restart, ++ t3_phy_advertise, ++ NULL, ++ vsc8211_set_speed_duplex, ++ vsc8211_get_link_status, ++ vsc8211_power_down, + }; + + static struct cphy_ops vsc8211_fiber_ops = { +- .reset = vsc8211_reset, +- .intr_enable = vsc8211_intr_enable, +- .intr_disable = vsc8211_intr_disable, +- .intr_clear = vsc8211_intr_clear, +- .intr_handler = vsc8211_intr_handler, +- .autoneg_enable = vsc8211_autoneg_enable, +- .autoneg_restart = vsc8211_autoneg_restart, +- .advertise = t3_phy_advertise_fiber, +- .set_speed_duplex = t3_set_phy_speed_duplex, +- .get_link_status = vsc8211_get_link_status_fiber, +- .power_down = vsc8211_power_down, ++ vsc8211_reset, ++ vsc8211_intr_enable, ++ vsc8211_intr_disable, ++ vsc8211_intr_clear, ++ vsc8211_intr_handler, ++ vsc8211_autoneg_enable, ++ vsc8211_autoneg_restart, ++ t3_phy_advertise_fiber, ++ NULL, ++ t3_set_phy_speed_duplex, ++ vsc8211_get_link_status_fiber, ++ vsc8211_power_down, ++}; ++#else ++static struct cphy_ops vsc8211_ops = { ++ .reset = vsc8211_reset, ++ .intr_enable = vsc8211_intr_enable, ++ .intr_disable = vsc8211_intr_disable, ++ .intr_clear = vsc8211_intr_clear, ++ .intr_handler = vsc8211_intr_handler, ++ .autoneg_enable = vsc8211_autoneg_enable, ++ .autoneg_restart = vsc8211_autoneg_restart, ++ .advertise = t3_phy_advertise, ++ .set_speed_duplex = vsc8211_set_speed_duplex, ++ .get_link_status = vsc8211_get_link_status, ++ .power_down = vsc8211_power_down, + }; + +-int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter, +- int phy_addr, const struct mdio_ops *mdio_ops) ++static struct cphy_ops vsc8211_fiber_ops = { ++ .reset = vsc8211_reset, ++ .intr_enable = vsc8211_intr_enable, ++ .intr_disable = vsc8211_intr_disable, ++ .intr_clear = vsc8211_intr_clear, ++ .intr_handler = vsc8211_intr_handler, ++ .autoneg_enable = vsc8211_autoneg_enable, ++ .autoneg_restart = vsc8211_autoneg_restart, ++ .advertise = t3_phy_advertise_fiber, ++ .set_speed_duplex = t3_set_phy_speed_duplex, ++ .get_link_status = vsc8211_get_link_status_fiber, ++ .power_down = vsc8211_power_down, ++}; ++#endif ++ ++#define VSC8211_PHY_CTRL 24 ++ ++#define S_VSC8211_TXFIFODEPTH 7 ++#define M_VSC8211_TXFIFODEPTH 0x7 ++#define V_VSC8211_TXFIFODEPTH(x) ((x) << S_VSC8211_TXFIFODEPTH) ++#define G_VSC8211_TXFIFODEPTH(x) (((x) >> S_VSC8211_TXFIFODEPTH) & M_VSC8211_TXFIFODEPTH) ++ ++#define S_VSC8211_RXFIFODEPTH 4 ++#define M_VSC8211_RXFIFODEPTH 0x7 ++#define V_VSC8211_RXFIFODEPTH(x) ((x) << S_VSC8211_RXFIFODEPTH) ++#define G_VSC8211_RXFIFODEPTH(x) (((x) >> S_VSC8211_RXFIFODEPTH) & M_VSC8211_RXFIFODEPTH) ++ ++int t3_vsc8211_fifo_depth(adapter_t *adap, unsigned int mtu, int port) + { ++ /* TX FIFO Depth set bits 9:7 to 100 (IEEE mode) */ ++ unsigned int val = 4; ++ unsigned int currentregval; ++ unsigned int regval; ++ int err; ++ ++ /* Retrieve the port info structure from adater_t */ ++ struct port_info *portinfo = adap2pinfo(adap, port); ++ ++ /* What phy is this */ ++ struct cphy *phy = &portinfo->phy; ++ ++ /* Read the current value of the PHY control Register */ ++ err = mdio_read(phy, 0, VSC8211_PHY_CTRL, ¤tregval); ++ ++ if (err) ++ return err; ++ ++ /* IEEE mode supports up to 1518 bytes */ ++ /* mtu does not contain the header + FCS (18 bytes) */ ++ if (mtu > 1500) ++ /* ++ * If using a packet size > 1500 set TX FIFO Depth bits ++ * 9:7 to 011 (Jumbo packet mode) ++ */ ++ val = 3; ++ ++ regval = V_VSC8211_TXFIFODEPTH(val) | V_VSC8211_RXFIFODEPTH(val) | ++ (currentregval & ~V_VSC8211_TXFIFODEPTH(M_VSC8211_TXFIFODEPTH) & ++ ~V_VSC8211_RXFIFODEPTH(M_VSC8211_RXFIFODEPTH)); ++ ++ return mdio_write(phy, 0, VSC8211_PHY_CTRL, regval); ++} ++ ++int t3_vsc8211_phy_prep(pinfo_t *pinfo, int phy_addr, ++ const struct mdio_ops *mdio_ops) ++{ ++ struct cphy *phy = &pinfo->phy; + int err; + unsigned int val; + +- cphy_init(phy, adapter, phy_addr, &vsc8211_ops, mdio_ops, ++ cphy_init(&pinfo->phy, pinfo->adapter, pinfo, phy_addr, &vsc8211_ops, mdio_ops, + SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_MII | + SUPPORTED_TP | SUPPORTED_IRQ, "10/100/1000BASE-T"); +@@ -378,25 +426,12 @@ + phy->desc = "1000BASE-X"; + phy->ops = &vsc8211_fiber_ops; + +- err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 1); +- if (err) +- return err; +- +- err = mdio_write(phy, 0, VSC8211_SIGDET_CTRL, 1); +- if (err) +- return err; +- +- err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0); +- if (err) +- return err; +- +- err = mdio_write(phy, 0, VSC8211_EXT_CTRL, +- val | VSC_CTRL_CLAUSE37_VIEW); +- if (err) +- return err; +- +- err = vsc8211_reset(phy, 0); +- if (err) ++ if ((err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 1)) != 0 || ++ (err = mdio_write(phy, 0, VSC8211_SIGDET_CTRL, 1)) != 0 || ++ (err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0)) != 0 || ++ (err = mdio_write(phy, 0, VSC8211_EXT_CTRL, ++ val | VSC_CTRL_CLAUSE37_VIEW)) != 0 || ++ (err = vsc8211_reset(phy, 0)) != 0) + return err; + + udelay(5); /* delay after reset before next SMI */ +diff -r c6413c34aa41 drivers/net/cxgb3/xgmac.c +--- a/drivers/net/cxgb3/xgmac.c Thu Oct 01 10:10:05 2009 +0100 ++++ b/drivers/net/cxgb3/xgmac.c Tue Oct 06 09:38:00 2009 +0100 +@@ -1,42 +1,16 @@ + /* +- * Copyright (c) 2005-2007 Chelsio, Inc. All rights reserved. ++ * This file is part of the Chelsio T3 Ethernet driver. + * +- * This software is available to you under a choice of one of two +- * licenses. You may choose to be licensed under the terms of the GNU +- * General Public License (GPL) Version 2, available from the file +- * COPYING in the main directory of this source tree, or the +- * OpenIB.org BSD license below: ++ * Copyright (C) 2005-2009 Chelsio Communications. All rights reserved. + * +- * Redistribution and use in source and binary forms, with or +- * without modification, are permitted provided that the following +- * conditions are met: +- * +- * - Redistributions of source code must retain the above +- * copyright notice, this list of conditions and the following +- * disclaimer. +- * +- * - Redistributions in binary form must reproduce the above +- * copyright notice, this list of conditions and the following +- * disclaimer in the documentation and/or other materials +- * provided with the distribution. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this ++ * release for licensing terms and conditions. + */ ++ + #include "common.h" + #include "regs.h" +- +-/* +- * # of exact address filters. The first one is used for the station address, +- * the rest are available for multicast addresses. +- */ +-#define EXACT_ADDR_FILTERS 8 + + static inline int macidx(const struct cmac *mac) + { +@@ -46,19 +20,19 @@ + static void xaui_serdes_reset(struct cmac *mac) + { + static const unsigned int clear[] = { +- F_PWRDN0 | F_PWRDN1, F_RESETPLL01, F_RESET0 | F_RESET1, +- F_PWRDN2 | F_PWRDN3, F_RESETPLL23, F_RESET2 | F_RESET3 ++ F_PWRDN0 | F_PWRDN1, F_RESETPLL01, F_RESET0 | F_RESET1, ++ F_PWRDN2 | F_PWRDN3, F_RESETPLL23, F_RESET2 | F_RESET3 + }; + + int i; +- struct adapter *adap = mac->adapter; ++ adapter_t *adap = mac->adapter; + u32 ctrl = A_XGM_SERDES_CTRL0 + mac->offset; + + t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] | + F_RESET3 | F_RESET2 | F_RESET1 | F_RESET0 | + F_PWRDN3 | F_PWRDN2 | F_PWRDN1 | F_PWRDN0 | + F_RESETPLL23 | F_RESETPLL01); +- t3_read_reg(adap, ctrl); ++ (void)t3_read_reg(adap, ctrl); + udelay(15); + + for (i = 0; i < ARRAY_SIZE(clear); i++) { +@@ -67,6 +41,12 @@ + } + } + ++/** ++ * t3b_pcs_reset - reset the PCS on T3B+ adapters ++ * @mac: the XGMAC handle ++ * ++ * Reset the XGMAC PCS block on T3B+ adapters. ++ */ + void t3b_pcs_reset(struct cmac *mac) + { + t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset, +@@ -76,31 +56,37 @@ + F_PCS_RESET_); + } + ++/** ++ * t3_mac_reset - reset a MAC ++ * @mac: the MAC to reset ++ * ++ * Reset the given MAC. ++ */ + int t3_mac_reset(struct cmac *mac) + { +- static const struct addr_val_pair mac_reset_avp[] = { +- {A_XGM_TX_CTRL, 0}, +- {A_XGM_RX_CTRL, 0}, +- {A_XGM_RX_CFG, F_DISPAUSEFRAMES | F_EN1536BFRAMES | +- F_RMFCS | F_ENJUMBO | F_ENHASHMCAST}, +- {A_XGM_RX_HASH_LOW, 0}, +- {A_XGM_RX_HASH_HIGH, 0}, +- {A_XGM_RX_EXACT_MATCH_LOW_1, 0}, +- {A_XGM_RX_EXACT_MATCH_LOW_2, 0}, +- {A_XGM_RX_EXACT_MATCH_LOW_3, 0}, +- {A_XGM_RX_EXACT_MATCH_LOW_4, 0}, +- {A_XGM_RX_EXACT_MATCH_LOW_5, 0}, +- {A_XGM_RX_EXACT_MATCH_LOW_6, 0}, +- {A_XGM_RX_EXACT_MATCH_LOW_7, 0}, +- {A_XGM_RX_EXACT_MATCH_LOW_8, 0}, +- {A_XGM_STAT_CTRL, F_CLRSTATS} ++ static struct addr_val_pair mac_reset_avp[] = { ++ { A_XGM_TX_CTRL, 0 }, ++ { A_XGM_RX_CTRL, 0 }, ++ { A_XGM_RX_CFG, F_DISPAUSEFRAMES | F_EN1536BFRAMES | ++ F_RMFCS | F_ENJUMBO | F_ENHASHMCAST }, ++ { A_XGM_RX_HASH_LOW, 0 }, ++ { A_XGM_RX_HASH_HIGH, 0 }, ++ { A_XGM_RX_EXACT_MATCH_LOW_1, 0 }, ++ { A_XGM_RX_EXACT_MATCH_LOW_2, 0 }, ++ { A_XGM_RX_EXACT_MATCH_LOW_3, 0 }, ++ { A_XGM_RX_EXACT_MATCH_LOW_4, 0 }, ++ { A_XGM_RX_EXACT_MATCH_LOW_5, 0 }, ++ { A_XGM_RX_EXACT_MATCH_LOW_6, 0 }, ++ { A_XGM_RX_EXACT_MATCH_LOW_7, 0 }, ++ { A_XGM_RX_EXACT_MATCH_LOW_8, 0 }, ++ { A_XGM_STAT_CTRL, F_CLRSTATS } + }; + u32 val; +- struct adapter *adap = mac->adapter; ++ adapter_t *adap = mac->adapter; + unsigned int oft = mac->offset; + + t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_); +- t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ ++ (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ + + t3_write_regs(adap, mac_reset_avp, ARRAY_SIZE(mac_reset_avp), oft); + t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft, +@@ -125,19 +111,34 @@ + xaui_serdes_reset(mac); + } + ++ ++ if (mac->multiport) { ++ t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + oft, ++ V_RXMAXPKTSIZE(MAX_FRAME_SIZE - 4)); ++ t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft, 0, ++ F_DISPREAMBLE); ++ t3_set_reg_field(adap, A_XGM_RX_CFG + oft, 0, F_COPYPREAMBLE | ++ F_ENNON802_3PREAMBLE); ++ t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft, ++ V_TXFIFOTHRESH(M_TXFIFOTHRESH), ++ V_TXFIFOTHRESH(64)); ++ t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN); ++ t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN); ++ } ++ + t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + oft, + V_RXMAXFRAMERSIZE(M_RXMAXFRAMERSIZE), + V_RXMAXFRAMERSIZE(MAX_FRAME_SIZE) | F_RXENFRAMER); ++ + val = F_MAC_RESET_ | F_XGMAC_STOP_EN; +- +- if (is_10G(adap)) ++ if (!mac->multiport) ++ val |= F_XG2G_RESET_; ++ if (uses_xaui(adap)) + val |= F_PCS_RESET_; +- else if (uses_xaui(adap)) +- val |= F_PCS_RESET_ | F_XG2G_RESET_; + else +- val |= F_RGMII_RESET_ | F_XG2G_RESET_; ++ val |= F_RGMII_RESET_; + t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val); +- t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ ++ (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ + if ((val & F_PCS_RESET_) && adap->params.rev) { + msleep(1); + t3b_pcs_reset(mac); +@@ -147,32 +148,52 @@ + return 0; + } + +-static int t3b2_mac_reset(struct cmac *mac) ++int t3b2_mac_reset(struct cmac *mac) + { +- struct adapter *adap = mac->adapter; ++ u32 val, store_mps; ++ adapter_t *adap = mac->adapter; + unsigned int oft = mac->offset; +- u32 val; ++ int idx = macidx(mac); ++ unsigned int store; + ++ /* Stop egress traffic to xgm*/ ++ store_mps = t3_read_reg(adap, A_MPS_CFG); + if (!macidx(mac)) + t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0); + else + t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0); + ++ /* This will reduce the number of TXTOGGLES */ ++ /* Clear: to stop the NIC traffic */ ++ t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 0); ++ /* Ensure TX drains */ ++ t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, 0); ++ ++ /* PCS in reset */ + t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_); +- t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ ++ (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ ++ ++ /* Store A_TP_TX_DROP_CFG_CH0 */ ++ t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); ++ store = t3_read_reg(adap, A_TP_PIO_DATA); + + msleep(10); + ++ /* Change DROP_CFG to 0xc0000011 */ ++ t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); ++ t3_write_reg(adap, A_TP_PIO_DATA, 0xc0000011); ++ + /* Check for xgm Rx fifo empty */ ++ /* Increased loop count to 1000 from 5 cover 1G and 100Mbps case */ + if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft, +- 0x80000000, 1, 5, 2)) { ++ 0x80000000, 1, 1000, 2)) { + CH_ERR(adap, "MAC %d Rx fifo drain failed\n", + macidx(mac)); + return -1; + } + +- t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0); +- t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ ++ t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0); /*MAC in reset*/ ++ (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ + + val = F_MAC_RESET_; + if (is_10G(adap)) +@@ -182,19 +203,25 @@ + else + val |= F_RGMII_RESET_ | F_XG2G_RESET_; + t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val); +- t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ ++ (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ + if ((val & F_PCS_RESET_) && adap->params.rev) { + msleep(1); + t3b_pcs_reset(mac); + } + t3_write_reg(adap, A_XGM_RX_CFG + oft, +- F_DISPAUSEFRAMES | F_EN1536BFRAMES | +- F_RMFCS | F_ENJUMBO | F_ENHASHMCAST); ++ F_DISPAUSEFRAMES | F_EN1536BFRAMES | ++ F_RMFCS | F_ENJUMBO | F_ENHASHMCAST ); + +- if (!macidx(mac)) +- t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT0ACTIVE); +- else +- t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT1ACTIVE); ++ /* Restore the DROP_CFG */ ++ t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); ++ t3_write_reg(adap, A_TP_PIO_DATA, store); ++ ++ /* Resume egress traffic to xgm */ ++ t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE | F_PORT0ACTIVE, ++ store_mps); ++ ++ /* Set: re-enable NIC traffic */ ++ t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, F_ENFORCEPKT); + + return 0; + } +@@ -202,7 +229,7 @@ + /* + * Set the exact match register 'idx' to recognize the given Ethernet address. + */ +-static void set_addr_filter(struct cmac *mac, int idx, const u8 * addr) ++static void set_addr_filter(struct cmac *mac, int idx, const u8 *addr) + { + u32 addr_lo, addr_hi; + unsigned int oft = mac->offset + idx * 8; +@@ -214,21 +241,39 @@ + t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_HIGH_1 + oft, addr_hi); + } + +-/* Set one of the station's unicast MAC addresses. */ ++/** ++ * t3_mac_set_address - set one of the station's unicast MAC addresses ++ * @mac: the MAC handle ++ * @idx: index of the exact address match filter to use ++ * @addr: the Ethernet address ++ * ++ * Set one of the station's unicast MAC addresses. ++ */ + int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]) + { ++ if (mac->multiport) ++ idx = mac->ext_port + idx * mac->adapter->params.nports; + if (idx >= mac->nucast) + return -EINVAL; + set_addr_filter(mac, idx, addr); ++ if (mac->multiport && idx < mac->adapter->params.nports) ++ t3_vsc7323_set_addr(mac->adapter, addr, idx); + return 0; + } + +-/* +- * Specify the number of exact address filters that should be reserved for +- * unicast addresses. Caller should reload the unicast and multicast addresses +- * after calling this. ++/** ++ * t3_mac_set_num_ucast - set the number of unicast addresses needed ++ * @mac: the MAC handle ++ * @n: number of unicast addresses needed ++ * ++ * Specify the number of exact address filters that should be reserved for ++ * unicast addresses. Caller should reload the unicast and multicast ++ * addresses after calling this. ++ * ++ * Generally, this is 1 with the first one used for the station address, ++ * and the rest are available for multicast addresses. + */ +-int t3_mac_set_num_ucast(struct cmac *mac, int n) ++int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n) + { + if (n > EXACT_ADDR_FILTERS) + return -EINVAL; +@@ -236,7 +281,7 @@ + return 0; + } + +-static void disable_exact_filters(struct cmac *mac) ++void t3_mac_disable_exact_filters(struct cmac *mac) + { + unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_LOW_1; + +@@ -244,10 +289,10 @@ + u32 v = t3_read_reg(mac->adapter, reg); + t3_write_reg(mac->adapter, reg, v); + } +- t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */ ++ t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */ + } + +-static void enable_exact_filters(struct cmac *mac) ++void t3_mac_enable_exact_filters(struct cmac *mac) + { + unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_HIGH_1; + +@@ -255,11 +300,11 @@ + u32 v = t3_read_reg(mac->adapter, reg); + t3_write_reg(mac->adapter, reg, v); + } +- t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */ ++ t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */ + } + + /* Calculate the RX hash filter index of an Ethernet address */ +-static int hash_hw_addr(const u8 * addr) ++static int hash_hw_addr(const u8 *addr) + { + int hash = 0, octet, bit, i = 0, c; + +@@ -272,18 +317,28 @@ + return hash; + } + ++/** ++ * t3_mac_set_rx_mode - set the Rx mode and address filters ++ * @mac: the MAC to configure ++ * @rm: structure containing the Rx mode and MAC addresses needed ++ * ++ * Configures the MAC Rx mode (promiscuity, etc) and exact and hash ++ * address filters. ++ */ + int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm) + { +- u32 val, hash_lo, hash_hi; +- struct adapter *adap = mac->adapter; ++ u32 hash_lo, hash_hi; ++ adapter_t *adap = mac->adapter; + unsigned int oft = mac->offset; + +- val = t3_read_reg(adap, A_XGM_RX_CFG + oft) & ~F_COPYALLFRAMES; +- if (rm->dev->flags & IFF_PROMISC) +- val |= F_COPYALLFRAMES; +- t3_write_reg(adap, A_XGM_RX_CFG + oft, val); ++ if (promisc_rx_mode(rm)) ++ mac->promisc_map |= 1 << mac->ext_port; ++ else ++ mac->promisc_map &= ~(1 << mac->ext_port); ++ t3_set_reg_field(adap, A_XGM_RX_CFG + oft, F_COPYALLFRAMES, ++ mac->promisc_map ? F_COPYALLFRAMES : 0); + +- if (rm->dev->flags & IFF_ALLMULTI) ++ if (allmulti_rx_mode(rm) || mac->multiport) + hash_lo = hash_hi = 0xffffffff; + else { + u8 *addr; +@@ -316,34 +371,45 @@ + return min(hwm, MAC_RXFIFO_SIZE - 8192); + } + ++/** ++ * t3_mac_set_mtu - set the MAC MTU ++ * @mac: the MAC to configure ++ * @mtu: the MTU ++ * ++ * Sets the MAC MTU and adjusts the FIFO PAUSE watermarks accordingly. ++ */ + int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu) + { + int hwm, lwm, divisor; + int ipg; + unsigned int thres, v, reg; +- struct adapter *adap = mac->adapter; ++ adapter_t *adap = mac->adapter; ++ unsigned port_type = adap->params.vpd.port_type[macidx(mac)]; ++ unsigned int orig_mtu=mtu; + + /* + * MAX_FRAME_SIZE inludes header + FCS, mtu doesn't. The HW max + * packet size register includes header, but not FCS. + */ + mtu += 14; ++ if (mac->multiport) ++ mtu += 8; /* for preamble */ + if (mtu > MAX_FRAME_SIZE - 4) + return -EINVAL; +- t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu); ++ if (mac->multiport) ++ return t3_vsc7323_set_mtu(adap, mtu - 4, mac->ext_port); + +- /* +- * Adjust the PAUSE frame watermarks. We always set the LWM, and the +- * HWM only if flow-control is enabled. +- */ +- hwm = max_t(unsigned int, MAC_RXFIFO_SIZE - 3 * mtu, +- MAC_RXFIFO_SIZE * 38 / 100); +- hwm = min(hwm, MAC_RXFIFO_SIZE - 8192); +- lwm = min(3 * (int)mtu, MAC_RXFIFO_SIZE / 4); ++ /* Modify the TX and RX fifo depth only if the card has a vsc8211 phy */ ++ if (port_type == 2) { ++ int err = t3_vsc8211_fifo_depth(adap,orig_mtu,macidx(mac)); ++ ++ if (err) ++ return err; ++ } + + if (adap->params.rev >= T3_REV_B2 && + (t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) { +- disable_exact_filters(mac); ++ t3_mac_disable_exact_filters(mac); + v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset); + t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset, + F_ENHASHMCAST | F_COPYALLFRAMES, F_DISBCAST); +@@ -355,25 +421,24 @@ + if (t3_wait_op_done(adap, reg + mac->offset, + F_RXFIFO_EMPTY, 1, 20, 5)) { + t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v); +- enable_exact_filters(mac); ++ t3_mac_enable_exact_filters(mac); + return -EIO; + } + t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, + V_RXMAXPKTSIZE(M_RXMAXPKTSIZE), + V_RXMAXPKTSIZE(mtu)); + t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v); +- enable_exact_filters(mac); ++ t3_mac_enable_exact_filters(mac); + } else + t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, + V_RXMAXPKTSIZE(M_RXMAXPKTSIZE), + V_RXMAXPKTSIZE(mtu)); +- + /* + * Adjust the PAUSE frame watermarks. We always set the LWM, and the + * HWM only if flow-control is enabled. + */ + hwm = rx_fifo_hwm(mtu); +- lwm = min(3 * (int)mtu, MAC_RXFIFO_SIZE / 4); ++ lwm = min(3 * (int) mtu, MAC_RXFIFO_SIZE /4); + v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset); + v &= ~V_RXFIFOPAUSELWM(M_RXFIFOPAUSELWM); + v |= V_RXFIFOPAUSELWM(lwm / 8); +@@ -389,12 +454,19 @@ + if (is_10G(adap)) + thres /= 10; + thres = mtu > thres ? (mtu - thres + 7) / 8 : 0; +- thres = max(thres, 8U); /* need at least 8 */ ++ thres = max(thres, 8U); /* need at least 8 */ + ipg = (adap->params.rev == T3_REV_C) ? 0 : 1; ++ ++ /* Ugly hack */ ++ if (is_demo_bt(adap)) ++ ipg = 1; ++ + t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset, + V_TXFIFOTHRESH(M_TXFIFOTHRESH) | V_TXIPG(M_TXIPG), + V_TXFIFOTHRESH(thres) | V_TXIPG(ipg)); + ++ /* Assuming a minimum drain rate of 2.5Gbps... ++ */ + if (adap->params.rev > 0) { + divisor = (adap->params.rev == T3_REV_C) ? 64 : 8; + t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset, +@@ -405,14 +477,38 @@ + return 0; + } + ++/** ++ * t3_mac_set_speed_duplex_fc - set MAC speed, duplex and flow control ++ * @mac: the MAC to configure ++ * @speed: the desired speed (10/100/1000/10000) ++ * @duplex: the desired duplex ++ * @fc: desired Tx/Rx PAUSE configuration ++ * ++ * Set the MAC speed, duplex (actually only full-duplex is supported), and ++ * flow control. If a parameter value is negative the corresponding ++ * MAC setting is left at its current value. ++ */ + int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc) + { + u32 val; +- struct adapter *adap = mac->adapter; ++ adapter_t *adap = mac->adapter; + unsigned int oft = mac->offset; + + if (duplex >= 0 && duplex != DUPLEX_FULL) + return -EINVAL; ++ if (mac->multiport) { ++ u32 rx_max_pkt_size = ++ G_RXMAXPKTSIZE(t3_read_reg(adap, ++ A_XGM_RX_MAX_PKT_SIZE + oft)); ++ val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft); ++ val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM); ++ val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(rx_max_pkt_size) / 8); ++ t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val); ++ ++ t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, ++ F_TXPAUSEEN); ++ return t3_vsc7323_set_speed_fc(adap, speed, fc, mac->ext_port); ++ } + if (speed >= 0) { + if (speed == SPEED_10) + val = V_PORTSPEED(0); +@@ -431,37 +527,54 @@ + + val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft); + val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM); +- if (fc & PAUSE_TX) +- val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm( +- t3_read_reg(adap, +- A_XGM_RX_MAX_PKT_SIZE +- + oft)) / 8); ++ if (fc & PAUSE_TX) { ++ u32 rx_max_pkt_size = ++ G_RXMAXPKTSIZE(t3_read_reg(adap, ++ A_XGM_RX_MAX_PKT_SIZE + oft)); ++ val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(rx_max_pkt_size) / 8); ++ } + t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val); + + t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, +- (fc & PAUSE_RX) ? F_TXPAUSEEN : 0); ++ (fc & PAUSE_RX) ? F_TXPAUSEEN : 0); + return 0; + } + ++/** ++ * t3_mac_enable - enable the MAC in the given directions ++ * @mac: the MAC to configure ++ * @which: bitmap indicating which directions to enable ++ * ++ * Enables the MAC for operation in the given directions. ++ * %MAC_DIRECTION_TX enables the Tx direction, and %MAC_DIRECTION_RX ++ * enables the Rx one. ++ */ + int t3_mac_enable(struct cmac *mac, int which) + { + int idx = macidx(mac); +- struct adapter *adap = mac->adapter; ++ adapter_t *adap = mac->adapter; + unsigned int oft = mac->offset; + struct mac_stats *s = &mac->stats; + ++ if (mac->multiport) ++ return t3_vsc7323_enable(adap, mac->ext_port, which); ++ + if (which & MAC_DIRECTION_TX) { + t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); +- t3_write_reg(adap, A_TP_PIO_DATA, 0xc0ede401); ++ t3_write_reg(adap, A_TP_PIO_DATA, ++ adap->params.rev == T3_REV_C ? ++ 0xc4ffff01 : 0xc0ede401); + t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE); +- t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx); ++ t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, ++ adap->params.rev == T3_REV_C ? ++ 0 : 1 << idx); + + t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN); + + t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx); + mac->tx_mcnt = s->tx_frames; + mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap, +- A_TP_PIO_DATA))); ++ A_TP_PIO_DATA))); + mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, + A_XGM_TX_SPI4_SOP_EOP_CNT + + oft))); +@@ -479,9 +592,21 @@ + return 0; + } + ++/** ++ * t3_mac_disable - disable the MAC in the given directions ++ * @mac: the MAC to configure ++ * @which: bitmap indicating which directions to disable ++ * ++ * Disables the MAC in the given directions. ++ * %MAC_DIRECTION_TX disables the Tx direction, and %MAC_DIRECTION_RX ++ * disables the Rx one. ++ */ + int t3_mac_disable(struct cmac *mac, int which) + { +- struct adapter *adap = mac->adapter; ++ adapter_t *adap = mac->adapter; ++ ++ if (mac->multiport) ++ return t3_vsc7323_disable(adap, mac->ext_port, which); + + if (which & MAC_DIRECTION_TX) { + t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0); +@@ -507,33 +632,38 @@ + + int t3b2_mac_watchdog_task(struct cmac *mac) + { +- struct adapter *adap = mac->adapter; ++ int status; ++ unsigned int tx_tcnt, tx_xcnt; ++ adapter_t *adap = mac->adapter; + struct mac_stats *s = &mac->stats; +- unsigned int tx_tcnt, tx_xcnt; +- unsigned int tx_mcnt = s->tx_frames; +- unsigned int rx_mcnt = s->rx_frames; +- unsigned int rx_xcnt; +- int status; ++ u64 tx_mcnt = s->tx_frames; ++ ++ if (mac->multiport) ++ tx_mcnt = t3_read_reg(adap, A_XGM_STAT_TX_FRAME_LOW); + + status = 0; +- tx_xcnt = 1; /* By default tx_xcnt is making progress */ +- tx_tcnt = mac->tx_tcnt; /* If tx_mcnt is progressing ignore tx_tcnt */ +- rx_xcnt = 1; /* By default rx_xcnt is making progress */ ++ tx_xcnt = 1; /* By default tx_xcnt is making progress*/ ++ tx_tcnt = mac->tx_tcnt; /* If tx_mcnt is progressing ignore tx_tcnt*/ + if (tx_mcnt == mac->tx_mcnt && mac->rx_pause == s->rx_pause) { ++ u32 cfg, active, enforcepkt; ++ + tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, +- A_XGM_TX_SPI4_SOP_EOP_CNT + +- mac->offset))); +- if (tx_xcnt == 0) { ++ A_XGM_TX_SPI4_SOP_EOP_CNT + ++ mac->offset))); ++ cfg = t3_read_reg(adap, A_MPS_CFG); ++ active = macidx(mac) ? cfg & F_PORT1ACTIVE : cfg & F_PORT0ACTIVE; ++ enforcepkt = cfg & F_ENFORCEPKT; ++ if (active && enforcepkt && (tx_xcnt == 0)) { + t3_write_reg(adap, A_TP_PIO_ADDR, +- A_TP_TX_DROP_CNT_CH0 + macidx(mac)); ++ A_TP_TX_DROP_CNT_CH0 + macidx(mac)); + tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap, +- A_TP_PIO_DATA))); +- } else { +- goto rxcheck; +- } ++ A_TP_PIO_DATA))); ++ } else ++ goto out; ++ + } else { + mac->toggle_cnt = 0; +- goto rxcheck; ++ goto out; + } + + if ((tx_tcnt != mac->tx_tcnt) && (mac->tx_xcnt == 0)) { +@@ -546,23 +676,6 @@ + } + } else { + mac->toggle_cnt = 0; +- goto rxcheck; +- } +- +-rxcheck: +- if (rx_mcnt != mac->rx_mcnt) { +- rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, +- A_XGM_RX_SPI4_SOP_EOP_CNT + +- mac->offset))) + +- (s->rx_fifo_ovfl - +- mac->rx_ocnt); +- mac->rx_ocnt = s->rx_fifo_ovfl; +- } else +- goto out; +- +- if (mac->rx_mcnt != s->rx_frames && rx_xcnt == 0 && +- mac->rx_xcnt == 0) { +- status = 2; + goto out; + } + +@@ -570,8 +683,6 @@ + mac->tx_tcnt = tx_tcnt; + mac->tx_xcnt = tx_xcnt; + mac->tx_mcnt = s->tx_frames; +- mac->rx_xcnt = rx_xcnt; +- mac->rx_mcnt = s->rx_frames; + mac->rx_pause = s->rx_pause; + if (status == 1) { + t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0); +@@ -586,12 +697,15 @@ + return status; + } + +-/* +- * This function is called periodically to accumulate the current values of the +- * RMON counters into the port statistics. Since the packet counters are only +- * 32 bits they can overflow in ~286 secs at 10G, so the function should be +- * called more frequently than that. The byte counters are 45-bit wide, they +- * would overflow in ~7.8 hours. ++/** ++ * t3_mac_update_stats - accumulate MAC statistics ++ * @mac: the MAC handle ++ * ++ * This function is called periodically to accumulate the current values ++ * of the RMON counters into the port statistics. Since the packet ++ * counters are only 32 bits they can overflow in ~286 secs at 10G, so the ++ * function should be called more frequently than that. The byte counters ++ * are 45-bit wide, they would overflow in ~7.8 hours. + */ + const struct mac_stats *t3_mac_update_stats(struct cmac *mac) + { +@@ -603,6 +717,9 @@ + ((u64)RMON_READ(mac, A_XGM_STAT_##reg_hi) << 32) + + u32 v, lo; ++ ++ if (mac->multiport) ++ return t3_vsc7323_update_stats(mac); + + RMON_UPDATE64(mac, rx_octets, RX_BYTES_LOW, RX_BYTES_HIGH); + RMON_UPDATE64(mac, rx_frames, RX_FRAMES_LOW, RX_FRAMES_HIGH); +@@ -621,13 +738,13 @@ + v &= 0x7fffffff; + mac->stats.rx_too_long += v; + +- RMON_UPDATE(mac, rx_frames_64, RX_64B_FRAMES); +- RMON_UPDATE(mac, rx_frames_65_127, RX_65_127B_FRAMES); +- RMON_UPDATE(mac, rx_frames_128_255, RX_128_255B_FRAMES); +- RMON_UPDATE(mac, rx_frames_256_511, RX_256_511B_FRAMES); +- RMON_UPDATE(mac, rx_frames_512_1023, RX_512_1023B_FRAMES); ++ RMON_UPDATE(mac, rx_frames_64, RX_64B_FRAMES); ++ RMON_UPDATE(mac, rx_frames_65_127, RX_65_127B_FRAMES); ++ RMON_UPDATE(mac, rx_frames_128_255, RX_128_255B_FRAMES); ++ RMON_UPDATE(mac, rx_frames_256_511, RX_256_511B_FRAMES); ++ RMON_UPDATE(mac, rx_frames_512_1023, RX_512_1023B_FRAMES); + RMON_UPDATE(mac, rx_frames_1024_1518, RX_1024_1518B_FRAMES); +- RMON_UPDATE(mac, rx_frames_1519_max, RX_1519_MAXB_FRAMES); ++ RMON_UPDATE(mac, rx_frames_1519_max, RX_1519_MAXB_FRAMES); + + RMON_UPDATE64(mac, tx_octets, TX_BYTE_LOW, TX_BYTE_HIGH); + RMON_UPDATE64(mac, tx_frames, TX_FRAME_LOW, TX_FRAME_HIGH); +@@ -637,19 +754,19 @@ + /* This counts error frames in general (bad FCS, underrun, etc). */ + RMON_UPDATE(mac, tx_underrun, TX_ERR_FRAMES); + +- RMON_UPDATE(mac, tx_frames_64, TX_64B_FRAMES); +- RMON_UPDATE(mac, tx_frames_65_127, TX_65_127B_FRAMES); +- RMON_UPDATE(mac, tx_frames_128_255, TX_128_255B_FRAMES); +- RMON_UPDATE(mac, tx_frames_256_511, TX_256_511B_FRAMES); +- RMON_UPDATE(mac, tx_frames_512_1023, TX_512_1023B_FRAMES); ++ RMON_UPDATE(mac, tx_frames_64, TX_64B_FRAMES); ++ RMON_UPDATE(mac, tx_frames_65_127, TX_65_127B_FRAMES); ++ RMON_UPDATE(mac, tx_frames_128_255, TX_128_255B_FRAMES); ++ RMON_UPDATE(mac, tx_frames_256_511, TX_256_511B_FRAMES); ++ RMON_UPDATE(mac, tx_frames_512_1023, TX_512_1023B_FRAMES); + RMON_UPDATE(mac, tx_frames_1024_1518, TX_1024_1518B_FRAMES); +- RMON_UPDATE(mac, tx_frames_1519_max, TX_1519_MAXB_FRAMES); ++ RMON_UPDATE(mac, tx_frames_1519_max, TX_1519_MAXB_FRAMES); + + /* The next stat isn't clear-on-read. */ + t3_write_reg(mac->adapter, A_TP_MIB_INDEX, mac->offset ? 51 : 50); + v = t3_read_reg(mac->adapter, A_TP_MIB_RDATA); +- lo = (u32) mac->stats.rx_cong_drops; +- mac->stats.rx_cong_drops += (u64) (v - lo); ++ lo = (u32)mac->stats.rx_cong_drops; ++ mac->stats.rx_cong_drops += (u64)(v - lo); + + return &mac->stats; + } diff --git a/master/debug-dump-skb-info-when-invalid b/master/debug-dump-skb-info-when-invalid index 1d838af..db14905 100644 --- a/master/debug-dump-skb-info-when-invalid +++ b/master/debug-dump-skb-info-when-invalid @@ -13,7 +13,7 @@ diff -r 2f8aba290013 include/linux/skbuff.h diff -r 2f8aba290013 net/core/skbuff.c --- a/net/core/skbuff.c Fri May 15 15:10:10 2009 +0100 +++ b/net/core/skbuff.c Fri May 15 15:11:31 2009 +0100 -@@ -64,11 +64,104 @@ +@@ -64,11 +64,100 @@ #include #include @@ -46,10 +46,6 @@ diff -r 2f8aba290013 net/core/skbuff.c + skb->local_df, skb->cloned, skb->ip_summed, skb->nohdr); + printk(KERN_ERR "skb: nfctinfo:%d pkt_type:%d fclone:%d ipvs_property:%d\n", + skb->nfctinfo, skb->pkt_type, skb->nohdr, skb->ipvs_property); -+#ifdef CONFIG_XEN -+ printk(KERN_ERR "skb: proto_data_valid:%d proto_csum_blank:%d\n", -+ skb->proto_data_valid, skb->proto_csum_blank); -+#endif + printk(KERN_ERR "skb: shared info %p ref %#x\n", skb_shinfo(skb), atomic_read(&skb_shinfo(skb)->dataref)); + printk(KERN_ERR "skb: frag_list %p\n", skb_shinfo(skb)->frag_list); + diff --git a/master/e1000-8.0.16.patch b/master/e1000-8.0.16.patch new file mode 100644 index 0000000..17c1e81 --- /dev/null +++ b/master/e1000-8.0.16.patch @@ -0,0 +1,31374 @@ +diff -r b58885ce604a drivers/net/e1000/Makefile +--- a/drivers/net/e1000/Makefile Wed Aug 05 09:27:10 2009 +0100 ++++ b/drivers/net/e1000/Makefile Wed Aug 05 11:02:21 2009 +0100 +@@ -32,4 +32,11 @@ + + obj-$(CONFIG_E1000) += e1000.o + +-e1000-objs := e1000_main.o e1000_hw.o e1000_ethtool.o e1000_param.o ++FAMILYC = e1000_82540.c e1000_82542.c e1000_82541.c e1000_82543.c ++ ++CFILES = e1000_main.c $(FAMILYC) e1000_mac.c e1000_nvm.c e1000_phy.c \ ++ e1000_manage.c e1000_param.c e1000_ethtool.c kcompat.c e1000_api.c ++ ++e1000-objs := $(CFILES:.c=.o) ++ ++EXTRA_CFLAGS += -DDRIVER_E1000 +diff -r b58885ce604a drivers/net/e1000/e1000.h +--- a/drivers/net/e1000/e1000.h Wed Aug 05 09:27:10 2009 +0100 ++++ b/drivers/net/e1000/e1000.h Wed Aug 05 11:02:21 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel PRO/1000 Linux driver +- Copyright(c) 1999 - 2006 Intel Corporation. ++ Copyright(c) 1999 - 2008 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -32,43 +32,9 @@ + #ifndef _E1000_H_ + #define _E1000_H_ + +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include ++#include "kcompat.h" ++ ++#include "e1000_api.h" + + #define BAR_0 0 + #define BAR_1 1 +@@ -79,24 +45,15 @@ + + struct e1000_adapter; + +-#include "e1000_hw.h" +- +-#ifdef DBG +-#define E1000_DBG(args...) printk(KERN_DEBUG "e1000: " args) +-#else + #define E1000_DBG(args...) +-#endif + + #define E1000_ERR(args...) printk(KERN_ERR "e1000: " args) + + #define PFX "e1000: " +- +-#define DPRINTK(nlevel, klevel, fmt, args...) \ +-do { \ +- if (NETIF_MSG_##nlevel & adapter->msg_enable) \ +- printk(KERN_##klevel PFX "%s: %s: " fmt, \ +- adapter->netdev->name, __func__, ##args); \ +-} while (0) ++#define DPRINTK(nlevel, klevel, fmt, args...) \ ++ (void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \ ++ printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \ ++ __FUNCTION__ , ## args)) + + #define E1000_MAX_INTR 10 + +@@ -106,17 +63,26 @@ + #define E1000_MIN_TXD 80 + #define E1000_MAX_82544_TXD 4096 + ++#define E1000_DEFAULT_TXD_PWR 12 ++#define E1000_MAX_TXD_PWR 12 ++#define E1000_MIN_TXD_PWR 7 ++ + #define E1000_DEFAULT_RXD 256 + #define E1000_MAX_RXD 256 ++ + #define E1000_MIN_RXD 80 + #define E1000_MAX_82544_RXD 4096 ++ ++#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ ++#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ ++ + + /* this is the size past which hardware will drop packets when setting LPE=0 */ + #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 + + /* Supported Rx Buffer Sizes */ +-#define E1000_RXBUFFER_128 128 /* Used for packet split */ +-#define E1000_RXBUFFER_256 256 /* Used for packet split */ ++#define E1000_RXBUFFER_128 128 ++#define E1000_RXBUFFER_256 256 + #define E1000_RXBUFFER_512 512 + #define E1000_RXBUFFER_1024 1024 + #define E1000_RXBUFFER_2048 2048 +@@ -133,9 +99,8 @@ + #define E1000_TX_HEAD_ADDR_SHIFT 7 + #define E1000_PBA_TX_MASK 0xFFFF0000 + +-/* Flow Control Watermarks */ +-#define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ +-#define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ ++/* Early Receive defines */ ++#define E1000_ERT_2048 0x100 + + #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ + +@@ -146,7 +111,6 @@ + + #define AUTO_ALL_MODES 0 + #define E1000_EEPROM_82544_APM 0x0004 +-#define E1000_EEPROM_ICH8_APME 0x0004 + #define E1000_EEPROM_APME 0x0400 + + #ifndef E1000_MASTER_SLAVE +@@ -154,9 +118,9 @@ + #define E1000_MASTER_SLAVE e1000_ms_hw_default + #endif + +-#define E1000_MNG_VLAN_NONE (-1) +-/* Number of packet split data buffers (not including the header buffer) */ +-#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) ++#ifdef NETIF_F_HW_VLAN_TX ++#define E1000_MNG_VLAN_NONE -1 ++#endif + + /* wrapper around a pointer to a socket buffer, + * so a DMA handle can be stored along with the buffer */ +@@ -168,13 +132,13 @@ + u16 next_to_watch; + }; + +-struct e1000_ps_page { +- struct page *ps_page[PS_PAGE_BUFFERS]; ++struct e1000_rx_buffer { ++ struct sk_buff *skb; ++ dma_addr_t dma; ++ struct page *page; + }; ++ + +-struct e1000_ps_page_dma { +- u64 ps_page_dma[PS_PAGE_BUFFERS]; +-}; + + struct e1000_tx_ring { + /* pointer to the descriptor ring memory */ +@@ -195,10 +159,20 @@ + spinlock_t tx_lock; + u16 tdh; + u16 tdt; ++ ++ /* TXDdescriptor index increment to be used when advancing ++ * to the next descriptor. This is normally one, but on some ++ * architectures, but on some architectures there are cache ++ * coherency issues that require only the first descriptor in ++ * cache line can be used. ++ */ ++ unsigned int step; ++ + bool last_tx_tso; + }; + + struct e1000_rx_ring { ++ struct e1000_adapter *adapter; /* back link */ + /* pointer to the descriptor ring memory */ + void *desc; + /* physical address of the descriptor ring */ +@@ -211,11 +185,12 @@ + unsigned int next_to_use; + /* next descriptor to check for DD status bit */ + unsigned int next_to_clean; ++#ifdef CONFIG_E1000_NAPI ++ struct napi_struct napi; ++#endif + /* array of buffer information structs */ +- struct e1000_buffer *buffer_info; +- /* arrays of page information for packet split */ +- struct e1000_ps_page *ps_page; +- struct e1000_ps_page_dma *ps_page_dma; ++ struct e1000_rx_buffer *buffer_info; ++ struct sk_buff *rx_skb_top; + + /* cpu for rx queue */ + int cpu; +@@ -224,18 +199,38 @@ + u16 rdt; + }; + +-#define E1000_DESC_UNUSED(R) \ +- ((((R)->next_to_clean > (R)->next_to_use) \ +- ? 0 : (R)->count) + (R)->next_to_clean - (R)->next_to_use - 1) + +-#define E1000_RX_DESC_PS(R, i) \ +- (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) +-#define E1000_RX_DESC_EXT(R, i) \ ++#define E1000_TX_DESC_INC(R,index) \ ++ {index += (R)->step; if (index == (R)->count) index = 0; } ++ ++#define E1000_TX_DESC_DEC(R,index) \ ++ { if (index == 0) index = (R)->count - (R)->step; \ ++ else index -= (R)->step; } ++ ++#define E1000_DESC_UNUSED(R) \ ++ ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ ++ (R)->next_to_clean - (R)->next_to_use - 1) ++ ++#define E1000_RX_DESC_EXT(R, i) \ + (&(((union e1000_rx_desc_extended *)((R).desc))[i])) + #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) + #define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc) + #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) + #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) ++ ++#ifdef SIOCGMIIPHY ++/* PHY register snapshot values */ ++struct e1000_phy_regs { ++ u16 bmcr; /* basic mode control register */ ++ u16 bmsr; /* basic mode status register */ ++ u16 advertise; /* auto-negotiation advertisement */ ++ u16 lpa; /* link partner ability register */ ++ u16 expansion; /* auto-negotiation expansion reg */ ++ u16 ctrl1000; /* 1000BASE-T control register */ ++ u16 stat1000; /* 1000BASE-T status register */ ++ u16 estatus; /* extended status register */ ++}; ++#endif + + /* board specific private data structure */ + +@@ -243,8 +238,10 @@ + struct timer_list tx_fifo_stall_timer; + struct timer_list watchdog_timer; + struct timer_list phy_info_timer; ++#ifdef NETIF_F_HW_VLAN_TX + struct vlan_group *vlgrp; + u16 mng_vlan_id; ++#endif + u32 bd_number; + u32 rx_buffer_len; + u32 wol; +@@ -253,7 +250,6 @@ + u16 link_speed; + u16 link_duplex; + spinlock_t stats_lock; +- spinlock_t tx_queue_lock; + unsigned int total_tx_bytes; + unsigned int total_tx_packets; + unsigned int total_rx_bytes; +@@ -265,56 +261,59 @@ + u16 rx_itr; + + struct work_struct reset_task; +- u8 fc_autoneg; ++ struct work_struct watchdog_task; ++ bool fc_autoneg; + ++#ifdef ETHTOOL_PHYS_ID + struct timer_list blink_timer; + unsigned long led_status; ++#endif + + /* TX */ +- struct e1000_tx_ring *tx_ring; /* One per active queue */ ++ struct e1000_tx_ring *tx_ring; + unsigned int restart_queue; + unsigned long tx_queue_len; + u32 txd_cmd; + u32 tx_int_delay; + u32 tx_abs_int_delay; +- u32 gotcl; +- u64 gotcl_old; ++ u32 gotc; ++ u64 gotc_old; + u64 tpt_old; + u64 colc_old; + u32 tx_timeout_count; + u32 tx_fifo_head; + u32 tx_head_addr; + u32 tx_fifo_size; +- u8 tx_timeout_factor; ++ u8 tx_timeout_factor; + atomic_t tx_fifo_stall; + bool pcix_82544; + bool detect_tx_hung; + + /* RX */ +- bool (*clean_rx)(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rx_ring, +- int *work_done, int work_to_do); +- void (*alloc_rx_buf)(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rx_ring, +- int cleaned_count); +- struct e1000_rx_ring *rx_ring; /* One per active queue */ +- struct napi_struct napi; +- struct net_device *polling_netdev; /* One per active queue */ +- +- int num_tx_queues; +- int num_rx_queues; ++#ifdef CONFIG_E1000_NAPI ++ bool (*clean_rx) (struct e1000_adapter *adapter, ++ struct e1000_rx_ring *rx_ring, ++ int *work_done, int work_to_do); ++#else ++ bool (*clean_rx) (struct e1000_adapter *adapter, ++ struct e1000_rx_ring *rx_ring); ++#endif ++ void (*alloc_rx_buf) (struct e1000_adapter *adapter, ++ struct e1000_rx_ring *rx_ring, ++ int cleaned_count); ++ struct e1000_rx_ring *rx_ring; + + u64 hw_csum_err; + u64 hw_csum_good; +- u64 rx_hdr_split; + u32 alloc_rx_buff_failed; + u32 rx_int_delay; + u32 rx_abs_int_delay; + bool rx_csum; +- unsigned int rx_ps_pages; +- u32 gorcl; +- u64 gorcl_old; +- u16 rx_ps_bsize0; ++ u32 gorc; ++ u64 gorc_old; ++ u32 max_frame_size; ++ u32 min_frame_size; ++ + + /* OS defined structs */ + struct net_device *netdev; +@@ -327,24 +326,41 @@ + struct e1000_phy_info phy_info; + struct e1000_phy_stats phy_stats; + ++#ifdef SIOCGMIIPHY ++ /* Snapshot of PHY registers */ ++ struct e1000_phy_regs phy_regs; ++#endif ++ ++#ifdef ETHTOOL_TEST + u32 test_icr; + struct e1000_tx_ring test_tx_ring; + struct e1000_rx_ring test_rx_ring; ++#endif ++ + + int msg_enable; +- bool have_msi; +- + /* to not mess up cache alignment, always add to the bottom */ +- bool tso_force; +- bool smart_power_down; /* phy smart power down */ +- bool quad_port_a; +- unsigned long flags; ++ unsigned long state; + u32 eeprom_wol; + +- /* for ioport free */ +- int bars; +- int need_ioport; ++ u32 *config_space; ++ ++ /* hardware capability, feature, and workaround flags */ ++ unsigned int flags; ++ ++ /* upper limit parameter for tx desc size */ ++ u32 tx_desc_pwr; + }; ++ ++#define E1000_FLAG_HAS_SMBUS (1 << 0) ++#define E1000_FLAG_HAS_INTR_MODERATION (1 << 4) ++#define E1000_FLAG_BAD_TX_CARRIER_STATS_FD (1 << 6) ++#define E1000_FLAG_QUAD_PORT_A (1 << 8) ++#define E1000_FLAG_SMART_POWER_DOWN (1 << 9) ++#ifdef NETIF_F_TSO ++#define E1000_FLAG_HAS_TSO (1 << 10) ++#define E1000_FLAG_TSO_FORCE (1 << 12) ++#endif + + enum e1000_state_t { + __E1000_TESTING, +@@ -354,6 +370,11 @@ + + extern char e1000_driver_name[]; + extern const char e1000_driver_version[]; ++ ++extern void e1000_power_up_phy(struct e1000_hw *hw); ++ ++extern void e1000_set_ethtool_ops(struct net_device *netdev); ++extern void e1000_check_options(struct e1000_adapter *adapter); + + extern int e1000_up(struct e1000_adapter *adapter); + extern void e1000_down(struct e1000_adapter *adapter); +@@ -365,8 +386,8 @@ + extern void e1000_free_all_rx_resources(struct e1000_adapter *adapter); + extern void e1000_free_all_tx_resources(struct e1000_adapter *adapter); + extern void e1000_update_stats(struct e1000_adapter *adapter); +-extern void e1000_power_up_phy(struct e1000_adapter *); +-extern void e1000_set_ethtool_ops(struct net_device *netdev); +-extern void e1000_check_options(struct e1000_adapter *adapter); ++#ifdef ETHTOOL_OPS_COMPAT ++extern int ethtool_ioctl(struct ifreq *ifr); ++#endif + + #endif /* _E1000_H_ */ +diff -r b58885ce604a drivers/net/e1000/e1000_80003es2lan.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_80003es2lan.h Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,95 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_80003ES2LAN_H_ ++#define _E1000_80003ES2LAN_H_ ++ ++#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 ++#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 ++#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 ++#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F ++ ++#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 ++#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 ++#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 ++ ++#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 ++#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 ++#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 ++ ++#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ ++#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 ++ ++#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 ++#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 ++ ++/* GG82563 PHY Specific Status Register (Page 0, Register 16 */ ++#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disabled */ ++#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 ++#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ ++#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ ++#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ ++ ++/* PHY Specific Control Register 2 (Page 0, Register 26) */ ++#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 ++ /* 1=Reverse Auto-Negotiation */ ++ ++/* MAC Specific Control Register (Page 2, Register 21) */ ++/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ ++#define GG82563_MSCR_TX_CLK_MASK 0x0007 ++#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 ++#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 ++#define GG82563_MSCR_TX_CLK_1000MBPS_2_5 0x0006 ++#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 ++ ++#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ ++ ++/* DSP Distance Register (Page 5, Register 26) */ ++/* ++ * 0 = <50M ++ * 1 = 50-80M ++ * 2 = 80-100M ++ * 3 = 110-140M ++ * 4 = >140M ++ */ ++#define GG82563_DSPD_CABLE_LENGTH 0x0007 ++ ++/* Kumeran Mode Control Register (Page 193, Register 16) */ ++#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 ++ ++/* Max number of times Kumeran read/write should be validated */ ++#define GG82563_MAX_KMRN_RETRY 0x5 ++ ++/* Power Management Control Register (Page 193, Register 20) */ ++#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 ++ /* 1=Enable SERDES Electrical Idle */ ++ ++/* In-Band Control Register (Page 194, Register 18) */ ++#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ ++ ++#endif +diff -r b58885ce604a drivers/net/e1000/e1000_82540.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_82540.c Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,717 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * 82540EM Gigabit Ethernet Controller ++ * 82540EP Gigabit Ethernet Controller ++ * 82545EM Gigabit Ethernet Controller (Copper) ++ * 82545EM Gigabit Ethernet Controller (Fiber) ++ * 82545GM Gigabit Ethernet Controller ++ * 82546EB Gigabit Ethernet Controller (Copper) ++ * 82546EB Gigabit Ethernet Controller (Fiber) ++ * 82546GB Gigabit Ethernet Controller ++ */ ++ ++#include "e1000_api.h" ++ ++static s32 e1000_init_phy_params_82540(struct e1000_hw *hw); ++static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw); ++static s32 e1000_init_mac_params_82540(struct e1000_hw *hw); ++static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw); ++static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw); ++static s32 e1000_init_hw_82540(struct e1000_hw *hw); ++static s32 e1000_reset_hw_82540(struct e1000_hw *hw); ++static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw); ++static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw); ++static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw); ++static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw); ++static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw); ++static s32 e1000_read_mac_addr_82540(struct e1000_hw *hw); ++ ++/** ++ * e1000_init_phy_params_82540 - Init PHY func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_phy_params_82540(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ ++ phy->addr = 1; ++ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; ++ phy->reset_delay_us = 10000; ++ phy->type = e1000_phy_m88; ++ ++ /* Function Pointers */ ++ phy->ops.check_polarity = e1000_check_polarity_m88; ++ phy->ops.commit = e1000_phy_sw_reset_generic; ++ phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; ++ phy->ops.get_cable_length = e1000_get_cable_length_m88; ++ phy->ops.get_cfg_done = e1000_get_cfg_done_generic; ++ phy->ops.read_reg = e1000_read_phy_reg_m88; ++ phy->ops.reset = e1000_phy_hw_reset_generic; ++ phy->ops.write_reg = e1000_write_phy_reg_m88; ++ phy->ops.get_info = e1000_get_phy_info_m88; ++ phy->ops.power_up = e1000_power_up_phy_copper; ++ phy->ops.power_down = e1000_power_down_phy_copper_82540; ++ ++ ret_val = e1000_get_phy_id(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Verify phy id */ ++ switch (hw->mac.type) { ++ case e1000_82540: ++ case e1000_82545: ++ case e1000_82545_rev_3: ++ case e1000_82546: ++ case e1000_82546_rev_3: ++ if (phy->id == M88E1011_I_PHY_ID) ++ break; ++ /* Fall Through */ ++ default: ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ break; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_nvm_params_82540 - Init NVM func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = E1000_READ_REG(hw, E1000_EECD); ++ ++ DEBUGFUNC("e1000_init_nvm_params_82540"); ++ ++ nvm->type = e1000_nvm_eeprom_microwire; ++ nvm->delay_usec = 50; ++ nvm->opcode_bits = 3; ++ switch (nvm->override) { ++ case e1000_nvm_override_microwire_large: ++ nvm->address_bits = 8; ++ nvm->word_size = 256; ++ break; ++ case e1000_nvm_override_microwire_small: ++ nvm->address_bits = 6; ++ nvm->word_size = 64; ++ break; ++ default: ++ nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6; ++ nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64; ++ break; ++ } ++ ++ /* Function Pointers */ ++ nvm->ops.acquire = e1000_acquire_nvm_generic; ++ nvm->ops.read = e1000_read_nvm_microwire; ++ nvm->ops.release = e1000_release_nvm_generic; ++ nvm->ops.update = e1000_update_nvm_checksum_generic; ++ nvm->ops.valid_led_default = e1000_valid_led_default_generic; ++ nvm->ops.validate = e1000_validate_nvm_checksum_generic; ++ nvm->ops.write = e1000_write_nvm_microwire; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_init_mac_params_82540 - Init MAC func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_mac_params_82540(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_init_mac_params_82540"); ++ ++ /* Set media type */ ++ switch (hw->device_id) { ++ case E1000_DEV_ID_82545EM_FIBER: ++ case E1000_DEV_ID_82545GM_FIBER: ++ case E1000_DEV_ID_82546EB_FIBER: ++ case E1000_DEV_ID_82546GB_FIBER: ++ hw->phy.media_type = e1000_media_type_fiber; ++ break; ++ case E1000_DEV_ID_82545GM_SERDES: ++ case E1000_DEV_ID_82546GB_SERDES: ++ hw->phy.media_type = e1000_media_type_internal_serdes; ++ break; ++ default: ++ hw->phy.media_type = e1000_media_type_copper; ++ break; ++ } ++ ++ /* Set mta register count */ ++ mac->mta_reg_count = 128; ++ /* Set rar entry count */ ++ mac->rar_entry_count = E1000_RAR_ENTRIES; ++ ++ /* Function pointers */ ++ ++ /* bus type/speed/width */ ++ mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; ++ /* function id */ ++ mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; ++ /* reset */ ++ mac->ops.reset_hw = e1000_reset_hw_82540; ++ /* hw initialization */ ++ mac->ops.init_hw = e1000_init_hw_82540; ++ /* link setup */ ++ mac->ops.setup_link = e1000_setup_link_generic; ++ /* physical interface setup */ ++ mac->ops.setup_physical_interface = ++ (hw->phy.media_type == e1000_media_type_copper) ++ ? e1000_setup_copper_link_82540 ++ : e1000_setup_fiber_serdes_link_82540; ++ /* check for link */ ++ switch (hw->phy.media_type) { ++ case e1000_media_type_copper: ++ mac->ops.check_for_link = e1000_check_for_copper_link_generic; ++ break; ++ case e1000_media_type_fiber: ++ mac->ops.check_for_link = e1000_check_for_fiber_link_generic; ++ break; ++ case e1000_media_type_internal_serdes: ++ mac->ops.check_for_link = e1000_check_for_serdes_link_generic; ++ break; ++ default: ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ break; ++ } ++ /* link info */ ++ mac->ops.get_link_up_info = ++ (hw->phy.media_type == e1000_media_type_copper) ++ ? e1000_get_speed_and_duplex_copper_generic ++ : e1000_get_speed_and_duplex_fiber_serdes_generic; ++ /* multicast address update */ ++ mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; ++ /* writing VFTA */ ++ mac->ops.write_vfta = e1000_write_vfta_generic; ++ /* clearing VFTA */ ++ mac->ops.clear_vfta = e1000_clear_vfta_generic; ++ /* setting MTA */ ++ mac->ops.mta_set = e1000_mta_set_generic; ++ /* read mac address */ ++ mac->ops.read_mac_addr = e1000_read_mac_addr_82540; ++ /* ID LED init */ ++ mac->ops.id_led_init = e1000_id_led_init_generic; ++ /* setup LED */ ++ mac->ops.setup_led = e1000_setup_led_generic; ++ /* cleanup LED */ ++ mac->ops.cleanup_led = e1000_cleanup_led_generic; ++ /* turn on/off LED */ ++ mac->ops.led_on = e1000_led_on_generic; ++ mac->ops.led_off = e1000_led_off_generic; ++ /* clear hardware counters */ ++ mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_function_pointers_82540 - Init func ptrs. ++ * @hw: pointer to the HW structure ++ * ++ * Called to initialize all function pointers and parameters. ++ **/ ++void e1000_init_function_pointers_82540(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_init_function_pointers_82540"); ++ ++ hw->mac.ops.init_params = e1000_init_mac_params_82540; ++ hw->nvm.ops.init_params = e1000_init_nvm_params_82540; ++ hw->phy.ops.init_params = e1000_init_phy_params_82540; ++} ++ ++/** ++ * e1000_reset_hw_82540 - Reset hardware ++ * @hw: pointer to the HW structure ++ * ++ * This resets the hardware into a known state. ++ **/ ++static s32 e1000_reset_hw_82540(struct e1000_hw *hw) ++{ ++ u32 ctrl, icr, manc; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_reset_hw_82540"); ++ ++ DEBUGOUT("Masking off all interrupts\n"); ++ E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); ++ ++ E1000_WRITE_REG(hw, E1000_RCTL, 0); ++ E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); ++ E1000_WRITE_FLUSH(hw); ++ ++ /* ++ * Delay to allow any outstanding PCI transactions to complete ++ * before resetting the device. ++ */ ++ msec_delay(10); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n"); ++ switch (hw->mac.type) { ++ case e1000_82545_rev_3: ++ case e1000_82546_rev_3: ++ E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST); ++ break; ++ default: ++ /* ++ * These controllers can't ack the 64-bit write when ++ * issuing the reset, so we use IO-mapping as a ++ * workaround to issue the reset. ++ */ ++ E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); ++ break; ++ } ++ ++ /* Wait for EEPROM reload */ ++ msec_delay(5); ++ ++ /* Disable HW ARPs on ASF enabled adapters */ ++ manc = E1000_READ_REG(hw, E1000_MANC); ++ manc &= ~E1000_MANC_ARP_EN; ++ E1000_WRITE_REG(hw, E1000_MANC, manc); ++ ++ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); ++ icr = E1000_READ_REG(hw, E1000_ICR); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_init_hw_82540 - Initialize hardware ++ * @hw: pointer to the HW structure ++ * ++ * This inits the hardware readying it for operation. ++ **/ ++static s32 e1000_init_hw_82540(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 txdctl, ctrl_ext; ++ s32 ret_val = E1000_SUCCESS; ++ u16 i; ++ ++ DEBUGFUNC("e1000_init_hw_82540"); ++ ++ /* Initialize identification LED */ ++ ret_val = mac->ops.id_led_init(hw); ++ if (ret_val) { ++ DEBUGOUT("Error initializing identification LED\n"); ++ /* This is not fatal and we should not stop init due to this */ ++ } ++ ++ /* Disabling VLAN filtering */ ++ DEBUGOUT("Initializing the IEEE VLAN\n"); ++ if (mac->type < e1000_82545_rev_3) ++ E1000_WRITE_REG(hw, E1000_VET, 0); ++ ++ mac->ops.clear_vfta(hw); ++ ++ /* Setup the receive address. */ ++ e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); ++ ++ /* Zero out the Multicast HASH table */ ++ DEBUGOUT("Zeroing the MTA\n"); ++ for (i = 0; i < mac->mta_reg_count; i++) { ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); ++ /* ++ * Avoid back to back register writes by adding the register ++ * read (flush). This is to protect against some strange ++ * bridge configurations that may issue Memory Write Block ++ * (MWB) to our register space. The *_rev_3 hardware at ++ * least doesn't respond correctly to every other dword in an ++ * MWB to our register space. ++ */ ++ E1000_WRITE_FLUSH(hw); ++ } ++ ++ if (mac->type < e1000_82545_rev_3) ++ e1000_pcix_mmrbc_workaround_generic(hw); ++ ++ /* Setup link and flow control */ ++ ret_val = mac->ops.setup_link(hw); ++ ++ txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); ++ txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB; ++ E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); ++ ++ /* ++ * Clear all of the statistics registers (clear on read). It is ++ * important that we do this after we have tried to establish link ++ * because the symbol error count will increment wildly if there ++ * is no link. ++ */ ++ e1000_clear_hw_cntrs_82540(hw); ++ ++ if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) || ++ (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) { ++ ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); ++ /* ++ * Relaxed ordering must be disabled to avoid a parity ++ * error crash in a PCI slot. ++ */ ++ ctrl_ext |= E1000_CTRL_EXT_RO_DIS; ++ E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_copper_link_82540 - Configure copper link settings ++ * @hw: pointer to the HW structure ++ * ++ * Calls the appropriate function to configure the link for auto-neg or forced ++ * speed and duplex. Then we check for link, once link is established calls ++ * to configure collision distance and flow control are called. If link is ++ * not established, we return -E1000_ERR_PHY (-2). ++ **/ ++static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ u16 data; ++ ++ DEBUGFUNC("e1000_setup_copper_link_82540"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl |= E1000_CTRL_SLU; ++ ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++ ret_val = e1000_set_phy_mode_82540(hw); ++ if (ret_val) ++ goto out; ++ ++ if (hw->mac.type == e1000_82545_rev_3 || ++ hw->mac.type == e1000_82546_rev_3) { ++ ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data); ++ if (ret_val) ++ goto out; ++ data |= 0x00000008; ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = e1000_copper_link_setup_m88(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_setup_copper_link_generic(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes ++ * @hw: pointer to the HW structure ++ * ++ * Set the output amplitude to the value in the EEPROM and adjust the VCO ++ * speed to improve Bit Error Rate (BER) performance. Configures collision ++ * distance and flow control for fiber and serdes links. Upon successful ++ * setup, poll for link. ++ **/ ++static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_setup_fiber_serdes_link_82540"); ++ ++ switch (mac->type) { ++ case e1000_82545_rev_3: ++ case e1000_82546_rev_3: ++ if (hw->phy.media_type == e1000_media_type_internal_serdes) { ++ /* ++ * If we're on serdes media, adjust the output ++ * amplitude to value set in the EEPROM. ++ */ ++ ret_val = e1000_adjust_serdes_amplitude_82540(hw); ++ if (ret_val) ++ goto out; ++ } ++ /* Adjust VCO speed to improve BER performance */ ++ ret_val = e1000_set_vco_speed_82540(hw); ++ if (ret_val) ++ goto out; ++ default: ++ break; ++ } ++ ++ ret_val = e1000_setup_fiber_serdes_link_generic(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Adjust the SERDES output amplitude based on the EEPROM settings. ++ **/ ++static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 nvm_data; ++ ++ DEBUGFUNC("e1000_adjust_serdes_amplitude_82540"); ++ ++ ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data); ++ if (ret_val) ++ goto out; ++ ++ if (nvm_data != NVM_RESERVED_WORD) { ++ /* Adjust serdes output amplitude only. */ ++ nvm_data &= NVM_SERDES_AMPLITUDE_MASK; ++ ret_val = hw->phy.ops.write_reg(hw, ++ M88E1000_PHY_EXT_CTRL, ++ nvm_data); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_set_vco_speed_82540 - Set VCO speed for better performance ++ * @hw: pointer to the HW structure ++ * ++ * Set the VCO speed to improve Bit Error Rate (BER) performance. ++ **/ ++static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 default_page = 0; ++ u16 phy_data; ++ ++ DEBUGFUNC("e1000_set_vco_speed_82540"); ++ ++ /* Set PHY register 30, page 5, bit 8 to 0 */ ++ ++ ret_val = hw->phy.ops.read_reg(hw, ++ M88E1000_PHY_PAGE_SELECT, ++ &default_page); ++ if (ret_val) ++ goto out; ++ ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); ++ if (ret_val) ++ goto out; ++ ++ ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* Set PHY register 30, page 4, bit 11 to 1 */ ++ ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); ++ if (ret_val) ++ goto out; ++ ++ ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data |= M88E1000_PHY_VCO_REG_BIT11; ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, ++ default_page); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_set_phy_mode_82540 - Set PHY to class A mode ++ * @hw: pointer to the HW structure ++ * ++ * Sets the PHY to class A mode and assumes the following operations will ++ * follow to enable the new class mode: ++ * 1. Do a PHY soft reset. ++ * 2. Restart auto-negotiation or force link. ++ **/ ++static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 nvm_data; ++ ++ DEBUGFUNC("e1000_set_phy_mode_82540"); ++ ++ if (hw->mac.type != e1000_82545_rev_3) ++ goto out; ++ ++ ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data); ++ if (ret_val) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++ if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) { ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, ++ 0x000B); ++ if (ret_val) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ret_val = hw->phy.ops.write_reg(hw, ++ M88E1000_PHY_GEN_CONTROL, ++ 0x8104); ++ if (ret_val) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++ phy->reset_disable = false; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down ++ * @hw: pointer to the HW structure ++ * ++ * In the case of a PHY power down to save power, or to turn off link during a ++ * driver unload, or wake on lan is not enabled, remove the link. ++ **/ ++static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw) ++{ ++ /* If the management interface is not enabled, then power down */ ++ if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) ++ e1000_power_down_phy_copper(hw); ++ ++ return; ++} ++ ++/** ++ * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters ++ * @hw: pointer to the HW structure ++ * ++ * Clears the hardware counters by reading the counter registers. ++ **/ ++static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_clear_hw_cntrs_82540"); ++ ++ e1000_clear_hw_cntrs_base_generic(hw); ++ ++ E1000_READ_REG(hw, E1000_PRC64); ++ E1000_READ_REG(hw, E1000_PRC127); ++ E1000_READ_REG(hw, E1000_PRC255); ++ E1000_READ_REG(hw, E1000_PRC511); ++ E1000_READ_REG(hw, E1000_PRC1023); ++ E1000_READ_REG(hw, E1000_PRC1522); ++ E1000_READ_REG(hw, E1000_PTC64); ++ E1000_READ_REG(hw, E1000_PTC127); ++ E1000_READ_REG(hw, E1000_PTC255); ++ E1000_READ_REG(hw, E1000_PTC511); ++ E1000_READ_REG(hw, E1000_PTC1023); ++ E1000_READ_REG(hw, E1000_PTC1522); ++ ++ E1000_READ_REG(hw, E1000_ALGNERRC); ++ E1000_READ_REG(hw, E1000_RXERRC); ++ E1000_READ_REG(hw, E1000_TNCRS); ++ E1000_READ_REG(hw, E1000_CEXTERR); ++ E1000_READ_REG(hw, E1000_TSCTC); ++ E1000_READ_REG(hw, E1000_TSCTFC); ++ ++ E1000_READ_REG(hw, E1000_MGTPRC); ++ E1000_READ_REG(hw, E1000_MGTPDC); ++ E1000_READ_REG(hw, E1000_MGTPTC); ++} ++ ++/** ++ * e1000_read_mac_addr_82540 - Read device MAC address ++ * @hw: pointer to the HW structure ++ * ++ * Reads the device MAC address from the EEPROM and stores the value. ++ * Since devices with two ports use the same EEPROM, we increment the ++ * last bit in the MAC address for the second port. ++ * ++ * This version is being used over generic because of customer issues ++ * with VmWare and Virtual Box when using generic. It seems in ++ * the emulated 82545, RAR[0] does NOT have a valid address after a ++ * reset, this older method works and using this breaks nothing for ++ * these legacy adapters. ++ **/ ++s32 e1000_read_mac_addr_82540(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 offset, nvm_data, i; ++ ++ DEBUGFUNC("e1000_read_mac_addr"); ++ ++ for (i = 0; i < ETH_ADDR_LEN; i += 2) { ++ offset = i >> 1; ++ ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); ++ if (ret_val) { ++ DEBUGOUT("NVM Read Error\n"); ++ goto out; ++ } ++ hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); ++ hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); ++ } ++ ++ /* Flip last bit of mac address if we're on second port */ ++ if (hw->bus.func == E1000_FUNC_1) ++ hw->mac.perm_addr[5] ^= 1; ++ ++ for (i = 0; i < ETH_ADDR_LEN; i++) ++ hw->mac.addr[i] = hw->mac.perm_addr[i]; ++ ++out: ++ return ret_val; ++} +diff -r b58885ce604a drivers/net/e1000/e1000_82541.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_82541.c Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,1288 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * 82541EI Gigabit Ethernet Controller ++ * 82541ER Gigabit Ethernet Controller ++ * 82541GI Gigabit Ethernet Controller ++ * 82541PI Gigabit Ethernet Controller ++ * 82547EI Gigabit Ethernet Controller ++ * 82547GI Gigabit Ethernet Controller ++ */ ++ ++#include "e1000_api.h" ++ ++static s32 e1000_init_phy_params_82541(struct e1000_hw *hw); ++static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); ++static s32 e1000_init_mac_params_82541(struct e1000_hw *hw); ++static s32 e1000_reset_hw_82541(struct e1000_hw *hw); ++static s32 e1000_init_hw_82541(struct e1000_hw *hw); ++static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex); ++static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); ++static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); ++static s32 e1000_check_for_link_82541(struct e1000_hw *hw); ++static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); ++static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, ++ bool active); ++static s32 e1000_setup_led_82541(struct e1000_hw *hw); ++static s32 e1000_cleanup_led_82541(struct e1000_hw *hw); ++static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); ++static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, ++ bool link_up); ++static s32 e1000_phy_init_script_82541(struct e1000_hw *hw); ++static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw); ++ ++static const u16 e1000_igp_cable_length_table[] = ++ { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, ++ 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, ++ 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, ++ 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, ++ 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, ++ 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, ++ 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, ++ 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; ++#define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ ++ (sizeof(e1000_igp_cable_length_table) / \ ++ sizeof(e1000_igp_cable_length_table[0])) ++ ++/** ++ * e1000_init_phy_params_82541 - Init PHY func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_phy_params_82541(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_init_phy_params_82541"); ++ ++ phy->addr = 1; ++ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; ++ phy->reset_delay_us = 10000; ++ phy->type = e1000_phy_igp; ++ ++ /* Function Pointers */ ++ phy->ops.check_polarity = e1000_check_polarity_igp; ++ phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; ++ phy->ops.get_cable_length = e1000_get_cable_length_igp_82541; ++ phy->ops.get_cfg_done = e1000_get_cfg_done_generic; ++ phy->ops.get_info = e1000_get_phy_info_igp; ++ phy->ops.read_reg = e1000_read_phy_reg_igp; ++ phy->ops.reset = e1000_phy_hw_reset_82541; ++ phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541; ++ phy->ops.write_reg = e1000_write_phy_reg_igp; ++ phy->ops.power_up = e1000_power_up_phy_copper; ++ phy->ops.power_down = e1000_power_down_phy_copper_82541; ++ ++ ret_val = e1000_get_phy_id(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Verify phy id */ ++ if (phy->id != IGP01E1000_I_PHY_ID) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_nvm_params_82541 - Init NVM func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ s32 ret_val = E1000_SUCCESS; ++ u32 eecd = E1000_READ_REG(hw, E1000_EECD); ++ u16 size; ++ ++ DEBUGFUNC("e1000_init_nvm_params_82541"); ++ ++ switch (nvm->override) { ++ case e1000_nvm_override_spi_large: ++ nvm->type = e1000_nvm_eeprom_spi; ++ eecd |= E1000_EECD_ADDR_BITS; ++ break; ++ case e1000_nvm_override_spi_small: ++ nvm->type = e1000_nvm_eeprom_spi; ++ eecd &= ~E1000_EECD_ADDR_BITS; ++ break; ++ case e1000_nvm_override_microwire_large: ++ nvm->type = e1000_nvm_eeprom_microwire; ++ eecd |= E1000_EECD_SIZE; ++ break; ++ case e1000_nvm_override_microwire_small: ++ nvm->type = e1000_nvm_eeprom_microwire; ++ eecd &= ~E1000_EECD_SIZE; ++ break; ++ default: ++ nvm->type = eecd & E1000_EECD_TYPE ++ ? e1000_nvm_eeprom_spi ++ : e1000_nvm_eeprom_microwire; ++ break; ++ } ++ ++ if (nvm->type == e1000_nvm_eeprom_spi) { ++ nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ++ ? 16 : 8; ++ nvm->delay_usec = 1; ++ nvm->opcode_bits = 8; ++ nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) ++ ? 32 : 8; ++ ++ /* Function Pointers */ ++ nvm->ops.acquire = e1000_acquire_nvm_generic; ++ nvm->ops.read = e1000_read_nvm_spi; ++ nvm->ops.release = e1000_release_nvm_generic; ++ nvm->ops.update = e1000_update_nvm_checksum_generic; ++ nvm->ops.valid_led_default = e1000_valid_led_default_generic; ++ nvm->ops.validate = e1000_validate_nvm_checksum_generic; ++ nvm->ops.write = e1000_write_nvm_spi; ++ ++ /* ++ * nvm->word_size must be discovered after the pointers ++ * are set so we can verify the size from the nvm image ++ * itself. Temporarily set it to a dummy value so the ++ * read will work. ++ */ ++ nvm->word_size = 64; ++ ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size); ++ if (ret_val) ++ goto out; ++ size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; ++ /* ++ * if size != 0, it can be added to a constant and become ++ * the left-shift value to set the word_size. Otherwise, ++ * word_size stays at 64. ++ */ ++ if (size) { ++ size += NVM_WORD_SIZE_BASE_SHIFT_82541; ++ nvm->word_size = 1 << size; ++ } ++ } else { ++ nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ++ ? 8 : 6; ++ nvm->delay_usec = 50; ++ nvm->opcode_bits = 3; ++ nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) ++ ? 256 : 64; ++ ++ /* Function Pointers */ ++ nvm->ops.acquire = e1000_acquire_nvm_generic; ++ nvm->ops.read = e1000_read_nvm_microwire; ++ nvm->ops.release = e1000_release_nvm_generic; ++ nvm->ops.update = e1000_update_nvm_checksum_generic; ++ nvm->ops.valid_led_default = e1000_valid_led_default_generic; ++ nvm->ops.validate = e1000_validate_nvm_checksum_generic; ++ nvm->ops.write = e1000_write_nvm_microwire; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_mac_params_82541 - Init MAC func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_mac_params_82541(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ ++ DEBUGFUNC("e1000_init_mac_params_82541"); ++ ++ /* Set media type */ ++ hw->phy.media_type = e1000_media_type_copper; ++ /* Set mta register count */ ++ mac->mta_reg_count = 128; ++ /* Set rar entry count */ ++ mac->rar_entry_count = E1000_RAR_ENTRIES; ++ /* Set if part includes ASF firmware */ ++ mac->asf_firmware_present = true; ++ ++ /* Function Pointers */ ++ ++ /* bus type/speed/width */ ++ mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; ++ /* function id */ ++ mac->ops.set_lan_id = e1000_set_lan_id_single_port; ++ /* reset */ ++ mac->ops.reset_hw = e1000_reset_hw_82541; ++ /* hw initialization */ ++ mac->ops.init_hw = e1000_init_hw_82541; ++ /* link setup */ ++ mac->ops.setup_link = e1000_setup_link_generic; ++ /* physical interface link setup */ ++ mac->ops.setup_physical_interface = e1000_setup_copper_link_82541; ++ /* check for link */ ++ mac->ops.check_for_link = e1000_check_for_link_82541; ++ /* link info */ ++ mac->ops.get_link_up_info = e1000_get_link_up_info_82541; ++ /* multicast address update */ ++ mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; ++ /* writing VFTA */ ++ mac->ops.write_vfta = e1000_write_vfta_generic; ++ /* clearing VFTA */ ++ mac->ops.clear_vfta = e1000_clear_vfta_generic; ++ /* setting MTA */ ++ mac->ops.mta_set = e1000_mta_set_generic; ++ /* ID LED init */ ++ mac->ops.id_led_init = e1000_id_led_init_generic; ++ /* setup LED */ ++ mac->ops.setup_led = e1000_setup_led_82541; ++ /* cleanup LED */ ++ mac->ops.cleanup_led = e1000_cleanup_led_82541; ++ /* turn on/off LED */ ++ mac->ops.led_on = e1000_led_on_generic; ++ mac->ops.led_off = e1000_led_off_generic; ++ /* clear hardware counters */ ++ mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_init_function_pointers_82541 - Init func ptrs. ++ * @hw: pointer to the HW structure ++ * ++ * Called to initialize all function pointers and parameters. ++ **/ ++void e1000_init_function_pointers_82541(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_init_function_pointers_82541"); ++ ++ hw->mac.ops.init_params = e1000_init_mac_params_82541; ++ hw->nvm.ops.init_params = e1000_init_nvm_params_82541; ++ hw->phy.ops.init_params = e1000_init_phy_params_82541; ++} ++ ++/** ++ * e1000_reset_hw_82541 - Reset hardware ++ * @hw: pointer to the HW structure ++ * ++ * This resets the hardware into a known state. ++ **/ ++static s32 e1000_reset_hw_82541(struct e1000_hw *hw) ++{ ++ u32 ledctl, ctrl, icr, manc; ++ ++ DEBUGFUNC("e1000_reset_hw_82541"); ++ ++ DEBUGOUT("Masking off all interrupts\n"); ++ E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); ++ ++ E1000_WRITE_REG(hw, E1000_RCTL, 0); ++ E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); ++ E1000_WRITE_FLUSH(hw); ++ ++ /* ++ * Delay to allow any outstanding PCI transactions to complete ++ * before resetting the device. ++ */ ++ msec_delay(10); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ /* Must reset the Phy before resetting the MAC */ ++ if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { ++ E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); ++ msec_delay(5); ++ } ++ ++ DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); ++ switch (hw->mac.type) { ++ case e1000_82541: ++ case e1000_82541_rev_2: ++ /* ++ * These controllers can't ack the 64-bit write when ++ * issuing the reset, so we use IO-mapping as a ++ * workaround to issue the reset. ++ */ ++ E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); ++ break; ++ default: ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); ++ break; ++ } ++ ++ /* Wait for NVM reload */ ++ msec_delay(20); ++ ++ /* Disable HW ARPs on ASF enabled adapters */ ++ manc = E1000_READ_REG(hw, E1000_MANC); ++ manc &= ~E1000_MANC_ARP_EN; ++ E1000_WRITE_REG(hw, E1000_MANC, manc); ++ ++ if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { ++ e1000_phy_init_script_82541(hw); ++ ++ /* Configure activity LED after Phy reset */ ++ ledctl = E1000_READ_REG(hw, E1000_LEDCTL); ++ ledctl &= IGP_ACTIVITY_LED_MASK; ++ ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); ++ E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); ++ } ++ ++ /* Once again, mask the interrupts */ ++ DEBUGOUT("Masking off all interrupts\n"); ++ E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); ++ ++ /* Clear any pending interrupt events. */ ++ icr = E1000_READ_REG(hw, E1000_ICR); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_init_hw_82541 - Initialize hardware ++ * @hw: pointer to the HW structure ++ * ++ * This inits the hardware readying it for operation. ++ **/ ++static s32 e1000_init_hw_82541(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; ++ u32 i, txdctl; ++ s32 ret_val; ++ ++ DEBUGFUNC("e1000_init_hw_82541"); ++ ++ /* Initialize identification LED */ ++ ret_val = mac->ops.id_led_init(hw); ++ if (ret_val) { ++ DEBUGOUT("Error initializing identification LED\n"); ++ /* This is not fatal and we should not stop init due to this */ ++ } ++ ++ /* Storing the Speed Power Down value for later use */ ++ ret_val = hw->phy.ops.read_reg(hw, ++ IGP01E1000_GMII_FIFO, ++ &dev_spec->spd_default); ++ if (ret_val) ++ goto out; ++ ++ /* Disabling VLAN filtering */ ++ DEBUGOUT("Initializing the IEEE VLAN\n"); ++ mac->ops.clear_vfta(hw); ++ ++ /* Setup the receive address. */ ++ e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); ++ ++ /* Zero out the Multicast HASH table */ ++ DEBUGOUT("Zeroing the MTA\n"); ++ for (i = 0; i < mac->mta_reg_count; i++) { ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); ++ /* ++ * Avoid back to back register writes by adding the register ++ * read (flush). This is to protect against some strange ++ * bridge configurations that may issue Memory Write Block ++ * (MWB) to our register space. ++ */ ++ E1000_WRITE_FLUSH(hw); ++ } ++ ++ /* Setup link and flow control */ ++ ret_val = mac->ops.setup_link(hw); ++ ++ txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); ++ txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB; ++ E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); ++ ++ /* ++ * Clear all of the statistics registers (clear on read). It is ++ * important that we do this after we have tried to establish link ++ * because the symbol error count will increment wildly if there ++ * is no link. ++ */ ++ e1000_clear_hw_cntrs_82541(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_link_up_info_82541 - Report speed and duplex ++ * @hw: pointer to the HW structure ++ * @speed: pointer to speed buffer ++ * @duplex: pointer to duplex buffer ++ * ++ * Retrieve the current speed and duplex configuration. ++ **/ ++static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ ++ DEBUGFUNC("e1000_get_link_up_info_82541"); ++ ++ ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); ++ if (ret_val) ++ goto out; ++ ++ if (!phy->speed_downgraded) ++ goto out; ++ ++ /* ++ * IGP01 PHY may advertise full duplex operation after speed ++ * downgrade even if it is operating at half duplex. ++ * Here we set the duplex settings to match the duplex in the ++ * link partner's capabilities. ++ */ ++ ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data); ++ if (ret_val) ++ goto out; ++ ++ if (!(data & NWAY_ER_LP_NWAY_CAPS)) { ++ *duplex = HALF_DUPLEX; ++ } else { ++ ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data); ++ if (ret_val) ++ goto out; ++ ++ if (*speed == SPEED_100) { ++ if (!(data & NWAY_LPAR_100TX_FD_CAPS)) ++ *duplex = HALF_DUPLEX; ++ } else if (*speed == SPEED_10) { ++ if (!(data & NWAY_LPAR_10T_FD_CAPS)) ++ *duplex = HALF_DUPLEX; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_hw_reset_82541 - PHY hardware reset ++ * @hw: pointer to the HW structure ++ * ++ * Verify the reset block is not blocking us from resetting. Acquire ++ * semaphore (if necessary) and read/set/write the device control reset ++ * bit in the PHY. Wait the appropriate delay time for the device to ++ * reset and release the semaphore (if necessary). ++ **/ ++static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ u32 ledctl; ++ ++ DEBUGFUNC("e1000_phy_hw_reset_82541"); ++ ++ ret_val = e1000_phy_hw_reset_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ e1000_phy_init_script_82541(hw); ++ ++ if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { ++ /* Configure activity LED after PHY reset */ ++ ledctl = E1000_READ_REG(hw, E1000_LEDCTL); ++ ledctl &= IGP_ACTIVITY_LED_MASK; ++ ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); ++ E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_copper_link_82541 - Configure copper link settings ++ * @hw: pointer to the HW structure ++ * ++ * Calls the appropriate function to configure the link for auto-neg or forced ++ * speed and duplex. Then we check for link, once link is established calls ++ * to configure collision distance and flow control are called. If link is ++ * not established, we return -E1000_ERR_PHY (-2). ++ **/ ++static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; ++ s32 ret_val; ++ u32 ctrl, ledctl; ++ ++ DEBUGFUNC("e1000_setup_copper_link_82541"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl |= E1000_CTRL_SLU; ++ ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++ hw->phy.reset_disable = false; ++ ++ /* Earlier revs of the IGP phy require us to force MDI. */ ++ if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { ++ dev_spec->dsp_config = e1000_dsp_config_disabled; ++ phy->mdix = 1; ++ } else { ++ dev_spec->dsp_config = e1000_dsp_config_enabled; ++ } ++ ++ ret_val = e1000_copper_link_setup_igp(hw); ++ if (ret_val) ++ goto out; ++ ++ if (hw->mac.autoneg) { ++ if (dev_spec->ffe_config == e1000_ffe_config_active) ++ dev_spec->ffe_config = e1000_ffe_config_enabled; ++ } ++ ++ /* Configure activity LED after Phy reset */ ++ ledctl = E1000_READ_REG(hw, E1000_LEDCTL); ++ ledctl &= IGP_ACTIVITY_LED_MASK; ++ ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); ++ E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); ++ ++ ret_val = e1000_setup_copper_link_generic(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_for_link_82541 - Check/Store link connection ++ * @hw: pointer to the HW structure ++ * ++ * This checks the link condition of the adapter and stores the ++ * results in the hw->mac structure. ++ **/ ++static s32 e1000_check_for_link_82541(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val; ++ bool link; ++ ++ DEBUGFUNC("e1000_check_for_link_82541"); ++ ++ /* ++ * We only want to go out to the PHY registers to see if Auto-Neg ++ * has completed and/or if our link status has changed. The ++ * get_link_status flag is set upon receiving a Link Status ++ * Change or Rx Sequence Error interrupt. ++ */ ++ if (!mac->get_link_status) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ /* ++ * First we want to see if the MII Status Register reports ++ * link. If so, then we want to get the current speed/duplex ++ * of the PHY. ++ */ ++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ ret_val = e1000_config_dsp_after_link_change_82541(hw, false); ++ goto out; /* No link detected */ ++ } ++ ++ mac->get_link_status = false; ++ ++ /* ++ * Check if there was DownShift, must be checked ++ * immediately after link-up ++ */ ++ e1000_check_downshift_generic(hw); ++ ++ /* ++ * If we are forcing speed/duplex, then we simply return since ++ * we have already determined whether we have link or not. ++ */ ++ if (!mac->autoneg) { ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ret_val = e1000_config_dsp_after_link_change_82541(hw, true); ++ ++ /* ++ * Auto-Neg is enabled. Auto Speed Detection takes care ++ * of MAC speed/duplex configuration. So we only need to ++ * configure Collision Distance in the MAC. ++ */ ++ e1000_config_collision_dist_generic(hw); ++ ++ /* ++ * Configure Flow Control now that Auto-Neg has completed. ++ * First, we need to restore the desired flow control ++ * settings because we may have had to re-autoneg with a ++ * different link partner. ++ */ ++ ret_val = e1000_config_fc_after_link_up_generic(hw); ++ if (ret_val) { ++ DEBUGOUT("Error configuring flow control\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_config_dsp_after_link_change_82541 - Config DSP after link ++ * @hw: pointer to the HW structure ++ * @link_up: boolean flag for link up status ++ * ++ * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS ++ * at any other case. ++ * ++ * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a ++ * gigabit link is achieved to improve link quality. ++ **/ ++static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, ++ bool link_up) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; ++ s32 ret_val; ++ u32 idle_errs = 0; ++ u16 phy_data, phy_saved_data, speed, duplex, i; ++ u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; ++ u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = ++ {IGP01E1000_PHY_AGC_PARAM_A, ++ IGP01E1000_PHY_AGC_PARAM_B, ++ IGP01E1000_PHY_AGC_PARAM_C, ++ IGP01E1000_PHY_AGC_PARAM_D}; ++ ++ DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); ++ ++ if (link_up) { ++ ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex); ++ if (ret_val) { ++ DEBUGOUT("Error getting link speed and duplex\n"); ++ goto out; ++ } ++ ++ if (speed != SPEED_1000) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ ret_val = phy->ops.get_cable_length(hw); ++ if (ret_val) ++ goto out; ++ ++ if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && ++ phy->min_cable_length >= 50) { ++ ++ for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { ++ ret_val = phy->ops.read_reg(hw, ++ dsp_reg_array[i], ++ &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; ++ ++ ret_val = phy->ops.write_reg(hw, ++ dsp_reg_array[i], ++ phy_data); ++ if (ret_val) ++ goto out; ++ } ++ dev_spec->dsp_config = e1000_dsp_config_activated; ++ } ++ ++ if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || ++ (phy->min_cable_length >= 50)) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ /* clear previous idle error counts */ ++ ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ for (i = 0; i < ffe_idle_err_timeout; i++) { ++ usec_delay(1000); ++ ret_val = phy->ops.read_reg(hw, ++ PHY_1000T_STATUS, ++ &phy_data); ++ if (ret_val) ++ goto out; ++ ++ idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); ++ if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { ++ dev_spec->ffe_config = e1000_ffe_config_active; ++ ++ ret_val = phy->ops.write_reg(hw, ++ IGP01E1000_PHY_DSP_FFE, ++ IGP01E1000_PHY_DSP_FFE_CM_CP); ++ if (ret_val) ++ goto out; ++ break; ++ } ++ ++ if (idle_errs) ++ ffe_idle_err_timeout = ++ FFE_IDLE_ERR_COUNT_TIMEOUT_100; ++ } ++ } else { ++ if (dev_spec->dsp_config == e1000_dsp_config_activated) { ++ /* ++ * Save off the current value of register 0x2F5B ++ * to be restored at the end of the routines. ++ */ ++ ret_val = phy->ops.read_reg(hw, ++ 0x2F5B, ++ &phy_saved_data); ++ if (ret_val) ++ goto out; ++ ++ /* Disable the PHY transmitter */ ++ ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); ++ if (ret_val) ++ goto out; ++ ++ msec_delay_irq(20); ++ ++ ret_val = phy->ops.write_reg(hw, ++ 0x0000, ++ IGP01E1000_IEEE_FORCE_GIG); ++ if (ret_val) ++ goto out; ++ for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { ++ ret_val = phy->ops.read_reg(hw, ++ dsp_reg_array[i], ++ &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; ++ phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; ++ ++ ret_val = phy->ops.write_reg(hw, ++ dsp_reg_array[i], ++ phy_data); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = phy->ops.write_reg(hw, ++ 0x0000, ++ IGP01E1000_IEEE_RESTART_AUTONEG); ++ if (ret_val) ++ goto out; ++ ++ msec_delay_irq(20); ++ ++ /* Now enable the transmitter */ ++ ret_val = phy->ops.write_reg(hw, ++ 0x2F5B, ++ phy_saved_data); ++ if (ret_val) ++ goto out; ++ ++ dev_spec->dsp_config = e1000_dsp_config_enabled; ++ } ++ ++ if (dev_spec->ffe_config != e1000_ffe_config_active) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ /* ++ * Save off the current value of register 0x2F5B ++ * to be restored at the end of the routines. ++ */ ++ ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data); ++ if (ret_val) ++ goto out; ++ ++ /* Disable the PHY transmitter */ ++ ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); ++ if (ret_val) ++ goto out; ++ ++ msec_delay_irq(20); ++ ++ ret_val = phy->ops.write_reg(hw, ++ 0x0000, ++ IGP01E1000_IEEE_FORCE_GIG); ++ if (ret_val) ++ goto out; ++ ++ ret_val = phy->ops.write_reg(hw, ++ IGP01E1000_PHY_DSP_FFE, ++ IGP01E1000_PHY_DSP_FFE_DEFAULT); ++ if (ret_val) ++ goto out; ++ ++ ret_val = phy->ops.write_reg(hw, ++ 0x0000, ++ IGP01E1000_IEEE_RESTART_AUTONEG); ++ if (ret_val) ++ goto out; ++ ++ msec_delay_irq(20); ++ ++ /* Now enable the transmitter */ ++ ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data); ++ ++ if (ret_val) ++ goto out; ++ ++ dev_spec->ffe_config = e1000_ffe_config_enabled; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY ++ * @hw: pointer to the HW structure ++ * ++ * The automatic gain control (agc) normalizes the amplitude of the ++ * received signal, adjusting for the attenuation produced by the ++ * cable. By reading the AGC registers, which represent the ++ * combination of coarse and fine gain value, the value can be put ++ * into a lookup table to obtain the approximate cable length ++ * for each channel. ++ **/ ++static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 i, data; ++ u16 cur_agc_value, agc_value = 0; ++ u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; ++ u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = ++ {IGP01E1000_PHY_AGC_A, ++ IGP01E1000_PHY_AGC_B, ++ IGP01E1000_PHY_AGC_C, ++ IGP01E1000_PHY_AGC_D}; ++ ++ DEBUGFUNC("e1000_get_cable_length_igp_82541"); ++ ++ /* Read the AGC registers for all channels */ ++ for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { ++ ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data); ++ if (ret_val) ++ goto out; ++ ++ cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; ++ ++ /* Bounds checking */ ++ if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || ++ (cur_agc_value == 0)) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++ agc_value += cur_agc_value; ++ ++ if (min_agc_value > cur_agc_value) ++ min_agc_value = cur_agc_value; ++ } ++ ++ /* Remove the minimal AGC result for length < 50m */ ++ if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { ++ agc_value -= min_agc_value; ++ /* Average the three remaining channels for the length. */ ++ agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); ++ } else { ++ /* Average the channels for the length. */ ++ agc_value /= IGP01E1000_PHY_CHANNEL_NUM; ++ } ++ ++ phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > ++ IGP01E1000_AGC_RANGE) ++ ? (e1000_igp_cable_length_table[agc_value] - ++ IGP01E1000_AGC_RANGE) ++ : 0; ++ phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + ++ IGP01E1000_AGC_RANGE; ++ ++ phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 ++ * @hw: pointer to the HW structure ++ * @active: boolean used to enable/disable lplu ++ * ++ * Success returns 0, Failure returns 1 ++ * ++ * The low power link up (lplu) state is set to the power management level D3 ++ * and SmartSpeed is disabled when active is true, else clear lplu for D3 ++ * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU ++ * is used during Dx states where the power conservation is most important. ++ * During driver activity, SmartSpeed should be enabled so performance is ++ * maintained. ++ **/ ++static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ ++ DEBUGFUNC("e1000_set_d3_lplu_state_82541"); ++ ++ switch (hw->mac.type) { ++ case e1000_82541_rev_2: ++ case e1000_82547_rev_2: ++ break; ++ default: ++ ret_val = e1000_set_d3_lplu_state_generic(hw, active); ++ goto out; ++ break; ++ } ++ ++ ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data); ++ if (ret_val) ++ goto out; ++ ++ if (!active) { ++ data &= ~IGP01E1000_GMII_FLEX_SPD; ++ ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * LPLU and SmartSpeed are mutually exclusive. LPLU is used ++ * during Dx states where the power conservation is most ++ * important. During driver activity we should enable ++ * SmartSpeed, so performance is maintained. ++ */ ++ if (phy->smart_speed == e1000_smart_speed_on) { ++ ret_val = phy->ops.read_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data |= IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = phy->ops.write_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } else if (phy->smart_speed == e1000_smart_speed_off) { ++ ret_val = phy->ops.read_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = phy->ops.write_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } ++ } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || ++ (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || ++ (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { ++ data |= IGP01E1000_GMII_FLEX_SPD; ++ ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); ++ if (ret_val) ++ goto out; ++ ++ /* When LPLU is enabled, we should disable SmartSpeed */ ++ ret_val = phy->ops.read_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = phy->ops.write_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_led_82541 - Configures SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * This prepares the SW controllable LED for use and saves the current state ++ * of the LED so it can be later restored. ++ **/ ++static s32 e1000_setup_led_82541(struct e1000_hw *hw) ++{ ++ struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; ++ s32 ret_val; ++ ++ DEBUGFUNC("e1000_setup_led_82541"); ++ ++ ret_val = hw->phy.ops.read_reg(hw, ++ IGP01E1000_GMII_FIFO, ++ &dev_spec->spd_default); ++ if (ret_val) ++ goto out; ++ ++ ret_val = hw->phy.ops.write_reg(hw, ++ IGP01E1000_GMII_FIFO, ++ (u16)(dev_spec->spd_default & ++ ~IGP01E1000_GMII_SPD)); ++ if (ret_val) ++ goto out; ++ ++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_cleanup_led_82541 - Set LED config to default operation ++ * @hw: pointer to the HW structure ++ * ++ * Remove the current LED configuration and set the LED configuration ++ * to the default value, saved from the EEPROM. ++ **/ ++static s32 e1000_cleanup_led_82541(struct e1000_hw *hw) ++{ ++ struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; ++ s32 ret_val; ++ ++ DEBUGFUNC("e1000_cleanup_led_82541"); ++ ++ ret_val = hw->phy.ops.write_reg(hw, ++ IGP01E1000_GMII_FIFO, ++ dev_spec->spd_default); ++ if (ret_val) ++ goto out; ++ ++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_init_script_82541 - Initialize GbE PHY ++ * @hw: pointer to the HW structure ++ * ++ * Initializes the IGP PHY. ++ **/ ++static s32 e1000_phy_init_script_82541(struct e1000_hw *hw) ++{ ++ struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; ++ u32 ret_val; ++ u16 phy_saved_data; ++ ++ DEBUGFUNC("e1000_phy_init_script_82541"); ++ ++ if (!dev_spec->phy_init_script) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ /* Delay after phy reset to enable NVM configuration to load */ ++ msec_delay(20); ++ ++ /* ++ * Save off the current value of register 0x2F5B to be restored at ++ * the end of this routine. ++ */ ++ ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data); ++ ++ /* Disabled the PHY transmitter */ ++ hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003); ++ ++ msec_delay(20); ++ ++ hw->phy.ops.write_reg(hw, 0x0000, 0x0140); ++ ++ msec_delay(5); ++ ++ switch (hw->mac.type) { ++ case e1000_82541: ++ case e1000_82547: ++ hw->phy.ops.write_reg(hw, 0x1F95, 0x0001); ++ ++ hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21); ++ ++ hw->phy.ops.write_reg(hw, 0x1F79, 0x0018); ++ ++ hw->phy.ops.write_reg(hw, 0x1F30, 0x1600); ++ ++ hw->phy.ops.write_reg(hw, 0x1F31, 0x0014); ++ ++ hw->phy.ops.write_reg(hw, 0x1F32, 0x161C); ++ ++ hw->phy.ops.write_reg(hw, 0x1F94, 0x0003); ++ ++ hw->phy.ops.write_reg(hw, 0x1F96, 0x003F); ++ ++ hw->phy.ops.write_reg(hw, 0x2010, 0x0008); ++ break; ++ case e1000_82541_rev_2: ++ case e1000_82547_rev_2: ++ hw->phy.ops.write_reg(hw, 0x1F73, 0x0099); ++ break; ++ default: ++ break; ++ } ++ ++ hw->phy.ops.write_reg(hw, 0x0000, 0x3300); ++ ++ msec_delay(20); ++ ++ /* Now enable the transmitter */ ++ hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data); ++ ++ if (hw->mac.type == e1000_82547) { ++ u16 fused, fine, coarse; ++ ++ /* Move to analog registers page */ ++ hw->phy.ops.read_reg(hw, ++ IGP01E1000_ANALOG_SPARE_FUSE_STATUS, ++ &fused); ++ ++ if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { ++ hw->phy.ops.read_reg(hw, ++ IGP01E1000_ANALOG_FUSE_STATUS, ++ &fused); ++ ++ fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; ++ coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; ++ ++ if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { ++ coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; ++ fine -= IGP01E1000_ANALOG_FUSE_FINE_1; ++ } else if (coarse == ++ IGP01E1000_ANALOG_FUSE_COARSE_THRESH) ++ fine -= IGP01E1000_ANALOG_FUSE_FINE_10; ++ ++ fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | ++ (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | ++ (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); ++ ++ hw->phy.ops.write_reg(hw, ++ IGP01E1000_ANALOG_FUSE_CONTROL, ++ fused); ++ hw->phy.ops.write_reg(hw, ++ IGP01E1000_ANALOG_FUSE_BYPASS, ++ IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_script_state_82541 - Enable/Disable PHY init script ++ * @hw: pointer to the HW structure ++ * @state: boolean value used to enable/disable PHY init script ++ * ++ * Allows the driver to enable/disable the PHY init script, if the PHY is an ++ * IGP PHY. ++ **/ ++void e1000_init_script_state_82541(struct e1000_hw *hw, bool state) ++{ ++ struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; ++ ++ DEBUGFUNC("e1000_init_script_state_82541"); ++ ++ if (hw->phy.type != e1000_phy_igp) { ++ DEBUGOUT("Initialization script not necessary.\n"); ++ goto out; ++ } ++ ++ dev_spec->phy_init_script = state; ++ ++out: ++ return; ++} ++ ++/** ++ * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down ++ * @hw: pointer to the HW structure ++ * ++ * In the case of a PHY power down to save power, or to turn off link during a ++ * driver unload, or wake on lan is not enabled, remove the link. ++ **/ ++static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw) ++{ ++ /* If the management interface is not enabled, then power down */ ++ if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) ++ e1000_power_down_phy_copper(hw); ++ ++ return; ++} ++ ++/** ++ * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters ++ * @hw: pointer to the HW structure ++ * ++ * Clears the hardware counters by reading the counter registers. ++ **/ ++static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_clear_hw_cntrs_82541"); ++ ++ e1000_clear_hw_cntrs_base_generic(hw); ++ ++ E1000_READ_REG(hw, E1000_PRC64); ++ E1000_READ_REG(hw, E1000_PRC127); ++ E1000_READ_REG(hw, E1000_PRC255); ++ E1000_READ_REG(hw, E1000_PRC511); ++ E1000_READ_REG(hw, E1000_PRC1023); ++ E1000_READ_REG(hw, E1000_PRC1522); ++ E1000_READ_REG(hw, E1000_PTC64); ++ E1000_READ_REG(hw, E1000_PTC127); ++ E1000_READ_REG(hw, E1000_PTC255); ++ E1000_READ_REG(hw, E1000_PTC511); ++ E1000_READ_REG(hw, E1000_PTC1023); ++ E1000_READ_REG(hw, E1000_PTC1522); ++ ++ E1000_READ_REG(hw, E1000_ALGNERRC); ++ E1000_READ_REG(hw, E1000_RXERRC); ++ E1000_READ_REG(hw, E1000_TNCRS); ++ E1000_READ_REG(hw, E1000_CEXTERR); ++ E1000_READ_REG(hw, E1000_TSCTC); ++ E1000_READ_REG(hw, E1000_TSCTFC); ++ ++ E1000_READ_REG(hw, E1000_MGTPRC); ++ E1000_READ_REG(hw, E1000_MGTPDC); ++ E1000_READ_REG(hw, E1000_MGTPTC); ++} +diff -r b58885ce604a drivers/net/e1000/e1000_82541.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_82541.h Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,86 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_82541_H_ ++#define _E1000_82541_H_ ++ ++#define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1) ++ ++#define IGP01E1000_PHY_CHANNEL_NUM 4 ++ ++#define IGP01E1000_PHY_AGC_A 0x1172 ++#define IGP01E1000_PHY_AGC_B 0x1272 ++#define IGP01E1000_PHY_AGC_C 0x1472 ++#define IGP01E1000_PHY_AGC_D 0x1872 ++ ++#define IGP01E1000_PHY_AGC_PARAM_A 0x1171 ++#define IGP01E1000_PHY_AGC_PARAM_B 0x1271 ++#define IGP01E1000_PHY_AGC_PARAM_C 0x1471 ++#define IGP01E1000_PHY_AGC_PARAM_D 0x1871 ++ ++#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 ++#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 ++ ++#define IGP01E1000_PHY_DSP_RESET 0x1F33 ++ ++#define IGP01E1000_PHY_DSP_FFE 0x1F35 ++#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 ++#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A ++ ++#define IGP01E1000_IEEE_FORCE_GIG 0x0140 ++#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 ++ ++#define IGP01E1000_AGC_LENGTH_SHIFT 7 ++#define IGP01E1000_AGC_RANGE 10 ++ ++#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 ++#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 ++ ++#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 ++#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 ++#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC ++#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE ++ ++#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 ++#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 ++#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 ++#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 ++#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 ++#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 ++#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 ++#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 ++#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 ++ ++#define IGP01E1000_MSE_CHANNEL_D 0x000F ++#define IGP01E1000_MSE_CHANNEL_C 0x00F0 ++#define IGP01E1000_MSE_CHANNEL_B 0x0F00 ++#define IGP01E1000_MSE_CHANNEL_A 0xF000 ++ ++ ++void e1000_init_script_state_82541(struct e1000_hw *hw, bool state); ++#endif +diff -r b58885ce604a drivers/net/e1000/e1000_82542.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_82542.c Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,550 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * 82542 Gigabit Ethernet Controller ++ */ ++ ++#include "e1000_api.h" ++ ++static s32 e1000_init_phy_params_82542(struct e1000_hw *hw); ++static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw); ++static s32 e1000_init_mac_params_82542(struct e1000_hw *hw); ++static s32 e1000_get_bus_info_82542(struct e1000_hw *hw); ++static s32 e1000_reset_hw_82542(struct e1000_hw *hw); ++static s32 e1000_init_hw_82542(struct e1000_hw *hw); ++static s32 e1000_setup_link_82542(struct e1000_hw *hw); ++static s32 e1000_led_on_82542(struct e1000_hw *hw); ++static s32 e1000_led_off_82542(struct e1000_hw *hw); ++static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index); ++static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw); ++ ++/** ++ * e1000_init_phy_params_82542 - Init PHY func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_phy_params_82542(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_init_phy_params_82542"); ++ ++ phy->type = e1000_phy_none; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_init_nvm_params_82542 - Init NVM func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ ++ DEBUGFUNC("e1000_init_nvm_params_82542"); ++ ++ nvm->address_bits = 6; ++ nvm->delay_usec = 50; ++ nvm->opcode_bits = 3; ++ nvm->type = e1000_nvm_eeprom_microwire; ++ nvm->word_size = 64; ++ ++ /* Function Pointers */ ++ nvm->ops.read = e1000_read_nvm_microwire; ++ nvm->ops.release = e1000_stop_nvm; ++ nvm->ops.write = e1000_write_nvm_microwire; ++ nvm->ops.update = e1000_update_nvm_checksum_generic; ++ nvm->ops.validate = e1000_validate_nvm_checksum_generic; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_init_mac_params_82542 - Init MAC func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_mac_params_82542(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ ++ DEBUGFUNC("e1000_init_mac_params_82542"); ++ ++ /* Set media type */ ++ hw->phy.media_type = e1000_media_type_fiber; ++ ++ /* Set mta register count */ ++ mac->mta_reg_count = 128; ++ /* Set rar entry count */ ++ mac->rar_entry_count = E1000_RAR_ENTRIES; ++ ++ /* Function pointers */ ++ ++ /* bus type/speed/width */ ++ mac->ops.get_bus_info = e1000_get_bus_info_82542; ++ /* function id */ ++ mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; ++ /* reset */ ++ mac->ops.reset_hw = e1000_reset_hw_82542; ++ /* hw initialization */ ++ mac->ops.init_hw = e1000_init_hw_82542; ++ /* link setup */ ++ mac->ops.setup_link = e1000_setup_link_82542; ++ /* phy/fiber/serdes setup */ ++ mac->ops.setup_physical_interface = e1000_setup_fiber_serdes_link_generic; ++ /* check for link */ ++ mac->ops.check_for_link = e1000_check_for_fiber_link_generic; ++ /* multicast address update */ ++ mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; ++ /* writing VFTA */ ++ mac->ops.write_vfta = e1000_write_vfta_generic; ++ /* clearing VFTA */ ++ mac->ops.clear_vfta = e1000_clear_vfta_generic; ++ /* setting MTA */ ++ mac->ops.mta_set = e1000_mta_set_generic; ++ /* set RAR */ ++ mac->ops.rar_set = e1000_rar_set_82542; ++ /* turn on/off LED */ ++ mac->ops.led_on = e1000_led_on_82542; ++ mac->ops.led_off = e1000_led_off_82542; ++ /* clear hardware counters */ ++ mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542; ++ /* link info */ ++ mac->ops.get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes_generic; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_init_function_pointers_82542 - Init func ptrs. ++ * @hw: pointer to the HW structure ++ * ++ * Called to initialize all function pointers and parameters. ++ **/ ++void e1000_init_function_pointers_82542(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_init_function_pointers_82542"); ++ ++ hw->mac.ops.init_params = e1000_init_mac_params_82542; ++ hw->nvm.ops.init_params = e1000_init_nvm_params_82542; ++ hw->phy.ops.init_params = e1000_init_phy_params_82542; ++} ++ ++/** ++ * e1000_get_bus_info_82542 - Obtain bus information for adapter ++ * @hw: pointer to the HW structure ++ * ++ * This will obtain information about the HW bus for which the ++ * adapter is attached and stores it in the hw structure. ++ **/ ++static s32 e1000_get_bus_info_82542(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_get_bus_info_82542"); ++ ++ hw->bus.type = e1000_bus_type_pci; ++ hw->bus.speed = e1000_bus_speed_unknown; ++ hw->bus.width = e1000_bus_width_unknown; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_reset_hw_82542 - Reset hardware ++ * @hw: pointer to the HW structure ++ * ++ * This resets the hardware into a known state. ++ **/ ++static s32 e1000_reset_hw_82542(struct e1000_hw *hw) ++{ ++ struct e1000_bus_info *bus = &hw->bus; ++ s32 ret_val = E1000_SUCCESS; ++ u32 ctrl, icr; ++ ++ DEBUGFUNC("e1000_reset_hw_82542"); ++ ++ if (hw->revision_id == E1000_REVISION_2) { ++ DEBUGOUT("Disabling MWI on 82542 rev 2\n"); ++ e1000_pci_clear_mwi(hw); ++ } ++ ++ DEBUGOUT("Masking off all interrupts\n"); ++ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); ++ ++ E1000_WRITE_REG(hw, E1000_RCTL, 0); ++ E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); ++ E1000_WRITE_FLUSH(hw); ++ ++ /* ++ * Delay to allow any outstanding PCI transactions to complete before ++ * resetting the device ++ */ ++ msec_delay(10); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n"); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); ++ ++ hw->nvm.ops.reload(hw); ++ msec_delay(2); ++ ++ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); ++ icr = E1000_READ_REG(hw, E1000_ICR); ++ ++ if (hw->revision_id == E1000_REVISION_2) { ++ if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) ++ e1000_pci_set_mwi(hw); ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_init_hw_82542 - Initialize hardware ++ * @hw: pointer to the HW structure ++ * ++ * This inits the hardware readying it for operation. ++ **/ ++static s32 e1000_init_hw_82542(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542; ++ s32 ret_val = E1000_SUCCESS; ++ u32 ctrl; ++ u16 i; ++ ++ DEBUGFUNC("e1000_init_hw_82542"); ++ ++ /* Disabling VLAN filtering */ ++ E1000_WRITE_REG(hw, E1000_VET, 0); ++ mac->ops.clear_vfta(hw); ++ ++ /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ ++ if (hw->revision_id == E1000_REVISION_2) { ++ DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); ++ e1000_pci_clear_mwi(hw); ++ E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); ++ E1000_WRITE_FLUSH(hw); ++ msec_delay(5); ++ } ++ ++ /* Setup the receive address. */ ++ e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); ++ ++ /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ ++ if (hw->revision_id == E1000_REVISION_2) { ++ E1000_WRITE_REG(hw, E1000_RCTL, 0); ++ E1000_WRITE_FLUSH(hw); ++ msec_delay(1); ++ if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) ++ e1000_pci_set_mwi(hw); ++ } ++ ++ /* Zero out the Multicast HASH table */ ++ DEBUGOUT("Zeroing the MTA\n"); ++ for (i = 0; i < mac->mta_reg_count; i++) ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); ++ ++ /* ++ * Set the PCI priority bit correctly in the CTRL register. This ++ * determines if the adapter gives priority to receives, or if it ++ * gives equal priority to transmits and receives. ++ */ ++ if (dev_spec->dma_fairness) { ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); ++ } ++ ++ /* Setup link and flow control */ ++ ret_val = e1000_setup_link_82542(hw); ++ ++ /* ++ * Clear all of the statistics registers (clear on read). It is ++ * important that we do this after we have tried to establish link ++ * because the symbol error count will increment wildly if there ++ * is no link. ++ */ ++ e1000_clear_hw_cntrs_82542(hw); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_link_82542 - Setup flow control and link settings ++ * @hw: pointer to the HW structure ++ * ++ * Determines which flow control settings to use, then configures flow ++ * control. Calls the appropriate media-specific link configuration ++ * function. Assuming the adapter has a valid link partner, a valid link ++ * should be established. Assumes the hardware has previously been reset ++ * and the transmitter and receiver are not enabled. ++ **/ ++static s32 e1000_setup_link_82542(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_setup_link_82542"); ++ ++ ret_val = e1000_set_default_fc_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ hw->fc.requested_mode &= ~e1000_fc_tx_pause; ++ ++ if (mac->report_tx_early == 1) ++ hw->fc.requested_mode &= ~e1000_fc_rx_pause; ++ ++ /* ++ * Save off the requested flow control mode for use later. Depending ++ * on the link partner's capabilities, we may or may not use this mode. ++ */ ++ hw->fc.current_mode = hw->fc.requested_mode; ++ ++ DEBUGOUT1("After fix-ups FlowControl is now = %x\n", ++ hw->fc.current_mode); ++ ++ /* Call the necessary subroutine to configure the link. */ ++ ret_val = mac->ops.setup_physical_interface(hw); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Initialize the flow control address, type, and PAUSE timer ++ * registers to their default values. This is done even if flow ++ * control is disabled, because it does not hurt anything to ++ * initialize these registers. ++ */ ++ DEBUGOUT("Initializing Flow Control address, type and timer regs\n"); ++ ++ E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); ++ E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); ++ E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); ++ ++ E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); ++ ++ ret_val = e1000_set_fc_watermarks_generic(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_led_on_82542 - Turn on SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * Turns the SW defined LED on. ++ **/ ++static s32 e1000_led_on_82542(struct e1000_hw *hw) ++{ ++ u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ DEBUGFUNC("e1000_led_on_82542"); ++ ++ ctrl |= E1000_CTRL_SWDPIN0; ++ ctrl |= E1000_CTRL_SWDPIO0; ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_led_off_82542 - Turn off SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * Turns the SW defined LED off. ++ **/ ++static s32 e1000_led_off_82542(struct e1000_hw *hw) ++{ ++ u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ DEBUGFUNC("e1000_led_off_82542"); ++ ++ ctrl &= ~E1000_CTRL_SWDPIN0; ++ ctrl |= E1000_CTRL_SWDPIO0; ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_rar_set_82542 - Set receive address register ++ * @hw: pointer to the HW structure ++ * @addr: pointer to the receive address ++ * @index: receive address array register ++ * ++ * Sets the receive address array register at index to the address passed ++ * in by addr. ++ **/ ++static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index) ++{ ++ u32 rar_low, rar_high; ++ ++ DEBUGFUNC("e1000_rar_set_82542"); ++ ++ /* ++ * HW expects these in little endian so we reverse the byte order ++ * from network order (big endian) to little endian ++ */ ++ rar_low = ((u32) addr[0] | ++ ((u32) addr[1] << 8) | ++ ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); ++ ++ rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); ++ ++ /* If MAC address zero, no need to set the AV bit */ ++ if (rar_low || rar_high) ++ rar_high |= E1000_RAH_AV; ++ ++ E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); ++ E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); ++} ++ ++/** ++ * e1000_translate_register_82542 - Translate the proper register offset ++ * @reg: e1000 register to be read ++ * ++ * Registers in 82542 are located in different offsets than other adapters ++ * even though they function in the same manner. This function takes in ++ * the name of the register to read and returns the correct offset for ++ * 82542 silicon. ++ **/ ++u32 e1000_translate_register_82542(u32 reg) ++{ ++ /* ++ * Some of the 82542 registers are located at different ++ * offsets than they are in newer adapters. ++ * Despite the difference in location, the registers ++ * function in the same manner. ++ */ ++ switch (reg) { ++ case E1000_RA: ++ reg = 0x00040; ++ break; ++ case E1000_RDTR: ++ reg = 0x00108; ++ break; ++ case E1000_RDBAL(0): ++ reg = 0x00110; ++ break; ++ case E1000_RDBAH(0): ++ reg = 0x00114; ++ break; ++ case E1000_RDLEN(0): ++ reg = 0x00118; ++ break; ++ case E1000_RDH(0): ++ reg = 0x00120; ++ break; ++ case E1000_RDT(0): ++ reg = 0x00128; ++ break; ++ case E1000_RDBAL(1): ++ reg = 0x00138; ++ break; ++ case E1000_RDBAH(1): ++ reg = 0x0013C; ++ break; ++ case E1000_RDLEN(1): ++ reg = 0x00140; ++ break; ++ case E1000_RDH(1): ++ reg = 0x00148; ++ break; ++ case E1000_RDT(1): ++ reg = 0x00150; ++ break; ++ case E1000_FCRTH: ++ reg = 0x00160; ++ break; ++ case E1000_FCRTL: ++ reg = 0x00168; ++ break; ++ case E1000_MTA: ++ reg = 0x00200; ++ break; ++ case E1000_TDBAL(0): ++ reg = 0x00420; ++ break; ++ case E1000_TDBAH(0): ++ reg = 0x00424; ++ break; ++ case E1000_TDLEN(0): ++ reg = 0x00428; ++ break; ++ case E1000_TDH(0): ++ reg = 0x00430; ++ break; ++ case E1000_TDT(0): ++ reg = 0x00438; ++ break; ++ case E1000_TIDV: ++ reg = 0x00440; ++ break; ++ case E1000_VFTA: ++ reg = 0x00600; ++ break; ++ case E1000_TDFH: ++ reg = 0x08010; ++ break; ++ case E1000_TDFT: ++ reg = 0x08018; ++ break; ++ default: ++ break; ++ } ++ ++ return reg; ++} ++ ++/** ++ * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters ++ * @hw: pointer to the HW structure ++ * ++ * Clears the hardware counters by reading the counter registers. ++ **/ ++static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_clear_hw_cntrs_82542"); ++ ++ e1000_clear_hw_cntrs_base_generic(hw); ++ ++ E1000_READ_REG(hw, E1000_PRC64); ++ E1000_READ_REG(hw, E1000_PRC127); ++ E1000_READ_REG(hw, E1000_PRC255); ++ E1000_READ_REG(hw, E1000_PRC511); ++ E1000_READ_REG(hw, E1000_PRC1023); ++ E1000_READ_REG(hw, E1000_PRC1522); ++ E1000_READ_REG(hw, E1000_PTC64); ++ E1000_READ_REG(hw, E1000_PTC127); ++ E1000_READ_REG(hw, E1000_PTC255); ++ E1000_READ_REG(hw, E1000_PTC511); ++ E1000_READ_REG(hw, E1000_PTC1023); ++ E1000_READ_REG(hw, E1000_PTC1522); ++} +diff -r b58885ce604a drivers/net/e1000/e1000_82543.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_82543.c Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,1596 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * 82543GC Gigabit Ethernet Controller (Fiber) ++ * 82543GC Gigabit Ethernet Controller (Copper) ++ * 82544EI Gigabit Ethernet Controller (Copper) ++ * 82544EI Gigabit Ethernet Controller (Fiber) ++ * 82544GC Gigabit Ethernet Controller (Copper) ++ * 82544GC Gigabit Ethernet Controller (LOM) ++ */ ++ ++#include "e1000_api.h" ++ ++static s32 e1000_init_phy_params_82543(struct e1000_hw *hw); ++static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); ++static s32 e1000_init_mac_params_82543(struct e1000_hw *hw); ++static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, ++ u16 *data); ++static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, ++ u16 data); ++static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); ++static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); ++static s32 e1000_reset_hw_82543(struct e1000_hw *hw); ++static s32 e1000_init_hw_82543(struct e1000_hw *hw); ++static s32 e1000_setup_link_82543(struct e1000_hw *hw); ++static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); ++static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); ++static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); ++static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); ++static s32 e1000_led_on_82543(struct e1000_hw *hw); ++static s32 e1000_led_off_82543(struct e1000_hw *hw); ++static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, ++ u32 value); ++static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value); ++static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); ++static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); ++static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw); ++static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); ++static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); ++static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); ++static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); ++static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, ++ u16 count); ++static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); ++static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state); ++ ++/** ++ * e1000_init_phy_params_82543 - Init PHY func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_phy_params_82543(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_init_phy_params_82543"); ++ ++ if (hw->phy.media_type != e1000_media_type_copper) { ++ phy->type = e1000_phy_none; ++ goto out; ++ } else { ++ phy->ops.power_up = e1000_power_up_phy_copper; ++ phy->ops.power_down = e1000_power_down_phy_copper; ++ } ++ ++ phy->addr = 1; ++ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; ++ phy->reset_delay_us = 10000; ++ phy->type = e1000_phy_m88; ++ ++ /* Function Pointers */ ++ phy->ops.check_polarity = e1000_check_polarity_m88; ++ phy->ops.commit = e1000_phy_sw_reset_generic; ++ phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543; ++ phy->ops.get_cable_length = e1000_get_cable_length_m88; ++ phy->ops.get_cfg_done = e1000_get_cfg_done_generic; ++ phy->ops.read_reg = (hw->mac.type == e1000_82543) ++ ? e1000_read_phy_reg_82543 ++ : e1000_read_phy_reg_m88; ++ phy->ops.reset = (hw->mac.type == e1000_82543) ++ ? e1000_phy_hw_reset_82543 ++ : e1000_phy_hw_reset_generic; ++ phy->ops.write_reg = (hw->mac.type == e1000_82543) ++ ? e1000_write_phy_reg_82543 ++ : e1000_write_phy_reg_m88; ++ phy->ops.get_info = e1000_get_phy_info_m88; ++ ++ /* ++ * The external PHY of the 82543 can be in a funky state. ++ * Resetting helps us read the PHY registers for acquiring ++ * the PHY ID. ++ */ ++ if (!e1000_init_phy_disabled_82543(hw)) { ++ ret_val = phy->ops.reset(hw); ++ if (ret_val) { ++ DEBUGOUT("Resetting PHY during init failed.\n"); ++ goto out; ++ } ++ msec_delay(20); ++ } ++ ++ ret_val = e1000_get_phy_id(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Verify phy id */ ++ switch (hw->mac.type) { ++ case e1000_82543: ++ if (phy->id != M88E1000_E_PHY_ID) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ break; ++ case e1000_82544: ++ if (phy->id != M88E1000_I_PHY_ID) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ break; ++ default: ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ break; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_nvm_params_82543 - Init NVM func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ ++ DEBUGFUNC("e1000_init_nvm_params_82543"); ++ ++ nvm->type = e1000_nvm_eeprom_microwire; ++ nvm->word_size = 64; ++ nvm->delay_usec = 50; ++ nvm->address_bits = 6; ++ nvm->opcode_bits = 3; ++ ++ /* Function Pointers */ ++ nvm->ops.read = e1000_read_nvm_microwire; ++ nvm->ops.update = e1000_update_nvm_checksum_generic; ++ nvm->ops.valid_led_default = e1000_valid_led_default_generic; ++ nvm->ops.validate = e1000_validate_nvm_checksum_generic; ++ nvm->ops.write = e1000_write_nvm_microwire; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_init_mac_params_82543 - Init MAC func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_mac_params_82543(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ ++ DEBUGFUNC("e1000_init_mac_params_82543"); ++ ++ /* Set media type */ ++ switch (hw->device_id) { ++ case E1000_DEV_ID_82543GC_FIBER: ++ case E1000_DEV_ID_82544EI_FIBER: ++ hw->phy.media_type = e1000_media_type_fiber; ++ break; ++ default: ++ hw->phy.media_type = e1000_media_type_copper; ++ break; ++ } ++ ++ /* Set mta register count */ ++ mac->mta_reg_count = 128; ++ /* Set rar entry count */ ++ mac->rar_entry_count = E1000_RAR_ENTRIES; ++ ++ /* Function pointers */ ++ ++ /* bus type/speed/width */ ++ mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; ++ /* function id */ ++ mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; ++ /* reset */ ++ mac->ops.reset_hw = e1000_reset_hw_82543; ++ /* hw initialization */ ++ mac->ops.init_hw = e1000_init_hw_82543; ++ /* link setup */ ++ mac->ops.setup_link = e1000_setup_link_82543; ++ /* physical interface setup */ ++ mac->ops.setup_physical_interface = ++ (hw->phy.media_type == e1000_media_type_copper) ++ ? e1000_setup_copper_link_82543 ++ : e1000_setup_fiber_link_82543; ++ /* check for link */ ++ mac->ops.check_for_link = ++ (hw->phy.media_type == e1000_media_type_copper) ++ ? e1000_check_for_copper_link_82543 ++ : e1000_check_for_fiber_link_82543; ++ /* link info */ ++ mac->ops.get_link_up_info = ++ (hw->phy.media_type == e1000_media_type_copper) ++ ? e1000_get_speed_and_duplex_copper_generic ++ : e1000_get_speed_and_duplex_fiber_serdes_generic; ++ /* multicast address update */ ++ mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; ++ /* writing VFTA */ ++ mac->ops.write_vfta = e1000_write_vfta_82543; ++ /* clearing VFTA */ ++ mac->ops.clear_vfta = e1000_clear_vfta_generic; ++ /* setting MTA */ ++ mac->ops.mta_set = e1000_mta_set_82543; ++ /* turn on/off LED */ ++ mac->ops.led_on = e1000_led_on_82543; ++ mac->ops.led_off = e1000_led_off_82543; ++ /* clear hardware counters */ ++ mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543; ++ ++ /* Set tbi compatibility */ ++ if ((hw->mac.type != e1000_82543) || ++ (hw->phy.media_type == e1000_media_type_fiber)) ++ e1000_set_tbi_compatibility_82543(hw, false); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_init_function_pointers_82543 - Init func ptrs. ++ * @hw: pointer to the HW structure ++ * ++ * Called to initialize all function pointers and parameters. ++ **/ ++void e1000_init_function_pointers_82543(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_init_function_pointers_82543"); ++ ++ hw->mac.ops.init_params = e1000_init_mac_params_82543; ++ hw->nvm.ops.init_params = e1000_init_nvm_params_82543; ++ hw->phy.ops.init_params = e1000_init_phy_params_82543; ++} ++ ++/** ++ * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status ++ * @hw: pointer to the HW structure ++ * ++ * Returns the current status of 10-bit Interface (TBI) compatibility ++ * (enabled/disabled). ++ **/ ++static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) ++{ ++ struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; ++ bool state = false; ++ ++ DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); ++ ++ if (hw->mac.type != e1000_82543) { ++ DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); ++ goto out; ++ } ++ ++ state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) ++ ? true : false; ++ ++out: ++ return state; ++} ++ ++/** ++ * e1000_set_tbi_compatibility_82543 - Set TBI compatibility ++ * @hw: pointer to the HW structure ++ * @state: enable/disable TBI compatibility ++ * ++ * Enables or disabled 10-bit Interface (TBI) compatibility. ++ **/ ++void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state) ++{ ++ struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; ++ ++ DEBUGFUNC("e1000_set_tbi_compatibility_82543"); ++ ++ if (hw->mac.type != e1000_82543) { ++ DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); ++ goto out; ++ } ++ ++ if (state) ++ dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; ++ else ++ dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; ++ ++out: ++ return; ++} ++ ++/** ++ * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status ++ * @hw: pointer to the HW structure ++ * ++ * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP) ++ * (enabled/disabled). ++ **/ ++bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) ++{ ++ struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; ++ bool state = false; ++ ++ DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); ++ ++ if (hw->mac.type != e1000_82543) { ++ DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); ++ goto out; ++ } ++ ++ state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) ++ ? true : false; ++ ++out: ++ return state; ++} ++ ++/** ++ * e1000_set_tbi_sbp_82543 - Set TBI SBP ++ * @hw: pointer to the HW structure ++ * @state: enable/disable TBI store bad packet ++ * ++ * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). ++ **/ ++static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state) ++{ ++ struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; ++ ++ DEBUGFUNC("e1000_set_tbi_sbp_82543"); ++ ++ if (state && e1000_tbi_compatibility_enabled_82543(hw)) ++ dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; ++ else ++ dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; ++ ++ return; ++} ++ ++/** ++ * e1000_init_phy_disabled_82543 - Returns init PHY status ++ * @hw: pointer to the HW structure ++ * ++ * Returns the current status of whether PHY initialization is disabled. ++ * True if PHY initialization is disabled else false. ++ **/ ++static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw) ++{ ++ struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; ++ bool ret_val; ++ ++ DEBUGFUNC("e1000_init_phy_disabled_82543"); ++ ++ if (hw->mac.type != e1000_82543) { ++ ret_val = false; ++ goto out; ++ } ++ ++ ret_val = dev_spec->init_phy_disabled; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled ++ * @hw: pointer to the HW structure ++ * @stats: Struct containing statistic register values ++ * @frame_len: The length of the frame in question ++ * @mac_addr: The Ethernet destination address of the frame in question ++ * @max_frame_size: The maximum frame size ++ * ++ * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT ++ **/ ++void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, ++ struct e1000_hw_stats *stats, u32 frame_len, ++ u8 *mac_addr, u32 max_frame_size) ++{ ++ if (!(e1000_tbi_sbp_enabled_82543(hw))) ++ goto out; ++ ++ /* First adjust the frame length. */ ++ frame_len--; ++ /* ++ * We need to adjust the statistics counters, since the hardware ++ * counters overcount this packet as a CRC error and undercount ++ * the packet as a good packet ++ */ ++ /* This packet should not be counted as a CRC error. */ ++ stats->crcerrs--; ++ /* This packet does count as a Good Packet Received. */ ++ stats->gprc++; ++ ++ /* Adjust the Good Octets received counters */ ++ stats->gorc += frame_len; ++ ++ /* ++ * Is this a broadcast or multicast? Check broadcast first, ++ * since the test for a multicast frame will test positive on ++ * a broadcast frame. ++ */ ++ if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) ++ /* Broadcast packet */ ++ stats->bprc++; ++ else if (*mac_addr & 0x01) ++ /* Multicast packet */ ++ stats->mprc++; ++ ++ /* ++ * In this case, the hardware has overcounted the number of ++ * oversize frames. ++ */ ++ if ((frame_len == max_frame_size) && (stats->roc > 0)) ++ stats->roc--; ++ ++ /* ++ * Adjust the bin counters when the extra byte put the frame in the ++ * wrong bin. Remember that the frame_len was adjusted above. ++ */ ++ if (frame_len == 64) { ++ stats->prc64++; ++ stats->prc127--; ++ } else if (frame_len == 127) { ++ stats->prc127++; ++ stats->prc255--; ++ } else if (frame_len == 255) { ++ stats->prc255++; ++ stats->prc511--; ++ } else if (frame_len == 511) { ++ stats->prc511++; ++ stats->prc1023--; ++ } else if (frame_len == 1023) { ++ stats->prc1023++; ++ stats->prc1522--; ++ } else if (frame_len == 1522) { ++ stats->prc1522++; ++ } ++ ++out: ++ return; ++} ++ ++/** ++ * e1000_read_phy_reg_82543 - Read PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Reads the PHY at offset and stores the information read to data. ++ **/ ++static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ u32 mdic; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_read_phy_reg_82543"); ++ ++ if (offset > MAX_PHY_REG_ADDRESS) { ++ DEBUGOUT1("PHY Address %d is out of range\n", offset); ++ ret_val = -E1000_ERR_PARAM; ++ goto out; ++ } ++ ++ /* ++ * We must first send a preamble through the MDIO pin to signal the ++ * beginning of an MII instruction. This is done by sending 32 ++ * consecutive "1" bits. ++ */ ++ e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); ++ ++ /* ++ * Now combine the next few fields that are required for a read ++ * operation. We use this method instead of calling the ++ * e1000_shift_out_mdi_bits routine five different times. The format ++ * of an MII read instruction consists of a shift out of 14 bits and ++ * is defined as follows: ++ * ++ * followed by a shift in of 18 bits. This first two bits shifted in ++ * are TurnAround bits used to avoid contention on the MDIO pin when a ++ * READ operation is performed. These two bits are thrown away ++ * followed by a shift in of 16 bits which contains the desired data. ++ */ ++ mdic = (offset | (hw->phy.addr << 5) | ++ (PHY_OP_READ << 10) | (PHY_SOF << 12)); ++ ++ e1000_shift_out_mdi_bits_82543(hw, mdic, 14); ++ ++ /* ++ * Now that we've shifted out the read command to the MII, we need to ++ * "shift in" the 16-bit value (18 total bits) of the requested PHY ++ * register address. ++ */ ++ *data = e1000_shift_in_mdi_bits_82543(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_phy_reg_82543 - Write PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be written ++ * @data: pointer to the data to be written at offset ++ * ++ * Writes data to the PHY at offset. ++ **/ ++static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ u32 mdic; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_write_phy_reg_82543"); ++ ++ if (offset > MAX_PHY_REG_ADDRESS) { ++ DEBUGOUT1("PHY Address %d is out of range\n", offset); ++ ret_val = -E1000_ERR_PARAM; ++ goto out; ++ } ++ ++ /* ++ * We'll need to use the SW defined pins to shift the write command ++ * out to the PHY. We first send a preamble to the PHY to signal the ++ * beginning of the MII instruction. This is done by sending 32 ++ * consecutive "1" bits. ++ */ ++ e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); ++ ++ /* ++ * Now combine the remaining required fields that will indicate a ++ * write operation. We use this method instead of calling the ++ * e1000_shift_out_mdi_bits routine for each field in the command. The ++ * format of a MII write instruction is as follows: ++ * . ++ */ ++ mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | ++ (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); ++ mdic <<= 16; ++ mdic |= (u32) data; ++ ++ e1000_shift_out_mdi_bits_82543(hw, mdic, 32); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock ++ * @hw: pointer to the HW structure ++ * @ctrl: pointer to the control register ++ * ++ * Raise the management data input clock by setting the MDC bit in the control ++ * register. ++ **/ ++static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) ++{ ++ /* ++ * Raise the clock input to the Management Data Clock (by setting the ++ * MDC bit), and then delay a sufficient amount of time. ++ */ ++ E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); ++ E1000_WRITE_FLUSH(hw); ++ usec_delay(10); ++} ++ ++/** ++ * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock ++ * @hw: pointer to the HW structure ++ * @ctrl: pointer to the control register ++ * ++ * Lower the management data input clock by clearing the MDC bit in the ++ * control register. ++ **/ ++static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) ++{ ++ /* ++ * Lower the clock input to the Management Data Clock (by clearing the ++ * MDC bit), and then delay a sufficient amount of time. ++ */ ++ E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); ++ E1000_WRITE_FLUSH(hw); ++ usec_delay(10); ++} ++ ++/** ++ * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY ++ * @hw: pointer to the HW structure ++ * @data: data to send to the PHY ++ * @count: number of bits to shift out ++ * ++ * We need to shift 'count' bits out to the PHY. So, the value in the ++ * "data" parameter will be shifted out to the PHY one bit at a time. ++ * In order to do this, "data" must be broken down into bits. ++ **/ ++static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, ++ u16 count) ++{ ++ u32 ctrl, mask; ++ ++ /* ++ * We need to shift "count" number of bits out to the PHY. So, the ++ * value in the "data" parameter will be shifted out to the PHY one ++ * bit at a time. In order to do this, "data" must be broken down ++ * into bits. ++ */ ++ mask = 0x01; ++ mask <<= (count -1); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ ++ ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); ++ ++ while (mask) { ++ /* ++ * A "1" is shifted out to the PHY by setting the MDIO bit to ++ * "1" and then raising and lowering the Management Data Clock. ++ * A "0" is shifted out to the PHY by setting the MDIO bit to ++ * "0" and then raising and lowering the clock. ++ */ ++ if (data & mask) ctrl |= E1000_CTRL_MDIO; ++ else ctrl &= ~E1000_CTRL_MDIO; ++ ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ E1000_WRITE_FLUSH(hw); ++ ++ usec_delay(10); ++ ++ e1000_raise_mdi_clk_82543(hw, &ctrl); ++ e1000_lower_mdi_clk_82543(hw, &ctrl); ++ ++ mask >>= 1; ++ } ++} ++ ++/** ++ * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY ++ * @hw: pointer to the HW structure ++ * ++ * In order to read a register from the PHY, we need to shift 18 bits ++ * in from the PHY. Bits are "shifted in" by raising the clock input to ++ * the PHY (setting the MDC bit), and then reading the value of the data out ++ * MDIO bit. ++ **/ ++static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ u16 data = 0; ++ u8 i; ++ ++ /* ++ * In order to read a register from the PHY, we need to shift in a ++ * total of 18 bits from the PHY. The first two bit (turnaround) ++ * times are used to avoid contention on the MDIO pin when a read ++ * operation is performed. These two bits are ignored by us and ++ * thrown away. Bits are "shifted in" by raising the input to the ++ * Management Data Clock (setting the MDC bit) and then reading the ++ * value of the MDIO bit. ++ */ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ /* ++ * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as ++ * input. ++ */ ++ ctrl &= ~E1000_CTRL_MDIO_DIR; ++ ctrl &= ~E1000_CTRL_MDIO; ++ ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ E1000_WRITE_FLUSH(hw); ++ ++ /* ++ * Raise and lower the clock before reading in the data. This accounts ++ * for the turnaround bits. The first clock occurred when we clocked ++ * out the last bit of the Register Address. ++ */ ++ e1000_raise_mdi_clk_82543(hw, &ctrl); ++ e1000_lower_mdi_clk_82543(hw, &ctrl); ++ ++ for (data = 0, i = 0; i < 16; i++) { ++ data <<= 1; ++ e1000_raise_mdi_clk_82543(hw, &ctrl); ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ /* Check to see if we shifted in a "1". */ ++ if (ctrl & E1000_CTRL_MDIO) ++ data |= 1; ++ e1000_lower_mdi_clk_82543(hw, &ctrl); ++ } ++ ++ e1000_raise_mdi_clk_82543(hw, &ctrl); ++ e1000_lower_mdi_clk_82543(hw, &ctrl); ++ ++ return data; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY ++ * @hw: pointer to the HW structure ++ * ++ * Calls the function to force speed and duplex for the m88 PHY, and ++ * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, ++ * then call the function for polarity reversal workaround. ++ **/ ++static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ ++ DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); ++ ++ ret_val = e1000_phy_force_speed_duplex_m88(hw); ++ if (ret_val) ++ goto out; ++ ++ if (!hw->mac.autoneg && ++ (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) ++ ret_val = e1000_polarity_reversal_workaround_82543(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal ++ * @hw: pointer to the HW structure ++ * ++ * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity ++ * inadvertently. To workaround the issue, we disable the transmitter on ++ * the PHY until we have established the link partner's link parameters. ++ **/ ++static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 mii_status_reg; ++ u16 i; ++ bool link; ++ ++ if (!(hw->phy.ops.write_reg)) ++ goto out; ++ ++ /* Polarity reversal workaround for forced 10F/10H links. */ ++ ++ /* Disable the transmitter on the PHY */ ++ ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); ++ if (ret_val) ++ goto out; ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); ++ if (ret_val) ++ goto out; ++ ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * This loop will early-out if the NO link condition has been met. ++ * In other words, DO NOT use e1000_phy_has_link_generic() here. ++ */ ++ for (i = PHY_FORCE_TIME; i > 0; i--) { ++ /* ++ * Read the MII Status Register and wait for Link Status bit ++ * to be clear. ++ */ ++ ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); ++ if (ret_val) ++ goto out; ++ ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); ++ if (ret_val) ++ goto out; ++ ++ if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) ++ break; ++ msec_delay_irq(100); ++ } ++ ++ /* Recommended delay time after link has been lost */ ++ msec_delay_irq(1000); ++ ++ /* Now we will re-enable the transmitter on the PHY */ ++ ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); ++ if (ret_val) ++ goto out; ++ msec_delay_irq(50); ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); ++ if (ret_val) ++ goto out; ++ msec_delay_irq(50); ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); ++ if (ret_val) ++ goto out; ++ msec_delay_irq(50); ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); ++ if (ret_val) ++ goto out; ++ ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Read the MII Status Register and wait for Link Status bit ++ * to be set. ++ */ ++ ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); ++ if (ret_val) ++ goto out; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_hw_reset_82543 - PHY hardware reset ++ * @hw: pointer to the HW structure ++ * ++ * Sets the PHY_RESET_DIR bit in the extended device control register ++ * to put the PHY into a reset and waits for completion. Once the reset ++ * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out ++ * of reset. ++ **/ ++static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw) ++{ ++ u32 ctrl_ext; ++ s32 ret_val; ++ ++ DEBUGFUNC("e1000_phy_hw_reset_82543"); ++ ++ /* ++ * Read the Extended Device Control Register, assert the PHY_RESET_DIR ++ * bit to put the PHY into reset... ++ */ ++ ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); ++ ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; ++ ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; ++ E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); ++ E1000_WRITE_FLUSH(hw); ++ ++ msec_delay(10); ++ ++ /* ...then take it out of reset. */ ++ ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; ++ E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); ++ E1000_WRITE_FLUSH(hw); ++ ++ usec_delay(150); ++ ++ if (!(hw->phy.ops.get_cfg_done)) ++ return E1000_SUCCESS; ++ ++ ret_val = hw->phy.ops.get_cfg_done(hw); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_reset_hw_82543 - Reset hardware ++ * @hw: pointer to the HW structure ++ * ++ * This resets the hardware into a known state. ++ **/ ++static s32 e1000_reset_hw_82543(struct e1000_hw *hw) ++{ ++ u32 ctrl, icr; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_reset_hw_82543"); ++ ++ DEBUGOUT("Masking off all interrupts\n"); ++ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); ++ ++ E1000_WRITE_REG(hw, E1000_RCTL, 0); ++ E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); ++ E1000_WRITE_FLUSH(hw); ++ ++ e1000_set_tbi_sbp_82543(hw, false); ++ ++ /* ++ * Delay to allow any outstanding PCI transactions to complete before ++ * resetting the device ++ */ ++ msec_delay(10); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); ++ if (hw->mac.type == e1000_82543) { ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); ++ } else { ++ /* ++ * The 82544 can't ACK the 64-bit write when issuing the ++ * reset, so use IO-mapping as a workaround. ++ */ ++ E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); ++ } ++ ++ /* ++ * After MAC reset, force reload of NVM to restore power-on ++ * settings to device. ++ */ ++ hw->nvm.ops.reload(hw); ++ msec_delay(2); ++ ++ /* Masking off and clearing any pending interrupts */ ++ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); ++ icr = E1000_READ_REG(hw, E1000_ICR); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_init_hw_82543 - Initialize hardware ++ * @hw: pointer to the HW structure ++ * ++ * This inits the hardware readying it for operation. ++ **/ ++static s32 e1000_init_hw_82543(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; ++ u32 ctrl; ++ s32 ret_val; ++ u16 i; ++ ++ DEBUGFUNC("e1000_init_hw_82543"); ++ ++ /* Disabling VLAN filtering */ ++ E1000_WRITE_REG(hw, E1000_VET, 0); ++ mac->ops.clear_vfta(hw); ++ ++ /* Setup the receive address. */ ++ e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); ++ ++ /* Zero out the Multicast HASH table */ ++ DEBUGOUT("Zeroing the MTA\n"); ++ for (i = 0; i < mac->mta_reg_count; i++) { ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); ++ E1000_WRITE_FLUSH(hw); ++ } ++ ++ /* ++ * Set the PCI priority bit correctly in the CTRL register. This ++ * determines if the adapter gives priority to receives, or if it ++ * gives equal priority to transmits and receives. ++ */ ++ if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); ++ } ++ ++ e1000_pcix_mmrbc_workaround_generic(hw); ++ ++ /* Setup link and flow control */ ++ ret_val = mac->ops.setup_link(hw); ++ ++ /* ++ * Clear all of the statistics registers (clear on read). It is ++ * important that we do this after we have tried to establish link ++ * because the symbol error count will increment wildly if there ++ * is no link. ++ */ ++ e1000_clear_hw_cntrs_82543(hw); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_link_82543 - Setup flow control and link settings ++ * @hw: pointer to the HW structure ++ * ++ * Read the EEPROM to determine the initial polarity value and write the ++ * extended device control register with the information before calling ++ * the generic setup link function, which does the following: ++ * Determines which flow control settings to use, then configures flow ++ * control. Calls the appropriate media-specific link configuration ++ * function. Assuming the adapter has a valid link partner, a valid link ++ * should be established. Assumes the hardware has previously been reset ++ * and the transmitter and receiver are not enabled. ++ **/ ++static s32 e1000_setup_link_82543(struct e1000_hw *hw) ++{ ++ u32 ctrl_ext; ++ s32 ret_val; ++ u16 data; ++ ++ DEBUGFUNC("e1000_setup_link_82543"); ++ ++ /* ++ * Take the 4 bits from NVM word 0xF that determine the initial ++ * polarity value for the SW controlled pins, and setup the ++ * Extended Device Control reg with that info. ++ * This is needed because one of the SW controlled pins is used for ++ * signal detection. So this should be done before phy setup. ++ */ ++ if (hw->mac.type == e1000_82543) { ++ ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); ++ if (ret_val) { ++ DEBUGOUT("NVM Read Error\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << ++ NVM_SWDPIO_EXT_SHIFT); ++ E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); ++ } ++ ++ ret_val = e1000_setup_link_generic(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_copper_link_82543 - Configure copper link settings ++ * @hw: pointer to the HW structure ++ * ++ * Configures the link for auto-neg or forced speed and duplex. Then we check ++ * for link, once link is established calls to configure collision distance ++ * and flow control are called. ++ **/ ++static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val; ++ bool link; ++ ++ DEBUGFUNC("e1000_setup_copper_link_82543"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; ++ /* ++ * With 82543, we need to force speed and duplex on the MAC ++ * equal to what the PHY speed and duplex configuration is. ++ * In addition, we need to perform a hardware reset on the ++ * PHY to take it out of reset. ++ */ ++ if (hw->mac.type == e1000_82543) { ++ ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ret_val = hw->phy.ops.reset(hw); ++ if (ret_val) ++ goto out; ++ hw->phy.reset_disable = false; ++ } else { ++ ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ } ++ ++ /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ ++ ret_val = e1000_copper_link_setup_m88(hw); ++ if (ret_val) ++ goto out; ++ ++ if (hw->mac.autoneg) { ++ /* ++ * Setup autoneg and flow control advertisement and perform ++ * autonegotiation. ++ */ ++ ret_val = e1000_copper_link_autoneg(hw); ++ if (ret_val) ++ goto out; ++ } else { ++ /* ++ * PHY will be set to 10H, 10F, 100H or 100F ++ * depending on user settings. ++ */ ++ DEBUGOUT("Forcing Speed and Duplex\n"); ++ ret_val = e1000_phy_force_speed_duplex_82543(hw); ++ if (ret_val) { ++ DEBUGOUT("Error Forcing Speed and Duplex\n"); ++ goto out; ++ } ++ } ++ ++ /* ++ * Check link status. Wait up to 100 microseconds for link to become ++ * valid. ++ */ ++ ret_val = e1000_phy_has_link_generic(hw, ++ COPPER_LINK_UP_LIMIT, ++ 10, ++ &link); ++ if (ret_val) ++ goto out; ++ ++ ++ if (link) { ++ DEBUGOUT("Valid link established!!!\n"); ++ /* Config the MAC and PHY after link is up */ ++ if (hw->mac.type == e1000_82544) { ++ e1000_config_collision_dist_generic(hw); ++ } else { ++ ret_val = e1000_config_mac_to_phy_82543(hw); ++ if (ret_val) ++ goto out; ++ } ++ ret_val = e1000_config_fc_after_link_up_generic(hw); ++ } else { ++ DEBUGOUT("Unable to establish link!!!\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_fiber_link_82543 - Setup link for fiber ++ * @hw: pointer to the HW structure ++ * ++ * Configures collision distance and flow control for fiber links. Upon ++ * successful setup, poll for link. ++ **/ ++static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val; ++ ++ DEBUGFUNC("e1000_setup_fiber_link_82543"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ /* Take the link out of reset */ ++ ctrl &= ~E1000_CTRL_LRST; ++ ++ e1000_config_collision_dist_generic(hw); ++ ++ ret_val = e1000_commit_fc_settings_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ DEBUGOUT("Auto-negotiation enabled\n"); ++ ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ E1000_WRITE_FLUSH(hw); ++ msec_delay(1); ++ ++ /* ++ * For these adapters, the SW definable pin 1 is cleared when the ++ * optics detect a signal. If we have a signal, then poll for a ++ * "Link-Up" indication. ++ */ ++ if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { ++ ret_val = e1000_poll_fiber_serdes_link_generic(hw); ++ } else { ++ DEBUGOUT("No signal detected\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_for_copper_link_82543 - Check for link (Copper) ++ * @hw: pointer to the HW structure ++ * ++ * Checks the phy for link, if link exists, do the following: ++ * - check for downshift ++ * - do polarity workaround (if necessary) ++ * - configure collision distance ++ * - configure flow control after link up ++ * - configure tbi compatibility ++ **/ ++static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 icr, rctl; ++ s32 ret_val; ++ u16 speed, duplex; ++ bool link; ++ ++ DEBUGFUNC("e1000_check_for_copper_link_82543"); ++ ++ if (!mac->get_link_status) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) ++ goto out; /* No link detected */ ++ ++ mac->get_link_status = false; ++ ++ e1000_check_downshift_generic(hw); ++ ++ /* ++ * If we are forcing speed/duplex, then we can return since ++ * we have already determined whether we have link or not. ++ */ ++ if (!mac->autoneg) { ++ /* ++ * If speed and duplex are forced to 10H or 10F, then we will ++ * implement the polarity reversal workaround. We disable ++ * interrupts first, and upon returning, place the devices ++ * interrupt state to its previous value except for the link ++ * status change interrupt which will happened due to the ++ * execution of this workaround. ++ */ ++ if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { ++ E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); ++ ret_val = e1000_polarity_reversal_workaround_82543(hw); ++ icr = E1000_READ_REG(hw, E1000_ICR); ++ E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); ++ E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); ++ } ++ ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ /* ++ * We have a M88E1000 PHY and Auto-Neg is enabled. If we ++ * have Si on board that is 82544 or newer, Auto ++ * Speed Detection takes care of MAC speed/duplex ++ * configuration. So we only need to configure Collision ++ * Distance in the MAC. Otherwise, we need to force ++ * speed/duplex on the MAC to the current PHY speed/duplex ++ * settings. ++ */ ++ if (mac->type == e1000_82544) ++ e1000_config_collision_dist_generic(hw); ++ else { ++ ret_val = e1000_config_mac_to_phy_82543(hw); ++ if (ret_val) { ++ DEBUGOUT("Error configuring MAC to PHY settings\n"); ++ goto out; ++ } ++ } ++ ++ /* ++ * Configure Flow Control now that Auto-Neg has completed. ++ * First, we need to restore the desired flow control ++ * settings because we may have had to re-autoneg with a ++ * different link partner. ++ */ ++ ret_val = e1000_config_fc_after_link_up_generic(hw); ++ if (ret_val) { ++ DEBUGOUT("Error configuring flow control\n"); ++ } ++ ++ /* ++ * At this point we know that we are on copper and we have ++ * auto-negotiated link. These are conditions for checking the link ++ * partner capability register. We use the link speed to determine if ++ * TBI compatibility needs to be turned on or off. If the link is not ++ * at gigabit speed, then TBI compatibility is not needed. If we are ++ * at gigabit speed, we turn on TBI compatibility. ++ */ ++ if (e1000_tbi_compatibility_enabled_82543(hw)) { ++ ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); ++ if (ret_val) { ++ DEBUGOUT("Error getting link speed and duplex\n"); ++ return ret_val; ++ } ++ if (speed != SPEED_1000) { ++ /* ++ * If link speed is not set to gigabit speed, ++ * we do not need to enable TBI compatibility. ++ */ ++ if (e1000_tbi_sbp_enabled_82543(hw)) { ++ /* ++ * If we previously were in the mode, ++ * turn it off. ++ */ ++ e1000_set_tbi_sbp_82543(hw, false); ++ rctl = E1000_READ_REG(hw, E1000_RCTL); ++ rctl &= ~E1000_RCTL_SBP; ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); ++ } ++ } else { ++ /* ++ * If TBI compatibility is was previously off, ++ * turn it on. For compatibility with a TBI link ++ * partner, we will store bad packets. Some ++ * frames have an additional byte on the end and ++ * will look like CRC errors to to the hardware. ++ */ ++ if (!e1000_tbi_sbp_enabled_82543(hw)) { ++ e1000_set_tbi_sbp_82543(hw, true); ++ rctl = E1000_READ_REG(hw, E1000_RCTL); ++ rctl |= E1000_RCTL_SBP; ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); ++ } ++ } ++ } ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_for_fiber_link_82543 - Check for link (Fiber) ++ * @hw: pointer to the HW structure ++ * ++ * Checks for link up on the hardware. If link is not up and we have ++ * a signal, then we need to force link up. ++ **/ ++static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 rxcw, ctrl, status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_check_for_fiber_link_82543"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ status = E1000_READ_REG(hw, E1000_STATUS); ++ rxcw = E1000_READ_REG(hw, E1000_RXCW); ++ ++ /* ++ * If we don't have link (auto-negotiation failed or link partner ++ * cannot auto-negotiate), the cable is plugged in (we have signal), ++ * and our link partner is not trying to auto-negotiate with us (we ++ * are receiving idles or data), we need to force link up. We also ++ * need to give auto-negotiation time to complete, in case the cable ++ * was just plugged in. The autoneg_failed flag does this. ++ */ ++ /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ ++ if ((!(ctrl & E1000_CTRL_SWDPIN1)) && ++ (!(status & E1000_STATUS_LU)) && ++ (!(rxcw & E1000_RXCW_C))) { ++ if (mac->autoneg_failed == 0) { ++ mac->autoneg_failed = 1; ++ ret_val = 0; ++ goto out; ++ } ++ DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); ++ ++ /* Disable auto-negotiation in the TXCW register */ ++ E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); ++ ++ /* Force link-up and also force full-duplex. */ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++ /* Configure Flow Control after forcing link up. */ ++ ret_val = e1000_config_fc_after_link_up_generic(hw); ++ if (ret_val) { ++ DEBUGOUT("Error configuring flow control\n"); ++ goto out; ++ } ++ } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { ++ /* ++ * If we are forcing link and we are receiving /C/ ordered ++ * sets, re-enable auto-negotiation in the TXCW register ++ * and disable forced link in the Device Control register ++ * in an attempt to auto-negotiate with our link partner. ++ */ ++ DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); ++ E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); ++ E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); ++ ++ mac->serdes_has_link = true; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings ++ * @hw: pointer to the HW structure ++ * ++ * For the 82543 silicon, we need to set the MAC to match the settings ++ * of the PHY, even if the PHY is auto-negotiating. ++ **/ ++static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ u16 phy_data; ++ ++ DEBUGFUNC("e1000_config_mac_to_phy_82543"); ++ ++ if (!(hw->phy.ops.read_reg)) ++ goto out; ++ ++ /* Set the bits to force speed and duplex */ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); ++ ++ /* ++ * Set up duplex in the Device Control and Transmit Control ++ * registers depending on negotiated values. ++ */ ++ ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ ctrl &= ~E1000_CTRL_FD; ++ if (phy_data & M88E1000_PSSR_DPLX) ++ ctrl |= E1000_CTRL_FD; ++ ++ e1000_config_collision_dist_generic(hw); ++ ++ /* ++ * Set up speed in the Device Control register depending on ++ * negotiated values. ++ */ ++ if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) ++ ctrl |= E1000_CTRL_SPD_1000; ++ else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) ++ ctrl |= E1000_CTRL_SPD_100; ++ ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_vfta_82543 - Write value to VLAN filter table ++ * @hw: pointer to the HW structure ++ * @offset: the 32-bit offset in which to write the value to. ++ * @value: the 32-bit value to write at location offset. ++ * ++ * This writes a 32-bit value to a 32-bit offset in the VLAN filter ++ * table. ++ **/ ++static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) ++{ ++ u32 temp; ++ ++ DEBUGFUNC("e1000_write_vfta_82543"); ++ ++ if ((hw->mac.type == e1000_82544) && (offset & 1)) { ++ temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); ++ E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); ++ E1000_WRITE_FLUSH(hw); ++ E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); ++ E1000_WRITE_FLUSH(hw); ++ } else { ++ e1000_write_vfta_generic(hw, offset, value); ++ } ++} ++ ++/** ++ * e1000_mta_set_82543 - Set multicast filter table address ++ * @hw: pointer to the HW structure ++ * @hash_value: determines the MTA register and bit to set ++ * ++ * The multicast table address is a register array of 32-bit registers. ++ * The hash_value is used to determine what register the bit is in, the ++ * current value is read, the new bit is OR'd in and the new value is ++ * written back into the register. ++ **/ ++static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value) ++{ ++ u32 hash_bit, hash_reg, mta, temp; ++ ++ DEBUGFUNC("e1000_mta_set_82543"); ++ ++ hash_reg = (hash_value >> 5); ++ ++ /* ++ * If we are on an 82544 and we are trying to write an odd offset ++ * in the MTA, save off the previous entry before writing and ++ * restore the old value after writing. ++ */ ++ if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) { ++ hash_reg &= (hw->mac.mta_reg_count - 1); ++ hash_bit = hash_value & 0x1F; ++ mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); ++ mta |= (1 << hash_bit); ++ temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1); ++ ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); ++ E1000_WRITE_FLUSH(hw); ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp); ++ E1000_WRITE_FLUSH(hw); ++ } else { ++ e1000_mta_set_generic(hw, hash_value); ++ } ++} ++ ++/** ++ * e1000_led_on_82543 - Turn on SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * Turns the SW defined LED on. ++ **/ ++static s32 e1000_led_on_82543(struct e1000_hw *hw) ++{ ++ u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ DEBUGFUNC("e1000_led_on_82543"); ++ ++ if (hw->mac.type == e1000_82544 && ++ hw->phy.media_type == e1000_media_type_copper) { ++ /* Clear SW-definable Pin 0 to turn on the LED */ ++ ctrl &= ~E1000_CTRL_SWDPIN0; ++ ctrl |= E1000_CTRL_SWDPIO0; ++ } else { ++ /* Fiber 82544 and all 82543 use this method */ ++ ctrl |= E1000_CTRL_SWDPIN0; ++ ctrl |= E1000_CTRL_SWDPIO0; ++ } ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_led_off_82543 - Turn off SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * Turns the SW defined LED off. ++ **/ ++static s32 e1000_led_off_82543(struct e1000_hw *hw) ++{ ++ u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ DEBUGFUNC("e1000_led_off_82543"); ++ ++ if (hw->mac.type == e1000_82544 && ++ hw->phy.media_type == e1000_media_type_copper) { ++ /* Set SW-definable Pin 0 to turn off the LED */ ++ ctrl |= E1000_CTRL_SWDPIN0; ++ ctrl |= E1000_CTRL_SWDPIO0; ++ } else { ++ ctrl &= ~E1000_CTRL_SWDPIN0; ++ ctrl |= E1000_CTRL_SWDPIO0; ++ } ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters ++ * @hw: pointer to the HW structure ++ * ++ * Clears the hardware counters by reading the counter registers. ++ **/ ++static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_clear_hw_cntrs_82543"); ++ ++ e1000_clear_hw_cntrs_base_generic(hw); ++ ++ E1000_READ_REG(hw, E1000_PRC64); ++ E1000_READ_REG(hw, E1000_PRC127); ++ E1000_READ_REG(hw, E1000_PRC255); ++ E1000_READ_REG(hw, E1000_PRC511); ++ E1000_READ_REG(hw, E1000_PRC1023); ++ E1000_READ_REG(hw, E1000_PRC1522); ++ E1000_READ_REG(hw, E1000_PTC64); ++ E1000_READ_REG(hw, E1000_PTC127); ++ E1000_READ_REG(hw, E1000_PTC255); ++ E1000_READ_REG(hw, E1000_PTC511); ++ E1000_READ_REG(hw, E1000_PTC1023); ++ E1000_READ_REG(hw, E1000_PTC1522); ++ ++ E1000_READ_REG(hw, E1000_ALGNERRC); ++ E1000_READ_REG(hw, E1000_RXERRC); ++ E1000_READ_REG(hw, E1000_TNCRS); ++ E1000_READ_REG(hw, E1000_CEXTERR); ++ E1000_READ_REG(hw, E1000_TSCTC); ++ E1000_READ_REG(hw, E1000_TSCTFC); ++} +diff -r b58885ce604a drivers/net/e1000/e1000_82543.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_82543.h Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,51 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_82543_H_ ++#define _E1000_82543_H_ ++ ++#define PHY_PREAMBLE 0xFFFFFFFF ++#define PHY_PREAMBLE_SIZE 32 ++#define PHY_SOF 0x1 ++#define PHY_OP_READ 0x2 ++#define PHY_OP_WRITE 0x1 ++#define PHY_TURNAROUND 0x2 ++ ++#define TBI_COMPAT_ENABLED 0x1 /* Global "knob" for the workaround */ ++/* If TBI_COMPAT_ENABLED, then this is the current state (on/off) */ ++#define TBI_SBP_ENABLED 0x2 ++ ++void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, ++ struct e1000_hw_stats *stats, ++ u32 frame_len, u8 *mac_addr, ++ u32 max_frame_size); ++void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, ++ bool state); ++bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw); ++ ++#endif +diff -r b58885ce604a drivers/net/e1000/e1000_82571.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_82571.h Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,40 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_82571_H_ ++#define _E1000_82571_H_ ++ ++#define ID_LED_RESERVED_F746 0xF746 ++#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ ++ (ID_LED_OFF1_ON2 << 8) | \ ++ (ID_LED_DEF1_DEF2 << 4) | \ ++ (ID_LED_DEF1_DEF2)) ++ ++#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 ++ ++#endif +diff -r b58885ce604a drivers/net/e1000/e1000_api.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_api.c Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,1102 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000_api.h" ++ ++/** ++ * e1000_init_mac_params - Initialize MAC function pointers ++ * @hw: pointer to the HW structure ++ * ++ * This function initializes the function pointers for the MAC ++ * set of functions. Called by drivers or by e1000_setup_init_funcs. ++ **/ ++s32 e1000_init_mac_params(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->mac.ops.init_params) { ++ ret_val = hw->mac.ops.init_params(hw); ++ if (ret_val) { ++ DEBUGOUT("MAC Initialization Error\n"); ++ goto out; ++ } ++ } else { ++ DEBUGOUT("mac.init_mac_params was NULL\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_nvm_params - Initialize NVM function pointers ++ * @hw: pointer to the HW structure ++ * ++ * This function initializes the function pointers for the NVM ++ * set of functions. Called by drivers or by e1000_setup_init_funcs. ++ **/ ++s32 e1000_init_nvm_params(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->nvm.ops.init_params) { ++ ret_val = hw->nvm.ops.init_params(hw); ++ if (ret_val) { ++ DEBUGOUT("NVM Initialization Error\n"); ++ goto out; ++ } ++ } else { ++ DEBUGOUT("nvm.init_nvm_params was NULL\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_phy_params - Initialize PHY function pointers ++ * @hw: pointer to the HW structure ++ * ++ * This function initializes the function pointers for the PHY ++ * set of functions. Called by drivers or by e1000_setup_init_funcs. ++ **/ ++s32 e1000_init_phy_params(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->phy.ops.init_params) { ++ ret_val = hw->phy.ops.init_params(hw); ++ if (ret_val) { ++ DEBUGOUT("PHY Initialization Error\n"); ++ goto out; ++ } ++ } else { ++ DEBUGOUT("phy.init_phy_params was NULL\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ } ++ ++out: ++ return ret_val; ++} ++ ++ ++/** ++ * e1000_set_mac_type - Sets MAC type ++ * @hw: pointer to the HW structure ++ * ++ * This function sets the mac type of the adapter based on the ++ * device ID stored in the hw structure. ++ * MUST BE FIRST FUNCTION CALLED (explicitly or through ++ * e1000_setup_init_funcs()). ++ **/ ++s32 e1000_set_mac_type(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_set_mac_type"); ++ ++ switch (hw->device_id) { ++ case E1000_DEV_ID_82542: ++ mac->type = e1000_82542; ++ break; ++ case E1000_DEV_ID_82543GC_FIBER: ++ case E1000_DEV_ID_82543GC_COPPER: ++ mac->type = e1000_82543; ++ break; ++ case E1000_DEV_ID_82544EI_COPPER: ++ case E1000_DEV_ID_82544EI_FIBER: ++ case E1000_DEV_ID_82544GC_COPPER: ++ case E1000_DEV_ID_82544GC_LOM: ++ mac->type = e1000_82544; ++ break; ++ case E1000_DEV_ID_82540EM: ++ case E1000_DEV_ID_82540EM_LOM: ++ case E1000_DEV_ID_82540EP: ++ case E1000_DEV_ID_82540EP_LOM: ++ case E1000_DEV_ID_82540EP_LP: ++ mac->type = e1000_82540; ++ break; ++ case E1000_DEV_ID_82545EM_COPPER: ++ case E1000_DEV_ID_82545EM_FIBER: ++ mac->type = e1000_82545; ++ break; ++ case E1000_DEV_ID_82545GM_COPPER: ++ case E1000_DEV_ID_82545GM_FIBER: ++ case E1000_DEV_ID_82545GM_SERDES: ++ mac->type = e1000_82545_rev_3; ++ break; ++ case E1000_DEV_ID_82546EB_COPPER: ++ case E1000_DEV_ID_82546EB_FIBER: ++ case E1000_DEV_ID_82546EB_QUAD_COPPER: ++ mac->type = e1000_82546; ++ break; ++ case E1000_DEV_ID_82546GB_COPPER: ++ case E1000_DEV_ID_82546GB_FIBER: ++ case E1000_DEV_ID_82546GB_SERDES: ++ case E1000_DEV_ID_82546GB_PCIE: ++ case E1000_DEV_ID_82546GB_QUAD_COPPER: ++ case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: ++ mac->type = e1000_82546_rev_3; ++ break; ++ case E1000_DEV_ID_82541EI: ++ case E1000_DEV_ID_82541EI_MOBILE: ++ case E1000_DEV_ID_82541ER_LOM: ++ mac->type = e1000_82541; ++ break; ++ case E1000_DEV_ID_82541ER: ++ case E1000_DEV_ID_82541GI: ++ case E1000_DEV_ID_82541GI_LF: ++ case E1000_DEV_ID_82541GI_MOBILE: ++ mac->type = e1000_82541_rev_2; ++ break; ++ case E1000_DEV_ID_82547EI: ++ case E1000_DEV_ID_82547EI_MOBILE: ++ mac->type = e1000_82547; ++ break; ++ case E1000_DEV_ID_82547GI: ++ mac->type = e1000_82547_rev_2; ++ break; ++ default: ++ /* Should never have loaded on this device */ ++ ret_val = -E1000_ERR_MAC_INIT; ++ break; ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_init_funcs - Initializes function pointers ++ * @hw: pointer to the HW structure ++ * @init_device: true will initialize the rest of the function pointers ++ * getting the device ready for use. false will only set ++ * MAC type and the function pointers for the other init ++ * functions. Passing false will not generate any hardware ++ * reads or writes. ++ * ++ * This function must be called by a driver in order to use the rest ++ * of the 'shared' code files. Called by drivers only. ++ **/ ++s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device) ++{ ++ s32 ret_val; ++ ++ /* Can't do much good without knowing the MAC type. */ ++ ret_val = e1000_set_mac_type(hw); ++ if (ret_val) { ++ DEBUGOUT("ERROR: MAC type could not be set properly.\n"); ++ goto out; ++ } ++ ++ if (!hw->hw_addr) { ++ DEBUGOUT("ERROR: Registers not mapped\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ /* ++ * Init function pointers to generic implementations. We do this first ++ * allowing a driver module to override it afterward. ++ */ ++ e1000_init_mac_ops_generic(hw); ++ e1000_init_phy_ops_generic(hw); ++ e1000_init_nvm_ops_generic(hw); ++ ++ /* ++ * Set up the init function pointers. These are functions within the ++ * adapter family file that sets up function pointers for the rest of ++ * the functions in that family. ++ */ ++ switch (hw->mac.type) { ++ case e1000_82542: ++ e1000_init_function_pointers_82542(hw); ++ break; ++ case e1000_82543: ++ case e1000_82544: ++ e1000_init_function_pointers_82543(hw); ++ break; ++ case e1000_82540: ++ case e1000_82545: ++ case e1000_82545_rev_3: ++ case e1000_82546: ++ case e1000_82546_rev_3: ++ e1000_init_function_pointers_82540(hw); ++ break; ++ case e1000_82541: ++ case e1000_82541_rev_2: ++ case e1000_82547: ++ case e1000_82547_rev_2: ++ e1000_init_function_pointers_82541(hw); ++ break; ++ default: ++ DEBUGOUT("Hardware not supported\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ break; ++ } ++ ++ /* ++ * Initialize the rest of the function pointers. These require some ++ * register reads/writes in some cases. ++ */ ++ if (!(ret_val) && init_device) { ++ ret_val = e1000_init_mac_params(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_init_nvm_params(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_init_phy_params(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_bus_info - Obtain bus information for adapter ++ * @hw: pointer to the HW structure ++ * ++ * This will obtain information about the HW bus for which the ++ * adapter is attached and stores it in the hw structure. This is a ++ * function pointer entry point called by drivers. ++ **/ ++s32 e1000_get_bus_info(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.get_bus_info) ++ return hw->mac.ops.get_bus_info(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_clear_vfta - Clear VLAN filter table ++ * @hw: pointer to the HW structure ++ * ++ * This clears the VLAN filter table on the adapter. This is a function ++ * pointer entry point called by drivers. ++ **/ ++void e1000_clear_vfta(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.clear_vfta) ++ hw->mac.ops.clear_vfta(hw); ++} ++ ++/** ++ * e1000_write_vfta - Write value to VLAN filter table ++ * @hw: pointer to the HW structure ++ * @offset: the 32-bit offset in which to write the value to. ++ * @value: the 32-bit value to write at location offset. ++ * ++ * This writes a 32-bit value to a 32-bit offset in the VLAN filter ++ * table. This is a function pointer entry point called by drivers. ++ **/ ++void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) ++{ ++ if (hw->mac.ops.write_vfta) ++ hw->mac.ops.write_vfta(hw, offset, value); ++} ++ ++/** ++ * e1000_update_mc_addr_list - Update Multicast addresses ++ * @hw: pointer to the HW structure ++ * @mc_addr_list: array of multicast addresses to program ++ * @mc_addr_count: number of multicast addresses to program ++ * ++ * Updates the Multicast Table Array. ++ * The caller must have a packed mc_addr_list of multicast addresses. ++ **/ ++void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list, ++ u32 mc_addr_count) ++{ ++ if (hw->mac.ops.update_mc_addr_list) ++ hw->mac.ops.update_mc_addr_list(hw, mc_addr_list, ++ mc_addr_count); ++} ++ ++/** ++ * e1000_force_mac_fc - Force MAC flow control ++ * @hw: pointer to the HW structure ++ * ++ * Force the MAC's flow control settings. Currently no func pointer exists ++ * and all implementations are handled in the generic version of this ++ * function. ++ **/ ++s32 e1000_force_mac_fc(struct e1000_hw *hw) ++{ ++ return e1000_force_mac_fc_generic(hw); ++} ++ ++/** ++ * e1000_check_for_link - Check/Store link connection ++ * @hw: pointer to the HW structure ++ * ++ * This checks the link condition of the adapter and stores the ++ * results in the hw->mac structure. This is a function pointer entry ++ * point called by drivers. ++ **/ ++s32 e1000_check_for_link(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.check_for_link) ++ return hw->mac.ops.check_for_link(hw); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_check_mng_mode - Check management mode ++ * @hw: pointer to the HW structure ++ * ++ * This checks if the adapter has manageability enabled. ++ * This is a function pointer entry point called by drivers. ++ **/ ++bool e1000_check_mng_mode(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.check_mng_mode) ++ return hw->mac.ops.check_mng_mode(hw); ++ ++ return false; ++} ++ ++/** ++ * e1000_mng_write_dhcp_info - Writes DHCP info to host interface ++ * @hw: pointer to the HW structure ++ * @buffer: pointer to the host interface ++ * @length: size of the buffer ++ * ++ * Writes the DHCP information to the host interface. ++ **/ ++s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) ++{ ++ return e1000_mng_write_dhcp_info_generic(hw, buffer, length); ++} ++ ++/** ++ * e1000_reset_hw - Reset hardware ++ * @hw: pointer to the HW structure ++ * ++ * This resets the hardware into a known state. This is a function pointer ++ * entry point called by drivers. ++ **/ ++s32 e1000_reset_hw(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.reset_hw) ++ return hw->mac.ops.reset_hw(hw); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_init_hw - Initialize hardware ++ * @hw: pointer to the HW structure ++ * ++ * This inits the hardware readying it for operation. This is a function ++ * pointer entry point called by drivers. ++ **/ ++s32 e1000_init_hw(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.init_hw) ++ return hw->mac.ops.init_hw(hw); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_setup_link - Configures link and flow control ++ * @hw: pointer to the HW structure ++ * ++ * This configures link and flow control settings for the adapter. This ++ * is a function pointer entry point called by drivers. While modules can ++ * also call this, they probably call their own version of this function. ++ **/ ++s32 e1000_setup_link(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.setup_link) ++ return hw->mac.ops.setup_link(hw); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_get_speed_and_duplex - Returns current speed and duplex ++ * @hw: pointer to the HW structure ++ * @speed: pointer to a 16-bit value to store the speed ++ * @duplex: pointer to a 16-bit value to store the duplex. ++ * ++ * This returns the speed and duplex of the adapter in the two 'out' ++ * variables passed in. This is a function pointer entry point called ++ * by drivers. ++ **/ ++s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) ++{ ++ if (hw->mac.ops.get_link_up_info) ++ return hw->mac.ops.get_link_up_info(hw, speed, duplex); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_setup_led - Configures SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * This prepares the SW controllable LED for use and saves the current state ++ * of the LED so it can be later restored. This is a function pointer entry ++ * point called by drivers. ++ **/ ++s32 e1000_setup_led(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.setup_led) ++ return hw->mac.ops.setup_led(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_cleanup_led - Restores SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * This restores the SW controllable LED to the value saved off by ++ * e1000_setup_led. This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_cleanup_led(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.cleanup_led) ++ return hw->mac.ops.cleanup_led(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_blink_led - Blink SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * This starts the adapter LED blinking. Request the LED to be setup first ++ * and cleaned up after. This is a function pointer entry point called by ++ * drivers. ++ **/ ++s32 e1000_blink_led(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.blink_led) ++ return hw->mac.ops.blink_led(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_id_led_init - store LED configurations in SW ++ * @hw: pointer to the HW structure ++ * ++ * Initializes the LED config in SW. This is a function pointer entry point ++ * called by drivers. ++ **/ ++s32 e1000_id_led_init(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.id_led_init) ++ return hw->mac.ops.id_led_init(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_led_on - Turn on SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * Turns the SW defined LED on. This is a function pointer entry point ++ * called by drivers. ++ **/ ++s32 e1000_led_on(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.led_on) ++ return hw->mac.ops.led_on(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_led_off - Turn off SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * Turns the SW defined LED off. This is a function pointer entry point ++ * called by drivers. ++ **/ ++s32 e1000_led_off(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.led_off) ++ return hw->mac.ops.led_off(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_reset_adaptive - Reset adaptive IFS ++ * @hw: pointer to the HW structure ++ * ++ * Resets the adaptive IFS. Currently no func pointer exists and all ++ * implementations are handled in the generic version of this function. ++ **/ ++void e1000_reset_adaptive(struct e1000_hw *hw) ++{ ++ e1000_reset_adaptive_generic(hw); ++} ++ ++/** ++ * e1000_update_adaptive - Update adaptive IFS ++ * @hw: pointer to the HW structure ++ * ++ * Updates adapter IFS. Currently no func pointer exists and all ++ * implementations are handled in the generic version of this function. ++ **/ ++void e1000_update_adaptive(struct e1000_hw *hw) ++{ ++ e1000_update_adaptive_generic(hw); ++} ++ ++/** ++ * e1000_disable_pcie_master - Disable PCI-Express master access ++ * @hw: pointer to the HW structure ++ * ++ * Disables PCI-Express master access and verifies there are no pending ++ * requests. Currently no func pointer exists and all implementations are ++ * handled in the generic version of this function. ++ **/ ++s32 e1000_disable_pcie_master(struct e1000_hw *hw) ++{ ++ return e1000_disable_pcie_master_generic(hw); ++} ++ ++/** ++ * e1000_config_collision_dist - Configure collision distance ++ * @hw: pointer to the HW structure ++ * ++ * Configures the collision distance to the default value and is used ++ * during link setup. ++ **/ ++void e1000_config_collision_dist(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.config_collision_dist) ++ hw->mac.ops.config_collision_dist(hw); ++} ++ ++/** ++ * e1000_rar_set - Sets a receive address register ++ * @hw: pointer to the HW structure ++ * @addr: address to set the RAR to ++ * @index: the RAR to set ++ * ++ * Sets a Receive Address Register (RAR) to the specified address. ++ **/ ++void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) ++{ ++ if (hw->mac.ops.rar_set) ++ hw->mac.ops.rar_set(hw, addr, index); ++} ++ ++/** ++ * e1000_validate_mdi_setting - Ensures valid MDI/MDIX SW state ++ * @hw: pointer to the HW structure ++ * ++ * Ensures that the MDI/MDIX SW state is valid. ++ **/ ++s32 e1000_validate_mdi_setting(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.validate_mdi_setting) ++ return hw->mac.ops.validate_mdi_setting(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_mta_set - Sets multicast table bit ++ * @hw: pointer to the HW structure ++ * @hash_value: Multicast hash value. ++ * ++ * This sets the bit in the multicast table corresponding to the ++ * hash value. This is a function pointer entry point called by drivers. ++ **/ ++void e1000_mta_set(struct e1000_hw *hw, u32 hash_value) ++{ ++ if (hw->mac.ops.mta_set) ++ hw->mac.ops.mta_set(hw, hash_value); ++} ++ ++/** ++ * e1000_hash_mc_addr - Determines address location in multicast table ++ * @hw: pointer to the HW structure ++ * @mc_addr: Multicast address to hash. ++ * ++ * This hashes an address to determine its location in the multicast ++ * table. Currently no func pointer exists and all implementations ++ * are handled in the generic version of this function. ++ **/ ++u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) ++{ ++ return e1000_hash_mc_addr_generic(hw, mc_addr); ++} ++ ++/** ++ * e1000_enable_tx_pkt_filtering - Enable packet filtering on TX ++ * @hw: pointer to the HW structure ++ * ++ * Enables packet filtering on transmit packets if manageability is enabled ++ * and host interface is enabled. ++ * Currently no func pointer exists and all implementations are handled in the ++ * generic version of this function. ++ **/ ++bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) ++{ ++ return e1000_enable_tx_pkt_filtering_generic(hw); ++} ++ ++/** ++ * e1000_mng_host_if_write - Writes to the manageability host interface ++ * @hw: pointer to the HW structure ++ * @buffer: pointer to the host interface buffer ++ * @length: size of the buffer ++ * @offset: location in the buffer to write to ++ * @sum: sum of the data (not checksum) ++ * ++ * This function writes the buffer content at the offset given on the host if. ++ * It also does alignment considerations to do the writes in most efficient ++ * way. Also fills up the sum of the buffer in *buffer parameter. ++ **/ ++s32 e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer, u16 length, ++ u16 offset, u8 *sum) ++{ ++ if (hw->mac.ops.mng_host_if_write) ++ return hw->mac.ops.mng_host_if_write(hw, buffer, length, ++ offset, sum); ++ ++ return E1000_NOT_IMPLEMENTED; ++} ++ ++/** ++ * e1000_mng_write_cmd_header - Writes manageability command header ++ * @hw: pointer to the HW structure ++ * @hdr: pointer to the host interface command header ++ * ++ * Writes the command header after does the checksum calculation. ++ **/ ++s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header *hdr) ++{ ++ if (hw->mac.ops.mng_write_cmd_header) ++ return hw->mac.ops.mng_write_cmd_header(hw, hdr); ++ ++ return E1000_NOT_IMPLEMENTED; ++} ++ ++/** ++ * e1000_mng_enable_host_if - Checks host interface is enabled ++ * @hw: pointer to the HW structure ++ * ++ * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND ++ * ++ * This function checks whether the HOST IF is enabled for command operation ++ * and also checks whether the previous command is completed. It busy waits ++ * in case of previous command is not completed. ++ **/ ++s32 e1000_mng_enable_host_if(struct e1000_hw * hw) ++{ ++ if (hw->mac.ops.mng_enable_host_if) ++ return hw->mac.ops.mng_enable_host_if(hw); ++ ++ return E1000_NOT_IMPLEMENTED; ++} ++ ++/** ++ * e1000_wait_autoneg - Waits for autonegotiation completion ++ * @hw: pointer to the HW structure ++ * ++ * Waits for autoneg to complete. Currently no func pointer exists and all ++ * implementations are handled in the generic version of this function. ++ **/ ++s32 e1000_wait_autoneg(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.wait_autoneg) ++ return hw->mac.ops.wait_autoneg(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_check_reset_block - Verifies PHY can be reset ++ * @hw: pointer to the HW structure ++ * ++ * Checks if the PHY is in a state that can be reset or if manageability ++ * has it tied up. This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_check_reset_block(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.check_reset_block) ++ return hw->phy.ops.check_reset_block(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_read_phy_reg - Reads PHY register ++ * @hw: pointer to the HW structure ++ * @offset: the register to read ++ * @data: the buffer to store the 16-bit read. ++ * ++ * Reads the PHY register and returns the value in data. ++ * This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ if (hw->phy.ops.read_reg) ++ return hw->phy.ops.read_reg(hw, offset, data); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_write_phy_reg - Writes PHY register ++ * @hw: pointer to the HW structure ++ * @offset: the register to write ++ * @data: the value to write. ++ * ++ * Writes the PHY register at offset with the value in data. ++ * This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ if (hw->phy.ops.write_reg) ++ return hw->phy.ops.write_reg(hw, offset, data); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_release_phy - Generic release PHY ++ * @hw: pointer to the HW structure ++ * ++ * Return if silicon family does not require a semaphore when accessing the ++ * PHY. ++ **/ ++void e1000_release_phy(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.release) ++ hw->phy.ops.release(hw); ++} ++ ++/** ++ * e1000_acquire_phy - Generic acquire PHY ++ * @hw: pointer to the HW structure ++ * ++ * Return success if silicon family does not require a semaphore when ++ * accessing the PHY. ++ **/ ++s32 e1000_acquire_phy(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.acquire) ++ return hw->phy.ops.acquire(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_read_kmrn_reg - Reads register using Kumeran interface ++ * @hw: pointer to the HW structure ++ * @offset: the register to read ++ * @data: the location to store the 16-bit value read. ++ * ++ * Reads a register out of the Kumeran interface. Currently no func pointer ++ * exists and all implementations are handled in the generic version of ++ * this function. ++ **/ ++s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ return e1000_read_kmrn_reg_generic(hw, offset, data); ++} ++ ++/** ++ * e1000_write_kmrn_reg - Writes register using Kumeran interface ++ * @hw: pointer to the HW structure ++ * @offset: the register to write ++ * @data: the value to write. ++ * ++ * Writes a register to the Kumeran interface. Currently no func pointer ++ * exists and all implementations are handled in the generic version of ++ * this function. ++ **/ ++s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ return e1000_write_kmrn_reg_generic(hw, offset, data); ++} ++ ++/** ++ * e1000_get_cable_length - Retrieves cable length estimation ++ * @hw: pointer to the HW structure ++ * ++ * This function estimates the cable length and stores them in ++ * hw->phy.min_length and hw->phy.max_length. This is a function pointer ++ * entry point called by drivers. ++ **/ ++s32 e1000_get_cable_length(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.get_cable_length) ++ return hw->phy.ops.get_cable_length(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_get_phy_info - Retrieves PHY information from registers ++ * @hw: pointer to the HW structure ++ * ++ * This function gets some information from various PHY registers and ++ * populates hw->phy values with it. This is a function pointer entry ++ * point called by drivers. ++ **/ ++s32 e1000_get_phy_info(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.get_info) ++ return hw->phy.ops.get_info(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_phy_hw_reset - Hard PHY reset ++ * @hw: pointer to the HW structure ++ * ++ * Performs a hard PHY reset. This is a function pointer entry point called ++ * by drivers. ++ **/ ++s32 e1000_phy_hw_reset(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.reset) ++ return hw->phy.ops.reset(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_phy_commit - Soft PHY reset ++ * @hw: pointer to the HW structure ++ * ++ * Performs a soft PHY reset on those that apply. This is a function pointer ++ * entry point called by drivers. ++ **/ ++s32 e1000_phy_commit(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.commit) ++ return hw->phy.ops.commit(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_set_d0_lplu_state - Sets low power link up state for D0 ++ * @hw: pointer to the HW structure ++ * @active: boolean used to enable/disable lplu ++ * ++ * Success returns 0, Failure returns 1 ++ * ++ * The low power link up (lplu) state is set to the power management level D0 ++ * and SmartSpeed is disabled when active is true, else clear lplu for D0 ++ * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU ++ * is used during Dx states where the power conservation is most important. ++ * During driver activity, SmartSpeed should be enabled so performance is ++ * maintained. This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) ++{ ++ if (hw->phy.ops.set_d0_lplu_state) ++ return hw->phy.ops.set_d0_lplu_state(hw, active); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_set_d3_lplu_state - Sets low power link up state for D3 ++ * @hw: pointer to the HW structure ++ * @active: boolean used to enable/disable lplu ++ * ++ * Success returns 0, Failure returns 1 ++ * ++ * The low power link up (lplu) state is set to the power management level D3 ++ * and SmartSpeed is disabled when active is true, else clear lplu for D3 ++ * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU ++ * is used during Dx states where the power conservation is most important. ++ * During driver activity, SmartSpeed should be enabled so performance is ++ * maintained. This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) ++{ ++ if (hw->phy.ops.set_d3_lplu_state) ++ return hw->phy.ops.set_d3_lplu_state(hw, active); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_read_mac_addr - Reads MAC address ++ * @hw: pointer to the HW structure ++ * ++ * Reads the MAC address out of the adapter and stores it in the HW structure. ++ * Currently no func pointer exists and all implementations are handled in the ++ * generic version of this function. ++ **/ ++s32 e1000_read_mac_addr(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.read_mac_addr) ++ return hw->mac.ops.read_mac_addr(hw); ++ ++ return e1000_read_mac_addr_generic(hw); ++} ++ ++/** ++ * e1000_read_pba_num - Read device part number ++ * @hw: pointer to the HW structure ++ * @pba_num: pointer to device part number ++ * ++ * Reads the product board assembly (PBA) number from the EEPROM and stores ++ * the value in pba_num. ++ * Currently no func pointer exists and all implementations are handled in the ++ * generic version of this function. ++ **/ ++s32 e1000_read_pba_num(struct e1000_hw *hw, u32 *pba_num) ++{ ++ return e1000_read_pba_num_generic(hw, pba_num); ++} ++ ++/** ++ * e1000_validate_nvm_checksum - Verifies NVM (EEPROM) checksum ++ * @hw: pointer to the HW structure ++ * ++ * Validates the NVM checksum is correct. This is a function pointer entry ++ * point called by drivers. ++ **/ ++s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) ++{ ++ if (hw->nvm.ops.validate) ++ return hw->nvm.ops.validate(hw); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_update_nvm_checksum - Updates NVM (EEPROM) checksum ++ * @hw: pointer to the HW structure ++ * ++ * Updates the NVM checksum. Currently no func pointer exists and all ++ * implementations are handled in the generic version of this function. ++ **/ ++s32 e1000_update_nvm_checksum(struct e1000_hw *hw) ++{ ++ if (hw->nvm.ops.update) ++ return hw->nvm.ops.update(hw); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_reload_nvm - Reloads EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the ++ * extended control register. ++ **/ ++void e1000_reload_nvm(struct e1000_hw *hw) ++{ ++ if (hw->nvm.ops.reload) ++ hw->nvm.ops.reload(hw); ++} ++ ++/** ++ * e1000_read_nvm - Reads NVM (EEPROM) ++ * @hw: pointer to the HW structure ++ * @offset: the word offset to read ++ * @words: number of 16-bit words to read ++ * @data: pointer to the properly sized buffer for the data. ++ * ++ * Reads 16-bit chunks of data from the NVM (EEPROM). This is a function ++ * pointer entry point called by drivers. ++ **/ ++s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ if (hw->nvm.ops.read) ++ return hw->nvm.ops.read(hw, offset, words, data); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_write_nvm - Writes to NVM (EEPROM) ++ * @hw: pointer to the HW structure ++ * @offset: the word offset to read ++ * @words: number of 16-bit words to write ++ * @data: pointer to the properly sized buffer for the data. ++ * ++ * Writes 16-bit chunks of data to the NVM (EEPROM). This is a function ++ * pointer entry point called by drivers. ++ **/ ++s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ if (hw->nvm.ops.write) ++ return hw->nvm.ops.write(hw, offset, words, data); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_power_up_phy - Restores link in case of PHY power down ++ * @hw: pointer to the HW structure ++ * ++ * The phy may be powered down to save power, to turn off link when the ++ * driver is unloaded, or wake on lan is not enabled (among others). ++ **/ ++void e1000_power_up_phy(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.power_up) ++ hw->phy.ops.power_up(hw); ++ ++ e1000_setup_link(hw); ++} ++ ++/** ++ * e1000_power_down_phy - Power down PHY ++ * @hw: pointer to the HW structure ++ * ++ * The phy may be powered down to save power, to turn off link when the ++ * driver is unloaded, or wake on lan is not enabled (among others). ++ **/ ++void e1000_power_down_phy(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.power_down) ++ hw->phy.ops.power_down(hw); ++} ++ +diff -r b58885ce604a drivers/net/e1000/e1000_api.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_api.h Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,146 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_API_H_ ++#define _E1000_API_H_ ++ ++#include "e1000_hw.h" ++ ++extern void e1000_init_function_pointers_82542(struct e1000_hw *hw); ++extern void e1000_init_function_pointers_82543(struct e1000_hw *hw); ++extern void e1000_init_function_pointers_82540(struct e1000_hw *hw); ++extern void e1000_init_function_pointers_82541(struct e1000_hw *hw); ++ ++s32 e1000_set_mac_type(struct e1000_hw *hw); ++s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device); ++s32 e1000_init_mac_params(struct e1000_hw *hw); ++s32 e1000_init_nvm_params(struct e1000_hw *hw); ++s32 e1000_init_phy_params(struct e1000_hw *hw); ++s32 e1000_get_bus_info(struct e1000_hw *hw); ++void e1000_clear_vfta(struct e1000_hw *hw); ++void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value); ++s32 e1000_force_mac_fc(struct e1000_hw *hw); ++s32 e1000_check_for_link(struct e1000_hw *hw); ++s32 e1000_reset_hw(struct e1000_hw *hw); ++s32 e1000_init_hw(struct e1000_hw *hw); ++s32 e1000_setup_link(struct e1000_hw *hw); ++s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex); ++s32 e1000_disable_pcie_master(struct e1000_hw *hw); ++void e1000_config_collision_dist(struct e1000_hw *hw); ++void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); ++void e1000_mta_set(struct e1000_hw *hw, u32 hash_value); ++u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr); ++void e1000_update_mc_addr_list(struct e1000_hw *hw, ++ u8 *mc_addr_list, u32 mc_addr_count); ++s32 e1000_setup_led(struct e1000_hw *hw); ++s32 e1000_cleanup_led(struct e1000_hw *hw); ++s32 e1000_check_reset_block(struct e1000_hw *hw); ++s32 e1000_blink_led(struct e1000_hw *hw); ++s32 e1000_led_on(struct e1000_hw *hw); ++s32 e1000_led_off(struct e1000_hw *hw); ++s32 e1000_id_led_init(struct e1000_hw *hw); ++void e1000_reset_adaptive(struct e1000_hw *hw); ++void e1000_update_adaptive(struct e1000_hw *hw); ++s32 e1000_get_cable_length(struct e1000_hw *hw); ++s32 e1000_validate_mdi_setting(struct e1000_hw *hw); ++s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_get_phy_info(struct e1000_hw *hw); ++void e1000_release_phy(struct e1000_hw *hw); ++s32 e1000_acquire_phy(struct e1000_hw *hw); ++s32 e1000_phy_hw_reset(struct e1000_hw *hw); ++s32 e1000_phy_commit(struct e1000_hw *hw); ++void e1000_power_up_phy(struct e1000_hw *hw); ++void e1000_power_down_phy(struct e1000_hw *hw); ++s32 e1000_read_mac_addr(struct e1000_hw *hw); ++s32 e1000_read_pba_num(struct e1000_hw *hw, u32 *part_num); ++void e1000_reload_nvm(struct e1000_hw *hw); ++s32 e1000_update_nvm_checksum(struct e1000_hw *hw); ++s32 e1000_validate_nvm_checksum(struct e1000_hw *hw); ++s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); ++s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data); ++s32 e1000_wait_autoneg(struct e1000_hw *hw); ++s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); ++s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); ++bool e1000_check_mng_mode(struct e1000_hw *hw); ++bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); ++s32 e1000_mng_enable_host_if(struct e1000_hw *hw); ++s32 e1000_mng_host_if_write(struct e1000_hw *hw, ++ u8 *buffer, u16 length, u16 offset, u8 *sum); ++s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header *hdr); ++s32 e1000_mng_write_dhcp_info(struct e1000_hw * hw, ++ u8 *buffer, u16 length); ++u32 e1000_translate_register_82542(u32 reg); ++ ++/* ++ * TBI_ACCEPT macro definition: ++ * ++ * This macro requires: ++ * adapter = a pointer to struct e1000_hw ++ * status = the 8 bit status field of the Rx descriptor with EOP set ++ * error = the 8 bit error field of the Rx descriptor with EOP set ++ * length = the sum of all the length fields of the Rx descriptors that ++ * make up the current frame ++ * last_byte = the last byte of the frame DMAed by the hardware ++ * max_frame_length = the maximum frame length we want to accept. ++ * min_frame_length = the minimum frame length we want to accept. ++ * ++ * This macro is a conditional that should be used in the interrupt ++ * handler's Rx processing routine when RxErrors have been detected. ++ * ++ * Typical use: ++ * ... ++ * if (TBI_ACCEPT) { ++ * accept_frame = true; ++ * e1000_tbi_adjust_stats(adapter, MacAddress); ++ * frame_length--; ++ * } else { ++ * accept_frame = false; ++ * } ++ * ... ++ */ ++ ++/* The carrier extension symbol, as received by the NIC. */ ++#define CARRIER_EXTENSION 0x0F ++ ++#define TBI_ACCEPT(a, status, errors, length, last_byte, min_frame_size, max_frame_size) \ ++ (e1000_tbi_sbp_enabled_82543(a) && \ ++ (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ ++ ((last_byte) == CARRIER_EXTENSION) && \ ++ (((status) & E1000_RXD_STAT_VP) ? \ ++ (((length) > (min_frame_size - VLAN_TAG_SIZE)) && \ ++ ((length) <= (max_frame_size + 1))) : \ ++ (((length) > min_frame_size) && \ ++ ((length) <= (max_frame_size + VLAN_TAG_SIZE + 1))))) ++ ++#endif +diff -r b58885ce604a drivers/net/e1000/e1000_defines.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_defines.h Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,1414 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_DEFINES_H_ ++#define _E1000_DEFINES_H_ ++ ++/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ ++#define REQ_TX_DESCRIPTOR_MULTIPLE 8 ++#define REQ_RX_DESCRIPTOR_MULTIPLE 8 ++ ++/* Definitions for power management and wakeup registers */ ++/* Wake Up Control */ ++#define E1000_WUC_APME 0x00000001 /* APM Enable */ ++#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ ++#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ ++#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ ++#define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */ ++#define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */ ++#define E1000_WUC_SPM 0x80000000 /* Enable SPM */ ++#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ ++ ++/* Wake Up Filter Control */ ++#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ ++#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ ++#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ ++#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ ++#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ ++#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ ++#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ ++#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ ++#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ ++#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ ++#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ ++#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ ++#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ ++#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ ++#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ ++#define E1000_WUFC_FLX_FILTERS 0x000F0000 /*Mask for the 4 flexible filters */ ++ ++/* Wake Up Status */ ++#define E1000_WUS_LNKC E1000_WUFC_LNKC ++#define E1000_WUS_MAG E1000_WUFC_MAG ++#define E1000_WUS_EX E1000_WUFC_EX ++#define E1000_WUS_MC E1000_WUFC_MC ++#define E1000_WUS_BC E1000_WUFC_BC ++#define E1000_WUS_ARP E1000_WUFC_ARP ++#define E1000_WUS_IPV4 E1000_WUFC_IPV4 ++#define E1000_WUS_IPV6 E1000_WUFC_IPV6 ++#define E1000_WUS_FLX0 E1000_WUFC_FLX0 ++#define E1000_WUS_FLX1 E1000_WUFC_FLX1 ++#define E1000_WUS_FLX2 E1000_WUFC_FLX2 ++#define E1000_WUS_FLX3 E1000_WUFC_FLX3 ++#define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS ++ ++/* Wake Up Packet Length */ ++#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ ++ ++/* Four Flexible Filters are supported */ ++#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 ++ ++/* Each Flexible Filter is at most 128 (0x80) bytes in length */ ++#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 ++ ++#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX ++#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX ++#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX ++ ++/* Extended Device Control */ ++#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ ++#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ ++#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN ++#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ ++#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ ++/* Reserved (bits 4,5) in >= 82575 */ ++#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */ ++#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */ ++#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA ++#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */ ++#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */ ++/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ ++#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ ++#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ ++#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ ++#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ ++#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ ++#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ ++#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ ++#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ ++#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ ++#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ ++#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 ++#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 ++#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 ++#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 ++#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 ++#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 ++#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 ++#define E1000_CTRL_EXT_EIAME 0x01000000 ++#define E1000_CTRL_EXT_IRCA 0x00000001 ++#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 ++#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 ++#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 ++#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 ++#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 ++#define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */ ++#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ ++/* IAME enable bit (27) was removed in >= 82575 */ ++#define E1000_CTRL_EXT_IAME 0x08000000 /* Int acknowledge Auto-mask */ ++#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error ++ * detection enabled */ ++#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity ++ * error detection enable */ ++#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 ++#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ ++#define E1000_I2CCMD_REG_ADDR_SHIFT 16 ++#define E1000_I2CCMD_REG_ADDR 0x00FF0000 ++#define E1000_I2CCMD_PHY_ADDR_SHIFT 24 ++#define E1000_I2CCMD_PHY_ADDR 0x07000000 ++#define E1000_I2CCMD_OPCODE_READ 0x08000000 ++#define E1000_I2CCMD_OPCODE_WRITE 0x00000000 ++#define E1000_I2CCMD_RESET 0x10000000 ++#define E1000_I2CCMD_READY 0x20000000 ++#define E1000_I2CCMD_INTERRUPT_ENA 0x40000000 ++#define E1000_I2CCMD_ERROR 0x80000000 ++#define E1000_MAX_SGMII_PHY_REG_ADDR 255 ++#define E1000_I2CCMD_PHY_TIMEOUT 200 ++ ++/* Receive Descriptor bit definitions */ ++#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ ++#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ ++#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ ++#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ ++#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ ++#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ ++#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ ++#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ ++#define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ ++#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ ++#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ ++#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ ++#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ ++#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ ++#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ ++#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ ++#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ ++#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ ++#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ ++#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ ++#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ ++#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ ++#define E1000_RXD_SPC_PRI_SHIFT 13 ++#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ ++#define E1000_RXD_SPC_CFI_SHIFT 12 ++ ++#define E1000_RXDEXT_STATERR_CE 0x01000000 ++#define E1000_RXDEXT_STATERR_SE 0x02000000 ++#define E1000_RXDEXT_STATERR_SEQ 0x04000000 ++#define E1000_RXDEXT_STATERR_CXE 0x10000000 ++#define E1000_RXDEXT_STATERR_TCPE 0x20000000 ++#define E1000_RXDEXT_STATERR_IPE 0x40000000 ++#define E1000_RXDEXT_STATERR_RXE 0x80000000 ++ ++/* mask to determine if packets should be dropped due to frame errors */ ++#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ ++ E1000_RXD_ERR_CE | \ ++ E1000_RXD_ERR_SE | \ ++ E1000_RXD_ERR_SEQ | \ ++ E1000_RXD_ERR_CXE | \ ++ E1000_RXD_ERR_RXE) ++ ++/* Same mask, but for extended and packet split descriptors */ ++#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ ++ E1000_RXDEXT_STATERR_CE | \ ++ E1000_RXDEXT_STATERR_SE | \ ++ E1000_RXDEXT_STATERR_SEQ | \ ++ E1000_RXDEXT_STATERR_CXE | \ ++ E1000_RXDEXT_STATERR_RXE) ++ ++#define E1000_MRQC_ENABLE_MASK 0x00000007 ++#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 ++#define E1000_MRQC_ENABLE_RSS_INT 0x00000004 ++#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 ++#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 ++#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 ++#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 ++#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 ++#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 ++#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 ++ ++#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 ++#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF ++ ++/* Management Control */ ++#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ ++#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ ++#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ ++#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ ++#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ ++#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ ++#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ ++#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ ++#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ ++/* Enable Neighbor Discovery Filtering */ ++#define E1000_MANC_NEIGHBOR_EN 0x00004000 ++#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ ++#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ ++#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ ++#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ ++#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ ++#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ ++/* Enable MAC address filtering */ ++#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 ++/* Enable MNG packets to host memory */ ++#define E1000_MANC_EN_MNG2HOST 0x00200000 ++/* Enable IP address filtering */ ++#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 ++#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ ++#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ ++#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ ++#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ ++#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ ++#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ ++#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ ++#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ ++ ++#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ ++#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ ++ ++/* Receive Control */ ++#define E1000_RCTL_RST 0x00000001 /* Software reset */ ++#define E1000_RCTL_EN 0x00000002 /* enable */ ++#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ ++#define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ ++#define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ ++#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ ++#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ ++#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ ++#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ ++#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ ++#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ ++#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ ++#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min thresh size */ ++#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min thresh size */ ++#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min thresh size */ ++#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ ++#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ ++#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ ++#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ ++#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ ++#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ ++#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ ++/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ ++#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ ++#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ ++#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ ++#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ ++/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ ++#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ ++#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ ++#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ ++#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ ++#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ ++#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ ++#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ ++#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ ++#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ ++#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ ++#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ ++#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ ++ ++/* ++ * Use byte values for the following shift parameters ++ * Usage: ++ * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & ++ * E1000_PSRCTL_BSIZE0_MASK) | ++ * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & ++ * E1000_PSRCTL_BSIZE1_MASK) | ++ * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & ++ * E1000_PSRCTL_BSIZE2_MASK) | ++ * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; ++ * E1000_PSRCTL_BSIZE3_MASK)) ++ * where value0 = [128..16256], default=256 ++ * value1 = [1024..64512], default=4096 ++ * value2 = [0..64512], default=4096 ++ * value3 = [0..64512], default=0 ++ */ ++ ++#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F ++#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 ++#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 ++#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 ++ ++#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ ++#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ ++#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ ++#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ ++ ++/* SWFW_SYNC Definitions */ ++#define E1000_SWFW_EEP_SM 0x01 ++#define E1000_SWFW_PHY0_SM 0x02 ++#define E1000_SWFW_PHY1_SM 0x04 ++#define E1000_SWFW_CSR_SM 0x08 ++ ++/* FACTPS Definitions */ ++#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */ ++/* Device Control */ ++#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ ++#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ ++#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ ++#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ ++#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ ++#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ ++#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ ++#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ ++#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ ++#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ ++#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ ++#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ ++#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ ++#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ ++#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ ++#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ ++#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ ++#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ ++#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock ++ * indication in SDP[0] */ ++#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through ++ * PHYRST_N pin */ ++#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external ++ * LINK_0 and LINK_1 pins */ ++#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ ++#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ ++#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ ++#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ ++#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ ++#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ ++#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ ++#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ ++#define E1000_CTRL_RST 0x04000000 /* Global reset */ ++#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ ++#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ ++#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ ++#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ ++#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ ++#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */ ++#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ ++ ++/* ++ * Bit definitions for the Management Data IO (MDIO) and Management Data ++ * Clock (MDC) pins in the Device Control Register. ++ */ ++#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 ++#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 ++#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 ++#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 ++#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 ++#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 ++#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR ++#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA ++ ++#define E1000_CONNSW_ENRGSRC 0x4 ++#define E1000_PCS_CFG_PCS_EN 8 ++#define E1000_PCS_LCTL_FLV_LINK_UP 1 ++#define E1000_PCS_LCTL_FSV_10 0 ++#define E1000_PCS_LCTL_FSV_100 2 ++#define E1000_PCS_LCTL_FSV_1000 4 ++#define E1000_PCS_LCTL_FDV_FULL 8 ++#define E1000_PCS_LCTL_FSD 0x10 ++#define E1000_PCS_LCTL_FORCE_LINK 0x20 ++#define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40 ++#define E1000_PCS_LCTL_FORCE_FCTRL 0x80 ++#define E1000_PCS_LCTL_AN_ENABLE 0x10000 ++#define E1000_PCS_LCTL_AN_RESTART 0x20000 ++#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 ++#define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 ++#define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 ++#define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 ++#define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000 ++#define E1000_PCS_LCTL_CRS_ON_NI 0x4000000 ++#define E1000_ENABLE_SERDES_LOOPBACK 0x0410 ++ ++#define E1000_PCS_LSTS_LINK_OK 1 ++#define E1000_PCS_LSTS_SPEED_10 0 ++#define E1000_PCS_LSTS_SPEED_100 2 ++#define E1000_PCS_LSTS_SPEED_1000 4 ++#define E1000_PCS_LSTS_DUPLEX_FULL 8 ++#define E1000_PCS_LSTS_SYNK_OK 0x10 ++#define E1000_PCS_LSTS_AN_COMPLETE 0x10000 ++#define E1000_PCS_LSTS_AN_PAGE_RX 0x20000 ++#define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000 ++#define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 ++#define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000 ++ ++/* Device Status */ ++#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ ++#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ ++#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ ++#define E1000_STATUS_FUNC_SHIFT 2 ++#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ ++#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ ++#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ ++#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ ++#define E1000_STATUS_SPEED_MASK 0x000000C0 ++#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ ++#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ ++#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ ++#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ ++#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ ++#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ ++#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. ++ * Clear on write '0'. */ ++#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ ++#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ ++#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ ++#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ ++#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ ++#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ ++#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ ++#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ ++#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ ++#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ ++#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution ++ * disabled */ ++#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ ++#define E1000_STATUS_FUSE_8 0x04000000 ++#define E1000_STATUS_FUSE_9 0x08000000 ++#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ ++#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ ++ ++/* Constants used to interpret the masked PCI-X bus speed. */ ++#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ ++#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ ++#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/ ++ ++#define SPEED_10 10 ++#define SPEED_100 100 ++#define SPEED_1000 1000 ++#define HALF_DUPLEX 1 ++#define FULL_DUPLEX 2 ++ ++#define PHY_FORCE_TIME 20 ++ ++#define ADVERTISE_10_HALF 0x0001 ++#define ADVERTISE_10_FULL 0x0002 ++#define ADVERTISE_100_HALF 0x0004 ++#define ADVERTISE_100_FULL 0x0008 ++#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ ++#define ADVERTISE_1000_FULL 0x0020 ++ ++/* 1000/H is not supported, nor spec-compliant. */ ++#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ++ ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ ++ ADVERTISE_1000_FULL) ++#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ++ ADVERTISE_100_HALF | ADVERTISE_100_FULL) ++#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) ++#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) ++#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ ++ ADVERTISE_1000_FULL) ++#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) ++ ++#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX ++ ++/* LED Control */ ++#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F ++#define E1000_LEDCTL_LED0_MODE_SHIFT 0 ++#define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020 ++#define E1000_LEDCTL_LED0_IVRT 0x00000040 ++#define E1000_LEDCTL_LED0_BLINK 0x00000080 ++#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 ++#define E1000_LEDCTL_LED1_MODE_SHIFT 8 ++#define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000 ++#define E1000_LEDCTL_LED1_IVRT 0x00004000 ++#define E1000_LEDCTL_LED1_BLINK 0x00008000 ++#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 ++#define E1000_LEDCTL_LED2_MODE_SHIFT 16 ++#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 ++#define E1000_LEDCTL_LED2_IVRT 0x00400000 ++#define E1000_LEDCTL_LED2_BLINK 0x00800000 ++#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 ++#define E1000_LEDCTL_LED3_MODE_SHIFT 24 ++#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 ++#define E1000_LEDCTL_LED3_IVRT 0x40000000 ++#define E1000_LEDCTL_LED3_BLINK 0x80000000 ++ ++#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 ++#define E1000_LEDCTL_MODE_LINK_100_1000 0x1 ++#define E1000_LEDCTL_MODE_LINK_UP 0x2 ++#define E1000_LEDCTL_MODE_ACTIVITY 0x3 ++#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 ++#define E1000_LEDCTL_MODE_LINK_10 0x5 ++#define E1000_LEDCTL_MODE_LINK_100 0x6 ++#define E1000_LEDCTL_MODE_LINK_1000 0x7 ++#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 ++#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 ++#define E1000_LEDCTL_MODE_COLLISION 0xA ++#define E1000_LEDCTL_MODE_BUS_SPEED 0xB ++#define E1000_LEDCTL_MODE_BUS_SIZE 0xC ++#define E1000_LEDCTL_MODE_PAUSED 0xD ++#define E1000_LEDCTL_MODE_LED_ON 0xE ++#define E1000_LEDCTL_MODE_LED_OFF 0xF ++ ++/* Transmit Descriptor bit definitions */ ++#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ ++#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ ++#define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */ ++#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ ++#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ ++#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ ++#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ ++#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ ++#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ ++#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ ++#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ ++#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ ++#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ ++#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ ++#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ ++#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ ++#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ ++#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ ++#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ ++#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ ++#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ ++/* Extended desc bits for Linksec and timesync */ ++ ++/* Transmit Control */ ++#define E1000_TCTL_RST 0x00000001 /* software reset */ ++#define E1000_TCTL_EN 0x00000002 /* enable tx */ ++#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ ++#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ ++#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ ++#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ ++#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ ++#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ ++#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ ++#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ ++#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ ++ ++/* Transmit Arbitration Count */ ++#define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ ++ ++/* SerDes Control */ ++#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 ++ ++/* Receive Checksum Control */ ++#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ ++#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ ++#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ ++#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ ++#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ ++#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ ++#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ ++ ++/* Header split receive */ ++#define E1000_RFCTL_ISCSI_DIS 0x00000001 ++#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E ++#define E1000_RFCTL_ISCSI_DWC_SHIFT 1 ++#define E1000_RFCTL_NFSW_DIS 0x00000040 ++#define E1000_RFCTL_NFSR_DIS 0x00000080 ++#define E1000_RFCTL_NFS_VER_MASK 0x00000300 ++#define E1000_RFCTL_NFS_VER_SHIFT 8 ++#define E1000_RFCTL_IPV6_DIS 0x00000400 ++#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 ++#define E1000_RFCTL_ACK_DIS 0x00001000 ++#define E1000_RFCTL_ACKD_DIS 0x00002000 ++#define E1000_RFCTL_IPFRSP_DIS 0x00004000 ++#define E1000_RFCTL_EXTEN 0x00008000 ++#define E1000_RFCTL_IPV6_EX_DIS 0x00010000 ++#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 ++#define E1000_RFCTL_LEF 0x00040000 ++ ++/* Collision related configuration parameters */ ++#define E1000_COLLISION_THRESHOLD 15 ++#define E1000_CT_SHIFT 4 ++#define E1000_COLLISION_DISTANCE 63 ++#define E1000_COLD_SHIFT 12 ++ ++/* Default values for the transmit IPG register */ ++#define DEFAULT_82542_TIPG_IPGT 10 ++#define DEFAULT_82543_TIPG_IPGT_FIBER 9 ++#define DEFAULT_82543_TIPG_IPGT_COPPER 8 ++ ++#define E1000_TIPG_IPGT_MASK 0x000003FF ++#define E1000_TIPG_IPGR1_MASK 0x000FFC00 ++#define E1000_TIPG_IPGR2_MASK 0x3FF00000 ++ ++#define DEFAULT_82542_TIPG_IPGR1 2 ++#define DEFAULT_82543_TIPG_IPGR1 8 ++#define E1000_TIPG_IPGR1_SHIFT 10 ++ ++#define DEFAULT_82542_TIPG_IPGR2 10 ++#define DEFAULT_82543_TIPG_IPGR2 6 ++#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 ++#define E1000_TIPG_IPGR2_SHIFT 20 ++ ++/* Ethertype field values */ ++#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ ++ ++#define ETHERNET_FCS_SIZE 4 ++#define MAX_JUMBO_FRAME_SIZE 0x3F00 ++ ++/* Extended Configuration Control and Size */ ++#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 ++#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 ++#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 ++#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 ++#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 ++#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 ++#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 ++ ++#define E1000_PHY_CTRL_SPD_EN 0x00000001 ++#define E1000_PHY_CTRL_D0A_LPLU 0x00000002 ++#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 ++#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 ++#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 ++ ++#define E1000_KABGTXD_BGSQLBIAS 0x00050000 ++ ++/* PBA constants */ ++#define E1000_PBA_6K 0x0006 /* 6KB */ ++#define E1000_PBA_8K 0x0008 /* 8KB */ ++#define E1000_PBA_10K 0x000A /* 10KB */ ++#define E1000_PBA_12K 0x000C /* 12KB */ ++#define E1000_PBA_14K 0x000E /* 14KB */ ++#define E1000_PBA_16K 0x0010 /* 16KB */ ++#define E1000_PBA_18K 0x0012 ++#define E1000_PBA_20K 0x0014 ++#define E1000_PBA_22K 0x0016 ++#define E1000_PBA_24K 0x0018 ++#define E1000_PBA_26K 0x001A ++#define E1000_PBA_30K 0x001E ++#define E1000_PBA_32K 0x0020 ++#define E1000_PBA_34K 0x0022 ++#define E1000_PBA_35K 0x0023 ++#define E1000_PBA_38K 0x0026 ++#define E1000_PBA_40K 0x0028 ++#define E1000_PBA_48K 0x0030 /* 48KB */ ++#define E1000_PBA_64K 0x0040 /* 64KB */ ++ ++#define E1000_PBS_16K E1000_PBA_16K ++#define E1000_PBS_24K E1000_PBA_24K ++ ++#define IFS_MAX 80 ++#define IFS_MIN 40 ++#define IFS_RATIO 4 ++#define IFS_STEP 10 ++#define MIN_NUM_XMITS 1000 ++ ++/* SW Semaphore Register */ ++#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ ++#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ ++#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ ++#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ ++ ++#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ ++ ++/* Interrupt Cause Read */ ++#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ ++#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ ++#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ ++#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ ++#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ ++#define E1000_ICR_RXO 0x00000040 /* rx overrun */ ++#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ ++#define E1000_ICR_VMMB 0x00000100 /* VM MB event */ ++#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ ++#define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ ++#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ ++#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ ++#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ ++#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ ++#define E1000_ICR_TXD_LOW 0x00008000 ++#define E1000_ICR_SRPD 0x00010000 ++#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ ++#define E1000_ICR_MNG 0x00040000 /* Manageability event */ ++#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ ++#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver ++ * should claim the interrupt */ ++#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */ ++#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */ ++#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */ ++#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ ++#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */ ++#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */ ++#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ ++#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW ++ * bit in the FWSM */ ++#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates ++ * an interrupt */ ++#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ ++#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ ++ ++ ++/* ++ * This defines the bits that are set in the Interrupt Mask ++ * Set/Read Register. Each bit is documented below: ++ * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) ++ * o RXSEQ = Receive Sequence Error ++ */ ++#define POLL_IMS_ENABLE_MASK ( \ ++ E1000_IMS_RXDMT0 | \ ++ E1000_IMS_RXSEQ) ++ ++/* ++ * This defines the bits that are set in the Interrupt Mask ++ * Set/Read Register. Each bit is documented below: ++ * o RXT0 = Receiver Timer Interrupt (ring 0) ++ * o TXDW = Transmit Descriptor Written Back ++ * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) ++ * o RXSEQ = Receive Sequence Error ++ * o LSC = Link Status Change ++ */ ++#define IMS_ENABLE_MASK ( \ ++ E1000_IMS_RXT0 | \ ++ E1000_IMS_TXDW | \ ++ E1000_IMS_RXDMT0 | \ ++ E1000_IMS_RXSEQ | \ ++ E1000_IMS_LSC) ++ ++/* Interrupt Mask Set */ ++#define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */ ++#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ ++#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ ++#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ ++#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ ++#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ ++#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ ++#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ ++#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ ++#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ ++#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ ++#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ ++#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ ++#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ ++#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW ++#define E1000_IMS_SRPD E1000_ICR_SRPD ++#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ ++#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ ++#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ ++#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO ++ * parity error */ ++#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO ++ * parity error */ ++#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer ++ * parity error */ ++#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity ++ * error */ ++#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO ++ * parity error */ ++#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO ++ * parity error */ ++#define E1000_IMS_DSW E1000_ICR_DSW ++#define E1000_IMS_PHYINT E1000_ICR_PHYINT ++#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ ++#define E1000_IMS_EPRST E1000_ICR_EPRST ++ ++/* Interrupt Cause Set */ ++#define E1000_ICS_TXDW E1000_ICR_TXDW /* Tx desc written back */ ++#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ ++#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ ++#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ ++#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ ++#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ ++#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ ++#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ ++#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ ++#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ ++#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ ++#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ ++#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ ++#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW ++#define E1000_ICS_SRPD E1000_ICR_SRPD ++#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ ++#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ ++#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ ++#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO ++ * parity error */ ++#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO ++ * parity error */ ++#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer ++ * parity error */ ++#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity ++ * error */ ++#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO ++ * parity error */ ++#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO ++ * parity error */ ++#define E1000_ICS_DSW E1000_ICR_DSW ++#define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ ++#define E1000_ICS_PHYINT E1000_ICR_PHYINT ++#define E1000_ICS_EPRST E1000_ICR_EPRST ++ ++/* Transmit Descriptor Control */ ++#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ ++#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ ++#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ ++#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ ++#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ ++#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ ++#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ ++/* Enable the counting of descriptors still to be processed. */ ++#define E1000_TXDCTL_COUNT_DESC 0x00400000 ++ ++/* Flow Control Constants */ ++#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 ++#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 ++#define FLOW_CONTROL_TYPE 0x8808 ++ ++/* 802.1q VLAN Packet Size */ ++#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ ++#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ ++ ++/* Receive Address */ ++/* ++ * Number of high/low register pairs in the RAR. The RAR (Receive Address ++ * Registers) holds the directed and multicast addresses that we monitor. ++ * Technically, we have 16 spots. However, we reserve one of these spots ++ * (RAR[15]) for our directed address used by controllers with ++ * manageability enabled, allowing us room for 15 multicast addresses. ++ */ ++#define E1000_RAR_ENTRIES 15 ++#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ ++#define E1000_RAL_MAC_ADDR_LEN 4 ++#define E1000_RAH_MAC_ADDR_LEN 2 ++#define E1000_RAH_POOL_MASK 0x03FC0000 ++#define E1000_RAH_POOL_1 0x00040000 ++ ++/* Error Codes */ ++#define E1000_SUCCESS 0 ++#define E1000_ERR_NVM 1 ++#define E1000_ERR_PHY 2 ++#define E1000_ERR_CONFIG 3 ++#define E1000_ERR_PARAM 4 ++#define E1000_ERR_MAC_INIT 5 ++#define E1000_ERR_PHY_TYPE 6 ++#define E1000_ERR_RESET 9 ++#define E1000_ERR_MASTER_REQUESTS_PENDING 10 ++#define E1000_ERR_HOST_INTERFACE_COMMAND 11 ++#define E1000_BLK_PHY_RESET 12 ++#define E1000_ERR_SWFW_SYNC 13 ++#define E1000_NOT_IMPLEMENTED 14 ++#define E1000_ERR_MBX 15 ++ ++/* Loop limit on how long we wait for auto-negotiation to complete */ ++#define FIBER_LINK_UP_LIMIT 50 ++#define COPPER_LINK_UP_LIMIT 10 ++#define PHY_AUTO_NEG_LIMIT 45 ++#define PHY_FORCE_LIMIT 20 ++/* Number of 100 microseconds we wait for PCI Express master disable */ ++#define MASTER_DISABLE_TIMEOUT 800 ++/* Number of milliseconds we wait for PHY configuration done after MAC reset */ ++#define PHY_CFG_TIMEOUT 100 ++/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ ++#define MDIO_OWNERSHIP_TIMEOUT 10 ++/* Number of milliseconds for NVM auto read done after MAC reset. */ ++#define AUTO_READ_DONE_TIMEOUT 10 ++ ++/* Flow Control */ ++#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ ++#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ ++#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ ++#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ ++ ++/* Transmit Configuration Word */ ++#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ ++#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ ++#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ ++#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ ++#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ ++#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ ++#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ ++#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ ++#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ ++#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ ++ ++/* Receive Configuration Word */ ++#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ ++#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ ++#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ ++#define E1000_RXCW_CC 0x10000000 /* Receive config change */ ++#define E1000_RXCW_C 0x20000000 /* Receive config */ ++#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ ++#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ ++ ++ ++/* PCI Express Control */ ++#define E1000_GCR_RXD_NO_SNOOP 0x00000001 ++#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 ++#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 ++#define E1000_GCR_TXD_NO_SNOOP 0x00000008 ++#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 ++#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 ++#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 ++#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 ++#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 ++#define E1000_GCR_CAP_VER2 0x00040000 ++ ++#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ ++ E1000_GCR_RXDSCW_NO_SNOOP | \ ++ E1000_GCR_RXDSCR_NO_SNOOP | \ ++ E1000_GCR_TXD_NO_SNOOP | \ ++ E1000_GCR_TXDSCW_NO_SNOOP | \ ++ E1000_GCR_TXDSCR_NO_SNOOP) ++ ++/* PHY Control Register */ ++#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ ++#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ ++#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ ++#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ ++#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ ++#define MII_CR_POWER_DOWN 0x0800 /* Power down */ ++#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ ++#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ ++#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ ++#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ ++#define MII_CR_SPEED_1000 0x0040 ++#define MII_CR_SPEED_100 0x2000 ++#define MII_CR_SPEED_10 0x0000 ++ ++/* PHY Status Register */ ++#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ ++#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ ++#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ ++#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ ++#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ ++#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ ++#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ ++#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ ++#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ ++#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ ++#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ ++#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ ++#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ ++#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ ++#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ ++ ++/* Autoneg Advertisement Register */ ++#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ ++#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ ++#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ ++#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ ++#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ ++#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ ++#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ ++#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ ++#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ ++#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ ++ ++/* Link Partner Ability Register (Base Page) */ ++#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ ++#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ ++#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ ++#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ ++#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ ++#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ ++#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ ++#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ ++#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ ++#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ ++#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ ++ ++/* Autoneg Expansion Register */ ++#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ ++#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ ++#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ ++#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ ++#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ ++ ++/* 1000BASE-T Control Register */ ++#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ ++#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ ++#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ ++#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ ++ /* 0=DTE device */ ++#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ ++ /* 0=Configure PHY as Slave */ ++#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ ++ /* 0=Automatic Master/Slave config */ ++#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ ++#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ ++#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ ++#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ ++#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ ++ ++/* 1000BASE-T Status Register */ ++#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ ++#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ ++#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ ++#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ ++#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ ++#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ ++#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx is Master, 0=Slave */ ++#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ ++ ++#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 ++ ++/* PHY 1000 MII Register/Bit Definitions */ ++/* PHY Registers defined by IEEE */ ++#define PHY_CONTROL 0x00 /* Control Register */ ++#define PHY_STATUS 0x01 /* Status Register */ ++#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ ++#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ ++#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ ++#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ ++#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ ++#define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ ++#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ ++#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ ++#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ ++#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ ++ ++#define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ ++ ++/* NVM Control */ ++#define E1000_EECD_SK 0x00000001 /* NVM Clock */ ++#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ ++#define E1000_EECD_DI 0x00000004 /* NVM Data In */ ++#define E1000_EECD_DO 0x00000008 /* NVM Data Out */ ++#define E1000_EECD_FWE_MASK 0x00000030 ++#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ ++#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ ++#define E1000_EECD_FWE_SHIFT 4 ++#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ ++#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ ++#define E1000_EECD_PRES 0x00000100 /* NVM Present */ ++#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ ++/* NVM Addressing bits based on type 0=small, 1=large */ ++#define E1000_EECD_ADDR_BITS 0x00000400 ++#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ ++#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ ++#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ ++#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ ++#define E1000_EECD_SIZE_EX_SHIFT 11 ++#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ ++#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ ++#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ ++#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ ++#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ ++#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ ++#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ ++#define E1000_EECD_SECVAL_SHIFT 22 ++#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) ++ ++#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */ ++#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */ ++#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ ++#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ ++#define E1000_NVM_RW_REG_START 1 /* Start operation */ ++#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ ++#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ ++#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ ++#define E1000_FLASH_UPDATES 2000 ++ ++/* NVM Word Offsets */ ++#define NVM_COMPAT 0x0003 ++#define NVM_ID_LED_SETTINGS 0x0004 ++#define NVM_VERSION 0x0005 ++#define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ ++#define NVM_PHY_CLASS_WORD 0x0007 ++#define NVM_INIT_CONTROL1_REG 0x000A ++#define NVM_INIT_CONTROL2_REG 0x000F ++#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 ++#define NVM_INIT_CONTROL3_PORT_B 0x0014 ++#define NVM_INIT_3GIO_3 0x001A ++#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 ++#define NVM_INIT_CONTROL3_PORT_A 0x0024 ++#define NVM_CFG 0x0012 ++#define NVM_FLASH_VERSION 0x0032 ++#define NVM_ALT_MAC_ADDR_PTR 0x0037 ++#define NVM_CHECKSUM_REG 0x003F ++ ++#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ ++#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ ++ ++/* Mask bits for fields in Word 0x0f of the NVM */ ++#define NVM_WORD0F_PAUSE_MASK 0x3000 ++#define NVM_WORD0F_PAUSE 0x1000 ++#define NVM_WORD0F_ASM_DIR 0x2000 ++#define NVM_WORD0F_ANE 0x0800 ++#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 ++#define NVM_WORD0F_LPLU 0x0001 ++ ++/* Mask bits for fields in Word 0x1a of the NVM */ ++#define NVM_WORD1A_ASPM_MASK 0x000C ++ ++/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ ++#define NVM_SUM 0xBABA ++ ++#define NVM_MAC_ADDR_OFFSET 0 ++#define NVM_PBA_OFFSET_0 8 ++#define NVM_PBA_OFFSET_1 9 ++#define NVM_RESERVED_WORD 0xFFFF ++#define NVM_PHY_CLASS_A 0x8000 ++#define NVM_SERDES_AMPLITUDE_MASK 0x000F ++#define NVM_SIZE_MASK 0x1C00 ++#define NVM_SIZE_SHIFT 10 ++#define NVM_WORD_SIZE_BASE_SHIFT 6 ++#define NVM_SWDPIO_EXT_SHIFT 4 ++ ++/* NVM Commands - Microwire */ ++#define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ ++#define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ ++#define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ ++#define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ ++#define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */ ++ ++/* NVM Commands - SPI */ ++#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ ++#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ ++#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ ++#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ ++#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ ++#define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */ ++#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ ++#define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */ ++ ++/* SPI NVM Status Register */ ++#define NVM_STATUS_RDY_SPI 0x01 ++#define NVM_STATUS_WEN_SPI 0x02 ++#define NVM_STATUS_BP0_SPI 0x04 ++#define NVM_STATUS_BP1_SPI 0x08 ++#define NVM_STATUS_WPEN_SPI 0x80 ++ ++/* Word definitions for ID LED Settings */ ++#define ID_LED_RESERVED_0000 0x0000 ++#define ID_LED_RESERVED_FFFF 0xFFFF ++#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ ++ (ID_LED_OFF1_OFF2 << 8) | \ ++ (ID_LED_DEF1_DEF2 << 4) | \ ++ (ID_LED_DEF1_DEF2)) ++#define ID_LED_DEF1_DEF2 0x1 ++#define ID_LED_DEF1_ON2 0x2 ++#define ID_LED_DEF1_OFF2 0x3 ++#define ID_LED_ON1_DEF2 0x4 ++#define ID_LED_ON1_ON2 0x5 ++#define ID_LED_ON1_OFF2 0x6 ++#define ID_LED_OFF1_DEF2 0x7 ++#define ID_LED_OFF1_ON2 0x8 ++#define ID_LED_OFF1_OFF2 0x9 ++ ++#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF ++#define IGP_ACTIVITY_LED_ENABLE 0x0300 ++#define IGP_LED3_MODE 0x07000000 ++ ++/* PCI/PCI-X/PCI-EX Config space */ ++#define PCIX_COMMAND_REGISTER 0xE6 ++#define PCIX_STATUS_REGISTER_LO 0xE8 ++#define PCIX_STATUS_REGISTER_HI 0xEA ++#define PCI_HEADER_TYPE_REGISTER 0x0E ++#define PCIE_LINK_STATUS 0x12 ++#define PCIE_DEVICE_CONTROL2 0x28 ++ ++#define PCIX_COMMAND_MMRBC_MASK 0x000C ++#define PCIX_COMMAND_MMRBC_SHIFT 0x2 ++#define PCIX_STATUS_HI_MMRBC_MASK 0x0060 ++#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 ++#define PCIX_STATUS_HI_MMRBC_4K 0x3 ++#define PCIX_STATUS_HI_MMRBC_2K 0x2 ++#define PCIX_STATUS_LO_FUNC_MASK 0x7 ++#define PCI_HEADER_TYPE_MULTIFUNC 0x80 ++#define PCIE_LINK_WIDTH_MASK 0x3F0 ++#define PCIE_LINK_WIDTH_SHIFT 4 ++#define PCIE_DEVICE_CONTROL2_16ms 0x0005 ++ ++#ifndef ETH_ADDR_LEN ++#define ETH_ADDR_LEN 6 ++#endif ++ ++#define PHY_REVISION_MASK 0xFFFFFFF0 ++#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ ++#define MAX_PHY_MULTI_PAGE_REG 0xF ++ ++/* Bit definitions for valid PHY IDs. */ ++/* ++ * I = Integrated ++ * E = External ++ */ ++#define M88E1000_E_PHY_ID 0x01410C50 ++#define M88E1000_I_PHY_ID 0x01410C30 ++#define M88E1011_I_PHY_ID 0x01410C20 ++#define IGP01E1000_I_PHY_ID 0x02A80380 ++#define M88E1011_I_REV_4 0x04 ++#define M88E1111_I_PHY_ID 0x01410CC0 ++#define GG82563_E_PHY_ID 0x01410CA0 ++#define IGP03E1000_E_PHY_ID 0x02A80390 ++#define IFE_E_PHY_ID 0x02A80330 ++#define IFE_PLUS_E_PHY_ID 0x02A80320 ++#define IFE_C_E_PHY_ID 0x02A80310 ++#define M88_VENDOR 0x0141 ++ ++/* M88E1000 Specific Registers */ ++#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ ++#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ ++#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ ++#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ ++#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ ++#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ ++ ++#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ ++#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ ++#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ ++#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ ++#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ ++ ++/* M88E1000 PHY Specific Control Register */ ++#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ ++#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ ++#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ ++/* 1=CLK125 low, 0=CLK125 toggling */ ++#define M88E1000_PSCR_CLK125_DISABLE 0x0010 ++#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ ++ /* Manual MDI configuration */ ++#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ ++/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ ++#define M88E1000_PSCR_AUTO_X_1000T 0x0040 ++/* Auto crossover enabled all speeds */ ++#define M88E1000_PSCR_AUTO_X_MODE 0x0060 ++/* ++ * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold ++ * 0=Normal 10BASE-T Rx Threshold ++ */ ++#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 ++/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ ++#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 ++#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ ++#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ ++#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ ++ ++/* M88E1000 PHY Specific Status Register */ ++#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ ++#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ ++#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ ++#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ ++/* ++ * 0 = <50M ++ * 1 = 50-80M ++ * 2 = 80-110M ++ * 3 = 110-140M ++ * 4 = >140M ++ */ ++#define M88E1000_PSSR_CABLE_LENGTH 0x0380 ++#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ ++#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ ++#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ ++#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ ++#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ ++#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ ++#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ ++#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ ++ ++#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 ++ ++/* M88E1000 Extended PHY Specific Control Register */ ++#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ ++/* ++ * 1 = Lost lock detect enabled. ++ * Will assert lost lock and bring ++ * link down if idle not seen ++ * within 1ms in 1000BASE-T ++ */ ++#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 ++/* ++ * Number of times we will attempt to autonegotiate before downshifting if we ++ * are the master ++ */ ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 ++/* ++ * Number of times we will attempt to autonegotiate before downshifting if we ++ * are the slave ++ */ ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 ++#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ ++#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ ++#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ ++ ++/* M88EC018 Rev 2 specific DownShift settings */ ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 ++ ++/* ++ * Bits... ++ * 15-5: page ++ * 4-0: register offset ++ */ ++#define GG82563_PAGE_SHIFT 5 ++#define GG82563_REG(page, reg) \ ++ (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) ++#define GG82563_MIN_ALT_REG 30 ++ ++/* GG82563 Specific Registers */ ++#define GG82563_PHY_SPEC_CTRL \ ++ GG82563_REG(0, 16) /* PHY Specific Control */ ++#define GG82563_PHY_SPEC_STATUS \ ++ GG82563_REG(0, 17) /* PHY Specific Status */ ++#define GG82563_PHY_INT_ENABLE \ ++ GG82563_REG(0, 18) /* Interrupt Enable */ ++#define GG82563_PHY_SPEC_STATUS_2 \ ++ GG82563_REG(0, 19) /* PHY Specific Status 2 */ ++#define GG82563_PHY_RX_ERR_CNTR \ ++ GG82563_REG(0, 21) /* Receive Error Counter */ ++#define GG82563_PHY_PAGE_SELECT \ ++ GG82563_REG(0, 22) /* Page Select */ ++#define GG82563_PHY_SPEC_CTRL_2 \ ++ GG82563_REG(0, 26) /* PHY Specific Control 2 */ ++#define GG82563_PHY_PAGE_SELECT_ALT \ ++ GG82563_REG(0, 29) /* Alternate Page Select */ ++#define GG82563_PHY_TEST_CLK_CTRL \ ++ GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ ++ ++#define GG82563_PHY_MAC_SPEC_CTRL \ ++ GG82563_REG(2, 21) /* MAC Specific Control Register */ ++#define GG82563_PHY_MAC_SPEC_CTRL_2 \ ++ GG82563_REG(2, 26) /* MAC Specific Control 2 */ ++ ++#define GG82563_PHY_DSP_DISTANCE \ ++ GG82563_REG(5, 26) /* DSP Distance */ ++ ++/* Page 193 - Port Control Registers */ ++#define GG82563_PHY_KMRN_MODE_CTRL \ ++ GG82563_REG(193, 16) /* Kumeran Mode Control */ ++#define GG82563_PHY_PORT_RESET \ ++ GG82563_REG(193, 17) /* Port Reset */ ++#define GG82563_PHY_REVISION_ID \ ++ GG82563_REG(193, 18) /* Revision ID */ ++#define GG82563_PHY_DEVICE_ID \ ++ GG82563_REG(193, 19) /* Device ID */ ++#define GG82563_PHY_PWR_MGMT_CTRL \ ++ GG82563_REG(193, 20) /* Power Management Control */ ++#define GG82563_PHY_RATE_ADAPT_CTRL \ ++ GG82563_REG(193, 25) /* Rate Adaptation Control */ ++ ++/* Page 194 - KMRN Registers */ ++#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ ++ GG82563_REG(194, 16) /* FIFO's Control/Status */ ++#define GG82563_PHY_KMRN_CTRL \ ++ GG82563_REG(194, 17) /* Control */ ++#define GG82563_PHY_INBAND_CTRL \ ++ GG82563_REG(194, 18) /* Inband Control */ ++#define GG82563_PHY_KMRN_DIAGNOSTIC \ ++ GG82563_REG(194, 19) /* Diagnostic */ ++#define GG82563_PHY_ACK_TIMEOUTS \ ++ GG82563_REG(194, 20) /* Acknowledge Timeouts */ ++#define GG82563_PHY_ADV_ABILITY \ ++ GG82563_REG(194, 21) /* Advertised Ability */ ++#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ ++ GG82563_REG(194, 23) /* Link Partner Advertised Ability */ ++#define GG82563_PHY_ADV_NEXT_PAGE \ ++ GG82563_REG(194, 24) /* Advertised Next Page */ ++#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ ++ GG82563_REG(194, 25) /* Link Partner Advertised Next page */ ++#define GG82563_PHY_KMRN_MISC \ ++ GG82563_REG(194, 26) /* Misc. */ ++ ++/* MDI Control */ ++#define E1000_MDIC_DATA_MASK 0x0000FFFF ++#define E1000_MDIC_REG_MASK 0x001F0000 ++#define E1000_MDIC_REG_SHIFT 16 ++#define E1000_MDIC_PHY_MASK 0x03E00000 ++#define E1000_MDIC_PHY_SHIFT 21 ++#define E1000_MDIC_OP_WRITE 0x04000000 ++#define E1000_MDIC_OP_READ 0x08000000 ++#define E1000_MDIC_READY 0x10000000 ++#define E1000_MDIC_INT_EN 0x20000000 ++#define E1000_MDIC_ERROR 0x40000000 ++ ++/* SerDes Control */ ++#define E1000_GEN_CTL_READY 0x80000000 ++#define E1000_GEN_CTL_ADDRESS_SHIFT 8 ++#define E1000_GEN_POLL_TIMEOUT 640 ++ ++ ++ ++#endif /* _E1000_DEFINES_H_ */ +diff -r b58885ce604a drivers/net/e1000/e1000_ethtool.c +--- a/drivers/net/e1000/e1000_ethtool.c Wed Aug 05 09:27:10 2009 +0100 ++++ b/drivers/net/e1000/e1000_ethtool.c Wed Aug 05 11:02:21 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel PRO/1000 Linux driver +- Copyright(c) 1999 - 2006 Intel Corporation. ++ Copyright(c) 1999 - 2008 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -28,32 +28,45 @@ + + /* ethtool support for e1000 */ + ++#include ++ ++#ifdef SIOCETHTOOL ++#include ++ + #include "e1000.h" +-#include ++#include "e1000_82541.h" ++#ifdef NETIF_F_HW_VLAN_TX ++#include ++#endif + ++#ifdef ETHTOOL_OPS_COMPAT ++#include "kcompat_ethtool.c" ++#endif ++ ++#ifdef ETHTOOL_GSTATS + struct e1000_stats { + char stat_string[ETH_GSTRING_LEN]; + int sizeof_stat; + int stat_offset; + }; + +-#define E1000_STAT(m) FIELD_SIZEOF(struct e1000_adapter, m), \ ++#define E1000_STAT(m) sizeof(((struct e1000_adapter *)0)->m), \ + offsetof(struct e1000_adapter, m) + static const struct e1000_stats e1000_gstrings_stats[] = { + { "rx_packets", E1000_STAT(stats.gprc) }, + { "tx_packets", E1000_STAT(stats.gptc) }, +- { "rx_bytes", E1000_STAT(stats.gorcl) }, +- { "tx_bytes", E1000_STAT(stats.gotcl) }, ++ { "rx_bytes", E1000_STAT(stats.gorc) }, ++ { "tx_bytes", E1000_STAT(stats.gotc) }, + { "rx_broadcast", E1000_STAT(stats.bprc) }, + { "tx_broadcast", E1000_STAT(stats.bptc) }, + { "rx_multicast", E1000_STAT(stats.mprc) }, + { "tx_multicast", E1000_STAT(stats.mptc) }, +- { "rx_errors", E1000_STAT(stats.rxerrc) }, +- { "tx_errors", E1000_STAT(stats.txerrc) }, ++ { "rx_errors", E1000_STAT(net_stats.rx_errors) }, ++ { "tx_errors", E1000_STAT(net_stats.tx_errors) }, + { "tx_dropped", E1000_STAT(net_stats.tx_dropped) }, + { "multicast", E1000_STAT(stats.mprc) }, + { "collisions", E1000_STAT(stats.colc) }, +- { "rx_length_errors", E1000_STAT(stats.rlerrc) }, ++ { "rx_length_errors", E1000_STAT(net_stats.rx_length_errors) }, + { "rx_over_errors", E1000_STAT(net_stats.rx_over_errors) }, + { "rx_crc_errors", E1000_STAT(stats.crcerrs) }, + { "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) }, +@@ -79,10 +92,9 @@ + { "rx_flow_control_xoff", E1000_STAT(stats.xoffrxc) }, + { "tx_flow_control_xon", E1000_STAT(stats.xontxc) }, + { "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) }, +- { "rx_long_byte_count", E1000_STAT(stats.gorcl) }, ++ { "rx_long_byte_count", E1000_STAT(stats.gorc) }, + { "rx_csum_offload_good", E1000_STAT(hw_csum_good) }, + { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) }, +- { "rx_header_split", E1000_STAT(rx_hdr_split) }, + { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) }, + { "tx_smbus", E1000_STAT(stats.mgptc) }, + { "rx_smbus", E1000_STAT(stats.mgprc) }, +@@ -90,22 +102,27 @@ + }; + + #define E1000_QUEUE_STATS_LEN 0 +-#define E1000_GLOBAL_STATS_LEN ARRAY_SIZE(e1000_gstrings_stats) ++#define E1000_GLOBAL_STATS_LEN \ ++ sizeof(e1000_gstrings_stats) / sizeof(struct e1000_stats) + #define E1000_STATS_LEN (E1000_GLOBAL_STATS_LEN + E1000_QUEUE_STATS_LEN) ++#endif /* ETHTOOL_GSTATS */ ++#ifdef ETHTOOL_TEST + static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = { + "Register test (offline)", "Eeprom test (offline)", + "Interrupt test (offline)", "Loopback test (offline)", + "Link test (on/offline)" + }; +-#define E1000_TEST_LEN ARRAY_SIZE(e1000_gstrings_test) ++#define E1000_TEST_LEN sizeof(e1000_gstrings_test) / ETH_GSTRING_LEN ++#endif /* ETHTOOL_TEST */ + + static int e1000_get_settings(struct net_device *netdev, +- struct ethtool_cmd *ecmd) ++ struct ethtool_cmd *ecmd) + { + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; ++ u32 status; + +- if (hw->media_type == e1000_media_type_copper) { ++ if (hw->phy.media_type == e1000_media_type_copper) { + + ecmd->supported = (SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | +@@ -114,20 +131,20 @@ + SUPPORTED_1000baseT_Full| + SUPPORTED_Autoneg | + SUPPORTED_TP); +- if (hw->phy_type == e1000_phy_ife) ++ if (hw->phy.type == e1000_phy_ife) + ecmd->supported &= ~SUPPORTED_1000baseT_Full; + ecmd->advertising = ADVERTISED_TP; + +- if (hw->autoneg == 1) { ++ if (hw->mac.autoneg == 1) { + ecmd->advertising |= ADVERTISED_Autoneg; + /* the e1000 autoneg seems to match ethtool nicely */ +- ecmd->advertising |= hw->autoneg_advertised; ++ ecmd->advertising |= hw->phy.autoneg_advertised; + } + + ecmd->port = PORT_TP; +- ecmd->phy_address = hw->phy_addr; ++ ecmd->phy_address = hw->phy.addr; + +- if (hw->mac_type == e1000_82543) ++ if (hw->mac.type == e1000_82543) + ecmd->transceiver = XCVR_EXTERNAL; + else + ecmd->transceiver = XCVR_INTERNAL; +@@ -143,22 +160,26 @@ + + ecmd->port = PORT_FIBRE; + +- if (hw->mac_type >= e1000_82545) ++ if (hw->mac.type >= e1000_82545) + ecmd->transceiver = XCVR_INTERNAL; + else + ecmd->transceiver = XCVR_EXTERNAL; + } + +- if (er32(STATUS) & E1000_STATUS_LU) { ++ status = E1000_READ_REG(&adapter->hw, E1000_STATUS); + +- e1000_get_speed_and_duplex(hw, &adapter->link_speed, +- &adapter->link_duplex); +- ecmd->speed = adapter->link_speed; ++ if (status & E1000_STATUS_LU) { + +- /* unfortunatly FULL_DUPLEX != DUPLEX_FULL +- * and HALF_DUPLEX != DUPLEX_HALF */ ++ if ((status & E1000_STATUS_SPEED_1000) || ++ hw->phy.media_type != e1000_media_type_copper) ++ ecmd->speed = SPEED_1000; ++ else if (status & E1000_STATUS_SPEED_100) ++ ecmd->speed = SPEED_100; ++ else ++ ecmd->speed = SPEED_10; + +- if (adapter->link_duplex == FULL_DUPLEX) ++ if ((status & E1000_STATUS_FD) || ++ hw->phy.media_type != e1000_media_type_copper) + ecmd->duplex = DUPLEX_FULL; + else + ecmd->duplex = DUPLEX_HALF; +@@ -167,59 +188,68 @@ + ecmd->duplex = -1; + } + +- ecmd->autoneg = ((hw->media_type == e1000_media_type_fiber) || +- hw->autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE; ++ ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) || ++ hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE; + return 0; + } + + static int e1000_set_settings(struct net_device *netdev, +- struct ethtool_cmd *ecmd) ++ struct ethtool_cmd *ecmd) + { + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; + ++ /* If speed is 1000, autoneg cannot be turned off */ ++ if ((ecmd->autoneg == 0) && (ecmd->speed == SPEED_1000) && ++ (ecmd->duplex = DUPLEX_FULL)) ++ return -EINVAL; ++ + /* When SoL/IDER sessions are active, autoneg/speed/duplex + * cannot be changed */ +- if (e1000_check_phy_reset_block(hw)) { ++ if (e1000_check_reset_block(hw)) { + DPRINTK(DRV, ERR, "Cannot change link characteristics " + "when SoL/IDER is active.\n"); + return -EINVAL; + } + +- while (test_and_set_bit(__E1000_RESETTING, &adapter->flags)) ++ while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) + msleep(1); + + if (ecmd->autoneg == AUTONEG_ENABLE) { +- hw->autoneg = 1; +- if (hw->media_type == e1000_media_type_fiber) +- hw->autoneg_advertised = ADVERTISED_1000baseT_Full | +- ADVERTISED_FIBRE | +- ADVERTISED_Autoneg; ++ hw->mac.autoneg = 1; ++ if (hw->phy.media_type == e1000_media_type_fiber) ++ hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full | ++ ADVERTISED_FIBRE | ++ ADVERTISED_Autoneg; + else +- hw->autoneg_advertised = ecmd->advertising | +- ADVERTISED_TP | +- ADVERTISED_Autoneg; +- ecmd->advertising = hw->autoneg_advertised; +- } else ++ hw->phy.autoneg_advertised = ecmd->advertising | ++ ADVERTISED_TP | ++ ADVERTISED_Autoneg; ++ ecmd->advertising = hw->phy.autoneg_advertised; ++ if (adapter->fc_autoneg) ++ hw->fc.requested_mode = e1000_fc_default; ++ } else { + if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) { +- clear_bit(__E1000_RESETTING, &adapter->flags); ++ clear_bit(__E1000_RESETTING, &adapter->state); + return -EINVAL; + } ++ } + + /* reset the link */ + + if (netif_running(adapter->netdev)) { + e1000_down(adapter); + e1000_up(adapter); +- } else ++ } else { + e1000_reset(adapter); ++ } + +- clear_bit(__E1000_RESETTING, &adapter->flags); ++ clear_bit(__E1000_RESETTING, &adapter->state); + return 0; + } + + static void e1000_get_pauseparam(struct net_device *netdev, +- struct ethtool_pauseparam *pause) ++ struct ethtool_pauseparam *pause) + { + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +@@ -227,18 +257,18 @@ + pause->autoneg = + (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); + +- if (hw->fc == E1000_FC_RX_PAUSE) ++ if (hw->fc.current_mode == e1000_fc_rx_pause) + pause->rx_pause = 1; +- else if (hw->fc == E1000_FC_TX_PAUSE) ++ else if (hw->fc.current_mode == e1000_fc_tx_pause) + pause->tx_pause = 1; +- else if (hw->fc == E1000_FC_FULL) { ++ else if (hw->fc.current_mode == e1000_fc_full) { + pause->rx_pause = 1; + pause->tx_pause = 1; + } + } + + static int e1000_set_pauseparam(struct net_device *netdev, +- struct ethtool_pauseparam *pause) ++ struct ethtool_pauseparam *pause) + { + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +@@ -246,31 +276,34 @@ + + adapter->fc_autoneg = pause->autoneg; + +- while (test_and_set_bit(__E1000_RESETTING, &adapter->flags)) ++ while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) + msleep(1); + + if (pause->rx_pause && pause->tx_pause) +- hw->fc = E1000_FC_FULL; ++ hw->fc.current_mode = e1000_fc_full; + else if (pause->rx_pause && !pause->tx_pause) +- hw->fc = E1000_FC_RX_PAUSE; ++ hw->fc.current_mode = e1000_fc_rx_pause; + else if (!pause->rx_pause && pause->tx_pause) +- hw->fc = E1000_FC_TX_PAUSE; ++ hw->fc.current_mode = e1000_fc_tx_pause; + else if (!pause->rx_pause && !pause->tx_pause) +- hw->fc = E1000_FC_NONE; ++ hw->fc.current_mode = e1000_fc_none; + +- hw->original_fc = hw->fc; ++ hw->fc.requested_mode = hw->fc.current_mode; + + if (adapter->fc_autoneg == AUTONEG_ENABLE) { ++ hw->fc.current_mode = e1000_fc_default; + if (netif_running(adapter->netdev)) { + e1000_down(adapter); + e1000_up(adapter); +- } else ++ } else { + e1000_reset(adapter); +- } else +- retval = ((hw->media_type == e1000_media_type_fiber) ? ++ } ++ } else { ++ retval = ((hw->phy.media_type == e1000_media_type_fiber) ? + e1000_setup_link(hw) : e1000_force_mac_fc(hw)); ++ } + +- clear_bit(__E1000_RESETTING, &adapter->flags); ++ clear_bit(__E1000_RESETTING, &adapter->state); + return retval; + } + +@@ -300,9 +333,8 @@ + static int e1000_set_tx_csum(struct net_device *netdev, u32 data) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; + +- if (hw->mac_type < e1000_82543) { ++ if (adapter->hw.mac.type < e1000_82543) { + if (!data) + return -EINVAL; + return 0; +@@ -316,29 +348,40 @@ + return 0; + } + ++#ifdef NETIF_F_TSO + static int e1000_set_tso(struct net_device *netdev, u32 data) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; +- +- if ((hw->mac_type < e1000_82544) || +- (hw->mac_type == e1000_82547)) ++ int i; ++ struct net_device *v_netdev; ++ if (!(adapter->flags & E1000_FLAG_HAS_TSO)) + return data ? -EINVAL : 0; + +- if (data) ++ if (data) { + netdev->features |= NETIF_F_TSO; +- else ++ } else { + netdev->features &= ~NETIF_F_TSO; ++#ifdef NETIF_F_HW_VLAN_TX ++ /* disable TSO on all VLANs if they're present */ ++ if (!adapter->vlgrp) ++ goto tso_out; ++ for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) { ++ v_netdev = vlan_group_get_device(adapter->vlgrp, i); ++ if (!v_netdev) ++ continue; + +- if (data && (adapter->hw.mac_type > e1000_82547_rev_2)) +- netdev->features |= NETIF_F_TSO6; +- else +- netdev->features &= ~NETIF_F_TSO6; ++ v_netdev->features &= ~NETIF_F_TSO; ++ vlan_group_set_device(adapter->vlgrp, i, v_netdev); ++ } ++#endif ++ } + ++tso_out: + DPRINTK(PROBE, INFO, "TSO is %s\n", data ? "Enabled" : "Disabled"); +- adapter->tso_force = true; ++ adapter->flags |= E1000_FLAG_TSO_FORCE; + return 0; + } ++#endif /* NETIF_F_TSO */ + + static u32 e1000_get_msglevel(struct net_device *netdev) + { +@@ -358,8 +401,8 @@ + return E1000_REGS_LEN * sizeof(u32); + } + +-static void e1000_get_regs(struct net_device *netdev, struct ethtool_regs *regs, +- void *p) ++static void e1000_get_regs(struct net_device *netdev, ++ struct ethtool_regs *regs, void *p) + { + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +@@ -370,23 +413,23 @@ + + regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; + +- regs_buff[0] = er32(CTRL); +- regs_buff[1] = er32(STATUS); ++ regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); ++ regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); + +- regs_buff[2] = er32(RCTL); +- regs_buff[3] = er32(RDLEN); +- regs_buff[4] = er32(RDH); +- regs_buff[5] = er32(RDT); +- regs_buff[6] = er32(RDTR); ++ regs_buff[2] = E1000_READ_REG(hw, E1000_RCTL); ++ regs_buff[3] = E1000_READ_REG(hw, E1000_RDLEN(0)); ++ regs_buff[4] = E1000_READ_REG(hw, E1000_RDH(0)); ++ regs_buff[5] = E1000_READ_REG(hw, E1000_RDT(0)); ++ regs_buff[6] = E1000_READ_REG(hw, E1000_RDTR); + +- regs_buff[7] = er32(TCTL); +- regs_buff[8] = er32(TDLEN); +- regs_buff[9] = er32(TDH); +- regs_buff[10] = er32(TDT); +- regs_buff[11] = er32(TIDV); ++ regs_buff[7] = E1000_READ_REG(hw, E1000_TCTL); ++ regs_buff[8] = E1000_READ_REG(hw, E1000_TDLEN(0)); ++ regs_buff[9] = E1000_READ_REG(hw, E1000_TDH(0)); ++ regs_buff[10] = E1000_READ_REG(hw, E1000_TDT(0)); ++ regs_buff[11] = E1000_READ_REG(hw, E1000_TIDV); + +- regs_buff[12] = hw->phy_type; /* PHY type (IGP=1, M88=0) */ +- if (hw->phy_type == e1000_phy_igp) { ++ regs_buff[12] = adapter->hw.phy.type; /* PHY type (IGP=1, M88=0) */ ++ if (hw->phy.type == e1000_phy_igp) { + e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, + IGP01E1000_PHY_AGC_A); + e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_A & +@@ -440,23 +483,20 @@ + e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); + regs_buff[24] = (u32)phy_data; /* phy local receiver status */ + regs_buff[25] = regs_buff[24]; /* phy remote receiver status */ +- if (hw->mac_type >= e1000_82540 && +- hw->mac_type < e1000_82571 && +- hw->media_type == e1000_media_type_copper) { +- regs_buff[26] = er32(MANC); ++ if (hw->mac.type >= e1000_82540 && ++ hw->phy.media_type == e1000_media_type_copper) { ++ regs_buff[26] = E1000_READ_REG(hw, E1000_MANC); + } + } + + static int e1000_get_eeprom_len(struct net_device *netdev) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; +- +- return hw->eeprom.word_size * 2; ++ return adapter->hw.nvm.word_size * 2; + } + + static int e1000_get_eeprom(struct net_device *netdev, +- struct ethtool_eeprom *eeprom, u8 *bytes) ++ struct ethtool_eeprom *eeprom, u8 *bytes) + { + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +@@ -478,17 +518,15 @@ + if (!eeprom_buff) + return -ENOMEM; + +- if (hw->eeprom.type == e1000_eeprom_spi) +- ret_val = e1000_read_eeprom(hw, first_word, +- last_word - first_word + 1, +- eeprom_buff); ++ if (hw->nvm.type == e1000_nvm_eeprom_spi) ++ ret_val = e1000_read_nvm(hw, first_word, ++ last_word - first_word + 1, ++ eeprom_buff); + else { +- for (i = 0; i < last_word - first_word + 1; i++) { +- ret_val = e1000_read_eeprom(hw, first_word + i, 1, +- &eeprom_buff[i]); +- if (ret_val) ++ for (i = 0; i < last_word - first_word + 1; i++) ++ if ((ret_val = e1000_read_nvm(hw, first_word + i, 1, ++ &eeprom_buff[i]))) + break; +- } + } + + /* Device's eeprom is always little-endian, word addressable */ +@@ -503,7 +541,7 @@ + } + + static int e1000_set_eeprom(struct net_device *netdev, +- struct ethtool_eeprom *eeprom, u8 *bytes) ++ struct ethtool_eeprom *eeprom, u8 *bytes) + { + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +@@ -518,7 +556,7 @@ + if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) + return -EFAULT; + +- max_len = hw->eeprom.word_size * 2; ++ max_len = hw->nvm.word_size * 2; + + first_word = eeprom->offset >> 1; + last_word = (eeprom->offset + eeprom->len - 1) >> 1; +@@ -531,14 +569,14 @@ + if (eeprom->offset & 1) { + /* need read/modify/write of first changed EEPROM word */ + /* only the second byte of the word is being modified */ +- ret_val = e1000_read_eeprom(hw, first_word, 1, ++ ret_val = e1000_read_nvm(hw, first_word, 1, + &eeprom_buff[0]); + ptr++; + } + if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { + /* need read/modify/write of last changed EEPROM word */ + /* only the first byte of the word is being modified */ +- ret_val = e1000_read_eeprom(hw, last_word, 1, ++ ret_val = e1000_read_nvm(hw, last_word, 1, + &eeprom_buff[last_word - first_word]); + } + +@@ -551,62 +589,39 @@ + for (i = 0; i < last_word - first_word + 1; i++) + eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); + +- ret_val = e1000_write_eeprom(hw, first_word, +- last_word - first_word + 1, eeprom_buff); ++ ret_val = e1000_write_nvm(hw, first_word, ++ last_word - first_word + 1, eeprom_buff); + +- /* Update the checksum over the first part of the EEPROM if needed +- * and flush shadow RAM for 82573 conrollers */ +- if ((ret_val == 0) && ((first_word <= EEPROM_CHECKSUM_REG) || +- (hw->mac_type == e1000_82573))) +- e1000_update_eeprom_checksum(hw); ++ /* Update the checksum over the first part of the EEPROM if needed */ ++ if ((ret_val == 0) && (first_word <= NVM_CHECKSUM_REG)) ++ e1000_update_nvm_checksum(hw); + + kfree(eeprom_buff); + return ret_val; + } + + static void e1000_get_drvinfo(struct net_device *netdev, +- struct ethtool_drvinfo *drvinfo) ++ struct ethtool_drvinfo *drvinfo) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; +- char firmware_version[32]; +- u16 eeprom_data; + + strncpy(drvinfo->driver, e1000_driver_name, 32); + strncpy(drvinfo->version, e1000_driver_version, 32); +- +- /* EEPROM image version # is reported as firmware version # for +- * 8257{1|2|3} controllers */ +- e1000_read_eeprom(hw, 5, 1, &eeprom_data); +- switch (hw->mac_type) { +- case e1000_82571: +- case e1000_82572: +- case e1000_82573: +- case e1000_80003es2lan: +- case e1000_ich8lan: +- sprintf(firmware_version, "%d.%d-%d", +- (eeprom_data & 0xF000) >> 12, +- (eeprom_data & 0x0FF0) >> 4, +- eeprom_data & 0x000F); +- break; +- default: +- sprintf(firmware_version, "N/A"); +- } +- +- strncpy(drvinfo->fw_version, firmware_version, 32); ++ strcpy(drvinfo->fw_version, "N/A"); + strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); ++ drvinfo->n_stats = E1000_STATS_LEN; ++ drvinfo->testinfo_len = E1000_TEST_LEN; + drvinfo->regdump_len = e1000_get_regs_len(netdev); + drvinfo->eedump_len = e1000_get_eeprom_len(netdev); + } + + static void e1000_get_ringparam(struct net_device *netdev, +- struct ethtool_ringparam *ring) ++ struct ethtool_ringparam *ring) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; +- e1000_mac_type mac_type = hw->mac_type; +- struct e1000_tx_ring *txdr = adapter->tx_ring; +- struct e1000_rx_ring *rxdr = adapter->rx_ring; ++ enum e1000_mac_type mac_type = adapter->hw.mac.type; ++ struct e1000_tx_ring *tx_ring = adapter->tx_ring; ++ struct e1000_rx_ring *rx_ring = adapter->rx_ring; + + ring->rx_max_pending = (mac_type < e1000_82544) ? E1000_MAX_RXD : + E1000_MAX_82544_RXD; +@@ -614,26 +629,28 @@ + E1000_MAX_82544_TXD; + ring->rx_mini_max_pending = 0; + ring->rx_jumbo_max_pending = 0; +- ring->rx_pending = rxdr->count; +- ring->tx_pending = txdr->count; ++ ring->rx_pending = rx_ring->count; ++ ring->tx_pending = tx_ring->count; + ring->rx_mini_pending = 0; + ring->rx_jumbo_pending = 0; + } + + static int e1000_set_ringparam(struct net_device *netdev, +- struct ethtool_ringparam *ring) ++ struct ethtool_ringparam *ring) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; +- e1000_mac_type mac_type = hw->mac_type; +- struct e1000_tx_ring *txdr, *tx_old; +- struct e1000_rx_ring *rxdr, *rx_old; +- int i, err; ++ enum e1000_mac_type mac_type = adapter->hw.mac.type; ++ struct e1000_tx_ring *tx_ring, *tx_old; ++ struct e1000_rx_ring *rx_ring, *rx_old; ++ int err, tx_ring_size, rx_ring_size; + + if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) + return -EINVAL; + +- while (test_and_set_bit(__E1000_RESETTING, &adapter->flags)) ++ tx_ring_size = sizeof(struct e1000_tx_ring); ++ rx_ring_size = sizeof(struct e1000_rx_ring); ++ ++ while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) + msleep(1); + + if (netif_running(adapter->netdev)) +@@ -643,164 +660,135 @@ + rx_old = adapter->rx_ring; + + err = -ENOMEM; +- txdr = kcalloc(adapter->num_tx_queues, sizeof(struct e1000_tx_ring), GFP_KERNEL); +- if (!txdr) ++ tx_ring = kzalloc(tx_ring_size, GFP_KERNEL); ++ if (!tx_ring) + goto err_alloc_tx; ++ /* use a memcpy to save any previously configured ++ * items like napi structs from having to be ++ * reinitialized */ ++ memcpy(tx_ring, tx_old, tx_ring_size); + +- rxdr = kcalloc(adapter->num_rx_queues, sizeof(struct e1000_rx_ring), GFP_KERNEL); +- if (!rxdr) ++ rx_ring = kzalloc(rx_ring_size, GFP_KERNEL); ++ if (!rx_ring) + goto err_alloc_rx; ++ memcpy(rx_ring, rx_old, rx_ring_size); + +- adapter->tx_ring = txdr; +- adapter->rx_ring = rxdr; ++ adapter->tx_ring = tx_ring; ++ adapter->rx_ring = rx_ring; + +- rxdr->count = max(ring->rx_pending,(u32)E1000_MIN_RXD); +- rxdr->count = min(rxdr->count,(u32)(mac_type < e1000_82544 ? ++ rx_ring->count = max(ring->rx_pending,(u32)E1000_MIN_RXD); ++ rx_ring->count = min(rx_ring->count,(u32)(mac_type < e1000_82544 ? + E1000_MAX_RXD : E1000_MAX_82544_RXD)); +- rxdr->count = ALIGN(rxdr->count, REQ_RX_DESCRIPTOR_MULTIPLE); ++ rx_ring->count = ALIGN(rx_ring->count, REQ_RX_DESCRIPTOR_MULTIPLE); + +- txdr->count = max(ring->tx_pending,(u32)E1000_MIN_TXD); +- txdr->count = min(txdr->count,(u32)(mac_type < e1000_82544 ? ++ tx_ring->count = max(ring->tx_pending,(u32)E1000_MIN_TXD); ++ tx_ring->count = min(tx_ring->count,(u32)(mac_type < e1000_82544 ? + E1000_MAX_TXD : E1000_MAX_82544_TXD)); +- txdr->count = ALIGN(txdr->count, REQ_TX_DESCRIPTOR_MULTIPLE); +- +- for (i = 0; i < adapter->num_tx_queues; i++) +- txdr[i].count = txdr->count; +- for (i = 0; i < adapter->num_rx_queues; i++) +- rxdr[i].count = rxdr->count; ++ tx_ring->count = ALIGN(tx_ring->count, REQ_TX_DESCRIPTOR_MULTIPLE); + + if (netif_running(adapter->netdev)) { + /* Try to get new resources before deleting old */ +- err = e1000_setup_all_rx_resources(adapter); +- if (err) ++ if ((err = e1000_setup_all_rx_resources(adapter))) + goto err_setup_rx; +- err = e1000_setup_all_tx_resources(adapter); +- if (err) ++ if ((err = e1000_setup_all_tx_resources(adapter))) + goto err_setup_tx; + +- /* save the new, restore the old in order to free it, +- * then restore the new back again */ +- ++ /* restore the old in order to free it, ++ * then add in the new */ + adapter->rx_ring = rx_old; + adapter->tx_ring = tx_old; + e1000_free_all_rx_resources(adapter); + e1000_free_all_tx_resources(adapter); + kfree(tx_old); + kfree(rx_old); +- adapter->rx_ring = rxdr; +- adapter->tx_ring = txdr; +- err = e1000_up(adapter); +- if (err) ++ adapter->rx_ring = rx_ring; ++ adapter->tx_ring = tx_ring; ++ if ((err = e1000_up(adapter))) + goto err_setup; + } + +- clear_bit(__E1000_RESETTING, &adapter->flags); ++ clear_bit(__E1000_RESETTING, &adapter->state); + return 0; + err_setup_tx: + e1000_free_all_rx_resources(adapter); + err_setup_rx: + adapter->rx_ring = rx_old; + adapter->tx_ring = tx_old; +- kfree(rxdr); ++ kfree(rx_ring); + err_alloc_rx: +- kfree(txdr); ++ kfree(tx_ring); + err_alloc_tx: + e1000_up(adapter); + err_setup: +- clear_bit(__E1000_RESETTING, &adapter->flags); ++ clear_bit(__E1000_RESETTING, &adapter->state); + return err; + } + +-static bool reg_pattern_test(struct e1000_adapter *adapter, u64 *data, int reg, +- u32 mask, u32 write) ++static bool reg_pattern_test(struct e1000_adapter *adapter, u64 *data, ++ int reg, int offset, u32 mask, u32 write) + { +- struct e1000_hw *hw = &adapter->hw; ++ u32 pat, val; + static const u32 test[] = + {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; +- u8 __iomem *address = hw->hw_addr + reg; +- u32 read; +- int i; +- +- for (i = 0; i < ARRAY_SIZE(test); i++) { +- writel(write & test[i], address); +- read = readl(address); +- if (read != (write & test[i] & mask)) { +- DPRINTK(DRV, ERR, "pattern test reg %04X failed: " +- "got 0x%08X expected 0x%08X\n", +- reg, read, (write & test[i] & mask)); +- *data = reg; +- return true; ++ for (pat = 0; pat < ARRAY_SIZE(test); pat++) { ++ E1000_WRITE_REG_ARRAY(&adapter->hw, reg, offset, ++ (test[pat] & write)); ++ val = E1000_READ_REG_ARRAY(&adapter->hw, reg, offset); ++ if (val != (test[pat] & write & mask)) { ++ DPRINTK(DRV, ERR, "pattern test reg %04X failed: got " ++ "0x%08X expected 0x%08X\n", ++ E1000_REGISTER(&adapter->hw, reg) + offset, ++ val, (test[pat] & write & mask)); ++ *data = E1000_REGISTER(&adapter->hw, reg); ++ return 1; + } + } +- return false; ++ return 0; + } + +-static bool reg_set_and_check(struct e1000_adapter *adapter, u64 *data, int reg, +- u32 mask, u32 write) ++static bool reg_set_and_check(struct e1000_adapter *adapter, u64 *data, ++ int reg, u32 mask, u32 write) + { +- struct e1000_hw *hw = &adapter->hw; +- u8 __iomem *address = hw->hw_addr + reg; +- u32 read; ++ u32 val; ++ E1000_WRITE_REG(&adapter->hw, reg, write & mask); ++ val = E1000_READ_REG(&adapter->hw, reg); ++ if ((write & mask) != (val & mask)) { ++ DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X" ++ "expected 0x%08X\n", reg, (val & mask), (write & mask)); ++ *data = E1000_REGISTER(&adapter->hw, reg); ++ return 1; ++ } ++ return 0; ++} ++#define REG_PATTERN_TEST_ARRAY(reg, offset, mask, write) \ ++ do { \ ++ if (reg_pattern_test(adapter, data, reg, offset, mask, write)) \ ++ return 1; \ ++ } while (0) ++#define REG_PATTERN_TEST(reg, mask, write) \ ++ REG_PATTERN_TEST_ARRAY(reg, 0, mask, write) + +- writel(write & mask, address); +- read = readl(address); +- if ((read & mask) != (write & mask)) { +- DPRINTK(DRV, ERR, "set/check reg %04X test failed: " +- "got 0x%08X expected 0x%08X\n", +- reg, (read & mask), (write & mask)); +- *data = reg; +- return true; +- } +- return false; +-} +- +-#define REG_PATTERN_TEST(reg, mask, write) \ +- do { \ +- if (reg_pattern_test(adapter, data, \ +- (hw->mac_type >= e1000_82543) \ +- ? E1000_##reg : E1000_82542_##reg, \ +- mask, write)) \ +- return 1; \ +- } while (0) +- +-#define REG_SET_AND_CHECK(reg, mask, write) \ +- do { \ +- if (reg_set_and_check(adapter, data, \ +- (hw->mac_type >= e1000_82543) \ +- ? E1000_##reg : E1000_82542_##reg, \ +- mask, write)) \ +- return 1; \ ++#define REG_SET_AND_CHECK(reg, mask, write) \ ++ do { \ ++ if (reg_set_and_check(adapter, data, reg, mask, write)) \ ++ return 1; \ + } while (0) + + static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) + { ++ struct e1000_mac_info *mac = &adapter->hw.mac; + u32 value, before, after; + u32 i, toggle; +- struct e1000_hw *hw = &adapter->hw; + + /* The status register is Read Only, so a write should fail. + * Some bits that get toggled are ignored. + */ +- switch (hw->mac_type) { +- /* there are several bits on newer hardware that are r/w */ +- case e1000_82571: +- case e1000_82572: +- case e1000_80003es2lan: +- toggle = 0x7FFFF3FF; +- break; +- case e1000_82573: +- case e1000_ich8lan: +- toggle = 0x7FFFF033; +- break; +- default: +- toggle = 0xFFFFF833; +- break; +- } ++ toggle = 0xFFFFF833; + +- before = er32(STATUS); +- value = (er32(STATUS) & toggle); +- ew32(STATUS, toggle); +- after = er32(STATUS) & toggle; ++ before = E1000_READ_REG(&adapter->hw, E1000_STATUS); ++ value = (E1000_READ_REG(&adapter->hw, E1000_STATUS) & toggle); ++ E1000_WRITE_REG(&adapter->hw, E1000_STATUS, toggle); ++ after = E1000_READ_REG(&adapter->hw, E1000_STATUS) & toggle; + if (value != after) { + DPRINTK(DRV, ERR, "failed STATUS register test got: " + "0x%08X expected: 0x%08X\n", after, value); +@@ -808,61 +796,52 @@ + return 1; + } + /* restore previous status */ +- ew32(STATUS, before); ++ E1000_WRITE_REG(&adapter->hw, E1000_STATUS, before); + +- if (hw->mac_type != e1000_ich8lan) { +- REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF); +- REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF); +- REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF); +- REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF); +- } ++ REG_PATTERN_TEST(E1000_FCAL, 0xFFFFFFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_FCAH, 0x0000FFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_FCT, 0x0000FFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_VET, 0x0000FFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_RDTR, 0x0000FFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_RDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_RDLEN(0), 0x000FFF80, 0x000FFFFF); ++ REG_PATTERN_TEST(E1000_RDH(0), 0x0000FFFF, 0x0000FFFF); ++ REG_PATTERN_TEST(E1000_RDT(0), 0x0000FFFF, 0x0000FFFF); ++ REG_PATTERN_TEST(E1000_FCRTH, 0x0000FFF8, 0x0000FFF8); ++ REG_PATTERN_TEST(E1000_FCTTV, 0x0000FFFF, 0x0000FFFF); ++ REG_PATTERN_TEST(E1000_TIPG, 0x3FFFFFFF, 0x3FFFFFFF); ++ REG_PATTERN_TEST(E1000_TDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_TDLEN(0), 0x000FFF80, 0x000FFFFF); + +- REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF); +- REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF); +- REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF); +- REG_PATTERN_TEST(RDH, 0x0000FFFF, 0x0000FFFF); +- REG_PATTERN_TEST(RDT, 0x0000FFFF, 0x0000FFFF); +- REG_PATTERN_TEST(FCRTH, 0x0000FFF8, 0x0000FFF8); +- REG_PATTERN_TEST(FCTTV, 0x0000FFFF, 0x0000FFFF); +- REG_PATTERN_TEST(TIPG, 0x3FFFFFFF, 0x3FFFFFFF); +- REG_PATTERN_TEST(TDBAH, 0xFFFFFFFF, 0xFFFFFFFF); +- REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF); ++ REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000); + +- REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000); ++ before = 0x06DFB3FE; ++ REG_SET_AND_CHECK(E1000_RCTL, before, 0x003FFFFB); ++ REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000); + +- before = (hw->mac_type == e1000_ich8lan ? +- 0x06C3B33E : 0x06DFB3FE); +- REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB); +- REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000); ++ if (mac->type >= e1000_82543) { + +- if (hw->mac_type >= e1000_82543) { +- +- REG_SET_AND_CHECK(RCTL, before, 0xFFFFFFFF); +- REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF); +- if (hw->mac_type != e1000_ich8lan) +- REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF); +- REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF); +- REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF); +- value = (hw->mac_type == e1000_ich8lan ? +- E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES); +- for (i = 0; i < value; i++) { +- REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF, +- 0xFFFFFFFF); ++ REG_SET_AND_CHECK(E1000_RCTL, before, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_RDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF); ++ REG_PATTERN_TEST(E1000_TDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF); ++ for (i = 0; i < mac->rar_entry_count; i++) { ++ REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1), ++ 0x8003FFFF, 0xFFFFFFFF); + } + + } else { + +- REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x01FFFFFF); +- REG_PATTERN_TEST(RDBAL, 0xFFFFF000, 0xFFFFFFFF); +- REG_PATTERN_TEST(TXCW, 0x0000FFFF, 0x0000FFFF); +- REG_PATTERN_TEST(TDBAL, 0xFFFFF000, 0xFFFFFFFF); ++ REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x01FFFFFF); ++ REG_PATTERN_TEST(E1000_RDBAL(0), 0xFFFFF000, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_TXCW, 0x0000FFFF, 0x0000FFFF); ++ REG_PATTERN_TEST(E1000_TDBAL(0), 0xFFFFF000, 0xFFFFFFFF); + + } + +- value = (hw->mac_type == e1000_ich8lan ? +- E1000_MC_TBL_SIZE_ICH8LAN : E1000_MC_TBL_SIZE); +- for (i = 0; i < value; i++) +- REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF); ++ for (i = 0; i < mac->mta_reg_count; i++) ++ REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF); + + *data = 0; + return 0; +@@ -870,15 +849,14 @@ + + static int e1000_eeprom_test(struct e1000_adapter *adapter, u64 *data) + { +- struct e1000_hw *hw = &adapter->hw; + u16 temp; + u16 checksum = 0; + u16 i; + + *data = 0; + /* Read and add up the contents of the EEPROM */ +- for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { +- if ((e1000_read_eeprom(hw, i, 1, &temp)) < 0) { ++ for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { ++ if ((e1000_read_nvm(&adapter->hw, i, 1, &temp)) < 0) { + *data = 1; + break; + } +@@ -886,7 +864,7 @@ + } + + /* If Checksum is not Correct return error else test passed */ +- if ((checksum != (u16)EEPROM_SUM) && !(*data)) ++ if ((checksum != (u16) NVM_SUM) && !(*data)) + *data = 2; + + return *data; +@@ -894,11 +872,10 @@ + + static irqreturn_t e1000_test_intr(int irq, void *data) + { +- struct net_device *netdev = (struct net_device *)data; ++ struct net_device *netdev = (struct net_device *) data; + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; + +- adapter->test_icr |= er32(ICR); ++ adapter->test_icr |= E1000_READ_REG(&adapter->hw, E1000_ICR); + + return IRQ_HANDLED; + } +@@ -906,10 +883,8 @@ + static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) + { + struct net_device *netdev = adapter->netdev; +- u32 mask, i = 0; +- bool shared_int = true; ++ u32 mask, i=0, shared_int = TRUE; + u32 irq = adapter->pdev->irq; +- struct e1000_hw *hw = &adapter->hw; + + *data = 0; + +@@ -917,7 +892,7 @@ + /* Hook up test interrupt handler just for this test */ + if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, netdev->name, + netdev)) +- shared_int = false; ++ shared_int = FALSE; + else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED, + netdev->name, netdev)) { + *data = 1; +@@ -927,14 +902,11 @@ + (shared_int ? "shared" : "unshared")); + + /* Disable all the interrupts */ +- ew32(IMC, 0xFFFFFFFF); ++ E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xFFFFFFFF); + msleep(10); + + /* Test each interrupt */ + for (; i < 10; i++) { +- +- if (hw->mac_type == e1000_ich8lan && i == 8) +- continue; + + /* Interrupt to test */ + mask = 1 << i; +@@ -947,8 +919,8 @@ + * test failed. + */ + adapter->test_icr = 0; +- ew32(IMC, mask); +- ew32(ICS, mask); ++ E1000_WRITE_REG(&adapter->hw, E1000_IMC, mask); ++ E1000_WRITE_REG(&adapter->hw, E1000_ICS, mask); + msleep(10); + + if (adapter->test_icr & mask) { +@@ -964,8 +936,8 @@ + * test failed. + */ + adapter->test_icr = 0; +- ew32(IMS, mask); +- ew32(ICS, mask); ++ E1000_WRITE_REG(&adapter->hw, E1000_IMS, mask); ++ E1000_WRITE_REG(&adapter->hw, E1000_ICS, mask); + msleep(10); + + if (!(adapter->test_icr & mask)) { +@@ -981,8 +953,10 @@ + * test failed. + */ + adapter->test_icr = 0; +- ew32(IMC, ~mask & 0x00007FFF); +- ew32(ICS, ~mask & 0x00007FFF); ++ E1000_WRITE_REG(&adapter->hw, E1000_IMC, ++ ~mask & 0x00007FFF); ++ E1000_WRITE_REG(&adapter->hw, E1000_ICS, ++ ~mask & 0x00007FFF); + msleep(10); + + if (adapter->test_icr) { +@@ -993,7 +967,7 @@ + } + + /* Disable all the interrupts */ +- ew32(IMC, 0xFFFFFFFF); ++ E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xFFFFFFFF); + msleep(10); + + /* Unhook test interrupt handler */ +@@ -1004,163 +978,167 @@ + + static void e1000_free_desc_rings(struct e1000_adapter *adapter) + { +- struct e1000_tx_ring *txdr = &adapter->test_tx_ring; +- struct e1000_rx_ring *rxdr = &adapter->test_rx_ring; ++ struct e1000_tx_ring *tx_ring = &adapter->test_tx_ring; ++ struct e1000_rx_ring *rx_ring = &adapter->test_rx_ring; + struct pci_dev *pdev = adapter->pdev; + int i; + +- if (txdr->desc && txdr->buffer_info) { +- for (i = 0; i < txdr->count; i++) { +- if (txdr->buffer_info[i].dma) +- pci_unmap_single(pdev, txdr->buffer_info[i].dma, +- txdr->buffer_info[i].length, ++ if (tx_ring->desc && tx_ring->buffer_info) { ++ for (i = 0; i < tx_ring->count; i++) { ++ if (tx_ring->buffer_info[i].dma) ++ pci_unmap_single(pdev, tx_ring->buffer_info[i].dma, ++ tx_ring->buffer_info[i].length, + PCI_DMA_TODEVICE); +- if (txdr->buffer_info[i].skb) +- dev_kfree_skb(txdr->buffer_info[i].skb); ++ if (tx_ring->buffer_info[i].skb) ++ dev_kfree_skb(tx_ring->buffer_info[i].skb); + } + } + +- if (rxdr->desc && rxdr->buffer_info) { +- for (i = 0; i < rxdr->count; i++) { +- if (rxdr->buffer_info[i].dma) +- pci_unmap_single(pdev, rxdr->buffer_info[i].dma, +- rxdr->buffer_info[i].length, ++ if (rx_ring->desc && rx_ring->buffer_info) { ++ for (i = 0; i < rx_ring->count; i++) { ++ if (rx_ring->buffer_info[i].dma) ++ pci_unmap_single(pdev, rx_ring->buffer_info[i].dma, ++ E1000_RXBUFFER_2048, + PCI_DMA_FROMDEVICE); +- if (rxdr->buffer_info[i].skb) +- dev_kfree_skb(rxdr->buffer_info[i].skb); ++ if (rx_ring->buffer_info[i].skb) ++ dev_kfree_skb(rx_ring->buffer_info[i].skb); + } + } + +- if (txdr->desc) { +- pci_free_consistent(pdev, txdr->size, txdr->desc, txdr->dma); +- txdr->desc = NULL; ++ if (tx_ring->desc) { ++ pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); ++ tx_ring->desc = NULL; + } +- if (rxdr->desc) { +- pci_free_consistent(pdev, rxdr->size, rxdr->desc, rxdr->dma); +- rxdr->desc = NULL; ++ if (rx_ring->desc) { ++ pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); ++ rx_ring->desc = NULL; + } + +- kfree(txdr->buffer_info); +- txdr->buffer_info = NULL; +- kfree(rxdr->buffer_info); +- rxdr->buffer_info = NULL; ++ kfree(tx_ring->buffer_info); ++ tx_ring->buffer_info = NULL; ++ kfree(rx_ring->buffer_info); ++ rx_ring->buffer_info = NULL; + + return; + } + + static int e1000_setup_desc_rings(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- struct e1000_tx_ring *txdr = &adapter->test_tx_ring; +- struct e1000_rx_ring *rxdr = &adapter->test_rx_ring; ++ struct e1000_tx_ring *tx_ring = &adapter->test_tx_ring; ++ struct e1000_rx_ring *rx_ring = &adapter->test_rx_ring; + struct pci_dev *pdev = adapter->pdev; + u32 rctl; + int i, ret_val; + + /* Setup Tx descriptor ring and Tx buffers */ + +- if (!txdr->count) +- txdr->count = E1000_DEFAULT_TXD; ++ if (!tx_ring->count) ++ tx_ring->count = E1000_DEFAULT_TXD; + +- txdr->buffer_info = kcalloc(txdr->count, sizeof(struct e1000_buffer), +- GFP_KERNEL); +- if (!txdr->buffer_info) { ++ if (!(tx_ring->buffer_info = kcalloc(tx_ring->count, ++ sizeof(struct e1000_buffer), ++ GFP_KERNEL))) { + ret_val = 1; + goto err_nomem; + } + +- txdr->size = txdr->count * sizeof(struct e1000_tx_desc); +- txdr->size = ALIGN(txdr->size, 4096); +- txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma); +- if (!txdr->desc) { ++ tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); ++ tx_ring->size = ALIGN(tx_ring->size, 4096); ++ if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, ++ &tx_ring->dma))) { + ret_val = 2; + goto err_nomem; + } +- memset(txdr->desc, 0, txdr->size); +- txdr->next_to_use = txdr->next_to_clean = 0; ++ tx_ring->next_to_use = tx_ring->next_to_clean = 0; + +- ew32(TDBAL, ((u64)txdr->dma & 0x00000000FFFFFFFF)); +- ew32(TDBAH, ((u64)txdr->dma >> 32)); +- ew32(TDLEN, txdr->count * sizeof(struct e1000_tx_desc)); +- ew32(TDH, 0); +- ew32(TDT, 0); +- ew32(TCTL, E1000_TCTL_PSP | E1000_TCTL_EN | +- E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT | +- E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT); ++ E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), ++ ((u64) tx_ring->dma & 0x00000000FFFFFFFF)); ++ E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), ((u64) tx_ring->dma >> 32)); ++ E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), ++ tx_ring->count * sizeof(struct e1000_tx_desc)); ++ E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); ++ E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); ++ E1000_WRITE_REG(&adapter->hw, E1000_TCTL, ++ E1000_TCTL_MULR | ++ E1000_TCTL_PSP | E1000_TCTL_EN | ++ E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT | ++ E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT); + +- for (i = 0; i < txdr->count; i++) { +- struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*txdr, i); ++ for (i = 0; i < tx_ring->count; i++) { ++ struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i); + struct sk_buff *skb; + unsigned int size = 1024; + +- skb = alloc_skb(size, GFP_KERNEL); +- if (!skb) { ++ if (!(skb = alloc_skb(size, GFP_KERNEL))) { + ret_val = 3; + goto err_nomem; + } + skb_put(skb, size); +- txdr->buffer_info[i].skb = skb; +- txdr->buffer_info[i].length = skb->len; +- txdr->buffer_info[i].dma = ++ tx_ring->buffer_info[i].skb = skb; ++ tx_ring->buffer_info[i].length = skb->len; ++ tx_ring->buffer_info[i].dma = + pci_map_single(pdev, skb->data, skb->len, + PCI_DMA_TODEVICE); +- tx_desc->buffer_addr = cpu_to_le64(txdr->buffer_info[i].dma); ++ tx_desc->buffer_addr = cpu_to_le64(tx_ring->buffer_info[i].dma); + tx_desc->lower.data = cpu_to_le32(skb->len); + tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP | +- E1000_TXD_CMD_IFCS | +- E1000_TXD_CMD_RPS); ++ E1000_TXD_CMD_IFCS); ++ if (adapter->hw.mac.type < e1000_82543) ++ tx_desc->lower.data |= E1000_TXD_CMD_RPS; ++ else ++ tx_desc->lower.data |= E1000_TXD_CMD_RS; ++ + tx_desc->upper.data = 0; + } + + /* Setup Rx descriptor ring and Rx buffers */ + +- if (!rxdr->count) +- rxdr->count = E1000_DEFAULT_RXD; ++ if (!rx_ring->count) ++ rx_ring->count = E1000_DEFAULT_RXD; + +- rxdr->buffer_info = kcalloc(rxdr->count, sizeof(struct e1000_buffer), +- GFP_KERNEL); +- if (!rxdr->buffer_info) { ++ if (!(rx_ring->buffer_info = kcalloc(rx_ring->count, ++ sizeof(struct e1000_rx_buffer), ++ GFP_KERNEL))) { + ret_val = 4; + goto err_nomem; + } + +- rxdr->size = rxdr->count * sizeof(struct e1000_rx_desc); +- rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma); +- if (!rxdr->desc) { ++ rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc); ++ if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, ++ &rx_ring->dma))) { + ret_val = 5; + goto err_nomem; + } +- memset(rxdr->desc, 0, rxdr->size); +- rxdr->next_to_use = rxdr->next_to_clean = 0; ++ rx_ring->next_to_use = rx_ring->next_to_clean = 0; + +- rctl = er32(RCTL); +- ew32(RCTL, rctl & ~E1000_RCTL_EN); +- ew32(RDBAL, ((u64)rxdr->dma & 0xFFFFFFFF)); +- ew32(RDBAH, ((u64)rxdr->dma >> 32)); +- ew32(RDLEN, rxdr->size); +- ew32(RDH, 0); +- ew32(RDT, 0); ++ rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); ++ E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); ++ E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), ++ ((u64) rx_ring->dma & 0xFFFFFFFF)); ++ E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), ((u64) rx_ring->dma >> 32)); ++ E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), rx_ring->size); ++ E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); ++ E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), 0); + rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 | + E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | +- (hw->mc_filter_type << E1000_RCTL_MO_SHIFT); +- ew32(RCTL, rctl); ++ (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); ++ E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); + +- for (i = 0; i < rxdr->count; i++) { +- struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rxdr, i); ++ for (i = 0; i < rx_ring->count; i++) { ++ struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i); + struct sk_buff *skb; + +- skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL); +- if (!skb) { ++ if (!(skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN, ++ GFP_KERNEL))) { + ret_val = 6; + goto err_nomem; + } + skb_reserve(skb, NET_IP_ALIGN); +- rxdr->buffer_info[i].skb = skb; +- rxdr->buffer_info[i].length = E1000_RXBUFFER_2048; +- rxdr->buffer_info[i].dma = ++ rx_ring->buffer_info[i].skb = skb; ++ rx_ring->buffer_info[i].dma = + pci_map_single(pdev, skb->data, E1000_RXBUFFER_2048, + PCI_DMA_FROMDEVICE); +- rx_desc->buffer_addr = cpu_to_le64(rxdr->buffer_info[i].dma); ++ rx_desc->buffer_addr = cpu_to_le64(rx_ring->buffer_info[i].dma); + memset(skb->data, 0x00, skb->len); + } + +@@ -1173,72 +1151,68 @@ + + static void e1000_phy_disable_receiver(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- + /* Write out to PHY registers 29 and 30 to disable the Receiver. */ +- e1000_write_phy_reg(hw, 29, 0x001F); +- e1000_write_phy_reg(hw, 30, 0x8FFC); +- e1000_write_phy_reg(hw, 29, 0x001A); +- e1000_write_phy_reg(hw, 30, 0x8FF0); ++ e1000_write_phy_reg(&adapter->hw, 29, 0x001F); ++ e1000_write_phy_reg(&adapter->hw, 30, 0x8FFC); ++ e1000_write_phy_reg(&adapter->hw, 29, 0x001A); ++ e1000_write_phy_reg(&adapter->hw, 30, 0x8FF0); + } + + static void e1000_phy_reset_clk_and_crs(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; + u16 phy_reg; + + /* Because we reset the PHY above, we need to re-force TX_CLK in the + * Extended PHY Specific Control Register to 25MHz clock. This + * value defaults back to a 2.5MHz clock when the PHY is reset. + */ +- e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg); ++ e1000_read_phy_reg(&adapter->hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg); + phy_reg |= M88E1000_EPSCR_TX_CLK_25; +- e1000_write_phy_reg(hw, ++ e1000_write_phy_reg(&adapter->hw, + M88E1000_EXT_PHY_SPEC_CTRL, phy_reg); + + /* In addition, because of the s/w reset above, we need to enable + * CRS on TX. This must be set for both full and half duplex + * operation. + */ +- e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_reg); ++ e1000_read_phy_reg(&adapter->hw, M88E1000_PHY_SPEC_CTRL, &phy_reg); + phy_reg |= M88E1000_PSCR_ASSERT_CRS_ON_TX; +- e1000_write_phy_reg(hw, ++ e1000_write_phy_reg(&adapter->hw, + M88E1000_PHY_SPEC_CTRL, phy_reg); + } + + static int e1000_nonintegrated_phy_loopback(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; + u32 ctrl_reg; + u16 phy_reg; + + /* Setup the Device Control Register for PHY loopback test. */ + +- ctrl_reg = er32(CTRL); ++ ctrl_reg = E1000_READ_REG(&adapter->hw, E1000_CTRL); + ctrl_reg |= (E1000_CTRL_ILOS | /* Invert Loss-Of-Signal */ + E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ + E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ + E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ + E1000_CTRL_FD); /* Force Duplex to FULL */ + +- ew32(CTRL, ctrl_reg); ++ E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl_reg); + + /* Read the PHY Specific Control Register (0x10) */ +- e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_reg); ++ e1000_read_phy_reg(&adapter->hw, M88E1000_PHY_SPEC_CTRL, &phy_reg); + + /* Clear Auto-Crossover bits in PHY Specific Control Register + * (bits 6:5). + */ + phy_reg &= ~M88E1000_PSCR_AUTO_X_MODE; +- e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_reg); ++ e1000_write_phy_reg(&adapter->hw, M88E1000_PHY_SPEC_CTRL, phy_reg); + + /* Perform software reset on the PHY */ +- e1000_phy_reset(hw); ++ e1000_phy_commit(&adapter->hw); + + /* Have to setup TX_CLK and TX_CRS after software reset */ + e1000_phy_reset_clk_and_crs(adapter); + +- e1000_write_phy_reg(hw, PHY_CTRL, 0x8100); ++ e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, 0x8100); + + /* Wait for reset to complete. */ + udelay(500); +@@ -1250,23 +1224,23 @@ + e1000_phy_disable_receiver(adapter); + + /* Set the loopback bit in the PHY control register. */ +- e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); ++ e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_reg); + phy_reg |= MII_CR_LOOPBACK; +- e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); ++ e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_reg); + + /* Setup TX_CLK and TX_CRS one more time. */ + e1000_phy_reset_clk_and_crs(adapter); + + /* Check Phy Configuration */ +- e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); ++ e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_reg); + if (phy_reg != 0x4100) + return 9; + +- e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg); ++ e1000_read_phy_reg(&adapter->hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg); + if (phy_reg != 0x0070) + return 10; + +- e1000_read_phy_reg(hw, 29, &phy_reg); ++ e1000_read_phy_reg(&adapter->hw, 29, &phy_reg); + if (phy_reg != 0x001A) + return 11; + +@@ -1275,30 +1249,29 @@ + + static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; + u32 ctrl_reg = 0; + u32 stat_reg = 0; + +- hw->autoneg = false; ++ adapter->hw.mac.autoneg = FALSE; + +- if (hw->phy_type == e1000_phy_m88) { ++ if (adapter->hw.phy.type == e1000_phy_m88) { + /* Auto-MDI/MDIX Off */ +- e1000_write_phy_reg(hw, ++ e1000_write_phy_reg(&adapter->hw, + M88E1000_PHY_SPEC_CTRL, 0x0808); + /* reset to update Auto-MDI/MDIX */ +- e1000_write_phy_reg(hw, PHY_CTRL, 0x9140); ++ e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, 0x9140); + /* autoneg off */ +- e1000_write_phy_reg(hw, PHY_CTRL, 0x8140); +- } else if (hw->phy_type == e1000_phy_gg82563) +- e1000_write_phy_reg(hw, ++ e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, 0x8140); ++ } else if (adapter->hw.phy.type == e1000_phy_gg82563) ++ e1000_write_phy_reg(&adapter->hw, + GG82563_PHY_KMRN_MODE_CTRL, + 0x1CC); + +- ctrl_reg = er32(CTRL); ++ ctrl_reg = E1000_READ_REG(&adapter->hw, E1000_CTRL); + +- if (hw->phy_type == e1000_phy_ife) { ++ if (adapter->hw.phy.type == e1000_phy_ife) { + /* force 100, set loopback */ +- e1000_write_phy_reg(hw, PHY_CTRL, 0x6100); ++ e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, 0x6100); + + /* Now set up the MAC to the same speed/duplex as the PHY. */ + ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ +@@ -1308,10 +1281,10 @@ + E1000_CTRL_FD); /* Force Duplex to FULL */ + } else { + /* force 1000, set loopback */ +- e1000_write_phy_reg(hw, PHY_CTRL, 0x4140); ++ e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, 0x4140); + + /* Now set up the MAC to the same speed/duplex as the PHY. */ +- ctrl_reg = er32(CTRL); ++ ctrl_reg = E1000_READ_REG(&adapter->hw, E1000_CTRL); + ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ + ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ + E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ +@@ -1319,23 +1292,23 @@ + E1000_CTRL_FD); /* Force Duplex to FULL */ + } + +- if (hw->media_type == e1000_media_type_copper && +- hw->phy_type == e1000_phy_m88) ++ if (adapter->hw.phy.media_type == e1000_media_type_copper && ++ adapter->hw.phy.type == e1000_phy_m88) { + ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ +- else { +- /* Set the ILOS bit on the fiber Nic is half +- * duplex link is detected. */ +- stat_reg = er32(STATUS); ++ } else { ++ /* Set the ILOS bit on the fiber Nic if half duplex link is ++ * detected. */ ++ stat_reg = E1000_READ_REG(&adapter->hw, E1000_STATUS); + if ((stat_reg & E1000_STATUS_FD) == 0) + ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU); + } + +- ew32(CTRL, ctrl_reg); ++ E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl_reg); + + /* Disable the receiver on the PHY so when a cable is plugged in, the + * PHY does not begin to autoneg when a cable is reconnected to the NIC. + */ +- if (hw->phy_type == e1000_phy_m88) ++ if (adapter->hw.phy.type == e1000_phy_m88) + e1000_phy_disable_receiver(adapter); + + udelay(500); +@@ -1345,13 +1318,12 @@ + + static int e1000_set_phy_loopback(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; + u16 phy_reg = 0; + u16 count = 0; + +- switch (hw->mac_type) { ++ switch (adapter->hw.mac.type) { + case e1000_82543: +- if (hw->media_type == e1000_media_type_copper) { ++ if (adapter->hw.phy.media_type == e1000_media_type_copper) { + /* Attempt to setup Loopback mode on Non-integrated PHY. + * Some PHY registers get corrupted at random, so + * attempt this 10 times. +@@ -1373,11 +1345,6 @@ + case e1000_82541_rev_2: + case e1000_82547: + case e1000_82547_rev_2: +- case e1000_82571: +- case e1000_82572: +- case e1000_82573: +- case e1000_80003es2lan: +- case e1000_ich8lan: + return e1000_integrated_phy_loopback(adapter); + break; + +@@ -1385,9 +1352,9 @@ + /* Default PHY loopback work is to read the MII + * control register and assert bit 14 (loopback mode). + */ +- e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); ++ e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_reg); + phy_reg |= MII_CR_LOOPBACK; +- e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); ++ e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_reg); + return 0; + break; + } +@@ -1400,30 +1367,22 @@ + struct e1000_hw *hw = &adapter->hw; + u32 rctl; + +- if (hw->media_type == e1000_media_type_fiber || +- hw->media_type == e1000_media_type_internal_serdes) { +- switch (hw->mac_type) { ++ if (hw->phy.media_type == e1000_media_type_fiber || ++ hw->phy.media_type == e1000_media_type_internal_serdes) { ++ switch (hw->mac.type) { + case e1000_82545: + case e1000_82546: + case e1000_82545_rev_3: + case e1000_82546_rev_3: + return e1000_set_phy_loopback(adapter); + break; +- case e1000_82571: +- case e1000_82572: +-#define E1000_SERDES_LB_ON 0x410 +- e1000_set_phy_loopback(adapter); +- ew32(SCTL, E1000_SERDES_LB_ON); +- msleep(10); +- return 0; +- break; + default: +- rctl = er32(RCTL); ++ rctl = E1000_READ_REG(hw, E1000_RCTL); + rctl |= E1000_RCTL_LBM_TCVR; +- ew32(RCTL, rctl); ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); + return 0; + } +- } else if (hw->media_type == e1000_media_type_copper) ++ } else if (hw->phy.media_type == e1000_media_type_copper) + return e1000_set_phy_loopback(adapter); + + return 7; +@@ -1435,43 +1394,23 @@ + u32 rctl; + u16 phy_reg; + +- rctl = er32(RCTL); ++ rctl = E1000_READ_REG(hw, E1000_RCTL); + rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); +- ew32(RCTL, rctl); ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); + +- switch (hw->mac_type) { +- case e1000_82571: +- case e1000_82572: +- if (hw->media_type == e1000_media_type_fiber || +- hw->media_type == e1000_media_type_internal_serdes) { +-#define E1000_SERDES_LB_OFF 0x400 +- ew32(SCTL, E1000_SERDES_LB_OFF); +- msleep(10); +- break; +- } +- /* Fall Through */ +- case e1000_82545: +- case e1000_82546: +- case e1000_82545_rev_3: +- case e1000_82546_rev_3: +- default: +- hw->autoneg = true; +- if (hw->phy_type == e1000_phy_gg82563) +- e1000_write_phy_reg(hw, +- GG82563_PHY_KMRN_MODE_CTRL, +- 0x180); +- e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); +- if (phy_reg & MII_CR_LOOPBACK) { +- phy_reg &= ~MII_CR_LOOPBACK; +- e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); +- e1000_phy_reset(hw); +- } +- break; ++ hw->mac.autoneg = TRUE; ++ if (hw->phy.type == e1000_phy_gg82563) ++ e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x180); ++ e1000_read_phy_reg(hw, PHY_CONTROL, &phy_reg); ++ if (phy_reg & MII_CR_LOOPBACK) { ++ phy_reg &= ~MII_CR_LOOPBACK; ++ e1000_write_phy_reg(hw, PHY_CONTROL, phy_reg); ++ e1000_phy_commit(hw); + } + } + + static void e1000_create_lbtest_frame(struct sk_buff *skb, +- unsigned int frame_size) ++ unsigned int frame_size) + { + memset(skb->data, 0xFF, frame_size); + frame_size &= ~1; +@@ -1480,8 +1419,7 @@ + memset(&skb->data[frame_size / 2 + 12], 0xAF, 1); + } + +-static int e1000_check_lbtest_frame(struct sk_buff *skb, +- unsigned int frame_size) ++static int e1000_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size) + { + frame_size &= ~1; + if (*(skb->data + 3) == 0xFF) { +@@ -1495,52 +1433,51 @@ + + static int e1000_run_loopback_test(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- struct e1000_tx_ring *txdr = &adapter->test_tx_ring; +- struct e1000_rx_ring *rxdr = &adapter->test_rx_ring; ++ struct e1000_tx_ring *tx_ring = &adapter->test_tx_ring; ++ struct e1000_rx_ring *rx_ring = &adapter->test_rx_ring; + struct pci_dev *pdev = adapter->pdev; + int i, j, k, l, lc, good_cnt, ret_val=0; + unsigned long time; + +- ew32(RDT, rxdr->count - 1); ++ E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), rx_ring->count - 1); + + /* Calculate the loop count based on the largest descriptor ring + * The idea is to wrap the largest ring a number of times using 64 + * send/receive pairs during each loop + */ + +- if (rxdr->count <= txdr->count) +- lc = ((txdr->count / 64) * 2) + 1; ++ if (rx_ring->count <= tx_ring->count) ++ lc = ((tx_ring->count / 64) * 2) + 1; + else +- lc = ((rxdr->count / 64) * 2) + 1; ++ lc = ((rx_ring->count / 64) * 2) + 1; + + k = l = 0; + for (j = 0; j <= lc; j++) { /* loop count loop */ + for (i = 0; i < 64; i++) { /* send the packets */ +- e1000_create_lbtest_frame(txdr->buffer_info[i].skb, ++ e1000_create_lbtest_frame(tx_ring->buffer_info[k].skb, + 1024); + pci_dma_sync_single_for_device(pdev, +- txdr->buffer_info[k].dma, +- txdr->buffer_info[k].length, ++ tx_ring->buffer_info[k].dma, ++ tx_ring->buffer_info[k].length, + PCI_DMA_TODEVICE); +- if (unlikely(++k == txdr->count)) k = 0; ++ if (unlikely(++k == tx_ring->count)) k = 0; + } +- ew32(TDT, k); ++ E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), k); + msleep(200); + time = jiffies; /* set the start time for the receive */ + good_cnt = 0; + do { /* receive the sent packets */ + pci_dma_sync_single_for_cpu(pdev, +- rxdr->buffer_info[l].dma, +- rxdr->buffer_info[l].length, +- PCI_DMA_FROMDEVICE); ++ rx_ring->buffer_info[l].dma, ++ E1000_RXBUFFER_2048, ++ PCI_DMA_FROMDEVICE); + + ret_val = e1000_check_lbtest_frame( +- rxdr->buffer_info[l].skb, ++ rx_ring->buffer_info[l].skb, + 1024); + if (!ret_val) + good_cnt++; +- if (unlikely(++l == rxdr->count)) l = 0; ++ if (unlikely(++l == rx_ring->count)) l = 0; + /* time + 20 msecs (200 msecs on 2.4) is more than + * enough time to complete the receives, if it's + * exceeded, break and error off +@@ -1550,7 +1487,7 @@ + ret_val = 13; /* ret_val is the same as mis-compare */ + break; + } +- if (jiffies >= (time + 2)) { ++ if (jiffies >= (time + 20)) { + ret_val = 14; /* error code for time out error */ + break; + } +@@ -1560,22 +1497,18 @@ + + static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data) + { +- struct e1000_hw *hw = &adapter->hw; +- + /* PHY loopback cannot be performed if SoL/IDER + * sessions are active */ +- if (e1000_check_phy_reset_block(hw)) { ++ if (e1000_check_reset_block(&adapter->hw)) { + DPRINTK(DRV, ERR, "Cannot do PHY loopback test " + "when SoL/IDER is active.\n"); + *data = 0; + goto out; + } + +- *data = e1000_setup_desc_rings(adapter); +- if (*data) ++ if ((*data = e1000_setup_desc_rings(adapter))) + goto out; +- *data = e1000_setup_loopback_test(adapter); +- if (*data) ++ if ((*data = e1000_setup_loopback_test(adapter))) + goto err_loopback; + *data = e1000_run_loopback_test(adapter); + e1000_loopback_cleanup(adapter); +@@ -1588,61 +1521,54 @@ + + static int e1000_link_test(struct e1000_adapter *adapter, u64 *data) + { +- struct e1000_hw *hw = &adapter->hw; + *data = 0; +- if (hw->media_type == e1000_media_type_internal_serdes) { ++ if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { + int i = 0; +- hw->serdes_link_down = true; ++ adapter->hw.mac.serdes_has_link = FALSE; + + /* On some blade server designs, link establishment + * could take as long as 2-3 minutes */ + do { +- e1000_check_for_link(hw); +- if (!hw->serdes_link_down) ++ e1000_check_for_link(&adapter->hw); ++ if (adapter->hw.mac.serdes_has_link == TRUE) + return *data; + msleep(20); + } while (i++ < 3750); + + *data = 1; + } else { +- e1000_check_for_link(hw); +- if (hw->autoneg) /* if auto_neg is set wait for it */ ++ e1000_check_for_link(&adapter->hw); ++ if (adapter->hw.mac.autoneg) + msleep(4000); + +- if (!(er32(STATUS) & E1000_STATUS_LU)) { ++ if (!(E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { + *data = 1; + } + } + return *data; + } + +-static int e1000_get_sset_count(struct net_device *netdev, int sset) ++static int e1000_diag_test_count(struct net_device *netdev) + { +- switch (sset) { +- case ETH_SS_TEST: +- return E1000_TEST_LEN; +- case ETH_SS_STATS: +- return E1000_STATS_LEN; +- default: +- return -EOPNOTSUPP; +- } ++ return E1000_TEST_LEN; + } + + static void e1000_diag_test(struct net_device *netdev, +- struct ethtool_test *eth_test, u64 *data) ++ struct ethtool_test *eth_test, u64 *data) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; ++ u16 autoneg_advertised; ++ u8 forced_speed_duplex, autoneg; + bool if_running = netif_running(netdev); + +- set_bit(__E1000_TESTING, &adapter->flags); ++ set_bit(__E1000_TESTING, &adapter->state); + if (eth_test->flags == ETH_TEST_FL_OFFLINE) { + /* Offline tests */ + + /* save speed, duplex, autoneg settings */ +- u16 autoneg_advertised = hw->autoneg_advertised; +- u8 forced_speed_duplex = hw->forced_speed_duplex; +- u8 autoneg = hw->autoneg; ++ autoneg_advertised = adapter->hw.phy.autoneg_advertised; ++ forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; ++ autoneg = adapter->hw.mac.autoneg; + + DPRINTK(HW, INFO, "offline testing starting\n"); + +@@ -1670,17 +1596,22 @@ + + e1000_reset(adapter); + /* make sure the phy is powered up */ +- e1000_power_up_phy(adapter); ++ if (adapter->hw.phy.media_type == e1000_media_type_copper) ++ e1000_power_up_phy(&adapter->hw); + if (e1000_loopback_test(adapter, &data[3])) + eth_test->flags |= ETH_TEST_FL_FAILED; + + /* restore speed, duplex, autoneg settings */ +- hw->autoneg_advertised = autoneg_advertised; +- hw->forced_speed_duplex = forced_speed_duplex; +- hw->autoneg = autoneg; ++ adapter->hw.phy.autoneg_advertised = autoneg_advertised; ++ adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; ++ adapter->hw.mac.autoneg = autoneg; + ++ /* force this routine to wait until autoneg complete/timeout */ ++ adapter->hw.phy.autoneg_wait_to_complete = TRUE; + e1000_reset(adapter); +- clear_bit(__E1000_TESTING, &adapter->flags); ++ adapter->hw.phy.autoneg_wait_to_complete = FALSE; ++ ++ clear_bit(__E1000_TESTING, &adapter->state); + if (if_running) + dev_open(netdev); + } else { +@@ -1695,13 +1626,13 @@ + data[2] = 0; + data[3] = 0; + +- clear_bit(__E1000_TESTING, &adapter->flags); ++ clear_bit(__E1000_TESTING, &adapter->state); + } + msleep_interruptible(4 * 1000); + } + + static int e1000_wol_exclusion(struct e1000_adapter *adapter, +- struct ethtool_wolinfo *wol) ++ struct ethtool_wolinfo *wol) + { + struct e1000_hw *hw = &adapter->hw; + int retval = 1; /* fail by default */ +@@ -1716,30 +1647,22 @@ + case E1000_DEV_ID_82545EM_COPPER: + case E1000_DEV_ID_82546GB_QUAD_COPPER: + case E1000_DEV_ID_82546GB_PCIE: +- case E1000_DEV_ID_82571EB_SERDES_QUAD: + /* these don't support WoL at all */ + wol->supported = 0; + break; + case E1000_DEV_ID_82546EB_FIBER: + case E1000_DEV_ID_82546GB_FIBER: +- case E1000_DEV_ID_82571EB_FIBER: +- case E1000_DEV_ID_82571EB_SERDES: +- case E1000_DEV_ID_82571EB_COPPER: + /* Wake events not supported on port B */ +- if (er32(STATUS) & E1000_STATUS_FUNC_1) { ++ if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FUNC_1) { + wol->supported = 0; + break; + } + /* return success for non excluded adapter ports */ + retval = 0; + break; +- case E1000_DEV_ID_82571EB_QUAD_COPPER: +- case E1000_DEV_ID_82571EB_QUAD_FIBER: +- case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: +- case E1000_DEV_ID_82571PT_QUAD_COPPER: + case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: + /* quad port adapters only support WoL on port A */ +- if (!adapter->quad_port_a) { ++ if (!(adapter->flags & E1000_FLAG_QUAD_PORT_A)) { + wol->supported = 0; + break; + } +@@ -1750,7 +1673,7 @@ + /* dual port cards only support WoL on port A from now on + * unless it was enabled in the eeprom for port B + * so exclude FUNC_1 ports from having WoL enabled */ +- if (er32(STATUS) & E1000_STATUS_FUNC_1 && ++ if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FUNC_1 && + !adapter->eeprom_wol) { + wol->supported = 0; + break; +@@ -1763,10 +1686,9 @@ + } + + static void e1000_get_wol(struct net_device *netdev, +- struct ethtool_wolinfo *wol) ++ struct ethtool_wolinfo *wol) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; + + wol->supported = WAKE_UCAST | WAKE_MCAST | + WAKE_BCAST | WAKE_MAGIC; +@@ -1774,14 +1696,13 @@ + + /* this function will set ->supported = 0 and return 1 if wol is not + * supported by this hardware */ +- if (e1000_wol_exclusion(adapter, wol) || +- !device_can_wakeup(&adapter->pdev->dev)) ++ if (e1000_wol_exclusion(adapter, wol)) + return; + + /* apply any specific unsupported masks here */ +- switch (hw->device_id) { ++ switch (adapter->hw.device_id) { + case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: +- /* KSP3 does not suppport UCAST wake-ups */ ++ /* KSP3 does not support UCAST wake-ups */ + wol->supported &= ~WAKE_UCAST; + + if (adapter->wol & E1000_WUFC_EX) +@@ -1804,7 +1725,8 @@ + return; + } + +-static int e1000_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) ++static int e1000_set_wol(struct net_device *netdev, ++ struct ethtool_wolinfo *wol) + { + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +@@ -1812,8 +1734,7 @@ + if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) + return -EOPNOTSUPP; + +- if (e1000_wol_exclusion(adapter, wol) || +- !device_can_wakeup(&adapter->pdev->dev)) ++ if (e1000_wol_exclusion(adapter, wol)) + return wol->wolopts ? -EOPNOTSUPP : 0; + + switch (hw->device_id) { +@@ -1840,8 +1761,6 @@ + if (wol->wolopts & WAKE_MAGIC) + adapter->wol |= E1000_WUFC_MAG; + +- device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); +- + return 0; + } + +@@ -1854,12 +1773,11 @@ + static void e1000_led_blink_callback(unsigned long data) + { + struct e1000_adapter *adapter = (struct e1000_adapter *) data; +- struct e1000_hw *hw = &adapter->hw; + + if (test_and_change_bit(E1000_LED_ON, &adapter->led_status)) +- e1000_led_off(hw); ++ e1000_led_off(&adapter->hw); + else +- e1000_led_on(hw); ++ e1000_led_on(&adapter->hw); + + mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL); + } +@@ -1867,39 +1785,67 @@ + static int e1000_phys_id(struct net_device *netdev, u32 data) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; + + if (!data) + data = INT_MAX; + +- if (hw->mac_type < e1000_82571) { +- if (!adapter->blink_timer.function) { +- init_timer(&adapter->blink_timer); +- adapter->blink_timer.function = e1000_led_blink_callback; +- adapter->blink_timer.data = (unsigned long)adapter; +- } +- e1000_setup_led(hw); +- mod_timer(&adapter->blink_timer, jiffies); +- msleep_interruptible(data * 1000); +- del_timer_sync(&adapter->blink_timer); +- } else if (hw->phy_type == e1000_phy_ife) { +- if (!adapter->blink_timer.function) { +- init_timer(&adapter->blink_timer); +- adapter->blink_timer.function = e1000_led_blink_callback; +- adapter->blink_timer.data = (unsigned long)adapter; +- } +- mod_timer(&adapter->blink_timer, jiffies); +- msleep_interruptible(data * 1000); +- del_timer_sync(&adapter->blink_timer); +- e1000_write_phy_reg(&(adapter->hw), IFE_PHY_SPECIAL_CONTROL_LED, 0); ++ if (!adapter->blink_timer.function) { ++ init_timer(&adapter->blink_timer); ++ adapter->blink_timer.function = e1000_led_blink_callback; ++ adapter->blink_timer.data = (unsigned long) adapter; ++ } ++ e1000_setup_led(&adapter->hw); ++ mod_timer(&adapter->blink_timer, jiffies); ++ msleep_interruptible(data * 1000); ++ del_timer_sync(&adapter->blink_timer); ++ ++ e1000_led_off(&adapter->hw); ++ clear_bit(E1000_LED_ON, &adapter->led_status); ++ e1000_cleanup_led(&adapter->hw); ++ ++ return 0; ++} ++ ++static int e1000_get_coalesce(struct net_device *netdev, ++ struct ethtool_coalesce *ec) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ if (adapter->itr_setting <= 3) ++ ec->rx_coalesce_usecs = adapter->itr_setting; ++ else ++ ec->rx_coalesce_usecs = 1000000 / adapter->itr_setting; ++ ++ return 0; ++} ++ ++static int e1000_set_coalesce(struct net_device *netdev, ++ struct ethtool_coalesce *ec) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ if ((ec->rx_coalesce_usecs > E1000_MAX_ITR_USECS) || ++ ((ec->rx_coalesce_usecs > 3) && ++ (ec->rx_coalesce_usecs < E1000_MIN_ITR_USECS)) || ++ (ec->rx_coalesce_usecs == 2)) ++ return -EINVAL; ++ ++ if (!(adapter->flags & E1000_FLAG_HAS_INTR_MODERATION)) ++ return -ENOTSUPP; ++ ++ if (ec->rx_coalesce_usecs <= 3) { ++ adapter->itr = 20000; ++ adapter->itr_setting = ec->rx_coalesce_usecs; + } else { +- e1000_blink_led_start(hw); +- msleep_interruptible(data * 1000); ++ adapter->itr = (1000000 / ec->rx_coalesce_usecs); ++ adapter->itr_setting = adapter->itr & ~3; + } + +- e1000_led_off(hw); +- clear_bit(E1000_LED_ON, &adapter->led_status); +- e1000_cleanup_led(hw); ++ if (adapter->itr_setting != 0) ++ E1000_WRITE_REG(&adapter->hw, E1000_ITR, ++ 1000000000 / (adapter->itr * 256)); ++ else ++ E1000_WRITE_REG(&adapter->hw, E1000_ITR, 0); + + return 0; + } +@@ -1912,8 +1858,13 @@ + return 0; + } + ++static int e1000_get_stats_count(struct net_device *netdev) ++{ ++ return E1000_STATS_LEN; ++} ++ + static void e1000_get_ethtool_stats(struct net_device *netdev, +- struct ethtool_stats *stats, u64 *data) ++ struct ethtool_stats *stats, u64 *data) + { + struct e1000_adapter *adapter = netdev_priv(netdev); + int i; +@@ -1928,7 +1879,7 @@ + } + + static void e1000_get_strings(struct net_device *netdev, u32 stringset, +- u8 *data) ++ u8 *data) + { + u8 *p = data; + int i; +@@ -1936,7 +1887,7 @@ + switch (stringset) { + case ETH_SS_TEST: + memcpy(data, *e1000_gstrings_test, +- sizeof(e1000_gstrings_test)); ++ E1000_TEST_LEN*ETH_GSTRING_LEN); + break; + case ETH_SS_STATS: + for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) { +@@ -1949,7 +1900,7 @@ + } + } + +-static const struct ethtool_ops e1000_ethtool_ops = { ++static struct ethtool_ops e1000_ethtool_ops = { + .get_settings = e1000_get_settings, + .set_settings = e1000_set_settings, + .get_drvinfo = e1000_get_drvinfo, +@@ -1972,16 +1923,27 @@ + .set_rx_csum = e1000_set_rx_csum, + .get_tx_csum = e1000_get_tx_csum, + .set_tx_csum = e1000_set_tx_csum, ++ .get_sg = ethtool_op_get_sg, + .set_sg = ethtool_op_set_sg, ++#ifdef NETIF_F_TSO ++ .get_tso = ethtool_op_get_tso, + .set_tso = e1000_set_tso, ++#endif ++ .self_test_count = e1000_diag_test_count, + .self_test = e1000_diag_test, + .get_strings = e1000_get_strings, + .phys_id = e1000_phys_id, ++ .get_stats_count = e1000_get_stats_count, + .get_ethtool_stats = e1000_get_ethtool_stats, +- .get_sset_count = e1000_get_sset_count, ++#ifdef ETHTOOL_GPERMADDR ++ .get_perm_addr = ethtool_op_get_perm_addr, ++#endif ++ .get_coalesce = e1000_get_coalesce, ++ .set_coalesce = e1000_set_coalesce, + }; + + void e1000_set_ethtool_ops(struct net_device *netdev) + { + SET_ETHTOOL_OPS(netdev, &e1000_ethtool_ops); + } ++#endif /* SIOCETHTOOL */ +diff -r b58885ce604a drivers/net/e1000/e1000_hw.h +--- a/drivers/net/e1000/e1000_hw.h Wed Aug 05 09:27:10 2009 +0100 ++++ b/drivers/net/e1000/e1000_hw.h Wed Aug 05 11:02:21 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel PRO/1000 Linux driver +- Copyright(c) 1999 - 2006 Intel Corporation. ++ Copyright(c) 1999 - 2008 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -26,3381 +26,697 @@ + + *******************************************************************************/ + +-/* e1000_hw.h +- * Structures, enums, and macros for the MAC +- */ +- + #ifndef _E1000_HW_H_ + #define _E1000_HW_H_ + + #include "e1000_osdep.h" ++#include "e1000_regs.h" ++#include "e1000_defines.h" + ++struct e1000_hw; + +-/* Forward declarations of structures used by the shared code */ +-struct e1000_hw; +-struct e1000_hw_stats; ++#define E1000_DEV_ID_82542 0x1000 ++#define E1000_DEV_ID_82543GC_FIBER 0x1001 ++#define E1000_DEV_ID_82543GC_COPPER 0x1004 ++#define E1000_DEV_ID_82544EI_COPPER 0x1008 ++#define E1000_DEV_ID_82544EI_FIBER 0x1009 ++#define E1000_DEV_ID_82544GC_COPPER 0x100C ++#define E1000_DEV_ID_82544GC_LOM 0x100D ++#define E1000_DEV_ID_82540EM 0x100E ++#define E1000_DEV_ID_82540EM_LOM 0x1015 ++#define E1000_DEV_ID_82540EP_LOM 0x1016 ++#define E1000_DEV_ID_82540EP 0x1017 ++#define E1000_DEV_ID_82540EP_LP 0x101E ++#define E1000_DEV_ID_82545EM_COPPER 0x100F ++#define E1000_DEV_ID_82545EM_FIBER 0x1011 ++#define E1000_DEV_ID_82545GM_COPPER 0x1026 ++#define E1000_DEV_ID_82545GM_FIBER 0x1027 ++#define E1000_DEV_ID_82545GM_SERDES 0x1028 ++#define E1000_DEV_ID_82546EB_COPPER 0x1010 ++#define E1000_DEV_ID_82546EB_FIBER 0x1012 ++#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D ++#define E1000_DEV_ID_82546GB_COPPER 0x1079 ++#define E1000_DEV_ID_82546GB_FIBER 0x107A ++#define E1000_DEV_ID_82546GB_SERDES 0x107B ++#define E1000_DEV_ID_82546GB_PCIE 0x108A ++#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 ++#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 ++#define E1000_DEV_ID_82541EI 0x1013 ++#define E1000_DEV_ID_82541EI_MOBILE 0x1018 ++#define E1000_DEV_ID_82541ER_LOM 0x1014 ++#define E1000_DEV_ID_82541ER 0x1078 ++#define E1000_DEV_ID_82541GI 0x1076 ++#define E1000_DEV_ID_82541GI_LF 0x107C ++#define E1000_DEV_ID_82541GI_MOBILE 0x1077 ++#define E1000_DEV_ID_82547EI 0x1019 ++#define E1000_DEV_ID_82547EI_MOBILE 0x101A ++#define E1000_DEV_ID_82547GI 0x1075 ++#define E1000_REVISION_0 0 ++#define E1000_REVISION_1 1 ++#define E1000_REVISION_2 2 ++#define E1000_REVISION_3 3 ++#define E1000_REVISION_4 4 + +-/* Enumerated types specific to the e1000 hardware */ +-/* Media Access Controlers */ +-typedef enum { +- e1000_undefined = 0, +- e1000_82542_rev2_0, +- e1000_82542_rev2_1, +- e1000_82543, +- e1000_82544, +- e1000_82540, +- e1000_82545, +- e1000_82545_rev_3, +- e1000_82546, +- e1000_82546_rev_3, +- e1000_82541, +- e1000_82541_rev_2, +- e1000_82547, +- e1000_82547_rev_2, +- e1000_82571, +- e1000_82572, +- e1000_82573, +- e1000_80003es2lan, +- e1000_ich8lan, +- e1000_num_macs +-} e1000_mac_type; ++#define E1000_FUNC_0 0 ++#define E1000_FUNC_1 1 + +-typedef enum { +- e1000_eeprom_uninitialized = 0, +- e1000_eeprom_spi, +- e1000_eeprom_microwire, +- e1000_eeprom_flash, +- e1000_eeprom_ich8, +- e1000_eeprom_none, /* No NVM support */ +- e1000_num_eeprom_types +-} e1000_eeprom_type; ++#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 ++#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 + +-/* Media Types */ +-typedef enum { +- e1000_media_type_copper = 0, +- e1000_media_type_fiber = 1, +- e1000_media_type_internal_serdes = 2, +- e1000_num_media_types +-} e1000_media_type; +- +-typedef enum { +- e1000_10_half = 0, +- e1000_10_full = 1, +- e1000_100_half = 2, +- e1000_100_full = 3 +-} e1000_speed_duplex_type; +- +-/* Flow Control Settings */ +-typedef enum { +- E1000_FC_NONE = 0, +- E1000_FC_RX_PAUSE = 1, +- E1000_FC_TX_PAUSE = 2, +- E1000_FC_FULL = 3, +- E1000_FC_DEFAULT = 0xFF +-} e1000_fc_type; +- +-struct e1000_shadow_ram { +- u16 eeprom_word; +- bool modified; ++enum e1000_mac_type { ++ e1000_undefined = 0, ++ e1000_82542, ++ e1000_82543, ++ e1000_82544, ++ e1000_82540, ++ e1000_82545, ++ e1000_82545_rev_3, ++ e1000_82546, ++ e1000_82546_rev_3, ++ e1000_82541, ++ e1000_82541_rev_2, ++ e1000_82547, ++ e1000_82547_rev_2, ++ e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ + }; + +-/* PCI bus types */ +-typedef enum { +- e1000_bus_type_unknown = 0, +- e1000_bus_type_pci, +- e1000_bus_type_pcix, +- e1000_bus_type_pci_express, +- e1000_bus_type_reserved +-} e1000_bus_type; +- +-/* PCI bus speeds */ +-typedef enum { +- e1000_bus_speed_unknown = 0, +- e1000_bus_speed_33, +- e1000_bus_speed_66, +- e1000_bus_speed_100, +- e1000_bus_speed_120, +- e1000_bus_speed_133, +- e1000_bus_speed_2500, +- e1000_bus_speed_reserved +-} e1000_bus_speed; +- +-/* PCI bus widths */ +-typedef enum { +- e1000_bus_width_unknown = 0, +- /* These PCIe values should literally match the possible return values +- * from config space */ +- e1000_bus_width_pciex_1 = 1, +- e1000_bus_width_pciex_2 = 2, +- e1000_bus_width_pciex_4 = 4, +- e1000_bus_width_32, +- e1000_bus_width_64, +- e1000_bus_width_reserved +-} e1000_bus_width; +- +-/* PHY status info structure and supporting enums */ +-typedef enum { +- e1000_cable_length_50 = 0, +- e1000_cable_length_50_80, +- e1000_cable_length_80_110, +- e1000_cable_length_110_140, +- e1000_cable_length_140, +- e1000_cable_length_undefined = 0xFF +-} e1000_cable_length; +- +-typedef enum { +- e1000_gg_cable_length_60 = 0, +- e1000_gg_cable_length_60_115 = 1, +- e1000_gg_cable_length_115_150 = 2, +- e1000_gg_cable_length_150 = 4 +-} e1000_gg_cable_length; +- +-typedef enum { +- e1000_igp_cable_length_10 = 10, +- e1000_igp_cable_length_20 = 20, +- e1000_igp_cable_length_30 = 30, +- e1000_igp_cable_length_40 = 40, +- e1000_igp_cable_length_50 = 50, +- e1000_igp_cable_length_60 = 60, +- e1000_igp_cable_length_70 = 70, +- e1000_igp_cable_length_80 = 80, +- e1000_igp_cable_length_90 = 90, +- e1000_igp_cable_length_100 = 100, +- e1000_igp_cable_length_110 = 110, +- e1000_igp_cable_length_115 = 115, +- e1000_igp_cable_length_120 = 120, +- e1000_igp_cable_length_130 = 130, +- e1000_igp_cable_length_140 = 140, +- e1000_igp_cable_length_150 = 150, +- e1000_igp_cable_length_160 = 160, +- e1000_igp_cable_length_170 = 170, +- e1000_igp_cable_length_180 = 180 +-} e1000_igp_cable_length; +- +-typedef enum { +- e1000_10bt_ext_dist_enable_normal = 0, +- e1000_10bt_ext_dist_enable_lower, +- e1000_10bt_ext_dist_enable_undefined = 0xFF +-} e1000_10bt_ext_dist_enable; +- +-typedef enum { +- e1000_rev_polarity_normal = 0, +- e1000_rev_polarity_reversed, +- e1000_rev_polarity_undefined = 0xFF +-} e1000_rev_polarity; +- +-typedef enum { +- e1000_downshift_normal = 0, +- e1000_downshift_activated, +- e1000_downshift_undefined = 0xFF +-} e1000_downshift; +- +-typedef enum { +- e1000_smart_speed_default = 0, +- e1000_smart_speed_on, +- e1000_smart_speed_off +-} e1000_smart_speed; +- +-typedef enum { +- e1000_polarity_reversal_enabled = 0, +- e1000_polarity_reversal_disabled, +- e1000_polarity_reversal_undefined = 0xFF +-} e1000_polarity_reversal; +- +-typedef enum { +- e1000_auto_x_mode_manual_mdi = 0, +- e1000_auto_x_mode_manual_mdix, +- e1000_auto_x_mode_auto1, +- e1000_auto_x_mode_auto2, +- e1000_auto_x_mode_undefined = 0xFF +-} e1000_auto_x_mode; +- +-typedef enum { +- e1000_1000t_rx_status_not_ok = 0, +- e1000_1000t_rx_status_ok, +- e1000_1000t_rx_status_undefined = 0xFF +-} e1000_1000t_rx_status; +- +-typedef enum { +- e1000_phy_m88 = 0, +- e1000_phy_igp, +- e1000_phy_igp_2, +- e1000_phy_gg82563, +- e1000_phy_igp_3, +- e1000_phy_ife, +- e1000_phy_undefined = 0xFF +-} e1000_phy_type; +- +-typedef enum { +- e1000_ms_hw_default = 0, +- e1000_ms_force_master, +- e1000_ms_force_slave, +- e1000_ms_auto +-} e1000_ms_type; +- +-typedef enum { +- e1000_ffe_config_enabled = 0, +- e1000_ffe_config_active, +- e1000_ffe_config_blocked +-} e1000_ffe_config; +- +-typedef enum { +- e1000_dsp_config_disabled = 0, +- e1000_dsp_config_enabled, +- e1000_dsp_config_activated, +- e1000_dsp_config_undefined = 0xFF +-} e1000_dsp_config; +- +-struct e1000_phy_info { +- e1000_cable_length cable_length; +- e1000_10bt_ext_dist_enable extended_10bt_distance; +- e1000_rev_polarity cable_polarity; +- e1000_downshift downshift; +- e1000_polarity_reversal polarity_correction; +- e1000_auto_x_mode mdix_mode; +- e1000_1000t_rx_status local_rx; +- e1000_1000t_rx_status remote_rx; ++enum e1000_media_type { ++ e1000_media_type_unknown = 0, ++ e1000_media_type_copper = 1, ++ e1000_media_type_fiber = 2, ++ e1000_media_type_internal_serdes = 3, ++ e1000_num_media_types + }; + +-struct e1000_phy_stats { +- u32 idle_errors; +- u32 receive_errors; ++enum e1000_nvm_type { ++ e1000_nvm_unknown = 0, ++ e1000_nvm_none, ++ e1000_nvm_eeprom_spi, ++ e1000_nvm_eeprom_microwire, ++ e1000_nvm_flash_hw, ++ e1000_nvm_flash_sw + }; + +-struct e1000_eeprom_info { +- e1000_eeprom_type type; +- u16 word_size; +- u16 opcode_bits; +- u16 address_bits; +- u16 delay_usec; +- u16 page_size; +- bool use_eerd; +- bool use_eewr; ++enum e1000_nvm_override { ++ e1000_nvm_override_none = 0, ++ e1000_nvm_override_spi_small, ++ e1000_nvm_override_spi_large, ++ e1000_nvm_override_microwire_small, ++ e1000_nvm_override_microwire_large + }; + +-/* Flex ASF Information */ +-#define E1000_HOST_IF_MAX_SIZE 2048 +- +-typedef enum { +- e1000_byte_align = 0, +- e1000_word_align = 1, +- e1000_dword_align = 2 +-} e1000_align_type; +- +- +- +-/* Error Codes */ +-#define E1000_SUCCESS 0 +-#define E1000_ERR_EEPROM 1 +-#define E1000_ERR_PHY 2 +-#define E1000_ERR_CONFIG 3 +-#define E1000_ERR_PARAM 4 +-#define E1000_ERR_MAC_TYPE 5 +-#define E1000_ERR_PHY_TYPE 6 +-#define E1000_ERR_RESET 9 +-#define E1000_ERR_MASTER_REQUESTS_PENDING 10 +-#define E1000_ERR_HOST_INTERFACE_COMMAND 11 +-#define E1000_BLK_PHY_RESET 12 +-#define E1000_ERR_SWFW_SYNC 13 +- +-#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \ +- (((_value) & 0xff00) >> 8)) +- +-/* Function prototypes */ +-/* Initialization */ +-s32 e1000_reset_hw(struct e1000_hw *hw); +-s32 e1000_init_hw(struct e1000_hw *hw); +-s32 e1000_set_mac_type(struct e1000_hw *hw); +-void e1000_set_media_type(struct e1000_hw *hw); +- +-/* Link Configuration */ +-s32 e1000_setup_link(struct e1000_hw *hw); +-s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); +-void e1000_config_collision_dist(struct e1000_hw *hw); +-s32 e1000_check_for_link(struct e1000_hw *hw); +-s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex); +-s32 e1000_force_mac_fc(struct e1000_hw *hw); +- +-/* PHY */ +-s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data); +-s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data); +-s32 e1000_phy_hw_reset(struct e1000_hw *hw); +-s32 e1000_phy_reset(struct e1000_hw *hw); +-s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); +-s32 e1000_validate_mdi_setting(struct e1000_hw *hw); +- +-void e1000_phy_powerdown_workaround(struct e1000_hw *hw); +- +-/* EEPROM Functions */ +-s32 e1000_init_eeprom_params(struct e1000_hw *hw); +- +-/* MNG HOST IF functions */ +-u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw); +- +-#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 +-#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ +- +-#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ +-#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ +-#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ +-#define E1000_MNG_IAMT_MODE 0x3 +-#define E1000_MNG_ICH_IAMT_MODE 0x2 +-#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ +- +-#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ +-#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */ +-#define E1000_VFTA_ENTRY_SHIFT 0x5 +-#define E1000_VFTA_ENTRY_MASK 0x7F +-#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F +- +-struct e1000_host_mng_command_header { +- u8 command_id; +- u8 checksum; +- u16 reserved1; +- u16 reserved2; +- u16 command_length; ++enum e1000_phy_type { ++ e1000_phy_unknown = 0, ++ e1000_phy_none, ++ e1000_phy_m88, ++ e1000_phy_igp, ++ e1000_phy_igp_2, ++ e1000_phy_gg82563, ++ e1000_phy_igp_3, ++ e1000_phy_ife, + }; + +-struct e1000_host_mng_command_info { +- struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ +- u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/ ++enum e1000_bus_type { ++ e1000_bus_type_unknown = 0, ++ e1000_bus_type_pci, ++ e1000_bus_type_pcix, ++ e1000_bus_type_pci_express, ++ e1000_bus_type_reserved + }; +-#ifdef __BIG_ENDIAN +-struct e1000_host_mng_dhcp_cookie{ +- u32 signature; +- u16 vlan_id; +- u8 reserved0; +- u8 status; +- u32 reserved1; +- u8 checksum; +- u8 reserved3; +- u16 reserved2; ++ ++enum e1000_bus_speed { ++ e1000_bus_speed_unknown = 0, ++ e1000_bus_speed_33, ++ e1000_bus_speed_66, ++ e1000_bus_speed_100, ++ e1000_bus_speed_120, ++ e1000_bus_speed_133, ++ e1000_bus_speed_2500, ++ e1000_bus_speed_5000, ++ e1000_bus_speed_reserved + }; +-#else +-struct e1000_host_mng_dhcp_cookie{ +- u32 signature; +- u8 status; +- u8 reserved0; +- u16 vlan_id; +- u32 reserved1; +- u16 reserved2; +- u8 reserved3; +- u8 checksum; ++ ++enum e1000_bus_width { ++ e1000_bus_width_unknown = 0, ++ e1000_bus_width_pcie_x1, ++ e1000_bus_width_pcie_x2, ++ e1000_bus_width_pcie_x4 = 4, ++ e1000_bus_width_pcie_x8 = 8, ++ e1000_bus_width_32, ++ e1000_bus_width_64, ++ e1000_bus_width_reserved + }; +-#endif + +-s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, +- u16 length); +-bool e1000_check_mng_mode(struct e1000_hw *hw); +-bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); +-s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data); +-s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw); +-s32 e1000_update_eeprom_checksum(struct e1000_hw *hw); +-s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data); +-s32 e1000_read_mac_addr(struct e1000_hw * hw); ++enum e1000_1000t_rx_status { ++ e1000_1000t_rx_status_not_ok = 0, ++ e1000_1000t_rx_status_ok, ++ e1000_1000t_rx_status_undefined = 0xFF ++}; + +-/* Filters (multicast, vlan, receive) */ +-u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr); +-void e1000_mta_set(struct e1000_hw *hw, u32 hash_value); +-void e1000_rar_set(struct e1000_hw *hw, u8 * mc_addr, u32 rar_index); +-void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value); ++enum e1000_rev_polarity { ++ e1000_rev_polarity_normal = 0, ++ e1000_rev_polarity_reversed, ++ e1000_rev_polarity_undefined = 0xFF ++}; + +-/* LED functions */ +-s32 e1000_setup_led(struct e1000_hw *hw); +-s32 e1000_cleanup_led(struct e1000_hw *hw); +-s32 e1000_led_on(struct e1000_hw *hw); +-s32 e1000_led_off(struct e1000_hw *hw); +-s32 e1000_blink_led_start(struct e1000_hw *hw); ++enum e1000_fc_mode { ++ e1000_fc_none = 0, ++ e1000_fc_rx_pause, ++ e1000_fc_tx_pause, ++ e1000_fc_full, ++ e1000_fc_default = 0xFF ++}; + +-/* Adaptive IFS Functions */ ++enum e1000_ffe_config { ++ e1000_ffe_config_enabled = 0, ++ e1000_ffe_config_active, ++ e1000_ffe_config_blocked ++}; + +-/* Everything else */ +-void e1000_reset_adaptive(struct e1000_hw *hw); +-void e1000_update_adaptive(struct e1000_hw *hw); +-void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, u32 frame_len, u8 * mac_addr); +-void e1000_get_bus_info(struct e1000_hw *hw); +-void e1000_pci_set_mwi(struct e1000_hw *hw); +-void e1000_pci_clear_mwi(struct e1000_hw *hw); +-s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); +-void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc); +-int e1000_pcix_get_mmrbc(struct e1000_hw *hw); +-/* Port I/O is only supported on 82544 and newer */ +-void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value); +-s32 e1000_disable_pciex_master(struct e1000_hw *hw); +-s32 e1000_check_phy_reset_block(struct e1000_hw *hw); ++enum e1000_dsp_config { ++ e1000_dsp_config_disabled = 0, ++ e1000_dsp_config_enabled, ++ e1000_dsp_config_activated, ++ e1000_dsp_config_undefined = 0xFF ++}; + ++enum e1000_ms_type { ++ e1000_ms_hw_default = 0, ++ e1000_ms_force_master, ++ e1000_ms_force_slave, ++ e1000_ms_auto ++}; + +-#define E1000_READ_REG_IO(a, reg) \ +- e1000_read_reg_io((a), E1000_##reg) +-#define E1000_WRITE_REG_IO(a, reg, val) \ +- e1000_write_reg_io((a), E1000_##reg, val) ++enum e1000_smart_speed { ++ e1000_smart_speed_default = 0, ++ e1000_smart_speed_on, ++ e1000_smart_speed_off ++}; + +-/* PCI Device IDs */ +-#define E1000_DEV_ID_82542 0x1000 +-#define E1000_DEV_ID_82543GC_FIBER 0x1001 +-#define E1000_DEV_ID_82543GC_COPPER 0x1004 +-#define E1000_DEV_ID_82544EI_COPPER 0x1008 +-#define E1000_DEV_ID_82544EI_FIBER 0x1009 +-#define E1000_DEV_ID_82544GC_COPPER 0x100C +-#define E1000_DEV_ID_82544GC_LOM 0x100D +-#define E1000_DEV_ID_82540EM 0x100E +-#define E1000_DEV_ID_82540EM_LOM 0x1015 +-#define E1000_DEV_ID_82540EP_LOM 0x1016 +-#define E1000_DEV_ID_82540EP 0x1017 +-#define E1000_DEV_ID_82540EP_LP 0x101E +-#define E1000_DEV_ID_82545EM_COPPER 0x100F +-#define E1000_DEV_ID_82545EM_FIBER 0x1011 +-#define E1000_DEV_ID_82545GM_COPPER 0x1026 +-#define E1000_DEV_ID_82545GM_FIBER 0x1027 +-#define E1000_DEV_ID_82545GM_SERDES 0x1028 +-#define E1000_DEV_ID_82546EB_COPPER 0x1010 +-#define E1000_DEV_ID_82546EB_FIBER 0x1012 +-#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D +-#define E1000_DEV_ID_82541EI 0x1013 +-#define E1000_DEV_ID_82541EI_MOBILE 0x1018 +-#define E1000_DEV_ID_82541ER_LOM 0x1014 +-#define E1000_DEV_ID_82541ER 0x1078 +-#define E1000_DEV_ID_82547GI 0x1075 +-#define E1000_DEV_ID_82541GI 0x1076 +-#define E1000_DEV_ID_82541GI_MOBILE 0x1077 +-#define E1000_DEV_ID_82541GI_LF 0x107C +-#define E1000_DEV_ID_82546GB_COPPER 0x1079 +-#define E1000_DEV_ID_82546GB_FIBER 0x107A +-#define E1000_DEV_ID_82546GB_SERDES 0x107B +-#define E1000_DEV_ID_82546GB_PCIE 0x108A +-#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 +-#define E1000_DEV_ID_82547EI 0x1019 +-#define E1000_DEV_ID_82547EI_MOBILE 0x101A +-#define E1000_DEV_ID_82571EB_COPPER 0x105E +-#define E1000_DEV_ID_82571EB_FIBER 0x105F +-#define E1000_DEV_ID_82571EB_SERDES 0x1060 +-#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 +-#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 +-#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 +-#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC +-#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 +-#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA +-#define E1000_DEV_ID_82572EI_COPPER 0x107D +-#define E1000_DEV_ID_82572EI_FIBER 0x107E +-#define E1000_DEV_ID_82572EI_SERDES 0x107F +-#define E1000_DEV_ID_82572EI 0x10B9 +-#define E1000_DEV_ID_82573E 0x108B +-#define E1000_DEV_ID_82573E_IAMT 0x108C +-#define E1000_DEV_ID_82573L 0x109A +-#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 +-#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 +-#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 +-#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA +-#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB +- +-#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 +-#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A +-#define E1000_DEV_ID_ICH8_IGP_C 0x104B +-#define E1000_DEV_ID_ICH8_IFE 0x104C +-#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 +-#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 +-#define E1000_DEV_ID_ICH8_IGP_M 0x104D +- +- +-#define NODE_ADDRESS_SIZE 6 +-#define ETH_LENGTH_OF_ADDRESS 6 +- +-/* MAC decode size is 128K - This is the size of BAR0 */ +-#define MAC_DECODE_SIZE (128 * 1024) +- +-#define E1000_82542_2_0_REV_ID 2 +-#define E1000_82542_2_1_REV_ID 3 +-#define E1000_REVISION_0 0 +-#define E1000_REVISION_1 1 +-#define E1000_REVISION_2 2 +-#define E1000_REVISION_3 3 +- +-#define SPEED_10 10 +-#define SPEED_100 100 +-#define SPEED_1000 1000 +-#define HALF_DUPLEX 1 +-#define FULL_DUPLEX 2 +- +-/* The sizes (in bytes) of a ethernet packet */ +-#define ENET_HEADER_SIZE 14 +-#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ +-#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ +-#define ETHERNET_FCS_SIZE 4 +-#define MAXIMUM_ETHERNET_PACKET_SIZE \ +- (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) +-#define MINIMUM_ETHERNET_PACKET_SIZE \ +- (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) +-#define CRC_LENGTH ETHERNET_FCS_SIZE +-#define MAX_JUMBO_FRAME_SIZE 0x3F00 +- +- +-/* 802.1q VLAN Packet Sizes */ +-#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ +- +-/* Ethertype field values */ +-#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ +-#define ETHERNET_IP_TYPE 0x0800 /* IP packets */ +-#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ +- +-/* Packet Header defines */ +-#define IP_PROTOCOL_TCP 6 +-#define IP_PROTOCOL_UDP 0x11 +- +-/* This defines the bits that are set in the Interrupt Mask +- * Set/Read Register. Each bit is documented below: +- * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) +- * o RXSEQ = Receive Sequence Error +- */ +-#define POLL_IMS_ENABLE_MASK ( \ +- E1000_IMS_RXDMT0 | \ +- E1000_IMS_RXSEQ) +- +-/* This defines the bits that are set in the Interrupt Mask +- * Set/Read Register. Each bit is documented below: +- * o RXT0 = Receiver Timer Interrupt (ring 0) +- * o TXDW = Transmit Descriptor Written Back +- * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) +- * o RXSEQ = Receive Sequence Error +- * o LSC = Link Status Change +- */ +-#define IMS_ENABLE_MASK ( \ +- E1000_IMS_RXT0 | \ +- E1000_IMS_TXDW | \ +- E1000_IMS_RXDMT0 | \ +- E1000_IMS_RXSEQ | \ +- E1000_IMS_LSC) +- +-/* Additional interrupts need to be handled for e1000_ich8lan: +- DSW = The FW changed the status of the DISSW bit in FWSM +- PHYINT = The LAN connected device generates an interrupt +- EPRST = Manageability reset event */ +-#define IMS_ICH8LAN_ENABLE_MASK (\ +- E1000_IMS_DSW | \ +- E1000_IMS_PHYINT | \ +- E1000_IMS_EPRST) +- +-/* Number of high/low register pairs in the RAR. The RAR (Receive Address +- * Registers) holds the directed and multicast addresses that we monitor. We +- * reserve one of these spots for our directed address, allowing us room for +- * E1000_RAR_ENTRIES - 1 multicast addresses. +- */ +-#define E1000_RAR_ENTRIES 15 +- +-#define E1000_RAR_ENTRIES_ICH8LAN 6 +- +-#define MIN_NUMBER_OF_DESCRIPTORS 8 +-#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 ++enum e1000_serdes_link_state { ++ e1000_serdes_link_down = 0, ++ e1000_serdes_link_autoneg_progress, ++ e1000_serdes_link_autoneg_complete, ++ e1000_serdes_link_forced_up ++}; + + /* Receive Descriptor */ + struct e1000_rx_desc { +- __le64 buffer_addr; /* Address of the descriptor's data buffer */ +- __le16 length; /* Length of data DMAed into data buffer */ +- __le16 csum; /* Packet checksum */ +- u8 status; /* Descriptor status */ +- u8 errors; /* Descriptor Errors */ +- __le16 special; ++ __le64 buffer_addr; /* Address of the descriptor's data buffer */ ++ __le16 length; /* Length of data DMAed into data buffer */ ++ __le16 csum; /* Packet checksum */ ++ u8 status; /* Descriptor status */ ++ u8 errors; /* Descriptor Errors */ ++ __le16 special; + }; + + /* Receive Descriptor - Extended */ + union e1000_rx_desc_extended { +- struct { +- __le64 buffer_addr; +- __le64 reserved; +- } read; +- struct { +- struct { +- __le32 mrq; /* Multiple Rx Queues */ +- union { +- __le32 rss; /* RSS Hash */ +- struct { +- __le16 ip_id; /* IP id */ +- __le16 csum; /* Packet Checksum */ +- } csum_ip; +- } hi_dword; +- } lower; +- struct { +- __le32 status_error; /* ext status/error */ +- __le16 length; +- __le16 vlan; /* VLAN tag */ +- } upper; +- } wb; /* writeback */ ++ struct { ++ __le64 buffer_addr; ++ __le64 reserved; ++ } read; ++ struct { ++ struct { ++ __le32 mrq; /* Multiple Rx Queues */ ++ union { ++ __le32 rss; /* RSS Hash */ ++ struct { ++ __le16 ip_id; /* IP id */ ++ __le16 csum; /* Packet Checksum */ ++ } csum_ip; ++ } hi_dword; ++ } lower; ++ struct { ++ __le32 status_error; /* ext status/error */ ++ __le16 length; ++ __le16 vlan; /* VLAN tag */ ++ } upper; ++ } wb; /* writeback */ + }; + + #define MAX_PS_BUFFERS 4 + /* Receive Descriptor - Packet Split */ + union e1000_rx_desc_packet_split { +- struct { +- /* one buffer for protocol header(s), three data buffers */ +- __le64 buffer_addr[MAX_PS_BUFFERS]; +- } read; +- struct { +- struct { +- __le32 mrq; /* Multiple Rx Queues */ +- union { +- __le32 rss; /* RSS Hash */ +- struct { +- __le16 ip_id; /* IP id */ +- __le16 csum; /* Packet Checksum */ +- } csum_ip; +- } hi_dword; +- } lower; +- struct { +- __le32 status_error; /* ext status/error */ +- __le16 length0; /* length of buffer 0 */ +- __le16 vlan; /* VLAN tag */ +- } middle; +- struct { +- __le16 header_status; +- __le16 length[3]; /* length of buffers 1-3 */ +- } upper; +- __le64 reserved; +- } wb; /* writeback */ ++ struct { ++ /* one buffer for protocol header(s), three data buffers */ ++ __le64 buffer_addr[MAX_PS_BUFFERS]; ++ } read; ++ struct { ++ struct { ++ __le32 mrq; /* Multiple Rx Queues */ ++ union { ++ __le32 rss; /* RSS Hash */ ++ struct { ++ __le16 ip_id; /* IP id */ ++ __le16 csum; /* Packet Checksum */ ++ } csum_ip; ++ } hi_dword; ++ } lower; ++ struct { ++ __le32 status_error; /* ext status/error */ ++ __le16 length0; /* length of buffer 0 */ ++ __le16 vlan; /* VLAN tag */ ++ } middle; ++ struct { ++ __le16 header_status; ++ __le16 length[3]; /* length of buffers 1-3 */ ++ } upper; ++ __le64 reserved; ++ } wb; /* writeback */ + }; +- +-/* Receive Decriptor bit definitions */ +-#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ +-#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ +-#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ +-#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ +-#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ +-#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ +-#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ +-#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ +-#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ +-#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ +-#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ +-#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ +-#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ +-#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ +-#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ +-#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ +-#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ +-#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ +-#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ +-#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ +-#define E1000_RXD_SPC_PRI_SHIFT 13 +-#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ +-#define E1000_RXD_SPC_CFI_SHIFT 12 +- +-#define E1000_RXDEXT_STATERR_CE 0x01000000 +-#define E1000_RXDEXT_STATERR_SE 0x02000000 +-#define E1000_RXDEXT_STATERR_SEQ 0x04000000 +-#define E1000_RXDEXT_STATERR_CXE 0x10000000 +-#define E1000_RXDEXT_STATERR_TCPE 0x20000000 +-#define E1000_RXDEXT_STATERR_IPE 0x40000000 +-#define E1000_RXDEXT_STATERR_RXE 0x80000000 +- +-#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 +-#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF +- +-/* mask to determine if packets should be dropped due to frame errors */ +-#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ +- E1000_RXD_ERR_CE | \ +- E1000_RXD_ERR_SE | \ +- E1000_RXD_ERR_SEQ | \ +- E1000_RXD_ERR_CXE | \ +- E1000_RXD_ERR_RXE) +- +- +-/* Same mask, but for extended and packet split descriptors */ +-#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ +- E1000_RXDEXT_STATERR_CE | \ +- E1000_RXDEXT_STATERR_SE | \ +- E1000_RXDEXT_STATERR_SEQ | \ +- E1000_RXDEXT_STATERR_CXE | \ +- E1000_RXDEXT_STATERR_RXE) +- + + /* Transmit Descriptor */ + struct e1000_tx_desc { +- __le64 buffer_addr; /* Address of the descriptor's data buffer */ +- union { +- __le32 data; +- struct { +- __le16 length; /* Data buffer length */ +- u8 cso; /* Checksum offset */ +- u8 cmd; /* Descriptor control */ +- } flags; +- } lower; +- union { +- __le32 data; +- struct { +- u8 status; /* Descriptor status */ +- u8 css; /* Checksum start */ +- __le16 special; +- } fields; +- } upper; ++ __le64 buffer_addr; /* Address of the descriptor's data buffer */ ++ union { ++ __le32 data; ++ struct { ++ __le16 length; /* Data buffer length */ ++ u8 cso; /* Checksum offset */ ++ u8 cmd; /* Descriptor control */ ++ } flags; ++ } lower; ++ union { ++ __le32 data; ++ struct { ++ u8 status; /* Descriptor status */ ++ u8 css; /* Checksum start */ ++ __le16 special; ++ } fields; ++ } upper; + }; +- +-/* Transmit Descriptor bit definitions */ +-#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ +-#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ +-#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ +-#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ +-#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ +-#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ +-#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ +-#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ +-#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ +-#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ +-#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ +-#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ +-#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ +-#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ +-#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ +-#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ +-#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ +-#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ +-#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ +-#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ + + /* Offload Context Descriptor */ + struct e1000_context_desc { +- union { +- __le32 ip_config; +- struct { +- u8 ipcss; /* IP checksum start */ +- u8 ipcso; /* IP checksum offset */ +- __le16 ipcse; /* IP checksum end */ +- } ip_fields; +- } lower_setup; +- union { +- __le32 tcp_config; +- struct { +- u8 tucss; /* TCP checksum start */ +- u8 tucso; /* TCP checksum offset */ +- __le16 tucse; /* TCP checksum end */ +- } tcp_fields; +- } upper_setup; +- __le32 cmd_and_length; /* */ +- union { +- __le32 data; +- struct { +- u8 status; /* Descriptor status */ +- u8 hdr_len; /* Header length */ +- __le16 mss; /* Maximum segment size */ +- } fields; +- } tcp_seg_setup; ++ union { ++ __le32 ip_config; ++ struct { ++ u8 ipcss; /* IP checksum start */ ++ u8 ipcso; /* IP checksum offset */ ++ __le16 ipcse; /* IP checksum end */ ++ } ip_fields; ++ } lower_setup; ++ union { ++ __le32 tcp_config; ++ struct { ++ u8 tucss; /* TCP checksum start */ ++ u8 tucso; /* TCP checksum offset */ ++ __le16 tucse; /* TCP checksum end */ ++ } tcp_fields; ++ } upper_setup; ++ __le32 cmd_and_length; ++ union { ++ __le32 data; ++ struct { ++ u8 status; /* Descriptor status */ ++ u8 hdr_len; /* Header length */ ++ __le16 mss; /* Maximum segment size */ ++ } fields; ++ } tcp_seg_setup; + }; + + /* Offload data descriptor */ + struct e1000_data_desc { +- __le64 buffer_addr; /* Address of the descriptor's buffer address */ +- union { +- __le32 data; +- struct { +- __le16 length; /* Data buffer length */ +- u8 typ_len_ext; /* */ +- u8 cmd; /* */ +- } flags; +- } lower; +- union { +- __le32 data; +- struct { +- u8 status; /* Descriptor status */ +- u8 popts; /* Packet Options */ +- __le16 special; /* */ +- } fields; +- } upper; ++ __le64 buffer_addr; /* Address of the descriptor's buffer address */ ++ union { ++ __le32 data; ++ struct { ++ __le16 length; /* Data buffer length */ ++ u8 typ_len_ext; ++ u8 cmd; ++ } flags; ++ } lower; ++ union { ++ __le32 data; ++ struct { ++ u8 status; /* Descriptor status */ ++ u8 popts; /* Packet Options */ ++ __le16 special; ++ } fields; ++ } upper; + }; +- +-/* Filters */ +-#define E1000_NUM_UNICAST 16 /* Unicast filter entries */ +-#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ +-#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ +- +-#define E1000_NUM_UNICAST_ICH8LAN 7 +-#define E1000_MC_TBL_SIZE_ICH8LAN 32 +- +- +-/* Receive Address Register */ +-struct e1000_rar { +- volatile __le32 low; /* receive address low */ +- volatile __le32 high; /* receive address high */ +-}; +- +-/* Number of entries in the Multicast Table Array (MTA). */ +-#define E1000_NUM_MTA_REGISTERS 128 +-#define E1000_NUM_MTA_REGISTERS_ICH8LAN 32 +- +-/* IPv4 Address Table Entry */ +-struct e1000_ipv4_at_entry { +- volatile u32 ipv4_addr; /* IP Address (RW) */ +- volatile u32 reserved; +-}; +- +-/* Four wakeup IP addresses are supported */ +-#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 +-#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX +-#define E1000_IP4AT_SIZE_ICH8LAN 3 +-#define E1000_IP6AT_SIZE 1 +- +-/* IPv6 Address Table Entry */ +-struct e1000_ipv6_at_entry { +- volatile u8 ipv6_addr[16]; +-}; +- +-/* Flexible Filter Length Table Entry */ +-struct e1000_fflt_entry { +- volatile u32 length; /* Flexible Filter Length (RW) */ +- volatile u32 reserved; +-}; +- +-/* Flexible Filter Mask Table Entry */ +-struct e1000_ffmt_entry { +- volatile u32 mask; /* Flexible Filter Mask (RW) */ +- volatile u32 reserved; +-}; +- +-/* Flexible Filter Value Table Entry */ +-struct e1000_ffvt_entry { +- volatile u32 value; /* Flexible Filter Value (RW) */ +- volatile u32 reserved; +-}; +- +-/* Four Flexible Filters are supported */ +-#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 +- +-/* Each Flexible Filter is at most 128 (0x80) bytes in length */ +-#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 +- +-#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX +-#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX +-#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX +- +-#define E1000_DISABLE_SERDES_LOOPBACK 0x0400 +- +-/* Register Set. (82543, 82544) +- * +- * Registers are defined to be 32 bits and should be accessed as 32 bit values. +- * These registers are physically located on the NIC, but are mapped into the +- * host memory address space. +- * +- * RW - register is both readable and writable +- * RO - register is read only +- * WO - register is write only +- * R/clr - register is read only and is cleared when read +- * A - register array +- */ +-#define E1000_CTRL 0x00000 /* Device Control - RW */ +-#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ +-#define E1000_STATUS 0x00008 /* Device Status - RO */ +-#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ +-#define E1000_EERD 0x00014 /* EEPROM Read - RW */ +-#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ +-#define E1000_FLA 0x0001C /* Flash Access - RW */ +-#define E1000_MDIC 0x00020 /* MDI Control - RW */ +-#define E1000_SCTL 0x00024 /* SerDes Control - RW */ +-#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */ +-#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ +-#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ +-#define E1000_FCT 0x00030 /* Flow Control Type - RW */ +-#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ +-#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ +-#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ +-#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ +-#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ +-#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ +-#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ +-#define E1000_RCTL 0x00100 /* RX Control - RW */ +-#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ +-#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ +-#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ +-#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ +-#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ +-#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ +-#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ +-#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ +-#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ +-#define E1000_TCTL 0x00400 /* TX Control - RW */ +-#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ +-#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ +-#define E1000_TBT 0x00448 /* TX Burst Timer - RW */ +-#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ +-#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ +-#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ +-#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ +-#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ +-#define FEXTNVM_SW_CONFIG 0x0001 +-#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ +-#define E1000_PBS 0x01008 /* Packet Buffer Size */ +-#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ +-#define E1000_FLASH_UPDATES 1000 +-#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ +-#define E1000_FLASHT 0x01028 /* FLASH Timer Register */ +-#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ +-#define E1000_FLSWCTL 0x01030 /* FLASH control register */ +-#define E1000_FLSWDATA 0x01034 /* FLASH data register */ +-#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ +-#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ +-#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ +-#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ +-#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ +-#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ +-#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ +-#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ +-#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ +-#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ +-#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ +-#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ +-#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ +-#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ +-#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ +-#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ +-#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ +-#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ +-#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */ +-#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */ +-#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ +-#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ +-#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ +-#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ +-#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ +-#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ +-#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ +-#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ +-#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ +-#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ +-#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ +-#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ +-#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ +-#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ +-#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ +-#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ +-#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ +-#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ +-#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ +-#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ +-#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ +-#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ +-#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ +-#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ +-#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ +-#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ +-#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ +-#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ +-#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ +-#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ +-#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ +-#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ +-#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ +-#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ +-#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ +-#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ +-#define E1000_COLC 0x04028 /* Collision Count - R/clr */ +-#define E1000_DC 0x04030 /* Defer Count - R/clr */ +-#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ +-#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ +-#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ +-#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ +-#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ +-#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ +-#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ +-#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ +-#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ +-#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ +-#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ +-#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ +-#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ +-#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ +-#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ +-#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ +-#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ +-#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ +-#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ +-#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ +-#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ +-#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ +-#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ +-#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ +-#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ +-#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ +-#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ +-#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ +-#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ +-#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ +-#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ +-#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ +-#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ +-#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ +-#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ +-#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ +-#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ +-#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ +-#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ +-#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ +-#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ +-#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ +-#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ +-#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ +-#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ +-#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ +-#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ +-#define E1000_IAC 0x04100 /* Interrupt Assertion Count */ +-#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ +-#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ +-#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ +-#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ +-#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ +-#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ +-#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ +-#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ +-#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ +-#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ +-#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ +-#define E1000_RA 0x05400 /* Receive Address - RW Array */ +-#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ +-#define E1000_WUC 0x05800 /* Wakeup Control - RW */ +-#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ +-#define E1000_WUS 0x05810 /* Wakeup Status - RO */ +-#define E1000_MANC 0x05820 /* Management Control - RW */ +-#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ +-#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ +-#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ +-#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ +-#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ +-#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ +-#define E1000_HOST_IF 0x08800 /* Host Interface */ +-#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ +-#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ +- +-#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ +-#define E1000_MDPHYA 0x0003C /* PHY address - RW */ +-#define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */ +-#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ +- +-#define E1000_GCR 0x05B00 /* PCI-Ex Control */ +-#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ +-#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ +-#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ +-#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ +-#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ +-#define E1000_SWSM 0x05B50 /* SW Semaphore */ +-#define E1000_FWSM 0x05B54 /* FW Semaphore */ +-#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ +-#define E1000_HICR 0x08F00 /* Host Inteface Control */ +- +-/* RSS registers */ +-#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ +-#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ +-#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ +-#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ +-#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ +-#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ +-/* Register Set (82542) +- * +- * Some of the 82542 registers are located at different offsets than they are +- * in more current versions of the 8254x. Despite the difference in location, +- * the registers function in the same manner. +- */ +-#define E1000_82542_CTRL E1000_CTRL +-#define E1000_82542_CTRL_DUP E1000_CTRL_DUP +-#define E1000_82542_STATUS E1000_STATUS +-#define E1000_82542_EECD E1000_EECD +-#define E1000_82542_EERD E1000_EERD +-#define E1000_82542_CTRL_EXT E1000_CTRL_EXT +-#define E1000_82542_FLA E1000_FLA +-#define E1000_82542_MDIC E1000_MDIC +-#define E1000_82542_SCTL E1000_SCTL +-#define E1000_82542_FEXTNVM E1000_FEXTNVM +-#define E1000_82542_FCAL E1000_FCAL +-#define E1000_82542_FCAH E1000_FCAH +-#define E1000_82542_FCT E1000_FCT +-#define E1000_82542_VET E1000_VET +-#define E1000_82542_RA 0x00040 +-#define E1000_82542_ICR E1000_ICR +-#define E1000_82542_ITR E1000_ITR +-#define E1000_82542_ICS E1000_ICS +-#define E1000_82542_IMS E1000_IMS +-#define E1000_82542_IMC E1000_IMC +-#define E1000_82542_RCTL E1000_RCTL +-#define E1000_82542_RDTR 0x00108 +-#define E1000_82542_RDBAL 0x00110 +-#define E1000_82542_RDBAH 0x00114 +-#define E1000_82542_RDLEN 0x00118 +-#define E1000_82542_RDH 0x00120 +-#define E1000_82542_RDT 0x00128 +-#define E1000_82542_RDTR0 E1000_82542_RDTR +-#define E1000_82542_RDBAL0 E1000_82542_RDBAL +-#define E1000_82542_RDBAH0 E1000_82542_RDBAH +-#define E1000_82542_RDLEN0 E1000_82542_RDLEN +-#define E1000_82542_RDH0 E1000_82542_RDH +-#define E1000_82542_RDT0 E1000_82542_RDT +-#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication +- * RX Control - RW */ +-#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8)) +-#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */ +-#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */ +-#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */ +-#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */ +-#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */ +-#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */ +-#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */ +-#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */ +-#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */ +-#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */ +-#define E1000_82542_RDTR1 0x00130 +-#define E1000_82542_RDBAL1 0x00138 +-#define E1000_82542_RDBAH1 0x0013C +-#define E1000_82542_RDLEN1 0x00140 +-#define E1000_82542_RDH1 0x00148 +-#define E1000_82542_RDT1 0x00150 +-#define E1000_82542_FCRTH 0x00160 +-#define E1000_82542_FCRTL 0x00168 +-#define E1000_82542_FCTTV E1000_FCTTV +-#define E1000_82542_TXCW E1000_TXCW +-#define E1000_82542_RXCW E1000_RXCW +-#define E1000_82542_MTA 0x00200 +-#define E1000_82542_TCTL E1000_TCTL +-#define E1000_82542_TCTL_EXT E1000_TCTL_EXT +-#define E1000_82542_TIPG E1000_TIPG +-#define E1000_82542_TDBAL 0x00420 +-#define E1000_82542_TDBAH 0x00424 +-#define E1000_82542_TDLEN 0x00428 +-#define E1000_82542_TDH 0x00430 +-#define E1000_82542_TDT 0x00438 +-#define E1000_82542_TIDV 0x00440 +-#define E1000_82542_TBT E1000_TBT +-#define E1000_82542_AIT E1000_AIT +-#define E1000_82542_VFTA 0x00600 +-#define E1000_82542_LEDCTL E1000_LEDCTL +-#define E1000_82542_PBA E1000_PBA +-#define E1000_82542_PBS E1000_PBS +-#define E1000_82542_EEMNGCTL E1000_EEMNGCTL +-#define E1000_82542_EEARBC E1000_EEARBC +-#define E1000_82542_FLASHT E1000_FLASHT +-#define E1000_82542_EEWR E1000_EEWR +-#define E1000_82542_FLSWCTL E1000_FLSWCTL +-#define E1000_82542_FLSWDATA E1000_FLSWDATA +-#define E1000_82542_FLSWCNT E1000_FLSWCNT +-#define E1000_82542_FLOP E1000_FLOP +-#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL +-#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE +-#define E1000_82542_PHY_CTRL E1000_PHY_CTRL +-#define E1000_82542_ERT E1000_ERT +-#define E1000_82542_RXDCTL E1000_RXDCTL +-#define E1000_82542_RXDCTL1 E1000_RXDCTL1 +-#define E1000_82542_RADV E1000_RADV +-#define E1000_82542_RSRPD E1000_RSRPD +-#define E1000_82542_TXDMAC E1000_TXDMAC +-#define E1000_82542_KABGTXD E1000_KABGTXD +-#define E1000_82542_TDFHS E1000_TDFHS +-#define E1000_82542_TDFTS E1000_TDFTS +-#define E1000_82542_TDFPC E1000_TDFPC +-#define E1000_82542_TXDCTL E1000_TXDCTL +-#define E1000_82542_TADV E1000_TADV +-#define E1000_82542_TSPMT E1000_TSPMT +-#define E1000_82542_CRCERRS E1000_CRCERRS +-#define E1000_82542_ALGNERRC E1000_ALGNERRC +-#define E1000_82542_SYMERRS E1000_SYMERRS +-#define E1000_82542_RXERRC E1000_RXERRC +-#define E1000_82542_MPC E1000_MPC +-#define E1000_82542_SCC E1000_SCC +-#define E1000_82542_ECOL E1000_ECOL +-#define E1000_82542_MCC E1000_MCC +-#define E1000_82542_LATECOL E1000_LATECOL +-#define E1000_82542_COLC E1000_COLC +-#define E1000_82542_DC E1000_DC +-#define E1000_82542_TNCRS E1000_TNCRS +-#define E1000_82542_SEC E1000_SEC +-#define E1000_82542_CEXTERR E1000_CEXTERR +-#define E1000_82542_RLEC E1000_RLEC +-#define E1000_82542_XONRXC E1000_XONRXC +-#define E1000_82542_XONTXC E1000_XONTXC +-#define E1000_82542_XOFFRXC E1000_XOFFRXC +-#define E1000_82542_XOFFTXC E1000_XOFFTXC +-#define E1000_82542_FCRUC E1000_FCRUC +-#define E1000_82542_PRC64 E1000_PRC64 +-#define E1000_82542_PRC127 E1000_PRC127 +-#define E1000_82542_PRC255 E1000_PRC255 +-#define E1000_82542_PRC511 E1000_PRC511 +-#define E1000_82542_PRC1023 E1000_PRC1023 +-#define E1000_82542_PRC1522 E1000_PRC1522 +-#define E1000_82542_GPRC E1000_GPRC +-#define E1000_82542_BPRC E1000_BPRC +-#define E1000_82542_MPRC E1000_MPRC +-#define E1000_82542_GPTC E1000_GPTC +-#define E1000_82542_GORCL E1000_GORCL +-#define E1000_82542_GORCH E1000_GORCH +-#define E1000_82542_GOTCL E1000_GOTCL +-#define E1000_82542_GOTCH E1000_GOTCH +-#define E1000_82542_RNBC E1000_RNBC +-#define E1000_82542_RUC E1000_RUC +-#define E1000_82542_RFC E1000_RFC +-#define E1000_82542_ROC E1000_ROC +-#define E1000_82542_RJC E1000_RJC +-#define E1000_82542_MGTPRC E1000_MGTPRC +-#define E1000_82542_MGTPDC E1000_MGTPDC +-#define E1000_82542_MGTPTC E1000_MGTPTC +-#define E1000_82542_TORL E1000_TORL +-#define E1000_82542_TORH E1000_TORH +-#define E1000_82542_TOTL E1000_TOTL +-#define E1000_82542_TOTH E1000_TOTH +-#define E1000_82542_TPR E1000_TPR +-#define E1000_82542_TPT E1000_TPT +-#define E1000_82542_PTC64 E1000_PTC64 +-#define E1000_82542_PTC127 E1000_PTC127 +-#define E1000_82542_PTC255 E1000_PTC255 +-#define E1000_82542_PTC511 E1000_PTC511 +-#define E1000_82542_PTC1023 E1000_PTC1023 +-#define E1000_82542_PTC1522 E1000_PTC1522 +-#define E1000_82542_MPTC E1000_MPTC +-#define E1000_82542_BPTC E1000_BPTC +-#define E1000_82542_TSCTC E1000_TSCTC +-#define E1000_82542_TSCTFC E1000_TSCTFC +-#define E1000_82542_RXCSUM E1000_RXCSUM +-#define E1000_82542_WUC E1000_WUC +-#define E1000_82542_WUFC E1000_WUFC +-#define E1000_82542_WUS E1000_WUS +-#define E1000_82542_MANC E1000_MANC +-#define E1000_82542_IPAV E1000_IPAV +-#define E1000_82542_IP4AT E1000_IP4AT +-#define E1000_82542_IP6AT E1000_IP6AT +-#define E1000_82542_WUPL E1000_WUPL +-#define E1000_82542_WUPM E1000_WUPM +-#define E1000_82542_FFLT E1000_FFLT +-#define E1000_82542_TDFH 0x08010 +-#define E1000_82542_TDFT 0x08018 +-#define E1000_82542_FFMT E1000_FFMT +-#define E1000_82542_FFVT E1000_FFVT +-#define E1000_82542_HOST_IF E1000_HOST_IF +-#define E1000_82542_IAM E1000_IAM +-#define E1000_82542_EEMNGCTL E1000_EEMNGCTL +-#define E1000_82542_PSRCTL E1000_PSRCTL +-#define E1000_82542_RAID E1000_RAID +-#define E1000_82542_TARC0 E1000_TARC0 +-#define E1000_82542_TDBAL1 E1000_TDBAL1 +-#define E1000_82542_TDBAH1 E1000_TDBAH1 +-#define E1000_82542_TDLEN1 E1000_TDLEN1 +-#define E1000_82542_TDH1 E1000_TDH1 +-#define E1000_82542_TDT1 E1000_TDT1 +-#define E1000_82542_TXDCTL1 E1000_TXDCTL1 +-#define E1000_82542_TARC1 E1000_TARC1 +-#define E1000_82542_RFCTL E1000_RFCTL +-#define E1000_82542_GCR E1000_GCR +-#define E1000_82542_GSCL_1 E1000_GSCL_1 +-#define E1000_82542_GSCL_2 E1000_GSCL_2 +-#define E1000_82542_GSCL_3 E1000_GSCL_3 +-#define E1000_82542_GSCL_4 E1000_GSCL_4 +-#define E1000_82542_FACTPS E1000_FACTPS +-#define E1000_82542_SWSM E1000_SWSM +-#define E1000_82542_FWSM E1000_FWSM +-#define E1000_82542_FFLT_DBG E1000_FFLT_DBG +-#define E1000_82542_IAC E1000_IAC +-#define E1000_82542_ICRXPTC E1000_ICRXPTC +-#define E1000_82542_ICRXATC E1000_ICRXATC +-#define E1000_82542_ICTXPTC E1000_ICTXPTC +-#define E1000_82542_ICTXATC E1000_ICTXATC +-#define E1000_82542_ICTXQEC E1000_ICTXQEC +-#define E1000_82542_ICTXQMTC E1000_ICTXQMTC +-#define E1000_82542_ICRXDMTC E1000_ICRXDMTC +-#define E1000_82542_ICRXOC E1000_ICRXOC +-#define E1000_82542_HICR E1000_HICR +- +-#define E1000_82542_CPUVEC E1000_CPUVEC +-#define E1000_82542_MRQC E1000_MRQC +-#define E1000_82542_RETA E1000_RETA +-#define E1000_82542_RSSRK E1000_RSSRK +-#define E1000_82542_RSSIM E1000_RSSIM +-#define E1000_82542_RSSIR E1000_RSSIR +-#define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA +-#define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC +-#define E1000_82542_MANC2H E1000_MANC2H + + /* Statistics counters collected by the MAC */ + struct e1000_hw_stats { +- u64 crcerrs; +- u64 algnerrc; +- u64 symerrs; +- u64 rxerrc; +- u64 txerrc; +- u64 mpc; +- u64 scc; +- u64 ecol; +- u64 mcc; +- u64 latecol; +- u64 colc; +- u64 dc; +- u64 tncrs; +- u64 sec; +- u64 cexterr; +- u64 rlec; +- u64 xonrxc; +- u64 xontxc; +- u64 xoffrxc; +- u64 xofftxc; +- u64 fcruc; +- u64 prc64; +- u64 prc127; +- u64 prc255; +- u64 prc511; +- u64 prc1023; +- u64 prc1522; +- u64 gprc; +- u64 bprc; +- u64 mprc; +- u64 gptc; +- u64 gorcl; +- u64 gorch; +- u64 gotcl; +- u64 gotch; +- u64 rnbc; +- u64 ruc; +- u64 rfc; +- u64 roc; +- u64 rlerrc; +- u64 rjc; +- u64 mgprc; +- u64 mgpdc; +- u64 mgptc; +- u64 torl; +- u64 torh; +- u64 totl; +- u64 toth; +- u64 tpr; +- u64 tpt; +- u64 ptc64; +- u64 ptc127; +- u64 ptc255; +- u64 ptc511; +- u64 ptc1023; +- u64 ptc1522; +- u64 mptc; +- u64 bptc; +- u64 tsctc; +- u64 tsctfc; +- u64 iac; +- u64 icrxptc; +- u64 icrxatc; +- u64 ictxptc; +- u64 ictxatc; +- u64 ictxqec; +- u64 ictxqmtc; +- u64 icrxdmtc; +- u64 icrxoc; ++ u64 crcerrs; ++ u64 algnerrc; ++ u64 symerrs; ++ u64 rxerrc; ++ u64 mpc; ++ u64 scc; ++ u64 ecol; ++ u64 mcc; ++ u64 latecol; ++ u64 colc; ++ u64 dc; ++ u64 tncrs; ++ u64 sec; ++ u64 cexterr; ++ u64 rlec; ++ u64 xonrxc; ++ u64 xontxc; ++ u64 xoffrxc; ++ u64 xofftxc; ++ u64 fcruc; ++ u64 prc64; ++ u64 prc127; ++ u64 prc255; ++ u64 prc511; ++ u64 prc1023; ++ u64 prc1522; ++ u64 gprc; ++ u64 bprc; ++ u64 mprc; ++ u64 gptc; ++ u64 gorc; ++ u64 gotc; ++ u64 rnbc; ++ u64 ruc; ++ u64 rfc; ++ u64 roc; ++ u64 rjc; ++ u64 mgprc; ++ u64 mgpdc; ++ u64 mgptc; ++ u64 tor; ++ u64 tot; ++ u64 tpr; ++ u64 tpt; ++ u64 ptc64; ++ u64 ptc127; ++ u64 ptc255; ++ u64 ptc511; ++ u64 ptc1023; ++ u64 ptc1522; ++ u64 mptc; ++ u64 bptc; ++ u64 tsctc; ++ u64 tsctfc; ++ u64 iac; ++ u64 icrxptc; ++ u64 icrxatc; ++ u64 ictxptc; ++ u64 ictxatc; ++ u64 ictxqec; ++ u64 ictxqmtc; ++ u64 icrxdmtc; ++ u64 icrxoc; ++ u64 cbtmpc; ++ u64 htdpmc; ++ u64 cbrdpc; ++ u64 cbrmpc; ++ u64 rpthc; ++ u64 hgptc; ++ u64 htcbdpc; ++ u64 hgorc; ++ u64 hgotc; ++ u64 lenerrs; ++ u64 scvpc; ++ u64 hrmpc; ++ u64 doosync; + }; + +-/* Structure containing variables used by the shared code (e1000_hw.c) */ +-struct e1000_hw { +- u8 __iomem *hw_addr; +- u8 __iomem *flash_address; +- e1000_mac_type mac_type; +- e1000_phy_type phy_type; +- u32 phy_init_script; +- e1000_media_type media_type; +- void *back; +- struct e1000_shadow_ram *eeprom_shadow_ram; +- u32 flash_bank_size; +- u32 flash_base_addr; +- e1000_fc_type fc; +- e1000_bus_speed bus_speed; +- e1000_bus_width bus_width; +- e1000_bus_type bus_type; +- struct e1000_eeprom_info eeprom; +- e1000_ms_type master_slave; +- e1000_ms_type original_master_slave; +- e1000_ffe_config ffe_config_state; +- u32 asf_firmware_present; +- u32 eeprom_semaphore_present; +- u32 swfw_sync_present; +- u32 swfwhw_semaphore_present; +- unsigned long io_base; +- u32 phy_id; +- u32 phy_revision; +- u32 phy_addr; +- u32 original_fc; +- u32 txcw; +- u32 autoneg_failed; +- u32 max_frame_size; +- u32 min_frame_size; +- u32 mc_filter_type; +- u32 num_mc_addrs; +- u32 collision_delta; +- u32 tx_packet_delta; +- u32 ledctl_default; +- u32 ledctl_mode1; +- u32 ledctl_mode2; +- bool tx_pkt_filtering; +- struct e1000_host_mng_dhcp_cookie mng_cookie; +- u16 phy_spd_default; +- u16 autoneg_advertised; +- u16 pci_cmd_word; +- u16 fc_high_water; +- u16 fc_low_water; +- u16 fc_pause_time; +- u16 current_ifs_val; +- u16 ifs_min_val; +- u16 ifs_max_val; +- u16 ifs_step_size; +- u16 ifs_ratio; +- u16 device_id; +- u16 vendor_id; +- u16 subsystem_id; +- u16 subsystem_vendor_id; +- u8 revision_id; +- u8 autoneg; +- u8 mdix; +- u8 forced_speed_duplex; +- u8 wait_autoneg_complete; +- u8 dma_fairness; +- u8 mac_addr[NODE_ADDRESS_SIZE]; +- u8 perm_mac_addr[NODE_ADDRESS_SIZE]; +- bool disable_polarity_correction; +- bool speed_downgraded; +- e1000_smart_speed smart_speed; +- e1000_dsp_config dsp_config_state; +- bool get_link_status; +- bool serdes_link_down; +- bool tbi_compatibility_en; +- bool tbi_compatibility_on; +- bool laa_is_present; +- bool phy_reset_disable; +- bool initialize_hw_bits_disable; +- bool fc_send_xon; +- bool fc_strict_ieee; +- bool report_tx_early; +- bool adaptive_ifs; +- bool ifs_params_forced; +- bool in_ifs_mode; +- bool mng_reg_access_disabled; +- bool leave_av_bit_off; +- bool kmrn_lock_loss_workaround_disabled; +- bool bad_tx_carr_stats_fd; +- bool has_manc2h; +- bool rx_needs_kicking; +- bool has_smbus; ++ ++struct e1000_phy_stats { ++ u32 idle_errors; ++ u32 receive_errors; + }; + +- +-#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ +-#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ +-#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ +-#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ +-#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ +-#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ +-#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ +-#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ +-/* Register Bit Masks */ +-/* Device Control */ +-#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ +-#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ +-#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ +-#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ +-#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ +-#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ +-#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ +-#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ +-#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ +-#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ +-#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ +-#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ +-#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ +-#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ +-#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ +-#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ +-#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +-#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ +-#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ +-#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ +-#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ +-#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ +-#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ +-#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ +-#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ +-#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ +-#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ +-#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ +-#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ +-#define E1000_CTRL_RST 0x04000000 /* Global reset */ +-#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ +-#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ +-#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ +-#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ +-#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ +-#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ +- +-/* Device Status */ +-#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ +-#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ +-#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ +-#define E1000_STATUS_FUNC_SHIFT 2 +-#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ +-#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ +-#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ +-#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ +-#define E1000_STATUS_SPEED_MASK 0x000000C0 +-#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ +-#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ +-#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ +-#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion +- by EEPROM/Flash */ +-#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ +-#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ +-#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ +-#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ +-#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ +-#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ +-#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ +-#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ +-#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ +-#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ +-#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ +-#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ +-#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ +-#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ +-#define E1000_STATUS_FUSE_8 0x04000000 +-#define E1000_STATUS_FUSE_9 0x08000000 +-#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ +-#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ +- +-/* Constants used to intrepret the masked PCI-X bus speed. */ +-#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ +-#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ +-#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ +- +-/* EEPROM/Flash Control */ +-#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ +-#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ +-#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ +-#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ +-#define E1000_EECD_FWE_MASK 0x00000030 +-#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ +-#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ +-#define E1000_EECD_FWE_SHIFT 4 +-#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ +-#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ +-#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ +-#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ +-#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type +- * (0-small, 1-large) */ +-#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ +-#ifndef E1000_EEPROM_GRANT_ATTEMPTS +-#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ +-#endif +-#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ +-#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ +-#define E1000_EECD_SIZE_EX_SHIFT 11 +-#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ +-#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ +-#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ +-#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ +-#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ +-#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ +-#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ +-#define E1000_EECD_SECVAL_SHIFT 22 +-#define E1000_STM_OPCODE 0xDB00 +-#define E1000_HICR_FW_RESET 0xC0 +- +-#define E1000_SHADOW_RAM_WORDS 2048 +-#define E1000_ICH_NVM_SIG_WORD 0x13 +-#define E1000_ICH_NVM_SIG_MASK 0xC0 +- +-/* EEPROM Read */ +-#define E1000_EERD_START 0x00000001 /* Start Read */ +-#define E1000_EERD_DONE 0x00000010 /* Read Done */ +-#define E1000_EERD_ADDR_SHIFT 8 +-#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ +-#define E1000_EERD_DATA_SHIFT 16 +-#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ +- +-/* SPI EEPROM Status Register */ +-#define EEPROM_STATUS_RDY_SPI 0x01 +-#define EEPROM_STATUS_WEN_SPI 0x02 +-#define EEPROM_STATUS_BP0_SPI 0x04 +-#define EEPROM_STATUS_BP1_SPI 0x08 +-#define EEPROM_STATUS_WPEN_SPI 0x80 +- +-/* Extended Device Control */ +-#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ +-#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ +-#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN +-#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ +-#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ +-#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ +-#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ +-#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA +-#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ +-#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ +-#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ +-#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ +-#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ +-#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ +-#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ +-#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ +-#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ +-#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ +-#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ +-#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 +-#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 +-#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 +-#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 +-#define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000 +-#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 +-#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 +-#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 +-#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 +-#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 +-#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 +-#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ +-#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ +-#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ +-#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ +-#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ +-#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 +- +-/* MDI Control */ +-#define E1000_MDIC_DATA_MASK 0x0000FFFF +-#define E1000_MDIC_REG_MASK 0x001F0000 +-#define E1000_MDIC_REG_SHIFT 16 +-#define E1000_MDIC_PHY_MASK 0x03E00000 +-#define E1000_MDIC_PHY_SHIFT 21 +-#define E1000_MDIC_OP_WRITE 0x04000000 +-#define E1000_MDIC_OP_READ 0x08000000 +-#define E1000_MDIC_READY 0x10000000 +-#define E1000_MDIC_INT_EN 0x20000000 +-#define E1000_MDIC_ERROR 0x40000000 +- +-#define E1000_KUMCTRLSTA_MASK 0x0000FFFF +-#define E1000_KUMCTRLSTA_OFFSET 0x001F0000 +-#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16 +-#define E1000_KUMCTRLSTA_REN 0x00200000 +- +-#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 +-#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001 +-#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 +-#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003 +-#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 +-#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 +-#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 +-#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E +-#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F +- +-/* FIFO Control */ +-#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 +-#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 +- +-/* In-Band Control */ +-#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500 +-#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 +- +-/* Half-Duplex Control */ +-#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 +-#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 +- +-#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E +- +-#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000 +-#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000 +- +-#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000 +-#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000 +-#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003 +- +-#define E1000_KABGTXD_BGSQLBIAS 0x00050000 +- +-#define E1000_PHY_CTRL_SPD_EN 0x00000001 +-#define E1000_PHY_CTRL_D0A_LPLU 0x00000002 +-#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 +-#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 +-#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 +-#define E1000_PHY_CTRL_B2B_EN 0x00000080 +- +-/* LED Control */ +-#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F +-#define E1000_LEDCTL_LED0_MODE_SHIFT 0 +-#define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020 +-#define E1000_LEDCTL_LED0_IVRT 0x00000040 +-#define E1000_LEDCTL_LED0_BLINK 0x00000080 +-#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 +-#define E1000_LEDCTL_LED1_MODE_SHIFT 8 +-#define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000 +-#define E1000_LEDCTL_LED1_IVRT 0x00004000 +-#define E1000_LEDCTL_LED1_BLINK 0x00008000 +-#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 +-#define E1000_LEDCTL_LED2_MODE_SHIFT 16 +-#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 +-#define E1000_LEDCTL_LED2_IVRT 0x00400000 +-#define E1000_LEDCTL_LED2_BLINK 0x00800000 +-#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 +-#define E1000_LEDCTL_LED3_MODE_SHIFT 24 +-#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 +-#define E1000_LEDCTL_LED3_IVRT 0x40000000 +-#define E1000_LEDCTL_LED3_BLINK 0x80000000 +- +-#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 +-#define E1000_LEDCTL_MODE_LINK_100_1000 0x1 +-#define E1000_LEDCTL_MODE_LINK_UP 0x2 +-#define E1000_LEDCTL_MODE_ACTIVITY 0x3 +-#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 +-#define E1000_LEDCTL_MODE_LINK_10 0x5 +-#define E1000_LEDCTL_MODE_LINK_100 0x6 +-#define E1000_LEDCTL_MODE_LINK_1000 0x7 +-#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 +-#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 +-#define E1000_LEDCTL_MODE_COLLISION 0xA +-#define E1000_LEDCTL_MODE_BUS_SPEED 0xB +-#define E1000_LEDCTL_MODE_BUS_SIZE 0xC +-#define E1000_LEDCTL_MODE_PAUSED 0xD +-#define E1000_LEDCTL_MODE_LED_ON 0xE +-#define E1000_LEDCTL_MODE_LED_OFF 0xF +- +-/* Receive Address */ +-#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ +- +-/* Interrupt Cause Read */ +-#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ +-#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ +-#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ +-#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ +-#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ +-#define E1000_ICR_RXO 0x00000040 /* rx overrun */ +-#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ +-#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ +-#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ +-#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ +-#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ +-#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ +-#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ +-#define E1000_ICR_TXD_LOW 0x00008000 +-#define E1000_ICR_SRPD 0x00010000 +-#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ +-#define E1000_ICR_MNG 0x00040000 /* Manageability event */ +-#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ +-#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ +-#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ +-#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ +-#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ +-#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ +-#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ +-#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ +-#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ +-#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ +-#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ +-#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ +- +-/* Interrupt Cause Set */ +-#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +-#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +-#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ +-#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +-#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +-#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ +-#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +-#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ +-#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +-#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +-#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +-#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +-#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +-#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW +-#define E1000_ICS_SRPD E1000_ICR_SRPD +-#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ +-#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ +-#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ +-#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ +-#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ +-#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ +-#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ +-#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ +-#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ +-#define E1000_ICS_DSW E1000_ICR_DSW +-#define E1000_ICS_PHYINT E1000_ICR_PHYINT +-#define E1000_ICS_EPRST E1000_ICR_EPRST +- +-/* Interrupt Mask Set */ +-#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +-#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +-#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ +-#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +-#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +-#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ +-#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +-#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ +-#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +-#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +-#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +-#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +-#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +-#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW +-#define E1000_IMS_SRPD E1000_ICR_SRPD +-#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ +-#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ +-#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ +-#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ +-#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ +-#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ +-#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ +-#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ +-#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ +-#define E1000_IMS_DSW E1000_ICR_DSW +-#define E1000_IMS_PHYINT E1000_ICR_PHYINT +-#define E1000_IMS_EPRST E1000_ICR_EPRST +- +-/* Interrupt Mask Clear */ +-#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +-#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +-#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ +-#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +-#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +-#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ +-#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +-#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ +-#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +-#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +-#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +-#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +-#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +-#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW +-#define E1000_IMC_SRPD E1000_ICR_SRPD +-#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ +-#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ +-#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ +-#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ +-#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ +-#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ +-#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ +-#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ +-#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ +-#define E1000_IMC_DSW E1000_ICR_DSW +-#define E1000_IMC_PHYINT E1000_ICR_PHYINT +-#define E1000_IMC_EPRST E1000_ICR_EPRST +- +-/* Receive Control */ +-#define E1000_RCTL_RST 0x00000001 /* Software reset */ +-#define E1000_RCTL_EN 0x00000002 /* enable */ +-#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ +-#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ +-#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ +-#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ +-#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ +-#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ +-#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ +-#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ +-#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ +-#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ +-#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ +-#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ +-#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ +-#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ +-#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ +-#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ +-#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ +-#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ +-#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ +-#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ +-/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ +-#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ +-#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ +-#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ +-#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ +-/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ +-#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ +-#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ +-#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ +-#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ +-#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ +-#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ +-#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ +-#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ +-#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ +-#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ +-#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ +-#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ +- +-/* Use byte values for the following shift parameters +- * Usage: +- * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & +- * E1000_PSRCTL_BSIZE0_MASK) | +- * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & +- * E1000_PSRCTL_BSIZE1_MASK) | +- * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & +- * E1000_PSRCTL_BSIZE2_MASK) | +- * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; +- * E1000_PSRCTL_BSIZE3_MASK)) +- * where value0 = [128..16256], default=256 +- * value1 = [1024..64512], default=4096 +- * value2 = [0..64512], default=4096 +- * value3 = [0..64512], default=0 +- */ +- +-#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F +-#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 +-#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 +-#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 +- +-#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ +-#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ +-#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ +-#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ +- +-/* SW_W_SYNC definitions */ +-#define E1000_SWFW_EEP_SM 0x0001 +-#define E1000_SWFW_PHY0_SM 0x0002 +-#define E1000_SWFW_PHY1_SM 0x0004 +-#define E1000_SWFW_MAC_CSR_SM 0x0008 +- +-/* Receive Descriptor */ +-#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ +-#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ +-#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ +-#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ +-#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ +- +-/* Flow Control */ +-#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ +-#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ +-#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ +-#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ +- +-/* Header split receive */ +-#define E1000_RFCTL_ISCSI_DIS 0x00000001 +-#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E +-#define E1000_RFCTL_ISCSI_DWC_SHIFT 1 +-#define E1000_RFCTL_NFSW_DIS 0x00000040 +-#define E1000_RFCTL_NFSR_DIS 0x00000080 +-#define E1000_RFCTL_NFS_VER_MASK 0x00000300 +-#define E1000_RFCTL_NFS_VER_SHIFT 8 +-#define E1000_RFCTL_IPV6_DIS 0x00000400 +-#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 +-#define E1000_RFCTL_ACK_DIS 0x00001000 +-#define E1000_RFCTL_ACKD_DIS 0x00002000 +-#define E1000_RFCTL_IPFRSP_DIS 0x00004000 +-#define E1000_RFCTL_EXTEN 0x00008000 +-#define E1000_RFCTL_IPV6_EX_DIS 0x00010000 +-#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 +- +-/* Receive Descriptor Control */ +-#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ +-#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ +-#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ +-#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ +- +-/* Transmit Descriptor Control */ +-#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ +-#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ +-#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ +-#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ +-#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ +-#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ +-#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. +- still to be processed. */ +-/* Transmit Configuration Word */ +-#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ +-#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ +-#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ +-#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ +-#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ +-#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ +-#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ +-#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ +-#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ +-#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ +- +-/* Receive Configuration Word */ +-#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ +-#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ +-#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ +-#define E1000_RXCW_CC 0x10000000 /* Receive config change */ +-#define E1000_RXCW_C 0x20000000 /* Receive config */ +-#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ +-#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ +- +-/* Transmit Control */ +-#define E1000_TCTL_RST 0x00000001 /* software reset */ +-#define E1000_TCTL_EN 0x00000002 /* enable tx */ +-#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ +-#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ +-#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ +-#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ +-#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ +-#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ +-#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ +-#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ +-#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ +-/* Extended Transmit Control */ +-#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ +-#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ +- +-#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 +- +-/* Receive Checksum Control */ +-#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ +-#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ +-#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ +-#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ +-#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ +-#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ +- +-/* Multiple Receive Queue Control */ +-#define E1000_MRQC_ENABLE_MASK 0x00000003 +-#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 +-#define E1000_MRQC_ENABLE_RSS_INT 0x00000004 +-#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 +-#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 +-#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 +-#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 +-#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 +-#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 +-#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 +- +-/* Definitions for power management and wakeup registers */ +-/* Wake Up Control */ +-#define E1000_WUC_APME 0x00000001 /* APM Enable */ +-#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ +-#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ +-#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ +-#define E1000_WUC_SPM 0x80000000 /* Enable SPM */ +- +-/* Wake Up Filter Control */ +-#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ +-#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ +-#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ +-#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ +-#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ +-#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ +-#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ +-#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ +-#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ +-#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ +-#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ +-#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ +-#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ +-#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ +-#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ +-#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ +- +-/* Wake Up Status */ +-#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ +-#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ +-#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ +-#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ +-#define E1000_WUS_BC 0x00000010 /* Broadcast Received */ +-#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ +-#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ +-#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ +-#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ +-#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ +-#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ +-#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ +-#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ +- +-/* Management Control */ +-#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ +-#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ +-#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ +-#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ +-#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ +-#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ +-#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ +-#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ +-#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ +-#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery +- * Filtering */ +-#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ +-#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ +-#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ +-#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ +-#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ +-#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ +-#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address +- * filtering */ +-#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host +- * memory */ +-#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address +- * filtering */ +-#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ +-#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ +-#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ +-#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ +-#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ +-#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ +-#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ +-#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ +- +-#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ +-#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ +- +-/* SW Semaphore Register */ +-#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ +-#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ +-#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ +-#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ +- +-/* FW Semaphore Register */ +-#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ +-#define E1000_FWSM_MODE_SHIFT 1 +-#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ +- +-#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ +-#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */ +-#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */ +-#define E1000_FWSM_SKUEL_SHIFT 29 +-#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */ +-#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */ +-#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */ +-#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */ +- +-/* FFLT Debug Register */ +-#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ +- +-typedef enum { +- e1000_mng_mode_none = 0, +- e1000_mng_mode_asf, +- e1000_mng_mode_pt, +- e1000_mng_mode_ipmi, +- e1000_mng_mode_host_interface_only +-} e1000_mng_mode; +- +-/* Host Inteface Control Register */ +-#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */ +-#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done +- * to put command in RAM */ +-#define E1000_HICR_SV 0x00000004 /* Status Validity */ +-#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */ +- +-/* Host Interface Command Interface - Address range 0x8800-0x8EFF */ +-#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */ +-#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */ +-#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */ +-#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ +- +-struct e1000_host_command_header { +- u8 command_id; +- u8 command_length; +- u8 command_options; /* I/F bits for command, status for return */ +- u8 checksum; +-}; +-struct e1000_host_command_info { +- struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ +- u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ ++struct e1000_host_mng_dhcp_cookie { ++ u32 signature; ++ u8 status; ++ u8 reserved0; ++ u16 vlan_id; ++ u32 reserved1; ++ u16 reserved2; ++ u8 reserved3; ++ u8 checksum; + }; + +-/* Host SMB register #0 */ +-#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */ +-#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */ +-#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */ +-#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */ +- +-/* Host SMB register #1 */ +-#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN +-#define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN +-#define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT +-#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT +- +-/* FW Status Register */ +-#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */ +- +-/* Wake Up Packet Length */ +-#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ +- +-#define E1000_MDALIGN 4096 +- +-/* PCI-Ex registers*/ +- +-/* PCI-Ex Control Register */ +-#define E1000_GCR_RXD_NO_SNOOP 0x00000001 +-#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 +-#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 +-#define E1000_GCR_TXD_NO_SNOOP 0x00000008 +-#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 +-#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 +- +-#define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ +- E1000_GCR_RXDSCW_NO_SNOOP | \ +- E1000_GCR_RXDSCR_NO_SNOOP | \ +- E1000_GCR_TXD_NO_SNOOP | \ +- E1000_GCR_TXDSCW_NO_SNOOP | \ +- E1000_GCR_TXDSCR_NO_SNOOP) +- +-#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL +- +-#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 +-/* Function Active and Power State to MNG */ +-#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003 +-#define E1000_FACTPS_LAN0_VALID 0x00000004 +-#define E1000_FACTPS_FUNC0_AUX_EN 0x00000008 +-#define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0 +-#define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6 +-#define E1000_FACTPS_LAN1_VALID 0x00000100 +-#define E1000_FACTPS_FUNC1_AUX_EN 0x00000200 +-#define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000 +-#define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12 +-#define E1000_FACTPS_IDE_ENABLE 0x00004000 +-#define E1000_FACTPS_FUNC2_AUX_EN 0x00008000 +-#define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000 +-#define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18 +-#define E1000_FACTPS_SP_ENABLE 0x00100000 +-#define E1000_FACTPS_FUNC3_AUX_EN 0x00200000 +-#define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000 +-#define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24 +-#define E1000_FACTPS_IPMI_ENABLE 0x04000000 +-#define E1000_FACTPS_FUNC4_AUX_EN 0x08000000 +-#define E1000_FACTPS_MNGCG 0x20000000 +-#define E1000_FACTPS_LAN_FUNC_SEL 0x40000000 +-#define E1000_FACTPS_PM_STATE_CHANGED 0x80000000 +- +-/* PCI-Ex Config Space */ +-#define PCI_EX_LINK_STATUS 0x12 +-#define PCI_EX_LINK_WIDTH_MASK 0x3F0 +-#define PCI_EX_LINK_WIDTH_SHIFT 4 +- +-/* EEPROM Commands - Microwire */ +-#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ +-#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ +-#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ +-#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ +-#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ +- +-/* EEPROM Commands - SPI */ +-#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ +-#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ +-#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ +-#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ +-#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ +-#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ +-#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ +-#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ +-#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ +-#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ +-#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ +- +-/* EEPROM Size definitions */ +-#define EEPROM_WORD_SIZE_SHIFT 6 +-#define EEPROM_SIZE_SHIFT 10 +-#define EEPROM_SIZE_MASK 0x1C00 +- +-/* EEPROM Word Offsets */ +-#define EEPROM_COMPAT 0x0003 +-#define EEPROM_ID_LED_SETTINGS 0x0004 +-#define EEPROM_VERSION 0x0005 +-#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ +-#define EEPROM_PHY_CLASS_WORD 0x0007 +-#define EEPROM_INIT_CONTROL1_REG 0x000A +-#define EEPROM_INIT_CONTROL2_REG 0x000F +-#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010 +-#define EEPROM_INIT_CONTROL3_PORT_B 0x0014 +-#define EEPROM_INIT_3GIO_3 0x001A +-#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020 +-#define EEPROM_INIT_CONTROL3_PORT_A 0x0024 +-#define EEPROM_CFG 0x0012 +-#define EEPROM_FLASH_VERSION 0x0032 +-#define EEPROM_CHECKSUM_REG 0x003F +- +-#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ +-#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ +- +-/* Word definitions for ID LED Settings */ +-#define ID_LED_RESERVED_0000 0x0000 +-#define ID_LED_RESERVED_FFFF 0xFFFF +-#define ID_LED_RESERVED_82573 0xF746 +-#define ID_LED_DEFAULT_82573 0x1811 +-#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ +- (ID_LED_OFF1_OFF2 << 8) | \ +- (ID_LED_DEF1_DEF2 << 4) | \ +- (ID_LED_DEF1_DEF2)) +-#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ +- (ID_LED_DEF1_OFF2 << 8) | \ +- (ID_LED_DEF1_ON2 << 4) | \ +- (ID_LED_DEF1_DEF2)) +-#define ID_LED_DEF1_DEF2 0x1 +-#define ID_LED_DEF1_ON2 0x2 +-#define ID_LED_DEF1_OFF2 0x3 +-#define ID_LED_ON1_DEF2 0x4 +-#define ID_LED_ON1_ON2 0x5 +-#define ID_LED_ON1_OFF2 0x6 +-#define ID_LED_OFF1_DEF2 0x7 +-#define ID_LED_OFF1_ON2 0x8 +-#define ID_LED_OFF1_OFF2 0x9 +- +-#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF +-#define IGP_ACTIVITY_LED_ENABLE 0x0300 +-#define IGP_LED3_MODE 0x07000000 +- +- +-/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ +-#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F +- +-/* Mask bit for PHY class in Word 7 of the EEPROM */ +-#define EEPROM_PHY_CLASS_A 0x8000 +- +-/* Mask bits for fields in Word 0x0a of the EEPROM */ +-#define EEPROM_WORD0A_ILOS 0x0010 +-#define EEPROM_WORD0A_SWDPIO 0x01E0 +-#define EEPROM_WORD0A_LRST 0x0200 +-#define EEPROM_WORD0A_FD 0x0400 +-#define EEPROM_WORD0A_66MHZ 0x0800 +- +-/* Mask bits for fields in Word 0x0f of the EEPROM */ +-#define EEPROM_WORD0F_PAUSE_MASK 0x3000 +-#define EEPROM_WORD0F_PAUSE 0x1000 +-#define EEPROM_WORD0F_ASM_DIR 0x2000 +-#define EEPROM_WORD0F_ANE 0x0800 +-#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 +-#define EEPROM_WORD0F_LPLU 0x0001 +- +-/* Mask bits for fields in Word 0x10/0x20 of the EEPROM */ +-#define EEPROM_WORD1020_GIGA_DISABLE 0x0010 +-#define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008 +- +-/* Mask bits for fields in Word 0x1a of the EEPROM */ +-#define EEPROM_WORD1A_ASPM_MASK 0x000C +- +-/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ +-#define EEPROM_SUM 0xBABA +- +-/* EEPROM Map defines (WORD OFFSETS)*/ +-#define EEPROM_NODE_ADDRESS_BYTE_0 0 +-#define EEPROM_PBA_BYTE_1 8 +- +-#define EEPROM_RESERVED_WORD 0xFFFF +- +-/* EEPROM Map Sizes (Byte Counts) */ +-#define PBA_SIZE 4 +- +-/* Collision related configuration parameters */ +-#define E1000_COLLISION_THRESHOLD 15 +-#define E1000_CT_SHIFT 4 +-/* Collision distance is a 0-based value that applies to +- * half-duplex-capable hardware only. */ +-#define E1000_COLLISION_DISTANCE 63 +-#define E1000_COLLISION_DISTANCE_82542 64 +-#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE +-#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE +-#define E1000_COLD_SHIFT 12 +- +-/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ +-#define REQ_TX_DESCRIPTOR_MULTIPLE 8 +-#define REQ_RX_DESCRIPTOR_MULTIPLE 8 +- +-/* Default values for the transmit IPG register */ +-#define DEFAULT_82542_TIPG_IPGT 10 +-#define DEFAULT_82543_TIPG_IPGT_FIBER 9 +-#define DEFAULT_82543_TIPG_IPGT_COPPER 8 +- +-#define E1000_TIPG_IPGT_MASK 0x000003FF +-#define E1000_TIPG_IPGR1_MASK 0x000FFC00 +-#define E1000_TIPG_IPGR2_MASK 0x3FF00000 +- +-#define DEFAULT_82542_TIPG_IPGR1 2 +-#define DEFAULT_82543_TIPG_IPGR1 8 +-#define E1000_TIPG_IPGR1_SHIFT 10 +- +-#define DEFAULT_82542_TIPG_IPGR2 10 +-#define DEFAULT_82543_TIPG_IPGR2 6 +-#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 +-#define E1000_TIPG_IPGR2_SHIFT 20 +- +-#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009 +-#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008 +-#define E1000_TXDMAC_DPP 0x00000001 +- +-/* Adaptive IFS defines */ +-#define TX_THRESHOLD_START 8 +-#define TX_THRESHOLD_INCREMENT 10 +-#define TX_THRESHOLD_DECREMENT 1 +-#define TX_THRESHOLD_STOP 190 +-#define TX_THRESHOLD_DISABLE 0 +-#define TX_THRESHOLD_TIMER_MS 10000 +-#define MIN_NUM_XMITS 1000 +-#define IFS_MAX 80 +-#define IFS_STEP 10 +-#define IFS_MIN 40 +-#define IFS_RATIO 4 +- +-/* Extended Configuration Control and Size */ +-#define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001 +-#define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002 +-#define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004 +-#define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008 +-#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010 +-#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 +-#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040 +-#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000 +- +-#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF +-#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00 +-#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000 +-#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 +-#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 +- +-/* PBA constants */ +-#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ +-#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ +-#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ +-#define E1000_PBA_20K 0x0014 +-#define E1000_PBA_22K 0x0016 +-#define E1000_PBA_24K 0x0018 +-#define E1000_PBA_30K 0x001E +-#define E1000_PBA_32K 0x0020 +-#define E1000_PBA_34K 0x0022 +-#define E1000_PBA_38K 0x0026 +-#define E1000_PBA_40K 0x0028 +-#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ +- +-#define E1000_PBS_16K E1000_PBA_16K +- +-/* Flow Control Constants */ +-#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 +-#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 +-#define FLOW_CONTROL_TYPE 0x8808 +- +-/* The historical defaults for the flow control values are given below. */ +-#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ +-#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ +-#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ +- +-/* PCIX Config space */ +-#define PCIX_COMMAND_REGISTER 0xE6 +-#define PCIX_STATUS_REGISTER_LO 0xE8 +-#define PCIX_STATUS_REGISTER_HI 0xEA +- +-#define PCIX_COMMAND_MMRBC_MASK 0x000C +-#define PCIX_COMMAND_MMRBC_SHIFT 0x2 +-#define PCIX_STATUS_HI_MMRBC_MASK 0x0060 +-#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 +-#define PCIX_STATUS_HI_MMRBC_4K 0x3 +-#define PCIX_STATUS_HI_MMRBC_2K 0x2 +- +- +-/* Number of bits required to shift right the "pause" bits from the +- * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. +- */ +-#define PAUSE_SHIFT 5 +- +-/* Number of bits required to shift left the "SWDPIO" bits from the +- * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register. +- */ +-#define SWDPIO_SHIFT 17 +- +-/* Number of bits required to shift left the "SWDPIO_EXT" bits from the +- * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register. +- */ +-#define SWDPIO__EXT_SHIFT 4 +- +-/* Number of bits required to shift left the "ILOS" bit from the EEPROM +- * (bit 4) to the "ILOS" (bit 7) field in the CTRL register. +- */ +-#define ILOS_SHIFT 3 +- +- +-#define RECEIVE_BUFFER_ALIGN_SIZE (256) +- +-/* Number of milliseconds we wait for auto-negotiation to complete */ +-#define LINK_UP_TIMEOUT 500 +- +-/* Number of 100 microseconds we wait for PCI Express master disable */ +-#define MASTER_DISABLE_TIMEOUT 800 +-/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ +-#define AUTO_READ_DONE_TIMEOUT 10 +-/* Number of milliseconds we wait for PHY configuration done after MAC reset */ +-#define PHY_CFG_TIMEOUT 100 +- +-#define E1000_TX_BUFFER_SIZE ((u32)1514) +- +-/* The carrier extension symbol, as received by the NIC. */ +-#define CARRIER_EXTENSION 0x0F +- +-/* TBI_ACCEPT macro definition: +- * +- * This macro requires: +- * adapter = a pointer to struct e1000_hw +- * status = the 8 bit status field of the RX descriptor with EOP set +- * error = the 8 bit error field of the RX descriptor with EOP set +- * length = the sum of all the length fields of the RX descriptors that +- * make up the current frame +- * last_byte = the last byte of the frame DMAed by the hardware +- * max_frame_length = the maximum frame length we want to accept. +- * min_frame_length = the minimum frame length we want to accept. +- * +- * This macro is a conditional that should be used in the interrupt +- * handler's Rx processing routine when RxErrors have been detected. +- * +- * Typical use: +- * ... +- * if (TBI_ACCEPT) { +- * accept_frame = true; +- * e1000_tbi_adjust_stats(adapter, MacAddress); +- * frame_length--; +- * } else { +- * accept_frame = false; +- * } +- * ... +- */ +- +-#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \ +- ((adapter)->tbi_compatibility_on && \ +- (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ +- ((last_byte) == CARRIER_EXTENSION) && \ +- (((status) & E1000_RXD_STAT_VP) ? \ +- (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ +- ((length) <= ((adapter)->max_frame_size + 1))) : \ +- (((length) > (adapter)->min_frame_size) && \ +- ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) +- +- +-/* Structures, enums, and macros for the PHY */ +- +-/* Bit definitions for the Management Data IO (MDIO) and Management Data +- * Clock (MDC) pins in the Device Control Register. +- */ +-#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 +-#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 +-#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 +-#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 +-#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 +-#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 +-#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR +-#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA +- +-/* PHY 1000 MII Register/Bit Definitions */ +-/* PHY Registers defined by IEEE */ +-#define PHY_CTRL 0x00 /* Control Register */ +-#define PHY_STATUS 0x01 /* Status Regiser */ +-#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ +-#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ +-#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ +-#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ +-#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ +-#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ +-#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ +-#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ +-#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ +-#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ +- +-#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ +-#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ +- +-/* M88E1000 Specific Registers */ +-#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ +-#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ +-#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ +-#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ +-#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ +-#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ +- +-#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ +-#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ +-#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ +-#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ +-#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ +- +-#define IGP01E1000_IEEE_REGS_PAGE 0x0000 +-#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 +-#define IGP01E1000_IEEE_FORCE_GIGA 0x0140 +- +-/* IGP01E1000 Specific Registers */ +-#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ +-#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ +-#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ +-#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ +-#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ +-#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ +-#define IGP02E1000_PHY_POWER_MGMT 0x19 +-#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ +- +-/* IGP01E1000 AGC Registers - stores the cable length values*/ +-#define IGP01E1000_PHY_AGC_A 0x1172 +-#define IGP01E1000_PHY_AGC_B 0x1272 +-#define IGP01E1000_PHY_AGC_C 0x1472 +-#define IGP01E1000_PHY_AGC_D 0x1872 +- +-/* IGP02E1000 AGC Registers for cable length values */ +-#define IGP02E1000_PHY_AGC_A 0x11B1 +-#define IGP02E1000_PHY_AGC_B 0x12B1 +-#define IGP02E1000_PHY_AGC_C 0x14B1 +-#define IGP02E1000_PHY_AGC_D 0x18B1 +- +-/* IGP01E1000 DSP Reset Register */ +-#define IGP01E1000_PHY_DSP_RESET 0x1F33 +-#define IGP01E1000_PHY_DSP_SET 0x1F71 +-#define IGP01E1000_PHY_DSP_FFE 0x1F35 +- +-#define IGP01E1000_PHY_CHANNEL_NUM 4 +-#define IGP02E1000_PHY_CHANNEL_NUM 4 +- +-#define IGP01E1000_PHY_AGC_PARAM_A 0x1171 +-#define IGP01E1000_PHY_AGC_PARAM_B 0x1271 +-#define IGP01E1000_PHY_AGC_PARAM_C 0x1471 +-#define IGP01E1000_PHY_AGC_PARAM_D 0x1871 +- +-#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 +-#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 +- +-#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890 +-#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000 +-#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004 +-#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 +- +-#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A +-/* IGP01E1000 PCS Initialization register - stores the polarity status when +- * speed = 1000 Mbps. */ +-#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 +-#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5 +- +-#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 +- +-/* Bits... +- * 15-5: page +- * 4-0: register offset +- */ +-#define GG82563_PAGE_SHIFT 5 +-#define GG82563_REG(page, reg) \ +- (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) +-#define GG82563_MIN_ALT_REG 30 +- +-/* GG82563 Specific Registers */ +-#define GG82563_PHY_SPEC_CTRL \ +- GG82563_REG(0, 16) /* PHY Specific Control */ +-#define GG82563_PHY_SPEC_STATUS \ +- GG82563_REG(0, 17) /* PHY Specific Status */ +-#define GG82563_PHY_INT_ENABLE \ +- GG82563_REG(0, 18) /* Interrupt Enable */ +-#define GG82563_PHY_SPEC_STATUS_2 \ +- GG82563_REG(0, 19) /* PHY Specific Status 2 */ +-#define GG82563_PHY_RX_ERR_CNTR \ +- GG82563_REG(0, 21) /* Receive Error Counter */ +-#define GG82563_PHY_PAGE_SELECT \ +- GG82563_REG(0, 22) /* Page Select */ +-#define GG82563_PHY_SPEC_CTRL_2 \ +- GG82563_REG(0, 26) /* PHY Specific Control 2 */ +-#define GG82563_PHY_PAGE_SELECT_ALT \ +- GG82563_REG(0, 29) /* Alternate Page Select */ +-#define GG82563_PHY_TEST_CLK_CTRL \ +- GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ +- +-#define GG82563_PHY_MAC_SPEC_CTRL \ +- GG82563_REG(2, 21) /* MAC Specific Control Register */ +-#define GG82563_PHY_MAC_SPEC_CTRL_2 \ +- GG82563_REG(2, 26) /* MAC Specific Control 2 */ +- +-#define GG82563_PHY_DSP_DISTANCE \ +- GG82563_REG(5, 26) /* DSP Distance */ +- +-/* Page 193 - Port Control Registers */ +-#define GG82563_PHY_KMRN_MODE_CTRL \ +- GG82563_REG(193, 16) /* Kumeran Mode Control */ +-#define GG82563_PHY_PORT_RESET \ +- GG82563_REG(193, 17) /* Port Reset */ +-#define GG82563_PHY_REVISION_ID \ +- GG82563_REG(193, 18) /* Revision ID */ +-#define GG82563_PHY_DEVICE_ID \ +- GG82563_REG(193, 19) /* Device ID */ +-#define GG82563_PHY_PWR_MGMT_CTRL \ +- GG82563_REG(193, 20) /* Power Management Control */ +-#define GG82563_PHY_RATE_ADAPT_CTRL \ +- GG82563_REG(193, 25) /* Rate Adaptation Control */ +- +-/* Page 194 - KMRN Registers */ +-#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ +- GG82563_REG(194, 16) /* FIFO's Control/Status */ +-#define GG82563_PHY_KMRN_CTRL \ +- GG82563_REG(194, 17) /* Control */ +-#define GG82563_PHY_INBAND_CTRL \ +- GG82563_REG(194, 18) /* Inband Control */ +-#define GG82563_PHY_KMRN_DIAGNOSTIC \ +- GG82563_REG(194, 19) /* Diagnostic */ +-#define GG82563_PHY_ACK_TIMEOUTS \ +- GG82563_REG(194, 20) /* Acknowledge Timeouts */ +-#define GG82563_PHY_ADV_ABILITY \ +- GG82563_REG(194, 21) /* Advertised Ability */ +-#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ +- GG82563_REG(194, 23) /* Link Partner Advertised Ability */ +-#define GG82563_PHY_ADV_NEXT_PAGE \ +- GG82563_REG(194, 24) /* Advertised Next Page */ +-#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ +- GG82563_REG(194, 25) /* Link Partner Advertised Next page */ +-#define GG82563_PHY_KMRN_MISC \ +- GG82563_REG(194, 26) /* Misc. */ +- +-/* PHY Control Register */ +-#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ +-#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ +-#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ +-#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ +-#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ +-#define MII_CR_POWER_DOWN 0x0800 /* Power down */ +-#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ +-#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ +-#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ +-#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ +- +-/* PHY Status Register */ +-#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ +-#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ +-#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ +-#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ +-#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ +-#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ +-#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ +-#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ +-#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ +-#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ +-#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ +-#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ +-#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ +-#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ +-#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ +- +-/* Autoneg Advertisement Register */ +-#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ +-#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ +-#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ +-#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ +-#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ +-#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ +-#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ +-#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ +-#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ +-#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ +- +-/* Link Partner Ability Register (Base Page) */ +-#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ +-#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ +-#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ +-#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ +-#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ +-#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ +-#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ +-#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ +-#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ +-#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ +-#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ +- +-/* Autoneg Expansion Register */ +-#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ +-#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ +-#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ +-#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ +-#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ +- +-/* Next Page TX Register */ +-#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ +-#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges +- * of different NP +- */ +-#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg +- * 0 = cannot comply with msg +- */ +-#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ +-#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow +- * 0 = sending last NP +- */ +- +-/* Link Partner Next Page Register */ +-#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ +-#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges +- * of different NP +- */ +-#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg +- * 0 = cannot comply with msg +- */ +-#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ +-#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ +-#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow +- * 0 = sending last NP +- */ +- +-/* 1000BASE-T Control Register */ +-#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ +-#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ +-#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ +-#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ +- /* 0=DTE device */ +-#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ +- /* 0=Configure PHY as Slave */ +-#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ +- /* 0=Automatic Master/Slave config */ +-#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ +-#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ +-#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ +-#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ +-#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ +- +-/* 1000BASE-T Status Register */ +-#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ +-#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ +-#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ +-#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ +-#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ +-#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ +-#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ +-#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ +-#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 +-#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 +-#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 +-#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 +-#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 +- +-/* Extended Status Register */ +-#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ +-#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ +-#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ +-#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ +- +-#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ +-#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ +- +-#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ +- /* (0=enable, 1=disable) */ +- +-/* M88E1000 PHY Specific Control Register */ +-#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ +-#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ +-#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ +-#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, +- * 0=CLK125 toggling +- */ +-#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ +- /* Manual MDI configuration */ +-#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ +-#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, +- * 100BASE-TX/10BASE-T: +- * MDI Mode +- */ +-#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled +- * all speeds. +- */ +-#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 +- /* 1=Enable Extended 10BASE-T distance +- * (Lower 10BASE-T RX Threshold) +- * 0=Normal 10BASE-T RX Threshold */ +-#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 +- /* 1=5-Bit interface in 100BASE-TX +- * 0=MII interface in 100BASE-TX */ +-#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ +-#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ +-#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ +- +-#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 +-#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 +-#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 +- +-/* M88E1000 PHY Specific Status Register */ +-#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ +-#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ +-#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ +-#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ +-#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; +- * 3=110-140M;4=>140M */ +-#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ +-#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ +-#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ +-#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ +-#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ +-#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ +-#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ +-#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ +- +-#define M88E1000_PSSR_REV_POLARITY_SHIFT 1 +-#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5 +-#define M88E1000_PSSR_MDIX_SHIFT 6 +-#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 +- +-/* M88E1000 Extended PHY Specific Control Register */ +-#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ +-#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. +- * Will assert lost lock and bring +- * link down if idle not seen +- * within 1ms in 1000BASE-T +- */ +-/* Number of times we will attempt to autonegotiate before downshifting if we +- * are the master */ +-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 +-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 +-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 +-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 +-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 +-/* Number of times we will attempt to autonegotiate before downshifting if we +- * are the slave */ +-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 +-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 +-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 +-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 +-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 +-#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ +-#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ +-#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ +- +-/* M88EC018 Rev 2 specific DownShift settings */ +-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 +-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 +-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 +-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 +-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 +-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 +-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 +-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 +-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 +- +-/* IGP01E1000 Specific Port Config Register - R/W */ +-#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 +-#define IGP01E1000_PSCFR_PRE_EN 0x0020 +-#define IGP01E1000_PSCFR_SMART_SPEED 0x0080 +-#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100 +-#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400 +-#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 +- +-/* IGP01E1000 Specific Port Status Register - R/O */ +-#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ +-#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 +-#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C +-#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200 +-#define IGP01E1000_PSSR_LINK_UP 0x0400 +-#define IGP01E1000_PSSR_MDIX 0x0800 +-#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */ +-#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000 +-#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000 +-#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 +-#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ +-#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ +- +-/* IGP01E1000 Specific Port Control Register - R/W */ +-#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 +-#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200 +-#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 +-#define IGP01E1000_PSCR_FLIP_CHIP 0x0800 +-#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 +-#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ +- +-/* IGP01E1000 Specific Port Link Health Register */ +-#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 +-#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000 +-#define IGP01E1000_PLHR_MASTER_FAULT 0x2000 +-#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000 +-#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ +-#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ +-#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */ +-#define IGP01E1000_PLHR_DATA_ERR_0 0x0100 +-#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040 +-#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010 +-#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008 +-#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004 +-#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002 +-#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001 +- +-/* IGP01E1000 Channel Quality Register */ +-#define IGP01E1000_MSE_CHANNEL_D 0x000F +-#define IGP01E1000_MSE_CHANNEL_C 0x00F0 +-#define IGP01E1000_MSE_CHANNEL_B 0x0F00 +-#define IGP01E1000_MSE_CHANNEL_A 0xF000 +- +-#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ +-#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */ +-#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */ +- +-/* IGP01E1000 DSP reset macros */ +-#define DSP_RESET_ENABLE 0x0 +-#define DSP_RESET_DISABLE 0x2 +-#define E1000_MAX_DSP_RESETS 10 +- +-/* IGP01E1000 & IGP02E1000 AGC Registers */ +- +-#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ +-#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */ +- +-/* IGP02E1000 AGC Register Length 9-bit mask */ +-#define IGP02E1000_AGC_LENGTH_MASK 0x7F +- +-/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */ +-#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128 +-#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113 +- +-/* The precision error of the cable length is +/- 10 meters */ +-#define IGP01E1000_AGC_RANGE 10 +-#define IGP02E1000_AGC_RANGE 15 +- +-/* IGP01E1000 PCS Initialization register */ +-/* bits 3:6 in the PCS registers stores the channels polarity */ +-#define IGP01E1000_PHY_POLARITY_MASK 0x0078 +- +-/* IGP01E1000 GMII FIFO Register */ +-#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed +- * on Link-Up */ +-#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ +- +-/* IGP01E1000 Analog Register */ +-#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 +-#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 +-#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC +-#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE +- +-#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 +-#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 +-#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 +-#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 +-#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 +- +-#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 +-#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 +-#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 +-#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 +- +-/* GG82563 PHY Specific Status Register (Page 0, Register 16 */ +-#define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */ +-#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */ +-#define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */ +-#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */ +-#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 +-#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */ +-#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */ +-#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */ +-#define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */ +-#define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300 +-#define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */ +-#define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */ +-#define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */ +-#define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */ +-#define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */ +-#define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000 +-#define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12 +- +-/* PHY Specific Status Register (Page 0, Register 17) */ +-#define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */ +-#define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */ +-#define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */ +-#define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */ +-#define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */ +-#define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */ +-#define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */ +-#define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */ +-#define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */ +-#define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */ +-#define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */ +-#define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */ +-#define GG82563_PSSR_SPEED_MASK 0xC000 +-#define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */ +-#define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */ +-#define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */ +- +-/* PHY Specific Status Register 2 (Page 0, Register 19) */ +-#define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */ +-#define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */ +-#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */ +-#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */ +-#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */ +-#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */ +-#define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */ +-#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */ +-#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */ +-#define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */ +-#define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */ +-#define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */ +-#define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */ +- +-/* PHY Specific Control Register 2 (Page 0, Register 26) */ +-#define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative Polarity */ +-#define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C +-#define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal Operation */ +-#define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns Sequence */ +-#define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns Sequence */ +-#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */ +-#define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 1000BASE-T */ +-#define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000 +-#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */ +-#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */ +- +-/* MAC Specific Control Register (Page 2, Register 21) */ +-/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ +-#define GG82563_MSCR_TX_CLK_MASK 0x0007 +-#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004 +-#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005 +-#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006 +-#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007 +- +-#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ +- +-/* DSP Distance Register (Page 5, Register 26) */ +-#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; +- 1 = 50-80M; +- 2 = 80-110M; +- 3 = 110-140M; +- 4 = >140M */ +- +-/* Kumeran Mode Control Register (Page 193, Register 16) */ +-#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */ +-#define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */ +-#define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080 +-#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400 +-#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 0=0.8MHz */ +-#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 +- +-/* Power Management Control Register (Page 193, Register 20) */ +-#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES Electrical Idle */ +-#define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */ +-#define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */ +-#define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse Auto-Negotiation */ +-#define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */ +-#define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */ +-#define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */ +-#define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */ +-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300 +-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */ +-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */ +-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */ +-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */ +- +-/* In-Band Control Register (Page 194, Register 18) */ +-#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */ +- +- +-/* Bit definitions for valid PHY IDs. */ +-/* I = Integrated +- * E = External +- */ +-#define M88_VENDOR 0x0141 +-#define M88E1000_E_PHY_ID 0x01410C50 +-#define M88E1000_I_PHY_ID 0x01410C30 +-#define M88E1011_I_PHY_ID 0x01410C20 +-#define IGP01E1000_I_PHY_ID 0x02A80380 +-#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID +-#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID +-#define M88E1011_I_REV_4 0x04 +-#define M88E1111_I_PHY_ID 0x01410CC0 +-#define L1LXT971A_PHY_ID 0x001378E0 +-#define GG82563_E_PHY_ID 0x01410CA0 +- +- +-/* Bits... +- * 15-5: page +- * 4-0: register offset +- */ +-#define PHY_PAGE_SHIFT 5 +-#define PHY_REG(page, reg) \ +- (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) +- +-#define IGP3_PHY_PORT_CTRL \ +- PHY_REG(769, 17) /* Port General Configuration */ +-#define IGP3_PHY_RATE_ADAPT_CTRL \ +- PHY_REG(769, 25) /* Rate Adapter Control Register */ +- +-#define IGP3_KMRN_FIFO_CTRL_STATS \ +- PHY_REG(770, 16) /* KMRN FIFO's control/status register */ +-#define IGP3_KMRN_POWER_MNG_CTRL \ +- PHY_REG(770, 17) /* KMRN Power Management Control Register */ +-#define IGP3_KMRN_INBAND_CTRL \ +- PHY_REG(770, 18) /* KMRN Inband Control Register */ +-#define IGP3_KMRN_DIAG \ +- PHY_REG(770, 19) /* KMRN Diagnostic register */ +-#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */ +-#define IGP3_KMRN_ACK_TIMEOUT \ +- PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */ +- +-#define IGP3_VR_CTRL \ +- PHY_REG(776, 18) /* Voltage regulator control register */ +-#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */ +-#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */ +- +-#define IGP3_CAPABILITY \ +- PHY_REG(776, 19) /* IGP3 Capability Register */ +- +-/* Capabilities for SKU Control */ +-#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */ +-#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */ +-#define IGP3_CAP_ASF 0x0004 /* Support ASF */ +-#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */ +-#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */ +-#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */ +-#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */ +-#define IGP3_CAP_RSS 0x0080 /* Support RSS */ +-#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */ +-#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */ +- +-#define IGP3_PPC_JORDAN_EN 0x0001 +-#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002 +- +-#define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001 +-#define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E +-#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020 +-#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040 +- +-#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */ +-#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */ +- +-#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18) +-#define IGP3_KMRN_EC_DIS_INBAND 0x0080 +- +-#define IGP03E1000_E_PHY_ID 0x02A80390 +-#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */ +-#define IFE_PLUS_E_PHY_ID 0x02A80320 +-#define IFE_C_E_PHY_ID 0x02A80310 +- +-#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */ +-#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */ +-#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */ +-#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */ +-#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */ +-#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */ +-#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */ +-#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */ +-#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */ +-#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */ +-#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */ +-#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ +-#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */ +- +-#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */ +-#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */ +-#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */ +-#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */ +-#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */ +-#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */ +-#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */ +-#define IFE_PESC_POLARITY_REVERSED_SHIFT 8 +- +-#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */ +-#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */ +-#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */ +-#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */ +-#define IFE_PSC_FORCE_POLARITY_SHIFT 5 +-#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4 +- +-#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */ +-#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */ +-#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ +-#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */ +-#define IFE_PMC_MDIX_MODE_SHIFT 6 +-#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */ +- +-#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */ +-#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */ +-#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */ +-#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */ +-#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */ +-#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */ +-#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */ +-#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */ +-#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */ +-#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ +-#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ +- +-#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ +-#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ +-#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ +-#define ICH_FLASH_SEG_SIZE_256 256 +-#define ICH_FLASH_SEG_SIZE_4K 4096 +-#define ICH_FLASH_SEG_SIZE_64K 65536 +- +-#define ICH_CYCLE_READ 0x0 +-#define ICH_CYCLE_RESERVED 0x1 +-#define ICH_CYCLE_WRITE 0x2 +-#define ICH_CYCLE_ERASE 0x3 +- +-#define ICH_FLASH_GFPREG 0x0000 +-#define ICH_FLASH_HSFSTS 0x0004 +-#define ICH_FLASH_HSFCTL 0x0006 +-#define ICH_FLASH_FADDR 0x0008 +-#define ICH_FLASH_FDATA0 0x0010 +-#define ICH_FLASH_FRACC 0x0050 +-#define ICH_FLASH_FREG0 0x0054 +-#define ICH_FLASH_FREG1 0x0058 +-#define ICH_FLASH_FREG2 0x005C +-#define ICH_FLASH_FREG3 0x0060 +-#define ICH_FLASH_FPR0 0x0074 +-#define ICH_FLASH_FPR1 0x0078 +-#define ICH_FLASH_SSFSTS 0x0090 +-#define ICH_FLASH_SSFCTL 0x0092 +-#define ICH_FLASH_PREOP 0x0094 +-#define ICH_FLASH_OPTYPE 0x0096 +-#define ICH_FLASH_OPMENU 0x0098 +- +-#define ICH_FLASH_REG_MAPSIZE 0x00A0 +-#define ICH_FLASH_SECTOR_SIZE 4096 +-#define ICH_GFPREG_BASE_MASK 0x1FFF +-#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF +- +-/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ +-/* Offset 04h HSFSTS */ +-union ich8_hws_flash_status { +- struct ich8_hsfsts { +-#ifdef __BIG_ENDIAN +- u16 reserved2 :6; +- u16 fldesvalid :1; +- u16 flockdn :1; +- u16 flcdone :1; +- u16 flcerr :1; +- u16 dael :1; +- u16 berasesz :2; +- u16 flcinprog :1; +- u16 reserved1 :2; +-#else +- u16 flcdone :1; /* bit 0 Flash Cycle Done */ +- u16 flcerr :1; /* bit 1 Flash Cycle Error */ +- u16 dael :1; /* bit 2 Direct Access error Log */ +- u16 berasesz :2; /* bit 4:3 Block/Sector Erase Size */ +- u16 flcinprog :1; /* bit 5 flash SPI cycle in Progress */ +- u16 reserved1 :2; /* bit 13:6 Reserved */ +- u16 reserved2 :6; /* bit 13:6 Reserved */ +- u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ +- u16 flockdn :1; /* bit 15 Flash Configuration Lock-Down */ +-#endif +- } hsf_status; +- u16 regval; ++/* Host Interface "Rev 1" */ ++struct e1000_host_command_header { ++ u8 command_id; ++ u8 command_length; ++ u8 command_options; ++ u8 checksum; + }; + +-/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */ +-/* Offset 06h FLCTL */ +-union ich8_hws_flash_ctrl { +- struct ich8_hsflctl { +-#ifdef __BIG_ENDIAN +- u16 fldbcount :2; +- u16 flockdn :6; +- u16 flcgo :1; +- u16 flcycle :2; +- u16 reserved :5; +-#else +- u16 flcgo :1; /* 0 Flash Cycle Go */ +- u16 flcycle :2; /* 2:1 Flash Cycle */ +- u16 reserved :5; /* 7:3 Reserved */ +- u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ +- u16 flockdn :6; /* 15:10 Reserved */ +-#endif +- } hsf_ctrl; +- u16 regval; ++#define E1000_HI_MAX_DATA_LENGTH 252 ++struct e1000_host_command_info { ++ struct e1000_host_command_header command_header; ++ u8 command_data[E1000_HI_MAX_DATA_LENGTH]; + }; + +-/* ICH8 Flash Region Access Permissions */ +-union ich8_hws_flash_regacc { +- struct ich8_flracc { +-#ifdef __BIG_ENDIAN +- u32 gmwag :8; +- u32 gmrag :8; +- u32 grwa :8; +- u32 grra :8; +-#else +- u32 grra :8; /* 0:7 GbE region Read Access */ +- u32 grwa :8; /* 8:15 GbE region Write Access */ +- u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ +- u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ +-#endif +- } hsf_flregacc; +- u16 regval; ++/* Host Interface "Rev 2" */ ++struct e1000_host_mng_command_header { ++ u8 command_id; ++ u8 checksum; ++ u16 reserved1; ++ u16 reserved2; ++ u16 command_length; + }; + +-/* Miscellaneous PHY bit definitions. */ +-#define PHY_PREAMBLE 0xFFFFFFFF +-#define PHY_SOF 0x01 +-#define PHY_OP_READ 0x02 +-#define PHY_OP_WRITE 0x01 +-#define PHY_TURNAROUND 0x02 +-#define PHY_PREAMBLE_SIZE 32 +-#define MII_CR_SPEED_1000 0x0040 +-#define MII_CR_SPEED_100 0x2000 +-#define MII_CR_SPEED_10 0x0000 +-#define E1000_PHY_ADDRESS 0x01 +-#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ +-#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ +-#define PHY_REVISION_MASK 0xFFFFFFF0 +-#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ +-#define REG4_SPEED_MASK 0x01E0 +-#define REG9_SPEED_MASK 0x0300 +-#define ADVERTISE_10_HALF 0x0001 +-#define ADVERTISE_10_FULL 0x0002 +-#define ADVERTISE_100_HALF 0x0004 +-#define ADVERTISE_100_FULL 0x0008 +-#define ADVERTISE_1000_HALF 0x0010 +-#define ADVERTISE_1000_FULL 0x0020 +-#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ +-#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ +-#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ ++#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 ++struct e1000_host_mng_command_info { ++ struct e1000_host_mng_command_header command_header; ++ u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; ++}; + +-#endif /* _E1000_HW_H_ */ ++#include "e1000_mac.h" ++#include "e1000_phy.h" ++#include "e1000_nvm.h" ++#include "e1000_manage.h" ++ ++struct e1000_mac_operations { ++ /* Function pointers for the MAC. */ ++ s32 (*init_params)(struct e1000_hw *); ++ s32 (*id_led_init)(struct e1000_hw *); ++ s32 (*blink_led)(struct e1000_hw *); ++ s32 (*check_for_link)(struct e1000_hw *); ++ bool (*check_mng_mode)(struct e1000_hw *hw); ++ s32 (*cleanup_led)(struct e1000_hw *); ++ void (*clear_hw_cntrs)(struct e1000_hw *); ++ void (*clear_vfta)(struct e1000_hw *); ++ s32 (*get_bus_info)(struct e1000_hw *); ++ void (*set_lan_id)(struct e1000_hw *); ++ s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); ++ s32 (*led_on)(struct e1000_hw *); ++ s32 (*led_off)(struct e1000_hw *); ++ void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); ++ s32 (*reset_hw)(struct e1000_hw *); ++ s32 (*init_hw)(struct e1000_hw *); ++ s32 (*setup_link)(struct e1000_hw *); ++ s32 (*setup_physical_interface)(struct e1000_hw *); ++ s32 (*setup_led)(struct e1000_hw *); ++ void (*write_vfta)(struct e1000_hw *, u32, u32); ++ void (*mta_set)(struct e1000_hw *, u32); ++ void (*config_collision_dist)(struct e1000_hw *); ++ void (*rar_set)(struct e1000_hw *, u8*, u32); ++ s32 (*read_mac_addr)(struct e1000_hw *); ++ s32 (*validate_mdi_setting)(struct e1000_hw *); ++ s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); ++ s32 (*mng_write_cmd_header)(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header*); ++ s32 (*mng_enable_host_if)(struct e1000_hw *); ++ s32 (*wait_autoneg)(struct e1000_hw *); ++}; ++ ++struct e1000_phy_operations { ++ s32 (*init_params)(struct e1000_hw *); ++ s32 (*acquire)(struct e1000_hw *); ++ s32 (*check_polarity)(struct e1000_hw *); ++ s32 (*check_reset_block)(struct e1000_hw *); ++ s32 (*commit)(struct e1000_hw *); ++ s32 (*force_speed_duplex)(struct e1000_hw *); ++ s32 (*get_cfg_done)(struct e1000_hw *hw); ++ s32 (*get_cable_length)(struct e1000_hw *); ++ s32 (*get_info)(struct e1000_hw *); ++ s32 (*read_reg)(struct e1000_hw *, u32, u16 *); ++ void (*release)(struct e1000_hw *); ++ s32 (*reset)(struct e1000_hw *); ++ s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); ++ s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); ++ s32 (*write_reg)(struct e1000_hw *, u32, u16); ++ void (*power_up)(struct e1000_hw *); ++ void (*power_down)(struct e1000_hw *); ++}; ++ ++struct e1000_nvm_operations { ++ s32 (*init_params)(struct e1000_hw *); ++ s32 (*acquire)(struct e1000_hw *); ++ s32 (*read)(struct e1000_hw *, u16, u16, u16 *); ++ void (*release)(struct e1000_hw *); ++ void (*reload)(struct e1000_hw *); ++ s32 (*update)(struct e1000_hw *); ++ s32 (*valid_led_default)(struct e1000_hw *, u16 *); ++ s32 (*validate)(struct e1000_hw *); ++ s32 (*write)(struct e1000_hw *, u16, u16, u16 *); ++}; ++ ++struct e1000_mac_info { ++ struct e1000_mac_operations ops; ++ u8 addr[6]; ++ u8 perm_addr[6]; ++ ++ enum e1000_mac_type type; ++ ++ u32 collision_delta; ++ u32 ledctl_default; ++ u32 ledctl_mode1; ++ u32 ledctl_mode2; ++ u32 mc_filter_type; ++ u32 tx_packet_delta; ++ u32 txcw; ++ ++ u16 current_ifs_val; ++ u16 ifs_max_val; ++ u16 ifs_min_val; ++ u16 ifs_ratio; ++ u16 ifs_step_size; ++ u16 mta_reg_count; ++ ++ /* Maximum size of the MTA register table in all supported adapters */ ++ #define MAX_MTA_REG 128 ++ u32 mta_shadow[MAX_MTA_REG]; ++ u16 rar_entry_count; ++ ++ u8 forced_speed_duplex; ++ ++ bool adaptive_ifs; ++ bool arc_subsystem_valid; ++ bool asf_firmware_present; ++ bool autoneg; ++ bool autoneg_failed; ++ bool get_link_status; ++ bool in_ifs_mode; ++ bool report_tx_early; ++ enum e1000_serdes_link_state serdes_link_state; ++ bool serdes_has_link; ++ bool tx_pkt_filtering; ++}; ++ ++struct e1000_phy_info { ++ struct e1000_phy_operations ops; ++ enum e1000_phy_type type; ++ ++ enum e1000_1000t_rx_status local_rx; ++ enum e1000_1000t_rx_status remote_rx; ++ enum e1000_ms_type ms_type; ++ enum e1000_ms_type original_ms_type; ++ enum e1000_rev_polarity cable_polarity; ++ enum e1000_smart_speed smart_speed; ++ ++ u32 addr; ++ u32 id; ++ u32 reset_delay_us; /* in usec */ ++ u32 revision; ++ ++ enum e1000_media_type media_type; ++ ++ u16 autoneg_advertised; ++ u16 autoneg_mask; ++ u16 cable_length; ++ u16 max_cable_length; ++ u16 min_cable_length; ++ ++ u8 mdix; ++ ++ bool disable_polarity_correction; ++ bool is_mdix; ++ bool polarity_correction; ++ bool reset_disable; ++ bool speed_downgraded; ++ bool autoneg_wait_to_complete; ++}; ++ ++struct e1000_nvm_info { ++ struct e1000_nvm_operations ops; ++ enum e1000_nvm_type type; ++ enum e1000_nvm_override override; ++ ++ u32 flash_bank_size; ++ u32 flash_base_addr; ++ ++ u16 word_size; ++ u16 delay_usec; ++ u16 address_bits; ++ u16 opcode_bits; ++ u16 page_size; ++}; ++ ++struct e1000_bus_info { ++ enum e1000_bus_type type; ++ enum e1000_bus_speed speed; ++ enum e1000_bus_width width; ++ ++ u16 func; ++ u16 pci_cmd_word; ++}; ++ ++struct e1000_fc_info { ++ u32 high_water; /* Flow control high-water mark */ ++ u32 low_water; /* Flow control low-water mark */ ++ u16 pause_time; /* Flow control pause timer */ ++ bool send_xon; /* Flow control send XON */ ++ bool strict_ieee; /* Strict IEEE mode */ ++ enum e1000_fc_mode current_mode; /* FC mode in effect */ ++ enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ ++}; ++ ++struct e1000_dev_spec_82541 { ++ enum e1000_dsp_config dsp_config; ++ enum e1000_ffe_config ffe_config; ++ u16 spd_default; ++ bool phy_init_script; ++}; ++ ++struct e1000_dev_spec_82542 { ++ bool dma_fairness; ++}; ++ ++struct e1000_dev_spec_82543 { ++ u32 tbi_compatibility; ++ bool dma_fairness; ++ bool init_phy_disabled; ++}; ++ ++struct e1000_hw { ++ void *back; ++ ++ u8 __iomem *hw_addr; ++ u8 __iomem *flash_address; ++ unsigned long io_base; ++ ++ struct e1000_mac_info mac; ++ struct e1000_fc_info fc; ++ struct e1000_phy_info phy; ++ struct e1000_nvm_info nvm; ++ struct e1000_bus_info bus; ++ struct e1000_host_mng_dhcp_cookie mng_cookie; ++ ++ union { ++ struct e1000_dev_spec_82541 _82541; ++ struct e1000_dev_spec_82542 _82542; ++ struct e1000_dev_spec_82543 _82543; ++ } dev_spec; ++ ++ u16 device_id; ++ u16 subsystem_vendor_id; ++ u16 subsystem_device_id; ++ u16 vendor_id; ++ ++ u8 revision_id; ++}; ++ ++#include "e1000_82541.h" ++#include "e1000_82543.h" ++ ++/* These functions must be implemented by drivers */ ++void e1000_pci_clear_mwi(struct e1000_hw *hw); ++void e1000_pci_set_mwi(struct e1000_hw *hw); ++s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); ++void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); ++void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); ++ ++#endif +diff -r b58885ce604a drivers/net/e1000/e1000_ich8lan.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_ich8lan.h Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,109 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_ICH8LAN_H_ ++#define _E1000_ICH8LAN_H_ ++ ++#define ICH_FLASH_GFPREG 0x0000 ++#define ICH_FLASH_HSFSTS 0x0004 ++#define ICH_FLASH_HSFCTL 0x0006 ++#define ICH_FLASH_FADDR 0x0008 ++#define ICH_FLASH_FDATA0 0x0010 ++ ++#define ICH_FLASH_READ_COMMAND_TIMEOUT 500 ++#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500 ++#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000 ++#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF ++#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 ++ ++#define ICH_CYCLE_READ 0 ++#define ICH_CYCLE_WRITE 2 ++#define ICH_CYCLE_ERASE 3 ++ ++#define FLASH_GFPREG_BASE_MASK 0x1FFF ++#define FLASH_SECTOR_ADDR_SHIFT 12 ++ ++#define E1000_SHADOW_RAM_WORDS 2048 ++ ++#define ICH_FLASH_SEG_SIZE_256 256 ++#define ICH_FLASH_SEG_SIZE_4K 4096 ++#define ICH_FLASH_SEG_SIZE_8K 8192 ++#define ICH_FLASH_SEG_SIZE_64K 65536 ++#define ICH_FLASH_SECTOR_SIZE 4096 ++ ++#define ICH_FLASH_REG_MAPSIZE 0x00A0 ++ ++#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ ++#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */ ++/* FW established a valid mode */ ++#define E1000_ICH_FWSM_FW_VALID 0x00008000 ++ ++#define E1000_ICH_MNG_IAMT_MODE 0x2 ++ ++#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ ++ (ID_LED_DEF1_OFF2 << 8) | \ ++ (ID_LED_DEF1_ON2 << 4) | \ ++ (ID_LED_DEF1_DEF2)) ++ ++#define E1000_ICH_NVM_SIG_WORD 0x13 ++#define E1000_ICH_NVM_SIG_MASK 0xC000 ++ ++#define E1000_ICH8_LAN_INIT_TIMEOUT 1500 ++ ++#define E1000_FEXTNVM_SW_CONFIG 1 ++#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ ++ ++#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL ++ ++#define E1000_ICH_RAR_ENTRIES 7 ++ ++#define PHY_PAGE_SHIFT 5 ++#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ ++ ((reg) & MAX_PHY_REG_ADDRESS)) ++#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ ++#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ ++#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */ ++#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */ ++ ++#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 ++#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 ++#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 ++#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020 ++ ++/* ++ * Additional interrupts need to be handled for ICH family: ++ * DSW = The FW changed the status of the DISSW bit in FWSM ++ * PHYINT = The LAN connected device generates an interrupt ++ * EPRST = Manageability reset event ++ */ ++#define IMS_ICH_ENABLE_MASK (\ ++ E1000_IMS_DSW | \ ++ E1000_IMS_PHYINT | \ ++ E1000_IMS_EPRST) ++ ++#endif +diff -r b58885ce604a drivers/net/e1000/e1000_mac.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_mac.c Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,2157 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000_api.h" ++ ++static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); ++static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); ++ ++/** ++ * e1000_init_mac_ops_generic - Initialize MAC function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Setups up the function pointers to no-op functions ++ **/ ++void e1000_init_mac_ops_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ DEBUGFUNC("e1000_init_mac_ops_generic"); ++ ++ /* General Setup */ ++ mac->ops.init_params = e1000_null_ops_generic; ++ mac->ops.init_hw = e1000_null_ops_generic; ++ mac->ops.reset_hw = e1000_null_ops_generic; ++ mac->ops.setup_physical_interface = e1000_null_ops_generic; ++ mac->ops.get_bus_info = e1000_null_ops_generic; ++ mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; ++ mac->ops.read_mac_addr = e1000_read_mac_addr_generic; ++ mac->ops.config_collision_dist = e1000_config_collision_dist_generic; ++ mac->ops.clear_hw_cntrs = e1000_null_mac_generic; ++ /* LED */ ++ mac->ops.cleanup_led = e1000_null_ops_generic; ++ mac->ops.setup_led = e1000_null_ops_generic; ++ mac->ops.blink_led = e1000_null_ops_generic; ++ mac->ops.led_on = e1000_null_ops_generic; ++ mac->ops.led_off = e1000_null_ops_generic; ++ /* LINK */ ++ mac->ops.setup_link = e1000_null_ops_generic; ++ mac->ops.get_link_up_info = e1000_null_link_info; ++ mac->ops.check_for_link = e1000_null_ops_generic; ++ mac->ops.wait_autoneg = e1000_wait_autoneg_generic; ++ /* Management */ ++ mac->ops.check_mng_mode = e1000_null_mng_mode; ++ mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; ++ mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; ++ mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; ++ /* VLAN, MC, etc. */ ++ mac->ops.update_mc_addr_list = e1000_null_update_mc; ++ mac->ops.clear_vfta = e1000_null_mac_generic; ++ mac->ops.write_vfta = e1000_null_write_vfta; ++ mac->ops.mta_set = e1000_null_mta_set; ++ mac->ops.rar_set = e1000_rar_set_generic; ++ mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; ++} ++ ++/** ++ * e1000_null_ops_generic - No-op function, returns 0 ++ * @hw: pointer to the HW structure ++ **/ ++s32 e1000_null_ops_generic(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_null_ops_generic"); ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_null_mac_generic - No-op function, return void ++ * @hw: pointer to the HW structure ++ **/ ++void e1000_null_mac_generic(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_null_mac_generic"); ++ return; ++} ++ ++/** ++ * e1000_null_link_info - No-op function, return 0 ++ * @hw: pointer to the HW structure ++ **/ ++s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) ++{ ++ DEBUGFUNC("e1000_null_link_info"); ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_null_mng_mode - No-op function, return false ++ * @hw: pointer to the HW structure ++ **/ ++bool e1000_null_mng_mode(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_null_mng_mode"); ++ return false; ++} ++ ++/** ++ * e1000_null_update_mc - No-op function, return void ++ * @hw: pointer to the HW structure ++ **/ ++void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) ++{ ++ DEBUGFUNC("e1000_null_update_mc"); ++ return; ++} ++ ++/** ++ * e1000_null_write_vfta - No-op function, return void ++ * @hw: pointer to the HW structure ++ **/ ++void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) ++{ ++ DEBUGFUNC("e1000_null_write_vfta"); ++ return; ++} ++ ++/** ++ * e1000_null_set_mta - No-op function, return void ++ * @hw: pointer to the HW structure ++ **/ ++void e1000_null_mta_set(struct e1000_hw *hw, u32 a) ++{ ++ DEBUGFUNC("e1000_null_mta_set"); ++ return; ++} ++ ++/** ++ * e1000_null_rar_set - No-op function, return void ++ * @hw: pointer to the HW structure ++ **/ ++void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) ++{ ++ DEBUGFUNC("e1000_null_rar_set"); ++ return; ++} ++ ++/** ++ * e1000_get_bus_info_pci_generic - Get PCI(x) bus information ++ * @hw: pointer to the HW structure ++ * ++ * Determines and stores the system bus information for a particular ++ * network interface. The following bus information is determined and stored: ++ * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. ++ **/ ++s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ struct e1000_bus_info *bus = &hw->bus; ++ u32 status = E1000_READ_REG(hw, E1000_STATUS); ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_get_bus_info_pci_generic"); ++ ++ /* PCI or PCI-X? */ ++ bus->type = (status & E1000_STATUS_PCIX_MODE) ++ ? e1000_bus_type_pcix ++ : e1000_bus_type_pci; ++ ++ /* Bus speed */ ++ if (bus->type == e1000_bus_type_pci) { ++ bus->speed = (status & E1000_STATUS_PCI66) ++ ? e1000_bus_speed_66 ++ : e1000_bus_speed_33; ++ } else { ++ switch (status & E1000_STATUS_PCIX_SPEED) { ++ case E1000_STATUS_PCIX_SPEED_66: ++ bus->speed = e1000_bus_speed_66; ++ break; ++ case E1000_STATUS_PCIX_SPEED_100: ++ bus->speed = e1000_bus_speed_100; ++ break; ++ case E1000_STATUS_PCIX_SPEED_133: ++ bus->speed = e1000_bus_speed_133; ++ break; ++ default: ++ bus->speed = e1000_bus_speed_reserved; ++ break; ++ } ++ } ++ ++ /* Bus width */ ++ bus->width = (status & E1000_STATUS_BUS64) ++ ? e1000_bus_width_64 ++ : e1000_bus_width_32; ++ ++ /* Which PCI(-X) function? */ ++ mac->ops.set_lan_id(hw); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_get_bus_info_pcie_generic - Get PCIe bus information ++ * @hw: pointer to the HW structure ++ * ++ * Determines and stores the system bus information for a particular ++ * network interface. The following bus information is determined and stored: ++ * bus speed, bus width, type (PCIe), and PCIe function. ++ **/ ++s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ struct e1000_bus_info *bus = &hw->bus; ++ ++ s32 ret_val; ++ u16 pcie_link_status; ++ ++ DEBUGFUNC("e1000_get_bus_info_pcie_generic"); ++ ++ bus->type = e1000_bus_type_pci_express; ++ bus->speed = e1000_bus_speed_2500; ++ ++ ret_val = e1000_read_pcie_cap_reg(hw, ++ PCIE_LINK_STATUS, ++ &pcie_link_status); ++ if (ret_val) ++ bus->width = e1000_bus_width_unknown; ++ else ++ bus->width = (enum e1000_bus_width)((pcie_link_status & ++ PCIE_LINK_WIDTH_MASK) >> ++ PCIE_LINK_WIDTH_SHIFT); ++ ++ mac->ops.set_lan_id(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices ++ * ++ * @hw: pointer to the HW structure ++ * ++ * Determines the LAN function id by reading memory-mapped registers ++ * and swaps the port value if requested. ++ **/ ++static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) ++{ ++ struct e1000_bus_info *bus = &hw->bus; ++ u32 reg; ++ ++ /* ++ * The status register reports the correct function number ++ * for the device regardless of function swap state. ++ */ ++ reg = E1000_READ_REG(hw, E1000_STATUS); ++ bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; ++} ++ ++/** ++ * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices ++ * @hw: pointer to the HW structure ++ * ++ * Determines the LAN function id by reading PCI config space. ++ **/ ++void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) ++{ ++ struct e1000_bus_info *bus = &hw->bus; ++ u16 pci_header_type; ++ u32 status; ++ ++ e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); ++ if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { ++ status = E1000_READ_REG(hw, E1000_STATUS); ++ bus->func = (status & E1000_STATUS_FUNC_MASK) ++ >> E1000_STATUS_FUNC_SHIFT; ++ } else { ++ bus->func = 0; ++ } ++} ++ ++/** ++ * e1000_set_lan_id_single_port - Set LAN id for a single port device ++ * @hw: pointer to the HW structure ++ * ++ * Sets the LAN function id to zero for a single port device. ++ **/ ++void e1000_set_lan_id_single_port(struct e1000_hw *hw) ++{ ++ struct e1000_bus_info *bus = &hw->bus; ++ ++ bus->func = 0; ++} ++ ++/** ++ * e1000_clear_vfta_generic - Clear VLAN filter table ++ * @hw: pointer to the HW structure ++ * ++ * Clears the register array which contains the VLAN filter table by ++ * setting all the values to 0. ++ **/ ++void e1000_clear_vfta_generic(struct e1000_hw *hw) ++{ ++ u32 offset; ++ ++ DEBUGFUNC("e1000_clear_vfta_generic"); ++ ++ for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { ++ E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); ++ E1000_WRITE_FLUSH(hw); ++ } ++} ++ ++/** ++ * e1000_write_vfta_generic - Write value to VLAN filter table ++ * @hw: pointer to the HW structure ++ * @offset: register offset in VLAN filter table ++ * @value: register value written to VLAN filter table ++ * ++ * Writes value at the given offset in the register array which stores ++ * the VLAN filter table. ++ **/ ++void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) ++{ ++ DEBUGFUNC("e1000_write_vfta_generic"); ++ ++ E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); ++ E1000_WRITE_FLUSH(hw); ++} ++ ++/** ++ * e1000_init_rx_addrs_generic - Initialize receive address's ++ * @hw: pointer to the HW structure ++ * @rar_count: receive address registers ++ * ++ * Setups the receive address registers by setting the base receive address ++ * register to the devices MAC address and clearing all the other receive ++ * address registers to 0. ++ **/ ++void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) ++{ ++ u32 i; ++ u8 mac_addr[ETH_ADDR_LEN] = {0}; ++ ++ DEBUGFUNC("e1000_init_rx_addrs_generic"); ++ ++ /* Setup the receive address */ ++ DEBUGOUT("Programming MAC Address into RAR[0]\n"); ++ ++ hw->mac.ops.rar_set(hw, hw->mac.addr, 0); ++ ++ /* Zero out the other (rar_entry_count - 1) receive addresses */ ++ DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); ++ for (i = 1; i < rar_count; i++) ++ hw->mac.ops.rar_set(hw, mac_addr, i); ++} ++ ++/** ++ * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr ++ * @hw: pointer to the HW structure ++ * ++ * Checks the nvm for an alternate MAC address. An alternate MAC address ++ * can be setup by pre-boot software and must be treated like a permanent ++ * address and must override the actual permanent MAC address. If an ++ * alternate MAC address is found it is programmed into RAR0, replacing ++ * the permanent address that was installed into RAR0 by the Si on reset. ++ * This function will return SUCCESS unless it encounters an error while ++ * reading the EEPROM. ++ **/ ++s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) ++{ ++ u32 i; ++ s32 ret_val = E1000_SUCCESS; ++ u16 offset, nvm_alt_mac_addr_offset, nvm_data; ++ u8 alt_mac_addr[ETH_ADDR_LEN]; ++ ++ DEBUGFUNC("e1000_check_alt_mac_addr_generic"); ++ ++ ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, ++ &nvm_alt_mac_addr_offset); ++ if (ret_val) { ++ DEBUGOUT("NVM Read Error\n"); ++ goto out; ++ } ++ ++ if (nvm_alt_mac_addr_offset == 0xFFFF) { ++ /* There is no Alternate MAC Address */ ++ goto out; ++ } ++ ++ if (hw->bus.func == E1000_FUNC_1) ++ nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; ++ for (i = 0; i < ETH_ADDR_LEN; i += 2) { ++ offset = nvm_alt_mac_addr_offset + (i >> 1); ++ ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); ++ if (ret_val) { ++ DEBUGOUT("NVM Read Error\n"); ++ goto out; ++ } ++ ++ alt_mac_addr[i] = (u8)(nvm_data & 0xFF); ++ alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); ++ } ++ ++ /* if multicast bit is set, the alternate address will not be used */ ++ if (alt_mac_addr[0] & 0x01) { ++ DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); ++ goto out; ++ } ++ ++ /* ++ * We have a valid alternate MAC address, and we want to treat it the ++ * same as the normal permanent MAC address stored by the HW into the ++ * RAR. Do this by mapping this address into RAR0. ++ */ ++ hw->mac.ops.rar_set(hw, alt_mac_addr, 0); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_rar_set_generic - Set receive address register ++ * @hw: pointer to the HW structure ++ * @addr: pointer to the receive address ++ * @index: receive address array register ++ * ++ * Sets the receive address array register at index to the address passed ++ * in by addr. ++ **/ ++void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) ++{ ++ u32 rar_low, rar_high; ++ ++ DEBUGFUNC("e1000_rar_set_generic"); ++ ++ /* ++ * HW expects these in little endian so we reverse the byte order ++ * from network order (big endian) to little endian ++ */ ++ rar_low = ((u32) addr[0] | ++ ((u32) addr[1] << 8) | ++ ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); ++ ++ rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); ++ ++ /* If MAC address zero, no need to set the AV bit */ ++ if (rar_low || rar_high) ++ rar_high |= E1000_RAH_AV; ++ ++ /* ++ * Some bridges will combine consecutive 32-bit writes into ++ * a single burst write, which will malfunction on some parts. ++ * The flushes avoid this. ++ */ ++ E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); ++ E1000_WRITE_FLUSH(hw); ++ E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); ++ E1000_WRITE_FLUSH(hw); ++} ++ ++/** ++ * e1000_mta_set_generic - Set multicast filter table address ++ * @hw: pointer to the HW structure ++ * @hash_value: determines the MTA register and bit to set ++ * ++ * The multicast table address is a register array of 32-bit registers. ++ * The hash_value is used to determine what register the bit is in, the ++ * current value is read, the new bit is OR'd in and the new value is ++ * written back into the register. ++ **/ ++void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) ++{ ++ u32 hash_bit, hash_reg, mta; ++ ++ DEBUGFUNC("e1000_mta_set_generic"); ++ /* ++ * The MTA is a register array of 32-bit registers. It is ++ * treated like an array of (32*mta_reg_count) bits. We want to ++ * set bit BitArray[hash_value]. So we figure out what register ++ * the bit is in, read it, OR in the new bit, then write ++ * back the new value. The (hw->mac.mta_reg_count - 1) serves as a ++ * mask to bits 31:5 of the hash value which gives us the ++ * register we're modifying. The hash bit within that register ++ * is determined by the lower 5 bits of the hash value. ++ */ ++ hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); ++ hash_bit = hash_value & 0x1F; ++ ++ mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); ++ ++ mta |= (1 << hash_bit); ++ ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); ++ E1000_WRITE_FLUSH(hw); ++} ++ ++/** ++ * e1000_update_mc_addr_list_generic - Update Multicast addresses ++ * @hw: pointer to the HW structure ++ * @mc_addr_list: array of multicast addresses to program ++ * @mc_addr_count: number of multicast addresses to program ++ * ++ * Updates entire Multicast Table Array. ++ * The caller must have a packed mc_addr_list of multicast addresses. ++ **/ ++void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, ++ u8 *mc_addr_list, u32 mc_addr_count) ++{ ++ u32 hash_value, hash_bit, hash_reg; ++ int i; ++ ++ DEBUGFUNC("e1000_update_mc_addr_list_generic"); ++ ++ /* clear mta_shadow */ ++ memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); ++ ++ /* update mta_shadow from mc_addr_list */ ++ for (i = 0; (u32) i < mc_addr_count; i++) { ++ hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); ++ ++ hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); ++ hash_bit = hash_value & 0x1F; ++ ++ hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); ++ mc_addr_list += (ETH_ADDR_LEN); ++ } ++ ++ /* replace the entire MTA table */ ++ for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); ++ E1000_WRITE_FLUSH(hw); ++} ++ ++/** ++ * e1000_hash_mc_addr_generic - Generate a multicast hash value ++ * @hw: pointer to the HW structure ++ * @mc_addr: pointer to a multicast address ++ * ++ * Generates a multicast address hash value which is used to determine ++ * the multicast filter table array address and new table value. See ++ * e1000_mta_set_generic() ++ **/ ++u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) ++{ ++ u32 hash_value, hash_mask; ++ u8 bit_shift = 0; ++ ++ DEBUGFUNC("e1000_hash_mc_addr_generic"); ++ ++ /* Register count multiplied by bits per register */ ++ hash_mask = (hw->mac.mta_reg_count * 32) - 1; ++ ++ /* ++ * For a mc_filter_type of 0, bit_shift is the number of left-shifts ++ * where 0xFF would still fall within the hash mask. ++ */ ++ while (hash_mask >> bit_shift != 0xFF) ++ bit_shift++; ++ ++ /* ++ * The portion of the address that is used for the hash table ++ * is determined by the mc_filter_type setting. ++ * The algorithm is such that there is a total of 8 bits of shifting. ++ * The bit_shift for a mc_filter_type of 0 represents the number of ++ * left-shifts where the MSB of mc_addr[5] would still fall within ++ * the hash_mask. Case 0 does this exactly. Since there are a total ++ * of 8 bits of shifting, then mc_addr[4] will shift right the ++ * remaining number of bits. Thus 8 - bit_shift. The rest of the ++ * cases are a variation of this algorithm...essentially raising the ++ * number of bits to shift mc_addr[5] left, while still keeping the ++ * 8-bit shifting total. ++ * ++ * For example, given the following Destination MAC Address and an ++ * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), ++ * we can see that the bit_shift for case 0 is 4. These are the hash ++ * values resulting from each mc_filter_type... ++ * [0] [1] [2] [3] [4] [5] ++ * 01 AA 00 12 34 56 ++ * LSB MSB ++ * ++ * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 ++ * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 ++ * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 ++ * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 ++ */ ++ switch (hw->mac.mc_filter_type) { ++ default: ++ case 0: ++ break; ++ case 1: ++ bit_shift += 1; ++ break; ++ case 2: ++ bit_shift += 2; ++ break; ++ case 3: ++ bit_shift += 4; ++ break; ++ } ++ ++ hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | ++ (((u16) mc_addr[5]) << bit_shift))); ++ ++ return hash_value; ++} ++ ++/** ++ * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value ++ * @hw: pointer to the HW structure ++ * ++ * In certain situations, a system BIOS may report that the PCIx maximum ++ * memory read byte count (MMRBC) value is higher than than the actual ++ * value. We check the PCIx command register with the current PCIx status ++ * register. ++ **/ ++void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) ++{ ++ u16 cmd_mmrbc; ++ u16 pcix_cmd; ++ u16 pcix_stat_hi_word; ++ u16 stat_mmrbc; ++ ++ DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); ++ ++ /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ ++ if (hw->bus.type != e1000_bus_type_pcix) ++ return; ++ ++ e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); ++ e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); ++ cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> ++ PCIX_COMMAND_MMRBC_SHIFT; ++ stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> ++ PCIX_STATUS_HI_MMRBC_SHIFT; ++ if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) ++ stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; ++ if (cmd_mmrbc > stat_mmrbc) { ++ pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; ++ pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; ++ e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); ++ } ++} ++ ++/** ++ * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters ++ * @hw: pointer to the HW structure ++ * ++ * Clears the base hardware counters by reading the counter registers. ++ **/ ++void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); ++ ++ E1000_READ_REG(hw, E1000_CRCERRS); ++ E1000_READ_REG(hw, E1000_SYMERRS); ++ E1000_READ_REG(hw, E1000_MPC); ++ E1000_READ_REG(hw, E1000_SCC); ++ E1000_READ_REG(hw, E1000_ECOL); ++ E1000_READ_REG(hw, E1000_MCC); ++ E1000_READ_REG(hw, E1000_LATECOL); ++ E1000_READ_REG(hw, E1000_COLC); ++ E1000_READ_REG(hw, E1000_DC); ++ E1000_READ_REG(hw, E1000_SEC); ++ E1000_READ_REG(hw, E1000_RLEC); ++ E1000_READ_REG(hw, E1000_XONRXC); ++ E1000_READ_REG(hw, E1000_XONTXC); ++ E1000_READ_REG(hw, E1000_XOFFRXC); ++ E1000_READ_REG(hw, E1000_XOFFTXC); ++ E1000_READ_REG(hw, E1000_FCRUC); ++ E1000_READ_REG(hw, E1000_GPRC); ++ E1000_READ_REG(hw, E1000_BPRC); ++ E1000_READ_REG(hw, E1000_MPRC); ++ E1000_READ_REG(hw, E1000_GPTC); ++ E1000_READ_REG(hw, E1000_GORCL); ++ E1000_READ_REG(hw, E1000_GORCH); ++ E1000_READ_REG(hw, E1000_GOTCL); ++ E1000_READ_REG(hw, E1000_GOTCH); ++ E1000_READ_REG(hw, E1000_RNBC); ++ E1000_READ_REG(hw, E1000_RUC); ++ E1000_READ_REG(hw, E1000_RFC); ++ E1000_READ_REG(hw, E1000_ROC); ++ E1000_READ_REG(hw, E1000_RJC); ++ E1000_READ_REG(hw, E1000_TORL); ++ E1000_READ_REG(hw, E1000_TORH); ++ E1000_READ_REG(hw, E1000_TOTL); ++ E1000_READ_REG(hw, E1000_TOTH); ++ E1000_READ_REG(hw, E1000_TPR); ++ E1000_READ_REG(hw, E1000_TPT); ++ E1000_READ_REG(hw, E1000_MPTC); ++ E1000_READ_REG(hw, E1000_BPTC); ++} ++ ++/** ++ * e1000_check_for_copper_link_generic - Check for link (Copper) ++ * @hw: pointer to the HW structure ++ * ++ * Checks to see of the link status of the hardware has changed. If a ++ * change in link status has been detected, then we read the PHY registers ++ * to get the current speed/duplex if link exists. ++ **/ ++s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val; ++ bool link; ++ ++ DEBUGFUNC("e1000_check_for_copper_link"); ++ ++ /* ++ * We only want to go out to the PHY registers to see if Auto-Neg ++ * has completed and/or if our link status has changed. The ++ * get_link_status flag is set upon receiving a Link Status ++ * Change or Rx Sequence Error interrupt. ++ */ ++ if (!mac->get_link_status) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ /* ++ * First we want to see if the MII Status Register reports ++ * link. If so, then we want to get the current speed/duplex ++ * of the PHY. ++ */ ++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) ++ goto out; /* No link detected */ ++ ++ mac->get_link_status = false; ++ ++ /* ++ * Check if there was DownShift, must be checked ++ * immediately after link-up ++ */ ++ e1000_check_downshift_generic(hw); ++ ++ /* ++ * If we are forcing speed/duplex, then we simply return since ++ * we have already determined whether we have link or not. ++ */ ++ if (!mac->autoneg) { ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ /* ++ * Auto-Neg is enabled. Auto Speed Detection takes care ++ * of MAC speed/duplex configuration. So we only need to ++ * configure Collision Distance in the MAC. ++ */ ++ e1000_config_collision_dist_generic(hw); ++ ++ /* ++ * Configure Flow Control now that Auto-Neg has completed. ++ * First, we need to restore the desired flow control ++ * settings because we may have had to re-autoneg with a ++ * different link partner. ++ */ ++ ret_val = e1000_config_fc_after_link_up_generic(hw); ++ if (ret_val) ++ DEBUGOUT("Error configuring flow control\n"); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_for_fiber_link_generic - Check for link (Fiber) ++ * @hw: pointer to the HW structure ++ * ++ * Checks for link up on the hardware. If link is not up and we have ++ * a signal, then we need to force link up. ++ **/ ++s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 rxcw; ++ u32 ctrl; ++ u32 status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_check_for_fiber_link_generic"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ status = E1000_READ_REG(hw, E1000_STATUS); ++ rxcw = E1000_READ_REG(hw, E1000_RXCW); ++ ++ /* ++ * If we don't have link (auto-negotiation failed or link partner ++ * cannot auto-negotiate), the cable is plugged in (we have signal), ++ * and our link partner is not trying to auto-negotiate with us (we ++ * are receiving idles or data), we need to force link up. We also ++ * need to give auto-negotiation time to complete, in case the cable ++ * was just plugged in. The autoneg_failed flag does this. ++ */ ++ /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ ++ if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && ++ (!(rxcw & E1000_RXCW_C))) { ++ if (mac->autoneg_failed == 0) { ++ mac->autoneg_failed = 1; ++ goto out; ++ } ++ DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); ++ ++ /* Disable auto-negotiation in the TXCW register */ ++ E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); ++ ++ /* Force link-up and also force full-duplex. */ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++ /* Configure Flow Control after forcing link up. */ ++ ret_val = e1000_config_fc_after_link_up_generic(hw); ++ if (ret_val) { ++ DEBUGOUT("Error configuring flow control\n"); ++ goto out; ++ } ++ } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { ++ /* ++ * If we are forcing link and we are receiving /C/ ordered ++ * sets, re-enable auto-negotiation in the TXCW register ++ * and disable forced link in the Device Control register ++ * in an attempt to auto-negotiate with our link partner. ++ */ ++ DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); ++ E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); ++ E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); ++ ++ mac->serdes_has_link = true; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_for_serdes_link_generic - Check for link (Serdes) ++ * @hw: pointer to the HW structure ++ * ++ * Checks for link up on the hardware. If link is not up and we have ++ * a signal, then we need to force link up. ++ **/ ++s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 rxcw; ++ u32 ctrl; ++ u32 status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_check_for_serdes_link_generic"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ status = E1000_READ_REG(hw, E1000_STATUS); ++ rxcw = E1000_READ_REG(hw, E1000_RXCW); ++ ++ /* ++ * If we don't have link (auto-negotiation failed or link partner ++ * cannot auto-negotiate), and our link partner is not trying to ++ * auto-negotiate with us (we are receiving idles or data), ++ * we need to force link up. We also need to give auto-negotiation ++ * time to complete. ++ */ ++ /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ ++ if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { ++ if (mac->autoneg_failed == 0) { ++ mac->autoneg_failed = 1; ++ goto out; ++ } ++ DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); ++ ++ /* Disable auto-negotiation in the TXCW register */ ++ E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); ++ ++ /* Force link-up and also force full-duplex. */ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++ /* Configure Flow Control after forcing link up. */ ++ ret_val = e1000_config_fc_after_link_up_generic(hw); ++ if (ret_val) { ++ DEBUGOUT("Error configuring flow control\n"); ++ goto out; ++ } ++ } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { ++ /* ++ * If we are forcing link and we are receiving /C/ ordered ++ * sets, re-enable auto-negotiation in the TXCW register ++ * and disable forced link in the Device Control register ++ * in an attempt to auto-negotiate with our link partner. ++ */ ++ DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); ++ E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); ++ E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); ++ ++ mac->serdes_has_link = true; ++ } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { ++ /* ++ * If we force link for non-auto-negotiation switch, check ++ * link status based on MAC synchronization for internal ++ * serdes media type. ++ */ ++ /* SYNCH bit and IV bit are sticky. */ ++ usec_delay(10); ++ rxcw = E1000_READ_REG(hw, E1000_RXCW); ++ if (rxcw & E1000_RXCW_SYNCH) { ++ if (!(rxcw & E1000_RXCW_IV)) { ++ mac->serdes_has_link = true; ++ DEBUGOUT("SERDES: Link up - forced.\n"); ++ } ++ } else { ++ mac->serdes_has_link = false; ++ DEBUGOUT("SERDES: Link down - force failed.\n"); ++ } ++ } ++ ++ if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { ++ status = E1000_READ_REG(hw, E1000_STATUS); ++ if (status & E1000_STATUS_LU) { ++ /* SYNCH bit and IV bit are sticky, so reread rxcw. */ ++ usec_delay(10); ++ rxcw = E1000_READ_REG(hw, E1000_RXCW); ++ if (rxcw & E1000_RXCW_SYNCH) { ++ if (!(rxcw & E1000_RXCW_IV)) { ++ mac->serdes_has_link = true; ++ DEBUGOUT("SERDES: Link up - autoneg " ++ "completed sucessfully.\n"); ++ } else { ++ mac->serdes_has_link = false; ++ DEBUGOUT("SERDES: Link down - invalid" ++ "codewords detected in autoneg.\n"); ++ } ++ } else { ++ mac->serdes_has_link = false; ++ DEBUGOUT("SERDES: Link down - no sync.\n"); ++ } ++ } else { ++ mac->serdes_has_link = false; ++ DEBUGOUT("SERDES: Link down - autoneg failed\n"); ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_link_generic - Setup flow control and link settings ++ * @hw: pointer to the HW structure ++ * ++ * Determines which flow control settings to use, then configures flow ++ * control. Calls the appropriate media-specific link configuration ++ * function. Assuming the adapter has a valid link partner, a valid link ++ * should be established. Assumes the hardware has previously been reset ++ * and the transmitter and receiver are not enabled. ++ **/ ++s32 e1000_setup_link_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_setup_link_generic"); ++ ++ /* ++ * In the case of the phy reset being blocked, we already have a link. ++ * We do not need to set it up again. ++ */ ++ if (hw->phy.ops.check_reset_block) ++ if (hw->phy.ops.check_reset_block(hw)) ++ goto out; ++ ++ /* ++ * If requested flow control is set to default, set flow control ++ * based on the EEPROM flow control settings. ++ */ ++ if (hw->fc.requested_mode == e1000_fc_default) { ++ ret_val = e1000_set_default_fc_generic(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* ++ * Save off the requested flow control mode for use later. Depending ++ * on the link partner's capabilities, we may or may not use this mode. ++ */ ++ hw->fc.current_mode = hw->fc.requested_mode; ++ ++ DEBUGOUT1("After fix-ups FlowControl is now = %x\n", ++ hw->fc.current_mode); ++ ++ /* Call the necessary media_type subroutine to configure the link. */ ++ ret_val = hw->mac.ops.setup_physical_interface(hw); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Initialize the flow control address, type, and PAUSE timer ++ * registers to their default values. This is done even if flow ++ * control is disabled, because it does not hurt anything to ++ * initialize these registers. ++ */ ++ DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); ++ E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); ++ E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); ++ E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); ++ ++ E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); ++ ++ ret_val = e1000_set_fc_watermarks_generic(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes ++ * @hw: pointer to the HW structure ++ * ++ * Configures collision distance and flow control for fiber and serdes ++ * links. Upon successful setup, poll for link. ++ **/ ++s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ /* Take the link out of reset */ ++ ctrl &= ~E1000_CTRL_LRST; ++ ++ e1000_config_collision_dist_generic(hw); ++ ++ ret_val = e1000_commit_fc_settings_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Since auto-negotiation is enabled, take the link out of reset (the ++ * link will be in reset, because we previously reset the chip). This ++ * will restart auto-negotiation. If auto-negotiation is successful ++ * then the link-up status bit will be set and the flow control enable ++ * bits (RFCE and TFCE) will be set according to their negotiated value. ++ */ ++ DEBUGOUT("Auto-negotiation enabled\n"); ++ ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ E1000_WRITE_FLUSH(hw); ++ msec_delay(1); ++ ++ /* ++ * For these adapters, the SW definable pin 1 is set when the optics ++ * detect a signal. If we have a signal, then poll for a "Link-Up" ++ * indication. ++ */ ++ if (hw->phy.media_type == e1000_media_type_internal_serdes || ++ (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { ++ ret_val = e1000_poll_fiber_serdes_link_generic(hw); ++ } else { ++ DEBUGOUT("No signal detected\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_config_collision_dist_generic - Configure collision distance ++ * @hw: pointer to the HW structure ++ * ++ * Configures the collision distance to the default value and is used ++ * during link setup. Currently no func pointer exists and all ++ * implementations are handled in the generic version of this function. ++ **/ ++void e1000_config_collision_dist_generic(struct e1000_hw *hw) ++{ ++ u32 tctl; ++ ++ DEBUGFUNC("e1000_config_collision_dist_generic"); ++ ++ tctl = E1000_READ_REG(hw, E1000_TCTL); ++ ++ tctl &= ~E1000_TCTL_COLD; ++ tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; ++ ++ E1000_WRITE_REG(hw, E1000_TCTL, tctl); ++ E1000_WRITE_FLUSH(hw); ++} ++ ++/** ++ * e1000_poll_fiber_serdes_link_generic - Poll for link up ++ * @hw: pointer to the HW structure ++ * ++ * Polls for link up by reading the status register, if link fails to come ++ * up with auto-negotiation, then the link is forced if a signal is detected. ++ **/ ++s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 i, status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); ++ ++ /* ++ * If we have a signal (the cable is plugged in, or assumed true for ++ * serdes media) then poll for a "Link-Up" indication in the Device ++ * Status Register. Time-out if a link isn't seen in 500 milliseconds ++ * seconds (Auto-negotiation should complete in less than 500 ++ * milliseconds even if the other end is doing it in SW). ++ */ ++ for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { ++ msec_delay(10); ++ status = E1000_READ_REG(hw, E1000_STATUS); ++ if (status & E1000_STATUS_LU) ++ break; ++ } ++ if (i == FIBER_LINK_UP_LIMIT) { ++ DEBUGOUT("Never got a valid link from auto-neg!!!\n"); ++ mac->autoneg_failed = 1; ++ /* ++ * AutoNeg failed to achieve a link, so we'll call ++ * mac->check_for_link. This routine will force the ++ * link up if we detect a signal. This will allow us to ++ * communicate with non-autonegotiating link partners. ++ */ ++ ret_val = hw->mac.ops.check_for_link(hw); ++ if (ret_val) { ++ DEBUGOUT("Error while checking for link\n"); ++ goto out; ++ } ++ mac->autoneg_failed = 0; ++ } else { ++ mac->autoneg_failed = 0; ++ DEBUGOUT("Valid Link Found\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_commit_fc_settings_generic - Configure flow control ++ * @hw: pointer to the HW structure ++ * ++ * Write the flow control settings to the Transmit Config Word Register (TXCW) ++ * base on the flow control settings in e1000_mac_info. ++ **/ ++s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 txcw; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_commit_fc_settings_generic"); ++ ++ /* ++ * Check for a software override of the flow control settings, and ++ * setup the device accordingly. If auto-negotiation is enabled, then ++ * software will have to set the "PAUSE" bits to the correct value in ++ * the Transmit Config Word Register (TXCW) and re-start auto- ++ * negotiation. However, if auto-negotiation is disabled, then ++ * software will have to manually configure the two flow control enable ++ * bits in the CTRL register. ++ * ++ * The possible values of the "fc" parameter are: ++ * 0: Flow control is completely disabled ++ * 1: Rx flow control is enabled (we can receive pause frames, ++ * but not send pause frames). ++ * 2: Tx flow control is enabled (we can send pause frames but we ++ * do not support receiving pause frames). ++ * 3: Both Rx and Tx flow control (symmetric) are enabled. ++ */ ++ switch (hw->fc.current_mode) { ++ case e1000_fc_none: ++ /* Flow control completely disabled by a software over-ride. */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); ++ break; ++ case e1000_fc_rx_pause: ++ /* ++ * Rx Flow control is enabled and Tx Flow control is disabled ++ * by a software over-ride. Since there really isn't a way to ++ * advertise that we are capable of Rx Pause ONLY, we will ++ * advertise that we support both symmetric and asymmetric RX ++ * PAUSE. Later, we will disable the adapter's ability to send ++ * PAUSE frames. ++ */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); ++ break; ++ case e1000_fc_tx_pause: ++ /* ++ * Tx Flow control is enabled, and Rx Flow control is disabled, ++ * by a software over-ride. ++ */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); ++ break; ++ case e1000_fc_full: ++ /* ++ * Flow control (both Rx and Tx) is enabled by a software ++ * over-ride. ++ */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); ++ break; ++ default: ++ DEBUGOUT("Flow control param set incorrectly\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ break; ++ } ++ ++ E1000_WRITE_REG(hw, E1000_TXCW, txcw); ++ mac->txcw = txcw; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks ++ * @hw: pointer to the HW structure ++ * ++ * Sets the flow control high/low threshold (watermark) registers. If ++ * flow control XON frame transmission is enabled, then set XON frame ++ * transmission as well. ++ **/ ++s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u32 fcrtl = 0, fcrth = 0; ++ ++ DEBUGFUNC("e1000_set_fc_watermarks_generic"); ++ ++ /* ++ * Set the flow control receive threshold registers. Normally, ++ * these registers will be set to a default threshold that may be ++ * adjusted later by the driver's runtime code. However, if the ++ * ability to transmit pause frames is not enabled, then these ++ * registers will be set to 0. ++ */ ++ if (hw->fc.current_mode & e1000_fc_tx_pause) { ++ /* ++ * We need to set up the Receive Threshold high and low water ++ * marks as well as (optionally) enabling the transmission of ++ * XON frames. ++ */ ++ fcrtl = hw->fc.low_water; ++ if (hw->fc.send_xon) ++ fcrtl |= E1000_FCRTL_XONE; ++ ++ fcrth = hw->fc.high_water; ++ } ++ E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); ++ E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_set_default_fc_generic - Set flow control default values ++ * @hw: pointer to the HW structure ++ * ++ * Read the EEPROM for the default values for flow control and store the ++ * values. ++ **/ ++s32 e1000_set_default_fc_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 nvm_data; ++ ++ DEBUGFUNC("e1000_set_default_fc_generic"); ++ ++ /* ++ * Read and store word 0x0F of the EEPROM. This word contains bits ++ * that determine the hardware's default PAUSE (flow control) mode, ++ * a bit that determines whether the HW defaults to enabling or ++ * disabling auto-negotiation, and the direction of the ++ * SW defined pins. If there is no SW over-ride of the flow ++ * control setting, then the variable hw->fc will ++ * be initialized based on a value in the EEPROM. ++ */ ++ ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); ++ ++ if (ret_val) { ++ DEBUGOUT("NVM Read Error\n"); ++ goto out; ++ } ++ ++ if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) ++ hw->fc.requested_mode = e1000_fc_none; ++ else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == ++ NVM_WORD0F_ASM_DIR) ++ hw->fc.requested_mode = e1000_fc_tx_pause; ++ else ++ hw->fc.requested_mode = e1000_fc_full; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_force_mac_fc_generic - Force the MAC's flow control settings ++ * @hw: pointer to the HW structure ++ * ++ * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the ++ * device control register to reflect the adapter settings. TFCE and RFCE ++ * need to be explicitly set by software when a copper PHY is used because ++ * autonegotiation is managed by the PHY rather than the MAC. Software must ++ * also configure these bits when link is forced on a fiber connection. ++ **/ ++s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_force_mac_fc_generic"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ /* ++ * Because we didn't get link via the internal auto-negotiation ++ * mechanism (we either forced link or we got link via PHY ++ * auto-neg), we have to manually enable/disable transmit an ++ * receive flow control. ++ * ++ * The "Case" statement below enables/disable flow control ++ * according to the "hw->fc.current_mode" parameter. ++ * ++ * The possible values of the "fc" parameter are: ++ * 0: Flow control is completely disabled ++ * 1: Rx flow control is enabled (we can receive pause ++ * frames but not send pause frames). ++ * 2: Tx flow control is enabled (we can send pause frames ++ * frames but we do not receive pause frames). ++ * 3: Both Rx and Tx flow control (symmetric) is enabled. ++ * other: No other values should be possible at this point. ++ */ ++ DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); ++ ++ switch (hw->fc.current_mode) { ++ case e1000_fc_none: ++ ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); ++ break; ++ case e1000_fc_rx_pause: ++ ctrl &= (~E1000_CTRL_TFCE); ++ ctrl |= E1000_CTRL_RFCE; ++ break; ++ case e1000_fc_tx_pause: ++ ctrl &= (~E1000_CTRL_RFCE); ++ ctrl |= E1000_CTRL_TFCE; ++ break; ++ case e1000_fc_full: ++ ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); ++ break; ++ default: ++ DEBUGOUT("Flow control param set incorrectly\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_config_fc_after_link_up_generic - Configures flow control after link ++ * @hw: pointer to the HW structure ++ * ++ * Checks the status of auto-negotiation after link up to ensure that the ++ * speed and duplex were not forced. If the link needed to be forced, then ++ * flow control needs to be forced also. If auto-negotiation is enabled ++ * and did not fail, then we configure flow control based on our link ++ * partner. ++ **/ ++s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; ++ u16 speed, duplex; ++ ++ DEBUGFUNC("e1000_config_fc_after_link_up_generic"); ++ ++ /* ++ * Check for the case where we have fiber media and auto-neg failed ++ * so we had to force link. In this case, we need to force the ++ * configuration of the MAC to match the "fc" parameter. ++ */ ++ if (mac->autoneg_failed) { ++ if (hw->phy.media_type == e1000_media_type_fiber || ++ hw->phy.media_type == e1000_media_type_internal_serdes) ++ ret_val = e1000_force_mac_fc_generic(hw); ++ } else { ++ if (hw->phy.media_type == e1000_media_type_copper) ++ ret_val = e1000_force_mac_fc_generic(hw); ++ } ++ ++ if (ret_val) { ++ DEBUGOUT("Error forcing flow control settings\n"); ++ goto out; ++ } ++ ++ /* ++ * Check for the case where we have copper media and auto-neg is ++ * enabled. In this case, we need to check and see if Auto-Neg ++ * has completed, and if so, how the PHY and link partner has ++ * flow control configured. ++ */ ++ if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { ++ /* ++ * Read the MII Status Register and check to see if AutoNeg ++ * has completed. We read this twice because this reg has ++ * some "sticky" (latched) bits. ++ */ ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); ++ if (ret_val) ++ goto out; ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); ++ if (ret_val) ++ goto out; ++ ++ if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { ++ DEBUGOUT("Copper PHY and Auto Neg " ++ "has not completed.\n"); ++ goto out; ++ } ++ ++ /* ++ * The AutoNeg process has completed, so we now need to ++ * read both the Auto Negotiation Advertisement ++ * Register (Address 4) and the Auto_Negotiation Base ++ * Page Ability Register (Address 5) to determine how ++ * flow control was negotiated. ++ */ ++ ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, ++ &mii_nway_adv_reg); ++ if (ret_val) ++ goto out; ++ ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, ++ &mii_nway_lp_ability_reg); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Two bits in the Auto Negotiation Advertisement Register ++ * (Address 4) and two bits in the Auto Negotiation Base ++ * Page Ability Register (Address 5) determine flow control ++ * for both the PHY and the link partner. The following ++ * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, ++ * 1999, describes these PAUSE resolution bits and how flow ++ * control is determined based upon these settings. ++ * NOTE: DC = Don't Care ++ * ++ * LOCAL DEVICE | LINK PARTNER ++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution ++ *-------|---------|-------|---------|-------------------- ++ * 0 | 0 | DC | DC | e1000_fc_none ++ * 0 | 1 | 0 | DC | e1000_fc_none ++ * 0 | 1 | 1 | 0 | e1000_fc_none ++ * 0 | 1 | 1 | 1 | e1000_fc_tx_pause ++ * 1 | 0 | 0 | DC | e1000_fc_none ++ * 1 | DC | 1 | DC | e1000_fc_full ++ * 1 | 1 | 0 | 0 | e1000_fc_none ++ * 1 | 1 | 0 | 1 | e1000_fc_rx_pause ++ * ++ * Are both PAUSE bits set to 1? If so, this implies ++ * Symmetric Flow Control is enabled at both ends. The ++ * ASM_DIR bits are irrelevant per the spec. ++ * ++ * For Symmetric Flow Control: ++ * ++ * LOCAL DEVICE | LINK PARTNER ++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ++ *-------|---------|-------|---------|-------------------- ++ * 1 | DC | 1 | DC | E1000_fc_full ++ * ++ */ ++ if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { ++ /* ++ * Now we need to check if the user selected Rx ONLY ++ * of pause frames. In this case, we had to advertise ++ * FULL flow control because we could not advertise RX ++ * ONLY. Hence, we must now check to see if we need to ++ * turn OFF the TRANSMISSION of PAUSE frames. ++ */ ++ if (hw->fc.requested_mode == e1000_fc_full) { ++ hw->fc.current_mode = e1000_fc_full; ++ DEBUGOUT("Flow Control = FULL.\r\n"); ++ } else { ++ hw->fc.current_mode = e1000_fc_rx_pause; ++ DEBUGOUT("Flow Control = " ++ "RX PAUSE frames only.\r\n"); ++ } ++ } ++ /* ++ * For receiving PAUSE frames ONLY. ++ * ++ * LOCAL DEVICE | LINK PARTNER ++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ++ *-------|---------|-------|---------|-------------------- ++ * 0 | 1 | 1 | 1 | e1000_fc_tx_pause ++ */ ++ else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && ++ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { ++ hw->fc.current_mode = e1000_fc_tx_pause; ++ DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); ++ } ++ /* ++ * For transmitting PAUSE frames ONLY. ++ * ++ * LOCAL DEVICE | LINK PARTNER ++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ++ *-------|---------|-------|---------|-------------------- ++ * 1 | 1 | 0 | 1 | e1000_fc_rx_pause ++ */ ++ else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && ++ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && ++ !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { ++ hw->fc.current_mode = e1000_fc_rx_pause; ++ DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); ++ } else { ++ /* ++ * Per the IEEE spec, at this point flow control ++ * should be disabled. ++ */ ++ hw->fc.current_mode = e1000_fc_none; ++ DEBUGOUT("Flow Control = NONE.\r\n"); ++ } ++ ++ /* ++ * Now we need to do one last check... If we auto- ++ * negotiated to HALF DUPLEX, flow control should not be ++ * enabled per IEEE 802.3 spec. ++ */ ++ ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); ++ if (ret_val) { ++ DEBUGOUT("Error getting link speed and duplex\n"); ++ goto out; ++ } ++ ++ if (duplex == HALF_DUPLEX) ++ hw->fc.current_mode = e1000_fc_none; ++ ++ /* ++ * Now we call a subroutine to actually force the MAC ++ * controller to use the correct flow control settings. ++ */ ++ ret_val = e1000_force_mac_fc_generic(hw); ++ if (ret_val) { ++ DEBUGOUT("Error forcing flow control settings\n"); ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex ++ * @hw: pointer to the HW structure ++ * @speed: stores the current speed ++ * @duplex: stores the current duplex ++ * ++ * Read the status register for the current speed/duplex and store the current ++ * speed and duplex for copper connections. ++ **/ ++s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex) ++{ ++ u32 status; ++ ++ DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); ++ ++ status = E1000_READ_REG(hw, E1000_STATUS); ++ if (status & E1000_STATUS_SPEED_1000) { ++ *speed = SPEED_1000; ++ DEBUGOUT("1000 Mbs, "); ++ } else if (status & E1000_STATUS_SPEED_100) { ++ *speed = SPEED_100; ++ DEBUGOUT("100 Mbs, "); ++ } else { ++ *speed = SPEED_10; ++ DEBUGOUT("10 Mbs, "); ++ } ++ ++ if (status & E1000_STATUS_FD) { ++ *duplex = FULL_DUPLEX; ++ DEBUGOUT("Full Duplex\n"); ++ } else { ++ *duplex = HALF_DUPLEX; ++ DEBUGOUT("Half Duplex\n"); ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex ++ * @hw: pointer to the HW structure ++ * @speed: stores the current speed ++ * @duplex: stores the current duplex ++ * ++ * Sets the speed and duplex to gigabit full duplex (the only possible option) ++ * for fiber/serdes links. ++ **/ ++s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, ++ u16 *speed, u16 *duplex) ++{ ++ DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); ++ ++ *speed = SPEED_1000; ++ *duplex = FULL_DUPLEX; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_get_hw_semaphore_generic - Acquire hardware semaphore ++ * @hw: pointer to the HW structure ++ * ++ * Acquire the HW semaphore to access the PHY or NVM ++ **/ ++s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) ++{ ++ u32 swsm; ++ s32 ret_val = E1000_SUCCESS; ++ s32 timeout = hw->nvm.word_size + 1; ++ s32 i = 0; ++ ++ DEBUGFUNC("e1000_get_hw_semaphore_generic"); ++ ++ /* Get the SW semaphore */ ++ while (i < timeout) { ++ swsm = E1000_READ_REG(hw, E1000_SWSM); ++ if (!(swsm & E1000_SWSM_SMBI)) ++ break; ++ ++ usec_delay(50); ++ i++; ++ } ++ ++ if (i == timeout) { ++ DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ /* Get the FW semaphore. */ ++ for (i = 0; i < timeout; i++) { ++ swsm = E1000_READ_REG(hw, E1000_SWSM); ++ E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); ++ ++ /* Semaphore acquired if bit latched */ ++ if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) ++ break; ++ ++ usec_delay(50); ++ } ++ ++ if (i == timeout) { ++ /* Release semaphores */ ++ e1000_put_hw_semaphore_generic(hw); ++ DEBUGOUT("Driver can't access the NVM\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_put_hw_semaphore_generic - Release hardware semaphore ++ * @hw: pointer to the HW structure ++ * ++ * Release hardware semaphore used to access the PHY or NVM ++ **/ ++void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) ++{ ++ u32 swsm; ++ ++ DEBUGFUNC("e1000_put_hw_semaphore_generic"); ++ ++ swsm = E1000_READ_REG(hw, E1000_SWSM); ++ ++ swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); ++ ++ E1000_WRITE_REG(hw, E1000_SWSM, swsm); ++} ++ ++/** ++ * e1000_get_auto_rd_done_generic - Check for auto read completion ++ * @hw: pointer to the HW structure ++ * ++ * Check EEPROM for Auto Read done bit. ++ **/ ++s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) ++{ ++ s32 i = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_get_auto_rd_done_generic"); ++ ++ while (i < AUTO_READ_DONE_TIMEOUT) { ++ if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) ++ break; ++ msec_delay(1); ++ i++; ++ } ++ ++ if (i == AUTO_READ_DONE_TIMEOUT) { ++ DEBUGOUT("Auto read by HW from NVM has not completed.\n"); ++ ret_val = -E1000_ERR_RESET; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_valid_led_default_generic - Verify a valid default LED config ++ * @hw: pointer to the HW structure ++ * @data: pointer to the NVM (EEPROM) ++ * ++ * Read the EEPROM for the current default LED configuration. If the ++ * LED configuration is not valid, set to a valid LED configuration. ++ **/ ++s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) ++{ ++ s32 ret_val; ++ ++ DEBUGFUNC("e1000_valid_led_default_generic"); ++ ++ ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); ++ if (ret_val) { ++ DEBUGOUT("NVM Read Error\n"); ++ goto out; ++ } ++ ++ if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) ++ *data = ID_LED_DEFAULT; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_id_led_init_generic - ++ * @hw: pointer to the HW structure ++ * ++ **/ ++s32 e1000_id_led_init_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val; ++ const u32 ledctl_mask = 0x000000FF; ++ const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; ++ const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; ++ u16 data, i, temp; ++ const u16 led_mask = 0x0F; ++ ++ DEBUGFUNC("e1000_id_led_init_generic"); ++ ++ ret_val = hw->nvm.ops.valid_led_default(hw, &data); ++ if (ret_val) ++ goto out; ++ ++ mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); ++ mac->ledctl_mode1 = mac->ledctl_default; ++ mac->ledctl_mode2 = mac->ledctl_default; ++ ++ for (i = 0; i < 4; i++) { ++ temp = (data >> (i << 2)) & led_mask; ++ switch (temp) { ++ case ID_LED_ON1_DEF2: ++ case ID_LED_ON1_ON2: ++ case ID_LED_ON1_OFF2: ++ mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); ++ mac->ledctl_mode1 |= ledctl_on << (i << 3); ++ break; ++ case ID_LED_OFF1_DEF2: ++ case ID_LED_OFF1_ON2: ++ case ID_LED_OFF1_OFF2: ++ mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); ++ mac->ledctl_mode1 |= ledctl_off << (i << 3); ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++ switch (temp) { ++ case ID_LED_DEF1_ON2: ++ case ID_LED_ON1_ON2: ++ case ID_LED_OFF1_ON2: ++ mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); ++ mac->ledctl_mode2 |= ledctl_on << (i << 3); ++ break; ++ case ID_LED_DEF1_OFF2: ++ case ID_LED_ON1_OFF2: ++ case ID_LED_OFF1_OFF2: ++ mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); ++ mac->ledctl_mode2 |= ledctl_off << (i << 3); ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_led_generic - Configures SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * This prepares the SW controllable LED for use and saves the current state ++ * of the LED so it can be later restored. ++ **/ ++s32 e1000_setup_led_generic(struct e1000_hw *hw) ++{ ++ u32 ledctl; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_setup_led_generic"); ++ ++ if (hw->mac.ops.setup_led != e1000_setup_led_generic) { ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ if (hw->phy.media_type == e1000_media_type_fiber) { ++ ledctl = E1000_READ_REG(hw, E1000_LEDCTL); ++ hw->mac.ledctl_default = ledctl; ++ /* Turn off LED0 */ ++ ledctl &= ~(E1000_LEDCTL_LED0_IVRT | ++ E1000_LEDCTL_LED0_BLINK | ++ E1000_LEDCTL_LED0_MODE_MASK); ++ ledctl |= (E1000_LEDCTL_MODE_LED_OFF << ++ E1000_LEDCTL_LED0_MODE_SHIFT); ++ E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); ++ } else if (hw->phy.media_type == e1000_media_type_copper) { ++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_cleanup_led_generic - Set LED config to default operation ++ * @hw: pointer to the HW structure ++ * ++ * Remove the current LED configuration and set the LED configuration ++ * to the default value, saved from the EEPROM. ++ **/ ++s32 e1000_cleanup_led_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_cleanup_led_generic"); ++ ++ if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) { ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_blink_led_generic - Blink LED ++ * @hw: pointer to the HW structure ++ * ++ * Blink the LEDs which are set to be on. ++ **/ ++s32 e1000_blink_led_generic(struct e1000_hw *hw) ++{ ++ u32 ledctl_blink = 0; ++ u32 i; ++ ++ DEBUGFUNC("e1000_blink_led_generic"); ++ ++ if (hw->phy.media_type == e1000_media_type_fiber) { ++ /* always blink LED0 for PCI-E fiber */ ++ ledctl_blink = E1000_LEDCTL_LED0_BLINK | ++ (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); ++ } else { ++ /* ++ * set the blink bit for each LED that's "on" (0x0E) ++ * in ledctl_mode2 ++ */ ++ ledctl_blink = hw->mac.ledctl_mode2; ++ for (i = 0; i < 4; i++) ++ if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == ++ E1000_LEDCTL_MODE_LED_ON) ++ ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << ++ (i * 8)); ++ } ++ ++ E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_led_on_generic - Turn LED on ++ * @hw: pointer to the HW structure ++ * ++ * Turn LED on. ++ **/ ++s32 e1000_led_on_generic(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ ++ DEBUGFUNC("e1000_led_on_generic"); ++ ++ switch (hw->phy.media_type) { ++ case e1000_media_type_fiber: ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl &= ~E1000_CTRL_SWDPIN0; ++ ctrl |= E1000_CTRL_SWDPIO0; ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ break; ++ case e1000_media_type_copper: ++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); ++ break; ++ default: ++ break; ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_led_off_generic - Turn LED off ++ * @hw: pointer to the HW structure ++ * ++ * Turn LED off. ++ **/ ++s32 e1000_led_off_generic(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ ++ DEBUGFUNC("e1000_led_off_generic"); ++ ++ switch (hw->phy.media_type) { ++ case e1000_media_type_fiber: ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl |= E1000_CTRL_SWDPIN0; ++ ctrl |= E1000_CTRL_SWDPIO0; ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ break; ++ case e1000_media_type_copper: ++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); ++ break; ++ default: ++ break; ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities ++ * @hw: pointer to the HW structure ++ * @no_snoop: bitmap of snoop events ++ * ++ * Set the PCI-express register to snoop for events enabled in 'no_snoop'. ++ **/ ++void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) ++{ ++ u32 gcr; ++ ++ DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); ++ ++ if (hw->bus.type != e1000_bus_type_pci_express) ++ goto out; ++ ++ if (no_snoop) { ++ gcr = E1000_READ_REG(hw, E1000_GCR); ++ gcr &= ~(PCIE_NO_SNOOP_ALL); ++ gcr |= no_snoop; ++ E1000_WRITE_REG(hw, E1000_GCR, gcr); ++ } ++out: ++ return; ++} ++ ++/** ++ * e1000_disable_pcie_master_generic - Disables PCI-express master access ++ * @hw: pointer to the HW structure ++ * ++ * Returns 0 (E1000_SUCCESS) if successful, else returns -10 ++ * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused ++ * the master requests to be disabled. ++ * ++ * Disables PCI-Express master access and verifies there are no pending ++ * requests. ++ **/ ++s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 timeout = MASTER_DISABLE_TIMEOUT; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_disable_pcie_master_generic"); ++ ++ if (hw->bus.type != e1000_bus_type_pci_express) ++ goto out; ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++ while (timeout) { ++ if (!(E1000_READ_REG(hw, E1000_STATUS) & ++ E1000_STATUS_GIO_MASTER_ENABLE)) ++ break; ++ usec_delay(100); ++ timeout--; ++ } ++ ++ if (!timeout) { ++ DEBUGOUT("Master requests are pending.\n"); ++ ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing ++ * @hw: pointer to the HW structure ++ * ++ * Reset the Adaptive Interframe Spacing throttle to default values. ++ **/ ++void e1000_reset_adaptive_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ ++ DEBUGFUNC("e1000_reset_adaptive_generic"); ++ ++ if (!mac->adaptive_ifs) { ++ DEBUGOUT("Not in Adaptive IFS mode!\n"); ++ goto out; ++ } ++ ++ mac->current_ifs_val = 0; ++ mac->ifs_min_val = IFS_MIN; ++ mac->ifs_max_val = IFS_MAX; ++ mac->ifs_step_size = IFS_STEP; ++ mac->ifs_ratio = IFS_RATIO; ++ ++ mac->in_ifs_mode = false; ++ E1000_WRITE_REG(hw, E1000_AIT, 0); ++out: ++ return; ++} ++ ++/** ++ * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing ++ * @hw: pointer to the HW structure ++ * ++ * Update the Adaptive Interframe Spacing Throttle value based on the ++ * time between transmitted packets and time between collisions. ++ **/ ++void e1000_update_adaptive_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ ++ DEBUGFUNC("e1000_update_adaptive_generic"); ++ ++ if (!mac->adaptive_ifs) { ++ DEBUGOUT("Not in Adaptive IFS mode!\n"); ++ goto out; ++ } ++ ++ if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { ++ if (mac->tx_packet_delta > MIN_NUM_XMITS) { ++ mac->in_ifs_mode = true; ++ if (mac->current_ifs_val < mac->ifs_max_val) { ++ if (!mac->current_ifs_val) ++ mac->current_ifs_val = mac->ifs_min_val; ++ else ++ mac->current_ifs_val += ++ mac->ifs_step_size; ++ E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); ++ } ++ } ++ } else { ++ if (mac->in_ifs_mode && ++ (mac->tx_packet_delta <= MIN_NUM_XMITS)) { ++ mac->current_ifs_val = 0; ++ mac->in_ifs_mode = false; ++ E1000_WRITE_REG(hw, E1000_AIT, 0); ++ } ++ } ++out: ++ return; ++} ++ ++/** ++ * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings ++ * @hw: pointer to the HW structure ++ * ++ * Verify that when not using auto-negotiation that MDI/MDIx is correctly ++ * set, which is forced to MDI mode only. ++ **/ ++static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_validate_mdi_setting_generic"); ++ ++ if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { ++ DEBUGOUT("Invalid MDI setting detected\n"); ++ hw->phy.mdix = 1; ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} +diff -r b58885ce604a drivers/net/e1000/e1000_mac.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_mac.h Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,92 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_MAC_H_ ++#define _E1000_MAC_H_ ++ ++/* ++ * Functions that should not be called directly from drivers but can be used ++ * by other files in this 'shared code' ++ */ ++void e1000_init_mac_ops_generic(struct e1000_hw *hw); ++void e1000_null_mac_generic(struct e1000_hw *hw); ++s32 e1000_null_ops_generic(struct e1000_hw *hw); ++s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d); ++bool e1000_null_mng_mode(struct e1000_hw *hw); ++void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a); ++void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b); ++void e1000_null_mta_set(struct e1000_hw *hw, u32 a); ++void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a); ++s32 e1000_blink_led_generic(struct e1000_hw *hw); ++s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw); ++s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw); ++s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw); ++s32 e1000_cleanup_led_generic(struct e1000_hw *hw); ++s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw); ++s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw); ++s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw); ++s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw); ++s32 e1000_force_mac_fc_generic(struct e1000_hw *hw); ++s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw); ++s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw); ++s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw); ++void e1000_set_lan_id_single_port(struct e1000_hw *hw); ++void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw); ++s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw); ++s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex); ++s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, ++ u16 *speed, u16 *duplex); ++s32 e1000_id_led_init_generic(struct e1000_hw *hw); ++s32 e1000_led_on_generic(struct e1000_hw *hw); ++s32 e1000_led_off_generic(struct e1000_hw *hw); ++void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, ++ u8 *mc_addr_list, u32 mc_addr_count); ++s32 e1000_set_default_fc_generic(struct e1000_hw *hw); ++s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw); ++s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw); ++s32 e1000_setup_led_generic(struct e1000_hw *hw); ++s32 e1000_setup_link_generic(struct e1000_hw *hw); ++ ++u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr); ++ ++void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw); ++void e1000_clear_vfta_generic(struct e1000_hw *hw); ++void e1000_config_collision_dist_generic(struct e1000_hw *hw); ++void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count); ++void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value); ++void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw); ++void e1000_put_hw_semaphore_generic(struct e1000_hw *hw); ++void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); ++s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw); ++void e1000_reset_adaptive_generic(struct e1000_hw *hw); ++void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop); ++void e1000_update_adaptive_generic(struct e1000_hw *hw); ++void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value); ++ ++#endif +diff -r b58885ce604a drivers/net/e1000/e1000_main.c +--- a/drivers/net/e1000/e1000_main.c Wed Aug 05 09:27:10 2009 +0100 ++++ b/drivers/net/e1000/e1000_main.c Wed Aug 05 11:02:21 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel PRO/1000 Linux driver +- Copyright(c) 1999 - 2006 Intel Corporation. ++ Copyright(c) 1999 - 2008 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -26,14 +26,48 @@ + + *******************************************************************************/ + ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef NETIF_F_TSO ++#include ++#ifdef NETIF_F_TSO6 ++#include ++#endif ++#endif ++#ifdef SIOCGMIIPHY ++#include ++#endif ++#ifdef SIOCETHTOOL ++#include ++#endif ++#ifdef NETIF_F_HW_VLAN_TX ++#include ++#endif ++ + #include "e1000.h" +-#include + + char e1000_driver_name[] = "e1000"; + static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver"; +-#define DRV_VERSION "7.3.21-k3-NAPI" ++ ++#ifdef CONFIG_E1000_NAPI ++#define DRV_NAPI "-NAPI" ++#else ++#define DRV_NAPI ++#endif ++ ++#define DRV_DEBUG ++ ++#define DRV_HW_PERF ++ ++#define DRV_VERSION "8.0.16" DRV_NAPI DRV_DEBUG DRV_HW_PERF + const char e1000_driver_version[] = DRV_VERSION; +-static const char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; ++static const char e1000_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; + + /* e1000_pci_tbl - PCI Device ID Table + * +@@ -43,75 +77,66 @@ + * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)} + */ + static struct pci_device_id e1000_pci_tbl[] = { +- INTEL_E1000_ETHERNET_DEVICE(0x1000), +- INTEL_E1000_ETHERNET_DEVICE(0x1001), +- INTEL_E1000_ETHERNET_DEVICE(0x1004), +- INTEL_E1000_ETHERNET_DEVICE(0x1008), +- INTEL_E1000_ETHERNET_DEVICE(0x1009), +- INTEL_E1000_ETHERNET_DEVICE(0x100C), +- INTEL_E1000_ETHERNET_DEVICE(0x100D), +- INTEL_E1000_ETHERNET_DEVICE(0x100E), +- INTEL_E1000_ETHERNET_DEVICE(0x100F), +- INTEL_E1000_ETHERNET_DEVICE(0x1010), +- INTEL_E1000_ETHERNET_DEVICE(0x1011), +- INTEL_E1000_ETHERNET_DEVICE(0x1012), +- INTEL_E1000_ETHERNET_DEVICE(0x1013), +- INTEL_E1000_ETHERNET_DEVICE(0x1014), +- INTEL_E1000_ETHERNET_DEVICE(0x1015), +- INTEL_E1000_ETHERNET_DEVICE(0x1016), +- INTEL_E1000_ETHERNET_DEVICE(0x1017), +- INTEL_E1000_ETHERNET_DEVICE(0x1018), +- INTEL_E1000_ETHERNET_DEVICE(0x1019), +- INTEL_E1000_ETHERNET_DEVICE(0x101A), +- INTEL_E1000_ETHERNET_DEVICE(0x101D), +- INTEL_E1000_ETHERNET_DEVICE(0x101E), +- INTEL_E1000_ETHERNET_DEVICE(0x1026), +- INTEL_E1000_ETHERNET_DEVICE(0x1027), +- INTEL_E1000_ETHERNET_DEVICE(0x1028), +- INTEL_E1000_ETHERNET_DEVICE(0x1075), +- INTEL_E1000_ETHERNET_DEVICE(0x1076), +- INTEL_E1000_ETHERNET_DEVICE(0x1077), +- INTEL_E1000_ETHERNET_DEVICE(0x1078), +- INTEL_E1000_ETHERNET_DEVICE(0x1079), +- INTEL_E1000_ETHERNET_DEVICE(0x107A), +- INTEL_E1000_ETHERNET_DEVICE(0x107B), +- INTEL_E1000_ETHERNET_DEVICE(0x107C), +- INTEL_E1000_ETHERNET_DEVICE(0x108A), +- INTEL_E1000_ETHERNET_DEVICE(0x1099), +- INTEL_E1000_ETHERNET_DEVICE(0x10B5), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82542), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82543GC_FIBER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82543GC_COPPER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82544EI_COPPER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82544EI_FIBER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82544GC_COPPER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82544GC_LOM), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82540EM), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82545EM_COPPER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82546EB_COPPER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82545EM_FIBER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82546EB_FIBER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82541EI), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82541ER_LOM), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82540EM_LOM), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82540EP_LOM), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82540EP), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82541EI_MOBILE), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82547EI), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82547EI_MOBILE), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82546EB_QUAD_COPPER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82540EP_LP), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82545GM_COPPER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82545GM_FIBER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82545GM_SERDES), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82547GI), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82541GI), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82541GI_MOBILE), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82541ER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82546GB_COPPER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82546GB_FIBER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82546GB_SERDES), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82541GI_LF), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82546GB_PCIE), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82546GB_QUAD_COPPER), ++ INTEL_E1000_ETHERNET_DEVICE(E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3), + /* required last entry */ + {0,} + }; + + MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); + +-int e1000_up(struct e1000_adapter *adapter); +-void e1000_down(struct e1000_adapter *adapter); +-void e1000_reinit_locked(struct e1000_adapter *adapter); +-void e1000_reset(struct e1000_adapter *adapter); +-int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx); +-int e1000_setup_all_tx_resources(struct e1000_adapter *adapter); +-int e1000_setup_all_rx_resources(struct e1000_adapter *adapter); +-void e1000_free_all_tx_resources(struct e1000_adapter *adapter); +-void e1000_free_all_rx_resources(struct e1000_adapter *adapter); + static int e1000_setup_tx_resources(struct e1000_adapter *adapter, +- struct e1000_tx_ring *txdr); ++ struct e1000_tx_ring *tx_ring); + static int e1000_setup_rx_resources(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rxdr); ++ struct e1000_rx_ring *rx_ring); + static void e1000_free_tx_resources(struct e1000_adapter *adapter, +- struct e1000_tx_ring *tx_ring); ++ struct e1000_tx_ring *tx_ring); + static void e1000_free_rx_resources(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rx_ring); +-void e1000_update_stats(struct e1000_adapter *adapter); ++ struct e1000_rx_ring *rx_ring); + + static int e1000_init_module(void); + static void e1000_exit_module(void); + static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent); + static void __devexit e1000_remove(struct pci_dev *pdev); +-static int e1000_alloc_queues(struct e1000_adapter *adapter); ++static int e1000_alloc_rings(struct e1000_adapter *adapter); + static int e1000_sw_init(struct e1000_adapter *adapter); + static int e1000_open(struct net_device *netdev); + static int e1000_close(struct net_device *netdev); ++static void e1000_configure(struct e1000_adapter *adapter); + static void e1000_configure_tx(struct e1000_adapter *adapter); + static void e1000_configure_rx(struct e1000_adapter *adapter); + static void e1000_setup_rctl(struct e1000_adapter *adapter); +@@ -121,34 +146,42 @@ + struct e1000_tx_ring *tx_ring); + static void e1000_clean_rx_ring(struct e1000_adapter *adapter, + struct e1000_rx_ring *rx_ring); +-static void e1000_set_rx_mode(struct net_device *netdev); ++static void e1000_set_multi(struct net_device *netdev); + static void e1000_update_phy_info(unsigned long data); + static void e1000_watchdog(unsigned long data); ++static void e1000_watchdog_task(struct work_struct *work); + static void e1000_82547_tx_fifo_stall(unsigned long data); + static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev); ++static void e1000_phy_read_status(struct e1000_adapter *adapter); + static struct net_device_stats * e1000_get_stats(struct net_device *netdev); + static int e1000_change_mtu(struct net_device *netdev, int new_mtu); + static int e1000_set_mac(struct net_device *netdev, void *p); + static irqreturn_t e1000_intr(int irq, void *data); +-static irqreturn_t e1000_intr_msi(int irq, void *data); + static bool e1000_clean_tx_irq(struct e1000_adapter *adapter, +- struct e1000_tx_ring *tx_ring); +-static int e1000_clean(struct napi_struct *napi, int budget); ++ struct e1000_tx_ring *tx_ring); ++#ifdef CONFIG_E1000_NAPI ++static int e1000_poll(struct napi_struct *napi, int budget); + static bool e1000_clean_rx_irq(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rx_ring, +- int *work_done, int work_to_do); +-static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rx_ring, +- int *work_done, int work_to_do); ++ struct e1000_rx_ring *rx_ring, ++ int *work_done, int work_to_do); ++static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter, ++ struct e1000_rx_ring *rx_ring, ++ int *work_done, int work_to_do); ++static void e1000_alloc_jumbo_rx_buffers(struct e1000_adapter *adapter, ++ struct e1000_rx_ring *rx_ring, ++ int cleaned_count); ++#else ++static bool e1000_clean_rx_irq(struct e1000_adapter *adapter, ++ struct e1000_rx_ring *rx_ring); ++#endif + static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter, + struct e1000_rx_ring *rx_ring, +- int cleaned_count); +-static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rx_ring, +- int cleaned_count); ++ int cleaned_count); + static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); ++#ifdef SIOCGMIIPHY + static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, +- int cmd); ++ int cmd); ++#endif + static void e1000_enter_82542_rst(struct e1000_adapter *adapter); + static void e1000_leave_82542_rst(struct e1000_adapter *adapter); + static void e1000_tx_timeout(struct net_device *dev); +@@ -157,16 +190,29 @@ + static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter, + struct sk_buff *skb); + +-static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp); ++#ifdef NETIF_F_HW_VLAN_TX ++static void e1000_vlan_rx_register(struct net_device *netdev, ++ struct vlan_group *grp); + static void e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid); + static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid); + static void e1000_restore_vlan(struct e1000_adapter *adapter); ++#endif + + static int e1000_suspend(struct pci_dev *pdev, pm_message_t state); + #ifdef CONFIG_PM + static int e1000_resume(struct pci_dev *pdev); + #endif ++#ifndef USE_REBOOT_NOTIFIER + static void e1000_shutdown(struct pci_dev *pdev); ++#else ++static int e1000_notify_reboot(struct notifier_block *, unsigned long event, ++ void *ptr); ++static struct notifier_block e1000_notifier_reboot = { ++ .notifier_call = e1000_notify_reboot, ++ .next = NULL, ++ .priority = 0 ++}; ++#endif + + #ifdef CONFIG_NET_POLL_CONTROLLER + /* for netdump / net console */ +@@ -179,6 +225,11 @@ + MODULE_PARM_DESC(copybreak, + "Maximum size of packet that is copied to a new buffer on receive"); + ++static int ignore_64bit_dma = 0; ++module_param(ignore_64bit_dma, int, 0644); ++MODULE_PARM_DESC(ignore_64bit_dma, "Ignore 64-bit DMA (DAC) capability"); ++ ++#ifdef HAVE_PCI_ERS + static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, + pci_channel_state_t state); + static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev); +@@ -189,6 +240,7 @@ + .slot_reset = e1000_io_slot_reset, + .resume = e1000_io_resume, + }; ++#endif + + static struct pci_driver e1000_driver = { + .name = e1000_driver_name, +@@ -196,12 +248,16 @@ + .probe = e1000_probe, + .remove = __devexit_p(e1000_remove), + #ifdef CONFIG_PM +- /* Power Managment Hooks */ ++ /* Power Management Hooks */ + .suspend = e1000_suspend, + .resume = e1000_resume, + #endif ++#ifndef USE_REBOOT_NOTIFIER + .shutdown = e1000_shutdown, ++#endif ++#ifdef HAVE_PCI_ERS + .err_handler = &e1000_err_handler ++#endif + }; + + MODULE_AUTHOR("Intel Corporation, "); +@@ -219,7 +275,6 @@ + * e1000_init_module is the first routine called when the driver is + * loaded. All it does is register with the PCI subsystem. + **/ +- + static int __init e1000_init_module(void) + { + int ret; +@@ -229,6 +284,11 @@ + printk(KERN_INFO "%s\n", e1000_copyright); + + ret = pci_register_driver(&e1000_driver); ++#ifdef USE_REBOOT_NOTIFIER ++ if (ret >= 0) { ++ register_reboot_notifier(&e1000_notifier_reboot); ++ } ++#endif + if (copybreak != COPYBREAK_DEFAULT) { + if (copybreak == 0) + printk(KERN_INFO "e1000: copybreak disabled\n"); +@@ -247,9 +307,11 @@ + * e1000_exit_module is called just before the driver is removed + * from memory. + **/ +- + static void __exit e1000_exit_module(void) + { ++#ifdef USE_REBOOT_NOTIFIER ++ unregister_reboot_notifier(&e1000_notifier_reboot); ++#endif + pci_unregister_driver(&e1000_driver); + } + +@@ -257,28 +319,16 @@ + + static int e1000_request_irq(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- struct net_device *netdev = adapter->netdev; +- irq_handler_t handler = e1000_intr; +- int irq_flags = IRQF_SHARED; +- int err; +- +- if (hw->mac_type >= e1000_82571) { +- adapter->have_msi = !pci_enable_msi(adapter->pdev); +- if (adapter->have_msi) { +- handler = e1000_intr_msi; +- irq_flags = 0; +- } +- } +- +- err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name, +- netdev); +- if (err) { +- if (adapter->have_msi) +- pci_disable_msi(adapter->pdev); +- DPRINTK(PROBE, ERR, +- "Unable to allocate interrupt Error: %d\n", err); +- } ++ struct net_device *netdev = adapter->netdev; ++ int irq_flags, err = 0; ++ ++ irq_flags = IRQF_SHARED; ++ ++ err = request_irq(adapter->pdev->irq, &e1000_intr, irq_flags, ++ netdev->name, netdev); ++ if (err) ++ DPRINTK(PROBE, ERR, "Unable to allocate interrupt Error: %d\n", ++ err); + + return err; + } +@@ -288,22 +338,16 @@ + struct net_device *netdev = adapter->netdev; + + free_irq(adapter->pdev->irq, netdev); +- +- if (adapter->have_msi) +- pci_disable_msi(adapter->pdev); + } + + /** + * e1000_irq_disable - Mask off interrupt generation on the NIC + * @adapter: board private structure + **/ +- + static void e1000_irq_disable(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- +- ew32(IMC, ~0); +- E1000_WRITE_FLUSH(); ++ E1000_WRITE_REG(&adapter->hw, E1000_IMC, ~0); ++ E1000_WRITE_FLUSH(&adapter->hw); + synchronize_irq(adapter->pdev->irq); + } + +@@ -314,166 +358,82 @@ + + static void e1000_irq_enable(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- +- ew32(IMS, IMS_ENABLE_MASK); +- E1000_WRITE_FLUSH(); +-} ++ E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK); ++ E1000_WRITE_FLUSH(&adapter->hw); ++} ++#ifdef NETIF_F_HW_VLAN_TX + + static void e1000_update_mng_vlan(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- struct net_device *netdev = adapter->netdev; +- u16 vid = hw->mng_cookie.vlan_id; ++ struct net_device *netdev = adapter->netdev; ++ u16 vid = adapter->hw.mng_cookie.vlan_id; + u16 old_vid = adapter->mng_vlan_id; + if (adapter->vlgrp) { + if (!vlan_group_get_device(adapter->vlgrp, vid)) { +- if (hw->mng_cookie.status & +- E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) { ++ if (adapter->hw.mng_cookie.status & ++ E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { + e1000_vlan_rx_add_vid(netdev, vid); + adapter->mng_vlan_id = vid; +- } else ++ } else { + adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; ++ } + + if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && + (vid != old_vid) && + !vlan_group_get_device(adapter->vlgrp, old_vid)) + e1000_vlan_rx_kill_vid(netdev, old_vid); +- } else ++ } else { + adapter->mng_vlan_id = vid; +- } +-} +- +-/** +- * e1000_release_hw_control - release control of the h/w to f/w +- * @adapter: address of board private structure +- * +- * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. +- * For ASF and Pass Through versions of f/w this means that the +- * driver is no longer loaded. For AMT version (only with 82573) i +- * of the f/w this means that the network i/f is closed. +- * +- **/ +- +-static void e1000_release_hw_control(struct e1000_adapter *adapter) +-{ +- u32 ctrl_ext; +- u32 swsm; +- struct e1000_hw *hw = &adapter->hw; +- +- /* Let firmware taken over control of h/w */ +- switch (hw->mac_type) { +- case e1000_82573: +- swsm = er32(SWSM); +- ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); +- break; +- case e1000_82571: +- case e1000_82572: +- case e1000_80003es2lan: +- case e1000_ich8lan: +- ctrl_ext = er32(CTRL_EXT); +- ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); +- break; +- default: +- break; +- } +-} +- +-/** +- * e1000_get_hw_control - get control of the h/w from f/w +- * @adapter: address of board private structure +- * +- * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit. +- * For ASF and Pass Through versions of f/w this means that +- * the driver is loaded. For AMT version (only with 82573) +- * of the f/w this means that the network i/f is open. +- * +- **/ +- +-static void e1000_get_hw_control(struct e1000_adapter *adapter) +-{ +- u32 ctrl_ext; +- u32 swsm; +- struct e1000_hw *hw = &adapter->hw; +- +- /* Let firmware know the driver has taken over */ +- switch (hw->mac_type) { +- case e1000_82573: +- swsm = er32(SWSM); +- ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); +- break; +- case e1000_82571: +- case e1000_82572: +- case e1000_80003es2lan: +- case e1000_ich8lan: +- ctrl_ext = er32(CTRL_EXT); +- ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); +- break; +- default: +- break; +- } +-} ++ } ++ } ++} ++#endif + + static void e1000_init_manageability(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- + if (adapter->en_mng_pt) { +- u32 manc = er32(MANC); ++ u32 manc = E1000_READ_REG(&adapter->hw, E1000_MANC); + + /* disable hardware interception of ARP */ + manc &= ~(E1000_MANC_ARP_EN); + +- /* enable receiving management packets to the host */ +- /* this will probably generate destination unreachable messages +- * from the host OS, but the packets will be handled on SMBUS */ +- if (hw->has_manc2h) { +- u32 manc2h = er32(MANC2H); +- +- manc |= E1000_MANC_EN_MNG2HOST; +-#define E1000_MNG2HOST_PORT_623 (1 << 5) +-#define E1000_MNG2HOST_PORT_664 (1 << 6) +- manc2h |= E1000_MNG2HOST_PORT_623; +- manc2h |= E1000_MNG2HOST_PORT_664; +- ew32(MANC2H, manc2h); +- } +- +- ew32(MANC, manc); ++ E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); + } + } + + static void e1000_release_manageability(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- + if (adapter->en_mng_pt) { +- u32 manc = er32(MANC); ++ u32 manc = E1000_READ_REG(&adapter->hw, E1000_MANC); + + /* re-enable hardware interception of ARP */ + manc |= E1000_MANC_ARP_EN; + +- if (hw->has_manc2h) +- manc &= ~E1000_MANC_EN_MNG2HOST; +- +- /* don't explicitly have to mess with MANC2H since +- * MANC has an enable disable that gates MANC2H */ +- +- ew32(MANC, manc); ++ /* This is asymmetric with init_manageability, as we want to ++ * ensure that MNG2HOST filters are still enabled after this ++ * driver is unloaded as other host drivers such as PXE also ++ * may require these filters. */ ++ ++ /* XXX stop the hardware watchdog ? */ ++ ++ E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); + } + } + + /** + * e1000_configure - configure the hardware for RX and TX +- * @adapter = private board structure ++ * @adapter: private board structure + **/ + static void e1000_configure(struct e1000_adapter *adapter) + { + struct net_device *netdev = adapter->netdev; +- int i; +- +- e1000_set_rx_mode(netdev); +- ++ struct e1000_rx_ring *ring = adapter->rx_ring; ++ ++ e1000_set_multi(netdev); ++ ++#ifdef NETIF_F_HW_VLAN_TX + e1000_restore_vlan(adapter); ++#endif + e1000_init_manageability(adapter); + + e1000_configure_tx(adapter); +@@ -482,115 +442,57 @@ + /* call E1000_DESC_UNUSED which always leaves + * at least 1 descriptor unused to make sure + * next_to_use != next_to_clean */ +- for (i = 0; i < adapter->num_rx_queues; i++) { +- struct e1000_rx_ring *ring = &adapter->rx_ring[i]; +- adapter->alloc_rx_buf(adapter, ring, +- E1000_DESC_UNUSED(ring)); +- } ++ adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring)); + + adapter->tx_queue_len = netdev->tx_queue_len; + } + + int e1000_up(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- + /* hardware has been reset, we need to reload some things */ + e1000_configure(adapter); + +- clear_bit(__E1000_DOWN, &adapter->flags); +- +- napi_enable(&adapter->napi); +- ++ clear_bit(__E1000_DOWN, &adapter->state); ++ ++#ifdef CONFIG_E1000_NAPI ++ napi_enable(&adapter->rx_ring->napi); ++ ++#endif + e1000_irq_enable(adapter); + + /* fire a link change interrupt to start the watchdog */ +- ew32(ICS, E1000_ICS_LSC); +- return 0; +-} +- +-/** +- * e1000_power_up_phy - restore link in case the phy was powered down +- * @adapter: address of board private structure +- * +- * The phy may be powered down to save power and turn off link when the +- * driver is unloaded and wake on lan is not enabled (among others) +- * *** this routine MUST be followed by a call to e1000_reset *** +- * +- **/ +- +-void e1000_power_up_phy(struct e1000_adapter *adapter) +-{ +- struct e1000_hw *hw = &adapter->hw; +- u16 mii_reg = 0; +- +- /* Just clear the power down bit to wake the phy back up */ +- if (hw->media_type == e1000_media_type_copper) { +- /* according to the manual, the phy will retain its +- * settings across a power-down/up cycle */ +- e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg); +- mii_reg &= ~MII_CR_POWER_DOWN; +- e1000_write_phy_reg(hw, PHY_CTRL, mii_reg); +- } +-} +- +-static void e1000_power_down_phy(struct e1000_adapter *adapter) +-{ +- struct e1000_hw *hw = &adapter->hw; +- +- /* Power down the PHY so no link is implied when interface is down * +- * The PHY cannot be powered down if any of the following is true * +- * (a) WoL is enabled +- * (b) AMT is active +- * (c) SoL/IDER session is active */ +- if (!adapter->wol && hw->mac_type >= e1000_82540 && +- hw->media_type == e1000_media_type_copper) { +- u16 mii_reg = 0; +- +- switch (hw->mac_type) { +- case e1000_82540: +- case e1000_82545: +- case e1000_82545_rev_3: +- case e1000_82546: +- case e1000_82546_rev_3: +- case e1000_82541: +- case e1000_82541_rev_2: +- case e1000_82547: +- case e1000_82547_rev_2: +- if (er32(MANC) & E1000_MANC_SMBUS_EN) +- goto out; +- break; +- case e1000_82571: +- case e1000_82572: +- case e1000_82573: +- case e1000_80003es2lan: +- case e1000_ich8lan: +- if (e1000_check_mng_mode(hw) || +- e1000_check_phy_reset_block(hw)) +- goto out; +- break; +- default: +- goto out; +- } +- e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg); +- mii_reg |= MII_CR_POWER_DOWN; +- e1000_write_phy_reg(hw, PHY_CTRL, mii_reg); +- mdelay(1); +- } +-out: +- return; ++ E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); ++ return 0; + } + + void e1000_down(struct e1000_adapter *adapter) + { + struct net_device *netdev = adapter->netdev; ++ u32 tctl, rctl; + + /* signal that we're down so the interrupt handler does not + * reschedule our watchdog timer */ +- set_bit(__E1000_DOWN, &adapter->flags); +- +- napi_disable(&adapter->napi); +- ++ set_bit(__E1000_DOWN, &adapter->state); ++ ++ /* disable receives in the hardware */ ++ rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); ++ E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); ++ /* flush and sleep below */ ++ ++ netif_tx_disable(netdev); ++ ++ /* disable transmits in the hardware */ ++ tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); ++ tctl &= ~E1000_TCTL_EN; ++ E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); ++ /* flush both disables and wait for them to finish */ ++ E1000_WRITE_FLUSH(&adapter->hw); ++ msleep(10); ++ ++#ifdef CONFIG_E1000_NAPI ++ napi_disable(&adapter->rx_ring->napi); ++ ++#endif + e1000_irq_disable(adapter); + + del_timer_sync(&adapter->tx_fifo_stall_timer); +@@ -598,10 +500,9 @@ + del_timer_sync(&adapter->phy_info_timer); + + netdev->tx_queue_len = adapter->tx_queue_len; ++ netif_carrier_off(netdev); + adapter->link_speed = 0; + adapter->link_duplex = 0; +- netif_carrier_off(netdev); +- netif_stop_queue(netdev); + + e1000_reset(adapter); + e1000_clean_all_tx_rings(adapter); +@@ -611,33 +512,33 @@ + void e1000_reinit_locked(struct e1000_adapter *adapter) + { + WARN_ON(in_interrupt()); +- while (test_and_set_bit(__E1000_RESETTING, &adapter->flags)) ++ while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) + msleep(1); + e1000_down(adapter); + e1000_up(adapter); +- clear_bit(__E1000_RESETTING, &adapter->flags); ++ clear_bit(__E1000_RESETTING, &adapter->state); + } + + void e1000_reset(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; ++ struct e1000_mac_info *mac = &adapter->hw.mac; ++ struct e1000_fc_info *fc = &adapter->hw.fc; + u32 pba = 0, tx_space, min_tx_space, min_rx_space; +- u16 fc_high_water_mark = E1000_FC_HIGH_DIFF; +- bool legacy_pba_adjust = false; ++ bool legacy_pba_adjust = FALSE; ++ u16 hwm; + + /* Repartition Pba for greater than 9k mtu + * To take effect CTRL.RST is required. + */ + +- switch (hw->mac_type) { +- case e1000_82542_rev2_0: +- case e1000_82542_rev2_1: ++ switch (mac->type) { ++ case e1000_82542: + case e1000_82543: + case e1000_82544: + case e1000_82540: + case e1000_82541: + case e1000_82541_rev_2: +- legacy_pba_adjust = true; ++ legacy_pba_adjust = TRUE; + pba = E1000_PBA_48K; + break; + case e1000_82545: +@@ -648,57 +549,49 @@ + break; + case e1000_82547: + case e1000_82547_rev_2: +- legacy_pba_adjust = true; ++ legacy_pba_adjust = TRUE; + pba = E1000_PBA_30K; + break; +- case e1000_82571: +- case e1000_82572: +- case e1000_80003es2lan: +- pba = E1000_PBA_38K; +- break; +- case e1000_82573: +- pba = E1000_PBA_20K; +- break; +- case e1000_ich8lan: +- pba = E1000_PBA_8K; + case e1000_undefined: + case e1000_num_macs: + break; + } + +- if (legacy_pba_adjust) { +- if (adapter->netdev->mtu > E1000_RXBUFFER_8192) ++ if (legacy_pba_adjust == TRUE) { ++ if (adapter->max_frame_size > E1000_RXBUFFER_8192) + pba -= 8; /* allocate more FIFO for Tx */ + +- if (hw->mac_type == e1000_82547) { ++ if (mac->type == e1000_82547) { + adapter->tx_fifo_head = 0; + adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT; + adapter->tx_fifo_size = + (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT; + atomic_set(&adapter->tx_fifo_stall, 0); + } +- } else if (hw->max_frame_size > MAXIMUM_ETHERNET_FRAME_SIZE) { ++ } else if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) { + /* adjust PBA for jumbo frames */ +- ew32(PBA, pba); ++ E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); + + /* To maintain wire speed transmits, the Tx FIFO should be +- * large enough to accomodate two full transmit packets, ++ * large enough to accommodate two full transmit packets, + * rounded up to the next 1KB and expressed in KB. Likewise, +- * the Rx FIFO should be large enough to accomodate at least ++ * the Rx FIFO should be large enough to accommodate at least + * one full receive packet and is similarly rounded up and + * expressed in KB. */ +- pba = er32(PBA); ++ pba = E1000_READ_REG(&adapter->hw, E1000_PBA); + /* upper 16 bits has Tx packet buffer allocation size in KB */ + tx_space = pba >> 16; + /* lower 16 bits has Rx packet buffer allocation size in KB */ + pba &= 0xffff; +- /* don't include ethernet FCS because hardware appends/strips */ +- min_rx_space = adapter->netdev->mtu + ENET_HEADER_SIZE + +- VLAN_TAG_SIZE; +- min_tx_space = min_rx_space; +- min_tx_space *= 2; ++ /* the tx fifo also stores 16 bytes of information about the tx ++ * but don't include ethernet FCS because hardware appends it */ ++ min_tx_space = (adapter->max_frame_size + ++ sizeof(struct e1000_tx_desc) - ++ ETH_FCS_LEN) * 2; + min_tx_space = ALIGN(min_tx_space, 1024); + min_tx_space >>= 10; ++ /* software strips receive CRC, so leave room for it */ ++ min_rx_space = adapter->max_frame_size; + min_rx_space = ALIGN(min_rx_space, 1024); + min_rx_space >>= 10; + +@@ -710,7 +603,7 @@ + pba = pba - (min_tx_space - tx_space); + + /* PCI/PCIx hardware has PBA alignment constraints */ +- switch (hw->mac_type) { ++ switch (mac->type) { + case e1000_82545 ... e1000_82546_rev_3: + pba &= ~(E1000_PBA_8K - 1); + break; +@@ -721,179 +614,86 @@ + /* if short on rx space, rx wins and must trump tx + * adjustment or use Early Receive if available */ + if (pba < min_rx_space) { +- switch (hw->mac_type) { +- case e1000_82573: +- /* ERT enabled in e1000_configure_rx */ +- break; +- default: +- pba = min_rx_space; +- break; +- } +- } +- } +- } +- +- ew32(PBA, pba); ++ pba = min_rx_space; ++ } ++ } ++ } ++ ++ E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); + + /* flow control settings */ +- /* Set the FC high water mark to 90% of the FIFO size. +- * Required to clear last 3 LSB */ +- fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8; +- /* We can't use 90% on small FIFOs because the remainder +- * would be less than 1 full frame. In this case, we size +- * it to allow at least a full frame above the high water +- * mark. */ +- if (pba < E1000_PBA_16K) +- fc_high_water_mark = (pba * 1024) - 1600; +- +- hw->fc_high_water = fc_high_water_mark; +- hw->fc_low_water = fc_high_water_mark - 8; +- if (hw->mac_type == e1000_80003es2lan) +- hw->fc_pause_time = 0xFFFF; +- else +- hw->fc_pause_time = E1000_FC_PAUSE_TIME; +- hw->fc_send_xon = 1; +- hw->fc = hw->original_fc; ++ /* The high water mark must be low enough to fit one full frame ++ * (or the size used for early receive) above it in the Rx FIFO. ++ * Set it to the lower of: ++ * - 90% of the Rx FIFO size, and ++ * - the full Rx FIFO size minus the early receive size (for parts ++ * with ERT support assuming ERT set to E1000_ERT_2048), or ++ * - the full Rx FIFO size minus one full frame */ ++ hwm = min(((pba << 10) * 9 / 10), ++ ((pba << 10) - adapter->max_frame_size)); ++ ++ fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ ++ fc->low_water = fc->high_water - 8; ++ ++ fc->pause_time = E1000_FC_PAUSE_TIME; ++ fc->send_xon = 1; ++ fc->current_mode = fc->requested_mode; + + /* Allow time for pending master requests to run */ +- e1000_reset_hw(hw); +- if (hw->mac_type >= e1000_82544) +- ew32(WUC, 0); +- +- if (e1000_init_hw(hw)) ++ e1000_reset_hw(&adapter->hw); ++ ++ if (mac->type >= e1000_82544) ++ E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); ++ ++ if (e1000_init_hw(&adapter->hw)) + DPRINTK(PROBE, ERR, "Hardware Error\n"); ++#ifdef NETIF_F_HW_VLAN_TX + e1000_update_mng_vlan(adapter); +- ++#endif + /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */ +- if (hw->mac_type >= e1000_82544 && +- hw->mac_type <= e1000_82547_rev_2 && +- hw->autoneg == 1 && +- hw->autoneg_advertised == ADVERTISE_1000_FULL) { +- u32 ctrl = er32(CTRL); ++ if (mac->type >= e1000_82544 && ++ mac->type <= e1000_82547_rev_2 && ++ mac->autoneg == 1 && ++ adapter->hw.phy.autoneg_advertised == ADVERTISE_1000_FULL) { ++ u32 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); + /* clear phy power management bit if we are in gig only mode, + * which if enabled will attempt negotiation to 100Mb, which + * can cause a loss of link at power off or driver unload */ + ctrl &= ~E1000_CTRL_SWDPIN3; +- ew32(CTRL, ctrl); ++ E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); + } + + /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ +- ew32(VET, ETHERNET_IEEE_VLAN_TYPE); +- +- e1000_reset_adaptive(hw); +- e1000_phy_get_info(hw, &adapter->phy_info); +- +- if (!adapter->smart_power_down && +- (hw->mac_type == e1000_82571 || +- hw->mac_type == e1000_82572)) { +- u16 phy_data = 0; +- /* speed up time to link by disabling smart power down, ignore +- * the return value of this function because there is nothing +- * different we would do if it failed */ +- e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, +- &phy_data); +- phy_data &= ~IGP02E1000_PM_SPD; +- e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, +- phy_data); +- } ++ E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERNET_IEEE_VLAN_TYPE); ++ ++ e1000_reset_adaptive(&adapter->hw); ++ e1000_get_phy_info(&adapter->hw); + + e1000_release_manageability(adapter); + } + +-/** +- * Dump the eeprom for users having checksum issues +- **/ +-static void e1000_dump_eeprom(struct e1000_adapter *adapter) +-{ +- struct net_device *netdev = adapter->netdev; +- struct ethtool_eeprom eeprom; +- const struct ethtool_ops *ops = netdev->ethtool_ops; +- u8 *data; +- int i; +- u16 csum_old, csum_new = 0; +- +- eeprom.len = ops->get_eeprom_len(netdev); +- eeprom.offset = 0; +- +- data = kmalloc(eeprom.len, GFP_KERNEL); +- if (!data) { +- printk(KERN_ERR "Unable to allocate memory to dump EEPROM" +- " data\n"); +- return; +- } +- +- ops->get_eeprom(netdev, &eeprom, data); +- +- csum_old = (data[EEPROM_CHECKSUM_REG * 2]) + +- (data[EEPROM_CHECKSUM_REG * 2 + 1] << 8); +- for (i = 0; i < EEPROM_CHECKSUM_REG * 2; i += 2) +- csum_new += data[i] + (data[i + 1] << 8); +- csum_new = EEPROM_SUM - csum_new; +- +- printk(KERN_ERR "/*********************/\n"); +- printk(KERN_ERR "Current EEPROM Checksum : 0x%04x\n", csum_old); +- printk(KERN_ERR "Calculated : 0x%04x\n", csum_new); +- +- printk(KERN_ERR "Offset Values\n"); +- printk(KERN_ERR "======== ======\n"); +- print_hex_dump(KERN_ERR, "", DUMP_PREFIX_OFFSET, 16, 1, data, 128, 0); +- +- printk(KERN_ERR "Include this output when contacting your support " +- "provider.\n"); +- printk(KERN_ERR "This is not a software error! Something bad " +- "happened to your hardware or\n"); +- printk(KERN_ERR "EEPROM image. Ignoring this " +- "problem could result in further problems,\n"); +- printk(KERN_ERR "possibly loss of data, corruption or system hangs!\n"); +- printk(KERN_ERR "The MAC Address will be reset to 00:00:00:00:00:00, " +- "which is invalid\n"); +- printk(KERN_ERR "and requires you to set the proper MAC " +- "address manually before continuing\n"); +- printk(KERN_ERR "to enable this network device.\n"); +- printk(KERN_ERR "Please inspect the EEPROM dump and report the issue " +- "to your hardware vendor\n"); +- printk(KERN_ERR "or Intel Customer Support.\n"); +- printk(KERN_ERR "/*********************/\n"); +- +- kfree(data); +-} +- +-/** +- * e1000_is_need_ioport - determine if an adapter needs ioport resources or not +- * @pdev: PCI device information struct +- * +- * Return true if an adapter needs ioport resources +- **/ +-static int e1000_is_need_ioport(struct pci_dev *pdev) +-{ +- switch (pdev->device) { +- case E1000_DEV_ID_82540EM: +- case E1000_DEV_ID_82540EM_LOM: +- case E1000_DEV_ID_82540EP: +- case E1000_DEV_ID_82540EP_LOM: +- case E1000_DEV_ID_82540EP_LP: +- case E1000_DEV_ID_82541EI: +- case E1000_DEV_ID_82541EI_MOBILE: +- case E1000_DEV_ID_82541ER: +- case E1000_DEV_ID_82541ER_LOM: +- case E1000_DEV_ID_82541GI: +- case E1000_DEV_ID_82541GI_LF: +- case E1000_DEV_ID_82541GI_MOBILE: +- case E1000_DEV_ID_82544EI_COPPER: +- case E1000_DEV_ID_82544EI_FIBER: +- case E1000_DEV_ID_82544GC_COPPER: +- case E1000_DEV_ID_82544GC_LOM: +- case E1000_DEV_ID_82545EM_COPPER: +- case E1000_DEV_ID_82545EM_FIBER: +- case E1000_DEV_ID_82546EB_COPPER: +- case E1000_DEV_ID_82546EB_FIBER: +- case E1000_DEV_ID_82546EB_QUAD_COPPER: +- return true; +- default: +- return false; +- } +-} +- ++#ifdef HAVE_NET_DEVICE_OPS ++static const struct net_device_ops e1000_netdev_ops = { ++ .ndo_open = e1000_open, ++ .ndo_stop = e1000_close, ++ .ndo_start_xmit = e1000_xmit_frame, ++ .ndo_get_stats = e1000_get_stats, ++ .ndo_set_multicast_list = e1000_set_multi, ++ .ndo_set_mac_address = e1000_set_mac, ++ .ndo_change_mtu = e1000_change_mtu, ++ .ndo_do_ioctl = e1000_ioctl, ++ .ndo_tx_timeout = e1000_tx_timeout, ++ .ndo_validate_addr = eth_validate_addr, ++ ++ .ndo_vlan_rx_register = e1000_vlan_rx_register, ++ .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, ++ .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = e1000_netpoll, ++#endif ++}; ++ ++#endif /* HAVE_NET_DEVICE_OPS */ + /** + * e1000_probe - Device Initialization Routine + * @pdev: PCI device information struct +@@ -906,50 +706,33 @@ + * and a hardware reset occur. + **/ + static int __devinit e1000_probe(struct pci_dev *pdev, +- const struct pci_device_id *ent) ++ const struct pci_device_id *ent) + { + struct net_device *netdev; + struct e1000_adapter *adapter; +- struct e1000_hw *hw; + + static int cards_found = 0; + static int global_quad_port_a = 0; /* global ksp3 port a indication */ + int i, err, pci_using_dac; + u16 eeprom_data = 0; + u16 eeprom_apme_mask = E1000_EEPROM_APME; +- int bars, need_ioport; +- DECLARE_MAC_BUF(mac); +- +- /* do not allocate ioport bars when not needed */ +- need_ioport = e1000_is_need_ioport(pdev); +- if (need_ioport) { +- bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); +- err = pci_enable_device(pdev); +- } else { +- bars = pci_select_bars(pdev, IORESOURCE_MEM); +- err = pci_enable_device_mem(pdev); +- } +- if (err) ++ if ((err = pci_enable_device(pdev))) + return err; + +- if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) && +- !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) { ++ if (!ignore_64bit_dma && ++ !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) && ++ !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) { + pci_using_dac = 1; + } else { +- err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); +- if (err) { +- err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); +- if (err) { +- E1000_ERR("No usable DMA configuration, " +- "aborting\n"); +- goto err_dma; +- } ++ if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) && ++ (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) { ++ E1000_ERR("No usable DMA configuration, aborting\n"); ++ goto err_dma; + } + pci_using_dac = 0; + } + +- err = pci_request_selected_regions(pdev, bars, e1000_driver_name); +- if (err) ++ if ((err = pci_request_regions(pdev, e1000_driver_name))) + goto err_pci_reg; + + pci_set_master(pdev); +@@ -959,143 +742,167 @@ + if (!netdev) + goto err_alloc_etherdev; + ++ SET_MODULE_OWNER(netdev); + SET_NETDEV_DEV(netdev, &pdev->dev); + + pci_set_drvdata(pdev, netdev); + adapter = netdev_priv(netdev); + adapter->netdev = netdev; + adapter->pdev = pdev; ++ adapter->hw.back = adapter; + adapter->msg_enable = (1 << debug) - 1; +- adapter->bars = bars; +- adapter->need_ioport = need_ioport; +- +- hw = &adapter->hw; +- hw->back = adapter; + + err = -EIO; +- hw->hw_addr = ioremap(pci_resource_start(pdev, BAR_0), +- pci_resource_len(pdev, BAR_0)); +- if (!hw->hw_addr) ++ adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, BAR_0), ++ pci_resource_len(pdev, BAR_0)); ++ if (!adapter->hw.hw_addr) + goto err_ioremap; + +- if (adapter->need_ioport) { +- for (i = BAR_1; i <= BAR_5; i++) { +- if (pci_resource_len(pdev, i) == 0) +- continue; +- if (pci_resource_flags(pdev, i) & IORESOURCE_IO) { +- hw->io_base = pci_resource_start(pdev, i); +- break; +- } +- } +- } +- ++ for (i = BAR_1; i <= BAR_5; i++) { ++ if (pci_resource_len(pdev, i) == 0) ++ continue; ++ if (pci_resource_flags(pdev, i) & IORESOURCE_IO) { ++ adapter->hw.io_base = pci_resource_start(pdev, i); ++ break; ++ } ++ } ++ ++#ifdef HAVE_NET_DEVICE_OPS ++ netdev->netdev_ops = &e1000_netdev_ops; ++#else + netdev->open = &e1000_open; + netdev->stop = &e1000_close; + netdev->hard_start_xmit = &e1000_xmit_frame; + netdev->get_stats = &e1000_get_stats; +- netdev->set_rx_mode = &e1000_set_rx_mode; ++ netdev->set_multicast_list = &e1000_set_multi; + netdev->set_mac_address = &e1000_set_mac; + netdev->change_mtu = &e1000_change_mtu; + netdev->do_ioctl = &e1000_ioctl; +- e1000_set_ethtool_ops(netdev); ++#ifdef HAVE_TX_TIMEOUT + netdev->tx_timeout = &e1000_tx_timeout; +- netdev->watchdog_timeo = 5 * HZ; +- netif_napi_add(netdev, &adapter->napi, e1000_clean, 64); ++#endif ++#ifdef NETIF_F_HW_VLAN_TX + netdev->vlan_rx_register = e1000_vlan_rx_register; + netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid; + netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid; ++#endif + #ifdef CONFIG_NET_POLL_CONTROLLER + netdev->poll_controller = e1000_netpoll; + #endif ++#endif /* HAVE_NET_DEVICE_OPS */ ++ e1000_set_ethtool_ops(netdev); ++ netdev->watchdog_timeo = 5 * HZ; ++ + strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); + + adapter->bd_number = cards_found; + + /* setup the private structure */ +- +- err = e1000_sw_init(adapter); +- if (err) ++ if ((err = e1000_sw_init(adapter))) + goto err_sw_init; + + err = -EIO; +- /* Flash BAR mapping must happen after e1000_sw_init +- * because it depends on mac_type */ +- if ((hw->mac_type == e1000_ich8lan) && +- (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { +- hw->flash_address = +- ioremap(pci_resource_start(pdev, 1), +- pci_resource_len(pdev, 1)); +- if (!hw->flash_address) +- goto err_flashmap; +- } +- +- if (e1000_check_phy_reset_block(hw)) ++ if ((err = e1000_init_mac_params(&adapter->hw))) ++ goto err_hw_init; ++ ++ if ((err = e1000_init_nvm_params(&adapter->hw))) ++ goto err_hw_init; ++ ++ if ((err = e1000_init_phy_params(&adapter->hw))) ++ goto err_hw_init; ++ ++ e1000_get_bus_info(&adapter->hw); ++ ++ e1000_init_script_state_82541(&adapter->hw, TRUE); ++ e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); ++ ++ adapter->hw.phy.autoneg_wait_to_complete = FALSE; ++ adapter->hw.mac.adaptive_ifs = TRUE; ++ ++ /* Copper options */ ++ ++ if (adapter->hw.phy.media_type == e1000_media_type_copper) { ++ adapter->hw.phy.mdix = AUTO_ALL_MODES; ++ adapter->hw.phy.disable_polarity_correction = FALSE; ++ adapter->hw.phy.ms_type = E1000_MASTER_SLAVE; ++ } ++ ++ if (e1000_check_reset_block(&adapter->hw)) + DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n"); + +- if (hw->mac_type >= e1000_82543) { ++#ifdef MAX_SKB_FRAGS ++ if (adapter->hw.mac.type >= e1000_82543) { ++#ifdef NETIF_F_HW_VLAN_TX + netdev->features = NETIF_F_SG | + NETIF_F_HW_CSUM | + NETIF_F_HW_VLAN_TX | + NETIF_F_HW_VLAN_RX | + NETIF_F_HW_VLAN_FILTER; +- if (hw->mac_type == e1000_ich8lan) +- netdev->features &= ~NETIF_F_HW_VLAN_FILTER; +- } +- +- if ((hw->mac_type >= e1000_82544) && +- (hw->mac_type != e1000_82547)) ++#else ++ netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM; ++#endif ++ } ++ ++#ifdef NETIF_F_TSO ++ if ((adapter->hw.mac.type >= e1000_82544) && ++ (adapter->hw.mac.type != e1000_82547)) { ++ adapter->flags |= E1000_FLAG_HAS_TSO; + netdev->features |= NETIF_F_TSO; +- +- if (hw->mac_type > e1000_82547_rev_2) +- netdev->features |= NETIF_F_TSO6; ++ } ++ ++#endif + if (pci_using_dac) + netdev->features |= NETIF_F_HIGHDMA; + +- netdev->features |= NETIF_F_LLTX; +- +- adapter->en_mng_pt = e1000_enable_mng_pass_thru(hw); +- +- /* initialize eeprom parameters */ +- if (e1000_init_eeprom_params(hw)) { +- E1000_ERR("EEPROM initialization failed\n"); ++#endif ++ ++ /* Hardware features, flags and workarounds */ ++ if (adapter->hw.mac.type >= e1000_82540) { ++ adapter->flags |= E1000_FLAG_HAS_SMBUS; ++ adapter->flags |= E1000_FLAG_HAS_INTR_MODERATION; ++ } ++ ++ if (adapter->hw.mac.type == e1000_82543) ++ adapter->flags |= E1000_FLAG_BAD_TX_CARRIER_STATS_FD; ++ ++ adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw); ++ ++ /* before reading the NVM, reset the controller to ++ * put the device in a known good starting state */ ++ ++ e1000_reset_hw(&adapter->hw); ++ ++ /* make sure we don't intercept ARP packets until we're up */ ++ e1000_release_manageability(adapter); ++ ++ /* make sure the NVM is good */ ++ ++ if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { ++ DPRINTK(PROBE, ERR, "The NVM Checksum Is Not Valid\n"); ++ err = -EIO; + goto err_eeprom; + } + +- /* before reading the EEPROM, reset the controller to +- * put the device in a known good starting state */ +- +- e1000_reset_hw(hw); +- +- /* make sure the EEPROM is good */ +- if (e1000_validate_eeprom_checksum(hw) < 0) { +- DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n"); +- e1000_dump_eeprom(adapter); +- /* +- * set MAC address to all zeroes to invalidate and temporary +- * disable this device for the user. This blocks regular +- * traffic while still permitting ethtool ioctls from reaching +- * the hardware as well as allowing the user to run the +- * interface after manually setting a hw addr using +- * `ip set address` +- */ +- memset(hw->mac_addr, 0, netdev->addr_len); +- } else { +- /* copy the MAC address out of the EEPROM */ +- if (e1000_read_mac_addr(hw)) +- DPRINTK(PROBE, ERR, "EEPROM Read Error\n"); +- } +- /* don't block initalization here due to bad MAC address */ +- memcpy(netdev->dev_addr, hw->mac_addr, netdev->addr_len); +- memcpy(netdev->perm_addr, hw->mac_addr, netdev->addr_len); +- +- if (!is_valid_ether_addr(netdev->perm_addr)) ++ /* copy the MAC address out of the NVM */ ++ ++ if (e1000_read_mac_addr(&adapter->hw)) ++ DPRINTK(PROBE, ERR, "NVM Read Error\n"); ++ memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); ++#ifdef ETHTOOL_GPERMADDR ++ memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len); ++ ++ if (!is_valid_ether_addr(netdev->perm_addr)) { ++#else ++ if (!is_valid_ether_addr(netdev->dev_addr)) { ++#endif + DPRINTK(PROBE, ERR, "Invalid MAC Address\n"); +- +- e1000_get_bus_info(hw); ++ err = -EIO; ++ goto err_eeprom; ++ } + + init_timer(&adapter->tx_fifo_stall_timer); + adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall; +- adapter->tx_fifo_stall_timer.data = (unsigned long)adapter; ++ adapter->tx_fifo_stall_timer.data = (unsigned long) adapter; + + init_timer(&adapter->watchdog_timer); + adapter->watchdog_timer.function = &e1000_watchdog; +@@ -1103,9 +910,10 @@ + + init_timer(&adapter->phy_info_timer); + adapter->phy_info_timer.function = &e1000_update_phy_info; +- adapter->phy_info_timer.data = (unsigned long)adapter; ++ adapter->phy_info_timer.data = (unsigned long) adapter; + + INIT_WORK(&adapter->reset_task, e1000_reset_task); ++ INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); + + e1000_check_options(adapter); + +@@ -1114,34 +922,26 @@ + * enable the ACPI Magic Packet filter + */ + +- switch (hw->mac_type) { +- case e1000_82542_rev2_0: +- case e1000_82542_rev2_1: ++ switch (adapter->hw.mac.type) { ++ case e1000_82542: + case e1000_82543: + break; + case e1000_82544: +- e1000_read_eeprom(hw, +- EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); ++ e1000_read_nvm(&adapter->hw, ++ NVM_INIT_CONTROL2_REG, 1, &eeprom_data); + eeprom_apme_mask = E1000_EEPROM_82544_APM; +- break; +- case e1000_ich8lan: +- e1000_read_eeprom(hw, +- EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data); +- eeprom_apme_mask = E1000_EEPROM_ICH8_APME; + break; + case e1000_82546: + case e1000_82546_rev_3: +- case e1000_82571: +- case e1000_80003es2lan: +- if (er32(STATUS) & E1000_STATUS_FUNC_1){ +- e1000_read_eeprom(hw, +- EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); ++ if (adapter->hw.bus.func == 1) { ++ e1000_read_nvm(&adapter->hw, ++ NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); + break; + } + /* Fall Through */ + default: +- e1000_read_eeprom(hw, +- EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); ++ e1000_read_nvm(&adapter->hw, ++ NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); + break; + } + if (eeprom_data & eeprom_apme_mask) +@@ -1156,22 +956,18 @@ + break; + case E1000_DEV_ID_82546EB_FIBER: + case E1000_DEV_ID_82546GB_FIBER: +- case E1000_DEV_ID_82571EB_FIBER: + /* Wake events only supported on port A for dual fiber + * regardless of eeprom setting */ +- if (er32(STATUS) & E1000_STATUS_FUNC_1) ++ if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & ++ E1000_STATUS_FUNC_1) + adapter->eeprom_wol = 0; + break; + case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: +- case E1000_DEV_ID_82571EB_QUAD_COPPER: +- case E1000_DEV_ID_82571EB_QUAD_FIBER: +- case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: +- case E1000_DEV_ID_82571PT_QUAD_COPPER: + /* if quad port adapter, disable WoL on all but port A */ + if (global_quad_port_a != 0) + adapter->eeprom_wol = 0; + else +- adapter->quad_port_a = 1; ++ adapter->flags |= E1000_FLAG_QUAD_PORT_A; + /* Reset for multiple quad port adapters */ + if (++global_quad_port_a == 4) + global_quad_port_a = 0; +@@ -1180,42 +976,29 @@ + + /* initialize the wol settings based on the eeprom settings */ + adapter->wol = adapter->eeprom_wol; +- device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); + + /* print bus type/speed/width info */ ++ { ++ struct e1000_hw *hw = &adapter->hw; + DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ", +- ((hw->bus_type == e1000_bus_type_pcix) ? "-X" : +- (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")), +- ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" : +- (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" : +- (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" : +- (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" : +- (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"), +- ((hw->bus_width == e1000_bus_width_64) ? "64-bit" : +- (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" : +- (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" : ++ ((hw->bus.type == e1000_bus_type_pcix) ? "-X" : ++ (hw->bus.type == e1000_bus_type_pci_express ? " Express":"")), ++ ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : ++ (hw->bus.speed == e1000_bus_speed_133) ? "133MHz" : ++ (hw->bus.speed == e1000_bus_speed_120) ? "120MHz" : ++ (hw->bus.speed == e1000_bus_speed_100) ? "100MHz" : ++ (hw->bus.speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"), ++ ((hw->bus.width == e1000_bus_width_64) ? "64-bit" : ++ (hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : ++ (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : + "32-bit")); +- +- printk("%s\n", print_mac(mac, netdev->dev_addr)); +- +- if (hw->bus_type == e1000_bus_type_pci_express) { +- DPRINTK(PROBE, WARNING, "This device (id %04x:%04x) will no " +- "longer be supported by this driver in the future.\n", +- pdev->vendor, pdev->device); +- DPRINTK(PROBE, WARNING, "please use the \"e1000e\" " +- "driver instead.\n"); +- } ++ } ++ ++ for (i = 0; i < 6; i++) ++ printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':'); + + /* reset the hardware with the new settings */ + e1000_reset(adapter); +- +- /* If the controller is 82573 and f/w is AMT, do not set +- * DRV_LOAD until the interface is up. For all other cases, +- * let the f/w know that the h/w is now under the control +- * of the driver. */ +- if (hw->mac_type != e1000_82573 || +- !e1000_check_mng_mode(hw)) +- e1000_get_hw_control(adapter); + + /* tell the stack to leave us alone until e1000_open() is called */ + netif_carrier_off(netdev); +@@ -1232,26 +1015,22 @@ + return 0; + + err_register: +- e1000_release_hw_control(adapter); ++err_hw_init: + err_eeprom: +- if (!e1000_check_phy_reset_block(hw)) +- e1000_phy_hw_reset(hw); +- +- if (hw->flash_address) +- iounmap(hw->flash_address); +-err_flashmap: +- for (i = 0; i < adapter->num_rx_queues; i++) +- dev_put(&adapter->polling_netdev[i]); ++ if (!e1000_check_reset_block(&adapter->hw)) ++ e1000_phy_hw_reset(&adapter->hw); ++ ++ if (adapter->hw.flash_address) ++ iounmap(adapter->hw.flash_address); + + kfree(adapter->tx_ring); + kfree(adapter->rx_ring); +- kfree(adapter->polling_netdev); + err_sw_init: +- iounmap(hw->hw_addr); ++ iounmap(adapter->hw.hw_addr); + err_ioremap: + free_netdev(netdev); + err_alloc_etherdev: +- pci_release_selected_regions(pdev, bars); ++ pci_release_regions(pdev); + err_pci_reg: + err_dma: + pci_disable_device(pdev); +@@ -1267,38 +1046,38 @@ + * Hot-Plug event, or because the driver is going to be removed from + * memory. + **/ +- + static void __devexit e1000_remove(struct pci_dev *pdev) + { + struct net_device *netdev = pci_get_drvdata(pdev); + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; +- int i; ++ ++ /* flush_scheduled work may reschedule our watchdog task, so ++ * explicitly disable watchdog tasks from being rescheduled */ ++ set_bit(__E1000_DOWN, &adapter->state); ++ del_timer_sync(&adapter->tx_fifo_stall_timer); ++ del_timer_sync(&adapter->watchdog_timer); ++ del_timer_sync(&adapter->phy_info_timer); + + cancel_work_sync(&adapter->reset_task); ++ cancel_work_sync(&adapter->watchdog_task); + + e1000_release_manageability(adapter); + +- /* Release control of h/w to f/w. If f/w is AMT enabled, this +- * would have already happened in close and is redundant. */ +- e1000_release_hw_control(adapter); +- +- for (i = 0; i < adapter->num_rx_queues; i++) +- dev_put(&adapter->polling_netdev[i]); +- + unregister_netdev(netdev); + +- if (!e1000_check_phy_reset_block(hw)) +- e1000_phy_hw_reset(hw); +- ++ if (!e1000_check_reset_block(&adapter->hw)) ++ e1000_phy_hw_reset(&adapter->hw); ++ ++#ifdef CONFIG_E1000_NAPI ++ netif_napi_del(&adapter->rx_ring->napi); ++#endif + kfree(adapter->tx_ring); + kfree(adapter->rx_ring); +- kfree(adapter->polling_netdev); +- +- iounmap(hw->hw_addr); +- if (hw->flash_address) +- iounmap(hw->flash_address); +- pci_release_selected_regions(pdev, adapter->bars); ++ ++ iounmap(adapter->hw.hw_addr); ++ if (adapter->hw.flash_address) ++ iounmap(adapter->hw.flash_address); ++ pci_release_regions(pdev); + + free_netdev(netdev); + +@@ -1313,121 +1092,72 @@ + * Fields are initialized based on PCI device information and + * OS network device settings (MTU size). + **/ +- + static int __devinit e1000_sw_init(struct e1000_adapter *adapter) + { + struct e1000_hw *hw = &adapter->hw; + struct net_device *netdev = adapter->netdev; + struct pci_dev *pdev = adapter->pdev; +- int i; + + /* PCI config space info */ + + hw->vendor_id = pdev->vendor; + hw->device_id = pdev->device; + hw->subsystem_vendor_id = pdev->subsystem_vendor; +- hw->subsystem_id = pdev->subsystem_device; +- hw->revision_id = pdev->revision; +- +- pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); ++ hw->subsystem_device_id = pdev->subsystem_device; ++ ++ pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); ++ ++ pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); + + adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; +- adapter->rx_ps_bsize0 = E1000_RXBUFFER_128; +- hw->max_frame_size = netdev->mtu + +- ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; +- hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE; +- +- /* identify the MAC */ +- +- if (e1000_set_mac_type(hw)) { +- DPRINTK(PROBE, ERR, "Unknown MAC Type\n"); ++ adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; ++ adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; ++ ++ hw->fc.requested_mode = e1000_fc_default; ++ ++ /* Initialize the hardware-specific values */ ++ if (e1000_setup_init_funcs(hw, FALSE)) { ++ DPRINTK(PROBE, ERR, "Hardware Initialization Failure\n"); + return -EIO; + } + +- switch (hw->mac_type) { +- default: +- break; +- case e1000_82541: +- case e1000_82547: +- case e1000_82541_rev_2: +- case e1000_82547_rev_2: +- hw->phy_init_script = 1; +- break; +- } +- +- e1000_set_media_type(hw); +- +- hw->wait_autoneg_complete = false; +- hw->tbi_compatibility_en = true; +- hw->adaptive_ifs = true; +- +- /* Copper options */ +- +- if (hw->media_type == e1000_media_type_copper) { +- hw->mdix = AUTO_ALL_MODES; +- hw->disable_polarity_correction = false; +- hw->master_slave = E1000_MASTER_SLAVE; +- } +- +- adapter->num_tx_queues = 1; +- adapter->num_rx_queues = 1; +- +- if (e1000_alloc_queues(adapter)) { ++ if (e1000_alloc_rings(adapter)) { + DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); + return -ENOMEM; + } + +- for (i = 0; i < adapter->num_rx_queues; i++) { +- adapter->polling_netdev[i].priv = adapter; +- dev_hold(&adapter->polling_netdev[i]); +- set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state); +- } +- spin_lock_init(&adapter->tx_queue_lock); +- ++#ifdef CONFIG_E1000_NAPI ++ netif_napi_add(adapter->netdev, &adapter->rx_ring->napi, e1000_poll, 64); ++ ++#endif + /* Explicitly disable IRQ since the NIC can be in any state. */ + e1000_irq_disable(adapter); + + spin_lock_init(&adapter->stats_lock); + +- set_bit(__E1000_DOWN, &adapter->flags); +- +- return 0; +-} +- +-/** +- * e1000_alloc_queues - Allocate memory for all rings ++ set_bit(__E1000_DOWN, &adapter->state); ++ return 0; ++} ++ ++/** ++ * e1000_alloc_rings - Allocate memory for all rings + * @adapter: board private structure to initialize +- * +- * We allocate one ring per queue at run-time since we don't know the +- * number of queues at compile-time. The polling_netdev array is +- * intended for Multiqueue, but should work fine with a single queue. +- **/ +- +-static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter) +-{ +- adapter->tx_ring = kcalloc(adapter->num_tx_queues, +- sizeof(struct e1000_tx_ring), GFP_KERNEL); ++ **/ ++static int __devinit e1000_alloc_rings(struct e1000_adapter *adapter) ++{ ++ adapter->tx_ring = kzalloc(sizeof(struct e1000_tx_ring), GFP_KERNEL); + if (!adapter->tx_ring) + return -ENOMEM; + +- adapter->rx_ring = kcalloc(adapter->num_rx_queues, +- sizeof(struct e1000_rx_ring), GFP_KERNEL); ++ adapter->rx_ring = kzalloc(sizeof(struct e1000_rx_ring), GFP_KERNEL); + if (!adapter->rx_ring) { + kfree(adapter->tx_ring); + return -ENOMEM; + } + +- adapter->polling_netdev = kcalloc(adapter->num_rx_queues, +- sizeof(struct net_device), +- GFP_KERNEL); +- if (!adapter->polling_netdev) { +- kfree(adapter->tx_ring); +- kfree(adapter->rx_ring); +- return -ENOMEM; +- } +- + return E1000_SUCCESS; + } ++ + + /** + * e1000_open - Called when a network interface is made active +@@ -1441,15 +1171,12 @@ + * handler is registered with the OS, the watchdog timer is started, + * and the stack is notified that the interface is ready. + **/ +- + static int e1000_open(struct net_device *netdev) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; + int err; +- + /* disallow open during test */ +- if (test_bit(__E1000_TESTING, &adapter->flags)) ++ if (test_bit(__E1000_TESTING, &adapter->state)) + return -EBUSY; + + /* allocate transmit descriptors */ +@@ -1462,19 +1189,16 @@ + if (err) + goto err_setup_rx; + +- e1000_power_up_phy(adapter); +- ++ if (adapter->hw.phy.media_type == e1000_media_type_copper) ++ e1000_power_up_phy(&adapter->hw); ++ ++#ifdef NETIF_F_HW_VLAN_TX + adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; +- if ((hw->mng_cookie.status & +- E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) { ++ if ((adapter->hw.mng_cookie.status & ++ E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) { + e1000_update_mng_vlan(adapter); + } +- +- /* If AMT is enabled, let the firmware know that the network +- * interface is now open */ +- if (hw->mac_type == e1000_82573 && +- e1000_check_mng_mode(hw)) +- e1000_get_hw_control(adapter); ++#endif + + /* before we allocate an interrupt, we must be ready to handle it. + * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt +@@ -1482,27 +1206,34 @@ + * clean_rx handler before we do so. */ + e1000_configure(adapter); + ++ + err = e1000_request_irq(adapter); + if (err) + goto err_req_irq; + + /* From here on the code is the same as e1000_up() */ +- clear_bit(__E1000_DOWN, &adapter->flags); +- +- napi_enable(&adapter->napi); +- ++ clear_bit(__E1000_DOWN, &adapter->state); ++ ++#ifdef CONFIG_E1000_NAPI ++ napi_enable(&adapter->rx_ring->napi); ++ ++#endif + e1000_irq_enable(adapter); + +- netif_start_queue(netdev); +- + /* fire a link status change interrupt to start the watchdog */ +- ew32(ICS, E1000_ICS_LSC); ++ E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); + + return E1000_SUCCESS; + + err_req_irq: +- e1000_release_hw_control(adapter); +- e1000_power_down_phy(adapter); ++ /* Power down the PHY so no link is implied when interface is down * ++ * The PHY cannot be powered down if any of the following is TRUE * ++ * (a) WoL is enabled ++ * (b) AMT is active ++ * (c) SoL/IDER session is active */ ++ if (!adapter->wol && adapter->hw.mac.type >= e1000_82540 && ++ adapter->hw.phy.media_type == e1000_media_type_copper) ++ e1000_power_down_phy(&adapter->hw); + e1000_free_all_rx_resources(adapter); + err_setup_rx: + e1000_free_all_tx_resources(adapter); +@@ -1523,34 +1254,35 @@ + * needs to be disabled. A global MAC reset is issued to stop the + * hardware, and all transmit and receive resources are freed. + **/ +- + static int e1000_close(struct net_device *netdev) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; +- +- WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags)); ++ ++ WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); + e1000_down(adapter); +- e1000_power_down_phy(adapter); ++ /* Power down the PHY so no link is implied when interface is down * ++ * The PHY cannot be powered down if any of the following is TRUE * ++ * (a) WoL is enabled ++ * (b) AMT is active ++ * (c) SoL/IDER session is active */ ++ if (!adapter->wol && adapter->hw.mac.type >= e1000_82540 && ++ adapter->hw.phy.media_type == e1000_media_type_copper) ++ e1000_power_down_phy(&adapter->hw); + e1000_free_irq(adapter); + + e1000_free_all_tx_resources(adapter); + e1000_free_all_rx_resources(adapter); + ++#ifdef NETIF_F_HW_VLAN_TX + /* kill manageability vlan ID if supported, but not if a vlan with + * the same ID is registered on the host OS (let 8021q kill it) */ +- if ((hw->mng_cookie.status & +- E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) && ++ if ((adapter->hw.mng_cookie.status & ++ E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && + !(adapter->vlgrp && + vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id))) { + e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); + } +- +- /* If AMT is enabled, let the firmware know that the network +- * interface is now closed */ +- if (hw->mac_type == e1000_82573 && +- e1000_check_mng_mode(hw)) +- e1000_release_hw_control(adapter); ++#endif + + return 0; + } +@@ -1561,121 +1293,116 @@ + * @start: address of beginning of memory + * @len: length of memory + **/ +-static bool e1000_check_64k_bound(struct e1000_adapter *adapter, void *start, +- unsigned long len) +-{ +- struct e1000_hw *hw = &adapter->hw; +- unsigned long begin = (unsigned long)start; ++static bool e1000_check_64k_bound(struct e1000_adapter *adapter, ++ void *start, unsigned long len) ++{ ++ unsigned long begin = (unsigned long) start; + unsigned long end = begin + len; + + /* First rev 82545 and 82546 need to not allow any memory + * write location to cross 64k boundary due to errata 23 */ +- if (hw->mac_type == e1000_82545 || +- hw->mac_type == e1000_82546) { +- return ((begin ^ (end - 1)) >> 16) != 0 ? false : true; +- } +- +- return true; ++ if (adapter->hw.mac.type == e1000_82545 || ++ adapter->hw.mac.type == e1000_82546) { ++ return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE; ++ } ++ ++ return TRUE; + } + + /** + * e1000_setup_tx_resources - allocate Tx resources (Descriptors) + * @adapter: board private structure +- * @txdr: tx descriptor ring (for a specific queue) to setup ++ * @tx_ring: tx descriptor ring (for a specific queue) to setup + * + * Return 0 on success, negative on failure + **/ +- + static int e1000_setup_tx_resources(struct e1000_adapter *adapter, +- struct e1000_tx_ring *txdr) ++ struct e1000_tx_ring *tx_ring) + { + struct pci_dev *pdev = adapter->pdev; + int size; + +- size = sizeof(struct e1000_buffer) * txdr->count; +- txdr->buffer_info = vmalloc(size); +- if (!txdr->buffer_info) { ++ size = sizeof(struct e1000_buffer) * tx_ring->count; ++ tx_ring->buffer_info = vmalloc(size); ++ if (!tx_ring->buffer_info) { + DPRINTK(PROBE, ERR, + "Unable to allocate memory for the transmit descriptor ring\n"); + return -ENOMEM; + } +- memset(txdr->buffer_info, 0, size); ++ memset(tx_ring->buffer_info, 0, size); + + /* round up to nearest 4K */ + +- txdr->size = txdr->count * sizeof(struct e1000_tx_desc); +- txdr->size = ALIGN(txdr->size, 4096); +- +- txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma); +- if (!txdr->desc) { ++ tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); ++ tx_ring->size = ALIGN(tx_ring->size, 4096); ++ ++ tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, ++ &tx_ring->dma); ++ if (!tx_ring->desc) { + setup_tx_desc_die: +- vfree(txdr->buffer_info); ++ vfree(tx_ring->buffer_info); + DPRINTK(PROBE, ERR, + "Unable to allocate memory for the transmit descriptor ring\n"); + return -ENOMEM; + } + + /* Fix for errata 23, can't cross 64kB boundary */ +- if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) { +- void *olddesc = txdr->desc; +- dma_addr_t olddma = txdr->dma; +- DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes " +- "at %p\n", txdr->size, txdr->desc); ++ if (!e1000_check_64k_bound(adapter, tx_ring->desc, tx_ring->size)) { ++ void *olddesc = tx_ring->desc; ++ dma_addr_t olddma = tx_ring->dma; ++ DPRINTK(TX_ERR, ERR, "tx_ring align check failed: %u bytes " ++ "at %p\n", tx_ring->size, tx_ring->desc); + /* Try again, without freeing the previous */ +- txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma); ++ tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, ++ &tx_ring->dma); + /* Failed allocation, critical failure */ +- if (!txdr->desc) { +- pci_free_consistent(pdev, txdr->size, olddesc, olddma); ++ if (!tx_ring->desc) { ++ pci_free_consistent(pdev, tx_ring->size, olddesc, ++ olddma); + goto setup_tx_desc_die; + } + +- if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) { ++ if (!e1000_check_64k_bound(adapter, tx_ring->desc, ++ tx_ring->size)) { + /* give up */ +- pci_free_consistent(pdev, txdr->size, txdr->desc, +- txdr->dma); +- pci_free_consistent(pdev, txdr->size, olddesc, olddma); ++ pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, ++ tx_ring->dma); ++ pci_free_consistent(pdev, tx_ring->size, olddesc, ++ olddma); + DPRINTK(PROBE, ERR, + "Unable to allocate aligned memory " + "for the transmit descriptor ring\n"); +- vfree(txdr->buffer_info); ++ vfree(tx_ring->buffer_info); + return -ENOMEM; + } else { + /* Free old allocation, new allocation was successful */ +- pci_free_consistent(pdev, txdr->size, olddesc, olddma); +- } +- } +- memset(txdr->desc, 0, txdr->size); +- +- txdr->next_to_use = 0; +- txdr->next_to_clean = 0; +- spin_lock_init(&txdr->tx_lock); ++ pci_free_consistent(pdev, tx_ring->size, olddesc, ++ olddma); ++ } ++ } ++ memset(tx_ring->desc, 0, tx_ring->size); ++ ++ tx_ring->next_to_use = 0; ++ tx_ring->next_to_clean = 0; ++ spin_lock_init(&tx_ring->tx_lock); + + return 0; + } + + /** + * e1000_setup_all_tx_resources - wrapper to allocate Tx resources +- * (Descriptors) for all queues +- * @adapter: board private structure +- * +- * Return 0 on success, negative on failure +- **/ +- ++ * @adapter: board private structure ++ * ++ * this allocates tx resources, return 0 on success, negative ++ * on failure ++ **/ + int e1000_setup_all_tx_resources(struct e1000_adapter *adapter) + { +- int i, err = 0; +- +- for (i = 0; i < adapter->num_tx_queues; i++) { +- err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]); +- if (err) { +- DPRINTK(PROBE, ERR, +- "Allocation for Tx Queue %u failed\n", i); +- for (i-- ; i >= 0; i--) +- e1000_free_tx_resources(adapter, +- &adapter->tx_ring[i]); +- break; +- } +- } ++ int err = 0; ++ ++ err = e1000_setup_tx_resources(adapter, adapter->tx_ring); ++ if (err) ++ DPRINTK(PROBE, ERR, "Allocation for Tx Queue failed\n"); + + return err; + } +@@ -1686,51 +1413,39 @@ + * + * Configure the Tx unit of the MAC after a reset. + **/ +- + static void e1000_configure_tx(struct e1000_adapter *adapter) + { + u64 tdba; + struct e1000_hw *hw = &adapter->hw; +- u32 tdlen, tctl, tipg, tarc; ++ u32 tdlen, tctl, tipg; + u32 ipgr1, ipgr2; + + /* Setup the HW Tx Head and Tail descriptor pointers */ +- +- switch (adapter->num_tx_queues) { +- case 1: +- default: +- tdba = adapter->tx_ring[0].dma; +- tdlen = adapter->tx_ring[0].count * +- sizeof(struct e1000_tx_desc); +- ew32(TDLEN, tdlen); +- ew32(TDBAH, (tdba >> 32)); +- ew32(TDBAL, (tdba & 0x00000000ffffffffULL)); +- ew32(TDT, 0); +- ew32(TDH, 0); +- adapter->tx_ring[0].tdh = ((hw->mac_type >= e1000_82543) ? E1000_TDH : E1000_82542_TDH); +- adapter->tx_ring[0].tdt = ((hw->mac_type >= e1000_82543) ? E1000_TDT : E1000_82542_TDT); +- break; +- } ++ tdba = adapter->tx_ring->dma; ++ tdlen = adapter->tx_ring->count * sizeof(struct e1000_tx_desc); ++ E1000_WRITE_REG(hw, E1000_TDBAL(0), (tdba & 0x00000000ffffffffULL)); ++ E1000_WRITE_REG(hw, E1000_TDBAH(0), (tdba >> 32)); ++ E1000_WRITE_REG(hw, E1000_TDLEN(0), tdlen); ++ E1000_WRITE_REG(hw, E1000_TDH(0), 0); ++ E1000_WRITE_REG(hw, E1000_TDT(0), 0); ++ adapter->tx_ring->tdh = E1000_REGISTER(hw, E1000_TDH(0)); ++ adapter->tx_ring->tdt = E1000_REGISTER(hw, E1000_TDT(0)); ++ + + /* Set the default values for the Tx Inter Packet Gap timer */ +- if (hw->mac_type <= e1000_82547_rev_2 && +- (hw->media_type == e1000_media_type_fiber || +- hw->media_type == e1000_media_type_internal_serdes)) ++ if (adapter->hw.mac.type <= e1000_82547_rev_2 && ++ (hw->phy.media_type == e1000_media_type_fiber || ++ hw->phy.media_type == e1000_media_type_internal_serdes)) + tipg = DEFAULT_82543_TIPG_IPGT_FIBER; + else + tipg = DEFAULT_82543_TIPG_IPGT_COPPER; + +- switch (hw->mac_type) { +- case e1000_82542_rev2_0: +- case e1000_82542_rev2_1: ++ switch (hw->mac.type) { ++ case e1000_82542: + tipg = DEFAULT_82542_TIPG_IPGT; + ipgr1 = DEFAULT_82542_TIPG_IPGR1; + ipgr2 = DEFAULT_82542_TIPG_IPGR2; + break; +- case e1000_80003es2lan: +- ipgr1 = DEFAULT_82543_TIPG_IPGR1; +- ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; +- break; + default: + ipgr1 = DEFAULT_82543_TIPG_IPGR1; + ipgr2 = DEFAULT_82543_TIPG_IPGR2; +@@ -1738,36 +1453,21 @@ + } + tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; + tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; +- ew32(TIPG, tipg); ++ E1000_WRITE_REG(hw, E1000_TIPG, tipg); + + /* Set the Tx Interrupt Delay register */ + +- ew32(TIDV, adapter->tx_int_delay); +- if (hw->mac_type >= e1000_82540) +- ew32(TADV, adapter->tx_abs_int_delay); ++ E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay); ++ if (adapter->flags & E1000_FLAG_HAS_INTR_MODERATION) ++ E1000_WRITE_REG(hw, E1000_TADV, adapter->tx_abs_int_delay); + + /* Program the Transmit Control Register */ + +- tctl = er32(TCTL); ++ tctl = E1000_READ_REG(hw, E1000_TCTL); + tctl &= ~E1000_TCTL_CT; + tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | + (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); + +- if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { +- tarc = er32(TARC0); +- /* set the speed mode bit, we'll clear it if we're not at +- * gigabit link later */ +- tarc |= (1 << 21); +- ew32(TARC0, tarc); +- } else if (hw->mac_type == e1000_80003es2lan) { +- tarc = er32(TARC0); +- tarc |= 1; +- ew32(TARC0, tarc); +- tarc = er32(TARC1); +- tarc |= 1; +- ew32(TARC1, tarc); +- } +- + e1000_config_collision_dist(hw); + + /* Setup Transmit Descriptor Settings for eop descriptor */ +@@ -1777,177 +1477,150 @@ + if (adapter->tx_int_delay) + adapter->txd_cmd |= E1000_TXD_CMD_IDE; + +- if (hw->mac_type < e1000_82543) ++ if (hw->mac.type < e1000_82543) + adapter->txd_cmd |= E1000_TXD_CMD_RPS; + else + adapter->txd_cmd |= E1000_TXD_CMD_RS; + + /* Cache if we're 82544 running in PCI-X because we'll + * need this to apply a workaround later in the send path. */ +- if (hw->mac_type == e1000_82544 && +- hw->bus_type == e1000_bus_type_pcix) ++ if (hw->mac.type == e1000_82544 && ++ hw->bus.type == e1000_bus_type_pcix) + adapter->pcix_82544 = 1; + +- ew32(TCTL, tctl); ++ E1000_WRITE_REG(hw, E1000_TCTL, tctl); + + } + + /** + * e1000_setup_rx_resources - allocate Rx resources (Descriptors) + * @adapter: board private structure +- * @rxdr: rx descriptor ring (for a specific queue) to setup ++ * @rx_ring: rx descriptor ring (for a specific queue) to setup + * + * Returns 0 on success, negative on failure + **/ +- + static int e1000_setup_rx_resources(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rxdr) +-{ +- struct e1000_hw *hw = &adapter->hw; ++ struct e1000_rx_ring *rx_ring) ++{ + struct pci_dev *pdev = adapter->pdev; + int size, desc_len; + +- size = sizeof(struct e1000_buffer) * rxdr->count; +- rxdr->buffer_info = vmalloc(size); +- if (!rxdr->buffer_info) { ++ size = sizeof(struct e1000_rx_buffer) * rx_ring->count; ++ rx_ring->buffer_info = vmalloc(size); ++ if (!rx_ring->buffer_info) { + DPRINTK(PROBE, ERR, + "Unable to allocate memory for the receive descriptor ring\n"); + return -ENOMEM; + } +- memset(rxdr->buffer_info, 0, size); +- +- rxdr->ps_page = kcalloc(rxdr->count, sizeof(struct e1000_ps_page), +- GFP_KERNEL); +- if (!rxdr->ps_page) { +- vfree(rxdr->buffer_info); +- DPRINTK(PROBE, ERR, +- "Unable to allocate memory for the receive descriptor ring\n"); +- return -ENOMEM; +- } +- +- rxdr->ps_page_dma = kcalloc(rxdr->count, +- sizeof(struct e1000_ps_page_dma), +- GFP_KERNEL); +- if (!rxdr->ps_page_dma) { +- vfree(rxdr->buffer_info); +- kfree(rxdr->ps_page); +- DPRINTK(PROBE, ERR, +- "Unable to allocate memory for the receive descriptor ring\n"); +- return -ENOMEM; +- } +- +- if (hw->mac_type <= e1000_82547_rev_2) +- desc_len = sizeof(struct e1000_rx_desc); +- else +- desc_len = sizeof(union e1000_rx_desc_packet_split); ++ memset(rx_ring->buffer_info, 0, size); ++ ++ desc_len = sizeof(struct e1000_rx_desc); + + /* Round up to nearest 4K */ + +- rxdr->size = rxdr->count * desc_len; +- rxdr->size = ALIGN(rxdr->size, 4096); +- +- rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma); +- +- if (!rxdr->desc) { ++ rx_ring->size = rx_ring->count * desc_len; ++ rx_ring->size = ALIGN(rx_ring->size, 4096); ++ ++ rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, ++ &rx_ring->dma); ++ ++ if (!rx_ring->desc) { + DPRINTK(PROBE, ERR, + "Unable to allocate memory for the receive descriptor ring\n"); + setup_rx_desc_die: +- vfree(rxdr->buffer_info); +- kfree(rxdr->ps_page); +- kfree(rxdr->ps_page_dma); ++ vfree(rx_ring->buffer_info); + return -ENOMEM; + } + + /* Fix for errata 23, can't cross 64kB boundary */ +- if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) { +- void *olddesc = rxdr->desc; +- dma_addr_t olddma = rxdr->dma; +- DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes " +- "at %p\n", rxdr->size, rxdr->desc); ++ if (!e1000_check_64k_bound(adapter, rx_ring->desc, rx_ring->size)) { ++ void *olddesc = rx_ring->desc; ++ dma_addr_t olddma = rx_ring->dma; ++ DPRINTK(RX_ERR, ERR, "rx_ring align check failed: %u bytes " ++ "at %p\n", rx_ring->size, rx_ring->desc); + /* Try again, without freeing the previous */ +- rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma); ++ rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, ++ &rx_ring->dma); + /* Failed allocation, critical failure */ +- if (!rxdr->desc) { +- pci_free_consistent(pdev, rxdr->size, olddesc, olddma); ++ if (!rx_ring->desc) { ++ pci_free_consistent(pdev, rx_ring->size, olddesc, ++ olddma); + DPRINTK(PROBE, ERR, + "Unable to allocate memory " + "for the receive descriptor ring\n"); + goto setup_rx_desc_die; + } + +- if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) { ++ if (!e1000_check_64k_bound(adapter, rx_ring->desc, ++ rx_ring->size)) { + /* give up */ +- pci_free_consistent(pdev, rxdr->size, rxdr->desc, +- rxdr->dma); +- pci_free_consistent(pdev, rxdr->size, olddesc, olddma); ++ pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, ++ rx_ring->dma); ++ pci_free_consistent(pdev, rx_ring->size, olddesc, ++ olddma); + DPRINTK(PROBE, ERR, + "Unable to allocate aligned memory " + "for the receive descriptor ring\n"); + goto setup_rx_desc_die; + } else { + /* Free old allocation, new allocation was successful */ +- pci_free_consistent(pdev, rxdr->size, olddesc, olddma); +- } +- } +- memset(rxdr->desc, 0, rxdr->size); +- +- rxdr->next_to_clean = 0; +- rxdr->next_to_use = 0; ++ pci_free_consistent(pdev, rx_ring->size, olddesc, ++ olddma); ++ } ++ } ++ memset(rx_ring->desc, 0, rx_ring->size); ++ ++ /* set up ring defaults */ ++ rx_ring->next_to_clean = 0; ++ rx_ring->next_to_use = 0; ++ rx_ring->rx_skb_top = NULL; ++ rx_ring->adapter = adapter; + + return 0; + } + + /** + * e1000_setup_all_rx_resources - wrapper to allocate Rx resources +- * (Descriptors) for all queues +- * @adapter: board private structure +- * +- * Return 0 on success, negative on failure +- **/ +- ++ * @adapter: board private structure ++ * ++ * this allocates rx resources, return 0 on success, negative on failure ++ **/ + int e1000_setup_all_rx_resources(struct e1000_adapter *adapter) + { +- int i, err = 0; +- +- for (i = 0; i < adapter->num_rx_queues; i++) { +- err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]); +- if (err) { +- DPRINTK(PROBE, ERR, +- "Allocation for Rx Queue %u failed\n", i); +- for (i-- ; i >= 0; i--) +- e1000_free_rx_resources(adapter, +- &adapter->rx_ring[i]); +- break; +- } +- } +- +- return err; +-} +- ++ int err = 0; ++ ++ err = e1000_setup_rx_resources(adapter, adapter->rx_ring); ++ if (err) ++ DPRINTK(PROBE, ERR, "Allocation for Rx Queue failed\n"); ++ ++ return err; ++} ++ ++#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ ++ (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) + /** + * e1000_setup_rctl - configure the receive control registers + * @adapter: Board private structure + **/ +-#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ +- (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) + static void e1000_setup_rctl(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- u32 rctl, rfctl; +- u32 psrctl = 0; +-#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT +- u32 pages = 0; +-#endif +- +- rctl = er32(RCTL); ++ u32 rctl; ++ ++ rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); + + rctl &= ~(3 << E1000_RCTL_MO_SHIFT); + + rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | + E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | +- (hw->mc_filter_type << E1000_RCTL_MO_SHIFT); +- +- if (hw->tbi_compatibility_on == 1) ++ (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); ++ ++ /* disable the stripping of CRC because it breaks ++ * BMC firmware connected over SMBUS ++ if (adapter->hw.mac.type > e1000_82543) ++ rctl |= E1000_RCTL_SECRC; ++ */ ++ ++ if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) + rctl |= E1000_RCTL_SBP; + else + rctl &= ~E1000_RCTL_SBP; +@@ -1989,56 +1662,7 @@ + break; + } + +-#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT +- /* 82571 and greater support packet-split where the protocol +- * header is placed in skb->data and the packet data is +- * placed in pages hanging off of skb_shinfo(skb)->nr_frags. +- * In the case of a non-split, skb->data is linearly filled, +- * followed by the page buffers. Therefore, skb->data is +- * sized to hold the largest protocol header. +- */ +- /* allocations using alloc_page take too long for regular MTU +- * so only enable packet split for jumbo frames */ +- pages = PAGE_USE_COUNT(adapter->netdev->mtu); +- if ((hw->mac_type >= e1000_82571) && (pages <= 3) && +- PAGE_SIZE <= 16384 && (rctl & E1000_RCTL_LPE)) +- adapter->rx_ps_pages = pages; +- else +- adapter->rx_ps_pages = 0; +-#endif +- if (adapter->rx_ps_pages) { +- /* Configure extra packet-split registers */ +- rfctl = er32(RFCTL); +- rfctl |= E1000_RFCTL_EXTEN; +- /* disable packet split support for IPv6 extension headers, +- * because some malformed IPv6 headers can hang the RX */ +- rfctl |= (E1000_RFCTL_IPV6_EX_DIS | +- E1000_RFCTL_NEW_IPV6_EXT_DIS); +- +- ew32(RFCTL, rfctl); +- +- rctl |= E1000_RCTL_DTYP_PS; +- +- psrctl |= adapter->rx_ps_bsize0 >> +- E1000_PSRCTL_BSIZE0_SHIFT; +- +- switch (adapter->rx_ps_pages) { +- case 3: +- psrctl |= PAGE_SIZE << +- E1000_PSRCTL_BSIZE3_SHIFT; +- case 2: +- psrctl |= PAGE_SIZE << +- E1000_PSRCTL_BSIZE2_SHIFT; +- case 1: +- psrctl |= PAGE_SIZE >> +- E1000_PSRCTL_BSIZE1_SHIFT; +- break; +- } +- +- ew32(PSRCTL, psrctl); +- } +- +- ew32(RCTL, rctl); ++ E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); + } + + /** +@@ -2047,93 +1671,67 @@ + * + * Configure the Rx unit of the MAC after a reset. + **/ +- + static void e1000_configure_rx(struct e1000_adapter *adapter) + { + u64 rdba; + struct e1000_hw *hw = &adapter->hw; +- u32 rdlen, rctl, rxcsum, ctrl_ext; +- +- if (adapter->rx_ps_pages) { +- /* this is a 32 byte descriptor */ +- rdlen = adapter->rx_ring[0].count * +- sizeof(union e1000_rx_desc_packet_split); +- adapter->clean_rx = e1000_clean_rx_irq_ps; +- adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; +- } else { +- rdlen = adapter->rx_ring[0].count * ++ u32 rdlen, rctl, rxcsum; ++#ifdef CONFIG_E1000_NAPI ++ if (adapter->netdev->mtu > MAXIMUM_ETHERNET_VLAN_SIZE) { ++ rdlen = adapter->rx_ring->count * ++ sizeof(struct e1000_rx_desc); ++ adapter->clean_rx = e1000_clean_jumbo_rx_irq; ++ adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; ++ } else ++#endif /* CONFIG_E1000_NAPI */ ++ { ++ rdlen = adapter->rx_ring->count * + sizeof(struct e1000_rx_desc); + adapter->clean_rx = e1000_clean_rx_irq; + adapter->alloc_rx_buf = e1000_alloc_rx_buffers; + } + + /* disable receives while setting up the descriptors */ +- rctl = er32(RCTL); +- ew32(RCTL, rctl & ~E1000_RCTL_EN); ++ rctl = E1000_READ_REG(hw, E1000_RCTL); ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); ++ /* do not flush or delay here, causes some strange problem ++ * on SERDES connected SFP modules */ + + /* set the Receive Delay Timer Register */ +- ew32(RDTR, adapter->rx_int_delay); +- +- if (hw->mac_type >= e1000_82540) { +- ew32(RADV, adapter->rx_abs_int_delay); ++ E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay); ++ ++ if (adapter->flags & E1000_FLAG_HAS_INTR_MODERATION) { ++ E1000_WRITE_REG(hw, E1000_RADV, adapter->rx_abs_int_delay); + if (adapter->itr_setting != 0) +- ew32(ITR, 1000000000 / (adapter->itr * 256)); +- } +- +- if (hw->mac_type >= e1000_82571) { +- ctrl_ext = er32(CTRL_EXT); +- /* Reset delay timers after every interrupt */ +- ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; +- /* Auto-Mask interrupts upon ICR access */ +- ctrl_ext |= E1000_CTRL_EXT_IAME; +- ew32(IAM, 0xffffffff); +- ew32(CTRL_EXT, ctrl_ext); +- E1000_WRITE_FLUSH(); ++ E1000_WRITE_REG(hw, E1000_ITR, ++ 1000000000 / (adapter->itr * 256)); + } + + /* Setup the HW Rx Head and Tail Descriptor Pointers and + * the Base and Length of the Rx Descriptor Ring */ +- switch (adapter->num_rx_queues) { +- case 1: +- default: +- rdba = adapter->rx_ring[0].dma; +- ew32(RDLEN, rdlen); +- ew32(RDBAH, (rdba >> 32)); +- ew32(RDBAL, (rdba & 0x00000000ffffffffULL)); +- ew32(RDT, 0); +- ew32(RDH, 0); +- adapter->rx_ring[0].rdh = ((hw->mac_type >= e1000_82543) ? E1000_RDH : E1000_82542_RDH); +- adapter->rx_ring[0].rdt = ((hw->mac_type >= e1000_82543) ? E1000_RDT : E1000_82542_RDT); +- break; +- } +- +- /* Enable 82543 Receive Checksum Offload for TCP and UDP */ +- if (hw->mac_type >= e1000_82543) { +- rxcsum = er32(RXCSUM); +- if (adapter->rx_csum) { ++ rdba = adapter->rx_ring->dma; ++ E1000_WRITE_REG(hw, E1000_RDBAL(0), (rdba & 0x00000000ffffffffULL)); ++ E1000_WRITE_REG(hw, E1000_RDBAH(0), (rdba >> 32)); ++ E1000_WRITE_REG(hw, E1000_RDLEN(0), rdlen); ++ E1000_WRITE_REG(hw, E1000_RDH(0), 0); ++ E1000_WRITE_REG(hw, E1000_RDT(0), 0); ++ adapter->rx_ring->rdh = E1000_REGISTER(hw, E1000_RDH(0)); ++ adapter->rx_ring->rdt = E1000_REGISTER(hw, E1000_RDT(0)); ++ ++ if (hw->mac.type >= e1000_82543) { ++ /* Enable 82543 Receive Checksum Offload for TCP and UDP */ ++ rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); ++ if (adapter->rx_csum == TRUE) { + rxcsum |= E1000_RXCSUM_TUOFL; +- +- /* Enable 82571 IPv4 payload checksum for UDP fragments +- * Must be used in conjunction with packet-split. */ +- if ((hw->mac_type >= e1000_82571) && +- (adapter->rx_ps_pages)) { +- rxcsum |= E1000_RXCSUM_IPPCSE; +- } + } else { + rxcsum &= ~E1000_RXCSUM_TUOFL; + /* don't need to clear IPPCSE as it defaults to 0 */ + } +- ew32(RXCSUM, rxcsum); +- } +- +- /* enable early receives on 82573, only takes effect if using > 2048 +- * byte total frame size. for example only for jumbo frames */ +-#define E1000_ERT_2048 0x100 +- if (hw->mac_type == e1000_82573) +- ew32(ERT, E1000_ERT_2048); ++ E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); ++ } + + /* Enable Receives */ +- ew32(RCTL, rctl); ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); + } + + /** +@@ -2143,9 +1741,8 @@ + * + * Free all transmit software resources + **/ +- + static void e1000_free_tx_resources(struct e1000_adapter *adapter, +- struct e1000_tx_ring *tx_ring) ++ struct e1000_tx_ring *tx_ring) + { + struct pci_dev *pdev = adapter->pdev; + +@@ -2165,17 +1762,13 @@ + * + * Free all transmit software resources + **/ +- + void e1000_free_all_tx_resources(struct e1000_adapter *adapter) + { +- int i; +- +- for (i = 0; i < adapter->num_tx_queues; i++) +- e1000_free_tx_resources(adapter, &adapter->tx_ring[i]); ++ e1000_free_tx_resources(adapter, adapter->tx_ring); + } + + static void e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter, +- struct e1000_buffer *buffer_info) ++ struct e1000_buffer *buffer_info) + { + if (buffer_info->dma) { + pci_unmap_page(adapter->pdev, +@@ -2196,11 +1789,9 @@ + * @adapter: board private structure + * @tx_ring: ring to be cleaned + **/ +- + static void e1000_clean_tx_ring(struct e1000_adapter *adapter, +- struct e1000_tx_ring *tx_ring) +-{ +- struct e1000_hw *hw = &adapter->hw; ++ struct e1000_tx_ring *tx_ring) ++{ + struct e1000_buffer *buffer_info; + unsigned long size; + unsigned int i; +@@ -2223,21 +1814,17 @@ + tx_ring->next_to_clean = 0; + tx_ring->last_tx_tso = 0; + +- writel(0, hw->hw_addr + tx_ring->tdh); +- writel(0, hw->hw_addr + tx_ring->tdt); ++ writel(0, adapter->hw.hw_addr + tx_ring->tdh); ++ writel(0, adapter->hw.hw_addr + tx_ring->tdt); + } + + /** + * e1000_clean_all_tx_rings - Free Tx Buffers for all queues + * @adapter: board private structure + **/ +- + static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter) + { +- int i; +- +- for (i = 0; i < adapter->num_tx_queues; i++) +- e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]); ++ e1000_clean_tx_ring(adapter, adapter->tx_ring); + } + + /** +@@ -2247,9 +1834,8 @@ + * + * Free all receive software resources + **/ +- + static void e1000_free_rx_resources(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rx_ring) ++ struct e1000_rx_ring *rx_ring) + { + struct pci_dev *pdev = adapter->pdev; + +@@ -2257,10 +1843,6 @@ + + vfree(rx_ring->buffer_info); + rx_ring->buffer_info = NULL; +- kfree(rx_ring->ps_page); +- rx_ring->ps_page = NULL; +- kfree(rx_ring->ps_page_dma); +- rx_ring->ps_page_dma = NULL; + + pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); + +@@ -2273,13 +1855,9 @@ + * + * Free all receive software resources + **/ +- + void e1000_free_all_rx_resources(struct e1000_adapter *adapter) + { +- int i; +- +- for (i = 0; i < adapter->num_rx_queues; i++) +- e1000_free_rx_resources(adapter, &adapter->rx_ring[i]); ++ e1000_free_rx_resources(adapter, adapter->rx_ring); + } + + /** +@@ -2287,49 +1865,51 @@ + * @adapter: board private structure + * @rx_ring: ring to free buffers from + **/ +- + static void e1000_clean_rx_ring(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rx_ring) +-{ +- struct e1000_hw *hw = &adapter->hw; +- struct e1000_buffer *buffer_info; +- struct e1000_ps_page *ps_page; +- struct e1000_ps_page_dma *ps_page_dma; ++ struct e1000_rx_ring *rx_ring) ++{ ++ struct e1000_rx_buffer *buffer_info; + struct pci_dev *pdev = adapter->pdev; + unsigned long size; +- unsigned int i, j; ++ unsigned int i; + + /* Free all the Rx ring sk_buffs */ + for (i = 0; i < rx_ring->count; i++) { + buffer_info = &rx_ring->buffer_info[i]; ++ if (buffer_info->dma && ++ adapter->clean_rx == e1000_clean_rx_irq) { ++ pci_unmap_single(pdev, buffer_info->dma, ++ adapter->rx_buffer_len, ++ PCI_DMA_FROMDEVICE); ++#ifdef CONFIG_E1000_NAPI ++ } else if (buffer_info->dma && ++ adapter->clean_rx == e1000_clean_jumbo_rx_irq) { ++ pci_unmap_page(pdev, buffer_info->dma, PAGE_SIZE, ++ PCI_DMA_FROMDEVICE); ++#endif /* CONFIG_E1000_NAPI */ ++ } ++ ++ buffer_info->dma = 0; ++ if (buffer_info->page) { ++ put_page(buffer_info->page); ++ buffer_info->page = NULL; ++ } + if (buffer_info->skb) { +- pci_unmap_single(pdev, +- buffer_info->dma, +- buffer_info->length, +- PCI_DMA_FROMDEVICE); +- + dev_kfree_skb(buffer_info->skb); + buffer_info->skb = NULL; + } +- ps_page = &rx_ring->ps_page[i]; +- ps_page_dma = &rx_ring->ps_page_dma[i]; +- for (j = 0; j < adapter->rx_ps_pages; j++) { +- if (!ps_page->ps_page[j]) break; +- pci_unmap_page(pdev, +- ps_page_dma->ps_page_dma[j], +- PAGE_SIZE, PCI_DMA_FROMDEVICE); +- ps_page_dma->ps_page_dma[j] = 0; +- put_page(ps_page->ps_page[j]); +- ps_page->ps_page[j] = NULL; +- } +- } +- +- size = sizeof(struct e1000_buffer) * rx_ring->count; ++ } ++ ++#ifdef CONFIG_E1000_NAPI ++ /* there also may be some cached data from a chained receive */ ++ if (rx_ring->rx_skb_top) { ++ dev_kfree_skb(rx_ring->rx_skb_top); ++ rx_ring->rx_skb_top = NULL; ++ } ++#endif ++ ++ size = sizeof(struct e1000_rx_buffer) * rx_ring->count; + memset(rx_ring->buffer_info, 0, size); +- size = sizeof(struct e1000_ps_page) * rx_ring->count; +- memset(rx_ring->ps_page, 0, size); +- size = sizeof(struct e1000_ps_page_dma) * rx_ring->count; +- memset(rx_ring->ps_page_dma, 0, size); + + /* Zero out the descriptor ring */ + +@@ -2338,21 +1918,17 @@ + rx_ring->next_to_clean = 0; + rx_ring->next_to_use = 0; + +- writel(0, hw->hw_addr + rx_ring->rdh); +- writel(0, hw->hw_addr + rx_ring->rdt); ++ writel(0, adapter->hw.hw_addr + rx_ring->rdh); ++ writel(0, adapter->hw.hw_addr + rx_ring->rdt); + } + + /** + * e1000_clean_all_rx_rings - Free Rx Buffers for all queues + * @adapter: board private structure + **/ +- + static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter) + { +- int i; +- +- for (i = 0; i < adapter->num_rx_queues; i++) +- e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]); ++ e1000_clean_rx_ring(adapter, adapter->rx_ring); + } + + /* The 82542 2.0 (revision 2) needs to have the receive unit in reset +@@ -2360,16 +1936,20 @@ + */ + static void e1000_enter_82542_rst(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; + struct net_device *netdev = adapter->netdev; + u32 rctl; + +- e1000_pci_clear_mwi(hw); +- +- rctl = er32(RCTL); ++ if (adapter->hw.mac.type != e1000_82542) ++ return; ++ if (adapter->hw.revision_id != E1000_REVISION_2) ++ return; ++ ++ e1000_pci_clear_mwi(&adapter->hw); ++ ++ rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); + rctl |= E1000_RCTL_RST; +- ew32(RCTL, rctl); +- E1000_WRITE_FLUSH(); ++ E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); ++ E1000_WRITE_FLUSH(&adapter->hw); + mdelay(5); + + if (netif_running(netdev)) +@@ -2378,22 +1958,26 @@ + + static void e1000_leave_82542_rst(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; + struct net_device *netdev = adapter->netdev; + u32 rctl; + +- rctl = er32(RCTL); ++ if (adapter->hw.mac.type != e1000_82542) ++ return; ++ if (adapter->hw.revision_id != E1000_REVISION_2) ++ return; ++ ++ rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); + rctl &= ~E1000_RCTL_RST; +- ew32(RCTL, rctl); +- E1000_WRITE_FLUSH(); ++ E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); ++ E1000_WRITE_FLUSH(&adapter->hw); + mdelay(5); + +- if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) +- e1000_pci_set_mwi(hw); ++ if (adapter->hw.bus.pci_cmd_word & PCI_COMMAND_INVALIDATE) ++ e1000_pci_set_mwi(&adapter->hw); + + if (netif_running(netdev)) { + /* No need to loop, because 82542 supports only 1 queue */ +- struct e1000_rx_ring *ring = &adapter->rx_ring[0]; ++ struct e1000_rx_ring *ring = adapter->rx_ring; + e1000_configure_rx(adapter); + adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring)); + } +@@ -2406,11 +1990,9 @@ + * + * Returns 0 on success, negative on failure + **/ +- + static int e1000_set_mac(struct net_device *netdev, void *p) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; + struct sockaddr *addr = p; + + if (!is_valid_ether_addr(addr->sa_data)) +@@ -2418,184 +2000,175 @@ + + /* 82542 2.0 needs to be in reset to write receive address registers */ + +- if (hw->mac_type == e1000_82542_rev2_0) ++ if (adapter->hw.mac.type == e1000_82542) + e1000_enter_82542_rst(adapter); + + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); +- memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len); +- +- e1000_rar_set(hw, hw->mac_addr, 0); +- +- /* With 82571 controllers, LAA may be overwritten (with the default) +- * due to controller reset from the other port. */ +- if (hw->mac_type == e1000_82571) { +- /* activate the work around */ +- hw->laa_is_present = 1; +- +- /* Hold a copy of the LAA in RAR[14] This is done so that +- * between the time RAR[0] gets clobbered and the time it +- * gets fixed (in e1000_watchdog), the actual LAA is in one +- * of the RARs and no incoming packets directed to this port +- * are dropped. Eventaully the LAA will be in RAR[0] and +- * RAR[14] */ +- e1000_rar_set(hw, hw->mac_addr, +- E1000_RAR_ENTRIES - 1); +- } +- +- if (hw->mac_type == e1000_82542_rev2_0) ++ memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); ++ ++ e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); ++ ++ if (adapter->hw.mac.type == e1000_82542) + e1000_leave_82542_rst(adapter); + + return 0; + } + + /** +- * e1000_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set +- * @netdev: network interface device structure +- * +- * The set_rx_mode entry point is called whenever the unicast or multicast +- * address lists or the network interface flags are updated. This routine is +- * responsible for configuring the hardware for proper unicast, multicast, ++ * e1000_set_multi - Multicast and Promiscuous mode set ++ * @netdev: network interface device structure ++ * ++ * The set_multi entry point is called whenever the multicast address ++ * list or the network interface flags are updated. This routine is ++ * responsible for configuring the hardware for proper multicast, + * promiscuous mode, and all-multi behavior. + **/ +- +-static void e1000_set_rx_mode(struct net_device *netdev) +-{ +- struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; +- struct dev_addr_list *uc_ptr; +- struct dev_addr_list *mc_ptr; ++static void e1000_set_multi(struct net_device *netdev) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ struct dev_mc_list *mc_ptr; ++ u8 *mta_list; + u32 rctl; +- u32 hash_value; +- int i, rar_entries = E1000_RAR_ENTRIES; +- int mta_reg_count = (hw->mac_type == e1000_ich8lan) ? +- E1000_NUM_MTA_REGISTERS_ICH8LAN : +- E1000_NUM_MTA_REGISTERS; +- +- if (hw->mac_type == e1000_ich8lan) +- rar_entries = E1000_RAR_ENTRIES_ICH8LAN; +- +- /* reserve RAR[14] for LAA over-write work-around */ +- if (hw->mac_type == e1000_82571) +- rar_entries--; ++ int i; + + /* Check for Promiscuous and All Multicast modes */ + +- rctl = er32(RCTL); ++ rctl = E1000_READ_REG(hw, E1000_RCTL); + + if (netdev->flags & IFF_PROMISC) { + rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); ++ ++ /* disable VLAN filters */ + rctl &= ~E1000_RCTL_VFE; + } else { + if (netdev->flags & IFF_ALLMULTI) { + rctl |= E1000_RCTL_MPE; +- } else { +- rctl &= ~E1000_RCTL_MPE; +- } +- if (adapter->hw.mac_type != e1000_ich8lan) +- rctl |= E1000_RCTL_VFE; +- } +- +- uc_ptr = NULL; +- if (netdev->uc_count > rar_entries - 1) { +- rctl |= E1000_RCTL_UPE; +- } else if (!(netdev->flags & IFF_PROMISC)) { +- rctl &= ~E1000_RCTL_UPE; +- uc_ptr = netdev->uc_list; +- } +- +- ew32(RCTL, rctl); ++ rctl &= ~E1000_RCTL_UPE; ++ } else { ++ rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); ++ } ++ ++ /* enable VLAN filters */ ++ rctl |= E1000_RCTL_VFE; ++ } ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); + + /* 82542 2.0 needs to be in reset to write receive address registers */ + +- if (hw->mac_type == e1000_82542_rev2_0) ++ if (hw->mac.type == e1000_82542) + e1000_enter_82542_rst(adapter); + +- /* load the first 14 addresses into the exact filters 1-14. Unicast +- * addresses take precedence to avoid disabling unicast filtering +- * when possible. +- * +- * RAR 0 is used for the station MAC adddress +- * if there are not 14 addresses, go ahead and clear the filters +- * -- with 82571 controllers only 0-13 entries are filled here +- */ ++ mta_list = kmalloc(netdev->mc_count * 6, GFP_ATOMIC); ++ if (!mta_list) ++ return; ++ ++ /* The shared function expects a packed array of only addresses. */ + mc_ptr = netdev->mc_list; + +- for (i = 1; i < rar_entries; i++) { +- if (uc_ptr) { +- e1000_rar_set(hw, uc_ptr->da_addr, i); +- uc_ptr = uc_ptr->next; +- } else if (mc_ptr) { +- e1000_rar_set(hw, mc_ptr->da_addr, i); +- mc_ptr = mc_ptr->next; +- } else { +- E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0); +- E1000_WRITE_FLUSH(); +- E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0); +- E1000_WRITE_FLUSH(); +- } +- } +- WARN_ON(uc_ptr != NULL); +- +- /* clear the old settings from the multicast hash table */ +- +- for (i = 0; i < mta_reg_count; i++) { +- E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); +- E1000_WRITE_FLUSH(); +- } +- +- /* load any remaining addresses into the hash table */ +- +- for (; mc_ptr; mc_ptr = mc_ptr->next) { +- hash_value = e1000_hash_mc_addr(hw, mc_ptr->da_addr); +- e1000_mta_set(hw, hash_value); +- } +- +- if (hw->mac_type == e1000_82542_rev2_0) ++ for (i = 0; i < netdev->mc_count; i++) { ++ if (!mc_ptr) ++ break; ++ memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); ++ mc_ptr = mc_ptr->next; ++ } ++ ++ e1000_update_mc_addr_list(hw, mta_list, i); ++ ++ kfree(mta_list); ++ ++ if (hw->mac.type == e1000_82542) + e1000_leave_82542_rst(adapter); + } + + /* Need to wait a few seconds after link up to get diagnostic information from + * the phy */ +- + static void e1000_update_phy_info(unsigned long data) + { +- struct e1000_adapter *adapter = (struct e1000_adapter *)data; +- struct e1000_hw *hw = &adapter->hw; +- e1000_phy_get_info(hw, &adapter->phy_info); ++ struct e1000_adapter *adapter = (struct e1000_adapter *) data; ++ e1000_get_phy_info(&adapter->hw); + } + + /** + * e1000_82547_tx_fifo_stall - Timer Call-back + * @data: pointer to adapter cast into an unsigned long + **/ +- + static void e1000_82547_tx_fifo_stall(unsigned long data) + { +- struct e1000_adapter *adapter = (struct e1000_adapter *)data; +- struct e1000_hw *hw = &adapter->hw; ++ struct e1000_adapter *adapter = (struct e1000_adapter *) data; + struct net_device *netdev = adapter->netdev; + u32 tctl; + + if (atomic_read(&adapter->tx_fifo_stall)) { +- if ((er32(TDT) == er32(TDH)) && +- (er32(TDFT) == er32(TDFH)) && +- (er32(TDFTS) == er32(TDFHS))) { +- tctl = er32(TCTL); +- ew32(TCTL, tctl & ~E1000_TCTL_EN); +- ew32(TDFT, adapter->tx_head_addr); +- ew32(TDFH, adapter->tx_head_addr); +- ew32(TDFTS, adapter->tx_head_addr); +- ew32(TDFHS, adapter->tx_head_addr); +- ew32(TCTL, tctl); +- E1000_WRITE_FLUSH(); ++ if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == ++ E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && ++ (E1000_READ_REG(&adapter->hw, E1000_TDFT) == ++ E1000_READ_REG(&adapter->hw, E1000_TDFH)) && ++ (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == ++ E1000_READ_REG(&adapter->hw, E1000_TDFHS))) { ++ tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); ++ E1000_WRITE_REG(&adapter->hw, E1000_TCTL, ++ tctl & ~E1000_TCTL_EN); ++ E1000_WRITE_REG(&adapter->hw, E1000_TDFT, ++ adapter->tx_head_addr); ++ E1000_WRITE_REG(&adapter->hw, E1000_TDFH, ++ adapter->tx_head_addr); ++ E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, ++ adapter->tx_head_addr); ++ E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, ++ adapter->tx_head_addr); ++ E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); ++ E1000_WRITE_FLUSH(&adapter->hw); + + adapter->tx_fifo_head = 0; + atomic_set(&adapter->tx_fifo_stall, 0); + netif_wake_queue(netdev); +- } else { ++ } else if (!test_bit(__E1000_DOWN, &adapter->state)) + mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1); +- } +- } ++ } ++} ++ ++static bool e1000_has_link(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ bool link_active = FALSE; ++ s32 ret_val = 0; ++ ++ /* get_link_status is set on LSC (link status) interrupt or ++ * rx sequence error interrupt. get_link_status will stay ++ * false until the e1000_check_for_link establishes link ++ * for copper adapters ONLY ++ */ ++ switch (hw->phy.media_type) { ++ case e1000_media_type_copper: ++ if (hw->mac.get_link_status) { ++ ret_val = e1000_check_for_link(hw); ++ link_active = !hw->mac.get_link_status; ++ } else { ++ link_active = TRUE; ++ } ++ break; ++ case e1000_media_type_fiber: ++ ret_val = e1000_check_for_link(hw); ++ link_active = !!(E1000_READ_REG(hw, E1000_STATUS) & ++ E1000_STATUS_LU); ++ break; ++ case e1000_media_type_internal_serdes: ++ ret_val = e1000_check_for_link(hw); ++ link_active = adapter->hw.mac.serdes_has_link; ++ break; ++ default: ++ case e1000_media_type_unknown: ++ break; ++ } ++ ++ if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && ++ (E1000_READ_REG(&adapter->hw, E1000_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { ++ DPRINTK(LINK, INFO, ++ "Gigabit has been disabled, downgrading speed\n"); ++ } ++ ++ return link_active; + } + + /** +@@ -2604,43 +2177,39 @@ + **/ + static void e1000_watchdog(unsigned long data) + { +- struct e1000_adapter *adapter = (struct e1000_adapter *)data; +- struct e1000_hw *hw = &adapter->hw; +- struct net_device *netdev = adapter->netdev; +- struct e1000_tx_ring *txdr = adapter->tx_ring; ++ struct e1000_adapter *adapter = (struct e1000_adapter *) data; ++ ++ /* Do the rest outside of interrupt context */ ++ schedule_work(&adapter->watchdog_task); ++} ++ ++static void e1000_watchdog_task(struct work_struct *work) ++{ ++ struct e1000_adapter *adapter = container_of(work, ++ struct e1000_adapter, watchdog_task); ++ struct net_device *netdev = adapter->netdev; ++ struct e1000_mac_info *mac = &adapter->hw.mac; ++ struct e1000_tx_ring *tx_ring; + u32 link, tctl; +- s32 ret_val; +- +- ret_val = e1000_check_for_link(hw); +- if ((ret_val == E1000_ERR_PHY) && +- (hw->phy_type == e1000_phy_igp_3) && +- (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { +- /* See e1000_kumeran_lock_loss_workaround() */ +- DPRINTK(LINK, INFO, +- "Gigabit has been disabled, downgrading speed\n"); +- } +- +- if (hw->mac_type == e1000_82573) { +- e1000_enable_tx_pkt_filtering(hw); +- if (adapter->mng_vlan_id != hw->mng_cookie.vlan_id) +- e1000_update_mng_vlan(adapter); +- } +- +- if ((hw->media_type == e1000_media_type_internal_serdes) && +- !(er32(TXCW) & E1000_TXCW_ANE)) +- link = !hw->serdes_link_down; +- else +- link = er32(STATUS) & E1000_STATUS_LU; ++ int tx_pending = 0; ++ ++ link = e1000_has_link(adapter); ++ if ((netif_carrier_ok(netdev)) && link) ++ goto link_up; + + if (link) { + if (!netif_carrier_ok(netdev)) { + u32 ctrl; +- bool txb2b = true; +- e1000_get_speed_and_duplex(hw, ++ bool txb2b = 1; ++#ifdef SIOCGMIIPHY ++ /* update snapshot of PHY registers on LSC */ ++ e1000_phy_read_status(adapter); ++#endif ++ e1000_get_speed_and_duplex(&adapter->hw, + &adapter->link_speed, + &adapter->link_duplex); + +- ctrl = er32(CTRL); ++ ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); + DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s, " + "Flow Control: %s\n", + adapter->link_speed, +@@ -2657,64 +2226,58 @@ + adapter->tx_timeout_factor = 1; + switch (adapter->link_speed) { + case SPEED_10: +- txb2b = false; ++ txb2b = 0; + netdev->tx_queue_len = 10; +- adapter->tx_timeout_factor = 8; ++ adapter->tx_timeout_factor = 16; + break; + case SPEED_100: +- txb2b = false; ++ txb2b = 0; + netdev->tx_queue_len = 100; + /* maybe add some timeout factor ? */ + break; + } + +- if ((hw->mac_type == e1000_82571 || +- hw->mac_type == e1000_82572) && +- !txb2b) { +- u32 tarc0; +- tarc0 = er32(TARC0); +- tarc0 &= ~(1 << 21); +- ew32(TARC0, tarc0); +- } +- ++#ifdef NETIF_F_TSO + /* disable TSO for pcie and 10/100 speeds, to avoid + * some hardware issues */ +- if (!adapter->tso_force && +- hw->bus_type == e1000_bus_type_pci_express){ ++ if (!(adapter->flags & E1000_FLAG_TSO_FORCE) && ++ adapter->hw.bus.type == e1000_bus_type_pci_express){ + switch (adapter->link_speed) { + case SPEED_10: + case SPEED_100: + DPRINTK(PROBE,INFO, + "10/100 speed: disabling TSO\n"); + netdev->features &= ~NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 + netdev->features &= ~NETIF_F_TSO6; ++#endif + break; + case SPEED_1000: + netdev->features |= NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 + netdev->features |= NETIF_F_TSO6; ++#endif + break; + default: + /* oops */ + break; + } + } ++#endif + + /* enable transmits in the hardware, need to do this + * after setting TARC0 */ +- tctl = er32(TCTL); ++ tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); + tctl |= E1000_TCTL_EN; +- ew32(TCTL, tctl); ++ E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); + + netif_carrier_on(netdev); + netif_wake_queue(netdev); +- mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ)); ++ ++ if (!test_bit(__E1000_DOWN, &adapter->state)) ++ mod_timer(&adapter->phy_info_timer, ++ round_jiffies(jiffies + 2 * HZ)); + adapter->smartspeed = 0; +- } else { +- /* make sure the receive unit is started */ +- if (hw->rx_needs_kicking) { +- u32 rctl = er32(RCTL); +- ew32(RCTL, rctl | E1000_RCTL_EN); +- } + } + } else { + if (netif_carrier_ok(netdev)) { +@@ -2723,37 +2286,35 @@ + DPRINTK(LINK, INFO, "NIC Link is Down\n"); + netif_carrier_off(netdev); + netif_stop_queue(netdev); +- mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ)); +- +- /* 80003ES2LAN workaround-- +- * For packet buffer work-around on link down event; +- * disable receives in the ISR and +- * reset device here in the watchdog +- */ +- if (hw->mac_type == e1000_80003es2lan) +- /* reset device */ +- schedule_work(&adapter->reset_task); ++ ++ if (!test_bit(__E1000_DOWN, &adapter->state)) ++ mod_timer(&adapter->phy_info_timer, ++ round_jiffies(jiffies + 2 * HZ)); + } + + e1000_smartspeed(adapter); + } + ++link_up: + e1000_update_stats(adapter); + +- hw->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; ++ mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; + adapter->tpt_old = adapter->stats.tpt; +- hw->collision_delta = adapter->stats.colc - adapter->colc_old; ++ mac->collision_delta = adapter->stats.colc - adapter->colc_old; + adapter->colc_old = adapter->stats.colc; + +- adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old; +- adapter->gorcl_old = adapter->stats.gorcl; +- adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old; +- adapter->gotcl_old = adapter->stats.gotcl; +- +- e1000_update_adaptive(hw); ++ adapter->gorc = adapter->stats.gorc - adapter->gorc_old; ++ adapter->gorc_old = adapter->stats.gorc; ++ adapter->gotc = adapter->stats.gotc - adapter->gotc_old; ++ adapter->gotc_old = adapter->stats.gotc; ++ ++ e1000_update_adaptive(&adapter->hw); + + if (!netif_carrier_ok(netdev)) { +- if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) { ++ tx_ring = adapter->tx_ring; ++ tx_pending |= (E1000_DESC_UNUSED(tx_ring) + ++ tx_ring->step < tx_ring->count); ++ if (tx_pending) { + /* We've lost link, so the controller stops DMA, + * but we've got queued Tx work that's never going + * to get done, so reset controller to flush Tx. +@@ -2764,18 +2325,15 @@ + } + + /* Cause software interrupt to ensure rx ring is cleaned */ +- ew32(ICS, E1000_ICS_RXDMT0); ++ E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_RXDMT0); + + /* Force detection of hung controller every watchdog period */ +- adapter->detect_tx_hung = true; +- +- /* With 82571 controllers, LAA may be overwritten due to controller +- * reset from the other port. Set the appropriate LAA in RAR[0] */ +- if (hw->mac_type == e1000_82571 && hw->laa_is_present) +- e1000_rar_set(hw, hw->mac_addr, 0); ++ adapter->detect_tx_hung = TRUE; + + /* Reset the timer */ +- mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ)); ++ if (!test_bit(__E1000_DOWN, &adapter->state)) ++ mod_timer(&adapter->watchdog_timer, ++ round_jiffies(jiffies + 2 * HZ)); + } + + enum latency_range { +@@ -2787,6 +2345,11 @@ + + /** + * e1000_update_itr - update the dynamic ITR value based on statistics ++ * @adapter: pointer to adapter ++ * @itr_setting: current adapter->itr ++ * @packets: the number of packets during this measurement interval ++ * @bytes: the number of bytes during this measurement interval ++ * + * Stores a new ITR value based on packets and byte + * counts during the last interrupt. The advantage of per interrupt + * computation is faster updates and more accurate ITR for the current +@@ -2796,18 +2359,14 @@ + * while increasing bulk throughput. + * this functionality is controlled by the InterruptThrottleRate module + * parameter (see e1000_param.c) +- * @adapter: pointer to adapter +- * @itr_setting: current adapter->itr +- * @packets: the number of packets during this measurement interval +- * @bytes: the number of bytes during this measurement interval + **/ + static unsigned int e1000_update_itr(struct e1000_adapter *adapter, +- u16 itr_setting, int packets, int bytes) ++ u16 itr_setting, int packets, ++ int bytes) + { + unsigned int retval = itr_setting; +- struct e1000_hw *hw = &adapter->hw; +- +- if (unlikely(hw->mac_type < e1000_82540)) ++ ++ if (unlikely(!(adapter->flags & E1000_FLAG_HAS_INTR_MODERATION))) + goto update_itr_done; + + if (packets == 0) +@@ -2815,30 +2374,34 @@ + + switch (itr_setting) { + case lowest_latency: +- /* jumbo frames get bulk treatment*/ ++ /* handle TSO and jumbo frames */ + if (bytes/packets > 8000) + retval = bulk_latency; +- else if ((packets < 5) && (bytes > 512)) ++ else if ((packets < 5) && (bytes > 512)) { + retval = low_latency; ++ } + break; + case low_latency: /* 50 usec aka 20000 ints/s */ + if (bytes > 10000) { +- /* jumbo frames need bulk latency setting */ +- if (bytes/packets > 8000) ++ /* this if handles the TSO accounting */ ++ if (bytes/packets > 8000) { + retval = bulk_latency; +- else if ((packets < 10) || ((bytes/packets) > 1200)) ++ } else if ((packets < 10) || ((bytes/packets) > 1200)) { + retval = bulk_latency; +- else if ((packets > 35)) ++ } else if ((packets > 35)) { + retval = lowest_latency; +- } else if (bytes/packets > 2000) ++ } ++ } else if (bytes/packets > 2000) { + retval = bulk_latency; +- else if (packets <= 2 && bytes < 512) ++ } else if (packets <= 2 && bytes < 512) { + retval = lowest_latency; ++ } + break; + case bulk_latency: /* 250 usec aka 4000 ints/s */ + if (bytes > 25000) { +- if (packets > 35) ++ if (packets > 35) { + retval = low_latency; ++ } + } else if (bytes < 6000) { + retval = low_latency; + } +@@ -2855,7 +2418,7 @@ + u16 current_itr; + u32 new_itr = adapter->itr; + +- if (unlikely(hw->mac_type < e1000_82540)) ++ if (unlikely(!(adapter->flags & E1000_FLAG_HAS_INTR_MODERATION))) + return; + + /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ +@@ -2907,7 +2470,7 @@ + min(adapter->itr + (new_itr >> 2), new_itr) : + new_itr; + adapter->itr = new_itr; +- ew32(ITR, 1000000000 / (new_itr * 256)); ++ E1000_WRITE_REG(hw, E1000_ITR, 1000000000 / (new_itr * 256)); + } + + return; +@@ -2921,8 +2484,9 @@ + #define E1000_TX_FLAGS_VLAN_SHIFT 16 + + static int e1000_tso(struct e1000_adapter *adapter, +- struct e1000_tx_ring *tx_ring, struct sk_buff *skb) +-{ ++ struct e1000_tx_ring *tx_ring, struct sk_buff *skb) ++{ ++#ifdef NETIF_F_TSO + struct e1000_context_desc *context_desc; + struct e1000_buffer *buffer_info; + unsigned int i; +@@ -2950,13 +2514,15 @@ + 0); + cmd_length = E1000_TXD_CMD_IP; + ipcse = skb_transport_offset(skb) - 1; +- } else if (skb->protocol == htons(ETH_P_IPV6)) { ++#ifdef NETIF_F_TSO6 ++ } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { + ipv6_hdr(skb)->payload_len = 0; + tcp_hdr(skb)->check = + ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, + &ipv6_hdr(skb)->daddr, + 0, IPPROTO_TCP, 0); + ipcse = 0; ++#endif + } + ipcss = skb_network_offset(skb); + ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; +@@ -2984,90 +2550,111 @@ + buffer_info->time_stamp = jiffies; + buffer_info->next_to_watch = i; + +- if (++i == tx_ring->count) i = 0; ++ E1000_TX_DESC_INC(tx_ring,i); + tx_ring->next_to_use = i; + +- return true; +- } +- return false; ++ return TRUE; ++ } ++#endif ++ ++ return FALSE; + } + + static bool e1000_tx_csum(struct e1000_adapter *adapter, +- struct e1000_tx_ring *tx_ring, struct sk_buff *skb) ++ struct e1000_tx_ring *tx_ring, ++ struct sk_buff *skb) + { + struct e1000_context_desc *context_desc; + struct e1000_buffer *buffer_info; + unsigned int i; + u8 css; +- +- if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { +- css = skb_transport_offset(skb); +- +- i = tx_ring->next_to_use; +- buffer_info = &tx_ring->buffer_info[i]; +- context_desc = E1000_CONTEXT_DESC(*tx_ring, i); +- +- context_desc->lower_setup.ip_config = 0; +- context_desc->upper_setup.tcp_fields.tucss = css; +- context_desc->upper_setup.tcp_fields.tucso = +- css + skb->csum_offset; +- context_desc->upper_setup.tcp_fields.tucse = 0; +- context_desc->tcp_seg_setup.data = 0; +- context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT); +- +- buffer_info->time_stamp = jiffies; +- buffer_info->next_to_watch = i; +- +- if (unlikely(++i == tx_ring->count)) i = 0; +- tx_ring->next_to_use = i; +- +- return true; +- } +- +- return false; +-} +- +-#define E1000_MAX_TXD_PWR 12 +-#define E1000_MAX_DATA_PER_TXD (1<ip_summed != CHECKSUM_PARTIAL)) ++ return FALSE; ++ ++ switch (skb->protocol) { ++ case __constant_htons(ETH_P_IP): ++ if (ip_hdr(skb)->protocol == IPPROTO_TCP) ++ cmd_len |= E1000_TXD_CMD_TCP; ++ break; ++ case __constant_htons(ETH_P_IPV6): ++ /* XXX not handling all IPV6 headers */ ++ if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) ++ cmd_len |= E1000_TXD_CMD_TCP; ++ break; ++ default: ++ if (unlikely(net_ratelimit())) { ++ DPRINTK(PROBE, WARNING, "checksum_partial proto=%x!\n", ++ skb->protocol); ++ } ++ break; ++ } ++ ++ css = skb_transport_offset(skb); ++ ++ i = tx_ring->next_to_use; ++ buffer_info = &tx_ring->buffer_info[i]; ++ context_desc = E1000_CONTEXT_DESC(*tx_ring, i); ++ ++ context_desc->lower_setup.ip_config = 0; ++ context_desc->upper_setup.tcp_fields.tucss = css; ++ context_desc->upper_setup.tcp_fields.tucso = css + ++ skb->csum_offset; ++ context_desc->upper_setup.tcp_fields.tucse = 0; ++ context_desc->tcp_seg_setup.data = 0; ++ context_desc->cmd_and_length = cpu_to_le32(cmd_len); ++ ++ buffer_info->time_stamp = jiffies; ++ buffer_info->next_to_watch = i; ++ ++ E1000_TX_DESC_INC(tx_ring,i); ++ tx_ring->next_to_use = i; ++ ++ return TRUE; ++} + + static int e1000_tx_map(struct e1000_adapter *adapter, +- struct e1000_tx_ring *tx_ring, +- struct sk_buff *skb, unsigned int first, +- unsigned int max_per_txd, unsigned int nr_frags, +- unsigned int mss) +-{ +- struct e1000_hw *hw = &adapter->hw; ++ struct e1000_tx_ring *tx_ring, ++ struct sk_buff *skb, unsigned int first, ++ unsigned int max_per_txd, unsigned int nr_frags, ++ unsigned int mss) ++{ + struct e1000_buffer *buffer_info; + unsigned int len = skb->len; + unsigned int offset = 0, size, count = 0, i; ++#ifdef MAX_SKB_FRAGS + unsigned int f; + len -= skb->data_len; ++#endif + + i = tx_ring->next_to_use; + + while (len) { + buffer_info = &tx_ring->buffer_info[i]; + size = min(len, max_per_txd); ++#ifdef NETIF_F_TSO + /* Workaround for Controller erratum -- + * descriptor for non-tso packet in a linear SKB that follows a + * tso gets written back prematurely before the data is fully + * DMA'd to the controller */ +- if (!skb->data_len && tx_ring->last_tx_tso && +- !skb_is_gso(skb)) { ++ if (tx_ring->last_tx_tso && !skb_is_gso(skb)) { + tx_ring->last_tx_tso = 0; +- size -= 4; ++ if (!skb->data_len) ++ size -= 4; + } + + /* Workaround for premature desc write-backs + * in TSO mode. Append 4-byte sentinel desc */ + if (unlikely(mss && !nr_frags && size == len && size > 8)) + size -= 4; ++#endif + /* work-around for errata 10 and it applies + * to all controllers in PCI-X mode + * The fix is to make sure that the first descriptor of a + * packet is smaller than 2048 - 16 - 16 (or 2016) bytes + */ +- if (unlikely((hw->bus_type == e1000_bus_type_pcix) && ++ if (unlikely((adapter->hw.bus.type == e1000_bus_type_pcix) && + (size > 2015) && count == 0)) + size = 2015; + +@@ -3079,20 +2666,22 @@ + size -= 4; + + buffer_info->length = size; ++ /* set time_stamp *before* dma to help avoid a possible race */ ++ buffer_info->time_stamp = jiffies; + buffer_info->dma = + pci_map_single(adapter->pdev, + skb->data + offset, + size, + PCI_DMA_TODEVICE); +- buffer_info->time_stamp = jiffies; + buffer_info->next_to_watch = i; + + len -= size; + offset += size; + count++; +- if (unlikely(++i == tx_ring->count)) i = 0; +- } +- ++ E1000_TX_DESC_INC(tx_ring,i); ++ } ++ ++#ifdef MAX_SKB_FRAGS + for (f = 0; f < nr_frags; f++) { + struct skb_frag_struct *frag; + +@@ -3103,36 +2692,39 @@ + while (len) { + buffer_info = &tx_ring->buffer_info[i]; + size = min(len, max_per_txd); ++#ifdef NETIF_F_TSO + /* Workaround for premature desc write-backs + * in TSO mode. Append 4-byte sentinel desc */ + if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8)) + size -= 4; ++#endif + /* Workaround for potential 82544 hang in PCI-X. + * Avoid terminating buffers within evenly-aligned + * dwords. */ + if (unlikely(adapter->pcix_82544 && +- !((unsigned long)(frag->page+offset+size-1) & 4) && +- size > 4)) ++ !((unsigned long)(page_to_phys(frag->page) + offset ++ + size - 1) & 4) && ++ size > 4)) + size -= 4; + + buffer_info->length = size; ++ buffer_info->time_stamp = jiffies; + buffer_info->dma = + pci_map_page(adapter->pdev, + frag->page, + offset, + size, + PCI_DMA_TODEVICE); +- buffer_info->time_stamp = jiffies; + buffer_info->next_to_watch = i; + + len -= size; + offset += size; + count++; +- if (unlikely(++i == tx_ring->count)) i = 0; +- } +- } +- +- i = (i == 0) ? tx_ring->count - 1 : i - 1; ++ E1000_TX_DESC_INC(tx_ring,i); ++ } ++ } ++#endif ++ E1000_TX_DESC_DEC(tx_ring,i); + tx_ring->buffer_info[i].skb = skb; + tx_ring->buffer_info[first].next_to_watch = i; + +@@ -3140,10 +2732,9 @@ + } + + static void e1000_tx_queue(struct e1000_adapter *adapter, +- struct e1000_tx_ring *tx_ring, int tx_flags, +- int count) +-{ +- struct e1000_hw *hw = &adapter->hw; ++ struct e1000_tx_ring *tx_ring, ++ int tx_flags, int count) ++{ + struct e1000_tx_desc *tx_desc = NULL; + struct e1000_buffer *buffer_info; + u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; +@@ -3177,7 +2768,7 @@ + tx_desc->lower.data = + cpu_to_le32(txd_lower | buffer_info->length); + tx_desc->upper.data = cpu_to_le32(txd_upper); +- if (unlikely(++i == tx_ring->count)) i = 0; ++ E1000_TX_DESC_INC(tx_ring,i); + } + + tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); +@@ -3189,11 +2780,14 @@ + wmb(); + + tx_ring->next_to_use = i; +- writel(i, hw->hw_addr + tx_ring->tdt); ++ writel(i, adapter->hw.hw_addr + tx_ring->tdt); + /* we need this if more than one processor can write to our tail +- * at a time, it syncronizes IO on IA64/Altix systems */ ++ * at a time, it synchronizes IO on IA64/Altix systems */ + mmiowb(); + } ++ ++#define E1000_FIFO_HDR 0x10 ++#define E1000_82547_PAD_LEN 0x3E0 + + /** + * 82547 workaround to avoid controller hang in half-duplex environment. +@@ -3203,12 +2797,8 @@ + * flush all packets. When that occurs, we reset the Tx FIFO pointers + * to the beginning of the Tx FIFO. + **/ +- +-#define E1000_FIFO_HDR 0x10 +-#define E1000_82547_PAD_LEN 0x3E0 +- + static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter, +- struct sk_buff *skb) ++ struct sk_buff *skb) + { + u32 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; + u32 skb_fifo_len = skb->len + E1000_FIFO_HDR; +@@ -3233,45 +2823,10 @@ + return 0; + } + +-#define MINIMUM_DHCP_PACKET_SIZE 282 +-static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, +- struct sk_buff *skb) +-{ +- struct e1000_hw *hw = &adapter->hw; +- u16 length, offset; +- if (vlan_tx_tag_present(skb)) { +- if (!((vlan_tx_tag_get(skb) == hw->mng_cookie.vlan_id) && +- ( hw->mng_cookie.status & +- E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) ) +- return 0; +- } +- if (skb->len > MINIMUM_DHCP_PACKET_SIZE) { +- struct ethhdr *eth = (struct ethhdr *)skb->data; +- if ((htons(ETH_P_IP) == eth->h_proto)) { +- const struct iphdr *ip = +- (struct iphdr *)((u8 *)skb->data+14); +- if (IPPROTO_UDP == ip->protocol) { +- struct udphdr *udp = +- (struct udphdr *)((u8 *)ip + +- (ip->ihl << 2)); +- if (ntohs(udp->dest) == 67) { +- offset = (u8 *)udp + 8 - skb->data; +- length = skb->len - offset; +- +- return e1000_mng_write_dhcp_info(hw, +- (u8 *)udp + 8, +- length); +- } +- } +- } +- } +- return 0; +-} +- +-static int __e1000_maybe_stop_tx(struct net_device *netdev, int size) +-{ +- struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_tx_ring *tx_ring = adapter->tx_ring; ++static int __e1000_maybe_stop_tx(struct net_device *netdev, ++ struct e1000_tx_ring *tx_ring, int size) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); + + netif_stop_queue(netdev); + /* Herbert's original patch had: +@@ -3281,7 +2836,7 @@ + + /* We need to check again in a case another CPU has just + * made room available. */ +- if (likely(E1000_DESC_UNUSED(tx_ring) < size)) ++ if (likely(E1000_DESC_UNUSED(tx_ring) < ((size) * tx_ring->step))) + return -EBUSY; + + /* A reprieve! */ +@@ -3293,44 +2848,53 @@ + static int e1000_maybe_stop_tx(struct net_device *netdev, + struct e1000_tx_ring *tx_ring, int size) + { +- if (likely(E1000_DESC_UNUSED(tx_ring) >= size)) ++ if (likely(E1000_DESC_UNUSED(tx_ring) >= ((size) * tx_ring->step))) + return 0; +- return __e1000_maybe_stop_tx(netdev, size); ++ return __e1000_maybe_stop_tx(netdev, tx_ring, size); + } + + #define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 ) + static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; +- struct e1000_tx_ring *tx_ring; +- unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD; +- unsigned int max_txd_pwr = E1000_MAX_TXD_PWR; ++ struct e1000_tx_ring *tx_ring = adapter->tx_ring; ++ unsigned int max_txd_pwr = adapter->tx_desc_pwr; ++ unsigned int first, max_per_txd = (1 << max_txd_pwr); + unsigned int tx_flags = 0; +- unsigned int len = skb->len - skb->data_len; +- unsigned long flags; +- unsigned int nr_frags; +- unsigned int mss; ++ unsigned int len = skb->len; ++ unsigned long irq_flags; ++ unsigned int nr_frags = 0; ++ unsigned int mss = 0; + int count = 0; + int tso; ++#ifdef MAX_SKB_FRAGS + unsigned int f; +- +- /* This goes back to the question of how to logically map a tx queue +- * to a flow. Right now, performance is impacted slightly negatively +- * if using multiple tx queues. If the stack breaks away from a +- * single qdisc implementation, we can look at this again. */ +- tx_ring = adapter->tx_ring; ++ len -= skb->data_len; ++#endif ++ ++ if (test_bit(__E1000_DOWN, &adapter->state)) { ++ dev_kfree_skb_any(skb); ++ return NETDEV_TX_OK; ++ } + + if (unlikely(skb->len <= 0)) { + dev_kfree_skb_any(skb); + return NETDEV_TX_OK; + } +- +- /* 82571 and newer doesn't need the workaround that limited descriptor +- * length to 4kB */ +- if (hw->mac_type >= e1000_82571) +- max_per_txd = 8192; +- ++ /* On PCIX HW, there have been rare TXHangs caused by custom apps ++ * sending frames with skb->len == 16 (macdest+macsrc+protocol+2bytes). ++ * Such frames are not transmitted by registered protocols, so are ++ * only a problem for experimental code. ++ * Pad all 16 byte packets with an additional byte to work-around this ++ * problem case. ++ */ ++ if (unlikely(skb->len == 16)) { ++ skb_pad(skb,1); ++ skb_put(skb,1); ++ } ++ ++ ++#ifdef NETIF_F_TSO + mss = skb_shinfo(skb)->gso_size; + /* The controller does a simple calculation to + * make sure there is enough room in the FIFO before +@@ -3343,12 +2907,10 @@ + max_per_txd = min(mss << 2, max_per_txd); + max_txd_pwr = fls(max_per_txd) - 1; + +- /* TSO Workaround for 82571/2/3 Controllers -- if skb->data +- * points to just header, pull a few bytes of payload from +- * frags into skb->data */ ++ /* TSO Workaround */ + hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); +- if (skb->data_len && hdr_len == len) { +- switch (hw->mac_type) { ++ if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) { ++ switch (adapter->hw.mac.type) { + unsigned int pull_size; + case e1000_82544: + /* Make sure we have room to chop off 4 bytes, +@@ -3359,11 +2921,6 @@ + * into the next dword */ + if ((unsigned long)(skb_tail_pointer(skb) - 1) & 4) + break; +- /* fall through */ +- case e1000_82571: +- case e1000_82572: +- case e1000_82573: +- case e1000_ich8lan: + pull_size = min((unsigned int)4, skb->data_len); + if (!__pskb_pull_tail(skb, pull_size)) { + DPRINTK(DRV, ERR, +@@ -3384,10 +2941,16 @@ + if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) + count++; + count++; +- ++#else ++ if (skb->ip_summed == CHECKSUM_PARTIAL) ++ count++; ++#endif ++ ++#ifdef NETIF_F_TSO + /* Controller Erratum workaround */ + if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb)) + count++; ++#endif + + count += TXD_USE_COUNT(len, max_txd_pwr); + +@@ -3397,10 +2960,11 @@ + /* work-around for errata 10 and it applies to all controllers + * in PCI-X mode, so add one more descriptor to the count + */ +- if (unlikely((hw->bus_type == e1000_bus_type_pcix) && ++ if (unlikely((adapter->hw.bus.type == e1000_bus_type_pcix) && + (len > 2015))) + count++; + ++#ifdef MAX_SKB_FRAGS + nr_frags = skb_shinfo(skb)->nr_frags; + for (f = 0; f < nr_frags; f++) + count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size, +@@ -3408,54 +2972,52 @@ + if (adapter->pcix_82544) + count += nr_frags; + +- +- if (hw->tx_pkt_filtering && +- (hw->mac_type == e1000_82573)) +- e1000_transfer_dhcp_info(adapter, skb); +- +- if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) +- /* Collision - tell upper layer to requeue */ +- return NETDEV_TX_LOCKED; ++#endif ++ ++ spin_lock_irqsave(&tx_ring->tx_lock, irq_flags); + + /* need: count + 2 desc gap to keep tail from touching + * head, otherwise try next time */ + if (unlikely(e1000_maybe_stop_tx(netdev, tx_ring, count + 2))) { +- spin_unlock_irqrestore(&tx_ring->tx_lock, flags); ++ spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags); + return NETDEV_TX_BUSY; + } + +- if (unlikely(hw->mac_type == e1000_82547)) { ++ if (unlikely(adapter->hw.mac.type == e1000_82547)) { + if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) { + netif_stop_queue(netdev); +- mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1); +- spin_unlock_irqrestore(&tx_ring->tx_lock, flags); ++ if (!test_bit(__E1000_DOWN, &adapter->state)) ++ mod_timer(&adapter->tx_fifo_stall_timer, ++ jiffies + 1); ++ spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags); + return NETDEV_TX_BUSY; + } + } + ++ spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags); ++ ++#ifdef NETIF_F_HW_VLAN_TX + if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) { + tx_flags |= E1000_TX_FLAGS_VLAN; + tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT); + } ++#endif + + first = tx_ring->next_to_use; + + tso = e1000_tso(adapter, tx_ring, skb); + if (tso < 0) { + dev_kfree_skb_any(skb); +- spin_unlock_irqrestore(&tx_ring->tx_lock, flags); + return NETDEV_TX_OK; + } + + if (likely(tso)) { +- tx_ring->last_tx_tso = 1; ++ if (likely(adapter->hw.mac.type != e1000_82544)) ++ tx_ring->last_tx_tso = 1; + tx_flags |= E1000_TX_FLAGS_TSO; + } else if (likely(e1000_tx_csum(adapter, tx_ring, skb))) + tx_flags |= E1000_TX_FLAGS_CSUM; + +- /* Old method was to assume IPv4 packet by default if TSO was enabled. +- * 82571 hardware supports TSO capabilities for IPv6 as well... +- * no longer assume, we must. */ + if (likely(skb->protocol == htons(ETH_P_IP))) + tx_flags |= E1000_TX_FLAGS_IPV4; + +@@ -3468,15 +3030,14 @@ + /* Make sure there is space in the ring for the next send. */ + e1000_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 2); + +- spin_unlock_irqrestore(&tx_ring->tx_lock, flags); + return NETDEV_TX_OK; + } + ++ + /** + * e1000_tx_timeout - Respond to a Tx Hang + * @netdev: network interface device structure + **/ +- + static void e1000_tx_timeout(struct net_device *netdev) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +@@ -3488,8 +3049,8 @@ + + static void e1000_reset_task(struct work_struct *work) + { +- struct e1000_adapter *adapter = +- container_of(work, struct e1000_adapter, reset_task); ++ struct e1000_adapter *adapter; ++ adapter = container_of(work, struct e1000_adapter, reset_task); + + e1000_reinit_locked(adapter); + } +@@ -3501,8 +3062,7 @@ + * Returns the address of the device statistics structure. + * The statistics are actually updated from the timer callback. + **/ +- +-static struct net_device_stats *e1000_get_stats(struct net_device *netdev) ++static struct net_device_stats * e1000_get_stats(struct net_device *netdev) + { + struct e1000_adapter *adapter = netdev_priv(netdev); + +@@ -3517,65 +3077,43 @@ + * + * Returns 0 on success, negative on failure + **/ +- + static int e1000_change_mtu(struct net_device *netdev, int new_mtu) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; +- int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; +- u16 eeprom_data = 0; +- +- if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) || +- (max_frame > MAX_JUMBO_FRAME_SIZE)) { ++ int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; ++ ++ if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { + DPRINTK(PROBE, ERR, "Invalid MTU setting\n"); + return -EINVAL; + } + + /* Adapter-specific max frame size limits. */ +- switch (hw->mac_type) { +- case e1000_undefined ... e1000_82542_rev2_1: +- case e1000_ich8lan: +- if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) { ++ switch (adapter->hw.mac.type) { ++ case e1000_undefined: ++ case e1000_82542: ++ if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) { + DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n"); + return -EINVAL; + } + break; +- case e1000_82573: +- /* Jumbo Frames not supported if: +- * - this is not an 82573L device +- * - ASPM is enabled in any way (0x1A bits 3:2) */ +- e1000_read_eeprom(hw, EEPROM_INIT_3GIO_3, 1, +- &eeprom_data); +- if ((hw->device_id != E1000_DEV_ID_82573L) || +- (eeprom_data & EEPROM_WORD1A_ASPM_MASK)) { +- if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) { +- DPRINTK(PROBE, ERR, +- "Jumbo Frames not supported.\n"); +- return -EINVAL; +- } +- break; +- } +- /* ERT will be enabled later to enable wire speed receives */ +- +- /* fall through to get support */ +- case e1000_82571: +- case e1000_82572: +- case e1000_80003es2lan: +-#define MAX_STD_JUMBO_FRAME_SIZE 9234 +- if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { +- DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n"); +- return -EINVAL; +- } +- break; + default: + /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */ + break; + } ++ ++ while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) ++ msleep(1); ++ /* e1000_down has a dependency on max_frame_size */ ++ adapter->max_frame_size = max_frame; ++ if (netif_running(netdev)) ++ e1000_down(adapter); + + /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN + * means we reserve 2 more, this pushes us to allocate from the next +- * larger slab size +- * i.e. RXBUFFER_2048 --> size-4096 slab */ ++ * larger slab size. ++ * i.e. RXBUFFER_2048 --> size-4096 slab ++ * however with the new *_jumbo_rx* routines, jumbo receives will use ++ * fragmented skbs */ + + if (max_frame <= E1000_RXBUFFER_256) + adapter->rx_buffer_len = E1000_RXBUFFER_256; +@@ -3585,24 +3123,34 @@ + adapter->rx_buffer_len = E1000_RXBUFFER_1024; + else if (max_frame <= E1000_RXBUFFER_2048) + adapter->rx_buffer_len = E1000_RXBUFFER_2048; ++#ifdef CONFIG_E1000_NAPI ++ else ++ adapter->rx_buffer_len = E1000_RXBUFFER_4096; ++#else + else if (max_frame <= E1000_RXBUFFER_4096) + adapter->rx_buffer_len = E1000_RXBUFFER_4096; + else if (max_frame <= E1000_RXBUFFER_8192) + adapter->rx_buffer_len = E1000_RXBUFFER_8192; + else if (max_frame <= E1000_RXBUFFER_16384) + adapter->rx_buffer_len = E1000_RXBUFFER_16384; ++#endif + + /* adjust allocation if LPE protects us, and we aren't using SBP */ +- if (!hw->tbi_compatibility_on && +- ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) || ++ if (!e1000_tbi_sbp_enabled_82543(&adapter->hw) && ++ ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || + (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))) + adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; + ++ DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", ++ netdev->mtu, new_mtu); + netdev->mtu = new_mtu; +- hw->max_frame_size = max_frame; +- +- if (netif_running(netdev)) +- e1000_reinit_locked(adapter); ++ ++ if (netif_running(netdev)) ++ e1000_up(adapter); ++ else ++ e1000_reset(adapter); ++ ++ clear_bit(__E1000_RESETTING, &adapter->state); + + return 0; + } +@@ -3611,12 +3159,13 @@ + * e1000_update_stats - Update the board statistics counters + * @adapter: board private structure + **/ +- + void e1000_update_stats(struct e1000_adapter *adapter) + { + struct e1000_hw *hw = &adapter->hw; +- struct pci_dev *pdev = adapter->pdev; +- unsigned long flags; ++#ifdef HAVE_PCI_ERS ++ struct pci_dev *pdev = adapter->pdev; ++#endif ++ unsigned long irq_flags; + u16 phy_tmp; + + #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF +@@ -3627,100 +3176,58 @@ + */ + if (adapter->link_speed == 0) + return; ++#ifdef HAVE_PCI_ERS + if (pci_channel_offline(pdev)) + return; +- +- spin_lock_irqsave(&adapter->stats_lock, flags); +- +- /* these counters are modified from e1000_tbi_adjust_stats, ++#endif ++ ++ spin_lock_irqsave(&adapter->stats_lock, irq_flags); ++ ++ /* these counters are modified from e1000_adjust_tbi_stats, + * called from the interrupt context, so they must only + * be written while holding adapter->stats_lock + */ + +- adapter->stats.crcerrs += er32(CRCERRS); +- adapter->stats.gprc += er32(GPRC); +- adapter->stats.gorcl += er32(GORCL); +- adapter->stats.gorch += er32(GORCH); +- adapter->stats.bprc += er32(BPRC); +- adapter->stats.mprc += er32(MPRC); +- adapter->stats.roc += er32(ROC); +- +- if (hw->mac_type != e1000_ich8lan) { +- adapter->stats.prc64 += er32(PRC64); +- adapter->stats.prc127 += er32(PRC127); +- adapter->stats.prc255 += er32(PRC255); +- adapter->stats.prc511 += er32(PRC511); +- adapter->stats.prc1023 += er32(PRC1023); +- adapter->stats.prc1522 += er32(PRC1522); +- } +- +- adapter->stats.symerrs += er32(SYMERRS); +- adapter->stats.mpc += er32(MPC); +- adapter->stats.scc += er32(SCC); +- adapter->stats.ecol += er32(ECOL); +- adapter->stats.mcc += er32(MCC); +- adapter->stats.latecol += er32(LATECOL); +- adapter->stats.dc += er32(DC); +- adapter->stats.sec += er32(SEC); +- adapter->stats.rlec += er32(RLEC); +- adapter->stats.xonrxc += er32(XONRXC); +- adapter->stats.xontxc += er32(XONTXC); +- adapter->stats.xoffrxc += er32(XOFFRXC); +- adapter->stats.xofftxc += er32(XOFFTXC); +- adapter->stats.fcruc += er32(FCRUC); +- adapter->stats.gptc += er32(GPTC); +- adapter->stats.gotcl += er32(GOTCL); +- adapter->stats.gotch += er32(GOTCH); +- adapter->stats.rnbc += er32(RNBC); +- adapter->stats.ruc += er32(RUC); +- adapter->stats.rfc += er32(RFC); +- adapter->stats.rjc += er32(RJC); +- adapter->stats.torl += er32(TORL); +- adapter->stats.torh += er32(TORH); +- adapter->stats.totl += er32(TOTL); +- adapter->stats.toth += er32(TOTH); +- adapter->stats.tpr += er32(TPR); +- +- if (hw->mac_type != e1000_ich8lan) { +- adapter->stats.ptc64 += er32(PTC64); +- adapter->stats.ptc127 += er32(PTC127); +- adapter->stats.ptc255 += er32(PTC255); +- adapter->stats.ptc511 += er32(PTC511); +- adapter->stats.ptc1023 += er32(PTC1023); +- adapter->stats.ptc1522 += er32(PTC1522); +- } +- +- adapter->stats.mptc += er32(MPTC); +- adapter->stats.bptc += er32(BPTC); ++ adapter->stats.crcerrs += E1000_READ_REG(hw, E1000_CRCERRS); ++ adapter->stats.gprc += E1000_READ_REG(hw, E1000_GPRC); ++ adapter->stats.gorc += E1000_READ_REG(hw, E1000_GORCL); ++ E1000_READ_REG(hw, E1000_GORCH); /* Clear gorc */ ++ adapter->stats.bprc += E1000_READ_REG(hw, E1000_BPRC); ++ adapter->stats.mprc += E1000_READ_REG(hw, E1000_MPRC); ++ adapter->stats.roc += E1000_READ_REG(hw, E1000_ROC); ++ adapter->stats.mpc += E1000_READ_REG(hw, E1000_MPC); ++ adapter->stats.scc += E1000_READ_REG(hw, E1000_SCC); ++ adapter->stats.ecol += E1000_READ_REG(hw, E1000_ECOL); ++ adapter->stats.mcc += E1000_READ_REG(hw, E1000_MCC); ++ adapter->stats.latecol += E1000_READ_REG(hw, E1000_LATECOL); ++ adapter->stats.dc += E1000_READ_REG(hw, E1000_DC); ++ adapter->stats.xonrxc += E1000_READ_REG(hw, E1000_XONRXC); ++ adapter->stats.xontxc += E1000_READ_REG(hw, E1000_XONTXC); ++ adapter->stats.xoffrxc += E1000_READ_REG(hw, E1000_XOFFRXC); ++ adapter->stats.xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC); ++ adapter->stats.gptc += E1000_READ_REG(hw, E1000_GPTC); ++ adapter->stats.gotc += E1000_READ_REG(hw, E1000_GOTCL); ++ E1000_READ_REG(hw, E1000_GOTCH); /* Clear gotc */ ++ adapter->stats.rnbc += E1000_READ_REG(hw, E1000_RNBC); ++ adapter->stats.ruc += E1000_READ_REG(hw, E1000_RUC); ++ ++ adapter->stats.mptc += E1000_READ_REG(hw, E1000_MPTC); ++ adapter->stats.bptc += E1000_READ_REG(hw, E1000_BPTC); + + /* used for adaptive IFS */ + +- hw->tx_packet_delta = er32(TPT); +- adapter->stats.tpt += hw->tx_packet_delta; +- hw->collision_delta = er32(COLC); +- adapter->stats.colc += hw->collision_delta; +- +- if (hw->mac_type >= e1000_82543) { +- adapter->stats.algnerrc += er32(ALGNERRC); +- adapter->stats.rxerrc += er32(RXERRC); +- adapter->stats.tncrs += er32(TNCRS); +- adapter->stats.cexterr += er32(CEXTERR); +- adapter->stats.tsctc += er32(TSCTC); +- adapter->stats.tsctfc += er32(TSCTFC); +- } +- if (hw->mac_type > e1000_82547_rev_2) { +- adapter->stats.iac += er32(IAC); +- adapter->stats.icrxoc += er32(ICRXOC); +- +- if (hw->mac_type != e1000_ich8lan) { +- adapter->stats.icrxptc += er32(ICRXPTC); +- adapter->stats.icrxatc += er32(ICRXATC); +- adapter->stats.ictxptc += er32(ICTXPTC); +- adapter->stats.ictxatc += er32(ICTXATC); +- adapter->stats.ictxqec += er32(ICTXQEC); +- adapter->stats.ictxqmtc += er32(ICTXQMTC); +- adapter->stats.icrxdmtc += er32(ICRXDMTC); +- } ++ hw->mac.tx_packet_delta = E1000_READ_REG(hw, E1000_TPT); ++ adapter->stats.tpt += hw->mac.tx_packet_delta; ++ hw->mac.collision_delta = E1000_READ_REG(hw, E1000_COLC); ++ adapter->stats.colc += hw->mac.collision_delta; ++ ++ if (hw->mac.type >= e1000_82543) { ++ adapter->stats.algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC); ++ adapter->stats.rxerrc += E1000_READ_REG(hw, E1000_RXERRC); ++ adapter->stats.tncrs += E1000_READ_REG(hw, E1000_TNCRS); ++ adapter->stats.cexterr += E1000_READ_REG(hw, E1000_CEXTERR); ++ adapter->stats.tsctc += E1000_READ_REG(hw, E1000_TSCTC); ++ adapter->stats.tsctfc += E1000_READ_REG(hw, E1000_TSCTFC); + } + + /* Fill out the OS statistics structure */ +@@ -3735,223 +3242,241 @@ + adapter->stats.crcerrs + adapter->stats.algnerrc + + adapter->stats.ruc + adapter->stats.roc + + adapter->stats.cexterr; +- adapter->stats.rlerrc = adapter->stats.ruc + adapter->stats.roc; +- adapter->net_stats.rx_length_errors = adapter->stats.rlerrc; ++ adapter->net_stats.rx_length_errors = adapter->stats.ruc + ++ adapter->stats.roc; + adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; + adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc; + adapter->net_stats.rx_missed_errors = adapter->stats.mpc; + + /* Tx Errors */ +- adapter->stats.txerrc = adapter->stats.ecol + adapter->stats.latecol; +- adapter->net_stats.tx_errors = adapter->stats.txerrc; ++ adapter->net_stats.tx_errors = adapter->stats.ecol + ++ adapter->stats.latecol; + adapter->net_stats.tx_aborted_errors = adapter->stats.ecol; + adapter->net_stats.tx_window_errors = adapter->stats.latecol; +- adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs; +- if (hw->bad_tx_carr_stats_fd && ++ if ((adapter->flags & E1000_FLAG_BAD_TX_CARRIER_STATS_FD) && + adapter->link_duplex == FULL_DUPLEX) { + adapter->net_stats.tx_carrier_errors = 0; + adapter->stats.tncrs = 0; ++ } else { ++ adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs; + } + + /* Tx Dropped needs to be maintained elsewhere */ + + /* Phy Stats */ +- if (hw->media_type == e1000_media_type_copper) { ++ if (hw->phy.media_type == e1000_media_type_copper) { + if ((adapter->link_speed == SPEED_1000) && + (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { + phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; + adapter->phy_stats.idle_errors += phy_tmp; + } + +- if ((hw->mac_type <= e1000_82546) && +- (hw->phy_type == e1000_phy_m88) && ++ if ((hw->mac.type <= e1000_82546) && ++ (hw->phy.type == e1000_phy_m88) && + !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp)) + adapter->phy_stats.receive_errors += phy_tmp; + } + + /* Management Stats */ +- if (hw->has_smbus) { +- adapter->stats.mgptc += er32(MGTPTC); +- adapter->stats.mgprc += er32(MGTPRC); +- adapter->stats.mgpdc += er32(MGTPDC); +- } +- +- spin_unlock_irqrestore(&adapter->stats_lock, flags); +-} +- +-/** +- * e1000_intr_msi - Interrupt Handler ++ if (adapter->flags & E1000_FLAG_HAS_SMBUS) { ++ adapter->stats.mgptc += E1000_READ_REG(hw, E1000_MGTPTC); ++ adapter->stats.mgprc += E1000_READ_REG(hw, E1000_MGTPRC); ++ adapter->stats.mgpdc += E1000_READ_REG(hw, E1000_MGTPDC); ++ } ++ ++ spin_unlock_irqrestore(&adapter->stats_lock, irq_flags); ++} ++#ifdef SIOCGMIIPHY ++ ++/** ++ * e1000_phy_read_status - Update the PHY register status snapshot ++ * @adapter: board private structure ++ **/ ++static void e1000_phy_read_status(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ struct e1000_phy_regs *phy = &adapter->phy_regs; ++ int ret_val = E1000_SUCCESS; ++ unsigned long irq_flags; ++ ++ ++ spin_lock_irqsave(&adapter->stats_lock, irq_flags); ++ ++ if (E1000_READ_REG(hw, E1000_STATUS)& E1000_STATUS_LU) { ++ ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy->bmcr); ++ ret_val |= e1000_read_phy_reg(hw, PHY_STATUS, &phy->bmsr); ++ ret_val |= e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, ++ &phy->advertise); ++ ret_val |= e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy->lpa); ++ ret_val |= e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, ++ &phy->expansion); ++ ret_val |= e1000_read_phy_reg(hw, PHY_1000T_CTRL, ++ &phy->ctrl1000); ++ ret_val |= e1000_read_phy_reg(hw, PHY_1000T_STATUS, ++ &phy->stat1000); ++ ret_val |= e1000_read_phy_reg(hw, PHY_EXT_STATUS, ++ &phy->estatus); ++ if (ret_val) ++ DPRINTK(DRV, WARNING, "Error reading PHY register\n"); ++ } else { ++ /* Do not read PHY registers if link is not up ++ * Set values to typical power-on defaults */ ++ phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); ++ phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | ++ BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | ++ BMSR_ERCAP); ++ phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | ++ ADVERTISE_ALL | ADVERTISE_CSMA); ++ phy->lpa = 0; ++ phy->expansion = EXPANSION_ENABLENPAGE; ++ phy->ctrl1000 = ADVERTISE_1000FULL; ++ phy->stat1000 = 0; ++ phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); ++ } ++ ++ spin_unlock_irqrestore(&adapter->stats_lock, irq_flags); ++} ++#endif ++ ++ ++/** ++ * e1000_intr - Interrupt Handler + * @irq: interrupt number + * @data: pointer to a network interface device structure + **/ +- +-static irqreturn_t e1000_intr_msi(int irq, void *data) ++static irqreturn_t e1000_intr(int irq, void *data) + { + struct net_device *netdev = data; + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +- u32 icr = er32(ICR); +- +- /* in NAPI mode read ICR disables interrupts using IAM */ +- +- if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { +- hw->get_link_status = 1; +- /* 80003ES2LAN workaround-- For packet buffer work-around on +- * link down event; disable receives here in the ISR and reset +- * adapter in watchdog */ +- if (netif_carrier_ok(netdev) && +- (hw->mac_type == e1000_80003es2lan)) { +- /* disable receives */ +- u32 rctl = er32(RCTL); +- ew32(RCTL, rctl & ~E1000_RCTL_EN); +- } ++ u32 icr = E1000_READ_REG(hw, E1000_ICR); ++ ++ if (unlikely((!icr) || test_bit(__E1000_DOWN, &adapter->state))) ++ return IRQ_NONE; /* Not our interrupt */ ++ ++ if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) { ++ hw->mac.get_link_status = 1; ++ + /* guard against interrupt when we're going down */ +- if (!test_bit(__E1000_DOWN, &adapter->flags)) ++ if (!test_bit(__E1000_DOWN, &adapter->state)) + mod_timer(&adapter->watchdog_timer, jiffies + 1); + } + +- if (likely(netif_rx_schedule_prep(netdev, &adapter->napi))) { ++#ifdef CONFIG_E1000_NAPI ++ if (likely(napi_schedule_prep(&adapter->rx_ring->napi))) { + adapter->total_tx_bytes = 0; + adapter->total_tx_packets = 0; + adapter->total_rx_bytes = 0; + adapter->total_rx_packets = 0; +- __netif_rx_schedule(netdev, &adapter->napi); +- } else +- e1000_irq_enable(adapter); +- ++ __napi_schedule(&adapter->rx_ring->napi); ++ } ++#else ++ /* Writing IMC and IMS is needed for 82547. ++ * Due to Hub Link bus being occupied, an interrupt ++ * de-assertion message is not able to be sent. ++ * When an interrupt assertion message is generated later, ++ * two messages are re-ordered and sent out. ++ * That causes APIC to think 82547 is in de-assertion ++ * state, while 82547 is in assertion state, resulting ++ * in dead lock. Writing IMC forces 82547 into ++ * de-assertion state. ++ */ ++ if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2) ++ E1000_WRITE_REG(hw, E1000_IMC, ~0); ++ ++ adapter->total_tx_bytes = 0; ++ adapter->total_rx_bytes = 0; ++ adapter->total_tx_packets = 0; ++ adapter->total_rx_packets = 0; ++ ++ adapter->clean_rx(adapter, adapter->rx_ring); ++ e1000_clean_tx_irq(adapter, adapter->tx_ring); ++ ++ if (likely(adapter->itr_setting & 3)) ++ e1000_set_itr(adapter); ++ ++ if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2) ++ if (!test_bit(__E1000_DOWN, &adapter->state)) ++ e1000_irq_enable(adapter); ++ ++#endif + return IRQ_HANDLED; + } + +-/** +- * e1000_intr - Interrupt Handler +- * @irq: interrupt number +- * @data: pointer to a network interface device structure +- **/ +- +-static irqreturn_t e1000_intr(int irq, void *data) +-{ +- struct net_device *netdev = data; +- struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; +- u32 rctl, icr = er32(ICR); +- +- if (unlikely((!icr) || test_bit(__E1000_RESETTING, &adapter->flags))) +- return IRQ_NONE; /* Not our interrupt */ +- +- /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is +- * not set, then the adapter didn't send an interrupt */ +- if (unlikely(hw->mac_type >= e1000_82571 && +- !(icr & E1000_ICR_INT_ASSERTED))) +- return IRQ_NONE; +- +- /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No +- * need for the IMC write */ +- +- if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) { +- hw->get_link_status = 1; +- /* 80003ES2LAN workaround-- +- * For packet buffer work-around on link down event; +- * disable receives here in the ISR and +- * reset adapter in watchdog +- */ +- if (netif_carrier_ok(netdev) && +- (hw->mac_type == e1000_80003es2lan)) { +- /* disable receives */ +- rctl = er32(RCTL); +- ew32(RCTL, rctl & ~E1000_RCTL_EN); +- } +- /* guard against interrupt when we're going down */ +- if (!test_bit(__E1000_DOWN, &adapter->flags)) +- mod_timer(&adapter->watchdog_timer, jiffies + 1); +- } +- +- if (unlikely(hw->mac_type < e1000_82571)) { +- /* disable interrupts, without the synchronize_irq bit */ +- ew32(IMC, ~0); +- E1000_WRITE_FLUSH(); +- } +- if (likely(netif_rx_schedule_prep(netdev, &adapter->napi))) { +- adapter->total_tx_bytes = 0; +- adapter->total_tx_packets = 0; +- adapter->total_rx_bytes = 0; +- adapter->total_rx_packets = 0; +- __netif_rx_schedule(netdev, &adapter->napi); +- } else +- /* this really should not happen! if it does it is basically a +- * bug, but not a hard error, so enable ints and continue */ +- e1000_irq_enable(adapter); +- +- return IRQ_HANDLED; +-} +- +-/** +- * e1000_clean - NAPI Rx polling callback +- * @adapter: board private structure +- **/ +-static int e1000_clean(struct napi_struct *napi, int budget) +-{ +- struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi); +- struct net_device *poll_dev = adapter->netdev; +- int tx_cleaned = 0, work_done = 0; +- +- /* Must NOT use netdev_priv macro here. */ +- adapter = poll_dev->priv; +- +- /* e1000_clean is called per-cpu. This lock protects +- * tx_ring[0] from being cleaned by multiple cpus +- * simultaneously. A failure obtaining the lock means +- * tx_ring[0] is currently being cleaned anyway. */ +- if (spin_trylock(&adapter->tx_queue_lock)) { +- tx_cleaned = e1000_clean_tx_irq(adapter, +- &adapter->tx_ring[0]); +- spin_unlock(&adapter->tx_queue_lock); +- } +- +- adapter->clean_rx(adapter, &adapter->rx_ring[0], +- &work_done, budget); +- +- if (tx_cleaned) ++#ifdef CONFIG_E1000_NAPI ++/** ++ * e1000_poll - NAPI Rx polling callback ++ * @napi: struct associated with this polling callback ++ * @budget: amount of packets driver is allowed to process this poll ++ **/ ++static int e1000_poll(struct napi_struct *napi, int budget) ++{ ++ struct e1000_rx_ring *rx_ring = container_of(napi, struct e1000_rx_ring, ++ napi); ++ struct e1000_adapter *adapter = rx_ring->adapter; ++ bool tx_clean_complete; ++ int work_done = 0; ++ ++ tx_clean_complete = e1000_clean_tx_irq(adapter, adapter->tx_ring); ++ ++ adapter->clean_rx(adapter, adapter->rx_ring, &work_done, budget); ++ ++ if (!tx_clean_complete) + work_done = budget; + +- /* If budget not fully consumed, exit the polling mode */ ++#ifndef HAVE_NETDEV_NAPI_LIST ++ if (!netif_running(adapter->netdev)) ++ work_done = 0; ++ ++#endif ++ /* If no Tx and not enough Rx work done, exit the polling mode */ + if (work_done < budget) { + if (likely(adapter->itr_setting & 3)) + e1000_set_itr(adapter); +- netif_rx_complete(poll_dev, napi); +- e1000_irq_enable(adapter); ++ napi_complete(napi); ++ if (!test_bit(__E1000_DOWN, &adapter->state)) ++ e1000_irq_enable(adapter); ++ + } + + return work_done; + } + ++#endif + /** + * e1000_clean_tx_irq - Reclaim resources after transmit completes + * @adapter: board private structure ++ * ++ * the return value indicates if transmit processing was completed + **/ + static bool e1000_clean_tx_irq(struct e1000_adapter *adapter, +- struct e1000_tx_ring *tx_ring) +-{ +- struct e1000_hw *hw = &adapter->hw; ++ struct e1000_tx_ring *tx_ring) ++{ + struct net_device *netdev = adapter->netdev; + struct e1000_tx_desc *tx_desc, *eop_desc; + struct e1000_buffer *buffer_info; + unsigned int i, eop; ++#ifdef CONFIG_E1000_NAPI + unsigned int count = 0; +- bool cleaned = false; ++#endif ++ bool cleaned = FALSE; ++ bool retval = TRUE; + unsigned int total_tx_bytes=0, total_tx_packets=0; ++ + + i = tx_ring->next_to_clean; + eop = tx_ring->buffer_info[i].next_to_watch; + eop_desc = E1000_TX_DESC(*tx_ring, eop); + + while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) { +- for (cleaned = false; !cleaned; ) { ++ for (cleaned = FALSE; !cleaned; ) { + tx_desc = E1000_TX_DESC(*tx_ring, i); + buffer_info = &tx_ring->buffer_info[i]; + cleaned = (i == eop); + + if (cleaned) { + struct sk_buff *skb = buffer_info->skb; ++#ifdef NETIF_F_TSO + unsigned int segs, bytecount; + segs = skb_shinfo(skb)->gso_segs ?: 1; + /* multiply data chunks by size of headers */ +@@ -3959,19 +3484,26 @@ + skb->len; + total_tx_packets += segs; + total_tx_bytes += bytecount; ++#else ++ total_tx_packets++; ++ total_tx_bytes += skb->len; ++#endif + } + e1000_unmap_and_free_tx_resource(adapter, buffer_info); + tx_desc->upper.data = 0; +- +- if (unlikely(++i == tx_ring->count)) i = 0; ++ E1000_TX_DESC_INC(tx_ring,i); + } + + eop = tx_ring->buffer_info[i].next_to_watch; + eop_desc = E1000_TX_DESC(*tx_ring, eop); ++#ifdef CONFIG_E1000_NAPI + #define E1000_TX_WEIGHT 64 + /* weight of a sort for tx, to avoid endless transmit cleanup */ +- if (count++ == E1000_TX_WEIGHT) +- break; ++ if (count++ == E1000_TX_WEIGHT) { ++ retval = FALSE; ++ break; ++ } ++#endif + } + + tx_ring->next_to_clean = i; +@@ -3983,7 +3515,9 @@ + * sees the new next_to_clean. + */ + smp_mb(); +- if (netif_queue_stopped(netdev)) { ++ ++ if (netif_queue_stopped(netdev) && ++ !(test_bit(__E1000_DOWN, &adapter->state))) { + netif_wake_queue(netdev); + ++adapter->restart_queue; + } +@@ -3992,11 +3526,12 @@ + if (adapter->detect_tx_hung) { + /* Detect a transmit hang in hardware, this serializes the + * check with the clearing of time_stamp and movement of i */ +- adapter->detect_tx_hung = false; ++ adapter->detect_tx_hung = FALSE; + if (tx_ring->buffer_info[eop].dma && + time_after(jiffies, tx_ring->buffer_info[eop].time_stamp + + (adapter->tx_timeout_factor * HZ)) +- && !(er32(STATUS) & E1000_STATUS_TXOFF)) { ++ && !(E1000_READ_REG(&adapter->hw, E1000_STATUS) & ++ E1000_STATUS_TXOFF)) { + + /* detected Tx unit hang */ + DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" +@@ -4012,8 +3547,8 @@ + " next_to_watch.status <%x>\n", + (unsigned long)((tx_ring - adapter->tx_ring) / + sizeof(struct e1000_tx_ring)), +- readl(hw->hw_addr + tx_ring->tdh), +- readl(hw->hw_addr + tx_ring->tdt), ++ readl(adapter->hw.hw_addr + tx_ring->tdh), ++ readl(adapter->hw.hw_addr + tx_ring->tdt), + tx_ring->next_to_use, + tx_ring->next_to_clean, + tx_ring->buffer_info[eop].time_stamp, +@@ -4027,7 +3562,7 @@ + adapter->total_tx_packets += total_tx_packets; + adapter->net_stats.tx_bytes += total_tx_bytes; + adapter->net_stats.tx_packets += total_tx_packets; +- return cleaned; ++ return retval; + } + + /** +@@ -4037,17 +3572,15 @@ + * @csum: receive descriptor csum field + * @sk_buff: socket buffer with received data + **/ +- + static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, +- u32 csum, struct sk_buff *skb) +-{ +- struct e1000_hw *hw = &adapter->hw; ++ u32 csum, struct sk_buff *skb) ++{ + u16 status = (u16)status_err; + u8 errors = (u8)(status_err >> 24); + skb->ip_summed = CHECKSUM_NONE; + + /* 82543 or newer only */ +- if (unlikely(hw->mac_type < e1000_82543)) return; ++ if (unlikely(adapter->hw.mac.type < e1000_82543)) return; + /* Ignore Checksum bit is set */ + if (unlikely(status & E1000_RXD_STAT_IXSM)) return; + /* TCP/UDP checksum error bit is set */ +@@ -4057,7 +3590,7 @@ + return; + } + /* TCP/UDP Checksum has not been calculated */ +- if (hw->mac_type <= e1000_82547_rev_2) { ++ if (adapter->hw.mac.type <= e1000_82547_rev_2) { + if (!(status & E1000_RXD_STAT_TCPCS)) + return; + } else { +@@ -4068,37 +3601,83 @@ + if (likely(status & E1000_RXD_STAT_TCPCS)) { + /* TCP checksum is good */ + skb->ip_summed = CHECKSUM_UNNECESSARY; +- } else if (hw->mac_type > e1000_82547_rev_2) { +- /* IP fragment with UDP payload */ +- /* Hardware complements the payload checksum, so we undo it +- * and then put the value in host order for further stack use. +- */ +- __sum16 sum = (__force __sum16)htons(csum); +- skb->csum = csum_unfold(~sum); +- skb->ip_summed = CHECKSUM_COMPLETE; + } + adapter->hw_csum_good++; + } + + /** +- * e1000_clean_rx_irq - Send received data up the network stack; legacy +- * @adapter: board private structure +- **/ +-static bool e1000_clean_rx_irq(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rx_ring, +- int *work_done, int work_to_do) +-{ +- struct e1000_hw *hw = &adapter->hw; ++ * e1000_receive_skb - helper function to handle rx indications ++ * @adapter: board private structure ++ * @status: descriptor status field as written by hardware ++ * @vlan: descriptor vlan field as written by hardware (no le/be conversion) ++ * @skb: pointer to sk_buff to be indicated to stack ++ **/ ++static void e1000_receive_skb(struct e1000_adapter *adapter, u8 status, ++ u16 vlan, struct sk_buff *skb) ++{ ++#ifdef CONFIG_E1000_NAPI ++#ifdef NETIF_F_HW_VLAN_TX ++ if (unlikely(adapter->vlgrp && (status & E1000_RXD_STAT_VP))) { ++ vlan_hwaccel_receive_skb(skb, adapter->vlgrp, ++ le16_to_cpu(vlan) & ++ E1000_RXD_SPC_VLAN_MASK); ++ } else { ++ netif_receive_skb(skb); ++ } ++#else ++ netif_receive_skb(skb); ++#endif ++#else /* CONFIG_E1000_NAPI */ ++#ifdef NETIF_F_HW_VLAN_TX ++ if (unlikely(adapter->vlgrp && (status & E1000_RXD_STAT_VP))) { ++ vlan_hwaccel_rx(skb, adapter->vlgrp, ++ le16_to_cpu(vlan) & E1000_RXD_SPC_VLAN_MASK); ++ } else { ++ netif_rx(skb); ++ } ++#else ++ netif_rx(skb); ++#endif ++#endif /* CONFIG_E1000_NAPI */ ++} ++ ++#ifdef CONFIG_E1000_NAPI ++/* NOTE: these new jumbo frame routines rely on NAPI because of the ++ * pskb_may_pull call, which eventually must call kmap_atomic which you cannot ++ * call from hard irq context */ ++ ++/** ++ * e1000_consume_page - helper function ++ **/ ++static void e1000_consume_page(struct e1000_rx_buffer *bi, struct sk_buff *skb, ++ u16 length) ++{ ++ bi->page = NULL; ++ skb->len += length; ++ skb->data_len += length; ++ skb->truesize += length; ++} ++ ++/** ++ * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy ++ * @adapter: board private structure ++ * ++ * the return value indicates whether actual cleaning was done, there ++ * is no guarantee that everything was cleaned ++ **/ ++static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter, ++ struct e1000_rx_ring *rx_ring, ++ int *work_done, int work_to_do) ++{ + struct net_device *netdev = adapter->netdev; + struct pci_dev *pdev = adapter->pdev; + struct e1000_rx_desc *rx_desc, *next_rxd; +- struct e1000_buffer *buffer_info, *next_buffer; +- unsigned long flags; ++ struct e1000_rx_buffer *buffer_info, *next_buffer; ++ unsigned long irq_flags; + u32 length; +- u8 last_byte; + unsigned int i; + int cleaned_count = 0; +- bool cleaned = false; ++ bool cleaned = FALSE; + unsigned int total_rx_bytes=0, total_rx_packets=0; + + i = rx_ring->next_to_clean; +@@ -4117,22 +3696,220 @@ + skb = buffer_info->skb; + buffer_info->skb = NULL; + +- prefetch(skb->data - NET_IP_ALIGN); +- + if (++i == rx_ring->count) i = 0; + next_rxd = E1000_RX_DESC(*rx_ring, i); + prefetch(next_rxd); + + next_buffer = &rx_ring->buffer_info[i]; + +- cleaned = true; ++ cleaned = TRUE; ++ cleaned_count++; ++ pci_unmap_page(pdev, ++ buffer_info->dma, ++ PAGE_SIZE, ++ PCI_DMA_FROMDEVICE); ++ buffer_info->dma = 0; ++ ++ length = le16_to_cpu(rx_desc->length); ++ ++ /* errors is only valid for DD + EOP descriptors */ ++ if (unlikely((status & E1000_RXD_STAT_EOP) && ++ (rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK))) { ++ u8 last_byte = *(skb->data + length - 1); ++ if (TBI_ACCEPT(&adapter->hw, status, ++ rx_desc->errors, length, last_byte, ++ adapter->min_frame_size, ++ adapter->max_frame_size)) { ++ spin_lock_irqsave(&adapter->stats_lock, ++ irq_flags); ++ e1000_tbi_adjust_stats_82543(&adapter->hw, ++ &adapter->stats, ++ length, skb->data, ++ adapter->max_frame_size); ++ spin_unlock_irqrestore(&adapter->stats_lock, ++ irq_flags); ++ length--; ++ } else { ++ /* recycle both page and skb */ ++ buffer_info->skb = skb; ++ /* an error means any chain goes out the window ++ * too */ ++ if (rx_ring->rx_skb_top) ++ dev_kfree_skb(rx_ring->rx_skb_top); ++ rx_ring->rx_skb_top = NULL; ++ goto next_desc; ++ } ++ } ++ ++#define rxtop rx_ring->rx_skb_top ++ if (!(status & E1000_RXD_STAT_EOP)) { ++ /* this descriptor is only the beginning (or middle) */ ++ if (!rxtop) { ++ /* this is the beginning of a chain */ ++ rxtop = skb; ++ skb_fill_page_desc(rxtop, 0, buffer_info->page, ++ 0, length); ++ } else { ++ /* this is the middle of a chain */ ++ skb_fill_page_desc(rxtop, ++ skb_shinfo(rxtop)->nr_frags, ++ buffer_info->page, 0, length); ++ /* re-use the skb, only consumed the page */ ++ buffer_info->skb = skb; ++ } ++ e1000_consume_page(buffer_info, rxtop, length); ++ goto next_desc; ++ } else { ++ if (rxtop) { ++ /* end of the chain */ ++ skb_fill_page_desc(rxtop, ++ skb_shinfo(rxtop)->nr_frags, ++ buffer_info->page, 0, length); ++ /* re-use the current skb, we only consumed the ++ * page */ ++ buffer_info->skb = skb; ++ skb = rxtop; ++ rxtop = NULL; ++ e1000_consume_page(buffer_info, skb, length); ++ } else { ++ /* no chain, got EOP, this buf is the packet ++ * copybreak to save the put_page/alloc_page */ ++ if (length <= copybreak && ++ skb_tailroom(skb) >= length) { ++ u8 *vaddr; ++ vaddr = kmap_atomic(buffer_info->page, ++ KM_SKB_DATA_SOFTIRQ); ++ memcpy(skb_tail_pointer(skb), vaddr, length); ++ kunmap_atomic(vaddr, ++ KM_SKB_DATA_SOFTIRQ); ++ /* re-use the page, so don't erase ++ * buffer_info->page */ ++ skb_put(skb, length); ++ } else { ++ skb_fill_page_desc(skb, 0, ++ buffer_info->page, 0, ++ length); ++ e1000_consume_page(buffer_info, skb, ++ length); ++ } ++ } ++ } ++ ++ /* Receive Checksum Offload XXX recompute due to CRC strip? */ ++ e1000_rx_checksum(adapter, ++ (u32)(status) | ++ ((u32)(rx_desc->errors) << 24), ++ le16_to_cpu(rx_desc->csum), skb); ++ ++ pskb_trim(skb, skb->len - 4); ++ ++ /* probably a little skewed due to removing CRC */ ++ total_rx_bytes += skb->len; ++ total_rx_packets++; ++ ++ /* eth type trans needs skb->data to point to something */ ++ if (!pskb_may_pull(skb, ETH_HLEN)) { ++ DPRINTK(DRV, ERR, "__pskb_pull_tail failed.\n"); ++ dev_kfree_skb(skb); ++ goto next_desc; ++ } ++ ++ skb->protocol = eth_type_trans(skb, netdev); ++ ++ e1000_receive_skb(adapter, status, rx_desc->special, skb); ++ ++ netdev->last_rx = jiffies; ++ ++next_desc: ++ rx_desc->status = 0; ++ ++ /* return some buffers to hardware, one at a time is too slow */ ++ if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { ++ adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count); ++ cleaned_count = 0; ++ } ++ ++ /* use prefetched values */ ++ rx_desc = next_rxd; ++ buffer_info = next_buffer; ++ } ++ rx_ring->next_to_clean = i; ++ ++ cleaned_count = E1000_DESC_UNUSED(rx_ring); ++ if (cleaned_count) ++ adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count); ++ ++ adapter->total_rx_packets += total_rx_packets; ++ adapter->total_rx_bytes += total_rx_bytes; ++ adapter->net_stats.rx_bytes += total_rx_bytes; ++ adapter->net_stats.rx_packets += total_rx_packets; ++ return cleaned; ++} ++#endif /* NAPI */ ++ ++ ++/** ++ * e1000_clean_rx_irq - Send received data up the network stack; legacy ++ * @adapter: board private structure ++ * ++ * the return value indicates whether actual cleaning was done, there ++ * is no guarantee that everything was cleaned ++ **/ ++#ifdef CONFIG_E1000_NAPI ++static bool e1000_clean_rx_irq(struct e1000_adapter *adapter, ++ struct e1000_rx_ring *rx_ring, ++ int *work_done, int work_to_do) ++#else ++static bool e1000_clean_rx_irq(struct e1000_adapter *adapter, ++ struct e1000_rx_ring *rx_ring) ++#endif ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct pci_dev *pdev = adapter->pdev; ++ struct e1000_rx_desc *rx_desc, *next_rxd; ++ struct e1000_rx_buffer *buffer_info, *next_buffer; ++ unsigned long irq_flags; ++ u32 length; ++ unsigned int i; ++ int cleaned_count = 0; ++ bool cleaned = FALSE; ++ unsigned int total_rx_bytes=0, total_rx_packets=0; ++ ++ i = rx_ring->next_to_clean; ++ rx_desc = E1000_RX_DESC(*rx_ring, i); ++ buffer_info = &rx_ring->buffer_info[i]; ++ ++ while (rx_desc->status & E1000_RXD_STAT_DD) { ++ struct sk_buff *skb; ++ u8 status; ++ ++#ifdef CONFIG_E1000_NAPI ++ if (*work_done >= work_to_do) ++ break; ++ (*work_done)++; ++#endif ++ status = rx_desc->status; ++ skb = buffer_info->skb; ++ buffer_info->skb = NULL; ++ ++ prefetch(skb->data - NET_IP_ALIGN); ++ ++ if (++i == rx_ring->count) i = 0; ++ next_rxd = E1000_RX_DESC(*rx_ring, i); ++ prefetch(next_rxd); ++ ++ next_buffer = &rx_ring->buffer_info[i]; ++ ++ cleaned = TRUE; + cleaned_count++; + pci_unmap_single(pdev, + buffer_info->dma, +- buffer_info->length, ++ adapter->rx_buffer_len, + PCI_DMA_FROMDEVICE); ++ buffer_info->dma = 0; + + length = le16_to_cpu(rx_desc->length); ++ + /* !EOP means multiple descriptors were used to store a single + * packet, also make sure the frame isn't just CRC only */ + if (unlikely(!(status & E1000_RXD_STAT_EOP) || (length <= 4))) { +@@ -4145,14 +3922,19 @@ + } + + if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) { +- last_byte = *(skb->data + length - 1); +- if (TBI_ACCEPT(hw, status, rx_desc->errors, length, +- last_byte)) { +- spin_lock_irqsave(&adapter->stats_lock, flags); +- e1000_tbi_adjust_stats(hw, &adapter->stats, +- length, skb->data); ++ u8 last_byte = *(skb->data + length - 1); ++ if (TBI_ACCEPT(&adapter->hw, status, ++ rx_desc->errors, length, last_byte, ++ adapter->min_frame_size, ++ adapter->max_frame_size)) { ++ spin_lock_irqsave(&adapter->stats_lock, ++ irq_flags); ++ e1000_tbi_adjust_stats_82543(&adapter->hw, ++ &adapter->stats, ++ length, skb->data, ++ adapter->max_frame_size); + spin_unlock_irqrestore(&adapter->stats_lock, +- flags); ++ irq_flags); + length--; + } else { + /* recycle */ +@@ -4178,11 +3960,11 @@ + if (new_skb) { + skb_reserve(new_skb, NET_IP_ALIGN); + skb_copy_to_linear_data_offset(new_skb, +- -NET_IP_ALIGN, +- (skb->data - +- NET_IP_ALIGN), +- (length + +- NET_IP_ALIGN)); ++ -NET_IP_ALIGN, ++ (skb->data - ++ NET_IP_ALIGN), ++ (length + ++ NET_IP_ALIGN)); + /* save the skb in buffer_info as good */ + buffer_info->skb = skb; + skb = new_skb; +@@ -4200,13 +3982,7 @@ + + skb->protocol = eth_type_trans(skb, netdev); + +- if (unlikely(adapter->vlgrp && +- (status & E1000_RXD_STAT_VP))) { +- vlan_hwaccel_receive_skb(skb, adapter->vlgrp, +- le16_to_cpu(rx_desc->special)); +- } else { +- netif_receive_skb(skb); +- } ++ e1000_receive_skb(adapter, status, rx_desc->special, skb); + + netdev->last_rx = jiffies; + +@@ -4236,191 +4012,127 @@ + return cleaned; + } + +-/** +- * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split +- * @adapter: board private structure +- **/ +- +-static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rx_ring, +- int *work_done, int work_to_do) +-{ +- union e1000_rx_desc_packet_split *rx_desc, *next_rxd; +- struct net_device *netdev = adapter->netdev; +- struct pci_dev *pdev = adapter->pdev; +- struct e1000_buffer *buffer_info, *next_buffer; +- struct e1000_ps_page *ps_page; +- struct e1000_ps_page_dma *ps_page_dma; ++#ifdef CONFIG_E1000_NAPI ++/** ++ * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers ++ * @adapter: address of board private structure ++ * @rx_ring: pointer to receive ring structure ++ * @cleaned_count: number of buffers to allocate this pass ++ **/ ++static void e1000_alloc_jumbo_rx_buffers(struct e1000_adapter *adapter, ++ struct e1000_rx_ring *rx_ring, ++ int cleaned_count) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct pci_dev *pdev = adapter->pdev; ++ struct e1000_rx_desc *rx_desc; ++ struct e1000_rx_buffer *buffer_info; + struct sk_buff *skb; +- unsigned int i, j; +- u32 length, staterr; +- int cleaned_count = 0; +- bool cleaned = false; +- unsigned int total_rx_bytes=0, total_rx_packets=0; +- +- i = rx_ring->next_to_clean; +- rx_desc = E1000_RX_DESC_PS(*rx_ring, i); +- staterr = le32_to_cpu(rx_desc->wb.middle.status_error); ++ unsigned int i; ++ unsigned int bufsz = 256 - ++ 16 /*for skb_reserve */ - ++ NET_IP_ALIGN; ++ ++ i = rx_ring->next_to_use; + buffer_info = &rx_ring->buffer_info[i]; + +- while (staterr & E1000_RXD_STAT_DD) { +- ps_page = &rx_ring->ps_page[i]; +- ps_page_dma = &rx_ring->ps_page_dma[i]; +- +- if (unlikely(*work_done >= work_to_do)) +- break; +- (*work_done)++; +- ++ while (cleaned_count--) { + skb = buffer_info->skb; +- +- /* in the packet split case this is header only */ +- prefetch(skb->data - NET_IP_ALIGN); +- +- if (++i == rx_ring->count) i = 0; +- next_rxd = E1000_RX_DESC_PS(*rx_ring, i); +- prefetch(next_rxd); +- +- next_buffer = &rx_ring->buffer_info[i]; +- +- cleaned = true; +- cleaned_count++; +- pci_unmap_single(pdev, buffer_info->dma, +- buffer_info->length, +- PCI_DMA_FROMDEVICE); +- +- if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) { +- E1000_DBG("%s: Packet Split buffers didn't pick up" +- " the full packet\n", netdev->name); +- dev_kfree_skb_irq(skb); +- goto next_desc; +- } +- +- if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) { +- dev_kfree_skb_irq(skb); +- goto next_desc; +- } +- +- length = le16_to_cpu(rx_desc->wb.middle.length0); +- +- if (unlikely(!length)) { +- E1000_DBG("%s: Last part of the packet spanning" +- " multiple descriptors\n", netdev->name); +- dev_kfree_skb_irq(skb); +- goto next_desc; +- } +- +- /* Good Receive */ +- skb_put(skb, length); +- +- { +- /* this looks ugly, but it seems compiler issues make it +- more efficient than reusing j */ +- int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); +- +- /* page alloc/put takes too long and effects small packet +- * throughput, so unsplit small packets and save the alloc/put*/ +- if (l1 && (l1 <= copybreak) && ((length + l1) <= adapter->rx_ps_bsize0)) { +- u8 *vaddr; +- /* there is no documentation about how to call +- * kmap_atomic, so we can't hold the mapping +- * very long */ +- pci_dma_sync_single_for_cpu(pdev, +- ps_page_dma->ps_page_dma[0], +- PAGE_SIZE, +- PCI_DMA_FROMDEVICE); +- vaddr = kmap_atomic(ps_page->ps_page[0], +- KM_SKB_DATA_SOFTIRQ); +- memcpy(skb_tail_pointer(skb), vaddr, l1); +- kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ); +- pci_dma_sync_single_for_device(pdev, +- ps_page_dma->ps_page_dma[0], +- PAGE_SIZE, PCI_DMA_FROMDEVICE); +- /* remove the CRC */ +- l1 -= 4; +- skb_put(skb, l1); +- goto copydone; +- } /* if */ +- } +- +- for (j = 0; j < adapter->rx_ps_pages; j++) { +- length = le16_to_cpu(rx_desc->wb.upper.length[j]); +- if (!length) +- break; +- pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j], +- PAGE_SIZE, PCI_DMA_FROMDEVICE); +- ps_page_dma->ps_page_dma[j] = 0; +- skb_add_rx_frag(skb, j, ps_page->ps_page[j], 0, length); +- ps_page->ps_page[j] = NULL; +- } +- +- /* strip the ethernet crc, problem is we're using pages now so +- * this whole operation can get a little cpu intensive */ +- pskb_trim(skb, skb->len - 4); +- +-copydone: +- total_rx_bytes += skb->len; +- total_rx_packets++; +- +- e1000_rx_checksum(adapter, staterr, +- le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb); +- skb->protocol = eth_type_trans(skb, netdev); +- +- if (likely(rx_desc->wb.upper.header_status & +- cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))) +- adapter->rx_hdr_split++; +- +- if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) { +- vlan_hwaccel_receive_skb(skb, adapter->vlgrp, +- le16_to_cpu(rx_desc->wb.middle.vlan)); +- } else { +- netif_receive_skb(skb); +- } +- +- netdev->last_rx = jiffies; +- +-next_desc: +- rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); +- buffer_info->skb = NULL; +- +- /* return some buffers to hardware, one at a time is too slow */ +- if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { +- adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count); +- cleaned_count = 0; +- } +- +- /* use prefetched values */ +- rx_desc = next_rxd; +- buffer_info = next_buffer; +- +- staterr = le32_to_cpu(rx_desc->wb.middle.status_error); +- } +- rx_ring->next_to_clean = i; +- +- cleaned_count = E1000_DESC_UNUSED(rx_ring); +- if (cleaned_count) +- adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count); +- +- adapter->total_rx_packets += total_rx_packets; +- adapter->total_rx_bytes += total_rx_bytes; +- adapter->net_stats.rx_bytes += total_rx_bytes; +- adapter->net_stats.rx_packets += total_rx_packets; +- return cleaned; +-} ++ if (skb) { ++ skb_trim(skb, 0); ++ goto check_page; ++ } ++ ++ skb = netdev_alloc_skb(netdev, bufsz); ++ if (unlikely(!skb)) { ++ /* Better luck next round */ ++ adapter->alloc_rx_buff_failed++; ++ break; ++ } ++ ++ /* Fix for errata 23, can't cross 64kB boundary */ ++ if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) { ++ struct sk_buff *oldskb = skb; ++ DPRINTK(PROBE, ERR, "skb align check failed: %u bytes " ++ "at %p\n", bufsz, skb->data); ++ /* Try again, without freeing the previous */ ++ skb = netdev_alloc_skb(netdev, bufsz); ++ /* Failed allocation, critical failure */ ++ if (!skb) { ++ dev_kfree_skb(oldskb); ++ adapter->alloc_rx_buff_failed++; ++ break; ++ } ++ ++ if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) { ++ /* give up */ ++ dev_kfree_skb(skb); ++ dev_kfree_skb(oldskb); ++ adapter->alloc_rx_buff_failed++; ++ break; /* while !buffer_info->skb */ ++ } ++ ++ /* Use new allocation */ ++ dev_kfree_skb(oldskb); ++ } ++ /* Make buffer alignment 2 beyond a 16 byte boundary ++ * this will result in a 16 byte aligned IP header after ++ * the 14 byte MAC header is removed ++ */ ++ skb_reserve(skb, NET_IP_ALIGN); ++ ++ buffer_info->skb = skb; ++check_page: ++ /* allocate a new page if necessary */ ++ if (!buffer_info->page) { ++ buffer_info->page = alloc_page(GFP_ATOMIC); ++ if (unlikely(!buffer_info->page)) { ++ adapter->alloc_rx_buff_failed++; ++ break; ++ } ++ } ++ ++ if (!buffer_info->dma) ++ buffer_info->dma = pci_map_page(pdev, ++ buffer_info->page, 0, ++ PAGE_SIZE, ++ PCI_DMA_FROMDEVICE); ++ ++ rx_desc = E1000_RX_DESC(*rx_ring, i); ++ rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); ++ ++ if (unlikely(++i == rx_ring->count)) ++ i = 0; ++ buffer_info = &rx_ring->buffer_info[i]; ++ } ++ ++ if (likely(rx_ring->next_to_use != i)) { ++ rx_ring->next_to_use = i; ++ if (unlikely(i-- == 0)) ++ i = (rx_ring->count - 1); ++ ++ /* Force memory writes to complete before letting h/w ++ * know there are new descriptors to fetch. (Only ++ * applicable for weak-ordered memory model archs, ++ * such as IA-64). */ ++ wmb(); ++ writel(i, adapter->hw.hw_addr + rx_ring->rdt); ++ } ++} ++#endif /* NAPI */ + + /** + * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended + * @adapter: address of board private structure + **/ +- + static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rx_ring, +- int cleaned_count) +-{ +- struct e1000_hw *hw = &adapter->hw; ++ struct e1000_rx_ring *rx_ring, ++ int cleaned_count) ++{ + struct net_device *netdev = adapter->netdev; + struct pci_dev *pdev = adapter->pdev; + struct e1000_rx_desc *rx_desc; +- struct e1000_buffer *buffer_info; ++ struct e1000_rx_buffer *buffer_info; + struct sk_buff *skb; + unsigned int i; + unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN; +@@ -4452,6 +4164,7 @@ + /* Failed allocation, critical failure */ + if (!skb) { + dev_kfree_skb(oldskb); ++ adapter->alloc_rx_buff_failed++; + break; + } + +@@ -4459,6 +4172,7 @@ + /* give up */ + dev_kfree_skb(skb); + dev_kfree_skb(oldskb); ++ adapter->alloc_rx_buff_failed++; + break; /* while !buffer_info->skb */ + } + +@@ -4472,7 +4186,6 @@ + skb_reserve(skb, NET_IP_ALIGN); + + buffer_info->skb = skb; +- buffer_info->length = adapter->rx_buffer_len; + map_skb: + buffer_info->dma = pci_map_single(pdev, + skb->data, +@@ -4493,7 +4206,9 @@ + pci_unmap_single(pdev, buffer_info->dma, + adapter->rx_buffer_len, + PCI_DMA_FROMDEVICE); +- ++ buffer_info->dma = 0; ++ ++ adapter->alloc_rx_buff_failed++; + break; /* while !buffer_info->skb */ + } + rx_desc = E1000_RX_DESC(*rx_ring, i); +@@ -4514,105 +4229,7 @@ + * applicable for weak-ordered memory model archs, + * such as IA-64). */ + wmb(); +- writel(i, hw->hw_addr + rx_ring->rdt); +- } +-} +- +-/** +- * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split +- * @adapter: address of board private structure +- **/ +- +-static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter, +- struct e1000_rx_ring *rx_ring, +- int cleaned_count) +-{ +- struct e1000_hw *hw = &adapter->hw; +- struct net_device *netdev = adapter->netdev; +- struct pci_dev *pdev = adapter->pdev; +- union e1000_rx_desc_packet_split *rx_desc; +- struct e1000_buffer *buffer_info; +- struct e1000_ps_page *ps_page; +- struct e1000_ps_page_dma *ps_page_dma; +- struct sk_buff *skb; +- unsigned int i, j; +- +- i = rx_ring->next_to_use; +- buffer_info = &rx_ring->buffer_info[i]; +- ps_page = &rx_ring->ps_page[i]; +- ps_page_dma = &rx_ring->ps_page_dma[i]; +- +- while (cleaned_count--) { +- rx_desc = E1000_RX_DESC_PS(*rx_ring, i); +- +- for (j = 0; j < PS_PAGE_BUFFERS; j++) { +- if (j < adapter->rx_ps_pages) { +- if (likely(!ps_page->ps_page[j])) { +- ps_page->ps_page[j] = +- netdev_alloc_page(netdev); +- if (unlikely(!ps_page->ps_page[j])) { +- adapter->alloc_rx_buff_failed++; +- goto no_buffers; +- } +- ps_page_dma->ps_page_dma[j] = +- pci_map_page(pdev, +- ps_page->ps_page[j], +- 0, PAGE_SIZE, +- PCI_DMA_FROMDEVICE); +- } +- /* Refresh the desc even if buffer_addrs didn't +- * change because each write-back erases +- * this info. +- */ +- rx_desc->read.buffer_addr[j+1] = +- cpu_to_le64(ps_page_dma->ps_page_dma[j]); +- } else +- rx_desc->read.buffer_addr[j+1] = ~cpu_to_le64(0); +- } +- +- skb = netdev_alloc_skb(netdev, +- adapter->rx_ps_bsize0 + NET_IP_ALIGN); +- +- if (unlikely(!skb)) { +- adapter->alloc_rx_buff_failed++; +- break; +- } +- +- /* Make buffer alignment 2 beyond a 16 byte boundary +- * this will result in a 16 byte aligned IP header after +- * the 14 byte MAC header is removed +- */ +- skb_reserve(skb, NET_IP_ALIGN); +- +- buffer_info->skb = skb; +- buffer_info->length = adapter->rx_ps_bsize0; +- buffer_info->dma = pci_map_single(pdev, skb->data, +- adapter->rx_ps_bsize0, +- PCI_DMA_FROMDEVICE); +- +- rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); +- +- if (unlikely(++i == rx_ring->count)) i = 0; +- buffer_info = &rx_ring->buffer_info[i]; +- ps_page = &rx_ring->ps_page[i]; +- ps_page_dma = &rx_ring->ps_page_dma[i]; +- } +- +-no_buffers: +- if (likely(rx_ring->next_to_use != i)) { +- rx_ring->next_to_use = i; +- if (unlikely(i-- == 0)) i = (rx_ring->count - 1); +- +- /* Force memory writes to complete before letting h/w +- * know there are new descriptors to fetch. (Only +- * applicable for weak-ordered memory model archs, +- * such as IA-64). */ +- wmb(); +- /* Hardware increments by 16 bytes, but packet split +- * descriptors are 32 bytes...so we increment tail +- * twice as much. +- */ +- writel(i<<1, hw->hw_addr + rx_ring->rdt); ++ writel(i, adapter->hw.hw_addr + rx_ring->rdt); + } + } + +@@ -4620,50 +4237,50 @@ + * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers. + * @adapter: + **/ +- + static void e1000_smartspeed(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; ++ struct e1000_mac_info *mac = &adapter->hw.mac; ++ struct e1000_phy_info *phy = &adapter->hw.phy; + u16 phy_status; + u16 phy_ctrl; + +- if ((hw->phy_type != e1000_phy_igp) || !hw->autoneg || +- !(hw->autoneg_advertised & ADVERTISE_1000_FULL)) ++ if ((phy->type != e1000_phy_igp) || !mac->autoneg || ++ !(phy->autoneg_advertised & ADVERTISE_1000_FULL)) + return; + + if (adapter->smartspeed == 0) { + /* If Master/Slave config fault is asserted twice, + * we assume back-to-back */ +- e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); ++ e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status); + if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return; +- e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); ++ e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status); + if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return; +- e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); ++ e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl); + if (phy_ctrl & CR_1000T_MS_ENABLE) { + phy_ctrl &= ~CR_1000T_MS_ENABLE; +- e1000_write_phy_reg(hw, PHY_1000T_CTRL, ++ e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, + phy_ctrl); + adapter->smartspeed++; +- if (!e1000_phy_setup_autoneg(hw) && +- !e1000_read_phy_reg(hw, PHY_CTRL, ++ if (!e1000_phy_setup_autoneg(&adapter->hw) && ++ !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, + &phy_ctrl)) { + phy_ctrl |= (MII_CR_AUTO_NEG_EN | + MII_CR_RESTART_AUTO_NEG); +- e1000_write_phy_reg(hw, PHY_CTRL, ++ e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, + phy_ctrl); + } + } + return; + } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { + /* If still no link, perhaps using 2/3 pair cable */ +- e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); ++ e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl); + phy_ctrl |= CR_1000T_MS_ENABLE; +- e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); +- if (!e1000_phy_setup_autoneg(hw) && +- !e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl)) { ++ e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl); ++ if (!e1000_phy_setup_autoneg(&adapter->hw) && ++ !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_ctrl)) { + phy_ctrl |= (MII_CR_AUTO_NEG_EN | + MII_CR_RESTART_AUTO_NEG); +- e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl); ++ e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_ctrl); + } + } + /* Restart process after E1000_SMARTSPEED_MAX iterations */ +@@ -4677,120 +4294,89 @@ + * @ifreq: + * @cmd: + **/ +- + static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) + { + switch (cmd) { ++#ifdef SIOCGMIIPHY + case SIOCGMIIPHY: + case SIOCGMIIREG: + case SIOCSMIIREG: + return e1000_mii_ioctl(netdev, ifr, cmd); ++#endif ++#ifdef ETHTOOL_OPS_COMPAT ++ case SIOCETHTOOL: ++ return ethtool_ioctl(ifr); ++#endif + default: + return -EOPNOTSUPP; + } + } + ++#ifdef SIOCGMIIPHY + /** + * e1000_mii_ioctl - + * @netdev: + * @ifreq: + * @cmd: + **/ +- + static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, +- int cmd) +-{ +- struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; ++ int cmd) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); + struct mii_ioctl_data *data = if_mii(ifr); +- int retval; +- u16 mii_reg; +- u16 spddplx; +- unsigned long flags; +- +- if (hw->media_type != e1000_media_type_copper) ++ ++ if (adapter->hw.phy.media_type != e1000_media_type_copper) + return -EOPNOTSUPP; + + switch (cmd) { + case SIOCGMIIPHY: +- data->phy_id = hw->phy_addr; ++ data->phy_id = adapter->hw.phy.addr; + break; + case SIOCGMIIREG: + if (!capable(CAP_NET_ADMIN)) + return -EPERM; +- spin_lock_irqsave(&adapter->stats_lock, flags); +- if (e1000_read_phy_reg(hw, data->reg_num & 0x1F, +- &data->val_out)) { +- spin_unlock_irqrestore(&adapter->stats_lock, flags); ++ switch (data->reg_num & 0x1F) { ++ case MII_BMCR: ++ data->val_out = adapter->phy_regs.bmcr; ++ break; ++ case MII_BMSR: ++ data->val_out = adapter->phy_regs.bmsr; ++ break; ++ case MII_PHYSID1: ++ data->val_out = (adapter->hw.phy.id >> 16); ++ break; ++ case MII_PHYSID2: ++ data->val_out = (adapter->hw.phy.id & 0xFFFF); ++ break; ++ case MII_ADVERTISE: ++ data->val_out = adapter->phy_regs.advertise; ++ break; ++ case MII_LPA: ++ data->val_out = adapter->phy_regs.lpa; ++ break; ++ case MII_EXPANSION: ++ data->val_out = adapter->phy_regs.expansion; ++ break; ++ case MII_CTRL1000: ++ data->val_out = adapter->phy_regs.ctrl1000; ++ break; ++ case MII_STAT1000: ++ data->val_out = adapter->phy_regs.stat1000; ++ break; ++ case MII_ESTATUS: ++ data->val_out = adapter->phy_regs.estatus; ++ break; ++ default: + return -EIO; + } +- spin_unlock_irqrestore(&adapter->stats_lock, flags); + break; + case SIOCSMIIREG: +- if (!capable(CAP_NET_ADMIN)) +- return -EPERM; +- if (data->reg_num & ~(0x1F)) +- return -EFAULT; +- mii_reg = data->val_in; +- spin_lock_irqsave(&adapter->stats_lock, flags); +- if (e1000_write_phy_reg(hw, data->reg_num, +- mii_reg)) { +- spin_unlock_irqrestore(&adapter->stats_lock, flags); +- return -EIO; +- } +- spin_unlock_irqrestore(&adapter->stats_lock, flags); +- if (hw->media_type == e1000_media_type_copper) { +- switch (data->reg_num) { +- case PHY_CTRL: +- if (mii_reg & MII_CR_POWER_DOWN) +- break; +- if (mii_reg & MII_CR_AUTO_NEG_EN) { +- hw->autoneg = 1; +- hw->autoneg_advertised = 0x2F; +- } else { +- if (mii_reg & 0x40) +- spddplx = SPEED_1000; +- else if (mii_reg & 0x2000) +- spddplx = SPEED_100; +- else +- spddplx = SPEED_10; +- spddplx += (mii_reg & 0x100) +- ? DUPLEX_FULL : +- DUPLEX_HALF; +- retval = e1000_set_spd_dplx(adapter, +- spddplx); +- if (retval) +- return retval; +- } +- if (netif_running(adapter->netdev)) +- e1000_reinit_locked(adapter); +- else +- e1000_reset(adapter); +- break; +- case M88E1000_PHY_SPEC_CTRL: +- case M88E1000_EXT_PHY_SPEC_CTRL: +- if (e1000_phy_reset(hw)) +- return -EIO; +- break; +- } +- } else { +- switch (data->reg_num) { +- case PHY_CTRL: +- if (mii_reg & MII_CR_POWER_DOWN) +- break; +- if (netif_running(adapter->netdev)) +- e1000_reinit_locked(adapter); +- else +- e1000_reset(adapter); +- break; +- } +- } +- break; + default: + return -EOPNOTSUPP; + } + return E1000_SUCCESS; + } ++#endif + + void e1000_pci_set_mwi(struct e1000_hw *hw) + { +@@ -4808,123 +4394,118 @@ + pci_clear_mwi(adapter->pdev); + } + +-int e1000_pcix_get_mmrbc(struct e1000_hw *hw) +-{ +- struct e1000_adapter *adapter = hw->back; +- return pcix_get_mmrbc(adapter->pdev); +-} +- +-void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc) +-{ +- struct e1000_adapter *adapter = hw->back; +- pcix_set_mmrbc(adapter->pdev, mmrbc); ++void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) ++{ ++ struct e1000_adapter *adapter = hw->back; ++ ++ pci_read_config_word(adapter->pdev, reg, value); ++} ++ ++void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) ++{ ++ struct e1000_adapter *adapter = hw->back; ++ ++ pci_write_config_word(adapter->pdev, reg, *value); + } + + s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) + { +- struct e1000_adapter *adapter = hw->back; +- u16 cap_offset; +- +- cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); +- if (!cap_offset) +- return -E1000_ERR_CONFIG; +- +- pci_read_config_word(adapter->pdev, cap_offset + reg, value); +- +- return E1000_SUCCESS; +-} +- +-void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value) +-{ +- outl(value, port); +-} +- ++ struct e1000_adapter *adapter = hw->back; ++ u16 cap_offset; ++ ++ cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); ++ if (!cap_offset) ++ return -E1000_ERR_CONFIG; ++ ++ pci_read_config_word(adapter->pdev, cap_offset + reg, value); ++ ++ return E1000_SUCCESS; ++} ++ ++#ifdef NETIF_F_HW_VLAN_TX + static void e1000_vlan_rx_register(struct net_device *netdev, +- struct vlan_group *grp) +-{ +- struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; ++ struct vlan_group *grp) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); + u32 ctrl, rctl; + +- if (!test_bit(__E1000_DOWN, &adapter->flags)) ++ if (!test_bit(__E1000_DOWN, &adapter->state)) + e1000_irq_disable(adapter); + adapter->vlgrp = grp; + + if (grp) { + /* enable VLAN tag insert/strip */ +- ctrl = er32(CTRL); ++ ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); + ctrl |= E1000_CTRL_VME; +- ew32(CTRL, ctrl); +- +- if (adapter->hw.mac_type != e1000_ich8lan) { +- /* enable VLAN receive filtering */ +- rctl = er32(RCTL); +- rctl &= ~E1000_RCTL_CFIEN; +- ew32(RCTL, rctl); +- e1000_update_mng_vlan(adapter); +- } ++ E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); ++ ++ /* enable VLAN receive filtering */ ++ rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); ++ if (!(netdev->flags & IFF_PROMISC)) ++ rctl |= E1000_RCTL_VFE; ++ rctl &= ~E1000_RCTL_CFIEN; ++ E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); ++ e1000_update_mng_vlan(adapter); + } else { + /* disable VLAN tag insert/strip */ +- ctrl = er32(CTRL); ++ ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); + ctrl &= ~E1000_CTRL_VME; +- ew32(CTRL, ctrl); +- +- if (adapter->hw.mac_type != e1000_ich8lan) { +- if (adapter->mng_vlan_id != +- (u16)E1000_MNG_VLAN_NONE) { +- e1000_vlan_rx_kill_vid(netdev, +- adapter->mng_vlan_id); +- adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; +- } +- } +- } +- +- if (!test_bit(__E1000_DOWN, &adapter->flags)) ++ E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); ++ ++ /* disable VLAN filtering */ ++ rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); ++ rctl &= ~E1000_RCTL_VFE; ++ E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); ++ if (adapter->mng_vlan_id != ++ (u16)E1000_MNG_VLAN_NONE) { ++ e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); ++ adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; ++ } ++ } ++ ++ if (!test_bit(__E1000_DOWN, &adapter->state)) + e1000_irq_enable(adapter); + } + + static void e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; + u32 vfta, index; +- +- if ((hw->mng_cookie.status & +- E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) && ++ struct net_device *v_netdev; ++ ++ if ((adapter->hw.mng_cookie.status & ++ E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && + (vid == adapter->mng_vlan_id)) + return; + /* add VID to filter table */ + index = (vid >> 5) & 0x7F; +- vfta = E1000_READ_REG_ARRAY(hw, VFTA, index); ++ vfta = E1000_READ_REG_ARRAY(&adapter->hw, E1000_VFTA, index); + vfta |= (1 << (vid & 0x1F)); +- e1000_write_vfta(hw, index, vfta); ++ e1000_write_vfta(&adapter->hw, index, vfta); ++ /* Copy feature flags from netdev to the vlan netdev for this vid. ++ * This allows things like TSO to bubble down to our vlan device. ++ */ ++ v_netdev = vlan_group_get_device(adapter->vlgrp, vid); ++ v_netdev->features |= adapter->netdev->features; ++ vlan_group_set_device(adapter->vlgrp, vid, v_netdev); + } + + static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; + u32 vfta, index; + +- if (!test_bit(__E1000_DOWN, &adapter->flags)) ++ if (!test_bit(__E1000_DOWN, &adapter->state)) + e1000_irq_disable(adapter); + vlan_group_set_device(adapter->vlgrp, vid, NULL); +- if (!test_bit(__E1000_DOWN, &adapter->flags)) ++ if (!test_bit(__E1000_DOWN, &adapter->state)) + e1000_irq_enable(adapter); +- +- if ((hw->mng_cookie.status & +- E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) && +- (vid == adapter->mng_vlan_id)) { +- /* release control to f/w */ +- e1000_release_hw_control(adapter); +- return; +- } + + /* remove VID from filter table */ + index = (vid >> 5) & 0x7F; +- vfta = E1000_READ_REG_ARRAY(hw, VFTA, index); ++ vfta = E1000_READ_REG_ARRAY(&adapter->hw, E1000_VFTA, index); + vfta &= ~(1 << (vid & 0x1F)); +- e1000_write_vfta(hw, index, vfta); ++ e1000_write_vfta(&adapter->hw, index, vfta); + } + + static void e1000_restore_vlan(struct e1000_adapter *adapter) +@@ -4940,15 +4521,16 @@ + } + } + } ++#endif + + int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx) + { +- struct e1000_hw *hw = &adapter->hw; +- +- hw->autoneg = 0; ++ struct e1000_mac_info *mac = &adapter->hw.mac; ++ ++ mac->autoneg = 0; + + /* Fiber NICs only allow 1000 gbps Full duplex */ +- if ((hw->media_type == e1000_media_type_fiber) && ++ if ((adapter->hw.phy.media_type == e1000_media_type_fiber) && + spddplx != (SPEED_1000 + DUPLEX_FULL)) { + DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n"); + return -EINVAL; +@@ -4956,20 +4538,20 @@ + + switch (spddplx) { + case SPEED_10 + DUPLEX_HALF: +- hw->forced_speed_duplex = e1000_10_half; ++ mac->forced_speed_duplex = ADVERTISE_10_HALF; + break; + case SPEED_10 + DUPLEX_FULL: +- hw->forced_speed_duplex = e1000_10_full; ++ mac->forced_speed_duplex = ADVERTISE_10_FULL; + break; + case SPEED_100 + DUPLEX_HALF: +- hw->forced_speed_duplex = e1000_100_half; ++ mac->forced_speed_duplex = ADVERTISE_100_HALF; + break; + case SPEED_100 + DUPLEX_FULL: +- hw->forced_speed_duplex = e1000_100_full; ++ mac->forced_speed_duplex = ADVERTISE_100_FULL; + break; + case SPEED_1000 + DUPLEX_FULL: +- hw->autoneg = 1; +- hw->autoneg_advertised = ADVERTISE_1000_FULL; ++ mac->autoneg = 1; ++ adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; + break; + case SPEED_1000 + DUPLEX_HALF: /* not supported */ + default: +@@ -4979,11 +4561,30 @@ + return 0; + } + ++#ifdef USE_REBOOT_NOTIFIER ++/* only want to do this for 2.4 kernels? */ ++static int e1000_notify_reboot(struct notifier_block *nb, ++ unsigned long event, void *p) ++{ ++ struct pci_dev *pdev = NULL; ++ ++ switch (event) { ++ case SYS_DOWN: ++ case SYS_HALT: ++ case SYS_POWER_OFF: ++ while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev))) { ++ if (pci_dev_driver(pdev) == &e1000_driver) ++ e1000_suspend(pdev, PMSG_SUSPEND); ++ } ++ } ++ return NOTIFY_DONE; ++} ++#endif ++ + static int e1000_suspend(struct pci_dev *pdev, pm_message_t state) + { + struct net_device *netdev = pci_get_drvdata(pdev); + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; + u32 ctrl, ctrl_ext, rctl, status; + u32 wufc = adapter->wol; + #ifdef CONFIG_PM +@@ -4993,8 +4594,9 @@ + netif_device_detach(netdev); + + if (netif_running(netdev)) { +- WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags)); ++ WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); + e1000_down(adapter); ++ e1000_free_irq(adapter); + } + + #ifdef CONFIG_PM +@@ -5003,50 +4605,50 @@ + return retval; + #endif + +- status = er32(STATUS); ++ status = E1000_READ_REG(&adapter->hw, E1000_STATUS); + if (status & E1000_STATUS_LU) + wufc &= ~E1000_WUFC_LNKC; + + if (wufc) { + e1000_setup_rctl(adapter); +- e1000_set_rx_mode(netdev); ++ e1000_set_multi(netdev); + + /* turn on all-multi mode if wake on multicast is enabled */ + if (wufc & E1000_WUFC_MC) { +- rctl = er32(RCTL); ++ rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); + rctl |= E1000_RCTL_MPE; +- ew32(RCTL, rctl); +- } +- +- if (hw->mac_type >= e1000_82540) { +- ctrl = er32(CTRL); ++ E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); ++ } ++ ++ if (adapter->hw.mac.type >= e1000_82540) { ++ ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); + /* advertise wake from D3Cold */ + #define E1000_CTRL_ADVD3WUC 0x00100000 + /* phy power management enable */ + #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 + ctrl |= E1000_CTRL_ADVD3WUC | + E1000_CTRL_EN_PHY_PWR_MGMT; +- ew32(CTRL, ctrl); +- } +- +- if (hw->media_type == e1000_media_type_fiber || +- hw->media_type == e1000_media_type_internal_serdes) { ++ E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); ++ } ++ ++ if (adapter->hw.phy.media_type == e1000_media_type_fiber || ++ adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { + /* keep the laser running in D3 */ +- ctrl_ext = er32(CTRL_EXT); ++ ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA; +- ew32(CTRL_EXT, ctrl_ext); ++ E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); + } + + /* Allow time for pending master requests to run */ +- e1000_disable_pciex_master(hw); +- +- ew32(WUC, E1000_WUC_PME_EN); +- ew32(WUFC, wufc); ++ e1000_disable_pcie_master(&adapter->hw); ++ ++ E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); ++ E1000_WRITE_REG(&adapter->hw, E1000_WUFC, wufc); + pci_enable_wake(pdev, PCI_D3hot, 1); + pci_enable_wake(pdev, PCI_D3cold, 1); + } else { +- ew32(WUC, 0); +- ew32(WUFC, 0); ++ E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); ++ E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); + pci_enable_wake(pdev, PCI_D3hot, 0); + pci_enable_wake(pdev, PCI_D3cold, 0); + } +@@ -5059,16 +4661,6 @@ + pci_enable_wake(pdev, PCI_D3cold, 1); + } + +- if (hw->phy_type == e1000_phy_igp_3) +- e1000_phy_powerdown_workaround(hw); +- +- if (netif_running(netdev)) +- e1000_free_irq(adapter); +- +- /* Release control of h/w to f/w. If f/w is AMT enabled, this +- * would have already happened in close and is redundant. */ +- e1000_release_hw_control(adapter); +- + pci_disable_device(pdev); + + pci_set_power_state(pdev, pci_choose_state(pdev, state)); +@@ -5081,17 +4673,11 @@ + { + struct net_device *netdev = pci_get_drvdata(pdev); + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; + u32 err; + + pci_set_power_state(pdev, PCI_D0); + pci_restore_state(pdev); +- +- if (adapter->need_ioport) +- err = pci_enable_device(pdev); +- else +- err = pci_enable_device_mem(pdev); +- if (err) { ++ if ((err = pci_enable_device(pdev))) { + printk(KERN_ERR "e1000: Cannot enable PCI device from suspend\n"); + return err; + } +@@ -5100,15 +4686,13 @@ + pci_enable_wake(pdev, PCI_D3hot, 0); + pci_enable_wake(pdev, PCI_D3cold, 0); + +- if (netif_running(netdev)) { +- err = e1000_request_irq(adapter); +- if (err) +- return err; +- } +- +- e1000_power_up_phy(adapter); +- e1000_reset(adapter); +- ew32(WUS, ~0); ++ if (netif_running(netdev) && (err = e1000_request_irq(adapter))) ++ return err; ++ ++ if (adapter->hw.phy.media_type == e1000_media_type_copper) ++ e1000_power_up_phy(&adapter->hw); ++ e1000_reset(adapter); ++ E1000_WRITE_REG(&adapter->hw, E1000_WUS, ~0); + + e1000_init_manageability(adapter); + +@@ -5117,22 +4701,16 @@ + + netif_device_attach(netdev); + +- /* If the controller is 82573 and f/w is AMT, do not set +- * DRV_LOAD until the interface is up. For all other cases, +- * let the f/w know that the h/w is now under the control +- * of the driver. */ +- if (hw->mac_type != e1000_82573 || +- !e1000_check_mng_mode(hw)) +- e1000_get_hw_control(adapter); +- +- return 0; +-} +-#endif +- ++ return 0; ++} ++#endif ++ ++#ifndef USE_REBOOT_NOTIFIER + static void e1000_shutdown(struct pci_dev *pdev) + { + e1000_suspend(pdev, PMSG_SUSPEND); + } ++#endif + + #ifdef CONFIG_NET_POLL_CONTROLLER + /* +@@ -5146,23 +4724,29 @@ + + disable_irq(adapter->pdev->irq); + e1000_intr(adapter->pdev->irq, netdev); ++ ++ e1000_clean_tx_irq(adapter, adapter->tx_ring); ++#ifndef CONFIG_E1000_NAPI ++ adapter->clean_rx(adapter, adapter->rx_ring); ++#endif + enable_irq(adapter->pdev->irq); + } + #endif + ++#ifdef HAVE_PCI_ERS + /** + * e1000_io_error_detected - called when PCI error is detected + * @pdev: Pointer to PCI device +- * @state: The current pci conneection state ++ * @state: The current pci connection state + * + * This function is called after a PCI bus error affecting + * this device has been detected. + */ + static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, +- pci_channel_state_t state) +-{ +- struct net_device *netdev = pci_get_drvdata(pdev); +- struct e1000_adapter *adapter = netdev->priv; ++ pci_channel_state_t state) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct e1000_adapter *adapter = netdev_priv(netdev); + + netif_device_detach(netdev); + +@@ -5184,15 +4768,9 @@ + static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) + { + struct net_device *netdev = pci_get_drvdata(pdev); +- struct e1000_adapter *adapter = netdev->priv; +- struct e1000_hw *hw = &adapter->hw; +- int err; +- +- if (adapter->need_ioport) +- err = pci_enable_device(pdev); +- else +- err = pci_enable_device_mem(pdev); +- if (err) { ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ if (pci_enable_device(pdev)) { + printk(KERN_ERR "e1000: Cannot re-enable PCI device after reset.\n"); + return PCI_ERS_RESULT_DISCONNECT; + } +@@ -5202,7 +4780,7 @@ + pci_enable_wake(pdev, PCI_D3cold, 0); + + e1000_reset(adapter); +- ew32(WUS, ~0); ++ E1000_WRITE_REG(&adapter->hw, E1000_WUS, ~0); + + return PCI_ERS_RESULT_RECOVERED; + } +@@ -5218,8 +4796,7 @@ + static void e1000_io_resume(struct pci_dev *pdev) + { + struct net_device *netdev = pci_get_drvdata(pdev); +- struct e1000_adapter *adapter = netdev->priv; +- struct e1000_hw *hw = &adapter->hw; ++ struct e1000_adapter *adapter = netdev_priv(netdev); + + e1000_init_manageability(adapter); + +@@ -5231,15 +4808,7 @@ + } + + netif_device_attach(netdev); +- +- /* If the controller is 82573 and f/w is AMT, do not set +- * DRV_LOAD until the interface is up. For all other cases, +- * let the f/w know that the h/w is now under the control +- * of the driver. */ +- if (hw->mac_type != e1000_82573 || +- !e1000_check_mng_mode(hw)) +- e1000_get_hw_control(adapter); +- +-} ++} ++#endif /* HAVE_PCI_ERS */ + + /* e1000_main.c */ +diff -r b58885ce604a drivers/net/e1000/e1000_manage.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_manage.c Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,384 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000_api.h" ++ ++static u8 e1000_calculate_checksum(u8 *buffer, u32 length); ++ ++/** ++ * e1000_calculate_checksum - Calculate checksum for buffer ++ * @buffer: pointer to EEPROM ++ * @length: size of EEPROM to calculate a checksum for ++ * ++ * Calculates the checksum for some buffer on a specified length. The ++ * checksum calculated is returned. ++ **/ ++static u8 e1000_calculate_checksum(u8 *buffer, u32 length) ++{ ++ u32 i; ++ u8 sum = 0; ++ ++ DEBUGFUNC("e1000_calculate_checksum"); ++ ++ if (!buffer) ++ return 0; ++ ++ for (i = 0; i < length; i++) ++ sum += buffer[i]; ++ ++ return (u8) (0 - sum); ++} ++ ++/** ++ * e1000_mng_enable_host_if_generic - Checks host interface is enabled ++ * @hw: pointer to the HW structure ++ * ++ * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND ++ * ++ * This function checks whether the HOST IF is enabled for command operation ++ * and also checks whether the previous command is completed. It busy waits ++ * in case of previous command is not completed. ++ **/ ++s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw) ++{ ++ u32 hicr; ++ s32 ret_val = E1000_SUCCESS; ++ u8 i; ++ ++ DEBUGFUNC("e1000_mng_enable_host_if_generic"); ++ ++ /* Check that the host interface is enabled. */ ++ hicr = E1000_READ_REG(hw, E1000_HICR); ++ if ((hicr & E1000_HICR_EN) == 0) { ++ DEBUGOUT("E1000_HOST_EN bit disabled.\n"); ++ ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; ++ goto out; ++ } ++ /* check the previous command is completed */ ++ for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { ++ hicr = E1000_READ_REG(hw, E1000_HICR); ++ if (!(hicr & E1000_HICR_C)) ++ break; ++ msec_delay_irq(1); ++ } ++ ++ if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { ++ DEBUGOUT("Previous command timeout failed .\n"); ++ ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_mng_mode_generic - Generic check management mode ++ * @hw: pointer to the HW structure ++ * ++ * Reads the firmware semaphore register and returns true (>0) if ++ * manageability is enabled, else false (0). ++ **/ ++bool e1000_check_mng_mode_generic(struct e1000_hw *hw) ++{ ++ u32 fwsm; ++ ++ DEBUGFUNC("e1000_check_mng_mode_generic"); ++ ++ fwsm = E1000_READ_REG(hw, E1000_FWSM); ++ ++ return (fwsm & E1000_FWSM_MODE_MASK) == ++ (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); ++} ++ ++/** ++ * e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on TX ++ * @hw: pointer to the HW structure ++ * ++ * Enables packet filtering on transmit packets if manageability is enabled ++ * and host interface is enabled. ++ **/ ++bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw) ++{ ++ struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie; ++ u32 *buffer = (u32 *)&hw->mng_cookie; ++ u32 offset; ++ s32 ret_val, hdr_csum, csum; ++ u8 i, len; ++ bool tx_filter = true; ++ ++ DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic"); ++ ++ /* No manageability, no filtering */ ++ if (!hw->mac.ops.check_mng_mode(hw)) { ++ tx_filter = false; ++ goto out; ++ } ++ ++ /* ++ * If we can't read from the host interface for whatever ++ * reason, disable filtering. ++ */ ++ ret_val = hw->mac.ops.mng_enable_host_if(hw); ++ if (ret_val != E1000_SUCCESS) { ++ tx_filter = false; ++ goto out; ++ } ++ ++ /* Read in the header. Length and offset are in dwords. */ ++ len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2; ++ offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2; ++ for (i = 0; i < len; i++) { ++ *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, ++ E1000_HOST_IF, ++ offset + i); ++ } ++ hdr_csum = hdr->checksum; ++ hdr->checksum = 0; ++ csum = e1000_calculate_checksum((u8 *)hdr, ++ E1000_MNG_DHCP_COOKIE_LENGTH); ++ /* ++ * If either the checksums or signature don't match, then ++ * the cookie area isn't considered valid, in which case we ++ * take the safe route of assuming Tx filtering is enabled. ++ */ ++ if (hdr_csum != csum) ++ goto out; ++ if (hdr->signature != E1000_IAMT_SIGNATURE) ++ goto out; ++ ++ /* Cookie area is valid, make the final check for filtering. */ ++ if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) ++ tx_filter = false; ++ ++out: ++ hw->mac.tx_pkt_filtering = tx_filter; ++ return tx_filter; ++} ++ ++/** ++ * e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface ++ * @hw: pointer to the HW structure ++ * @buffer: pointer to the host interface ++ * @length: size of the buffer ++ * ++ * Writes the DHCP information to the host interface. ++ **/ ++s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer, ++ u16 length) ++{ ++ struct e1000_host_mng_command_header hdr; ++ s32 ret_val; ++ u32 hicr; ++ ++ DEBUGFUNC("e1000_mng_write_dhcp_info_generic"); ++ ++ hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; ++ hdr.command_length = length; ++ hdr.reserved1 = 0; ++ hdr.reserved2 = 0; ++ hdr.checksum = 0; ++ ++ /* Enable the host interface */ ++ ret_val = hw->mac.ops.mng_enable_host_if(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Populate the host interface with the contents of "buffer". */ ++ ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length, ++ sizeof(hdr), &(hdr.checksum)); ++ if (ret_val) ++ goto out; ++ ++ /* Write the manageability command header */ ++ ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr); ++ if (ret_val) ++ goto out; ++ ++ /* Tell the ARC a new command is pending. */ ++ hicr = E1000_READ_REG(hw, E1000_HICR); ++ E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_mng_write_cmd_header_generic - Writes manageability command header ++ * @hw: pointer to the HW structure ++ * @hdr: pointer to the host interface command header ++ * ++ * Writes the command header after does the checksum calculation. ++ **/ ++s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header *hdr) ++{ ++ u16 i, length = sizeof(struct e1000_host_mng_command_header); ++ ++ DEBUGFUNC("e1000_mng_write_cmd_header_generic"); ++ ++ /* Write the whole command header structure with new checksum. */ ++ ++ hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length); ++ ++ length >>= 2; ++ /* Write the relevant command block into the ram area. */ ++ for (i = 0; i < length; i++) { ++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i, ++ *((u32 *) hdr + i)); ++ E1000_WRITE_FLUSH(hw); ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_mng_host_if_write_generic - Write to the manageability host interface ++ * @hw: pointer to the HW structure ++ * @buffer: pointer to the host interface buffer ++ * @length: size of the buffer ++ * @offset: location in the buffer to write to ++ * @sum: sum of the data (not checksum) ++ * ++ * This function writes the buffer content at the offset given on the host if. ++ * It also does alignment considerations to do the writes in most efficient ++ * way. Also fills up the sum of the buffer in *buffer parameter. ++ **/ ++s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer, ++ u16 length, u16 offset, u8 *sum) ++{ ++ u8 *tmp; ++ u8 *bufptr = buffer; ++ u32 data = 0; ++ s32 ret_val = E1000_SUCCESS; ++ u16 remaining, i, j, prev_bytes; ++ ++ DEBUGFUNC("e1000_mng_host_if_write_generic"); ++ ++ /* sum = only sum of the data and it is not checksum */ ++ ++ if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { ++ ret_val = -E1000_ERR_PARAM; ++ goto out; ++ } ++ ++ tmp = (u8 *)&data; ++ prev_bytes = offset & 0x3; ++ offset >>= 2; ++ ++ if (prev_bytes) { ++ data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset); ++ for (j = prev_bytes; j < sizeof(u32); j++) { ++ *(tmp + j) = *bufptr++; ++ *sum += *(tmp + j); ++ } ++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data); ++ length -= j - prev_bytes; ++ offset++; ++ } ++ ++ remaining = length & 0x3; ++ length -= remaining; ++ ++ /* Calculate length in DWORDs */ ++ length >>= 2; ++ ++ /* ++ * The device driver writes the relevant command block into the ++ * ram area. ++ */ ++ for (i = 0; i < length; i++) { ++ for (j = 0; j < sizeof(u32); j++) { ++ *(tmp + j) = *bufptr++; ++ *sum += *(tmp + j); ++ } ++ ++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, ++ data); ++ } ++ if (remaining) { ++ for (j = 0; j < sizeof(u32); j++) { ++ if (j < remaining) ++ *(tmp + j) = *bufptr++; ++ else ++ *(tmp + j) = 0; ++ ++ *sum += *(tmp + j); ++ } ++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_enable_mng_pass_thru - Enable processing of ARP's ++ * @hw: pointer to the HW structure ++ * ++ * Verifies the hardware needs to allow ARPs to be processed by the host. ++ **/ ++bool e1000_enable_mng_pass_thru(struct e1000_hw *hw) ++{ ++ u32 manc; ++ u32 fwsm, factps; ++ bool ret_val = false; ++ ++ DEBUGFUNC("e1000_enable_mng_pass_thru"); ++ ++ if (!hw->mac.asf_firmware_present) ++ goto out; ++ ++ manc = E1000_READ_REG(hw, E1000_MANC); ++ ++ if (!(manc & E1000_MANC_RCV_TCO_EN) || ++ !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) ++ goto out; ++ ++ if (hw->mac.arc_subsystem_valid) { ++ fwsm = E1000_READ_REG(hw, E1000_FWSM); ++ factps = E1000_READ_REG(hw, E1000_FACTPS); ++ ++ if (!(factps & E1000_FACTPS_MNGCG) && ++ ((fwsm & E1000_FWSM_MODE_MASK) == ++ (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { ++ ret_val = true; ++ goto out; ++ } ++ } else { ++ if ((manc & E1000_MANC_SMBUS_EN) && ++ !(manc & E1000_MANC_ASF_EN)) { ++ ret_val = true; ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ +diff -r b58885ce604a drivers/net/e1000/e1000_manage.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_manage.h Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,82 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_MANAGE_H_ ++#define _E1000_MANAGE_H_ ++ ++bool e1000_check_mng_mode_generic(struct e1000_hw *hw); ++bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw); ++s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw); ++s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer, ++ u16 length, u16 offset, u8 *sum); ++s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header *hdr); ++s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, ++ u8 *buffer, u16 length); ++bool e1000_enable_mng_pass_thru(struct e1000_hw *hw); ++ ++enum e1000_mng_mode { ++ e1000_mng_mode_none = 0, ++ e1000_mng_mode_asf, ++ e1000_mng_mode_pt, ++ e1000_mng_mode_ipmi, ++ e1000_mng_mode_host_if_only ++}; ++ ++#define E1000_FACTPS_MNGCG 0x20000000 ++ ++#define E1000_FWSM_MODE_MASK 0xE ++#define E1000_FWSM_MODE_SHIFT 1 ++ ++#define E1000_MNG_IAMT_MODE 0x3 ++#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 ++#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 ++#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 ++#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 ++#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 ++#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 ++ ++#define E1000_VFTA_ENTRY_SHIFT 5 ++#define E1000_VFTA_ENTRY_MASK 0x7F ++#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F ++ ++#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ ++#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ ++#define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ ++ ++#define E1000_HICR_EN 0x01 /* Enable bit - RO */ ++/* Driver sets this bit when done to put command in RAM */ ++#define E1000_HICR_C 0x02 ++#define E1000_HICR_SV 0x04 /* Status Validity */ ++#define E1000_HICR_FW_RESET_ENABLE 0x40 ++#define E1000_HICR_FW_RESET 0x80 ++ ++/* Intel(R) Active Management Technology signature */ ++#define E1000_IAMT_SIGNATURE 0x544D4149 ++ ++#endif +diff -r b58885ce604a drivers/net/e1000/e1000_nvm.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_nvm.c Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,919 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000_api.h" ++ ++static void e1000_reload_nvm_generic(struct e1000_hw *hw); ++ ++/** ++ * e1000_init_nvm_ops_generic - Initialize NVM function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Setups up the function pointers to no-op functions ++ **/ ++void e1000_init_nvm_ops_generic(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ DEBUGFUNC("e1000_init_nvm_ops_generic"); ++ ++ /* Initialize function pointers */ ++ nvm->ops.init_params = e1000_null_ops_generic; ++ nvm->ops.acquire = e1000_null_ops_generic; ++ nvm->ops.read = e1000_null_read_nvm; ++ nvm->ops.release = e1000_null_nvm_generic; ++ nvm->ops.reload = e1000_reload_nvm_generic; ++ nvm->ops.update = e1000_null_ops_generic; ++ nvm->ops.valid_led_default = e1000_null_led_default; ++ nvm->ops.validate = e1000_null_ops_generic; ++ nvm->ops.write = e1000_null_write_nvm; ++} ++ ++/** ++ * e1000_null_nvm_read - No-op function, return 0 ++ * @hw: pointer to the HW structure ++ **/ ++s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) ++{ ++ DEBUGFUNC("e1000_null_read_nvm"); ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_null_nvm_generic - No-op function, return void ++ * @hw: pointer to the HW structure ++ **/ ++void e1000_null_nvm_generic(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_null_nvm_generic"); ++ return; ++} ++ ++/** ++ * e1000_null_led_default - No-op function, return 0 ++ * @hw: pointer to the HW structure ++ **/ ++s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data) ++{ ++ DEBUGFUNC("e1000_null_led_default"); ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_null_write_nvm - No-op function, return 0 ++ * @hw: pointer to the HW structure ++ **/ ++s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) ++{ ++ DEBUGFUNC("e1000_null_write_nvm"); ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_raise_eec_clk - Raise EEPROM clock ++ * @hw: pointer to the HW structure ++ * @eecd: pointer to the EEPROM ++ * ++ * Enable/Raise the EEPROM clock bit. ++ **/ ++static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) ++{ ++ *eecd = *eecd | E1000_EECD_SK; ++ E1000_WRITE_REG(hw, E1000_EECD, *eecd); ++ E1000_WRITE_FLUSH(hw); ++ usec_delay(hw->nvm.delay_usec); ++} ++ ++/** ++ * e1000_lower_eec_clk - Lower EEPROM clock ++ * @hw: pointer to the HW structure ++ * @eecd: pointer to the EEPROM ++ * ++ * Clear/Lower the EEPROM clock bit. ++ **/ ++static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) ++{ ++ *eecd = *eecd & ~E1000_EECD_SK; ++ E1000_WRITE_REG(hw, E1000_EECD, *eecd); ++ E1000_WRITE_FLUSH(hw); ++ usec_delay(hw->nvm.delay_usec); ++} ++ ++/** ++ * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM ++ * @hw: pointer to the HW structure ++ * @data: data to send to the EEPROM ++ * @count: number of bits to shift out ++ * ++ * We need to shift 'count' bits out to the EEPROM. So, the value in the ++ * "data" parameter will be shifted out to the EEPROM one bit at a time. ++ * In order to do this, "data" must be broken down into bits. ++ **/ ++static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = E1000_READ_REG(hw, E1000_EECD); ++ u32 mask; ++ ++ DEBUGFUNC("e1000_shift_out_eec_bits"); ++ ++ mask = 0x01 << (count - 1); ++ if (nvm->type == e1000_nvm_eeprom_microwire) ++ eecd &= ~E1000_EECD_DO; ++ else ++ if (nvm->type == e1000_nvm_eeprom_spi) ++ eecd |= E1000_EECD_DO; ++ ++ do { ++ eecd &= ~E1000_EECD_DI; ++ ++ if (data & mask) ++ eecd |= E1000_EECD_DI; ++ ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ E1000_WRITE_FLUSH(hw); ++ ++ usec_delay(nvm->delay_usec); ++ ++ e1000_raise_eec_clk(hw, &eecd); ++ e1000_lower_eec_clk(hw, &eecd); ++ ++ mask >>= 1; ++ } while (mask); ++ ++ eecd &= ~E1000_EECD_DI; ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++} ++ ++/** ++ * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM ++ * @hw: pointer to the HW structure ++ * @count: number of bits to shift in ++ * ++ * In order to read a register from the EEPROM, we need to shift 'count' bits ++ * in from the EEPROM. Bits are "shifted in" by raising the clock input to ++ * the EEPROM (setting the SK bit), and then reading the value of the data out ++ * "DO" bit. During this "shifting in" process the data in "DI" bit should ++ * always be clear. ++ **/ ++static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) ++{ ++ u32 eecd; ++ u32 i; ++ u16 data; ++ ++ DEBUGFUNC("e1000_shift_in_eec_bits"); ++ ++ eecd = E1000_READ_REG(hw, E1000_EECD); ++ ++ eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); ++ data = 0; ++ ++ for (i = 0; i < count; i++) { ++ data <<= 1; ++ e1000_raise_eec_clk(hw, &eecd); ++ ++ eecd = E1000_READ_REG(hw, E1000_EECD); ++ ++ eecd &= ~E1000_EECD_DI; ++ if (eecd & E1000_EECD_DO) ++ data |= 1; ++ ++ e1000_lower_eec_clk(hw, &eecd); ++ } ++ ++ return data; ++} ++ ++/** ++ * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion ++ * @hw: pointer to the HW structure ++ * @ee_reg: EEPROM flag for polling ++ * ++ * Polls the EEPROM status bit for either read or write completion based ++ * upon the value of 'ee_reg'. ++ **/ ++s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) ++{ ++ u32 attempts = 100000; ++ u32 i, reg = 0; ++ s32 ret_val = -E1000_ERR_NVM; ++ ++ DEBUGFUNC("e1000_poll_eerd_eewr_done"); ++ ++ for (i = 0; i < attempts; i++) { ++ if (ee_reg == E1000_NVM_POLL_READ) ++ reg = E1000_READ_REG(hw, E1000_EERD); ++ else ++ reg = E1000_READ_REG(hw, E1000_EEWR); ++ ++ if (reg & E1000_NVM_RW_REG_DONE) { ++ ret_val = E1000_SUCCESS; ++ break; ++ } ++ ++ usec_delay(5); ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_acquire_nvm_generic - Generic request for access to EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Set the EEPROM access request bit and wait for EEPROM access grant bit. ++ * Return successful if access grant bit set, else clear the request for ++ * EEPROM access and return -E1000_ERR_NVM (-1). ++ **/ ++s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) ++{ ++ u32 eecd = E1000_READ_REG(hw, E1000_EECD); ++ s32 timeout = E1000_NVM_GRANT_ATTEMPTS; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_acquire_nvm_generic"); ++ ++ E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); ++ eecd = E1000_READ_REG(hw, E1000_EECD); ++ ++ while (timeout) { ++ if (eecd & E1000_EECD_GNT) ++ break; ++ usec_delay(5); ++ eecd = E1000_READ_REG(hw, E1000_EECD); ++ timeout--; ++ } ++ ++ if (!timeout) { ++ eecd &= ~E1000_EECD_REQ; ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ DEBUGOUT("Could not acquire NVM grant\n"); ++ ret_val = -E1000_ERR_NVM; ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_standby_nvm - Return EEPROM to standby state ++ * @hw: pointer to the HW structure ++ * ++ * Return the EEPROM to a standby state. ++ **/ ++static void e1000_standby_nvm(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = E1000_READ_REG(hw, E1000_EECD); ++ ++ DEBUGFUNC("e1000_standby_nvm"); ++ ++ if (nvm->type == e1000_nvm_eeprom_microwire) { ++ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ E1000_WRITE_FLUSH(hw); ++ usec_delay(nvm->delay_usec); ++ ++ e1000_raise_eec_clk(hw, &eecd); ++ ++ /* Select EEPROM */ ++ eecd |= E1000_EECD_CS; ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ E1000_WRITE_FLUSH(hw); ++ usec_delay(nvm->delay_usec); ++ ++ e1000_lower_eec_clk(hw, &eecd); ++ } else ++ if (nvm->type == e1000_nvm_eeprom_spi) { ++ /* Toggle CS to flush commands */ ++ eecd |= E1000_EECD_CS; ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ E1000_WRITE_FLUSH(hw); ++ usec_delay(nvm->delay_usec); ++ eecd &= ~E1000_EECD_CS; ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ E1000_WRITE_FLUSH(hw); ++ usec_delay(nvm->delay_usec); ++ } ++} ++ ++/** ++ * e1000_stop_nvm - Terminate EEPROM command ++ * @hw: pointer to the HW structure ++ * ++ * Terminates the current command by inverting the EEPROM's chip select pin. ++ **/ ++void e1000_stop_nvm(struct e1000_hw *hw) ++{ ++ u32 eecd; ++ ++ DEBUGFUNC("e1000_stop_nvm"); ++ ++ eecd = E1000_READ_REG(hw, E1000_EECD); ++ if (hw->nvm.type == e1000_nvm_eeprom_spi) { ++ /* Pull CS high */ ++ eecd |= E1000_EECD_CS; ++ e1000_lower_eec_clk(hw, &eecd); ++ } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { ++ /* CS on Microwire is active-high */ ++ eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ e1000_raise_eec_clk(hw, &eecd); ++ e1000_lower_eec_clk(hw, &eecd); ++ } ++} ++ ++/** ++ * e1000_release_nvm_generic - Release exclusive access to EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Stop any current commands to the EEPROM and clear the EEPROM request bit. ++ **/ ++void e1000_release_nvm_generic(struct e1000_hw *hw) ++{ ++ u32 eecd; ++ ++ DEBUGFUNC("e1000_release_nvm_generic"); ++ ++ e1000_stop_nvm(hw); ++ ++ eecd = E1000_READ_REG(hw, E1000_EECD); ++ eecd &= ~E1000_EECD_REQ; ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++} ++ ++/** ++ * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write ++ * @hw: pointer to the HW structure ++ * ++ * Setups the EEPROM for reading and writing. ++ **/ ++static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = E1000_READ_REG(hw, E1000_EECD); ++ s32 ret_val = E1000_SUCCESS; ++ u16 timeout = 0; ++ u8 spi_stat_reg; ++ ++ DEBUGFUNC("e1000_ready_nvm_eeprom"); ++ ++ if (nvm->type == e1000_nvm_eeprom_microwire) { ++ /* Clear SK and DI */ ++ eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ /* Set CS */ ++ eecd |= E1000_EECD_CS; ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ } else ++ if (nvm->type == e1000_nvm_eeprom_spi) { ++ /* Clear SK and CS */ ++ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ usec_delay(1); ++ timeout = NVM_MAX_RETRY_SPI; ++ ++ /* ++ * Read "Status Register" repeatedly until the LSB is cleared. ++ * The EEPROM will signal that the command has been completed ++ * by clearing bit 0 of the internal status register. If it's ++ * not cleared within 'timeout', then error out. ++ */ ++ while (timeout) { ++ e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, ++ hw->nvm.opcode_bits); ++ spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); ++ if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) ++ break; ++ ++ usec_delay(5); ++ e1000_standby_nvm(hw); ++ timeout--; ++ } ++ ++ if (!timeout) { ++ DEBUGOUT("SPI NVM Status error\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_nvm_spi - Read EEPROM's using SPI ++ * @hw: pointer to the HW structure ++ * @offset: offset of word in the EEPROM to read ++ * @words: number of words to read ++ * @data: word read from the EEPROM ++ * ++ * Reads a 16 bit word from the EEPROM. ++ **/ ++s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 i = 0; ++ s32 ret_val; ++ u16 word_in; ++ u8 read_opcode = NVM_READ_OPCODE_SPI; ++ ++ DEBUGFUNC("e1000_read_nvm_spi"); ++ ++ /* ++ * A check for invalid values: offset too large, too many words, ++ * and not enough words. ++ */ ++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || ++ (words == 0)) { ++ DEBUGOUT("nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ ret_val = nvm->ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_ready_nvm_eeprom(hw); ++ if (ret_val) ++ goto release; ++ ++ e1000_standby_nvm(hw); ++ ++ if ((nvm->address_bits == 8) && (offset >= 128)) ++ read_opcode |= NVM_A8_OPCODE_SPI; ++ ++ /* Send the READ command (opcode + addr) */ ++ e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); ++ e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); ++ ++ /* ++ * Read the data. SPI NVMs increment the address with each byte ++ * read and will roll over if reading beyond the end. This allows ++ * us to read the whole NVM from any offset ++ */ ++ for (i = 0; i < words; i++) { ++ word_in = e1000_shift_in_eec_bits(hw, 16); ++ data[i] = (word_in >> 8) | (word_in << 8); ++ } ++ ++release: ++ nvm->ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_nvm_microwire - Reads EEPROM's using microwire ++ * @hw: pointer to the HW structure ++ * @offset: offset of word in the EEPROM to read ++ * @words: number of words to read ++ * @data: word read from the EEPROM ++ * ++ * Reads a 16 bit word from the EEPROM. ++ **/ ++s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 i = 0; ++ s32 ret_val; ++ u8 read_opcode = NVM_READ_OPCODE_MICROWIRE; ++ ++ DEBUGFUNC("e1000_read_nvm_microwire"); ++ ++ /* ++ * A check for invalid values: offset too large, too many words, ++ * and not enough words. ++ */ ++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || ++ (words == 0)) { ++ DEBUGOUT("nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ ret_val = nvm->ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_ready_nvm_eeprom(hw); ++ if (ret_val) ++ goto release; ++ ++ for (i = 0; i < words; i++) { ++ /* Send the READ command (opcode + addr) */ ++ e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); ++ e1000_shift_out_eec_bits(hw, (u16)(offset + i), ++ nvm->address_bits); ++ ++ /* ++ * Read the data. For microwire, each word requires the ++ * overhead of setup and tear-down. ++ */ ++ data[i] = e1000_shift_in_eec_bits(hw, 16); ++ e1000_standby_nvm(hw); ++ } ++ ++release: ++ nvm->ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_nvm_eerd - Reads EEPROM using EERD register ++ * @hw: pointer to the HW structure ++ * @offset: offset of word in the EEPROM to read ++ * @words: number of words to read ++ * @data: word read from the EEPROM ++ * ++ * Reads a 16 bit word from the EEPROM using the EERD register. ++ **/ ++s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 i, eerd = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_read_nvm_eerd"); ++ ++ /* ++ * A check for invalid values: offset too large, too many words, ++ * too many words for the offset, and not enough words. ++ */ ++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || ++ (words == 0)) { ++ DEBUGOUT("nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ for (i = 0; i < words; i++) { ++ eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + ++ E1000_NVM_RW_REG_START; ++ ++ E1000_WRITE_REG(hw, E1000_EERD, eerd); ++ ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); ++ if (ret_val) ++ break; ++ ++ data[i] = (E1000_READ_REG(hw, E1000_EERD) >> ++ E1000_NVM_RW_REG_DATA); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_nvm_spi - Write to EEPROM using SPI ++ * @hw: pointer to the HW structure ++ * @offset: offset within the EEPROM to be written to ++ * @words: number of words to write ++ * @data: 16 bit word(s) to be written to the EEPROM ++ * ++ * Writes data to EEPROM at offset using SPI interface. ++ * ++ * If e1000_update_nvm_checksum is not called after this function , the ++ * EEPROM will most likely contain an invalid checksum. ++ **/ ++s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ s32 ret_val; ++ u16 widx = 0; ++ ++ DEBUGFUNC("e1000_write_nvm_spi"); ++ ++ /* ++ * A check for invalid values: offset too large, too many words, ++ * and not enough words. ++ */ ++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || ++ (words == 0)) { ++ DEBUGOUT("nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ ret_val = nvm->ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ while (widx < words) { ++ u8 write_opcode = NVM_WRITE_OPCODE_SPI; ++ ++ ret_val = e1000_ready_nvm_eeprom(hw); ++ if (ret_val) ++ goto release; ++ ++ e1000_standby_nvm(hw); ++ ++ /* Send the WRITE ENABLE command (8 bit opcode) */ ++ e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, ++ nvm->opcode_bits); ++ ++ e1000_standby_nvm(hw); ++ ++ /* ++ * Some SPI eeproms use the 8th address bit embedded in the ++ * opcode ++ */ ++ if ((nvm->address_bits == 8) && (offset >= 128)) ++ write_opcode |= NVM_A8_OPCODE_SPI; ++ ++ /* Send the Write command (8-bit opcode + addr) */ ++ e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); ++ e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), ++ nvm->address_bits); ++ ++ /* Loop to allow for up to whole page write of eeprom */ ++ while (widx < words) { ++ u16 word_out = data[widx]; ++ word_out = (word_out >> 8) | (word_out << 8); ++ e1000_shift_out_eec_bits(hw, word_out, 16); ++ widx++; ++ ++ if ((((offset + widx) * 2) % nvm->page_size) == 0) { ++ e1000_standby_nvm(hw); ++ break; ++ } ++ } ++ } ++ ++ msec_delay(10); ++release: ++ nvm->ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_nvm_microwire - Writes EEPROM using microwire ++ * @hw: pointer to the HW structure ++ * @offset: offset within the EEPROM to be written to ++ * @words: number of words to write ++ * @data: 16 bit word(s) to be written to the EEPROM ++ * ++ * Writes data to EEPROM at offset using microwire interface. ++ * ++ * If e1000_update_nvm_checksum is not called after this function , the ++ * EEPROM will most likely contain an invalid checksum. ++ **/ ++s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ s32 ret_val; ++ u32 eecd; ++ u16 words_written = 0; ++ u16 widx = 0; ++ ++ DEBUGFUNC("e1000_write_nvm_microwire"); ++ ++ /* ++ * A check for invalid values: offset too large, too many words, ++ * and not enough words. ++ */ ++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || ++ (words == 0)) { ++ DEBUGOUT("nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ ret_val = nvm->ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_ready_nvm_eeprom(hw); ++ if (ret_val) ++ goto release; ++ ++ e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE, ++ (u16)(nvm->opcode_bits + 2)); ++ ++ e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); ++ ++ e1000_standby_nvm(hw); ++ ++ while (words_written < words) { ++ e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE, ++ nvm->opcode_bits); ++ ++ e1000_shift_out_eec_bits(hw, (u16)(offset + words_written), ++ nvm->address_bits); ++ ++ e1000_shift_out_eec_bits(hw, data[words_written], 16); ++ ++ e1000_standby_nvm(hw); ++ ++ for (widx = 0; widx < 200; widx++) { ++ eecd = E1000_READ_REG(hw, E1000_EECD); ++ if (eecd & E1000_EECD_DO) ++ break; ++ usec_delay(50); ++ } ++ ++ if (widx == 200) { ++ DEBUGOUT("NVM Write did not complete\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto release; ++ } ++ ++ e1000_standby_nvm(hw); ++ ++ words_written++; ++ } ++ ++ e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE, ++ (u16)(nvm->opcode_bits + 2)); ++ ++ e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); ++ ++release: ++ nvm->ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_pba_num_generic - Read device part number ++ * @hw: pointer to the HW structure ++ * @pba_num: pointer to device part number ++ * ++ * Reads the product board assembly (PBA) number from the EEPROM and stores ++ * the value in pba_num. ++ **/ ++s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num) ++{ ++ s32 ret_val; ++ u16 nvm_data; ++ ++ DEBUGFUNC("e1000_read_pba_num_generic"); ++ ++ ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); ++ if (ret_val) { ++ DEBUGOUT("NVM Read Error\n"); ++ goto out; ++ } ++ *pba_num = (u32)(nvm_data << 16); ++ ++ ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); ++ if (ret_val) { ++ DEBUGOUT("NVM Read Error\n"); ++ goto out; ++ } ++ *pba_num |= nvm_data; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_mac_addr_generic - Read device MAC address ++ * @hw: pointer to the HW structure ++ * ++ * Reads the device MAC address from the EEPROM and stores the value. ++ * Since devices with two ports use the same EEPROM, we increment the ++ * last bit in the MAC address for the second port. ++ **/ ++s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) ++{ ++ u32 rar_high; ++ u32 rar_low; ++ u16 i; ++ ++ rar_high = E1000_READ_REG(hw, E1000_RAH(0)); ++ rar_low = E1000_READ_REG(hw, E1000_RAL(0)); ++ ++ for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) ++ hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); ++ ++ for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) ++ hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); ++ ++ for (i = 0; i < ETH_ADDR_LEN; i++) ++ hw->mac.addr[i] = hw->mac.perm_addr[i]; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Calculates the EEPROM checksum by reading/adding each word of the EEPROM ++ * and then verifies that the sum of the EEPROM is equal to 0xBABA. ++ **/ ++s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 checksum = 0; ++ u16 i, nvm_data; ++ ++ DEBUGFUNC("e1000_validate_nvm_checksum_generic"); ++ ++ for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { ++ ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); ++ if (ret_val) { ++ DEBUGOUT("NVM Read Error\n"); ++ goto out; ++ } ++ checksum += nvm_data; ++ } ++ ++ if (checksum != (u16) NVM_SUM) { ++ DEBUGOUT("NVM Checksum Invalid\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_update_nvm_checksum_generic - Update EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Updates the EEPROM checksum by reading/adding each word of the EEPROM ++ * up to the checksum. Then calculates the EEPROM checksum and writes the ++ * value to the EEPROM. ++ **/ ++s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ u16 checksum = 0; ++ u16 i, nvm_data; ++ ++ DEBUGFUNC("e1000_update_nvm_checksum"); ++ ++ for (i = 0; i < NVM_CHECKSUM_REG; i++) { ++ ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); ++ if (ret_val) { ++ DEBUGOUT("NVM Read Error while updating checksum.\n"); ++ goto out; ++ } ++ checksum += nvm_data; ++ } ++ checksum = (u16) NVM_SUM - checksum; ++ ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); ++ if (ret_val) ++ DEBUGOUT("NVM Write Error while updating checksum.\n"); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_reload_nvm_generic - Reloads EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the ++ * extended control register. ++ **/ ++static void e1000_reload_nvm_generic(struct e1000_hw *hw) ++{ ++ u32 ctrl_ext; ++ ++ DEBUGFUNC("e1000_reload_nvm_generic"); ++ ++ usec_delay(10); ++ ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); ++ ctrl_ext |= E1000_CTRL_EXT_EE_RST; ++ E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); ++ E1000_WRITE_FLUSH(hw); ++} ++ +diff -r b58885ce604a drivers/net/e1000/e1000_nvm.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_nvm.h Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,61 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_NVM_H_ ++#define _E1000_NVM_H_ ++ ++void e1000_init_nvm_ops_generic(struct e1000_hw *hw); ++s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c); ++void e1000_null_nvm_generic(struct e1000_hw *hw); ++s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data); ++s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c); ++s32 e1000_acquire_nvm_generic(struct e1000_hw *hw); ++ ++s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg); ++s32 e1000_read_mac_addr_generic(struct e1000_hw *hw); ++s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num); ++s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); ++s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data); ++s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data); ++s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data); ++s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw); ++s32 e1000_write_nvm_eewr(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data); ++s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data); ++s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data); ++s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw); ++void e1000_stop_nvm(struct e1000_hw *hw); ++void e1000_release_nvm_generic(struct e1000_hw *hw); ++ ++#define E1000_STM_OPCODE 0xDB00 ++ ++#endif +diff -r b58885ce604a drivers/net/e1000/e1000_osdep.h +--- a/drivers/net/e1000/e1000_osdep.h Wed Aug 05 09:27:10 2009 +0100 ++++ b/drivers/net/e1000/e1000_osdep.h Wed Aug 05 11:02:21 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel PRO/1000 Linux driver +- Copyright(c) 1999 - 2006 Intel Corporation. ++ Copyright(c) 1999 - 2008 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -27,87 +27,98 @@ + *******************************************************************************/ + + +-/* glue for the OS independent part of e1000 ++/* glue for the OS-dependent part of e1000 + * includes register access macros + */ + + #ifndef _E1000_OSDEP_H_ + #define _E1000_OSDEP_H_ + +-#include + #include + #include +-#include + #include +-#include ++#include + +-#ifdef DBG +-#define DEBUGOUT(S) printk(KERN_DEBUG S "\n") +-#define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A) +-#else ++#include "kcompat.h" ++ ++#define usec_delay(x) udelay(x) ++#ifndef msec_delay ++#define msec_delay(x) do { if(in_interrupt()) { \ ++ /* Don't sleep in interrupt context! */ \ ++ BUG(); \ ++ } else { \ ++ msleep(x); \ ++ } } while (0) ++ ++/* Some workarounds require millisecond delays and are run during interrupt ++ * context. Most notably, when establishing link, the phy may need tweaking ++ * but cannot process phy register reads/writes faster than millisecond ++ * intervals...and we establish link due to a "link status change" interrupt. ++ */ ++#define msec_delay_irq(x) mdelay(x) ++#endif ++ ++#define PCI_COMMAND_REGISTER PCI_COMMAND ++#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE ++#define ETH_ADDR_LEN ETH_ALEN ++ ++#ifdef __BIG_ENDIAN ++#define E1000_BIG_ENDIAN __BIG_ENDIAN ++#endif ++ ++ + #define DEBUGOUT(S) + #define DEBUGOUT1(S, A...) +-#endif + + #define DEBUGFUNC(F) DEBUGOUT(F "\n") + #define DEBUGOUT2 DEBUGOUT1 + #define DEBUGOUT3 DEBUGOUT2 + #define DEBUGOUT7 DEBUGOUT3 + ++#define E1000_REGISTER(a, reg) (((a)->mac.type >= e1000_82543) \ ++ ? reg \ ++ : e1000_translate_register_82542(reg)) + +-#define er32(reg) \ +- (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543) \ +- ? E1000_##reg : E1000_82542_##reg))) ++#define E1000_WRITE_REG(a, reg, value) ( \ ++ writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg)))) + +-#define ew32(reg, value) \ +- (writel((value), (hw->hw_addr + ((hw->mac_type >= e1000_82543) \ +- ? E1000_##reg : E1000_82542_##reg)))) ++#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_REGISTER(a, reg))) + + #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \ +- writel((value), ((a)->hw_addr + \ +- (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ +- ((offset) << 2)))) ++ writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2)))) + + #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ +- readl((a)->hw_addr + \ +- (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ +- ((offset) << 2))) ++ readl((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2))) + + #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY + #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY + + #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \ +- writew((value), ((a)->hw_addr + \ +- (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ +- ((offset) << 1)))) ++ writew((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1)))) + + #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \ +- readw((a)->hw_addr + \ +- (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ +- ((offset) << 1))) ++ readw((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1))) + + #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \ +- writeb((value), ((a)->hw_addr + \ +- (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ +- (offset)))) ++ writeb((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + (offset)))) + + #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \ +- readb((a)->hw_addr + \ +- (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ +- (offset))) ++ readb((a)->hw_addr + E1000_REGISTER(a, reg) + (offset))) + +-#define E1000_WRITE_FLUSH() er32(STATUS) ++#define E1000_WRITE_REG_IO(a, reg, offset) do { \ ++ outl(reg, ((a)->io_base)); \ ++ outl(offset, ((a)->io_base + 4)); } while(0) + +-#define E1000_WRITE_ICH_FLASH_REG(a, reg, value) ( \ ++#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS) ++ ++#define E1000_WRITE_FLASH_REG(a, reg, value) ( \ + writel((value), ((a)->flash_address + reg))) + +-#define E1000_READ_ICH_FLASH_REG(a, reg) ( \ +- readl((a)->flash_address + reg)) +- +-#define E1000_WRITE_ICH_FLASH_REG16(a, reg, value) ( \ ++#define E1000_WRITE_FLASH_REG16(a, reg, value) ( \ + writew((value), ((a)->flash_address + reg))) + +-#define E1000_READ_ICH_FLASH_REG16(a, reg) ( \ +- readw((a)->flash_address + reg)) ++#define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg)) ++ ++#define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg)) + + #endif /* _E1000_OSDEP_H_ */ +diff -r b58885ce604a drivers/net/e1000/e1000_param.c +--- a/drivers/net/e1000/e1000_param.c Wed Aug 05 09:27:10 2009 +0100 ++++ b/drivers/net/e1000/e1000_param.c Wed Aug 05 11:02:21 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel PRO/1000 Linux driver +- Copyright(c) 1999 - 2006 Intel Corporation. ++ Copyright(c) 1999 - 2008 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -26,6 +26,9 @@ + + *******************************************************************************/ + ++ ++#include ++ + #include "e1000.h" + + /* This is the only thing that needs to be changed to adjust the +@@ -44,11 +47,28 @@ + */ + + #define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET } ++#ifndef module_param_array ++/* Module Parameters are always initialized to -1, so that the driver ++ * can tell the difference between no user specified value or the ++ * user asking for the default value. ++ * The true default values are loaded in when e1000_check_options is called. ++ * ++ * This is a GCC extension to ANSI C. ++ * See the item "Labeled Elements in Initializers" in the section ++ * "Extensions to the C Language Family" of the GCC documentation. ++ */ ++ ++#define E1000_PARAM(X, desc) \ ++ static const int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \ ++ MODULE_PARM(X, "1-" __MODULE_STRING(E1000_MAX_NIC) "i"); \ ++ MODULE_PARM_DESC(X, desc); ++#else + #define E1000_PARAM(X, desc) \ + static int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \ +- static unsigned int num_##X; \ ++ static unsigned int num_##X = 0; \ + module_param_array_named(X, X, int, &num_##X, 0); \ + MODULE_PARM_DESC(X, desc); ++#endif + + /* Transmit Descriptor Count + * +@@ -59,6 +79,18 @@ + */ + E1000_PARAM(TxDescriptors, "Number of transmit descriptors"); + ++/* Transmit Descriptor Power ++ * ++ * Valid Range: 7-12 ++ * This value represents the size-order of each transmit descriptor. ++ * The valid size for descriptors would be 2^7 (128) to 2^12 (4096) bytes ++ * each. As this value decreases one may want to consider increasing ++ * the TxDescriptors value to maintain the same amount of frame memory. ++ * ++ * Default Value: 12 ++ */ ++E1000_PARAM(TxDescPower, "Binary exponential size (2^X) of each transmit descriptor"); ++ + /* Receive Descriptor Count + * + * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers +@@ -67,6 +99,16 @@ + * Default Value: 256 + */ + E1000_PARAM(RxDescriptors, "Number of receive descriptors"); ++ ++/* User Specified Transmit Decriptor Step ++ * ++ * Valid Range: 1, 4 ++ * - 1 - Use every TX descriptor ++ * - 4 - Use every 4th TX descriptor ++ * ++ * Default Value: 1 ++ */ ++E1000_PARAM(TxDescriptorStep, "Transmit Descriptor Step"); + + /* User Specified Speed Override + * +@@ -188,13 +230,7 @@ + */ + E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down"); + +-/* Enable Kumeran Lock Loss workaround +- * +- * Valid Range: 0, 1 +- * +- * Default Value: 1 (enabled) +- */ +-E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround"); ++ + + struct e1000_option { + enum { enable_option, range_option, list_option } type; +@@ -208,14 +244,14 @@ + } r; + struct { /* list_option info */ + int nr; +- const struct e1000_opt_list { int i; char *str; } *p; ++ struct e1000_opt_list { int i; char *str; } *p; + } l; + } arg; + }; + + static int __devinit e1000_validate_option(unsigned int *value, +- const struct e1000_option *opt, +- struct e1000_adapter *adapter) ++ const struct e1000_option *opt, ++ struct e1000_adapter *adapter) + { + if (*value == OPTION_UNSET) { + *value = opt->def; +@@ -242,7 +278,7 @@ + break; + case list_option: { + int i; +- const struct e1000_opt_list *ent; ++ struct e1000_opt_list *ent; + + for (i = 0; i < opt->arg.l.nr; i++) { + ent = &opt->arg.l.p[i]; +@@ -276,118 +312,177 @@ + * value exists, a default value is used. The final value is stored + * in a variable in the adapter structure. + **/ +- + void __devinit e1000_check_options(struct e1000_adapter *adapter) + { +- struct e1000_option opt; ++ struct e1000_hw *hw = &adapter->hw; + int bd = adapter->bd_number; +- + if (bd >= E1000_MAX_NIC) { + DPRINTK(PROBE, NOTICE, + "Warning: no configuration for board #%i\n", bd); + DPRINTK(PROBE, NOTICE, "Using defaults for all values\n"); ++#ifndef module_param_array ++ bd = E1000_MAX_NIC; ++#endif + } + + { /* Transmit Descriptor Count */ +- struct e1000_tx_ring *tx_ring = adapter->tx_ring; +- int i; +- e1000_mac_type mac_type = adapter->hw.mac_type; +- +- opt = (struct e1000_option) { ++ struct e1000_option opt = { + .type = range_option, + .name = "Transmit Descriptors", + .err = "using default of " + __MODULE_STRING(E1000_DEFAULT_TXD), + .def = E1000_DEFAULT_TXD, +- .arg = { .r = { +- .min = E1000_MIN_TXD, +- .max = mac_type < e1000_82544 ? E1000_MAX_TXD : E1000_MAX_82544_TXD +- }} ++ .arg = { .r = { .min = E1000_MIN_TXD }} + }; ++ struct e1000_tx_ring *tx_ring = adapter->tx_ring; ++ opt.arg.r.max = hw->mac.type < e1000_82544 ? ++ E1000_MAX_TXD : E1000_MAX_82544_TXD; + ++#ifdef module_param_array + if (num_TxDescriptors > bd) { ++#endif + tx_ring->count = TxDescriptors[bd]; + e1000_validate_option(&tx_ring->count, &opt, adapter); + tx_ring->count = ALIGN(tx_ring->count, +- REQ_TX_DESCRIPTOR_MULTIPLE); ++ REQ_TX_DESCRIPTOR_MULTIPLE); ++#ifdef module_param_array + } else { + tx_ring->count = opt.def; + } +- for (i = 0; i < adapter->num_tx_queues; i++) +- tx_ring[i].count = tx_ring->count; ++#endif + } ++ ++ { /* Transmit Descriptor Power */ ++ struct e1000_option opt = { ++ .type = range_option, ++ .name = "Transmit Descriptor Power", ++ .err = "using default of " ++ __MODULE_STRING(E1000_DEFAULT_TXD_PWR), ++ .def = E1000_DEFAULT_TXD_PWR, ++ .arg = { .r = { .min = E1000_MIN_TXD_PWR, ++ .max = E1000_MAX_TXD_PWR }} ++ }; ++ ++#ifdef module_param_array ++ if (num_TxDescPower > bd) { ++#endif ++ adapter->tx_desc_pwr = TxDescPower[bd]; ++ e1000_validate_option(&adapter->tx_desc_pwr, &opt, adapter); ++#ifdef module_param_array ++ } else { ++ adapter->tx_desc_pwr = opt.def; ++ } ++#endif ++ } ++ + { /* Receive Descriptor Count */ +- struct e1000_rx_ring *rx_ring = adapter->rx_ring; +- int i; +- e1000_mac_type mac_type = adapter->hw.mac_type; +- +- opt = (struct e1000_option) { ++ struct e1000_option opt = { + .type = range_option, + .name = "Receive Descriptors", + .err = "using default of " + __MODULE_STRING(E1000_DEFAULT_RXD), + .def = E1000_DEFAULT_RXD, +- .arg = { .r = { +- .min = E1000_MIN_RXD, +- .max = mac_type < e1000_82544 ? E1000_MAX_RXD : E1000_MAX_82544_RXD +- }} ++ .arg = { .r = { .min = E1000_MIN_RXD }} + }; ++ struct e1000_rx_ring *rx_ring = adapter->rx_ring; ++ opt.arg.r.max = hw->mac.type < e1000_82544 ? E1000_MAX_RXD : ++ E1000_MAX_82544_RXD; + ++#ifdef module_param_array + if (num_RxDescriptors > bd) { ++#endif + rx_ring->count = RxDescriptors[bd]; + e1000_validate_option(&rx_ring->count, &opt, adapter); + rx_ring->count = ALIGN(rx_ring->count, +- REQ_RX_DESCRIPTOR_MULTIPLE); ++ REQ_RX_DESCRIPTOR_MULTIPLE); ++#ifdef module_param_array + } else { + rx_ring->count = opt.def; + } +- for (i = 0; i < adapter->num_rx_queues; i++) +- rx_ring[i].count = rx_ring->count; ++#endif ++ } ++ { /* Transmit Descriptor Step */ ++ struct e1000_tx_ring *tx_ring = adapter->tx_ring; ++ ++ struct e1000_opt_list step_list[] = ++ {{ 1, "Transmit Descriptor step = 1" }, ++ { 4, "Transmit_descriptor_step = 4" }}; ++ ++ struct e1000_option opt = { ++ .type = list_option, ++ .name = "Transmit Descriptor Step", ++ .err = "using default of 1", ++ .def = 1, ++ .arg = { .l = { .nr = ARRAY_SIZE(step_list), ++ .p = step_list }} ++ }; ++ ++#ifdef module_param_array ++ if (num_TxDescriptorStep > bd) { ++#endif ++ tx_ring->step = TxDescriptorStep[bd]; ++ e1000_validate_option(&tx_ring->step, ++ &opt, adapter); ++#ifdef module_param_array ++ } else { ++ tx_ring->step = opt.def; ++ } ++#endif + } + { /* Checksum Offload Enable/Disable */ +- opt = (struct e1000_option) { ++ struct e1000_option opt = { + .type = enable_option, + .name = "Checksum Offload", + .err = "defaulting to Enabled", + .def = OPTION_ENABLED + }; + ++#ifdef module_param_array + if (num_XsumRX > bd) { ++#endif + unsigned int rx_csum = XsumRX[bd]; + e1000_validate_option(&rx_csum, &opt, adapter); + adapter->rx_csum = rx_csum; ++#ifdef module_param_array + } else { + adapter->rx_csum = opt.def; + } ++#endif + } + { /* Flow Control */ + + struct e1000_opt_list fc_list[] = +- {{ E1000_FC_NONE, "Flow Control Disabled" }, +- { E1000_FC_RX_PAUSE,"Flow Control Receive Only" }, +- { E1000_FC_TX_PAUSE,"Flow Control Transmit Only" }, +- { E1000_FC_FULL, "Flow Control Enabled" }, +- { E1000_FC_DEFAULT, "Flow Control Hardware Default" }}; ++ {{ e1000_fc_none, "Flow Control Disabled" }, ++ { e1000_fc_rx_pause,"Flow Control Receive Only" }, ++ { e1000_fc_tx_pause,"Flow Control Transmit Only" }, ++ { e1000_fc_full, "Flow Control Enabled" }, ++ { e1000_fc_default, "Flow Control Hardware Default" }}; + +- opt = (struct e1000_option) { ++ struct e1000_option opt = { + .type = list_option, + .name = "Flow Control", + .err = "reading default settings from EEPROM", +- .def = E1000_FC_DEFAULT, ++ .def = e1000_fc_default, + .arg = { .l = { .nr = ARRAY_SIZE(fc_list), + .p = fc_list }} + }; + ++#ifdef module_param_array + if (num_FlowControl > bd) { ++#endif + unsigned int fc = FlowControl[bd]; + e1000_validate_option(&fc, &opt, adapter); +- adapter->hw.fc = adapter->hw.original_fc = fc; ++ hw->fc.requested_mode = fc; ++ hw->fc.current_mode = fc; ++#ifdef module_param_array + } else { +- adapter->hw.fc = adapter->hw.original_fc = opt.def; ++ hw->fc.requested_mode = opt.def; ++ hw->fc.current_mode = opt.def; + } ++#endif + } + { /* Transmit Interrupt Delay */ +- opt = (struct e1000_option) { ++ struct e1000_option opt = { + .type = range_option, + .name = "Transmit Interrupt Delay", + .err = "using default of " __MODULE_STRING(DEFAULT_TIDV), +@@ -396,16 +491,20 @@ + .max = MAX_TXDELAY }} + }; + ++#ifdef module_param_array + if (num_TxIntDelay > bd) { ++#endif + adapter->tx_int_delay = TxIntDelay[bd]; + e1000_validate_option(&adapter->tx_int_delay, &opt, + adapter); ++#ifdef module_param_array + } else { + adapter->tx_int_delay = opt.def; + } ++#endif + } + { /* Transmit Absolute Interrupt Delay */ +- opt = (struct e1000_option) { ++ struct e1000_option opt = { + .type = range_option, + .name = "Transmit Absolute Interrupt Delay", + .err = "using default of " __MODULE_STRING(DEFAULT_TADV), +@@ -414,16 +513,20 @@ + .max = MAX_TXABSDELAY }} + }; + ++#ifdef module_param_array + if (num_TxAbsIntDelay > bd) { ++#endif + adapter->tx_abs_int_delay = TxAbsIntDelay[bd]; + e1000_validate_option(&adapter->tx_abs_int_delay, &opt, + adapter); ++#ifdef module_param_array + } else { + adapter->tx_abs_int_delay = opt.def; + } ++#endif + } + { /* Receive Interrupt Delay */ +- opt = (struct e1000_option) { ++ struct e1000_option opt = { + .type = range_option, + .name = "Receive Interrupt Delay", + .err = "using default of " __MODULE_STRING(DEFAULT_RDTR), +@@ -432,16 +535,20 @@ + .max = MAX_RXDELAY }} + }; + ++#ifdef module_param_array + if (num_RxIntDelay > bd) { ++#endif + adapter->rx_int_delay = RxIntDelay[bd]; + e1000_validate_option(&adapter->rx_int_delay, &opt, + adapter); ++#ifdef module_param_array + } else { + adapter->rx_int_delay = opt.def; + } ++#endif + } + { /* Receive Absolute Interrupt Delay */ +- opt = (struct e1000_option) { ++ struct e1000_option opt = { + .type = range_option, + .name = "Receive Absolute Interrupt Delay", + .err = "using default of " __MODULE_STRING(DEFAULT_RADV), +@@ -450,16 +557,20 @@ + .max = MAX_RXABSDELAY }} + }; + ++#ifdef module_param_array + if (num_RxAbsIntDelay > bd) { ++#endif + adapter->rx_abs_int_delay = RxAbsIntDelay[bd]; + e1000_validate_option(&adapter->rx_abs_int_delay, &opt, + adapter); ++#ifdef module_param_array + } else { + adapter->rx_abs_int_delay = opt.def; + } ++#endif + } + { /* Interrupt Throttling Rate */ +- opt = (struct e1000_option) { ++ struct e1000_option opt = { + .type = range_option, + .name = "Interrupt Throttling Rate (ints/sec)", + .err = "using default of " __MODULE_STRING(DEFAULT_ITR), +@@ -468,7 +579,9 @@ + .max = MAX_ITR }} + }; + ++#ifdef module_param_array + if (num_InterruptThrottleRate > bd) { ++#endif + adapter->itr = InterruptThrottleRate[bd]; + switch (adapter->itr) { + case 0: +@@ -489,53 +602,58 @@ + adapter->itr = 20000; + break; + default: +- e1000_validate_option(&adapter->itr, &opt, +- adapter); +- /* save the setting, because the dynamic bits change itr */ +- /* clear the lower two bits because they are +- * used as control */ +- adapter->itr_setting = adapter->itr & ~3; ++ /* ++ * Save the setting, because the dynamic bits ++ * change itr. ++ */ ++ if (e1000_validate_option(&adapter->itr, &opt, ++ adapter) && ++ (adapter->itr == 3)) { ++ /* ++ * In case of invalid user value, ++ * default to conservative mode. ++ */ ++ adapter->itr_setting = adapter->itr; ++ adapter->itr = 20000; ++ } else { ++ /* ++ * Clear the lower two bits because ++ * they are used as control. ++ */ ++ adapter->itr_setting = ++ adapter->itr & ~3; ++ } + break; + } ++#ifdef module_param_array + } else { + adapter->itr_setting = opt.def; + adapter->itr = 20000; + } ++#endif + } + { /* Smart Power Down */ +- opt = (struct e1000_option) { ++ struct e1000_option opt = { + .type = enable_option, + .name = "PHY Smart Power Down", + .err = "defaulting to Disabled", + .def = OPTION_DISABLED + }; + ++#ifdef module_param_array + if (num_SmartPowerDownEnable > bd) { ++#endif + unsigned int spd = SmartPowerDownEnable[bd]; + e1000_validate_option(&spd, &opt, adapter); +- adapter->smart_power_down = spd; ++ adapter->flags |= spd ? E1000_FLAG_SMART_POWER_DOWN : 0; ++#ifdef module_param_array + } else { +- adapter->smart_power_down = opt.def; ++ adapter->flags &= ~E1000_FLAG_SMART_POWER_DOWN; + } +- } +- { /* Kumeran Lock Loss Workaround */ +- opt = (struct e1000_option) { +- .type = enable_option, +- .name = "Kumeran Lock Loss Workaround", +- .err = "defaulting to Enabled", +- .def = OPTION_ENABLED +- }; +- +- if (num_KumeranLockLoss > bd) { +- unsigned int kmrn_lock_loss = KumeranLockLoss[bd]; +- e1000_validate_option(&kmrn_lock_loss, &opt, adapter); +- adapter->hw.kmrn_lock_loss_workaround_disabled = !kmrn_lock_loss; +- } else { +- adapter->hw.kmrn_lock_loss_workaround_disabled = !opt.def; +- } ++#endif + } + +- switch (adapter->hw.media_type) { ++ switch (hw->phy.media_type) { + case e1000_media_type_fiber: + case e1000_media_type_internal_serdes: + e1000_check_fiber_options(adapter); +@@ -546,6 +664,7 @@ + default: + BUG(); + } ++ + } + + /** +@@ -554,21 +673,33 @@ + * + * Handles speed and duplex options on fiber adapters + **/ +- + static void __devinit e1000_check_fiber_options(struct e1000_adapter *adapter) + { + int bd = adapter->bd_number; ++#ifndef module_param_array ++ bd = bd > E1000_MAX_NIC ? E1000_MAX_NIC : bd; ++ if ((Speed[bd] != OPTION_UNSET)) { ++#else + if (num_Speed > bd) { ++#endif + DPRINTK(PROBE, INFO, "Speed not valid for fiber adapters, " + "parameter ignored\n"); + } + ++#ifndef module_param_array ++ if ((Duplex[bd] != OPTION_UNSET)) { ++#else + if (num_Duplex > bd) { ++#endif + DPRINTK(PROBE, INFO, "Duplex not valid for fiber adapters, " + "parameter ignored\n"); + } + ++#ifndef module_param_array ++ if ((AutoNeg[bd] != OPTION_UNSET) && (AutoNeg[bd] != 0x20)) { ++#else + if ((num_AutoNeg > bd) && (AutoNeg[bd] != 0x20)) { ++#endif + DPRINTK(PROBE, INFO, "AutoNeg other than 1000/Full is " + "not valid for fiber adapters, " + "parameter ignored\n"); +@@ -581,21 +712,22 @@ + * + * Handles speed and duplex options on copper adapters + **/ +- + static void __devinit e1000_check_copper_options(struct e1000_adapter *adapter) + { +- struct e1000_option opt; ++ struct e1000_hw *hw = &adapter->hw; + unsigned int speed, dplx, an; + int bd = adapter->bd_number; ++#ifndef module_param_array ++ bd = bd > E1000_MAX_NIC ? E1000_MAX_NIC : bd; ++#endif + + { /* Speed */ +- static const struct e1000_opt_list speed_list[] = { +- { 0, "" }, +- { SPEED_10, "" }, +- { SPEED_100, "" }, +- { SPEED_1000, "" }}; ++ struct e1000_opt_list speed_list[] = {{ 0, "" }, ++ { SPEED_10, "" }, ++ { SPEED_100, "" }, ++ { SPEED_1000, "" }}; + +- opt = (struct e1000_option) { ++ struct e1000_option opt = { + .type = list_option, + .name = "Speed", + .err = "parameter ignored", +@@ -604,20 +736,23 @@ + .p = speed_list }} + }; + ++#ifdef module_param_array + if (num_Speed > bd) { ++#endif + speed = Speed[bd]; + e1000_validate_option(&speed, &opt, adapter); ++#ifdef module_param_array + } else { + speed = opt.def; + } ++#endif + } + { /* Duplex */ +- static const struct e1000_opt_list dplx_list[] = { +- { 0, "" }, +- { HALF_DUPLEX, "" }, +- { FULL_DUPLEX, "" }}; ++ struct e1000_opt_list dplx_list[] = {{ 0, "" }, ++ { HALF_DUPLEX, "" }, ++ { FULL_DUPLEX, "" }}; + +- opt = (struct e1000_option) { ++ struct e1000_option opt = { + .type = list_option, + .name = "Duplex", + .err = "parameter ignored", +@@ -626,27 +761,35 @@ + .p = dplx_list }} + }; + +- if (e1000_check_phy_reset_block(&adapter->hw)) { ++ if (e1000_check_reset_block(hw)) { + DPRINTK(PROBE, INFO, + "Link active due to SoL/IDER Session. " + "Speed/Duplex/AutoNeg parameter ignored.\n"); + return; + } ++#ifdef module_param_array + if (num_Duplex > bd) { ++#endif + dplx = Duplex[bd]; + e1000_validate_option(&dplx, &opt, adapter); ++#ifdef module_param_array + } else { + dplx = opt.def; + } ++#endif + } + ++#ifdef module_param_array + if ((num_AutoNeg > bd) && (speed != 0 || dplx != 0)) { ++#else ++ if (AutoNeg[bd] != OPTION_UNSET && (speed != 0 || dplx != 0)) { ++#endif + DPRINTK(PROBE, INFO, + "AutoNeg specified along with Speed or Duplex, " + "parameter ignored\n"); +- adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; ++ hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; + } else { /* Autoneg */ +- static const struct e1000_opt_list an_list[] = ++ struct e1000_opt_list an_list[] = + #define AA "AutoNeg advertising " + {{ 0x01, AA "10/HD" }, + { 0x02, AA "10/FD" }, +@@ -680,7 +823,7 @@ + { 0x2e, AA "1000/FD, 100/FD, 100/HD, 10/FD" }, + { 0x2f, AA "1000/FD, 100/FD, 100/HD, 10/FD, 10/HD" }}; + +- opt = (struct e1000_option) { ++ struct e1000_option opt = { + .type = list_option, + .name = "AutoNeg", + .err = "parameter ignored", +@@ -689,19 +832,27 @@ + .p = an_list }} + }; + ++#ifdef module_param_array + if (num_AutoNeg > bd) { ++#endif + an = AutoNeg[bd]; + e1000_validate_option(&an, &opt, adapter); ++#ifdef module_param_array + } else { + an = opt.def; + } +- adapter->hw.autoneg_advertised = an; ++#endif ++ hw->phy.autoneg_advertised = an; + } + + switch (speed + dplx) { + case 0: +- adapter->hw.autoneg = adapter->fc_autoneg = 1; ++ hw->mac.autoneg = adapter->fc_autoneg = TRUE; ++#ifdef module_param_array + if ((num_Speed > bd) && (speed != 0 || dplx != 0)) ++#else ++ if (Speed[bd] != OPTION_UNSET || Duplex[bd] != OPTION_UNSET) ++#endif + DPRINTK(PROBE, INFO, + "Speed and duplex autonegotiation enabled\n"); + break; +@@ -709,59 +860,59 @@ + DPRINTK(PROBE, INFO, "Half Duplex specified without Speed\n"); + DPRINTK(PROBE, INFO, "Using Autonegotiation at " + "Half Duplex only\n"); +- adapter->hw.autoneg = adapter->fc_autoneg = 1; +- adapter->hw.autoneg_advertised = ADVERTISE_10_HALF | +- ADVERTISE_100_HALF; ++ hw->mac.autoneg = adapter->fc_autoneg = TRUE; ++ hw->phy.autoneg_advertised = ADVERTISE_10_HALF | ++ ADVERTISE_100_HALF; + break; + case FULL_DUPLEX: + DPRINTK(PROBE, INFO, "Full Duplex specified without Speed\n"); + DPRINTK(PROBE, INFO, "Using Autonegotiation at " + "Full Duplex only\n"); +- adapter->hw.autoneg = adapter->fc_autoneg = 1; +- adapter->hw.autoneg_advertised = ADVERTISE_10_FULL | +- ADVERTISE_100_FULL | +- ADVERTISE_1000_FULL; ++ hw->mac.autoneg = adapter->fc_autoneg = TRUE; ++ hw->phy.autoneg_advertised = ADVERTISE_10_FULL | ++ ADVERTISE_100_FULL | ++ ADVERTISE_1000_FULL; + break; + case SPEED_10: + DPRINTK(PROBE, INFO, "10 Mbps Speed specified " + "without Duplex\n"); + DPRINTK(PROBE, INFO, "Using Autonegotiation at 10 Mbps only\n"); +- adapter->hw.autoneg = adapter->fc_autoneg = 1; +- adapter->hw.autoneg_advertised = ADVERTISE_10_HALF | +- ADVERTISE_10_FULL; ++ hw->mac.autoneg = adapter->fc_autoneg = TRUE; ++ hw->phy.autoneg_advertised = ADVERTISE_10_HALF | ++ ADVERTISE_10_FULL; + break; + case SPEED_10 + HALF_DUPLEX: + DPRINTK(PROBE, INFO, "Forcing to 10 Mbps Half Duplex\n"); +- adapter->hw.autoneg = adapter->fc_autoneg = 0; +- adapter->hw.forced_speed_duplex = e1000_10_half; +- adapter->hw.autoneg_advertised = 0; ++ hw->mac.autoneg = adapter->fc_autoneg = FALSE; ++ hw->mac.forced_speed_duplex = ADVERTISE_10_HALF; ++ hw->phy.autoneg_advertised = 0; + break; + case SPEED_10 + FULL_DUPLEX: + DPRINTK(PROBE, INFO, "Forcing to 10 Mbps Full Duplex\n"); +- adapter->hw.autoneg = adapter->fc_autoneg = 0; +- adapter->hw.forced_speed_duplex = e1000_10_full; +- adapter->hw.autoneg_advertised = 0; ++ hw->mac.autoneg = adapter->fc_autoneg = FALSE; ++ hw->mac.forced_speed_duplex = ADVERTISE_10_FULL; ++ hw->phy.autoneg_advertised = 0; + break; + case SPEED_100: + DPRINTK(PROBE, INFO, "100 Mbps Speed specified " + "without Duplex\n"); + DPRINTK(PROBE, INFO, "Using Autonegotiation at " + "100 Mbps only\n"); +- adapter->hw.autoneg = adapter->fc_autoneg = 1; +- adapter->hw.autoneg_advertised = ADVERTISE_100_HALF | +- ADVERTISE_100_FULL; ++ hw->mac.autoneg = adapter->fc_autoneg = TRUE; ++ hw->phy.autoneg_advertised = ADVERTISE_100_HALF | ++ ADVERTISE_100_FULL; + break; + case SPEED_100 + HALF_DUPLEX: + DPRINTK(PROBE, INFO, "Forcing to 100 Mbps Half Duplex\n"); +- adapter->hw.autoneg = adapter->fc_autoneg = 0; +- adapter->hw.forced_speed_duplex = e1000_100_half; +- adapter->hw.autoneg_advertised = 0; ++ hw->mac.autoneg = adapter->fc_autoneg = FALSE; ++ hw->mac.forced_speed_duplex = ADVERTISE_100_HALF; ++ hw->phy.autoneg_advertised = 0; + break; + case SPEED_100 + FULL_DUPLEX: + DPRINTK(PROBE, INFO, "Forcing to 100 Mbps Full Duplex\n"); +- adapter->hw.autoneg = adapter->fc_autoneg = 0; +- adapter->hw.forced_speed_duplex = e1000_100_full; +- adapter->hw.autoneg_advertised = 0; ++ hw->mac.autoneg = adapter->fc_autoneg = FALSE; ++ hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; ++ hw->phy.autoneg_advertised = 0; + break; + case SPEED_1000: + DPRINTK(PROBE, INFO, "1000 Mbps Speed specified without " +@@ -775,8 +926,8 @@ + full_duplex_only: + DPRINTK(PROBE, INFO, + "Using Autonegotiation at 1000 Mbps Full Duplex only\n"); +- adapter->hw.autoneg = adapter->fc_autoneg = 1; +- adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL; ++ hw->mac.autoneg = adapter->fc_autoneg = TRUE; ++ hw->phy.autoneg_advertised = ADVERTISE_1000_FULL; + break; + default: + BUG(); +diff -r b58885ce604a drivers/net/e1000/e1000_phy.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_phy.c Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,2285 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000_api.h" ++ ++/* Cable length tables */ ++static const u16 e1000_m88_cable_length_table[] = ++ { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; ++#define M88E1000_CABLE_LENGTH_TABLE_SIZE \ ++ (sizeof(e1000_m88_cable_length_table) / \ ++ sizeof(e1000_m88_cable_length_table[0])) ++ ++static const u16 e1000_igp_2_cable_length_table[] = ++ { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, ++ 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, ++ 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, ++ 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, ++ 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, ++ 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, ++ 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, ++ 104, 109, 114, 118, 121, 124}; ++#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ ++ (sizeof(e1000_igp_2_cable_length_table) / \ ++ sizeof(e1000_igp_2_cable_length_table[0])) ++ ++/** ++ * e1000_init_phy_ops_generic - Initialize PHY function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Setups up the function pointers to no-op functions ++ **/ ++void e1000_init_phy_ops_generic(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ DEBUGFUNC("e1000_init_phy_ops_generic"); ++ ++ /* Initialize function pointers */ ++ phy->ops.init_params = e1000_null_ops_generic; ++ phy->ops.acquire = e1000_null_ops_generic; ++ phy->ops.check_polarity = e1000_null_ops_generic; ++ phy->ops.check_reset_block = e1000_null_ops_generic; ++ phy->ops.commit = e1000_null_ops_generic; ++ phy->ops.force_speed_duplex = e1000_null_ops_generic; ++ phy->ops.get_cfg_done = e1000_null_ops_generic; ++ phy->ops.get_cable_length = e1000_null_ops_generic; ++ phy->ops.get_info = e1000_null_ops_generic; ++ phy->ops.read_reg = e1000_null_read_reg; ++ phy->ops.release = e1000_null_phy_generic; ++ phy->ops.reset = e1000_null_ops_generic; ++ phy->ops.set_d0_lplu_state = e1000_null_lplu_state; ++ phy->ops.set_d3_lplu_state = e1000_null_lplu_state; ++ phy->ops.write_reg = e1000_null_write_reg; ++ phy->ops.power_up = e1000_null_phy_generic; ++ phy->ops.power_down = e1000_null_phy_generic; ++} ++ ++/** ++ * e1000_null_read_reg - No-op function, return 0 ++ * @hw: pointer to the HW structure ++ **/ ++s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ DEBUGFUNC("e1000_null_read_reg"); ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_null_phy_generic - No-op function, return void ++ * @hw: pointer to the HW structure ++ **/ ++void e1000_null_phy_generic(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_null_phy_generic"); ++ return; ++} ++ ++/** ++ * e1000_null_lplu_state - No-op function, return 0 ++ * @hw: pointer to the HW structure ++ **/ ++s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active) ++{ ++ DEBUGFUNC("e1000_null_lplu_state"); ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_null_write_reg - No-op function, return 0 ++ * @hw: pointer to the HW structure ++ **/ ++s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ DEBUGFUNC("e1000_null_write_reg"); ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_check_reset_block_generic - Check if PHY reset is blocked ++ * @hw: pointer to the HW structure ++ * ++ * Read the PHY management control register and check whether a PHY reset ++ * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise ++ * return E1000_BLK_PHY_RESET (12). ++ **/ ++s32 e1000_check_reset_block_generic(struct e1000_hw *hw) ++{ ++ u32 manc; ++ ++ DEBUGFUNC("e1000_check_reset_block"); ++ ++ manc = E1000_READ_REG(hw, E1000_MANC); ++ ++ return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? ++ E1000_BLK_PHY_RESET : E1000_SUCCESS; ++} ++ ++/** ++ * e1000_get_phy_id - Retrieve the PHY ID and revision ++ * @hw: pointer to the HW structure ++ * ++ * Reads the PHY registers and stores the PHY ID and possibly the PHY ++ * revision in the hardware structure. ++ **/ ++s32 e1000_get_phy_id(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 phy_id; ++ ++ DEBUGFUNC("e1000_get_phy_id"); ++ ++ if (!(phy->ops.read_reg)) ++ goto out; ++ ++ ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); ++ if (ret_val) ++ goto out; ++ ++ phy->id = (u32)(phy_id << 16); ++ usec_delay(20); ++ ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); ++ if (ret_val) ++ goto out; ++ ++ phy->id |= (u32)(phy_id & PHY_REVISION_MASK); ++ phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_reset_dsp_generic - Reset PHY DSP ++ * @hw: pointer to the HW structure ++ * ++ * Reset the digital signal processor. ++ **/ ++s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_phy_reset_dsp_generic"); ++ ++ if (!(hw->phy.ops.write_reg)) ++ goto out; ++ ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); ++ if (ret_val) ++ goto out; ++ ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_phy_reg_mdic - Read MDI control register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Reads the MDI control register in the PHY at offset and stores the ++ * information read to data. ++ **/ ++s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ u32 i, mdic = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_read_phy_reg_mdic"); ++ ++ /* ++ * Set up Op-code, Phy Address, and register offset in the MDI ++ * Control register. The MAC will take care of interfacing with the ++ * PHY to retrieve the desired data. ++ */ ++ mdic = ((offset << E1000_MDIC_REG_SHIFT) | ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_READ)); ++ ++ E1000_WRITE_REG(hw, E1000_MDIC, mdic); ++ ++ /* ++ * Poll the ready bit to see if the MDI read completed ++ * Increasing the time out as testing showed failures with ++ * the lower time out ++ */ ++ for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { ++ usec_delay(50); ++ mdic = E1000_READ_REG(hw, E1000_MDIC); ++ if (mdic & E1000_MDIC_READY) ++ break; ++ } ++ if (!(mdic & E1000_MDIC_READY)) { ++ DEBUGOUT("MDI Read did not complete\n"); ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ if (mdic & E1000_MDIC_ERROR) { ++ DEBUGOUT("MDI Error\n"); ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ *data = (u16) mdic; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_phy_reg_mdic - Write MDI control register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write to register at offset ++ * ++ * Writes data to MDI control register in the PHY at offset. ++ **/ ++s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ u32 i, mdic = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_write_phy_reg_mdic"); ++ ++ /* ++ * Set up Op-code, Phy Address, and register offset in the MDI ++ * Control register. The MAC will take care of interfacing with the ++ * PHY to retrieve the desired data. ++ */ ++ mdic = (((u32)data) | ++ (offset << E1000_MDIC_REG_SHIFT) | ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_WRITE)); ++ ++ E1000_WRITE_REG(hw, E1000_MDIC, mdic); ++ ++ /* ++ * Poll the ready bit to see if the MDI read completed ++ * Increasing the time out as testing showed failures with ++ * the lower time out ++ */ ++ for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { ++ usec_delay(50); ++ mdic = E1000_READ_REG(hw, E1000_MDIC); ++ if (mdic & E1000_MDIC_READY) ++ break; ++ } ++ if (!(mdic & E1000_MDIC_READY)) { ++ DEBUGOUT("MDI Write did not complete\n"); ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ if (mdic & E1000_MDIC_ERROR) { ++ DEBUGOUT("MDI Error\n"); ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_phy_reg_m88 - Read m88 PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retrieved information in data. Release any acquired ++ * semaphores before exiting. ++ **/ ++s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_read_phy_reg_m88"); ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_phy_reg_m88 - Write m88 PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary, then writes the data to PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_write_phy_reg_m88"); ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_phy_reg_igp - Read igp PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retrieved information in data. Release any acquired ++ * semaphores before exiting. ++ **/ ++s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_read_phy_reg_igp"); ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ ret_val = e1000_write_phy_reg_mdic(hw, ++ IGP01E1000_PHY_PAGE_SELECT, ++ (u16)offset); ++ if (ret_val) { ++ hw->phy.ops.release(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_phy_reg_igp - Write igp PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary, then writes the data to PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_write_phy_reg_igp"); ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ ret_val = e1000_write_phy_reg_mdic(hw, ++ IGP01E1000_PHY_PAGE_SELECT, ++ (u16)offset); ++ if (ret_val) { ++ hw->phy.ops.release(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_kmrn_reg_generic - Read kumeran register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary. Then reads the PHY register at offset ++ * using the kumeran interface. The information retrieved is stored in data. ++ * Release any acquired semaphores before exiting. ++ **/ ++s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ u32 kmrnctrlsta; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_read_kmrn_reg_generic"); ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & ++ E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; ++ E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); ++ ++ usec_delay(2); ++ ++ kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); ++ *data = (u16)kmrnctrlsta; ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_kmrn_reg_generic - Write kumeran register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary. Then write the data to PHY register ++ * at the offset using the kumeran interface. Release any acquired semaphores ++ * before exiting. ++ **/ ++s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ u32 kmrnctrlsta; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_write_kmrn_reg_generic"); ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & ++ E1000_KMRNCTRLSTA_OFFSET) | data; ++ E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); ++ ++ usec_delay(2); ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link ++ * @hw: pointer to the HW structure ++ * ++ * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock ++ * and downshift values are set also. ++ **/ ++s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ ++ DEBUGFUNC("e1000_copper_link_setup_m88"); ++ ++ if (phy->reset_disable) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ /* Enable CRS on TX. This must be set for half-duplex operation. */ ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; ++ ++ /* ++ * Options: ++ * MDI/MDI-X = 0 (default) ++ * 0 - Auto for all speeds ++ * 1 - MDI mode ++ * 2 - MDI-X mode ++ * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) ++ */ ++ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; ++ ++ switch (phy->mdix) { ++ case 1: ++ phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; ++ break; ++ case 2: ++ phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; ++ break; ++ case 3: ++ phy_data |= M88E1000_PSCR_AUTO_X_1000T; ++ break; ++ case 0: ++ default: ++ phy_data |= M88E1000_PSCR_AUTO_X_MODE; ++ break; ++ } ++ ++ /* ++ * Options: ++ * disable_polarity_correction = 0 (default) ++ * Automatic Correction for Reversed Cable Polarity ++ * 0 - Disabled ++ * 1 - Enabled ++ */ ++ phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; ++ if (phy->disable_polarity_correction == 1) ++ phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; ++ ++ ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ if (phy->revision < E1000_REVISION_4) { ++ /* ++ * Force TX_CLK in the Extended PHY Specific Control Register ++ * to 25MHz clock. ++ */ ++ ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, ++ &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data |= M88E1000_EPSCR_TX_CLK_25; ++ ++ if ((phy->revision == E1000_REVISION_2) && ++ (phy->id == M88E1111_I_PHY_ID)) { ++ /* 82573L PHY - set the downshift counter to 5x. */ ++ phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; ++ phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; ++ } else { ++ /* Configure Master and Slave downshift values */ ++ phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | ++ M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); ++ phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | ++ M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); ++ } ++ ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, ++ phy_data); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* Commit the changes. */ ++ ret_val = phy->ops.commit(hw); ++ if (ret_val) { ++ DEBUGOUT("Error committing the PHY changes\n"); ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_copper_link_setup_igp - Setup igp PHY's for copper link ++ * @hw: pointer to the HW structure ++ * ++ * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for ++ * igp PHY's. ++ **/ ++s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ ++ DEBUGFUNC("e1000_copper_link_setup_igp"); ++ ++ if (phy->reset_disable) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ ret_val = hw->phy.ops.reset(hw); ++ if (ret_val) { ++ DEBUGOUT("Error resetting the PHY.\n"); ++ goto out; ++ } ++ ++ /* ++ * Wait 100ms for MAC to configure PHY from NVM settings, to avoid ++ * timeout issues when LFS is enabled. ++ */ ++ msec_delay(100); ++ ++ /* ++ * The NVM settings will configure LPLU in D3 for ++ * non-IGP1 PHYs. ++ */ ++ if (phy->type == e1000_phy_igp) { ++ /* disable lplu d3 during driver init */ ++ ret_val = hw->phy.ops.set_d3_lplu_state(hw, false); ++ if (ret_val) { ++ DEBUGOUT("Error Disabling LPLU D3\n"); ++ goto out; ++ } ++ } ++ ++ /* disable lplu d0 during driver init */ ++ if (hw->phy.ops.set_d0_lplu_state) { ++ ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); ++ if (ret_val) { ++ DEBUGOUT("Error Disabling LPLU D0\n"); ++ goto out; ++ } ++ } ++ /* Configure mdi-mdix settings */ ++ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCR_AUTO_MDIX; ++ ++ switch (phy->mdix) { ++ case 1: ++ data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; ++ break; ++ case 2: ++ data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; ++ break; ++ case 0: ++ default: ++ data |= IGP01E1000_PSCR_AUTO_MDIX; ++ break; ++ } ++ ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); ++ if (ret_val) ++ goto out; ++ ++ /* set auto-master slave resolution settings */ ++ if (hw->mac.autoneg) { ++ /* ++ * when autonegotiation advertisement is only 1000Mbps then we ++ * should disable SmartSpeed and enable Auto MasterSlave ++ * resolution as hardware default. ++ */ ++ if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { ++ /* Disable SmartSpeed */ ++ ret_val = phy->ops.read_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = phy->ops.write_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ ++ /* Set auto Master/Slave resolution process */ ++ ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~CR_1000T_MS_ENABLE; ++ ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ /* load defaults for future use */ ++ phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? ++ ((data & CR_1000T_MS_VALUE) ? ++ e1000_ms_force_master : ++ e1000_ms_force_slave) : ++ e1000_ms_auto; ++ ++ switch (phy->ms_type) { ++ case e1000_ms_force_master: ++ data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); ++ break; ++ case e1000_ms_force_slave: ++ data |= CR_1000T_MS_ENABLE; ++ data &= ~(CR_1000T_MS_VALUE); ++ break; ++ case e1000_ms_auto: ++ data &= ~CR_1000T_MS_ENABLE; ++ default: ++ break; ++ } ++ ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link ++ * @hw: pointer to the HW structure ++ * ++ * Performs initial bounds checking on autoneg advertisement parameter, then ++ * configure to advertise the full capability. Setup the PHY to autoneg ++ * and restart the negotiation process between the link partner. If ++ * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. ++ **/ ++s32 e1000_copper_link_autoneg(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_ctrl; ++ ++ DEBUGFUNC("e1000_copper_link_autoneg"); ++ ++ /* ++ * Perform some bounds checking on the autoneg advertisement ++ * parameter. ++ */ ++ phy->autoneg_advertised &= phy->autoneg_mask; ++ ++ /* ++ * If autoneg_advertised is zero, we assume it was not defaulted ++ * by the calling code so we set to advertise full capability. ++ */ ++ if (phy->autoneg_advertised == 0) ++ phy->autoneg_advertised = phy->autoneg_mask; ++ ++ DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); ++ ret_val = e1000_phy_setup_autoneg(hw); ++ if (ret_val) { ++ DEBUGOUT("Error Setting up Auto-Negotiation\n"); ++ goto out; ++ } ++ DEBUGOUT("Restarting Auto-Neg\n"); ++ ++ /* ++ * Restart auto-negotiation by setting the Auto Neg Enable bit and ++ * the Auto Neg Restart bit in the PHY control register. ++ */ ++ ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); ++ if (ret_val) ++ goto out; ++ ++ phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); ++ ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Does the user want to wait for Auto-Neg to complete here, or ++ * check at a later time (for example, callback routine). ++ */ ++ if (phy->autoneg_wait_to_complete) { ++ ret_val = hw->mac.ops.wait_autoneg(hw); ++ if (ret_val) { ++ DEBUGOUT("Error while waiting for " ++ "autoneg to complete\n"); ++ goto out; ++ } ++ } ++ ++ hw->mac.get_link_status = true; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation ++ * @hw: pointer to the HW structure ++ * ++ * Reads the MII auto-neg advertisement register and/or the 1000T control ++ * register and if the PHY is already setup for auto-negotiation, then ++ * return successful. Otherwise, setup advertisement and flow control to ++ * the appropriate values for the wanted auto-negotiation. ++ **/ ++s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 mii_autoneg_adv_reg; ++ u16 mii_1000t_ctrl_reg = 0; ++ ++ DEBUGFUNC("e1000_phy_setup_autoneg"); ++ ++ phy->autoneg_advertised &= phy->autoneg_mask; ++ ++ /* Read the MII Auto-Neg Advertisement Register (Address 4). */ ++ ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); ++ if (ret_val) ++ goto out; ++ ++ if (phy->autoneg_mask & ADVERTISE_1000_FULL) { ++ /* Read the MII 1000Base-T Control Register (Address 9). */ ++ ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, ++ &mii_1000t_ctrl_reg); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* ++ * Need to parse both autoneg_advertised and fc and set up ++ * the appropriate PHY registers. First we will parse for ++ * autoneg_advertised software override. Since we can advertise ++ * a plethora of combinations, we need to check each bit ++ * individually. ++ */ ++ ++ /* ++ * First we clear all the 10/100 mb speed bits in the Auto-Neg ++ * Advertisement Register (Address 4) and the 1000 mb speed bits in ++ * the 1000Base-T Control Register (Address 9). ++ */ ++ mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | ++ NWAY_AR_100TX_HD_CAPS | ++ NWAY_AR_10T_FD_CAPS | ++ NWAY_AR_10T_HD_CAPS); ++ mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); ++ ++ DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); ++ ++ /* Do we want to advertise 10 Mb Half Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_10_HALF) { ++ DEBUGOUT("Advertise 10mb Half duplex\n"); ++ mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; ++ } ++ ++ /* Do we want to advertise 10 Mb Full Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_10_FULL) { ++ DEBUGOUT("Advertise 10mb Full duplex\n"); ++ mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; ++ } ++ ++ /* Do we want to advertise 100 Mb Half Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_100_HALF) { ++ DEBUGOUT("Advertise 100mb Half duplex\n"); ++ mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; ++ } ++ ++ /* Do we want to advertise 100 Mb Full Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_100_FULL) { ++ DEBUGOUT("Advertise 100mb Full duplex\n"); ++ mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; ++ } ++ ++ /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ ++ if (phy->autoneg_advertised & ADVERTISE_1000_HALF) ++ DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); ++ ++ /* Do we want to advertise 1000 Mb Full Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { ++ DEBUGOUT("Advertise 1000mb Full duplex\n"); ++ mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; ++ } ++ ++ /* ++ * Check for a software override of the flow control settings, and ++ * setup the PHY advertisement registers accordingly. If ++ * auto-negotiation is enabled, then software will have to set the ++ * "PAUSE" bits to the correct value in the Auto-Negotiation ++ * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- ++ * negotiation. ++ * ++ * The possible values of the "fc" parameter are: ++ * 0: Flow control is completely disabled ++ * 1: Rx flow control is enabled (we can receive pause frames ++ * but not send pause frames). ++ * 2: Tx flow control is enabled (we can send pause frames ++ * but we do not support receiving pause frames). ++ * 3: Both Rx and Tx flow control (symmetric) are enabled. ++ * other: No software override. The flow control configuration ++ * in the EEPROM is used. ++ */ ++ switch (hw->fc.current_mode) { ++ case e1000_fc_none: ++ /* ++ * Flow control (Rx & Tx) is completely disabled by a ++ * software over-ride. ++ */ ++ mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ++ break; ++ case e1000_fc_rx_pause: ++ /* ++ * Rx Flow control is enabled, and Tx Flow control is ++ * disabled, by a software over-ride. ++ * ++ * Since there really isn't a way to advertise that we are ++ * capable of Rx Pause ONLY, we will advertise that we ++ * support both symmetric and asymmetric Rx PAUSE. Later ++ * (in e1000_config_fc_after_link_up) we will disable the ++ * hw's ability to send PAUSE frames. ++ */ ++ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ++ break; ++ case e1000_fc_tx_pause: ++ /* ++ * Tx Flow control is enabled, and Rx Flow control is ++ * disabled, by a software over-ride. ++ */ ++ mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; ++ mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; ++ break; ++ case e1000_fc_full: ++ /* ++ * Flow control (both Rx and Tx) is enabled by a software ++ * over-ride. ++ */ ++ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ++ break; ++ default: ++ DEBUGOUT("Flow control param set incorrectly\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); ++ if (ret_val) ++ goto out; ++ ++ DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); ++ ++ if (phy->autoneg_mask & ADVERTISE_1000_FULL) { ++ ret_val = phy->ops.write_reg(hw, ++ PHY_1000T_CTRL, ++ mii_1000t_ctrl_reg); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_copper_link_generic - Configure copper link settings ++ * @hw: pointer to the HW structure ++ * ++ * Calls the appropriate function to configure the link for auto-neg or forced ++ * speed and duplex. Then we check for link, once link is established calls ++ * to configure collision distance and flow control are called. If link is ++ * not established, we return -E1000_ERR_PHY (-2). ++ **/ ++s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ bool link; ++ ++ DEBUGFUNC("e1000_setup_copper_link_generic"); ++ ++ if (hw->mac.autoneg) { ++ /* ++ * Setup autoneg and flow control advertisement and perform ++ * autonegotiation. ++ */ ++ ret_val = e1000_copper_link_autoneg(hw); ++ if (ret_val) ++ goto out; ++ } else { ++ /* ++ * PHY will be set to 10H, 10F, 100H or 100F ++ * depending on user settings. ++ */ ++ DEBUGOUT("Forcing Speed and Duplex\n"); ++ ret_val = hw->phy.ops.force_speed_duplex(hw); ++ if (ret_val) { ++ DEBUGOUT("Error Forcing Speed and Duplex\n"); ++ goto out; ++ } ++ } ++ ++ /* ++ * Check link status. Wait up to 100 microseconds for link to become ++ * valid. ++ */ ++ ret_val = e1000_phy_has_link_generic(hw, ++ COPPER_LINK_UP_LIMIT, ++ 10, ++ &link); ++ if (ret_val) ++ goto out; ++ ++ if (link) { ++ DEBUGOUT("Valid link established!!!\n"); ++ e1000_config_collision_dist_generic(hw); ++ ret_val = e1000_config_fc_after_link_up_generic(hw); ++ } else { ++ DEBUGOUT("Unable to establish link!!!\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY ++ * @hw: pointer to the HW structure ++ * ++ * Calls the PHY setup function to force speed and duplex. Clears the ++ * auto-crossover to force MDI manually. Waits for link and returns ++ * successful if link up is successful, else -E1000_ERR_PHY (-2). ++ **/ ++s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ bool link; ++ ++ DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); ++ ++ ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ e1000_phy_force_speed_duplex_setup(hw, &phy_data); ++ ++ ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Clear Auto-Crossover to force MDI manually. IGP requires MDI ++ * forced whenever speed and duplex are forced. ++ */ ++ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; ++ phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; ++ ++ ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ DEBUGOUT1("IGP PSCR: %X\n", phy_data); ++ ++ usec_delay(1); ++ ++ if (phy->autoneg_wait_to_complete) { ++ DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); ++ ++ ret_val = e1000_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) ++ DEBUGOUT("Link taking longer than expected.\n"); ++ ++ /* Try once more */ ++ ret_val = e1000_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY ++ * @hw: pointer to the HW structure ++ * ++ * Calls the PHY setup function to force speed and duplex. Clears the ++ * auto-crossover to force MDI manually. Resets the PHY to commit the ++ * changes. If time expires while waiting for link up, we reset the DSP. ++ * After reset, TX_CLK and CRS on Tx must be set. Return successful upon ++ * successful completion, else return corresponding error code. ++ **/ ++s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ bool link; ++ ++ DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); ++ ++ /* ++ * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI ++ * forced whenever speed and duplex are forced. ++ */ ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; ++ ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); ++ ++ ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ e1000_phy_force_speed_duplex_setup(hw, &phy_data); ++ ++ ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* Reset the phy to commit changes. */ ++ ret_val = hw->phy.ops.commit(hw); ++ if (ret_val) ++ goto out; ++ ++ if (phy->autoneg_wait_to_complete) { ++ DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); ++ ++ ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ 100000, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ /* ++ * We didn't get link. ++ * Reset the DSP and cross our fingers. ++ */ ++ ret_val = phy->ops.write_reg(hw, ++ M88E1000_PHY_PAGE_SELECT, ++ 0x001d); ++ if (ret_val) ++ goto out; ++ ret_val = e1000_phy_reset_dsp_generic(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* Try once more */ ++ ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ 100000, &link); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Resetting the phy means we need to re-force TX_CLK in the ++ * Extended PHY Specific Control Register to 25MHz clock from ++ * the reset value of 2.5MHz. ++ */ ++ phy_data |= M88E1000_EPSCR_TX_CLK_25; ++ ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * In addition, we must re-enable CRS on Tx for both half and full ++ * duplex. ++ */ ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; ++ ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex ++ * @hw: pointer to the HW structure ++ * ++ * Forces the speed and duplex settings of the PHY. ++ * This is a function pointer entry point only called by ++ * PHY setup routines. ++ **/ ++s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ bool link; ++ ++ DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); ++ ++ if (phy->type != e1000_phy_ife) { ++ ret_val = e1000_phy_force_speed_duplex_igp(hw); ++ goto out; ++ } ++ ++ ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); ++ if (ret_val) ++ goto out; ++ ++ e1000_phy_force_speed_duplex_setup(hw, &data); ++ ++ ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); ++ if (ret_val) ++ goto out; ++ ++ /* Disable MDI-X support for 10/100 */ ++ ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IFE_PMC_AUTO_MDIX; ++ data &= ~IFE_PMC_FORCE_MDIX; ++ ++ ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); ++ if (ret_val) ++ goto out; ++ ++ DEBUGOUT1("IFE PMC: %X\n", data); ++ ++ usec_delay(1); ++ ++ if (phy->autoneg_wait_to_complete) { ++ DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); ++ ++ ret_val = e1000_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) ++ DEBUGOUT("Link taking longer than expected.\n"); ++ ++ /* Try once more */ ++ ret_val = e1000_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex ++ * @hw: pointer to the HW structure ++ * @phy_ctrl: pointer to current value of PHY_CONTROL ++ * ++ * Forces speed and duplex on the PHY by doing the following: disable flow ++ * control, force speed/duplex on the MAC, disable auto speed detection, ++ * disable auto-negotiation, configure duplex, configure speed, configure ++ * the collision distance, write configuration to CTRL register. The ++ * caller must write to the PHY_CONTROL register for these settings to ++ * take affect. ++ **/ ++void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 ctrl; ++ ++ DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); ++ ++ /* Turn off flow control when forcing speed/duplex */ ++ hw->fc.current_mode = e1000_fc_none; ++ ++ /* Force speed/duplex on the mac */ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ ctrl &= ~E1000_CTRL_SPD_SEL; ++ ++ /* Disable Auto Speed Detection */ ++ ctrl &= ~E1000_CTRL_ASDE; ++ ++ /* Disable autoneg on the phy */ ++ *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; ++ ++ /* Forcing Full or Half Duplex? */ ++ if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { ++ ctrl &= ~E1000_CTRL_FD; ++ *phy_ctrl &= ~MII_CR_FULL_DUPLEX; ++ DEBUGOUT("Half Duplex\n"); ++ } else { ++ ctrl |= E1000_CTRL_FD; ++ *phy_ctrl |= MII_CR_FULL_DUPLEX; ++ DEBUGOUT("Full Duplex\n"); ++ } ++ ++ /* Forcing 10mb or 100mb? */ ++ if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { ++ ctrl |= E1000_CTRL_SPD_100; ++ *phy_ctrl |= MII_CR_SPEED_100; ++ *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); ++ DEBUGOUT("Forcing 100mb\n"); ++ } else { ++ ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); ++ *phy_ctrl |= MII_CR_SPEED_10; ++ *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); ++ DEBUGOUT("Forcing 10mb\n"); ++ } ++ ++ e1000_config_collision_dist_generic(hw); ++ ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++} ++ ++/** ++ * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 ++ * @hw: pointer to the HW structure ++ * @active: boolean used to enable/disable lplu ++ * ++ * Success returns 0, Failure returns 1 ++ * ++ * The low power link up (lplu) state is set to the power management level D3 ++ * and SmartSpeed is disabled when active is true, else clear lplu for D3 ++ * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU ++ * is used during Dx states where the power conservation is most important. ++ * During driver activity, SmartSpeed should be enabled so performance is ++ * maintained. ++ **/ ++s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 data; ++ ++ DEBUGFUNC("e1000_set_d3_lplu_state_generic"); ++ ++ if (!(hw->phy.ops.read_reg)) ++ goto out; ++ ++ ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); ++ if (ret_val) ++ goto out; ++ ++ if (!active) { ++ data &= ~IGP02E1000_PM_D3_LPLU; ++ ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, ++ data); ++ if (ret_val) ++ goto out; ++ /* ++ * LPLU and SmartSpeed are mutually exclusive. LPLU is used ++ * during Dx states where the power conservation is most ++ * important. During driver activity we should enable ++ * SmartSpeed, so performance is maintained. ++ */ ++ if (phy->smart_speed == e1000_smart_speed_on) { ++ ret_val = phy->ops.read_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data |= IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = phy->ops.write_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } else if (phy->smart_speed == e1000_smart_speed_off) { ++ ret_val = phy->ops.read_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = phy->ops.write_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } ++ } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || ++ (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || ++ (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { ++ data |= IGP02E1000_PM_D3_LPLU; ++ ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, ++ data); ++ if (ret_val) ++ goto out; ++ ++ /* When LPLU is enabled, we should disable SmartSpeed */ ++ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_downshift_generic - Checks whether a downshift in speed occurred ++ * @hw: pointer to the HW structure ++ * ++ * Success returns 0, Failure returns 1 ++ * ++ * A downshift is detected by querying the PHY link health. ++ **/ ++s32 e1000_check_downshift_generic(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data, offset, mask; ++ ++ DEBUGFUNC("e1000_check_downshift_generic"); ++ ++ switch (phy->type) { ++ case e1000_phy_m88: ++ case e1000_phy_gg82563: ++ offset = M88E1000_PHY_SPEC_STATUS; ++ mask = M88E1000_PSSR_DOWNSHIFT; ++ break; ++ case e1000_phy_igp_2: ++ case e1000_phy_igp: ++ case e1000_phy_igp_3: ++ offset = IGP01E1000_PHY_LINK_HEALTH; ++ mask = IGP01E1000_PLHR_SS_DOWNGRADE; ++ break; ++ default: ++ /* speed downshift not supported */ ++ phy->speed_downgraded = false; ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ ret_val = phy->ops.read_reg(hw, offset, &phy_data); ++ ++ if (!ret_val) ++ phy->speed_downgraded = (phy_data & mask) ? true : false; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_polarity_m88 - Checks the polarity. ++ * @hw: pointer to the HW structure ++ * ++ * Success returns 0, Failure returns -E1000_ERR_PHY (-2) ++ * ++ * Polarity is determined based on the PHY specific status register. ++ **/ ++s32 e1000_check_polarity_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ ++ DEBUGFUNC("e1000_check_polarity_m88"); ++ ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); ++ ++ if (!ret_val) ++ phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_check_polarity_igp - Checks the polarity. ++ * @hw: pointer to the HW structure ++ * ++ * Success returns 0, Failure returns -E1000_ERR_PHY (-2) ++ * ++ * Polarity is determined based on the PHY port status register, and the ++ * current speed (since there is no polarity at 100Mbps). ++ **/ ++s32 e1000_check_polarity_igp(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data, offset, mask; ++ ++ DEBUGFUNC("e1000_check_polarity_igp"); ++ ++ /* ++ * Polarity is determined based on the speed of ++ * our connection. ++ */ ++ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); ++ if (ret_val) ++ goto out; ++ ++ if ((data & IGP01E1000_PSSR_SPEED_MASK) == ++ IGP01E1000_PSSR_SPEED_1000MBPS) { ++ offset = IGP01E1000_PHY_PCS_INIT_REG; ++ mask = IGP01E1000_PHY_POLARITY_MASK; ++ } else { ++ /* ++ * This really only applies to 10Mbps since ++ * there is no polarity for 100Mbps (always 0). ++ */ ++ offset = IGP01E1000_PHY_PORT_STATUS; ++ mask = IGP01E1000_PSSR_POLARITY_REVERSED; ++ } ++ ++ ret_val = phy->ops.read_reg(hw, offset, &data); ++ ++ if (!ret_val) ++ phy->cable_polarity = (data & mask) ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_polarity_ife - Check cable polarity for IFE PHY ++ * @hw: pointer to the HW structure ++ * ++ * Polarity is determined on the polarity reversal feature being enabled. ++ **/ ++s32 e1000_check_polarity_ife(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data, offset, mask; ++ ++ DEBUGFUNC("e1000_check_polarity_ife"); ++ ++ /* ++ * Polarity is determined based on the reversal feature being enabled. ++ */ ++ if (phy->polarity_correction) { ++ offset = IFE_PHY_EXTENDED_STATUS_CONTROL; ++ mask = IFE_PESC_POLARITY_REVERSED; ++ } else { ++ offset = IFE_PHY_SPECIAL_CONTROL; ++ mask = IFE_PSC_FORCE_POLARITY; ++ } ++ ++ ret_val = phy->ops.read_reg(hw, offset, &phy_data); ++ ++ if (!ret_val) ++ phy->cable_polarity = (phy_data & mask) ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_wait_autoneg_generic - Wait for auto-neg completion ++ * @hw: pointer to the HW structure ++ * ++ * Waits for auto-negotiation to complete or for the auto-negotiation time ++ * limit to expire, which ever happens first. ++ **/ ++s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 i, phy_status; ++ ++ DEBUGFUNC("e1000_wait_autoneg_generic"); ++ ++ if (!(hw->phy.ops.read_reg)) ++ return E1000_SUCCESS; ++ ++ /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ ++ for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); ++ if (ret_val) ++ break; ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); ++ if (ret_val) ++ break; ++ if (phy_status & MII_SR_AUTONEG_COMPLETE) ++ break; ++ msec_delay(100); ++ } ++ ++ /* ++ * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation ++ * has completed. ++ */ ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_has_link_generic - Polls PHY for link ++ * @hw: pointer to the HW structure ++ * @iterations: number of times to poll for link ++ * @usec_interval: delay between polling attempts ++ * @success: pointer to whether polling was successful or not ++ * ++ * Polls the PHY status register for link, 'iterations' number of times. ++ **/ ++s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, ++ u32 usec_interval, bool *success) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 i, phy_status; ++ ++ DEBUGFUNC("e1000_phy_has_link_generic"); ++ ++ if (!(hw->phy.ops.read_reg)) ++ return E1000_SUCCESS; ++ ++ for (i = 0; i < iterations; i++) { ++ /* ++ * Some PHYs require the PHY_STATUS register to be read ++ * twice due to the link bit being sticky. No harm doing ++ * it across the board. ++ */ ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); ++ if (ret_val) { ++ /* ++ * If the first read fails, another entity may have ++ * ownership of the resources, wait and try again to ++ * see if they have relinquished the resources yet. ++ */ ++ usec_delay(usec_interval); ++ } ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); ++ if (ret_val) ++ break; ++ if (phy_status & MII_SR_LINK_STATUS) ++ break; ++ if (usec_interval >= 1000) ++ msec_delay_irq(usec_interval/1000); ++ else ++ usec_delay(usec_interval); ++ } ++ ++ *success = (i < iterations) ? true : false; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_get_cable_length_m88 - Determine cable length for m88 PHY ++ * @hw: pointer to the HW structure ++ * ++ * Reads the PHY specific status register to retrieve the cable length ++ * information. The cable length is determined by averaging the minimum and ++ * maximum values to get the "average" cable length. The m88 PHY has four ++ * possible cable length values, which are: ++ * Register Value Cable Length ++ * 0 < 50 meters ++ * 1 50 - 80 meters ++ * 2 80 - 110 meters ++ * 3 110 - 140 meters ++ * 4 > 140 meters ++ **/ ++s32 e1000_get_cable_length_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data, index; ++ ++ DEBUGFUNC("e1000_get_cable_length_m88"); ++ ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> ++ M88E1000_PSSR_CABLE_LENGTH_SHIFT; ++ if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE + 1) { ++ ret_val = E1000_ERR_PHY; ++ goto out; ++ } ++ ++ phy->min_cable_length = e1000_m88_cable_length_table[index]; ++ phy->max_cable_length = e1000_m88_cable_length_table[index+1]; ++ ++ phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY ++ * @hw: pointer to the HW structure ++ * ++ * The automatic gain control (agc) normalizes the amplitude of the ++ * received signal, adjusting for the attenuation produced by the ++ * cable. By reading the AGC registers, which represent the ++ * combination of coarse and fine gain value, the value can be put ++ * into a lookup table to obtain the approximate cable length ++ * for each channel. ++ **/ ++s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 phy_data, i, agc_value = 0; ++ u16 cur_agc_index, max_agc_index = 0; ++ u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; ++ u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = ++ {IGP02E1000_PHY_AGC_A, ++ IGP02E1000_PHY_AGC_B, ++ IGP02E1000_PHY_AGC_C, ++ IGP02E1000_PHY_AGC_D}; ++ ++ DEBUGFUNC("e1000_get_cable_length_igp_2"); ++ ++ /* Read the AGC registers for all channels */ ++ for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { ++ ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Getting bits 15:9, which represent the combination of ++ * coarse and fine gain values. The result is a number ++ * that can be put into the lookup table to obtain the ++ * approximate cable length. ++ */ ++ cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & ++ IGP02E1000_AGC_LENGTH_MASK; ++ ++ /* Array index bound check. */ ++ if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || ++ (cur_agc_index == 0)) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++ /* Remove min & max AGC values from calculation. */ ++ if (e1000_igp_2_cable_length_table[min_agc_index] > ++ e1000_igp_2_cable_length_table[cur_agc_index]) ++ min_agc_index = cur_agc_index; ++ if (e1000_igp_2_cable_length_table[max_agc_index] < ++ e1000_igp_2_cable_length_table[cur_agc_index]) ++ max_agc_index = cur_agc_index; ++ ++ agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; ++ } ++ ++ agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + ++ e1000_igp_2_cable_length_table[max_agc_index]); ++ agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); ++ ++ /* Calculate cable length with the error range of +/- 10 meters. */ ++ phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? ++ (agc_value - IGP02E1000_AGC_RANGE) : 0; ++ phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; ++ ++ phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_phy_info_m88 - Retrieve PHY information ++ * @hw: pointer to the HW structure ++ * ++ * Valid for only copper links. Read the PHY status register (sticky read) ++ * to verify that link is up. Read the PHY special control register to ++ * determine the polarity and 10base-T extended distance. Read the PHY ++ * special status register to determine MDI/MDIx and current speed. If ++ * speed is 1000, then determine cable length, local and remote receiver. ++ **/ ++s32 e1000_get_phy_info_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ bool link; ++ ++ DEBUGFUNC("e1000_get_phy_info_m88"); ++ ++ if (hw->phy.media_type != e1000_media_type_copper) { ++ DEBUGOUT("Phy info is only valid for copper media\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ DEBUGOUT("Phy info is only valid if link is up\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) ++ ? true : false; ++ ++ ret_val = e1000_check_polarity_m88(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; ++ ++ if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { ++ ret_val = hw->phy.ops.get_cable_length(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ ++ phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ } else { ++ /* Set values to "undefined" */ ++ phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; ++ phy->local_rx = e1000_1000t_rx_status_undefined; ++ phy->remote_rx = e1000_1000t_rx_status_undefined; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_phy_info_igp - Retrieve igp PHY information ++ * @hw: pointer to the HW structure ++ * ++ * Read PHY status to determine if link is up. If link is up, then ++ * set/determine 10base-T extended distance and polarity correction. Read ++ * PHY port status to determine MDI/MDIx and speed. Based on the speed, ++ * determine on the cable length, local and remote receiver. ++ **/ ++s32 e1000_get_phy_info_igp(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ bool link; ++ ++ DEBUGFUNC("e1000_get_phy_info_igp"); ++ ++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ DEBUGOUT("Phy info is only valid if link is up\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ phy->polarity_correction = true; ++ ++ ret_val = e1000_check_polarity_igp(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); ++ if (ret_val) ++ goto out; ++ ++ phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; ++ ++ if ((data & IGP01E1000_PSSR_SPEED_MASK) == ++ IGP01E1000_PSSR_SPEED_1000MBPS) { ++ ret_val = hw->phy.ops.get_cable_length(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); ++ if (ret_val) ++ goto out; ++ ++ phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ ++ phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ } else { ++ phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; ++ phy->local_rx = e1000_1000t_rx_status_undefined; ++ phy->remote_rx = e1000_1000t_rx_status_undefined; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_sw_reset_generic - PHY software reset ++ * @hw: pointer to the HW structure ++ * ++ * Does a software reset of the PHY by reading the PHY control register and ++ * setting/write the control register reset bit to the PHY. ++ **/ ++s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 phy_ctrl; ++ ++ DEBUGFUNC("e1000_phy_sw_reset_generic"); ++ ++ if (!(hw->phy.ops.read_reg)) ++ goto out; ++ ++ ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); ++ if (ret_val) ++ goto out; ++ ++ phy_ctrl |= MII_CR_RESET; ++ ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); ++ if (ret_val) ++ goto out; ++ ++ usec_delay(1); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_hw_reset_generic - PHY hardware reset ++ * @hw: pointer to the HW structure ++ * ++ * Verify the reset block is not blocking us from resetting. Acquire ++ * semaphore (if necessary) and read/set/write the device control reset ++ * bit in the PHY. Wait the appropriate delay time for the device to ++ * reset and release the semaphore (if necessary). ++ **/ ++s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u32 ctrl; ++ ++ DEBUGFUNC("e1000_phy_hw_reset_generic"); ++ ++ ret_val = phy->ops.check_reset_block(hw); ++ if (ret_val) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ ret_val = phy->ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); ++ E1000_WRITE_FLUSH(hw); ++ ++ usec_delay(phy->reset_delay_us); ++ ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ E1000_WRITE_FLUSH(hw); ++ ++ usec_delay(150); ++ ++ phy->ops.release(hw); ++ ++ ret_val = phy->ops.get_cfg_done(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_cfg_done_generic - Generic configuration done ++ * @hw: pointer to the HW structure ++ * ++ * Generic function to wait 10 milli-seconds for configuration to complete ++ * and return success. ++ **/ ++s32 e1000_get_cfg_done_generic(struct e1000_hw *hw) ++{ ++ DEBUGFUNC("e1000_get_cfg_done_generic"); ++ ++ msec_delay_irq(10); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_phy_init_script_igp3 - Inits the IGP3 PHY ++ * @hw: pointer to the HW structure ++ * ++ * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. ++ **/ ++s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) ++{ ++ DEBUGOUT("Running IGP 3 PHY init script\n"); ++ ++ /* PHY init IGP 3 */ ++ /* Enable rise/fall, 10-mode work in class-A */ ++ hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); ++ /* Remove all caps from Replica path filter */ ++ hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); ++ /* Bias trimming for ADC, AFE and Driver (Default) */ ++ hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); ++ /* Increase Hybrid poly bias */ ++ hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); ++ /* Add 4% to Tx amplitude in Gig mode */ ++ hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); ++ /* Disable trimming (TTT) */ ++ hw->phy.ops.write_reg(hw, 0x2011, 0x0000); ++ /* Poly DC correction to 94.6% + 2% for all channels */ ++ hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); ++ /* ABS DC correction to 95.9% */ ++ hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); ++ /* BG temp curve trim */ ++ hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); ++ /* Increasing ADC OPAMP stage 1 currents to max */ ++ hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); ++ /* Force 1000 ( required for enabling PHY regs configuration) */ ++ hw->phy.ops.write_reg(hw, 0x0000, 0x0140); ++ /* Set upd_freq to 6 */ ++ hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); ++ /* Disable NPDFE */ ++ hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); ++ /* Disable adaptive fixed FFE (Default) */ ++ hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); ++ /* Enable FFE hysteresis */ ++ hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); ++ /* Fixed FFE for short cable lengths */ ++ hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); ++ /* Fixed FFE for medium cable lengths */ ++ hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); ++ /* Fixed FFE for long cable lengths */ ++ hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); ++ /* Enable Adaptive Clip Threshold */ ++ hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); ++ /* AHT reset limit to 1 */ ++ hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); ++ /* Set AHT master delay to 127 msec */ ++ hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); ++ /* Set scan bits for AHT */ ++ hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); ++ /* Set AHT Preset bits */ ++ hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); ++ /* Change integ_factor of channel A to 3 */ ++ hw->phy.ops.write_reg(hw, 0x1895, 0x0003); ++ /* Change prop_factor of channels BCD to 8 */ ++ hw->phy.ops.write_reg(hw, 0x1796, 0x0008); ++ /* Change cg_icount + enable integbp for channels BCD */ ++ hw->phy.ops.write_reg(hw, 0x1798, 0xD008); ++ /* ++ * Change cg_icount + enable integbp + change prop_factor_master ++ * to 8 for channel A ++ */ ++ hw->phy.ops.write_reg(hw, 0x1898, 0xD918); ++ /* Disable AHT in Slave mode on channel A */ ++ hw->phy.ops.write_reg(hw, 0x187A, 0x0800); ++ /* ++ * Enable LPLU and disable AN to 1000 in non-D0a states, ++ * Enable SPD+B2B ++ */ ++ hw->phy.ops.write_reg(hw, 0x0019, 0x008D); ++ /* Enable restart AN on an1000_dis change */ ++ hw->phy.ops.write_reg(hw, 0x001B, 0x2080); ++ /* Enable wh_fifo read clock in 10/100 modes */ ++ hw->phy.ops.write_reg(hw, 0x0014, 0x0045); ++ /* Restart AN, Speed selection is 1000 */ ++ hw->phy.ops.write_reg(hw, 0x0000, 0x1340); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_get_phy_type_from_id - Get PHY type from id ++ * @phy_id: phy_id read from the phy ++ * ++ * Returns the phy type from the id. ++ **/ ++enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) ++{ ++ enum e1000_phy_type phy_type = e1000_phy_unknown; ++ ++ switch (phy_id) { ++ case M88E1000_I_PHY_ID: ++ case M88E1000_E_PHY_ID: ++ case M88E1111_I_PHY_ID: ++ case M88E1011_I_PHY_ID: ++ phy_type = e1000_phy_m88; ++ break; ++ case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ ++ phy_type = e1000_phy_igp_2; ++ break; ++ case GG82563_E_PHY_ID: ++ phy_type = e1000_phy_gg82563; ++ break; ++ case IGP03E1000_E_PHY_ID: ++ phy_type = e1000_phy_igp_3; ++ break; ++ case IFE_E_PHY_ID: ++ case IFE_PLUS_E_PHY_ID: ++ case IFE_C_E_PHY_ID: ++ phy_type = e1000_phy_ife; ++ break; ++ default: ++ phy_type = e1000_phy_unknown; ++ break; ++ } ++ return phy_type; ++} ++ ++/** ++ * e1000_determine_phy_address - Determines PHY address. ++ * @hw: pointer to the HW structure ++ * ++ * This uses a trial and error method to loop through possible PHY ++ * addresses. It tests each by reading the PHY ID registers and ++ * checking for a match. ++ **/ ++s32 e1000_determine_phy_address(struct e1000_hw *hw) ++{ ++ s32 ret_val = -E1000_ERR_PHY_TYPE; ++ u32 phy_addr = 0; ++ u32 i; ++ enum e1000_phy_type phy_type = e1000_phy_unknown; ++ ++ hw->phy.id = phy_type; ++ ++ for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { ++ hw->phy.addr = phy_addr; ++ i = 0; ++ ++ do { ++ e1000_get_phy_id(hw); ++ phy_type = e1000_get_phy_type_from_id(hw->phy.id); ++ ++ /* ++ * If phy_type is valid, break - we found our ++ * PHY address ++ */ ++ if (phy_type != e1000_phy_unknown) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ msec_delay(1); ++ i++; ++ } while (i < 10); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_power_up_phy_copper - Restore copper link in case of PHY power down ++ * @hw: pointer to the HW structure ++ * ++ * In the case of a PHY power down to save power, or to turn off link during a ++ * driver unload, or wake on lan is not enabled, restore the link to previous ++ * settings. ++ **/ ++void e1000_power_up_phy_copper(struct e1000_hw *hw) ++{ ++ u16 mii_reg = 0; ++ ++ /* The PHY will retain its settings across a power down/up cycle */ ++ hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); ++ mii_reg &= ~MII_CR_POWER_DOWN; ++ hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); ++} ++ ++/** ++ * e1000_power_down_phy_copper - Restore copper link in case of PHY power down ++ * @hw: pointer to the HW structure ++ * ++ * In the case of a PHY power down to save power, or to turn off link during a ++ * driver unload, or wake on lan is not enabled, restore the link to previous ++ * settings. ++ **/ ++void e1000_power_down_phy_copper(struct e1000_hw *hw) ++{ ++ u16 mii_reg = 0; ++ ++ /* The PHY will retain its settings across a power down/up cycle */ ++ hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); ++ mii_reg |= MII_CR_POWER_DOWN; ++ hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); ++ msec_delay(1); ++} +diff -r b58885ce604a drivers/net/e1000/e1000_phy.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_phy.h Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,163 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_PHY_H_ ++#define _E1000_PHY_H_ ++ ++void e1000_init_phy_ops_generic(struct e1000_hw *hw); ++s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data); ++void e1000_null_phy_generic(struct e1000_hw *hw); ++s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active); ++s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_check_downshift_generic(struct e1000_hw *hw); ++s32 e1000_check_polarity_m88(struct e1000_hw *hw); ++s32 e1000_check_polarity_igp(struct e1000_hw *hw); ++s32 e1000_check_polarity_ife(struct e1000_hw *hw); ++s32 e1000_check_reset_block_generic(struct e1000_hw *hw); ++s32 e1000_copper_link_autoneg(struct e1000_hw *hw); ++s32 e1000_copper_link_setup_igp(struct e1000_hw *hw); ++s32 e1000_copper_link_setup_m88(struct e1000_hw *hw); ++s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw); ++s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw); ++s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); ++s32 e1000_get_cable_length_m88(struct e1000_hw *hw); ++s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw); ++s32 e1000_get_cfg_done_generic(struct e1000_hw *hw); ++s32 e1000_get_phy_id(struct e1000_hw *hw); ++s32 e1000_get_phy_info_igp(struct e1000_hw *hw); ++s32 e1000_get_phy_info_m88(struct e1000_hw *hw); ++s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw); ++void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); ++s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw); ++s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw); ++s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); ++s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active); ++s32 e1000_setup_copper_link_generic(struct e1000_hw *hw); ++s32 e1000_wait_autoneg_generic(struct e1000_hw *hw); ++s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_phy_reset_dsp(struct e1000_hw *hw); ++s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, ++ u32 usec_interval, bool *success); ++s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); ++enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id); ++s32 e1000_determine_phy_address(struct e1000_hw *hw); ++void e1000_power_up_phy_copper(struct e1000_hw *hw); ++void e1000_power_down_phy_copper(struct e1000_hw *hw); ++s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); ++ ++#define E1000_MAX_PHY_ADDR 4 ++ ++/* IGP01E1000 Specific Registers */ ++#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ ++#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ ++#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ ++#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ ++#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ ++#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ ++#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ ++#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ ++#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ ++#define IGP_PAGE_SHIFT 5 ++#define PHY_REG_MASK 0x1F ++ ++#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 ++#define IGP01E1000_PHY_POLARITY_MASK 0x0078 ++ ++#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 ++#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ ++ ++#define IGP01E1000_PSCFR_SMART_SPEED 0x0080 ++ ++/* Enable flexible speed on link-up */ ++#define IGP01E1000_GMII_FLEX_SPD 0x0010 ++#define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */ ++ ++#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ ++#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ ++#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ ++ ++#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 ++ ++#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 ++#define IGP01E1000_PSSR_MDIX 0x0800 ++#define IGP01E1000_PSSR_SPEED_MASK 0xC000 ++#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 ++ ++#define IGP02E1000_PHY_CHANNEL_NUM 4 ++#define IGP02E1000_PHY_AGC_A 0x11B1 ++#define IGP02E1000_PHY_AGC_B 0x12B1 ++#define IGP02E1000_PHY_AGC_C 0x14B1 ++#define IGP02E1000_PHY_AGC_D 0x18B1 ++ ++#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ ++#define IGP02E1000_AGC_LENGTH_MASK 0x7F ++#define IGP02E1000_AGC_RANGE 15 ++ ++#define IGP03E1000_PHY_MISC_CTRL 0x1B ++#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */ ++ ++#define E1000_CABLE_LENGTH_UNDEFINED 0xFF ++ ++#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 ++#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 ++#define E1000_KMRNCTRLSTA_REN 0x00200000 ++#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ ++#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ ++#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ ++#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ ++ ++#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 ++#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */ ++#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */ ++#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ ++ ++/* IFE PHY Extended Status Control */ ++#define IFE_PESC_POLARITY_REVERSED 0x0100 ++ ++/* IFE PHY Special Control */ ++#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 ++#define IFE_PSC_FORCE_POLARITY 0x0020 ++#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 ++ ++/* IFE PHY Special Control and LED Control */ ++#define IFE_PSCL_PROBE_MODE 0x0020 ++#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ ++#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ ++ ++/* IFE PHY MDIX Control */ ++#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ ++#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ ++#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */ ++ ++#endif +diff -r b58885ce604a drivers/net/e1000/e1000_regs.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/e1000_regs.h Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,327 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_REGS_H_ ++#define _E1000_REGS_H_ ++ ++#define E1000_CTRL 0x00000 /* Device Control - RW */ ++#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ ++#define E1000_STATUS 0x00008 /* Device Status - RO */ ++#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ ++#define E1000_EERD 0x00014 /* EEPROM Read - RW */ ++#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ ++#define E1000_FLA 0x0001C /* Flash Access - RW */ ++#define E1000_MDIC 0x00020 /* MDI Control - RW */ ++#define E1000_SCTL 0x00024 /* SerDes Control - RW */ ++#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ ++#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ ++#define E1000_FEXT 0x0002C /* Future Extended - RW */ ++#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ ++#define E1000_FCT 0x00030 /* Flow Control Type - RW */ ++#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ ++#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ ++#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ ++#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ ++#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ ++#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ ++#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ ++#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ ++#define E1000_RCTL 0x00100 /* Rx Control - RW */ ++#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ ++#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ ++#define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ ++#define E1000_TCTL 0x00400 /* Tx Control - RW */ ++#define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */ ++#define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */ ++#define E1000_TBT 0x00448 /* Tx Burst Timer - RW */ ++#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ ++#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ ++#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ ++#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ ++#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ ++#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ ++#define E1000_PBS 0x01008 /* Packet Buffer Size */ ++#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ ++#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ ++#define E1000_FLASHT 0x01028 /* FLASH Timer Register */ ++#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ ++#define E1000_FLSWCTL 0x01030 /* FLASH control register */ ++#define E1000_FLSWDATA 0x01034 /* FLASH data register */ ++#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ ++#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ ++#define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */ ++#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */ ++#define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */ ++#define E1000_SWDSTS 0x01044 /* SW Device Status - RW */ ++#define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */ ++#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ ++#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ ++#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ ++#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ ++#define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n))) ++#define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */ ++#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ ++/* Split and Replication Rx Control - RW */ ++#define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */ ++#define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */ ++#define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */ ++#define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */ ++#define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */ ++#define E1000_RXCTL(_n) (0x0C014 + (0x40 * (_n))) ++#define E1000_RQDPC(_n) (0x0C030 + (0x40 * (_n))) ++#define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ ++#define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ ++/* ++ * Convenience macros ++ * ++ * Note: "_n" is the queue number of the register to be written to. ++ * ++ * Example usage: ++ * E1000_RDBAL_REG(current_rx_queue) ++ */ ++#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \ ++ (0x0C000 + ((_n) * 0x40))) ++#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ ++ (0x0C004 + ((_n) * 0x40))) ++#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ ++ (0x0C008 + ((_n) * 0x40))) ++#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \ ++ (0x0C00C + ((_n) * 0x40))) ++#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ ++ (0x0C010 + ((_n) * 0x40))) ++#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ ++ (0x0C018 + ((_n) * 0x40))) ++#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ ++ (0x0C028 + ((_n) * 0x40))) ++#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ ++ (0x0E000 + ((_n) * 0x40))) ++#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ ++ (0x0E004 + ((_n) * 0x40))) ++#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ ++ (0x0E008 + ((_n) * 0x40))) ++#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ ++ (0x0E010 + ((_n) * 0x40))) ++#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ ++ (0x0E018 + ((_n) * 0x40))) ++#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ ++ (0x0E028 + ((_n) * 0x40))) ++#define E1000_TARC(_n) (0x03840 + (_n << 8)) ++#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) ++#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) ++#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \ ++ (0x0E038 + ((_n) * 0x40))) ++#define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \ ++ (0x0E03C + ((_n) * 0x40))) ++#define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */ ++#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ ++#define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */ ++#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ ++#define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) ++#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ ++ (0x054E0 + ((_i - 16) * 8))) ++#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ ++ (0x054E4 + ((_i - 16) * 8))) ++#define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) ++#define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) ++#define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) ++#define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) ++#define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) ++#define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) ++#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ ++#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ ++#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ ++#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ ++#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ ++#define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */ ++#define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */ ++#define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */ ++#define E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */ ++#define E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */ ++#define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */ ++#define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */ ++#define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */ ++#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ ++#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ ++#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ ++#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ ++#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ ++#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ ++#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ ++#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ ++#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ ++#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ ++#define E1000_COLC 0x04028 /* Collision Count - R/clr */ ++#define E1000_DC 0x04030 /* Defer Count - R/clr */ ++#define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */ ++#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ ++#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ ++#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ ++#define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */ ++#define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */ ++#define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */ ++#define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */ ++#define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */ ++#define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */ ++#define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */ ++#define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */ ++#define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */ ++#define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */ ++#define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */ ++#define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */ ++#define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */ ++#define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */ ++#define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */ ++#define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */ ++#define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */ ++#define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */ ++#define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */ ++#define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */ ++#define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */ ++#define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */ ++#define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */ ++#define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */ ++#define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */ ++#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ ++#define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */ ++#define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */ ++#define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */ ++#define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */ ++#define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */ ++#define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */ ++#define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */ ++#define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */ ++#define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */ ++#define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */ ++#define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */ ++#define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */ ++#define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */ ++#define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */ ++#define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */ ++#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */ ++#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */ ++#define E1000_IAC 0x04100 /* Interrupt Assertion Count */ ++#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ ++#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ ++#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ ++#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ ++#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ ++#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ ++#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ ++#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ ++ ++#define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ ++#define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ ++#define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ ++#define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */ ++#define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */ ++#define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */ ++#define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */ ++#define E1000_RPTHC 0x04104 /* Rx Packets To Host */ ++#define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */ ++#define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */ ++#define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */ ++#define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */ ++#define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */ ++#define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */ ++#define E1000_LENERRS 0x04138 /* Length Errors Count */ ++#define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */ ++#define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */ ++#define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ ++#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ ++#define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ ++#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */ ++#define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Packet Count - RW */ ++#define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */ ++#define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */ ++#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ ++#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ ++#define E1000_RA 0x05400 /* Receive Address - RW Array */ ++#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ ++#define E1000_VT_CTL 0x0581C /* VMDq Control - RW */ ++#define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */ ++#define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */ ++#define E1000_WUC 0x05800 /* Wakeup Control - RW */ ++#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ ++#define E1000_WUS 0x05810 /* Wakeup Status - RO */ ++#define E1000_MANC 0x05820 /* Management Control - RW */ ++#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ ++#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ ++#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ ++#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ ++#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ ++#define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */ ++#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ ++#define E1000_HOST_IF 0x08800 /* Host Interface */ ++#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ ++#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ ++ ++#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ ++#define E1000_MDPHYA 0x0003C /* PHY address - RW */ ++#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ ++#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ ++#define E1000_CCMCTL 0x05B48 /* CCM Control Register */ ++#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ ++#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ ++#define E1000_GCR 0x05B00 /* PCI-Ex Control */ ++#define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ ++#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ ++#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ ++#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ ++#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ ++#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ ++#define E1000_SWSM 0x05B50 /* SW Semaphore */ ++#define E1000_FWSM 0x05B54 /* FW Semaphore */ ++#define E1000_SWSM2 0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */ ++#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ ++#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ ++#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ ++#define E1000_HICR 0x08F00 /* Host Interface Control */ ++ ++/* RSS registers */ ++#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ ++#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ ++#define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ ++#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/ ++#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */ ++#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register ++ * (_i) - RW */ ++#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr ++ * low reg - RW */ ++#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr ++ * upper reg - RW */ ++#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry ++ * message reg - RW */ ++#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry ++ * vector ctrl reg - RW */ ++#define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */ ++#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ ++#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ ++#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ ++#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ ++ ++#endif +diff -r b58885ce604a drivers/net/e1000/kcompat.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/kcompat.c Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,472 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000.h" ++#include "kcompat.h" ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,21) ) ++struct sk_buff * ++_kc_skb_pad(struct sk_buff *skb, int pad) ++{ ++ struct sk_buff *nskb; ++ ++ /* If the skbuff is non linear tailroom is always zero.. */ ++ if(skb_tailroom(skb) >= pad) ++ { ++ memset(skb->data+skb->len, 0, pad); ++ return skb; ++ } ++ ++ nskb = skb_copy_expand(skb, skb_headroom(skb), skb_tailroom(skb) + pad, GFP_ATOMIC); ++ kfree_skb(skb); ++ if(nskb) ++ memset(nskb->data+nskb->len, 0, pad); ++ return nskb; ++} ++#endif /* < 2.4.21 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) ) ++ ++/**************************************/ ++/* PCI DMA MAPPING */ ++ ++#if defined(CONFIG_HIGHMEM) ++ ++#ifndef PCI_DRAM_OFFSET ++#define PCI_DRAM_OFFSET 0 ++#endif ++ ++u64 ++_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, ++ size_t size, int direction) ++{ ++ return (((u64) (page - mem_map) << PAGE_SHIFT) + offset + ++ PCI_DRAM_OFFSET); ++} ++ ++#else /* CONFIG_HIGHMEM */ ++ ++u64 ++_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, ++ size_t size, int direction) ++{ ++ return pci_map_single(dev, (void *)page_address(page) + offset, size, ++ direction); ++} ++ ++#endif /* CONFIG_HIGHMEM */ ++ ++void ++_kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, ++ int direction) ++{ ++ return pci_unmap_single(dev, dma_addr, size, direction); ++} ++ ++#endif /* 2.4.13 => 2.4.3 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) ) ++ ++/**************************************/ ++/* PCI DRIVER API */ ++ ++int ++_kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask) ++{ ++ if (!pci_dma_supported(dev, mask)) ++ return -EIO; ++ dev->dma_mask = mask; ++ return 0; ++} ++ ++int ++_kc_pci_request_regions(struct pci_dev *dev, char *res_name) ++{ ++ int i; ++ ++ for (i = 0; i < 6; i++) { ++ if (pci_resource_len(dev, i) == 0) ++ continue; ++ ++ if (pci_resource_flags(dev, i) & IORESOURCE_IO) { ++ if (!request_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) { ++ pci_release_regions(dev); ++ return -EBUSY; ++ } ++ } else if (pci_resource_flags(dev, i) & IORESOURCE_MEM) { ++ if (!request_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) { ++ pci_release_regions(dev); ++ return -EBUSY; ++ } ++ } ++ } ++ return 0; ++} ++ ++void ++_kc_pci_release_regions(struct pci_dev *dev) ++{ ++ int i; ++ ++ for (i = 0; i < 6; i++) { ++ if (pci_resource_len(dev, i) == 0) ++ continue; ++ ++ if (pci_resource_flags(dev, i) & IORESOURCE_IO) ++ release_region(pci_resource_start(dev, i), pci_resource_len(dev, i)); ++ ++ else if (pci_resource_flags(dev, i) & IORESOURCE_MEM) ++ release_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i)); ++ } ++} ++ ++/**************************************/ ++/* NETWORK DRIVER API */ ++ ++struct net_device * ++_kc_alloc_etherdev(int sizeof_priv) ++{ ++ struct net_device *dev; ++ int alloc_size; ++ ++ alloc_size = sizeof(*dev) + sizeof_priv + IFNAMSIZ + 31; ++ dev = kmalloc(alloc_size, GFP_KERNEL); ++ if (!dev) ++ return NULL; ++ memset(dev, 0, alloc_size); ++ ++ if (sizeof_priv) ++ dev->priv = (void *) (((unsigned long)(dev + 1) + 31) & ~31); ++ dev->name[0] = '\0'; ++ ether_setup(dev); ++ ++ return dev; ++} ++ ++int ++_kc_is_valid_ether_addr(u8 *addr) ++{ ++ const char zaddr[6] = { 0, }; ++ ++ return !(addr[0] & 1) && memcmp(addr, zaddr, 6); ++} ++ ++#endif /* 2.4.3 => 2.4.0 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) ) ++ ++int ++_kc_pci_set_power_state(struct pci_dev *dev, int state) ++{ ++ return 0; ++} ++ ++int ++_kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable) ++{ ++ return 0; ++} ++ ++#endif /* 2.4.6 => 2.4.3 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) ++void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, ++ int off, int size) ++{ ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ frag->page = page; ++ frag->page_offset = off; ++ frag->size = size; ++ skb_shinfo(skb)->nr_frags = i + 1; ++} ++ ++/* ++ * Original Copyright: ++ * find_next_bit.c: fallback find next bit implementation ++ * ++ * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. ++ * Written by David Howells (dhowells@redhat.com) ++ */ ++ ++/** ++ * find_next_bit - find the next set bit in a memory region ++ * @addr: The address to base the search on ++ * @offset: The bitnumber to start searching at ++ * @size: The maximum size to search ++ */ ++unsigned long find_next_bit(const unsigned long *addr, unsigned long size, ++ unsigned long offset) ++{ ++ const unsigned long *p = addr + BITOP_WORD(offset); ++ unsigned long result = offset & ~(BITS_PER_LONG-1); ++ unsigned long tmp; ++ ++ if (offset >= size) ++ return size; ++ size -= result; ++ offset %= BITS_PER_LONG; ++ if (offset) { ++ tmp = *(p++); ++ tmp &= (~0UL << offset); ++ if (size < BITS_PER_LONG) ++ goto found_first; ++ if (tmp) ++ goto found_middle; ++ size -= BITS_PER_LONG; ++ result += BITS_PER_LONG; ++ } ++ while (size & ~(BITS_PER_LONG-1)) { ++ if ((tmp = *(p++))) ++ goto found_middle; ++ result += BITS_PER_LONG; ++ size -= BITS_PER_LONG; ++ } ++ if (!size) ++ return result; ++ tmp = *p; ++ ++found_first: ++ tmp &= (~0UL >> (BITS_PER_LONG - size)); ++ if (tmp == 0UL) /* Are any bits set? */ ++ return result + size; /* Nope. */ ++found_middle: ++ return result + ffs(tmp); ++} ++ ++#endif /* 2.6.0 => 2.4.6 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) ) ++void *_kc_kzalloc(size_t size, int flags) ++{ ++ void *ret = kmalloc(size, flags); ++ if (ret) ++ memset(ret, 0, size); ++ return ret; ++} ++#endif /* <= 2.6.13 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ) ++struct sk_buff *_kc_netdev_alloc_skb(struct net_device *dev, ++ unsigned int length) ++{ ++ /* 16 == NET_PAD_SKB */ ++ struct sk_buff *skb; ++ skb = alloc_skb(length + 16, GFP_ATOMIC); ++ if (likely(skb != NULL)) { ++ skb_reserve(skb, 16); ++ skb->dev = dev; ++ } ++ return skb; ++} ++#endif /* <= 2.6.17 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ) ++int _kc_pci_save_state(struct pci_dev *pdev) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int size = PCI_CONFIG_SPACE_LEN, i; ++ u16 pcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP); ++ u16 pcie_link_status; ++ ++ if (pcie_cap_offset) { ++ if (!pci_read_config_word(pdev, ++ pcie_cap_offset + PCIE_LINK_STATUS, ++ &pcie_link_status)) ++ size = PCIE_CONFIG_SPACE_LEN; ++ } ++ pci_config_space_ich8lan(); ++#ifdef HAVE_PCI_ERS ++ if (adapter->config_space == NULL) ++#else ++ WARN_ON(adapter->config_space != NULL); ++#endif ++ adapter->config_space = kmalloc(size, GFP_KERNEL); ++ if (!adapter->config_space) { ++ printk(KERN_ERR "Out of memory in pci_save_state\n"); ++ return -ENOMEM; ++ } ++ for (i = 0; i < (size / 4); i++) ++ pci_read_config_dword(pdev, i * 4, &adapter->config_space[i]); ++ return 0; ++} ++ ++void _kc_pci_restore_state(struct pci_dev * pdev) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int size = PCI_CONFIG_SPACE_LEN, i; ++ u16 pcie_cap_offset; ++ u16 pcie_link_status; ++ ++ if (adapter->config_space != NULL) { ++ pcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP); ++ if (pcie_cap_offset && ++ !pci_read_config_word(pdev, ++ pcie_cap_offset + PCIE_LINK_STATUS, ++ &pcie_link_status)) ++ size = PCIE_CONFIG_SPACE_LEN; ++ ++ pci_config_space_ich8lan(); ++ for (i = 0; i < (size / 4); i++) ++ pci_write_config_dword(pdev, i * 4, adapter->config_space[i]); ++#ifndef HAVE_PCI_ERS ++ kfree(adapter->config_space); ++ adapter->config_space = NULL; ++#endif ++ } ++} ++ ++#ifdef HAVE_PCI_ERS ++void _kc_free_netdev(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ ++ if (adapter->config_space != NULL) ++ kfree(adapter->config_space); ++#ifdef CONFIG_SYSFS ++ if (netdev->reg_state == NETREG_UNINITIALIZED) { ++ kfree((char *)netdev - netdev->padded); ++ } else { ++ BUG_ON(netdev->reg_state != NETREG_UNREGISTERED); ++ netdev->reg_state = NETREG_RELEASED; ++ class_device_put(&netdev->class_dev); ++ } ++#else ++ kfree((char *)netdev - netdev->padded); ++#endif ++} ++#endif ++#endif /* <= 2.6.18 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ) ++#ifdef NAPI ++ ++int __kc_adapter_clean(struct net_device *netdev, int *budget) ++{ ++ int work_done; ++ int work_to_do = min(*budget, netdev->quota); ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ struct napi_struct *napi = &adapter->rx_ring[0].napi; ++ work_done = napi->poll(napi, work_to_do); ++ *budget -= work_done; ++ netdev->quota -= work_done; ++ return (work_done >= work_to_do) ? 1 : 0; ++} ++#endif /* NAPI */ ++#endif /* <= 2.6.24 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) ++#ifdef HAVE_TX_MQ ++void _kc_netif_tx_stop_all_queues(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int i; ++ ++ netif_stop_queue(netdev); ++ if (netif_is_multiqueue(netdev)) ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ netif_stop_subqueue(netdev, i); ++} ++void _kc_netif_tx_wake_all_queues(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int i; ++ ++ netif_wake_queue(netdev); ++ if (netif_is_multiqueue(netdev)) ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ netif_wake_subqueue(netdev, i); ++} ++void _kc_netif_tx_start_all_queues(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int i; ++ ++ netif_start_queue(netdev); ++ if (netif_is_multiqueue(netdev)) ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ netif_start_subqueue(netdev, i); ++} ++#endif /* HAVE_TX_MQ */ ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) ++ ++int ++_kc_pci_prepare_to_sleep(struct pci_dev *dev) ++{ ++ pci_power_t target_state; ++ int error; ++ ++ target_state = pci_choose_state(dev, PMSG_SUSPEND); ++ ++ pci_enable_wake(dev, target_state, true); ++ ++ error = pci_set_power_state(dev, target_state); ++ ++ if (error) ++ pci_enable_wake(dev, target_state, false); ++ ++ return error; ++} ++ ++int ++_kc_pci_wake_from_d3(struct pci_dev *dev, bool enable) ++{ ++ int err; ++ ++ err = pci_enable_wake(dev, PCI_D3cold, enable); ++ if (err) ++ goto out; ++ ++ err = pci_enable_wake(dev, PCI_D3hot, enable); ++ ++out: ++ return err; ++} ++#endif /* < 2.6.28 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) ) ++#endif /* < 2.6.29 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ) ++#endif /* < 2.6.30 */ +diff -r b58885ce604a drivers/net/e1000/kcompat.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/kcompat.h Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,1742 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _KCOMPAT_H_ ++#define _KCOMPAT_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* NAPI enable/disable flags here */ ++/* set the default on 2.6.27 and newer kernels, if older ++ * kernel default to value of CONFIG_E1000_NAPI */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) ++#ifdef CONFIG_E1000_NAPI ++#define NAPI ++#endif ++#else ++#define NAPI ++#endif ++#ifdef E1000_NAPI ++#undef NAPI ++#define NAPI ++#endif ++#ifdef E1000_NO_NAPI ++#undef NAPI ++#endif ++ ++#define adapter_struct e1000_adapter ++#define adapter_q_vector e1000_rx_ring ++ ++/* and finally set defines so that the code sees the changes */ ++#ifdef NAPI ++#ifndef CONFIG_E1000_NAPI ++#define CONFIG_E1000_NAPI ++#endif ++#else ++#undef CONFIG_E1000_NAPI ++#endif /* NAPI */ ++ ++/* packet split disable/enable */ ++#ifdef DISABLE_PACKET_SPLIT ++#undef CONFIG_E1000_DISABLE_PACKET_SPLIT ++#define CONFIG_E1000_DISABLE_PACKET_SPLIT ++#undef CONFIG_IGB_DISABLE_PACKET_SPLIT ++#define CONFIG_IGB_DISABLE_PACKET_SPLIT ++#endif ++ ++/* MSI compatibility code for all kernels and drivers */ ++#ifdef DISABLE_PCI_MSI ++#undef CONFIG_PCI_MSI ++#endif ++#ifndef CONFIG_PCI_MSI ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) ) ++struct msix_entry { ++ u16 vector; /* kernel uses to write allocated vector */ ++ u16 entry; /* driver uses to specify entry, OS writes */ ++}; ++#endif ++#define pci_enable_msi(a) -ENOTSUPP ++#define pci_disable_msi(a) do {} while (0) ++#define pci_enable_msix(a, b, c) -ENOTSUPP ++#define pci_disable_msix(a) do {} while (0) ++#define msi_remove_pci_irq_vectors(a) do {} while (0) ++#endif /* CONFIG_PCI_MSI */ ++#ifdef DISABLE_PM ++#undef CONFIG_PM ++#endif ++ ++#ifdef DISABLE_NET_POLL_CONTROLLER ++#undef CONFIG_NET_POLL_CONTROLLER ++#endif ++ ++#ifndef PMSG_SUSPEND ++#define PMSG_SUSPEND 3 ++#endif ++ ++/* generic boolean compatibility */ ++#undef TRUE ++#undef FALSE ++#define TRUE true ++#define FALSE false ++#ifdef GCC_VERSION ++#if ( GCC_VERSION < 3000 ) ++#define _Bool char ++#endif ++#else ++#define _Bool char ++#endif ++#ifndef bool ++#define bool _Bool ++#define true 1 ++#define false 0 ++#endif ++ ++ ++#ifndef module_param ++#define module_param(v,t,p) MODULE_PARM(v, "i"); ++#endif ++ ++#ifndef DMA_64BIT_MASK ++#define DMA_64BIT_MASK 0xffffffffffffffffULL ++#endif ++ ++#ifndef DMA_32BIT_MASK ++#define DMA_32BIT_MASK 0x00000000ffffffffULL ++#endif ++ ++#ifndef PCI_CAP_ID_EXP ++#define PCI_CAP_ID_EXP 0x10 ++#endif ++ ++#ifndef PCIE_LINK_STATE_L0S ++#define PCIE_LINK_STATE_L0S 1 ++#endif ++ ++#ifndef mmiowb ++#ifdef CONFIG_IA64 ++#define mmiowb() asm volatile ("mf.a" ::: "memory") ++#else ++#define mmiowb() ++#endif ++#endif ++ ++#ifndef SET_NETDEV_DEV ++#define SET_NETDEV_DEV(net, pdev) ++#endif ++ ++#ifndef HAVE_FREE_NETDEV ++#define free_netdev(x) kfree(x) ++#endif ++ ++#ifdef HAVE_POLL_CONTROLLER ++#define CONFIG_NET_POLL_CONTROLLER ++#endif ++ ++#ifndef NETDEV_TX_OK ++#define NETDEV_TX_OK 0 ++#endif ++ ++#ifndef NETDEV_TX_BUSY ++#define NETDEV_TX_BUSY 1 ++#endif ++ ++#ifndef NETDEV_TX_LOCKED ++#define NETDEV_TX_LOCKED -1 ++#endif ++ ++#ifndef SKB_DATAREF_SHIFT ++/* if we do not have the infrastructure to detect if skb_header is cloned ++ just return false in all cases */ ++#define skb_header_cloned(x) 0 ++#endif ++ ++#ifndef NETIF_F_GSO ++#define gso_size tso_size ++#define gso_segs tso_segs ++#endif ++ ++#ifndef NETIF_F_GRO ++#define vlan_gro_receive(_napi, _vlgrp, _vlan, _skb) \ ++ vlan_hwaccel_receive_skb(_skb, _vlgrp, _vlan) ++#define napi_gro_receive(_napi, _skb) netif_receive_skb(_skb) ++#endif ++ ++#ifndef NETIF_F_SCTP_CSUM ++#define NETIF_F_SCTP_CSUM 0 ++#endif ++ ++#ifndef CHECKSUM_PARTIAL ++#define CHECKSUM_PARTIAL CHECKSUM_HW ++#define CHECKSUM_COMPLETE CHECKSUM_HW ++#endif ++ ++#ifndef __read_mostly ++#define __read_mostly ++#endif ++ ++#ifndef HAVE_NETIF_MSG ++#define HAVE_NETIF_MSG 1 ++enum { ++ NETIF_MSG_DRV = 0x0001, ++ NETIF_MSG_PROBE = 0x0002, ++ NETIF_MSG_LINK = 0x0004, ++ NETIF_MSG_TIMER = 0x0008, ++ NETIF_MSG_IFDOWN = 0x0010, ++ NETIF_MSG_IFUP = 0x0020, ++ NETIF_MSG_RX_ERR = 0x0040, ++ NETIF_MSG_TX_ERR = 0x0080, ++ NETIF_MSG_TX_QUEUED = 0x0100, ++ NETIF_MSG_INTR = 0x0200, ++ NETIF_MSG_TX_DONE = 0x0400, ++ NETIF_MSG_RX_STATUS = 0x0800, ++ NETIF_MSG_PKTDATA = 0x1000, ++ NETIF_MSG_HW = 0x2000, ++ NETIF_MSG_WOL = 0x4000, ++}; ++ ++#else ++#define NETIF_MSG_HW 0x2000 ++#define NETIF_MSG_WOL 0x4000 ++#endif /* HAVE_NETIF_MSG */ ++ ++#ifndef MII_RESV1 ++#define MII_RESV1 0x17 /* Reserved... */ ++#endif ++ ++#ifndef unlikely ++#define unlikely(_x) _x ++#define likely(_x) _x ++#endif ++ ++#ifndef WARN_ON ++#define WARN_ON(x) ++#endif ++ ++#ifndef PCI_DEVICE ++#define PCI_DEVICE(vend,dev) \ ++ .vendor = (vend), .device = (dev), \ ++ .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID ++#endif ++ ++#ifndef num_online_cpus ++#define num_online_cpus() smp_num_cpus ++#endif ++ ++#ifndef _LINUX_RANDOM_H ++#include ++#endif ++ ++#ifndef DECLARE_BITMAP ++#ifndef BITS_TO_LONGS ++#define BITS_TO_LONGS(bits) (((bits)+BITS_PER_LONG-1)/BITS_PER_LONG) ++#endif ++#define DECLARE_BITMAP(name,bits) long name[BITS_TO_LONGS(bits)] ++#endif ++ ++#ifndef VLAN_HLEN ++#define VLAN_HLEN 4 ++#endif ++ ++#ifndef VLAN_ETH_HLEN ++#define VLAN_ETH_HLEN 18 ++#endif ++ ++#ifndef VLAN_ETH_FRAME_LEN ++#define VLAN_ETH_FRAME_LEN 1518 ++#endif ++ ++#ifndef DCA_GET_TAG_TWO_ARGS ++#define dca3_get_tag(a,b) dca_get_tag(b) ++#endif ++ ++/*****************************************************************************/ ++/* Installations with ethtool version without eeprom, adapter id, or statistics ++ * support */ ++ ++#ifndef ETH_GSTRING_LEN ++#define ETH_GSTRING_LEN 32 ++#endif ++ ++#ifndef ETHTOOL_GSTATS ++#define ETHTOOL_GSTATS 0x1d ++#undef ethtool_drvinfo ++#define ethtool_drvinfo k_ethtool_drvinfo ++struct k_ethtool_drvinfo { ++ u32 cmd; ++ char driver[32]; ++ char version[32]; ++ char fw_version[32]; ++ char bus_info[32]; ++ char reserved1[32]; ++ char reserved2[16]; ++ u32 n_stats; ++ u32 testinfo_len; ++ u32 eedump_len; ++ u32 regdump_len; ++}; ++ ++struct ethtool_stats { ++ u32 cmd; ++ u32 n_stats; ++ u64 data[0]; ++}; ++#endif /* ETHTOOL_GSTATS */ ++ ++#ifndef ETHTOOL_PHYS_ID ++#define ETHTOOL_PHYS_ID 0x1c ++#endif /* ETHTOOL_PHYS_ID */ ++ ++#ifndef ETHTOOL_GSTRINGS ++#define ETHTOOL_GSTRINGS 0x1b ++enum ethtool_stringset { ++ ETH_SS_TEST = 0, ++ ETH_SS_STATS, ++}; ++struct ethtool_gstrings { ++ u32 cmd; /* ETHTOOL_GSTRINGS */ ++ u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/ ++ u32 len; /* number of strings in the string set */ ++ u8 data[0]; ++}; ++#endif /* ETHTOOL_GSTRINGS */ ++ ++#ifndef ETHTOOL_TEST ++#define ETHTOOL_TEST 0x1a ++enum ethtool_test_flags { ++ ETH_TEST_FL_OFFLINE = (1 << 0), ++ ETH_TEST_FL_FAILED = (1 << 1), ++}; ++struct ethtool_test { ++ u32 cmd; ++ u32 flags; ++ u32 reserved; ++ u32 len; ++ u64 data[0]; ++}; ++#endif /* ETHTOOL_TEST */ ++ ++#ifndef ETHTOOL_GEEPROM ++#define ETHTOOL_GEEPROM 0xb ++#undef ETHTOOL_GREGS ++struct ethtool_eeprom { ++ u32 cmd; ++ u32 magic; ++ u32 offset; ++ u32 len; ++ u8 data[0]; ++}; ++ ++struct ethtool_value { ++ u32 cmd; ++ u32 data; ++}; ++#endif /* ETHTOOL_GEEPROM */ ++ ++#ifndef ETHTOOL_GLINK ++#define ETHTOOL_GLINK 0xa ++#endif /* ETHTOOL_GLINK */ ++ ++#ifndef ETHTOOL_GREGS ++#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers */ ++#define ethtool_regs _kc_ethtool_regs ++/* for passing big chunks of data */ ++struct _kc_ethtool_regs { ++ u32 cmd; ++ u32 version; /* driver-specific, indicates different chips/revs */ ++ u32 len; /* bytes */ ++ u8 data[0]; ++}; ++#endif /* ETHTOOL_GREGS */ ++ ++#ifndef ETHTOOL_GMSGLVL ++#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */ ++#endif ++#ifndef ETHTOOL_SMSGLVL ++#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level, priv. */ ++#endif ++#ifndef ETHTOOL_NWAY_RST ++#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation, priv */ ++#endif ++#ifndef ETHTOOL_GLINK ++#define ETHTOOL_GLINK 0x0000000a /* Get link status */ ++#endif ++#ifndef ETHTOOL_GEEPROM ++#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */ ++#endif ++#ifndef ETHTOOL_SEEPROM ++#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */ ++#endif ++#ifndef ETHTOOL_GCOALESCE ++#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */ ++/* for configuring coalescing parameters of chip */ ++#define ethtool_coalesce _kc_ethtool_coalesce ++struct _kc_ethtool_coalesce { ++ u32 cmd; /* ETHTOOL_{G,S}COALESCE */ ++ ++ /* How many usecs to delay an RX interrupt after ++ * a packet arrives. If 0, only rx_max_coalesced_frames ++ * is used. ++ */ ++ u32 rx_coalesce_usecs; ++ ++ /* How many packets to delay an RX interrupt after ++ * a packet arrives. If 0, only rx_coalesce_usecs is ++ * used. It is illegal to set both usecs and max frames ++ * to zero as this would cause RX interrupts to never be ++ * generated. ++ */ ++ u32 rx_max_coalesced_frames; ++ ++ /* Same as above two parameters, except that these values ++ * apply while an IRQ is being serviced by the host. Not ++ * all cards support this feature and the values are ignored ++ * in that case. ++ */ ++ u32 rx_coalesce_usecs_irq; ++ u32 rx_max_coalesced_frames_irq; ++ ++ /* How many usecs to delay a TX interrupt after ++ * a packet is sent. If 0, only tx_max_coalesced_frames ++ * is used. ++ */ ++ u32 tx_coalesce_usecs; ++ ++ /* How many packets to delay a TX interrupt after ++ * a packet is sent. If 0, only tx_coalesce_usecs is ++ * used. It is illegal to set both usecs and max frames ++ * to zero as this would cause TX interrupts to never be ++ * generated. ++ */ ++ u32 tx_max_coalesced_frames; ++ ++ /* Same as above two parameters, except that these values ++ * apply while an IRQ is being serviced by the host. Not ++ * all cards support this feature and the values are ignored ++ * in that case. ++ */ ++ u32 tx_coalesce_usecs_irq; ++ u32 tx_max_coalesced_frames_irq; ++ ++ /* How many usecs to delay in-memory statistics ++ * block updates. Some drivers do not have an in-memory ++ * statistic block, and in such cases this value is ignored. ++ * This value must not be zero. ++ */ ++ u32 stats_block_coalesce_usecs; ++ ++ /* Adaptive RX/TX coalescing is an algorithm implemented by ++ * some drivers to improve latency under low packet rates and ++ * improve throughput under high packet rates. Some drivers ++ * only implement one of RX or TX adaptive coalescing. Anything ++ * not implemented by the driver causes these values to be ++ * silently ignored. ++ */ ++ u32 use_adaptive_rx_coalesce; ++ u32 use_adaptive_tx_coalesce; ++ ++ /* When the packet rate (measured in packets per second) ++ * is below pkt_rate_low, the {rx,tx}_*_low parameters are ++ * used. ++ */ ++ u32 pkt_rate_low; ++ u32 rx_coalesce_usecs_low; ++ u32 rx_max_coalesced_frames_low; ++ u32 tx_coalesce_usecs_low; ++ u32 tx_max_coalesced_frames_low; ++ ++ /* When the packet rate is below pkt_rate_high but above ++ * pkt_rate_low (both measured in packets per second) the ++ * normal {rx,tx}_* coalescing parameters are used. ++ */ ++ ++ /* When the packet rate is (measured in packets per second) ++ * is above pkt_rate_high, the {rx,tx}_*_high parameters are ++ * used. ++ */ ++ u32 pkt_rate_high; ++ u32 rx_coalesce_usecs_high; ++ u32 rx_max_coalesced_frames_high; ++ u32 tx_coalesce_usecs_high; ++ u32 tx_max_coalesced_frames_high; ++ ++ /* How often to do adaptive coalescing packet rate sampling, ++ * measured in seconds. Must not be zero. ++ */ ++ u32 rate_sample_interval; ++}; ++#endif /* ETHTOOL_GCOALESCE */ ++ ++#ifndef ETHTOOL_SCOALESCE ++#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */ ++#endif ++#ifndef ETHTOOL_GRINGPARAM ++#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */ ++/* for configuring RX/TX ring parameters */ ++#define ethtool_ringparam _kc_ethtool_ringparam ++struct _kc_ethtool_ringparam { ++ u32 cmd; /* ETHTOOL_{G,S}RINGPARAM */ ++ ++ /* Read only attributes. These indicate the maximum number ++ * of pending RX/TX ring entries the driver will allow the ++ * user to set. ++ */ ++ u32 rx_max_pending; ++ u32 rx_mini_max_pending; ++ u32 rx_jumbo_max_pending; ++ u32 tx_max_pending; ++ ++ /* Values changeable by the user. The valid values are ++ * in the range 1 to the "*_max_pending" counterpart above. ++ */ ++ u32 rx_pending; ++ u32 rx_mini_pending; ++ u32 rx_jumbo_pending; ++ u32 tx_pending; ++}; ++#endif /* ETHTOOL_GRINGPARAM */ ++ ++#ifndef ETHTOOL_SRINGPARAM ++#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters, priv. */ ++#endif ++#ifndef ETHTOOL_GPAUSEPARAM ++#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */ ++/* for configuring link flow control parameters */ ++#define ethtool_pauseparam _kc_ethtool_pauseparam ++struct _kc_ethtool_pauseparam { ++ u32 cmd; /* ETHTOOL_{G,S}PAUSEPARAM */ ++ ++ /* If the link is being auto-negotiated (via ethtool_cmd.autoneg ++ * being true) the user may set 'autoneg' here non-zero to have the ++ * pause parameters be auto-negotiated too. In such a case, the ++ * {rx,tx}_pause values below determine what capabilities are ++ * advertised. ++ * ++ * If 'autoneg' is zero or the link is not being auto-negotiated, ++ * then {rx,tx}_pause force the driver to use/not-use pause ++ * flow control. ++ */ ++ u32 autoneg; ++ u32 rx_pause; ++ u32 tx_pause; ++}; ++#endif /* ETHTOOL_GPAUSEPARAM */ ++ ++#ifndef ETHTOOL_SPAUSEPARAM ++#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */ ++#endif ++#ifndef ETHTOOL_GRXCSUM ++#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_SRXCSUM ++#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_GTXCSUM ++#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_STXCSUM ++#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_GSG ++#define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable ++ * (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_SSG ++#define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable ++ * (ethtool_value). */ ++#endif ++#ifndef ETHTOOL_TEST ++#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test, priv. */ ++#endif ++#ifndef ETHTOOL_GSTRINGS ++#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */ ++#endif ++#ifndef ETHTOOL_PHYS_ID ++#define ETHTOOL_PHYS_ID 0x0000001c /* identify the NIC */ ++#endif ++#ifndef ETHTOOL_GSTATS ++#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */ ++#endif ++#ifndef ETHTOOL_GTSO ++#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_STSO ++#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */ ++#endif ++ ++#ifndef ETHTOOL_BUSINFO_LEN ++#define ETHTOOL_BUSINFO_LEN 32 ++#endif ++ ++/*****************************************************************************/ ++/* 2.4.3 => 2.4.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) ) ++ ++/**************************************/ ++/* PCI DRIVER API */ ++ ++#ifndef pci_set_dma_mask ++#define pci_set_dma_mask _kc_pci_set_dma_mask ++extern int _kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask); ++#endif ++ ++#ifndef pci_request_regions ++#define pci_request_regions _kc_pci_request_regions ++extern int _kc_pci_request_regions(struct pci_dev *pdev, char *res_name); ++#endif ++ ++#ifndef pci_release_regions ++#define pci_release_regions _kc_pci_release_regions ++extern void _kc_pci_release_regions(struct pci_dev *pdev); ++#endif ++ ++/**************************************/ ++/* NETWORK DRIVER API */ ++ ++#ifndef alloc_etherdev ++#define alloc_etherdev _kc_alloc_etherdev ++extern struct net_device * _kc_alloc_etherdev(int sizeof_priv); ++#endif ++ ++#ifndef is_valid_ether_addr ++#define is_valid_ether_addr _kc_is_valid_ether_addr ++extern int _kc_is_valid_ether_addr(u8 *addr); ++#endif ++ ++/**************************************/ ++/* MISCELLANEOUS */ ++ ++#ifndef INIT_TQUEUE ++#define INIT_TQUEUE(_tq, _routine, _data) \ ++ do { \ ++ INIT_LIST_HEAD(&(_tq)->list); \ ++ (_tq)->sync = 0; \ ++ (_tq)->routine = _routine; \ ++ (_tq)->data = _data; \ ++ } while (0) ++#endif ++ ++#endif /* 2.4.3 => 2.4.0 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,5) ) ++/* Generic MII registers. */ ++#define MII_BMCR 0x00 /* Basic mode control register */ ++#define MII_BMSR 0x01 /* Basic mode status register */ ++#define MII_PHYSID1 0x02 /* PHYS ID 1 */ ++#define MII_PHYSID2 0x03 /* PHYS ID 2 */ ++#define MII_ADVERTISE 0x04 /* Advertisement control reg */ ++#define MII_LPA 0x05 /* Link partner ability reg */ ++#define MII_EXPANSION 0x06 /* Expansion register */ ++/* Basic mode control register. */ ++#define BMCR_FULLDPLX 0x0100 /* Full duplex */ ++#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ ++/* Basic mode status register. */ ++#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ ++#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ ++#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ ++#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ ++#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ ++#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ ++/* Advertisement control register. */ ++#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ ++#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ ++#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ ++#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ ++#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ ++#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ++ ADVERTISE_100HALF | ADVERTISE_100FULL) ++/* Expansion register for auto-negotiation. */ ++#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ ++#endif ++ ++/*****************************************************************************/ ++/* 2.4.6 => 2.4.3 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) ) ++ ++#ifndef pci_set_power_state ++#define pci_set_power_state _kc_pci_set_power_state ++extern int _kc_pci_set_power_state(struct pci_dev *dev, int state); ++#endif ++ ++#ifndef pci_enable_wake ++#define pci_enable_wake _kc_pci_enable_wake ++extern int _kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable); ++#endif ++ ++#ifndef pci_disable_device ++#define pci_disable_device _kc_pci_disable_device ++extern void _kc_pci_disable_device(struct pci_dev *pdev); ++#endif ++ ++/* PCI PM entry point syntax changed, so don't support suspend/resume */ ++#undef CONFIG_PM ++ ++#endif /* 2.4.6 => 2.4.3 */ ++ ++#ifndef HAVE_PCI_SET_MWI ++#define pci_set_mwi(X) pci_write_config_word(X, \ ++ PCI_COMMAND, adapter->hw.bus.pci_cmd_word | \ ++ PCI_COMMAND_INVALIDATE); ++#define pci_clear_mwi(X) pci_write_config_word(X, \ ++ PCI_COMMAND, adapter->hw.bus.pci_cmd_word & \ ++ ~PCI_COMMAND_INVALIDATE); ++#endif ++ ++/*****************************************************************************/ ++/* 2.4.10 => 2.4.9 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,10) ) ++ ++/**************************************/ ++/* MODULE API */ ++ ++#ifndef MODULE_LICENSE ++ #define MODULE_LICENSE(X) ++#endif ++ ++/**************************************/ ++/* OTHER */ ++ ++#undef min ++#define min(x,y) ({ \ ++ const typeof(x) _x = (x); \ ++ const typeof(y) _y = (y); \ ++ (void) (&_x == &_y); \ ++ _x < _y ? _x : _y; }) ++ ++#undef max ++#define max(x,y) ({ \ ++ const typeof(x) _x = (x); \ ++ const typeof(y) _y = (y); \ ++ (void) (&_x == &_y); \ ++ _x > _y ? _x : _y; }) ++ ++#define min_t(type,x,y) ({ \ ++ type _x = (x); \ ++ type _y = (y); \ ++ _x < _y ? _x : _y; }) ++ ++#define max_t(type,x,y) ({ \ ++ type _x = (x); \ ++ type _y = (y); \ ++ _x > _y ? _x : _y; }) ++ ++#ifndef list_for_each_safe ++#define list_for_each_safe(pos, n, head) \ ++ for (pos = (head)->next, n = pos->next; pos != (head); \ ++ pos = n, n = pos->next) ++#endif ++ ++#endif /* 2.4.10 -> 2.4.6 */ ++ ++ ++/*****************************************************************************/ ++/* 2.4.13 => 2.4.10 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) ) ++ ++/**************************************/ ++/* PCI DMA MAPPING */ ++ ++#ifndef virt_to_page ++ #define virt_to_page(v) (mem_map + (virt_to_phys(v) >> PAGE_SHIFT)) ++#endif ++ ++#ifndef pci_map_page ++#define pci_map_page _kc_pci_map_page ++extern u64 _kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, size_t size, int direction); ++#endif ++ ++#ifndef pci_unmap_page ++#define pci_unmap_page _kc_pci_unmap_page ++extern void _kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, int direction); ++#endif ++ ++/* pci_set_dma_mask takes dma_addr_t, which is only 32-bits prior to 2.4.13 */ ++ ++#undef DMA_32BIT_MASK ++#define DMA_32BIT_MASK 0xffffffff ++#undef DMA_64BIT_MASK ++#define DMA_64BIT_MASK 0xffffffff ++ ++/**************************************/ ++/* OTHER */ ++ ++#ifndef cpu_relax ++#define cpu_relax() rep_nop() ++#endif ++ ++struct vlan_ethhdr { ++ unsigned char h_dest[ETH_ALEN]; ++ unsigned char h_source[ETH_ALEN]; ++ unsigned short h_vlan_proto; ++ unsigned short h_vlan_TCI; ++ unsigned short h_vlan_encapsulated_proto; ++}; ++#endif /* 2.4.13 => 2.4.10 */ ++ ++/*****************************************************************************/ ++/* 2.4.17 => 2.4.12 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17) ) ++ ++#ifndef __devexit_p ++ #define __devexit_p(x) &(x) ++#endif ++ ++#endif /* 2.4.17 => 2.4.13 */ ++ ++/*****************************************************************************/ ++/* 2.4.20 => 2.4.19 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,20) ) ++ ++/* we won't support NAPI on less than 2.4.20 */ ++#ifdef NAPI ++#undef NAPI ++#undef CONFIG_E1000_NAPI ++#endif ++ ++#endif /* 2.4.20 => 2.4.19 */ ++ ++/*****************************************************************************/ ++/* < 2.4.21 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,21) ) ++#define skb_pad(x,y) _kc_skb_pad(x, y) ++struct sk_buff * _kc_skb_pad(struct sk_buff *skb, int pad); ++#endif /* < 2.4.21 */ ++ ++/*****************************************************************************/ ++/* 2.4.22 => 2.4.17 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) ) ++#define pci_name(x) ((x)->slot_name) ++#endif ++ ++/*****************************************************************************/ ++/*****************************************************************************/ ++/* 2.4.23 => 2.4.22 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23) ) ++/*****************************************************************************/ ++#ifdef NAPI ++#ifndef netif_poll_disable ++#define netif_poll_disable(x) _kc_netif_poll_disable(x) ++static inline void _kc_netif_poll_disable(struct net_device *netdev) ++{ ++ while (test_and_set_bit(__LINK_STATE_RX_SCHED, &netdev->state)) { ++ /* No hurry */ ++ current->state = TASK_INTERRUPTIBLE; ++ schedule_timeout(1); ++ } ++} ++#endif ++ ++#ifndef netif_poll_enable ++#define netif_poll_enable(x) _kc_netif_poll_enable(x) ++static inline void _kc_netif_poll_enable(struct net_device *netdev) ++{ ++ clear_bit(__LINK_STATE_RX_SCHED, &netdev->state); ++} ++#endif ++#endif /* NAPI */ ++#ifndef netif_tx_disable ++#define netif_tx_disable(x) _kc_netif_tx_disable(x) ++static inline void _kc_netif_tx_disable(struct net_device *dev) ++{ ++ spin_lock_bh(&dev->xmit_lock); ++ netif_stop_queue(dev); ++ spin_unlock_bh(&dev->xmit_lock); ++} ++#endif ++#endif /* 2.4.23 => 2.4.22 */ ++ ++/*****************************************************************************/ ++/* 2.6.4 => 2.6.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,25) || \ ++ ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \ ++ LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) ) ++#define ETHTOOL_OPS_COMPAT ++#endif /* 2.6.4 => 2.6.0 */ ++ ++/*****************************************************************************/ ++/* 2.5.71 => 2.4.x */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,71) ) ++#define sk_protocol protocol ++#define pci_get_device pci_find_device ++#endif /* 2.5.70 => 2.4.x */ ++ ++/*****************************************************************************/ ++/* < 2.4.27 or 2.6.0 <= 2.6.5 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) || \ ++ ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \ ++ LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) ) ++ ++#ifndef netif_msg_init ++#define netif_msg_init _kc_netif_msg_init ++static inline u32 _kc_netif_msg_init(int debug_value, int default_msg_enable_bits) ++{ ++ /* use default */ ++ if (debug_value < 0 || debug_value >= (sizeof(u32) * 8)) ++ return default_msg_enable_bits; ++ if (debug_value == 0) /* no output */ ++ return 0; ++ /* set low N bits */ ++ return (1 << debug_value) -1; ++} ++#endif ++ ++#endif /* < 2.4.27 or 2.6.0 <= 2.6.5 */ ++/*****************************************************************************/ ++#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \ ++ (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \ ++ ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) ))) ++#define netdev_priv(x) x->priv ++#endif ++ ++/*****************************************************************************/ ++/* <= 2.5.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ) ++#undef pci_register_driver ++#define pci_register_driver pci_module_init ++ ++#define dev_err(__unused_dev, format, arg...) \ ++ printk(KERN_ERR "%s: " format, pci_name(adapter->pdev) , ## arg) ++#define dev_warn(__unused_dev, format, arg...) \ ++ printk(KERN_WARNING "%s: " format, pci_name(pdev) , ## arg) ++ ++/* hlist_* code - double linked lists */ ++struct hlist_head { ++ struct hlist_node *first; ++}; ++ ++struct hlist_node { ++ struct hlist_node *next, **pprev; ++}; ++ ++static inline void __hlist_del(struct hlist_node *n) ++{ ++ struct hlist_node *next = n->next; ++ struct hlist_node **pprev = n->pprev; ++ *pprev = next; ++ if (next) ++ next->pprev = pprev; ++} ++ ++static inline void hlist_del(struct hlist_node *n) ++{ ++ __hlist_del(n); ++ n->next = NULL; ++ n->pprev = NULL; ++} ++ ++static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) ++{ ++ struct hlist_node *first = h->first; ++ n->next = first; ++ if (first) ++ first->pprev = &n->next; ++ h->first = n; ++ n->pprev = &h->first; ++} ++ ++static inline int hlist_empty(const struct hlist_head *h) ++{ ++ return !h->first; ++} ++#define HLIST_HEAD_INIT { .first = NULL } ++#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL } ++#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL) ++static inline void INIT_HLIST_NODE(struct hlist_node *h) ++{ ++ h->next = NULL; ++ h->pprev = NULL; ++} ++#define hlist_entry(ptr, type, member) container_of(ptr,type,member) ++ ++#define hlist_for_each_entry(tpos, pos, head, member) \ ++ for (pos = (head)->first; \ ++ pos && ({ prefetch(pos->next); 1;}) && \ ++ ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ ++ pos = pos->next) ++ ++#define hlist_for_each_entry_safe(tpos, pos, n, head, member) \ ++ for (pos = (head)->first; \ ++ pos && ({ n = pos->next; 1; }) && \ ++ ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ ++ pos = n) ++ ++/* we ignore GFP here */ ++#define dma_alloc_coherent(dv, sz, dma, gfp) \ ++ pci_alloc_consistent(pdev, (sz), (dma)) ++#define dma_free_coherent(dv, sz, addr, dma_addr) \ ++ pci_free_consistent(pdev, (sz), (addr), (dma_addr)) ++ ++#ifndef might_sleep ++#define might_sleep() ++#endif ++ ++#endif /* <= 2.5.0 */ ++ ++/*****************************************************************************/ ++/* 2.5.28 => 2.4.23 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) ) ++ ++static inline void _kc_synchronize_irq(void) ++{ ++ synchronize_irq(); ++} ++#undef synchronize_irq ++#define synchronize_irq(X) _kc_synchronize_irq() ++ ++#include ++#define work_struct tq_struct ++#undef INIT_WORK ++#define INIT_WORK(a,b) INIT_TQUEUE(a,(void (*)(void *))b,a) ++#undef container_of ++#define container_of list_entry ++#define schedule_work schedule_task ++#define flush_scheduled_work flush_scheduled_tasks ++#define cancel_work_sync(x) flush_scheduled_work() ++ ++#endif /* 2.5.28 => 2.4.17 */ ++ ++/*****************************************************************************/ ++/* 2.6.0 => 2.5.28 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) ++#define MODULE_INFO(version, _version) ++#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT ++#define CONFIG_IGB_DISABLE_PACKET_SPLIT 1 ++#endif ++ ++#define pci_set_consistent_dma_mask(dev,mask) 1 ++ ++#undef dev_put ++#define dev_put(dev) __dev_put(dev) ++ ++#ifndef skb_fill_page_desc ++#define skb_fill_page_desc _kc_skb_fill_page_desc ++extern void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int off, int size); ++#endif ++ ++#undef ALIGN ++#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1)) ++ ++#ifndef page_count ++#define page_count(p) atomic_read(&(p)->count) ++#endif ++ ++/* find_first_bit and find_next bit are not defined for most ++ * 2.4 kernels (except for the redhat 2.4.21 kernels ++ */ ++#include ++#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG) ++#undef find_next_bit ++#define find_next_bit _kc_find_next_bit ++extern unsigned long _kc_find_next_bit(const unsigned long *addr, ++ unsigned long size, ++ unsigned long offset); ++#define find_first_bit(addr, size) find_next_bit((addr), (size), 0) ++ ++#endif /* 2.6.0 => 2.5.28 */ ++ ++/*****************************************************************************/ ++/* 2.6.4 => 2.6.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) ++#define MODULE_VERSION(_version) MODULE_INFO(version, _version) ++#endif /* 2.6.4 => 2.6.0 */ ++ ++/*****************************************************************************/ ++/* 2.6.5 => 2.6.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) ++#define pci_dma_sync_single_for_cpu pci_dma_sync_single ++#define pci_dma_sync_single_for_device pci_dma_sync_single_for_cpu ++#endif /* 2.6.5 => 2.6.0 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,6) ) ++/* taken from 2.6 include/linux/bitmap.h */ ++#undef bitmap_zero ++#define bitmap_zero _kc_bitmap_zero ++static inline void _kc_bitmap_zero(unsigned long *dst, int nbits) ++{ ++ if (nbits <= BITS_PER_LONG) ++ *dst = 0UL; ++ else { ++ int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long); ++ memset(dst, 0, len); ++ } ++} ++#define random_ether_addr _kc_random_ether_addr ++static inline void _kc_random_ether_addr(u8 *addr) ++{ ++ get_random_bytes(addr, ETH_ALEN); ++ addr[0] &= 0xfe; /* clear multicast */ ++ addr[0] |= 0x02; /* set local assignment */ ++} ++#endif /* < 2.6.6 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) ) ++#undef if_mii ++#define if_mii _kc_if_mii ++static inline struct mii_ioctl_data *_kc_if_mii(struct ifreq *rq) ++{ ++ return (struct mii_ioctl_data *) &rq->ifr_ifru; ++} ++#endif /* < 2.6.7 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) ) ++#ifndef PCI_EXP_DEVCTL ++#define PCI_EXP_DEVCTL 8 ++#endif ++#ifndef PCI_EXP_DEVCTL_CERE ++#define PCI_EXP_DEVCTL_CERE 0x0001 ++#endif ++#define msleep(x) do { set_current_state(TASK_UNINTERRUPTIBLE); \ ++ schedule_timeout((x * HZ)/1000 + 2); \ ++ } while (0) ++ ++#endif /* < 2.6.8 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)) ++#include ++#define __iomem ++ ++#ifndef kcalloc ++#define kcalloc(n, size, flags) _kc_kzalloc(((n) * (size)), flags) ++extern void *_kc_kzalloc(size_t size, int flags); ++#endif ++#define MSEC_PER_SEC 1000L ++static inline unsigned int _kc_jiffies_to_msecs(const unsigned long j) ++{ ++#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) ++ return (MSEC_PER_SEC / HZ) * j; ++#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) ++ return (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC); ++#else ++ return (j * MSEC_PER_SEC) / HZ; ++#endif ++} ++static inline unsigned long _kc_msecs_to_jiffies(const unsigned int m) ++{ ++ if (m > _kc_jiffies_to_msecs(MAX_JIFFY_OFFSET)) ++ return MAX_JIFFY_OFFSET; ++#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) ++ return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ); ++#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) ++ return m * (HZ / MSEC_PER_SEC); ++#else ++ return (m * HZ + MSEC_PER_SEC - 1) / MSEC_PER_SEC; ++#endif ++} ++ ++#define msleep_interruptible _kc_msleep_interruptible ++static inline unsigned long _kc_msleep_interruptible(unsigned int msecs) ++{ ++ unsigned long timeout = _kc_msecs_to_jiffies(msecs) + 1; ++ ++ while (timeout && !signal_pending(current)) { ++ __set_current_state(TASK_INTERRUPTIBLE); ++ timeout = schedule_timeout(timeout); ++ } ++ return _kc_jiffies_to_msecs(timeout); ++} ++ ++/* Basic mode control register. */ ++#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ ++ ++#ifndef __le16 ++#define __le16 u16 ++#endif ++#ifndef __le32 ++#define __le32 u32 ++#endif ++#ifndef __le64 ++#define __le64 u64 ++#endif ++#ifndef __be16 ++#define __be16 u16 ++#endif ++ ++#ifdef pci_dma_mapping_error ++#undef pci_dma_mapping_error ++#endif ++#define pci_dma_mapping_error _kc_pci_dma_mapping_error ++static inline int _kc_pci_dma_mapping_error(struct pci_dev *pdev, ++ dma_addr_t dma_addr) ++{ ++ return dma_addr == 0; ++} ++#endif /* < 2.6.9 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ) ++#ifdef module_param_array_named ++#undef module_param_array_named ++#define module_param_array_named(name, array, type, nump, perm) \ ++ static struct kparam_array __param_arr_##name \ ++ = { ARRAY_SIZE(array), nump, param_set_##type, param_get_##type, \ ++ sizeof(array[0]), array }; \ ++ module_param_call(name, param_array_set, param_array_get, \ ++ &__param_arr_##name, perm) ++#endif /* module_param_array_named */ ++#endif /* < 2.6.10 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) ) ++#define PCI_D0 0 ++#define PCI_D1 1 ++#define PCI_D2 2 ++#define PCI_D3hot 3 ++#define PCI_D3cold 4 ++typedef int pci_power_t; ++#define pci_choose_state(pdev,state) state ++#define PMSG_SUSPEND 3 ++#define PCI_EXP_LNKCTL 16 ++ ++#undef NETIF_F_LLTX ++ ++#ifndef ARCH_HAS_PREFETCH ++#define prefetch(X) ++#endif ++ ++#ifndef NET_IP_ALIGN ++#define NET_IP_ALIGN 2 ++#endif ++ ++#define KC_USEC_PER_SEC 1000000L ++#define usecs_to_jiffies _kc_usecs_to_jiffies ++static inline unsigned int _kc_jiffies_to_usecs(const unsigned long j) ++{ ++#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ) ++ return (KC_USEC_PER_SEC / HZ) * j; ++#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC) ++ return (j + (HZ / KC_USEC_PER_SEC) - 1)/(HZ / KC_USEC_PER_SEC); ++#else ++ return (j * KC_USEC_PER_SEC) / HZ; ++#endif ++} ++static inline unsigned long _kc_usecs_to_jiffies(const unsigned int m) ++{ ++ if (m > _kc_jiffies_to_usecs(MAX_JIFFY_OFFSET)) ++ return MAX_JIFFY_OFFSET; ++#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ) ++ return (m + (KC_USEC_PER_SEC / HZ) - 1) / (KC_USEC_PER_SEC / HZ); ++#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC) ++ return m * (HZ / KC_USEC_PER_SEC); ++#else ++ return (m * HZ + KC_USEC_PER_SEC - 1) / KC_USEC_PER_SEC; ++#endif ++} ++#endif /* < 2.6.11 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,12) ) ++#include ++#define USE_REBOOT_NOTIFIER ++ ++/* Generic MII registers. */ ++#define MII_CTRL1000 0x09 /* 1000BASE-T control */ ++#define MII_STAT1000 0x0a /* 1000BASE-T status */ ++/* Advertisement control register. */ ++#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ ++#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymmetric pause */ ++/* 1000BASE-T Control register */ ++#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ ++#endif /* < 2.6.12 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) ) ++#define pm_message_t u32 ++#ifndef kzalloc ++#define kzalloc _kc_kzalloc ++extern void *_kc_kzalloc(size_t size, int flags); ++#endif ++ ++/* Generic MII registers. */ ++#define MII_ESTATUS 0x0f /* Extended Status */ ++/* Basic mode status register. */ ++#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ ++/* Extended status register. */ ++#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ ++#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ ++#endif /* < 2.6.14 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) ) ++#ifndef device_can_wakeup ++#define device_can_wakeup(dev) (1) ++#endif ++#ifndef device_set_wakeup_enable ++#define device_set_wakeup_enable(dev, val) do{}while(0) ++#endif ++#ifndef device_init_wakeup ++#define device_init_wakeup(dev,val) do {} while (0) ++#endif ++#endif /* < 2.6.15 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) ) ++#undef DEFINE_MUTEX ++#define DEFINE_MUTEX(x) DECLARE_MUTEX(x) ++#define mutex_lock(x) down_interruptible(x) ++#define mutex_unlock(x) up(x) ++ ++#undef HAVE_PCI_ERS ++#else /* 2.6.16 and above */ ++#undef HAVE_PCI_ERS ++#define HAVE_PCI_ERS ++#endif /* < 2.6.16 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ) ++ ++#ifndef IRQ_HANDLED ++#define irqreturn_t void ++#define IRQ_HANDLED ++#define IRQ_NONE ++#endif ++ ++#ifndef IRQF_PROBE_SHARED ++#ifdef SA_PROBEIRQ ++#define IRQF_PROBE_SHARED SA_PROBEIRQ ++#else ++#define IRQF_PROBE_SHARED 0 ++#endif ++#endif ++ ++#ifndef IRQF_SHARED ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#ifndef ARRAY_SIZE ++#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) ++#endif ++ ++#ifndef netdev_alloc_skb ++#define netdev_alloc_skb _kc_netdev_alloc_skb ++extern struct sk_buff *_kc_netdev_alloc_skb(struct net_device *dev, ++ unsigned int length); ++#endif ++ ++#ifndef skb_is_gso ++#ifdef NETIF_F_TSO ++#define skb_is_gso _kc_skb_is_gso ++static inline int _kc_skb_is_gso(const struct sk_buff *skb) ++{ ++ return skb_shinfo(skb)->gso_size; ++} ++#else ++#define skb_is_gso(a) 0 ++#endif ++#endif ++ ++#endif /* < 2.6.18 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ) ++ ++#ifndef DIV_ROUND_UP ++#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) ++#endif ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) ) ++#ifndef RHEL_RELEASE_CODE ++#define RHEL_RELEASE_CODE 0 ++#endif ++#ifndef RHEL_RELEASE_VERSION ++#define RHEL_RELEASE_VERSION(a,b) 0 ++#endif ++#ifndef AX_RELEASE_CODE ++#define AX_RELEASE_CODE 0 ++#endif ++#ifndef AX_RELEASE_VERSION ++#define AX_RELEASE_VERSION(a,b) 0 ++#endif ++#if (!(( RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,4) ) && ( RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0) ) || ( RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,0) ) || (AX_RELEASE_CODE > AX_RELEASE_VERSION(3,0)))) ++typedef irqreturn_t (*irq_handler_t)(int, void*, struct pt_regs *); ++#endif ++#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0)) ++#undef CONFIG_INET_LRO ++#undef CONFIG_INET_LRO_MODULE ++#ifdef IXGBE_FCOE ++#undef CONFIG_FCOE ++#undef CONFIG_FCOE_MODULE ++#endif /* IXGBE_FCOE */ ++#endif ++typedef irqreturn_t (*new_handler_t)(int, void*); ++static inline irqreturn_t _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id) ++#else /* 2.4.x */ ++typedef void (*irq_handler_t)(int, void*, struct pt_regs *); ++typedef void (*new_handler_t)(int, void*); ++static inline int _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id) ++#endif /* >= 2.5.x */ ++{ ++ irq_handler_t new_handler = (irq_handler_t) handler; ++ return request_irq(irq, new_handler, flags, devname, dev_id); ++} ++ ++#undef request_irq ++#define request_irq(irq, handler, flags, devname, dev_id) _kc_request_irq((irq), (handler), (flags), (devname), (dev_id)) ++ ++#define irq_handler_t new_handler_t ++/* pci_restore_state and pci_save_state handles MSI/PCIE from 2.6.19 */ ++#define PCIE_CONFIG_SPACE_LEN 256 ++#define PCI_CONFIG_SPACE_LEN 64 ++#define PCIE_LINK_STATUS 0x12 ++#define pci_config_space_ich8lan() do {} while(0) ++#undef pci_save_state ++extern int _kc_pci_save_state(struct pci_dev *); ++#define pci_save_state(pdev) _kc_pci_save_state(pdev) ++#undef pci_restore_state ++extern void _kc_pci_restore_state(struct pci_dev *); ++#define pci_restore_state(pdev) _kc_pci_restore_state(pdev) ++#ifdef HAVE_PCI_ERS ++#undef free_netdev ++extern void _kc_free_netdev(struct net_device *); ++#define free_netdev(netdev) _kc_free_netdev(netdev) ++#endif ++static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev) ++{ ++ return 0; ++} ++#define pci_disable_pcie_error_reporting(dev) do {} while (0) ++#define pci_cleanup_aer_uncorrect_error_status(dev) do {} while (0) ++#else /* 2.6.19 */ ++#include ++#endif /* < 2.6.19 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ) ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,28) ) ++#undef INIT_WORK ++#define INIT_WORK(_work, _func) \ ++do { \ ++ INIT_LIST_HEAD(&(_work)->entry); \ ++ (_work)->pending = 0; \ ++ (_work)->func = (void (*)(void *))_func; \ ++ (_work)->data = _work; \ ++ init_timer(&(_work)->timer); \ ++} while (0) ++#endif ++ ++#ifndef PCI_VDEVICE ++#define PCI_VDEVICE(ven, dev) \ ++ PCI_VENDOR_ID_##ven, (dev), \ ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0 ++#endif ++ ++#ifndef round_jiffies ++#define round_jiffies(x) x ++#endif ++ ++#define csum_offset csum ++ ++#endif /* < 2.6.20 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) ) ++#define to_net_dev(class) container_of(class, struct net_device, class_dev) ++#define NETDEV_CLASS_DEV ++#define vlan_group_get_device(vg, id) (vg->vlan_devices[id]) ++#define vlan_group_set_device(vg, id, dev) if (vg) vg->vlan_devices[id] = dev; ++#define pci_channel_offline(pdev) (pdev->error_state && \ ++ pdev->error_state != pci_channel_io_normal) ++#define pci_request_selected_regions(pdev, bars, name) \ ++ pci_request_regions(pdev, name) ++#define pci_release_selected_regions(pdev, bars) pci_release_regions(pdev); ++#endif /* < 2.6.21 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) ) ++#define tcp_hdr(skb) (skb->h.th) ++#define tcp_hdrlen(skb) (skb->h.th->doff << 2) ++#define skb_transport_offset(skb) (skb->h.raw - skb->data) ++#define skb_transport_header(skb) (skb->h.raw) ++#define ipv6_hdr(skb) (skb->nh.ipv6h) ++#define ip_hdr(skb) (skb->nh.iph) ++#define skb_network_offset(skb) (skb->nh.raw - skb->data) ++#define skb_network_header(skb) (skb->nh.raw) ++#define skb_tail_pointer(skb) skb->tail ++#define skb_copy_to_linear_data_offset(skb, offset, from, len) \ ++ memcpy(skb->data + offset, from, len) ++#define skb_network_header_len(skb) (skb->h.raw - skb->nh.raw) ++#define pci_register_driver pci_module_init ++#define skb_mac_header(skb) skb->mac.raw ++ ++#ifndef alloc_etherdev_mq ++#define alloc_etherdev_mq(_a, _b) alloc_etherdev(_a) ++#endif ++ ++#ifndef ETH_FCS_LEN ++#define ETH_FCS_LEN 4 ++#endif ++#define cancel_work_sync(x) flush_scheduled_work() ++#ifndef udp_hdr ++#define udp_hdr _udp_hdr ++static inline struct udphdr *_udp_hdr(const struct sk_buff *skb) ++{ ++ return (struct udphdr *)skb_transport_header(skb); ++} ++#endif ++#endif /* < 2.6.22 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) ) ++#undef ETHTOOL_GPERMADDR ++#undef SET_MODULE_OWNER ++#define SET_MODULE_OWNER(dev) do { } while (0) ++#endif /* > 2.6.22 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ) ++#define netif_subqueue_stopped(_a, _b) 0 ++#endif /* < 2.6.23 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ) ++/* if GRO is supported then the napi struct must already exist */ ++#ifndef NETIF_F_GRO ++/* NAPI API changes in 2.6.24 break everything */ ++struct napi_struct { ++ /* used to look up the real NAPI polling routine */ ++ int (*poll)(struct napi_struct *, int); ++ struct net_device *dev; ++ int weight; ++}; ++#endif ++ ++#ifdef NAPI ++extern int __kc_adapter_clean(struct net_device *, int *); ++#define napi_to_poll_dev(_napi) (_napi)->dev ++#define napi_enable(_napi) netif_poll_enable((_napi)->dev) ++#define napi_disable(_napi) netif_poll_disable((_napi)->dev) ++#define netif_napi_add(_netdev, _napi, _poll, _weight) \ ++ do { \ ++ struct napi_struct *__napi = (_napi); \ ++ _netdev->poll = &(__kc_adapter_clean); \ ++ _netdev->weight = (_weight); \ ++ __napi->poll = &(_poll); \ ++ __napi->weight = (_weight); \ ++ __napi->dev = (_netdev); \ ++ netif_poll_disable(_netdev); \ ++ } while (0) ++#define netif_napi_del(_a) do {} while (0) ++#define napi_schedule_prep(_napi) netif_rx_schedule_prep((_napi)->dev) ++#define napi_schedule(_napi) netif_rx_schedule(napi_to_poll_dev(_napi)) ++#define __napi_schedule(_napi) __netif_rx_schedule(napi_to_poll_dev(_napi)) ++#define napi_complete(_napi) netif_rx_complete(napi_to_poll_dev(_napi)) ++#else /* NAPI */ ++#define netif_napi_add(_netdev, _napi, _poll, _weight) \ ++ do { \ ++ struct napi_struct *__napi = _napi; \ ++ _netdev->poll = &(_poll); \ ++ _netdev->weight = (_weight); \ ++ __napi->poll = &(_poll); \ ++ __napi->weight = (_weight); \ ++ __napi->dev = (_netdev); \ ++ } while (0) ++#define netif_napi_del(_a) do {} while (0) ++#endif /* NAPI */ ++ ++#undef dev_get_by_name ++#define dev_get_by_name(_a, _b) dev_get_by_name(_b) ++#define __netif_subqueue_stopped(_a, _b) netif_subqueue_stopped(_a, _b) ++#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) ++#else /* < 2.6.24 */ ++#define HAVE_NETDEV_NAPI_LIST ++#endif /* < 2.6.24 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,24) ) ++#include ++#endif /* > 2.6.24 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) ) ++#define PM_QOS_CPU_DMA_LATENCY 1 ++ ++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18) ) ++#include ++#define PM_QOS_DEFAULT_VALUE INFINITE_LATENCY ++#define pm_qos_add_requirement(pm_qos_class, name, value) \ ++ set_acceptable_latency(name, value) ++#define pm_qos_remove_requirement(pm_qos_class, name) \ ++ remove_acceptable_latency(name) ++#define pm_qos_update_requirement(pm_qos_class, name, value) \ ++ modify_acceptable_latency(name, value) ++#else ++#define PM_QOS_DEFAULT_VALUE -1 ++#define pm_qos_add_requirement(pm_qos_class, name, value) ++#define pm_qos_remove_requirement(pm_qos_class, name) ++#define pm_qos_update_requirement(pm_qos_class, name, value) { \ ++ if (value != PM_QOS_DEFAULT_VALUE) { \ ++ printk(KERN_WARNING "%s: unable to set PM QoS requirement\n", \ ++ pci_name(adapter->pdev)); \ ++ } \ ++} ++#endif /* > 2.6.18 */ ++ ++#define pci_enable_device_mem(pdev) pci_enable_device(pdev) ++ ++#endif /* < 2.6.25 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) ) ++#else /* < 2.6.26 */ ++#include ++#define HAVE_NETDEV_VLAN_FEATURES ++#endif /* < 2.6.26 */ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) ) ++#if (((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) && defined(CONFIG_PM)) || ((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) && defined(CONFIG_PM_SLEEP))) ++#undef device_set_wakeup_enable ++#define device_set_wakeup_enable(dev, val) \ ++ do { \ ++ u16 pmc = 0; \ ++ int pm = pci_find_capability(adapter->pdev, PCI_CAP_ID_PM); \ ++ if (pm) { \ ++ pci_read_config_word(adapter->pdev, pm + PCI_PM_PMC, \ ++ &pmc); \ ++ } \ ++ (dev)->power.can_wakeup = !!(pmc >> 11); \ ++ (dev)->power.should_wakeup = (val && (pmc >> 11)); \ ++ } while (0) ++#endif /* 2.6.15-2.6.22 and CONFIG_PM or 2.6.23-2.6.25 and CONFIG_PM_SLEEP */ ++#endif /* 2.6.15 through 2.6.27 */ ++#ifndef netif_napi_del ++#define netif_napi_del(_a) do {} while (0) ++#ifdef NAPI ++#ifdef CONFIG_NETPOLL ++#undef netif_napi_del ++#define netif_napi_del(_a) list_del(&(_a)->dev_list); ++#endif ++#endif ++#endif /* netif_napi_del */ ++#ifndef pci_dma_mapping_error ++#define pci_dma_mapping_error(pdev, dma_addr) pci_dma_mapping_error(dma_addr) ++#endif ++ ++ ++#ifdef HAVE_TX_MQ ++extern void _kc_netif_tx_stop_all_queues(struct net_device *); ++extern void _kc_netif_tx_wake_all_queues(struct net_device *); ++extern void _kc_netif_tx_start_all_queues(struct net_device *); ++#define netif_tx_stop_all_queues(a) _kc_netif_tx_stop_all_queues(a) ++#define netif_tx_wake_all_queues(a) _kc_netif_tx_wake_all_queues(a) ++#define netif_tx_start_all_queues(a) _kc_netif_tx_start_all_queues(a) ++#undef netif_stop_subqueue ++#define netif_stop_subqueue(_ndev,_qi) do { \ ++ if (netif_is_multiqueue((_ndev))) \ ++ netif_stop_subqueue((_ndev), (_qi)); \ ++ else \ ++ netif_stop_queue((_ndev)); \ ++ } while (0) ++#undef netif_start_subqueue ++#define netif_start_subqueue(_ndev,_qi) do { \ ++ if (netif_is_multiqueue((_ndev))) \ ++ netif_start_subqueue((_ndev), (_qi)); \ ++ else \ ++ netif_start_queue((_ndev)); \ ++ } while (0) ++#else /* HAVE_TX_MQ */ ++#define netif_tx_stop_all_queues(a) netif_stop_queue(a) ++#define netif_tx_wake_all_queues(a) netif_wake_queue(a) ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12) ) ++#define netif_tx_start_all_queues(a) netif_start_queue(a) ++#else ++#define netif_tx_start_all_queues(a) do {} while (0) ++#endif ++#define netif_stop_subqueue(_ndev,_qi) netif_stop_queue((_ndev)) ++#define netif_start_subqueue(_ndev,_qi) netif_start_queue((_ndev)) ++#endif /* HAVE_TX_MQ */ ++#else /* < 2.6.27 */ ++#define HAVE_TX_MQ ++#define HAVE_NETDEV_SELECT_QUEUE ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) ++#define pci_ioremap_bar(pdev, bar) ioremap(pci_resource_start(pdev, bar), \ ++ pci_resource_len(pdev, bar)) ++#define pci_wake_from_d3 _kc_pci_wake_from_d3 ++#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep ++extern int _kc_pci_wake_from_d3(struct pci_dev *dev, bool enable); ++extern int _kc_pci_prepare_to_sleep(struct pci_dev *dev); ++#endif /* < 2.6.28 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) ) ++#define pci_request_selected_regions_exclusive(pdev, bars, name) \ ++ pci_request_selected_regions(pdev, bars, name) ++#else /* < 2.6.29 */ ++#ifdef CONFIG_DCB ++#define HAVE_PFC_MODE_ENABLE ++#endif /* CONFIG_DCB */ ++#endif /* < 2.6.29 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ) ++#ifdef IXGBE_FCOE ++#undef CONFIG_FCOE ++#undef CONFIG_FCOE_MODULE ++#endif /* IXGBE_FCOE */ ++extern u16 _kc_skb_tx_hash(struct net_device *dev, struct sk_buff *skb); ++#define skb_tx_hash(n, s) _kc_skb_tx_hash(n, s) ++#define skb_record_rx_queue(a, b) do {} while (0) ++#else ++#define HAVE_ASPM_QUIRKS ++#endif /* < 2.6.30 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31) ) ++#define ETH_P_1588 0x88F7 ++#else ++#ifndef HAVE_NETDEV_STORAGE_ADDRESS ++#define HAVE_NETDEV_STORAGE_ADDRESS ++#endif ++#ifndef HAVE_NETDEV_HW_ADDR ++#define HAVE_NETDEV_HW_ADDR ++#endif ++#endif /* < 2.6.31 */ ++#endif /* _KCOMPAT_H_ */ +diff -r b58885ce604a drivers/net/e1000/kcompat_ethtool.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000/kcompat_ethtool.c Wed Aug 05 11:02:21 2009 +0100 +@@ -0,0 +1,1169 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * net/core/ethtool.c - Ethtool ioctl handler ++ * Copyright (c) 2003 Matthew Wilcox ++ * ++ * This file is where we call all the ethtool_ops commands to get ++ * the information ethtool needs. We fall back to calling do_ioctl() ++ * for drivers which haven't been converted to ethtool_ops yet. ++ * ++ * It's GPL, stupid. ++ * ++ * Modification by sfeldma@pobox.com to work as backward compat ++ * solution for pre-ethtool_ops kernels. ++ * - copied struct ethtool_ops from ethtool.h ++ * - defined SET_ETHTOOL_OPS ++ * - put in some #ifndef NETIF_F_xxx wrappers ++ * - changes refs to dev->ethtool_ops to ethtool_ops ++ * - changed dev_ethtool to ethtool_ioctl ++ * - remove EXPORT_SYMBOL()s ++ * - added _kc_ prefix in built-in ethtool_op_xxx ops. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "kcompat.h" ++ ++#undef SUPPORTED_10000baseT_Full ++#define SUPPORTED_10000baseT_Full (1 << 12) ++#undef ADVERTISED_10000baseT_Full ++#define ADVERTISED_10000baseT_Full (1 << 12) ++#undef SPEED_10000 ++#define SPEED_10000 10000 ++ ++#undef ethtool_ops ++#define ethtool_ops _kc_ethtool_ops ++ ++struct _kc_ethtool_ops { ++ int (*get_settings)(struct net_device *, struct ethtool_cmd *); ++ int (*set_settings)(struct net_device *, struct ethtool_cmd *); ++ void (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *); ++ int (*get_regs_len)(struct net_device *); ++ void (*get_regs)(struct net_device *, struct ethtool_regs *, void *); ++ void (*get_wol)(struct net_device *, struct ethtool_wolinfo *); ++ int (*set_wol)(struct net_device *, struct ethtool_wolinfo *); ++ u32 (*get_msglevel)(struct net_device *); ++ void (*set_msglevel)(struct net_device *, u32); ++ int (*nway_reset)(struct net_device *); ++ u32 (*get_link)(struct net_device *); ++ int (*get_eeprom_len)(struct net_device *); ++ int (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); ++ int (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); ++ int (*get_coalesce)(struct net_device *, struct ethtool_coalesce *); ++ int (*set_coalesce)(struct net_device *, struct ethtool_coalesce *); ++ void (*get_ringparam)(struct net_device *, struct ethtool_ringparam *); ++ int (*set_ringparam)(struct net_device *, struct ethtool_ringparam *); ++ void (*get_pauseparam)(struct net_device *, ++ struct ethtool_pauseparam*); ++ int (*set_pauseparam)(struct net_device *, ++ struct ethtool_pauseparam*); ++ u32 (*get_rx_csum)(struct net_device *); ++ int (*set_rx_csum)(struct net_device *, u32); ++ u32 (*get_tx_csum)(struct net_device *); ++ int (*set_tx_csum)(struct net_device *, u32); ++ u32 (*get_sg)(struct net_device *); ++ int (*set_sg)(struct net_device *, u32); ++ u32 (*get_tso)(struct net_device *); ++ int (*set_tso)(struct net_device *, u32); ++ int (*self_test_count)(struct net_device *); ++ void (*self_test)(struct net_device *, struct ethtool_test *, u64 *); ++ void (*get_strings)(struct net_device *, u32 stringset, u8 *); ++ int (*phys_id)(struct net_device *, u32); ++ int (*get_stats_count)(struct net_device *); ++ void (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, ++ u64 *); ++} *ethtool_ops = NULL; ++ ++#undef SET_ETHTOOL_OPS ++#define SET_ETHTOOL_OPS(netdev, ops) (ethtool_ops = (ops)) ++ ++/* ++ * Some useful ethtool_ops methods that are device independent. If we find that ++ * all drivers want to do the same thing here, we can turn these into dev_() ++ * function calls. ++ */ ++ ++#undef ethtool_op_get_link ++#define ethtool_op_get_link _kc_ethtool_op_get_link ++u32 _kc_ethtool_op_get_link(struct net_device *dev) ++{ ++ return netif_carrier_ok(dev) ? 1 : 0; ++} ++ ++#undef ethtool_op_get_tx_csum ++#define ethtool_op_get_tx_csum _kc_ethtool_op_get_tx_csum ++u32 _kc_ethtool_op_get_tx_csum(struct net_device *dev) ++{ ++#ifdef NETIF_F_IP_CSUM ++ return (dev->features & NETIF_F_IP_CSUM) != 0; ++#else ++ return 0; ++#endif ++} ++ ++#undef ethtool_op_set_tx_csum ++#define ethtool_op_set_tx_csum _kc_ethtool_op_set_tx_csum ++int _kc_ethtool_op_set_tx_csum(struct net_device *dev, u32 data) ++{ ++#ifdef NETIF_F_IP_CSUM ++ if (data) ++#ifdef NETIF_F_IPV6_CSUM ++ dev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); ++ else ++ dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); ++#else ++ dev->features |= NETIF_F_IP_CSUM; ++ else ++ dev->features &= ~NETIF_F_IP_CSUM; ++#endif ++#endif ++ ++ return 0; ++} ++ ++#undef ethtool_op_get_sg ++#define ethtool_op_get_sg _kc_ethtool_op_get_sg ++u32 _kc_ethtool_op_get_sg(struct net_device *dev) ++{ ++#ifdef NETIF_F_SG ++ return (dev->features & NETIF_F_SG) != 0; ++#else ++ return 0; ++#endif ++} ++ ++#undef ethtool_op_set_sg ++#define ethtool_op_set_sg _kc_ethtool_op_set_sg ++int _kc_ethtool_op_set_sg(struct net_device *dev, u32 data) ++{ ++#ifdef NETIF_F_SG ++ if (data) ++ dev->features |= NETIF_F_SG; ++ else ++ dev->features &= ~NETIF_F_SG; ++#endif ++ ++ return 0; ++} ++ ++#undef ethtool_op_get_tso ++#define ethtool_op_get_tso _kc_ethtool_op_get_tso ++u32 _kc_ethtool_op_get_tso(struct net_device *dev) ++{ ++#ifdef NETIF_F_TSO ++ return (dev->features & NETIF_F_TSO) != 0; ++#else ++ return 0; ++#endif ++} ++ ++#undef ethtool_op_set_tso ++#define ethtool_op_set_tso _kc_ethtool_op_set_tso ++int _kc_ethtool_op_set_tso(struct net_device *dev, u32 data) ++{ ++#ifdef NETIF_F_TSO ++ if (data) ++ dev->features |= NETIF_F_TSO; ++ else ++ dev->features &= ~NETIF_F_TSO; ++#endif ++ ++ return 0; ++} ++ ++/* Handlers for each ethtool command */ ++ ++static int ethtool_get_settings(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_cmd cmd = { ETHTOOL_GSET }; ++ int err; ++ ++ if (!ethtool_ops->get_settings) ++ return -EOPNOTSUPP; ++ ++ err = ethtool_ops->get_settings(dev, &cmd); ++ if (err < 0) ++ return err; ++ ++ if (copy_to_user(useraddr, &cmd, sizeof(cmd))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_settings(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_cmd cmd; ++ ++ if (!ethtool_ops->set_settings) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&cmd, useraddr, sizeof(cmd))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_settings(dev, &cmd); ++} ++ ++static int ethtool_get_drvinfo(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_drvinfo info; ++ struct ethtool_ops *ops = ethtool_ops; ++ ++ if (!ops->get_drvinfo) ++ return -EOPNOTSUPP; ++ ++ memset(&info, 0, sizeof(info)); ++ info.cmd = ETHTOOL_GDRVINFO; ++ ops->get_drvinfo(dev, &info); ++ ++ if (ops->self_test_count) ++ info.testinfo_len = ops->self_test_count(dev); ++ if (ops->get_stats_count) ++ info.n_stats = ops->get_stats_count(dev); ++ if (ops->get_regs_len) ++ info.regdump_len = ops->get_regs_len(dev); ++ if (ops->get_eeprom_len) ++ info.eedump_len = ops->get_eeprom_len(dev); ++ ++ if (copy_to_user(useraddr, &info, sizeof(info))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_get_regs(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_regs regs; ++ struct ethtool_ops *ops = ethtool_ops; ++ void *regbuf; ++ int reglen, ret; ++ ++ if (!ops->get_regs || !ops->get_regs_len) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(®s, useraddr, sizeof(regs))) ++ return -EFAULT; ++ ++ reglen = ops->get_regs_len(dev); ++ if (regs.len > reglen) ++ regs.len = reglen; ++ ++ regbuf = kmalloc(reglen, GFP_USER); ++ if (!regbuf) ++ return -ENOMEM; ++ ++ ops->get_regs(dev, ®s, regbuf); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, ®s, sizeof(regs))) ++ goto out; ++ useraddr += offsetof(struct ethtool_regs, data); ++ if (copy_to_user(useraddr, regbuf, reglen)) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(regbuf); ++ return ret; ++} ++ ++static int ethtool_get_wol(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_wolinfo wol = { ETHTOOL_GWOL }; ++ ++ if (!ethtool_ops->get_wol) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_wol(dev, &wol); ++ ++ if (copy_to_user(useraddr, &wol, sizeof(wol))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_wol(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_wolinfo wol; ++ ++ if (!ethtool_ops->set_wol) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&wol, useraddr, sizeof(wol))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_wol(dev, &wol); ++} ++ ++static int ethtool_get_msglevel(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GMSGLVL }; ++ ++ if (!ethtool_ops->get_msglevel) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_msglevel(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_msglevel(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_msglevel) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ ethtool_ops->set_msglevel(dev, edata.data); ++ return 0; ++} ++ ++static int ethtool_nway_reset(struct net_device *dev) ++{ ++ if (!ethtool_ops->nway_reset) ++ return -EOPNOTSUPP; ++ ++ return ethtool_ops->nway_reset(dev); ++} ++ ++static int ethtool_get_link(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ ++ if (!ethtool_ops->get_link) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_link(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_get_eeprom(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_eeprom eeprom; ++ struct ethtool_ops *ops = ethtool_ops; ++ u8 *data; ++ int ret; ++ ++ if (!ops->get_eeprom || !ops->get_eeprom_len) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) ++ return -EFAULT; ++ ++ /* Check for wrap and zero */ ++ if (eeprom.offset + eeprom.len <= eeprom.offset) ++ return -EINVAL; ++ ++ /* Check for exceeding total eeprom len */ ++ if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev)) ++ return -EINVAL; ++ ++ data = kmalloc(eeprom.len, GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ret = -EFAULT; ++ if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len)) ++ goto out; ++ ++ ret = ops->get_eeprom(dev, &eeprom, data); ++ if (ret) ++ goto out; ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &eeprom, sizeof(eeprom))) ++ goto out; ++ if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len)) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_set_eeprom(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_eeprom eeprom; ++ struct ethtool_ops *ops = ethtool_ops; ++ u8 *data; ++ int ret; ++ ++ if (!ops->set_eeprom || !ops->get_eeprom_len) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) ++ return -EFAULT; ++ ++ /* Check for wrap and zero */ ++ if (eeprom.offset + eeprom.len <= eeprom.offset) ++ return -EINVAL; ++ ++ /* Check for exceeding total eeprom len */ ++ if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev)) ++ return -EINVAL; ++ ++ data = kmalloc(eeprom.len, GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ret = -EFAULT; ++ if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len)) ++ goto out; ++ ++ ret = ops->set_eeprom(dev, &eeprom, data); ++ if (ret) ++ goto out; ++ ++ if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len)) ++ ret = -EFAULT; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_get_coalesce(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_coalesce coalesce = { ETHTOOL_GCOALESCE }; ++ ++ if (!ethtool_ops->get_coalesce) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_coalesce(dev, &coalesce); ++ ++ if (copy_to_user(useraddr, &coalesce, sizeof(coalesce))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_coalesce(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_coalesce coalesce; ++ ++ if (!ethtool_ops->get_coalesce) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&coalesce, useraddr, sizeof(coalesce))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_coalesce(dev, &coalesce); ++} ++ ++static int ethtool_get_ringparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_ringparam ringparam = { ETHTOOL_GRINGPARAM }; ++ ++ if (!ethtool_ops->get_ringparam) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_ringparam(dev, &ringparam); ++ ++ if (copy_to_user(useraddr, &ringparam, sizeof(ringparam))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_ringparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_ringparam ringparam; ++ ++ if (!ethtool_ops->get_ringparam) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&ringparam, useraddr, sizeof(ringparam))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_ringparam(dev, &ringparam); ++} ++ ++static int ethtool_get_pauseparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_pauseparam pauseparam = { ETHTOOL_GPAUSEPARAM }; ++ ++ if (!ethtool_ops->get_pauseparam) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_pauseparam(dev, &pauseparam); ++ ++ if (copy_to_user(useraddr, &pauseparam, sizeof(pauseparam))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_pauseparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_pauseparam pauseparam; ++ ++ if (!ethtool_ops->get_pauseparam) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&pauseparam, useraddr, sizeof(pauseparam))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_pauseparam(dev, &pauseparam); ++} ++ ++static int ethtool_get_rx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GRXCSUM }; ++ ++ if (!ethtool_ops->get_rx_csum) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_rx_csum(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_rx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_rx_csum) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ ethtool_ops->set_rx_csum(dev, edata.data); ++ return 0; ++} ++ ++static int ethtool_get_tx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GTXCSUM }; ++ ++ if (!ethtool_ops->get_tx_csum) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_tx_csum(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_tx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_tx_csum) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_tx_csum(dev, edata.data); ++} ++ ++static int ethtool_get_sg(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GSG }; ++ ++ if (!ethtool_ops->get_sg) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_sg(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_sg(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_sg) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_sg(dev, edata.data); ++} ++ ++static int ethtool_get_tso(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GTSO }; ++ ++ if (!ethtool_ops->get_tso) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_tso(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_tso(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_tso) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_tso(dev, edata.data); ++} ++ ++static int ethtool_self_test(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_test test; ++ struct ethtool_ops *ops = ethtool_ops; ++ u64 *data; ++ int ret; ++ ++ if (!ops->self_test || !ops->self_test_count) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&test, useraddr, sizeof(test))) ++ return -EFAULT; ++ ++ test.len = ops->self_test_count(dev); ++ data = kmalloc(test.len * sizeof(u64), GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ops->self_test(dev, &test, data); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &test, sizeof(test))) ++ goto out; ++ useraddr += sizeof(test); ++ if (copy_to_user(useraddr, data, test.len * sizeof(u64))) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_get_strings(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_gstrings gstrings; ++ struct ethtool_ops *ops = ethtool_ops; ++ u8 *data; ++ int ret; ++ ++ if (!ops->get_strings) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&gstrings, useraddr, sizeof(gstrings))) ++ return -EFAULT; ++ ++ switch (gstrings.string_set) { ++ case ETH_SS_TEST: ++ if (!ops->self_test_count) ++ return -EOPNOTSUPP; ++ gstrings.len = ops->self_test_count(dev); ++ break; ++ case ETH_SS_STATS: ++ if (!ops->get_stats_count) ++ return -EOPNOTSUPP; ++ gstrings.len = ops->get_stats_count(dev); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ data = kmalloc(gstrings.len * ETH_GSTRING_LEN, GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ops->get_strings(dev, gstrings.string_set, data); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &gstrings, sizeof(gstrings))) ++ goto out; ++ useraddr += sizeof(gstrings); ++ if (copy_to_user(useraddr, data, gstrings.len * ETH_GSTRING_LEN)) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_phys_id(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_value id; ++ ++ if (!ethtool_ops->phys_id) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&id, useraddr, sizeof(id))) ++ return -EFAULT; ++ ++ return ethtool_ops->phys_id(dev, id.data); ++} ++ ++static int ethtool_get_stats(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_stats stats; ++ struct ethtool_ops *ops = ethtool_ops; ++ u64 *data; ++ int ret; ++ ++ if (!ops->get_ethtool_stats || !ops->get_stats_count) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&stats, useraddr, sizeof(stats))) ++ return -EFAULT; ++ ++ stats.n_stats = ops->get_stats_count(dev); ++ data = kmalloc(stats.n_stats * sizeof(u64), GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ops->get_ethtool_stats(dev, &stats, data); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &stats, sizeof(stats))) ++ goto out; ++ useraddr += sizeof(stats); ++ if (copy_to_user(useraddr, data, stats.n_stats * sizeof(u64))) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++/* The main entry point in this file. Called from net/core/dev.c */ ++ ++#define ETHTOOL_OPS_COMPAT ++int ethtool_ioctl(struct ifreq *ifr) ++{ ++ struct net_device *dev = __dev_get_by_name(ifr->ifr_name); ++ void *useraddr = (void *) ifr->ifr_data; ++ u32 ethcmd; ++ ++ /* ++ * XXX: This can be pushed down into the ethtool_* handlers that ++ * need it. Keep existing behavior for the moment. ++ */ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++ if (!dev || !netif_device_present(dev)) ++ return -ENODEV; ++ ++ if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd))) ++ return -EFAULT; ++ ++ switch (ethcmd) { ++ case ETHTOOL_GSET: ++ return ethtool_get_settings(dev, useraddr); ++ case ETHTOOL_SSET: ++ return ethtool_set_settings(dev, useraddr); ++ case ETHTOOL_GDRVINFO: ++ return ethtool_get_drvinfo(dev, useraddr); ++ case ETHTOOL_GREGS: ++ return ethtool_get_regs(dev, useraddr); ++ case ETHTOOL_GWOL: ++ return ethtool_get_wol(dev, useraddr); ++ case ETHTOOL_SWOL: ++ return ethtool_set_wol(dev, useraddr); ++ case ETHTOOL_GMSGLVL: ++ return ethtool_get_msglevel(dev, useraddr); ++ case ETHTOOL_SMSGLVL: ++ return ethtool_set_msglevel(dev, useraddr); ++ case ETHTOOL_NWAY_RST: ++ return ethtool_nway_reset(dev); ++ case ETHTOOL_GLINK: ++ return ethtool_get_link(dev, useraddr); ++ case ETHTOOL_GEEPROM: ++ return ethtool_get_eeprom(dev, useraddr); ++ case ETHTOOL_SEEPROM: ++ return ethtool_set_eeprom(dev, useraddr); ++ case ETHTOOL_GCOALESCE: ++ return ethtool_get_coalesce(dev, useraddr); ++ case ETHTOOL_SCOALESCE: ++ return ethtool_set_coalesce(dev, useraddr); ++ case ETHTOOL_GRINGPARAM: ++ return ethtool_get_ringparam(dev, useraddr); ++ case ETHTOOL_SRINGPARAM: ++ return ethtool_set_ringparam(dev, useraddr); ++ case ETHTOOL_GPAUSEPARAM: ++ return ethtool_get_pauseparam(dev, useraddr); ++ case ETHTOOL_SPAUSEPARAM: ++ return ethtool_set_pauseparam(dev, useraddr); ++ case ETHTOOL_GRXCSUM: ++ return ethtool_get_rx_csum(dev, useraddr); ++ case ETHTOOL_SRXCSUM: ++ return ethtool_set_rx_csum(dev, useraddr); ++ case ETHTOOL_GTXCSUM: ++ return ethtool_get_tx_csum(dev, useraddr); ++ case ETHTOOL_STXCSUM: ++ return ethtool_set_tx_csum(dev, useraddr); ++ case ETHTOOL_GSG: ++ return ethtool_get_sg(dev, useraddr); ++ case ETHTOOL_SSG: ++ return ethtool_set_sg(dev, useraddr); ++ case ETHTOOL_GTSO: ++ return ethtool_get_tso(dev, useraddr); ++ case ETHTOOL_STSO: ++ return ethtool_set_tso(dev, useraddr); ++ case ETHTOOL_TEST: ++ return ethtool_self_test(dev, useraddr); ++ case ETHTOOL_GSTRINGS: ++ return ethtool_get_strings(dev, useraddr); ++ case ETHTOOL_PHYS_ID: ++ return ethtool_phys_id(dev, useraddr); ++ case ETHTOOL_GSTATS: ++ return ethtool_get_stats(dev, useraddr); ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return -EOPNOTSUPP; ++} ++ ++#define mii_if_info _kc_mii_if_info ++struct _kc_mii_if_info { ++ int phy_id; ++ int advertising; ++ int phy_id_mask; ++ int reg_num_mask; ++ ++ unsigned int full_duplex : 1; /* is full duplex? */ ++ unsigned int force_media : 1; /* is autoneg. disabled? */ ++ ++ struct net_device *dev; ++ int (*mdio_read) (struct net_device *dev, int phy_id, int location); ++ void (*mdio_write) (struct net_device *dev, int phy_id, int location, int val); ++}; ++ ++struct ethtool_cmd; ++struct mii_ioctl_data; ++ ++#undef mii_link_ok ++#define mii_link_ok _kc_mii_link_ok ++#undef mii_nway_restart ++#define mii_nway_restart _kc_mii_nway_restart ++#undef mii_ethtool_gset ++#define mii_ethtool_gset _kc_mii_ethtool_gset ++#undef mii_ethtool_sset ++#define mii_ethtool_sset _kc_mii_ethtool_sset ++#undef mii_check_link ++#define mii_check_link _kc_mii_check_link ++#undef generic_mii_ioctl ++#define generic_mii_ioctl _kc_generic_mii_ioctl ++extern int _kc_mii_link_ok (struct mii_if_info *mii); ++extern int _kc_mii_nway_restart (struct mii_if_info *mii); ++extern int _kc_mii_ethtool_gset(struct mii_if_info *mii, ++ struct ethtool_cmd *ecmd); ++extern int _kc_mii_ethtool_sset(struct mii_if_info *mii, ++ struct ethtool_cmd *ecmd); ++extern void _kc_mii_check_link (struct mii_if_info *mii); ++extern int _kc_generic_mii_ioctl(struct mii_if_info *mii_if, ++ struct mii_ioctl_data *mii_data, int cmd, ++ unsigned int *duplex_changed); ++ ++ ++struct _kc_pci_dev_ext { ++ struct pci_dev *dev; ++ void *pci_drvdata; ++ struct pci_driver *driver; ++}; ++ ++struct _kc_net_dev_ext { ++ struct net_device *dev; ++ unsigned int carrier; ++}; ++ ++ ++/**************************************/ ++/* mii support */ ++ ++int _kc_mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) ++{ ++ struct net_device *dev = mii->dev; ++ u32 advert, bmcr, lpa, nego; ++ ++ ecmd->supported = ++ (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | ++ SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | ++ SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII); ++ ++ /* only supports twisted-pair */ ++ ecmd->port = PORT_MII; ++ ++ /* only supports internal transceiver */ ++ ecmd->transceiver = XCVR_INTERNAL; ++ ++ /* this isn't fully supported at higher layers */ ++ ecmd->phy_address = mii->phy_id; ++ ++ ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII; ++ advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE); ++ if (advert & ADVERTISE_10HALF) ++ ecmd->advertising |= ADVERTISED_10baseT_Half; ++ if (advert & ADVERTISE_10FULL) ++ ecmd->advertising |= ADVERTISED_10baseT_Full; ++ if (advert & ADVERTISE_100HALF) ++ ecmd->advertising |= ADVERTISED_100baseT_Half; ++ if (advert & ADVERTISE_100FULL) ++ ecmd->advertising |= ADVERTISED_100baseT_Full; ++ ++ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); ++ lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA); ++ if (bmcr & BMCR_ANENABLE) { ++ ecmd->advertising |= ADVERTISED_Autoneg; ++ ecmd->autoneg = AUTONEG_ENABLE; ++ ++ nego = mii_nway_result(advert & lpa); ++ if (nego == LPA_100FULL || nego == LPA_100HALF) ++ ecmd->speed = SPEED_100; ++ else ++ ecmd->speed = SPEED_10; ++ if (nego == LPA_100FULL || nego == LPA_10FULL) { ++ ecmd->duplex = DUPLEX_FULL; ++ mii->full_duplex = 1; ++ } else { ++ ecmd->duplex = DUPLEX_HALF; ++ mii->full_duplex = 0; ++ } ++ } else { ++ ecmd->autoneg = AUTONEG_DISABLE; ++ ++ ecmd->speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; ++ ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; ++ } ++ ++ /* ignore maxtxpkt, maxrxpkt for now */ ++ ++ return 0; ++} ++ ++int _kc_mii_ethtool_sset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) ++{ ++ struct net_device *dev = mii->dev; ++ ++ if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) ++ return -EINVAL; ++ if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) ++ return -EINVAL; ++ if (ecmd->port != PORT_MII) ++ return -EINVAL; ++ if (ecmd->transceiver != XCVR_INTERNAL) ++ return -EINVAL; ++ if (ecmd->phy_address != mii->phy_id) ++ return -EINVAL; ++ if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE) ++ return -EINVAL; ++ ++ /* ignore supported, maxtxpkt, maxrxpkt */ ++ ++ if (ecmd->autoneg == AUTONEG_ENABLE) { ++ u32 bmcr, advert, tmp; ++ ++ if ((ecmd->advertising & (ADVERTISED_10baseT_Half | ++ ADVERTISED_10baseT_Full | ++ ADVERTISED_100baseT_Half | ++ ADVERTISED_100baseT_Full)) == 0) ++ return -EINVAL; ++ ++ /* advertise only what has been requested */ ++ advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE); ++ tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4); ++ if (ADVERTISED_10baseT_Half) ++ tmp |= ADVERTISE_10HALF; ++ if (ADVERTISED_10baseT_Full) ++ tmp |= ADVERTISE_10FULL; ++ if (ADVERTISED_100baseT_Half) ++ tmp |= ADVERTISE_100HALF; ++ if (ADVERTISED_100baseT_Full) ++ tmp |= ADVERTISE_100FULL; ++ if (advert != tmp) { ++ mii->mdio_write(dev, mii->phy_id, MII_ADVERTISE, tmp); ++ mii->advertising = tmp; ++ } ++ ++ /* turn on autonegotiation, and force a renegotiate */ ++ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); ++ bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); ++ mii->mdio_write(dev, mii->phy_id, MII_BMCR, bmcr); ++ ++ mii->force_media = 0; ++ } else { ++ u32 bmcr, tmp; ++ ++ /* turn off auto negotiation, set speed and duplexity */ ++ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); ++ tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX); ++ if (ecmd->speed == SPEED_100) ++ tmp |= BMCR_SPEED100; ++ if (ecmd->duplex == DUPLEX_FULL) { ++ tmp |= BMCR_FULLDPLX; ++ mii->full_duplex = 1; ++ } else ++ mii->full_duplex = 0; ++ if (bmcr != tmp) ++ mii->mdio_write(dev, mii->phy_id, MII_BMCR, tmp); ++ ++ mii->force_media = 1; ++ } ++ return 0; ++} ++ ++int _kc_mii_link_ok (struct mii_if_info *mii) ++{ ++ /* first, a dummy read, needed to latch some MII phys */ ++ mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); ++ if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS) ++ return 1; ++ return 0; ++} ++ ++int _kc_mii_nway_restart (struct mii_if_info *mii) ++{ ++ int bmcr; ++ int r = -EINVAL; ++ ++ /* if autoneg is off, it's an error */ ++ bmcr = mii->mdio_read(mii->dev, mii->phy_id, MII_BMCR); ++ ++ if (bmcr & BMCR_ANENABLE) { ++ bmcr |= BMCR_ANRESTART; ++ mii->mdio_write(mii->dev, mii->phy_id, MII_BMCR, bmcr); ++ r = 0; ++ } ++ ++ return r; ++} ++ ++void _kc_mii_check_link (struct mii_if_info *mii) ++{ ++ int cur_link = mii_link_ok(mii); ++ int prev_link = netif_carrier_ok(mii->dev); ++ ++ if (cur_link && !prev_link) ++ netif_carrier_on(mii->dev); ++ else if (prev_link && !cur_link) ++ netif_carrier_off(mii->dev); ++} ++ ++int _kc_generic_mii_ioctl(struct mii_if_info *mii_if, ++ struct mii_ioctl_data *mii_data, int cmd, ++ unsigned int *duplex_chg_out) ++{ ++ int rc = 0; ++ unsigned int duplex_changed = 0; ++ ++ if (duplex_chg_out) ++ *duplex_chg_out = 0; ++ ++ mii_data->phy_id &= mii_if->phy_id_mask; ++ mii_data->reg_num &= mii_if->reg_num_mask; ++ ++ switch(cmd) { ++ case SIOCDEVPRIVATE: /* binary compat, remove in 2.5 */ ++ case SIOCGMIIPHY: ++ mii_data->phy_id = mii_if->phy_id; ++ /* fall through */ ++ ++ case SIOCDEVPRIVATE + 1:/* binary compat, remove in 2.5 */ ++ case SIOCGMIIREG: ++ mii_data->val_out = ++ mii_if->mdio_read(mii_if->dev, mii_data->phy_id, ++ mii_data->reg_num); ++ break; ++ ++ case SIOCDEVPRIVATE + 2:/* binary compat, remove in 2.5 */ ++ case SIOCSMIIREG: { ++ u16 val = mii_data->val_in; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++ if (mii_data->phy_id == mii_if->phy_id) { ++ switch(mii_data->reg_num) { ++ case MII_BMCR: { ++ unsigned int new_duplex = 0; ++ if (val & (BMCR_RESET|BMCR_ANENABLE)) ++ mii_if->force_media = 0; ++ else ++ mii_if->force_media = 1; ++ if (mii_if->force_media && ++ (val & BMCR_FULLDPLX)) ++ new_duplex = 1; ++ if (mii_if->full_duplex != new_duplex) { ++ duplex_changed = 1; ++ mii_if->full_duplex = new_duplex; ++ } ++ break; ++ } ++ case MII_ADVERTISE: ++ mii_if->advertising = val; ++ break; ++ default: ++ /* do nothing */ ++ break; ++ } ++ } ++ ++ mii_if->mdio_write(mii_if->dev, mii_data->phy_id, ++ mii_data->reg_num, val); ++ break; ++ } ++ ++ default: ++ rc = -EOPNOTSUPP; ++ break; ++ } ++ ++ if ((rc == 0) && (duplex_chg_out) && (duplex_changed)) ++ *duplex_chg_out = 1; ++ ++ return rc; ++} ++ diff --git a/master/e1000e-1.0.2.5.patch b/master/e1000e-1.0.2.5.patch new file mode 100644 index 0000000..543b0ce --- /dev/null +++ b/master/e1000e-1.0.2.5.patch @@ -0,0 +1,24819 @@ +diff -r 5638ec0574f5 drivers/net/e1000e/82571.c +--- a/drivers/net/e1000e/82571.c Tue Sep 01 13:47:57 2009 +0100 ++++ b/drivers/net/e1000e/82571.c Tue Sep 01 13:48:50 2009 +0100 +@@ -93,10 +93,22 @@ + switch (hw->mac.type) { + case e1000_82571: + case e1000_82572: +- phy->type = e1000_phy_igp_2; ++ phy->type = e1000_phy_igp_2; ++ ret_val = e1000_get_phy_id_82571(hw); ++ ++ /* Verify PHY ID */ ++ if (phy->id != IGP01E1000_I_PHY_ID) ++ return -E1000_ERR_PHY; + break; + case e1000_82573: +- phy->type = e1000_phy_m88; ++ phy->type = e1000_phy_m88; ++ ret_val = e1000_get_phy_id_82571(hw); ++ ++ /* Verify PHY ID */ ++ if (phy->id != M88E1111_I_PHY_ID) { ++ hw_dbg(hw, "PHY ID unknown: type = 0x%08x\n", phy->id); ++ return -E1000_ERR_PHY; ++ } + break; + case e1000_82574: + phy->type = e1000_phy_bm; +@@ -381,10 +393,11 @@ + if (pdev->device == E1000_DEV_ID_82573L) { + e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1, + &eeprom_data); +- if (eeprom_data & NVM_WORD1A_ASPM_MASK) +- adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; ++ if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) ++ adapter->flags |= FLAG_HAS_JUMBO_FRAMES; + } + break; ++ + default: + break; + } +diff -r 5638ec0574f5 drivers/net/e1000e/Makefile +--- a/drivers/net/e1000e/Makefile Tue Sep 01 13:47:57 2009 +0100 ++++ b/drivers/net/e1000e/Makefile Tue Sep 01 13:48:50 2009 +0100 +@@ -32,6 +32,13 @@ + + obj-$(CONFIG_E1000E) += e1000e.o + +-e1000e-objs := 82571.o ich8lan.o es2lan.o \ +- lib.o phy.o param.o ethtool.o netdev.o ++FAMILYC = e1000_82571.c e1000_ich8lan.c e1000_80003es2lan.c + ++# core driver files ++CFILES = netdev.c ethtool.c param.c $(FAMILYC) \ ++ e1000_mac.c e1000_nvm.c e1000_phy.c e1000_manage.c kcompat.c ++ ++e1000e-objs := $(CFILES:.c=.o) ++ ++EXTRA_CFLAGS += -DDRIVER_E1000E ++ +diff -r 5638ec0574f5 drivers/net/e1000e/e1000.h +--- a/drivers/net/e1000e/e1000.h Tue Sep 01 13:47:57 2009 +0100 ++++ b/drivers/net/e1000e/e1000.h Tue Sep 01 13:48:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel PRO/1000 Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -32,24 +32,25 @@ + #define _E1000_H_ + + #include +-#include +-#include +-#include ++#include + #include ++#include + ++#include "kcompat.h" + #include "hw.h" + + struct e1000_info; + + #define e_printk(level, adapter, format, arg...) \ + printk(level "%s: %s: " format, pci_name(adapter->pdev), \ +- adapter->netdev->name, ## arg) ++ (strchr(adapter->netdev->name, '%') ? "" : \ ++ adapter->netdev->name), ## arg) + + #ifdef DEBUG + #define e_dbg(format, arg...) \ +- e_printk(KERN_DEBUG , adapter, format, ## arg) ++ e_printk(KERN_DEBUG, hw->adapter, format, ## arg) + #else +-#define e_dbg(format, arg...) do { (void)(adapter); } while (0) ++#define e_dbg(format, arg...) do { (void)(hw); } while (0) + #endif + + #define e_err(format, arg...) \ +@@ -62,11 +63,17 @@ + e_printk(KERN_NOTICE, adapter, format, ## arg) + + ++#ifdef CONFIG_E1000E_MSIX + /* Interrupt modes, as used by the IntMode paramter */ + #define E1000E_INT_MODE_LEGACY 0 + #define E1000E_INT_MODE_MSI 1 + #define E1000E_INT_MODE_MSIX 2 + ++#endif /* CONFIG_E1000E_MSIX */ ++#ifndef CONFIG_E1000E_NAPI ++#define E1000_MAX_INTR 10 ++ ++#endif /* CONFIG_E1000E_NAPI */ + /* Tx/Rx descriptor defines */ + #define E1000_DEFAULT_TXD 256 + #define E1000_MAX_TXD 4096 +@@ -96,6 +103,8 @@ + /* Number of packet split data buffers (not including the header buffer) */ + #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) + ++#define DEFAULT_JUMBO 9234 ++ + enum e1000_boards { + board_82571, + board_82572, +@@ -105,6 +114,8 @@ + board_ich8lan, + board_ich9lan, + board_ich10lan, ++ board_pchlan, ++ board_82583, + }; + + struct e1000_queue_stats { +@@ -153,17 +164,20 @@ + /* array of buffer information structs */ + struct e1000_buffer *buffer_info; + ++#ifdef CONFIG_E1000E_MSIX + char name[IFNAMSIZ + 5]; + u32 ims_val; + u32 itr_val; + u16 itr_register; + int set_itr; + ++#endif /* CONFIG_E1000E_MSIX */ + struct sk_buff *rx_skb_top; + + struct e1000_queue_stats stats; + }; + ++#ifdef SIOCGMIIPHY + /* PHY register snapshot values */ + struct e1000_phy_regs { + u16 bmcr; /* basic mode control register */ +@@ -175,6 +189,7 @@ + u16 stat1000; /* 1000BASE-T status register */ + u16 estatus; /* extended status register */ + }; ++#endif + + /* board specific private data structure */ + struct e1000_adapter { +@@ -193,8 +208,7 @@ + u16 mng_vlan_id; + u16 link_speed; + u16 link_duplex; +- +- spinlock_t tx_queue_lock; /* prevent concurrent tail updates */ ++ u16 eeprom_vers; + + /* track device up/down/testing state */ + unsigned long state; +@@ -211,7 +225,9 @@ + struct e1000_ring *tx_ring /* One per active queue */ + ____cacheline_aligned_in_smp; + ++#ifdef CONFIG_E1000E_NAPI + struct napi_struct napi; ++#endif + + unsigned long tx_queue_len; + unsigned int restart_queue; +@@ -242,9 +258,14 @@ + /* + * Rx + */ ++#ifdef CONFIG_E1000E_NAPI + bool (*clean_rx) (struct e1000_adapter *adapter, + int *work_done, int work_to_do) + ____cacheline_aligned_in_smp; ++#else ++ bool (*clean_rx) (struct e1000_adapter *adapter) ++ ____cacheline_aligned_in_smp; ++#endif + void (*alloc_rx_buf) (struct e1000_adapter *adapter, + int cleaned_count); + struct e1000_ring *rx_ring; +@@ -263,6 +284,9 @@ + + unsigned int rx_ps_pages; + u16 rx_ps_bsize0; ++#ifndef CONFIG_E1000E_NAPI ++ u64 rx_dropped_backlog; /* count drops from rx int handler */ ++#endif + u32 max_frame_size; + u32 min_frame_size; + +@@ -278,21 +302,26 @@ + struct e1000_phy_info phy_info; + struct e1000_phy_stats phy_stats; + ++#ifdef SIOCGMIIPHY + /* Snapshot of PHY registers */ + struct e1000_phy_regs phy_regs; ++#endif + + struct e1000_ring test_tx_ring; + struct e1000_ring test_rx_ring; + u32 test_icr; + + u32 msg_enable; ++#ifdef CONFIG_E1000E_MSIX + struct msix_entry *msix_entries; + int int_mode; + u32 eiac_mask; ++#endif /* CONFIG_E1000E_MSIX */ + + u32 eeprom_wol; + u32 wol; + u32 pba; ++ u32 max_hw_frame_size; + + bool fc_autoneg; + +@@ -302,17 +331,18 @@ + unsigned int flags2; + struct work_struct downshift_task; + struct work_struct update_phy_task; ++ struct work_struct led_blink_task; ++ u32 *config_space; + }; + + struct e1000_info { + enum e1000_mac_type mac; + unsigned int flags; +- unsigned int flags2; ++ unsigned int flags2; + u32 pba; ++ u32 max_hw_frame_size; + s32 (*get_variants)(struct e1000_adapter *); +- struct e1000_mac_operations *mac_ops; +- struct e1000_phy_operations *phy_ops; +- struct e1000_nvm_operations *nvm_ops; ++ void (*init_ops)(struct e1000_hw *); + }; + + /* hardware capability, feature, and workaround flags */ +@@ -324,9 +354,10 @@ + #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) + #define FLAG_HAS_SWSM_ON_LOAD (1 << 6) + #define FLAG_HAS_JUMBO_FRAMES (1 << 7) +-#define FLAG_READ_ONLY_NVM (1 << 8) + #define FLAG_IS_ICH (1 << 9) ++#ifdef CONFIG_E1000E_MSIX + #define FLAG_HAS_MSIX (1 << 10) ++#endif + #define FLAG_HAS_SMART_POWER_DOWN (1 << 11) + #define FLAG_IS_QUAD_PORT_A (1 << 12) + #define FLAG_IS_QUAD_PORT (1 << 13) +@@ -351,6 +382,7 @@ + + /* CRC Stripping defines */ + #define FLAG2_CRC_STRIPPING (1 << 0) ++#define FLAG2_HAS_PHY_WAKEUP (1 << 1) + + #define E1000_RX_DESC_PS(R, i) \ + (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) +@@ -377,6 +409,9 @@ + + extern void e1000e_check_options(struct e1000_adapter *adapter); + extern void e1000e_set_ethtool_ops(struct net_device *netdev); ++#ifdef ETHTOOL_OPS_COMPAT ++extern int ethtool_ioctl(struct ifreq *ifr); ++#endif + + extern int e1000e_up(struct e1000_adapter *adapter); + extern void e1000e_down(struct e1000_adapter *adapter); +@@ -388,32 +423,33 @@ + extern void e1000e_free_rx_resources(struct e1000_adapter *adapter); + extern void e1000e_free_tx_resources(struct e1000_adapter *adapter); + extern void e1000e_update_stats(struct e1000_adapter *adapter); ++extern bool e1000_has_link(struct e1000_adapter *adapter); ++#ifdef CONFIG_E1000E_MSIX + extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); + extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); ++#endif + + extern unsigned int copybreak; + +-extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw); +- +-extern struct e1000_info e1000_82571_info; +-extern struct e1000_info e1000_82572_info; +-extern struct e1000_info e1000_82573_info; +-extern struct e1000_info e1000_82574_info; +-extern struct e1000_info e1000_ich8_info; +-extern struct e1000_info e1000_ich9_info; +-extern struct e1000_info e1000_ich10_info; +-extern struct e1000_info e1000_es2_info; ++extern void e1000_init_function_pointers_82571(struct e1000_hw *hw); ++extern void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw); ++extern void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw); + + extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num); + +-extern s32 e1000e_commit_phy(struct e1000_hw *hw); ++static inline s32 e1000e_commit_phy(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.commit) ++ return hw->phy.ops.commit(hw); ++ ++ return 0; ++} + + extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); + + extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw); + extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state); + +-extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw); + extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, + bool state); + extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); +@@ -437,13 +473,14 @@ + extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); + extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); + extern s32 e1000e_setup_link(struct e1000_hw *hw); +-extern void e1000e_clear_vfta(struct e1000_hw *hw); ++static inline void e1000e_clear_vfta(struct e1000_hw *hw) ++{ ++ hw->mac.ops.clear_vfta(hw); ++} + extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); + extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, + u8 *mc_addr_list, +- u32 mc_addr_count, +- u32 rar_used_count, +- u32 rar_count); ++ u32 mc_addr_count); + extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); + extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw); + extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop); +@@ -453,12 +490,16 @@ + extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw); + extern s32 e1000e_force_mac_fc(struct e1000_hw *hw); + extern s32 e1000e_blink_led(struct e1000_hw *hw); +-extern void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value); ++extern void e1000e_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value); ++static inline void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) ++{ ++ if (hw->mac.ops.write_vfta) ++ hw->mac.ops.write_vfta(hw, offset, value); ++} + extern void e1000e_reset_adaptive(struct e1000_hw *hw); + extern void e1000e_update_adaptive(struct e1000_hw *hw); + + extern s32 e1000e_setup_copper_link(struct e1000_hw *hw); +-extern s32 e1000e_get_phy_id(struct e1000_hw *hw); + extern void e1000e_put_hw_semaphore(struct e1000_hw *hw); + extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); + extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); +@@ -475,13 +516,10 @@ + extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); + extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); + extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); +-extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); + extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); + extern s32 e1000e_determine_phy_address(struct e1000_hw *hw); + extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); + extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); +-extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); +-extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); + extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); + extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); + extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); +@@ -494,27 +532,42 @@ + + static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) + { +- return hw->phy.ops.reset_phy(hw); ++ if (hw->phy.ops.reset) ++ return hw->phy.ops.reset(hw); ++ ++ return 0; + } + + static inline s32 e1000_check_reset_block(struct e1000_hw *hw) + { +- return hw->phy.ops.check_reset_block(hw); ++ if (hw->phy.ops.check_reset_block) ++ return hw->phy.ops.check_reset_block(hw); ++ ++ return 0; + } + + static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) + { +- return hw->phy.ops.read_phy_reg(hw, offset, data); ++ if (hw->phy.ops.read_reg) ++ return hw->phy.ops.read_reg(hw, offset, data); ++ ++ return 0; + } + + static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) + { +- return hw->phy.ops.write_phy_reg(hw, offset, data); ++ if (hw->phy.ops.write_reg) ++ return hw->phy.ops.write_reg(hw, offset, data); ++ ++ return 0; + } + + static inline s32 e1000_get_cable_length(struct e1000_hw *hw) + { +- return hw->phy.ops.get_cable_length(hw); ++ if (hw->phy.ops.get_cable_length) ++ return hw->phy.ops.get_cable_length(hw); ++ ++ return 0; + } + + extern s32 e1000e_acquire_nvm(struct e1000_hw *hw); +@@ -524,40 +577,43 @@ + extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); + extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw); + extern void e1000e_release_nvm(struct e1000_hw *hw); +-extern void e1000e_reload_nvm(struct e1000_hw *hw); +-extern s32 e1000e_read_mac_addr(struct e1000_hw *hw); ++ ++static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.read_mac_addr) ++ return hw->mac.ops.read_mac_addr(hw); ++ ++ return e1000e_read_mac_addr_generic(hw); ++} + + static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) + { +- return hw->nvm.ops.validate_nvm(hw); ++ return hw->nvm.ops.validate(hw); + } + + static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) + { +- return hw->nvm.ops.update_nvm(hw); ++ return hw->nvm.ops.update(hw); + } + + static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + { +- return hw->nvm.ops.read_nvm(hw, offset, words, data); ++ return hw->nvm.ops.read(hw, offset, words, data); + } + + static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + { +- return hw->nvm.ops.write_nvm(hw, offset, words, data); ++ return hw->nvm.ops.write(hw, offset, words, data); + } + + static inline s32 e1000_get_phy_info(struct e1000_hw *hw) + { +- return hw->phy.ops.get_phy_info(hw); ++ if (hw->phy.ops.get_info) ++ return hw->phy.ops.get_info(hw); ++ ++ return 0; + } + +-static inline s32 e1000e_check_mng_mode(struct e1000_hw *hw) +-{ +- return hw->mac.ops.check_mng_mode(hw); +-} +- +-extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw); + extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw); + extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); + +@@ -571,4 +627,47 @@ + writel(val, hw->hw_addr + reg); + } + ++#define er32(reg) __er32(hw, E1000_##reg) ++#define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) ++#define e1e_flush() er32(STATUS) ++ ++#define E1000_WRITE_REG(a, reg, value) ( \ ++ writel((value), ((a)->hw_addr + reg))) ++ ++#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + reg)) ++ ++#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \ ++ writel((value), ((a)->hw_addr + reg + ((offset) << 2)))) ++ ++#define E1000_READ_REG_ARRAY(a, reg, offset) ( \ ++ readl((a)->hw_addr + reg + ((offset) << 2))) ++ ++#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY ++#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY ++ ++static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) ++{ ++ return readw(hw->flash_address + reg); ++} ++ ++static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) ++{ ++ return readl(hw->flash_address + reg); ++} ++ ++static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) ++{ ++ writew(val, hw->flash_address + reg); ++} ++ ++static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) ++{ ++ writel(val, hw->flash_address + reg); ++} ++ ++#define er16flash(reg) __er16flash(hw, (reg)) ++#define er32flash(reg) __er32flash(hw, (reg)) ++#define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) ++#define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) ++ + #endif /* _E1000_H_ */ +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_80003es2lan.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_80003es2lan.c Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,1474 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * 80003ES2LAN Gigabit Ethernet Controller (Copper) ++ * 80003ES2LAN Gigabit Ethernet Controller (Serdes) ++ */ ++ ++#include "e1000.h" ++ ++static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); ++static void e1000_release_phy_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); ++static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, ++ u32 offset, ++ u16 *data); ++static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, ++ u32 offset, ++ u16 data); ++static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data); ++static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex); ++static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); ++static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); ++static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); ++static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, ++ u16 *data); ++static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, ++ u16 data); ++static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw); ++static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); ++static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); ++static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw); ++static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); ++ ++/* ++ * A table for the GG82563 cable length where the range is defined ++ * with a lower bound at "index" and the upper bound at ++ * "index + 5". ++ */ ++static const u16 e1000_gg82563_cable_length_table[] = ++ { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; ++#define GG82563_CABLE_LENGTH_TABLE_SIZE \ ++ (sizeof(e1000_gg82563_cable_length_table) / \ ++ sizeof(e1000_gg82563_cable_length_table[0])) ++ ++/** ++ * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->phy.media_type != e1000_media_type_copper) { ++ phy->type = e1000_phy_none; ++ goto out; ++ } else { ++ phy->ops.power_up = e1000_power_up_phy_copper; ++ phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; ++ } ++ ++ phy->addr = 1; ++ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; ++ phy->reset_delay_us = 100; ++ phy->type = e1000_phy_gg82563; ++ ++ phy->ops.acquire = e1000_acquire_phy_80003es2lan; ++ phy->ops.check_polarity = e1000_check_polarity_m88; ++ phy->ops.check_reset_block = e1000e_check_reset_block_generic; ++ phy->ops.commit = e1000e_phy_sw_reset; ++ phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan; ++ phy->ops.get_info = e1000e_get_phy_info_m88; ++ phy->ops.release = e1000_release_phy_80003es2lan; ++ phy->ops.reset = e1000e_phy_hw_reset_generic; ++ phy->ops.set_d3_lplu_state = e1000e_set_d3_lplu_state; ++ ++ phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; ++ phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan; ++ phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan; ++ phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; ++ ++ phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan; ++ ++ /* This can only be done after all function pointers are setup. */ ++ ret_val = e1000e_get_phy_id(hw); ++ ++ /* Verify phy id */ ++ if (phy->id != GG82563_E_PHY_ID) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = er32(EECD); ++ u16 size; ++ ++ nvm->opcode_bits = 8; ++ nvm->delay_usec = 1; ++ switch (nvm->override) { ++ case e1000_nvm_override_spi_large: ++ nvm->page_size = 32; ++ nvm->address_bits = 16; ++ break; ++ case e1000_nvm_override_spi_small: ++ nvm->page_size = 8; ++ nvm->address_bits = 8; ++ break; ++ default: ++ nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; ++ nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; ++ break; ++ } ++ ++ nvm->type = e1000_nvm_eeprom_spi; ++ ++ size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> ++ E1000_EECD_SIZE_EX_SHIFT); ++ ++ /* ++ * Added to a constant, "size" becomes the left-shift value ++ * for setting word_size. ++ */ ++ size += NVM_WORD_SIZE_BASE_SHIFT; ++ ++ /* EEPROM access above 16k is unsupported */ ++ if (size > 14) ++ size = 14; ++ nvm->word_size = 1 << size; ++ ++ /* Function Pointers */ ++ nvm->ops.acquire = e1000_acquire_nvm_80003es2lan; ++ nvm->ops.read = e1000e_read_nvm_eerd; ++ nvm->ops.release = e1000_release_nvm_80003es2lan; ++ nvm->ops.update = e1000e_update_nvm_checksum_generic; ++ nvm->ops.valid_led_default = e1000e_valid_led_default; ++ nvm->ops.validate = e1000e_validate_nvm_checksum_generic; ++ nvm->ops.write = e1000_write_nvm_80003es2lan; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* Set media type */ ++ switch (hw->device_id) { ++ case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: ++ hw->phy.media_type = e1000_media_type_internal_serdes; ++ break; ++ default: ++ hw->phy.media_type = e1000_media_type_copper; ++ break; ++ } ++ ++ /* Set mta register count */ ++ mac->mta_reg_count = 128; ++ /* Set rar entry count */ ++ mac->rar_entry_count = E1000_RAR_ENTRIES; ++ /* Set if part includes ASF firmware */ ++ mac->asf_firmware_present = true; ++ /* Set if manageability features are enabled. */ ++ mac->arc_subsystem_valid = ++ (er32(FWSM) & E1000_FWSM_MODE_MASK) ++ ? true : false; ++ ++ /* Function pointers */ ++ ++ /* bus type/speed/width */ ++ mac->ops.get_bus_info = e1000e_get_bus_info_pcie; ++ /* reset */ ++ mac->ops.reset_hw = e1000_reset_hw_80003es2lan; ++ /* hw initialization */ ++ mac->ops.init_hw = e1000_init_hw_80003es2lan; ++ /* link setup */ ++ mac->ops.setup_link = e1000e_setup_link; ++ /* physical interface link setup */ ++ mac->ops.setup_physical_interface = ++ (hw->phy.media_type == e1000_media_type_copper) ++ ? e1000_setup_copper_link_80003es2lan ++ : e1000e_setup_fiber_serdes_link; ++ /* check for link */ ++ switch (hw->phy.media_type) { ++ case e1000_media_type_copper: ++ mac->ops.check_for_link = e1000e_check_for_copper_link; ++ break; ++ case e1000_media_type_fiber: ++ mac->ops.check_for_link = e1000e_check_for_fiber_link; ++ break; ++ case e1000_media_type_internal_serdes: ++ mac->ops.check_for_link = e1000e_check_for_serdes_link; ++ break; ++ default: ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ break; ++ } ++ /* check management mode */ ++ mac->ops.check_mng_mode = e1000_check_mng_mode_generic; ++ /* multicast address update */ ++ mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic; ++ /* writing VFTA */ ++ mac->ops.write_vfta = e1000e_write_vfta_generic; ++ /* clearing VFTA */ ++ mac->ops.clear_vfta = e1000e_clear_vfta_generic; ++ /* setting MTA */ ++ mac->ops.mta_set = e1000_mta_set_generic; ++ /* read mac address */ ++ mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan; ++ /* ID LED init */ ++ mac->ops.id_led_init = e1000e_id_led_init; ++ /* blink LED */ ++ mac->ops.blink_led = e1000e_blink_led; ++ /* setup LED */ ++ mac->ops.setup_led = e1000_setup_led_generic; ++ /* cleanup LED */ ++ mac->ops.cleanup_led = e1000e_cleanup_led_generic; ++ /* turn on/off LED */ ++ mac->ops.led_on = e1000e_led_on_generic; ++ mac->ops.led_off = e1000e_led_off_generic; ++ /* clear hardware counters */ ++ mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; ++ /* link info */ ++ mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. ++ * @hw: pointer to the HW structure ++ * ++ * Called to initialize all function pointers and parameters. ++ **/ ++void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) ++{ ++ e1000_init_mac_ops_generic(hw); ++ e1000_init_nvm_ops_generic(hw); ++ hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan; ++ hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan; ++ hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan; ++ e1000e_get_bus_info_pcie(hw); ++} ++ ++/** ++ * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY ++ * @hw: pointer to the HW structure ++ * ++ * A wrapper to acquire access rights to the correct PHY. ++ **/ ++static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) ++{ ++ u16 mask; ++ ++ mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; ++ return e1000_acquire_swfw_sync_80003es2lan(hw, mask); ++} ++ ++/** ++ * e1000_release_phy_80003es2lan - Release rights to access PHY ++ * @hw: pointer to the HW structure ++ * ++ * A wrapper to release access rights to the correct PHY. ++ **/ ++static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) ++{ ++ u16 mask; ++ ++ mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; ++ e1000_release_swfw_sync_80003es2lan(hw, mask); ++} ++ ++ ++/** ++ * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register ++ * @hw: pointer to the HW structure ++ * ++ * Acquire the semaphore to access the Kumeran interface. ++ * ++ **/ ++static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) ++{ ++ u16 mask; ++ ++ mask = E1000_SWFW_CSR_SM; ++ ++ return e1000_acquire_swfw_sync_80003es2lan(hw, mask); ++} ++ ++/** ++ * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register ++ * @hw: pointer to the HW structure ++ * ++ * Release the semaphore used to access the Kumeran interface ++ **/ ++static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) ++{ ++ u16 mask; ++ ++ mask = E1000_SWFW_CSR_SM; ++ ++ e1000_release_swfw_sync_80003es2lan(hw, mask); ++} ++ ++/** ++ * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM ++ * @hw: pointer to the HW structure ++ * ++ * Acquire the semaphore to access the EEPROM. ++ **/ ++static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ ++ ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000e_acquire_nvm(hw); ++ ++ if (ret_val) ++ e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM ++ * @hw: pointer to the HW structure ++ * ++ * Release the semaphore used to access the EEPROM. ++ **/ ++static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) ++{ ++ e1000e_release_nvm(hw); ++ e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); ++} ++ ++/** ++ * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore ++ * @hw: pointer to the HW structure ++ * @mask: specifies which semaphore to acquire ++ * ++ * Acquire the SW/FW semaphore to access the PHY or NVM. The mask ++ * will also specify which port we're acquiring the lock for. ++ **/ ++static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) ++{ ++ u32 swfw_sync; ++ u32 swmask = mask; ++ u32 fwmask = mask << 16; ++ s32 ret_val = E1000_SUCCESS; ++ s32 i = 0, timeout = 50; ++ ++ while (i < timeout) { ++ if (e1000e_get_hw_semaphore(hw)) { ++ ret_val = -E1000_ERR_SWFW_SYNC; ++ goto out; ++ } ++ ++ swfw_sync = er32(SW_FW_SYNC); ++ if (!(swfw_sync & (fwmask | swmask))) ++ break; ++ ++ /* ++ * Firmware currently using resource (fwmask) ++ * or other software thread using resource (swmask) ++ */ ++ e1000e_put_hw_semaphore(hw); ++ mdelay(5); ++ i++; ++ } ++ ++ if (i == timeout) { ++ e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); ++ ret_val = -E1000_ERR_SWFW_SYNC; ++ goto out; ++ } ++ ++ swfw_sync |= swmask; ++ ew32(SW_FW_SYNC, swfw_sync); ++ ++ e1000e_put_hw_semaphore(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore ++ * @hw: pointer to the HW structure ++ * @mask: specifies which semaphore to acquire ++ * ++ * Release the SW/FW semaphore used to access the PHY or NVM. The mask ++ * will also specify which port we're releasing the lock for. ++ **/ ++static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) ++{ ++ u32 swfw_sync; ++ ++ while (e1000e_get_hw_semaphore(hw) != E1000_SUCCESS) ++ ; /* Empty */ ++ ++ swfw_sync = er32(SW_FW_SYNC); ++ swfw_sync &= ~mask; ++ ew32(SW_FW_SYNC, swfw_sync); ++ ++ e1000e_put_hw_semaphore(hw); ++} ++ ++/** ++ * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register ++ * @hw: pointer to the HW structure ++ * @offset: offset of the register to read ++ * @data: pointer to the data returned from the operation ++ * ++ * Read the GG82563 PHY register. ++ **/ ++static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, ++ u32 offset, u16 *data) ++{ ++ s32 ret_val; ++ u32 page_select; ++ u16 temp; ++ ++ ret_val = e1000_acquire_phy_80003es2lan(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Select Configuration Page */ ++ if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { ++ page_select = GG82563_PHY_PAGE_SELECT; ++ } else { ++ /* ++ * Use Alternative Page Select register to access ++ * registers 30 and 31 ++ */ ++ page_select = GG82563_PHY_PAGE_SELECT_ALT; ++ } ++ ++ temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); ++ ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); ++ if (ret_val) { ++ e1000_release_phy_80003es2lan(hw); ++ goto out; ++ } ++ ++ /* ++ * The "ready" bit in the MDIC register may be incorrectly set ++ * before the device has completed the "Page Select" MDI ++ * transaction. So we wait 200us after each MDI command... ++ */ ++ udelay(200); ++ ++ /* ...and verify the command was successful. */ ++ ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); ++ ++ if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { ++ ret_val = -E1000_ERR_PHY; ++ e1000_release_phy_80003es2lan(hw); ++ goto out; ++ } ++ ++ udelay(200); ++ ++ ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ udelay(200); ++ e1000_release_phy_80003es2lan(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register ++ * @hw: pointer to the HW structure ++ * @offset: offset of the register to read ++ * @data: value to write to the register ++ * ++ * Write to the GG82563 PHY register. ++ **/ ++static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, ++ u32 offset, u16 data) ++{ ++ s32 ret_val; ++ u32 page_select; ++ u16 temp; ++ ++ ret_val = e1000_acquire_phy_80003es2lan(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Select Configuration Page */ ++ if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { ++ page_select = GG82563_PHY_PAGE_SELECT; ++ } else { ++ /* ++ * Use Alternative Page Select register to access ++ * registers 30 and 31 ++ */ ++ page_select = GG82563_PHY_PAGE_SELECT_ALT; ++ } ++ ++ temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); ++ ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); ++ if (ret_val) { ++ e1000_release_phy_80003es2lan(hw); ++ goto out; ++ } ++ ++ ++ /* ++ * The "ready" bit in the MDIC register may be incorrectly set ++ * before the device has completed the "Page Select" MDI ++ * transaction. So we wait 200us after each MDI command... ++ */ ++ udelay(200); ++ ++ /* ...and verify the command was successful. */ ++ ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); ++ ++ if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { ++ ret_val = -E1000_ERR_PHY; ++ e1000_release_phy_80003es2lan(hw); ++ goto out; ++ } ++ ++ udelay(200); ++ ++ ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ udelay(200); ++ e1000_release_phy_80003es2lan(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_nvm_80003es2lan - Write to ESB2 NVM ++ * @hw: pointer to the HW structure ++ * @offset: offset of the register to read ++ * @words: number of words to write ++ * @data: buffer of data to write to the NVM ++ * ++ * Write "words" of data to the ESB2 NVM. ++ **/ ++static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data) ++{ ++ return e1000e_write_nvm_spi(hw, offset, words, data); ++} ++ ++/** ++ * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete ++ * @hw: pointer to the HW structure ++ * ++ * Wait a specific amount of time for manageability processes to complete. ++ * This is a function pointer entry point called by the phy module. ++ **/ ++static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) ++{ ++ s32 timeout = PHY_CFG_TIMEOUT; ++ s32 ret_val = E1000_SUCCESS; ++ u32 mask = E1000_NVM_CFG_DONE_PORT_0; ++ ++ if (hw->bus.func == 1) ++ mask = E1000_NVM_CFG_DONE_PORT_1; ++ ++ while (timeout) { ++ if (er32(EEMNGCTL) & mask) ++ break; ++ msleep(1); ++ timeout--; ++ } ++ if (!timeout) { ++ e_dbg("MNG configuration cycle has not completed.\n"); ++ ret_val = -E1000_ERR_RESET; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex ++ * @hw: pointer to the HW structure ++ * ++ * Force the speed and duplex settings onto the PHY. This is a ++ * function pointer entry point called by the phy module. ++ **/ ++static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 phy_data; ++ bool link; ++ ++ if (!(hw->phy.ops.read_reg)) ++ goto out; ++ ++ /* ++ * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI ++ * forced whenever speed and duplex are forced. ++ */ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; ++ ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ e_dbg("GG82563 PSCR: %X\n", phy_data); ++ ++ ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ e1000e_phy_force_speed_duplex_setup(hw, &phy_data); ++ ++ /* Reset the phy to commit changes. */ ++ phy_data |= MII_CR_RESET; ++ ++ ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ udelay(1); ++ ++ if (hw->phy.autoneg_wait_to_complete) { ++ e_dbg("Waiting for forced speed/duplex link " ++ "on GG82563 phy.\n"); ++ ++ ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ 100000, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ /* ++ * We didn't get link. ++ * Reset the DSP and cross our fingers. ++ */ ++ ret_val = e1000e_phy_reset_dsp(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* Try once more */ ++ ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ 100000, &link); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Resetting the phy means we need to verify the TX_CLK corresponds ++ * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. ++ */ ++ phy_data &= ~GG82563_MSCR_TX_CLK_MASK; ++ if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) ++ phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; ++ else ++ phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; ++ ++ /* ++ * In addition, we must re-enable CRS on Tx for both half and full ++ * duplex. ++ */ ++ phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; ++ ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_cable_length_80003es2lan - Set approximate cable length ++ * @hw: pointer to the HW structure ++ * ++ * Find the approximate cable length as measured by the GG82563 PHY. ++ * This is a function pointer entry point called by the phy module. ++ **/ ++static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 phy_data, index; ++ ++ if (!(hw->phy.ops.read_reg)) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ index = phy_data & GG82563_DSPD_CABLE_LENGTH; ++ ++ if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE + 5) { ++ ret_val = E1000_ERR_PHY; ++ goto out; ++ } ++ ++ phy->min_cable_length = e1000_gg82563_cable_length_table[index]; ++ phy->max_cable_length = e1000_gg82563_cable_length_table[index+5]; ++ ++ phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_link_up_info_80003es2lan - Report speed and duplex ++ * @hw: pointer to the HW structure ++ * @speed: pointer to speed buffer ++ * @duplex: pointer to duplex buffer ++ * ++ * Retrieve the current speed and duplex configuration. ++ **/ ++static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex) ++{ ++ s32 ret_val; ++ ++ if (hw->phy.media_type == e1000_media_type_copper) { ++ ret_val = e1000e_get_speed_and_duplex_copper(hw, ++ speed, ++ duplex); ++ hw->phy.ops.cfg_on_link_up(hw); ++ } else { ++ ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, ++ speed, ++ duplex); ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_reset_hw_80003es2lan - Reset the ESB2 controller ++ * @hw: pointer to the HW structure ++ * ++ * Perform a global reset to the ESB2 controller. ++ **/ ++static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) ++{ ++ u32 ctrl, icr; ++ s32 ret_val; ++ ++ /* ++ * Prevent the PCI-E bus from sticking if there is no TLP connection ++ * on the last TLP read/write transaction when MAC is reset. ++ */ ++ ret_val = e1000e_disable_pcie_master(hw); ++ if (ret_val) ++ e_dbg("PCI-E Master disable polling has failed.\n"); ++ ++ e_dbg("Masking off all interrupts\n"); ++ ew32(IMC, 0xffffffff); ++ ++ ew32(RCTL, 0); ++ ew32(TCTL, E1000_TCTL_PSP); ++ e1e_flush(); ++ ++ msleep(10); ++ ++ ctrl = er32(CTRL); ++ ++ ret_val = e1000_acquire_phy_80003es2lan(hw); ++ e_dbg("Issuing a global reset to MAC\n"); ++ ew32(CTRL, ctrl | E1000_CTRL_RST); ++ e1000_release_phy_80003es2lan(hw); ++ ++ ret_val = e1000e_get_auto_rd_done(hw); ++ if (ret_val) ++ /* We don't want to continue accessing MAC registers. */ ++ goto out; ++ ++ /* Clear any pending interrupt events. */ ++ ew32(IMC, 0xffffffff); ++ icr = er32(ICR); ++ ++ ret_val = e1000_check_alt_mac_addr_generic(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_hw_80003es2lan - Initialize the ESB2 controller ++ * @hw: pointer to the HW structure ++ * ++ * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. ++ **/ ++static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 reg_data; ++ s32 ret_val; ++ u16 i; ++ ++ e1000_initialize_hw_bits_80003es2lan(hw); ++ ++ /* Initialize identification LED */ ++ ret_val = mac->ops.id_led_init(hw); ++ if (ret_val) { ++ e_dbg("Error initializing identification LED\n"); ++ /* This is not fatal and we should not stop init due to this */ ++ } ++ ++ /* Disabling VLAN filtering */ ++ e_dbg("Initializing the IEEE VLAN\n"); ++ e1000e_clear_vfta(hw); ++ ++ /* Setup the receive address. */ ++ e1000e_init_rx_addrs(hw, mac->rar_entry_count); ++ ++ /* Zero out the Multicast HASH table */ ++ e_dbg("Zeroing the MTA\n"); ++ for (i = 0; i < mac->mta_reg_count; i++) ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); ++ ++ /* Setup link and flow control */ ++ ret_val = mac->ops.setup_link(hw); ++ ++ /* Set the transmit descriptor write-back policy */ ++ reg_data = er32(TXDCTL(0)); ++ reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; ++ ew32(TXDCTL(0), reg_data); ++ ++ /* ...for both queues. */ ++ reg_data = er32(TXDCTL(1)); ++ reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; ++ ew32(TXDCTL(1), reg_data); ++ ++ /* Enable retransmit on late collisions */ ++ reg_data = er32(TCTL); ++ reg_data |= E1000_TCTL_RTLC; ++ ew32(TCTL, reg_data); ++ ++ /* Configure Gigabit Carry Extend Padding */ ++ reg_data = er32(TCTL_EXT); ++ reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; ++ reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; ++ ew32(TCTL_EXT, reg_data); ++ ++ /* Configure Transmit Inter-Packet Gap */ ++ reg_data = er32(TIPG); ++ reg_data &= ~E1000_TIPG_IPGT_MASK; ++ reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; ++ ew32(TIPG, reg_data); ++ ++ reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); ++ reg_data &= ~0x00100000; ++ E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); ++ ++ /* ++ * Clear all of the statistics registers (clear on read). It is ++ * important that we do this after we have tried to establish link ++ * because the symbol error count will increment wildly if there ++ * is no link. ++ */ ++ e1000_clear_hw_cntrs_80003es2lan(hw); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 ++ * @hw: pointer to the HW structure ++ * ++ * Initializes required hardware-dependent bits needed for normal operation. ++ **/ ++static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) ++{ ++ u32 reg; ++ ++ /* Transmit Descriptor Control 0 */ ++ reg = er32(TXDCTL(0)); ++ reg |= (1 << 22); ++ ew32(TXDCTL(0), reg); ++ ++ /* Transmit Descriptor Control 1 */ ++ reg = er32(TXDCTL(1)); ++ reg |= (1 << 22); ++ ew32(TXDCTL(1), reg); ++ ++ /* Transmit Arbitration Control 0 */ ++ reg = er32(TARC(0)); ++ reg &= ~(0xF << 27); /* 30:27 */ ++ if (hw->phy.media_type != e1000_media_type_copper) ++ reg &= ~(1 << 20); ++ ew32(TARC(0), reg); ++ ++ /* Transmit Arbitration Control 1 */ ++ reg = er32(TARC(1)); ++ if (er32(TCTL) & E1000_TCTL_MULR) ++ reg &= ~(1 << 28); ++ else ++ reg |= (1 << 28); ++ ew32(TARC(1), reg); ++ ++ return; ++} ++ ++/** ++ * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link ++ * @hw: pointer to the HW structure ++ * ++ * Setup some GG82563 PHY registers for obtaining link ++ **/ ++static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u32 ctrl_ext; ++ u16 data; ++ ++ if (!phy->reset_disable) { ++ ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data |= GG82563_MSCR_ASSERT_CRS_ON_TX; ++ /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ ++ data |= GG82563_MSCR_TX_CLK_1000MBPS_25; ++ ++ ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, ++ data); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Options: ++ * MDI/MDI-X = 0 (default) ++ * 0 - Auto for all speeds ++ * 1 - MDI mode ++ * 2 - MDI-X mode ++ * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) ++ */ ++ ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; ++ ++ switch (phy->mdix) { ++ case 1: ++ data |= GG82563_PSCR_CROSSOVER_MODE_MDI; ++ break; ++ case 2: ++ data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; ++ break; ++ case 0: ++ default: ++ data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; ++ break; ++ } ++ ++ /* ++ * Options: ++ * disable_polarity_correction = 0 (default) ++ * Automatic Correction for Reversed Cable Polarity ++ * 0 - Disabled ++ * 1 - Enabled ++ */ ++ data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; ++ if (phy->disable_polarity_correction) ++ data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; ++ ++ ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); ++ if (ret_val) ++ goto out; ++ ++ /* SW Reset the PHY so all changes take effect */ ++ ret_val = e1000e_commit_phy(hw); ++ if (ret_val) { ++ e_dbg("Error Resetting the PHY\n"); ++ goto out; ++ } ++ ++ } ++ ++ /* Bypass Rx and Tx FIFO's */ ++ ret_val = e1000_write_kmrn_reg_80003es2lan(hw, ++ E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, ++ E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | ++ E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_read_kmrn_reg_80003es2lan(hw, ++ E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, ++ &data); ++ if (ret_val) ++ goto out; ++ data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; ++ ret_val = e1000_write_kmrn_reg_80003es2lan(hw, ++ E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, ++ data); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; ++ ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); ++ if (ret_val) ++ goto out; ++ ++ ctrl_ext = er32(CTRL_EXT); ++ ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); ++ ew32(CTRL_EXT, ctrl_ext); ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Do not init these registers when the HW is in IAMT mode, since the ++ * firmware will have already initialized them. We only initialize ++ * them if the HW is not in IAMT mode. ++ */ ++ if (!(hw->mac.ops.check_mng_mode(hw))) { ++ /* Enable Electrical Idle on the PHY */ ++ data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; ++ ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, ++ data); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; ++ ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ++ data); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* ++ * Workaround: Disable padding in Kumeran interface in the MAC ++ * and in the PHY to avoid CRC errors. ++ */ ++ ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ data |= GG82563_ICR_DIS_PADDING; ++ ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); ++ if (ret_val) ++ goto out; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 ++ * @hw: pointer to the HW structure ++ * ++ * Essentially a wrapper for setting up all things "copper" related. ++ * This is a function pointer entry point called by the mac module. ++ **/ ++static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val; ++ u16 reg_data; ++ ++ ctrl = er32(CTRL); ++ ctrl |= E1000_CTRL_SLU; ++ ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ ew32(CTRL, ctrl); ++ ++ /* ++ * Set the mac to wait the maximum time between each ++ * iteration and increase the max iterations when ++ * polling the phy; this fixes erroneous timeouts at 10Mbps. ++ */ ++ ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), ++ 0xFFFF); ++ if (ret_val) ++ goto out; ++ ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), ++ ®_data); ++ if (ret_val) ++ goto out; ++ reg_data |= 0x3F; ++ ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), ++ reg_data); ++ if (ret_val) ++ goto out; ++ ret_val = e1000_read_kmrn_reg_80003es2lan(hw, ++ E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, ++ ®_data); ++ if (ret_val) ++ goto out; ++ reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; ++ ret_val = e1000_write_kmrn_reg_80003es2lan(hw, ++ E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, ++ reg_data); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000e_setup_copper_link(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up ++ * @hw: pointer to the HW structure ++ * @duplex: current duplex setting ++ * ++ * Configure the KMRN interface by applying last minute quirks for ++ * 10/100 operation. ++ **/ ++static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 speed; ++ u16 duplex; ++ ++ if (hw->phy.media_type == e1000_media_type_copper) { ++ ret_val = e1000e_get_speed_and_duplex_copper(hw, ++ &speed, ++ &duplex); ++ if (ret_val) ++ goto out; ++ ++ if (speed == SPEED_1000) ++ ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); ++ else ++ ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation ++ * @hw: pointer to the HW structure ++ * @duplex: current duplex setting ++ * ++ * Configure the KMRN interface by applying last minute quirks for ++ * 10/100 operation. ++ **/ ++static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u32 tipg; ++ u32 i = 0; ++ u16 reg_data, reg_data2; ++ ++ reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; ++ ret_val = e1000_write_kmrn_reg_80003es2lan(hw, ++ E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, ++ reg_data); ++ if (ret_val) ++ goto out; ++ ++ /* Configure Transmit Inter-Packet Gap */ ++ tipg = er32(TIPG); ++ tipg &= ~E1000_TIPG_IPGT_MASK; ++ tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; ++ ew32(TIPG, tipg); ++ ++ ++ do { ++ ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ++ ®_data); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ++ ®_data2); ++ if (ret_val) ++ goto out; ++ i++; ++ } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); ++ ++ if (duplex == HALF_DUPLEX) ++ reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; ++ else ++ reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; ++ ++ ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation ++ * @hw: pointer to the HW structure ++ * ++ * Configure the KMRN interface by applying last minute quirks for ++ * gigabit operation. ++ **/ ++static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 reg_data, reg_data2; ++ u32 tipg; ++ u32 i = 0; ++ ++ reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; ++ ret_val = e1000_write_kmrn_reg_80003es2lan(hw, ++ E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, ++ reg_data); ++ if (ret_val) ++ goto out; ++ ++ /* Configure Transmit Inter-Packet Gap */ ++ tipg = er32(TIPG); ++ tipg &= ~E1000_TIPG_IPGT_MASK; ++ tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; ++ ew32(TIPG, tipg); ++ ++ ++ do { ++ ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ++ ®_data); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ++ ®_data2); ++ if (ret_val) ++ goto out; ++ i++; ++ } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); ++ ++ reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; ++ ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_kmrn_reg_80003es2lan - Read kumeran register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquire semaphore, then read the PHY register at offset ++ * using the kumeran interface. The information retrieved is stored in data. ++ * Release the semaphore before exiting. ++ **/ ++static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, ++ u16 *data) ++{ ++ u32 kmrnctrlsta; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ret_val = e1000_acquire_mac_csr_80003es2lan(hw); ++ if (ret_val) ++ goto out; ++ ++ kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & ++ E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; ++ ew32(KMRNCTRLSTA, kmrnctrlsta); ++ ++ udelay(2); ++ ++ kmrnctrlsta = er32(KMRNCTRLSTA); ++ *data = (u16)kmrnctrlsta; ++ ++ e1000_release_mac_csr_80003es2lan(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_kmrn_reg_80003es2lan - Write kumeran register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquire semaphore, then write the data to PHY register ++ * at the offset using the kumeran interface. Release semaphore ++ * before exiting. ++ **/ ++static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, ++ u16 data) ++{ ++ u32 kmrnctrlsta; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ret_val = e1000_acquire_mac_csr_80003es2lan(hw); ++ if (ret_val) ++ goto out; ++ ++ kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & ++ E1000_KMRNCTRLSTA_OFFSET) | data; ++ ew32(KMRNCTRLSTA, kmrnctrlsta); ++ ++ udelay(2); ++ ++ e1000_release_mac_csr_80003es2lan(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_mac_addr_80003es2lan - Read device MAC address ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* ++ * If there's an alternate MAC address place it in RAR0 ++ * so that it will override the Si installed default perm ++ * address. ++ */ ++ ret_val = e1000_check_alt_mac_addr_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000e_read_mac_addr_generic(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down ++ * @hw: pointer to the HW structure ++ * ++ * In the case of a PHY power down to save power, or to turn off link during a ++ * driver unload, or wake on lan is not enabled, remove the link. ++ **/ ++static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) ++{ ++ /* If the management interface is not enabled, then power down */ ++ if (!(hw->mac.ops.check_mng_mode(hw) || ++ e1000_check_reset_block(hw))) ++ e1000_power_down_phy_copper(hw); ++ ++ return; ++} ++ ++/** ++ * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters ++ * @hw: pointer to the HW structure ++ * ++ * Clears the hardware counters by reading the counter registers. ++ **/ ++static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) ++{ ++ e1000e_clear_hw_cntrs_base(hw); ++ ++ er32(PRC64); ++ er32(PRC127); ++ er32(PRC255); ++ er32(PRC511); ++ er32(PRC1023); ++ er32(PRC1522); ++ er32(PTC64); ++ er32(PTC127); ++ er32(PTC255); ++ er32(PTC511); ++ er32(PTC1023); ++ er32(PTC1522); ++ ++ er32(ALGNERRC); ++ er32(RXERRC); ++ er32(TNCRS); ++ er32(CEXTERR); ++ er32(TSCTC); ++ er32(TSCTFC); ++ ++ er32(MGTPRC); ++ er32(MGTPDC); ++ er32(MGTPTC); ++ ++ er32(IAC); ++ er32(ICRXOC); ++ ++ er32(ICRXPTC); ++ er32(ICRXATC); ++ er32(ICTXPTC); ++ er32(ICTXATC); ++ er32(ICTXQEC); ++ er32(ICTXQMTC); ++ er32(ICRXDMTC); ++} +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_80003es2lan.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_80003es2lan.h Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,95 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_80003ES2LAN_H_ ++#define _E1000_80003ES2LAN_H_ ++ ++#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 ++#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 ++#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 ++#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F ++ ++#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 ++#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 ++#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 ++ ++#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 ++#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 ++#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 ++ ++#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ ++#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 ++ ++#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 ++#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 ++ ++/* GG82563 PHY Specific Status Register (Page 0, Register 16 */ ++#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disabled */ ++#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 ++#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ ++#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ ++#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ ++ ++/* PHY Specific Control Register 2 (Page 0, Register 26) */ ++#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 ++ /* 1=Reverse Auto-Negotiation */ ++ ++/* MAC Specific Control Register (Page 2, Register 21) */ ++/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ ++#define GG82563_MSCR_TX_CLK_MASK 0x0007 ++#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 ++#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 ++#define GG82563_MSCR_TX_CLK_1000MBPS_2_5 0x0006 ++#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 ++ ++#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ ++ ++/* DSP Distance Register (Page 5, Register 26) */ ++/* ++ * 0 = <50M ++ * 1 = 50-80M ++ * 2 = 80-100M ++ * 3 = 110-140M ++ * 4 = >140M ++ */ ++#define GG82563_DSPD_CABLE_LENGTH 0x0007 ++ ++/* Kumeran Mode Control Register (Page 193, Register 16) */ ++#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 ++ ++/* Max number of times Kumeran read/write should be validated */ ++#define GG82563_MAX_KMRN_RETRY 0x5 ++ ++/* Power Management Control Register (Page 193, Register 20) */ ++#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 ++ /* 1=Enable SERDES Electrical Idle */ ++ ++/* In-Band Control Register (Page 194, Register 18) */ ++#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ ++ ++#endif +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_82571.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_82571.c Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,1767 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * 82571EB Gigabit Ethernet Controller ++ * 82571EB Gigabit Ethernet Controller (Copper) ++ * 82571EB Gigabit Ethernet Controller (Fiber) ++ * 82571EB Dual Port Gigabit Mezzanine Adapter ++ * 82571EB Quad Port Gigabit Mezzanine Adapter ++ * 82571PT Gigabit PT Quad Port Server ExpressModule ++ * 82572EI Gigabit Ethernet Controller (Copper) ++ * 82572EI Gigabit Ethernet Controller (Fiber) ++ * 82572EI Gigabit Ethernet Controller ++ * 82573V Gigabit Ethernet Controller (Copper) ++ * 82573E Gigabit Ethernet Controller (Copper) ++ * 82573L Gigabit Ethernet Controller ++ * 82574L Gigabit Network Connection ++ * 82574L Gigabit Network Connection ++ * 82583V Gigabit Network Connection ++ */ ++ ++#include "e1000.h" ++ ++static s32 e1000_init_phy_params_82571(struct e1000_hw *hw); ++static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); ++static s32 e1000_init_mac_params_82571(struct e1000_hw *hw); ++static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); ++static void e1000_release_nvm_82571(struct e1000_hw *hw); ++static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data); ++static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); ++static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); ++static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); ++static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, ++ bool active); ++static s32 e1000_reset_hw_82571(struct e1000_hw *hw); ++static s32 e1000_init_hw_82571(struct e1000_hw *hw); ++static void e1000_clear_vfta_82571(struct e1000_hw *hw); ++static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); ++static s32 e1000_led_on_82574(struct e1000_hw *hw); ++static s32 e1000_setup_link_82571(struct e1000_hw *hw); ++static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); ++static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); ++static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); ++static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); ++static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); ++static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); ++static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); ++static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); ++static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); ++static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); ++static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data); ++static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); ++static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); ++ ++/** ++ * e1000_init_phy_params_82571 - Init PHY func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->phy.media_type != e1000_media_type_copper) { ++ phy->type = e1000_phy_none; ++ goto out; ++ } ++ ++ phy->addr = 1; ++ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; ++ phy->reset_delay_us = 100; ++ ++ phy->ops.acquire = e1000_get_hw_semaphore_82571; ++ phy->ops.check_polarity = e1000_check_polarity_igp; ++ phy->ops.check_reset_block = e1000e_check_reset_block_generic; ++ phy->ops.release = e1000_put_hw_semaphore_82571; ++ phy->ops.reset = e1000e_phy_hw_reset_generic; ++ phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; ++ phy->ops.set_d3_lplu_state = e1000e_set_d3_lplu_state; ++ phy->ops.power_up = e1000_power_up_phy_copper; ++ phy->ops.power_down = e1000_power_down_phy_copper_82571; ++ ++ switch (hw->mac.type) { ++ case e1000_82571: ++ case e1000_82572: ++ phy->type = e1000_phy_igp_2; ++ phy->ops.get_cfg_done = e1000_get_cfg_done_82571; ++ phy->ops.get_info = e1000e_get_phy_info_igp; ++ phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; ++ phy->ops.get_cable_length = e1000e_get_cable_length_igp_2; ++ phy->ops.read_reg = e1000e_read_phy_reg_igp; ++ phy->ops.write_reg = e1000e_write_phy_reg_igp; ++ ++ /* This uses above function pointers */ ++ ret_val = e1000_get_phy_id_82571(hw); ++ ++ /* Verify PHY ID */ ++ if (phy->id != IGP01E1000_I_PHY_ID) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ break; ++ case e1000_82573: ++ phy->type = e1000_phy_m88; ++ phy->ops.get_cfg_done = e1000e_get_cfg_done; ++ phy->ops.get_info = e1000e_get_phy_info_m88; ++ phy->ops.commit = e1000e_phy_sw_reset; ++ phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; ++ phy->ops.get_cable_length = e1000e_get_cable_length_m88; ++ phy->ops.read_reg = e1000e_read_phy_reg_m88; ++ phy->ops.write_reg = e1000e_write_phy_reg_m88; ++ ++ /* This uses above function pointers */ ++ ret_val = e1000_get_phy_id_82571(hw); ++ ++ /* Verify PHY ID */ ++ if (phy->id != M88E1111_I_PHY_ID) { ++ ret_val = -E1000_ERR_PHY; ++ e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id); ++ goto out; ++ } ++ break; ++ case e1000_82583: ++ case e1000_82574: ++ phy->type = e1000_phy_bm; ++ phy->ops.get_cfg_done = e1000e_get_cfg_done; ++ phy->ops.get_info = e1000e_get_phy_info_m88; ++ phy->ops.commit = e1000e_phy_sw_reset; ++ phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; ++ phy->ops.get_cable_length = e1000e_get_cable_length_m88; ++ phy->ops.read_reg = e1000e_read_phy_reg_bm2; ++ phy->ops.write_reg = e1000e_write_phy_reg_bm2; ++ ++ /* This uses above function pointers */ ++ ret_val = e1000_get_phy_id_82571(hw); ++ /* Verify PHY ID */ ++ if (phy->id != BME1000_E_PHY_ID_R2) { ++ ret_val = -E1000_ERR_PHY; ++ e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id); ++ goto out; ++ } ++ break; ++ default: ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ break; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_nvm_params_82571 - Init NVM func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = er32(EECD); ++ u16 size; ++ ++ nvm->opcode_bits = 8; ++ nvm->delay_usec = 1; ++ switch (nvm->override) { ++ case e1000_nvm_override_spi_large: ++ nvm->page_size = 32; ++ nvm->address_bits = 16; ++ break; ++ case e1000_nvm_override_spi_small: ++ nvm->page_size = 8; ++ nvm->address_bits = 8; ++ break; ++ default: ++ nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; ++ nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; ++ break; ++ } ++ ++ switch (hw->mac.type) { ++ case e1000_82573: ++ case e1000_82574: ++ case e1000_82583: ++ if (((eecd >> 15) & 0x3) == 0x3) { ++ nvm->type = e1000_nvm_flash_hw; ++ nvm->word_size = 2048; ++ /* ++ * Autonomous Flash update bit must be cleared due ++ * to Flash update issue. ++ */ ++ eecd &= ~E1000_EECD_AUPDEN; ++ ew32(EECD, eecd); ++ break; ++ } ++ /* Fall Through */ ++ default: ++ nvm->type = e1000_nvm_eeprom_spi; ++ size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> ++ E1000_EECD_SIZE_EX_SHIFT); ++ /* ++ * Added to a constant, "size" becomes the left-shift value ++ * for setting word_size. ++ */ ++ size += NVM_WORD_SIZE_BASE_SHIFT; ++ ++ /* EEPROM access above 16k is unsupported */ ++ if (size > 14) ++ size = 14; ++ nvm->word_size = 1 << size; ++ break; ++ } ++ ++ /* Function Pointers */ ++ nvm->ops.acquire = e1000_acquire_nvm_82571; ++ nvm->ops.read = e1000e_read_nvm_eerd; ++ nvm->ops.release = e1000_release_nvm_82571; ++ nvm->ops.update = e1000_update_nvm_checksum_82571; ++ nvm->ops.validate = e1000_validate_nvm_checksum_82571; ++ nvm->ops.valid_led_default = e1000_valid_led_default_82571; ++ nvm->ops.write = e1000_write_nvm_82571; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_init_mac_params_82571 - Init MAC func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ u32 swsm = 0; ++ u32 swsm2 = 0; ++ bool force_clear_smbi = false; ++ ++ /* Set media type */ ++ switch (hw->device_id) { ++ case E1000_DEV_ID_82571EB_FIBER: ++ case E1000_DEV_ID_82572EI_FIBER: ++ case E1000_DEV_ID_82571EB_QUAD_FIBER: ++ hw->phy.media_type = e1000_media_type_fiber; ++ break; ++ case E1000_DEV_ID_82571EB_SERDES: ++ case E1000_DEV_ID_82571EB_SERDES_DUAL: ++ case E1000_DEV_ID_82571EB_SERDES_QUAD: ++ case E1000_DEV_ID_82572EI_SERDES: ++ hw->phy.media_type = e1000_media_type_internal_serdes; ++ break; ++ default: ++ hw->phy.media_type = e1000_media_type_copper; ++ break; ++ } ++ ++ /* Set mta register count */ ++ mac->mta_reg_count = 128; ++ /* Set rar entry count */ ++ mac->rar_entry_count = E1000_RAR_ENTRIES; ++ /* Set if part includes ASF firmware */ ++ mac->asf_firmware_present = true; ++ /* Set if manageability features are enabled. */ ++ mac->arc_subsystem_valid = ++ (er32(FWSM) & E1000_FWSM_MODE_MASK) ++ ? true : false; ++ ++ /* Function pointers */ ++ ++ /* bus type/speed/width */ ++ mac->ops.get_bus_info = e1000e_get_bus_info_pcie; ++ /* function id */ ++ switch (hw->mac.type) { ++ case e1000_82573: ++ case e1000_82574: ++ case e1000_82583: ++ mac->ops.set_lan_id = e1000_set_lan_id_single_port; ++ break; ++ default: ++ break; ++ } ++ /* reset */ ++ mac->ops.reset_hw = e1000_reset_hw_82571; ++ /* hw initialization */ ++ mac->ops.init_hw = e1000_init_hw_82571; ++ /* link setup */ ++ mac->ops.setup_link = e1000_setup_link_82571; ++ /* physical interface link setup */ ++ mac->ops.setup_physical_interface = ++ (hw->phy.media_type == e1000_media_type_copper) ++ ? e1000_setup_copper_link_82571 ++ : e1000_setup_fiber_serdes_link_82571; ++ /* check for link */ ++ switch (hw->phy.media_type) { ++ case e1000_media_type_copper: ++ mac->ops.check_for_link = e1000e_check_for_copper_link; ++ break; ++ case e1000_media_type_fiber: ++ mac->ops.check_for_link = e1000e_check_for_fiber_link; ++ break; ++ case e1000_media_type_internal_serdes: ++ mac->ops.check_for_link = e1000_check_for_serdes_link_82571; ++ break; ++ default: ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ break; ++ } ++ /* check management mode */ ++ switch (hw->mac.type) { ++ case e1000_82574: ++ case e1000_82583: ++ mac->ops.check_mng_mode = e1000_check_mng_mode_82574; ++ break; ++ default: ++ mac->ops.check_mng_mode = e1000_check_mng_mode_generic; ++ break; ++ } ++ /* multicast address update */ ++ mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic; ++ /* writing VFTA */ ++ mac->ops.write_vfta = e1000e_write_vfta_generic; ++ /* clearing VFTA */ ++ mac->ops.clear_vfta = e1000_clear_vfta_82571; ++ /* setting MTA */ ++ mac->ops.mta_set = e1000_mta_set_generic; ++ /* read mac address */ ++ mac->ops.read_mac_addr = e1000_read_mac_addr_82571; ++ /* ID LED init */ ++ mac->ops.id_led_init = e1000e_id_led_init; ++ /* blink LED */ ++ mac->ops.blink_led = e1000e_blink_led; ++ /* setup LED */ ++ mac->ops.setup_led = e1000_setup_led_generic; ++ /* cleanup LED */ ++ mac->ops.cleanup_led = e1000e_cleanup_led_generic; ++ /* turn on/off LED */ ++ switch (hw->mac.type) { ++ case e1000_82574: ++ case e1000_82583: ++ mac->ops.led_on = e1000_led_on_82574; ++ break; ++ default: ++ mac->ops.led_on = e1000e_led_on_generic; ++ break; ++ } ++ mac->ops.led_off = e1000e_led_off_generic; ++ /* clear hardware counters */ ++ mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; ++ /* link info */ ++ mac->ops.get_link_up_info = ++ (hw->phy.media_type == e1000_media_type_copper) ++ ? e1000e_get_speed_and_duplex_copper ++ : e1000e_get_speed_and_duplex_fiber_serdes; ++ ++ /* ++ * Ensure that the inter-port SWSM.SMBI lock bit is clear before ++ * first NVM or PHY acess. This should be done for single-port ++ * devices, and for one port only on dual-port devices so that ++ * for those devices we can still use the SMBI lock to synchronize ++ * inter-port accesses to the PHY & NVM. ++ */ ++ switch (hw->mac.type) { ++ case e1000_82571: ++ case e1000_82572: ++ swsm2 = er32(SWSM2); ++ ++ if (!(swsm2 & E1000_SWSM2_LOCK)) { ++ /* Only do this for the first interface on this card */ ++ ew32(SWSM2, ++ swsm2 | E1000_SWSM2_LOCK); ++ force_clear_smbi = true; ++ } else ++ force_clear_smbi = false; ++ break; ++ default: ++ force_clear_smbi = true; ++ break; ++ } ++ ++ if (force_clear_smbi) { ++ /* Make sure SWSM.SMBI is clear */ ++ swsm = er32(SWSM); ++ if (swsm & E1000_SWSM_SMBI) { ++ /* This bit should not be set on a first interface, and ++ * indicates that the bootagent or EFI code has ++ * improperly left this bit enabled ++ */ ++ e_dbg("Please update your 82571 Bootagent\n"); ++ } ++ ew32(SWSM, swsm & ~E1000_SWSM_SMBI); ++ } ++ ++ /* ++ * Initialze device specific counter of SMBI acquisition ++ * timeouts. ++ */ ++ hw->dev_spec._82571.smb_counter = 0; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_function_pointers_82571 - Init func ptrs. ++ * @hw: pointer to the HW structure ++ * ++ * Called to initialize all function pointers and parameters. ++ **/ ++void e1000_init_function_pointers_82571(struct e1000_hw *hw) ++{ ++ e1000_init_mac_ops_generic(hw); ++ e1000_init_nvm_ops_generic(hw); ++ hw->mac.ops.init_params = e1000_init_mac_params_82571; ++ hw->nvm.ops.init_params = e1000_init_nvm_params_82571; ++ hw->phy.ops.init_params = e1000_init_phy_params_82571; ++} ++ ++/** ++ * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision ++ * @hw: pointer to the HW structure ++ * ++ * Reads the PHY registers and stores the PHY ID and possibly the PHY ++ * revision in the hardware structure. ++ **/ ++static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 phy_id = 0; ++ ++ switch (hw->mac.type) { ++ case e1000_82571: ++ case e1000_82572: ++ /* ++ * The 82571 firmware may still be configuring the PHY. ++ * In this case, we cannot access the PHY until the ++ * configuration is done. So we explicitly set the ++ * PHY ID. ++ */ ++ phy->id = IGP01E1000_I_PHY_ID; ++ break; ++ case e1000_82573: ++ ret_val = e1000e_get_phy_id(hw); ++ break; ++ case e1000_82574: ++ case e1000_82583: ++ ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); ++ if (ret_val) ++ goto out; ++ ++ phy->id = (u32)(phy_id << 16); ++ udelay(20); ++ ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); ++ if (ret_val) ++ goto out; ++ ++ phy->id |= (u32)(phy_id); ++ phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); ++ break; ++ default: ++ ret_val = -E1000_ERR_PHY; ++ break; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore ++ * @hw: pointer to the HW structure ++ * ++ * Acquire the HW semaphore to access the PHY or NVM ++ **/ ++s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) ++{ ++ u32 swsm; ++ s32 ret_val = E1000_SUCCESS; ++ s32 sw_timeout = hw->nvm.word_size + 1; ++ s32 fw_timeout = hw->nvm.word_size + 1; ++ s32 i = 0; ++ ++ /* ++ * If we have timedout 3 times on trying to acquire ++ * the inter-port SMBI semaphore, there is old code ++ * operating on the other port, and it is not ++ * releasing SMBI. Modify the number of times that ++ * we try for the semaphore to interwork with this ++ * older code. ++ */ ++ if (hw->dev_spec._82571.smb_counter > 2) ++ sw_timeout = 1; ++ ++ /* Get the SW semaphore */ ++ while (i < sw_timeout) { ++ swsm = er32(SWSM); ++ if (!(swsm & E1000_SWSM_SMBI)) ++ break; ++ ++ udelay(50); ++ i++; ++ } ++ ++ if (i == sw_timeout) { ++ e_dbg("Driver can't access device - SMBI bit is set.\n"); ++ hw->dev_spec._82571.smb_counter++; ++ } ++ /* Get the FW semaphore. */ ++ for (i = 0; i < fw_timeout; i++) { ++ swsm = er32(SWSM); ++ ew32(SWSM, swsm | E1000_SWSM_SWESMBI); ++ ++ /* Semaphore acquired if bit latched */ ++ if (er32(SWSM) & E1000_SWSM_SWESMBI) ++ break; ++ ++ udelay(50); ++ } ++ ++ if (i == fw_timeout) { ++ /* Release semaphores */ ++ e1000_put_hw_semaphore_82571(hw); ++ e_dbg("Driver can't access the NVM\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_put_hw_semaphore_82571 - Release hardware semaphore ++ * @hw: pointer to the HW structure ++ * ++ * Release hardware semaphore used to access the PHY or NVM ++ **/ ++void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) ++{ ++ u32 swsm; ++ ++ swsm = er32(SWSM); ++ swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); ++ ew32(SWSM, swsm); ++} ++/** ++ * e1000_acquire_nvm_82571 - Request for access to the EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * To gain access to the EEPROM, first we must obtain a hardware semaphore. ++ * Then for non-82573 hardware, set the EEPROM access request bit and wait ++ * for EEPROM access grant bit. If the access grant bit is not set, release ++ * hardware semaphore. ++ **/ ++static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ ++ ret_val = e1000_get_hw_semaphore_82571(hw); ++ if (ret_val) ++ goto out; ++ ++ switch (hw->mac.type) { ++ case e1000_82574: ++ case e1000_82583: ++ case e1000_82573: ++ break; ++ default: ++ ret_val = e1000e_acquire_nvm(hw); ++ break; ++ } ++ ++ if (ret_val) ++ e1000_put_hw_semaphore_82571(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_release_nvm_82571 - Release exclusive access to EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Stop any current commands to the EEPROM and clear the EEPROM request bit. ++ **/ ++static void e1000_release_nvm_82571(struct e1000_hw *hw) ++{ ++ e1000e_release_nvm(hw); ++ e1000_put_hw_semaphore_82571(hw); ++} ++ ++/** ++ * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface ++ * @hw: pointer to the HW structure ++ * @offset: offset within the EEPROM to be written to ++ * @words: number of words to write ++ * @data: 16 bit word(s) to be written to the EEPROM ++ * ++ * For non-82573 silicon, write data to EEPROM at offset using SPI interface. ++ * ++ * If e1000_update_nvm_checksum is not called after this function, the ++ * EEPROM will most likely contain an invalid checksum. ++ **/ ++static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ switch (hw->mac.type) { ++ case e1000_82573: ++ case e1000_82574: ++ case e1000_82583: ++ ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); ++ break; ++ case e1000_82571: ++ case e1000_82572: ++ ret_val = e1000e_write_nvm_spi(hw, offset, words, data); ++ break; ++ default: ++ ret_val = -E1000_ERR_NVM; ++ break; ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_update_nvm_checksum_82571 - Update EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Updates the EEPROM checksum by reading/adding each word of the EEPROM ++ * up to the checksum. Then calculates the EEPROM checksum and writes the ++ * value to the EEPROM. ++ **/ ++static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) ++{ ++ u32 eecd; ++ s32 ret_val; ++ u16 i; ++ ++ ret_val = e1000e_update_nvm_checksum_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * If our nvm is an EEPROM, then we're done ++ * otherwise, commit the checksum to the flash NVM. ++ */ ++ if (hw->nvm.type != e1000_nvm_flash_hw) ++ goto out; ++ ++ /* Check for pending operations. */ ++ for (i = 0; i < E1000_FLASH_UPDATES; i++) { ++ msleep(1); ++ if ((er32(EECD) & E1000_EECD_FLUPD) == 0) ++ break; ++ } ++ ++ if (i == E1000_FLASH_UPDATES) { ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ /* Reset the firmware if using STM opcode. */ ++ if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { ++ /* ++ * The enabling of and the actual reset must be done ++ * in two write cycles. ++ */ ++ ew32(HICR, E1000_HICR_FW_RESET_ENABLE); ++ e1e_flush(); ++ ew32(HICR, E1000_HICR_FW_RESET); ++ } ++ ++ /* Commit the write to flash */ ++ eecd = er32(EECD) | E1000_EECD_FLUPD; ++ ew32(EECD, eecd); ++ ++ for (i = 0; i < E1000_FLASH_UPDATES; i++) { ++ msleep(1); ++ if ((er32(EECD) & E1000_EECD_FLUPD) == 0) ++ break; ++ } ++ ++ if (i == E1000_FLASH_UPDATES) { ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Calculates the EEPROM checksum by reading/adding each word of the EEPROM ++ * and then verifies that the sum of the EEPROM is equal to 0xBABA. ++ **/ ++static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) ++{ ++ if (hw->nvm.type == e1000_nvm_flash_hw) ++ e1000_fix_nvm_checksum_82571(hw); ++ ++ return e1000e_validate_nvm_checksum_generic(hw); ++} ++ ++/** ++ * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon ++ * @hw: pointer to the HW structure ++ * @offset: offset within the EEPROM to be written to ++ * @words: number of words to write ++ * @data: 16 bit word(s) to be written to the EEPROM ++ * ++ * After checking for invalid values, poll the EEPROM to ensure the previous ++ * command has completed before trying to write the next word. After write ++ * poll for completion. ++ * ++ * If e1000_update_nvm_checksum is not called after this function, the ++ * EEPROM will most likely contain an invalid checksum. ++ **/ ++static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 i, eewr = 0; ++ s32 ret_val = 0; ++ ++ /* ++ * A check for invalid values: offset too large, too many words, ++ * and not enough words. ++ */ ++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || ++ (words == 0)) { ++ e_dbg("nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ for (i = 0; i < words; i++) { ++ eewr = (data[i] << E1000_NVM_RW_REG_DATA) | ++ ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | ++ E1000_NVM_RW_REG_START; ++ ++ ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); ++ if (ret_val) ++ break; ++ ++ ew32(EEWR, eewr); ++ ++ ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); ++ if (ret_val) ++ break; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_cfg_done_82571 - Poll for configuration done ++ * @hw: pointer to the HW structure ++ * ++ * Reads the management control register for the config done bit to be set. ++ **/ ++static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) ++{ ++ s32 timeout = PHY_CFG_TIMEOUT; ++ s32 ret_val = E1000_SUCCESS; ++ ++ while (timeout) { ++ if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) ++ break; ++ msleep(1); ++ timeout--; ++ } ++ if (!timeout) { ++ e_dbg("MNG configuration cycle has not completed.\n"); ++ ret_val = -E1000_ERR_RESET; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state ++ * @hw: pointer to the HW structure ++ * @active: true to enable LPLU, false to disable ++ * ++ * Sets the LPLU D0 state according to the active flag. When activating LPLU ++ * this function also disables smart speed and vice versa. LPLU will not be ++ * activated unless the device autonegotiation advertisement meets standards ++ * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function ++ * pointer entry point only called by PHY setup routines. ++ **/ ++static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 data; ++ ++ if (!(phy->ops.read_reg)) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); ++ if (ret_val) ++ goto out; ++ ++ if (active) { ++ data |= IGP02E1000_PM_D0_LPLU; ++ ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, ++ data); ++ if (ret_val) ++ goto out; ++ ++ /* When LPLU is enabled, we should disable SmartSpeed */ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } else { ++ data &= ~IGP02E1000_PM_D0_LPLU; ++ ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, ++ data); ++ /* ++ * LPLU and SmartSpeed are mutually exclusive. LPLU is used ++ * during Dx states where the power conservation is most ++ * important. During driver activity we should enable ++ * SmartSpeed, so performance is maintained. ++ */ ++ if (phy->smart_speed == e1000_smart_speed_on) { ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data |= IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } else if (phy->smart_speed == e1000_smart_speed_off) { ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_reset_hw_82571 - Reset hardware ++ * @hw: pointer to the HW structure ++ * ++ * This resets the hardware into a known state. ++ **/ ++static s32 e1000_reset_hw_82571(struct e1000_hw *hw) ++{ ++ u32 ctrl, extcnf_ctrl, ctrl_ext, icr; ++ s32 ret_val; ++ u16 i = 0; ++ ++ /* ++ * Prevent the PCI-E bus from sticking if there is no TLP connection ++ * on the last TLP read/write transaction when MAC is reset. ++ */ ++ ret_val = e1000e_disable_pcie_master(hw); ++ if (ret_val) ++ e_dbg("PCI-E Master disable polling has failed.\n"); ++ ++ e_dbg("Masking off all interrupts\n"); ++ ew32(IMC, 0xffffffff); ++ ++ ew32(RCTL, 0); ++ ew32(TCTL, E1000_TCTL_PSP); ++ e1e_flush(); ++ ++ msleep(10); ++ ++ /* ++ * Must acquire the MDIO ownership before MAC reset. ++ * Ownership defaults to firmware after a reset. ++ */ ++ switch (hw->mac.type) { ++ case e1000_82574: ++ case e1000_82583: ++ case e1000_82573: ++ extcnf_ctrl = er32(EXTCNF_CTRL); ++ extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; ++ ++ do { ++ ew32(EXTCNF_CTRL, extcnf_ctrl); ++ extcnf_ctrl = er32(EXTCNF_CTRL); ++ ++ if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) ++ break; ++ ++ extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; ++ ++ msleep(2); ++ i++; ++ } while (i < MDIO_OWNERSHIP_TIMEOUT); ++ break; ++ default: ++ break; ++ } ++ ++ ctrl = er32(CTRL); ++ ++ e_dbg("Issuing a global reset to MAC\n"); ++ ew32(CTRL, ctrl | E1000_CTRL_RST); ++ ++ if (hw->nvm.type == e1000_nvm_flash_hw) { ++ udelay(10); ++ ctrl_ext = er32(CTRL_EXT); ++ ctrl_ext |= E1000_CTRL_EXT_EE_RST; ++ ew32(CTRL_EXT, ctrl_ext); ++ e1e_flush(); ++ } ++ ++ ret_val = e1000e_get_auto_rd_done(hw); ++ if (ret_val) ++ /* We don't want to continue accessing MAC registers. */ ++ goto out; ++ ++ /* ++ * Phy configuration from NVM just starts after EECD_AUTO_RD is set. ++ * Need to wait for Phy configuration completion before accessing ++ * NVM and Phy. ++ */ ++ ++ switch (hw->mac.type) { ++ case e1000_82574: ++ case e1000_82583: ++ case e1000_82573: ++ msleep(25); ++ break; ++ default: ++ break; ++ } ++ ++ /* Clear any pending interrupt events. */ ++ ew32(IMC, 0xffffffff); ++ icr = er32(ICR); ++ ++ /* Install any alternate MAC address into RAR0 */ ++ ret_val = e1000_check_alt_mac_addr_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ e1000e_set_laa_state_82571(hw, true); ++ ++ /* Reinitialize the 82571 serdes link state machine */ ++ if (hw->phy.media_type == e1000_media_type_internal_serdes) ++ hw->mac.serdes_link_state = e1000_serdes_link_down; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_hw_82571 - Initialize hardware ++ * @hw: pointer to the HW structure ++ * ++ * This inits the hardware readying it for operation. ++ **/ ++static s32 e1000_init_hw_82571(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 reg_data; ++ s32 ret_val; ++ u16 i, rar_count = mac->rar_entry_count; ++ ++ e1000_initialize_hw_bits_82571(hw); ++ ++ /* Initialize identification LED */ ++ ret_val = mac->ops.id_led_init(hw); ++ if (ret_val) { ++ e_dbg("Error initializing identification LED\n"); ++ /* This is not fatal and we should not stop init due to this */ ++ } ++ ++ /* Disabling VLAN filtering */ ++ e_dbg("Initializing the IEEE VLAN\n"); ++ e1000e_clear_vfta(hw); ++ ++ /* Setup the receive address. */ ++ /* ++ * If, however, a locally administered address was assigned to the ++ * 82571, we must reserve a RAR for it to work around an issue where ++ * resetting one port will reload the MAC on the other port. ++ */ ++ if (e1000e_get_laa_state_82571(hw)) ++ rar_count--; ++ e1000e_init_rx_addrs(hw, rar_count); ++ ++ /* Zero out the Multicast HASH table */ ++ e_dbg("Zeroing the MTA\n"); ++ for (i = 0; i < mac->mta_reg_count; i++) ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); ++ ++ /* Setup link and flow control */ ++ ret_val = mac->ops.setup_link(hw); ++ ++ /* Set the transmit descriptor write-back policy */ ++ reg_data = er32(TXDCTL(0)); ++ reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB | ++ E1000_TXDCTL_COUNT_DESC; ++ ew32(TXDCTL(0), reg_data); ++ ++ /* ...for both queues. */ ++ switch (mac->type) { ++ case e1000_82574: ++ case e1000_82583: ++ case e1000_82573: ++ e1000e_enable_tx_pkt_filtering(hw); ++ reg_data = er32(GCR); ++ reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; ++ ew32(GCR, reg_data); ++ break; ++ default: ++ reg_data = er32(TXDCTL(1)); ++ reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB | ++ E1000_TXDCTL_COUNT_DESC; ++ ew32(TXDCTL(1), reg_data); ++ break; ++ } ++ ++ /* ++ * Clear all of the statistics registers (clear on read). It is ++ * important that we do this after we have tried to establish link ++ * because the symbol error count will increment wildly if there ++ * is no link. ++ */ ++ e1000_clear_hw_cntrs_82571(hw); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits ++ * @hw: pointer to the HW structure ++ * ++ * Initializes required hardware-dependent bits needed for normal operation. ++ **/ ++static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) ++{ ++ u32 reg; ++ ++ /* Transmit Descriptor Control 0 */ ++ reg = er32(TXDCTL(0)); ++ reg |= (1 << 22); ++ ew32(TXDCTL(0), reg); ++ ++ /* Transmit Descriptor Control 1 */ ++ reg = er32(TXDCTL(1)); ++ reg |= (1 << 22); ++ ew32(TXDCTL(1), reg); ++ ++ /* Transmit Arbitration Control 0 */ ++ reg = er32(TARC(0)); ++ reg &= ~(0xF << 27); /* 30:27 */ ++ switch (hw->mac.type) { ++ case e1000_82571: ++ case e1000_82572: ++ reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); ++ break; ++ default: ++ break; ++ } ++ ew32(TARC(0), reg); ++ ++ /* Transmit Arbitration Control 1 */ ++ reg = er32(TARC(1)); ++ switch (hw->mac.type) { ++ case e1000_82571: ++ case e1000_82572: ++ reg &= ~((1 << 29) | (1 << 30)); ++ reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); ++ if (er32(TCTL) & E1000_TCTL_MULR) ++ reg &= ~(1 << 28); ++ else ++ reg |= (1 << 28); ++ ew32(TARC(1), reg); ++ break; ++ default: ++ break; ++ } ++ ++ /* Device Control */ ++ ++ switch (hw->mac.type) { ++ case e1000_82574: ++ case e1000_82583: ++ case e1000_82573: ++ reg = er32(CTRL); ++ reg &= ~(1 << 29); ++ ew32(CTRL, reg); ++ break; ++ default: ++ break; ++ } ++ ++ /* Extended Device Control */ ++ switch (hw->mac.type) { ++ case e1000_82574: ++ case e1000_82583: ++ case e1000_82573: ++ reg = er32(CTRL_EXT); ++ reg &= ~(1 << 23); ++ reg |= (1 << 22); ++ ew32(CTRL_EXT, reg); ++ break; ++ default: ++ break; ++ } ++ ++ ++ if (hw->mac.type == e1000_82571) { ++ reg = er32(PBA_ECC); ++ reg |= E1000_PBA_ECC_CORR_EN; ++ ew32(PBA_ECC, reg); ++ } ++ ++ /* ++ * Workaround for hardware errata. ++ * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 ++ */ ++ ++ if ((hw->mac.type == e1000_82571) || ++ (hw->mac.type == e1000_82572)) { ++ reg = er32(CTRL_EXT); ++ reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; ++ ew32(CTRL_EXT, reg); ++ } ++ ++ /* PCI-Ex Control Registers */ ++ ++ switch (hw->mac.type) { ++ case e1000_82574: ++ case e1000_82583: ++ reg = er32(GCR); ++ reg |= (1 << 22); ++ ew32(GCR, reg); ++ /* ++ * Workaround for hardware errata. ++ * apply workaround for hardware errata documented in errata ++ * docs Fixes issue where some error prone or unreliable PCIe ++ * completions are occurring, particularly with ASPM enabled. ++ * Without fix, issue can cause tx timeouts. ++ */ ++ reg = er32(GCR2); ++ reg |= 1; ++ ew32(GCR2, reg); ++ break; ++ default: ++ break; ++ } ++ ++ return; ++} ++ ++/** ++ * e1000_clear_vfta_82571 - Clear VLAN filter table ++ * @hw: pointer to the HW structure ++ * ++ * Clears the register array which contains the VLAN filter table by ++ * setting all the values to 0. ++ **/ ++static void e1000_clear_vfta_82571(struct e1000_hw *hw) ++{ ++ u32 offset; ++ u32 vfta_value = 0; ++ u32 vfta_offset = 0; ++ u32 vfta_bit_in_reg = 0; ++ ++ switch (hw->mac.type) { ++ case e1000_82574: ++ case e1000_82583: ++ case e1000_82573: ++ if (hw->mng_cookie.vlan_id != 0) { ++ /* ++ *The VFTA is a 4096b bit-field, each identifying ++ *a single VLAN ID. The following operations ++ *determine which 32b entry (i.e. offset) into the ++ *array we want to set the VLAN ID (i.e. bit) of ++ *the manageability unit. ++ */ ++ vfta_offset = (hw->mng_cookie.vlan_id >> ++ E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; ++ vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & ++ E1000_VFTA_ENTRY_BIT_SHIFT_MASK); ++ } ++ ++ for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { ++ /* ++ *If the offset we want to clear is the same offset of ++ *the manageability VLAN ID, then clear all bits except ++ *that of the manageability unit ++ */ ++ vfta_value = (offset == vfta_offset) ? ++ vfta_bit_in_reg : 0; ++ E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, ++ vfta_value); ++ e1e_flush(); ++ } ++ break; ++ default: ++ break; ++ } ++} ++ ++/** ++ * e1000_check_mng_mode_82574 - Check manageability is enabled ++ * @hw: pointer to the HW structure ++ * ++ * Reads the NVM Initialization Control Word 2 and returns true ++ * (>0) if any manageability is enabled, else false (0). ++ **/ ++static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) ++{ ++ u16 data; ++ ++ e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); ++ return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; ++} ++ ++/** ++ * e1000_led_on_82574 - Turn LED on ++ * @hw: pointer to the HW structure ++ * ++ * Turn LED on. ++ **/ ++static s32 e1000_led_on_82574(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ u32 i; ++ ++ ctrl = hw->mac.ledctl_mode2; ++ if (!(E1000_STATUS_LU & er32(STATUS))) { ++ /* ++ * If no link, then turn LED on by setting the invert bit ++ * for each LED that's "on" (0x0E) in ledctl_mode2. ++ */ ++ for (i = 0; i < 4; i++) ++ if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == ++ E1000_LEDCTL_MODE_LED_ON) ++ ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); ++ } ++ ew32(LEDCTL, ctrl); ++ ++ return E1000_SUCCESS; ++} ++ ++ ++/** ++ * e1000_setup_link_82571 - Setup flow control and link settings ++ * @hw: pointer to the HW structure ++ * ++ * Determines which flow control settings to use, then configures flow ++ * control. Calls the appropriate media-specific link configuration ++ * function. Assuming the adapter has a valid link partner, a valid link ++ * should be established. Assumes the hardware has previously been reset ++ * and the transmitter and receiver are not enabled. ++ **/ ++static s32 e1000_setup_link_82571(struct e1000_hw *hw) ++{ ++ /* ++ * 82573 does not have a word in the NVM to determine ++ * the default flow control setting, so we explicitly ++ * set it to full. ++ */ ++ switch (hw->mac.type) { ++ case e1000_82574: ++ case e1000_82583: ++ case e1000_82573: ++ if (hw->fc.requested_mode == e1000_fc_default) ++ hw->fc.requested_mode = e1000_fc_full; ++ break; ++ default: ++ break; ++ } ++ return e1000e_setup_link(hw); ++} ++ ++/** ++ * e1000_setup_copper_link_82571 - Configure copper link settings ++ * @hw: pointer to the HW structure ++ * ++ * Configures the link for auto-neg or forced speed and duplex. Then we check ++ * for link, once link is established calls to configure collision distance ++ * and flow control are called. ++ **/ ++static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val; ++ ++ ctrl = er32(CTRL); ++ ctrl |= E1000_CTRL_SLU; ++ ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ ew32(CTRL, ctrl); ++ ++ switch (hw->phy.type) { ++ case e1000_phy_m88: ++ case e1000_phy_bm: ++ ret_val = e1000e_copper_link_setup_m88(hw); ++ break; ++ case e1000_phy_igp_2: ++ ret_val = e1000e_copper_link_setup_igp(hw); ++ break; ++ default: ++ ret_val = -E1000_ERR_PHY; ++ break; ++ } ++ ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000e_setup_copper_link(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes ++ * @hw: pointer to the HW structure ++ * ++ * Configures collision distance and flow control for fiber and serdes links. ++ * Upon successful setup, poll for link. ++ **/ ++static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) ++{ ++ switch (hw->mac.type) { ++ case e1000_82571: ++ case e1000_82572: ++ /* ++ * If SerDes loopback mode is entered, there is no form ++ * of reset to take the adapter out of that mode. So we ++ * have to explicitly take the adapter out of loopback ++ * mode. This prevents drivers from twiddling their thumbs ++ * if another tool failed to take it out of loopback mode. ++ */ ++ ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); ++ break; ++ default: ++ break; ++ } ++ ++ return e1000e_setup_fiber_serdes_link(hw); ++} ++ ++/** ++ * e1000_check_for_serdes_link_82571 - Check for link (Serdes) ++ * @hw: pointer to the HW structure ++ * ++ * Reports the link state as up or down. ++ * ++ * If autonegotiation is supported by the link partner, the link state is ++ * determined by the result of autongotiation. This is the most likely case. ++ * If autonegotiation is not supported by the link partner, and the link ++ * has a valid signal, force the link up. ++ * ++ * The link state is represented internally here by 4 states: ++ * ++ * 1) down ++ * 2) autoneg_progress ++ * 3) autoneg_complete (the link sucessfully autonegotiated) ++ * 4) forced_up (the link has been forced up, it did not autonegotiate) ++ * ++ **/ ++s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 rxcw; ++ u32 ctrl; ++ u32 status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ctrl = er32(CTRL); ++ status = er32(STATUS); ++ rxcw = er32(RXCW); ++ ++ if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { ++ ++ /* Receiver is synchronized with no invalid bits. */ ++ switch (mac->serdes_link_state) { ++ case e1000_serdes_link_autoneg_complete: ++ if (!(status & E1000_STATUS_LU)) { ++ /* ++ * We have lost link, retry autoneg before ++ * reporting link failure ++ */ ++ mac->serdes_link_state = ++ e1000_serdes_link_autoneg_progress; ++ mac->serdes_has_link = false; ++ e_dbg("AN_UP -> AN_PROG\n"); ++ } ++ break; ++ ++ case e1000_serdes_link_forced_up: ++ /* ++ * If we are receiving /C/ ordered sets, re-enable ++ * auto-negotiation in the TXCW register and disable ++ * forced link in the Device Control register in an ++ * attempt to auto-negotiate with our link partner. ++ */ ++ if (rxcw & E1000_RXCW_C) { ++ /* Enable autoneg, and unforce link up */ ++ ew32(TXCW, mac->txcw); ++ ew32(CTRL, ++ (ctrl & ~E1000_CTRL_SLU)); ++ mac->serdes_link_state = ++ e1000_serdes_link_autoneg_progress; ++ mac->serdes_has_link = false; ++ e_dbg("FORCED_UP -> AN_PROG\n"); ++ } ++ break; ++ ++ case e1000_serdes_link_autoneg_progress: ++ if (rxcw & E1000_RXCW_C) { ++ /* We received /C/ ordered sets, meaning the ++ * link partner has autonegotiated, and we can ++ * trust the Link Up (LU) status bit ++ */ ++ if (status & E1000_STATUS_LU) { ++ mac->serdes_link_state = ++ e1000_serdes_link_autoneg_complete; ++ e_dbg("AN_PROG -> AN_UP\n"); ++ mac->serdes_has_link = true; ++ } else { ++ /* Autoneg completed, but failed */ ++ mac->serdes_link_state = ++ e1000_serdes_link_down; ++ e_dbg("AN_PROG -> DOWN\n"); ++ } ++ } else { ++ /* The link partner did not autoneg. ++ * Force link up and full duplex, and change ++ * state to forced. ++ */ ++ ew32(TXCW, ++ (mac->txcw & ~E1000_TXCW_ANE)); ++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); ++ ew32(CTRL, ctrl); ++ ++ /* Configure Flow Control after link up. */ ++ ret_val = ++ e1000e_config_fc_after_link_up(hw); ++ if (ret_val) { ++ e_dbg("Error config flow control\n"); ++ break; ++ } ++ mac->serdes_link_state = ++ e1000_serdes_link_forced_up; ++ mac->serdes_has_link = true; ++ e_dbg("AN_PROG -> FORCED_UP\n"); ++ } ++ break; ++ ++ case e1000_serdes_link_down: ++ default: ++ /* The link was down but the receiver has now gained ++ * valid sync, so lets see if we can bring the link ++ * up. */ ++ ew32(TXCW, mac->txcw); ++ ew32(CTRL, ++ (ctrl & ~E1000_CTRL_SLU)); ++ mac->serdes_link_state = ++ e1000_serdes_link_autoneg_progress; ++ e_dbg("DOWN -> AN_PROG\n"); ++ break; ++ } ++ } else { ++ if (!(rxcw & E1000_RXCW_SYNCH)) { ++ mac->serdes_has_link = false; ++ mac->serdes_link_state = e1000_serdes_link_down; ++ e_dbg("ANYSTATE -> DOWN\n"); ++ } else { ++ /* ++ * We have sync, and can tolerate one ++ * invalid (IV) codeword before declaring ++ * link down, so reread to look again ++ */ ++ udelay(10); ++ rxcw = er32(RXCW); ++ if (rxcw & E1000_RXCW_IV) { ++ mac->serdes_link_state = e1000_serdes_link_down; ++ mac->serdes_has_link = false; ++ e_dbg("ANYSTATE -> DOWN\n"); ++ } ++ } ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_valid_led_default_82571 - Verify a valid default LED config ++ * @hw: pointer to the HW structure ++ * @data: pointer to the NVM (EEPROM) ++ * ++ * Read the EEPROM for the current default LED configuration. If the ++ * LED configuration is not valid, set to a valid LED configuration. ++ **/ ++static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) ++{ ++ s32 ret_val; ++ ++ ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); ++ if (ret_val) { ++ e_dbg("NVM Read Error\n"); ++ goto out; ++ } ++ ++ switch (hw->mac.type) { ++ case e1000_82574: ++ case e1000_82583: ++ case e1000_82573: ++ if(*data == ID_LED_RESERVED_F746) ++ *data = ID_LED_DEFAULT_82573; ++ break; ++ default: ++ if (*data == ID_LED_RESERVED_0000 || ++ *data == ID_LED_RESERVED_FFFF) ++ *data = ID_LED_DEFAULT; ++ break; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_get_laa_state_82571 - Get locally administered address state ++ * @hw: pointer to the HW structure ++ * ++ * Retrieve and return the current locally administered address state. ++ **/ ++bool e1000e_get_laa_state_82571(struct e1000_hw *hw) ++{ ++ if (hw->mac.type != e1000_82571) ++ return false; ++ ++ return hw->dev_spec._82571.laa_is_present; ++} ++ ++/** ++ * e1000e_set_laa_state_82571 - Set locally administered address state ++ * @hw: pointer to the HW structure ++ * @state: enable/disable locally administered address ++ * ++ * Enable/Disable the current locally administered address state. ++ **/ ++void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) ++{ ++ if (hw->mac.type != e1000_82571) ++ return; ++ ++ hw->dev_spec._82571.laa_is_present = state; ++ ++ /* If workaround is activated... */ ++ if (state) ++ /* ++ * Hold a copy of the LAA in RAR[14] This is done so that ++ * between the time RAR[0] gets clobbered and the time it ++ * gets fixed, the actual LAA is in one of the RARs and no ++ * incoming packets directed to this port are dropped. ++ * Eventually the LAA will be in RAR[0] and RAR[14]. ++ */ ++ e1000e_rar_set(hw, hw->mac.addr, ++ hw->mac.rar_entry_count - 1); ++ return; ++} ++ ++/** ++ * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Verifies that the EEPROM has completed the update. After updating the ++ * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If ++ * the checksum fix is not implemented, we need to set the bit and update ++ * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, ++ * we need to return bad checksum. ++ **/ ++static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ s32 ret_val = E1000_SUCCESS; ++ u16 data; ++ ++ if (nvm->type != e1000_nvm_flash_hw) ++ goto out; ++ ++ /* ++ * Check bit 4 of word 10h. If it is 0, firmware is done updating ++ * 10h-12h. Checksum may need to be fixed. ++ */ ++ ret_val = e1000_read_nvm(hw, 0x10, 1, &data); ++ if (ret_val) ++ goto out; ++ ++ if (!(data & 0x10)) { ++ /* ++ * Read 0x23 and check bit 15. This bit is a 1 ++ * when the checksum has already been fixed. If ++ * the checksum is still wrong and this bit is a ++ * 1, we need to return bad checksum. Otherwise, ++ * we need to set this bit to a 1 and update the ++ * checksum. ++ */ ++ ret_val = e1000_read_nvm(hw, 0x23, 1, &data); ++ if (ret_val) ++ goto out; ++ ++ if (!(data & 0x8000)) { ++ data |= 0x8000; ++ ret_val = e1000_write_nvm(hw, 0x23, 1, &data); ++ if (ret_val) ++ goto out; ++ ret_val = e1000e_update_nvm_checksum(hw); ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++ ++/** ++ * e1000_read_mac_addr_82571 - Read device MAC address ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* ++ * If there's an alternate MAC address place it in RAR0 ++ * so that it will override the Si installed default perm ++ * address. ++ */ ++ ret_val = e1000_check_alt_mac_addr_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000e_read_mac_addr_generic(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_power_down_phy_copper_82571 - Remove link during PHY power down ++ * @hw: pointer to the HW structure ++ * ++ * In the case of a PHY power down to save power, or to turn off link during a ++ * driver unload, or wake on lan is not enabled, remove the link. ++ **/ ++static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ struct e1000_mac_info *mac = &hw->mac; ++ ++ if (!(phy->ops.check_reset_block)) ++ return; ++ ++ /* If the management interface is not enabled, then power down */ ++ if (!(mac->ops.check_mng_mode(hw) || e1000_check_reset_block(hw))) ++ e1000_power_down_phy_copper(hw); ++ ++ return; ++} ++ ++/** ++ * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters ++ * @hw: pointer to the HW structure ++ * ++ * Clears the hardware counters by reading the counter registers. ++ **/ ++static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) ++{ ++ e1000e_clear_hw_cntrs_base(hw); ++ ++ er32(PRC64); ++ er32(PRC127); ++ er32(PRC255); ++ er32(PRC511); ++ er32(PRC1023); ++ er32(PRC1522); ++ er32(PTC64); ++ er32(PTC127); ++ er32(PTC255); ++ er32(PTC511); ++ er32(PTC1023); ++ er32(PTC1522); ++ ++ er32(ALGNERRC); ++ er32(RXERRC); ++ er32(TNCRS); ++ er32(CEXTERR); ++ er32(TSCTC); ++ er32(TSCTFC); ++ ++ er32(MGTPRC); ++ er32(MGTPDC); ++ er32(MGTPTC); ++ ++ er32(IAC); ++ er32(ICRXOC); ++ ++ er32(ICRXPTC); ++ er32(ICRXATC); ++ er32(ICTXPTC); ++ er32(ICTXATC); ++ er32(ICTXQEC); ++ er32(ICTXQMTC); ++ er32(ICRXDMTC); ++} +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_82571.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_82571.h Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,53 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_82571_H_ ++#define _E1000_82571_H_ ++ ++#define ID_LED_RESERVED_F746 0xF746 ++#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ ++ (ID_LED_OFF1_ON2 << 8) | \ ++ (ID_LED_DEF1_DEF2 << 4) | \ ++ (ID_LED_DEF1_DEF2)) ++ ++#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 ++ ++/* Intr Throttling - RW */ ++#define E1000_EITR_82574(_n) (0x000E8 + (0x4 * (_n))) ++ ++#define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */ ++#define E1000_EIAC_MASK_82574 0x01F00000 ++ ++#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ ++ ++#define E1000_RXCFGL 0x0B634 /* TimeSync Rx EtherType & Msg Type Reg - RW */ ++ ++bool e1000e_get_laa_state_82571(struct e1000_hw *hw); ++void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state); ++ ++#endif +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_defines.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_defines.h Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,1466 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_DEFINES_H_ ++#define _E1000_DEFINES_H_ ++ ++/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ ++#define REQ_TX_DESCRIPTOR_MULTIPLE 8 ++#define REQ_RX_DESCRIPTOR_MULTIPLE 8 ++ ++/* Definitions for power management and wakeup registers */ ++/* Wake Up Control */ ++#define E1000_WUC_APME 0x00000001 /* APM Enable */ ++#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ ++#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ ++#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ ++#define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */ ++#define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */ ++#define E1000_WUC_SPM 0x80000000 /* Enable SPM */ ++#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ ++ ++/* Wake Up Filter Control */ ++#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ ++#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ ++#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ ++#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ ++#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ ++#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ ++#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ ++#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ ++#define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */ ++#define E1000_WUFC_FLX0_PHY 0x00001000 /* Flexible Filter 0 Enable */ ++#define E1000_WUFC_FLX1_PHY 0x00002000 /* Flexible Filter 1 Enable */ ++#define E1000_WUFC_FLX2_PHY 0x00004000 /* Flexible Filter 2 Enable */ ++#define E1000_WUFC_FLX3_PHY 0x00008000 /* Flexible Filter 3 Enable */ ++#define E1000_WUFC_FLX4_PHY 0x00000200 /* Flexible Filter 4 Enable */ ++#define E1000_WUFC_FLX5_PHY 0x00000400 /* Flexible Filter 5 Enable */ ++#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ ++#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ ++#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ ++#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ ++#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ ++#define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ ++#define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ ++#define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF /*Mask for all wakeup filters*/ ++#define E1000_WUFC_FLX_OFFSET_PHY 12 /* Offset to the Flexible Filters bits */ ++#define E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 /*Mask for 4 flexible filters*/ ++#define E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF /*Mask for 6 wakeup filters */ ++#define E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 /*Mask for 6 flexible filters*/ ++#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ ++#define E1000_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask for all 6 wakeup filters*/ ++#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ ++#define E1000_WUFC_FLX_FILTERS 0x000F0000 /*Mask for the 4 flexible filters */ ++#define E1000_WUFC_FLX_FILTERS_6 0x003F0000 /* Mask for 6 flexible filters */ ++ ++/* Wake Up Status */ ++#define E1000_WUS_LNKC E1000_WUFC_LNKC ++#define E1000_WUS_MAG E1000_WUFC_MAG ++#define E1000_WUS_EX E1000_WUFC_EX ++#define E1000_WUS_MC E1000_WUFC_MC ++#define E1000_WUS_BC E1000_WUFC_BC ++#define E1000_WUS_ARP E1000_WUFC_ARP ++#define E1000_WUS_IPV4 E1000_WUFC_IPV4 ++#define E1000_WUS_IPV6 E1000_WUFC_IPV6 ++#define E1000_WUS_FLX0_PHY E1000_WUFC_FLX0_PHY ++#define E1000_WUS_FLX1_PHY E1000_WUFC_FLX1_PHY ++#define E1000_WUS_FLX2_PHY E1000_WUFC_FLX2_PHY ++#define E1000_WUS_FLX3_PHY E1000_WUFC_FLX3_PHY ++#define E1000_WUS_FLX_FILTERS_PHY_4 E1000_WUFC_FLX_FILTERS_PHY_4 ++#define E1000_WUS_FLX0 E1000_WUFC_FLX0 ++#define E1000_WUS_FLX1 E1000_WUFC_FLX1 ++#define E1000_WUS_FLX2 E1000_WUFC_FLX2 ++#define E1000_WUS_FLX3 E1000_WUFC_FLX3 ++#define E1000_WUS_FLX4 E1000_WUFC_FLX4 ++#define E1000_WUS_FLX5 E1000_WUFC_FLX5 ++#define E1000_WUS_FLX4_PHY E1000_WUFC_FLX4_PHY ++#define E1000_WUS_FLX5_PHY E1000_WUFC_FLX5_PHY ++#define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS ++#define E1000_WUS_FLX_FILTERS_6 E1000_WUFC_FLX_FILTERS_6 ++#define E1000_WUS_FLX_FILTERS_PHY_6 E1000_WUFC_FLX_FILTERS_PHY_6 ++ ++/* Wake Up Packet Length */ ++#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ ++ ++/* Four Flexible Filters are supported */ ++#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 ++/* Six Flexible Filters are supported */ ++#define E1000_FLEXIBLE_FILTER_COUNT_MAX_6 6 ++ ++/* Each Flexible Filter is at most 128 (0x80) bytes in length */ ++#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 ++ ++#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX ++#define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6 ++#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX ++#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX ++ ++/* Extended Device Control */ ++#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ ++#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ ++#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN ++#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ ++#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ ++/* Reserved (bits 4,5) in >= 82575 */ ++#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */ ++#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */ ++#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA ++#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */ ++#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */ ++/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ ++#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ ++#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ ++#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ ++#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ ++#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ ++#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ ++#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ ++#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ ++#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ ++#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ ++#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 ++#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 ++#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 ++#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 ++#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 ++#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 ++#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 ++#define E1000_CTRL_EXT_EIAME 0x01000000 ++#define E1000_CTRL_EXT_IRCA 0x00000001 ++#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 ++#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 ++#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 ++#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 ++#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 ++#define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */ ++#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ ++/* IAME enable bit (27) was removed in >= 82575 */ ++#define E1000_CTRL_EXT_IAME 0x08000000 /* Int acknowledge Auto-mask */ ++#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error ++ * detection enabled */ ++#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity ++ * error detection enable */ ++#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 ++#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ ++#define E1000_CTRL_EXT_LSECCK 0x00001000 ++#define E1000_CTRL_EXT_PHYPDEN 0x00100000 ++#define E1000_I2CCMD_REG_ADDR_SHIFT 16 ++#define E1000_I2CCMD_REG_ADDR 0x00FF0000 ++#define E1000_I2CCMD_PHY_ADDR_SHIFT 24 ++#define E1000_I2CCMD_PHY_ADDR 0x07000000 ++#define E1000_I2CCMD_OPCODE_READ 0x08000000 ++#define E1000_I2CCMD_OPCODE_WRITE 0x00000000 ++#define E1000_I2CCMD_RESET 0x10000000 ++#define E1000_I2CCMD_READY 0x20000000 ++#define E1000_I2CCMD_INTERRUPT_ENA 0x40000000 ++#define E1000_I2CCMD_ERROR 0x80000000 ++#define E1000_MAX_SGMII_PHY_REG_ADDR 255 ++#define E1000_I2CCMD_PHY_TIMEOUT 200 ++ ++/* Receive Descriptor bit definitions */ ++#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ ++#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ ++#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ ++#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ ++#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ ++#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ ++#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ ++#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ ++#define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ ++#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ ++#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ ++#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ ++#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ ++#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ ++#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ ++#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ ++#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ ++#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ ++#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ ++#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ ++#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ ++#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ ++#define E1000_RXD_SPC_PRI_SHIFT 13 ++#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ ++#define E1000_RXD_SPC_CFI_SHIFT 12 ++ ++#define E1000_RXDEXT_STATERR_CE 0x01000000 ++#define E1000_RXDEXT_STATERR_SE 0x02000000 ++#define E1000_RXDEXT_STATERR_SEQ 0x04000000 ++#define E1000_RXDEXT_STATERR_CXE 0x10000000 ++#define E1000_RXDEXT_STATERR_TCPE 0x20000000 ++#define E1000_RXDEXT_STATERR_IPE 0x40000000 ++#define E1000_RXDEXT_STATERR_RXE 0x80000000 ++ ++#define E1000_RXDEXT_LSECH 0x01000000 ++#define E1000_RXDEXT_LSECE_MASK 0x60000000 ++#define E1000_RXDEXT_LSECE_NO_ERROR 0x00000000 ++#define E1000_RXDEXT_LSECE_NO_SA_MATCH 0x20000000 ++#define E1000_RXDEXT_LSECE_REPLAY_DETECT 0x40000000 ++#define E1000_RXDEXT_LSECE_BAD_SIG 0x60000000 ++ ++/* mask to determine if packets should be dropped due to frame errors */ ++#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ ++ E1000_RXD_ERR_CE | \ ++ E1000_RXD_ERR_SE | \ ++ E1000_RXD_ERR_SEQ | \ ++ E1000_RXD_ERR_CXE | \ ++ E1000_RXD_ERR_RXE) ++ ++/* Same mask, but for extended and packet split descriptors */ ++#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ ++ E1000_RXDEXT_STATERR_CE | \ ++ E1000_RXDEXT_STATERR_SE | \ ++ E1000_RXDEXT_STATERR_SEQ | \ ++ E1000_RXDEXT_STATERR_CXE | \ ++ E1000_RXDEXT_STATERR_RXE) ++ ++#define E1000_MRQC_ENABLE_MASK 0x00000007 ++#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 ++#define E1000_MRQC_ENABLE_RSS_INT 0x00000004 ++#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 ++#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 ++#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 ++#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 ++#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 ++#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 ++#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 ++ ++#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 ++#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF ++ ++/* Management Control */ ++#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ ++#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ ++#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ ++#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ ++#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ ++#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ ++#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ ++#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ ++#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ ++/* Enable Neighbor Discovery Filtering */ ++#define E1000_MANC_NEIGHBOR_EN 0x00004000 ++#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ ++#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ ++#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ ++#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ ++#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ ++#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ ++/* Enable MAC address filtering */ ++#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 ++/* Enable MNG packets to host memory */ ++#define E1000_MANC_EN_MNG2HOST 0x00200000 ++/* Enable IP address filtering */ ++#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 ++#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ ++#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ ++#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ ++#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ ++#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ ++#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ ++#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ ++#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ ++ ++#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ ++#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ ++ ++/* Receive Control */ ++#define E1000_RCTL_RST 0x00000001 /* Software reset */ ++#define E1000_RCTL_EN 0x00000002 /* enable */ ++#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ ++#define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ ++#define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ ++#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ ++#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ ++#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ ++#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ ++#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ ++#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ ++#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ ++#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min thresh size */ ++#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min thresh size */ ++#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min thresh size */ ++#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ ++#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ ++#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ ++#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ ++#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ ++#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ ++#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ ++/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ ++#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ ++#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ ++#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ ++#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ ++/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ ++#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ ++#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ ++#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ ++#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ ++#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ ++#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ ++#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ ++#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ ++#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ ++#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ ++#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ ++#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ ++ ++/* ++ * Use byte values for the following shift parameters ++ * Usage: ++ * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & ++ * E1000_PSRCTL_BSIZE0_MASK) | ++ * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & ++ * E1000_PSRCTL_BSIZE1_MASK) | ++ * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & ++ * E1000_PSRCTL_BSIZE2_MASK) | ++ * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; ++ * E1000_PSRCTL_BSIZE3_MASK)) ++ * where value0 = [128..16256], default=256 ++ * value1 = [1024..64512], default=4096 ++ * value2 = [0..64512], default=4096 ++ * value3 = [0..64512], default=0 ++ */ ++ ++#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F ++#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 ++#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 ++#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 ++ ++#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ ++#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ ++#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ ++#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ ++ ++/* SWFW_SYNC Definitions */ ++#define E1000_SWFW_EEP_SM 0x01 ++#define E1000_SWFW_PHY0_SM 0x02 ++#define E1000_SWFW_PHY1_SM 0x04 ++#define E1000_SWFW_CSR_SM 0x08 ++ ++/* FACTPS Definitions */ ++#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */ ++/* Device Control */ ++#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ ++#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ ++#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ ++#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ ++#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ ++#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ ++#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ ++#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ ++#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ ++#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ ++#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ ++#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ ++#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ ++#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ ++#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ ++#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ ++#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ ++#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ ++#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock ++ * indication in SDP[0] */ ++#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through ++ * PHYRST_N pin */ ++#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external ++ * LINK_0 and LINK_1 pins */ ++#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ ++#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ ++#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ ++#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ ++#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ ++#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ ++#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ ++#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ ++#define E1000_CTRL_RST 0x04000000 /* Global reset */ ++#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ ++#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ ++#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ ++#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ ++#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ ++#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */ ++#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ ++ ++/* ++ * Bit definitions for the Management Data IO (MDIO) and Management Data ++ * Clock (MDC) pins in the Device Control Register. ++ */ ++#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 ++#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 ++#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 ++#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 ++#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 ++#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 ++#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR ++#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA ++ ++#define E1000_CONNSW_ENRGSRC 0x4 ++#define E1000_PCS_CFG_PCS_EN 8 ++#define E1000_PCS_LCTL_FLV_LINK_UP 1 ++#define E1000_PCS_LCTL_FSV_10 0 ++#define E1000_PCS_LCTL_FSV_100 2 ++#define E1000_PCS_LCTL_FSV_1000 4 ++#define E1000_PCS_LCTL_FDV_FULL 8 ++#define E1000_PCS_LCTL_FSD 0x10 ++#define E1000_PCS_LCTL_FORCE_LINK 0x20 ++#define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40 ++#define E1000_PCS_LCTL_FORCE_FCTRL 0x80 ++#define E1000_PCS_LCTL_AN_ENABLE 0x10000 ++#define E1000_PCS_LCTL_AN_RESTART 0x20000 ++#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 ++#define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 ++#define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 ++#define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 ++#define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000 ++#define E1000_PCS_LCTL_CRS_ON_NI 0x4000000 ++#define E1000_ENABLE_SERDES_LOOPBACK 0x0410 ++ ++#define E1000_PCS_LSTS_LINK_OK 1 ++#define E1000_PCS_LSTS_SPEED_10 0 ++#define E1000_PCS_LSTS_SPEED_100 2 ++#define E1000_PCS_LSTS_SPEED_1000 4 ++#define E1000_PCS_LSTS_DUPLEX_FULL 8 ++#define E1000_PCS_LSTS_SYNK_OK 0x10 ++#define E1000_PCS_LSTS_AN_COMPLETE 0x10000 ++#define E1000_PCS_LSTS_AN_PAGE_RX 0x20000 ++#define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000 ++#define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 ++#define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000 ++ ++/* Device Status */ ++#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ ++#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ ++#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ ++#define E1000_STATUS_FUNC_SHIFT 2 ++#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ ++#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ ++#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ ++#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ ++#define E1000_STATUS_SPEED_MASK 0x000000C0 ++#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ ++#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ ++#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ ++#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ ++#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ ++#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ ++#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. ++ * Clear on write '0'. */ ++#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ ++#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ ++#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ ++#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ ++#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ ++#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ ++#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ ++#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ ++#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ ++#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ ++#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution ++ * disabled */ ++#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ ++#define E1000_STATUS_FUSE_8 0x04000000 ++#define E1000_STATUS_FUSE_9 0x08000000 ++#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ ++#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ ++ ++/* Constants used to interpret the masked PCI-X bus speed. */ ++#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ ++#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ ++#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/ ++ ++#define SPEED_10 10 ++#define SPEED_100 100 ++#define SPEED_1000 1000 ++#define HALF_DUPLEX 1 ++#define FULL_DUPLEX 2 ++ ++#define PHY_FORCE_TIME 20 ++ ++#define ADVERTISE_10_HALF 0x0001 ++#define ADVERTISE_10_FULL 0x0002 ++#define ADVERTISE_100_HALF 0x0004 ++#define ADVERTISE_100_FULL 0x0008 ++#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ ++#define ADVERTISE_1000_FULL 0x0020 ++ ++/* 1000/H is not supported, nor spec-compliant. */ ++#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ++ ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ ++ ADVERTISE_1000_FULL) ++#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ++ ADVERTISE_100_HALF | ADVERTISE_100_FULL) ++#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) ++#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) ++#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ ++ ADVERTISE_1000_FULL) ++#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) ++ ++#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX ++ ++/* LED Control */ ++#define E1000_PHY_LED0_MODE_MASK 0x00000007 ++#define E1000_PHY_LED0_IVRT 0x00000008 ++#define E1000_PHY_LED0_BLINK 0x00000010 ++#define E1000_PHY_LED0_MASK 0x0000001F ++ ++#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F ++#define E1000_LEDCTL_LED0_MODE_SHIFT 0 ++#define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020 ++#define E1000_LEDCTL_LED0_IVRT 0x00000040 ++#define E1000_LEDCTL_LED0_BLINK 0x00000080 ++#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 ++#define E1000_LEDCTL_LED1_MODE_SHIFT 8 ++#define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000 ++#define E1000_LEDCTL_LED1_IVRT 0x00004000 ++#define E1000_LEDCTL_LED1_BLINK 0x00008000 ++#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 ++#define E1000_LEDCTL_LED2_MODE_SHIFT 16 ++#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 ++#define E1000_LEDCTL_LED2_IVRT 0x00400000 ++#define E1000_LEDCTL_LED2_BLINK 0x00800000 ++#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 ++#define E1000_LEDCTL_LED3_MODE_SHIFT 24 ++#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 ++#define E1000_LEDCTL_LED3_IVRT 0x40000000 ++#define E1000_LEDCTL_LED3_BLINK 0x80000000 ++ ++#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 ++#define E1000_LEDCTL_MODE_LINK_100_1000 0x1 ++#define E1000_LEDCTL_MODE_LINK_UP 0x2 ++#define E1000_LEDCTL_MODE_ACTIVITY 0x3 ++#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 ++#define E1000_LEDCTL_MODE_LINK_10 0x5 ++#define E1000_LEDCTL_MODE_LINK_100 0x6 ++#define E1000_LEDCTL_MODE_LINK_1000 0x7 ++#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 ++#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 ++#define E1000_LEDCTL_MODE_COLLISION 0xA ++#define E1000_LEDCTL_MODE_BUS_SPEED 0xB ++#define E1000_LEDCTL_MODE_BUS_SIZE 0xC ++#define E1000_LEDCTL_MODE_PAUSED 0xD ++#define E1000_LEDCTL_MODE_LED_ON 0xE ++#define E1000_LEDCTL_MODE_LED_OFF 0xF ++ ++/* Transmit Descriptor bit definitions */ ++#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ ++#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ ++#define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */ ++#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ ++#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ ++#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ ++#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ ++#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ ++#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ ++#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ ++#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ ++#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ ++#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ ++#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ ++#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ ++#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ ++#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ ++#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ ++#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ ++#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ ++#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ ++/* Extended desc bits for Linksec and timesync */ ++#define E1000_TXD_CMD_LINKSEC 0x10000000 /* Apply LinkSec on packet */ ++#define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ ++ ++/* Transmit Control */ ++#define E1000_TCTL_RST 0x00000001 /* software reset */ ++#define E1000_TCTL_EN 0x00000002 /* enable tx */ ++#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ ++#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ ++#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ ++#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ ++#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ ++#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ ++#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ ++#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ ++#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ ++ ++/* Transmit Arbitration Count */ ++#define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ ++ ++/* SerDes Control */ ++#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 ++ ++/* Receive Checksum Control */ ++#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ ++#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ ++#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ ++#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ ++#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ ++#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ ++#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ ++ ++/* Header split receive */ ++#define E1000_RFCTL_ISCSI_DIS 0x00000001 ++#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E ++#define E1000_RFCTL_ISCSI_DWC_SHIFT 1 ++#define E1000_RFCTL_NFSW_DIS 0x00000040 ++#define E1000_RFCTL_NFSR_DIS 0x00000080 ++#define E1000_RFCTL_NFS_VER_MASK 0x00000300 ++#define E1000_RFCTL_NFS_VER_SHIFT 8 ++#define E1000_RFCTL_IPV6_DIS 0x00000400 ++#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 ++#define E1000_RFCTL_ACK_DIS 0x00001000 ++#define E1000_RFCTL_ACKD_DIS 0x00002000 ++#define E1000_RFCTL_IPFRSP_DIS 0x00004000 ++#define E1000_RFCTL_EXTEN 0x00008000 ++#define E1000_RFCTL_IPV6_EX_DIS 0x00010000 ++#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 ++#define E1000_RFCTL_LEF 0x00040000 ++ ++/* Collision related configuration parameters */ ++#define E1000_COLLISION_THRESHOLD 15 ++#define E1000_CT_SHIFT 4 ++#define E1000_COLLISION_DISTANCE 63 ++#define E1000_COLD_SHIFT 12 ++ ++/* Default values for the transmit IPG register */ ++#define DEFAULT_82543_TIPG_IPGT_FIBER 9 ++#define DEFAULT_82543_TIPG_IPGT_COPPER 8 ++ ++#define E1000_TIPG_IPGT_MASK 0x000003FF ++#define E1000_TIPG_IPGR1_MASK 0x000FFC00 ++#define E1000_TIPG_IPGR2_MASK 0x3FF00000 ++ ++#define DEFAULT_82543_TIPG_IPGR1 8 ++#define E1000_TIPG_IPGR1_SHIFT 10 ++ ++#define DEFAULT_82543_TIPG_IPGR2 6 ++#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 ++#define E1000_TIPG_IPGR2_SHIFT 20 ++ ++/* Ethertype field values */ ++#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ ++ ++#define ETHERNET_FCS_SIZE 4 ++#define MAX_JUMBO_FRAME_SIZE 0x3F00 ++ ++/* Extended Configuration Control and Size */ ++#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 ++#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 ++#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 ++#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 ++#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 ++#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 ++#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 ++ ++#define E1000_PHY_CTRL_SPD_EN 0x00000001 ++#define E1000_PHY_CTRL_D0A_LPLU 0x00000002 ++#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 ++#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 ++#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 ++ ++#define E1000_KABGTXD_BGSQLBIAS 0x00050000 ++ ++/* PBA constants */ ++#define E1000_PBA_6K 0x0006 /* 6KB */ ++#define E1000_PBA_8K 0x0008 /* 8KB */ ++#define E1000_PBA_10K 0x000A /* 10KB */ ++#define E1000_PBA_12K 0x000C /* 12KB */ ++#define E1000_PBA_14K 0x000E /* 14KB */ ++#define E1000_PBA_16K 0x0010 /* 16KB */ ++#define E1000_PBA_18K 0x0012 ++#define E1000_PBA_20K 0x0014 ++#define E1000_PBA_22K 0x0016 ++#define E1000_PBA_24K 0x0018 ++#define E1000_PBA_26K 0x001A ++#define E1000_PBA_30K 0x001E ++#define E1000_PBA_32K 0x0020 ++#define E1000_PBA_34K 0x0022 ++#define E1000_PBA_35K 0x0023 ++#define E1000_PBA_38K 0x0026 ++#define E1000_PBA_40K 0x0028 ++#define E1000_PBA_48K 0x0030 /* 48KB */ ++#define E1000_PBA_64K 0x0040 /* 64KB */ ++ ++#define E1000_PBS_16K E1000_PBA_16K ++#define E1000_PBS_24K E1000_PBA_24K ++ ++#define IFS_MAX 80 ++#define IFS_MIN 40 ++#define IFS_RATIO 4 ++#define IFS_STEP 10 ++#define MIN_NUM_XMITS 1000 ++ ++/* SW Semaphore Register */ ++#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ ++#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ ++#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ ++#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ ++ ++#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ ++ ++/* Interrupt Cause Read */ ++#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ ++#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ ++#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ ++#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ ++#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ ++#define E1000_ICR_RXO 0x00000040 /* rx overrun */ ++#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ ++#define E1000_ICR_VMMB 0x00000100 /* VM MB event */ ++#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ ++#define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ ++#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ ++#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ ++#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ ++#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ ++#define E1000_ICR_TXD_LOW 0x00008000 ++#define E1000_ICR_SRPD 0x00010000 ++#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ ++#define E1000_ICR_MNG 0x00040000 /* Manageability event */ ++#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ ++#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver ++ * should claim the interrupt */ ++#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */ ++#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */ ++#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */ ++#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ ++#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */ ++#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */ ++#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ ++#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW ++ * bit in the FWSM */ ++#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates ++ * an interrupt */ ++#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ ++#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ ++#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ ++#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ ++#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ ++#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ ++#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ ++ ++/* PBA ECC Register */ ++#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ ++#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ ++#define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ ++#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ ++#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ ++ ++/* ++ * This defines the bits that are set in the Interrupt Mask ++ * Set/Read Register. Each bit is documented below: ++ * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) ++ * o RXSEQ = Receive Sequence Error ++ */ ++#define POLL_IMS_ENABLE_MASK ( \ ++ E1000_IMS_RXDMT0 | \ ++ E1000_IMS_RXSEQ) ++ ++/* ++ * This defines the bits that are set in the Interrupt Mask ++ * Set/Read Register. Each bit is documented below: ++ * o RXT0 = Receiver Timer Interrupt (ring 0) ++ * o TXDW = Transmit Descriptor Written Back ++ * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) ++ * o RXSEQ = Receive Sequence Error ++ * o LSC = Link Status Change ++ */ ++#define IMS_ENABLE_MASK ( \ ++ E1000_IMS_RXT0 | \ ++ E1000_IMS_TXDW | \ ++ E1000_IMS_RXDMT0 | \ ++ E1000_IMS_RXSEQ | \ ++ E1000_IMS_LSC) ++ ++/* Interrupt Mask Set */ ++#define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */ ++#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ ++#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ ++#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ ++#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ ++#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ ++#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ ++#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ ++#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ ++#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ ++#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ ++#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ ++#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ ++#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ ++#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW ++#define E1000_IMS_SRPD E1000_ICR_SRPD ++#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ ++#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ ++#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ ++#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO ++ * parity error */ ++#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO ++ * parity error */ ++#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer ++ * parity error */ ++#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity ++ * error */ ++#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO ++ * parity error */ ++#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO ++ * parity error */ ++#define E1000_IMS_DSW E1000_ICR_DSW ++#define E1000_IMS_PHYINT E1000_ICR_PHYINT ++#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ ++#define E1000_IMS_EPRST E1000_ICR_EPRST ++#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ ++#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ ++#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ ++#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ ++#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ ++ ++/* Interrupt Cause Set */ ++#define E1000_ICS_TXDW E1000_ICR_TXDW /* Tx desc written back */ ++#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ ++#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ ++#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ ++#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ ++#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ ++#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ ++#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ ++#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ ++#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ ++#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ ++#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ ++#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ ++#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW ++#define E1000_ICS_SRPD E1000_ICR_SRPD ++#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ ++#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ ++#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ ++#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO ++ * parity error */ ++#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO ++ * parity error */ ++#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer ++ * parity error */ ++#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity ++ * error */ ++#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO ++ * parity error */ ++#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO ++ * parity error */ ++#define E1000_ICS_DSW E1000_ICR_DSW ++#define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ ++#define E1000_ICS_PHYINT E1000_ICR_PHYINT ++#define E1000_ICS_EPRST E1000_ICR_EPRST ++ ++/* Transmit Descriptor Control */ ++#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ ++#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ ++#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ ++#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ ++#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ ++#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ ++#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ ++/* Enable the counting of descriptors still to be processed. */ ++#define E1000_TXDCTL_COUNT_DESC 0x00400000 ++ ++/* Flow Control Constants */ ++#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 ++#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 ++#define FLOW_CONTROL_TYPE 0x8808 ++ ++/* 802.1q VLAN Packet Size */ ++#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ ++#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ ++ ++/* Receive Address */ ++/* ++ * Number of high/low register pairs in the RAR. The RAR (Receive Address ++ * Registers) holds the directed and multicast addresses that we monitor. ++ * Technically, we have 16 spots. However, we reserve one of these spots ++ * (RAR[15]) for our directed address used by controllers with ++ * manageability enabled, allowing us room for 15 multicast addresses. ++ */ ++#define E1000_RAR_ENTRIES 15 ++#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ ++#define E1000_RAL_MAC_ADDR_LEN 4 ++#define E1000_RAH_MAC_ADDR_LEN 2 ++#define E1000_RAH_POOL_MASK 0x03FC0000 ++#define E1000_RAH_POOL_1 0x00040000 ++ ++/* Error Codes */ ++#define E1000_SUCCESS 0 ++#define E1000_ERR_NVM 1 ++#define E1000_ERR_PHY 2 ++#define E1000_ERR_CONFIG 3 ++#define E1000_ERR_PARAM 4 ++#define E1000_ERR_MAC_INIT 5 ++#define E1000_ERR_PHY_TYPE 6 ++#define E1000_ERR_RESET 9 ++#define E1000_ERR_MASTER_REQUESTS_PENDING 10 ++#define E1000_ERR_HOST_INTERFACE_COMMAND 11 ++#define E1000_BLK_PHY_RESET 12 ++#define E1000_ERR_SWFW_SYNC 13 ++#define E1000_NOT_IMPLEMENTED 14 ++#define E1000_ERR_MBX 15 ++ ++/* Loop limit on how long we wait for auto-negotiation to complete */ ++#define FIBER_LINK_UP_LIMIT 50 ++#define COPPER_LINK_UP_LIMIT 10 ++#define PHY_AUTO_NEG_LIMIT 45 ++#define PHY_FORCE_LIMIT 20 ++/* Number of 100 microseconds we wait for PCI Express master disable */ ++#define MASTER_DISABLE_TIMEOUT 800 ++/* Number of milliseconds we wait for PHY configuration done after MAC reset */ ++#define PHY_CFG_TIMEOUT 100 ++/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ ++#define MDIO_OWNERSHIP_TIMEOUT 10 ++/* Number of milliseconds for NVM auto read done after MAC reset. */ ++#define AUTO_READ_DONE_TIMEOUT 10 ++ ++/* Flow Control */ ++#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ ++#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ ++#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ ++#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ ++ ++/* Transmit Configuration Word */ ++#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ ++#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ ++#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ ++#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ ++#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ ++#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ ++#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ ++#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ ++#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ ++#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ ++ ++/* Receive Configuration Word */ ++#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ ++#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ ++#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ ++#define E1000_RXCW_CC 0x10000000 /* Receive config change */ ++#define E1000_RXCW_C 0x20000000 /* Receive config */ ++#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ ++#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ ++ ++ ++/* PCI Express Control */ ++#define E1000_GCR_RXD_NO_SNOOP 0x00000001 ++#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 ++#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 ++#define E1000_GCR_TXD_NO_SNOOP 0x00000008 ++#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 ++#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 ++#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 ++#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 ++#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 ++#define E1000_GCR_CAP_VER2 0x00040000 ++ ++#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ ++ E1000_GCR_RXDSCW_NO_SNOOP | \ ++ E1000_GCR_RXDSCR_NO_SNOOP | \ ++ E1000_GCR_TXD_NO_SNOOP | \ ++ E1000_GCR_TXDSCW_NO_SNOOP | \ ++ E1000_GCR_TXDSCR_NO_SNOOP) ++ ++/* PHY Control Register */ ++#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ ++#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ ++#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ ++#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ ++#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ ++#define MII_CR_POWER_DOWN 0x0800 /* Power down */ ++#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ ++#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ ++#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ ++#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ ++#define MII_CR_SPEED_1000 0x0040 ++#define MII_CR_SPEED_100 0x2000 ++#define MII_CR_SPEED_10 0x0000 ++ ++/* PHY Status Register */ ++#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ ++#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ ++#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ ++#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ ++#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ ++#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ ++#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ ++#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ ++#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ ++#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ ++#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ ++#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ ++#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ ++#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ ++#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ ++ ++/* Autoneg Advertisement Register */ ++#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ ++#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ ++#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ ++#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ ++#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ ++#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ ++#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ ++#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ ++#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ ++#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ ++ ++/* Link Partner Ability Register (Base Page) */ ++#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ ++#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ ++#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ ++#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ ++#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ ++#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ ++#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ ++#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ ++#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ ++#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ ++#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ ++ ++/* Autoneg Expansion Register */ ++#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ ++#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ ++#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ ++#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ ++#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ ++ ++/* 1000BASE-T Control Register */ ++#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ ++#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ ++#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ ++#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ ++ /* 0=DTE device */ ++#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ ++ /* 0=Configure PHY as Slave */ ++#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ ++ /* 0=Automatic Master/Slave config */ ++#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ ++#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ ++#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ ++#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ ++#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ ++ ++/* 1000BASE-T Status Register */ ++#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ ++#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ ++#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ ++#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ ++#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ ++#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ ++#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx is Master, 0=Slave */ ++#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ ++ ++#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 ++ ++/* PHY 1000 MII Register/Bit Definitions */ ++/* PHY Registers defined by IEEE */ ++#define PHY_CONTROL 0x00 /* Control Register */ ++#define PHY_STATUS 0x01 /* Status Register */ ++#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ ++#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ ++#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ ++#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ ++#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ ++#define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ ++#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ ++#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ ++#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ ++#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ ++ ++#define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ ++ ++/* NVM Control */ ++#define E1000_EECD_SK 0x00000001 /* NVM Clock */ ++#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ ++#define E1000_EECD_DI 0x00000004 /* NVM Data In */ ++#define E1000_EECD_DO 0x00000008 /* NVM Data Out */ ++#define E1000_EECD_FWE_MASK 0x00000030 ++#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ ++#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ ++#define E1000_EECD_FWE_SHIFT 4 ++#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ ++#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ ++#define E1000_EECD_PRES 0x00000100 /* NVM Present */ ++#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ ++/* NVM Addressing bits based on type 0=small, 1=large */ ++#define E1000_EECD_ADDR_BITS 0x00000400 ++#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ ++#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ ++#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ ++#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ ++#define E1000_EECD_SIZE_EX_SHIFT 11 ++#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ ++#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ ++#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ ++#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ ++#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ ++#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ ++#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ ++#define E1000_EECD_SECVAL_SHIFT 22 ++#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) ++ ++#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */ ++#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */ ++#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ ++#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ ++#define E1000_NVM_RW_REG_START 1 /* Start operation */ ++#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ ++#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ ++#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ ++#define E1000_FLASH_UPDATES 2000 ++ ++/* NVM Word Offsets */ ++#define NVM_COMPAT 0x0003 ++#define NVM_ID_LED_SETTINGS 0x0004 ++#define NVM_VERSION 0x0005 ++#define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ ++#define NVM_PHY_CLASS_WORD 0x0007 ++#define NVM_INIT_CONTROL1_REG 0x000A ++#define NVM_INIT_CONTROL2_REG 0x000F ++#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 ++#define NVM_INIT_CONTROL3_PORT_B 0x0014 ++#define NVM_INIT_3GIO_3 0x001A ++#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 ++#define NVM_INIT_CONTROL3_PORT_A 0x0024 ++#define NVM_CFG 0x0012 ++#define NVM_FLASH_VERSION 0x0032 ++#define NVM_ALT_MAC_ADDR_PTR 0x0037 ++#define NVM_CHECKSUM_REG 0x003F ++ ++#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ ++#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ ++ ++/* Mask bits for fields in Word 0x0f of the NVM */ ++#define NVM_WORD0F_PAUSE_MASK 0x3000 ++#define NVM_WORD0F_PAUSE 0x1000 ++#define NVM_WORD0F_ASM_DIR 0x2000 ++#define NVM_WORD0F_ANE 0x0800 ++#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 ++#define NVM_WORD0F_LPLU 0x0001 ++ ++/* Mask bits for fields in Word 0x1a of the NVM */ ++#define NVM_WORD1A_ASPM_MASK 0x000C ++ ++/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ ++#define NVM_SUM 0xBABA ++ ++#define NVM_MAC_ADDR_OFFSET 0 ++#define NVM_PBA_OFFSET_0 8 ++#define NVM_PBA_OFFSET_1 9 ++#define NVM_RESERVED_WORD 0xFFFF ++#define NVM_PHY_CLASS_A 0x8000 ++#define NVM_SERDES_AMPLITUDE_MASK 0x000F ++#define NVM_SIZE_MASK 0x1C00 ++#define NVM_SIZE_SHIFT 10 ++#define NVM_WORD_SIZE_BASE_SHIFT 6 ++#define NVM_SWDPIO_EXT_SHIFT 4 ++ ++/* NVM Commands - SPI */ ++#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ ++#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ ++#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ ++#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ ++#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ ++#define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */ ++#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ ++#define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */ ++ ++/* SPI NVM Status Register */ ++#define NVM_STATUS_RDY_SPI 0x01 ++#define NVM_STATUS_WEN_SPI 0x02 ++#define NVM_STATUS_BP0_SPI 0x04 ++#define NVM_STATUS_BP1_SPI 0x08 ++#define NVM_STATUS_WPEN_SPI 0x80 ++ ++/* Word definitions for ID LED Settings */ ++#define ID_LED_RESERVED_0000 0x0000 ++#define ID_LED_RESERVED_FFFF 0xFFFF ++#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ ++ (ID_LED_OFF1_OFF2 << 8) | \ ++ (ID_LED_DEF1_DEF2 << 4) | \ ++ (ID_LED_DEF1_DEF2)) ++#define ID_LED_DEF1_DEF2 0x1 ++#define ID_LED_DEF1_ON2 0x2 ++#define ID_LED_DEF1_OFF2 0x3 ++#define ID_LED_ON1_DEF2 0x4 ++#define ID_LED_ON1_ON2 0x5 ++#define ID_LED_ON1_OFF2 0x6 ++#define ID_LED_OFF1_DEF2 0x7 ++#define ID_LED_OFF1_ON2 0x8 ++#define ID_LED_OFF1_OFF2 0x9 ++ ++#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF ++#define IGP_ACTIVITY_LED_ENABLE 0x0300 ++#define IGP_LED3_MODE 0x07000000 ++ ++/* PCI/PCI-X/PCI-EX Config space */ ++#define PCI_HEADER_TYPE_REGISTER 0x0E ++#define PCIE_LINK_STATUS 0x12 ++#define PCIE_DEVICE_CONTROL2 0x28 ++ ++#define PCI_HEADER_TYPE_MULTIFUNC 0x80 ++#define PCIE_LINK_WIDTH_MASK 0x3F0 ++#define PCIE_LINK_WIDTH_SHIFT 4 ++#define PCIE_DEVICE_CONTROL2_16ms 0x0005 ++ ++#ifndef ETH_ADDR_LEN ++#define ETH_ADDR_LEN 6 ++#endif ++ ++#define PHY_REVISION_MASK 0xFFFFFFF0 ++#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ ++#define MAX_PHY_MULTI_PAGE_REG 0xF ++ ++/* Bit definitions for valid PHY IDs. */ ++/* ++ * I = Integrated ++ * E = External ++ */ ++#define M88E1000_E_PHY_ID 0x01410C50 ++#define M88E1000_I_PHY_ID 0x01410C30 ++#define M88E1011_I_PHY_ID 0x01410C20 ++#define IGP01E1000_I_PHY_ID 0x02A80380 ++#define M88E1011_I_REV_4 0x04 ++#define M88E1111_I_PHY_ID 0x01410CC0 ++#define GG82563_E_PHY_ID 0x01410CA0 ++#define IGP03E1000_E_PHY_ID 0x02A80390 ++#define IFE_E_PHY_ID 0x02A80330 ++#define IFE_PLUS_E_PHY_ID 0x02A80320 ++#define IFE_C_E_PHY_ID 0x02A80310 ++#define BME1000_E_PHY_ID 0x01410CB0 ++#define BME1000_E_PHY_ID_R2 0x01410CB1 ++#define I82577_E_PHY_ID 0x01540050 ++#define I82578_E_PHY_ID 0x004DD040 ++#define M88_VENDOR 0x0141 ++ ++/* M88E1000 Specific Registers */ ++#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ ++#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ ++#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ ++#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ ++#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ ++#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ ++ ++#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ ++#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ ++#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ ++#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ ++#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ ++ ++/* M88E1000 PHY Specific Control Register */ ++#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ ++#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ ++#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ ++/* 1=CLK125 low, 0=CLK125 toggling */ ++#define M88E1000_PSCR_CLK125_DISABLE 0x0010 ++#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ ++ /* Manual MDI configuration */ ++#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ ++/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ ++#define M88E1000_PSCR_AUTO_X_1000T 0x0040 ++/* Auto crossover enabled all speeds */ ++#define M88E1000_PSCR_AUTO_X_MODE 0x0060 ++/* ++ * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold ++ * 0=Normal 10BASE-T Rx Threshold ++ */ ++#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 ++/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ ++#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 ++#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ ++#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ ++#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ ++ ++/* M88E1000 PHY Specific Status Register */ ++#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ ++#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ ++#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ ++#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ ++/* ++ * 0 = <50M ++ * 1 = 50-80M ++ * 2 = 80-110M ++ * 3 = 110-140M ++ * 4 = >140M ++ */ ++#define M88E1000_PSSR_CABLE_LENGTH 0x0380 ++#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ ++#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ ++#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ ++#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ ++#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ ++#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ ++#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ ++#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ ++ ++#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 ++ ++/* M88E1000 Extended PHY Specific Control Register */ ++#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ ++/* ++ * 1 = Lost lock detect enabled. ++ * Will assert lost lock and bring ++ * link down if idle not seen ++ * within 1ms in 1000BASE-T ++ */ ++#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 ++/* ++ * Number of times we will attempt to autonegotiate before downshifting if we ++ * are the master ++ */ ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 ++/* ++ * Number of times we will attempt to autonegotiate before downshifting if we ++ * are the slave ++ */ ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 ++#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ ++#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ ++#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ ++ ++/* M88EC018 Rev 2 specific DownShift settings */ ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 ++ ++#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 ++#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C ++ ++/* BME1000 PHY Specific Control Register */ ++#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ ++ ++/* ++ * Bits... ++ * 15-5: page ++ * 4-0: register offset ++ */ ++#define GG82563_PAGE_SHIFT 5 ++#define GG82563_REG(page, reg) \ ++ (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) ++#define GG82563_MIN_ALT_REG 30 ++ ++/* GG82563 Specific Registers */ ++#define GG82563_PHY_SPEC_CTRL \ ++ GG82563_REG(0, 16) /* PHY Specific Control */ ++#define GG82563_PHY_SPEC_STATUS \ ++ GG82563_REG(0, 17) /* PHY Specific Status */ ++#define GG82563_PHY_INT_ENABLE \ ++ GG82563_REG(0, 18) /* Interrupt Enable */ ++#define GG82563_PHY_SPEC_STATUS_2 \ ++ GG82563_REG(0, 19) /* PHY Specific Status 2 */ ++#define GG82563_PHY_RX_ERR_CNTR \ ++ GG82563_REG(0, 21) /* Receive Error Counter */ ++#define GG82563_PHY_PAGE_SELECT \ ++ GG82563_REG(0, 22) /* Page Select */ ++#define GG82563_PHY_SPEC_CTRL_2 \ ++ GG82563_REG(0, 26) /* PHY Specific Control 2 */ ++#define GG82563_PHY_PAGE_SELECT_ALT \ ++ GG82563_REG(0, 29) /* Alternate Page Select */ ++#define GG82563_PHY_TEST_CLK_CTRL \ ++ GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ ++ ++#define GG82563_PHY_MAC_SPEC_CTRL \ ++ GG82563_REG(2, 21) /* MAC Specific Control Register */ ++#define GG82563_PHY_MAC_SPEC_CTRL_2 \ ++ GG82563_REG(2, 26) /* MAC Specific Control 2 */ ++ ++#define GG82563_PHY_DSP_DISTANCE \ ++ GG82563_REG(5, 26) /* DSP Distance */ ++ ++/* Page 193 - Port Control Registers */ ++#define GG82563_PHY_KMRN_MODE_CTRL \ ++ GG82563_REG(193, 16) /* Kumeran Mode Control */ ++#define GG82563_PHY_PORT_RESET \ ++ GG82563_REG(193, 17) /* Port Reset */ ++#define GG82563_PHY_REVISION_ID \ ++ GG82563_REG(193, 18) /* Revision ID */ ++#define GG82563_PHY_DEVICE_ID \ ++ GG82563_REG(193, 19) /* Device ID */ ++#define GG82563_PHY_PWR_MGMT_CTRL \ ++ GG82563_REG(193, 20) /* Power Management Control */ ++#define GG82563_PHY_RATE_ADAPT_CTRL \ ++ GG82563_REG(193, 25) /* Rate Adaptation Control */ ++ ++/* Page 194 - KMRN Registers */ ++#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ ++ GG82563_REG(194, 16) /* FIFO's Control/Status */ ++#define GG82563_PHY_KMRN_CTRL \ ++ GG82563_REG(194, 17) /* Control */ ++#define GG82563_PHY_INBAND_CTRL \ ++ GG82563_REG(194, 18) /* Inband Control */ ++#define GG82563_PHY_KMRN_DIAGNOSTIC \ ++ GG82563_REG(194, 19) /* Diagnostic */ ++#define GG82563_PHY_ACK_TIMEOUTS \ ++ GG82563_REG(194, 20) /* Acknowledge Timeouts */ ++#define GG82563_PHY_ADV_ABILITY \ ++ GG82563_REG(194, 21) /* Advertised Ability */ ++#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ ++ GG82563_REG(194, 23) /* Link Partner Advertised Ability */ ++#define GG82563_PHY_ADV_NEXT_PAGE \ ++ GG82563_REG(194, 24) /* Advertised Next Page */ ++#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ ++ GG82563_REG(194, 25) /* Link Partner Advertised Next page */ ++#define GG82563_PHY_KMRN_MISC \ ++ GG82563_REG(194, 26) /* Misc. */ ++ ++/* MDI Control */ ++#define E1000_MDIC_DATA_MASK 0x0000FFFF ++#define E1000_MDIC_REG_MASK 0x001F0000 ++#define E1000_MDIC_REG_SHIFT 16 ++#define E1000_MDIC_PHY_MASK 0x03E00000 ++#define E1000_MDIC_PHY_SHIFT 21 ++#define E1000_MDIC_OP_WRITE 0x04000000 ++#define E1000_MDIC_OP_READ 0x08000000 ++#define E1000_MDIC_READY 0x10000000 ++#define E1000_MDIC_INT_EN 0x20000000 ++#define E1000_MDIC_ERROR 0x40000000 ++ ++/* SerDes Control */ ++#define E1000_GEN_CTL_READY 0x80000000 ++#define E1000_GEN_CTL_ADDRESS_SHIFT 8 ++#define E1000_GEN_POLL_TIMEOUT 640 ++ ++ ++ ++#endif /* _E1000_DEFINES_H_ */ +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_hw.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_hw.h Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,671 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_HW_H_ ++#define _E1000_HW_H_ ++ ++#include "e1000_osdep.h" ++#include "e1000_regs.h" ++#include "e1000_defines.h" ++ ++struct e1000_hw; ++ ++#define E1000_DEV_ID_82571EB_COPPER 0x105E ++#define E1000_DEV_ID_82571EB_FIBER 0x105F ++#define E1000_DEV_ID_82571EB_SERDES 0x1060 ++#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 ++#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA ++#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 ++#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 ++#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 ++#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC ++#define E1000_DEV_ID_82572EI_COPPER 0x107D ++#define E1000_DEV_ID_82572EI_FIBER 0x107E ++#define E1000_DEV_ID_82572EI_SERDES 0x107F ++#define E1000_DEV_ID_82572EI 0x10B9 ++#define E1000_DEV_ID_82573E 0x108B ++#define E1000_DEV_ID_82573E_IAMT 0x108C ++#define E1000_DEV_ID_82573L 0x109A ++#define E1000_DEV_ID_82574L 0x10D3 ++#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 ++#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 ++#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA ++#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB ++#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 ++#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A ++#define E1000_DEV_ID_ICH8_IGP_C 0x104B ++#define E1000_DEV_ID_ICH8_IFE 0x104C ++#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 ++#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 ++#define E1000_DEV_ID_ICH8_IGP_M 0x104D ++#define E1000_DEV_ID_ICH9_IGP_M 0x10BF ++#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 ++#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB ++#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD ++#define E1000_DEV_ID_ICH9_BM 0x10E5 ++#define E1000_DEV_ID_ICH9_IGP_C 0x294C ++#define E1000_DEV_ID_ICH9_IFE 0x10C0 ++#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 ++#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 ++#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC ++#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD ++#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE ++#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE ++#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF ++ ++#define E1000_REVISION_0 0 ++#define E1000_REVISION_1 1 ++#define E1000_REVISION_2 2 ++#define E1000_REVISION_3 3 ++#define E1000_REVISION_4 4 ++ ++#define E1000_FUNC_0 0 ++#define E1000_FUNC_1 1 ++ ++typedef enum { ++ e1000_undefined = 0, ++ e1000_82571, ++ e1000_82572, ++ e1000_82573, ++ e1000_82574, ++ e1000_80003es2lan, ++ e1000_ich8lan, ++ e1000_ich9lan, ++ e1000_ich10lan, ++ e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ ++} e1000_mac_type; ++ ++typedef enum { ++ e1000_media_type_unknown = 0, ++ e1000_media_type_copper = 1, ++ e1000_media_type_fiber = 2, ++ e1000_media_type_internal_serdes = 3, ++ e1000_num_media_types ++} e1000_media_type; ++ ++typedef enum { ++ e1000_nvm_unknown = 0, ++ e1000_nvm_none, ++ e1000_nvm_eeprom_spi, ++ e1000_nvm_eeprom_microwire, ++ e1000_nvm_flash_hw, ++ e1000_nvm_flash_sw ++} e1000_nvm_type; ++ ++typedef enum { ++ e1000_nvm_override_none = 0, ++ e1000_nvm_override_spi_small, ++ e1000_nvm_override_spi_large, ++ e1000_nvm_override_microwire_small, ++ e1000_nvm_override_microwire_large ++} e1000_nvm_override; ++ ++typedef enum { ++ e1000_phy_unknown = 0, ++ e1000_phy_none, ++ e1000_phy_m88, ++ e1000_phy_igp, ++ e1000_phy_igp_2, ++ e1000_phy_gg82563, ++ e1000_phy_igp_3, ++ e1000_phy_ife, ++ e1000_phy_bm, ++} e1000_phy_type; ++ ++typedef enum { ++ e1000_bus_type_unknown = 0, ++ e1000_bus_type_pci, ++ e1000_bus_type_pcix, ++ e1000_bus_type_pci_express, ++ e1000_bus_type_reserved ++} e1000_bus_type; ++ ++typedef enum { ++ e1000_bus_speed_unknown = 0, ++ e1000_bus_speed_33, ++ e1000_bus_speed_66, ++ e1000_bus_speed_100, ++ e1000_bus_speed_120, ++ e1000_bus_speed_133, ++ e1000_bus_speed_2500, ++ e1000_bus_speed_5000, ++ e1000_bus_speed_reserved ++} e1000_bus_speed; ++ ++typedef enum { ++ e1000_bus_width_unknown = 0, ++ e1000_bus_width_pcie_x1, ++ e1000_bus_width_pcie_x2, ++ e1000_bus_width_pcie_x4 = 4, ++ e1000_bus_width_pcie_x8 = 8, ++ e1000_bus_width_32, ++ e1000_bus_width_64, ++ e1000_bus_width_reserved ++} e1000_bus_width; ++ ++typedef enum { ++ e1000_1000t_rx_status_not_ok = 0, ++ e1000_1000t_rx_status_ok, ++ e1000_1000t_rx_status_undefined = 0xFF ++} e1000_1000t_rx_status; ++ ++typedef enum { ++ e1000_rev_polarity_normal = 0, ++ e1000_rev_polarity_reversed, ++ e1000_rev_polarity_undefined = 0xFF ++} e1000_rev_polarity; ++ ++typedef enum { ++ e1000_fc_none = 0, ++ e1000_fc_rx_pause, ++ e1000_fc_tx_pause, ++ e1000_fc_full, ++ e1000_fc_default = 0xFF ++} e1000_fc_type; ++ ++ ++/* Receive Descriptor */ ++struct e1000_rx_desc { ++ u64 buffer_addr; /* Address of the descriptor's data buffer */ ++ u16 length; /* Length of data DMAed into data buffer */ ++ u16 csum; /* Packet checksum */ ++ u8 status; /* Descriptor status */ ++ u8 errors; /* Descriptor Errors */ ++ u16 special; ++}; ++ ++/* Receive Descriptor - Extended */ ++union e1000_rx_desc_extended { ++ struct { ++ u64 buffer_addr; ++ u64 reserved; ++ } read; ++ struct { ++ struct { ++ u32 mrq; /* Multiple Rx Queues */ ++ union { ++ u32 rss; /* RSS Hash */ ++ struct { ++ u16 ip_id; /* IP id */ ++ u16 csum; /* Packet Checksum */ ++ } csum_ip; ++ } hi_dword; ++ } lower; ++ struct { ++ u32 status_error; /* ext status/error */ ++ u16 length; ++ u16 vlan; /* VLAN tag */ ++ } upper; ++ } wb; /* writeback */ ++}; ++ ++#define MAX_PS_BUFFERS 4 ++/* Receive Descriptor - Packet Split */ ++union e1000_rx_desc_packet_split { ++ struct { ++ /* one buffer for protocol header(s), three data buffers */ ++ u64 buffer_addr[MAX_PS_BUFFERS]; ++ } read; ++ struct { ++ struct { ++ u32 mrq; /* Multiple Rx Queues */ ++ union { ++ u32 rss; /* RSS Hash */ ++ struct { ++ u16 ip_id; /* IP id */ ++ u16 csum; /* Packet Checksum */ ++ } csum_ip; ++ } hi_dword; ++ } lower; ++ struct { ++ u32 status_error; /* ext status/error */ ++ u16 length0; /* length of buffer 0 */ ++ u16 vlan; /* VLAN tag */ ++ } middle; ++ struct { ++ u16 header_status; ++ u16 length[3]; /* length of buffers 1-3 */ ++ } upper; ++ u64 reserved; ++ } wb; /* writeback */ ++}; ++ ++/* Transmit Descriptor */ ++struct e1000_tx_desc { ++ u64 buffer_addr; /* Address of the descriptor's data buffer */ ++ union { ++ u32 data; ++ struct { ++ u16 length; /* Data buffer length */ ++ u8 cso; /* Checksum offset */ ++ u8 cmd; /* Descriptor control */ ++ } flags; ++ } lower; ++ union { ++ u32 data; ++ struct { ++ u8 status; /* Descriptor status */ ++ u8 css; /* Checksum start */ ++ u16 special; ++ } fields; ++ } upper; ++}; ++ ++/* Offload Context Descriptor */ ++struct e1000_context_desc { ++ union { ++ u32 ip_config; ++ struct { ++ u8 ipcss; /* IP checksum start */ ++ u8 ipcso; /* IP checksum offset */ ++ u16 ipcse; /* IP checksum end */ ++ } ip_fields; ++ } lower_setup; ++ union { ++ u32 tcp_config; ++ struct { ++ u8 tucss; /* TCP checksum start */ ++ u8 tucso; /* TCP checksum offset */ ++ u16 tucse; /* TCP checksum end */ ++ } tcp_fields; ++ } upper_setup; ++ u32 cmd_and_length; ++ union { ++ u32 data; ++ struct { ++ u8 status; /* Descriptor status */ ++ u8 hdr_len; /* Header length */ ++ u16 mss; /* Maximum segment size */ ++ } fields; ++ } tcp_seg_setup; ++}; ++ ++/* Offload data descriptor */ ++struct e1000_data_desc { ++ u64 buffer_addr; /* Address of the descriptor's buffer address */ ++ union { ++ u32 data; ++ struct { ++ u16 length; /* Data buffer length */ ++ u8 typ_len_ext; ++ u8 cmd; ++ } flags; ++ } lower; ++ union { ++ u32 data; ++ struct { ++ u8 status; /* Descriptor status */ ++ u8 popts; /* Packet Options */ ++ u16 special; ++ } fields; ++ } upper; ++}; ++ ++/* Statistics counters collected by the MAC */ ++struct e1000_hw_stats { ++ u64 crcerrs; ++ u64 algnerrc; ++ u64 symerrs; ++ u64 rxerrc; ++ u64 mpc; ++ u64 scc; ++ u64 ecol; ++ u64 mcc; ++ u64 latecol; ++ u64 colc; ++ u64 dc; ++ u64 tncrs; ++ u64 sec; ++ u64 cexterr; ++ u64 rlec; ++ u64 xonrxc; ++ u64 xontxc; ++ u64 xoffrxc; ++ u64 xofftxc; ++ u64 fcruc; ++ u64 prc64; ++ u64 prc127; ++ u64 prc255; ++ u64 prc511; ++ u64 prc1023; ++ u64 prc1522; ++ u64 gprc; ++ u64 bprc; ++ u64 mprc; ++ u64 gptc; ++ u64 gorc; ++ u64 gotc; ++ u64 rnbc; ++ u64 ruc; ++ u64 rfc; ++ u64 roc; ++ u64 rjc; ++ u64 mgprc; ++ u64 mgpdc; ++ u64 mgptc; ++ u64 tor; ++ u64 tot; ++ u64 tpr; ++ u64 tpt; ++ u64 ptc64; ++ u64 ptc127; ++ u64 ptc255; ++ u64 ptc511; ++ u64 ptc1023; ++ u64 ptc1522; ++ u64 mptc; ++ u64 bptc; ++ u64 tsctc; ++ u64 tsctfc; ++ u64 iac; ++ u64 icrxptc; ++ u64 icrxatc; ++ u64 ictxptc; ++ u64 ictxatc; ++ u64 ictxqec; ++ u64 ictxqmtc; ++ u64 icrxdmtc; ++ u64 icrxoc; ++ u64 cbtmpc; ++ u64 htdpmc; ++ u64 cbrdpc; ++ u64 cbrmpc; ++ u64 rpthc; ++ u64 hgptc; ++ u64 htcbdpc; ++ u64 hgorc; ++ u64 hgotc; ++ u64 lenerrs; ++ u64 scvpc; ++ u64 hrmpc; ++}; ++ ++struct e1000_phy_stats { ++ u32 idle_errors; ++ u32 receive_errors; ++}; ++ ++struct e1000_host_mng_dhcp_cookie { ++ u32 signature; ++ u8 status; ++ u8 reserved0; ++ u16 vlan_id; ++ u32 reserved1; ++ u16 reserved2; ++ u8 reserved3; ++ u8 checksum; ++}; ++ ++/* Host Interface "Rev 1" */ ++struct e1000_host_command_header { ++ u8 command_id; ++ u8 command_length; ++ u8 command_options; ++ u8 checksum; ++}; ++ ++#define E1000_HI_MAX_DATA_LENGTH 252 ++struct e1000_host_command_info { ++ struct e1000_host_command_header command_header; ++ u8 command_data[E1000_HI_MAX_DATA_LENGTH]; ++}; ++ ++/* Host Interface "Rev 2" */ ++struct e1000_host_mng_command_header { ++ u8 command_id; ++ u8 checksum; ++ u16 reserved1; ++ u16 reserved2; ++ u16 command_length; ++}; ++ ++#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 ++struct e1000_host_mng_command_info { ++ struct e1000_host_mng_command_header command_header; ++ u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; ++}; ++ ++#include "e1000_mac.h" ++#include "e1000_phy.h" ++#include "e1000_nvm.h" ++#include "e1000_manage.h" ++ ++struct e1000_mac_operations { ++ /* Function pointers for the MAC. */ ++ s32 (*init_params)(struct e1000_hw *); ++ s32 (*blink_led)(struct e1000_hw *); ++ s32 (*check_for_link)(struct e1000_hw *); ++ bool (*check_mng_mode)(struct e1000_hw *hw); ++ s32 (*cleanup_led)(struct e1000_hw *); ++ void (*clear_hw_cntrs)(struct e1000_hw *); ++ void (*clear_vfta)(struct e1000_hw *); ++ s32 (*get_bus_info)(struct e1000_hw *); ++ s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); ++ s32 (*led_on)(struct e1000_hw *); ++ s32 (*led_off)(struct e1000_hw *); ++ void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, ++ u32); ++ void (*remove_device)(struct e1000_hw *); ++ s32 (*reset_hw)(struct e1000_hw *); ++ s32 (*init_hw)(struct e1000_hw *); ++ s32 (*setup_link)(struct e1000_hw *); ++ s32 (*setup_physical_interface)(struct e1000_hw *); ++ s32 (*setup_led)(struct e1000_hw *); ++ void (*write_vfta)(struct e1000_hw *, u32, u32); ++ void (*mta_set)(struct e1000_hw *, u32); ++ void (*config_collision_dist)(struct e1000_hw*); ++ void (*rar_set)(struct e1000_hw*, u8*, u32); ++ s32 (*read_mac_addr)(struct e1000_hw*); ++ s32 (*validate_mdi_setting)(struct e1000_hw*); ++ s32 (*mng_host_if_write)(struct e1000_hw*, u8*, u16, u16, u8*); ++ s32 (*mng_write_cmd_header)(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header*); ++ s32 (*mng_enable_host_if)(struct e1000_hw*); ++ s32 (*wait_autoneg)(struct e1000_hw*); ++}; ++ ++struct e1000_phy_operations { ++ s32 (*init_params)(struct e1000_hw *); ++ s32 (*acquire)(struct e1000_hw *); ++ s32 (*cfg_on_link_up)(struct e1000_hw *); ++ s32 (*check_polarity)(struct e1000_hw *); ++ s32 (*check_reset_block)(struct e1000_hw *); ++ s32 (*commit)(struct e1000_hw *); ++ s32 (*force_speed_duplex)(struct e1000_hw *); ++ s32 (*get_cfg_done)(struct e1000_hw *hw); ++ s32 (*get_cable_length)(struct e1000_hw *); ++ s32 (*get_info)(struct e1000_hw *); ++ s32 (*read_reg)(struct e1000_hw *, u32, u16 *); ++ void (*release)(struct e1000_hw *); ++ s32 (*reset)(struct e1000_hw *); ++ s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); ++ s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); ++ s32 (*write_reg)(struct e1000_hw *, u32, u16); ++ void (*power_up)(struct e1000_hw *); ++ void (*power_down)(struct e1000_hw *); ++}; ++ ++struct e1000_nvm_operations { ++ s32 (*init_params)(struct e1000_hw *); ++ s32 (*acquire)(struct e1000_hw *); ++ s32 (*read)(struct e1000_hw *, u16, u16, u16 *); ++ void (*release)(struct e1000_hw *); ++ void (*reload)(struct e1000_hw *); ++ s32 (*update)(struct e1000_hw *); ++ s32 (*valid_led_default)(struct e1000_hw *, u16 *); ++ s32 (*validate)(struct e1000_hw *); ++ s32 (*write)(struct e1000_hw *, u16, u16, u16 *); ++}; ++ ++struct e1000_mac_info { ++ struct e1000_mac_operations ops; ++ u8 addr[6]; ++ u8 perm_addr[6]; ++ ++ e1000_mac_type type; ++ ++ u32 collision_delta; ++ u32 ledctl_default; ++ u32 ledctl_mode1; ++ u32 ledctl_mode2; ++ u32 mc_filter_type; ++ u32 tx_packet_delta; ++ u32 txcw; ++ ++ u16 current_ifs_val; ++ u16 ifs_max_val; ++ u16 ifs_min_val; ++ u16 ifs_ratio; ++ u16 ifs_step_size; ++ u16 mta_reg_count; ++ u16 rar_entry_count; ++ ++ u8 forced_speed_duplex; ++ ++ bool adaptive_ifs; ++ bool arc_subsystem_valid; ++ bool asf_firmware_present; ++ bool autoneg; ++ bool autoneg_failed; ++ bool disable_av; ++ bool disable_hw_init_bits; ++ bool get_link_status; ++ bool ifs_params_forced; ++ bool in_ifs_mode; ++ bool report_tx_early; ++ bool serdes_has_link; ++ bool tx_pkt_filtering; ++}; ++ ++struct e1000_phy_info { ++ struct e1000_phy_operations ops; ++ e1000_phy_type type; ++ ++ e1000_1000t_rx_status local_rx; ++ e1000_1000t_rx_status remote_rx; ++ e1000_ms_type ms_type; ++ e1000_ms_type original_ms_type; ++ e1000_rev_polarity cable_polarity; ++ e1000_smart_speed smart_speed; ++ ++ u32 addr; ++ u32 id; ++ u32 reset_delay_us; /* in usec */ ++ u32 revision; ++ ++ e1000_media_type media_type; ++ ++ u16 autoneg_advertised; ++ u16 autoneg_mask; ++ u16 cable_length; ++ u16 max_cable_length; ++ u16 min_cable_length; ++ ++ u8 mdix; ++ ++ bool disable_polarity_correction; ++ bool is_mdix; ++ bool polarity_correction; ++ bool reset_disable; ++ bool speed_downgraded; ++ bool autoneg_wait_to_complete; ++}; ++ ++struct e1000_nvm_info { ++ struct e1000_nvm_operations ops; ++ e1000_nvm_type type; ++ e1000_nvm_override override; ++ ++ u32 flash_bank_size; ++ u32 flash_base_addr; ++ u32 semaphore_delay; ++ ++ u16 word_size; ++ u16 delay_usec; ++ u16 address_bits; ++ u16 opcode_bits; ++ u16 page_size; ++}; ++ ++struct e1000_bus_info { ++ e1000_bus_type type; ++ e1000_bus_speed speed; ++ e1000_bus_width width; ++ ++ u32 snoop; ++ ++ u16 func; ++ u16 pci_cmd_word; ++}; ++ ++struct e1000_fc_info { ++ u32 high_water; /* Flow control high-water mark */ ++ u32 low_water; /* Flow control low-water mark */ ++ u16 pause_time; /* Flow control pause timer */ ++ bool send_xon; /* Flow control send XON */ ++ bool strict_ieee; /* Strict IEEE mode */ ++ e1000_fc_type type; /* Type of flow control */ ++ e1000_fc_type original_type; ++}; ++ ++struct e1000_hw { ++ void *back; ++ void *dev_spec; ++ ++ u8 __iomem *hw_addr; ++ u8 __iomem *flash_address; ++ unsigned long io_base; ++ ++ struct e1000_mac_info mac; ++ struct e1000_fc_info fc; ++ struct e1000_phy_info phy; ++ struct e1000_nvm_info nvm; ++ struct e1000_bus_info bus; ++ struct e1000_host_mng_dhcp_cookie mng_cookie; ++ ++ u32 dev_spec_size; ++ ++ u16 device_id; ++ u16 subsystem_vendor_id; ++ u16 subsystem_device_id; ++ u16 vendor_id; ++ ++ u8 revision_id; ++}; ++ ++#include "e1000_82571.h" ++#include "e1000_80003es2lan.h" ++#include "e1000_ich8lan.h" ++ ++/* These functions must be implemented by drivers */ ++s32 e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size); ++s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); ++void e1000_free_dev_spec_struct(struct e1000_hw *hw); ++void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); ++ ++#endif +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_ich8lan.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_ich8lan.c Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,3042 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * 82562G 10/100 Network Connection ++ * 82562G-2 10/100 Network Connection ++ * 82562GT 10/100 Network Connection ++ * 82562GT-2 10/100 Network Connection ++ * 82562V 10/100 Network Connection ++ * 82562V-2 10/100 Network Connection ++ * 82566DC-2 Gigabit Network Connection ++ * 82566DC Gigabit Network Connection ++ * 82566DM-2 Gigabit Network Connection ++ * 82566DM Gigabit Network Connection ++ * 82566MC Gigabit Network Connection ++ * 82566MM Gigabit Network Connection ++ * 82567LM Gigabit Network Connection ++ * 82567LF Gigabit Network Connection ++ * 82567V Gigabit Network Connection ++ * 82567LM-2 Gigabit Network Connection ++ * 82567LF-2 Gigabit Network Connection ++ * 82567V-2 Gigabit Network Connection ++ * 82567LF-3 Gigabit Network Connection ++ * 82567LM-3 Gigabit Network Connection ++ * 82567LM-4 Gigabit Network Connection ++ * 82577LM Gigabit Network Connection ++ * 82577LC Gigabit Network Connection ++ * 82578DM Gigabit Network Connection ++ * 82578DC Gigabit Network Connection ++ */ ++ ++#include "e1000.h" ++ ++static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); ++static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw); ++static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); ++static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); ++static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); ++static void e1000_release_swflag_ich8lan(struct e1000_hw *hw); ++static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); ++static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); ++static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); ++static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw); ++static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, ++ bool active); ++static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, ++ bool active); ++static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data); ++static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data); ++static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); ++static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); ++static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, ++ u16 *data); ++static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); ++static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); ++static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); ++static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); ++static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); ++static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); ++static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, ++ u16 *speed, u16 *duplex); ++static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); ++static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); ++static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); ++static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); ++static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); ++static s32 e1000_led_on_pchlan(struct e1000_hw *hw); ++static s32 e1000_led_off_pchlan(struct e1000_hw *hw); ++static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); ++static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); ++static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); ++static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); ++static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw); ++static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); ++static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); ++static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, ++ u32 offset, u8 *data); ++static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, ++ u8 size, u16 *data); ++static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, ++ u32 offset, u16 *data); ++static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, ++ u32 offset, u8 byte); ++static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, ++ u32 offset, u8 data); ++static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, ++ u8 size, u16 data); ++static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); ++static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); ++static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw); ++ ++/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ ++/* Offset 04h HSFSTS */ ++union ich8_hws_flash_status { ++ struct ich8_hsfsts { ++ u16 flcdone :1; /* bit 0 Flash Cycle Done */ ++ u16 flcerr :1; /* bit 1 Flash Cycle Error */ ++ u16 dael :1; /* bit 2 Direct Access error Log */ ++ u16 berasesz :2; /* bit 4:3 Sector Erase Size */ ++ u16 flcinprog :1; /* bit 5 flash cycle in Progress */ ++ u16 reserved1 :2; /* bit 13:6 Reserved */ ++ u16 reserved2 :6; /* bit 13:6 Reserved */ ++ u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ ++ u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ ++ } hsf_status; ++ u16 regval; ++}; ++ ++/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ ++/* Offset 06h FLCTL */ ++union ich8_hws_flash_ctrl { ++ struct ich8_hsflctl { ++ u16 flcgo :1; /* 0 Flash Cycle Go */ ++ u16 flcycle :2; /* 2:1 Flash Cycle */ ++ u16 reserved :5; /* 7:3 Reserved */ ++ u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ ++ u16 flockdn :6; /* 15:10 Reserved */ ++ } hsf_ctrl; ++ u16 regval; ++}; ++ ++/* ICH Flash Region Access Permissions */ ++union ich8_hws_flash_regacc { ++ struct ich8_flracc { ++ u32 grra :8; /* 0:7 GbE region Read Access */ ++ u32 grwa :8; /* 8:15 GbE region Write Access */ ++ u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ ++ u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ ++ } hsf_flregacc; ++ u16 regval; ++}; ++ ++/** ++ * e1000_init_phy_params_pchlan - Initialize PHY function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Initialize family-specific PHY parameters and function pointers. ++ **/ ++static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ ++ phy->addr = 1; ++ phy->reset_delay_us = 100; ++ ++ phy->ops.acquire = e1000_acquire_swflag_ich8lan; ++ phy->ops.check_polarity = e1000_check_polarity_ife; ++ phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; ++ phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; ++ phy->ops.get_cable_length = e1000e_get_cable_length_igp_2; ++ phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; ++ phy->ops.get_info = e1000_get_phy_info_ich8lan; ++ phy->ops.read_reg = e1000_read_phy_reg_hv; ++ phy->ops.release = e1000_release_swflag_ich8lan; ++ phy->ops.reset = e1000_phy_hw_reset_ich8lan; ++ phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; ++ phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; ++ phy->ops.write_reg = e1000_write_phy_reg_hv; ++ phy->ops.power_up = e1000_power_up_phy_copper; ++ phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; ++ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; ++ ++ phy->id = e1000_phy_unknown; ++ e1000e_get_phy_id(hw); ++ phy->type = e1000e_get_phy_type_from_id(phy->id); ++ ++ if (phy->type == e1000_phy_82577) { ++ phy->ops.check_polarity = e1000_check_polarity_82577; ++ phy->ops.force_speed_duplex = ++ e1000_phy_force_speed_duplex_82577; ++ phy->ops.get_cable_length = e1000_get_cable_length_82577; ++ phy->ops.get_info = e1000_get_phy_info_82577; ++ phy->ops.commit = e1000e_phy_sw_reset; ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_init_phy_params_ich8lan - Initialize PHY function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Initialize family-specific PHY parameters and function pointers. ++ **/ ++static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 i = 0; ++ ++ phy->addr = 1; ++ phy->reset_delay_us = 100; ++ ++ phy->ops.acquire = e1000_acquire_swflag_ich8lan; ++ phy->ops.check_polarity = e1000_check_polarity_ife; ++ phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; ++ phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; ++ phy->ops.get_cable_length = e1000e_get_cable_length_igp_2; ++ phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; ++ phy->ops.get_info = e1000_get_phy_info_ich8lan; ++ phy->ops.read_reg = e1000e_read_phy_reg_igp; ++ phy->ops.release = e1000_release_swflag_ich8lan; ++ phy->ops.reset = e1000_phy_hw_reset_ich8lan; ++ phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; ++ phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; ++ phy->ops.write_reg = e1000e_write_phy_reg_igp; ++ phy->ops.power_up = e1000_power_up_phy_copper; ++ phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; ++ ++ /* ++ * We may need to do this twice - once for IGP and if that fails, ++ * we'll set BM func pointers and try again ++ */ ++ ret_val = e1000e_determine_phy_address(hw); ++ if (ret_val) { ++ phy->ops.write_reg = e1000e_write_phy_reg_bm; ++ phy->ops.read_reg = e1000e_read_phy_reg_bm; ++ ret_val = e1000e_determine_phy_address(hw); ++ if (ret_val) { ++ e_dbg("Cannot determine PHY addr. Erroring out\n"); ++ goto out; ++ } ++ } ++ ++ phy->id = 0; ++ while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && ++ (i++ < 100)) { ++ msleep(1); ++ ret_val = e1000e_get_phy_id(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* Verify phy id */ ++ switch (phy->id) { ++ case IGP03E1000_E_PHY_ID: ++ phy->type = e1000_phy_igp_3; ++ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; ++ break; ++ case IFE_E_PHY_ID: ++ case IFE_PLUS_E_PHY_ID: ++ case IFE_C_E_PHY_ID: ++ phy->type = e1000_phy_ife; ++ phy->autoneg_mask = E1000_ALL_NOT_GIG; ++ break; ++ case BME1000_E_PHY_ID: ++ phy->type = e1000_phy_bm; ++ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; ++ phy->ops.read_reg = e1000e_read_phy_reg_bm; ++ phy->ops.write_reg = e1000e_write_phy_reg_bm; ++ phy->ops.commit = e1000e_phy_sw_reset; ++ break; ++ default: ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Initialize family-specific NVM parameters and function ++ * pointers. ++ **/ ++static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; ++ union ich8_hws_flash_status hsfsts; ++ u32 gfpreg, sector_base_addr, sector_end_addr; ++ s32 ret_val = E1000_SUCCESS; ++ u16 i; ++ ++ /* Can't read flash registers if the register set isn't mapped. */ ++ if (!hw->flash_address) { ++ e_dbg("ERROR: Flash registers not mapped\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ nvm->type = e1000_nvm_flash_sw; ++ ++ gfpreg = er32flash(ICH_FLASH_GFPREG); ++ ++ /* ++ * sector_X_addr is a "sector"-aligned address (4096 bytes) ++ * Add 1 to sector_end_addr since this sector is included in ++ * the overall size. ++ */ ++ sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; ++ sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; ++ ++ /* flash_base_addr is byte-aligned */ ++ nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; ++ ++ /* ++ * find total size of the NVM, then cut in half since the total ++ * size represents two separate NVM banks. ++ */ ++ nvm->flash_bank_size = (sector_end_addr - sector_base_addr) ++ << FLASH_SECTOR_ADDR_SHIFT; ++ nvm->flash_bank_size /= 2; ++ /* Adjust to word count */ ++ nvm->flash_bank_size /= sizeof(u16); ++ ++ /* ++ * Make sure the flash bank size does not overwrite the 4k ++ * sector ranges. We may have 64k allotted to us but we only care ++ * about the first 2 4k sectors. Therefore, if we have anything less ++ * than 64k set in the HSFSTS register, we will reduce the bank size ++ * down to 4k and let the rest remain unused. If berasesz == 3, then ++ * we are working in 64k mode. Otherwise we are not. ++ */ ++ if (nvm->flash_bank_size > E1000_ICH8_SHADOW_RAM_WORDS) { ++ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); ++ if (hsfsts.hsf_status.berasesz != 3) ++ nvm->flash_bank_size = E1000_ICH8_SHADOW_RAM_WORDS; ++ } ++ ++ nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; ++ ++ /* Clear shadow ram */ ++ for (i = 0; i < nvm->word_size; i++) { ++ dev_spec->shadow_ram[i].modified = false; ++ dev_spec->shadow_ram[i].value = 0xFFFF; ++ } ++ ++ /* Function Pointers */ ++ nvm->ops.acquire = e1000_acquire_swflag_ich8lan; ++ nvm->ops.read = e1000_read_nvm_ich8lan; ++ nvm->ops.release = e1000_release_swflag_ich8lan; ++ nvm->ops.update = e1000_update_nvm_checksum_ich8lan; ++ nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; ++ nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; ++ nvm->ops.write = e1000_write_nvm_ich8lan; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_mac_params_ich8lan - Initialize MAC function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Initialize family-specific MAC parameters and function ++ * pointers. ++ **/ ++static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ ++ /* Set media type function pointer */ ++ hw->phy.media_type = e1000_media_type_copper; ++ ++ /* Set mta register count */ ++ mac->mta_reg_count = 32; ++ /* Set rar entry count */ ++ mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; ++ if (mac->type == e1000_ich8lan) ++ mac->rar_entry_count--; ++ /* Set if part includes ASF firmware */ ++ mac->asf_firmware_present = true; ++ /* Set if manageability features are enabled. */ ++ mac->arc_subsystem_valid = true; ++ ++ /* Function pointers */ ++ ++ /* bus type/speed/width */ ++ mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; ++ /* function id */ ++ mac->ops.set_lan_id = e1000_set_lan_id_single_port; ++ /* reset */ ++ mac->ops.reset_hw = e1000_reset_hw_ich8lan; ++ /* hw initialization */ ++ mac->ops.init_hw = e1000_init_hw_ich8lan; ++ /* link setup */ ++ mac->ops.setup_link = e1000_setup_link_ich8lan; ++ /* physical interface setup */ ++ mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; ++ /* check for link */ ++ mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan; ++ /* check management mode */ ++ mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; ++ /* link info */ ++ mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; ++ /* multicast address update */ ++ mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic; ++ /* setting MTA */ ++ mac->ops.mta_set = e1000_mta_set_generic; ++ /* clear hardware counters */ ++ mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; ++ ++ /* LED operations */ ++ switch (mac->type) { ++ case e1000_ich8lan: ++ case e1000_ich9lan: ++ case e1000_ich10lan: ++ /* ID LED init */ ++ mac->ops.id_led_init = e1000e_id_led_init; ++ /* blink LED */ ++ mac->ops.blink_led = e1000e_blink_led; ++ /* setup LED */ ++ mac->ops.setup_led = e1000_setup_led_generic; ++ /* cleanup LED */ ++ mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; ++ /* turn on/off LED */ ++ mac->ops.led_on = e1000_led_on_ich8lan; ++ mac->ops.led_off = e1000_led_off_ich8lan; ++ break; ++ case e1000_pchlan: ++ /* ID LED init */ ++ mac->ops.id_led_init = e1000_id_led_init_pchlan; ++ /* setup LED */ ++ mac->ops.setup_led = e1000_setup_led_pchlan; ++ /* cleanup LED */ ++ mac->ops.cleanup_led = e1000_cleanup_led_pchlan; ++ /* turn on/off LED */ ++ mac->ops.led_on = e1000_led_on_pchlan; ++ mac->ops.led_off = e1000_led_off_pchlan; ++ break; ++ default: ++ break; ++ } ++ ++ /* Enable PCS Lock-loss workaround for ICH8 */ ++ if (mac->type == e1000_ich8lan) ++ e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); ++ ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_check_for_copper_link_ich8lan - Check for link (Copper) ++ * @hw: pointer to the HW structure ++ * ++ * Checks to see of the link status of the hardware has changed. If a ++ * change in link status has been detected, then we read the PHY registers ++ * to get the current speed/duplex if link exists. ++ **/ ++static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val; ++ bool link; ++ ++ /* ++ * We only want to go out to the PHY registers to see if Auto-Neg ++ * has completed and/or if our link status has changed. The ++ * get_link_status flag is set upon receiving a Link Status ++ * Change or Rx Sequence Error interrupt. ++ */ ++ if (!mac->get_link_status) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ if (hw->mac.type == e1000_pchlan) { ++ ret_val = e1000e_write_kmrn_reg(hw, ++ E1000_KMRNCTRLSTA_K1_CONFIG, ++ E1000_KMRNCTRLSTA_K1_ENABLE); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* ++ * First we want to see if the MII Status Register reports ++ * link. If so, then we want to get the current speed/duplex ++ * of the PHY. ++ */ ++ ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) ++ goto out; /* No link detected */ ++ ++ mac->get_link_status = false; ++ ++ if (hw->phy.type == e1000_phy_82578) { ++ ret_val = e1000_link_stall_workaround_hv(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* ++ * Check if there was DownShift, must be checked ++ * immediately after link-up ++ */ ++ e1000e_check_downshift(hw); ++ ++ /* ++ * If we are forcing speed/duplex, then we simply return since ++ * we have already determined whether we have link or not. ++ */ ++ if (!mac->autoneg) { ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ /* ++ * Auto-Neg is enabled. Auto Speed Detection takes care ++ * of MAC speed/duplex configuration. So we only need to ++ * configure Collision Distance in the MAC. ++ */ ++ e1000e_config_collision_dist(hw); ++ ++ /* ++ * Configure Flow Control now that Auto-Neg has completed. ++ * First, we need to restore the desired flow control ++ * settings because we may have had to re-autoneg with a ++ * different link partner. ++ */ ++ ret_val = e1000e_config_fc_after_link_up(hw); ++ if (ret_val) ++ e_dbg("Error configuring flow control\n"); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Initialize family-specific function pointers for PHY, MAC, and NVM. ++ **/ ++void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) ++{ ++ e1000_init_mac_ops_generic(hw); ++ e1000_init_nvm_ops_generic(hw); ++ hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; ++ hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; ++ switch (hw->mac.type) { ++ case e1000_ich8lan: ++ case e1000_ich9lan: ++ case e1000_ich10lan: ++ hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; ++ break; ++ case e1000_pchlan: ++ hw->phy.ops.init_params = e1000_init_phy_params_pchlan; ++ break; ++ default: ++ break; ++ } ++} ++ ++static DEFINE_MUTEX(nvm_mutex); ++ ++/** ++ * e1000_acquire_swflag_ich8lan - Acquire software control flag ++ * @hw: pointer to the HW structure ++ * ++ * Acquires the software control flag for performing NVM and PHY ++ * operations. This is a function pointer entry point only called by ++ * read/write routines for the PHY and NVM parts. ++ **/ ++static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) ++{ ++ u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; ++ s32 ret_val = E1000_SUCCESS; ++ ++ might_sleep(); ++ ++ mutex_lock(&nvm_mutex); ++ ++ while (timeout) { ++ extcnf_ctrl = er32(EXTCNF_CTRL); ++ ++ if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) { ++ extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; ++ ew32(EXTCNF_CTRL, extcnf_ctrl); ++ ++ extcnf_ctrl = er32(EXTCNF_CTRL); ++ if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) ++ break; ++ } ++ mdelay(1); ++ timeout--; ++ } ++ ++ if (!timeout) { ++ e_dbg("SW/FW/HW has locked the resource for too long.\n"); ++ extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; ++ ew32(EXTCNF_CTRL, extcnf_ctrl); ++ mutex_unlock(&nvm_mutex); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_release_swflag_ich8lan - Release software control flag ++ * @hw: pointer to the HW structure ++ * ++ * Releases the software control flag for performing NVM and PHY operations. ++ * This is a function pointer entry point only called by read/write ++ * routines for the PHY and NVM parts. ++ **/ ++static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) ++{ ++ u32 extcnf_ctrl; ++ ++ extcnf_ctrl = er32(EXTCNF_CTRL); ++ extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; ++ ew32(EXTCNF_CTRL, extcnf_ctrl); ++ ++ mutex_unlock(&nvm_mutex); ++} ++ ++/** ++ * e1000_check_mng_mode_ich8lan - Checks management mode ++ * @hw: pointer to the HW structure ++ * ++ * This checks if the adapter has manageability enabled. ++ * This is a function pointer entry point only called by read/write ++ * routines for the PHY and NVM parts. ++ **/ ++static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) ++{ ++ u32 fwsm; ++ ++ fwsm = er32(FWSM); ++ return (fwsm & E1000_FWSM_MODE_MASK) == ++ (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); ++} ++/** ++ * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked ++ * @hw: pointer to the HW structure ++ * ++ * Checks if firmware is blocking the reset of the PHY. ++ * This is a function pointer entry point only called by ++ * reset routines. ++ **/ ++static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) ++{ ++ u32 fwsm; ++ ++ fwsm = er32(FWSM); ++ return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS ++ : E1000_BLK_PHY_RESET; ++} ++ ++/** ++ * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be ++ * done after every PHY reset. ++ **/ ++static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->mac.type != e1000_pchlan) ++ return ret_val; ++ ++ if (((hw->phy.type == e1000_phy_82577) && ++ ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || ++ ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { ++ /* Disable generation of early preamble */ ++ ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); ++ if (ret_val) ++ return ret_val; ++ ++ /* Preamble tuning for SSC */ ++ ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204); ++ if (ret_val) ++ return ret_val; ++ } ++ ++ if (hw->phy.type == e1000_phy_82578) { ++ /* ++ * Return registers to default by doing a soft reset then ++ * writing 0x3140 to the control register. ++ */ ++ if (hw->phy.revision < 2) { ++ e1000e_phy_sw_reset(hw); ++ ret_val = e1e_wphy(hw, PHY_CONTROL, ++ 0x3140); ++ } ++ } ++ ++ /* Select page 0 */ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ return ret_val; ++ hw->phy.addr = 1; ++ e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); ++ hw->phy.ops.release(hw); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_lan_init_done_ich8lan - Check for PHY config completion ++ * @hw: pointer to the HW structure ++ * ++ * Check the appropriate indication the MAC has finished configuring the ++ * PHY after a software reset. ++ **/ ++static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) ++{ ++ u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; ++ ++ /* Wait for basic configuration completes before proceeding */ ++ do { ++ data = er32(STATUS); ++ data &= E1000_STATUS_LAN_INIT_DONE; ++ udelay(100); ++ } while ((!data) && --loop); ++ ++ /* ++ * If basic configuration is incomplete before the above loop ++ * count reaches 0, loading the configuration from NVM will ++ * leave the PHY in a bad state possibly resulting in no link. ++ */ ++ if (loop == 0) ++ e_dbg("LAN_INIT_DONE not set, increase timeout\n"); ++ ++ /* Clear the Init Done bit for the next init event */ ++ data = er32(STATUS); ++ data &= ~E1000_STATUS_LAN_INIT_DONE; ++ ew32(STATUS, data); ++} ++ ++/** ++ * e1000_phy_hw_reset_ich8lan - Performs a PHY reset ++ * @hw: pointer to the HW structure ++ * ++ * Resets the PHY ++ * This is a function pointer entry point called by drivers ++ * or other shared routines. ++ **/ ++static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; ++ s32 ret_val; ++ u16 word_addr, reg_data, reg_addr, phy_page = 0; ++ ++ ret_val = e1000e_phy_hw_reset_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Allow time for h/w to get to a quiescent state after reset */ ++ msleep(10); ++ ++ if (hw->mac.type == e1000_pchlan) { ++ ret_val = e1000_hv_phy_workarounds_ich8lan(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* ++ * Initialize the PHY from the NVM on ICH platforms. This ++ * is needed due to an issue where the NVM configuration is ++ * not properly autoloaded after power transitions. ++ * Therefore, after each PHY reset, we will load the ++ * configuration data out of the NVM manually. ++ */ ++ if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { ++ /* Check if SW needs configure the PHY */ ++ if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) || ++ (hw->device_id == E1000_DEV_ID_ICH8_IGP_M)) ++ sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; ++ else ++ sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; ++ ++ data = er32(FEXTNVM); ++ if (!(data & sw_cfg_mask)) ++ goto out; ++ ++ /* Wait for basic configuration completes before proceeding */ ++ e1000_lan_init_done_ich8lan(hw); ++ ++ /* ++ * Make sure HW does not configure LCD from PHY ++ * extended configuration before SW configuration ++ */ ++ data = er32(EXTCNF_CTRL); ++ if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) ++ goto out; ++ ++ cnf_size = er32(EXTCNF_SIZE); ++ cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; ++ cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; ++ if (!cnf_size) ++ goto out; ++ ++ cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; ++ cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; ++ ++ /* Configure LCD from extended configuration region. */ ++ ++ /* cnf_base_addr is in DWORD */ ++ word_addr = (u16)(cnf_base_addr << 1); ++ ++ for (i = 0; i < cnf_size; i++) { ++ ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ++ ®_data); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), ++ 1, ®_addr); ++ if (ret_val) ++ goto out; ++ ++ /* Save off the PHY page for future writes. */ ++ if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { ++ phy_page = reg_data; ++ continue; ++ } ++ ++ reg_addr |= phy_page; ++ ++ ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data); ++ if (ret_val) ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info ++ * @hw: pointer to the HW structure ++ * ++ * Wrapper for calling the get_phy_info routines for the appropriate phy type. ++ **/ ++static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = -E1000_ERR_PHY_TYPE; ++ ++ switch (hw->phy.type) { ++ case e1000_phy_ife: ++ ret_val = e1000_get_phy_info_ife_ich8lan(hw); ++ break; ++ case e1000_phy_igp_3: ++ case e1000_phy_bm: ++ case e1000_phy_82578: ++ case e1000_phy_82577: ++ ret_val = e1000e_get_phy_info_igp(hw); ++ break; ++ default: ++ break; ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states ++ * @hw: pointer to the HW structure ++ * ++ * Populates "phy" structure with various feature states. ++ * This function is only called by other family-specific ++ * routines. ++ **/ ++static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ bool link; ++ ++ ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ e_dbg("Phy info is only valid if link is up\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); ++ if (ret_val) ++ goto out; ++ phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) ++ ? false : true; ++ ++ if (phy->polarity_correction) { ++ ret_val = e1000_check_polarity_ife(hw); ++ if (ret_val) ++ goto out; ++ } else { ++ /* Polarity is forced */ ++ phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; ++ } ++ ++ ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); ++ if (ret_val) ++ goto out; ++ ++ phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false; ++ ++ /* The following parameters are undefined for 10/100 operation. */ ++ phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; ++ phy->local_rx = e1000_1000t_rx_status_undefined; ++ phy->remote_rx = e1000_1000t_rx_status_undefined; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state ++ * @hw: pointer to the HW structure ++ * @active: true to enable LPLU, false to disable ++ * ++ * Sets the LPLU D0 state according to the active flag. When ++ * activating LPLU this function also disables smart speed ++ * and vice versa. LPLU will not be activated unless the ++ * device autonegotiation advertisement meets standards of ++ * either 10 or 10/100 or 10/100/1000 at all duplexes. ++ * This is a function pointer entry point only called by ++ * PHY setup routines. ++ **/ ++static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ u32 phy_ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ u16 data; ++ ++ if (phy->type == e1000_phy_ife) ++ goto out; ++ ++ phy_ctrl = er32(PHY_CTRL); ++ ++ if (active) { ++ phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; ++ ew32(PHY_CTRL, phy_ctrl); ++ ++ if (phy->type != e1000_phy_igp_3) ++ goto out; ++ ++ /* ++ * Call gig speed drop workaround on LPLU before accessing ++ * any PHY registers ++ */ ++ if (hw->mac.type == e1000_ich8lan) ++ e1000e_gig_downshift_workaround_ich8lan(hw); ++ ++ /* When LPLU is enabled, we should disable SmartSpeed */ ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } else { ++ phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; ++ ew32(PHY_CTRL, phy_ctrl); ++ ++ if (phy->type != e1000_phy_igp_3) ++ goto out; ++ ++ /* ++ * LPLU and SmartSpeed are mutually exclusive. LPLU is used ++ * during Dx states where the power conservation is most ++ * important. During driver activity we should enable ++ * SmartSpeed, so performance is maintained. ++ */ ++ if (phy->smart_speed == e1000_smart_speed_on) { ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data |= IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } else if (phy->smart_speed == e1000_smart_speed_off) { ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state ++ * @hw: pointer to the HW structure ++ * @active: true to enable LPLU, false to disable ++ * ++ * Sets the LPLU D3 state according to the active flag. When ++ * activating LPLU this function also disables smart speed ++ * and vice versa. LPLU will not be activated unless the ++ * device autonegotiation advertisement meets standards of ++ * either 10 or 10/100 or 10/100/1000 at all duplexes. ++ * This is a function pointer entry point only called by ++ * PHY setup routines. ++ **/ ++static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ u32 phy_ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ u16 data; ++ ++ phy_ctrl = er32(PHY_CTRL); ++ ++ if (!active) { ++ phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; ++ ew32(PHY_CTRL, phy_ctrl); ++ ++ if (phy->type != e1000_phy_igp_3) ++ goto out; ++ ++ /* ++ * LPLU and SmartSpeed are mutually exclusive. LPLU is used ++ * during Dx states where the power conservation is most ++ * important. During driver activity we should enable ++ * SmartSpeed, so performance is maintained. ++ */ ++ if (phy->smart_speed == e1000_smart_speed_on) { ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data |= IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } else if (phy->smart_speed == e1000_smart_speed_off) { ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } ++ } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || ++ (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || ++ (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { ++ phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; ++ ew32(PHY_CTRL, phy_ctrl); ++ ++ if (phy->type != e1000_phy_igp_3) ++ goto out; ++ ++ /* ++ * Call gig speed drop workaround on LPLU before accessing ++ * any PHY registers ++ */ ++ if (hw->mac.type == e1000_ich8lan) ++ e1000e_gig_downshift_workaround_ich8lan(hw); ++ ++ /* When LPLU is enabled, we should disable SmartSpeed */ ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 ++ * @hw: pointer to the HW structure ++ * @bank: pointer to the variable that returns the active bank ++ * ++ * Reads signature byte from the NVM using the flash access registers. ++ * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. ++ **/ ++static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) ++{ ++ u32 eecd; ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); ++ u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; ++ u8 sig_byte = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ switch (hw->mac.type) { ++ case e1000_ich8lan: ++ case e1000_ich9lan: ++ eecd = er32(EECD); ++ if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == ++ E1000_EECD_SEC1VAL_VALID_MASK) { ++ if (eecd & E1000_EECD_SEC1VAL) ++ *bank = 1; ++ else ++ *bank = 0; ++ ++ goto out; ++ } ++ e_dbg("Unable to determine valid NVM bank via EEC - " ++ "reading flash signature\n"); ++ /* fall-thru */ ++ default: ++ /* set bank to 0 in case flash read fails */ ++ *bank = 0; ++ ++ /* Check bank 0 */ ++ ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, ++ &sig_byte); ++ if (ret_val) ++ goto out; ++ if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == ++ E1000_ICH_NVM_SIG_VALUE) { ++ *bank = 0; ++ goto out; ++ } ++ ++ /* Check bank 1 */ ++ ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + ++ bank1_offset, ++ &sig_byte); ++ if (ret_val) ++ goto out; ++ if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == ++ E1000_ICH_NVM_SIG_VALUE) { ++ *bank = 1; ++ goto out; ++ } ++ ++ e_dbg("ERROR: No valid NVM bank present\n"); ++ ret_val = -E1000_ERR_NVM; ++ break; ++ } ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_nvm_ich8lan - Read word(s) from the NVM ++ * @hw: pointer to the HW structure ++ * @offset: The offset (in bytes) of the word(s) to read. ++ * @words: Size of data to read in words ++ * @data: Pointer to the word(s) to read at offset. ++ * ++ * Reads a word(s) from the NVM using the flash access registers. ++ **/ ++static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; ++ u32 act_offset; ++ s32 ret_val = E1000_SUCCESS; ++ u32 bank = 0; ++ u16 i, word; ++ ++ if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || ++ (words == 0)) { ++ e_dbg("nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ ret_val = nvm->ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); ++ if (ret_val != E1000_SUCCESS) ++ goto release; ++ ++ act_offset = (bank) ? nvm->flash_bank_size : 0; ++ act_offset += offset; ++ ++ for (i = 0; i < words; i++) { ++ if ((dev_spec->shadow_ram) && ++ (dev_spec->shadow_ram[offset+i].modified)) { ++ data[i] = dev_spec->shadow_ram[offset+i].value; ++ } else { ++ ret_val = e1000_read_flash_word_ich8lan(hw, ++ act_offset + i, ++ &word); ++ if (ret_val) ++ break; ++ data[i] = word; ++ } ++ } ++ ++release: ++ nvm->ops.release(hw); ++ ++out: ++ if (ret_val) ++ e_dbg("NVM read error: %d\n", ret_val); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_flash_cycle_init_ich8lan - Initialize flash ++ * @hw: pointer to the HW structure ++ * ++ * This function does initial flash setup so that a new read/write/erase cycle ++ * can be started. ++ **/ ++static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) ++{ ++ union ich8_hws_flash_status hsfsts; ++ s32 ret_val = -E1000_ERR_NVM; ++ s32 i = 0; ++ ++ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); ++ ++ /* Check if the flash descriptor is valid */ ++ if (hsfsts.hsf_status.fldesvalid == 0) { ++ e_dbg("Flash descriptor invalid. " ++ "SW Sequencing must be used."); ++ goto out; ++ } ++ ++ /* Clear FCERR and DAEL in hw status by writing 1 */ ++ hsfsts.hsf_status.flcerr = 1; ++ hsfsts.hsf_status.dael = 1; ++ ++ ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); ++ ++ /* ++ * Either we should have a hardware SPI cycle in progress ++ * bit to check against, in order to start a new cycle or ++ * FDONE bit should be changed in the hardware so that it ++ * is 1 after hardware reset, which can then be used as an ++ * indication whether a cycle is in progress or has been ++ * completed. ++ */ ++ ++ if (hsfsts.hsf_status.flcinprog == 0) { ++ /* ++ * There is no cycle running at present, ++ * so we can start a cycle. ++ * Begin by setting Flash Cycle Done. ++ */ ++ hsfsts.hsf_status.flcdone = 1; ++ ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); ++ ret_val = E1000_SUCCESS; ++ } else { ++ /* ++ * Otherwise poll for sometime so the current ++ * cycle has a chance to end before giving up. ++ */ ++ for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { ++ hsfsts.regval = er16flash( ++ ICH_FLASH_HSFSTS); ++ if (hsfsts.hsf_status.flcinprog == 0) { ++ ret_val = E1000_SUCCESS; ++ break; ++ } ++ udelay(1); ++ } ++ if (ret_val == E1000_SUCCESS) { ++ /* ++ * Successful in waiting for previous cycle to timeout, ++ * now set the Flash Cycle Done. ++ */ ++ hsfsts.hsf_status.flcdone = 1; ++ ew16flash(ICH_FLASH_HSFSTS, ++ hsfsts.regval); ++ } else { ++ e_dbg("Flash controller busy, cannot get access"); ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) ++ * @hw: pointer to the HW structure ++ * @timeout: maximum time to wait for completion ++ * ++ * This function starts a flash cycle and waits for its completion. ++ **/ ++static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) ++{ ++ union ich8_hws_flash_ctrl hsflctl; ++ union ich8_hws_flash_status hsfsts; ++ s32 ret_val = -E1000_ERR_NVM; ++ u32 i = 0; ++ ++ /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ ++ hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); ++ hsflctl.hsf_ctrl.flcgo = 1; ++ ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); ++ ++ /* wait till FDONE bit is set to 1 */ ++ do { ++ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); ++ if (hsfsts.hsf_status.flcdone == 1) ++ break; ++ udelay(1); ++ } while (i++ < timeout); ++ ++ if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) ++ ret_val = E1000_SUCCESS; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_read_flash_word_ich8lan - Read word from flash ++ * @hw: pointer to the HW structure ++ * @offset: offset to data location ++ * @data: pointer to the location for storing the data ++ * ++ * Reads the flash word at offset into data. Offset is converted ++ * to bytes before read. ++ **/ ++static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, ++ u16 *data) ++{ ++ s32 ret_val; ++ ++ if (!data) { ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ /* Must convert offset into bytes. */ ++ offset <<= 1; ++ ++ ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_flash_byte_ich8lan - Read byte from flash ++ * @hw: pointer to the HW structure ++ * @offset: The offset of the byte to read. ++ * @data: Pointer to a byte to store the value read. ++ * ++ * Reads a single byte from the NVM using the flash access registers. ++ **/ ++static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, ++ u8 *data) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 word = 0; ++ ++ ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); ++ if (ret_val) ++ goto out; ++ ++ *data = (u8)word; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_flash_data_ich8lan - Read byte or word from NVM ++ * @hw: pointer to the HW structure ++ * @offset: The offset (in bytes) of the byte or word to read. ++ * @size: Size of data to read, 1=byte 2=word ++ * @data: Pointer to the word to store the value read. ++ * ++ * Reads a byte or word from the NVM using the flash access registers. ++ **/ ++static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, ++ u8 size, u16 *data) ++{ ++ union ich8_hws_flash_status hsfsts; ++ union ich8_hws_flash_ctrl hsflctl; ++ u32 flash_linear_addr; ++ u32 flash_data = 0; ++ s32 ret_val = -E1000_ERR_NVM; ++ u8 count = 0; ++ ++ if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) ++ goto out; ++ flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + ++ hw->nvm.flash_base_addr; ++ ++ do { ++ udelay(1); ++ /* Steps */ ++ ret_val = e1000_flash_cycle_init_ich8lan(hw); ++ if (ret_val != E1000_SUCCESS) ++ break; ++ ++ hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); ++ /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ ++ hsflctl.hsf_ctrl.fldbcount = size - 1; ++ hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; ++ ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); ++ ++ ew32flash(ICH_FLASH_FADDR, flash_linear_addr); ++ ++ ret_val = e1000_flash_cycle_ich8lan(hw, ++ ICH_FLASH_READ_COMMAND_TIMEOUT); ++ ++ /* ++ * Check if FCERR is set to 1, if set to 1, clear it ++ * and try the whole sequence a few more times, else ++ * read in (shift in) the Flash Data0, the order is ++ * least significant byte first msb to lsb ++ */ ++ if (ret_val == E1000_SUCCESS) { ++ flash_data = er32flash(ICH_FLASH_FDATA0); ++ if (size == 1) ++ *data = (u8)(flash_data & 0x000000FF); ++ else if (size == 2) ++ *data = (u16)(flash_data & 0x0000FFFF); ++ break; ++ } else { ++ /* ++ * If we've gotten here, then things are probably ++ * completely hosed, but if the error condition is ++ * detected, it won't hurt to give it another try... ++ * ICH_FLASH_CYCLE_REPEAT_COUNT times. ++ */ ++ hsfsts.regval = er16flash( ++ ICH_FLASH_HSFSTS); ++ if (hsfsts.hsf_status.flcerr == 1) { ++ /* Repeat for some time before giving up. */ ++ continue; ++ } else if (hsfsts.hsf_status.flcdone == 0) { ++ e_dbg("Timeout error - flash cycle " ++ "did not complete."); ++ break; ++ } ++ } ++ } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_nvm_ich8lan - Write word(s) to the NVM ++ * @hw: pointer to the HW structure ++ * @offset: The offset (in bytes) of the word(s) to write. ++ * @words: Size of data to write in words ++ * @data: Pointer to the word(s) to write at offset. ++ * ++ * Writes a byte or word to the NVM using the flash access registers. ++ **/ ++static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; ++ s32 ret_val = E1000_SUCCESS; ++ u16 i; ++ ++ if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || ++ (words == 0)) { ++ e_dbg("nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ ret_val = nvm->ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ for (i = 0; i < words; i++) { ++ dev_spec->shadow_ram[offset+i].modified = true; ++ dev_spec->shadow_ram[offset+i].value = data[i]; ++ } ++ ++ nvm->ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM ++ * @hw: pointer to the HW structure ++ * ++ * The NVM checksum is updated by calling the generic update_nvm_checksum, ++ * which writes the checksum to the shadow ram. The changes in the shadow ++ * ram are then committed to the EEPROM by processing each bank at a time ++ * checking for the modified bit and writing only the pending changes. ++ * After a successful commit, the shadow ram is cleared and is ready for ++ * future writes. ++ **/ ++static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; ++ u32 i, act_offset, new_bank_offset, old_bank_offset, bank; ++ s32 ret_val; ++ u16 data; ++ ++ ret_val = e1000e_update_nvm_checksum_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ if (nvm->type != e1000_nvm_flash_sw) ++ goto out; ++ ++ ret_val = nvm->ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * We're writing to the opposite bank so if we're on bank 1, ++ * write to bank 0 etc. We also need to erase the segment that ++ * is going to be written ++ */ ++ ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); ++ if (ret_val != E1000_SUCCESS) { ++ nvm->ops.release(hw); ++ goto out; ++ } ++ ++ if (bank == 0) { ++ new_bank_offset = nvm->flash_bank_size; ++ old_bank_offset = 0; ++ ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); ++ if (ret_val) { ++ nvm->ops.release(hw); ++ goto out; ++ } ++ } else { ++ old_bank_offset = nvm->flash_bank_size; ++ new_bank_offset = 0; ++ ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); ++ if (ret_val) { ++ nvm->ops.release(hw); ++ goto out; ++ } ++ } ++ ++ for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { ++ /* ++ * Determine whether to write the value stored ++ * in the other NVM bank or a modified value stored ++ * in the shadow RAM ++ */ ++ if (dev_spec->shadow_ram[i].modified) { ++ data = dev_spec->shadow_ram[i].value; ++ } else { ++ ret_val = e1000_read_flash_word_ich8lan(hw, i + ++ old_bank_offset, ++ &data); ++ if (ret_val) ++ break; ++ } ++ ++ /* ++ * If the word is 0x13, then make sure the signature bits ++ * (15:14) are 11b until the commit has completed. ++ * This will allow us to write 10b which indicates the ++ * signature is valid. We want to do this after the write ++ * has completed so that we don't mark the segment valid ++ * while the write is still in progress ++ */ ++ if (i == E1000_ICH_NVM_SIG_WORD) ++ data |= E1000_ICH_NVM_SIG_MASK; ++ ++ /* Convert offset to bytes. */ ++ act_offset = (i + new_bank_offset) << 1; ++ ++ udelay(100); ++ /* Write the bytes to the new bank. */ ++ ret_val = e1000_retry_write_flash_byte_ich8lan(hw, ++ act_offset, ++ (u8)data); ++ if (ret_val) ++ break; ++ ++ udelay(100); ++ ret_val = e1000_retry_write_flash_byte_ich8lan(hw, ++ act_offset + 1, ++ (u8)(data >> 8)); ++ if (ret_val) ++ break; ++ } ++ ++ /* ++ * Don't bother writing the segment valid bits if sector ++ * programming failed. ++ */ ++ if (ret_val) { ++ e_dbg("Flash commit failed.\n"); ++ nvm->ops.release(hw); ++ goto out; ++ } ++ ++ /* ++ * Finally validate the new segment by setting bit 15:14 ++ * to 10b in word 0x13 , this can be done without an ++ * erase as well since these bits are 11 to start with ++ * and we need to change bit 14 to 0b ++ */ ++ act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; ++ ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); ++ if (ret_val) { ++ nvm->ops.release(hw); ++ goto out; ++ } ++ data &= 0xBFFF; ++ ret_val = e1000_retry_write_flash_byte_ich8lan(hw, ++ act_offset * 2 + 1, ++ (u8)(data >> 8)); ++ if (ret_val) { ++ nvm->ops.release(hw); ++ goto out; ++ } ++ ++ /* ++ * And invalidate the previously valid segment by setting ++ * its signature word (0x13) high_byte to 0b. This can be ++ * done without an erase because flash erase sets all bits ++ * to 1's. We can write 1's to 0's without an erase ++ */ ++ act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; ++ ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); ++ if (ret_val) { ++ nvm->ops.release(hw); ++ goto out; ++ } ++ ++ /* Great! Everything worked, we can now clear the cached entries. */ ++ for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { ++ dev_spec->shadow_ram[i].modified = false; ++ dev_spec->shadow_ram[i].value = 0xFFFF; ++ } ++ ++ nvm->ops.release(hw); ++ ++ /* ++ * Reload the EEPROM, or else modifications will not appear ++ * until after the next adapter reset. ++ */ ++ nvm->ops.reload(hw); ++ msleep(10); ++ ++out: ++ if (ret_val) ++ e_dbg("NVM update error: %d\n", ret_val); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. ++ * If the bit is 0, that the EEPROM had been modified, but the checksum was not ++ * calculated, in which case we need to calculate the checksum and set bit 6. ++ **/ ++static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 data; ++ ++ /* ++ * Read 0x19 and check bit 6. If this bit is 0, the checksum ++ * needs to be fixed. This bit is an indication that the NVM ++ * was prepared by OEM software and did not calculate the ++ * checksum...a likely scenario. ++ */ ++ ret_val = e1000_read_nvm(hw, 0x19, 1, &data); ++ if (ret_val) ++ goto out; ++ ++ if ((data & 0x40) == 0) { ++ data |= 0x40; ++ ret_val = e1000_write_nvm(hw, 0x19, 1, &data); ++ if (ret_val) ++ goto out; ++ ret_val = e1000e_update_nvm_checksum(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = e1000e_validate_nvm_checksum_generic(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_flash_data_ich8lan - Writes bytes to the NVM ++ * @hw: pointer to the HW structure ++ * @offset: The offset (in bytes) of the byte/word to read. ++ * @size: Size of data to read, 1=byte 2=word ++ * @data: The byte(s) to write to the NVM. ++ * ++ * Writes one/two bytes to the NVM using the flash access registers. ++ **/ ++static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, ++ u8 size, u16 data) ++{ ++ union ich8_hws_flash_status hsfsts; ++ union ich8_hws_flash_ctrl hsflctl; ++ u32 flash_linear_addr; ++ u32 flash_data = 0; ++ s32 ret_val = -E1000_ERR_NVM; ++ u8 count = 0; ++ ++ if (size < 1 || size > 2 || data > size * 0xff || ++ offset > ICH_FLASH_LINEAR_ADDR_MASK) ++ goto out; ++ ++ flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + ++ hw->nvm.flash_base_addr; ++ ++ do { ++ udelay(1); ++ /* Steps */ ++ ret_val = e1000_flash_cycle_init_ich8lan(hw); ++ if (ret_val != E1000_SUCCESS) ++ break; ++ ++ hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); ++ /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ ++ hsflctl.hsf_ctrl.fldbcount = size - 1; ++ hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; ++ ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); ++ ++ ew32flash(ICH_FLASH_FADDR, flash_linear_addr); ++ ++ if (size == 1) ++ flash_data = (u32)data & 0x00FF; ++ else ++ flash_data = (u32)data; ++ ++ ew32flash(ICH_FLASH_FDATA0, flash_data); ++ ++ /* ++ * check if FCERR is set to 1 , if set to 1, clear it ++ * and try the whole sequence a few more times else done ++ */ ++ ret_val = e1000_flash_cycle_ich8lan(hw, ++ ICH_FLASH_WRITE_COMMAND_TIMEOUT); ++ if (ret_val == E1000_SUCCESS) ++ break; ++ ++ /* ++ * If we're here, then things are most likely ++ * completely hosed, but if the error condition ++ * is detected, it won't hurt to give it another ++ * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. ++ */ ++ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); ++ if (hsfsts.hsf_status.flcerr == 1) { ++ /* Repeat for some time before giving up. */ ++ continue; ++ } else if (hsfsts.hsf_status.flcdone == 0) { ++ e_dbg("Timeout error - flash cycle " ++ "did not complete."); ++ break; ++ } ++ } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_flash_byte_ich8lan - Write a single byte to NVM ++ * @hw: pointer to the HW structure ++ * @offset: The index of the byte to read. ++ * @data: The byte to write to the NVM. ++ * ++ * Writes a single byte to the NVM using the flash access registers. ++ **/ ++static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, ++ u8 data) ++{ ++ u16 word = (u16)data; ++ ++ return e1000_write_flash_data_ich8lan(hw, offset, 1, word); ++} ++ ++/** ++ * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM ++ * @hw: pointer to the HW structure ++ * @offset: The offset of the byte to write. ++ * @byte: The byte to write to the NVM. ++ * ++ * Writes a single byte to the NVM using the flash access registers. ++ * Goes through a retry algorithm before giving up. ++ **/ ++static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, ++ u32 offset, u8 byte) ++{ ++ s32 ret_val; ++ u16 program_retries; ++ ++ ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); ++ if (ret_val == E1000_SUCCESS) ++ goto out; ++ ++ for (program_retries = 0; program_retries < 100; program_retries++) { ++ e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); ++ udelay(100); ++ ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); ++ if (ret_val == E1000_SUCCESS) ++ break; ++ } ++ if (program_retries == 100) { ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM ++ * @hw: pointer to the HW structure ++ * @bank: 0 for first bank, 1 for second bank, etc. ++ * ++ * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. ++ * bank N is 4096 * N + flash_reg_addr. ++ **/ ++static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ union ich8_hws_flash_status hsfsts; ++ union ich8_hws_flash_ctrl hsflctl; ++ u32 flash_linear_addr; ++ /* bank size is in 16bit words - adjust to bytes */ ++ u32 flash_bank_size = nvm->flash_bank_size * 2; ++ s32 ret_val = E1000_SUCCESS; ++ s32 count = 0; ++ s32 j, iteration, sector_size; ++ ++ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); ++ ++ /* ++ * Determine HW Sector size: Read BERASE bits of hw flash status ++ * register ++ * 00: The Hw sector is 256 bytes, hence we need to erase 16 ++ * consecutive sectors. The start index for the nth Hw sector ++ * can be calculated as = bank * 4096 + n * 256 ++ * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. ++ * The start index for the nth Hw sector can be calculated ++ * as = bank * 4096 ++ * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 ++ * (ich9 only, otherwise error condition) ++ * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 ++ */ ++ switch (hsfsts.hsf_status.berasesz) { ++ case 0: ++ /* Hw sector size 256 */ ++ sector_size = ICH_FLASH_SEG_SIZE_256; ++ iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; ++ break; ++ case 1: ++ sector_size = ICH_FLASH_SEG_SIZE_4K; ++ iteration = 1; ++ break; ++ case 2: ++ if (hw->mac.type == e1000_ich9lan) { ++ sector_size = ICH_FLASH_SEG_SIZE_8K; ++ iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; ++ } else { ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ break; ++ case 3: ++ sector_size = ICH_FLASH_SEG_SIZE_64K; ++ iteration = 1; ++ break; ++ default: ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ /* Start with the base address, then add the sector offset. */ ++ flash_linear_addr = hw->nvm.flash_base_addr; ++ flash_linear_addr += (bank) ? (sector_size * iteration) : 0; ++ ++ for (j = 0; j < iteration ; j++) { ++ do { ++ /* Steps */ ++ ret_val = e1000_flash_cycle_init_ich8lan(hw); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Write a value 11 (block Erase) in Flash ++ * Cycle field in hw flash control ++ */ ++ hsflctl.regval = er16flash( ++ ICH_FLASH_HSFCTL); ++ hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; ++ ew16flash(ICH_FLASH_HSFCTL, ++ hsflctl.regval); ++ ++ /* ++ * Write the last 24 bits of an index within the ++ * block into Flash Linear address field in Flash ++ * Address. ++ */ ++ flash_linear_addr += (j * sector_size); ++ ew32flash(ICH_FLASH_FADDR, ++ flash_linear_addr); ++ ++ ret_val = e1000_flash_cycle_ich8lan(hw, ++ ICH_FLASH_ERASE_COMMAND_TIMEOUT); ++ if (ret_val == E1000_SUCCESS) ++ break; ++ ++ /* ++ * Check if FCERR is set to 1. If 1, ++ * clear it and try the whole sequence ++ * a few more times else Done ++ */ ++ hsfsts.regval = er16flash( ++ ICH_FLASH_HSFSTS); ++ if (hsfsts.hsf_status.flcerr == 1) ++ /* repeat for some time before giving up */ ++ continue; ++ else if (hsfsts.hsf_status.flcdone == 0) ++ goto out; ++ } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_valid_led_default_ich8lan - Set the default LED settings ++ * @hw: pointer to the HW structure ++ * @data: Pointer to the LED settings ++ * ++ * Reads the LED default settings from the NVM to data. If the NVM LED ++ * settings is all 0's or F's, set the LED default to a valid LED default ++ * setting. ++ **/ ++static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) ++{ ++ s32 ret_val; ++ ++ ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); ++ if (ret_val) { ++ e_dbg("NVM Read Error\n"); ++ goto out; ++ } ++ ++ if (*data == ID_LED_RESERVED_0000 || ++ *data == ID_LED_RESERVED_FFFF) ++ *data = ID_LED_DEFAULT_ICH8LAN; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_id_led_init_pchlan - store LED configurations ++ * @hw: pointer to the HW structure ++ * ++ * PCH does not control LEDs via the LEDCTL register, rather it uses ++ * the PHY LED configuration register. ++ * ++ * PCH also does not have an "always on" or "always off" mode which ++ * complicates the ID feature. Instead of using the "on" mode to indicate ++ * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()), ++ * use "link_up" mode. The LEDs will still ID on request if there is no ++ * link based on logic in e1000_led_[on|off]_pchlan(). ++ **/ ++static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val; ++ const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; ++ const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; ++ u16 data, i, temp, shift; ++ ++ /* Get default ID LED modes */ ++ ret_val = hw->nvm.ops.valid_led_default(hw, &data); ++ if (ret_val) ++ goto out; ++ ++ mac->ledctl_default = er32(LEDCTL); ++ mac->ledctl_mode1 = mac->ledctl_default; ++ mac->ledctl_mode2 = mac->ledctl_default; ++ ++ for (i = 0; i < 4; i++) { ++ temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; ++ shift = (i * 5); ++ switch (temp) { ++ case ID_LED_ON1_DEF2: ++ case ID_LED_ON1_ON2: ++ case ID_LED_ON1_OFF2: ++ mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); ++ mac->ledctl_mode1 |= (ledctl_on << shift); ++ break; ++ case ID_LED_OFF1_DEF2: ++ case ID_LED_OFF1_ON2: ++ case ID_LED_OFF1_OFF2: ++ mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); ++ mac->ledctl_mode1 |= (ledctl_off << shift); ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++ switch (temp) { ++ case ID_LED_DEF1_ON2: ++ case ID_LED_ON1_ON2: ++ case ID_LED_OFF1_ON2: ++ mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); ++ mac->ledctl_mode2 |= (ledctl_on << shift); ++ break; ++ case ID_LED_DEF1_OFF2: ++ case ID_LED_ON1_OFF2: ++ case ID_LED_OFF1_OFF2: ++ mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); ++ mac->ledctl_mode2 |= (ledctl_off << shift); ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_bus_info_ich8lan - Get/Set the bus type and width ++ * @hw: pointer to the HW structure ++ * ++ * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability ++ * register, so the the bus width is hard coded. ++ **/ ++static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_bus_info *bus = &hw->bus; ++ s32 ret_val; ++ ++ ret_val = e1000e_get_bus_info_pcie(hw); ++ ++ /* ++ * ICH devices are "PCI Express"-ish. They have ++ * a configuration space, but do not contain ++ * PCI Express Capability registers, so bus width ++ * must be hardcoded. ++ */ ++ if (bus->width == e1000_bus_width_unknown) ++ bus->width = e1000_bus_width_pcie_x1; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_reset_hw_ich8lan - Reset the hardware ++ * @hw: pointer to the HW structure ++ * ++ * Does a full reset of the hardware which includes a reset of the PHY and ++ * MAC. ++ **/ ++static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) ++{ ++ u32 ctrl, icr, kab; ++ s32 ret_val; ++ ++ /* ++ * Prevent the PCI-E bus from sticking if there is no TLP connection ++ * on the last TLP read/write transaction when MAC is reset. ++ */ ++ ret_val = e1000e_disable_pcie_master(hw); ++ if (ret_val) ++ e_dbg("PCI-E Master disable polling has failed.\n"); ++ ++ e_dbg("Masking off all interrupts\n"); ++ ew32(IMC, 0xffffffff); ++ ++ /* ++ * Disable the Transmit and Receive units. Then delay to allow ++ * any pending transactions to complete before we hit the MAC ++ * with the global reset. ++ */ ++ ew32(RCTL, 0); ++ ew32(TCTL, E1000_TCTL_PSP); ++ e1e_flush(); ++ ++ msleep(10); ++ ++ /* Workaround for ICH8 bit corruption issue in FIFO memory */ ++ if (hw->mac.type == e1000_ich8lan) { ++ /* Set Tx and Rx buffer allocation to 8k apiece. */ ++ ew32(PBA, E1000_PBA_8K); ++ /* Set Packet Buffer Size to 16k. */ ++ ew32(PBS, E1000_PBS_16K); ++ } ++ ++ ctrl = er32(CTRL); ++ ++ if (!e1000_check_reset_block(hw) && !hw->phy.reset_disable) { ++ /* Clear PHY Reset Asserted bit */ ++ if (hw->mac.type >= e1000_pchlan) { ++ u32 status = er32(STATUS); ++ ew32(STATUS, status & ++ ~E1000_STATUS_PHYRA); ++ } ++ ++ /* ++ * PHY HW reset requires MAC CORE reset at the same ++ * time to make sure the interface between MAC and the ++ * external PHY is reset. ++ */ ++ ctrl |= E1000_CTRL_PHY_RST; ++ } ++ ret_val = e1000_acquire_swflag_ich8lan(hw); ++ e_dbg("Issuing a global reset to ich8lan\n"); ++ ew32(CTRL, (ctrl | E1000_CTRL_RST)); ++ msleep(20); ++ ++ if (!ret_val) ++ e1000_release_swflag_ich8lan(hw); ++ ++ if (ctrl & E1000_CTRL_PHY_RST) ++ ret_val = hw->phy.ops.get_cfg_done(hw); ++ ++ if (hw->mac.type >= e1000_ich10lan) { ++ e1000_lan_init_done_ich8lan(hw); ++ } else { ++ if (!ret_val) { ++ /* release the swflag because it is not reset by ++ * hardware reset ++ */ ++ e1000_release_swflag_ich8lan(hw); ++ } ++ ++ ret_val = e1000e_get_auto_rd_done(hw); ++ if (ret_val) { ++ /* ++ * When auto config read does not complete, do not ++ * return with an error. This can happen in situations ++ * where there is no eeprom and prevents getting link. ++ */ ++ e_dbg("Auto Read Done did not complete\n"); ++ } ++ } ++ ++ /* ++ * For PCH, this write will make sure that any noise ++ * will be detected as a CRC error and be dropped rather than show up ++ * as a bad packet to the DMA engine. ++ */ ++ if (hw->mac.type == e1000_pchlan) ++ ew32(CRC_OFFSET, 0x65656565); ++ ++ ew32(IMC, 0xffffffff); ++ icr = er32(ICR); ++ ++ kab = er32(KABGTXD); ++ kab |= E1000_KABGTXD_BGSQLBIAS; ++ ew32(KABGTXD, kab); ++ ++ if (hw->mac.type == e1000_pchlan) ++ ret_val = e1000_hv_phy_workarounds_ich8lan(hw); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_init_hw_ich8lan - Initialize the hardware ++ * @hw: pointer to the HW structure ++ * ++ * Prepares the hardware for transmit and receive by doing the following: ++ * - initialize hardware bits ++ * - initialize LED identification ++ * - setup receive address registers ++ * - setup flow control ++ * - setup transmit descriptors ++ * - clear statistics ++ **/ ++static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 ctrl_ext, txdctl, snoop; ++ s32 ret_val; ++ u16 i; ++ ++ e1000_initialize_hw_bits_ich8lan(hw); ++ ++ /* Initialize identification LED */ ++ ret_val = mac->ops.id_led_init(hw); ++ if (ret_val) ++ /* This is not fatal and we should not stop init due to this */ ++ e_dbg("Error initializing identification LED\n"); ++ ++ /* Setup the receive address. */ ++ e1000e_init_rx_addrs(hw, mac->rar_entry_count); ++ ++ /* Zero out the Multicast HASH table */ ++ e_dbg("Zeroing the MTA\n"); ++ for (i = 0; i < mac->mta_reg_count; i++) ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); ++ ++ /* ++ * The 82578 Rx buffer will stall if wakeup is enabled in host and ++ * the ME. Reading the BM_WUC register will clear the host wakeup bit. ++ * Reset the phy after disabling host wakeup to reset the Rx buffer. ++ */ ++ if (hw->phy.type == e1000_phy_82578) { ++ e1e_rphy(hw, BM_WUC, &i); ++ ret_val = e1000_phy_hw_reset_ich8lan(hw); ++ if (ret_val) ++ return ret_val; ++ } ++ ++ /* Setup link and flow control */ ++ ret_val = mac->ops.setup_link(hw); ++ ++ /* Set the transmit descriptor write-back policy for both queues */ ++ txdctl = er32(TXDCTL(0)); ++ txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB; ++ txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | ++ E1000_TXDCTL_MAX_TX_DESC_PREFETCH; ++ ew32(TXDCTL(0), txdctl); ++ txdctl = er32(TXDCTL(1)); ++ txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB; ++ txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | ++ E1000_TXDCTL_MAX_TX_DESC_PREFETCH; ++ ew32(TXDCTL(1), txdctl); ++ ++ /* ++ * ICH8 has opposite polarity of no_snoop bits. ++ * By default, we should use snoop behavior. ++ */ ++ if (mac->type == e1000_ich8lan) ++ snoop = PCIE_ICH8_SNOOP_ALL; ++ else ++ snoop = (u32)~(PCIE_NO_SNOOP_ALL); ++ e1000e_set_pcie_no_snoop(hw, snoop); ++ ++ ctrl_ext = er32(CTRL_EXT); ++ ctrl_ext |= E1000_CTRL_EXT_RO_DIS; ++ ew32(CTRL_EXT, ctrl_ext); ++ ++ /* ++ * Clear all of the statistics registers (clear on read). It is ++ * important that we do this after we have tried to establish link ++ * because the symbol error count will increment wildly if there ++ * is no link. ++ */ ++ e1000_clear_hw_cntrs_ich8lan(hw); ++ ++ return ret_val; ++} ++/** ++ * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits ++ * @hw: pointer to the HW structure ++ * ++ * Sets/Clears required hardware bits necessary for correctly setting up the ++ * hardware for transmit and receive. ++ **/ ++static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) ++{ ++ u32 reg; ++ ++ /* Extended Device Control */ ++ reg = er32(CTRL_EXT); ++ reg |= (1 << 22); ++ /* Enable PHY low-power state when MAC is at D3 w/o WoL */ ++ if (hw->mac.type >= e1000_pchlan) ++ reg |= E1000_CTRL_EXT_PHYPDEN; ++ ew32(CTRL_EXT, reg); ++ ++ /* Transmit Descriptor Control 0 */ ++ reg = er32(TXDCTL(0)); ++ reg |= (1 << 22); ++ ew32(TXDCTL(0), reg); ++ ++ /* Transmit Descriptor Control 1 */ ++ reg = er32(TXDCTL(1)); ++ reg |= (1 << 22); ++ ew32(TXDCTL(1), reg); ++ ++ /* Transmit Arbitration Control 0 */ ++ reg = er32(TARC(0)); ++ if (hw->mac.type == e1000_ich8lan) ++ reg |= (1 << 28) | (1 << 29); ++ reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); ++ ew32(TARC(0), reg); ++ ++ /* Transmit Arbitration Control 1 */ ++ reg = er32(TARC(1)); ++ if (er32(TCTL) & E1000_TCTL_MULR) ++ reg &= ~(1 << 28); ++ else ++ reg |= (1 << 28); ++ reg |= (1 << 24) | (1 << 26) | (1 << 30); ++ ew32(TARC(1), reg); ++ ++ /* Device Status */ ++ if (hw->mac.type == e1000_ich8lan) { ++ reg = er32(STATUS); ++ reg &= ~(1 << 31); ++ ew32(STATUS, reg); ++ } ++ ++ return; ++} ++ ++/** ++ * e1000_setup_link_ich8lan - Setup flow control and link settings ++ * @hw: pointer to the HW structure ++ * ++ * Determines which flow control settings to use, then configures flow ++ * control. Calls the appropriate media-specific link configuration ++ * function. Assuming the adapter has a valid link partner, a valid link ++ * should be established. Assumes the hardware has previously been reset ++ * and the transmitter and receiver are not enabled. ++ **/ ++static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (e1000_check_reset_block(hw)) ++ goto out; ++ ++ /* ++ * ICH parts do not have a word in the NVM to determine ++ * the default flow control setting, so we explicitly ++ * set it to full. ++ */ ++ if (hw->fc.requested_mode == e1000_fc_default) ++ hw->fc.requested_mode = e1000_fc_full; ++ ++ /* ++ * Save off the requested flow control mode for use later. Depending ++ * on the link partner's capabilities, we may or may not use this mode. ++ */ ++ hw->fc.current_mode = hw->fc.requested_mode; ++ ++ e_dbg("After fix-ups FlowControl is now = %x\n", ++ hw->fc.current_mode); ++ ++ /* Continue to configure the copper link. */ ++ ret_val = hw->mac.ops.setup_physical_interface(hw); ++ if (ret_val) ++ goto out; ++ ++ ew32(FCTTV, hw->fc.pause_time); ++ if ((hw->phy.type == e1000_phy_82578) || ++ (hw->phy.type == e1000_phy_82577)) { ++ ret_val = e1e_wphy(hw, ++ PHY_REG(BM_PORT_CTRL_PAGE, 27), ++ hw->fc.pause_time); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = e1000e_set_fc_watermarks(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface ++ * @hw: pointer to the HW structure ++ * ++ * Configures the kumeran interface to the PHY to wait the appropriate time ++ * when polling the PHY, then call the generic setup_copper_link to finish ++ * configuring the copper link. ++ **/ ++static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val; ++ u16 reg_data; ++ ++ ctrl = er32(CTRL); ++ ctrl |= E1000_CTRL_SLU; ++ ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ ew32(CTRL, ctrl); ++ ++ /* ++ * Set the mac to wait the maximum time between each iteration ++ * and increase the max iterations when polling the phy; ++ * this fixes erroneous timeouts at 10Mbps. ++ */ ++ ret_val = e1000e_write_kmrn_reg(hw, ++ E1000_KMRNCTRLSTA_TIMEOUTS, ++ 0xFFFF); ++ if (ret_val) ++ goto out; ++ ret_val = e1000e_read_kmrn_reg(hw, ++ E1000_KMRNCTRLSTA_INBAND_PARAM, ++ ®_data); ++ if (ret_val) ++ goto out; ++ reg_data |= 0x3F; ++ ret_val = e1000e_write_kmrn_reg(hw, ++ E1000_KMRNCTRLSTA_INBAND_PARAM, ++ reg_data); ++ if (ret_val) ++ goto out; ++ ++ switch (hw->phy.type) { ++ case e1000_phy_igp_3: ++ ret_val = e1000e_copper_link_setup_igp(hw); ++ if (ret_val) ++ goto out; ++ break; ++ case e1000_phy_bm: ++ case e1000_phy_82578: ++ ret_val = e1000e_copper_link_setup_m88(hw); ++ if (ret_val) ++ goto out; ++ break; ++ case e1000_phy_82577: ++ ret_val = e1000_copper_link_setup_82577(hw); ++ if (ret_val) ++ goto out; ++ break; ++ case e1000_phy_ife: ++ ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ++ ®_data); ++ if (ret_val) ++ goto out; ++ ++ reg_data &= ~IFE_PMC_AUTO_MDIX; ++ ++ switch (hw->phy.mdix) { ++ case 1: ++ reg_data &= ~IFE_PMC_FORCE_MDIX; ++ break; ++ case 2: ++ reg_data |= IFE_PMC_FORCE_MDIX; ++ break; ++ case 0: ++ default: ++ reg_data |= IFE_PMC_AUTO_MDIX; ++ break; ++ } ++ ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, ++ reg_data); ++ if (ret_val) ++ goto out; ++ break; ++ default: ++ break; ++ } ++ ret_val = e1000e_setup_copper_link(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_link_up_info_ich8lan - Get current link speed and duplex ++ * @hw: pointer to the HW structure ++ * @speed: pointer to store current link speed ++ * @duplex: pointer to store the current link duplex ++ * ++ * Calls the generic get_speed_and_duplex to retrieve the current link ++ * information and then calls the Kumeran lock loss workaround for links at ++ * gigabit speeds. ++ **/ ++static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex) ++{ ++ s32 ret_val; ++ ++ ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); ++ if (ret_val) ++ goto out; ++ ++ if ((hw->mac.type == e1000_pchlan) && (*speed == SPEED_1000)) { ++ ret_val = e1000e_write_kmrn_reg(hw, ++ E1000_KMRNCTRLSTA_K1_CONFIG, ++ E1000_KMRNCTRLSTA_K1_DISABLE); ++ if (ret_val) ++ goto out; ++ } ++ ++ if ((hw->mac.type == e1000_ich8lan) && ++ (hw->phy.type == e1000_phy_igp_3) && ++ (*speed == SPEED_1000)) { ++ ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround ++ * @hw: pointer to the HW structure ++ * ++ * Work-around for 82566 Kumeran PCS lock loss: ++ * On link status change (i.e. PCI reset, speed change) and link is up and ++ * speed is gigabit- ++ * 0) if workaround is optionally disabled do nothing ++ * 1) wait 1ms for Kumeran link to come up ++ * 2) check Kumeran Diagnostic register PCS lock loss bit ++ * 3) if not set the link is locked (all is good), otherwise... ++ * 4) reset the PHY ++ * 5) repeat up to 10 times ++ * Note: this is only called for IGP3 copper when speed is 1gb. ++ **/ ++static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; ++ u32 phy_ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ u16 i, data; ++ bool link; ++ ++ if (!(dev_spec->kmrn_lock_loss_workaround_enabled)) ++ goto out; ++ ++ /* ++ * Make sure link is up before proceeding. If not just return. ++ * Attempting this while link is negotiating fouled up link ++ * stability ++ */ ++ ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); ++ if (!link) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ for (i = 0; i < 10; i++) { ++ /* read once to clear */ ++ ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); ++ if (ret_val) ++ goto out; ++ /* and again to get new status */ ++ ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); ++ if (ret_val) ++ goto out; ++ ++ /* check for PCS lock */ ++ if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ /* Issue PHY reset */ ++ e1000_phy_hw_reset(hw); ++ mdelay(5); ++ } ++ /* Disable GigE link negotiation */ ++ phy_ctrl = er32(PHY_CTRL); ++ phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | ++ E1000_PHY_CTRL_NOND0A_GBE_DISABLE); ++ ew32(PHY_CTRL, phy_ctrl); ++ ++ /* ++ * Call gig speed drop workaround on Gig disable before accessing ++ * any PHY registers ++ */ ++ e1000e_gig_downshift_workaround_ich8lan(hw); ++ ++ /* unable to acquire PCS lock */ ++ ret_val = -E1000_ERR_PHY; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state ++ * @hw: pointer to the HW structure ++ * @state: boolean value used to set the current Kumeran workaround state ++ * ++ * If ICH8, set the current Kumeran workaround state (enabled - true ++ * /disabled - false). ++ **/ ++void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, ++ bool state) ++{ ++ struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; ++ ++ if (hw->mac.type != e1000_ich8lan) { ++ e_dbg("Workaround applies to ICH8 only.\n"); ++ return; ++ } ++ ++ dev_spec->kmrn_lock_loss_workaround_enabled = state; ++ ++ return; ++} ++ ++/** ++ * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 ++ * @hw: pointer to the HW structure ++ * ++ * Workaround for 82566 power-down on D3 entry: ++ * 1) disable gigabit link ++ * 2) write VR power-down enable ++ * 3) read it back ++ * Continue if successful, else issue LCD reset and repeat ++ **/ ++void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) ++{ ++ u32 reg; ++ u16 data; ++ u8 retry = 0; ++ ++ if (hw->phy.type != e1000_phy_igp_3) ++ goto out; ++ ++ /* Try the workaround twice (if needed) */ ++ do { ++ /* Disable link */ ++ reg = er32(PHY_CTRL); ++ reg |= (E1000_PHY_CTRL_GBE_DISABLE | ++ E1000_PHY_CTRL_NOND0A_GBE_DISABLE); ++ ew32(PHY_CTRL, reg); ++ ++ /* ++ * Call gig speed drop workaround on Gig disable before ++ * accessing any PHY registers ++ */ ++ if (hw->mac.type == e1000_ich8lan) ++ e1000e_gig_downshift_workaround_ich8lan(hw); ++ ++ /* Write VR power-down enable */ ++ e1e_rphy(hw, IGP3_VR_CTRL, &data); ++ data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; ++ e1e_wphy(hw, IGP3_VR_CTRL, ++ data | IGP3_VR_CTRL_MODE_SHUTDOWN); ++ ++ /* Read it back and test */ ++ e1e_rphy(hw, IGP3_VR_CTRL, &data); ++ data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; ++ if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) ++ break; ++ ++ /* Issue PHY reset and repeat at most one more time */ ++ reg = er32(CTRL); ++ ew32(CTRL, reg | E1000_CTRL_PHY_RST); ++ retry++; ++ } while (retry); ++ ++out: ++ return; ++} ++ ++/** ++ * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working ++ * @hw: pointer to the HW structure ++ * ++ * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), ++ * LPLU, Gig disable, MDIC PHY reset): ++ * 1) Set Kumeran Near-end loopback ++ * 2) Clear Kumeran Near-end loopback ++ * Should only be called for ICH8[m] devices with IGP_3 Phy. ++ **/ ++void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 reg_data; ++ ++ if ((hw->mac.type != e1000_ich8lan) || ++ (hw->phy.type != e1000_phy_igp_3)) ++ goto out; ++ ++ ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, ++ ®_data); ++ if (ret_val) ++ goto out; ++ reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; ++ ret_val = e1000e_write_kmrn_reg(hw, ++ E1000_KMRNCTRLSTA_DIAG_OFFSET, ++ reg_data); ++ if (ret_val) ++ goto out; ++ reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; ++ ret_val = e1000e_write_kmrn_reg(hw, ++ E1000_KMRNCTRLSTA_DIAG_OFFSET, ++ reg_data); ++out: ++ return; ++} ++ ++/** ++ * e1000e_disable_gig_wol_ich8lan - disable gig during WoL ++ * @hw: pointer to the HW structure ++ * ++ * During S0 to Sx transition, it is possible the link remains at gig ++ * instead of negotiating to a lower speed. Before going to Sx, set ++ * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation ++ * to a lower speed. ++ * ++ * Should only be called for applicable parts. ++ **/ ++void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) ++{ ++ u32 phy_ctrl; ++ ++ switch (hw->mac.type) { ++ case e1000_ich9lan: ++ case e1000_ich10lan: ++ case e1000_pchlan: ++ phy_ctrl = er32(PHY_CTRL); ++ phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | ++ E1000_PHY_CTRL_GBE_DISABLE; ++ ew32(PHY_CTRL, phy_ctrl); ++ ++ /* Workaround SWFLAG unexpectedly set during S0->Sx */ ++ if (hw->mac.type == e1000_pchlan) ++ udelay(500); ++ default: ++ break; ++ } ++ ++ return; ++} ++ ++/** ++ * e1000_cleanup_led_ich8lan - Restore the default LED operation ++ * @hw: pointer to the HW structure ++ * ++ * Return the LED back to the default configuration. ++ **/ ++static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->phy.type == e1000_phy_ife) ++ ret_val = e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, ++ 0); ++ else ++ ew32(LEDCTL, hw->mac.ledctl_default); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_led_on_ich8lan - Turn LEDs on ++ * @hw: pointer to the HW structure ++ * ++ * Turn on the LEDs. ++ **/ ++static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->phy.type == e1000_phy_ife) ++ ret_val = e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, ++ (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); ++ else ++ ew32(LEDCTL, hw->mac.ledctl_mode2); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_led_off_ich8lan - Turn LEDs off ++ * @hw: pointer to the HW structure ++ * ++ * Turn off the LEDs. ++ **/ ++static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->phy.type == e1000_phy_ife) ++ ret_val = e1e_wphy(hw, ++ IFE_PHY_SPECIAL_CONTROL_LED, ++ (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); ++ else ++ ew32(LEDCTL, hw->mac.ledctl_mode1); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_led_pchlan - Configures SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * This prepares the SW controllable LED for use. ++ **/ ++static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) ++{ ++ return e1e_wphy(hw, HV_LED_CONFIG, ++ (u16)hw->mac.ledctl_mode1); ++} ++ ++/** ++ * e1000_cleanup_led_pchlan - Restore the default LED operation ++ * @hw: pointer to the HW structure ++ * ++ * Return the LED back to the default configuration. ++ **/ ++static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) ++{ ++ return e1e_wphy(hw, HV_LED_CONFIG, ++ (u16)hw->mac.ledctl_default); ++} ++ ++/** ++ * e1000_led_on_pchlan - Turn LEDs on ++ * @hw: pointer to the HW structure ++ * ++ * Turn on the LEDs. ++ **/ ++static s32 e1000_led_on_pchlan(struct e1000_hw *hw) ++{ ++ u16 data = (u16)hw->mac.ledctl_mode2; ++ u32 i, led; ++ ++ /* ++ * If no link, then turn LED on by setting the invert bit ++ * for each LED that's mode is "link_up" in ledctl_mode2. ++ */ ++ if (!(er32(STATUS) & E1000_STATUS_LU)) { ++ for (i = 0; i < 3; i++) { ++ led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; ++ if ((led & E1000_PHY_LED0_MODE_MASK) != ++ E1000_LEDCTL_MODE_LINK_UP) ++ continue; ++ if (led & E1000_PHY_LED0_IVRT) ++ data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); ++ else ++ data |= (E1000_PHY_LED0_IVRT << (i * 5)); ++ } ++ } ++ ++ return e1e_wphy(hw, HV_LED_CONFIG, data); ++} ++ ++/** ++ * e1000_led_off_pchlan - Turn LEDs off ++ * @hw: pointer to the HW structure ++ * ++ * Turn off the LEDs. ++ **/ ++static s32 e1000_led_off_pchlan(struct e1000_hw *hw) ++{ ++ u16 data = (u16)hw->mac.ledctl_mode1; ++ u32 i, led; ++ ++ /* ++ * If no link, then turn LED off by clearing the invert bit ++ * for each LED that's mode is "link_up" in ledctl_mode1. ++ */ ++ if (!(er32(STATUS) & E1000_STATUS_LU)) { ++ for (i = 0; i < 3; i++) { ++ led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; ++ if ((led & E1000_PHY_LED0_MODE_MASK) != ++ E1000_LEDCTL_MODE_LINK_UP) ++ continue; ++ if (led & E1000_PHY_LED0_IVRT) ++ data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); ++ else ++ data |= (E1000_PHY_LED0_IVRT << (i * 5)); ++ } ++ } ++ ++ return e1e_wphy(hw, HV_LED_CONFIG, data); ++} ++ ++/** ++ * e1000_get_cfg_done_ich8lan - Read config done bit ++ * @hw: pointer to the HW structure ++ * ++ * Read the management control register for the config done bit for ++ * completion status. NOTE: silicon which is EEPROM-less will fail trying ++ * to read the config done bit, so an error is *ONLY* logged and returns ++ * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon ++ * would not be able to be reset or change link. ++ **/ ++static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u32 bank = 0; ++ ++ if (hw->mac.type >= e1000_pchlan) { ++ u32 status = er32(STATUS); ++ ++ if (status & E1000_STATUS_PHYRA) { ++ ew32(STATUS, status & ++ ~E1000_STATUS_PHYRA); ++ } else ++ e_dbg("PHY Reset Asserted not set - needs delay\n"); ++ } ++ ++ e1000e_get_cfg_done(hw); ++ ++ /* If EEPROM is not marked present, init the IGP 3 PHY manually */ ++ if ((hw->mac.type != e1000_ich10lan) && ++ (hw->mac.type != e1000_pchlan)) { ++ if (((er32(EECD) & E1000_EECD_PRES) == 0) && ++ (hw->phy.type == e1000_phy_igp_3)) { ++ e1000_phy_init_script_igp3(hw); ++ } ++ } else { ++ if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { ++ /* Maybe we should do a basic PHY config */ ++ e_dbg("EEPROM not present\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ } ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down ++ * @hw: pointer to the HW structure ++ * ++ * In the case of a PHY power down to save power, or to turn off link during a ++ * driver unload, or wake on lan is not enabled, remove the link. ++ **/ ++static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) ++{ ++ /* If the management interface is not enabled, then power down */ ++ if (!(hw->mac.ops.check_mng_mode(hw) || ++ e1000_check_reset_block(hw))) ++ e1000_power_down_phy_copper(hw); ++ ++ return; ++} ++ ++/** ++ * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters ++ * @hw: pointer to the HW structure ++ * ++ * Clears hardware counters specific to the silicon family and calls ++ * clear_hw_cntrs_generic to clear all general purpose counters. ++ **/ ++static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) ++{ ++ u16 phy_data; ++ ++ e1000e_clear_hw_cntrs_base(hw); ++ ++ er32(ALGNERRC); ++ er32(RXERRC); ++ er32(TNCRS); ++ er32(CEXTERR); ++ er32(TSCTC); ++ er32(TSCTFC); ++ ++ er32(MGTPRC); ++ er32(MGTPDC); ++ er32(MGTPTC); ++ ++ er32(IAC); ++ er32(ICRXOC); ++ ++ /* Clear PHY statistics registers */ ++ if ((hw->phy.type == e1000_phy_82578) || ++ (hw->phy.type == e1000_phy_82577)) { ++ e1e_rphy(hw, HV_SCC_UPPER, &phy_data); ++ e1e_rphy(hw, HV_SCC_LOWER, &phy_data); ++ e1e_rphy(hw, HV_ECOL_UPPER, &phy_data); ++ e1e_rphy(hw, HV_ECOL_LOWER, &phy_data); ++ e1e_rphy(hw, HV_MCC_UPPER, &phy_data); ++ e1e_rphy(hw, HV_MCC_LOWER, &phy_data); ++ e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data); ++ e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data); ++ e1e_rphy(hw, HV_COLC_UPPER, &phy_data); ++ e1e_rphy(hw, HV_COLC_LOWER, &phy_data); ++ e1e_rphy(hw, HV_DC_UPPER, &phy_data); ++ e1e_rphy(hw, HV_DC_LOWER, &phy_data); ++ e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data); ++ e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data); ++ } ++} ++ +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_ich8lan.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_ich8lan.h Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,167 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_ICH8LAN_H_ ++#define _E1000_ICH8LAN_H_ ++ ++#define ICH_FLASH_GFPREG 0x0000 ++#define ICH_FLASH_HSFSTS 0x0004 ++#define ICH_FLASH_HSFCTL 0x0006 ++#define ICH_FLASH_FADDR 0x0008 ++#define ICH_FLASH_FDATA0 0x0010 ++ ++/* Requires up to 10 seconds when MNG might be accessing part. */ ++#define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000 ++#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 ++#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 ++#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF ++#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 ++ ++#define ICH_CYCLE_READ 0 ++#define ICH_CYCLE_WRITE 2 ++#define ICH_CYCLE_ERASE 3 ++ ++#define FLASH_GFPREG_BASE_MASK 0x1FFF ++#define FLASH_SECTOR_ADDR_SHIFT 12 ++ ++#define ICH_FLASH_SEG_SIZE_256 256 ++#define ICH_FLASH_SEG_SIZE_4K 4096 ++#define ICH_FLASH_SEG_SIZE_8K 8192 ++#define ICH_FLASH_SEG_SIZE_64K 65536 ++#define ICH_FLASH_SECTOR_SIZE 4096 ++ ++#define ICH_FLASH_REG_MAPSIZE 0x00A0 ++ ++#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ ++#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */ ++/* FW established a valid mode */ ++#define E1000_ICH_FWSM_FW_VALID 0x00008000 ++ ++#define E1000_ICH_MNG_IAMT_MODE 0x2 ++ ++#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ ++ (ID_LED_OFF1_OFF2 << 8) | \ ++ (ID_LED_OFF1_ON2 << 4) | \ ++ (ID_LED_DEF1_DEF2)) ++ ++#define E1000_ICH_NVM_SIG_WORD 0x13 ++#define E1000_ICH_NVM_SIG_MASK 0xC000 ++#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 ++#define E1000_ICH_NVM_SIG_VALUE 0x80 ++ ++#define E1000_ICH8_LAN_INIT_TIMEOUT 1500 ++ ++#define E1000_FEXTNVM_SW_CONFIG 1 ++#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */ ++ ++#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL ++ ++#define E1000_ICH_RAR_ENTRIES 7 ++ ++#define PHY_PAGE_SHIFT 5 ++#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ ++ ((reg) & MAX_PHY_REG_ADDRESS)) ++#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ ++#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ ++#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */ ++#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */ ++ ++#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 ++#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 ++#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 ++#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020 ++ ++/* PHY Wakeup Registers and defines */ ++#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) ++#define BM_WUC PHY_REG(BM_WUC_PAGE, 1) ++#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) ++#define BM_WUS PHY_REG(BM_WUC_PAGE, 3) ++#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) ++#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) ++#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) ++#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) ++#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) ++ ++#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ ++#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ ++#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ ++#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ ++#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ ++#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ ++#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ ++ ++#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ ++#define HV_MUX_DATA_CTRL PHY_REG(776, 16) ++#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 ++#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 ++#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */ ++#define HV_SCC_LOWER PHY_REG(778, 17) ++#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */ ++#define HV_ECOL_LOWER PHY_REG(778, 19) ++#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */ ++#define HV_MCC_LOWER PHY_REG(778, 21) ++#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */ ++#define HV_LATECOL_LOWER PHY_REG(778, 24) ++#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */ ++#define HV_COLC_LOWER PHY_REG(778, 26) ++#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */ ++#define HV_DC_LOWER PHY_REG(778, 28) ++#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ ++#define HV_TNCRS_LOWER PHY_REG(778, 30) ++ ++/* ++ * Additional interrupts need to be handled for ICH family: ++ * DSW = The FW changed the status of the DISSW bit in FWSM ++ * PHYINT = The LAN connected device generates an interrupt ++ * EPRST = Manageability reset event ++ */ ++#define IMS_ICH_ENABLE_MASK (\ ++ E1000_IMS_DSW | \ ++ E1000_IMS_PHYINT | \ ++ E1000_IMS_EPRST) ++ ++/* Additional interrupt register bit definitions */ ++#define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */ ++#define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */ ++#define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */ ++ ++/* Security Processing bit Indication */ ++#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000 ++#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000 ++#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000 ++#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000 ++#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000 ++ ++ ++void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, ++ bool state); ++void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); ++void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); ++void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw); ++ ++#endif +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_mac.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_mac.c Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,1864 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000.h" ++ ++static u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr); ++static s32 e1000_set_default_fc_generic(struct e1000_hw *hw); ++static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw); ++static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw); ++static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); ++static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); ++ ++/** ++ * e1000_init_mac_ops_generic - Initialize MAC function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Setups up the function pointers to no-op functions ++ **/ ++void e1000_init_mac_ops_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ /* General Setup */ ++ mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; ++ mac->ops.read_mac_addr = e1000e_read_mac_addr_generic; ++ mac->ops.config_collision_dist = e1000e_config_collision_dist; ++ /* LINK */ ++ mac->ops.wait_autoneg = e1000_wait_autoneg; ++ /* Management */ ++ mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; ++ mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; ++ mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; ++ /* VLAN, MC, etc. */ ++ mac->ops.rar_set = e1000e_rar_set; ++ mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; ++} ++ ++/** ++ * e1000e_get_bus_info_pcie - Get PCIe bus information ++ * @hw: pointer to the HW structure ++ * ++ * Determines and stores the system bus information for a particular ++ * network interface. The following bus information is determined and stored: ++ * bus speed, bus width, type (PCIe), and PCIe function. ++ **/ ++s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ struct e1000_bus_info *bus = &hw->bus; ++ ++ s32 ret_val; ++ u16 pcie_link_status; ++ ++ bus->type = e1000_bus_type_pci_express; ++ bus->speed = e1000_bus_speed_2500; ++ ++ ret_val = e1000_read_pcie_cap_reg(hw, ++ PCIE_LINK_STATUS, ++ &pcie_link_status); ++ if (ret_val) ++ bus->width = e1000_bus_width_unknown; ++ else ++ bus->width = (enum e1000_bus_width)((pcie_link_status & ++ PCIE_LINK_WIDTH_MASK) >> ++ PCIE_LINK_WIDTH_SHIFT); ++ ++ mac->ops.set_lan_id(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices ++ * ++ * @hw: pointer to the HW structure ++ * ++ * Determines the LAN function id by reading memory-mapped registers ++ * and swaps the port value if requested. ++ **/ ++static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) ++{ ++ struct e1000_bus_info *bus = &hw->bus; ++ u32 reg; ++ ++ /* ++ * The status register reports the correct function number ++ * for the device regardless of function swap state. ++ */ ++ reg = er32(STATUS); ++ bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; ++} ++ ++/** ++ * e1000_set_lan_id_single_port - Set LAN id for a single port device ++ * @hw: pointer to the HW structure ++ * ++ * Sets the LAN function id to zero for a single port device. ++ **/ ++void e1000_set_lan_id_single_port(struct e1000_hw *hw) ++{ ++ struct e1000_bus_info *bus = &hw->bus; ++ ++ bus->func = 0; ++} ++ ++/** ++ * e1000e_clear_vfta_generic - Clear VLAN filter table ++ * @hw: pointer to the HW structure ++ * ++ * Clears the register array which contains the VLAN filter table by ++ * setting all the values to 0. ++ **/ ++void e1000e_clear_vfta_generic(struct e1000_hw *hw) ++{ ++ u32 offset; ++ ++ for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { ++ E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); ++ e1e_flush(); ++ } ++} ++ ++/** ++ * e1000e_write_vfta_generic - Write value to VLAN filter table ++ * @hw: pointer to the HW structure ++ * @offset: register offset in VLAN filter table ++ * @value: register value written to VLAN filter table ++ * ++ * Writes value at the given offset in the register array which stores ++ * the VLAN filter table. ++ **/ ++void e1000e_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) ++{ ++ E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); ++ e1e_flush(); ++} ++ ++/** ++ * e1000e_init_rx_addrs - Initialize receive address's ++ * @hw: pointer to the HW structure ++ * @rar_count: receive address registers ++ * ++ * Setups the receive address registers by setting the base receive address ++ * register to the devices MAC address and clearing all the other receive ++ * address registers to 0. ++ **/ ++void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) ++{ ++ u32 i; ++ u8 mac_addr[ETH_ADDR_LEN] = {0}; ++ ++ /* Setup the receive address */ ++ e_dbg("Programming MAC Address into RAR[0]\n"); ++ ++ hw->mac.ops.rar_set(hw, hw->mac.addr, 0); ++ ++ /* Zero out the other (rar_entry_count - 1) receive addresses */ ++ e_dbg("Clearing RAR[1-%u]\n", rar_count-1); ++ for (i = 1; i < rar_count; i++) ++ hw->mac.ops.rar_set(hw, mac_addr, i); ++} ++ ++/** ++ * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr ++ * @hw: pointer to the HW structure ++ * ++ * Checks the nvm for an alternate MAC address. An alternate MAC address ++ * can be setup by pre-boot software and must be treated like a permanent ++ * address and must override the actual permanent MAC address. If an ++ * alternate MAC address is found it is programmed into RAR0, replacing ++ * the permanent address that was installed into RAR0 by the Si on reset. ++ * This function will return SUCCESS unless it encounters an error while ++ * reading the EEPROM. ++ **/ ++s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) ++{ ++ u32 i; ++ s32 ret_val = E1000_SUCCESS; ++ u16 offset, nvm_alt_mac_addr_offset, nvm_data; ++ u8 alt_mac_addr[ETH_ADDR_LEN]; ++ ++ ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, ++ &nvm_alt_mac_addr_offset); ++ if (ret_val) { ++ e_dbg("NVM Read Error\n"); ++ goto out; ++ } ++ ++ if (nvm_alt_mac_addr_offset == 0xFFFF) { ++ /* There is no Alternate MAC Address */ ++ goto out; ++ } ++ ++ if (hw->bus.func == E1000_FUNC_1) ++ nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; ++ for (i = 0; i < ETH_ADDR_LEN; i += 2) { ++ offset = nvm_alt_mac_addr_offset + (i >> 1); ++ ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); ++ if (ret_val) { ++ e_dbg("NVM Read Error\n"); ++ goto out; ++ } ++ ++ alt_mac_addr[i] = (u8)(nvm_data & 0xFF); ++ alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); ++ } ++ ++ /* if multicast bit is set, the alternate address will not be used */ ++ if (alt_mac_addr[0] & 0x01) { ++ e_dbg("Ignoring Alternate Mac Address with MC bit set\n"); ++ goto out; ++ } ++ ++ /* ++ * We have a valid alternate MAC address, and we want to treat it the ++ * same as the normal permanent MAC address stored by the HW into the ++ * RAR. Do this by mapping this address into RAR0. ++ */ ++ hw->mac.ops.rar_set(hw, alt_mac_addr, 0); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_rar_set - Set receive address register ++ * @hw: pointer to the HW structure ++ * @addr: pointer to the receive address ++ * @index: receive address array register ++ * ++ * Sets the receive address array register at index to the address passed ++ * in by addr. ++ **/ ++void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) ++{ ++ u32 rar_low, rar_high; ++ ++ /* ++ * HW expects these in little endian so we reverse the byte order ++ * from network order (big endian) to little endian ++ */ ++ rar_low = ((u32) addr[0] | ++ ((u32) addr[1] << 8) | ++ ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); ++ ++ rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); ++ ++ /* If MAC address zero, no need to set the AV bit */ ++ if (rar_low || rar_high) ++ rar_high |= E1000_RAH_AV; ++ ++ /* ++ * Some bridges will combine consecutive 32-bit writes into ++ * a single burst write, which will malfunction on some parts. ++ * The flushes avoid this. ++ */ ++ ew32(RAL(index), rar_low); ++ e1e_flush(); ++ ew32(RAH(index), rar_high); ++ e1e_flush(); ++} ++ ++/** ++ * e1000_mta_set_generic - Set multicast filter table address ++ * @hw: pointer to the HW structure ++ * @hash_value: determines the MTA register and bit to set ++ * ++ * The multicast table address is a register array of 32-bit registers. ++ * The hash_value is used to determine what register the bit is in, the ++ * current value is read, the new bit is OR'd in and the new value is ++ * written back into the register. ++ **/ ++void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) ++{ ++ u32 hash_bit, hash_reg, mta; ++ ++ /* ++ * The MTA is a register array of 32-bit registers. It is ++ * treated like an array of (32*mta_reg_count) bits. We want to ++ * set bit BitArray[hash_value]. So we figure out what register ++ * the bit is in, read it, OR in the new bit, then write ++ * back the new value. The (hw->mac.mta_reg_count - 1) serves as a ++ * mask to bits 31:5 of the hash value which gives us the ++ * register we're modifying. The hash bit within that register ++ * is determined by the lower 5 bits of the hash value. ++ */ ++ hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); ++ hash_bit = hash_value & 0x1F; ++ ++ mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); ++ ++ mta |= (1 << hash_bit); ++ ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); ++ e1e_flush(); ++} ++ ++/** ++ * e1000e_update_mc_addr_list_generic - Update Multicast addresses ++ * @hw: pointer to the HW structure ++ * @mc_addr_list: array of multicast addresses to program ++ * @mc_addr_count: number of multicast addresses to program ++ * ++ * Updates entire Multicast Table Array. ++ * The caller must have a packed mc_addr_list of multicast addresses. ++ **/ ++void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, ++ u8 *mc_addr_list, u32 mc_addr_count) ++{ ++ u32 hash_value, hash_bit, hash_reg; ++ int i; ++ ++ /* clear mta_shadow */ ++ memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); ++ ++ /* update mta_shadow from mc_addr_list */ ++ for (i = 0; (u32) i < mc_addr_count; i++) { ++ hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); ++ ++ hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); ++ hash_bit = hash_value & 0x1F; ++ ++ hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); ++ mc_addr_list += (ETH_ADDR_LEN); ++ } ++ ++ /* replace the entire MTA table */ ++ for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); ++ e1e_flush(); ++} ++ ++/** ++ * e1000_hash_mc_addr_generic - Generate a multicast hash value ++ * @hw: pointer to the HW structure ++ * @mc_addr: pointer to a multicast address ++ * ++ * Generates a multicast address hash value which is used to determine ++ * the multicast filter table array address and new table value. See ++ * e1000_mta_set_generic() ++ **/ ++static u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) ++{ ++ u32 hash_value, hash_mask; ++ u8 bit_shift = 0; ++ ++ /* Register count multiplied by bits per register */ ++ hash_mask = (hw->mac.mta_reg_count * 32) - 1; ++ ++ /* ++ * For a mc_filter_type of 0, bit_shift is the number of left-shifts ++ * where 0xFF would still fall within the hash mask. ++ */ ++ while (hash_mask >> bit_shift != 0xFF) ++ bit_shift++; ++ ++ /* ++ * The portion of the address that is used for the hash table ++ * is determined by the mc_filter_type setting. ++ * The algorithm is such that there is a total of 8 bits of shifting. ++ * The bit_shift for a mc_filter_type of 0 represents the number of ++ * left-shifts where the MSB of mc_addr[5] would still fall within ++ * the hash_mask. Case 0 does this exactly. Since there are a total ++ * of 8 bits of shifting, then mc_addr[4] will shift right the ++ * remaining number of bits. Thus 8 - bit_shift. The rest of the ++ * cases are a variation of this algorithm...essentially raising the ++ * number of bits to shift mc_addr[5] left, while still keeping the ++ * 8-bit shifting total. ++ * ++ * For example, given the following Destination MAC Address and an ++ * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), ++ * we can see that the bit_shift for case 0 is 4. These are the hash ++ * values resulting from each mc_filter_type... ++ * [0] [1] [2] [3] [4] [5] ++ * 01 AA 00 12 34 56 ++ * LSB MSB ++ * ++ * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 ++ * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 ++ * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 ++ * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 ++ */ ++ switch (hw->mac.mc_filter_type) { ++ default: ++ case 0: ++ break; ++ case 1: ++ bit_shift += 1; ++ break; ++ case 2: ++ bit_shift += 2; ++ break; ++ case 3: ++ bit_shift += 4; ++ break; ++ } ++ ++ hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | ++ (((u16) mc_addr[5]) << bit_shift))); ++ ++ return hash_value; ++} ++ ++/** ++ * e1000e_clear_hw_cntrs_base - Clear base hardware counters ++ * @hw: pointer to the HW structure ++ * ++ * Clears the base hardware counters by reading the counter registers. ++ **/ ++void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw) ++{ ++ er32(CRCERRS); ++ er32(SYMERRS); ++ er32(MPC); ++ er32(SCC); ++ er32(ECOL); ++ er32(MCC); ++ er32(LATECOL); ++ er32(COLC); ++ er32(DC); ++ er32(SEC); ++ er32(RLEC); ++ er32(XONRXC); ++ er32(XONTXC); ++ er32(XOFFRXC); ++ er32(XOFFTXC); ++ er32(FCRUC); ++ er32(GPRC); ++ er32(BPRC); ++ er32(MPRC); ++ er32(GPTC); ++ er32(GORCL); ++ er32(GORCH); ++ er32(GOTCL); ++ er32(GOTCH); ++ er32(RNBC); ++ er32(RUC); ++ er32(RFC); ++ er32(ROC); ++ er32(RJC); ++ er32(TORL); ++ er32(TORH); ++ er32(TOTL); ++ er32(TOTH); ++ er32(TPR); ++ er32(TPT); ++ er32(MPTC); ++ er32(BPTC); ++} ++/** ++ * e1000e_check_for_copper_link - Check for link (Copper) ++ * @hw: pointer to the HW structure ++ * ++ * Checks to see of the link status of the hardware has changed. If a ++ * change in link status has been detected, then we read the PHY registers ++ * to get the current speed/duplex if link exists. ++ **/ ++s32 e1000e_check_for_copper_link(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val; ++ bool link; ++ ++ /* ++ * We only want to go out to the PHY registers to see if Auto-Neg ++ * has completed and/or if our link status has changed. The ++ * get_link_status flag is set upon receiving a Link Status ++ * Change or Rx Sequence Error interrupt. ++ */ ++ if (!mac->get_link_status) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ /* ++ * First we want to see if the MII Status Register reports ++ * link. If so, then we want to get the current speed/duplex ++ * of the PHY. ++ */ ++ ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) ++ goto out; /* No link detected */ ++ ++ mac->get_link_status = false; ++ ++ /* ++ * Check if there was DownShift, must be checked ++ * immediately after link-up ++ */ ++ e1000e_check_downshift(hw); ++ ++ /* ++ * If we are forcing speed/duplex, then we simply return since ++ * we have already determined whether we have link or not. ++ */ ++ if (!mac->autoneg) { ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ /* ++ * Auto-Neg is enabled. Auto Speed Detection takes care ++ * of MAC speed/duplex configuration. So we only need to ++ * configure Collision Distance in the MAC. ++ */ ++ e1000e_config_collision_dist(hw); ++ ++ /* ++ * Configure Flow Control now that Auto-Neg has completed. ++ * First, we need to restore the desired flow control ++ * settings because we may have had to re-autoneg with a ++ * different link partner. ++ */ ++ ret_val = e1000e_config_fc_after_link_up(hw); ++ if (ret_val) ++ e_dbg("Error configuring flow control\n"); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_check_for_fiber_link - Check for link (Fiber) ++ * @hw: pointer to the HW structure ++ * ++ * Checks for link up on the hardware. If link is not up and we have ++ * a signal, then we need to force link up. ++ **/ ++s32 e1000e_check_for_fiber_link(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 rxcw; ++ u32 ctrl; ++ u32 status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ctrl = er32(CTRL); ++ status = er32(STATUS); ++ rxcw = er32(RXCW); ++ ++ /* ++ * If we don't have link (auto-negotiation failed or link partner ++ * cannot auto-negotiate), the cable is plugged in (we have signal), ++ * and our link partner is not trying to auto-negotiate with us (we ++ * are receiving idles or data), we need to force link up. We also ++ * need to give auto-negotiation time to complete, in case the cable ++ * was just plugged in. The autoneg_failed flag does this. ++ */ ++ /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ ++ if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && ++ (!(rxcw & E1000_RXCW_C))) { ++ if (mac->autoneg_failed == 0) { ++ mac->autoneg_failed = 1; ++ goto out; ++ } ++ e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); ++ ++ /* Disable auto-negotiation in the TXCW register */ ++ ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); ++ ++ /* Force link-up and also force full-duplex. */ ++ ctrl = er32(CTRL); ++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); ++ ew32(CTRL, ctrl); ++ ++ /* Configure Flow Control after forcing link up. */ ++ ret_val = e1000e_config_fc_after_link_up(hw); ++ if (ret_val) { ++ e_dbg("Error configuring flow control\n"); ++ goto out; ++ } ++ } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { ++ /* ++ * If we are forcing link and we are receiving /C/ ordered ++ * sets, re-enable auto-negotiation in the TXCW register ++ * and disable forced link in the Device Control register ++ * in an attempt to auto-negotiate with our link partner. ++ */ ++ e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); ++ ew32(TXCW, mac->txcw); ++ ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); ++ ++ mac->serdes_has_link = true; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_check_for_serdes_link - Check for link (Serdes) ++ * @hw: pointer to the HW structure ++ * ++ * Checks for link up on the hardware. If link is not up and we have ++ * a signal, then we need to force link up. ++ **/ ++s32 e1000e_check_for_serdes_link(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 rxcw; ++ u32 ctrl; ++ u32 status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ctrl = er32(CTRL); ++ status = er32(STATUS); ++ rxcw = er32(RXCW); ++ ++ /* ++ * If we don't have link (auto-negotiation failed or link partner ++ * cannot auto-negotiate), and our link partner is not trying to ++ * auto-negotiate with us (we are receiving idles or data), ++ * we need to force link up. We also need to give auto-negotiation ++ * time to complete. ++ */ ++ /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ ++ if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { ++ if (mac->autoneg_failed == 0) { ++ mac->autoneg_failed = 1; ++ goto out; ++ } ++ e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); ++ ++ /* Disable auto-negotiation in the TXCW register */ ++ ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); ++ ++ /* Force link-up and also force full-duplex. */ ++ ctrl = er32(CTRL); ++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); ++ ew32(CTRL, ctrl); ++ ++ /* Configure Flow Control after forcing link up. */ ++ ret_val = e1000e_config_fc_after_link_up(hw); ++ if (ret_val) { ++ e_dbg("Error configuring flow control\n"); ++ goto out; ++ } ++ } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { ++ /* ++ * If we are forcing link and we are receiving /C/ ordered ++ * sets, re-enable auto-negotiation in the TXCW register ++ * and disable forced link in the Device Control register ++ * in an attempt to auto-negotiate with our link partner. ++ */ ++ e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); ++ ew32(TXCW, mac->txcw); ++ ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); ++ ++ mac->serdes_has_link = true; ++ } else if (!(E1000_TXCW_ANE & er32(TXCW))) { ++ /* ++ * If we force link for non-auto-negotiation switch, check ++ * link status based on MAC synchronization for internal ++ * serdes media type. ++ */ ++ /* SYNCH bit and IV bit are sticky. */ ++ udelay(10); ++ rxcw = er32(RXCW); ++ if (rxcw & E1000_RXCW_SYNCH) { ++ if (!(rxcw & E1000_RXCW_IV)) { ++ mac->serdes_has_link = true; ++ e_dbg("SERDES: Link up - forced.\n"); ++ } ++ } else { ++ mac->serdes_has_link = false; ++ e_dbg("SERDES: Link down - force failed.\n"); ++ } ++ } ++ ++ if (E1000_TXCW_ANE & er32(TXCW)) { ++ status = er32(STATUS); ++ if (status & E1000_STATUS_LU) { ++ /* SYNCH bit and IV bit are sticky, so reread rxcw. */ ++ udelay(10); ++ rxcw = er32(RXCW); ++ if (rxcw & E1000_RXCW_SYNCH) { ++ if (!(rxcw & E1000_RXCW_IV)) { ++ mac->serdes_has_link = true; ++ e_dbg("SERDES: Link up - autoneg " ++ "completed sucessfully.\n"); ++ } else { ++ mac->serdes_has_link = false; ++ e_dbg("SERDES: Link down - invalid" ++ "codewords detected in autoneg.\n"); ++ } ++ } else { ++ mac->serdes_has_link = false; ++ e_dbg("SERDES: Link down - no sync.\n"); ++ } ++ } else { ++ mac->serdes_has_link = false; ++ e_dbg("SERDES: Link down - autoneg failed\n"); ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_setup_link - Setup flow control and link settings ++ * @hw: pointer to the HW structure ++ * ++ * Determines which flow control settings to use, then configures flow ++ * control. Calls the appropriate media-specific link configuration ++ * function. Assuming the adapter has a valid link partner, a valid link ++ * should be established. Assumes the hardware has previously been reset ++ * and the transmitter and receiver are not enabled. ++ **/ ++s32 e1000e_setup_link(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* ++ * In the case of the phy reset being blocked, we already have a link. ++ * We do not need to set it up again. ++ */ ++ if (hw->phy.ops.check_reset_block) ++ if (e1000_check_reset_block(hw)) ++ goto out; ++ ++ /* ++ * If requested flow control is set to default, set flow control ++ * based on the EEPROM flow control settings. ++ */ ++ if (hw->fc.requested_mode == e1000_fc_default) { ++ ret_val = e1000_set_default_fc_generic(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* ++ * Save off the requested flow control mode for use later. Depending ++ * on the link partner's capabilities, we may or may not use this mode. ++ */ ++ hw->fc.current_mode = hw->fc.requested_mode; ++ ++ e_dbg("After fix-ups FlowControl is now = %x\n", ++ hw->fc.current_mode); ++ ++ /* Call the necessary media_type subroutine to configure the link. */ ++ ret_val = hw->mac.ops.setup_physical_interface(hw); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Initialize the flow control address, type, and PAUSE timer ++ * registers to their default values. This is done even if flow ++ * control is disabled, because it does not hurt anything to ++ * initialize these registers. ++ */ ++ e_dbg("Initializing the Flow Control address, type and timer regs\n"); ++ ew32(FCT, FLOW_CONTROL_TYPE); ++ ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); ++ ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); ++ ++ ew32(FCTTV, hw->fc.pause_time); ++ ++ ret_val = e1000e_set_fc_watermarks(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes ++ * @hw: pointer to the HW structure ++ * ++ * Configures collision distance and flow control for fiber and serdes ++ * links. Upon successful setup, poll for link. ++ **/ ++s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ctrl = er32(CTRL); ++ ++ /* Take the link out of reset */ ++ ctrl &= ~E1000_CTRL_LRST; ++ ++ e1000e_config_collision_dist(hw); ++ ++ ret_val = e1000_commit_fc_settings_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Since auto-negotiation is enabled, take the link out of reset (the ++ * link will be in reset, because we previously reset the chip). This ++ * will restart auto-negotiation. If auto-negotiation is successful ++ * then the link-up status bit will be set and the flow control enable ++ * bits (RFCE and TFCE) will be set according to their negotiated value. ++ */ ++ e_dbg("Auto-negotiation enabled\n"); ++ ++ ew32(CTRL, ctrl); ++ e1e_flush(); ++ msleep(1); ++ ++ /* ++ * For these adapters, the SW definable pin 1 is set when the optics ++ * detect a signal. If we have a signal, then poll for a "Link-Up" ++ * indication. ++ */ ++ if (hw->phy.media_type == e1000_media_type_internal_serdes || ++ (er32(CTRL) & E1000_CTRL_SWDPIN1)) { ++ ret_val = e1000_poll_fiber_serdes_link_generic(hw); ++ } else { ++ e_dbg("No signal detected\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_config_collision_dist - Configure collision distance ++ * @hw: pointer to the HW structure ++ * ++ * Configures the collision distance to the default value and is used ++ * during link setup. Currently no func pointer exists and all ++ * implementations are handled in the generic version of this function. ++ **/ ++void e1000e_config_collision_dist(struct e1000_hw *hw) ++{ ++ u32 tctl; ++ ++ tctl = er32(TCTL); ++ ++ tctl &= ~E1000_TCTL_COLD; ++ tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; ++ ++ ew32(TCTL, tctl); ++ e1e_flush(); ++} ++ ++/** ++ * e1000_poll_fiber_serdes_link_generic - Poll for link up ++ * @hw: pointer to the HW structure ++ * ++ * Polls for link up by reading the status register, if link fails to come ++ * up with auto-negotiation, then the link is forced if a signal is detected. ++ **/ ++static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 i, status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* ++ * If we have a signal (the cable is plugged in, or assumed true for ++ * serdes media) then poll for a "Link-Up" indication in the Device ++ * Status Register. Time-out if a link isn't seen in 500 milliseconds ++ * seconds (Auto-negotiation should complete in less than 500 ++ * milliseconds even if the other end is doing it in SW). ++ */ ++ for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { ++ msleep(10); ++ status = er32(STATUS); ++ if (status & E1000_STATUS_LU) ++ break; ++ } ++ if (i == FIBER_LINK_UP_LIMIT) { ++ e_dbg("Never got a valid link from auto-neg!!!\n"); ++ mac->autoneg_failed = 1; ++ /* ++ * AutoNeg failed to achieve a link, so we'll call ++ * mac->check_for_link. This routine will force the ++ * link up if we detect a signal. This will allow us to ++ * communicate with non-autonegotiating link partners. ++ */ ++ ret_val = hw->mac.ops.check_for_link(hw); ++ if (ret_val) { ++ e_dbg("Error while checking for link\n"); ++ goto out; ++ } ++ mac->autoneg_failed = 0; ++ } else { ++ mac->autoneg_failed = 0; ++ e_dbg("Valid Link Found\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_commit_fc_settings_generic - Configure flow control ++ * @hw: pointer to the HW structure ++ * ++ * Write the flow control settings to the Transmit Config Word Register (TXCW) ++ * base on the flow control settings in e1000_mac_info. ++ **/ ++static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 txcw; ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* ++ * Check for a software override of the flow control settings, and ++ * setup the device accordingly. If auto-negotiation is enabled, then ++ * software will have to set the "PAUSE" bits to the correct value in ++ * the Transmit Config Word Register (TXCW) and re-start auto- ++ * negotiation. However, if auto-negotiation is disabled, then ++ * software will have to manually configure the two flow control enable ++ * bits in the CTRL register. ++ * ++ * The possible values of the "fc" parameter are: ++ * 0: Flow control is completely disabled ++ * 1: Rx flow control is enabled (we can receive pause frames, ++ * but not send pause frames). ++ * 2: Tx flow control is enabled (we can send pause frames but we ++ * do not support receiving pause frames). ++ * 3: Both Rx and Tx flow control (symmetric) are enabled. ++ */ ++ switch (hw->fc.current_mode) { ++ case e1000_fc_none: ++ /* Flow control completely disabled by a software over-ride. */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); ++ break; ++ case e1000_fc_rx_pause: ++ /* ++ * Rx Flow control is enabled and Tx Flow control is disabled ++ * by a software over-ride. Since there really isn't a way to ++ * advertise that we are capable of Rx Pause ONLY, we will ++ * advertise that we support both symmetric and asymmetric RX ++ * PAUSE. Later, we will disable the adapter's ability to send ++ * PAUSE frames. ++ */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); ++ break; ++ case e1000_fc_tx_pause: ++ /* ++ * Tx Flow control is enabled, and Rx Flow control is disabled, ++ * by a software over-ride. ++ */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); ++ break; ++ case e1000_fc_full: ++ /* ++ * Flow control (both Rx and Tx) is enabled by a software ++ * over-ride. ++ */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); ++ break; ++ default: ++ e_dbg("Flow control param set incorrectly\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ break; ++ } ++ ++ ew32(TXCW, txcw); ++ mac->txcw = txcw; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_set_fc_watermarks - Set flow control high/low watermarks ++ * @hw: pointer to the HW structure ++ * ++ * Sets the flow control high/low threshold (watermark) registers. If ++ * flow control XON frame transmission is enabled, then set XON frame ++ * transmission as well. ++ **/ ++s32 e1000e_set_fc_watermarks(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u32 fcrtl = 0, fcrth = 0; ++ ++ /* ++ * Set the flow control receive threshold registers. Normally, ++ * these registers will be set to a default threshold that may be ++ * adjusted later by the driver's runtime code. However, if the ++ * ability to transmit pause frames is not enabled, then these ++ * registers will be set to 0. ++ */ ++ if (hw->fc.current_mode & e1000_fc_tx_pause) { ++ /* ++ * We need to set up the Receive Threshold high and low water ++ * marks as well as (optionally) enabling the transmission of ++ * XON frames. ++ */ ++ fcrtl = hw->fc.low_water; ++ if (hw->fc.send_xon) ++ fcrtl |= E1000_FCRTL_XONE; ++ ++ fcrth = hw->fc.high_water; ++ } ++ ew32(FCRTL, fcrtl); ++ ew32(FCRTH, fcrth); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_set_default_fc_generic - Set flow control default values ++ * @hw: pointer to the HW structure ++ * ++ * Read the EEPROM for the default values for flow control and store the ++ * values. ++ **/ ++static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 nvm_data; ++ ++ /* ++ * Read and store word 0x0F of the EEPROM. This word contains bits ++ * that determine the hardware's default PAUSE (flow control) mode, ++ * a bit that determines whether the HW defaults to enabling or ++ * disabling auto-negotiation, and the direction of the ++ * SW defined pins. If there is no SW over-ride of the flow ++ * control setting, then the variable hw->fc will ++ * be initialized based on a value in the EEPROM. ++ */ ++ ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); ++ ++ if (ret_val) { ++ e_dbg("NVM Read Error\n"); ++ goto out; ++ } ++ ++ if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) ++ hw->fc.requested_mode = e1000_fc_none; ++ else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == ++ NVM_WORD0F_ASM_DIR) ++ hw->fc.requested_mode = e1000_fc_tx_pause; ++ else ++ hw->fc.requested_mode = e1000_fc_full; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_force_mac_fc - Force the MAC's flow control settings ++ * @hw: pointer to the HW structure ++ * ++ * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the ++ * device control register to reflect the adapter settings. TFCE and RFCE ++ * need to be explicitly set by software when a copper PHY is used because ++ * autonegotiation is managed by the PHY rather than the MAC. Software must ++ * also configure these bits when link is forced on a fiber connection. ++ **/ ++s32 e1000e_force_mac_fc(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ctrl = er32(CTRL); ++ ++ /* ++ * Because we didn't get link via the internal auto-negotiation ++ * mechanism (we either forced link or we got link via PHY ++ * auto-neg), we have to manually enable/disable transmit an ++ * receive flow control. ++ * ++ * The "Case" statement below enables/disable flow control ++ * according to the "hw->fc.current_mode" parameter. ++ * ++ * The possible values of the "fc" parameter are: ++ * 0: Flow control is completely disabled ++ * 1: Rx flow control is enabled (we can receive pause ++ * frames but not send pause frames). ++ * 2: Tx flow control is enabled (we can send pause frames ++ * frames but we do not receive pause frames). ++ * 3: Both Rx and Tx flow control (symmetric) is enabled. ++ * other: No other values should be possible at this point. ++ */ ++ e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); ++ ++ switch (hw->fc.current_mode) { ++ case e1000_fc_none: ++ ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); ++ break; ++ case e1000_fc_rx_pause: ++ ctrl &= (~E1000_CTRL_TFCE); ++ ctrl |= E1000_CTRL_RFCE; ++ break; ++ case e1000_fc_tx_pause: ++ ctrl &= (~E1000_CTRL_RFCE); ++ ctrl |= E1000_CTRL_TFCE; ++ break; ++ case e1000_fc_full: ++ ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); ++ break; ++ default: ++ e_dbg("Flow control param set incorrectly\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ew32(CTRL, ctrl); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_config_fc_after_link_up - Configures flow control after link ++ * @hw: pointer to the HW structure ++ * ++ * Checks the status of auto-negotiation after link up to ensure that the ++ * speed and duplex were not forced. If the link needed to be forced, then ++ * flow control needs to be forced also. If auto-negotiation is enabled ++ * and did not fail, then we configure flow control based on our link ++ * partner. ++ **/ ++s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; ++ u16 speed, duplex; ++ ++ /* ++ * Check for the case where we have fiber media and auto-neg failed ++ * so we had to force link. In this case, we need to force the ++ * configuration of the MAC to match the "fc" parameter. ++ */ ++ if (mac->autoneg_failed) { ++ if (hw->phy.media_type == e1000_media_type_fiber || ++ hw->phy.media_type == e1000_media_type_internal_serdes) ++ ret_val = e1000e_force_mac_fc(hw); ++ } else { ++ if (hw->phy.media_type == e1000_media_type_copper) ++ ret_val = e1000e_force_mac_fc(hw); ++ } ++ ++ if (ret_val) { ++ e_dbg("Error forcing flow control settings\n"); ++ goto out; ++ } ++ ++ /* ++ * Check for the case where we have copper media and auto-neg is ++ * enabled. In this case, we need to check and see if Auto-Neg ++ * has completed, and if so, how the PHY and link partner has ++ * flow control configured. ++ */ ++ if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { ++ /* ++ * Read the MII Status Register and check to see if AutoNeg ++ * has completed. We read this twice because this reg has ++ * some "sticky" (latched) bits. ++ */ ++ ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); ++ if (ret_val) ++ goto out; ++ ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); ++ if (ret_val) ++ goto out; ++ ++ if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { ++ e_dbg("Copper PHY and Auto Neg " ++ "has not completed.\n"); ++ goto out; ++ } ++ ++ /* ++ * The AutoNeg process has completed, so we now need to ++ * read both the Auto Negotiation Advertisement ++ * Register (Address 4) and the Auto_Negotiation Base ++ * Page Ability Register (Address 5) to determine how ++ * flow control was negotiated. ++ */ ++ ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, ++ &mii_nway_adv_reg); ++ if (ret_val) ++ goto out; ++ ret_val = e1e_rphy(hw, PHY_LP_ABILITY, ++ &mii_nway_lp_ability_reg); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Two bits in the Auto Negotiation Advertisement Register ++ * (Address 4) and two bits in the Auto Negotiation Base ++ * Page Ability Register (Address 5) determine flow control ++ * for both the PHY and the link partner. The following ++ * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, ++ * 1999, describes these PAUSE resolution bits and how flow ++ * control is determined based upon these settings. ++ * NOTE: DC = Don't Care ++ * ++ * LOCAL DEVICE | LINK PARTNER ++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution ++ *-------|---------|-------|---------|-------------------- ++ * 0 | 0 | DC | DC | e1000_fc_none ++ * 0 | 1 | 0 | DC | e1000_fc_none ++ * 0 | 1 | 1 | 0 | e1000_fc_none ++ * 0 | 1 | 1 | 1 | e1000_fc_tx_pause ++ * 1 | 0 | 0 | DC | e1000_fc_none ++ * 1 | DC | 1 | DC | e1000_fc_full ++ * 1 | 1 | 0 | 0 | e1000_fc_none ++ * 1 | 1 | 0 | 1 | e1000_fc_rx_pause ++ * ++ * Are both PAUSE bits set to 1? If so, this implies ++ * Symmetric Flow Control is enabled at both ends. The ++ * ASM_DIR bits are irrelevant per the spec. ++ * ++ * For Symmetric Flow Control: ++ * ++ * LOCAL DEVICE | LINK PARTNER ++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ++ *-------|---------|-------|---------|-------------------- ++ * 1 | DC | 1 | DC | E1000_fc_full ++ * ++ */ ++ if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { ++ /* ++ * Now we need to check if the user selected Rx ONLY ++ * of pause frames. In this case, we had to advertise ++ * FULL flow control because we could not advertise RX ++ * ONLY. Hence, we must now check to see if we need to ++ * turn OFF the TRANSMISSION of PAUSE frames. ++ */ ++ if (hw->fc.requested_mode == e1000_fc_full) { ++ hw->fc.current_mode = e1000_fc_full; ++ e_dbg("Flow Control = FULL.\r\n"); ++ } else { ++ hw->fc.current_mode = e1000_fc_rx_pause; ++ e_dbg("Flow Control = " ++ "RX PAUSE frames only.\r\n"); ++ } ++ } ++ /* ++ * For receiving PAUSE frames ONLY. ++ * ++ * LOCAL DEVICE | LINK PARTNER ++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ++ *-------|---------|-------|---------|-------------------- ++ * 0 | 1 | 1 | 1 | e1000_fc_tx_pause ++ */ ++ else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && ++ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { ++ hw->fc.current_mode = e1000_fc_tx_pause; ++ e_dbg("Flow Control = TX PAUSE frames only.\r\n"); ++ } ++ /* ++ * For transmitting PAUSE frames ONLY. ++ * ++ * LOCAL DEVICE | LINK PARTNER ++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ++ *-------|---------|-------|---------|-------------------- ++ * 1 | 1 | 0 | 1 | e1000_fc_rx_pause ++ */ ++ else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && ++ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && ++ !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { ++ hw->fc.current_mode = e1000_fc_rx_pause; ++ e_dbg("Flow Control = RX PAUSE frames only.\r\n"); ++ } else { ++ /* ++ * Per the IEEE spec, at this point flow control ++ * should be disabled. ++ */ ++ hw->fc.current_mode = e1000_fc_none; ++ e_dbg("Flow Control = NONE.\r\n"); ++ } ++ ++ /* ++ * Now we need to do one last check... If we auto- ++ * negotiated to HALF DUPLEX, flow control should not be ++ * enabled per IEEE 802.3 spec. ++ */ ++ ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); ++ if (ret_val) { ++ e_dbg("Error getting link speed and duplex\n"); ++ goto out; ++ } ++ ++ if (duplex == HALF_DUPLEX) ++ hw->fc.current_mode = e1000_fc_none; ++ ++ /* ++ * Now we call a subroutine to actually force the MAC ++ * controller to use the correct flow control settings. ++ */ ++ ret_val = e1000e_force_mac_fc(hw); ++ if (ret_val) { ++ e_dbg("Error forcing flow control settings\n"); ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex ++ * @hw: pointer to the HW structure ++ * @speed: stores the current speed ++ * @duplex: stores the current duplex ++ * ++ * Read the status register for the current speed/duplex and store the current ++ * speed and duplex for copper connections. ++ **/ ++s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex) ++{ ++ u32 status; ++ ++ status = er32(STATUS); ++ if (status & E1000_STATUS_SPEED_1000) { ++ *speed = SPEED_1000; ++ e_dbg("1000 Mbs, "); ++ } else if (status & E1000_STATUS_SPEED_100) { ++ *speed = SPEED_100; ++ e_dbg("100 Mbs, "); ++ } else { ++ *speed = SPEED_10; ++ e_dbg("10 Mbs, "); ++ } ++ ++ if (status & E1000_STATUS_FD) { ++ *duplex = FULL_DUPLEX; ++ e_dbg("Full Duplex\n"); ++ } else { ++ *duplex = HALF_DUPLEX; ++ e_dbg("Half Duplex\n"); ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex ++ * @hw: pointer to the HW structure ++ * @speed: stores the current speed ++ * @duplex: stores the current duplex ++ * ++ * Sets the speed and duplex to gigabit full duplex (the only possible option) ++ * for fiber/serdes links. ++ **/ ++s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, ++ u16 *speed, u16 *duplex) ++{ ++ *speed = SPEED_1000; ++ *duplex = FULL_DUPLEX; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000e_get_hw_semaphore - Acquire hardware semaphore ++ * @hw: pointer to the HW structure ++ * ++ * Acquire the HW semaphore to access the PHY or NVM ++ **/ ++s32 e1000e_get_hw_semaphore(struct e1000_hw *hw) ++{ ++ u32 swsm; ++ s32 ret_val = E1000_SUCCESS; ++ s32 timeout = hw->nvm.word_size + 1; ++ s32 i = 0; ++ ++ /* Get the SW semaphore */ ++ while (i < timeout) { ++ swsm = er32(SWSM); ++ if (!(swsm & E1000_SWSM_SMBI)) ++ break; ++ ++ udelay(50); ++ i++; ++ } ++ ++ if (i == timeout) { ++ e_dbg("Driver can't access device - SMBI bit is set.\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ /* Get the FW semaphore. */ ++ for (i = 0; i < timeout; i++) { ++ swsm = er32(SWSM); ++ ew32(SWSM, swsm | E1000_SWSM_SWESMBI); ++ ++ /* Semaphore acquired if bit latched */ ++ if (er32(SWSM) & E1000_SWSM_SWESMBI) ++ break; ++ ++ udelay(50); ++ } ++ ++ if (i == timeout) { ++ /* Release semaphores */ ++ e1000e_put_hw_semaphore(hw); ++ e_dbg("Driver can't access the NVM\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_put_hw_semaphore - Release hardware semaphore ++ * @hw: pointer to the HW structure ++ * ++ * Release hardware semaphore used to access the PHY or NVM ++ **/ ++void e1000e_put_hw_semaphore(struct e1000_hw *hw) ++{ ++ u32 swsm; ++ ++ swsm = er32(SWSM); ++ swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); ++ ew32(SWSM, swsm); ++} ++/** ++ * e1000e_get_auto_rd_done - Check for auto read completion ++ * @hw: pointer to the HW structure ++ * ++ * Check EEPROM for Auto Read done bit. ++ **/ ++s32 e1000e_get_auto_rd_done(struct e1000_hw *hw) ++{ ++ s32 i = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ while (i < AUTO_READ_DONE_TIMEOUT) { ++ if (er32(EECD) & E1000_EECD_AUTO_RD) ++ break; ++ msleep(1); ++ i++; ++ } ++ ++ if (i == AUTO_READ_DONE_TIMEOUT) { ++ e_dbg("Auto read by HW from NVM has not completed.\n"); ++ ret_val = -E1000_ERR_RESET; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_valid_led_default - Verify a valid default LED config ++ * @hw: pointer to the HW structure ++ * @data: pointer to the NVM (EEPROM) ++ * ++ * Read the EEPROM for the current default LED configuration. If the ++ * LED configuration is not valid, set to a valid LED configuration. ++ **/ ++s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data) ++{ ++ s32 ret_val; ++ ++ ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); ++ if (ret_val) { ++ e_dbg("NVM Read Error\n"); ++ goto out; ++ } ++ ++ if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) ++ *data = ID_LED_DEFAULT; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_id_led_init - ++ * @hw: pointer to the HW structure ++ * ++ **/ ++s32 e1000e_id_led_init(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val; ++ const u32 ledctl_mask = 0x000000FF; ++ const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; ++ const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; ++ u16 data, i, temp; ++ const u16 led_mask = 0x0F; ++ ++ ret_val = hw->nvm.ops.valid_led_default(hw, &data); ++ if (ret_val) ++ goto out; ++ ++ mac->ledctl_default = er32(LEDCTL); ++ mac->ledctl_mode1 = mac->ledctl_default; ++ mac->ledctl_mode2 = mac->ledctl_default; ++ ++ for (i = 0; i < 4; i++) { ++ temp = (data >> (i << 2)) & led_mask; ++ switch (temp) { ++ case ID_LED_ON1_DEF2: ++ case ID_LED_ON1_ON2: ++ case ID_LED_ON1_OFF2: ++ mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); ++ mac->ledctl_mode1 |= ledctl_on << (i << 3); ++ break; ++ case ID_LED_OFF1_DEF2: ++ case ID_LED_OFF1_ON2: ++ case ID_LED_OFF1_OFF2: ++ mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); ++ mac->ledctl_mode1 |= ledctl_off << (i << 3); ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++ switch (temp) { ++ case ID_LED_DEF1_ON2: ++ case ID_LED_ON1_ON2: ++ case ID_LED_OFF1_ON2: ++ mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); ++ mac->ledctl_mode2 |= ledctl_on << (i << 3); ++ break; ++ case ID_LED_DEF1_OFF2: ++ case ID_LED_ON1_OFF2: ++ case ID_LED_OFF1_OFF2: ++ mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); ++ mac->ledctl_mode2 |= ledctl_off << (i << 3); ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_led_generic - Configures SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * This prepares the SW controllable LED for use and saves the current state ++ * of the LED so it can be later restored. ++ **/ ++s32 e1000_setup_led_generic(struct e1000_hw *hw) ++{ ++ u32 ledctl; ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->mac.ops.setup_led != e1000_setup_led_generic) { ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ if (hw->phy.media_type == e1000_media_type_fiber) { ++ ledctl = er32(LEDCTL); ++ hw->mac.ledctl_default = ledctl; ++ /* Turn off LED0 */ ++ ledctl &= ~(E1000_LEDCTL_LED0_IVRT | ++ E1000_LEDCTL_LED0_BLINK | ++ E1000_LEDCTL_LED0_MODE_MASK); ++ ledctl |= (E1000_LEDCTL_MODE_LED_OFF << ++ E1000_LEDCTL_LED0_MODE_SHIFT); ++ ew32(LEDCTL, ledctl); ++ } else if (hw->phy.media_type == e1000_media_type_copper) { ++ ew32(LEDCTL, hw->mac.ledctl_mode1); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_cleanup_led_generic - Set LED config to default operation ++ * @hw: pointer to the HW structure ++ * ++ * Remove the current LED configuration and set the LED configuration ++ * to the default value, saved from the EEPROM. ++ **/ ++s32 e1000e_cleanup_led_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->mac.ops.cleanup_led != e1000e_cleanup_led_generic) { ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ew32(LEDCTL, hw->mac.ledctl_default); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_blink_led - Blink LED ++ * @hw: pointer to the HW structure ++ * ++ * Blink the LEDs which are set to be on. ++ **/ ++s32 e1000e_blink_led(struct e1000_hw *hw) ++{ ++ u32 ledctl_blink = 0; ++ u32 i; ++ ++ if (hw->phy.media_type == e1000_media_type_fiber) { ++ /* always blink LED0 for PCI-E fiber */ ++ ledctl_blink = E1000_LEDCTL_LED0_BLINK | ++ (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); ++ } else { ++ /* ++ * set the blink bit for each LED that's "on" (0x0E) ++ * in ledctl_mode2 ++ */ ++ ledctl_blink = hw->mac.ledctl_mode2; ++ for (i = 0; i < 4; i++) ++ if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == ++ E1000_LEDCTL_MODE_LED_ON) ++ ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << ++ (i * 8)); ++ } ++ ++ ew32(LEDCTL, ledctl_blink); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000e_led_on_generic - Turn LED on ++ * @hw: pointer to the HW structure ++ * ++ * Turn LED on. ++ **/ ++s32 e1000e_led_on_generic(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ ++ switch (hw->phy.media_type) { ++ case e1000_media_type_fiber: ++ ctrl = er32(CTRL); ++ ctrl &= ~E1000_CTRL_SWDPIN0; ++ ctrl |= E1000_CTRL_SWDPIO0; ++ ew32(CTRL, ctrl); ++ break; ++ case e1000_media_type_copper: ++ ew32(LEDCTL, hw->mac.ledctl_mode2); ++ break; ++ default: ++ break; ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000e_led_off_generic - Turn LED off ++ * @hw: pointer to the HW structure ++ * ++ * Turn LED off. ++ **/ ++s32 e1000e_led_off_generic(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ ++ switch (hw->phy.media_type) { ++ case e1000_media_type_fiber: ++ ctrl = er32(CTRL); ++ ctrl |= E1000_CTRL_SWDPIN0; ++ ctrl |= E1000_CTRL_SWDPIO0; ++ ew32(CTRL, ctrl); ++ break; ++ case e1000_media_type_copper: ++ ew32(LEDCTL, hw->mac.ledctl_mode1); ++ break; ++ default: ++ break; ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000e_set_pcie_no_snoop - Set PCI-express capabilities ++ * @hw: pointer to the HW structure ++ * @no_snoop: bitmap of snoop events ++ * ++ * Set the PCI-express register to snoop for events enabled in 'no_snoop'. ++ **/ ++void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) ++{ ++ u32 gcr; ++ ++ if (hw->bus.type != e1000_bus_type_pci_express) ++ goto out; ++ ++ if (no_snoop) { ++ gcr = er32(GCR); ++ gcr &= ~(PCIE_NO_SNOOP_ALL); ++ gcr |= no_snoop; ++ ew32(GCR, gcr); ++ } ++out: ++ return; ++} ++ ++/** ++ * e1000e_disable_pcie_master - Disables PCI-express master access ++ * @hw: pointer to the HW structure ++ * ++ * Returns 0 (E1000_SUCCESS) if successful, else returns -10 ++ * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused ++ * the master requests to be disabled. ++ * ++ * Disables PCI-Express master access and verifies there are no pending ++ * requests. ++ **/ ++s32 e1000e_disable_pcie_master(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 timeout = MASTER_DISABLE_TIMEOUT; ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->bus.type != e1000_bus_type_pci_express) ++ goto out; ++ ++ ctrl = er32(CTRL); ++ ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; ++ ew32(CTRL, ctrl); ++ ++ while (timeout) { ++ if (!(er32(STATUS) & ++ E1000_STATUS_GIO_MASTER_ENABLE)) ++ break; ++ udelay(100); ++ timeout--; ++ } ++ ++ if (!timeout) { ++ e_dbg("Master requests are pending.\n"); ++ ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing ++ * @hw: pointer to the HW structure ++ * ++ * Reset the Adaptive Interframe Spacing throttle to default values. ++ **/ ++void e1000e_reset_adaptive(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ ++ if (!mac->adaptive_ifs) { ++ e_dbg("Not in Adaptive IFS mode!\n"); ++ goto out; ++ } ++ ++ mac->current_ifs_val = 0; ++ mac->ifs_min_val = IFS_MIN; ++ mac->ifs_max_val = IFS_MAX; ++ mac->ifs_step_size = IFS_STEP; ++ mac->ifs_ratio = IFS_RATIO; ++ ++ mac->in_ifs_mode = false; ++ ew32(AIT, 0); ++out: ++ return; ++} ++ ++/** ++ * e1000e_update_adaptive - Update Adaptive Interframe Spacing ++ * @hw: pointer to the HW structure ++ * ++ * Update the Adaptive Interframe Spacing Throttle value based on the ++ * time between transmitted packets and time between collisions. ++ **/ ++void e1000e_update_adaptive(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ ++ if (!mac->adaptive_ifs) { ++ e_dbg("Not in Adaptive IFS mode!\n"); ++ goto out; ++ } ++ ++ if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { ++ if (mac->tx_packet_delta > MIN_NUM_XMITS) { ++ mac->in_ifs_mode = true; ++ if (mac->current_ifs_val < mac->ifs_max_val) { ++ if (!mac->current_ifs_val) ++ mac->current_ifs_val = mac->ifs_min_val; ++ else ++ mac->current_ifs_val += ++ mac->ifs_step_size; ++ ew32(AIT, mac->current_ifs_val); ++ } ++ } ++ } else { ++ if (mac->in_ifs_mode && ++ (mac->tx_packet_delta <= MIN_NUM_XMITS)) { ++ mac->current_ifs_val = 0; ++ mac->in_ifs_mode = false; ++ ew32(AIT, 0); ++ } ++ } ++out: ++ return; ++} ++ ++/** ++ * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings ++ * @hw: pointer to the HW structure ++ * ++ * Verify that when not using auto-negotiation that MDI/MDIx is correctly ++ * set, which is forced to MDI mode only. ++ **/ ++s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { ++ e_dbg("Invalid MDI setting detected\n"); ++ hw->phy.mdix = 1; ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_mac.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_mac.h Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,77 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_MAC_H_ ++#define _E1000_MAC_H_ ++ ++/* ++ * Functions that should not be called directly from drivers but can be used ++ * by other files in this 'shared code' ++ */ ++void e1000_init_mac_ops_generic(struct e1000_hw *hw); ++s32 e1000e_blink_led(struct e1000_hw *hw); ++s32 e1000e_check_for_copper_link(struct e1000_hw *hw); ++s32 e1000e_check_for_fiber_link(struct e1000_hw *hw); ++s32 e1000e_check_for_serdes_link(struct e1000_hw *hw); ++s32 e1000e_cleanup_led_generic(struct e1000_hw *hw); ++s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw); ++s32 e1000e_disable_pcie_master(struct e1000_hw *hw); ++s32 e1000e_force_mac_fc(struct e1000_hw *hw); ++s32 e1000e_get_auto_rd_done(struct e1000_hw *hw); ++s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw); ++void e1000_set_lan_id_single_port(struct e1000_hw *hw); ++s32 e1000e_get_hw_semaphore(struct e1000_hw *hw); ++s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex); ++s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, ++ u16 *speed, u16 *duplex); ++s32 e1000e_id_led_init(struct e1000_hw *hw); ++s32 e1000e_led_on_generic(struct e1000_hw *hw); ++s32 e1000e_led_off_generic(struct e1000_hw *hw); ++void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, ++ u8 *mc_addr_list, u32 mc_addr_count); ++s32 e1000e_set_fc_watermarks(struct e1000_hw *hw); ++s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw); ++s32 e1000_setup_led_generic(struct e1000_hw *hw); ++s32 e1000e_setup_link(struct e1000_hw *hw); ++ ++void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw); ++void e1000e_clear_vfta_generic(struct e1000_hw *hw); ++void e1000e_config_collision_dist(struct e1000_hw *hw); ++void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); ++void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value); ++void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw); ++void e1000e_put_hw_semaphore(struct e1000_hw *hw); ++void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); ++s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw); ++void e1000e_reset_adaptive(struct e1000_hw *hw); ++void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop); ++void e1000e_update_adaptive(struct e1000_hw *hw); ++void e1000e_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value); ++ ++#endif +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_manage.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_manage.c Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,365 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000.h" ++ ++static u8 e1000_calculate_checksum(u8 *buffer, u32 length); ++ ++/** ++ * e1000_calculate_checksum - Calculate checksum for buffer ++ * @buffer: pointer to EEPROM ++ * @length: size of EEPROM to calculate a checksum for ++ * ++ * Calculates the checksum for some buffer on a specified length. The ++ * checksum calculated is returned. ++ **/ ++static u8 e1000_calculate_checksum(u8 *buffer, u32 length) ++{ ++ u32 i; ++ u8 sum = 0; ++ ++ if (!buffer) ++ return 0; ++ for (i = 0; i < length; i++) ++ sum += buffer[i]; ++ ++ return (u8) (0 - sum); ++} ++ ++/** ++ * e1000_mng_enable_host_if_generic - Checks host interface is enabled ++ * @hw: pointer to the HW structure ++ * ++ * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND ++ * ++ * This function checks whether the HOST IF is enabled for command operation ++ * and also checks whether the previous command is completed. It busy waits ++ * in case of previous command is not completed. ++ **/ ++s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw) ++{ ++ u32 hicr; ++ s32 ret_val = E1000_SUCCESS; ++ u8 i; ++ ++ /* Check that the host interface is enabled. */ ++ hicr = er32(HICR); ++ if ((hicr & E1000_HICR_EN) == 0) { ++ e_dbg("E1000_HOST_EN bit disabled.\n"); ++ ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; ++ goto out; ++ } ++ /* check the previous command is completed */ ++ for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { ++ hicr = er32(HICR); ++ if (!(hicr & E1000_HICR_C)) ++ break; ++ mdelay(1); ++ } ++ ++ if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { ++ e_dbg("Previous command timeout failed .\n"); ++ ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_mng_mode_generic - Generic check management mode ++ * @hw: pointer to the HW structure ++ * ++ * Reads the firmware semaphore register and returns true (>0) if ++ * manageability is enabled, else false (0). ++ **/ ++bool e1000_check_mng_mode_generic(struct e1000_hw *hw) ++{ ++ u32 fwsm; ++ ++ fwsm = er32(FWSM); ++ return (fwsm & E1000_FWSM_MODE_MASK) == ++ (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); ++} ++/** ++ * e1000e_enable_tx_pkt_filtering - Enable packet filtering on TX ++ * @hw: pointer to the HW structure ++ * ++ * Enables packet filtering on transmit packets if manageability is enabled ++ * and host interface is enabled. ++ **/ ++bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw) ++{ ++ struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie; ++ u32 *buffer = (u32 *)&hw->mng_cookie; ++ u32 offset; ++ s32 ret_val, hdr_csum, csum; ++ u8 i, len; ++ bool tx_filter = true; ++ ++ /* No manageability, no filtering */ ++ if (!hw->mac.ops.check_mng_mode(hw)) { ++ tx_filter = false; ++ goto out; ++ } ++ ++ /* ++ * If we can't read from the host interface for whatever ++ * reason, disable filtering. ++ */ ++ ret_val = hw->mac.ops.mng_enable_host_if(hw); ++ if (ret_val != E1000_SUCCESS) { ++ tx_filter = false; ++ goto out; ++ } ++ ++ /* Read in the header. Length and offset are in dwords. */ ++ len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2; ++ offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2; ++ for (i = 0; i < len; i++) { ++ *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, ++ E1000_HOST_IF, ++ offset + i); ++ } ++ hdr_csum = hdr->checksum; ++ hdr->checksum = 0; ++ csum = e1000_calculate_checksum((u8 *)hdr, ++ E1000_MNG_DHCP_COOKIE_LENGTH); ++ /* ++ * If either the checksums or signature don't match, then ++ * the cookie area isn't considered valid, in which case we ++ * take the safe route of assuming Tx filtering is enabled. ++ */ ++ if (hdr_csum != csum) ++ goto out; ++ if (hdr->signature != E1000_IAMT_SIGNATURE) ++ goto out; ++ ++ /* Cookie area is valid, make the final check for filtering. */ ++ if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) ++ tx_filter = false; ++ ++out: ++ hw->mac.tx_pkt_filtering = tx_filter; ++ return tx_filter; ++} ++ ++/** ++ * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface ++ * @hw: pointer to the HW structure ++ * @buffer: pointer to the host interface ++ * @length: size of the buffer ++ * ++ * Writes the DHCP information to the host interface. ++ **/ ++s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, ++ u16 length) ++{ ++ struct e1000_host_mng_command_header hdr; ++ s32 ret_val; ++ u32 hicr; ++ ++ hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; ++ hdr.command_length = length; ++ hdr.reserved1 = 0; ++ hdr.reserved2 = 0; ++ hdr.checksum = 0; ++ ++ /* Enable the host interface */ ++ ret_val = hw->mac.ops.mng_enable_host_if(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Populate the host interface with the contents of "buffer". */ ++ ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length, ++ sizeof(hdr), &(hdr.checksum)); ++ if (ret_val) ++ goto out; ++ ++ /* Write the manageability command header */ ++ ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr); ++ if (ret_val) ++ goto out; ++ ++ /* Tell the ARC a new command is pending. */ ++ hicr = er32(HICR); ++ ew32(HICR, hicr | E1000_HICR_C); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_mng_write_cmd_header_generic - Writes manageability command header ++ * @hw: pointer to the HW structure ++ * @hdr: pointer to the host interface command header ++ * ++ * Writes the command header after does the checksum calculation. ++ **/ ++s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header *hdr) ++{ ++ u16 i, length = sizeof(struct e1000_host_mng_command_header); ++ ++ /* Write the whole command header structure with new checksum. */ ++ ++ hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length); ++ ++ length >>= 2; ++ /* Write the relevant command block into the ram area. */ ++ for (i = 0; i < length; i++) { ++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i, ++ *((u32 *) hdr + i)); ++ e1e_flush(); ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_mng_host_if_write_generic - Write to the manageability host interface ++ * @hw: pointer to the HW structure ++ * @buffer: pointer to the host interface buffer ++ * @length: size of the buffer ++ * @offset: location in the buffer to write to ++ * @sum: sum of the data (not checksum) ++ * ++ * This function writes the buffer content at the offset given on the host if. ++ * It also does alignment considerations to do the writes in most efficient ++ * way. Also fills up the sum of the buffer in *buffer parameter. ++ **/ ++s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer, ++ u16 length, u16 offset, u8 *sum) ++{ ++ u8 *tmp; ++ u8 *bufptr = buffer; ++ u32 data = 0; ++ s32 ret_val = E1000_SUCCESS; ++ u16 remaining, i, j, prev_bytes; ++ ++ /* sum = only sum of the data and it is not checksum */ ++ ++ if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { ++ ret_val = -E1000_ERR_PARAM; ++ goto out; ++ } ++ ++ tmp = (u8 *)&data; ++ prev_bytes = offset & 0x3; ++ offset >>= 2; ++ ++ if (prev_bytes) { ++ data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset); ++ for (j = prev_bytes; j < sizeof(u32); j++) { ++ *(tmp + j) = *bufptr++; ++ *sum += *(tmp + j); ++ } ++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data); ++ length -= j - prev_bytes; ++ offset++; ++ } ++ ++ remaining = length & 0x3; ++ length -= remaining; ++ ++ /* Calculate length in DWORDs */ ++ length >>= 2; ++ ++ /* ++ * The device driver writes the relevant command block into the ++ * ram area. ++ */ ++ for (i = 0; i < length; i++) { ++ for (j = 0; j < sizeof(u32); j++) { ++ *(tmp + j) = *bufptr++; ++ *sum += *(tmp + j); ++ } ++ ++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, ++ data); ++ } ++ if (remaining) { ++ for (j = 0; j < sizeof(u32); j++) { ++ if (j < remaining) ++ *(tmp + j) = *bufptr++; ++ else ++ *(tmp + j) = 0; ++ ++ *sum += *(tmp + j); ++ } ++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_enable_mng_pass_thru - Enable processing of ARP's ++ * @hw: pointer to the HW structure ++ * ++ * Verifies the hardware needs to allow ARPs to be processed by the host. ++ **/ ++bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw) ++{ ++ u32 manc; ++ u32 fwsm, factps; ++ bool ret_val = false; ++ ++ if (!hw->mac.asf_firmware_present) ++ goto out; ++ ++ manc = er32(MANC); ++ ++ if (!(manc & E1000_MANC_RCV_TCO_EN) || ++ !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) ++ goto out; ++ ++ if (hw->mac.arc_subsystem_valid) { ++ fwsm = er32(FWSM); ++ factps = er32(FACTPS); ++ ++ if (!(factps & E1000_FACTPS_MNGCG) && ++ ((fwsm & E1000_FWSM_MODE_MASK) == ++ (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { ++ ret_val = true; ++ goto out; ++ } ++ } else { ++ if ((manc & E1000_MANC_SMBUS_EN) && ++ !(manc & E1000_MANC_ASF_EN)) { ++ ret_val = true; ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_manage.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_manage.h Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,82 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_MANAGE_H_ ++#define _E1000_MANAGE_H_ ++ ++bool e1000_check_mng_mode_generic(struct e1000_hw *hw); ++bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw); ++s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw); ++s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer, ++ u16 length, u16 offset, u8 *sum); ++s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header *hdr); ++s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, ++ u8 *buffer, u16 length); ++bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); ++ ++enum e1000_mng_mode { ++ e1000_mng_mode_none = 0, ++ e1000_mng_mode_asf, ++ e1000_mng_mode_pt, ++ e1000_mng_mode_ipmi, ++ e1000_mng_mode_host_if_only ++}; ++ ++#define E1000_FACTPS_MNGCG 0x20000000 ++ ++#define E1000_FWSM_MODE_MASK 0xE ++#define E1000_FWSM_MODE_SHIFT 1 ++ ++#define E1000_MNG_IAMT_MODE 0x3 ++#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 ++#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 ++#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 ++#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 ++#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 ++#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 ++ ++#define E1000_VFTA_ENTRY_SHIFT 5 ++#define E1000_VFTA_ENTRY_MASK 0x7F ++#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F ++ ++#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ ++#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ ++#define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ ++ ++#define E1000_HICR_EN 0x01 /* Enable bit - RO */ ++/* Driver sets this bit when done to put command in RAM */ ++#define E1000_HICR_C 0x02 ++#define E1000_HICR_SV 0x04 /* Status Validity */ ++#define E1000_HICR_FW_RESET_ENABLE 0x40 ++#define E1000_HICR_FW_RESET 0x80 ++ ++/* Intel(R) Active Management Technology signature */ ++#define E1000_IAMT_SIGNATURE 0x544D4149 ++ ++#endif +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_nvm.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_nvm.c Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,594 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000.h" ++ ++static void e1000_stop_nvm(struct e1000_hw *hw); ++static void e1000e_reload_nvm(struct e1000_hw *hw); ++ ++/** ++ * e1000_init_nvm_ops_generic - Initialize NVM function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Setups up the function pointers to no-op functions ++ **/ ++void e1000_init_nvm_ops_generic(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ /* Initialize function pointers */ ++ nvm->ops.reload = e1000e_reload_nvm; ++} ++ ++/** ++ * e1000_raise_eec_clk - Raise EEPROM clock ++ * @hw: pointer to the HW structure ++ * @eecd: pointer to the EEPROM ++ * ++ * Enable/Raise the EEPROM clock bit. ++ **/ ++static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) ++{ ++ *eecd = *eecd | E1000_EECD_SK; ++ ew32(EECD, *eecd); ++ e1e_flush(); ++ udelay(hw->nvm.delay_usec); ++} ++ ++/** ++ * e1000_lower_eec_clk - Lower EEPROM clock ++ * @hw: pointer to the HW structure ++ * @eecd: pointer to the EEPROM ++ * ++ * Clear/Lower the EEPROM clock bit. ++ **/ ++static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) ++{ ++ *eecd = *eecd & ~E1000_EECD_SK; ++ ew32(EECD, *eecd); ++ e1e_flush(); ++ udelay(hw->nvm.delay_usec); ++} ++ ++/** ++ * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM ++ * @hw: pointer to the HW structure ++ * @data: data to send to the EEPROM ++ * @count: number of bits to shift out ++ * ++ * We need to shift 'count' bits out to the EEPROM. So, the value in the ++ * "data" parameter will be shifted out to the EEPROM one bit at a time. ++ * In order to do this, "data" must be broken down into bits. ++ **/ ++static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = er32(EECD); ++ u32 mask; ++ ++ mask = 0x01 << (count - 1); ++ if (nvm->type == e1000_nvm_eeprom_spi) ++ eecd |= E1000_EECD_DO; ++ ++ do { ++ eecd &= ~E1000_EECD_DI; ++ ++ if (data & mask) ++ eecd |= E1000_EECD_DI; ++ ++ ew32(EECD, eecd); ++ e1e_flush(); ++ ++ udelay(nvm->delay_usec); ++ ++ e1000_raise_eec_clk(hw, &eecd); ++ e1000_lower_eec_clk(hw, &eecd); ++ ++ mask >>= 1; ++ } while (mask); ++ ++ eecd &= ~E1000_EECD_DI; ++ ew32(EECD, eecd); ++} ++ ++/** ++ * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM ++ * @hw: pointer to the HW structure ++ * @count: number of bits to shift in ++ * ++ * In order to read a register from the EEPROM, we need to shift 'count' bits ++ * in from the EEPROM. Bits are "shifted in" by raising the clock input to ++ * the EEPROM (setting the SK bit), and then reading the value of the data out ++ * "DO" bit. During this "shifting in" process the data in "DI" bit should ++ * always be clear. ++ **/ ++static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) ++{ ++ u32 eecd; ++ u32 i; ++ u16 data; ++ ++ eecd = er32(EECD); ++ eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); ++ data = 0; ++ ++ for (i = 0; i < count; i++) { ++ data <<= 1; ++ e1000_raise_eec_clk(hw, &eecd); ++ ++ eecd = er32(EECD); ++ ++ eecd &= ~E1000_EECD_DI; ++ if (eecd & E1000_EECD_DO) ++ data |= 1; ++ ++ e1000_lower_eec_clk(hw, &eecd); ++ } ++ ++ return data; ++} ++ ++/** ++ * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion ++ * @hw: pointer to the HW structure ++ * @ee_reg: EEPROM flag for polling ++ * ++ * Polls the EEPROM status bit for either read or write completion based ++ * upon the value of 'ee_reg'. ++ **/ ++s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) ++{ ++ u32 attempts = 100000; ++ u32 i, reg = 0; ++ s32 ret_val = -E1000_ERR_NVM; ++ ++ for (i = 0; i < attempts; i++) { ++ if (ee_reg == E1000_NVM_POLL_READ) ++ reg = er32(EERD); ++ else ++ reg = er32(EEWR); ++ ++ if (reg & E1000_NVM_RW_REG_DONE) { ++ ret_val = E1000_SUCCESS; ++ break; ++ } ++ ++ udelay(5); ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000e_acquire_nvm - Generic request for access to EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Set the EEPROM access request bit and wait for EEPROM access grant bit. ++ * Return successful if access grant bit set, else clear the request for ++ * EEPROM access and return -E1000_ERR_NVM (-1). ++ **/ ++s32 e1000e_acquire_nvm(struct e1000_hw *hw) ++{ ++ u32 eecd = er32(EECD); ++ s32 timeout = E1000_NVM_GRANT_ATTEMPTS; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ew32(EECD, eecd | E1000_EECD_REQ); ++ eecd = er32(EECD); ++ while (timeout) { ++ if (eecd & E1000_EECD_GNT) ++ break; ++ udelay(5); ++ eecd = er32(EECD); ++ timeout--; ++ } ++ ++ if (!timeout) { ++ eecd &= ~E1000_EECD_REQ; ++ ew32(EECD, eecd); ++ e_dbg("Could not acquire NVM grant\n"); ++ ret_val = -E1000_ERR_NVM; ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_standby_nvm - Return EEPROM to standby state ++ * @hw: pointer to the HW structure ++ * ++ * Return the EEPROM to a standby state. ++ **/ ++static void e1000_standby_nvm(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = er32(EECD); ++ ++ if (nvm->type == e1000_nvm_eeprom_spi) { ++ /* Toggle CS to flush commands */ ++ eecd |= E1000_EECD_CS; ++ ew32(EECD, eecd); ++ e1e_flush(); ++ udelay(nvm->delay_usec); ++ eecd &= ~E1000_EECD_CS; ++ ew32(EECD, eecd); ++ e1e_flush(); ++ udelay(nvm->delay_usec); ++ } ++} ++ ++/** ++ * e1000_stop_nvm - Terminate EEPROM command ++ * @hw: pointer to the HW structure ++ * ++ * Terminates the current command by inverting the EEPROM's chip select pin. ++ **/ ++static void e1000_stop_nvm(struct e1000_hw *hw) ++{ ++ u32 eecd; ++ ++ eecd = er32(EECD); ++ if (hw->nvm.type == e1000_nvm_eeprom_spi) { ++ /* Pull CS high */ ++ eecd |= E1000_EECD_CS; ++ e1000_lower_eec_clk(hw, &eecd); ++ } ++} ++ ++/** ++ * e1000e_release_nvm - Release exclusive access to EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Stop any current commands to the EEPROM and clear the EEPROM request bit. ++ **/ ++void e1000e_release_nvm(struct e1000_hw *hw) ++{ ++ u32 eecd; ++ ++ e1000_stop_nvm(hw); ++ ++ eecd = er32(EECD); ++ eecd &= ~E1000_EECD_REQ; ++ ew32(EECD, eecd); ++} ++ ++/** ++ * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write ++ * @hw: pointer to the HW structure ++ * ++ * Setups the EEPROM for reading and writing. ++ **/ ++static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = er32(EECD); ++ s32 ret_val = E1000_SUCCESS; ++ u16 timeout = 0; ++ u8 spi_stat_reg; ++ ++ if (nvm->type == e1000_nvm_eeprom_spi) { ++ /* Clear SK and CS */ ++ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); ++ ew32(EECD, eecd); ++ udelay(1); ++ timeout = NVM_MAX_RETRY_SPI; ++ ++ /* ++ * Read "Status Register" repeatedly until the LSB is cleared. ++ * The EEPROM will signal that the command has been completed ++ * by clearing bit 0 of the internal status register. If it's ++ * not cleared within 'timeout', then error out. ++ */ ++ while (timeout) { ++ e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, ++ hw->nvm.opcode_bits); ++ spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); ++ if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) ++ break; ++ ++ udelay(5); ++ e1000_standby_nvm(hw); ++ timeout--; ++ } ++ ++ if (!timeout) { ++ e_dbg("SPI NVM Status error\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_read_nvm_eerd - Reads EEPROM using EERD register ++ * @hw: pointer to the HW structure ++ * @offset: offset of word in the EEPROM to read ++ * @words: number of words to read ++ * @data: word read from the EEPROM ++ * ++ * Reads a 16 bit word from the EEPROM using the EERD register. ++ **/ ++s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 i, eerd = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* ++ * A check for invalid values: offset too large, too many words, ++ * too many words for the offset, and not enough words. ++ */ ++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || ++ (words == 0)) { ++ e_dbg("nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ for (i = 0; i < words; i++) { ++ eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + ++ E1000_NVM_RW_REG_START; ++ ++ ew32(EERD, eerd); ++ ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); ++ if (ret_val) ++ break; ++ ++ data[i] = (er32(EERD) >> ++ E1000_NVM_RW_REG_DATA); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_write_nvm_spi - Write to EEPROM using SPI ++ * @hw: pointer to the HW structure ++ * @offset: offset within the EEPROM to be written to ++ * @words: number of words to write ++ * @data: 16 bit word(s) to be written to the EEPROM ++ * ++ * Writes data to EEPROM at offset using SPI interface. ++ * ++ * If e1000_update_nvm_checksum is not called after this function , the ++ * EEPROM will most likely contain an invalid checksum. ++ **/ ++s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ s32 ret_val; ++ u16 widx = 0; ++ ++ /* ++ * A check for invalid values: offset too large, too many words, ++ * and not enough words. ++ */ ++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || ++ (words == 0)) { ++ e_dbg("nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ ret_val = nvm->ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ while (widx < words) { ++ u8 write_opcode = NVM_WRITE_OPCODE_SPI; ++ ++ ret_val = e1000_ready_nvm_eeprom(hw); ++ if (ret_val) ++ goto release; ++ ++ e1000_standby_nvm(hw); ++ ++ /* Send the WRITE ENABLE command (8 bit opcode) */ ++ e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, ++ nvm->opcode_bits); ++ ++ e1000_standby_nvm(hw); ++ ++ /* ++ * Some SPI eeproms use the 8th address bit embedded in the ++ * opcode ++ */ ++ if ((nvm->address_bits == 8) && (offset >= 128)) ++ write_opcode |= NVM_A8_OPCODE_SPI; ++ ++ /* Send the Write command (8-bit opcode + addr) */ ++ e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); ++ e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), ++ nvm->address_bits); ++ ++ /* Loop to allow for up to whole page write of eeprom */ ++ while (widx < words) { ++ u16 word_out = data[widx]; ++ word_out = (word_out >> 8) | (word_out << 8); ++ e1000_shift_out_eec_bits(hw, word_out, 16); ++ widx++; ++ ++ if ((((offset + widx) * 2) % nvm->page_size) == 0) { ++ e1000_standby_nvm(hw); ++ break; ++ } ++ } ++ } ++ ++ msleep(10); ++release: ++ nvm->ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_read_pba_num - Read device part number ++ * @hw: pointer to the HW structure ++ * @pba_num: pointer to device part number ++ * ++ * Reads the product board assembly (PBA) number from the EEPROM and stores ++ * the value in pba_num. ++ **/ ++s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num) ++{ ++ s32 ret_val; ++ u16 nvm_data; ++ ++ ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); ++ if (ret_val) { ++ e_dbg("NVM Read Error\n"); ++ goto out; ++ } ++ *pba_num = (u32)(nvm_data << 16); ++ ++ ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); ++ if (ret_val) { ++ e_dbg("NVM Read Error\n"); ++ goto out; ++ } ++ *pba_num |= nvm_data; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_read_mac_addr_generic - Read device MAC address ++ * @hw: pointer to the HW structure ++ * ++ * Reads the device MAC address from the EEPROM and stores the value. ++ * Since devices with two ports use the same EEPROM, we increment the ++ * last bit in the MAC address for the second port. ++ **/ ++s32 e1000e_read_mac_addr_generic(struct e1000_hw *hw) ++{ ++ u32 rar_high; ++ u32 rar_low; ++ u16 i; ++ ++ rar_high = er32(RAH(0)); ++ rar_low = er32(RAL(0)); ++ ++ for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) ++ hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); ++ ++ for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) ++ hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); ++ ++ for (i = 0; i < ETH_ADDR_LEN; i++) ++ hw->mac.addr[i] = hw->mac.perm_addr[i]; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Calculates the EEPROM checksum by reading/adding each word of the EEPROM ++ * and then verifies that the sum of the EEPROM is equal to 0xBABA. ++ **/ ++s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 checksum = 0; ++ u16 i, nvm_data; ++ ++ for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { ++ ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); ++ if (ret_val) { ++ e_dbg("NVM Read Error\n"); ++ goto out; ++ } ++ checksum += nvm_data; ++ } ++ ++ if (checksum != (u16) NVM_SUM) { ++ e_dbg("NVM Checksum Invalid\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_update_nvm_checksum_generic - Update EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Updates the EEPROM checksum by reading/adding each word of the EEPROM ++ * up to the checksum. Then calculates the EEPROM checksum and writes the ++ * value to the EEPROM. ++ **/ ++s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ u16 checksum = 0; ++ u16 i, nvm_data; ++ ++ for (i = 0; i < NVM_CHECKSUM_REG; i++) { ++ ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); ++ if (ret_val) { ++ e_dbg("NVM Read Error while updating checksum.\n"); ++ goto out; ++ } ++ checksum += nvm_data; ++ } ++ checksum = (u16) NVM_SUM - checksum; ++ ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); ++ if (ret_val) ++ e_dbg("NVM Write Error while updating checksum.\n"); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_reload_nvm - Reloads EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the ++ * extended control register. ++ **/ ++static void e1000e_reload_nvm(struct e1000_hw *hw) ++{ ++ u32 ctrl_ext; ++ ++ udelay(10); ++ ctrl_ext = er32(CTRL_EXT); ++ ctrl_ext |= E1000_CTRL_EXT_EE_RST; ++ ew32(CTRL_EXT, ctrl_ext); ++ e1e_flush(); ++} ++ +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_nvm.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_nvm.h Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,51 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_NVM_H_ ++#define _E1000_NVM_H_ ++ ++void e1000_init_nvm_ops_generic(struct e1000_hw *hw); ++s32 e1000e_acquire_nvm(struct e1000_hw *hw); ++ ++s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg); ++s32 e1000e_read_mac_addr_generic(struct e1000_hw *hw); ++s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num); ++s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data); ++s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data); ++s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw); ++s32 e1000_write_nvm_eewr(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data); ++s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data); ++s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw); ++void e1000e_release_nvm(struct e1000_hw *hw); ++ ++#define E1000_STM_OPCODE 0xDB00 ++ ++#endif +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_osdep.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_osdep.h Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,116 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2008 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++ ++/* glue for the OS-dependent part of e1000 ++ * includes register access macros ++ */ ++ ++#ifndef _E1000_OSDEP_H_ ++#define _E1000_OSDEP_H_ ++ ++#include ++#include ++#include ++#include ++ ++#include "kcompat.h" ++ ++#define usec_delay(x) udelay(x) ++#ifndef msec_delay ++#define msec_delay(x) do { if(in_interrupt()) { \ ++ /* Don't sleep in interrupt context! */ \ ++ BUG(); \ ++ } else { \ ++ msleep(x); \ ++ } } while (0) ++ ++/* Some workarounds require millisecond delays and are run during interrupt ++ * context. Most notably, when establishing link, the phy may need tweaking ++ * but cannot process phy register reads/writes faster than millisecond ++ * intervals...and we establish link due to a "link status change" interrupt. ++ */ ++#define msec_delay_irq(x) mdelay(x) ++#endif ++ ++#define PCI_COMMAND_REGISTER PCI_COMMAND ++#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE ++#define ETH_ADDR_LEN ETH_ALEN ++ ++ ++#define DEBUGOUT(S) ++#define DEBUGOUT1(S, A...) ++ ++#define DEBUGFUNC(F) DEBUGOUT(F "\n") ++#define DEBUGOUT2 DEBUGOUT1 ++#define DEBUGOUT3 DEBUGOUT2 ++#define DEBUGOUT7 DEBUGOUT3 ++ ++#define E1000_WRITE_REG(a, reg, value) ( \ ++ writel((value), ((a)->hw_addr + reg))) ++ ++#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + reg)) ++ ++#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \ ++ writel((value), ((a)->hw_addr + reg + ((offset) << 2)))) ++ ++#define E1000_READ_REG_ARRAY(a, reg, offset) ( \ ++ readl((a)->hw_addr + reg + ((offset) << 2))) ++ ++#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY ++#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY ++ ++#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \ ++ writew((value), ((a)->hw_addr + reg + ((offset) << 1)))) ++ ++#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \ ++ readw((a)->hw_addr + reg + ((offset) << 1))) ++ ++#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \ ++ writeb((value), ((a)->hw_addr + reg + (offset)))) ++ ++#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \ ++ readb((a)->hw_addr + reg + (offset))) ++ ++#define E1000_WRITE_REG_IO(a, reg, offset) do { \ ++ outl(reg, ((a)->io_base)); \ ++ outl(offset, ((a)->io_base + 4)); } while(0) ++ ++#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS) ++ ++#define E1000_WRITE_FLASH_REG(a, reg, value) ( \ ++ writel((value), ((a)->flash_address + reg))) ++ ++#define E1000_WRITE_FLASH_REG16(a, reg, value) ( \ ++ writew((value), ((a)->flash_address + reg))) ++ ++#define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg)) ++ ++#define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg)) ++ ++#endif /* _E1000_OSDEP_H_ */ +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_phy.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_phy.c Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,3137 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000.h" ++ ++static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); ++static s32 e1000_copper_link_autoneg(struct e1000_hw *hw); ++static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); ++static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, ++ u16 *data, bool read); ++static u32 e1000_get_phy_addr_for_hv_page(u32 page); ++static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, ++ u16 *data, bool read); ++ ++/* Cable length tables */ ++static const u16 e1000_m88_cable_length_table[] = ++ { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; ++#define M88E1000_CABLE_LENGTH_TABLE_SIZE \ ++ (sizeof(e1000_m88_cable_length_table) / \ ++ sizeof(e1000_m88_cable_length_table[0])) ++ ++static const u16 e1000_igp_2_cable_length_table[] = ++ { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, ++ 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, ++ 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, ++ 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, ++ 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, ++ 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, ++ 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, ++ 104, 109, 114, 118, 121, 124}; ++#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ ++ (sizeof(e1000_igp_2_cable_length_table) / \ ++ sizeof(e1000_igp_2_cable_length_table[0])) ++ ++/** ++ * e1000e_check_reset_block_generic - Check if PHY reset is blocked ++ * @hw: pointer to the HW structure ++ * ++ * Read the PHY management control register and check whether a PHY reset ++ * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise ++ * return E1000_BLK_PHY_RESET (12). ++ **/ ++s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) ++{ ++ u32 manc; ++ ++ manc = er32(MANC); ++ ++ return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? ++ E1000_BLK_PHY_RESET : E1000_SUCCESS; ++} ++ ++/** ++ * e1000e_get_phy_id - Retrieve the PHY ID and revision ++ * @hw: pointer to the HW structure ++ * ++ * Reads the PHY registers and stores the PHY ID and possibly the PHY ++ * revision in the hardware structure. ++ **/ ++s32 e1000e_get_phy_id(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 phy_id; ++ u16 retry_count = 0; ++ ++ if (!(phy->ops.read_reg)) ++ goto out; ++ ++ while (retry_count < 2) { ++ ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); ++ if (ret_val) ++ goto out; ++ ++ phy->id = (u32)(phy_id << 16); ++ udelay(20); ++ ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); ++ if (ret_val) ++ goto out; ++ ++ phy->id |= (u32)(phy_id & PHY_REVISION_MASK); ++ phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); ++ ++ if (phy->id != 0 && phy->id != PHY_REVISION_MASK) ++ goto out; ++ ++ /* ++ * If the PHY ID is still unknown, we may have an 82577 without link. ++ * We will try again after setting Slow MDIC mode. No harm in trying ++ * again in this case since the PHY ID is unknown at this point anyway ++ */ ++ ret_val = e1000_set_mdio_slow_mode_hv(hw, true); ++ if (ret_val) ++ goto out; ++ ++ retry_count++; ++ } ++out: ++ /* Revert to MDIO fast mode, if applicable */ ++ if (retry_count) ++ ret_val = e1000_set_mdio_slow_mode_hv(hw, false); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000e_phy_reset_dsp - Reset PHY DSP ++ * @hw: pointer to the HW structure ++ * ++ * Reset the digital signal processor. ++ **/ ++s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (!(hw->phy.ops.write_reg)) ++ goto out; ++ ++ ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_read_phy_reg_mdic - Read MDI control register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Reads the MDI control register in the PHY at offset and stores the ++ * information read to data. ++ **/ ++s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ u32 i, mdic = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* ++ * Set up Op-code, Phy Address, and register offset in the MDI ++ * Control register. The MAC will take care of interfacing with the ++ * PHY to retrieve the desired data. ++ */ ++ mdic = ((offset << E1000_MDIC_REG_SHIFT) | ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_READ)); ++ ++ ew32(MDIC, mdic); ++ ++ /* ++ * Poll the ready bit to see if the MDI read completed ++ * Increasing the time out as testing showed failures with ++ * the lower time out ++ */ ++ for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { ++ udelay(50); ++ mdic = er32(MDIC); ++ if (mdic & E1000_MDIC_READY) ++ break; ++ } ++ if (!(mdic & E1000_MDIC_READY)) { ++ e_dbg("MDI Read did not complete\n"); ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ if (mdic & E1000_MDIC_ERROR) { ++ e_dbg("MDI Error\n"); ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ *data = (u16) mdic; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_write_phy_reg_mdic - Write MDI control register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write to register at offset ++ * ++ * Writes data to MDI control register in the PHY at offset. ++ **/ ++s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ u32 i, mdic = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* ++ * Set up Op-code, Phy Address, and register offset in the MDI ++ * Control register. The MAC will take care of interfacing with the ++ * PHY to retrieve the desired data. ++ */ ++ mdic = (((u32)data) | ++ (offset << E1000_MDIC_REG_SHIFT) | ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_WRITE)); ++ ++ ew32(MDIC, mdic); ++ ++ /* ++ * Poll the ready bit to see if the MDI read completed ++ * Increasing the time out as testing showed failures with ++ * the lower time out ++ */ ++ for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { ++ udelay(50); ++ mdic = er32(MDIC); ++ if (mdic & E1000_MDIC_READY) ++ break; ++ } ++ if (!(mdic & E1000_MDIC_READY)) { ++ e_dbg("MDI Write did not complete\n"); ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ if (mdic & E1000_MDIC_ERROR) { ++ e_dbg("MDI Error\n"); ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_read_phy_reg_m88 - Read m88 PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retrieved information in data. Release any acquired ++ * semaphores before exiting. ++ **/ ++s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_write_phy_reg_m88 - Write m88 PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary, then writes the data to PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_read_phy_reg_igp - Read igp PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retrieved information in data. Release any acquired ++ * semaphores before exiting. ++ **/ ++s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ ret_val = e1000e_write_phy_reg_mdic(hw, ++ IGP01E1000_PHY_PAGE_SELECT, ++ (u16)offset); ++ if (ret_val) { ++ hw->phy.ops.release(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_write_phy_reg_igp - Write igp PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary, then writes the data to PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ ret_val = e1000e_write_phy_reg_mdic(hw, ++ IGP01E1000_PHY_PAGE_SELECT, ++ (u16)offset); ++ if (ret_val) { ++ hw->phy.ops.release(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_read_kmrn_reg - Read kumeran register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary. Then reads the PHY register at offset ++ * using the kumeran interface. The information retrieved is stored in data. ++ * Release any acquired semaphores before exiting. ++ **/ ++s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ u32 kmrnctrlsta; ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & ++ E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; ++ ew32(KMRNCTRLSTA, kmrnctrlsta); ++ ++ udelay(2); ++ ++ kmrnctrlsta = er32(KMRNCTRLSTA); ++ *data = (u16)kmrnctrlsta; ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_write_kmrn_reg - Write kumeran register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary. Then write the data to PHY register ++ * at the offset using the kumeran interface. Release any acquired semaphores ++ * before exiting. ++ **/ ++s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ u32 kmrnctrlsta; ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & ++ E1000_KMRNCTRLSTA_OFFSET) | data; ++ ew32(KMRNCTRLSTA, kmrnctrlsta); ++ ++ udelay(2); ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link ++ * @hw: pointer to the HW structure ++ * ++ * Sets up Carrier-sense on Transmit and downshift values. ++ **/ ++s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ ++ if (phy->reset_disable) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ /* Enable CRS on TX. This must be set for half-duplex operation. */ ++ ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; ++ ++ /* Enable downshift */ ++ phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; ++ ++ ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* Set number of link attempts before downshift */ ++ ret_val = e1e_rphy(hw, I82577_CTRL_REG, &phy_data); ++ if (ret_val) ++ goto out; ++ phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK; ++ ret_val = e1e_wphy(hw, I82577_CTRL_REG, phy_data); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link ++ * @hw: pointer to the HW structure ++ * ++ * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock ++ * and downshift values are set also. ++ **/ ++s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ ++ if (phy->reset_disable) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ /* Enable CRS on TX. This must be set for half-duplex operation. */ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* For BM PHY this bit is downshift enable */ ++ if (phy->type != e1000_phy_bm) ++ phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; ++ ++ /* ++ * Options: ++ * MDI/MDI-X = 0 (default) ++ * 0 - Auto for all speeds ++ * 1 - MDI mode ++ * 2 - MDI-X mode ++ * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) ++ */ ++ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; ++ ++ switch (phy->mdix) { ++ case 1: ++ phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; ++ break; ++ case 2: ++ phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; ++ break; ++ case 3: ++ phy_data |= M88E1000_PSCR_AUTO_X_1000T; ++ break; ++ case 0: ++ default: ++ phy_data |= M88E1000_PSCR_AUTO_X_MODE; ++ break; ++ } ++ ++ /* ++ * Options: ++ * disable_polarity_correction = 0 (default) ++ * Automatic Correction for Reversed Cable Polarity ++ * 0 - Disabled ++ * 1 - Enabled ++ */ ++ phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; ++ if (phy->disable_polarity_correction == 1) ++ phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; ++ ++ /* Enable downshift on BM (disabled by default) */ ++ if (phy->type == e1000_phy_bm) ++ phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; ++ ++ ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ if ((phy->type == e1000_phy_m88) && ++ (phy->revision < E1000_REVISION_4) && ++ (phy->id != BME1000_E_PHY_ID_R2)) { ++ /* ++ * Force TX_CLK in the Extended PHY Specific Control Register ++ * to 25MHz clock. ++ */ ++ ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, ++ &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data |= M88E1000_EPSCR_TX_CLK_25; ++ ++ if ((phy->revision == E1000_REVISION_2) && ++ (phy->id == M88E1111_I_PHY_ID)) { ++ /* 82573L PHY - set the downshift counter to 5x. */ ++ phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; ++ phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; ++ } else { ++ /* Configure Master and Slave downshift values */ ++ phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | ++ M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); ++ phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | ++ M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); ++ } ++ ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, ++ phy_data); ++ if (ret_val) ++ goto out; ++ } ++ ++ if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { ++ /* Set PHY page 0, register 29 to 0x0003 */ ++ ret_val = e1e_wphy(hw, 29, 0x0003); ++ if (ret_val) ++ goto out; ++ ++ /* Set PHY page 0, register 30 to 0x0000 */ ++ ret_val = e1e_wphy(hw, 30, 0x0000); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* Commit the changes. */ ++ ret_val = e1000e_commit_phy(hw); ++ if (ret_val) { ++ e_dbg("Error committing the PHY changes\n"); ++ goto out; ++ } ++ ++ if (phy->type == e1000_phy_82578) { ++ ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, ++ &phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* 82578 PHY - set the downshift count to 1x. */ ++ phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; ++ phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; ++ ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, ++ phy_data); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link ++ * @hw: pointer to the HW structure ++ * ++ * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for ++ * igp PHY's. ++ **/ ++s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ ++ if (phy->reset_disable) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ ret_val = e1000_phy_hw_reset(hw); ++ if (ret_val) { ++ e_dbg("Error resetting the PHY.\n"); ++ goto out; ++ } ++ ++ /* ++ * Wait 100ms for MAC to configure PHY from NVM settings, to avoid ++ * timeout issues when LFS is enabled. ++ */ ++ msleep(100); ++ ++ /* ++ * The NVM settings will configure LPLU in D3 for ++ * non-IGP1 PHYs. ++ */ ++ if (phy->type == e1000_phy_igp) { ++ /* disable lplu d3 during driver init */ ++ ret_val = hw->phy.ops.set_d3_lplu_state(hw, false); ++ if (ret_val) { ++ e_dbg("Error Disabling LPLU D3\n"); ++ goto out; ++ } ++ } ++ ++ /* disable lplu d0 during driver init */ ++ if (hw->phy.ops.set_d0_lplu_state) { ++ ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); ++ if (ret_val) { ++ e_dbg("Error Disabling LPLU D0\n"); ++ goto out; ++ } ++ } ++ /* Configure mdi-mdix settings */ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCR_AUTO_MDIX; ++ ++ switch (phy->mdix) { ++ case 1: ++ data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; ++ break; ++ case 2: ++ data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; ++ break; ++ case 0: ++ default: ++ data |= IGP01E1000_PSCR_AUTO_MDIX; ++ break; ++ } ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); ++ if (ret_val) ++ goto out; ++ ++ /* set auto-master slave resolution settings */ ++ if (hw->mac.autoneg) { ++ /* ++ * when autonegotiation advertisement is only 1000Mbps then we ++ * should disable SmartSpeed and enable Auto MasterSlave ++ * resolution as hardware default. ++ */ ++ if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { ++ /* Disable SmartSpeed */ ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ ++ /* Set auto Master/Slave resolution process */ ++ ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~CR_1000T_MS_ENABLE; ++ ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ /* load defaults for future use */ ++ phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? ++ ((data & CR_1000T_MS_VALUE) ? ++ e1000_ms_force_master : ++ e1000_ms_force_slave) : ++ e1000_ms_auto; ++ ++ switch (phy->ms_type) { ++ case e1000_ms_force_master: ++ data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); ++ break; ++ case e1000_ms_force_slave: ++ data |= CR_1000T_MS_ENABLE; ++ data &= ~(CR_1000T_MS_VALUE); ++ break; ++ case e1000_ms_auto: ++ data &= ~CR_1000T_MS_ENABLE; ++ default: ++ break; ++ } ++ ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link ++ * @hw: pointer to the HW structure ++ * ++ * Performs initial bounds checking on autoneg advertisement parameter, then ++ * configure to advertise the full capability. Setup the PHY to autoneg ++ * and restart the negotiation process between the link partner. If ++ * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. ++ **/ ++static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_ctrl; ++ ++ /* ++ * Perform some bounds checking on the autoneg advertisement ++ * parameter. ++ */ ++ phy->autoneg_advertised &= phy->autoneg_mask; ++ ++ /* ++ * If autoneg_advertised is zero, we assume it was not defaulted ++ * by the calling code so we set to advertise full capability. ++ */ ++ if (phy->autoneg_advertised == 0) ++ phy->autoneg_advertised = phy->autoneg_mask; ++ ++ e_dbg("Reconfiguring auto-neg advertisement params\n"); ++ ret_val = e1000_phy_setup_autoneg(hw); ++ if (ret_val) { ++ e_dbg("Error Setting up Auto-Negotiation\n"); ++ goto out; ++ } ++ e_dbg("Restarting Auto-Neg\n"); ++ ++ /* ++ * Restart auto-negotiation by setting the Auto Neg Enable bit and ++ * the Auto Neg Restart bit in the PHY control register. ++ */ ++ ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); ++ if (ret_val) ++ goto out; ++ ++ phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); ++ ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Does the user want to wait for Auto-Neg to complete here, or ++ * check at a later time (for example, callback routine). ++ */ ++ if (phy->autoneg_wait_to_complete) { ++ ret_val = hw->mac.ops.wait_autoneg(hw); ++ if (ret_val) { ++ e_dbg("Error while waiting for " ++ "autoneg to complete\n"); ++ goto out; ++ } ++ } ++ ++ hw->mac.get_link_status = true; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation ++ * @hw: pointer to the HW structure ++ * ++ * Reads the MII auto-neg advertisement register and/or the 1000T control ++ * register and if the PHY is already setup for auto-negotiation, then ++ * return successful. Otherwise, setup advertisement and flow control to ++ * the appropriate values for the wanted auto-negotiation. ++ **/ ++static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 mii_autoneg_adv_reg; ++ u16 mii_1000t_ctrl_reg = 0; ++ ++ phy->autoneg_advertised &= phy->autoneg_mask; ++ ++ /* Read the MII Auto-Neg Advertisement Register (Address 4). */ ++ ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); ++ if (ret_val) ++ goto out; ++ ++ if (phy->autoneg_mask & ADVERTISE_1000_FULL) { ++ /* Read the MII 1000Base-T Control Register (Address 9). */ ++ ret_val = e1e_rphy(hw, PHY_1000T_CTRL, ++ &mii_1000t_ctrl_reg); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* ++ * Need to parse both autoneg_advertised and fc and set up ++ * the appropriate PHY registers. First we will parse for ++ * autoneg_advertised software override. Since we can advertise ++ * a plethora of combinations, we need to check each bit ++ * individually. ++ */ ++ ++ /* ++ * First we clear all the 10/100 mb speed bits in the Auto-Neg ++ * Advertisement Register (Address 4) and the 1000 mb speed bits in ++ * the 1000Base-T Control Register (Address 9). ++ */ ++ mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | ++ NWAY_AR_100TX_HD_CAPS | ++ NWAY_AR_10T_FD_CAPS | ++ NWAY_AR_10T_HD_CAPS); ++ mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); ++ ++ e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); ++ ++ /* Do we want to advertise 10 Mb Half Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_10_HALF) { ++ e_dbg("Advertise 10mb Half duplex\n"); ++ mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; ++ } ++ ++ /* Do we want to advertise 10 Mb Full Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_10_FULL) { ++ e_dbg("Advertise 10mb Full duplex\n"); ++ mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; ++ } ++ ++ /* Do we want to advertise 100 Mb Half Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_100_HALF) { ++ e_dbg("Advertise 100mb Half duplex\n"); ++ mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; ++ } ++ ++ /* Do we want to advertise 100 Mb Full Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_100_FULL) { ++ e_dbg("Advertise 100mb Full duplex\n"); ++ mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; ++ } ++ ++ /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ ++ if (phy->autoneg_advertised & ADVERTISE_1000_HALF) ++ e_dbg("Advertise 1000mb Half duplex request denied!\n"); ++ ++ /* Do we want to advertise 1000 Mb Full Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { ++ e_dbg("Advertise 1000mb Full duplex\n"); ++ mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; ++ } ++ ++ /* ++ * Check for a software override of the flow control settings, and ++ * setup the PHY advertisement registers accordingly. If ++ * auto-negotiation is enabled, then software will have to set the ++ * "PAUSE" bits to the correct value in the Auto-Negotiation ++ * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- ++ * negotiation. ++ * ++ * The possible values of the "fc" parameter are: ++ * 0: Flow control is completely disabled ++ * 1: Rx flow control is enabled (we can receive pause frames ++ * but not send pause frames). ++ * 2: Tx flow control is enabled (we can send pause frames ++ * but we do not support receiving pause frames). ++ * 3: Both Rx and Tx flow control (symmetric) are enabled. ++ * other: No software override. The flow control configuration ++ * in the EEPROM is used. ++ */ ++ switch (hw->fc.current_mode) { ++ case e1000_fc_none: ++ /* ++ * Flow control (Rx & Tx) is completely disabled by a ++ * software over-ride. ++ */ ++ mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ++ break; ++ case e1000_fc_rx_pause: ++ /* ++ * Rx Flow control is enabled, and Tx Flow control is ++ * disabled, by a software over-ride. ++ * ++ * Since there really isn't a way to advertise that we are ++ * capable of Rx Pause ONLY, we will advertise that we ++ * support both symmetric and asymmetric Rx PAUSE. Later ++ * (in e1000e_config_fc_after_link_up) we will disable the ++ * hw's ability to send PAUSE frames. ++ */ ++ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ++ break; ++ case e1000_fc_tx_pause: ++ /* ++ * Tx Flow control is enabled, and Rx Flow control is ++ * disabled, by a software over-ride. ++ */ ++ mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; ++ mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; ++ break; ++ case e1000_fc_full: ++ /* ++ * Flow control (both Rx and Tx) is enabled by a software ++ * over-ride. ++ */ ++ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ++ break; ++ default: ++ e_dbg("Flow control param set incorrectly\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); ++ if (ret_val) ++ goto out; ++ ++ e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); ++ ++ if (phy->autoneg_mask & ADVERTISE_1000_FULL) { ++ ret_val = e1e_wphy(hw, ++ PHY_1000T_CTRL, ++ mii_1000t_ctrl_reg); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_setup_copper_link - Configure copper link settings ++ * @hw: pointer to the HW structure ++ * ++ * Calls the appropriate function to configure the link for auto-neg or forced ++ * speed and duplex. Then we check for link, once link is established calls ++ * to configure collision distance and flow control are called. If link is ++ * not established, we return -E1000_ERR_PHY (-2). ++ **/ ++s32 e1000e_setup_copper_link(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ bool link; ++ ++ if (hw->mac.autoneg) { ++ /* ++ * Setup autoneg and flow control advertisement and perform ++ * autonegotiation. ++ */ ++ ret_val = e1000_copper_link_autoneg(hw); ++ if (ret_val) ++ goto out; ++ } else { ++ /* ++ * PHY will be set to 10H, 10F, 100H or 100F ++ * depending on user settings. ++ */ ++ e_dbg("Forcing Speed and Duplex\n"); ++ ret_val = hw->phy.ops.force_speed_duplex(hw); ++ if (ret_val) { ++ e_dbg("Error Forcing Speed and Duplex\n"); ++ goto out; ++ } ++ } ++ ++ /* ++ * Check link status. Wait up to 100 microseconds for link to become ++ * valid. ++ */ ++ ret_val = e1000e_phy_has_link_generic(hw, ++ COPPER_LINK_UP_LIMIT, ++ 10, ++ &link); ++ if (ret_val) ++ goto out; ++ ++ if (link) { ++ e_dbg("Valid link established!!!\n"); ++ e1000e_config_collision_dist(hw); ++ ret_val = e1000e_config_fc_after_link_up(hw); ++ } else { ++ e_dbg("Unable to establish link!!!\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY ++ * @hw: pointer to the HW structure ++ * ++ * Calls the PHY setup function to force speed and duplex. Clears the ++ * auto-crossover to force MDI manually. Waits for link and returns ++ * successful if link up is successful, else -E1000_ERR_PHY (-2). ++ **/ ++s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ bool link; ++ ++ ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ e1000e_phy_force_speed_duplex_setup(hw, &phy_data); ++ ++ ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Clear Auto-Crossover to force MDI manually. IGP requires MDI ++ * forced whenever speed and duplex are forced. ++ */ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; ++ phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; ++ ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ e_dbg("IGP PSCR: %X\n", phy_data); ++ ++ udelay(1); ++ ++ if (phy->autoneg_wait_to_complete) { ++ e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); ++ ++ ret_val = e1000e_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) ++ e_dbg("Link taking longer than expected.\n"); ++ ++ /* Try once more */ ++ ret_val = e1000e_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY ++ * @hw: pointer to the HW structure ++ * ++ * Calls the PHY setup function to force speed and duplex. Clears the ++ * auto-crossover to force MDI manually. Resets the PHY to commit the ++ * changes. If time expires while waiting for link up, we reset the DSP. ++ * After reset, TX_CLK and CRS on Tx must be set. Return successful upon ++ * successful completion, else return corresponding error code. ++ **/ ++s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ bool link; ++ ++ /* ++ * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI ++ * forced whenever speed and duplex are forced. ++ */ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; ++ ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ e_dbg("M88E1000 PSCR: %X\n", phy_data); ++ ++ ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ e1000e_phy_force_speed_duplex_setup(hw, &phy_data); ++ ++ ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* Reset the phy to commit changes. */ ++ ret_val = e1000e_commit_phy(hw); ++ if (ret_val) ++ goto out; ++ ++ if (phy->autoneg_wait_to_complete) { ++ e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); ++ ++ ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ 100000, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ /* ++ * We didn't get link. ++ * Reset the DSP and cross our fingers. ++ */ ++ ret_val = e1e_wphy(hw, ++ M88E1000_PHY_PAGE_SELECT, ++ 0x001d); ++ if (ret_val) ++ goto out; ++ ret_val = e1000e_phy_reset_dsp(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* Try once more */ ++ ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ 100000, &link); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Resetting the phy means we need to re-force TX_CLK in the ++ * Extended PHY Specific Control Register to 25MHz clock from ++ * the reset value of 2.5MHz. ++ */ ++ phy_data |= M88E1000_EPSCR_TX_CLK_25; ++ ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * In addition, we must re-enable CRS on Tx for both half and full ++ * duplex. ++ */ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; ++ ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex ++ * @hw: pointer to the HW structure ++ * ++ * Forces the speed and duplex settings of the PHY. ++ * This is a function pointer entry point only called by ++ * PHY setup routines. ++ **/ ++s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ bool link; ++ ++ if (phy->type != e1000_phy_ife) { ++ ret_val = e1000e_phy_force_speed_duplex_igp(hw); ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, PHY_CONTROL, &data); ++ if (ret_val) ++ goto out; ++ ++ e1000e_phy_force_speed_duplex_setup(hw, &data); ++ ++ ret_val = e1e_wphy(hw, PHY_CONTROL, data); ++ if (ret_val) ++ goto out; ++ ++ /* Disable MDI-X support for 10/100 */ ++ ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IFE_PMC_AUTO_MDIX; ++ data &= ~IFE_PMC_FORCE_MDIX; ++ ++ ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); ++ if (ret_val) ++ goto out; ++ ++ e_dbg("IFE PMC: %X\n", data); ++ ++ udelay(1); ++ ++ if (phy->autoneg_wait_to_complete) { ++ e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); ++ ++ ret_val = e1000e_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) ++ e_dbg("Link taking longer than expected.\n"); ++ ++ /* Try once more */ ++ ret_val = e1000e_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex ++ * @hw: pointer to the HW structure ++ * @phy_ctrl: pointer to current value of PHY_CONTROL ++ * ++ * Forces speed and duplex on the PHY by doing the following: disable flow ++ * control, force speed/duplex on the MAC, disable auto speed detection, ++ * disable auto-negotiation, configure duplex, configure speed, configure ++ * the collision distance, write configuration to CTRL register. The ++ * caller must write to the PHY_CONTROL register for these settings to ++ * take affect. ++ **/ ++void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 ctrl; ++ ++ /* Turn off flow control when forcing speed/duplex */ ++ hw->fc.current_mode = e1000_fc_none; ++ ++ /* Force speed/duplex on the mac */ ++ ctrl = er32(CTRL); ++ ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ ctrl &= ~E1000_CTRL_SPD_SEL; ++ ++ /* Disable Auto Speed Detection */ ++ ctrl &= ~E1000_CTRL_ASDE; ++ ++ /* Disable autoneg on the phy */ ++ *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; ++ ++ /* Forcing Full or Half Duplex? */ ++ if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { ++ ctrl &= ~E1000_CTRL_FD; ++ *phy_ctrl &= ~MII_CR_FULL_DUPLEX; ++ e_dbg("Half Duplex\n"); ++ } else { ++ ctrl |= E1000_CTRL_FD; ++ *phy_ctrl |= MII_CR_FULL_DUPLEX; ++ e_dbg("Full Duplex\n"); ++ } ++ ++ /* Forcing 10mb or 100mb? */ ++ if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { ++ ctrl |= E1000_CTRL_SPD_100; ++ *phy_ctrl |= MII_CR_SPEED_100; ++ *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); ++ e_dbg("Forcing 100mb\n"); ++ } else { ++ ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); ++ *phy_ctrl |= MII_CR_SPEED_10; ++ *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); ++ e_dbg("Forcing 10mb\n"); ++ } ++ ++ e1000e_config_collision_dist(hw); ++ ++ ew32(CTRL, ctrl); ++} ++ ++/** ++ * e1000e_set_d3_lplu_state - Sets low power link up state for D3 ++ * @hw: pointer to the HW structure ++ * @active: boolean used to enable/disable lplu ++ * ++ * Success returns 0, Failure returns 1 ++ * ++ * The low power link up (lplu) state is set to the power management level D3 ++ * and SmartSpeed is disabled when active is true, else clear lplu for D3 ++ * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU ++ * is used during Dx states where the power conservation is most important. ++ * During driver activity, SmartSpeed should be enabled so performance is ++ * maintained. ++ **/ ++s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 data; ++ ++ if (!(hw->phy.ops.read_reg)) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); ++ if (ret_val) ++ goto out; ++ ++ if (!active) { ++ data &= ~IGP02E1000_PM_D3_LPLU; ++ ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, ++ data); ++ if (ret_val) ++ goto out; ++ /* ++ * LPLU and SmartSpeed are mutually exclusive. LPLU is used ++ * during Dx states where the power conservation is most ++ * important. During driver activity we should enable ++ * SmartSpeed, so performance is maintained. ++ */ ++ if (phy->smart_speed == e1000_smart_speed_on) { ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data |= IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } else if (phy->smart_speed == e1000_smart_speed_off) { ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } ++ } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || ++ (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || ++ (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { ++ data |= IGP02E1000_PM_D3_LPLU; ++ ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, ++ data); ++ if (ret_val) ++ goto out; ++ ++ /* When LPLU is enabled, we should disable SmartSpeed */ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_check_downshift - Checks whether a downshift in speed occurred ++ * @hw: pointer to the HW structure ++ * ++ * Success returns 0, Failure returns 1 ++ * ++ * A downshift is detected by querying the PHY link health. ++ **/ ++s32 e1000e_check_downshift(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data, offset, mask; ++ ++ switch (phy->type) { ++ case e1000_phy_m88: ++ case e1000_phy_gg82563: ++ case e1000_phy_bm: ++ case e1000_phy_82578: ++ case e1000_phy_82577: ++ offset = M88E1000_PHY_SPEC_STATUS; ++ mask = M88E1000_PSSR_DOWNSHIFT; ++ break; ++ case e1000_phy_igp_2: ++ case e1000_phy_igp: ++ case e1000_phy_igp_3: ++ offset = IGP01E1000_PHY_LINK_HEALTH; ++ mask = IGP01E1000_PLHR_SS_DOWNGRADE; ++ break; ++ default: ++ /* speed downshift not supported */ ++ phy->speed_downgraded = false; ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, offset, &phy_data); ++ ++ if (!ret_val) ++ phy->speed_downgraded = (phy_data & mask) ? true : false; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_polarity_m88 - Checks the polarity. ++ * @hw: pointer to the HW structure ++ * ++ * Success returns 0, Failure returns -E1000_ERR_PHY (-2) ++ * ++ * Polarity is determined based on the PHY specific status register. ++ **/ ++s32 e1000_check_polarity_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); ++ ++ if (!ret_val) ++ phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_check_polarity_igp - Checks the polarity. ++ * @hw: pointer to the HW structure ++ * ++ * Success returns 0, Failure returns -E1000_ERR_PHY (-2) ++ * ++ * Polarity is determined based on the PHY port status register, and the ++ * current speed (since there is no polarity at 100Mbps). ++ **/ ++s32 e1000_check_polarity_igp(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data, offset, mask; ++ ++ /* ++ * Polarity is determined based on the speed of ++ * our connection. ++ */ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); ++ if (ret_val) ++ goto out; ++ ++ if ((data & IGP01E1000_PSSR_SPEED_MASK) == ++ IGP01E1000_PSSR_SPEED_1000MBPS) { ++ offset = IGP01E1000_PHY_PCS_INIT_REG; ++ mask = IGP01E1000_PHY_POLARITY_MASK; ++ } else { ++ /* ++ * This really only applies to 10Mbps since ++ * there is no polarity for 100Mbps (always 0). ++ */ ++ offset = IGP01E1000_PHY_PORT_STATUS; ++ mask = IGP01E1000_PSSR_POLARITY_REVERSED; ++ } ++ ++ ret_val = e1e_rphy(hw, offset, &data); ++ ++ if (!ret_val) ++ phy->cable_polarity = (data & mask) ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_polarity_ife - Check cable polarity for IFE PHY ++ * @hw: pointer to the HW structure ++ * ++ * Polarity is determined on the polarity reversal feature being enabled. ++ **/ ++s32 e1000_check_polarity_ife(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data, offset, mask; ++ ++ /* ++ * Polarity is determined based on the reversal feature being enabled. ++ */ ++ if (phy->polarity_correction) { ++ offset = IFE_PHY_EXTENDED_STATUS_CONTROL; ++ mask = IFE_PESC_POLARITY_REVERSED; ++ } else { ++ offset = IFE_PHY_SPECIAL_CONTROL; ++ mask = IFE_PSC_FORCE_POLARITY; ++ } ++ ++ ret_val = e1e_rphy(hw, offset, &phy_data); ++ ++ if (!ret_val) ++ phy->cable_polarity = (phy_data & mask) ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_wait_autoneg - Wait for auto-neg completion ++ * @hw: pointer to the HW structure ++ * ++ * Waits for auto-negotiation to complete or for the auto-negotiation time ++ * limit to expire, which ever happens first. ++ **/ ++s32 e1000_wait_autoneg(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 i, phy_status; ++ ++ if (!(hw->phy.ops.read_reg)) ++ return E1000_SUCCESS; ++ ++ /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ ++ for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { ++ ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); ++ if (ret_val) ++ break; ++ ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); ++ if (ret_val) ++ break; ++ if (phy_status & MII_SR_AUTONEG_COMPLETE) ++ break; ++ msleep(100); ++ } ++ ++ /* ++ * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation ++ * has completed. ++ */ ++ return ret_val; ++} ++ ++/** ++ * e1000e_phy_has_link_generic - Polls PHY for link ++ * @hw: pointer to the HW structure ++ * @iterations: number of times to poll for link ++ * @usec_interval: delay between polling attempts ++ * @success: pointer to whether polling was successful or not ++ * ++ * Polls the PHY status register for link, 'iterations' number of times. ++ **/ ++s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, ++ u32 usec_interval, bool *success) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 i, phy_status; ++ ++ if (!(hw->phy.ops.read_reg)) ++ return E1000_SUCCESS; ++ ++ for (i = 0; i < iterations; i++) { ++ /* ++ * Some PHYs require the PHY_STATUS register to be read ++ * twice due to the link bit being sticky. No harm doing ++ * it across the board. ++ */ ++ ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); ++ if (ret_val) ++ /* ++ * If the first read fails, another entity may have ++ * ownership of the resources, wait and try again to ++ * see if they have relinquished the resources yet. ++ */ ++ udelay(usec_interval); ++ ret_val = e1e_rphy(hw, PHY_STATUS, ++ &phy_status); ++ if (ret_val) ++ break; ++ if (phy_status & MII_SR_LINK_STATUS) ++ break; ++ if (usec_interval >= 1000) ++ mdelay(usec_interval/1000); ++ else ++ udelay(usec_interval); ++ } ++ ++ *success = (i < iterations) ? true : false; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY ++ * @hw: pointer to the HW structure ++ * ++ * Reads the PHY specific status register to retrieve the cable length ++ * information. The cable length is determined by averaging the minimum and ++ * maximum values to get the "average" cable length. The m88 PHY has four ++ * possible cable length values, which are: ++ * Register Value Cable Length ++ * 0 < 50 meters ++ * 1 50 - 80 meters ++ * 2 80 - 110 meters ++ * 3 110 - 140 meters ++ * 4 > 140 meters ++ **/ ++s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data, index; ++ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> ++ M88E1000_PSSR_CABLE_LENGTH_SHIFT; ++ if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE + 1) { ++ ret_val = E1000_ERR_PHY; ++ goto out; ++ } ++ ++ phy->min_cable_length = e1000_m88_cable_length_table[index]; ++ phy->max_cable_length = e1000_m88_cable_length_table[index+1]; ++ ++ phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY ++ * @hw: pointer to the HW structure ++ * ++ * The automatic gain control (agc) normalizes the amplitude of the ++ * received signal, adjusting for the attenuation produced by the ++ * cable. By reading the AGC registers, which represent the ++ * combination of coarse and fine gain value, the value can be put ++ * into a lookup table to obtain the approximate cable length ++ * for each channel. ++ **/ ++s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 phy_data, i, agc_value = 0; ++ u16 cur_agc_index, max_agc_index = 0; ++ u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; ++ u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = ++ {IGP02E1000_PHY_AGC_A, ++ IGP02E1000_PHY_AGC_B, ++ IGP02E1000_PHY_AGC_C, ++ IGP02E1000_PHY_AGC_D}; ++ ++ /* Read the AGC registers for all channels */ ++ for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { ++ ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Getting bits 15:9, which represent the combination of ++ * coarse and fine gain values. The result is a number ++ * that can be put into the lookup table to obtain the ++ * approximate cable length. ++ */ ++ cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & ++ IGP02E1000_AGC_LENGTH_MASK; ++ ++ /* Array index bound check. */ ++ if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || ++ (cur_agc_index == 0)) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++ /* Remove min & max AGC values from calculation. */ ++ if (e1000_igp_2_cable_length_table[min_agc_index] > ++ e1000_igp_2_cable_length_table[cur_agc_index]) ++ min_agc_index = cur_agc_index; ++ if (e1000_igp_2_cable_length_table[max_agc_index] < ++ e1000_igp_2_cable_length_table[cur_agc_index]) ++ max_agc_index = cur_agc_index; ++ ++ agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; ++ } ++ ++ agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + ++ e1000_igp_2_cable_length_table[max_agc_index]); ++ agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); ++ ++ /* Calculate cable length with the error range of +/- 10 meters. */ ++ phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? ++ (agc_value - IGP02E1000_AGC_RANGE) : 0; ++ phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; ++ ++ phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_get_phy_info_m88 - Retrieve PHY information ++ * @hw: pointer to the HW structure ++ * ++ * Valid for only copper links. Read the PHY status register (sticky read) ++ * to verify that link is up. Read the PHY special control register to ++ * determine the polarity and 10base-T extended distance. Read the PHY ++ * special status register to determine MDI/MDIx and current speed. If ++ * speed is 1000, then determine cable length, local and remote receiver. ++ **/ ++s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ bool link; ++ ++ if (hw->phy.media_type != e1000_media_type_copper) { ++ e_dbg("Phy info is only valid for copper media\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ e_dbg("Phy info is only valid if link is up\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) ++ ? true : false; ++ ++ ret_val = e1000_check_polarity_m88(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; ++ ++ if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { ++ ret_val = e1000_get_cable_length(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ ++ phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ } else { ++ /* Set values to "undefined" */ ++ phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; ++ phy->local_rx = e1000_1000t_rx_status_undefined; ++ phy->remote_rx = e1000_1000t_rx_status_undefined; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_get_phy_info_igp - Retrieve igp PHY information ++ * @hw: pointer to the HW structure ++ * ++ * Read PHY status to determine if link is up. If link is up, then ++ * set/determine 10base-T extended distance and polarity correction. Read ++ * PHY port status to determine MDI/MDIx and speed. Based on the speed, ++ * determine on the cable length, local and remote receiver. ++ **/ ++s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ bool link; ++ ++ ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ e_dbg("Phy info is only valid if link is up\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ phy->polarity_correction = true; ++ ++ ret_val = e1000_check_polarity_igp(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); ++ if (ret_val) ++ goto out; ++ ++ phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; ++ ++ if ((data & IGP01E1000_PSSR_SPEED_MASK) == ++ IGP01E1000_PSSR_SPEED_1000MBPS) { ++ ret_val = e1000_get_cable_length(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); ++ if (ret_val) ++ goto out; ++ ++ phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ ++ phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ } else { ++ phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; ++ phy->local_rx = e1000_1000t_rx_status_undefined; ++ phy->remote_rx = e1000_1000t_rx_status_undefined; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_phy_sw_reset - PHY software reset ++ * @hw: pointer to the HW structure ++ * ++ * Does a software reset of the PHY by reading the PHY control register and ++ * setting/write the control register reset bit to the PHY. ++ **/ ++s32 e1000e_phy_sw_reset(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 phy_ctrl; ++ ++ if (!(hw->phy.ops.read_reg)) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); ++ if (ret_val) ++ goto out; ++ ++ phy_ctrl |= MII_CR_RESET; ++ ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); ++ if (ret_val) ++ goto out; ++ ++ udelay(1); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_phy_hw_reset_generic - PHY hardware reset ++ * @hw: pointer to the HW structure ++ * ++ * Verify the reset block is not blocking us from resetting. Acquire ++ * semaphore (if necessary) and read/set/write the device control reset ++ * bit in the PHY. Wait the appropriate delay time for the device to ++ * reset and release the semaphore (if necessary). ++ **/ ++s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u32 ctrl; ++ ++ ret_val = e1000_check_reset_block(hw); ++ if (ret_val) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ ret_val = phy->ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ ctrl = er32(CTRL); ++ ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); ++ e1e_flush(); ++ ++ udelay(phy->reset_delay_us); ++ ++ ew32(CTRL, ctrl); ++ e1e_flush(); ++ ++ udelay(150); ++ ++ phy->ops.release(hw); ++ ++ ret_val = phy->ops.get_cfg_done(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_get_cfg_done - Generic configuration done ++ * @hw: pointer to the HW structure ++ * ++ * Generic function to wait 10 milli-seconds for configuration to complete ++ * and return success. ++ **/ ++s32 e1000e_get_cfg_done(struct e1000_hw *hw) ++{ ++ mdelay(10); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_phy_init_script_igp3 - Inits the IGP3 PHY ++ * @hw: pointer to the HW structure ++ * ++ * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. ++ **/ ++s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) ++{ ++ e_dbg("Running IGP 3 PHY init script\n"); ++ ++ /* PHY init IGP 3 */ ++ /* Enable rise/fall, 10-mode work in class-A */ ++ e1e_wphy(hw, 0x2F5B, 0x9018); ++ /* Remove all caps from Replica path filter */ ++ e1e_wphy(hw, 0x2F52, 0x0000); ++ /* Bias trimming for ADC, AFE and Driver (Default) */ ++ e1e_wphy(hw, 0x2FB1, 0x8B24); ++ /* Increase Hybrid poly bias */ ++ e1e_wphy(hw, 0x2FB2, 0xF8F0); ++ /* Add 4% to Tx amplitude in Gig mode */ ++ e1e_wphy(hw, 0x2010, 0x10B0); ++ /* Disable trimming (TTT) */ ++ e1e_wphy(hw, 0x2011, 0x0000); ++ /* Poly DC correction to 94.6% + 2% for all channels */ ++ e1e_wphy(hw, 0x20DD, 0x249A); ++ /* ABS DC correction to 95.9% */ ++ e1e_wphy(hw, 0x20DE, 0x00D3); ++ /* BG temp curve trim */ ++ e1e_wphy(hw, 0x28B4, 0x04CE); ++ /* Increasing ADC OPAMP stage 1 currents to max */ ++ e1e_wphy(hw, 0x2F70, 0x29E4); ++ /* Force 1000 ( required for enabling PHY regs configuration) */ ++ e1e_wphy(hw, 0x0000, 0x0140); ++ /* Set upd_freq to 6 */ ++ e1e_wphy(hw, 0x1F30, 0x1606); ++ /* Disable NPDFE */ ++ e1e_wphy(hw, 0x1F31, 0xB814); ++ /* Disable adaptive fixed FFE (Default) */ ++ e1e_wphy(hw, 0x1F35, 0x002A); ++ /* Enable FFE hysteresis */ ++ e1e_wphy(hw, 0x1F3E, 0x0067); ++ /* Fixed FFE for short cable lengths */ ++ e1e_wphy(hw, 0x1F54, 0x0065); ++ /* Fixed FFE for medium cable lengths */ ++ e1e_wphy(hw, 0x1F55, 0x002A); ++ /* Fixed FFE for long cable lengths */ ++ e1e_wphy(hw, 0x1F56, 0x002A); ++ /* Enable Adaptive Clip Threshold */ ++ e1e_wphy(hw, 0x1F72, 0x3FB0); ++ /* AHT reset limit to 1 */ ++ e1e_wphy(hw, 0x1F76, 0xC0FF); ++ /* Set AHT master delay to 127 msec */ ++ e1e_wphy(hw, 0x1F77, 0x1DEC); ++ /* Set scan bits for AHT */ ++ e1e_wphy(hw, 0x1F78, 0xF9EF); ++ /* Set AHT Preset bits */ ++ e1e_wphy(hw, 0x1F79, 0x0210); ++ /* Change integ_factor of channel A to 3 */ ++ e1e_wphy(hw, 0x1895, 0x0003); ++ /* Change prop_factor of channels BCD to 8 */ ++ e1e_wphy(hw, 0x1796, 0x0008); ++ /* Change cg_icount + enable integbp for channels BCD */ ++ e1e_wphy(hw, 0x1798, 0xD008); ++ /* ++ * Change cg_icount + enable integbp + change prop_factor_master ++ * to 8 for channel A ++ */ ++ e1e_wphy(hw, 0x1898, 0xD918); ++ /* Disable AHT in Slave mode on channel A */ ++ e1e_wphy(hw, 0x187A, 0x0800); ++ /* ++ * Enable LPLU and disable AN to 1000 in non-D0a states, ++ * Enable SPD+B2B ++ */ ++ e1e_wphy(hw, 0x0019, 0x008D); ++ /* Enable restart AN on an1000_dis change */ ++ e1e_wphy(hw, 0x001B, 0x2080); ++ /* Enable wh_fifo read clock in 10/100 modes */ ++ e1e_wphy(hw, 0x0014, 0x0045); ++ /* Restart AN, Speed selection is 1000 */ ++ e1e_wphy(hw, 0x0000, 0x1340); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000e_get_phy_type_from_id - Get PHY type from id ++ * @phy_id: phy_id read from the phy ++ * ++ * Returns the phy type from the id. ++ **/ ++enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) ++{ ++ enum e1000_phy_type phy_type = e1000_phy_unknown; ++ ++ switch (phy_id) { ++ case M88E1000_I_PHY_ID: ++ case M88E1000_E_PHY_ID: ++ case M88E1111_I_PHY_ID: ++ case M88E1011_I_PHY_ID: ++ phy_type = e1000_phy_m88; ++ break; ++ case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ ++ phy_type = e1000_phy_igp_2; ++ break; ++ case GG82563_E_PHY_ID: ++ phy_type = e1000_phy_gg82563; ++ break; ++ case IGP03E1000_E_PHY_ID: ++ phy_type = e1000_phy_igp_3; ++ break; ++ case IFE_E_PHY_ID: ++ case IFE_PLUS_E_PHY_ID: ++ case IFE_C_E_PHY_ID: ++ phy_type = e1000_phy_ife; ++ break; ++ case BME1000_E_PHY_ID: ++ case BME1000_E_PHY_ID_R2: ++ phy_type = e1000_phy_bm; ++ break; ++ case I82578_E_PHY_ID: ++ phy_type = e1000_phy_82578; ++ break; ++ case I82577_E_PHY_ID: ++ phy_type = e1000_phy_82577; ++ break; ++ default: ++ phy_type = e1000_phy_unknown; ++ break; ++ } ++ return phy_type; ++} ++ ++/** ++ * e1000e_determine_phy_address - Determines PHY address. ++ * @hw: pointer to the HW structure ++ * ++ * This uses a trial and error method to loop through possible PHY ++ * addresses. It tests each by reading the PHY ID registers and ++ * checking for a match. ++ **/ ++s32 e1000e_determine_phy_address(struct e1000_hw *hw) ++{ ++ s32 ret_val = -E1000_ERR_PHY_TYPE; ++ u32 phy_addr = 0; ++ u32 i; ++ enum e1000_phy_type phy_type = e1000_phy_unknown; ++ ++ hw->phy.id = phy_type; ++ ++ for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { ++ hw->phy.addr = phy_addr; ++ i = 0; ++ ++ do { ++ e1000e_get_phy_id(hw); ++ phy_type = e1000e_get_phy_type_from_id(hw->phy.id); ++ ++ /* ++ * If phy_type is valid, break - we found our ++ * PHY address ++ */ ++ if (phy_type != e1000_phy_unknown) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ msleep(1); ++ i++; ++ } while (i < 10); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address ++ * @page: page to access ++ * ++ * Returns the phy address for the page requested. ++ **/ ++static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) ++{ ++ u32 phy_addr = 2; ++ ++ if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) ++ phy_addr = 1; ++ ++ return phy_addr; ++} ++ ++/** ++ * e1000e_write_phy_reg_bm - Write BM PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary, then writes the data to PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ s32 ret_val; ++ u32 page_select = 0; ++ u32 page = offset >> IGP_PAGE_SHIFT; ++ u32 page_shift = 0; ++ ++ /* Page 800 works differently than the rest so it has its own func */ ++ if (page == BM_WUC_PAGE) { ++ ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, ++ false); ++ goto out; ++ } ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ /* ++ * Page select is register 31 for phy address 1 and 22 for ++ * phy address 2 and 3. Page select is shifted only for ++ * phy address 1. ++ */ ++ if (hw->phy.addr == 1) { ++ page_shift = IGP_PAGE_SHIFT; ++ page_select = IGP01E1000_PHY_PAGE_SELECT; ++ } else { ++ page_shift = 0; ++ page_select = BM_PHY_PAGE_SELECT; ++ } ++ ++ /* Page is shifted left, PHY expects (page x 32) */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, page_select, ++ (page << page_shift)); ++ if (ret_val) { ++ hw->phy.ops.release(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_read_phy_reg_bm - Read BM PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retrieved information in data. Release any acquired ++ * semaphores before exiting. ++ **/ ++s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ s32 ret_val; ++ u32 page_select = 0; ++ u32 page = offset >> IGP_PAGE_SHIFT; ++ u32 page_shift = 0; ++ ++ /* Page 800 works differently than the rest so it has its own func */ ++ if (page == BM_WUC_PAGE) { ++ ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, ++ true); ++ goto out; ++ } ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ /* ++ * Page select is register 31 for phy address 1 and 22 for ++ * phy address 2 and 3. Page select is shifted only for ++ * phy address 1. ++ */ ++ if (hw->phy.addr == 1) { ++ page_shift = IGP_PAGE_SHIFT; ++ page_select = IGP01E1000_PHY_PAGE_SELECT; ++ } else { ++ page_shift = 0; ++ page_select = BM_PHY_PAGE_SELECT; ++ } ++ ++ /* Page is shifted left, PHY expects (page x 32) */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, page_select, ++ (page << page_shift)); ++ if (ret_val) { ++ hw->phy.ops.release(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_read_phy_reg_bm2 - Read BM PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retrieved information in data. Release any acquired ++ * semaphores before exiting. ++ **/ ++s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ s32 ret_val; ++ u16 page = (u16)(offset >> IGP_PAGE_SHIFT); ++ ++ /* Page 800 works differently than the rest so it has its own func */ ++ if (page == BM_WUC_PAGE) { ++ ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, ++ true); ++ goto out; ++ } ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ hw->phy.addr = 1; ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ ++ /* Page is shifted left, PHY expects (page x 32) */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, ++ page); ++ ++ if (ret_val) { ++ hw->phy.ops.release(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_write_phy_reg_bm2 - Write BM PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary, then writes the data to PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ s32 ret_val; ++ u16 page = (u16)(offset >> IGP_PAGE_SHIFT); ++ ++ /* Page 800 works differently than the rest so it has its own func */ ++ if (page == BM_WUC_PAGE) { ++ ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, ++ false); ++ goto out; ++ } ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ hw->phy.addr = 1; ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ /* Page is shifted left, PHY expects (page x 32) */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, ++ page); ++ ++ if (ret_val) { ++ hw->phy.ops.release(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read or written ++ * @data: pointer to the data to read or write ++ * @read: determines if operation is read or write ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retrieved information in data. Release any acquired ++ * semaphores before exiting. Note that procedure to read the wakeup ++ * registers are different. It works as such: ++ * 1) Set page 769, register 17, bit 2 = 1 ++ * 2) Set page to 800 for host (801 if we were manageability) ++ * 3) Write the address using the address opcode (0x11) ++ * 4) Read or write the data using the data opcode (0x12) ++ * 5) Restore 769_17.2 to its original value ++ **/ ++static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, ++ u16 *data, bool read) ++{ ++ s32 ret_val; ++ u16 reg = BM_PHY_REG_NUM(offset); ++ u16 phy_reg = 0; ++ u8 phy_acquired = 1; ++ ++ /* Gig must be disabled for MDIO accesses to page 800 */ ++ if ((hw->mac.type == e1000_pchlan) && ++ (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) ++ e_dbg("Attempting to access page 800 while gig enabled.\n"); ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) { ++ e_dbg("Could not acquire PHY\n"); ++ phy_acquired = 0; ++ goto out; ++ } ++ ++ /* All operations in this function are phy address 1 */ ++ hw->phy.addr = 1; ++ ++ /* Set page 769 */ ++ e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, ++ (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); ++ ++ ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); ++ if (ret_val) { ++ e_dbg("Could not read PHY page 769\n"); ++ goto out; ++ } ++ ++ /* First clear bit 4 to avoid a power state change */ ++ phy_reg &= ~(BM_WUC_HOST_WU_BIT); ++ ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); ++ if (ret_val) { ++ e_dbg("Could not clear PHY page 769 bit 4\n"); ++ goto out; ++ } ++ ++ /* Write bit 2 = 1, and clear bit 4 to 769_17 */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, ++ phy_reg | BM_WUC_ENABLE_BIT); ++ if (ret_val) { ++ e_dbg("Could not write PHY page 769 bit 2\n"); ++ goto out; ++ } ++ ++ /* Select page 800 */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, ++ IGP01E1000_PHY_PAGE_SELECT, ++ (BM_WUC_PAGE << IGP_PAGE_SHIFT)); ++ ++ /* Write the page 800 offset value using opcode 0x11 */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); ++ if (ret_val) { ++ e_dbg("Could not write address opcode to page 800\n"); ++ goto out; ++ } ++ ++ if (read) { ++ /* Read the page 800 value using opcode 0x12 */ ++ ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, ++ data); ++ } else { ++ /* Write the page 800 value using opcode 0x12 */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, ++ *data); ++ } ++ ++ if (ret_val) { ++ e_dbg("Could not access data value from page 800\n"); ++ goto out; ++ } ++ ++ /* ++ * Restore 769_17.2 to its original value ++ * Set page 769 ++ */ ++ e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, ++ (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); ++ ++ /* Clear 769_17.2 */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); ++ if (ret_val) { ++ e_dbg("Could not clear PHY page 769 bit 2\n"); ++ goto out; ++ } ++ ++out: ++ if (phy_acquired == 1) ++ hw->phy.ops.release(hw); ++ return ret_val; ++} ++ ++/** ++ * e1000_power_up_phy_copper - Restore copper link in case of PHY power down ++ * @hw: pointer to the HW structure ++ * ++ * In the case of a PHY power down to save power, or to turn off link during a ++ * driver unload, or wake on lan is not enabled, restore the link to previous ++ * settings. ++ **/ ++void e1000_power_up_phy_copper(struct e1000_hw *hw) ++{ ++ u16 mii_reg = 0; ++ ++ /* The PHY will retain its settings across a power down/up cycle */ ++ e1e_rphy(hw, PHY_CONTROL, &mii_reg); ++ mii_reg &= ~MII_CR_POWER_DOWN; ++ e1e_wphy(hw, PHY_CONTROL, mii_reg); ++} ++ ++/** ++ * e1000_power_down_phy_copper - Restore copper link in case of PHY power down ++ * @hw: pointer to the HW structure ++ * ++ * In the case of a PHY power down to save power, or to turn off link during a ++ * driver unload, or wake on lan is not enabled, restore the link to previous ++ * settings. ++ **/ ++void e1000_power_down_phy_copper(struct e1000_hw *hw) ++{ ++ u16 mii_reg = 0; ++ ++ /* The PHY will retain its settings across a power down/up cycle */ ++ e1e_rphy(hw, PHY_CONTROL, &mii_reg); ++ mii_reg |= MII_CR_POWER_DOWN; ++ e1e_wphy(hw, PHY_CONTROL, mii_reg); ++ msleep(1); ++} ++ ++s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 data = 0; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ return ret_val; ++ ++ /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */ ++ hw->phy.addr = 1; ++ ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, ++ (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); ++ if (ret_val) { ++ hw->phy.ops.release(hw); ++ return ret_val; ++ } ++ ret_val = e1000e_write_phy_reg_mdic(hw, BM_CS_CTRL1, ++ (0x2180 | (slow << 10))); ++ ++ /* dummy read when reverting to fast mode - throw away result */ ++ if (!slow) ++ e1000e_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data); ++ ++ hw->phy.ops.release(hw); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_read_phy_reg_hv - Read HV PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retrieved information in data. Release any acquired ++ * semaphore before exiting. ++ **/ ++s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ s32 ret_val; ++ u16 page = BM_PHY_REG_PAGE(offset); ++ u16 reg = BM_PHY_REG_NUM(offset); ++ bool in_slow_mode = false; ++ ++ /* Workaround failure in MDIO access while cable is disconnected */ ++ if ((hw->phy.type == e1000_phy_82577) && ++ !(er32(STATUS) & E1000_STATUS_LU)) { ++ ret_val = e1000_set_mdio_slow_mode_hv(hw, true); ++ if (ret_val) ++ goto out; ++ ++ in_slow_mode = true; ++ } ++ ++ /* Page 800 works differently than the rest so it has its own func */ ++ if (page == BM_WUC_PAGE) { ++ ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, ++ data, true); ++ goto out; ++ } ++ ++ if (page > 0 && page < HV_INTC_FC_PAGE_START) { ++ ret_val = e1000_access_phy_debug_regs_hv(hw, offset, ++ data, true); ++ goto out; ++ } ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); ++ ++ if (page == HV_INTC_FC_PAGE_START) ++ page = 0; ++ ++ if (reg > MAX_PHY_MULTI_PAGE_REG) { ++ if ((hw->phy.type != e1000_phy_82578) || ++ ((reg != I82578_ADDR_REG) && ++ (reg != I82578_ADDR_REG + 1))) { ++ u32 phy_addr = hw->phy.addr; ++ ++ hw->phy.addr = 1; ++ ++ /* Page is shifted left, PHY expects (page x 32) */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, ++ IGP01E1000_PHY_PAGE_SELECT, ++ (page << IGP_PAGE_SHIFT)); ++ if (ret_val) { ++ hw->phy.ops.release(hw); ++ goto out; ++ } ++ hw->phy.addr = phy_addr; ++ } ++ } ++ ++ ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, ++ data); ++ hw->phy.ops.release(hw); ++ ++out: ++ /* Revert to MDIO fast mode, if applicable */ ++ if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) ++ ret_val = e1000_set_mdio_slow_mode_hv(hw, false); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_write_phy_reg_hv - Write HV PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary, then writes the data to PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ s32 ret_val; ++ u16 page = BM_PHY_REG_PAGE(offset); ++ u16 reg = BM_PHY_REG_NUM(offset); ++ bool in_slow_mode = false; ++ ++ /* Workaround failure in MDIO access while cable is disconnected */ ++ if ((hw->phy.type == e1000_phy_82577) && ++ !(er32(STATUS) & E1000_STATUS_LU)) { ++ ret_val = e1000_set_mdio_slow_mode_hv(hw, true); ++ if (ret_val) ++ goto out; ++ ++ in_slow_mode = true; ++ } ++ ++ /* Page 800 works differently than the rest so it has its own func */ ++ if (page == BM_WUC_PAGE) { ++ ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, ++ &data, false); ++ goto out; ++ } ++ ++ if (page > 0 && page < HV_INTC_FC_PAGE_START) { ++ ret_val = e1000_access_phy_debug_regs_hv(hw, offset, ++ &data, false); ++ goto out; ++ } ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); ++ ++ if (page == HV_INTC_FC_PAGE_START) ++ page = 0; ++ ++ /* ++ * Workaround MDIO accesses being disabled after entering IEEE Power ++ * Down (whenever bit 11 of the PHY Control register is set) ++ */ ++ if ((hw->phy.type == e1000_phy_82578) && ++ (hw->phy.revision >= 1) && ++ (hw->phy.addr == 2) && ++ ((MAX_PHY_REG_ADDRESS & reg) == 0) && ++ (data & (1 << 11))) { ++ u16 data2 = 0x7EFF; ++ hw->phy.ops.release(hw); ++ ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, ++ &data2, false); ++ if (ret_val) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ if (reg > MAX_PHY_MULTI_PAGE_REG) { ++ if ((hw->phy.type != e1000_phy_82578) || ++ ((reg != I82578_ADDR_REG) && ++ (reg != I82578_ADDR_REG + 1))) { ++ u32 phy_addr = hw->phy.addr; ++ ++ hw->phy.addr = 1; ++ ++ /* Page is shifted left, PHY expects (page x 32) */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, ++ IGP01E1000_PHY_PAGE_SELECT, ++ (page << IGP_PAGE_SHIFT)); ++ if (ret_val) { ++ hw->phy.ops.release(hw); ++ goto out; ++ } ++ hw->phy.addr = phy_addr; ++ } ++ } ++ ++ ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, ++ data); ++ hw->phy.ops.release(hw); ++ ++out: ++ /* Revert to MDIO fast mode, if applicable */ ++ if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) ++ ret_val = e1000_set_mdio_slow_mode_hv(hw, false); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page ++ * @page: page to be accessed ++ **/ ++static u32 e1000_get_phy_addr_for_hv_page(u32 page) ++{ ++ u32 phy_addr = 2; ++ ++ if (page >= HV_INTC_FC_PAGE_START) ++ phy_addr = 1; ++ ++ return phy_addr; ++} ++ ++/** ++ * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read or written ++ * @data: pointer to the data to be read or written ++ * @read: determines if operation is read or written ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retreived information in data. Release any acquired ++ * semaphores before exiting. Note that the procedure to read these regs ++ * uses the address port and data port to read/write. ++ **/ ++static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, ++ u16 *data, bool read) ++{ ++ s32 ret_val; ++ u32 addr_reg = 0; ++ u32 data_reg = 0; ++ u8 phy_acquired = 1; ++ ++ /* This takes care of the difference with desktop vs mobile phy */ ++ addr_reg = (hw->phy.type == e1000_phy_82578) ? ++ I82578_ADDR_REG : I82577_ADDR_REG; ++ data_reg = addr_reg + 1; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) { ++ e_dbg("Could not acquire PHY\n"); ++ phy_acquired = 0; ++ goto out; ++ } ++ ++ /* All operations in this function are phy address 2 */ ++ hw->phy.addr = 2; ++ ++ /* masking with 0x3F to remove the page from offset */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); ++ if (ret_val) { ++ e_dbg("Could not write PHY the HV address register\n"); ++ goto out; ++ } ++ ++ /* Read or write the data value next */ ++ if (read) ++ ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); ++ else ++ ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); ++ ++ if (ret_val) { ++ e_dbg("Could not read data value from HV data register\n"); ++ goto out; ++ } ++ ++out: ++ if (phy_acquired == 1) ++ hw->phy.ops.release(hw); ++ return ret_val; ++} ++ ++/** ++ * e1000_link_stall_workaround_hv - Si workaround ++ * @hw: pointer to the HW structure ++ * ++ * This function works around a Si bug where the link partner can get ++ * a link up indication before the PHY does. If small packets are sent ++ * by the link partner they can be placed in the packet buffer without ++ * being properly accounted for by the PHY and will stall preventing ++ * further packets from being received. The workaround is to clear the ++ * packet buffer after the PHY detects link up. ++ **/ ++s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 data; ++ ++ if (hw->phy.type != e1000_phy_82578) ++ goto out; ++ ++ /* Do not apply workaround if in PHY loopback bit 14 set */ ++ e1e_rphy(hw, PHY_CONTROL, &data); ++ if (data & PHY_CONTROL_LB) ++ goto out; ++ ++ /* check if link is up and at 1Gbps */ ++ ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= BM_CS_STATUS_LINK_UP | ++ BM_CS_STATUS_RESOLVED | ++ BM_CS_STATUS_SPEED_MASK; ++ ++ if (data != (BM_CS_STATUS_LINK_UP | ++ BM_CS_STATUS_RESOLVED | ++ BM_CS_STATUS_SPEED_1000)) ++ goto out; ++ ++ msleep(200); ++ ++ /* flush the packets in the fifo buffer */ ++ ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, ++ HV_MUX_DATA_CTRL_GEN_TO_MAC | ++ HV_MUX_DATA_CTRL_FORCE_SPEED); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, ++ HV_MUX_DATA_CTRL_GEN_TO_MAC); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_polarity_82577 - Checks the polarity. ++ * @hw: pointer to the HW structure ++ * ++ * Success returns 0, Failure returns -E1000_ERR_PHY (-2) ++ * ++ * Polarity is determined based on the PHY specific status register. ++ **/ ++s32 e1000_check_polarity_82577(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ ++ ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); ++ ++ if (!ret_val) ++ phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY ++ * @hw: pointer to the HW structure ++ * ++ * Calls the PHY setup function to force speed and duplex. Clears the ++ * auto-crossover to force MDI manually. Waits for link and returns ++ * successful if link up is successful, else -E1000_ERR_PHY (-2). ++ **/ ++s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ bool link; ++ ++ ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ e1000e_phy_force_speed_duplex_setup(hw, &phy_data); ++ ++ ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Clear Auto-Crossover to force MDI manually. 82577 requires MDI ++ * forced whenever speed and duplex are forced. ++ */ ++ ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX; ++ phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX; ++ ++ ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data); ++ if (ret_val) ++ goto out; ++ ++ e_dbg("I82577_PHY_CTRL_2: %X\n", phy_data); ++ ++ udelay(1); ++ ++ if (phy->autoneg_wait_to_complete) { ++ e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); ++ ++ ret_val = e1000e_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) ++ e_dbg("Link taking longer than expected.\n"); ++ ++ /* Try once more */ ++ ret_val = e1000e_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_phy_info_82577 - Retrieve I82577 PHY information ++ * @hw: pointer to the HW structure ++ * ++ * Read PHY status to determine if link is up. If link is up, then ++ * set/determine 10base-T extended distance and polarity correction. Read ++ * PHY port status to determine MDI/MDIx and speed. Based on the speed, ++ * determine on the cable length, local and remote receiver. ++ **/ ++s32 e1000_get_phy_info_82577(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ bool link; ++ ++ ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ e_dbg("Phy info is only valid if link is up\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ phy->polarity_correction = true; ++ ++ ret_val = e1000_check_polarity_82577(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); ++ if (ret_val) ++ goto out; ++ ++ phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false; ++ ++ if ((data & I82577_PHY_STATUS2_SPEED_MASK) == ++ I82577_PHY_STATUS2_SPEED_1000MBPS) { ++ ret_val = e1000_get_cable_length(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); ++ if (ret_val) ++ goto out; ++ ++ phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ ++ phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ } else { ++ phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; ++ phy->local_rx = e1000_1000t_rx_status_undefined; ++ phy->remote_rx = e1000_1000t_rx_status_undefined; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY ++ * @hw: pointer to the HW structure ++ * ++ * Reads the diagnostic status register and verifies result is valid before ++ * placing it in the phy_cable_length field. ++ **/ ++s32 e1000_get_cable_length_82577(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data, length; ++ ++ ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> ++ I82577_DSTATUS_CABLE_LENGTH_SHIFT; ++ ++ if (length == E1000_CABLE_LENGTH_UNDEFINED) ++ ret_val = E1000_ERR_PHY; ++ ++ phy->cable_length = length; ++ ++out: ++ return ret_val; ++} +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_phy.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_phy.h Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,238 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_PHY_H_ ++#define _E1000_PHY_H_ ++ ++void e1000_init_phy_ops_generic(struct e1000_hw *hw); ++s32 e1000e_check_downshift(struct e1000_hw *hw); ++s32 e1000_check_polarity_m88(struct e1000_hw *hw); ++s32 e1000_check_polarity_igp(struct e1000_hw *hw); ++s32 e1000_check_polarity_ife(struct e1000_hw *hw); ++s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); ++s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); ++s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); ++s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); ++s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); ++s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); ++s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); ++s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); ++s32 e1000e_get_cfg_done(struct e1000_hw *hw); ++s32 e1000e_get_phy_id(struct e1000_hw *hw); ++s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); ++s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); ++s32 e1000e_phy_sw_reset(struct e1000_hw *hw); ++void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); ++s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); ++s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); ++s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); ++s32 e1000e_setup_copper_link(struct e1000_hw *hw); ++s32 e1000_wait_autoneg(struct e1000_hw *hw); ++s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_phy_reset_dsp(struct e1000_hw *hw); ++s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, ++ u32 usec_interval, bool *success); ++s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); ++enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); ++s32 e1000e_determine_phy_address(struct e1000_hw *hw); ++s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); ++void e1000_power_up_phy_copper(struct e1000_hw *hw); ++void e1000_power_down_phy_copper(struct e1000_hw *hw); ++s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow); ++s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); ++s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); ++s32 e1000_check_polarity_82577(struct e1000_hw *hw); ++s32 e1000_get_phy_info_82577(struct e1000_hw *hw); ++s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); ++s32 e1000_get_cable_length_82577(struct e1000_hw *hw); ++ ++#define E1000_MAX_PHY_ADDR 4 ++ ++/* IGP01E1000 Specific Registers */ ++#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ ++#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ ++#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ ++#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ ++#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ ++#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ ++#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ ++#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ ++#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ ++#define IGP_PAGE_SHIFT 5 ++#define PHY_REG_MASK 0x1F ++ ++/* BM/HV Specific Registers */ ++#define BM_PORT_CTRL_PAGE 769 ++#define BM_PCIE_PAGE 770 ++#define BM_WUC_PAGE 800 ++#define BM_WUC_ADDRESS_OPCODE 0x11 ++#define BM_WUC_DATA_OPCODE 0x12 ++#define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE ++#define BM_WUC_ENABLE_REG 17 ++#define BM_WUC_ENABLE_BIT (1 << 2) ++#define BM_WUC_HOST_WU_BIT (1 << 4) ++ ++#define PHY_UPPER_SHIFT 21 ++#define BM_PHY_REG(page, reg) \ ++ (((reg) & MAX_PHY_REG_ADDRESS) |\ ++ (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ ++ (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) ++#define BM_PHY_REG_PAGE(offset) \ ++ ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) ++#define BM_PHY_REG_NUM(offset) \ ++ ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ ++ (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ ++ ~MAX_PHY_REG_ADDRESS))) ++ ++#define HV_INTC_FC_PAGE_START 768 ++#define I82578_ADDR_REG 29 ++#define I82577_ADDR_REG 16 ++#define I82577_CFG_REG 22 ++#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) ++#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ ++#define I82577_CTRL_REG 23 ++#define I82577_CTRL_DOWNSHIFT_MASK (7 << 10) ++ ++/* 82577 specific PHY registers */ ++#define I82577_PHY_CTRL_2 18 ++#define I82577_PHY_LBK_CTRL 19 ++#define I82577_PHY_STATUS_2 26 ++#define I82577_PHY_DIAG_STATUS 31 ++ ++/* I82577 PHY Status 2 */ ++#define I82577_PHY_STATUS2_REV_POLARITY 0x0400 ++#define I82577_PHY_STATUS2_MDIX 0x0800 ++#define I82577_PHY_STATUS2_SPEED_MASK 0x0300 ++#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 ++#define I82577_PHY_STATUS2_SPEED_100MBPS 0x0100 ++ ++/* I82577 PHY Control 2 */ ++#define I82577_PHY_CTRL2_AUTO_MDIX 0x0400 ++#define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 ++ ++/* I82577 PHY Diagnostics Status */ ++#define I82577_DSTATUS_CABLE_LENGTH 0x03FC ++#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 ++ ++/* BM PHY Copper Specific Control 1 */ ++#define BM_CS_CTRL1 16 ++#define BM_CS_CTRL1_ENERGY_DETECT 0x0300 /* Enable Energy Detect */ ++ ++/* BM PHY Copper Specific Status */ ++#define BM_CS_STATUS 17 ++#define BM_CS_STATUS_ENERGY_DETECT 0x0010 /* Energy Detect Status */ ++#define BM_CS_STATUS_LINK_UP 0x0400 ++#define BM_CS_STATUS_RESOLVED 0x0800 ++#define BM_CS_STATUS_SPEED_MASK 0xC000 ++#define BM_CS_STATUS_SPEED_1000 0x8000 ++ ++#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 ++#define IGP01E1000_PHY_POLARITY_MASK 0x0078 ++ ++#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 ++#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ ++ ++#define IGP01E1000_PSCFR_SMART_SPEED 0x0080 ++ ++/* Enable flexible speed on link-up */ ++#define IGP01E1000_GMII_FLEX_SPD 0x0010 ++#define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */ ++ ++#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ ++#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ ++#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ ++ ++#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 ++ ++#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 ++#define IGP01E1000_PSSR_MDIX 0x0800 ++#define IGP01E1000_PSSR_SPEED_MASK 0xC000 ++#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 ++ ++#define IGP02E1000_PHY_CHANNEL_NUM 4 ++#define IGP02E1000_PHY_AGC_A 0x11B1 ++#define IGP02E1000_PHY_AGC_B 0x12B1 ++#define IGP02E1000_PHY_AGC_C 0x14B1 ++#define IGP02E1000_PHY_AGC_D 0x18B1 ++ ++#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ ++#define IGP02E1000_AGC_LENGTH_MASK 0x7F ++#define IGP02E1000_AGC_RANGE 15 ++ ++#define IGP03E1000_PHY_MISC_CTRL 0x1B ++#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */ ++ ++#define E1000_CABLE_LENGTH_UNDEFINED 0xFF ++ ++#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 ++#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 ++#define E1000_KMRNCTRLSTA_REN 0x00200000 ++#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ ++#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ ++#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ ++#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ ++#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 ++#define E1000_KMRNCTRLSTA_K1_ENABLE 0x140E ++#define E1000_KMRNCTRLSTA_K1_DISABLE 0x1400 ++ ++#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 ++#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */ ++#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */ ++#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ ++ ++/* IFE PHY Extended Status Control */ ++#define IFE_PESC_POLARITY_REVERSED 0x0100 ++ ++/* IFE PHY Special Control */ ++#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 ++#define IFE_PSC_FORCE_POLARITY 0x0020 ++#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 ++ ++/* IFE PHY Special Control and LED Control */ ++#define IFE_PSCL_PROBE_MODE 0x0020 ++#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ ++#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ ++ ++/* IFE PHY MDIX Control */ ++#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ ++#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ ++#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */ ++ ++#endif +diff -r 5638ec0574f5 drivers/net/e1000e/e1000_regs.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/e1000_regs.h Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,338 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_REGS_H_ ++#define _E1000_REGS_H_ ++ ++#define E1000_CTRL 0x00000 /* Device Control - RW */ ++#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ ++#define E1000_STATUS 0x00008 /* Device Status - RO */ ++#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ ++#define E1000_EERD 0x00014 /* EEPROM Read - RW */ ++#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ ++#define E1000_FLA 0x0001C /* Flash Access - RW */ ++#define E1000_MDIC 0x00020 /* MDI Control - RW */ ++#define E1000_SCTL 0x00024 /* SerDes Control - RW */ ++#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ ++#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ ++#define E1000_FEXT 0x0002C /* Future Extended - RW */ ++#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ ++#define E1000_FCT 0x00030 /* Flow Control Type - RW */ ++#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ ++#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ ++#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ ++#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ ++#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ ++#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ ++#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ ++#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ ++#define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ ++#define E1000_SVCR 0x000F0 ++#define E1000_SVT 0x000F4 ++#define E1000_RCTL 0x00100 /* Rx Control - RW */ ++#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ ++#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ ++#define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ ++#define E1000_PBA_ECC 0x01100 /* PBA ECC Register */ ++#define E1000_TCTL 0x00400 /* Tx Control - RW */ ++#define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */ ++#define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */ ++#define E1000_TBT 0x00448 /* Tx Burst Timer - RW */ ++#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ ++#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ ++#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ ++#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ ++#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ ++#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ ++#define E1000_PBS 0x01008 /* Packet Buffer Size */ ++#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ ++#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ ++#define E1000_FLASHT 0x01028 /* FLASH Timer Register */ ++#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ ++#define E1000_FLSWCTL 0x01030 /* FLASH control register */ ++#define E1000_FLSWDATA 0x01034 /* FLASH data register */ ++#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ ++#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ ++#define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */ ++#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */ ++#define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */ ++#define E1000_SWDSTS 0x01044 /* SW Device Status - RW */ ++#define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */ ++#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ ++#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ ++#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ ++#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ ++#define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n))) ++#define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */ ++#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ ++/* Split and Replication Rx Control - RW */ ++#define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */ ++#define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */ ++#define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */ ++#define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */ ++#define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */ ++#define E1000_RXCTL(_n) (0x0C014 + (0x40 * (_n))) ++#define E1000_RQDPC(_n) (0x0C030 + (0x40 * (_n))) ++#define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ ++#define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ ++/* ++ * Convenience macros ++ * ++ * Note: "_n" is the queue number of the register to be written to. ++ * ++ * Example usage: ++ * E1000_RDBAL_REG(current_rx_queue) ++ */ ++#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \ ++ (0x0C000 + ((_n) * 0x40))) ++#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ ++ (0x0C004 + ((_n) * 0x40))) ++#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ ++ (0x0C008 + ((_n) * 0x40))) ++#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \ ++ (0x0C00C + ((_n) * 0x40))) ++#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ ++ (0x0C010 + ((_n) * 0x40))) ++#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ ++ (0x0C018 + ((_n) * 0x40))) ++#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ ++ (0x0C028 + ((_n) * 0x40))) ++#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ ++ (0x0E000 + ((_n) * 0x40))) ++#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ ++ (0x0E004 + ((_n) * 0x40))) ++#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ ++ (0x0E008 + ((_n) * 0x40))) ++#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ ++ (0x0E010 + ((_n) * 0x40))) ++#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ ++ (0x0E018 + ((_n) * 0x40))) ++#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ ++ (0x0E028 + ((_n) * 0x40))) ++#define E1000_TARC(_n) (0x03840 + (_n << 8)) ++#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) ++#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) ++#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \ ++ (0x0E038 + ((_n) * 0x40))) ++#define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \ ++ (0x0E03C + ((_n) * 0x40))) ++#define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */ ++#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ ++#define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */ ++#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ ++#define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) ++#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ ++ (0x054E0 + ((_i - 16) * 8))) ++#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ ++ (0x054E4 + ((_i - 16) * 8))) ++#define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) ++#define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) ++#define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) ++#define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) ++#define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) ++#define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) ++#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ ++#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ ++#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ ++#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ ++#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ ++#define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */ ++#define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */ ++#define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */ ++#define E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */ ++#define E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */ ++#define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */ ++#define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */ ++#define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */ ++#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ ++#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ ++#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ ++#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ ++#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ ++#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ ++#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ ++#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ ++#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ ++#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ ++#define E1000_COLC 0x04028 /* Collision Count - R/clr */ ++#define E1000_DC 0x04030 /* Defer Count - R/clr */ ++#define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */ ++#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ ++#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ ++#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ ++#define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */ ++#define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */ ++#define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */ ++#define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */ ++#define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */ ++#define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */ ++#define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */ ++#define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */ ++#define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */ ++#define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */ ++#define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */ ++#define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */ ++#define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */ ++#define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */ ++#define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */ ++#define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */ ++#define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */ ++#define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */ ++#define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */ ++#define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */ ++#define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */ ++#define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */ ++#define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */ ++#define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */ ++#define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */ ++#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ ++#define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */ ++#define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */ ++#define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */ ++#define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */ ++#define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */ ++#define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */ ++#define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */ ++#define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */ ++#define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */ ++#define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */ ++#define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */ ++#define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */ ++#define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */ ++#define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */ ++#define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */ ++#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */ ++#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */ ++#define E1000_IAC 0x04100 /* Interrupt Assertion Count */ ++#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ ++#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ ++#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ ++#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ ++#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ ++#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ ++#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ ++#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ ++/* ++ * The CRC offset register is undocumented because it is for future use and ++ * may change in the future. ++ */ ++#define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */ ++ ++#define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ ++#define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ ++#define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ ++#define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */ ++#define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */ ++#define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */ ++#define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */ ++#define E1000_RPTHC 0x04104 /* Rx Packets To Host */ ++#define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */ ++#define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */ ++#define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */ ++#define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */ ++#define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */ ++#define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */ ++#define E1000_LENERRS 0x04138 /* Length Errors Count */ ++#define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */ ++#define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */ ++#define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ ++#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ ++#define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ ++#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */ ++#define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Packet Count - RW */ ++#define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */ ++#define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */ ++#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ ++#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ ++#define E1000_RA 0x05400 /* Receive Address - RW Array */ ++#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ ++#define E1000_VT_CTL 0x0581C /* VMDq Control - RW */ ++#define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */ ++#define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */ ++#define E1000_WUC 0x05800 /* Wakeup Control - RW */ ++#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ ++#define E1000_WUS 0x05810 /* Wakeup Status - RO */ ++#define E1000_MANC 0x05820 /* Management Control - RW */ ++#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ ++#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ ++#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ ++#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ ++#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ ++#define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */ ++#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ ++#define E1000_HOST_IF 0x08800 /* Host Interface */ ++#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ ++#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ ++ ++#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ ++#define E1000_MDPHYA 0x0003C /* PHY address - RW */ ++#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ ++#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ ++#define E1000_CCMCTL 0x05B48 /* CCM Control Register */ ++#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ ++#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ ++#define E1000_GCR 0x05B00 /* PCI-Ex Control */ ++#define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ ++#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ ++#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ ++#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ ++#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ ++#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ ++#define E1000_SWSM 0x05B50 /* SW Semaphore */ ++#define E1000_FWSM 0x05B54 /* FW Semaphore */ ++#define E1000_SWSM2 0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */ ++#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ ++#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ ++#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ ++#define E1000_HICR 0x08F00 /* Host Interface Control */ ++ ++/* RSS registers */ ++#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ ++#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ ++#define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ ++#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/ ++#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */ ++#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register ++ * (_i) - RW */ ++#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr ++ * low reg - RW */ ++#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr ++ * upper reg - RW */ ++#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry ++ * message reg - RW */ ++#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry ++ * vector ctrl reg - RW */ ++#define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */ ++#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ ++#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ ++#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ ++#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ ++#define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ ++#define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ ++ ++#endif +diff -r 5638ec0574f5 drivers/net/e1000e/es2lan.c +--- a/drivers/net/e1000e/es2lan.c Tue Sep 01 13:47:57 2009 +0100 ++++ b/drivers/net/e1000e/es2lan.c Tue Sep 01 13:48:50 2009 +0100 +@@ -86,6 +86,9 @@ + + /* Kumeran Mode Control Register (Page 193, Register 16) */ + #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 ++ ++/* Max number of times Kumeran read/write should be validated */ ++#define GG82563_MAX_KMRN_RETRY 0x5 + + /* Max number of times Kumeran read/write should be validated */ + #define GG82563_MAX_KMRN_RETRY 0x5 +@@ -798,7 +801,7 @@ + ret_val = e1000e_id_led_init(hw); + if (ret_val) { + hw_dbg(hw, "Error initializing identification LED\n"); +- return ret_val; ++ /* This is not fatal and we should not stop init due to this */ + } + + /* Disabling VLAN filtering */ +diff -r 5638ec0574f5 drivers/net/e1000e/ethtool.c +--- a/drivers/net/e1000e/ethtool.c Tue Sep 01 13:47:57 2009 +0100 ++++ b/drivers/net/e1000e/ethtool.c Tue Sep 01 13:48:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel PRO/1000 Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -29,11 +29,18 @@ + /* ethtool support for e1000 */ + + #include ++#ifdef SIOCETHTOOL + #include + #include + #include + + #include "e1000.h" ++#ifdef NETIF_F_HW_VLAN_TX ++#include ++#endif ++#ifdef ETHTOOL_OPS_COMPAT ++#include "kcompat_ethtool.c" ++#endif + + struct e1000_stats { + char stat_string[ETH_GSTRING_LEN]; +@@ -54,6 +61,9 @@ + { "tx_multicast", E1000_STAT(stats.mptc) }, + { "rx_errors", E1000_STAT(net_stats.rx_errors) }, + { "tx_errors", E1000_STAT(net_stats.tx_errors) }, ++#ifndef CONFIG_E1000E_NAPI ++ { "rx_dropped_backlog", E1000_STAT(rx_dropped_backlog) }, ++#endif + { "tx_dropped", E1000_STAT(net_stats.tx_dropped) }, + { "multicast", E1000_STAT(stats.mprc) }, + { "collisions", E1000_STAT(stats.colc) }, +@@ -173,11 +183,8 @@ + static u32 e1000_get_link(struct net_device *netdev) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; +- u32 status; +- +- status = er32(STATUS); +- return (status & E1000_STATUS_LU) ? 1 : 0; ++ ++ return e1000_has_link(adapter); + } + + static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx) +@@ -248,8 +255,15 @@ + ADVERTISED_TP | + ADVERTISED_Autoneg; + ecmd->advertising = hw->phy.autoneg_advertised; +- if (adapter->fc_autoneg) +- hw->fc.original_type = e1000_fc_default; ++ if (adapter->fc_autoneg) { ++ if (hw->mac.type == e1000_pchlan) { ++ /* Workaround h/w hang when Tx flow control ++ * enabled */ ++ hw->fc.requested_mode = e1000_fc_rx_pause; ++ } else { ++ hw->fc.requested_mode = e1000_fc_default; ++ } ++ } + } else { + if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) { + clear_bit(__E1000_RESETTING, &adapter->state); +@@ -279,11 +293,11 @@ + pause->autoneg = + (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); + +- if (hw->fc.type == e1000_fc_rx_pause) { ++ if (hw->fc.current_mode == e1000_fc_rx_pause) { + pause->rx_pause = 1; +- } else if (hw->fc.type == e1000_fc_tx_pause) { ++ } else if (hw->fc.current_mode == e1000_fc_tx_pause) { + pause->tx_pause = 1; +- } else if (hw->fc.type == e1000_fc_full) { ++ } else if (hw->fc.current_mode == e1000_fc_full) { + pause->rx_pause = 1; + pause->tx_pause = 1; + } +@@ -301,19 +315,13 @@ + while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) + msleep(1); + +- if (pause->rx_pause && pause->tx_pause) +- hw->fc.type = e1000_fc_full; +- else if (pause->rx_pause && !pause->tx_pause) +- hw->fc.type = e1000_fc_rx_pause; +- else if (!pause->rx_pause && pause->tx_pause) +- hw->fc.type = e1000_fc_tx_pause; +- else if (!pause->rx_pause && !pause->tx_pause) +- hw->fc.type = e1000_fc_none; +- +- hw->fc.original_type = hw->fc.type; +- + if (adapter->fc_autoneg == AUTONEG_ENABLE) { +- hw->fc.type = e1000_fc_default; ++ if (hw->mac.type == e1000_pchlan) { ++ /* Workaround h/w hang when Tx flow control enabled */ ++ hw->fc.requested_mode = e1000_fc_rx_pause; ++ } else { ++ hw->fc.requested_mode = e1000_fc_default; ++ } + if (netif_running(adapter->netdev)) { + e1000e_down(adapter); + e1000e_up(adapter); +@@ -321,6 +329,17 @@ + e1000e_reset(adapter); + } + } else { ++ if (pause->rx_pause && pause->tx_pause) ++ hw->fc.requested_mode = e1000_fc_full; ++ else if (pause->rx_pause && !pause->tx_pause) ++ hw->fc.requested_mode = e1000_fc_rx_pause; ++ else if (!pause->rx_pause && pause->tx_pause) ++ hw->fc.requested_mode = e1000_fc_tx_pause; ++ else if (!pause->rx_pause && !pause->tx_pause) ++ hw->fc.requested_mode = e1000_fc_none; ++ ++ hw->fc.current_mode = hw->fc.requested_mode; ++ + retval = ((hw->phy.media_type == e1000_media_type_fiber) ? + hw->mac.ops.setup_link(hw) : e1000e_force_mac_fc(hw)); + } +@@ -332,7 +351,7 @@ + static u32 e1000_get_rx_csum(struct net_device *netdev) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +- return (adapter->flags & FLAG_RX_CSUM_ENABLED); ++ return adapter->flags & FLAG_RX_CSUM_ENABLED; + } + + static int e1000_set_rx_csum(struct net_device *netdev, u32 data) +@@ -366,22 +385,47 @@ + return 0; + } + ++#ifdef NETIF_F_TSO + static int e1000_set_tso(struct net_device *netdev, u32 data) + { + struct e1000_adapter *adapter = netdev_priv(netdev); ++ int i; ++ struct net_device *v_netdev; + + if (data) { + netdev->features |= NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 + netdev->features |= NETIF_F_TSO6; ++#endif + } else { + netdev->features &= ~NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 + netdev->features &= ~NETIF_F_TSO6; ++#endif ++#ifdef NETIF_F_HW_VLAN_TX ++ /* disable TSO on all VLANs if they're present */ ++ if (!adapter->vlgrp) ++ goto tso_out; ++ for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) { ++ v_netdev = vlan_group_get_device(adapter->vlgrp, i); ++ if (!v_netdev) ++ continue; ++ ++ v_netdev->features &= ~NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 ++ v_netdev->features &= ~NETIF_F_TSO6; ++#endif ++ vlan_group_set_device(adapter->vlgrp, i, v_netdev); ++ } ++#endif + } + ++tso_out: + e_info("TSO is %s\n", data ? "Enabled" : "Disabled"); + adapter->flags |= FLAG_TSO_FORCE; + return 0; + } ++#endif + + static u32 e1000_get_msglevel(struct net_device *netdev) + { +@@ -420,15 +464,15 @@ + regs_buff[1] = er32(STATUS); + + regs_buff[2] = er32(RCTL); +- regs_buff[3] = er32(RDLEN); +- regs_buff[4] = er32(RDH); +- regs_buff[5] = er32(RDT); ++ regs_buff[3] = er32(RDLEN(0)); ++ regs_buff[4] = er32(RDH(0)); ++ regs_buff[5] = er32(RDT(0)); + regs_buff[6] = er32(RDTR); + + regs_buff[7] = er32(TCTL); +- regs_buff[8] = er32(TDLEN); +- regs_buff[9] = er32(TDH); +- regs_buff[10] = er32(TDT); ++ regs_buff[8] = er32(TDLEN(0)); ++ regs_buff[9] = er32(TDH(0)); ++ regs_buff[10] = er32(TDT(0)); + regs_buff[11] = er32(TIDV); + + regs_buff[12] = adapter->hw.phy.type; /* PHY type (IGP=1, M88=0) */ +@@ -494,19 +538,20 @@ + } else { + for (i = 0; i < last_word - first_word + 1; i++) { + ret_val = e1000_read_nvm(hw, first_word + i, 1, +- &eeprom_buff[i]); +- if (ret_val) { +- /* a read error occurred, throw away the +- * result */ +- memset(eeprom_buff, 0xff, sizeof(eeprom_buff)); ++ &eeprom_buff[i]); ++ if (ret_val) + break; +- } + } + } + +- /* Device's eeprom is always little-endian, word addressable */ +- for (i = 0; i < last_word - first_word + 1; i++) +- le16_to_cpus(&eeprom_buff[i]); ++ if (ret_val) { ++ /* a read error occurred, throw away the result */ ++ memset(eeprom_buff, 0xff, sizeof(eeprom_buff)); ++ } else { ++ /* Device's eeprom is always little-endian, word addressable */ ++ for (i = 0; i < last_word - first_word + 1; i++) ++ le16_to_cpus(&eeprom_buff[i]); ++ } + + memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); + kfree(eeprom_buff); +@@ -533,9 +578,6 @@ + if (eeprom->magic != (adapter->pdev->vendor | (adapter->pdev->device << 16))) + return -EFAULT; + +- if (adapter->flags & FLAG_READ_ONLY_NVM) +- return -EINVAL; +- + max_len = hw->nvm.word_size * 2; + + first_word = eeprom->offset >> 1; +@@ -558,6 +600,9 @@ + ret_val = e1000_read_nvm(hw, last_word, 1, + &eeprom_buff[last_word - first_word]); + ++ if (ret_val) ++ goto out; ++ + /* Device's eeprom is always little-endian, word addressable */ + for (i = 0; i < last_word - first_word + 1; i++) + le16_to_cpus(&eeprom_buff[i]); +@@ -570,15 +615,20 @@ + ret_val = e1000_write_nvm(hw, first_word, + last_word - first_word + 1, eeprom_buff); + ++ if (ret_val) ++ goto out; ++ + /* + * Update the checksum over the first part of the EEPROM if needed +- * and flush shadow RAM for 82573 controllers ++ * and flush shadow RAM for applicable controllers + */ +- if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG) || +- (hw->mac.type == e1000_82574) || +- (hw->mac.type == e1000_82573))) +- e1000e_update_nvm_checksum(hw); ++ if ((first_word <= NVM_CHECKSUM_REG) || ++ (hw->mac.type == e1000_82583) || ++ (hw->mac.type == e1000_82574) || ++ (hw->mac.type == e1000_82573)) ++ ret_val = e1000e_update_nvm_checksum(hw); + ++out: + kfree(eeprom_buff); + return ret_val; + } +@@ -588,7 +638,6 @@ + { + struct e1000_adapter *adapter = netdev_priv(netdev); + char firmware_version[32]; +- u16 eeprom_data; + + strncpy(drvinfo->driver, e1000e_driver_name, 32); + strncpy(drvinfo->version, e1000e_driver_version, 32); +@@ -597,11 +646,10 @@ + * EEPROM image version # is reported as firmware version # for + * PCI-E controllers + */ +- e1000_read_nvm(&adapter->hw, 5, 1, &eeprom_data); + sprintf(firmware_version, "%d.%d-%d", +- (eeprom_data & 0xF000) >> 12, +- (eeprom_data & 0x0FF0) >> 4, +- eeprom_data & 0x000F); ++ (adapter->eeprom_vers & 0xF000) >> 12, ++ (adapter->eeprom_vers & 0x0FF0) >> 4, ++ (adapter->eeprom_vers & 0x000F)); + + strncpy(drvinfo->fw_version, firmware_version, 32); + strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); +@@ -727,7 +775,7 @@ + (test[pat] & write)); + val = E1000_READ_REG_ARRAY(&adapter->hw, reg, offset); + if (val != (test[pat] & write & mask)) { +- e_err("pattern test reg %04X failed: got 0x%08X " ++ e_err("Register 0x%05X pattern test failed: got 0x%08X " + "expected 0x%08X\n", reg + offset, val, + (test[pat] & write & mask)); + *data = reg; +@@ -744,7 +792,7 @@ + __ew32(&adapter->hw, reg, write & mask); + val = __er32(&adapter->hw, reg); + if ((write & mask) != (val & mask)) { +- e_err("set/check reg %04X test failed: got 0x%08X " ++ e_err("Register 0x%05X set/check test failed: got 0x%08X " + "expected 0x%08X\n", reg, (val & mask), (write & mask)); + *data = reg; + return 1; +@@ -774,6 +822,7 @@ + u32 after; + u32 i; + u32 toggle; ++ u32 mask; + + /* + * The status register is Read Only, so a write should fail. +@@ -786,15 +835,8 @@ + case e1000_80003es2lan: + toggle = 0x7FFFF3FF; + break; +- case e1000_82573: +- case e1000_82574: +- case e1000_ich8lan: +- case e1000_ich9lan: +- case e1000_ich10lan: ++ default: + toggle = 0x7FFFF033; +- break; +- default: +- toggle = 0xFFFFF833; + break; + } + +@@ -819,15 +861,15 @@ + } + + REG_PATTERN_TEST(E1000_RDTR, 0x0000FFFF, 0xFFFFFFFF); +- REG_PATTERN_TEST(E1000_RDBAH, 0xFFFFFFFF, 0xFFFFFFFF); +- REG_PATTERN_TEST(E1000_RDLEN, 0x000FFF80, 0x000FFFFF); +- REG_PATTERN_TEST(E1000_RDH, 0x0000FFFF, 0x0000FFFF); +- REG_PATTERN_TEST(E1000_RDT, 0x0000FFFF, 0x0000FFFF); ++ REG_PATTERN_TEST(E1000_RDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_RDLEN(0), 0x000FFF80, 0x000FFFFF); ++ REG_PATTERN_TEST(E1000_RDH(0), 0x0000FFFF, 0x0000FFFF); ++ REG_PATTERN_TEST(E1000_RDT(0), 0x0000FFFF, 0x0000FFFF); + REG_PATTERN_TEST(E1000_FCRTH, 0x0000FFF8, 0x0000FFF8); + REG_PATTERN_TEST(E1000_FCTTV, 0x0000FFFF, 0x0000FFFF); + REG_PATTERN_TEST(E1000_TIPG, 0x3FFFFFFF, 0x3FFFFFFF); +- REG_PATTERN_TEST(E1000_TDBAH, 0xFFFFFFFF, 0xFFFFFFFF); +- REG_PATTERN_TEST(E1000_TDLEN, 0x000FFF80, 0x000FFFFF); ++ REG_PATTERN_TEST(E1000_TDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_TDLEN(0), 0x000FFF80, 0x000FFFFF); + + REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000); + +@@ -836,16 +878,23 @@ + REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000); + + REG_SET_AND_CHECK(E1000_RCTL, before, 0xFFFFFFFF); +- REG_PATTERN_TEST(E1000_RDBAL, 0xFFFFFFF0, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_RDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF); + if (!(adapter->flags & FLAG_IS_ICH)) + REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF); +- REG_PATTERN_TEST(E1000_TDBAL, 0xFFFFFFF0, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_TDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF); + REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF); ++ mask = 0x8003FFFF; ++ switch (mac->type) { ++ case e1000_ich10lan: ++ case e1000_pchlan: ++ mask |= (1 << 18); ++ break; ++ default: ++ break; ++ } + for (i = 0; i < mac->rar_entry_count; i++) + REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1), +- ((mac->type == e1000_ich10lan) ? +- 0x8007FFFF : 0x8003FFFF), +- 0xFFFFFFFF); ++ mask, 0xFFFFFFFF); + + for (i = 0; i < mac->mta_reg_count; i++) + REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF); +@@ -865,7 +914,7 @@ + for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { + if ((e1000_read_nvm(&adapter->hw, i, 1, &temp)) < 0) { + *data = 1; +- break; ++ return *data; + } + checksum += temp; + } +@@ -896,11 +945,14 @@ + u32 shared_int = 1; + u32 irq = adapter->pdev->irq; + int i; ++#ifdef CONFIG_E1000E_MSIX + int ret_val = 0; + int int_mode = E1000E_INT_MODE_LEGACY; ++#endif + + *data = 0; + ++#ifdef CONFIG_E1000E_MSIX + /* NOTE: we don't test MSI/MSI-X interrupts here, yet */ + if (adapter->int_mode == E1000E_INT_MODE_MSIX) { + int_mode = adapter->int_mode; +@@ -908,6 +960,9 @@ + adapter->int_mode = E1000E_INT_MODE_LEGACY; + e1000e_set_interrupt_capability(adapter); + } ++#else ++ /* NOTE: we don't test MSI interrupts here, yet */ ++#endif + /* Hook up test interrupt handler just for this test */ + if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, netdev->name, + netdev)) { +@@ -915,8 +970,12 @@ + } else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED, + netdev->name, netdev)) { + *data = 1; ++#ifdef CONFIG_E1000E_MSIX + ret_val = -1; + goto out; ++#else ++ return -1; ++#endif + } + e_info("testing %s interrupt\n", (shared_int ? "shared" : "unshared")); + +@@ -1006,6 +1065,7 @@ + /* Unhook test interrupt handler */ + free_irq(irq, netdev); + ++#ifdef CONFIG_E1000E_MSIX + out: + if (int_mode == E1000E_INT_MODE_MSIX) { + e1000e_reset_interrupt_capability(adapter); +@@ -1014,6 +1074,9 @@ + } + + return ret_val; ++#else ++ return *data; ++#endif + } + + static void e1000_free_desc_rings(struct e1000_adapter *adapter) +@@ -1097,11 +1160,11 @@ + tx_ring->next_to_use = 0; + tx_ring->next_to_clean = 0; + +- ew32(TDBAL, ((u64) tx_ring->dma & 0x00000000FFFFFFFF)); +- ew32(TDBAH, ((u64) tx_ring->dma >> 32)); +- ew32(TDLEN, tx_ring->count * sizeof(struct e1000_tx_desc)); +- ew32(TDH, 0); +- ew32(TDT, 0); ++ ew32(TDBAL(0), ((u64) tx_ring->dma & 0x00000000FFFFFFFF)); ++ ew32(TDBAH(0), ((u64) tx_ring->dma >> 32)); ++ ew32(TDLEN(0), tx_ring->count * sizeof(struct e1000_tx_desc)); ++ ew32(TDH(0), 0); ++ ew32(TDT(0), 0); + ew32(TCTL, E1000_TCTL_PSP | E1000_TCTL_EN | E1000_TCTL_MULR | + E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT | + E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT); +@@ -1159,11 +1222,11 @@ + + rctl = er32(RCTL); + ew32(RCTL, rctl & ~E1000_RCTL_EN); +- ew32(RDBAL, ((u64) rx_ring->dma & 0xFFFFFFFF)); +- ew32(RDBAH, ((u64) rx_ring->dma >> 32)); +- ew32(RDLEN, rx_ring->size); +- ew32(RDH, 0); +- ew32(RDT, 0); ++ ew32(RDBAL(0), ((u64) rx_ring->dma & 0xFFFFFFFF)); ++ ew32(RDBAH(0), ((u64) rx_ring->dma >> 32)); ++ ew32(RDLEN(0), rx_ring->size); ++ ew32(RDH(0), 0); ++ ew32(RDT(0), 0); + rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 | + E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_LPE | + E1000_RCTL_SBP | E1000_RCTL_SECRC | +@@ -1490,7 +1553,7 @@ + int ret_val = 0; + unsigned long time; + +- ew32(RDT, rx_ring->count - 1); ++ ew32(RDT(0), rx_ring->count - 1); + + /* + * Calculate the loop count based on the largest descriptor ring +@@ -1517,7 +1580,7 @@ + if (k == tx_ring->count) + k = 0; + } +- ew32(TDT, k); ++ ew32(TDT(0), k); + msleep(200); + time = jiffies; /* set the start time for the receive */ + good_cnt = 0; +@@ -1613,16 +1676,14 @@ + return *data; + } + +-static int e1000e_get_sset_count(struct net_device *netdev, int sset) ++static int e1000_get_self_test_count(struct net_device *netdev) + { +- switch (sset) { +- case ETH_SS_TEST: +- return E1000_TEST_LEN; +- case ETH_SS_STATS: +- return E1000_STATS_LEN; +- default: +- return -EOPNOTSUPP; +- } ++ return E1000_TEST_LEN; ++} ++ ++static int e1000_get_stats_count(struct net_device *netdev) ++{ ++ return E1000_STATS_LEN; + } + + static void e1000_diag_test(struct net_device *netdev, +@@ -1749,12 +1810,11 @@ + { + struct e1000_adapter *adapter = netdev_priv(netdev); + +- if (wol->wolopts & WAKE_MAGICSECURE) ++ if (!(adapter->flags & FLAG_HAS_WOL) || ++ !device_can_wakeup(&adapter->pdev->dev) || ++ (wol->wolopts & ~(WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | ++ WAKE_MAGIC | WAKE_PHY | WAKE_ARP))) + return -EOPNOTSUPP; +- +- if (!(adapter->flags & FLAG_HAS_WOL) || +- !device_can_wakeup(&adapter->pdev->dev)) +- return wol->wolopts ? -EOPNOTSUPP : 0; + + /* these settings will always override what we currently have */ + adapter->wol = 0; +@@ -1783,15 +1843,22 @@ + /* bit defines for adapter->led_status */ + #define E1000_LED_ON 0 + +-static void e1000_led_blink_callback(unsigned long data) ++static void e1000e_led_blink_task(struct work_struct *work) + { +- struct e1000_adapter *adapter = (struct e1000_adapter *) data; ++ struct e1000_adapter *adapter = container_of(work, ++ struct e1000_adapter, led_blink_task); + + if (test_and_change_bit(E1000_LED_ON, &adapter->led_status)) + adapter->hw.mac.ops.led_off(&adapter->hw); + else + adapter->hw.mac.ops.led_on(&adapter->hw); ++} + ++static void e1000_led_blink_callback(unsigned long data) ++{ ++ struct e1000_adapter *adapter = (struct e1000_adapter *) data; ++ ++ schedule_work(&adapter->led_blink_task); + mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL); + } + +@@ -1804,7 +1871,10 @@ + data = INT_MAX; + + if ((hw->phy.type == e1000_phy_ife) || ++ (hw->mac.type == e1000_pchlan) || ++ (hw->mac.type == e1000_82583) || + (hw->mac.type == e1000_82574)) { ++ INIT_WORK(&adapter->led_blink_task, e1000e_led_blink_task); + if (!adapter->blink_timer.function) { + init_timer(&adapter->blink_timer); + adapter->blink_timer.function = +@@ -1937,18 +2007,27 @@ + .set_tx_csum = e1000_set_tx_csum, + .get_sg = ethtool_op_get_sg, + .set_sg = ethtool_op_set_sg, ++#ifdef NETIF_F_TSO + .get_tso = ethtool_op_get_tso, + .set_tso = e1000_set_tso, ++#endif + .self_test = e1000_diag_test, + .get_strings = e1000_get_strings, + .phys_id = e1000_phys_id, + .get_ethtool_stats = e1000_get_ethtool_stats, +- .get_sset_count = e1000e_get_sset_count, ++ .self_test_count = e1000_get_self_test_count, ++ .get_stats_count = e1000_get_stats_count, + .get_coalesce = e1000_get_coalesce, + .set_coalesce = e1000_set_coalesce, ++#ifdef NETIF_F_LRO ++ .get_flags = ethtool_op_get_flags, ++ .set_flags = ethtool_op_set_flags, ++#endif + }; + + void e1000e_set_ethtool_ops(struct net_device *netdev) + { +- SET_ETHTOOL_OPS(netdev, &e1000_ethtool_ops); ++ /* have to "undeclare" const on this struct to remove warnings */ ++ SET_ETHTOOL_OPS(netdev, (struct ethtool_ops *)&e1000_ethtool_ops); + } ++#endif /* SIOCETHTOOL */ +diff -r 5638ec0574f5 drivers/net/e1000e/hw.h +--- a/drivers/net/e1000e/hw.h Tue Sep 01 13:47:57 2009 +0100 ++++ b/drivers/net/e1000e/hw.h Tue Sep 01 13:48:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel PRO/1000 Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -29,357 +29,84 @@ + #ifndef _E1000_HW_H_ + #define _E1000_HW_H_ + +-#include ++#include "e1000_regs.h" ++#include "e1000_defines.h" + + struct e1000_hw; +-struct e1000_adapter; + +-#include "defines.h" +- +-#define er32(reg) __er32(hw, E1000_##reg) +-#define ew32(reg,val) __ew32(hw, E1000_##reg, (val)) +-#define e1e_flush() er32(STATUS) +- +-#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ +- (writel((value), ((a)->hw_addr + reg + ((offset) << 2)))) +- +-#define E1000_READ_REG_ARRAY(a, reg, offset) \ +- (readl((a)->hw_addr + reg + ((offset) << 2))) +- +-enum e1e_registers { +- E1000_CTRL = 0x00000, /* Device Control - RW */ +- E1000_STATUS = 0x00008, /* Device Status - RO */ +- E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */ +- E1000_EERD = 0x00014, /* EEPROM Read - RW */ +- E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */ +- E1000_FLA = 0x0001C, /* Flash Access - RW */ +- E1000_MDIC = 0x00020, /* MDI Control - RW */ +- E1000_SCTL = 0x00024, /* SerDes Control - RW */ +- E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */ +- E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */ +- E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */ +- E1000_FCT = 0x00030, /* Flow Control Type - RW */ +- E1000_VET = 0x00038, /* VLAN Ether Type - RW */ +- E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */ +- E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */ +- E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */ +- E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */ +- E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */ +- E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */ +- E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */ +- E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */ +- E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */ +-#define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2)) +- E1000_RCTL = 0x00100, /* Rx Control - RW */ +- E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */ +- E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */ +- E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */ +- E1000_TCTL = 0x00400, /* Tx Control - RW */ +- E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */ +- E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */ +- E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */ +- E1000_LEDCTL = 0x00E00, /* LED Control - RW */ +- E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */ +- E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */ +- E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */ +- E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */ +- E1000_PBS = 0x01008, /* Packet Buffer Size */ +- E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */ +- E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */ +- E1000_FLOP = 0x0103C, /* FLASH Opcode Register */ +- E1000_PBA_ECC = 0x01100, /* PBA ECC Register */ +- E1000_ERT = 0x02008, /* Early Rx Threshold - RW */ +- E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */ +- E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */ +- E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */ +- E1000_RDBAL = 0x02800, /* Rx Descriptor Base Address Low - RW */ +- E1000_RDBAH = 0x02804, /* Rx Descriptor Base Address High - RW */ +- E1000_RDLEN = 0x02808, /* Rx Descriptor Length - RW */ +- E1000_RDH = 0x02810, /* Rx Descriptor Head - RW */ +- E1000_RDT = 0x02818, /* Rx Descriptor Tail - RW */ +- E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */ +- E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */ +-#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8)) +- E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */ +- +-/* Convenience macros +- * +- * Note: "_n" is the queue number of the register to be written to. +- * +- * Example usage: +- * E1000_RDBAL_REG(current_rx_queue) +- * +- */ +-#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8)) +- E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */ +- E1000_TDBAL = 0x03800, /* Tx Descriptor Base Address Low - RW */ +- E1000_TDBAH = 0x03804, /* Tx Descriptor Base Address High - RW */ +- E1000_TDLEN = 0x03808, /* Tx Descriptor Length - RW */ +- E1000_TDH = 0x03810, /* Tx Descriptor Head - RW */ +- E1000_TDT = 0x03818, /* Tx Descriptor Tail - RW */ +- E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */ +- E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */ +-#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8)) +- E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */ +- E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */ +-#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8)) +- E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */ +- E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */ +- E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */ +- E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */ +- E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */ +- E1000_SCC = 0x04014, /* Single Collision Count - R/clr */ +- E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */ +- E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */ +- E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */ +- E1000_COLC = 0x04028, /* Collision Count - R/clr */ +- E1000_DC = 0x04030, /* Defer Count - R/clr */ +- E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */ +- E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */ +- E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */ +- E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */ +- E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */ +- E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */ +- E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */ +- E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */ +- E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */ +- E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */ +- E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */ +- E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */ +- E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */ +- E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */ +- E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */ +- E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */ +- E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */ +- E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */ +- E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */ +- E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */ +- E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */ +- E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */ +- E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */ +- E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */ +- E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */ +- E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */ +- E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */ +- E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */ +- E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */ +- E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */ +- E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */ +- E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */ +- E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */ +- E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */ +- E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */ +- E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */ +- E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */ +- E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */ +- E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */ +- E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */ +- E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */ +- E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */ +- E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */ +- E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */ +- E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */ +- E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */ +- E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */ +- E1000_IAC = 0x04100, /* Interrupt Assertion Count */ +- E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */ +- E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */ +- E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */ +- E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */ +- E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */ +- E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */ +- E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */ +- E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */ +- E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */ +- E1000_RFCTL = 0x05008, /* Receive Filter Control */ +- E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */ +- E1000_RA = 0x05400, /* Receive Address - RW Array */ +- E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */ +- E1000_WUC = 0x05800, /* Wakeup Control - RW */ +- E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */ +- E1000_WUS = 0x05810, /* Wakeup Status - RO */ +- E1000_MANC = 0x05820, /* Management Control - RW */ +- E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */ +- E1000_HOST_IF = 0x08800, /* Host Interface */ +- +- E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */ +- E1000_MANC2H = 0x05860, /* Management Control To Host - RW */ +- E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */ +- E1000_GCR = 0x05B00, /* PCI-Ex Control */ +- E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */ +- E1000_SWSM = 0x05B50, /* SW Semaphore */ +- E1000_FWSM = 0x05B54, /* FW Semaphore */ +- E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */ +- E1000_HICR = 0x08F00, /* Host Interface Control */ +-}; +- +-/* RSS registers */ +- +-/* IGP01E1000 Specific Registers */ +-#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ +-#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ +-#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ +-#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ +-#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ +-#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ +-#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ +-#define IGP_PAGE_SHIFT 5 +-#define PHY_REG_MASK 0x1F +- +-#define BM_WUC_PAGE 800 +-#define BM_WUC_ADDRESS_OPCODE 0x11 +-#define BM_WUC_DATA_OPCODE 0x12 +-#define BM_WUC_ENABLE_PAGE 769 +-#define BM_WUC_ENABLE_REG 17 +-#define BM_WUC_ENABLE_BIT (1 << 2) +-#define BM_WUC_HOST_WU_BIT (1 << 4) +- +-#define BM_WUC PHY_REG(BM_WUC_PAGE, 1) +-#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) +-#define BM_WUS PHY_REG(BM_WUC_PAGE, 3) +- +-#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 +-#define IGP01E1000_PHY_POLARITY_MASK 0x0078 +- +-#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 +-#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ +- +-#define IGP01E1000_PSCFR_SMART_SPEED 0x0080 +- +-#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ +-#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ +-#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ +- +-#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 +- +-#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 +-#define IGP01E1000_PSSR_MDIX 0x0008 +-#define IGP01E1000_PSSR_SPEED_MASK 0xC000 +-#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 +- +-#define IGP02E1000_PHY_CHANNEL_NUM 4 +-#define IGP02E1000_PHY_AGC_A 0x11B1 +-#define IGP02E1000_PHY_AGC_B 0x12B1 +-#define IGP02E1000_PHY_AGC_C 0x14B1 +-#define IGP02E1000_PHY_AGC_D 0x18B1 +- +-#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ +-#define IGP02E1000_AGC_LENGTH_MASK 0x7F +-#define IGP02E1000_AGC_RANGE 15 +- +-/* manage.c */ +-#define E1000_VFTA_ENTRY_SHIFT 5 +-#define E1000_VFTA_ENTRY_MASK 0x7F +-#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F +- +-#define E1000_HICR_EN 0x01 /* Enable bit - RO */ +-/* Driver sets this bit when done to put command in RAM */ +-#define E1000_HICR_C 0x02 +-#define E1000_HICR_FW_RESET_ENABLE 0x40 +-#define E1000_HICR_FW_RESET 0x80 +- +-#define E1000_FWSM_MODE_MASK 0xE +-#define E1000_FWSM_MODE_SHIFT 1 +- +-#define E1000_MNG_IAMT_MODE 0x3 +-#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 +-#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 +-#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 +-#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 +-#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 +-#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 +- +-/* nvm.c */ +-#define E1000_STM_OPCODE 0xDB00 +- +-#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 +-#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 +-#define E1000_KMRNCTRLSTA_REN 0x00200000 +-#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ +-#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ +- +-#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 +-#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */ +-#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */ +-#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ +- +-/* IFE PHY Extended Status Control */ +-#define IFE_PESC_POLARITY_REVERSED 0x0100 +- +-/* IFE PHY Special Control */ +-#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 +-#define IFE_PSC_FORCE_POLARITY 0x0020 +- +-/* IFE PHY Special Control and LED Control */ +-#define IFE_PSCL_PROBE_MODE 0x0020 +-#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ +-#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ +- +-/* IFE PHY MDIX Control */ +-#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ +-#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ +-#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */ +- +-#define E1000_CABLE_LENGTH_UNDEFINED 0xFF +- +-#define E1000_DEV_ID_82571EB_COPPER 0x105E +-#define E1000_DEV_ID_82571EB_FIBER 0x105F +-#define E1000_DEV_ID_82571EB_SERDES 0x1060 +-#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 +-#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 +-#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 +-#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC +-#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 +-#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA +-#define E1000_DEV_ID_82572EI_COPPER 0x107D +-#define E1000_DEV_ID_82572EI_FIBER 0x107E +-#define E1000_DEV_ID_82572EI_SERDES 0x107F +-#define E1000_DEV_ID_82572EI 0x10B9 +-#define E1000_DEV_ID_82573E 0x108B +-#define E1000_DEV_ID_82573E_IAMT 0x108C +-#define E1000_DEV_ID_82573L 0x109A +-#define E1000_DEV_ID_82574L 0x10D3 +- +-#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 +-#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 +-#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA +-#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB +- +-#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 +-#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A +-#define E1000_DEV_ID_ICH8_IGP_C 0x104B +-#define E1000_DEV_ID_ICH8_IFE 0x104C +-#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 +-#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 +-#define E1000_DEV_ID_ICH8_IGP_M 0x104D +-#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD +-#define E1000_DEV_ID_ICH9_BM 0x10E5 +-#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 +-#define E1000_DEV_ID_ICH9_IGP_M 0x10BF +-#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB +-#define E1000_DEV_ID_ICH9_IGP_C 0x294C +-#define E1000_DEV_ID_ICH9_IFE 0x10C0 +-#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 +-#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 +-#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC +-#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD +-#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE +-#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE +-#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF +- ++#define E1000_DEV_ID_82571EB_COPPER 0x105E ++#define E1000_DEV_ID_82571EB_FIBER 0x105F ++#define E1000_DEV_ID_82571EB_SERDES 0x1060 ++#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 ++#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA ++#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 ++#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 ++#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 ++#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC ++#define E1000_DEV_ID_82572EI_COPPER 0x107D ++#define E1000_DEV_ID_82572EI_FIBER 0x107E ++#define E1000_DEV_ID_82572EI_SERDES 0x107F ++#define E1000_DEV_ID_82572EI 0x10B9 ++#define E1000_DEV_ID_82573E 0x108B ++#define E1000_DEV_ID_82573E_IAMT 0x108C ++#define E1000_DEV_ID_82573L 0x109A ++#define E1000_DEV_ID_82574L 0x10D3 ++#define E1000_DEV_ID_82574LA 0x10F6 ++#define E1000_DEV_ID_82583V 0x150C ++#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 ++#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 ++#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA ++#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB ++#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 ++#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A ++#define E1000_DEV_ID_ICH8_IGP_C 0x104B ++#define E1000_DEV_ID_ICH8_IFE 0x104C ++#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 ++#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 ++#define E1000_DEV_ID_ICH8_IGP_M 0x104D ++#define E1000_DEV_ID_ICH9_IGP_M 0x10BF ++#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 ++#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB ++#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD ++#define E1000_DEV_ID_ICH9_BM 0x10E5 ++#define E1000_DEV_ID_ICH9_IGP_C 0x294C ++#define E1000_DEV_ID_ICH9_IFE 0x10C0 ++#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 ++#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 ++#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC ++#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD ++#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE ++#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE ++#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF ++#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA ++#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB ++#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF ++#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 ++#define E1000_REVISION_0 0 ++#define E1000_REVISION_1 1 ++#define E1000_REVISION_2 2 ++#define E1000_REVISION_3 3 + #define E1000_REVISION_4 4 + +-#define E1000_FUNC_1 1 ++#define E1000_FUNC_0 0 ++#define E1000_FUNC_1 1 ++ ++#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 ++#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 + + enum e1000_mac_type { ++ e1000_undefined = 0, + e1000_82571, + e1000_82572, + e1000_82573, + e1000_82574, ++ e1000_82583, + e1000_80003es2lan, + e1000_ich8lan, + e1000_ich9lan, + e1000_ich10lan, ++ e1000_pchlan, ++ e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ + }; + + enum e1000_media_type { +@@ -401,7 +128,7 @@ + enum e1000_nvm_override { + e1000_nvm_override_none = 0, + e1000_nvm_override_spi_small, +- e1000_nvm_override_spi_large ++ e1000_nvm_override_spi_large, + }; + + enum e1000_phy_type { +@@ -414,6 +141,28 @@ + e1000_phy_igp_3, + e1000_phy_ife, + e1000_phy_bm, ++ e1000_phy_82578, ++ e1000_phy_82577, ++}; ++ ++enum e1000_bus_type { ++ e1000_bus_type_unknown = 0, ++ e1000_bus_type_pci, ++ e1000_bus_type_pcix, ++ e1000_bus_type_pci_express, ++ e1000_bus_type_reserved ++}; ++ ++enum e1000_bus_speed { ++ e1000_bus_speed_unknown = 0, ++ e1000_bus_speed_33, ++ e1000_bus_speed_66, ++ e1000_bus_speed_100, ++ e1000_bus_speed_120, ++ e1000_bus_speed_133, ++ e1000_bus_speed_2500, ++ e1000_bus_speed_5000, ++ e1000_bus_speed_reserved + }; + + enum e1000_bus_width { +@@ -421,6 +170,7 @@ + e1000_bus_width_pcie_x1, + e1000_bus_width_pcie_x2, + e1000_bus_width_pcie_x4 = 4, ++ e1000_bus_width_pcie_x8 = 8, + e1000_bus_width_32, + e1000_bus_width_64, + e1000_bus_width_reserved +@@ -432,13 +182,13 @@ + e1000_1000t_rx_status_undefined = 0xFF + }; + +-enum e1000_rev_polarity{ ++enum e1000_rev_polarity { + e1000_rev_polarity_normal = 0, + e1000_rev_polarity_reversed, + e1000_rev_polarity_undefined = 0xFF + }; + +-enum e1000_fc_type { ++enum e1000_fc_mode { + e1000_fc_none = 0, + e1000_fc_rx_pause, + e1000_fc_tx_pause, +@@ -459,13 +209,20 @@ + e1000_smart_speed_off + }; + ++enum e1000_serdes_link_state { ++ e1000_serdes_link_down = 0, ++ e1000_serdes_link_autoneg_progress, ++ e1000_serdes_link_autoneg_complete, ++ e1000_serdes_link_forced_up ++}; ++ + /* Receive Descriptor */ + struct e1000_rx_desc { + __le64 buffer_addr; /* Address of the descriptor's data buffer */ + __le16 length; /* Length of data DMAed into data buffer */ +- __le16 csum; /* Packet checksum */ +- u8 status; /* Descriptor status */ +- u8 errors; /* Descriptor Errors */ ++ __le16 csum; /* Packet checksum */ ++ u8 status; /* Descriptor status */ ++ u8 errors; /* Descriptor Errors */ + __le16 special; + }; + +@@ -477,9 +234,9 @@ + } read; + struct { + struct { +- __le32 mrq; /* Multiple Rx Queues */ ++ __le32 mrq; /* Multiple Rx Queues */ + union { +- __le32 rss; /* RSS Hash */ ++ __le32 rss; /* RSS Hash */ + struct { + __le16 ip_id; /* IP id */ + __le16 csum; /* Packet Checksum */ +@@ -487,9 +244,9 @@ + } hi_dword; + } lower; + struct { +- __le32 status_error; /* ext status/error */ ++ __le32 status_error; /* ext status/error */ + __le16 length; +- __le16 vlan; /* VLAN tag */ ++ __le16 vlan; /* VLAN tag */ + } upper; + } wb; /* writeback */ + }; +@@ -503,9 +260,9 @@ + } read; + struct { + struct { +- __le32 mrq; /* Multiple Rx Queues */ ++ __le32 mrq; /* Multiple Rx Queues */ + union { +- __le32 rss; /* RSS Hash */ ++ __le32 rss; /* RSS Hash */ + struct { + __le16 ip_id; /* IP id */ + __le16 csum; /* Packet Checksum */ +@@ -513,13 +270,13 @@ + } hi_dword; + } lower; + struct { +- __le32 status_error; /* ext status/error */ +- __le16 length0; /* length of buffer 0 */ +- __le16 vlan; /* VLAN tag */ ++ __le32 status_error; /* ext status/error */ ++ __le16 length0; /* length of buffer 0 */ ++ __le16 vlan; /* VLAN tag */ + } middle; + struct { + __le16 header_status; +- __le16 length[3]; /* length of buffers 1-3 */ ++ __le16 length[3]; /* length of buffers 1-3 */ + } upper; + __le64 reserved; + } wb; /* writeback */ +@@ -527,20 +284,20 @@ + + /* Transmit Descriptor */ + struct e1000_tx_desc { +- __le64 buffer_addr; /* Address of the descriptor's data buffer */ ++ __le64 buffer_addr; /* Address of the descriptor's data buffer */ + union { + __le32 data; + struct { + __le16 length; /* Data buffer length */ +- u8 cso; /* Checksum offset */ +- u8 cmd; /* Descriptor control */ ++ u8 cso; /* Checksum offset */ ++ u8 cmd; /* Descriptor control */ + } flags; + } lower; + union { + __le32 data; + struct { +- u8 status; /* Descriptor status */ +- u8 css; /* Checksum start */ ++ u8 status; /* Descriptor status */ ++ u8 css; /* Checksum start */ + __le16 special; + } fields; + } upper; +@@ -551,16 +308,16 @@ + union { + __le32 ip_config; + struct { +- u8 ipcss; /* IP checksum start */ +- u8 ipcso; /* IP checksum offset */ ++ u8 ipcss; /* IP checksum start */ ++ u8 ipcso; /* IP checksum offset */ + __le16 ipcse; /* IP checksum end */ + } ip_fields; + } lower_setup; + union { + __le32 tcp_config; + struct { +- u8 tucss; /* TCP checksum start */ +- u8 tucso; /* TCP checksum offset */ ++ u8 tucss; /* TCP checksum start */ ++ u8 tucso; /* TCP checksum offset */ + __le16 tucse; /* TCP checksum end */ + } tcp_fields; + } upper_setup; +@@ -568,8 +325,8 @@ + union { + __le32 data; + struct { +- u8 status; /* Descriptor status */ +- u8 hdr_len; /* Header length */ ++ u8 status; /* Descriptor status */ ++ u8 hdr_len; /* Header length */ + __le16 mss; /* Maximum segment size */ + } fields; + } tcp_seg_setup; +@@ -589,9 +346,9 @@ + union { + __le32 data; + struct { +- u8 status; /* Descriptor status */ +- u8 popts; /* Packet Options */ +- __le16 special; /* */ ++ u8 status; /* Descriptor status */ ++ u8 popts; /* Packet Options */ ++ __le16 special; + } fields; + } upper; + }; +@@ -661,7 +418,9 @@ + u64 ictxqmtc; + u64 icrxdmtc; + u64 icrxoc; ++ u64 doosync; + }; ++ + + struct e1000_phy_stats { + u32 idle_errors; +@@ -708,54 +467,80 @@ + u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; + }; + +-/* Function pointers and static data for the MAC. */ ++#include "e1000_mac.h" ++#include "e1000_phy.h" ++#include "e1000_nvm.h" ++#include "e1000_manage.h" ++ + struct e1000_mac_operations { +- bool (*check_mng_mode)(struct e1000_hw *); ++ /* Function pointers for the MAC. */ ++ s32 (*init_params)(struct e1000_hw *); ++ s32 (*id_led_init)(struct e1000_hw *); ++ s32 (*blink_led)(struct e1000_hw *); + s32 (*check_for_link)(struct e1000_hw *); ++ bool (*check_mng_mode)(struct e1000_hw *hw); + s32 (*cleanup_led)(struct e1000_hw *); + void (*clear_hw_cntrs)(struct e1000_hw *); ++ void (*clear_vfta)(struct e1000_hw *); + s32 (*get_bus_info)(struct e1000_hw *); ++ void (*set_lan_id)(struct e1000_hw *); + s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); + s32 (*led_on)(struct e1000_hw *); + s32 (*led_off)(struct e1000_hw *); +- void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32); ++ void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); + s32 (*reset_hw)(struct e1000_hw *); + s32 (*init_hw)(struct e1000_hw *); + s32 (*setup_link)(struct e1000_hw *); + s32 (*setup_physical_interface)(struct e1000_hw *); ++ s32 (*setup_led)(struct e1000_hw *); ++ void (*write_vfta)(struct e1000_hw *, u32, u32); ++ void (*mta_set)(struct e1000_hw *, u32); ++ void (*config_collision_dist)(struct e1000_hw *); ++ void (*rar_set)(struct e1000_hw *, u8*, u32); ++ s32 (*read_mac_addr)(struct e1000_hw *); ++ s32 (*validate_mdi_setting)(struct e1000_hw *); ++ s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); ++ s32 (*mng_write_cmd_header)(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header*); ++ s32 (*mng_enable_host_if)(struct e1000_hw *); ++ s32 (*wait_autoneg)(struct e1000_hw *); + }; + +-/* Function pointers for the PHY. */ + struct e1000_phy_operations { +- s32 (*acquire_phy)(struct e1000_hw *); ++ s32 (*init_params)(struct e1000_hw *); ++ s32 (*acquire)(struct e1000_hw *); ++ s32 (*cfg_on_link_up)(struct e1000_hw *); ++ s32 (*check_polarity)(struct e1000_hw *); + s32 (*check_reset_block)(struct e1000_hw *); +- s32 (*commit_phy)(struct e1000_hw *); ++ s32 (*commit)(struct e1000_hw *); + s32 (*force_speed_duplex)(struct e1000_hw *); + s32 (*get_cfg_done)(struct e1000_hw *hw); + s32 (*get_cable_length)(struct e1000_hw *); +- s32 (*get_phy_info)(struct e1000_hw *); +- s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *); +- void (*release_phy)(struct e1000_hw *); +- s32 (*reset_phy)(struct e1000_hw *); ++ s32 (*get_info)(struct e1000_hw *); ++ s32 (*read_reg)(struct e1000_hw *, u32, u16 *); ++ void (*release)(struct e1000_hw *); ++ s32 (*reset)(struct e1000_hw *); + s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); + s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); +- s32 (*write_phy_reg)(struct e1000_hw *, u32, u16); ++ s32 (*write_reg)(struct e1000_hw *, u32, u16); ++ void (*power_up)(struct e1000_hw *); ++ void (*power_down)(struct e1000_hw *); + }; + +-/* Function pointers for the NVM. */ + struct e1000_nvm_operations { +- s32 (*acquire_nvm)(struct e1000_hw *); +- s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *); +- void (*release_nvm)(struct e1000_hw *); +- s32 (*update_nvm)(struct e1000_hw *); ++ s32 (*init_params)(struct e1000_hw *); ++ s32 (*acquire)(struct e1000_hw *); ++ s32 (*read)(struct e1000_hw *, u16, u16, u16 *); ++ void (*release)(struct e1000_hw *); ++ void (*reload)(struct e1000_hw *); ++ s32 (*update)(struct e1000_hw *); + s32 (*valid_led_default)(struct e1000_hw *, u16 *); +- s32 (*validate_nvm)(struct e1000_hw *); +- s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *); ++ s32 (*validate)(struct e1000_hw *); ++ s32 (*write)(struct e1000_hw *, u16, u16, u16 *); + }; + + struct e1000_mac_info { + struct e1000_mac_operations ops; +- + u8 addr[6]; + u8 perm_addr[6]; + +@@ -775,22 +560,28 @@ + u16 ifs_ratio; + u16 ifs_step_size; + u16 mta_reg_count; ++ ++ /* Maximum size of the MTA register table in all supported adapters */ ++ #define MAX_MTA_REG 128 ++ u32 mta_shadow[MAX_MTA_REG]; + u16 rar_entry_count; + + u8 forced_speed_duplex; + ++ bool adaptive_ifs; + bool arc_subsystem_valid; ++ bool asf_firmware_present; + bool autoneg; + bool autoneg_failed; + bool get_link_status; + bool in_ifs_mode; ++ enum e1000_serdes_link_state serdes_link_state; + bool serdes_has_link; + bool tx_pkt_filtering; + }; + + struct e1000_phy_info { + struct e1000_phy_operations ops; +- + enum e1000_phy_type type; + + enum e1000_1000t_rx_status local_rx; +@@ -818,13 +609,13 @@ + bool disable_polarity_correction; + bool is_mdix; + bool polarity_correction; ++ bool reset_disable; + bool speed_downgraded; + bool autoneg_wait_to_complete; + }; + + struct e1000_nvm_info { + struct e1000_nvm_operations ops; +- + enum e1000_nvm_type type; + enum e1000_nvm_override override; + +@@ -839,9 +630,12 @@ + }; + + struct e1000_bus_info { ++ enum e1000_bus_type type; ++ enum e1000_bus_speed speed; + enum e1000_bus_width width; + + u16 func; ++ u16 pci_cmd_word; + }; + + struct e1000_fc_info { +@@ -850,13 +644,12 @@ + u16 pause_time; /* Flow control pause timer */ + bool send_xon; /* Flow control send XON */ + bool strict_ieee; /* Strict IEEE mode */ +- enum e1000_fc_type type; /* Type of flow control */ +- enum e1000_fc_type original_type; ++ enum e1000_fc_mode current_mode; /* FC mode in effect */ ++ enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ + }; + + struct e1000_dev_spec_82571 { + bool laa_is_present; +- bool alt_mac_addr_is_present; + u32 smb_counter; + }; + +@@ -886,20 +679,23 @@ + struct e1000_host_mng_dhcp_cookie mng_cookie; + + union { +- struct e1000_dev_spec_82571 e82571; ++ struct e1000_dev_spec_82571 _82571; + struct e1000_dev_spec_ich8lan ich8lan; + } dev_spec; ++ ++ u16 device_id; ++ u16 subsystem_vendor_id; ++ u16 subsystem_device_id; ++ u16 vendor_id; ++ ++ u8 revision_id; + }; + +-#ifdef DEBUG +-#define hw_dbg(hw, format, arg...) \ +- printk(KERN_DEBUG "%s: " format, e1000e_get_hw_dev_name(hw), ##arg) +-#else +-static inline int __attribute__ ((format (printf, 2, 3))) +-hw_dbg(struct e1000_hw *hw, const char *format, ...) +-{ +- return 0; +-} +-#endif ++#include "e1000_82571.h" ++#include "e1000_80003es2lan.h" ++#include "e1000_ich8lan.h" ++ ++/* These functions must be implemented by drivers */ ++s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); + + #endif +diff -r 5638ec0574f5 drivers/net/e1000e/ich8lan.c +--- a/drivers/net/e1000e/ich8lan.c Tue Sep 01 13:47:57 2009 +0100 ++++ b/drivers/net/e1000e/ich8lan.c Tue Sep 01 13:48:50 2009 +0100 +@@ -102,9 +102,6 @@ + + #define E1000_ICH_RAR_ENTRIES 7 + +-#define PHY_PAGE_SHIFT 5 +-#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ +- ((reg) & MAX_PHY_REG_ADDRESS)) + #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ + #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ + +@@ -236,6 +233,19 @@ + return ret_val; + } + ++ /* ++ * We may need to do this twice - once for IGP and if that fails, ++ * we'll set BM func pointers and try again ++ */ ++ ret_val = e1000e_determine_phy_address(hw); ++ if (ret_val) { ++ hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; ++ hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; ++ ret_val = e1000e_determine_phy_address(hw); ++ if (ret_val) ++ return ret_val; ++ } ++ + phy->id = 0; + while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && + (i++ < 100)) { +@@ -256,6 +266,13 @@ + case IFE_C_E_PHY_ID: + phy->type = e1000_phy_ife; + phy->autoneg_mask = E1000_ALL_NOT_GIG; ++ break; ++ case BME1000_E_PHY_ID: ++ phy->type = e1000_phy_bm; ++ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; ++ hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; ++ hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; ++ hw->phy.ops.commit_phy = e1000e_phy_sw_reset; + break; + case BME1000_E_PHY_ID: + phy->type = e1000_phy_bm; +@@ -378,9 +395,17 @@ + if (rc) + return rc; + +- if ((adapter->hw.mac.type == e1000_ich8lan) && +- (adapter->hw.phy.type == e1000_phy_igp_3)) +- adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; ++ if (adapter->hw.phy.type == e1000_phy_ife) ++ adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; ++ ++ switch (adapter->hw.mac.type) { ++ case e1000_ich8lan: ++ if (adapter->hw.phy.type == e1000_phy_igp_3) ++ adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; ++ break; ++ default: ++ break; ++ } + + return 0; + } +@@ -1948,7 +1973,7 @@ + ret_val = e1000e_id_led_init(hw); + if (ret_val) { + hw_dbg(hw, "Error initializing identification LED\n"); +- return ret_val; ++ /* This is not fatal and we should not stop init due to this */ + } + + /* Setup the receive address. */ +@@ -2390,6 +2415,31 @@ + } + + /** ++ * e1000e_disable_gig_wol_ich8lan - disable gig during WoL ++ * @hw: pointer to the HW structure ++ * ++ * During S0 to Sx transition, it is possible the link remains at gig ++ * instead of negotiating to a lower speed. Before going to Sx, set ++ * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation ++ * to a lower speed. ++ * ++ * Should only be called for ICH9 devices. ++ **/ ++void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) ++{ ++ u32 phy_ctrl; ++ ++ if (hw->mac.type == e1000_ich9lan) { ++ phy_ctrl = er32(PHY_CTRL); ++ phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | ++ E1000_PHY_CTRL_GBE_DISABLE; ++ ew32(PHY_CTRL, phy_ctrl); ++ } ++ ++ return; ++} ++ ++/** + * e1000_cleanup_led_ich8lan - Restore the default LED operation + * @hw: pointer to the HW structure + * +@@ -2433,6 +2483,113 @@ + (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); + + ew32(LEDCTL, hw->mac.ledctl_mode1); ++ return 0; ++} ++ ++/** ++ * e1000_phy_init_script_igp3 - Inits the IGP3 PHY ++ * @hw: pointer to the HW structure ++ * ++ * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. ++ **/ ++static s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) ++{ ++ /* PHY init IGP 3 */ ++ /* Enable rise/fall, 10-mode work in class-A */ ++ e1e_wphy(hw, 0x2F5B, 0x9018); ++ /* Remove all caps from Replica path filter */ ++ e1e_wphy(hw, 0x2F52, 0x0000); ++ /* Bias trimming for ADC, AFE and Driver (Default) */ ++ e1e_wphy(hw, 0x2FB1, 0x8B24); ++ /* Increase Hybrid poly bias */ ++ e1e_wphy(hw, 0x2FB2, 0xF8F0); ++ /* Add 4% to Tx amplitude in Gig mode */ ++ e1e_wphy(hw, 0x2010, 0x10B0); ++ /* Disable trimming (TTT) */ ++ e1e_wphy(hw, 0x2011, 0x0000); ++ /* Poly DC correction to 94.6% + 2% for all channels */ ++ e1e_wphy(hw, 0x20DD, 0x249A); ++ /* ABS DC correction to 95.9% */ ++ e1e_wphy(hw, 0x20DE, 0x00D3); ++ /* BG temp curve trim */ ++ e1e_wphy(hw, 0x28B4, 0x04CE); ++ /* Increasing ADC OPAMP stage 1 currents to max */ ++ e1e_wphy(hw, 0x2F70, 0x29E4); ++ /* Force 1000 ( required for enabling PHY regs configuration) */ ++ e1e_wphy(hw, 0x0000, 0x0140); ++ /* Set upd_freq to 6 */ ++ e1e_wphy(hw, 0x1F30, 0x1606); ++ /* Disable NPDFE */ ++ e1e_wphy(hw, 0x1F31, 0xB814); ++ /* Disable adaptive fixed FFE (Default) */ ++ e1e_wphy(hw, 0x1F35, 0x002A); ++ /* Enable FFE hysteresis */ ++ e1e_wphy(hw, 0x1F3E, 0x0067); ++ /* Fixed FFE for short cable lengths */ ++ e1e_wphy(hw, 0x1F54, 0x0065); ++ /* Fixed FFE for medium cable lengths */ ++ e1e_wphy(hw, 0x1F55, 0x002A); ++ /* Fixed FFE for long cable lengths */ ++ e1e_wphy(hw, 0x1F56, 0x002A); ++ /* Enable Adaptive Clip Threshold */ ++ e1e_wphy(hw, 0x1F72, 0x3FB0); ++ /* AHT reset limit to 1 */ ++ e1e_wphy(hw, 0x1F76, 0xC0FF); ++ /* Set AHT master delay to 127 msec */ ++ e1e_wphy(hw, 0x1F77, 0x1DEC); ++ /* Set scan bits for AHT */ ++ e1e_wphy(hw, 0x1F78, 0xF9EF); ++ /* Set AHT Preset bits */ ++ e1e_wphy(hw, 0x1F79, 0x0210); ++ /* Change integ_factor of channel A to 3 */ ++ e1e_wphy(hw, 0x1895, 0x0003); ++ /* Change prop_factor of channels BCD to 8 */ ++ e1e_wphy(hw, 0x1796, 0x0008); ++ /* Change cg_icount + enable integbp for channels BCD */ ++ e1e_wphy(hw, 0x1798, 0xD008); ++ /* ++ * Change cg_icount + enable integbp + change prop_factor_master ++ * to 8 for channel A ++ */ ++ e1e_wphy(hw, 0x1898, 0xD918); ++ /* Disable AHT in Slave mode on channel A */ ++ e1e_wphy(hw, 0x187A, 0x0800); ++ /* ++ * Enable LPLU and disable AN to 1000 in non-D0a states, ++ * Enable SPD+B2B ++ */ ++ e1e_wphy(hw, 0x0019, 0x008D); ++ /* Enable restart AN on an1000_dis change */ ++ e1e_wphy(hw, 0x001B, 0x2080); ++ /* Enable wh_fifo read clock in 10/100 modes */ ++ e1e_wphy(hw, 0x0014, 0x0045); ++ /* Restart AN, Speed selection is 1000 */ ++ e1e_wphy(hw, 0x0000, 0x1340); ++ ++ return 0; ++} ++ ++/** ++ * e1000_get_cfg_done_ich8lan - Read config done bit ++ * @hw: pointer to the HW structure ++ * ++ * Read the management control register for the config done bit for ++ * completion status. NOTE: silicon which is EEPROM-less will fail trying ++ * to read the config done bit, so an error is *ONLY* logged and returns ++ * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon ++ * would not be able to be reset or change link. ++ **/ ++static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) ++{ ++ ++ e1000e_get_cfg_done(hw); ++ ++ /* If EEPROM is not marked present, init the IGP 3 PHY manually */ ++ if (((er32(EECD) & E1000_EECD_PRES) == 0) && ++ (hw->phy.type == e1000_phy_igp_3)) { ++ e1000_phy_init_script_igp3(hw); ++ } ++ + return 0; + } + +diff -r 5638ec0574f5 drivers/net/e1000e/kcompat.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/kcompat.c Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,480 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000.h" ++#include "kcompat.h" ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,21) ) ++struct sk_buff * ++_kc_skb_pad(struct sk_buff *skb, int pad) ++{ ++ struct sk_buff *nskb; ++ ++ /* If the skbuff is non linear tailroom is always zero.. */ ++ if(skb_tailroom(skb) >= pad) ++ { ++ memset(skb->data+skb->len, 0, pad); ++ return skb; ++ } ++ ++ nskb = skb_copy_expand(skb, skb_headroom(skb), skb_tailroom(skb) + pad, GFP_ATOMIC); ++ kfree_skb(skb); ++ if(nskb) ++ memset(nskb->data+nskb->len, 0, pad); ++ return nskb; ++} ++#endif /* < 2.4.21 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) ) ++ ++/**************************************/ ++/* PCI DMA MAPPING */ ++ ++#if defined(CONFIG_HIGHMEM) ++ ++#ifndef PCI_DRAM_OFFSET ++#define PCI_DRAM_OFFSET 0 ++#endif ++ ++u64 ++_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, ++ size_t size, int direction) ++{ ++ return (((u64) (page - mem_map) << PAGE_SHIFT) + offset + ++ PCI_DRAM_OFFSET); ++} ++ ++#else /* CONFIG_HIGHMEM */ ++ ++u64 ++_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, ++ size_t size, int direction) ++{ ++ return pci_map_single(dev, (void *)page_address(page) + offset, size, ++ direction); ++} ++ ++#endif /* CONFIG_HIGHMEM */ ++ ++void ++_kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, ++ int direction) ++{ ++ return pci_unmap_single(dev, dma_addr, size, direction); ++} ++ ++#endif /* 2.4.13 => 2.4.3 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) ) ++ ++/**************************************/ ++/* PCI DRIVER API */ ++ ++int ++_kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask) ++{ ++ if (!pci_dma_supported(dev, mask)) ++ return -EIO; ++ dev->dma_mask = mask; ++ return 0; ++} ++ ++int ++_kc_pci_request_regions(struct pci_dev *dev, char *res_name) ++{ ++ int i; ++ ++ for (i = 0; i < 6; i++) { ++ if (pci_resource_len(dev, i) == 0) ++ continue; ++ ++ if (pci_resource_flags(dev, i) & IORESOURCE_IO) { ++ if (!request_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) { ++ pci_release_regions(dev); ++ return -EBUSY; ++ } ++ } else if (pci_resource_flags(dev, i) & IORESOURCE_MEM) { ++ if (!request_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) { ++ pci_release_regions(dev); ++ return -EBUSY; ++ } ++ } ++ } ++ return 0; ++} ++ ++void ++_kc_pci_release_regions(struct pci_dev *dev) ++{ ++ int i; ++ ++ for (i = 0; i < 6; i++) { ++ if (pci_resource_len(dev, i) == 0) ++ continue; ++ ++ if (pci_resource_flags(dev, i) & IORESOURCE_IO) ++ release_region(pci_resource_start(dev, i), pci_resource_len(dev, i)); ++ ++ else if (pci_resource_flags(dev, i) & IORESOURCE_MEM) ++ release_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i)); ++ } ++} ++ ++/**************************************/ ++/* NETWORK DRIVER API */ ++ ++struct net_device * ++_kc_alloc_etherdev(int sizeof_priv) ++{ ++ struct net_device *dev; ++ int alloc_size; ++ ++ alloc_size = sizeof(*dev) + sizeof_priv + IFNAMSIZ + 31; ++ dev = kmalloc(alloc_size, GFP_KERNEL); ++ if (!dev) ++ return NULL; ++ memset(dev, 0, alloc_size); ++ ++ if (sizeof_priv) ++ dev->priv = (void *) (((unsigned long)(dev + 1) + 31) & ~31); ++ dev->name[0] = '\0'; ++ ether_setup(dev); ++ ++ return dev; ++} ++ ++int ++_kc_is_valid_ether_addr(u8 *addr) ++{ ++ const char zaddr[6] = { 0, }; ++ ++ return !(addr[0] & 1) && memcmp(addr, zaddr, 6); ++} ++ ++#endif /* 2.4.3 => 2.4.0 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) ) ++ ++int ++_kc_pci_set_power_state(struct pci_dev *dev, int state) ++{ ++ return 0; ++} ++ ++int ++_kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable) ++{ ++ return 0; ++} ++ ++#endif /* 2.4.6 => 2.4.3 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) ++void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, ++ int off, int size) ++{ ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ frag->page = page; ++ frag->page_offset = off; ++ frag->size = size; ++ skb_shinfo(skb)->nr_frags = i + 1; ++} ++ ++/* ++ * Original Copyright: ++ * find_next_bit.c: fallback find next bit implementation ++ * ++ * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. ++ * Written by David Howells (dhowells@redhat.com) ++ */ ++ ++/** ++ * find_next_bit - find the next set bit in a memory region ++ * @addr: The address to base the search on ++ * @offset: The bitnumber to start searching at ++ * @size: The maximum size to search ++ */ ++unsigned long find_next_bit(const unsigned long *addr, unsigned long size, ++ unsigned long offset) ++{ ++ const unsigned long *p = addr + BITOP_WORD(offset); ++ unsigned long result = offset & ~(BITS_PER_LONG-1); ++ unsigned long tmp; ++ ++ if (offset >= size) ++ return size; ++ size -= result; ++ offset %= BITS_PER_LONG; ++ if (offset) { ++ tmp = *(p++); ++ tmp &= (~0UL << offset); ++ if (size < BITS_PER_LONG) ++ goto found_first; ++ if (tmp) ++ goto found_middle; ++ size -= BITS_PER_LONG; ++ result += BITS_PER_LONG; ++ } ++ while (size & ~(BITS_PER_LONG-1)) { ++ if ((tmp = *(p++))) ++ goto found_middle; ++ result += BITS_PER_LONG; ++ size -= BITS_PER_LONG; ++ } ++ if (!size) ++ return result; ++ tmp = *p; ++ ++found_first: ++ tmp &= (~0UL >> (BITS_PER_LONG - size)); ++ if (tmp == 0UL) /* Are any bits set? */ ++ return result + size; /* Nope. */ ++found_middle: ++ return result + ffs(tmp); ++} ++ ++#endif /* 2.6.0 => 2.4.6 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) ) ++void *_kc_kzalloc(size_t size, int flags) ++{ ++ void *ret = kmalloc(size, flags); ++ if (ret) ++ memset(ret, 0, size); ++ return ret; ++} ++#endif /* <= 2.6.13 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ) ++struct sk_buff *_kc_netdev_alloc_skb(struct net_device *dev, ++ unsigned int length) ++{ ++ /* 16 == NET_PAD_SKB */ ++ struct sk_buff *skb; ++ skb = alloc_skb(length + 16, GFP_ATOMIC); ++ if (likely(skb != NULL)) { ++ skb_reserve(skb, 16); ++ skb->dev = dev; ++ } ++ return skb; ++} ++#endif /* <= 2.6.17 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ) ++int _kc_pci_save_state(struct pci_dev *pdev) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int size = PCI_CONFIG_SPACE_LEN, i; ++ u16 pcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP); ++ u16 pcie_link_status; ++ ++ if (pcie_cap_offset) { ++ if (!pci_read_config_word(pdev, ++ pcie_cap_offset + PCIE_LINK_STATUS, ++ &pcie_link_status)) ++ size = PCIE_CONFIG_SPACE_LEN; ++ } ++ pci_config_space_ich8lan(); ++#ifdef HAVE_PCI_ERS ++ if (adapter->config_space == NULL) ++#else ++ WARN_ON(adapter->config_space != NULL); ++#endif ++ adapter->config_space = kmalloc(size, GFP_KERNEL); ++ if (!adapter->config_space) { ++ printk(KERN_ERR "Out of memory in pci_save_state\n"); ++ return -ENOMEM; ++ } ++ for (i = 0; i < (size / 4); i++) ++ pci_read_config_dword(pdev, i * 4, &adapter->config_space[i]); ++ return 0; ++} ++ ++void _kc_pci_restore_state(struct pci_dev * pdev) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int size = PCI_CONFIG_SPACE_LEN, i; ++ u16 pcie_cap_offset; ++ u16 pcie_link_status; ++ ++ if (adapter->config_space != NULL) { ++ pcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP); ++ if (pcie_cap_offset && ++ !pci_read_config_word(pdev, ++ pcie_cap_offset + PCIE_LINK_STATUS, ++ &pcie_link_status)) ++ size = PCIE_CONFIG_SPACE_LEN; ++ ++ pci_config_space_ich8lan(); ++ for (i = 0; i < (size / 4); i++) ++ pci_write_config_dword(pdev, i * 4, adapter->config_space[i]); ++#ifndef HAVE_PCI_ERS ++ kfree(adapter->config_space); ++ adapter->config_space = NULL; ++#endif ++ } ++} ++ ++#ifdef HAVE_PCI_ERS ++void _kc_free_netdev(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ ++ if (adapter->config_space != NULL) ++ kfree(adapter->config_space); ++#ifdef CONFIG_SYSFS ++ if (netdev->reg_state == NETREG_UNINITIALIZED) { ++ kfree((char *)netdev - netdev->padded); ++ } else { ++ BUG_ON(netdev->reg_state != NETREG_UNREGISTERED); ++ netdev->reg_state = NETREG_RELEASED; ++ class_device_put(&netdev->class_dev); ++ } ++#else ++ kfree((char *)netdev - netdev->padded); ++#endif ++} ++#endif ++#endif /* <= 2.6.18 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ) ++#ifdef NAPI ++/* this function returns the true netdev of the napi struct */ ++struct net_device * napi_to_netdev(struct napi_struct *napi) ++{ ++ struct adapter_struct *adapter = container_of(napi, ++ struct adapter_struct, ++ napi); ++ return adapter->netdev; ++} ++ ++int __kc_adapter_clean(struct net_device *netdev, int *budget) ++{ ++ int work_done; ++ int work_to_do = min(*budget, netdev->quota); ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ struct napi_struct *napi = &adapter->napi; ++ work_done = napi->poll(napi, work_to_do); ++ *budget -= work_done; ++ netdev->quota -= work_done; ++ return (work_done >= work_to_do) ? 1 : 0; ++} ++#endif /* NAPI */ ++#endif /* <= 2.6.24 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) ++#ifdef HAVE_TX_MQ ++void _kc_netif_tx_stop_all_queues(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int i; ++ ++ netif_stop_queue(netdev); ++ if (netif_is_multiqueue(netdev)) ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ netif_stop_subqueue(netdev, i); ++} ++void _kc_netif_tx_wake_all_queues(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int i; ++ ++ netif_wake_queue(netdev); ++ if (netif_is_multiqueue(netdev)) ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ netif_wake_subqueue(netdev, i); ++} ++void _kc_netif_tx_start_all_queues(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int i; ++ ++ netif_start_queue(netdev); ++ if (netif_is_multiqueue(netdev)) ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ netif_start_subqueue(netdev, i); ++} ++#endif /* HAVE_TX_MQ */ ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) ++ ++int ++_kc_pci_prepare_to_sleep(struct pci_dev *dev) ++{ ++ pci_power_t target_state; ++ int error; ++ ++ target_state = pci_choose_state(dev, PMSG_SUSPEND); ++ ++ pci_enable_wake(dev, target_state, true); ++ ++ error = pci_set_power_state(dev, target_state); ++ ++ if (error) ++ pci_enable_wake(dev, target_state, false); ++ ++ return error; ++} ++ ++int ++_kc_pci_wake_from_d3(struct pci_dev *dev, bool enable) ++{ ++ int err; ++ ++ err = pci_enable_wake(dev, PCI_D3cold, enable); ++ if (err) ++ goto out; ++ ++ err = pci_enable_wake(dev, PCI_D3hot, enable); ++ ++out: ++ return err; ++} ++#endif /* < 2.6.28 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) ) ++#endif /* < 2.6.29 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ) ++#endif /* < 2.6.30 */ +diff -r 5638ec0574f5 drivers/net/e1000e/kcompat.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/kcompat.h Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,1704 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _KCOMPAT_H_ ++#define _KCOMPAT_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* NAPI enable/disable flags here */ ++#define NAPI ++#ifdef E1000E_NO_NAPI ++#undef NAPI ++#endif ++ ++#define adapter_struct e1000_adapter ++#define CONFIG_E1000E_MSIX ++ ++/* and finally set defines so that the code sees the changes */ ++#ifdef NAPI ++#ifndef CONFIG_E1000E_NAPI ++#define CONFIG_E1000E_NAPI ++#endif ++#else ++#undef CONFIG_E1000E_NAPI ++#endif /* NAPI */ ++ ++/* MSI compatibility code for all kernels and drivers */ ++#ifdef DISABLE_PCI_MSI ++#undef CONFIG_PCI_MSI ++#endif ++#ifndef CONFIG_PCI_MSI ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) ) ++struct msix_entry { ++ u16 vector; /* kernel uses to write allocated vector */ ++ u16 entry; /* driver uses to specify entry, OS writes */ ++}; ++#endif ++#define pci_enable_msi(a) -ENOTSUPP ++#define pci_disable_msi(a) do {} while (0) ++#define pci_enable_msix(a, b, c) -ENOTSUPP ++#define pci_disable_msix(a) do {} while (0) ++#define msi_remove_pci_irq_vectors(a) do {} while (0) ++#endif /* CONFIG_PCI_MSI */ ++#ifdef DISABLE_PM ++#undef CONFIG_PM ++#endif ++ ++#ifdef DISABLE_NET_POLL_CONTROLLER ++#undef CONFIG_NET_POLL_CONTROLLER ++#endif ++ ++#ifndef PMSG_SUSPEND ++#define PMSG_SUSPEND 3 ++#endif ++ ++/* generic boolean compatibility */ ++#undef TRUE ++#undef FALSE ++#define TRUE true ++#define FALSE false ++#ifdef GCC_VERSION ++#if ( GCC_VERSION < 3000 ) ++#define _Bool char ++#endif ++#endif ++#ifndef bool ++#define bool _Bool ++#define true 1 ++#define false 0 ++#endif ++ ++ ++#ifndef module_param ++#define module_param(v,t,p) MODULE_PARM(v, "i"); ++#endif ++ ++#ifndef DMA_64BIT_MASK ++#define DMA_64BIT_MASK 0xffffffffffffffffULL ++#endif ++ ++#ifndef DMA_32BIT_MASK ++#define DMA_32BIT_MASK 0x00000000ffffffffULL ++#endif ++ ++#ifndef PCI_CAP_ID_EXP ++#define PCI_CAP_ID_EXP 0x10 ++#endif ++ ++#ifndef PCIE_LINK_STATE_L0S ++#define PCIE_LINK_STATE_L0S 1 ++#endif ++ ++#ifndef mmiowb ++#ifdef CONFIG_IA64 ++#define mmiowb() asm volatile ("mf.a" ::: "memory") ++#else ++#define mmiowb() ++#endif ++#endif ++ ++#ifndef SET_NETDEV_DEV ++#define SET_NETDEV_DEV(net, pdev) ++#endif ++ ++#ifndef HAVE_FREE_NETDEV ++#define free_netdev(x) kfree(x) ++#endif ++ ++#ifdef HAVE_POLL_CONTROLLER ++#define CONFIG_NET_POLL_CONTROLLER ++#endif ++ ++#ifndef NETDEV_TX_OK ++#define NETDEV_TX_OK 0 ++#endif ++ ++#ifndef NETDEV_TX_BUSY ++#define NETDEV_TX_BUSY 1 ++#endif ++ ++#ifndef NETDEV_TX_LOCKED ++#define NETDEV_TX_LOCKED -1 ++#endif ++ ++#ifndef SKB_DATAREF_SHIFT ++/* if we do not have the infrastructure to detect if skb_header is cloned ++ just return false in all cases */ ++#define skb_header_cloned(x) 0 ++#endif ++ ++#ifndef NETIF_F_GSO ++#define gso_size tso_size ++#define gso_segs tso_segs ++#endif ++ ++#ifndef NETIF_F_GRO ++#define vlan_gro_receive(_napi, _vlgrp, _vlan, _skb) \ ++ vlan_hwaccel_receive_skb(_skb, _vlgrp, _vlan) ++#define napi_gro_receive(_napi, _skb) netif_receive_skb(_skb) ++#endif ++ ++#ifndef CHECKSUM_PARTIAL ++#define CHECKSUM_PARTIAL CHECKSUM_HW ++#define CHECKSUM_COMPLETE CHECKSUM_HW ++#endif ++ ++#ifndef __read_mostly ++#define __read_mostly ++#endif ++ ++#ifndef HAVE_NETIF_MSG ++#define HAVE_NETIF_MSG 1 ++enum { ++ NETIF_MSG_DRV = 0x0001, ++ NETIF_MSG_PROBE = 0x0002, ++ NETIF_MSG_LINK = 0x0004, ++ NETIF_MSG_TIMER = 0x0008, ++ NETIF_MSG_IFDOWN = 0x0010, ++ NETIF_MSG_IFUP = 0x0020, ++ NETIF_MSG_RX_ERR = 0x0040, ++ NETIF_MSG_TX_ERR = 0x0080, ++ NETIF_MSG_TX_QUEUED = 0x0100, ++ NETIF_MSG_INTR = 0x0200, ++ NETIF_MSG_TX_DONE = 0x0400, ++ NETIF_MSG_RX_STATUS = 0x0800, ++ NETIF_MSG_PKTDATA = 0x1000, ++ NETIF_MSG_HW = 0x2000, ++ NETIF_MSG_WOL = 0x4000, ++}; ++ ++#else ++#define NETIF_MSG_HW 0x2000 ++#define NETIF_MSG_WOL 0x4000 ++#endif /* HAVE_NETIF_MSG */ ++ ++#ifndef MII_RESV1 ++#define MII_RESV1 0x17 /* Reserved... */ ++#endif ++ ++#ifndef unlikely ++#define unlikely(_x) _x ++#define likely(_x) _x ++#endif ++ ++#ifndef WARN_ON ++#define WARN_ON(x) ++#endif ++ ++#ifndef PCI_DEVICE ++#define PCI_DEVICE(vend,dev) \ ++ .vendor = (vend), .device = (dev), \ ++ .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID ++#endif ++ ++#ifndef num_online_cpus ++#define num_online_cpus() smp_num_cpus ++#endif ++ ++#ifndef _LINUX_RANDOM_H ++#include ++#endif ++ ++#ifndef DECLARE_BITMAP ++#ifndef BITS_TO_LONGS ++#define BITS_TO_LONGS(bits) (((bits)+BITS_PER_LONG-1)/BITS_PER_LONG) ++#endif ++#define DECLARE_BITMAP(name,bits) long name[BITS_TO_LONGS(bits)] ++#endif ++ ++#ifndef VLAN_HLEN ++#define VLAN_HLEN 4 ++#endif ++ ++#ifndef VLAN_ETH_HLEN ++#define VLAN_ETH_HLEN 18 ++#endif ++ ++#ifndef VLAN_ETH_FRAME_LEN ++#define VLAN_ETH_FRAME_LEN 1518 ++#endif ++ ++#ifndef DCA_GET_TAG_TWO_ARGS ++#define dca3_get_tag(a,b) dca_get_tag(b) ++#endif ++ ++ ++/*****************************************************************************/ ++/* Installations with ethtool version without eeprom, adapter id, or statistics ++ * support */ ++ ++#ifndef ETH_GSTRING_LEN ++#define ETH_GSTRING_LEN 32 ++#endif ++ ++#ifndef ETHTOOL_GSTATS ++#define ETHTOOL_GSTATS 0x1d ++#undef ethtool_drvinfo ++#define ethtool_drvinfo k_ethtool_drvinfo ++struct k_ethtool_drvinfo { ++ u32 cmd; ++ char driver[32]; ++ char version[32]; ++ char fw_version[32]; ++ char bus_info[32]; ++ char reserved1[32]; ++ char reserved2[16]; ++ u32 n_stats; ++ u32 testinfo_len; ++ u32 eedump_len; ++ u32 regdump_len; ++}; ++ ++struct ethtool_stats { ++ u32 cmd; ++ u32 n_stats; ++ u64 data[0]; ++}; ++#endif /* ETHTOOL_GSTATS */ ++ ++#ifndef ETHTOOL_PHYS_ID ++#define ETHTOOL_PHYS_ID 0x1c ++#endif /* ETHTOOL_PHYS_ID */ ++ ++#ifndef ETHTOOL_GSTRINGS ++#define ETHTOOL_GSTRINGS 0x1b ++enum ethtool_stringset { ++ ETH_SS_TEST = 0, ++ ETH_SS_STATS, ++}; ++struct ethtool_gstrings { ++ u32 cmd; /* ETHTOOL_GSTRINGS */ ++ u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/ ++ u32 len; /* number of strings in the string set */ ++ u8 data[0]; ++}; ++#endif /* ETHTOOL_GSTRINGS */ ++ ++#ifndef ETHTOOL_TEST ++#define ETHTOOL_TEST 0x1a ++enum ethtool_test_flags { ++ ETH_TEST_FL_OFFLINE = (1 << 0), ++ ETH_TEST_FL_FAILED = (1 << 1), ++}; ++struct ethtool_test { ++ u32 cmd; ++ u32 flags; ++ u32 reserved; ++ u32 len; ++ u64 data[0]; ++}; ++#endif /* ETHTOOL_TEST */ ++ ++#ifndef ETHTOOL_GEEPROM ++#define ETHTOOL_GEEPROM 0xb ++#undef ETHTOOL_GREGS ++struct ethtool_eeprom { ++ u32 cmd; ++ u32 magic; ++ u32 offset; ++ u32 len; ++ u8 data[0]; ++}; ++ ++struct ethtool_value { ++ u32 cmd; ++ u32 data; ++}; ++#endif /* ETHTOOL_GEEPROM */ ++ ++#ifndef ETHTOOL_GLINK ++#define ETHTOOL_GLINK 0xa ++#endif /* ETHTOOL_GLINK */ ++ ++#ifndef ETHTOOL_GREGS ++#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers */ ++#define ethtool_regs _kc_ethtool_regs ++/* for passing big chunks of data */ ++struct _kc_ethtool_regs { ++ u32 cmd; ++ u32 version; /* driver-specific, indicates different chips/revs */ ++ u32 len; /* bytes */ ++ u8 data[0]; ++}; ++#endif /* ETHTOOL_GREGS */ ++ ++#ifndef ETHTOOL_GMSGLVL ++#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */ ++#endif ++#ifndef ETHTOOL_SMSGLVL ++#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level, priv. */ ++#endif ++#ifndef ETHTOOL_NWAY_RST ++#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation, priv */ ++#endif ++#ifndef ETHTOOL_GLINK ++#define ETHTOOL_GLINK 0x0000000a /* Get link status */ ++#endif ++#ifndef ETHTOOL_GEEPROM ++#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */ ++#endif ++#ifndef ETHTOOL_SEEPROM ++#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */ ++#endif ++#ifndef ETHTOOL_GCOALESCE ++#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */ ++/* for configuring coalescing parameters of chip */ ++#define ethtool_coalesce _kc_ethtool_coalesce ++struct _kc_ethtool_coalesce { ++ u32 cmd; /* ETHTOOL_{G,S}COALESCE */ ++ ++ /* How many usecs to delay an RX interrupt after ++ * a packet arrives. If 0, only rx_max_coalesced_frames ++ * is used. ++ */ ++ u32 rx_coalesce_usecs; ++ ++ /* How many packets to delay an RX interrupt after ++ * a packet arrives. If 0, only rx_coalesce_usecs is ++ * used. It is illegal to set both usecs and max frames ++ * to zero as this would cause RX interrupts to never be ++ * generated. ++ */ ++ u32 rx_max_coalesced_frames; ++ ++ /* Same as above two parameters, except that these values ++ * apply while an IRQ is being serviced by the host. Not ++ * all cards support this feature and the values are ignored ++ * in that case. ++ */ ++ u32 rx_coalesce_usecs_irq; ++ u32 rx_max_coalesced_frames_irq; ++ ++ /* How many usecs to delay a TX interrupt after ++ * a packet is sent. If 0, only tx_max_coalesced_frames ++ * is used. ++ */ ++ u32 tx_coalesce_usecs; ++ ++ /* How many packets to delay a TX interrupt after ++ * a packet is sent. If 0, only tx_coalesce_usecs is ++ * used. It is illegal to set both usecs and max frames ++ * to zero as this would cause TX interrupts to never be ++ * generated. ++ */ ++ u32 tx_max_coalesced_frames; ++ ++ /* Same as above two parameters, except that these values ++ * apply while an IRQ is being serviced by the host. Not ++ * all cards support this feature and the values are ignored ++ * in that case. ++ */ ++ u32 tx_coalesce_usecs_irq; ++ u32 tx_max_coalesced_frames_irq; ++ ++ /* How many usecs to delay in-memory statistics ++ * block updates. Some drivers do not have an in-memory ++ * statistic block, and in such cases this value is ignored. ++ * This value must not be zero. ++ */ ++ u32 stats_block_coalesce_usecs; ++ ++ /* Adaptive RX/TX coalescing is an algorithm implemented by ++ * some drivers to improve latency under low packet rates and ++ * improve throughput under high packet rates. Some drivers ++ * only implement one of RX or TX adaptive coalescing. Anything ++ * not implemented by the driver causes these values to be ++ * silently ignored. ++ */ ++ u32 use_adaptive_rx_coalesce; ++ u32 use_adaptive_tx_coalesce; ++ ++ /* When the packet rate (measured in packets per second) ++ * is below pkt_rate_low, the {rx,tx}_*_low parameters are ++ * used. ++ */ ++ u32 pkt_rate_low; ++ u32 rx_coalesce_usecs_low; ++ u32 rx_max_coalesced_frames_low; ++ u32 tx_coalesce_usecs_low; ++ u32 tx_max_coalesced_frames_low; ++ ++ /* When the packet rate is below pkt_rate_high but above ++ * pkt_rate_low (both measured in packets per second) the ++ * normal {rx,tx}_* coalescing parameters are used. ++ */ ++ ++ /* When the packet rate is (measured in packets per second) ++ * is above pkt_rate_high, the {rx,tx}_*_high parameters are ++ * used. ++ */ ++ u32 pkt_rate_high; ++ u32 rx_coalesce_usecs_high; ++ u32 rx_max_coalesced_frames_high; ++ u32 tx_coalesce_usecs_high; ++ u32 tx_max_coalesced_frames_high; ++ ++ /* How often to do adaptive coalescing packet rate sampling, ++ * measured in seconds. Must not be zero. ++ */ ++ u32 rate_sample_interval; ++}; ++#endif /* ETHTOOL_GCOALESCE */ ++ ++#ifndef ETHTOOL_SCOALESCE ++#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */ ++#endif ++#ifndef ETHTOOL_GRINGPARAM ++#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */ ++/* for configuring RX/TX ring parameters */ ++#define ethtool_ringparam _kc_ethtool_ringparam ++struct _kc_ethtool_ringparam { ++ u32 cmd; /* ETHTOOL_{G,S}RINGPARAM */ ++ ++ /* Read only attributes. These indicate the maximum number ++ * of pending RX/TX ring entries the driver will allow the ++ * user to set. ++ */ ++ u32 rx_max_pending; ++ u32 rx_mini_max_pending; ++ u32 rx_jumbo_max_pending; ++ u32 tx_max_pending; ++ ++ /* Values changeable by the user. The valid values are ++ * in the range 1 to the "*_max_pending" counterpart above. ++ */ ++ u32 rx_pending; ++ u32 rx_mini_pending; ++ u32 rx_jumbo_pending; ++ u32 tx_pending; ++}; ++#endif /* ETHTOOL_GRINGPARAM */ ++ ++#ifndef ETHTOOL_SRINGPARAM ++#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters, priv. */ ++#endif ++#ifndef ETHTOOL_GPAUSEPARAM ++#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */ ++/* for configuring link flow control parameters */ ++#define ethtool_pauseparam _kc_ethtool_pauseparam ++struct _kc_ethtool_pauseparam { ++ u32 cmd; /* ETHTOOL_{G,S}PAUSEPARAM */ ++ ++ /* If the link is being auto-negotiated (via ethtool_cmd.autoneg ++ * being true) the user may set 'autoneg' here non-zero to have the ++ * pause parameters be auto-negotiated too. In such a case, the ++ * {rx,tx}_pause values below determine what capabilities are ++ * advertised. ++ * ++ * If 'autoneg' is zero or the link is not being auto-negotiated, ++ * then {rx,tx}_pause force the driver to use/not-use pause ++ * flow control. ++ */ ++ u32 autoneg; ++ u32 rx_pause; ++ u32 tx_pause; ++}; ++#endif /* ETHTOOL_GPAUSEPARAM */ ++ ++#ifndef ETHTOOL_SPAUSEPARAM ++#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */ ++#endif ++#ifndef ETHTOOL_GRXCSUM ++#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_SRXCSUM ++#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_GTXCSUM ++#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_STXCSUM ++#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_GSG ++#define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable ++ * (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_SSG ++#define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable ++ * (ethtool_value). */ ++#endif ++#ifndef ETHTOOL_TEST ++#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test, priv. */ ++#endif ++#ifndef ETHTOOL_GSTRINGS ++#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */ ++#endif ++#ifndef ETHTOOL_PHYS_ID ++#define ETHTOOL_PHYS_ID 0x0000001c /* identify the NIC */ ++#endif ++#ifndef ETHTOOL_GSTATS ++#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */ ++#endif ++#ifndef ETHTOOL_GTSO ++#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_STSO ++#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */ ++#endif ++ ++#ifndef ETHTOOL_BUSINFO_LEN ++#define ETHTOOL_BUSINFO_LEN 32 ++#endif ++ ++/*****************************************************************************/ ++/* 2.4.3 => 2.4.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) ) ++ ++/**************************************/ ++/* PCI DRIVER API */ ++ ++#ifndef pci_set_dma_mask ++#define pci_set_dma_mask _kc_pci_set_dma_mask ++extern int _kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask); ++#endif ++ ++#ifndef pci_request_regions ++#define pci_request_regions _kc_pci_request_regions ++extern int _kc_pci_request_regions(struct pci_dev *pdev, char *res_name); ++#endif ++ ++#ifndef pci_release_regions ++#define pci_release_regions _kc_pci_release_regions ++extern void _kc_pci_release_regions(struct pci_dev *pdev); ++#endif ++ ++/**************************************/ ++/* NETWORK DRIVER API */ ++ ++#ifndef alloc_etherdev ++#define alloc_etherdev _kc_alloc_etherdev ++extern struct net_device * _kc_alloc_etherdev(int sizeof_priv); ++#endif ++ ++#ifndef is_valid_ether_addr ++#define is_valid_ether_addr _kc_is_valid_ether_addr ++extern int _kc_is_valid_ether_addr(u8 *addr); ++#endif ++ ++/**************************************/ ++/* MISCELLANEOUS */ ++ ++#ifndef INIT_TQUEUE ++#define INIT_TQUEUE(_tq, _routine, _data) \ ++ do { \ ++ INIT_LIST_HEAD(&(_tq)->list); \ ++ (_tq)->sync = 0; \ ++ (_tq)->routine = _routine; \ ++ (_tq)->data = _data; \ ++ } while (0) ++#endif ++ ++#endif /* 2.4.3 => 2.4.0 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,5) ) ++/* Generic MII registers. */ ++#define MII_BMCR 0x00 /* Basic mode control register */ ++#define MII_BMSR 0x01 /* Basic mode status register */ ++#define MII_PHYSID1 0x02 /* PHYS ID 1 */ ++#define MII_PHYSID2 0x03 /* PHYS ID 2 */ ++#define MII_ADVERTISE 0x04 /* Advertisement control reg */ ++#define MII_LPA 0x05 /* Link partner ability reg */ ++#define MII_EXPANSION 0x06 /* Expansion register */ ++/* Basic mode control register. */ ++#define BMCR_FULLDPLX 0x0100 /* Full duplex */ ++#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ ++/* Basic mode status register. */ ++#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ ++#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ ++#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ ++#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ ++#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ ++#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ ++/* Advertisement control register. */ ++#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ ++#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ ++#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ ++#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ ++#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ ++#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ++ ADVERTISE_100HALF | ADVERTISE_100FULL) ++/* Expansion register for auto-negotiation. */ ++#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ ++#endif ++ ++/*****************************************************************************/ ++/* 2.4.6 => 2.4.3 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) ) ++ ++#ifndef pci_set_power_state ++#define pci_set_power_state _kc_pci_set_power_state ++extern int _kc_pci_set_power_state(struct pci_dev *dev, int state); ++#endif ++ ++#ifndef pci_enable_wake ++#define pci_enable_wake _kc_pci_enable_wake ++extern int _kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable); ++#endif ++ ++#ifndef pci_disable_device ++#define pci_disable_device _kc_pci_disable_device ++extern void _kc_pci_disable_device(struct pci_dev *pdev); ++#endif ++ ++/* PCI PM entry point syntax changed, so don't support suspend/resume */ ++#undef CONFIG_PM ++ ++#endif /* 2.4.6 => 2.4.3 */ ++ ++#ifndef HAVE_PCI_SET_MWI ++#define pci_set_mwi(X) pci_write_config_word(X, \ ++ PCI_COMMAND, adapter->hw.bus.pci_cmd_word | \ ++ PCI_COMMAND_INVALIDATE); ++#define pci_clear_mwi(X) pci_write_config_word(X, \ ++ PCI_COMMAND, adapter->hw.bus.pci_cmd_word & \ ++ ~PCI_COMMAND_INVALIDATE); ++#endif ++ ++/*****************************************************************************/ ++/* 2.4.10 => 2.4.9 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,10) ) ++ ++/**************************************/ ++/* MODULE API */ ++ ++#ifndef MODULE_LICENSE ++ #define MODULE_LICENSE(X) ++#endif ++ ++/**************************************/ ++/* OTHER */ ++ ++#undef min ++#define min(x,y) ({ \ ++ const typeof(x) _x = (x); \ ++ const typeof(y) _y = (y); \ ++ (void) (&_x == &_y); \ ++ _x < _y ? _x : _y; }) ++ ++#undef max ++#define max(x,y) ({ \ ++ const typeof(x) _x = (x); \ ++ const typeof(y) _y = (y); \ ++ (void) (&_x == &_y); \ ++ _x > _y ? _x : _y; }) ++ ++#define min_t(type,x,y) ({ \ ++ type _x = (x); \ ++ type _y = (y); \ ++ _x < _y ? _x : _y; }) ++ ++#define max_t(type,x,y) ({ \ ++ type _x = (x); \ ++ type _y = (y); \ ++ _x > _y ? _x : _y; }) ++ ++#ifndef list_for_each_safe ++#define list_for_each_safe(pos, n, head) \ ++ for (pos = (head)->next, n = pos->next; pos != (head); \ ++ pos = n, n = pos->next) ++#endif ++ ++#endif /* 2.4.10 -> 2.4.6 */ ++ ++ ++/*****************************************************************************/ ++/* 2.4.13 => 2.4.10 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) ) ++ ++/**************************************/ ++/* PCI DMA MAPPING */ ++ ++#ifndef virt_to_page ++ #define virt_to_page(v) (mem_map + (virt_to_phys(v) >> PAGE_SHIFT)) ++#endif ++ ++#ifndef pci_map_page ++#define pci_map_page _kc_pci_map_page ++extern u64 _kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, size_t size, int direction); ++#endif ++ ++#ifndef pci_unmap_page ++#define pci_unmap_page _kc_pci_unmap_page ++extern void _kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, int direction); ++#endif ++ ++/* pci_set_dma_mask takes dma_addr_t, which is only 32-bits prior to 2.4.13 */ ++ ++#undef DMA_32BIT_MASK ++#define DMA_32BIT_MASK 0xffffffff ++#undef DMA_64BIT_MASK ++#define DMA_64BIT_MASK 0xffffffff ++ ++/**************************************/ ++/* OTHER */ ++ ++#ifndef cpu_relax ++#define cpu_relax() rep_nop() ++#endif ++ ++#endif /* 2.4.13 => 2.4.10 */ ++ ++/*****************************************************************************/ ++/* 2.4.17 => 2.4.12 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17) ) ++ ++#ifndef __devexit_p ++ #define __devexit_p(x) &(x) ++#endif ++ ++#endif /* 2.4.17 => 2.4.13 */ ++ ++/*****************************************************************************/ ++/* 2.4.20 => 2.4.19 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,20) ) ++ ++/* we won't support NAPI on less than 2.4.20 */ ++#ifdef NAPI ++#undef CONFIG_E1000E_NAPI ++#endif ++ ++#endif /* 2.4.20 => 2.4.19 */ ++ ++/*****************************************************************************/ ++/* < 2.4.21 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,21) ) ++#define skb_pad(x,y) _kc_skb_pad(x, y) ++struct sk_buff * _kc_skb_pad(struct sk_buff *skb, int pad); ++#endif /* < 2.4.21 */ ++ ++/*****************************************************************************/ ++/* 2.4.22 => 2.4.17 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) ) ++#define pci_name(x) ((x)->slot_name) ++#endif ++ ++/*****************************************************************************/ ++/*****************************************************************************/ ++/* 2.4.23 => 2.4.22 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23) ) ++/*****************************************************************************/ ++#ifdef NAPI ++#ifndef netif_poll_disable ++#define netif_poll_disable(x) _kc_netif_poll_disable(x) ++static inline void _kc_netif_poll_disable(struct net_device *netdev) ++{ ++ while (test_and_set_bit(__LINK_STATE_RX_SCHED, &netdev->state)) { ++ /* No hurry */ ++ current->state = TASK_INTERRUPTIBLE; ++ schedule_timeout(1); ++ } ++} ++#endif ++ ++#ifndef netif_poll_enable ++#define netif_poll_enable(x) _kc_netif_poll_enable(x) ++static inline void _kc_netif_poll_enable(struct net_device *netdev) ++{ ++ clear_bit(__LINK_STATE_RX_SCHED, &netdev->state); ++} ++#endif ++#endif /* NAPI */ ++#ifndef netif_tx_disable ++#define netif_tx_disable(x) _kc_netif_tx_disable(x) ++static inline void _kc_netif_tx_disable(struct net_device *dev) ++{ ++ spin_lock_bh(&dev->xmit_lock); ++ netif_stop_queue(dev); ++ spin_unlock_bh(&dev->xmit_lock); ++} ++#endif ++#endif /* 2.4.23 => 2.4.22 */ ++ ++/*****************************************************************************/ ++/* 2.6.4 => 2.6.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,25) || \ ++ ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \ ++ LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) ) ++#define ETHTOOL_OPS_COMPAT ++#endif /* 2.6.4 => 2.6.0 */ ++ ++/*****************************************************************************/ ++/* 2.5.71 => 2.4.x */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,71) ) ++#include ++#define sk_protocol protocol ++ ++#define pci_get_device pci_find_device ++#endif /* 2.5.70 => 2.4.x */ ++ ++/*****************************************************************************/ ++/* < 2.4.27 or 2.6.0 <= 2.6.5 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) || \ ++ ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \ ++ LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) ) ++ ++#ifndef netif_msg_init ++#define netif_msg_init _kc_netif_msg_init ++static inline u32 _kc_netif_msg_init(int debug_value, int default_msg_enable_bits) ++{ ++ /* use default */ ++ if (debug_value < 0 || debug_value >= (sizeof(u32) * 8)) ++ return default_msg_enable_bits; ++ if (debug_value == 0) /* no output */ ++ return 0; ++ /* set low N bits */ ++ return (1 << debug_value) -1; ++} ++#endif ++ ++#endif /* < 2.4.27 or 2.6.0 <= 2.6.5 */ ++/*****************************************************************************/ ++#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \ ++ (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \ ++ ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) ))) ++#define netdev_priv(x) x->priv ++#endif ++ ++/*****************************************************************************/ ++/* <= 2.5.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ) ++#undef pci_register_driver ++#define pci_register_driver pci_module_init ++ ++#define dev_err(__unused_dev, format, arg...) \ ++ printk(KERN_ERR "%s: " format, pci_name(adapter->pdev) , ## arg) ++#define dev_warn(__unused_dev, format, arg...) \ ++ printk(KERN_WARNING "%s: " format, pci_name(pdev) , ## arg) ++ ++/* hlist_* code - double linked lists */ ++struct hlist_head { ++ struct hlist_node *first; ++}; ++ ++struct hlist_node { ++ struct hlist_node *next, **pprev; ++}; ++ ++static inline void __hlist_del(struct hlist_node *n) ++{ ++ struct hlist_node *next = n->next; ++ struct hlist_node **pprev = n->pprev; ++ *pprev = next; ++ if (next) ++ next->pprev = pprev; ++} ++ ++static inline void hlist_del(struct hlist_node *n) ++{ ++ __hlist_del(n); ++ n->next = NULL; ++ n->pprev = NULL; ++} ++ ++static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) ++{ ++ struct hlist_node *first = h->first; ++ n->next = first; ++ if (first) ++ first->pprev = &n->next; ++ h->first = n; ++ n->pprev = &h->first; ++} ++ ++static inline int hlist_empty(const struct hlist_head *h) ++{ ++ return !h->first; ++} ++#define HLIST_HEAD_INIT { .first = NULL } ++#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL } ++#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL) ++static inline void INIT_HLIST_NODE(struct hlist_node *h) ++{ ++ h->next = NULL; ++ h->pprev = NULL; ++} ++#define hlist_entry(ptr, type, member) container_of(ptr,type,member) ++ ++#define hlist_for_each_entry(tpos, pos, head, member) \ ++ for (pos = (head)->first; \ ++ pos && ({ prefetch(pos->next); 1;}) && \ ++ ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ ++ pos = pos->next) ++ ++#define hlist_for_each_entry_safe(tpos, pos, n, head, member) \ ++ for (pos = (head)->first; \ ++ pos && ({ n = pos->next; 1; }) && \ ++ ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ ++ pos = n) ++ ++/* we ignore GFP here */ ++#define dma_alloc_coherent(dv, sz, dma, gfp) \ ++ pci_alloc_consistent(pdev, (sz), (dma)) ++#define dma_free_coherent(dv, sz, addr, dma_addr) \ ++ pci_free_consistent(pdev, (sz), (addr), (dma_addr)) ++ ++#ifndef might_sleep ++#define might_sleep() ++#endif ++ ++#endif /* <= 2.5.0 */ ++ ++/*****************************************************************************/ ++/* 2.5.28 => 2.4.23 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) ) ++ ++static inline void _kc_synchronize_irq(void) ++{ ++ synchronize_irq(); ++} ++#undef synchronize_irq ++#define synchronize_irq(X) _kc_synchronize_irq() ++ ++#include ++#define work_struct tq_struct ++#undef INIT_WORK ++#define INIT_WORK(a,b) INIT_TQUEUE(a,(void (*)(void *))b,a) ++#undef container_of ++#define container_of list_entry ++#define schedule_work schedule_task ++#define flush_scheduled_work flush_scheduled_tasks ++#define cancel_work_sync(x) flush_scheduled_work() ++ ++#endif /* 2.5.28 => 2.4.17 */ ++ ++/*****************************************************************************/ ++/* 2.6.0 => 2.5.28 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) ++#define MODULE_INFO(version, _version) ++#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT ++#define CONFIG_E1000_DISABLE_PACKET_SPLIT 1 ++#endif ++#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT ++#define CONFIG_IGB_DISABLE_PACKET_SPLIT 1 ++#endif ++ ++#define pci_set_consistent_dma_mask(dev,mask) 1 ++ ++#undef dev_put ++#define dev_put(dev) __dev_put(dev) ++ ++#ifndef skb_fill_page_desc ++#define skb_fill_page_desc _kc_skb_fill_page_desc ++extern void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int off, int size); ++#endif ++ ++#undef ALIGN ++#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1)) ++ ++#ifndef page_count ++#define page_count(p) atomic_read(&(p)->count) ++#endif ++ ++/* find_first_bit and find_next bit are not defined for most ++ * 2.4 kernels (except for the redhat 2.4.21 kernels ++ */ ++#include ++#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG) ++#undef find_next_bit ++#define find_next_bit _kc_find_next_bit ++extern unsigned long _kc_find_next_bit(const unsigned long *addr, ++ unsigned long size, ++ unsigned long offset); ++#define find_first_bit(addr, size) find_next_bit((addr), (size), 0) ++ ++#endif /* 2.6.0 => 2.5.28 */ ++ ++/*****************************************************************************/ ++/* 2.6.4 => 2.6.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) ++#define MODULE_VERSION(_version) MODULE_INFO(version, _version) ++#endif /* 2.6.4 => 2.6.0 */ ++ ++/*****************************************************************************/ ++/* 2.6.5 => 2.6.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) ++#define pci_dma_sync_single_for_cpu pci_dma_sync_single ++#define pci_dma_sync_single_for_device pci_dma_sync_single_for_cpu ++#endif /* 2.6.5 => 2.6.0 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,6) ) ++/* taken from 2.6 include/linux/bitmap.h */ ++#undef bitmap_zero ++#define bitmap_zero _kc_bitmap_zero ++static inline void _kc_bitmap_zero(unsigned long *dst, int nbits) ++{ ++ if (nbits <= BITS_PER_LONG) ++ *dst = 0UL; ++ else { ++ int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long); ++ memset(dst, 0, len); ++ } ++} ++#endif /* < 2.6.6 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) ) ++#undef if_mii ++#define if_mii _kc_if_mii ++static inline struct mii_ioctl_data *_kc_if_mii(struct ifreq *rq) ++{ ++ return (struct mii_ioctl_data *) &rq->ifr_ifru; ++} ++#endif /* < 2.6.7 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) ) ++#ifndef PCI_EXP_DEVCTL ++#define PCI_EXP_DEVCTL 8 ++#endif ++#ifndef PCI_EXP_DEVCTL_CERE ++#define PCI_EXP_DEVCTL_CERE 0x0001 ++#endif ++#define msleep(x) do { set_current_state(TASK_UNINTERRUPTIBLE); \ ++ schedule_timeout((x * HZ)/1000 + 2); \ ++ } while (0) ++ ++#endif /* < 2.6.8 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)) ++#include ++#define __iomem ++ ++#ifndef kcalloc ++#define kcalloc(n, size, flags) _kc_kzalloc(((n) * (size)), flags) ++extern void *_kc_kzalloc(size_t size, int flags); ++#endif ++#define MSEC_PER_SEC 1000L ++static inline unsigned int _kc_jiffies_to_msecs(const unsigned long j) ++{ ++#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) ++ return (MSEC_PER_SEC / HZ) * j; ++#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) ++ return (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC); ++#else ++ return (j * MSEC_PER_SEC) / HZ; ++#endif ++} ++static inline unsigned long _kc_msecs_to_jiffies(const unsigned int m) ++{ ++ if (m > _kc_jiffies_to_msecs(MAX_JIFFY_OFFSET)) ++ return MAX_JIFFY_OFFSET; ++#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) ++ return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ); ++#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) ++ return m * (HZ / MSEC_PER_SEC); ++#else ++ return (m * HZ + MSEC_PER_SEC - 1) / MSEC_PER_SEC; ++#endif ++} ++ ++#define msleep_interruptible _kc_msleep_interruptible ++static inline unsigned long _kc_msleep_interruptible(unsigned int msecs) ++{ ++ unsigned long timeout = _kc_msecs_to_jiffies(msecs) + 1; ++ ++ while (timeout && !signal_pending(current)) { ++ __set_current_state(TASK_INTERRUPTIBLE); ++ timeout = schedule_timeout(timeout); ++ } ++ return _kc_jiffies_to_msecs(timeout); ++} ++ ++/* Basic mode control register. */ ++#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ ++ ++#ifndef __le16 ++#define __le16 u16 ++#endif ++#ifndef __le32 ++#define __le32 u32 ++#endif ++#ifndef __le64 ++#define __le64 u64 ++#endif ++ ++#ifdef pci_dma_mapping_error ++#undef pci_dma_mapping_error ++#endif ++#define pci_dma_mapping_error _kc_pci_dma_mapping_error ++static inline int _kc_pci_dma_mapping_error(struct pci_dev *pdev, ++ dma_addr_t dma_addr) ++{ ++ return dma_addr == 0; ++} ++ ++#endif /* < 2.6.9 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ) ++#ifdef module_param_array_named ++#undef module_param_array_named ++#define module_param_array_named(name, array, type, nump, perm) \ ++ static struct kparam_array __param_arr_##name \ ++ = { ARRAY_SIZE(array), nump, param_set_##type, param_get_##type, \ ++ sizeof(array[0]), array }; \ ++ module_param_call(name, param_array_set, param_array_get, \ ++ &__param_arr_##name, perm) ++#endif /* module_param_array_named */ ++#endif /* < 2.6.10 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) ) ++#define PCI_D0 0 ++#define PCI_D1 1 ++#define PCI_D2 2 ++#define PCI_D3hot 3 ++#define PCI_D3cold 4 ++typedef int pci_power_t; ++#define pci_choose_state(pdev,state) state ++#define PMSG_SUSPEND 3 ++#define PCI_EXP_LNKCTL 16 ++ ++#undef NETIF_F_LLTX ++ ++#ifndef ARCH_HAS_PREFETCH ++#define prefetch(X) ++#endif ++ ++#ifndef NET_IP_ALIGN ++#define NET_IP_ALIGN 2 ++#endif ++ ++#define KC_USEC_PER_SEC 1000000L ++#define usecs_to_jiffies _kc_usecs_to_jiffies ++static inline unsigned int _kc_jiffies_to_usecs(const unsigned long j) ++{ ++#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ) ++ return (KC_USEC_PER_SEC / HZ) * j; ++#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC) ++ return (j + (HZ / KC_USEC_PER_SEC) - 1)/(HZ / KC_USEC_PER_SEC); ++#else ++ return (j * KC_USEC_PER_SEC) / HZ; ++#endif ++} ++static inline unsigned long _kc_usecs_to_jiffies(const unsigned int m) ++{ ++ if (m > _kc_jiffies_to_usecs(MAX_JIFFY_OFFSET)) ++ return MAX_JIFFY_OFFSET; ++#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ) ++ return (m + (KC_USEC_PER_SEC / HZ) - 1) / (KC_USEC_PER_SEC / HZ); ++#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC) ++ return m * (HZ / KC_USEC_PER_SEC); ++#else ++ return (m * HZ + KC_USEC_PER_SEC - 1) / KC_USEC_PER_SEC; ++#endif ++} ++#endif /* < 2.6.11 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,12) ) ++#include ++#define USE_REBOOT_NOTIFIER ++ ++/* Generic MII registers. */ ++#define MII_CTRL1000 0x09 /* 1000BASE-T control */ ++#define MII_STAT1000 0x0a /* 1000BASE-T status */ ++/* Advertisement control register. */ ++#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ ++#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymmetric pause */ ++/* 1000BASE-T Control register */ ++#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ ++#endif /* < 2.6.12 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) ) ++#define pm_message_t u32 ++#ifndef kzalloc ++#define kzalloc _kc_kzalloc ++extern void *_kc_kzalloc(size_t size, int flags); ++#endif ++ ++/* Generic MII registers. */ ++#define MII_ESTATUS 0x0f /* Extended Status */ ++/* Basic mode status register. */ ++#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ ++/* Extended status register. */ ++#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ ++#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ ++#endif /* < 2.6.14 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) ) ++#ifndef device_can_wakeup ++#define device_can_wakeup(dev) (1) ++#endif ++#ifndef device_set_wakeup_enable ++#define device_set_wakeup_enable(dev, val) do{}while(0) ++#endif ++#ifndef device_init_wakeup ++#define device_init_wakeup(dev,val) do {} while (0) ++#endif ++#endif /* < 2.6.15 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) ) ++#define DEFINE_MUTEX(x) DECLARE_MUTEX(x) ++#define mutex_lock(x) down_interruptible(x) ++#define mutex_unlock(x) up(x) ++ ++#undef HAVE_PCI_ERS ++#else /* 2.6.16 and above */ ++#undef HAVE_PCI_ERS ++#define HAVE_PCI_ERS ++#endif /* < 2.6.16 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ) ++ ++#ifndef IRQ_HANDLED ++#define irqreturn_t void ++#define IRQ_HANDLED ++#define IRQ_NONE ++#endif ++ ++#ifndef IRQF_PROBE_SHARED ++#ifdef SA_PROBEIRQ ++#define IRQF_PROBE_SHARED SA_PROBEIRQ ++#else ++#define IRQF_PROBE_SHARED 0 ++#endif ++#endif ++ ++#ifndef IRQF_SHARED ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#ifndef ARRAY_SIZE ++#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) ++#endif ++ ++#ifndef netdev_alloc_skb ++#define netdev_alloc_skb _kc_netdev_alloc_skb ++extern struct sk_buff *_kc_netdev_alloc_skb(struct net_device *dev, ++ unsigned int length); ++#endif ++ ++#ifndef skb_is_gso ++#ifdef NETIF_F_TSO ++#define skb_is_gso _kc_skb_is_gso ++static inline int _kc_skb_is_gso(const struct sk_buff *skb) ++{ ++ return skb_shinfo(skb)->gso_size; ++} ++#else ++#define skb_is_gso(a) 0 ++#endif ++#endif ++ ++#endif /* < 2.6.18 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ) ++ ++#ifndef DIV_ROUND_UP ++#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) ++#endif ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) ) ++#ifndef RHEL_RELEASE_CODE ++#define RHEL_RELEASE_CODE 0 ++#endif ++#ifndef RHEL_RELEASE_VERSION ++#define RHEL_RELEASE_VERSION(a,b) 0 ++#endif ++#ifndef AX_RELEASE_CODE ++#define AX_RELEASE_CODE 0 ++#endif ++#ifndef AX_RELEASE_VERSION ++#define AX_RELEASE_VERSION(a,b) 0 ++#endif ++#if (!(( RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,4) ) && ( RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0) ) || ( RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,0) ) || (AX_RELEASE_CODE > AX_RELEASE_VERSION(3,0)))) ++typedef irqreturn_t (*irq_handler_t)(int, void*, struct pt_regs *); ++#endif ++#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0)) ++#undef CONFIG_INET_LRO ++#undef CONFIG_INET_LRO_MODULE ++#ifdef IXGBE_FCOE ++#undef CONFIG_FCOE ++#undef CONFIG_FCOE_MODULE ++#endif /* IXGBE_FCOE */ ++#endif ++typedef irqreturn_t (*new_handler_t)(int, void*); ++static inline irqreturn_t _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id) ++#else /* 2.4.x */ ++typedef void (*irq_handler_t)(int, void*, struct pt_regs *); ++typedef void (*new_handler_t)(int, void*); ++static inline int _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id) ++#endif /* >= 2.5.x */ ++{ ++ irq_handler_t new_handler = (irq_handler_t) handler; ++ return request_irq(irq, new_handler, flags, devname, dev_id); ++} ++ ++#undef request_irq ++#define request_irq(irq, handler, flags, devname, dev_id) _kc_request_irq((irq), (handler), (flags), (devname), (dev_id)) ++ ++#define irq_handler_t new_handler_t ++/* pci_restore_state and pci_save_state handles MSI/PCIE from 2.6.19 */ ++#define PCIE_CONFIG_SPACE_LEN 256 ++#define PCI_CONFIG_SPACE_LEN 64 ++#define PCIE_LINK_STATUS 0x12 ++#define pci_config_space_ich8lan() { \ ++ if (adapter->flags & FLAG_IS_ICH) \ ++ size = PCIE_CONFIG_SPACE_LEN; \ ++} ++#undef pci_save_state ++extern int _kc_pci_save_state(struct pci_dev *); ++#define pci_save_state(pdev) _kc_pci_save_state(pdev) ++#undef pci_restore_state ++extern void _kc_pci_restore_state(struct pci_dev *); ++#define pci_restore_state(pdev) _kc_pci_restore_state(pdev) ++#ifdef HAVE_PCI_ERS ++#undef free_netdev ++extern void _kc_free_netdev(struct net_device *); ++#define free_netdev(netdev) _kc_free_netdev(netdev) ++#endif ++static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev) ++{ ++ return 0; ++} ++#define pci_disable_pcie_error_reporting(dev) do {} while (0) ++#define pci_cleanup_aer_uncorrect_error_status(dev) do {} while (0) ++#else /* 2.6.19 */ ++#include ++#endif /* < 2.6.19 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ) ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,28) ) ++#undef INIT_WORK ++#define INIT_WORK(_work, _func) \ ++do { \ ++ INIT_LIST_HEAD(&(_work)->entry); \ ++ (_work)->pending = 0; \ ++ (_work)->func = (void (*)(void *))_func; \ ++ (_work)->data = _work; \ ++ init_timer(&(_work)->timer); \ ++} while (0) ++#endif ++ ++#ifndef PCI_VDEVICE ++#define PCI_VDEVICE(ven, dev) \ ++ PCI_VENDOR_ID_##ven, (dev), \ ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0 ++#endif ++ ++#ifndef round_jiffies ++#define round_jiffies(x) x ++#endif ++ ++#define csum_offset csum ++ ++#endif /* < 2.6.20 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) ) ++#define to_net_dev(class) container_of(class, struct net_device, class_dev) ++#define NETDEV_CLASS_DEV ++#define vlan_group_get_device(vg, id) (vg->vlan_devices[id]) ++#define vlan_group_set_device(vg, id, dev) if (vg) vg->vlan_devices[id] = dev; ++#define pci_channel_offline(pdev) (pdev->error_state && \ ++ pdev->error_state != pci_channel_io_normal) ++#define pci_request_selected_regions(pdev, bars, name) \ ++ pci_request_regions(pdev, name) ++#define pci_release_selected_regions(pdev, bars) pci_release_regions(pdev); ++#endif /* < 2.6.21 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) ) ++#define tcp_hdr(skb) (skb->h.th) ++#define tcp_hdrlen(skb) (skb->h.th->doff << 2) ++#define skb_transport_offset(skb) (skb->h.raw - skb->data) ++#define skb_transport_header(skb) (skb->h.raw) ++#define ipv6_hdr(skb) (skb->nh.ipv6h) ++#define ip_hdr(skb) (skb->nh.iph) ++#define skb_network_offset(skb) (skb->nh.raw - skb->data) ++#define skb_network_header(skb) (skb->nh.raw) ++#define skb_tail_pointer(skb) skb->tail ++#define skb_copy_to_linear_data_offset(skb, offset, from, len) \ ++ memcpy(skb->data + offset, from, len) ++#define skb_network_header_len(skb) (skb->h.raw - skb->nh.raw) ++#define pci_register_driver pci_module_init ++#define skb_mac_header(skb) skb->mac.raw ++ ++#ifdef NETIF_F_MULTI_QUEUE ++#ifndef alloc_etherdev_mq ++#define alloc_etherdev_mq(_a, _b) alloc_etherdev(_a) ++#endif ++#endif /* NETIF_F_MULTI_QUEUE */ ++ ++#ifndef ETH_FCS_LEN ++#define ETH_FCS_LEN 4 ++#endif ++#define cancel_work_sync(x) flush_scheduled_work() ++#ifndef udp_hdr ++#define udp_hdr _udp_hdr ++static inline struct udphdr *_udp_hdr(const struct sk_buff *skb) ++{ ++ return (struct udphdr *)skb_transport_header(skb); ++} ++#endif ++#endif /* < 2.6.22 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) ) ++#undef ETHTOOL_GPERMADDR ++#undef SET_MODULE_OWNER ++#define SET_MODULE_OWNER(dev) do { } while (0) ++#endif /* > 2.6.22 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ) ++#define netif_subqueue_stopped(_a, _b) 0 ++#endif /* < 2.6.23 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ) ++/* NAPI API changes in 2.6.24 break everything */ ++struct napi_struct { ++ /* used to look up the real NAPI polling routine */ ++ int (*poll)(struct napi_struct *, int); ++ struct net_device poll_dev; ++ int weight; ++}; ++#ifdef NAPI ++extern int __kc_adapter_clean(struct net_device *, int *); ++extern struct net_device * napi_to_netdev(struct napi_struct *); ++#define napi_to_poll_dev(napi) napi_to_netdev(napi) ++#define napi_enable(napi) netif_poll_enable(adapter->netdev) ++#define napi_disable(napi) netif_poll_disable(adapter->netdev) ++#define netif_napi_add(_netdev, _napi, _poll, _weight) \ ++ do { \ ++ struct napi_struct *__napi = (_napi); \ ++ _netdev->poll = &(__kc_adapter_clean); \ ++ _netdev->weight = (_weight); \ ++ __napi->poll = &(_poll); \ ++ __napi->weight = (_weight); \ ++ netif_poll_disable(_netdev); \ ++ } while (0) ++#define netif_napi_del(_a) do {} while (0) ++#define napi_schedule_prep(napi) netif_rx_schedule_prep(napi_to_netdev(napi)) ++#define napi_schedule(napi) netif_rx_schedule(napi_to_poll_dev(napi)) ++#define __napi_schedule(napi) __netif_rx_schedule(napi_to_poll_dev(napi)) ++#define napi_complete(napi) netif_rx_complete(napi_to_poll_dev(napi)) ++#else /* NAPI */ ++#define netif_napi_add(_netdev, _napi, _poll, _weight) \ ++ do { \ ++ struct napi_struct *__napi = _napi; \ ++ _netdev->poll = &(_poll); \ ++ _netdev->weight = (_weight); \ ++ __napi->poll = &(_poll); \ ++ __napi->weight = (_weight); \ ++ } while (0) ++#define netif_napi_del(_a) do {} while (0) ++#endif /* NAPI */ ++ ++#undef dev_get_by_name ++#define dev_get_by_name(_a, _b) dev_get_by_name(_b) ++#define __netif_subqueue_stopped(_a, _b) netif_subqueue_stopped(_a, _b) ++#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) ++#else /* < 2.6.24 */ ++#define HAVE_NETDEV_NAPI_LIST ++#endif /* < 2.6.24 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,24) ) ++#include ++#endif /* > 2.6.24 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) ) ++#define PM_QOS_CPU_DMA_LATENCY 1 ++ ++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18) ) ++#include ++#define PM_QOS_DEFAULT_VALUE INFINITE_LATENCY ++#define pm_qos_add_requirement(pm_qos_class, name, value) \ ++ set_acceptable_latency(name, value) ++#define pm_qos_remove_requirement(pm_qos_class, name) \ ++ remove_acceptable_latency(name) ++#define pm_qos_update_requirement(pm_qos_class, name, value) \ ++ modify_acceptable_latency(name, value) ++#else ++#define PM_QOS_DEFAULT_VALUE -1 ++#define pm_qos_add_requirement(pm_qos_class, name, value) ++#define pm_qos_remove_requirement(pm_qos_class, name) ++#define pm_qos_update_requirement(pm_qos_class, name, value) { \ ++ if (value != PM_QOS_DEFAULT_VALUE) { \ ++ printk(KERN_WARNING "%s: unable to set PM QoS requirement\n", \ ++ pci_name(adapter->pdev)); \ ++ } \ ++} ++#endif /* > 2.6.18 */ ++ ++#define pci_enable_device_mem(pdev) pci_enable_device(pdev) ++ ++#endif /* < 2.6.25 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) ) ++#else /* < 2.6.26 */ ++#include ++#define HAVE_NETDEV_VLAN_FEATURES ++#endif /* < 2.6.26 */ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) ) ++#if (((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) && defined(CONFIG_PM)) || ((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) && defined(CONFIG_PM_SLEEP))) ++#undef device_set_wakeup_enable ++#define device_set_wakeup_enable(dev, val) \ ++ do { \ ++ u16 pmc = 0; \ ++ int pm = pci_find_capability(adapter->pdev, PCI_CAP_ID_PM); \ ++ if (pm) { \ ++ pci_read_config_word(adapter->pdev, pm + PCI_PM_PMC, \ ++ &pmc); \ ++ } \ ++ (dev)->power.can_wakeup = !!(pmc >> 11); \ ++ (dev)->power.should_wakeup = (val && (pmc >> 11)); \ ++ } while (0) ++#endif /* 2.6.15-2.6.22 and CONFIG_PM or 2.6.23-2.6.25 and CONFIG_PM_SLEEP */ ++#endif /* 2.6.15 through 2.6.27 */ ++#ifndef netif_napi_del ++#define netif_napi_del(_a) do {} while (0) ++#ifdef NAPI ++#ifdef CONFIG_NETPOLL ++#undef netif_napi_del ++#define netif_napi_del(_a) list_del(&(_a)->dev_list); ++#endif ++#endif ++#endif /* netif_napi_del */ ++#ifndef pci_dma_mapping_error ++#define pci_dma_mapping_error(pdev, dma_addr) pci_dma_mapping_error(dma_addr) ++#endif ++ ++ ++#ifdef HAVE_TX_MQ ++extern void _kc_netif_tx_stop_all_queues(struct net_device *); ++extern void _kc_netif_tx_wake_all_queues(struct net_device *); ++extern void _kc_netif_tx_start_all_queues(struct net_device *); ++#define netif_tx_stop_all_queues(a) _kc_netif_tx_stop_all_queues(a) ++#define netif_tx_wake_all_queues(a) _kc_netif_tx_wake_all_queues(a) ++#define netif_tx_start_all_queues(a) _kc_netif_tx_start_all_queues(a) ++#undef netif_stop_subqueue ++#define netif_stop_subqueue(_ndev,_qi) do { \ ++ if (netif_is_multiqueue((_ndev))) \ ++ netif_stop_subqueue((_ndev), (_qi)); \ ++ else \ ++ netif_stop_queue((_ndev)); \ ++ } while (0) ++#undef netif_start_subqueue ++#define netif_start_subqueue(_ndev,_qi) do { \ ++ if (netif_is_multiqueue((_ndev))) \ ++ netif_start_subqueue((_ndev), (_qi)); \ ++ else \ ++ netif_start_queue((_ndev)); \ ++ } while (0) ++#else /* HAVE_TX_MQ */ ++#define netif_tx_stop_all_queues(a) netif_stop_queue(a) ++#define netif_tx_wake_all_queues(a) netif_wake_queue(a) ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12) ) ++#define netif_tx_start_all_queues(a) netif_start_queue(a) ++#else ++#define netif_tx_start_all_queues(a) do {} while (0) ++#endif ++#define netif_stop_subqueue(_ndev,_qi) netif_stop_queue((_ndev)) ++#define netif_start_subqueue(_ndev,_qi) netif_start_queue((_ndev)) ++#endif /* HAVE_TX_MQ */ ++#ifndef NETIF_F_MULTI_QUEUE ++#define NETIF_F_MULTI_QUEUE 0 ++#define netif_is_multiqueue(a) 0 ++#define netif_wake_subqueue(a, b) ++#endif /* NETIF_F_MULTI_QUEUE */ ++#else /* < 2.6.27 */ ++#define HAVE_TX_MQ ++#define HAVE_NETDEV_SELECT_QUEUE ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) ++#define pci_ioremap_bar(pdev, bar) ioremap(pci_resource_start(pdev, bar), \ ++ pci_resource_len(pdev, bar)) ++#define pci_wake_from_d3 _kc_pci_wake_from_d3 ++#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep ++extern int _kc_pci_wake_from_d3(struct pci_dev *dev, bool enable); ++extern int _kc_pci_prepare_to_sleep(struct pci_dev *dev); ++#endif /* < 2.6.28 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) ) ++#define pci_request_selected_regions_exclusive(pdev, bars, name) \ ++ pci_request_selected_regions(pdev, bars, name) ++#else /* < 2.6.29 */ ++#ifdef CONFIG_DCB ++#define HAVE_PFC_MODE_ENABLE ++#endif /* CONFIG_DCB */ ++#endif /* < 2.6.29 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ) ++#ifdef IXGBE_FCOE ++#undef CONFIG_FCOE ++#undef CONFIG_FCOE_MODULE ++#endif /* IXGBE_FCOE */ ++extern u16 _kc_skb_tx_hash(struct net_device *dev, struct sk_buff *skb); ++#define skb_tx_hash(n, s) _kc_skb_tx_hash(n, s) ++#else ++#define HAVE_ASPM_QUIRKS ++#endif /* < 2.6.30 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31) ) ++#else ++#ifndef HAVE_NETDEV_STORAGE_ADDRESS ++#define HAVE_NETDEV_STORAGE_ADDRESS ++#endif ++#endif /* < 2.6.31 */ ++#endif /* _KCOMPAT_H_ */ +diff -r 5638ec0574f5 drivers/net/e1000e/kcompat_ethtool.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/e1000e/kcompat_ethtool.c Tue Sep 01 13:48:50 2009 +0100 +@@ -0,0 +1,1169 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * net/core/ethtool.c - Ethtool ioctl handler ++ * Copyright (c) 2003 Matthew Wilcox ++ * ++ * This file is where we call all the ethtool_ops commands to get ++ * the information ethtool needs. We fall back to calling do_ioctl() ++ * for drivers which haven't been converted to ethtool_ops yet. ++ * ++ * It's GPL, stupid. ++ * ++ * Modification by sfeldma@pobox.com to work as backward compat ++ * solution for pre-ethtool_ops kernels. ++ * - copied struct ethtool_ops from ethtool.h ++ * - defined SET_ETHTOOL_OPS ++ * - put in some #ifndef NETIF_F_xxx wrappers ++ * - changes refs to dev->ethtool_ops to ethtool_ops ++ * - changed dev_ethtool to ethtool_ioctl ++ * - remove EXPORT_SYMBOL()s ++ * - added _kc_ prefix in built-in ethtool_op_xxx ops. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "kcompat.h" ++ ++#undef SUPPORTED_10000baseT_Full ++#define SUPPORTED_10000baseT_Full (1 << 12) ++#undef ADVERTISED_10000baseT_Full ++#define ADVERTISED_10000baseT_Full (1 << 12) ++#undef SPEED_10000 ++#define SPEED_10000 10000 ++ ++#undef ethtool_ops ++#define ethtool_ops _kc_ethtool_ops ++ ++struct _kc_ethtool_ops { ++ int (*get_settings)(struct net_device *, struct ethtool_cmd *); ++ int (*set_settings)(struct net_device *, struct ethtool_cmd *); ++ void (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *); ++ int (*get_regs_len)(struct net_device *); ++ void (*get_regs)(struct net_device *, struct ethtool_regs *, void *); ++ void (*get_wol)(struct net_device *, struct ethtool_wolinfo *); ++ int (*set_wol)(struct net_device *, struct ethtool_wolinfo *); ++ u32 (*get_msglevel)(struct net_device *); ++ void (*set_msglevel)(struct net_device *, u32); ++ int (*nway_reset)(struct net_device *); ++ u32 (*get_link)(struct net_device *); ++ int (*get_eeprom_len)(struct net_device *); ++ int (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); ++ int (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); ++ int (*get_coalesce)(struct net_device *, struct ethtool_coalesce *); ++ int (*set_coalesce)(struct net_device *, struct ethtool_coalesce *); ++ void (*get_ringparam)(struct net_device *, struct ethtool_ringparam *); ++ int (*set_ringparam)(struct net_device *, struct ethtool_ringparam *); ++ void (*get_pauseparam)(struct net_device *, ++ struct ethtool_pauseparam*); ++ int (*set_pauseparam)(struct net_device *, ++ struct ethtool_pauseparam*); ++ u32 (*get_rx_csum)(struct net_device *); ++ int (*set_rx_csum)(struct net_device *, u32); ++ u32 (*get_tx_csum)(struct net_device *); ++ int (*set_tx_csum)(struct net_device *, u32); ++ u32 (*get_sg)(struct net_device *); ++ int (*set_sg)(struct net_device *, u32); ++ u32 (*get_tso)(struct net_device *); ++ int (*set_tso)(struct net_device *, u32); ++ int (*self_test_count)(struct net_device *); ++ void (*self_test)(struct net_device *, struct ethtool_test *, u64 *); ++ void (*get_strings)(struct net_device *, u32 stringset, u8 *); ++ int (*phys_id)(struct net_device *, u32); ++ int (*get_stats_count)(struct net_device *); ++ void (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, ++ u64 *); ++} *ethtool_ops = NULL; ++ ++#undef SET_ETHTOOL_OPS ++#define SET_ETHTOOL_OPS(netdev, ops) (ethtool_ops = (ops)) ++ ++/* ++ * Some useful ethtool_ops methods that are device independent. If we find that ++ * all drivers want to do the same thing here, we can turn these into dev_() ++ * function calls. ++ */ ++ ++#undef ethtool_op_get_link ++#define ethtool_op_get_link _kc_ethtool_op_get_link ++u32 _kc_ethtool_op_get_link(struct net_device *dev) ++{ ++ return netif_carrier_ok(dev) ? 1 : 0; ++} ++ ++#undef ethtool_op_get_tx_csum ++#define ethtool_op_get_tx_csum _kc_ethtool_op_get_tx_csum ++u32 _kc_ethtool_op_get_tx_csum(struct net_device *dev) ++{ ++#ifdef NETIF_F_IP_CSUM ++ return (dev->features & NETIF_F_IP_CSUM) != 0; ++#else ++ return 0; ++#endif ++} ++ ++#undef ethtool_op_set_tx_csum ++#define ethtool_op_set_tx_csum _kc_ethtool_op_set_tx_csum ++int _kc_ethtool_op_set_tx_csum(struct net_device *dev, u32 data) ++{ ++#ifdef NETIF_F_IP_CSUM ++ if (data) ++#ifdef NETIF_F_IPV6_CSUM ++ dev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); ++ else ++ dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); ++#else ++ dev->features |= NETIF_F_IP_CSUM; ++ else ++ dev->features &= ~NETIF_F_IP_CSUM; ++#endif ++#endif ++ ++ return 0; ++} ++ ++#undef ethtool_op_get_sg ++#define ethtool_op_get_sg _kc_ethtool_op_get_sg ++u32 _kc_ethtool_op_get_sg(struct net_device *dev) ++{ ++#ifdef NETIF_F_SG ++ return (dev->features & NETIF_F_SG) != 0; ++#else ++ return 0; ++#endif ++} ++ ++#undef ethtool_op_set_sg ++#define ethtool_op_set_sg _kc_ethtool_op_set_sg ++int _kc_ethtool_op_set_sg(struct net_device *dev, u32 data) ++{ ++#ifdef NETIF_F_SG ++ if (data) ++ dev->features |= NETIF_F_SG; ++ else ++ dev->features &= ~NETIF_F_SG; ++#endif ++ ++ return 0; ++} ++ ++#undef ethtool_op_get_tso ++#define ethtool_op_get_tso _kc_ethtool_op_get_tso ++u32 _kc_ethtool_op_get_tso(struct net_device *dev) ++{ ++#ifdef NETIF_F_TSO ++ return (dev->features & NETIF_F_TSO) != 0; ++#else ++ return 0; ++#endif ++} ++ ++#undef ethtool_op_set_tso ++#define ethtool_op_set_tso _kc_ethtool_op_set_tso ++int _kc_ethtool_op_set_tso(struct net_device *dev, u32 data) ++{ ++#ifdef NETIF_F_TSO ++ if (data) ++ dev->features |= NETIF_F_TSO; ++ else ++ dev->features &= ~NETIF_F_TSO; ++#endif ++ ++ return 0; ++} ++ ++/* Handlers for each ethtool command */ ++ ++static int ethtool_get_settings(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_cmd cmd = { ETHTOOL_GSET }; ++ int err; ++ ++ if (!ethtool_ops->get_settings) ++ return -EOPNOTSUPP; ++ ++ err = ethtool_ops->get_settings(dev, &cmd); ++ if (err < 0) ++ return err; ++ ++ if (copy_to_user(useraddr, &cmd, sizeof(cmd))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_settings(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_cmd cmd; ++ ++ if (!ethtool_ops->set_settings) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&cmd, useraddr, sizeof(cmd))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_settings(dev, &cmd); ++} ++ ++static int ethtool_get_drvinfo(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_drvinfo info; ++ struct ethtool_ops *ops = ethtool_ops; ++ ++ if (!ops->get_drvinfo) ++ return -EOPNOTSUPP; ++ ++ memset(&info, 0, sizeof(info)); ++ info.cmd = ETHTOOL_GDRVINFO; ++ ops->get_drvinfo(dev, &info); ++ ++ if (ops->self_test_count) ++ info.testinfo_len = ops->self_test_count(dev); ++ if (ops->get_stats_count) ++ info.n_stats = ops->get_stats_count(dev); ++ if (ops->get_regs_len) ++ info.regdump_len = ops->get_regs_len(dev); ++ if (ops->get_eeprom_len) ++ info.eedump_len = ops->get_eeprom_len(dev); ++ ++ if (copy_to_user(useraddr, &info, sizeof(info))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_get_regs(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_regs regs; ++ struct ethtool_ops *ops = ethtool_ops; ++ void *regbuf; ++ int reglen, ret; ++ ++ if (!ops->get_regs || !ops->get_regs_len) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(®s, useraddr, sizeof(regs))) ++ return -EFAULT; ++ ++ reglen = ops->get_regs_len(dev); ++ if (regs.len > reglen) ++ regs.len = reglen; ++ ++ regbuf = kmalloc(reglen, GFP_USER); ++ if (!regbuf) ++ return -ENOMEM; ++ ++ ops->get_regs(dev, ®s, regbuf); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, ®s, sizeof(regs))) ++ goto out; ++ useraddr += offsetof(struct ethtool_regs, data); ++ if (copy_to_user(useraddr, regbuf, reglen)) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(regbuf); ++ return ret; ++} ++ ++static int ethtool_get_wol(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_wolinfo wol = { ETHTOOL_GWOL }; ++ ++ if (!ethtool_ops->get_wol) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_wol(dev, &wol); ++ ++ if (copy_to_user(useraddr, &wol, sizeof(wol))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_wol(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_wolinfo wol; ++ ++ if (!ethtool_ops->set_wol) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&wol, useraddr, sizeof(wol))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_wol(dev, &wol); ++} ++ ++static int ethtool_get_msglevel(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GMSGLVL }; ++ ++ if (!ethtool_ops->get_msglevel) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_msglevel(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_msglevel(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_msglevel) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ ethtool_ops->set_msglevel(dev, edata.data); ++ return 0; ++} ++ ++static int ethtool_nway_reset(struct net_device *dev) ++{ ++ if (!ethtool_ops->nway_reset) ++ return -EOPNOTSUPP; ++ ++ return ethtool_ops->nway_reset(dev); ++} ++ ++static int ethtool_get_link(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ ++ if (!ethtool_ops->get_link) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_link(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_get_eeprom(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_eeprom eeprom; ++ struct ethtool_ops *ops = ethtool_ops; ++ u8 *data; ++ int ret; ++ ++ if (!ops->get_eeprom || !ops->get_eeprom_len) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) ++ return -EFAULT; ++ ++ /* Check for wrap and zero */ ++ if (eeprom.offset + eeprom.len <= eeprom.offset) ++ return -EINVAL; ++ ++ /* Check for exceeding total eeprom len */ ++ if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev)) ++ return -EINVAL; ++ ++ data = kmalloc(eeprom.len, GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ret = -EFAULT; ++ if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len)) ++ goto out; ++ ++ ret = ops->get_eeprom(dev, &eeprom, data); ++ if (ret) ++ goto out; ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &eeprom, sizeof(eeprom))) ++ goto out; ++ if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len)) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_set_eeprom(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_eeprom eeprom; ++ struct ethtool_ops *ops = ethtool_ops; ++ u8 *data; ++ int ret; ++ ++ if (!ops->set_eeprom || !ops->get_eeprom_len) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) ++ return -EFAULT; ++ ++ /* Check for wrap and zero */ ++ if (eeprom.offset + eeprom.len <= eeprom.offset) ++ return -EINVAL; ++ ++ /* Check for exceeding total eeprom len */ ++ if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev)) ++ return -EINVAL; ++ ++ data = kmalloc(eeprom.len, GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ret = -EFAULT; ++ if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len)) ++ goto out; ++ ++ ret = ops->set_eeprom(dev, &eeprom, data); ++ if (ret) ++ goto out; ++ ++ if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len)) ++ ret = -EFAULT; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_get_coalesce(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_coalesce coalesce = { ETHTOOL_GCOALESCE }; ++ ++ if (!ethtool_ops->get_coalesce) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_coalesce(dev, &coalesce); ++ ++ if (copy_to_user(useraddr, &coalesce, sizeof(coalesce))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_coalesce(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_coalesce coalesce; ++ ++ if (!ethtool_ops->get_coalesce) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&coalesce, useraddr, sizeof(coalesce))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_coalesce(dev, &coalesce); ++} ++ ++static int ethtool_get_ringparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_ringparam ringparam = { ETHTOOL_GRINGPARAM }; ++ ++ if (!ethtool_ops->get_ringparam) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_ringparam(dev, &ringparam); ++ ++ if (copy_to_user(useraddr, &ringparam, sizeof(ringparam))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_ringparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_ringparam ringparam; ++ ++ if (!ethtool_ops->get_ringparam) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&ringparam, useraddr, sizeof(ringparam))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_ringparam(dev, &ringparam); ++} ++ ++static int ethtool_get_pauseparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_pauseparam pauseparam = { ETHTOOL_GPAUSEPARAM }; ++ ++ if (!ethtool_ops->get_pauseparam) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_pauseparam(dev, &pauseparam); ++ ++ if (copy_to_user(useraddr, &pauseparam, sizeof(pauseparam))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_pauseparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_pauseparam pauseparam; ++ ++ if (!ethtool_ops->get_pauseparam) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&pauseparam, useraddr, sizeof(pauseparam))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_pauseparam(dev, &pauseparam); ++} ++ ++static int ethtool_get_rx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GRXCSUM }; ++ ++ if (!ethtool_ops->get_rx_csum) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_rx_csum(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_rx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_rx_csum) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ ethtool_ops->set_rx_csum(dev, edata.data); ++ return 0; ++} ++ ++static int ethtool_get_tx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GTXCSUM }; ++ ++ if (!ethtool_ops->get_tx_csum) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_tx_csum(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_tx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_tx_csum) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_tx_csum(dev, edata.data); ++} ++ ++static int ethtool_get_sg(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GSG }; ++ ++ if (!ethtool_ops->get_sg) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_sg(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_sg(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_sg) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_sg(dev, edata.data); ++} ++ ++static int ethtool_get_tso(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GTSO }; ++ ++ if (!ethtool_ops->get_tso) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_tso(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_tso(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_tso) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_tso(dev, edata.data); ++} ++ ++static int ethtool_self_test(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_test test; ++ struct ethtool_ops *ops = ethtool_ops; ++ u64 *data; ++ int ret; ++ ++ if (!ops->self_test || !ops->self_test_count) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&test, useraddr, sizeof(test))) ++ return -EFAULT; ++ ++ test.len = ops->self_test_count(dev); ++ data = kmalloc(test.len * sizeof(u64), GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ops->self_test(dev, &test, data); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &test, sizeof(test))) ++ goto out; ++ useraddr += sizeof(test); ++ if (copy_to_user(useraddr, data, test.len * sizeof(u64))) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_get_strings(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_gstrings gstrings; ++ struct ethtool_ops *ops = ethtool_ops; ++ u8 *data; ++ int ret; ++ ++ if (!ops->get_strings) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&gstrings, useraddr, sizeof(gstrings))) ++ return -EFAULT; ++ ++ switch (gstrings.string_set) { ++ case ETH_SS_TEST: ++ if (!ops->self_test_count) ++ return -EOPNOTSUPP; ++ gstrings.len = ops->self_test_count(dev); ++ break; ++ case ETH_SS_STATS: ++ if (!ops->get_stats_count) ++ return -EOPNOTSUPP; ++ gstrings.len = ops->get_stats_count(dev); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ data = kmalloc(gstrings.len * ETH_GSTRING_LEN, GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ops->get_strings(dev, gstrings.string_set, data); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &gstrings, sizeof(gstrings))) ++ goto out; ++ useraddr += sizeof(gstrings); ++ if (copy_to_user(useraddr, data, gstrings.len * ETH_GSTRING_LEN)) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_phys_id(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_value id; ++ ++ if (!ethtool_ops->phys_id) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&id, useraddr, sizeof(id))) ++ return -EFAULT; ++ ++ return ethtool_ops->phys_id(dev, id.data); ++} ++ ++static int ethtool_get_stats(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_stats stats; ++ struct ethtool_ops *ops = ethtool_ops; ++ u64 *data; ++ int ret; ++ ++ if (!ops->get_ethtool_stats || !ops->get_stats_count) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&stats, useraddr, sizeof(stats))) ++ return -EFAULT; ++ ++ stats.n_stats = ops->get_stats_count(dev); ++ data = kmalloc(stats.n_stats * sizeof(u64), GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ops->get_ethtool_stats(dev, &stats, data); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &stats, sizeof(stats))) ++ goto out; ++ useraddr += sizeof(stats); ++ if (copy_to_user(useraddr, data, stats.n_stats * sizeof(u64))) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++/* The main entry point in this file. Called from net/core/dev.c */ ++ ++#define ETHTOOL_OPS_COMPAT ++int ethtool_ioctl(struct ifreq *ifr) ++{ ++ struct net_device *dev = __dev_get_by_name(ifr->ifr_name); ++ void *useraddr = (void *) ifr->ifr_data; ++ u32 ethcmd; ++ ++ /* ++ * XXX: This can be pushed down into the ethtool_* handlers that ++ * need it. Keep existing behavior for the moment. ++ */ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++ if (!dev || !netif_device_present(dev)) ++ return -ENODEV; ++ ++ if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd))) ++ return -EFAULT; ++ ++ switch (ethcmd) { ++ case ETHTOOL_GSET: ++ return ethtool_get_settings(dev, useraddr); ++ case ETHTOOL_SSET: ++ return ethtool_set_settings(dev, useraddr); ++ case ETHTOOL_GDRVINFO: ++ return ethtool_get_drvinfo(dev, useraddr); ++ case ETHTOOL_GREGS: ++ return ethtool_get_regs(dev, useraddr); ++ case ETHTOOL_GWOL: ++ return ethtool_get_wol(dev, useraddr); ++ case ETHTOOL_SWOL: ++ return ethtool_set_wol(dev, useraddr); ++ case ETHTOOL_GMSGLVL: ++ return ethtool_get_msglevel(dev, useraddr); ++ case ETHTOOL_SMSGLVL: ++ return ethtool_set_msglevel(dev, useraddr); ++ case ETHTOOL_NWAY_RST: ++ return ethtool_nway_reset(dev); ++ case ETHTOOL_GLINK: ++ return ethtool_get_link(dev, useraddr); ++ case ETHTOOL_GEEPROM: ++ return ethtool_get_eeprom(dev, useraddr); ++ case ETHTOOL_SEEPROM: ++ return ethtool_set_eeprom(dev, useraddr); ++ case ETHTOOL_GCOALESCE: ++ return ethtool_get_coalesce(dev, useraddr); ++ case ETHTOOL_SCOALESCE: ++ return ethtool_set_coalesce(dev, useraddr); ++ case ETHTOOL_GRINGPARAM: ++ return ethtool_get_ringparam(dev, useraddr); ++ case ETHTOOL_SRINGPARAM: ++ return ethtool_set_ringparam(dev, useraddr); ++ case ETHTOOL_GPAUSEPARAM: ++ return ethtool_get_pauseparam(dev, useraddr); ++ case ETHTOOL_SPAUSEPARAM: ++ return ethtool_set_pauseparam(dev, useraddr); ++ case ETHTOOL_GRXCSUM: ++ return ethtool_get_rx_csum(dev, useraddr); ++ case ETHTOOL_SRXCSUM: ++ return ethtool_set_rx_csum(dev, useraddr); ++ case ETHTOOL_GTXCSUM: ++ return ethtool_get_tx_csum(dev, useraddr); ++ case ETHTOOL_STXCSUM: ++ return ethtool_set_tx_csum(dev, useraddr); ++ case ETHTOOL_GSG: ++ return ethtool_get_sg(dev, useraddr); ++ case ETHTOOL_SSG: ++ return ethtool_set_sg(dev, useraddr); ++ case ETHTOOL_GTSO: ++ return ethtool_get_tso(dev, useraddr); ++ case ETHTOOL_STSO: ++ return ethtool_set_tso(dev, useraddr); ++ case ETHTOOL_TEST: ++ return ethtool_self_test(dev, useraddr); ++ case ETHTOOL_GSTRINGS: ++ return ethtool_get_strings(dev, useraddr); ++ case ETHTOOL_PHYS_ID: ++ return ethtool_phys_id(dev, useraddr); ++ case ETHTOOL_GSTATS: ++ return ethtool_get_stats(dev, useraddr); ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return -EOPNOTSUPP; ++} ++ ++#define mii_if_info _kc_mii_if_info ++struct _kc_mii_if_info { ++ int phy_id; ++ int advertising; ++ int phy_id_mask; ++ int reg_num_mask; ++ ++ unsigned int full_duplex : 1; /* is full duplex? */ ++ unsigned int force_media : 1; /* is autoneg. disabled? */ ++ ++ struct net_device *dev; ++ int (*mdio_read) (struct net_device *dev, int phy_id, int location); ++ void (*mdio_write) (struct net_device *dev, int phy_id, int location, int val); ++}; ++ ++struct ethtool_cmd; ++struct mii_ioctl_data; ++ ++#undef mii_link_ok ++#define mii_link_ok _kc_mii_link_ok ++#undef mii_nway_restart ++#define mii_nway_restart _kc_mii_nway_restart ++#undef mii_ethtool_gset ++#define mii_ethtool_gset _kc_mii_ethtool_gset ++#undef mii_ethtool_sset ++#define mii_ethtool_sset _kc_mii_ethtool_sset ++#undef mii_check_link ++#define mii_check_link _kc_mii_check_link ++#undef generic_mii_ioctl ++#define generic_mii_ioctl _kc_generic_mii_ioctl ++extern int _kc_mii_link_ok (struct mii_if_info *mii); ++extern int _kc_mii_nway_restart (struct mii_if_info *mii); ++extern int _kc_mii_ethtool_gset(struct mii_if_info *mii, ++ struct ethtool_cmd *ecmd); ++extern int _kc_mii_ethtool_sset(struct mii_if_info *mii, ++ struct ethtool_cmd *ecmd); ++extern void _kc_mii_check_link (struct mii_if_info *mii); ++extern int _kc_generic_mii_ioctl(struct mii_if_info *mii_if, ++ struct mii_ioctl_data *mii_data, int cmd, ++ unsigned int *duplex_changed); ++ ++ ++struct _kc_pci_dev_ext { ++ struct pci_dev *dev; ++ void *pci_drvdata; ++ struct pci_driver *driver; ++}; ++ ++struct _kc_net_dev_ext { ++ struct net_device *dev; ++ unsigned int carrier; ++}; ++ ++ ++/**************************************/ ++/* mii support */ ++ ++int _kc_mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) ++{ ++ struct net_device *dev = mii->dev; ++ u32 advert, bmcr, lpa, nego; ++ ++ ecmd->supported = ++ (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | ++ SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | ++ SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII); ++ ++ /* only supports twisted-pair */ ++ ecmd->port = PORT_MII; ++ ++ /* only supports internal transceiver */ ++ ecmd->transceiver = XCVR_INTERNAL; ++ ++ /* this isn't fully supported at higher layers */ ++ ecmd->phy_address = mii->phy_id; ++ ++ ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII; ++ advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE); ++ if (advert & ADVERTISE_10HALF) ++ ecmd->advertising |= ADVERTISED_10baseT_Half; ++ if (advert & ADVERTISE_10FULL) ++ ecmd->advertising |= ADVERTISED_10baseT_Full; ++ if (advert & ADVERTISE_100HALF) ++ ecmd->advertising |= ADVERTISED_100baseT_Half; ++ if (advert & ADVERTISE_100FULL) ++ ecmd->advertising |= ADVERTISED_100baseT_Full; ++ ++ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); ++ lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA); ++ if (bmcr & BMCR_ANENABLE) { ++ ecmd->advertising |= ADVERTISED_Autoneg; ++ ecmd->autoneg = AUTONEG_ENABLE; ++ ++ nego = mii_nway_result(advert & lpa); ++ if (nego == LPA_100FULL || nego == LPA_100HALF) ++ ecmd->speed = SPEED_100; ++ else ++ ecmd->speed = SPEED_10; ++ if (nego == LPA_100FULL || nego == LPA_10FULL) { ++ ecmd->duplex = DUPLEX_FULL; ++ mii->full_duplex = 1; ++ } else { ++ ecmd->duplex = DUPLEX_HALF; ++ mii->full_duplex = 0; ++ } ++ } else { ++ ecmd->autoneg = AUTONEG_DISABLE; ++ ++ ecmd->speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; ++ ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; ++ } ++ ++ /* ignore maxtxpkt, maxrxpkt for now */ ++ ++ return 0; ++} ++ ++int _kc_mii_ethtool_sset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) ++{ ++ struct net_device *dev = mii->dev; ++ ++ if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) ++ return -EINVAL; ++ if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) ++ return -EINVAL; ++ if (ecmd->port != PORT_MII) ++ return -EINVAL; ++ if (ecmd->transceiver != XCVR_INTERNAL) ++ return -EINVAL; ++ if (ecmd->phy_address != mii->phy_id) ++ return -EINVAL; ++ if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE) ++ return -EINVAL; ++ ++ /* ignore supported, maxtxpkt, maxrxpkt */ ++ ++ if (ecmd->autoneg == AUTONEG_ENABLE) { ++ u32 bmcr, advert, tmp; ++ ++ if ((ecmd->advertising & (ADVERTISED_10baseT_Half | ++ ADVERTISED_10baseT_Full | ++ ADVERTISED_100baseT_Half | ++ ADVERTISED_100baseT_Full)) == 0) ++ return -EINVAL; ++ ++ /* advertise only what has been requested */ ++ advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE); ++ tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4); ++ if (ADVERTISED_10baseT_Half) ++ tmp |= ADVERTISE_10HALF; ++ if (ADVERTISED_10baseT_Full) ++ tmp |= ADVERTISE_10FULL; ++ if (ADVERTISED_100baseT_Half) ++ tmp |= ADVERTISE_100HALF; ++ if (ADVERTISED_100baseT_Full) ++ tmp |= ADVERTISE_100FULL; ++ if (advert != tmp) { ++ mii->mdio_write(dev, mii->phy_id, MII_ADVERTISE, tmp); ++ mii->advertising = tmp; ++ } ++ ++ /* turn on autonegotiation, and force a renegotiate */ ++ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); ++ bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); ++ mii->mdio_write(dev, mii->phy_id, MII_BMCR, bmcr); ++ ++ mii->force_media = 0; ++ } else { ++ u32 bmcr, tmp; ++ ++ /* turn off auto negotiation, set speed and duplexity */ ++ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); ++ tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX); ++ if (ecmd->speed == SPEED_100) ++ tmp |= BMCR_SPEED100; ++ if (ecmd->duplex == DUPLEX_FULL) { ++ tmp |= BMCR_FULLDPLX; ++ mii->full_duplex = 1; ++ } else ++ mii->full_duplex = 0; ++ if (bmcr != tmp) ++ mii->mdio_write(dev, mii->phy_id, MII_BMCR, tmp); ++ ++ mii->force_media = 1; ++ } ++ return 0; ++} ++ ++int _kc_mii_link_ok (struct mii_if_info *mii) ++{ ++ /* first, a dummy read, needed to latch some MII phys */ ++ mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); ++ if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS) ++ return 1; ++ return 0; ++} ++ ++int _kc_mii_nway_restart (struct mii_if_info *mii) ++{ ++ int bmcr; ++ int r = -EINVAL; ++ ++ /* if autoneg is off, it's an error */ ++ bmcr = mii->mdio_read(mii->dev, mii->phy_id, MII_BMCR); ++ ++ if (bmcr & BMCR_ANENABLE) { ++ bmcr |= BMCR_ANRESTART; ++ mii->mdio_write(mii->dev, mii->phy_id, MII_BMCR, bmcr); ++ r = 0; ++ } ++ ++ return r; ++} ++ ++void _kc_mii_check_link (struct mii_if_info *mii) ++{ ++ int cur_link = mii_link_ok(mii); ++ int prev_link = netif_carrier_ok(mii->dev); ++ ++ if (cur_link && !prev_link) ++ netif_carrier_on(mii->dev); ++ else if (prev_link && !cur_link) ++ netif_carrier_off(mii->dev); ++} ++ ++int _kc_generic_mii_ioctl(struct mii_if_info *mii_if, ++ struct mii_ioctl_data *mii_data, int cmd, ++ unsigned int *duplex_chg_out) ++{ ++ int rc = 0; ++ unsigned int duplex_changed = 0; ++ ++ if (duplex_chg_out) ++ *duplex_chg_out = 0; ++ ++ mii_data->phy_id &= mii_if->phy_id_mask; ++ mii_data->reg_num &= mii_if->reg_num_mask; ++ ++ switch(cmd) { ++ case SIOCDEVPRIVATE: /* binary compat, remove in 2.5 */ ++ case SIOCGMIIPHY: ++ mii_data->phy_id = mii_if->phy_id; ++ /* fall through */ ++ ++ case SIOCDEVPRIVATE + 1:/* binary compat, remove in 2.5 */ ++ case SIOCGMIIREG: ++ mii_data->val_out = ++ mii_if->mdio_read(mii_if->dev, mii_data->phy_id, ++ mii_data->reg_num); ++ break; ++ ++ case SIOCDEVPRIVATE + 2:/* binary compat, remove in 2.5 */ ++ case SIOCSMIIREG: { ++ u16 val = mii_data->val_in; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++ if (mii_data->phy_id == mii_if->phy_id) { ++ switch(mii_data->reg_num) { ++ case MII_BMCR: { ++ unsigned int new_duplex = 0; ++ if (val & (BMCR_RESET|BMCR_ANENABLE)) ++ mii_if->force_media = 0; ++ else ++ mii_if->force_media = 1; ++ if (mii_if->force_media && ++ (val & BMCR_FULLDPLX)) ++ new_duplex = 1; ++ if (mii_if->full_duplex != new_duplex) { ++ duplex_changed = 1; ++ mii_if->full_duplex = new_duplex; ++ } ++ break; ++ } ++ case MII_ADVERTISE: ++ mii_if->advertising = val; ++ break; ++ default: ++ /* do nothing */ ++ break; ++ } ++ } ++ ++ mii_if->mdio_write(mii_if->dev, mii_data->phy_id, ++ mii_data->reg_num, val); ++ break; ++ } ++ ++ default: ++ rc = -EOPNOTSUPP; ++ break; ++ } ++ ++ if ((rc == 0) && (duplex_chg_out) && (duplex_changed)) ++ *duplex_chg_out = 1; ++ ++ return rc; ++} ++ +diff -r 5638ec0574f5 drivers/net/e1000e/netdev.c +--- a/drivers/net/e1000e/netdev.c Tue Sep 01 13:47:57 2009 +0100 ++++ b/drivers/net/e1000e/netdev.c Tue Sep 01 13:48:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel PRO/1000 Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -36,42 +36,284 @@ + #include + #include + #include ++#ifdef NETIF_F_TSO + #include ++#ifdef NETIF_F_TSO6 + #include ++#endif ++#endif + #include + #include + #include +-#include +-#include +-#include + + #include "e1000.h" + +-#define DRV_VERSION "0.3.3.3-k6" ++#ifdef CONFIG_E1000E_NAPI ++#define DRV_EXTRAVERSION "-NAPI" ++#else ++#define DRV_EXTRAVERSION ++#endif ++ ++#define DRV_VERSION "1.0.2.5" DRV_EXTRAVERSION + char e1000e_driver_name[] = "e1000e"; + const char e1000e_driver_version[] = DRV_VERSION; ++ ++static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ static int global_quad_port_a; /* global port a indication */ ++ struct pci_dev *pdev = adapter->pdev; ++ u16 eeprom_data = 0; ++ int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; ++ ++ /* tag quad port adapters first, it's used below */ ++ switch (pdev->device) { ++ case E1000_DEV_ID_82571EB_QUAD_COPPER: ++ case E1000_DEV_ID_82571EB_QUAD_FIBER: ++ case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: ++ case E1000_DEV_ID_82571PT_QUAD_COPPER: ++ adapter->flags |= FLAG_IS_QUAD_PORT; ++ /* mark the first port */ ++ if (global_quad_port_a == 0) ++ adapter->flags |= FLAG_IS_QUAD_PORT_A; ++ /* Reset for multiple quad port adapters */ ++ global_quad_port_a++; ++ if (global_quad_port_a == 4) ++ global_quad_port_a = 0; ++ break; ++ default: ++ break; ++ } ++ ++ switch (adapter->hw.mac.type) { ++ case e1000_82571: ++ /* these dual ports don't have WoL on port B at all */ ++ if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || ++ (pdev->device == E1000_DEV_ID_82571EB_SERDES) || ++ (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && ++ (is_port_b)) ++ adapter->flags &= ~FLAG_HAS_WOL; ++ /* quad ports only support WoL on port A */ ++ if (adapter->flags & FLAG_IS_QUAD_PORT && ++ (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) ++ adapter->flags &= ~FLAG_HAS_WOL; ++ /* Does not support WoL on any port */ ++ if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) ++ adapter->flags &= ~FLAG_HAS_WOL; ++ break; ++ ++ case e1000_82573: ++ if (pdev->device == E1000_DEV_ID_82573L) { ++ if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1, ++ &eeprom_data) < 0) ++ break; ++ if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) { ++ adapter->flags |= FLAG_HAS_JUMBO_FRAMES; ++ adapter->max_hw_frame_size = DEFAULT_JUMBO; ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static struct e1000_info e1000_82571_info = { ++ .mac = e1000_82571, ++ .flags = FLAG_HAS_HW_VLAN_FILTER ++ | FLAG_HAS_JUMBO_FRAMES ++ | FLAG_HAS_WOL ++ | FLAG_APME_IN_CTRL3 ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_CTRLEXT_ON_LOAD ++ | FLAG_HAS_SMART_POWER_DOWN ++ | FLAG_RESET_OVERWRITES_LAA /* errata */ ++ | FLAG_TARC_SPEED_MODE_BIT /* errata */ ++ | FLAG_APME_CHECK_PORT_B, ++ .pba = 38, ++ .max_hw_frame_size = DEFAULT_JUMBO, ++ .init_ops = e1000_init_function_pointers_82571, ++ .get_variants = e1000_get_variants_82571, ++}; ++ ++static struct e1000_info e1000_82572_info = { ++ .mac = e1000_82572, ++ .flags = FLAG_HAS_HW_VLAN_FILTER ++ | FLAG_HAS_JUMBO_FRAMES ++ | FLAG_HAS_WOL ++ | FLAG_APME_IN_CTRL3 ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_CTRLEXT_ON_LOAD ++ | FLAG_TARC_SPEED_MODE_BIT, /* errata */ ++ .pba = 38, ++ .max_hw_frame_size = DEFAULT_JUMBO, ++ .init_ops = e1000_init_function_pointers_82571, ++ .get_variants = e1000_get_variants_82571, ++}; ++ ++static struct e1000_info e1000_82573_info = { ++ .mac = e1000_82573, ++ .flags = FLAG_HAS_HW_VLAN_FILTER ++ | FLAG_HAS_WOL ++ | FLAG_APME_IN_CTRL3 ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_SMART_POWER_DOWN ++ | FLAG_HAS_AMT ++ | FLAG_HAS_ERT ++ | FLAG_HAS_SWSM_ON_LOAD, ++ .pba = 20, ++ .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, ++ .init_ops = e1000_init_function_pointers_82571, ++ .get_variants = e1000_get_variants_82571, ++}; ++ ++static struct e1000_info e1000_82574_info = { ++ .mac = e1000_82574, ++ .flags = FLAG_HAS_HW_VLAN_FILTER ++#ifdef CONFIG_E1000E_MSIX ++ | FLAG_HAS_MSIX ++#endif ++ | FLAG_HAS_JUMBO_FRAMES ++ | FLAG_HAS_WOL ++ | FLAG_APME_IN_CTRL3 ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_SMART_POWER_DOWN ++ | FLAG_HAS_AMT ++ | FLAG_HAS_CTRLEXT_ON_LOAD, ++ .pba = 20, ++ .max_hw_frame_size = DEFAULT_JUMBO, ++ .init_ops = e1000_init_function_pointers_82571, ++ .get_variants = e1000_get_variants_82571, ++}; ++ ++static struct e1000_info e1000_82583_info = { ++ .mac = e1000_82583, ++ .flags = FLAG_HAS_HW_VLAN_FILTER ++ | FLAG_HAS_WOL ++ | FLAG_APME_IN_CTRL3 ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_SMART_POWER_DOWN ++ | FLAG_HAS_AMT ++ | FLAG_HAS_CTRLEXT_ON_LOAD, ++ .pba = 20, ++ .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, ++ .init_ops = e1000_init_function_pointers_82571, ++ .get_variants = e1000_get_variants_82571, ++}; ++ ++static struct e1000_info e1000_es2_info = { ++ .mac = e1000_80003es2lan, ++ .flags = FLAG_HAS_HW_VLAN_FILTER ++ | FLAG_HAS_JUMBO_FRAMES ++ | FLAG_HAS_WOL ++ | FLAG_APME_IN_CTRL3 ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_CTRLEXT_ON_LOAD ++ | FLAG_RX_NEEDS_RESTART /* errata */ ++ | FLAG_TARC_SET_BIT_ZERO /* errata */ ++ | FLAG_APME_CHECK_PORT_B ++ | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ ++ | FLAG_TIPG_MEDIUM_FOR_80003ESLAN, ++ .pba = 38, ++ .max_hw_frame_size = DEFAULT_JUMBO, ++ .init_ops = e1000_init_function_pointers_80003es2lan, ++ .get_variants = NULL, ++}; ++ ++static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) ++{ ++ if (adapter->hw.phy.type == e1000_phy_ife) { ++ adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; ++ adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN; ++ } ++ ++ if ((adapter->hw.mac.type == e1000_ich8lan) && ++ (adapter->hw.phy.type == e1000_phy_igp_3)) ++ adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; ++ ++ return 0; ++} ++ ++static struct e1000_info e1000_ich8_info = { ++ .mac = e1000_ich8lan, ++ .flags = FLAG_HAS_WOL ++ | FLAG_IS_ICH ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_CTRLEXT_ON_LOAD ++ | FLAG_HAS_AMT ++ | FLAG_HAS_FLASH ++ | FLAG_APME_IN_WUC, ++ .pba = 8, ++ .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, ++ .init_ops = e1000_init_function_pointers_ich8lan, ++ .get_variants = e1000_get_variants_ich8lan, ++}; ++ ++static struct e1000_info e1000_ich9_info = { ++ .mac = e1000_ich9lan, ++ .flags = FLAG_HAS_JUMBO_FRAMES ++ | FLAG_IS_ICH ++ | FLAG_HAS_WOL ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_CTRLEXT_ON_LOAD ++ | FLAG_HAS_AMT ++ | FLAG_HAS_ERT ++ | FLAG_HAS_FLASH ++ | FLAG_APME_IN_WUC, ++ .pba = 10, ++ .max_hw_frame_size = DEFAULT_JUMBO, ++ .init_ops = e1000_init_function_pointers_ich8lan, ++ .get_variants = e1000_get_variants_ich8lan, ++}; ++ ++static struct e1000_info e1000_ich10_info = { ++ .mac = e1000_ich10lan, ++ .flags = FLAG_HAS_JUMBO_FRAMES ++ | FLAG_IS_ICH ++ | FLAG_HAS_WOL ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_CTRLEXT_ON_LOAD ++ | FLAG_HAS_AMT ++ | FLAG_HAS_ERT ++ | FLAG_HAS_FLASH ++ | FLAG_APME_IN_WUC, ++ .pba = 10, ++ .max_hw_frame_size = DEFAULT_JUMBO, ++ .init_ops = e1000_init_function_pointers_ich8lan, ++ .get_variants = e1000_get_variants_ich8lan, ++}; ++ ++static struct e1000_info e1000_pch_info = { ++ .mac = e1000_pchlan, ++ .flags = FLAG_IS_ICH ++ | FLAG_HAS_WOL ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_CTRLEXT_ON_LOAD ++ | FLAG_HAS_AMT ++ | FLAG_HAS_FLASH ++ | FLAG_HAS_JUMBO_FRAMES ++ | FLAG_APME_IN_WUC, ++ .pba = 26, ++ .max_hw_frame_size = 4096, ++ .init_ops = e1000_init_function_pointers_ich8lan, ++ .get_variants = e1000_get_variants_ich8lan, ++}; + + static const struct e1000_info *e1000_info_tbl[] = { + [board_82571] = &e1000_82571_info, + [board_82572] = &e1000_82572_info, + [board_82573] = &e1000_82573_info, + [board_82574] = &e1000_82574_info, ++ [board_82583] = &e1000_82583_info, + [board_80003es2lan] = &e1000_es2_info, + [board_ich8lan] = &e1000_ich8_info, + [board_ich9lan] = &e1000_ich9_info, + [board_ich10lan] = &e1000_ich10_info, +-}; +- +-#ifdef DEBUG +-/** +- * e1000_get_hw_dev_name - return device name string +- * used by hardware layer to print debugging information +- **/ +-char *e1000e_get_hw_dev_name(struct e1000_hw *hw) +-{ +- return hw->adapter->netdev->name; +-} +-#endif ++ [board_pchlan] = &e1000_pch_info, ++}; + + /** + * e1000_desc_unused - calculate if we have unused descriptors +@@ -96,15 +338,34 @@ + struct sk_buff *skb, + u8 status, __le16 vlan) + { ++#ifndef CONFIG_E1000E_NAPI ++ int ret; ++ ++#endif + skb->protocol = eth_type_trans(skb, netdev); + ++#ifdef CONFIG_E1000E_NAPI + if (adapter->vlgrp && (status & E1000_RXD_STAT_VP)) + vlan_hwaccel_receive_skb(skb, adapter->vlgrp, + le16_to_cpu(vlan)); + else ++#ifdef NETIF_F_GRO ++ napi_gro_receive(&adapter->napi, skb); ++#else + netif_receive_skb(skb); ++#endif /* NETIF_F_GRO */ ++#else ++ if (adapter->vlgrp && (status & E1000_RXD_STAT_VP)) ++ ret = vlan_hwaccel_rx(skb, adapter->vlgrp, le16_to_cpu(vlan)); ++ else ++ ret = netif_rx(skb); ++ if (unlikely(ret == NET_RX_DROP)) ++ adapter->rx_dropped_backlog++; ++#endif ++#ifndef NETIF_F_GRO + + netdev->last_rx = jiffies; ++#endif + } + + /** +@@ -145,8 +406,8 @@ + * Hardware complements the payload checksum, so we undo it + * and then put the value in host order for further stack use. + */ +- __sum16 sum = (__force __sum16)htons(csum); +- skb->csum = csum_unfold(~sum); ++ csum = ntohl(csum ^ 0xFFFF); ++ skb->csum = csum; + skb->ip_summed = CHECKSUM_COMPLETE; + } + adapter->hw_csum_good++; +@@ -258,7 +519,7 @@ + continue; + } + if (!ps_page->page) { +- ps_page->page = netdev_alloc_page(netdev); ++ ps_page->page = alloc_page(GFP_ATOMIC); + if (!ps_page->page) { + adapter->alloc_rx_buff_failed++; + goto no_buffers; +@@ -342,10 +603,10 @@ + } + } + ++#ifdef CONFIG_E1000E_NAPI + /** + * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers + * @adapter: address of board private structure +- * @rx_ring: pointer to receive ring structure + * @cleaned_count: number of buffers to allocate this pass + **/ + +@@ -424,6 +685,7 @@ + writel(i, adapter->hw.hw_addr + rx_ring->tail); + } + } ++#endif /* CONFIG_E1000E_NAPI */ + + /** + * e1000_clean_rx_irq - Send received data up the network stack; legacy +@@ -432,11 +694,16 @@ + * the return value indicates whether actual cleaning was done, there + * is no guarantee that everything was cleaned + **/ ++#ifdef CONFIG_E1000E_NAPI + static bool e1000_clean_rx_irq(struct e1000_adapter *adapter, + int *work_done, int work_to_do) +-{ +- struct net_device *netdev = adapter->netdev; +- struct pci_dev *pdev = adapter->pdev; ++#else ++static bool e1000_clean_rx_irq(struct e1000_adapter *adapter) ++#endif ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct pci_dev *pdev = adapter->pdev; ++ struct e1000_hw *hw = &adapter->hw; + struct e1000_ring *rx_ring = adapter->rx_ring; + struct e1000_rx_desc *rx_desc, *next_rxd; + struct e1000_buffer *buffer_info, *next_buffer; +@@ -454,9 +721,11 @@ + struct sk_buff *skb; + u8 status; + ++#ifdef CONFIG_E1000E_NAPI + if (*work_done >= work_to_do) + break; + (*work_done)++; ++#endif + + status = rx_desc->status; + skb = buffer_info->skb; +@@ -486,8 +755,7 @@ + * packet, also make sure the frame isn't just CRC only */ + if (!(status & E1000_RXD_STAT_EOP) || (length <= 4)) { + /* All receives must fit into a single buffer */ +- e_dbg("%s: Receive packet consumed multiple buffers\n", +- netdev->name); ++ e_dbg("Receive packet consumed multiple buffers\n"); + /* recycle */ + buffer_info->skb = skb; + goto next_desc; +@@ -537,7 +805,7 @@ + ((u32)(rx_desc->errors) << 24), + le16_to_cpu(rx_desc->csum), skb); + +- e1000_receive_skb(adapter, netdev, skb,status,rx_desc->special); ++ e1000_receive_skb(adapter, netdev, skb, status, rx_desc->special); + + next_desc: + rx_desc->status = 0; +@@ -611,8 +879,7 @@ + * e1000_clean_tx_irq - Reclaim resources after transmit completes + * @adapter: board private structure + * +- * the return value indicates whether actual cleaning was done, there +- * is no guarantee that everything was cleaned ++ * the return value indicates if there is more work to do (later) + **/ + static bool e1000_clean_tx_irq(struct e1000_adapter *adapter) + { +@@ -622,8 +889,7 @@ + struct e1000_tx_desc *tx_desc, *eop_desc; + struct e1000_buffer *buffer_info; + unsigned int i, eop; +- unsigned int count = 0; +- bool cleaned = 0; ++ bool cleaned = 0, retval = 1; + unsigned int total_tx_bytes = 0, total_tx_packets = 0; + + i = tx_ring->next_to_clean; +@@ -638,6 +904,7 @@ + + if (cleaned) { + struct sk_buff *skb = buffer_info->skb; ++#ifdef NETIF_F_TSO + unsigned int segs, bytecount; + segs = skb_shinfo(skb)->gso_segs ?: 1; + /* multiply data chunks by size of headers */ +@@ -645,6 +912,10 @@ + skb->len; + total_tx_packets += segs; + total_tx_bytes += bytecount; ++#else ++ total_tx_packets++; ++ total_tx_bytes += skb->len; ++#endif + } + + e1000_put_txbuf(adapter, buffer_info); +@@ -653,16 +924,21 @@ + i++; + if (i == tx_ring->count) + i = 0; ++#ifdef CONFIG_E1000E_NAPI ++ if (total_tx_packets >= tx_ring->count) { ++ retval = 0; ++ goto done_cleaning; ++ } ++#endif + } + + eop = tx_ring->buffer_info[i].next_to_watch; + eop_desc = E1000_TX_DESC(*tx_ring, eop); +-#define E1000_TX_WEIGHT 64 +- /* weight of a sort for tx, to avoid endless transmit cleanup */ +- if (count++ == E1000_TX_WEIGHT) +- break; +- } +- ++ } ++ ++#ifdef CONFIG_E1000E_NAPI ++done_cleaning: ++#endif + tx_ring->next_to_clean = i; + + #define TX_WAKE_THRESHOLD 32 +@@ -698,7 +974,7 @@ + adapter->total_tx_packets += total_tx_packets; + adapter->net_stats.tx_bytes += total_tx_bytes; + adapter->net_stats.tx_packets += total_tx_packets; +- return cleaned; ++ return retval; + } + + /** +@@ -708,9 +984,14 @@ + * the return value indicates whether actual cleaning was done, there + * is no guarantee that everything was cleaned + **/ ++#ifdef CONFIG_E1000E_NAPI + static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter, + int *work_done, int work_to_do) +-{ ++#else ++static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter) ++#endif ++{ ++ struct e1000_hw *hw = &adapter->hw; + union e1000_rx_desc_packet_split *rx_desc, *next_rxd; + struct net_device *netdev = adapter->netdev; + struct pci_dev *pdev = adapter->pdev; +@@ -730,9 +1011,11 @@ + buffer_info = &rx_ring->buffer_info[i]; + + while (staterr & E1000_RXD_STAT_DD) { ++#ifdef CONFIG_E1000E_NAPI + if (*work_done >= work_to_do) + break; + (*work_done)++; ++#endif + skb = buffer_info->skb; + + /* in the packet split case this is header only */ +@@ -754,8 +1037,8 @@ + buffer_info->dma = 0; + + if (!(staterr & E1000_RXD_STAT_EOP)) { +- e_dbg("%s: Packet Split buffers didn't pick up the " +- "full packet\n", netdev->name); ++ e_dbg("Packet Split buffers didn't pick up the full " ++ "packet\n"); + dev_kfree_skb_irq(skb); + goto next_desc; + } +@@ -768,8 +1051,8 @@ + length = le16_to_cpu(rx_desc->wb.middle.length0); + + if (!length) { +- e_dbg("%s: Last part of the packet spanning multiple " +- "descriptors\n", netdev->name); ++ e_dbg("Last part of the packet spanning multiple " ++ "descriptors\n"); + dev_kfree_skb_irq(skb); + goto next_desc; + } +@@ -777,6 +1060,7 @@ + /* Good Receive */ + skb_put(skb, length); + ++#ifdef CONFIG_E1000E_NAPI + { + /* + * this looks ugly, but it seems compiler issues make it +@@ -816,6 +1100,7 @@ + goto copydone; + } /* if */ + } ++#endif + + for (j = 0; j < PS_PAGE_BUFFERS; j++) { + length = le16_to_cpu(rx_desc->wb.upper.length[j]); +@@ -826,17 +1111,21 @@ + pci_unmap_page(pdev, ps_page->dma, PAGE_SIZE, + PCI_DMA_FROMDEVICE); + ps_page->dma = 0; +- skb_add_rx_frag(skb, j, ps_page->page, 0, length); ++ skb_fill_page_desc(skb, j, ps_page->page, 0, length); + ps_page->page = NULL; ++ skb->len += length; ++ skb->data_len += length; ++ skb->truesize += length; + } + + /* strip the ethernet crc, problem is we're using pages now so +- * this whole operation can get a little cpu intensive +- */ ++ * this whole operation can get a little cpu intensive */ + if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) + pskb_trim(skb, skb->len - 4); + ++#ifdef CONFIG_E1000E_NAPI + copydone: ++#endif + total_rx_bytes += skb->len; + total_rx_packets++; + +@@ -879,6 +1168,7 @@ + return cleaned; + } + ++#ifdef CONFIG_E1000E_NAPI + /** + * e1000_consume_page - helper function + **/ +@@ -911,7 +1201,7 @@ + unsigned int i; + int cleaned_count = 0; + bool cleaned = false; +- unsigned int total_rx_bytes=0, total_rx_packets=0; ++ unsigned int total_rx_bytes = 0, total_rx_packets = 0; + + i = rx_ring->next_to_clean; + rx_desc = E1000_RX_DESC(*rx_ring, i); +@@ -958,7 +1248,7 @@ + goto next_desc; + } + +-#define rxtop rx_ring->rx_skb_top ++#define rxtop (rx_ring->rx_skb_top) + if (!(status & E1000_RXD_STAT_EOP)) { + /* this descriptor is only the beginning (or middle) */ + if (!rxtop) { +@@ -1059,6 +1349,7 @@ + return cleaned; + } + ++#endif /* CONFIG_E1000E_NAPI */ + /** + * e1000_clean_rx_ring - Free Rx Buffers per Queue + * @adapter: board private structure +@@ -1079,10 +1370,12 @@ + pci_unmap_single(pdev, buffer_info->dma, + adapter->rx_buffer_len, + PCI_DMA_FROMDEVICE); ++#ifdef CONFIG_E1000E_NAPI + else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) + pci_unmap_page(pdev, buffer_info->dma, + PAGE_SIZE, + PCI_DMA_FROMDEVICE); ++#endif + else if (adapter->clean_rx == e1000_clean_rx_irq_ps) + pci_unmap_single(pdev, buffer_info->dma, + adapter->rx_ps_bsize0, +@@ -1112,11 +1405,13 @@ + } + } + ++#ifdef CONFIG_E1000E_NAPI + /* there also may be some cached data from a chained receive */ + if (rx_ring->rx_skb_top) { + dev_kfree_skb(rx_ring->rx_skb_top); + rx_ring->rx_skb_top = NULL; + } ++#endif + + /* Zero out the descriptor ring */ + memset(rx_ring->desc, 0, rx_ring->size); +@@ -1136,6 +1431,9 @@ + e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); + } + ++#ifndef CONFIG_E1000E_NAPI ++static void e1000_set_itr(struct e1000_adapter *adapter); ++#endif + /** + * e1000_intr_msi - Interrupt Handler + * @irq: interrupt number +@@ -1146,13 +1444,16 @@ + struct net_device *netdev = data; + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; ++#ifndef CONFIG_E1000E_NAPI ++ int i; ++#endif + u32 icr = er32(ICR); + + /* + * read ICR disables interrupts using IAM + */ + +- if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { ++ if (icr & E1000_ICR_LSC) { + hw->mac.get_link_status = 1; + /* + * ICH8 workaround-- Call gig speed drop workaround on cable +@@ -1179,13 +1480,30 @@ + mod_timer(&adapter->watchdog_timer, jiffies + 1); + } + +- if (netif_rx_schedule_prep(netdev, &adapter->napi)) { ++#ifdef CONFIG_E1000E_NAPI ++ if (napi_schedule_prep(&adapter->napi)) { + adapter->total_tx_bytes = 0; + adapter->total_tx_packets = 0; + adapter->total_rx_bytes = 0; + adapter->total_rx_packets = 0; +- __netif_rx_schedule(netdev, &adapter->napi); +- } ++ __napi_schedule(&adapter->napi); ++ } ++#else ++ adapter->total_tx_bytes = 0; ++ adapter->total_rx_bytes = 0; ++ adapter->total_tx_packets = 0; ++ adapter->total_rx_packets = 0; ++ ++ for (i = 0; i < E1000_MAX_INTR; i++) { ++ int rx_cleaned = adapter->clean_rx(adapter); ++ int tx_cleaned_complete = e1000_clean_tx_irq(adapter); ++ if (!rx_cleaned && tx_cleaned_complete) ++ break; ++ } ++ ++ if (likely(adapter->itr_setting & 3)) ++ e1000_set_itr(adapter); ++#endif /* CONFIG_E1000E_NAPI */ + + return IRQ_HANDLED; + } +@@ -1200,11 +1518,16 @@ + struct net_device *netdev = data; + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; ++#ifndef CONFIG_E1000E_NAPI ++ int i; ++ int rx_cleaned, tx_cleaned_complete; ++#endif + u32 rctl, icr = er32(ICR); + +- if (!icr) ++ if (!icr || test_bit(__E1000_DOWN, &adapter->state)) + return IRQ_NONE; /* Not our interrupt */ + ++#ifdef CONFIG_E1000E_NAPI + /* + * IMS will not auto-mask if INT_ASSERTED is not set, and if it is + * not set, then the adapter didn't send an interrupt +@@ -1212,13 +1535,14 @@ + if (!(icr & E1000_ICR_INT_ASSERTED)) + return IRQ_NONE; + ++#endif /* CONFIG_E1000E_NAPI */ + /* + * Interrupt Auto-Mask...upon reading ICR, + * interrupts are masked. No need for the + * IMC write + */ + +- if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { ++ if (icr & E1000_ICR_LSC) { + hw->mac.get_link_status = 1; + /* + * ICH8 workaround-- Call gig speed drop workaround on cable +@@ -1246,17 +1570,35 @@ + mod_timer(&adapter->watchdog_timer, jiffies + 1); + } + +- if (netif_rx_schedule_prep(netdev, &adapter->napi)) { ++#ifdef CONFIG_E1000E_NAPI ++ if (napi_schedule_prep(&adapter->napi)) { + adapter->total_tx_bytes = 0; + adapter->total_tx_packets = 0; + adapter->total_rx_bytes = 0; + adapter->total_rx_packets = 0; +- __netif_rx_schedule(netdev, &adapter->napi); +- } ++ __napi_schedule(&adapter->napi); ++ } ++#else ++ adapter->total_tx_bytes = 0; ++ adapter->total_rx_bytes = 0; ++ adapter->total_tx_packets = 0; ++ adapter->total_rx_packets = 0; ++ ++ for (i = 0; i < E1000_MAX_INTR; i++) { ++ rx_cleaned = adapter->clean_rx(adapter); ++ tx_cleaned_complete = e1000_clean_tx_irq(adapter); ++ if (!rx_cleaned && tx_cleaned_complete) ++ break; ++ } ++ ++ if (likely(adapter->itr_setting & 3)) ++ e1000_set_itr(adapter); ++#endif /* CONFIG_E1000E_NAPI */ + + return IRQ_HANDLED; + } + ++#ifdef CONFIG_E1000E_MSIX + static irqreturn_t e1000_msix_other(int irq, void *data) + { + struct net_device *netdev = data; +@@ -1288,6 +1630,7 @@ + } + + ++#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER + static irqreturn_t e1000_intr_msix_tx(int irq, void *data) + { + struct net_device *netdev = data; +@@ -1306,10 +1649,15 @@ + return IRQ_HANDLED; + } + ++#endif /* CONFIG_E1000E_SEPARATE_TX_HANDLER */ + static irqreturn_t e1000_intr_msix_rx(int irq, void *data) + { + struct net_device *netdev = data; + struct e1000_adapter *adapter = netdev_priv(netdev); ++#ifndef CONFIG_E1000E_NAPI ++ int i; ++ struct e1000_hw *hw = &adapter->hw; ++#endif + + /* Write the ITR value calculated at the end of the + * previous interrupt. +@@ -1320,11 +1668,41 @@ + adapter->rx_ring->set_itr = 0; + } + +- if (netif_rx_schedule_prep(netdev, &adapter->napi)) { ++#ifdef CONFIG_E1000E_NAPI ++ if (napi_schedule_prep(&adapter->napi)) { + adapter->total_rx_bytes = 0; + adapter->total_rx_packets = 0; +- __netif_rx_schedule(netdev, &adapter->napi); +- } ++#ifndef CONFIG_E1000E_SEPARATE_TX_HANDLER ++ adapter->total_tx_bytes = 0; ++ adapter->total_tx_packets = 0; ++#endif /* CONFIG_E1000E_SEPARATE_TX_HANDLER */ ++ __napi_schedule(&adapter->napi); ++ } ++#else ++ adapter->total_rx_bytes = 0; ++ adapter->total_rx_packets = 0; ++#ifndef CONFIG_E1000E_SEPARATE_TX_HANDLER ++ adapter->total_tx_bytes = 0; ++ adapter->total_tx_packets = 0; ++#endif ++ ++ for (i = 0; i < E1000_MAX_INTR; i++) { ++ int rx_cleaned = adapter->clean_rx(adapter); ++#ifndef CONFIG_E1000E_SEPARATE_TX_HANDLER ++ int tx_cleaned_complete = e1000_clean_tx_irq(adapter); ++ if (!rx_cleaned && tx_cleaned_complete) ++#else ++ if (!rx_cleaned) ++#endif ++ goto out; ++ } ++ /* If we got here, the ring was not completely cleaned, ++ * so fire another interrupt. ++ */ ++ ew32(ICS, adapter->rx_ring->ims_val); ++ ++out: ++#endif /* CONFIG_E1000E_NAPI */ + return IRQ_HANDLED; + } + +@@ -1364,12 +1742,16 @@ + + /* Configure Tx vector */ + tx_ring->ims_val = E1000_IMS_TXQ0; ++#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER + vector++; + if (tx_ring->itr_val) + writel(1000000000 / (tx_ring->itr_val * 256), + hw->hw_addr + tx_ring->itr_register); + else + writel(1, hw->hw_addr + tx_ring->itr_register); ++#else ++ rx_ring->ims_val |= tx_ring->ims_val; ++#endif + adapter->eiac_mask |= tx_ring->ims_val; + ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); + +@@ -1392,7 +1774,6 @@ + ctrl_ext |= E1000_CTRL_EXT_PBA_CLR; + + /* Auto-Mask Other interrupts upon ICR read */ +-#define E1000_EIAC_MASK_82574 0x01F00000 + ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER); + ctrl_ext |= E1000_CTRL_EXT_EIAME; + ew32(CTRL_EXT, ctrl_ext); +@@ -1428,7 +1809,11 @@ + switch (adapter->int_mode) { + case E1000E_INT_MODE_MSIX: + if (adapter->flags & FLAG_HAS_MSIX) { ++#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER + numvecs = 3; /* RxQ0, TxQ0 and other */ ++#else ++ numvecs = 2; /* RxQ0/TxQ0 and other */ ++#endif + adapter->msix_entries = kcalloc(numvecs, + sizeof(struct msix_entry), + GFP_KERNEL); +@@ -1478,7 +1863,11 @@ + int err = 0, vector = 0; + + if (strlen(netdev->name) < (IFNAMSIZ - 5)) +- sprintf(adapter->rx_ring->name, "%s-rx0", netdev->name); ++#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER ++ sprintf(adapter->rx_ring->name, "%s-rx-0", netdev->name); ++#else ++ sprintf(adapter->rx_ring->name, "%s-Q0", netdev->name); ++#endif + else + memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); + err = request_irq(adapter->msix_entries[vector].vector, +@@ -1490,8 +1879,9 @@ + adapter->rx_ring->itr_val = adapter->itr; + vector++; + ++#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER + if (strlen(netdev->name) < (IFNAMSIZ - 5)) +- sprintf(adapter->tx_ring->name, "%s-tx0", netdev->name); ++ sprintf(adapter->tx_ring->name, "%s-tx-0", netdev->name); + else + memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); + err = request_irq(adapter->msix_entries[vector].vector, +@@ -1503,6 +1893,7 @@ + adapter->tx_ring->itr_val = adapter->itr; + vector++; + ++#endif /* CONFIG_E1000E_SEPARATE_TX_HANDLER */ + err = request_irq(adapter->msix_entries[vector].vector, + &e1000_msix_other, 0, netdev->name, netdev); + if (err) +@@ -1514,6 +1905,7 @@ + return err; + } + ++#endif /* CONFIG_E1000E_MSIX */ + /** + * e1000_request_irq - initialize interrupts + * +@@ -1523,8 +1915,12 @@ + static int e1000_request_irq(struct e1000_adapter *adapter) + { + struct net_device *netdev = adapter->netdev; +- int err; +- ++#ifndef CONFIG_E1000E_MSIX ++ int irq_flags = IRQF_SHARED; ++#endif ++ int err; ++ ++#ifdef CONFIG_E1000E_MSIX + if (adapter->msix_entries) { + err = e1000_request_msix(adapter); + if (!err) +@@ -1549,6 +1945,27 @@ + netdev->name, netdev); + if (err) + e_err("Unable to allocate interrupt, Error: %d\n", err); ++#else ++ if (!(adapter->flags & FLAG_MSI_TEST_FAILED)) { ++ err = pci_enable_msi(adapter->pdev); ++ if (!err) { ++ adapter->flags |= FLAG_MSI_ENABLED; ++ irq_flags = 0; ++ } ++ } ++ ++ err = request_irq(adapter->pdev->irq, ++ ((adapter->flags & FLAG_MSI_ENABLED) ? ++ &e1000_intr_msi : &e1000_intr), ++ irq_flags, netdev->name, netdev); ++ if (err) { ++ if (adapter->flags & FLAG_MSI_ENABLED) { ++ pci_disable_msi(adapter->pdev); ++ adapter->flags &= ~FLAG_MSI_ENABLED; ++ } ++ e_err("Unable to allocate interrupt, Error: %d\n", err); ++ } ++#endif /* CONFIG_E1000E_MSIX */ + + return err; + } +@@ -1557,21 +1974,31 @@ + { + struct net_device *netdev = adapter->netdev; + ++#ifdef CONFIG_E1000E_MSIX + if (adapter->msix_entries) { + int vector = 0; + + free_irq(adapter->msix_entries[vector].vector, netdev); + vector++; + ++#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER + free_irq(adapter->msix_entries[vector].vector, netdev); + vector++; + ++#endif + /* Other Causes interrupt vector */ + free_irq(adapter->msix_entries[vector].vector, netdev); + return; + } + ++#endif /* CONFIG_E1000E_MSIX */ + free_irq(adapter->pdev->irq, netdev); ++#ifndef CONFIG_E1000E_MSIX ++ if (adapter->flags & FLAG_MSI_ENABLED) { ++ pci_disable_msi(adapter->pdev); ++ adapter->flags &= ~FLAG_MSI_ENABLED; ++ } ++#endif + } + + /** +@@ -1582,8 +2009,10 @@ + struct e1000_hw *hw = &adapter->hw; + + ew32(IMC, ~0); ++#ifdef CONFIG_E1000E_MSIX + if (adapter->msix_entries) + ew32(EIAC_82574, 0); ++#endif /* CONFIG_E1000E_MSIX */ + e1e_flush(); + synchronize_irq(adapter->pdev->irq); + } +@@ -1595,12 +2024,16 @@ + { + struct e1000_hw *hw = &adapter->hw; + ++#ifdef CONFIG_E1000E_MSIX + if (adapter->msix_entries) { + ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); + ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC); + } else { + ew32(IMS, IMS_ENABLE_MASK); + } ++#else ++ ew32(IMS, IMS_ENABLE_MASK); ++#endif /* CONFIG_E1000E_MSIX */ + e1e_flush(); + } + +@@ -1698,7 +2131,6 @@ + + tx_ring->next_to_use = 0; + tx_ring->next_to_clean = 0; +- spin_lock_init(&adapter->tx_queue_lock); + + return 0; + err: +@@ -1757,7 +2189,7 @@ + } + err: + vfree(rx_ring->buffer_info); +- e_err("Unable to allocate memory for the transmit descriptor ring\n"); ++ e_err("Unable to allocate memory for the receive descriptor ring\n"); + return err; + } + +@@ -1959,11 +2391,15 @@ + min(adapter->itr + (new_itr >> 2), new_itr) : + new_itr; + adapter->itr = new_itr; ++#ifdef CONFIG_E1000E_MSIX + adapter->rx_ring->itr_val = new_itr; + if (adapter->msix_entries) + adapter->rx_ring->set_itr = 1; + else + ew32(ITR, 1000000000 / (new_itr * 256)); ++#else ++ ew32(ITR, 1000000000 / (new_itr * 256)); ++#endif + } + } + +@@ -1989,61 +2425,62 @@ + return -ENOMEM; + } + +-/** +- * e1000_clean - NAPI Rx polling callback ++#ifdef CONFIG_E1000E_NAPI ++/** ++ * e1000_poll - NAPI Rx polling callback + * @napi: struct associated with this polling callback + * @budget: amount of packets driver is allowed to process this poll + **/ +-static int e1000_clean(struct napi_struct *napi, int budget) +-{ +- struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi); +- struct e1000_hw *hw = &adapter->hw; +- struct net_device *poll_dev = adapter->netdev; +- int tx_cleaned = 0, work_done = 0; +- +- /* Must NOT use netdev_priv macro here. */ +- adapter = poll_dev->priv; +- +- if (adapter->msix_entries && +- !(adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) +- goto clean_rx; +- +- /* +- * e1000_clean is called per-cpu. This lock protects +- * tx_ring from being cleaned by multiple cpus +- * simultaneously. A failure obtaining the lock means +- * tx_ring is currently being cleaned anyway. +- */ +- if (spin_trylock(&adapter->tx_queue_lock)) { +- tx_cleaned = e1000_clean_tx_irq(adapter); +- spin_unlock(&adapter->tx_queue_lock); +- } +- +-clean_rx: ++static int e1000_poll(struct napi_struct *napi, int budget) ++{ ++ struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, ++ napi); ++ int tx_clean_complete = 1, work_done = 0; ++#ifdef CONFIG_E1000E_MSIX ++ struct e1000_hw *hw = &adapter->hw; ++#endif ++ ++#ifdef CONFIG_E1000E_MSIX ++ if (!adapter->msix_entries || ++ (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) ++#endif ++ tx_clean_complete = e1000_clean_tx_irq(adapter); ++ + adapter->clean_rx(adapter, &work_done, budget); + +- if (tx_cleaned) ++ if (!tx_clean_complete) + work_done = budget; + +- /* If budget not fully consumed, exit the polling mode */ ++#ifndef HAVE_NETDEV_NAPI_LIST ++ if (!netif_running(adapter->netdev)) ++ work_done = 0; ++ ++#endif ++ /* If Tx completed and all Rx work done, exit the polling mode */ + if (work_done < budget) { ++ napi_complete(napi); + if (adapter->itr_setting & 3) + e1000_set_itr(adapter); +- netif_rx_complete(poll_dev, napi); +- if (adapter->msix_entries) +- ew32(IMS, adapter->rx_ring->ims_val); +- else +- e1000_irq_enable(adapter); ++ if (!test_bit(__E1000_DOWN, &adapter->state)) { ++#ifdef CONFIG_E1000E_MSIX ++ if (adapter->msix_entries) ++ ew32(IMS, adapter->rx_ring->ims_val); ++ else ++#endif ++ e1000_irq_enable(adapter); ++ } + } + + return work_done; + } + ++#endif /* CONFIG_E1000E_NAPI */ + static void e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid) + { + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; + u32 vfta, index; ++ struct net_device *v_netdev; + + /* don't update vlan cookie if already programmed */ + if ((adapter->hw.mng_cookie.status & +@@ -2055,6 +2492,13 @@ + vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); + vfta |= (1 << (vid & 0x1F)); + e1000e_write_vfta(hw, index, vfta); ++ /* ++ * Copy feature flags from netdev to the vlan netdev for this vid. ++ * This allows things like TSO to bubble down to our vlan device. ++ */ ++ v_netdev = vlan_group_get_device(adapter->vlgrp, vid); ++ v_netdev->features |= adapter->netdev->features; ++ vlan_group_set_device(adapter->vlgrp, vid, v_netdev); + } + + static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) +@@ -2214,13 +2658,13 @@ + /* Setup the HW Tx Head and Tail descriptor pointers */ + tdba = tx_ring->dma; + tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); +- ew32(TDBAL, (tdba & DMA_32BIT_MASK)); +- ew32(TDBAH, (tdba >> 32)); +- ew32(TDLEN, tdlen); +- ew32(TDH, 0); +- ew32(TDT, 0); +- tx_ring->head = E1000_TDH; +- tx_ring->tail = E1000_TDT; ++ ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); ++ ew32(TDBAH(0), (tdba >> 32)); ++ ew32(TDLEN(0), tdlen); ++ ew32(TDH(0), 0); ++ ew32(TDT(0), 0); ++ tx_ring->head = E1000_TDH(0); ++ tx_ring->tail = E1000_TDT(0); + + /* Set the default values for the Tx Inter Packet Gap timer */ + tipg = DEFAULT_82543_TIPG_IPGT_COPPER; /* 8 */ +@@ -2312,12 +2756,28 @@ + else + rctl |= E1000_RCTL_LPE; + +- /* Some systems expect that the CRC is included in SMBUS traffic. The ++ /* Some systems expect that the CRC is included in SMBUS traffic. The + * hardware strips the CRC before sending to both SMBUS (BMC) and to +- * host memory when this is enabled +- */ ++ * host memory when this is enabled */ + if (adapter->flags2 & FLAG2_CRC_STRIPPING) + rctl |= E1000_RCTL_SECRC; ++ ++ /* Workaround Si errata on 82577 PHY */ ++ if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { ++ u16 phy_data; ++ ++ e1e_rphy(hw, PHY_REG(770, 26), &phy_data); ++ phy_data &= 0xfff8; ++ phy_data |= (1 << 2); ++ e1e_wphy(hw, PHY_REG(770, 26), phy_data); ++ ++ e1e_rphy(hw, 22, &phy_data); ++ phy_data &= 0x0fff; ++ phy_data |= (1 << 14); ++ e1e_wphy(hw, 0x10, 0x2823); ++ e1e_wphy(hw, 0x11, 0x0003); ++ e1e_wphy(hw, 22, phy_data); ++ } + + /* Setup buffer sizes */ + rctl &= ~E1000_RCTL_SZ_4096; +@@ -2432,10 +2892,12 @@ + sizeof(union e1000_rx_desc_packet_split); + adapter->clean_rx = e1000_clean_rx_irq_ps; + adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; ++#ifdef CONFIG_E1000E_NAPI + } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { + rdlen = rx_ring->count * sizeof(struct e1000_rx_desc); + adapter->clean_rx = e1000_clean_jumbo_rx_irq; + adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; ++#endif + } else { + rdlen = rx_ring->count * sizeof(struct e1000_rx_desc); + adapter->clean_rx = e1000_clean_rx_irq; +@@ -2457,11 +2919,11 @@ + ew32(ITR, 1000000000 / (adapter->itr * 256)); + + ctrl_ext = er32(CTRL_EXT); +- /* Reset delay timers after every interrupt */ +- ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; ++#ifdef CONFIG_E1000E_NAPI + /* Auto-Mask interrupts upon ICR access */ + ctrl_ext |= E1000_CTRL_EXT_IAME; + ew32(IAM, 0xffffffff); ++#endif + ew32(CTRL_EXT, ctrl_ext); + e1e_flush(); + +@@ -2470,13 +2932,13 @@ + * the Base and Length of the Rx Descriptor Ring + */ + rdba = rx_ring->dma; +- ew32(RDBAL, (rdba & DMA_32BIT_MASK)); +- ew32(RDBAH, (rdba >> 32)); +- ew32(RDLEN, rdlen); +- ew32(RDH, 0); +- ew32(RDT, 0); +- rx_ring->head = E1000_RDH; +- rx_ring->tail = E1000_RDT; ++ ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); ++ ew32(RDBAH(0), (rdba >> 32)); ++ ew32(RDLEN(0), rdlen); ++ ew32(RDH(0), 0); ++ ew32(RDT(0), 0); ++ rx_ring->head = E1000_RDH(0); ++ rx_ring->tail = E1000_RDT(0); + + /* Enable Receive Checksum Offload for TCP and UDP */ + rxcsum = er32(RXCSUM); +@@ -2500,21 +2962,23 @@ + * packet size is equal or larger than the specified value (in 8 byte + * units), e.g. using jumbo frames when setting to E1000_ERT_2048 + */ +- if ((adapter->flags & FLAG_HAS_ERT) && +- (adapter->netdev->mtu > ETH_DATA_LEN)) { +- u32 rxdctl = er32(RXDCTL(0)); +- ew32(RXDCTL(0), rxdctl | 0x3); +- ew32(ERT, E1000_ERT_2048 | (1 << 13)); +- /* +- * With jumbo frames and early-receive enabled, excessive +- * C4->C2 latencies result in dropped transactions. +- */ +- pm_qos_update_requirement(PM_QOS_CPU_DMA_LATENCY, +- e1000e_driver_name, 55); +- } else { +- pm_qos_update_requirement(PM_QOS_CPU_DMA_LATENCY, +- e1000e_driver_name, +- PM_QOS_DEFAULT_VALUE); ++ if (adapter->flags & FLAG_HAS_ERT) { ++ if (adapter->netdev->mtu > ETH_DATA_LEN) { ++ u32 rxdctl = er32(RXDCTL(0)); ++ ew32(RXDCTL(0), rxdctl | 0x3); ++ ew32(ERT, E1000_ERT_2048 | (1 << 13)); ++ /* ++ * With jumbo frames and early-receive enabled, ++ * excessive C-state transition latencies result in ++ * dropped transactions. ++ */ ++ pm_qos_update_requirement(PM_QOS_CPU_DMA_LATENCY, ++ adapter->netdev->name, 55); ++ } else { ++ pm_qos_update_requirement(PM_QOS_CPU_DMA_LATENCY, ++ adapter->netdev->name, ++ PM_QOS_DEFAULT_VALUE); ++ } + } + + /* Enable Receives */ +@@ -2526,22 +2990,14 @@ + * @hw: pointer to the HW structure + * @mc_addr_list: array of multicast addresses to program + * @mc_addr_count: number of multicast addresses to program +- * @rar_used_count: the first RAR register free to program +- * @rar_count: total number of supported Receive Address Registers +- * +- * Updates the Receive Address Registers and Multicast Table Array. ++ * ++ * Updates the Multicast Table Array. + * The caller must have a packed mc_addr_list of multicast addresses. +- * The parameter rar_count will usually be hw->mac.rar_entry_count +- * unless there are workarounds that change this. Currently no func pointer +- * exists and all implementations are handled in the generic version of this +- * function. + **/ + static void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list, +- u32 mc_addr_count, u32 rar_used_count, +- u32 rar_count) +-{ +- hw->mac.ops.update_mc_addr_list(hw, mc_addr_list, mc_addr_count, +- rar_used_count, rar_count); ++ u32 mc_addr_count) ++{ ++ hw->mac.ops.update_mc_addr_list(hw, mc_addr_list, mc_addr_count); + } + + /** +@@ -2557,7 +3013,6 @@ + { + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +- struct e1000_mac_info *mac = &hw->mac; + struct dev_mc_list *mc_ptr; + u8 *mta_list; + u32 rctl; +@@ -2599,15 +3054,14 @@ + mc_ptr = mc_ptr->next; + } + +- e1000_update_mc_addr_list(hw, mta_list, i, 1, +- mac->rar_entry_count); ++ e1000_update_mc_addr_list(hw, mta_list, i); + kfree(mta_list); + } else { + /* + * if we're called from probe, we might not have + * anything to do here, so clear out the list + */ +- e1000_update_mc_addr_list(hw, NULL, 0, 1, mac->rar_entry_count); ++ e1000_update_mc_addr_list(hw, NULL, 0); + } + } + +@@ -2638,18 +3092,8 @@ + **/ + void e1000e_power_up_phy(struct e1000_adapter *adapter) + { +- u16 mii_reg = 0; +- +- /* Just clear the power down bit to wake the phy back up */ +- if (adapter->hw.phy.media_type == e1000_media_type_copper) { +- /* +- * According to the manual, the phy will retain its +- * settings across a power-down/up cycle +- */ +- e1e_rphy(&adapter->hw, PHY_CONTROL, &mii_reg); +- mii_reg &= ~MII_CR_POWER_DOWN; +- e1e_wphy(&adapter->hw, PHY_CONTROL, mii_reg); +- } ++ if (adapter->hw.phy.ops.power_up) ++ adapter->hw.phy.ops.power_up(&adapter->hw); + + adapter->hw.mac.ops.setup_link(&adapter->hw); + } +@@ -2657,35 +3101,17 @@ + /** + * e1000_power_down_phy - Power down the PHY + * +- * Power down the PHY so no link is implied when interface is down +- * The PHY cannot be powered down is management or WoL is active ++ * Power down the PHY so no link is implied when interface is down. ++ * The PHY cannot be powered down if management or WoL is active. + */ + static void e1000_power_down_phy(struct e1000_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- u16 mii_reg; +- + /* WoL is enabled */ + if (adapter->wol) + return; + +- /* non-copper PHY? */ +- if (adapter->hw.phy.media_type != e1000_media_type_copper) +- return; +- +- /* reset is blocked because of a SoL/IDER session */ +- if (e1000e_check_mng_mode(hw) || e1000_check_reset_block(hw)) +- return; +- +- /* manageability (AMT) is enabled */ +- if (er32(MANC) & E1000_MANC_SMBUS_EN) +- return; +- +- /* power down the PHY */ +- e1e_rphy(hw, PHY_CONTROL, &mii_reg); +- mii_reg |= MII_CR_POWER_DOWN; +- e1e_wphy(hw, PHY_CONTROL, mii_reg); +- mdelay(1); ++ if (adapter->hw.phy.ops.power_down) ++ adapter->hw.phy.ops.power_down(&adapter->hw); + } + + /** +@@ -2762,30 +3188,32 @@ + /* + * flow control settings + * +- * The high water mark must be low enough to fit one full frame ++ * The high water mark must be low enough to fit two full frames + * (or the size used for early receive) above it in the Rx FIFO. + * Set it to the lower of: + * - 90% of the Rx FIFO size, and + * - the full Rx FIFO size minus the early receive size (for parts + * with ERT support assuming ERT set to E1000_ERT_2048), or +- * - the full Rx FIFO size minus one full frame +- */ +- if (adapter->flags & FLAG_HAS_ERT) ++ * - the full Rx FIFO size minus two full frames ++ */ ++ if ((adapter->flags & FLAG_HAS_ERT) && ++ (adapter->netdev->mtu > ETH_DATA_LEN)) + hwm = min(((pba << 10) * 9 / 10), + ((pba << 10) - (E1000_ERT_2048 << 3))); + else + hwm = min(((pba << 10) * 9 / 10), +- ((pba << 10) - adapter->max_frame_size)); +- +- fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ +- fc->low_water = fc->high_water - 8; ++ ((pba << 10) - (2 * adapter->max_frame_size))); ++ ++ fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ ++ fc->low_water = (fc->high_water - (2 * adapter->max_frame_size)); ++ fc->low_water &= E1000_FCRTL_RTL; /* 8-byte granularity */ + + if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) + fc->pause_time = 0xFFFF; + else + fc->pause_time = E1000_FC_PAUSE_TIME; + fc->send_xon = 1; +- fc->type = fc->original_type; ++ fc->current_mode = fc->requested_mode; + + /* Allow time for pending master requests to run */ + mac->ops.reset_hw(hw); +@@ -2798,6 +3226,8 @@ + e1000_get_hw_control(adapter); + + ew32(WUC, 0); ++ if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) ++ e1e_wphy(&adapter->hw, BM_WUC, 0); + + if (mac->ops.init_hw(hw)) + e_err("Hardware Error\n"); +@@ -2810,7 +3240,8 @@ + e1000e_reset_adaptive(hw); + e1000_get_phy_info(hw); + +- if (!(adapter->flags & FLAG_SMART_POWER_DOWN)) { ++ if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && ++ !(adapter->flags & FLAG_SMART_POWER_DOWN)) { + u16 phy_data = 0; + /* + * speed up time to link by disabling smart power down, ignore +@@ -2827,14 +3258,24 @@ + { + struct e1000_hw *hw = &adapter->hw; + ++ /* DMA latency requirement to workaround early-receive/jumbo issue */ ++ if (adapter->flags & FLAG_HAS_ERT) ++ pm_qos_add_requirement(PM_QOS_CPU_DMA_LATENCY, ++ adapter->netdev->name, ++ PM_QOS_DEFAULT_VALUE); ++ + /* hardware has been reset, we need to reload some things */ + e1000_configure(adapter); + + clear_bit(__E1000_DOWN, &adapter->state); + ++#ifdef CONFIG_E1000E_NAPI + napi_enable(&adapter->napi); ++#endif ++#ifdef CONFIG_E1000E_MSIX + if (adapter->msix_entries) + e1000_configure_msix(adapter); ++#endif /* CONFIG_E1000E_MSIX */ + e1000_irq_enable(adapter); + + /* fire a link change interrupt to start the watchdog */ +@@ -2869,7 +3310,9 @@ + e1e_flush(); + msleep(10); + ++#ifdef CONFIG_E1000E_NAPI + napi_disable(&adapter->napi); ++#endif + e1000_irq_disable(adapter); + + del_timer_sync(&adapter->watchdog_timer); +@@ -2880,10 +3323,16 @@ + adapter->link_speed = 0; + adapter->link_duplex = 0; + ++#ifdef HAVE_PCI_ERS + if (!pci_channel_offline(adapter->pdev)) ++#endif + e1000e_reset(adapter); + e1000_clean_tx_ring(adapter); + e1000_clean_rx_ring(adapter); ++ ++ if (adapter->flags & FLAG_HAS_ERT) ++ pm_qos_remove_requirement(PM_QOS_CPU_DMA_LATENCY, ++ adapter->netdev->name); + + /* + * TODO: for power management, we could drop the link and +@@ -2912,18 +3361,34 @@ + static int __devinit e1000_sw_init(struct e1000_adapter *adapter) + { + struct net_device *netdev = adapter->netdev; ++ s32 rc; + + adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN; + adapter->rx_ps_bsize0 = 128; + adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; + adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; + ++ /* Set various function pointers */ ++ adapter->ei->init_ops(&adapter->hw); ++ ++ rc = adapter->hw.mac.ops.init_params(&adapter->hw); ++ if (rc) ++ return rc; ++ ++ rc = adapter->hw.nvm.ops.init_params(&adapter->hw); ++ if (rc) ++ return rc; ++ ++ rc = adapter->hw.phy.ops.init_params(&adapter->hw); ++ if (rc) ++ return rc; ++ ++#ifdef CONFIG_E1000E_MSIX + e1000e_set_interrupt_capability(adapter); + ++#endif /* CONFIG_E1000E_MSIX */ + if (e1000_alloc_queues(adapter)) + return -ENOMEM; +- +- spin_lock_init(&adapter->tx_queue_lock); + + /* Explicitly disable IRQ since the NIC can be in any state. */ + e1000_irq_disable(adapter); +@@ -2944,7 +3409,7 @@ + struct e1000_hw *hw = &adapter->hw; + u32 icr = er32(ICR); + +- e_dbg("%s: icr is %08X\n", netdev->name, icr); ++ e_dbg("icr is %08X\n", icr); + if (icr & E1000_ICR_RXSEQ) { + adapter->flags &= ~FLAG_MSI_TEST_FAILED; + wmb(); +@@ -2971,7 +3436,9 @@ + + /* free the real vector and request a test handler */ + e1000_free_irq(adapter); ++#ifdef CONFIG_E1000E_MSIX + e1000e_reset_interrupt_capability(adapter); ++#endif + + /* Assume that the test fails, if it succeeds then the test + * MSI irq handler will unset this flag */ +@@ -3002,7 +3469,9 @@ + rmb(); + + if (adapter->flags & FLAG_MSI_TEST_FAILED) { ++#ifdef CONFIG_E1000E_MSIX + adapter->int_mode = E1000E_INT_MODE_LEGACY; ++#endif + err = -EIO; + e_info("MSI interrupt test failed!\n"); + } +@@ -3014,9 +3483,13 @@ + goto msi_test_failed; + + /* okay so the test worked, restore settings */ +- e_dbg("%s: MSI interrupt test succeeded!\n", netdev->name); ++ e_dbg("MSI interrupt test succeeded!\n"); + msi_test_failed: ++#ifdef CONFIG_E1000E_MSIX + e1000e_set_interrupt_capability(adapter); ++#else ++ /* restore the original vector, even if it failed */ ++#endif + e1000_request_irq(adapter); + return err; + } +@@ -3126,7 +3599,11 @@ + * ignore e1000e MSI messages, which means we need to test our MSI + * interrupt now + */ ++#ifdef CONFIG_E1000E_MSIX + if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { ++#else ++ { ++#endif + err = e1000_test_msi(adapter); + if (err) { + e_err("Interrupt allocation failed\n"); +@@ -3137,7 +3614,9 @@ + /* From here on the code is the same as e1000e_up() */ + clear_bit(__E1000_DOWN, &adapter->state); + ++#ifdef CONFIG_E1000E_NAPI + napi_enable(&adapter->napi); ++#endif + + e1000_irq_enable(adapter); + +@@ -3274,7 +3753,10 @@ + void e1000e_update_stats(struct e1000_adapter *adapter) + { + struct e1000_hw *hw = &adapter->hw; +- struct pci_dev *pdev = adapter->pdev; ++#ifdef HAVE_PCI_ERS ++ struct pci_dev *pdev = adapter->pdev; ++#endif ++ u16 phy_data; + + /* + * Prevent stats update while adapter is being reset, or if the pci +@@ -3282,8 +3764,10 @@ + */ + if (adapter->link_speed == 0) + return; ++#ifdef HAVE_PCI_ERS + if (pci_channel_offline(pdev)) + return; ++#endif + + adapter->stats.crcerrs += er32(CRCERRS); + adapter->stats.gprc += er32(GPRC); +@@ -3294,11 +3778,34 @@ + adapter->stats.roc += er32(ROC); + + adapter->stats.mpc += er32(MPC); +- adapter->stats.scc += er32(SCC); +- adapter->stats.ecol += er32(ECOL); +- adapter->stats.mcc += er32(MCC); +- adapter->stats.latecol += er32(LATECOL); +- adapter->stats.dc += er32(DC); ++ if ((hw->phy.type == e1000_phy_82578) || ++ (hw->phy.type == e1000_phy_82577)) { ++ e1e_rphy(hw, HV_SCC_UPPER, &phy_data); ++ e1e_rphy(hw, HV_SCC_LOWER, &phy_data); ++ adapter->stats.scc += phy_data; ++ ++ e1e_rphy(hw, HV_ECOL_UPPER, &phy_data); ++ e1e_rphy(hw, HV_ECOL_LOWER, &phy_data); ++ adapter->stats.ecol += phy_data; ++ ++ e1e_rphy(hw, HV_MCC_UPPER, &phy_data); ++ e1e_rphy(hw, HV_MCC_LOWER, &phy_data); ++ adapter->stats.mcc += phy_data; ++ ++ e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data); ++ e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data); ++ adapter->stats.latecol += phy_data; ++ ++ e1e_rphy(hw, HV_DC_UPPER, &phy_data); ++ e1e_rphy(hw, HV_DC_LOWER, &phy_data); ++ adapter->stats.dc += phy_data; ++ } else { ++ adapter->stats.scc += er32(SCC); ++ adapter->stats.ecol += er32(ECOL); ++ adapter->stats.mcc += er32(MCC); ++ adapter->stats.latecol += er32(LATECOL); ++ adapter->stats.dc += er32(DC); ++ } + adapter->stats.xonrxc += er32(XONRXC); + adapter->stats.xontxc += er32(XONTXC); + adapter->stats.xoffrxc += er32(XOFFRXC); +@@ -3316,13 +3823,28 @@ + + hw->mac.tx_packet_delta = er32(TPT); + adapter->stats.tpt += hw->mac.tx_packet_delta; +- hw->mac.collision_delta = er32(COLC); ++ if ((hw->phy.type == e1000_phy_82578) || ++ (hw->phy.type == e1000_phy_82577)) { ++ e1e_rphy(hw, HV_COLC_UPPER, &phy_data); ++ e1e_rphy(hw, HV_COLC_LOWER, &phy_data); ++ hw->mac.collision_delta = phy_data; ++ } else { ++ hw->mac.collision_delta = er32(COLC); ++ } + adapter->stats.colc += hw->mac.collision_delta; + + adapter->stats.algnerrc += er32(ALGNERRC); + adapter->stats.rxerrc += er32(RXERRC); +- if (hw->mac.type != e1000_82574) +- adapter->stats.tncrs += er32(TNCRS); ++ if ((hw->phy.type == e1000_phy_82578) || ++ (hw->phy.type == e1000_phy_82577)) { ++ e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data); ++ e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data); ++ adapter->stats.tncrs += phy_data; ++ } else { ++ if ((hw->mac.type != e1000_82574) && ++ (hw->mac.type != e1000_82583)) ++ adapter->stats.tncrs += er32(TNCRS); ++ } + adapter->stats.cexterr += er32(CEXTERR); + adapter->stats.tsctc += er32(TSCTC); + adapter->stats.tsctfc += er32(TSCTFC); +@@ -3362,6 +3884,7 @@ + adapter->stats.mgpdc += er32(MGTPDC); + } + ++#ifdef SIOCGMIIPHY + /** + * e1000_phy_read_status - Update the PHY register status snapshot + * @adapter: board private structure +@@ -3403,22 +3926,26 @@ + } + } + ++#endif /* SIOCGMIIPHY */ + static void e1000_print_link_info(struct e1000_adapter *adapter) + { + struct e1000_hw *hw = &adapter->hw; + u32 ctrl = er32(CTRL); + +- e_info("Link is Up %d Mbps %s, Flow Control: %s\n", ++ /* Link status message must follow this format for user tools */ ++ printk(KERN_INFO "e1000e: %s NIC Link is Up %d Mbps %s, " ++ "Flow Control: %s\n", ++ adapter->netdev->name, + adapter->link_speed, + (adapter->link_duplex == FULL_DUPLEX) ? + "Full Duplex" : "Half Duplex", + ((ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE)) ? + "RX/TX" : + ((ctrl & E1000_CTRL_RFCE) ? "RX" : +- ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None" ))); +-} +- +-static bool e1000_has_link(struct e1000_adapter *adapter) ++ ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None"))); ++} ++ ++bool e1000_has_link(struct e1000_adapter *adapter) + { + struct e1000_hw *hw = &adapter->hw; + bool link_active = 0; +@@ -3493,6 +4020,7 @@ + struct e1000_adapter, watchdog_task); + struct net_device *netdev = adapter->netdev; + struct e1000_mac_info *mac = &adapter->hw.mac; ++ struct e1000_phy_info *phy = &adapter->hw.phy; + struct e1000_ring *tx_ring = adapter->tx_ring; + struct e1000_hw *hw = &adapter->hw; + u32 link, tctl; +@@ -3511,8 +4039,10 @@ + if (link) { + if (!netif_carrier_ok(netdev)) { + bool txb2b = 1; ++#ifdef SIOCGMIIPHY + /* update snapshot of PHY registers on LSC */ + e1000_phy_read_status(adapter); ++#endif + mac->ops.get_link_up_info(&adapter->hw, + &adapter->link_speed, + &adapter->link_duplex); +@@ -3569,6 +4099,7 @@ + ew32(TARC(0), tarc0); + } + ++#ifdef NETIF_F_TSO + /* + * disable TSO for pcie and 10/100 speeds, to avoid + * some hardware issues +@@ -3579,17 +4110,22 @@ + case SPEED_100: + e_info("10/100 speed: disabling TSO\n"); + netdev->features &= ~NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 + netdev->features &= ~NETIF_F_TSO6; ++#endif + break; + case SPEED_1000: + netdev->features |= NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 + netdev->features |= NETIF_F_TSO6; ++#endif + break; + default: + /* oops */ + break; + } + } ++#endif + + /* + * enable transmits in the hardware, need to do this +@@ -3599,6 +4135,13 @@ + tctl |= E1000_TCTL_EN; + ew32(TCTL, tctl); + ++ /* ++ * Perform any post-link-up configuration before ++ * reporting link up. ++ */ ++ if (phy->ops.cfg_on_link_up) ++ phy->ops.cfg_on_link_up(hw); ++ + netif_carrier_on(netdev); + netif_tx_wake_all_queues(netdev); + +@@ -3610,7 +4153,9 @@ + if (netif_carrier_ok(netdev)) { + adapter->link_speed = 0; + adapter->link_duplex = 0; +- e_info("Link is Down\n"); ++ /* Link status message must follow this format */ ++ printk(KERN_INFO "e1000e: %s NIC Link is Down\n", ++ adapter->netdev->name); + netif_carrier_off(netdev); + netif_tx_stop_all_queues(netdev); + if (!test_bit(__E1000_DOWN, &adapter->state)) +@@ -3653,10 +4198,14 @@ + } + + /* Cause software interrupt to ensure Rx ring is cleaned */ ++#ifdef CONFIG_E1000E_MSIX + if (adapter->msix_entries) + ew32(ICS, adapter->rx_ring->ims_val); + else + ew32(ICS, E1000_ICS_RXDMT0); ++#else ++ ew32(ICS, E1000_ICS_RXDMT0); ++#endif + + /* Force detection of hung controller every watchdog period */ + adapter->detect_tx_hung = 1; +@@ -3684,6 +4233,7 @@ + static int e1000_tso(struct e1000_adapter *adapter, + struct sk_buff *skb) + { ++#ifdef NETIF_F_TSO + struct e1000_ring *tx_ring = adapter->tx_ring; + struct e1000_context_desc *context_desc; + struct e1000_buffer *buffer_info; +@@ -3693,68 +4243,69 @@ + u8 ipcss, ipcso, tucss, tucso, hdr_len; + int err; + +- if (skb_is_gso(skb)) { +- if (skb_header_cloned(skb)) { +- err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); +- if (err) +- return err; +- } +- +- hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); +- mss = skb_shinfo(skb)->gso_size; +- if (skb->protocol == htons(ETH_P_IP)) { +- struct iphdr *iph = ip_hdr(skb); +- iph->tot_len = 0; +- iph->check = 0; +- tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, +- iph->daddr, 0, +- IPPROTO_TCP, +- 0); +- cmd_length = E1000_TXD_CMD_IP; +- ipcse = skb_transport_offset(skb) - 1; +- } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { +- ipv6_hdr(skb)->payload_len = 0; +- tcp_hdr(skb)->check = +- ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, +- &ipv6_hdr(skb)->daddr, +- 0, IPPROTO_TCP, 0); +- ipcse = 0; +- } +- ipcss = skb_network_offset(skb); +- ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; +- tucss = skb_transport_offset(skb); +- tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; +- tucse = 0; +- +- cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | +- E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); +- +- i = tx_ring->next_to_use; +- context_desc = E1000_CONTEXT_DESC(*tx_ring, i); +- buffer_info = &tx_ring->buffer_info[i]; +- +- context_desc->lower_setup.ip_fields.ipcss = ipcss; +- context_desc->lower_setup.ip_fields.ipcso = ipcso; +- context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); +- context_desc->upper_setup.tcp_fields.tucss = tucss; +- context_desc->upper_setup.tcp_fields.tucso = tucso; +- context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse); +- context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); +- context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; +- context_desc->cmd_and_length = cpu_to_le32(cmd_length); +- +- buffer_info->time_stamp = jiffies; +- buffer_info->next_to_watch = i; +- +- i++; +- if (i == tx_ring->count) +- i = 0; +- tx_ring->next_to_use = i; +- +- return 1; +- } +- +- return 0; ++ if (!skb_is_gso(skb)) ++ return 0; ++ ++ if (skb_header_cloned(skb)) { ++ err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); ++ if (err) ++ return err; ++ } ++ ++ hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); ++ mss = skb_shinfo(skb)->gso_size; ++ if (skb->protocol == htons(ETH_P_IP)) { ++ struct iphdr *iph = ip_hdr(skb); ++ iph->tot_len = 0; ++ iph->check = 0; ++ tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, ++ 0, IPPROTO_TCP, 0); ++ cmd_length = E1000_TXD_CMD_IP; ++ ipcse = skb_transport_offset(skb) - 1; ++#ifdef NETIF_F_TSO6 ++ } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { ++ ipv6_hdr(skb)->payload_len = 0; ++ tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, ++ &ipv6_hdr(skb)->daddr, ++ 0, IPPROTO_TCP, 0); ++ ipcse = 0; ++#endif ++ } ++ ipcss = skb_network_offset(skb); ++ ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; ++ tucss = skb_transport_offset(skb); ++ tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; ++ tucse = 0; ++ ++ cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | ++ E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); ++ ++ i = tx_ring->next_to_use; ++ context_desc = E1000_CONTEXT_DESC(*tx_ring, i); ++ buffer_info = &tx_ring->buffer_info[i]; ++ ++ context_desc->lower_setup.ip_fields.ipcss = ipcss; ++ context_desc->lower_setup.ip_fields.ipcso = ipcso; ++ context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); ++ context_desc->upper_setup.tcp_fields.tucss = tucss; ++ context_desc->upper_setup.tcp_fields.tucso = tucso; ++ context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse); ++ context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); ++ context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; ++ context_desc->cmd_and_length = cpu_to_le32(cmd_length); ++ ++ buffer_info->time_stamp = jiffies; ++ buffer_info->next_to_watch = i; ++ ++ i++; ++ if (i == tx_ring->count) ++ i = 0; ++ tx_ring->next_to_use = i; ++ ++ return 1; ++#else ++ return 0; ++#endif + } + + static bool e1000_tx_csum(struct e1000_adapter *adapter, struct sk_buff *skb) +@@ -3764,34 +4315,50 @@ + struct e1000_buffer *buffer_info; + unsigned int i; + u8 css; +- +- if (skb->ip_summed == CHECKSUM_PARTIAL) { +- css = skb_transport_offset(skb); +- +- i = tx_ring->next_to_use; +- buffer_info = &tx_ring->buffer_info[i]; +- context_desc = E1000_CONTEXT_DESC(*tx_ring, i); +- +- context_desc->lower_setup.ip_config = 0; +- context_desc->upper_setup.tcp_fields.tucss = css; +- context_desc->upper_setup.tcp_fields.tucso = +- css + skb->csum_offset; +- context_desc->upper_setup.tcp_fields.tucse = 0; +- context_desc->tcp_seg_setup.data = 0; +- context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT); +- +- buffer_info->time_stamp = jiffies; +- buffer_info->next_to_watch = i; +- +- i++; +- if (i == tx_ring->count) +- i = 0; +- tx_ring->next_to_use = i; +- +- return 1; +- } +- +- return 0; ++ u32 cmd_len = E1000_TXD_CMD_DEXT; ++ ++ if (skb->ip_summed != CHECKSUM_PARTIAL) ++ return 0; ++ ++ switch (skb->protocol) { ++ case __constant_htons(ETH_P_IP): ++ if (ip_hdr(skb)->protocol == IPPROTO_TCP) ++ cmd_len |= E1000_TXD_CMD_TCP; ++ break; ++ case __constant_htons(ETH_P_IPV6): ++ /* XXX not handling all IPV6 headers */ ++ if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) ++ cmd_len |= E1000_TXD_CMD_TCP; ++ break; ++ default: ++ if (unlikely(net_ratelimit())) ++ e_warn("checksum_partial proto=%x!\n", skb->protocol); ++ break; ++ } ++ ++ css = skb_transport_offset(skb); ++ ++ i = tx_ring->next_to_use; ++ buffer_info = &tx_ring->buffer_info[i]; ++ context_desc = E1000_CONTEXT_DESC(*tx_ring, i); ++ ++ context_desc->lower_setup.ip_config = 0; ++ context_desc->upper_setup.tcp_fields.tucss = css; ++ context_desc->upper_setup.tcp_fields.tucso = ++ css + skb->csum_offset; ++ context_desc->upper_setup.tcp_fields.tucse = 0; ++ context_desc->tcp_seg_setup.data = 0; ++ context_desc->cmd_and_length = cpu_to_le32(cmd_len); ++ ++ buffer_info->time_stamp = jiffies; ++ buffer_info->next_to_watch = i; ++ ++ i++; ++ if (i == tx_ring->count) ++ i = 0; ++ tx_ring->next_to_use = i; ++ ++ return 1; + } + + #define E1000_MAX_PER_TXD 8192 +@@ -3813,11 +4380,6 @@ + while (len) { + buffer_info = &tx_ring->buffer_info[i]; + size = min(len, max_per_txd); +- +- /* Workaround for premature desc write-backs +- * in TSO mode. Append 4-byte sentinel desc */ +- if (mss && !nr_frags && size == len && size > 8) +- size -= 4; + + buffer_info->length = size; + /* set time_stamp *before* dma to help avoid a possible race */ +@@ -3852,10 +4414,6 @@ + while (len) { + buffer_info = &tx_ring->buffer_info[i]; + size = min(len, max_per_txd); +- /* Workaround for premature desc write-backs +- * in TSO mode. Append 4-byte sentinel desc */ +- if (mss && f == (nr_frags-1) && size == len && size > 8) +- size -= 4; + + buffer_info->length = size; + buffer_info->time_stamp = jiffies; +@@ -4031,7 +4589,7 @@ + return __e1000_maybe_stop_tx(netdev, size); + } + +-#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 ) ++#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1) + static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) + { + struct e1000_adapter *adapter = netdev_priv(netdev); +@@ -4041,9 +4599,8 @@ + unsigned int max_txd_pwr = E1000_MAX_TXD_PWR; + unsigned int tx_flags = 0; + unsigned int len = skb->len - skb->data_len; +- unsigned long irq_flags; + unsigned int nr_frags; +- unsigned int mss; ++ unsigned int mss = 0; + int count = 0; + int tso; + unsigned int f; +@@ -4058,6 +4615,7 @@ + return NETDEV_TX_OK; + } + ++#ifdef NETIF_F_TSO + mss = skb_shinfo(skb)->gso_size; + /* + * The controller does a simple calculation to +@@ -4099,6 +4657,10 @@ + if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) + count++; + count++; ++#else ++ if (skb->ip_summed == CHECKSUM_PARTIAL) ++ count++; ++#endif + + count += TXD_USE_COUNT(len, max_txd_pwr); + +@@ -4110,16 +4672,12 @@ + if (adapter->hw.mac.tx_pkt_filtering) + e1000_transfer_dhcp_info(adapter, skb); + +- if (!spin_trylock_irqsave(&adapter->tx_queue_lock, irq_flags)) +- /* Collision - tell upper layer to requeue */ +- return NETDEV_TX_LOCKED; + + /* + * need: count + 2 desc gap to keep tail from touching + * head, otherwise try next time + */ + if (e1000_maybe_stop_tx(netdev, count + 2)) { +- spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags); + return NETDEV_TX_BUSY; + } + +@@ -4133,7 +4691,6 @@ + tso = e1000_tso(adapter, skb); + if (tso < 0) { + dev_kfree_skb_any(skb); +- spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags); + return NETDEV_TX_OK; + } + +@@ -4154,7 +4711,6 @@ + if (count < 0) { + /* handle pci_map_single() error in e1000_tx_map */ + dev_kfree_skb_any(skb); +- spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags); + return NETDEV_TX_OK; + } + +@@ -4165,7 +4721,6 @@ + /* Make sure there is space in the ring for the next send. */ + e1000_maybe_stop_tx(netdev, MAX_SKB_FRAGS + 2); + +- spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags); + return NETDEV_TX_OK; + } + +@@ -4217,27 +4772,17 @@ + struct e1000_adapter *adapter = netdev_priv(netdev); + int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; + ++ /* Jumbo frame support */ ++ if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) && ++ !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { ++ e_err("Jumbo Frames not supported.\n"); ++ return -EINVAL; ++ } ++ ++ /* Supported frame sizes */ + if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) || +- (max_frame > MAX_JUMBO_FRAME_SIZE)) { +- e_err("Invalid MTU setting\n"); +- return -EINVAL; +- } +- +- /* Jumbo frame size limits */ +- if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) { +- if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { +- e_err("Jumbo Frames not supported.\n"); +- return -EINVAL; +- } +- if (adapter->hw.phy.type == e1000_phy_ife) { +- e_err("Jumbo Frames not supported.\n"); +- return -EINVAL; +- } +- } +- +-#define MAX_STD_JUMBO_FRAME_SIZE 9234 +- if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { +- e_err("MTU > 9216 not supported.\n"); ++ (max_frame > adapter->max_hw_frame_size)) { ++ e_err("Unsupported MTU setting\n"); + return -EINVAL; + } + +@@ -4265,8 +4810,17 @@ + adapter->rx_buffer_len = 1024; + else if (max_frame <= 2048) + adapter->rx_buffer_len = 2048; ++#ifdef CONFIG_E1000E_NAPI + else + adapter->rx_buffer_len = 4096; ++#else ++ else if (max_frame <= 4096) ++ adapter->rx_buffer_len = 4096; ++ else if (max_frame <= 8192) ++ adapter->rx_buffer_len = 8192; ++ else if (max_frame <= 16384) ++ adapter->rx_buffer_len = 16384; ++#endif + + /* adjust allocation if LPE protects us, and we aren't using SBP */ + if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || +@@ -4352,9 +4906,88 @@ + case SIOCGMIIREG: + case SIOCSMIIREG: + return e1000_mii_ioctl(netdev, ifr, cmd); ++#ifdef ETHTOOL_OPS_COMPAT ++ case SIOCETHTOOL: ++ return ethtool_ioctl(ifr); ++#endif + default: + return -EOPNOTSUPP; + } ++} ++ ++static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u32 i, mac_reg; ++ u16 phy_reg; ++ int retval = 0; ++ ++ /* copy MAC RARs to PHY RARs */ ++ for (i = 0; i < adapter->hw.mac.rar_entry_count; i++) { ++ mac_reg = er32(RAL(i)); ++ e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF)); ++ e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF)); ++ mac_reg = er32(RAH(i)); ++ e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF)); ++ e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0xFFFF)); ++ } ++ ++ /* copy MAC MTA to PHY MTA */ ++ for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { ++ mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); ++ e1e_wphy(hw, BM_MTA(i), (u16)(mac_reg & 0xFFFF)); ++ e1e_wphy(hw, BM_MTA(i) + 1, (u16)((mac_reg >> 16) & 0xFFFF)); ++ } ++ ++ /* configure PHY Rx Control register */ ++ e1e_rphy(&adapter->hw, BM_RCTL, &phy_reg); ++ mac_reg = er32(RCTL); ++ if (mac_reg & E1000_RCTL_UPE) ++ phy_reg |= BM_RCTL_UPE; ++ if (mac_reg & E1000_RCTL_MPE) ++ phy_reg |= BM_RCTL_MPE; ++ phy_reg &= ~(BM_RCTL_MO_MASK); ++ if (mac_reg & E1000_RCTL_MO_3) ++ phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) ++ << BM_RCTL_MO_SHIFT); ++ if (mac_reg & E1000_RCTL_BAM) ++ phy_reg |= BM_RCTL_BAM; ++ if (mac_reg & E1000_RCTL_PMCF) ++ phy_reg |= BM_RCTL_PMCF; ++ mac_reg = er32(CTRL); ++ if (mac_reg & E1000_CTRL_RFCE) ++ phy_reg |= BM_RCTL_RFCE; ++ e1e_wphy(&adapter->hw, BM_RCTL, phy_reg); ++ ++ /* enable PHY wakeup in MAC register */ ++ ew32(WUFC, wufc); ++ ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN); ++ ++ /* configure and enable PHY wakeup in PHY registers */ ++ e1e_wphy(&adapter->hw, BM_WUFC, wufc); ++ e1e_wphy(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); ++ ++ /* activate PHY wakeup */ ++ retval = hw->phy.ops.acquire(hw); ++ if (retval) { ++ e_err("Could not acquire PHY\n"); ++ return retval; ++ } ++ e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, ++ (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); ++ retval = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); ++ if (retval) { ++ e_err("Could not read PHY page 769\n"); ++ goto out; ++ } ++ phy_reg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; ++ retval = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); ++ if (retval) ++ e_err("Could not set PHY Host Wakeup bit\n"); ++out: ++ hw->phy.ops.release(hw); ++ ++ return retval; + } + + static int e1000_suspend(struct pci_dev *pdev, pm_message_t state) +@@ -4373,7 +5006,9 @@ + e1000e_down(adapter); + e1000_free_irq(adapter); + } ++#ifdef CONFIG_E1000E_MSIX + e1000e_reset_interrupt_capability(adapter); ++#endif + + retval = pci_save_state(pdev); + if (retval) +@@ -4399,8 +5034,9 @@ + #define E1000_CTRL_ADVD3WUC 0x00100000 + /* phy power management enable */ + #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 +- ctrl |= E1000_CTRL_ADVD3WUC | +- E1000_CTRL_EN_PHY_PWR_MGMT; ++ ctrl |= E1000_CTRL_ADVD3WUC; ++ if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) ++ ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; + ew32(CTRL, ctrl); + + if (adapter->hw.phy.media_type == e1000_media_type_fiber || +@@ -4418,8 +5054,17 @@ + /* Allow time for pending master requests to run */ + e1000e_disable_pcie_master(&adapter->hw); + +- ew32(WUC, E1000_WUC_PME_EN); +- ew32(WUFC, wufc); ++ if ((adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) && ++ !(hw->mac.ops.check_mng_mode(hw))) { ++ /* enable wakeup by the PHY */ ++ retval = e1000_init_phy_wakeup(adapter, wufc); ++ if (retval) ++ return retval; ++ } else { ++ /* enable wakeup by the MAC */ ++ ew32(WUFC, wufc); ++ ew32(WUC, E1000_WUC_PME_EN); ++ } + pci_enable_wake(pdev, PCI_D3hot, 1); + pci_enable_wake(pdev, PCI_D3cold, 1); + } else { +@@ -4446,7 +5091,27 @@ + + pci_disable_device(pdev); + +- pci_set_power_state(pdev, pci_choose_state(pdev, state)); ++ /* ++ * The pci-e switch on some quad port adapters will report a ++ * correctable error when the MAC transitions from D0 to D3. To ++ * prevent this we need to mask off the correctable errors on the ++ * downstream port of the pci-e switch. ++ */ ++ if (adapter->flags & FLAG_IS_QUAD_PORT) { ++ struct pci_dev *us_dev = pdev->bus->self; ++ int pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP); ++ u16 devctl; ++ ++ pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl); ++ pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, ++ (devctl & ~PCI_EXP_DEVCTL_CERE)); ++ ++ pci_set_power_state(pdev, pci_choose_state(pdev, state)); ++ ++ pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl); ++ } else { ++ pci_set_power_state(pdev, pci_choose_state(pdev, state)); ++ } + + return 0; + } +@@ -4495,12 +5160,22 @@ + return err; + } + ++ /* AER (Advanced Error Reporting) hooks */ ++ err = pci_enable_pcie_error_reporting(pdev); ++ if (err) { ++ dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " ++ "0x%x\n", err); ++ /* non-fatal, continue */ ++ } ++ + pci_set_master(pdev); + + pci_enable_wake(pdev, PCI_D3hot, 0); + pci_enable_wake(pdev, PCI_D3cold, 0); + ++#ifdef CONFIG_E1000E_MSIX + e1000e_set_interrupt_capability(adapter); ++#endif + if (netif_running(netdev)) { + err = e1000_request_irq(adapter); + if (err) +@@ -4508,8 +5183,37 @@ + } + + e1000e_power_up_phy(adapter); ++ ++ /* report the system wakeup cause from S3/S4 */ ++ if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { ++ u16 phy_data; ++ ++ e1e_rphy(&adapter->hw, BM_WUS, &phy_data); ++ if (phy_data) { ++ e_info("PHY Wakeup cause - %s\n", ++ phy_data & E1000_WUS_EX ? "Unicast Packet" : ++ phy_data & E1000_WUS_MC ? "Multicast Packet" : ++ phy_data & E1000_WUS_BC ? "Broadcast Packet" : ++ phy_data & E1000_WUS_MAG ? "Magic Packet" : ++ phy_data & E1000_WUS_LNKC ? "Link Status " ++ " Change" : "other"); ++ } ++ e1e_wphy(&adapter->hw, BM_WUS, ~0); ++ } else { ++ u32 wus = er32(WUS); ++ if (wus) { ++ e_info("MAC Wakeup cause - %s\n", ++ wus & E1000_WUS_EX ? "Unicast Packet" : ++ wus & E1000_WUS_MC ? "Multicast Packet" : ++ wus & E1000_WUS_BC ? "Broadcast Packet" : ++ wus & E1000_WUS_MAG ? "Magic Packet" : ++ wus & E1000_WUS_LNKC ? "Link Status Change" : ++ "other"); ++ } ++ ew32(WUS, ~0); ++ } ++ + e1000e_reset(adapter); +- ew32(WUS, ~0); + + e1000_init_manageability(adapter); + +@@ -4530,10 +5234,37 @@ + } + #endif + ++#ifndef USE_REBOOT_NOTIFIER + static void e1000_shutdown(struct pci_dev *pdev) + { + e1000_suspend(pdev, PMSG_SUSPEND); + } ++#else ++static struct pci_driver e1000_driver; ++static int e1000_notify_reboot(struct notifier_block *nb, unsigned long event, ++ void *ptr) ++{ ++ struct pci_dev *pdev = NULL; ++ ++ switch (event) { ++ case SYS_DOWN: ++ case SYS_HALT: ++ case SYS_POWER_OFF: ++ while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev))) { ++ if (pci_dev_driver(pdev) == &e1000_driver) ++ e1000_suspend(pdev, PMSG_SUSPEND); ++ } ++ break; ++ } ++ return NOTIFY_DONE; ++} ++ ++static struct notifier_block e1000_notifier_reboot = { ++ .notifier_call = e1000_notify_reboot, ++ .next = NULL, ++ .priority = 0 ++}; ++#endif + + #ifdef CONFIG_NET_POLL_CONTROLLER + /* +@@ -4548,10 +5279,15 @@ + disable_irq(adapter->pdev->irq); + e1000_intr(adapter->pdev->irq, netdev); + ++#ifndef CONFIG_E1000E_NAPI ++ adapter->clean_rx(adapter); ++ ++#endif + enable_irq(adapter->pdev->irq); + } + #endif + ++#ifdef HAVE_PCI_ERS + /** + * e1000_io_error_detected - called when PCI error is detected + * @pdev: Pointer to PCI device +@@ -4589,24 +5325,29 @@ + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; + int err; ++ pci_ers_result_t result; + + e1000e_disable_l1aspm(pdev); + err = pci_enable_device_mem(pdev); + if (err) { + dev_err(&pdev->dev, + "Cannot re-enable PCI device after reset.\n"); +- return PCI_ERS_RESULT_DISCONNECT; +- } +- pci_set_master(pdev); +- pci_restore_state(pdev); +- +- pci_enable_wake(pdev, PCI_D3hot, 0); +- pci_enable_wake(pdev, PCI_D3cold, 0); +- +- e1000e_reset(adapter); +- ew32(WUS, ~0); +- +- return PCI_ERS_RESULT_RECOVERED; ++ result = PCI_ERS_RESULT_DISCONNECT; ++ } else { ++ pci_set_master(pdev); ++ pci_restore_state(pdev); ++ ++ pci_enable_wake(pdev, PCI_D3hot, 0); ++ pci_enable_wake(pdev, PCI_D3cold, 0); ++ ++ e1000e_reset(adapter); ++ ew32(WUS, ~0); ++ result = PCI_ERS_RESULT_RECOVERED; ++ } ++ ++ pci_cleanup_aer_uncorrect_error_status(pdev); ++ ++ return result; + } + + /** +@@ -4643,6 +5384,7 @@ + e1000_get_hw_control(adapter); + + } ++#endif /* HAVE_PCI_ERS */ + + static void e1000_print_device_info(struct e1000_adapter *adapter) + { +@@ -4656,9 +5398,9 @@ + ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : + "Width x1"), + /* MAC address */ +- netdev->dev_addr[0], netdev->dev_addr[1], +- netdev->dev_addr[2], netdev->dev_addr[3], +- netdev->dev_addr[4], netdev->dev_addr[5]); ++ netdev->dev_addr[0], netdev->dev_addr[1], ++ netdev->dev_addr[2], netdev->dev_addr[3], ++ netdev->dev_addr[4], netdev->dev_addr[5]); + e_info("Intel(R) PRO/%s Network Connection\n", + (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); + e1000e_read_pba_num(hw, &pba_num); +@@ -4671,27 +5413,67 @@ + struct e1000_hw *hw = &adapter->hw; + int ret_val; + u16 buf = 0; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) ++ struct pci_dev *pdev = adapter->pdev; ++#endif + + if (hw->mac.type != e1000_82573) + return; + + ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); +- if (!(le16_to_cpu(buf) & (1 << 0))) { ++ if (!ret_val && (!(le16_to_cpu(buf) & (1 << 0)))) { + /* Deep Smart Power Down (DSPD) */ +- e_warn("Warning: detected DSPD enabled in EEPROM\n"); ++ dev_warn(&adapter->pdev->dev, ++ "Warning: detected DSPD enabled in EEPROM\n"); + } + + ret_val = e1000_read_nvm(hw, NVM_INIT_3GIO_3, 1, &buf); +- if (le16_to_cpu(buf) & (3 << 2)) { ++ if (!ret_val && (le16_to_cpu(buf) & (3 << 2))) { + /* ASPM enable */ +- e_warn("Warning: detected ASPM enabled in EEPROM\n"); +- } +-} +- ++ dev_warn(&adapter->pdev->dev, ++ "Warning: detected ASPM enabled in EEPROM\n"); ++ } ++} ++ ++s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) ++{ ++ u16 cap_offset; ++ ++ cap_offset = pci_find_capability(hw->adapter->pdev, PCI_CAP_ID_EXP); ++ if (!cap_offset) ++ return -E1000_ERR_CONFIG; ++ ++ pci_read_config_word(hw->adapter->pdev, cap_offset + reg, value); ++ ++ return E1000_SUCCESS; ++} ++ ++#ifdef HAVE_NET_DEVICE_OPS ++static const struct net_device_ops e1000e_netdev_ops = { ++ .ndo_open = e1000_open, ++ .ndo_stop = e1000_close, ++ .ndo_start_xmit = e1000_xmit_frame, ++ .ndo_get_stats = e1000_get_stats, ++ .ndo_set_multicast_list = e1000_set_multi, ++ .ndo_set_mac_address = e1000_set_mac, ++ .ndo_change_mtu = e1000_change_mtu, ++ .ndo_do_ioctl = e1000_ioctl, ++ .ndo_tx_timeout = e1000_tx_timeout, ++ .ndo_validate_addr = eth_validate_addr, ++ ++ .ndo_vlan_rx_register = e1000_vlan_rx_register, ++ .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, ++ .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = e1000_netpoll, ++#endif ++}; ++ ++#endif /* HAVE_NET_DEVICE_OPS */ + /** + * e1000_probe - Device Initialization Routine + * @pdev: PCI device information struct +- * @ent: entry in e1000_pci_tbl ++ * @ent: entry in e1000e_pci_tbl + * + * Returns 0 on success, negative on failure + * +@@ -4706,9 +5488,6 @@ + struct e1000_adapter *adapter; + struct e1000_hw *hw; + const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; +- resource_size_t mmio_start, mmio_len; +- resource_size_t flash_start, flash_len; +- + static int cards_found; + int i, err, pci_using_dac; + u16 eeprom_data = 0; +@@ -4721,38 +5500,39 @@ + return err; + + pci_using_dac = 0; +- err = pci_set_dma_mask(pdev, DMA_64BIT_MASK); ++ err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); + if (!err) { +- err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); ++ err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); + if (!err) + pci_using_dac = 1; + } else { +- err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); ++ err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + if (err) { + err = pci_set_consistent_dma_mask(pdev, +- DMA_32BIT_MASK); ++ DMA_BIT_MASK(32)); + if (err) { +- dev_err(&pdev->dev, "No usable DMA " +- "configuration, aborting\n"); ++ printk(KERN_ERR "%s: No usable DMA " ++ "configuration, aborting\n", ++ pci_name(pdev)); + goto err_dma; + } + } + } + +- err = pci_request_selected_regions(pdev, ++ err = pci_request_selected_regions_exclusive(pdev, + pci_select_bars(pdev, IORESOURCE_MEM), + e1000e_driver_name); + if (err) + goto err_pci_reg; + + pci_set_master(pdev); +- pci_save_state(pdev); + + err = -ENOMEM; + netdev = alloc_etherdev(sizeof(struct e1000_adapter)); + if (!netdev) + goto err_alloc_etherdev; + ++ SET_MODULE_OWNER(netdev); + SET_NETDEV_DEV(netdev, &pdev->dev); + + pci_set_drvdata(pdev, netdev); +@@ -4766,26 +5546,48 @@ + adapter->flags2 = ei->flags2; + adapter->hw.adapter = adapter; + adapter->hw.mac.type = ei->mac; ++ adapter->max_hw_frame_size = ei->max_hw_frame_size; + adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1; + +- mmio_start = pci_resource_start(pdev, 0); +- mmio_len = pci_resource_len(pdev, 0); ++ /* PCI config space info */ ++ hw->device_id = pdev->device; ++#ifdef HAVE_PCI_ERS ++ err = pci_save_state(pdev); ++ if (err) ++ goto err_ioremap; ++#endif + + err = -EIO; +- adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); ++ adapter->hw.hw_addr = pci_ioremap_bar(pdev, 0); + if (!adapter->hw.hw_addr) + goto err_ioremap; + + if ((adapter->flags & FLAG_HAS_FLASH) && + (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { +- flash_start = pci_resource_start(pdev, 1); +- flash_len = pci_resource_len(pdev, 1); +- adapter->hw.flash_address = ioremap(flash_start, flash_len); ++ adapter->hw.flash_address = pci_ioremap_bar(pdev, 1); + if (!adapter->hw.flash_address) + goto err_flashmap; + } + ++ adapter->bd_number = cards_found++; ++ ++ e1000e_check_options(adapter); ++ ++ /* setup adapter struct */ ++ err = e1000_sw_init(adapter); ++ if (err) ++ goto err_sw_init; ++ ++ if (ei->get_variants) { ++ err = ei->get_variants(adapter); ++ if (err) ++ goto err_hw_init; ++ } ++ + /* construct the net_device struct */ ++#ifdef HAVE_NET_DEVICE_OPS ++ netdev->netdev_ops = &e1000e_netdev_ops; ++#else + netdev->open = &e1000_open; + netdev->stop = &e1000_close; + netdev->hard_start_xmit = &e1000_xmit_frame; +@@ -4794,43 +5596,20 @@ + netdev->set_mac_address = &e1000_set_mac; + netdev->change_mtu = &e1000_change_mtu; + netdev->do_ioctl = &e1000_ioctl; +- e1000e_set_ethtool_ops(netdev); + netdev->tx_timeout = &e1000_tx_timeout; +- netdev->watchdog_timeo = 5 * HZ; +- netif_napi_add(netdev, &adapter->napi, e1000_clean, 64); + netdev->vlan_rx_register = e1000_vlan_rx_register; + netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid; + netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid; + #ifdef CONFIG_NET_POLL_CONTROLLER + netdev->poll_controller = e1000_netpoll; + #endif ++#endif /* HAVE_NET_DEVICE_OPS */ ++ e1000e_set_ethtool_ops(netdev); ++ netdev->watchdog_timeo = 5 * HZ; ++#ifdef CONFIG_E1000E_NAPI ++ netif_napi_add(netdev, &adapter->napi, e1000_poll, 64); ++#endif + strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); +- +- netdev->mem_start = mmio_start; +- netdev->mem_end = mmio_start + mmio_len; +- +- adapter->bd_number = cards_found++; +- +- e1000e_check_options(adapter); +- +- /* setup adapter struct */ +- err = e1000_sw_init(adapter); +- if (err) +- goto err_sw_init; +- +- err = -EIO; +- +- memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); +- memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); +- memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); +- +- err = ei->get_variants(adapter); +- if (err) +- goto err_hw_init; +- +- if ((adapter->flags & FLAG_IS_ICH) && +- (adapter->flags & FLAG_READ_ONLY_NVM)) +- e1000e_write_protect_nvm_ich8lan(&adapter->hw); + + hw->mac.ops.get_bus_info(&adapter->hw); + +@@ -4854,22 +5633,16 @@ + if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) + netdev->features |= NETIF_F_HW_VLAN_FILTER; + ++#ifdef NETIF_F_TSO + netdev->features |= NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 + netdev->features |= NETIF_F_TSO6; +- +- netdev->vlan_features |= NETIF_F_TSO; +- netdev->vlan_features |= NETIF_F_TSO6; +- netdev->vlan_features |= NETIF_F_HW_CSUM; +- netdev->vlan_features |= NETIF_F_SG; ++#endif ++#endif + + if (pci_using_dac) + netdev->features |= NETIF_F_HIGHDMA; + +- /* +- * We should not be using LLTX anymore, but we are still Tx faster with +- * it. +- */ +- netdev->features |= NETIF_F_LLTX; + + if (e1000e_enable_mng_pass_thru(&adapter->hw)) + adapter->flags |= FLAG_MNG_PT_ENABLED; +@@ -4901,13 +5674,17 @@ + e_err("NVM Read Error while reading MAC address\n"); + + memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); ++#ifdef ETHTOOL_GPERMADDR + memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len); + + if (!is_valid_ether_addr(netdev->perm_addr)) { ++#else ++ if (!is_valid_ether_addr(netdev->dev_addr)) { ++#endif + e_err("Invalid MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n", +- netdev->perm_addr[0], netdev->perm_addr[1], +- netdev->perm_addr[2], netdev->perm_addr[3], +- netdev->perm_addr[4], netdev->perm_addr[5]); ++ netdev->dev_addr[0], netdev->dev_addr[1], ++ netdev->dev_addr[2], netdev->dev_addr[3], ++ netdev->dev_addr[4], netdev->dev_addr[5]); + err = -EIO; + goto err_eeprom; + } +@@ -4928,8 +5705,14 @@ + /* Initialize link parameters. User can change them with ethtool */ + adapter->hw.mac.autoneg = 1; + adapter->fc_autoneg = 1; +- adapter->hw.fc.original_type = e1000_fc_default; +- adapter->hw.fc.type = e1000_fc_default; ++ if (adapter->hw.mac.type == e1000_pchlan) { ++ /* Workaround h/w hang when Tx flow control enabled */ ++ adapter->hw.fc.requested_mode = e1000_fc_rx_pause; ++ adapter->hw.fc.current_mode = e1000_fc_rx_pause; ++ } else { ++ adapter->hw.fc.requested_mode = e1000_fc_default; ++ adapter->hw.fc.current_mode = e1000_fc_default; ++ } + adapter->hw.phy.autoneg_advertised = 0x2f; + + /* ring size defaults */ +@@ -4944,14 +5727,16 @@ + /* APME bit in EEPROM is mapped to WUC.APME */ + eeprom_data = er32(WUC); + eeprom_apme_mask = E1000_WUC_APME; ++ if (eeprom_data & E1000_WUC_PHY_WAKE) ++ adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; + } else if (adapter->flags & FLAG_APME_IN_CTRL3) { + if (adapter->flags & FLAG_APME_CHECK_PORT_B && + (adapter->hw.bus.func == 1)) +- e1000_read_nvm(&adapter->hw, +- NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); ++ e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B, ++ 1, &eeprom_data); + else +- e1000_read_nvm(&adapter->hw, +- NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); ++ e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A, ++ 1, &eeprom_data); + } + + /* fetch WoL from EEPROM */ +@@ -4969,6 +5754,9 @@ + /* initialize the wol settings based on the eeprom settings */ + adapter->wol = adapter->eeprom_wol; + device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); ++ ++ /* save off EEPROM version number */ ++ e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); + + /* reset the hardware with the new settings */ + e1000e_reset(adapter); +@@ -5001,10 +5789,12 @@ + if (!e1000_check_reset_block(&adapter->hw)) + e1000_phy_hw_reset(&adapter->hw); + err_hw_init: +- + kfree(adapter->tx_ring); + kfree(adapter->rx_ring); + err_sw_init: ++#ifdef CONFIG_E1000E_MSIX ++ e1000e_reset_interrupt_capability(adapter); ++#endif /* CONFIG_E1000E_MSIX */ + if (adapter->hw.flash_address) + iounmap(adapter->hw.flash_address); + err_flashmap: +@@ -5055,7 +5845,9 @@ + if (!e1000_check_reset_block(&adapter->hw)) + e1000_phy_hw_reset(&adapter->hw); + ++#ifdef CONFIG_E1000E_MSIX + e1000e_reset_interrupt_capability(adapter); ++#endif /* CONFIG_E1000E_MSIX */ + kfree(adapter->tx_ring); + kfree(adapter->rx_ring); + +@@ -5067,17 +5859,22 @@ + + free_netdev(netdev); + ++ /* AER disable */ ++ pci_disable_pcie_error_reporting(pdev); ++ + pci_disable_device(pdev); + } + ++#ifdef HAVE_PCI_ERS + /* PCI Error Recovery (ERS) */ + static struct pci_error_handlers e1000_err_handler = { + .error_detected = e1000_io_error_detected, + .slot_reset = e1000_io_slot_reset, + .resume = e1000_io_resume, + }; +- +-static struct pci_device_id e1000_pci_tbl[] = { ++#endif ++ ++static struct pci_device_id e1000e_pci_tbl[] = { + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, +@@ -5098,6 +5895,8 @@ + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, + + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, + + { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), + board_80003es2lan }, +@@ -5133,14 +5932,19 @@ + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, + ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, ++ + { } /* terminate list */ + }; +-MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); ++MODULE_DEVICE_TABLE(pci, e1000e_pci_tbl); + + /* PCI Device API Driver */ + static struct pci_driver e1000_driver = { + .name = e1000e_driver_name, +- .id_table = e1000_pci_tbl, ++ .id_table = e1000e_pci_tbl, + .probe = e1000_probe, + .remove = __devexit_p(e1000_remove), + #ifdef CONFIG_PM +@@ -5148,8 +5952,12 @@ + .suspend = e1000_suspend, + .resume = e1000_resume, + #endif ++#ifndef USE_REBOOT_NOTIFIER + .shutdown = e1000_shutdown, ++#endif ++#ifdef HAVE_PCI_ERS + .err_handler = &e1000_err_handler ++#endif + }; + + /** +@@ -5163,12 +5971,14 @@ + int ret; + printk(KERN_INFO "%s: Intel(R) PRO/1000 Network Driver - %s\n", + e1000e_driver_name, e1000e_driver_version); +- printk(KERN_INFO "%s: Copyright (c) 1999-2008 Intel Corporation.\n", ++ printk(KERN_INFO "%s: Copyright(c) 1999 - 2009 Intel Corporation.\n", + e1000e_driver_name); + ret = pci_register_driver(&e1000_driver); +- pm_qos_add_requirement(PM_QOS_CPU_DMA_LATENCY, e1000e_driver_name, +- PM_QOS_DEFAULT_VALUE); +- ++#ifdef USE_REBOOT_NOTIFIER ++ if (ret >= 0) ++ register_reboot_notifier(&e1000_notifier_reboot); ++#endif ++ + return ret; + } + module_init(e1000_init_module); +@@ -5181,8 +5991,10 @@ + **/ + static void __exit e1000_exit_module(void) + { ++#ifdef USE_REBOOT_NOTIFIER ++ unregister_reboot_notifier(&e1000_notifier_reboot); ++#endif + pci_unregister_driver(&e1000_driver); +- pm_qos_remove_requirement(PM_QOS_CPU_DMA_LATENCY, e1000e_driver_name); + } + module_exit(e1000_exit_module); + +@@ -5192,4 +6004,4 @@ + MODULE_LICENSE("GPL"); + MODULE_VERSION(DRV_VERSION); + +-/* e1000_main.c */ ++/* netdev.c */ +diff -r 5638ec0574f5 drivers/net/e1000e/param.c +--- a/drivers/net/e1000e/param.c Tue Sep 01 13:47:57 2009 +0100 ++++ b/drivers/net/e1000e/param.c Tue Sep 01 13:48:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel PRO/1000 Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -27,7 +27,6 @@ + *******************************************************************************/ + + #include +-#include + + #include "e1000.h" + +@@ -55,12 +54,29 @@ + */ + + #define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET } ++#ifndef module_param_array ++/* Module Parameters are always initialized to -1, so that the driver ++ * can tell the difference between no user specified value or the ++ * user asking for the default value. ++ * The true default values are loaded in when e1000e_check_options is called. ++ * ++ * This is a GCC extension to ANSI C. ++ * See the item "Labeled Elements in Initializers" in the section ++ * "Extensions to the C Language Family" of the GCC documentation. ++ */ ++#define E1000_PARAM(X, desc) \ ++ static const int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \ ++ static unsigned int num_##X; \ ++ MODULE_PARM(X, "1-" __MODULE_STRING(E1000_MAX_NIC) "i"); \ ++ MODULE_PARM_DESC(X, desc); ++#else + #define E1000_PARAM(X, desc) \ + static int __devinitdata X[E1000_MAX_NIC+1] \ + = E1000_PARAM_INIT; \ + static unsigned int num_##X; \ + module_param_array_named(X, X, int, &num_##X, 0); \ + MODULE_PARM_DESC(X, desc); ++#endif + + + /* +@@ -114,6 +130,8 @@ + #define DEFAULT_ITR 3 + #define MAX_ITR 100000 + #define MIN_ITR 100 ++ ++#ifdef CONFIG_E1000E_MSIX + /* IntMode (Interrupt Mode) + * + * Valid Range: 0 - 2 +@@ -124,6 +142,7 @@ + #define MAX_INTMODE 2 + #define MIN_INTMODE 0 + ++#endif /* CONFIG_E1000E_MSIX */ + /* + * Enable Smart Power Down of the PHY + * +@@ -141,15 +160,6 @@ + * Default Value: 1 (enabled) + */ + E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround"); +- +-/* +- * Write Protect NVM +- * +- * Valid Range: 0, 1 +- * +- * Default Value: 1 (enabled) +- */ +-E1000_PARAM(WriteProtectNVM, "Write-protect NVM [WARNING: disabling this can lead to corrupted NVM]"); + + /* + * Enable CRC Stripping +@@ -380,6 +390,7 @@ + adapter->itr = 20000; + } + } ++#ifdef CONFIG_E1000E_MSIX + { /* Interrupt Mode */ + struct e1000_option opt = { + .type = range_option, +@@ -398,6 +409,7 @@ + adapter->int_mode = opt.def; + } + } ++#endif /* CONFIG_E1000E_MSIX */ + { /* Smart Power Down */ + const struct e1000_option opt = { + .type = enable_option, +@@ -418,7 +430,7 @@ + const struct e1000_option opt = { + .type = enable_option, + .name = "CRC Stripping", +- .err = "defaulting to enabled", ++ .err = "defaulting to Enabled", + .def = OPTION_ENABLED + }; + +@@ -427,6 +439,8 @@ + e1000_validate_option(&crc_stripping, &opt, adapter); + if (crc_stripping == OPTION_ENABLED) + adapter->flags2 |= FLAG2_CRC_STRIPPING; ++ } else { ++ adapter->flags2 |= FLAG2_CRC_STRIPPING; + } + } + { /* Kumeran Lock Loss Workaround */ +@@ -449,25 +463,4 @@ + opt.def); + } + } +- { /* Write-protect NVM */ +- const struct e1000_option opt = { +- .type = enable_option, +- .name = "Write-protect NVM", +- .err = "defaulting to Enabled", +- .def = OPTION_ENABLED +- }; +- +- if (adapter->flags & FLAG_IS_ICH) { +- if (num_WriteProtectNVM > bd) { +- unsigned int write_protect_nvm = WriteProtectNVM[bd]; +- e1000_validate_option(&write_protect_nvm, &opt, +- adapter); +- if (write_protect_nvm) +- adapter->flags |= FLAG_READ_ONLY_NVM; +- } else { +- if (opt.def) +- adapter->flags |= FLAG_READ_ONLY_NVM; +- } +- } +- } + } +diff -r 5638ec0574f5 drivers/net/e1000e/phy.c +--- a/drivers/net/e1000e/phy.c Tue Sep 01 13:47:57 2009 +0100 ++++ b/drivers/net/e1000e/phy.c Tue Sep 01 13:48:50 2009 +0100 +@@ -1886,11 +1886,282 @@ + case BME1000_E_PHY_ID_R2: + phy_type = e1000_phy_bm; + break; ++ case BME1000_E_PHY_ID: ++ case BME1000_E_PHY_ID_R2: ++ phy_type = e1000_phy_bm; ++ break; + default: + phy_type = e1000_phy_unknown; + break; + } + return phy_type; ++} ++ ++/** ++ * e1000e_determine_phy_address - Determines PHY address. ++ * @hw: pointer to the HW structure ++ * ++ * This uses a trial and error method to loop through possible PHY ++ * addresses. It tests each by reading the PHY ID registers and ++ * checking for a match. ++ **/ ++s32 e1000e_determine_phy_address(struct e1000_hw *hw) ++{ ++ s32 ret_val = -E1000_ERR_PHY_TYPE; ++ u32 phy_addr= 0; ++ u32 i = 0; ++ enum e1000_phy_type phy_type = e1000_phy_unknown; ++ ++ do { ++ for (phy_addr = 0; phy_addr < 4; phy_addr++) { ++ hw->phy.addr = phy_addr; ++ e1000e_get_phy_id(hw); ++ phy_type = e1000e_get_phy_type_from_id(hw->phy.id); ++ ++ /* ++ * If phy_type is valid, break - we found our ++ * PHY address ++ */ ++ if (phy_type != e1000_phy_unknown) { ++ ret_val = 0; ++ break; ++ } ++ } ++ i++; ++ } while ((ret_val != 0) && (i < 100)); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address ++ * @page: page to access ++ * ++ * Returns the phy address for the page requested. ++ **/ ++static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) ++{ ++ u32 phy_addr = 2; ++ ++ if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) ++ phy_addr = 1; ++ ++ return phy_addr; ++} ++ ++/** ++ * e1000e_write_phy_reg_bm - Write BM PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary, then writes the data to PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ s32 ret_val; ++ u32 page_select = 0; ++ u32 page = offset >> IGP_PAGE_SHIFT; ++ u32 page_shift = 0; ++ ++ /* Page 800 works differently than the rest so it has its own func */ ++ if (page == BM_WUC_PAGE) { ++ ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, ++ FALSE); ++ goto out; ++ } ++ ++ ret_val = hw->phy.ops.acquire_phy(hw); ++ if (ret_val) ++ goto out; ++ ++ hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ /* ++ * Page select is register 31 for phy address 1 and 22 for ++ * phy address 2 and 3. Page select is shifted only for ++ * phy address 1. ++ */ ++ if (hw->phy.addr == 1) { ++ page_shift = IGP_PAGE_SHIFT; ++ page_select = IGP01E1000_PHY_PAGE_SELECT; ++ } else { ++ page_shift = 0; ++ page_select = BM_PHY_PAGE_SELECT; ++ } ++ ++ /* Page is shifted left, PHY expects (page x 32) */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, page_select, ++ (page << page_shift)); ++ if (ret_val) { ++ hw->phy.ops.release_phy(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release_phy(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000e_read_phy_reg_bm - Read BM PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retrieved information in data. Release any acquired ++ * semaphores before exiting. ++ **/ ++s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ s32 ret_val; ++ u32 page_select = 0; ++ u32 page = offset >> IGP_PAGE_SHIFT; ++ u32 page_shift = 0; ++ ++ /* Page 800 works differently than the rest so it has its own func */ ++ if (page == BM_WUC_PAGE) { ++ ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, ++ TRUE); ++ goto out; ++ } ++ ++ ret_val = hw->phy.ops.acquire_phy(hw); ++ if (ret_val) ++ goto out; ++ ++ hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ /* ++ * Page select is register 31 for phy address 1 and 22 for ++ * phy address 2 and 3. Page select is shifted only for ++ * phy address 1. ++ */ ++ if (hw->phy.addr == 1) { ++ page_shift = IGP_PAGE_SHIFT; ++ page_select = IGP01E1000_PHY_PAGE_SELECT; ++ } else { ++ page_shift = 0; ++ page_select = BM_PHY_PAGE_SELECT; ++ } ++ ++ /* Page is shifted left, PHY expects (page x 32) */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, page_select, ++ (page << page_shift)); ++ if (ret_val) { ++ hw->phy.ops.release_phy(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ hw->phy.ops.release_phy(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read or written ++ * @data: pointer to the data to read or write ++ * @read: determines if operation is read or write ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retrieved information in data. Release any acquired ++ * semaphores before exiting. Note that procedure to read the wakeup ++ * registers are different. It works as such: ++ * 1) Set page 769, register 17, bit 2 = 1 ++ * 2) Set page to 800 for host (801 if we were manageability) ++ * 3) Write the address using the address opcode (0x11) ++ * 4) Read or write the data using the data opcode (0x12) ++ * 5) Restore 769_17.2 to its original value ++ **/ ++static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, ++ u16 *data, bool read) ++{ ++ s32 ret_val; ++ u16 reg = ((u16)offset) & PHY_REG_MASK; ++ u16 phy_reg = 0; ++ u8 phy_acquired = 1; ++ ++ ++ ret_val = hw->phy.ops.acquire_phy(hw); ++ if (ret_val) { ++ phy_acquired = 0; ++ goto out; ++ } ++ ++ /* All operations in this function are phy address 1 */ ++ hw->phy.addr = 1; ++ ++ /* Set page 769 */ ++ e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, ++ (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); ++ ++ ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); ++ if (ret_val) ++ goto out; ++ ++ /* First clear bit 4 to avoid a power state change */ ++ phy_reg &= ~(BM_WUC_HOST_WU_BIT); ++ ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); ++ if (ret_val) ++ goto out; ++ ++ /* Write bit 2 = 1, and clear bit 4 to 769_17 */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, ++ phy_reg | BM_WUC_ENABLE_BIT); ++ if (ret_val) ++ goto out; ++ ++ /* Select page 800 */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, ++ (BM_WUC_PAGE << IGP_PAGE_SHIFT)); ++ ++ /* Write the page 800 offset value using opcode 0x11 */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); ++ if (ret_val) ++ goto out; ++ ++ if (read) { ++ /* Read the page 800 value using opcode 0x12 */ ++ ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, ++ data); ++ } else { ++ /* Read the page 800 value using opcode 0x12 */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, ++ *data); ++ } ++ ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Restore 769_17.2 to its original value ++ * Set page 769 ++ */ ++ e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, ++ (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); ++ ++ /* Clear 769_17.2 */ ++ ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); ++ ++out: ++ if (phy_acquired == 1) ++ hw->phy.ops.release_phy(hw); ++ return ret_val; + } + + /** diff --git a/master/feature-gso-tcpv4-prefix b/master/feature-gso-tcpv4-prefix index 17d717d..c81a86f 100644 --- a/master/feature-gso-tcpv4-prefix +++ b/master/feature-gso-tcpv4-prefix @@ -117,7 +117,7 @@ diff -r 2e19d0030606 drivers/xen/netback/netback.c + if (skb->ip_summed == CHECKSUM_PARTIAL) /* local packet? */ flags |= NETRXF_csum_blank | NETRXF_data_validated; - else if (skb->proto_data_valid) /* remote but checksummed? */ + else if (skb->ip_summed == CHECKSUM_UNNECESSARY) /* remote but checksummed? */ flags |= NETRXF_data_validated; if (meta[npo.meta_cons].copy) diff --git a/master/git-3c598766a2bae1b208470e7cc934ac462561e3cb.patch b/master/git-3c598766a2bae1b208470e7cc934ac462561e3cb.patch new file mode 100644 index 0000000..f68e110 --- /dev/null +++ b/master/git-3c598766a2bae1b208470e7cc934ac462561e3cb.patch @@ -0,0 +1,48 @@ +commit 3c598766a2bae1b208470e7cc934ac462561e3cb +Author: Jan Beulich +Date: Mon May 11 16:49:28 2009 +0100 + + x86: fix percpu_{to,from}_op() + + - the byte operand constraints were wrong for 32-bit + - the to-op's input operands weren't properly parenthesized + + [ Impact: fix possible miscompilation or build failure ] + + Signed-off-by: Jan Beulich + Signed-off-by: H. Peter Anvin + +diff --git a/include/asm-x86/percpu.h b/include/asm-x86/percpu.h +index aee103b..02ecb30 100644 +--- a/include/asm-x86/percpu.h ++++ b/include/asm-x86/percpu.h +@@ -82,17 +82,17 @@ do { \ + case 1: \ + asm(op "b %1,"__percpu_seg"%0" \ + : "+m" (var) \ +- : "ri" ((T__)val)); \ ++ : "qi" ((T__)(val))); \ + break; \ + case 2: \ + asm(op "w %1,"__percpu_seg"%0" \ + : "+m" (var) \ +- : "ri" ((T__)val)); \ ++ : "ri" ((T__)(val))); \ + break; \ + case 4: \ + asm(op "l %1,"__percpu_seg"%0" \ + : "+m" (var) \ +- : "ri" ((T__)val)); \ ++ : "ri" ((T__)(val))); \ + break; \ + default: __bad_percpu_size(); \ + } \ +@@ -109,7 +109,7 @@ do { \ + switch (sizeof(var)) { \ + case 1: \ + asm(op "b "__percpu_seg"%1,%0" \ +- : "=r" (ret__) \ ++ : "=q" (ret__) \ + : "m" (var)); \ + break; \ + case 2: \ diff --git a/master/git-641cd4cfcdc71ce01535b31cc4d57d59a1fae1fc.patch b/master/git-641cd4cfcdc71ce01535b31cc4d57d59a1fae1fc.patch new file mode 100644 index 0000000..d794258 --- /dev/null +++ b/master/git-641cd4cfcdc71ce01535b31cc4d57d59a1fae1fc.patch @@ -0,0 +1,51 @@ +commit 641cd4cfcdc71ce01535b31cc4d57d59a1fae1fc +Author: Ingo Molnar +Date: Fri Mar 13 10:47:34 2009 +0100 + + generic-ipi: eliminate WARN_ON()s during oops/panic + + Do not output smp-call related warnings in the oops/panic codepath. + + Reported-by: Jan Beulich + Acked-by: Peter Zijlstra + LKML-Reference: <49B91A7E.76E4.0078.0@novell.com> + Signed-off-by: Ingo Molnar + +diff --git a/kernel/smp.c b/kernel/smp.c +--- a/kernel/smp.c ++++ b/kernel/smp.c +@@ -5,6 +5,7 @@ + * + */ + #include ++#include + #include + #include + #include +@@ -216,7 +217,7 @@ + int err = 0; + + /* Can deadlock when called with interrupts disabled */ +- WARN_ON(irqs_disabled()); ++ WARN_ON_ONCE(irqs_disabled() && !oops_in_progress); + + if (cpu == me) { + local_irq_save(flags); +@@ -260,7 +261,7 @@ + void __smp_call_function_single(int cpu, struct call_single_data *data) + { + /* Can deadlock when called with interrupts disabled */ +- WARN_ON((data->flags & CSD_FLAG_WAIT) && irqs_disabled()); ++ WARN_ON((data->flags & CSD_FLAG_WAIT) && irqs_disabled() && !oops_in_progress); + + generic_exec_single(cpu, data); + } +@@ -328,7 +329,7 @@ + int slowpath = 0; + + /* Can deadlock when called with interrupts disabled */ +- WARN_ON(irqs_disabled()); ++ WARN_ON_ONCE(irqs_disabled() && !oops_in_progress); + + cpu = smp_processor_id(); + cpus_and(mask, mask, cpu_online_map); diff --git a/master/git-6ff9c2e7fa8ca63a575792534b63c5092099c286.patch b/master/git-6ff9c2e7fa8ca63a575792534b63c5092099c286.patch new file mode 100644 index 0000000..83da64b --- /dev/null +++ b/master/git-6ff9c2e7fa8ca63a575792534b63c5092099c286.patch @@ -0,0 +1,37 @@ +commit 6ff9c2e7fa8ca63a575792534b63c5092099c286 +Author: Krzysztof Halasa +Date: Sun Aug 23 19:02:13 2009 -0700 + + E100: fix interaction with swiotlb on X86. + + E100 places it's RX packet descriptors inside skb->data and uses them + with bidirectional streaming DMA mapping. Data in descriptors is + accessed simultaneously by the chip (writing status and size when + a packet is received) and CPU (reading to check if the packet was + received). This isn't a valid usage of PCI DMA API, which requires use + of the coherent (consistent) memory for such purpose. Unfortunately e100 + chips working in "simplified" RX mode have to store received data + directly after the descriptor. Fixing the driver to conform to the API + would require using unsupported "flexible" RX mode or receiving data + into a coherent memory and using CPU to copy it to network buffers. + + This patch, while not yet making the driver conform to the PCI DMA API, + allows it to work correctly on X86 with swiotlb (while not breaking + other architectures). + + Signed-off-by: Krzysztof Halasa + Signed-off-by: David S. Miller + +diff --git a/drivers/net/e100.c b/drivers/net/e100.c +index 41b648a..3a6735d 100644 +--- a/drivers/net/e100.c ++++ b/drivers/net/e100.c +@@ -1899,7 +1899,7 @@ static int e100_rx_indicate(struct nic *nic, struct rx *rx, + nic->ru_running = RU_SUSPENDED; + pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr, + sizeof(struct rfd), +- PCI_DMA_BIDIRECTIONAL); ++ PCI_DMA_FROMDEVICE); + return -ENODATA; + } + diff --git a/master/git-fa4a7ef36ec834fee1719636b30d2f28f4cb0166.patch b/master/git-fa4a7ef36ec834fee1719636b30d2f28f4cb0166.patch new file mode 100644 index 0000000..e28c209 --- /dev/null +++ b/master/git-fa4a7ef36ec834fee1719636b30d2f28f4cb0166.patch @@ -0,0 +1,51 @@ +commit fa4a7ef36ec834fee1719636b30d2f28f4cb0166 +Author: Arthur Jones +Date: Sat Mar 21 16:55:07 2009 -0700 + + igb: allow tx of pre-formatted vlan tagged packets + + When the 82575 is fed 802.1q packets, it chokes with + an error of the form: + + igb 0000:08:00.1 partial checksum but proto=81! + + As the logic there was not smart enough to look into + the vlan header to pick out the encapsulated protocol. + + There are times when we'd like to send these packets + out without having to configure a vlan on the interface. + Here we check for the vlan tag and allow the packet to + go out with the correct hardware checksum. + + Thanks to Kand Ly for discovering the + issue and the coming up with a solution. This patch is + based upon his work. + + Signed-off-by: Arthur Jones + Signed-off-by: Jeff Kirsher + Signed-off-by: David S. Miller + +diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c +index 7c4481b..39ac375 100644 +--- a/drivers/net/igb/igb_main.c ++++ b/drivers/net/igb/igb_main.c +@@ -3008,7 +3008,18 @@ static inline bool igb_tx_csum_adv(struct igb_adapter *adapter, + tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); + + if (skb->ip_summed == CHECKSUM_PARTIAL) { +- switch (skb->protocol) { ++ __be16 protocol; ++ ++ if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) { ++ const struct vlan_ethhdr *vhdr = ++ (const struct vlan_ethhdr*)skb->data; ++ ++ protocol = vhdr->h_vlan_encapsulated_proto; ++ } else { ++ protocol = skb->protocol; ++ } ++ ++ switch (protocol) { + case __constant_htons(ETH_P_IP): + tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; + if (ip_hdr(skb)->protocol == IPPROTO_TCP) diff --git a/master/git-ffd71da4e3f323b7673b061e6f7e0d0c12dc2b49.patch b/master/git-ffd71da4e3f323b7673b061e6f7e0d0c12dc2b49.patch new file mode 100644 index 0000000..3facf22 --- /dev/null +++ b/master/git-ffd71da4e3f323b7673b061e6f7e0d0c12dc2b49.patch @@ -0,0 +1,44 @@ +commit ffd71da4e3f323b7673b061e6f7e0d0c12dc2b49 +Author: Ingo Molnar +Date: Fri Mar 13 10:54:24 2009 +0100 + + panic: decrease oops_in_progress only after having done the panic + + Impact: eliminate secondary warnings during panic() + + We can panic() in a number of difficult, atomic contexts, hence + we use bust_spinlocks(1) in panic() to increase oops_in_progress, + which prevents various debug checks we have in place. + + But in practice this protection only covers the first few printk's + done by panic() - it does not cover the later attempt to stop all + other CPUs and kexec(). If a secondary warning triggers in one of + those facilities that can make the panic message scroll off. + + So do bust_spinlocks(0) only much later in panic(). (which code + is only reached if panic policy is relaxed that it can return + after a warning message) + + Reported-by: Jan Beulich + LKML-Reference: <49B91A7E.76E4.0078.0@novell.com> + Signed-off-by: Ingo Molnar + +diff --git a/kernel/panic.c b/kernel/panic.c +index 32fe4ef..57fb005 100644 +--- a/kernel/panic.c ++++ b/kernel/panic.c +@@ -77,6 +77,5 @@ NORET_TYPE void panic(const char * fmt, ...) + va_end(args); + printk(KERN_EMERG "Kernel panic - not syncing: %s\n",buf); +- bust_spinlocks(0); + + #ifdef CONFIG_KDB_KDUMP + if (kdb_kdump_state == KDB_KDUMP_RESET) { +@@ -136,6 +135,7 @@ NORET_TYPE void panic(const char * fmt, ...) + mdelay(1); + i++; + } ++ bust_spinlocks(0); + } + + EXPORT_SYMBOL(panic); diff --git a/master/ibft-find.patch b/master/ibft-find.patch new file mode 100644 index 0000000..184881b --- /dev/null +++ b/master/ibft-find.patch @@ -0,0 +1,44 @@ +Make the routine that searches for an iSCSI Boot Firmware Table work on Xen. + +diff -r 2c48f84781e9 drivers/firmware/iscsi_ibft_find.c +--- a/drivers/firmware/iscsi_ibft_find.c Wed Sep 30 10:19:15 2009 +0100 ++++ b/drivers/firmware/iscsi_ibft_find.c Wed Oct 07 16:36:11 2009 +0100 +@@ -56,28 +56,34 @@ + { + unsigned long pos; + unsigned int len = 0; +- void *virt; ++ void *virt, *vbase; + + ibft_addr = NULL; ++ ++ /* Map the entire region we shall be scanning */ ++ vbase = ioremap(IBFT_START, IBFT_END - IBFT_START); + + for (pos = IBFT_START; pos < IBFT_END; pos += 16) { + /* The table can't be inside the VGA BIOS reserved space, + * so skip that area */ + if (pos == VGA_MEM) + pos += VGA_SIZE; +- virt = phys_to_virt(pos); ++ virt = vbase + (pos - IBFT_START); + if (memcmp(virt, IBFT_SIGN, IBFT_SIGN_LEN) == 0) { + unsigned long *addr = +- (unsigned long *)phys_to_virt(pos + 4); ++ (unsigned long *)(virt + 4); + len = *addr; + /* if the length of the table extends past 1M, + * the table cannot be valid. */ + if (pos + len <= (IBFT_END-1)) { +- ibft_addr = (struct ibft_table_header *)virt; ++ ibft_addr = (struct ibft_table_header *)ioremap(pos, len); + break; + } + } + } + if (ibft_addr) + reserve_bootmem(pos, PAGE_ALIGN(len), BOOTMEM_DEFAULT); ++ ++ /* Unmap the region we just scanned */ ++ iounmap(vbase); + } diff --git a/master/igb-1.3.28.4.patch b/master/igb-1.3.28.4.patch new file mode 100644 index 0000000..cd6ea02 --- /dev/null +++ b/master/igb-1.3.28.4.patch @@ -0,0 +1,23508 @@ +diff -r 4f0f8bc35440 drivers/net/igb/Makefile +--- a/drivers/net/igb/Makefile Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/Makefile Wed Aug 05 11:03:37 2009 +0100 +@@ -1,6 +1,6 @@ + ################################################################################ + # +-# Intel 82575 PCI-Express Ethernet Linux driver ++# Intel PRO/1000 Linux driver + # Copyright(c) 1999 - 2007 Intel Corporation. + # + # This program is free software; you can redistribute it and/or modify it +@@ -27,11 +27,16 @@ + ################################################################################ + + # +-# Makefile for the Intel(R) 82575 PCI-Express ethernet driver ++# Makefile for the Intel(R) PRO/1000 ethernet driver + # + + obj-$(CONFIG_IGB) += igb.o + +-igb-objs := igb_main.o igb_ethtool.o e1000_82575.o \ +- e1000_mac.o e1000_nvm.o e1000_phy.o ++FAMILYC = e1000_82575.c + ++CFILES = igb_main.c $(FAMILYC) e1000_mac.c e1000_nvm.c e1000_phy.c \ ++ e1000_manage.c igb_param.c igb_ethtool.c kcompat.c e1000_api.c ++ ++igb-objs := $(CFILES:.c=.o) ++ ++EXTRA_CFLAGS += -DDRIVER_IGB +diff -r 4f0f8bc35440 drivers/net/igb/e1000_82575.c +--- a/drivers/net/igb/e1000_82575.c Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/e1000_82575.c Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 - 2008 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -25,131 +25,133 @@ + + *******************************************************************************/ + +-/* e1000_82575 +- * e1000_82576 ++/* ++ * 82575EB Gigabit Network Connection ++ * 82575EB Gigabit Backplane Connection ++ * 82575GB Gigabit Network Connection ++ * 82576 Gigabit Network Connection ++ * 82576 Quad Port Gigabit Mezzanine Adapter + */ + +-#include +-#include +-#include ++#include "e1000_api.h" + +-#include "e1000_mac.h" +-#include "e1000_82575.h" ++static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); ++static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); ++static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); ++static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); ++static void e1000_release_phy_82575(struct e1000_hw *hw); ++static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); ++static void e1000_release_nvm_82575(struct e1000_hw *hw); ++static s32 e1000_check_for_link_82575(struct e1000_hw *hw); ++static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); ++static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex); ++static s32 e1000_init_hw_82575(struct e1000_hw *hw); ++static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); ++static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, ++ u16 *data); ++static s32 e1000_reset_hw_82575(struct e1000_hw *hw); ++static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, ++ bool active); ++static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); ++static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw); ++static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); ++static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, ++ u32 offset, u16 data); ++static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); ++static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); ++static void e1000_configure_pcs_link_82575(struct e1000_hw *hw); ++static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, ++ u16 *speed, u16 *duplex); ++static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); ++static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); ++static bool e1000_sgmii_active_82575(struct e1000_hw *hw); ++static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); ++static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); ++static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); ++void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw); ++static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); + +-static s32 igb_get_invariants_82575(struct e1000_hw *); +-static s32 igb_acquire_phy_82575(struct e1000_hw *); +-static void igb_release_phy_82575(struct e1000_hw *); +-static s32 igb_acquire_nvm_82575(struct e1000_hw *); +-static void igb_release_nvm_82575(struct e1000_hw *); +-static s32 igb_check_for_link_82575(struct e1000_hw *); +-static s32 igb_get_cfg_done_82575(struct e1000_hw *); +-static s32 igb_init_hw_82575(struct e1000_hw *); +-static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); +-static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); +-static s32 igb_reset_hw_82575(struct e1000_hw *); +-static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); +-static s32 igb_setup_copper_link_82575(struct e1000_hw *); +-static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *); +-static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); +-static void igb_clear_hw_cntrs_82575(struct e1000_hw *); +-static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); +-static s32 igb_configure_pcs_link_82575(struct e1000_hw *); +-static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, +- u16 *); +-static s32 igb_get_phy_id_82575(struct e1000_hw *); +-static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); +-static bool igb_sgmii_active_82575(struct e1000_hw *); +-static s32 igb_reset_init_script_82575(struct e1000_hw *); +-static s32 igb_read_mac_addr_82575(struct e1000_hw *); +- +- +-struct e1000_dev_spec_82575 { +- bool sgmii_active; +-}; +- +-static s32 igb_get_invariants_82575(struct e1000_hw *hw) ++/** ++ * e1000_init_phy_params_82575 - Init PHY func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; +- struct e1000_nvm_info *nvm = &hw->nvm; +- struct e1000_mac_info *mac = &hw->mac; +- struct e1000_dev_spec_82575 *dev_spec; +- u32 eecd; +- s32 ret_val; +- u16 size; +- u32 ctrl_ext = 0; ++ s32 ret_val = E1000_SUCCESS; + +- switch (hw->device_id) { +- case E1000_DEV_ID_82575EB_COPPER: +- case E1000_DEV_ID_82575EB_FIBER_SERDES: +- case E1000_DEV_ID_82575GB_QUAD_COPPER: +- mac->type = e1000_82575; ++ DEBUGFUNC("e1000_init_phy_params_82575"); ++ ++ if (hw->phy.media_type != e1000_media_type_copper) { ++ phy->type = e1000_phy_none; ++ goto out; ++ } else { ++ phy->ops.power_up = e1000_power_up_phy_copper; ++ phy->ops.power_down = e1000_power_down_phy_copper_82575; ++ } ++ ++ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; ++ phy->reset_delay_us = 100; ++ ++ phy->ops.acquire = e1000_acquire_phy_82575; ++ phy->ops.check_reset_block = e1000_check_reset_block_generic; ++ phy->ops.commit = e1000_phy_sw_reset_generic; ++ phy->ops.get_cfg_done = e1000_get_cfg_done_82575; ++ phy->ops.release = e1000_release_phy_82575; ++ ++ if (e1000_sgmii_active_82575(hw)) { ++ phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; ++ phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; ++ phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; ++ } else { ++ phy->ops.reset = e1000_phy_hw_reset_generic; ++ phy->ops.read_reg = e1000_read_phy_reg_igp; ++ phy->ops.write_reg = e1000_write_phy_reg_igp; ++ } ++ ++ /* Set phy->phy_addr and phy->id. */ ++ ret_val = e1000_get_phy_id_82575(hw); ++ ++ /* Verify phy id and set remaining function pointers */ ++ switch (phy->id) { ++ case M88E1111_I_PHY_ID: ++ phy->type = e1000_phy_m88; ++ phy->ops.check_polarity = e1000_check_polarity_m88; ++ phy->ops.get_info = e1000_get_phy_info_m88; ++ phy->ops.get_cable_length = e1000_get_cable_length_m88; ++ phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; + break; +- case E1000_DEV_ID_82576: +- case E1000_DEV_ID_82576_FIBER: +- case E1000_DEV_ID_82576_SERDES: +- mac->type = e1000_82576; ++ case IGP03E1000_E_PHY_ID: ++ case IGP04E1000_E_PHY_ID: ++ phy->type = e1000_phy_igp_3; ++ phy->ops.check_polarity = e1000_check_polarity_igp; ++ phy->ops.get_info = e1000_get_phy_info_igp; ++ phy->ops.get_cable_length = e1000_get_cable_length_igp_2; ++ phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; ++ phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; ++ phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; + break; + default: +- return -E1000_ERR_MAC_INIT; +- break; ++ ret_val = -E1000_ERR_PHY; ++ goto out; + } + +- /* MAC initialization */ +- hw->dev_spec_size = sizeof(struct e1000_dev_spec_82575); ++out: ++ return ret_val; ++} + +- /* Device-specific structure allocation */ +- hw->dev_spec = kzalloc(hw->dev_spec_size, GFP_KERNEL); ++/** ++ * e1000_init_nvm_params_82575 - Init NVM func ptrs. ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = E1000_READ_REG(hw, E1000_EECD); ++ u16 size; + +- if (!hw->dev_spec) +- return -ENOMEM; +- +- dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec; +- +- /* Set media type */ +- /* +- * The 82575 uses bits 22:23 for link mode. The mode can be changed +- * based on the EEPROM. We cannot rely upon device ID. There +- * is no distinguishable difference between fiber and internal +- * SerDes mode on the 82575. There can be an external PHY attached +- * on the SGMII interface. For this, we'll set sgmii_active to true. +- */ +- phy->media_type = e1000_media_type_copper; +- dev_spec->sgmii_active = false; +- +- ctrl_ext = rd32(E1000_CTRL_EXT); +- if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) == +- E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) { +- hw->phy.media_type = e1000_media_type_internal_serdes; +- ctrl_ext |= E1000_CTRL_I2C_ENA; +- } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) { +- dev_spec->sgmii_active = true; +- ctrl_ext |= E1000_CTRL_I2C_ENA; +- } else { +- ctrl_ext &= ~E1000_CTRL_I2C_ENA; +- } +- wr32(E1000_CTRL_EXT, ctrl_ext); +- +- /* Set mta register count */ +- mac->mta_reg_count = 128; +- /* Set rar entry count */ +- mac->rar_entry_count = E1000_RAR_ENTRIES_82575; +- if (mac->type == e1000_82576) +- mac->rar_entry_count = E1000_RAR_ENTRIES_82576; +- /* Set if part includes ASF firmware */ +- mac->asf_firmware_present = true; +- /* Set if manageability features are enabled. */ +- mac->arc_subsystem_valid = +- (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) +- ? true : false; +- +- /* physical interface link setup */ +- mac->ops.setup_physical_interface = +- (hw->phy.media_type == e1000_media_type_copper) +- ? igb_setup_copper_link_82575 +- : igb_setup_fiber_serdes_link_82575; +- +- /* NVM initialization */ +- eecd = rd32(E1000_EECD); ++ DEBUGFUNC("e1000_init_nvm_params_82575"); + + nvm->opcode_bits = 8; + nvm->delay_usec = 1; +@@ -168,10 +170,10 @@ + break; + } + +- nvm->type = e1000_nvm_eeprom_spi; ++ nvm->type = e1000_nvm_eeprom_spi; + + size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> +- E1000_EECD_SIZE_EX_SHIFT); ++ E1000_EECD_SIZE_EX_SHIFT); + + /* + * Added to a constant, "size" becomes the left-shift value +@@ -182,89 +184,175 @@ + /* EEPROM access above 16k is unsupported */ + if (size > 14) + size = 14; +- nvm->word_size = 1 << size; ++ nvm->word_size = 1 << size; + +- /* setup PHY parameters */ +- if (phy->media_type != e1000_media_type_copper) { +- phy->type = e1000_phy_none; +- return 0; +- } ++ /* Function Pointers */ ++ nvm->ops.acquire = e1000_acquire_nvm_82575; ++ nvm->ops.read = e1000_read_nvm_eerd; ++ nvm->ops.release = e1000_release_nvm_82575; ++ nvm->ops.update = e1000_update_nvm_checksum_generic; ++ nvm->ops.valid_led_default = e1000_valid_led_default_82575; ++ nvm->ops.validate = e1000_validate_nvm_checksum_generic; ++ nvm->ops.write = e1000_write_nvm_spi; + +- phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; +- phy->reset_delay_us = 100; +- +- /* PHY function pointers */ +- if (igb_sgmii_active_82575(hw)) { +- phy->ops.reset_phy = igb_phy_hw_reset_sgmii_82575; +- phy->ops.read_phy_reg = igb_read_phy_reg_sgmii_82575; +- phy->ops.write_phy_reg = igb_write_phy_reg_sgmii_82575; +- } else { +- phy->ops.reset_phy = igb_phy_hw_reset; +- phy->ops.read_phy_reg = igb_read_phy_reg_igp; +- phy->ops.write_phy_reg = igb_write_phy_reg_igp; +- } +- +- /* Set phy->phy_addr and phy->id. */ +- ret_val = igb_get_phy_id_82575(hw); +- if (ret_val) +- return ret_val; +- +- /* Verify phy id and set remaining function pointers */ +- switch (phy->id) { +- case M88E1111_I_PHY_ID: +- phy->type = e1000_phy_m88; +- phy->ops.get_phy_info = igb_get_phy_info_m88; +- phy->ops.get_cable_length = igb_get_cable_length_m88; +- phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; +- break; +- case IGP03E1000_E_PHY_ID: +- phy->type = e1000_phy_igp_3; +- phy->ops.get_phy_info = igb_get_phy_info_igp; +- phy->ops.get_cable_length = igb_get_cable_length_igp_2; +- phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; +- phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; +- phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; +- break; +- default: +- return -E1000_ERR_PHY; +- } +- +- return 0; ++ return E1000_SUCCESS; + } + + /** +- * igb_acquire_phy_82575 - Acquire rights to access PHY ++ * e1000_init_mac_params_82575 - Init MAC func ptrs. + * @hw: pointer to the HW structure +- * +- * Acquire access rights to the correct PHY. This is a +- * function pointer entry point called by the api module. + **/ +-static s32 igb_acquire_phy_82575(struct e1000_hw *hw) ++static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) + { +- u16 mask; ++ struct e1000_mac_info *mac = &hw->mac; ++ struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; ++ u32 ctrl_ext = 0; + +- mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; ++ DEBUGFUNC("e1000_init_mac_params_82575"); + +- return igb_acquire_swfw_sync_82575(hw, mask); ++ /* Set media type */ ++ /* ++ * The 82575 uses bits 22:23 for link mode. The mode can be changed ++ * based on the EEPROM. We cannot rely upon device ID. There ++ * is no distinguishable difference between fiber and internal ++ * SerDes mode on the 82575. There can be an external PHY attached ++ * on the SGMII interface. For this, we'll set sgmii_active to true. ++ */ ++ hw->phy.media_type = e1000_media_type_copper; ++ dev_spec->sgmii_active = false; ++ ++ ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); ++ if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) == ++ E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) { ++ hw->phy.media_type = e1000_media_type_internal_serdes; ++ ctrl_ext |= E1000_CTRL_I2C_ENA; ++ } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) { ++ dev_spec->sgmii_active = true; ++ ctrl_ext |= E1000_CTRL_I2C_ENA; ++ } else { ++ ctrl_ext &= ~E1000_CTRL_I2C_ENA; ++ } ++ E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); ++ ++ /* Set mta register count */ ++ mac->mta_reg_count = 128; ++ /* Set rar entry count */ ++ mac->rar_entry_count = E1000_RAR_ENTRIES_82575; ++ if (mac->type == e1000_82576) ++ mac->rar_entry_count = E1000_RAR_ENTRIES_82576; ++ /* Set if part includes ASF firmware */ ++ mac->asf_firmware_present = true; ++ /* Set if manageability features are enabled. */ ++ mac->arc_subsystem_valid = ++ (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) ++ ? true : false; ++ ++ /* Function pointers */ ++ ++ /* bus type/speed/width */ ++ mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; ++ /* reset */ ++ mac->ops.reset_hw = e1000_reset_hw_82575; ++ /* hw initialization */ ++ mac->ops.init_hw = e1000_init_hw_82575; ++ /* link setup */ ++ mac->ops.setup_link = e1000_setup_link_generic; ++ /* physical interface link setup */ ++ mac->ops.setup_physical_interface = ++ (hw->phy.media_type == e1000_media_type_copper) ++ ? e1000_setup_copper_link_82575 ++ : e1000_setup_fiber_serdes_link_82575; ++ /* physical interface shutdown */ ++ mac->ops.shutdown_serdes = e1000_shutdown_fiber_serdes_link_82575; ++ /* check for link */ ++ mac->ops.check_for_link = e1000_check_for_link_82575; ++ /* receive address register setting */ ++ mac->ops.rar_set = e1000_rar_set_generic; ++ /* read mac address */ ++ mac->ops.read_mac_addr = e1000_read_mac_addr_82575; ++ /* multicast address update */ ++ mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; ++ /* writing VFTA */ ++ mac->ops.write_vfta = e1000_write_vfta_generic; ++ /* clearing VFTA */ ++ mac->ops.clear_vfta = e1000_clear_vfta_generic; ++ /* setting MTA */ ++ mac->ops.mta_set = e1000_mta_set_generic; ++ /* ID LED init */ ++ mac->ops.id_led_init = e1000_id_led_init_generic; ++ /* blink LED */ ++ mac->ops.blink_led = e1000_blink_led_generic; ++ /* setup LED */ ++ mac->ops.setup_led = e1000_setup_led_generic; ++ /* cleanup LED */ ++ mac->ops.cleanup_led = e1000_cleanup_led_generic; ++ /* turn on/off LED */ ++ mac->ops.led_on = e1000_led_on_generic; ++ mac->ops.led_off = e1000_led_off_generic; ++ /* clear hardware counters */ ++ mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; ++ /* link info */ ++ mac->ops.get_link_up_info = e1000_get_link_up_info_82575; ++ ++ /* set lan id for port to determine which phy lock to use */ ++ hw->mac.ops.set_lan_id(hw); ++ ++ return E1000_SUCCESS; + } + + /** +- * igb_release_phy_82575 - Release rights to access PHY ++ * e1000_init_function_pointers_82575 - Init func ptrs. + * @hw: pointer to the HW structure + * +- * A wrapper to release access rights to the correct PHY. This is a +- * function pointer entry point called by the api module. ++ * Called to initialize all function pointers and parameters. + **/ +-static void igb_release_phy_82575(struct e1000_hw *hw) ++void e1000_init_function_pointers_82575(struct e1000_hw *hw) + { +- u16 mask; ++ DEBUGFUNC("e1000_init_function_pointers_82575"); + +- mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; +- igb_release_swfw_sync_82575(hw, mask); ++ hw->mac.ops.init_params = e1000_init_mac_params_82575; ++ hw->nvm.ops.init_params = e1000_init_nvm_params_82575; ++ hw->phy.ops.init_params = e1000_init_phy_params_82575; + } + + /** +- * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii ++ * e1000_acquire_phy_82575 - Acquire rights to access PHY ++ * @hw: pointer to the HW structure ++ * ++ * Acquire access rights to the correct PHY. ++ **/ ++static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) ++{ ++ u16 mask = E1000_SWFW_PHY0_SM; ++ ++ DEBUGFUNC("e1000_acquire_phy_82575"); ++ ++ if (hw->bus.func == E1000_FUNC_1) ++ mask = E1000_SWFW_PHY1_SM; ++ ++ return e1000_acquire_swfw_sync_82575(hw, mask); ++} ++ ++/** ++ * e1000_release_phy_82575 - Release rights to access PHY ++ * @hw: pointer to the HW structure ++ * ++ * A wrapper to release access rights to the correct PHY. ++ **/ ++static void e1000_release_phy_82575(struct e1000_hw *hw) ++{ ++ u16 mask = E1000_SWFW_PHY0_SM; ++ ++ DEBUGFUNC("e1000_release_phy_82575"); ++ ++ if (hw->bus.func == E1000_FUNC_1) ++ mask = E1000_SWFW_PHY1_SM; ++ ++ e1000_release_swfw_sync_82575(hw, mask); ++} ++ ++/** ++ * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii + * @hw: pointer to the HW structure + * @offset: register offset to be read + * @data: pointer to the read data +@@ -272,14 +360,16 @@ + * Reads the PHY register at offset using the serial gigabit media independent + * interface and stores the retrieved information in data. + **/ +-static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, +- u16 *data) ++static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, ++ u16 *data) + { + struct e1000_phy_info *phy = &hw->phy; + u32 i, i2ccmd = 0; + ++ DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); ++ + if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { +- hw_dbg("PHY Address %u is out of range\n", offset); ++ DEBUGOUT1("PHY Address %u is out of range\n", offset); + return -E1000_ERR_PARAM; + } + +@@ -289,35 +379,35 @@ + * PHY to retrieve the desired data. + */ + i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | +- (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | +- (E1000_I2CCMD_OPCODE_READ)); ++ (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | ++ (E1000_I2CCMD_OPCODE_READ)); + +- wr32(E1000_I2CCMD, i2ccmd); ++ E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); + + /* Poll the ready bit to see if the I2C read completed */ + for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { +- udelay(50); +- i2ccmd = rd32(E1000_I2CCMD); ++ usec_delay(50); ++ i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); + if (i2ccmd & E1000_I2CCMD_READY) + break; + } + if (!(i2ccmd & E1000_I2CCMD_READY)) { +- hw_dbg("I2CCMD Read did not complete\n"); ++ DEBUGOUT("I2CCMD Read did not complete\n"); + return -E1000_ERR_PHY; + } + if (i2ccmd & E1000_I2CCMD_ERROR) { +- hw_dbg("I2CCMD Error bit set\n"); ++ DEBUGOUT("I2CCMD Error bit set\n"); + return -E1000_ERR_PHY; + } + + /* Need to byte-swap the 16-bit value. */ + *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); + +- return 0; ++ return E1000_SUCCESS; + } + + /** +- * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii ++ * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii + * @hw: pointer to the HW structure + * @offset: register offset to write to + * @data: data to write at register offset +@@ -325,15 +415,17 @@ + * Writes the data to PHY register at the offset using the serial gigabit + * media independent interface. + **/ +-static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, +- u16 data) ++static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, ++ u16 data) + { + struct e1000_phy_info *phy = &hw->phy; + u32 i, i2ccmd = 0; + u16 phy_data_swapped; + ++ DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); ++ + if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { +- hw_dbg("PHY Address %d is out of range\n", offset); ++ DEBUGOUT1("PHY Address %d is out of range\n", offset); + return -E1000_ERR_PARAM; + } + +@@ -346,43 +438,45 @@ + * PHY to retrieve the desired data. + */ + i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | +- (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | +- E1000_I2CCMD_OPCODE_WRITE | +- phy_data_swapped); ++ (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | ++ E1000_I2CCMD_OPCODE_WRITE | ++ phy_data_swapped); + +- wr32(E1000_I2CCMD, i2ccmd); ++ E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); + + /* Poll the ready bit to see if the I2C read completed */ + for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { +- udelay(50); +- i2ccmd = rd32(E1000_I2CCMD); ++ usec_delay(50); ++ i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); + if (i2ccmd & E1000_I2CCMD_READY) + break; + } + if (!(i2ccmd & E1000_I2CCMD_READY)) { +- hw_dbg("I2CCMD Write did not complete\n"); ++ DEBUGOUT("I2CCMD Write did not complete\n"); + return -E1000_ERR_PHY; + } + if (i2ccmd & E1000_I2CCMD_ERROR) { +- hw_dbg("I2CCMD Error bit set\n"); ++ DEBUGOUT("I2CCMD Error bit set\n"); + return -E1000_ERR_PHY; + } + +- return 0; ++ return E1000_SUCCESS; + } + + /** +- * igb_get_phy_id_82575 - Retrieve PHY addr and id ++ * e1000_get_phy_id_82575 - Retrieve PHY addr and id + * @hw: pointer to the HW structure + * + * Retrieves the PHY address and ID for both PHY's which do and do not use + * sgmi interface. + **/ +-static s32 igb_get_phy_id_82575(struct e1000_hw *hw) ++static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + u16 phy_id; ++ ++ DEBUGFUNC("e1000_get_phy_id_82575"); + + /* + * For SGMII PHYs, we try the list of possible addresses until +@@ -391,9 +485,9 @@ + * work. The result of this function should mean phy->phy_addr + * and phy->id are set correctly. + */ +- if (!(igb_sgmii_active_82575(hw))) { ++ if (!(e1000_sgmii_active_82575(hw))) { + phy->addr = 1; +- ret_val = igb_get_phy_id(hw); ++ ret_val = e1000_get_phy_id(hw); + goto out; + } + +@@ -402,10 +496,11 @@ + * Therefore, we need to test 1-7 + */ + for (phy->addr = 1; phy->addr < 8; phy->addr++) { +- ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); +- if (ret_val == 0) { +- hw_dbg("Vendor ID 0x%08X read at address %u\n", +- phy_id, phy->addr); ++ ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); ++ if (ret_val == E1000_SUCCESS) { ++ DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", ++ phy_id, ++ phy->addr); + /* + * At the time of this writing, The M88 part is + * the only supported SGMII PHY product. +@@ -413,7 +508,8 @@ + if (phy_id == M88_VENDOR) + break; + } else { +- hw_dbg("PHY address %u was unreadable\n", phy->addr); ++ DEBUGOUT1("PHY address %u was unreadable\n", ++ phy->addr); + } + } + +@@ -424,45 +520,50 @@ + goto out; + } + +- ret_val = igb_get_phy_id(hw); ++ ret_val = e1000_get_phy_id(hw); + + out: + return ret_val; + } + + /** +- * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset ++ * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset + * @hw: pointer to the HW structure + * + * Resets the PHY using the serial gigabit media independent interface. + **/ +-static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) ++static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) + { +- s32 ret_val; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); + + /* + * This isn't a true "hard" reset, but is the only reset + * available to us at this time. + */ + +- hw_dbg("Soft resetting SGMII attached PHY...\n"); ++ DEBUGOUT("Soft resetting SGMII attached PHY...\n"); ++ ++ if (!(hw->phy.ops.write_reg)) ++ goto out; + + /* + * SFP documentation requires the following to configure the SPF module + * to work on SGMII. No further documentation is given. + */ +- ret_val = hw->phy.ops.write_phy_reg(hw, 0x1B, 0x8084); ++ ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); + if (ret_val) + goto out; + +- ret_val = igb_phy_sw_reset(hw); ++ ret_val = hw->phy.ops.commit(hw); + + out: + return ret_val; + } + + /** +- * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state ++ * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state + * @hw: pointer to the HW structure + * @active: true to enable LPLU, false to disable + * +@@ -474,35 +575,40 @@ + * This is a function pointer entry point only called by + * PHY setup routines. + **/ +-static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) ++static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) + { + struct e1000_phy_info *phy = &hw->phy; +- s32 ret_val; ++ s32 ret_val = E1000_SUCCESS; + u16 data; + +- ret_val = phy->ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); ++ DEBUGFUNC("e1000_set_d0_lplu_state_82575"); ++ ++ if (!(hw->phy.ops.read_reg)) ++ goto out; ++ ++ ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); + if (ret_val) + goto out; + + if (active) { + data |= IGP02E1000_PM_D0_LPLU; +- ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, +- data); ++ ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, ++ data); + if (ret_val) + goto out; + + /* When LPLU is enabled, we should disable SmartSpeed */ +- ret_val = phy->ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, +- &data); ++ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ++ &data); + data &= ~IGP01E1000_PSCFR_SMART_SPEED; +- ret_val = phy->ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, +- data); ++ ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ++ data); + if (ret_val) + goto out; + } else { + data &= ~IGP02E1000_PM_D0_LPLU; +- ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, +- data); ++ ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, ++ data); + /* + * LPLU and SmartSpeed are mutually exclusive. LPLU is used + * during Dx states where the power conservation is most +@@ -510,25 +616,29 @@ + * SmartSpeed, so performance is maintained. + */ + if (phy->smart_speed == e1000_smart_speed_on) { +- ret_val = phy->ops.read_phy_reg(hw, +- IGP01E1000_PHY_PORT_CONFIG, &data); ++ ret_val = phy->ops.read_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); + if (ret_val) + goto out; + + data |= IGP01E1000_PSCFR_SMART_SPEED; +- ret_val = phy->ops.write_phy_reg(hw, +- IGP01E1000_PHY_PORT_CONFIG, data); ++ ret_val = phy->ops.write_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); + if (ret_val) + goto out; + } else if (phy->smart_speed == e1000_smart_speed_off) { +- ret_val = phy->ops.read_phy_reg(hw, +- IGP01E1000_PHY_PORT_CONFIG, &data); ++ ret_val = phy->ops.read_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; +- ret_val = phy->ops.write_phy_reg(hw, +- IGP01E1000_PHY_PORT_CONFIG, data); ++ ret_val = phy->ops.write_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); + if (ret_val) + goto out; + } +@@ -539,7 +649,7 @@ + } + + /** +- * igb_acquire_nvm_82575 - Request for access to EEPROM ++ * e1000_acquire_nvm_82575 - Request for access to EEPROM + * @hw: pointer to the HW structure + * + * Acquire the necessary semaphores for exclusive access to the EEPROM. +@@ -547,59 +657,65 @@ + * Return successful if access grant bit set, else clear the request for + * EEPROM access and return -E1000_ERR_NVM (-1). + **/ +-static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) ++static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) + { + s32 ret_val; + +- ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); ++ DEBUGFUNC("e1000_acquire_nvm_82575"); ++ ++ ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); + if (ret_val) + goto out; + +- ret_val = igb_acquire_nvm(hw); ++ ret_val = e1000_acquire_nvm_generic(hw); + + if (ret_val) +- igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); ++ e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); + + out: + return ret_val; + } + + /** +- * igb_release_nvm_82575 - Release exclusive access to EEPROM ++ * e1000_release_nvm_82575 - Release exclusive access to EEPROM + * @hw: pointer to the HW structure + * + * Stop any current commands to the EEPROM and clear the EEPROM request bit, + * then release the semaphores acquired. + **/ +-static void igb_release_nvm_82575(struct e1000_hw *hw) ++static void e1000_release_nvm_82575(struct e1000_hw *hw) + { +- igb_release_nvm(hw); +- igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); ++ DEBUGFUNC("e1000_release_nvm_82575"); ++ ++ e1000_release_nvm_generic(hw); ++ e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); + } + + /** +- * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore ++ * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore + * @hw: pointer to the HW structure + * @mask: specifies which semaphore to acquire + * + * Acquire the SW/FW semaphore to access the PHY or NVM. The mask + * will also specify which port we're acquiring the lock for. + **/ +-static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) ++static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) + { + u32 swfw_sync; + u32 swmask = mask; + u32 fwmask = mask << 16; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ + ++ DEBUGFUNC("e1000_acquire_swfw_sync_82575"); ++ + while (i < timeout) { +- if (igb_get_hw_semaphore(hw)) { ++ if (e1000_get_hw_semaphore_generic(hw)) { + ret_val = -E1000_ERR_SWFW_SYNC; + goto out; + } + +- swfw_sync = rd32(E1000_SW_FW_SYNC); ++ swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); + if (!(swfw_sync & (fwmask | swmask))) + break; + +@@ -607,108 +723,152 @@ + * Firmware currently using resource (fwmask) + * or other software thread using resource (swmask) + */ +- igb_put_hw_semaphore(hw); +- mdelay(5); ++ e1000_put_hw_semaphore_generic(hw); ++ msec_delay_irq(5); + i++; + } + + if (i == timeout) { +- hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); ++ DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); + ret_val = -E1000_ERR_SWFW_SYNC; + goto out; + } + + swfw_sync |= swmask; +- wr32(E1000_SW_FW_SYNC, swfw_sync); ++ E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); + +- igb_put_hw_semaphore(hw); ++ e1000_put_hw_semaphore_generic(hw); + + out: + return ret_val; + } + + /** +- * igb_release_swfw_sync_82575 - Release SW/FW semaphore ++ * e1000_release_swfw_sync_82575 - Release SW/FW semaphore + * @hw: pointer to the HW structure + * @mask: specifies which semaphore to acquire + * + * Release the SW/FW semaphore used to access the PHY or NVM. The mask + * will also specify which port we're releasing the lock for. + **/ +-static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) ++static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) + { + u32 swfw_sync; + +- while (igb_get_hw_semaphore(hw) != 0); ++ DEBUGFUNC("e1000_release_swfw_sync_82575"); ++ ++ while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); + /* Empty */ + +- swfw_sync = rd32(E1000_SW_FW_SYNC); ++ swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); + swfw_sync &= ~mask; +- wr32(E1000_SW_FW_SYNC, swfw_sync); ++ E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); + +- igb_put_hw_semaphore(hw); ++ e1000_put_hw_semaphore_generic(hw); + } + + /** +- * igb_get_cfg_done_82575 - Read config done bit ++ * e1000_get_cfg_done_82575 - Read config done bit + * @hw: pointer to the HW structure + * + * Read the management control register for the config done bit for + * completion status. NOTE: silicon which is EEPROM-less will fail trying + * to read the config done bit, so an error is *ONLY* logged and returns +- * 0. If we were to return with error, EEPROM-less silicon ++ * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon + * would not be able to be reset or change link. + **/ +-static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) ++static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) + { + s32 timeout = PHY_CFG_TIMEOUT; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + u32 mask = E1000_NVM_CFG_DONE_PORT_0; + +- if (hw->bus.func == 1) ++ DEBUGFUNC("e1000_get_cfg_done_82575"); ++ ++ if (hw->bus.func == E1000_FUNC_1) + mask = E1000_NVM_CFG_DONE_PORT_1; +- + while (timeout) { +- if (rd32(E1000_EEMNGCTL) & mask) ++ if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) + break; +- msleep(1); ++ msec_delay(1); + timeout--; + } +- if (!timeout) +- hw_dbg("MNG configuration cycle has not completed.\n"); ++ if (!timeout) { ++ DEBUGOUT("MNG configuration cycle has not completed.\n"); ++ } + + /* If EEPROM is not marked present, init the PHY manually */ +- if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && +- (hw->phy.type == e1000_phy_igp_3)) +- igb_phy_init_script_igp3(hw); ++ if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && ++ (hw->phy.type == e1000_phy_igp_3)) { ++ e1000_phy_init_script_igp3(hw); ++ } + + return ret_val; + } + + /** +- * igb_check_for_link_82575 - Check for link ++ * e1000_get_link_up_info_82575 - Get link speed/duplex info ++ * @hw: pointer to the HW structure ++ * @speed: stores the current speed ++ * @duplex: stores the current duplex ++ * ++ * This is a wrapper function, if using the serial gigabit media independent ++ * interface, use PCS to retrieve the link speed and duplex information. ++ * Otherwise, use the generic function to get the link speed and duplex info. ++ **/ ++static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex) ++{ ++ s32 ret_val; ++ ++ DEBUGFUNC("e1000_get_link_up_info_82575"); ++ ++ if (hw->phy.media_type != e1000_media_type_copper || ++ e1000_sgmii_active_82575(hw)) { ++ ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, ++ duplex); ++ } else { ++ ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, ++ duplex); ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_check_for_link_82575 - Check for link + * @hw: pointer to the HW structure + * + * If sgmii is enabled, then use the pcs register to determine link, otherwise + * use the generic interface for determining link. + **/ +-static s32 igb_check_for_link_82575(struct e1000_hw *hw) ++static s32 e1000_check_for_link_82575(struct e1000_hw *hw) + { + s32 ret_val; + u16 speed, duplex; + ++ DEBUGFUNC("e1000_check_for_link_82575"); ++ + /* SGMII link check is done through the PCS register. */ + if ((hw->phy.media_type != e1000_media_type_copper) || +- (igb_sgmii_active_82575(hw))) +- ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, +- &duplex); +- else +- ret_val = igb_check_for_copper_link(hw); ++ (e1000_sgmii_active_82575(hw))) { ++ ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, ++ &duplex); ++ /* ++ * Use this flag to determine if link needs to be checked or ++ * not. If we have link clear the flag so that we do not ++ * continue to check for link. ++ */ ++ hw->mac.get_link_status = !hw->mac.serdes_has_link; ++ } else { ++ ret_val = e1000_check_for_copper_link_generic(hw); ++ } + + return ret_val; + } ++ + /** +- * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex ++ * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex + * @hw: pointer to the HW structure + * @speed: stores the current speed + * @duplex: stores the current duplex +@@ -716,11 +876,13 @@ + * Using the physical coding sub-layer (PCS), retrieve the current speed and + * duplex, then store the values in the pointers provided. + **/ +-static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, +- u16 *duplex) ++static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, ++ u16 *speed, u16 *duplex) + { + struct e1000_mac_info *mac = &hw->mac; + u32 pcs; ++ ++ DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); + + /* Set up defaults for the return values of this function */ + mac->serdes_has_link = false; +@@ -732,7 +894,7 @@ + * the status register is not accurate. The PCS status register is + * used instead. + */ +- pcs = rd32(E1000_PCS_LSTAT); ++ pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); + + /* + * The link up bit determines when link is up on autoneg. The sync ok +@@ -759,226 +921,193 @@ + } + } + +- return 0; ++ return E1000_SUCCESS; + } + + /** +- * igb_init_rx_addrs_82575 - Initialize receive address's ++ * e1000_shutdown_fiber_serdes_link_82575 - Remove link during power down + * @hw: pointer to the HW structure +- * @rar_count: receive address registers + * +- * Setups the receive address registers by setting the base receive address +- * register to the devices MAC address and clearing all the other receive +- * address registers to 0. ++ * In the case of fiber serdes shut down optics and PCS on driver unload ++ * when management pass thru is not enabled. + **/ +-static void igb_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count) ++void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw) + { +- u32 i; +- u8 addr[6] = {0,0,0,0,0,0}; +- /* +- * This function is essentially the same as that of +- * e1000_init_rx_addrs_generic. However it also takes care +- * of the special case where the register offset of the +- * second set of RARs begins elsewhere. This is implicitly taken care by +- * function e1000_rar_set_generic. +- */ ++ u32 reg; ++ u16 eeprom_data = 0; + +- hw_dbg("e1000_init_rx_addrs_82575"); ++ if (hw->phy.media_type != e1000_media_type_internal_serdes) ++ return; + +- /* Setup the receive address */ +- hw_dbg("Programming MAC Address into RAR[0]\n"); +- hw->mac.ops.rar_set(hw, hw->mac.addr, 0); +- +- /* Zero out the other (rar_entry_count - 1) receive addresses */ +- hw_dbg("Clearing RAR[1-%u]\n", rar_count-1); +- for (i = 1; i < rar_count; i++) +- hw->mac.ops.rar_set(hw, addr, i); +-} +- +-/** +- * igb_update_mc_addr_list_82575 - Update Multicast addresses +- * @hw: pointer to the HW structure +- * @mc_addr_list: array of multicast addresses to program +- * @mc_addr_count: number of multicast addresses to program +- * @rar_used_count: the first RAR register free to program +- * @rar_count: total number of supported Receive Address Registers +- * +- * Updates the Receive Address Registers and Multicast Table Array. +- * The caller must have a packed mc_addr_list of multicast addresses. +- * The parameter rar_count will usually be hw->mac.rar_entry_count +- * unless there are workarounds that change this. +- **/ +-void igb_update_mc_addr_list_82575(struct e1000_hw *hw, +- u8 *mc_addr_list, u32 mc_addr_count, +- u32 rar_used_count, u32 rar_count) +-{ +- u32 hash_value; +- u32 i; +- u8 addr[6] = {0,0,0,0,0,0}; +- /* +- * This function is essentially the same as that of +- * igb_update_mc_addr_list_generic. However it also takes care +- * of the special case where the register offset of the +- * second set of RARs begins elsewhere. This is implicitly taken care by +- * function e1000_rar_set_generic. +- */ ++ if (hw->bus.func == E1000_FUNC_0) ++ hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); ++ else if (hw->bus.func == E1000_FUNC_1) ++ hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); + + /* +- * Load the first set of multicast addresses into the exact +- * filters (RAR). If there are not enough to fill the RAR +- * array, clear the filters. ++ * If APM is not enabled in the EEPROM and management interface is ++ * not enabled, then power down. + */ +- for (i = rar_used_count; i < rar_count; i++) { +- if (mc_addr_count) { +- igb_rar_set(hw, mc_addr_list, i); +- mc_addr_count--; +- mc_addr_list += ETH_ALEN; +- } else { +- igb_rar_set(hw, addr, i); +- } +- } +- +- /* Clear the old settings from the MTA */ +- hw_dbg("Clearing MTA\n"); +- for (i = 0; i < hw->mac.mta_reg_count; i++) { +- array_wr32(E1000_MTA, i, 0); +- wrfl(); +- } +- +- /* Load any remaining multicast addresses into the hash table. */ +- for (; mc_addr_count > 0; mc_addr_count--) { +- hash_value = igb_hash_mc_addr(hw, mc_addr_list); +- hw_dbg("Hash value = 0x%03X\n", hash_value); +- igb_mta_set(hw, hash_value); +- mc_addr_list += ETH_ALEN; +- } +-} +- +-/** +- * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down +- * @hw: pointer to the HW structure +- * +- * In the case of fiber serdes, shut down optics and PCS on driver unload +- * when management pass thru is not enabled. +- **/ +-void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw) +-{ +- u32 reg; +- +- if (hw->mac.type != e1000_82576 || +- (hw->phy.media_type != e1000_media_type_fiber && +- hw->phy.media_type != e1000_media_type_internal_serdes)) +- return; +- +- /* if the management interface is not enabled, then power down */ +- if (!igb_enable_mng_pass_thru(hw)) { ++ if (!(eeprom_data & E1000_NVM_APME_82575) && ++ !e1000_enable_mng_pass_thru(hw)) { + /* Disable PCS to turn off link */ +- reg = rd32(E1000_PCS_CFG0); ++ reg = E1000_READ_REG(hw, E1000_PCS_CFG0); + reg &= ~E1000_PCS_CFG_PCS_EN; +- wr32(E1000_PCS_CFG0, reg); ++ E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); + + /* shutdown the laser */ +- reg = rd32(E1000_CTRL_EXT); ++ reg = E1000_READ_REG(hw, E1000_CTRL_EXT); + reg |= E1000_CTRL_EXT_SDP7_DATA; +- wr32(E1000_CTRL_EXT, reg); ++ E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); + +- /* flush the write to verify completion */ +- wrfl(); +- msleep(1); ++ /* flush the write to verfiy completion */ ++ E1000_WRITE_FLUSH(hw); ++ msec_delay(1); + } + + return; + } + + /** +- * igb_reset_hw_82575 - Reset hardware ++ * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback ++ * @hw: pointer to the HW structure ++ * @enable: state to enter, either enabled or disabled ++ * ++ * enables/disables L2 switch loopback functionality ++ **/ ++void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) ++{ ++ u32 reg; ++ ++ reg = E1000_READ_REG(hw, E1000_DTXSWC); ++ if (enable) ++ reg |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; ++ else ++ reg &= ~(E1000_DTXSWC_VMDQ_LOOPBACK_EN); ++ E1000_WRITE_REG(hw, E1000_DTXSWC, reg); ++} ++ ++/** ++ * e1000_vmdq_set_replication_pf - enable or disable vmdq replication ++ * @hw: pointer to the HW structure ++ * @enable: state to enter, either enabled or disabled ++ * ++ * enables/disables replication of packets across multiple pools ++ **/ ++void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) ++{ ++ u32 reg; ++ ++ reg = E1000_READ_REG(hw, E1000_VT_CTL); ++ if (enable) ++ reg |= E1000_VT_CTL_VM_REPL_EN; ++ else ++ reg &= ~(E1000_VT_CTL_VM_REPL_EN); ++ ++ E1000_WRITE_REG(hw, E1000_VT_CTL, reg); ++} ++ ++/** ++ * e1000_reset_hw_82575 - Reset hardware + * @hw: pointer to the HW structure + * +- * This resets the hardware into a known state. This is a +- * function pointer entry point called by the api module. ++ * This resets the hardware into a known state. + **/ +-static s32 igb_reset_hw_82575(struct e1000_hw *hw) ++static s32 e1000_reset_hw_82575(struct e1000_hw *hw) + { + u32 ctrl, icr; + s32 ret_val; ++ ++ DEBUGFUNC("e1000_reset_hw_82575"); + + /* + * Prevent the PCI-E bus from sticking if there is no TLP connection + * on the last TLP read/write transaction when MAC is reset. + */ +- ret_val = igb_disable_pcie_master(hw); +- if (ret_val) +- hw_dbg("PCI-E Master disable polling has failed.\n"); ++ ret_val = e1000_disable_pcie_master_generic(hw); ++ if (ret_val) { ++ DEBUGOUT("PCI-E Master disable polling has failed.\n"); ++ } + +- hw_dbg("Masking off all interrupts\n"); +- wr32(E1000_IMC, 0xffffffff); ++ /* set the completion timeout for interface */ ++ ret_val = e1000_set_pcie_completion_timeout(hw); ++ if (ret_val) { ++ DEBUGOUT("PCI-E Set completion timeout has failed.\n"); ++ } + +- wr32(E1000_RCTL, 0); +- wr32(E1000_TCTL, E1000_TCTL_PSP); +- wrfl(); ++ DEBUGOUT("Masking off all interrupts\n"); ++ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); + +- msleep(10); ++ E1000_WRITE_REG(hw, E1000_RCTL, 0); ++ E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); ++ E1000_WRITE_FLUSH(hw); + +- ctrl = rd32(E1000_CTRL); ++ msec_delay(10); + +- hw_dbg("Issuing a global reset to MAC\n"); +- wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); + +- ret_val = igb_get_auto_rd_done(hw); ++ DEBUGOUT("Issuing a global reset to MAC\n"); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); ++ ++ ret_val = e1000_get_auto_rd_done_generic(hw); + if (ret_val) { + /* + * When auto config read does not complete, do not + * return with an error. This can happen in situations + * where there is no eeprom and prevents getting link. + */ +- hw_dbg("Auto Read Done did not complete\n"); ++ DEBUGOUT("Auto Read Done did not complete\n"); + } + + /* If EEPROM is not present, run manual init scripts */ +- if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) +- igb_reset_init_script_82575(hw); ++ if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) ++ e1000_reset_init_script_82575(hw); + + /* Clear any pending interrupt events. */ +- wr32(E1000_IMC, 0xffffffff); +- icr = rd32(E1000_ICR); ++ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); ++ icr = E1000_READ_REG(hw, E1000_ICR); + +- igb_check_alt_mac_addr(hw); ++ /* Install any alternate MAC address into RAR0 */ ++ ret_val = e1000_check_alt_mac_addr_generic(hw); + + return ret_val; + } + + /** +- * igb_init_hw_82575 - Initialize hardware ++ * e1000_init_hw_82575 - Initialize hardware + * @hw: pointer to the HW structure + * + * This inits the hardware readying it for operation. + **/ +-static s32 igb_init_hw_82575(struct e1000_hw *hw) ++static s32 e1000_init_hw_82575(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val; + u16 i, rar_count = mac->rar_entry_count; + ++ DEBUGFUNC("e1000_init_hw_82575"); ++ + /* Initialize identification LED */ +- ret_val = igb_id_led_init(hw); ++ ret_val = mac->ops.id_led_init(hw); + if (ret_val) { +- hw_dbg("Error initializing identification LED\n"); ++ DEBUGOUT("Error initializing identification LED\n"); + /* This is not fatal and we should not stop init due to this */ + } + + /* Disabling VLAN filtering */ +- hw_dbg("Initializing the IEEE VLAN\n"); +- igb_clear_vfta(hw); ++ DEBUGOUT("Initializing the IEEE VLAN\n"); ++ mac->ops.clear_vfta(hw); + + /* Setup the receive address */ +- igb_init_rx_addrs_82575(hw, rar_count); ++ e1000_init_rx_addrs_generic(hw, rar_count); ++ + /* Zero out the Multicast HASH table */ +- hw_dbg("Zeroing the MTA\n"); ++ DEBUGOUT("Zeroing the MTA\n"); + for (i = 0; i < mac->mta_reg_count; i++) +- array_wr32(E1000_MTA, i, 0); ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); + + /* Setup link and flow control */ +- ret_val = igb_setup_link(hw); ++ ret_val = mac->ops.setup_link(hw); + + /* + * Clear all of the statistics registers (clear on read). It is +@@ -986,41 +1115,38 @@ + * because the symbol error count will increment wildly if there + * is no link. + */ +- igb_clear_hw_cntrs_82575(hw); ++ e1000_clear_hw_cntrs_82575(hw); + + return ret_val; + } + + /** +- * igb_setup_copper_link_82575 - Configure copper link settings ++ * e1000_setup_copper_link_82575 - Configure copper link settings + * @hw: pointer to the HW structure + * + * Configures the link for auto-neg or forced speed and duplex. Then we check + * for link, once link is established calls to configure collision distance + * and flow control are called. + **/ +-static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) ++static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) + { +- u32 ctrl, led_ctrl; ++ u32 ctrl; + s32 ret_val; + bool link; + +- ctrl = rd32(E1000_CTRL); ++ DEBUGFUNC("e1000_setup_copper_link_82575"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= E1000_CTRL_SLU; + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); +- wr32(E1000_CTRL, ctrl); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + switch (hw->phy.type) { + case e1000_phy_m88: +- ret_val = igb_copper_link_setup_m88(hw); ++ ret_val = e1000_copper_link_setup_m88(hw); + break; + case e1000_phy_igp_3: +- ret_val = igb_copper_link_setup_igp(hw); +- /* Setup activity LED */ +- led_ctrl = rd32(E1000_LEDCTL); +- led_ctrl &= IGP_ACTIVITY_LED_MASK; +- led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); +- wr32(E1000_LEDCTL, led_ctrl); ++ ret_val = e1000_copper_link_setup_igp(hw); + break; + default: + ret_val = -E1000_ERR_PHY; +@@ -1035,7 +1161,7 @@ + * Setup autoneg and flow control advertisement + * and perform autonegotiation. + */ +- ret_val = igb_copper_link_autoneg(hw); ++ ret_val = e1000_copper_link_autoneg(hw); + if (ret_val) + goto out; + } else { +@@ -1043,33 +1169,34 @@ + * PHY will be set to 10H, 10F, 100H or 100F + * depending on user settings. + */ +- hw_dbg("Forcing Speed and Duplex\n"); +- ret_val = igb_phy_force_speed_duplex(hw); ++ DEBUGOUT("Forcing Speed and Duplex\n"); ++ ret_val = hw->phy.ops.force_speed_duplex(hw); + if (ret_val) { +- hw_dbg("Error Forcing Speed and Duplex\n"); ++ DEBUGOUT("Error Forcing Speed and Duplex\n"); + goto out; + } + } + +- ret_val = igb_configure_pcs_link_82575(hw); +- if (ret_val) +- goto out; ++ e1000_configure_pcs_link_82575(hw); + + /* + * Check link status. Wait up to 100 microseconds for link to become + * valid. + */ +- ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); ++ ret_val = e1000_phy_has_link_generic(hw, ++ COPPER_LINK_UP_LIMIT, ++ 10, ++ &link); + if (ret_val) + goto out; + + if (link) { +- hw_dbg("Valid link established!!!\n"); ++ DEBUGOUT("Valid link established!!!\n"); + /* Config the MAC and PHY after link is up */ +- igb_config_collision_dist(hw); +- ret_val = igb_config_fc_after_link_up(hw); ++ e1000_config_collision_dist_generic(hw); ++ ret_val = e1000_config_fc_after_link_up_generic(hw); + } else { +- hw_dbg("Unable to establish link!!!\n"); ++ DEBUGOUT("Unable to establish link!!!\n"); + } + + out: +@@ -1077,14 +1204,16 @@ + } + + /** +- * igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes ++ * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes + * @hw: pointer to the HW structure + * + * Configures speed and duplex for fiber and serdes links. + **/ +-static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw) ++static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw) + { + u32 reg; ++ ++ DEBUGFUNC("e1000_setup_fiber_serdes_link_82575"); + + /* + * On the 82575, SerDes loopback mode persists until it is +@@ -1092,21 +1221,27 @@ + * the register does not indicate its status. Therefore, we ensure + * loopback mode is disabled during initialization. + */ +- wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); ++ E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); + +- /* Force link up, set 1gb, set both sw defined pins */ +- reg = rd32(E1000_CTRL); +- reg |= E1000_CTRL_SLU | +- E1000_CTRL_SPD_1000 | +- E1000_CTRL_FRCSPD | +- E1000_CTRL_SWDPIN0 | +- E1000_CTRL_SWDPIN1; +- wr32(E1000_CTRL, reg); ++ /* Force link up, set 1gb */ ++ reg = E1000_READ_REG(hw, E1000_CTRL); ++ reg |= E1000_CTRL_SLU | E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD; ++ if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { ++ /* set both sw defined pins */ ++ reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; ++ } ++ E1000_WRITE_REG(hw, E1000_CTRL, reg); ++ /* Power on phy for 82576 fiber adapters */ ++ if (hw->mac.type == e1000_82576) { ++ reg = E1000_READ_REG(hw, E1000_CTRL_EXT); ++ reg &= ~E1000_CTRL_EXT_SDP7_DATA; ++ E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); ++ } + + /* Set switch control to serdes energy detect */ +- reg = rd32(E1000_CONNSW); ++ reg = E1000_READ_REG(hw, E1000_CONNSW); + reg |= E1000_CONNSW_ENRGSRC; +- wr32(E1000_CONNSW, reg); ++ E1000_WRITE_REG(hw, E1000_CONNSW, reg); + + /* + * New SerDes mode allows for forcing speed or autonegotiating speed +@@ -1114,7 +1249,7 @@ + * mode that will be compatible with older link partners and switches. + * However, both are supported by the hardware and some drivers/tools. + */ +- reg = rd32(E1000_PCS_LCTL); ++ reg = E1000_READ_REG(hw, E1000_PCS_LCTL); + + reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | + E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); +@@ -1125,7 +1260,7 @@ + E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ + E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ + E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ +- hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); ++ DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); + } else { + /* Set PCS register for forced speed */ + reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ +@@ -1133,21 +1268,56 @@ + E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ + E1000_PCS_LCTL_FSD | /* Force Speed */ + E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ +- hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); ++ DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); + } + + if (hw->mac.type == e1000_82576) { + reg |= E1000_PCS_LCTL_FORCE_FCTRL; +- igb_force_mac_fc(hw); ++ e1000_force_mac_fc_generic(hw); + } + +- wr32(E1000_PCS_LCTL, reg); ++ E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); + +- return 0; ++ return E1000_SUCCESS; + } + + /** +- * igb_configure_pcs_link_82575 - Configure PCS link ++ * e1000_valid_led_default_82575 - Verify a valid default LED config ++ * @hw: pointer to the HW structure ++ * @data: pointer to the NVM (EEPROM) ++ * ++ * Read the EEPROM for the current default LED configuration. If the ++ * LED configuration is not valid, set to a valid LED configuration. ++ **/ ++static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) ++{ ++ s32 ret_val; ++ ++ DEBUGFUNC("e1000_valid_led_default_82575"); ++ ++ ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); ++ if (ret_val) { ++ DEBUGOUT("NVM Read Error\n"); ++ goto out; ++ } ++ ++ if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { ++ switch(hw->phy.media_type) { ++ case e1000_media_type_internal_serdes: ++ *data = ID_LED_DEFAULT_82575_SERDES; ++ break; ++ case e1000_media_type_copper: ++ default: ++ *data = ID_LED_DEFAULT; ++ break; ++ } ++ } ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_configure_pcs_link_82575 - Configure PCS link + * @hw: pointer to the HW structure + * + * Configure the physical coding sub-layer (PCS) link. The PCS link is +@@ -1155,17 +1325,19 @@ + * independent interface (sgmii) is being used. Configures the link + * for auto-negotiation or forces speed/duplex. + **/ +-static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw) ++static void e1000_configure_pcs_link_82575(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + u32 reg = 0; + ++ DEBUGFUNC("e1000_configure_pcs_link_82575"); ++ + if (hw->phy.media_type != e1000_media_type_copper || +- !(igb_sgmii_active_82575(hw))) +- goto out; ++ !(e1000_sgmii_active_82575(hw))) ++ return; + + /* For SGMII, we need to issue a PCS autoneg restart */ +- reg = rd32(E1000_PCS_LCTL); ++ reg = E1000_READ_REG(hw, E1000_PCS_LCTL); + + /* AN time out should be disabled for SGMII mode */ + reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); +@@ -1184,9 +1356,9 @@ + + /* Turn off bits for full duplex, speed, and autoneg */ + reg &= ~(E1000_PCS_LCTL_FSV_1000 | +- E1000_PCS_LCTL_FSV_100 | +- E1000_PCS_LCTL_FDV_FULL | +- E1000_PCS_LCTL_AN_ENABLE); ++ E1000_PCS_LCTL_FSV_100 | ++ E1000_PCS_LCTL_FDV_FULL | ++ E1000_PCS_LCTL_AN_ENABLE); + + /* Check for duplex first */ + if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX) +@@ -1201,157 +1373,177 @@ + E1000_PCS_LCTL_FORCE_LINK | + E1000_PCS_LCTL_FLV_LINK_UP; + +- hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n", +- reg); ++ DEBUGOUT1("Wrote 0x%08X to PCS_LCTL to configure forced link\n", ++ reg); + } +- wr32(E1000_PCS_LCTL, reg); +- +-out: +- return 0; ++ E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); + } + + /** +- * igb_sgmii_active_82575 - Return sgmii state ++ * e1000_sgmii_active_82575 - Return sgmii state + * @hw: pointer to the HW structure + * + * 82575 silicon has a serialized gigabit media independent interface (sgmii) + * which can be enabled for use in the embedded applications. Simply + * return the current state of the sgmii interface. + **/ +-static bool igb_sgmii_active_82575(struct e1000_hw *hw) ++static bool e1000_sgmii_active_82575(struct e1000_hw *hw) + { +- struct e1000_dev_spec_82575 *dev_spec; +- bool ret_val; ++ struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; ++ return dev_spec->sgmii_active; ++} + +- if (hw->mac.type != e1000_82575) { +- ret_val = false; +- goto out; ++/** ++ * e1000_reset_init_script_82575 - Inits HW defaults after reset ++ * @hw: pointer to the HW structure ++ * ++ * Inits recommended HW defaults after a reset when there is no EEPROM ++ * detected. This is only for the 82575. ++ **/ ++static s32 e1000_reset_init_script_82575(struct e1000_hw* hw) ++{ ++ DEBUGFUNC("e1000_reset_init_script_82575"); ++ ++ if (hw->mac.type == e1000_82575) { ++ DEBUGOUT("Running reset init script for 82575\n"); ++ /* SerDes configuration via SERDESCTRL */ ++ e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); ++ e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); ++ e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); ++ e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); ++ ++ /* CCM configuration via CCMCTL register */ ++ e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); ++ e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); ++ ++ /* PCIe lanes configuration */ ++ e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); ++ e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); ++ e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); ++ e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); ++ ++ /* PCIe PLL Configuration */ ++ e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); ++ e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); ++ e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); + } + +- dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec; ++ return E1000_SUCCESS; ++} + +- ret_val = dev_spec->sgmii_active; ++/** ++ * e1000_read_mac_addr_82575 - Read device MAC address ++ * @hw: pointer to the HW structure ++ **/ ++static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_read_mac_addr_82575"); ++ ++ /* ++ * If there's an alternate MAC address place it in RAR0 ++ * so that it will override the Si installed default perm ++ * address. ++ */ ++ ret_val = e1000_check_alt_mac_addr_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_read_mac_addr_generic(hw); + + out: + return ret_val; + } + + /** +- * igb_reset_init_script_82575 - Inits HW defaults after reset +- * @hw: pointer to the HW structure ++ * e1000_power_down_phy_copper_82575 - Remove link during PHY power down ++ * @hw: pointer to the HW structure + * +- * Inits recommended HW defaults after a reset when there is no EEPROM +- * detected. This is only for the 82575. ++ * In the case of a PHY power down to save power, or to turn off link during a ++ * driver unload, or wake on lan is not enabled, remove the link. + **/ +-static s32 igb_reset_init_script_82575(struct e1000_hw *hw) ++static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) + { +- if (hw->mac.type == e1000_82575) { +- hw_dbg("Running reset init script for 82575\n"); +- /* SerDes configuration via SERDESCTRL */ +- igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); +- igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); +- igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); +- igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); ++ struct e1000_phy_info *phy = &hw->phy; ++ struct e1000_mac_info *mac = &hw->mac; + +- /* CCM configuration via CCMCTL register */ +- igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); +- igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); ++ if (!(phy->ops.check_reset_block)) ++ return; + +- /* PCIe lanes configuration */ +- igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); +- igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); +- igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); +- igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); ++ /* If the management interface is not enabled, then power down */ ++ if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) ++ e1000_power_down_phy_copper(hw); + +- /* PCIe PLL Configuration */ +- igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); +- igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); +- igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); +- } +- +- return 0; ++ return; + } + + /** +- * igb_read_mac_addr_82575 - Read device MAC address +- * @hw: pointer to the HW structure +- **/ +-static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) +-{ +- s32 ret_val = 0; +- +- if (igb_check_alt_mac_addr(hw)) +- ret_val = igb_read_mac_addr(hw); +- +- return ret_val; +-} +- +-/** +- * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters ++ * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters + * @hw: pointer to the HW structure + * + * Clears the hardware counters by reading the counter registers. + **/ +-static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) ++static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) + { +- u32 temp; ++ DEBUGFUNC("e1000_clear_hw_cntrs_82575"); + +- igb_clear_hw_cntrs_base(hw); ++ e1000_clear_hw_cntrs_base_generic(hw); + +- temp = rd32(E1000_PRC64); +- temp = rd32(E1000_PRC127); +- temp = rd32(E1000_PRC255); +- temp = rd32(E1000_PRC511); +- temp = rd32(E1000_PRC1023); +- temp = rd32(E1000_PRC1522); +- temp = rd32(E1000_PTC64); +- temp = rd32(E1000_PTC127); +- temp = rd32(E1000_PTC255); +- temp = rd32(E1000_PTC511); +- temp = rd32(E1000_PTC1023); +- temp = rd32(E1000_PTC1522); ++ E1000_READ_REG(hw, E1000_PRC64); ++ E1000_READ_REG(hw, E1000_PRC127); ++ E1000_READ_REG(hw, E1000_PRC255); ++ E1000_READ_REG(hw, E1000_PRC511); ++ E1000_READ_REG(hw, E1000_PRC1023); ++ E1000_READ_REG(hw, E1000_PRC1522); ++ E1000_READ_REG(hw, E1000_PTC64); ++ E1000_READ_REG(hw, E1000_PTC127); ++ E1000_READ_REG(hw, E1000_PTC255); ++ E1000_READ_REG(hw, E1000_PTC511); ++ E1000_READ_REG(hw, E1000_PTC1023); ++ E1000_READ_REG(hw, E1000_PTC1522); + +- temp = rd32(E1000_ALGNERRC); +- temp = rd32(E1000_RXERRC); +- temp = rd32(E1000_TNCRS); +- temp = rd32(E1000_CEXTERR); +- temp = rd32(E1000_TSCTC); +- temp = rd32(E1000_TSCTFC); ++ E1000_READ_REG(hw, E1000_ALGNERRC); ++ E1000_READ_REG(hw, E1000_RXERRC); ++ E1000_READ_REG(hw, E1000_TNCRS); ++ E1000_READ_REG(hw, E1000_CEXTERR); ++ E1000_READ_REG(hw, E1000_TSCTC); ++ E1000_READ_REG(hw, E1000_TSCTFC); + +- temp = rd32(E1000_MGTPRC); +- temp = rd32(E1000_MGTPDC); +- temp = rd32(E1000_MGTPTC); ++ E1000_READ_REG(hw, E1000_MGTPRC); ++ E1000_READ_REG(hw, E1000_MGTPDC); ++ E1000_READ_REG(hw, E1000_MGTPTC); + +- temp = rd32(E1000_IAC); +- temp = rd32(E1000_ICRXOC); ++ E1000_READ_REG(hw, E1000_IAC); ++ E1000_READ_REG(hw, E1000_ICRXOC); + +- temp = rd32(E1000_ICRXPTC); +- temp = rd32(E1000_ICRXATC); +- temp = rd32(E1000_ICTXPTC); +- temp = rd32(E1000_ICTXATC); +- temp = rd32(E1000_ICTXQEC); +- temp = rd32(E1000_ICTXQMTC); +- temp = rd32(E1000_ICRXDMTC); ++ E1000_READ_REG(hw, E1000_ICRXPTC); ++ E1000_READ_REG(hw, E1000_ICRXATC); ++ E1000_READ_REG(hw, E1000_ICTXPTC); ++ E1000_READ_REG(hw, E1000_ICTXATC); ++ E1000_READ_REG(hw, E1000_ICTXQEC); ++ E1000_READ_REG(hw, E1000_ICTXQMTC); ++ E1000_READ_REG(hw, E1000_ICRXDMTC); + +- temp = rd32(E1000_CBTMPC); +- temp = rd32(E1000_HTDPMC); +- temp = rd32(E1000_CBRMPC); +- temp = rd32(E1000_RPTHC); +- temp = rd32(E1000_HGPTC); +- temp = rd32(E1000_HTCBDPC); +- temp = rd32(E1000_HGORCL); +- temp = rd32(E1000_HGORCH); +- temp = rd32(E1000_HGOTCL); +- temp = rd32(E1000_HGOTCH); +- temp = rd32(E1000_LENERRS); ++ E1000_READ_REG(hw, E1000_CBTMPC); ++ E1000_READ_REG(hw, E1000_HTDPMC); ++ E1000_READ_REG(hw, E1000_CBRMPC); ++ E1000_READ_REG(hw, E1000_RPTHC); ++ E1000_READ_REG(hw, E1000_HGPTC); ++ E1000_READ_REG(hw, E1000_HTCBDPC); ++ E1000_READ_REG(hw, E1000_HGORCL); ++ E1000_READ_REG(hw, E1000_HGORCH); ++ E1000_READ_REG(hw, E1000_HGOTCL); ++ E1000_READ_REG(hw, E1000_HGOTCH); ++ E1000_READ_REG(hw, E1000_LENERRS); + + /* This register should not be read in copper configurations */ + if (hw->phy.media_type == e1000_media_type_internal_serdes) +- temp = rd32(E1000_SCVPC); ++ E1000_READ_REG(hw, E1000_SCVPC); + } + + /** +- * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable ++ * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable + * @hw: pointer to the HW structure + * + * After rx enable if managability is enabled then there is likely some +@@ -1359,96 +1551,119 @@ + * function clears the fifos and flushes any packets that came in as rx was + * being enabled. + **/ +-void igb_rx_fifo_flush_82575(struct e1000_hw *hw) ++void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) + { + u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; + int i, ms_wait; + ++ DEBUGFUNC("e1000_rx_fifo_workaround_82575"); + if (hw->mac.type != e1000_82575 || +- !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) ++ !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) + return; + + /* Disable all RX queues */ + for (i = 0; i < 4; i++) { +- rxdctl[i] = rd32(E1000_RXDCTL(i)); +- wr32(E1000_RXDCTL(i), +- rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); ++ rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); ++ E1000_WRITE_REG(hw, E1000_RXDCTL(i), ++ rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); + } + /* Poll all queues to verify they have shut down */ + for (ms_wait = 0; ms_wait < 10; ms_wait++) { +- msleep(1); ++ msec_delay(1); + rx_enabled = 0; + for (i = 0; i < 4; i++) +- rx_enabled |= rd32(E1000_RXDCTL(i)); ++ rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); + if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) + break; + } + + if (ms_wait == 10) +- hw_dbg("Queue disable timed out after 10ms\n"); ++ DEBUGOUT("Queue disable timed out after 10ms\n"); + + /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all + * incoming packets are rejected. Set enable and wait 2ms so that + * any packet that was coming in as RCTL.EN was set is flushed + */ +- rfctl = rd32(E1000_RFCTL); +- wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); ++ rfctl = E1000_READ_REG(hw, E1000_RFCTL); ++ E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); + +- rlpml = rd32(E1000_RLPML); +- wr32(E1000_RLPML, 0); ++ rlpml = E1000_READ_REG(hw, E1000_RLPML); ++ E1000_WRITE_REG(hw, E1000_RLPML, 0); + +- rctl = rd32(E1000_RCTL); ++ rctl = E1000_READ_REG(hw, E1000_RCTL); + temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); + temp_rctl |= E1000_RCTL_LPE; + +- wr32(E1000_RCTL, temp_rctl); +- wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); +- wrfl(); +- msleep(2); ++ E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); ++ E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); ++ E1000_WRITE_FLUSH(hw); ++ msec_delay(2); + + /* Enable RX queues that were previously enabled and restore our + * previous state + */ + for (i = 0; i < 4; i++) +- wr32(E1000_RXDCTL(i), rxdctl[i]); +- wr32(E1000_RCTL, rctl); +- wrfl(); ++ E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); ++ E1000_WRITE_FLUSH(hw); + +- wr32(E1000_RLPML, rlpml); +- wr32(E1000_RFCTL, rfctl); ++ E1000_WRITE_REG(hw, E1000_RLPML, rlpml); ++ E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); + + /* Flush receive errors generated by workaround */ +- rd32(E1000_ROC); +- rd32(E1000_RNBC); +- rd32(E1000_MPC); ++ E1000_READ_REG(hw, E1000_ROC); ++ E1000_READ_REG(hw, E1000_RNBC); ++ E1000_READ_REG(hw, E1000_MPC); + } + +-static struct e1000_mac_operations e1000_mac_ops_82575 = { +- .reset_hw = igb_reset_hw_82575, +- .init_hw = igb_init_hw_82575, +- .check_for_link = igb_check_for_link_82575, +- .rar_set = igb_rar_set, +- .read_mac_addr = igb_read_mac_addr_82575, +- .get_speed_and_duplex = igb_get_speed_and_duplex_copper, +-}; ++/** ++ * e1000_set_pcie_completion_timeout - set pci-e completion timeout ++ * @hw: pointer to the HW structure ++ * ++ * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, ++ * however the hardware default for these parts is 500us to 1ms which is less ++ * than the 10ms recommended by the pci-e spec. To address this we need to ++ * increase the value to either 10ms to 200ms for capability version 1 config, ++ * or 16ms to 55ms for version 2. ++ **/ ++static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) ++{ ++ u32 gcr = E1000_READ_REG(hw, E1000_GCR); ++ s32 ret_val = E1000_SUCCESS; ++ u16 pcie_devctl2; + +-static struct e1000_phy_operations e1000_phy_ops_82575 = { +- .acquire_phy = igb_acquire_phy_82575, +- .get_cfg_done = igb_get_cfg_done_82575, +- .release_phy = igb_release_phy_82575, +-}; ++ /* only take action if timeout value is defaulted to 0 */ ++ if (gcr & E1000_GCR_CMPL_TMOUT_MASK) ++ goto out; + +-static struct e1000_nvm_operations e1000_nvm_ops_82575 = { +- .acquire_nvm = igb_acquire_nvm_82575, +- .read_nvm = igb_read_nvm_eerd, +- .release_nvm = igb_release_nvm_82575, +- .write_nvm = igb_write_nvm_spi, +-}; ++ /* ++ * if capababilities version is type 1 we can write the ++ * timeout of 10ms to 200ms through the GCR register ++ */ ++ if (!(gcr & E1000_GCR_CAP_VER2)) { ++ gcr |= E1000_GCR_CMPL_TMOUT_10ms; ++ goto out; ++ } + +-const struct e1000_info e1000_82575_info = { +- .get_invariants = igb_get_invariants_82575, +- .mac_ops = &e1000_mac_ops_82575, +- .phy_ops = &e1000_phy_ops_82575, +- .nvm_ops = &e1000_nvm_ops_82575, +-}; ++ /* ++ * for version 2 capabilities we need to write the config space ++ * directly in order to set the completion timeout value for ++ * 16ms to 55ms ++ */ ++ ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, ++ &pcie_devctl2); ++ if (ret_val) ++ goto out; + ++ pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; ++ ++ ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, ++ &pcie_devctl2); ++out: ++ /* disable completion timeout resend */ ++ gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; ++ ++ E1000_WRITE_REG(hw, E1000_GCR, gcr); ++ return ret_val; ++} ++ +diff -r 4f0f8bc35440 drivers/net/igb/e1000_82575.h +--- a/drivers/net/igb/e1000_82575.h Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/e1000_82575.h Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 - 2008 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -28,23 +28,117 @@ + #ifndef _E1000_82575_H_ + #define _E1000_82575_H_ + +-void igb_update_mc_addr_list_82575(struct e1000_hw*, u8*, u32, u32, u32); +-extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw); +-extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); +- ++#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ ++ (ID_LED_DEF1_DEF2 << 8) | \ ++ (ID_LED_DEF1_DEF2 << 4) | \ ++ (ID_LED_OFF1_ON2)) ++/* ++ * Receive Address Register Count ++ * Number of high/low register pairs in the RAR. The RAR (Receive Address ++ * Registers) holds the directed and multicast addresses that we monitor. ++ * These entries are also used for MAC-based filtering. ++ */ ++/* ++ * For 82576, there are an additional set of RARs that begin at an offset ++ * separate from the first set of RARs. ++ */ + #define E1000_RAR_ENTRIES_82575 16 + #define E1000_RAR_ENTRIES_82576 24 + ++struct e1000_adv_data_desc { ++ __le64 buffer_addr; /* Address of the descriptor's data buffer */ ++ union { ++ u32 data; ++ struct { ++ u32 datalen :16; /* Data buffer length */ ++ u32 rsvd :4; ++ u32 dtyp :4; /* Descriptor type */ ++ u32 dcmd :8; /* Descriptor command */ ++ } config; ++ } lower; ++ union { ++ u32 data; ++ struct { ++ u32 status :4; /* Descriptor status */ ++ u32 idx :4; ++ u32 popts :6; /* Packet Options */ ++ u32 paylen :18; /* Payload length */ ++ } options; ++ } upper; ++}; ++ ++#define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */ ++#define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */ ++#define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */ ++#define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */ ++#define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */ ++#define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */ ++#define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */ ++#define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */ ++#define E1000_ADV_DCMD_EOP 0x1 /* End of Packet */ ++#define E1000_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */ ++#define E1000_ADV_DCMD_RS 0x8 /* Report Status */ ++#define E1000_ADV_DCMD_VLE 0x40 /* Add VLAN tag */ ++#define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */ ++/* Extended Device Control */ ++#define E1000_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */ ++ ++struct e1000_adv_context_desc { ++ union { ++ u32 ip_config; ++ struct { ++ u32 iplen :9; ++ u32 maclen :7; ++ u32 vlan_tag :16; ++ } fields; ++ } ip_setup; ++ u32 seq_num; ++ union { ++ u64 l4_config; ++ struct { ++ u32 mkrloc :9; ++ u32 tucmd :11; ++ u32 dtyp :4; ++ u32 adv :8; ++ u32 rsvd :4; ++ u32 idx :4; ++ u32 l4len :8; ++ u32 mss :16; ++ } fields; ++ } l4_setup; ++}; ++ + /* SRRCTL bit definitions */ + #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ ++#define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 + #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ ++#define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 + #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 ++#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 + #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 ++#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 ++#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 ++#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 ++#define E1000_SRRCTL_DROP_EN 0x80000000 ++ ++#define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F ++#define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 ++ ++#define E1000_TX_HEAD_WB_ENABLE 0x1 ++#define E1000_TX_SEQNUM_WB_ENABLE 0x2 + + #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002 ++#define E1000_MRQC_ENABLE_VMDQ 0x00000003 ++#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 + #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 + #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 + #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 ++ ++#define E1000_VMRCTL_MIRROR_PORT_SHIFT 8 ++#define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT) ++#define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0) ++#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1) ++#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2) + + #define E1000_EICR_TX_QUEUE ( \ + E1000_EICR_TX_QUEUE0 | \ +@@ -61,7 +155,23 @@ + #define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE + #define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE + ++#define EIMS_ENABLE_MASK ( \ ++ E1000_EIMS_RX_QUEUE | \ ++ E1000_EIMS_TX_QUEUE | \ ++ E1000_EIMS_TCP_TIMER | \ ++ E1000_EIMS_OTHER) ++ + /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ ++#define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ ++#define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ ++#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ ++#define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ ++#define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ ++#define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ ++#define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ ++#define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ ++#define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ ++#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ + + /* Receive Descriptor - Advanced */ + union e1000_adv_rx_desc { +@@ -71,10 +181,13 @@ + } read; + struct { + struct { +- struct { +- __le16 pkt_info; /* RSS type, Packet type */ +- __le16 hdr_info; /* Split Header, +- * header buffer length */ ++ union { ++ __le32 data; ++ struct { ++ __le16 pkt_info; /*RSS type, Pkt type*/ ++ __le16 hdr_info; /* Split Header, ++ * header buffer len*/ ++ } hs_rss; + } lo_dword; + union { + __le32 rss; /* RSS Hash */ +@@ -92,14 +205,58 @@ + } wb; /* writeback */ + }; + ++#define E1000_RXDADV_RSSTYPE_MASK 0x0000000F ++#define E1000_RXDADV_RSSTYPE_SHIFT 12 + #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 + #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 ++#define E1000_RXDADV_SPLITHEADER_EN 0x00001000 ++#define E1000_RXDADV_SPH 0x8000 ++#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ ++#define E1000_RXDADV_ERR_HBO 0x00800000 + + /* RSS Hash results */ ++#define E1000_RXDADV_RSSTYPE_NONE 0x00000000 ++#define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 ++#define E1000_RXDADV_RSSTYPE_IPV4 0x00000002 ++#define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 ++#define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004 ++#define E1000_RXDADV_RSSTYPE_IPV6 0x00000005 ++#define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 ++#define E1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 ++#define E1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 ++#define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 + + /* RSS Packet Types as indicated in the receive descriptor */ ++#define E1000_RXDADV_PKTTYPE_NONE 0x00000000 + #define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ ++#define E1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */ ++#define E1000_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */ ++#define E1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */ + #define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ ++#define E1000_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ ++#define E1000_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ ++#define E1000_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ ++ ++#define E1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ ++#define E1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ ++#define E1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ ++#define E1000_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ ++#define E1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ ++#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ ++ ++/* LinkSec results */ ++/* Security Processing bit Indication */ ++#define E1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000 ++#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 ++#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 ++#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 ++#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 ++ ++#define E1000_RXDADV_IPSEC_STATUS_SECP 0x00020000 ++#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 ++#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 ++#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 ++#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000 + + /* Transmit Descriptor - Advanced */ + union e1000_adv_tx_desc { +@@ -118,10 +275,22 @@ + /* Adv Transmit Descriptor Config Masks */ + #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ + #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ ++#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ + #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ ++#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ ++#define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ + #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ + #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ + #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ ++#define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on packet */ ++#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */ ++#define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */ ++#define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ ++#define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ ++#define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ ++#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ ++#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/ ++#define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ + #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ + + /* Context descriptors */ +@@ -133,20 +302,32 @@ + }; + + #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ ++#define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ + #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ ++#define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ ++#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ + #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ ++#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ ++#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ + /* IPSec Encrypt Enable for ESP */ ++#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 ++#define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */ + #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ + #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ + /* Adv ctxt IPSec SA IDX mask */ ++#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF + /* Adv ctxt IPSec ESP len mask */ ++#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF + + /* Additional Transmit Descriptor Control definitions */ + #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ ++#define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ + /* Tx Queue Arbitration Priority 0=low, 1=high */ ++#define E1000_TXDCTL_PRIORITY 0x08000000 + + /* Additional Receive Descriptor Control definitions */ + #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ ++#define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ + + /* Direct Cache Access (DCA) definitions */ + #define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ +@@ -164,10 +345,87 @@ + #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ + #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ + +-/* Additional DCA related definitions, note change in position of CPUID */ + #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ + #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ +-#define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */ +-#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */ ++#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */ ++#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */ + +-#endif ++/* Additional interrupt register bit definitions */ ++#define E1000_ICR_LSECPNS 0x00000020 /* PN threshold - server */ ++#define E1000_IMS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ ++#define E1000_ICS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ ++ ++/* ETQF register bit definitions */ ++#define E1000_ETQF_FILTER_ENABLE (1 << 26) ++#define E1000_ETQF_IMM_INT (1 << 29) ++#define E1000_ETQF_1588 (1 << 30) ++#define E1000_ETQF_QUEUE_ENABLE (1 << 31) ++/* ++ * ETQF filter list: one static filter per filter consumer. This is ++ * to avoid filter collisions later. Add new filters ++ * here!! ++ * ++ * Current filters: ++ * EAPOL 802.1x (0x888e): Filter 0 ++ */ ++#define E1000_ETQF_FILTER_EAPOL 0 ++ ++#define E1000_FTQF_VF_BP 0x00008000 ++#define E1000_FTQF_1588_TIME_STAMP 0x08000000 ++#define E1000_FTQF_MASK 0xF0000000 ++#define E1000_FTQF_MASK_PROTO_BP 0x10000000 ++#define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000 ++#define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000 ++#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000 ++ ++#define E1000_NVM_APME_82575 0x0400 ++#define MAX_NUM_VFS 8 ++ ++#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */ ++#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */ ++#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ ++#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 ++#define E1000_DTXSWC_LLE_SHIFT 16 ++#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ ++ ++/* Easy defines for setting default pool, would normally be left a zero */ ++#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 ++#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) ++ ++/* Other useful VMD_CTL register defines */ ++#define E1000_VT_CTL_IGNORE_MAC (1 << 28) ++#define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) ++#define E1000_VT_CTL_VM_REPL_EN (1 << 30) ++ ++/* Per VM Offload register setup */ ++#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ ++#define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */ ++#define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */ ++#define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */ ++#define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */ ++#define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */ ++#define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */ ++#define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */ ++#define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ ++#define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */ ++ ++#define E1000_VLVF_ARRAY_SIZE 32 ++#define E1000_VLVF_VLANID_MASK 0x00000FFF ++#define E1000_VLVF_POOLSEL_SHIFT 12 ++#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) ++#define E1000_VLVF_LVLAN 0x00100000 ++#define E1000_VLVF_VLANID_ENABLE 0x80000000 ++ ++#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ ++ ++#define E1000_IOVCTL 0x05BBC ++#define E1000_IOVCTL_REUSE_VFQ 0x00000001 ++ ++#define E1000_RPLOLR_STRVLAN 0x40000000 ++#define E1000_RPLOLR_STRCRC 0x80000000 ++ ++#define ALL_QUEUES 0xFFFF ++ ++void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable); ++void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable); ++#endif /* _E1000_82575_H_ */ +diff -r 4f0f8bc35440 drivers/net/igb/e1000_api.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/igb/e1000_api.c Wed Aug 05 11:03:37 2009 +0100 +@@ -0,0 +1,1065 @@ ++/******************************************************************************* ++ ++ Intel(R) Gigabit Ethernet Linux driver ++ Copyright(c) 2007-2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000_api.h" ++ ++/** ++ * e1000_init_mac_params - Initialize MAC function pointers ++ * @hw: pointer to the HW structure ++ * ++ * This function initializes the function pointers for the MAC ++ * set of functions. Called by drivers or by e1000_setup_init_funcs. ++ **/ ++s32 e1000_init_mac_params(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->mac.ops.init_params) { ++ ret_val = hw->mac.ops.init_params(hw); ++ if (ret_val) { ++ DEBUGOUT("MAC Initialization Error\n"); ++ goto out; ++ } ++ } else { ++ DEBUGOUT("mac.init_mac_params was NULL\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_nvm_params - Initialize NVM function pointers ++ * @hw: pointer to the HW structure ++ * ++ * This function initializes the function pointers for the NVM ++ * set of functions. Called by drivers or by e1000_setup_init_funcs. ++ **/ ++s32 e1000_init_nvm_params(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->nvm.ops.init_params) { ++ ret_val = hw->nvm.ops.init_params(hw); ++ if (ret_val) { ++ DEBUGOUT("NVM Initialization Error\n"); ++ goto out; ++ } ++ } else { ++ DEBUGOUT("nvm.init_nvm_params was NULL\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_phy_params - Initialize PHY function pointers ++ * @hw: pointer to the HW structure ++ * ++ * This function initializes the function pointers for the PHY ++ * set of functions. Called by drivers or by e1000_setup_init_funcs. ++ **/ ++s32 e1000_init_phy_params(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->phy.ops.init_params) { ++ ret_val = hw->phy.ops.init_params(hw); ++ if (ret_val) { ++ DEBUGOUT("PHY Initialization Error\n"); ++ goto out; ++ } ++ } else { ++ DEBUGOUT("phy.init_phy_params was NULL\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ } ++ ++out: ++ return ret_val; ++} ++ ++ ++/** ++ * e1000_set_mac_type - Sets MAC type ++ * @hw: pointer to the HW structure ++ * ++ * This function sets the mac type of the adapter based on the ++ * device ID stored in the hw structure. ++ * MUST BE FIRST FUNCTION CALLED (explicitly or through ++ * e1000_setup_init_funcs()). ++ **/ ++s32 e1000_set_mac_type(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_set_mac_type"); ++ ++ switch (hw->device_id) { ++ case E1000_DEV_ID_82575EB_COPPER: ++ case E1000_DEV_ID_82575EB_FIBER_SERDES: ++ case E1000_DEV_ID_82575GB_QUAD_COPPER: ++ mac->type = e1000_82575; ++ break; ++ case E1000_DEV_ID_82576: ++ case E1000_DEV_ID_82576_FIBER: ++ case E1000_DEV_ID_82576_SERDES: ++ case E1000_DEV_ID_82576_QUAD_COPPER: ++ case E1000_DEV_ID_82576_NS: ++ case E1000_DEV_ID_82576_SERDES_QUAD: ++ mac->type = e1000_82576; ++ break; ++ default: ++ /* Should never have loaded on this device */ ++ ret_val = -E1000_ERR_MAC_INIT; ++ break; ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_init_funcs - Initializes function pointers ++ * @hw: pointer to the HW structure ++ * @init_device: true will initialize the rest of the function pointers ++ * getting the device ready for use. false will only set ++ * MAC type and the function pointers for the other init ++ * functions. Passing false will not generate any hardware ++ * reads or writes. ++ * ++ * This function must be called by a driver in order to use the rest ++ * of the 'shared' code files. Called by drivers only. ++ **/ ++s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device) ++{ ++ s32 ret_val; ++ ++ /* Can't do much good without knowing the MAC type. */ ++ ret_val = e1000_set_mac_type(hw); ++ if (ret_val) { ++ DEBUGOUT("ERROR: MAC type could not be set properly.\n"); ++ goto out; ++ } ++ ++ if (!hw->hw_addr) { ++ DEBUGOUT("ERROR: Registers not mapped\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ /* ++ * Init function pointers to generic implementations. We do this first ++ * allowing a driver module to override it afterward. ++ */ ++ e1000_init_mac_ops_generic(hw); ++ e1000_init_nvm_ops_generic(hw); ++ ++ /* ++ * Set up the init function pointers. These are functions within the ++ * adapter family file that sets up function pointers for the rest of ++ * the functions in that family. ++ */ ++ switch (hw->mac.type) { ++ case e1000_82575: ++ case e1000_82576: ++ e1000_init_function_pointers_82575(hw); ++ break; ++ default: ++ DEBUGOUT("Hardware not supported\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ break; ++ } ++ ++ /* ++ * Initialize the rest of the function pointers. These require some ++ * register reads/writes in some cases. ++ */ ++ if (!(ret_val) && init_device) { ++ ret_val = e1000_init_mac_params(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_init_nvm_params(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_init_phy_params(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_bus_info - Obtain bus information for adapter ++ * @hw: pointer to the HW structure ++ * ++ * This will obtain information about the HW bus for which the ++ * adapter is attached and stores it in the hw structure. This is a ++ * function pointer entry point called by drivers. ++ **/ ++s32 e1000_get_bus_info(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.get_bus_info) ++ return hw->mac.ops.get_bus_info(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_clear_vfta - Clear VLAN filter table ++ * @hw: pointer to the HW structure ++ * ++ * This clears the VLAN filter table on the adapter. This is a function ++ * pointer entry point called by drivers. ++ **/ ++void e1000_clear_vfta(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.clear_vfta) ++ hw->mac.ops.clear_vfta(hw); ++} ++ ++/** ++ * e1000_write_vfta - Write value to VLAN filter table ++ * @hw: pointer to the HW structure ++ * @offset: the 32-bit offset in which to write the value to. ++ * @value: the 32-bit value to write at location offset. ++ * ++ * This writes a 32-bit value to a 32-bit offset in the VLAN filter ++ * table. This is a function pointer entry point called by drivers. ++ **/ ++void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) ++{ ++ if (hw->mac.ops.write_vfta) ++ hw->mac.ops.write_vfta(hw, offset, value); ++} ++ ++/** ++ * e1000_update_mc_addr_list - Update Multicast addresses ++ * @hw: pointer to the HW structure ++ * @mc_addr_list: array of multicast addresses to program ++ * @mc_addr_count: number of multicast addresses to program ++ * ++ * Updates the Multicast Table Array. ++ * The caller must have a packed mc_addr_list of multicast addresses. ++ **/ ++void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list, ++ u32 mc_addr_count) ++{ ++ if (hw->mac.ops.update_mc_addr_list) ++ hw->mac.ops.update_mc_addr_list(hw, mc_addr_list, ++ mc_addr_count); ++} ++ ++/** ++ * e1000_force_mac_fc - Force MAC flow control ++ * @hw: pointer to the HW structure ++ * ++ * Force the MAC's flow control settings. Currently no func pointer exists ++ * and all implementations are handled in the generic version of this ++ * function. ++ **/ ++s32 e1000_force_mac_fc(struct e1000_hw *hw) ++{ ++ return e1000_force_mac_fc_generic(hw); ++} ++ ++/** ++ * e1000_check_for_link - Check/Store link connection ++ * @hw: pointer to the HW structure ++ * ++ * This checks the link condition of the adapter and stores the ++ * results in the hw->mac structure. This is a function pointer entry ++ * point called by drivers. ++ **/ ++s32 e1000_check_for_link(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.check_for_link) ++ return hw->mac.ops.check_for_link(hw); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_check_mng_mode - Check management mode ++ * @hw: pointer to the HW structure ++ * ++ * This checks if the adapter has manageability enabled. ++ * This is a function pointer entry point called by drivers. ++ **/ ++bool e1000_check_mng_mode(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.check_mng_mode) ++ return hw->mac.ops.check_mng_mode(hw); ++ ++ return false; ++} ++ ++/** ++ * e1000_mng_write_dhcp_info - Writes DHCP info to host interface ++ * @hw: pointer to the HW structure ++ * @buffer: pointer to the host interface ++ * @length: size of the buffer ++ * ++ * Writes the DHCP information to the host interface. ++ **/ ++s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) ++{ ++ return e1000_mng_write_dhcp_info_generic(hw, buffer, length); ++} ++ ++/** ++ * e1000_reset_hw - Reset hardware ++ * @hw: pointer to the HW structure ++ * ++ * This resets the hardware into a known state. This is a function pointer ++ * entry point called by drivers. ++ **/ ++s32 e1000_reset_hw(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.reset_hw) ++ return hw->mac.ops.reset_hw(hw); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_init_hw - Initialize hardware ++ * @hw: pointer to the HW structure ++ * ++ * This inits the hardware readying it for operation. This is a function ++ * pointer entry point called by drivers. ++ **/ ++s32 e1000_init_hw(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.init_hw) ++ return hw->mac.ops.init_hw(hw); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_setup_link - Configures link and flow control ++ * @hw: pointer to the HW structure ++ * ++ * This configures link and flow control settings for the adapter. This ++ * is a function pointer entry point called by drivers. While modules can ++ * also call this, they probably call their own version of this function. ++ **/ ++s32 e1000_setup_link(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.setup_link) ++ return hw->mac.ops.setup_link(hw); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_get_speed_and_duplex - Returns current speed and duplex ++ * @hw: pointer to the HW structure ++ * @speed: pointer to a 16-bit value to store the speed ++ * @duplex: pointer to a 16-bit value to store the duplex. ++ * ++ * This returns the speed and duplex of the adapter in the two 'out' ++ * variables passed in. This is a function pointer entry point called ++ * by drivers. ++ **/ ++s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) ++{ ++ if (hw->mac.ops.get_link_up_info) ++ return hw->mac.ops.get_link_up_info(hw, speed, duplex); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_setup_led - Configures SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * This prepares the SW controllable LED for use and saves the current state ++ * of the LED so it can be later restored. This is a function pointer entry ++ * point called by drivers. ++ **/ ++s32 e1000_setup_led(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.setup_led) ++ return hw->mac.ops.setup_led(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_cleanup_led - Restores SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * This restores the SW controllable LED to the value saved off by ++ * e1000_setup_led. This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_cleanup_led(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.cleanup_led) ++ return hw->mac.ops.cleanup_led(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_blink_led - Blink SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * This starts the adapter LED blinking. Request the LED to be setup first ++ * and cleaned up after. This is a function pointer entry point called by ++ * drivers. ++ **/ ++s32 e1000_blink_led(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.blink_led) ++ return hw->mac.ops.blink_led(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_id_led_init - store LED configurations in SW ++ * @hw: pointer to the HW structure ++ * ++ * Initializes the LED config in SW. This is a function pointer entry point ++ * called by drivers. ++ **/ ++s32 e1000_id_led_init(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.id_led_init) ++ return hw->mac.ops.id_led_init(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_led_on - Turn on SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * Turns the SW defined LED on. This is a function pointer entry point ++ * called by drivers. ++ **/ ++s32 e1000_led_on(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.led_on) ++ return hw->mac.ops.led_on(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_led_off - Turn off SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * Turns the SW defined LED off. This is a function pointer entry point ++ * called by drivers. ++ **/ ++s32 e1000_led_off(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.led_off) ++ return hw->mac.ops.led_off(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_reset_adaptive - Reset adaptive IFS ++ * @hw: pointer to the HW structure ++ * ++ * Resets the adaptive IFS. Currently no func pointer exists and all ++ * implementations are handled in the generic version of this function. ++ **/ ++void e1000_reset_adaptive(struct e1000_hw *hw) ++{ ++ e1000_reset_adaptive_generic(hw); ++} ++ ++/** ++ * e1000_update_adaptive - Update adaptive IFS ++ * @hw: pointer to the HW structure ++ * ++ * Updates adapter IFS. Currently no func pointer exists and all ++ * implementations are handled in the generic version of this function. ++ **/ ++void e1000_update_adaptive(struct e1000_hw *hw) ++{ ++ e1000_update_adaptive_generic(hw); ++} ++ ++/** ++ * e1000_disable_pcie_master - Disable PCI-Express master access ++ * @hw: pointer to the HW structure ++ * ++ * Disables PCI-Express master access and verifies there are no pending ++ * requests. Currently no func pointer exists and all implementations are ++ * handled in the generic version of this function. ++ **/ ++s32 e1000_disable_pcie_master(struct e1000_hw *hw) ++{ ++ return e1000_disable_pcie_master_generic(hw); ++} ++ ++/** ++ * e1000_config_collision_dist - Configure collision distance ++ * @hw: pointer to the HW structure ++ * ++ * Configures the collision distance to the default value and is used ++ * during link setup. ++ **/ ++void e1000_config_collision_dist(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.config_collision_dist) ++ hw->mac.ops.config_collision_dist(hw); ++} ++ ++/** ++ * e1000_rar_set - Sets a receive address register ++ * @hw: pointer to the HW structure ++ * @addr: address to set the RAR to ++ * @index: the RAR to set ++ * ++ * Sets a Receive Address Register (RAR) to the specified address. ++ **/ ++void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) ++{ ++ if (hw->mac.ops.rar_set) ++ hw->mac.ops.rar_set(hw, addr, index); ++} ++ ++/** ++ * e1000_validate_mdi_setting - Ensures valid MDI/MDIX SW state ++ * @hw: pointer to the HW structure ++ * ++ * Ensures that the MDI/MDIX SW state is valid. ++ **/ ++s32 e1000_validate_mdi_setting(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.validate_mdi_setting) ++ return hw->mac.ops.validate_mdi_setting(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_mta_set - Sets multicast table bit ++ * @hw: pointer to the HW structure ++ * @hash_value: Multicast hash value. ++ * ++ * This sets the bit in the multicast table corresponding to the ++ * hash value. This is a function pointer entry point called by drivers. ++ **/ ++void e1000_mta_set(struct e1000_hw *hw, u32 hash_value) ++{ ++ if (hw->mac.ops.mta_set) ++ hw->mac.ops.mta_set(hw, hash_value); ++} ++ ++/** ++ * e1000_hash_mc_addr - Determines address location in multicast table ++ * @hw: pointer to the HW structure ++ * @mc_addr: Multicast address to hash. ++ * ++ * This hashes an address to determine its location in the multicast ++ * table. Currently no func pointer exists and all implementations ++ * are handled in the generic version of this function. ++ **/ ++u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) ++{ ++ return e1000_hash_mc_addr_generic(hw, mc_addr); ++} ++ ++/** ++ * e1000_enable_tx_pkt_filtering - Enable packet filtering on TX ++ * @hw: pointer to the HW structure ++ * ++ * Enables packet filtering on transmit packets if manageability is enabled ++ * and host interface is enabled. ++ * Currently no func pointer exists and all implementations are handled in the ++ * generic version of this function. ++ **/ ++bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) ++{ ++ return e1000_enable_tx_pkt_filtering_generic(hw); ++} ++ ++/** ++ * e1000_mng_host_if_write - Writes to the manageability host interface ++ * @hw: pointer to the HW structure ++ * @buffer: pointer to the host interface buffer ++ * @length: size of the buffer ++ * @offset: location in the buffer to write to ++ * @sum: sum of the data (not checksum) ++ * ++ * This function writes the buffer content at the offset given on the host if. ++ * It also does alignment considerations to do the writes in most efficient ++ * way. Also fills up the sum of the buffer in *buffer parameter. ++ **/ ++s32 e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer, u16 length, ++ u16 offset, u8 *sum) ++{ ++ if (hw->mac.ops.mng_host_if_write) ++ return hw->mac.ops.mng_host_if_write(hw, buffer, length, ++ offset, sum); ++ ++ return E1000_NOT_IMPLEMENTED; ++} ++ ++/** ++ * e1000_mng_write_cmd_header - Writes manageability command header ++ * @hw: pointer to the HW structure ++ * @hdr: pointer to the host interface command header ++ * ++ * Writes the command header after does the checksum calculation. ++ **/ ++s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header *hdr) ++{ ++ if (hw->mac.ops.mng_write_cmd_header) ++ return hw->mac.ops.mng_write_cmd_header(hw, hdr); ++ ++ return E1000_NOT_IMPLEMENTED; ++} ++ ++/** ++ * e1000_mng_enable_host_if - Checks host interface is enabled ++ * @hw: pointer to the HW structure ++ * ++ * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND ++ * ++ * This function checks whether the HOST IF is enabled for command operation ++ * and also checks whether the previous command is completed. It busy waits ++ * in case of previous command is not completed. ++ **/ ++s32 e1000_mng_enable_host_if(struct e1000_hw * hw) ++{ ++ if (hw->mac.ops.mng_enable_host_if) ++ return hw->mac.ops.mng_enable_host_if(hw); ++ ++ return E1000_NOT_IMPLEMENTED; ++} ++ ++/** ++ * e1000_wait_autoneg - Waits for autonegotiation completion ++ * @hw: pointer to the HW structure ++ * ++ * Waits for autoneg to complete. Currently no func pointer exists and all ++ * implementations are handled in the generic version of this function. ++ **/ ++s32 e1000_wait_autoneg(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.wait_autoneg) ++ return hw->mac.ops.wait_autoneg(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_check_reset_block - Verifies PHY can be reset ++ * @hw: pointer to the HW structure ++ * ++ * Checks if the PHY is in a state that can be reset or if manageability ++ * has it tied up. This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_check_reset_block(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.check_reset_block) ++ return hw->phy.ops.check_reset_block(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_read_phy_reg - Reads PHY register ++ * @hw: pointer to the HW structure ++ * @offset: the register to read ++ * @data: the buffer to store the 16-bit read. ++ * ++ * Reads the PHY register and returns the value in data. ++ * This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ if (hw->phy.ops.read_reg) ++ return hw->phy.ops.read_reg(hw, offset, data); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_write_phy_reg - Writes PHY register ++ * @hw: pointer to the HW structure ++ * @offset: the register to write ++ * @data: the value to write. ++ * ++ * Writes the PHY register at offset with the value in data. ++ * This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ if (hw->phy.ops.write_reg) ++ return hw->phy.ops.write_reg(hw, offset, data); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_release_phy - Generic release PHY ++ * @hw: pointer to the HW structure ++ * ++ * Return if silicon family does not require a semaphore when accessing the ++ * PHY. ++ **/ ++void e1000_release_phy(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.release) ++ hw->phy.ops.release(hw); ++} ++ ++/** ++ * e1000_acquire_phy - Generic acquire PHY ++ * @hw: pointer to the HW structure ++ * ++ * Return success if silicon family does not require a semaphore when ++ * accessing the PHY. ++ **/ ++s32 e1000_acquire_phy(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.acquire) ++ return hw->phy.ops.acquire(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_read_kmrn_reg - Reads register using Kumeran interface ++ * @hw: pointer to the HW structure ++ * @offset: the register to read ++ * @data: the location to store the 16-bit value read. ++ * ++ * Reads a register out of the Kumeran interface. Currently no func pointer ++ * exists and all implementations are handled in the generic version of ++ * this function. ++ **/ ++s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ return e1000_read_kmrn_reg_generic(hw, offset, data); ++} ++ ++/** ++ * e1000_write_kmrn_reg - Writes register using Kumeran interface ++ * @hw: pointer to the HW structure ++ * @offset: the register to write ++ * @data: the value to write. ++ * ++ * Writes a register to the Kumeran interface. Currently no func pointer ++ * exists and all implementations are handled in the generic version of ++ * this function. ++ **/ ++s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ return e1000_write_kmrn_reg_generic(hw, offset, data); ++} ++ ++/** ++ * e1000_get_cable_length - Retrieves cable length estimation ++ * @hw: pointer to the HW structure ++ * ++ * This function estimates the cable length and stores them in ++ * hw->phy.min_length and hw->phy.max_length. This is a function pointer ++ * entry point called by drivers. ++ **/ ++s32 e1000_get_cable_length(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.get_cable_length) ++ return hw->phy.ops.get_cable_length(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_get_phy_info - Retrieves PHY information from registers ++ * @hw: pointer to the HW structure ++ * ++ * This function gets some information from various PHY registers and ++ * populates hw->phy values with it. This is a function pointer entry ++ * point called by drivers. ++ **/ ++s32 e1000_get_phy_info(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.get_info) ++ return hw->phy.ops.get_info(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_phy_hw_reset - Hard PHY reset ++ * @hw: pointer to the HW structure ++ * ++ * Performs a hard PHY reset. This is a function pointer entry point called ++ * by drivers. ++ **/ ++s32 e1000_phy_hw_reset(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.reset) ++ return hw->phy.ops.reset(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_phy_commit - Soft PHY reset ++ * @hw: pointer to the HW structure ++ * ++ * Performs a soft PHY reset on those that apply. This is a function pointer ++ * entry point called by drivers. ++ **/ ++s32 e1000_phy_commit(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.commit) ++ return hw->phy.ops.commit(hw); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_set_d0_lplu_state - Sets low power link up state for D0 ++ * @hw: pointer to the HW structure ++ * @active: boolean used to enable/disable lplu ++ * ++ * Success returns 0, Failure returns 1 ++ * ++ * The low power link up (lplu) state is set to the power management level D0 ++ * and SmartSpeed is disabled when active is true, else clear lplu for D0 ++ * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU ++ * is used during Dx states where the power conservation is most important. ++ * During driver activity, SmartSpeed should be enabled so performance is ++ * maintained. This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) ++{ ++ if (hw->phy.ops.set_d0_lplu_state) ++ return hw->phy.ops.set_d0_lplu_state(hw, active); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_set_d3_lplu_state - Sets low power link up state for D3 ++ * @hw: pointer to the HW structure ++ * @active: boolean used to enable/disable lplu ++ * ++ * Success returns 0, Failure returns 1 ++ * ++ * The low power link up (lplu) state is set to the power management level D3 ++ * and SmartSpeed is disabled when active is true, else clear lplu for D3 ++ * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU ++ * is used during Dx states where the power conservation is most important. ++ * During driver activity, SmartSpeed should be enabled so performance is ++ * maintained. This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) ++{ ++ if (hw->phy.ops.set_d3_lplu_state) ++ return hw->phy.ops.set_d3_lplu_state(hw, active); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_read_mac_addr - Reads MAC address ++ * @hw: pointer to the HW structure ++ * ++ * Reads the MAC address out of the adapter and stores it in the HW structure. ++ * Currently no func pointer exists and all implementations are handled in the ++ * generic version of this function. ++ **/ ++s32 e1000_read_mac_addr(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.read_mac_addr) ++ return hw->mac.ops.read_mac_addr(hw); ++ ++ return e1000_read_mac_addr_generic(hw); ++} ++ ++/** ++ * e1000_read_pba_num - Read device part number ++ * @hw: pointer to the HW structure ++ * @pba_num: pointer to device part number ++ * ++ * Reads the product board assembly (PBA) number from the EEPROM and stores ++ * the value in pba_num. ++ * Currently no func pointer exists and all implementations are handled in the ++ * generic version of this function. ++ **/ ++s32 e1000_read_pba_num(struct e1000_hw *hw, u32 *pba_num) ++{ ++ return e1000_read_pba_num_generic(hw, pba_num); ++} ++ ++/** ++ * e1000_validate_nvm_checksum - Verifies NVM (EEPROM) checksum ++ * @hw: pointer to the HW structure ++ * ++ * Validates the NVM checksum is correct. This is a function pointer entry ++ * point called by drivers. ++ **/ ++s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) ++{ ++ if (hw->nvm.ops.validate) ++ return hw->nvm.ops.validate(hw); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_update_nvm_checksum - Updates NVM (EEPROM) checksum ++ * @hw: pointer to the HW structure ++ * ++ * Updates the NVM checksum. Currently no func pointer exists and all ++ * implementations are handled in the generic version of this function. ++ **/ ++s32 e1000_update_nvm_checksum(struct e1000_hw *hw) ++{ ++ if (hw->nvm.ops.update) ++ return hw->nvm.ops.update(hw); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_reload_nvm - Reloads EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the ++ * extended control register. ++ **/ ++void e1000_reload_nvm(struct e1000_hw *hw) ++{ ++ if (hw->nvm.ops.reload) ++ hw->nvm.ops.reload(hw); ++} ++ ++/** ++ * e1000_read_nvm - Reads NVM (EEPROM) ++ * @hw: pointer to the HW structure ++ * @offset: the word offset to read ++ * @words: number of 16-bit words to read ++ * @data: pointer to the properly sized buffer for the data. ++ * ++ * Reads 16-bit chunks of data from the NVM (EEPROM). This is a function ++ * pointer entry point called by drivers. ++ **/ ++s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ if (hw->nvm.ops.read) ++ return hw->nvm.ops.read(hw, offset, words, data); ++ ++ return -E1000_ERR_CONFIG; ++} ++ ++/** ++ * e1000_write_nvm - Writes to NVM (EEPROM) ++ * @hw: pointer to the HW structure ++ * @offset: the word offset to read ++ * @words: number of 16-bit words to write ++ * @data: pointer to the properly sized buffer for the data. ++ * ++ * Writes 16-bit chunks of data to the NVM (EEPROM). This is a function ++ * pointer entry point called by drivers. ++ **/ ++s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ if (hw->nvm.ops.write) ++ return hw->nvm.ops.write(hw, offset, words, data); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_write_8bit_ctrl_reg - Writes 8bit Control register ++ * @hw: pointer to the HW structure ++ * @reg: 32bit register offset ++ * @offset: the register to write ++ * @data: the value to write. ++ * ++ * Writes the PHY register at offset with the value in data. ++ * This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset, ++ u8 data) ++{ ++ return e1000_write_8bit_ctrl_reg_generic(hw, reg, offset, data); ++} ++ ++/** ++ * e1000_power_up_phy - Restores link in case of PHY power down ++ * @hw: pointer to the HW structure ++ * ++ * The phy may be powered down to save power, to turn off link when the ++ * driver is unloaded, or wake on lan is not enabled (among others). ++ **/ ++void e1000_power_up_phy(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.power_up) ++ hw->phy.ops.power_up(hw); ++ ++ e1000_setup_link(hw); ++} ++ ++/** ++ * e1000_power_down_phy - Power down PHY ++ * @hw: pointer to the HW structure ++ * ++ * The phy may be powered down to save power, to turn off link when the ++ * driver is unloaded, or wake on lan is not enabled (among others). ++ **/ ++void e1000_power_down_phy(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.power_down) ++ hw->phy.ops.power_down(hw); ++} ++ ++/** ++ * e1000_shutdown_fiber_serdes_link - Remove link during power down ++ * @hw: pointer to the HW structure ++ * ++ * Shutdown the optics and PCS on driver unload. ++ **/ ++void e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw) ++{ ++ if (hw->mac.ops.shutdown_serdes) ++ hw->mac.ops.shutdown_serdes(hw); ++} ++ +diff -r 4f0f8bc35440 drivers/net/igb/e1000_api.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/igb/e1000_api.h Wed Aug 05 11:03:37 2009 +0100 +@@ -0,0 +1,146 @@ ++/******************************************************************************* ++ ++ Intel(R) Gigabit Ethernet Linux driver ++ Copyright(c) 2007-2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_API_H_ ++#define _E1000_API_H_ ++ ++#include "e1000_hw.h" ++ ++extern void e1000_init_function_pointers_82575(struct e1000_hw *hw); ++extern void e1000_rx_fifo_flush_82575(struct e1000_hw *hw); ++extern void e1000_init_function_pointers_vf(struct e1000_hw *hw); ++extern void e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw); ++ ++s32 e1000_set_mac_type(struct e1000_hw *hw); ++s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device); ++s32 e1000_init_mac_params(struct e1000_hw *hw); ++s32 e1000_init_nvm_params(struct e1000_hw *hw); ++s32 e1000_init_phy_params(struct e1000_hw *hw); ++s32 e1000_get_bus_info(struct e1000_hw *hw); ++void e1000_clear_vfta(struct e1000_hw *hw); ++void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value); ++s32 e1000_force_mac_fc(struct e1000_hw *hw); ++s32 e1000_check_for_link(struct e1000_hw *hw); ++s32 e1000_reset_hw(struct e1000_hw *hw); ++s32 e1000_init_hw(struct e1000_hw *hw); ++s32 e1000_setup_link(struct e1000_hw *hw); ++s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex); ++s32 e1000_disable_pcie_master(struct e1000_hw *hw); ++void e1000_config_collision_dist(struct e1000_hw *hw); ++void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); ++void e1000_mta_set(struct e1000_hw *hw, u32 hash_value); ++u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr); ++void e1000_update_mc_addr_list(struct e1000_hw *hw, ++ u8 *mc_addr_list, u32 mc_addr_count); ++s32 e1000_setup_led(struct e1000_hw *hw); ++s32 e1000_cleanup_led(struct e1000_hw *hw); ++s32 e1000_check_reset_block(struct e1000_hw *hw); ++s32 e1000_blink_led(struct e1000_hw *hw); ++s32 e1000_led_on(struct e1000_hw *hw); ++s32 e1000_led_off(struct e1000_hw *hw); ++s32 e1000_id_led_init(struct e1000_hw *hw); ++void e1000_reset_adaptive(struct e1000_hw *hw); ++void e1000_update_adaptive(struct e1000_hw *hw); ++s32 e1000_get_cable_length(struct e1000_hw *hw); ++s32 e1000_validate_mdi_setting(struct e1000_hw *hw); ++s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, ++ u32 offset, u8 data); ++s32 e1000_get_phy_info(struct e1000_hw *hw); ++void e1000_release_phy(struct e1000_hw *hw); ++s32 e1000_acquire_phy(struct e1000_hw *hw); ++s32 e1000_phy_hw_reset(struct e1000_hw *hw); ++s32 e1000_phy_commit(struct e1000_hw *hw); ++void e1000_power_up_phy(struct e1000_hw *hw); ++void e1000_power_down_phy(struct e1000_hw *hw); ++s32 e1000_read_mac_addr(struct e1000_hw *hw); ++s32 e1000_read_pba_num(struct e1000_hw *hw, u32 *part_num); ++void e1000_reload_nvm(struct e1000_hw *hw); ++s32 e1000_update_nvm_checksum(struct e1000_hw *hw); ++s32 e1000_validate_nvm_checksum(struct e1000_hw *hw); ++s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); ++s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data); ++s32 e1000_wait_autoneg(struct e1000_hw *hw); ++s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); ++s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); ++bool e1000_check_mng_mode(struct e1000_hw *hw); ++bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); ++s32 e1000_mng_enable_host_if(struct e1000_hw *hw); ++s32 e1000_mng_host_if_write(struct e1000_hw *hw, ++ u8 *buffer, u16 length, u16 offset, u8 *sum); ++s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header *hdr); ++s32 e1000_mng_write_dhcp_info(struct e1000_hw * hw, ++ u8 *buffer, u16 length); ++ ++/* ++ * TBI_ACCEPT macro definition: ++ * ++ * This macro requires: ++ * adapter = a pointer to struct e1000_hw ++ * status = the 8 bit status field of the Rx descriptor with EOP set ++ * error = the 8 bit error field of the Rx descriptor with EOP set ++ * length = the sum of all the length fields of the Rx descriptors that ++ * make up the current frame ++ * last_byte = the last byte of the frame DMAed by the hardware ++ * max_frame_length = the maximum frame length we want to accept. ++ * min_frame_length = the minimum frame length we want to accept. ++ * ++ * This macro is a conditional that should be used in the interrupt ++ * handler's Rx processing routine when RxErrors have been detected. ++ * ++ * Typical use: ++ * ... ++ * if (TBI_ACCEPT) { ++ * accept_frame = true; ++ * e1000_tbi_adjust_stats(adapter, MacAddress); ++ * frame_length--; ++ * } else { ++ * accept_frame = false; ++ * } ++ * ... ++ */ ++ ++/* The carrier extension symbol, as received by the NIC. */ ++#define CARRIER_EXTENSION 0x0F ++ ++#define TBI_ACCEPT(a, status, errors, length, last_byte, min_frame_size, max_frame_size) \ ++ (e1000_tbi_sbp_enabled_82543(a) && \ ++ (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ ++ ((last_byte) == CARRIER_EXTENSION) && \ ++ (((status) & E1000_RXD_STAT_VP) ? \ ++ (((length) > (min_frame_size - VLAN_TAG_SIZE)) && \ ++ ((length) <= (max_frame_size + 1))) : \ ++ (((length) > min_frame_size) && \ ++ ((length) <= (max_frame_size + VLAN_TAG_SIZE + 1))))) ++ ++#endif +diff -r 4f0f8bc35440 drivers/net/igb/e1000_defines.h +--- a/drivers/net/igb/e1000_defines.h Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/e1000_defines.h Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 - 2008 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -34,7 +34,14 @@ + + /* Definitions for power management and wakeup registers */ + /* Wake Up Control */ ++#define E1000_WUC_APME 0x00000001 /* APM Enable */ + #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ ++#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ ++#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ ++#define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */ ++#define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */ ++#define E1000_WUC_SPM 0x80000000 /* Enable SPM */ ++#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ + + /* Wake Up Filter Control */ + #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ +@@ -45,56 +52,120 @@ + #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ + #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ + #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ ++#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ + #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ + #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ + #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ + #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ +-#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ ++#define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ ++#define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ ++#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ ++#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ ++#define E1000_WUFC_FLX_FILTERS 0x000F0000 /*Mask for the 4 flexible filters */ ++/* ++ * For 82576 to utilize Extended filter masks in addition to ++ * existing (filter) masks ++ */ ++#define E1000_WUFC_EXT_FLX_FILTERS 0x00300000 /* Ext. FLX filter mask */ + + /* Wake Up Status */ ++#define E1000_WUS_LNKC E1000_WUFC_LNKC ++#define E1000_WUS_MAG E1000_WUFC_MAG ++#define E1000_WUS_EX E1000_WUFC_EX ++#define E1000_WUS_MC E1000_WUFC_MC ++#define E1000_WUS_BC E1000_WUFC_BC ++#define E1000_WUS_ARP E1000_WUFC_ARP ++#define E1000_WUS_IPV4 E1000_WUFC_IPV4 ++#define E1000_WUS_IPV6 E1000_WUFC_IPV6 ++#define E1000_WUS_FLX0 E1000_WUFC_FLX0 ++#define E1000_WUS_FLX1 E1000_WUFC_FLX1 ++#define E1000_WUS_FLX2 E1000_WUFC_FLX2 ++#define E1000_WUS_FLX3 E1000_WUFC_FLX3 ++#define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS + + /* Wake Up Packet Length */ ++#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ + + /* Four Flexible Filters are supported */ + #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 ++/* Two Extended Flexible Filters are supported (82576) */ ++#define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 ++#define E1000_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ ++#define E1000_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ + + /* Each Flexible Filter is at most 128 (0x80) bytes in length */ + #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 + ++#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX ++#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX ++#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX + + /* Extended Device Control */ ++#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ + #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ +-#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ +-#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ +-#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ ++#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN ++#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ ++#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ ++/* Reserved (bits 4,5) in >= 82575 */ ++#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */ ++#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */ ++#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA ++#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */ ++#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */ ++/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ + #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ ++#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ ++#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ ++#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ ++#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ + #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ ++#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ ++/* Physical Func Reset Done Indication */ ++#define E1000_CTRL_EXT_PFRSTD 0x00004000 ++#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ ++#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ ++#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ + #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 ++#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 ++#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 ++#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 + #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 ++#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 + #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 + #define E1000_CTRL_EXT_EIAME 0x01000000 + #define E1000_CTRL_EXT_IRCA 0x00000001 +-/* Interrupt delay cancellation */ +-/* Driver loaded bit for FW */ +-#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 +-/* Interrupt acknowledge Auto-mask */ +-/* Clear Interrupt timers after IMS clear */ +-/* packet buffer parity error detection enabled */ +-/* descriptor FIFO parity error detection enable */ ++#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 ++#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 ++#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 ++#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 ++#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 ++#define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */ ++#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ ++/* IAME enable bit (27) was removed in >= 82575 */ ++#define E1000_CTRL_EXT_IAME 0x08000000 /* Int acknowledge Auto-mask */ ++#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error ++ * detection enabled */ ++#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity ++ * error detection enable */ ++#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 + #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ + #define E1000_I2CCMD_REG_ADDR_SHIFT 16 ++#define E1000_I2CCMD_REG_ADDR 0x00FF0000 + #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 ++#define E1000_I2CCMD_PHY_ADDR 0x07000000 + #define E1000_I2CCMD_OPCODE_READ 0x08000000 + #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 ++#define E1000_I2CCMD_RESET 0x10000000 + #define E1000_I2CCMD_READY 0x20000000 ++#define E1000_I2CCMD_INTERRUPT_ENA 0x40000000 + #define E1000_I2CCMD_ERROR 0x80000000 + #define E1000_MAX_SGMII_PHY_REG_ADDR 255 + #define E1000_I2CCMD_PHY_TIMEOUT 200 +-#define E1000_IVAR_VALID 0x80 +-#define E1000_GPIE_NSICR 0x00000001 +-#define E1000_GPIE_MSIX_MODE 0x00000010 +-#define E1000_GPIE_EIAME 0x40000000 +-#define E1000_GPIE_PBA 0x80000000 ++#define E1000_IVAR_VALID 0x80 ++#define E1000_GPIE_NSICR 0x00000001 ++#define E1000_GPIE_MSIX_MODE 0x00000010 ++#define E1000_GPIE_EIAME 0x40000000 ++#define E1000_GPIE_PBA 0x80000000 + + /* Receive Descriptor bit definitions */ + #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ +@@ -103,13 +174,25 @@ + #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ + #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ + #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ ++#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ ++#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ ++#define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ ++#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ ++#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ + #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ ++#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ + #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ + #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ + #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ + #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ ++#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ ++#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ + #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ + #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ ++#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ ++#define E1000_RXD_SPC_PRI_SHIFT 13 ++#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ ++#define E1000_RXD_SPC_CFI_SHIFT 12 + + #define E1000_RXDEXT_STATERR_CE 0x01000000 + #define E1000_RXDEXT_STATERR_SE 0x02000000 +@@ -135,38 +218,78 @@ + E1000_RXDEXT_STATERR_CXE | \ + E1000_RXDEXT_STATERR_RXE) + ++#define E1000_MRQC_ENABLE_MASK 0x00000007 ++#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 ++#define E1000_MRQC_ENABLE_RSS_INT 0x00000004 ++#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 + #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 + #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 + #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 ++#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 + #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 + #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 + ++#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 ++#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF + + /* Management Control */ + #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ + #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ ++#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ ++#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ ++#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ ++#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ ++#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ ++#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ + #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ + /* Enable Neighbor Discovery Filtering */ ++#define E1000_MANC_NEIGHBOR_EN 0x00004000 ++#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ ++#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ + #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ ++#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ ++#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ + #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ + /* Enable MAC address filtering */ + #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 + /* Enable MNG packets to host memory */ + #define E1000_MANC_EN_MNG2HOST 0x00200000 + /* Enable IP address filtering */ ++#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 ++#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ ++#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ ++#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ ++#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ ++#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ ++#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ ++#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ ++#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ + ++#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ ++#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ + + /* Receive Control */ ++#define E1000_RCTL_RST 0x00000001 /* Software reset */ + #define E1000_RCTL_EN 0x00000002 /* enable */ + #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ +-#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ +-#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ ++#define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ ++#define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ + #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ + #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ + #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ ++#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ + #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ +-#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ ++#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ ++#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ ++#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min thresh size */ ++#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min thresh size */ ++#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min thresh size */ + #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ ++#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ ++#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ ++#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ ++#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ ++#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ + #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ + /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ + #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ +@@ -179,8 +302,13 @@ + #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ + #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ + #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ ++#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ ++#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ ++#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ + #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ + #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ ++#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ ++#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ + + /* + * Use byte values for the following shift parameters +@@ -210,80 +338,142 @@ + #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ + + /* SWFW_SYNC Definitions */ +-#define E1000_SWFW_EEP_SM 0x1 +-#define E1000_SWFW_PHY0_SM 0x2 +-#define E1000_SWFW_PHY1_SM 0x4 ++#define E1000_SWFW_EEP_SM 0x01 ++#define E1000_SWFW_PHY0_SM 0x02 ++#define E1000_SWFW_PHY1_SM 0x04 ++#define E1000_SWFW_CSR_SM 0x08 + + /* FACTPS Definitions */ ++#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */ + /* Device Control */ + #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ +-#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ ++#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ ++#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ ++#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ + #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ ++#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ ++#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ + #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ + #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ + #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ + #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ ++#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ + #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ + #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ ++#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ + #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ + #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +-/* Defined polarity of Dock/Undock indication in SDP[0] */ +-/* Reset both PHY ports, through PHYRST_N pin */ +-/* enable link status from external LINK_0 and LINK_1 pins */ ++#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ ++#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock ++ * indication in SDP[0] */ ++#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through ++ * PHYRST_N pin */ ++#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external ++ * LINK_0 and LINK_1 pins */ + #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ + #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ + #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ ++#define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ + #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ + #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ ++#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ + #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ + #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ + #define E1000_CTRL_RST 0x04000000 /* Global reset */ + #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ + #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ ++#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ + #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ + #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ +-/* Initiate an interrupt to manageability engine */ ++#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */ + #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ + +-/* Bit definitions for the Management Data IO (MDIO) and Management Data ++/* ++ * Bit definitions for the Management Data IO (MDIO) and Management Data + * Clock (MDC) pins in the Device Control Register. + */ ++#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 ++#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 ++#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 ++#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 ++#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 ++#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 ++#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR ++#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA + + #define E1000_CONNSW_ENRGSRC 0x4 + #define E1000_PCS_CFG_PCS_EN 8 + #define E1000_PCS_LCTL_FLV_LINK_UP 1 ++#define E1000_PCS_LCTL_FSV_10 0 + #define E1000_PCS_LCTL_FSV_100 2 + #define E1000_PCS_LCTL_FSV_1000 4 + #define E1000_PCS_LCTL_FDV_FULL 8 + #define E1000_PCS_LCTL_FSD 0x10 + #define E1000_PCS_LCTL_FORCE_LINK 0x20 ++#define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40 + #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 + #define E1000_PCS_LCTL_AN_ENABLE 0x10000 + #define E1000_PCS_LCTL_AN_RESTART 0x20000 + #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 ++#define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 ++#define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 ++#define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 ++#define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000 ++#define E1000_PCS_LCTL_CRS_ON_NI 0x4000000 + #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 + + #define E1000_PCS_LSTS_LINK_OK 1 ++#define E1000_PCS_LSTS_SPEED_10 0 + #define E1000_PCS_LSTS_SPEED_100 2 + #define E1000_PCS_LSTS_SPEED_1000 4 + #define E1000_PCS_LSTS_DUPLEX_FULL 8 + #define E1000_PCS_LSTS_SYNK_OK 0x10 ++#define E1000_PCS_LSTS_AN_COMPLETE 0x10000 ++#define E1000_PCS_LSTS_AN_PAGE_RX 0x20000 ++#define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000 ++#define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 ++#define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000 + + /* Device Status */ + #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ + #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ + #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ + #define E1000_STATUS_FUNC_SHIFT 2 ++#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ + #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ + #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ ++#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ ++#define E1000_STATUS_SPEED_MASK 0x000000C0 ++#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ + #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ + #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ +-/* Change in Dock/Undock state. Clear on write '0'. */ +-/* Status of Master requests. */ +-#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 +-/* BMC external code execution disabled */ ++#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ ++#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ ++#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ ++#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. ++ * Clear on write '0'. */ ++#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ ++#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ ++#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ ++#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ ++#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ ++#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ ++#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ ++#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ ++#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ ++#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ ++#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution ++ * disabled */ ++#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ ++#define E1000_STATUS_FUSE_8 0x04000000 ++#define E1000_STATUS_FUSE_9 0x08000000 ++#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ ++#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ + +-/* Constants used to intrepret the masked PCI-X bus speed. */ ++/* Constants used to interpret the masked PCI-X bus speed. */ ++#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ ++#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ ++#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/ + + #define SPEED_10 10 + #define SPEED_100 100 +@@ -291,6 +481,7 @@ + #define HALF_DUPLEX 1 + #define FULL_DUPLEX 2 + ++#define PHY_FORCE_TIME 20 + + #define ADVERTISE_10_HALF 0x0001 + #define ADVERTISE_10_FULL 0x0002 +@@ -300,56 +491,127 @@ + #define ADVERTISE_1000_FULL 0x0020 + + /* 1000/H is not supported, nor spec-compliant. */ +-#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ +- ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ +- ADVERTISE_1000_FULL) +-#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ +- ADVERTISE_100_HALF | ADVERTISE_100_FULL) ++#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ++ ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ ++ ADVERTISE_1000_FULL) ++#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ++ ADVERTISE_100_HALF | ADVERTISE_100_FULL) + #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) +-#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) +-#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ +- ADVERTISE_1000_FULL) +-#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) ++#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) ++#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ ++ ADVERTISE_1000_FULL) ++#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) + + #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX + + /* LED Control */ + #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F + #define E1000_LEDCTL_LED0_MODE_SHIFT 0 ++#define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020 + #define E1000_LEDCTL_LED0_IVRT 0x00000040 + #define E1000_LEDCTL_LED0_BLINK 0x00000080 ++#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 ++#define E1000_LEDCTL_LED1_MODE_SHIFT 8 ++#define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000 ++#define E1000_LEDCTL_LED1_IVRT 0x00004000 ++#define E1000_LEDCTL_LED1_BLINK 0x00008000 ++#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 ++#define E1000_LEDCTL_LED2_MODE_SHIFT 16 ++#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 ++#define E1000_LEDCTL_LED2_IVRT 0x00400000 ++#define E1000_LEDCTL_LED2_BLINK 0x00800000 ++#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 ++#define E1000_LEDCTL_LED3_MODE_SHIFT 24 ++#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 ++#define E1000_LEDCTL_LED3_IVRT 0x40000000 ++#define E1000_LEDCTL_LED3_BLINK 0x80000000 + ++#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 ++#define E1000_LEDCTL_MODE_LINK_100_1000 0x1 ++#define E1000_LEDCTL_MODE_LINK_UP 0x2 ++#define E1000_LEDCTL_MODE_ACTIVITY 0x3 ++#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 ++#define E1000_LEDCTL_MODE_LINK_10 0x5 ++#define E1000_LEDCTL_MODE_LINK_100 0x6 ++#define E1000_LEDCTL_MODE_LINK_1000 0x7 ++#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 ++#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 ++#define E1000_LEDCTL_MODE_COLLISION 0xA ++#define E1000_LEDCTL_MODE_BUS_SPEED 0xB ++#define E1000_LEDCTL_MODE_BUS_SIZE 0xC ++#define E1000_LEDCTL_MODE_PAUSED 0xD + #define E1000_LEDCTL_MODE_LED_ON 0xE + #define E1000_LEDCTL_MODE_LED_OFF 0xF + + /* Transmit Descriptor bit definitions */ ++#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ ++#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ ++#define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */ + #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ + #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ + #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ + #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ ++#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ + #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ ++#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ + #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ ++#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ ++#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ ++#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ ++#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ ++#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ ++#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ ++#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ ++#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ ++#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ ++#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ + /* Extended desc bits for Linksec and timesync */ + + /* Transmit Control */ ++#define E1000_TCTL_RST 0x00000001 /* software reset */ + #define E1000_TCTL_EN 0x00000002 /* enable tx */ ++#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ + #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ + #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ + #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ ++#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ ++#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ + #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ ++#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ ++#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ + + /* Transmit Arbitration Count */ ++#define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ + + /* SerDes Control */ + #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 + + /* Receive Checksum Control */ ++#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ ++#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ + #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ ++#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ ++#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ + #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ + #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ + + /* Header split receive */ +-#define E1000_RFCTL_LEF 0x00040000 ++#define E1000_RFCTL_ISCSI_DIS 0x00000001 ++#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E ++#define E1000_RFCTL_ISCSI_DWC_SHIFT 1 ++#define E1000_RFCTL_NFSW_DIS 0x00000040 ++#define E1000_RFCTL_NFSR_DIS 0x00000080 ++#define E1000_RFCTL_NFS_VER_MASK 0x00000300 ++#define E1000_RFCTL_NFS_VER_SHIFT 8 ++#define E1000_RFCTL_IPV6_DIS 0x00000400 ++#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 ++#define E1000_RFCTL_ACK_DIS 0x00001000 ++#define E1000_RFCTL_ACKD_DIS 0x00002000 ++#define E1000_RFCTL_IPFRSP_DIS 0x00004000 ++#define E1000_RFCTL_EXTEN 0x00008000 ++#define E1000_RFCTL_IPV6_EX_DIS 0x00010000 ++#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 ++#define E1000_RFCTL_LEF 0x00040000 + + /* Collision related configuration parameters */ + #define E1000_COLLISION_THRESHOLD 15 +@@ -357,19 +619,67 @@ + #define E1000_COLLISION_DISTANCE 63 + #define E1000_COLD_SHIFT 12 + ++/* Default values for the transmit IPG register */ ++#define DEFAULT_82543_TIPG_IPGT_FIBER 9 ++#define DEFAULT_82543_TIPG_IPGT_COPPER 8 ++ ++#define E1000_TIPG_IPGT_MASK 0x000003FF ++#define E1000_TIPG_IPGR1_MASK 0x000FFC00 ++#define E1000_TIPG_IPGR2_MASK 0x3FF00000 ++ ++#define DEFAULT_82543_TIPG_IPGR1 8 ++#define E1000_TIPG_IPGR1_SHIFT 10 ++ ++#define DEFAULT_82543_TIPG_IPGR2 6 ++#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 ++#define E1000_TIPG_IPGR2_SHIFT 20 ++ + /* Ethertype field values */ + #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ + ++#define ETHERNET_FCS_SIZE 4 + #define MAX_JUMBO_FRAME_SIZE 0x3F00 + + /* Extended Configuration Control and Size */ ++#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 ++#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 ++#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 ++#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 ++#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 ++#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 ++#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 ++ ++#define E1000_PHY_CTRL_SPD_EN 0x00000001 ++#define E1000_PHY_CTRL_D0A_LPLU 0x00000002 ++#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 ++#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 + #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 + ++#define E1000_KABGTXD_BGSQLBIAS 0x00050000 ++ + /* PBA constants */ +-#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ ++#define E1000_PBA_6K 0x0006 /* 6KB */ ++#define E1000_PBA_8K 0x0008 /* 8KB */ ++#define E1000_PBA_10K 0x000A /* 10KB */ ++#define E1000_PBA_12K 0x000C /* 12KB */ ++#define E1000_PBA_14K 0x000E /* 14KB */ ++#define E1000_PBA_16K 0x0010 /* 16KB */ ++#define E1000_PBA_18K 0x0012 ++#define E1000_PBA_20K 0x0014 ++#define E1000_PBA_22K 0x0016 + #define E1000_PBA_24K 0x0018 ++#define E1000_PBA_26K 0x001A ++#define E1000_PBA_30K 0x001E ++#define E1000_PBA_32K 0x0020 + #define E1000_PBA_34K 0x0022 ++#define E1000_PBA_35K 0x0023 ++#define E1000_PBA_38K 0x0026 ++#define E1000_PBA_40K 0x0028 ++#define E1000_PBA_48K 0x0030 /* 48KB */ + #define E1000_PBA_64K 0x0040 /* 64KB */ ++ ++#define E1000_PBS_16K E1000_PBA_16K ++#define E1000_PBS_24K E1000_PBA_24K + + #define IFS_MAX 80 + #define IFS_MIN 40 +@@ -380,6 +690,10 @@ + /* SW Semaphore Register */ + #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ + #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ ++#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ ++#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ ++ ++#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ + + /* Interrupt Cause Read */ + #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ +@@ -389,6 +703,7 @@ + #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ + #define E1000_ICR_RXO 0x00000040 /* rx overrun */ + #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ ++#define E1000_ICR_VMMB 0x00000100 /* VM MB event */ + #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ + #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ + #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ +@@ -400,24 +715,22 @@ + #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ + #define E1000_ICR_MNG 0x00040000 /* Manageability event */ + #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ +-/* If this bit asserted, the driver should claim the interrupt */ +-#define E1000_ICR_INT_ASSERTED 0x80000000 +-/* queue 0 Rx descriptor FIFO parity error */ +-#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 +-/* queue 0 Tx descriptor FIFO parity error */ +-#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 +-/* host arb read buffer parity error */ +-#define E1000_ICR_HOST_ARB_PAR 0x00400000 ++#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver ++ * should claim the interrupt */ ++#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */ ++#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */ ++#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */ + #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ +-/* queue 1 Rx descriptor FIFO parity error */ +-#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 +-/* queue 1 Tx descriptor FIFO parity error */ +-#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 +-/* FW changed the status of DISSW bit in the FWSM */ +-#define E1000_ICR_DSW 0x00000020 +-/* LAN connected device generates an interrupt */ +-#define E1000_ICR_PHYINT 0x00001000 +-#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ ++#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */ ++#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */ ++#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ ++#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW ++ * bit in the FWSM */ ++#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates ++ * an interrupt */ ++#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ ++#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ ++ + + /* Extended Interrupt Cause Read */ + #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ +@@ -431,6 +744,20 @@ + #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ + #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ + /* TCP Timer */ ++#define E1000_TCPTIMER_KS 0x00000100 /* KickStart */ ++#define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ ++#define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ ++#define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */ ++ ++/* ++ * This defines the bits that are set in the Interrupt Mask ++ * Set/Read Register. Each bit is documented below: ++ * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) ++ * o RXSEQ = Receive Sequence Error ++ */ ++#define POLL_IMS_ENABLE_MASK ( \ ++ E1000_IMS_RXDMT0 | \ ++ E1000_IMS_RXSEQ) + + /* + * This defines the bits that are set in the Interrupt Mask +@@ -449,24 +776,114 @@ + E1000_IMS_LSC) + + /* Interrupt Mask Set */ +-#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ ++#define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */ ++#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ + #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ ++#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ + #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ + #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ ++#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ + #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ ++#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ ++#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ ++#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ ++#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ ++#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ ++#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ ++#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW ++#define E1000_IMS_SRPD E1000_ICR_SRPD ++#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ ++#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ ++#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ ++#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO ++ * parity error */ ++#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO ++ * parity error */ ++#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer ++ * parity error */ ++#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity ++ * error */ ++#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO ++ * parity error */ ++#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO ++ * parity error */ ++#define E1000_IMS_DSW E1000_ICR_DSW ++#define E1000_IMS_PHYINT E1000_ICR_PHYINT ++#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ ++#define E1000_IMS_EPRST E1000_ICR_EPRST + + /* Extended Interrupt Mask Set */ ++#define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ ++#define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ ++#define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ ++#define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ ++#define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ ++#define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ ++#define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ ++#define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ + #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ + #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ + + /* Interrupt Cause Set */ ++#define E1000_ICS_TXDW E1000_ICR_TXDW /* Tx desc written back */ ++#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ + #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ ++#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ + #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ ++#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ ++#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ ++#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ ++#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ ++#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ ++#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ ++#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ ++#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ ++#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW ++#define E1000_ICS_SRPD E1000_ICR_SRPD ++#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ ++#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ ++#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ ++#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO ++ * parity error */ ++#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO ++ * parity error */ ++#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer ++ * parity error */ ++#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity ++ * error */ ++#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO ++ * parity error */ ++#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO ++ * parity error */ ++#define E1000_ICS_DSW E1000_ICR_DSW ++#define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ ++#define E1000_ICS_PHYINT E1000_ICR_PHYINT ++#define E1000_ICS_EPRST E1000_ICR_EPRST + + /* Extended Interrupt Cause Set */ ++#define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ ++#define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ ++#define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ ++#define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ ++#define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ ++#define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ ++#define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ ++#define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ ++#define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ ++#define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ ++ ++#define E1000_EITR_ITR_INT_MASK 0x0000FFFF + + /* Transmit Descriptor Control */ ++#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ ++#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ ++#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ ++#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ ++#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ ++#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ ++#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ + /* Enable the counting of descriptors still to be processed. */ ++#define E1000_TXDCTL_COUNT_DESC 0x00400000 + + /* Flow Control Constants */ + #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 +@@ -485,22 +902,31 @@ + * (RAR[15]) for our directed address used by controllers with + * manageability enabled, allowing us room for 15 multicast addresses. + */ ++#define E1000_RAR_ENTRIES 15 + #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ ++#define E1000_RAL_MAC_ADDR_LEN 4 ++#define E1000_RAH_MAC_ADDR_LEN 2 ++#define E1000_RAH_POOL_MASK 0x03FC0000 ++#define E1000_RAH_POOL_1 0x00040000 + + /* Error Codes */ ++#define E1000_SUCCESS 0 + #define E1000_ERR_NVM 1 + #define E1000_ERR_PHY 2 + #define E1000_ERR_CONFIG 3 + #define E1000_ERR_PARAM 4 + #define E1000_ERR_MAC_INIT 5 ++#define E1000_ERR_PHY_TYPE 6 + #define E1000_ERR_RESET 9 + #define E1000_ERR_MASTER_REQUESTS_PENDING 10 + #define E1000_ERR_HOST_INTERFACE_COMMAND 11 + #define E1000_BLK_PHY_RESET 12 + #define E1000_ERR_SWFW_SYNC 13 + #define E1000_NOT_IMPLEMENTED 14 ++#define E1000_ERR_MBX 15 + + /* Loop limit on how long we wait for auto-negotiation to complete */ ++#define FIBER_LINK_UP_LIMIT 50 + #define COPPER_LINK_UP_LIMIT 10 + #define PHY_AUTO_NEG_LIMIT 45 + #define PHY_FORCE_LIMIT 20 +@@ -509,16 +935,37 @@ + /* Number of milliseconds we wait for PHY configuration done after MAC reset */ + #define PHY_CFG_TIMEOUT 100 + /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ ++#define MDIO_OWNERSHIP_TIMEOUT 10 + /* Number of milliseconds for NVM auto read done after MAC reset. */ + #define AUTO_READ_DONE_TIMEOUT 10 + + /* Flow Control */ ++#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ ++#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ ++#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ + #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ + + /* Transmit Configuration Word */ ++#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ ++#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ ++#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ ++#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ ++#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ ++#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ ++#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ ++#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ ++#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ + #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ + + /* Receive Configuration Word */ ++#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ ++#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ ++#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ ++#define E1000_RXCW_CC 0x10000000 /* Receive config change */ ++#define E1000_RXCW_C 0x20000000 /* Receive config */ ++#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ ++#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ ++ + + /* PCI Express Control */ + #define E1000_GCR_RXD_NO_SNOOP 0x00000001 +@@ -527,19 +974,27 @@ + #define E1000_GCR_TXD_NO_SNOOP 0x00000008 + #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 + #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 ++#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 ++#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 ++#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 ++#define E1000_GCR_CAP_VER2 0x00040000 + + #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ +- E1000_GCR_RXDSCW_NO_SNOOP | \ +- E1000_GCR_RXDSCR_NO_SNOOP | \ +- E1000_GCR_TXD_NO_SNOOP | \ +- E1000_GCR_TXDSCW_NO_SNOOP | \ +- E1000_GCR_TXDSCR_NO_SNOOP) ++ E1000_GCR_RXDSCW_NO_SNOOP | \ ++ E1000_GCR_RXDSCR_NO_SNOOP | \ ++ E1000_GCR_TXD_NO_SNOOP | \ ++ E1000_GCR_TXDSCW_NO_SNOOP | \ ++ E1000_GCR_TXDSCR_NO_SNOOP) + + /* PHY Control Register */ ++#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ ++#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ + #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ + #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ ++#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ + #define MII_CR_POWER_DOWN 0x0800 /* Power down */ + #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ ++#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ + #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ + #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ + #define MII_CR_SPEED_1000 0x0040 +@@ -547,35 +1002,81 @@ + #define MII_CR_SPEED_10 0x0000 + + /* PHY Status Register */ ++#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ ++#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ + #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ ++#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ ++#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ + #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ ++#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ ++#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ ++#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ ++#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ ++#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ ++#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ ++#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ ++#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ ++#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ + + /* Autoneg Advertisement Register */ ++#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ + #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ + #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ + #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ + #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ ++#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ + #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ + #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ ++#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ ++#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ + + /* Link Partner Ability Register (Base Page) */ ++#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ ++#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ ++#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ ++#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ ++#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ ++#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ + #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ + #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ ++#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ ++#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ ++#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ + + /* Autoneg Expansion Register */ ++#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ ++#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ ++#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ ++#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ ++#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ + + /* 1000BASE-T Control Register */ ++#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ + #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ + #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ ++#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ ++ /* 0=DTE device */ + #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ +- /* 0=Configure PHY as Slave */ +-#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ +- /* 0=Automatic Master/Slave config */ ++ /* 0=Configure PHY as Slave */ ++#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ ++ /* 0=Automatic Master/Slave config */ ++#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ ++#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ ++#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ ++#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ ++#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ + + /* 1000BASE-T Status Register */ ++#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ ++#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ ++#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ ++#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ + #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ + #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ ++#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx is Master, 0=Slave */ ++#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ + ++#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 + + /* PHY 1000 MII Register/Bit Definitions */ + /* PHY Registers defined by IEEE */ +@@ -585,74 +1086,125 @@ + #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ + #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ + #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ ++#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ ++#define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ ++#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ + #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ + #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ ++#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ ++ ++#define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ + + /* NVM Control */ + #define E1000_EECD_SK 0x00000001 /* NVM Clock */ + #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ + #define E1000_EECD_DI 0x00000004 /* NVM Data In */ + #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ ++#define E1000_EECD_FWE_MASK 0x00000030 ++#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ ++#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ ++#define E1000_EECD_FWE_SHIFT 4 + #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ + #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ + #define E1000_EECD_PRES 0x00000100 /* NVM Present */ ++#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ + /* NVM Addressing bits based on type 0=small, 1=large */ + #define E1000_EECD_ADDR_BITS 0x00000400 ++#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ + #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ + #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ + #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ + #define E1000_EECD_SIZE_EX_SHIFT 11 ++#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ ++#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ ++#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ ++#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ ++#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ ++#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ ++#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ ++#define E1000_EECD_SECVAL_SHIFT 22 ++#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) + +-/* Offset to data in NVM read/write registers */ +-#define E1000_NVM_RW_REG_DATA 16 ++#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */ ++#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */ ++#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ + #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ + #define E1000_NVM_RW_REG_START 1 /* Start operation */ + #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ ++#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ + #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ ++#define E1000_FLASH_UPDATES 2000 + + /* NVM Word Offsets */ ++#define NVM_COMPAT 0x0003 + #define NVM_ID_LED_SETTINGS 0x0004 +-/* For SERDES output amplitude adjustment. */ ++#define NVM_VERSION 0x0005 ++#define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ ++#define NVM_PHY_CLASS_WORD 0x0007 ++#define NVM_INIT_CONTROL1_REG 0x000A + #define NVM_INIT_CONTROL2_REG 0x000F ++#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 ++#define NVM_INIT_CONTROL3_PORT_B 0x0014 ++#define NVM_INIT_3GIO_3 0x001A ++#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 + #define NVM_INIT_CONTROL3_PORT_A 0x0024 ++#define NVM_CFG 0x0012 ++#define NVM_FLASH_VERSION 0x0032 + #define NVM_ALT_MAC_ADDR_PTR 0x0037 + #define NVM_CHECKSUM_REG 0x003F + +-#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ +-#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ ++#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ ++#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ + + /* Mask bits for fields in Word 0x0f of the NVM */ + #define NVM_WORD0F_PAUSE_MASK 0x3000 ++#define NVM_WORD0F_PAUSE 0x1000 + #define NVM_WORD0F_ASM_DIR 0x2000 ++#define NVM_WORD0F_ANE 0x0800 ++#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 ++#define NVM_WORD0F_LPLU 0x0001 + + /* Mask bits for fields in Word 0x1a of the NVM */ ++#define NVM_WORD1A_ASPM_MASK 0x000C + + /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ + #define NVM_SUM 0xBABA + ++#define NVM_MAC_ADDR_OFFSET 0 + #define NVM_PBA_OFFSET_0 8 + #define NVM_PBA_OFFSET_1 9 ++#define NVM_RESERVED_WORD 0xFFFF ++#define NVM_PHY_CLASS_A 0x8000 ++#define NVM_SERDES_AMPLITUDE_MASK 0x000F ++#define NVM_SIZE_MASK 0x1C00 ++#define NVM_SIZE_SHIFT 10 + #define NVM_WORD_SIZE_BASE_SHIFT 6 +- +-/* NVM Commands - Microwire */ ++#define NVM_SWDPIO_EXT_SHIFT 4 + + /* NVM Commands - SPI */ + #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ ++#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ + #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ + #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ + #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ ++#define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */ + #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ ++#define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */ + + /* SPI NVM Status Register */ + #define NVM_STATUS_RDY_SPI 0x01 ++#define NVM_STATUS_WEN_SPI 0x02 ++#define NVM_STATUS_BP0_SPI 0x04 ++#define NVM_STATUS_BP1_SPI 0x08 ++#define NVM_STATUS_WPEN_SPI 0x80 + + /* Word definitions for ID LED Settings */ + #define ID_LED_RESERVED_0000 0x0000 + #define ID_LED_RESERVED_FFFF 0xFFFF + #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ +- (ID_LED_OFF1_OFF2 << 8) | \ +- (ID_LED_DEF1_DEF2 << 4) | \ +- (ID_LED_DEF1_DEF2)) ++ (ID_LED_OFF1_OFF2 << 8) | \ ++ (ID_LED_DEF1_DEF2 << 4) | \ ++ (ID_LED_DEF1_DEF2)) + #define ID_LED_DEF1_DEF2 0x1 + #define ID_LED_DEF1_ON2 0x2 + #define ID_LED_DEF1_OFF2 0x3 +@@ -670,10 +1222,16 @@ + /* PCI/PCI-X/PCI-EX Config space */ + #define PCI_HEADER_TYPE_REGISTER 0x0E + #define PCIE_LINK_STATUS 0x12 ++#define PCIE_DEVICE_CONTROL2 0x28 + + #define PCI_HEADER_TYPE_MULTIFUNC 0x80 + #define PCIE_LINK_WIDTH_MASK 0x3F0 + #define PCIE_LINK_WIDTH_SHIFT 4 ++#define PCIE_DEVICE_CONTROL2_16ms 0x0005 ++ ++#ifndef ETH_ADDR_LEN ++#define ETH_ADDR_LEN 6 ++#endif + + #define PHY_REVISION_MASK 0xFFFFFFF0 + #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ +@@ -684,23 +1242,42 @@ + * I = Integrated + * E = External + */ ++#define M88E1000_E_PHY_ID 0x01410C50 ++#define M88E1000_I_PHY_ID 0x01410C30 ++#define M88E1011_I_PHY_ID 0x01410C20 ++#define IGP01E1000_I_PHY_ID 0x02A80380 ++#define M88E1011_I_REV_4 0x04 + #define M88E1111_I_PHY_ID 0x01410CC0 ++#define GG82563_E_PHY_ID 0x01410CA0 + #define IGP03E1000_E_PHY_ID 0x02A80390 ++#define IFE_E_PHY_ID 0x02A80330 ++#define IFE_PLUS_E_PHY_ID 0x02A80320 ++#define IFE_C_E_PHY_ID 0x02A80310 ++#define IGP04E1000_E_PHY_ID 0x02A80391 + #define M88_VENDOR 0x0141 + + /* M88E1000 Specific Registers */ + #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ + #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ ++#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ ++#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ + #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ ++#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ + ++#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ + #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ + #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ ++#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ ++#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ + + /* M88E1000 PHY Specific Control Register */ +-#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ ++#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ ++#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ ++#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ + /* 1=CLK125 low, 0=CLK125 toggling */ +-#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ +- /* Manual MDI configuration */ ++#define M88E1000_PSCR_CLK125_DISABLE 0x0010 ++#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ ++ /* Manual MDI configuration */ + #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ + /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ + #define M88E1000_PSCR_AUTO_X_1000T 0x0040 +@@ -710,10 +1287,15 @@ + * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold + * 0=Normal 10BASE-T Rx Threshold + */ ++#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 + /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ +-#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ ++#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 ++#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ ++#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ ++#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ + + /* M88E1000 PHY Specific Status Register */ ++#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ + #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ + #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ + #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ +@@ -725,42 +1307,143 @@ + * 4 = >140M + */ + #define M88E1000_PSSR_CABLE_LENGTH 0x0380 ++#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ ++#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ ++#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ ++#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ + #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ ++#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ ++#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ + #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ + + #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 + + /* M88E1000 Extended PHY Specific Control Register */ ++#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ + /* + * 1 = Lost lock detect enabled. + * Will assert lost lock and bring + * link down if idle not seen + * within 1ms in 1000BASE-T + */ ++#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 + /* + * Number of times we will attempt to autonegotiate before downshifting if we + * are the master + */ + #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 + #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 + /* + * Number of times we will attempt to autonegotiate before downshifting if we + * are the slave + */ + #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 + #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 ++#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ + #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ ++#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ + + /* M88EC018 Rev 2 specific DownShift settings */ + #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 + #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 ++ ++/* ++ * Bits... ++ * 15-5: page ++ * 4-0: register offset ++ */ ++#define GG82563_PAGE_SHIFT 5 ++#define GG82563_REG(page, reg) \ ++ (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) ++#define GG82563_MIN_ALT_REG 30 ++ ++/* GG82563 Specific Registers */ ++#define GG82563_PHY_SPEC_CTRL \ ++ GG82563_REG(0, 16) /* PHY Specific Control */ ++#define GG82563_PHY_SPEC_STATUS \ ++ GG82563_REG(0, 17) /* PHY Specific Status */ ++#define GG82563_PHY_INT_ENABLE \ ++ GG82563_REG(0, 18) /* Interrupt Enable */ ++#define GG82563_PHY_SPEC_STATUS_2 \ ++ GG82563_REG(0, 19) /* PHY Specific Status 2 */ ++#define GG82563_PHY_RX_ERR_CNTR \ ++ GG82563_REG(0, 21) /* Receive Error Counter */ ++#define GG82563_PHY_PAGE_SELECT \ ++ GG82563_REG(0, 22) /* Page Select */ ++#define GG82563_PHY_SPEC_CTRL_2 \ ++ GG82563_REG(0, 26) /* PHY Specific Control 2 */ ++#define GG82563_PHY_PAGE_SELECT_ALT \ ++ GG82563_REG(0, 29) /* Alternate Page Select */ ++#define GG82563_PHY_TEST_CLK_CTRL \ ++ GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ ++ ++#define GG82563_PHY_MAC_SPEC_CTRL \ ++ GG82563_REG(2, 21) /* MAC Specific Control Register */ ++#define GG82563_PHY_MAC_SPEC_CTRL_2 \ ++ GG82563_REG(2, 26) /* MAC Specific Control 2 */ ++ ++#define GG82563_PHY_DSP_DISTANCE \ ++ GG82563_REG(5, 26) /* DSP Distance */ ++ ++/* Page 193 - Port Control Registers */ ++#define GG82563_PHY_KMRN_MODE_CTRL \ ++ GG82563_REG(193, 16) /* Kumeran Mode Control */ ++#define GG82563_PHY_PORT_RESET \ ++ GG82563_REG(193, 17) /* Port Reset */ ++#define GG82563_PHY_REVISION_ID \ ++ GG82563_REG(193, 18) /* Revision ID */ ++#define GG82563_PHY_DEVICE_ID \ ++ GG82563_REG(193, 19) /* Device ID */ ++#define GG82563_PHY_PWR_MGMT_CTRL \ ++ GG82563_REG(193, 20) /* Power Management Control */ ++#define GG82563_PHY_RATE_ADAPT_CTRL \ ++ GG82563_REG(193, 25) /* Rate Adaptation Control */ ++ ++/* Page 194 - KMRN Registers */ ++#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ ++ GG82563_REG(194, 16) /* FIFO's Control/Status */ ++#define GG82563_PHY_KMRN_CTRL \ ++ GG82563_REG(194, 17) /* Control */ ++#define GG82563_PHY_INBAND_CTRL \ ++ GG82563_REG(194, 18) /* Inband Control */ ++#define GG82563_PHY_KMRN_DIAGNOSTIC \ ++ GG82563_REG(194, 19) /* Diagnostic */ ++#define GG82563_PHY_ACK_TIMEOUTS \ ++ GG82563_REG(194, 20) /* Acknowledge Timeouts */ ++#define GG82563_PHY_ADV_ABILITY \ ++ GG82563_REG(194, 21) /* Advertised Ability */ ++#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ ++ GG82563_REG(194, 23) /* Link Partner Advertised Ability */ ++#define GG82563_PHY_ADV_NEXT_PAGE \ ++ GG82563_REG(194, 24) /* Advertised Next Page */ ++#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ ++ GG82563_REG(194, 25) /* Link Partner Advertised Next page */ ++#define GG82563_PHY_KMRN_MISC \ ++ GG82563_REG(194, 26) /* Misc. */ + + /* MDI Control */ ++#define E1000_MDIC_DATA_MASK 0x0000FFFF ++#define E1000_MDIC_REG_MASK 0x001F0000 + #define E1000_MDIC_REG_SHIFT 16 ++#define E1000_MDIC_PHY_MASK 0x03E00000 + #define E1000_MDIC_PHY_SHIFT 21 + #define E1000_MDIC_OP_WRITE 0x04000000 + #define E1000_MDIC_OP_READ 0x08000000 + #define E1000_MDIC_READY 0x10000000 ++#define E1000_MDIC_INT_EN 0x20000000 + #define E1000_MDIC_ERROR 0x40000000 + + /* SerDes Control */ +@@ -768,4 +1451,30 @@ + #define E1000_GEN_CTL_ADDRESS_SHIFT 8 + #define E1000_GEN_POLL_TIMEOUT 640 + +-#endif ++/* LinkSec register fields */ ++#define E1000_LSECTXCAP_SUM_MASK 0x00FF0000 ++#define E1000_LSECTXCAP_SUM_SHIFT 16 ++#define E1000_LSECRXCAP_SUM_MASK 0x00FF0000 ++#define E1000_LSECRXCAP_SUM_SHIFT 16 ++ ++#define E1000_LSECTXCTRL_EN_MASK 0x00000003 ++#define E1000_LSECTXCTRL_DISABLE 0x0 ++#define E1000_LSECTXCTRL_AUTH 0x1 ++#define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2 ++#define E1000_LSECTXCTRL_AISCI 0x00000020 ++#define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 ++#define E1000_LSECTXCTRL_RSV_MASK 0x000000D8 ++ ++#define E1000_LSECRXCTRL_EN_MASK 0x0000000C ++#define E1000_LSECRXCTRL_EN_SHIFT 2 ++#define E1000_LSECRXCTRL_DISABLE 0x0 ++#define E1000_LSECRXCTRL_CHECK 0x1 ++#define E1000_LSECRXCTRL_STRICT 0x2 ++#define E1000_LSECRXCTRL_DROP 0x3 ++#define E1000_LSECRXCTRL_PLSH 0x00000040 ++#define E1000_LSECRXCTRL_RP 0x00000080 ++#define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33 ++ ++ ++ ++#endif /* _E1000_DEFINES_H_ */ +diff -r 4f0f8bc35440 drivers/net/igb/e1000_hw.h +--- a/drivers/net/igb/e1000_hw.h Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/e1000_hw.h Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -28,11 +28,7 @@ + #ifndef _E1000_HW_H_ + #define _E1000_HW_H_ + +-#include +-#include +-#include +- +-#include "e1000_mac.h" ++#include "e1000_osdep.h" + #include "e1000_regs.h" + #include "e1000_defines.h" + +@@ -41,14 +37,23 @@ + #define E1000_DEV_ID_82576 0x10C9 + #define E1000_DEV_ID_82576_FIBER 0x10E6 + #define E1000_DEV_ID_82576_SERDES 0x10E7 ++#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 ++#define E1000_DEV_ID_82576_NS 0x150A ++#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D + #define E1000_DEV_ID_82575EB_COPPER 0x10A7 + #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 + #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 +- ++#define E1000_REVISION_0 0 ++#define E1000_REVISION_1 1 + #define E1000_REVISION_2 2 ++#define E1000_REVISION_3 3 + #define E1000_REVISION_4 4 + ++#define E1000_FUNC_0 0 + #define E1000_FUNC_1 1 ++ ++#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 ++#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 + + enum e1000_mac_type { + e1000_undefined = 0, +@@ -69,7 +74,6 @@ + e1000_nvm_unknown = 0, + e1000_nvm_none, + e1000_nvm_eeprom_spi, +- e1000_nvm_eeprom_microwire, + e1000_nvm_flash_hw, + e1000_nvm_flash_sw + }; +@@ -78,8 +82,6 @@ + e1000_nvm_override_none = 0, + e1000_nvm_override_spi_small, + e1000_nvm_override_spi_large, +- e1000_nvm_override_microwire_small, +- e1000_nvm_override_microwire_large + }; + + enum e1000_phy_type { +@@ -91,6 +93,7 @@ + e1000_phy_gg82563, + e1000_phy_igp_3, + e1000_phy_ife, ++ e1000_phy_vf, + }; + + enum e1000_bus_type { +@@ -136,7 +139,7 @@ + e1000_rev_polarity_undefined = 0xFF + }; + +-enum e1000_fc_type { ++enum e1000_fc_mode { + e1000_fc_none = 0, + e1000_fc_rx_pause, + e1000_fc_tx_pause, +@@ -144,14 +147,33 @@ + e1000_fc_default = 0xFF + }; + ++enum e1000_ms_type { ++ e1000_ms_hw_default = 0, ++ e1000_ms_force_master, ++ e1000_ms_force_slave, ++ e1000_ms_auto ++}; ++ ++enum e1000_smart_speed { ++ e1000_smart_speed_default = 0, ++ e1000_smart_speed_on, ++ e1000_smart_speed_off ++}; ++ ++enum e1000_serdes_link_state { ++ e1000_serdes_link_down = 0, ++ e1000_serdes_link_autoneg_progress, ++ e1000_serdes_link_autoneg_complete, ++ e1000_serdes_link_forced_up ++}; + + /* Receive Descriptor */ + struct e1000_rx_desc { + __le64 buffer_addr; /* Address of the descriptor's data buffer */ + __le16 length; /* Length of data DMAed into data buffer */ + __le16 csum; /* Packet checksum */ +- u8 status; /* Descriptor status */ +- u8 errors; /* Descriptor Errors */ ++ u8 status; /* Descriptor status */ ++ u8 errors; /* Descriptor Errors */ + __le16 special; + }; + +@@ -163,9 +185,9 @@ + } read; + struct { + struct { +- __le32 mrq; /* Multiple Rx Queues */ ++ __le32 mrq; /* Multiple Rx Queues */ + union { +- __le32 rss; /* RSS Hash */ ++ __le32 rss; /* RSS Hash */ + struct { + __le16 ip_id; /* IP id */ + __le16 csum; /* Packet Checksum */ +@@ -173,9 +195,9 @@ + } hi_dword; + } lower; + struct { +- __le32 status_error; /* ext status/error */ ++ __le32 status_error; /* ext status/error */ + __le16 length; +- __le16 vlan; /* VLAN tag */ ++ __le16 vlan; /* VLAN tag */ + } upper; + } wb; /* writeback */ + }; +@@ -189,9 +211,9 @@ + } read; + struct { + struct { +- __le32 mrq; /* Multiple Rx Queues */ ++ __le32 mrq; /* Multiple Rx Queues */ + union { +- __le32 rss; /* RSS Hash */ ++ __le32 rss; /* RSS Hash */ + struct { + __le16 ip_id; /* IP id */ + __le16 csum; /* Packet Checksum */ +@@ -199,13 +221,13 @@ + } hi_dword; + } lower; + struct { +- __le32 status_error; /* ext status/error */ +- __le16 length0; /* length of buffer 0 */ +- __le16 vlan; /* VLAN tag */ ++ __le32 status_error; /* ext status/error */ ++ __le16 length0; /* length of buffer 0 */ ++ __le16 vlan; /* VLAN tag */ + } middle; + struct { + __le16 header_status; +- __le16 length[3]; /* length of buffers 1-3 */ ++ __le16 length[3]; /* length of buffers 1-3 */ + } upper; + __le64 reserved; + } wb; /* writeback */ +@@ -213,20 +235,20 @@ + + /* Transmit Descriptor */ + struct e1000_tx_desc { +- __le64 buffer_addr; /* Address of the descriptor's data buffer */ ++ __le64 buffer_addr; /* Address of the descriptor's data buffer */ + union { + __le32 data; + struct { + __le16 length; /* Data buffer length */ +- u8 cso; /* Checksum offset */ +- u8 cmd; /* Descriptor control */ ++ u8 cso; /* Checksum offset */ ++ u8 cmd; /* Descriptor control */ + } flags; + } lower; + union { + __le32 data; + struct { +- u8 status; /* Descriptor status */ +- u8 css; /* Checksum start */ ++ u8 status; /* Descriptor status */ ++ u8 css; /* Checksum start */ + __le16 special; + } fields; + } upper; +@@ -237,16 +259,16 @@ + union { + __le32 ip_config; + struct { +- u8 ipcss; /* IP checksum start */ +- u8 ipcso; /* IP checksum offset */ ++ u8 ipcss; /* IP checksum start */ ++ u8 ipcso; /* IP checksum offset */ + __le16 ipcse; /* IP checksum end */ + } ip_fields; + } lower_setup; + union { + __le32 tcp_config; + struct { +- u8 tucss; /* TCP checksum start */ +- u8 tucso; /* TCP checksum offset */ ++ u8 tucss; /* TCP checksum start */ ++ u8 tucso; /* TCP checksum offset */ + __le16 tucse; /* TCP checksum end */ + } tcp_fields; + } upper_setup; +@@ -254,8 +276,8 @@ + union { + __le32 data; + struct { +- u8 status; /* Descriptor status */ +- u8 hdr_len; /* Header length */ ++ u8 status; /* Descriptor status */ ++ u8 hdr_len; /* Header length */ + __le16 mss; /* Maximum segment size */ + } fields; + } tcp_seg_setup; +@@ -275,8 +297,8 @@ + union { + __le32 data; + struct { +- u8 status; /* Descriptor status */ +- u8 popts; /* Packet Options */ ++ u8 status; /* Descriptor status */ ++ u8 popts; /* Packet Options */ + __le16 special; + } fields; + } upper; +@@ -359,7 +381,9 @@ + u64 lenerrs; + u64 scvpc; + u64 hrmpc; ++ u64 doosync; + }; ++ + + struct e1000_phy_stats { + u32 idle_errors; +@@ -409,52 +433,77 @@ + #include "e1000_mac.h" + #include "e1000_phy.h" + #include "e1000_nvm.h" ++#include "e1000_manage.h" + + struct e1000_mac_operations { ++ /* Function pointers for the MAC. */ ++ s32 (*init_params)(struct e1000_hw *); ++ s32 (*id_led_init)(struct e1000_hw *); ++ s32 (*blink_led)(struct e1000_hw *); + s32 (*check_for_link)(struct e1000_hw *); ++ bool (*check_mng_mode)(struct e1000_hw *hw); ++ s32 (*cleanup_led)(struct e1000_hw *); ++ void (*clear_hw_cntrs)(struct e1000_hw *); ++ void (*clear_vfta)(struct e1000_hw *); ++ s32 (*get_bus_info)(struct e1000_hw *); ++ void (*set_lan_id)(struct e1000_hw *); ++ s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); ++ s32 (*led_on)(struct e1000_hw *); ++ s32 (*led_off)(struct e1000_hw *); ++ void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); + s32 (*reset_hw)(struct e1000_hw *); + s32 (*init_hw)(struct e1000_hw *); +- bool (*check_mng_mode)(struct e1000_hw *); ++ void (*shutdown_serdes)(struct e1000_hw *); ++ s32 (*setup_link)(struct e1000_hw *); + s32 (*setup_physical_interface)(struct e1000_hw *); +- void (*rar_set)(struct e1000_hw *, u8 *, u32); ++ s32 (*setup_led)(struct e1000_hw *); ++ void (*write_vfta)(struct e1000_hw *, u32, u32); ++ void (*mta_set)(struct e1000_hw *, u32); ++ void (*config_collision_dist)(struct e1000_hw *); ++ void (*rar_set)(struct e1000_hw *, u8*, u32); + s32 (*read_mac_addr)(struct e1000_hw *); +- s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); ++ s32 (*validate_mdi_setting)(struct e1000_hw *); ++ s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); ++ s32 (*mng_write_cmd_header)(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header*); ++ s32 (*mng_enable_host_if)(struct e1000_hw *); ++ s32 (*wait_autoneg)(struct e1000_hw *); + }; + + struct e1000_phy_operations { +- s32 (*acquire_phy)(struct e1000_hw *); ++ s32 (*init_params)(struct e1000_hw *); ++ s32 (*acquire)(struct e1000_hw *); ++ s32 (*check_polarity)(struct e1000_hw *); + s32 (*check_reset_block)(struct e1000_hw *); ++ s32 (*commit)(struct e1000_hw *); + s32 (*force_speed_duplex)(struct e1000_hw *); + s32 (*get_cfg_done)(struct e1000_hw *hw); + s32 (*get_cable_length)(struct e1000_hw *); +- s32 (*get_phy_info)(struct e1000_hw *); +- s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *); +- void (*release_phy)(struct e1000_hw *); +- s32 (*reset_phy)(struct e1000_hw *); ++ s32 (*get_info)(struct e1000_hw *); ++ s32 (*read_reg)(struct e1000_hw *, u32, u16 *); ++ void (*release)(struct e1000_hw *); ++ s32 (*reset)(struct e1000_hw *); + s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); + s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); +- s32 (*write_phy_reg)(struct e1000_hw *, u32, u16); ++ s32 (*write_reg)(struct e1000_hw *, u32, u16); ++ void (*power_up)(struct e1000_hw *); ++ void (*power_down)(struct e1000_hw *); + }; + + struct e1000_nvm_operations { +- s32 (*acquire_nvm)(struct e1000_hw *); +- s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *); +- void (*release_nvm)(struct e1000_hw *); +- s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *); ++ s32 (*init_params)(struct e1000_hw *); ++ s32 (*acquire)(struct e1000_hw *); ++ s32 (*read)(struct e1000_hw *, u16, u16, u16 *); ++ void (*release)(struct e1000_hw *); ++ void (*reload)(struct e1000_hw *); ++ s32 (*update)(struct e1000_hw *); ++ s32 (*valid_led_default)(struct e1000_hw *, u16 *); ++ s32 (*validate)(struct e1000_hw *); ++ s32 (*write)(struct e1000_hw *, u16, u16, u16 *); + }; +- +-struct e1000_info { +- s32 (*get_invariants)(struct e1000_hw *); +- struct e1000_mac_operations *mac_ops; +- struct e1000_phy_operations *phy_ops; +- struct e1000_nvm_operations *nvm_ops; +-}; +- +-extern const struct e1000_info e1000_82575_info; + + struct e1000_mac_info { + struct e1000_mac_operations ops; +- + u8 addr[6]; + u8 perm_addr[6]; + +@@ -474,6 +523,10 @@ + u16 ifs_ratio; + u16 ifs_step_size; + u16 mta_reg_count; ++ ++ /* Maximum size of the MTA register table in all supported adapters */ ++ #define MAX_MTA_REG 128 ++ u32 mta_shadow[MAX_MTA_REG]; + u16 rar_entry_count; + + u8 forced_speed_duplex; +@@ -483,19 +536,15 @@ + bool asf_firmware_present; + bool autoneg; + bool autoneg_failed; +- bool disable_av; +- bool disable_hw_init_bits; + bool get_link_status; +- bool ifs_params_forced; + bool in_ifs_mode; +- bool report_tx_early; ++ enum e1000_serdes_link_state serdes_link_state; + bool serdes_has_link; + bool tx_pkt_filtering; + }; + + struct e1000_phy_info { + struct e1000_phy_operations ops; +- + enum e1000_phy_type type; + + enum e1000_1000t_rx_status local_rx; +@@ -530,7 +579,6 @@ + + struct e1000_nvm_info { + struct e1000_nvm_operations ops; +- + enum e1000_nvm_type type; + enum e1000_nvm_override override; + +@@ -549,25 +597,33 @@ + enum e1000_bus_speed speed; + enum e1000_bus_width width; + +- u32 snoop; +- + u16 func; + u16 pci_cmd_word; + }; + + struct e1000_fc_info { +- u32 high_water; /* Flow control high-water mark */ +- u32 low_water; /* Flow control low-water mark */ +- u16 pause_time; /* Flow control pause timer */ +- bool send_xon; /* Flow control send XON */ +- bool strict_ieee; /* Strict IEEE mode */ +- enum e1000_fc_type type; /* Type of flow control */ +- enum e1000_fc_type original_type; ++ u32 high_water; /* Flow control high-water mark */ ++ u32 low_water; /* Flow control low-water mark */ ++ u16 pause_time; /* Flow control pause timer */ ++ bool send_xon; /* Flow control send XON */ ++ bool strict_ieee; /* Strict IEEE mode */ ++ enum e1000_fc_mode current_mode; /* FC mode in effect */ ++ enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ + }; ++ ++struct e1000_dev_spec_82575 { ++ bool sgmii_active; ++ bool global_device_reset; ++}; ++ ++struct e1000_dev_spec_vf { ++ u32 vf_number; ++ u32 v2p_mailbox; ++}; ++ + + struct e1000_hw { + void *back; +- void *dev_spec; + + u8 __iomem *hw_addr; + u8 __iomem *flash_address; +@@ -580,7 +636,10 @@ + struct e1000_bus_info bus; + struct e1000_host_mng_dhcp_cookie mng_cookie; + +- u32 dev_spec_size; ++ union { ++ struct e1000_dev_spec_82575 _82575; ++ struct e1000_dev_spec_vf vf; ++ } dev_spec; + + u16 device_id; + u16 subsystem_vendor_id; +@@ -590,12 +649,10 @@ + u8 revision_id; + }; + +-#ifdef DEBUG +-extern char *igb_get_hw_dev_name(struct e1000_hw *hw); +-#define hw_dbg(format, arg...) \ +- printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg) +-#else +-#define hw_dbg(format, arg...) +-#endif ++#include "e1000_82575.h" ++ ++/* These functions must be implemented by drivers */ ++s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); ++s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); + + #endif +diff -r 4f0f8bc35440 drivers/net/igb/e1000_mac.c +--- a/drivers/net/igb/e1000_mac.c Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/e1000_mac.c Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -25,111 +25,131 @@ + + *******************************************************************************/ + +-#include +-#include +-#include +-#include ++#include "e1000_api.h" + +-#include "e1000_mac.h" +- +-#include "igb.h" +- +-static s32 igb_set_default_fc(struct e1000_hw *hw); +-static s32 igb_set_fc_watermarks(struct e1000_hw *hw); ++static s32 e1000_set_default_fc_generic(struct e1000_hw *hw); ++static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw); ++static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw); ++static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); ++static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); + + /** +- * igb_remove_device - Free device specific structure ++ * e1000_init_mac_ops_generic - Initialize MAC function pointers + * @hw: pointer to the HW structure + * +- * If a device specific structure was allocated, this function will +- * free it. ++ * Setups up the function pointers to no-op functions + **/ +-void igb_remove_device(struct e1000_hw *hw) ++void e1000_init_mac_ops_generic(struct e1000_hw *hw) + { +- /* Freeing the dev_spec member of e1000_hw structure */ +- kfree(hw->dev_spec); +-} ++ struct e1000_mac_info *mac = &hw->mac; ++ DEBUGFUNC("e1000_init_mac_ops_generic"); + +-static void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) +-{ +- struct igb_adapter *adapter = hw->back; +- +- pci_read_config_word(adapter->pdev, reg, value); +-} +- +-static s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) +-{ +- struct igb_adapter *adapter = hw->back; +- u16 cap_offset; +- +- cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); +- if (!cap_offset) +- return -E1000_ERR_CONFIG; +- +- pci_read_config_word(adapter->pdev, cap_offset + reg, value); +- +- return 0; ++ /* General Setup */ ++ mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; ++ mac->ops.read_mac_addr = e1000_read_mac_addr_generic; ++ mac->ops.config_collision_dist = e1000_config_collision_dist_generic; ++ /* LINK */ ++ mac->ops.wait_autoneg = e1000_wait_autoneg_generic; ++ /* Management */ ++ mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; ++ mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; ++ mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; ++ /* VLAN, MC, etc. */ ++ mac->ops.rar_set = e1000_rar_set_generic; ++ mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; + } + + /** +- * igb_get_bus_info_pcie - Get PCIe bus information ++ * e1000_get_bus_info_pcie_generic - Get PCIe bus information + * @hw: pointer to the HW structure + * + * Determines and stores the system bus information for a particular + * network interface. The following bus information is determined and stored: + * bus speed, bus width, type (PCIe), and PCIe function. + **/ +-s32 igb_get_bus_info_pcie(struct e1000_hw *hw) ++s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) + { ++ struct e1000_mac_info *mac = &hw->mac; + struct e1000_bus_info *bus = &hw->bus; ++ + s32 ret_val; +- u32 status; +- u16 pcie_link_status, pci_header_type; ++ u16 pcie_link_status; ++ ++ DEBUGFUNC("e1000_get_bus_info_pcie_generic"); + + bus->type = e1000_bus_type_pci_express; + bus->speed = e1000_bus_speed_2500; + +- ret_val = igb_read_pcie_cap_reg(hw, +- PCIE_LINK_STATUS, +- &pcie_link_status); ++ ret_val = e1000_read_pcie_cap_reg(hw, ++ PCIE_LINK_STATUS, ++ &pcie_link_status); + if (ret_val) + bus->width = e1000_bus_width_unknown; + else + bus->width = (enum e1000_bus_width)((pcie_link_status & +- PCIE_LINK_WIDTH_MASK) >> +- PCIE_LINK_WIDTH_SHIFT); ++ PCIE_LINK_WIDTH_MASK) >> ++ PCIE_LINK_WIDTH_SHIFT); + +- igb_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); +- if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { +- status = rd32(E1000_STATUS); +- bus->func = (status & E1000_STATUS_FUNC_MASK) +- >> E1000_STATUS_FUNC_SHIFT; +- } else { +- bus->func = 0; +- } ++ mac->ops.set_lan_id(hw); + +- return 0; ++ return E1000_SUCCESS; + } + + /** +- * igb_clear_vfta - Clear VLAN filter table ++ * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices ++ * ++ * @hw: pointer to the HW structure ++ * ++ * Determines the LAN function id by reading memory-mapped registers ++ * and swaps the port value if requested. ++ **/ ++static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) ++{ ++ struct e1000_bus_info *bus = &hw->bus; ++ u32 reg; ++ ++ /* ++ * The status register reports the correct function number ++ * for the device regardless of function swap state. ++ */ ++ reg = E1000_READ_REG(hw, E1000_STATUS); ++ bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; ++} ++ ++/** ++ * e1000_set_lan_id_single_port - Set LAN id for a single port device ++ * @hw: pointer to the HW structure ++ * ++ * Sets the LAN function id to zero for a single port device. ++ **/ ++void e1000_set_lan_id_single_port(struct e1000_hw *hw) ++{ ++ struct e1000_bus_info *bus = &hw->bus; ++ ++ bus->func = 0; ++} ++ ++/** ++ * e1000_clear_vfta_generic - Clear VLAN filter table + * @hw: pointer to the HW structure + * + * Clears the register array which contains the VLAN filter table by + * setting all the values to 0. + **/ +-void igb_clear_vfta(struct e1000_hw *hw) ++void e1000_clear_vfta_generic(struct e1000_hw *hw) + { + u32 offset; + ++ DEBUGFUNC("e1000_clear_vfta_generic"); ++ + for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { +- array_wr32(E1000_VFTA, offset, 0); +- wrfl(); ++ E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); ++ E1000_WRITE_FLUSH(hw); + } + } + + /** +- * igb_write_vfta - Write value to VLAN filter table ++ * e1000_write_vfta_generic - Write value to VLAN filter table + * @hw: pointer to the HW structure + * @offset: register offset in VLAN filter table + * @value: register value written to VLAN filter table +@@ -137,50 +157,81 @@ + * Writes value at the given offset in the register array which stores + * the VLAN filter table. + **/ +-void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) ++void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) + { +- array_wr32(E1000_VFTA, offset, value); +- wrfl(); ++ DEBUGFUNC("e1000_write_vfta_generic"); ++ ++ E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); ++ E1000_WRITE_FLUSH(hw); + } + + /** +- * igb_check_alt_mac_addr - Check for alternate MAC addr ++ * e1000_init_rx_addrs_generic - Initialize receive address's ++ * @hw: pointer to the HW structure ++ * @rar_count: receive address registers ++ * ++ * Setups the receive address registers by setting the base receive address ++ * register to the devices MAC address and clearing all the other receive ++ * address registers to 0. ++ **/ ++void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) ++{ ++ u32 i; ++ u8 mac_addr[ETH_ADDR_LEN] = {0}; ++ ++ DEBUGFUNC("e1000_init_rx_addrs_generic"); ++ ++ /* Setup the receive address */ ++ DEBUGOUT("Programming MAC Address into RAR[0]\n"); ++ ++ hw->mac.ops.rar_set(hw, hw->mac.addr, 0); ++ ++ /* Zero out the other (rar_entry_count - 1) receive addresses */ ++ DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); ++ for (i = 1; i < rar_count; i++) ++ hw->mac.ops.rar_set(hw, mac_addr, i); ++} ++ ++/** ++ * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr + * @hw: pointer to the HW structure + * + * Checks the nvm for an alternate MAC address. An alternate MAC address + * can be setup by pre-boot software and must be treated like a permanent +- * address and must override the actual permanent MAC address. If an +- * alternate MAC address is fopund it is saved in the hw struct and +- * prgrammed into RAR0 and the cuntion returns success, otherwise the +- * fucntion returns an error. ++ * address and must override the actual permanent MAC address. If an ++ * alternate MAC address is found it is programmed into RAR0, replacing ++ * the permanent address that was installed into RAR0 by the Si on reset. ++ * This function will return SUCCESS unless it encounters an error while ++ * reading the EEPROM. + **/ +-s32 igb_check_alt_mac_addr(struct e1000_hw *hw) ++s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) + { + u32 i; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + u16 offset, nvm_alt_mac_addr_offset, nvm_data; +- u8 alt_mac_addr[ETH_ALEN]; ++ u8 alt_mac_addr[ETH_ADDR_LEN]; + +- ret_val = hw->nvm.ops.read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, +- &nvm_alt_mac_addr_offset); ++ DEBUGFUNC("e1000_check_alt_mac_addr_generic"); ++ ++ ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, ++ &nvm_alt_mac_addr_offset); + if (ret_val) { +- hw_dbg("NVM Read Error\n"); ++ DEBUGOUT("NVM Read Error\n"); + goto out; + } + + if (nvm_alt_mac_addr_offset == 0xFFFF) { +- ret_val = -(E1000_NOT_IMPLEMENTED); ++ /* There is no Alternate MAC Address */ + goto out; + } + + if (hw->bus.func == E1000_FUNC_1) +- nvm_alt_mac_addr_offset += ETH_ALEN/sizeof(u16); +- +- for (i = 0; i < ETH_ALEN; i += 2) { ++ nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; ++ for (i = 0; i < ETH_ADDR_LEN; i += 2) { + offset = nvm_alt_mac_addr_offset + (i >> 1); +- ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data); ++ ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); + if (ret_val) { +- hw_dbg("NVM Read Error\n"); ++ DEBUGOUT("NVM Read Error\n"); + goto out; + } + +@@ -190,21 +241,23 @@ + + /* if multicast bit is set, the alternate address will not be used */ + if (alt_mac_addr[0] & 0x01) { +- ret_val = -(E1000_NOT_IMPLEMENTED); ++ DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); + goto out; + } + +- for (i = 0; i < ETH_ALEN; i++) +- hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i]; +- +- hw->mac.ops.rar_set(hw, hw->mac.perm_addr, 0); ++ /* ++ * We have a valid alternate MAC address, and we want to treat it the ++ * same as the normal permanent MAC address stored by the HW into the ++ * RAR. Do this by mapping this address into RAR0. ++ */ ++ hw->mac.ops.rar_set(hw, alt_mac_addr, 0); + + out: + return ret_val; + } + + /** +- * igb_rar_set - Set receive address register ++ * e1000_rar_set_generic - Set receive address register + * @hw: pointer to the HW structure + * @addr: pointer to the receive address + * @index: receive address array register +@@ -212,29 +265,39 @@ + * Sets the receive address array register at index to the address passed + * in by addr. + **/ +-void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) ++void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) + { + u32 rar_low, rar_high; ++ ++ DEBUGFUNC("e1000_rar_set_generic"); + + /* + * HW expects these in little endian so we reverse the byte order + * from network order (big endian) to little endian + */ + rar_low = ((u32) addr[0] | +- ((u32) addr[1] << 8) | +- ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); ++ ((u32) addr[1] << 8) | ++ ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); + + rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); + +- if (!hw->mac.disable_av) ++ /* If MAC address zero, no need to set the AV bit */ ++ if (rar_low || rar_high) + rar_high |= E1000_RAH_AV; + +- array_wr32(E1000_RA, (index << 1), rar_low); +- array_wr32(E1000_RA, ((index << 1) + 1), rar_high); ++ /* ++ * Some bridges will combine consecutive 32-bit writes into ++ * a single burst write, which will malfunction on some parts. ++ * The flushes avoid this. ++ */ ++ E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); ++ E1000_WRITE_FLUSH(hw); ++ E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); ++ E1000_WRITE_FLUSH(hw); + } + + /** +- * igb_mta_set - Set multicast filter table address ++ * e1000_mta_set_generic - Set multicast filter table address + * @hw: pointer to the HW structure + * @hash_value: determines the MTA register and bit to set + * +@@ -243,10 +306,11 @@ + * current value is read, the new bit is OR'd in and the new value is + * written back into the register. + **/ +-void igb_mta_set(struct e1000_hw *hw, u32 hash_value) ++void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) + { + u32 hash_bit, hash_reg, mta; + ++ DEBUGFUNC("e1000_mta_set_generic"); + /* + * The MTA is a register array of 32-bit registers. It is + * treated like an array of (32*mta_reg_count) bits. We want to +@@ -260,27 +324,66 @@ + hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); + hash_bit = hash_value & 0x1F; + +- mta = array_rd32(E1000_MTA, hash_reg); ++ mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); + + mta |= (1 << hash_bit); + +- array_wr32(E1000_MTA, hash_reg, mta); +- wrfl(); ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); ++ E1000_WRITE_FLUSH(hw); + } + + /** +- * igb_hash_mc_addr - Generate a multicast hash value ++ * e1000_update_mc_addr_list_generic - Update Multicast addresses ++ * @hw: pointer to the HW structure ++ * @mc_addr_list: array of multicast addresses to program ++ * @mc_addr_count: number of multicast addresses to program ++ * ++ * Updates entire Multicast Table Array. ++ * The caller must have a packed mc_addr_list of multicast addresses. ++ **/ ++void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, ++ u8 *mc_addr_list, u32 mc_addr_count) ++{ ++ u32 hash_value, hash_bit, hash_reg; ++ int i; ++ ++ DEBUGFUNC("e1000_update_mc_addr_list_generic"); ++ ++ /* clear mta_shadow */ ++ memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); ++ ++ /* update mta_shadow from mc_addr_list */ ++ for (i = 0; (u32) i < mc_addr_count; i++) { ++ hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); ++ ++ hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); ++ hash_bit = hash_value & 0x1F; ++ ++ hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); ++ mc_addr_list += (ETH_ADDR_LEN); ++ } ++ ++ /* replace the entire MTA table */ ++ for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); ++ E1000_WRITE_FLUSH(hw); ++} ++ ++/** ++ * e1000_hash_mc_addr_generic - Generate a multicast hash value + * @hw: pointer to the HW structure + * @mc_addr: pointer to a multicast address + * + * Generates a multicast address hash value which is used to determine + * the multicast filter table array address and new table value. See +- * igb_mta_set() ++ * e1000_mta_set_generic() + **/ +-u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) ++u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) + { + u32 hash_value, hash_mask; + u8 bit_shift = 0; ++ ++ DEBUGFUNC("e1000_hash_mc_addr_generic"); + + /* Register count multiplied by bits per register */ + hash_mask = (hw->mac.mta_reg_count * 32) - 1; +@@ -334,73 +437,75 @@ + } + + hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | +- (((u16) mc_addr[5]) << bit_shift))); ++ (((u16) mc_addr[5]) << bit_shift))); + + return hash_value; + } + + /** +- * igb_clear_hw_cntrs_base - Clear base hardware counters ++ * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters + * @hw: pointer to the HW structure + * + * Clears the base hardware counters by reading the counter registers. + **/ +-void igb_clear_hw_cntrs_base(struct e1000_hw *hw) ++void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) + { +- u32 temp; ++ DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); + +- temp = rd32(E1000_CRCERRS); +- temp = rd32(E1000_SYMERRS); +- temp = rd32(E1000_MPC); +- temp = rd32(E1000_SCC); +- temp = rd32(E1000_ECOL); +- temp = rd32(E1000_MCC); +- temp = rd32(E1000_LATECOL); +- temp = rd32(E1000_COLC); +- temp = rd32(E1000_DC); +- temp = rd32(E1000_SEC); +- temp = rd32(E1000_RLEC); +- temp = rd32(E1000_XONRXC); +- temp = rd32(E1000_XONTXC); +- temp = rd32(E1000_XOFFRXC); +- temp = rd32(E1000_XOFFTXC); +- temp = rd32(E1000_FCRUC); +- temp = rd32(E1000_GPRC); +- temp = rd32(E1000_BPRC); +- temp = rd32(E1000_MPRC); +- temp = rd32(E1000_GPTC); +- temp = rd32(E1000_GORCL); +- temp = rd32(E1000_GORCH); +- temp = rd32(E1000_GOTCL); +- temp = rd32(E1000_GOTCH); +- temp = rd32(E1000_RNBC); +- temp = rd32(E1000_RUC); +- temp = rd32(E1000_RFC); +- temp = rd32(E1000_ROC); +- temp = rd32(E1000_RJC); +- temp = rd32(E1000_TORL); +- temp = rd32(E1000_TORH); +- temp = rd32(E1000_TOTL); +- temp = rd32(E1000_TOTH); +- temp = rd32(E1000_TPR); +- temp = rd32(E1000_TPT); +- temp = rd32(E1000_MPTC); +- temp = rd32(E1000_BPTC); ++ E1000_READ_REG(hw, E1000_CRCERRS); ++ E1000_READ_REG(hw, E1000_SYMERRS); ++ E1000_READ_REG(hw, E1000_MPC); ++ E1000_READ_REG(hw, E1000_SCC); ++ E1000_READ_REG(hw, E1000_ECOL); ++ E1000_READ_REG(hw, E1000_MCC); ++ E1000_READ_REG(hw, E1000_LATECOL); ++ E1000_READ_REG(hw, E1000_COLC); ++ E1000_READ_REG(hw, E1000_DC); ++ E1000_READ_REG(hw, E1000_SEC); ++ E1000_READ_REG(hw, E1000_RLEC); ++ E1000_READ_REG(hw, E1000_XONRXC); ++ E1000_READ_REG(hw, E1000_XONTXC); ++ E1000_READ_REG(hw, E1000_XOFFRXC); ++ E1000_READ_REG(hw, E1000_XOFFTXC); ++ E1000_READ_REG(hw, E1000_FCRUC); ++ E1000_READ_REG(hw, E1000_GPRC); ++ E1000_READ_REG(hw, E1000_BPRC); ++ E1000_READ_REG(hw, E1000_MPRC); ++ E1000_READ_REG(hw, E1000_GPTC); ++ E1000_READ_REG(hw, E1000_GORCL); ++ E1000_READ_REG(hw, E1000_GORCH); ++ E1000_READ_REG(hw, E1000_GOTCL); ++ E1000_READ_REG(hw, E1000_GOTCH); ++ E1000_READ_REG(hw, E1000_RNBC); ++ E1000_READ_REG(hw, E1000_RUC); ++ E1000_READ_REG(hw, E1000_RFC); ++ E1000_READ_REG(hw, E1000_ROC); ++ E1000_READ_REG(hw, E1000_RJC); ++ E1000_READ_REG(hw, E1000_TORL); ++ E1000_READ_REG(hw, E1000_TORH); ++ E1000_READ_REG(hw, E1000_TOTL); ++ E1000_READ_REG(hw, E1000_TOTH); ++ E1000_READ_REG(hw, E1000_TPR); ++ E1000_READ_REG(hw, E1000_TPT); ++ E1000_READ_REG(hw, E1000_MPTC); ++ E1000_READ_REG(hw, E1000_BPTC); + } + + /** +- * igb_check_for_copper_link - Check for link (Copper) ++ * e1000_check_for_copper_link_generic - Check for link (Copper) + * @hw: pointer to the HW structure + * + * Checks to see of the link status of the hardware has changed. If a + * change in link status has been detected, then we read the PHY registers + * to get the current speed/duplex if link exists. + **/ +-s32 igb_check_for_copper_link(struct e1000_hw *hw) ++s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val; + bool link; ++ ++ DEBUGFUNC("e1000_check_for_copper_link"); + + /* + * We only want to go out to the PHY registers to see if Auto-Neg +@@ -409,7 +514,7 @@ + * Change or Rx Sequence Error interrupt. + */ + if (!mac->get_link_status) { +- ret_val = 0; ++ ret_val = E1000_SUCCESS; + goto out; + } + +@@ -418,7 +523,7 @@ + * link. If so, then we want to get the current speed/duplex + * of the PHY. + */ +- ret_val = igb_phy_has_link(hw, 1, 0, &link); ++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + goto out; + +@@ -431,7 +536,7 @@ + * Check if there was DownShift, must be checked + * immediately after link-up + */ +- igb_check_downshift(hw); ++ e1000_check_downshift_generic(hw); + + /* + * If we are forcing speed/duplex, then we simply return since +@@ -447,7 +552,7 @@ + * of MAC speed/duplex configuration. So we only need to + * configure Collision Distance in the MAC. + */ +- igb_config_collision_dist(hw); ++ e1000_config_collision_dist_generic(hw); + + /* + * Configure Flow Control now that Auto-Neg has completed. +@@ -455,16 +560,198 @@ + * settings because we may have had to re-autoneg with a + * different link partner. + */ +- ret_val = igb_config_fc_after_link_up(hw); ++ ret_val = e1000_config_fc_after_link_up_generic(hw); + if (ret_val) +- hw_dbg("Error configuring flow control\n"); ++ DEBUGOUT("Error configuring flow control\n"); + + out: + return ret_val; + } + + /** +- * igb_setup_link - Setup flow control and link settings ++ * e1000_check_for_fiber_link_generic - Check for link (Fiber) ++ * @hw: pointer to the HW structure ++ * ++ * Checks for link up on the hardware. If link is not up and we have ++ * a signal, then we need to force link up. ++ **/ ++s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 rxcw; ++ u32 ctrl; ++ u32 status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_check_for_fiber_link_generic"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ status = E1000_READ_REG(hw, E1000_STATUS); ++ rxcw = E1000_READ_REG(hw, E1000_RXCW); ++ ++ /* ++ * If we don't have link (auto-negotiation failed or link partner ++ * cannot auto-negotiate), the cable is plugged in (we have signal), ++ * and our link partner is not trying to auto-negotiate with us (we ++ * are receiving idles or data), we need to force link up. We also ++ * need to give auto-negotiation time to complete, in case the cable ++ * was just plugged in. The autoneg_failed flag does this. ++ */ ++ /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ ++ if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && ++ (!(rxcw & E1000_RXCW_C))) { ++ if (mac->autoneg_failed == 0) { ++ mac->autoneg_failed = 1; ++ goto out; ++ } ++ DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); ++ ++ /* Disable auto-negotiation in the TXCW register */ ++ E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); ++ ++ /* Force link-up and also force full-duplex. */ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++ /* Configure Flow Control after forcing link up. */ ++ ret_val = e1000_config_fc_after_link_up_generic(hw); ++ if (ret_val) { ++ DEBUGOUT("Error configuring flow control\n"); ++ goto out; ++ } ++ } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { ++ /* ++ * If we are forcing link and we are receiving /C/ ordered ++ * sets, re-enable auto-negotiation in the TXCW register ++ * and disable forced link in the Device Control register ++ * in an attempt to auto-negotiate with our link partner. ++ */ ++ DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); ++ E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); ++ E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); ++ ++ mac->serdes_has_link = true; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_for_serdes_link_generic - Check for link (Serdes) ++ * @hw: pointer to the HW structure ++ * ++ * Checks for link up on the hardware. If link is not up and we have ++ * a signal, then we need to force link up. ++ **/ ++s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 rxcw; ++ u32 ctrl; ++ u32 status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_check_for_serdes_link_generic"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ status = E1000_READ_REG(hw, E1000_STATUS); ++ rxcw = E1000_READ_REG(hw, E1000_RXCW); ++ ++ /* ++ * If we don't have link (auto-negotiation failed or link partner ++ * cannot auto-negotiate), and our link partner is not trying to ++ * auto-negotiate with us (we are receiving idles or data), ++ * we need to force link up. We also need to give auto-negotiation ++ * time to complete. ++ */ ++ /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ ++ if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { ++ if (mac->autoneg_failed == 0) { ++ mac->autoneg_failed = 1; ++ goto out; ++ } ++ DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); ++ ++ /* Disable auto-negotiation in the TXCW register */ ++ E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); ++ ++ /* Force link-up and also force full-duplex. */ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++ /* Configure Flow Control after forcing link up. */ ++ ret_val = e1000_config_fc_after_link_up_generic(hw); ++ if (ret_val) { ++ DEBUGOUT("Error configuring flow control\n"); ++ goto out; ++ } ++ } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { ++ /* ++ * If we are forcing link and we are receiving /C/ ordered ++ * sets, re-enable auto-negotiation in the TXCW register ++ * and disable forced link in the Device Control register ++ * in an attempt to auto-negotiate with our link partner. ++ */ ++ DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); ++ E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); ++ E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); ++ ++ mac->serdes_has_link = true; ++ } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { ++ /* ++ * If we force link for non-auto-negotiation switch, check ++ * link status based on MAC synchronization for internal ++ * serdes media type. ++ */ ++ /* SYNCH bit and IV bit are sticky. */ ++ usec_delay(10); ++ rxcw = E1000_READ_REG(hw, E1000_RXCW); ++ if (rxcw & E1000_RXCW_SYNCH) { ++ if (!(rxcw & E1000_RXCW_IV)) { ++ mac->serdes_has_link = true; ++ DEBUGOUT("SERDES: Link up - forced.\n"); ++ } ++ } else { ++ mac->serdes_has_link = false; ++ DEBUGOUT("SERDES: Link down - force failed.\n"); ++ } ++ } ++ ++ if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { ++ status = E1000_READ_REG(hw, E1000_STATUS); ++ if (status & E1000_STATUS_LU) { ++ /* SYNCH bit and IV bit are sticky, so reread rxcw. */ ++ usec_delay(10); ++ rxcw = E1000_READ_REG(hw, E1000_RXCW); ++ if (rxcw & E1000_RXCW_SYNCH) { ++ if (!(rxcw & E1000_RXCW_IV)) { ++ mac->serdes_has_link = true; ++ DEBUGOUT("SERDES: Link up - autoneg " ++ "completed sucessfully.\n"); ++ } else { ++ mac->serdes_has_link = false; ++ DEBUGOUT("SERDES: Link down - invalid" ++ "codewords detected in autoneg.\n"); ++ } ++ } else { ++ mac->serdes_has_link = false; ++ DEBUGOUT("SERDES: Link down - no sync.\n"); ++ } ++ } else { ++ mac->serdes_has_link = false; ++ DEBUGOUT("SERDES: Link down - autoneg failed\n"); ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_link_generic - Setup flow control and link settings + * @hw: pointer to the HW structure + * + * Determines which flow control settings to use, then configures flow +@@ -473,29 +760,38 @@ + * should be established. Assumes the hardware has previously been reset + * and the transmitter and receiver are not enabled. + **/ +-s32 igb_setup_link(struct e1000_hw *hw) ++s32 e1000_setup_link_generic(struct e1000_hw *hw) + { +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_setup_link_generic"); + + /* + * In the case of the phy reset being blocked, we already have a link. + * We do not need to set it up again. + */ +- if (igb_check_reset_block(hw)) +- goto out; +- +- ret_val = igb_set_default_fc(hw); +- if (ret_val) +- goto out; ++ if (hw->phy.ops.check_reset_block) ++ if (hw->phy.ops.check_reset_block(hw)) ++ goto out; + + /* +- * We want to save off the original Flow Control configuration just +- * in case we get disconnected and then reconnected into a different +- * hub or switch with different Flow Control capabilities. ++ * If requested flow control is set to default, set flow control ++ * based on the EEPROM flow control settings. + */ +- hw->fc.original_type = hw->fc.type; ++ if (hw->fc.requested_mode == e1000_fc_default) { ++ ret_val = e1000_set_default_fc_generic(hw); ++ if (ret_val) ++ goto out; ++ } + +- hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.type); ++ /* ++ * Save off the requested flow control mode for use later. Depending ++ * on the link partner's capabilities, we may or may not use this mode. ++ */ ++ hw->fc.current_mode = hw->fc.requested_mode; ++ ++ DEBUGOUT1("After fix-ups FlowControl is now = %x\n", ++ hw->fc.current_mode); + + /* Call the necessary media_type subroutine to configure the link. */ + ret_val = hw->mac.ops.setup_physical_interface(hw); +@@ -508,52 +804,238 @@ + * control is disabled, because it does not hurt anything to + * initialize these registers. + */ +- hw_dbg("Initializing the Flow Control address, type and timer regs\n"); +- wr32(E1000_FCT, FLOW_CONTROL_TYPE); +- wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); +- wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); ++ DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); ++ E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); ++ E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); ++ E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); + +- wr32(E1000_FCTTV, hw->fc.pause_time); ++ E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); + +- ret_val = igb_set_fc_watermarks(hw); ++ ret_val = e1000_set_fc_watermarks_generic(hw); + + out: + return ret_val; + } + + /** +- * igb_config_collision_dist - Configure collision distance ++ * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes ++ * @hw: pointer to the HW structure ++ * ++ * Configures collision distance and flow control for fiber and serdes ++ * links. Upon successful setup, poll for link. ++ **/ ++s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ++ /* Take the link out of reset */ ++ ctrl &= ~E1000_CTRL_LRST; ++ ++ e1000_config_collision_dist_generic(hw); ++ ++ ret_val = e1000_commit_fc_settings_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ /* ++ * Since auto-negotiation is enabled, take the link out of reset (the ++ * link will be in reset, because we previously reset the chip). This ++ * will restart auto-negotiation. If auto-negotiation is successful ++ * then the link-up status bit will be set and the flow control enable ++ * bits (RFCE and TFCE) will be set according to their negotiated value. ++ */ ++ DEBUGOUT("Auto-negotiation enabled\n"); ++ ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ E1000_WRITE_FLUSH(hw); ++ msec_delay(1); ++ ++ /* ++ * For these adapters, the SW definable pin 1 is set when the optics ++ * detect a signal. If we have a signal, then poll for a "Link-Up" ++ * indication. ++ */ ++ if (hw->phy.media_type == e1000_media_type_internal_serdes || ++ (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { ++ ret_val = e1000_poll_fiber_serdes_link_generic(hw); ++ } else { ++ DEBUGOUT("No signal detected\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_config_collision_dist_generic - Configure collision distance + * @hw: pointer to the HW structure + * + * Configures the collision distance to the default value and is used + * during link setup. Currently no func pointer exists and all + * implementations are handled in the generic version of this function. + **/ +-void igb_config_collision_dist(struct e1000_hw *hw) ++void e1000_config_collision_dist_generic(struct e1000_hw *hw) + { + u32 tctl; + +- tctl = rd32(E1000_TCTL); ++ DEBUGFUNC("e1000_config_collision_dist_generic"); ++ ++ tctl = E1000_READ_REG(hw, E1000_TCTL); + + tctl &= ~E1000_TCTL_COLD; + tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; + +- wr32(E1000_TCTL, tctl); +- wrfl(); ++ E1000_WRITE_REG(hw, E1000_TCTL, tctl); ++ E1000_WRITE_FLUSH(hw); + } + + /** +- * igb_set_fc_watermarks - Set flow control high/low watermarks ++ * e1000_poll_fiber_serdes_link_generic - Poll for link up ++ * @hw: pointer to the HW structure ++ * ++ * Polls for link up by reading the status register, if link fails to come ++ * up with auto-negotiation, then the link is forced if a signal is detected. ++ **/ ++static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 i, status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); ++ ++ /* ++ * If we have a signal (the cable is plugged in, or assumed true for ++ * serdes media) then poll for a "Link-Up" indication in the Device ++ * Status Register. Time-out if a link isn't seen in 500 milliseconds ++ * seconds (Auto-negotiation should complete in less than 500 ++ * milliseconds even if the other end is doing it in SW). ++ */ ++ for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { ++ msec_delay(10); ++ status = E1000_READ_REG(hw, E1000_STATUS); ++ if (status & E1000_STATUS_LU) ++ break; ++ } ++ if (i == FIBER_LINK_UP_LIMIT) { ++ DEBUGOUT("Never got a valid link from auto-neg!!!\n"); ++ mac->autoneg_failed = 1; ++ /* ++ * AutoNeg failed to achieve a link, so we'll call ++ * mac->check_for_link. This routine will force the ++ * link up if we detect a signal. This will allow us to ++ * communicate with non-autonegotiating link partners. ++ */ ++ ret_val = hw->mac.ops.check_for_link(hw); ++ if (ret_val) { ++ DEBUGOUT("Error while checking for link\n"); ++ goto out; ++ } ++ mac->autoneg_failed = 0; ++ } else { ++ mac->autoneg_failed = 0; ++ DEBUGOUT("Valid Link Found\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_commit_fc_settings_generic - Configure flow control ++ * @hw: pointer to the HW structure ++ * ++ * Write the flow control settings to the Transmit Config Word Register (TXCW) ++ * base on the flow control settings in e1000_mac_info. ++ **/ ++static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 txcw; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_commit_fc_settings_generic"); ++ ++ /* ++ * Check for a software override of the flow control settings, and ++ * setup the device accordingly. If auto-negotiation is enabled, then ++ * software will have to set the "PAUSE" bits to the correct value in ++ * the Transmit Config Word Register (TXCW) and re-start auto- ++ * negotiation. However, if auto-negotiation is disabled, then ++ * software will have to manually configure the two flow control enable ++ * bits in the CTRL register. ++ * ++ * The possible values of the "fc" parameter are: ++ * 0: Flow control is completely disabled ++ * 1: Rx flow control is enabled (we can receive pause frames, ++ * but not send pause frames). ++ * 2: Tx flow control is enabled (we can send pause frames but we ++ * do not support receiving pause frames). ++ * 3: Both Rx and Tx flow control (symmetric) are enabled. ++ */ ++ switch (hw->fc.current_mode) { ++ case e1000_fc_none: ++ /* Flow control completely disabled by a software over-ride. */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); ++ break; ++ case e1000_fc_rx_pause: ++ /* ++ * Rx Flow control is enabled and Tx Flow control is disabled ++ * by a software over-ride. Since there really isn't a way to ++ * advertise that we are capable of Rx Pause ONLY, we will ++ * advertise that we support both symmetric and asymmetric RX ++ * PAUSE. Later, we will disable the adapter's ability to send ++ * PAUSE frames. ++ */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); ++ break; ++ case e1000_fc_tx_pause: ++ /* ++ * Tx Flow control is enabled, and Rx Flow control is disabled, ++ * by a software over-ride. ++ */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); ++ break; ++ case e1000_fc_full: ++ /* ++ * Flow control (both Rx and Tx) is enabled by a software ++ * over-ride. ++ */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); ++ break; ++ default: ++ DEBUGOUT("Flow control param set incorrectly\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ break; ++ } ++ ++ E1000_WRITE_REG(hw, E1000_TXCW, txcw); ++ mac->txcw = txcw; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks + * @hw: pointer to the HW structure + * + * Sets the flow control high/low threshold (watermark) registers. If + * flow control XON frame transmission is enabled, then set XON frame +- * tansmission as well. ++ * transmission as well. + **/ +-static s32 igb_set_fc_watermarks(struct e1000_hw *hw) ++s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) + { +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + u32 fcrtl = 0, fcrth = 0; ++ ++ DEBUGFUNC("e1000_set_fc_watermarks_generic"); + + /* + * Set the flow control receive threshold registers. Normally, +@@ -562,7 +1044,7 @@ + * ability to transmit pause frames is not enabled, then these + * registers will be set to 0. + */ +- if (hw->fc.type & e1000_fc_tx_pause) { ++ if (hw->fc.current_mode & e1000_fc_tx_pause) { + /* + * We need to set up the Receive Threshold high and low water + * marks as well as (optionally) enabling the transmission of +@@ -574,23 +1056,25 @@ + + fcrth = hw->fc.high_water; + } +- wr32(E1000_FCRTL, fcrtl); +- wr32(E1000_FCRTH, fcrth); ++ E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); ++ E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); + + return ret_val; + } + + /** +- * igb_set_default_fc - Set flow control default values ++ * e1000_set_default_fc_generic - Set flow control default values + * @hw: pointer to the HW structure + * + * Read the EEPROM for the default values for flow control and store the + * values. + **/ +-static s32 igb_set_default_fc(struct e1000_hw *hw) ++static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) + { +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + u16 nvm_data; ++ ++ DEBUGFUNC("e1000_set_default_fc_generic"); + + /* + * Read and store word 0x0F of the EEPROM. This word contains bits +@@ -601,28 +1085,27 @@ + * control setting, then the variable hw->fc will + * be initialized based on a value in the EEPROM. + */ +- ret_val = hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, +- &nvm_data); ++ ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); + + if (ret_val) { +- hw_dbg("NVM Read Error\n"); ++ DEBUGOUT("NVM Read Error\n"); + goto out; + } + + if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) +- hw->fc.type = e1000_fc_none; ++ hw->fc.requested_mode = e1000_fc_none; + else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == + NVM_WORD0F_ASM_DIR) +- hw->fc.type = e1000_fc_tx_pause; ++ hw->fc.requested_mode = e1000_fc_tx_pause; + else +- hw->fc.type = e1000_fc_full; ++ hw->fc.requested_mode = e1000_fc_full; + + out: + return ret_val; + } + + /** +- * igb_force_mac_fc - Force the MAC's flow control settings ++ * e1000_force_mac_fc_generic - Force the MAC's flow control settings + * @hw: pointer to the HW structure + * + * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the +@@ -631,12 +1114,14 @@ + * autonegotiation is managed by the PHY rather than the MAC. Software must + * also configure these bits when link is forced on a fiber connection. + **/ +-s32 igb_force_mac_fc(struct e1000_hw *hw) ++s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) + { + u32 ctrl; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + +- ctrl = rd32(E1000_CTRL); ++ DEBUGFUNC("e1000_force_mac_fc_generic"); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); + + /* + * Because we didn't get link via the internal auto-negotiation +@@ -645,7 +1130,7 @@ + * receive flow control. + * + * The "Case" statement below enables/disable flow control +- * according to the "hw->fc.type" parameter. ++ * according to the "hw->fc.current_mode" parameter. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled +@@ -653,12 +1138,12 @@ + * frames but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames + * frames but we do not receive pause frames). +- * 3: Both Rx and TX flow control (symmetric) is enabled. ++ * 3: Both Rx and Tx flow control (symmetric) is enabled. + * other: No other values should be possible at this point. + */ +- hw_dbg("hw->fc.type = %u\n", hw->fc.type); ++ DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); + +- switch (hw->fc.type) { ++ switch (hw->fc.current_mode) { + case e1000_fc_none: + ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); + break; +@@ -674,19 +1159,19 @@ + ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); + break; + default: +- hw_dbg("Flow control param set incorrectly\n"); ++ DEBUGOUT("Flow control param set incorrectly\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + +- wr32(E1000_CTRL, ctrl); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + out: + return ret_val; + } + + /** +- * igb_config_fc_after_link_up - Configures flow control after link ++ * e1000_config_fc_after_link_up_generic - Configures flow control after link + * @hw: pointer to the HW structure + * + * Checks the status of auto-negotiation after link up to ensure that the +@@ -695,12 +1180,14 @@ + * and did not fail, then we configure flow control based on our link + * partner. + **/ +-s32 igb_config_fc_after_link_up(struct e1000_hw *hw) ++s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; + u16 speed, duplex; ++ ++ DEBUGFUNC("e1000_config_fc_after_link_up_generic"); + + /* + * Check for the case where we have fiber media and auto-neg failed +@@ -710,14 +1197,14 @@ + if (mac->autoneg_failed) { + if (hw->phy.media_type == e1000_media_type_fiber || + hw->phy.media_type == e1000_media_type_internal_serdes) +- ret_val = igb_force_mac_fc(hw); ++ ret_val = e1000_force_mac_fc_generic(hw); + } else { + if (hw->phy.media_type == e1000_media_type_copper) +- ret_val = igb_force_mac_fc(hw); ++ ret_val = e1000_force_mac_fc_generic(hw); + } + + if (ret_val) { +- hw_dbg("Error forcing flow control settings\n"); ++ DEBUGOUT("Error forcing flow control settings\n"); + goto out; + } + +@@ -733,18 +1220,16 @@ + * has completed. We read this twice because this reg has + * some "sticky" (latched) bits. + */ +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, +- &mii_status_reg); ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + goto out; +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, +- &mii_status_reg); ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + goto out; + + if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { +- hw_dbg("Copper PHY and Auto Neg " +- "has not completed.\n"); ++ DEBUGOUT("Copper PHY and Auto Neg " ++ "has not completed.\n"); + goto out; + } + +@@ -755,12 +1240,12 @@ + * Page Ability Register (Address 5) to determine how + * flow control was negotiated. + */ +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_AUTONEG_ADV, +- &mii_nway_adv_reg); ++ ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, ++ &mii_nway_adv_reg); + if (ret_val) + goto out; +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_LP_ABILITY, +- &mii_nway_lp_ability_reg); ++ ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, ++ &mii_nway_lp_ability_reg); + if (ret_val) + goto out; + +@@ -801,19 +1286,19 @@ + if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { + /* +- * Now we need to check if the user selected RX ONLY ++ * Now we need to check if the user selected Rx ONLY + * of pause frames. In this case, we had to advertise + * FULL flow control because we could not advertise RX + * ONLY. Hence, we must now check to see if we need to + * turn OFF the TRANSMISSION of PAUSE frames. + */ +- if (hw->fc.original_type == e1000_fc_full) { +- hw->fc.type = e1000_fc_full; +- hw_dbg("Flow Control = FULL.\r\n"); ++ if (hw->fc.requested_mode == e1000_fc_full) { ++ hw->fc.current_mode = e1000_fc_full; ++ DEBUGOUT("Flow Control = FULL.\r\n"); + } else { +- hw->fc.type = e1000_fc_rx_pause; +- hw_dbg("Flow Control = " +- "RX PAUSE frames only.\r\n"); ++ hw->fc.current_mode = e1000_fc_rx_pause; ++ DEBUGOUT("Flow Control = " ++ "RX PAUSE frames only.\r\n"); + } + } + /* +@@ -825,11 +1310,11 @@ + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + */ + else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && +- (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && +- (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && +- (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { +- hw->fc.type = e1000_fc_tx_pause; +- hw_dbg("Flow Control = TX PAUSE frames only.\r\n"); ++ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { ++ hw->fc.current_mode = e1000_fc_tx_pause; ++ DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); + } + /* + * For transmitting PAUSE frames ONLY. +@@ -840,41 +1325,18 @@ + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + */ + else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && +- (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && +- !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && +- (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { +- hw->fc.type = e1000_fc_rx_pause; +- hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); +- } +- /* +- * Per the IEEE spec, at this point flow control should be +- * disabled. However, we want to consider that we could +- * be connected to a legacy switch that doesn't advertise +- * desired flow control, but can be forced on the link +- * partner. So if we advertised no flow control, that is +- * what we will resolve to. If we advertised some kind of +- * receive capability (Rx Pause Only or Full Flow Control) +- * and the link partner advertised none, we will configure +- * ourselves to enable Rx Flow Control only. We can do +- * this safely for two reasons: If the link partner really +- * didn't want flow control enabled, and we enable Rx, no +- * harm done since we won't be receiving any PAUSE frames +- * anyway. If the intent on the link partner was to have +- * flow control enabled, then by us enabling RX only, we +- * can at least receive pause frames and process them. +- * This is a good idea because in most cases, since we are +- * predominantly a server NIC, more times than not we will +- * be asked to delay transmission of packets than asking +- * our link partner to pause transmission of frames. +- */ +- else if ((hw->fc.original_type == e1000_fc_none || +- hw->fc.original_type == e1000_fc_tx_pause) || +- hw->fc.strict_ieee) { +- hw->fc.type = e1000_fc_none; +- hw_dbg("Flow Control = NONE.\r\n"); ++ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && ++ !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { ++ hw->fc.current_mode = e1000_fc_rx_pause; ++ DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); + } else { +- hw->fc.type = e1000_fc_rx_pause; +- hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); ++ /* ++ * Per the IEEE spec, at this point flow control ++ * should be disabled. ++ */ ++ hw->fc.current_mode = e1000_fc_none; ++ DEBUGOUT("Flow Control = NONE.\r\n"); + } + + /* +@@ -882,22 +1344,22 @@ + * negotiated to HALF DUPLEX, flow control should not be + * enabled per IEEE 802.3 spec. + */ +- ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); ++ ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); + if (ret_val) { +- hw_dbg("Error getting link speed and duplex\n"); ++ DEBUGOUT("Error getting link speed and duplex\n"); + goto out; + } + + if (duplex == HALF_DUPLEX) +- hw->fc.type = e1000_fc_none; ++ hw->fc.current_mode = e1000_fc_none; + + /* + * Now we call a subroutine to actually force the MAC + * controller to use the correct flow control settings. + */ +- ret_val = igb_force_mac_fc(hw); ++ ret_val = e1000_force_mac_fc_generic(hw); + if (ret_val) { +- hw_dbg("Error forcing flow control settings\n"); ++ DEBUGOUT("Error forcing flow control settings\n"); + goto out; + } + } +@@ -907,7 +1369,7 @@ + } + + /** +- * igb_get_speed_and_duplex_copper - Retreive current speed/duplex ++ * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex + * @hw: pointer to the HW structure + * @speed: stores the current speed + * @duplex: stores the current duplex +@@ -915,79 +1377,103 @@ + * Read the status register for the current speed/duplex and store the current + * speed and duplex for copper connections. + **/ +-s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, +- u16 *duplex) ++s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex) + { + u32 status; + +- status = rd32(E1000_STATUS); ++ DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); ++ ++ status = E1000_READ_REG(hw, E1000_STATUS); + if (status & E1000_STATUS_SPEED_1000) { + *speed = SPEED_1000; +- hw_dbg("1000 Mbs, "); ++ DEBUGOUT("1000 Mbs, "); + } else if (status & E1000_STATUS_SPEED_100) { + *speed = SPEED_100; +- hw_dbg("100 Mbs, "); ++ DEBUGOUT("100 Mbs, "); + } else { + *speed = SPEED_10; +- hw_dbg("10 Mbs, "); ++ DEBUGOUT("10 Mbs, "); + } + + if (status & E1000_STATUS_FD) { + *duplex = FULL_DUPLEX; +- hw_dbg("Full Duplex\n"); ++ DEBUGOUT("Full Duplex\n"); + } else { + *duplex = HALF_DUPLEX; +- hw_dbg("Half Duplex\n"); ++ DEBUGOUT("Half Duplex\n"); + } + +- return 0; ++ return E1000_SUCCESS; + } + + /** +- * igb_get_hw_semaphore - Acquire hardware semaphore ++ * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex ++ * @hw: pointer to the HW structure ++ * @speed: stores the current speed ++ * @duplex: stores the current duplex ++ * ++ * Sets the speed and duplex to gigabit full duplex (the only possible option) ++ * for fiber/serdes links. ++ **/ ++s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, ++ u16 *speed, u16 *duplex) ++{ ++ DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); ++ ++ *speed = SPEED_1000; ++ *duplex = FULL_DUPLEX; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_get_hw_semaphore_generic - Acquire hardware semaphore + * @hw: pointer to the HW structure + * + * Acquire the HW semaphore to access the PHY or NVM + **/ +-s32 igb_get_hw_semaphore(struct e1000_hw *hw) ++s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) + { + u32 swsm; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + s32 timeout = hw->nvm.word_size + 1; + s32 i = 0; + ++ DEBUGFUNC("e1000_get_hw_semaphore_generic"); ++ + /* Get the SW semaphore */ + while (i < timeout) { +- swsm = rd32(E1000_SWSM); ++ swsm = E1000_READ_REG(hw, E1000_SWSM); + if (!(swsm & E1000_SWSM_SMBI)) + break; + +- udelay(50); ++ usec_delay(50); + i++; + } + + if (i == timeout) { +- hw_dbg("Driver can't access device - SMBI bit is set.\n"); ++ DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + + /* Get the FW semaphore. */ + for (i = 0; i < timeout; i++) { +- swsm = rd32(E1000_SWSM); +- wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI); ++ swsm = E1000_READ_REG(hw, E1000_SWSM); ++ E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); + + /* Semaphore acquired if bit latched */ +- if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI) ++ if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) + break; + +- udelay(50); ++ usec_delay(50); + } + + if (i == timeout) { + /* Release semaphores */ +- igb_put_hw_semaphore(hw); +- hw_dbg("Driver can't access the NVM\n"); ++ e1000_put_hw_semaphore_generic(hw); ++ DEBUGOUT("Driver can't access the NVM\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } +@@ -997,43 +1483,46 @@ + } + + /** +- * igb_put_hw_semaphore - Release hardware semaphore ++ * e1000_put_hw_semaphore_generic - Release hardware semaphore + * @hw: pointer to the HW structure + * + * Release hardware semaphore used to access the PHY or NVM + **/ +-void igb_put_hw_semaphore(struct e1000_hw *hw) ++void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) + { + u32 swsm; + +- swsm = rd32(E1000_SWSM); ++ DEBUGFUNC("e1000_put_hw_semaphore_generic"); ++ ++ swsm = E1000_READ_REG(hw, E1000_SWSM); + + swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); + +- wr32(E1000_SWSM, swsm); ++ E1000_WRITE_REG(hw, E1000_SWSM, swsm); + } + + /** +- * igb_get_auto_rd_done - Check for auto read completion ++ * e1000_get_auto_rd_done_generic - Check for auto read completion + * @hw: pointer to the HW structure + * + * Check EEPROM for Auto Read done bit. + **/ +-s32 igb_get_auto_rd_done(struct e1000_hw *hw) ++s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) + { + s32 i = 0; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + ++ DEBUGFUNC("e1000_get_auto_rd_done_generic"); + + while (i < AUTO_READ_DONE_TIMEOUT) { +- if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD) ++ if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) + break; +- msleep(1); ++ msec_delay(1); + i++; + } + + if (i == AUTO_READ_DONE_TIMEOUT) { +- hw_dbg("Auto read by HW from NVM has not completed.\n"); ++ DEBUGOUT("Auto read by HW from NVM has not completed.\n"); + ret_val = -E1000_ERR_RESET; + goto out; + } +@@ -1043,20 +1532,22 @@ + } + + /** +- * igb_valid_led_default - Verify a valid default LED config ++ * e1000_valid_led_default_generic - Verify a valid default LED config + * @hw: pointer to the HW structure + * @data: pointer to the NVM (EEPROM) + * + * Read the EEPROM for the current default LED configuration. If the + * LED configuration is not valid, set to a valid LED configuration. + **/ +-static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data) ++s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) + { + s32 ret_val; + +- ret_val = hw->nvm.ops.read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); ++ DEBUGFUNC("e1000_valid_led_default_generic"); ++ ++ ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); + if (ret_val) { +- hw_dbg("NVM Read Error\n"); ++ DEBUGOUT("NVM Read Error\n"); + goto out; + } + +@@ -1068,11 +1559,11 @@ + } + + /** +- * igb_id_led_init - ++ * e1000_id_led_init_generic - + * @hw: pointer to the HW structure + * + **/ +-s32 igb_id_led_init(struct e1000_hw *hw) ++s32 e1000_id_led_init_generic(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val; +@@ -1082,11 +1573,13 @@ + u16 data, i, temp; + const u16 led_mask = 0x0F; + +- ret_val = igb_valid_led_default(hw, &data); ++ DEBUGFUNC("e1000_id_led_init_generic"); ++ ++ ret_val = hw->nvm.ops.valid_led_default(hw, &data); + if (ret_val) + goto out; + +- mac->ledctl_default = rd32(E1000_LEDCTL); ++ mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); + mac->ledctl_mode1 = mac->ledctl_default; + mac->ledctl_mode2 = mac->ledctl_default; + +@@ -1133,28 +1626,78 @@ + } + + /** +- * igb_cleanup_led - Set LED config to default operation ++ * e1000_setup_led_generic - Configures SW controllable LED ++ * @hw: pointer to the HW structure ++ * ++ * This prepares the SW controllable LED for use and saves the current state ++ * of the LED so it can be later restored. ++ **/ ++s32 e1000_setup_led_generic(struct e1000_hw *hw) ++{ ++ u32 ledctl; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_setup_led_generic"); ++ ++ if (hw->mac.ops.setup_led != e1000_setup_led_generic) { ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ if (hw->phy.media_type == e1000_media_type_fiber) { ++ ledctl = E1000_READ_REG(hw, E1000_LEDCTL); ++ hw->mac.ledctl_default = ledctl; ++ /* Turn off LED0 */ ++ ledctl &= ~(E1000_LEDCTL_LED0_IVRT | ++ E1000_LEDCTL_LED0_BLINK | ++ E1000_LEDCTL_LED0_MODE_MASK); ++ ledctl |= (E1000_LEDCTL_MODE_LED_OFF << ++ E1000_LEDCTL_LED0_MODE_SHIFT); ++ E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); ++ } else if (hw->phy.media_type == e1000_media_type_copper) { ++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_cleanup_led_generic - Set LED config to default operation + * @hw: pointer to the HW structure + * + * Remove the current LED configuration and set the LED configuration + * to the default value, saved from the EEPROM. + **/ +-s32 igb_cleanup_led(struct e1000_hw *hw) ++s32 e1000_cleanup_led_generic(struct e1000_hw *hw) + { +- wr32(E1000_LEDCTL, hw->mac.ledctl_default); +- return 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_cleanup_led_generic"); ++ ++ if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) { ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); ++ ++out: ++ return ret_val; + } + + /** +- * igb_blink_led - Blink LED ++ * e1000_blink_led_generic - Blink LED + * @hw: pointer to the HW structure + * +- * Blink the led's which are set to be on. ++ * Blink the LEDs which are set to be on. + **/ +-s32 igb_blink_led(struct e1000_hw *hw) ++s32 e1000_blink_led_generic(struct e1000_hw *hw) + { + u32 ledctl_blink = 0; + u32 i; ++ ++ DEBUGFUNC("e1000_blink_led_generic"); + + if (hw->phy.media_type == e1000_media_type_fiber) { + /* always blink LED0 for PCI-E fiber */ +@@ -1170,75 +1713,134 @@ + if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == + E1000_LEDCTL_MODE_LED_ON) + ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << +- (i * 8)); ++ (i * 8)); + } + +- wr32(E1000_LEDCTL, ledctl_blink); ++ E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); + +- return 0; ++ return E1000_SUCCESS; + } + + /** +- * igb_led_off - Turn LED off ++ * e1000_led_on_generic - Turn LED on + * @hw: pointer to the HW structure + * +- * Turn LED off. ++ * Turn LED on. + **/ +-s32 igb_led_off(struct e1000_hw *hw) ++s32 e1000_led_on_generic(struct e1000_hw *hw) + { + u32 ctrl; + ++ DEBUGFUNC("e1000_led_on_generic"); ++ + switch (hw->phy.media_type) { + case e1000_media_type_fiber: +- ctrl = rd32(E1000_CTRL); +- ctrl |= E1000_CTRL_SWDPIN0; ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl &= ~E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; +- wr32(E1000_CTRL, ctrl); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + break; + case e1000_media_type_copper: +- wr32(E1000_LEDCTL, hw->mac.ledctl_mode1); ++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); + break; + default: + break; + } + +- return 0; ++ return E1000_SUCCESS; + } + + /** +- * igb_disable_pcie_master - Disables PCI-express master access ++ * e1000_led_off_generic - Turn LED off + * @hw: pointer to the HW structure + * +- * Returns 0 (0) if successful, else returns -10 +- * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued ++ * Turn LED off. ++ **/ ++s32 e1000_led_off_generic(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ ++ DEBUGFUNC("e1000_led_off_generic"); ++ ++ switch (hw->phy.media_type) { ++ case e1000_media_type_fiber: ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ ctrl |= E1000_CTRL_SWDPIN0; ++ ctrl |= E1000_CTRL_SWDPIO0; ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ break; ++ case e1000_media_type_copper: ++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); ++ break; ++ default: ++ break; ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities ++ * @hw: pointer to the HW structure ++ * @no_snoop: bitmap of snoop events ++ * ++ * Set the PCI-express register to snoop for events enabled in 'no_snoop'. ++ **/ ++void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) ++{ ++ u32 gcr; ++ ++ DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); ++ ++ if (hw->bus.type != e1000_bus_type_pci_express) ++ goto out; ++ ++ if (no_snoop) { ++ gcr = E1000_READ_REG(hw, E1000_GCR); ++ gcr &= ~(PCIE_NO_SNOOP_ALL); ++ gcr |= no_snoop; ++ E1000_WRITE_REG(hw, E1000_GCR, gcr); ++ } ++out: ++ return; ++} ++ ++/** ++ * e1000_disable_pcie_master_generic - Disables PCI-express master access ++ * @hw: pointer to the HW structure ++ * ++ * Returns 0 (E1000_SUCCESS) if successful, else returns -10 ++ * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused + * the master requests to be disabled. + * + * Disables PCI-Express master access and verifies there are no pending + * requests. + **/ +-s32 igb_disable_pcie_master(struct e1000_hw *hw) ++s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) + { + u32 ctrl; + s32 timeout = MASTER_DISABLE_TIMEOUT; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_disable_pcie_master_generic"); + + if (hw->bus.type != e1000_bus_type_pci_express) + goto out; + +- ctrl = rd32(E1000_CTRL); ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; +- wr32(E1000_CTRL, ctrl); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + while (timeout) { +- if (!(rd32(E1000_STATUS) & ++ if (!(E1000_READ_REG(hw, E1000_STATUS) & + E1000_STATUS_GIO_MASTER_ENABLE)) + break; +- udelay(100); ++ usec_delay(100); + timeout--; + } + + if (!timeout) { +- hw_dbg("Master requests are pending.\n"); ++ DEBUGOUT("Master requests are pending.\n"); + ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; + goto out; + } +@@ -1248,47 +1850,49 @@ + } + + /** +- * igb_reset_adaptive - Reset Adaptive Interframe Spacing ++ * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing + * @hw: pointer to the HW structure + * + * Reset the Adaptive Interframe Spacing throttle to default values. + **/ +-void igb_reset_adaptive(struct e1000_hw *hw) ++void e1000_reset_adaptive_generic(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + ++ DEBUGFUNC("e1000_reset_adaptive_generic"); ++ + if (!mac->adaptive_ifs) { +- hw_dbg("Not in Adaptive IFS mode!\n"); ++ DEBUGOUT("Not in Adaptive IFS mode!\n"); + goto out; + } + +- if (!mac->ifs_params_forced) { +- mac->current_ifs_val = 0; +- mac->ifs_min_val = IFS_MIN; +- mac->ifs_max_val = IFS_MAX; +- mac->ifs_step_size = IFS_STEP; +- mac->ifs_ratio = IFS_RATIO; +- } ++ mac->current_ifs_val = 0; ++ mac->ifs_min_val = IFS_MIN; ++ mac->ifs_max_val = IFS_MAX; ++ mac->ifs_step_size = IFS_STEP; ++ mac->ifs_ratio = IFS_RATIO; + + mac->in_ifs_mode = false; +- wr32(E1000_AIT, 0); ++ E1000_WRITE_REG(hw, E1000_AIT, 0); + out: + return; + } + + /** +- * igb_update_adaptive - Update Adaptive Interframe Spacing ++ * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing + * @hw: pointer to the HW structure + * + * Update the Adaptive Interframe Spacing Throttle value based on the + * time between transmitted packets and time between collisions. + **/ +-void igb_update_adaptive(struct e1000_hw *hw) ++void e1000_update_adaptive_generic(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + ++ DEBUGFUNC("e1000_update_adaptive_generic"); ++ + if (!mac->adaptive_ifs) { +- hw_dbg("Not in Adaptive IFS mode!\n"); ++ DEBUGOUT("Not in Adaptive IFS mode!\n"); + goto out; + } + +@@ -1301,8 +1905,7 @@ + else + mac->current_ifs_val += + mac->ifs_step_size; +- wr32(E1000_AIT, +- mac->current_ifs_val); ++ E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); + } + } + } else { +@@ -1310,7 +1913,7 @@ + (mac->tx_packet_delta <= MIN_NUM_XMITS)) { + mac->current_ifs_val = 0; + mac->in_ifs_mode = false; +- wr32(E1000_AIT, 0); ++ E1000_WRITE_REG(hw, E1000_AIT, 0); + } + } + out: +@@ -1318,18 +1921,20 @@ + } + + /** +- * igb_validate_mdi_setting - Verify MDI/MDIx settings ++ * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings + * @hw: pointer to the HW structure + * +- * Verify that when not using auto-negotitation that MDI/MDIx is correctly ++ * Verify that when not using auto-negotiation that MDI/MDIx is correctly + * set, which is forced to MDI mode only. + **/ +-s32 igb_validate_mdi_setting(struct e1000_hw *hw) ++static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) + { +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_validate_mdi_setting_generic"); + + if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { +- hw_dbg("Invalid MDI setting detected\n"); ++ DEBUGOUT("Invalid MDI setting detected\n"); + hw->phy.mdix = 1; + ret_val = -E1000_ERR_CONFIG; + goto out; +@@ -1340,7 +1945,7 @@ + } + + /** +- * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register ++ * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register + * @hw: pointer to the HW structure + * @reg: 32bit register offset such as E1000_SCTL + * @offset: register offset to write to +@@ -1350,25 +1955,27 @@ + * and they all have the format address << 8 | data and bit 31 is polled for + * completion. + **/ +-s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, +- u32 offset, u8 data) ++s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, ++ u32 offset, u8 data) + { + u32 i, regvalue = 0; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); + + /* Set up the address and data */ + regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); +- wr32(reg, regvalue); ++ E1000_WRITE_REG(hw, reg, regvalue); + + /* Poll the ready bit to see if the MDI read completed */ + for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { +- udelay(5); +- regvalue = rd32(reg); ++ usec_delay(5); ++ regvalue = E1000_READ_REG(hw, reg); + if (regvalue & E1000_GEN_CTL_READY) + break; + } + if (!(regvalue & E1000_GEN_CTL_READY)) { +- hw_dbg("Reg %08x did not indicate ready\n", reg); ++ DEBUGOUT1("Reg %08x did not indicate ready\n", reg); + ret_val = -E1000_ERR_PHY; + goto out; + } +@@ -1376,46 +1983,3 @@ + out: + return ret_val; + } +- +-/** +- * igb_enable_mng_pass_thru - Enable processing of ARP's +- * @hw: pointer to the HW structure +- * +- * Verifies the hardware needs to allow ARPs to be processed by the host. +- **/ +-bool igb_enable_mng_pass_thru(struct e1000_hw *hw) +-{ +- u32 manc; +- u32 fwsm, factps; +- bool ret_val = false; +- +- if (!hw->mac.asf_firmware_present) +- goto out; +- +- manc = rd32(E1000_MANC); +- +- if (!(manc & E1000_MANC_RCV_TCO_EN) || +- !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) +- goto out; +- +- if (hw->mac.arc_subsystem_valid) { +- fwsm = rd32(E1000_FWSM); +- factps = rd32(E1000_FACTPS); +- +- if (!(factps & E1000_FACTPS_MNGCG) && +- ((fwsm & E1000_FWSM_MODE_MASK) == +- (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { +- ret_val = true; +- goto out; +- } +- } else { +- if ((manc & E1000_MANC_SMBUS_EN) && +- !(manc & E1000_MANC_ASF_EN)) { +- ret_val = true; +- goto out; +- } +- } +- +-out: +- return ret_val; +-} +diff -r 4f0f8bc35440 drivers/net/igb/e1000_mac.h +--- a/drivers/net/igb/e1000_mac.h Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/e1000_mac.h Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -28,69 +28,53 @@ + #ifndef _E1000_MAC_H_ + #define _E1000_MAC_H_ + +-#include "e1000_hw.h" +- +-#include "e1000_phy.h" +-#include "e1000_nvm.h" +-#include "e1000_defines.h" +- + /* + * Functions that should not be called directly from drivers but can be used + * by other files in this 'shared code' + */ +-s32 igb_blink_led(struct e1000_hw *hw); +-s32 igb_check_for_copper_link(struct e1000_hw *hw); +-s32 igb_cleanup_led(struct e1000_hw *hw); +-s32 igb_config_fc_after_link_up(struct e1000_hw *hw); +-s32 igb_disable_pcie_master(struct e1000_hw *hw); +-s32 igb_force_mac_fc(struct e1000_hw *hw); +-s32 igb_get_auto_rd_done(struct e1000_hw *hw); +-s32 igb_get_bus_info_pcie(struct e1000_hw *hw); +-s32 igb_get_hw_semaphore(struct e1000_hw *hw); +-s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, +- u16 *duplex); +-s32 igb_id_led_init(struct e1000_hw *hw); +-s32 igb_led_off(struct e1000_hw *hw); +-s32 igb_setup_link(struct e1000_hw *hw); +-s32 igb_validate_mdi_setting(struct e1000_hw *hw); +-s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, +- u32 offset, u8 data); ++void e1000_init_mac_ops_generic(struct e1000_hw *hw); ++s32 e1000_blink_led_generic(struct e1000_hw *hw); ++s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw); ++s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw); ++s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw); ++s32 e1000_cleanup_led_generic(struct e1000_hw *hw); ++s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw); ++s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw); ++s32 e1000_force_mac_fc_generic(struct e1000_hw *hw); ++s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw); ++s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw); ++void e1000_set_lan_id_single_port(struct e1000_hw *hw); ++s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw); ++s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex); ++s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, ++ u16 *speed, u16 *duplex); ++s32 e1000_id_led_init_generic(struct e1000_hw *hw); ++s32 e1000_led_on_generic(struct e1000_hw *hw); ++s32 e1000_led_off_generic(struct e1000_hw *hw); ++void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, ++ u8 *mc_addr_list, u32 mc_addr_count); ++s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw); ++s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw); ++s32 e1000_setup_led_generic(struct e1000_hw *hw); ++s32 e1000_setup_link_generic(struct e1000_hw *hw); ++s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, ++ u32 offset, u8 data); + +-void igb_clear_hw_cntrs_base(struct e1000_hw *hw); +-void igb_clear_vfta(struct e1000_hw *hw); +-void igb_config_collision_dist(struct e1000_hw *hw); +-void igb_mta_set(struct e1000_hw *hw, u32 hash_value); +-void igb_put_hw_semaphore(struct e1000_hw *hw); +-void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); +-s32 igb_check_alt_mac_addr(struct e1000_hw *hw); +-void igb_remove_device(struct e1000_hw *hw); +-void igb_reset_adaptive(struct e1000_hw *hw); +-void igb_update_adaptive(struct e1000_hw *hw); +-void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value); ++u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr); + +-bool igb_enable_mng_pass_thru(struct e1000_hw *hw); +- +-enum e1000_mng_mode { +- e1000_mng_mode_none = 0, +- e1000_mng_mode_asf, +- e1000_mng_mode_pt, +- e1000_mng_mode_ipmi, +- e1000_mng_mode_host_if_only +-}; +- +-#define E1000_FACTPS_MNGCG 0x20000000 +- +-#define E1000_FWSM_MODE_MASK 0xE +-#define E1000_FWSM_MODE_SHIFT 1 +- +-#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 +-#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 +- +-#define E1000_HICR_EN 0x01 /* Enable bit - RO */ +-/* Driver sets this bit when done to put command in RAM */ +-#define E1000_HICR_C 0x02 +- +-extern void e1000_init_function_pointers_82575(struct e1000_hw *hw); +-extern u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr); ++void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw); ++void e1000_clear_vfta_generic(struct e1000_hw *hw); ++void e1000_config_collision_dist_generic(struct e1000_hw *hw); ++void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count); ++void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value); ++void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw); ++void e1000_put_hw_semaphore_generic(struct e1000_hw *hw); ++void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); ++s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw); ++void e1000_reset_adaptive_generic(struct e1000_hw *hw); ++void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop); ++void e1000_update_adaptive_generic(struct e1000_hw *hw); ++void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value); + + #endif +diff -r 4f0f8bc35440 drivers/net/igb/e1000_manage.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/igb/e1000_manage.c Wed Aug 05 11:03:37 2009 +0100 +@@ -0,0 +1,383 @@ ++/******************************************************************************* ++ ++ Intel(R) Gigabit Ethernet Linux driver ++ Copyright(c) 2007-2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000_api.h" ++ ++static u8 e1000_calculate_checksum(u8 *buffer, u32 length); ++ ++/** ++ * e1000_calculate_checksum - Calculate checksum for buffer ++ * @buffer: pointer to EEPROM ++ * @length: size of EEPROM to calculate a checksum for ++ * ++ * Calculates the checksum for some buffer on a specified length. The ++ * checksum calculated is returned. ++ **/ ++static u8 e1000_calculate_checksum(u8 *buffer, u32 length) ++{ ++ u32 i; ++ u8 sum = 0; ++ ++ DEBUGFUNC("e1000_calculate_checksum"); ++ ++ if (!buffer) ++ return 0; ++ ++ for (i = 0; i < length; i++) ++ sum += buffer[i]; ++ ++ return (u8) (0 - sum); ++} ++ ++/** ++ * e1000_mng_enable_host_if_generic - Checks host interface is enabled ++ * @hw: pointer to the HW structure ++ * ++ * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND ++ * ++ * This function checks whether the HOST IF is enabled for command operation ++ * and also checks whether the previous command is completed. It busy waits ++ * in case of previous command is not completed. ++ **/ ++s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw) ++{ ++ u32 hicr; ++ s32 ret_val = E1000_SUCCESS; ++ u8 i; ++ ++ DEBUGFUNC("e1000_mng_enable_host_if_generic"); ++ ++ /* Check that the host interface is enabled. */ ++ hicr = E1000_READ_REG(hw, E1000_HICR); ++ if ((hicr & E1000_HICR_EN) == 0) { ++ DEBUGOUT("E1000_HOST_EN bit disabled.\n"); ++ ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; ++ goto out; ++ } ++ /* check the previous command is completed */ ++ for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { ++ hicr = E1000_READ_REG(hw, E1000_HICR); ++ if (!(hicr & E1000_HICR_C)) ++ break; ++ msec_delay_irq(1); ++ } ++ ++ if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { ++ DEBUGOUT("Previous command timeout failed .\n"); ++ ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_mng_mode_generic - Generic check management mode ++ * @hw: pointer to the HW structure ++ * ++ * Reads the firmware semaphore register and returns true (>0) if ++ * manageability is enabled, else false (0). ++ **/ ++bool e1000_check_mng_mode_generic(struct e1000_hw *hw) ++{ ++ u32 fwsm; ++ ++ DEBUGFUNC("e1000_check_mng_mode_generic"); ++ ++ fwsm = E1000_READ_REG(hw, E1000_FWSM); ++ ++ return (fwsm & E1000_FWSM_MODE_MASK) == ++ (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); ++} ++ ++/** ++ * e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on TX ++ * @hw: pointer to the HW structure ++ * ++ * Enables packet filtering on transmit packets if manageability is enabled ++ * and host interface is enabled. ++ **/ ++bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw) ++{ ++ struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie; ++ u32 *buffer = (u32 *)&hw->mng_cookie; ++ u32 offset; ++ s32 ret_val, hdr_csum, csum; ++ u8 i, len; ++ bool tx_filter = true; ++ ++ DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic"); ++ ++ /* No manageability, no filtering */ ++ if (!hw->mac.ops.check_mng_mode(hw)) { ++ tx_filter = false; ++ goto out; ++ } ++ ++ /* ++ * If we can't read from the host interface for whatever ++ * reason, disable filtering. ++ */ ++ ret_val = hw->mac.ops.mng_enable_host_if(hw); ++ if (ret_val != E1000_SUCCESS) { ++ tx_filter = false; ++ goto out; ++ } ++ ++ /* Read in the header. Length and offset are in dwords. */ ++ len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2; ++ offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2; ++ for (i = 0; i < len; i++) { ++ *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, ++ E1000_HOST_IF, ++ offset + i); ++ } ++ hdr_csum = hdr->checksum; ++ hdr->checksum = 0; ++ csum = e1000_calculate_checksum((u8 *)hdr, ++ E1000_MNG_DHCP_COOKIE_LENGTH); ++ /* ++ * If either the checksums or signature don't match, then ++ * the cookie area isn't considered valid, in which case we ++ * take the safe route of assuming Tx filtering is enabled. ++ */ ++ if (hdr_csum != csum) ++ goto out; ++ if (hdr->signature != E1000_IAMT_SIGNATURE) ++ goto out; ++ ++ /* Cookie area is valid, make the final check for filtering. */ ++ if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) ++ tx_filter = false; ++ ++out: ++ hw->mac.tx_pkt_filtering = tx_filter; ++ return tx_filter; ++} ++ ++/** ++ * e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface ++ * @hw: pointer to the HW structure ++ * @buffer: pointer to the host interface ++ * @length: size of the buffer ++ * ++ * Writes the DHCP information to the host interface. ++ **/ ++s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer, ++ u16 length) ++{ ++ struct e1000_host_mng_command_header hdr; ++ s32 ret_val; ++ u32 hicr; ++ ++ DEBUGFUNC("e1000_mng_write_dhcp_info_generic"); ++ ++ hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; ++ hdr.command_length = length; ++ hdr.reserved1 = 0; ++ hdr.reserved2 = 0; ++ hdr.checksum = 0; ++ ++ /* Enable the host interface */ ++ ret_val = hw->mac.ops.mng_enable_host_if(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Populate the host interface with the contents of "buffer". */ ++ ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length, ++ sizeof(hdr), &(hdr.checksum)); ++ if (ret_val) ++ goto out; ++ ++ /* Write the manageability command header */ ++ ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr); ++ if (ret_val) ++ goto out; ++ ++ /* Tell the ARC a new command is pending. */ ++ hicr = E1000_READ_REG(hw, E1000_HICR); ++ E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_mng_write_cmd_header_generic - Writes manageability command header ++ * @hw: pointer to the HW structure ++ * @hdr: pointer to the host interface command header ++ * ++ * Writes the command header after does the checksum calculation. ++ **/ ++s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header *hdr) ++{ ++ u16 i, length = sizeof(struct e1000_host_mng_command_header); ++ ++ DEBUGFUNC("e1000_mng_write_cmd_header_generic"); ++ ++ /* Write the whole command header structure with new checksum. */ ++ ++ hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length); ++ ++ length >>= 2; ++ /* Write the relevant command block into the ram area. */ ++ for (i = 0; i < length; i++) { ++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i, ++ *((u32 *) hdr + i)); ++ E1000_WRITE_FLUSH(hw); ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_mng_host_if_write_generic - Write to the manageability host interface ++ * @hw: pointer to the HW structure ++ * @buffer: pointer to the host interface buffer ++ * @length: size of the buffer ++ * @offset: location in the buffer to write to ++ * @sum: sum of the data (not checksum) ++ * ++ * This function writes the buffer content at the offset given on the host if. ++ * It also does alignment considerations to do the writes in most efficient ++ * way. Also fills up the sum of the buffer in *buffer parameter. ++ **/ ++s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer, ++ u16 length, u16 offset, u8 *sum) ++{ ++ u8 *tmp; ++ u8 *bufptr = buffer; ++ u32 data = 0; ++ s32 ret_val = E1000_SUCCESS; ++ u16 remaining, i, j, prev_bytes; ++ ++ DEBUGFUNC("e1000_mng_host_if_write_generic"); ++ ++ /* sum = only sum of the data and it is not checksum */ ++ ++ if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { ++ ret_val = -E1000_ERR_PARAM; ++ goto out; ++ } ++ ++ tmp = (u8 *)&data; ++ prev_bytes = offset & 0x3; ++ offset >>= 2; ++ ++ if (prev_bytes) { ++ data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset); ++ for (j = prev_bytes; j < sizeof(u32); j++) { ++ *(tmp + j) = *bufptr++; ++ *sum += *(tmp + j); ++ } ++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data); ++ length -= j - prev_bytes; ++ offset++; ++ } ++ ++ remaining = length & 0x3; ++ length -= remaining; ++ ++ /* Calculate length in DWORDs */ ++ length >>= 2; ++ ++ /* ++ * The device driver writes the relevant command block into the ++ * ram area. ++ */ ++ for (i = 0; i < length; i++) { ++ for (j = 0; j < sizeof(u32); j++) { ++ *(tmp + j) = *bufptr++; ++ *sum += *(tmp + j); ++ } ++ ++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, ++ data); ++ } ++ if (remaining) { ++ for (j = 0; j < sizeof(u32); j++) { ++ if (j < remaining) ++ *(tmp + j) = *bufptr++; ++ else ++ *(tmp + j) = 0; ++ ++ *sum += *(tmp + j); ++ } ++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_enable_mng_pass_thru - Enable processing of ARP's ++ * @hw: pointer to the HW structure ++ * ++ * Verifies the hardware needs to allow ARPs to be processed by the host. ++ **/ ++bool e1000_enable_mng_pass_thru(struct e1000_hw *hw) ++{ ++ u32 manc; ++ u32 fwsm, factps; ++ bool ret_val = false; ++ ++ DEBUGFUNC("e1000_enable_mng_pass_thru"); ++ ++ if (!hw->mac.asf_firmware_present) ++ goto out; ++ ++ manc = E1000_READ_REG(hw, E1000_MANC); ++ ++ if (!(manc & E1000_MANC_RCV_TCO_EN) || ++ !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) ++ goto out; ++ ++ if (hw->mac.arc_subsystem_valid) { ++ fwsm = E1000_READ_REG(hw, E1000_FWSM); ++ factps = E1000_READ_REG(hw, E1000_FACTPS); ++ ++ if (!(factps & E1000_FACTPS_MNGCG) && ++ ((fwsm & E1000_FWSM_MODE_MASK) == ++ (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { ++ ret_val = true; ++ goto out; ++ } ++ } else { ++ if ((manc & E1000_MANC_SMBUS_EN) && ++ !(manc & E1000_MANC_ASF_EN)) { ++ ret_val = true; ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ +diff -r 4f0f8bc35440 drivers/net/igb/e1000_manage.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/igb/e1000_manage.h Wed Aug 05 11:03:37 2009 +0100 +@@ -0,0 +1,81 @@ ++/******************************************************************************* ++ ++ Intel(R) Gigabit Ethernet Linux driver ++ Copyright(c) 2007-2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_MANAGE_H_ ++#define _E1000_MANAGE_H_ ++ ++bool e1000_check_mng_mode_generic(struct e1000_hw *hw); ++bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw); ++s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw); ++s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer, ++ u16 length, u16 offset, u8 *sum); ++s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header *hdr); ++s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, ++ u8 *buffer, u16 length); ++bool e1000_enable_mng_pass_thru(struct e1000_hw *hw); ++ ++enum e1000_mng_mode { ++ e1000_mng_mode_none = 0, ++ e1000_mng_mode_asf, ++ e1000_mng_mode_pt, ++ e1000_mng_mode_ipmi, ++ e1000_mng_mode_host_if_only ++}; ++ ++#define E1000_FACTPS_MNGCG 0x20000000 ++ ++#define E1000_FWSM_MODE_MASK 0xE ++#define E1000_FWSM_MODE_SHIFT 1 ++ ++#define E1000_MNG_IAMT_MODE 0x3 ++#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 ++#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 ++#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 ++#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 ++#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 ++#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 ++ ++#define E1000_VFTA_ENTRY_SHIFT 5 ++#define E1000_VFTA_ENTRY_MASK 0x7F ++#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F ++ ++#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ ++#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ ++#define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ ++ ++#define E1000_HICR_EN 0x01 /* Enable bit - RO */ ++/* Driver sets this bit when done to put command in RAM */ ++#define E1000_HICR_C 0x02 ++#define E1000_HICR_SV 0x04 /* Status Validity */ ++#define E1000_HICR_FW_RESET_ENABLE 0x40 ++#define E1000_HICR_FW_RESET 0x80 ++ ++/* Intel(R) Active Management Technology signature */ ++#define E1000_IAMT_SIGNATURE 0x544D4149 ++ ++#endif +diff -r 4f0f8bc35440 drivers/net/igb/e1000_nvm.c +--- a/drivers/net/igb/e1000_nvm.c Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/e1000_nvm.c Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -25,44 +25,58 @@ + + *******************************************************************************/ + +-#include +-#include ++#include "e1000_api.h" + +-#include "e1000_mac.h" +-#include "e1000_nvm.h" ++static void e1000_stop_nvm(struct e1000_hw *hw); ++static void e1000_reload_nvm_generic(struct e1000_hw *hw); + + /** +- * igb_raise_eec_clk - Raise EEPROM clock ++ * e1000_init_nvm_ops_generic - Initialize NVM function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Setups up the function pointers to no-op functions ++ **/ ++void e1000_init_nvm_ops_generic(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ DEBUGFUNC("e1000_init_nvm_ops_generic"); ++ ++ /* Initialize function pointers */ ++ nvm->ops.reload = e1000_reload_nvm_generic; ++} ++ ++/** ++ * e1000_raise_eec_clk - Raise EEPROM clock + * @hw: pointer to the HW structure + * @eecd: pointer to the EEPROM + * + * Enable/Raise the EEPROM clock bit. + **/ +-static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) ++static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) + { + *eecd = *eecd | E1000_EECD_SK; +- wr32(E1000_EECD, *eecd); +- wrfl(); +- udelay(hw->nvm.delay_usec); ++ E1000_WRITE_REG(hw, E1000_EECD, *eecd); ++ E1000_WRITE_FLUSH(hw); ++ usec_delay(hw->nvm.delay_usec); + } + + /** +- * igb_lower_eec_clk - Lower EEPROM clock ++ * e1000_lower_eec_clk - Lower EEPROM clock + * @hw: pointer to the HW structure + * @eecd: pointer to the EEPROM + * + * Clear/Lower the EEPROM clock bit. + **/ +-static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) ++static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) + { + *eecd = *eecd & ~E1000_EECD_SK; +- wr32(E1000_EECD, *eecd); +- wrfl(); +- udelay(hw->nvm.delay_usec); ++ E1000_WRITE_REG(hw, E1000_EECD, *eecd); ++ E1000_WRITE_FLUSH(hw); ++ usec_delay(hw->nvm.delay_usec); + } + + /** +- * igb_shift_out_eec_bits - Shift data bits our to the EEPROM ++ * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM + * @hw: pointer to the HW structure + * @data: data to send to the EEPROM + * @count: number of bits to shift out +@@ -71,16 +85,16 @@ + * "data" parameter will be shifted out to the EEPROM one bit at a time. + * In order to do this, "data" must be broken down into bits. + **/ +-static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) ++static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) + { + struct e1000_nvm_info *nvm = &hw->nvm; +- u32 eecd = rd32(E1000_EECD); ++ u32 eecd = E1000_READ_REG(hw, E1000_EECD); + u32 mask; + ++ DEBUGFUNC("e1000_shift_out_eec_bits"); ++ + mask = 0x01 << (count - 1); +- if (nvm->type == e1000_nvm_eeprom_microwire) +- eecd &= ~E1000_EECD_DO; +- else if (nvm->type == e1000_nvm_eeprom_spi) ++ if (nvm->type == e1000_nvm_eeprom_spi) + eecd |= E1000_EECD_DO; + + do { +@@ -89,23 +103,23 @@ + if (data & mask) + eecd |= E1000_EECD_DI; + +- wr32(E1000_EECD, eecd); +- wrfl(); ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ E1000_WRITE_FLUSH(hw); + +- udelay(nvm->delay_usec); ++ usec_delay(nvm->delay_usec); + +- igb_raise_eec_clk(hw, &eecd); +- igb_lower_eec_clk(hw, &eecd); ++ e1000_raise_eec_clk(hw, &eecd); ++ e1000_lower_eec_clk(hw, &eecd); + + mask >>= 1; + } while (mask); + + eecd &= ~E1000_EECD_DI; +- wr32(E1000_EECD, eecd); ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); + } + + /** +- * igb_shift_in_eec_bits - Shift data bits in from the EEPROM ++ * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM + * @hw: pointer to the HW structure + * @count: number of bits to shift in + * +@@ -115,94 +129,99 @@ + * "DO" bit. During this "shifting in" process the data in "DI" bit should + * always be clear. + **/ +-static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count) ++static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) + { + u32 eecd; + u32 i; + u16 data; + +- eecd = rd32(E1000_EECD); ++ DEBUGFUNC("e1000_shift_in_eec_bits"); ++ ++ eecd = E1000_READ_REG(hw, E1000_EECD); + + eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); + data = 0; + + for (i = 0; i < count; i++) { + data <<= 1; +- igb_raise_eec_clk(hw, &eecd); ++ e1000_raise_eec_clk(hw, &eecd); + +- eecd = rd32(E1000_EECD); ++ eecd = E1000_READ_REG(hw, E1000_EECD); + + eecd &= ~E1000_EECD_DI; + if (eecd & E1000_EECD_DO) + data |= 1; + +- igb_lower_eec_clk(hw, &eecd); ++ e1000_lower_eec_clk(hw, &eecd); + } + + return data; + } + + /** +- * igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion ++ * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion + * @hw: pointer to the HW structure + * @ee_reg: EEPROM flag for polling + * + * Polls the EEPROM status bit for either read or write completion based + * upon the value of 'ee_reg'. + **/ +-static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) ++s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) + { + u32 attempts = 100000; + u32 i, reg = 0; + s32 ret_val = -E1000_ERR_NVM; + ++ DEBUGFUNC("e1000_poll_eerd_eewr_done"); ++ + for (i = 0; i < attempts; i++) { + if (ee_reg == E1000_NVM_POLL_READ) +- reg = rd32(E1000_EERD); ++ reg = E1000_READ_REG(hw, E1000_EERD); + else +- reg = rd32(E1000_EEWR); ++ reg = E1000_READ_REG(hw, E1000_EEWR); + + if (reg & E1000_NVM_RW_REG_DONE) { +- ret_val = 0; ++ ret_val = E1000_SUCCESS; + break; + } + +- udelay(5); ++ usec_delay(5); + } + + return ret_val; + } + + /** +- * igb_acquire_nvm - Generic request for access to EEPROM ++ * e1000_acquire_nvm_generic - Generic request for access to EEPROM + * @hw: pointer to the HW structure + * + * Set the EEPROM access request bit and wait for EEPROM access grant bit. + * Return successful if access grant bit set, else clear the request for + * EEPROM access and return -E1000_ERR_NVM (-1). + **/ +-s32 igb_acquire_nvm(struct e1000_hw *hw) ++s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) + { +- u32 eecd = rd32(E1000_EECD); ++ u32 eecd = E1000_READ_REG(hw, E1000_EECD); + s32 timeout = E1000_NVM_GRANT_ATTEMPTS; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + ++ DEBUGFUNC("e1000_acquire_nvm_generic"); + +- wr32(E1000_EECD, eecd | E1000_EECD_REQ); +- eecd = rd32(E1000_EECD); ++ E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); ++ eecd = E1000_READ_REG(hw, E1000_EECD); + + while (timeout) { + if (eecd & E1000_EECD_GNT) + break; +- udelay(5); +- eecd = rd32(E1000_EECD); ++ usec_delay(5); ++ eecd = E1000_READ_REG(hw, E1000_EECD); + timeout--; + } + + if (!timeout) { + eecd &= ~E1000_EECD_REQ; +- wr32(E1000_EECD, eecd); +- hw_dbg("Could not acquire NVM grant\n"); ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ DEBUGOUT("Could not acquire NVM grant\n"); + ret_val = -E1000_ERR_NVM; + } + +@@ -210,41 +229,28 @@ + } + + /** +- * igb_standby_nvm - Return EEPROM to standby state ++ * e1000_standby_nvm - Return EEPROM to standby state + * @hw: pointer to the HW structure + * + * Return the EEPROM to a standby state. + **/ +-static void igb_standby_nvm(struct e1000_hw *hw) ++static void e1000_standby_nvm(struct e1000_hw *hw) + { + struct e1000_nvm_info *nvm = &hw->nvm; +- u32 eecd = rd32(E1000_EECD); ++ u32 eecd = E1000_READ_REG(hw, E1000_EECD); + +- if (nvm->type == e1000_nvm_eeprom_microwire) { +- eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); +- wr32(E1000_EECD, eecd); +- wrfl(); +- udelay(nvm->delay_usec); ++ DEBUGFUNC("e1000_standby_nvm"); + +- igb_raise_eec_clk(hw, &eecd); +- +- /* Select EEPROM */ +- eecd |= E1000_EECD_CS; +- wr32(E1000_EECD, eecd); +- wrfl(); +- udelay(nvm->delay_usec); +- +- igb_lower_eec_clk(hw, &eecd); +- } else if (nvm->type == e1000_nvm_eeprom_spi) { ++ if (nvm->type == e1000_nvm_eeprom_spi) { + /* Toggle CS to flush commands */ + eecd |= E1000_EECD_CS; +- wr32(E1000_EECD, eecd); +- wrfl(); +- udelay(nvm->delay_usec); ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ E1000_WRITE_FLUSH(hw); ++ usec_delay(nvm->delay_usec); + eecd &= ~E1000_EECD_CS; +- wr32(E1000_EECD, eecd); +- wrfl(); +- udelay(nvm->delay_usec); ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ E1000_WRITE_FLUSH(hw); ++ usec_delay(nvm->delay_usec); + } + } + +@@ -258,64 +264,56 @@ + { + u32 eecd; + +- eecd = rd32(E1000_EECD); ++ DEBUGFUNC("e1000_stop_nvm"); ++ ++ eecd = E1000_READ_REG(hw, E1000_EECD); + if (hw->nvm.type == e1000_nvm_eeprom_spi) { + /* Pull CS high */ + eecd |= E1000_EECD_CS; +- igb_lower_eec_clk(hw, &eecd); +- } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { +- /* CS on Microcwire is active-high */ +- eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); +- wr32(E1000_EECD, eecd); +- igb_raise_eec_clk(hw, &eecd); +- igb_lower_eec_clk(hw, &eecd); ++ e1000_lower_eec_clk(hw, &eecd); + } + } + + /** +- * igb_release_nvm - Release exclusive access to EEPROM ++ * e1000_release_nvm_generic - Release exclusive access to EEPROM + * @hw: pointer to the HW structure + * + * Stop any current commands to the EEPROM and clear the EEPROM request bit. + **/ +-void igb_release_nvm(struct e1000_hw *hw) ++void e1000_release_nvm_generic(struct e1000_hw *hw) + { + u32 eecd; + ++ DEBUGFUNC("e1000_release_nvm_generic"); ++ + e1000_stop_nvm(hw); + +- eecd = rd32(E1000_EECD); ++ eecd = E1000_READ_REG(hw, E1000_EECD); + eecd &= ~E1000_EECD_REQ; +- wr32(E1000_EECD, eecd); ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); + } + + /** +- * igb_ready_nvm_eeprom - Prepares EEPROM for read/write ++ * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write + * @hw: pointer to the HW structure + * + * Setups the EEPROM for reading and writing. + **/ +-static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw) ++static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) + { + struct e1000_nvm_info *nvm = &hw->nvm; +- u32 eecd = rd32(E1000_EECD); +- s32 ret_val = 0; ++ u32 eecd = E1000_READ_REG(hw, E1000_EECD); ++ s32 ret_val = E1000_SUCCESS; + u16 timeout = 0; + u8 spi_stat_reg; + ++ DEBUGFUNC("e1000_ready_nvm_eeprom"); + +- if (nvm->type == e1000_nvm_eeprom_microwire) { +- /* Clear SK and DI */ +- eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); +- wr32(E1000_EECD, eecd); +- /* Set CS */ +- eecd |= E1000_EECD_CS; +- wr32(E1000_EECD, eecd); +- } else if (nvm->type == e1000_nvm_eeprom_spi) { ++ if (nvm->type == e1000_nvm_eeprom_spi) { + /* Clear SK and CS */ + eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); +- wr32(E1000_EECD, eecd); +- udelay(1); ++ E1000_WRITE_REG(hw, E1000_EECD, eecd); ++ usec_delay(1); + timeout = NVM_MAX_RETRY_SPI; + + /* +@@ -325,19 +323,19 @@ + * not cleared within 'timeout', then error out. + */ + while (timeout) { +- igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, +- hw->nvm.opcode_bits); +- spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8); ++ e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, ++ hw->nvm.opcode_bits); ++ spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); + if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) + break; + +- udelay(5); +- igb_standby_nvm(hw); ++ usec_delay(5); ++ e1000_standby_nvm(hw); + timeout--; + } + + if (!timeout) { +- hw_dbg("SPI NVM Status error\n"); ++ DEBUGOUT("SPI NVM Status error\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } +@@ -348,7 +346,7 @@ + } + + /** +- * igb_read_nvm_eerd - Reads EEPROM using EERD register ++ * e1000_read_nvm_eerd - Reads EEPROM using EERD register + * @hw: pointer to the HW structure + * @offset: offset of word in the EEPROM to read + * @words: number of words to read +@@ -356,19 +354,21 @@ + * + * Reads a 16 bit word from the EEPROM using the EERD register. + **/ +-s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + { + struct e1000_nvm_info *nvm = &hw->nvm; + u32 i, eerd = 0; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_read_nvm_eerd"); + + /* + * A check for invalid values: offset too large, too many words, +- * and not enough words. ++ * too many words for the offset, and not enough words. + */ + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || + (words == 0)) { +- hw_dbg("nvm parameter(s) out of bounds\n"); ++ DEBUGOUT("nvm parameter(s) out of bounds\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } +@@ -377,13 +377,13 @@ + eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + + E1000_NVM_RW_REG_START; + +- wr32(E1000_EERD, eerd); +- ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); ++ E1000_WRITE_REG(hw, E1000_EERD, eerd); ++ ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); + if (ret_val) + break; + +- data[i] = (rd32(E1000_EERD) >> +- E1000_NVM_RW_REG_DATA); ++ data[i] = (E1000_READ_REG(hw, E1000_EERD) >> ++ E1000_NVM_RW_REG_DATA); + } + + out: +@@ -391,7 +391,7 @@ + } + + /** +- * igb_write_nvm_spi - Write to EEPROM using SPI ++ * e1000_write_nvm_spi - Write to EEPROM using SPI + * @hw: pointer to the HW structure + * @offset: offset within the EEPROM to be written to + * @words: number of words to write +@@ -400,13 +400,15 @@ + * Writes data to EEPROM at offset using SPI interface. + * + * If e1000_update_nvm_checksum is not called after this function , the +- * EEPROM will most likley contain an invalid checksum. ++ * EEPROM will most likely contain an invalid checksum. + **/ +-s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + { + struct e1000_nvm_info *nvm = &hw->nvm; + s32 ret_val; + u16 widx = 0; ++ ++ DEBUGFUNC("e1000_write_nvm_spi"); + + /* + * A check for invalid values: offset too large, too many words, +@@ -414,31 +416,29 @@ + */ + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || + (words == 0)) { +- hw_dbg("nvm parameter(s) out of bounds\n"); ++ DEBUGOUT("nvm parameter(s) out of bounds\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + +- ret_val = hw->nvm.ops.acquire_nvm(hw); ++ ret_val = nvm->ops.acquire(hw); + if (ret_val) + goto out; +- +- msleep(10); + + while (widx < words) { + u8 write_opcode = NVM_WRITE_OPCODE_SPI; + +- ret_val = igb_ready_nvm_eeprom(hw); ++ ret_val = e1000_ready_nvm_eeprom(hw); + if (ret_val) + goto release; + +- igb_standby_nvm(hw); ++ e1000_standby_nvm(hw); + + /* Send the WRITE ENABLE command (8 bit opcode) */ +- igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, +- nvm->opcode_bits); ++ e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, ++ nvm->opcode_bits); + +- igb_standby_nvm(hw); ++ e1000_standby_nvm(hw); + + /* + * Some SPI eeproms use the 8th address bit embedded in the +@@ -448,122 +448,120 @@ + write_opcode |= NVM_A8_OPCODE_SPI; + + /* Send the Write command (8-bit opcode + addr) */ +- igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); +- igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), +- nvm->address_bits); ++ e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); ++ e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), ++ nvm->address_bits); + + /* Loop to allow for up to whole page write of eeprom */ + while (widx < words) { + u16 word_out = data[widx]; + word_out = (word_out >> 8) | (word_out << 8); +- igb_shift_out_eec_bits(hw, word_out, 16); ++ e1000_shift_out_eec_bits(hw, word_out, 16); + widx++; + + if ((((offset + widx) * 2) % nvm->page_size) == 0) { +- igb_standby_nvm(hw); ++ e1000_standby_nvm(hw); + break; + } + } + } + +- msleep(10); ++ msec_delay(10); + release: +- hw->nvm.ops.release_nvm(hw); ++ nvm->ops.release(hw); + + out: + return ret_val; + } + + /** +- * igb_read_part_num - Read device part number ++ * e1000_read_pba_num_generic - Read device part number + * @hw: pointer to the HW structure +- * @part_num: pointer to device part number ++ * @pba_num: pointer to device part number + * + * Reads the product board assembly (PBA) number from the EEPROM and stores +- * the value in part_num. ++ * the value in pba_num. + **/ +-s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num) ++s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num) + { + s32 ret_val; + u16 nvm_data; + +- ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); ++ DEBUGFUNC("e1000_read_pba_num_generic"); ++ ++ ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); + if (ret_val) { +- hw_dbg("NVM Read Error\n"); ++ DEBUGOUT("NVM Read Error\n"); + goto out; + } +- *part_num = (u32)(nvm_data << 16); ++ *pba_num = (u32)(nvm_data << 16); + +- ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); ++ ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); + if (ret_val) { +- hw_dbg("NVM Read Error\n"); ++ DEBUGOUT("NVM Read Error\n"); + goto out; + } +- *part_num |= nvm_data; ++ *pba_num |= nvm_data; + + out: + return ret_val; + } + + /** +- * igb_read_mac_addr - Read device MAC address ++ * e1000_read_mac_addr_generic - Read device MAC address + * @hw: pointer to the HW structure + * + * Reads the device MAC address from the EEPROM and stores the value. + * Since devices with two ports use the same EEPROM, we increment the + * last bit in the MAC address for the second port. + **/ +-s32 igb_read_mac_addr(struct e1000_hw *hw) ++s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) + { +- s32 ret_val = 0; +- u16 offset, nvm_data, i; ++ u32 rar_high; ++ u32 rar_low; ++ u16 i; + +- for (i = 0; i < ETH_ALEN; i += 2) { +- offset = i >> 1; +- ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data); +- if (ret_val) { +- hw_dbg("NVM Read Error\n"); +- goto out; +- } +- hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); +- hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); +- } ++ rar_high = E1000_READ_REG(hw, E1000_RAH(0)); ++ rar_low = E1000_READ_REG(hw, E1000_RAL(0)); + +- /* Flip last bit of mac address if we're on second port */ +- if (hw->bus.func == E1000_FUNC_1) +- hw->mac.perm_addr[5] ^= 1; ++ for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) ++ hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); + +- for (i = 0; i < ETH_ALEN; i++) ++ for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) ++ hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); ++ ++ for (i = 0; i < ETH_ADDR_LEN; i++) + hw->mac.addr[i] = hw->mac.perm_addr[i]; + +-out: +- return ret_val; ++ return E1000_SUCCESS; + } + + /** +- * igb_validate_nvm_checksum - Validate EEPROM checksum ++ * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum + * @hw: pointer to the HW structure + * + * Calculates the EEPROM checksum by reading/adding each word of the EEPROM + * and then verifies that the sum of the EEPROM is equal to 0xBABA. + **/ +-s32 igb_validate_nvm_checksum(struct e1000_hw *hw) ++s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) + { +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + u16 checksum = 0; + u16 i, nvm_data; + ++ DEBUGFUNC("e1000_validate_nvm_checksum_generic"); ++ + for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { +- ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data); ++ ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); + if (ret_val) { +- hw_dbg("NVM Read Error\n"); ++ DEBUGOUT("NVM Read Error\n"); + goto out; + } + checksum += nvm_data; + } + + if (checksum != (u16) NVM_SUM) { +- hw_dbg("NVM Checksum Invalid\n"); ++ DEBUGOUT("NVM Checksum Invalid\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } +@@ -573,33 +571,55 @@ + } + + /** +- * igb_update_nvm_checksum - Update EEPROM checksum ++ * e1000_update_nvm_checksum_generic - Update EEPROM checksum + * @hw: pointer to the HW structure + * + * Updates the EEPROM checksum by reading/adding each word of the EEPROM + * up to the checksum. Then calculates the EEPROM checksum and writes the + * value to the EEPROM. + **/ +-s32 igb_update_nvm_checksum(struct e1000_hw *hw) ++s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) + { + s32 ret_val; + u16 checksum = 0; + u16 i, nvm_data; + ++ DEBUGFUNC("e1000_update_nvm_checksum"); ++ + for (i = 0; i < NVM_CHECKSUM_REG; i++) { +- ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data); ++ ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); + if (ret_val) { +- hw_dbg("NVM Read Error while updating checksum.\n"); ++ DEBUGOUT("NVM Read Error while updating checksum.\n"); + goto out; + } + checksum += nvm_data; + } + checksum = (u16) NVM_SUM - checksum; +- ret_val = hw->nvm.ops.write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); ++ ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); + if (ret_val) +- hw_dbg("NVM Write Error while updating checksum.\n"); ++ DEBUGOUT("NVM Write Error while updating checksum.\n"); + + out: + return ret_val; + } + ++/** ++ * e1000_reload_nvm_generic - Reloads EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the ++ * extended control register. ++ **/ ++static void e1000_reload_nvm_generic(struct e1000_hw *hw) ++{ ++ u32 ctrl_ext; ++ ++ DEBUGFUNC("e1000_reload_nvm_generic"); ++ ++ usec_delay(10); ++ ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); ++ ctrl_ext |= E1000_CTRL_EXT_EE_RST; ++ E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); ++ E1000_WRITE_FLUSH(hw); ++} ++ +diff -r 4f0f8bc35440 drivers/net/igb/e1000_nvm.h +--- a/drivers/net/igb/e1000_nvm.h Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/e1000_nvm.h Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -28,13 +28,23 @@ + #ifndef _E1000_NVM_H_ + #define _E1000_NVM_H_ + +-s32 igb_acquire_nvm(struct e1000_hw *hw); +-void igb_release_nvm(struct e1000_hw *hw); +-s32 igb_read_mac_addr(struct e1000_hw *hw); +-s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num); +-s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); +-s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); +-s32 igb_validate_nvm_checksum(struct e1000_hw *hw); +-s32 igb_update_nvm_checksum(struct e1000_hw *hw); ++void e1000_init_nvm_ops_generic(struct e1000_hw *hw); ++s32 e1000_acquire_nvm_generic(struct e1000_hw *hw); ++ ++s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg); ++s32 e1000_read_mac_addr_generic(struct e1000_hw *hw); ++s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num); ++s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data); ++s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data); ++s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw); ++s32 e1000_write_nvm_eewr(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data); ++s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data); ++s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw); ++void e1000_release_nvm_generic(struct e1000_hw *hw); ++ ++#define E1000_STM_OPCODE 0xDB00 + + #endif +diff -r 4f0f8bc35440 drivers/net/igb/e1000_osdep.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/igb/e1000_osdep.h Wed Aug 05 11:03:37 2009 +0100 +@@ -0,0 +1,122 @@ ++/******************************************************************************* ++ ++ Intel(R) Gigabit Ethernet Linux driver ++ Copyright(c) 2007-2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++ ++/* glue for the OS independent part of e1000 ++ * includes register access macros ++ */ ++ ++#ifndef _E1000_OSDEP_H_ ++#define _E1000_OSDEP_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include "kcompat.h" ++ ++#define usec_delay(x) udelay(x) ++#ifndef msec_delay ++#define msec_delay(x) do { \ ++ /* Don't mdelay in interrupt context! */ \ ++ if (in_interrupt()) \ ++ BUG(); \ ++ else \ ++ msleep(x); \ ++} while (0) ++ ++/* Some workarounds require millisecond delays and are run during interrupt ++ * context. Most notably, when establishing link, the phy may need tweaking ++ * but cannot process phy register reads/writes faster than millisecond ++ * intervals...and we establish link due to a "link status change" interrupt. ++ */ ++#define msec_delay_irq(x) mdelay(x) ++#endif ++ ++#define PCI_COMMAND_REGISTER PCI_COMMAND ++#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE ++#define ETH_ADDR_LEN ETH_ALEN ++ ++#ifdef __BIG_ENDIAN ++#define E1000_BIG_ENDIAN __BIG_ENDIAN ++#endif ++ ++ ++#define DEBUGOUT(S) ++#define DEBUGOUT1(S, A...) ++ ++#define DEBUGFUNC(F) DEBUGOUT(F "\n") ++#define DEBUGOUT2 DEBUGOUT1 ++#define DEBUGOUT3 DEBUGOUT2 ++#define DEBUGOUT7 DEBUGOUT3 ++ ++#define E1000_REGISTER(a, reg) reg ++ ++#define E1000_WRITE_REG(a, reg, value) ( \ ++ writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg)))) ++ ++#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_REGISTER(a, reg))) ++ ++#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \ ++ writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2)))) ++ ++#define E1000_READ_REG_ARRAY(a, reg, offset) ( \ ++ readl((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2))) ++ ++#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY ++#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY ++ ++#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \ ++ writew((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1)))) ++ ++#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \ ++ readw((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1))) ++ ++#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \ ++ writeb((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + (offset)))) ++ ++#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \ ++ readb((a)->hw_addr + E1000_REGISTER(a, reg) + (offset))) ++ ++#define E1000_WRITE_REG_IO(a, reg, offset) do { \ ++ outl(reg, ((a)->io_base)); \ ++ outl(offset, ((a)->io_base + 4)); } while (0) ++ ++#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS) ++ ++#define E1000_WRITE_FLASH_REG(a, reg, value) ( \ ++ writel((value), ((a)->flash_address + reg))) ++ ++#define E1000_WRITE_FLASH_REG16(a, reg, value) ( \ ++ writew((value), ((a)->flash_address + reg))) ++ ++#define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg)) ++ ++#define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg)) ++ ++#endif /* _E1000_OSDEP_H_ */ +diff -r 4f0f8bc35440 drivers/net/igb/e1000_phy.c +--- a/drivers/net/igb/e1000_phy.c Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/e1000_phy.c Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -25,27 +25,15 @@ + + *******************************************************************************/ + +-#include +-#include ++#include "e1000_api.h" + +-#include "e1000_mac.h" +-#include "e1000_phy.h" +- +-static s32 igb_get_phy_cfg_done(struct e1000_hw *hw); +-static void igb_release_phy(struct e1000_hw *hw); +-static s32 igb_acquire_phy(struct e1000_hw *hw); +-static s32 igb_phy_reset_dsp(struct e1000_hw *hw); +-static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); +-static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, +- u16 *phy_ctrl); +-static s32 igb_wait_autoneg(struct e1000_hw *hw); +- ++static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); + /* Cable length tables */ + static const u16 e1000_m88_cable_length_table[] = + { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; + #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ +- (sizeof(e1000_m88_cable_length_table) / \ +- sizeof(e1000_m88_cable_length_table[0])) ++ (sizeof(e1000_m88_cable_length_table) / \ ++ sizeof(e1000_m88_cable_length_table[0])) + + static const u16 e1000_igp_2_cable_length_table[] = + { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, +@@ -57,97 +45,105 @@ + 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, + 104, 109, 114, 118, 121, 124}; + #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ +- (sizeof(e1000_igp_2_cable_length_table) / \ +- sizeof(e1000_igp_2_cable_length_table[0])) ++ (sizeof(e1000_igp_2_cable_length_table) / \ ++ sizeof(e1000_igp_2_cable_length_table[0])) + + /** +- * igb_check_reset_block - Check if PHY reset is blocked ++ * e1000_check_reset_block_generic - Check if PHY reset is blocked + * @hw: pointer to the HW structure + * + * Read the PHY management control register and check whether a PHY reset +- * is blocked. If a reset is not blocked return 0, otherwise ++ * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise + * return E1000_BLK_PHY_RESET (12). + **/ +-s32 igb_check_reset_block(struct e1000_hw *hw) ++s32 e1000_check_reset_block_generic(struct e1000_hw *hw) + { + u32 manc; + +- manc = rd32(E1000_MANC); ++ DEBUGFUNC("e1000_check_reset_block"); ++ ++ manc = E1000_READ_REG(hw, E1000_MANC); + + return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? +- E1000_BLK_PHY_RESET : 0; ++ E1000_BLK_PHY_RESET : E1000_SUCCESS; + } + + /** +- * igb_get_phy_id - Retrieve the PHY ID and revision ++ * e1000_get_phy_id - Retrieve the PHY ID and revision + * @hw: pointer to the HW structure + * + * Reads the PHY registers and stores the PHY ID and possibly the PHY + * revision in the hardware structure. + **/ +-s32 igb_get_phy_id(struct e1000_hw *hw) ++s32 e1000_get_phy_id(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + u16 phy_id; + +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_ID1, &phy_id); +- if (ret_val) ++ DEBUGFUNC("e1000_get_phy_id"); ++ ++ if (!(phy->ops.read_reg)) + goto out; + +- phy->id = (u32)(phy_id << 16); +- udelay(20); +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_ID2, &phy_id); +- if (ret_val) +- goto out; ++ ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); ++ if (ret_val) ++ goto out; + +- phy->id |= (u32)(phy_id & PHY_REVISION_MASK); +- phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); ++ phy->id = (u32)(phy_id << 16); ++ usec_delay(20); ++ ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); ++ if (ret_val) ++ goto out; ++ ++ phy->id |= (u32)(phy_id & PHY_REVISION_MASK); ++ phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); + + out: + return ret_val; + } + + /** +- * igb_phy_reset_dsp - Reset PHY DSP ++ * e1000_phy_reset_dsp_generic - Reset PHY DSP + * @hw: pointer to the HW structure + * + * Reset the digital signal processor. + **/ +-static s32 igb_phy_reset_dsp(struct e1000_hw *hw) ++s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) + { +- s32 ret_val; ++ s32 ret_val = E1000_SUCCESS; + +- ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); ++ DEBUGFUNC("e1000_phy_reset_dsp_generic"); ++ ++ if (!(hw->phy.ops.write_reg)) ++ goto out; ++ ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); + if (ret_val) + goto out; + +- ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); ++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); + + out: + return ret_val; + } + + /** +- * igb_read_phy_reg_mdic - Read MDI control register ++ * e1000_read_phy_reg_mdic - Read MDI control register + * @hw: pointer to the HW structure + * @offset: register offset to be read + * @data: pointer to the read data + * +- * Reads the MDI control regsiter in the PHY at offset and stores the ++ * Reads the MDI control register in the PHY at offset and stores the + * information read to data. + **/ +-static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) ++s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) + { + struct e1000_phy_info *phy = &hw->phy; + u32 i, mdic = 0; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + +- if (offset > MAX_PHY_REG_ADDRESS) { +- hw_dbg("PHY Address %d is out of range\n", offset); +- ret_val = -E1000_ERR_PARAM; +- goto out; +- } ++ DEBUGFUNC("e1000_read_phy_reg_mdic"); + + /* + * Set up Op-code, Phy Address, and register offset in the MDI +@@ -155,10 +151,10 @@ + * PHY to retrieve the desired data. + */ + mdic = ((offset << E1000_MDIC_REG_SHIFT) | +- (phy->addr << E1000_MDIC_PHY_SHIFT) | +- (E1000_MDIC_OP_READ)); ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_READ)); + +- wr32(E1000_MDIC, mdic); ++ E1000_WRITE_REG(hw, E1000_MDIC, mdic); + + /* + * Poll the ready bit to see if the MDI read completed +@@ -166,18 +162,18 @@ + * the lower time out + */ + for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { +- udelay(50); +- mdic = rd32(E1000_MDIC); ++ usec_delay(50); ++ mdic = E1000_READ_REG(hw, E1000_MDIC); + if (mdic & E1000_MDIC_READY) + break; + } + if (!(mdic & E1000_MDIC_READY)) { +- hw_dbg("MDI Read did not complete\n"); ++ DEBUGOUT("MDI Read did not complete\n"); + ret_val = -E1000_ERR_PHY; + goto out; + } + if (mdic & E1000_MDIC_ERROR) { +- hw_dbg("MDI Error\n"); ++ DEBUGOUT("MDI Error\n"); + ret_val = -E1000_ERR_PHY; + goto out; + } +@@ -188,24 +184,20 @@ + } + + /** +- * igb_write_phy_reg_mdic - Write MDI control register ++ * e1000_write_phy_reg_mdic - Write MDI control register + * @hw: pointer to the HW structure + * @offset: register offset to write to + * @data: data to write to register at offset + * + * Writes data to MDI control register in the PHY at offset. + **/ +-static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) ++s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) + { + struct e1000_phy_info *phy = &hw->phy; + u32 i, mdic = 0; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + +- if (offset > MAX_PHY_REG_ADDRESS) { +- hw_dbg("PHY Address %d is out of range\n", offset); +- ret_val = -E1000_ERR_PARAM; +- goto out; +- } ++ DEBUGFUNC("e1000_write_phy_reg_mdic"); + + /* + * Set up Op-code, Phy Address, and register offset in the MDI +@@ -213,11 +205,11 @@ + * PHY to retrieve the desired data. + */ + mdic = (((u32)data) | +- (offset << E1000_MDIC_REG_SHIFT) | +- (phy->addr << E1000_MDIC_PHY_SHIFT) | +- (E1000_MDIC_OP_WRITE)); ++ (offset << E1000_MDIC_REG_SHIFT) | ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_WRITE)); + +- wr32(E1000_MDIC, mdic); ++ E1000_WRITE_REG(hw, E1000_MDIC, mdic); + + /* + * Poll the ready bit to see if the MDI read completed +@@ -225,18 +217,18 @@ + * the lower time out + */ + for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { +- udelay(50); +- mdic = rd32(E1000_MDIC); ++ usec_delay(50); ++ mdic = E1000_READ_REG(hw, E1000_MDIC); + if (mdic & E1000_MDIC_READY) + break; + } + if (!(mdic & E1000_MDIC_READY)) { +- hw_dbg("MDI Write did not complete\n"); ++ DEBUGOUT("MDI Write did not complete\n"); + ret_val = -E1000_ERR_PHY; + goto out; + } + if (mdic & E1000_MDIC_ERROR) { +- hw_dbg("MDI Error\n"); ++ DEBUGOUT("MDI Error\n"); + ret_val = -E1000_ERR_PHY; + goto out; + } +@@ -246,7 +238,7 @@ + } + + /** +- * igb_read_phy_reg_igp - Read igp PHY register ++ * e1000_read_phy_reg_m88 - Read m88 PHY register + * @hw: pointer to the HW structure + * @offset: register offset to be read + * @data: pointer to the read data +@@ -255,36 +247,30 @@ + * and storing the retrieved information in data. Release any acquired + * semaphores before exiting. + **/ +-s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) ++s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) + { +- s32 ret_val; ++ s32 ret_val = E1000_SUCCESS; + +- ret_val = igb_acquire_phy(hw); ++ DEBUGFUNC("e1000_read_phy_reg_m88"); ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); + if (ret_val) + goto out; + +- if (offset > MAX_PHY_MULTI_PAGE_REG) { +- ret_val = igb_write_phy_reg_mdic(hw, +- IGP01E1000_PHY_PAGE_SELECT, +- (u16)offset); +- if (ret_val) { +- igb_release_phy(hw); +- goto out; +- } +- } ++ ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); + +- ret_val = igb_read_phy_reg_mdic(hw, +- MAX_PHY_REG_ADDRESS & offset, +- data); +- +- igb_release_phy(hw); ++ hw->phy.ops.release(hw); + + out: + return ret_val; + } + + /** +- * igb_write_phy_reg_igp - Write igp PHY register ++ * e1000_write_phy_reg_m88 - Write m88 PHY register + * @hw: pointer to the HW structure + * @offset: register offset to write to + * @data: data to write at register offset +@@ -292,55 +278,207 @@ + * Acquires semaphore, if necessary, then writes the data to PHY register + * at the offset. Release any acquired semaphores before exiting. + **/ +-s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) ++s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) + { +- s32 ret_val; ++ s32 ret_val = E1000_SUCCESS; + +- ret_val = igb_acquire_phy(hw); ++ DEBUGFUNC("e1000_write_phy_reg_m88"); ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); + if (ret_val) + goto out; + +- if (offset > MAX_PHY_MULTI_PAGE_REG) { +- ret_val = igb_write_phy_reg_mdic(hw, +- IGP01E1000_PHY_PAGE_SELECT, +- (u16)offset); +- if (ret_val) { +- igb_release_phy(hw); +- goto out; +- } +- } ++ ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); + +- ret_val = igb_write_phy_reg_mdic(hw, +- MAX_PHY_REG_ADDRESS & offset, +- data); +- +- igb_release_phy(hw); ++ hw->phy.ops.release(hw); + + out: + return ret_val; + } + + /** +- * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link ++ * e1000_read_phy_reg_igp - Read igp PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retrieved information in data. Release any acquired ++ * semaphores before exiting. ++ **/ ++s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_read_phy_reg_igp"); ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ ret_val = e1000_write_phy_reg_mdic(hw, ++ IGP01E1000_PHY_PAGE_SELECT, ++ (u16)offset); ++ if (ret_val) { ++ hw->phy.ops.release(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_phy_reg_igp - Write igp PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary, then writes the data to PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_write_phy_reg_igp"); ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ ret_val = e1000_write_phy_reg_mdic(hw, ++ IGP01E1000_PHY_PAGE_SELECT, ++ (u16)offset); ++ if (ret_val) { ++ hw->phy.ops.release(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_kmrn_reg_generic - Read kumeran register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary. Then reads the PHY register at offset ++ * using the kumeran interface. The information retrieved is stored in data. ++ * Release any acquired semaphores before exiting. ++ **/ ++s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ u32 kmrnctrlsta; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_read_kmrn_reg_generic"); ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & ++ E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; ++ E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); ++ ++ usec_delay(2); ++ ++ kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); ++ *data = (u16)kmrnctrlsta; ++ ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_kmrn_reg_generic - Write kumeran register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary. Then write the data to PHY register ++ * at the offset using the kumeran interface. Release any acquired semaphores ++ * before exiting. ++ **/ ++s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ u32 kmrnctrlsta; ++ s32 ret_val = E1000_SUCCESS; ++ ++ DEBUGFUNC("e1000_write_kmrn_reg_generic"); ++ ++ if (!(hw->phy.ops.acquire)) ++ goto out; ++ ++ ret_val = hw->phy.ops.acquire(hw); ++ if (ret_val) ++ goto out; ++ ++ kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & ++ E1000_KMRNCTRLSTA_OFFSET) | data; ++ E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); ++ ++ usec_delay(2); ++ hw->phy.ops.release(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link + * @hw: pointer to the HW structure + * + * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock + * and downshift values are set also. + **/ +-s32 igb_copper_link_setup_m88(struct e1000_hw *hw) ++s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data; + ++ DEBUGFUNC("e1000_copper_link_setup_m88"); ++ + if (phy->reset_disable) { +- ret_val = 0; ++ ret_val = E1000_SUCCESS; + goto out; + } + + /* Enable CRS on TX. This must be set for half-duplex operation. */ +- ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, +- &phy_data); ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + goto out; + +@@ -383,8 +521,7 @@ + if (phy->disable_polarity_correction == 1) + phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; + +- ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, +- phy_data); ++ ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + if (ret_val) + goto out; + +@@ -393,9 +530,8 @@ + * Force TX_CLK in the Extended PHY Specific Control Register + * to 25MHz clock. + */ +- ret_val = hw->phy.ops.read_phy_reg(hw, +- M88E1000_EXT_PHY_SPEC_CTRL, +- &phy_data); ++ ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, ++ &phy_data); + if (ret_val) + goto out; + +@@ -409,21 +545,20 @@ + } else { + /* Configure Master and Slave downshift values */ + phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | +- M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); ++ M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); + phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | +- M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); ++ M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); + } +- ret_val = hw->phy.ops.write_phy_reg(hw, +- M88E1000_EXT_PHY_SPEC_CTRL, +- phy_data); ++ ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, ++ phy_data); + if (ret_val) + goto out; + } + + /* Commit the changes. */ +- ret_val = igb_phy_sw_reset(hw); ++ ret_val = phy->ops.commit(hw); + if (ret_val) { +- hw_dbg("Error committing the PHY changes\n"); ++ DEBUGOUT("Error committing the PHY changes\n"); + goto out; + } + +@@ -432,31 +567,36 @@ + } + + /** +- * igb_copper_link_setup_igp - Setup igp PHY's for copper link ++ * e1000_copper_link_setup_igp - Setup igp PHY's for copper link + * @hw: pointer to the HW structure + * + * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for + * igp PHY's. + **/ +-s32 igb_copper_link_setup_igp(struct e1000_hw *hw) ++s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data; + ++ DEBUGFUNC("e1000_copper_link_setup_igp"); ++ + if (phy->reset_disable) { +- ret_val = 0; ++ ret_val = E1000_SUCCESS; + goto out; + } + +- ret_val = hw->phy.ops.reset_phy(hw); ++ ret_val = hw->phy.ops.reset(hw); + if (ret_val) { +- hw_dbg("Error resetting the PHY.\n"); ++ DEBUGOUT("Error resetting the PHY.\n"); + goto out; + } + +- /* Wait 15ms for MAC to configure PHY from NVM settings. */ +- msleep(15); ++ /* ++ * Wait 100ms for MAC to configure PHY from NVM settings, to avoid ++ * timeout issues when LFS is enabled. ++ */ ++ msec_delay(100); + + /* + * The NVM settings will configure LPLU in D3 for +@@ -464,22 +604,23 @@ + */ + if (phy->type == e1000_phy_igp) { + /* disable lplu d3 during driver init */ +- if (hw->phy.ops.set_d3_lplu_state) +- ret_val = hw->phy.ops.set_d3_lplu_state(hw, false); ++ ret_val = hw->phy.ops.set_d3_lplu_state(hw, false); + if (ret_val) { +- hw_dbg("Error Disabling LPLU D3\n"); ++ DEBUGOUT("Error Disabling LPLU D3\n"); + goto out; + } + } + + /* disable lplu d0 during driver init */ +- ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); +- if (ret_val) { +- hw_dbg("Error Disabling LPLU D0\n"); +- goto out; ++ if (hw->phy.ops.set_d0_lplu_state) { ++ ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); ++ if (ret_val) { ++ DEBUGOUT("Error Disabling LPLU D0\n"); ++ goto out; ++ } + } + /* Configure mdi-mdix settings */ +- ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); ++ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); + if (ret_val) + goto out; + +@@ -497,7 +638,7 @@ + data |= IGP01E1000_PSCR_AUTO_MDIX; + break; + } +- ret_val = hw->phy.ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); ++ ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); + if (ret_val) + goto out; + +@@ -510,33 +651,31 @@ + */ + if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { + /* Disable SmartSpeed */ +- ret_val = hw->phy.ops.read_phy_reg(hw, +- IGP01E1000_PHY_PORT_CONFIG, +- &data); ++ ret_val = phy->ops.read_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; +- ret_val = hw->phy.ops.write_phy_reg(hw, +- IGP01E1000_PHY_PORT_CONFIG, +- data); ++ ret_val = phy->ops.write_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); + if (ret_val) + goto out; + + /* Set auto Master/Slave resolution process */ +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_CTRL, +- &data); ++ ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); + if (ret_val) + goto out; + + data &= ~CR_1000T_MS_ENABLE; +- ret_val = hw->phy.ops.write_phy_reg(hw, PHY_1000T_CTRL, +- data); ++ ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); + if (ret_val) + goto out; + } + +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_CTRL, &data); ++ ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); + if (ret_val) + goto out; + +@@ -560,7 +699,7 @@ + default: + break; + } +- ret_val = hw->phy.ops.write_phy_reg(hw, PHY_1000T_CTRL, data); ++ ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); + if (ret_val) + goto out; + } +@@ -570,7 +709,7 @@ + } + + /** +- * igb_copper_link_autoneg - Setup/Enable autoneg for copper link ++ * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link + * @hw: pointer to the HW structure + * + * Performs initial bounds checking on autoneg advertisement parameter, then +@@ -578,11 +717,13 @@ + * and restart the negotiation process between the link partner. If + * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. + **/ +-s32 igb_copper_link_autoneg(struct e1000_hw *hw) ++s32 e1000_copper_link_autoneg(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_ctrl; ++ ++ DEBUGFUNC("e1000_copper_link_autoneg"); + + /* + * Perform some bounds checking on the autoneg advertisement +@@ -597,24 +738,24 @@ + if (phy->autoneg_advertised == 0) + phy->autoneg_advertised = phy->autoneg_mask; + +- hw_dbg("Reconfiguring auto-neg advertisement params\n"); +- ret_val = igb_phy_setup_autoneg(hw); ++ DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); ++ ret_val = e1000_phy_setup_autoneg(hw); + if (ret_val) { +- hw_dbg("Error Setting up Auto-Negotiation\n"); ++ DEBUGOUT("Error Setting up Auto-Negotiation\n"); + goto out; + } +- hw_dbg("Restarting Auto-Neg\n"); ++ DEBUGOUT("Restarting Auto-Neg\n"); + + /* + * Restart auto-negotiation by setting the Auto Neg Enable bit and + * the Auto Neg Restart bit in the PHY control register. + */ +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); ++ ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); + if (ret_val) + goto out; + + phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); +- ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_ctrl); ++ ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); + if (ret_val) + goto out; + +@@ -623,10 +764,10 @@ + * check at a later time (for example, callback routine). + */ + if (phy->autoneg_wait_to_complete) { +- ret_val = igb_wait_autoneg(hw); ++ ret_val = hw->mac.ops.wait_autoneg(hw); + if (ret_val) { +- hw_dbg("Error while waiting for " +- "autoneg to complete\n"); ++ DEBUGOUT("Error while waiting for " ++ "autoneg to complete\n"); + goto out; + } + } +@@ -638,7 +779,7 @@ + } + + /** +- * igb_phy_setup_autoneg - Configure PHY for auto-negotiation ++ * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation + * @hw: pointer to the HW structure + * + * Reads the MII auto-neg advertisement register and/or the 1000T control +@@ -646,26 +787,26 @@ + * return successful. Otherwise, setup advertisement and flow control to + * the appropriate values for the wanted auto-negotiation. + **/ +-static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) ++static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 mii_autoneg_adv_reg; + u16 mii_1000t_ctrl_reg = 0; + ++ DEBUGFUNC("e1000_phy_setup_autoneg"); ++ + phy->autoneg_advertised &= phy->autoneg_mask; + + /* Read the MII Auto-Neg Advertisement Register (Address 4). */ +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_AUTONEG_ADV, +- &mii_autoneg_adv_reg); ++ ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); + if (ret_val) + goto out; + + if (phy->autoneg_mask & ADVERTISE_1000_FULL) { + /* Read the MII 1000Base-T Control Register (Address 9). */ +- ret_val = hw->phy.ops.read_phy_reg(hw, +- PHY_1000T_CTRL, +- &mii_1000t_ctrl_reg); ++ ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, ++ &mii_1000t_ctrl_reg); + if (ret_val) + goto out; + } +@@ -684,44 +825,44 @@ + * the 1000Base-T Control Register (Address 9). + */ + mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | +- NWAY_AR_100TX_HD_CAPS | +- NWAY_AR_10T_FD_CAPS | +- NWAY_AR_10T_HD_CAPS); ++ NWAY_AR_100TX_HD_CAPS | ++ NWAY_AR_10T_FD_CAPS | ++ NWAY_AR_10T_HD_CAPS); + mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); + +- hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); ++ DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); + + /* Do we want to advertise 10 Mb Half Duplex? */ + if (phy->autoneg_advertised & ADVERTISE_10_HALF) { +- hw_dbg("Advertise 10mb Half duplex\n"); ++ DEBUGOUT("Advertise 10mb Half duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; + } + + /* Do we want to advertise 10 Mb Full Duplex? */ + if (phy->autoneg_advertised & ADVERTISE_10_FULL) { +- hw_dbg("Advertise 10mb Full duplex\n"); ++ DEBUGOUT("Advertise 10mb Full duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; + } + + /* Do we want to advertise 100 Mb Half Duplex? */ + if (phy->autoneg_advertised & ADVERTISE_100_HALF) { +- hw_dbg("Advertise 100mb Half duplex\n"); ++ DEBUGOUT("Advertise 100mb Half duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; + } + + /* Do we want to advertise 100 Mb Full Duplex? */ + if (phy->autoneg_advertised & ADVERTISE_100_FULL) { +- hw_dbg("Advertise 100mb Full duplex\n"); ++ DEBUGOUT("Advertise 100mb Full duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; + } + + /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ + if (phy->autoneg_advertised & ADVERTISE_1000_HALF) +- hw_dbg("Advertise 1000mb Half duplex request denied!\n"); ++ DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); + + /* Do we want to advertise 1000 Mb Full Duplex? */ + if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { +- hw_dbg("Advertise 1000mb Full duplex\n"); ++ DEBUGOUT("Advertise 1000mb Full duplex\n"); + mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; + } + +@@ -739,26 +880,26 @@ + * but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames + * but we do not support receiving pause frames). +- * 3: Both Rx and TX flow control (symmetric) are enabled. ++ * 3: Both Rx and Tx flow control (symmetric) are enabled. + * other: No software override. The flow control configuration + * in the EEPROM is used. + */ +- switch (hw->fc.type) { ++ switch (hw->fc.current_mode) { + case e1000_fc_none: + /* +- * Flow control (RX & TX) is completely disabled by a ++ * Flow control (Rx & Tx) is completely disabled by a + * software over-ride. + */ + mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + case e1000_fc_rx_pause: + /* +- * RX Flow control is enabled, and TX Flow control is ++ * Rx Flow control is enabled, and Tx Flow control is + * disabled, by a software over-ride. + * + * Since there really isn't a way to advertise that we are +- * capable of RX Pause ONLY, we will advertise that we +- * support both symmetric and asymmetric RX PAUSE. Later ++ * capable of Rx Pause ONLY, we will advertise that we ++ * support both symmetric and asymmetric Rx PAUSE. Later + * (in e1000_config_fc_after_link_up) we will disable the + * hw's ability to send PAUSE frames. + */ +@@ -766,7 +907,7 @@ + break; + case e1000_fc_tx_pause: + /* +- * TX Flow control is enabled, and RX Flow control is ++ * Tx Flow control is enabled, and Rx Flow control is + * disabled, by a software over-ride. + */ + mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; +@@ -774,28 +915,27 @@ + break; + case e1000_fc_full: + /* +- * Flow control (both RX and TX) is enabled by a software ++ * Flow control (both Rx and Tx) is enabled by a software + * over-ride. + */ + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + default: +- hw_dbg("Flow control param set incorrectly\n"); ++ DEBUGOUT("Flow control param set incorrectly\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + +- ret_val = hw->phy.ops.write_phy_reg(hw, PHY_AUTONEG_ADV, +- mii_autoneg_adv_reg); ++ ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); + if (ret_val) + goto out; + +- hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); ++ DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); + + if (phy->autoneg_mask & ADVERTISE_1000_FULL) { +- ret_val = hw->phy.ops.write_phy_reg(hw, +- PHY_1000T_CTRL, +- mii_1000t_ctrl_reg); ++ ret_val = phy->ops.write_reg(hw, ++ PHY_1000T_CTRL, ++ mii_1000t_ctrl_reg); + if (ret_val) + goto out; + } +@@ -805,27 +945,89 @@ + } + + /** +- * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY ++ * e1000_setup_copper_link_generic - Configure copper link settings ++ * @hw: pointer to the HW structure ++ * ++ * Calls the appropriate function to configure the link for auto-neg or forced ++ * speed and duplex. Then we check for link, once link is established calls ++ * to configure collision distance and flow control are called. If link is ++ * not established, we return -E1000_ERR_PHY (-2). ++ **/ ++s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ bool link; ++ ++ DEBUGFUNC("e1000_setup_copper_link_generic"); ++ ++ if (hw->mac.autoneg) { ++ /* ++ * Setup autoneg and flow control advertisement and perform ++ * autonegotiation. ++ */ ++ ret_val = e1000_copper_link_autoneg(hw); ++ if (ret_val) ++ goto out; ++ } else { ++ /* ++ * PHY will be set to 10H, 10F, 100H or 100F ++ * depending on user settings. ++ */ ++ DEBUGOUT("Forcing Speed and Duplex\n"); ++ ret_val = hw->phy.ops.force_speed_duplex(hw); ++ if (ret_val) { ++ DEBUGOUT("Error Forcing Speed and Duplex\n"); ++ goto out; ++ } ++ } ++ ++ /* ++ * Check link status. Wait up to 100 microseconds for link to become ++ * valid. ++ */ ++ ret_val = e1000_phy_has_link_generic(hw, ++ COPPER_LINK_UP_LIMIT, ++ 10, ++ &link); ++ if (ret_val) ++ goto out; ++ ++ if (link) { ++ DEBUGOUT("Valid link established!!!\n"); ++ e1000_config_collision_dist_generic(hw); ++ ret_val = e1000_config_fc_after_link_up_generic(hw); ++ } else { ++ DEBUGOUT("Unable to establish link!!!\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY + * @hw: pointer to the HW structure + * + * Calls the PHY setup function to force speed and duplex. Clears the + * auto-crossover to force MDI manually. Waits for link and returns + * successful if link up is successful, else -E1000_ERR_PHY (-2). + **/ +-s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) ++s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data; + bool link; + +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data); ++ DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); ++ ++ ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); + if (ret_val) + goto out; + +- igb_phy_force_speed_duplex_setup(hw, &phy_data); ++ e1000_phy_force_speed_duplex_setup(hw, &phy_data); + +- ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_data); ++ ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); + if (ret_val) + goto out; + +@@ -833,41 +1035,39 @@ + * Clear Auto-Crossover to force MDI manually. IGP requires MDI + * forced whenever speed and duplex are forced. + */ +- ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, +- &phy_data); ++ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); + if (ret_val) + goto out; + + phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; + phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; + +- ret_val = hw->phy.ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, +- phy_data); ++ ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); + if (ret_val) + goto out; + +- hw_dbg("IGP PSCR: %X\n", phy_data); ++ DEBUGOUT1("IGP PSCR: %X\n", phy_data); + +- udelay(1); ++ usec_delay(1); + + if (phy->autoneg_wait_to_complete) { +- hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); ++ DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); + +- ret_val = igb_phy_has_link(hw, +- PHY_FORCE_LIMIT, +- 100000, +- &link); ++ ret_val = e1000_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); + if (ret_val) + goto out; + + if (!link) +- hw_dbg("Link taking longer than expected.\n"); ++ DEBUGOUT("Link taking longer than expected.\n"); + + /* Try once more */ +- ret_val = igb_phy_has_link(hw, +- PHY_FORCE_LIMIT, +- 100000, +- &link); ++ ret_val = e1000_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); + if (ret_val) + goto out; + } +@@ -877,61 +1077,59 @@ + } + + /** +- * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY ++ * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY + * @hw: pointer to the HW structure + * + * Calls the PHY setup function to force speed and duplex. Clears the + * auto-crossover to force MDI manually. Resets the PHY to commit the + * changes. If time expires while waiting for link up, we reset the DSP. +- * After reset, TX_CLK and CRS on TX must be set. Return successful upon ++ * After reset, TX_CLK and CRS on Tx must be set. Return successful upon + * successful completion, else return corresponding error code. + **/ +-s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) ++s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data; + bool link; + ++ DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); ++ + /* + * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI + * forced whenever speed and duplex are forced. + */ +- ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, +- &phy_data); ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + goto out; + + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; +- ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, +- phy_data); ++ ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + if (ret_val) + goto out; + +- hw_dbg("M88E1000 PSCR: %X\n", phy_data); ++ DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); + +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data); ++ ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); + if (ret_val) + goto out; + +- igb_phy_force_speed_duplex_setup(hw, &phy_data); ++ e1000_phy_force_speed_duplex_setup(hw, &phy_data); + +- /* Reset the phy to commit changes. */ +- phy_data |= MII_CR_RESET; +- +- ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_data); ++ ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); + if (ret_val) + goto out; + +- udelay(1); ++ /* Reset the phy to commit changes. */ ++ ret_val = hw->phy.ops.commit(hw); ++ if (ret_val) ++ goto out; + + if (phy->autoneg_wait_to_complete) { +- hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); ++ DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); + +- ret_val = igb_phy_has_link(hw, +- PHY_FORCE_LIMIT, +- 100000, +- &link); ++ ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ 100000, &link); + if (ret_val) + goto out; + +@@ -940,25 +1138,24 @@ + * We didn't get link. + * Reset the DSP and cross our fingers. + */ +- ret_val = hw->phy.ops.write_phy_reg(hw, +- M88E1000_PHY_PAGE_SELECT, +- 0x001d); ++ ret_val = phy->ops.write_reg(hw, ++ M88E1000_PHY_PAGE_SELECT, ++ 0x001d); + if (ret_val) + goto out; +- ret_val = igb_phy_reset_dsp(hw); ++ ret_val = e1000_phy_reset_dsp_generic(hw); + if (ret_val) + goto out; + } + + /* Try once more */ +- ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, +- 100000, &link); ++ ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ 100000, &link); + if (ret_val) + goto out; + } + +- ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, +- &phy_data); ++ ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + goto out; + +@@ -968,8 +1165,7 @@ + * the reset value of 2.5MHz. + */ + phy_data |= M88E1000_EPSCR_TX_CLK_25; +- ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, +- phy_data); ++ ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); + if (ret_val) + goto out; + +@@ -977,21 +1173,93 @@ + * In addition, we must re-enable CRS on Tx for both half and full + * duplex. + */ +- ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, +- &phy_data); ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + goto out; + + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; +- ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, +- phy_data); ++ ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + + out: + return ret_val; + } + + /** +- * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex ++ * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex ++ * @hw: pointer to the HW structure ++ * ++ * Forces the speed and duplex settings of the PHY. ++ * This is a function pointer entry point only called by ++ * PHY setup routines. ++ **/ ++s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ bool link; ++ ++ DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); ++ ++ if (phy->type != e1000_phy_ife) { ++ ret_val = e1000_phy_force_speed_duplex_igp(hw); ++ goto out; ++ } ++ ++ ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); ++ if (ret_val) ++ goto out; ++ ++ e1000_phy_force_speed_duplex_setup(hw, &data); ++ ++ ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); ++ if (ret_val) ++ goto out; ++ ++ /* Disable MDI-X support for 10/100 */ ++ ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IFE_PMC_AUTO_MDIX; ++ data &= ~IFE_PMC_FORCE_MDIX; ++ ++ ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); ++ if (ret_val) ++ goto out; ++ ++ DEBUGOUT1("IFE PMC: %X\n", data); ++ ++ usec_delay(1); ++ ++ if (phy->autoneg_wait_to_complete) { ++ DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); ++ ++ ret_val = e1000_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) ++ DEBUGOUT("Link taking longer than expected.\n"); ++ ++ /* Try once more */ ++ ret_val = e1000_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex + * @hw: pointer to the HW structure + * @phy_ctrl: pointer to current value of PHY_CONTROL + * +@@ -1002,17 +1270,18 @@ + * caller must write to the PHY_CONTROL register for these settings to + * take affect. + **/ +-static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, +- u16 *phy_ctrl) ++void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) + { + struct e1000_mac_info *mac = &hw->mac; + u32 ctrl; + ++ DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); ++ + /* Turn off flow control when forcing speed/duplex */ +- hw->fc.type = e1000_fc_none; ++ hw->fc.current_mode = e1000_fc_none; + + /* Force speed/duplex on the mac */ +- ctrl = rd32(E1000_CTRL); ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + ctrl &= ~E1000_CTRL_SPD_SEL; + +@@ -1026,11 +1295,11 @@ + if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { + ctrl &= ~E1000_CTRL_FD; + *phy_ctrl &= ~MII_CR_FULL_DUPLEX; +- hw_dbg("Half Duplex\n"); ++ DEBUGOUT("Half Duplex\n"); + } else { + ctrl |= E1000_CTRL_FD; + *phy_ctrl |= MII_CR_FULL_DUPLEX; +- hw_dbg("Full Duplex\n"); ++ DEBUGOUT("Full Duplex\n"); + } + + /* Forcing 10mb or 100mb? */ +@@ -1038,21 +1307,21 @@ + ctrl |= E1000_CTRL_SPD_100; + *phy_ctrl |= MII_CR_SPEED_100; + *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); +- hw_dbg("Forcing 100mb\n"); ++ DEBUGOUT("Forcing 100mb\n"); + } else { + ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); + *phy_ctrl |= MII_CR_SPEED_10; + *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); +- hw_dbg("Forcing 10mb\n"); ++ DEBUGOUT("Forcing 10mb\n"); + } + +- igb_config_collision_dist(hw); ++ e1000_config_collision_dist_generic(hw); + +- wr32(E1000_CTRL, ctrl); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + } + + /** +- * igb_set_d3_lplu_state - Sets low power link up state for D3 ++ * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 + * @hw: pointer to the HW structure + * @active: boolean used to enable/disable lplu + * +@@ -1065,22 +1334,25 @@ + * During driver activity, SmartSpeed should be enabled so performance is + * maintained. + **/ +-s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) ++s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) + { + struct e1000_phy_info *phy = &hw->phy; +- s32 ret_val; ++ s32 ret_val = E1000_SUCCESS; + u16 data; + +- ret_val = hw->phy.ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, +- &data); ++ DEBUGFUNC("e1000_set_d3_lplu_state_generic"); ++ ++ if (!(hw->phy.ops.read_reg)) ++ goto out; ++ ++ ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); + if (ret_val) + goto out; + + if (!active) { + data &= ~IGP02E1000_PM_D3_LPLU; +- ret_val = hw->phy.ops.write_phy_reg(hw, +- IGP02E1000_PHY_POWER_MGMT, +- data); ++ ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, ++ data); + if (ret_val) + goto out; + /* +@@ -1090,53 +1362,50 @@ + * SmartSpeed, so performance is maintained. + */ + if (phy->smart_speed == e1000_smart_speed_on) { +- ret_val = hw->phy.ops.read_phy_reg(hw, +- IGP01E1000_PHY_PORT_CONFIG, +- &data); ++ ret_val = phy->ops.read_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); + if (ret_val) + goto out; + + data |= IGP01E1000_PSCFR_SMART_SPEED; +- ret_val = hw->phy.ops.write_phy_reg(hw, +- IGP01E1000_PHY_PORT_CONFIG, +- data); ++ ret_val = phy->ops.write_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); + if (ret_val) + goto out; + } else if (phy->smart_speed == e1000_smart_speed_off) { +- ret_val = hw->phy.ops.read_phy_reg(hw, +- IGP01E1000_PHY_PORT_CONFIG, +- &data); ++ ret_val = phy->ops.read_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; +- ret_val = hw->phy.ops.write_phy_reg(hw, +- IGP01E1000_PHY_PORT_CONFIG, +- data); ++ ret_val = phy->ops.write_reg(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); + if (ret_val) + goto out; + } + } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || +- (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || +- (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { ++ (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || ++ (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { + data |= IGP02E1000_PM_D3_LPLU; +- ret_val = hw->phy.ops.write_phy_reg(hw, +- IGP02E1000_PHY_POWER_MGMT, +- data); ++ ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, ++ data); + if (ret_val) + goto out; + + /* When LPLU is enabled, we should disable SmartSpeed */ +- ret_val = hw->phy.ops.read_phy_reg(hw, +- IGP01E1000_PHY_PORT_CONFIG, +- &data); ++ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ++ &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; +- ret_val = hw->phy.ops.write_phy_reg(hw, +- IGP01E1000_PHY_PORT_CONFIG, +- data); ++ ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ++ data); + } + + out: +@@ -1144,18 +1413,20 @@ + } + + /** +- * igb_check_downshift - Checks whether a downshift in speed occured ++ * e1000_check_downshift_generic - Checks whether a downshift in speed occurred + * @hw: pointer to the HW structure + * + * Success returns 0, Failure returns 1 + * + * A downshift is detected by querying the PHY link health. + **/ +-s32 igb_check_downshift(struct e1000_hw *hw) ++s32 e1000_check_downshift_generic(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data, offset, mask; ++ ++ DEBUGFUNC("e1000_check_downshift_generic"); + + switch (phy->type) { + case e1000_phy_m88: +@@ -1172,11 +1443,11 @@ + default: + /* speed downshift not supported */ + phy->speed_downgraded = false; +- ret_val = 0; ++ ret_val = E1000_SUCCESS; + goto out; + } + +- ret_val = hw->phy.ops.read_phy_reg(hw, offset, &phy_data); ++ ret_val = phy->ops.read_reg(hw, offset, &phy_data); + + if (!ret_val) + phy->speed_downgraded = (phy_data & mask) ? true : false; +@@ -1186,31 +1457,33 @@ + } + + /** +- * igb_check_polarity_m88 - Checks the polarity. ++ * e1000_check_polarity_m88 - Checks the polarity. + * @hw: pointer to the HW structure + * + * Success returns 0, Failure returns -E1000_ERR_PHY (-2) + * + * Polarity is determined based on the PHY specific status register. + **/ +-static s32 igb_check_polarity_m88(struct e1000_hw *hw) ++s32 e1000_check_polarity_m88(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data; + +- ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); ++ DEBUGFUNC("e1000_check_polarity_m88"); ++ ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); + + if (!ret_val) + phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) +- ? e1000_rev_polarity_reversed +- : e1000_rev_polarity_normal; ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; + + return ret_val; + } + + /** +- * igb_check_polarity_igp - Checks the polarity. ++ * e1000_check_polarity_igp - Checks the polarity. + * @hw: pointer to the HW structure + * + * Success returns 0, Failure returns -E1000_ERR_PHY (-2) +@@ -1218,18 +1491,19 @@ + * Polarity is determined based on the PHY port status register, and the + * current speed (since there is no polarity at 100Mbps). + **/ +-static s32 igb_check_polarity_igp(struct e1000_hw *hw) ++s32 e1000_check_polarity_igp(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data, offset, mask; + ++ DEBUGFUNC("e1000_check_polarity_igp"); ++ + /* + * Polarity is determined based on the speed of + * our connection. + */ +- ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, +- &data); ++ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); + if (ret_val) + goto out; + +@@ -1246,40 +1520,80 @@ + mask = IGP01E1000_PSSR_POLARITY_REVERSED; + } + +- ret_val = hw->phy.ops.read_phy_reg(hw, offset, &data); ++ ret_val = phy->ops.read_reg(hw, offset, &data); + + if (!ret_val) + phy->cable_polarity = (data & mask) +- ? e1000_rev_polarity_reversed +- : e1000_rev_polarity_normal; ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; + + out: + return ret_val; + } + + /** +- * igb_wait_autoneg - Wait for auto-neg compeletion ++ * e1000_check_polarity_ife - Check cable polarity for IFE PHY ++ * @hw: pointer to the HW structure ++ * ++ * Polarity is determined on the polarity reversal feature being enabled. ++ **/ ++s32 e1000_check_polarity_ife(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data, offset, mask; ++ ++ DEBUGFUNC("e1000_check_polarity_ife"); ++ ++ /* ++ * Polarity is determined based on the reversal feature being enabled. ++ */ ++ if (phy->polarity_correction) { ++ offset = IFE_PHY_EXTENDED_STATUS_CONTROL; ++ mask = IFE_PESC_POLARITY_REVERSED; ++ } else { ++ offset = IFE_PHY_SPECIAL_CONTROL; ++ mask = IFE_PSC_FORCE_POLARITY; ++ } ++ ++ ret_val = phy->ops.read_reg(hw, offset, &phy_data); ++ ++ if (!ret_val) ++ phy->cable_polarity = (phy_data & mask) ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_wait_autoneg_generic - Wait for auto-neg completion + * @hw: pointer to the HW structure + * + * Waits for auto-negotiation to complete or for the auto-negotiation time + * limit to expire, which ever happens first. + **/ +-static s32 igb_wait_autoneg(struct e1000_hw *hw) ++s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) + { +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + u16 i, phy_status; ++ ++ DEBUGFUNC("e1000_wait_autoneg_generic"); ++ ++ if (!(hw->phy.ops.read_reg)) ++ return E1000_SUCCESS; + + /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ + for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status); ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); + if (ret_val) + break; +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status); ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); + if (ret_val) + break; + if (phy_status & MII_SR_AUTONEG_COMPLETE) + break; +- msleep(100); ++ msec_delay(100); + } + + /* +@@ -1290,7 +1604,7 @@ + } + + /** +- * igb_phy_has_link - Polls PHY for link ++ * e1000_phy_has_link_generic - Polls PHY for link + * @hw: pointer to the HW structure + * @iterations: number of times to poll for link + * @usec_interval: delay between polling attempts +@@ -1298,11 +1612,16 @@ + * + * Polls the PHY status register for link, 'iterations' number of times. + **/ +-s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, +- u32 usec_interval, bool *success) ++s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, ++ u32 usec_interval, bool *success) + { +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + u16 i, phy_status; ++ ++ DEBUGFUNC("e1000_phy_has_link_generic"); ++ ++ if (!(hw->phy.ops.read_reg)) ++ return E1000_SUCCESS; + + for (i = 0; i < iterations; i++) { + /* +@@ -1310,18 +1629,24 @@ + * twice due to the link bit being sticky. No harm doing + * it across the board. + */ +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status); +- if (ret_val) +- break; +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status); ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); ++ if (ret_val) { ++ /* ++ * If the first read fails, another entity may have ++ * ownership of the resources, wait and try again to ++ * see if they have relinquished the resources yet. ++ */ ++ usec_delay(usec_interval); ++ } ++ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); + if (ret_val) + break; + if (phy_status & MII_SR_LINK_STATUS) + break; + if (usec_interval >= 1000) +- mdelay(usec_interval/1000); ++ msec_delay_irq(usec_interval/1000); + else +- udelay(usec_interval); ++ usec_delay(usec_interval); + } + + *success = (i < iterations) ? true : false; +@@ -1330,7 +1655,7 @@ + } + + /** +- * igb_get_cable_length_m88 - Determine cable length for m88 PHY ++ * e1000_get_cable_length_m88 - Determine cable length for m88 PHY + * @hw: pointer to the HW structure + * + * Reads the PHY specific status register to retrieve the cable length +@@ -1344,19 +1669,25 @@ + * 3 110 - 140 meters + * 4 > 140 meters + **/ +-s32 igb_get_cable_length_m88(struct e1000_hw *hw) ++s32 e1000_get_cable_length_m88(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data, index; + +- ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, +- &phy_data); ++ DEBUGFUNC("e1000_get_cable_length_m88"); ++ ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); + if (ret_val) + goto out; + + index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> +- M88E1000_PSSR_CABLE_LENGTH_SHIFT; ++ M88E1000_PSSR_CABLE_LENGTH_SHIFT; ++ if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE + 1) { ++ ret_val = E1000_ERR_PHY; ++ goto out; ++ } ++ + phy->min_cable_length = e1000_m88_cable_length_table[index]; + phy->max_cable_length = e1000_m88_cable_length_table[index+1]; + +@@ -1367,44 +1698,45 @@ + } + + /** +- * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY ++ * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY + * @hw: pointer to the HW structure + * + * The automatic gain control (agc) normalizes the amplitude of the + * received signal, adjusting for the attenuation produced by the +- * cable. By reading the AGC registers, which reperesent the +- * cobination of course and fine gain value, the value can be put ++ * cable. By reading the AGC registers, which represent the ++ * combination of coarse and fine gain value, the value can be put + * into a lookup table to obtain the approximate cable length + * for each channel. + **/ +-s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) ++s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; +- s32 ret_val = 0; ++ s32 ret_val = E1000_SUCCESS; + u16 phy_data, i, agc_value = 0; + u16 cur_agc_index, max_agc_index = 0; + u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; + u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = +- {IGP02E1000_PHY_AGC_A, +- IGP02E1000_PHY_AGC_B, +- IGP02E1000_PHY_AGC_C, +- IGP02E1000_PHY_AGC_D}; ++ {IGP02E1000_PHY_AGC_A, ++ IGP02E1000_PHY_AGC_B, ++ IGP02E1000_PHY_AGC_C, ++ IGP02E1000_PHY_AGC_D}; ++ ++ DEBUGFUNC("e1000_get_cable_length_igp_2"); + + /* Read the AGC registers for all channels */ + for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { +- ret_val = hw->phy.ops.read_phy_reg(hw, agc_reg_array[i], +- &phy_data); ++ ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); + if (ret_val) + goto out; + + /* + * Getting bits 15:9, which represent the combination of +- * course and fine gain values. The result is a number ++ * coarse and fine gain values. The result is a number + * that can be put into the lookup table to obtain the + * approximate cable length. + */ + cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & +- IGP02E1000_AGC_LENGTH_MASK; ++ IGP02E1000_AGC_LENGTH_MASK; + + /* Array index bound check. */ + if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || +@@ -1425,12 +1757,12 @@ + } + + agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + +- e1000_igp_2_cable_length_table[max_agc_index]); ++ e1000_igp_2_cable_length_table[max_agc_index]); + agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); + + /* Calculate cable length with the error range of +/- 10 meters. */ + phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? +- (agc_value - IGP02E1000_AGC_RANGE) : 0; ++ (agc_value - IGP02E1000_AGC_RANGE) : 0; + phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; + + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; +@@ -1440,7 +1772,7 @@ + } + + /** +- * igb_get_phy_info_m88 - Retrieve PHY information ++ * e1000_get_phy_info_m88 - Retrieve PHY information + * @hw: pointer to the HW structure + * + * Valid for only copper links. Read the PHY status register (sticky read) +@@ -1449,44 +1781,43 @@ + * special status register to determine MDI/MDIx and current speed. If + * speed is 1000, then determine cable length, local and remote receiver. + **/ +-s32 igb_get_phy_info_m88(struct e1000_hw *hw) ++s32 e1000_get_phy_info_m88(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data; + bool link; + ++ DEBUGFUNC("e1000_get_phy_info_m88"); ++ + if (hw->phy.media_type != e1000_media_type_copper) { +- hw_dbg("Phy info is only valid for copper media\n"); ++ DEBUGOUT("Phy info is only valid for copper media\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + +- ret_val = igb_phy_has_link(hw, 1, 0, &link); ++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + goto out; + + if (!link) { +- hw_dbg("Phy info is only valid if link is up\n"); ++ DEBUGOUT("Phy info is only valid if link is up\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + +- ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, +- &phy_data); ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + goto out; + + phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) +- ? true +- : false; ++ ? true : false; + +- ret_val = igb_check_polarity_m88(hw); ++ ret_val = e1000_check_polarity_m88(hw); + if (ret_val) + goto out; + +- ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, +- &phy_data); ++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); + if (ret_val) + goto out; + +@@ -1497,18 +1828,17 @@ + if (ret_val) + goto out; + +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS, +- &phy_data); ++ ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); + if (ret_val) + goto out; + + phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) +- ? e1000_1000t_rx_status_ok +- : e1000_1000t_rx_status_not_ok; ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; + + phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) +- ? e1000_1000t_rx_status_ok +- : e1000_1000t_rx_status_not_ok; ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; + } else { + /* Set values to "undefined" */ + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; +@@ -1521,7 +1851,7 @@ + } + + /** +- * igb_get_phy_info_igp - Retrieve igp PHY information ++ * e1000_get_phy_info_igp - Retrieve igp PHY information + * @hw: pointer to the HW structure + * + * Read PHY status to determine if link is up. If link is up, then +@@ -1529,31 +1859,32 @@ + * PHY port status to determine MDI/MDIx and speed. Based on the speed, + * determine on the cable length, local and remote receiver. + **/ +-s32 igb_get_phy_info_igp(struct e1000_hw *hw) ++s32 e1000_get_phy_info_igp(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data; + bool link; + +- ret_val = igb_phy_has_link(hw, 1, 0, &link); ++ DEBUGFUNC("e1000_get_phy_info_igp"); ++ ++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + goto out; + + if (!link) { +- hw_dbg("Phy info is only valid if link is up\n"); ++ DEBUGOUT("Phy info is only valid if link is up\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + phy->polarity_correction = true; + +- ret_val = igb_check_polarity_igp(hw); ++ ret_val = e1000_check_polarity_igp(hw); + if (ret_val) + goto out; + +- ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, +- &data); ++ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); + if (ret_val) + goto out; + +@@ -1565,18 +1896,17 @@ + if (ret_val) + goto out; + +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS, +- &data); ++ ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); + if (ret_val) + goto out; + + phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) +- ? e1000_1000t_rx_status_ok +- : e1000_1000t_rx_status_not_ok; ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; + + phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) +- ? e1000_1000t_rx_status_ok +- : e1000_1000t_rx_status_not_ok; ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; + } else { + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; + phy->local_rx = e1000_1000t_rx_status_undefined; +@@ -1588,218 +1918,297 @@ + } + + /** +- * igb_phy_sw_reset - PHY software reset ++ * e1000_phy_sw_reset_generic - PHY software reset + * @hw: pointer to the HW structure + * + * Does a software reset of the PHY by reading the PHY control register and + * setting/write the control register reset bit to the PHY. + **/ +-s32 igb_phy_sw_reset(struct e1000_hw *hw) ++s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) + { +- s32 ret_val; ++ s32 ret_val = E1000_SUCCESS; + u16 phy_ctrl; + +- ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); ++ DEBUGFUNC("e1000_phy_sw_reset_generic"); ++ ++ if (!(hw->phy.ops.read_reg)) ++ goto out; ++ ++ ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); + if (ret_val) + goto out; + + phy_ctrl |= MII_CR_RESET; +- ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_ctrl); ++ ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); + if (ret_val) + goto out; + +- udelay(1); ++ usec_delay(1); + + out: + return ret_val; + } + + /** +- * igb_phy_hw_reset - PHY hardware reset ++ * e1000_phy_hw_reset_generic - PHY hardware reset + * @hw: pointer to the HW structure + * + * Verify the reset block is not blocking us from resetting. Acquire + * semaphore (if necessary) and read/set/write the device control reset + * bit in the PHY. Wait the appropriate delay time for the device to +- * reset and relase the semaphore (if necessary). ++ * reset and release the semaphore (if necessary). + **/ +-s32 igb_phy_hw_reset(struct e1000_hw *hw) ++s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; +- s32 ret_val; ++ s32 ret_val = E1000_SUCCESS; + u32 ctrl; + +- ret_val = igb_check_reset_block(hw); ++ DEBUGFUNC("e1000_phy_hw_reset_generic"); ++ ++ ret_val = phy->ops.check_reset_block(hw); + if (ret_val) { +- ret_val = 0; ++ ret_val = E1000_SUCCESS; + goto out; + } + +- ret_val = igb_acquire_phy(hw); ++ ret_val = phy->ops.acquire(hw); + if (ret_val) + goto out; + +- ctrl = rd32(E1000_CTRL); +- wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); +- wrfl(); ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); ++ E1000_WRITE_FLUSH(hw); + +- udelay(phy->reset_delay_us); ++ usec_delay(phy->reset_delay_us); + +- wr32(E1000_CTRL, ctrl); +- wrfl(); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ E1000_WRITE_FLUSH(hw); + +- udelay(150); ++ usec_delay(150); + +- igb_release_phy(hw); ++ phy->ops.release(hw); + +- ret_val = igb_get_phy_cfg_done(hw); ++ ret_val = phy->ops.get_cfg_done(hw); + + out: + return ret_val; + } + +-/* Internal function pointers */ +- + /** +- * igb_get_phy_cfg_done - Generic PHY configuration done ++ * e1000_get_cfg_done_generic - Generic configuration done + * @hw: pointer to the HW structure + * +- * Return success if silicon family did not implement a family specific +- * get_cfg_done function. ++ * Generic function to wait 10 milli-seconds for configuration to complete ++ * and return success. + **/ +-static s32 igb_get_phy_cfg_done(struct e1000_hw *hw) ++s32 e1000_get_cfg_done_generic(struct e1000_hw *hw) + { +- if (hw->phy.ops.get_cfg_done) +- return hw->phy.ops.get_cfg_done(hw); ++ DEBUGFUNC("e1000_get_cfg_done_generic"); + +- return 0; ++ msec_delay_irq(10); ++ ++ return E1000_SUCCESS; + } + + /** +- * igb_release_phy - Generic release PHY +- * @hw: pointer to the HW structure +- * +- * Return if silicon family does not require a semaphore when accessing the +- * PHY. +- **/ +-static void igb_release_phy(struct e1000_hw *hw) +-{ +- if (hw->phy.ops.release_phy) +- hw->phy.ops.release_phy(hw); +-} +- +-/** +- * igb_acquire_phy - Generic acquire PHY +- * @hw: pointer to the HW structure +- * +- * Return success if silicon family does not require a semaphore when +- * accessing the PHY. +- **/ +-static s32 igb_acquire_phy(struct e1000_hw *hw) +-{ +- if (hw->phy.ops.acquire_phy) +- return hw->phy.ops.acquire_phy(hw); +- +- return 0; +-} +- +-/** +- * igb_phy_force_speed_duplex - Generic force PHY speed/duplex +- * @hw: pointer to the HW structure +- * +- * When the silicon family has not implemented a forced speed/duplex +- * function for the PHY, simply return 0. +- **/ +-s32 igb_phy_force_speed_duplex(struct e1000_hw *hw) +-{ +- if (hw->phy.ops.force_speed_duplex) +- return hw->phy.ops.force_speed_duplex(hw); +- +- return 0; +-} +- +-/** +- * igb_phy_init_script_igp3 - Inits the IGP3 PHY ++ * e1000_phy_init_script_igp3 - Inits the IGP3 PHY + * @hw: pointer to the HW structure + * + * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. + **/ +-s32 igb_phy_init_script_igp3(struct e1000_hw *hw) ++s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) + { +- hw_dbg("Running IGP 3 PHY init script\n"); ++ DEBUGOUT("Running IGP 3 PHY init script\n"); + + /* PHY init IGP 3 */ + /* Enable rise/fall, 10-mode work in class-A */ +- hw->phy.ops.write_phy_reg(hw, 0x2F5B, 0x9018); ++ hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); + /* Remove all caps from Replica path filter */ +- hw->phy.ops.write_phy_reg(hw, 0x2F52, 0x0000); ++ hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); + /* Bias trimming for ADC, AFE and Driver (Default) */ +- hw->phy.ops.write_phy_reg(hw, 0x2FB1, 0x8B24); ++ hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); + /* Increase Hybrid poly bias */ +- hw->phy.ops.write_phy_reg(hw, 0x2FB2, 0xF8F0); +- /* Add 4% to TX amplitude in Giga mode */ +- hw->phy.ops.write_phy_reg(hw, 0x2010, 0x10B0); ++ hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); ++ /* Add 4% to Tx amplitude in Gig mode */ ++ hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); + /* Disable trimming (TTT) */ +- hw->phy.ops.write_phy_reg(hw, 0x2011, 0x0000); ++ hw->phy.ops.write_reg(hw, 0x2011, 0x0000); + /* Poly DC correction to 94.6% + 2% for all channels */ +- hw->phy.ops.write_phy_reg(hw, 0x20DD, 0x249A); ++ hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); + /* ABS DC correction to 95.9% */ +- hw->phy.ops.write_phy_reg(hw, 0x20DE, 0x00D3); ++ hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); + /* BG temp curve trim */ +- hw->phy.ops.write_phy_reg(hw, 0x28B4, 0x04CE); ++ hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); + /* Increasing ADC OPAMP stage 1 currents to max */ +- hw->phy.ops.write_phy_reg(hw, 0x2F70, 0x29E4); ++ hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); + /* Force 1000 ( required for enabling PHY regs configuration) */ +- hw->phy.ops.write_phy_reg(hw, 0x0000, 0x0140); ++ hw->phy.ops.write_reg(hw, 0x0000, 0x0140); + /* Set upd_freq to 6 */ +- hw->phy.ops.write_phy_reg(hw, 0x1F30, 0x1606); ++ hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); + /* Disable NPDFE */ +- hw->phy.ops.write_phy_reg(hw, 0x1F31, 0xB814); ++ hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); + /* Disable adaptive fixed FFE (Default) */ +- hw->phy.ops.write_phy_reg(hw, 0x1F35, 0x002A); ++ hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); + /* Enable FFE hysteresis */ +- hw->phy.ops.write_phy_reg(hw, 0x1F3E, 0x0067); ++ hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); + /* Fixed FFE for short cable lengths */ +- hw->phy.ops.write_phy_reg(hw, 0x1F54, 0x0065); ++ hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); + /* Fixed FFE for medium cable lengths */ +- hw->phy.ops.write_phy_reg(hw, 0x1F55, 0x002A); ++ hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); + /* Fixed FFE for long cable lengths */ +- hw->phy.ops.write_phy_reg(hw, 0x1F56, 0x002A); ++ hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); + /* Enable Adaptive Clip Threshold */ +- hw->phy.ops.write_phy_reg(hw, 0x1F72, 0x3FB0); ++ hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); + /* AHT reset limit to 1 */ +- hw->phy.ops.write_phy_reg(hw, 0x1F76, 0xC0FF); ++ hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); + /* Set AHT master delay to 127 msec */ +- hw->phy.ops.write_phy_reg(hw, 0x1F77, 0x1DEC); ++ hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); + /* Set scan bits for AHT */ +- hw->phy.ops.write_phy_reg(hw, 0x1F78, 0xF9EF); ++ hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); + /* Set AHT Preset bits */ +- hw->phy.ops.write_phy_reg(hw, 0x1F79, 0x0210); ++ hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); + /* Change integ_factor of channel A to 3 */ +- hw->phy.ops.write_phy_reg(hw, 0x1895, 0x0003); ++ hw->phy.ops.write_reg(hw, 0x1895, 0x0003); + /* Change prop_factor of channels BCD to 8 */ +- hw->phy.ops.write_phy_reg(hw, 0x1796, 0x0008); ++ hw->phy.ops.write_reg(hw, 0x1796, 0x0008); + /* Change cg_icount + enable integbp for channels BCD */ +- hw->phy.ops.write_phy_reg(hw, 0x1798, 0xD008); ++ hw->phy.ops.write_reg(hw, 0x1798, 0xD008); + /* + * Change cg_icount + enable integbp + change prop_factor_master + * to 8 for channel A + */ +- hw->phy.ops.write_phy_reg(hw, 0x1898, 0xD918); ++ hw->phy.ops.write_reg(hw, 0x1898, 0xD918); + /* Disable AHT in Slave mode on channel A */ +- hw->phy.ops.write_phy_reg(hw, 0x187A, 0x0800); ++ hw->phy.ops.write_reg(hw, 0x187A, 0x0800); + /* + * Enable LPLU and disable AN to 1000 in non-D0a states, + * Enable SPD+B2B + */ +- hw->phy.ops.write_phy_reg(hw, 0x0019, 0x008D); ++ hw->phy.ops.write_reg(hw, 0x0019, 0x008D); + /* Enable restart AN on an1000_dis change */ +- hw->phy.ops.write_phy_reg(hw, 0x001B, 0x2080); ++ hw->phy.ops.write_reg(hw, 0x001B, 0x2080); + /* Enable wh_fifo read clock in 10/100 modes */ +- hw->phy.ops.write_phy_reg(hw, 0x0014, 0x0045); ++ hw->phy.ops.write_reg(hw, 0x0014, 0x0045); + /* Restart AN, Speed selection is 1000 */ +- hw->phy.ops.write_phy_reg(hw, 0x0000, 0x1340); ++ hw->phy.ops.write_reg(hw, 0x0000, 0x1340); + +- return 0; ++ return E1000_SUCCESS; + } + ++/** ++ * e1000_get_phy_type_from_id - Get PHY type from id ++ * @phy_id: phy_id read from the phy ++ * ++ * Returns the phy type from the id. ++ **/ ++enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) ++{ ++ enum e1000_phy_type phy_type = e1000_phy_unknown; ++ ++ switch (phy_id) { ++ case M88E1000_I_PHY_ID: ++ case M88E1000_E_PHY_ID: ++ case M88E1111_I_PHY_ID: ++ case M88E1011_I_PHY_ID: ++ phy_type = e1000_phy_m88; ++ break; ++ case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ ++ phy_type = e1000_phy_igp_2; ++ break; ++ case GG82563_E_PHY_ID: ++ phy_type = e1000_phy_gg82563; ++ break; ++ case IGP03E1000_E_PHY_ID: ++ phy_type = e1000_phy_igp_3; ++ break; ++ case IFE_E_PHY_ID: ++ case IFE_PLUS_E_PHY_ID: ++ case IFE_C_E_PHY_ID: ++ phy_type = e1000_phy_ife; ++ break; ++ default: ++ phy_type = e1000_phy_unknown; ++ break; ++ } ++ return phy_type; ++} ++ ++/** ++ * e1000_determine_phy_address - Determines PHY address. ++ * @hw: pointer to the HW structure ++ * ++ * This uses a trial and error method to loop through possible PHY ++ * addresses. It tests each by reading the PHY ID registers and ++ * checking for a match. ++ **/ ++s32 e1000_determine_phy_address(struct e1000_hw *hw) ++{ ++ s32 ret_val = -E1000_ERR_PHY_TYPE; ++ u32 phy_addr = 0; ++ u32 i; ++ enum e1000_phy_type phy_type = e1000_phy_unknown; ++ ++ hw->phy.id = phy_type; ++ ++ for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { ++ hw->phy.addr = phy_addr; ++ i = 0; ++ ++ do { ++ e1000_get_phy_id(hw); ++ phy_type = e1000_get_phy_type_from_id(hw->phy.id); ++ ++ /* ++ * If phy_type is valid, break - we found our ++ * PHY address ++ */ ++ if (phy_type != e1000_phy_unknown) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ msec_delay(1); ++ i++; ++ } while (i < 10); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_power_up_phy_copper - Restore copper link in case of PHY power down ++ * @hw: pointer to the HW structure ++ * ++ * In the case of a PHY power down to save power, or to turn off link during a ++ * driver unload, or wake on lan is not enabled, restore the link to previous ++ * settings. ++ **/ ++void e1000_power_up_phy_copper(struct e1000_hw *hw) ++{ ++ u16 mii_reg = 0; ++ ++ /* The PHY will retain its settings across a power down/up cycle */ ++ hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); ++ mii_reg &= ~MII_CR_POWER_DOWN; ++ hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); ++} ++ ++/** ++ * e1000_power_down_phy_copper - Restore copper link in case of PHY power down ++ * @hw: pointer to the HW structure ++ * ++ * In the case of a PHY power down to save power, or to turn off link during a ++ * driver unload, or wake on lan is not enabled, restore the link to previous ++ * settings. ++ **/ ++void e1000_power_down_phy_copper(struct e1000_hw *hw) ++{ ++ u16 mii_reg = 0; ++ ++ /* The PHY will retain its settings across a power down/up cycle */ ++ hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); ++ mii_reg |= MII_CR_POWER_DOWN; ++ hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); ++ msec_delay(1); ++} +diff -r 4f0f8bc35440 drivers/net/igb/e1000_phy.h +--- a/drivers/net/igb/e1000_phy.h Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/e1000_phy.h Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -28,71 +28,130 @@ + #ifndef _E1000_PHY_H_ + #define _E1000_PHY_H_ + +-enum e1000_ms_type { +- e1000_ms_hw_default = 0, +- e1000_ms_force_master, +- e1000_ms_force_slave, +- e1000_ms_auto +-}; ++void e1000_init_phy_ops_generic(struct e1000_hw *hw); ++s32 e1000_check_downshift_generic(struct e1000_hw *hw); ++s32 e1000_check_polarity_m88(struct e1000_hw *hw); ++s32 e1000_check_polarity_igp(struct e1000_hw *hw); ++s32 e1000_check_polarity_ife(struct e1000_hw *hw); ++s32 e1000_check_reset_block_generic(struct e1000_hw *hw); ++s32 e1000_copper_link_autoneg(struct e1000_hw *hw); ++s32 e1000_copper_link_setup_igp(struct e1000_hw *hw); ++s32 e1000_copper_link_setup_m88(struct e1000_hw *hw); ++s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw); ++s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw); ++s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); ++s32 e1000_get_cable_length_m88(struct e1000_hw *hw); ++s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw); ++s32 e1000_get_cfg_done_generic(struct e1000_hw *hw); ++s32 e1000_get_phy_id(struct e1000_hw *hw); ++s32 e1000_get_phy_info_igp(struct e1000_hw *hw); ++s32 e1000_get_phy_info_m88(struct e1000_hw *hw); ++s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw); ++void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); ++s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw); ++s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw); ++s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active); ++s32 e1000_setup_copper_link_generic(struct e1000_hw *hw); ++s32 e1000_wait_autoneg_generic(struct e1000_hw *hw); ++s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); ++s32 e1000_phy_reset_dsp(struct e1000_hw *hw); ++s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, ++ u32 usec_interval, bool *success); ++s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); ++enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id); ++s32 e1000_determine_phy_address(struct e1000_hw *hw); ++void e1000_power_up_phy_copper(struct e1000_hw *hw); ++void e1000_power_down_phy_copper(struct e1000_hw *hw); ++s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); ++s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); + +-enum e1000_smart_speed { +- e1000_smart_speed_default = 0, +- e1000_smart_speed_on, +- e1000_smart_speed_off +-}; +- +-s32 igb_check_downshift(struct e1000_hw *hw); +-s32 igb_check_reset_block(struct e1000_hw *hw); +-s32 igb_copper_link_autoneg(struct e1000_hw *hw); +-s32 igb_phy_force_speed_duplex(struct e1000_hw *hw); +-s32 igb_copper_link_setup_igp(struct e1000_hw *hw); +-s32 igb_copper_link_setup_m88(struct e1000_hw *hw); +-s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw); +-s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw); +-s32 igb_get_cable_length_m88(struct e1000_hw *hw); +-s32 igb_get_cable_length_igp_2(struct e1000_hw *hw); +-s32 igb_get_phy_id(struct e1000_hw *hw); +-s32 igb_get_phy_info_igp(struct e1000_hw *hw); +-s32 igb_get_phy_info_m88(struct e1000_hw *hw); +-s32 igb_phy_sw_reset(struct e1000_hw *hw); +-s32 igb_phy_hw_reset(struct e1000_hw *hw); +-s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); +-s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active); +-s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); +-s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, +- u32 usec_interval, bool *success); +-s32 igb_phy_init_script_igp3(struct e1000_hw *hw); ++#define E1000_MAX_PHY_ADDR 4 + + /* IGP01E1000 Specific Registers */ + #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ + #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ + #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ + #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ ++#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ ++#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ + #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ + #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ ++#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ ++#define IGP_PAGE_SHIFT 5 ++#define PHY_REG_MASK 0x1F ++ + #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 + #define IGP01E1000_PHY_POLARITY_MASK 0x0078 ++ + #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 + #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ ++ + #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 + + /* Enable flexible speed on link-up */ ++#define IGP01E1000_GMII_FLEX_SPD 0x0010 ++#define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */ ++ ++#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ + #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ + #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ ++ + #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 ++ + #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 +-#define IGP01E1000_PSSR_MDIX 0x0008 ++#define IGP01E1000_PSSR_MDIX 0x0800 + #define IGP01E1000_PSSR_SPEED_MASK 0xC000 + #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 ++ + #define IGP02E1000_PHY_CHANNEL_NUM 4 + #define IGP02E1000_PHY_AGC_A 0x11B1 + #define IGP02E1000_PHY_AGC_B 0x12B1 + #define IGP02E1000_PHY_AGC_C 0x14B1 + #define IGP02E1000_PHY_AGC_D 0x18B1 ++ + #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ + #define IGP02E1000_AGC_LENGTH_MASK 0x7F + #define IGP02E1000_AGC_RANGE 15 + ++#define IGP03E1000_PHY_MISC_CTRL 0x1B ++#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */ ++ + #define E1000_CABLE_LENGTH_UNDEFINED 0xFF + ++#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 ++#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 ++#define E1000_KMRNCTRLSTA_REN 0x00200000 ++#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ ++#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ ++#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ ++#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ ++ ++#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 ++#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */ ++#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */ ++#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ ++ ++/* IFE PHY Extended Status Control */ ++#define IFE_PESC_POLARITY_REVERSED 0x0100 ++ ++/* IFE PHY Special Control */ ++#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 ++#define IFE_PSC_FORCE_POLARITY 0x0020 ++#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 ++ ++/* IFE PHY Special Control and LED Control */ ++#define IFE_PSCL_PROBE_MODE 0x0020 ++#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ ++#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ ++ ++/* IFE PHY MDIX Control */ ++#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ ++#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ ++#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */ ++ + #endif +diff -r 4f0f8bc35440 drivers/net/igb/e1000_regs.h +--- a/drivers/net/igb/e1000_regs.h Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/e1000_regs.h Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -29,14 +29,18 @@ + #define _E1000_REGS_H_ + + #define E1000_CTRL 0x00000 /* Device Control - RW */ ++#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ + #define E1000_STATUS 0x00008 /* Device Status - RO */ + #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ + #define E1000_EERD 0x00014 /* EEPROM Read - RW */ + #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ ++#define E1000_FLA 0x0001C /* Flash Access - RW */ + #define E1000_MDIC 0x00020 /* MDI Control - RW */ + #define E1000_SCTL 0x00024 /* SerDes Control - RW */ + #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ + #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ ++#define E1000_FEXT 0x0002C /* Future Extended - RW */ ++#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ + #define E1000_FCT 0x00030 /* Flow Control Type - RW */ + #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ + #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ +@@ -46,9 +50,10 @@ + #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ + #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ + #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ +-#define E1000_RCTL 0x00100 /* RX Control - RW */ ++#define E1000_RCTL 0x00100 /* Rx Control - RW */ + #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ +-#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ ++#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ ++#define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ + #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ + #define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) + #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ +@@ -59,23 +64,59 @@ + #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */ + #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ + #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ +-#define E1000_TCTL 0x00400 /* TX Control - RW */ +-#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ +-#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ ++#define E1000_TCTL 0x00400 /* Tx Control - RW */ ++#define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */ ++#define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */ ++#define E1000_TBT 0x00448 /* Tx Burst Timer - RW */ + #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ + #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ ++#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ ++#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ ++#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ + #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ + #define E1000_PBS 0x01008 /* Packet Buffer Size */ + #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ ++#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ ++#define E1000_FLASHT 0x01028 /* FLASH Timer Register */ + #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ ++#define E1000_FLSWCTL 0x01030 /* FLASH control register */ ++#define E1000_FLSWDATA 0x01034 /* FLASH data register */ ++#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ ++#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ + #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */ ++#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */ ++#define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */ ++#define E1000_SWDSTS 0x01044 /* SW Device Status - RW */ + #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */ + #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ ++#define E1000_VPDDIAG 0x01060 /* VPD Diagnostic - RO */ ++#define E1000_ICR_V2 0x01500 /* Interrupt Cause - new location - RC */ ++#define E1000_ICS_V2 0x01504 /* Interrupt Cause Set - new location - WO */ ++#define E1000_IMS_V2 0x01508 /* Interrupt Mask Set/Read - new location - RW */ ++#define E1000_IMC_V2 0x0150C /* Interrupt Mask Clear - new location - WO */ ++#define E1000_IAM_V2 0x01510 /* Interrupt Ack Auto Mask - new location - RW */ ++#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ + #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ + #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ ++#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ + #define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n))) ++#define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */ + #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ +-/* Split and Replication RX Control - RW */ ++/* Split and Replication Rx Control - RW */ ++#define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */ ++#define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */ ++#define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */ ++#define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */ ++#define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */ ++#define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */ ++#define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ ++#define E1000_RXCTL(_n) (0x0C014 + (0x40 * (_n))) ++#define E1000_RQDPC(_n) (0x0C030 + (0x40 * (_n))) ++#define E1000_TXCTL(_n) (0x0E014 + (0x40 * (_n))) ++#define E1000_RXCTL(_n) (0x0C014 + (0x40 * (_n))) ++#define E1000_RQDPC(_n) (0x0C030 + (0x40 * (_n))) ++#define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ ++#define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ + /* + * Convenience macros + * +@@ -84,44 +125,74 @@ + * Example usage: + * E1000_RDBAL_REG(current_rx_queue) + */ +-#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) \ +- : (0x0C000 + ((_n) * 0x40))) +-#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) \ +- : (0x0C004 + ((_n) * 0x40))) +-#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) \ +- : (0x0C008 + ((_n) * 0x40))) +-#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) \ +- : (0x0C00C + ((_n) * 0x40))) +-#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) \ +- : (0x0C010 + ((_n) * 0x40))) +-#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) \ +- : (0x0C018 + ((_n) * 0x40))) +-#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) \ +- : (0x0C028 + ((_n) * 0x40))) +-#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) \ +- : (0x0E000 + ((_n) * 0x40))) +-#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) \ +- : (0x0E004 + ((_n) * 0x40))) +-#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) \ +- : (0x0E008 + ((_n) * 0x40))) +-#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) \ +- : (0x0E010 + ((_n) * 0x40))) +-#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) \ +- : (0x0E018 + ((_n) * 0x40))) +-#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \ +- : (0x0E028 + ((_n) * 0x40))) +-#define E1000_TARC(_n) (0x03840 + (_n << 8)) ++#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \ ++ (0x0C000 + ((_n) * 0x40))) ++#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ ++ (0x0C004 + ((_n) * 0x40))) ++#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ ++ (0x0C008 + ((_n) * 0x40))) ++#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \ ++ (0x0C00C + ((_n) * 0x40))) ++#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ ++ (0x0C010 + ((_n) * 0x40))) ++#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ ++ (0x0C018 + ((_n) * 0x40))) ++#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ ++ (0x0C028 + ((_n) * 0x40))) ++#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ ++ (0x0E000 + ((_n) * 0x40))) ++#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ ++ (0x0E004 + ((_n) * 0x40))) ++#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ ++ (0x0E008 + ((_n) * 0x40))) ++#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ ++ (0x0E010 + ((_n) * 0x40))) ++#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ ++ (0x0E018 + ((_n) * 0x40))) ++#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ ++ (0x0E028 + ((_n) * 0x40))) ++#define E1000_TARC(_n) (0x03840 + (_n << 8)) + #define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) + #define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) +-#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \ +- : (0x0E038 + ((_n) * 0x40))) +-#define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) \ +- : (0x0E03C + ((_n) * 0x40))) +-#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ +-#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ +-#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ +-#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ +-#define E1000_DTXCTL 0x03590 /* DMA TX Control - RW */ ++#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \ ++ (0x0E038 + ((_n) * 0x40))) ++#define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \ ++ (0x0E03C + ((_n) * 0x40))) ++#define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */ ++#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ ++#define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */ ++#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ ++#define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) ++#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ ++ (0x054E0 + ((_i - 16) * 8))) ++#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ ++ (0x054E4 + ((_i - 16) * 8))) ++#define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) ++#define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) ++#define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) ++#define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) ++#define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) ++#define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) ++#define E1000_PBSLAC 0x03100 /* Packet Buffer Slave Access Control */ ++#define E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n))) /* Packet Buffer DWORD (_n) */ ++#define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */ ++#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ ++#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ ++#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ ++#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ ++#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ ++#define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */ ++#define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */ ++#define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */ ++#define E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */ ++#define E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */ ++#define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */ ++#define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */ ++#define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */ ++#define E1000_DTXMXSZRQ 0x03540 /* DMA Tx Max Total Allow Size Requests - RW */ ++#define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */ ++#define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */ ++#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ + #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ + #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ + #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ +@@ -133,142 +204,267 @@ + #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ + #define E1000_COLC 0x04028 /* Collision Count - R/clr */ + #define E1000_DC 0x04030 /* Defer Count - R/clr */ +-#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ ++#define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */ + #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ + #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ + #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ +-#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ +-#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ +-#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ +-#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ +-#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ +-#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ +-#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ +-#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ +-#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ +-#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ +-#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ +-#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ +-#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ +-#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ +-#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ +-#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ +-#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ +-#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ +-#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ +-#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ +-#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ +-#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ +-#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ +-#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ +-#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ ++#define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */ ++#define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */ ++#define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */ ++#define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */ ++#define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */ ++#define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */ ++#define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */ ++#define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */ ++#define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */ ++#define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */ ++#define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */ ++#define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */ ++#define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */ ++#define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */ ++#define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */ ++#define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */ ++#define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */ ++#define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */ ++#define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */ ++#define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */ ++#define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */ ++#define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */ ++#define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */ ++#define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */ ++#define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */ + #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ +-#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ +-#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ +-#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ +-#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ +-#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ +-#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ +-#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ +-#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ +-#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ +-#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ +-#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ +-#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ +-#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ +-#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ +-#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ +-#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ +-#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ ++#define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */ ++#define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */ ++#define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */ ++#define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */ ++#define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */ ++#define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */ ++#define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */ ++#define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */ ++#define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */ ++#define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */ ++#define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */ ++#define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */ ++#define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */ ++#define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */ ++#define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */ ++#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */ ++#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */ + #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ +-/* Interrupt Cause Rx Packet Timer Expire Count */ +-#define E1000_ICRXPTC 0x04104 +-/* Interrupt Cause Rx Absolute Timer Expire Count */ +-#define E1000_ICRXATC 0x04108 +-/* Interrupt Cause Tx Packet Timer Expire Count */ +-#define E1000_ICTXPTC 0x0410C +-/* Interrupt Cause Tx Absolute Timer Expire Count */ +-#define E1000_ICTXATC 0x04110 +-/* Interrupt Cause Tx Queue Empty Count */ +-#define E1000_ICTXQEC 0x04118 +-/* Interrupt Cause Tx Queue Minimum Threshold Count */ +-#define E1000_ICTXQMTC 0x0411C +-/* Interrupt Cause Rx Descriptor Minimum Threshold Count */ +-#define E1000_ICRXDMTC 0x04120 ++#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ ++#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ ++#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ ++#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ ++#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ ++#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ ++#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ + #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ ++ ++#define E1000_LSECTXUT 0x04300 /* LinkSec Tx Untagged Packet Count - OutPktsUntagged */ ++#define E1000_LSECTXPKTE 0x04304 /* LinkSec Encrypted Tx Packets Count - OutPktsEncrypted */ ++#define E1000_LSECTXPKTP 0x04308 /* LinkSec Protected Tx Packet Count - OutPktsProtected */ ++#define E1000_LSECTXOCTE 0x0430C /* LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted */ ++#define E1000_LSECTXOCTP 0x04310 /* LinkSec Protected Tx Octets Count - OutOctetsProtected */ ++#define E1000_LSECRXUT 0x04314 /* LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag */ ++#define E1000_LSECRXOCTD 0x0431C /* LinkSec Rx Octets Decrypted Count - InOctetsDecrypted */ ++#define E1000_LSECRXOCTV 0x04320 /* LinkSec Rx Octets Validated - InOctetsValidated */ ++#define E1000_LSECRXBAD 0x04324 /* LinkSec Rx Bad Tag - InPktsBadTag */ ++#define E1000_LSECRXNOSCI 0x04328 /* LinkSec Rx Packet No SCI Count - InPktsNoSci */ ++#define E1000_LSECRXUNSCI 0x0432C /* LinkSec Rx Packet Unknown SCI Count - InPktsUnknownSci */ ++#define E1000_LSECRXUNCH 0x04330 /* LinkSec Rx Unchecked Packets Count - InPktsUnchecked */ ++#define E1000_LSECRXDELAY 0x04340 /* LinkSec Rx Delayed Packet Count - InPktsDelayed */ ++#define E1000_LSECRXLATE 0x04350 /* LinkSec Rx Late Packets Count - InPktsLate */ ++#define E1000_LSECRXOK(_n) (0x04360 + (0x04 * (_n))) /* LinkSec Rx Packet OK Count - InPktsOk */ ++#define E1000_LSECRXINV(_n) (0x04380 + (0x04 * (_n))) /* LinkSec Rx Invalid Count - InPktsInvalid */ ++#define E1000_LSECRXNV(_n) (0x043A0 + (0x04 * (_n))) /* LinkSec Rx Not Valid Count - InPktsNotValid */ ++#define E1000_LSECRXUNSA 0x043C0 /* LinkSec Rx Unused SA Count - InPktsUnusedSa */ ++#define E1000_LSECRXNUSA 0x043D0 /* LinkSec Rx Not Using SA Count - InPktsNotUsingSa */ ++#define E1000_LSECTXCAP 0x0B000 /* LinkSec Tx Capabilities Register - RO */ ++#define E1000_LSECRXCAP 0x0B300 /* LinkSec Rx Capabilities Register - RO */ ++#define E1000_LSECTXCTRL 0x0B004 /* LinkSec Tx Control - RW */ ++#define E1000_LSECRXCTRL 0x0B304 /* LinkSec Rx Control - RW */ ++#define E1000_LSECTXSCL 0x0B008 /* LinkSec Tx SCI Low - RW */ ++#define E1000_LSECTXSCH 0x0B00C /* LinkSec Tx SCI High - RW */ ++#define E1000_LSECTXSA 0x0B010 /* LinkSec Tx SA0 - RW */ ++#define E1000_LSECTXPN0 0x0B018 /* LinkSec Tx SA PN 0 - RW */ ++#define E1000_LSECTXPN1 0x0B01C /* LinkSec Tx SA PN 1 - RW */ ++#define E1000_LSECRXSCL 0x0B3D0 /* LinkSec Rx SCI Low - RW */ ++#define E1000_LSECRXSCH 0x0B3E0 /* LinkSec Rx SCI High - RW */ ++#define E1000_LSECTXKEY0(_n) (0x0B020 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 0 - WO */ ++#define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 1 - WO */ ++#define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */ ++#define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */ ++/* ++ * LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit ++ * key - RW. ++ */ ++#define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m))) ++ ++#define E1000_SSVPC 0x041A0 /* Switch Security Violation Packet Count */ ++#define E1000_IPSCTRL 0xB430 /* IpSec Control Register */ ++#define E1000_IPSRXCMD 0x0B408 /* IPSec Rx Command Register - RW */ ++#define E1000_IPSRXIDX 0x0B400 /* IPSec Rx Index - RW */ ++#define E1000_IPSRXIPADDR(_n) (0x0B420+ (0x04 * (_n))) /* IPSec Rx IPv4/v6 Address - RW */ ++#define E1000_IPSRXKEY(_n) (0x0B410 + (0x04 * (_n))) /* IPSec Rx 128-bit Key - RW */ ++#define E1000_IPSRXSALT 0x0B404 /* IPSec Rx Salt - RW */ ++#define E1000_IPSRXSPI 0x0B40C /* IPSec Rx SPI - RW */ ++#define E1000_IPSTXKEY(_n) (0x0B460 + (0x04 * (_n))) /* IPSec Tx 128-bit Key - RW */ ++#define E1000_IPSTXSALT 0x0B454 /* IPSec Tx Salt - RW */ ++#define E1000_IPSTXIDX 0x0B450 /* IPSec Tx SA IDX - RW */ + #define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ + #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ + #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ +-#define E1000_CBTMPC 0x0402C /* Circuit Breaker TX Packet Count */ ++#define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */ + #define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */ +-#define E1000_CBRMPC 0x040FC /* Circuit Breaker RX Packet Count */ ++#define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */ ++#define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */ + #define E1000_RPTHC 0x04104 /* Rx Packets To Host */ +-#define E1000_HGPTC 0x04118 /* Host Good Packets TX Count */ +-#define E1000_HTCBDPC 0x04124 /* Host TX Circuit Breaker Dropped Count */ ++#define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */ ++#define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */ + #define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */ + #define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */ + #define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */ + #define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */ + #define E1000_LENERRS 0x04138 /* Length Errors Count */ + #define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */ ++#define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */ + #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ + #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ + #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ + #define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */ +-#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ +-#define E1000_RLPML 0x05004 /* RX Long Packet Max Length */ ++#define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Packet Count - RW */ ++#define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */ ++#define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */ + #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ + #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ + #define E1000_RA 0x05400 /* Receive Address - RW Array */ + #define E1000_RA2 0x054E0 /* 2nd half of receive address array - RW Array */ + #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ +-#define E1000_VMD_CTL 0x0581C /* VMDq Control - RW */ ++#define E1000_VT_CTL 0x0581C /* VMDq Control - RW */ ++#define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */ ++#define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */ + #define E1000_WUC 0x05800 /* Wakeup Control - RW */ + #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ + #define E1000_WUS 0x05810 /* Wakeup Status - RO */ + #define E1000_MANC 0x05820 /* Management Control - RW */ + #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ ++#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ ++#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ + #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ ++#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ ++#define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */ ++#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ + #define E1000_HOST_IF 0x08800 /* Host Interface */ ++#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ ++#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ ++#define E1000_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flexible Host Filter Table */ ++#define E1000_FHFT_EXT(_n) (0x09A00 + (_n * 0x100)) /* Ext Flexible Host Filter Table */ + ++ ++#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ ++#define E1000_MDPHYA 0x0003C /* PHY address - RW */ + #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ + #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ + #define E1000_CCMCTL 0x05B48 /* CCM Control Register */ + #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ + #define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ ++#define E1000_GCR 0x05B00 /* PCI-Ex Control */ ++#define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ ++#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ ++#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ ++#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ ++#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ + #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ + #define E1000_SWSM 0x05B50 /* SW Semaphore */ + #define E1000_FWSM 0x05B54 /* FW Semaphore */ ++#define E1000_SWSM2 0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */ + #define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ + #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ +-#define E1000_HICR 0x08F00 /* Host Inteface Control */ ++#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ ++#define E1000_HICR 0x08F00 /* Host Interface Control */ + + /* RSS registers */ ++#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ + #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ + #define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ + #define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/ +-#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */ +-/* MSI-X Allocation Register (_i) - RW */ +-#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) +-/* MSI-X Table entry addr low reg 0 - RW */ +-#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) +-/* MSI-X Table entry addr upper reg 0 - RW */ +-#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) +-/* MSI-X Table entry message reg 0 - RW */ +-#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) +-/* MSI-X Table entry vector ctrl reg 0 - RW */ +-#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) +-/* Redirection Table - RW Array */ +-#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) +-#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ ++#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */ ++#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register ++ * (_i) - RW */ ++#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr ++ * low reg - RW */ ++#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr ++ * upper reg - RW */ ++#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry ++ * message reg - RW */ ++#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry ++ * vector ctrl reg - RW */ ++#define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */ ++#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ ++#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ ++#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ ++#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ ++/* VT Registers */ ++#define E1000_SWPBS 0x03004 /* Switch Packet Buffer Size - RW */ ++#define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */ ++#define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */ ++#define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */ ++#define E1000_VFRE 0x00C8C /* VF Receive Enables */ ++#define E1000_VFTE 0x00C90 /* VF Transmit Enables */ ++#define E1000_QDE 0x02408 /* Queue Drop Enable - RW */ ++#define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */ ++#define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */ ++#define E1000_UTA 0x0A000 /* Unicast Table Array - RW */ ++#define E1000_IOVTCL 0x05BBC /* IOV Control Register */ ++#define E1000_VMRCTL 0X05D80 /* Virtual Mirror Rule Control */ ++/* These act per VF so an array friendly macro is used */ ++#define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n))) ++#define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n))) ++#define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) ++#define E1000_VFVMBMEM(_n) (0x00800 + (_n)) ++#define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n))) ++#define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) /* VLAN Virtual Machine ++ * Filter - RW */ + +-#define wr32(reg, value) (writel(value, hw->hw_addr + reg)) +-#define rd32(reg) (readl(hw->hw_addr + reg)) +-#define wrfl() ((void)rd32(E1000_STATUS)) ++/* Filtering Registers */ ++#define E1000_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */ ++#define E1000_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */ ++#define E1000_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */ ++#define E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */ ++#define E1000_TTQF(_n) (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */ ++#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */ ++#define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */ + +-#define array_wr32(reg, offset, value) \ +- (writel(value, hw->hw_addr + reg + ((offset) << 2))) +-#define array_rd32(reg, offset) \ +- (readl(hw->hw_addr + reg + ((offset) << 2))) ++#define E1000_RTTDCS 0x3600 /* Reedtown Tx Desc plane control and status */ ++#define E1000_RTTPCS 0x3474 /* Reedtown Tx Packet Plane control and status */ ++#define E1000_RTRPCS 0x2474 /* Rx packet plane control and status */ ++#define E1000_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */ ++#define E1000_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class */ ++#define E1000_RTTDTCRC(_n) (0x3610 + ((_n) * 4)) /* Tx Desc plane TC Rate-scheduler config */ ++#define E1000_RTTPTCRC(_n) (0x3480 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Config */ ++#define E1000_RTRPTCRC(_n) (0x2480 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Config */ ++#define E1000_RTTDTCRS(_n) (0x3630 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler Status */ ++#define E1000_RTTDTCRM(_n) (0x3650 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler MMW */ ++#define E1000_RTTPTCRS(_n) (0x34A0 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Status */ ++#define E1000_RTTPTCRM(_n) (0x34C0 + ((_n) * 4)) /* Tx Packet plane TC Rate-scheduler MMW */ ++#define E1000_RTRPTCRS(_n) (0x24A0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Status */ ++#define E1000_RTRPTCRM(_n) (0x24C0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler MMW */ ++#define E1000_RTTDVMRM(_n) (0x3670 + ((_n) * 4)) /* Tx Desc plane VM Rate-Scheduler MMW*/ ++#define E1000_RTTBCNRM(_n) (0x3690 + ((_n) * 4)) /* Tx BCN Rate-Scheduler MMW */ ++#define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select */ ++#define E1000_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */ ++#define E1000_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */ ++#define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config */ ++#define E1000_RTTBCNRS 0x36B4 /* Tx BCN Rate-Scheduler Status */ ++#define E1000_RTTBCNCR 0xB200 /* Tx BCN Control Register */ ++#define E1000_RTTBCNTG 0x35A4 /* Tx BCN Tagging */ ++#define E1000_RTTBCNCP 0xB208 /* Tx BCN Congestion point */ ++#define E1000_RTRBCNCR 0xB20C /* Rx BCN Control Register */ ++#define E1000_RTTBCNRD 0x36B8 /* Tx BCN Rate Drift */ ++#define E1000_PFCTOP 0x1080 /* Priority Flow Control Type and Opcode */ ++#define E1000_RTTBCNIDX 0xB204 /* Tx BCN Congestion Point */ ++#define E1000_RTTBCNACH 0x0B214 /* Tx BCN Control High */ ++#define E1000_RTTBCNACL 0x0B210 /* Tx BCN Control Low */ + + #endif +diff -r 4f0f8bc35440 drivers/net/igb/igb.h +--- a/drivers/net/igb/igb.h Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/igb.h Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -31,30 +31,57 @@ + #ifndef _IGB_H_ + #define _IGB_H_ + +-#include "e1000_mac.h" +-#include "e1000_82575.h" ++#include ++#include ++#include ++ ++#ifdef SIOCETHTOOL ++#include ++#endif + + struct igb_adapter; + +-#ifdef CONFIG_IGB_LRO +-#include +-#define MAX_LRO_AGGR 32 +-#define MAX_LRO_DESCRIPTORS 8 ++#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) ++#define IGB_DCA ++#endif ++#ifdef IGB_DCA ++#include + #endif + ++#ifdef IGB_LRO ++#undef IGB_LRO ++#ifdef NETIF_F_LRO ++#if defined(CONFIG_INET_LRO) || defined(CONFIG_INET_LRO_MODULE) ++#include ++#define MAX_LRO_DESCRIPTORS 8 ++#define IGB_LRO ++#endif ++#endif ++#endif /* IGB_LRO */ ++ ++#include "kcompat.h" ++ ++#include "e1000_api.h" ++#include "e1000_82575.h" ++ ++#define IGB_ERR(args...) printk(KERN_ERR "igb: " args) ++ ++#define PFX "igb: " ++#define DPRINTK(nlevel, klevel, fmt, args...) \ ++ (void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \ ++ printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \ ++ __FUNCTION__ , ## args)) ++ + /* Interrupt defines */ +-#define IGB_MAX_TX_CLEAN 72 ++#define IGB_START_ITR 648 /* ~6000 ints/sec */ + +-#define IGB_MIN_DYN_ITR 3000 +-#define IGB_MAX_DYN_ITR 96000 ++/* Interrupt modes, as used by the IntMode paramter */ ++#define IGB_INT_MODE_LEGACY 0 ++#define IGB_INT_MODE_MSI 1 ++#define IGB_INT_MODE_MSIX_1Q 2 ++#define IGB_INT_MODE_MSIX_MQ 3 + +-/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */ +-#define IGB_START_ITR 648 +- +-#define IGB_DYN_ITR_PACKET_THRESHOLD 2 +-#define IGB_DYN_ITR_LENGTH_LOW 200 +-#define IGB_DYN_ITR_LENGTH_HIGH 1000 +- ++#define HW_PERF + /* TX/RX descriptor defines */ + #define IGB_DEFAULT_TXD 256 + #define IGB_MIN_TXD 80 +@@ -64,13 +91,18 @@ + #define IGB_MIN_RXD 80 + #define IGB_MAX_RXD 4096 + +-#define IGB_DEFAULT_ITR 3 /* dynamic */ +-#define IGB_MAX_ITR_USECS 10000 +-#define IGB_MIN_ITR_USECS 10 ++#define IGB_MIN_ITR_USECS 10 /* 100k irq/sec */ ++#define IGB_MAX_ITR_USECS 10000 /* 100 irq/sec */ + + /* Transmit and receive queues */ ++#ifndef CONFIG_IGB_SEPARATE_TX_HANDLER ++#define IGB_MAX_RX_QUEUES (hw->mac.type > e1000_82575 ? 8 : 4) ++#define IGB_ABS_MAX_TX_QUEUES 8 ++#else /* CONFIG_IGB_SEPARATE_TX_HANDLER */ + #define IGB_MAX_RX_QUEUES 4 +-#define IGB_MAX_TX_QUEUES 4 ++#define IGB_ABS_MAX_TX_QUEUES 4 ++#endif /* CONFIG_IGB_SEPARATE_TX_HANDLER */ ++#define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES + + /* RX descriptor control thresholds. + * PTHRESH - MAC will consider prefetch if it has fewer than this number of +@@ -101,10 +133,14 @@ + #define IGB_RXBUFFER_16384 16384 + + /* Packet Buffer allocations */ ++#define IGB_PBA_BYTES_SHIFT 0xA ++#define IGB_TX_HEAD_ADDR_SHIFT 7 ++#define IGB_PBA_TX_MASK 0xFFFF0000 + ++#define IGB_FC_PAUSE_TIME 0x0680 /* 858 usec */ + + /* How many Tx Descriptors do we need to call netif_wake_queue ? */ +-#define IGB_TX_QUEUE_WAKE 16 ++#define IGB_TX_QUEUE_WAKE 32 + /* How many Rx Buffers do we bundle into one write to the hardware ? */ + #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ + +@@ -123,18 +159,22 @@ + struct igb_buffer { + struct sk_buff *skb; + dma_addr_t dma; ++ dma_addr_t page_dma; + union { + /* TX */ + struct { + unsigned long time_stamp; +- u32 length; ++ u16 length; ++ u16 next_to_watch; + }; ++ ++#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT + /* RX */ + struct { ++ unsigned long page_offset; + struct page *page; +- u64 page_dma; +- unsigned int page_offset; + }; ++#endif + }; + }; + +@@ -160,10 +200,13 @@ + u16 itr_register; + u16 cpu; + +- int queue_index; ++ u16 queue_index; ++ u16 reg_idx; ++ + unsigned int total_bytes; + unsigned int total_packets; + ++ char name[IFNAMSIZ + 9]; + union { + /* TX */ + struct { +@@ -176,15 +219,14 @@ + struct napi_struct napi; + int set_itr; + struct igb_ring *buddy; +-#ifdef CONFIG_IGB_LRO ++#ifdef IGB_LRO + struct net_lro_mgr lro_mgr; + bool lro_used; + #endif + }; + }; ++}; + +- char name[IFNAMSIZ + 5]; +-}; + + #define IGB_DESC_UNUSED(R) \ + ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ +@@ -200,6 +242,7 @@ + #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) + #define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc) + ++#define MAX_MSIX_COUNT 10 + /* board specific private data structure */ + + struct igb_adapter { +@@ -213,6 +256,7 @@ + u32 en_mng_pt; + u16 link_speed; + u16 link_duplex; ++ + unsigned int total_tx_bytes; + unsigned int total_tx_packets; + unsigned int total_rx_bytes; +@@ -227,18 +271,16 @@ + struct work_struct watchdog_task; + bool fc_autoneg; + u8 tx_timeout_factor; ++#ifdef ETHTOOL_PHYS_ID + struct timer_list blink_timer; + unsigned long led_status; ++#endif + + /* TX */ + struct igb_ring *tx_ring; /* One per active queue */ + unsigned int restart_queue; + unsigned long tx_queue_len; + u32 txd_cmd; +- u32 gotc; +- u64 gotc_old; +- u64 tpt_old; +- u64 colc_old; + u32 tx_timeout_count; + + /* RX */ +@@ -248,18 +290,13 @@ + + u64 hw_csum_err; + u64 hw_csum_good; +- u64 rx_hdr_split; + u32 alloc_rx_buff_failed; +- bool rx_csum; +- u32 gorc; +- u64 gorc_old; + u16 rx_ps_hdr_size; + u32 max_frame_size; + u32 min_frame_size; + + /* OS defined structs */ + struct net_device *netdev; +- struct napi_struct napi; + struct pci_dev *pdev; + struct net_device_stats net_stats; + +@@ -269,26 +306,29 @@ + struct e1000_phy_info phy_info; + struct e1000_phy_stats phy_stats; + ++#ifdef ETHTOOL_TEST + u32 test_icr; + struct igb_ring test_tx_ring; + struct igb_ring test_rx_ring; ++#endif ++ + + int msg_enable; + struct msix_entry *msix_entries; ++ int int_mode; + u32 eims_enable_mask; + u32 eims_other; +- +- /* to not mess up cache alignment, always add to the bottom */ ++ u32 lli_port; ++ u32 lli_size; ++ u64 lli_int; + unsigned long state; + unsigned int flags; + u32 eeprom_wol; +- +- /* for ioport free */ +- int bars; +- int need_ioport; +- +- struct igb_ring *multi_tx_table[IGB_MAX_TX_QUEUES]; +-#ifdef CONFIG_IGB_LRO ++ u32 *config_space; ++#ifdef HAVE_TX_MQ ++ struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES]; ++#endif /* HAVE_TX_MQ */ ++#ifdef IGB_LRO + unsigned int lro_max_aggr; + unsigned int lro_aggregated; + unsigned int lro_flushed; +@@ -298,13 +338,16 @@ + unsigned int rx_ring_count; + }; + ++ + #define IGB_FLAG_HAS_MSI (1 << 0) + #define IGB_FLAG_MSI_ENABLE (1 << 1) + #define IGB_FLAG_HAS_DCA (1 << 2) + #define IGB_FLAG_DCA_ENABLED (1 << 3) ++#define IGB_FLAG_LLI_PUSH (1 << 4) + #define IGB_FLAG_IN_NETPOLL (1 << 5) + #define IGB_FLAG_QUAD_PORT_A (1 << 6) + #define IGB_FLAG_NEED_CTX_IDX (1 << 7) ++#define IGB_FLAG_RX_CSUM_DISABLED (1 << 8) + + enum e1000_state_t { + __IGB_TESTING, +@@ -312,14 +355,9 @@ + __IGB_DOWN + }; + +-enum igb_boards { +- board_82575, +-}; +- + extern char igb_driver_name[]; + extern char igb_driver_version[]; + +-extern char *igb_get_hw_dev_name(struct e1000_hw *hw); + extern int igb_up(struct igb_adapter *); + extern void igb_down(struct igb_adapter *); + extern void igb_reinit_locked(struct igb_adapter *); +@@ -331,5 +369,9 @@ + extern void igb_free_rx_resources(struct igb_ring *); + extern void igb_update_stats(struct igb_adapter *); + extern void igb_set_ethtool_ops(struct net_device *); ++extern void igb_check_options(struct igb_adapter *); ++#ifdef ETHTOOL_OPS_COMPAT ++extern int ethtool_ioctl(struct ifreq *); ++#endif + + #endif /* _IGB_H_ */ +diff -r 4f0f8bc35440 drivers/net/igb/igb_ethtool.c +--- a/drivers/net/igb/igb_ethtool.c Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/igb_ethtool.c Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -27,23 +27,28 @@ + + /* ethtool support for igb */ + ++#include + #include +-#include +-#include +-#include +-#include +-#include ++ ++#ifdef SIOCETHTOOL + #include + + #include "igb.h" ++#include "igb_regtest.h" ++#include + ++#ifdef ETHTOOL_OPS_COMPAT ++#include "kcompat_ethtool.c" ++#endif ++ ++#ifdef ETHTOOL_GSTATS + struct igb_stats { + char stat_string[ETH_GSTRING_LEN]; + int sizeof_stat; + int stat_offset; + }; + +-#define IGB_STAT(m) FIELD_SIZEOF(struct igb_adapter, m), \ ++#define IGB_STAT(m) sizeof(((struct igb_adapter *)0)->m), \ + offsetof(struct igb_adapter, m) + static const struct igb_stats igb_gstrings_stats[] = { + { "rx_packets", IGB_STAT(stats.gprc) }, +@@ -88,12 +93,13 @@ + { "rx_long_byte_count", IGB_STAT(stats.gorc) }, + { "rx_csum_offload_good", IGB_STAT(hw_csum_good) }, + { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) }, +- { "rx_header_split", IGB_STAT(rx_hdr_split) }, ++ { "tx_dma_out_of_sync", IGB_STAT(stats.doosync) }, ++ { "low_latency_interrupt", IGB_STAT(lli_int)}, + { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) }, + { "tx_smbus", IGB_STAT(stats.mgptc) }, + { "rx_smbus", IGB_STAT(stats.mgprc) }, + { "dropped_smbus", IGB_STAT(stats.mgpdc) }, +-#ifdef CONFIG_IGB_LRO ++#ifdef IGB_LRO + { "lro_aggregated", IGB_STAT(lro_aggregated) }, + { "lro_flushed", IGB_STAT(lro_flushed) }, + { "lro_no_desc", IGB_STAT(lro_no_desc) }, +@@ -101,33 +107,37 @@ + }; + + #define IGB_QUEUE_STATS_LEN \ +- ((((struct igb_adapter *)netdev->priv)->num_rx_queues + \ +- ((struct igb_adapter *)netdev->priv)->num_tx_queues) * \ ++ ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues + \ ++ ((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues) * \ + (sizeof(struct igb_queue_stats) / sizeof(u64))) + #define IGB_GLOBAL_STATS_LEN \ +- sizeof(igb_gstrings_stats) / sizeof(struct igb_stats) ++ (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) + #define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN) ++#endif /* ETHTOOL_GSTATS */ ++#ifdef ETHTOOL_TEST + static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { + "Register test (offline)", "Eeprom test (offline)", + "Interrupt test (offline)", "Loopback test (offline)", + "Link test (on/offline)" + }; +-#define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN ++#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) ++#endif /* ETHTOOL_TEST */ + + static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) + { + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; ++ u32 status; + + if (hw->phy.media_type == e1000_media_type_copper) { + + ecmd->supported = (SUPPORTED_10baseT_Half | +- SUPPORTED_10baseT_Full | +- SUPPORTED_100baseT_Half | +- SUPPORTED_100baseT_Full | +- SUPPORTED_1000baseT_Full| +- SUPPORTED_Autoneg | +- SUPPORTED_TP); ++ SUPPORTED_10baseT_Full | ++ SUPPORTED_100baseT_Half | ++ SUPPORTED_100baseT_Full | ++ SUPPORTED_1000baseT_Full| ++ SUPPORTED_Autoneg | ++ SUPPORTED_TP); + ecmd->advertising = ADVERTISED_TP; + + if (hw->mac.autoneg == 1) { +@@ -152,17 +162,20 @@ + + ecmd->transceiver = XCVR_INTERNAL; + +- if (rd32(E1000_STATUS) & E1000_STATUS_LU) { ++ status = E1000_READ_REG(hw, E1000_STATUS); + +- adapter->hw.mac.ops.get_speed_and_duplex(hw, +- &adapter->link_speed, +- &adapter->link_duplex); +- ecmd->speed = adapter->link_speed; ++ if (status & E1000_STATUS_LU) { + +- /* unfortunately FULL_DUPLEX != DUPLEX_FULL +- * and HALF_DUPLEX != DUPLEX_HALF */ ++ if ((status & E1000_STATUS_SPEED_1000) || ++ hw->phy.media_type != e1000_media_type_copper) ++ ecmd->speed = SPEED_1000; ++ else if (status & E1000_STATUS_SPEED_100) ++ ecmd->speed = SPEED_100; ++ else ++ ecmd->speed = SPEED_10; + +- if (adapter->link_duplex == FULL_DUPLEX) ++ if ((status & E1000_STATUS_FD) || ++ hw->phy.media_type != e1000_media_type_copper) + ecmd->duplex = DUPLEX_FULL; + else + ecmd->duplex = DUPLEX_HALF; +@@ -171,8 +184,7 @@ + ecmd->duplex = -1; + } + +- ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) || +- hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE; ++ ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; + return 0; + } + +@@ -183,9 +195,9 @@ + + /* When SoL/IDER sessions are active, autoneg/speed/duplex + * cannot be changed */ +- if (igb_check_reset_block(hw)) { +- dev_err(&adapter->pdev->dev, "Cannot change link " +- "characteristics when SoL/IDER is active.\n"); ++ if (e1000_check_reset_block(hw)) { ++ DPRINTK(DRV, ERR, "Cannot change link characteristics " ++ "when SoL/IDER is active.\n"); + return -EINVAL; + } + +@@ -194,23 +206,20 @@ + + if (ecmd->autoneg == AUTONEG_ENABLE) { + hw->mac.autoneg = 1; +- if (hw->phy.media_type == e1000_media_type_fiber) +- hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full | +- ADVERTISED_FIBRE | +- ADVERTISED_Autoneg; +- else +- hw->phy.autoneg_advertised = ecmd->advertising | +- ADVERTISED_TP | +- ADVERTISED_Autoneg; ++ hw->phy.autoneg_advertised = ecmd->advertising | ++ ADVERTISED_TP | ++ ADVERTISED_Autoneg; + ecmd->advertising = hw->phy.autoneg_advertised; +- } else ++ if (adapter->fc_autoneg) ++ hw->fc.requested_mode = e1000_fc_default; ++ } else { + if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) { + clear_bit(__IGB_RESETTING, &adapter->state); + return -EINVAL; + } ++ } + + /* reset the link */ +- + if (netif_running(adapter->netdev)) { + igb_down(adapter); + igb_up(adapter); +@@ -222,7 +231,7 @@ + } + + static void igb_get_pauseparam(struct net_device *netdev, +- struct ethtool_pauseparam *pause) ++ struct ethtool_pauseparam *pause) + { + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +@@ -230,18 +239,18 @@ + pause->autoneg = + (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); + +- if (hw->fc.type == e1000_fc_rx_pause) ++ if (hw->fc.current_mode == e1000_fc_rx_pause) + pause->rx_pause = 1; +- else if (hw->fc.type == e1000_fc_tx_pause) ++ else if (hw->fc.current_mode == e1000_fc_tx_pause) + pause->tx_pause = 1; +- else if (hw->fc.type == e1000_fc_full) { ++ else if (hw->fc.current_mode == e1000_fc_full) { + pause->rx_pause = 1; + pause->tx_pause = 1; + } + } + + static int igb_set_pauseparam(struct net_device *netdev, +- struct ethtool_pauseparam *pause) ++ struct ethtool_pauseparam *pause) + { + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +@@ -252,26 +261,29 @@ + while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) + msleep(1); + +- if (pause->rx_pause && pause->tx_pause) +- hw->fc.type = e1000_fc_full; +- else if (pause->rx_pause && !pause->tx_pause) +- hw->fc.type = e1000_fc_rx_pause; +- else if (!pause->rx_pause && pause->tx_pause) +- hw->fc.type = e1000_fc_tx_pause; +- else if (!pause->rx_pause && !pause->tx_pause) +- hw->fc.type = e1000_fc_none; +- +- hw->fc.original_type = hw->fc.type; +- + if (adapter->fc_autoneg == AUTONEG_ENABLE) { ++ hw->fc.requested_mode = e1000_fc_default; + if (netif_running(adapter->netdev)) { + igb_down(adapter); + igb_up(adapter); +- } else ++ } else { + igb_reset(adapter); +- } else +- retval = ((hw->phy.media_type == e1000_media_type_fiber) ? +- igb_setup_link(hw) : igb_force_mac_fc(hw)); ++ } ++ } else { ++ if (pause->rx_pause && pause->tx_pause) ++ hw->fc.requested_mode = e1000_fc_full; ++ else if (pause->rx_pause && !pause->tx_pause) ++ hw->fc.requested_mode = e1000_fc_rx_pause; ++ else if (!pause->rx_pause && pause->tx_pause) ++ hw->fc.requested_mode = e1000_fc_tx_pause; ++ else if (!pause->rx_pause && !pause->tx_pause) ++ hw->fc.requested_mode = e1000_fc_none; ++ ++ hw->fc.current_mode = hw->fc.requested_mode; ++ ++ retval = ((hw->phy.media_type == e1000_media_type_copper) ? ++ e1000_force_mac_fc(hw) : hw->mac.ops.setup_link(hw)); ++ } + + clear_bit(__IGB_RESETTING, &adapter->state); + return retval; +@@ -280,50 +292,80 @@ + static u32 igb_get_rx_csum(struct net_device *netdev) + { + struct igb_adapter *adapter = netdev_priv(netdev); +- return adapter->rx_csum; ++ return !(adapter->flags & IGB_FLAG_RX_CSUM_DISABLED); + } + + static int igb_set_rx_csum(struct net_device *netdev, u32 data) + { + struct igb_adapter *adapter = netdev_priv(netdev); +- adapter->rx_csum = data; ++ ++ if (data) ++ adapter->flags &= ~IGB_FLAG_RX_CSUM_DISABLED; ++ else ++ adapter->flags |= IGB_FLAG_RX_CSUM_DISABLED; + + return 0; + } + + static u32 igb_get_tx_csum(struct net_device *netdev) + { +- return (netdev->features & NETIF_F_HW_CSUM) != 0; ++ return (netdev->features & NETIF_F_IP_CSUM) != 0; + } + + static int igb_set_tx_csum(struct net_device *netdev, u32 data) + { + if (data) +- netdev->features |= NETIF_F_HW_CSUM; ++#ifdef NETIF_F_IPV6_CSUM ++ netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); + else +- netdev->features &= ~NETIF_F_HW_CSUM; ++ netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); ++#else ++ netdev->features |= NETIF_F_IP_CSUM; ++ else ++ netdev->features &= ~NETIF_F_IP_CSUM; ++#endif + + return 0; + } + ++#ifdef NETIF_F_TSO + static int igb_set_tso(struct net_device *netdev, u32 data) + { + struct igb_adapter *adapter = netdev_priv(netdev); ++ int i; ++ struct net_device *v_netdev; + +- if (data) ++ if (data) { + netdev->features |= NETIF_F_TSO; +- else ++#ifdef NETIF_F_TSO6 ++ netdev->features |= NETIF_F_TSO6; ++#endif ++ } else { + netdev->features &= ~NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 ++ netdev->features &= ~NETIF_F_TSO6; ++#endif ++ /* disable TSO on all VLANs if they're present */ ++ if (!adapter->vlgrp) ++ goto tso_out; ++ for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) { ++ v_netdev = vlan_group_get_device(adapter->vlgrp, i); ++ if (!v_netdev) ++ continue; + +- if (data) +- netdev->features |= NETIF_F_TSO6; +- else +- netdev->features &= ~NETIF_F_TSO6; ++ v_netdev->features &= ~NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 ++ v_netdev->features &= ~NETIF_F_TSO6; ++#endif ++ vlan_group_set_device(adapter->vlgrp, i, v_netdev); ++ } ++ } + +- dev_info(&adapter->pdev->dev, "TSO is %s\n", +- data ? "Enabled" : "Disabled"); ++tso_out: ++ DPRINTK(PROBE, INFO, "TSO is %s\n", data ? "Enabled" : "Disabled"); + return 0; + } ++#endif /* NETIF_F_TSO */ + + static u32 igb_get_msglevel(struct net_device *netdev) + { +@@ -344,7 +386,7 @@ + } + + static void igb_get_regs(struct net_device *netdev, +- struct ethtool_regs *regs, void *p) ++ struct ethtool_regs *regs, void *p) + { + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +@@ -356,78 +398,78 @@ + regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; + + /* General Registers */ +- regs_buff[0] = rd32(E1000_CTRL); +- regs_buff[1] = rd32(E1000_STATUS); +- regs_buff[2] = rd32(E1000_CTRL_EXT); +- regs_buff[3] = rd32(E1000_MDIC); +- regs_buff[4] = rd32(E1000_SCTL); +- regs_buff[5] = rd32(E1000_CONNSW); +- regs_buff[6] = rd32(E1000_VET); +- regs_buff[7] = rd32(E1000_LEDCTL); +- regs_buff[8] = rd32(E1000_PBA); +- regs_buff[9] = rd32(E1000_PBS); +- regs_buff[10] = rd32(E1000_FRTIMER); +- regs_buff[11] = rd32(E1000_TCPTIMER); ++ regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); ++ regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); ++ regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); ++ regs_buff[3] = E1000_READ_REG(hw, E1000_MDIC); ++ regs_buff[4] = E1000_READ_REG(hw, E1000_SCTL); ++ regs_buff[5] = E1000_READ_REG(hw, E1000_CONNSW); ++ regs_buff[6] = E1000_READ_REG(hw, E1000_VET); ++ regs_buff[7] = E1000_READ_REG(hw, E1000_LEDCTL); ++ regs_buff[8] = E1000_READ_REG(hw, E1000_PBA); ++ regs_buff[9] = E1000_READ_REG(hw, E1000_PBS); ++ regs_buff[10] = E1000_READ_REG(hw, E1000_FRTIMER); ++ regs_buff[11] = E1000_READ_REG(hw, E1000_TCPTIMER); + + /* NVM Register */ +- regs_buff[12] = rd32(E1000_EECD); ++ regs_buff[12] = E1000_READ_REG(hw, E1000_EECD); + + /* Interrupt */ + /* Reading EICS for EICR because they read the + * same but EICS does not clear on read */ +- regs_buff[13] = rd32(E1000_EICS); +- regs_buff[14] = rd32(E1000_EICS); +- regs_buff[15] = rd32(E1000_EIMS); +- regs_buff[16] = rd32(E1000_EIMC); +- regs_buff[17] = rd32(E1000_EIAC); +- regs_buff[18] = rd32(E1000_EIAM); ++ regs_buff[13] = E1000_READ_REG(hw, E1000_EICS); ++ regs_buff[14] = E1000_READ_REG(hw, E1000_EICS); ++ regs_buff[15] = E1000_READ_REG(hw, E1000_EIMS); ++ regs_buff[16] = E1000_READ_REG(hw, E1000_EIMC); ++ regs_buff[17] = E1000_READ_REG(hw, E1000_EIAC); ++ regs_buff[18] = E1000_READ_REG(hw, E1000_EIAM); + /* Reading ICS for ICR because they read the + * same but ICS does not clear on read */ +- regs_buff[19] = rd32(E1000_ICS); +- regs_buff[20] = rd32(E1000_ICS); +- regs_buff[21] = rd32(E1000_IMS); +- regs_buff[22] = rd32(E1000_IMC); +- regs_buff[23] = rd32(E1000_IAC); +- regs_buff[24] = rd32(E1000_IAM); +- regs_buff[25] = rd32(E1000_IMIRVP); ++ regs_buff[19] = E1000_READ_REG(hw, E1000_ICS); ++ regs_buff[20] = E1000_READ_REG(hw, E1000_ICS); ++ regs_buff[21] = E1000_READ_REG(hw, E1000_IMS); ++ regs_buff[22] = E1000_READ_REG(hw, E1000_IMC); ++ regs_buff[23] = E1000_READ_REG(hw, E1000_IAC); ++ regs_buff[24] = E1000_READ_REG(hw, E1000_IAM); ++ regs_buff[25] = E1000_READ_REG(hw, E1000_IMIRVP); + + /* Flow Control */ +- regs_buff[26] = rd32(E1000_FCAL); +- regs_buff[27] = rd32(E1000_FCAH); +- regs_buff[28] = rd32(E1000_FCTTV); +- regs_buff[29] = rd32(E1000_FCRTL); +- regs_buff[30] = rd32(E1000_FCRTH); +- regs_buff[31] = rd32(E1000_FCRTV); ++ regs_buff[26] = E1000_READ_REG(hw, E1000_FCAL); ++ regs_buff[27] = E1000_READ_REG(hw, E1000_FCAH); ++ regs_buff[28] = E1000_READ_REG(hw, E1000_FCTTV); ++ regs_buff[29] = E1000_READ_REG(hw, E1000_FCRTL); ++ regs_buff[30] = E1000_READ_REG(hw, E1000_FCRTH); ++ regs_buff[31] = E1000_READ_REG(hw, E1000_FCRTV); + + /* Receive */ +- regs_buff[32] = rd32(E1000_RCTL); +- regs_buff[33] = rd32(E1000_RXCSUM); +- regs_buff[34] = rd32(E1000_RLPML); +- regs_buff[35] = rd32(E1000_RFCTL); +- regs_buff[36] = rd32(E1000_MRQC); +- regs_buff[37] = rd32(E1000_VMD_CTL); ++ regs_buff[32] = E1000_READ_REG(hw, E1000_RCTL); ++ regs_buff[33] = E1000_READ_REG(hw, E1000_RXCSUM); ++ regs_buff[34] = E1000_READ_REG(hw, E1000_RLPML); ++ regs_buff[35] = E1000_READ_REG(hw, E1000_RFCTL); ++ regs_buff[36] = E1000_READ_REG(hw, E1000_MRQC); ++ regs_buff[37] = E1000_READ_REG(hw, E1000_VT_CTL); + + /* Transmit */ +- regs_buff[38] = rd32(E1000_TCTL); +- regs_buff[39] = rd32(E1000_TCTL_EXT); +- regs_buff[40] = rd32(E1000_TIPG); +- regs_buff[41] = rd32(E1000_DTXCTL); ++ regs_buff[38] = E1000_READ_REG(hw, E1000_TCTL); ++ regs_buff[39] = E1000_READ_REG(hw, E1000_TCTL_EXT); ++ regs_buff[40] = E1000_READ_REG(hw, E1000_TIPG); ++ regs_buff[41] = E1000_READ_REG(hw, E1000_DTXCTL); + + /* Wake Up */ +- regs_buff[42] = rd32(E1000_WUC); +- regs_buff[43] = rd32(E1000_WUFC); +- regs_buff[44] = rd32(E1000_WUS); +- regs_buff[45] = rd32(E1000_IPAV); +- regs_buff[46] = rd32(E1000_WUPL); ++ regs_buff[42] = E1000_READ_REG(hw, E1000_WUC); ++ regs_buff[43] = E1000_READ_REG(hw, E1000_WUFC); ++ regs_buff[44] = E1000_READ_REG(hw, E1000_WUS); ++ regs_buff[45] = E1000_READ_REG(hw, E1000_IPAV); ++ regs_buff[46] = E1000_READ_REG(hw, E1000_WUPL); + + /* MAC */ +- regs_buff[47] = rd32(E1000_PCS_CFG0); +- regs_buff[48] = rd32(E1000_PCS_LCTL); +- regs_buff[49] = rd32(E1000_PCS_LSTAT); +- regs_buff[50] = rd32(E1000_PCS_ANADV); +- regs_buff[51] = rd32(E1000_PCS_LPAB); +- regs_buff[52] = rd32(E1000_PCS_NPTX); +- regs_buff[53] = rd32(E1000_PCS_LPABNP); ++ regs_buff[47] = E1000_READ_REG(hw, E1000_PCS_CFG0); ++ regs_buff[48] = E1000_READ_REG(hw, E1000_PCS_LCTL); ++ regs_buff[49] = E1000_READ_REG(hw, E1000_PCS_LSTAT); ++ regs_buff[50] = E1000_READ_REG(hw, E1000_PCS_ANADV); ++ regs_buff[51] = E1000_READ_REG(hw, E1000_PCS_LPAB); ++ regs_buff[52] = E1000_READ_REG(hw, E1000_PCS_NPTX); ++ regs_buff[53] = E1000_READ_REG(hw, E1000_PCS_LPABNP); + + /* Statistics */ + regs_buff[54] = adapter->stats.crcerrs; +@@ -492,81 +534,70 @@ + regs_buff[119] = adapter->stats.scvpc; + regs_buff[120] = adapter->stats.hrmpc; + +- /* These should probably be added to e1000_regs.h instead */ +- #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4)) +- #define E1000_RAL(_i) (0x05400 + ((_i) * 8)) +- #define E1000_RAH(_i) (0x05404 + ((_i) * 8)) +- #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) +- #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) +- #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) +- #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) +- #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) +- #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) ++ for (i = 0; i < 4; i++) ++ regs_buff[121 + i] = E1000_READ_REG(hw, E1000_SRRCTL(i)); ++ for (i = 0; i < 4; i++) ++ regs_buff[125 + i] = E1000_READ_REG(hw, E1000_PSRTYPE(i)); ++ for (i = 0; i < 4; i++) ++ regs_buff[129 + i] = E1000_READ_REG(hw, E1000_RDBAL(i)); ++ for (i = 0; i < 4; i++) ++ regs_buff[133 + i] = E1000_READ_REG(hw, E1000_RDBAH(i)); ++ for (i = 0; i < 4; i++) ++ regs_buff[137 + i] = E1000_READ_REG(hw, E1000_RDLEN(i)); ++ for (i = 0; i < 4; i++) ++ regs_buff[141 + i] = E1000_READ_REG(hw, E1000_RDH(i)); ++ for (i = 0; i < 4; i++) ++ regs_buff[145 + i] = E1000_READ_REG(hw, E1000_RDT(i)); ++ for (i = 0; i < 4; i++) ++ regs_buff[149 + i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); ++ ++ for (i = 0; i < 10; i++) ++ regs_buff[153 + i] = E1000_READ_REG(hw, E1000_EITR(i)); ++ for (i = 0; i < 8; i++) ++ regs_buff[163 + i] = E1000_READ_REG(hw, E1000_IMIR(i)); ++ for (i = 0; i < 8; i++) ++ regs_buff[171 + i] = E1000_READ_REG(hw, E1000_IMIREXT(i)); ++ for (i = 0; i < 16; i++) ++ regs_buff[179 + i] = E1000_READ_REG(hw, E1000_RAL(i)); ++ for (i = 0; i < 16; i++) ++ regs_buff[195 + i] = E1000_READ_REG(hw, E1000_RAH(i)); + + for (i = 0; i < 4; i++) +- regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); ++ regs_buff[211 + i] = E1000_READ_REG(hw, E1000_TDBAL(i)); + for (i = 0; i < 4; i++) +- regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i)); ++ regs_buff[215 + i] = E1000_READ_REG(hw, E1000_TDBAH(i)); + for (i = 0; i < 4; i++) +- regs_buff[129 + i] = rd32(E1000_RDBAL(i)); ++ regs_buff[219 + i] = E1000_READ_REG(hw, E1000_TDLEN(i)); + for (i = 0; i < 4; i++) +- regs_buff[133 + i] = rd32(E1000_RDBAH(i)); ++ regs_buff[223 + i] = E1000_READ_REG(hw, E1000_TDH(i)); + for (i = 0; i < 4; i++) +- regs_buff[137 + i] = rd32(E1000_RDLEN(i)); ++ regs_buff[227 + i] = E1000_READ_REG(hw, E1000_TDT(i)); + for (i = 0; i < 4; i++) +- regs_buff[141 + i] = rd32(E1000_RDH(i)); ++ regs_buff[231 + i] = E1000_READ_REG(hw, E1000_TXDCTL(i)); + for (i = 0; i < 4; i++) +- regs_buff[145 + i] = rd32(E1000_RDT(i)); ++ regs_buff[235 + i] = E1000_READ_REG(hw, E1000_TDWBAL(i)); + for (i = 0; i < 4; i++) +- regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); +- +- for (i = 0; i < 10; i++) +- regs_buff[153 + i] = rd32(E1000_EITR(i)); +- for (i = 0; i < 8; i++) +- regs_buff[163 + i] = rd32(E1000_IMIR(i)); +- for (i = 0; i < 8; i++) +- regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); +- for (i = 0; i < 16; i++) +- regs_buff[179 + i] = rd32(E1000_RAL(i)); +- for (i = 0; i < 16; i++) +- regs_buff[195 + i] = rd32(E1000_RAH(i)); ++ regs_buff[239 + i] = E1000_READ_REG(hw, E1000_TDWBAH(i)); ++ for (i = 0; i < 4; i++) ++ regs_buff[243 + i] = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i)); + + for (i = 0; i < 4; i++) +- regs_buff[211 + i] = rd32(E1000_TDBAL(i)); ++ regs_buff[247 + i] = E1000_READ_REG(hw, E1000_IP4AT_REG(i)); + for (i = 0; i < 4; i++) +- regs_buff[215 + i] = rd32(E1000_TDBAH(i)); ++ regs_buff[251 + i] = E1000_READ_REG(hw, E1000_IP6AT_REG(i)); ++ for (i = 0; i < 32; i++) ++ regs_buff[255 + i] = E1000_READ_REG(hw, E1000_WUPM_REG(i)); ++ for (i = 0; i < 128; i++) ++ regs_buff[287 + i] = E1000_READ_REG(hw, E1000_FFMT_REG(i)); ++ for (i = 0; i < 128; i++) ++ regs_buff[415 + i] = E1000_READ_REG(hw, E1000_FFVT_REG(i)); + for (i = 0; i < 4; i++) +- regs_buff[219 + i] = rd32(E1000_TDLEN(i)); +- for (i = 0; i < 4; i++) +- regs_buff[223 + i] = rd32(E1000_TDH(i)); +- for (i = 0; i < 4; i++) +- regs_buff[227 + i] = rd32(E1000_TDT(i)); +- for (i = 0; i < 4; i++) +- regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); +- for (i = 0; i < 4; i++) +- regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); +- for (i = 0; i < 4; i++) +- regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); +- for (i = 0; i < 4; i++) +- regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); ++ regs_buff[543 + i] = E1000_READ_REG(hw, E1000_FFLT_REG(i)); + +- for (i = 0; i < 4; i++) +- regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); +- for (i = 0; i < 4; i++) +- regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); +- for (i = 0; i < 32; i++) +- regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); +- for (i = 0; i < 128; i++) +- regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); +- for (i = 0; i < 128; i++) +- regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); +- for (i = 0; i < 4; i++) +- regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); +- +- regs_buff[547] = rd32(E1000_TDFH); +- regs_buff[548] = rd32(E1000_TDFT); +- regs_buff[549] = rd32(E1000_TDFHS); +- regs_buff[550] = rd32(E1000_TDFPC); ++ regs_buff[547] = E1000_READ_REG(hw, E1000_TDFH); ++ regs_buff[548] = E1000_READ_REG(hw, E1000_TDFT); ++ regs_buff[549] = E1000_READ_REG(hw, E1000_TDFHS); ++ regs_buff[550] = E1000_READ_REG(hw, E1000_TDFPC); + + } + +@@ -577,7 +608,7 @@ + } + + static int igb_get_eeprom(struct net_device *netdev, +- struct ethtool_eeprom *eeprom, u8 *bytes) ++ struct ethtool_eeprom *eeprom, u8 *bytes) + { + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +@@ -600,13 +631,13 @@ + return -ENOMEM; + + if (hw->nvm.type == e1000_nvm_eeprom_spi) +- ret_val = hw->nvm.ops.read_nvm(hw, first_word, +- last_word - first_word + 1, +- eeprom_buff); ++ ret_val = e1000_read_nvm(hw, first_word, ++ last_word - first_word + 1, ++ eeprom_buff); + else { + for (i = 0; i < last_word - first_word + 1; i++) { +- ret_val = hw->nvm.ops.read_nvm(hw, first_word + i, 1, +- &eeprom_buff[i]); ++ ret_val = e1000_read_nvm(hw, first_word + i, 1, ++ &eeprom_buff[i]); + if (ret_val) + break; + } +@@ -624,7 +655,7 @@ + } + + static int igb_set_eeprom(struct net_device *netdev, +- struct ethtool_eeprom *eeprom, u8 *bytes) ++ struct ethtool_eeprom *eeprom, u8 *bytes) + { + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +@@ -652,15 +683,15 @@ + if (eeprom->offset & 1) { + /* need read/modify/write of first changed EEPROM word */ + /* only the second byte of the word is being modified */ +- ret_val = hw->nvm.ops.read_nvm(hw, first_word, 1, ++ ret_val = e1000_read_nvm(hw, first_word, 1, + &eeprom_buff[0]); + ptr++; + } + if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { + /* need read/modify/write of last changed EEPROM word */ + /* only the first byte of the word is being modified */ +- ret_val = hw->nvm.ops.read_nvm(hw, last_word, 1, +- &eeprom_buff[last_word - first_word]); ++ ret_val = e1000_read_nvm(hw, last_word, 1, ++ &eeprom_buff[last_word - first_word]); + } + + /* Device's eeprom is always little-endian, word addressable */ +@@ -672,20 +703,20 @@ + for (i = 0; i < last_word - first_word + 1; i++) + eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); + +- ret_val = hw->nvm.ops.write_nvm(hw, first_word, +- last_word - first_word + 1, eeprom_buff); ++ ret_val = e1000_write_nvm(hw, first_word, ++ last_word - first_word + 1, eeprom_buff); + + /* Update the checksum over the first part of the EEPROM if needed + * and flush shadow RAM for 82573 controllers */ + if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG))) +- igb_update_nvm_checksum(hw); ++ e1000_update_nvm_checksum(hw); + + kfree(eeprom_buff); + return ret_val; + } + + static void igb_get_drvinfo(struct net_device *netdev, +- struct ethtool_drvinfo *drvinfo) ++ struct ethtool_drvinfo *drvinfo) + { + struct igb_adapter *adapter = netdev_priv(netdev); + char firmware_version[32]; +@@ -696,7 +727,7 @@ + + /* EEPROM image version # is reported as firmware version # for + * 82575 controllers */ +- adapter->hw.nvm.ops.read_nvm(&adapter->hw, 5, 1, &eeprom_data); ++ e1000_read_nvm(&adapter->hw, 5, 1, &eeprom_data); + sprintf(firmware_version, "%d.%d-%d", + (eeprom_data & 0xF000) >> 12, + (eeprom_data & 0x0FF0) >> 4, +@@ -711,7 +742,7 @@ + } + + static void igb_get_ringparam(struct net_device *netdev, +- struct ethtool_ringparam *ring) ++ struct ethtool_ringparam *ring) + { + struct igb_adapter *adapter = netdev_priv(netdev); + +@@ -726,7 +757,7 @@ + } + + static int igb_set_ringparam(struct net_device *netdev, +- struct ethtool_ringparam *ring) ++ struct ethtool_ringparam *ring) + { + struct igb_adapter *adapter = netdev_priv(netdev); + struct igb_ring *temp_ring; +@@ -829,148 +860,56 @@ + return err; + } + +-/* ethtool register test data */ +-struct igb_reg_test { +- u16 reg; +- u16 reg_offset; +- u16 array_len; +- u16 test_type; +- u32 mask; +- u32 write; +-}; +- +-/* In the hardware, registers are laid out either singly, in arrays +- * spaced 0x100 bytes apart, or in contiguous tables. We assume +- * most tests take place on arrays or single registers (handled +- * as a single-element array) and special-case the tables. +- * Table tests are always pattern tests. +- * +- * We also make provision for some required setup steps by specifying +- * registers to be written without any read-back testing. +- */ +- +-#define PATTERN_TEST 1 +-#define SET_READ_TEST 2 +-#define WRITE_NO_TEST 3 +-#define TABLE32_TEST 4 +-#define TABLE64_TEST_LO 5 +-#define TABLE64_TEST_HI 6 +- +-/* 82576 reg test */ +-static struct igb_reg_test reg_test_82576[] = { +- { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, +- { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, +- { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, +- { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, +- { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, +- { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, +- { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, +- { E1000_RDBAL(4), 0x40, 8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, +- { E1000_RDBAH(4), 0x40, 8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, +- { E1000_RDLEN(4), 0x40, 8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, +- /* Enable all four RX queues before testing. */ +- { E1000_RXDCTL(0), 0x100, 1, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, +- /* RDH is read-only for 82576, only test RDT. */ +- { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, +- { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, +- { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, +- { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, +- { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, +- { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, +- { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, +- { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, +- { E1000_TDBAL(4), 0x40, 8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, +- { E1000_TDBAH(4), 0x40, 8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, +- { E1000_TDLEN(4), 0x40, 8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, +- { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, +- { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, +- { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, +- { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, +- { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, +- { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, +- { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, +- { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, +- { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, +- { 0, 0, 0, 0 } +-}; +- +-/* 82575 register test */ +-static struct igb_reg_test reg_test_82575[] = { +- { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, +- { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, +- { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, +- { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, +- { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, +- { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, +- { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, +- /* Enable all four RX queues before testing. */ +- { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, +- /* RDH is read-only for 82575, only test RDT. */ +- { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, +- { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, +- { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, +- { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, +- { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, +- { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, +- { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, +- { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, +- { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, +- { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, +- { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, +- { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, +- { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, +- { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, +- { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, +- { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, +- { 0, 0, 0, 0 } +-}; +- + static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, + int reg, u32 mask, u32 write) + { ++ struct e1000_hw *hw = &adapter->hw; + u32 pat, val; +- u32 _test[] = ++ static const u32 _test[] = + {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; + for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { +- writel((_test[pat] & write), (adapter->hw.hw_addr + reg)); +- val = readl(adapter->hw.hw_addr + reg); ++ E1000_WRITE_REG(hw, reg, (_test[pat] & write)); ++ val = E1000_READ_REG(hw, reg); + if (val != (_test[pat] & write & mask)) { +- dev_err(&adapter->pdev->dev, "pattern test reg %04X " +- "failed: got 0x%08X expected 0x%08X\n", +- reg, val, (_test[pat] & write & mask)); +- *data = reg; ++ DPRINTK(DRV, ERR, "pattern test reg %04X failed: got " ++ "0x%08X expected 0x%08X\n", ++ E1000_REGISTER(hw, reg), val, ++ (_test[pat] & write & mask)); ++ *data = E1000_REGISTER(hw, reg); + return 1; + } + } ++ + return 0; + } + + static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, + int reg, u32 mask, u32 write) + { ++ struct e1000_hw *hw = &adapter->hw; + u32 val; +- writel((write & mask), (adapter->hw.hw_addr + reg)); +- val = readl(adapter->hw.hw_addr + reg); ++ E1000_WRITE_REG(hw, reg, write & mask); ++ val = E1000_READ_REG(hw, reg); + if ((write & mask) != (val & mask)) { +- dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:" +- " got 0x%08X expected 0x%08X\n", reg, +- (val & mask), (write & mask)); +- *data = reg; ++ DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X " ++ "expected 0x%08X\n", reg, (val & mask), (write & mask)); ++ *data = E1000_REGISTER(hw, reg); + return 1; + } ++ + return 0; + } + +-#define REG_PATTERN_TEST(reg, mask, write) \ +- do { \ +- if (reg_pattern_test(adapter, data, reg, mask, write)) \ +- return 1; \ ++#define REG_PATTERN_TEST(reg, mask, write) \ ++ do { \ ++ if (reg_pattern_test(adapter, data, reg, mask, write)) \ ++ return 1; \ + } while (0) + +-#define REG_SET_AND_CHECK(reg, mask, write) \ +- do { \ +- if (reg_set_and_check(adapter, data, reg, mask, write)) \ +- return 1; \ ++#define REG_SET_AND_CHECK(reg, mask, write) \ ++ do { \ ++ if (reg_set_and_check(adapter, data, reg, mask, write)) \ ++ return 1; \ + } while (0) + + static int igb_reg_test(struct igb_adapter *adapter, u64 *data) +@@ -980,14 +919,14 @@ + u32 value, before, after; + u32 i, toggle; + +- toggle = 0x7FFFF3FF; +- + switch (adapter->hw.mac.type) { + case e1000_82576: + test = reg_test_82576; ++ toggle = 0x7FFFF3FF; + break; + default: + test = reg_test_82575; ++ toggle = 0x7FFFF3FF; + break; + } + +@@ -996,18 +935,18 @@ + * tests. Some bits are read-only, some toggle, and some + * are writable on newer MACs. + */ +- before = rd32(E1000_STATUS); +- value = (rd32(E1000_STATUS) & toggle); +- wr32(E1000_STATUS, toggle); +- after = rd32(E1000_STATUS) & toggle; ++ before = E1000_READ_REG(hw, E1000_STATUS); ++ value = (E1000_READ_REG(hw, E1000_STATUS) & toggle); ++ E1000_WRITE_REG(hw, E1000_STATUS, toggle); ++ after = E1000_READ_REG(hw, E1000_STATUS) & toggle; + if (value != after) { +- dev_err(&adapter->pdev->dev, "failed STATUS register test " +- "got: 0x%08X expected: 0x%08X\n", after, value); ++ DPRINTK(DRV, ERR, "failed STATUS register test got: " ++ "0x%08X expected: 0x%08X\n", after, value); + *data = 1; + return 1; + } + /* restore previous status */ +- wr32(E1000_STATUS, before); ++ E1000_WRITE_REG(hw, E1000_STATUS, before); + + /* Perform the remainder of the register test, looping through + * the test table until we either fail or reach the null entry. +@@ -1016,19 +955,21 @@ + for (i = 0; i < test->array_len; i++) { + switch (test->test_type) { + case PATTERN_TEST: +- REG_PATTERN_TEST(test->reg + (i * test->reg_offset), ++ REG_PATTERN_TEST(test->reg + ++ (i * test->reg_offset), + test->mask, + test->write); + break; + case SET_READ_TEST: +- REG_SET_AND_CHECK(test->reg + (i * test->reg_offset), ++ REG_SET_AND_CHECK(test->reg + ++ (i * test->reg_offset), + test->mask, + test->write); + break; + case WRITE_NO_TEST: + writel(test->write, +- (adapter->hw.hw_addr + test->reg) +- + (i * test->reg_offset)); ++ (adapter->hw.hw_addr + test->reg) ++ + (i * test->reg_offset)); + break; + case TABLE32_TEST: + REG_PATTERN_TEST(test->reg + (i * 4), +@@ -1063,8 +1004,7 @@ + *data = 0; + /* Read and add up the contents of the EEPROM */ + for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { +- if ((adapter->hw.nvm.ops.read_nvm(&adapter->hw, i, 1, &temp)) +- < 0) { ++ if ((e1000_read_nvm(&adapter->hw, i, 1, &temp)) < 0) { + *data = 1; + break; + } +@@ -1084,7 +1024,7 @@ + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; + +- adapter->test_icr |= rd32(E1000_ICR); ++ adapter->test_icr |= E1000_READ_REG(hw, E1000_ICR); + + return IRQ_HANDLED; + } +@@ -1093,40 +1033,57 @@ + { + struct e1000_hw *hw = &adapter->hw; + struct net_device *netdev = adapter->netdev; +- u32 mask, i = 0, shared_int = true; ++ u32 mask, ics_mask, i = 0, shared_int = TRUE; + u32 irq = adapter->pdev->irq; + + *data = 0; + + /* Hook up test interrupt handler just for this test */ +- if (adapter->msix_entries) { ++ if (adapter->msix_entries) + /* NOTE: we don't test MSI-X interrupts here, yet */ + return 0; +- } else if (adapter->flags & IGB_FLAG_HAS_MSI) { +- shared_int = false; ++ ++ if (adapter->flags & IGB_FLAG_HAS_MSI) { ++ shared_int = FALSE; + if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) { + *data = 1; + return -1; + } + } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED, +- netdev->name, netdev)) { +- shared_int = false; ++ netdev->name, netdev)) { ++ shared_int = FALSE; + } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED, +- netdev->name, netdev)) { ++ netdev->name, netdev)) { + *data = 1; + return -1; + } +- dev_info(&adapter->pdev->dev, "testing %s interrupt\n", +- (shared_int ? "shared" : "unshared")); ++ DPRINTK(HW, INFO, "testing %s interrupt\n", ++ (shared_int ? "shared" : "unshared")); + + /* Disable all the interrupts */ +- wr32(E1000_IMC, 0xFFFFFFFF); ++ E1000_WRITE_REG(hw, E1000_IMC, ~0); + msleep(10); + ++ /* Define all writable bits for ICS */ ++ switch (hw->mac.type) { ++ case e1000_82575: ++ ics_mask = 0x37F47EDD; ++ break; ++ case e1000_82576: ++ ics_mask = 0x77D4FBFD; ++ break; ++ default: ++ ics_mask = 0x7FFFFFFF; ++ break; ++ } ++ + /* Test each interrupt */ +- for (; i < 10; i++) { ++ for (; i < 31; i++) { + /* Interrupt to test */ + mask = 1 << i; ++ ++ if (!(mask & ics_mask)) ++ continue; + + if (!shared_int) { + /* Disable the interrupt to be reported in +@@ -1136,8 +1093,12 @@ + * test failed. + */ + adapter->test_icr = 0; +- wr32(E1000_IMC, ~mask & 0x00007FFF); +- wr32(E1000_ICS, ~mask & 0x00007FFF); ++ ++ /* Flush any pending interrupts */ ++ E1000_WRITE_REG(hw, E1000_ICR, ~0); ++ ++ E1000_WRITE_REG(hw, E1000_IMC, mask); ++ E1000_WRITE_REG(hw, E1000_ICS, mask); + msleep(10); + + if (adapter->test_icr & mask) { +@@ -1153,8 +1114,12 @@ + * test failed. + */ + adapter->test_icr = 0; +- wr32(E1000_IMS, mask); +- wr32(E1000_ICS, mask); ++ ++ /* Flush any pending interrupts */ ++ E1000_WRITE_REG(hw, E1000_ICR, ~0); ++ ++ E1000_WRITE_REG(hw, E1000_IMS, mask); ++ E1000_WRITE_REG(hw, E1000_ICS, mask); + msleep(10); + + if (!(adapter->test_icr & mask)) { +@@ -1170,11 +1135,15 @@ + * test failed. + */ + adapter->test_icr = 0; +- wr32(E1000_IMC, ~mask & 0x00007FFF); +- wr32(E1000_ICS, ~mask & 0x00007FFF); ++ ++ /* Flush any pending interrupts */ ++ E1000_WRITE_REG(hw, E1000_ICR, ~0); ++ ++ E1000_WRITE_REG(hw, E1000_IMC, ~mask); ++ E1000_WRITE_REG(hw, E1000_ICS, ~mask); + msleep(10); + +- if (adapter->test_icr) { ++ if (adapter->test_icr & mask) { + *data = 5; + break; + } +@@ -1182,7 +1151,7 @@ + } + + /* Disable all the interrupts */ +- wr32(E1000_IMC, 0xFFFFFFFF); ++ E1000_WRITE_REG(hw, E1000_IMC, ~0); + msleep(10); + + /* Unhook test interrupt handler */ +@@ -1203,7 +1172,7 @@ + struct igb_buffer *buf = &(tx_ring->buffer_info[i]); + if (buf->dma) + pci_unmap_single(pdev, buf->dma, buf->length, +- PCI_DMA_TODEVICE); ++ PCI_DMA_TODEVICE); + if (buf->skb) + dev_kfree_skb(buf->skb); + } +@@ -1214,8 +1183,8 @@ + struct igb_buffer *buf = &(rx_ring->buffer_info[i]); + if (buf->dma) + pci_unmap_single(pdev, buf->dma, +- IGB_RXBUFFER_2048, +- PCI_DMA_FROMDEVICE); ++ IGB_RXBUFFER_2048, ++ PCI_DMA_FROMDEVICE); + if (buf->skb) + dev_kfree_skb(buf->skb); + } +@@ -1223,12 +1192,12 @@ + + if (tx_ring->desc) { + pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, +- tx_ring->dma); ++ tx_ring->dma); + tx_ring->desc = NULL; + } + if (rx_ring->desc) { + pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, +- rx_ring->dma); ++ rx_ring->dma); + rx_ring->desc = NULL; + } + +@@ -1246,7 +1215,7 @@ + struct igb_ring *tx_ring = &adapter->test_tx_ring; + struct igb_ring *rx_ring = &adapter->test_rx_ring; + struct pci_dev *pdev = adapter->pdev; +- u32 rctl; ++ u32 rctl , rxdctl, txdctl; + int i, ret_val; + + /* Setup Tx descriptor ring and Tx buffers */ +@@ -1255,8 +1224,8 @@ + tx_ring->count = IGB_DEFAULT_TXD; + + tx_ring->buffer_info = kcalloc(tx_ring->count, +- sizeof(struct igb_buffer), +- GFP_KERNEL); ++ sizeof(struct igb_buffer), ++ GFP_KERNEL); + if (!tx_ring->buffer_info) { + ret_val = 1; + goto err_nomem; +@@ -1265,31 +1234,33 @@ + tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); + tx_ring->size = ALIGN(tx_ring->size, 4096); + tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, +- &tx_ring->dma); ++ &tx_ring->dma); + if (!tx_ring->desc) { + ret_val = 2; + goto err_nomem; + } + tx_ring->next_to_use = tx_ring->next_to_clean = 0; + +- wr32(E1000_TDBAL(0), ++ E1000_WRITE_REG(hw, E1000_TDBAL(0), + ((u64) tx_ring->dma & 0x00000000FFFFFFFF)); +- wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32)); +- wr32(E1000_TDLEN(0), ++ E1000_WRITE_REG(hw, E1000_TDBAH(0), ((u64) tx_ring->dma >> 32)); ++ E1000_WRITE_REG(hw, E1000_TDLEN(0), + tx_ring->count * sizeof(struct e1000_tx_desc)); +- wr32(E1000_TDH(0), 0); +- wr32(E1000_TDT(0), 0); +- wr32(E1000_TCTL, ++ E1000_WRITE_REG(hw, E1000_TDH(0), 0); ++ E1000_WRITE_REG(hw, E1000_TDT(0), 0); ++ txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); ++ txdctl |= E1000_TXDCTL_QUEUE_ENABLE; ++ E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); ++ E1000_WRITE_REG(hw, E1000_TCTL, + E1000_TCTL_PSP | E1000_TCTL_EN | + E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT | + E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT); + + for (i = 0; i < tx_ring->count; i++) { + struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i); +- struct sk_buff *skb; + unsigned int size = 1024; ++ struct sk_buff *skb = alloc_skb(size, GFP_KERNEL); + +- skb = alloc_skb(size, GFP_KERNEL); + if (!skb) { + ret_val = 3; + goto err_nomem; +@@ -1314,8 +1285,8 @@ + rx_ring->count = IGB_DEFAULT_RXD; + + rx_ring->buffer_info = kcalloc(rx_ring->count, +- sizeof(struct igb_buffer), +- GFP_KERNEL); ++ sizeof(struct igb_buffer), ++ GFP_KERNEL); + if (!rx_ring->buffer_info) { + ret_val = 4; + goto err_nomem; +@@ -1323,34 +1294,37 @@ + + rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc); + rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, +- &rx_ring->dma); ++ &rx_ring->dma); + if (!rx_ring->desc) { + ret_val = 5; + goto err_nomem; + } + rx_ring->next_to_use = rx_ring->next_to_clean = 0; + +- rctl = rd32(E1000_RCTL); +- wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); +- wr32(E1000_RDBAL(0), ++ rctl = E1000_READ_REG(hw, E1000_RCTL); ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); ++ E1000_WRITE_REG(hw, E1000_RDBAL(0), + ((u64) rx_ring->dma & 0xFFFFFFFF)); +- wr32(E1000_RDBAH(0), +- ((u64) rx_ring->dma >> 32)); +- wr32(E1000_RDLEN(0), rx_ring->size); +- wr32(E1000_RDH(0), 0); +- wr32(E1000_RDT(0), 0); ++ E1000_WRITE_REG(hw, E1000_RDBAH(0), ((u64) rx_ring->dma >> 32)); ++ E1000_WRITE_REG(hw, E1000_RDLEN(0), rx_ring->size); ++ E1000_WRITE_REG(hw, E1000_RDH(0), 0); ++ E1000_WRITE_REG(hw, E1000_RDT(0), 0); ++ rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); ++ rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; ++ E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); ++ rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); + rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 | +- E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | +- (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); +- wr32(E1000_RCTL, rctl); +- wr32(E1000_SRRCTL(0), 0); ++ E1000_RCTL_RDMTS_HALF | ++ (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); ++ E1000_WRITE_REG(hw, E1000_SRRCTL(0), 0); + + for (i = 0; i < rx_ring->count; i++) { + struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i); + struct sk_buff *skb; + + skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN, +- GFP_KERNEL); ++ GFP_KERNEL); + if (!skb) { + ret_val = 6; + goto err_nomem; +@@ -1373,57 +1347,47 @@ + + static void igb_phy_disable_receiver(struct igb_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- + /* Write out to PHY registers 29 and 30 to disable the Receiver. */ +- hw->phy.ops.write_phy_reg(hw, 29, 0x001F); +- hw->phy.ops.write_phy_reg(hw, 30, 0x8FFC); +- hw->phy.ops.write_phy_reg(hw, 29, 0x001A); +- hw->phy.ops.write_phy_reg(hw, 30, 0x8FF0); ++ e1000_write_phy_reg(&adapter->hw, 29, 0x001F); ++ e1000_write_phy_reg(&adapter->hw, 30, 0x8FFC); ++ e1000_write_phy_reg(&adapter->hw, 29, 0x001A); ++ e1000_write_phy_reg(&adapter->hw, 30, 0x8FF0); + } + + static int igb_integrated_phy_loopback(struct igb_adapter *adapter) + { + struct e1000_hw *hw = &adapter->hw; + u32 ctrl_reg = 0; +- u32 stat_reg = 0; + +- hw->mac.autoneg = false; ++ hw->mac.autoneg = FALSE; + + if (hw->phy.type == e1000_phy_m88) { + /* Auto-MDI/MDIX Off */ +- hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); ++ e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); + /* reset to update Auto-MDI/MDIX */ +- hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x9140); ++ e1000_write_phy_reg(hw, PHY_CONTROL, 0x9140); + /* autoneg off */ +- hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x8140); ++ e1000_write_phy_reg(hw, PHY_CONTROL, 0x8140); + } + +- ctrl_reg = rd32(E1000_CTRL); ++ ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); + + /* force 1000, set loopback */ +- hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x4140); ++ e1000_write_phy_reg(hw, PHY_CONTROL, 0x4140); + + /* Now set up the MAC to the same speed/duplex as the PHY. */ +- ctrl_reg = rd32(E1000_CTRL); ++ ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); + ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ + ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ + E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ + E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ +- E1000_CTRL_FD); /* Force Duplex to FULL */ ++ E1000_CTRL_FD | /* Force Duplex to FULL */ ++ E1000_CTRL_SLU); /* Set link up enable bit */ + +- if (hw->phy.media_type == e1000_media_type_copper && +- hw->phy.type == e1000_phy_m88) ++ if (hw->phy.type == e1000_phy_m88) + ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ +- else { +- /* Set the ILOS bit on the fiber Nic if half duplex link is +- * detected. */ +- stat_reg = rd32(E1000_STATUS); +- if ((stat_reg & E1000_STATUS_FD) == 0) +- ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU); +- } + +- wr32(E1000_CTRL, ctrl_reg); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); + + /* Disable the receiver on the PHY so when a cable is plugged in, the + * PHY does not begin to autoneg when a cable is reconnected to the NIC. +@@ -1446,41 +1410,42 @@ + struct e1000_hw *hw = &adapter->hw; + u32 reg; + +- if (hw->phy.media_type == e1000_media_type_fiber || +- hw->phy.media_type == e1000_media_type_internal_serdes) { +- reg = rd32(E1000_RCTL); ++ if (hw->phy.media_type == e1000_media_type_internal_serdes) { ++ ++ reg = E1000_READ_REG(hw, E1000_RCTL); + reg |= E1000_RCTL_LBM_TCVR; +- wr32(E1000_RCTL, reg); ++ E1000_WRITE_REG(hw, E1000_RCTL, reg); + +- wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); ++ E1000_WRITE_REG(hw, E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); + +- reg = rd32(E1000_CTRL); ++ reg = E1000_READ_REG(hw, E1000_CTRL); + reg &= ~(E1000_CTRL_RFCE | + E1000_CTRL_TFCE | + E1000_CTRL_LRST); + reg |= E1000_CTRL_SLU | +- E1000_CTRL_FD; +- wr32(E1000_CTRL, reg); ++ E1000_CTRL_FD; ++ E1000_WRITE_REG(hw, E1000_CTRL, reg); + + /* Unset switch control to serdes energy detect */ +- reg = rd32(E1000_CONNSW); ++ reg = E1000_READ_REG(hw, E1000_CONNSW); + reg &= ~E1000_CONNSW_ENRGSRC; +- wr32(E1000_CONNSW, reg); ++ E1000_WRITE_REG(hw, E1000_CONNSW, reg); + + /* Set PCS register for forced speed */ +- reg = rd32(E1000_PCS_LCTL); ++ reg = E1000_READ_REG(hw, E1000_PCS_LCTL); + reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ + reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ + E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ + E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ + E1000_PCS_LCTL_FSD | /* Force Speed */ + E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ +- wr32(E1000_PCS_LCTL, reg); ++ E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); + + return 0; +- } else if (hw->phy.media_type == e1000_media_type_copper) { ++ } ++ ++ if (hw->phy.media_type == e1000_media_type_copper) + return igb_set_phy_loopback(adapter); +- } + + return 7; + } +@@ -1491,21 +1456,21 @@ + u32 rctl; + u16 phy_reg; + +- rctl = rd32(E1000_RCTL); ++ rctl = E1000_READ_REG(hw, E1000_RCTL); + rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); +- wr32(E1000_RCTL, rctl); ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); + +- hw->mac.autoneg = true; +- hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_reg); ++ hw->mac.autoneg = TRUE; ++ e1000_read_phy_reg(hw, PHY_CONTROL, &phy_reg); + if (phy_reg & MII_CR_LOOPBACK) { + phy_reg &= ~MII_CR_LOOPBACK; +- hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_reg); +- igb_phy_sw_reset(hw); ++ e1000_write_phy_reg(hw, PHY_CONTROL, phy_reg); ++ e1000_phy_commit(hw); + } + } + + static void igb_create_lbtest_frame(struct sk_buff *skb, +- unsigned int frame_size) ++ unsigned int frame_size) + { + memset(skb->data, 0xFF, frame_size); + frame_size &= ~1; +@@ -1517,10 +1482,12 @@ + static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size) + { + frame_size &= ~1; +- if (*(skb->data + 3) == 0xFF) ++ if (*(skb->data + 3) == 0xFF) { + if ((*(skb->data + frame_size / 2 + 10) == 0xBE) && +- (*(skb->data + frame_size / 2 + 12) == 0xAF)) ++ (*(skb->data + frame_size / 2 + 12) == 0xAF)) { + return 0; ++ } ++ } + return 13; + } + +@@ -1530,11 +1497,10 @@ + struct igb_ring *tx_ring = &adapter->test_tx_ring; + struct igb_ring *rx_ring = &adapter->test_rx_ring; + struct pci_dev *pdev = adapter->pdev; +- int i, j, k, l, lc, good_cnt; +- int ret_val = 0; ++ int i, j, k, l, lc, good_cnt, ret_val = 0; + unsigned long time; + +- wr32(E1000_RDT(0), rx_ring->count - 1); ++ E1000_WRITE_REG(hw, E1000_RDT(0), rx_ring->count - 1); + + /* Calculate the loop count based on the largest descriptor ring + * The idea is to wrap the largest ring a number of times using 64 +@@ -1550,31 +1516,30 @@ + for (j = 0; j <= lc; j++) { /* loop count loop */ + for (i = 0; i < 64; i++) { /* send the packets */ + igb_create_lbtest_frame(tx_ring->buffer_info[k].skb, +- 1024); ++ 1024); + pci_dma_sync_single_for_device(pdev, + tx_ring->buffer_info[k].dma, + tx_ring->buffer_info[k].length, + PCI_DMA_TODEVICE); +- k++; +- if (k == tx_ring->count) ++ if (unlikely(++k == tx_ring->count)) + k = 0; + } +- wr32(E1000_TDT(0), k); ++ E1000_WRITE_REG(hw, E1000_TDT(0), k); + msleep(200); ++ + time = jiffies; /* set the start time for the receive */ + good_cnt = 0; + do { /* receive the sent packets */ + pci_dma_sync_single_for_cpu(pdev, +- rx_ring->buffer_info[l].dma, +- IGB_RXBUFFER_2048, +- PCI_DMA_FROMDEVICE); ++ rx_ring->buffer_info[l].dma, ++ IGB_RXBUFFER_2048, ++ PCI_DMA_FROMDEVICE); + + ret_val = igb_check_lbtest_frame( +- rx_ring->buffer_info[l].skb, 1024); ++ rx_ring->buffer_info[l].skb, 1024); + if (!ret_val) + good_cnt++; +- l++; +- if (l == rx_ring->count) ++ if (unlikely(++l == rx_ring->count)) + l = 0; + /* time + 20 msecs (200 msecs on 2.4) is more than + * enough time to complete the receives, if it's +@@ -1597,10 +1562,9 @@ + { + /* PHY loopback cannot be performed if SoL/IDER + * sessions are active */ +- if (igb_check_reset_block(&adapter->hw)) { +- dev_err(&adapter->pdev->dev, +- "Cannot do PHY loopback test " +- "when SoL/IDER is active.\n"); ++ if (e1000_check_reset_block(&adapter->hw)) { ++ DPRINTK(DRV, ERR, "Cannot do PHY loopback test " ++ "when SoL/IDER is active.\n"); + *data = 0; + goto out; + } +@@ -1623,34 +1587,38 @@ + { + struct e1000_hw *hw = &adapter->hw; + *data = 0; +- if (hw->phy.media_type == e1000_media_type_internal_serdes) { ++ if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { + int i = 0; +- hw->mac.serdes_has_link = false; ++ adapter->hw.mac.serdes_has_link = FALSE; + + /* On some blade server designs, link establishment + * could take as long as 2-3 minutes */ + do { +- hw->mac.ops.check_for_link(&adapter->hw); +- if (hw->mac.serdes_has_link) ++ e1000_check_for_link(&adapter->hw); ++ if (adapter->hw.mac.serdes_has_link) + return *data; + msleep(20); + } while (i++ < 3750); + + *data = 1; + } else { +- hw->mac.ops.check_for_link(&adapter->hw); +- if (hw->mac.autoneg) ++ e1000_check_for_link(&adapter->hw); ++ if (adapter->hw.mac.autoneg) + msleep(4000); + +- if (!(rd32(E1000_STATUS) & +- E1000_STATUS_LU)) ++ if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) + *data = 1; + } + return *data; + } + ++static int igb_diag_test_count(struct net_device *netdev) ++{ ++ return IGB_TEST_LEN; ++} ++ + static void igb_diag_test(struct net_device *netdev, +- struct ethtool_test *eth_test, u64 *data) ++ struct ethtool_test *eth_test, u64 *data) + { + struct igb_adapter *adapter = netdev_priv(netdev); + u16 autoneg_advertised; +@@ -1666,7 +1634,7 @@ + forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; + autoneg = adapter->hw.mac.autoneg; + +- dev_info(&adapter->pdev->dev, "offline testing starting\n"); ++ DPRINTK(HW, INFO, "offline testing starting\n"); + + /* Link test performed before hardware reset so autoneg doesn't + * interfere with test result */ +@@ -1700,15 +1668,15 @@ + adapter->hw.mac.autoneg = autoneg; + + /* force this routine to wait until autoneg complete/timeout */ +- adapter->hw.phy.autoneg_wait_to_complete = true; ++ adapter->hw.phy.autoneg_wait_to_complete = TRUE; + igb_reset(adapter); +- adapter->hw.phy.autoneg_wait_to_complete = false; ++ adapter->hw.phy.autoneg_wait_to_complete = FALSE; + + clear_bit(__IGB_TESTING, &adapter->state); + if (if_running) + dev_open(netdev); + } else { +- dev_info(&adapter->pdev->dev, "online testing starting\n"); ++ DPRINTK(HW, INFO, "online testing starting\n"); + /* Online tests */ + if (igb_link_test(adapter, &data[4])) + eth_test->flags |= ETH_TEST_FL_FAILED; +@@ -1725,7 +1693,7 @@ + } + + static int igb_wol_exclusion(struct igb_adapter *adapter, +- struct ethtool_wolinfo *wol) ++ struct ethtool_wolinfo *wol) + { + struct e1000_hw *hw = &adapter->hw; + int retval = 1; /* fail by default */ +@@ -1739,7 +1707,16 @@ + case E1000_DEV_ID_82576_FIBER: + case E1000_DEV_ID_82576_SERDES: + /* Wake events not supported on port B */ +- if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) { ++ if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FUNC_1) { ++ wol->supported = 0; ++ break; ++ } ++ /* return success for non excluded adapter ports */ ++ retval = 0; ++ break; ++ case E1000_DEV_ID_82576_QUAD_COPPER: ++ /* quad port adapters only support WoL on port A */ ++ if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) { + wol->supported = 0; + break; + } +@@ -1750,7 +1727,7 @@ + /* dual port cards only support WoL on port A from now on + * unless it was enabled in the eeprom for port B + * so exclude FUNC_1 ports from having WoL enabled */ +- if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 && ++ if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FUNC_1 && + !adapter->eeprom_wol) { + wol->supported = 0; + break; +@@ -1767,7 +1744,7 @@ + struct igb_adapter *adapter = netdev_priv(netdev); + + wol->supported = WAKE_UCAST | WAKE_MCAST | +- WAKE_BCAST | WAKE_MAGIC; ++ WAKE_BCAST | WAKE_MAGIC; + wol->wolopts = 0; + + /* this function will set ->supported = 0 and return 1 if wol is not +@@ -1797,19 +1774,12 @@ + static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) + { + struct igb_adapter *adapter = netdev_priv(netdev); +- struct e1000_hw *hw = &adapter->hw; + + if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) + return -EOPNOTSUPP; + +- if (igb_wol_exclusion(adapter, wol) || +- !device_can_wakeup(&adapter->pdev->dev)) ++ if (igb_wol_exclusion(adapter, wol)) + return wol->wolopts ? -EOPNOTSUPP : 0; +- +- switch (hw->device_id) { +- default: +- break; +- } + + /* these settings will always override what we currently have */ + adapter->wol = 0; +@@ -1822,7 +1792,6 @@ + adapter->wol |= E1000_WUFC_BC; + if (wol->wolopts & WAKE_MAGIC) + adapter->wol |= E1000_WUFC_MAG; +- + device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); + + return 0; +@@ -1842,12 +1811,12 @@ + if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)) + data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ); + +- igb_blink_led(hw); ++ e1000_blink_led(hw); + msleep_interruptible(data * 1000); + +- igb_led_off(hw); ++ e1000_led_off(hw); + clear_bit(IGB_LED_ON, &adapter->led_status); +- igb_cleanup_led(hw); ++ e1000_cleanup_led(hw); + + return 0; + } +@@ -1867,15 +1836,16 @@ + + /* convert to rate of irq's per second */ + if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) { ++ adapter->itr = IGB_START_ITR; + adapter->itr_setting = ec->rx_coalesce_usecs; +- adapter->itr = IGB_START_ITR; + } else { +- adapter->itr_setting = ec->rx_coalesce_usecs << 2; +- adapter->itr = adapter->itr_setting; ++ adapter->itr = ec->rx_coalesce_usecs << 2; ++ adapter->itr_setting = adapter->itr; + } + + for (i = 0; i < adapter->num_rx_queues; i++) +- wr32(adapter->rx_ring[i].itr_register, adapter->itr); ++ writel(adapter->itr, ++ hw->hw_addr + adapter->rx_ring[i].itr_register); + + return 0; + } +@@ -1893,7 +1863,6 @@ + return 0; + } + +- + static int igb_nway_reset(struct net_device *netdev) + { + struct igb_adapter *adapter = netdev_priv(netdev); +@@ -1902,27 +1871,20 @@ + return 0; + } + +-static int igb_get_sset_count(struct net_device *netdev, int sset) ++static int igb_get_stats_count(struct net_device *netdev) + { +- switch (sset) { +- case ETH_SS_STATS: +- return IGB_STATS_LEN; +- case ETH_SS_TEST: +- return IGB_TEST_LEN; +- default: +- return -ENOTSUPP; +- } ++ return IGB_STATS_LEN; + } + + static void igb_get_ethtool_stats(struct net_device *netdev, +- struct ethtool_stats *stats, u64 *data) ++ struct ethtool_stats *stats, u64 *data) + { + struct igb_adapter *adapter = netdev_priv(netdev); + u64 *queue_stat; + int stat_count = sizeof(struct igb_queue_stats) / sizeof(u64); + int j; + int i; +-#ifdef CONFIG_IGB_LRO ++#ifdef IGB_LRO + int aggregated = 0, flushed = 0, no_desc = 0; + + for (i = 0; i < adapter->num_rx_queues; i++) { +@@ -1936,6 +1898,7 @@ + #endif + + igb_update_stats(adapter); ++ + for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { + char *p = (char *)adapter+igb_gstrings_stats[i].stat_offset; + data[i] = (igb_gstrings_stats[i].sizeof_stat == +@@ -2016,17 +1979,23 @@ + .set_tx_csum = igb_set_tx_csum, + .get_sg = ethtool_op_get_sg, + .set_sg = ethtool_op_set_sg, ++#ifdef NETIF_F_TSO + .get_tso = ethtool_op_get_tso, + .set_tso = igb_set_tso, ++#endif ++ .self_test_count = igb_diag_test_count, + .self_test = igb_diag_test, + .get_strings = igb_get_strings, + .phys_id = igb_phys_id, +- .get_sset_count = igb_get_sset_count, ++ .get_stats_count = igb_get_stats_count, + .get_ethtool_stats = igb_get_ethtool_stats, ++#ifdef ETHTOOL_GPERMADDR ++ .get_perm_addr = ethtool_op_get_perm_addr, ++#endif + .get_coalesce = igb_get_coalesce, + .set_coalesce = igb_set_coalesce, ++#ifdef NETIF_F_LRO + .get_flags = ethtool_op_get_flags, +-#ifdef CONFIG_IGB_LRO + .set_flags = ethtool_op_set_flags, + #endif + }; +@@ -2035,3 +2004,4 @@ + { + SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops); + } ++#endif /* SIOCETHTOOL */ +diff -r 4f0f8bc35440 drivers/net/igb/igb_main.c +--- a/drivers/net/igb/igb_main.c Wed Aug 05 11:02:57 2009 +0100 ++++ b/drivers/net/igb/igb_main.c Wed Aug 05 11:03:37 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel(R) Gigabit Ethernet Linux driver +- Copyright(c) 2007 Intel Corporation. ++ Copyright(c) 2007-2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -31,39 +31,46 @@ + #include + #include + #include ++#include ++#ifdef NETIF_F_TSO ++#include ++#ifdef NETIF_F_TSO6 + #include +-#include + #include ++#endif ++#endif ++#ifdef SIOCGMIIPHY + #include ++#endif ++#ifdef SIOCETHTOOL + #include ++#endif + #include +-#include +-#include +-#include +-#include +-#ifdef CONFIG_DCA +-#include +-#endif ++ + #include "igb.h" + +-#define DRV_VERSION "1.2.45-k2" ++#define DRV_DEBUG ++#define DRV_HW_PERF ++#define VERSION_SUFFIX ++ ++#define DRV_VERSION "1.3.28.4" VERSION_SUFFIX DRV_DEBUG DRV_HW_PERF ++ + char igb_driver_name[] = "igb"; + char igb_driver_version[] = DRV_VERSION; + static const char igb_driver_string[] = +- "Intel(R) Gigabit Ethernet Network Driver"; +-static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation."; +- +-static const struct e1000_info *igb_info_tbl[] = { +- [board_82575] = &e1000_82575_info, +-}; ++ "Intel(R) Gigabit Ethernet Network Driver"; ++static const char igb_copyright[] = "Copyright (c) 2007-2008 Intel Corporation."; + + static struct pci_device_id igb_pci_tbl[] = { +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576) }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS) }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER) }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES) }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD) }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER) }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER) }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES) }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER) }, + /* required last entry */ + {0, } + }; +@@ -93,7 +100,7 @@ + static void igb_watchdog(unsigned long); + static void igb_watchdog_task(struct work_struct *); + static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *, +- struct igb_ring *); ++ struct igb_ring *); + static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *); + static struct net_device_stats *igb_get_stats(struct net_device *); + static int igb_change_mtu(struct net_device *, int); +@@ -102,18 +109,19 @@ + static irqreturn_t igb_intr_msi(int irq, void *); + static irqreturn_t igb_msix_other(int irq, void *); + static irqreturn_t igb_msix_rx(int irq, void *); ++#ifdef CONFIG_IGB_SEPARATE_TX_HANDLER + static irqreturn_t igb_msix_tx(int irq, void *); +-static int igb_clean_rx_ring_msix(struct napi_struct *, int); +-#ifdef CONFIG_DCA ++#endif ++#ifdef IGB_DCA + static void igb_update_rx_dca(struct igb_ring *); + static void igb_update_tx_dca(struct igb_ring *); + static void igb_setup_dca(struct igb_adapter *); +-#endif /* CONFIG_DCA */ ++#endif /* IGB_DCA */ + static bool igb_clean_tx_irq(struct igb_ring *); + static int igb_poll(struct napi_struct *, int); + static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int); + static void igb_alloc_rx_buffers_adv(struct igb_ring *, int); +-#ifdef CONFIG_IGB_LRO ++#ifdef IGB_LRO + static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *); + #endif + static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); +@@ -128,8 +136,17 @@ + #ifdef CONFIG_PM + static int igb_resume(struct pci_dev *); + #endif ++#ifndef USE_REBOOT_NOTIFIER + static void igb_shutdown(struct pci_dev *); +-#ifdef CONFIG_DCA ++#else ++static int igb_notify_reboot(struct notifier_block *, unsigned long, void *); ++static struct notifier_block igb_notifier_reboot = { ++ .notifier_call = igb_notify_reboot, ++ .next = NULL, ++ .priority = 0 ++}; ++#endif ++#ifdef IGB_DCA + static int igb_notify_dca(struct notifier_block *, unsigned long, void *); + static struct notifier_block dca_notifier = { + .notifier_call = igb_notify_dca, +@@ -140,11 +157,12 @@ + + #ifdef CONFIG_NET_POLL_CONTROLLER + /* for netdump / net console */ +-static void igb_netpoll(struct net_device *); +-#endif +- ++static void igb_netpoll (struct net_device *); ++#endif ++ ++#ifdef HAVE_PCI_ERS + static pci_ers_result_t igb_io_error_detected(struct pci_dev *, +- pci_channel_state_t); ++ pci_channel_state_t); + static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); + static void igb_io_resume(struct pci_dev *); + +@@ -153,6 +171,7 @@ + .slot_reset = igb_io_slot_reset, + .resume = igb_io_resume, + }; ++#endif + + + static struct pci_driver igb_driver = { +@@ -165,28 +184,22 @@ + .suspend = igb_suspend, + .resume = igb_resume, + #endif ++#ifndef USE_REBOOT_NOTIFIER + .shutdown = igb_shutdown, +- .err_handler = &igb_err_handler +-}; +- +-static int global_quad_port_a; /* global quad port a indication */ ++#endif ++#ifdef HAVE_PCI_ERS ++ .err_handler = &igb_err_handler, ++#endif ++}; + + MODULE_AUTHOR("Intel Corporation, "); + MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); + MODULE_LICENSE("GPL"); + MODULE_VERSION(DRV_VERSION); + +-#ifdef DEBUG +-/** +- * igb_get_hw_dev_name - return device name string +- * used by hardware layer to print debugging information +- **/ +-char *igb_get_hw_dev_name(struct e1000_hw *hw) +-{ +- struct igb_adapter *adapter = hw->back; +- return adapter->netdev->name; +-} +-#endif ++static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE; ++module_param(debug, int, 0); ++MODULE_PARM_DESC(debug, "Debug level (0=none, ..., 16=all)"); + + /** + * igb_init_module - Driver Registration Routine +@@ -202,11 +215,14 @@ + + printk(KERN_INFO "%s\n", igb_copyright); + +- global_quad_port_a = 0; +- ++#ifdef IGB_DCA ++ dca_register_notify(&dca_notifier); ++#endif + ret = pci_register_driver(&igb_driver); +-#ifdef CONFIG_DCA +- dca_register_notify(&dca_notifier); ++#ifdef USE_REBOOT_NOTIFIER ++ if (ret >= 0) { ++ register_reboot_notifier(&igb_notifier_reboot); ++ } + #endif + return ret; + } +@@ -221,13 +237,52 @@ + **/ + static void __exit igb_exit_module(void) + { +-#ifdef CONFIG_DCA ++#ifdef IGB_DCA + dca_unregister_notify(&dca_notifier); + #endif ++#ifdef USE_REBOOT_NOTIFIER ++ unregister_reboot_notifier(&igb_notifier_reboot); ++#endif + pci_unregister_driver(&igb_driver); + } + + module_exit(igb_exit_module); ++ ++/** ++ * igb_cache_ring_register - Descriptor ring to register mapping ++ * @adapter: board private structure to initialize ++ * ++ * Once we know the feature-set enabled for the device, we'll cache ++ * the register offset the descriptor ring is assigned to. ++ **/ ++static void igb_cache_ring_register(struct igb_adapter *adapter) ++{ ++ int i; ++ u32 rbase_offset = 0; ++ ++ switch (adapter->hw.mac.type) { ++ case e1000_82576: ++ /* The queues are allocated for virtualization such that VF 0 ++ * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. ++ * In order to avoid collision we start at the first free queue ++ * and continue consuming queues in the same sequence ++ */ ++ for (i = 0; i < adapter->num_rx_queues; i++) ++ adapter->rx_ring[i].reg_idx = rbase_offset + ++ ((i & 0x1) << 3) + (i >> 1); ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ adapter->tx_ring[i].reg_idx = rbase_offset + ++ ((i & 0x1) << 3) + (i >> 1); ++ break; ++ case e1000_82575: ++ default: ++ for (i = 0; i < adapter->num_rx_queues; i++) ++ adapter->rx_ring[i].reg_idx = i; ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ adapter->tx_ring[i].reg_idx = i; ++ break; ++ } ++} + + /** + * igb_alloc_queues - Allocate memory for all rings +@@ -241,16 +296,14 @@ + int i; + + adapter->tx_ring = kcalloc(adapter->num_tx_queues, +- sizeof(struct igb_ring), GFP_KERNEL); ++ sizeof(struct igb_ring), GFP_KERNEL); + if (!adapter->tx_ring) +- return -ENOMEM; ++ goto err; + + adapter->rx_ring = kcalloc(adapter->num_rx_queues, +- sizeof(struct igb_ring), GFP_KERNEL); +- if (!adapter->rx_ring) { +- kfree(adapter->tx_ring); +- return -ENOMEM; +- } ++ sizeof(struct igb_ring), GFP_KERNEL); ++ if (!adapter->rx_ring) ++ goto err; + + adapter->rx_ring->buddy = adapter->tx_ring; + +@@ -266,27 +319,74 @@ + ring->adapter = adapter; + ring->queue_index = i; + ring->itr_register = E1000_ITR; +- + /* set a default napi handler for each rx_ring */ + netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64); + } +- return 0; +-} +- +-static void igb_free_queues(struct igb_adapter *adapter) +-{ +- int i; +- +- for (i = 0; i < adapter->num_rx_queues; i++) +- netif_napi_del(&adapter->rx_ring[i].napi); +- ++ ++ igb_cache_ring_register(adapter); ++ ++ return E1000_SUCCESS; ++ ++err: + kfree(adapter->tx_ring); + kfree(adapter->rx_ring); ++ ++ return -ENOMEM; ++} ++ ++static void igb_free_queues(struct igb_adapter *adapter) ++{ ++ int i; ++ ++ for (i = 0; i < adapter->num_rx_queues; i++) ++ netif_napi_del(&adapter->rx_ring[i].napi); ++ ++ adapter->num_rx_queues = 0; ++ adapter->num_tx_queues = 0; ++ ++ kfree(adapter->tx_ring); ++ kfree(adapter->rx_ring); ++} ++ ++static void igb_configure_lli(struct igb_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u16 port; ++ ++ /* LLI should only be enabled for MSI-X or MSI interrupts */ ++ if (!adapter->msix_entries && !(adapter->flags & IGB_FLAG_HAS_MSI)) ++ return; ++ ++ if (adapter->lli_port) { ++ /* use filter 0 for port */ ++ port = ntohs((u16)adapter->lli_port); ++ E1000_WRITE_REG(hw, E1000_IMIR(0), ++ (port | E1000_IMIR_PORT_IM_EN)); ++ E1000_WRITE_REG(hw, E1000_IMIREXT(0), ++ (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); ++ } ++ ++ if (adapter->flags & IGB_FLAG_LLI_PUSH) { ++ /* use filter 1 for push flag */ ++ E1000_WRITE_REG(hw, E1000_IMIR(1), ++ (E1000_IMIR_PORT_BP | E1000_IMIR_PORT_IM_EN)); ++ E1000_WRITE_REG(hw, E1000_IMIREXT(1), ++ (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_PSH)); ++ } ++ ++ if (adapter->lli_size) { ++ /* use filter 2 for size */ ++ E1000_WRITE_REG(hw, E1000_IMIR(2), ++ (E1000_IMIR_PORT_BP | E1000_IMIR_PORT_IM_EN)); ++ E1000_WRITE_REG(hw, E1000_IMIREXT(2), ++ (adapter->lli_size | E1000_IMIREXT_CTRL_BP)); ++ } ++ + } + + #define IGB_N0_QUEUE -1 + static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, +- int tx_queue, int msix_vector) ++ int tx_queue, int msix_vector) + { + u32 msixbm = 0; + struct e1000_hw *hw = &adapter->hw; +@@ -305,44 +405,44 @@ + if (tx_queue > IGB_N0_QUEUE) { + msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; + adapter->tx_ring[tx_queue].eims_value = +- E1000_EICR_TX_QUEUE0 << tx_queue; +- } +- array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); +- break; +- case e1000_82576: +- /* The 82576 uses a table-based method for assigning vectors. ++ E1000_EICR_TX_QUEUE0 << tx_queue; ++ } ++ E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), msix_vector, msixbm); ++ break; ++ case e1000_82576: ++ /* 82576 uses a table-based method for assigning vectors. + Each queue has a single entry in the table to which we write + a vector number along with a "valid" bit. Sadly, the layout + of the table is somewhat counterintuitive. */ + if (rx_queue > IGB_N0_QUEUE) { +- index = (rx_queue & 0x7); +- ivar = array_rd32(E1000_IVAR0, index); +- if (rx_queue < 8) { ++ index = (rx_queue >> 1); ++ ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); ++ if (rx_queue & 0x1) { ++ /* vector goes into third byte of register */ ++ ivar = ivar & 0xFF00FFFF; ++ ivar |= (msix_vector | E1000_IVAR_VALID) << 16; ++ } else { + /* vector goes into low byte of register */ + ivar = ivar & 0xFFFFFF00; + ivar |= msix_vector | E1000_IVAR_VALID; ++ } ++ adapter->rx_ring[rx_queue].eims_value = 1 << msix_vector; ++ E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); ++ } ++ if (tx_queue > IGB_N0_QUEUE) { ++ index = (tx_queue >> 1); ++ ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); ++ if (tx_queue & 0x1) { ++ /* vector goes into high byte of register */ ++ ivar = ivar & 0x00FFFFFF; ++ ivar |= (msix_vector | E1000_IVAR_VALID) << 24; + } else { +- /* vector goes into third byte of register */ +- ivar = ivar & 0xFF00FFFF; +- ivar |= (msix_vector | E1000_IVAR_VALID) << 16; +- } +- adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector; +- array_wr32(E1000_IVAR0, index, ivar); +- } +- if (tx_queue > IGB_N0_QUEUE) { +- index = (tx_queue & 0x7); +- ivar = array_rd32(E1000_IVAR0, index); +- if (tx_queue < 8) { + /* vector goes into second byte of register */ + ivar = ivar & 0xFFFF00FF; + ivar |= (msix_vector | E1000_IVAR_VALID) << 8; +- } else { +- /* vector goes into high byte of register */ +- ivar = ivar & 0x00FFFFFF; +- ivar |= (msix_vector | E1000_IVAR_VALID) << 24; +- } +- adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector; +- array_wr32(E1000_IVAR0, index, ivar); ++ } ++ adapter->tx_ring[tx_queue].eims_value = 1 << msix_vector; ++ E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); + } + break; + default: +@@ -367,10 +467,11 @@ + if (hw->mac.type == e1000_82576) + /* Turn on MSI-X capability first, or our settings + * won't stick. And it will take days to debug. */ +- wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | +- E1000_GPIE_PBA | E1000_GPIE_EIAME | +- E1000_GPIE_NSICR); +- ++ E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE | ++ E1000_GPIE_PBA | E1000_GPIE_EIAME | ++ E1000_GPIE_NSICR); ++ ++#ifdef CONFIG_IGB_SEPARATE_TX_HANDLER + for (i = 0; i < adapter->num_tx_queues; i++) { + struct igb_ring *tx_ring = &adapter->tx_ring[i]; + igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++); +@@ -394,14 +495,33 @@ + writel(1, hw->hw_addr + rx_ring->itr_register); + } + ++#else ++ for (i = 0; i < adapter->num_rx_queues; i++) { ++ struct igb_ring *rx_ring = &adapter->rx_ring[i]; ++ if (i < adapter->num_tx_queues) { ++ igb_assign_vector(adapter, i, i, vector++); ++ rx_ring->buddy = &adapter->tx_ring[i]; ++ rx_ring->eims_value |= adapter->tx_ring[i].eims_value; ++ } else { ++ igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++); ++ } ++ adapter->eims_enable_mask |= rx_ring->eims_value; ++ if (rx_ring->itr_val) ++ writel(rx_ring->itr_val, ++ hw->hw_addr + rx_ring->itr_register); ++ else ++ writel(1, hw->hw_addr + rx_ring->itr_register); ++ } ++ ++#endif + + /* set vector for other causes, i.e. link changes */ + switch (hw->mac.type) { + case e1000_82575: +- array_wr32(E1000_MSIXBM(0), vector++, +- E1000_EIMS_OTHER); +- +- tmp = rd32(E1000_CTRL_EXT); ++ E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), vector++, ++ E1000_EIMS_OTHER); ++ ++ tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); + /* enable MSI-X PBA support*/ + tmp |= E1000_CTRL_EXT_PBA_CLR; + +@@ -409,7 +529,7 @@ + tmp |= E1000_CTRL_EXT_EIAME; + tmp |= E1000_CTRL_EXT_IRCA; + +- wr32(E1000_CTRL_EXT, tmp); ++ E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); + adapter->eims_enable_mask |= E1000_EIMS_OTHER; + adapter->eims_other = E1000_EIMS_OTHER; + +@@ -417,7 +537,7 @@ + + case e1000_82576: + tmp = (vector++ | E1000_IVAR_VALID) << 8; +- wr32(E1000_IVAR_MISC, tmp); ++ E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmp); + + adapter->eims_enable_mask = (1 << (vector)) - 1; + adapter->eims_other = 1 << (vector - 1); +@@ -426,7 +546,7 @@ + /* do nothing, since nothing else supports MSI-X */ + break; + } /* switch (hw->mac.type) */ +- wrfl(); ++ E1000_WRITE_FLUSH(hw); + } + + /** +@@ -440,41 +560,42 @@ + struct net_device *netdev = adapter->netdev; + int i, err = 0, vector = 0; + +- vector = 0; +- ++#ifdef CONFIG_IGB_SEPARATE_TX_HANDLER + for (i = 0; i < adapter->num_tx_queues; i++) { + struct igb_ring *ring = &(adapter->tx_ring[i]); +- sprintf(ring->name, "%s-tx%d", netdev->name, i); ++ sprintf(ring->name, "%s-tx-%d", netdev->name, i); + err = request_irq(adapter->msix_entries[vector].vector, +- &igb_msix_tx, 0, ring->name, +- &(adapter->tx_ring[i])); ++ &igb_msix_tx, 0, ring->name, ++ &(adapter->tx_ring[i])); + if (err) + goto out; +- ring->itr_register = E1000_EITR(0) + (vector << 2); +- ring->itr_val = 976; /* ~4000 ints/sec */ ++ ring->itr_register = E1000_EITR(vector); ++ ring->itr_val = 1952; /* ~2000 ints/sec */ + vector++; + } ++#endif + for (i = 0; i < adapter->num_rx_queues; i++) { + struct igb_ring *ring = &(adapter->rx_ring[i]); + if (strlen(netdev->name) < (IFNAMSIZ - 5)) +- sprintf(ring->name, "%s-rx%d", netdev->name, i); ++#ifdef CONFIG_IGB_SEPARATE_TX_HANDLER ++ sprintf(ring->name, "%s-rx-%d", netdev->name, i); ++#else ++ sprintf(ring->name, "%s-TxRx-%d", netdev->name, i); ++#endif + else + memcpy(ring->name, netdev->name, IFNAMSIZ); + err = request_irq(adapter->msix_entries[vector].vector, +- &igb_msix_rx, 0, ring->name, +- &(adapter->rx_ring[i])); ++ &igb_msix_rx, 0, ring->name, ++ &(adapter->rx_ring[i])); + if (err) + goto out; +- ring->itr_register = E1000_EITR(0) + (vector << 2); ++ ring->itr_register = E1000_EITR(vector); + ring->itr_val = adapter->itr; +- /* overwrite the poll routine for MSIX, we've already done +- * netif_napi_add */ +- ring->napi.poll = &igb_clean_rx_ring_msix; + vector++; + } + + err = request_irq(adapter->msix_entries[vector].vector, +- &igb_msix_other, 0, netdev->name, netdev); ++ &igb_msix_other, 0, netdev->name, netdev); + if (err) + goto out; + +@@ -506,33 +627,67 @@ + { + int err; + int numvecs, i; +- +- numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1; +- adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), +- GFP_KERNEL); +- if (!adapter->msix_entries) +- goto msi_only; +- +- for (i = 0; i < numvecs; i++) +- adapter->msix_entries[i].entry = i; +- +- err = pci_enable_msix(adapter->pdev, +- adapter->msix_entries, +- numvecs); +- if (err == 0) +- goto out; +- +- igb_reset_interrupt_capability(adapter); +- +- /* If we can't do MSI-X, try MSI */ +-msi_only: +- adapter->num_rx_queues = 1; ++#ifndef CONFIG_IGB_SEPARATE_TX_HANDLER ++ struct e1000_hw *hw = &adapter->hw; ++#endif ++ ++ /* Number of supported queues. */ ++ adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus()); ++#ifdef HAVE_TX_MQ ++ adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus()); ++#else + adapter->num_tx_queues = 1; +- if (!pci_enable_msi(adapter->pdev)) +- adapter->flags |= IGB_FLAG_HAS_MSI; +-out: ++#endif ++ ++ switch (adapter->int_mode) { ++ case IGB_INT_MODE_MSIX_1Q: ++ adapter->num_rx_queues = 1; ++ adapter->num_tx_queues = 1; ++ case IGB_INT_MODE_MSIX_MQ: ++#ifdef CONFIG_IGB_SEPARATE_TX_HANDLER ++ numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1; ++#else ++ numvecs = adapter->num_rx_queues + 1; ++#endif ++ adapter->msix_entries = kcalloc(numvecs, ++ sizeof(struct msix_entry), ++ GFP_KERNEL); ++ if (adapter->msix_entries) { ++ for (i = 0; i < numvecs; i++) ++ adapter->msix_entries[i].entry = i; ++ ++ err = pci_enable_msix(adapter->pdev, ++ adapter->msix_entries, numvecs); ++ if (err == 0) ++ break; ++ } ++ /* MSI-X failed, so fall through and try MSI */ ++ DPRINTK(PROBE, WARNING, "Failed to initialize MSI-X interrupts." ++ " Falling back to MSI interrupts.\n"); ++ igb_reset_interrupt_capability(adapter); ++ case IGB_INT_MODE_MSI: ++ if (!pci_enable_msi(adapter->pdev)) ++ adapter->flags |= IGB_FLAG_HAS_MSI; ++ else ++ DPRINTK(PROBE, WARNING, "Failed to initialize MSI " ++ "interrupts. Falling back to legacy interrupts.\n"); ++ /* Fall through */ ++ case IGB_INT_MODE_LEGACY: ++ adapter->num_rx_queues = 1; ++ adapter->num_tx_queues = 1; ++ /* Don't do anything; this is system default */ ++ break; ++ } ++ ++#ifdef HAVE_TX_MQ + /* Notify the stack of the (possibly) reduced Tx Queue count. */ ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ adapter->netdev->egress_subqueue_count = adapter->num_tx_queues; ++#else + adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; ++#endif ++#endif ++ + return; + } + +@@ -563,33 +718,35 @@ + } else { + switch (hw->mac.type) { + case e1000_82575: +- wr32(E1000_MSIXBM(0), +- (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER)); ++ E1000_WRITE_REG(hw, E1000_MSIXBM(0), ++ (E1000_EICR_RX_QUEUE0 | ++ E1000_EIMS_OTHER)); + break; + case e1000_82576: +- wr32(E1000_IVAR0, E1000_IVAR_VALID); ++ E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID); + break; + default: + break; + } + } +- + if (adapter->flags & IGB_FLAG_HAS_MSI) { + err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0, +- netdev->name, netdev); ++ netdev->name, netdev); + if (!err) + goto request_done; ++ + /* fall back to legacy interrupts */ + igb_reset_interrupt_capability(adapter); + adapter->flags &= ~IGB_FLAG_HAS_MSI; + } + + err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED, +- netdev->name, netdev); +- +- if (err) +- dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n", +- err); ++ netdev->name, netdev); ++ ++ if (err) { ++ DPRINTK(PROBE, ERR, "Error %d getting interrupt\n", err); ++ goto request_done; ++ } + + request_done: + return err; +@@ -602,9 +759,11 @@ + if (adapter->msix_entries) { + int vector = 0, i; + ++#ifdef CONFIG_IGB_SEPARATE_TX_HANDLER + for (i = 0; i < adapter->num_tx_queues; i++) + free_irq(adapter->msix_entries[vector++].vector, + &(adapter->tx_ring[i])); ++#endif + for (i = 0; i < adapter->num_rx_queues; i++) + free_irq(adapter->msix_entries[vector++].vector, + &(adapter->rx_ring[i])); +@@ -625,14 +784,15 @@ + struct e1000_hw *hw = &adapter->hw; + + if (adapter->msix_entries) { +- wr32(E1000_EIAM, 0); +- wr32(E1000_EIMC, ~0); +- wr32(E1000_EIAC, 0); +- } +- +- wr32(E1000_IAM, 0); +- wr32(E1000_IMC, ~0); +- wrfl(); ++ E1000_WRITE_REG(hw, E1000_EIAM, 0); ++ E1000_WRITE_REG(hw, E1000_EIMC, ~0); ++ E1000_WRITE_REG(hw, E1000_EIAC, 0); ++ } ++ ++ E1000_WRITE_REG(hw, E1000_IAM, 0); ++ E1000_WRITE_REG(hw, E1000_IMC, ~0); ++ E1000_WRITE_FLUSH(hw); ++ + synchronize_irq(adapter->pdev->irq); + } + +@@ -645,13 +805,14 @@ + struct e1000_hw *hw = &adapter->hw; + + if (adapter->msix_entries) { +- wr32(E1000_EIAC, adapter->eims_enable_mask); +- wr32(E1000_EIAM, adapter->eims_enable_mask); +- wr32(E1000_EIMS, adapter->eims_enable_mask); +- wr32(E1000_IMS, E1000_IMS_LSC); +- } else { +- wr32(E1000_IMS, IMS_ENABLE_MASK); +- wr32(E1000_IAM, IMS_ENABLE_MASK); ++ u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC; ++ E1000_WRITE_REG(hw, E1000_EIAC, adapter->eims_enable_mask); ++ E1000_WRITE_REG(hw, E1000_EIAM, adapter->eims_enable_mask); ++ E1000_WRITE_REG(hw, E1000_EIMS, adapter->eims_enable_mask); ++ E1000_WRITE_REG(hw, E1000_IMS, ims); ++ } else { ++ E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); ++ E1000_WRITE_REG(hw, E1000_IAM, IMS_ENABLE_MASK); + } + } + +@@ -693,11 +854,10 @@ + u32 ctrl_ext; + + /* Let firmware take over control of h/w */ +- ctrl_ext = rd32(E1000_CTRL_EXT); +- wr32(E1000_CTRL_EXT, +- ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); +-} +- ++ ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); ++ E1000_WRITE_REG(hw, E1000_CTRL_EXT, ++ ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); ++} + + /** + * igb_get_hw_control - get control of the h/w from f/w +@@ -714,9 +874,9 @@ + u32 ctrl_ext; + + /* Let firmware know the driver has taken over */ +- ctrl_ext = rd32(E1000_CTRL_EXT); +- wr32(E1000_CTRL_EXT, +- ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); ++ ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); ++ E1000_WRITE_REG(hw, E1000_CTRL_EXT, ++ ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); + } + + /** +@@ -737,8 +897,14 @@ + igb_setup_rctl(adapter); + igb_configure_rx(adapter); + +- igb_rx_fifo_flush_82575(&adapter->hw); +- ++ e1000_rx_fifo_flush_82575(&adapter->hw); ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ if (adapter->num_tx_queues > 1) ++ netdev->features |= NETIF_F_MULTI_QUEUE; ++ else ++ netdev->features &= ~NETIF_F_MULTI_QUEUE; ++ ++#endif + /* call IGB_DESC_UNUSED which always leaves + * at least 1 descriptor unused to make sure + * next_to_use != next_to_clean */ +@@ -756,7 +922,6 @@ + * igb_up - Open the interface and prepare it to handle traffic + * @adapter: board private structure + **/ +- + int igb_up(struct igb_adapter *adapter) + { + struct e1000_hw *hw = &adapter->hw; +@@ -772,19 +937,21 @@ + if (adapter->msix_entries) + igb_configure_msix(adapter); + ++ igb_configure_lli(adapter); ++ + /* Clear any pending interrupts. */ +- rd32(E1000_ICR); ++ E1000_READ_REG(hw, E1000_ICR); + igb_irq_enable(adapter); + + /* Fire a link change interrupt to start the watchdog. */ +- wr32(E1000_ICS, E1000_ICS_LSC); ++ E1000_WRITE_REG(hw, E1000_ICS, E1000_ICS_LSC); + return 0; + } + + void igb_down(struct igb_adapter *adapter) + { +- struct e1000_hw *hw = &adapter->hw; +- struct net_device *netdev = adapter->netdev; ++ struct net_device *netdev = adapter->netdev; ++ struct e1000_hw *hw = &adapter->hw; + u32 tctl, rctl; + int i; + +@@ -793,18 +960,18 @@ + set_bit(__IGB_DOWN, &adapter->state); + + /* disable receives in the hardware */ +- rctl = rd32(E1000_RCTL); +- wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); ++ rctl = E1000_READ_REG(hw, E1000_RCTL); ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); + /* flush and sleep below */ + + netif_tx_stop_all_queues(netdev); + + /* disable transmits in the hardware */ +- tctl = rd32(E1000_TCTL); ++ tctl = E1000_READ_REG(hw, E1000_TCTL); + tctl &= ~E1000_TCTL_EN; +- wr32(E1000_TCTL, tctl); ++ E1000_WRITE_REG(hw, E1000_TCTL, tctl); + /* flush both disables and wait for them to finish */ +- wrfl(); ++ E1000_WRITE_FLUSH(hw); + msleep(10); + + for (i = 0; i < adapter->num_rx_queues; i++) +@@ -817,13 +984,33 @@ + + netdev->tx_queue_len = adapter->tx_queue_len; + netif_carrier_off(netdev); ++ ++ /* record the stats before reset*/ ++ igb_update_stats(adapter); ++ + adapter->link_speed = 0; + adapter->link_duplex = 0; + ++#ifdef IGB_DCA ++ if (adapter->flags & IGB_FLAG_DCA_ENABLED) { ++ adapter->flags &= ~IGB_FLAG_DCA_ENABLED; ++ dca_remove_requester(&adapter->pdev->dev); ++ } ++ ++#endif ++#ifdef HAVE_PCI_ERS + if (!pci_channel_offline(adapter->pdev)) + igb_reset(adapter); ++#else ++ igb_reset(adapter); ++#endif + igb_clean_all_tx_rings(adapter); + igb_clean_all_rx_rings(adapter); ++#ifdef IGB_DCA ++ ++ /* since we reset the hardware DCA settings were cleared */ ++ igb_setup_dca(adapter); ++#endif + } + + void igb_reinit_locked(struct igb_adapter *adapter) +@@ -847,17 +1034,20 @@ + /* Repartition Pba for greater than 9k mtu + * To take effect CTRL.RST is required. + */ +- if (mac->type != e1000_82576) { +- pba = E1000_PBA_34K; +- } +- else { ++ switch (mac->type) { ++ case e1000_82576: + pba = E1000_PBA_64K; ++ break; ++ case e1000_82575: ++ default: ++ pba = E1000_PBA_34K; ++ break; + } + + if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && + (mac->type < e1000_82576)) { + /* adjust PBA for jumbo frames */ +- wr32(E1000_PBA, pba); ++ E1000_WRITE_REG(hw, E1000_PBA, pba); + + /* To maintain wire speed transmits, the Tx FIFO should be + * large enough to accommodate two full transmit packets, +@@ -865,7 +1055,7 @@ + * the Rx FIFO should be large enough to accommodate at least + * one full receive packet and is similarly rounded up and + * expressed in KB. */ +- pba = rd32(E1000_PBA); ++ pba = E1000_READ_REG(hw, E1000_PBA); + /* upper 16 bits has Tx packet buffer allocation size in KB */ + tx_space = pba >> 16; + /* lower 16 bits has Rx packet buffer allocation size in KB */ +@@ -873,8 +1063,8 @@ + /* the tx fifo also stores 16 bytes of information about the tx + * but don't include ethernet FCS because hardware appends it */ + min_tx_space = (adapter->max_frame_size + +- sizeof(struct e1000_tx_desc) - +- ETH_FCS_LEN) * 2; ++ sizeof(struct e1000_tx_desc) - ++ ETH_FCS_LEN) * 2; + min_tx_space = ALIGN(min_tx_space, 1024); + min_tx_space >>= 10; + /* software strips receive CRC, so leave room for it */ +@@ -894,7 +1084,7 @@ + if (pba < min_rx_space) + pba = min_rx_space; + } +- wr32(E1000_PBA, pba); ++ E1000_WRITE_REG(hw, E1000_PBA, pba); + } + + /* flow control settings */ +@@ -915,39 +1105,43 @@ + } + fc->pause_time = 0xFFFF; + fc->send_xon = 1; +- fc->type = fc->original_type; ++ fc->current_mode = fc->requested_mode; + + /* Allow time for pending master requests to run */ +- adapter->hw.mac.ops.reset_hw(&adapter->hw); +- wr32(E1000_WUC, 0); +- +- if (adapter->hw.mac.ops.init_hw(&adapter->hw)) +- dev_err(&adapter->pdev->dev, "Hardware Error\n"); ++ e1000_reset_hw(hw); ++ E1000_WRITE_REG(hw, E1000_WUC, 0); ++ ++ if (e1000_init_hw(hw)) ++ DPRINTK(PROBE, ERR, "Hardware Error\n"); + + igb_update_mng_vlan(adapter); + + /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ +- wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); +- +- igb_reset_adaptive(&adapter->hw); +- if (adapter->hw.phy.ops.get_phy_info) +- adapter->hw.phy.ops.get_phy_info(&adapter->hw); +-} +- +-/** +- * igb_is_need_ioport - determine if an adapter needs ioport resources or not +- * @pdev: PCI device information struct +- * +- * Returns true if an adapter needs ioport resources +- **/ +-static int igb_is_need_ioport(struct pci_dev *pdev) +-{ +- switch (pdev->device) { +- /* Currently there are no adapters that need ioport resources */ +- default: +- return false; +- } +-} ++ E1000_WRITE_REG(hw, E1000_VET, ETHERNET_IEEE_VLAN_TYPE); ++ ++ e1000_get_phy_info(hw); ++} ++ ++#ifdef HAVE_NET_DEVICE_OPS ++static const struct net_device_ops igb_netdev_ops = { ++ .ndo_open = igb_open, ++ .ndo_stop = igb_close, ++ .ndo_start_xmit = igb_xmit_frame_adv, ++ .ndo_get_stats = igb_get_stats, ++ .ndo_set_multicast_list = igb_set_multi, ++ .ndo_set_mac_address = igb_set_mac, ++ .ndo_change_mtu = igb_change_mtu, ++ .ndo_do_ioctl = igb_ioctl, ++ .ndo_tx_timeout = igb_tx_timeout, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_vlan_rx_register = igb_vlan_rx_register, ++ .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, ++ .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = igb_netpoll, ++#endif ++}; ++#endif /* HAVE_NET_DEVICE_OPS */ + + /** + * igb_probe - Device Initialization Routine +@@ -961,28 +1155,18 @@ + * and a hardware reset occur. + **/ + static int __devinit igb_probe(struct pci_dev *pdev, +- const struct pci_device_id *ent) ++ const struct pci_device_id *ent) + { + struct net_device *netdev; + struct igb_adapter *adapter; + struct e1000_hw *hw; +- const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; +- unsigned long mmio_start, mmio_len; + int i, err, pci_using_dac; + u16 eeprom_data = 0; + u16 eeprom_apme_mask = IGB_EEPROM_APME; +- u32 part_num; +- int bars, need_ioport; +- +- /* do not allocate ioport bars when not needed */ +- need_ioport = igb_is_need_ioport(pdev); +- if (need_ioport) { +- bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); +- err = pci_enable_device(pdev); +- } else { +- bars = pci_select_bars(pdev, IORESOURCE_MEM); +- err = pci_enable_device_mem(pdev); +- } ++ static int cards_found; ++ static int global_quad_port_a; /* global quad port a indication */ ++ ++ err = pci_enable_device_mem(pdev); + if (err) + return err; + +@@ -997,25 +1181,46 @@ + if (err) { + err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); + if (err) { +- dev_err(&pdev->dev, "No usable DMA " +- "configuration, aborting\n"); ++ IGB_ERR("No usable DMA configuration, " ++ "aborting\n"); + goto err_dma; + } + } + } + +- err = pci_request_selected_regions(pdev, bars, igb_driver_name); ++#ifndef HAVE_ASPM_QUIRKS ++ /* 82575 requires that the pci-e link partner disable the L0s state */ ++ switch (pdev->device) { ++ case E1000_DEV_ID_82575EB_COPPER: ++ case E1000_DEV_ID_82575EB_FIBER_SERDES: ++ case E1000_DEV_ID_82575GB_QUAD_COPPER: ++ pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S); ++ default: ++ break; ++ } ++ ++#endif /* HAVE_ASPM_QUIRKS */ ++ err = pci_request_selected_regions(pdev, ++ pci_select_bars(pdev, ++ IORESOURCE_MEM), ++ igb_driver_name); + if (err) + goto err_pci_reg; + ++ pci_enable_pcie_error_reporting(pdev); ++ + pci_set_master(pdev); +- pci_save_state(pdev); + + err = -ENOMEM; +- netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES); ++#ifdef HAVE_TX_MQ ++ netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_ABS_MAX_TX_QUEUES); ++#else ++ netdev = alloc_etherdev(sizeof(struct igb_adapter)); ++#endif /* HAVE_TX_MQ */ + if (!netdev) + goto err_alloc_etherdev; + ++ SET_MODULE_OWNER(netdev); + SET_NETDEV_DEV(netdev, &pdev->dev); + + pci_set_drvdata(pdev, netdev); +@@ -1024,18 +1229,23 @@ + adapter->pdev = pdev; + hw = &adapter->hw; + hw->back = adapter; +- adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE; +- adapter->bars = bars; +- adapter->need_ioport = need_ioport; +- +- mmio_start = pci_resource_start(pdev, 0); +- mmio_len = pci_resource_len(pdev, 0); +- ++ adapter->msg_enable = (1 << debug) - 1; ++ ++#ifdef HAVE_PCI_ERS ++ err = pci_save_state(pdev); ++ if (err) ++ goto err_ioremap; ++#endif + err = -EIO; +- adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); +- if (!adapter->hw.hw_addr) ++ hw->hw_addr = ioremap(pci_resource_start(pdev, 0), ++ pci_resource_len(pdev, 0)); ++ if (!hw->hw_addr) + goto err_ioremap; + ++ ++#ifdef HAVE_NET_DEVICE_OPS ++ netdev->netdev_ops = &igb_netdev_ops; ++#else /* HAVE_NET_DEVICE_OPS */ + netdev->open = &igb_open; + netdev->stop = &igb_close; + netdev->get_stats = &igb_get_stats; +@@ -1043,9 +1253,9 @@ + netdev->set_mac_address = &igb_set_mac; + netdev->change_mtu = &igb_change_mtu; + netdev->do_ioctl = &igb_ioctl; +- igb_set_ethtool_ops(netdev); ++#ifdef HAVE_TX_TIMEOUT + netdev->tx_timeout = &igb_tx_timeout; +- netdev->watchdog_timeo = 5 * HZ; ++#endif + netdev->vlan_rx_register = igb_vlan_rx_register; + netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid; + netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid; +@@ -1053,39 +1263,30 @@ + netdev->poll_controller = igb_netpoll; + #endif + netdev->hard_start_xmit = &igb_xmit_frame_adv; ++#endif /* HAVE_NET_DEVICE_OPS */ ++ igb_set_ethtool_ops(netdev); ++#ifdef HAVE_TX_TIMEOUT ++ netdev->watchdog_timeo = 5 * HZ; ++#endif + + strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); + +- netdev->mem_start = mmio_start; +- netdev->mem_end = mmio_start + mmio_len; +- +- /* PCI config space info */ +- hw->vendor_id = pdev->vendor; +- hw->device_id = pdev->device; +- hw->revision_id = pdev->revision; +- hw->subsystem_vendor_id = pdev->subsystem_vendor; +- hw->subsystem_device_id = pdev->subsystem_device; ++ adapter->bd_number = cards_found; ++ ++ igb_check_options(adapter); + + /* setup the private structure */ +- hw->back = adapter; +- /* Copy the default MAC, PHY and NVM function pointers */ +- memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); +- memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); +- memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); +- /* Initialize skew-specific constants */ +- err = ei->get_invariants(hw); +- if (err) +- goto err_hw_init; +- + err = igb_sw_init(adapter); + if (err) + goto err_sw_init; + +- igb_get_bus_info_pcie(hw); ++ e1000_get_bus_info(hw); + + /* set flags */ + switch (hw->mac.type) { + case e1000_82576: ++ adapter->flags |= IGB_FLAG_HAS_DCA; ++ break; + case e1000_82575: + adapter->flags |= IGB_FLAG_HAS_DCA; + adapter->flags |= IGB_FLAG_NEED_CTX_IDX; +@@ -1094,64 +1295,79 @@ + break; + } + +- hw->phy.autoneg_wait_to_complete = false; +- hw->mac.adaptive_ifs = true; ++ hw->phy.autoneg_wait_to_complete = FALSE; ++ hw->mac.adaptive_ifs = FALSE; + + /* Copper options */ + if (hw->phy.media_type == e1000_media_type_copper) { + hw->phy.mdix = AUTO_ALL_MODES; +- hw->phy.disable_polarity_correction = false; ++ hw->phy.disable_polarity_correction = FALSE; + hw->phy.ms_type = e1000_ms_hw_default; + } + +- if (igb_check_reset_block(hw)) +- dev_info(&pdev->dev, +- "PHY reset is blocked due to SOL/IDER session.\n"); ++ if (e1000_check_reset_block(hw)) ++ DPRINTK(PROBE, INFO, ++ "PHY reset is blocked due to SOL/IDER session.\n"); + + netdev->features = NETIF_F_SG | +- NETIF_F_HW_CSUM | ++ NETIF_F_IP_CSUM | + NETIF_F_HW_VLAN_TX | + NETIF_F_HW_VLAN_RX | + NETIF_F_HW_VLAN_FILTER; + ++#ifdef NETIF_F_IPV6_CSUM ++ netdev->features |= NETIF_F_IPV6_CSUM; ++#endif ++#ifdef NETIF_F_TSO + netdev->features |= NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 + netdev->features |= NETIF_F_TSO6; +- +-#ifdef CONFIG_IGB_LRO ++#endif ++#endif /* NETIF_F_TSO */ ++ ++#ifdef IGB_LRO + netdev->features |= NETIF_F_LRO; + #endif +- ++#ifdef NETIF_F_GRO ++ netdev->features |= NETIF_F_GRO; ++#endif ++ ++#ifdef HAVE_NETDEV_VLAN_FEATURES + netdev->vlan_features |= NETIF_F_TSO; + netdev->vlan_features |= NETIF_F_TSO6; +- netdev->vlan_features |= NETIF_F_HW_CSUM; ++ netdev->vlan_features |= NETIF_F_IP_CSUM; ++ netdev->vlan_features |= NETIF_F_IPV6_CSUM; + netdev->vlan_features |= NETIF_F_SG; + ++#endif + if (pci_using_dac) + netdev->features |= NETIF_F_HIGHDMA; + +- netdev->features |= NETIF_F_LLTX; +- adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw); ++ adapter->en_mng_pt = e1000_enable_mng_pass_thru(hw); + + /* before reading the NVM, reset the controller to put the device in a + * known good starting state */ +- hw->mac.ops.reset_hw(hw); ++ e1000_reset_hw(hw); + + /* make sure the NVM is good */ +- if (igb_validate_nvm_checksum(hw) < 0) { +- dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); ++ if (e1000_validate_nvm_checksum(hw) < 0) { ++ DPRINTK(PROBE, ERR, "The NVM Checksum Is Not Valid\n"); + err = -EIO; + goto err_eeprom; + } + + /* copy the MAC address out of the NVM */ +- if (hw->mac.ops.read_mac_addr(hw)) +- dev_err(&pdev->dev, "NVM Read Error\n"); +- ++ if (e1000_read_mac_addr(hw)) ++ DPRINTK(PROBE, ERR, "NVM Read Error\n"); + memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); ++#ifdef ETHTOOL_GPERMADDR + memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); + + if (!is_valid_ether_addr(netdev->perm_addr)) { +- dev_err(&pdev->dev, "Invalid MAC Address\n"); ++#else ++ if (!is_valid_ether_addr(netdev->dev_addr)) { ++#endif ++ DPRINTK(PROBE, ERR, "Invalid MAC Address\n"); + err = -EIO; + goto err_eeprom; + } +@@ -1167,36 +1383,24 @@ + INIT_WORK(&adapter->reset_task, igb_reset_task); + INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); + +- /* Initialize link & ring properties that are user-changeable */ +- adapter->tx_ring->count = 256; +- for (i = 0; i < adapter->num_tx_queues; i++) +- adapter->tx_ring[i].count = adapter->tx_ring->count; +- adapter->rx_ring->count = 256; +- for (i = 0; i < adapter->num_rx_queues; i++) +- adapter->rx_ring[i].count = adapter->rx_ring->count; +- ++ /* Initialize link properties that are user-changeable */ + adapter->fc_autoneg = true; + hw->mac.autoneg = true; + hw->phy.autoneg_advertised = 0x2f; + +- hw->fc.original_type = e1000_fc_default; +- hw->fc.type = e1000_fc_default; +- +- adapter->itr_setting = 3; +- adapter->itr = IGB_START_ITR; +- +- igb_validate_mdi_setting(hw); +- +- adapter->rx_csum = 1; ++ hw->fc.requested_mode = e1000_fc_default; ++ hw->fc.current_mode = e1000_fc_default; ++ ++ e1000_validate_mdi_setting(hw); + + /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, + * enable the ACPI Magic Packet filter + */ + +- if (hw->bus.func == 0 || +- hw->device_id == E1000_DEV_ID_82575EB_COPPER) +- hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1, +- &eeprom_data); ++ if (hw->bus.func == 0) ++ e1000_read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); ++ else if (hw->bus.func == 1) ++ e1000_read_nvm(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); + + if (eeprom_data & eeprom_apme_mask) + adapter->eeprom_wol |= E1000_WUFC_MAG; +@@ -1213,8 +1417,18 @@ + case E1000_DEV_ID_82576_SERDES: + /* Wake events only supported on port A for dual fiber + * regardless of eeprom setting */ +- if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) ++ if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FUNC_1) + adapter->eeprom_wol = 0; ++ break; ++ case E1000_DEV_ID_82576_QUAD_COPPER: ++ /* if quad port adapter, disable WoL on all but port A */ ++ if (global_quad_port_a != 0) ++ adapter->eeprom_wol = 0; ++ else ++ adapter->flags |= IGB_FLAG_QUAD_PORT_A; ++ /* Reset for multiple quad port adapters */ ++ if (++global_quad_port_a == 4) ++ global_quad_port_a = 0; + break; + } + +@@ -1238,61 +1452,55 @@ + if (err) + goto err_register; + +-#ifdef CONFIG_DCA ++#ifdef IGB_DCA + if ((adapter->flags & IGB_FLAG_HAS_DCA) && +- (dca_add_requester(&pdev->dev) == 0)) { ++ (dca_add_requester(&pdev->dev) == E1000_SUCCESS)) { + adapter->flags |= IGB_FLAG_DCA_ENABLED; +- dev_info(&pdev->dev, "DCA enabled\n"); +- /* Always use CB2 mode, difference is masked +- * in the CB driver. */ +- wr32(E1000_DCA_CTRL, 2); ++ DPRINTK(PROBE, INFO, "DCA enabled\n"); + igb_setup_dca(adapter); + } + #endif + +- dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); ++ DPRINTK(PROBE, INFO, "Intel(R) Gigabit Ethernet Network Connection\n"); + /* print bus type/speed/width info */ +- dev_info(&pdev->dev, +- "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n", +- netdev->name, +- ((hw->bus.speed == e1000_bus_speed_2500) +- ? "2.5Gb/s" : "unknown"), +- ((hw->bus.width == e1000_bus_width_pcie_x4) +- ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1) +- ? "Width x1" : "unknown"), +- netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2], +- netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]); +- +- igb_read_part_num(hw, &part_num); +- dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name, +- (part_num >> 8), (part_num & 0xff)); +- +- dev_info(&pdev->dev, +- "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", +- adapter->msix_entries ? "MSI-X" : +- (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", +- adapter->num_rx_queues, adapter->num_tx_queues); +- ++ DPRINTK(PROBE, INFO, "(PCIe:%s:%s) ", ++ ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : "unknown"), ++ ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : ++ (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" : ++ (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : ++ "unknown")); ++ ++ for (i = 0; i < 6; i++) ++ printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':'); ++ ++ DPRINTK(PROBE, INFO, ++ "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", ++ adapter->msix_entries ? "MSI-X" : ++ adapter->flags & IGB_FLAG_HAS_MSI ? "MSI" : ++ "legacy", ++ adapter->num_rx_queues, adapter->num_tx_queues); ++ ++ cards_found++; + return 0; + + err_register: + igb_release_hw_control(adapter); + err_eeprom: +- if (!igb_check_reset_block(hw)) +- hw->phy.ops.reset_phy(hw); ++ if (!e1000_check_reset_block(hw)) ++ e1000_phy_hw_reset(hw); + + if (hw->flash_address) + iounmap(hw->flash_address); + +- igb_remove_device(hw); + igb_free_queues(adapter); + err_sw_init: +-err_hw_init: ++ igb_reset_interrupt_capability(adapter); + iounmap(hw->hw_addr); + err_ioremap: + free_netdev(netdev); + err_alloc_etherdev: +- pci_release_selected_regions(pdev, bars); ++ pci_release_selected_regions(pdev, ++ pci_select_bars(pdev, IORESOURCE_MEM)); + err_pci_reg: + err_dma: + pci_disable_device(pdev); +@@ -1312,9 +1520,7 @@ + { + struct net_device *netdev = pci_get_drvdata(pdev); + struct igb_adapter *adapter = netdev_priv(netdev); +-#ifdef CONFIG_DCA +- struct e1000_hw *hw = &adapter->hw; +-#endif ++ struct e1000_hw *hw = &adapter->hw; + + /* flush_scheduled work may reschedule our watchdog task, so + * explicitly disable watchdog tasks from being rescheduled */ +@@ -1324,12 +1530,13 @@ + + flush_scheduled_work(); + +-#ifdef CONFIG_DCA ++ ++#ifdef IGB_DCA + if (adapter->flags & IGB_FLAG_DCA_ENABLED) { +- dev_info(&pdev->dev, "DCA disabled\n"); ++ DPRINTK(PROBE, INFO, "DCA disabled\n"); + dca_remove_requester(&pdev->dev); + adapter->flags &= ~IGB_FLAG_DCA_ENABLED; +- wr32(E1000_DCA_CTRL, 1); ++ E1000_WRITE_REG(hw, E1000_DCA_CTRL, 1); + } + #endif + +@@ -1339,21 +1546,22 @@ + + unregister_netdev(netdev); + +- if (adapter->hw.phy.ops.reset_phy && +- !igb_check_reset_block(&adapter->hw)) +- adapter->hw.phy.ops.reset_phy(&adapter->hw); +- +- igb_remove_device(&adapter->hw); ++ if (!e1000_check_reset_block(hw)) ++ e1000_phy_hw_reset(hw); ++ + igb_reset_interrupt_capability(adapter); + + igb_free_queues(adapter); + +- iounmap(adapter->hw.hw_addr); +- if (adapter->hw.flash_address) ++ iounmap(hw->hw_addr); ++ if (hw->flash_address) + iounmap(adapter->hw.flash_address); +- pci_release_selected_regions(pdev, adapter->bars); ++ pci_release_selected_regions(pdev, ++ pci_select_bars(pdev, IORESOURCE_MEM)); + + free_netdev(netdev); ++ ++ pci_disable_pcie_error_reporting(pdev); + + pci_disable_device(pdev); + } +@@ -1371,6 +1579,15 @@ + struct e1000_hw *hw = &adapter->hw; + struct net_device *netdev = adapter->netdev; + struct pci_dev *pdev = adapter->pdev; ++ ++ /* PCI config space info */ ++ ++ hw->vendor_id = pdev->vendor; ++ hw->device_id = pdev->device; ++ hw->subsystem_vendor_id = pdev->subsystem_vendor; ++ hw->subsystem_device_id = pdev->subsystem_device; ++ ++ pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); + + pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); + +@@ -1381,17 +1598,18 @@ + adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; + adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; + +- /* Number of supported queues. */ +- /* Having more queues than CPUs doesn't make sense. */ +- adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus()); +- adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus()); ++ /* Initialize the hardware-specific values */ ++ if (e1000_setup_init_funcs(hw, TRUE)) { ++ DPRINTK(PROBE, ERR, "Hardware Initialization Failure\n"); ++ return -EIO; ++ } + + /* This call may decrease the number of queues depending on + * interrupt mode. */ + igb_set_interrupt_capability(adapter); + + if (igb_alloc_queues(adapter)) { +- dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); ++ DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); + return -ENOMEM; + } + +@@ -1457,18 +1675,19 @@ + + for (i = 0; i < adapter->num_rx_queues; i++) + napi_enable(&adapter->rx_ring[i].napi); ++ igb_configure_lli(adapter); + + /* Clear any pending interrupts. */ +- rd32(E1000_ICR); ++ E1000_READ_REG(hw, E1000_ICR); + + igb_irq_enable(adapter); + + netif_tx_start_all_queues(netdev); + + /* Fire a link status change interrupt to start the watchdog. */ +- wr32(E1000_ICS, E1000_ICS_LSC); +- +- return 0; ++ E1000_WRITE_REG(hw, E1000_ICS, E1000_ICS_LSC); ++ ++ return E1000_SUCCESS; + + err_req_irq: + igb_release_hw_control(adapter); +@@ -1523,9 +1742,8 @@ + * + * Return 0 on success, negative on failure + **/ +- + int igb_setup_tx_resources(struct igb_adapter *adapter, +- struct igb_ring *tx_ring) ++ struct igb_ring *tx_ring) + { + struct pci_dev *pdev = adapter->pdev; + int size; +@@ -1537,12 +1755,11 @@ + memset(tx_ring->buffer_info, 0, size); + + /* round up to nearest 4K */ +- tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc) +- + sizeof(u32); ++ tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); + tx_ring->size = ALIGN(tx_ring->size, 4096); + + tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, +- &tx_ring->dma); ++ &tx_ring->dma); + + if (!tx_ring->desc) + goto err; +@@ -1554,8 +1771,8 @@ + + err: + vfree(tx_ring->buffer_info); +- dev_err(&adapter->pdev->dev, +- "Unable to allocate memory for the transmit descriptor ring\n"); ++ DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " ++ "descriptor ring\n"); + return -ENOMEM; + } + +@@ -1569,12 +1786,14 @@ + static int igb_setup_all_tx_resources(struct igb_adapter *adapter) + { + int i, err = 0; ++#ifdef HAVE_TX_MQ + int r_idx; ++#endif + + for (i = 0; i < adapter->num_tx_queues; i++) { + err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]); + if (err) { +- dev_err(&adapter->pdev->dev, ++ DPRINTK(PROBE, ERR, + "Allocation for Tx Queue %u failed\n", i); + for (i--; i >= 0; i--) + igb_free_tx_resources(&adapter->tx_ring[i]); +@@ -1582,10 +1801,12 @@ + } + } + +- for (i = 0; i < IGB_MAX_TX_QUEUES; i++) { ++#ifdef HAVE_TX_MQ ++ for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) { + r_idx = i % adapter->num_tx_queues; + adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx]; +- } ++ } ++#endif + return err; + } + +@@ -1597,57 +1818,51 @@ + **/ + static void igb_configure_tx(struct igb_adapter *adapter) + { +- u64 tdba, tdwba; ++ u64 tdba; + struct e1000_hw *hw = &adapter->hw; + u32 tctl; + u32 txdctl, txctrl; +- int i; +- +- for (i = 0; i < adapter->num_tx_queues; i++) { +- struct igb_ring *ring = &(adapter->tx_ring[i]); +- +- wr32(E1000_TDLEN(i), +- ring->count * sizeof(struct e1000_tx_desc)); ++ int i, j; ++ ++ for (i = 0; i < adapter->num_tx_queues; i++) { ++ struct igb_ring *ring = &adapter->tx_ring[i]; ++ j = ring->reg_idx; ++ ++ E1000_WRITE_REG(hw, E1000_TDLEN(j), ++ ring->count * sizeof(struct e1000_tx_desc)); + tdba = ring->dma; +- wr32(E1000_TDBAL(i), +- tdba & 0x00000000ffffffffULL); +- wr32(E1000_TDBAH(i), tdba >> 32); +- +- tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc); +- tdwba |= 1; /* enable head wb */ +- wr32(E1000_TDWBAL(i), +- tdwba & 0x00000000ffffffffULL); +- wr32(E1000_TDWBAH(i), tdwba >> 32); +- +- ring->head = E1000_TDH(i); +- ring->tail = E1000_TDT(i); ++ E1000_WRITE_REG(hw, E1000_TDBAL(j), ++ tdba & 0x00000000ffffffffULL); ++ E1000_WRITE_REG(hw, E1000_TDBAH(j), tdba >> 32); ++ ++ ring->head = E1000_TDH(j); ++ ring->tail = E1000_TDT(j); + writel(0, hw->hw_addr + ring->tail); + writel(0, hw->hw_addr + ring->head); +- txdctl = rd32(E1000_TXDCTL(i)); ++ txdctl = E1000_READ_REG(hw, E1000_TXDCTL(j)); + txdctl |= E1000_TXDCTL_QUEUE_ENABLE; +- wr32(E1000_TXDCTL(i), txdctl); ++ E1000_WRITE_REG(hw, E1000_TXDCTL(j), txdctl); + + /* Turn off Relaxed Ordering on head write-backs. The + * writebacks MUST be delivered in order or it will + * completely screw up our bookeeping. + */ +- txctrl = rd32(E1000_DCA_TXCTRL(i)); ++ txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(j)); + txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; +- wr32(E1000_DCA_TXCTRL(i), txctrl); +- } +- +- ++ E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(j), txctrl); ++ } + + /* Use the default values for the Tx Inter Packet Gap (IPG) timer */ + ++ + /* Program the Transmit Control Register */ + +- tctl = rd32(E1000_TCTL); ++ tctl = E1000_READ_REG(hw, E1000_TCTL); + tctl &= ~E1000_TCTL_CT; + tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | + (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); + +- igb_config_collision_dist(hw); ++ e1000_config_collision_dist(hw); + + /* Setup Transmit Descriptor Settings for eop descriptor */ + adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS; +@@ -1655,7 +1870,7 @@ + /* Enable transmits */ + tctl |= E1000_TCTL_EN; + +- wr32(E1000_TCTL, tctl); ++ E1000_WRITE_REG(hw, E1000_TCTL, tctl); + } + + /** +@@ -1665,20 +1880,19 @@ + * + * Returns 0 on success, negative on failure + **/ +- + int igb_setup_rx_resources(struct igb_adapter *adapter, +- struct igb_ring *rx_ring) ++ struct igb_ring *rx_ring) + { + struct pci_dev *pdev = adapter->pdev; + int size, desc_len; + +-#ifdef CONFIG_IGB_LRO ++#ifdef IGB_LRO + size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS; + rx_ring->lro_mgr.lro_arr = vmalloc(size); + if (!rx_ring->lro_mgr.lro_arr) + goto err; + memset(rx_ring->lro_mgr.lro_arr, 0, size); +-#endif ++#endif /* IGB_LRO */ + + size = sizeof(struct igb_buffer) * rx_ring->count; + rx_ring->buffer_info = vmalloc(size); +@@ -1693,7 +1907,7 @@ + rx_ring->size = ALIGN(rx_ring->size, 4096); + + rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, +- &rx_ring->dma); ++ &rx_ring->dma); + + if (!rx_ring->desc) + goto err; +@@ -1706,19 +1920,20 @@ + return 0; + + err: +-#ifdef CONFIG_IGB_LRO ++#ifdef IGB_LRO + vfree(rx_ring->lro_mgr.lro_arr); + rx_ring->lro_mgr.lro_arr = NULL; + #endif + vfree(rx_ring->buffer_info); +- dev_err(&adapter->pdev->dev, "Unable to allocate memory for " +- "the receive descriptor ring\n"); ++ rx_ring->buffer_info = NULL; ++ DPRINTK(PROBE, ERR, "Unable to allocate memory for the receive " ++ "descriptor ring\n"); + return -ENOMEM; + } + + /** + * igb_setup_all_rx_resources - wrapper to allocate Rx resources +- * (Descriptors) for all queues ++ * (Descriptors) for all queues + * @adapter: board private structure + * + * Return 0 on success, negative on failure +@@ -1730,7 +1945,7 @@ + for (i = 0; i < adapter->num_rx_queues; i++) { + err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]); + if (err) { +- dev_err(&adapter->pdev->dev, ++ DPRINTK(PROBE, ERR, + "Allocation for Rx Queue %u failed\n", i); + for (i--; i >= 0; i--) + igb_free_rx_resources(&adapter->rx_ring[i]); +@@ -1750,57 +1965,45 @@ + struct e1000_hw *hw = &adapter->hw; + u32 rctl; + u32 srrctl = 0; +- int i; +- +- rctl = rd32(E1000_RCTL); ++ int i, j; ++ ++ rctl = E1000_READ_REG(hw, E1000_RCTL); + + rctl &= ~(3 << E1000_RCTL_MO_SHIFT); +- +- rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | +- E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | +- (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); ++ rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); ++ ++ rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | ++ (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); + + /* + * enable stripping of CRC. It's unlikely this will break BMC + * redirection as it did with e1000. Newer features require + * that the HW strips the CRC. +- */ ++ */ + rctl |= E1000_RCTL_SECRC; + +- rctl &= ~E1000_RCTL_SBP; +- +- if (adapter->netdev->mtu <= ETH_DATA_LEN) +- rctl &= ~E1000_RCTL_LPE; +- else +- rctl |= E1000_RCTL_LPE; +- if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) { +- /* Setup buffer sizes */ +- rctl &= ~E1000_RCTL_SZ_4096; +- rctl |= E1000_RCTL_BSEX; +- switch (adapter->rx_buffer_len) { +- case IGB_RXBUFFER_256: +- rctl |= E1000_RCTL_SZ_256; +- rctl &= ~E1000_RCTL_BSEX; +- break; +- case IGB_RXBUFFER_512: +- rctl |= E1000_RCTL_SZ_512; +- rctl &= ~E1000_RCTL_BSEX; +- break; +- case IGB_RXBUFFER_1024: +- rctl |= E1000_RCTL_SZ_1024; +- rctl &= ~E1000_RCTL_BSEX; +- break; +- case IGB_RXBUFFER_2048: +- default: +- rctl |= E1000_RCTL_SZ_2048; +- rctl &= ~E1000_RCTL_BSEX; +- break; +- } +- } else { +- rctl &= ~E1000_RCTL_BSEX; +- srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT; +- } +- ++ ++ /* disable store bad packets and clear size bits. */ ++ rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); ++ ++ /* enable LPE to prevent packets larger than max_frame_size */ ++ rctl |= E1000_RCTL_LPE; ++ ++ /* Setup buffer sizes */ ++ switch (adapter->rx_buffer_len) { ++ case IGB_RXBUFFER_256: ++ rctl |= E1000_RCTL_SZ_256; ++ break; ++ case IGB_RXBUFFER_512: ++ rctl |= E1000_RCTL_SZ_512; ++ break; ++ default: ++ srrctl = ALIGN(adapter->rx_buffer_len, 1024) ++ >> E1000_SRRCTL_BSIZEPKT_SHIFT; ++ break; ++ } ++ ++#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT + /* 82575 and greater support packet-split where the protocol + * header is placed in skb->data and the packet data is + * placed in pages hanging off of skb_shinfo(skb)->nr_frags. +@@ -1810,20 +2013,43 @@ + */ + /* allocations using alloc_page take too long for regular MTU + * so only enable packet split for jumbo frames */ +- if (rctl & E1000_RCTL_LPE) { ++ if (adapter->netdev->mtu > ETH_DATA_LEN) { + adapter->rx_ps_hdr_size = IGB_RXBUFFER_128; + srrctl |= adapter->rx_ps_hdr_size << +- E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; ++ E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; + srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; + } else { ++#endif /* CONFIG_IGB_DISABLE_PACKET_SPLIT */ + adapter->rx_ps_hdr_size = 0; + srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; +- } +- +- for (i = 0; i < adapter->num_rx_queues; i++) +- wr32(E1000_SRRCTL(i), srrctl); +- +- wr32(E1000_RCTL, rctl); ++#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT ++ } ++#endif /* CONFIG_IGB_DISABLE_PACKET_SPLIT */ ++ ++ for (i = 0; i < adapter->num_rx_queues; i++) { ++ j = adapter->rx_ring[i].reg_idx; ++ E1000_WRITE_REG(hw, E1000_SRRCTL(j), srrctl); ++ } ++ ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); ++} ++ ++ ++/** ++ * igb_set_rlpml - set receive large packet maximum length ++ * @adapter: board private structure ++ * ++ * Configure the maximum size of packets that will be received ++ */ ++static void igb_set_rlpml(struct igb_adapter *adapter) ++{ ++ int max_frame_size = adapter->max_frame_size; ++ struct e1000_hw *hw = &adapter->hw; ++ ++ if (adapter->vlgrp) ++ max_frame_size += VLAN_TAG_SIZE; ++ E1000_WRITE_REG(hw, E1000_RLPML, max_frame_size); ++ + } + + /** +@@ -1838,43 +2064,44 @@ + struct e1000_hw *hw = &adapter->hw; + u32 rctl, rxcsum; + u32 rxdctl; +- int i; ++ int i, j; + + /* disable receives while setting up the descriptors */ +- rctl = rd32(E1000_RCTL); +- wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); +- wrfl(); ++ rctl = E1000_READ_REG(hw, E1000_RCTL); ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); ++ E1000_WRITE_FLUSH(hw); + mdelay(10); + + if (adapter->itr_setting > 3) +- wr32(E1000_ITR, adapter->itr); ++ E1000_WRITE_REG(hw, E1000_ITR, adapter->itr); + + /* Setup the HW Rx Head and Tail Descriptor Pointers and + * the Base and Length of the Rx Descriptor Ring */ +- for (i = 0; i < adapter->num_rx_queues; i++) { +- struct igb_ring *ring = &(adapter->rx_ring[i]); ++ for (i = 0; i < adapter->num_rx_queues; i++) { ++ struct igb_ring *ring = &adapter->rx_ring[i]; ++ j = ring->reg_idx; + rdba = ring->dma; +- wr32(E1000_RDBAL(i), +- rdba & 0x00000000ffffffffULL); +- wr32(E1000_RDBAH(i), rdba >> 32); +- wr32(E1000_RDLEN(i), +- ring->count * sizeof(union e1000_adv_rx_desc)); +- +- ring->head = E1000_RDH(i); +- ring->tail = E1000_RDT(i); ++ E1000_WRITE_REG(hw, E1000_RDBAL(j), ++ rdba & 0x00000000ffffffffULL); ++ E1000_WRITE_REG(hw, E1000_RDBAH(j), rdba >> 32); ++ E1000_WRITE_REG(hw, E1000_RDLEN(j), ++ ring->count * sizeof(union e1000_adv_rx_desc)); ++ ++ ring->head = E1000_RDH(j); ++ ring->tail = E1000_RDT(j); + writel(0, hw->hw_addr + ring->tail); + writel(0, hw->hw_addr + ring->head); + +- rxdctl = rd32(E1000_RXDCTL(i)); ++ rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(j)); + rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; + rxdctl &= 0xFFF00000; + rxdctl |= IGB_RX_PTHRESH; + rxdctl |= IGB_RX_HTHRESH << 8; + rxdctl |= IGB_RX_WTHRESH << 16; +- wr32(E1000_RXDCTL(i), rxdctl); +-#ifdef CONFIG_IGB_LRO ++ E1000_WRITE_REG(hw, E1000_RXDCTL(j), rxdctl); ++#ifdef IGB_LRO + /* Intitial LRO Settings */ +- ring->lro_mgr.max_aggr = MAX_LRO_AGGR; ++ ring->lro_mgr.max_aggr = adapter->lro_max_aggr; + ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS; + ring->lro_mgr.get_skb_header = igb_get_skb_hdr; + ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID; +@@ -1885,7 +2112,12 @@ + } + + if (adapter->num_rx_queues > 1) { +- u32 random[10]; ++ static const u8 rsshash[40] = { ++ 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, ++ 0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, ++ 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4, ++ 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c, ++ 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa }; + u32 mrqc; + u32 j, shift; + union e1000_reta { +@@ -1893,15 +2125,13 @@ + u8 bytes[4]; + } reta; + +- get_random_bytes(&random[0], 40); +- + if (hw->mac.type >= e1000_82576) + shift = 0; + else + shift = 6; + for (j = 0; j < (32 * 4); j++) { + reta.bytes[j & 3] = +- (j % adapter->num_rx_queues) << shift; ++ adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift; + if ((j & 3) == 3) + writel(reta.dword, + hw->hw_addr + E1000_RETA(0) + (j & ~3)); +@@ -1909,8 +2139,13 @@ + mrqc = E1000_MRQC_ENABLE_RSS_4Q; + + /* Fill out hash function seeds */ +- for (j = 0; j < 10; j++) +- array_wr32(E1000_RSSRK(0), j, random[j]); ++ for (j = 0; j < 10; j++) { ++ u32 rsskey = rsshash[(j * 4)]; ++ rsskey |= rsshash[(j * 4) + 1] << 8; ++ rsskey |= rsshash[(j * 4) + 2] << 16; ++ rsskey |= rsshash[(j * 4) + 3] << 24; ++ E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), j, rsskey); ++ } + + mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | + E1000_MRQC_RSS_FIELD_IPV4_TCP); +@@ -1922,44 +2157,24 @@ + E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); + + +- wr32(E1000_MRQC, mrqc); +- +- /* Multiqueue and raw packet checksumming are mutually +- * exclusive. Note that this not the same as TCP/IP +- * checksumming, which works fine. */ +- rxcsum = rd32(E1000_RXCSUM); +- rxcsum |= E1000_RXCSUM_PCSD; +- wr32(E1000_RXCSUM, rxcsum); +- } else { +- /* Enable Receive Checksum Offload for TCP and UDP */ +- rxcsum = rd32(E1000_RXCSUM); +- if (adapter->rx_csum) { +- rxcsum |= E1000_RXCSUM_TUOFL; +- +- /* Enable IPv4 payload checksum for UDP fragments +- * Must be used in conjunction with packet-split. */ +- if (adapter->rx_ps_hdr_size) +- rxcsum |= E1000_RXCSUM_IPPCSE; +- } else { +- rxcsum &= ~E1000_RXCSUM_TUOFL; +- /* don't need to clear IPPCSE as it defaults to 0 */ +- } +- wr32(E1000_RXCSUM, rxcsum); +- } +- +- if (adapter->vlgrp) +- wr32(E1000_RLPML, +- adapter->max_frame_size + VLAN_TAG_SIZE); +- else +- wr32(E1000_RLPML, adapter->max_frame_size); ++ E1000_WRITE_REG(hw, E1000_MRQC, mrqc); ++ } ++ ++ /* Enable Receive Checksum Offload for TCP and UDP */ ++ rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); ++ /* Disable raw packet checksumming */ ++ rxcsum |= E1000_RXCSUM_PCSD; ++ /* Don't need to set TUOFL or IPOFL, they default to 1 */ ++ E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); ++ ++ igb_set_rlpml(adapter); + + /* Enable Receives */ +- wr32(E1000_RCTL, rctl); ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); + } + + /** + * igb_free_tx_resources - Free Tx Resources per Queue +- * @adapter: board private structure + * @tx_ring: Tx descriptor ring for a specific queue + * + * Free all transmit software resources +@@ -1993,10 +2208,17 @@ + } + + static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter, +- struct igb_buffer *buffer_info) +-{ ++ struct igb_buffer *buffer_info) ++{ ++ if (buffer_info->page_dma) { ++ pci_unmap_page(adapter->pdev, ++ buffer_info->page_dma, ++ buffer_info->length, ++ PCI_DMA_TODEVICE); ++ buffer_info->page_dma = 0; ++ } + if (buffer_info->dma) { +- pci_unmap_page(adapter->pdev, ++ pci_unmap_single(adapter->pdev, + buffer_info->dma, + buffer_info->length, + PCI_DMA_TODEVICE); +@@ -2007,12 +2229,12 @@ + buffer_info->skb = NULL; + } + buffer_info->time_stamp = 0; ++ buffer_info->next_to_watch = 0; + /* buffer_info must be completely set up in the transmit path */ + } + + /** + * igb_clean_tx_ring - Free Tx Buffers +- * @adapter: board private structure + * @tx_ring: ring to be cleaned + **/ + static void igb_clean_tx_ring(struct igb_ring *tx_ring) +@@ -2059,7 +2281,6 @@ + + /** + * igb_free_rx_resources - Free Rx Resources +- * @adapter: board private structure + * @rx_ring: ring to clean the resources from + * + * Free all receive software resources +@@ -2073,10 +2294,10 @@ + vfree(rx_ring->buffer_info); + rx_ring->buffer_info = NULL; + +-#ifdef CONFIG_IGB_LRO ++#ifdef IGB_LRO + vfree(rx_ring->lro_mgr.lro_arr); + rx_ring->lro_mgr.lro_arr = NULL; +-#endif ++#endif /* IGB_LRO */ + + pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); + +@@ -2099,7 +2320,6 @@ + + /** + * igb_clean_rx_ring - Free Rx Buffers per Queue +- * @adapter: board private structure + * @rx_ring: ring to free buffers from + **/ + static void igb_clean_rx_ring(struct igb_ring *rx_ring) +@@ -2118,29 +2338,31 @@ + if (buffer_info->dma) { + if (adapter->rx_ps_hdr_size) + pci_unmap_single(pdev, buffer_info->dma, +- adapter->rx_ps_hdr_size, +- PCI_DMA_FROMDEVICE); ++ adapter->rx_ps_hdr_size, ++ PCI_DMA_FROMDEVICE); + else + pci_unmap_single(pdev, buffer_info->dma, +- adapter->rx_buffer_len, +- PCI_DMA_FROMDEVICE); ++ adapter->rx_buffer_len, ++ PCI_DMA_FROMDEVICE); + buffer_info->dma = 0; + } +- + if (buffer_info->skb) { + dev_kfree_skb(buffer_info->skb); + buffer_info->skb = NULL; + } ++#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT ++ if (buffer_info->page_dma) { ++ pci_unmap_page(pdev, buffer_info->page_dma, ++ PAGE_SIZE / 2, ++ PCI_DMA_FROMDEVICE); ++ buffer_info->page_dma = 0; ++ } + if (buffer_info->page) { +- if (buffer_info->page_dma) +- pci_unmap_page(pdev, buffer_info->page_dma, +- PAGE_SIZE / 2, +- PCI_DMA_FROMDEVICE); + put_page(buffer_info->page); + buffer_info->page = NULL; +- buffer_info->page_dma = 0; + buffer_info->page_offset = 0; + } ++#endif + } + + size = sizeof(struct igb_buffer) * rx_ring->count; +@@ -2178,15 +2400,16 @@ + static int igb_set_mac(struct net_device *netdev, void *p) + { + struct igb_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; + struct sockaddr *addr = p; + + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); +- memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); +- +- adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); ++ memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); ++ ++ e1000_rar_set(hw, hw->mac.addr, 0); + + return 0; + } +@@ -2204,7 +2427,6 @@ + { + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +- struct e1000_mac_info *mac = &hw->mac; + struct dev_mc_list *mc_ptr; + u8 *mta_list; + u32 rctl; +@@ -2212,7 +2434,7 @@ + + /* Check for Promiscuous and All Multicast modes */ + +- rctl = rd32(E1000_RCTL); ++ rctl = E1000_READ_REG(hw, E1000_RCTL); + + if (netdev->flags & IFF_PROMISC) { + rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); +@@ -2225,12 +2447,11 @@ + rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); + rctl |= E1000_RCTL_VFE; + } +- wr32(E1000_RCTL, rctl); ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); + + if (!netdev->mc_count) { + /* nothing to program, so clear mc list */ +- igb_update_mc_addr_list_82575(hw, NULL, 0, 1, +- mac->rar_entry_count); ++ e1000_update_mc_addr_list(hw, NULL, 0); + return; + } + +@@ -2247,8 +2468,7 @@ + memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); + mc_ptr = mc_ptr->next; + } +- igb_update_mc_addr_list_82575(hw, mta_list, i, 1, +- mac->rar_entry_count); ++ e1000_update_mc_addr_list(hw, mta_list, i); + kfree(mta_list); + } + +@@ -2257,8 +2477,43 @@ + static void igb_update_phy_info(unsigned long data) + { + struct igb_adapter *adapter = (struct igb_adapter *) data; +- if (adapter->hw.phy.ops.get_phy_info) +- adapter->hw.phy.ops.get_phy_info(&adapter->hw); ++ e1000_get_phy_info(&adapter->hw); ++} ++ ++/** ++ * igb_has_link - check shared code for link and determine up/down ++ * @adapter: pointer to driver private info ++ **/ ++static bool igb_has_link(struct igb_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ bool link_active = FALSE; ++ s32 ret_val = 0; ++ ++ /* get_link_status is set on LSC (link status) interrupt or ++ * rx sequence error interrupt. get_link_status will stay ++ * false until the e1000_check_for_link establishes link ++ * for copper adapters ONLY ++ */ ++ switch (hw->phy.media_type) { ++ case e1000_media_type_copper: ++ if (hw->mac.get_link_status) { ++ ret_val = e1000_check_for_link(hw); ++ link_active = !hw->mac.get_link_status; ++ } else { ++ link_active = TRUE; ++ } ++ break; ++ case e1000_media_type_internal_serdes: ++ ret_val = e1000_check_for_link(hw); ++ link_active = hw->mac.serdes_has_link; ++ break; ++ default: ++ case e1000_media_type_unknown: ++ break; ++ } ++ ++ return link_active; + } + + /** +@@ -2275,54 +2530,32 @@ + static void igb_watchdog_task(struct work_struct *work) + { + struct igb_adapter *adapter = container_of(work, +- struct igb_adapter, watchdog_task); +- struct e1000_hw *hw = &adapter->hw; +- ++ struct igb_adapter, watchdog_task); ++ struct e1000_hw *hw = &adapter->hw; + struct net_device *netdev = adapter->netdev; + struct igb_ring *tx_ring = adapter->tx_ring; +- struct e1000_mac_info *mac = &adapter->hw.mac; + u32 link; + u32 eics = 0; +- s32 ret_val; +- int i; +- +- if ((netif_carrier_ok(netdev)) && +- (rd32(E1000_STATUS) & E1000_STATUS_LU)) +- goto link_up; +- +- ret_val = hw->mac.ops.check_for_link(&adapter->hw); +- if ((ret_val == E1000_ERR_PHY) && +- (hw->phy.type == e1000_phy_igp_3) && +- (rd32(E1000_CTRL) & +- E1000_PHY_CTRL_GBE_DISABLE)) +- dev_info(&adapter->pdev->dev, +- "Gigabit has been disabled, downgrading speed\n"); +- +- if ((hw->phy.media_type == e1000_media_type_internal_serdes) && +- !(rd32(E1000_TXCW) & E1000_TXCW_ANE)) +- link = mac->serdes_has_link; +- else +- link = rd32(E1000_STATUS) & +- E1000_STATUS_LU; ++ int i; ++ ++ link = igb_has_link(adapter); + + if (link) { + if (!netif_carrier_ok(netdev)) { + u32 ctrl; +- hw->mac.ops.get_speed_and_duplex(&adapter->hw, +- &adapter->link_speed, +- &adapter->link_duplex); +- +- ctrl = rd32(E1000_CTRL); +- dev_info(&adapter->pdev->dev, +- "NIC Link is Up %d Mbps %s, " +- "Flow Control: %s\n", +- adapter->link_speed, +- adapter->link_duplex == FULL_DUPLEX ? +- "Full Duplex" : "Half Duplex", +- ((ctrl & E1000_CTRL_TFCE) && (ctrl & +- E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl & +- E1000_CTRL_RFCE) ? "RX" : ((ctrl & +- E1000_CTRL_TFCE) ? "TX" : "None"))); ++ e1000_get_speed_and_duplex(hw, &adapter->link_speed, ++ &adapter->link_duplex); ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); ++ DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s, " ++ "Flow Control: %s\n", ++ adapter->link_speed, ++ adapter->link_duplex == FULL_DUPLEX ? ++ "Full Duplex" : "Half Duplex", ++ ((ctrl & E1000_CTRL_TFCE) && (ctrl & ++ E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl & ++ E1000_CTRL_RFCE) ? "RX" : ((ctrl & ++ E1000_CTRL_TFCE) ? "TX" : "None"))); + + /* tweak tx_queue_len according to speed/duplex and + * adjust the timeout factor */ +@@ -2342,6 +2575,7 @@ + netif_carrier_on(netdev); + netif_tx_wake_all_queues(netdev); + ++ /* link state has changed, schedule phy info update */ + if (!test_bit(__IGB_DOWN, &adapter->state)) + mod_timer(&adapter->phy_info_timer, + round_jiffies(jiffies + 2 * HZ)); +@@ -2350,29 +2584,18 @@ + if (netif_carrier_ok(netdev)) { + adapter->link_speed = 0; + adapter->link_duplex = 0; +- dev_info(&adapter->pdev->dev, "NIC Link is Down\n"); ++ DPRINTK(LINK, INFO, "NIC Link is Down\n"); + netif_carrier_off(netdev); + netif_tx_stop_all_queues(netdev); ++ ++ /* link state has changed, schedule phy info update */ + if (!test_bit(__IGB_DOWN, &adapter->state)) + mod_timer(&adapter->phy_info_timer, + round_jiffies(jiffies + 2 * HZ)); + } + } + +-link_up: + igb_update_stats(adapter); +- +- mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; +- adapter->tpt_old = adapter->stats.tpt; +- mac->collision_delta = adapter->stats.colc - adapter->colc_old; +- adapter->colc_old = adapter->stats.colc; +- +- adapter->gorc = adapter->stats.gorc - adapter->gorc_old; +- adapter->gorc_old = adapter->stats.gorc; +- adapter->gotc = adapter->stats.gotc - adapter->gotc_old; +- adapter->gotc_old = adapter->stats.gotc; +- +- igb_update_adaptive(&adapter->hw); + + if (!netif_carrier_ok(netdev)) { + if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) { +@@ -2389,18 +2612,18 @@ + if (adapter->msix_entries) { + for (i = 0; i < adapter->num_rx_queues; i++) + eics |= adapter->rx_ring[i].eims_value; +- wr32(E1000_EICS, eics); +- } else { +- wr32(E1000_ICS, E1000_ICS_RXDMT0); ++ E1000_WRITE_REG(hw, E1000_EICS, eics); ++ } else { ++ E1000_WRITE_REG(hw, E1000_ICS, E1000_ICS_RXDMT0); + } + + /* Force detection of hung controller every watchdog period */ +- tx_ring->detect_tx_hung = true; ++ tx_ring->detect_tx_hung = TRUE; + + /* Reset the timer */ + if (!test_bit(__IGB_DOWN, &adapter->state)) + mod_timer(&adapter->watchdog_timer, +- round_jiffies(jiffies + 2 * HZ)); ++ round_jiffies(jiffies + 2 * HZ)); + } + + enum latency_range { +@@ -2444,6 +2667,10 @@ + goto set_itr_val; + } + avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets; ++ if (rx_ring->buddy && rx_ring->buddy->total_packets) ++ avg_wire_size = max(avg_wire_size, ++ (int)(rx_ring->buddy->total_bytes / ++ rx_ring->buddy->total_packets)); + + /* Add 24 bytes to size to account for CRC, preamble, and gap */ + avg_wire_size += 24; +@@ -2465,6 +2692,10 @@ + clear_counts: + rx_ring->total_bytes = 0; + rx_ring->total_packets = 0; ++ if (rx_ring->buddy) { ++ rx_ring->buddy->total_bytes = 0; ++ rx_ring->buddy->total_packets = 0; ++ } + } + + /** +@@ -2486,7 +2717,7 @@ + * @bytes: the number of bytes during this measurement interval + **/ + static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting, +- int packets, int bytes) ++ int packets, int bytes) + { + unsigned int retval = itr_setting; + +@@ -2521,7 +2752,7 @@ + if (bytes > 25000) { + if (packets > 35) + retval = low_latency; +- } else if (bytes < 6000) { ++ } else if (bytes < 1500) { + retval = low_latency; + } + break; +@@ -2530,7 +2761,6 @@ + update_itr_done: + return retval; + } +- + static void igb_set_itr(struct igb_adapter *adapter) + { + u16 current_itr; +@@ -2544,36 +2774,34 @@ + } + + adapter->rx_itr = igb_update_itr(adapter, +- adapter->rx_itr, +- adapter->rx_ring->total_packets, +- adapter->rx_ring->total_bytes); ++ adapter->rx_itr, ++ adapter->rx_ring->total_packets, ++ adapter->rx_ring->total_bytes); + + if (adapter->rx_ring->buddy) { + adapter->tx_itr = igb_update_itr(adapter, +- adapter->tx_itr, +- adapter->tx_ring->total_packets, +- adapter->tx_ring->total_bytes); +- ++ adapter->tx_itr, ++ adapter->tx_ring->total_packets, ++ adapter->tx_ring->total_bytes); + current_itr = max(adapter->rx_itr, adapter->tx_itr); + } else { + current_itr = adapter->rx_itr; + } + + /* conservative mode (itr 3) eliminates the lowest_latency setting */ +- if (adapter->itr_setting == 3 && +- current_itr == lowest_latency) ++ if (adapter->itr_setting == 3 && current_itr == lowest_latency) + current_itr = low_latency; + + switch (current_itr) { + /* counts and packets in update_itr are dependent on these numbers */ + case lowest_latency: +- new_itr = 70000; ++ new_itr = 56; /* aka 70,000 ints/sec */ + break; + case low_latency: +- new_itr = 20000; /* aka hwitr = ~200 */ ++ new_itr = 196; /* aka 20,000 ints/sec */ + break; + case bulk_latency: +- new_itr = 4000; ++ new_itr = 980; /* aka 4,000 ints/sec */ + break; + default: + break; +@@ -2592,8 +2820,9 @@ + * by adding intermediate steps when interrupt rate is + * increasing */ + new_itr = new_itr > adapter->itr ? +- min(adapter->itr + (new_itr >> 2), new_itr) : +- new_itr; ++ max((new_itr * adapter->itr) / ++ (new_itr + (adapter->itr >> 2)), new_itr) : ++ new_itr; + /* Don't write the value here; it resets the adapter's + * internal timer, and causes us to delay far longer than + * we should between interrupts. Instead, we write the ITR +@@ -2601,25 +2830,25 @@ + * ends up being correct. + */ + adapter->itr = new_itr; +- adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256); ++ adapter->rx_ring->itr_val = new_itr; + adapter->rx_ring->set_itr = 1; + } + + return; + } +- + + #define IGB_TX_FLAGS_CSUM 0x00000001 + #define IGB_TX_FLAGS_VLAN 0x00000002 + #define IGB_TX_FLAGS_TSO 0x00000004 + #define IGB_TX_FLAGS_IPV4 0x00000008 +-#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 +-#define IGB_TX_FLAGS_VLAN_SHIFT 16 ++#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 ++#define IGB_TX_FLAGS_VLAN_SHIFT 16 + + static inline int igb_tso_adv(struct igb_adapter *adapter, +- struct igb_ring *tx_ring, +- struct sk_buff *skb, u32 tx_flags, u8 *hdr_len) +-{ ++ struct igb_ring *tx_ring, ++ struct sk_buff *skb, u32 tx_flags, u8 *hdr_len) ++{ ++#ifdef NETIF_F_TSO + struct e1000_adv_tx_context_desc *context_desc; + unsigned int i; + int err; +@@ -2645,11 +2874,13 @@ + iph->daddr, 0, + IPPROTO_TCP, + 0); ++#ifdef NETIF_F_TSO6 + } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { + ipv6_hdr(skb)->payload_len = 0; + tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, + &ipv6_hdr(skb)->daddr, + 0, IPPROTO_TCP, 0); ++#endif + } + + i = tx_ring->next_to_use; +@@ -2678,7 +2909,7 @@ + mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT); + mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT); + +- /* Context index must be unique per ring. */ ++ /* For 82575, context index must be unique per ring. */ + if (adapter->flags & IGB_FLAG_NEED_CTX_IDX) + mss_l4len_idx |= tx_ring->queue_index << 4; + +@@ -2686,6 +2917,7 @@ + context_desc->seqnum_seed = 0; + + buffer_info->time_stamp = jiffies; ++ buffer_info->next_to_watch = i; + buffer_info->dma = 0; + i++; + if (i == tx_ring->count) +@@ -2693,12 +2925,15 @@ + + tx_ring->next_to_use = i; + +- return true; ++ return TRUE; ++#else ++ return FALSE; ++#endif /* NETIF_F_TSO */ + } + + static inline bool igb_tx_csum_adv(struct igb_adapter *adapter, +- struct igb_ring *tx_ring, +- struct sk_buff *skb, u32 tx_flags) ++ struct igb_ring *tx_ring, ++ struct sk_buff *skb, u32 tx_flags) + { + struct e1000_adv_tx_context_desc *context_desc; + unsigned int i; +@@ -2713,6 +2948,7 @@ + + if (tx_flags & IGB_TX_FLAGS_VLAN) + info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); ++ + info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); + if (skb->ip_summed == CHECKSUM_PARTIAL) + info |= skb_network_header_len(skb); +@@ -2728,16 +2964,19 @@ + if (ip_hdr(skb)->protocol == IPPROTO_TCP) + tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; + break; ++#ifdef NETIF_F_IPV6_CSUM + case __constant_htons(ETH_P_IPV6): + /* XXX what about other V6 headers?? */ + if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) + tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; + break; ++#endif + default: +- if (unlikely(net_ratelimit())) +- dev_warn(&adapter->pdev->dev, +- "partial checksum but proto=%x!\n", +- skb->protocol); ++ if (unlikely(net_ratelimit())) { ++ DPRINTK(PROBE, WARNING, ++ "partial checksum but proto=%x!\n", ++ skb->protocol); ++ } + break; + } + } +@@ -2747,8 +2986,11 @@ + if (adapter->flags & IGB_FLAG_NEED_CTX_IDX) + context_desc->mss_l4len_idx = + cpu_to_le32(tx_ring->queue_index << 4); ++ else ++ context_desc->mss_l4len_idx = 0; + + buffer_info->time_stamp = jiffies; ++ buffer_info->next_to_watch = i; + buffer_info->dma = 0; + + i++; +@@ -2756,19 +2998,17 @@ + i = 0; + tx_ring->next_to_use = i; + +- return true; +- } +- +- +- return false; ++ return TRUE; ++ } ++ return FALSE; + } + + #define IGB_MAX_TXD_PWR 16 + #define IGB_MAX_DATA_PER_TXD (1<length = len; + /* set time_stamp *before* dma to help avoid a possible race */ + buffer_info->time_stamp = jiffies; ++ buffer_info->next_to_watch = i; + buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len, +- PCI_DMA_TODEVICE); ++ PCI_DMA_TODEVICE); + count++; + i++; + if (i == tx_ring->count) +@@ -2799,11 +3040,12 @@ + BUG_ON(len >= IGB_MAX_DATA_PER_TXD); + buffer_info->length = len; + buffer_info->time_stamp = jiffies; +- buffer_info->dma = pci_map_page(adapter->pdev, +- frag->page, +- frag->page_offset, +- len, +- PCI_DMA_TODEVICE); ++ buffer_info->next_to_watch = i; ++ buffer_info->page_dma = pci_map_page(adapter->pdev, ++ frag->page, ++ frag->page_offset, ++ len, ++ PCI_DMA_TODEVICE); + + count++; + i++; +@@ -2811,16 +3053,17 @@ + i = 0; + } + +- i = (i == 0) ? tx_ring->count - 1 : i - 1; ++ i = ((i == 0) ? tx_ring->count - 1 : i - 1); + tx_ring->buffer_info[i].skb = skb; ++ tx_ring->buffer_info[first].next_to_watch = i; + + return count; + } + + static inline void igb_tx_queue_adv(struct igb_adapter *adapter, +- struct igb_ring *tx_ring, +- int tx_flags, int count, u32 paylen, +- u8 hdr_len) ++ struct igb_ring *tx_ring, ++ int tx_flags, int count, u32 paylen, ++ u8 hdr_len) + { + union e1000_adv_tx_desc *tx_desc = NULL; + struct igb_buffer *buffer_info; +@@ -2828,7 +3071,7 @@ + unsigned int i; + + cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS | +- E1000_ADVTXD_DCMD_DEXT); ++ E1000_ADVTXD_DCMD_DEXT); + + if (tx_flags & IGB_TX_FLAGS_VLAN) + cmd_type_len |= E1000_ADVTXD_DCMD_VLE; +@@ -2858,7 +3101,9 @@ + while (count--) { + buffer_info = &tx_ring->buffer_info[i]; + tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); +- tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); ++ tx_desc->read.buffer_addr = buffer_info->dma ? ++ cpu_to_le64(buffer_info->dma) : ++ cpu_to_le64(buffer_info->page_dma); + tx_desc->read.cmd_type_len = + cpu_to_le32(cmd_type_len | buffer_info->length); + tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); +@@ -2882,11 +3127,14 @@ + } + + static int __igb_maybe_stop_tx(struct net_device *netdev, +- struct igb_ring *tx_ring, int size) +-{ +- struct igb_adapter *adapter = netdev_priv(netdev); +- +- netif_stop_subqueue(netdev, tx_ring->queue_index); ++ struct igb_ring *tx_ring, int size) ++{ ++ struct igb_adapter *adapter = netdev_priv(netdev); ++ ++ if (netif_is_multiqueue(netdev)) ++ netif_stop_subqueue(netdev, tx_ring->queue_index); ++ else ++ netif_stop_queue(netdev); + + /* Herbert's original patch had: + * smp_mb__after_netif_stop_queue(); +@@ -2899,13 +3147,16 @@ + return -EBUSY; + + /* A reprieve! */ +- netif_wake_subqueue(netdev, tx_ring->queue_index); ++ if (netif_is_multiqueue(netdev)) ++ netif_wake_subqueue(netdev, tx_ring->queue_index); ++ else ++ netif_wake_queue(netdev); + ++adapter->restart_queue; + return 0; + } + + static int igb_maybe_stop_tx(struct net_device *netdev, +- struct igb_ring *tx_ring, int size) ++ struct igb_ring *tx_ring, int size) + { + if (IGB_DESC_UNUSED(tx_ring) >= size) + return 0; +@@ -2915,10 +3166,11 @@ + #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1) + + static int igb_xmit_frame_ring_adv(struct sk_buff *skb, +- struct net_device *netdev, +- struct igb_ring *tx_ring) +-{ +- struct igb_adapter *adapter = netdev_priv(netdev); ++ struct net_device *netdev, ++ struct igb_ring *tx_ring) ++{ ++ struct igb_adapter *adapter = netdev_priv(netdev); ++ unsigned int first; + unsigned int tx_flags = 0; + unsigned int len; + u8 hdr_len = 0; +@@ -2945,7 +3197,6 @@ + /* this is a hard error */ + return NETDEV_TX_BUSY; + } +- skb_orphan(skb); + + if (adapter->vlgrp && vlan_tx_tag_present(skb)) { + tx_flags |= IGB_TX_FLAGS_VLAN; +@@ -2955,8 +3206,11 @@ + if (skb->protocol == htons(ETH_P_IP)) + tx_flags |= IGB_TX_FLAGS_IPV4; + ++ first = tx_ring->next_to_use; ++#ifdef NETIF_F_TSO + tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags, +- &hdr_len) : 0; ++ &hdr_len) : 0; ++#endif + + if (tso < 0) { + dev_kfree_skb_any(skb); +@@ -2965,13 +3219,13 @@ + + if (tso) + tx_flags |= IGB_TX_FLAGS_TSO; +- else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags)) +- if (skb->ip_summed == CHECKSUM_PARTIAL) +- tx_flags |= IGB_TX_FLAGS_CSUM; ++ else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) && ++ (skb->ip_summed == CHECKSUM_PARTIAL)) ++ tx_flags |= IGB_TX_FLAGS_CSUM; + + igb_tx_queue_adv(adapter, tx_ring, tx_flags, +- igb_tx_map_adv(adapter, tx_ring, skb), +- skb->len, hdr_len); ++ igb_tx_map_adv(adapter, tx_ring, skb, first), ++ skb->len, hdr_len); + + netdev->trans_start = jiffies; + +@@ -2986,15 +3240,19 @@ + struct igb_adapter *adapter = netdev_priv(netdev); + struct igb_ring *tx_ring; + ++#ifdef HAVE_TX_MQ + int r_idx = 0; +- r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1); ++ r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1); + tx_ring = adapter->multi_tx_table[r_idx]; ++#else ++ tx_ring = &adapter->tx_ring[0]; ++#endif + + /* This goes back to the question of how to logically map a tx queue + * to a flow. Right now, performance is impacted slightly negatively + * if using multiple tx queues. If the stack breaks away from a + * single qdisc implementation, we can look at this again. */ +- return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring)); ++ return igb_xmit_frame_ring_adv(skb, netdev, tx_ring); + } + + /** +@@ -3008,9 +3266,10 @@ + + /* Do the reset outside of interrupt context */ + adapter->tx_timeout_count++; ++ + schedule_work(&adapter->reset_task); +- wr32(E1000_EICS, adapter->eims_enable_mask & +- ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER)); ++ E1000_WRITE_REG(hw, E1000_EICS, ++ (adapter->eims_enable_mask & ~adapter->eims_other)); + } + + static void igb_reset_task(struct work_struct *work) +@@ -3028,8 +3287,7 @@ + * Returns the address of the device statistics structure. + * The statistics are actually updated from the timer callback. + **/ +-static struct net_device_stats * +-igb_get_stats(struct net_device *netdev) ++static struct net_device_stats *igb_get_stats(struct net_device *netdev) + { + struct igb_adapter *adapter = netdev_priv(netdev); + +@@ -3049,20 +3307,20 @@ + struct igb_adapter *adapter = netdev_priv(netdev); + int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; + +- if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || +- (max_frame > MAX_JUMBO_FRAME_SIZE)) { +- dev_err(&adapter->pdev->dev, "Invalid MTU setting\n"); ++ if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { ++ DPRINTK(PROBE, ERR, "Invalid MTU setting\n"); + return -EINVAL; + } + + #define MAX_STD_JUMBO_FRAME_SIZE 9234 + if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { +- dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n"); ++ DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n"); + return -EINVAL; + } + + while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) + msleep(1); ++ + /* igb_down has a dependency on max_frame_size */ + adapter->max_frame_size = max_frame; + if (netif_running(netdev)) +@@ -3082,19 +3340,28 @@ + adapter->rx_buffer_len = IGB_RXBUFFER_1024; + else if (max_frame <= IGB_RXBUFFER_2048) + adapter->rx_buffer_len = IGB_RXBUFFER_2048; ++#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT + else + #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384 + adapter->rx_buffer_len = IGB_RXBUFFER_16384; + #else + adapter->rx_buffer_len = PAGE_SIZE / 2; ++#endif ++#else ++ else if (max_frame <= IGB_RXBUFFER_4096) ++ adapter->rx_buffer_len = IGB_RXBUFFER_4096; ++ else if (max_frame <= IGB_RXBUFFER_8192) ++ adapter->rx_buffer_len = IGB_RXBUFFER_8192; ++ else if (max_frame <= IGB_RXBUFFER_16384) ++ adapter->rx_buffer_len = IGB_RXBUFFER_16384; + #endif + /* adjust allocation if LPE protects us, and we aren't using SBP */ + if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || + (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)) + adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; + +- dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n", +- netdev->mtu, new_mtu); ++ DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", ++ netdev->mtu, new_mtu); + netdev->mtu = new_mtu; + + if (netif_running(netdev)) +@@ -3115,7 +3382,9 @@ + void igb_update_stats(struct igb_adapter *adapter) + { + struct e1000_hw *hw = &adapter->hw; +- struct pci_dev *pdev = adapter->pdev; ++#ifdef HAVE_PCI_ERS ++ struct pci_dev *pdev = adapter->pdev; ++#endif + u16 phy_tmp; + + #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF +@@ -3126,81 +3395,79 @@ + */ + if (adapter->link_speed == 0) + return; ++#ifdef HAVE_PCI_ERS + if (pci_channel_offline(pdev)) + return; +- +- adapter->stats.crcerrs += rd32(E1000_CRCERRS); +- adapter->stats.gprc += rd32(E1000_GPRC); +- adapter->stats.gorc += rd32(E1000_GORCL); +- rd32(E1000_GORCH); /* clear GORCL */ +- adapter->stats.bprc += rd32(E1000_BPRC); +- adapter->stats.mprc += rd32(E1000_MPRC); +- adapter->stats.roc += rd32(E1000_ROC); +- +- adapter->stats.prc64 += rd32(E1000_PRC64); +- adapter->stats.prc127 += rd32(E1000_PRC127); +- adapter->stats.prc255 += rd32(E1000_PRC255); +- adapter->stats.prc511 += rd32(E1000_PRC511); +- adapter->stats.prc1023 += rd32(E1000_PRC1023); +- adapter->stats.prc1522 += rd32(E1000_PRC1522); +- adapter->stats.symerrs += rd32(E1000_SYMERRS); +- adapter->stats.sec += rd32(E1000_SEC); +- +- adapter->stats.mpc += rd32(E1000_MPC); +- adapter->stats.scc += rd32(E1000_SCC); +- adapter->stats.ecol += rd32(E1000_ECOL); +- adapter->stats.mcc += rd32(E1000_MCC); +- adapter->stats.latecol += rd32(E1000_LATECOL); +- adapter->stats.dc += rd32(E1000_DC); +- adapter->stats.rlec += rd32(E1000_RLEC); +- adapter->stats.xonrxc += rd32(E1000_XONRXC); +- adapter->stats.xontxc += rd32(E1000_XONTXC); +- adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); +- adapter->stats.xofftxc += rd32(E1000_XOFFTXC); +- adapter->stats.fcruc += rd32(E1000_FCRUC); +- adapter->stats.gptc += rd32(E1000_GPTC); +- adapter->stats.gotc += rd32(E1000_GOTCL); +- rd32(E1000_GOTCH); /* clear GOTCL */ +- adapter->stats.rnbc += rd32(E1000_RNBC); +- adapter->stats.ruc += rd32(E1000_RUC); +- adapter->stats.rfc += rd32(E1000_RFC); +- adapter->stats.rjc += rd32(E1000_RJC); +- adapter->stats.tor += rd32(E1000_TORH); +- adapter->stats.tot += rd32(E1000_TOTH); +- adapter->stats.tpr += rd32(E1000_TPR); +- +- adapter->stats.ptc64 += rd32(E1000_PTC64); +- adapter->stats.ptc127 += rd32(E1000_PTC127); +- adapter->stats.ptc255 += rd32(E1000_PTC255); +- adapter->stats.ptc511 += rd32(E1000_PTC511); +- adapter->stats.ptc1023 += rd32(E1000_PTC1023); +- adapter->stats.ptc1522 += rd32(E1000_PTC1522); +- +- adapter->stats.mptc += rd32(E1000_MPTC); +- adapter->stats.bptc += rd32(E1000_BPTC); +- +- /* used for adaptive IFS */ +- +- hw->mac.tx_packet_delta = rd32(E1000_TPT); +- adapter->stats.tpt += hw->mac.tx_packet_delta; +- hw->mac.collision_delta = rd32(E1000_COLC); +- adapter->stats.colc += hw->mac.collision_delta; +- +- adapter->stats.algnerrc += rd32(E1000_ALGNERRC); +- adapter->stats.rxerrc += rd32(E1000_RXERRC); +- adapter->stats.tncrs += rd32(E1000_TNCRS); +- adapter->stats.tsctc += rd32(E1000_TSCTC); +- adapter->stats.tsctfc += rd32(E1000_TSCTFC); +- +- adapter->stats.iac += rd32(E1000_IAC); +- adapter->stats.icrxoc += rd32(E1000_ICRXOC); +- adapter->stats.icrxptc += rd32(E1000_ICRXPTC); +- adapter->stats.icrxatc += rd32(E1000_ICRXATC); +- adapter->stats.ictxptc += rd32(E1000_ICTXPTC); +- adapter->stats.ictxatc += rd32(E1000_ICTXATC); +- adapter->stats.ictxqec += rd32(E1000_ICTXQEC); +- adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); +- adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); ++#endif ++ ++ adapter->stats.crcerrs += E1000_READ_REG(hw, E1000_CRCERRS); ++ adapter->stats.gprc += E1000_READ_REG(hw, E1000_GPRC); ++ adapter->stats.gorc += E1000_READ_REG(hw, E1000_GORCL); ++ E1000_READ_REG(hw, E1000_GORCH); /* clear GORCL */ ++ adapter->stats.bprc += E1000_READ_REG(hw, E1000_BPRC); ++ adapter->stats.mprc += E1000_READ_REG(hw, E1000_MPRC); ++ adapter->stats.roc += E1000_READ_REG(hw, E1000_ROC); ++ ++ adapter->stats.prc64 += E1000_READ_REG(hw, E1000_PRC64); ++ adapter->stats.prc127 += E1000_READ_REG(hw, E1000_PRC127); ++ adapter->stats.prc255 += E1000_READ_REG(hw, E1000_PRC255); ++ adapter->stats.prc511 += E1000_READ_REG(hw, E1000_PRC511); ++ adapter->stats.prc1023 += E1000_READ_REG(hw, E1000_PRC1023); ++ adapter->stats.prc1522 += E1000_READ_REG(hw, E1000_PRC1522); ++ adapter->stats.symerrs += E1000_READ_REG(hw, E1000_SYMERRS); ++ adapter->stats.sec += E1000_READ_REG(hw, E1000_SEC); ++ ++ adapter->stats.mpc += E1000_READ_REG(hw, E1000_MPC); ++ adapter->stats.scc += E1000_READ_REG(hw, E1000_SCC); ++ adapter->stats.ecol += E1000_READ_REG(hw, E1000_ECOL); ++ adapter->stats.mcc += E1000_READ_REG(hw, E1000_MCC); ++ adapter->stats.latecol += E1000_READ_REG(hw, E1000_LATECOL); ++ adapter->stats.dc += E1000_READ_REG(hw, E1000_DC); ++ adapter->stats.rlec += E1000_READ_REG(hw, E1000_RLEC); ++ adapter->stats.xonrxc += E1000_READ_REG(hw, E1000_XONRXC); ++ adapter->stats.xontxc += E1000_READ_REG(hw, E1000_XONTXC); ++ adapter->stats.xoffrxc += E1000_READ_REG(hw, E1000_XOFFRXC); ++ adapter->stats.xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC); ++ adapter->stats.fcruc += E1000_READ_REG(hw, E1000_FCRUC); ++ adapter->stats.gptc += E1000_READ_REG(hw, E1000_GPTC); ++ adapter->stats.gotc += E1000_READ_REG(hw, E1000_GOTCL); ++ E1000_READ_REG(hw, E1000_GOTCH); /* clear GOTCL */ ++ adapter->stats.rnbc += E1000_READ_REG(hw, E1000_RNBC); ++ adapter->stats.ruc += E1000_READ_REG(hw, E1000_RUC); ++ adapter->stats.rfc += E1000_READ_REG(hw, E1000_RFC); ++ adapter->stats.rjc += E1000_READ_REG(hw, E1000_RJC); ++ adapter->stats.tor += E1000_READ_REG(hw, E1000_TORH); ++ adapter->stats.tot += E1000_READ_REG(hw, E1000_TOTH); ++ adapter->stats.tpr += E1000_READ_REG(hw, E1000_TPR); ++ ++ adapter->stats.ptc64 += E1000_READ_REG(hw, E1000_PTC64); ++ adapter->stats.ptc127 += E1000_READ_REG(hw, E1000_PTC127); ++ adapter->stats.ptc255 += E1000_READ_REG(hw, E1000_PTC255); ++ adapter->stats.ptc511 += E1000_READ_REG(hw, E1000_PTC511); ++ adapter->stats.ptc1023 += E1000_READ_REG(hw, E1000_PTC1023); ++ adapter->stats.ptc1522 += E1000_READ_REG(hw, E1000_PTC1522); ++ ++ adapter->stats.mptc += E1000_READ_REG(hw, E1000_MPTC); ++ adapter->stats.bptc += E1000_READ_REG(hw, E1000_BPTC); ++ ++ adapter->stats.tpt += E1000_READ_REG(hw, E1000_TPT); ++ adapter->stats.colc += E1000_READ_REG(hw, E1000_COLC); ++ ++ adapter->stats.algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC); ++ adapter->stats.rxerrc += E1000_READ_REG(hw, E1000_RXERRC); ++ adapter->stats.tncrs += E1000_READ_REG(hw, E1000_TNCRS); ++ adapter->stats.tsctc += E1000_READ_REG(hw, E1000_TSCTC); ++ adapter->stats.tsctfc += E1000_READ_REG(hw, E1000_TSCTFC); ++ ++ adapter->stats.iac += E1000_READ_REG(hw, E1000_IAC); ++ adapter->stats.icrxoc += E1000_READ_REG(hw, E1000_ICRXOC); ++ adapter->stats.icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC); ++ adapter->stats.icrxatc += E1000_READ_REG(hw, E1000_ICRXATC); ++ adapter->stats.ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC); ++ adapter->stats.ictxatc += E1000_READ_REG(hw, E1000_ICTXATC); ++ adapter->stats.ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC); ++ adapter->stats.ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC); ++ adapter->stats.icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC); + + /* Fill out the OS statistics structure */ + adapter->net_stats.multicast = adapter->stats.mprc; +@@ -3215,14 +3482,14 @@ + adapter->stats.ruc + adapter->stats.roc + + adapter->stats.cexterr; + adapter->net_stats.rx_length_errors = adapter->stats.ruc + +- adapter->stats.roc; ++ adapter->stats.roc; + adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; + adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc; + adapter->net_stats.rx_missed_errors = adapter->stats.mpc; + + /* Tx Errors */ + adapter->net_stats.tx_errors = adapter->stats.ecol + +- adapter->stats.latecol; ++ adapter->stats.latecol; + adapter->net_stats.tx_aborted_errors = adapter->stats.ecol; + adapter->net_stats.tx_window_errors = adapter->stats.latecol; + adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs; +@@ -3232,52 +3499,56 @@ + /* Phy Stats */ + if (hw->phy.media_type == e1000_media_type_copper) { + if ((adapter->link_speed == SPEED_1000) && +- (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS, +- &phy_tmp))) { ++ (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { + phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; + adapter->phy_stats.idle_errors += phy_tmp; + } + } + + /* Management Stats */ +- adapter->stats.mgptc += rd32(E1000_MGTPTC); +- adapter->stats.mgprc += rd32(E1000_MGTPRC); +- adapter->stats.mgpdc += rd32(E1000_MGTPDC); +-} +- ++ adapter->stats.mgptc += E1000_READ_REG(hw, E1000_MGTPTC); ++ adapter->stats.mgprc += E1000_READ_REG(hw, E1000_MGTPRC); ++ adapter->stats.mgpdc += E1000_READ_REG(hw, E1000_MGTPDC); ++} + + static irqreturn_t igb_msix_other(int irq, void *data) + { + struct net_device *netdev = data; + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +- u32 icr = rd32(E1000_ICR); +- ++ u32 icr = E1000_READ_REG(hw, E1000_ICR); + /* reading ICR causes bit 31 of EICR to be cleared */ ++ ++ if (icr & E1000_ICR_DOUTSYNC) { ++ /* HW is reporting DMA is out of sync */ ++ adapter->stats.doosync++; ++ } + if (!(icr & E1000_ICR_LSC)) + goto no_link_interrupt; + hw->mac.get_link_status = 1; + /* guard against interrupt when we're going down */ + if (!test_bit(__IGB_DOWN, &adapter->state)) + mod_timer(&adapter->watchdog_timer, jiffies + 1); +- ++ + no_link_interrupt: +- wr32(E1000_IMS, E1000_IMS_LSC); +- wr32(E1000_EIMS, adapter->eims_other); +- +- return IRQ_HANDLED; +-} +- ++ E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC); ++ E1000_WRITE_REG(hw, E1000_EIMS, adapter->eims_other); ++ ++ return IRQ_HANDLED; ++} ++ ++#ifdef CONFIG_IGB_SEPARATE_TX_HANDLER + static irqreturn_t igb_msix_tx(int irq, void *data) + { + struct igb_ring *tx_ring = data; + struct igb_adapter *adapter = tx_ring->adapter; + struct e1000_hw *hw = &adapter->hw; + +-#ifdef CONFIG_DCA ++#ifdef IGB_DCA + if (adapter->flags & IGB_FLAG_DCA_ENABLED) + igb_update_tx_dca(tx_ring); + #endif ++ + tx_ring->total_bytes = 0; + tx_ring->total_packets = 0; + +@@ -3285,27 +3556,26 @@ + * EICS */ + if (!igb_clean_tx_irq(tx_ring)) + /* Ring was not completely cleaned, so fire another interrupt */ +- wr32(E1000_EICS, tx_ring->eims_value); +- else +- wr32(E1000_EIMS, tx_ring->eims_value); +- +- return IRQ_HANDLED; +-} +- ++ E1000_WRITE_REG(hw, E1000_EICS, tx_ring->eims_value); ++ else ++ E1000_WRITE_REG(hw, E1000_EIMS, tx_ring->eims_value); ++ ++ return IRQ_HANDLED; ++} ++ ++#endif /* CONFIG_IGB_SEPARATE_TX_HANDLER */ + static void igb_write_itr(struct igb_ring *ring) + { + struct e1000_hw *hw = &ring->adapter->hw; +- if ((ring->adapter->itr_setting & 3) && ring->set_itr) { ++ if (ring->set_itr) { + switch (hw->mac.type) { + case e1000_82576: +- wr32(ring->itr_register, +- ring->itr_val | +- 0x80000000); ++ E1000_WRITE_REG(hw, ring->itr_register, ring->itr_val | ++ 0x80000000); + break; + default: +- wr32(ring->itr_register, +- ring->itr_val | +- (ring->itr_val << 16)); ++ E1000_WRITE_REG(hw, ring->itr_register, ring->itr_val | ++ (ring->itr_val << 16)); + break; + } + ring->set_itr = 0; +@@ -3315,47 +3585,40 @@ + static irqreturn_t igb_msix_rx(int irq, void *data) + { + struct igb_ring *rx_ring = data; +- struct igb_adapter *adapter = rx_ring->adapter; + + /* Write the ITR value calculated at the end of the + * previous interrupt. + */ +- + igb_write_itr(rx_ring); + +- if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi)) +- __netif_rx_schedule(adapter->netdev, &rx_ring->napi); +- +-#ifdef CONFIG_DCA +- if (adapter->flags & IGB_FLAG_DCA_ENABLED) +- igb_update_rx_dca(rx_ring); +-#endif +- return IRQ_HANDLED; +-} +- +-#ifdef CONFIG_DCA ++ if (napi_schedule_prep(&rx_ring->napi)) ++ __napi_schedule(&rx_ring->napi); ++ return IRQ_HANDLED; ++} ++ ++#ifdef IGB_DCA + static void igb_update_rx_dca(struct igb_ring *rx_ring) + { + u32 dca_rxctrl; + struct igb_adapter *adapter = rx_ring->adapter; + struct e1000_hw *hw = &adapter->hw; + int cpu = get_cpu(); +- int q = rx_ring - adapter->rx_ring; ++ int q = rx_ring->reg_idx; + + if (rx_ring->cpu != cpu) { +- dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); ++ dca_rxctrl = E1000_READ_REG(hw, E1000_DCA_RXCTRL(q)); + if (hw->mac.type == e1000_82576) { + dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576; +- dca_rxctrl |= dca_get_tag(cpu) << +- E1000_DCA_RXCTRL_CPUID_SHIFT; ++ dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << ++ E1000_DCA_RXCTRL_CPUID_SHIFT_82576; + } else { + dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; +- dca_rxctrl |= dca_get_tag(cpu); ++ dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); + } + dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; + dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; + dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; +- wr32(E1000_DCA_RXCTRL(q), dca_rxctrl); ++ E1000_WRITE_REG(hw, E1000_DCA_RXCTRL(q), dca_rxctrl); + rx_ring->cpu = cpu; + } + put_cpu(); +@@ -3367,20 +3630,20 @@ + struct igb_adapter *adapter = tx_ring->adapter; + struct e1000_hw *hw = &adapter->hw; + int cpu = get_cpu(); +- int q = tx_ring - adapter->tx_ring; ++ int q = tx_ring->reg_idx; + + if (tx_ring->cpu != cpu) { +- dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); ++ dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(q)); + if (hw->mac.type == e1000_82576) { + dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576; +- dca_txctrl |= dca_get_tag(cpu) << +- E1000_DCA_TXCTRL_CPUID_SHIFT; ++ dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << ++ E1000_DCA_TXCTRL_CPUID_SHIFT_82576; + } else { + dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; +- dca_txctrl |= dca_get_tag(cpu); ++ dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); + } + dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; +- wr32(E1000_DCA_TXCTRL(q), dca_txctrl); ++ E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(q), dca_txctrl); + tx_ring->cpu = cpu; + } + put_cpu(); +@@ -3388,10 +3651,14 @@ + + static void igb_setup_dca(struct igb_adapter *adapter) + { ++ struct e1000_hw *hw = &adapter->hw; + int i; + + if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) + return; ++ ++ /* Always use CB2 mode, difference is masked in the CB driver. */ ++ E1000_WRITE_REG(hw, E1000_DCA_CTRL, 2); + + for (i = 0; i < adapter->num_tx_queues; i++) { + adapter->tx_ring[i].cpu = -1; +@@ -3418,12 +3685,9 @@ + /* if already enabled, don't do it again */ + if (adapter->flags & IGB_FLAG_DCA_ENABLED) + break; +- adapter->flags |= IGB_FLAG_DCA_ENABLED; +- /* Always use CB2 mode, difference is masked +- * in the CB driver. */ +- wr32(E1000_DCA_CTRL, 2); +- if (dca_add_requester(dev) == 0) { +- dev_info(&adapter->pdev->dev, "DCA enabled\n"); ++ if (dca_add_requester(dev) == E1000_SUCCESS) { ++ adapter->flags |= IGB_FLAG_DCA_ENABLED; ++ DPRINTK(PROBE, INFO, "DCA enabled\n"); + igb_setup_dca(adapter); + break; + } +@@ -3431,16 +3695,16 @@ + case DCA_PROVIDER_REMOVE: + if (adapter->flags & IGB_FLAG_DCA_ENABLED) { + /* without this a class_device is left +- * hanging around in the sysfs model */ ++ * hanging around in the sysfs model */ + dca_remove_requester(dev); +- dev_info(&adapter->pdev->dev, "DCA disabled\n"); ++ DPRINTK(PROBE, INFO, "DCA disabled\n"); + adapter->flags &= ~IGB_FLAG_DCA_ENABLED; +- wr32(E1000_DCA_CTRL, 1); ++ E1000_WRITE_REG(hw, E1000_DCA_CTRL, 1); + } + break; + } + out: +- return 0; ++ return E1000_SUCCESS; + } + + static int igb_notify_dca(struct notifier_block *nb, unsigned long event, +@@ -3453,7 +3717,7 @@ + + return ret_val ? NOTIFY_BAD : NOTIFY_DONE; + } +-#endif /* CONFIG_DCA */ ++#endif /* IGB_DCA */ + + /** + * igb_intr_msi - Interrupt Handler +@@ -3466,9 +3730,14 @@ + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; + /* read ICR disables interrupts using IAM */ +- u32 icr = rd32(E1000_ICR); ++ u32 icr = E1000_READ_REG(hw, E1000_ICR); + + igb_write_itr(adapter->rx_ring); ++ ++ if (icr & E1000_ICR_DOUTSYNC) { ++ /* HW is reporting DMA is out of sync */ ++ adapter->stats.doosync++; ++ } + + if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { + hw->mac.get_link_status = 1; +@@ -3476,13 +3745,13 @@ + mod_timer(&adapter->watchdog_timer, jiffies + 1); + } + +- netif_rx_schedule(netdev, &adapter->rx_ring[0].napi); +- +- return IRQ_HANDLED; +-} +- +-/** +- * igb_intr - Interrupt Handler ++ napi_schedule(&adapter->rx_ring[0].napi); ++ ++ return IRQ_HANDLED; ++} ++ ++/** ++ * igb_intr - Legacy Interrupt Handler + * @irq: interrupt number + * @data: pointer to a network interface device structure + **/ +@@ -3493,8 +3762,7 @@ + struct e1000_hw *hw = &adapter->hw; + /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No + * need for the IMC write */ +- u32 icr = rd32(E1000_ICR); +- u32 eicr = 0; ++ u32 icr = E1000_READ_REG(hw, E1000_ICR); + if (!icr) + return IRQ_NONE; /* Not our interrupt */ + +@@ -3505,7 +3773,10 @@ + if (!(icr & E1000_ICR_INT_ASSERTED)) + return IRQ_NONE; + +- eicr = rd32(E1000_EICR); ++ if (icr & E1000_ICR_DOUTSYNC) { ++ /* HW is reporting DMA is out of sync */ ++ adapter->stats.doosync++; ++ } + + if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { + hw->mac.get_link_status = 1; +@@ -3514,9 +3785,29 @@ + mod_timer(&adapter->watchdog_timer, jiffies + 1); + } + +- netif_rx_schedule(netdev, &adapter->rx_ring[0].napi); +- +- return IRQ_HANDLED; ++ napi_schedule(&adapter->rx_ring[0].napi); ++ ++ return IRQ_HANDLED; ++} ++ ++static inline void igb_rx_irq_enable(struct igb_ring *rx_ring) ++{ ++ struct igb_adapter *adapter = rx_ring->adapter; ++ struct e1000_hw *hw = &adapter->hw; ++ ++ if (adapter->itr_setting & 3) { ++ if (adapter->num_rx_queues == 1) ++ igb_set_itr(adapter); ++ else ++ igb_update_ring_itr(rx_ring); ++ } ++ ++ if (!test_bit(__IGB_DOWN, &adapter->state)) { ++ if (adapter->msix_entries) ++ E1000_WRITE_REG(hw, E1000_EIMS, rx_ring->eims_value); ++ else ++ igb_irq_enable(adapter); ++ } + } + + /** +@@ -3527,195 +3818,157 @@ + static int igb_poll(struct napi_struct *napi, int budget) + { + struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi); +- struct igb_adapter *adapter = rx_ring->adapter; +- struct net_device *netdev = adapter->netdev; +- int tx_clean_complete, work_done = 0; +- +- /* this poll routine only supports one tx and one rx queue */ +-#ifdef CONFIG_DCA +- if (adapter->flags & IGB_FLAG_DCA_ENABLED) +- igb_update_tx_dca(&adapter->tx_ring[0]); +-#endif +- tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]); +- +-#ifdef CONFIG_DCA +- if (adapter->flags & IGB_FLAG_DCA_ENABLED) +- igb_update_rx_dca(&adapter->rx_ring[0]); +-#endif +- igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget); +- +- /* If no Tx and not enough Rx work done, exit the polling mode */ +- if ((tx_clean_complete && (work_done < budget)) || +- !netif_running(netdev)) { +- if (adapter->itr_setting & 3) +- igb_set_itr(adapter); +- netif_rx_complete(netdev, napi); +- if (!test_bit(__IGB_DOWN, &adapter->state)) +- igb_irq_enable(adapter); +- return 0; +- } +- +- return 1; +-} +- +-static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget) +-{ +- struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi); +- struct igb_adapter *adapter = rx_ring->adapter; +- struct e1000_hw *hw = &adapter->hw; +- struct net_device *netdev = adapter->netdev; +- int work_done = 0; +- +- /* Keep link state information with original netdev */ +- if (!netif_carrier_ok(netdev)) +- goto quit_polling; +- +-#ifdef CONFIG_DCA +- if (adapter->flags & IGB_FLAG_DCA_ENABLED) ++ int tx_clean_complete = 1, work_done = 0; ++ ++ if (rx_ring->buddy) { ++#ifdef IGB_DCA ++ if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED) ++ igb_update_tx_dca(rx_ring->buddy); ++#endif ++ tx_clean_complete = igb_clean_tx_irq(rx_ring->buddy); ++ } ++ ++#ifdef IGB_DCA ++ if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED) + igb_update_rx_dca(rx_ring); ++ + #endif + igb_clean_rx_irq_adv(rx_ring, &work_done, budget); + +- ++ if (!tx_clean_complete) ++ work_done = budget; ++ ++#ifndef HAVE_NETDEV_NAPI_LIST ++ /* if netdev is disabled we need to stop polling */ ++ if (!netif_running(rx_ring->adapter->netdev)) ++ work_done = 0; ++ ++#endif + /* If not enough Rx work done, exit the polling mode */ +- if ((work_done == 0) || !netif_running(netdev)) { +-quit_polling: +- netif_rx_complete(netdev, napi); +- +- if (adapter->itr_setting & 3) { +- if (adapter->num_rx_queues == 1) +- igb_set_itr(adapter); +- else +- igb_update_ring_itr(rx_ring); +- } +- +- if (!test_bit(__IGB_DOWN, &adapter->state)) +- wr32(E1000_EIMS, rx_ring->eims_value); +- +- return 0; +- } +- +- return 1; +-} +- +-static inline u32 get_head(struct igb_ring *tx_ring) +-{ +- void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count; +- return le32_to_cpu(*(volatile __le32 *)end); ++ if (work_done < budget) { ++ napi_complete(napi); ++ igb_rx_irq_enable(rx_ring); ++ } ++ ++ return work_done; + } + + /** + * igb_clean_tx_irq - Reclaim resources after transmit completes + * @adapter: board private structure +- * returns true if ring is completely cleaned ++ * returns TRUE if ring is completely cleaned + **/ + static bool igb_clean_tx_irq(struct igb_ring *tx_ring) + { + struct igb_adapter *adapter = tx_ring->adapter; +- struct e1000_hw *hw = &adapter->hw; +- struct net_device *netdev = adapter->netdev; +- struct e1000_tx_desc *tx_desc; ++ struct net_device *netdev = adapter->netdev; ++ struct e1000_hw *hw = &adapter->hw; + struct igb_buffer *buffer_info; + struct sk_buff *skb; +- unsigned int i; +- u32 head, oldhead; +- unsigned int count = 0; ++ union e1000_adv_tx_desc *tx_desc, *eop_desc; ++ unsigned int total_bytes = 0, total_packets = 0; ++ unsigned int i, eop, count = 0; + bool cleaned = false; +- bool retval = true; +- unsigned int total_bytes = 0, total_packets = 0; +- +- rmb(); +- head = get_head(tx_ring); ++ + i = tx_ring->next_to_clean; +- while (1) { +- while (i != head) { +- cleaned = true; +- tx_desc = E1000_TX_DESC(*tx_ring, i); ++ eop = tx_ring->buffer_info[i].next_to_watch; ++ eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop); ++ ++ while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) && ++ (count < tx_ring->count)) { ++ for (cleaned = false; !cleaned; count++) { ++ tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); + buffer_info = &tx_ring->buffer_info[i]; ++ cleaned = (i == eop); + skb = buffer_info->skb; + + if (skb) { ++#ifdef NETIF_F_TSO + unsigned int segs, bytecount; + /* gso_segs is currently only valid for tcp */ + segs = skb_shinfo(skb)->gso_segs ?: 1; + /* multiply data chunks by size of headers */ + bytecount = ((segs - 1) * skb_headlen(skb)) + +- skb->len; ++ skb->len; + total_packets += segs; + total_bytes += bytecount; ++#else ++ total_packets++; ++ total_bytes += skb->len; ++#endif + } + + igb_unmap_and_free_tx_resource(adapter, buffer_info); +- tx_desc->upper.data = 0; ++ tx_desc->wb.status = 0; + + i++; + if (i == tx_ring->count) + i = 0; +- +- count++; +- if (count == IGB_MAX_TX_CLEAN) { +- retval = false; +- goto done_cleaning; +- } +- } +- oldhead = head; +- rmb(); +- head = get_head(tx_ring); +- if (head == oldhead) +- goto done_cleaning; +- } /* while (1) */ +- +-done_cleaning: ++ } ++ eop = tx_ring->buffer_info[i].next_to_watch; ++ eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop); ++ } ++ + tx_ring->next_to_clean = i; + +- if (unlikely(cleaned && +- netif_carrier_ok(netdev) && +- IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) { ++ if (unlikely(count && ++ netif_carrier_ok(netdev) && ++ IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) { + /* Make sure that anybody stopping the queue after this + * sees the new next_to_clean. + */ + smp_mb(); +- if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && +- !(test_bit(__IGB_DOWN, &adapter->state))) { +- netif_wake_subqueue(netdev, tx_ring->queue_index); +- ++adapter->restart_queue; ++ if (netif_is_multiqueue(netdev)) { ++ if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && ++ !(test_bit(__IGB_DOWN, &adapter->state))) { ++ netif_wake_subqueue(netdev, tx_ring->queue_index); ++ ++adapter->restart_queue; ++ } ++ } else { ++ if (netif_queue_stopped(netdev) && ++ !(test_bit(__IGB_DOWN, &adapter->state))) { ++ netif_wake_queue(netdev); ++ ++adapter->restart_queue; ++ } + } + } + + if (tx_ring->detect_tx_hung) { + /* Detect a transmit hang in hardware, this serializes the + * check with the clearing of time_stamp and movement of i */ +- tx_ring->detect_tx_hung = false; ++ tx_ring->detect_tx_hung = FALSE; + if (tx_ring->buffer_info[i].time_stamp && + time_after(jiffies, tx_ring->buffer_info[i].time_stamp + +- (adapter->tx_timeout_factor * HZ)) +- && !(rd32(E1000_STATUS) & +- E1000_STATUS_TXOFF)) { +- +- tx_desc = E1000_TX_DESC(*tx_ring, i); ++ (adapter->tx_timeout_factor * HZ)) ++ && !(E1000_READ_REG(hw, E1000_STATUS) & ++ E1000_STATUS_TXOFF)) { ++ + /* detected Tx unit hang */ +- dev_err(&adapter->pdev->dev, +- "Detected Tx Unit Hang\n" +- " Tx Queue <%d>\n" +- " TDH <%x>\n" +- " TDT <%x>\n" +- " next_to_use <%x>\n" +- " next_to_clean <%x>\n" +- " head (WB) <%x>\n" +- "buffer_info[next_to_clean]\n" +- " time_stamp <%lx>\n" +- " jiffies <%lx>\n" +- " desc.status <%x>\n", ++ DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" ++ " Tx Queue <%d>\n" ++ " TDH <%x>\n" ++ " TDT <%x>\n" ++ " next_to_use <%x>\n" ++ " next_to_clean <%x>\n" ++ "buffer_info[next_to_clean]\n" ++ " time_stamp <%lx>\n" ++ " next_to_watch <%x>\n" ++ " jiffies <%lx>\n" ++ " desc.status <%x>\n", + tx_ring->queue_index, +- readl(adapter->hw.hw_addr + tx_ring->head), +- readl(adapter->hw.hw_addr + tx_ring->tail), ++ readl(hw->hw_addr + tx_ring->head), ++ readl(hw->hw_addr + tx_ring->tail), + tx_ring->next_to_use, + tx_ring->next_to_clean, +- head, +- tx_ring->buffer_info[i].time_stamp, ++ tx_ring->buffer_info[eop].time_stamp, ++ eop, + jiffies, +- tx_desc->upper.fields.status); +- netif_stop_subqueue(netdev, tx_ring->queue_index); ++ eop_desc->wb.status); ++ if (netif_is_multiqueue(netdev)) ++ netif_stop_subqueue(netdev, ++ tx_ring->queue_index); ++ else ++ netif_stop_queue(netdev); + } + } + tx_ring->total_bytes += total_bytes; +@@ -3724,10 +3977,10 @@ + tx_ring->tx_stats.packets += total_packets; + adapter->net_stats.tx_bytes += total_bytes; + adapter->net_stats.tx_packets += total_packets; +- return retval; +-} +- +-#ifdef CONFIG_IGB_LRO ++ return (count < tx_ring->count); ++} ++ ++#ifdef IGB_LRO + /** + * igb_get_skb_hdr - helper function for LRO header processing + * @skb: pointer to sk_buff to be added to LRO packet +@@ -3740,7 +3993,7 @@ + u64 *hdr_flags, void *priv) + { + union e1000_adv_rx_desc *rx_desc = priv; +- u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info & ++ u16 pkt_type = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info & + (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP); + + /* Verify that this is a valid IPv4 TCP packet */ +@@ -3758,54 +4011,55 @@ + return 0; + + } +-#endif /* CONFIG_IGB_LRO */ ++#endif /* IGB_LRO */ + + /** + * igb_receive_skb - helper function to handle rx indications +- * @ring: pointer to receive ring receving this packet ++ * @ring: pointer to receive ring receving this packet + * @status: descriptor status field as written by hardware +- * @vlan: descriptor vlan field as written by hardware (no le/be conversion) ++ * @rx_desc: receive descriptor containing vlan and type information. + * @skb: pointer to sk_buff to be indicated to stack + **/ + static void igb_receive_skb(struct igb_ring *ring, u8 status, +- union e1000_adv_rx_desc * rx_desc, ++ union e1000_adv_rx_desc *rx_desc, + struct sk_buff *skb) + { +- struct igb_adapter * adapter = ring->adapter; ++ struct igb_adapter *adapter = ring->adapter; + bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP)); + +-#ifdef CONFIG_IGB_LRO ++#ifdef IGB_LRO + if (adapter->netdev->features & NETIF_F_LRO && + skb->ip_summed == CHECKSUM_UNNECESSARY) { + if (vlan_extracted) + lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb, +- adapter->vlgrp, +- le16_to_cpu(rx_desc->wb.upper.vlan), +- rx_desc); +- else +- lro_receive_skb(&ring->lro_mgr,skb, rx_desc); +- ring->lro_used = 1; ++ adapter->vlgrp, ++ le16_to_cpu(rx_desc->wb.upper.vlan), ++ rx_desc); ++ else ++ lro_receive_skb(&ring->lro_mgr, skb, rx_desc); ++ ring->lro_used = TRUE; + } else { + #endif + if (vlan_extracted) +- vlan_hwaccel_receive_skb(skb, adapter->vlgrp, +- le16_to_cpu(rx_desc->wb.upper.vlan)); +- else +- +- netif_receive_skb(skb); +-#ifdef CONFIG_IGB_LRO +- } +-#endif +-} +- ++ vlan_gro_receive(&ring->napi, adapter->vlgrp, ++ le16_to_cpu(rx_desc->wb.upper.vlan), ++ skb); ++ else ++ ++ napi_gro_receive(&ring->napi, skb); ++#ifdef IGB_LRO ++ } ++#endif ++} + + static inline void igb_rx_checksum_adv(struct igb_adapter *adapter, +- u32 status_err, struct sk_buff *skb) ++ u32 status_err, struct sk_buff *skb) + { + skb->ip_summed = CHECKSUM_NONE; + + /* Ignore Checksum bit is set or checksum is disabled through ethtool */ +- if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum) ++ if ((status_err & E1000_RXD_STAT_IXSM) || ++ (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED)) + return; + /* TCP/UDP checksum error bit is set */ + if (status_err & +@@ -3822,7 +4076,7 @@ + } + + static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring, +- int *work_done, int budget) ++ int *work_done, int budget) + { + struct igb_adapter *adapter = rx_ring->adapter; + struct net_device *netdev = adapter->netdev; +@@ -3830,13 +4084,18 @@ + union e1000_adv_rx_desc *rx_desc , *next_rxd; + struct igb_buffer *buffer_info , *next_buffer; + struct sk_buff *skb; +- unsigned int i; +- u32 length, hlen, staterr; +- bool cleaned = false; ++ bool cleaned = FALSE; + int cleaned_count = 0; + unsigned int total_bytes = 0, total_packets = 0; ++ unsigned int i; ++#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT ++ u32 length, hlen, staterr; ++#else ++ u32 length, staterr; ++#endif + + i = rx_ring->next_to_clean; ++ buffer_info = &rx_ring->buffer_info[i]; + rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); + staterr = le32_to_cpu(rx_desc->wb.upper.status_error); + +@@ -3844,72 +4103,90 @@ + if (*work_done >= budget) + break; + (*work_done)++; +- buffer_info = &rx_ring->buffer_info[i]; ++ ++ if (staterr & E1000_RXD_STAT_DYNINT) ++ adapter->lli_int++; ++ ++ skb = buffer_info->skb; ++ prefetch(skb->data - NET_IP_ALIGN); ++ buffer_info->skb = NULL; ++ ++ i++; ++ if (i == rx_ring->count) ++ i = 0; ++ next_rxd = E1000_RX_DESC_ADV(*rx_ring, i); ++ prefetch(next_rxd); ++ next_buffer = &rx_ring->buffer_info[i]; ++ ++ length = le16_to_cpu(rx_desc->wb.upper.length); ++ cleaned = TRUE; ++ cleaned_count++; ++ ++#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT ++ pci_unmap_single(pdev, buffer_info->dma, ++ adapter->rx_buffer_len, ++ PCI_DMA_FROMDEVICE); ++ buffer_info->dma = 0; ++ skb_put(skb, length); ++#else ++ if (!adapter->rx_ps_hdr_size) { ++ pci_unmap_single(pdev, buffer_info->dma, ++ adapter->rx_buffer_len, ++ PCI_DMA_FROMDEVICE); ++ buffer_info->dma = 0; ++ skb_put(skb, length); ++ goto send_up; ++ } + + /* HW will not DMA in data larger than the given buffer, even + * if it parses the (NFS, of course) header to be larger. In + * that case, it fills the header buffer and spills the rest + * into the page. + */ +- hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) & ++ hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info) & + E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT; + if (hlen > adapter->rx_ps_hdr_size) + hlen = adapter->rx_ps_hdr_size; + +- length = le16_to_cpu(rx_desc->wb.upper.length); +- cleaned = true; +- cleaned_count++; +- +- skb = buffer_info->skb; +- prefetch(skb->data - NET_IP_ALIGN); +- buffer_info->skb = NULL; +- if (!adapter->rx_ps_hdr_size) { ++ if (buffer_info->dma) { + pci_unmap_single(pdev, buffer_info->dma, +- adapter->rx_buffer_len + +- NET_IP_ALIGN, ++ adapter->rx_ps_hdr_size, + PCI_DMA_FROMDEVICE); +- skb_put(skb, length); +- goto send_up; +- } +- +- if (!skb_shinfo(skb)->nr_frags) { +- pci_unmap_single(pdev, buffer_info->dma, +- adapter->rx_ps_hdr_size + +- NET_IP_ALIGN, +- PCI_DMA_FROMDEVICE); ++ buffer_info->dma = 0; + skb_put(skb, hlen); + } + + if (length) { + pci_unmap_page(pdev, buffer_info->page_dma, +- PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); ++ PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); + buffer_info->page_dma = 0; + +- skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags++, +- buffer_info->page, +- buffer_info->page_offset, +- length); ++ skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++, ++ buffer_info->page, ++ buffer_info->page_offset, ++ length); + + if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) || + (page_count(buffer_info->page) != 1)) + buffer_info->page = NULL; + else + get_page(buffer_info->page); ++ ++ skb->len += length; ++ skb->data_len += length; ++ ++ skb->truesize += length; ++ } ++ ++ if (!(staterr & E1000_RXD_STAT_EOP)) { ++ buffer_info->skb = next_buffer->skb; ++ buffer_info->dma = next_buffer->dma; ++ next_buffer->skb = skb; ++ next_buffer->dma = 0; ++ goto next_desc; + } + send_up: +- i++; +- if (i == rx_ring->count) +- i = 0; +- next_rxd = E1000_RX_DESC_ADV(*rx_ring, i); +- prefetch(next_rxd); +- next_buffer = &rx_ring->buffer_info[i]; +- +- if (!(staterr & E1000_RXD_STAT_EOP)) { +- buffer_info->skb = xchg(&next_buffer->skb, skb); +- buffer_info->dma = xchg(&next_buffer->dma, 0); +- goto next_desc; +- } +- ++#endif /* CONFIG_IGB_DISABLE_PACKET_SPLIT */ + if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) { + dev_kfree_skb_irq(skb); + goto next_desc; +@@ -3938,17 +4215,16 @@ + /* use prefetched values */ + rx_desc = next_rxd; + buffer_info = next_buffer; +- + staterr = le32_to_cpu(rx_desc->wb.upper.status_error); + } + + rx_ring->next_to_clean = i; + cleaned_count = IGB_DESC_UNUSED(rx_ring); + +-#ifdef CONFIG_IGB_LRO ++#ifdef IGB_LRO + if (rx_ring->lro_used) { + lro_flush_all(&rx_ring->lro_mgr); +- rx_ring->lro_used = 0; ++ rx_ring->lro_used = FALSE; + } + #endif + +@@ -3964,13 +4240,12 @@ + return cleaned; + } + +- + /** + * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split + * @adapter: address of board private structure + **/ + static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, +- int cleaned_count) ++ int cleaned_count) + { + struct igb_adapter *adapter = rx_ring->adapter; + struct net_device *netdev = adapter->netdev; +@@ -3979,16 +4254,27 @@ + struct igb_buffer *buffer_info; + struct sk_buff *skb; + unsigned int i; ++ int bufsz; + + i = rx_ring->next_to_use; + buffer_info = &rx_ring->buffer_info[i]; + ++#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT ++ if (adapter->rx_ps_hdr_size) ++ bufsz = adapter->rx_ps_hdr_size; ++ else ++ bufsz = adapter->rx_buffer_len; ++#else ++ bufsz = adapter->rx_buffer_len; ++#endif /* CONFIG_IGB_DISABLE_PACKET_SPLIT */ ++ + while (cleaned_count--) { + rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); + ++#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT + if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) { + if (!buffer_info->page) { +- buffer_info->page = netdev_alloc_page(netdev); ++ buffer_info->page = alloc_page(GFP_ATOMIC); + if (!buffer_info->page) { + adapter->alloc_rx_buff_failed++; + goto no_buffers; +@@ -3998,23 +4284,15 @@ + buffer_info->page_offset ^= PAGE_SIZE / 2; + } + buffer_info->page_dma = +- pci_map_page(pdev, +- buffer_info->page, +- buffer_info->page_offset, +- PAGE_SIZE / 2, +- PCI_DMA_FROMDEVICE); +- } ++ pci_map_page(pdev, buffer_info->page, ++ buffer_info->page_offset, ++ PAGE_SIZE / 2, ++ PCI_DMA_FROMDEVICE); ++ } ++#endif /* CONFIG_IGB_DISABLE_PACKET_SPLIT */ + + if (!buffer_info->skb) { +- int bufsz; +- +- if (adapter->rx_ps_hdr_size) +- bufsz = adapter->rx_ps_hdr_size; +- else +- bufsz = adapter->rx_buffer_len; +- bufsz += NET_IP_ALIGN; +- skb = netdev_alloc_skb(netdev, bufsz); +- ++ skb = netdev_alloc_skb(netdev, bufsz + NET_IP_ALIGN); + if (!skb) { + adapter->alloc_rx_buff_failed++; + goto no_buffers; +@@ -4028,17 +4306,20 @@ + + buffer_info->skb = skb; + buffer_info->dma = pci_map_single(pdev, skb->data, +- bufsz, +- PCI_DMA_FROMDEVICE); +- ++ bufsz, ++ PCI_DMA_FROMDEVICE); + } + /* Refresh the desc even if buffer_addrs didn't change because + * each write-back erases this info. */ ++#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT + if (adapter->rx_ps_hdr_size) { + rx_desc->read.pkt_addr = + cpu_to_le64(buffer_info->page_dma); + rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma); + } else { ++#else ++ { ++#endif /* CONFIG_IGB_DISABLE_PACKET_SPLIT */ + rx_desc->read.pkt_addr = + cpu_to_le64(buffer_info->dma); + rx_desc->read.hdr_addr = 0; +@@ -4067,6 +4348,7 @@ + } + } + ++#ifdef SIOCGMIIPHY + /** + * igb_mii_ioctl - + * @netdev: +@@ -4088,18 +4370,18 @@ + case SIOCGMIIREG: + if (!capable(CAP_NET_ADMIN)) + return -EPERM; +- if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw, +- data->reg_num +- & 0x1F, &data->val_out)) ++ if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, ++ &data->val_out)) + return -EIO; + break; + case SIOCSMIIREG: + default: + return -EOPNOTSUPP; + } +- return 0; +-} +- ++ return E1000_SUCCESS; ++} ++ ++#endif + /** + * igb_ioctl - + * @netdev: +@@ -4109,17 +4391,51 @@ + static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) + { + switch (cmd) { ++#ifdef SIOCGMIIPHY + case SIOCGMIIPHY: + case SIOCGMIIREG: + case SIOCSMIIREG: + return igb_mii_ioctl(netdev, ifr, cmd); ++#endif ++#ifdef ETHTOOL_OPS_COMPAT ++ case SIOCETHTOOL: ++ return ethtool_ioctl(ifr); ++#endif + default: + return -EOPNOTSUPP; + } + } + ++s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) ++{ ++ struct igb_adapter *adapter = hw->back; ++ u16 cap_offset; ++ ++ cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); ++ if (!cap_offset) ++ return -E1000_ERR_CONFIG; ++ ++ pci_read_config_word(adapter->pdev, cap_offset + reg, value); ++ ++ return E1000_SUCCESS; ++} ++ ++s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) ++{ ++ struct igb_adapter *adapter = hw->back; ++ u16 cap_offset; ++ ++ cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); ++ if (!cap_offset) ++ return -E1000_ERR_CONFIG; ++ ++ pci_write_config_word(adapter->pdev, cap_offset + reg, *value); ++ ++ return E1000_SUCCESS; ++} ++ + static void igb_vlan_rx_register(struct net_device *netdev, +- struct vlan_group *grp) ++ struct vlan_group *grp) + { + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +@@ -4130,30 +4446,28 @@ + + if (grp) { + /* enable VLAN tag insert/strip */ +- ctrl = rd32(E1000_CTRL); ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= E1000_CTRL_VME; +- wr32(E1000_CTRL, ctrl); +- +- /* enable VLAN receive filtering */ +- rctl = rd32(E1000_RCTL); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); ++ ++ /* Disable CFI check */ ++ rctl = E1000_READ_REG(hw, E1000_RCTL); + rctl &= ~E1000_RCTL_CFIEN; +- wr32(E1000_RCTL, rctl); ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); + igb_update_mng_vlan(adapter); +- wr32(E1000_RLPML, +- adapter->max_frame_size + VLAN_TAG_SIZE); + } else { + /* disable VLAN tag insert/strip */ +- ctrl = rd32(E1000_CTRL); ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl &= ~E1000_CTRL_VME; +- wr32(E1000_CTRL, ctrl); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) { + igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); + adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; + } +- wr32(E1000_RLPML, +- adapter->max_frame_size); +- } ++ } ++ ++ igb_set_rlpml(adapter); + + if (!test_bit(__IGB_DOWN, &adapter->state)) + igb_irq_enable(adapter); +@@ -4164,16 +4478,27 @@ + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; + u32 vfta, index; +- +- if ((adapter->hw.mng_cookie.status & ++#ifndef HAVE_NETDEV_VLAN_FEATURES ++ struct net_device *v_netdev; ++#endif ++ ++ if ((hw->mng_cookie.status & + E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && + (vid == adapter->mng_vlan_id)) + return; + /* add VID to filter table */ + index = (vid >> 5) & 0x7F; +- vfta = array_rd32(E1000_VFTA, index); ++ vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); + vfta |= (1 << (vid & 0x1F)); +- igb_write_vfta(&adapter->hw, index, vfta); ++ e1000_write_vfta(hw, index, vfta); ++#ifndef HAVE_NETDEV_VLAN_FEATURES ++ /* Copy feature flags from netdev to the vlan netdev for this vid. ++ * This allows things like TSO to bubble down to our vlan device. ++ */ ++ v_netdev = vlan_group_get_device(adapter->vlgrp, vid); ++ v_netdev->features |= adapter->netdev->features; ++ vlan_group_set_device(adapter->vlgrp, vid, v_netdev); ++#endif + } + + static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) +@@ -4198,9 +4523,9 @@ + + /* remove VID from filter table */ + index = (vid >> 5) & 0x7F; +- vfta = array_rd32(E1000_VFTA, index); ++ vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); + vfta &= ~(1 << (vid & 0x1F)); +- igb_write_vfta(&adapter->hw, index, vfta); ++ e1000_write_vfta(hw, index, vfta); + } + + static void igb_restore_vlan(struct igb_adapter *adapter) +@@ -4223,14 +4548,6 @@ + + mac->autoneg = 0; + +- /* Fiber NICs only allow 1000 gbps Full duplex */ +- if ((adapter->hw.phy.media_type == e1000_media_type_fiber) && +- spddplx != (SPEED_1000 + DUPLEX_FULL)) { +- dev_err(&adapter->pdev->dev, +- "Unsupported Speed/Duplex configuration\n"); +- return -EINVAL; +- } +- + switch (spddplx) { + case SPEED_10 + DUPLEX_HALF: + mac->forced_speed_duplex = ADVERTISE_10_HALF; +@@ -4250,14 +4567,32 @@ + break; + case SPEED_1000 + DUPLEX_HALF: /* not supported */ + default: +- dev_err(&adapter->pdev->dev, +- "Unsupported Speed/Duplex configuration\n"); ++ DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n"); + return -EINVAL; + } + return 0; + } + +- ++#ifdef USE_REBOOT_NOTIFIER ++/* only want to do this for 2.4 kernels? */ ++static int igb_notify_reboot(struct notifier_block *nb, unsigned long event, ++ void *p) ++{ ++ struct pci_dev *pdev = NULL; ++ ++ switch (event) { ++ case SYS_DOWN: ++ case SYS_HALT: ++ case SYS_POWER_OFF: ++ while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev))) { ++ if (pci_dev_driver(pdev) == &igb_driver) ++ igb_suspend(pdev, PMSG_SUSPEND); ++ } ++ } ++ return NOTIFY_DONE; ++} ++ ++#endif + static int igb_suspend(struct pci_dev *pdev, pm_message_t state) + { + struct net_device *netdev = pci_get_drvdata(pdev); +@@ -4284,7 +4619,7 @@ + return retval; + #endif + +- status = rd32(E1000_STATUS); ++ status = E1000_READ_REG(hw, E1000_STATUS); + if (status & E1000_STATUS_LU) + wufc &= ~E1000_WUFC_LNKC; + +@@ -4294,27 +4629,25 @@ + + /* turn on all-multi mode if wake on multicast is enabled */ + if (wufc & E1000_WUFC_MC) { +- rctl = rd32(E1000_RCTL); ++ rctl = E1000_READ_REG(hw, E1000_RCTL); + rctl |= E1000_RCTL_MPE; +- wr32(E1000_RCTL, rctl); +- } +- +- ctrl = rd32(E1000_CTRL); +- /* advertise wake from D3Cold */ +- #define E1000_CTRL_ADVD3WUC 0x00100000 ++ E1000_WRITE_REG(hw, E1000_RCTL, rctl); ++ } ++ ++ ctrl = E1000_READ_REG(hw, E1000_CTRL); + /* phy power management enable */ + #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 + ctrl |= E1000_CTRL_ADVD3WUC; +- wr32(E1000_CTRL, ctrl); ++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + /* Allow time for pending master requests to run */ +- igb_disable_pcie_master(&adapter->hw); +- +- wr32(E1000_WUC, E1000_WUC_PME_EN); +- wr32(E1000_WUFC, wufc); +- } else { +- wr32(E1000_WUC, 0); +- wr32(E1000_WUFC, 0); ++ e1000_disable_pcie_master(hw); ++ ++ E1000_WRITE_REG(hw, E1000_WUC, E1000_WUC_PME_EN); ++ E1000_WRITE_REG(hw, E1000_WUFC, wufc); ++ } else { ++ E1000_WRITE_REG(hw, E1000_WUC, 0); ++ E1000_WRITE_REG(hw, E1000_WUFC, 0); + } + + /* make sure adapter isn't asleep if manageability/wol is enabled */ +@@ -4322,7 +4655,7 @@ + pci_enable_wake(pdev, PCI_D3hot, 1); + pci_enable_wake(pdev, PCI_D3cold, 1); + } else { +- igb_shutdown_fiber_serdes_link_82575(hw); ++ e1000_shutdown_fiber_serdes_link(hw); + pci_enable_wake(pdev, PCI_D3hot, 0); + pci_enable_wake(pdev, PCI_D3cold, 0); + } +@@ -4348,14 +4681,10 @@ + + pci_set_power_state(pdev, PCI_D0); + pci_restore_state(pdev); +- +- if (adapter->need_ioport) +- err = pci_enable_device(pdev); +- else +- err = pci_enable_device_mem(pdev); ++ err = pci_enable_device_mem(pdev); + if (err) { +- dev_err(&pdev->dev, +- "igb: Cannot enable PCI device from suspend\n"); ++ dev_err(&pdev->dev, "igb: Cannot enable PCI device " ++ "from suspend\n"); + return err; + } + pci_set_master(pdev); +@@ -4366,14 +4695,19 @@ + igb_set_interrupt_capability(adapter); + + if (igb_alloc_queues(adapter)) { +- dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); ++ DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); + return -ENOMEM; + } + + /* e1000_power_up_phy(adapter); */ + + igb_reset(adapter); +- wr32(E1000_WUS, ~0); ++ ++ /* let the f/w know that the h/w is now under the control of the ++ * driver. */ ++ igb_get_hw_control(adapter); ++ ++ E1000_WRITE_REG(hw, E1000_WUS, ~0); + + if (netif_running(netdev)) { + err = igb_open(netdev); +@@ -4383,19 +4717,17 @@ + + netif_device_attach(netdev); + +- /* let the f/w know that the h/w is now under the control of the +- * driver. */ +- igb_get_hw_control(adapter); +- +- return 0; +-} +-#endif +- ++ return 0; ++} ++#endif ++ ++#ifndef USE_REBOOT_NOTIFIER + static void igb_shutdown(struct pci_dev *pdev) + { + igb_suspend(pdev, PMSG_SUSPEND); + } + ++#endif + #ifdef CONFIG_NET_POLL_CONTROLLER + /* + * Polling 'interrupt' - used by things like netconsole to send skbs +@@ -4405,25 +4737,33 @@ + static void igb_netpoll(struct net_device *netdev) + { + struct igb_adapter *adapter = netdev_priv(netdev); +- int i; +- int work_done = 0; +- +- igb_irq_disable(adapter); +- adapter->flags |= IGB_FLAG_IN_NETPOLL; +- +- for (i = 0; i < adapter->num_tx_queues; i++) +- igb_clean_tx_irq(&adapter->tx_ring[i]); +- +- for (i = 0; i < adapter->num_rx_queues; i++) +- igb_clean_rx_irq_adv(&adapter->rx_ring[i], +- &work_done, +- adapter->rx_ring[i].napi.weight); +- +- adapter->flags &= ~IGB_FLAG_IN_NETPOLL; +- igb_irq_enable(adapter); ++ struct e1000_hw *hw = &adapter->hw; ++ int i; ++ ++ if (!adapter->msix_entries) { ++ igb_irq_disable(adapter); ++ napi_schedule(&adapter->rx_ring[0].napi); ++ return; ++ } ++ ++#ifdef CONFIG_IGB_SEPARATE_TX_HANDLER ++ for (i = 0; i < adapter->num_tx_queues; i++) { ++ struct igb_ring *tx_ring = &adapter->tx_ring[i]; ++ E1000_WRITE_REG(hw, E1000_EIMC, tx_ring->eims_value); ++ igb_clean_tx_irq(tx_ring); ++ E1000_WRITE_REG(hw, E1000_EIMS, tx_ring->eims_value); ++ } ++ ++#endif /* CONFIG_IGB_SEPARATE_TX_HANDLER */ ++ for (i = 0; i < adapter->num_rx_queues; i++) { ++ struct igb_ring *rx_ring = &adapter->rx_ring[i]; ++ E1000_WRITE_REG(hw, E1000_EIMC, rx_ring->eims_value); ++ napi_schedule(&rx_ring->napi); ++ } + } + #endif /* CONFIG_NET_POLL_CONTROLLER */ + ++#ifdef HAVE_PCI_ERS + /** + * igb_io_error_detected - called when PCI error is detected + * @pdev: Pointer to PCI device +@@ -4433,7 +4773,7 @@ + * this device has been detected. + */ + static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, +- pci_channel_state_t state) ++ pci_channel_state_t state) + { + struct net_device *netdev = pci_get_drvdata(pdev); + struct igb_adapter *adapter = netdev_priv(netdev); +@@ -4460,27 +4800,27 @@ + struct net_device *netdev = pci_get_drvdata(pdev); + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; +- int err; +- +- if (adapter->need_ioport) +- err = pci_enable_device(pdev); +- else +- err = pci_enable_device_mem(pdev); +- if (err) { ++ pci_ers_result_t result; ++ ++ if (pci_enable_device_mem(pdev)) { + dev_err(&pdev->dev, + "Cannot re-enable PCI device after reset.\n"); +- return PCI_ERS_RESULT_DISCONNECT; +- } +- pci_set_master(pdev); +- pci_restore_state(pdev); +- +- pci_enable_wake(pdev, PCI_D3hot, 0); +- pci_enable_wake(pdev, PCI_D3cold, 0); +- +- igb_reset(adapter); +- wr32(E1000_WUS, ~0); +- +- return PCI_ERS_RESULT_RECOVERED; ++ result = PCI_ERS_RESULT_DISCONNECT; ++ } else { ++ pci_set_master(pdev); ++ pci_restore_state(pdev); ++ ++ pci_enable_wake(pdev, PCI_D3hot, 0); ++ pci_enable_wake(pdev, PCI_D3cold, 0); ++ ++ igb_reset(adapter); ++ E1000_WRITE_REG(hw, E1000_WUS, ~0); ++ result = PCI_ERS_RESULT_RECOVERED; ++ } ++ ++ pci_cleanup_aer_uncorrect_error_status(pdev); ++ ++ return result; + } + + /** +@@ -4508,7 +4848,7 @@ + /* let the f/w know that the h/w is now under the control of the + * driver. */ + igb_get_hw_control(adapter); +- +-} +- ++} ++ ++#endif /* HAVE_PCI_ERS */ + /* igb_main.c */ +diff -r 4f0f8bc35440 drivers/net/igb/igb_param.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/igb/igb_param.c Wed Aug 05 11:03:37 2009 +0100 +@@ -0,0 +1,408 @@ ++/******************************************************************************* ++ ++ Intel(R) Gigabit Ethernet Linux driver ++ Copyright(c) 2007-2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++ ++#include ++ ++#include "igb.h" ++ ++/* This is the only thing that needs to be changed to adjust the ++ * maximum number of ports that the driver can manage. ++ */ ++ ++#define IGB_MAX_NIC 32 ++ ++#define OPTION_UNSET -1 ++#define OPTION_DISABLED 0 ++#define OPTION_ENABLED 1 ++ ++/* All parameters are treated the same, as an integer array of values. ++ * This macro just reduces the need to repeat the same declaration code ++ * over and over (plus this helps to avoid typo bugs). ++ */ ++ ++#define IGB_PARAM_INIT { [0 ... IGB_MAX_NIC] = OPTION_UNSET } ++#ifndef module_param_array ++/* Module Parameters are always initialized to -1, so that the driver ++ * can tell the difference between no user specified value or the ++ * user asking for the default value. ++ * The true default values are loaded in when igb_check_options is called. ++ * ++ * This is a GCC extension to ANSI C. ++ * See the item "Labeled Elements in Initializers" in the section ++ * "Extensions to the C Language Family" of the GCC documentation. ++ */ ++ ++#define IGB_PARAM(X, desc) \ ++ static const int __devinitdata X[IGB_MAX_NIC+1] = IGB_PARAM_INIT; \ ++ MODULE_PARM(X, "1-" __MODULE_STRING(IGB_MAX_NIC) "i"); \ ++ MODULE_PARM_DESC(X, desc); ++#else ++#define IGB_PARAM(X, desc) \ ++ static int __devinitdata X[IGB_MAX_NIC+1] = IGB_PARAM_INIT; \ ++ static unsigned int num_##X; \ ++ module_param_array_named(X, X, int, &num_##X, 0); \ ++ MODULE_PARM_DESC(X, desc); ++#endif ++ ++/* Interrupt Throttle Rate (interrupts/sec) ++ * ++ * Valid Range: 100-100000 (0=off, 1=dynamic, 3=dynamic conservative) ++ */ ++IGB_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate"); ++#define DEFAULT_ITR 3 ++#define MAX_ITR 100000 ++#define MIN_ITR 120 ++/* IntMode (Interrupt Mode) ++ * ++ * Valid Range: 0 - 3 ++ * ++ * Default Value: 2 (MSI-X single queue) ++ */ ++IGB_PARAM(IntMode, "Interrupt Mode"); ++#define MAX_INTMODE 3 ++#define MIN_INTMODE 0 ++ ++/* LLIPort (Low Latency Interrupt TCP Port) ++ * ++ * Valid Range: 0 - 65535 ++ * ++ * Default Value: 0 (disabled) ++ */ ++IGB_PARAM(LLIPort, "Low Latency Interrupt TCP Port"); ++ ++#define DEFAULT_LLIPORT 0 ++#define MAX_LLIPORT 0xFFFF ++#define MIN_LLIPORT 0 ++ ++/* LLIPush (Low Latency Interrupt on TCP Push flag) ++ * ++ * Valid Range: 0, 1 ++ * ++ * Default Value: 0 (disabled) ++ */ ++IGB_PARAM(LLIPush, "Low Latency Interrupt on TCP Push flag"); ++ ++#define DEFAULT_LLIPUSH 0 ++#define MAX_LLIPUSH 1 ++#define MIN_LLIPUSH 0 ++ ++/* LLISize (Low Latency Interrupt on Packet Size) ++ * ++ * Valid Range: 0 - 1500 ++ * ++ * Default Value: 0 (disabled) ++ */ ++IGB_PARAM(LLISize, "Low Latency Interrupt on Packet Size"); ++ ++#define DEFAULT_LLISIZE 0 ++#define MAX_LLISIZE 1500 ++#define MIN_LLISIZE 0 ++ ++#ifdef IGB_LRO ++/* LROAggr (Large Receive Offload) ++ * ++ * Valid Range: 2 - 44 ++ * ++ * Default Value: 32 ++ */ ++IGB_PARAM(LROAggr, "LRO - Maximum packets to aggregate"); ++ ++#define DEFAULT_LRO_AGGR 32 ++#define MAX_LRO_AGGR 44 ++#define MIN_LRO_AGGR 2 ++#endif ++ ++struct igb_option { ++ enum { enable_option, range_option, list_option } type; ++ const char *name; ++ const char *err; ++ int def; ++ union { ++ struct { /* range_option info */ ++ int min; ++ int max; ++ } r; ++ struct { /* list_option info */ ++ int nr; ++ struct igb_opt_list { int i; char *str; } *p; ++ } l; ++ } arg; ++}; ++ ++static int __devinit igb_validate_option(unsigned int *value, ++ struct igb_option *opt, ++ struct igb_adapter *adapter) ++{ ++ if (*value == OPTION_UNSET) { ++ *value = opt->def; ++ return 0; ++ } ++ ++ switch (opt->type) { ++ case enable_option: ++ switch (*value) { ++ case OPTION_ENABLED: ++ DPRINTK(PROBE, INFO, "%s Enabled\n", opt->name); ++ return 0; ++ case OPTION_DISABLED: ++ DPRINTK(PROBE, INFO, "%s Disabled\n", opt->name); ++ return 0; ++ } ++ break; ++ case range_option: ++ if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { ++ DPRINTK(PROBE, INFO, ++ "%s set to %d\n", opt->name, *value); ++ return 0; ++ } ++ break; ++ case list_option: { ++ int i; ++ struct igb_opt_list *ent; ++ ++ for (i = 0; i < opt->arg.l.nr; i++) { ++ ent = &opt->arg.l.p[i]; ++ if (*value == ent->i) { ++ if (ent->str[0] != '\0') ++ DPRINTK(PROBE, INFO, "%s\n", ent->str); ++ return 0; ++ } ++ } ++ } ++ break; ++ default: ++ BUG(); ++ } ++ ++ DPRINTK(PROBE, INFO, "Invalid %s value specified (%d) %s\n", ++ opt->name, *value, opt->err); ++ *value = opt->def; ++ return -1; ++} ++ ++/** ++ * igb_check_options - Range Checking for Command Line Parameters ++ * @adapter: board private structure ++ * ++ * This routine checks all command line parameters for valid user ++ * input. If an invalid value is given, or if no user specified ++ * value exists, a default value is used. The final value is stored ++ * in a variable in the adapter structure. ++ **/ ++ ++void __devinit igb_check_options(struct igb_adapter *adapter) ++{ ++ int bd = adapter->bd_number; ++ ++ if (bd >= IGB_MAX_NIC) { ++ DPRINTK(PROBE, NOTICE, ++ "Warning: no configuration for board #%d\n", bd); ++ DPRINTK(PROBE, NOTICE, "Using defaults for all values\n"); ++#ifndef module_param_array ++ bd = IGB_MAX_NIC; ++#endif ++ } ++ ++ { /* Interrupt Throttling Rate */ ++ struct igb_option opt = { ++ .type = range_option, ++ .name = "Interrupt Throttling Rate (ints/sec)", ++ .err = "using default of " __MODULE_STRING(DEFAULT_ITR), ++ .def = DEFAULT_ITR, ++ .arg = { .r = { .min = MIN_ITR, ++ .max = MAX_ITR } } ++ }; ++ ++#ifdef module_param_array ++ if (num_InterruptThrottleRate > bd) { ++#endif ++ adapter->itr = InterruptThrottleRate[bd]; ++ switch (adapter->itr) { ++ case 0: ++ DPRINTK(PROBE, INFO, "%s turned off\n", ++ opt.name); ++ break; ++ case 1: ++ DPRINTK(PROBE, INFO, "%s set to dynamic mode\n", ++ opt.name); ++ adapter->itr_setting = adapter->itr; ++ adapter->itr = IGB_START_ITR; ++ break; ++ case 3: ++ DPRINTK(PROBE, INFO, ++ "%s set to dynamic conservative mode\n", ++ opt.name); ++ adapter->itr_setting = adapter->itr; ++ adapter->itr = IGB_START_ITR; ++ break; ++ default: ++ igb_validate_option(&adapter->itr, &opt, ++ adapter); ++ /* Save the setting, because the dynamic bits ++ * change itr. In case of invalid user value, ++ * default to conservative mode, else need to ++ * clear the lower two bits because they are ++ * used as control */ ++ if (adapter->itr == 3) { ++ adapter->itr_setting = adapter->itr; ++ adapter->itr = IGB_START_ITR; ++ } else { ++ adapter->itr = 1000000000 / (adapter->itr * 256); ++ adapter->itr_setting = adapter->itr & ~3; ++ } ++ break; ++ } ++#ifdef module_param_array ++ } else { ++ adapter->itr_setting = opt.def; ++ adapter->itr = 8000; ++ } ++#endif ++ } ++ { /* Interrupt Mode */ ++ struct igb_option opt = { ++ .type = range_option, ++ .name = "Interrupt Mode", ++ .err = "defaulting to 2 (MSI-X single queue)", ++ .def = IGB_INT_MODE_MSIX_1Q, ++ .arg = { .r = { .min = MIN_INTMODE, ++ .max = MAX_INTMODE } } ++ }; ++ ++#ifdef module_param_array ++ if (num_IntMode > bd) { ++#endif ++ unsigned int int_mode = IntMode[bd]; ++ igb_validate_option(&int_mode, &opt, adapter); ++ adapter->int_mode = int_mode; ++#ifdef module_param_array ++ } else { ++ adapter->int_mode = opt.def; ++ } ++#endif ++ } ++ { /* Low Latency Interrupt TCP Port */ ++ struct igb_option opt = { ++ .type = range_option, ++ .name = "Low Latency Interrupt TCP Port", ++ .err = "using default of " __MODULE_STRING(DEFAULT_LLIPORT), ++ .def = DEFAULT_LLIPORT, ++ .arg = { .r = { .min = MIN_LLIPORT, ++ .max = MAX_LLIPORT } } ++ }; ++ ++#ifdef module_param_array ++ if (num_LLIPort > bd) { ++#endif ++ adapter->lli_port = LLIPort[bd]; ++ if (adapter->lli_port) { ++ igb_validate_option(&adapter->lli_port, &opt, ++ adapter); ++ } else { ++ DPRINTK(PROBE, INFO, "%s turned off\n", ++ opt.name); ++ } ++#ifdef module_param_array ++ } else { ++ adapter->lli_port = opt.def; ++ } ++#endif ++ } ++ { /* Low Latency Interrupt on Packet Size */ ++ struct igb_option opt = { ++ .type = range_option, ++ .name = "Low Latency Interrupt on Packet Size", ++ .err = "using default of " __MODULE_STRING(DEFAULT_LLISIZE), ++ .def = DEFAULT_LLISIZE, ++ .arg = { .r = { .min = MIN_LLISIZE, ++ .max = MAX_LLISIZE } } ++ }; ++ ++#ifdef module_param_array ++ if (num_LLISize > bd) { ++#endif ++ adapter->lli_size = LLISize[bd]; ++ if (adapter->lli_size) { ++ igb_validate_option(&adapter->lli_size, &opt, ++ adapter); ++ } else { ++ DPRINTK(PROBE, INFO, "%s turned off\n", ++ opt.name); ++ } ++#ifdef module_param_array ++ } else { ++ adapter->lli_size = opt.def; ++ } ++#endif ++ } ++ { /* Low Latency Interrupt on TCP Push flag */ ++ struct igb_option opt = { ++ .type = enable_option, ++ .name = "Low Latency Interrupt on TCP Push flag", ++ .err = "defaulting to Disabled", ++ .def = OPTION_DISABLED ++ }; ++ ++#ifdef module_param_array ++ if (num_LLIPush > bd) { ++#endif ++ unsigned int lli_push = LLIPush[bd]; ++ igb_validate_option(&lli_push, &opt, adapter); ++ adapter->flags |= lli_push ? IGB_FLAG_LLI_PUSH : 0; ++#ifdef module_param_array ++ } else { ++ adapter->flags |= opt.def ? IGB_FLAG_LLI_PUSH : 0; ++ } ++#endif ++ } ++#ifdef IGB_LRO ++ { /* Large Receive Offload - Maximum packets to aggregate */ ++ struct igb_option opt = { ++ .type = range_option, ++ .name = "LRO - Maximum packets to aggregate", ++ .err = "using default of " __MODULE_STRING(DEFAULT_LRO_AGGR), ++ .def = DEFAULT_LRO_AGGR, ++ .arg = { .r = { .min = MIN_LRO_AGGR, ++ .max = MAX_LRO_AGGR } } ++ }; ++ ++#ifdef module_param_array ++ if (num_LROAggr > bd) { ++#endif ++ adapter->lro_max_aggr = LROAggr[bd]; ++ igb_validate_option(&adapter->lro_max_aggr, &opt, adapter); ++ ++#ifdef module_param_array ++ } else { ++ adapter->lro_max_aggr = opt.def; ++ } ++#endif ++ } ++#endif /* IGB_LRO */ ++} ++ +diff -r 4f0f8bc35440 drivers/net/igb/igb_regtest.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/igb/igb_regtest.h Wed Aug 05 11:03:37 2009 +0100 +@@ -0,0 +1,135 @@ ++/******************************************************************************* ++ ++ Intel(R) Gigabit Ethernet Linux driver ++ Copyright(c) 2007-2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ethtool register test data */ ++struct igb_reg_test { ++ u16 reg; ++ u16 reg_offset; ++ u16 array_len; ++ u16 test_type; ++ u32 mask; ++ u32 write; ++}; ++ ++/* In the hardware, registers are laid out either singly, in arrays ++ * spaced 0x100 bytes apart, or in contiguous tables. We assume ++ * most tests take place on arrays or single registers (handled ++ * as a single-element array) and special-case the tables. ++ * Table tests are always pattern tests. ++ * ++ * We also make provision for some required setup steps by specifying ++ * registers to be written without any read-back testing. ++ */ ++ ++#define PATTERN_TEST 1 ++#define SET_READ_TEST 2 ++#define WRITE_NO_TEST 3 ++#define TABLE32_TEST 4 ++#define TABLE64_TEST_LO 5 ++#define TABLE64_TEST_HI 6 ++ ++/* 82576 reg test */ ++static struct igb_reg_test reg_test_82576[] = { ++ { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, ++ { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, ++ { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, ++ { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, ++ { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, ++ { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, ++ /* Enable all queues before testing. */ ++ { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, ++ { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, ++ /* RDH is read-only for 82576, only test RDT. */ ++ { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, ++ { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, ++ { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, ++ { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, ++ { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, ++ { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, ++ { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, ++ { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, ++ { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, ++ { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, ++ { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, ++ { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, ++ { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, ++ { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, ++ { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, ++ { E1000_RA, 0, 16, TABLE64_TEST_LO, ++ 0xFFFFFFFF, 0xFFFFFFFF }, ++ { E1000_RA, 0, 16, TABLE64_TEST_HI, ++ 0x83FFFFFF, 0xFFFFFFFF }, ++ { E1000_RA2, 0, 8, TABLE64_TEST_LO, ++ 0xFFFFFFFF, 0xFFFFFFFF }, ++ { E1000_RA2, 0, 8, TABLE64_TEST_HI, ++ 0x83FFFFFF, 0xFFFFFFFF }, ++ { E1000_MTA, 0, 128, TABLE32_TEST, ++ 0xFFFFFFFF, 0xFFFFFFFF }, ++ { 0, 0, 0, 0 } ++}; ++ ++/* 82575 register test */ ++static struct igb_reg_test reg_test_82575[] = { ++ { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, ++ { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, ++ { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, ++ { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, ++ /* Enable all four RX queues before testing. */ ++ { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, ++ /* RDH is read-only for 82575, only test RDT. */ ++ { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, ++ { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, ++ { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, ++ { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, ++ { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, ++ { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, ++ { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, ++ { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, ++ { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, ++ { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, ++ { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, ++ { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, ++ { E1000_RA, 0, 16, TABLE64_TEST_LO, ++ 0xFFFFFFFF, 0xFFFFFFFF }, ++ { E1000_RA, 0, 16, TABLE64_TEST_HI, ++ 0x800FFFFF, 0xFFFFFFFF }, ++ { E1000_MTA, 0, 128, TABLE32_TEST, ++ 0xFFFFFFFF, 0xFFFFFFFF }, ++ { 0, 0, 0, 0 } ++}; ++ ++ +diff -r 4f0f8bc35440 drivers/net/igb/kcompat.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/igb/kcompat.c Wed Aug 05 11:03:37 2009 +0100 +@@ -0,0 +1,559 @@ ++/******************************************************************************* ++ ++ Intel(R) Gigabit Ethernet Linux driver ++ Copyright(c) 2007-2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "igb.h" ++#include "kcompat.h" ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,21) ) ++struct sk_buff * ++_kc_skb_pad(struct sk_buff *skb, int pad) ++{ ++ struct sk_buff *nskb; ++ ++ /* If the skbuff is non linear tailroom is always zero.. */ ++ if(skb_tailroom(skb) >= pad) ++ { ++ memset(skb->data+skb->len, 0, pad); ++ return skb; ++ } ++ ++ nskb = skb_copy_expand(skb, skb_headroom(skb), skb_tailroom(skb) + pad, GFP_ATOMIC); ++ kfree_skb(skb); ++ if(nskb) ++ memset(nskb->data+nskb->len, 0, pad); ++ return nskb; ++} ++#endif /* < 2.4.21 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) ) ++ ++/**************************************/ ++/* PCI DMA MAPPING */ ++ ++#if defined(CONFIG_HIGHMEM) ++ ++#ifndef PCI_DRAM_OFFSET ++#define PCI_DRAM_OFFSET 0 ++#endif ++ ++u64 ++_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, ++ size_t size, int direction) ++{ ++ return (((u64) (page - mem_map) << PAGE_SHIFT) + offset + ++ PCI_DRAM_OFFSET); ++} ++ ++#else /* CONFIG_HIGHMEM */ ++ ++u64 ++_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, ++ size_t size, int direction) ++{ ++ return pci_map_single(dev, (void *)page_address(page) + offset, size, ++ direction); ++} ++ ++#endif /* CONFIG_HIGHMEM */ ++ ++void ++_kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, ++ int direction) ++{ ++ return pci_unmap_single(dev, dma_addr, size, direction); ++} ++ ++#endif /* 2.4.13 => 2.4.3 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) ) ++ ++/**************************************/ ++/* PCI DRIVER API */ ++ ++int ++_kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask) ++{ ++ if (!pci_dma_supported(dev, mask)) ++ return -EIO; ++ dev->dma_mask = mask; ++ return 0; ++} ++ ++int ++_kc_pci_request_regions(struct pci_dev *dev, char *res_name) ++{ ++ int i; ++ ++ for (i = 0; i < 6; i++) { ++ if (pci_resource_len(dev, i) == 0) ++ continue; ++ ++ if (pci_resource_flags(dev, i) & IORESOURCE_IO) { ++ if (!request_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) { ++ pci_release_regions(dev); ++ return -EBUSY; ++ } ++ } else if (pci_resource_flags(dev, i) & IORESOURCE_MEM) { ++ if (!request_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) { ++ pci_release_regions(dev); ++ return -EBUSY; ++ } ++ } ++ } ++ return 0; ++} ++ ++void ++_kc_pci_release_regions(struct pci_dev *dev) ++{ ++ int i; ++ ++ for (i = 0; i < 6; i++) { ++ if (pci_resource_len(dev, i) == 0) ++ continue; ++ ++ if (pci_resource_flags(dev, i) & IORESOURCE_IO) ++ release_region(pci_resource_start(dev, i), pci_resource_len(dev, i)); ++ ++ else if (pci_resource_flags(dev, i) & IORESOURCE_MEM) ++ release_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i)); ++ } ++} ++ ++/**************************************/ ++/* NETWORK DRIVER API */ ++ ++struct net_device * ++_kc_alloc_etherdev(int sizeof_priv) ++{ ++ struct net_device *dev; ++ int alloc_size; ++ ++ alloc_size = sizeof(*dev) + sizeof_priv + IFNAMSIZ + 31; ++ dev = kmalloc(alloc_size, GFP_KERNEL); ++ if (!dev) ++ return NULL; ++ memset(dev, 0, alloc_size); ++ ++ if (sizeof_priv) ++ dev->priv = (void *) (((unsigned long)(dev + 1) + 31) & ~31); ++ dev->name[0] = '\0'; ++ ether_setup(dev); ++ ++ return dev; ++} ++ ++int ++_kc_is_valid_ether_addr(u8 *addr) ++{ ++ const char zaddr[6] = { 0, }; ++ ++ return !(addr[0] & 1) && memcmp(addr, zaddr, 6); ++} ++ ++#endif /* 2.4.3 => 2.4.0 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) ) ++ ++int ++_kc_pci_set_power_state(struct pci_dev *dev, int state) ++{ ++ return 0; ++} ++ ++int ++_kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable) ++{ ++ return 0; ++} ++ ++#endif /* 2.4.6 => 2.4.3 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) ++void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, ++ int off, int size) ++{ ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ frag->page = page; ++ frag->page_offset = off; ++ frag->size = size; ++ skb_shinfo(skb)->nr_frags = i + 1; ++} ++ ++/* ++ * Original Copyright: ++ * find_next_bit.c: fallback find next bit implementation ++ * ++ * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. ++ * Written by David Howells (dhowells@redhat.com) ++ */ ++ ++/** ++ * find_next_bit - find the next set bit in a memory region ++ * @addr: The address to base the search on ++ * @offset: The bitnumber to start searching at ++ * @size: The maximum size to search ++ */ ++unsigned long find_next_bit(const unsigned long *addr, unsigned long size, ++ unsigned long offset) ++{ ++ const unsigned long *p = addr + BITOP_WORD(offset); ++ unsigned long result = offset & ~(BITS_PER_LONG-1); ++ unsigned long tmp; ++ ++ if (offset >= size) ++ return size; ++ size -= result; ++ offset %= BITS_PER_LONG; ++ if (offset) { ++ tmp = *(p++); ++ tmp &= (~0UL << offset); ++ if (size < BITS_PER_LONG) ++ goto found_first; ++ if (tmp) ++ goto found_middle; ++ size -= BITS_PER_LONG; ++ result += BITS_PER_LONG; ++ } ++ while (size & ~(BITS_PER_LONG-1)) { ++ if ((tmp = *(p++))) ++ goto found_middle; ++ result += BITS_PER_LONG; ++ size -= BITS_PER_LONG; ++ } ++ if (!size) ++ return result; ++ tmp = *p; ++ ++found_first: ++ tmp &= (~0UL >> (BITS_PER_LONG - size)); ++ if (tmp == 0UL) /* Are any bits set? */ ++ return result + size; /* Nope. */ ++found_middle: ++ return result + ffs(tmp); ++} ++ ++#endif /* 2.6.0 => 2.4.6 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) ) ++void *_kc_kzalloc(size_t size, int flags) ++{ ++ void *ret = kmalloc(size, flags); ++ if (ret) ++ memset(ret, 0, size); ++ return ret; ++} ++#endif /* <= 2.6.13 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ) ++struct sk_buff *_kc_netdev_alloc_skb(struct net_device *dev, ++ unsigned int length) ++{ ++ /* 16 == NET_PAD_SKB */ ++ struct sk_buff *skb; ++ skb = alloc_skb(length + 16, GFP_ATOMIC); ++ if (likely(skb != NULL)) { ++ skb_reserve(skb, 16); ++ skb->dev = dev; ++ } ++ return skb; ++} ++#endif /* <= 2.6.17 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ) ++int _kc_pci_save_state(struct pci_dev *pdev) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int size = PCI_CONFIG_SPACE_LEN, i; ++ u16 pcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP); ++ u16 pcie_link_status; ++ ++ if (pcie_cap_offset) { ++ if (!pci_read_config_word(pdev, ++ pcie_cap_offset + PCIE_LINK_STATUS, ++ &pcie_link_status)) ++ size = PCIE_CONFIG_SPACE_LEN; ++ } ++ pci_config_space_ich8lan(); ++#ifdef HAVE_PCI_ERS ++ if (adapter->config_space == NULL) ++#else ++ WARN_ON(adapter->config_space != NULL); ++#endif ++ adapter->config_space = kmalloc(size, GFP_KERNEL); ++ if (!adapter->config_space) { ++ printk(KERN_ERR "Out of memory in pci_save_state\n"); ++ return -ENOMEM; ++ } ++ for (i = 0; i < (size / 4); i++) ++ pci_read_config_dword(pdev, i * 4, &adapter->config_space[i]); ++ return 0; ++} ++ ++void _kc_pci_restore_state(struct pci_dev * pdev) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int size = PCI_CONFIG_SPACE_LEN, i; ++ u16 pcie_cap_offset; ++ u16 pcie_link_status; ++ ++ if (adapter->config_space != NULL) { ++ pcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP); ++ if (pcie_cap_offset && ++ !pci_read_config_word(pdev, ++ pcie_cap_offset + PCIE_LINK_STATUS, ++ &pcie_link_status)) ++ size = PCIE_CONFIG_SPACE_LEN; ++ ++ pci_config_space_ich8lan(); ++ for (i = 0; i < (size / 4); i++) ++ pci_write_config_dword(pdev, i * 4, adapter->config_space[i]); ++#ifndef HAVE_PCI_ERS ++ kfree(adapter->config_space); ++ adapter->config_space = NULL; ++#endif ++ } ++} ++ ++#ifdef HAVE_PCI_ERS ++void _kc_free_netdev(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ ++ if (adapter->config_space != NULL) ++ kfree(adapter->config_space); ++#ifdef CONFIG_SYSFS ++ if (netdev->reg_state == NETREG_UNINITIALIZED) { ++ kfree((char *)netdev - netdev->padded); ++ } else { ++ BUG_ON(netdev->reg_state != NETREG_UNREGISTERED); ++ netdev->reg_state = NETREG_RELEASED; ++ class_device_put(&netdev->class_dev); ++ } ++#else ++ kfree((char *)netdev - netdev->padded); ++#endif ++} ++#endif ++#endif /* <= 2.6.18 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ) ++#ifdef NAPI ++/* this function returns the true netdev of the napi struct */ ++struct net_device * napi_to_netdev(struct napi_struct *napi) ++{ ++ struct adapter_q_vector *q_vector = container_of(napi, ++ struct adapter_q_vector, ++ napi); ++ struct adapter_struct *adapter = q_vector->adapter; ++ ++ return adapter->netdev; ++} ++ ++int _kc_napi_schedule_prep(struct napi_struct *napi) ++{ ++ return (netif_running(napi_to_netdev(napi)) && ++ netif_rx_schedule_prep(napi_to_poll_dev(napi))); ++} ++ ++int __kc_adapter_clean(struct net_device *netdev, int *budget) ++{ ++ int work_done; ++ int work_to_do = min(*budget, netdev->quota); ++ /* kcompat.h netif_napi_add puts napi struct in "fake netdev->priv" */ ++ struct napi_struct *napi = netdev->priv; ++ work_done = napi->poll(napi, work_to_do); ++ *budget -= work_done; ++ netdev->quota -= work_done; ++ return (work_done >= work_to_do) ? 1 : 0; ++} ++#endif /* NAPI */ ++#endif /* <= 2.6.24 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) ++#ifdef HAVE_TX_MQ ++void _kc_netif_tx_stop_all_queues(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int i; ++ ++ netif_stop_queue(netdev); ++ if (netif_is_multiqueue(netdev)) ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ netif_stop_subqueue(netdev, i); ++} ++void _kc_netif_tx_wake_all_queues(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int i; ++ ++ netif_wake_queue(netdev); ++ if (netif_is_multiqueue(netdev)) ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ netif_wake_subqueue(netdev, i); ++} ++void _kc_netif_tx_start_all_queues(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int i; ++ ++ netif_start_queue(netdev); ++ if (netif_is_multiqueue(netdev)) ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ netif_start_subqueue(netdev, i); ++} ++#endif /* HAVE_TX_MQ */ ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) ++ ++int ++_kc_pci_prepare_to_sleep(struct pci_dev *dev) ++{ ++ pci_power_t target_state; ++ int error; ++ ++ target_state = pci_choose_state(dev, PMSG_SUSPEND); ++ ++ pci_enable_wake(dev, target_state, true); ++ ++ error = pci_set_power_state(dev, target_state); ++ ++ if (error) ++ pci_enable_wake(dev, target_state, false); ++ ++ return error; ++} ++ ++int ++_kc_pci_wake_from_d3(struct pci_dev *dev, bool enable) ++{ ++ int err; ++ ++ err = pci_enable_wake(dev, PCI_D3cold, enable); ++ if (err) ++ goto out; ++ ++ err = pci_enable_wake(dev, PCI_D3hot, enable); ++ ++out: ++ return err; ++} ++#endif /* < 2.6.28 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) ) ++void _kc_pci_disable_link_state(struct pci_dev *pdev, int state) ++{ ++ struct pci_dev *parent = pdev->bus->self; ++ u16 link_state; ++ int pos; ++ ++ if (!parent) ++ return; ++ ++ pos = pci_find_capability(parent, PCI_CAP_ID_EXP); ++ if (pos) { ++ pci_read_config_word(parent, pos + PCI_EXP_LNKCTL, &link_state); ++ link_state &= ~state; ++ pci_write_config_word(parent, pos + PCI_EXP_LNKCTL, link_state); ++ } ++} ++#endif /* < 2.6.29 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ) ++#ifdef HAVE_NETDEV_SELECT_QUEUE ++#include ++u32 _kc_simple_tx_hashrnd; ++u32 _kc_simple_tx_hashrnd_initialized = 0; ++ ++u16 _kc_skb_tx_hash(struct net_device *dev, struct sk_buff *skb) ++{ ++ u32 addr1, addr2, ports; ++ u32 hash, ihl; ++ u8 ip_proto = 0; ++ ++ if (unlikely(!_kc_simple_tx_hashrnd_initialized)) { ++ get_random_bytes(&_kc_simple_tx_hashrnd, 4); ++ _kc_simple_tx_hashrnd_initialized = 1; ++ } ++ ++ switch (skb->protocol) { ++ case htons(ETH_P_IP): ++ if (!(ip_hdr(skb)->frag_off & htons(IP_MF | IP_OFFSET))) ++ ip_proto = ip_hdr(skb)->protocol; ++ addr1 = ip_hdr(skb)->saddr; ++ addr2 = ip_hdr(skb)->daddr; ++ ihl = ip_hdr(skb)->ihl; ++ break; ++ case htons(ETH_P_IPV6): ++ ip_proto = ipv6_hdr(skb)->nexthdr; ++ addr1 = ipv6_hdr(skb)->saddr.s6_addr32[3]; ++ addr2 = ipv6_hdr(skb)->daddr.s6_addr32[3]; ++ ihl = (40 >> 2); ++ break; ++ default: ++ return 0; ++ } ++ ++ ++ switch (ip_proto) { ++ case IPPROTO_TCP: ++ case IPPROTO_UDP: ++ case IPPROTO_DCCP: ++ case IPPROTO_ESP: ++ case IPPROTO_AH: ++ case IPPROTO_SCTP: ++ case IPPROTO_UDPLITE: ++ ports = *((u32 *) (skb_network_header(skb) + (ihl * 4))); ++ break; ++ ++ default: ++ ports = 0; ++ break; ++ } ++ ++ hash = jhash_3words(addr1, addr2, ports, _kc_simple_tx_hashrnd); ++ ++ return (u16) (((u64) hash * dev->real_num_tx_queues) >> 32); ++} ++#endif /* HAVE_NETDEV_SELECT_QUEUE */ ++#endif /* < 2.6.30 */ +diff -r 4f0f8bc35440 drivers/net/igb/kcompat.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/igb/kcompat.h Wed Aug 05 11:03:37 2009 +0100 +@@ -0,0 +1,1727 @@ ++/******************************************************************************* ++ ++ Intel(R) Gigabit Ethernet Linux driver ++ Copyright(c) 2007-2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _KCOMPAT_H_ ++#define _KCOMPAT_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* NAPI enable/disable flags here */ ++#define NAPI ++ ++#define adapter_struct igb_adapter ++#define adapter_q_vector igb_ring ++#define NAPI ++ ++/* and finally set defines so that the code sees the changes */ ++#ifdef NAPI ++#else ++#endif /* NAPI */ ++ ++/* packet split disable/enable */ ++#ifdef DISABLE_PACKET_SPLIT ++#undef CONFIG_E1000_DISABLE_PACKET_SPLIT ++#define CONFIG_E1000_DISABLE_PACKET_SPLIT ++#undef CONFIG_IGB_DISABLE_PACKET_SPLIT ++#define CONFIG_IGB_DISABLE_PACKET_SPLIT ++#endif ++ ++/* MSI compatibility code for all kernels and drivers */ ++#ifdef DISABLE_PCI_MSI ++#undef CONFIG_PCI_MSI ++#endif ++#ifndef CONFIG_PCI_MSI ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) ) ++struct msix_entry { ++ u16 vector; /* kernel uses to write allocated vector */ ++ u16 entry; /* driver uses to specify entry, OS writes */ ++}; ++#endif ++#define pci_enable_msi(a) -ENOTSUPP ++#define pci_disable_msi(a) do {} while (0) ++#define pci_enable_msix(a, b, c) -ENOTSUPP ++#define pci_disable_msix(a) do {} while (0) ++#define msi_remove_pci_irq_vectors(a) do {} while (0) ++#endif /* CONFIG_PCI_MSI */ ++#ifdef DISABLE_PM ++#undef CONFIG_PM ++#endif ++ ++#ifdef DISABLE_NET_POLL_CONTROLLER ++#undef CONFIG_NET_POLL_CONTROLLER ++#endif ++ ++#ifndef PMSG_SUSPEND ++#define PMSG_SUSPEND 3 ++#endif ++ ++/* generic boolean compatibility */ ++#undef TRUE ++#undef FALSE ++#define TRUE true ++#define FALSE false ++#ifdef GCC_VERSION ++#if ( GCC_VERSION < 3000 ) ++#define _Bool char ++#endif ++#endif ++#ifndef bool ++#define bool _Bool ++#define true 1 ++#define false 0 ++#endif ++ ++ ++#ifndef module_param ++#define module_param(v,t,p) MODULE_PARM(v, "i"); ++#endif ++ ++#ifndef DMA_64BIT_MASK ++#define DMA_64BIT_MASK 0xffffffffffffffffULL ++#endif ++ ++#ifndef DMA_32BIT_MASK ++#define DMA_32BIT_MASK 0x00000000ffffffffULL ++#endif ++ ++#ifndef PCI_CAP_ID_EXP ++#define PCI_CAP_ID_EXP 0x10 ++#endif ++ ++#ifndef PCIE_LINK_STATE_L0S ++#define PCIE_LINK_STATE_L0S 1 ++#endif ++ ++#ifndef mmiowb ++#ifdef CONFIG_IA64 ++#define mmiowb() asm volatile ("mf.a" ::: "memory") ++#else ++#define mmiowb() ++#endif ++#endif ++ ++#ifndef SET_NETDEV_DEV ++#define SET_NETDEV_DEV(net, pdev) ++#endif ++ ++#ifndef HAVE_FREE_NETDEV ++#define free_netdev(x) kfree(x) ++#endif ++ ++#ifdef HAVE_POLL_CONTROLLER ++#define CONFIG_NET_POLL_CONTROLLER ++#endif ++ ++#ifndef NETDEV_TX_OK ++#define NETDEV_TX_OK 0 ++#endif ++ ++#ifndef NETDEV_TX_BUSY ++#define NETDEV_TX_BUSY 1 ++#endif ++ ++#ifndef NETDEV_TX_LOCKED ++#define NETDEV_TX_LOCKED -1 ++#endif ++ ++#ifndef SKB_DATAREF_SHIFT ++/* if we do not have the infrastructure to detect if skb_header is cloned ++ just return false in all cases */ ++#define skb_header_cloned(x) 0 ++#endif ++ ++#ifndef NETIF_F_GSO ++#define gso_size tso_size ++#define gso_segs tso_segs ++#endif ++ ++#ifndef NETIF_F_GRO ++#define vlan_gro_receive(_napi, _vlgrp, _vlan, _skb) \ ++ vlan_hwaccel_receive_skb(_skb, _vlgrp, _vlan) ++#define napi_gro_receive(_napi, _skb) netif_receive_skb(_skb) ++#endif ++ ++#ifndef CHECKSUM_PARTIAL ++#define CHECKSUM_PARTIAL CHECKSUM_HW ++#define CHECKSUM_COMPLETE CHECKSUM_HW ++#endif ++ ++#ifndef __read_mostly ++#define __read_mostly ++#endif ++ ++#ifndef HAVE_NETIF_MSG ++#define HAVE_NETIF_MSG 1 ++enum { ++ NETIF_MSG_DRV = 0x0001, ++ NETIF_MSG_PROBE = 0x0002, ++ NETIF_MSG_LINK = 0x0004, ++ NETIF_MSG_TIMER = 0x0008, ++ NETIF_MSG_IFDOWN = 0x0010, ++ NETIF_MSG_IFUP = 0x0020, ++ NETIF_MSG_RX_ERR = 0x0040, ++ NETIF_MSG_TX_ERR = 0x0080, ++ NETIF_MSG_TX_QUEUED = 0x0100, ++ NETIF_MSG_INTR = 0x0200, ++ NETIF_MSG_TX_DONE = 0x0400, ++ NETIF_MSG_RX_STATUS = 0x0800, ++ NETIF_MSG_PKTDATA = 0x1000, ++ NETIF_MSG_HW = 0x2000, ++ NETIF_MSG_WOL = 0x4000, ++}; ++ ++#else ++#define NETIF_MSG_HW 0x2000 ++#define NETIF_MSG_WOL 0x4000 ++#endif /* HAVE_NETIF_MSG */ ++ ++#ifndef MII_RESV1 ++#define MII_RESV1 0x17 /* Reserved... */ ++#endif ++ ++#ifndef unlikely ++#define unlikely(_x) _x ++#define likely(_x) _x ++#endif ++ ++#ifndef WARN_ON ++#define WARN_ON(x) ++#endif ++ ++#ifndef PCI_DEVICE ++#define PCI_DEVICE(vend,dev) \ ++ .vendor = (vend), .device = (dev), \ ++ .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID ++#endif ++ ++#ifndef num_online_cpus ++#define num_online_cpus() smp_num_cpus ++#endif ++ ++#ifndef _LINUX_RANDOM_H ++#include ++#endif ++ ++#ifndef DECLARE_BITMAP ++#ifndef BITS_TO_LONGS ++#define BITS_TO_LONGS(bits) (((bits)+BITS_PER_LONG-1)/BITS_PER_LONG) ++#endif ++#define DECLARE_BITMAP(name,bits) long name[BITS_TO_LONGS(bits)] ++#endif ++ ++#ifndef VLAN_HLEN ++#define VLAN_HLEN 4 ++#endif ++ ++#ifndef VLAN_ETH_HLEN ++#define VLAN_ETH_HLEN 18 ++#endif ++ ++#ifndef VLAN_ETH_FRAME_LEN ++#define VLAN_ETH_FRAME_LEN 1518 ++#endif ++ ++#ifndef DCA_GET_TAG_TWO_ARGS ++#define dca3_get_tag(a,b) dca_get_tag(b) ++#endif ++ ++ ++/*****************************************************************************/ ++/* Installations with ethtool version without eeprom, adapter id, or statistics ++ * support */ ++ ++#ifndef ETH_GSTRING_LEN ++#define ETH_GSTRING_LEN 32 ++#endif ++ ++#ifndef ETHTOOL_GSTATS ++#define ETHTOOL_GSTATS 0x1d ++#undef ethtool_drvinfo ++#define ethtool_drvinfo k_ethtool_drvinfo ++struct k_ethtool_drvinfo { ++ u32 cmd; ++ char driver[32]; ++ char version[32]; ++ char fw_version[32]; ++ char bus_info[32]; ++ char reserved1[32]; ++ char reserved2[16]; ++ u32 n_stats; ++ u32 testinfo_len; ++ u32 eedump_len; ++ u32 regdump_len; ++}; ++ ++struct ethtool_stats { ++ u32 cmd; ++ u32 n_stats; ++ u64 data[0]; ++}; ++#endif /* ETHTOOL_GSTATS */ ++ ++#ifndef ETHTOOL_PHYS_ID ++#define ETHTOOL_PHYS_ID 0x1c ++#endif /* ETHTOOL_PHYS_ID */ ++ ++#ifndef ETHTOOL_GSTRINGS ++#define ETHTOOL_GSTRINGS 0x1b ++enum ethtool_stringset { ++ ETH_SS_TEST = 0, ++ ETH_SS_STATS, ++}; ++struct ethtool_gstrings { ++ u32 cmd; /* ETHTOOL_GSTRINGS */ ++ u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/ ++ u32 len; /* number of strings in the string set */ ++ u8 data[0]; ++}; ++#endif /* ETHTOOL_GSTRINGS */ ++ ++#ifndef ETHTOOL_TEST ++#define ETHTOOL_TEST 0x1a ++enum ethtool_test_flags { ++ ETH_TEST_FL_OFFLINE = (1 << 0), ++ ETH_TEST_FL_FAILED = (1 << 1), ++}; ++struct ethtool_test { ++ u32 cmd; ++ u32 flags; ++ u32 reserved; ++ u32 len; ++ u64 data[0]; ++}; ++#endif /* ETHTOOL_TEST */ ++ ++#ifndef ETHTOOL_GEEPROM ++#define ETHTOOL_GEEPROM 0xb ++#undef ETHTOOL_GREGS ++struct ethtool_eeprom { ++ u32 cmd; ++ u32 magic; ++ u32 offset; ++ u32 len; ++ u8 data[0]; ++}; ++ ++struct ethtool_value { ++ u32 cmd; ++ u32 data; ++}; ++#endif /* ETHTOOL_GEEPROM */ ++ ++#ifndef ETHTOOL_GLINK ++#define ETHTOOL_GLINK 0xa ++#endif /* ETHTOOL_GLINK */ ++ ++#ifndef ETHTOOL_GREGS ++#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers */ ++#define ethtool_regs _kc_ethtool_regs ++/* for passing big chunks of data */ ++struct _kc_ethtool_regs { ++ u32 cmd; ++ u32 version; /* driver-specific, indicates different chips/revs */ ++ u32 len; /* bytes */ ++ u8 data[0]; ++}; ++#endif /* ETHTOOL_GREGS */ ++ ++#ifndef ETHTOOL_GMSGLVL ++#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */ ++#endif ++#ifndef ETHTOOL_SMSGLVL ++#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level, priv. */ ++#endif ++#ifndef ETHTOOL_NWAY_RST ++#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation, priv */ ++#endif ++#ifndef ETHTOOL_GLINK ++#define ETHTOOL_GLINK 0x0000000a /* Get link status */ ++#endif ++#ifndef ETHTOOL_GEEPROM ++#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */ ++#endif ++#ifndef ETHTOOL_SEEPROM ++#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */ ++#endif ++#ifndef ETHTOOL_GCOALESCE ++#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */ ++/* for configuring coalescing parameters of chip */ ++#define ethtool_coalesce _kc_ethtool_coalesce ++struct _kc_ethtool_coalesce { ++ u32 cmd; /* ETHTOOL_{G,S}COALESCE */ ++ ++ /* How many usecs to delay an RX interrupt after ++ * a packet arrives. If 0, only rx_max_coalesced_frames ++ * is used. ++ */ ++ u32 rx_coalesce_usecs; ++ ++ /* How many packets to delay an RX interrupt after ++ * a packet arrives. If 0, only rx_coalesce_usecs is ++ * used. It is illegal to set both usecs and max frames ++ * to zero as this would cause RX interrupts to never be ++ * generated. ++ */ ++ u32 rx_max_coalesced_frames; ++ ++ /* Same as above two parameters, except that these values ++ * apply while an IRQ is being serviced by the host. Not ++ * all cards support this feature and the values are ignored ++ * in that case. ++ */ ++ u32 rx_coalesce_usecs_irq; ++ u32 rx_max_coalesced_frames_irq; ++ ++ /* How many usecs to delay a TX interrupt after ++ * a packet is sent. If 0, only tx_max_coalesced_frames ++ * is used. ++ */ ++ u32 tx_coalesce_usecs; ++ ++ /* How many packets to delay a TX interrupt after ++ * a packet is sent. If 0, only tx_coalesce_usecs is ++ * used. It is illegal to set both usecs and max frames ++ * to zero as this would cause TX interrupts to never be ++ * generated. ++ */ ++ u32 tx_max_coalesced_frames; ++ ++ /* Same as above two parameters, except that these values ++ * apply while an IRQ is being serviced by the host. Not ++ * all cards support this feature and the values are ignored ++ * in that case. ++ */ ++ u32 tx_coalesce_usecs_irq; ++ u32 tx_max_coalesced_frames_irq; ++ ++ /* How many usecs to delay in-memory statistics ++ * block updates. Some drivers do not have an in-memory ++ * statistic block, and in such cases this value is ignored. ++ * This value must not be zero. ++ */ ++ u32 stats_block_coalesce_usecs; ++ ++ /* Adaptive RX/TX coalescing is an algorithm implemented by ++ * some drivers to improve latency under low packet rates and ++ * improve throughput under high packet rates. Some drivers ++ * only implement one of RX or TX adaptive coalescing. Anything ++ * not implemented by the driver causes these values to be ++ * silently ignored. ++ */ ++ u32 use_adaptive_rx_coalesce; ++ u32 use_adaptive_tx_coalesce; ++ ++ /* When the packet rate (measured in packets per second) ++ * is below pkt_rate_low, the {rx,tx}_*_low parameters are ++ * used. ++ */ ++ u32 pkt_rate_low; ++ u32 rx_coalesce_usecs_low; ++ u32 rx_max_coalesced_frames_low; ++ u32 tx_coalesce_usecs_low; ++ u32 tx_max_coalesced_frames_low; ++ ++ /* When the packet rate is below pkt_rate_high but above ++ * pkt_rate_low (both measured in packets per second) the ++ * normal {rx,tx}_* coalescing parameters are used. ++ */ ++ ++ /* When the packet rate is (measured in packets per second) ++ * is above pkt_rate_high, the {rx,tx}_*_high parameters are ++ * used. ++ */ ++ u32 pkt_rate_high; ++ u32 rx_coalesce_usecs_high; ++ u32 rx_max_coalesced_frames_high; ++ u32 tx_coalesce_usecs_high; ++ u32 tx_max_coalesced_frames_high; ++ ++ /* How often to do adaptive coalescing packet rate sampling, ++ * measured in seconds. Must not be zero. ++ */ ++ u32 rate_sample_interval; ++}; ++#endif /* ETHTOOL_GCOALESCE */ ++ ++#ifndef ETHTOOL_SCOALESCE ++#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */ ++#endif ++#ifndef ETHTOOL_GRINGPARAM ++#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */ ++/* for configuring RX/TX ring parameters */ ++#define ethtool_ringparam _kc_ethtool_ringparam ++struct _kc_ethtool_ringparam { ++ u32 cmd; /* ETHTOOL_{G,S}RINGPARAM */ ++ ++ /* Read only attributes. These indicate the maximum number ++ * of pending RX/TX ring entries the driver will allow the ++ * user to set. ++ */ ++ u32 rx_max_pending; ++ u32 rx_mini_max_pending; ++ u32 rx_jumbo_max_pending; ++ u32 tx_max_pending; ++ ++ /* Values changeable by the user. The valid values are ++ * in the range 1 to the "*_max_pending" counterpart above. ++ */ ++ u32 rx_pending; ++ u32 rx_mini_pending; ++ u32 rx_jumbo_pending; ++ u32 tx_pending; ++}; ++#endif /* ETHTOOL_GRINGPARAM */ ++ ++#ifndef ETHTOOL_SRINGPARAM ++#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters, priv. */ ++#endif ++#ifndef ETHTOOL_GPAUSEPARAM ++#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */ ++/* for configuring link flow control parameters */ ++#define ethtool_pauseparam _kc_ethtool_pauseparam ++struct _kc_ethtool_pauseparam { ++ u32 cmd; /* ETHTOOL_{G,S}PAUSEPARAM */ ++ ++ /* If the link is being auto-negotiated (via ethtool_cmd.autoneg ++ * being true) the user may set 'autoneg' here non-zero to have the ++ * pause parameters be auto-negotiated too. In such a case, the ++ * {rx,tx}_pause values below determine what capabilities are ++ * advertised. ++ * ++ * If 'autoneg' is zero or the link is not being auto-negotiated, ++ * then {rx,tx}_pause force the driver to use/not-use pause ++ * flow control. ++ */ ++ u32 autoneg; ++ u32 rx_pause; ++ u32 tx_pause; ++}; ++#endif /* ETHTOOL_GPAUSEPARAM */ ++ ++#ifndef ETHTOOL_SPAUSEPARAM ++#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */ ++#endif ++#ifndef ETHTOOL_GRXCSUM ++#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_SRXCSUM ++#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_GTXCSUM ++#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_STXCSUM ++#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_GSG ++#define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable ++ * (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_SSG ++#define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable ++ * (ethtool_value). */ ++#endif ++#ifndef ETHTOOL_TEST ++#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test, priv. */ ++#endif ++#ifndef ETHTOOL_GSTRINGS ++#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */ ++#endif ++#ifndef ETHTOOL_PHYS_ID ++#define ETHTOOL_PHYS_ID 0x0000001c /* identify the NIC */ ++#endif ++#ifndef ETHTOOL_GSTATS ++#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */ ++#endif ++#ifndef ETHTOOL_GTSO ++#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_STSO ++#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */ ++#endif ++ ++#ifndef ETHTOOL_BUSINFO_LEN ++#define ETHTOOL_BUSINFO_LEN 32 ++#endif ++ ++/*****************************************************************************/ ++/* 2.4.3 => 2.4.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) ) ++ ++/**************************************/ ++/* PCI DRIVER API */ ++ ++#ifndef pci_set_dma_mask ++#define pci_set_dma_mask _kc_pci_set_dma_mask ++extern int _kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask); ++#endif ++ ++#ifndef pci_request_regions ++#define pci_request_regions _kc_pci_request_regions ++extern int _kc_pci_request_regions(struct pci_dev *pdev, char *res_name); ++#endif ++ ++#ifndef pci_release_regions ++#define pci_release_regions _kc_pci_release_regions ++extern void _kc_pci_release_regions(struct pci_dev *pdev); ++#endif ++ ++/**************************************/ ++/* NETWORK DRIVER API */ ++ ++#ifndef alloc_etherdev ++#define alloc_etherdev _kc_alloc_etherdev ++extern struct net_device * _kc_alloc_etherdev(int sizeof_priv); ++#endif ++ ++#ifndef is_valid_ether_addr ++#define is_valid_ether_addr _kc_is_valid_ether_addr ++extern int _kc_is_valid_ether_addr(u8 *addr); ++#endif ++ ++/**************************************/ ++/* MISCELLANEOUS */ ++ ++#ifndef INIT_TQUEUE ++#define INIT_TQUEUE(_tq, _routine, _data) \ ++ do { \ ++ INIT_LIST_HEAD(&(_tq)->list); \ ++ (_tq)->sync = 0; \ ++ (_tq)->routine = _routine; \ ++ (_tq)->data = _data; \ ++ } while (0) ++#endif ++ ++#endif /* 2.4.3 => 2.4.0 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,5) ) ++/* Generic MII registers. */ ++#define MII_BMCR 0x00 /* Basic mode control register */ ++#define MII_BMSR 0x01 /* Basic mode status register */ ++#define MII_PHYSID1 0x02 /* PHYS ID 1 */ ++#define MII_PHYSID2 0x03 /* PHYS ID 2 */ ++#define MII_ADVERTISE 0x04 /* Advertisement control reg */ ++#define MII_LPA 0x05 /* Link partner ability reg */ ++#define MII_EXPANSION 0x06 /* Expansion register */ ++/* Basic mode control register. */ ++#define BMCR_FULLDPLX 0x0100 /* Full duplex */ ++#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ ++/* Basic mode status register. */ ++#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ ++#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ ++#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ ++#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ ++#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ ++#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ ++/* Advertisement control register. */ ++#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ ++#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ ++#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ ++#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ ++#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ ++#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ++ ADVERTISE_100HALF | ADVERTISE_100FULL) ++/* Expansion register for auto-negotiation. */ ++#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ ++#endif ++ ++/*****************************************************************************/ ++/* 2.4.6 => 2.4.3 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) ) ++ ++#ifndef pci_set_power_state ++#define pci_set_power_state _kc_pci_set_power_state ++extern int _kc_pci_set_power_state(struct pci_dev *dev, int state); ++#endif ++ ++#ifndef pci_enable_wake ++#define pci_enable_wake _kc_pci_enable_wake ++extern int _kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable); ++#endif ++ ++#ifndef pci_disable_device ++#define pci_disable_device _kc_pci_disable_device ++extern void _kc_pci_disable_device(struct pci_dev *pdev); ++#endif ++ ++/* PCI PM entry point syntax changed, so don't support suspend/resume */ ++#undef CONFIG_PM ++ ++#endif /* 2.4.6 => 2.4.3 */ ++ ++#ifndef HAVE_PCI_SET_MWI ++#define pci_set_mwi(X) pci_write_config_word(X, \ ++ PCI_COMMAND, adapter->hw.bus.pci_cmd_word | \ ++ PCI_COMMAND_INVALIDATE); ++#define pci_clear_mwi(X) pci_write_config_word(X, \ ++ PCI_COMMAND, adapter->hw.bus.pci_cmd_word & \ ++ ~PCI_COMMAND_INVALIDATE); ++#endif ++ ++/*****************************************************************************/ ++/* 2.4.10 => 2.4.9 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,10) ) ++ ++/**************************************/ ++/* MODULE API */ ++ ++#ifndef MODULE_LICENSE ++ #define MODULE_LICENSE(X) ++#endif ++ ++/**************************************/ ++/* OTHER */ ++ ++#undef min ++#define min(x,y) ({ \ ++ const typeof(x) _x = (x); \ ++ const typeof(y) _y = (y); \ ++ (void) (&_x == &_y); \ ++ _x < _y ? _x : _y; }) ++ ++#undef max ++#define max(x,y) ({ \ ++ const typeof(x) _x = (x); \ ++ const typeof(y) _y = (y); \ ++ (void) (&_x == &_y); \ ++ _x > _y ? _x : _y; }) ++ ++#define min_t(type,x,y) ({ \ ++ type _x = (x); \ ++ type _y = (y); \ ++ _x < _y ? _x : _y; }) ++ ++#define max_t(type,x,y) ({ \ ++ type _x = (x); \ ++ type _y = (y); \ ++ _x > _y ? _x : _y; }) ++ ++#ifndef list_for_each_safe ++#define list_for_each_safe(pos, n, head) \ ++ for (pos = (head)->next, n = pos->next; pos != (head); \ ++ pos = n, n = pos->next) ++#endif ++ ++#endif /* 2.4.10 -> 2.4.6 */ ++ ++ ++/*****************************************************************************/ ++/* 2.4.13 => 2.4.10 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) ) ++ ++/**************************************/ ++/* PCI DMA MAPPING */ ++ ++#ifndef virt_to_page ++ #define virt_to_page(v) (mem_map + (virt_to_phys(v) >> PAGE_SHIFT)) ++#endif ++ ++#ifndef pci_map_page ++#define pci_map_page _kc_pci_map_page ++extern u64 _kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, size_t size, int direction); ++#endif ++ ++#ifndef pci_unmap_page ++#define pci_unmap_page _kc_pci_unmap_page ++extern void _kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, int direction); ++#endif ++ ++/* pci_set_dma_mask takes dma_addr_t, which is only 32-bits prior to 2.4.13 */ ++ ++#undef DMA_32BIT_MASK ++#define DMA_32BIT_MASK 0xffffffff ++#undef DMA_64BIT_MASK ++#define DMA_64BIT_MASK 0xffffffff ++ ++/**************************************/ ++/* OTHER */ ++ ++#ifndef cpu_relax ++#define cpu_relax() rep_nop() ++#endif ++ ++#endif /* 2.4.13 => 2.4.10 */ ++ ++/*****************************************************************************/ ++/* 2.4.17 => 2.4.12 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17) ) ++ ++#ifndef __devexit_p ++ #define __devexit_p(x) &(x) ++#endif ++ ++#endif /* 2.4.17 => 2.4.13 */ ++ ++/*****************************************************************************/ ++/* 2.4.20 => 2.4.19 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,20) ) ++ ++/* we won't support NAPI on less than 2.4.20 */ ++#ifdef NAPI ++#endif ++ ++#endif /* 2.4.20 => 2.4.19 */ ++ ++/*****************************************************************************/ ++/* < 2.4.21 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,21) ) ++#define skb_pad(x,y) _kc_skb_pad(x, y) ++struct sk_buff * _kc_skb_pad(struct sk_buff *skb, int pad); ++#endif /* < 2.4.21 */ ++ ++/*****************************************************************************/ ++/* 2.4.22 => 2.4.17 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) ) ++#define pci_name(x) ((x)->slot_name) ++#endif ++ ++/*****************************************************************************/ ++/*****************************************************************************/ ++/* 2.4.23 => 2.4.22 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23) ) ++/*****************************************************************************/ ++#ifdef NAPI ++#ifndef netif_poll_disable ++#define netif_poll_disable(x) _kc_netif_poll_disable(x) ++static inline void _kc_netif_poll_disable(struct net_device *netdev) ++{ ++ while (test_and_set_bit(__LINK_STATE_RX_SCHED, &netdev->state)) { ++ /* No hurry */ ++ current->state = TASK_INTERRUPTIBLE; ++ schedule_timeout(1); ++ } ++} ++#endif ++ ++#ifndef netif_poll_enable ++#define netif_poll_enable(x) _kc_netif_poll_enable(x) ++static inline void _kc_netif_poll_enable(struct net_device *netdev) ++{ ++ clear_bit(__LINK_STATE_RX_SCHED, &netdev->state); ++} ++#endif ++#endif /* NAPI */ ++#ifndef netif_tx_disable ++#define netif_tx_disable(x) _kc_netif_tx_disable(x) ++static inline void _kc_netif_tx_disable(struct net_device *dev) ++{ ++ spin_lock_bh(&dev->xmit_lock); ++ netif_stop_queue(dev); ++ spin_unlock_bh(&dev->xmit_lock); ++} ++#endif ++#endif /* 2.4.23 => 2.4.22 */ ++ ++/*****************************************************************************/ ++/* 2.6.4 => 2.6.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,25) || \ ++ ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \ ++ LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) ) ++#define ETHTOOL_OPS_COMPAT ++#endif /* 2.6.4 => 2.6.0 */ ++ ++/*****************************************************************************/ ++/* 2.5.71 => 2.4.x */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,71) ) ++#include ++#define sk_protocol protocol ++ ++#define pci_get_device pci_find_device ++#endif /* 2.5.70 => 2.4.x */ ++ ++/*****************************************************************************/ ++/* < 2.4.27 or 2.6.0 <= 2.6.5 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) || \ ++ ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \ ++ LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) ) ++ ++#ifndef netif_msg_init ++#define netif_msg_init _kc_netif_msg_init ++static inline u32 _kc_netif_msg_init(int debug_value, int default_msg_enable_bits) ++{ ++ /* use default */ ++ if (debug_value < 0 || debug_value >= (sizeof(u32) * 8)) ++ return default_msg_enable_bits; ++ if (debug_value == 0) /* no output */ ++ return 0; ++ /* set low N bits */ ++ return (1 << debug_value) -1; ++} ++#endif ++ ++#endif /* < 2.4.27 or 2.6.0 <= 2.6.5 */ ++/*****************************************************************************/ ++#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \ ++ (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \ ++ ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) ))) ++#define netdev_priv(x) x->priv ++#endif ++ ++/*****************************************************************************/ ++/* <= 2.5.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ) ++#undef pci_register_driver ++#define pci_register_driver pci_module_init ++ ++#define dev_err(__unused_dev, format, arg...) \ ++ printk(KERN_ERR "%s: " format, pci_name(adapter->pdev) , ## arg) ++#define dev_warn(__unused_dev, format, arg...) \ ++ printk(KERN_WARNING "%s: " format, pci_name(pdev) , ## arg) ++ ++/* hlist_* code - double linked lists */ ++struct hlist_head { ++ struct hlist_node *first; ++}; ++ ++struct hlist_node { ++ struct hlist_node *next, **pprev; ++}; ++ ++static inline void __hlist_del(struct hlist_node *n) ++{ ++ struct hlist_node *next = n->next; ++ struct hlist_node **pprev = n->pprev; ++ *pprev = next; ++ if (next) ++ next->pprev = pprev; ++} ++ ++static inline void hlist_del(struct hlist_node *n) ++{ ++ __hlist_del(n); ++ n->next = NULL; ++ n->pprev = NULL; ++} ++ ++static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) ++{ ++ struct hlist_node *first = h->first; ++ n->next = first; ++ if (first) ++ first->pprev = &n->next; ++ h->first = n; ++ n->pprev = &h->first; ++} ++ ++static inline int hlist_empty(const struct hlist_head *h) ++{ ++ return !h->first; ++} ++#define HLIST_HEAD_INIT { .first = NULL } ++#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL } ++#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL) ++static inline void INIT_HLIST_NODE(struct hlist_node *h) ++{ ++ h->next = NULL; ++ h->pprev = NULL; ++} ++#define hlist_entry(ptr, type, member) container_of(ptr,type,member) ++ ++#define hlist_for_each_entry(tpos, pos, head, member) \ ++ for (pos = (head)->first; \ ++ pos && ({ prefetch(pos->next); 1;}) && \ ++ ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ ++ pos = pos->next) ++ ++#define hlist_for_each_entry_safe(tpos, pos, n, head, member) \ ++ for (pos = (head)->first; \ ++ pos && ({ n = pos->next; 1; }) && \ ++ ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ ++ pos = n) ++ ++/* we ignore GFP here */ ++#define dma_alloc_coherent(dv, sz, dma, gfp) \ ++ pci_alloc_consistent(pdev, (sz), (dma)) ++#define dma_free_coherent(dv, sz, addr, dma_addr) \ ++ pci_free_consistent(pdev, (sz), (addr), (dma_addr)) ++ ++#ifndef might_sleep ++#define might_sleep() ++#endif ++ ++#endif /* <= 2.5.0 */ ++ ++/*****************************************************************************/ ++/* 2.5.28 => 2.4.23 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) ) ++ ++static inline void _kc_synchronize_irq(void) ++{ ++ synchronize_irq(); ++} ++#undef synchronize_irq ++#define synchronize_irq(X) _kc_synchronize_irq() ++ ++#include ++#define work_struct tq_struct ++#undef INIT_WORK ++#define INIT_WORK(a,b) INIT_TQUEUE(a,(void (*)(void *))b,a) ++#undef container_of ++#define container_of list_entry ++#define schedule_work schedule_task ++#define flush_scheduled_work flush_scheduled_tasks ++#define cancel_work_sync(x) flush_scheduled_work() ++ ++#endif /* 2.5.28 => 2.4.17 */ ++ ++/*****************************************************************************/ ++/* 2.6.0 => 2.5.28 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) ++#define MODULE_INFO(version, _version) ++#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT ++#define CONFIG_E1000_DISABLE_PACKET_SPLIT 1 ++#endif ++#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT ++#define CONFIG_IGB_DISABLE_PACKET_SPLIT 1 ++#endif ++ ++#define pci_set_consistent_dma_mask(dev,mask) 1 ++ ++#undef dev_put ++#define dev_put(dev) __dev_put(dev) ++ ++#ifndef skb_fill_page_desc ++#define skb_fill_page_desc _kc_skb_fill_page_desc ++extern void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int off, int size); ++#endif ++ ++#undef ALIGN ++#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1)) ++ ++#ifndef page_count ++#define page_count(p) atomic_read(&(p)->count) ++#endif ++ ++/* find_first_bit and find_next bit are not defined for most ++ * 2.4 kernels (except for the redhat 2.4.21 kernels ++ */ ++#include ++#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG) ++#undef find_next_bit ++#define find_next_bit _kc_find_next_bit ++extern unsigned long _kc_find_next_bit(const unsigned long *addr, ++ unsigned long size, ++ unsigned long offset); ++#define find_first_bit(addr, size) find_next_bit((addr), (size), 0) ++ ++#endif /* 2.6.0 => 2.5.28 */ ++ ++/*****************************************************************************/ ++/* 2.6.4 => 2.6.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) ++#define MODULE_VERSION(_version) MODULE_INFO(version, _version) ++#endif /* 2.6.4 => 2.6.0 */ ++ ++/*****************************************************************************/ ++/* 2.6.5 => 2.6.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) ++#define pci_dma_sync_single_for_cpu pci_dma_sync_single ++#define pci_dma_sync_single_for_device pci_dma_sync_single_for_cpu ++#endif /* 2.6.5 => 2.6.0 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,6) ) ++/* taken from 2.6 include/linux/bitmap.h */ ++#undef bitmap_zero ++#define bitmap_zero _kc_bitmap_zero ++static inline void _kc_bitmap_zero(unsigned long *dst, int nbits) ++{ ++ if (nbits <= BITS_PER_LONG) ++ *dst = 0UL; ++ else { ++ int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long); ++ memset(dst, 0, len); ++ } ++} ++#endif /* < 2.6.6 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) ) ++#undef if_mii ++#define if_mii _kc_if_mii ++static inline struct mii_ioctl_data *_kc_if_mii(struct ifreq *rq) ++{ ++ return (struct mii_ioctl_data *) &rq->ifr_ifru; ++} ++#endif /* < 2.6.7 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) ) ++#ifndef PCI_EXP_DEVCTL ++#define PCI_EXP_DEVCTL 8 ++#endif ++#ifndef PCI_EXP_DEVCTL_CERE ++#define PCI_EXP_DEVCTL_CERE 0x0001 ++#endif ++#define msleep(x) do { set_current_state(TASK_UNINTERRUPTIBLE); \ ++ schedule_timeout((x * HZ)/1000 + 2); \ ++ } while (0) ++ ++#endif /* < 2.6.8 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)) ++#include ++#define __iomem ++ ++#ifndef kcalloc ++#define kcalloc(n, size, flags) _kc_kzalloc(((n) * (size)), flags) ++extern void *_kc_kzalloc(size_t size, int flags); ++#endif ++#define MSEC_PER_SEC 1000L ++static inline unsigned int _kc_jiffies_to_msecs(const unsigned long j) ++{ ++#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) ++ return (MSEC_PER_SEC / HZ) * j; ++#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) ++ return (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC); ++#else ++ return (j * MSEC_PER_SEC) / HZ; ++#endif ++} ++static inline unsigned long _kc_msecs_to_jiffies(const unsigned int m) ++{ ++ if (m > _kc_jiffies_to_msecs(MAX_JIFFY_OFFSET)) ++ return MAX_JIFFY_OFFSET; ++#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) ++ return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ); ++#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) ++ return m * (HZ / MSEC_PER_SEC); ++#else ++ return (m * HZ + MSEC_PER_SEC - 1) / MSEC_PER_SEC; ++#endif ++} ++ ++#define msleep_interruptible _kc_msleep_interruptible ++static inline unsigned long _kc_msleep_interruptible(unsigned int msecs) ++{ ++ unsigned long timeout = _kc_msecs_to_jiffies(msecs) + 1; ++ ++ while (timeout && !signal_pending(current)) { ++ __set_current_state(TASK_INTERRUPTIBLE); ++ timeout = schedule_timeout(timeout); ++ } ++ return _kc_jiffies_to_msecs(timeout); ++} ++ ++/* Basic mode control register. */ ++#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ ++ ++#ifndef __le16 ++#define __le16 u16 ++#endif ++#ifndef __le32 ++#define __le32 u32 ++#endif ++#ifndef __le64 ++#define __le64 u64 ++#endif ++ ++#ifdef pci_dma_mapping_error ++#undef pci_dma_mapping_error ++#endif ++#define pci_dma_mapping_error _kc_pci_dma_mapping_error ++static inline int _kc_pci_dma_mapping_error(struct pci_dev *pdev, ++ dma_addr_t dma_addr) ++{ ++ return dma_addr == 0; ++} ++ ++#endif /* < 2.6.9 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ) ++#ifdef module_param_array_named ++#undef module_param_array_named ++#define module_param_array_named(name, array, type, nump, perm) \ ++ static struct kparam_array __param_arr_##name \ ++ = { ARRAY_SIZE(array), nump, param_set_##type, param_get_##type, \ ++ sizeof(array[0]), array }; \ ++ module_param_call(name, param_array_set, param_array_get, \ ++ &__param_arr_##name, perm) ++#endif /* module_param_array_named */ ++#endif /* < 2.6.10 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) ) ++#define PCI_D0 0 ++#define PCI_D1 1 ++#define PCI_D2 2 ++#define PCI_D3hot 3 ++#define PCI_D3cold 4 ++typedef int pci_power_t; ++#define pci_choose_state(pdev,state) state ++#define PMSG_SUSPEND 3 ++#define PCI_EXP_LNKCTL 16 ++ ++#undef NETIF_F_LLTX ++ ++#ifndef ARCH_HAS_PREFETCH ++#define prefetch(X) ++#endif ++ ++#ifndef NET_IP_ALIGN ++#define NET_IP_ALIGN 2 ++#endif ++ ++#define KC_USEC_PER_SEC 1000000L ++#define usecs_to_jiffies _kc_usecs_to_jiffies ++static inline unsigned int _kc_jiffies_to_usecs(const unsigned long j) ++{ ++#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ) ++ return (KC_USEC_PER_SEC / HZ) * j; ++#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC) ++ return (j + (HZ / KC_USEC_PER_SEC) - 1)/(HZ / KC_USEC_PER_SEC); ++#else ++ return (j * KC_USEC_PER_SEC) / HZ; ++#endif ++} ++static inline unsigned long _kc_usecs_to_jiffies(const unsigned int m) ++{ ++ if (m > _kc_jiffies_to_usecs(MAX_JIFFY_OFFSET)) ++ return MAX_JIFFY_OFFSET; ++#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ) ++ return (m + (KC_USEC_PER_SEC / HZ) - 1) / (KC_USEC_PER_SEC / HZ); ++#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC) ++ return m * (HZ / KC_USEC_PER_SEC); ++#else ++ return (m * HZ + KC_USEC_PER_SEC - 1) / KC_USEC_PER_SEC; ++#endif ++} ++#endif /* < 2.6.11 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,12) ) ++#include ++#define USE_REBOOT_NOTIFIER ++ ++/* Generic MII registers. */ ++#define MII_CTRL1000 0x09 /* 1000BASE-T control */ ++#define MII_STAT1000 0x0a /* 1000BASE-T status */ ++/* Advertisement control register. */ ++#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ ++#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymmetric pause */ ++/* 1000BASE-T Control register */ ++#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ ++#endif /* < 2.6.12 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) ) ++#define pm_message_t u32 ++#ifndef kzalloc ++#define kzalloc _kc_kzalloc ++extern void *_kc_kzalloc(size_t size, int flags); ++#endif ++ ++/* Generic MII registers. */ ++#define MII_ESTATUS 0x0f /* Extended Status */ ++/* Basic mode status register. */ ++#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ ++/* Extended status register. */ ++#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ ++#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ ++#endif /* < 2.6.14 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) ) ++#ifndef device_can_wakeup ++#define device_can_wakeup(dev) (1) ++#endif ++#ifndef device_set_wakeup_enable ++#define device_set_wakeup_enable(dev, val) do{}while(0) ++#endif ++#ifndef device_init_wakeup ++#define device_init_wakeup(dev,val) do {} while (0) ++#endif ++#endif /* < 2.6.15 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) ) ++#undef HAVE_PCI_ERS ++#else /* 2.6.16 and above */ ++#undef HAVE_PCI_ERS ++#define HAVE_PCI_ERS ++#endif /* < 2.6.16 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ) ++ ++#ifndef IRQ_HANDLED ++#define irqreturn_t void ++#define IRQ_HANDLED ++#define IRQ_NONE ++#endif ++ ++#ifndef IRQF_PROBE_SHARED ++#ifdef SA_PROBEIRQ ++#define IRQF_PROBE_SHARED SA_PROBEIRQ ++#else ++#define IRQF_PROBE_SHARED 0 ++#endif ++#endif ++ ++#ifndef IRQF_SHARED ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#ifndef ARRAY_SIZE ++#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) ++#endif ++ ++#ifndef netdev_alloc_skb ++#define netdev_alloc_skb _kc_netdev_alloc_skb ++extern struct sk_buff *_kc_netdev_alloc_skb(struct net_device *dev, ++ unsigned int length); ++#endif ++ ++#ifndef skb_is_gso ++#ifdef NETIF_F_TSO ++#define skb_is_gso _kc_skb_is_gso ++static inline int _kc_skb_is_gso(const struct sk_buff *skb) ++{ ++ return skb_shinfo(skb)->gso_size; ++} ++#else ++#define skb_is_gso(a) 0 ++#endif ++#endif ++ ++#endif /* < 2.6.18 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ) ++ ++#ifndef DIV_ROUND_UP ++#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) ++#endif ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) ) ++#ifndef RHEL_RELEASE_CODE ++#define RHEL_RELEASE_CODE 0 ++#endif ++#ifndef RHEL_RELEASE_VERSION ++#define RHEL_RELEASE_VERSION(a,b) 0 ++#endif ++#ifndef AX_RELEASE_CODE ++#define AX_RELEASE_CODE 0 ++#endif ++#ifndef AX_RELEASE_VERSION ++#define AX_RELEASE_VERSION(a,b) 0 ++#endif ++#if (!(( RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,4) ) && ( RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0) ) || ( RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,0) ) || (AX_RELEASE_CODE > AX_RELEASE_VERSION(3,0)))) ++typedef irqreturn_t (*irq_handler_t)(int, void*, struct pt_regs *); ++#endif ++#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0)) ++#undef CONFIG_INET_LRO ++#undef CONFIG_INET_LRO_MODULE ++#ifdef IXGBE_FCOE ++#undef CONFIG_FCOE ++#undef CONFIG_FCOE_MODULE ++#endif /* IXGBE_FCOE */ ++#endif ++typedef irqreturn_t (*new_handler_t)(int, void*); ++static inline irqreturn_t _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id) ++#else /* 2.4.x */ ++typedef void (*irq_handler_t)(int, void*, struct pt_regs *); ++typedef void (*new_handler_t)(int, void*); ++static inline int _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id) ++#endif /* >= 2.5.x */ ++{ ++ irq_handler_t new_handler = (irq_handler_t) handler; ++ return request_irq(irq, new_handler, flags, devname, dev_id); ++} ++ ++#undef request_irq ++#define request_irq(irq, handler, flags, devname, dev_id) _kc_request_irq((irq), (handler), (flags), (devname), (dev_id)) ++ ++#define irq_handler_t new_handler_t ++/* pci_restore_state and pci_save_state handles MSI/PCIE from 2.6.19 */ ++#define PCIE_CONFIG_SPACE_LEN 256 ++#define PCI_CONFIG_SPACE_LEN 64 ++#define PCIE_LINK_STATUS 0x12 ++#define pci_config_space_ich8lan() do {} while(0) ++#undef pci_save_state ++extern int _kc_pci_save_state(struct pci_dev *); ++#define pci_save_state(pdev) _kc_pci_save_state(pdev) ++#undef pci_restore_state ++extern void _kc_pci_restore_state(struct pci_dev *); ++#define pci_restore_state(pdev) _kc_pci_restore_state(pdev) ++#ifdef HAVE_PCI_ERS ++#undef free_netdev ++extern void _kc_free_netdev(struct net_device *); ++#define free_netdev(netdev) _kc_free_netdev(netdev) ++#endif ++static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev) ++{ ++ return 0; ++} ++#define pci_disable_pcie_error_reporting(dev) do {} while (0) ++#define pci_cleanup_aer_uncorrect_error_status(dev) do {} while (0) ++#else /* 2.6.19 */ ++#include ++#endif /* < 2.6.19 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ) ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,28) ) ++#undef INIT_WORK ++#define INIT_WORK(_work, _func) \ ++do { \ ++ INIT_LIST_HEAD(&(_work)->entry); \ ++ (_work)->pending = 0; \ ++ (_work)->func = (void (*)(void *))_func; \ ++ (_work)->data = _work; \ ++ init_timer(&(_work)->timer); \ ++} while (0) ++#endif ++ ++#ifndef PCI_VDEVICE ++#define PCI_VDEVICE(ven, dev) \ ++ PCI_VENDOR_ID_##ven, (dev), \ ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0 ++#endif ++ ++#ifndef round_jiffies ++#define round_jiffies(x) x ++#endif ++ ++#define csum_offset csum ++ ++#endif /* < 2.6.20 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) ) ++#define to_net_dev(class) container_of(class, struct net_device, class_dev) ++#define NETDEV_CLASS_DEV ++#define vlan_group_get_device(vg, id) (vg->vlan_devices[id]) ++#define vlan_group_set_device(vg, id, dev) if (vg) vg->vlan_devices[id] = dev; ++#define pci_channel_offline(pdev) (pdev->error_state && \ ++ pdev->error_state != pci_channel_io_normal) ++#define pci_request_selected_regions(pdev, bars, name) \ ++ pci_request_regions(pdev, name) ++#define pci_release_selected_regions(pdev, bars) pci_release_regions(pdev); ++#endif /* < 2.6.21 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) ) ++#define tcp_hdr(skb) (skb->h.th) ++#define tcp_hdrlen(skb) (skb->h.th->doff << 2) ++#define skb_transport_offset(skb) (skb->h.raw - skb->data) ++#define skb_transport_header(skb) (skb->h.raw) ++#define ipv6_hdr(skb) (skb->nh.ipv6h) ++#define ip_hdr(skb) (skb->nh.iph) ++#define skb_network_offset(skb) (skb->nh.raw - skb->data) ++#define skb_network_header(skb) (skb->nh.raw) ++#define skb_tail_pointer(skb) skb->tail ++#define skb_copy_to_linear_data_offset(skb, offset, from, len) \ ++ memcpy(skb->data + offset, from, len) ++#define skb_network_header_len(skb) (skb->h.raw - skb->nh.raw) ++#define pci_register_driver pci_module_init ++#define skb_mac_header(skb) skb->mac.raw ++ ++#ifdef NETIF_F_MULTI_QUEUE ++#ifndef alloc_etherdev_mq ++#define alloc_etherdev_mq(_a, _b) alloc_etherdev(_a) ++#endif ++#endif /* NETIF_F_MULTI_QUEUE */ ++ ++#ifndef ETH_FCS_LEN ++#define ETH_FCS_LEN 4 ++#endif ++#define cancel_work_sync(x) flush_scheduled_work() ++#ifndef udp_hdr ++#define udp_hdr _udp_hdr ++static inline struct udphdr *_udp_hdr(const struct sk_buff *skb) ++{ ++ return (struct udphdr *)skb_transport_header(skb); ++} ++#endif ++#endif /* < 2.6.22 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) ) ++#undef ETHTOOL_GPERMADDR ++#undef SET_MODULE_OWNER ++#define SET_MODULE_OWNER(dev) do { } while (0) ++#endif /* > 2.6.22 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ) ++#define netif_subqueue_stopped(_a, _b) 0 ++#endif /* < 2.6.23 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ) ++/* NAPI API changes in 2.6.24 break everything */ ++struct napi_struct { ++ /* used to look up the real NAPI polling routine */ ++ int (*poll)(struct napi_struct *, int); ++ struct net_device poll_dev; ++ int weight; ++}; ++#ifdef NAPI ++extern int __kc_adapter_clean(struct net_device *, int *); ++extern struct net_device * napi_to_netdev(struct napi_struct *); ++#define napi_to_poll_dev(_napi) &(_napi)->poll_dev ++#define napi_enable(napi) do { \ ++ /* abuse if_port as a counter */ \ ++ if (!adapter->netdev->if_port) { \ ++ netif_poll_enable(adapter->netdev); \ ++ } \ ++ ++adapter->netdev->if_port; \ ++ netif_poll_enable(&(napi)->poll_dev); \ ++ } while (0) ++#define napi_disable(_napi) do { \ ++ netif_poll_disable(&(_napi)->poll_dev); \ ++ --adapter->netdev->if_port; \ ++ if (!adapter->netdev->if_port) \ ++ netif_poll_disable(adapter->netdev); \ ++ } while (0) ++ ++#define netif_napi_add(_netdev, _napi, _poll, _weight) \ ++ do { \ ++ struct napi_struct *__napi = (_napi); \ ++ __napi->poll_dev.poll = &(__kc_adapter_clean); \ ++ __napi->poll_dev.priv = (_napi); \ ++ __napi->poll_dev.weight = (_weight); \ ++ dev_hold(&__napi->poll_dev); \ ++ set_bit(__LINK_STATE_START, &__napi->poll_dev.state);\ ++ _netdev->poll = &(__kc_adapter_clean); \ ++ _netdev->weight = (_weight); \ ++ __napi->poll = &(_poll); \ ++ __napi->weight = (_weight); \ ++ set_bit(__LINK_STATE_RX_SCHED, &(_netdev)->state); \ ++ set_bit(__LINK_STATE_RX_SCHED, &__napi->poll_dev.state); \ ++ } while (0) ++#define netif_napi_del(_napi) \ ++ do { \ ++ WARN_ON(!test_bit(__LINK_STATE_RX_SCHED, &(_napi)->poll_dev.state)); \ ++ dev_put(&(_napi)->poll_dev); \ ++ memset(&(_napi)->poll_dev, 0, sizeof(struct napi_struct));\ ++ } while (0) ++extern int _kc_napi_schedule_prep(struct napi_struct *napi); ++#define napi_schedule_prep _kc_napi_schedule_prep ++#define napi_schedule(napi) netif_rx_schedule(napi_to_poll_dev(napi)) ++#define __napi_schedule(napi) __netif_rx_schedule(napi_to_poll_dev(napi)) ++#define napi_complete(napi) netif_rx_complete(napi_to_poll_dev(napi)) ++#else /* NAPI */ ++#define netif_napi_add(_netdev, _napi, _poll, _weight) \ ++ do { \ ++ struct napi_struct *__napi = _napi; \ ++ _netdev->poll = &(_poll); \ ++ _netdev->weight = (_weight); \ ++ __napi->poll = &(_poll); \ ++ __napi->weight = (_weight); \ ++ } while (0) ++#define netif_napi_del(_a) do {} while (0) ++#endif /* NAPI */ ++ ++#undef dev_get_by_name ++#define dev_get_by_name(_a, _b) dev_get_by_name(_b) ++#define __netif_subqueue_stopped(_a, _b) netif_subqueue_stopped(_a, _b) ++#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) ++#else /* < 2.6.24 */ ++#define HAVE_NETDEV_NAPI_LIST ++#endif /* < 2.6.24 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,24) ) ++#include ++#endif /* > 2.6.24 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) ) ++#define PM_QOS_CPU_DMA_LATENCY 1 ++ ++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18) ) ++#include ++#define PM_QOS_DEFAULT_VALUE INFINITE_LATENCY ++#define pm_qos_add_requirement(pm_qos_class, name, value) \ ++ set_acceptable_latency(name, value) ++#define pm_qos_remove_requirement(pm_qos_class, name) \ ++ remove_acceptable_latency(name) ++#define pm_qos_update_requirement(pm_qos_class, name, value) \ ++ modify_acceptable_latency(name, value) ++#else ++#define PM_QOS_DEFAULT_VALUE -1 ++#define pm_qos_add_requirement(pm_qos_class, name, value) ++#define pm_qos_remove_requirement(pm_qos_class, name) ++#define pm_qos_update_requirement(pm_qos_class, name, value) { \ ++ if (value != PM_QOS_DEFAULT_VALUE) { \ ++ printk(KERN_WARNING "%s: unable to set PM QoS requirement\n", \ ++ pci_name(adapter->pdev)); \ ++ } \ ++} ++#endif /* > 2.6.18 */ ++ ++#define pci_enable_device_mem(pdev) pci_enable_device(pdev) ++ ++#endif /* < 2.6.25 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) ) ++#else /* < 2.6.26 */ ++#include ++#define HAVE_NETDEV_VLAN_FEATURES ++#endif /* < 2.6.26 */ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) ) ++#if (((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) && defined(CONFIG_PM)) || ((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) && defined(CONFIG_PM_SLEEP))) ++#undef device_set_wakeup_enable ++#define device_set_wakeup_enable(dev, val) \ ++ do { \ ++ u16 pmc = 0; \ ++ int pm = pci_find_capability(adapter->pdev, PCI_CAP_ID_PM); \ ++ if (pm) { \ ++ pci_read_config_word(adapter->pdev, pm + PCI_PM_PMC, \ ++ &pmc); \ ++ } \ ++ (dev)->power.can_wakeup = !!(pmc >> 11); \ ++ (dev)->power.should_wakeup = (val && (pmc >> 11)); \ ++ } while (0) ++#endif /* 2.6.15-2.6.22 and CONFIG_PM or 2.6.23-2.6.25 and CONFIG_PM_SLEEP */ ++#endif /* 2.6.15 through 2.6.27 */ ++#ifndef netif_napi_del ++#define netif_napi_del(_a) do {} while (0) ++#ifdef NAPI ++#ifdef CONFIG_NETPOLL ++#undef netif_napi_del ++#define netif_napi_del(_a) list_del(&(_a)->dev_list); ++#endif ++#endif ++#endif /* netif_napi_del */ ++#ifndef pci_dma_mapping_error ++#define pci_dma_mapping_error(pdev, dma_addr) pci_dma_mapping_error(dma_addr) ++#endif ++ ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++#define HAVE_TX_MQ ++#endif ++ ++#ifdef HAVE_TX_MQ ++extern void _kc_netif_tx_stop_all_queues(struct net_device *); ++extern void _kc_netif_tx_wake_all_queues(struct net_device *); ++extern void _kc_netif_tx_start_all_queues(struct net_device *); ++#define netif_tx_stop_all_queues(a) _kc_netif_tx_stop_all_queues(a) ++#define netif_tx_wake_all_queues(a) _kc_netif_tx_wake_all_queues(a) ++#define netif_tx_start_all_queues(a) _kc_netif_tx_start_all_queues(a) ++#undef netif_stop_subqueue ++#define netif_stop_subqueue(_ndev,_qi) do { \ ++ if (netif_is_multiqueue((_ndev))) \ ++ netif_stop_subqueue((_ndev), (_qi)); \ ++ else \ ++ netif_stop_queue((_ndev)); \ ++ } while (0) ++#undef netif_start_subqueue ++#define netif_start_subqueue(_ndev,_qi) do { \ ++ if (netif_is_multiqueue((_ndev))) \ ++ netif_start_subqueue((_ndev), (_qi)); \ ++ else \ ++ netif_start_queue((_ndev)); \ ++ } while (0) ++#else /* HAVE_TX_MQ */ ++#define netif_tx_stop_all_queues(a) netif_stop_queue(a) ++#define netif_tx_wake_all_queues(a) netif_wake_queue(a) ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12) ) ++#define netif_tx_start_all_queues(a) netif_start_queue(a) ++#else ++#define netif_tx_start_all_queues(a) do {} while (0) ++#endif ++#define netif_stop_subqueue(_ndev,_qi) netif_stop_queue((_ndev)) ++#define netif_start_subqueue(_ndev,_qi) netif_start_queue((_ndev)) ++#endif /* HAVE_TX_MQ */ ++#ifndef NETIF_F_MULTI_QUEUE ++#define NETIF_F_MULTI_QUEUE 0 ++#define netif_is_multiqueue(a) 0 ++#define netif_wake_subqueue(a, b) ++#endif /* NETIF_F_MULTI_QUEUE */ ++#else /* < 2.6.27 */ ++#define HAVE_TX_MQ ++#define HAVE_NETDEV_SELECT_QUEUE ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) ++#define pci_ioremap_bar(pdev, bar) ioremap(pci_resource_start(pdev, bar), \ ++ pci_resource_len(pdev, bar)) ++#define pci_wake_from_d3 _kc_pci_wake_from_d3 ++#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep ++extern int _kc_pci_wake_from_d3(struct pci_dev *dev, bool enable); ++extern int _kc_pci_prepare_to_sleep(struct pci_dev *dev); ++#endif /* < 2.6.28 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) ) ++#define pci_request_selected_regions_exclusive(pdev, bars, name) \ ++ pci_request_selected_regions(pdev, bars, name) ++extern void _kc_pci_disable_link_state(struct pci_dev *dev, int state); ++#define pci_disable_link_state(p, s) _kc_pci_disable_link_state(p, s) ++#else /* < 2.6.29 */ ++#ifdef CONFIG_DCB ++#define HAVE_PFC_MODE_ENABLE ++#endif /* CONFIG_DCB */ ++#endif /* < 2.6.29 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ) ++#ifdef IXGBE_FCOE ++#undef CONFIG_FCOE ++#undef CONFIG_FCOE_MODULE ++#endif /* IXGBE_FCOE */ ++extern u16 _kc_skb_tx_hash(struct net_device *dev, struct sk_buff *skb); ++#define skb_tx_hash(n, s) _kc_skb_tx_hash(n, s) ++#else ++#define HAVE_ASPM_QUIRKS ++#endif /* < 2.6.30 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31) ) ++#else ++#ifndef HAVE_NETDEV_STORAGE_ADDRESS ++#define HAVE_NETDEV_STORAGE_ADDRESS ++#endif ++#endif /* < 2.6.31 */ ++#endif /* _KCOMPAT_H_ */ +diff -r 4f0f8bc35440 drivers/net/igb/kcompat_ethtool.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/igb/kcompat_ethtool.c Wed Aug 05 11:03:37 2009 +0100 +@@ -0,0 +1,1168 @@ ++/******************************************************************************* ++ ++ Intel(R) Gigabit Ethernet Linux driver ++ Copyright(c) 2007-2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * net/core/ethtool.c - Ethtool ioctl handler ++ * Copyright (c) 2003 Matthew Wilcox ++ * ++ * This file is where we call all the ethtool_ops commands to get ++ * the information ethtool needs. We fall back to calling do_ioctl() ++ * for drivers which haven't been converted to ethtool_ops yet. ++ * ++ * It's GPL, stupid. ++ * ++ * Modification by sfeldma@pobox.com to work as backward compat ++ * solution for pre-ethtool_ops kernels. ++ * - copied struct ethtool_ops from ethtool.h ++ * - defined SET_ETHTOOL_OPS ++ * - put in some #ifndef NETIF_F_xxx wrappers ++ * - changes refs to dev->ethtool_ops to ethtool_ops ++ * - changed dev_ethtool to ethtool_ioctl ++ * - remove EXPORT_SYMBOL()s ++ * - added _kc_ prefix in built-in ethtool_op_xxx ops. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "kcompat.h" ++ ++#undef SUPPORTED_10000baseT_Full ++#define SUPPORTED_10000baseT_Full (1 << 12) ++#undef ADVERTISED_10000baseT_Full ++#define ADVERTISED_10000baseT_Full (1 << 12) ++#undef SPEED_10000 ++#define SPEED_10000 10000 ++ ++#undef ethtool_ops ++#define ethtool_ops _kc_ethtool_ops ++ ++struct _kc_ethtool_ops { ++ int (*get_settings)(struct net_device *, struct ethtool_cmd *); ++ int (*set_settings)(struct net_device *, struct ethtool_cmd *); ++ void (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *); ++ int (*get_regs_len)(struct net_device *); ++ void (*get_regs)(struct net_device *, struct ethtool_regs *, void *); ++ void (*get_wol)(struct net_device *, struct ethtool_wolinfo *); ++ int (*set_wol)(struct net_device *, struct ethtool_wolinfo *); ++ u32 (*get_msglevel)(struct net_device *); ++ void (*set_msglevel)(struct net_device *, u32); ++ int (*nway_reset)(struct net_device *); ++ u32 (*get_link)(struct net_device *); ++ int (*get_eeprom_len)(struct net_device *); ++ int (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); ++ int (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); ++ int (*get_coalesce)(struct net_device *, struct ethtool_coalesce *); ++ int (*set_coalesce)(struct net_device *, struct ethtool_coalesce *); ++ void (*get_ringparam)(struct net_device *, struct ethtool_ringparam *); ++ int (*set_ringparam)(struct net_device *, struct ethtool_ringparam *); ++ void (*get_pauseparam)(struct net_device *, ++ struct ethtool_pauseparam*); ++ int (*set_pauseparam)(struct net_device *, ++ struct ethtool_pauseparam*); ++ u32 (*get_rx_csum)(struct net_device *); ++ int (*set_rx_csum)(struct net_device *, u32); ++ u32 (*get_tx_csum)(struct net_device *); ++ int (*set_tx_csum)(struct net_device *, u32); ++ u32 (*get_sg)(struct net_device *); ++ int (*set_sg)(struct net_device *, u32); ++ u32 (*get_tso)(struct net_device *); ++ int (*set_tso)(struct net_device *, u32); ++ int (*self_test_count)(struct net_device *); ++ void (*self_test)(struct net_device *, struct ethtool_test *, u64 *); ++ void (*get_strings)(struct net_device *, u32 stringset, u8 *); ++ int (*phys_id)(struct net_device *, u32); ++ int (*get_stats_count)(struct net_device *); ++ void (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, ++ u64 *); ++} *ethtool_ops = NULL; ++ ++#undef SET_ETHTOOL_OPS ++#define SET_ETHTOOL_OPS(netdev, ops) (ethtool_ops = (ops)) ++ ++/* ++ * Some useful ethtool_ops methods that are device independent. If we find that ++ * all drivers want to do the same thing here, we can turn these into dev_() ++ * function calls. ++ */ ++ ++#undef ethtool_op_get_link ++#define ethtool_op_get_link _kc_ethtool_op_get_link ++u32 _kc_ethtool_op_get_link(struct net_device *dev) ++{ ++ return netif_carrier_ok(dev) ? 1 : 0; ++} ++ ++#undef ethtool_op_get_tx_csum ++#define ethtool_op_get_tx_csum _kc_ethtool_op_get_tx_csum ++u32 _kc_ethtool_op_get_tx_csum(struct net_device *dev) ++{ ++#ifdef NETIF_F_IP_CSUM ++ return (dev->features & NETIF_F_IP_CSUM) != 0; ++#else ++ return 0; ++#endif ++} ++ ++#undef ethtool_op_set_tx_csum ++#define ethtool_op_set_tx_csum _kc_ethtool_op_set_tx_csum ++int _kc_ethtool_op_set_tx_csum(struct net_device *dev, u32 data) ++{ ++#ifdef NETIF_F_IP_CSUM ++ if (data) ++#ifdef NETIF_F_IPV6_CSUM ++ dev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); ++ else ++ dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); ++#else ++ dev->features |= NETIF_F_IP_CSUM; ++ else ++ dev->features &= ~NETIF_F_IP_CSUM; ++#endif ++#endif ++ ++ return 0; ++} ++ ++#undef ethtool_op_get_sg ++#define ethtool_op_get_sg _kc_ethtool_op_get_sg ++u32 _kc_ethtool_op_get_sg(struct net_device *dev) ++{ ++#ifdef NETIF_F_SG ++ return (dev->features & NETIF_F_SG) != 0; ++#else ++ return 0; ++#endif ++} ++ ++#undef ethtool_op_set_sg ++#define ethtool_op_set_sg _kc_ethtool_op_set_sg ++int _kc_ethtool_op_set_sg(struct net_device *dev, u32 data) ++{ ++#ifdef NETIF_F_SG ++ if (data) ++ dev->features |= NETIF_F_SG; ++ else ++ dev->features &= ~NETIF_F_SG; ++#endif ++ ++ return 0; ++} ++ ++#undef ethtool_op_get_tso ++#define ethtool_op_get_tso _kc_ethtool_op_get_tso ++u32 _kc_ethtool_op_get_tso(struct net_device *dev) ++{ ++#ifdef NETIF_F_TSO ++ return (dev->features & NETIF_F_TSO) != 0; ++#else ++ return 0; ++#endif ++} ++ ++#undef ethtool_op_set_tso ++#define ethtool_op_set_tso _kc_ethtool_op_set_tso ++int _kc_ethtool_op_set_tso(struct net_device *dev, u32 data) ++{ ++#ifdef NETIF_F_TSO ++ if (data) ++ dev->features |= NETIF_F_TSO; ++ else ++ dev->features &= ~NETIF_F_TSO; ++#endif ++ ++ return 0; ++} ++ ++/* Handlers for each ethtool command */ ++ ++static int ethtool_get_settings(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_cmd cmd = { ETHTOOL_GSET }; ++ int err; ++ ++ if (!ethtool_ops->get_settings) ++ return -EOPNOTSUPP; ++ ++ err = ethtool_ops->get_settings(dev, &cmd); ++ if (err < 0) ++ return err; ++ ++ if (copy_to_user(useraddr, &cmd, sizeof(cmd))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_settings(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_cmd cmd; ++ ++ if (!ethtool_ops->set_settings) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&cmd, useraddr, sizeof(cmd))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_settings(dev, &cmd); ++} ++ ++static int ethtool_get_drvinfo(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_drvinfo info; ++ struct ethtool_ops *ops = ethtool_ops; ++ ++ if (!ops->get_drvinfo) ++ return -EOPNOTSUPP; ++ ++ memset(&info, 0, sizeof(info)); ++ info.cmd = ETHTOOL_GDRVINFO; ++ ops->get_drvinfo(dev, &info); ++ ++ if (ops->self_test_count) ++ info.testinfo_len = ops->self_test_count(dev); ++ if (ops->get_stats_count) ++ info.n_stats = ops->get_stats_count(dev); ++ if (ops->get_regs_len) ++ info.regdump_len = ops->get_regs_len(dev); ++ if (ops->get_eeprom_len) ++ info.eedump_len = ops->get_eeprom_len(dev); ++ ++ if (copy_to_user(useraddr, &info, sizeof(info))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_get_regs(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_regs regs; ++ struct ethtool_ops *ops = ethtool_ops; ++ void *regbuf; ++ int reglen, ret; ++ ++ if (!ops->get_regs || !ops->get_regs_len) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(®s, useraddr, sizeof(regs))) ++ return -EFAULT; ++ ++ reglen = ops->get_regs_len(dev); ++ if (regs.len > reglen) ++ regs.len = reglen; ++ ++ regbuf = kmalloc(reglen, GFP_USER); ++ if (!regbuf) ++ return -ENOMEM; ++ ++ ops->get_regs(dev, ®s, regbuf); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, ®s, sizeof(regs))) ++ goto out; ++ useraddr += offsetof(struct ethtool_regs, data); ++ if (copy_to_user(useraddr, regbuf, reglen)) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(regbuf); ++ return ret; ++} ++ ++static int ethtool_get_wol(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_wolinfo wol = { ETHTOOL_GWOL }; ++ ++ if (!ethtool_ops->get_wol) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_wol(dev, &wol); ++ ++ if (copy_to_user(useraddr, &wol, sizeof(wol))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_wol(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_wolinfo wol; ++ ++ if (!ethtool_ops->set_wol) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&wol, useraddr, sizeof(wol))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_wol(dev, &wol); ++} ++ ++static int ethtool_get_msglevel(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GMSGLVL }; ++ ++ if (!ethtool_ops->get_msglevel) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_msglevel(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_msglevel(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_msglevel) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ ethtool_ops->set_msglevel(dev, edata.data); ++ return 0; ++} ++ ++static int ethtool_nway_reset(struct net_device *dev) ++{ ++ if (!ethtool_ops->nway_reset) ++ return -EOPNOTSUPP; ++ ++ return ethtool_ops->nway_reset(dev); ++} ++ ++static int ethtool_get_link(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ ++ if (!ethtool_ops->get_link) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_link(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_get_eeprom(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_eeprom eeprom; ++ struct ethtool_ops *ops = ethtool_ops; ++ u8 *data; ++ int ret; ++ ++ if (!ops->get_eeprom || !ops->get_eeprom_len) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) ++ return -EFAULT; ++ ++ /* Check for wrap and zero */ ++ if (eeprom.offset + eeprom.len <= eeprom.offset) ++ return -EINVAL; ++ ++ /* Check for exceeding total eeprom len */ ++ if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev)) ++ return -EINVAL; ++ ++ data = kmalloc(eeprom.len, GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ret = -EFAULT; ++ if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len)) ++ goto out; ++ ++ ret = ops->get_eeprom(dev, &eeprom, data); ++ if (ret) ++ goto out; ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &eeprom, sizeof(eeprom))) ++ goto out; ++ if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len)) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_set_eeprom(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_eeprom eeprom; ++ struct ethtool_ops *ops = ethtool_ops; ++ u8 *data; ++ int ret; ++ ++ if (!ops->set_eeprom || !ops->get_eeprom_len) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) ++ return -EFAULT; ++ ++ /* Check for wrap and zero */ ++ if (eeprom.offset + eeprom.len <= eeprom.offset) ++ return -EINVAL; ++ ++ /* Check for exceeding total eeprom len */ ++ if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev)) ++ return -EINVAL; ++ ++ data = kmalloc(eeprom.len, GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ret = -EFAULT; ++ if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len)) ++ goto out; ++ ++ ret = ops->set_eeprom(dev, &eeprom, data); ++ if (ret) ++ goto out; ++ ++ if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len)) ++ ret = -EFAULT; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_get_coalesce(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_coalesce coalesce = { ETHTOOL_GCOALESCE }; ++ ++ if (!ethtool_ops->get_coalesce) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_coalesce(dev, &coalesce); ++ ++ if (copy_to_user(useraddr, &coalesce, sizeof(coalesce))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_coalesce(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_coalesce coalesce; ++ ++ if (!ethtool_ops->get_coalesce) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&coalesce, useraddr, sizeof(coalesce))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_coalesce(dev, &coalesce); ++} ++ ++static int ethtool_get_ringparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_ringparam ringparam = { ETHTOOL_GRINGPARAM }; ++ ++ if (!ethtool_ops->get_ringparam) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_ringparam(dev, &ringparam); ++ ++ if (copy_to_user(useraddr, &ringparam, sizeof(ringparam))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_ringparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_ringparam ringparam; ++ ++ if (!ethtool_ops->get_ringparam) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&ringparam, useraddr, sizeof(ringparam))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_ringparam(dev, &ringparam); ++} ++ ++static int ethtool_get_pauseparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_pauseparam pauseparam = { ETHTOOL_GPAUSEPARAM }; ++ ++ if (!ethtool_ops->get_pauseparam) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_pauseparam(dev, &pauseparam); ++ ++ if (copy_to_user(useraddr, &pauseparam, sizeof(pauseparam))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_pauseparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_pauseparam pauseparam; ++ ++ if (!ethtool_ops->get_pauseparam) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&pauseparam, useraddr, sizeof(pauseparam))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_pauseparam(dev, &pauseparam); ++} ++ ++static int ethtool_get_rx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GRXCSUM }; ++ ++ if (!ethtool_ops->get_rx_csum) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_rx_csum(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_rx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_rx_csum) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ ethtool_ops->set_rx_csum(dev, edata.data); ++ return 0; ++} ++ ++static int ethtool_get_tx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GTXCSUM }; ++ ++ if (!ethtool_ops->get_tx_csum) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_tx_csum(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_tx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_tx_csum) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_tx_csum(dev, edata.data); ++} ++ ++static int ethtool_get_sg(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GSG }; ++ ++ if (!ethtool_ops->get_sg) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_sg(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_sg(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_sg) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_sg(dev, edata.data); ++} ++ ++static int ethtool_get_tso(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GTSO }; ++ ++ if (!ethtool_ops->get_tso) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_tso(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_tso(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_tso) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_tso(dev, edata.data); ++} ++ ++static int ethtool_self_test(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_test test; ++ struct ethtool_ops *ops = ethtool_ops; ++ u64 *data; ++ int ret; ++ ++ if (!ops->self_test || !ops->self_test_count) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&test, useraddr, sizeof(test))) ++ return -EFAULT; ++ ++ test.len = ops->self_test_count(dev); ++ data = kmalloc(test.len * sizeof(u64), GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ops->self_test(dev, &test, data); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &test, sizeof(test))) ++ goto out; ++ useraddr += sizeof(test); ++ if (copy_to_user(useraddr, data, test.len * sizeof(u64))) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_get_strings(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_gstrings gstrings; ++ struct ethtool_ops *ops = ethtool_ops; ++ u8 *data; ++ int ret; ++ ++ if (!ops->get_strings) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&gstrings, useraddr, sizeof(gstrings))) ++ return -EFAULT; ++ ++ switch (gstrings.string_set) { ++ case ETH_SS_TEST: ++ if (!ops->self_test_count) ++ return -EOPNOTSUPP; ++ gstrings.len = ops->self_test_count(dev); ++ break; ++ case ETH_SS_STATS: ++ if (!ops->get_stats_count) ++ return -EOPNOTSUPP; ++ gstrings.len = ops->get_stats_count(dev); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ data = kmalloc(gstrings.len * ETH_GSTRING_LEN, GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ops->get_strings(dev, gstrings.string_set, data); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &gstrings, sizeof(gstrings))) ++ goto out; ++ useraddr += sizeof(gstrings); ++ if (copy_to_user(useraddr, data, gstrings.len * ETH_GSTRING_LEN)) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_phys_id(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_value id; ++ ++ if (!ethtool_ops->phys_id) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&id, useraddr, sizeof(id))) ++ return -EFAULT; ++ ++ return ethtool_ops->phys_id(dev, id.data); ++} ++ ++static int ethtool_get_stats(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_stats stats; ++ struct ethtool_ops *ops = ethtool_ops; ++ u64 *data; ++ int ret; ++ ++ if (!ops->get_ethtool_stats || !ops->get_stats_count) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&stats, useraddr, sizeof(stats))) ++ return -EFAULT; ++ ++ stats.n_stats = ops->get_stats_count(dev); ++ data = kmalloc(stats.n_stats * sizeof(u64), GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ops->get_ethtool_stats(dev, &stats, data); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &stats, sizeof(stats))) ++ goto out; ++ useraddr += sizeof(stats); ++ if (copy_to_user(useraddr, data, stats.n_stats * sizeof(u64))) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++/* The main entry point in this file. Called from net/core/dev.c */ ++ ++#define ETHTOOL_OPS_COMPAT ++int ethtool_ioctl(struct ifreq *ifr) ++{ ++ struct net_device *dev = __dev_get_by_name(ifr->ifr_name); ++ void *useraddr = (void *) ifr->ifr_data; ++ u32 ethcmd; ++ ++ /* ++ * XXX: This can be pushed down into the ethtool_* handlers that ++ * need it. Keep existing behavior for the moment. ++ */ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++ if (!dev || !netif_device_present(dev)) ++ return -ENODEV; ++ ++ if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd))) ++ return -EFAULT; ++ ++ switch (ethcmd) { ++ case ETHTOOL_GSET: ++ return ethtool_get_settings(dev, useraddr); ++ case ETHTOOL_SSET: ++ return ethtool_set_settings(dev, useraddr); ++ case ETHTOOL_GDRVINFO: ++ return ethtool_get_drvinfo(dev, useraddr); ++ case ETHTOOL_GREGS: ++ return ethtool_get_regs(dev, useraddr); ++ case ETHTOOL_GWOL: ++ return ethtool_get_wol(dev, useraddr); ++ case ETHTOOL_SWOL: ++ return ethtool_set_wol(dev, useraddr); ++ case ETHTOOL_GMSGLVL: ++ return ethtool_get_msglevel(dev, useraddr); ++ case ETHTOOL_SMSGLVL: ++ return ethtool_set_msglevel(dev, useraddr); ++ case ETHTOOL_NWAY_RST: ++ return ethtool_nway_reset(dev); ++ case ETHTOOL_GLINK: ++ return ethtool_get_link(dev, useraddr); ++ case ETHTOOL_GEEPROM: ++ return ethtool_get_eeprom(dev, useraddr); ++ case ETHTOOL_SEEPROM: ++ return ethtool_set_eeprom(dev, useraddr); ++ case ETHTOOL_GCOALESCE: ++ return ethtool_get_coalesce(dev, useraddr); ++ case ETHTOOL_SCOALESCE: ++ return ethtool_set_coalesce(dev, useraddr); ++ case ETHTOOL_GRINGPARAM: ++ return ethtool_get_ringparam(dev, useraddr); ++ case ETHTOOL_SRINGPARAM: ++ return ethtool_set_ringparam(dev, useraddr); ++ case ETHTOOL_GPAUSEPARAM: ++ return ethtool_get_pauseparam(dev, useraddr); ++ case ETHTOOL_SPAUSEPARAM: ++ return ethtool_set_pauseparam(dev, useraddr); ++ case ETHTOOL_GRXCSUM: ++ return ethtool_get_rx_csum(dev, useraddr); ++ case ETHTOOL_SRXCSUM: ++ return ethtool_set_rx_csum(dev, useraddr); ++ case ETHTOOL_GTXCSUM: ++ return ethtool_get_tx_csum(dev, useraddr); ++ case ETHTOOL_STXCSUM: ++ return ethtool_set_tx_csum(dev, useraddr); ++ case ETHTOOL_GSG: ++ return ethtool_get_sg(dev, useraddr); ++ case ETHTOOL_SSG: ++ return ethtool_set_sg(dev, useraddr); ++ case ETHTOOL_GTSO: ++ return ethtool_get_tso(dev, useraddr); ++ case ETHTOOL_STSO: ++ return ethtool_set_tso(dev, useraddr); ++ case ETHTOOL_TEST: ++ return ethtool_self_test(dev, useraddr); ++ case ETHTOOL_GSTRINGS: ++ return ethtool_get_strings(dev, useraddr); ++ case ETHTOOL_PHYS_ID: ++ return ethtool_phys_id(dev, useraddr); ++ case ETHTOOL_GSTATS: ++ return ethtool_get_stats(dev, useraddr); ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return -EOPNOTSUPP; ++} ++ ++#define mii_if_info _kc_mii_if_info ++struct _kc_mii_if_info { ++ int phy_id; ++ int advertising; ++ int phy_id_mask; ++ int reg_num_mask; ++ ++ unsigned int full_duplex : 1; /* is full duplex? */ ++ unsigned int force_media : 1; /* is autoneg. disabled? */ ++ ++ struct net_device *dev; ++ int (*mdio_read) (struct net_device *dev, int phy_id, int location); ++ void (*mdio_write) (struct net_device *dev, int phy_id, int location, int val); ++}; ++ ++struct ethtool_cmd; ++struct mii_ioctl_data; ++ ++#undef mii_link_ok ++#define mii_link_ok _kc_mii_link_ok ++#undef mii_nway_restart ++#define mii_nway_restart _kc_mii_nway_restart ++#undef mii_ethtool_gset ++#define mii_ethtool_gset _kc_mii_ethtool_gset ++#undef mii_ethtool_sset ++#define mii_ethtool_sset _kc_mii_ethtool_sset ++#undef mii_check_link ++#define mii_check_link _kc_mii_check_link ++#undef generic_mii_ioctl ++#define generic_mii_ioctl _kc_generic_mii_ioctl ++extern int _kc_mii_link_ok (struct mii_if_info *mii); ++extern int _kc_mii_nway_restart (struct mii_if_info *mii); ++extern int _kc_mii_ethtool_gset(struct mii_if_info *mii, ++ struct ethtool_cmd *ecmd); ++extern int _kc_mii_ethtool_sset(struct mii_if_info *mii, ++ struct ethtool_cmd *ecmd); ++extern void _kc_mii_check_link (struct mii_if_info *mii); ++extern int _kc_generic_mii_ioctl(struct mii_if_info *mii_if, ++ struct mii_ioctl_data *mii_data, int cmd, ++ unsigned int *duplex_changed); ++ ++ ++struct _kc_pci_dev_ext { ++ struct pci_dev *dev; ++ void *pci_drvdata; ++ struct pci_driver *driver; ++}; ++ ++struct _kc_net_dev_ext { ++ struct net_device *dev; ++ unsigned int carrier; ++}; ++ ++ ++/**************************************/ ++/* mii support */ ++ ++int _kc_mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) ++{ ++ struct net_device *dev = mii->dev; ++ u32 advert, bmcr, lpa, nego; ++ ++ ecmd->supported = ++ (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | ++ SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | ++ SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII); ++ ++ /* only supports twisted-pair */ ++ ecmd->port = PORT_MII; ++ ++ /* only supports internal transceiver */ ++ ecmd->transceiver = XCVR_INTERNAL; ++ ++ /* this isn't fully supported at higher layers */ ++ ecmd->phy_address = mii->phy_id; ++ ++ ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII; ++ advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE); ++ if (advert & ADVERTISE_10HALF) ++ ecmd->advertising |= ADVERTISED_10baseT_Half; ++ if (advert & ADVERTISE_10FULL) ++ ecmd->advertising |= ADVERTISED_10baseT_Full; ++ if (advert & ADVERTISE_100HALF) ++ ecmd->advertising |= ADVERTISED_100baseT_Half; ++ if (advert & ADVERTISE_100FULL) ++ ecmd->advertising |= ADVERTISED_100baseT_Full; ++ ++ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); ++ lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA); ++ if (bmcr & BMCR_ANENABLE) { ++ ecmd->advertising |= ADVERTISED_Autoneg; ++ ecmd->autoneg = AUTONEG_ENABLE; ++ ++ nego = mii_nway_result(advert & lpa); ++ if (nego == LPA_100FULL || nego == LPA_100HALF) ++ ecmd->speed = SPEED_100; ++ else ++ ecmd->speed = SPEED_10; ++ if (nego == LPA_100FULL || nego == LPA_10FULL) { ++ ecmd->duplex = DUPLEX_FULL; ++ mii->full_duplex = 1; ++ } else { ++ ecmd->duplex = DUPLEX_HALF; ++ mii->full_duplex = 0; ++ } ++ } else { ++ ecmd->autoneg = AUTONEG_DISABLE; ++ ++ ecmd->speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; ++ ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; ++ } ++ ++ /* ignore maxtxpkt, maxrxpkt for now */ ++ ++ return 0; ++} ++ ++int _kc_mii_ethtool_sset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) ++{ ++ struct net_device *dev = mii->dev; ++ ++ if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) ++ return -EINVAL; ++ if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) ++ return -EINVAL; ++ if (ecmd->port != PORT_MII) ++ return -EINVAL; ++ if (ecmd->transceiver != XCVR_INTERNAL) ++ return -EINVAL; ++ if (ecmd->phy_address != mii->phy_id) ++ return -EINVAL; ++ if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE) ++ return -EINVAL; ++ ++ /* ignore supported, maxtxpkt, maxrxpkt */ ++ ++ if (ecmd->autoneg == AUTONEG_ENABLE) { ++ u32 bmcr, advert, tmp; ++ ++ if ((ecmd->advertising & (ADVERTISED_10baseT_Half | ++ ADVERTISED_10baseT_Full | ++ ADVERTISED_100baseT_Half | ++ ADVERTISED_100baseT_Full)) == 0) ++ return -EINVAL; ++ ++ /* advertise only what has been requested */ ++ advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE); ++ tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4); ++ if (ADVERTISED_10baseT_Half) ++ tmp |= ADVERTISE_10HALF; ++ if (ADVERTISED_10baseT_Full) ++ tmp |= ADVERTISE_10FULL; ++ if (ADVERTISED_100baseT_Half) ++ tmp |= ADVERTISE_100HALF; ++ if (ADVERTISED_100baseT_Full) ++ tmp |= ADVERTISE_100FULL; ++ if (advert != tmp) { ++ mii->mdio_write(dev, mii->phy_id, MII_ADVERTISE, tmp); ++ mii->advertising = tmp; ++ } ++ ++ /* turn on autonegotiation, and force a renegotiate */ ++ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); ++ bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); ++ mii->mdio_write(dev, mii->phy_id, MII_BMCR, bmcr); ++ ++ mii->force_media = 0; ++ } else { ++ u32 bmcr, tmp; ++ ++ /* turn off auto negotiation, set speed and duplexity */ ++ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); ++ tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX); ++ if (ecmd->speed == SPEED_100) ++ tmp |= BMCR_SPEED100; ++ if (ecmd->duplex == DUPLEX_FULL) { ++ tmp |= BMCR_FULLDPLX; ++ mii->full_duplex = 1; ++ } else ++ mii->full_duplex = 0; ++ if (bmcr != tmp) ++ mii->mdio_write(dev, mii->phy_id, MII_BMCR, tmp); ++ ++ mii->force_media = 1; ++ } ++ return 0; ++} ++ ++int _kc_mii_link_ok (struct mii_if_info *mii) ++{ ++ /* first, a dummy read, needed to latch some MII phys */ ++ mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); ++ if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS) ++ return 1; ++ return 0; ++} ++ ++int _kc_mii_nway_restart (struct mii_if_info *mii) ++{ ++ int bmcr; ++ int r = -EINVAL; ++ ++ /* if autoneg is off, it's an error */ ++ bmcr = mii->mdio_read(mii->dev, mii->phy_id, MII_BMCR); ++ ++ if (bmcr & BMCR_ANENABLE) { ++ bmcr |= BMCR_ANRESTART; ++ mii->mdio_write(mii->dev, mii->phy_id, MII_BMCR, bmcr); ++ r = 0; ++ } ++ ++ return r; ++} ++ ++void _kc_mii_check_link (struct mii_if_info *mii) ++{ ++ int cur_link = mii_link_ok(mii); ++ int prev_link = netif_carrier_ok(mii->dev); ++ ++ if (cur_link && !prev_link) ++ netif_carrier_on(mii->dev); ++ else if (prev_link && !cur_link) ++ netif_carrier_off(mii->dev); ++} ++ ++int _kc_generic_mii_ioctl(struct mii_if_info *mii_if, ++ struct mii_ioctl_data *mii_data, int cmd, ++ unsigned int *duplex_chg_out) ++{ ++ int rc = 0; ++ unsigned int duplex_changed = 0; ++ ++ if (duplex_chg_out) ++ *duplex_chg_out = 0; ++ ++ mii_data->phy_id &= mii_if->phy_id_mask; ++ mii_data->reg_num &= mii_if->reg_num_mask; ++ ++ switch(cmd) { ++ case SIOCDEVPRIVATE: /* binary compat, remove in 2.5 */ ++ case SIOCGMIIPHY: ++ mii_data->phy_id = mii_if->phy_id; ++ /* fall through */ ++ ++ case SIOCDEVPRIVATE + 1:/* binary compat, remove in 2.5 */ ++ case SIOCGMIIREG: ++ mii_data->val_out = ++ mii_if->mdio_read(mii_if->dev, mii_data->phy_id, ++ mii_data->reg_num); ++ break; ++ ++ case SIOCDEVPRIVATE + 2:/* binary compat, remove in 2.5 */ ++ case SIOCSMIIREG: { ++ u16 val = mii_data->val_in; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++ if (mii_data->phy_id == mii_if->phy_id) { ++ switch(mii_data->reg_num) { ++ case MII_BMCR: { ++ unsigned int new_duplex = 0; ++ if (val & (BMCR_RESET|BMCR_ANENABLE)) ++ mii_if->force_media = 0; ++ else ++ mii_if->force_media = 1; ++ if (mii_if->force_media && ++ (val & BMCR_FULLDPLX)) ++ new_duplex = 1; ++ if (mii_if->full_duplex != new_duplex) { ++ duplex_changed = 1; ++ mii_if->full_duplex = new_duplex; ++ } ++ break; ++ } ++ case MII_ADVERTISE: ++ mii_if->advertising = val; ++ break; ++ default: ++ /* do nothing */ ++ break; ++ } ++ } ++ ++ mii_if->mdio_write(mii_if->dev, mii_data->phy_id, ++ mii_data->reg_num, val); ++ break; ++ } ++ ++ default: ++ rc = -EOPNOTSUPP; ++ break; ++ } ++ ++ if ((rc == 0) && (duplex_chg_out) && (duplex_changed)) ++ *duplex_chg_out = 1; ++ ++ return rc; ++} ++ diff --git a/master/increase-maximum-number-of-loop-devices b/master/increase-maximum-number-of-loop-devices new file mode 100644 index 0000000..8ae6fe7 --- /dev/null +++ b/master/increase-maximum-number-of-loop-devices @@ -0,0 +1,12 @@ +diff -r 1d03d2b8f9f3 drivers/block/loop.c +--- a/drivers/block/loop.c Sat Sep 05 13:06:44 2009 +0100 ++++ b/drivers/block/loop.c Wed Sep 16 17:39:57 2009 +0100 +@@ -1525,7 +1525,7 @@ + nr = max_loop; + range = max_loop; + } else { +- nr = 8; ++ nr = 128; + range = 1UL << (MINORBITS - part_shift); + } + diff --git a/master/intel-net-driver-conflicting-names.patch b/master/intel-net-driver-conflicting-names.patch index 6be2b13..9032d48 100644 --- a/master/intel-net-driver-conflicting-names.patch +++ b/master/intel-net-driver-conflicting-names.patch @@ -1,3 +1,31 @@ +The following symbols are present in both e1000 and e1000e: + _kc_pci_wake_from_d3 + e1000_check_alt_mac_addr_generic + e1000_check_mng_mode_generic + e1000_check_polarity_ife + e1000_check_polarity_igp + e1000_check_polarity_m88 + e1000_init_mac_ops_generic + e1000_init_nvm_ops_generic + e1000_mng_enable_host_if_generic + e1000_mng_host_if_write_generic + e1000_mng_write_cmd_header_generic + e1000_mta_set_generic + e1000_phy_force_speed_duplex_ife + e1000_phy_init_script_igp3 + e1000_power_down_phy_copper + e1000_power_up_phy_copper + e1000_read_pcie_cap_reg + e1000_set_lan_id_single_port + e1000_setup_led_generic + e1000_wait_autoneg + +sed -e 's/e1000_\(check_alt_mac_addr_generic\|check_mng_mode_generic\|check_polarity_ife\|check_polarity_igp\|check_polarity_m88\|init_mac_ops_generic\|init_nvm_ops_generic\|mng_enable_host_if_generic\|mng_host_if_write_generic\|mng_write_cmd_header_generic\|mta_set_generic\|phy_force_speed_duplex_ife\|phy_init_script_igp3\|power_down_phy_copper\|power_up_phy_copper\|read_pcie_cap_reg\|set_lan_id_single_port\|setup_led_generic\|wait_autoneg\)/e1000e_\1/g' -i drivers/net/e1000e/* + +for i in e1000 e1000e igx ixgbe ; do + sed -e "s/_kc_pci_wake_from_d3/_kc_$i_pci_wake_from_d3/g" -i drivers/net/$i/* +done + diff --git a/drivers/net/e1000e/e1000_80003es2lan.c b/drivers/net/e1000e/e1000_80003es2lan.c --- a/drivers/net/e1000e/e1000_80003es2lan.c +++ b/drivers/net/e1000e/e1000_80003es2lan.c @@ -72,20 +100,21 @@ diff --git a/drivers/net/e1000e/e1000_80003es2lan.c b/drivers/net/e1000e/e1000_8 ew32(IMC, 0xffffffff); icr = er32(ICR); -- e1000_check_alt_mac_addr_generic(hw); -+ e1000e_check_alt_mac_addr_generic(hw); +- ret_val = e1000_check_alt_mac_addr_generic(hw); ++ ret_val = e1000e_check_alt_mac_addr_generic(hw); out: return ret_val; -@@ -1395,25 +1395,25 @@ - { - s32 ret_val = E1000_SUCCESS; - -- if (e1000_check_alt_mac_addr_generic(hw)) -+ if (e1000e_check_alt_mac_addr_generic(hw)) - ret_val = e1000e_read_mac_addr_generic(hw); +@@ -1400,7 +1400,7 @@ + * so that it will override the Si installed default perm + * address. + */ +- ret_val = e1000_check_alt_mac_addr_generic(hw); ++ ret_val = e1000e_check_alt_mac_addr_generic(hw); + if (ret_val) + goto out; - return ret_val; +@@ -1411,18 +1411,18 @@ } /** @@ -110,7 +139,7 @@ diff --git a/drivers/net/e1000e/e1000_80003es2lan.c b/drivers/net/e1000e/e1000_8 diff --git a/drivers/net/e1000e/e1000_82571.c b/drivers/net/e1000e/e1000_82571.c --- a/drivers/net/e1000e/e1000_82571.c +++ b/drivers/net/e1000e/e1000_82571.c -@@ -80,7 +80,7 @@ +@@ -77,7 +77,7 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); @@ -119,7 +148,7 @@ diff --git a/drivers/net/e1000e/e1000_82571.c b/drivers/net/e1000e/e1000_82571.c /** * e1000_init_phy_params_82571 - Init PHY func ptrs. -@@ -101,14 +101,14 @@ +@@ -98,14 +98,14 @@ phy->reset_delay_us = 100; phy->ops.acquire = e1000_get_hw_semaphore_82571; @@ -173,7 +202,7 @@ diff --git a/drivers/net/e1000e/e1000_82571.c b/drivers/net/e1000e/e1000_82571.c /* cleanup LED */ mac->ops.cleanup_led = e1000e_cleanup_led_generic; /* turn on/off LED */ -@@ -390,8 +390,8 @@ +@@ -434,8 +434,8 @@ **/ void e1000_init_function_pointers_82571(struct e1000_hw *hw) { @@ -184,24 +213,25 @@ diff --git a/drivers/net/e1000e/e1000_82571.c b/drivers/net/e1000e/e1000_82571.c hw->mac.ops.init_params = e1000_init_mac_params_82571; hw->nvm.ops.init_params = e1000_init_nvm_params_82571; hw->phy.ops.init_params = e1000_init_phy_params_82571; -@@ -918,7 +918,7 @@ - ew32(IMC, 0xffffffff); +@@ -989,7 +989,7 @@ icr = er32(ICR); -- if (!(e1000_check_alt_mac_addr_generic(hw))) -+ if (!(e1000e_check_alt_mac_addr_generic(hw))) - e1000e_set_laa_state_82571(hw, true); - - /* Reinitialize the 82571 serdes link state machine */ -@@ -1617,20 +1617,20 @@ - { - s32 ret_val = E1000_SUCCESS; + /* Install any alternate MAC address into RAR0 */ +- ret_val = e1000_check_alt_mac_addr_generic(hw); ++ ret_val = e1000e_check_alt_mac_addr_generic(hw); + if (ret_val) + goto out; -- if (e1000_check_alt_mac_addr_generic(hw)) -+ if (e1000e_check_alt_mac_addr_generic(hw)) - ret_val = e1000e_read_mac_addr_generic(hw); +@@ -1688,7 +1688,7 @@ + * so that it will override the Si installed default perm + * address. + */ +- ret_val = e1000_check_alt_mac_addr_generic(hw); ++ ret_val = e1000e_check_alt_mac_addr_generic(hw); + if (ret_val) + goto out; - return ret_val; +@@ -1699,13 +1699,13 @@ } /** @@ -217,7 +247,7 @@ diff --git a/drivers/net/e1000e/e1000_82571.c b/drivers/net/e1000e/e1000_82571.c { struct e1000_phy_info *phy = &hw->phy; struct e1000_mac_info *mac = &hw->mac; -@@ -1640,7 +1640,7 @@ +@@ -1715,7 +1715,7 @@ /* If the management interface is not enabled, then power down */ if (!(mac->ops.check_mng_mode(hw) || e1000_check_reset_block(hw))) @@ -241,16 +271,51 @@ diff --git a/drivers/net/e1000e/e1000_hw.h b/drivers/net/e1000e/e1000_hw.h diff --git a/drivers/net/e1000e/e1000_ich8lan.c b/drivers/net/e1000e/e1000_ich8lan.c --- a/drivers/net/e1000e/e1000_ich8lan.c +++ b/drivers/net/e1000e/e1000_ich8lan.c -@@ -105,7 +105,7 @@ +@@ -113,7 +113,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, u8 size, u16 data); static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); -static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); +static void e1000e_power_down_phy_copper_ich8lan(struct e1000_hw *hw); - static void e1000_rar_set_ich8lan(struct e1000_hw *hw, u8 *mac_addr, u32 index); - static void e1000_mta_set_ich8lan(struct e1000_hw *hw, u32 hash_value); - static void e1000_update_mc_addr_list_ich8lan(struct e1000_hw *hw, -@@ -183,8 +183,8 @@ + static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw); + + /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ +@@ -172,9 +172,9 @@ + phy->reset_delay_us = 100; + + phy->ops.acquire = e1000_acquire_swflag_ich8lan; +- phy->ops.check_polarity = e1000_check_polarity_ife; ++ phy->ops.check_polarity = e1000e_check_polarity_ife; + phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; +- phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; ++ phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_ife; + phy->ops.get_cable_length = e1000e_get_cable_length_igp_2; + phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; + phy->ops.get_info = e1000_get_phy_info_ich8lan; +@@ -184,8 +184,8 @@ + phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; + phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; + phy->ops.write_reg = e1000_write_phy_reg_hv; +- phy->ops.power_up = e1000_power_up_phy_copper; +- phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; ++ phy->ops.power_up = e1000e_power_up_phy_copper; ++ phy->ops.power_down = e1000e_power_down_phy_copper_ich8lan; + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; + + phy->id = e1000_phy_unknown; +@@ -220,9 +220,9 @@ + phy->reset_delay_us = 100; + + phy->ops.acquire = e1000_acquire_swflag_ich8lan; +- phy->ops.check_polarity = e1000_check_polarity_ife; ++ phy->ops.check_polarity = e1000e_check_polarity_ife; + phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; +- phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; ++ phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_ife; + phy->ops.get_cable_length = e1000e_get_cable_length_igp_2; + phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; + phy->ops.get_info = e1000_get_phy_info_ich8lan; +@@ -232,8 +232,8 @@ phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; phy->ops.write_reg = e1000e_write_phy_reg_igp; @@ -261,7 +326,7 @@ diff --git a/drivers/net/e1000e/e1000_ich8lan.c b/drivers/net/e1000e/e1000_ich8l /* * We may need to do this twice - once for IGP and if that fails, -@@ -336,7 +336,7 @@ +@@ -400,7 +400,7 @@ /* bus type/speed/width */ mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; /* function id */ @@ -270,7 +335,16 @@ diff --git a/drivers/net/e1000e/e1000_ich8lan.c b/drivers/net/e1000e/e1000_ich8l /* reset */ mac->ops.reset_hw = e1000_reset_hw_ich8lan; /* hw initialization */ -@@ -370,7 +370,7 @@ +@@ -418,7 +418,7 @@ + /* multicast address update */ + mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic; + /* setting MTA */ +- mac->ops.mta_set = e1000_mta_set_generic; ++ mac->ops.mta_set = e1000e_mta_set_generic; + /* clear hardware counters */ + mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; + +@@ -432,7 +432,7 @@ /* blink LED */ mac->ops.blink_led = e1000e_blink_led; /* setup LED */ @@ -279,7 +353,7 @@ diff --git a/drivers/net/e1000e/e1000_ich8lan.c b/drivers/net/e1000e/e1000_ich8l /* cleanup LED */ mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; /* turn on/off LED */ -@@ -397,8 +397,8 @@ +@@ -559,8 +559,8 @@ **/ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) { @@ -289,9 +363,18 @@ diff --git a/drivers/net/e1000e/e1000_ich8lan.c b/drivers/net/e1000e/e1000_ich8l + e1000e_init_nvm_ops_generic(hw); hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; - hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; -@@ -2559,7 +2559,7 @@ - if (hw->mac.type != e1000_ich10lan) { + switch (hw->mac.type) { +@@ -916,7 +916,7 @@ + ? false : true; + + if (phy->polarity_correction) { +- ret_val = e1000_check_polarity_ife(hw); ++ ret_val = e1000e_check_polarity_ife(hw); + if (ret_val) + goto out; + } else { +@@ -2963,7 +2963,7 @@ + (hw->mac.type != e1000_pchlan)) { if (((er32(EECD) & E1000_EECD_PRES) == 0) && (hw->phy.type == e1000_phy_igp_3)) { - e1000_phy_init_script_igp3(hw); @@ -299,7 +382,7 @@ diff --git a/drivers/net/e1000e/e1000_ich8lan.c b/drivers/net/e1000e/e1000_ich8l } } else { if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { -@@ -2573,18 +2573,18 @@ +@@ -2977,18 +2977,18 @@ } /** @@ -321,23 +404,6 @@ diff --git a/drivers/net/e1000e/e1000_ich8lan.c b/drivers/net/e1000e/e1000_ich8l return; } -@@ -2625,14 +2625,14 @@ - * @hw: pointer to the HW structure - * @hash_value: determines the MTA register and bit to set - * -- * Set the MAC MTA register via e1000_mta_set_generic() and copy to -+ * Set the MAC MTA register via e1000e_mta_set_generic() and copy to - * the appropriate PHY MTA register. - **/ - static void e1000_mta_set_ich8lan(struct e1000_hw *hw, u32 hash_value) - { - u32 hash_bit, hash_reg, mta; - -- e1000_mta_set_generic(hw, hash_value); -+ e1000e_mta_set_generic(hw, hash_value); - - if ((hw->phy.type == e1000_phy_ife) || - (hw->phy.type == e1000_phy_igp_3)) diff --git a/drivers/net/e1000e/e1000_mac.c b/drivers/net/e1000e/e1000_mac.c --- a/drivers/net/e1000e/e1000_mac.c +++ b/drivers/net/e1000e/e1000_mac.c @@ -405,16 +471,16 @@ diff --git a/drivers/net/e1000e/e1000_mac.c b/drivers/net/e1000e/e1000_mac.c * @hw: pointer to the HW structure * * Checks the nvm for an alternate MAC address. An alternate MAC address -@@ -195,7 +195,7 @@ - * programmed into RAR0 and the function returns success, otherwise the - * function returns an error. +@@ -196,7 +196,7 @@ + * This function will return SUCCESS unless it encounters an error while + * reading the EEPROM. **/ -s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) +s32 e1000e_check_alt_mac_addr_generic(struct e1000_hw *hw) { u32 i; s32 ret_val = E1000_SUCCESS; -@@ -282,7 +282,7 @@ +@@ -285,7 +285,7 @@ } /** @@ -423,7 +489,7 @@ diff --git a/drivers/net/e1000e/e1000_mac.c b/drivers/net/e1000e/e1000_mac.c * @hw: pointer to the HW structure * @hash_value: determines the MTA register and bit to set * -@@ -291,7 +291,7 @@ +@@ -294,7 +294,7 @@ * current value is read, the new bit is OR'd in and the new value is * written back into the register. **/ @@ -432,7 +498,7 @@ diff --git a/drivers/net/e1000e/e1000_mac.c b/drivers/net/e1000e/e1000_mac.c { u32 hash_bit, hash_reg, mta; -@@ -375,7 +375,7 @@ +@@ -361,7 +361,7 @@ * * Generates a multicast address hash value which is used to determine * the multicast filter table array address and new table value. See @@ -441,7 +507,7 @@ diff --git a/drivers/net/e1000e/e1000_mac.c b/drivers/net/e1000e/e1000_mac.c **/ static u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) { -@@ -1579,18 +1579,18 @@ +@@ -1565,18 +1565,18 @@ } /** @@ -484,8 +550,8 @@ diff --git a/drivers/net/e1000e/e1000_mac.h b/drivers/net/e1000e/e1000_mac.h s32 e1000e_get_hw_semaphore(struct e1000_hw *hw); s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex); -@@ -58,18 +58,18 @@ - u32 rar_used_count, u32 rar_count); +@@ -57,18 +57,18 @@ + u8 *mc_addr_list, u32 mc_addr_count); s32 e1000e_set_fc_watermarks(struct e1000_hw *hw); s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw); -s32 e1000_setup_led_generic(struct e1000_hw *hw); @@ -630,7 +696,24 @@ diff --git a/drivers/net/e1000e/e1000_nvm.h b/drivers/net/e1000e/e1000_nvm.h diff --git a/drivers/net/e1000e/e1000_phy.c b/drivers/net/e1000e/e1000_phy.c --- a/drivers/net/e1000e/e1000_phy.c +++ b/drivers/net/e1000e/e1000_phy.c -@@ -1367,14 +1367,14 @@ +@@ -1255,14 +1255,14 @@ + } + + /** +- * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex ++ * e1000e_phy_force_speed_duplex_ife - Force PHY speed & duplex + * @hw: pointer to the HW structure + * + * Forces the speed and duplex settings of the PHY. + * This is a function pointer entry point only called by + * PHY setup routines. + **/ +-s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) ++s32 e1000e_phy_force_speed_duplex_ife(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -1522,14 +1522,14 @@ } /** @@ -647,7 +730,7 @@ diff --git a/drivers/net/e1000e/e1000_phy.c b/drivers/net/e1000e/e1000_phy.c { struct e1000_phy_info *phy = &hw->phy; s32 ret_val; -@@ -1391,7 +1391,7 @@ +@@ -1546,7 +1546,7 @@ } /** @@ -656,7 +739,7 @@ diff --git a/drivers/net/e1000e/e1000_phy.c b/drivers/net/e1000e/e1000_phy.c * @hw: pointer to the HW structure * * Success returns 0, Failure returns -E1000_ERR_PHY (-2) -@@ -1399,7 +1399,7 @@ +@@ -1554,7 +1554,7 @@ * Polarity is determined based on the PHY port status register, and the * current speed (since there is no polarity at 100Mbps). **/ @@ -665,7 +748,22 @@ diff --git a/drivers/net/e1000e/e1000_phy.c b/drivers/net/e1000e/e1000_phy.c { struct e1000_phy_info *phy = &hw->phy; s32 ret_val; -@@ -1438,13 +1438,13 @@ +@@ -1593,12 +1593,12 @@ + } + + /** +- * e1000_check_polarity_ife - Check cable polarity for IFE PHY ++ * e1000e_check_polarity_ife - Check cable polarity for IFE PHY + * @hw: pointer to the HW structure + * + * Polarity is determined on the polarity reversal feature being enabled. + **/ +-s32 e1000_check_polarity_ife(struct e1000_hw *hw) ++s32 e1000e_check_polarity_ife(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -1626,13 +1626,13 @@ } /** @@ -681,7 +779,7 @@ diff --git a/drivers/net/e1000e/e1000_phy.c b/drivers/net/e1000e/e1000_phy.c { s32 ret_val = E1000_SUCCESS; u16 i, phy_status; -@@ -1668,7 +1668,7 @@ +@@ -1862,7 +1862,7 @@ phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) ? true : false; @@ -690,7 +788,7 @@ diff --git a/drivers/net/e1000e/e1000_phy.c b/drivers/net/e1000e/e1000_phy.c if (ret_val) goto out; -@@ -1733,7 +1733,7 @@ +@@ -1927,7 +1927,7 @@ phy->polarity_correction = true; @@ -699,7 +797,7 @@ diff --git a/drivers/net/e1000e/e1000_phy.c b/drivers/net/e1000e/e1000_phy.c if (ret_val) goto out; -@@ -1859,12 +1859,12 @@ +@@ -2053,12 +2053,12 @@ } /** @@ -714,7 +812,7 @@ diff --git a/drivers/net/e1000e/e1000_phy.c b/drivers/net/e1000e/e1000_phy.c { e_dbg("Running IGP 3 PHY init script\n"); -@@ -2369,14 +2369,14 @@ +@@ -2574,14 +2574,14 @@ } /** @@ -731,7 +829,7 @@ diff --git a/drivers/net/e1000e/e1000_phy.c b/drivers/net/e1000e/e1000_phy.c { u16 mii_reg = 0; -@@ -2387,14 +2387,14 @@ +@@ -2592,14 +2592,14 @@ } /** @@ -751,18 +849,27 @@ diff --git a/drivers/net/e1000e/e1000_phy.c b/drivers/net/e1000e/e1000_phy.c diff --git a/drivers/net/e1000e/e1000_phy.h b/drivers/net/e1000e/e1000_phy.h --- a/drivers/net/e1000e/e1000_phy.h +++ b/drivers/net/e1000e/e1000_phy.h -@@ -31,8 +31,8 @@ +@@ -31,15 +31,15 @@ void e1000_init_phy_ops_generic(struct e1000_hw *hw); s32 e1000e_check_downshift(struct e1000_hw *hw); -s32 e1000_check_polarity_m88(struct e1000_hw *hw); -s32 e1000_check_polarity_igp(struct e1000_hw *hw); +-s32 e1000_check_polarity_ife(struct e1000_hw *hw); +s32 e1000e_check_polarity_m88(struct e1000_hw *hw); +s32 e1000e_check_polarity_igp(struct e1000_hw *hw); ++s32 e1000e_check_polarity_ife(struct e1000_hw *hw); s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); -@@ -53,22 +53,22 @@ + s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); + s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); +-s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); ++s32 e1000e_phy_force_speed_duplex_ife(struct e1000_hw *hw); + s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); + s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); + s32 e1000e_get_cfg_done(struct e1000_hw *hw); +@@ -55,22 +55,22 @@ s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); s32 e1000e_setup_copper_link(struct e1000_hw *hw); @@ -777,22 +884,22 @@ diff --git a/drivers/net/e1000e/e1000_phy.h b/drivers/net/e1000e/e1000_phy.h -s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); +s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); - s32 e1000e_determine_phy_address(struct e1000_hw *hw); - s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); - s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); - s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); - s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); + s32 e1000e_determine_phy_address(struct e1000_hw *hw); + s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); + s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); + s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); + s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); -void e1000_power_up_phy_copper(struct e1000_hw *hw); -void e1000_power_down_phy_copper(struct e1000_hw *hw); +void e1000e_power_up_phy_copper(struct e1000_hw *hw); +void e1000e_power_down_phy_copper(struct e1000_hw *hw); - s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); - s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); - + s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); + s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); + s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h --- a/drivers/net/e1000e/hw.h +++ b/drivers/net/e1000e/hw.h -@@ -683,6 +683,6 @@ +@@ -696,6 +696,6 @@ #include "e1000_ich8lan.h" /* These functions must be implemented by drivers */ @@ -803,6 +910,41 @@ diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c +@@ -166,7 +166,7 @@ + static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); + static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); + static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); +-static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); ++static s32 e1000e_check_polarity_ife_ich8lan(struct e1000_hw *hw); + static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); + static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, + u32 offset, u8 byte); +@@ -728,7 +728,7 @@ + phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE)); + + if (phy->polarity_correction) { +- ret_val = e1000_check_polarity_ife_ich8lan(hw); ++ ret_val = e1000e_check_polarity_ife_ich8lan(hw); + if (ret_val) + return ret_val; + } else { +@@ -778,14 +778,14 @@ + } + + /** +- * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY ++ * e1000e_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY + * @hw: pointer to the HW structure + * + * Polarity is determined on the polarity reversal feature being enabled. + * This function is only called by other family-specific + * routines. + **/ +-static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) ++static s32 e1000e_check_polarity_ife_ich8lan(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; @@ -2487,12 +2487,12 @@ } @@ -842,7 +984,7 @@ diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c --- a/drivers/net/e1000e/netdev.c +++ b/drivers/net/e1000e/netdev.c -@@ -5228,7 +5228,7 @@ +@@ -5435,7 +5435,7 @@ } } diff --git a/master/intel-net-driver-kcompat.patch b/master/intel-net-driver-kcompat.patch index 83ca72b..772ad12 100644 --- a/master/intel-net-driver-kcompat.patch +++ b/master/intel-net-driver-kcompat.patch @@ -1,7 +1,34 @@ -diff -r 64a037056e9d drivers/net/e1000/kcompat.h ---- a/drivers/net/e1000/kcompat.h Mon Jun 15 12:06:27 2009 +0100 -+++ b/drivers/net/e1000/kcompat.h Mon Jun 15 13:38:57 2009 +0100 -@@ -1361,9 +1361,9 @@ +diff -r fe053dc2924b drivers/net/e1000/kcompat.c +--- a/drivers/net/e1000/kcompat.c Wed Aug 05 11:05:54 2009 +0100 ++++ b/drivers/net/e1000/kcompat.c Wed Aug 05 11:28:17 2009 +0100 +@@ -427,7 +427,7 @@ + #endif /* < 2.6.27 */ + + /*****************************************************************************/ +-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) + + int + _kc_pci_prepare_to_sleep(struct pci_dev *dev) +@@ -446,9 +446,13 @@ + + return error; + } ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) + + int +-_kc_pci_wake_from_d3(struct pci_dev *dev, bool enable) ++_kc_e1000_pci_wake_from_d3(struct pci_dev *dev, bool enable) + { + int err; + +diff -r fe053dc2924b drivers/net/e1000/kcompat.h +--- a/drivers/net/e1000/kcompat.h Wed Aug 05 11:05:54 2009 +0100 ++++ b/drivers/net/e1000/kcompat.h Wed Aug 05 11:28:17 2009 +0100 +@@ -1392,9 +1392,9 @@ #ifndef AX_RELEASE_VERSION #define AX_RELEASE_VERSION(a,b) 0 #endif @@ -14,10 +41,59 @@ diff -r 64a037056e9d drivers/net/e1000/kcompat.h #if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0)) #undef CONFIG_INET_LRO #undef CONFIG_INET_LRO_MODULE -diff -r 64a037056e9d drivers/net/e1000e/kcompat.h ---- a/drivers/net/e1000e/kcompat.h Mon Jun 15 12:06:27 2009 +0100 -+++ b/drivers/net/e1000e/kcompat.h Mon Jun 15 13:38:57 2009 +0100 -@@ -1343,9 +1343,9 @@ +@@ -1696,13 +1696,17 @@ + #endif /* < 2.6.27 */ + + /*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) ++#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep ++extern int _kc_pci_prepare_to_sleep(struct pci_dev *dev); ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ + #if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) + #define pci_ioremap_bar(pdev, bar) ioremap(pci_resource_start(pdev, bar), \ + pci_resource_len(pdev, bar)) +-#define pci_wake_from_d3 _kc_pci_wake_from_d3 +-#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep +-extern int _kc_pci_wake_from_d3(struct pci_dev *dev, bool enable); +-extern int _kc_pci_prepare_to_sleep(struct pci_dev *dev); ++#define pci_wake_from_d3 _kc_e1000_pci_wake_from_d3 ++extern int _kc_e1000_pci_wake_from_d3(struct pci_dev *dev, bool enable); + #endif /* < 2.6.28 */ + + /*****************************************************************************/ +diff -r fe053dc2924b drivers/net/e1000e/kcompat.c +--- a/drivers/net/e1000e/kcompat.c Wed Aug 05 11:05:54 2009 +0100 ++++ b/drivers/net/e1000e/kcompat.c Wed Aug 05 11:28:17 2009 +0100 +@@ -435,7 +435,7 @@ + #endif /* < 2.6.27 */ + + /*****************************************************************************/ +-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) + + int + _kc_pci_prepare_to_sleep(struct pci_dev *dev) +@@ -454,9 +454,13 @@ + + return error; + } ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) + + int +-_kc_pci_wake_from_d3(struct pci_dev *dev, bool enable) ++_kc_e1000e_pci_wake_from_d3(struct pci_dev *dev, bool enable) + { + int err; + +diff -r fe053dc2924b drivers/net/e1000e/kcompat.h +--- a/drivers/net/e1000e/kcompat.h Wed Aug 05 11:05:54 2009 +0100 ++++ b/drivers/net/e1000e/kcompat.h Wed Aug 05 11:28:17 2009 +0100 +@@ -1354,9 +1354,9 @@ #ifndef AX_RELEASE_VERSION #define AX_RELEASE_VERSION(a,b) 0 #endif @@ -30,10 +106,59 @@ diff -r 64a037056e9d drivers/net/e1000e/kcompat.h #if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0)) #undef CONFIG_INET_LRO #undef CONFIG_INET_LRO_MODULE -diff -r 64a037056e9d drivers/net/igb/kcompat.h ---- a/drivers/net/igb/kcompat.h Mon Jun 15 12:06:27 2009 +0100 -+++ b/drivers/net/igb/kcompat.h Mon Jun 15 13:38:57 2009 +0100 -@@ -1344,9 +1344,9 @@ +@@ -1663,13 +1663,17 @@ + #endif /* < 2.6.27 */ + + /*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) ++#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep ++extern int _kc_pci_prepare_to_sleep(struct pci_dev *dev); ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ + #if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) + #define pci_ioremap_bar(pdev, bar) ioremap(pci_resource_start(pdev, bar), \ + pci_resource_len(pdev, bar)) +-#define pci_wake_from_d3 _kc_pci_wake_from_d3 +-#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep +-extern int _kc_pci_wake_from_d3(struct pci_dev *dev, bool enable); +-extern int _kc_pci_prepare_to_sleep(struct pci_dev *dev); ++#define pci_wake_from_d3 _kc_e1000e_pci_wake_from_d3 ++extern int _kc_e1000e_pci_wake_from_d3(struct pci_dev *dev, bool enable); + #endif /* < 2.6.28 */ + + /*****************************************************************************/ +diff -r fe053dc2924b drivers/net/igb/kcompat.c +--- a/drivers/net/igb/kcompat.c Wed Aug 05 11:05:54 2009 +0100 ++++ b/drivers/net/igb/kcompat.c Wed Aug 05 11:28:17 2009 +0100 +@@ -442,7 +442,7 @@ + #endif /* < 2.6.27 */ + + /*****************************************************************************/ +-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) + + int + _kc_pci_prepare_to_sleep(struct pci_dev *dev) +@@ -461,9 +461,13 @@ + + return error; + } ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) + + int +-_kc_pci_wake_from_d3(struct pci_dev *dev, bool enable) ++_kc_igb_pci_wake_from_d3(struct pci_dev *dev, bool enable) + { + int err; + +diff -r fe053dc2924b drivers/net/igb/kcompat.h +--- a/drivers/net/igb/kcompat.h Wed Aug 05 11:05:54 2009 +0100 ++++ b/drivers/net/igb/kcompat.h Wed Aug 05 11:28:17 2009 +0100 +@@ -1350,9 +1350,9 @@ #ifndef AX_RELEASE_VERSION #define AX_RELEASE_VERSION(a,b) 0 #endif @@ -46,9 +171,31 @@ diff -r 64a037056e9d drivers/net/igb/kcompat.h #if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0)) #undef CONFIG_INET_LRO #undef CONFIG_INET_LRO_MODULE -diff -r 64a037056e9d drivers/net/ixgb/kcompat.h ---- a/drivers/net/ixgb/kcompat.h Mon Jun 15 12:06:27 2009 +0100 -+++ b/drivers/net/ixgb/kcompat.h Mon Jun 15 13:38:57 2009 +0100 +@@ -1684,13 +1684,17 @@ + #endif /* < 2.6.27 */ + + /*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) ++#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep ++extern int _kc_pci_prepare_to_sleep(struct pci_dev *dev); ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ + #if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) + #define pci_ioremap_bar(pdev, bar) ioremap(pci_resource_start(pdev, bar), \ + pci_resource_len(pdev, bar)) +-#define pci_wake_from_d3 _kc_pci_wake_from_d3 +-#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep +-extern int _kc_pci_wake_from_d3(struct pci_dev *dev, bool enable); +-extern int _kc_pci_prepare_to_sleep(struct pci_dev *dev); ++#define pci_wake_from_d3 _kc_igb_pci_wake_from_d3 ++extern int _kc_igb_pci_wake_from_d3(struct pci_dev *dev, bool enable); + #endif /* < 2.6.28 */ + + /*****************************************************************************/ +diff -r fe053dc2924b drivers/net/ixgb/kcompat.h +--- a/drivers/net/ixgb/kcompat.h Wed Aug 05 11:05:54 2009 +0100 ++++ b/drivers/net/ixgb/kcompat.h Wed Aug 05 11:28:17 2009 +0100 @@ -1359,9 +1359,9 @@ #ifndef RHEL_RELEASE_VERSION #define RHEL_RELEASE_VERSION(a,b) 0 @@ -62,10 +209,37 @@ diff -r 64a037056e9d drivers/net/ixgb/kcompat.h typedef irqreturn_t (*new_handler_t)(int, void*); static inline irqreturn_t _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id) #else /* 2.4.x */ -diff -r 64a037056e9d drivers/net/ixgbe/kcompat.h ---- a/drivers/net/ixgbe/kcompat.h Mon Jun 15 12:06:27 2009 +0100 -+++ b/drivers/net/ixgbe/kcompat.h Mon Jun 15 13:38:57 2009 +0100 -@@ -1373,9 +1373,9 @@ +diff -r fe053dc2924b drivers/net/ixgbe/kcompat.c +--- a/drivers/net/ixgbe/kcompat.c Wed Aug 05 11:05:54 2009 +0100 ++++ b/drivers/net/ixgbe/kcompat.c Wed Aug 05 11:28:17 2009 +0100 +@@ -447,7 +447,7 @@ + #endif /* < 2.6.27 */ + + /*****************************************************************************/ +-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) + + int + _kc_pci_prepare_to_sleep(struct pci_dev *dev) +@@ -466,9 +466,13 @@ + + return error; + } ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) + + int +-_kc_pci_wake_from_d3(struct pci_dev *dev, bool enable) ++_kc_ixgbe_pci_wake_from_d3(struct pci_dev *dev, bool enable) + { + int err; + +diff -r fe053dc2924b drivers/net/ixgbe/kcompat.h +--- a/drivers/net/ixgbe/kcompat.h Wed Aug 05 11:05:54 2009 +0100 ++++ b/drivers/net/ixgbe/kcompat.h Wed Aug 05 11:28:17 2009 +0100 +@@ -1395,9 +1395,9 @@ #ifndef AX_RELEASE_VERSION #define AX_RELEASE_VERSION(a,b) 0 #endif @@ -78,3 +252,25 @@ diff -r 64a037056e9d drivers/net/ixgbe/kcompat.h #if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0)) #undef CONFIG_INET_LRO #undef CONFIG_INET_LRO_MODULE +@@ -1759,13 +1759,17 @@ + #endif /* < 2.6.27 */ + + /*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) ++#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep ++extern int _kc_pci_prepare_to_sleep(struct pci_dev *dev); ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ + #if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) + #define pci_ioremap_bar(pdev, bar) ioremap(pci_resource_start(pdev, bar), \ + pci_resource_len(pdev, bar)) +-#define pci_wake_from_d3 _kc_pci_wake_from_d3 +-#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep +-extern int _kc_pci_wake_from_d3(struct pci_dev *dev, bool enable); +-extern int _kc_pci_prepare_to_sleep(struct pci_dev *dev); ++#define pci_wake_from_d3 _kc_ixgbe_pci_wake_from_d3 ++extern int _kc_ixgbe_pci_wake_from_d3(struct pci_dev *dev, bool enable); + #endif /* < 2.6.28 */ + + /*****************************************************************************/ diff --git a/master/itpm b/master/itpm index 6f13d52..e8f8649 100644 --- a/master/itpm +++ b/master/itpm @@ -1233,7 +1233,7 @@ index d0e7926..c64a1bc 100644 } diff --git a/drivers/char/tpm/tpm_bios.c b/drivers/char/tpm/tpm_bios.c -index 68f052b..0c2f55a 100644 +index 2db432d..0c2f55a 100644 --- a/drivers/char/tpm/tpm_bios.c +++ b/drivers/char/tpm/tpm_bios.c @@ -23,8 +23,6 @@ @@ -1245,16 +1245,6 @@ index 68f052b..0c2f55a 100644 #include "tpm.h" #define TCG_EVENT_NAME_LEN_MAX 255 -@@ -214,7 +212,8 @@ static int get_event_name(char *dest, struct tcpa_event *event, - unsigned char * event_entry) - { - const char *name = ""; -- char data[40] = ""; -+ /* 41 so there is room for 40 data and 1 nul */ -+ char data[41] = ""; - int i, n_len = 0, d_len = 0; - struct tcpa_pc_event *pc_event; - diff --git a/drivers/char/tpm/tpm_infineon.c b/drivers/char/tpm/tpm_infineon.c index 726ee8a..ecba494 100644 --- a/drivers/char/tpm/tpm_infineon.c diff --git a/master/ixgbe-2.0.38.2.patch b/master/ixgbe-2.0.38.2.patch new file mode 100644 index 0000000..5409000 --- /dev/null +++ b/master/ixgbe-2.0.38.2.patch @@ -0,0 +1,26874 @@ +diff -r 1efe16c57de3 drivers/net/Kconfig +--- a/drivers/net/Kconfig Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/Kconfig Wed Aug 05 11:05:50 2009 +0100 +@@ -2417,16 +2417,6 @@ + + If in doubt, say N. + +-config IXGBE_DCB +- bool "Data Center Bridging (DCB) Support" +- default n +- depends on IXGBE && DCB +- ---help--- +- Say Y here if you want to use Data Center Bridging (DCB) in the +- driver. +- +- If unsure, say N. +- + config IXGB + tristate "Intel(R) PRO/10GbE support" + depends on PCI +diff -r 1efe16c57de3 drivers/net/ixgbe/Makefile +--- a/drivers/net/ixgbe/Makefile Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/Makefile Wed Aug 05 11:05:50 2009 +0100 +@@ -32,7 +32,21 @@ + + obj-$(CONFIG_IXGBE) += ixgbe.o + +-ixgbe-objs := ixgbe_main.o ixgbe_common.o ixgbe_ethtool.o \ +- ixgbe_82598.o ixgbe_phy.o ++CFILES = ixgbe_main.c ixgbe_common.c ixgbe_api.c ixgbe_param.c \ ++ ixgbe_ethtool.c kcompat.c ixgbe_82598.c ixgbe_82599.c \ ++ ixgbe_dcb.c ixgbe_dcb_nl.c ixgbe_dcb_82598.c ixgbe_dcb_82599.c \ ++ ixgbe_phy.c ixgbe_sysfs.c + +-ixgbe-$(CONFIG_IXGBE_DCB) += ixgbe_dcb.o ixgbe_dcb_82598.o ixgbe_dcb_nl.o ++# Add FCoE source if FCoE is supported by the kernel ++#FCOE := $(shell grep -wE 'CONFIG_FCOE|CONFIG_FCOE_MODULE' $(CONFIG_FILE) | \ ++# awk '{print $$3}') ++#ifeq ($(FCOE), 1) ++# CFILES += ixgbe_sysfs.c ++# CFILES += ixgbe_fcoe.c ++# HFILES += ixgbe_fcoe.h ++#endif ++ ++ ++ixgbe-objs := $(CFILES:.c=.o) ++ ++EXTRA_CFLAGS += -DDRIVER_IXGBE -DIXGBE_NO_LRO +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe.h +--- a/drivers/net/ixgbe/ixgbe.h Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe.h Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -28,23 +28,37 @@ + #ifndef _IXGBE_H_ + #define _IXGBE_H_ + +-#include ++#ifndef IXGBE_NO_LRO ++#include ++#endif ++ + #include + #include ++#include + +-#ifdef CONFIG_IXGBE_LRO +-#include +-#define IXGBE_MAX_LRO_AGGREGATE 32 +-#define IXGBE_MAX_LRO_DESCRIPTORS 8 ++#ifdef SIOCETHTOOL ++#include ++#endif ++#ifdef NETIF_F_HW_VLAN_TX ++#include ++#endif ++#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) ++#define IXGBE_DCA ++#include ++ + #endif + +-#include "ixgbe_type.h" +-#include "ixgbe_common.h" + #include "ixgbe_dcb.h" + +-#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) +-#include +-#endif ++ ++#include "kcompat.h" ++ ++#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) ++#define IXGBE_FCOE ++#include "ixgbe_fcoe.h" ++#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ ++ ++#include "ixgbe_api.h" + + #define PFX "ixgbe: " + #define DPRINTK(nlevel, klevel, fmt, args...) \ +@@ -60,6 +74,7 @@ + #define IXGBE_DEFAULT_RXD 1024 + #define IXGBE_MAX_RXD 4096 + #define IXGBE_MIN_RXD 64 ++ + + /* flow control */ + #define IXGBE_DEFAULT_FCRTL 0x10000 +@@ -77,11 +92,18 @@ + #define IXGBE_RXBUFFER_128 128 /* Used for packet split */ + #define IXGBE_RXBUFFER_256 256 /* Used for packet split */ + #define IXGBE_RXBUFFER_2048 2048 +-#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ ++#define IXGBE_RXBUFFER_4096 4096 ++#define IXGBE_RXBUFFER_8192 8192 ++#define IXGBE_MAX_RXBUFFER 16384 /* largest size for single descriptor */ + + #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 + +-#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) ++#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) ++ ++#if defined(IXGBE_DCB) || defined(IXGBE_RSS) || \ ++ defined(IXGBE_VMDQ) ++#define IXGBE_MQ ++#endif + + /* How many Rx Buffers do we bundle into one write to the hardware ? */ + #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ +@@ -90,10 +112,52 @@ + #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1) + #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2) + #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3) ++#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4) ++#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5) + #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 + #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000 + #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 + ++#define IXGBE_MAX_RSC_INT_RATE 162760 ++ ++#ifndef IXGBE_NO_LRO ++#define IXGBE_LRO_MAX 32 /*Maximum number of LRO descriptors*/ ++#define IXGBE_LRO_GLOBAL 10 ++ ++struct ixgbe_lro_stats { ++ u32 flushed; ++ u32 coal; ++ u32 recycled; ++}; ++ ++struct ixgbe_lro_desc { ++ struct hlist_node lro_node; ++ struct sk_buff *skb; ++ u32 source_ip; ++ u32 dest_ip; ++ u16 source_port; ++ u16 dest_port; ++ u16 vlan_tag; ++ u16 len; ++ u32 next_seq; ++ u32 ack_seq; ++ u16 window; ++ u16 mss; ++ u16 opt_bytes; ++ u16 psh:1; ++ u32 tsval; ++ u32 tsecr; ++ u32 append_cnt; ++}; ++ ++struct ixgbe_lro_list { ++ struct hlist_head active; ++ struct hlist_head free; ++ int active_cnt; ++ struct ixgbe_lro_stats stats; ++}; ++ ++#endif /* IXGBE_NO_LRO */ + /* wrapper around a pointer to a socket buffer, + * so a DMA handle can be stored along with the buffer */ + struct ixgbe_tx_buffer { +@@ -119,17 +183,18 @@ + + struct ixgbe_ring { + void *desc; /* descriptor ring memory */ +- dma_addr_t dma; /* phys. address of descriptor ring */ +- unsigned int size; /* length in bytes */ +- unsigned int count; /* amount of descriptors */ +- unsigned int next_to_use; +- unsigned int next_to_clean; +- +- int queue_index; /* needed for multiqueue queue management */ + union { + struct ixgbe_tx_buffer *tx_buffer_info; + struct ixgbe_rx_buffer *rx_buffer_info; + }; ++ u8 atr_sample_rate; ++ u8 atr_count; ++ u16 count; /* amount of descriptors */ ++ u16 rx_buf_len; ++ u16 next_to_use; ++ u16 next_to_clean; ++ ++ u8 queue_index; /* needed for multiqueue queue management */ + + u16 head; + u16 tail; +@@ -137,44 +202,46 @@ + unsigned int total_bytes; + unsigned int total_packets; + +- u16 reg_idx; /* holds the special value that gets the hardware register +- * offset associated with this ring, which is different +- * for DCB and RSS modes */ +- + #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) + /* cpu for tx queue */ + int cpu; + #endif +-#ifdef CONFIG_IXGBE_LRO +- struct net_lro_mgr lro_mgr; +- bool lro_used; +-#endif ++ u16 work_limit; /* max work per interrupt */ ++ u16 reg_idx; /* holds the special value that gets the ++ * hardware register offset associated ++ * with this ring, which is different ++ * for DCB and RSS modes */ ++ + struct ixgbe_queue_stats stats; +- u16 v_idx; /* maps directly to the index for this ring in the hardware +- * vector array, can also be used for finding the bit in EICR +- * and friends that represents the vector for this ring */ +- +- +- u16 work_limit; /* max work per interrupt */ +- u16 rx_buf_len; ++ unsigned long reinit_state; ++ u64 rsc_count; /* stat for coalesced packets */ ++ unsigned int size; /* length in bytes */ ++ dma_addr_t dma; /* phys. address of descriptor ring */ + }; + +-#define RING_F_DCB 0 +-#define RING_F_VMDQ 1 +-#define RING_F_RSS 2 ++enum ixgbe_ring_f_enum { ++ RING_F_NONE = 0, ++ RING_F_DCB, ++ RING_F_VMDQ, ++ RING_F_RSS, ++ RING_F_FDIR, ++ RING_F_ARRAY_SIZE /* must be last in enum set */ ++}; ++ + #define IXGBE_MAX_DCB_INDICES 8 + #define IXGBE_MAX_RSS_INDICES 16 +-#define IXGBE_MAX_VMDQ_INDICES 16 ++#define IXGBE_MAX_VMDQ_INDICES 64 ++#define IXGBE_MAX_FDIR_INDICES 64 + struct ixgbe_ring_feature { + int indices; + int mask; + }; + +-#define MAX_RX_QUEUES 64 +-#define MAX_TX_QUEUES 32 ++#define MAX_RX_QUEUES 128 ++#define MAX_TX_QUEUES 128 + + #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ +- ? 8 : 1) ++ ? 8 : 1) + #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS + + /* MAX_MSIX_Q_VECTORS of these are allocated, +@@ -182,7 +249,12 @@ + */ + struct ixgbe_q_vector { + struct ixgbe_adapter *adapter; ++ unsigned int v_idx; /* index of q_vector within array, also used for ++ * finding the bit in EICR and friends that ++ * represents the vector for this ring */ ++#ifdef CONFIG_IXGBE_NAPI + struct napi_struct napi; ++#endif + DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */ + DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */ + u8 rxr_count; /* Rx ring count assigned to this vector */ +@@ -190,13 +262,22 @@ + u8 tx_itr; + u8 rx_itr; + u32 eitr; ++#ifndef IXGBE_NO_LRO ++ struct ixgbe_lro_list *lrolist; /* LRO list for queue vector*/ ++#endif ++ char name[IFNAMSIZ + 9]; ++#ifndef HAVE_NETDEV_NAPI_LIST ++ struct net_device poll_dev; ++#endif + }; + ++ + /* Helper macros to switch between ints/sec and what the register uses. +- * And yes, it's the same math going both ways. ++ * And yes, it's the same math going both ways. The lowest value ++ * supported by all of the ixgbe hardware is 8. + */ + #define EITR_INTS_PER_SEC_TO_REG(_eitr) \ +- ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0) ++ ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8) + #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG + + #define IXGBE_DESC_UNUSED(R) \ +@@ -212,25 +293,44 @@ + + #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128 + ++#ifdef IXGBE_TCP_TIMER ++#define TCP_TIMER_VECTOR 1 ++#else ++#define TCP_TIMER_VECTOR 0 ++#endif + #define OTHER_VECTOR 1 +-#define NON_Q_VECTORS (OTHER_VECTOR) ++#define NON_Q_VECTORS (OTHER_VECTOR + TCP_TIMER_VECTOR) + +-#define MAX_MSIX_Q_VECTORS 16 ++#define IXGBE_MAX_MSIX_VECTORS_82599 64 ++#define IXGBE_MAX_MSIX_Q_VECTORS_82599 64 ++#define IXGBE_MAX_MSIX_Q_VECTORS_82598 16 ++#define IXGBE_MAX_MSIX_VECTORS_82598 18 ++ ++/* ++ * Only for array allocations in our adapter struct. On 82598, there will be ++ * unused entries in the array, but that's not a big deal. Also, in 82599, ++ * we can actually assign 64 queue vectors based on our extended-extended ++ * interrupt registers. This is different than 82598, which is limited to 16. ++ */ ++#define MAX_MSIX_Q_VECTORS IXGBE_MAX_MSIX_Q_VECTORS_82599 ++#define MAX_MSIX_COUNT IXGBE_MAX_MSIX_VECTORS_82599 ++ + #define MIN_MSIX_Q_VECTORS 2 +-#define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS) + #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) + + /* board specific private data structure */ + struct ixgbe_adapter { + struct timer_list watchdog_timer; ++#ifdef NETIF_F_HW_VLAN_TX + struct vlan_group *vlgrp; ++#endif + u16 bd_number; + struct work_struct reset_task; +- struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS]; +- char name[MAX_MSIX_COUNT][IFNAMSIZ + 5]; ++ struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS]; + struct ixgbe_dcb_config dcb_cfg; + struct ixgbe_dcb_config temp_dcb_cfg; + u8 dcb_set_bitmap; ++ enum ixgbe_fc_mode last_lfc_mode; + + /* Interrupt Throttle Rate */ + u32 itr_setting; +@@ -251,14 +351,24 @@ + /* RX */ + struct ixgbe_ring *rx_ring; /* One per active queue */ + int num_rx_queues; ++ int num_rx_pools; /* == num_rx_queues in 82598 */ ++ int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ + u64 hw_csum_rx_error; ++ u64 hw_rx_no_dma_resources; + u64 hw_csum_rx_good; + u64 non_eop_descs; ++#ifndef CONFIG_IXGBE_NAPI ++ u64 rx_dropped_backlog; /* count drops from rx intr handler */ ++#endif + int num_msix_vectors; +- struct ixgbe_ring_feature ring_feature[3]; ++ int max_msix_q_vectors; /* true count of q_vectors for device */ ++ struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; + struct msix_entry *msix_entries; ++#ifdef IXGBE_TCP_TIMER ++ irqreturn_t (*msix_handlers[MAX_MSIX_COUNT])(int irq, void *data, ++ struct pt_regs *regs); ++#endif + +- u64 rx_hdr_split; + u32 alloc_rx_page_failed; + u32 alloc_rx_buff_failed; + +@@ -271,14 +381,19 @@ + #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2) + #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3) + #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4) ++#ifndef IXGBE_NO_LLI ++#define IXGBE_FLAG_LLI_PUSH (u32)(1 << 5) ++#endif + #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6) + #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7) + #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8) + #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9) + #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10) + #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11) +-#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12) ++#define IXGBE_FLAG_DCA_ENABLED_DATA (u32)(1 << 12) + #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13) ++#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14) ++#define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 15) + #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16) + #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17) + #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18) +@@ -286,7 +401,20 @@ + #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20) + #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22) + #define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23) +-#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 24) ++#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 24) ++#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 25) ++#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 26) ++#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 27) ++ ++ u32 flags2; ++#ifndef IXGBE_NO_HW_RSC ++#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1) ++#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) ++#endif /* IXGBE_NO_HW_RSC */ ++#ifndef IXGBE_NO_LRO ++#define IXGBE_FLAG2_SWLRO_ENABLED (u32)(1 << 2) ++#endif /* IXGBE_NO_LRO */ ++#define IXGBE_FLAG2_VMDQ_DEFAULT_OVERRIDE (u32)(1 << 3) + + /* default to trying for four seconds */ + #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) +@@ -295,22 +423,33 @@ + struct net_device *netdev; + struct pci_dev *pdev; + struct net_device_stats net_stats; ++#ifndef IXGBE_NO_LRO ++ struct ixgbe_lro_stats lro_stats; ++#endif ++ ++#ifdef ETHTOOL_TEST ++ u32 test_icr; ++ struct ixgbe_ring test_tx_ring; ++ struct ixgbe_ring test_rx_ring; ++#endif + + /* structs defined in ixgbe_hw.h */ + struct ixgbe_hw hw; + u16 msg_enable; + struct ixgbe_hw_stats stats; +- ++#ifndef IXGBE_NO_LLI ++ u32 lli_port; ++ u32 lli_size; ++ u64 lli_int; ++ u32 lli_etype; ++ u32 lli_vlan_pri; ++#endif /* IXGBE_NO_LLI */ + /* Interrupt Throttle Rate */ + u32 eitr_param; + + unsigned long state; ++ u32 *config_space; + u64 tx_busy; +-#ifndef IXGBE_NO_INET_LRO +- u64 lro_aggregated; +- u64 lro_flushed; +- u64 lro_no_desc; +-#endif + unsigned int tx_ring_count; + unsigned int rx_ring_count; + +@@ -321,28 +460,44 @@ + struct work_struct watchdog_task; + struct work_struct sfp_task; + struct timer_list sfp_timer; ++ struct work_struct multispeed_fiber_task; ++ struct work_struct sfp_config_module_task; ++ u64 flm; ++ u32 fdir_pballoc; ++ u32 atr_sample_rate; ++ spinlock_t fdir_perfect_lock; ++ struct work_struct fdir_reinit_task; ++ u64 rsc_count; ++ u32 wol; ++ u16 eeprom_version; ++ bool netdev_registered; ++ char lsc_int_name[IFNAMSIZ + 9]; ++#ifdef IXGBE_TCP_TIMER ++ char tcp_timer_name[IFNAMSIZ + 9]; ++#endif ++ + }; + + enum ixbge_state_t { + __IXGBE_TESTING, + __IXGBE_RESETTING, + __IXGBE_DOWN, ++ __IXGBE_FDIR_INIT_DONE, + __IXGBE_SFP_MODULE_NOT_FOUND + }; + +-enum ixgbe_boards { +- board_82598, +-}; +- +-extern struct ixgbe_info ixgbe_82598_info; +-#ifdef CONFIG_DCBNL ++#ifdef CONFIG_DCB + extern struct dcbnl_rtnl_ops dcbnl_ops; + extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg, + struct ixgbe_dcb_config *dst_dcb_cfg, int tc_max); + #endif + ++/* needed by ixgbe_main.c */ ++extern int ixgbe_validate_mac_addr(u8 *mc_addr); ++extern void ixgbe_check_options(struct ixgbe_adapter *adapter); ++extern void ixgbe_assign_netdev_ops(struct net_device *netdev); + +- ++/* needed by ixgbe_ethtool.c */ + extern char ixgbe_driver_name[]; + extern const char ixgbe_driver_version[]; + +@@ -351,13 +506,24 @@ + extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); + extern void ixgbe_reset(struct ixgbe_adapter *adapter); + extern void ixgbe_set_ethtool_ops(struct net_device *netdev); +-extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); +-extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); +-extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); +-extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); ++extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *,struct ixgbe_ring *); ++extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *,struct ixgbe_ring *); ++extern void ixgbe_free_rx_resources(struct ixgbe_adapter *,struct ixgbe_ring *); ++extern void ixgbe_free_tx_resources(struct ixgbe_adapter *,struct ixgbe_ring *); + extern void ixgbe_update_stats(struct ixgbe_adapter *adapter); +-extern void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter); + extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); +-void ixgbe_napi_add_all(struct ixgbe_adapter *adapter); +-void ixgbe_napi_del_all(struct ixgbe_adapter *adapter); ++extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); ++extern bool ixgbe_is_ixgbe(struct pci_dev *pcidev); ++ ++ ++void ixgbe_set_rx_mode(struct net_device *netdev); ++ ++#ifdef ETHTOOL_OPS_COMPAT ++extern int ethtool_ioctl(struct ifreq *ifr); ++ ++#endif ++extern int ixgbe_dcb_netlink_register(void); ++extern int ixgbe_dcb_netlink_unregister(void); ++ ++ + #endif /* _IXGBE_H_ */ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_82598.c +--- a/drivers/net/ixgbe/ixgbe_82598.c Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe_82598.c Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -25,44 +25,209 @@ + + *******************************************************************************/ + +-#include +-#include +-#include +- +-#include "ixgbe.h" ++#include "ixgbe_type.h" ++#include "ixgbe_api.h" ++#include "ixgbe_common.h" + #include "ixgbe_phy.h" + +-#define IXGBE_82598_MAX_TX_QUEUES 32 +-#define IXGBE_82598_MAX_RX_QUEUES 64 +-#define IXGBE_82598_RAR_ENTRIES 16 +-#define IXGBE_82598_MC_TBL_SIZE 128 +-#define IXGBE_82598_VFT_TBL_SIZE 128 +- +-static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, ++u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw); ++s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); ++static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, + ixgbe_link_speed *speed, + bool *autoneg); ++static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); ++s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num); ++static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw); ++static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ++ ixgbe_link_speed *speed, bool *link_up, ++ bool link_up_wait_to_complete); ++static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, ++ ixgbe_link_speed speed, ++ bool autoneg, ++ bool autoneg_wait_to_complete); + static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw); + static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, + ixgbe_link_speed speed, + bool autoneg, + bool autoneg_wait_to_complete); +-static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, +- u8 *eeprom_data); ++static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); ++s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw); ++s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); ++static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); ++s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, ++ u32 vind, bool vlan_on); ++static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); ++s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val); ++s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val); ++s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, ++ u8 *eeprom_data); ++u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw); ++s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw); ++void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw); ++ + + /** +- */ +-static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) ++ * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout ++ * @hw: pointer to the HW structure ++ * ++ * The defaults for 82598 should be in the range of 50us to 50ms, ++ * however the hardware default for these parts is 500us to 1ms which is less ++ * than the 10ms recommended by the pci-e spec. To address this we need to ++ * increase the value to either 10ms to 250ms for capability version 1 config, ++ * or 16ms to 55ms for version 2. ++ **/ ++void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) ++{ ++ u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); ++ u16 pcie_devctl2; ++ ++ /* only take action if timeout value is defaulted to 0 */ ++ if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) ++ goto out; ++ ++ /* ++ * if capababilities version is type 1 we can write the ++ * timeout of 10ms to 250ms through the GCR register ++ */ ++ if (!(gcr & IXGBE_GCR_CAP_VER2)) { ++ gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; ++ goto out; ++ } ++ ++ /* ++ * for version 2 capabilities we need to write the config space ++ * directly in order to set the completion timeout value for ++ * 16ms to 55ms ++ */ ++ pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); ++ pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; ++ IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); ++out: ++ /* disable completion timeout resend */ ++ gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; ++ IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); ++} ++ ++/** ++ * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count ++ * @hw: pointer to hardware structure ++ * ++ * Read PCIe configuration space, and get the MSI-X vector count from ++ * the capabilities table. ++ **/ ++u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) ++{ ++ u32 msix_count = 18; ++ ++ if (hw->mac.msix_vectors_from_pcie) { ++ msix_count = IXGBE_READ_PCIE_WORD(hw, ++ IXGBE_PCIE_MSIX_82598_CAPS); ++ msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; ++ ++ /* MSI-X count is zero-based in HW, so increment to give ++ * proper value */ ++ msix_count++; ++ } ++ return msix_count; ++} ++ ++/** ++ * ixgbe_init_ops_82598 - Inits func ptrs and MAC type ++ * @hw: pointer to hardware structure ++ * ++ * Initialize the function pointers and assign the MAC type for 82598. ++ * Does not touch the hardware. ++ **/ ++s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw) ++{ ++ struct ixgbe_mac_info *mac = &hw->mac; ++ struct ixgbe_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ ++ ret_val = ixgbe_init_phy_ops_generic(hw); ++ ret_val = ixgbe_init_ops_generic(hw); ++ ++ /* PHY */ ++ phy->ops.init = &ixgbe_init_phy_ops_82598; ++ ++ /* MAC */ ++ mac->ops.start_hw = &ixgbe_start_hw_82598; ++ mac->ops.reset_hw = &ixgbe_reset_hw_82598; ++ mac->ops.get_media_type = &ixgbe_get_media_type_82598; ++ mac->ops.get_supported_physical_layer = ++ &ixgbe_get_supported_physical_layer_82598; ++ mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598; ++ mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598; ++ mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598; ++ ++ /* RAR, Multicast, VLAN */ ++ mac->ops.set_vmdq = &ixgbe_set_vmdq_82598; ++ mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598; ++ mac->ops.set_vfta = &ixgbe_set_vfta_82598; ++ mac->ops.clear_vfta = &ixgbe_clear_vfta_82598; ++ ++ /* Flow Control */ ++ mac->ops.fc_enable = &ixgbe_fc_enable_82598; ++ ++ mac->mcft_size = 128; ++ mac->vft_size = 128; ++ mac->num_rar_entries = 16; ++ mac->max_tx_queues = 32; ++ mac->max_rx_queues = 64; ++ mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); ++ ++ /* SFP+ Module */ ++ phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598; ++ ++ /* Link */ ++ mac->ops.check_link = &ixgbe_check_mac_link_82598; ++ mac->ops.setup_link = &ixgbe_setup_mac_link_82598; ++ mac->ops.setup_link_speed = &ixgbe_setup_mac_link_speed_82598; ++ mac->ops.get_link_capabilities = ++ &ixgbe_get_link_capabilities_82598; ++ ++ return ret_val; ++} ++ ++/** ++ * ixgbe_init_phy_ops_82598 - PHY/SFP specific init ++ * @hw: pointer to hardware structure ++ * ++ * Initialize any function pointers that were not able to be ++ * set during init_shared_code because the PHY/SFP type was ++ * not known. Perform the SFP init if necessary. ++ * ++ **/ ++s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) + { + struct ixgbe_mac_info *mac = &hw->mac; + struct ixgbe_phy_info *phy = &hw->phy; + s32 ret_val = 0; + u16 list_offset, data_offset; + +- /* Call PHY identify routine to get the phy type */ +- ixgbe_identify_phy_generic(hw); ++ /* Identify the PHY */ ++ phy->ops.identify(hw); + +- /* PHY Init */ +- switch (phy->type) { ++ /* Overwrite the link function pointers if copper PHY */ ++ if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { ++ mac->ops.setup_link = &ixgbe_setup_copper_link_82598; ++ mac->ops.setup_link_speed = ++ &ixgbe_setup_copper_link_speed_82598; ++ mac->ops.get_link_capabilities = ++ &ixgbe_get_copper_link_capabilities_generic; ++ } ++ ++ switch (hw->phy.type) { ++ case ixgbe_phy_tn: ++ phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; ++ phy->ops.check_link = &ixgbe_check_phy_link_tnx; ++ phy->ops.get_firmware_version = ++ &ixgbe_get_phy_firmware_version_tnx; ++ break; ++ case ixgbe_phy_aq: ++ phy->ops.get_firmware_version = ++ &ixgbe_get_phy_firmware_version_aq; ++ break; + case ixgbe_phy_nl: + phy->ops.reset = &ixgbe_reset_phy_nl; + +@@ -77,37 +242,38 @@ + + /* Check to see if SFP+ module is supported */ + ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, +- &list_offset, +- &data_offset); ++ &list_offset, ++ &data_offset); + if (ret_val != 0) { + ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; + goto out; + } + break; +- case ixgbe_phy_tn: +- phy->ops.check_link = &ixgbe_check_phy_link_tnx; +- phy->ops.get_firmware_version = +- &ixgbe_get_phy_firmware_version_tnx; +- break; + default: + break; + } + +- if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { +- mac->ops.setup_link = &ixgbe_setup_copper_link_82598; +- mac->ops.setup_link_speed = +- &ixgbe_setup_copper_link_speed_82598; +- mac->ops.get_link_capabilities = +- &ixgbe_get_copper_link_capabilities_82598; +- } ++out: ++ return ret_val; ++} + +- mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; +- mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; +- mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; +- mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; +- mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; ++/** ++ * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx ++ * @hw: pointer to hardware structure ++ * ++ * Starts the hardware using the generic start_hw function. ++ * Then set pcie completion timeout ++ **/ ++s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) ++{ ++ s32 ret_val = 0; + +-out: ++ ret_val = ixgbe_start_hw_generic(hw); ++ ++ /* set the completion timeout for interface */ ++ if (ret_val == 0) ++ ixgbe_set_pcie_completion_timeout(hw); ++ + return ret_val; + } + +@@ -124,18 +290,19 @@ + bool *autoneg) + { + s32 status = 0; +- s32 autoc_reg; ++ u32 autoc = 0; + +- autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); ++ /* ++ * Determine link capabilities based on the stored value of AUTOC, ++ * which represents EEPROM defaults. If AUTOC value has not been ++ * stored, use the current register value. ++ */ ++ if (hw->mac.orig_link_settings_stored) ++ autoc = hw->mac.orig_autoc; ++ else ++ autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); + +- if (hw->mac.link_settings_loaded) { +- autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE; +- autoc_reg &= ~IXGBE_AUTOC_LMS_MASK; +- autoc_reg |= hw->mac.link_attach_type; +- autoc_reg |= hw->mac.link_mode_select; +- } +- +- switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) { ++ switch (autoc & IXGBE_AUTOC_LMS_MASK) { + case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: + *speed = IXGBE_LINK_SPEED_1GB_FULL; + *autoneg = false; +@@ -154,9 +321,9 @@ + case IXGBE_AUTOC_LMS_KX4_AN: + case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: + *speed = IXGBE_LINK_SPEED_UNKNOWN; +- if (autoc_reg & IXGBE_AUTOC_KX4_SUPP) ++ if (autoc & IXGBE_AUTOC_KX4_SUPP) + *speed |= IXGBE_LINK_SPEED_10GB_FULL; +- if (autoc_reg & IXGBE_AUTOC_KX_SUPP) ++ if (autoc & IXGBE_AUTOC_KX_SUPP) + *speed |= IXGBE_LINK_SPEED_1GB_FULL; + *autoneg = true; + break; +@@ -164,38 +331,6 @@ + default: + status = IXGBE_ERR_LINK_SETUP; + break; +- } +- +- return status; +-} +- +-/** +- * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities +- * @hw: pointer to hardware structure +- * @speed: pointer to link speed +- * @autoneg: boolean auto-negotiation value +- * +- * Determines the link capabilities by reading the AUTOC register. +- **/ +-s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, +- ixgbe_link_speed *speed, +- bool *autoneg) +-{ +- s32 status = IXGBE_ERR_LINK_SETUP; +- u16 speed_ability; +- +- *speed = 0; +- *autoneg = true; +- +- status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, +- IXGBE_MDIO_PMA_PMD_DEV_TYPE, +- &speed_ability); +- +- if (status == 0) { +- if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) +- *speed |= IXGBE_LINK_SPEED_10GB_FULL; +- if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) +- *speed |= IXGBE_LINK_SPEED_1GB_FULL; + } + + return status; +@@ -211,8 +346,21 @@ + { + enum ixgbe_media_type media_type; + ++ /* Detect if there is a copper PHY attached. */ ++ if (hw->phy.type == ixgbe_phy_cu_unknown || ++ hw->phy.type == ixgbe_phy_tn || ++ hw->phy.type == ixgbe_phy_aq) { ++ media_type = ixgbe_media_type_copper; ++ goto out; ++ } ++ + /* Media type for I82598 is based on device ID */ + switch (hw->device_id) { ++ case IXGBE_DEV_ID_82598: ++ case IXGBE_DEV_ID_82598_BX: ++ /* Default device ID is mezzanine card KX/KX4 */ ++ media_type = ixgbe_media_type_backplane; ++ break; + case IXGBE_DEV_ID_82598AF_DUAL_PORT: + case IXGBE_DEV_ID_82598AF_SINGLE_PORT: + case IXGBE_DEV_ID_82598EB_CX4: +@@ -224,115 +372,109 @@ + media_type = ixgbe_media_type_fiber; + break; + case IXGBE_DEV_ID_82598AT: ++ case IXGBE_DEV_ID_82598AT2: + media_type = ixgbe_media_type_copper; + break; + default: + media_type = ixgbe_media_type_unknown; + break; + } +- ++out: + return media_type; + } + + /** +- * ixgbe_setup_fc_82598 - Configure flow control settings ++ * ixgbe_fc_enable_82598 - Enable flow control + * @hw: pointer to hardware structure + * @packetbuf_num: packet buffer number (0-7) + * +- * Configures the flow control settings based on SW configuration. This +- * function is used for 802.3x flow control configuration only. ++ * Enable flow control according to the current settings. + **/ +-s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num) ++s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) + { +- u32 frctl_reg; ++ s32 ret_val = 0; ++ u32 fctrl_reg; + u32 rmcs_reg; ++ u32 reg; + +- if (packetbuf_num < 0 || packetbuf_num > 7) { +- hw_dbg(hw, "Invalid packet buffer number [%d], expected range is" +- " 0-7\n", packetbuf_num); +- } ++#ifdef CONFIG_DCB ++ if (hw->fc.requested_mode == ixgbe_fc_pfc) ++ goto out; + +- frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); +- frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); ++#endif /* CONFIG_DCB */ ++ /* Negotiate the fc mode to use */ ++ ret_val = ixgbe_fc_autoneg(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Disable any previous flow control settings */ ++ fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); ++ fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); + + rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); + rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); + + /* +- * 10 gig parts do not have a word in the EEPROM to determine the +- * default flow control setting, so we explicitly set it to full. +- */ +- if (hw->fc.type == ixgbe_fc_default) +- hw->fc.type = ixgbe_fc_full; +- +- /* +- * We want to save off the original Flow Control configuration just in +- * case we get disconnected and then reconnected into a different hub +- * or switch with different Flow Control capabilities. +- */ +- hw->fc.original_type = hw->fc.type; +- +- /* +- * The possible values of the "flow_control" parameter are: ++ * The possible values of fc.current_mode are: + * 0: Flow control is completely disabled +- * 1: Rx flow control is enabled (we can receive pause frames but not +- * send pause frames). +- * 2: Tx flow control is enabled (we can send pause frames but we do not +- * support receiving pause frames) ++ * 1: Rx flow control is enabled (we can receive pause frames, ++ * but not send pause frames). ++ * 2: Tx flow control is enabled (we can send pause frames but ++ * we do not support receiving pause frames). + * 3: Both Rx and Tx flow control (symmetric) are enabled. ++#ifdef CONFIG_DCB ++ * 4: Priority Flow Control is enabled. ++#endif + * other: Invalid. + */ +- switch (hw->fc.type) { ++ switch (hw->fc.current_mode) { + case ixgbe_fc_none: ++ /* Flow control is disabled by software override or autoneg. ++ * The code below will actually disable it in the HW. ++ */ + break; + case ixgbe_fc_rx_pause: + /* +- * Rx Flow control is enabled, +- * and Tx Flow control is disabled. ++ * Rx Flow control is enabled and Tx Flow control is ++ * disabled by software override. Since there really ++ * isn't a way to advertise that we are capable of RX ++ * Pause ONLY, we will advertise that we support both ++ * symmetric and asymmetric Rx PAUSE. Later, we will ++ * disable the adapter's ability to send PAUSE frames. + */ +- frctl_reg |= IXGBE_FCTRL_RFCE; ++ fctrl_reg |= IXGBE_FCTRL_RFCE; + break; + case ixgbe_fc_tx_pause: + /* +- * Tx Flow control is enabled, and Rx Flow control is disabled, +- * by a software over-ride. ++ * Tx Flow control is enabled, and Rx Flow control is ++ * disabled by software override. + */ + rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; + break; + case ixgbe_fc_full: +- /* +- * Flow control (both Rx and Tx) is enabled by a software +- * over-ride. +- */ +- frctl_reg |= IXGBE_FCTRL_RFCE; ++ /* Flow control (both Rx and Tx) is enabled by SW override. */ ++ fctrl_reg |= IXGBE_FCTRL_RFCE; + rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; + break; ++#ifdef CONFIG_DCB ++ case ixgbe_fc_pfc: ++ goto out; ++ break; ++#endif /* CONFIG_DCB */ + default: +- /* We should never get here. The value should be 0-3. */ + hw_dbg(hw, "Flow control param set incorrectly\n"); ++ ret_val = -IXGBE_ERR_CONFIG; ++ goto out; + break; + } + +- /* Enable 802.3x based flow control settings. */ +- IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg); ++ /* Set 802.3x based flow control settings. */ ++ fctrl_reg |= IXGBE_FCTRL_DPF; ++ IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); + IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); + +- /* +- * Check for invalid software configuration, zeros are completely +- * invalid for all parameters used past this point, and if we enable +- * flow control with zero water marks, we blast flow control packets. +- */ +- if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { +- hw_dbg(hw, "Flow control structure initialized incorrectly\n"); +- return IXGBE_ERR_INVALID_LINK_SETTINGS; +- } +- +- /* +- * We need to set up the Receive Threshold high and low water +- * marks as well as (optionally) enabling the transmission of +- * XON frames. +- */ +- if (hw->fc.type & ixgbe_fc_tx_pause) { ++ /* Set up and enable Rx high/low water mark thresholds, enable XON. */ ++ if (hw->fc.current_mode & ixgbe_fc_tx_pause) { + if (hw->fc.send_xon) { + IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), + (hw->fc.low_water | IXGBE_FCRTL_XONE)); +@@ -340,14 +482,23 @@ + IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), + hw->fc.low_water); + } ++ + IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), +- (hw->fc.high_water)|IXGBE_FCRTH_FCEN); ++ (hw->fc.high_water | IXGBE_FCRTH_FCEN)); + } + +- IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time); ++ /* Configure pause time (2 TCs per register) */ ++ reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); ++ if ((packetbuf_num & 1) == 0) ++ reg = (reg & 0xFFFF0000) | hw->fc.pause_time; ++ else ++ reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); ++ IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); ++ + IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); + +- return 0; ++out: ++ return ret_val; + } + + /** +@@ -364,27 +515,17 @@ + u32 i; + s32 status = 0; + ++ /* Restart link */ + autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); +- +- if (hw->mac.link_settings_loaded) { +- autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE; +- autoc_reg &= ~IXGBE_AUTOC_LMS_MASK; +- autoc_reg |= hw->mac.link_attach_type; +- autoc_reg |= hw->mac.link_mode_select; +- +- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); +- IXGBE_WRITE_FLUSH(hw); +- msleep(50); +- } +- +- /* Restart link */ + autoc_reg |= IXGBE_AUTOC_AN_RESTART; + IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); + + /* Only poll for autoneg to complete if specified to do so */ + if (hw->phy.autoneg_wait_to_complete) { +- if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN || +- hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { ++ if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == ++ IXGBE_AUTOC_LMS_KX4_AN || ++ (autoc_reg & IXGBE_AUTOC_LMS_MASK) == ++ IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { + links_reg = 0; /* Just in case Autoneg time = 0 */ + for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { + links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); +@@ -398,14 +539,6 @@ + } + } + } +- +- /* +- * We want to save off the original Flow Control configuration just in +- * case we get disconnected and then reconnected into a different hub +- * or switch with different Flow Control capabilities. +- */ +- hw->fc.original_type = hw->fc.type; +- ixgbe_setup_fc_82598(hw, 0); + + /* Add delay to filter out noises during initial link setup */ + msleep(50); +@@ -431,16 +564,16 @@ + u16 link_reg, adapt_comp_reg; + + /* +- * SERDES PHY requires us to read link status from register 0xC79F. +- * Bit 0 set indicates link is up/ready; clear indicates link down. +- * OxC00C is read to check that the XAUI lanes are active. Bit 0 +- * clear indicates active; set indicates inactive. ++ * SERDES PHY requires us to read link status from undocumented ++ * register 0xC79F. Bit 0 set indicates link is up/ready; clear ++ * indicates link down. OxC00C is read to check that the XAUI lanes ++ * are active. Bit 0 clear indicates active; set indicates inactive. + */ + if (hw->phy.type == ixgbe_phy_nl) { + hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); + hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); + hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, +- &adapt_comp_reg); ++ &adapt_comp_reg); + if (link_up_wait_to_complete) { + for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { + if ((link_reg & 1) && +@@ -452,11 +585,11 @@ + } + msleep(100); + hw->phy.ops.read_reg(hw, 0xC79F, +- IXGBE_TWINAX_DEV, +- &link_reg); ++ IXGBE_TWINAX_DEV, ++ &link_reg); + hw->phy.ops.read_reg(hw, 0xC00C, +- IXGBE_TWINAX_DEV, +- &adapt_comp_reg); ++ IXGBE_TWINAX_DEV, ++ &adapt_comp_reg); + } + } else { + if ((link_reg & 1) && +@@ -494,52 +627,62 @@ + else + *speed = IXGBE_LINK_SPEED_1GB_FULL; + ++ /* if link is down, zero out the current_mode */ ++ if (*link_up == false) { ++ hw->fc.current_mode = ixgbe_fc_none; ++ hw->fc.fc_was_autonegged = false; ++ } + out: + return 0; + } +- + + /** + * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed + * @hw: pointer to hardware structure + * @speed: new link speed +- * @autoneg: true if auto-negotiation enabled +- * @autoneg_wait_to_complete: true if waiting is needed to complete ++ * @autoneg: true if autonegotiation enabled ++ * @autoneg_wait_to_complete: true when waiting for completion is needed + * + * Set the link speed in the AUTOC register and restarts link. + **/ + static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, +- ixgbe_link_speed speed, bool autoneg, +- bool autoneg_wait_to_complete) ++ ixgbe_link_speed speed, bool autoneg, ++ bool autoneg_wait_to_complete) + { +- s32 status = 0; ++ s32 status = 0; ++ ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; ++ u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); ++ u32 autoc = curr_autoc; ++ u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; + +- /* If speed is 10G, then check for CX4 or XAUI. */ +- if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && +- (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) { +- hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN; +- } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) { +- hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN; +- } else if (autoneg) { +- /* BX mode - Autonegotiate 1G */ +- if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD)) +- hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN; +- else /* KX/KX4 mode */ +- hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN; +- } else { ++ /* Check to see if speed passed in is supported. */ ++ ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); ++ speed &= link_capabilities; ++ ++ if (speed == IXGBE_LINK_SPEED_UNKNOWN) + status = IXGBE_ERR_LINK_SETUP; ++ ++ /* Set KX4/KX support according to speed requested */ ++ else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || ++ link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { ++ autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; ++ if (speed & IXGBE_LINK_SPEED_10GB_FULL) ++ autoc |= IXGBE_AUTOC_KX4_SUPP; ++ if (speed & IXGBE_LINK_SPEED_1GB_FULL) ++ autoc |= IXGBE_AUTOC_KX_SUPP; ++ if (autoc != curr_autoc) ++ IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); + } + + if (status == 0) { + hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete; + +- hw->mac.link_settings_loaded = true; + /* + * Setup and restart the link based on the new values in + * ixgbe_hw This will write the AUTOC register based on the new + * stored values + */ +- ixgbe_setup_mac_link_82598(hw); ++ status = ixgbe_setup_mac_link_82598(hw); + } + + return status; +@@ -561,10 +704,6 @@ + + /* Restart autonegotiation on PHY */ + status = hw->phy.ops.setup_link(hw); +- +- /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */ +- hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); +- hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; + + /* Set up MAC */ + ixgbe_setup_mac_link_82598(hw); +@@ -591,11 +730,6 @@ + /* Setup the PHY according to input speed */ + status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, + autoneg_wait_to_complete); +- +- /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */ +- hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); +- hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; +- + /* Set up MAC */ + ixgbe_setup_mac_link_82598(hw); + +@@ -613,6 +747,7 @@ + static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) + { + s32 status = 0; ++ s32 phy_status = 0; + u32 ctrl; + u32 gheccr; + u32 i; +@@ -656,14 +791,26 @@ + } + + /* Reset PHY */ +- if (hw->phy.reset_disable == false) ++ if (hw->phy.reset_disable == false) { ++ /* PHY ops must be identified and initialized prior to reset */ ++ ++ /* Init PHY and function pointers, perform SFP setup */ ++ phy_status = hw->phy.ops.init(hw); ++ if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) ++ goto reset_hw_out; ++ else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) ++ goto no_phy_reset; ++ + hw->phy.ops.reset(hw); ++ } + ++no_phy_reset: + /* + * Prevent the PCI-E bus from from hanging by disabling PCI-E master + * access and verify no pending requests before reset + */ +- if (ixgbe_disable_pcie_master(hw) != 0) { ++ status = ixgbe_disable_pcie_master(hw); ++ if (status != 0) { + status = IXGBE_ERR_MASTER_REQUESTS_PENDING; + hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); + } +@@ -695,29 +842,31 @@ + IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); + + /* +- * AUTOC register which stores link settings gets cleared +- * and reloaded from EEPROM after reset. We need to restore +- * our stored value from init in case SW changed the attach +- * type or speed. If this is the first time and link settings +- * have not been stored, store default settings from AUTOC. ++ * Store the original AUTOC value if it has not been ++ * stored off yet. Otherwise restore the stored original ++ * AUTOC value since the reset operation sets back to deaults. + */ + autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); +- if (hw->mac.link_settings_loaded) { +- autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE); +- autoc &= ~(IXGBE_AUTOC_LMS_MASK); +- autoc |= hw->mac.link_attach_type; +- autoc |= hw->mac.link_mode_select; +- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); +- } else { +- hw->mac.link_attach_type = +- (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE); +- hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK); +- hw->mac.link_settings_loaded = true; +- } ++ if (hw->mac.orig_link_settings_stored == false) { ++ hw->mac.orig_autoc = autoc; ++ hw->mac.orig_link_settings_stored = true; ++ } else if (autoc != hw->mac.orig_autoc) ++ IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); + + /* Store the permanent mac address */ + hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); + ++ /* ++ * Store MAC address from RAR0, clear receive address registers, and ++ * clear the multicast table ++ */ ++ hw->mac.ops.init_rx_addrs(hw); ++ ++ ++ ++reset_hw_out: ++ if (phy_status != 0) ++ status = phy_status; + return status; + } + +@@ -749,6 +898,7 @@ + u32 rar_high; + u32 rar_entries = hw->mac.num_rar_entries; + ++ + if (rar < rar_entries) { + rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); + if (rar_high & IXGBE_RAH_VIND_MASK) { +@@ -772,7 +922,7 @@ + * Turn on/off specified VLAN in the VLAN filter table. + **/ + s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, +- bool vlan_on) ++ bool vlan_on) + { + u32 regindex; + u32 bitindex; +@@ -833,61 +983,6 @@ + } + + /** +- * ixgbe_blink_led_start_82598 - Blink LED based on index. +- * @hw: pointer to hardware structure +- * @index: led number to blink +- **/ +-static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index) +-{ +- ixgbe_link_speed speed = 0; +- bool link_up = 0; +- u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); +- u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); +- +- /* +- * Link must be up to auto-blink the LEDs on the 82598EB MAC; +- * force it if link is down. +- */ +- hw->mac.ops.check_link(hw, &speed, &link_up, false); +- +- if (!link_up) { +- autoc_reg |= IXGBE_AUTOC_FLU; +- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); +- msleep(10); +- } +- +- led_reg &= ~IXGBE_LED_MODE_MASK(index); +- led_reg |= IXGBE_LED_BLINK(index); +- IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); +- IXGBE_WRITE_FLUSH(hw); +- +- return 0; +-} +- +-/** +- * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index. +- * @hw: pointer to hardware structure +- * @index: led number to stop blinking +- **/ +-static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index) +-{ +- u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); +- u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); +- +- autoc_reg &= ~IXGBE_AUTOC_FLU; +- autoc_reg |= IXGBE_AUTOC_AN_RESTART; +- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); +- +- led_reg &= ~IXGBE_LED_MODE_MASK(index); +- led_reg &= ~IXGBE_LED_BLINK(index); +- led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); +- IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); +- IXGBE_WRITE_FLUSH(hw); +- +- return 0; +-} +- +-/** + * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register + * @hw: pointer to hardware structure + * @reg: analog register to read +@@ -930,16 +1025,15 @@ + } + + /** +- * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit EEPROM word of an SFP+ module +- * over I2C interface through an intermediate phy. ++ * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. + * @hw: pointer to hardware structure + * @byte_offset: EEPROM byte offset to read + * @eeprom_data: value read + * +- * Performs byte read operation to SFP module's EEPROM over I2C interface. ++ * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. + **/ + s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, +- u8 *eeprom_data) ++ u8 *eeprom_data) + { + s32 status = 0; + u16 sfp_addr = 0; +@@ -949,23 +1043,23 @@ + + if (hw->phy.type == ixgbe_phy_nl) { + /* +- * phy SDA/SCL registers are at addresses 0xC30A to ++ * NetLogic phy SDA/SCL registers are at addresses 0xC30A to + * 0xC30D. These registers are used to talk to the SFP+ + * module's EEPROM through the SDA/SCL (I2C) interface. + */ + sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; + sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); + hw->phy.ops.write_reg(hw, +- IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, +- IXGBE_MDIO_PMA_PMD_DEV_TYPE, +- sfp_addr); ++ IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, ++ IXGBE_MDIO_PMA_PMD_DEV_TYPE, ++ sfp_addr); + + /* Poll status */ + for (i = 0; i < 100; i++) { + hw->phy.ops.read_reg(hw, +- IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, +- IXGBE_MDIO_PMA_PMD_DEV_TYPE, +- &sfp_stat); ++ IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, ++ IXGBE_MDIO_PMA_PMD_DEV_TYPE, ++ &sfp_stat); + sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; + if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) + break; +@@ -980,7 +1074,7 @@ + + /* Read data */ + hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, +- IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); ++ IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); + + *eeprom_data = (u8)(sfp_data >> 8); + } else { +@@ -998,27 +1092,59 @@ + * + * Determines physical layer capabilities of the current configuration. + **/ +-s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) ++u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) + { +- s32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; ++ u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; ++ u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); ++ u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; ++ u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; ++ u16 ext_ability = 0; + +- switch (hw->device_id) { +- case IXGBE_DEV_ID_82598EB_CX4: +- case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: +- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; ++ hw->phy.ops.identify(hw); ++ ++ /* Copper PHY must be checked before AUTOC LMS to determine correct ++ * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ ++ if (hw->phy.type == ixgbe_phy_tn || ++ hw->phy.type == ixgbe_phy_cu_unknown) { ++ hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, ++ IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); ++ if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) ++ physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; ++ if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) ++ physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; ++ if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) ++ physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; ++ goto out; ++ } ++ ++ switch (autoc & IXGBE_AUTOC_LMS_MASK) { ++ case IXGBE_AUTOC_LMS_1G_AN: ++ case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: ++ if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) ++ physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; ++ else ++ physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; + break; +- case IXGBE_DEV_ID_82598_DA_DUAL_PORT: +- physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; ++ case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: ++ if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) ++ physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; ++ else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) ++ physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; ++ else /* XAUI */ ++ physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; + break; +- case IXGBE_DEV_ID_82598AF_DUAL_PORT: +- case IXGBE_DEV_ID_82598AF_SINGLE_PORT: +- case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: +- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; ++ case IXGBE_AUTOC_LMS_KX4_AN: ++ case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: ++ if (autoc & IXGBE_AUTOC_KX_SUPP) ++ physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; ++ if (autoc & IXGBE_AUTOC_KX4_SUPP) ++ physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; + break; +- case IXGBE_DEV_ID_82598EB_XF_LR: +- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; ++ default: + break; +- case IXGBE_DEV_ID_82598EB_SFP_LOM: ++ } ++ ++ if (hw->phy.type == ixgbe_phy_nl) { + hw->phy.ops.identify_sfp(hw); + + switch (hw->phy.sfp_type) { +@@ -1035,76 +1161,57 @@ + physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; + break; + } ++ } ++ ++ switch (hw->device_id) { ++ case IXGBE_DEV_ID_82598_DA_DUAL_PORT: ++ physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; + break; +- case IXGBE_DEV_ID_82598AT: +- physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T | +- IXGBE_PHYSICAL_LAYER_1000BASE_T); ++ case IXGBE_DEV_ID_82598AF_DUAL_PORT: ++ case IXGBE_DEV_ID_82598AF_SINGLE_PORT: ++ case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: ++ physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; + break; +- ++ case IXGBE_DEV_ID_82598EB_XF_LR: ++ physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; ++ break; + default: +- physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; + break; + } + ++out: + return physical_layer; + } + +-static struct ixgbe_mac_operations mac_ops_82598 = { +- .init_hw = &ixgbe_init_hw_generic, +- .reset_hw = &ixgbe_reset_hw_82598, +- .start_hw = &ixgbe_start_hw_generic, +- .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, +- .get_media_type = &ixgbe_get_media_type_82598, +- .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, +- .get_mac_addr = &ixgbe_get_mac_addr_generic, +- .stop_adapter = &ixgbe_stop_adapter_generic, +- .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, +- .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, +- .setup_link = &ixgbe_setup_mac_link_82598, +- .setup_link_speed = &ixgbe_setup_mac_link_speed_82598, +- .check_link = &ixgbe_check_mac_link_82598, +- .get_link_capabilities = &ixgbe_get_link_capabilities_82598, +- .led_on = &ixgbe_led_on_generic, +- .led_off = &ixgbe_led_off_generic, +- .blink_led_start = &ixgbe_blink_led_start_82598, +- .blink_led_stop = &ixgbe_blink_led_stop_82598, +- .set_rar = &ixgbe_set_rar_generic, +- .clear_rar = &ixgbe_clear_rar_generic, +- .set_vmdq = &ixgbe_set_vmdq_82598, +- .clear_vmdq = &ixgbe_clear_vmdq_82598, +- .init_rx_addrs = &ixgbe_init_rx_addrs_generic, +- .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic, +- .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, +- .enable_mc = &ixgbe_enable_mc_generic, +- .disable_mc = &ixgbe_disable_mc_generic, +- .clear_vfta = &ixgbe_clear_vfta_82598, +- .set_vfta = &ixgbe_set_vfta_82598, +- .setup_fc = &ixgbe_setup_fc_82598, +-}; ++/** ++ * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple ++ * port devices. ++ * @hw: pointer to the HW structure ++ * ++ * Calls common function and corrects issue with some single port devices ++ * that enable LAN1 but not LAN0. ++ **/ ++void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) ++{ ++ struct ixgbe_bus_info *bus = &hw->bus; ++ u16 pci_gen, pci_ctrl2; + +-static struct ixgbe_eeprom_operations eeprom_ops_82598 = { +- .init_params = &ixgbe_init_eeprom_params_generic, +- .read = &ixgbe_read_eeprom_generic, +- .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, +- .update_checksum = &ixgbe_update_eeprom_checksum_generic, +-}; ++ ixgbe_set_lan_id_multi_port_pcie(hw); + +-static struct ixgbe_phy_operations phy_ops_82598 = { +- .identify = &ixgbe_identify_phy_generic, +- .identify_sfp = &ixgbe_identify_sfp_module_generic, +- .reset = &ixgbe_reset_phy_generic, +- .read_reg = &ixgbe_read_phy_reg_generic, +- .write_reg = &ixgbe_write_phy_reg_generic, +- .setup_link = &ixgbe_setup_phy_link_generic, +- .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, +- .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, +-}; ++ /* check if LAN0 is disabled */ ++ hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); ++ if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { + +-struct ixgbe_info ixgbe_82598_info = { +- .mac = ixgbe_mac_82598EB, +- .get_invariants = &ixgbe_get_invariants_82598, +- .mac_ops = &mac_ops_82598, +- .eeprom_ops = &eeprom_ops_82598, +- .phy_ops = &phy_ops_82598, +-}; ++ hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); + ++ /* if LAN0 is completely disabled force function to 0 */ ++ if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && ++ !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && ++ !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { ++ ++ bus->func = 0; ++ } ++ } ++} ++ ++ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_82599.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/ixgbe/ixgbe_82599.c Wed Aug 05 11:05:50 2009 +0100 +@@ -0,0 +1,2658 @@ ++/******************************************************************************* ++ ++ Intel 10 Gigabit PCI Express Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "ixgbe_type.h" ++#include "ixgbe_api.h" ++#include "ixgbe_common.h" ++#include "ixgbe_phy.h" ++ ++u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw); ++s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); ++s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, ++ ixgbe_link_speed *speed, ++ bool *autoneg); ++enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); ++s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw); ++s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw, ++ ixgbe_link_speed speed, bool autoneg, ++ bool autoneg_wait_to_complete); ++s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw); ++s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ++ ixgbe_link_speed *speed, ++ bool *link_up, bool link_up_wait_to_complete); ++s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw, ++ ixgbe_link_speed speed, ++ bool autoneg, ++ bool autoneg_wait_to_complete); ++static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw); ++static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw, ++ ixgbe_link_speed speed, ++ bool autoneg, ++ bool autoneg_wait_to_complete); ++s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw); ++void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw); ++s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw); ++s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq); ++s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq); ++s32 ixgbe_insert_mac_addr_82599(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); ++s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, ++ u32 vind, bool vlan_on); ++s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw); ++s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw); ++s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val); ++s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val); ++s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw); ++s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw); ++s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw); ++u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); ++s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval); ++s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw, ++ u16 *san_mac_offset); ++s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr); ++s32 ixgbe_set_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr); ++s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps); ++static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); ++ ++void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) ++{ ++ struct ixgbe_mac_info *mac = &hw->mac; ++ ++ if (hw->phy.multispeed_fiber) { ++ /* Set up dual speed SFP+ support */ ++ mac->ops.setup_link = ++ &ixgbe_setup_mac_link_multispeed_fiber; ++ mac->ops.setup_link_speed = ++ &ixgbe_setup_mac_link_speed_multispeed_fiber; ++ } else { ++ mac->ops.setup_link = ++ &ixgbe_setup_mac_link_82599; ++ mac->ops.setup_link_speed = ++ &ixgbe_setup_mac_link_speed_82599; ++ } ++} ++ ++/** ++ * ixgbe_init_phy_ops_82599 - PHY/SFP specific init ++ * @hw: pointer to hardware structure ++ * ++ * Initialize any function pointers that were not able to be ++ * set during init_shared_code because the PHY/SFP type was ++ * not known. Perform the SFP init if necessary. ++ * ++ **/ ++s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) ++{ ++ struct ixgbe_mac_info *mac = &hw->mac; ++ struct ixgbe_phy_info *phy = &hw->phy; ++ s32 ret_val = 0; ++ ++ /* Identify the PHY or SFP module */ ++ ret_val = phy->ops.identify(hw); ++ if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) ++ goto init_phy_ops_out; ++ ++ /* Setup function pointers based on detected SFP module and speeds */ ++ ixgbe_init_mac_link_ops_82599(hw); ++ if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) ++ hw->phy.ops.reset = NULL; ++ ++ /* If copper media, overwrite with copper function pointers */ ++ if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { ++ mac->ops.setup_link = &ixgbe_setup_copper_link_82599; ++ mac->ops.setup_link_speed = ++ &ixgbe_setup_copper_link_speed_82599; ++ mac->ops.get_link_capabilities = ++ &ixgbe_get_copper_link_capabilities_generic; ++ } ++ ++ /* Set necessary function pointers based on phy type */ ++ switch (hw->phy.type) { ++ case ixgbe_phy_tn: ++ phy->ops.check_link = &ixgbe_check_phy_link_tnx; ++ phy->ops.get_firmware_version = ++ &ixgbe_get_phy_firmware_version_tnx; ++ break; ++ case ixgbe_phy_aq: ++ phy->ops.get_firmware_version = ++ &ixgbe_get_phy_firmware_version_aq; ++ break; ++ default: ++ break; ++ } ++init_phy_ops_out: ++ return ret_val; ++} ++ ++s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) ++{ ++ s32 ret_val = 0; ++ u16 list_offset, data_offset, data_value; ++ ++ if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { ++ ixgbe_init_mac_link_ops_82599(hw); ++ ++ hw->phy.ops.reset = NULL; ++ ++ ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, ++ &data_offset); ++ if (ret_val != 0) ++ goto setup_sfp_out; ++ ++ /* PHY config will finish before releasing the semaphore */ ++ ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); ++ if (ret_val != 0) { ++ ret_val = IXGBE_ERR_SWFW_SYNC; ++ goto setup_sfp_out; ++ } ++ ++ hw->eeprom.ops.read(hw, ++data_offset, &data_value); ++ while (data_value != 0xffff) { ++ IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); ++ IXGBE_WRITE_FLUSH(hw); ++ hw->eeprom.ops.read(hw, ++data_offset, &data_value); ++ } ++ /* Now restart DSP by setting Restart_AN */ ++ IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ++ (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART)); ++ ++ /* Release the semaphore */ ++ ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); ++ /* Delay obtaining semaphore again to allow FW access */ ++ msleep(hw->eeprom.semaphore_delay); ++ } ++ ++setup_sfp_out: ++ return ret_val; ++} ++ ++/** ++ * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count ++ * @hw: pointer to hardware structure ++ * ++ * Read PCIe configuration space, and get the MSI-X vector count from ++ * the capabilities table. ++ **/ ++u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw) ++{ ++ u32 msix_count = 64; ++ ++ if (hw->mac.msix_vectors_from_pcie) { ++ msix_count = IXGBE_READ_PCIE_WORD(hw, ++ IXGBE_PCIE_MSIX_82599_CAPS); ++ msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; ++ ++ /* MSI-X count is zero-based in HW, so increment to give ++ * proper value */ ++ msix_count++; ++ } ++ ++ return msix_count; ++} ++ ++/** ++ * ixgbe_init_ops_82599 - Inits func ptrs and MAC type ++ * @hw: pointer to hardware structure ++ * ++ * Initialize the function pointers and assign the MAC type for 82599. ++ * Does not touch the hardware. ++ **/ ++ ++s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) ++{ ++ struct ixgbe_mac_info *mac = &hw->mac; ++ struct ixgbe_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ ++ ret_val = ixgbe_init_phy_ops_generic(hw); ++ ret_val = ixgbe_init_ops_generic(hw); ++ ++ /* PHY */ ++ phy->ops.identify = &ixgbe_identify_phy_82599; ++ phy->ops.init = &ixgbe_init_phy_ops_82599; ++ ++ /* MAC */ ++ mac->ops.reset_hw = &ixgbe_reset_hw_82599; ++ mac->ops.get_media_type = &ixgbe_get_media_type_82599; ++ mac->ops.get_supported_physical_layer = ++ &ixgbe_get_supported_physical_layer_82599; ++ mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599; ++ mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599; ++ mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599; ++ mac->ops.start_hw = &ixgbe_start_hw_rev_1_82599; ++ mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_82599; ++ mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_82599; ++ mac->ops.get_device_caps = &ixgbe_get_device_caps_82599; ++ ++ /* RAR, Multicast, VLAN */ ++ mac->ops.set_vmdq = &ixgbe_set_vmdq_82599; ++ mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82599; ++ mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_82599; ++ mac->rar_highwater = 1; ++ mac->ops.set_vfta = &ixgbe_set_vfta_82599; ++ mac->ops.clear_vfta = &ixgbe_clear_vfta_82599; ++ mac->ops.init_uta_tables = &ixgbe_init_uta_tables_82599; ++ mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599; ++ ++ /* Link */ ++ mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599; ++ mac->ops.check_link = &ixgbe_check_mac_link_82599; ++ ixgbe_init_mac_link_ops_82599(hw); ++ ++ mac->mcft_size = 128; ++ mac->vft_size = 128; ++ mac->num_rar_entries = 128; ++ mac->max_tx_queues = 128; ++ mac->max_rx_queues = 128; ++ mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw); ++ ++ ++ return ret_val; ++} ++ ++/** ++ * ixgbe_get_link_capabilities_82599 - Determines link capabilities ++ * @hw: pointer to hardware structure ++ * @speed: pointer to link speed ++ * @negotiation: true when autoneg or autotry is enabled ++ * ++ * Determines the link capabilities by reading the AUTOC register. ++ **/ ++s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, ++ ixgbe_link_speed *speed, ++ bool *negotiation) ++{ ++ s32 status = 0; ++ u32 autoc = 0; ++ ++ /* ++ * Determine link capabilities based on the stored value of AUTOC, ++ * which represents EEPROM defaults. If AUTOC value has not ++ * been stored, use the current register values. ++ */ ++ if (hw->mac.orig_link_settings_stored) ++ autoc = hw->mac.orig_autoc; ++ else ++ autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); ++ ++ switch (autoc & IXGBE_AUTOC_LMS_MASK) { ++ case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: ++ *speed = IXGBE_LINK_SPEED_1GB_FULL; ++ *negotiation = false; ++ break; ++ ++ case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: ++ *speed = IXGBE_LINK_SPEED_10GB_FULL; ++ *negotiation = false; ++ break; ++ ++ case IXGBE_AUTOC_LMS_1G_AN: ++ *speed = IXGBE_LINK_SPEED_1GB_FULL; ++ *negotiation = true; ++ break; ++ ++ case IXGBE_AUTOC_LMS_10G_SERIAL: ++ *speed = IXGBE_LINK_SPEED_10GB_FULL; ++ *negotiation = false; ++ break; ++ ++ case IXGBE_AUTOC_LMS_KX4_KX_KR: ++ case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: ++ *speed = IXGBE_LINK_SPEED_UNKNOWN; ++ if (autoc & IXGBE_AUTOC_KR_SUPP) ++ *speed |= IXGBE_LINK_SPEED_10GB_FULL; ++ if (autoc & IXGBE_AUTOC_KX4_SUPP) ++ *speed |= IXGBE_LINK_SPEED_10GB_FULL; ++ if (autoc & IXGBE_AUTOC_KX_SUPP) ++ *speed |= IXGBE_LINK_SPEED_1GB_FULL; ++ *negotiation = true; ++ break; ++ ++ case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: ++ *speed = IXGBE_LINK_SPEED_100_FULL; ++ if (autoc & IXGBE_AUTOC_KR_SUPP) ++ *speed |= IXGBE_LINK_SPEED_10GB_FULL; ++ if (autoc & IXGBE_AUTOC_KX4_SUPP) ++ *speed |= IXGBE_LINK_SPEED_10GB_FULL; ++ if (autoc & IXGBE_AUTOC_KX_SUPP) ++ *speed |= IXGBE_LINK_SPEED_1GB_FULL; ++ *negotiation = true; ++ break; ++ ++ case IXGBE_AUTOC_LMS_SGMII_1G_100M: ++ *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; ++ *negotiation = false; ++ break; ++ ++ default: ++ status = IXGBE_ERR_LINK_SETUP; ++ goto out; ++ break; ++ } ++ ++ if (hw->phy.multispeed_fiber) { ++ *speed |= IXGBE_LINK_SPEED_10GB_FULL | ++ IXGBE_LINK_SPEED_1GB_FULL; ++ *negotiation = true; ++ } ++ ++out: ++ return status; ++} ++ ++/** ++ * ixgbe_get_media_type_82599 - Get media type ++ * @hw: pointer to hardware structure ++ * ++ * Returns the media type (fiber, copper, backplane) ++ **/ ++enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) ++{ ++ enum ixgbe_media_type media_type; ++ ++ /* Detect if there is a copper PHY attached. */ ++ if (hw->phy.type == ixgbe_phy_cu_unknown || ++ hw->phy.type == ixgbe_phy_tn || ++ hw->phy.type == ixgbe_phy_aq) { ++ media_type = ixgbe_media_type_copper; ++ goto out; ++ } ++ ++ switch (hw->device_id) { ++ case IXGBE_DEV_ID_82599_KX4: ++ case IXGBE_DEV_ID_82599_XAUI_LOM: ++ /* Default device ID is mezzanine card KX/KX4 */ ++ media_type = ixgbe_media_type_backplane; ++ break; ++ case IXGBE_DEV_ID_82599_SFP: ++ media_type = ixgbe_media_type_fiber; ++ break; ++ default: ++ media_type = ixgbe_media_type_unknown; ++ break; ++ } ++out: ++ return media_type; ++} ++ ++/** ++ * ixgbe_setup_mac_link_82599 - Setup MAC link settings ++ * @hw: pointer to hardware structure ++ * ++ * Configures link settings based on values in the ixgbe_hw struct. ++ * Restarts the link. Performs autonegotiation if needed. ++ **/ ++s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw) ++{ ++ u32 autoc_reg; ++ u32 links_reg; ++ u32 i; ++ s32 status = 0; ++ ++ /* Restart link */ ++ autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); ++ autoc_reg |= IXGBE_AUTOC_AN_RESTART; ++ IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); ++ ++ /* Only poll for autoneg to complete if specified to do so */ ++ if (hw->phy.autoneg_wait_to_complete) { ++ if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == ++ IXGBE_AUTOC_LMS_KX4_KX_KR || ++ (autoc_reg & IXGBE_AUTOC_LMS_MASK) == ++ IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ++ || (autoc_reg & IXGBE_AUTOC_LMS_MASK) == ++ IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { ++ links_reg = 0; /* Just in case Autoneg time = 0 */ ++ for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { ++ links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); ++ if (links_reg & IXGBE_LINKS_KX_AN_COMP) ++ break; ++ msleep(100); ++ } ++ if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { ++ status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; ++ hw_dbg(hw, "Autoneg did not complete.\n"); ++ } ++ } ++ } ++ ++ /* Add delay to filter out noises during initial link setup */ ++ msleep(50); ++ ++ return status; ++} ++ ++/** ++ * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings ++ * @hw: pointer to hardware structure ++ * ++ * Configures link settings based on values in the ixgbe_hw struct. ++ * Restarts the link for multi-speed fiber at 1G speed, if link ++ * fails at 10G. ++ * Performs autonegotiation if needed. ++ **/ ++s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw) ++{ ++ s32 status = 0; ++ ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG; ++ status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, ++ link_speed, true, true); ++ return status; ++} ++ ++/** ++ * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed ++ * @hw: pointer to hardware structure ++ * @speed: new link speed ++ * @autoneg: true if autonegotiation enabled ++ * @autoneg_wait_to_complete: true when waiting for completion is needed ++ * ++ * Set the link speed in the AUTOC register and restarts link. ++ **/ ++s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw, ++ ixgbe_link_speed speed, bool autoneg, ++ bool autoneg_wait_to_complete) ++{ ++ s32 status = 0; ++ ixgbe_link_speed link_speed; ++ ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; ++ u32 speedcnt = 0; ++ u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); ++ u32 i = 0; ++ bool link_up = false; ++ bool negotiation; ++ ++ /* Mask off requested but non-supported speeds */ ++ status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation); ++ if (status != 0) ++ goto out; ++ ++ speed &= link_speed; ++ ++ /* Set autoneg_advertised value based on input link speed */ ++ hw->phy.autoneg_advertised = 0; ++ ++ if (speed & IXGBE_LINK_SPEED_10GB_FULL) ++ hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; ++ ++ if (speed & IXGBE_LINK_SPEED_1GB_FULL) ++ hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; ++ ++ /* ++ * When the driver changes the link speeds that it can support, ++ * it sets autotry_restart to true to indicate that we need to ++ * initiate a new autotry session with the link partner. To do ++ * so, we set the speed then disable and re-enable the tx laser, to ++ * alert the link partner that it also needs to restart autotry on its ++ * end. This is consistent with true clause 37 autoneg, which also ++ * involves a loss of signal. ++ */ ++ ++ /* ++ * Try each speed one by one, highest priority first. We do this in ++ * software because 10gb fiber doesn't support speed autonegotiation. ++ */ ++ if (speed & IXGBE_LINK_SPEED_10GB_FULL) { ++ speedcnt++; ++ highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; ++ ++ /* If we already have link at this speed, just jump out */ ++ status = ixgbe_check_link(hw, &link_speed, &link_up, false); ++ if (status != 0) ++ goto out; ++ ++ if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) ++ goto out; ++ ++ /* Set the module link speed */ ++ esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); ++ IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); ++ ++ /* Allow module to change analog characteristics (1G->10G) */ ++ msleep(40); ++ ++ status = ixgbe_setup_mac_link_speed_82599( ++ hw, IXGBE_LINK_SPEED_10GB_FULL, autoneg, ++ autoneg_wait_to_complete); ++ if (status != 0) ++ goto out; ++ ++ /* Flap the tx laser if it has not already been done */ ++ if (hw->mac.autotry_restart) { ++ /* Disable tx laser; allow 100us to go dark per spec */ ++ esdp_reg |= IXGBE_ESDP_SDP3; ++ IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); ++ udelay(100); ++ ++ /* Enable tx laser; allow 2ms to light up per spec */ ++ esdp_reg &= ~IXGBE_ESDP_SDP3; ++ IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); ++ msleep(2); ++ ++ hw->mac.autotry_restart = false; ++ } ++ ++ /* The controller may take up to 500ms at 10g to acquire link */ ++ for (i = 0; i < 5; i++) { ++ /* Wait for the link partner to also set speed */ ++ msleep(100); ++ ++ /* If we have link, just jump out */ ++ status = ixgbe_check_link(hw, &link_speed, ++ &link_up, false); ++ if (status != 0) ++ goto out; ++ ++ if (link_up) ++ goto out; ++ } ++ } ++ ++ if (speed & IXGBE_LINK_SPEED_1GB_FULL) { ++ speedcnt++; ++ if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) ++ highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; ++ ++ /* If we already have link at this speed, just jump out */ ++ status = ixgbe_check_link(hw, &link_speed, &link_up, false); ++ if (status != 0) ++ goto out; ++ ++ if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) ++ goto out; ++ ++ /* Set the module link speed */ ++ esdp_reg &= ~IXGBE_ESDP_SDP5; ++ esdp_reg |= IXGBE_ESDP_SDP5_DIR; ++ IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); ++ ++ /* Allow module to change analog characteristics (10G->1G) */ ++ msleep(40); ++ ++ status = ixgbe_setup_mac_link_speed_82599( ++ hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg, ++ autoneg_wait_to_complete); ++ if (status != 0) ++ goto out; ++ ++ /* Flap the tx laser if it has not already been done */ ++ if (hw->mac.autotry_restart) { ++ /* Disable tx laser; allow 100us to go dark per spec */ ++ esdp_reg |= IXGBE_ESDP_SDP3; ++ IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); ++ udelay(100); ++ ++ /* Enable tx laser; allow 2ms to light up per spec */ ++ esdp_reg &= ~IXGBE_ESDP_SDP3; ++ IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); ++ msleep(2); ++ ++ hw->mac.autotry_restart = false; ++ } ++ ++ /* Wait for the link partner to also set speed */ ++ msleep(100); ++ ++ /* If we have link, just jump out */ ++ status = ixgbe_check_link(hw, &link_speed, &link_up, false); ++ if (status != 0) ++ goto out; ++ ++ if (link_up) ++ goto out; ++ } ++ ++ /* ++ * We didn't get link. Configure back to the highest speed we tried, ++ * (if there was more than one). We call ourselves back with just the ++ * single highest speed that the user requested. ++ */ ++ if (speedcnt > 1) ++ status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, ++ highest_link_speed, autoneg, autoneg_wait_to_complete); ++ ++out: ++ return status; ++} ++ ++/** ++ * ixgbe_check_mac_link_82599 - Determine link and speed status ++ * @hw: pointer to hardware structure ++ * @speed: pointer to link speed ++ * @link_up: true when link is up ++ * @link_up_wait_to_complete: bool used to wait for link up or not ++ * ++ * Reads the links register to determine if link is up and the current speed ++ **/ ++s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed, ++ bool *link_up, bool link_up_wait_to_complete) ++{ ++ u32 links_reg; ++ u32 i; ++ ++ links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); ++ if (link_up_wait_to_complete) { ++ for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { ++ if (links_reg & IXGBE_LINKS_UP) { ++ *link_up = true; ++ break; ++ } else { ++ *link_up = false; ++ } ++ msleep(100); ++ links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); ++ } ++ } else { ++ if (links_reg & IXGBE_LINKS_UP) ++ *link_up = true; ++ else ++ *link_up = false; ++ } ++ ++ if ((links_reg & IXGBE_LINKS_SPEED_82599) == ++ IXGBE_LINKS_SPEED_10G_82599) ++ *speed = IXGBE_LINK_SPEED_10GB_FULL; ++ else if ((links_reg & IXGBE_LINKS_SPEED_82599) == ++ IXGBE_LINKS_SPEED_1G_82599) ++ *speed = IXGBE_LINK_SPEED_1GB_FULL; ++ else ++ *speed = IXGBE_LINK_SPEED_100_FULL; ++ ++ /* if link is down, zero out the current_mode */ ++ if (*link_up == false) { ++ hw->fc.current_mode = ixgbe_fc_none; ++ hw->fc.fc_was_autonegged = false; ++ } ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed ++ * @hw: pointer to hardware structure ++ * @speed: new link speed ++ * @autoneg: true if autonegotiation enabled ++ * @autoneg_wait_to_complete: true when waiting for completion is needed ++ * ++ * Set the link speed in the AUTOC register and restarts link. ++ **/ ++s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw, ++ ixgbe_link_speed speed, bool autoneg, ++ bool autoneg_wait_to_complete) ++{ ++ s32 status = 0; ++ u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); ++ u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); ++ u32 start_autoc = autoc; ++ u32 orig_autoc = 0; ++ u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; ++ u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; ++ u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; ++ u32 links_reg; ++ u32 i; ++ ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; ++ ++ /* Check to see if speed passed in is supported. */ ++ status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); ++ if (status != 0) ++ goto out; ++ ++ speed &= link_capabilities; ++ ++ if (speed == IXGBE_LINK_SPEED_UNKNOWN) { ++ status = IXGBE_ERR_LINK_SETUP; ++ goto out; ++ } ++ ++ /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ ++ if (hw->mac.orig_link_settings_stored) ++ orig_autoc = hw->mac.orig_autoc; ++ else ++ orig_autoc = autoc; ++ ++ if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || ++ link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || ++ link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { ++ /* Set KX4/KX/KR support according to speed requested */ ++ autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); ++ if (speed & IXGBE_LINK_SPEED_10GB_FULL) ++ if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) ++ autoc |= IXGBE_AUTOC_KX4_SUPP; ++ if (orig_autoc & IXGBE_AUTOC_KR_SUPP) ++ autoc |= IXGBE_AUTOC_KR_SUPP; ++ if (speed & IXGBE_LINK_SPEED_1GB_FULL) ++ autoc |= IXGBE_AUTOC_KX_SUPP; ++ } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && ++ (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || ++ link_mode == IXGBE_AUTOC_LMS_1G_AN)) { ++ /* Switch from 1G SFI to 10G SFI if requested */ ++ if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && ++ (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { ++ autoc &= ~IXGBE_AUTOC_LMS_MASK; ++ autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; ++ } ++ } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && ++ (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { ++ /* Switch from 10G SFI to 1G SFI if requested */ ++ if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && ++ (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { ++ autoc &= ~IXGBE_AUTOC_LMS_MASK; ++ if (autoneg) ++ autoc |= IXGBE_AUTOC_LMS_1G_AN; ++ else ++ autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; ++ } ++ } ++ ++ if (autoc != start_autoc) { ++ ++ /* Restart link */ ++ autoc |= IXGBE_AUTOC_AN_RESTART; ++ IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); ++ ++ /* Only poll for autoneg to complete if specified to do so */ ++ if (autoneg_wait_to_complete) { ++ if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || ++ link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || ++ link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { ++ links_reg = 0; /*Just in case Autoneg time=0*/ ++ for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { ++ links_reg = ++ IXGBE_READ_REG(hw, IXGBE_LINKS); ++ if (links_reg & IXGBE_LINKS_KX_AN_COMP) ++ break; ++ msleep(100); ++ } ++ if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { ++ status = ++ IXGBE_ERR_AUTONEG_NOT_COMPLETE; ++ hw_dbg(hw, "Autoneg did not complete.\n"); ++ } ++ } ++ } ++ ++ /* Add delay to filter out noises during initial link setup */ ++ msleep(50); ++ } ++ ++out: ++ return status; ++} ++ ++/** ++ * ixgbe_setup_copper_link_82599 - Setup copper link settings ++ * @hw: pointer to hardware structure ++ * ++ * Restarts the link on PHY and then MAC. Performs autonegotiation if needed. ++ **/ ++static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw) ++{ ++ s32 status; ++ ++ /* Restart autonegotiation on PHY */ ++ status = hw->phy.ops.setup_link(hw); ++ ++ /* Set up MAC */ ++ ixgbe_setup_mac_link_82599(hw); ++ ++ return status; ++} ++ ++/** ++ * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field ++ * @hw: pointer to hardware structure ++ * @speed: new link speed ++ * @autoneg: true if autonegotiation enabled ++ * @autoneg_wait_to_complete: true if waiting is needed to complete ++ * ++ * Restarts link on PHY and MAC based on settings passed in. ++ **/ ++static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw, ++ ixgbe_link_speed speed, ++ bool autoneg, ++ bool autoneg_wait_to_complete) ++{ ++ s32 status; ++ ++ /* Setup the PHY according to input speed */ ++ status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, ++ autoneg_wait_to_complete); ++ /* Set up MAC */ ++ ixgbe_setup_mac_link_82599(hw); ++ ++ return status; ++} ++/** ++ * ixgbe_reset_hw_82599 - Perform hardware reset ++ * @hw: pointer to hardware structure ++ * ++ * Resets the hardware by resetting the transmit and receive units, masks ++ * and clears all interrupts, perform a PHY reset, and perform a link (MAC) ++ * reset. ++ **/ ++s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) ++{ ++ s32 status = 0; ++ u32 ctrl, ctrl_ext; ++ u32 i; ++ u32 autoc; ++ u32 autoc2; ++ ++ /* Call adapter stop to disable tx/rx and clear interrupts */ ++ hw->mac.ops.stop_adapter(hw); ++ ++ /* PHY ops must be identified and initialized prior to reset */ ++ ++ /* Identify PHY and related function pointers */ ++ status = hw->phy.ops.init(hw); ++ ++ if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) ++ goto reset_hw_out; ++ ++ /* Setup SFP module if there is one present. */ ++ if (hw->phy.sfp_setup_needed) { ++ status = hw->mac.ops.setup_sfp(hw); ++ hw->phy.sfp_setup_needed = false; ++ } ++ ++ if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) ++ goto reset_hw_out; ++ ++ /* Reset PHY */ ++ if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) ++ hw->phy.ops.reset(hw); ++ ++ /* ++ * Prevent the PCI-E bus from from hanging by disabling PCI-E master ++ * access and verify no pending requests before reset ++ */ ++ status = ixgbe_disable_pcie_master(hw); ++ if (status != 0) { ++ status = IXGBE_ERR_MASTER_REQUESTS_PENDING; ++ hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); ++ } ++ ++ /* ++ * Issue global reset to the MAC. This needs to be a SW reset. ++ * If link reset is used, it might reset the MAC when mng is using it ++ */ ++ ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); ++ IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); ++ IXGBE_WRITE_FLUSH(hw); ++ ++ /* Poll for reset bit to self-clear indicating reset is complete */ ++ for (i = 0; i < 10; i++) { ++ udelay(1); ++ ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); ++ if (!(ctrl & IXGBE_CTRL_RST)) ++ break; ++ } ++ if (ctrl & IXGBE_CTRL_RST) { ++ status = IXGBE_ERR_RESET_FAILED; ++ hw_dbg(hw, "Reset polling failed to complete.\n"); ++ } ++ /* Clear PF Reset Done bit so PF/VF Mail Ops can work */ ++ ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); ++ ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; ++ IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); ++ ++ msleep(50); ++ ++ ++ ++ /* ++ * Store the original AUTOC/AUTOC2 values if they have not been ++ * stored off yet. Otherwise restore the stored original ++ * values since the reset operation sets back to defaults. ++ */ ++ autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); ++ autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); ++ if (hw->mac.orig_link_settings_stored == false) { ++ hw->mac.orig_autoc = autoc; ++ hw->mac.orig_autoc2 = autoc2; ++ hw->mac.orig_link_settings_stored = true; ++ } else { ++ if (autoc != hw->mac.orig_autoc) ++ IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | ++ IXGBE_AUTOC_AN_RESTART)); ++ ++ if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != ++ (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { ++ autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; ++ autoc2 |= (hw->mac.orig_autoc2 & ++ IXGBE_AUTOC2_UPPER_MASK); ++ IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); ++ } ++ } ++ ++ /* Store the permanent mac address */ ++ hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); ++ ++ /* ++ * Store MAC address from RAR0, clear receive address registers, and ++ * clear the multicast table. Also reset num_rar_entries to 128, ++ * since we modify this value when programming the SAN MAC address. ++ */ ++ hw->mac.num_rar_entries = 128; ++ hw->mac.ops.init_rx_addrs(hw); ++ ++ ++ ++ /* Store the permanent SAN mac address */ ++ hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); ++ ++ /* Add the SAN MAC address to the RAR only if it's a valid address */ ++ if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { ++ hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, ++ hw->mac.san_addr, 0, IXGBE_RAH_AV); ++ ++ /* Reserve the last RAR for the SAN MAC address */ ++ hw->mac.num_rar_entries--; ++ } ++ ++reset_hw_out: ++ return status; ++} ++ ++/** ++ * ixgbe_insert_mac_addr_82599 - Find a RAR for this mac address ++ * @hw: pointer to hardware structure ++ * @addr: Address to put into receive address register ++ * @vmdq: VMDq pool to assign ++ * ++ * Puts an ethernet address into a receive address register, or ++ * finds the rar that it is aleady in; adds to the pool list ++ **/ ++s32 ixgbe_insert_mac_addr_82599(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) ++{ ++ static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; ++ u32 first_empty_rar = NO_EMPTY_RAR_FOUND; ++ u32 rar; ++ u32 rar_low, rar_high; ++ u32 addr_low, addr_high; ++ ++ /* swap bytes for HW little endian */ ++ addr_low = addr[0] | (addr[1] << 8) ++ | (addr[2] << 16) ++ | (addr[3] << 24); ++ addr_high = addr[4] | (addr[5] << 8); ++ ++ /* ++ * Either find the mac_id in rar or find the first empty space. ++ * rar_highwater points to just after the highest currently used ++ * rar in order to shorten the search. It grows when we add a new ++ * rar to the top. ++ */ ++ for (rar = 0; rar < hw->mac.rar_highwater; rar++) { ++ rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); ++ ++ if (((IXGBE_RAH_AV & rar_high) == 0) ++ && first_empty_rar == NO_EMPTY_RAR_FOUND) { ++ first_empty_rar = rar; ++ } else if ((rar_high & 0xFFFF) == addr_high) { ++ rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); ++ if (rar_low == addr_low) ++ break; /* found it already in the rars */ ++ } ++ } ++ ++ if (rar < hw->mac.rar_highwater) { ++ /* already there so just add to the pool bits */ ++ ixgbe_set_vmdq(hw, rar, vmdq); ++ } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { ++ /* stick it into first empty RAR slot we found */ ++ rar = first_empty_rar; ++ ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); ++ } else if (rar == hw->mac.rar_highwater) { ++ /* add it to the top of the list and inc the highwater mark */ ++ ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); ++ hw->mac.rar_highwater++; ++ } else if (rar >= hw->mac.num_rar_entries) { ++ return IXGBE_ERR_INVALID_MAC_ADDR; ++ } ++ ++ /* ++ * If we found rar[0], make sure the default pool bit (we use pool 0) ++ * remains cleared to be sure default pool packets will get delivered ++ */ ++ if (rar == 0) ++ ixgbe_clear_vmdq(hw, rar, 0); ++ ++ return rar; ++} ++ ++/** ++ * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address ++ * @hw: pointer to hardware struct ++ * @rar: receive address register index to disassociate ++ * @vmdq: VMDq pool index to remove from the rar ++ **/ ++s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq) ++{ ++ u32 mpsar_lo, mpsar_hi; ++ u32 rar_entries = hw->mac.num_rar_entries; ++ ++ if (rar < rar_entries) { ++ mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); ++ mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); ++ ++ if (!mpsar_lo && !mpsar_hi) ++ goto done; ++ ++ if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { ++ if (mpsar_lo) { ++ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); ++ mpsar_lo = 0; ++ } ++ if (mpsar_hi) { ++ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); ++ mpsar_hi = 0; ++ } ++ } else if (vmdq < 32) { ++ mpsar_lo &= ~(1 << vmdq); ++ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); ++ } else { ++ mpsar_hi &= ~(1 << (vmdq - 32)); ++ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); ++ } ++ ++ /* was that the last pool using this rar? */ ++ if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) ++ hw->mac.ops.clear_rar(hw, rar); ++ } else { ++ hw_dbg(hw, "RAR index %d is out of range.\n", rar); ++ } ++ ++done: ++ return 0; ++} ++ ++/** ++ * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address ++ * @hw: pointer to hardware struct ++ * @rar: receive address register index to associate with a VMDq index ++ * @vmdq: VMDq pool index ++ **/ ++s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq) ++{ ++ u32 mpsar; ++ u32 rar_entries = hw->mac.num_rar_entries; ++ ++ if (rar < rar_entries) { ++ if (vmdq < 32) { ++ mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); ++ mpsar |= 1 << vmdq; ++ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); ++ } else { ++ mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); ++ mpsar |= 1 << (vmdq - 32); ++ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); ++ } ++ } else { ++ hw_dbg(hw, "RAR index %d is out of range.\n", rar); ++ } ++ return 0; ++} ++ ++/** ++ * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot ++ * @hw: pointer to hardware structure ++ * @vlan: VLAN id to write to VLAN filter ++ * ++ * return the VLVF index where this VLAN id should be placed ++ * ++ **/ ++inline s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) ++{ ++ u32 bits = 0; ++ u32 first_empty_slot = 0; ++ s32 regindex; ++ ++ /* ++ * Search for the vlan id in the VLVF entries. Save off the first empty ++ * slot found along the way ++ */ ++ for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { ++ bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); ++ if (!bits && !(first_empty_slot)) ++ first_empty_slot = regindex; ++ else if ((bits & 0x0FFF) == vlan) ++ break; ++ } ++ ++ /* ++ * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan ++ * in the VLVF. Else use the first empty VLVF register for this ++ * vlan id. ++ */ ++ if (regindex >= IXGBE_VLVF_ENTRIES) { ++ if (first_empty_slot) ++ regindex = first_empty_slot; ++ else { ++ hw_dbg(hw, "No space in VLVF.\n"); ++ regindex = -1; ++ } ++ } ++ ++ return regindex; ++} ++ ++/** ++ * ixgbe_set_vfta_82599 - Set VLAN filter table ++ * @hw: pointer to hardware structure ++ * @vlan: VLAN id to write to VLAN filter ++ * @vind: VMDq output index that maps queue to VLAN id in VFVFB ++ * @vlan_on: boolean flag to turn on/off VLAN in VFVF ++ * ++ * Turn on/off specified VLAN in the VLAN filter table. ++ **/ ++s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind, ++ bool vlan_on) ++{ ++ s32 regindex; ++ u32 bitindex; ++ u32 bits; ++ u32 vt; ++ ++ if (vlan > 4095) ++ return IXGBE_ERR_PARAM; ++ ++ /* ++ * this is a 2 part operation - first the VFTA, then the ++ * VLVF and VLVFB if VT Mode is set ++ */ ++ ++ /* Part 1 ++ * The VFTA is a bitstring made up of 128 32-bit registers ++ * that enable the particular VLAN id, much like the MTA: ++ * bits[11-5]: which register ++ * bits[4-0]: which bit in the register ++ */ ++ regindex = (vlan >> 5) & 0x7F; ++ bitindex = vlan & 0x1F; ++ bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); ++ if (vlan_on) ++ bits |= (1 << bitindex); ++ else ++ bits &= ~(1 << bitindex); ++ IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); ++ ++ ++ /* Part 2 ++ * If VT Mode is set ++ * Either vlan_on ++ * make sure the vlan is in VLVF ++ * set the vind bit in the matching VLVFB ++ * Or !vlan_on ++ * clear the pool bit and possibly the vind ++ */ ++ vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); ++ if (vt & IXGBE_VT_CTL_VT_ENABLE) { ++ if (vlan == 0) { ++ regindex = 0; ++ } else { ++ regindex = ixgbe_find_vlvf_slot(hw, vlan); ++ if (regindex < 0) ++ goto out; ++ } ++ ++ if (vlan_on) { ++ /* set the pool bit */ ++ if (vind < 32) { ++ bits = IXGBE_READ_REG(hw, ++ IXGBE_VLVFB(regindex*2)); ++ bits |= (1 << vind); ++ IXGBE_WRITE_REG(hw, ++ IXGBE_VLVFB(regindex*2), ++ bits); ++ } else { ++ bits = IXGBE_READ_REG(hw, ++ IXGBE_VLVFB((regindex*2)+1)); ++ bits |= (1 << vind); ++ IXGBE_WRITE_REG(hw, ++ IXGBE_VLVFB((regindex*2)+1), ++ bits); ++ } ++ } else { ++ /* clear the pool bit */ ++ if (vind < 32) { ++ bits = IXGBE_READ_REG(hw, ++ IXGBE_VLVFB(regindex*2)); ++ bits &= ~(1 << vind); ++ IXGBE_WRITE_REG(hw, ++ IXGBE_VLVFB(regindex*2), ++ bits); ++ bits |= IXGBE_READ_REG(hw, ++ IXGBE_VLVFB((regindex*2)+1)); ++ } else { ++ bits = IXGBE_READ_REG(hw, ++ IXGBE_VLVFB((regindex*2)+1)); ++ bits &= ~(1 << vind); ++ IXGBE_WRITE_REG(hw, ++ IXGBE_VLVFB((regindex*2)+1), ++ bits); ++ bits |= IXGBE_READ_REG(hw, ++ IXGBE_VLVFB(regindex*2)); ++ } ++ } ++ ++ if (bits) ++ IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), ++ (IXGBE_VLVF_VIEN | vlan)); ++ else ++ IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0); ++ } ++out: ++ return 0; ++} ++ ++/** ++ * ixgbe_clear_vfta_82599 - Clear VLAN filter table ++ * @hw: pointer to hardware structure ++ * ++ * Clears the VLAN filer table, and the VMDq index associated with the filter ++ **/ ++s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw) ++{ ++ u32 offset; ++ ++ for (offset = 0; offset < hw->mac.vft_size; offset++) ++ IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); ++ ++ for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { ++ IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); ++ IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0); ++ IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0); ++ } ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array ++ * @hw: pointer to hardware structure ++ **/ ++s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw) ++{ ++ int i; ++ ++ hw_dbg(hw, " Clearing UTA\n"); ++ ++ for (i = 0; i < 128; i++) ++ IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. ++ * @hw: pointer to hardware structure ++ **/ ++s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) ++{ ++ int i; ++ u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); ++ fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; ++ ++ /* ++ * Before starting reinitialization process, ++ * FDIRCMD.CMD must be zero. ++ */ ++ for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { ++ if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & ++ IXGBE_FDIRCMD_CMD_MASK)) ++ break; ++ udelay(10); ++ } ++ if (i >= IXGBE_FDIRCMD_CMD_POLL) { ++ hw_dbg(hw, "Flow Director previous command isn't complete, " ++ "aborting table re-initialization. \n"); ++ return IXGBE_ERR_FDIR_REINIT_FAILED; ++ } ++ ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); ++ IXGBE_WRITE_FLUSH(hw); ++ /* ++ * 82599 adapters flow director init flow cannot be restarted, ++ * Workaround 82599 silicon errata by performing the following steps ++ * before re-writing the FDIRCTRL control register with the same value. ++ * - write 1 to bit 8 of FDIRCMD register & ++ * - write 0 to bit 8 of FDIRCMD register ++ */ ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, ++ (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | ++ IXGBE_FDIRCMD_CLEARHT)); ++ IXGBE_WRITE_FLUSH(hw); ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, ++ (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & ++ ~IXGBE_FDIRCMD_CLEARHT)); ++ IXGBE_WRITE_FLUSH(hw); ++ /* ++ * Clear FDIR Hash register to clear any leftover hashes ++ * waiting to be programmed. ++ */ ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); ++ IXGBE_WRITE_FLUSH(hw); ++ ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); ++ IXGBE_WRITE_FLUSH(hw); ++ ++ /* Poll init-done after we write FDIRCTRL register */ ++ for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { ++ if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & ++ IXGBE_FDIRCTRL_INIT_DONE) ++ break; ++ udelay(10); ++ } ++ if (i >= IXGBE_FDIR_INIT_DONE_POLL) { ++ hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); ++ return IXGBE_ERR_FDIR_REINIT_FAILED; ++ } ++ ++ /* Clear FDIR statistics registers (read to clear) */ ++ IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); ++ IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); ++ IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); ++ IXGBE_READ_REG(hw, IXGBE_FDIRMISS); ++ IXGBE_READ_REG(hw, IXGBE_FDIRLEN); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters ++ * @hw: pointer to hardware structure ++ * @pballoc: which mode to allocate filters with ++ **/ ++s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc) ++{ ++ u32 fdirctrl = 0; ++ u32 pbsize; ++ int i; ++ ++ /* ++ * Before enabling Flow Director, the Rx Packet Buffer size ++ * must be reduced. The new value is the current size minus ++ * flow director memory usage size. ++ */ ++ pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); ++ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), ++ (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); ++ ++ /* ++ * The defaults in the HW for RX PB 1-7 are not zero and so should be ++ * intialized to zero for non DCB mode otherwise actual total RX PB ++ * would be bigger than programmed and filter space would run into ++ * the PB 0 region. ++ */ ++ for (i = 1; i < 8; i++) ++ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); ++ ++ /* Send interrupt when 64 filters are left */ ++ fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; ++ ++ /* Set the maximum length per hash bucket to 0xA filters */ ++ fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT; ++ ++ switch (pballoc) { ++ case IXGBE_FDIR_PBALLOC_64K: ++ /* 8k - 1 signature filters */ ++ fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; ++ break; ++ case IXGBE_FDIR_PBALLOC_128K: ++ /* 16k - 1 signature filters */ ++ fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; ++ break; ++ case IXGBE_FDIR_PBALLOC_256K: ++ /* 32k - 1 signature filters */ ++ fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; ++ break; ++ default: ++ /* bad value */ ++ return IXGBE_ERR_CONFIG; ++ }; ++ ++ /* Move the flexible bytes to use the ethertype - shift 6 words */ ++ fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); ++ ++ ++ /* Prime the keys for hashing */ ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, ++ IXGBE_HTONL(IXGBE_ATR_BUCKET_HASH_KEY)); ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, ++ IXGBE_HTONL(IXGBE_ATR_SIGNATURE_HASH_KEY)); ++ ++ /* ++ * Poll init-done after we write the register. Estimated times: ++ * 10G: PBALLOC = 11b, timing is 60us ++ * 1G: PBALLOC = 11b, timing is 600us ++ * 100M: PBALLOC = 11b, timing is 6ms ++ * ++ * Multiple these timings by 4 if under full Rx load ++ * ++ * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for ++ * 1 msec per poll time. If we're at line rate and drop to 100M, then ++ * this might not finish in our poll time, but we can live with that ++ * for now. ++ */ ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); ++ IXGBE_WRITE_FLUSH(hw); ++ for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { ++ if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & ++ IXGBE_FDIRCTRL_INIT_DONE) ++ break; ++ msleep(1); ++ } ++ if (i >= IXGBE_FDIR_INIT_DONE_POLL) ++ hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters ++ * @hw: pointer to hardware structure ++ * @pballoc: which mode to allocate filters with ++ **/ ++s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc) ++{ ++ u32 fdirctrl = 0; ++ u32 pbsize; ++ int i; ++ ++ /* ++ * Before enabling Flow Director, the Rx Packet Buffer size ++ * must be reduced. The new value is the current size minus ++ * flow director memory usage size. ++ */ ++ ++ pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); ++ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), ++ (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); ++ ++ /* ++ * The defaults in the HW for RX PB 1-7 are not zero and so should be ++ * intialized to zero for non DCB mode otherwise actual total RX PB ++ * would be bigger than programmed and filter space would run into ++ * the PB 0 region. ++ */ ++ for (i = 1; i < 8; i++) ++ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); ++ ++ /* Send interrupt when 64 filters are left */ ++ fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; ++ ++ switch (pballoc) { ++ case IXGBE_FDIR_PBALLOC_64K: ++ /* 2k - 1 perfect filters */ ++ fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; ++ break; ++ case IXGBE_FDIR_PBALLOC_128K: ++ /* 4k - 1 perfect filters */ ++ fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; ++ break; ++ case IXGBE_FDIR_PBALLOC_256K: ++ /* 8k - 1 perfect filters */ ++ fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; ++ break; ++ default: ++ /* bad value */ ++ return IXGBE_ERR_CONFIG; ++ }; ++ ++ /* Turn perfect match filtering on */ ++ fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH; ++ fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; ++ ++ /* Move the flexible bytes to use the ethertype - shift 6 words */ ++ fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); ++ ++ /* Prime the keys for hashing */ ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, ++ IXGBE_HTONL(IXGBE_ATR_BUCKET_HASH_KEY)); ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, ++ IXGBE_HTONL(IXGBE_ATR_SIGNATURE_HASH_KEY)); ++ ++ /* ++ * Poll init-done after we write the register. Estimated times: ++ * 10G: PBALLOC = 11b, timing is 60us ++ * 1G: PBALLOC = 11b, timing is 600us ++ * 100M: PBALLOC = 11b, timing is 6ms ++ * ++ * Multiple these timings by 4 if under full Rx load ++ * ++ * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for ++ * 1 msec per poll time. If we're at line rate and drop to 100M, then ++ * this might not finish in our poll time, but we can live with that ++ * for now. ++ */ ++ ++ /* Set the maximum length per hash bucket to 0xA filters */ ++ fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT); ++ ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); ++ IXGBE_WRITE_FLUSH(hw); ++ for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { ++ if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & ++ IXGBE_FDIRCTRL_INIT_DONE) ++ break; ++ msleep(1); ++ } ++ if (i >= IXGBE_FDIR_INIT_DONE_POLL) ++ hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n"); ++ ++ return 0; ++} ++ ++ ++/** ++ * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR ++ * @stream: input bitstream to compute the hash on ++ * @key: 32-bit hash key ++ **/ ++u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, u32 key) ++{ ++ /* ++ * The algorithm is as follows: ++ * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350 ++ * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n] ++ * and A[n] x B[n] is bitwise AND between same length strings ++ * ++ * K[n] is 16 bits, defined as: ++ * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15] ++ * for n modulo 32 < 15, K[n] = ++ * K[(n % 32:0) | (31:31 - (14 - (n % 32)))] ++ * ++ * S[n] is 16 bits, defined as: ++ * for n >= 15, S[n] = S[n:n - 15] ++ * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))] ++ * ++ * To simplify for programming, the algorithm is implemented ++ * in software this way: ++ * ++ * Key[31:0], Stream[335:0] ++ * ++ * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times ++ * int_key[350:0] = tmp_key[351:1] ++ * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321] ++ * ++ * hash[15:0] = 0; ++ * for (i = 0; i < 351; i++) { ++ * if (int_key[i]) ++ * hash ^= int_stream[(i + 15):i]; ++ * } ++ */ ++ ++ union { ++ u64 fill[6]; ++ u32 key[11]; ++ u8 key_stream[44]; ++ } tmp_key; ++ ++ u8 *stream = (u8 *)atr_input; ++ u8 int_key[44]; /* upper-most bit unused */ ++ u8 hash_str[46]; /* upper-most 2 bits unused */ ++ u16 hash_result = 0; ++ int i, j, k, h; ++ ++ /* ++ * Initialize the fill member to prevent warnings ++ * on some compilers ++ */ ++ tmp_key.fill[0] = 0; ++ ++ /* First load the temporary key stream */ ++ for (i = 0; i < 6; i++) { ++ u64 fillkey = ((u64)key << 32) | key; ++ tmp_key.fill[i] = fillkey; ++ } ++ ++ /* ++ * Set the interim key for the hashing. Bit 352 is unused, so we must ++ * shift and compensate when building the key. ++ */ ++ ++ int_key[0] = tmp_key.key_stream[0] >> 1; ++ for (i = 1, j = 0; i < 44; i++) { ++ unsigned int this_key = tmp_key.key_stream[j] << 7; ++ j++; ++ int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1)); ++ } ++ ++ /* ++ * Set the interim bit string for the hashing. Bits 368 and 367 are ++ * unused, so shift and compensate when building the string. ++ */ ++ hash_str[0] = (stream[40] & 0x7f) >> 1; ++ for (i = 1, j = 40; i < 46; i++) { ++ unsigned int this_str = stream[j] << 7; ++ j++; ++ if (j > 41) ++ j = 0; ++ hash_str[i] = (u8)(this_str | (stream[j] >> 1)); ++ } ++ ++ /* ++ * Now compute the hash. i is the index into hash_str, j is into our ++ * key stream, k is counting the number of bits, and h interates within ++ * each byte. ++ */ ++ for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) { ++ for (h = 0; h < 8 && k < 351; h++, k++) { ++ if (int_key[j] & (1 << h)) { ++ /* ++ * Key bit is set, XOR in the current 16-bit ++ * string. Example of processing: ++ * h = 0, ++ * tmp = (hash_str[i - 2] & 0 << 16) | ++ * (hash_str[i - 1] & 0xff << 8) | ++ * (hash_str[i] & 0xff >> 0) ++ * So tmp = hash_str[15 + k:k], since the ++ * i + 2 clause rolls off the 16-bit value ++ * h = 7, ++ * tmp = (hash_str[i - 2] & 0x7f << 9) | ++ * (hash_str[i - 1] & 0xff << 1) | ++ * (hash_str[i] & 0x80 >> 7) ++ */ ++ int tmp = (hash_str[i] >> h); ++ tmp |= (hash_str[i - 1] << (8 - h)); ++ tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1)) ++ << (16 - h); ++ hash_result ^= (u16)tmp; ++ } ++ } ++ } ++ ++ return hash_result; ++} ++ ++/** ++ * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream ++ * @input: input stream to modify ++ * @vlan: the VLAN id to load ++ **/ ++s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan) ++{ ++ input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8; ++ input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address ++ * @input: input stream to modify ++ * @src_addr: the IP address to load ++ **/ ++s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr) ++{ ++ input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24; ++ input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] = ++ (src_addr >> 16) & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] = ++ (src_addr >> 8) & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address ++ * @input: input stream to modify ++ * @dst_addr: the IP address to load ++ **/ ++s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr) ++{ ++ input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24; ++ input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] = ++ (dst_addr >> 16) & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] = ++ (dst_addr >> 8) & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address ++ * @input: input stream to modify ++ * @src_addr_1: the first 4 bytes of the IP address to load ++ * @src_addr_2: the second 4 bytes of the IP address to load ++ * @src_addr_3: the third 4 bytes of the IP address to load ++ * @src_addr_4: the fourth 4 bytes of the IP address to load ++ **/ ++s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input, ++ u32 src_addr_1, u32 src_addr_2, ++ u32 src_addr_3, u32 src_addr_4) ++{ ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] = ++ (src_addr_4 >> 8) & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] = ++ (src_addr_4 >> 16) & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24; ++ ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] = ++ (src_addr_3 >> 8) & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] = ++ (src_addr_3 >> 16) & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24; ++ ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] = ++ (src_addr_2 >> 8) & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] = ++ (src_addr_2 >> 16) & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24; ++ ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] = ++ (src_addr_1 >> 8) & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] = ++ (src_addr_1 >> 16) & 0xff; ++ input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address ++ * @input: input stream to modify ++ * @dst_addr_1: the first 4 bytes of the IP address to load ++ * @dst_addr_2: the second 4 bytes of the IP address to load ++ * @dst_addr_3: the third 4 bytes of the IP address to load ++ * @dst_addr_4: the fourth 4 bytes of the IP address to load ++ **/ ++s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input, ++ u32 dst_addr_1, u32 dst_addr_2, ++ u32 dst_addr_3, u32 dst_addr_4) ++{ ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] = ++ (dst_addr_4 >> 8) & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] = ++ (dst_addr_4 >> 16) & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24; ++ ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] = ++ (dst_addr_3 >> 8) & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] = ++ (dst_addr_3 >> 16) & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24; ++ ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] = ++ (dst_addr_2 >> 8) & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] = ++ (dst_addr_2 >> 16) & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24; ++ ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] = ++ (dst_addr_1 >> 8) & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] = ++ (dst_addr_1 >> 16) & 0xff; ++ input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_set_src_port_82599 - Sets the source port ++ * @input: input stream to modify ++ * @src_port: the source port to load ++ **/ ++s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port) ++{ ++ input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8; ++ input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_set_dst_port_82599 - Sets the destination port ++ * @input: input stream to modify ++ * @dst_port: the destination port to load ++ **/ ++s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port) ++{ ++ input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8; ++ input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes ++ * @input: input stream to modify ++ * @flex_bytes: the flexible bytes to load ++ **/ ++s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte) ++{ ++ input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8; ++ input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool ++ * @input: input stream to modify ++ * @vm_pool: the Virtual Machine pool to load ++ **/ ++s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input, u8 vm_pool) ++{ ++ input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type ++ * @input: input stream to modify ++ * @l4type: the layer 4 type value to load ++ **/ ++s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type) ++{ ++ input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream ++ * @input: input stream to search ++ * @vlan: the VLAN id to load ++ **/ ++s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan) ++{ ++ *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET]; ++ *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address ++ * @input: input stream to search ++ * @src_addr: the IP address to load ++ **/ ++s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input, u32 *src_addr) ++{ ++ *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET]; ++ *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8; ++ *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16; ++ *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address ++ * @input: input stream to search ++ * @dst_addr: the IP address to load ++ **/ ++s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 *dst_addr) ++{ ++ *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET]; ++ *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8; ++ *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16; ++ *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address ++ * @input: input stream to search ++ * @src_addr_1: the first 4 bytes of the IP address to load ++ * @src_addr_2: the second 4 bytes of the IP address to load ++ * @src_addr_3: the third 4 bytes of the IP address to load ++ * @src_addr_4: the fourth 4 bytes of the IP address to load ++ **/ ++s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input, ++ u32 *src_addr_1, u32 *src_addr_2, ++ u32 *src_addr_3, u32 *src_addr_4) ++{ ++ *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12]; ++ *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8; ++ *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16; ++ *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24; ++ ++ *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8]; ++ *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8; ++ *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16; ++ *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24; ++ ++ *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4]; ++ *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8; ++ *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16; ++ *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24; ++ ++ *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET]; ++ *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8; ++ *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16; ++ *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address ++ * @input: input stream to search ++ * @dst_addr_1: the first 4 bytes of the IP address to load ++ * @dst_addr_2: the second 4 bytes of the IP address to load ++ * @dst_addr_3: the third 4 bytes of the IP address to load ++ * @dst_addr_4: the fourth 4 bytes of the IP address to load ++ **/ ++s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input, ++ u32 *dst_addr_1, u32 *dst_addr_2, ++ u32 *dst_addr_3, u32 *dst_addr_4) ++{ ++ *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12]; ++ *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8; ++ *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16; ++ *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24; ++ ++ *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8]; ++ *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8; ++ *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16; ++ *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24; ++ ++ *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4]; ++ *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8; ++ *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16; ++ *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24; ++ ++ *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET]; ++ *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8; ++ *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16; ++ *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_get_src_port_82599 - Gets the source port ++ * @input: input stream to modify ++ * @src_port: the source port to load ++ * ++ * Even though the input is given in big-endian, the FDIRPORT registers ++ * expect the ports to be programmed in little-endian. Hence the need to swap ++ * endianness when retrieving the data. This can be confusing since the ++ * internal hash engine expects it to be big-endian. ++ **/ ++s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input, u16 *src_port) ++{ ++ *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8; ++ *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1]; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_get_dst_port_82599 - Gets the destination port ++ * @input: input stream to modify ++ * @dst_port: the destination port to load ++ * ++ * Even though the input is given in big-endian, the FDIRPORT registers ++ * expect the ports to be programmed in little-endian. Hence the need to swap ++ * endianness when retrieving the data. This can be confusing since the ++ * internal hash engine expects it to be big-endian. ++ **/ ++s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input, u16 *dst_port) ++{ ++ *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8; ++ *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1]; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes ++ * @input: input stream to modify ++ * @flex_bytes: the flexible bytes to load ++ **/ ++s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input, u16 *flex_byte) ++{ ++ *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET]; ++ *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool ++ * @input: input stream to modify ++ * @vm_pool: the Virtual Machine pool to load ++ **/ ++s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input, u8 *vm_pool) ++{ ++ *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET]; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type ++ * @input: input stream to modify ++ * @l4type: the layer 4 type value to load ++ **/ ++s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input, u8 *l4type) ++{ ++ *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET]; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter ++ * @hw: pointer to hardware structure ++ * @stream: input bitstream ++ * @queue: queue index to direct traffic to ++ **/ ++s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, ++ struct ixgbe_atr_input *input, ++ u8 queue) ++{ ++ u64 fdirhashcmd; ++ u64 fdircmd; ++ u32 fdirhash; ++ u16 bucket_hash, sig_hash; ++ u8 l4type; ++ ++ bucket_hash = ixgbe_atr_compute_hash_82599(input, ++ IXGBE_ATR_BUCKET_HASH_KEY); ++ ++ /* bucket_hash is only 15 bits */ ++ bucket_hash &= IXGBE_ATR_HASH_MASK; ++ ++ sig_hash = ixgbe_atr_compute_hash_82599(input, ++ IXGBE_ATR_SIGNATURE_HASH_KEY); ++ ++ /* Get the l4type in order to program FDIRCMD properly */ ++ /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */ ++ ixgbe_atr_get_l4type_82599(input, &l4type); ++ ++ /* ++ * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits ++ * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. ++ */ ++ fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash; ++ ++ fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | ++ IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN); ++ ++ switch (l4type & IXGBE_ATR_L4TYPE_MASK) { ++ case IXGBE_ATR_L4TYPE_TCP: ++ fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP; ++ break; ++ case IXGBE_ATR_L4TYPE_UDP: ++ fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP; ++ break; ++ case IXGBE_ATR_L4TYPE_SCTP: ++ fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP; ++ break; ++ default: ++ hw_dbg(hw, " Error on l4type input\n"); ++ return IXGBE_ERR_CONFIG; ++ } ++ ++ if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) ++ fdircmd |= IXGBE_FDIRCMD_IPV6; ++ ++ fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT); ++ fdirhashcmd = ((fdircmd << 32) | fdirhash); ++ ++ hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, fdirhash & 0x7FFF7FFF); ++ IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter ++ * @hw: pointer to hardware structure ++ * @input: input bitstream ++ * @queue: queue index to direct traffic to ++ * ++ * Note that the caller to this function must lock before calling, since the ++ * hardware writes must be protected from one another. ++ **/ ++s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, ++ struct ixgbe_atr_input *input, ++ u16 soft_id, ++ u8 queue) ++{ ++ u32 fdircmd = 0; ++ u32 fdirhash; ++ u32 src_ipv4, dst_ipv4; ++ u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4; ++ u16 src_port, dst_port, vlan_id, flex_bytes; ++ u16 bucket_hash; ++ u8 l4type; ++ ++ /* Get our input values */ ++ ixgbe_atr_get_l4type_82599(input, &l4type); ++ ++ /* ++ * Check l4type formatting, and bail out before we touch the hardware ++ * if there's a configuration issue ++ */ ++ switch (l4type & IXGBE_ATR_L4TYPE_MASK) { ++ case IXGBE_ATR_L4TYPE_TCP: ++ fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP; ++ break; ++ case IXGBE_ATR_L4TYPE_UDP: ++ fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP; ++ break; ++ case IXGBE_ATR_L4TYPE_SCTP: ++ fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP; ++ break; ++ default: ++ hw_dbg(hw, " Error on l4type input\n"); ++ return IXGBE_ERR_CONFIG; ++ } ++ ++ bucket_hash = ixgbe_atr_compute_hash_82599(input, ++ IXGBE_ATR_BUCKET_HASH_KEY); ++ ++ /* bucket_hash is only 15 bits */ ++ bucket_hash &= IXGBE_ATR_HASH_MASK; ++ ++ ixgbe_atr_get_vlan_id_82599(input, &vlan_id); ++ ixgbe_atr_get_src_port_82599(input, &src_port); ++ ixgbe_atr_get_dst_port_82599(input, &dst_port); ++ ixgbe_atr_get_flex_byte_82599(input, &flex_bytes); ++ ++ fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash; ++ ++ /* Now figure out if we're IPv4 or IPv6 */ ++ if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) { ++ /* IPv6 */ ++ ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2, ++ &src_ipv6_3, &src_ipv6_4); ++ ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1); ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2); ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3); ++ /* The last 4 bytes is the same register as IPv4 */ ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4); ++ ++ fdircmd |= IXGBE_FDIRCMD_IPV6; ++ fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH; ++ } else { ++ /* IPv4 */ ++ ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4); ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4); ++ ++ } ++ ++ ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4); ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4); ++ ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id | ++ (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT))); ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port | ++ (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT))); ++ ++ fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW; ++ fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE; ++ fdircmd |= IXGBE_FDIRCMD_LAST; ++ fdircmd |= IXGBE_FDIRCMD_QUEUE_EN; ++ fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; ++ ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); ++ IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register ++ * @hw: pointer to hardware structure ++ * @reg: analog register to read ++ * @val: read value ++ * ++ * Performs read operation to Omer analog register specified. ++ **/ ++s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) ++{ ++ u32 core_ctl; ++ ++ IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | ++ (reg << 8)); ++ IXGBE_WRITE_FLUSH(hw); ++ udelay(10); ++ core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); ++ *val = (u8)core_ctl; ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register ++ * @hw: pointer to hardware structure ++ * @reg: atlas register to write ++ * @val: value to write ++ * ++ * Performs write operation to Omer analog register specified. ++ **/ ++s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) ++{ ++ u32 core_ctl; ++ ++ core_ctl = (reg << 8) | val; ++ IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); ++ IXGBE_WRITE_FLUSH(hw); ++ udelay(10); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_start_hw_rev_1_82599 - Prepare hardware for Tx/Rx ++ * @hw: pointer to hardware structure ++ * ++ * Starts the hardware using the generic start_hw function. ++ * Then performs revision-specific operations: ++ * Clears the rate limiter registers. ++ **/ ++s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw) ++{ ++ u32 q_num; ++ s32 ret_val = 0; ++ ++ ret_val = ixgbe_start_hw_generic(hw); ++ ++ /* Clear the rate limiters */ ++ for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) { ++ IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num); ++ IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); ++ } ++ IXGBE_WRITE_FLUSH(hw); ++ ++ /* We need to run link autotry after the driver loads */ ++ hw->mac.autotry_restart = true; ++ ++ if (ret_val == 0) ++ ret_val = ixgbe_verify_fw_version_82599(hw); ++ return ret_val; ++} ++ ++/** ++ * ixgbe_identify_phy_82599 - Get physical layer module ++ * @hw: pointer to hardware structure ++ * ++ * Determines the physical layer module found on the current adapter. ++ * If PHY already detected, maintains current PHY type in hw struct, ++ * otherwise executes the PHY detection routine. ++ **/ ++s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) ++{ ++ s32 status = IXGBE_ERR_PHY_ADDR_INVALID; ++ ++ /* Detect PHY if not unknown - returns success if already detected. */ ++ status = ixgbe_identify_phy_generic(hw); ++ if (status != 0) ++ status = ixgbe_identify_sfp_module_generic(hw); ++ /* Set PHY type none if no PHY detected */ ++ if (hw->phy.type == ixgbe_phy_unknown) { ++ hw->phy.type = ixgbe_phy_none; ++ status = 0; ++ } ++ ++ /* Return error if SFP module has been detected but is not supported */ ++ if (hw->phy.type == ixgbe_phy_sfp_unsupported) ++ status = IXGBE_ERR_SFP_NOT_SUPPORTED; ++ ++ return status; ++} ++ ++/** ++ * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type ++ * @hw: pointer to hardware structure ++ * ++ * Determines physical layer capabilities of the current configuration. ++ **/ ++u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) ++{ ++ u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; ++ u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); ++ u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); ++ u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; ++ u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; ++ u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; ++ u16 ext_ability = 0; ++ u8 comp_codes_10g = 0; ++ ++ hw->phy.ops.identify(hw); ++ ++ if (hw->phy.type == ixgbe_phy_tn || ++ hw->phy.type == ixgbe_phy_aq || ++ hw->phy.type == ixgbe_phy_cu_unknown) { ++ hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, ++ IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); ++ if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) ++ physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; ++ if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) ++ physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; ++ if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) ++ physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; ++ goto out; ++ } ++ ++ switch (autoc & IXGBE_AUTOC_LMS_MASK) { ++ case IXGBE_AUTOC_LMS_1G_AN: ++ case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: ++ if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { ++ physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | ++ IXGBE_PHYSICAL_LAYER_1000BASE_BX; ++ goto out; ++ } else ++ /* SFI mode so read SFP module */ ++ goto sfp_check; ++ break; ++ case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: ++ if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) ++ physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; ++ else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) ++ physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; ++ else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) ++ physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; ++ goto out; ++ break; ++ case IXGBE_AUTOC_LMS_10G_SERIAL: ++ if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { ++ physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; ++ goto out; ++ } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) ++ goto sfp_check; ++ break; ++ case IXGBE_AUTOC_LMS_KX4_KX_KR: ++ case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: ++ if (autoc & IXGBE_AUTOC_KX_SUPP) ++ physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; ++ if (autoc & IXGBE_AUTOC_KX4_SUPP) ++ physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; ++ if (autoc & IXGBE_AUTOC_KR_SUPP) ++ physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; ++ goto out; ++ break; ++ default: ++ goto out; ++ break; ++ } ++ ++sfp_check: ++ /* SFP check must be done last since DA modules are sometimes used to ++ * test KR mode - we need to id KR mode correctly before SFP module. ++ * Call identify_sfp because the pluggable module may have changed */ ++ hw->phy.ops.identify_sfp(hw); ++ if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) ++ goto out; ++ ++ switch (hw->phy.type) { ++ case ixgbe_phy_tw_tyco: ++ case ixgbe_phy_tw_unknown: ++ physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; ++ break; ++ case ixgbe_phy_sfp_avago: ++ case ixgbe_phy_sfp_ftl: ++ case ixgbe_phy_sfp_intel: ++ case ixgbe_phy_sfp_unknown: ++ hw->phy.ops.read_i2c_eeprom(hw, ++ IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); ++ if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) ++ physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; ++ else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) ++ physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; ++ break; ++ default: ++ break; ++ } ++ ++out: ++ return physical_layer; ++} ++ ++/** ++ * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 ++ * @hw: pointer to hardware structure ++ * @regval: register value to write to RXCTRL ++ * ++ * Enables the Rx DMA unit for 82599 ++ **/ ++s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) ++{ ++#define IXGBE_MAX_SECRX_POLL 30 ++ int i; ++ int secrxreg; ++ ++ /* ++ * Workaround for 82599 silicon errata when enabling the Rx datapath. ++ * If traffic is incoming before we enable the Rx unit, it could hang ++ * the Rx DMA unit. Therefore, make sure the security engine is ++ * completely disabled prior to enabling the Rx unit. ++ */ ++ secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); ++ secrxreg |= IXGBE_SECRXCTRL_RX_DIS; ++ IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); ++ for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { ++ secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); ++ if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) ++ break; ++ else ++ /* Use interrupt-safe sleep just in case */ ++ udelay(10); ++ } ++ ++ /* For informational purposes only */ ++ if (i >= IXGBE_MAX_SECRX_POLL) ++ hw_dbg(hw, "Rx unit being enabled before security " ++ "path fully disabled. Continuing with init.\n"); ++ ++ IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); ++ secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); ++ secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; ++ IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); ++ IXGBE_WRITE_FLUSH(hw); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_get_device_caps_82599 - Get additional device capabilities ++ * @hw: pointer to hardware structure ++ * @device_caps: the EEPROM word with the extra device capabilities ++ * ++ * This function will read the EEPROM location for the device capabilities, ++ * and return the word through device_caps. ++ **/ ++s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps) ++{ ++ hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599 ++ * @hw: pointer to hardware structure ++ * @san_mac_offset: SAN MAC address offset ++ * ++ * This function will read the EEPROM location for the SAN MAC address ++ * pointer, and returns the value at that location. This is used in both ++ * get and set mac_addr routines. ++ **/ ++s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw, ++ u16 *san_mac_offset) ++{ ++ /* ++ * First read the EEPROM pointer to see if the MAC addresses are ++ * available. ++ */ ++ hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599 ++ * @hw: pointer to hardware structure ++ * @san_mac_addr: SAN MAC address ++ * ++ * Reads the SAN MAC address from the EEPROM, if it's available. This is ++ * per-port, so set_lan_id() must be called before reading the addresses. ++ * set_lan_id() is called by identify_sfp(), but this cannot be relied ++ * upon for non-SFP connections, so we must call it here. ++ **/ ++s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr) ++{ ++ u16 san_mac_data, san_mac_offset; ++ u8 i; ++ ++ /* ++ * First read the EEPROM pointer to see if the MAC addresses are ++ * available. If they're not, no point in calling set_lan_id() here. ++ */ ++ ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset); ++ ++ if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { ++ /* ++ * No addresses available in this EEPROM. It's not an ++ * error though, so just wipe the local address and return. ++ */ ++ for (i = 0; i < 6; i++) ++ san_mac_addr[i] = 0xFF; ++ ++ goto san_mac_addr_out; ++ } ++ ++ /* make sure we know which port we need to program */ ++ hw->mac.ops.set_lan_id(hw); ++ /* apply the port offset to the address offset */ ++ (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : ++ (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); ++ for (i = 0; i < 3; i++) { ++ hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data); ++ san_mac_addr[i * 2] = (u8)(san_mac_data); ++ san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); ++ san_mac_offset++; ++ } ++ ++san_mac_addr_out: ++ return 0; ++} ++ ++/** ++ * ixgbe_set_san_mac_addr_82599 - Write the SAN MAC address to the EEPROM ++ * @hw: pointer to hardware structure ++ * @san_mac_addr: SAN MAC address ++ * ++ * Write a SAN MAC address to the EEPROM. ++ **/ ++s32 ixgbe_set_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr) ++{ ++ s32 status = 0; ++ u16 san_mac_data, san_mac_offset; ++ u8 i; ++ ++ /* Look for SAN mac address pointer. If not defined, return */ ++ ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset); ++ ++ if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { ++ status = IXGBE_ERR_NO_SAN_ADDR_PTR; ++ goto san_mac_addr_out; ++ } ++ ++ /* Make sure we know which port we need to write */ ++ hw->mac.ops.set_lan_id(hw); ++ /* Apply the port offset to the address offset */ ++ (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : ++ (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); ++ ++ for (i = 0; i < 3; i++) { ++ san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); ++ san_mac_data |= (u16)(san_mac_addr[i * 2]); ++ hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); ++ san_mac_offset++; ++ } ++ ++san_mac_addr_out: ++ return status; ++} ++ ++/** ++ * ixgbe_verify_fw_version_82599 - verify fw version for 82599 ++ * @hw: pointer to hardware structure ++ * ++ * Verifies that installed the firmware version is 0.6 or higher ++ * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. ++ * ++ * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or ++ * if the FW version is not supported. ++ **/ ++static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) ++{ ++ s32 status = IXGBE_ERR_EEPROM_VERSION; ++ u16 fw_offset, fw_ptp_cfg_offset; ++ u16 fw_version = 0; ++ ++ /* firmware check is only necessary for SFI devices */ ++ if (hw->phy.media_type != ixgbe_media_type_fiber) { ++ status = 0; ++ goto fw_version_out; ++ } ++ ++ /* get the offset to the Firmware Module block */ ++ hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); ++ ++ if ((fw_offset == 0) || (fw_offset == 0xFFFF)) ++ goto fw_version_out; ++ ++ /* get the offset to the Pass Through Patch Configuration block */ ++ hw->eeprom.ops.read(hw, (fw_offset + ++ IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), ++ &fw_ptp_cfg_offset); ++ ++ if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) ++ goto fw_version_out; ++ ++ /* get the firmware version */ ++ hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + ++ IXGBE_FW_PATCH_VERSION_4), ++ &fw_version); ++ ++ if (fw_version > 0x5) ++ status = 0; ++ ++fw_version_out: ++ return status; ++} +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_api.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/ixgbe/ixgbe_api.c Wed Aug 05 11:05:50 2009 +0100 +@@ -0,0 +1,958 @@ ++/******************************************************************************* ++ ++ Intel 10 Gigabit PCI Express Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "ixgbe_api.h" ++#include "ixgbe_common.h" ++ ++extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); ++extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); ++ ++/** ++ * ixgbe_init_shared_code - Initialize the shared code ++ * @hw: pointer to hardware structure ++ * ++ * This will assign function pointers and assign the MAC type and PHY code. ++ * Does not touch the hardware. This function must be called prior to any ++ * other function in the shared code. The ixgbe_hw structure should be ++ * memset to 0 prior to calling this function. The following fields in ++ * hw structure should be filled in prior to calling this function: ++ * hw_addr, back, device_id, vendor_id, subsystem_device_id, ++ * subsystem_vendor_id, and revision_id ++ **/ ++s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) ++{ ++ s32 status; ++ ++ /* ++ * Set the mac type ++ */ ++ ixgbe_set_mac_type(hw); ++ ++ switch (hw->mac.type) { ++ case ixgbe_mac_82598EB: ++ status = ixgbe_init_ops_82598(hw); ++ break; ++ case ixgbe_mac_82599EB: ++ status = ixgbe_init_ops_82599(hw); ++ break; ++ default: ++ status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; ++ break; ++ } ++ ++ return status; ++} ++ ++/** ++ * ixgbe_set_mac_type - Sets MAC type ++ * @hw: pointer to the HW structure ++ * ++ * This function sets the mac type of the adapter based on the ++ * vendor ID and device ID stored in the hw structure. ++ **/ ++s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) ++{ ++ s32 ret_val = 0; ++ ++ if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) { ++ switch (hw->device_id) { ++ case IXGBE_DEV_ID_82598: ++ case IXGBE_DEV_ID_82598_BX: ++ case IXGBE_DEV_ID_82598AF_SINGLE_PORT: ++ case IXGBE_DEV_ID_82598AF_DUAL_PORT: ++ case IXGBE_DEV_ID_82598AT: ++ case IXGBE_DEV_ID_82598AT2: ++ case IXGBE_DEV_ID_82598EB_CX4: ++ case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: ++ case IXGBE_DEV_ID_82598_DA_DUAL_PORT: ++ case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: ++ case IXGBE_DEV_ID_82598EB_XF_LR: ++ case IXGBE_DEV_ID_82598EB_SFP_LOM: ++ hw->mac.type = ixgbe_mac_82598EB; ++ break; ++ case IXGBE_DEV_ID_82599_KX4: ++ case IXGBE_DEV_ID_82599_XAUI_LOM: ++ case IXGBE_DEV_ID_82599_SFP: ++ hw->mac.type = ixgbe_mac_82599EB; ++ break; ++ default: ++ ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; ++ break; ++ } ++ } else { ++ ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; ++ } ++ ++ hw_dbg(hw, "ixgbe_set_mac_type found mac: %d, returns: %d\n", ++ hw->mac.type, ret_val); ++ return ret_val; ++} ++ ++/** ++ * ixgbe_init_hw - Initialize the hardware ++ * @hw: pointer to hardware structure ++ * ++ * Initialize the hardware by resetting and then starting the hardware ++ **/ ++s32 ixgbe_init_hw(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_reset_hw - Performs a hardware reset ++ * @hw: pointer to hardware structure ++ * ++ * Resets the hardware by resetting the transmit and receive units, masks and ++ * clears all interrupts, performs a PHY reset, and performs a MAC reset ++ **/ ++s32 ixgbe_reset_hw(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_start_hw - Prepares hardware for Rx/Tx ++ * @hw: pointer to hardware structure ++ * ++ * Starts the hardware by filling the bus info structure and media type, ++ * clears all on chip counters, initializes receive address registers, ++ * multicast table, VLAN filter table, calls routine to setup link and ++ * flow control settings, and leaves transmit and receive units disabled ++ * and uninitialized. ++ **/ ++s32 ixgbe_start_hw(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_clear_hw_cntrs - Clear hardware counters ++ * @hw: pointer to hardware structure ++ * ++ * Clears all hardware statistics counters by reading them from the hardware ++ * Statistics counters are clear on read. ++ **/ ++s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_get_media_type - Get media type ++ * @hw: pointer to hardware structure ++ * ++ * Returns the media type (fiber, copper, backplane) ++ **/ ++enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), ++ ixgbe_media_type_unknown); ++} ++ ++/** ++ * ixgbe_get_mac_addr - Get MAC address ++ * @hw: pointer to hardware structure ++ * @mac_addr: Adapter MAC address ++ * ++ * Reads the adapter's MAC address from the first Receive Address Register ++ * (RAR0) A reset of the adapter must have been performed prior to calling ++ * this function in order for the MAC address to have been loaded from the ++ * EEPROM into RAR0 ++ **/ ++s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, ++ (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_get_san_mac_addr - Get SAN MAC address ++ * @hw: pointer to hardware structure ++ * @san_mac_addr: SAN MAC address ++ * ++ * Reads the SAN MAC address from the EEPROM, if it's available. This is ++ * per-port, so set_lan_id() must be called before reading the addresses. ++ **/ ++s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, ++ (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_set_san_mac_addr - Write a SAN MAC address ++ * @hw: pointer to hardware structure ++ * @san_mac_addr: SAN MAC address ++ * ++ * Writes A SAN MAC address to the EEPROM. ++ **/ ++s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, ++ (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_get_device_caps - Get additional device capabilities ++ * @hw: pointer to hardware structure ++ * @device_caps: the EEPROM word for device capabilities ++ * ++ * Reads the extra device capabilities from the EEPROM ++ **/ ++s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, ++ (hw, device_caps), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_get_bus_info - Set PCI bus info ++ * @hw: pointer to hardware structure ++ * ++ * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure ++ **/ ++s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_get_num_of_tx_queues - Get Tx queues ++ * @hw: pointer to hardware structure ++ * ++ * Returns the number of transmit queues for the given adapter. ++ **/ ++u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) ++{ ++ return hw->mac.max_tx_queues; ++} ++ ++/** ++ * ixgbe_get_num_of_rx_queues - Get Rx queues ++ * @hw: pointer to hardware structure ++ * ++ * Returns the number of receive queues for the given adapter. ++ **/ ++u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) ++{ ++ return hw->mac.max_rx_queues; ++} ++ ++/** ++ * ixgbe_stop_adapter - Disable Rx/Tx units ++ * @hw: pointer to hardware structure ++ * ++ * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, ++ * disables transmit and receive units. The adapter_stopped flag is used by ++ * the shared code and drivers to determine if the adapter is in a stopped ++ * state and should not touch the hardware. ++ **/ ++s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_read_pba_num - Reads part number from EEPROM ++ * @hw: pointer to hardware structure ++ * @pba_num: stores the part number from the EEPROM ++ * ++ * Reads the part number from the EEPROM. ++ **/ ++s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) ++{ ++ return ixgbe_read_pba_num_generic(hw, pba_num); ++} ++ ++/** ++ * ixgbe_identify_phy - Get PHY type ++ * @hw: pointer to hardware structure ++ * ++ * Determines the physical layer module found on the current adapter. ++ **/ ++s32 ixgbe_identify_phy(struct ixgbe_hw *hw) ++{ ++ s32 status = 0; ++ ++ if (hw->phy.type == ixgbe_phy_unknown) { ++ status = ixgbe_call_func(hw, ++ hw->phy.ops.identify, ++ (hw), ++ IXGBE_NOT_IMPLEMENTED); ++ } ++ ++ return status; ++} ++ ++/** ++ * ixgbe_reset_phy - Perform a PHY reset ++ * @hw: pointer to hardware structure ++ **/ ++s32 ixgbe_reset_phy(struct ixgbe_hw *hw) ++{ ++ s32 status = 0; ++ ++ if (hw->phy.type == ixgbe_phy_unknown) { ++ if (ixgbe_identify_phy(hw) != 0) ++ status = IXGBE_ERR_PHY; ++ } ++ ++ if (status == 0) { ++ status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++ } ++ return status; ++} ++ ++/** ++ * ixgbe_get_phy_firmware_version - ++ * @hw: pointer to hardware structure ++ * @firmware_version: pointer to firmware version ++ **/ ++s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) ++{ ++ s32 status = 0; ++ ++ status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, ++ (hw, firmware_version), ++ IXGBE_NOT_IMPLEMENTED); ++ return status; ++} ++ ++/** ++ * ixgbe_read_phy_reg - Read PHY register ++ * @hw: pointer to hardware structure ++ * @reg_addr: 32 bit address of PHY register to read ++ * @phy_data: Pointer to read data from PHY register ++ * ++ * Reads a value from a specified PHY register ++ **/ ++s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, ++ u16 *phy_data) ++{ ++ if (hw->phy.id == 0) ++ ixgbe_identify_phy(hw); ++ ++ return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, ++ device_type, phy_data), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_write_phy_reg - Write PHY register ++ * @hw: pointer to hardware structure ++ * @reg_addr: 32 bit PHY register to write ++ * @phy_data: Data to write to the PHY register ++ * ++ * Writes a value to specified PHY register ++ **/ ++s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, ++ u16 phy_data) ++{ ++ if (hw->phy.id == 0) ++ ixgbe_identify_phy(hw); ++ ++ return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, ++ device_type, phy_data), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_setup_phy_link - Restart PHY autoneg ++ * @hw: pointer to hardware structure ++ * ++ * Restart autonegotiation and PHY and waits for completion. ++ **/ ++s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_check_phy_link - Determine link and speed status ++ * @hw: pointer to hardware structure ++ * ++ * Reads a PHY register to determine if link is up and the current speed for ++ * the PHY. ++ **/ ++s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, ++ bool *link_up) ++{ ++ return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, ++ link_up), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_setup_phy_link_speed - Set auto advertise ++ * @hw: pointer to hardware structure ++ * @speed: new link speed ++ * @autoneg: true if autonegotiation enabled ++ * ++ * Sets the auto advertised capabilities ++ **/ ++s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, ++ bool autoneg, ++ bool autoneg_wait_to_complete) ++{ ++ return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, ++ autoneg, autoneg_wait_to_complete), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_setup_link - Configure link settings ++ * @hw: pointer to hardware structure ++ * ++ * Configures link settings based on values in the ixgbe_hw struct. ++ * Restarts the link. Performs autonegotiation if needed. ++ **/ ++s32 ixgbe_setup_link(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_check_link - Get link and speed status ++ * @hw: pointer to hardware structure ++ * ++ * Reads the links register to determine if link is up and the current speed ++ **/ ++s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, ++ bool *link_up, bool link_up_wait_to_complete) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, ++ link_up, link_up_wait_to_complete), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_setup_link_speed - Set link speed ++ * @hw: pointer to hardware structure ++ * @speed: new link speed ++ * @autoneg: true if autonegotiation enabled ++ * ++ * Set the link speed and restarts the link. ++ **/ ++s32 ixgbe_setup_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, ++ bool autoneg, ++ bool autoneg_wait_to_complete) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.setup_link_speed, (hw, speed, ++ autoneg, autoneg_wait_to_complete), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_get_link_capabilities - Returns link capabilities ++ * @hw: pointer to hardware structure ++ * ++ * Determines the link capabilities of the current configuration. ++ **/ ++s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, ++ bool *autoneg) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, ++ speed, autoneg), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_led_on - Turn on LEDs ++ * @hw: pointer to hardware structure ++ * @index: led number to turn on ++ * ++ * Turns on the software controllable LEDs. ++ **/ ++s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_led_off - Turn off LEDs ++ * @hw: pointer to hardware structure ++ * @index: led number to turn off ++ * ++ * Turns off the software controllable LEDs. ++ **/ ++s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_blink_led_start - Blink LEDs ++ * @hw: pointer to hardware structure ++ * @index: led number to blink ++ * ++ * Blink LED based on index. ++ **/ ++s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_blink_led_stop - Stop blinking LEDs ++ * @hw: pointer to hardware structure ++ * ++ * Stop blinking LED based on index. ++ **/ ++s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_init_eeprom_params - Initialize EEPROM parameters ++ * @hw: pointer to hardware structure ++ * ++ * Initializes the EEPROM parameters ixgbe_eeprom_info within the ++ * ixgbe_hw struct in order to set up EEPROM access. ++ **/ ++s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++ ++/** ++ * ixgbe_write_eeprom - Write word to EEPROM ++ * @hw: pointer to hardware structure ++ * @offset: offset within the EEPROM to be written to ++ * @data: 16 bit word to be written to the EEPROM ++ * ++ * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not ++ * called after this function, the EEPROM will most likely contain an ++ * invalid checksum. ++ **/ ++s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) ++{ ++ return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_read_eeprom - Read word from EEPROM ++ * @hw: pointer to hardware structure ++ * @offset: offset within the EEPROM to be read ++ * @data: read 16 bit value from EEPROM ++ * ++ * Reads 16 bit value from EEPROM ++ **/ ++s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) ++{ ++ return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum ++ * @hw: pointer to hardware structure ++ * @checksum_val: calculated checksum ++ * ++ * Performs checksum calculation and validates the EEPROM checksum ++ **/ ++s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) ++{ ++ return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, ++ (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum ++ * @hw: pointer to hardware structure ++ **/ ++s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_insert_mac_addr - Find a RAR for this mac address ++ * @hw: pointer to hardware structure ++ * @addr: Address to put into receive address register ++ * @vmdq: VMDq pool to assign ++ * ++ * Puts an ethernet address into a receive address register, or ++ * finds the rar that it is aleady in; adds to the pool list ++ **/ ++s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, ++ (hw, addr, vmdq), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_set_rar - Set Rx address register ++ * @hw: pointer to hardware structure ++ * @index: Receive address register to write ++ * @addr: Address to put into receive address register ++ * @vmdq: VMDq "set" ++ * @enable_addr: set flag that address is active ++ * ++ * Puts an ethernet address into a receive address register. ++ **/ ++s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, ++ u32 enable_addr) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, ++ enable_addr), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_clear_rar - Clear Rx address register ++ * @hw: pointer to hardware structure ++ * @index: Receive address register to write ++ * ++ * Puts an ethernet address into a receive address register. ++ **/ ++s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_set_vmdq - Associate a VMDq index with a receive address ++ * @hw: pointer to hardware structure ++ * @rar: receive address register index to associate with VMDq index ++ * @vmdq: VMDq set or pool index ++ **/ ++s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address ++ * @hw: pointer to hardware structure ++ * @rar: receive address register index to disassociate with VMDq index ++ * @vmdq: VMDq set or pool index ++ **/ ++s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_init_rx_addrs - Initializes receive address filters. ++ * @hw: pointer to hardware structure ++ * ++ * Places the MAC address in receive address register 0 and clears the rest ++ * of the receive address registers. Clears the multicast table. Assumes ++ * the receiver is in reset when the routine is called. ++ **/ ++s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. ++ * @hw: pointer to hardware structure ++ **/ ++u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) ++{ ++ return hw->mac.num_rar_entries; ++} ++ ++/** ++ * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses ++ * @hw: pointer to hardware structure ++ * @addr_list: the list of new multicast addresses ++ * @addr_count: number of addresses ++ * @func: iterator function to walk the multicast address list ++ * ++ * The given list replaces any existing list. Clears the secondary addrs from ++ * receive address registers. Uses unused receive address registers for the ++ * first secondary addresses, and falls back to promiscuous mode as needed. ++ **/ ++s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, ++ u32 addr_count, ixgbe_mc_addr_itr func) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, ++ addr_list, addr_count, func), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses ++ * @hw: pointer to hardware structure ++ * @mc_addr_list: the list of new multicast addresses ++ * @mc_addr_count: number of addresses ++ * @func: iterator function to walk the multicast address list ++ * ++ * The given list replaces any existing list. Clears the MC addrs from receive ++ * address registers and the multicast table. Uses unused receive address ++ * registers for the first multicast addresses, and hashes the rest into the ++ * multicast table. ++ **/ ++s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, ++ u32 mc_addr_count, ixgbe_mc_addr_itr func) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, ++ mc_addr_list, mc_addr_count, func), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_enable_mc - Enable multicast address in RAR ++ * @hw: pointer to hardware structure ++ * ++ * Enables multicast address in RAR and the use of the multicast hash table. ++ **/ ++s32 ixgbe_enable_mc(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_disable_mc - Disable multicast address in RAR ++ * @hw: pointer to hardware structure ++ * ++ * Disables multicast address in RAR and the use of the multicast hash table. ++ **/ ++s32 ixgbe_disable_mc(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_clear_vfta - Clear VLAN filter table ++ * @hw: pointer to hardware structure ++ * ++ * Clears the VLAN filer table, and the VMDq index associated with the filter ++ **/ ++s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_set_vfta - Set VLAN filter table ++ * @hw: pointer to hardware structure ++ * @vlan: VLAN id to write to VLAN filter ++ * @vind: VMDq output index that maps queue to VLAN id in VFTA ++ * @vlan_on: boolean flag to turn on/off VLAN in VFTA ++ * ++ * Turn on/off specified VLAN in the VLAN filter table. ++ **/ ++s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, ++ vlan_on), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_fc_enable - Enable flow control ++ * @hw: pointer to hardware structure ++ * @packetbuf_num: packet buffer number (0-7) ++ * ++ * Configures the flow control settings based on SW configuration. ++ **/ ++s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_read_analog_reg8 - Reads 8 bit analog register ++ * @hw: pointer to hardware structure ++ * @reg: analog register to read ++ * @val: read value ++ * ++ * Performs write operation to analog register specified. ++ **/ ++s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, ++ val), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_write_analog_reg8 - Writes 8 bit analog register ++ * @hw: pointer to hardware structure ++ * @reg: analog register to write ++ * @val: value to write ++ * ++ * Performs write operation to Atlas analog register specified. ++ **/ ++s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, ++ val), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. ++ * @hw: pointer to hardware structure ++ * ++ * Initializes the Unicast Table Arrays to zero on device load. This ++ * is part of the Rx init addr execution path. ++ **/ ++s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address ++ * @hw: pointer to hardware structure ++ * @byte_offset: byte offset to read ++ * @data: value read ++ * ++ * Performs byte read operation to SFP module's EEPROM over I2C interface. ++ **/ ++s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, ++ u8 *data) ++{ ++ return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, ++ dev_addr, data), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_write_i2c_byte - Writes 8 bit word over I2C ++ * @hw: pointer to hardware structure ++ * @byte_offset: byte offset to write ++ * @data: value to write ++ * ++ * Performs byte write operation to SFP module's EEPROM over I2C interface ++ * at a specified device address. ++ **/ ++s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, ++ u8 data) ++{ ++ return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, ++ dev_addr, data), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface ++ * @hw: pointer to hardware structure ++ * @byte_offset: EEPROM byte offset to write ++ * @eeprom_data: value to write ++ * ++ * Performs byte write operation to SFP module's EEPROM over I2C interface. ++ **/ ++s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, ++ u8 byte_offset, u8 eeprom_data) ++{ ++ return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, ++ (hw, byte_offset, eeprom_data), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface ++ * @hw: pointer to hardware structure ++ * @byte_offset: EEPROM byte offset to read ++ * @eeprom_data: value read ++ * ++ * Performs byte read operation to SFP module's EEPROM over I2C interface. ++ **/ ++s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) ++{ ++ return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, ++ (hw, byte_offset, eeprom_data), ++ IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_get_supported_physical_layer - Returns physical layer type ++ * @hw: pointer to hardware structure ++ * ++ * Determines physical layer capabilities of the current configuration. ++ **/ ++u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, ++ (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); ++} ++ ++/** ++ * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics ++ * @hw: pointer to hardware structure ++ * @regval: bitfield to write to the Rx DMA register ++ * ++ * Enables the Rx DMA unit of the device. ++ **/ ++s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, ++ (hw, regval), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore ++ * @hw: pointer to hardware structure ++ * @mask: Mask to specify which semaphore to acquire ++ * ++ * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified ++ * function (CSR, PHY0, PHY1, EEPROM, Flash) ++ **/ ++s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) ++{ ++ return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, ++ (hw, mask), IXGBE_NOT_IMPLEMENTED); ++} ++ ++/** ++ * ixgbe_release_swfw_semaphore - Release SWFW semaphore ++ * @hw: pointer to hardware structure ++ * @mask: Mask to specify which semaphore to release ++ * ++ * Releases the SWFW semaphore through SW_FW_SYNC register for the specified ++ * function (CSR, PHY0, PHY1, EEPROM, Flash) ++ **/ ++void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) ++{ ++ if (hw->mac.ops.release_swfw_sync) ++ hw->mac.ops.release_swfw_sync(hw, mask); ++} ++ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_api.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/ixgbe/ixgbe_api.h Wed Aug 05 11:05:50 2009 +0100 +@@ -0,0 +1,163 @@ ++/******************************************************************************* ++ ++ Intel 10 Gigabit PCI Express Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _IXGBE_API_H_ ++#define _IXGBE_API_H_ ++ ++#include "ixgbe_type.h" ++ ++s32 ixgbe_init_shared_code(struct ixgbe_hw *hw); ++ ++s32 ixgbe_set_mac_type(struct ixgbe_hw *hw); ++s32 ixgbe_init_hw(struct ixgbe_hw *hw); ++s32 ixgbe_reset_hw(struct ixgbe_hw *hw); ++s32 ixgbe_start_hw(struct ixgbe_hw *hw); ++s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw); ++enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw); ++s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr); ++s32 ixgbe_get_bus_info(struct ixgbe_hw *hw); ++u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw); ++u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw); ++s32 ixgbe_stop_adapter(struct ixgbe_hw *hw); ++s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num); ++ ++s32 ixgbe_identify_phy(struct ixgbe_hw *hw); ++s32 ixgbe_reset_phy(struct ixgbe_hw *hw); ++s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, ++ u16 *phy_data); ++s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, ++ u16 phy_data); ++ ++s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw); ++s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ++ ixgbe_link_speed *speed, ++ bool *link_up); ++s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ++ ixgbe_link_speed speed, ++ bool autoneg, ++ bool autoneg_wait_to_complete); ++s32 ixgbe_setup_link(struct ixgbe_hw *hw); ++s32 ixgbe_setup_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, ++ bool autoneg, bool autoneg_wait_to_complete); ++s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, ++ bool *link_up, bool link_up_wait_to_complete); ++s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, ++ bool *autoneg); ++s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index); ++s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index); ++s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index); ++s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index); ++ ++s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw); ++s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data); ++s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data); ++s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val); ++s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw); ++ ++s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); ++s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, ++ u32 enable_addr); ++s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index); ++s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq); ++s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq); ++s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw); ++u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw); ++s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, ++ u32 addr_count, ixgbe_mc_addr_itr func); ++s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, ++ u32 mc_addr_count, ixgbe_mc_addr_itr func); ++void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq); ++s32 ixgbe_enable_mc(struct ixgbe_hw *hw); ++s32 ixgbe_disable_mc(struct ixgbe_hw *hw); ++s32 ixgbe_clear_vfta(struct ixgbe_hw *hw); ++s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, ++ u32 vind, bool vlan_on); ++ ++s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num); ++ ++void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr); ++s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, ++ u16 *firmware_version); ++s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val); ++s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val); ++s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw); ++s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data); ++u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw); ++s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval); ++s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); ++s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc); ++s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc); ++s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, ++ struct ixgbe_atr_input *input, ++ u8 queue); ++s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, ++ struct ixgbe_atr_input *input, ++ u16 soft_id, ++ u8 queue); ++u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *input, u32 key); ++s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan_id); ++s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr); ++s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr); ++s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input, u32 src_addr_1, ++ u32 src_addr_2, u32 src_addr_3, ++ u32 src_addr_4); ++s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input, u32 dst_addr_1, ++ u32 dst_addr_2, u32 dst_addr_3, ++ u32 dst_addr_4); ++s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port); ++s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port); ++s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte); ++s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input, u8 vm_pool); ++s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type); ++s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan_id); ++s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input, u32 *src_addr); ++s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 *dst_addr); ++s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input, u32 *src_addr_1, ++ u32 *src_addr_2, u32 *src_addr_3, ++ u32 *src_addr_4); ++s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input, u32 *dst_addr_1, ++ u32 *dst_addr_2, u32 *dst_addr_3, ++ u32 *dst_addr_4); ++s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input, u16 *src_port); ++s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input, u16 *dst_port); ++s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input, ++ u16 *flex_byte); ++s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input, u8 *vm_pool); ++s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input, u8 *l4type); ++s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, ++ u8 *data); ++s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, ++ u8 data); ++s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data); ++s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr); ++s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr); ++s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps); ++s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask); ++void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask); ++ ++ ++#endif /* _IXGBE_API_H_ */ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_common.c +--- a/drivers/net/ixgbe/ixgbe_common.c Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe_common.c Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -25,12 +25,8 @@ + + *******************************************************************************/ + +-#include +-#include +-#include +- + #include "ixgbe_common.h" +-#include "ixgbe_phy.h" ++#include "ixgbe_api.h" + + static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); + static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); +@@ -46,11 +42,79 @@ + static void ixgbe_release_eeprom(struct ixgbe_hw *hw); + static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); + +-static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index); +-static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index); + static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); +-static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr); +-static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); ++ ++/** ++ * ixgbe_init_ops_generic - Inits function ptrs ++ * @hw: pointer to the hardware structure ++ * ++ * Initialize the function pointers. ++ **/ ++s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) ++{ ++ struct ixgbe_eeprom_info *eeprom = &hw->eeprom; ++ struct ixgbe_mac_info *mac = &hw->mac; ++ u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); ++ ++ /* EEPROM */ ++ eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; ++ /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ ++ if (eec & (1 << 8)) ++ eeprom->ops.read = &ixgbe_read_eeprom_generic; ++ else ++ eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; ++ eeprom->ops.write = &ixgbe_write_eeprom_generic; ++ eeprom->ops.validate_checksum = ++ &ixgbe_validate_eeprom_checksum_generic; ++ eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; ++ ++ /* MAC */ ++ mac->ops.init_hw = &ixgbe_init_hw_generic; ++ mac->ops.reset_hw = NULL; ++ mac->ops.start_hw = &ixgbe_start_hw_generic; ++ mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; ++ mac->ops.get_media_type = NULL; ++ mac->ops.get_supported_physical_layer = NULL; ++ mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic; ++ mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; ++ mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; ++ mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; ++ mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie; ++ mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync; ++ mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync; ++ ++ /* LEDs */ ++ mac->ops.led_on = &ixgbe_led_on_generic; ++ mac->ops.led_off = &ixgbe_led_off_generic; ++ mac->ops.blink_led_start = &ixgbe_blink_led_start_generic; ++ mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic; ++ ++ /* RAR, Multicast, VLAN */ ++ mac->ops.set_rar = &ixgbe_set_rar_generic; ++ mac->ops.clear_rar = &ixgbe_clear_rar_generic; ++ mac->ops.insert_mac_addr = NULL; ++ mac->ops.set_vmdq = NULL; ++ mac->ops.clear_vmdq = NULL; ++ mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; ++ mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; ++ mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; ++ mac->ops.enable_mc = &ixgbe_enable_mc_generic; ++ mac->ops.disable_mc = &ixgbe_disable_mc_generic; ++ mac->ops.clear_vfta = NULL; ++ mac->ops.set_vfta = NULL; ++ mac->ops.init_uta_tables = NULL; ++ ++ /* Flow Control */ ++ mac->ops.fc_enable = &ixgbe_fc_enable_generic; ++ ++ /* Link */ ++ mac->ops.get_link_capabilities = NULL; ++ mac->ops.setup_link = NULL; ++ mac->ops.setup_link_speed = NULL; ++ mac->ops.check_link = NULL; ++ ++ return 0; ++} + + /** + * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx +@@ -64,24 +128,15 @@ + s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) + { + u32 ctrl_ext; ++ s32 ret_val = 0; + + /* Set the media type */ + hw->phy.media_type = hw->mac.ops.get_media_type(hw); + +- /* Identify the PHY */ +- hw->phy.ops.identify(hw); +- +- /* +- * Store MAC address from RAR0, clear receive address registers, and +- * clear the multicast table +- */ +- hw->mac.ops.init_rx_addrs(hw); ++ /* PHY ops initialization must be done in reset_hw() */ + + /* Clear the VLAN filter table */ + hw->mac.ops.clear_vfta(hw); +- +- /* Set up link */ +- hw->mac.ops.setup_link(hw); + + /* Clear statistics registers */ + hw->mac.ops.clear_hw_cntrs(hw); +@@ -92,10 +147,13 @@ + IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); + IXGBE_WRITE_FLUSH(hw); + ++ /* Setup flow control */ ++ ixgbe_setup_fc(hw, 0); ++ + /* Clear adapter stopped flag */ + hw->adapter_stopped = false; + +- return 0; ++ return ret_val; + } + + /** +@@ -110,13 +168,17 @@ + **/ + s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) + { ++ s32 status = 0; ++ + /* Reset the hardware */ +- hw->mac.ops.reset_hw(hw); ++ status = hw->mac.ops.reset_hw(hw); + +- /* Start the HW */ +- hw->mac.ops.start_hw(hw); ++ if (status == 0) { ++ /* Start the HW */ ++ status = hw->mac.ops.start_hw(hw); ++ } + +- return 0; ++ return status; + } + + /** +@@ -141,17 +203,29 @@ + IXGBE_READ_REG(hw, IXGBE_MRFC); + IXGBE_READ_REG(hw, IXGBE_RLEC); + IXGBE_READ_REG(hw, IXGBE_LXONTXC); +- IXGBE_READ_REG(hw, IXGBE_LXONRXC); + IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); +- IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); ++ if (hw->mac.type >= ixgbe_mac_82599EB) { ++ IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); ++ IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); ++ } else { ++ IXGBE_READ_REG(hw, IXGBE_LXONRXC); ++ IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); ++ } + + for (i = 0; i < 8; i++) { + IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); +- IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); + IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); +- IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); ++ if (hw->mac.type >= ixgbe_mac_82599EB) { ++ IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); ++ IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); ++ } else { ++ IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); ++ IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); ++ } + } +- ++ if (hw->mac.type >= ixgbe_mac_82599EB) ++ for (i = 0; i < 8; i++) ++ IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); + IXGBE_READ_REG(hw, IXGBE_PRC64); + IXGBE_READ_REG(hw, IXGBE_PRC127); + IXGBE_READ_REG(hw, IXGBE_PRC255); +@@ -251,6 +325,79 @@ + mac_addr[i+4] = (u8)(rar_high >> (i*8)); + + return 0; ++} ++ ++/** ++ * ixgbe_get_bus_info_generic - Generic set PCI bus info ++ * @hw: pointer to hardware structure ++ * ++ * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure ++ **/ ++s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) ++{ ++ struct ixgbe_mac_info *mac = &hw->mac; ++ u16 link_status; ++ ++ hw->bus.type = ixgbe_bus_type_pci_express; ++ ++ /* Get the negotiated link width and speed from PCI config space */ ++ link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); ++ ++ switch (link_status & IXGBE_PCI_LINK_WIDTH) { ++ case IXGBE_PCI_LINK_WIDTH_1: ++ hw->bus.width = ixgbe_bus_width_pcie_x1; ++ break; ++ case IXGBE_PCI_LINK_WIDTH_2: ++ hw->bus.width = ixgbe_bus_width_pcie_x2; ++ break; ++ case IXGBE_PCI_LINK_WIDTH_4: ++ hw->bus.width = ixgbe_bus_width_pcie_x4; ++ break; ++ case IXGBE_PCI_LINK_WIDTH_8: ++ hw->bus.width = ixgbe_bus_width_pcie_x8; ++ break; ++ default: ++ hw->bus.width = ixgbe_bus_width_unknown; ++ break; ++ } ++ ++ switch (link_status & IXGBE_PCI_LINK_SPEED) { ++ case IXGBE_PCI_LINK_SPEED_2500: ++ hw->bus.speed = ixgbe_bus_speed_2500; ++ break; ++ case IXGBE_PCI_LINK_SPEED_5000: ++ hw->bus.speed = ixgbe_bus_speed_5000; ++ break; ++ default: ++ hw->bus.speed = ixgbe_bus_speed_unknown; ++ break; ++ } ++ ++ mac->ops.set_lan_id(hw); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices ++ * @hw: pointer to the HW structure ++ * ++ * Determines the LAN function id by reading memory-mapped registers ++ * and swaps the port value if requested. ++ **/ ++void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) ++{ ++ struct ixgbe_bus_info *bus = &hw->bus; ++ u32 reg; ++ ++ reg = IXGBE_READ_REG(hw, IXGBE_STATUS); ++ bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; ++ bus->lan_id = bus->func; ++ ++ /* check for a port swap */ ++ reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); ++ if (reg & IXGBE_FACTPS_LFS) ++ bus->func ^= 0x1; + } + + /** +@@ -375,9 +522,9 @@ + * change if a future EEPROM is not SPI. + */ + eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> +- IXGBE_EEC_SIZE_SHIFT); ++ IXGBE_EEC_SIZE_SHIFT); + eeprom->word_size = 1 << (eeprom_size + +- IXGBE_EEPROM_WORD_SIZE_SHIFT); ++ IXGBE_EEPROM_WORD_SIZE_SHIFT); + } + + if (eec & IXGBE_EEC_ADDR_SIZE) +@@ -385,11 +532,77 @@ + else + eeprom->address_bits = 8; + hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: " +- "%d\n", eeprom->type, eeprom->word_size, +- eeprom->address_bits); ++ "%d\n", eeprom->type, eeprom->word_size, ++ eeprom->address_bits); + } + + return 0; ++} ++ ++/** ++ * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM ++ * @hw: pointer to hardware structure ++ * @offset: offset within the EEPROM to be written to ++ * @data: 16 bit word to be written to the EEPROM ++ * ++ * If ixgbe_eeprom_update_checksum is not called after this function, the ++ * EEPROM will most likely contain an invalid checksum. ++ **/ ++s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) ++{ ++ s32 status; ++ u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; ++ ++ hw->eeprom.ops.init_params(hw); ++ ++ if (offset >= hw->eeprom.word_size) { ++ status = IXGBE_ERR_EEPROM; ++ goto out; ++ } ++ ++ /* Prepare the EEPROM for writing */ ++ status = ixgbe_acquire_eeprom(hw); ++ ++ if (status == 0) { ++ if (ixgbe_ready_eeprom(hw) != 0) { ++ ixgbe_release_eeprom(hw); ++ status = IXGBE_ERR_EEPROM; ++ } ++ } ++ ++ if (status == 0) { ++ ixgbe_standby_eeprom(hw); ++ ++ /* Send the WRITE ENABLE command (8 bit opcode ) */ ++ ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, ++ IXGBE_EEPROM_OPCODE_BITS); ++ ++ ixgbe_standby_eeprom(hw); ++ ++ /* ++ * Some SPI eeproms use the 8th address bit embedded in the ++ * opcode ++ */ ++ if ((hw->eeprom.address_bits == 8) && (offset >= 128)) ++ write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; ++ ++ /* Send the Write command (8-bit opcode + addr) */ ++ ixgbe_shift_out_eeprom_bits(hw, write_opcode, ++ IXGBE_EEPROM_OPCODE_BITS); ++ ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), ++ hw->eeprom.address_bits); ++ ++ /* Send the data */ ++ data = (data >> 8) | (data << 8); ++ ixgbe_shift_out_eeprom_bits(hw, data, 16); ++ ixgbe_standby_eeprom(hw); ++ ++ /* Done with writing - release the EEPROM */ ++ ixgbe_release_eeprom(hw); ++ } ++ ++out: ++ return status; + } + + /** +@@ -572,12 +785,9 @@ + static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) + { + s32 status = IXGBE_ERR_EEPROM; +- u32 timeout; ++ u32 timeout = 2000; + u32 i; + u32 swsm; +- +- /* Set timeout value based on size of EEPROM */ +- timeout = hw->eeprom.word_size + 1; + + /* Get SMBI software semaphore between device drivers first */ + for (i = 0; i < timeout; i++) { +@@ -590,7 +800,7 @@ + status = 0; + break; + } +- msleep(1); ++ udelay(50); + } + + /* Now get the semaphore between SW/FW through the SWESMBI bit */ +@@ -618,11 +828,14 @@ + * was not granted because we don't have access to the EEPROM + */ + if (i >= timeout) { +- hw_dbg(hw, "Driver can't access the Eeprom - Semaphore " +- "not granted.\n"); ++ hw_dbg(hw, "SWESMBI Software EEPROM semaphore " ++ "not granted.\n"); + ixgbe_release_eeprom_semaphore(hw); + status = IXGBE_ERR_EEPROM; + } ++ } else { ++ hw_dbg(hw, "Software semaphore SMBI between device drivers " ++ "not granted.\n"); + } + + return status; +@@ -855,6 +1068,9 @@ + IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); + + ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ++ ++ /* Delay before attempt to obtain semaphore again to allow FW access */ ++ msleep(hw->eeprom.semaphore_delay); + } + + /** +@@ -964,7 +1180,7 @@ + if (status == 0) { + checksum = ixgbe_calc_eeprom_checksum(hw); + status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, +- checksum); ++ checksum); + } else { + hw_dbg(hw, "EEPROM read failed\n"); + } +@@ -983,16 +1199,19 @@ + s32 status = 0; + + /* Make sure it is not a multicast address */ +- if (IXGBE_IS_MULTICAST(mac_addr)) ++ if (IXGBE_IS_MULTICAST(mac_addr)) { ++ hw_dbg(hw, "MAC address is multicast\n"); + status = IXGBE_ERR_INVALID_MAC_ADDR; + /* Not a broadcast address */ +- else if (IXGBE_IS_BROADCAST(mac_addr)) ++ } else if (IXGBE_IS_BROADCAST(mac_addr)) { ++ hw_dbg(hw, "MAC address is broadcast\n"); + status = IXGBE_ERR_INVALID_MAC_ADDR; + /* Reject the zero address */ +- else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && +- mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) ++ } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && ++ mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { ++ hw_dbg(hw, "MAC address is all zeros\n"); + status = IXGBE_ERR_INVALID_MAC_ADDR; +- ++ } + return status; + } + +@@ -1081,38 +1300,6 @@ + } + + /** +- * ixgbe_enable_rar - Enable Rx address register +- * @hw: pointer to hardware structure +- * @index: index into the RAR table +- * +- * Enables the select receive address register. +- **/ +-static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index) +-{ +- u32 rar_high; +- +- rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); +- rar_high |= IXGBE_RAH_AV; +- IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); +-} +- +-/** +- * ixgbe_disable_rar - Disable Rx address register +- * @hw: pointer to hardware structure +- * @index: index into the RAR table +- * +- * Disables the select receive address register. +- **/ +-static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index) +-{ +- u32 rar_high; +- +- rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); +- rar_high &= (~IXGBE_RAH_AV); +- IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); +-} +- +-/** + * ixgbe_init_rx_addrs_generic - Initializes receive address filters. + * @hw: pointer to hardware structure + * +@@ -1136,18 +1323,18 @@ + hw->mac.ops.get_mac_addr(hw, hw->mac.addr); + + hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ", +- hw->mac.addr[0], hw->mac.addr[1], +- hw->mac.addr[2]); ++ hw->mac.addr[0], hw->mac.addr[1], ++ hw->mac.addr[2]); + hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], +- hw->mac.addr[4], hw->mac.addr[5]); ++ hw->mac.addr[4], hw->mac.addr[5]); + } else { + /* Setup the receive address. */ + hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); + hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ", +- hw->mac.addr[0], hw->mac.addr[1], +- hw->mac.addr[2]); ++ hw->mac.addr[0], hw->mac.addr[1], ++ hw->mac.addr[2]); + hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], +- hw->mac.addr[4], hw->mac.addr[5]); ++ hw->mac.addr[4], hw->mac.addr[5]); + + hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); + } +@@ -1163,7 +1350,6 @@ + } + + /* Clear the MTA */ +- hw->addr_ctrl.mc_addr_in_rar_count = 0; + hw->addr_ctrl.mta_in_use = 0; + IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); + +@@ -1171,8 +1357,7 @@ + for (i = 0; i < hw->mac.mcft_size; i++) + IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); + +- if (hw->mac.ops.init_uta_tables) +- hw->mac.ops.init_uta_tables(hw); ++ ixgbe_init_uta_tables(hw); + + return 0; + } +@@ -1184,7 +1369,7 @@ + * + * Adds it to unused receive address register or goes into promiscuous mode. + **/ +-static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) ++void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) + { + u32 rar_entries = hw->mac.num_rar_entries; + u32 rar; +@@ -1197,8 +1382,7 @@ + * else put the controller into promiscuous mode + */ + if (hw->addr_ctrl.rar_used_count < rar_entries) { +- rar = hw->addr_ctrl.rar_used_count - +- hw->addr_ctrl.mc_addr_in_rar_count; ++ rar = hw->addr_ctrl.rar_used_count; + hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); + hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar); + hw->addr_ctrl.rar_used_count++; +@@ -1224,7 +1408,7 @@ + * manually putting the device into promiscuous mode. + **/ + s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, +- u32 addr_count, ixgbe_mc_addr_itr next) ++ u32 addr_count, ixgbe_mc_addr_itr next) + { + u8 *addr; + u32 i; +@@ -1237,14 +1421,13 @@ + * Clear accounting of old secondary address list, + * don't count RAR[0] + */ +- uc_addr_in_use = hw->addr_ctrl.rar_used_count - +- hw->addr_ctrl.mc_addr_in_rar_count - 1; ++ uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; + hw->addr_ctrl.rar_used_count -= uc_addr_in_use; + hw->addr_ctrl.overflow_promisc = 0; + + /* Zero out the other receive addresses */ +- hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use); +- for (i = 1; i <= uc_addr_in_use; i++) { ++ hw_dbg(hw, "Clearing RAR[1-%d]\n", hw->addr_ctrl.rar_used_count); ++ for (i = 1; i <= hw->addr_ctrl.rar_used_count; i++) { + IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); + IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); + } +@@ -1324,7 +1507,7 @@ + * + * Sets the bit-vector in the multicast table. + **/ +-static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) ++void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) + { + u32 vector; + u32 vector_bit; +@@ -1353,40 +1536,6 @@ + } + + /** +- * ixgbe_add_mc_addr - Adds a multicast address. +- * @hw: pointer to hardware structure +- * @mc_addr: new multicast address +- * +- * Adds it to unused receive address register or to the multicast table. +- **/ +-static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr) +-{ +- u32 rar_entries = hw->mac.num_rar_entries; +- u32 rar; +- +- hw_dbg(hw, " MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n", +- mc_addr[0], mc_addr[1], mc_addr[2], +- mc_addr[3], mc_addr[4], mc_addr[5]); +- +- /* +- * Place this multicast address in the RAR if there is room, +- * else put it in the MTA +- */ +- if (hw->addr_ctrl.rar_used_count < rar_entries) { +- /* use RAR from the end up for multicast */ +- rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1; +- hw->mac.ops.set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV); +- hw_dbg(hw, "Added a multicast address to RAR[%d]\n", rar); +- hw->addr_ctrl.rar_used_count++; +- hw->addr_ctrl.mc_addr_in_rar_count++; +- } else { +- ixgbe_set_mta(hw, mc_addr); +- } +- +- hw_dbg(hw, "ixgbe_add_mc_addr Complete\n"); +-} +- +-/** + * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses + * @hw: pointer to hardware structure + * @mc_addr_list: the list of new multicast addresses +@@ -1402,7 +1551,6 @@ + u32 mc_addr_count, ixgbe_mc_addr_itr next) + { + u32 i; +- u32 rar_entries = hw->mac.num_rar_entries; + u32 vmdq; + + /* +@@ -1410,17 +1558,7 @@ + * use. + */ + hw->addr_ctrl.num_mc_addrs = mc_addr_count; +- hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count; +- hw->addr_ctrl.mc_addr_in_rar_count = 0; + hw->addr_ctrl.mta_in_use = 0; +- +- /* Zero out the other receive addresses. */ +- hw_dbg(hw, "Clearing RAR[%d-%d]\n", hw->addr_ctrl.rar_used_count, +- rar_entries - 1); +- for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) { +- IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); +- IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); +- } + + /* Clear the MTA */ + hw_dbg(hw, " Clearing MTA\n"); +@@ -1430,7 +1568,7 @@ + /* Add the new addresses */ + for (i = 0; i < mc_addr_count; i++) { + hw_dbg(hw, " Adding the multicast addresses:\n"); +- ixgbe_add_mc_addr(hw, next(hw, &mc_addr_list, &vmdq)); ++ ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); + } + + /* Enable mta */ +@@ -1450,14 +1588,7 @@ + **/ + s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) + { +- u32 i; +- u32 rar_entries = hw->mac.num_rar_entries; + struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; +- +- if (a->mc_addr_in_rar_count > 0) +- for (i = (rar_entries - a->mc_addr_in_rar_count); +- i < rar_entries; i++) +- ixgbe_enable_rar(hw, i); + + if (a->mta_in_use > 0) + IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | +@@ -1474,19 +1605,368 @@ + **/ + s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) + { +- u32 i; +- u32 rar_entries = hw->mac.num_rar_entries; + struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; +- +- if (a->mc_addr_in_rar_count > 0) +- for (i = (rar_entries - a->mc_addr_in_rar_count); +- i < rar_entries; i++) +- ixgbe_disable_rar(hw, i); + + if (a->mta_in_use > 0) + IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); + + return 0; ++} ++ ++/** ++ * ixgbe_fc_enable_generic - Enable flow control ++ * @hw: pointer to hardware structure ++ * @packetbuf_num: packet buffer number (0-7) ++ * ++ * Enable flow control according to the current settings. ++ **/ ++s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) ++{ ++ s32 ret_val = 0; ++ u32 mflcn_reg, fccfg_reg; ++ u32 reg; ++ u32 rx_pba_size; ++ ++#ifdef CONFIG_DCB ++ if (hw->fc.requested_mode == ixgbe_fc_pfc) ++ goto out; ++ ++#endif /* CONFIG_DCB */ ++ /* Negotiate the fc mode to use */ ++ ret_val = ixgbe_fc_autoneg(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Disable any previous flow control settings */ ++ mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); ++ mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE); ++ ++ fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); ++ fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); ++ ++ /* ++ * The possible values of fc.current_mode are: ++ * 0: Flow control is completely disabled ++ * 1: Rx flow control is enabled (we can receive pause frames, ++ * but not send pause frames). ++ * 2: Tx flow control is enabled (we can send pause frames but ++ * we do not support receiving pause frames). ++ * 3: Both Rx and Tx flow control (symmetric) are enabled. ++#ifdef CONFIG_DCB ++ * 4: Priority Flow Control is enabled. ++#endif ++ * other: Invalid. ++ */ ++ switch (hw->fc.current_mode) { ++ case ixgbe_fc_none: ++ /* Flow control is disabled by software override or autoneg. ++ * The code below will actually disable it in the HW. ++ */ ++ break; ++ case ixgbe_fc_rx_pause: ++ /* ++ * Rx Flow control is enabled and Tx Flow control is ++ * disabled by software override. Since there really ++ * isn't a way to advertise that we are capable of RX ++ * Pause ONLY, we will advertise that we support both ++ * symmetric and asymmetric Rx PAUSE. Later, we will ++ * disable the adapter's ability to send PAUSE frames. ++ */ ++ mflcn_reg |= IXGBE_MFLCN_RFCE; ++ break; ++ case ixgbe_fc_tx_pause: ++ /* ++ * Tx Flow control is enabled, and Rx Flow control is ++ * disabled by software override. ++ */ ++ fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; ++ break; ++ case ixgbe_fc_full: ++ /* Flow control (both Rx and Tx) is enabled by SW override. */ ++ mflcn_reg |= IXGBE_MFLCN_RFCE; ++ fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; ++ break; ++#ifdef CONFIG_DCB ++ case ixgbe_fc_pfc: ++ goto out; ++ break; ++#endif /* CONFIG_DCB */ ++ default: ++ hw_dbg(hw, "Flow control param set incorrectly\n"); ++ ret_val = -IXGBE_ERR_CONFIG; ++ goto out; ++ break; ++ } ++ ++ /* Set 802.3x based flow control settings. */ ++ mflcn_reg |= IXGBE_MFLCN_DPF; ++ IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); ++ IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); ++ ++ reg = IXGBE_READ_REG(hw, IXGBE_MTQC); ++ /* Thresholds are different for link flow control when in DCB mode */ ++ if (reg & IXGBE_MTQC_RT_ENA) { ++ rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)); ++ ++ /* Always disable XON for LFC when in DCB mode */ ++ reg = (rx_pba_size >> 5) & 0xFFE0; ++ IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg); ++ ++ reg = (rx_pba_size >> 2) & 0xFFE0; ++ if (hw->fc.current_mode & ixgbe_fc_tx_pause) ++ reg |= IXGBE_FCRTH_FCEN; ++ IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg); ++ } else { ++ /* Set up and enable Rx high/low water mark thresholds, ++ * enable XON. */ ++ if (hw->fc.current_mode & ixgbe_fc_tx_pause) { ++ if (hw->fc.send_xon) { ++ IXGBE_WRITE_REG(hw, ++ IXGBE_FCRTL_82599(packetbuf_num), ++ (hw->fc.low_water | ++ IXGBE_FCRTL_XONE)); ++ } else { ++ IXGBE_WRITE_REG(hw, ++ IXGBE_FCRTL_82599(packetbuf_num), ++ hw->fc.low_water); ++ } ++ ++ IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), ++ (hw->fc.high_water | IXGBE_FCRTH_FCEN)); ++ } ++ } ++ ++ /* Configure pause time (2 TCs per register) */ ++ reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); ++ if ((packetbuf_num & 1) == 0) ++ reg = (reg & 0xFFFF0000) | hw->fc.pause_time; ++ else ++ reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); ++ IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); ++ ++ IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * ixgbe_fc_autoneg - Configure flow control ++ * @hw: pointer to hardware structure ++ * ++ * Compares our advertised flow control capabilities to those advertised by ++ * our link partner, and determines the proper flow control mode to use. ++ **/ ++s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw) ++{ ++ s32 ret_val = 0; ++ ixgbe_link_speed speed; ++ u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; ++ bool link_up; ++ ++ /* ++ * AN should have completed when the cable was plugged in. ++ * Look for reasons to bail out. Bail out if: ++ * - FC autoneg is disabled, or if ++ * - we don't have multispeed fiber, or if ++ * - we're not running at 1G, or if ++ * - link is not up, or if ++ * - link is up but AN did not complete, or if ++ * - link is up and AN completed but timed out ++ * ++ * Since we're being called from an LSC, link is already know to be up. ++ * So use link_up_wait_to_complete=false. ++ */ ++ hw->mac.ops.check_link(hw, &speed, &link_up, false); ++ linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); ++ ++ if (hw->fc.disable_fc_autoneg || ++ !hw->phy.multispeed_fiber || ++ (speed != IXGBE_LINK_SPEED_1GB_FULL) || ++ !link_up || ++ ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || ++ ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { ++ hw->fc.fc_was_autonegged = false; ++ hw->fc.current_mode = hw->fc.requested_mode; ++ hw_dbg(hw, "Autoneg FC was skipped.\n"); ++ goto out; ++ } ++ ++ /* ++ * Read the AN advertisement and LP ability registers and resolve ++ * local flow control settings accordingly ++ */ ++ pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); ++ pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); ++ if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && ++ (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { ++ /* ++ * Now we need to check if the user selected Rx ONLY ++ * of pause frames. In this case, we had to advertise ++ * FULL flow control because we could not advertise RX ++ * ONLY. Hence, we must now check to see if we need to ++ * turn OFF the TRANSMISSION of PAUSE frames. ++ */ ++ if (hw->fc.requested_mode == ixgbe_fc_full) { ++ hw->fc.current_mode = ixgbe_fc_full; ++ hw_dbg(hw, "Flow Control = FULL.\n"); ++ } else { ++ hw->fc.current_mode = ixgbe_fc_rx_pause; ++ hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); ++ } ++ } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && ++ (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && ++ (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && ++ (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { ++ hw->fc.current_mode = ixgbe_fc_tx_pause; ++ hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); ++ } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && ++ (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && ++ !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && ++ (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { ++ hw->fc.current_mode = ixgbe_fc_rx_pause; ++ hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); ++ } else { ++ hw->fc.current_mode = ixgbe_fc_none; ++ hw_dbg(hw, "Flow Control = NONE.\n"); ++ } ++ ++ /* Record that current_mode is the result of a successful autoneg */ ++ hw->fc.fc_was_autonegged = true; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * ixgbe_setup_fc - Set up flow control ++ * @hw: pointer to hardware structure ++ * ++ * Called at init time to set up flow control. ++ **/ ++s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) ++{ ++ s32 ret_val = 0; ++ u32 reg; ++ ++#ifdef CONFIG_DCB ++ if (hw->fc.requested_mode == ixgbe_fc_pfc) { ++ hw->fc.current_mode = hw->fc.requested_mode; ++ goto out; ++ } ++ ++#endif /* CONFIG_DCB */ ++ ++ /* Validate the packetbuf configuration */ ++ if (packetbuf_num < 0 || packetbuf_num > 7) { ++ hw_dbg(hw, "Invalid packet buffer number [%d], expected range is" ++ " 0-7\n", packetbuf_num); ++ ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; ++ goto out; ++ } ++ ++ /* ++ * Validate the water mark configuration. Zero water marks are invalid ++ * because it causes the controller to just blast out fc packets. ++ */ ++ if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { ++ hw_dbg(hw, "Invalid water mark configuration\n"); ++ ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; ++ goto out; ++ } ++ ++ /* ++ * Validate the requested mode. Strict IEEE mode does not allow ++ * ixgbe_fc_rx_pause because it will cause us to fail at UNH. ++ */ ++ if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { ++ hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); ++ ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; ++ goto out; ++ } ++ ++ /* ++ * 10gig parts do not have a word in the EEPROM to determine the ++ * default flow control setting, so we explicitly set it to full. ++ */ ++ if (hw->fc.requested_mode == ixgbe_fc_default) ++ hw->fc.requested_mode = ixgbe_fc_full; ++ ++ /* ++ * Set up the 1G flow control advertisement registers so the HW will be ++ * able to do fc autoneg once the cable is plugged in. If we end up ++ * using 10g instead, this is harmless. ++ */ ++ reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); ++ ++ /* ++ * The possible values of fc.requested_mode are: ++ * 0: Flow control is completely disabled ++ * 1: Rx flow control is enabled (we can receive pause frames, ++ * but not send pause frames). ++ * 2: Tx flow control is enabled (we can send pause frames but ++ * we do not support receiving pause frames). ++ * 3: Both Rx and Tx flow control (symmetric) are enabled. ++#ifdef CONFIG_DCB ++ * 4: Priority Flow Control is enabled. ++#endif ++ * other: Invalid. ++ */ ++ switch (hw->fc.requested_mode) { ++ case ixgbe_fc_none: ++ /* Flow control completely disabled by software override. */ ++ reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); ++ break; ++ case ixgbe_fc_rx_pause: ++ /* ++ * Rx Flow control is enabled and Tx Flow control is ++ * disabled by software override. Since there really ++ * isn't a way to advertise that we are capable of RX ++ * Pause ONLY, we will advertise that we support both ++ * symmetric and asymmetric Rx PAUSE. Later, we will ++ * disable the adapter's ability to send PAUSE frames. ++ */ ++ reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); ++ break; ++ case ixgbe_fc_tx_pause: ++ /* ++ * Tx Flow control is enabled, and Rx Flow control is ++ * disabled by software override. ++ */ ++ reg |= (IXGBE_PCS1GANA_ASM_PAUSE); ++ reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); ++ break; ++ case ixgbe_fc_full: ++ /* Flow control (both Rx and Tx) is enabled by SW override. */ ++ reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); ++ break; ++#ifdef CONFIG_DCB ++ case ixgbe_fc_pfc: ++ goto out; ++ break; ++#endif /* CONFIG_DCB */ ++ default: ++ hw_dbg(hw, "Flow control param set incorrectly\n"); ++ ret_val = -IXGBE_ERR_CONFIG; ++ goto out; ++ break; ++ } ++ ++ IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); ++ reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); ++ ++ /* Enable and restart autoneg to inform the link partner */ ++ reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART; ++ ++ /* Disable AN timeout */ ++ if (hw->fc.strict_ieee) ++ reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; ++ ++ IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); ++ hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); ++ ++out: ++ return ret_val; + } + + /** +@@ -1547,6 +2027,10 @@ + s32 timeout = 200; + + while (timeout) { ++ /* ++ * SW EEPROM semaphore bit is used for access to all ++ * SW_FW_SYNC/GSSR bits (not just EEPROM) ++ */ + if (ixgbe_get_eeprom_semaphore(hw)) + return -IXGBE_ERR_SWFW_SYNC; + +@@ -1564,7 +2048,7 @@ + } + + if (!timeout) { +- hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); ++ hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n"); + return -IXGBE_ERR_SWFW_SYNC; + } + +@@ -1597,3 +2081,74 @@ + ixgbe_release_eeprom_semaphore(hw); + } + ++/** ++ * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit ++ * @hw: pointer to hardware structure ++ * @regval: register value to write to RXCTRL ++ * ++ * Enables the Rx DMA unit ++ **/ ++s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) ++{ ++ IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_blink_led_start_generic - Blink LED based on index. ++ * @hw: pointer to hardware structure ++ * @index: led number to blink ++ **/ ++s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) ++{ ++ ixgbe_link_speed speed = 0; ++ bool link_up = 0; ++ u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); ++ u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); ++ ++ /* ++ * Link must be up to auto-blink the LEDs; ++ * Force it if link is down. ++ */ ++ hw->mac.ops.check_link(hw, &speed, &link_up, false); ++ ++ if (!link_up) { ++ ++ autoc_reg |= IXGBE_AUTOC_AN_RESTART; ++ autoc_reg |= IXGBE_AUTOC_FLU; ++ IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); ++ msleep(10); ++ } ++ ++ led_reg &= ~IXGBE_LED_MODE_MASK(index); ++ led_reg |= IXGBE_LED_BLINK(index); ++ IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); ++ IXGBE_WRITE_FLUSH(hw); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. ++ * @hw: pointer to hardware structure ++ * @index: led number to stop blinking ++ **/ ++s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) ++{ ++ u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); ++ u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); ++ ++ autoc_reg &= ~IXGBE_AUTOC_FLU; ++ autoc_reg |= IXGBE_AUTOC_AN_RESTART; ++ IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); ++ ++ led_reg &= ~IXGBE_LED_MODE_MASK(index); ++ led_reg &= ~IXGBE_LED_BLINK(index); ++ led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); ++ IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); ++ IXGBE_WRITE_FLUSH(hw); ++ ++ return 0; ++} ++ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_common.h +--- a/drivers/net/ixgbe/ixgbe_common.h Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe_common.h Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -37,12 +37,14 @@ + s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num); + s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr); + s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw); ++void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw); + s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw); + + s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index); + s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index); + + s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw); ++s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data); + s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data); + s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, + u16 *data); +@@ -59,8 +61,14 @@ + ixgbe_mc_addr_itr func); + s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, + u32 addr_count, ixgbe_mc_addr_itr func); ++void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); + s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw); + s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw); ++s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval); ++ ++s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num); ++s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packtetbuf_num); ++s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw); + + s32 ixgbe_validate_mac_addr(u8 *mac_addr); + s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask); +@@ -69,28 +77,7 @@ + + s32 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val); + s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val); +- +-#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg))) +- +-#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg)) +- +-#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\ +- writel((value), ((a)->hw_addr + (reg) + ((offset) << 2)))) +- +-#define IXGBE_READ_REG_ARRAY(a, reg, offset) (\ +- readl((a)->hw_addr + (reg) + ((offset) << 2))) +- +-#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS) +- +-#ifdef DEBUG +-#define hw_dbg(hw, format, arg...) \ +-printk(KERN_DEBUG, "%s: " format, ixgbe_get_hw_dev_name(hw), ##arg); +-#else +-static inline int __attribute__ ((format (printf, 2, 3))) +-hw_dbg(struct ixgbe_hw *hw, const char *format, ...) +-{ +- return 0; +-} +-#endif ++s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index); ++s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index); + + #endif /* IXGBE_COMMON */ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_dcb.c +--- a/drivers/net/ixgbe/ixgbe_dcb.c Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe_dcb.c Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2007 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -20,17 +20,16 @@ + the file called "COPYING". + + Contact Information: +- Linux NICS + e1000-devel Mailing List + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + + *******************************************************************************/ + + +-#include "ixgbe.h" + #include "ixgbe_type.h" + #include "ixgbe_dcb.h" + #include "ixgbe_dcb_82598.h" ++#include "ixgbe_dcb_82599.h" + + /** + * ixgbe_dcb_config - Struct containing DCB settings. +@@ -108,7 +107,7 @@ + goto err_config; + } + } else if (bw_sum[i][j] != BW_PERCENT && +- bw_sum[i][j] != 0) { ++ bw_sum[i][j] != 0) { + ret_val = DCB_ERR_TC_BW; + goto err_config; + } +@@ -120,7 +119,12 @@ + } + } + ++ return DCB_SUCCESS; ++ + err_config: ++ hw_dbg(hw, "DCB error code %d while checking %s settings.\n", ++ ret_val, (j == DCB_TX_CONFIG) ? "Tx" : "Rx"); ++ + return ret_val; + } + +@@ -134,7 +138,7 @@ + * ixgbe_dcb_check_config(). + */ + s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *dcb_config, +- u8 direction) ++ u8 direction) + { + struct tc_bw_alloc *p; + s32 ret_val = 0; +@@ -186,12 +190,11 @@ + * credit may not be enough to send out a TSO + * packet in descriptor plane arbitration. + */ +- if (credit_max && +- (credit_max < MINIMUM_CREDIT_FOR_TSO)) ++ if (credit_max && (credit_max < MINIMUM_CREDIT_FOR_TSO)) + credit_max = MINIMUM_CREDIT_FOR_TSO; + + dcb_config->tc_config[i].desc_credits_max = +- (u16)credit_max; ++ (u16)credit_max; + } + + p->data_credits_max = (u16)credit_max; +@@ -210,28 +213,32 @@ + * This function returns the status data for each of the Traffic Classes in use. + */ + s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, +- u8 tc_count) ++ u8 tc_count) + { + s32 ret = 0; + if (hw->mac.type == ixgbe_mac_82598EB) + ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count); ++ else if (hw->mac.type == ixgbe_mac_82599EB) ++ ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count); + return ret; + } + + /** + * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class +- * hw - pointer to hardware structure +- * stats - pointer to statistics structure +- * tc_count - Number of elements in bwg_array. ++ * @hw: pointer to hardware structure ++ * @stats: pointer to statistics structure ++ * @tc_count: Number of elements in bwg_array. + * + * This function returns the CBFC status data for each of the Traffic Classes. + */ + s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, +- u8 tc_count) ++ u8 tc_count) + { + s32 ret = 0; + if (hw->mac.type == ixgbe_mac_82598EB) + ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count); ++ else if (hw->mac.type == ixgbe_mac_82599EB) ++ ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count); + return ret; + } + +@@ -243,11 +250,13 @@ + * Configure Rx Data Arbiter and credits for each traffic class. + */ + s32 ixgbe_dcb_config_rx_arbiter(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config) ++ struct ixgbe_dcb_config *dcb_config) + { + s32 ret = 0; + if (hw->mac.type == ixgbe_mac_82598EB) + ret = ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config); ++ else if (hw->mac.type == ixgbe_mac_82599EB) ++ ret = ixgbe_dcb_config_rx_arbiter_82599(hw, dcb_config); + return ret; + } + +@@ -259,11 +268,13 @@ + * Configure Tx Descriptor Arbiter and credits for each traffic class. + */ + s32 ixgbe_dcb_config_tx_desc_arbiter(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config) ++ struct ixgbe_dcb_config *dcb_config) + { + s32 ret = 0; + if (hw->mac.type == ixgbe_mac_82598EB) + ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config); ++ else if (hw->mac.type == ixgbe_mac_82599EB) ++ ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, dcb_config); + return ret; + } + +@@ -275,11 +286,13 @@ + * Configure Tx Data Arbiter and credits for each traffic class. + */ + s32 ixgbe_dcb_config_tx_data_arbiter(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config) ++ struct ixgbe_dcb_config *dcb_config) + { + s32 ret = 0; + if (hw->mac.type == ixgbe_mac_82598EB) + ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, dcb_config); ++ else if (hw->mac.type == ixgbe_mac_82599EB) ++ ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, dcb_config); + return ret; + } + +@@ -291,11 +304,13 @@ + * Configure Priority Flow Control for each traffic class. + */ + s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config) ++ struct ixgbe_dcb_config *dcb_config) + { + s32 ret = 0; + if (hw->mac.type == ixgbe_mac_82598EB) + ret = ixgbe_dcb_config_pfc_82598(hw, dcb_config); ++ else if (hw->mac.type == ixgbe_mac_82599EB) ++ ret = ixgbe_dcb_config_pfc_82599(hw, dcb_config); + return ret; + } + +@@ -311,6 +326,8 @@ + s32 ret = 0; + if (hw->mac.type == ixgbe_mac_82598EB) + ret = ixgbe_dcb_config_tc_stats_82598(hw); ++ else if (hw->mac.type == ixgbe_mac_82599EB) ++ ret = ixgbe_dcb_config_tc_stats_82599(hw); + return ret; + } + +@@ -322,11 +339,12 @@ + * Configure dcb settings and enable dcb mode. + */ + s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config) ++ struct ixgbe_dcb_config *dcb_config) + { + s32 ret = 0; + if (hw->mac.type == ixgbe_mac_82598EB) + ret = ixgbe_dcb_hw_config_82598(hw, dcb_config); ++ else if (hw->mac.type == ixgbe_mac_82599EB) ++ ret = ixgbe_dcb_hw_config_82599(hw, dcb_config); + return ret; + } +- +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_dcb.h +--- a/drivers/net/ixgbe/ixgbe_dcb.h Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe_dcb.h Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2007 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -20,7 +20,6 @@ + the file called "COPYING". + + Contact Information: +- Linux NICS + e1000-devel Mailing List + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + +@@ -75,15 +74,35 @@ + prio_link + }; + ++/* DCB capability definitions */ ++#define IXGBE_DCB_PG_SUPPORT 0x00000001 ++#define IXGBE_DCB_PFC_SUPPORT 0x00000002 ++#define IXGBE_DCB_BCN_SUPPORT 0x00000004 ++#define IXGBE_DCB_UP2TC_SUPPORT 0x00000008 ++#define IXGBE_DCB_GSP_SUPPORT 0x00000010 ++ ++#define IXGBE_DCB_8_TC_SUPPORT 0x80 ++ ++struct dcb_support { ++ /* DCB capabilities */ ++ u32 capabilities; ++ ++ /* Each bit represents a number of TCs configurable in the hw. ++ * If 8 traffic classes can be configured, the value is 0x80. ++ */ ++ u8 traffic_classes; ++ u8 pfc_traffic_classes; ++}; ++ + /* Traffic class bandwidth allocation per direction */ + struct tc_bw_alloc { +- u8 bwg_id; /* Bandwidth Group (BWG) ID */ +- u8 bwg_percent; /* % of BWG's bandwidth */ +- u8 link_percent; /* % of link bandwidth */ +- u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */ ++ u8 bwg_id; /* Bandwidth Group (BWG) ID */ ++ u8 bwg_percent; /* % of BWG's bandwidth */ ++ u8 link_percent; /* % of link bandwidth */ ++ u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */ + u16 data_credits_refill; /* Credit refill amount in 64B granularity */ +- u16 data_credits_max; /* Max credits for a configured packet buffer +- * in 64B granularity.*/ ++ u16 data_credits_max; /* Max credits for a configured packet buffer ++ * in 64B granularity.*/ + enum strict_prio_type prio_type; /* Link or Group Strict Priority */ + }; + +@@ -108,37 +127,17 @@ + pba_80_48 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */ + }; + +-/* +- * This structure contains many values encoded as fixed-point +- * numbers, meaning that some of bits are dedicated to the +- * magnitude and others to the fraction part. In the comments +- * this is shown as f=n, where n is the number of fraction bits. +- * These fraction bits are always the low-order bits. The size +- * of the magnitude is not specified. +- */ +-struct bcn_config { +- u32 rp_admin_mode[MAX_TRAFFIC_CLASS]; /* BCN enabled, per TC */ +- u32 bcna_option[2]; /* BCNA Port + MAC Addr */ +- u32 rp_w; /* Derivative Weight, f=3 */ +- u32 rp_gi; /* Increase Gain, f=12 */ +- u32 rp_gd; /* Decrease Gain, f=12 */ +- u32 rp_ru; /* Rate Unit */ +- u32 rp_alpha; /* Max Decrease Factor, f=12 */ +- u32 rp_beta; /* Max Increase Factor, f=12 */ +- u32 rp_ri; /* Initial Rate */ +- u32 rp_td; /* Drift Interval Timer */ +- u32 rp_rd; /* Drift Increase */ +- u32 rp_tmax; /* Severe Congestion Backoff Timer Range */ +- u32 rp_rmin; /* Severe Congestion Restart Rate */ +- u32 rp_wrtt; /* RTT Moving Average Weight */ ++struct dcb_num_tcs { ++ u8 pg_tcs; ++ u8 pfc_tcs; + }; + + struct ixgbe_dcb_config { +- struct bcn_config bcn; +- + struct tc_configuration tc_config[MAX_TRAFFIC_CLASS]; ++ struct dcb_support support; ++ struct dcb_num_tcs num_tcs; + u8 bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */ +- ++ bool pfc_mode_enable; + bool round_robin_enable; + + enum dcb_rx_pba_cfg rx_pba_cfg; +@@ -154,36 +153,41 @@ + + /* DCB credits calculation */ + s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *config, +- u8 direction); ++ u8 direction); + + /* DCB PFC functions */ + s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config); ++ struct ixgbe_dcb_config *dcb_config); + s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, +- u8 tc_count); ++ u8 tc_count); + + /* DCB traffic class stats */ + s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *); + s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, +- u8 tc_count); ++ u8 tc_count); + + /* DCB config arbiters */ + s32 ixgbe_dcb_config_tx_desc_arbiter(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config); ++ struct ixgbe_dcb_config *dcb_config); + s32 ixgbe_dcb_config_tx_data_arbiter(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config); ++ struct ixgbe_dcb_config *dcb_config); + s32 ixgbe_dcb_config_rx_arbiter(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config); ++ struct ixgbe_dcb_config *dcb_config); + + /* DCB hw initialization */ + s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, struct ixgbe_dcb_config *config); + ++ + /* DCB definitions for credit calculation */ + #define MAX_CREDIT_REFILL 511 /* 0x1FF * 64B = 32704B */ + #define MINIMUM_CREDIT_REFILL 5 /* 5*64B = 320B */ +-#define MINIMUM_CREDIT_FOR_JUMBO 145 /* 145= UpperBound((9*1024+54)/64B) for 9KB jumbo frame */ +-#define DCB_MAX_TSO_SIZE (32*1024) /* MAX TSO packet size supported in DCB mode */ +-#define MINIMUM_CREDIT_FOR_TSO (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */ +-#define MAX_CREDIT 4095 /* Maximum credit supported: 256KB * 1204 / 64B */ ++#define MINIMUM_CREDIT_FOR_JUMBO 145 /* 145 = UpperBound((9*1024+54)/64B) ++ * for 9KB jumbo frame */ ++#define DCB_MAX_TSO_SIZE 32*1024 /* MAX TSO packet size supported ++ * in DCB mode */ ++#define MINIMUM_CREDIT_FOR_TSO (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO ++ * packet */ ++#define MAX_CREDIT 4095 /* Maximum credit supported: ++ * 256KB * 1204 / 64B */ + + #endif /* _DCB_CONFIG_H */ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_dcb_82598.c +--- a/drivers/net/ixgbe/ixgbe_dcb_82598.c Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe_dcb_82598.c Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2007 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -20,13 +20,12 @@ + the file called "COPYING". + + Contact Information: +- Linux NICS + e1000-devel Mailing List + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + + *******************************************************************************/ + +-#include "ixgbe.h" ++ + #include "ixgbe_type.h" + #include "ixgbe_dcb.h" + #include "ixgbe_dcb_82598.h" +@@ -40,14 +39,13 @@ + * This function returns the status data for each of the Traffic Classes in use. + */ + s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw, +- struct ixgbe_hw_stats *stats, +- u8 tc_count) ++ struct ixgbe_hw_stats *stats, ++ u8 tc_count) + { + int tc; + + if (tc_count > MAX_TRAFFIC_CLASS) + return DCB_ERR_PARAM; +- + /* Statistics pertaining to each traffic class */ + for (tc = 0; tc < tc_count; tc++) { + /* Transmitted Packets */ +@@ -58,6 +56,14 @@ + stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc)); + /* Received Bytes */ + stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc)); ++ ++#if 0 ++ /* Can we get rid of these?? Consequently, getting rid ++ * of the tc_stats structure. ++ */ ++ tc_stats_array[up]->in_overflow_discards = 0; ++ tc_stats_array[up]->out_overflow_discards = 0; ++#endif + } + + return 0; +@@ -72,14 +78,13 @@ + * This function returns the CBFC status data for each of the Traffic Classes. + */ + s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw, +- struct ixgbe_hw_stats *stats, +- u8 tc_count) ++ struct ixgbe_hw_stats *stats, ++ u8 tc_count) + { + int tc; + + if (tc_count > MAX_TRAFFIC_CLASS) + return DCB_ERR_PARAM; +- + for (tc = 0; tc < tc_count; tc++) { + /* Priority XOFF Transmitted */ + stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc)); +@@ -98,7 +103,7 @@ + * Configure packet buffers for DCB mode. + */ + s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config) ++ struct ixgbe_dcb_config *dcb_config) + { + s32 ret_val = 0; + u32 value = IXGBE_RXPBSIZE_64KB; +@@ -122,7 +127,7 @@ + /* Setup Tx packet buffer sizes */ + for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { + IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), +- IXGBE_TXPBSIZE_40KB); ++ IXGBE_TXPBSIZE_40KB); + } + break; + } +@@ -138,7 +143,7 @@ + * Configure Rx Data Arbiter and credits for each traffic class. + */ + s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config) ++ struct ixgbe_dcb_config *dcb_config) + { + struct tc_bw_alloc *p; + u32 reg = 0; +@@ -195,7 +200,7 @@ + * Configure Tx Descriptor Arbiter and credits for each traffic class. + */ + s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config) ++ struct ixgbe_dcb_config *dcb_config) + { + struct tc_bw_alloc *p; + u32 reg, max_credits; +@@ -243,7 +248,7 @@ + * Configure Tx Data Arbiter and credits for each traffic class. + */ + s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config) ++ struct ixgbe_dcb_config *dcb_config) + { + struct tc_bw_alloc *p; + u32 reg; +@@ -289,16 +294,18 @@ + * Configure Priority Flow Control for each traffic class. + */ + s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config) ++ struct ixgbe_dcb_config *dcb_config) + { + u32 reg, rx_pba_size; + u8 i; ++ ++ if (!dcb_config->pfc_mode_enable) ++ goto out; + + /* Enable Transmit Priority Flow Control */ + reg = IXGBE_READ_REG(hw, IXGBE_RMCS); + reg &= ~IXGBE_RMCS_TFCE_802_3X; + /* correct the reporting of our flow control status */ +- hw->fc.type = ixgbe_fc_none; + reg |= IXGBE_RMCS_TFCE_PRIORITY; + IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); + +@@ -317,7 +324,7 @@ + rx_pba_size = IXGBE_RXPBSIZE_64KB; + } else { + rx_pba_size = (i < 4) ? IXGBE_RXPBSIZE_80KB +- : IXGBE_RXPBSIZE_48KB; ++ : IXGBE_RXPBSIZE_48KB; + } + + reg = ((rx_pba_size >> 5) & 0xFFF0); +@@ -342,6 +349,7 @@ + /* Configure flow control refresh threshold value */ + IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400); + ++out: + return 0; + } + +@@ -367,7 +375,7 @@ + reg |= ((0x1010101) * j); + IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); + } +- /* Transmit Queues stats setting - 4 queues per statistics reg */ ++ /* Transmit Queues stats setting - 4 queues per statistics reg*/ + for (i = 0; i < 8; i++) { + reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); + reg |= ((0x1010101) * i); +@@ -385,8 +393,9 @@ + * Configure dcb settings and enable dcb mode. + */ + s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config) ++ struct ixgbe_dcb_config *dcb_config) + { ++ + ixgbe_dcb_config_packet_buffers_82598(hw, dcb_config); + ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config); + ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config); +@@ -394,5 +403,6 @@ + ixgbe_dcb_config_pfc_82598(hw, dcb_config); + ixgbe_dcb_config_tc_stats_82598(hw); + ++ + return 0; + } +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_dcb_82598.h +--- a/drivers/net/ixgbe/ixgbe_dcb_82598.h Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe_dcb_82598.h Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2007 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -20,7 +20,6 @@ + the file called "COPYING". + + Contact Information: +- Linux NICS + e1000-devel Mailing List + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + +@@ -32,7 +31,8 @@ + /* DCB register definitions */ + + #define IXGBE_DPMCS_MTSOS_SHIFT 16 +-#define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */ ++#define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, ++ * 1 DFP - Deficit Fixed Priority */ + #define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */ + #define IXGBE_DPMCS_ARBDIS 0x00000040 /* DCB arbiter disable */ + #define IXGBE_DPMCS_TSOEF 0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */ +@@ -42,8 +42,10 @@ + #define IXGBE_RT2CR_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ + #define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */ + +-#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet buffers enable */ +-#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores (RSS) enable */ ++#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet ++ * buffers enable */ ++#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores ++ * (RSS) enable */ + + #define IXGBE_TDTQ2TCCR_MCL_SHIFT 12 + #define IXGBE_TDTQ2TCCR_BWG_SHIFT 9 +@@ -55,7 +57,8 @@ + #define IXGBE_TDPT2TCCR_GSP 0x40000000 + #define IXGBE_TDPT2TCCR_LSP 0x80000000 + +-#define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */ ++#define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, ++ * 1 DFP - Deficit Fixed Priority */ + #define IXGBE_PDPMCS_ARBDIS 0x00000040 /* Arbiter disable */ + #define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */ + +@@ -66,33 +69,31 @@ + #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ + #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ + +-#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 +- + /* DCB hardware-specific driver APIs */ + + /* DCB PFC functions */ + s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config); ++ struct ixgbe_dcb_config *dcb_config); + s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw, +- struct ixgbe_hw_stats *stats, +- u8 tc_count); ++ struct ixgbe_hw_stats *stats, ++ u8 tc_count); + + /* DCB traffic class stats */ + s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw); + s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw, +- struct ixgbe_hw_stats *stats, +- u8 tc_count); ++ struct ixgbe_hw_stats *stats, ++ u8 tc_count); + + /* DCB config arbiters */ + s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config); ++ struct ixgbe_dcb_config *dcb_config); + s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config); ++ struct ixgbe_dcb_config *dcb_config); + s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *dcb_config); ++ struct ixgbe_dcb_config *dcb_config); + + /* DCB hw initialization */ + s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, +- struct ixgbe_dcb_config *config); ++ struct ixgbe_dcb_config *config); + + #endif /* _DCB_82598_CONFIG_H */ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_dcb_82599.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c Wed Aug 05 11:05:50 2009 +0100 +@@ -0,0 +1,501 @@ ++/******************************************************************************* ++ ++ Intel 10 Gigabit PCI Express Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++ ++#include "ixgbe_type.h" ++#include "ixgbe_dcb.h" ++#include "ixgbe_dcb_82599.h" ++ ++/** ++ * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class ++ * @hw: pointer to hardware structure ++ * @stats: pointer to statistics structure ++ * @tc_count: Number of elements in bwg_array. ++ * ++ * This function returns the status data for each of the Traffic Classes in use. ++ */ ++s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw, ++ struct ixgbe_hw_stats *stats, ++ u8 tc_count) ++{ ++ int tc; ++ ++ if (tc_count > MAX_TRAFFIC_CLASS) ++ return DCB_ERR_PARAM; ++ /* Statistics pertaining to each traffic class */ ++ for (tc = 0; tc < tc_count; tc++) { ++ /* Transmitted Packets */ ++ stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc)); ++ /* Transmitted Bytes */ ++ stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc)); ++ /* Received Packets */ ++ stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc)); ++ /* Received Bytes */ ++ stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc)); ++ ++#if 0 ++ /* Can we get rid of these?? Consequently, getting rid ++ * of the tc_stats structure. ++ */ ++ tc_stats_array[up]->in_overflow_discards = 0; ++ tc_stats_array[up]->out_overflow_discards = 0; ++#endif ++ } ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_dcb_get_pfc_stats_82599 - Return CBFC status data ++ * @hw: pointer to hardware structure ++ * @stats: pointer to statistics structure ++ * @tc_count: Number of elements in bwg_array. ++ * ++ * This function returns the CBFC status data for each of the Traffic Classes. ++ */ ++s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw, ++ struct ixgbe_hw_stats *stats, ++ u8 tc_count) ++{ ++ int tc; ++ ++ if (tc_count > MAX_TRAFFIC_CLASS) ++ return DCB_ERR_PARAM; ++ for (tc = 0; tc < tc_count; tc++) { ++ /* Priority XOFF Transmitted */ ++ stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc)); ++ /* Priority XOFF Received */ ++ stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(tc)); ++ } ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_dcb_config_packet_buffers_82599 - Configure DCB packet buffers ++ * @hw: pointer to hardware structure ++ * @dcb_config: pointer to ixgbe_dcb_config structure ++ * ++ * Configure packet buffers for DCB mode. ++ */ ++s32 ixgbe_dcb_config_packet_buffers_82599(struct ixgbe_hw *hw, ++ struct ixgbe_dcb_config *dcb_config) ++{ ++ s32 ret_val = 0; ++ u32 value = IXGBE_RXPBSIZE_64KB; ++ u8 i = 0; ++ ++ /* Setup Rx packet buffer sizes */ ++ switch (dcb_config->rx_pba_cfg) { ++ case pba_80_48: ++ /* Setup the first four at 80KB */ ++ value = IXGBE_RXPBSIZE_80KB; ++ for (; i < 4; i++) ++ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value); ++ /* Setup the last four at 48KB...don't re-init i */ ++ value = IXGBE_RXPBSIZE_48KB; ++ /* Fall Through */ ++ case pba_equal: ++ default: ++ for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) ++ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value); ++ ++ /* Setup Tx packet buffer sizes */ ++ for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { ++ IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), ++ IXGBE_TXPBSIZE_20KB); ++ IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), ++ IXGBE_TXPBTHRESH_DCB); ++ } ++ break; ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter ++ * @hw: pointer to hardware structure ++ * @dcb_config: pointer to ixgbe_dcb_config structure ++ * ++ * Configure Rx Packet Arbiter and credits for each traffic class. ++ */ ++s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, ++ struct ixgbe_dcb_config *dcb_config) ++{ ++ struct tc_bw_alloc *p; ++ u32 reg = 0; ++ u32 credit_refill = 0; ++ u32 credit_max = 0; ++ u8 i = 0; ++ ++ /* ++ * Disable the arbiter before changing parameters ++ * (always enable recycle mode; WSP) ++ */ ++ reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; ++ IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); ++ ++ /* Map all traffic classes to their UP, 1 to 1 */ ++ reg = 0; ++ for (i = 0; i < MAX_TRAFFIC_CLASS; i++) ++ reg |= (i << (i * IXGBE_RTRUP2TC_UP_SHIFT)); ++ IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); ++ ++ /* Configure traffic class credits and priority */ ++ for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { ++ p = &dcb_config->tc_config[i].path[DCB_RX_CONFIG]; ++ ++ credit_refill = p->data_credits_refill; ++ credit_max = p->data_credits_max; ++ reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); ++ ++ reg |= (u32)(p->bwg_id) << IXGBE_RTRPT4C_BWG_SHIFT; ++ ++ if (p->prio_type == prio_link) ++ reg |= IXGBE_RTRPT4C_LSP; ++ ++ IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); ++ } ++ ++ /* ++ * Configure Rx packet plane (recycle mode; WSP) and ++ * enable arbiter ++ */ ++ reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC; ++ IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter ++ * @hw: pointer to hardware structure ++ * @dcb_config: pointer to ixgbe_dcb_config structure ++ * ++ * Configure Tx Descriptor Arbiter and credits for each traffic class. ++ */ ++s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, ++ struct ixgbe_dcb_config *dcb_config) ++{ ++ struct tc_bw_alloc *p; ++ u32 reg, max_credits; ++ u8 i; ++ ++ /* Clear the per-Tx queue credits; we use per-TC instead */ ++ for (i = 0; i < 128; i++) { ++ IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); ++ IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0); ++ } ++ ++ /* Configure traffic class credits and priority */ ++ for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { ++ p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG]; ++ max_credits = dcb_config->tc_config[i].desc_credits_max; ++ reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT; ++ reg |= p->data_credits_refill; ++ reg |= (u32)(p->bwg_id) << IXGBE_RTTDT2C_BWG_SHIFT; ++ ++ if (p->prio_type == prio_group) ++ reg |= IXGBE_RTTDT2C_GSP; ++ ++ if (p->prio_type == prio_link) ++ reg |= IXGBE_RTTDT2C_LSP; ++ ++ IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg); ++ } ++ ++ /* ++ * Configure Tx descriptor plane (recycle mode; WSP) and ++ * enable arbiter ++ */ ++ reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM; ++ IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter ++ * @hw: pointer to hardware structure ++ * @dcb_config: pointer to ixgbe_dcb_config structure ++ * ++ * Configure Tx Packet Arbiter and credits for each traffic class. ++ */ ++s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, ++ struct ixgbe_dcb_config *dcb_config) ++{ ++ struct tc_bw_alloc *p; ++ u32 reg; ++ u8 i; ++ ++ /* ++ * Disable the arbiter before changing parameters ++ * (always enable recycle mode; SP; arb delay) ++ */ ++ reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | ++ (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) | ++ IXGBE_RTTPCS_ARBDIS; ++ IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); ++ ++ /* Map all traffic classes to their UP, 1 to 1 */ ++ reg = 0; ++ for (i = 0; i < MAX_TRAFFIC_CLASS; i++) ++ reg |= (i << (i * IXGBE_RTTUP2TC_UP_SHIFT)); ++ IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); ++ ++ /* Configure traffic class credits and priority */ ++ for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { ++ p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG]; ++ reg = p->data_credits_refill; ++ reg |= (u32)(p->data_credits_max) << IXGBE_RTTPT2C_MCL_SHIFT; ++ reg |= (u32)(p->bwg_id) << IXGBE_RTTPT2C_BWG_SHIFT; ++ ++ if (p->prio_type == prio_group) ++ reg |= IXGBE_RTTPT2C_GSP; ++ ++ if (p->prio_type == prio_link) ++ reg |= IXGBE_RTTPT2C_LSP; ++ ++ IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg); ++ } ++ ++ /* ++ * Configure Tx packet plane (recycle mode; SP; arb delay) and ++ * enable arbiter ++ */ ++ reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | ++ (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT); ++ IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_dcb_config_pfc_82599 - Configure priority flow control ++ * @hw: pointer to hardware structure ++ * @dcb_config: pointer to ixgbe_dcb_config structure ++ * ++ * Configure Priority Flow Control (PFC) for each traffic class. ++ */ ++s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, ++ struct ixgbe_dcb_config *dcb_config) ++{ ++ u32 i, reg, rx_pba_size; ++ ++ /* If PFC is disabled globally then fall back to LFC. */ ++ if (!dcb_config->pfc_mode_enable) { ++ for (i = 0; i < MAX_TRAFFIC_CLASS; i++) ++ hw->mac.ops.fc_enable(hw, i); ++ goto out; ++ } ++ ++ /* Configure PFC Tx thresholds per TC */ ++ for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { ++ if (dcb_config->rx_pba_cfg == pba_equal) ++ rx_pba_size = IXGBE_RXPBSIZE_64KB; ++ else ++ rx_pba_size = (i < 4) ? IXGBE_RXPBSIZE_80KB ++ : IXGBE_RXPBSIZE_48KB; ++ ++ reg = ((rx_pba_size >> 5) & 0xFFE0); ++ if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full || ++ dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx) ++ reg |= IXGBE_FCRTL_XONE; ++ IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg); ++ ++ reg = ((rx_pba_size >> 2) & 0xFFE0); ++ if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full || ++ dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx) ++ reg |= IXGBE_FCRTH_FCEN; ++ IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); ++ } ++ ++ /* Configure pause time (2 TCs per register) */ ++ reg = hw->fc.pause_time | (hw->fc.pause_time << 16); ++ for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) ++ IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); ++ ++ /* Configure flow control refresh threshold value */ ++ IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); ++ ++ /* Enable Transmit PFC */ ++ reg = IXGBE_FCCFG_TFCE_PRIORITY; ++ IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg); ++ ++ /* ++ * Enable Receive PFC ++ * We will always honor XOFF frames we receive when ++ * we are in PFC mode. ++ */ ++ reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); ++ reg &= ~IXGBE_MFLCN_RFCE; ++ reg |= IXGBE_MFLCN_RPFCE; ++ IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); ++out: ++ return 0; ++} ++ ++/** ++ * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics ++ * @hw: pointer to hardware structure ++ * ++ * Configure queue statistics registers, all queues belonging to same traffic ++ * class uses a single set of queue statistics counters. ++ */ ++s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw) ++{ ++ u32 reg = 0; ++ u8 i = 0; ++ ++ /* ++ * Receive Queues stats setting ++ * 32 RQSMR registers, each configuring 4 queues. ++ * Set all 16 queues of each TC to the same stat ++ * with TC 'n' going to stat 'n'. ++ */ ++ for (i = 0; i < 32; i++) { ++ reg = 0x01010101 * (i / 4); ++ IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); ++ } ++ /* ++ * Transmit Queues stats setting ++ * 32 TQSM registers, each controlling 4 queues. ++ * Set all queues of each TC to the same stat ++ * with TC 'n' going to stat 'n'. ++ * Tx queues are allocated non-uniformly to TCs: ++ * 32, 32, 16, 16, 8, 8, 8, 8. ++ */ ++ for (i = 0; i < 32; i++) { ++ if (i < 8) ++ reg = 0x00000000; ++ else if (i < 16) ++ reg = 0x01010101; ++ else if (i < 20) ++ reg = 0x02020202; ++ else if (i < 24) ++ reg = 0x03030303; ++ else if (i < 26) ++ reg = 0x04040404; ++ else if (i < 28) ++ reg = 0x05050505; ++ else if (i < 30) ++ reg = 0x06060606; ++ else ++ reg = 0x07070707; ++ IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg); ++ } ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_dcb_config_82599 - Configure general DCB parameters ++ * @hw: pointer to hardware structure ++ * @dcb_config: pointer to ixgbe_dcb_config structure ++ * ++ * Configure general DCB parameters. ++ */ ++s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw) ++{ ++ u32 reg; ++ u32 q; ++ ++ /* Disable the Tx desc arbiter so that MTQC can be changed */ ++ reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS); ++ reg |= IXGBE_RTTDCS_ARBDIS; ++ IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); ++ ++ /* Enable DCB for Rx with 8 TCs */ ++ reg = IXGBE_READ_REG(hw, IXGBE_MRQC); ++ switch (reg & IXGBE_MRQC_MRQE_MASK) { ++ case 0: ++ case IXGBE_MRQC_RT4TCEN: ++ /* RSS disabled cases */ ++ reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RT8TCEN; ++ break; ++ case IXGBE_MRQC_RSSEN: ++ case IXGBE_MRQC_RTRSS4TCEN: ++ /* RSS enabled cases */ ++ reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RTRSS8TCEN; ++ break; ++ default: ++ /* Unsupported value, assume stale data, overwrite no RSS */ ++ reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RT8TCEN; ++ } ++ IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg); ++ ++ /* Enable DCB for Tx with 8 TCs */ ++ reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; ++ IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg); ++ ++ /* Disable drop for all queues */ ++ for (q=0; q < 128; q++) { ++ IXGBE_WRITE_REG(hw, IXGBE_QDE, q << IXGBE_QDE_IDX_SHIFT); ++ } ++ ++ /* Enable the Tx desc arbiter */ ++ reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS); ++ reg &= ~IXGBE_RTTDCS_ARBDIS; ++ IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_dcb_hw_config_82599 - Configure and enable DCB ++ * @hw: pointer to hardware structure ++ * @dcb_config: pointer to ixgbe_dcb_config structure ++ * ++ * Configure dcb settings and enable dcb mode. ++ */ ++s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, ++ struct ixgbe_dcb_config *dcb_config) ++{ ++ u32 pap = 0; ++ ++ ixgbe_dcb_config_packet_buffers_82599(hw, dcb_config); ++ ixgbe_dcb_config_82599(hw); ++ ixgbe_dcb_config_rx_arbiter_82599(hw, dcb_config); ++ ixgbe_dcb_config_tx_desc_arbiter_82599(hw, dcb_config); ++ ixgbe_dcb_config_tx_data_arbiter_82599(hw, dcb_config); ++ ixgbe_dcb_config_pfc_82599(hw, dcb_config); ++ ixgbe_dcb_config_tc_stats_82599(hw); ++ ++ /* ++ * TODO: For DCB SV purpose only, ++ * remove it before product release ++ */ ++ if (dcb_config->link_speed > 0 && dcb_config->link_speed <= 9) { ++ pap = IXGBE_READ_REG(hw, IXGBE_PAP); ++ pap |= (dcb_config->link_speed << 16); ++ IXGBE_WRITE_REG(hw, IXGBE_PAP, pap); ++ } ++ ++ return 0; ++} ++ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_dcb_82599.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/ixgbe/ixgbe_dcb_82599.h Wed Aug 05 11:05:50 2009 +0100 +@@ -0,0 +1,125 @@ ++/******************************************************************************* ++ ++ Intel 10 Gigabit PCI Express Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _DCB_82599_CONFIG_H_ ++#define _DCB_82599_CONFIG_H_ ++ ++/* DCB register definitions */ ++#define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin, ++ * 1 WSP - Weighted Strict Priority ++ */ ++#define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin, ++ * 1 WRR - Weighted Round Robin ++ */ ++#define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */ ++#define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */ ++#define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must ++ * clear! ++ */ ++#define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */ ++ ++/* Receive UP2TC mapping */ ++#define IXGBE_RTRUP2TC_UP_SHIFT 3 ++/* Transmit UP2TC mapping */ ++#define IXGBE_RTTUP2TC_UP_SHIFT 3 ++ ++#define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ ++#define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */ ++#define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */ ++#define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */ ++ ++#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet ++ * buffers enable ++ */ ++#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores ++ * (RSS) enable ++ */ ++ ++/* RTRPCS Bit Masks */ ++#define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */ ++/* Receive Arbitration Control: 0 Round Robin, 1 DFP */ ++#define IXGBE_RTRPCS_RAC 0x00000004 ++#define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */ ++ ++/* RTTDT2C Bit Masks */ ++#define IXGBE_RTTDT2C_MCL_SHIFT 12 ++#define IXGBE_RTTDT2C_BWG_SHIFT 9 ++#define IXGBE_RTTDT2C_GSP 0x40000000 ++#define IXGBE_RTTDT2C_LSP 0x80000000 ++ ++#define IXGBE_RTTPT2C_MCL_SHIFT 12 ++#define IXGBE_RTTPT2C_BWG_SHIFT 9 ++#define IXGBE_RTTPT2C_GSP 0x40000000 ++#define IXGBE_RTTPT2C_LSP 0x80000000 ++ ++/* RTTPCS Bit Masks */ ++#define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin, ++ * 1 SP - Strict Priority ++ */ ++#define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */ ++#define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */ ++#define IXGBE_RTTPCS_ARBD_SHIFT 22 ++#define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */ ++ ++#define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */ ++#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ ++#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ ++#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ ++#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ ++#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */ ++ ++#define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */ ++ ++ ++/* DCB hardware-specific driver APIs */ ++ ++/* DCB PFC functions */ ++s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, ++ struct ixgbe_dcb_config *dcb_config); ++s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw, ++ struct ixgbe_hw_stats *stats, ++ u8 tc_count); ++ ++/* DCB traffic class stats */ ++s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw); ++s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw, ++ struct ixgbe_hw_stats *stats, ++ u8 tc_count); ++ ++/* DCB config arbiters */ ++s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, ++ struct ixgbe_dcb_config *dcb_config); ++s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, ++ struct ixgbe_dcb_config *dcb_config); ++s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, ++ struct ixgbe_dcb_config *dcb_config); ++ ++/* DCB hw initialization */ ++s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, ++ struct ixgbe_dcb_config *config); ++ ++#endif /* _DCB_82599_CONFIG_H */ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_dcb_nl.c +--- a/drivers/net/ixgbe/ixgbe_dcb_nl.c Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe_dcb_nl.c Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -20,22 +20,256 @@ + the file called "COPYING". + + Contact Information: +- Linux NICS + e1000-devel Mailing List + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + + *******************************************************************************/ + + #include "ixgbe.h" ++ ++#ifdef CONFIG_DCB + #include ++#include "ixgbe_dcb_82598.h" ++#include "ixgbe_dcb_82599.h" ++#else ++#include ++#include ++#include ++#include ++#endif + + /* Callbacks for DCB netlink in the kernel */ +-#define BIT_DCB_MODE 0x01 +-#define BIT_PFC 0x02 +-#define BIT_PG_RX 0x04 +-#define BIT_PG_TX 0x08 +-#define BIT_BCN 0x10 ++#define BIT_DCB_MODE 0x01 ++#define BIT_PFC 0x02 ++#define BIT_PG_RX 0x04 ++#define BIT_PG_TX 0x08 ++#define BIT_RESETLINK 0x40 ++#define BIT_LINKSPEED 0x80 + ++/* Responses for the DCB_C_SET_ALL command */ ++#define DCB_HW_CHG_RST 0 /* DCB configuration changed with reset */ ++#define DCB_NO_HW_CHG 1 /* DCB configuration did not change */ ++#define DCB_HW_CHG 2 /* DCB configuration changed, no reset */ ++ ++#ifndef CONFIG_DCB ++/* DCB configuration commands */ ++enum { ++ DCB_C_UNDEFINED, ++ DCB_C_GSTATE, ++ DCB_C_SSTATE, ++ DCB_C_PG_STATS, ++ DCB_C_PGTX_GCFG, ++ DCB_C_PGTX_SCFG, ++ DCB_C_PGRX_GCFG, ++ DCB_C_PGRX_SCFG, ++ DCB_C_PFC_GCFG, ++ DCB_C_PFC_SCFG, ++ DCB_C_PFC_STATS, ++ DCB_C_GLINK_SPD, ++ DCB_C_SLINK_SPD, ++ DCB_C_SET_ALL, ++ DCB_C_GPERM_HWADDR, ++ __DCB_C_ENUM_MAX, ++}; ++ ++#define IXGBE_DCB_C_MAX (__DCB_C_ENUM_MAX - 1) ++ ++/* DCB configuration attributes */ ++enum { ++ DCB_A_UNDEFINED = 0, ++ DCB_A_IFNAME, ++ DCB_A_STATE, ++ DCB_A_PFC_STATS, ++ DCB_A_PFC_CFG, ++ DCB_A_PG_STATS, ++ DCB_A_PG_CFG, ++ DCB_A_LINK_SPD, ++ DCB_A_SET_ALL, ++ DCB_A_PERM_HWADDR, ++ __DCB_A_ENUM_MAX, ++}; ++ ++#define IXGBE_DCB_A_MAX (__DCB_A_ENUM_MAX - 1) ++ ++/* PERM HWADDR attributes */ ++enum { ++ PERM_HW_A_UNDEFINED, ++ PERM_HW_A_0, ++ PERM_HW_A_1, ++ PERM_HW_A_2, ++ PERM_HW_A_3, ++ PERM_HW_A_4, ++ PERM_HW_A_5, ++ PERM_HW_A_ALL, ++ __PERM_HW_A_ENUM_MAX, ++}; ++ ++#define IXGBE_DCB_PERM_HW_A_MAX (__PERM_HW_A_ENUM_MAX - 1) ++ ++/* PFC configuration attributes */ ++enum { ++ PFC_A_UP_UNDEFINED, ++ PFC_A_UP_0, ++ PFC_A_UP_1, ++ PFC_A_UP_2, ++ PFC_A_UP_3, ++ PFC_A_UP_4, ++ PFC_A_UP_5, ++ PFC_A_UP_6, ++ PFC_A_UP_7, ++ PFC_A_UP_MAX, /* Used as an iterator cap */ ++ PFC_A_UP_ALL, ++ __PFC_A_UP_ENUM_MAX, ++}; ++ ++#define IXGBE_DCB_PFC_A_UP_MAX (__PFC_A_UP_ENUM_MAX - 1) ++ ++/* Priority Group Traffic Class and Bandwidth Group ++ * configuration attributes ++ */ ++enum { ++ PG_A_UNDEFINED, ++ PG_A_TC_0, ++ PG_A_TC_1, ++ PG_A_TC_2, ++ PG_A_TC_3, ++ PG_A_TC_4, ++ PG_A_TC_5, ++ PG_A_TC_6, ++ PG_A_TC_7, ++ PG_A_TC_MAX, /* Used as an iterator cap */ ++ PG_A_TC_ALL, ++ PG_A_BWG_0, ++ PG_A_BWG_1, ++ PG_A_BWG_2, ++ PG_A_BWG_3, ++ PG_A_BWG_4, ++ PG_A_BWG_5, ++ PG_A_BWG_6, ++ PG_A_BWG_7, ++ PG_A_BWG_MAX, /* Used as an iterator cap */ ++ PG_A_BWG_ALL, ++ __PG_A_ENUM_MAX, ++}; ++ ++#define IXGBE_DCB_PG_A_MAX (__PG_A_ENUM_MAX - 1) ++ ++enum { ++ TC_A_PARAM_UNDEFINED, ++ TC_A_PARAM_STRICT_PRIO, ++ TC_A_PARAM_BW_GROUP_ID, ++ TC_A_PARAM_BW_PCT_IN_GROUP, ++ TC_A_PARAM_UP_MAPPING, ++ TC_A_PARAM_MAX, /* Used as an iterator cap */ ++ TC_A_PARAM_ALL, ++ __TC_A_PARAM_ENUM_MAX, ++}; ++ ++#define IXGBE_DCB_TC_A_PARAM_MAX (__TC_A_PARAM_ENUM_MAX - 1) ++ ++#define DCB_PROTO_VERSION 0x1 ++#define is_pci_device(dev) ((dev)->bus == &pci_bus_type) ++ ++static struct genl_family dcb_family = { ++ .id = GENL_ID_GENERATE, ++ .hdrsize = 0, ++ .name = "IXGBE_DCB", ++ .version = DCB_PROTO_VERSION, ++ .maxattr = IXGBE_DCB_A_MAX, ++}; ++ ++/* DCB NETLINK attributes policy */ ++static struct nla_policy dcb_genl_policy[IXGBE_DCB_A_MAX + 1] = { ++ [DCB_A_IFNAME] = {.type = NLA_STRING, .len = IFNAMSIZ - 1}, ++ [DCB_A_STATE] = {.type = NLA_U8}, ++ [DCB_A_PG_CFG] = {.type = NLA_NESTED}, ++ [DCB_A_PFC_CFG] = {.type = NLA_NESTED}, ++ [DCB_A_PFC_STATS] = {.type = NLA_NESTED}, ++ [DCB_A_PG_STATS] = {.type = NLA_NESTED}, ++ [DCB_A_LINK_SPD] = {.type = NLA_U8}, ++ [DCB_A_SET_ALL] = {.type = NLA_U8}, ++ [DCB_A_PERM_HWADDR] = {.type = NLA_NESTED}, ++}; ++ ++/* DCB_A_PERM_HWADDR nested attributes... an array. */ ++static struct nla_policy dcb_perm_hwaddr_nest[IXGBE_DCB_PERM_HW_A_MAX + 1] = { ++ [PERM_HW_A_0] = {.type = NLA_U8}, ++ [PERM_HW_A_1] = {.type = NLA_U8}, ++ [PERM_HW_A_2] = {.type = NLA_U8}, ++ [PERM_HW_A_3] = {.type = NLA_U8}, ++ [PERM_HW_A_4] = {.type = NLA_U8}, ++ [PERM_HW_A_5] = {.type = NLA_U8}, ++ [PERM_HW_A_ALL] = {.type = NLA_FLAG}, ++}; ++ ++/* DCB_A_PFC_CFG nested attributes...like an array. */ ++static struct nla_policy dcb_pfc_up_nest[IXGBE_DCB_PFC_A_UP_MAX + 1] = { ++ [PFC_A_UP_0] = {.type = NLA_U8}, ++ [PFC_A_UP_1] = {.type = NLA_U8}, ++ [PFC_A_UP_2] = {.type = NLA_U8}, ++ [PFC_A_UP_3] = {.type = NLA_U8}, ++ [PFC_A_UP_4] = {.type = NLA_U8}, ++ [PFC_A_UP_5] = {.type = NLA_U8}, ++ [PFC_A_UP_6] = {.type = NLA_U8}, ++ [PFC_A_UP_7] = {.type = NLA_U8}, ++ [PFC_A_UP_ALL] = {.type = NLA_FLAG}, ++}; ++ ++/* DCB_A_PG_CFG nested attributes...like a struct. */ ++static struct nla_policy dcb_pg_nest[IXGBE_DCB_PG_A_MAX + 1] = { ++ [PG_A_TC_0] = {.type = NLA_NESTED}, ++ [PG_A_TC_1] = {.type = NLA_NESTED}, ++ [PG_A_TC_2] = {.type = NLA_NESTED}, ++ [PG_A_TC_3] = {.type = NLA_NESTED}, ++ [PG_A_TC_4] = {.type = NLA_NESTED}, ++ [PG_A_TC_5] = {.type = NLA_NESTED}, ++ [PG_A_TC_6] = {.type = NLA_NESTED}, ++ [PG_A_TC_7] = {.type = NLA_NESTED}, ++ [PG_A_TC_ALL] = {.type = NLA_NESTED}, ++ [PG_A_BWG_0] = {.type = NLA_U8}, ++ [PG_A_BWG_1] = {.type = NLA_U8}, ++ [PG_A_BWG_2] = {.type = NLA_U8}, ++ [PG_A_BWG_3] = {.type = NLA_U8}, ++ [PG_A_BWG_4] = {.type = NLA_U8}, ++ [PG_A_BWG_5] = {.type = NLA_U8}, ++ [PG_A_BWG_6] = {.type = NLA_U8}, ++ [PG_A_BWG_7] = {.type = NLA_U8}, ++ [PG_A_BWG_ALL]= {.type = NLA_FLAG}, ++}; ++ ++/* TC_A_CLASS_X nested attributes. */ ++static struct nla_policy dcb_tc_param_nest[IXGBE_DCB_TC_A_PARAM_MAX + 1] = { ++ [TC_A_PARAM_STRICT_PRIO] = {.type = NLA_U8}, ++ [TC_A_PARAM_BW_GROUP_ID] = {.type = NLA_U8}, ++ [TC_A_PARAM_BW_PCT_IN_GROUP] = {.type = NLA_U8}, ++ [TC_A_PARAM_UP_MAPPING] = {.type = NLA_U8}, ++ [TC_A_PARAM_ALL] = {.type = NLA_FLAG}, ++}; ++ ++static int ixgbe_dcb_check_adapter(struct net_device *netdev) ++{ ++ struct device *busdev; ++ struct pci_dev *pcidev; ++ ++ busdev = netdev->dev.parent; ++ if (!busdev) ++ return -EINVAL; ++ ++ if (!is_pci_device(busdev)) ++ return -EINVAL; ++ ++ pcidev = to_pci_dev(busdev); ++ if (!pcidev) ++ return -EINVAL; ++ ++ if (ixgbe_is_ixgbe(pcidev)) ++ return 0; ++ else ++ return -EINVAL; ++} ++#endif ++ ++#ifdef CONFIG_DCB + int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg, + struct ixgbe_dcb_config *dst_dcb_cfg, int tc_max) + { +@@ -88,111 +322,495 @@ + dst_dcb_cfg->tc_config[i - DCB_PFC_UP_ATTR_0].dcb_pfc = + src_dcb_cfg->tc_config[i - DCB_PFC_UP_ATTR_0].dcb_pfc; + } ++ dst_dcb_cfg->pfc_mode_enable = src_dcb_cfg->pfc_mode_enable; + +- for (i = DCB_BCN_ATTR_RP_0; i < DCB_BCN_ATTR_RP_ALL; i++) { +- dst_dcb_cfg->bcn.rp_admin_mode[i - DCB_BCN_ATTR_RP_0] = +- src_dcb_cfg->bcn.rp_admin_mode[i - DCB_BCN_ATTR_RP_0]; ++ return 0; ++} ++#else ++static int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg, ++ struct ixgbe_dcb_config *dst_dcb_cfg, int tc_max) ++{ ++ struct tc_configuration *src_tc_cfg = NULL; ++ struct tc_configuration *dst_tc_cfg = NULL; ++ int i; ++ ++ if (!src_dcb_cfg || !dst_dcb_cfg) ++ return -EINVAL; ++ ++ dst_dcb_cfg->link_speed = src_dcb_cfg->link_speed; ++ ++ for (i = PG_A_TC_0; i < tc_max + PG_A_TC_0; i++) { ++ src_tc_cfg = &src_dcb_cfg->tc_config[i - PG_A_TC_0]; ++ dst_tc_cfg = &dst_dcb_cfg->tc_config[i - PG_A_TC_0]; ++ ++ dst_tc_cfg->path[DCB_TX_CONFIG].prio_type = ++ src_tc_cfg->path[DCB_TX_CONFIG].prio_type; ++ ++ dst_tc_cfg->path[DCB_TX_CONFIG].bwg_id = ++ src_tc_cfg->path[DCB_TX_CONFIG].bwg_id; ++ ++ dst_tc_cfg->path[DCB_TX_CONFIG].bwg_percent = ++ src_tc_cfg->path[DCB_TX_CONFIG].bwg_percent; ++ ++ dst_tc_cfg->path[DCB_TX_CONFIG].up_to_tc_bitmap = ++ src_tc_cfg->path[DCB_TX_CONFIG].up_to_tc_bitmap; ++ ++ dst_tc_cfg->path[DCB_RX_CONFIG].prio_type = ++ src_tc_cfg->path[DCB_RX_CONFIG].prio_type; ++ ++ dst_tc_cfg->path[DCB_RX_CONFIG].bwg_id = ++ src_tc_cfg->path[DCB_RX_CONFIG].bwg_id; ++ ++ dst_tc_cfg->path[DCB_RX_CONFIG].bwg_percent = ++ src_tc_cfg->path[DCB_RX_CONFIG].bwg_percent; ++ ++ dst_tc_cfg->path[DCB_RX_CONFIG].up_to_tc_bitmap = ++ src_tc_cfg->path[DCB_RX_CONFIG].up_to_tc_bitmap; + } +- dst_dcb_cfg->bcn.bcna_option[0] = src_dcb_cfg->bcn.bcna_option[0]; +- dst_dcb_cfg->bcn.bcna_option[1] = src_dcb_cfg->bcn.bcna_option[1]; +- dst_dcb_cfg->bcn.rp_alpha = src_dcb_cfg->bcn.rp_alpha; +- dst_dcb_cfg->bcn.rp_beta = src_dcb_cfg->bcn.rp_beta; +- dst_dcb_cfg->bcn.rp_gd = src_dcb_cfg->bcn.rp_gd; +- dst_dcb_cfg->bcn.rp_gi = src_dcb_cfg->bcn.rp_gi; +- dst_dcb_cfg->bcn.rp_tmax = src_dcb_cfg->bcn.rp_tmax; +- dst_dcb_cfg->bcn.rp_td = src_dcb_cfg->bcn.rp_td; +- dst_dcb_cfg->bcn.rp_rmin = src_dcb_cfg->bcn.rp_rmin; +- dst_dcb_cfg->bcn.rp_w = src_dcb_cfg->bcn.rp_w; +- dst_dcb_cfg->bcn.rp_rd = src_dcb_cfg->bcn.rp_rd; +- dst_dcb_cfg->bcn.rp_ru = src_dcb_cfg->bcn.rp_ru; +- dst_dcb_cfg->bcn.rp_wrtt = src_dcb_cfg->bcn.rp_wrtt; +- dst_dcb_cfg->bcn.rp_ri = src_dcb_cfg->bcn.rp_ri; ++ ++ for (i = PG_A_BWG_0; i < PG_A_BWG_MAX; i++) { ++ dst_dcb_cfg->bw_percentage[DCB_TX_CONFIG][i - PG_A_BWG_0] = ++ src_dcb_cfg->bw_percentage[DCB_TX_CONFIG][i - PG_A_BWG_0]; ++ dst_dcb_cfg->bw_percentage[DCB_RX_CONFIG][i - PG_A_BWG_0] = ++ src_dcb_cfg->bw_percentage[DCB_RX_CONFIG][i - PG_A_BWG_0]; ++ } ++ ++ for (i = PFC_A_UP_0; i < PFC_A_UP_MAX; i++) { ++ dst_dcb_cfg->tc_config[i - PFC_A_UP_0].dcb_pfc = ++ src_dcb_cfg->tc_config[i - PFC_A_UP_0].dcb_pfc; ++ } + + return 0; + } + ++static int ixgbe_nl_reply(u8 value, u8 cmd, u8 attr, struct genl_info *info) ++{ ++ struct sk_buff *dcb_skb = NULL; ++ void *data; ++ int ret; ++ ++ dcb_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); ++ if (!dcb_skb) ++ return -EINVAL; ++ ++ data = genlmsg_put_reply(dcb_skb, info, &dcb_family, 0, cmd); ++ if (!data) ++ goto err; ++ ++ ret = nla_put_u8(dcb_skb, attr, value); ++ if (ret) ++ goto err; ++ ++ /* end the message, assign the nlmsg_len. */ ++ genlmsg_end(dcb_skb, data); ++ ret = genlmsg_reply(dcb_skb, info); ++ if (ret) ++ goto err; ++ ++ return 0; ++ ++err: ++ kfree(dcb_skb); ++ return -EINVAL; ++} ++#endif ++ ++#ifdef CONFIG_DCB + static u8 ixgbe_dcbnl_get_state(struct net_device *netdev) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); + +- DPRINTK(DRV, INFO, "Get DCB Admin Mode.\n"); +- + return !!(adapter->flags & IXGBE_FLAG_DCB_ENABLED); +-} +- +-static u16 ixgbe_dcb_select_queue(struct net_device *dev, struct sk_buff *skb) +-{ +- /* All traffic should default to class 0 */ +- return 0; + } + + static u8 ixgbe_dcbnl_set_state(struct net_device *netdev, u8 state) + { ++ u8 err = 0; + struct ixgbe_adapter *adapter = netdev_priv(netdev); +- +- DPRINTK(DRV, INFO, "Set DCB Admin Mode.\n"); + + if (state > 0) { + /* Turn on DCB */ +- if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { +- return 0; +- } ++ if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) ++ goto out; + + if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { +- DPRINTK(DRV, ERR, "Enable Failed, needs MSI-X\n"); +- return 1; +- } ++ DPRINTK(DRV, ERR, "Enable failed, needs MSI-X\n"); ++ err = 1; ++ goto out; ++ } + + if (netif_running(netdev)) ++#ifdef HAVE_NET_DEVICE_OPS ++ netdev->netdev_ops->ndo_stop(netdev); ++#else + netdev->stop(netdev); +- ixgbe_reset_interrupt_capability(adapter); +- ixgbe_napi_del_all(adapter); +- kfree(adapter->tx_ring); +- kfree(adapter->rx_ring); +- adapter->tx_ring = NULL; +- adapter->rx_ring = NULL; +- netdev->select_queue = &ixgbe_dcb_select_queue; +- ++#endif ++ ixgbe_clear_interrupt_scheme(adapter); ++ if (adapter->hw.mac.type == ixgbe_mac_82598EB) { ++ adapter->last_lfc_mode = adapter->hw.fc.current_mode; ++ adapter->hw.fc.requested_mode = ixgbe_fc_none; ++ } + adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; ++ if (adapter->hw.mac.type == ixgbe_mac_82599EB) { ++ DPRINTK(DRV, INFO, "DCB enabled, " ++ "disabling Flow Director\n"); ++ adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; ++ adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; ++ } + adapter->flags |= IXGBE_FLAG_DCB_ENABLED; + ixgbe_init_interrupt_scheme(adapter); +- ixgbe_napi_add_all(adapter); + if (netif_running(netdev)) ++#ifdef HAVE_NET_DEVICE_OPS ++ netdev->netdev_ops->ndo_open(netdev); ++#else + netdev->open(netdev); ++#endif + } else { + /* Turn off DCB */ + if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { + if (netif_running(netdev)) ++#ifdef HAVE_NET_DEVICE_OPS ++ netdev->netdev_ops->ndo_stop(netdev); ++#else + netdev->stop(netdev); +- ixgbe_reset_interrupt_capability(adapter); +- ixgbe_napi_del_all(adapter); +- kfree(adapter->tx_ring); +- kfree(adapter->rx_ring); +- adapter->tx_ring = NULL; +- adapter->rx_ring = NULL; +- netdev->select_queue = NULL; +- ++#endif ++ ixgbe_clear_interrupt_scheme(adapter); ++ adapter->hw.fc.requested_mode = adapter->last_lfc_mode; ++ adapter->temp_dcb_cfg.pfc_mode_enable = false; ++ adapter->dcb_cfg.pfc_mode_enable = false; + adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; + adapter->flags |= IXGBE_FLAG_RSS_ENABLED; ++ if (adapter->hw.mac.type == ixgbe_mac_82599EB) ++ adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; + ixgbe_init_interrupt_scheme(adapter); +- ixgbe_napi_add_all(adapter); + if (netif_running(netdev)) ++#ifdef HAVE_NET_DEVICE_OPS ++ netdev->netdev_ops->ndo_open(netdev); ++#else + netdev->open(netdev); ++#endif + } + } +- return 0; ++out: ++ return err; ++} ++#else ++static int ixgbe_dcb_gstate(struct sk_buff *skb, struct genl_info *info) ++{ ++ int ret = -ENOMEM; ++ struct net_device *netdev = NULL; ++ struct ixgbe_adapter *adapter = NULL; ++ ++ if (!info->attrs[DCB_A_IFNAME]) ++ return -EINVAL; ++ ++ netdev = dev_get_by_name(&init_net, ++ nla_data(info->attrs[DCB_A_IFNAME])); ++ if (!netdev) ++ return -EINVAL; ++ ++ ret = ixgbe_dcb_check_adapter(netdev); ++ if (ret) ++ goto err_out; ++ else ++ adapter = netdev_priv(netdev); ++ ++ ret = ixgbe_nl_reply(!!(adapter->flags & IXGBE_FLAG_DCB_ENABLED), ++ DCB_C_GSTATE, DCB_A_STATE, info); ++ if (ret) ++ goto err_out; ++ ++err_out: ++ dev_put(netdev); ++ return ret; + } + ++static int ixgbe_dcb_sstate(struct sk_buff *skb, struct genl_info *info) ++{ ++ struct net_device *netdev = NULL; ++ struct ixgbe_adapter *adapter = NULL; ++ int ret = -EINVAL; ++ u8 value; ++ ++ if (!info->attrs[DCB_A_IFNAME] || !info->attrs[DCB_A_STATE]) ++ goto err; ++ ++ netdev = dev_get_by_name(&init_net, ++ nla_data(info->attrs[DCB_A_IFNAME])); ++ if (!netdev) ++ goto err; ++ ++ ret = ixgbe_dcb_check_adapter(netdev); ++ if (ret) ++ goto err_out; ++ else ++ adapter = netdev_priv(netdev); ++ ++ value = nla_get_u8(info->attrs[DCB_A_STATE]); ++ if ((value & 1) != value) { ++ DPRINTK(DRV, ERR, "Value is not 1 or 0, it is %d.\n", value); ++ } else { ++ switch (value) { ++ case 0: ++ if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { ++ if (netdev->flags & IFF_UP) ++#ifdef HAVE_NET_DEVICE_OPS ++ netdev->netdev_ops->ndo_stop(netdev); ++#else ++ netdev->stop(netdev); ++#endif ++ ixgbe_clear_interrupt_scheme(adapter); ++ ++ adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; ++ if (adapter->flags & IXGBE_FLAG_RSS_CAPABLE) ++ adapter->flags |= ++ IXGBE_FLAG_RSS_ENABLED; ++ ixgbe_init_interrupt_scheme(adapter); ++ ixgbe_reset(adapter); ++ if (netdev->flags & IFF_UP) ++#ifdef HAVE_NET_DEVICE_OPS ++ netdev->netdev_ops->ndo_open(netdev); ++#else ++ netdev->open(netdev); ++#endif ++ break; ++ } else { ++ /* Nothing to do, already off */ ++ goto out; ++ } ++ case 1: ++ if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { ++ /* Nothing to do, already on */ ++ goto out; ++ } else if (!(adapter->flags & IXGBE_FLAG_DCB_CAPABLE)) { ++ DPRINTK(DRV, ERR, "Enable failed. Make sure " ++ "the driver can enable MSI-X.\n"); ++ ret = -EINVAL; ++ goto err_out; ++ } else { ++ if (netdev->flags & IFF_UP) ++#ifdef HAVE_NET_DEVICE_OPS ++ netdev->netdev_ops->ndo_stop(netdev); ++#else ++ netdev->stop(netdev); ++#endif ++ ixgbe_clear_interrupt_scheme(adapter); ++ ++ adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; ++ adapter->flags |= IXGBE_FLAG_DCB_ENABLED; ++ adapter->dcb_cfg.support.capabilities = ++ (IXGBE_DCB_PG_SUPPORT | IXGBE_DCB_PFC_SUPPORT | ++ IXGBE_DCB_GSP_SUPPORT); ++ if (adapter->hw.mac.type == ixgbe_mac_82599EB) { ++ DPRINTK(DRV, INFO, "DCB enabled, " ++ "disabling Flow Director\n"); ++ adapter->flags &= ++ ~IXGBE_FLAG_FDIR_HASH_CAPABLE; ++ adapter->flags &= ++ ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; ++ adapter->dcb_cfg.support.capabilities |= ++ IXGBE_DCB_UP2TC_SUPPORT; ++ } ++ adapter->ring_feature[RING_F_DCB].indices = 8; ++ ixgbe_init_interrupt_scheme(adapter); ++ ixgbe_reset(adapter); ++ if (netdev->flags & IFF_UP) ++#ifdef HAVE_NET_DEVICE_OPS ++ netdev->netdev_ops->ndo_open(netdev); ++#else ++ netdev->open(netdev); ++#endif ++ break; ++ } ++ } ++ } ++ ++out: ++ ret = ixgbe_nl_reply(0, DCB_C_SSTATE, DCB_A_STATE, info); ++ if (ret) ++ goto err_out; ++ ++err_out: ++ dev_put(netdev); ++err: ++ return ret; ++} ++ ++static int ixgbe_dcb_glink_spd(struct sk_buff *skb, struct genl_info *info) ++{ ++ int ret = -ENOMEM; ++ struct net_device *netdev = NULL; ++ struct ixgbe_adapter *adapter = NULL; ++ ++ if (!info->attrs[DCB_A_IFNAME]) ++ return -EINVAL; ++ ++ netdev = dev_get_by_name(&init_net, ++ nla_data(info->attrs[DCB_A_IFNAME])); ++ if (!netdev) ++ return -EINVAL; ++ ++ ret = ixgbe_dcb_check_adapter(netdev); ++ if (ret) ++ goto err_out; ++ else ++ adapter = netdev_priv(netdev); ++ ++ ret = ixgbe_nl_reply(adapter->dcb_cfg.link_speed & 0xff, ++ DCB_C_GLINK_SPD, DCB_A_LINK_SPD, info); ++ if (ret) ++ goto err_out; ++ ++err_out: ++ dev_put(netdev); ++ return ret; ++} ++ ++static int ixgbe_dcb_slink_spd(struct sk_buff *skb, struct genl_info *info) ++{ ++ struct net_device *netdev = NULL; ++ struct ixgbe_adapter *adapter = NULL; ++ int ret = -EINVAL; ++ u8 value; ++ ++ if (!info->attrs[DCB_A_IFNAME] || !info->attrs[DCB_A_LINK_SPD]) ++ goto err; ++ ++ netdev = dev_get_by_name(&init_net, ++ nla_data(info->attrs[DCB_A_IFNAME])); ++ if (!netdev) ++ goto err; ++ ++ ret = ixgbe_dcb_check_adapter(netdev); ++ if (ret) ++ goto err_out; ++ else ++ adapter = netdev_priv(netdev); ++ ++ value = nla_get_u8(info->attrs[DCB_A_LINK_SPD]); ++ if (value > 9) { ++ DPRINTK(DRV, ERR, "Value is not 0 thru 9, it is %d.\n", value); ++ } else { ++ if (!adapter->dcb_set_bitmap && ++ ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, ++ adapter->ring_feature[RING_F_DCB].indices)) { ++ ret = -EINVAL; ++ goto err_out; ++ } ++ ++ adapter->temp_dcb_cfg.link_speed = value; ++ adapter->dcb_set_bitmap |= BIT_LINKSPEED; ++ } ++ ++ ret = ixgbe_nl_reply(0, DCB_C_SLINK_SPD, DCB_A_LINK_SPD, info); ++ if (ret) ++ goto err_out; ++ ++err_out: ++ dev_put(netdev); ++err: ++ return ret; ++} ++#endif ++ ++#ifdef CONFIG_DCB + static void ixgbe_dcbnl_get_perm_hw_addr(struct net_device *netdev, + u8 *perm_addr) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); +- int i; ++ int i, j; ++ ++ memset(perm_addr, 0xff, MAX_ADDR_LEN); + + for (i = 0; i < netdev->addr_len; i++) + perm_addr[i] = adapter->hw.mac.perm_addr[i]; ++ ++ if (adapter->hw.mac.type == ixgbe_mac_82599EB) { ++ for (j = 0; j < netdev->addr_len; j++, i++) ++ perm_addr[i] = adapter->hw.mac.san_addr[j]; ++ } + } ++#else ++static int ixgbe_dcb_gperm_hwaddr(struct sk_buff *skb, struct genl_info *info) ++{ ++ void *data; ++ struct sk_buff *dcb_skb = NULL; ++ struct nlattr *tb[IXGBE_DCB_PERM_HW_A_MAX + 1], *nest; ++ struct net_device *netdev = NULL; ++ struct ixgbe_adapter *adapter = NULL; ++ struct ixgbe_hw *hw = NULL; ++ int ret = -ENOMEM; ++ int i; + ++ if (!info->attrs[DCB_A_IFNAME] || !info->attrs[DCB_A_PERM_HWADDR]) ++ return -EINVAL; ++ ++ netdev = dev_get_by_name(&init_net, ++ nla_data(info->attrs[DCB_A_IFNAME])); ++ if (!netdev) ++ return -EINVAL; ++ ++ ret = ixgbe_dcb_check_adapter(netdev); ++ if (ret) ++ goto err_out; ++ else ++ adapter = netdev_priv(netdev); ++ ++ hw = &adapter->hw; ++ ++ ret = nla_parse_nested(tb, IXGBE_DCB_PERM_HW_A_MAX, ++ info->attrs[DCB_A_PERM_HWADDR], ++ dcb_perm_hwaddr_nest); ++ if (ret) ++ goto err; ++ ++ dcb_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); ++ if (!dcb_skb) ++ goto err; ++ ++ data = genlmsg_put_reply(dcb_skb, info, &dcb_family, 0, ++ DCB_C_GPERM_HWADDR); ++ if (!data) ++ goto err; ++ ++ nest = nla_nest_start(dcb_skb, DCB_A_PERM_HWADDR); ++ if (!nest) ++ goto err; ++ ++ for (i = 0; i < netdev->addr_len; i++) { ++ if (!tb[i+PERM_HW_A_0] && !tb[PERM_HW_A_ALL]) ++ goto err; ++ ++ ret = nla_put_u8(dcb_skb, DCB_A_PERM_HWADDR, ++ hw->mac.perm_addr[i]); ++ ++ if (ret) { ++ nla_nest_cancel(dcb_skb, nest); ++ goto err; ++ } ++ } ++ ++ nla_nest_end(dcb_skb, nest); ++ ++ genlmsg_end(dcb_skb, data); ++ ++ ret = genlmsg_reply(dcb_skb, info); ++ if (ret) ++ goto err; ++ ++ dev_put(netdev); ++ return 0; ++ ++err: ++ DPRINTK(DRV, ERR, "Error in get permanent hwaddr.\n"); ++ kfree(dcb_skb); ++err_out: ++ dev_put(netdev); ++ return ret; ++} ++#endif ++ ++#ifdef CONFIG_DCB + static void ixgbe_dcbnl_set_pg_tc_cfg_tx(struct net_device *netdev, int tc, + u8 prio, u8 bwg_id, u8 bw_pct, + u8 up_map) +@@ -217,8 +835,10 @@ + (adapter->temp_dcb_cfg.tc_config[tc].path[0].bwg_percent != + adapter->dcb_cfg.tc_config[tc].path[0].bwg_percent) || + (adapter->temp_dcb_cfg.tc_config[tc].path[0].up_to_tc_bitmap != +- adapter->dcb_cfg.tc_config[tc].path[0].up_to_tc_bitmap)) ++ adapter->dcb_cfg.tc_config[tc].path[0].up_to_tc_bitmap)) { + adapter->dcb_set_bitmap |= BIT_PG_TX; ++ adapter->dcb_set_bitmap |= BIT_RESETLINK; ++ } + } + + static void ixgbe_dcbnl_set_pg_bwg_cfg_tx(struct net_device *netdev, int bwg_id, +@@ -229,8 +849,10 @@ + adapter->temp_dcb_cfg.bw_percentage[0][bwg_id] = bw_pct; + + if (adapter->temp_dcb_cfg.bw_percentage[0][bwg_id] != +- adapter->dcb_cfg.bw_percentage[0][bwg_id]) ++ adapter->dcb_cfg.bw_percentage[0][bwg_id]) { + adapter->dcb_set_bitmap |= BIT_PG_RX; ++ adapter->dcb_set_bitmap |= BIT_RESETLINK; ++ } + } + + static void ixgbe_dcbnl_set_pg_tc_cfg_rx(struct net_device *netdev, int tc, +@@ -257,8 +879,10 @@ + (adapter->temp_dcb_cfg.tc_config[tc].path[1].bwg_percent != + adapter->dcb_cfg.tc_config[tc].path[1].bwg_percent) || + (adapter->temp_dcb_cfg.tc_config[tc].path[1].up_to_tc_bitmap != +- adapter->dcb_cfg.tc_config[tc].path[1].up_to_tc_bitmap)) ++ adapter->dcb_cfg.tc_config[tc].path[1].up_to_tc_bitmap)) { + adapter->dcb_set_bitmap |= BIT_PG_RX; ++ adapter->dcb_set_bitmap |= BIT_RESETLINK; ++ } + } + + static void ixgbe_dcbnl_set_pg_bwg_cfg_rx(struct net_device *netdev, int bwg_id, +@@ -269,8 +893,10 @@ + adapter->temp_dcb_cfg.bw_percentage[1][bwg_id] = bw_pct; + + if (adapter->temp_dcb_cfg.bw_percentage[1][bwg_id] != +- adapter->dcb_cfg.bw_percentage[1][bwg_id]) ++ adapter->dcb_cfg.bw_percentage[1][bwg_id]) { + adapter->dcb_set_bitmap |= BIT_PG_RX; ++ adapter->dcb_set_bitmap |= BIT_RESETLINK; ++ } + } + + static void ixgbe_dcbnl_get_pg_tc_cfg_tx(struct net_device *netdev, int tc, +@@ -312,7 +938,274 @@ + + *bw_pct = adapter->dcb_cfg.bw_percentage[1][bwg_id]; + } ++#else ++static int ixgbe_dcb_pg_scfg(struct sk_buff *skb, struct genl_info *info, ++ int dir) ++{ ++ struct net_device *netdev = NULL; ++ struct ixgbe_adapter *adapter = NULL; ++ struct tc_configuration *tc_config = NULL; ++ struct tc_configuration *tc_tmpcfg = NULL; ++ struct nlattr *pg_tb[IXGBE_DCB_PG_A_MAX + 1]; ++ struct nlattr *param_tb[IXGBE_DCB_TC_A_PARAM_MAX + 1]; ++ int i, ret, tc_max; ++ u8 value; ++ u8 changed = 0; + ++ if (!info->attrs[DCB_A_IFNAME] || !info->attrs[DCB_A_PG_CFG]) ++ return -EINVAL; ++ ++ netdev = dev_get_by_name(&init_net, ++ nla_data(info->attrs[DCB_A_IFNAME])); ++ if (!netdev) ++ return -EINVAL; ++ ++ ret = ixgbe_dcb_check_adapter(netdev); ++ if (ret) ++ goto err; ++ else ++ adapter = netdev_priv(netdev); ++ ++ ret = nla_parse_nested(pg_tb, IXGBE_DCB_PG_A_MAX, ++ info->attrs[DCB_A_PG_CFG], dcb_pg_nest); ++ if (ret) ++ goto err; ++ ++ if (!adapter->dcb_set_bitmap && ++ ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, ++ adapter->ring_feature[RING_F_DCB].indices)) ++ goto err; ++ ++ tc_max = adapter->ring_feature[RING_F_DCB].indices; ++ for (i = PG_A_TC_0; i < tc_max + PG_A_TC_0; i++) { ++ if (!pg_tb[i]) ++ continue; ++ ++ ret = nla_parse_nested(param_tb, IXGBE_DCB_TC_A_PARAM_MAX, ++ pg_tb[i], dcb_tc_param_nest); ++ if (ret) ++ goto err; ++ ++ tc_config = &adapter->dcb_cfg.tc_config[i - PG_A_TC_0]; ++ tc_tmpcfg = &adapter->temp_dcb_cfg.tc_config[i - PG_A_TC_0]; ++ if (param_tb[TC_A_PARAM_STRICT_PRIO]) { ++ value = nla_get_u8(param_tb[TC_A_PARAM_STRICT_PRIO]); ++ tc_tmpcfg->path[dir].prio_type = value; ++ if (tc_tmpcfg->path[dir].prio_type != ++ tc_config->path[dir].prio_type) ++ changed = 1; ++ } ++ if (param_tb[TC_A_PARAM_BW_GROUP_ID]) { ++ value = nla_get_u8(param_tb[TC_A_PARAM_BW_GROUP_ID]); ++ tc_tmpcfg->path[dir].bwg_id = value; ++ if (tc_tmpcfg->path[dir].bwg_id != ++ tc_config->path[dir].bwg_id) ++ changed = 1; ++ } ++ if (param_tb[TC_A_PARAM_BW_PCT_IN_GROUP]) { ++ value = nla_get_u8(param_tb[TC_A_PARAM_BW_PCT_IN_GROUP]); ++ tc_tmpcfg->path[dir].bwg_percent = value; ++ if (tc_tmpcfg->path[dir].bwg_percent != ++ tc_config->path[dir].bwg_percent) ++ changed = 1; ++ } ++ if (param_tb[TC_A_PARAM_UP_MAPPING]) { ++ value = nla_get_u8(param_tb[TC_A_PARAM_UP_MAPPING]); ++ tc_tmpcfg->path[dir].up_to_tc_bitmap = value; ++ if (tc_tmpcfg->path[dir].up_to_tc_bitmap != ++ tc_config->path[dir].up_to_tc_bitmap) ++ changed = 1; ++ } ++ } ++ ++ for (i = PG_A_BWG_0; i < PG_A_BWG_MAX; i++) { ++ if (!pg_tb[i]) ++ continue; ++ ++ value = nla_get_u8(pg_tb[i]); ++ adapter->temp_dcb_cfg.bw_percentage[dir][i-PG_A_BWG_0] = value; ++ ++ if (adapter->temp_dcb_cfg.bw_percentage[dir][i-PG_A_BWG_0] != ++ adapter->dcb_cfg.bw_percentage[dir][i-PG_A_BWG_0]) ++ changed = 1; ++ } ++ ++ adapter->temp_dcb_cfg.round_robin_enable = false; ++ ++ if (changed) { ++ if (dir == DCB_TX_CONFIG) ++ adapter->dcb_set_bitmap |= BIT_PG_TX; ++ else ++ adapter->dcb_set_bitmap |= BIT_PG_RX; ++ ++ adapter->dcb_set_bitmap |= BIT_RESETLINK; ++ } ++ ++ ret = ixgbe_nl_reply(0, (dir? DCB_C_PGRX_SCFG : DCB_C_PGTX_SCFG), ++ DCB_A_PG_CFG, info); ++ if (ret) ++ goto err; ++ ++err: ++ dev_put(netdev); ++ return ret; ++} ++ ++static int ixgbe_dcb_pgtx_scfg(struct sk_buff *skb, struct genl_info *info) ++{ ++ return ixgbe_dcb_pg_scfg(skb, info, DCB_TX_CONFIG); ++} ++ ++static int ixgbe_dcb_pgrx_scfg(struct sk_buff *skb, struct genl_info *info) ++{ ++ return ixgbe_dcb_pg_scfg(skb, info, DCB_RX_CONFIG); ++} ++ ++static int ixgbe_dcb_pg_gcfg(struct sk_buff *skb, struct genl_info *info, ++ int dir) ++{ ++ void *data; ++ struct sk_buff *dcb_skb = NULL; ++ struct nlattr *pg_nest, *param_nest, *tb; ++ struct nlattr *pg_tb[IXGBE_DCB_PG_A_MAX + 1]; ++ struct nlattr *param_tb[IXGBE_DCB_TC_A_PARAM_MAX + 1]; ++ struct net_device *netdev = NULL; ++ struct ixgbe_adapter *adapter = NULL; ++ struct tc_configuration *tc_config = NULL; ++ struct tc_bw_alloc *tc = NULL; ++ int ret = -ENOMEM; ++ int i, tc_max; ++ ++ if (!info->attrs[DCB_A_IFNAME] || !info->attrs[DCB_A_PG_CFG]) ++ return -EINVAL; ++ ++ netdev = dev_get_by_name(&init_net, ++ nla_data(info->attrs[DCB_A_IFNAME])); ++ if (!netdev) ++ return -EINVAL; ++ ++ ret = ixgbe_dcb_check_adapter(netdev); ++ if (ret) ++ goto err_out; ++ else ++ adapter = netdev_priv(netdev); ++ ++ ret = nla_parse_nested(pg_tb, IXGBE_DCB_PG_A_MAX, ++ info->attrs[DCB_A_PG_CFG], dcb_pg_nest); ++ if (ret) ++ goto err; ++ ++ dcb_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); ++ if (!dcb_skb) ++ goto err; ++ ++ data = genlmsg_put_reply(dcb_skb, info, &dcb_family, 0, ++ (dir) ? DCB_C_PGRX_GCFG : DCB_C_PGTX_GCFG); ++ ++ if (!data) ++ goto err; ++ ++ pg_nest = nla_nest_start(dcb_skb, DCB_A_PG_CFG); ++ if (!pg_nest) ++ goto err; ++ ++ tc_max = adapter->ring_feature[RING_F_DCB].indices; ++ for (i = PG_A_TC_0; i < tc_max + PG_A_TC_0; i++) { ++ if (!pg_tb[i] && !pg_tb[PG_A_TC_ALL]) ++ continue; ++ ++ if (pg_tb[PG_A_TC_ALL]) ++ tb = pg_tb[PG_A_TC_ALL]; ++ else ++ tb = pg_tb[i]; ++ ret = nla_parse_nested(param_tb, IXGBE_DCB_TC_A_PARAM_MAX, ++ tb, dcb_tc_param_nest); ++ if (ret) ++ goto err_pg; ++ ++ param_nest = nla_nest_start(dcb_skb, i); ++ if (!param_nest) ++ goto err_pg; ++ ++ tc_config = &adapter->dcb_cfg.tc_config[i - PG_A_TC_0]; ++ tc = &adapter->dcb_cfg.tc_config[i - PG_A_TC_0].path[dir]; ++ ++ if (param_tb[TC_A_PARAM_STRICT_PRIO] || ++ param_tb[TC_A_PARAM_ALL]) { ++ ret = nla_put_u8(dcb_skb, TC_A_PARAM_STRICT_PRIO, ++ tc->prio_type); ++ if (ret) ++ goto err_param; ++ } ++ if (param_tb[TC_A_PARAM_BW_GROUP_ID] || ++ param_tb[TC_A_PARAM_ALL]) { ++ ret = nla_put_u8(dcb_skb, TC_A_PARAM_BW_GROUP_ID, ++ tc->bwg_id); ++ if (ret) ++ goto err_param; ++ } ++ if (param_tb[TC_A_PARAM_BW_PCT_IN_GROUP] || ++ param_tb[TC_A_PARAM_ALL]) { ++ ret = nla_put_u8(dcb_skb, TC_A_PARAM_BW_PCT_IN_GROUP, ++ tc->bwg_percent); ++ if (ret) ++ goto err_param; ++ } ++ if (param_tb[TC_A_PARAM_UP_MAPPING] || ++ param_tb[TC_A_PARAM_ALL]) { ++ ret = nla_put_u8(dcb_skb, TC_A_PARAM_UP_MAPPING, ++ tc->up_to_tc_bitmap); ++ if (ret) ++ goto err_param; ++ } ++ nla_nest_end(dcb_skb, param_nest); ++ } ++ ++ for (i = PG_A_BWG_0; i < PG_A_BWG_MAX; i++) { ++ if (!pg_tb[i] && !pg_tb[PG_A_BWG_ALL]) ++ continue; ++ ++ ret = nla_put_u8(dcb_skb, i, ++ adapter->dcb_cfg.bw_percentage[dir][i-PG_A_BWG_0]); ++ ++ if (ret) ++ goto err_pg; ++ } ++ ++ nla_nest_end(dcb_skb, pg_nest); ++ ++ genlmsg_end(dcb_skb, data); ++ ret = genlmsg_reply(dcb_skb, info); ++ if (ret) ++ goto err; ++ ++ dev_put(netdev); ++ return 0; ++ ++err_param: ++ DPRINTK(DRV, ERR, "Error in get pg %s.\n", dir?"rx":"tx"); ++ nla_nest_cancel(dcb_skb, param_nest); ++err_pg: ++ nla_nest_cancel(dcb_skb, pg_nest); ++err: ++ kfree(dcb_skb); ++err_out: ++ dev_put(netdev); ++ return ret; ++} ++ ++static int ixgbe_dcb_pgtx_gcfg(struct sk_buff *skb, struct genl_info *info) ++{ ++ return ixgbe_dcb_pg_gcfg(skb, info, DCB_TX_CONFIG); ++} ++ ++static int ixgbe_dcb_pgrx_gcfg(struct sk_buff *skb, struct genl_info *info) ++{ ++ return ixgbe_dcb_pg_gcfg(skb, info, DCB_RX_CONFIG); ++} ++#endif ++ ++#ifdef CONFIG_DCB + static void ixgbe_dcbnl_set_pfc_cfg(struct net_device *netdev, int priority, + u8 setting) + { +@@ -320,8 +1213,9 @@ + + adapter->temp_dcb_cfg.tc_config[priority].dcb_pfc = setting; + if (adapter->temp_dcb_cfg.tc_config[priority].dcb_pfc != +- adapter->dcb_cfg.tc_config[priority].dcb_pfc) ++ adapter->dcb_cfg.tc_config[priority].dcb_pfc) { + adapter->dcb_set_bitmap |= BIT_PFC; ++ } + } + + static void ixgbe_dcbnl_get_pfc_cfg(struct net_device *netdev, int priority, +@@ -331,37 +1225,271 @@ + + *setting = adapter->dcb_cfg.tc_config[priority].dcb_pfc; + } ++#else ++static int ixgbe_dcb_spfccfg(struct sk_buff *skb, struct genl_info *info) ++{ ++ struct nlattr *tb[IXGBE_DCB_PFC_A_UP_MAX + 1]; ++ struct net_device *netdev = NULL; ++ struct ixgbe_adapter *adapter = NULL; ++ int i, ret = -ENOMEM; ++ u8 setting; ++ u8 changed = 0; + ++ netdev = dev_get_by_name(&init_net, ++ nla_data(info->attrs[DCB_A_IFNAME])); ++ if (!netdev) ++ return -EINVAL; ++ ++ adapter = netdev_priv(netdev); ++ ++ if (!info->attrs[DCB_A_IFNAME] || !info->attrs[DCB_A_PFC_CFG]) ++ return -EINVAL; ++ ++ ret = ixgbe_dcb_check_adapter(netdev); ++ if (ret) ++ goto err; ++ else ++ adapter = netdev_priv(netdev); ++ ++ ret = nla_parse_nested(tb, IXGBE_DCB_PFC_A_UP_MAX, ++ info->attrs[DCB_A_PFC_CFG], ++ dcb_pfc_up_nest); ++ if (ret) ++ goto err; ++ ++ if (!adapter->dcb_set_bitmap && ++ ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, ++ adapter->ring_feature[RING_F_DCB].indices)) { ++ ret = -EINVAL; ++ goto err; ++ } ++ ++ for (i = PFC_A_UP_0; i < PFC_A_UP_MAX; i++) { ++ if (!tb[i]) ++ continue; ++ ++ setting = nla_get_u8(tb[i]); ++ adapter->temp_dcb_cfg.tc_config[i-PFC_A_UP_0].dcb_pfc = setting; ++ ++ if (adapter->temp_dcb_cfg.tc_config[i-PFC_A_UP_0].dcb_pfc != ++ adapter->dcb_cfg.tc_config[i-PFC_A_UP_0].dcb_pfc) ++ changed = 1; ++ } ++ ++ if (changed) ++ adapter->dcb_set_bitmap |= BIT_PFC; ++ ++ ret = ixgbe_nl_reply(0, DCB_C_PFC_SCFG, DCB_A_PFC_CFG, info); ++ if (ret) ++ goto err; ++ ++err: ++ dev_put(netdev); ++ return ret; ++} ++ ++static int ixgbe_dcb_gpfccfg(struct sk_buff *skb, struct genl_info *info) ++{ ++ void *data; ++ struct sk_buff *dcb_skb = NULL; ++ struct nlattr *tb[IXGBE_DCB_PFC_A_UP_MAX + 1], *nest; ++ struct net_device *netdev = NULL; ++ struct ixgbe_adapter *adapter = NULL; ++ int ret = -ENOMEM; ++ int i; ++ ++ if (!info->attrs[DCB_A_IFNAME] || !info->attrs[DCB_A_PFC_CFG]) ++ return -EINVAL; ++ ++ netdev = dev_get_by_name(&init_net, ++ nla_data(info->attrs[DCB_A_IFNAME])); ++ if (!netdev) ++ return -EINVAL; ++ ++ ret = ixgbe_dcb_check_adapter(netdev); ++ if (ret) ++ goto err_out; ++ else ++ adapter = netdev_priv(netdev); ++ ++ ret = nla_parse_nested(tb, IXGBE_DCB_PFC_A_UP_MAX, ++ info->attrs[DCB_A_PFC_CFG], dcb_pfc_up_nest); ++ if (ret) ++ goto err; ++ ++ dcb_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); ++ if (!dcb_skb) ++ goto err; ++ ++ data = genlmsg_put_reply(dcb_skb, info, &dcb_family, 0, ++ DCB_C_PFC_GCFG); ++ if (!data) ++ goto err; ++ ++ nest = nla_nest_start(dcb_skb, DCB_A_PFC_CFG); ++ if (!nest) ++ goto err; ++ ++ for (i = PFC_A_UP_0; i < PFC_A_UP_MAX; i++) { ++ if (!tb[i] && !tb[PFC_A_UP_ALL]) ++ continue; ++ ++ ret = nla_put_u8(dcb_skb, i, ++ adapter->dcb_cfg.tc_config[i-PFC_A_UP_0].dcb_pfc); ++ if (ret) { ++ nla_nest_cancel(dcb_skb, nest); ++ goto err; ++ } ++ } ++ ++ nla_nest_end(dcb_skb, nest); ++ ++ genlmsg_end(dcb_skb, data); ++ ++ ret = genlmsg_reply(dcb_skb, info); ++ if (ret) ++ goto err; ++ ++ dev_put(netdev); ++ return 0; ++ ++err: ++ DPRINTK(DRV, ERR, "Error in get pfc stats.\n"); ++ kfree(dcb_skb); ++err_out: ++ dev_put(netdev); ++ return ret; ++} ++#endif ++ ++#ifdef CONFIG_DCB + static u8 ixgbe_dcbnl_set_all(struct net_device *netdev) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); + int ret; + +- adapter->dcb_set_bitmap &= ~BIT_BCN; /* no set for BCN */ + if (!adapter->dcb_set_bitmap) +- return 1; ++ return DCB_NO_HW_CHG; + +- while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) +- msleep(1); ++ /* Only take down the adapter if the configuration change ++ * requires a reset. ++ */ ++ if (adapter->dcb_set_bitmap & BIT_RESETLINK) { ++ while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) ++ msleep(1); + +- if (netif_running(netdev)) +- ixgbe_down(adapter); ++ if (netif_running(netdev)) ++ ixgbe_down(adapter); ++ } + + ret = ixgbe_copy_dcb_cfg(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, + adapter->ring_feature[RING_F_DCB].indices); + if (ret) { +- clear_bit(__IXGBE_RESETTING, &adapter->state); +- return ret; ++ if (adapter->dcb_set_bitmap & BIT_RESETLINK) ++ clear_bit(__IXGBE_RESETTING, &adapter->state); ++ return DCB_NO_HW_CHG; + } + +- if (netif_running(netdev)) +- ixgbe_up(adapter); ++ if (adapter->dcb_cfg.pfc_mode_enable) { ++ if ((adapter->hw.mac.type != ixgbe_mac_82598EB) && ++ (adapter->hw.fc.current_mode != ixgbe_fc_pfc)) ++ adapter->last_lfc_mode = adapter->hw.fc.current_mode; ++ adapter->hw.fc.requested_mode = ixgbe_fc_pfc; ++ } else { ++ if (adapter->hw.mac.type != ixgbe_mac_82598EB) ++ adapter->hw.fc.requested_mode = adapter->last_lfc_mode; ++ else ++ adapter->hw.fc.requested_mode = ixgbe_fc_none; ++ } + ++ if (adapter->dcb_set_bitmap & BIT_RESETLINK) { ++ if (netif_running(netdev)) ++ ixgbe_up(adapter); ++ ret = DCB_HW_CHG_RST; ++ } else if (adapter->dcb_set_bitmap & BIT_PFC) { ++ if (adapter->hw.mac.type == ixgbe_mac_82598EB) ++ ixgbe_dcb_config_pfc_82598(&adapter->hw, ++ &adapter->dcb_cfg); ++ else if (adapter->hw.mac.type == ixgbe_mac_82599EB) ++ ixgbe_dcb_config_pfc_82599(&adapter->hw, ++ &adapter->dcb_cfg); ++ ret = DCB_HW_CHG; ++ } ++ if (adapter->dcb_cfg.pfc_mode_enable) ++ adapter->hw.fc.current_mode = ixgbe_fc_pfc; ++ ++ if (adapter->dcb_set_bitmap & BIT_RESETLINK) ++ clear_bit(__IXGBE_RESETTING, &adapter->state); + adapter->dcb_set_bitmap = 0x00; +- clear_bit(__IXGBE_RESETTING, &adapter->state); + return ret; + } ++#else ++static int ixgbe_dcb_set_all(struct sk_buff *skb, struct genl_info *info) ++{ ++ struct net_device *netdev = NULL; ++ struct ixgbe_adapter *adapter = NULL; ++ int ret = -ENOMEM; ++ u8 value; ++ u8 retval = 0; + ++ if (!info->attrs[DCB_A_IFNAME] || !info->attrs[DCB_A_SET_ALL]) ++ goto err; ++ ++ netdev = dev_get_by_name(&init_net, ++ nla_data(info->attrs[DCB_A_IFNAME])); ++ if (!netdev) ++ goto err; ++ ++ ret = ixgbe_dcb_check_adapter(netdev); ++ if (ret) ++ goto err_out; ++ else ++ adapter = netdev_priv(netdev); ++ ++ if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) { ++ ret = -EINVAL; ++ goto err_out; ++ } ++ ++ value = nla_get_u8(info->attrs[DCB_A_SET_ALL]); ++ if ((value & 1) != value) { ++ DPRINTK(DRV, ERR, "Value is not 1 or 0, it is %d.\n", value); ++ } else { ++ if (!adapter->dcb_set_bitmap) { ++ retval = 1; ++ goto out; ++ } ++ ++ while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) ++ msleep(1); ++ ++ ret = ixgbe_copy_dcb_cfg(&adapter->temp_dcb_cfg, ++ &adapter->dcb_cfg, ++ adapter->ring_feature[RING_F_DCB].indices); ++ if (ret) { ++ clear_bit(__IXGBE_RESETTING, &adapter->state); ++ goto err_out; ++ } ++ ++ ixgbe_down(adapter); ++ ixgbe_up(adapter); ++ adapter->dcb_set_bitmap = 0x00; ++ clear_bit(__IXGBE_RESETTING, &adapter->state); ++ } ++ ++out: ++ ret = ixgbe_nl_reply(retval, DCB_C_SET_ALL, DCB_A_SET_ALL, info); ++ if (ret) ++ goto err_out; ++ ++err_out: ++ dev_put(netdev); ++err: ++ return ret; ++} ++#endif ++ ++#ifdef CONFIG_DCB + static u8 ixgbe_dcbnl_getcap(struct net_device *netdev, int capid, u8 *cap) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); +@@ -386,9 +1514,6 @@ + break; + case DCB_CAP_ATTR_GSP: + *cap = true; +- break; +- case DCB_CAP_ATTR_BCN: +- *cap = false; + break; + default: + rval = -EINVAL; +@@ -434,183 +1559,24 @@ + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); + +- return !!(adapter->flags & IXGBE_FLAG_DCB_ENABLED); ++ return adapter->dcb_cfg.pfc_mode_enable; + } + + static void ixgbe_dcbnl_setpfcstate(struct net_device *netdev, u8 state) + { ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); ++ ++ adapter->temp_dcb_cfg.pfc_mode_enable = state; ++ if (adapter->temp_dcb_cfg.pfc_mode_enable != ++ adapter->dcb_cfg.pfc_mode_enable) ++ adapter->dcb_set_bitmap |= BIT_PFC; + return; + } + +-static void ixgbe_dcbnl_getbcnrp(struct net_device *netdev, int priority, +- u8 *setting) +-{ +- struct ixgbe_adapter *adapter = netdev_priv(netdev); ++#else ++#endif + +- *setting = adapter->dcb_cfg.bcn.rp_admin_mode[priority]; +-} +- +- +-static void ixgbe_dcbnl_getbcncfg(struct net_device *netdev, int enum_index, +- u32 *setting) +-{ +- struct ixgbe_adapter *adapter = netdev_priv(netdev); +- +- switch (enum_index) { +- case DCB_BCN_ATTR_BCNA_0: +- *setting = adapter->dcb_cfg.bcn.bcna_option[0]; +- break; +- case DCB_BCN_ATTR_BCNA_1: +- *setting = adapter->dcb_cfg.bcn.bcna_option[1]; +- break; +- case DCB_BCN_ATTR_ALPHA: +- *setting = adapter->dcb_cfg.bcn.rp_alpha; +- break; +- case DCB_BCN_ATTR_BETA: +- *setting = adapter->dcb_cfg.bcn.rp_beta; +- break; +- case DCB_BCN_ATTR_GD: +- *setting = adapter->dcb_cfg.bcn.rp_gd; +- break; +- case DCB_BCN_ATTR_GI: +- *setting = adapter->dcb_cfg.bcn.rp_gi; +- break; +- case DCB_BCN_ATTR_TMAX: +- *setting = adapter->dcb_cfg.bcn.rp_tmax; +- break; +- case DCB_BCN_ATTR_TD: +- *setting = adapter->dcb_cfg.bcn.rp_td; +- break; +- case DCB_BCN_ATTR_RMIN: +- *setting = adapter->dcb_cfg.bcn.rp_rmin; +- break; +- case DCB_BCN_ATTR_W: +- *setting = adapter->dcb_cfg.bcn.rp_w; +- break; +- case DCB_BCN_ATTR_RD: +- *setting = adapter->dcb_cfg.bcn.rp_rd; +- break; +- case DCB_BCN_ATTR_RU: +- *setting = adapter->dcb_cfg.bcn.rp_ru; +- break; +- case DCB_BCN_ATTR_WRTT: +- *setting = adapter->dcb_cfg.bcn.rp_wrtt; +- break; +- case DCB_BCN_ATTR_RI: +- *setting = adapter->dcb_cfg.bcn.rp_ri; +- break; +- default: +- *setting = -1; +- } +-} +- +-static void ixgbe_dcbnl_setbcnrp(struct net_device *netdev, int priority, +- u8 setting) +-{ +- struct ixgbe_adapter *adapter = netdev_priv(netdev); +- +- adapter->temp_dcb_cfg.bcn.rp_admin_mode[priority] = setting; +- +- if (adapter->temp_dcb_cfg.bcn.rp_admin_mode[priority] != +- adapter->dcb_cfg.bcn.rp_admin_mode[priority]) +- adapter->dcb_set_bitmap |= BIT_BCN; +-} +- +-static void ixgbe_dcbnl_setbcncfg(struct net_device *netdev, int enum_index, +- u32 setting) +-{ +- struct ixgbe_adapter *adapter = netdev_priv(netdev); +- +- switch (enum_index) { +- case DCB_BCN_ATTR_BCNA_0: +- adapter->temp_dcb_cfg.bcn.bcna_option[0] = setting; +- if (adapter->temp_dcb_cfg.bcn.bcna_option[0] != +- adapter->dcb_cfg.bcn.bcna_option[0]) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- case DCB_BCN_ATTR_BCNA_1: +- adapter->temp_dcb_cfg.bcn.bcna_option[1] = setting; +- if (adapter->temp_dcb_cfg.bcn.bcna_option[1] != +- adapter->dcb_cfg.bcn.bcna_option[1]) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- case DCB_BCN_ATTR_ALPHA: +- adapter->temp_dcb_cfg.bcn.rp_alpha = setting; +- if (adapter->temp_dcb_cfg.bcn.rp_alpha != +- adapter->dcb_cfg.bcn.rp_alpha) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- case DCB_BCN_ATTR_BETA: +- adapter->temp_dcb_cfg.bcn.rp_beta = setting; +- if (adapter->temp_dcb_cfg.bcn.rp_beta != +- adapter->dcb_cfg.bcn.rp_beta) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- case DCB_BCN_ATTR_GD: +- adapter->temp_dcb_cfg.bcn.rp_gd = setting; +- if (adapter->temp_dcb_cfg.bcn.rp_gd != +- adapter->dcb_cfg.bcn.rp_gd) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- case DCB_BCN_ATTR_GI: +- adapter->temp_dcb_cfg.bcn.rp_gi = setting; +- if (adapter->temp_dcb_cfg.bcn.rp_gi != +- adapter->dcb_cfg.bcn.rp_gi) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- case DCB_BCN_ATTR_TMAX: +- adapter->temp_dcb_cfg.bcn.rp_tmax = setting; +- if (adapter->temp_dcb_cfg.bcn.rp_tmax != +- adapter->dcb_cfg.bcn.rp_tmax) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- case DCB_BCN_ATTR_TD: +- adapter->temp_dcb_cfg.bcn.rp_td = setting; +- if (adapter->temp_dcb_cfg.bcn.rp_td != +- adapter->dcb_cfg.bcn.rp_td) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- case DCB_BCN_ATTR_RMIN: +- adapter->temp_dcb_cfg.bcn.rp_rmin = setting; +- if (adapter->temp_dcb_cfg.bcn.rp_rmin != +- adapter->dcb_cfg.bcn.rp_rmin) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- case DCB_BCN_ATTR_W: +- adapter->temp_dcb_cfg.bcn.rp_w = setting; +- if (adapter->temp_dcb_cfg.bcn.rp_w != +- adapter->dcb_cfg.bcn.rp_w) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- case DCB_BCN_ATTR_RD: +- adapter->temp_dcb_cfg.bcn.rp_rd = setting; +- if (adapter->temp_dcb_cfg.bcn.rp_rd != +- adapter->dcb_cfg.bcn.rp_rd) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- case DCB_BCN_ATTR_RU: +- adapter->temp_dcb_cfg.bcn.rp_ru = setting; +- if (adapter->temp_dcb_cfg.bcn.rp_ru != +- adapter->dcb_cfg.bcn.rp_ru) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- case DCB_BCN_ATTR_WRTT: +- adapter->temp_dcb_cfg.bcn.rp_wrtt = setting; +- if (adapter->temp_dcb_cfg.bcn.rp_wrtt != +- adapter->dcb_cfg.bcn.rp_wrtt) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- case DCB_BCN_ATTR_RI: +- adapter->temp_dcb_cfg.bcn.rp_ri = setting; +- if (adapter->temp_dcb_cfg.bcn.rp_ri != +- adapter->dcb_cfg.bcn.rp_ri) +- adapter->dcb_set_bitmap |= BIT_BCN; +- break; +- default: +- break; +- } +-} +- ++#ifdef CONFIG_DCB + struct dcbnl_rtnl_ops dcbnl_ops = { + .getstate = ixgbe_dcbnl_get_state, + .setstate = ixgbe_dcbnl_set_state, +@@ -631,9 +1597,200 @@ + .setnumtcs = ixgbe_dcbnl_setnumtcs, + .getpfcstate = ixgbe_dcbnl_getpfcstate, + .setpfcstate = ixgbe_dcbnl_setpfcstate, +- .getbcncfg = ixgbe_dcbnl_getbcncfg, +- .getbcnrp = ixgbe_dcbnl_getbcnrp, +- .setbcncfg = ixgbe_dcbnl_setbcncfg, +- .setbcnrp = ixgbe_dcbnl_setbcnrp ++}; ++#else ++/* DCB Generic NETLINK command Definitions */ ++/* Get DCB Admin Mode */ ++static struct genl_ops ixgbe_dcb_genl_c_gstate = { ++ .cmd = DCB_C_GSTATE, ++ .flags = GENL_ADMIN_PERM, ++ .policy = dcb_genl_policy, ++ .doit = ixgbe_dcb_gstate, ++ .dumpit = NULL, + }; + ++/* Set DCB Admin Mode */ ++static struct genl_ops ixgbe_dcb_genl_c_sstate = { ++ .cmd = DCB_C_SSTATE, ++ .flags = GENL_ADMIN_PERM, ++ .policy = dcb_genl_policy, ++ .doit = ixgbe_dcb_sstate, ++ .dumpit = NULL, ++}; ++ ++/* Set TX Traffic Attributes */ ++static struct genl_ops ixgbe_dcb_genl_c_spgtx = { ++ .cmd = DCB_C_PGTX_SCFG, ++ .flags = GENL_ADMIN_PERM, ++ .policy = dcb_genl_policy, ++ .doit = ixgbe_dcb_pgtx_scfg, ++ .dumpit = NULL, ++}; ++ ++/* Set RX Traffic Attributes */ ++static struct genl_ops ixgbe_dcb_genl_c_spgrx = { ++ .cmd = DCB_C_PGRX_SCFG, ++ .flags = GENL_ADMIN_PERM, ++ .policy = dcb_genl_policy, ++ .doit = ixgbe_dcb_pgrx_scfg, ++ .dumpit = NULL, ++}; ++ ++/* Set PFC CFG */ ++static struct genl_ops ixgbe_dcb_genl_c_spfc = { ++ .cmd = DCB_C_PFC_SCFG, ++ .flags = GENL_ADMIN_PERM, ++ .policy = dcb_genl_policy, ++ .doit = ixgbe_dcb_spfccfg, ++ .dumpit = NULL, ++}; ++ ++/* Get TX Traffic Attributes */ ++static struct genl_ops ixgbe_dcb_genl_c_gpgtx = { ++ .cmd = DCB_C_PGTX_GCFG, ++ .flags = GENL_ADMIN_PERM, ++ .policy = dcb_genl_policy, ++ .doit = ixgbe_dcb_pgtx_gcfg, ++ .dumpit = NULL, ++}; ++ ++/* Get RX Traffic Attributes */ ++static struct genl_ops ixgbe_dcb_genl_c_gpgrx = { ++ .cmd = DCB_C_PGRX_GCFG, ++ .flags = GENL_ADMIN_PERM, ++ .policy = dcb_genl_policy, ++ .doit = ixgbe_dcb_pgrx_gcfg, ++ .dumpit = NULL, ++}; ++ ++/* Get PFC CFG */ ++static struct genl_ops ixgbe_dcb_genl_c_gpfc = { ++ .cmd = DCB_C_PFC_GCFG, ++ .flags = GENL_ADMIN_PERM, ++ .policy = dcb_genl_policy, ++ .doit = ixgbe_dcb_gpfccfg, ++ .dumpit = NULL, ++}; ++ ++ ++/* Get Link Speed setting */ ++static struct genl_ops ixgbe_dcb_genl_c_glink_spd = { ++ .cmd = DCB_C_GLINK_SPD, ++ .flags = GENL_ADMIN_PERM, ++ .policy = dcb_genl_policy, ++ .doit = ixgbe_dcb_glink_spd, ++ .dumpit = NULL, ++}; ++ ++/* Set Link Speed setting */ ++static struct genl_ops ixgbe_dcb_genl_c_slink_spd = { ++ .cmd = DCB_C_SLINK_SPD, ++ .flags = GENL_ADMIN_PERM, ++ .policy = dcb_genl_policy, ++ .doit = ixgbe_dcb_slink_spd, ++ .dumpit = NULL, ++}; ++ ++/* Set all "set" feature */ ++static struct genl_ops ixgbe_dcb_genl_c_set_all= { ++ .cmd = DCB_C_SET_ALL, ++ .flags = GENL_ADMIN_PERM, ++ .policy = dcb_genl_policy, ++ .doit = ixgbe_dcb_set_all, ++ .dumpit = NULL, ++}; ++ ++/* Get permanent HW address */ ++static struct genl_ops ixgbe_dcb_genl_c_gperm_hwaddr = { ++ .cmd = DCB_C_GPERM_HWADDR, ++ .flags = GENL_ADMIN_PERM, ++ .policy = dcb_genl_policy, ++ .doit = ixgbe_dcb_gperm_hwaddr, ++ .dumpit = NULL, ++}; ++ ++/** ++ * ixgbe_dcb_netlink_register - Initialize the NETLINK communication channel ++ * ++ * Description: ++ * Call out to the DCB components so they can register their families and ++ * commands with Generic NETLINK mechanism. Return zero on success and ++ * non-zero on failure. ++ * ++ */ ++int ixgbe_dcb_netlink_register(void) ++{ ++ int ret = 1; ++ ++ /* consider writing as: ++ * ret = genl_register_family(aaa) ++ * || genl_register_ops(bbb, bbb) ++ * || genl_register_ops(ccc, ccc); ++ * if (ret) ++ * goto err; ++ */ ++ ret = genl_register_family(&dcb_family); ++ if (ret) ++ return ret; ++ ++ ret = genl_register_ops(&dcb_family, &ixgbe_dcb_genl_c_gstate); ++ if (ret) ++ goto err; ++ ++ ret = genl_register_ops(&dcb_family, &ixgbe_dcb_genl_c_sstate); ++ if (ret) ++ goto err; ++ ++ ret = genl_register_ops(&dcb_family, &ixgbe_dcb_genl_c_spgtx); ++ if (ret) ++ goto err; ++ ++ ret = genl_register_ops(&dcb_family, &ixgbe_dcb_genl_c_spgrx); ++ if (ret) ++ goto err; ++ ++ ret = genl_register_ops(&dcb_family, &ixgbe_dcb_genl_c_spfc); ++ if (ret) ++ goto err; ++ ++ ret = genl_register_ops(&dcb_family, &ixgbe_dcb_genl_c_gpfc); ++ if (ret) ++ goto err; ++ ++ ret = genl_register_ops(&dcb_family, &ixgbe_dcb_genl_c_gpgtx); ++ if (ret) ++ goto err; ++ ++ ret = genl_register_ops(&dcb_family, &ixgbe_dcb_genl_c_gpgrx); ++ if (ret) ++ goto err; ++ ++ ++ ret = genl_register_ops(&dcb_family, &ixgbe_dcb_genl_c_glink_spd); ++ if (ret) ++ goto err; ++ ++ ret = genl_register_ops(&dcb_family, &ixgbe_dcb_genl_c_slink_spd); ++ if (ret) ++ goto err; ++ ++ ret = genl_register_ops(&dcb_family, &ixgbe_dcb_genl_c_set_all); ++ if (ret) ++ goto err; ++ ++ ret = genl_register_ops(&dcb_family, &ixgbe_dcb_genl_c_gperm_hwaddr); ++ if (ret) ++ goto err; ++ ++ return 0; ++ ++err: ++ genl_unregister_family(&dcb_family); ++ return ret; ++} ++ ++int ixgbe_dcb_netlink_unregister(void) ++{ ++ return genl_unregister_family(&dcb_family); ++} ++#endif +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_ethtool.c +--- a/drivers/net/ixgbe/ixgbe_ethtool.c Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe_ethtool.c Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -33,13 +33,21 @@ + #include + #include + #include +-#include ++#ifdef SIOCETHTOOL ++#include + + #include "ixgbe.h" + ++#ifndef ETH_GSTRING_LEN ++#define ETH_GSTRING_LEN 32 ++#endif + + #define IXGBE_ALL_RAR_ENTRIES 16 + ++#ifdef ETHTOOL_OPS_COMPAT ++#include "kcompat_ethtool.c" ++#endif ++#ifdef ETHTOOL_GSTATS + struct ixgbe_stats { + char stat_string[ETH_GSTRING_LEN]; + int sizeof_stat; +@@ -47,7 +55,7 @@ + }; + + #define IXGBE_STAT(m) sizeof(((struct ixgbe_adapter *)0)->m), \ +- offsetof(struct ixgbe_adapter, m) ++ offsetof(struct ixgbe_adapter, m) + static struct ixgbe_stats ixgbe_gstrings_stats[] = { + {"rx_packets", IXGBE_STAT(net_stats.rx_packets)}, + {"tx_packets", IXGBE_STAT(net_stats.tx_packets)}, +@@ -59,6 +67,9 @@ + {"rx_errors", IXGBE_STAT(net_stats.rx_errors)}, + {"tx_errors", IXGBE_STAT(net_stats.tx_errors)}, + {"rx_dropped", IXGBE_STAT(net_stats.rx_dropped)}, ++#ifndef CONFIG_IXGBE_NAPI ++ {"rx_dropped_backlog", IXGBE_STAT(rx_dropped_backlog)}, ++#endif + {"tx_dropped", IXGBE_STAT(net_stats.tx_dropped)}, + {"multicast", IXGBE_STAT(net_stats.multicast)}, + {"broadcast", IXGBE_STAT(stats.bprc)}, +@@ -77,8 +88,12 @@ + {"tx_restart_queue", IXGBE_STAT(restart_queue)}, + {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, + {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, ++#ifdef NETIF_F_TSO + {"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)}, ++#ifdef NETIF_F_TSO6 + {"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)}, ++#endif ++#endif + {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, + {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, + {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, +@@ -86,31 +101,48 @@ + {"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)}, + {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, + {"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)}, +- {"rx_header_split", IXGBE_STAT(rx_hdr_split)}, ++#ifndef IXGBE_NO_LLI ++ {"low_latency_interrupt", IXGBE_STAT(lli_int)}, ++#endif + {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, + {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, +-#ifdef CONFIG_IXGBE_LRO +- {"lro_aggregated", IXGBE_STAT(lro_aggregated)}, +- {"lro_flushed", IXGBE_STAT(lro_flushed)}, ++#ifndef IXGBE_NO_LRO ++ {"lro_aggregated", IXGBE_STAT(lro_stats.coal)}, ++ {"lro_flushed", IXGBE_STAT(lro_stats.flushed)}, ++ {"lro_recycled", IXGBE_STAT(lro_stats.recycled)}, ++#endif /* IXGBE_NO_LRO */ ++ {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, ++#ifndef IXGBE_NO_HW_RSC ++ {"hw_rsc_count", IXGBE_STAT(rsc_count)}, + #endif ++ {"rx_flm", IXGBE_STAT(flm)}, ++ {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, ++ {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, + }; + + #define IXGBE_QUEUE_STATS_LEN \ +- ((((struct ixgbe_adapter *)netdev->priv)->num_tx_queues + \ +- ((struct ixgbe_adapter *)netdev->priv)->num_rx_queues) * \ +- (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) +-#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) ++ ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \ ++ ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \ ++ (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) + #define IXGBE_PB_STATS_LEN ( \ +- (((struct ixgbe_adapter *)netdev->priv)->flags & \ +- IXGBE_FLAG_DCB_ENABLED) ? \ +- (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ +- sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ +- sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ +- sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ +- / sizeof(u64) : 0) +-#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ +- IXGBE_PB_STATS_LEN + \ +- IXGBE_QUEUE_STATS_LEN) ++ (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \ ++ IXGBE_FLAG_DCB_ENABLED) ? \ ++ (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ ++ sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ ++ sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ ++ sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ ++ / sizeof(u64) : 0) ++#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + IXGBE_PB_STATS_LEN + IXGBE_QUEUE_STATS_LEN) ++#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) ++#endif /* ETHTOOL_GSTATS */ ++#ifdef ETHTOOL_TEST ++static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { ++ "Register test (offline)", "Eeprom test (offline)", ++ "Interrupt test (offline)", "Loopback test (offline)", ++ "Link test (on/offline)" ++}; ++#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN ++#endif /* ETHTOOL_TEST */ + + static int ixgbe_get_settings(struct net_device *netdev, + struct ethtool_cmd *ecmd) +@@ -123,17 +155,55 @@ + ecmd->supported = SUPPORTED_10000baseT_Full; + ecmd->autoneg = AUTONEG_ENABLE; + ecmd->transceiver = XCVR_EXTERNAL; +- if (hw->phy.media_type == ixgbe_media_type_copper) { ++ if ((hw->phy.media_type == ixgbe_media_type_copper) || ++ (hw->phy.multispeed_fiber)) { + ecmd->supported |= (SUPPORTED_1000baseT_Full | +- SUPPORTED_TP | SUPPORTED_Autoneg); ++ SUPPORTED_Autoneg); + +- ecmd->advertising = (ADVERTISED_TP | ADVERTISED_Autoneg); ++ ecmd->advertising = ADVERTISED_Autoneg; + if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) + ecmd->advertising |= ADVERTISED_10000baseT_Full; + if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) + ecmd->advertising |= ADVERTISED_1000baseT_Full; ++ /* ++ * It's possible that phy.autoneg_advertised may not be ++ * set yet. If so display what the default would be - ++ * both 1G and 10G supported. ++ */ ++ if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full | ++ ADVERTISED_10000baseT_Full))) ++ ecmd->advertising |= (ADVERTISED_10000baseT_Full | ++ ADVERTISED_1000baseT_Full); + +- ecmd->port = PORT_TP; ++ if (hw->phy.media_type == ixgbe_media_type_copper) { ++ ecmd->supported |= SUPPORTED_TP; ++ ecmd->advertising |= ADVERTISED_TP; ++ ecmd->port = PORT_TP; ++ } else { ++ ecmd->supported |= SUPPORTED_FIBRE; ++ ecmd->advertising |= ADVERTISED_FIBRE; ++ ecmd->port = PORT_FIBRE; ++ } ++ } else if (hw->phy.media_type == ixgbe_media_type_backplane) { ++ /* Set as FIBRE until SERDES defined in kernel */ ++ switch (hw->device_id) { ++ case IXGBE_DEV_ID_82598: ++ ecmd->supported |= (SUPPORTED_1000baseT_Full | ++ SUPPORTED_FIBRE); ++ ecmd->advertising = (ADVERTISED_10000baseT_Full | ++ ADVERTISED_1000baseT_Full | ++ ADVERTISED_FIBRE); ++ ecmd->port = PORT_FIBRE; ++ break; ++ case IXGBE_DEV_ID_82598_BX: ++ ecmd->supported = (SUPPORTED_1000baseT_Full | ++ SUPPORTED_FIBRE); ++ ecmd->advertising = (ADVERTISED_1000baseT_Full | ++ ADVERTISED_FIBRE); ++ ecmd->port = PORT_FIBRE; ++ ecmd->autoneg = AUTONEG_DISABLE; ++ break; ++ } + } else { + ecmd->supported |= SUPPORTED_FIBRE; + ecmd->advertising = (ADVERTISED_10000baseT_Full | +@@ -142,7 +212,17 @@ + ecmd->autoneg = AUTONEG_DISABLE; + } + +- hw->mac.ops.check_link(hw, &link_speed, &link_up, false); ++ if (!in_interrupt()) { ++ hw->mac.ops.check_link(hw, &link_speed, &link_up, false); ++ } else { ++ /* ++ * this case is a special workaround for RHEL5 bonding ++ * that calls this routine from interrupt context ++ */ ++ link_speed = adapter->link_speed; ++ link_up = adapter->link_up; ++ } ++ + if (link_up) { + ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ? + SPEED_10000 : SPEED_1000; +@@ -161,16 +241,10 @@ + struct ixgbe_adapter *adapter = netdev_priv(netdev); + struct ixgbe_hw *hw = &adapter->hw; + u32 advertised, old; +- s32 err; ++ s32 err = 0; + +- switch (hw->phy.media_type) { +- case ixgbe_media_type_fiber: +- if ((ecmd->autoneg == AUTONEG_ENABLE) || +- (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL)) +- return -EINVAL; +- /* in this case we currently only support 10Gb/FULL */ +- break; +- case ixgbe_media_type_copper: ++ if ((hw->phy.media_type == ixgbe_media_type_copper) || ++ (hw->phy.multispeed_fiber)) { + /* 10000/copper and 1000/copper must autoneg + * this function does not support any duplex forcing, but can + * limit the advertising of the adapter to only 10000 or 1000 */ +@@ -186,20 +260,24 @@ + advertised |= IXGBE_LINK_SPEED_1GB_FULL; + + if (old == advertised) +- break; ++ return err; + /* this sets the link speed and restarts auto-neg */ ++ hw->mac.autotry_restart = true; + err = hw->mac.ops.setup_link_speed(hw, advertised, true, true); + if (err) { + DPRINTK(PROBE, INFO, + "setup link failed with code %d\n", err); + hw->mac.ops.setup_link_speed(hw, old, true, true); + } +- break; +- default: +- break; ++ } else { ++ /* in this case we currently only support 10Gb/FULL */ ++ if ((ecmd->autoneg == AUTONEG_ENABLE) || ++ (ecmd->advertising != ADVERTISED_10000baseT_Full) || ++ (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL)) ++ return -EINVAL; + } + +- return 0; ++ return err; + } + + static void ixgbe_get_pauseparam(struct net_device *netdev, +@@ -208,13 +286,29 @@ + struct ixgbe_adapter *adapter = netdev_priv(netdev); + struct ixgbe_hw *hw = &adapter->hw; + +- pause->autoneg = (hw->fc.type == ixgbe_fc_full ? 1 : 0); ++ /* ++ * Flow Control Autoneg isn't on if ++ * - we didn't ask for it OR ++ * - it failed, we know this by tx & rx being off ++ */ ++ if (hw->fc.disable_fc_autoneg || (hw->fc.current_mode == ixgbe_fc_none)) ++ pause->autoneg = 0; ++ else ++ pause->autoneg = 1; + +- if (hw->fc.type == ixgbe_fc_rx_pause) { ++#ifdef CONFIG_DCB ++ if (hw->fc.current_mode == ixgbe_fc_pfc) { ++ pause->rx_pause = 0; ++ pause->tx_pause = 0; ++ return; ++ } ++#endif ++ ++ if (hw->fc.current_mode == ixgbe_fc_rx_pause) { + pause->rx_pause = 1; +- } else if (hw->fc.type == ixgbe_fc_tx_pause) { ++ } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { + pause->tx_pause = 1; +- } else if (hw->fc.type == ixgbe_fc_full) { ++ } else if (hw->fc.current_mode == ixgbe_fc_full) { + pause->rx_pause = 1; + pause->tx_pause = 1; + } +@@ -225,25 +319,41 @@ + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); + struct ixgbe_hw *hw = &adapter->hw; ++ struct ixgbe_fc_info fc; + +- if ((pause->autoneg == AUTONEG_ENABLE) || +- (pause->rx_pause && pause->tx_pause)) +- hw->fc.type = ixgbe_fc_full; ++ if (adapter->dcb_cfg.pfc_mode_enable || ++ ((hw->mac.type == ixgbe_mac_82598EB) && ++ (adapter->flags & IXGBE_FLAG_DCB_ENABLED))) ++ return -EINVAL; ++ ++ fc = hw->fc; ++ ++ if (pause->autoneg != AUTONEG_ENABLE) ++ fc.disable_fc_autoneg = true; ++ else ++ fc.disable_fc_autoneg = false; ++ ++ if (pause->rx_pause && pause->tx_pause) ++ fc.requested_mode = ixgbe_fc_full; + else if (pause->rx_pause && !pause->tx_pause) +- hw->fc.type = ixgbe_fc_rx_pause; ++ fc.requested_mode = ixgbe_fc_rx_pause; + else if (!pause->rx_pause && pause->tx_pause) +- hw->fc.type = ixgbe_fc_tx_pause; ++ fc.requested_mode = ixgbe_fc_tx_pause; + else if (!pause->rx_pause && !pause->tx_pause) +- hw->fc.type = ixgbe_fc_none; ++ fc.requested_mode = ixgbe_fc_none; + else + return -EINVAL; + +- hw->fc.original_type = hw->fc.type; ++ adapter->last_lfc_mode = fc.requested_mode; + +- if (netif_running(netdev)) +- ixgbe_reinit_locked(adapter); +- else +- ixgbe_reset(adapter); ++ /* if the thing changed then we'll update and use new autoneg */ ++ if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { ++ hw->fc = fc; ++ if (netif_running(netdev)) ++ ixgbe_reinit_locked(adapter); ++ else ++ ixgbe_reset(adapter); ++ } + + return 0; + } +@@ -278,26 +388,62 @@ + static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data) + { + if (data) ++#ifdef NETIF_F_IPV6_CSUM + netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); + else + netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); ++#else ++ netdev->features |= NETIF_F_IP_CSUM; ++ else ++ netdev->features &= ~NETIF_F_IP_CSUM; ++#endif + + return 0; + } + ++#ifdef NETIF_F_TSO + static int ixgbe_set_tso(struct net_device *netdev, u32 data) + { ++#ifndef HAVE_NETDEV_VLAN_FEATURES ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); ++#endif /* HAVE_NETDEV_VLAN_FEATURES */ + if (data) { + netdev->features |= NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 + netdev->features |= NETIF_F_TSO6; ++#endif + } else { + netif_tx_stop_all_queues(netdev); + netdev->features &= ~NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 + netdev->features &= ~NETIF_F_TSO6; ++#endif ++#ifndef HAVE_NETDEV_VLAN_FEATURES ++#ifdef NETIF_F_HW_VLAN_TX ++ /* disable TSO on all VLANs if they're present */ ++ if (adapter->vlgrp) { ++ int i; ++ struct net_device *v_netdev; ++ for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) { ++ v_netdev = ++ vlan_group_get_device(adapter->vlgrp, i); ++ if (v_netdev) { ++ v_netdev->features &= ~NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 ++ v_netdev->features &= ~NETIF_F_TSO6; ++#endif ++ vlan_group_set_device(adapter->vlgrp, i, ++ v_netdev); ++ } ++ } ++ } ++#endif ++#endif /* HAVE_NETDEV_VLAN_FEATURES */ + netif_tx_start_all_queues(netdev); + } + return 0; + } ++#endif /* NETIF_F_TSO */ + + static u32 ixgbe_get_msglevel(struct net_device *netdev) + { +@@ -319,8 +465,8 @@ + + #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ + +-static void ixgbe_get_regs(struct net_device *netdev, +- struct ethtool_regs *regs, void *p) ++static void ixgbe_get_regs(struct net_device *netdev, struct ethtool_regs *regs, ++ void *p) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); + struct ixgbe_hw *hw = &adapter->hw; +@@ -376,9 +522,15 @@ + regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2)); + regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3)); + for (i = 0; i < 8; i++) +- regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); ++ if (hw->mac.type == ixgbe_mac_82599EB) ++ regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); ++ else ++ regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); + for (i = 0; i < 8; i++) +- regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); ++ if (hw->mac.type == ixgbe_mac_82599EB) ++ regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); ++ else ++ regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); + regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); + regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); + +@@ -458,8 +610,9 @@ + regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); + regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); + regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); +- regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT); ++ regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); + ++ /* DCB */ + regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); + regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); + regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); +@@ -644,8 +797,8 @@ + return -ENOMEM; + + for (i = 0; i < eeprom_len; i++) { +- if ((ret_val = hw->eeprom.ops.read(hw, first_word + i, +- &eeprom_buff[i]))) ++ if ((ret_val = ixgbe_read_eeprom(hw, first_word + i, ++ &eeprom_buff[i]))) + break; + } + +@@ -659,16 +812,79 @@ + return ret_val; + } + ++static int ixgbe_set_eeprom(struct net_device *netdev, ++ struct ethtool_eeprom *eeprom, u8 *bytes) ++{ ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); ++ struct ixgbe_hw *hw = &adapter->hw; ++ u16 *eeprom_buff; ++ void *ptr; ++ int max_len, first_word, last_word, ret_val = 0; ++ u16 i; ++ ++ if (eeprom->len == 0) ++ return -EOPNOTSUPP; ++ ++ if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) ++ return -EFAULT; ++ ++ max_len = hw->eeprom.word_size * 2; ++ ++ first_word = eeprom->offset >> 1; ++ last_word = (eeprom->offset + eeprom->len - 1) >> 1; ++ eeprom_buff = kmalloc(max_len, GFP_KERNEL); ++ if (!eeprom_buff) ++ return -ENOMEM; ++ ++ ptr = (void *)eeprom_buff; ++ ++ if (eeprom->offset & 1) { ++ /* need read/modify/write of first changed EEPROM word */ ++ /* only the second byte of the word is being modified */ ++ ret_val = ixgbe_read_eeprom(hw, first_word, &eeprom_buff[0]); ++ ptr++; ++ } ++ if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { ++ /* need read/modify/write of last changed EEPROM word */ ++ /* only the first byte of the word is being modified */ ++ ret_val = ixgbe_read_eeprom(hw, last_word, ++ &eeprom_buff[last_word - first_word]); ++ } ++ ++ /* Device's eeprom is always little-endian, word addressable */ ++ for (i = 0; i < last_word - first_word + 1; i++) ++ le16_to_cpus(&eeprom_buff[i]); ++ ++ memcpy(ptr, bytes, eeprom->len); ++ ++ for (i = 0; i <= (last_word - first_word); i++) ++ ret_val |= ixgbe_write_eeprom(hw, first_word + i, eeprom_buff[i]); ++ ++ /* Update the checksum */ ++ ixgbe_update_eeprom_checksum(hw); ++ ++ kfree(eeprom_buff); ++ return ret_val; ++} ++ + static void ixgbe_get_drvinfo(struct net_device *netdev, + struct ethtool_drvinfo *drvinfo) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); ++ char firmware_version[32]; + + strncpy(drvinfo->driver, ixgbe_driver_name, 32); + strncpy(drvinfo->version, ixgbe_driver_version, 32); +- strncpy(drvinfo->fw_version, "N/A", 32); ++ ++ sprintf(firmware_version, "%d.%d-%d", ++ (adapter->eeprom_version & 0xF000) >> 12, ++ (adapter->eeprom_version & 0x0FF0) >> 4, ++ adapter->eeprom_version & 0x000F); ++ ++ strncpy(drvinfo->fw_version, firmware_version, 32); + strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); + drvinfo->n_stats = IXGBE_STATS_LEN; ++ drvinfo->testinfo_len = IXGBE_TEST_LEN; + drvinfo->regdump_len = ixgbe_get_regs_len(netdev); + } + +@@ -693,9 +909,10 @@ + struct ethtool_ringparam *ring) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); +- struct ixgbe_ring *temp_ring; ++ struct ixgbe_ring *temp_tx_ring, *temp_rx_ring; + int i, err; + u32 new_rx_count, new_tx_count; ++ bool need_update = false; + + if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) + return -EINVAL; +@@ -714,96 +931,99 @@ + return 0; + } + +- if (adapter->num_tx_queues > adapter->num_rx_queues) +- temp_ring = vmalloc(adapter->num_tx_queues * +- sizeof(struct ixgbe_ring)); +- else +- temp_ring = vmalloc(adapter->num_rx_queues * +- sizeof(struct ixgbe_ring)); +- if (!temp_ring) +- return -ENOMEM; +- + while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) + msleep(1); + +- if (netif_running(netdev)) +- ixgbe_down(adapter); ++ temp_tx_ring = kcalloc(adapter->num_tx_queues, ++ sizeof(struct ixgbe_ring), GFP_KERNEL); ++ if (!temp_tx_ring) { ++ err = -ENOMEM; ++ goto err_setup; ++ } + +- /* +- * We can't just free everything and then setup again, +- * because the ISRs in MSI-X mode get passed pointers +- * to the tx and rx ring structs. +- */ +- if (new_tx_count != adapter->tx_ring->count) { +- memcpy(temp_ring, adapter->tx_ring, ++ if (new_tx_count != adapter->tx_ring_count) { ++ memcpy(temp_tx_ring, adapter->tx_ring, + adapter->num_tx_queues * sizeof(struct ixgbe_ring)); +- + for (i = 0; i < adapter->num_tx_queues; i++) { +- temp_ring[i].count = new_tx_count; +- err = ixgbe_setup_tx_resources(adapter, &temp_ring[i]); ++ temp_tx_ring[i].count = new_tx_count; ++ err = ixgbe_setup_tx_resources(adapter, ++ &temp_tx_ring[i]); + if (err) { + while (i) { + i--; + ixgbe_free_tx_resources(adapter, +- &temp_ring[i]); ++ &temp_tx_ring[i]); + } + goto err_setup; + } + } +- +- for (i = 0; i < adapter->num_tx_queues; i++) +- ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); +- +- memcpy(adapter->tx_ring, temp_ring, +- adapter->num_tx_queues * sizeof(struct ixgbe_ring)); +- +- adapter->tx_ring_count = new_tx_count; ++ need_update = true; + } + +- if (new_rx_count != adapter->rx_ring->count) { +- memcpy(temp_ring, adapter->rx_ring, ++ temp_rx_ring = kcalloc(adapter->num_rx_queues, ++ sizeof(struct ixgbe_ring), GFP_KERNEL); ++ if ((!temp_rx_ring) && (need_update)) { ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ ixgbe_free_tx_resources(adapter, &temp_tx_ring[i]); ++ kfree(temp_tx_ring); ++ err = -ENOMEM; ++ goto err_setup; ++ } ++ ++ if (new_rx_count != adapter->rx_ring_count) { ++ memcpy(temp_rx_ring, adapter->rx_ring, + adapter->num_rx_queues * sizeof(struct ixgbe_ring)); +- + for (i = 0; i < adapter->num_rx_queues; i++) { +- temp_ring[i].count = new_rx_count; +- err = ixgbe_setup_rx_resources(adapter, &temp_ring[i]); ++ temp_rx_ring[i].count = new_rx_count; ++ err = ixgbe_setup_rx_resources(adapter, ++ &temp_rx_ring[i]); + if (err) { + while (i) { + i--; + ixgbe_free_rx_resources(adapter, +- &temp_ring[i]); ++ &temp_rx_ring[i]); + } + goto err_setup; + } + } ++ need_update = true; ++ } + +- for (i = 0; i < adapter->num_rx_queues; i++) +- ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); ++ /* if rings need to be updated, here's the place to do it in one shot */ ++ if (need_update) { ++ if (netif_running(netdev)) ++ ixgbe_down(adapter); + +- memcpy(adapter->rx_ring, temp_ring, +- adapter->num_rx_queues * sizeof(struct ixgbe_ring)); ++ /* tx */ ++ if (new_tx_count != adapter->tx_ring_count) { ++ kfree(adapter->tx_ring); ++ adapter->tx_ring = temp_tx_ring; ++ temp_tx_ring = NULL; ++ adapter->tx_ring_count = new_tx_count; ++ } + +- adapter->rx_ring_count = new_rx_count; ++ /* rx */ ++ if (new_rx_count != adapter->rx_ring_count) { ++ kfree(adapter->rx_ring); ++ adapter->rx_ring = temp_rx_ring; ++ temp_rx_ring = NULL; ++ adapter->rx_ring_count = new_rx_count; ++ } + } + + /* success! */ + err = 0; +-err_setup: + if (netif_running(netdev)) + ixgbe_up(adapter); + ++err_setup: + clear_bit(__IXGBE_RESETTING, &adapter->state); + return err; + } + +-static int ixgbe_get_sset_count(struct net_device *netdev, int sset) ++static int ixgbe_get_stats_count(struct net_device *netdev) + { +- switch (sset) { +- case ETH_SS_STATS: +- return IXGBE_STATS_LEN; +- default: +- return -EOPNOTSUPP; +- } ++ return IXGBE_STATS_LEN; + } + + static void ixgbe_get_ethtool_stats(struct net_device *netdev, +@@ -814,18 +1034,6 @@ + int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64); + int j, k; + int i; +- +-#ifdef CONFIG_IXGBE_LRO +- u64 aggregated = 0, flushed = 0, no_desc = 0; +- for (i = 0; i < adapter->num_rx_queues; i++) { +- aggregated += adapter->rx_ring[i].lro_mgr.stats.aggregated; +- flushed += adapter->rx_ring[i].lro_mgr.stats.flushed; +- no_desc += adapter->rx_ring[i].lro_mgr.stats.no_desc; +- } +- adapter->lro_aggregated = aggregated; +- adapter->lro_flushed = flushed; +- adapter->lro_no_desc = no_desc; +-#endif + + ixgbe_update_stats(adapter); + for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { +@@ -865,6 +1073,10 @@ + int i; + + switch (stringset) { ++ case ETH_SS_TEST: ++ memcpy(data, *ixgbe_gstrings_test, ++ IXGBE_TEST_LEN * ETH_GSTRING_LEN); ++ break; + case ETH_SS_STATS: + for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { + memcpy(p, ixgbe_gstrings_stats[i].stat_string, +@@ -897,19 +1109,904 @@ + p += ETH_GSTRING_LEN; + } + } +- /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ ++/* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ + break; + } + } + ++static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) ++{ ++ struct ixgbe_hw *hw = &adapter->hw; ++ bool link_up; ++ u32 link_speed = 0; ++ *data = 0; ++ ++ hw->mac.ops.check_link(hw, &link_speed, &link_up, true); ++ if (link_up) ++ return *data; ++ else ++ *data = 1; ++ return *data; ++} ++ ++/* ethtool register test data */ ++struct ixgbe_reg_test { ++ u16 reg; ++ u8 array_len; ++ u8 test_type; ++ u32 mask; ++ u32 write; ++}; ++ ++/* In the hardware, registers are laid out either singly, in arrays ++ * spaced 0x40 bytes apart, or in contiguous tables. We assume ++ * most tests take place on arrays or single registers (handled ++ * as a single-element array) and special-case the tables. ++ * Table tests are always pattern tests. ++ * ++ * We also make provision for some required setup steps by specifying ++ * registers to be written without any read-back testing. ++ */ ++ ++#define PATTERN_TEST 1 ++#define SET_READ_TEST 2 ++#define WRITE_NO_TEST 3 ++#define TABLE32_TEST 4 ++#define TABLE64_TEST_LO 5 ++#define TABLE64_TEST_HI 6 ++ ++/* default 82599 register test */ ++static struct ixgbe_reg_test reg_test_82599[] = { ++ { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, ++ { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, ++ { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, ++ { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, ++ { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, ++ { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, ++ { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, ++ { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, ++ { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, ++ { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, ++ { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, ++ { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, ++ { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, ++ { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { 0, 0, 0, 0 } ++}; ++ ++/* default 82598 register test */ ++static struct ixgbe_reg_test reg_test_82598[] = { ++ { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, ++ { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, ++ { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, ++ { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, ++ { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, ++ /* Enable all four RX queues before testing. */ ++ { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, ++ /* RDH is read-only for 82598, only test RDT. */ ++ { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, ++ { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, ++ { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, ++ { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, ++ { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, ++ { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, ++ { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, ++ { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, ++ { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, ++ { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, ++ { 0, 0, 0, 0 } ++}; ++ ++#define REG_PATTERN_TEST(R, M, W) \ ++{ \ ++ u32 pat, val, before; \ ++ const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \ ++ for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \ ++ before = readl(adapter->hw.hw_addr + R); \ ++ writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \ ++ val = readl(adapter->hw.hw_addr + R); \ ++ if (val != (_test[pat] & W & M)) { \ ++ DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\ ++ "0x%08X expected 0x%08X\n", \ ++ R, val, (_test[pat] & W & M)); \ ++ *data = R; \ ++ writel(before, adapter->hw.hw_addr + R); \ ++ return 1; \ ++ } \ ++ writel(before, adapter->hw.hw_addr + R); \ ++ } \ ++} ++ ++#define REG_SET_AND_CHECK(R, M, W) \ ++{ \ ++ u32 val, before; \ ++ before = readl(adapter->hw.hw_addr + R); \ ++ writel((W & M), (adapter->hw.hw_addr + R)); \ ++ val = readl(adapter->hw.hw_addr + R); \ ++ if ((W & M) != (val & M)) { \ ++ DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\ ++ "expected 0x%08X\n", R, (val & M), (W & M)); \ ++ *data = R; \ ++ writel(before, (adapter->hw.hw_addr + R)); \ ++ return 1; \ ++ } \ ++ writel(before, (adapter->hw.hw_addr + R)); \ ++} ++ ++static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) ++{ ++ struct ixgbe_reg_test *test; ++ u32 value, before, after; ++ u32 i, toggle; ++ ++ if (adapter->hw.mac.type == ixgbe_mac_82599EB) { ++ toggle = 0x7FFFF30F; ++ test = reg_test_82599; ++ } else { ++ toggle = 0x7FFFF3FF; ++ test = reg_test_82598; ++ } ++ ++ /* ++ * Because the status register is such a special case, ++ * we handle it separately from the rest of the register ++ * tests. Some bits are read-only, some toggle, and some ++ * are writeable on newer MACs. ++ */ ++ before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS); ++ value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle); ++ after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle; ++ if (value != after) { ++ DPRINTK(DRV, ERR, "failed STATUS register test got: " ++ "0x%08X expected: 0x%08X\n", after, value); ++ *data = 1; ++ return 1; ++ } ++ /* restore previous status */ ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before); ++ ++ /* ++ * Perform the remainder of the register test, looping through ++ * the test table until we either fail or reach the null entry. ++ */ ++ while (test->reg) { ++ for (i = 0; i < test->array_len; i++) { ++ switch (test->test_type) { ++ case PATTERN_TEST: ++ REG_PATTERN_TEST(test->reg + (i * 0x40), ++ test->mask, ++ test->write); ++ break; ++ case SET_READ_TEST: ++ REG_SET_AND_CHECK(test->reg + (i * 0x40), ++ test->mask, ++ test->write); ++ break; ++ case WRITE_NO_TEST: ++ writel(test->write, ++ (adapter->hw.hw_addr + test->reg) ++ + (i * 0x40)); ++ break; ++ case TABLE32_TEST: ++ REG_PATTERN_TEST(test->reg + (i * 4), ++ test->mask, ++ test->write); ++ break; ++ case TABLE64_TEST_LO: ++ REG_PATTERN_TEST(test->reg + (i * 8), ++ test->mask, ++ test->write); ++ break; ++ case TABLE64_TEST_HI: ++ REG_PATTERN_TEST((test->reg + 4) + (i * 8), ++ test->mask, ++ test->write); ++ break; ++ } ++ } ++ test++; ++ } ++ ++ *data = 0; ++ return 0; ++} ++ ++static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) ++{ ++ if (ixgbe_validate_eeprom_checksum(&adapter->hw, NULL)) ++ *data = 1; ++ else ++ *data = 0; ++ return *data; ++} ++ ++static irqreturn_t ixgbe_test_intr(int irq, void *data) ++{ ++ struct net_device *netdev = (struct net_device *) data; ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); ++ ++ adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) ++{ ++ struct net_device *netdev = adapter->netdev; ++ u32 mask, i = 0, shared_int = true; ++ u32 irq = adapter->pdev->irq; ++ ++ *data = 0; ++ ++ /* Hook up test interrupt handler just for this test */ ++ if (adapter->msix_entries) { ++ /* NOTE: we don't test MSI-X interrupts here, yet */ ++ return 0; ++ } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { ++ shared_int = false; ++ if (request_irq(irq, &ixgbe_test_intr, 0, netdev->name, ++ netdev)) { ++ *data = 1; ++ return -1; ++ } ++ } else if (!request_irq(irq, &ixgbe_test_intr, IRQF_PROBE_SHARED, ++ netdev->name, netdev)) { ++ shared_int = false; ++ } else if (request_irq(irq, &ixgbe_test_intr, IRQF_SHARED, ++ netdev->name, netdev)) { ++ *data = 1; ++ return -1; ++ } ++ DPRINTK(HW, INFO, "testing %s interrupt\n", ++ (shared_int ? "shared" : "unshared")); ++ ++ /* Disable all the interrupts */ ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); ++ msleep(10); ++ ++ /* Test each interrupt */ ++ for (; i < 10; i++) { ++ /* Interrupt to test */ ++ mask = 1 << i; ++ ++ if (!shared_int) { ++ /* ++ * Disable the interrupts to be reported in ++ * the cause register and then force the same ++ * interrupt and see if one gets posted. If ++ * an interrupt was posted to the bus, the ++ * test failed. ++ */ ++ adapter->test_icr = 0; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ++ ~mask & 0x00007FFF); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, ++ ~mask & 0x00007FFF); ++ msleep(10); ++ ++ if (adapter->test_icr & mask) { ++ *data = 3; ++ break; ++ } ++ } ++ ++ /* ++ * Enable the interrupt to be reported in the cause ++ * register and then force the same interrupt and see ++ * if one gets posted. If an interrupt was not posted ++ * to the bus, the test failed. ++ */ ++ adapter->test_icr = 0; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); ++ msleep(10); ++ ++ if (!(adapter->test_icr &mask)) { ++ *data = 4; ++ break; ++ } ++ ++ if (!shared_int) { ++ /* ++ * Disable the other interrupts to be reported in ++ * the cause register and then force the other ++ * interrupts and see if any get posted. If ++ * an interrupt was posted to the bus, the ++ * test failed. ++ */ ++ adapter->test_icr = 0; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ++ ~mask & 0x00007FFF); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, ++ ~mask & 0x00007FFF); ++ msleep(10); ++ ++ if (adapter->test_icr) { ++ *data = 5; ++ break; ++ } ++ } ++ } ++ ++ /* Disable all the interrupts */ ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); ++ msleep(10); ++ ++ /* Unhook test interrupt handler */ ++ free_irq(irq, netdev); ++ ++ return *data; ++} ++ ++static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) ++{ ++ struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; ++ struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; ++ struct ixgbe_hw *hw = &adapter->hw; ++ struct pci_dev *pdev = adapter->pdev; ++ u32 reg_ctl; ++ int i; ++ ++ /* shut down the DMA engines now so they can be reinitialized later */ ++ ++ /* first Rx */ ++ reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); ++ reg_ctl &= ~IXGBE_RXCTRL_RXEN; ++ IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl); ++ reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0)); ++ reg_ctl &= ~IXGBE_RXDCTL_ENABLE; ++ IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl); ++ ++ /* now Tx */ ++ reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0)); ++ reg_ctl &= ~IXGBE_TXDCTL_ENABLE; ++ IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl); ++ if (hw->mac.type == ixgbe_mac_82599EB) { ++ reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); ++ reg_ctl &= ~IXGBE_DMATXCTL_TE; ++ IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl); ++ } ++ ++ ixgbe_reset(adapter); ++ ++ if (tx_ring->desc && tx_ring->tx_buffer_info) { ++ for (i = 0; i < tx_ring->count; i++) { ++ struct ixgbe_tx_buffer *buf = ++ &(tx_ring->tx_buffer_info[i]); ++ if (buf->dma) { ++ pci_unmap_single(pdev, buf->dma, buf->length, ++ PCI_DMA_TODEVICE); ++ buf->dma = 0; ++ } ++ if (buf->skb) ++ dev_kfree_skb(buf->skb); ++ } ++ } ++ ++ if (rx_ring->desc && rx_ring->rx_buffer_info) { ++ for (i = 0; i < rx_ring->count; i++) { ++ struct ixgbe_rx_buffer *buf = ++ &(rx_ring->rx_buffer_info[i]); ++ if (buf->dma) { ++ pci_unmap_single(pdev, buf->dma, ++ IXGBE_RXBUFFER_2048, ++ PCI_DMA_FROMDEVICE); ++ buf->dma = 0; ++ } ++ if (buf->skb) ++ dev_kfree_skb(buf->skb); ++ } ++ } ++ ++ if (tx_ring->desc) { ++ pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, ++ tx_ring->dma); ++ tx_ring->desc = NULL; ++ } ++ if (rx_ring->desc) { ++ pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, ++ rx_ring->dma); ++ rx_ring->desc = NULL; ++ } ++ ++ kfree(tx_ring->tx_buffer_info); ++ tx_ring->tx_buffer_info = NULL; ++ kfree(rx_ring->rx_buffer_info); ++ rx_ring->rx_buffer_info = NULL; ++ ++ return; ++} ++ ++static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) ++{ ++ struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; ++ struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; ++ struct pci_dev *pdev = adapter->pdev; ++ u32 rctl, reg_data; ++ int i, ret_val; ++ ++ /* Setup Tx descriptor ring and Tx buffers */ ++ ++ if (!tx_ring->count) ++ tx_ring->count = IXGBE_DEFAULT_TXD; ++ ++ tx_ring->tx_buffer_info = kcalloc(tx_ring->count, ++ sizeof(struct ixgbe_tx_buffer), ++ GFP_KERNEL); ++ if (!(tx_ring->tx_buffer_info)) { ++ ret_val = 1; ++ goto err_nomem; ++ } ++ ++ tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); ++ tx_ring->size = ALIGN(tx_ring->size, 4096); ++ if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, ++ &tx_ring->dma))) { ++ ret_val = 2; ++ goto err_nomem; ++ } ++ tx_ring->next_to_use = tx_ring->next_to_clean = 0; ++ ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0), ++ ((u64) tx_ring->dma & 0x00000000FFFFFFFF)); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0), ++ ((u64) tx_ring->dma >> 32)); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0), ++ tx_ring->count * sizeof(union ixgbe_adv_tx_desc)); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0); ++ ++ reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); ++ reg_data |= IXGBE_HLREG0_TXPADEN; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); ++ ++ if (adapter->hw.mac.type == ixgbe_mac_82599EB) { ++ reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); ++ reg_data |= IXGBE_DMATXCTL_TE; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); ++ } ++ reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0)); ++ reg_data |= IXGBE_TXDCTL_ENABLE; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data); ++ ++ for (i = 0; i < tx_ring->count; i++) { ++ union ixgbe_adv_tx_desc *desc = IXGBE_TX_DESC_ADV(*tx_ring, i); ++ struct sk_buff *skb; ++ unsigned int size = 1024; ++ ++ skb = alloc_skb(size, GFP_KERNEL); ++ if (!skb) { ++ ret_val = 3; ++ goto err_nomem; ++ } ++ skb_put(skb, size); ++ tx_ring->tx_buffer_info[i].skb = skb; ++ tx_ring->tx_buffer_info[i].length = skb->len; ++ tx_ring->tx_buffer_info[i].dma = ++ pci_map_single(pdev, skb->data, skb->len, PCI_DMA_TODEVICE); ++ desc->read.buffer_addr = cpu_to_le64(tx_ring->tx_buffer_info[i].dma); ++ desc->read.cmd_type_len = cpu_to_le32(skb->len); ++ desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_EOP | ++ IXGBE_TXD_CMD_IFCS | ++ IXGBE_TXD_CMD_RS); ++ desc->read.olinfo_status = 0; ++ if (adapter->hw.mac.type == ixgbe_mac_82599EB) ++ desc->read.olinfo_status |= ++ (skb->len << IXGBE_ADVTXD_PAYLEN_SHIFT); ++ } ++ ++ /* Setup Rx Descriptor ring and Rx buffers */ ++ ++ if (!rx_ring->count) ++ rx_ring->count = IXGBE_DEFAULT_RXD; ++ ++ rx_ring->rx_buffer_info = kcalloc(rx_ring->count, ++ sizeof(struct ixgbe_rx_buffer), ++ GFP_KERNEL); ++ if (!(rx_ring->rx_buffer_info)) { ++ ret_val = 4; ++ goto err_nomem; ++ } ++ ++ rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); ++ rx_ring->size = ALIGN(rx_ring->size, 4096); ++ if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, ++ &rx_ring->dma))) { ++ ret_val = 5; ++ goto err_nomem; ++ } ++ rx_ring->next_to_use = rx_ring->next_to_clean = 0; ++ ++ rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0), ++ ((u64)rx_ring->dma & 0xFFFFFFFF)); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0), ++ ((u64) rx_ring->dma >> 32)); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0); ++ ++ reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); ++ reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data); ++ ++ reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); ++ reg_data &= ~IXGBE_HLREG0_LPBK; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); ++ ++ reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL); ++#define IXGBE_RDRXCTL_RDMTS_MASK 0x00000003 /* Receive Descriptor Minimum ++ Threshold Size mask */ ++ reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data); ++ ++ reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL); ++#define IXGBE_MCSTCTRL_MO_MASK 0x00000003 /* Multicast Offset mask */ ++ reg_data &= ~IXGBE_MCSTCTRL_MO_MASK; ++ reg_data |= adapter->hw.mac.mc_filter_type; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data); ++ ++ reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0)); ++ reg_data |= IXGBE_RXDCTL_ENABLE; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data); ++ if (adapter->hw.mac.type == ixgbe_mac_82599EB) { ++ int j = adapter->rx_ring[0].reg_idx; ++ u32 k; ++ for (k = 0; k < 10; k++) { ++ if (IXGBE_READ_REG(&adapter->hw, ++ IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) ++ break; ++ else ++ msleep(1); ++ } ++ } ++ ++ rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); ++ ++ for (i = 0; i < rx_ring->count; i++) { ++ union ixgbe_adv_rx_desc *rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); ++ struct sk_buff *skb; ++ ++ skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL); ++ if (!skb) { ++ ret_val = 6; ++ goto err_nomem; ++ } ++ skb_reserve(skb, NET_IP_ALIGN); ++ rx_ring->rx_buffer_info[i].skb = skb; ++ rx_ring->rx_buffer_info[i].dma = ++ pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048, ++ PCI_DMA_FROMDEVICE); ++ rx_desc->read.pkt_addr = ++ cpu_to_le64(rx_ring->rx_buffer_info[i].dma); ++ memset(skb->data, 0x00, skb->len); ++ } ++ ++ return 0; ++ ++err_nomem: ++ ixgbe_free_desc_rings(adapter); ++ return ret_val; ++} ++ ++static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) ++{ ++ struct ixgbe_hw *hw = &adapter->hw; ++ u32 reg_data; ++ ++ /* right now we only support MAC loopback in the driver */ ++ ++ /* Setup MAC loopback */ ++ reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); ++ reg_data |= IXGBE_HLREG0_LPBK; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); ++ ++ reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC); ++ reg_data &= ~IXGBE_AUTOC_LMS_MASK; ++ reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data); ++ ++ /* Disable Atlas Tx lanes; re-enabled in reset path */ ++ if (hw->mac.type == ixgbe_mac_82598EB) { ++ u8 atlas; ++ ++ ixgbe_read_analog_reg8(&adapter->hw, ++ IXGBE_ATLAS_PDN_LPBK, &atlas); ++ atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; ++ ixgbe_write_analog_reg8(&adapter->hw, ++ IXGBE_ATLAS_PDN_LPBK, atlas); ++ ++ ixgbe_read_analog_reg8(&adapter->hw, ++ IXGBE_ATLAS_PDN_10G, &atlas); ++ atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; ++ ixgbe_write_analog_reg8(&adapter->hw, ++ IXGBE_ATLAS_PDN_10G, atlas); ++ ++ ixgbe_read_analog_reg8(&adapter->hw, ++ IXGBE_ATLAS_PDN_1G, &atlas); ++ atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; ++ ixgbe_write_analog_reg8(&adapter->hw, ++ IXGBE_ATLAS_PDN_1G, atlas); ++ ++ ixgbe_read_analog_reg8(&adapter->hw, ++ IXGBE_ATLAS_PDN_AN, &atlas); ++ atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; ++ ixgbe_write_analog_reg8(&adapter->hw, ++ IXGBE_ATLAS_PDN_AN, atlas); ++ } ++ ++ return 0; ++} ++ ++static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) ++{ ++ u32 reg_data; ++ ++ reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); ++ reg_data &= ~IXGBE_HLREG0_LPBK; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); ++} ++ ++static void ixgbe_create_lbtest_frame(struct sk_buff *skb, ++ unsigned int frame_size) ++{ ++ memset(skb->data, 0xFF, frame_size); ++ frame_size &= ~1; ++ memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1); ++ memset(&skb->data[frame_size / 2 + 10], 0xBE, 1); ++ memset(&skb->data[frame_size / 2 + 12], 0xAF, 1); ++} ++ ++static int ixgbe_check_lbtest_frame(struct sk_buff *skb, ++ unsigned int frame_size) ++{ ++ frame_size &= ~1; ++ if (*(skb->data + 3) == 0xFF) { ++ if ((*(skb->data + frame_size / 2 + 10) == 0xBE) && ++ (*(skb->data + frame_size / 2 + 12) == 0xAF)) { ++ return 0; ++ } ++ } ++ return 13; ++} ++ ++static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) ++{ ++ struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; ++ struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; ++ struct pci_dev *pdev = adapter->pdev; ++ int i, j, k, l, lc, good_cnt, ret_val = 0; ++ unsigned long time; ++ ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1); ++ ++ /* ++ * Calculate the loop count based on the largest descriptor ring ++ * The idea is to wrap the largest ring a number of times using 64 ++ * send/receive pairs during each loop ++ */ ++ ++ if (rx_ring->count <= tx_ring->count) ++ lc = ((tx_ring->count / 64) * 2) + 1; ++ else ++ lc = ((rx_ring->count / 64) * 2) + 1; ++ ++ k = l = 0; ++ for (j = 0; j <= lc; j++) { ++ for (i = 0; i < 64; i++) { ++ ixgbe_create_lbtest_frame( ++ tx_ring->tx_buffer_info[k].skb, ++ 1024); ++ pci_dma_sync_single_for_device(pdev, ++ tx_ring->tx_buffer_info[k].dma, ++ tx_ring->tx_buffer_info[k].length, ++ PCI_DMA_TODEVICE); ++ if (unlikely(++k == tx_ring->count)) ++ k = 0; ++ } ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k); ++ msleep(200); ++ /* set the start time for the receive */ ++ time = jiffies; ++ good_cnt = 0; ++ do { ++ /* receive the sent packets */ ++ pci_dma_sync_single_for_cpu(pdev, ++ rx_ring->rx_buffer_info[l].dma, ++ IXGBE_RXBUFFER_2048, ++ PCI_DMA_FROMDEVICE); ++ ret_val = ixgbe_check_lbtest_frame( ++ rx_ring->rx_buffer_info[l].skb, 1024); ++ if (!ret_val) ++ good_cnt++; ++ if (++l == rx_ring->count) ++ l = 0; ++ /* ++ * time + 20 msecs (200 msecs on 2.4) is more than ++ * enough time to complete the receives, if it's ++ * exceeded, break and error off ++ */ ++ } while (good_cnt < 64 && jiffies < (time + 20)); ++ if (good_cnt != 64) { ++ /* ret_val is the same as mis-compare */ ++ ret_val = 13; ++ break; ++ } ++ if (jiffies >= (time + 20)) { ++ /* Error code for time out error */ ++ ret_val = 14; ++ break; ++ } ++ } ++ ++ return ret_val; ++} ++ ++static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) ++{ ++ *data = ixgbe_setup_desc_rings(adapter); ++ if (*data) ++ goto out; ++ *data = ixgbe_setup_loopback_test(adapter); ++ if (*data) ++ goto err_loopback; ++ *data = ixgbe_run_loopback_test(adapter); ++ ixgbe_loopback_cleanup(adapter); ++ ++err_loopback: ++ ixgbe_free_desc_rings(adapter); ++out: ++ return *data; ++} ++ ++static int ixgbe_diag_test_count(struct net_device *netdev) ++{ ++ return IXGBE_TEST_LEN; ++} ++ ++static void ixgbe_diag_test(struct net_device *netdev, ++ struct ethtool_test *eth_test, u64 *data) ++{ ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); ++ bool if_running = netif_running(netdev); ++ ++ set_bit(__IXGBE_TESTING, &adapter->state); ++ if (eth_test->flags == ETH_TEST_FL_OFFLINE) { ++ /* Offline tests */ ++ ++ DPRINTK(HW, INFO, "offline testing starting\n"); ++ ++ /* Link test performed before hardware reset so autoneg doesn't ++ * interfere with test result */ ++ if (ixgbe_link_test(adapter, &data[4])) ++ eth_test->flags |= ETH_TEST_FL_FAILED; ++ ++ if (if_running) ++ /* indicate we're in test mode */ ++ dev_close(netdev); ++ else ++ ixgbe_reset(adapter); ++ ++ DPRINTK(HW, INFO, "register testing starting\n"); ++ if (ixgbe_reg_test(adapter, &data[0])) ++ eth_test->flags |= ETH_TEST_FL_FAILED; ++ ++ ixgbe_reset(adapter); ++ DPRINTK(HW, INFO, "eeprom testing starting\n"); ++ if (ixgbe_eeprom_test(adapter, &data[1])) ++ eth_test->flags |= ETH_TEST_FL_FAILED; ++ ++ ixgbe_reset(adapter); ++ DPRINTK(HW, INFO, "interrupt testing starting\n"); ++ if (ixgbe_intr_test(adapter, &data[2])) ++ eth_test->flags |= ETH_TEST_FL_FAILED; ++ ++ ixgbe_reset(adapter); ++ DPRINTK(HW, INFO, "loopback testing starting\n"); ++ if (ixgbe_loopback_test(adapter, &data[3])) ++ eth_test->flags |= ETH_TEST_FL_FAILED; ++ ++ ixgbe_reset(adapter); ++ ++ clear_bit(__IXGBE_TESTING, &adapter->state); ++ if (if_running) ++ dev_open(netdev); ++ } else { ++ DPRINTK(HW, INFO, "online testing starting\n"); ++ /* Online tests */ ++ if (ixgbe_link_test(adapter, &data[4])) ++ eth_test->flags |= ETH_TEST_FL_FAILED; ++ ++ /* Online tests aren't run; pass by default */ ++ data[0] = 0; ++ data[1] = 0; ++ data[2] = 0; ++ data[3] = 0; ++ ++ clear_bit(__IXGBE_TESTING, &adapter->state); ++ } ++ msleep_interruptible(4 * 1000); ++} ++ ++static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, ++ struct ethtool_wolinfo *wol) ++{ ++ struct ixgbe_hw *hw = &adapter->hw; ++ int retval = 1; ++ ++ switch(hw->device_id) { ++ case IXGBE_DEV_ID_82599_KX4: ++ retval = 0; ++ break; ++ default: ++ wol->supported = 0; ++ } ++ ++ return retval; ++} + + static void ixgbe_get_wol(struct net_device *netdev, + struct ethtool_wolinfo *wol) + { +- wol->supported = 0; ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); ++ ++ wol->supported = WAKE_UCAST | WAKE_MCAST | ++ WAKE_BCAST | WAKE_MAGIC; + wol->wolopts = 0; + ++ if (ixgbe_wol_exclusion(adapter, wol) || ++ !device_can_wakeup(&adapter->pdev->dev)) ++ return; ++ ++ if (adapter->wol & IXGBE_WUFC_EX) ++ wol->wolopts |= WAKE_UCAST; ++ if (adapter->wol & IXGBE_WUFC_MC) ++ wol->wolopts |= WAKE_MCAST; ++ if (adapter->wol & IXGBE_WUFC_BC) ++ wol->wolopts |= WAKE_BCAST; ++ if (adapter->wol & IXGBE_WUFC_MAG) ++ wol->wolopts |= WAKE_MAGIC; ++ + return; ++} ++ ++static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) ++{ ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); ++ ++ if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) ++ return -EOPNOTSUPP; ++ ++ if (ixgbe_wol_exclusion(adapter, wol)) ++ return wol->wolopts ? -EOPNOTSUPP : 0; ++ ++ adapter->wol = 0; ++ ++ if (wol->wolopts & WAKE_UCAST) ++ adapter->wol |= IXGBE_WUFC_EX; ++ if (wol->wolopts & WAKE_MCAST) ++ adapter->wol |= IXGBE_WUFC_MC; ++ if (wol->wolopts & WAKE_BCAST) ++ adapter->wol |= IXGBE_WUFC_BC; ++ if (wol->wolopts & WAKE_MAGIC) ++ adapter->wol |= IXGBE_WUFC_MAG; ++ ++ device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); ++ ++ return 0; + } + + static int ixgbe_nway_reset(struct net_device *netdev) +@@ -925,17 +2022,16 @@ + static int ixgbe_phys_id(struct net_device *netdev, u32 data) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); +- struct ixgbe_hw *hw = &adapter->hw; +- u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); ++ u32 led_reg = IXGBE_READ_REG(&adapter->hw, IXGBE_LEDCTL); + u32 i; + + if (!data || data > 300) + data = 300; + + for (i = 0; i < (data * 1000); i += 400) { +- hw->mac.ops.led_on(hw, IXGBE_LED_ON); ++ ixgbe_led_on(&adapter->hw, IXGBE_LED_ON); + msleep_interruptible(200); +- hw->mac.ops.led_off(hw, IXGBE_LED_ON); ++ ixgbe_led_off(&adapter->hw, IXGBE_LED_ON); + msleep_interruptible(200); + } + +@@ -951,6 +2047,9 @@ + struct ixgbe_adapter *adapter = netdev_priv(netdev); + + ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit; ++#ifndef CONFIG_IXGBE_NAPI ++ ec->rx_max_coalesced_frames_irq = adapter->rx_ring[0].work_limit; ++#endif + + /* only valid if in constant ITR mode */ + switch (adapter->itr_setting) { +@@ -970,61 +2069,128 @@ + return 0; + } + ++extern void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector); ++ + static int ixgbe_set_coalesce(struct net_device *netdev, + struct ethtool_coalesce *ec) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); +- struct ixgbe_hw *hw = &adapter->hw; ++ struct ixgbe_q_vector *q_vector; + int i; + + if (ec->tx_max_coalesced_frames_irq) + adapter->tx_ring[0].work_limit = ec->tx_max_coalesced_frames_irq; + ++#ifndef CONFIG_IXGBE_NAPI ++ if (ec->rx_max_coalesced_frames_irq) ++ adapter->rx_ring[0].work_limit = ec->rx_max_coalesced_frames_irq; ++ ++#endif + if (ec->rx_coalesce_usecs > 1) { ++ /* check the limits */ ++ if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) || ++ (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE)) ++ return -EINVAL; ++ + /* store the value in ints/second */ + adapter->eitr_param = 1000000/ec->rx_coalesce_usecs; + + /* static value of interrupt rate */ + adapter->itr_setting = adapter->eitr_param; +- /* clear the lower bit */ ++ /* clear the lower bit as its used for dynamic state */ + adapter->itr_setting &= ~1; + } else if (ec->rx_coalesce_usecs == 1) { + /* 1 means dynamic mode */ + adapter->eitr_param = 20000; + adapter->itr_setting = 1; + } else { +- /* any other value means disable eitr, which is best +- * served by setting the interrupt rate very high */ +- adapter->eitr_param = 3000000; ++ /* ++ * any other value means disable eitr, which is best ++ * served by setting the interrupt rate very high ++ */ ++#ifndef IXGBE_NO_HW_RSC ++ if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) ++ adapter->eitr_param = IXGBE_MAX_RSC_INT_RATE; ++ else ++ adapter->eitr_param = IXGBE_MAX_INT_RATE; ++#else ++ adapter->eitr_param = IXGBE_MAX_INT_RATE; ++#endif + adapter->itr_setting = 0; + } + +- for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { +- struct ixgbe_q_vector *q_vector = &adapter->q_vector[i]; +- if (q_vector->txr_count && !q_vector->rxr_count) +- q_vector->eitr = (adapter->eitr_param >> 1); +- else +- /* rx only or mixed */ +- q_vector->eitr = adapter->eitr_param; +- IXGBE_WRITE_REG(hw, IXGBE_EITR(i), +- EITR_INTS_PER_SEC_TO_REG(q_vector->eitr)); ++ /* MSI/MSIx Interrupt Mode */ ++ if (adapter->flags & ++ (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) { ++ int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; ++ for (i = 0; i < num_vectors; i++) { ++ q_vector = adapter->q_vector[i]; ++ if (q_vector->txr_count && !q_vector->rxr_count) ++ /* tx vector gets half the rate */ ++ q_vector->eitr = (adapter->eitr_param >> 1); ++ else if (q_vector->rxr_count) ++ /* rx only or mixed */ ++ q_vector->eitr = adapter->eitr_param; ++ ixgbe_write_eitr(q_vector); ++ } ++ /* Legacy Interrupt Mode */ ++ } else { ++ q_vector = adapter->q_vector[0]; ++ q_vector->eitr = adapter->eitr_param; ++ ixgbe_write_eitr(q_vector); + } + + return 0; + } + ++#ifdef ETHTOOL_GFLAGS ++static int ixgbe_set_flags(struct net_device *netdev, u32 data) ++{ ++#if !defined(IXGBE_NO_HW_RSC) || !defined(IXGBE_NO_LRO) ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); ++#endif ++ ethtool_op_set_flags(netdev, data); + +-static const struct ethtool_ops ixgbe_ethtool_ops = { ++#ifndef IXGBE_NO_HW_RSC ++ /* if state changes we need to update adapter->flags and reset */ ++ if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) { ++ /* cast both to bool and verify if they are set the same */ ++ if ((!!(data & ETH_FLAG_LRO)) != ++ (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) { ++ adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED; ++ if (netif_running(netdev)) ++ ixgbe_reinit_locked(adapter); ++ else ++ ixgbe_reset(adapter); ++ } ++ return 0; ++ } ++#endif /* IXGBE_NO_HW_RSC */ ++#ifndef IXGBE_NO_LRO ++ /* cast both to bool and verify if they are set the same */ ++ if ((!!(data & ETH_FLAG_LRO)) != ++ (!!(adapter->flags2 & IXGBE_FLAG2_SWLRO_ENABLED))) ++ adapter->flags2 ^= IXGBE_FLAG2_SWLRO_ENABLED; ++ ++#endif /* IXGBE_NO_LRO */ ++ return 0; ++ ++} ++ ++#endif /* ETHTOOL_GFLAGS */ ++static struct ethtool_ops ixgbe_ethtool_ops = { + .get_settings = ixgbe_get_settings, + .set_settings = ixgbe_set_settings, + .get_drvinfo = ixgbe_get_drvinfo, + .get_regs_len = ixgbe_get_regs_len, + .get_regs = ixgbe_get_regs, + .get_wol = ixgbe_get_wol, ++ .set_wol = ixgbe_set_wol, + .nway_reset = ixgbe_nway_reset, + .get_link = ethtool_op_get_link, + .get_eeprom_len = ixgbe_get_eeprom_len, + .get_eeprom = ixgbe_get_eeprom, ++ .set_eeprom = ixgbe_set_eeprom, + .get_ringparam = ixgbe_get_ringparam, + .set_ringparam = ixgbe_set_ringparam, + .get_pauseparam = ixgbe_get_pauseparam, +@@ -1037,19 +2203,29 @@ + .set_sg = ethtool_op_set_sg, + .get_msglevel = ixgbe_get_msglevel, + .set_msglevel = ixgbe_set_msglevel, ++#ifdef NETIF_F_TSO + .get_tso = ethtool_op_get_tso, + .set_tso = ixgbe_set_tso, ++#endif ++ .self_test_count = ixgbe_diag_test_count, ++ .self_test = ixgbe_diag_test, + .get_strings = ixgbe_get_strings, + .phys_id = ixgbe_phys_id, +- .get_sset_count = ixgbe_get_sset_count, ++ .get_stats_count = ixgbe_get_stats_count, + .get_ethtool_stats = ixgbe_get_ethtool_stats, ++#ifdef ETHTOOL_GPERMADDR ++ .get_perm_addr = ethtool_op_get_perm_addr, ++#endif + .get_coalesce = ixgbe_get_coalesce, + .set_coalesce = ixgbe_set_coalesce, ++#ifdef ETHTOOL_GFLAGS + .get_flags = ethtool_op_get_flags, +- .set_flags = ethtool_op_set_flags, ++ .set_flags = ixgbe_set_flags, ++#endif + }; + + void ixgbe_set_ethtool_ops(struct net_device *netdev) + { + SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops); + } ++#endif /* SIOCETHTOOL */ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_fcoe.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/ixgbe/ixgbe_fcoe.c Wed Aug 05 11:05:50 2009 +0100 +@@ -0,0 +1,29 @@ ++/******************************************************************************* ++ ++ Intel 10 Gigabit PCI Express Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "ixgbe.h" ++ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_fcoe.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/ixgbe/ixgbe_fcoe.h Wed Aug 05 11:05:50 2009 +0100 +@@ -0,0 +1,32 @@ ++/******************************************************************************* ++ ++ Intel 10 Gigabit PCI Express Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _IXGBE_FCOE_H ++#define _IXGBE_FCOE_H ++ ++ ++#endif /* _IXGBE_FCOE_H */ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_main.c +--- a/drivers/net/ixgbe/ixgbe_main.c Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe_main.c Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -25,6 +25,10 @@ + + *******************************************************************************/ + ++ ++/****************************************************************************** ++ Copyright (c)2006 - 2007 Myricom, Inc. for some LRO specific code ++******************************************************************************/ + #include + #include + #include +@@ -34,27 +38,42 @@ + #include + #include + #include ++#include + #include ++#ifdef NETIF_F_TSO + #include ++#ifdef NETIF_F_TSO6 + #include ++#endif ++#endif ++#ifdef SIOCETHTOOL + #include ++#endif ++#ifdef NETIF_F_HW_VLAN_TX + #include ++#endif ++ + + #include "ixgbe.h" +-#include "ixgbe_common.h" ++ ++ + + char ixgbe_driver_name[] = "ixgbe"; + static const char ixgbe_driver_string[] = +- "Intel(R) 10 Gigabit PCI Express Network Driver"; +- +-#define DRV_VERSION "1.3.30-k2" ++ "Intel(R) 10 Gigabit PCI Express Network Driver"; ++#define DRV_HW_PERF ++ ++#ifndef CONFIG_IXGBE_NAPI ++#define DRIVERNAPI ++#else ++#define DRIVERNAPI "-NAPI" ++#endif ++ ++#define FPGA ++ ++#define DRV_VERSION "2.0.38.2" DRIVERNAPI DRV_HW_PERF FPGA + const char ixgbe_driver_version[] = DRV_VERSION; +-static char ixgbe_copyright[] = "Copyright (c) 1999-2007 Intel Corporation."; +- +-static const struct ixgbe_info *ixgbe_info_tbl[] = { +- [board_82598] = &ixgbe_82598_info, +-}; +- ++static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; + /* ixgbe_pci_tbl - PCI Device ID Table + * + * Wildcard entries (PCI_ANY_ID) should come last +@@ -64,25 +83,21 @@ + * Class, Class Mask, private data (not used) } + */ + static struct pci_device_id ixgbe_pci_tbl[] = { +- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), +- board_82598 }, +- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), +- board_82598 }, +- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), +- board_82598 }, +- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), +- board_82598 }, +- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), +- board_82598 }, +- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), +- board_82598 }, +- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), +- board_82598 }, +- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), +- board_82598 }, +- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), +- board_82598 }, +- ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598_BX)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598AT)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598AT2)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598EB_CX4)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598EB_XF_LR)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_KX4)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_XAUI_LOM)}, ++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_SFP)}, + /* required last entry */ + {0, } + }; +@@ -96,8 +111,8 @@ + .next = NULL, + .priority = 0 + }; +-#endif +- ++ ++#endif + MODULE_AUTHOR("Intel Corporation, "); + MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); + MODULE_LICENSE("GPL"); +@@ -125,17 +140,69 @@ + ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); + } + +-static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry, +- u8 msix_vector) ++/* ++ * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors ++ * @adapter: pointer to adapter struct ++ * @direction: 0 for Rx, 1 for Tx, -1 for other causes ++ * @queue: queue to map the corresponding interrupt to ++ * @msix_vector: the vector to map to the corresponding queue ++ * ++ */ ++static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, ++ u8 queue, u8 msix_vector) + { + u32 ivar, index; +- +- msix_vector |= IXGBE_IVAR_ALLOC_VAL; +- index = (int_alloc_entry >> 2) & 0x1F; +- ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index)); +- ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3))); +- ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3))); +- IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar); ++ struct ixgbe_hw *hw = &adapter->hw; ++ switch (hw->mac.type) { ++ case ixgbe_mac_82598EB: ++ msix_vector |= IXGBE_IVAR_ALLOC_VAL; ++ if (direction == -1) ++ direction = 0; ++ index = (((direction * 64) + queue) >> 2) & 0x1F; ++ ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); ++ ivar &= ~(0xFF << (8 * (queue & 0x3))); ++ ivar |= (msix_vector << (8 * (queue & 0x3))); ++ IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); ++ break; ++ case ixgbe_mac_82599EB: ++ if (direction == -1) { ++ /* other causes */ ++ msix_vector |= IXGBE_IVAR_ALLOC_VAL; ++ index = ((queue & 1) * 8); ++ ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); ++ ivar &= ~(0xFF << index); ++ ivar |= (msix_vector << index); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); ++ break; ++ } else { ++ /* tx or rx causes */ ++ msix_vector |= IXGBE_IVAR_ALLOC_VAL; ++ index = ((16 * (queue & 1)) + (8 * direction)); ++ ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); ++ ivar &= ~(0xFF << index); ++ ivar |= (msix_vector << index); ++ IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); ++ break; ++ } ++ default: ++ break; ++ } ++} ++ ++static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, ++ u64 qmask) ++{ ++ u32 mask; ++ ++ if (adapter->hw.mac.type == ixgbe_mac_82598EB) { ++ mask = (IXGBE_EIMS_RTX_QUEUE & qmask); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); ++ } else { ++ mask = (qmask & 0xFFFFFFFF); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); ++ mask = (qmask >> 32); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); ++ } + } + + static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, +@@ -191,79 +258,81 @@ + return false; + } + +-#define IXGBE_MAX_TXD_PWR 14 +-#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) ++#define IXGBE_MAX_TXD_PWR 14 ++#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) + + /* Tx Descriptors needed, worst case */ + #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ + (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) ++#ifdef MAX_SKB_FRAGS + #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ +- MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ +- +-#define GET_TX_HEAD_FROM_RING(ring) (\ +- *(volatile u32 *) \ +- ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count)) ++ MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ ++#else ++#define DESC_NEEDED TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) ++#endif ++ + static void ixgbe_tx_timeout(struct net_device *netdev); + + /** + * ixgbe_clean_tx_irq - Reclaim resources after transmit completes +- * @adapter: board private structure ++ * @q_vector: structure containing interrupt and ring information + * @tx_ring: tx ring to clean + **/ +-static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter, ++static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, + struct ixgbe_ring *tx_ring) + { +- union ixgbe_adv_tx_desc *tx_desc; ++ struct ixgbe_adapter *adapter = q_vector->adapter; ++ struct net_device *netdev = adapter->netdev; ++ union ixgbe_adv_tx_desc *tx_desc, *eop_desc; + struct ixgbe_tx_buffer *tx_buffer_info; +- struct net_device *netdev = adapter->netdev; +- struct sk_buff *skb; +- unsigned int i; +- u32 head, oldhead; +- unsigned int count = 0; ++ unsigned int i, eop, count = 0; + unsigned int total_bytes = 0, total_packets = 0; + +- rmb(); +- head = GET_TX_HEAD_FROM_RING(tx_ring); +- head = le32_to_cpu(head); + i = tx_ring->next_to_clean; +- while (1) { +- while (i != head) { ++ eop = tx_ring->tx_buffer_info[i].next_to_watch; ++ eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); ++ ++ while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && ++ (count < tx_ring->work_limit)) { ++ bool cleaned = false; ++ for ( ; !cleaned; count++) { ++ struct sk_buff *skb; + tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); + tx_buffer_info = &tx_ring->tx_buffer_info[i]; ++ cleaned = (i == eop); + skb = tx_buffer_info->skb; + +- if (skb) { ++ if (cleaned && skb) { ++#ifdef NETIF_F_TSO + unsigned int segs, bytecount; ++ unsigned int hlen = skb_headlen(skb); + + /* gso_segs is currently only valid for tcp */ + segs = skb_shinfo(skb)->gso_segs ?: 1; + /* multiply data chunks by size of headers */ +- bytecount = ((segs - 1) * skb_headlen(skb)) + +- skb->len; ++ bytecount = ((segs - 1) * hlen) + skb->len; + total_packets += segs; + total_bytes += bytecount; ++#else ++ total_packets++; ++ total_bytes += skb->len; ++#endif + } + + ixgbe_unmap_and_free_tx_resource(adapter, + tx_buffer_info); ++ ++ tx_desc->wb.status = 0; + + i++; + if (i == tx_ring->count) + i = 0; +- +- count++; +- if (count == tx_ring->count) +- goto done_cleaning; +- } +- oldhead = head; +- rmb(); +- head = GET_TX_HEAD_FROM_RING(tx_ring); +- head = le32_to_cpu(head); +- if (head == oldhead) +- goto done_cleaning; +- } /* while (1) */ +- +-done_cleaning: ++ } ++ ++ eop = tx_ring->tx_buffer_info[i].next_to_watch; ++ eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); ++ } ++ + tx_ring->next_to_clean = i; + + #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) +@@ -273,11 +342,19 @@ + * sees the new next_to_clean. + */ + smp_mb(); ++#ifdef HAVE_TX_MQ + if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && + !test_bit(__IXGBE_DOWN, &adapter->state)) { + netif_wake_subqueue(netdev, tx_ring->queue_index); + ++adapter->restart_queue; + } ++#else ++ if (netif_queue_stopped(netdev) && ++ !test_bit(__IXGBE_DOWN, &adapter->state)) { ++ netif_wake_queue(netdev); ++ ++adapter->restart_queue; ++ } ++#endif + } + + if (adapter->detect_tx_hung) { +@@ -290,18 +367,20 @@ + } + } + ++#ifndef CONFIG_IXGBE_NAPI + /* re-arm the interrupt */ +- if ((total_packets >= tx_ring->work_limit) || +- (count == tx_ring->count)) +- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx); +- ++ if ((count >= tx_ring->work_limit) && ++ (!test_bit(__IXGBE_DOWN, &adapter->state))) ++ ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx)); ++ ++#endif + tx_ring->total_bytes += total_bytes; + tx_ring->total_packets += total_packets; ++ tx_ring->stats.packets += total_packets; + tx_ring->stats.bytes += total_bytes; +- tx_ring->stats.packets += total_packets; + adapter->net_stats.tx_bytes += total_bytes; + adapter->net_stats.tx_packets += total_packets; +- return (total_packets ? true : false); ++ return (count < tx_ring->work_limit); + } + + #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) +@@ -311,14 +390,31 @@ + u32 rxctrl; + int cpu = get_cpu(); + int q = rx_ring - adapter->rx_ring; ++ struct ixgbe_hw *hw = &adapter->hw; + + if (rx_ring->cpu != cpu) { +- rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); +- rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; +- rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); ++ rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(q)); ++ if (hw->mac.type == ixgbe_mac_82598EB) { ++ rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; ++ rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); ++ } else if (hw->mac.type == ixgbe_mac_82599EB) { ++ rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; ++ rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << ++ IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); ++ } + rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; + rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; +- IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); ++ if (adapter->flags & IXGBE_FLAG_DCA_ENABLED_DATA) { ++ /* just do the header data when in Packet Split mode */ ++ if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) ++ rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; ++ else ++ rxctrl |= IXGBE_DCA_RXCTRL_DATA_DCA_EN; ++ } ++ rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); ++ rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | ++ IXGBE_DCA_RXCTRL_DESC_HSRO_EN); ++ IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(q), rxctrl); + rx_ring->cpu = cpu; + } + put_cpu(); +@@ -330,13 +426,23 @@ + u32 txctrl; + int cpu = get_cpu(); + int q = tx_ring - adapter->tx_ring; ++ struct ixgbe_hw *hw = &adapter->hw; + + if (tx_ring->cpu != cpu) { +- txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q)); +- txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; +- txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); +- txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; +- IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl); ++ if (hw->mac.type == ixgbe_mac_82598EB) { ++ txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q)); ++ txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; ++ txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); ++ txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; ++ IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl); ++ } else if (hw->mac.type == ixgbe_mac_82599EB) { ++ txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q)); ++ txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; ++ txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << ++ IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); ++ txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; ++ IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl); ++ } + tx_ring->cpu = cpu; + } + put_cpu(); +@@ -348,6 +454,9 @@ + + if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) + return; ++ ++ /* Always use CB2 mode, difference is masked in the CB driver. */ ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); + + for (i = 0; i < adapter->num_tx_queues; i++) { + adapter->tx_ring[i].cpu = -1; +@@ -370,9 +479,6 @@ + /* if we're already enabled, don't do it again */ + if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) + break; +- /* Always use CB2 mode, difference is masked +- * in the CB driver. */ +- IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); + if (dca_add_requester(dev) == 0) { + adapter->flags |= IXGBE_FLAG_DCA_ENABLED; + ixgbe_setup_dca(adapter); +@@ -394,57 +500,60 @@ + #endif /* CONFIG_DCA or CONFIG_DCA_MODULE */ + /** + * ixgbe_receive_skb - Send a completed packet up the stack +- * @adapter: board private structure ++ * @q_vector: structure containing interrupt and ring information + * @skb: packet to send up +- * @status: hardware indication of status of receive +- * @rx_ring: rx descriptor ring (for a specific queue) to setup +- * @rx_desc: rx descriptor +- **/ +-static void ixgbe_receive_skb(struct ixgbe_adapter *adapter, +- struct sk_buff *skb, u8 status, +- struct ixgbe_ring *ring, +- union ixgbe_adv_rx_desc *rx_desc) +-{ +- bool is_vlan = (status & IXGBE_RXD_STAT_VP); +- u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); +- +-#ifdef CONFIG_IXGBE_LRO +- if (adapter->netdev->features & NETIF_F_LRO && +- skb->ip_summed == CHECKSUM_UNNECESSARY) { +- if (adapter->vlgrp && is_vlan && (tag != 0)) +- lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb, +- adapter->vlgrp, tag, +- rx_desc); +- else +- lro_receive_skb(&ring->lro_mgr, skb, rx_desc); +- ring->lro_used = true; +- } else { +-#endif ++ * @vlan_tag: vlan tag for packet ++ **/ ++static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, ++ struct sk_buff *skb, u16 vlan_tag) ++{ ++ struct ixgbe_adapter *adapter = q_vector->adapter; ++ int ret; ++ ++#ifdef CONFIG_IXGBE_NAPI + if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { +- if (adapter->vlgrp && is_vlan && (tag != 0)) +- vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag); ++#ifdef NETIF_F_HW_VLAN_TX ++ if (adapter->vlgrp && vlan_tag) ++ vlan_gro_receive(&q_vector->napi, ++ adapter->vlgrp, ++ vlan_tag, skb); + else +- netif_receive_skb(skb); +- } else { +- if (adapter->vlgrp && is_vlan && (tag != 0)) +- vlan_hwaccel_rx(skb, adapter->vlgrp, tag); ++ napi_gro_receive(&q_vector->napi, skb); ++#else ++ napi_gro_receive(&q_vector->napi, skb); ++#endif ++ } else { ++#endif /* CONFIG_IXGBE_NAPI */ ++ ++#ifdef NETIF_F_HW_VLAN_TX ++ if (adapter->vlgrp && vlan_tag) ++ ret = vlan_hwaccel_rx(skb, adapter->vlgrp, ++ vlan_tag); + else +- netif_rx(skb); +- } +-#ifdef CONFIG_IXGBE_LRO +- } +-#endif ++ ret = netif_rx(skb); ++#else ++ ret = netif_rx(skb); ++#endif ++#ifndef CONFIG_IXGBE_NAPI ++ if (ret == NET_RX_DROP) ++ adapter->rx_dropped_backlog++; ++#endif ++#ifdef CONFIG_IXGBE_NAPI ++ } ++#endif /* CONFIG_IXGBE_NAPI */ + } + + /** + * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum + * @adapter: address of board private structure +- * @status_err: hardware indication of status of receive ++ * @rx_desc: current Rx descriptor being processed + * @skb: skb currently being received and modified + **/ + static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, +- u32 status_err, struct sk_buff *skb) +-{ ++ union ixgbe_adv_rx_desc *rx_desc, ++ struct sk_buff *skb) ++{ ++ u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error); + skb->ip_summed = CHECKSUM_NONE; + + /* Rx csum disabled */ +@@ -462,6 +571,15 @@ + return; + + if (status_err & IXGBE_RXDADV_ERR_TCPE) { ++ u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; ++ /* ++ * 82599 errata, UDP frames with a 0 checksum can be marked as ++ * checksum errors. ++ */ ++ if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) && ++ (adapter->hw.mac.type == ixgbe_mac_82599EB)) ++ return; ++ + adapter->hw_csum_rx_error++; + return; + } +@@ -471,6 +589,19 @@ + adapter->hw_csum_rx_good++; + } + ++static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw, ++ struct ixgbe_ring *rx_ring, u32 val) ++{ ++ /* ++ * Force memory writes to complete before letting h/w ++ * know there are new descriptors to fetch. (Only ++ * applicable for weak-ordered memory model archs, ++ * such as IA-64). ++ */ ++ wmb(); ++ writel(val, hw->hw_addr + rx_ring->tail); ++} ++ + /** + * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split + * @adapter: address of board private structure +@@ -480,7 +611,6 @@ + int cleaned_count) + { + struct pci_dev *pdev = adapter->pdev; +- struct net_device *netdev = adapter->netdev; + union ixgbe_adv_rx_desc *rx_desc; + struct ixgbe_rx_buffer *bi; + unsigned int i; +@@ -495,7 +625,7 @@ + if (!bi->page_dma && + (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) { + if (!bi->page) { +- bi->page = netdev_alloc_page(netdev); ++ bi->page = alloc_page(GFP_ATOMIC); + if (!bi->page) { + adapter->alloc_rx_page_failed++; + goto no_buffers; +@@ -529,9 +659,12 @@ + skb_reserve(skb, NET_IP_ALIGN); + + bi->skb = skb; +- bi->dma = pci_map_single(pdev, skb->data, bufsz, ++ } ++ ++ if (!bi->dma) ++ bi->dma = pci_map_single(pdev, bi->skb->data, rx_ring->rx_buf_len, + PCI_DMA_FROMDEVICE); +- } ++ + /* Refresh the desc even if buffer_addrs didn't change because + * each write-back erases this info. */ + if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { +@@ -553,14 +686,7 @@ + if (i-- == 0) + i = (rx_ring->count - 1); + +- /* +- * Force memory writes to complete before letting h/w +- * know there are new descriptors to fetch. (Only +- * applicable for weak-ordered memory model archs, +- * such as IA-64). +- */ +- wmb(); +- writel(i, adapter->hw.hw_addr + rx_ring->tail); ++ ixgbe_release_rx_desc(&adapter->hw, rx_ring, i); + } + } + +@@ -569,24 +695,428 @@ + return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; + } + +-static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) +-{ +- return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; +-} +- +-static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter, ++#if !defined(IXGBE_NO_LRO) || !defined(IXGBE_NO_HW_RSC) ++/** ++ * ixgbe_transform_rsc_queue - change rsc queue into a full packet ++ * @skb: pointer to the last skb in the rsc queue ++ * ++ * This function changes a queue full of hw rsc buffers into a completed ++ * packet. It uses the ->prev pointers to find the first packet and then ++ * turns it into the frag list owner. ++ **/ ++static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb) ++{ ++ unsigned int frag_list_size = 0; ++ ++ while (skb->prev) { ++ struct sk_buff *prev = skb->prev; ++ frag_list_size += skb->len; ++ skb->prev = NULL; ++ skb = prev; ++ } ++ ++ skb_shinfo(skb)->frag_list = skb->next; ++ skb->next = NULL; ++ skb->len += frag_list_size; ++ skb->data_len += frag_list_size; ++ skb->truesize += frag_list_size; ++ return skb; ++} ++ ++#endif /* !IXGBE_NO_LRO || !IXGBE_NO_HW_RSC */ ++#ifndef IXGBE_NO_LRO ++/** ++ * ixgbe_can_lro - returns true if packet is TCP/IPV4 and LRO is enabled ++ * @adapter: board private structure ++ * @rx_desc: pointer to the rx descriptor ++ * ++ **/ ++static inline bool ixgbe_can_lro(struct ixgbe_adapter *adapter, ++ union ixgbe_adv_rx_desc *rx_desc) ++{ ++ u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; ++ ++ return (adapter->flags2 & IXGBE_FLAG2_SWLRO_ENABLED) && ++ !(adapter->netdev->flags & IFF_PROMISC) && ++ (pkt_info & IXGBE_RXDADV_PKTTYPE_IPV4) && ++ (pkt_info & IXGBE_RXDADV_PKTTYPE_TCP); ++} ++ ++/** ++ * ixgbe_lro_flush - Indicate packets to upper layer. ++ * ++ * Update IP and TCP header part of head skb if more than one ++ * skb's chained and indicate packets to upper layer. ++ **/ ++static void ixgbe_lro_flush(struct ixgbe_q_vector *q_vector, ++ struct ixgbe_lro_desc *lrod) ++{ ++ struct ixgbe_lro_list *lrolist = q_vector->lrolist; ++ struct iphdr *iph; ++ struct tcphdr *th; ++ struct sk_buff *skb; ++ u32 *ts_ptr; ++ ++ hlist_del(&lrod->lro_node); ++ lrolist->active_cnt--; ++ ++ skb = lrod->skb; ++ lrod->skb = NULL; ++ ++ if (lrod->append_cnt) { ++ /* take the lro queue and convert to skb format */ ++ skb = ixgbe_transform_rsc_queue(skb); ++ ++ /* incorporate ip header and re-calculate checksum */ ++ iph = (struct iphdr *)skb->data; ++ iph->tot_len = ntohs(skb->len); ++ iph->check = 0; ++ iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl); ++ ++ /* incorporate the latest ack into the tcp header */ ++ th = (struct tcphdr *) ((char *)skb->data + sizeof(*iph)); ++ th->ack_seq = lrod->ack_seq; ++ th->psh = lrod->psh; ++ th->window = lrod->window; ++ th->check = 0; ++ ++ /* incorporate latest timestamp into the tcp header */ ++ if (lrod->opt_bytes) { ++ ts_ptr = (u32 *)(th + 1); ++ ts_ptr[1] = htonl(lrod->tsval); ++ ts_ptr[2] = lrod->tsecr; ++ } ++ } ++ ++#ifdef NETIF_F_TSO ++ skb_shinfo(skb)->gso_size = lrod->mss; ++#endif ++ ixgbe_receive_skb(q_vector, skb, lrod->vlan_tag); ++ lrolist->stats.flushed++; ++ ++ ++ hlist_add_head(&lrod->lro_node, &lrolist->free); ++} ++ ++static void ixgbe_lro_flush_all(struct ixgbe_q_vector *q_vector) ++{ ++ struct ixgbe_lro_desc *lrod; ++ struct hlist_node *node, *node2; ++ struct ixgbe_lro_list *lrolist = q_vector->lrolist; ++ ++ hlist_for_each_entry_safe(lrod, node, node2, &lrolist->active, lro_node) ++ ixgbe_lro_flush(q_vector, lrod); ++} ++ ++/* ++ * ixgbe_lro_header_ok - Main LRO function. ++ **/ ++static u16 ixgbe_lro_header_ok(struct sk_buff *new_skb, struct iphdr *iph, ++ struct tcphdr *th) ++{ ++ int opt_bytes, tcp_data_len; ++ u32 *ts_ptr = NULL; ++ ++ /* If we see CE codepoint in IP header, packet is not mergeable */ ++ if (INET_ECN_is_ce(ipv4_get_dsfield(iph))) ++ return -1; ++ ++ /* ensure there are no options */ ++ if ((iph->ihl << 2) != sizeof(*iph)) ++ return -1; ++ ++ /* .. and the packet is not fragmented */ ++ if (iph->frag_off & htons(IP_MF|IP_OFFSET)) ++ return -1; ++ ++ /* ensure no bits set besides ack or psh */ ++ if (th->fin || th->syn || th->rst || ++ th->urg || th->ece || th->cwr || !th->ack) ++ return -1; ++ ++ /* ensure that the checksum is valid */ ++ if (new_skb->ip_summed != CHECKSUM_UNNECESSARY) ++ return -1; ++ ++ /* ++ * check for timestamps. Since the only option we handle are timestamps, ++ * we only have to handle the simple case of aligned timestamps ++ */ ++ ++ opt_bytes = (th->doff << 2) - sizeof(*th); ++ if (opt_bytes != 0) { ++ ts_ptr = (u32 *)(th + 1); ++ if ((opt_bytes != TCPOLEN_TSTAMP_ALIGNED) || ++ (*ts_ptr != ntohl((TCPOPT_NOP << 24) | ++ (TCPOPT_NOP << 16) | (TCPOPT_TIMESTAMP << 8) | ++ TCPOLEN_TIMESTAMP))) { ++ return -1; ++ } ++ } ++ ++ tcp_data_len = ntohs(iph->tot_len) - (th->doff << 2) - sizeof(*iph); ++ ++ return tcp_data_len; ++} ++ ++/** ++ * ixgbe_lro_queue - if able, queue skb into lro chain ++ * @q_vector: structure containing interrupt and ring information ++ * @new_skb: pointer to current skb being checked ++ * @tag: vlan tag for skb ++ * ++ * Checks whether the skb given is eligible for LRO and if that's ++ * fine chains it to the existing lro_skb based on flowid. If an LRO for ++ * the flow doesn't exist create one. ++ **/ ++static struct sk_buff *ixgbe_lro_queue(struct ixgbe_q_vector *q_vector, ++ struct sk_buff *new_skb, ++ u16 tag) ++{ ++ struct sk_buff *lro_skb; ++ struct ixgbe_lro_desc *lrod; ++ struct hlist_node *node; ++ struct skb_shared_info *new_skb_info = skb_shinfo(new_skb); ++ struct ixgbe_lro_list *lrolist = q_vector->lrolist; ++ struct iphdr *iph = (struct iphdr *)new_skb->data; ++ struct tcphdr *th = (struct tcphdr *)(iph + 1); ++ int tcp_data_len = ixgbe_lro_header_ok(new_skb, iph, th); ++ u16 opt_bytes = (th->doff << 2) - sizeof(*th); ++ u32 *ts_ptr = (opt_bytes ? (u32 *)(th + 1) : NULL); ++ u32 seq = ntohl(th->seq); ++ ++ /* ++ * we have a packet that might be eligible for LRO, ++ * so see if it matches anything we might expect ++ */ ++ hlist_for_each_entry(lrod, node, &lrolist->active, lro_node) { ++ if (lrod->source_port != th->source || ++ lrod->dest_port != th->dest || ++ lrod->source_ip != iph->saddr || ++ lrod->dest_ip != iph->daddr || ++ lrod->vlan_tag != tag) ++ continue; ++ ++ /* malformed header, or resultant packet would be too large */ ++ if (tcp_data_len < 0 || (tcp_data_len + lrod->len) > 65535) { ++ ixgbe_lro_flush(q_vector, lrod); ++ break; ++ } ++ ++ /* out of order packet */ ++ if (seq != lrod->next_seq) { ++ ixgbe_lro_flush(q_vector, lrod); ++ tcp_data_len = -1; ++ break; ++ } ++ ++ if (lrod->opt_bytes || opt_bytes) { ++ u32 tsval = ntohl(*(ts_ptr + 1)); ++ /* make sure timestamp values are increasing */ ++ if (opt_bytes != lrod->opt_bytes || ++ lrod->tsval > tsval || *(ts_ptr + 2) == 0) { ++ ixgbe_lro_flush(q_vector, lrod); ++ tcp_data_len = -1; ++ break; ++ } ++ ++ lrod->tsval = tsval; ++ lrod->tsecr = *(ts_ptr + 2); ++ } ++ ++ /* remove any padding from the end of the skb */ ++ __pskb_trim(new_skb, ntohs(iph->tot_len)); ++ /* Remove IP and TCP header*/ ++ skb_pull(new_skb, ntohs(iph->tot_len) - tcp_data_len); ++ ++ lrod->next_seq += tcp_data_len; ++ lrod->ack_seq = th->ack_seq; ++ lrod->window = th->window; ++ lrod->len += tcp_data_len; ++ lrod->psh |= th->psh; ++ lrod->append_cnt++; ++ lrolist->stats.coal++; ++ ++ if (tcp_data_len > lrod->mss) ++ lrod->mss = tcp_data_len; ++ ++ lro_skb = lrod->skb; ++ ++ /* if header is empty pull pages into current skb */ ++ if (!skb_headlen(new_skb) && ++ ((skb_shinfo(lro_skb)->nr_frags + ++ skb_shinfo(new_skb)->nr_frags) <= MAX_SKB_FRAGS )) { ++ struct skb_shared_info *lro_skb_info = skb_shinfo(lro_skb); ++ ++ /* copy frags into the last skb */ ++ memcpy(lro_skb_info->frags + lro_skb_info->nr_frags, ++ new_skb_info->frags, ++ new_skb_info->nr_frags * sizeof(skb_frag_t)); ++ ++ lro_skb_info->nr_frags += new_skb_info->nr_frags; ++ lro_skb->len += tcp_data_len; ++ lro_skb->data_len += tcp_data_len; ++ lro_skb->truesize += tcp_data_len; ++ ++ new_skb_info->nr_frags = 0; ++ new_skb->truesize -= tcp_data_len; ++ new_skb->len = new_skb->data_len = 0; ++ } else if (tcp_data_len) { ++ /* Chain this new skb in frag_list */ ++ new_skb->prev = lro_skb; ++ lro_skb->next = new_skb; ++ lrod->skb = new_skb ; ++ } ++ ++ if (lrod->psh) ++ ixgbe_lro_flush(q_vector, lrod); ++ ++ /* return the skb if it is empty for recycling */ ++ if (!new_skb->len) { ++ new_skb->data = skb_mac_header(new_skb); ++ __pskb_trim(new_skb, 0); ++ new_skb->protocol = 0; ++ lrolist->stats.recycled++; ++ return new_skb; ++ } ++ ++ return NULL; ++ } ++ ++ /* start a new packet */ ++ if (tcp_data_len > 0 && !hlist_empty(&lrolist->free) && !th->psh) { ++ lrod = hlist_entry(lrolist->free.first, struct ixgbe_lro_desc, ++ lro_node); ++ ++ lrod->skb = new_skb; ++ lrod->source_ip = iph->saddr; ++ lrod->dest_ip = iph->daddr; ++ lrod->source_port = th->source; ++ lrod->dest_port = th->dest; ++ lrod->vlan_tag = tag; ++ lrod->len = new_skb->len; ++ lrod->next_seq = seq + tcp_data_len; ++ lrod->ack_seq = th->ack_seq; ++ lrod->window = th->window; ++ lrod->mss = tcp_data_len; ++ lrod->opt_bytes = opt_bytes; ++ lrod->psh = 0; ++ lrod->append_cnt = 0; ++ ++ /* record timestamp if it is present */ ++ if (opt_bytes) { ++ lrod->tsval = ntohl(*(ts_ptr + 1)); ++ lrod->tsecr = *(ts_ptr + 2); ++ } ++ /* remove first packet from freelist.. */ ++ hlist_del(&lrod->lro_node); ++ /* .. and insert at the front of the active list */ ++ hlist_add_head(&lrod->lro_node, &lrolist->active); ++ lrolist->active_cnt++; ++ lrolist->stats.coal++; ++ return NULL; ++ } ++ ++ /* packet not handled by any of the above, pass it to the stack */ ++ ixgbe_receive_skb(q_vector, new_skb, tag); ++ return NULL; ++} ++ ++static void ixgbe_lro_ring_exit(struct ixgbe_lro_list *lrolist) ++{ ++ struct hlist_node *node, *node2; ++ struct ixgbe_lro_desc *lrod; ++ ++ hlist_for_each_entry_safe(lrod, node, node2, &lrolist->active, ++ lro_node) { ++ hlist_del(&lrod->lro_node); ++ kfree(lrod); ++ } ++ ++ hlist_for_each_entry_safe(lrod, node, node2, &lrolist->free, ++ lro_node) { ++ hlist_del(&lrod->lro_node); ++ kfree(lrod); ++ } ++} ++ ++static void ixgbe_lro_ring_init(struct ixgbe_lro_list *lrolist) ++{ ++ int j, bytes; ++ struct ixgbe_lro_desc *lrod; ++ ++ bytes = sizeof(struct ixgbe_lro_desc); ++ ++ INIT_HLIST_HEAD(&lrolist->free); ++ INIT_HLIST_HEAD(&lrolist->active); ++ ++ for (j = 0; j < IXGBE_LRO_MAX; j++) { ++ lrod = kzalloc(bytes, GFP_KERNEL); ++ if (lrod != NULL) { ++ INIT_HLIST_NODE(&lrod->lro_node); ++ hlist_add_head(&lrod->lro_node, &lrolist->free); ++ } ++ } ++} ++ ++#endif /* IXGBE_NO_LRO */ ++ ++#ifndef IXGBE_NO_HW_RSC ++static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc) ++{ ++ return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & ++ IXGBE_RXDADV_RSCCNT_MASK) >> ++ IXGBE_RXDADV_RSCCNT_SHIFT; ++} ++ ++#endif /* IXGBE_NO_HW_RSC */ ++ ++static void ixgbe_rx_status_indication(u32 staterr, ++ struct ixgbe_adapter *adapter) ++{ ++ switch (adapter->hw.mac.type) { ++ case ixgbe_mac_82599EB: ++ if (staterr & IXGBE_RXD_STAT_FLM) ++ adapter->flm++; ++#ifndef IXGBE_NO_LLI ++ if (staterr & IXGBE_RXD_STAT_DYNINT) ++ adapter->lli_int++; ++#endif /* IXGBE_NO_LLI */ ++ break; ++ case ixgbe_mac_82598EB: ++#ifndef IXGBE_NO_LLI ++ if (staterr & IXGBE_RXD_STAT_DYNINT) ++ adapter->lli_int++; ++#endif /* IXGBE_NO_LLI */ ++ break; ++ default: ++ break; ++ } ++} ++ ++#ifdef CONFIG_IXGBE_NAPI ++static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, + struct ixgbe_ring *rx_ring, + int *work_done, int work_to_do) +-{ ++#else ++static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, ++ struct ixgbe_ring *rx_ring) ++#endif ++{ ++ struct ixgbe_adapter *adapter = q_vector->adapter; + struct pci_dev *pdev = adapter->pdev; + union ixgbe_adv_rx_desc *rx_desc, *next_rxd; + struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; + struct sk_buff *skb; +- unsigned int i; ++ unsigned int i, rsc_count = 0; + u32 len, staterr; +- u16 hdr_info; ++ u16 hdr_info, vlan_tag; + bool cleaned = false; + int cleaned_count = 0; ++#ifndef CONFIG_IXGBE_NAPI ++ int work_to_do = rx_ring->work_limit, local_work_done = 0; ++ int *work_done = &local_work_done; ++#endif + unsigned int total_rx_bytes = 0, total_rx_packets = 0; + + i = rx_ring->next_to_clean; +@@ -604,24 +1134,23 @@ + hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); + len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> + IXGBE_RXDADV_HDRBUFLEN_SHIFT; +- if (hdr_info & IXGBE_RXDADV_SPH) +- adapter->rx_hdr_split++; + if (len > IXGBE_RX_HDR_SIZE) + len = IXGBE_RX_HDR_SIZE; + upper_len = le16_to_cpu(rx_desc->wb.upper.length); + } else { + len = le16_to_cpu(rx_desc->wb.upper.length); + } +- + cleaned = true; + skb = rx_buffer_info->skb; + prefetch(skb->data - NET_IP_ALIGN); + rx_buffer_info->skb = NULL; + +- if (len && !skb_shinfo(skb)->nr_frags) { ++ /* if this is a skb from previous receive dma will be 0 */ ++ if (rx_buffer_info->dma) { + pci_unmap_single(pdev, rx_buffer_info->dma, +- rx_ring->rx_buf_len + NET_IP_ALIGN, ++ rx_ring->rx_buf_len, + PCI_DMA_FROMDEVICE); ++ rx_buffer_info->dma = 0; + skb_put(skb, len); + } + +@@ -629,53 +1158,92 @@ + pci_unmap_page(pdev, rx_buffer_info->page_dma, + PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); + rx_buffer_info->page_dma = 0; +- skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, +- rx_buffer_info->page, +- rx_buffer_info->page_offset, +- upper_len); +- +- if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || +- (page_count(rx_buffer_info->page) != 1)) ++ skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, ++ rx_buffer_info->page, ++ rx_buffer_info->page_offset, ++ upper_len); ++ ++ if (page_count(rx_buffer_info->page) != 1) + rx_buffer_info->page = NULL; + else + get_page(rx_buffer_info->page); + ++ skb->len += upper_len; ++ skb->data_len += upper_len; ++ skb->truesize += upper_len; + } + + i++; + if (i == rx_ring->count) + i = 0; +- next_buffer = &rx_ring->rx_buffer_info[i]; + + next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); + prefetch(next_rxd); +- + cleaned_count++; ++ ++#ifndef IXGBE_NO_HW_RSC ++ if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ++ rsc_count = ixgbe_get_rsc_count(rx_desc); ++ ++#endif ++ if (rsc_count) { ++ u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> ++ IXGBE_RXDADV_NEXTP_SHIFT; ++ next_buffer = &rx_ring->rx_buffer_info[nextp]; ++ rx_ring->rsc_count += (rsc_count - 1); ++ } else { ++ next_buffer = &rx_ring->rx_buffer_info[i]; ++ } ++ + if (staterr & IXGBE_RXD_STAT_EOP) { ++ ixgbe_rx_status_indication(staterr, adapter); ++#ifndef IXGBE_NO_HW_RSC ++ if (skb->prev) ++ skb = ixgbe_transform_rsc_queue(skb); ++#endif + rx_ring->stats.packets++; + rx_ring->stats.bytes += skb->len; + } else { +- rx_buffer_info->skb = next_buffer->skb; +- rx_buffer_info->dma = next_buffer->dma; +- next_buffer->skb = skb; +- next_buffer->dma = 0; ++ if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { ++ rx_buffer_info->skb = next_buffer->skb; ++ rx_buffer_info->dma = next_buffer->dma; ++ next_buffer->skb = skb; ++ next_buffer->dma = 0; ++ } else { ++ skb->next = next_buffer->skb; ++ skb->next->prev = skb; ++ } + adapter->non_eop_descs++; + goto next_desc; + } + +- if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { +- dev_kfree_skb_irq(skb); ++ /* ERR_MASK will only have valid bits if EOP set */ ++ if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) { ++ /* trim packet back to size 0 and recycle it */ ++ __pskb_trim(skb, 0); ++ rx_buffer_info->skb = skb; + goto next_desc; + } + +- ixgbe_rx_checksum(adapter, staterr, skb); ++ ixgbe_rx_checksum(adapter, rx_desc, skb); + + /* probably a little skewed due to removing CRC */ + total_rx_bytes += skb->len; + total_rx_packets++; + + skb->protocol = eth_type_trans(skb, adapter->netdev); +- ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc); ++ skb_record_rx_queue(skb, rx_ring->queue_index); ++ ++ vlan_tag = ((staterr & IXGBE_RXD_STAT_VP) ? ++ le16_to_cpu(rx_desc->wb.upper.vlan) : 0); ++ ++#ifndef IXGBE_NO_LRO ++ if (ixgbe_can_lro(adapter, rx_desc)) ++ rx_buffer_info->skb = ixgbe_lro_queue(q_vector, skb, vlan_tag); ++ else ++#endif ++ ixgbe_receive_skb(q_vector, skb, vlan_tag); ++ + adapter->netdev->last_rx = jiffies; + + next_desc: +@@ -689,33 +1257,67 @@ + + /* use prefetched values */ + rx_desc = next_rxd; +- rx_buffer_info = next_buffer; ++ rx_buffer_info = &rx_ring->rx_buffer_info[i]; + + staterr = le32_to_cpu(rx_desc->wb.upper.status_error); + } + +-#ifdef CONFIG_IXGBE_LRO +- if (rx_ring->lro_used) { +- lro_flush_all(&rx_ring->lro_mgr); +- rx_ring->lro_used = false; +- } +-#endif +- ++#ifndef IXGBE_NO_LRO ++ if (adapter->flags2 & IXGBE_FLAG2_SWLRO_ENABLED) ++ ixgbe_lro_flush_all(q_vector); ++#endif /* IXGBE_NO_LRO */ + rx_ring->next_to_clean = i; + cleaned_count = IXGBE_DESC_UNUSED(rx_ring); + + if (cleaned_count) + ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); ++ + + rx_ring->total_packets += total_rx_packets; + rx_ring->total_bytes += total_rx_bytes; + adapter->net_stats.rx_bytes += total_rx_bytes; + adapter->net_stats.rx_packets += total_rx_packets; + ++#ifndef CONFIG_IXGBE_NAPI ++ /* re-arm the interrupt if we had to bail early and have more work */ ++ if ((*work_done >= work_to_do) && ++ (!test_bit(__IXGBE_DOWN, &adapter->state))) ++ ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx)); ++#endif + return cleaned; + } + ++/** ++ * ixgbe_write_eitr - write EITR register in hardware specific way ++ * @q_vector: structure containing interrupt and ring information ++ * ++ * This function is made to be called by ethtool and by the driver ++ * when it needs to update EITR registers at runtime. Hardware ++ * specific quirks/differences are taken care of here. ++ */ ++void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) ++{ ++ struct ixgbe_adapter *adapter = q_vector->adapter; ++ struct ixgbe_hw *hw = &adapter->hw; ++ int v_idx = q_vector->v_idx; ++ u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr); ++ ++ if (adapter->hw.mac.type == ixgbe_mac_82598EB) { ++ /* must write high and low 16 bits to reset counter */ ++ itr_reg |= (itr_reg << 16); ++ } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { ++ /* ++ * set the WDIS bit to not clear the timer bits and cause an ++ * immediate assertion of the interrupt ++ */ ++ itr_reg |= IXGBE_EITR_CNT_WDIS; ++ } ++ IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); ++} ++ ++#ifdef CONFIG_IXGBE_NAPI + static int ixgbe_clean_rxonly(struct napi_struct *, int); ++#endif + /** + * ixgbe_configure_msix - Configure MSI-X hardware + * @adapter: board private structure +@@ -731,18 +1333,19 @@ + + q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; + +- /* Populate the IVAR table and set the ITR values to the ++ /* ++ * Populate the IVAR table and set the ITR values to the + * corresponding register. + */ + for (v_idx = 0; v_idx < q_vectors; v_idx++) { +- q_vector = &adapter->q_vector[v_idx]; ++ q_vector = adapter->q_vector[v_idx]; + /* XXX for_each_bit(...) */ + r_idx = find_first_bit(q_vector->rxr_idx, + adapter->num_rx_queues); + + for (i = 0; i < q_vector->rxr_count; i++) { + j = adapter->rx_ring[r_idx].reg_idx; +- ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx); ++ ixgbe_set_ivar(adapter, 0, j, v_idx); + r_idx = find_next_bit(q_vector->rxr_idx, + adapter->num_rx_queues, + r_idx + 1); +@@ -752,7 +1355,7 @@ + + for (i = 0; i < q_vector->txr_count; i++) { + j = adapter->tx_ring[r_idx].reg_idx; +- ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx); ++ ixgbe_set_ivar(adapter, 1, j, v_idx); + r_idx = find_next_bit(q_vector->txr_idx, + adapter->num_tx_queues, + r_idx + 1); +@@ -761,20 +1364,28 @@ + /* if this is a tx only vector halve the interrupt rate */ + if (q_vector->txr_count && !q_vector->rxr_count) + q_vector->eitr = (adapter->eitr_param >> 1); +- else ++ else if (q_vector->rxr_count) + /* rx only */ + q_vector->eitr = adapter->eitr_param; + +- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), +- EITR_INTS_PER_SEC_TO_REG(q_vector->eitr)); +- } +- +- ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx); ++ ixgbe_write_eitr(q_vector); ++ } ++ ++ if (adapter->hw.mac.type == ixgbe_mac_82598EB) ++ ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, ++ v_idx); ++ else if (adapter->hw.mac.type == ixgbe_mac_82599EB) ++ ixgbe_set_ivar(adapter, -1, 1, v_idx); + IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); ++#ifdef IXGBE_TCP_TIMER ++ ixgbe_set_ivar(adapter, -1, 0, ++v_idx); ++#endif /* IXGBE_TCP_TIMER */ + + /* set up to autoclear timer, and the vectors */ + mask = IXGBE_EIMS_ENABLE_MASK; +- mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); ++ mask &= ~(IXGBE_EIMS_OTHER | ++ IXGBE_EIMS_LSC); ++ + IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); + } + +@@ -826,18 +1437,22 @@ + + switch (itr_setting) { + case lowest_latency: +- if (bytes_perint > adapter->eitr_low) ++ if (bytes_perint > adapter->eitr_low) { + retval = low_latency; ++ } + break; + case low_latency: +- if (bytes_perint > adapter->eitr_high) ++ if (bytes_perint > adapter->eitr_high) { + retval = bulk_latency; +- else if (bytes_perint <= adapter->eitr_low) ++ } ++ else if (bytes_perint <= adapter->eitr_low) { + retval = lowest_latency; ++ } + break; + case bulk_latency: +- if (bytes_perint <= adapter->eitr_high) ++ if (bytes_perint <= adapter->eitr_high) { + retval = low_latency; ++ } + break; + } + +@@ -848,12 +1463,10 @@ + static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) + { + struct ixgbe_adapter *adapter = q_vector->adapter; +- struct ixgbe_hw *hw = &adapter->hw; + u32 new_itr; + u8 current_itr, ret_itr; +- int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) / +- sizeof(struct ixgbe_q_vector); +- struct ixgbe_ring *rx_ring, *tx_ring; ++ int i, r_idx; ++ struct ixgbe_ring *rx_ring = NULL, *tx_ring = NULL; + + r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); + for (i = 0; i < q_vector->txr_count; i++) { +@@ -902,15 +1515,14 @@ + } + + if (new_itr != q_vector->eitr) { +- u32 itr_reg; ++ + /* do an exponential smoothing */ + new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); ++ ++ /* save the algorithm value here */ + q_vector->eitr = new_itr; +- itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); +- /* must write high and low 16 bits to reset counter */ +- DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx, +- itr_reg); +- IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16); ++ ++ ixgbe_write_eitr(q_vector); + } + + return; +@@ -925,6 +1537,26 @@ + DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); + /* write to clear the interrupt */ + IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); ++ } ++} ++ ++static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) ++{ ++ struct ixgbe_hw *hw = &adapter->hw; ++ ++ if (eicr & IXGBE_EICR_GPI_SDP1) { ++ /* Clear the interrupt */ ++ IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); ++ if (!test_bit(__IXGBE_DOWN, &adapter->state)) ++ schedule_work(&adapter->multispeed_fiber_task); ++ } else if (eicr & IXGBE_EICR_GPI_SDP2) { ++ /* Clear the interrupt */ ++ IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); ++ if (!test_bit(__IXGBE_DOWN, &adapter->state)) ++ schedule_work(&adapter->sfp_config_module_task); ++ } else { ++ /* Interrupt isn't for us... */ ++ return; + } + } + +@@ -946,17 +1578,122 @@ + struct net_device *netdev = data; + struct ixgbe_adapter *adapter = netdev_priv(netdev); + struct ixgbe_hw *hw = &adapter->hw; +- u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); ++ u32 eicr; ++ ++ /* ++ * Workaround of Silicon errata on 82598. Use clear-by-write ++ * instead of clear-by-read to clear EICR , reading EICS gives the ++ * value of EICR without read-clear of EICR ++ */ ++ eicr = IXGBE_READ_REG(hw, IXGBE_EICS); ++ IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); + + if (eicr & IXGBE_EICR_LSC) + ixgbe_check_lsc(adapter); + ++ if (hw->mac.type == ixgbe_mac_82599EB) { ++ if (eicr & IXGBE_EICR_ECC) { ++ DPRINTK(LINK, INFO, "Received unrecoverable ECC Err, " ++ "please reboot\n"); ++ IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); ++ } ++ /* Handle Flow Director Full threshold interrupt */ ++ if (eicr & IXGBE_EICR_FLOW_DIR) { ++ int i; ++ IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR); ++ /* Disable transmits before FDIR Re-initialization */ ++ netif_tx_stop_all_queues(netdev); ++ for (i = 0; i < adapter->num_tx_queues; i++) { ++ struct ixgbe_ring *tx_ring = ++ &adapter->tx_ring[i]; ++ if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE, ++ &tx_ring->reinit_state)) ++ schedule_work(&adapter->fdir_reinit_task); ++ } ++ } ++ } ++ + ixgbe_check_fan_failure(adapter, eicr); + +- if (!test_bit(__IXGBE_DOWN, &adapter->state)) +- IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); +- +- return IRQ_HANDLED; ++ if (hw->mac.type == ixgbe_mac_82599EB) ++ ixgbe_check_sfp_event(adapter, eicr); ++ ++ /* re-enable the original interrupt state, no lsc, no queues */ ++ if (!test_bit(__IXGBE_DOWN, &adapter->state)) ++ IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr & ++ ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE)); ++ ++ return IRQ_HANDLED; ++} ++ ++#ifdef IXGBE_TCP_TIMER ++static irqreturn_t ixgbe_msix_pba(int irq, void *data) ++{ ++ struct net_device *netdev = data; ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); ++ int i; ++ ++ u32 pba = readl(adapter->msix_addr + IXGBE_MSIXPBA); ++ for (i = 0; i < MAX_MSIX_COUNT; i++) { ++ if (pba & (1 << i)) ++ adapter->msix_handlers[i](irq, data, regs); ++ else ++ adapter->pba_zero[i]++; ++ } ++ ++ adapter->msix_pba++; ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t ixgbe_msix_tcp_timer(int irq, void *data) ++{ ++ struct net_device *netdev = data; ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); ++ ++ adapter->msix_tcp_timer++; ++ ++ return IRQ_HANDLED; ++} ++ ++#endif /* IXGBE_TCP_TIMER */ ++static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, ++ u64 qmask) ++{ ++ u32 mask; ++ struct ixgbe_hw *hw = &adapter->hw; ++ ++ if (hw->mac.type == ixgbe_mac_82598EB) { ++ mask = (IXGBE_EIMS_RTX_QUEUE & qmask); ++ IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); ++ } else { ++ mask = (qmask & 0xFFFFFFFF); ++ if (mask) ++ IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); ++ mask = (qmask >> 32); ++ if (mask) ++ IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); ++ } ++ /* skip the flush */ ++} ++ ++static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, ++ u64 qmask) ++{ ++ u32 mask; ++ struct ixgbe_hw *hw = &adapter->hw; ++ ++ if (hw->mac.type == ixgbe_mac_82598EB) { ++ mask = (IXGBE_EIMS_RTX_QUEUE & qmask); ++ IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); ++ } else { ++ mask = (qmask & 0xFFFFFFFF); ++ if (mask) ++ IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); ++ mask = (qmask >> 32); ++ if (mask) ++ IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); ++ } ++ /* skip the flush */ + } + + static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) +@@ -972,16 +1709,30 @@ + r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); + for (i = 0; i < q_vector->txr_count; i++) { + tx_ring = &(adapter->tx_ring[r_idx]); +-#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) +- if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) +- ixgbe_update_tx_dca(adapter, tx_ring); +-#endif + tx_ring->total_bytes = 0; + tx_ring->total_packets = 0; +- ixgbe_clean_tx_irq(adapter, tx_ring); ++#ifndef CONFIG_IXGBE_NAPI ++ ixgbe_clean_tx_irq(q_vector, tx_ring); ++#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) ++ if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) ++ ixgbe_update_tx_dca(adapter, tx_ring); ++#endif ++#endif + r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, + r_idx + 1); + } ++ ++#ifdef CONFIG_IXGBE_NAPI ++ /* disable interrupts on this vector only */ ++ ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx)); ++ napi_schedule(&q_vector->napi); ++#endif ++ /* ++ * possibly later we can enable tx auto-adjustment if necessary ++ * ++ if (adapter->itr_setting & 1) ++ ixgbe_set_itr_msix(q_vector); ++ */ + + return IRQ_HANDLED; + } +@@ -1000,10 +1751,25 @@ + int i; + + r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); +- for (i = 0; i < q_vector->rxr_count; i++) { ++ for (i = 0; i < q_vector->rxr_count; i++) { + rx_ring = &(adapter->rx_ring[r_idx]); + rx_ring->total_bytes = 0; + rx_ring->total_packets = 0; ++#ifndef CONFIG_IXGBE_NAPI ++ ixgbe_clean_rx_irq(q_vector, rx_ring); ++ ++#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) ++ if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) ++ ixgbe_update_rx_dca(adapter, rx_ring); ++ ++#endif ++ r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, ++ r_idx + 1); ++ } ++ ++ if (adapter->itr_setting & 1) ++ ixgbe_set_itr_msix(q_vector); ++#else + r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, + r_idx + 1); + } +@@ -1011,23 +1777,74 @@ + if (!q_vector->rxr_count) + return IRQ_HANDLED; + ++ /* disable interrupts on this vector only */ ++ ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx)); ++ napi_schedule(&q_vector->napi); ++#endif ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) ++{ ++ struct ixgbe_q_vector *q_vector = data; ++ struct ixgbe_adapter *adapter = q_vector->adapter; ++ struct ixgbe_ring *ring; ++ int r_idx; ++ int i; ++ ++ if (!q_vector->txr_count && !q_vector->rxr_count) ++ return IRQ_HANDLED; ++ ++ r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); ++ for (i = 0; i < q_vector->txr_count; i++) { ++ ring = &(adapter->tx_ring[r_idx]); ++ ring->total_bytes = 0; ++ ring->total_packets = 0; ++#ifndef CONFIG_IXGBE_NAPI ++ ixgbe_clean_tx_irq(q_vector, ring); ++#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) ++ if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) ++ ixgbe_update_tx_dca(adapter, ring); ++#endif ++#endif ++ r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, ++ r_idx + 1); ++ } ++ + r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); +- rx_ring = &(adapter->rx_ring[r_idx]); ++ for (i = 0; i < q_vector->rxr_count; i++) { ++ ring = &(adapter->rx_ring[r_idx]); ++ ring->total_bytes = 0; ++ ring->total_packets = 0; ++#ifndef CONFIG_IXGBE_NAPI ++ ixgbe_clean_rx_irq(q_vector, ring); ++ ++#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) ++ if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) ++ ixgbe_update_rx_dca(adapter, ring); ++ ++#endif ++ r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, ++ r_idx + 1); ++ } ++ ++ if (adapter->itr_setting & 1) ++ ixgbe_set_itr_msix(q_vector); ++#else ++ r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, ++ r_idx + 1); ++ } ++ + /* disable interrupts on this vector only */ +- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx); +- netif_rx_schedule(adapter->netdev, &q_vector->napi); +- +- return IRQ_HANDLED; +-} +- +-static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) +-{ +- ixgbe_msix_clean_rx(irq, data); +- ixgbe_msix_clean_tx(irq, data); +- +- return IRQ_HANDLED; +-} +- ++ ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx)); ++ napi_schedule(&q_vector->napi); ++#endif ++ ++ return IRQ_HANDLED; ++} ++ ++#ifdef CONFIG_IXGBE_NAPI + /** + * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine + * @napi: napi struct with our devices info in it +@@ -1052,37 +1869,54 @@ + ixgbe_update_rx_dca(adapter, rx_ring); + #endif + +- ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget); +- ++ ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); ++ ++#ifndef HAVE_NETDEV_NAPI_LIST ++ if (!netif_running(adapter->netdev)) ++ work_done = 0; ++ ++#endif + /* If all Rx work done, exit the polling mode */ + if (work_done < budget) { +- netif_rx_complete(adapter->netdev, napi); +- if (adapter->itr_setting & 3) ++ napi_complete(napi); ++ if (adapter->itr_setting & 1) + ixgbe_set_itr_msix(q_vector); + if (!test_bit(__IXGBE_DOWN, &adapter->state)) +- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx); ++ ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); + } + + return work_done; + } + + /** +- * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine ++ * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine + * @napi: napi struct with our devices info in it + * @budget: amount of work driver is allowed to do this pass, in packets + * + * This function will clean more than one rx queue associated with a + * q_vector. + **/ +-static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget) ++static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget) + { + struct ixgbe_q_vector *q_vector = + container_of(napi, struct ixgbe_q_vector, napi); + struct ixgbe_adapter *adapter = q_vector->adapter; +- struct ixgbe_ring *rx_ring = NULL; +- int work_done = 0, i; ++ struct ixgbe_ring *ring = NULL; ++ int work_done = 0, total_work = 0, i; + long r_idx; +- u16 enable_mask = 0; ++ bool rx_clean_complete = true, tx_clean_complete = true; ++ ++ r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); ++ for (i = 0; i < q_vector->txr_count; i++) { ++ ring = &(adapter->tx_ring[r_idx]); ++#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) ++ if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) ++ ixgbe_update_tx_dca(adapter, ring); ++#endif ++ tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring); ++ r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, ++ r_idx + 1); ++ } + + /* attempt to distribute budget to each queue fairly, but don't allow + * the budget to go below 1 because we'll exit polling */ +@@ -1090,53 +1924,105 @@ + budget = max(budget, 1); + r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); + for (i = 0; i < q_vector->rxr_count; i++) { +- rx_ring = &(adapter->rx_ring[r_idx]); +-#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) +- if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) +- ixgbe_update_rx_dca(adapter, rx_ring); +-#endif +- ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget); +- enable_mask |= rx_ring->v_idx; ++ work_done = 0; ++ ring = &(adapter->rx_ring[r_idx]); ++#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) ++ if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) ++ ixgbe_update_rx_dca(adapter, ring); ++#endif ++ ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget); ++ total_work += work_done; ++ rx_clean_complete &= (work_done < budget); + r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, + r_idx + 1); + } + +- r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); +- rx_ring = &(adapter->rx_ring[r_idx]); ++ if (!tx_clean_complete || !rx_clean_complete) ++ work_done = budget; ++ ++#ifndef HAVE_NETDEV_NAPI_LIST ++ if (!netif_running(adapter->netdev)) ++ work_done = 0; ++ ++#endif + /* If all Rx work done, exit the polling mode */ + if (work_done < budget) { +- netif_rx_complete(adapter->netdev, napi); +- if (adapter->itr_setting & 3) ++ napi_complete(napi); ++ if (adapter->itr_setting & 1) + ixgbe_set_itr_msix(q_vector); + if (!test_bit(__IXGBE_DOWN, &adapter->state)) +- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask); +- return 0; ++ ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); + } + + return work_done; + } ++ ++/** ++ * ixgbe_clean_txonly - msix (aka one shot) tx clean routine ++ * @napi: napi struct with our devices info in it ++ * @budget: amount of work driver is allowed to do this pass, in packets ++ * ++ * This function is optimized for cleaning one queue only on a single ++ * q_vector!!! ++ **/ ++static int ixgbe_clean_txonly(struct napi_struct *napi, int budget) ++{ ++ struct ixgbe_q_vector *q_vector = ++ container_of(napi, struct ixgbe_q_vector, napi); ++ struct ixgbe_adapter *adapter = q_vector->adapter; ++ struct ixgbe_ring *tx_ring = NULL; ++ int work_done = 0; ++ long r_idx; ++ ++ r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); ++ tx_ring = &(adapter->tx_ring[r_idx]); ++#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) ++ if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) ++ ixgbe_update_tx_dca(adapter, tx_ring); ++#endif ++ ++ if (!ixgbe_clean_tx_irq(q_vector, tx_ring)) ++ work_done = budget; ++ ++#ifndef HAVE_NETDEV_NAPI_LIST ++ if (!netif_running(adapter->netdev)) ++ work_done = 0; ++ ++#endif ++ /* If all Rx work done, exit the polling mode */ ++ if (work_done < budget) { ++ napi_complete(napi); ++ if (adapter->itr_setting & 1) ++ ixgbe_set_itr_msix(q_vector); ++ if (!test_bit(__IXGBE_DOWN, &adapter->state)) ++ ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); ++ } ++ ++ return work_done; ++} ++ ++#endif /* CONFIG_IXGBE_NAPI */ + static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, + int r_idx) + { +- a->q_vector[v_idx].adapter = a; +- set_bit(r_idx, a->q_vector[v_idx].rxr_idx); +- a->q_vector[v_idx].rxr_count++; +- a->rx_ring[r_idx].v_idx = 1 << v_idx; ++ struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; ++ ++ set_bit(r_idx, q_vector->rxr_idx); ++ q_vector->rxr_count++; + } + + static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, +- int r_idx) +-{ +- a->q_vector[v_idx].adapter = a; +- set_bit(r_idx, a->q_vector[v_idx].txr_idx); +- a->q_vector[v_idx].txr_count++; +- a->tx_ring[r_idx].v_idx = 1 << v_idx; ++ int t_idx) ++{ ++ struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; ++ ++ set_bit(t_idx, q_vector->txr_idx); ++ q_vector->txr_count++; + } + + /** + * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors + * @adapter: board private structure to initialize +- * @vectors: allotted vector count for descriptor rings + * + * This function maps descriptor rings to the queue-specific vectors + * we were allotted through the MSI-X enabling code. Ideally, we'd have +@@ -1144,9 +2030,9 @@ + * group the rings as "efficiently" as possible. You would add new + * mapping configurations in here. + **/ +-static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, +- int vectors) +-{ ++static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter) ++{ ++ int q_vectors; + int v_start = 0; + int rxr_idx = 0, txr_idx = 0; + int rxr_remaining = adapter->num_rx_queues; +@@ -1159,17 +2045,18 @@ + if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) + goto out; + ++ q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; ++ + /* + * The ideal configuration... + * We have enough vectors to map one per queue. + */ +- if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { ++ if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) { + for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) + map_vector_to_rxq(adapter, v_start, rxr_idx); + + for (; txr_idx < txr_remaining; v_start++, txr_idx++) + map_vector_to_txq(adapter, v_start, txr_idx); +- + goto out; + } + +@@ -1179,16 +2066,16 @@ + * multiple queues per vector. + */ + /* Re-adjusting *qpv takes care of the remainder. */ +- for (i = v_start; i < vectors; i++) { +- rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); ++ for (i = v_start; i < q_vectors; i++) { ++ rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i); + for (j = 0; j < rqpv; j++) { + map_vector_to_rxq(adapter, i, rxr_idx); + rxr_idx++; + rxr_remaining--; + } + } +- for (i = v_start; i < vectors; i++) { +- tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); ++ for (i = v_start; i < q_vectors; i++) { ++ tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i); + for (j = 0; j < tqpv; j++) { + map_vector_to_txq(adapter, i, txr_idx); + txr_idx++; +@@ -1212,27 +2099,36 @@ + struct net_device *netdev = adapter->netdev; + irqreturn_t (*handler)(int, void *); + int i, vector, q_vectors, err; ++ int ri = 0, ti = 0; + + /* Decrement for Other and TCP Timer vectors */ + q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; + +- /* Map the Tx/Rx rings to the vectors we were allotted. */ +- err = ixgbe_map_rings_to_vectors(adapter, q_vectors); +- if (err) +- goto out; +- +-#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ +- (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ +- &ixgbe_msix_clean_many) ++#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \ ++ ? &ixgbe_msix_clean_many : \ ++ (_v)->rxr_count ? &ixgbe_msix_clean_rx : \ ++ (_v)->txr_count ? &ixgbe_msix_clean_tx : \ ++ NULL) + for (vector = 0; vector < q_vectors; vector++) { +- handler = SET_HANDLER(&adapter->q_vector[vector]); +- sprintf(adapter->name[vector], "%s:v%d-%s", +- netdev->name, vector, +- (handler == &ixgbe_msix_clean_rx) ? "Rx" : +- ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx")); ++ struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; ++ handler = SET_HANDLER(q_vector); ++ ++ if (handler == &ixgbe_msix_clean_rx) { ++ sprintf(q_vector->name, "%s-%s-%d", ++ netdev->name, "rx", ri++); ++ } else if (handler == &ixgbe_msix_clean_tx) { ++ sprintf(q_vector->name, "%s-%s-%d", ++ netdev->name, "tx", ti++); ++ } else if (handler == &ixgbe_msix_clean_many) { ++ sprintf(q_vector->name, "%s-%s-%d", ++ netdev->name, "TxRx", vector); ++ } else { ++ /* skip this unused q_vector */ ++ continue; ++ } + err = request_irq(adapter->msix_entries[vector].vector, +- handler, 0, adapter->name[vector], +- &(adapter->q_vector[vector])); ++ handler, 0, q_vector->name, ++ q_vector); + if (err) { + DPRINTK(PROBE, ERR, + "request_irq failed for MSIX interrupt " +@@ -1241,33 +2137,46 @@ + } + } + +- sprintf(adapter->name[vector], "%s:lsc", netdev->name); ++ sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name); + err = request_irq(adapter->msix_entries[vector].vector, +- &ixgbe_msix_lsc, 0, adapter->name[vector], netdev); ++ &ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev); + if (err) { + DPRINTK(PROBE, ERR, +- "request_irq for msix_lsc failed: %d\n", err); ++ "request_irq for msix_lsc failed: %d\n", err); + goto free_queue_irqs; + } + ++#ifdef IXGBE_TCP_TIMER ++ vector++; ++ sprintf(adapter->tcp_timer_name, "%s:timer", netdev->name); ++ err = request_irq(adapter->msix_entries[vector].vector, ++ &ixgbe_msix_tcp_timer, 0, adapter->tcp_timer_name, ++ netdev); ++ if (err) { ++ DPRINTK(PROBE, ERR, ++ "request_irq for msix_tcp_timer failed: %d\n", err); ++ /* Free "Other" interrupt */ ++ free_irq(adapter->msix_entries[--vector].vector, netdev); ++ goto free_queue_irqs; ++ } ++ ++#endif + return 0; + + free_queue_irqs: + for (i = vector - 1; i >= 0; i--) + free_irq(adapter->msix_entries[--vector].vector, +- &(adapter->q_vector[i])); ++ adapter->q_vector[i]); + adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; + pci_disable_msix(adapter->pdev); + kfree(adapter->msix_entries); + adapter->msix_entries = NULL; +-out: + return err; + } + + static void ixgbe_set_itr(struct ixgbe_adapter *adapter) + { +- struct ixgbe_hw *hw = &adapter->hw; +- struct ixgbe_q_vector *q_vector = adapter->q_vector; ++ struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; + u8 current_itr; + u32 new_itr = q_vector->eitr; + struct ixgbe_ring *rx_ring = &adapter->rx_ring[0]; +@@ -1300,58 +2209,135 @@ + } + + if (new_itr != q_vector->eitr) { +- u32 itr_reg; ++ + /* do an exponential smoothing */ + new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); ++ ++ /* save the algorithm value here */ + q_vector->eitr = new_itr; +- itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); +- /* must write high and low 16 bits to reset counter */ +- IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16); ++ ++ ixgbe_write_eitr(q_vector); + } + + return; + } + +-static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter); ++/** ++ * ixgbe_irq_enable - Enable default interrupt generation settings ++ * @adapter: board private structure ++ **/ ++static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, bool flush) ++{ ++ u32 mask; ++ u64 qmask; ++ ++ mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); ++ qmask = ~0; ++ ++ /* don't reenable LSC while waiting for link */ ++ if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) ++ mask &= ~IXGBE_EIMS_LSC; ++ if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) ++ mask |= IXGBE_EIMS_GPI_SDP1; ++ if (adapter->hw.mac.type == ixgbe_mac_82599EB) { ++ mask |= IXGBE_EIMS_ECC; ++ mask |= IXGBE_EIMS_GPI_SDP1; ++ mask |= IXGBE_EIMS_GPI_SDP2; ++ } ++ if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || ++ adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) ++ mask |= IXGBE_EIMS_FLOW_DIR; ++ ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); ++ if (queues) ++ ixgbe_irq_enable_queues(adapter, qmask); ++ if (flush) ++ IXGBE_WRITE_FLUSH(&adapter->hw); ++} + + /** + * ixgbe_intr - legacy mode Interrupt Handler + * @irq: interrupt number + * @data: pointer to a network interface device structure +- * @pt_regs: CPU registers structure + **/ + static irqreturn_t ixgbe_intr(int irq, void *data) + { + struct net_device *netdev = data; + struct ixgbe_adapter *adapter = netdev_priv(netdev); + struct ixgbe_hw *hw = &adapter->hw; ++ struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; + u32 eicr; ++ ++ /* ++ * Workaround of Silicon errata on 82598. Mask the interrupt ++ * before the read of EICR. ++ */ ++ IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); + + /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read + * therefore no explict interrupt disable is necessary */ + eicr = IXGBE_READ_REG(hw, IXGBE_EICR); + if (!eicr) { +- /* shared interrupt alert! ++ /* ++ * shared interrupt alert! + * make sure interrupts are enabled because the read will +- * have disabled interrupts due to EIAM */ +- ixgbe_irq_enable(adapter); +- return IRQ_NONE; /* Not our interrupt */ ++ * have disabled interrupts due to EIAM ++ * finish the workaround of silicon errata on 82598. Unmask ++ * the interrupt that we masked before the EICR read. ++ */ ++ if (!test_bit(__IXGBE_DOWN, &adapter->state)) ++ ixgbe_irq_enable(adapter, true, true); ++ return IRQ_NONE; /* Not our interrupt */ + } + + if (eicr & IXGBE_EICR_LSC) + ixgbe_check_lsc(adapter); + ++ if (hw->mac.type == ixgbe_mac_82599EB) { ++ if (eicr & IXGBE_EICR_ECC) ++ DPRINTK(LINK, INFO, "Received unrecoverable ECC Err, " ++ "please reboot\n"); ++ ixgbe_check_sfp_event(adapter, eicr); ++ } ++ + ixgbe_check_fan_failure(adapter, eicr); + +- if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) { ++#ifdef CONFIG_IXGBE_NAPI ++ if (napi_schedule_prep(&(q_vector->napi))) { + adapter->tx_ring[0].total_packets = 0; + adapter->tx_ring[0].total_bytes = 0; + adapter->rx_ring[0].total_packets = 0; + adapter->rx_ring[0].total_bytes = 0; + /* would disable interrupts here but EIAM disabled it */ +- __netif_rx_schedule(netdev, &adapter->q_vector[0].napi); +- } +- ++ __napi_schedule(&(q_vector->napi)); ++ } ++ ++ /* ++ * re-enable link(maybe) and non-queue interrupts, no flush. ++ * ixgbe_poll will re-enable the queue interrupts ++ */ ++ if (!test_bit(__IXGBE_DOWN, &adapter->state)) ++ ixgbe_irq_enable(adapter, false, false); ++#else ++ adapter->tx_ring[0].total_packets = 0; ++ adapter->tx_ring[0].total_bytes = 0; ++ adapter->rx_ring[0].total_packets = 0; ++ adapter->rx_ring[0].total_bytes = 0; ++ ixgbe_clean_tx_irq(q_vector, adapter->tx_ring); ++ ixgbe_clean_rx_irq(q_vector, adapter->rx_ring); ++ ++ /* dynamically adjust throttle */ ++ if (adapter->itr_setting & 1) ++ ixgbe_set_itr(adapter); ++ ++ /* ++ * Workaround of Silicon errata on 82598. Unmask ++ * the interrupt that we masked before the EICR read ++ * no flush of the re-enable is necessary here ++ */ ++ if (!test_bit(__IXGBE_DOWN, &adapter->state)) ++ ixgbe_irq_enable(adapter, true, false); ++#endif + return IRQ_HANDLED; + } + +@@ -1360,11 +2346,12 @@ + int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; + + for (i = 0; i < q_vectors; i++) { +- struct ixgbe_q_vector *q_vector = &adapter->q_vector[i]; ++ struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; + bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); + bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); + q_vector->rxr_count = 0; + q_vector->txr_count = 0; ++ q_vector->eitr = adapter->eitr_param; + } + } + +@@ -1406,12 +2393,16 @@ + q_vectors = adapter->num_msix_vectors; + + i = q_vectors - 1; ++#ifdef IXGBE_TCP_TIMER + free_irq(adapter->msix_entries[i].vector, netdev); +- + i--; ++#endif ++ free_irq(adapter->msix_entries[i].vector, netdev); ++ i--; ++ + for (; i >= 0; i--) { + free_irq(adapter->msix_entries[i].vector, +- &(adapter->q_vector[i])); ++ adapter->q_vector[i]); + } + + ixgbe_reset_q_vectors(adapter); +@@ -1426,7 +2417,13 @@ + **/ + static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) + { +- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); ++ if (adapter->hw.mac.type == ixgbe_mac_82598EB) { ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); ++ } else { ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); ++ } + IXGBE_WRITE_FLUSH(&adapter->hw); + if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { + int i; +@@ -1438,20 +2435,6 @@ + } + + /** +- * ixgbe_irq_enable - Enable default interrupt generation settings +- * @adapter: board private structure +- **/ +-static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) +-{ +- u32 mask; +- mask = IXGBE_EIMS_ENABLE_MASK; +- if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) +- mask |= IXGBE_EIMS_GPI_SDP1; +- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); +- IXGBE_WRITE_FLUSH(&adapter->hw); +-} +- +-/** + * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts + * + **/ +@@ -1462,8 +2445,8 @@ + IXGBE_WRITE_REG(hw, IXGBE_EITR(0), + EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param)); + +- ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0); +- ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0); ++ ixgbe_set_ivar(adapter, 0, 0, 0); ++ ixgbe_set_ivar(adapter, 1, 0, 0); + + map_vector_to_rxq(adapter, 0, 0); + map_vector_to_txq(adapter, 0, 0); +@@ -1479,9 +2462,10 @@ + **/ + static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) + { +- u64 tdba, tdwba; ++ u64 tdba; + struct ixgbe_hw *hw = &adapter->hw; + u32 i, j, tdlen, txctrl; ++ u32 mask; + + /* Setup the HW Tx Head and Tail descriptor pointers */ + for (i = 0; i < adapter->num_tx_queues; i++) { +@@ -1492,11 +2476,6 @@ + IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), + (tdba & DMA_32BIT_MASK)); + IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); +- tdwba = ring->dma + +- (ring->count * sizeof(union ixgbe_adv_tx_desc)); +- tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE; +- IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK); +- IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32)); + IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); + IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); + IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); +@@ -1509,6 +2488,39 @@ + txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; + IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); + } ++ ++ if (hw->mac.type == ixgbe_mac_82599EB) { ++ u32 rttdcs; ++ ++ /* disable the arbiter while setting MTQC */ ++ rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); ++ rttdcs |= IXGBE_RTTDCS_ARBDIS; ++ IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); ++ ++ /* set transmit pool layout */ ++ mask = IXGBE_FLAG_VMDQ_ENABLED; ++ mask |= IXGBE_FLAG_DCB_ENABLED; ++ switch (adapter->flags & mask) { ++ ++ case (IXGBE_FLAG_VMDQ_ENABLED): ++ IXGBE_WRITE_REG(hw, IXGBE_MTQC, ++ (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); ++ break; ++ ++ case (IXGBE_FLAG_DCB_ENABLED): ++ IXGBE_WRITE_REG(hw, IXGBE_MTQC, ++ (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ)); ++ break; ++ ++ default: ++ IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB); ++ break; ++ } ++ ++ /* re-eable the arbiter */ ++ rttdcs &= ~IXGBE_RTTDCS_ARBDIS; ++ IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); ++ } + } + + #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 +@@ -1517,15 +2529,27 @@ + { + struct ixgbe_ring *rx_ring; + u32 srrctl; +- int queue0; ++ int queue0 = 0; + unsigned long mask; +- +- /* we must program one srrctl register per RSS queue since we +- * have enabled RDRXCTL.MVMEN +- */ +- mask = (unsigned long)adapter->ring_feature[RING_F_RSS].mask; +- queue0 = index & mask; +- index = index & mask; ++ struct ixgbe_ring_feature *feature = adapter->ring_feature; ++ ++ if (adapter->hw.mac.type == ixgbe_mac_82599EB) { ++ if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { ++ int dcb_i = feature[RING_F_DCB].indices; ++ if (dcb_i == 8) ++ queue0 = index >> 4; ++ else if (dcb_i == 4) ++ queue0 = index >> 5; ++ else ++ DPRINTK(PROBE, ERR, "Invalid DCB configuration"); ++ } else { ++ queue0 = index; ++ } ++ } else { ++ mask = (unsigned long) feature[RING_F_RSS].mask; ++ queue0 = index & mask; ++ index = index & mask; ++ } + + rx_ring = &adapter->rx_ring[queue0]; + +@@ -1534,63 +2558,50 @@ + srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; + srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; + ++ srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & ++ IXGBE_SRRCTL_BSIZEHDR_MASK; ++ + if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { +- u16 bufsz = IXGBE_RXBUFFER_2048; +- /* grow the amount we can receive on large page machines */ +- if (bufsz < (PAGE_SIZE / 2)) +- bufsz = (PAGE_SIZE / 2); +- /* cap the bufsz at our largest descriptor size */ +- bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz); +- +- srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; ++#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER ++ srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; ++#else ++ srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; ++#endif + srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; +- srrctl |= ((IXGBE_RX_HDR_SIZE << +- IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & +- IXGBE_SRRCTL_BSIZEHDR_MASK); +- } else { ++ } else { ++ srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> ++ IXGBE_SRRCTL_BSIZEPKT_SHIFT; + srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; +- +- if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE) +- srrctl |= IXGBE_RXBUFFER_2048 >> +- IXGBE_SRRCTL_BSIZEPKT_SHIFT; +- else +- srrctl |= rx_ring->rx_buf_len >> +- IXGBE_SRRCTL_BSIZEPKT_SHIFT; + } + IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); + } + +-#ifdef CONFIG_IXGBE_LRO +-/** +- * ixgbe_get_skb_hdr - helper function for LRO header processing +- * @skb: pointer to sk_buff to be added to LRO packet +- * @iphdr: pointer to ip header structure +- * @tcph: pointer to tcp header structure +- * @hdr_flags: pointer to header flags +- * @priv: private data +- **/ +-static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph, +- u64 *hdr_flags, void *priv) +-{ +- union ixgbe_adv_rx_desc *rx_desc = priv; +- +- /* Verify that this is a valid IPv4 TCP packet */ +- if (!((ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_IPV4) && +- (ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_TCP))) +- return -1; +- +- /* Set network headers */ +- skb_reset_network_header(skb); +- skb_set_transport_header(skb, ip_hdrlen(skb)); +- *iphdr = ip_hdr(skb); +- *tcph = tcp_hdr(skb); +- *hdr_flags = LRO_IPV4 | LRO_TCP; +- return 0; +-} +- +-#endif /* CONFIG_IXGBE_LRO */ +-#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ +- (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) ++ ++static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) ++{ ++ u32 mrqc = 0; ++ int mask; ++ ++ if (!(adapter->hw.mac.type == ixgbe_mac_82599EB)) ++ return mrqc; ++ ++ mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED ++ | IXGBE_FLAG_DCB_ENABLED ++ ); ++ ++ switch (mask) { ++ case (IXGBE_FLAG_RSS_ENABLED): ++ mrqc = IXGBE_MRQC_RSSEN; ++ break; ++ case (IXGBE_FLAG_DCB_ENABLED): ++ mrqc = IXGBE_MRQC_RT8TCEN; ++ break; ++ default: ++ break; ++ } ++ ++ return mrqc; ++} + + /** + * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset +@@ -1610,19 +2621,45 @@ + 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, + 0x6A3E67EA, 0x14364D17, 0x3BED200D}; + u32 fctrl, hlreg0; +- u32 pages; +- u32 reta = 0, mrqc; ++ u32 reta = 0, mrqc = 0; + u32 rdrxctl; ++#ifndef IXGBE_NO_HW_RSC ++ u32 rscctrl; ++#endif /* IXGBE_NO_HW_RSC */ + int rx_buf_len; + + /* Decide whether to use packet split mode or not */ +- adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; ++ if (netdev->mtu > ETH_DATA_LEN) { ++ if (adapter->flags & IXGBE_FLAG_RX_PS_CAPABLE) ++ adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; ++ else ++ adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; ++ } else { ++ if (adapter->flags & IXGBE_FLAG_RX_1BUF_CAPABLE) { ++ adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; ++ } else ++ adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; ++ } + + /* Set the RX buffer length according to the mode */ + if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { + rx_buf_len = IXGBE_RX_HDR_SIZE; +- } else { ++ if (hw->mac.type == ixgbe_mac_82599EB) { ++ /* PSRTYPE must be initialized in 82599 */ ++ u32 psrtype = IXGBE_PSRTYPE_TCPHDR | ++ IXGBE_PSRTYPE_UDPHDR | ++ IXGBE_PSRTYPE_IPV4HDR | ++ IXGBE_PSRTYPE_IPV6HDR | ++ IXGBE_PSRTYPE_L2HDR; ++ IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); ++ } ++ } else { ++#ifndef IXGBE_NO_HW_RSC ++ if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && ++ (netdev->mtu <= ETH_DATA_LEN)) ++#else + if (netdev->mtu <= ETH_DATA_LEN) ++#endif /* IXGBE_NO_HW_RSC */ + rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; + else + rx_buf_len = ALIGN(max_frame, 1024); +@@ -1631,6 +2668,7 @@ + fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); + fctrl |= IXGBE_FCTRL_BAM; + fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ ++ fctrl |= IXGBE_FCTRL_PMCF; + IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); + + hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); +@@ -1640,15 +2678,15 @@ + hlreg0 |= IXGBE_HLREG0_JUMBOEN; + IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); + +- pages = PAGE_USE_COUNT(adapter->netdev->mtu); +- +- rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); + /* disable receives while setting up the descriptors */ + rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); + IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); + +- /* Setup the HW Rx Head and Tail Descriptor Pointers and +- * the Base and Length of the Rx Descriptor Ring */ ++ rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); ++ /* ++ * Setup the HW Rx Head and Tail Descriptor Pointers and ++ * the Base and Length of the Rx Descriptor Ring ++ */ + for (i = 0; i < adapter->num_rx_queues; i++) { + rdba = adapter->rx_ring[i].dma; + j = adapter->rx_ring[i].reg_idx; +@@ -1660,38 +2698,29 @@ + adapter->rx_ring[i].head = IXGBE_RDH(j); + adapter->rx_ring[i].tail = IXGBE_RDT(j); + adapter->rx_ring[i].rx_buf_len = rx_buf_len; +-#ifdef CONFIG_IXGBE_LRO +- /* Intitial LRO Settings */ +- adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE; +- adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS; +- adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr; +- adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID; +- if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) +- adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI; +- adapter->rx_ring[i].lro_mgr.dev = adapter->netdev; +- adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; +- adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; +-#endif + + ixgbe_configure_srrctl(adapter, j); + } + +- /* +- * For VMDq support of different descriptor types or +- * buffer sizes through the use of multiple SRRCTL +- * registers, RDRXCTL.MVMEN must be set to 1 +- * +- * also, the manual doesn't mention it clearly but DCA hints +- * will only use queue 0's tags unless this bit is set. Side +- * effects of setting this bit are only that SRRCTL must be +- * fully programmed [0..15] +- */ +- if (adapter->flags & +- (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) { ++ if (hw->mac.type == ixgbe_mac_82598EB) { ++ /* ++ * For VMDq support of different descriptor types or ++ * buffer sizes through the use of multiple SRRCTL ++ * registers, RDRXCTL.MVMEN must be set to 1 ++ * ++ * also, the manual doesn't mention it clearly but DCA hints ++ * will only use queue 0's tags unless this bit is set. Side ++ * effects of setting this bit are only that SRRCTL must be ++ * fully programmed [0..15] ++ */ + rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); + rdrxctl |= IXGBE_RDRXCTL_MVMEN; + IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); + } ++ ++ ++ /* Program MRQC for the distribution of queues */ ++ mrqc = ixgbe_setup_mrqc(adapter); + + if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { + /* Fill out redirection table */ +@@ -1709,19 +2738,17 @@ + for (i = 0; i < 10; i++) + IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); + +- mrqc = IXGBE_MRQC_RSSEN ++ if (hw->mac.type == ixgbe_mac_82598EB) ++ mrqc |= IXGBE_MRQC_RSSEN; + /* Perform hash on these packet types */ +- | IXGBE_MRQC_RSS_FIELD_IPV4 +- | IXGBE_MRQC_RSS_FIELD_IPV4_TCP +- | IXGBE_MRQC_RSS_FIELD_IPV4_UDP +- | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP +- | IXGBE_MRQC_RSS_FIELD_IPV6_EX +- | IXGBE_MRQC_RSS_FIELD_IPV6 +- | IXGBE_MRQC_RSS_FIELD_IPV6_TCP +- | IXGBE_MRQC_RSS_FIELD_IPV6_UDP +- | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP; +- IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); +- } ++ mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 ++ | IXGBE_MRQC_RSS_FIELD_IPV4_TCP ++ | IXGBE_MRQC_RSS_FIELD_IPV4_UDP ++ | IXGBE_MRQC_RSS_FIELD_IPV6 ++ | IXGBE_MRQC_RSS_FIELD_IPV6_TCP ++ | IXGBE_MRQC_RSS_FIELD_IPV6_UDP; ++ } ++ IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); + + rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); + +@@ -1738,53 +2765,140 @@ + } + + IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); +-} +- ++ ++ if (hw->mac.type == ixgbe_mac_82599EB) { ++ rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); ++#ifndef IXGBE_NO_HW_RSC ++ if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) ++ rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; ++#endif /* IXGBE_NO_HW_RSC */ ++ rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; ++ IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); ++ } ++ ++#ifndef IXGBE_NO_HW_RSC ++ if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { ++ /* Enable 82599 HW RSC */ ++ for (i = 0; i < adapter->num_rx_queues; i++) { ++ j = adapter->rx_ring[i].reg_idx; ++ rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j)); ++ rscctrl |= IXGBE_RSCCTL_RSCEN; ++ /* ++ * we must limit the number of descriptors so that ++ * the total size of max desc * buf_len is not greater ++ * than 65535 ++ */ ++ if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { ++#if (MAX_SKB_FRAGS > 16) ++ rscctrl |= IXGBE_RSCCTL_MAXDESC_16; ++#elif (MAX_SKB_FRAGS > 8) ++ rscctrl |= IXGBE_RSCCTL_MAXDESC_8; ++#elif (MAX_SKB_FRAGS > 4) ++ rscctrl |= IXGBE_RSCCTL_MAXDESC_4; ++#else ++ rscctrl |= IXGBE_RSCCTL_MAXDESC_1; ++#endif ++ } else { ++ if (rx_buf_len < IXGBE_RXBUFFER_4096) ++ rscctrl |= IXGBE_RSCCTL_MAXDESC_16; ++ else if (rx_buf_len < IXGBE_RXBUFFER_8192) ++ rscctrl |= IXGBE_RSCCTL_MAXDESC_8; ++ else ++ rscctrl |= IXGBE_RSCCTL_MAXDESC_4; ++ } ++ ++ ++ IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl); ++ ++ } ++ /* Enable TCP header recognition in PSRTYPE */ ++ IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), ++ (IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)) | ++ IXGBE_PSRTYPE_TCPHDR)); ++ ++ /* Disable RSC for ACK packets */ ++ IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, ++ (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); ++ } ++#endif /* IXGBE_NO_HW_RSC */ ++} ++ ++#ifdef NETIF_F_HW_VLAN_TX + static void ixgbe_vlan_rx_register(struct net_device *netdev, + struct vlan_group *grp) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); + u32 ctrl; ++ int i, j; + + if (!test_bit(__IXGBE_DOWN, &adapter->state)) + ixgbe_irq_disable(adapter); + adapter->vlgrp = grp; + +- /* +- * For a DCB driver, always enable VLAN tag stripping so we can +- * still receive traffic from a DCB-enabled host even if we're +- * not in DCB mode. +- */ +- ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); +- ctrl |= IXGBE_VLNCTRL_VME; +- ctrl &= ~IXGBE_VLNCTRL_CFIEN; +- IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); +- +- if (grp) { ++ if (adapter->hw.mac.type == ixgbe_mac_82598EB) { ++ /* always enable VLAN tag insert/strip */ ++ ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); ++ ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; ++ ctrl &= ~IXGBE_VLNCTRL_CFIEN; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); ++ } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { + /* enable VLAN tag insert/strip */ + ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); +- ctrl |= IXGBE_VLNCTRL_VME; ++ ctrl |= IXGBE_VLNCTRL_VFE; + ctrl &= ~IXGBE_VLNCTRL_CFIEN; + IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); +- } +- +- if (!test_bit(__IXGBE_DOWN, &adapter->state)) +- ixgbe_irq_enable(adapter); ++ for (i = 0; i < adapter->num_rx_queues; i++) { ++ j = adapter->rx_ring[i].reg_idx; ++ ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j)); ++ ctrl |= IXGBE_RXDCTL_VME; ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl); ++ } ++ } ++ ++ if (!test_bit(__IXGBE_DOWN, &adapter->state)) ++ ixgbe_irq_enable(adapter, true, true); + } + + static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); + struct ixgbe_hw *hw = &adapter->hw; ++ int i; ++#ifndef HAVE_NETDEV_VLAN_FEATURES ++ struct net_device *v_netdev; ++#endif /* HAVE_NETDEV_VLAN_FEATURES */ + + /* add VID to filter table */ +- hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true); ++ if (hw->mac.ops.set_vfta) { ++ hw->mac.ops.set_vfta(hw, vid, 0, true); ++ if ((adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) && ++ (adapter->hw.mac.type == ixgbe_mac_82599EB)) { ++ /* enable vlan id for all pools */ ++ for (i = 1; i < adapter->num_rx_pools; i++) { ++ hw->mac.ops.set_vfta(hw, vid, VMDQ_P(i), true); ++ } ++ } ++ } ++#ifndef HAVE_NETDEV_VLAN_FEATURES ++ /* ++ * Copy feature flags from netdev to the vlan netdev for this vid. ++ * This allows things like TSO to bubble down to our vlan device. ++ */ ++ v_netdev = vlan_group_get_device(adapter->vlgrp, vid); ++ v_netdev->features |= adapter->netdev->features; ++ vlan_group_set_device(adapter->vlgrp, vid, v_netdev); ++#endif /* HAVE_NETDEV_VLAN_FEATURES */ + } + + static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); + struct ixgbe_hw *hw = &adapter->hw; ++ int i; ++ ++ /* User is not allowed to remove vlan ID 0 */ ++ if (!vid) ++ return; + + if (!test_bit(__IXGBE_DOWN, &adapter->state)) + ixgbe_irq_disable(adapter); +@@ -1792,15 +2906,29 @@ + vlan_group_set_device(adapter->vlgrp, vid, NULL); + + if (!test_bit(__IXGBE_DOWN, &adapter->state)) +- ixgbe_irq_enable(adapter); +- ++ ixgbe_irq_enable(adapter, true, true); + /* remove VID from filter table */ +- hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false); ++ if (hw->mac.ops.set_vfta) { ++ hw->mac.ops.set_vfta(hw, vid, 0, false); ++ if ((adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) && ++ (adapter->hw.mac.type == ixgbe_mac_82599EB)) { ++ /* remove vlan id from all pools */ ++ for (i = 1; i < adapter->num_rx_pools; i++) { ++ hw->mac.ops.set_vfta(hw, vid, VMDQ_P(i), false); ++ } ++ } ++ } + } + + static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) + { ++ struct ixgbe_hw *hw = &adapter->hw; ++ + ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); ++ ++ /* add vlan ID 0 so we always accept priority-tagged traffic */ ++ if (hw->mac.ops.set_vfta) ++ hw->mac.ops.set_vfta(hw, 0, 0, true); + + if (adapter->vlgrp) { + u16 vid; +@@ -1812,10 +2940,12 @@ + } + } + ++#endif + static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) + { + struct dev_mc_list *mc_ptr; + u8 *addr = *mc_addr_ptr; ++ + *vmdq = 0; + + mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); +@@ -1836,10 +2966,13 @@ + * responsible for configuring the hardware for proper unicast, multicast and + * promiscuous mode. + **/ +-static void ixgbe_set_rx_mode(struct net_device *netdev) +-{ +- struct ixgbe_adapter *adapter = netdev_priv(netdev); +- struct ixgbe_hw *hw = &adapter->hw; ++void ixgbe_set_rx_mode(struct net_device *netdev) ++{ ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); ++ struct ixgbe_hw *hw = &adapter->hw; ++#ifdef HAVE_NETDEV_HW_ADDR ++ struct netdev_hw_addr *ha; ++#endif + u32 fctrl, vlnctrl; + u8 *addr_list = NULL; + int addr_count = 0; +@@ -1862,28 +2995,51 @@ + } + vlnctrl |= IXGBE_VLNCTRL_VFE; + hw->addr_ctrl.user_set_promisc = 0; ++ fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); + } + + IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); + IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); + ++#ifdef HAVE_SET_RX_MODE + /* reprogram secondary unicast list */ ++#ifdef HAVE_NETDEV_HW_ADDR ++ /* ++ * Zero out addr_count and the addr_list. We'll program ++ * the RARs by hand after they've been cleared. ++ */ ++ addr_list = NULL; ++ addr_count = 0; ++#else + addr_count = netdev->uc_count; + if (addr_count) + addr_list = netdev->uc_list->dmi_addr; +- hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count, +- ixgbe_addr_list_itr); +- ++#endif /* HAVE_NETDEV_HW_ADDR */ ++ if (hw->mac.ops.update_uc_addr_list) ++ hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count, ++ ixgbe_addr_list_itr); ++#ifdef HAVE_NETDEV_HW_ADDR ++ if (netdev->uc.count) { ++ /* Program the RARs, one by one */ ++ list_for_each_entry(ha, &netdev->uc.list, list) { ++ ixgbe_add_uc_addr(hw, ha->addr, 0); ++ } ++ } ++ ++#endif /* HAVE_NETDEV_HW_ADDR */ ++#endif /* HAVE_SET_RX_MODE */ + /* reprogram multicast list */ + addr_count = netdev->mc_count; + if (addr_count) + addr_list = netdev->mc_list->dmi_addr; +- hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, +- ixgbe_addr_list_itr); ++ if (hw->mac.ops.update_mc_addr_list) ++ hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, ++ ixgbe_addr_list_itr); + } + + static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) + { ++#ifdef CONFIG_IXGBE_NAPI + int q_idx; + struct ixgbe_q_vector *q_vector; + int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; +@@ -1894,20 +3050,25 @@ + + for (q_idx = 0; q_idx < q_vectors; q_idx++) { + struct napi_struct *napi; +- q_vector = &adapter->q_vector[q_idx]; +- if (!q_vector->rxr_count) +- continue; ++ q_vector = adapter->q_vector[q_idx]; + napi = &q_vector->napi; +- if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) && +- (q_vector->rxr_count > 1)) +- napi->poll = &ixgbe_clean_rxonly_many; ++ if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { ++ if (!q_vector->rxr_count || !q_vector->txr_count) { ++ if (q_vector->txr_count == 1) ++ napi->poll = &ixgbe_clean_txonly; ++ else if (q_vector->rxr_count == 1) ++ napi->poll = &ixgbe_clean_rxonly; ++ } ++ } + + napi_enable(napi); + } ++#endif /* CONFIG_IXGBE_NAPI */ + } + + static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) + { ++#ifdef CONFIG_IXGBE_NAPI + int q_idx; + struct ixgbe_q_vector *q_vector; + int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; +@@ -1917,14 +3078,12 @@ + q_vectors = 1; + + for (q_idx = 0; q_idx < q_vectors; q_idx++) { +- q_vector = &adapter->q_vector[q_idx]; +- if (!q_vector->rxr_count) +- continue; ++ q_vector = adapter->q_vector[q_idx]; + napi_disable(&q_vector->napi); + } +-} +- +-#ifdef CONFIG_IXGBE_DCB ++#endif ++} ++ + /* + * ixgbe_configure_dcb - Configure DCB hardware + * @adapter: ixgbe adapter struct +@@ -1937,11 +3096,18 @@ + { + struct ixgbe_hw *hw = &adapter->hw; + u32 txdctl, vlnctrl; ++ s32 err; + int i, j; + +- ixgbe_dcb_check_config(&adapter->dcb_cfg); +- ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); +- ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); ++ err = ixgbe_dcb_check_config(&adapter->dcb_cfg); ++ if (err) ++ DPRINTK(DRV, ERR, "err in dcb_check_config\n"); ++ err = ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); ++ if (err) ++ DPRINTK(DRV, ERR, "err in dcb_calculate_tc_credits (TX)\n"); ++ err = ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); ++ if (err) ++ DPRINTK(DRV, ERR, "err in dcb_calculate_tc_credits (RX)\n"); + + /* reconfigure the hardware */ + ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); +@@ -1955,38 +3121,252 @@ + } + /* Enable VLAN tag insert/strip */ + vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); +- vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; +- vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; +- IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); +- hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); +-} +-#endif /* CONFIG_IXGBE_DCB */ +- ++ if (hw->mac.type == ixgbe_mac_82598EB) { ++ vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; ++ vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; ++ IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); ++ } else if (hw->mac.type == ixgbe_mac_82599EB) { ++ vlnctrl |= IXGBE_VLNCTRL_VFE; ++ vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; ++ IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); ++ for (i = 0; i < adapter->num_rx_queues; i++) { ++ j = adapter->rx_ring[i].reg_idx; ++ vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); ++ vlnctrl |= IXGBE_RXDCTL_VME; ++ IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); ++ } ++ } ++ if (hw->mac.ops.set_vfta) ++ hw->mac.ops.set_vfta(hw, 0, 0, true); ++} ++ ++#ifndef IXGBE_NO_LLI ++static void ixgbe_configure_lli_82599(struct ixgbe_adapter *adapter) ++{ ++ u16 port; ++ ++ if (adapter->lli_etype) { ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_L34T_IMIR(0), ++ (IXGBE_IMIR_LLI_EN_82599 | IXGBE_IMIR_SIZE_BP_82599 | ++ IXGBE_IMIR_CTRL_BP_82599)); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_ETQS(0), IXGBE_ETQS_LLI); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_ETQF(0), ++ (adapter->lli_etype | IXGBE_ETQF_FILTER_EN)); ++ } ++ ++ if (adapter->lli_port) { ++ port = ntohs((u16)adapter->lli_port); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_L34T_IMIR(0), ++ (IXGBE_IMIR_LLI_EN_82599 | IXGBE_IMIR_SIZE_BP_82599 | ++ IXGBE_IMIR_CTRL_BP_82599)); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_FTQF(0), ++ (IXGBE_FTQF_POOL_MASK_EN | ++ (IXGBE_FTQF_PRIORITY_MASK << ++ IXGBE_FTQF_PRIORITY_SHIFT) | ++ (IXGBE_FTQF_DEST_PORT_MASK << ++ IXGBE_FTQF_5TUPLE_MASK_SHIFT))); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_SDPQF(0), (port << 16)); ++ } ++ ++ if (adapter->flags & IXGBE_FLAG_LLI_PUSH) { ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_L34T_IMIR(0), ++ (IXGBE_IMIR_LLI_EN_82599 | IXGBE_IMIR_SIZE_BP_82599 | ++ IXGBE_IMIR_CTRL_PSH_82599 | IXGBE_IMIR_CTRL_SYN_82599 | ++ IXGBE_IMIR_CTRL_URG_82599 | IXGBE_IMIR_CTRL_ACK_82599 | ++ IXGBE_IMIR_CTRL_RST_82599 | IXGBE_IMIR_CTRL_FIN_82599)); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_FTQF(0), ++ (IXGBE_FTQF_POOL_MASK_EN | ++ (IXGBE_FTQF_PRIORITY_MASK << ++ IXGBE_FTQF_PRIORITY_SHIFT) | ++ (IXGBE_FTQF_5TUPLE_MASK_MASK << ++ IXGBE_FTQF_5TUPLE_MASK_SHIFT))); ++ ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_LLITHRESH, 0xfc000000); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_SYNQF, 0x80000100); ++ } ++ ++ if (adapter->lli_size) { ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_L34T_IMIR(0), ++ (IXGBE_IMIR_LLI_EN_82599 | IXGBE_IMIR_CTRL_BP_82599)); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_LLITHRESH, adapter->lli_size); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_FTQF(0), ++ (IXGBE_FTQF_POOL_MASK_EN | ++ (IXGBE_FTQF_PRIORITY_MASK << ++ IXGBE_FTQF_PRIORITY_SHIFT) | ++ (IXGBE_FTQF_5TUPLE_MASK_MASK << ++ IXGBE_FTQF_5TUPLE_MASK_SHIFT))); ++ } ++ ++ if (adapter->lli_vlan_pri) { ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_IMIRVP, ++ (IXGBE_IMIRVP_PRIORITY_EN | adapter->lli_vlan_pri)); ++ } ++} ++ ++static void ixgbe_configure_lli(struct ixgbe_adapter *adapter) ++{ ++ u16 port; ++ ++ if (adapter->lli_port) { ++ /* use filter 0 for port */ ++ port = ntohs((u16)adapter->lli_port); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_IMIR(0), ++ (port | IXGBE_IMIR_PORT_IM_EN)); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_IMIREXT(0), ++ (IXGBE_IMIREXT_SIZE_BP | ++ IXGBE_IMIREXT_CTRL_BP)); ++ } ++ ++ if (adapter->flags & IXGBE_FLAG_LLI_PUSH) { ++ /* use filter 1 for push flag */ ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_IMIR(1), ++ (IXGBE_IMIR_PORT_BP | IXGBE_IMIR_PORT_IM_EN)); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_IMIREXT(1), ++ (IXGBE_IMIREXT_SIZE_BP | ++ IXGBE_IMIREXT_CTRL_PSH)); ++ } ++ ++ if (adapter->lli_size) { ++ /* use filter 2 for size */ ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_IMIR(2), ++ (IXGBE_IMIR_PORT_BP | IXGBE_IMIR_PORT_IM_EN)); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_IMIREXT(2), ++ (adapter->lli_size | IXGBE_IMIREXT_CTRL_BP)); ++ } ++} ++ ++#endif /* IXGBE_NO_LLI */ + static void ixgbe_configure(struct ixgbe_adapter *adapter) + { + struct net_device *netdev = adapter->netdev; + int i; ++ struct ixgbe_hw *hw = &adapter->hw; + + ixgbe_set_rx_mode(netdev); + ++#ifdef NETIF_F_HW_VLAN_TX + ixgbe_restore_vlan(adapter); +-#ifdef CONFIG_IXGBE_DCB ++#endif + if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { + netif_set_gso_max_size(netdev, 32768); + ixgbe_configure_dcb(adapter); + } else { + netif_set_gso_max_size(netdev, 65536); + } +-#else +- netif_set_gso_max_size(netdev, 65536); +-#endif /* CONFIG_IXGBE_DCB */ +- ++ ++ if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ++ ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc); ++ else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) ++ ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc); + + ixgbe_configure_tx(adapter); + ixgbe_configure_rx(adapter); +- for (i = 0; i < adapter->num_rx_queues; i++) +- ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i], +- (adapter->rx_ring[i].count - 1)); ++ ++ for (i = 0; i < adapter->num_rx_queues; i++) { ++ struct ixgbe_ring *ring = &adapter->rx_ring[i]; ++ ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring)); ++ } ++} ++ ++static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) ++{ ++ switch (hw->phy.type) { ++ case ixgbe_phy_sfp_avago: ++ case ixgbe_phy_sfp_ftl: ++ case ixgbe_phy_sfp_intel: ++ case ixgbe_phy_sfp_unknown: ++ case ixgbe_phy_tw_tyco: ++ case ixgbe_phy_tw_unknown: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++/** ++ * ixgbe_sfp_link_config - set up SFP+ link ++ * @adapter: pointer to private adapter struct ++ **/ ++static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) ++{ ++ struct ixgbe_hw *hw = &adapter->hw; ++ ++ if (hw->phy.multispeed_fiber) { ++ /* ++ * In multispeed fiber setups, the device may not have ++ * had a physical connection when the driver loaded. ++ * If that's the case, the initial link configuration ++ * couldn't get the MAC into 10G or 1G mode, so we'll ++ * never have a link status change interrupt fire. ++ * We need to try and force an autonegotiation ++ * session, then bring up link. ++ */ ++ hw->mac.ops.setup_sfp(hw); ++ if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) ++ schedule_work(&adapter->multispeed_fiber_task); ++ } else { ++ /* ++ * Direct Attach Cu and non-multispeed fiber modules ++ * still need to be configured properly prior to ++ * attempting link. ++ */ ++ if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) ++ schedule_work(&adapter->sfp_config_module_task); ++ } ++} ++ ++/** ++ * ixgbe_non_sfp_link_config - set up non-SFP+ link ++ * @hw: pointer to private hardware struct ++ * ++ * Returns 0 on success, negative on failure ++ **/ ++static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) ++{ ++ u32 autoneg; ++ bool link_up = false; ++ u32 ret = IXGBE_ERR_LINK_SETUP; ++ ++ if (hw->mac.ops.check_link) ++ ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); ++ ++ if (ret) ++ goto link_cfg_out; ++ ++ autoneg = hw->phy.autoneg_advertised; ++ if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) ++ ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, ++ &hw->mac.autoneg); ++ if (ret) ++ goto link_cfg_out; ++ ++ if (hw->mac.ops.setup_link_speed) ++ ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up); ++link_cfg_out: ++ return ret; ++} ++ ++#define IXGBE_MAX_RX_DESC_POLL 10 ++ ++static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, ++ int rxr) ++{ ++ int j = adapter->rx_ring[rxr].reg_idx; ++ int k; ++ ++ for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) { ++ if (IXGBE_READ_REG(&adapter->hw, ++ IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) ++ break; ++ else ++ msleep(1); ++ } ++ if (k >= IXGBE_MAX_RX_DESC_POLL) { ++ DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d " ++ "not set within the polling period\n", rxr); ++ } ++ ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr], ++ (adapter->rx_ring[rxr].count - 1)); + } + + static int ixgbe_up_complete(struct ixgbe_adapter *adapter) +@@ -1995,11 +3375,21 @@ + struct ixgbe_hw *hw = &adapter->hw; + int i, j = 0; + int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; ++ int err; ++#ifdef IXGBE_TCP_TIMER ++ u32 tcp_timer; ++#endif + u32 txdctl, rxdctl, mhadd; ++ u32 dmatxctl; + u32 gpie; + + ixgbe_get_hw_control(adapter); + ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ if (adapter->num_tx_queues > 1) ++ netdev->features |= NETIF_F_MULTI_QUEUE; ++ ++#endif + if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || + (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { + if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { +@@ -2012,21 +3402,40 @@ + /* XXX: to interrupt immediately for EICS writes, enable this */ + /* gpie |= IXGBE_GPIE_EIMEN; */ + IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); +- } +- ++#ifdef IXGBE_TCP_TIMER ++ ++ tcp_timer = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); ++ tcp_timer |= IXGBE_TCPTIMER_DURATION_MASK; ++ tcp_timer |= (IXGBE_TCPTIMER_KS | ++ IXGBE_TCPTIMER_COUNT_ENABLE | ++ IXGBE_TCPTIMER_LOOP); ++ IXGBE_WRITE_REG(hw, IXGBE_TCPTIMER, tcp_timer); ++ tcp_timer = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); ++#endif ++ } ++ ++#ifdef CONFIG_IXGBE_NAPI + if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { + /* legacy interrupts, use EIAM to auto-mask when reading EICR, + * specifically only auto mask tx and rx interrupts */ + IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); + } + +- /* Enable fan failure interrupt if media type is copper */ ++#endif ++ /* Enable fan failure interrupt */ + if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { + gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); + gpie |= IXGBE_SDP1_GPIEN; + IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); + } + ++ if (hw->mac.type == ixgbe_mac_82599EB) { ++ gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); ++ gpie |= IXGBE_SDP1_GPIEN; ++ gpie |= IXGBE_SDP2_GPIEN; ++ IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); ++ } ++ + mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); + if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { + mhadd &= ~IXGBE_MHADD_MFS_MASK; +@@ -2040,43 +3449,121 @@ + txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); + /* enable WTHRESH=8 descriptors, to encourage burst writeback */ + txdctl |= (8 << 16); ++ IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); ++ } ++ ++ if (hw->mac.type == ixgbe_mac_82599EB) { ++ /* DMATXCTL.EN must be set after all Tx queue config is done */ ++ dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); ++ dmatxctl |= IXGBE_DMATXCTL_TE; ++ IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); ++ } ++ ++ for (i = 0; i < adapter->num_tx_queues; i++) { ++ int wait_loop = 10; ++ j = adapter->tx_ring[i].reg_idx; ++ txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); + txdctl |= IXGBE_TXDCTL_ENABLE; + IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); ++ ++ if (hw->mac.type == ixgbe_mac_82599EB) { ++ /* poll for Tx Enable ready */ ++ do { ++ msleep(1); ++ txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); ++ } while (--wait_loop && ++ !(txdctl & IXGBE_TXDCTL_ENABLE)); ++ if (!wait_loop) ++ DPRINTK(DRV, ERR, "Could not enable " ++ "Tx Queue %d\n", j); ++ } + } + + for (i = 0; i < adapter->num_rx_queues; i++) { + j = adapter->rx_ring[i].reg_idx; + rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); +- /* enable PTHRESH=32 descriptors (half the internal cache) +- * and HTHRESH=0 descriptors (to minimize latency on fetch), +- * this also removes a pesky rx_no_buffer_count increment */ +- rxdctl |= 0x0020; ++ if (hw->mac.type == ixgbe_mac_82598EB) { ++ /* ++ * enable cache line friendly hardware writes: ++ * PTHRESH=32 descriptors (half the internal cache), ++ * this also removes ugly rx_no_buffer_count increment ++ * HTHRESH=4 descriptors (to minimize latency on fetch) ++ * WTHRESH=8 burst writeback up to two cachelines ++ */ ++ rxdctl &= ~0x3FFFFF; ++ rxdctl |= 0x080420; ++ } + rxdctl |= IXGBE_RXDCTL_ENABLE; + IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); ++ if (hw->mac.type == ixgbe_mac_82599EB) ++ ixgbe_rx_desc_queue_enable(adapter, i); + } + /* enable all receives */ + rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); +- rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); +- IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl); ++ if (hw->mac.type == ixgbe_mac_82598EB) ++ rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); ++ else ++ rxdctl |= IXGBE_RXCTRL_RXEN; ++ ixgbe_enable_rx_dma(hw, rxdctl); + + if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) + ixgbe_configure_msix(adapter); + else + ixgbe_configure_msi_and_legacy(adapter); +- ++#ifndef IXGBE_NO_LLI ++ /* lli should only be enabled with MSI-X and MSI */ ++ if (adapter->flags & IXGBE_FLAG_MSI_ENABLED || ++ adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { ++ if (adapter->hw.mac.type == ixgbe_mac_82599EB) ++ ixgbe_configure_lli_82599(adapter); ++ else ++ ixgbe_configure_lli(adapter); ++ } ++ ++#endif + clear_bit(__IXGBE_DOWN, &adapter->state); + ixgbe_napi_enable_all(adapter); + +- /* clear any pending interrupts, may auto mask */ +- IXGBE_READ_REG(hw, IXGBE_EICR); +- +- ixgbe_irq_enable(adapter); ++ /* ++ * For hot-pluggable SFP+ devices, a SFP+ module may have arrived ++ * before interrupts were enabled but after probe. Such devices ++ * wouldn't have their type indentified yet. We need to kick off ++ * the SFP+ module setup first, then try to bring up link. If we're ++ * not hot-pluggable SFP+, we just need to configure link and bring ++ * it up. ++ */ ++ if (hw->phy.type == ixgbe_phy_none) { ++ err = hw->phy.ops.identify_sfp(hw); ++ if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { ++ /* ++ * Take the device down and set schedule sfp tasklet ++ * which will unregister_netdev it and log it. ++ */ ++ ixgbe_down(adapter); ++ schedule_work(&adapter->sfp_config_module_task); ++ return err; ++ } ++ } ++ ++ if (ixgbe_is_sfp(hw)) { ++ ixgbe_sfp_link_config(adapter); ++ } else { ++ err = ixgbe_non_sfp_link_config(hw); ++ if (err) ++ DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err); ++ } ++ ++ /* enable transmits */ ++ netif_tx_start_all_queues(netdev); + + /* bring the link up in the watchdog, this could race with our first + * link up interrupt but shouldn't be a problem */ + adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; + adapter->link_check_timeout = jiffies; + mod_timer(&adapter->watchdog_timer, jiffies); ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ set_bit(__IXGBE_FDIR_INIT_DONE, ++ &(adapter->tx_ring[i].reinit_state)); + return 0; + } + +@@ -2092,21 +3579,48 @@ + + int ixgbe_up(struct ixgbe_adapter *adapter) + { +- /* hardware has been reset, we need to reload some things */ ++ int err; ++ struct ixgbe_hw *hw = &adapter->hw; ++ + ixgbe_configure(adapter); + +- return ixgbe_up_complete(adapter); ++ err = ixgbe_up_complete(adapter); ++ ++ /* clear any pending interrupts, may auto mask */ ++ IXGBE_READ_REG(hw, IXGBE_EICR); ++ ixgbe_irq_enable(adapter, true, true); ++ ++ return err; + } + + void ixgbe_reset(struct ixgbe_adapter *adapter) + { + struct ixgbe_hw *hw = &adapter->hw; +- if (hw->mac.ops.init_hw(hw)) +- dev_err(&adapter->pdev->dev, "Hardware Error\n"); ++ int err; ++ ++ err = hw->mac.ops.init_hw(hw); ++ switch (err) { ++ case 0: ++ case IXGBE_ERR_SFP_NOT_PRESENT: ++ break; ++ case IXGBE_ERR_MASTER_REQUESTS_PENDING: ++ DPRINTK(HW, INFO, "master disable timed out\n"); ++ break; ++ case IXGBE_ERR_EEPROM_VERSION: ++ /* We are running on a pre-production device, log a warning */ ++ DPRINTK(PROBE, INFO, "This device is a pre-production adapter/" ++ "LOM. Please be aware there may be issues associated " ++ "with your hardware. If you are experiencing problems " ++ "please contact your Intel or hardware representative " ++ "who provided you with this hardware.\n"); ++ break; ++ default: ++ DPRINTK(PROBE, ERR, "Hardware Error: %d\n", err); ++ } + + /* reprogram the RAR[0] in case user changed it. */ +- hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); +- ++ if (hw->mac.ops.set_rar) ++ hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); + } + + /** +@@ -2115,7 +3629,7 @@ + * @rx_ring: ring to free buffers from + **/ + static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, +- struct ixgbe_ring *rx_ring) ++ struct ixgbe_ring *rx_ring) + { + struct pci_dev *pdev = adapter->pdev; + unsigned long size; +@@ -2134,8 +3648,13 @@ + rx_buffer_info->dma = 0; + } + if (rx_buffer_info->skb) { +- dev_kfree_skb(rx_buffer_info->skb); ++ struct sk_buff *skb = rx_buffer_info->skb; + rx_buffer_info->skb = NULL; ++ do { ++ struct sk_buff *this = skb; ++ skb = skb->prev; ++ dev_kfree_skb(this); ++ } while (skb); + } + if (!rx_buffer_info->page) + continue; +@@ -2156,8 +3675,10 @@ + rx_ring->next_to_clean = 0; + rx_ring->next_to_use = 0; + +- writel(0, adapter->hw.hw_addr + rx_ring->head); +- writel(0, adapter->hw.hw_addr + rx_ring->tail); ++ if (rx_ring->head) ++ writel(0, adapter->hw.hw_addr + rx_ring->head); ++ if (rx_ring->tail) ++ writel(0, adapter->hw.hw_addr + rx_ring->tail); + } + + /** +@@ -2182,14 +3703,15 @@ + size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; + memset(tx_ring->tx_buffer_info, 0, size); + +- /* Zero out the descriptor ring */ + memset(tx_ring->desc, 0, tx_ring->size); + + tx_ring->next_to_use = 0; + tx_ring->next_to_clean = 0; + +- writel(0, adapter->hw.hw_addr + tx_ring->head); +- writel(0, adapter->hw.hw_addr + tx_ring->tail); ++ if (tx_ring->head) ++ writel(0, adapter->hw.hw_addr + tx_ring->head); ++ if (tx_ring->tail) ++ writel(0, adapter->hw.hw_addr + tx_ring->tail); + } + + /** +@@ -2243,7 +3765,14 @@ + ixgbe_napi_disable_all(adapter); + + del_timer_sync(&adapter->watchdog_timer); +- cancel_work_sync(&adapter->watchdog_task); ++ /* can't call flush scheduled work here because it can deadlock ++ * if linkwatch_event tries to acquire the rtnl_lock which we are ++ * holding */ ++ while (adapter->flags & IXGBE_FLAG_IN_WATCHDOG_TASK) ++ msleep(1); ++ if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || ++ adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) ++ cancel_work_sync(&adapter->fdir_reinit_task); + + /* disable transmits in the hardware now that interrupts are off */ + for (i = 0; i < adapter->num_tx_queues; i++) { +@@ -2252,33 +3781,28 @@ + IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), + (txdctl & ~IXGBE_TXDCTL_ENABLE)); + } ++ /* Disable the Tx DMA engine on 82599 */ ++ if (hw->mac.type == ixgbe_mac_82599EB) ++ IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ++ (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & ++ ~IXGBE_DMATXCTL_TE)); + + netif_carrier_off(netdev); + +-#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) +- if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { +- adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; +- dca_remove_requester(&adapter->pdev->dev); +- } +- +-#endif ++#ifdef HAVE_PCI_ERS + if (!pci_channel_offline(adapter->pdev)) ++#endif + ixgbe_reset(adapter); + ixgbe_clean_all_tx_rings(adapter); + ixgbe_clean_all_rx_rings(adapter); + + #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) + /* since we reset the hardware DCA settings were cleared */ +- if (dca_add_requester(&adapter->pdev->dev) == 0) { +- adapter->flags |= IXGBE_FLAG_DCA_ENABLED; +- /* always use CB2 mode, difference is masked +- * in the CB driver */ +- IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); +- ixgbe_setup_dca(adapter); +- } +-#endif +-} +- ++ ixgbe_setup_dca(adapter); ++#endif ++} ++ ++#ifdef CONFIG_IXGBE_NAPI + /** + * ixgbe_poll - NAPI Rx polling callback + * @napi: structure for representing this polling device +@@ -2288,10 +3812,10 @@ + **/ + static int ixgbe_poll(struct napi_struct *napi, int budget) + { +- struct ixgbe_q_vector *q_vector = container_of(napi, +- struct ixgbe_q_vector, napi); +- struct ixgbe_adapter *adapter = q_vector->adapter; +- int tx_cleaned, work_done = 0; ++ struct ixgbe_q_vector *q_vector = ++ container_of(napi, struct ixgbe_q_vector, napi); ++ struct ixgbe_adapter *adapter = q_vector->adapter; ++ int tx_clean_complete, work_done = 0; + + #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) + if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { +@@ -2300,23 +3824,29 @@ + } + #endif + +- tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring); +- ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget); +- +- if (tx_cleaned) ++ tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring); ++ ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget); ++ ++ if (!tx_clean_complete) + work_done = budget; + +- /* If budget not fully consumed, exit the polling mode */ ++#ifndef HAVE_NETDEV_NAPI_LIST ++ if (!netif_running(adapter->netdev)) ++ work_done = 0; ++ ++#endif ++ /* If no Tx and not enough Rx work done, exit the polling mode */ + if (work_done < budget) { +- netif_rx_complete(adapter->netdev, napi); +- if (adapter->itr_setting & 3) ++ napi_complete(napi); ++ if (adapter->itr_setting & 1) + ixgbe_set_itr(adapter); + if (!test_bit(__IXGBE_DOWN, &adapter->state)) +- ixgbe_irq_enable(adapter); ++ ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); + } + return work_done; + } + ++#endif /* CONFIG_IXGBE_NAPI */ + /** + * ixgbe_tx_timeout - Respond to a Tx Hang + * @netdev: network interface device structure +@@ -2344,68 +3874,125 @@ + ixgbe_reinit_locked(adapter); + } + ++ ++/** ++ * ixgbe_set_dcb_queues: Allocate queues for a DCB-enabled device ++ * @adapter: board private structure to initialize ++ * ++ * When DCB (Data Center Bridging) is enabled, allocate queues for ++ * each traffic class. If multiqueue isn't availabe, then abort DCB ++ * initialization. ++ * ++ **/ ++static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) ++{ ++ bool ret = false; ++ struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB]; ++ ++ if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) ++ return ret; ++ ++#ifdef HAVE_TX_MQ ++ f->mask = 0x7 << 3; ++ adapter->num_rx_queues = f->indices; ++ adapter->num_tx_queues = f->indices; ++ ret = true; ++#else ++ DPRINTK(DRV, INFO, "Kernel has no multiqueue support, disabling DCB\n"); ++ f->mask = 0; ++ f->indices = 0; ++#endif ++ ++ return ret; ++} ++ ++/** ++ * ixgbe_set_rss_queues: Allocate queues for RSS ++ * @adapter: board private structure to initialize ++ * ++ * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try ++ * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. ++ * ++ **/ ++static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) ++{ ++ bool ret = false; ++ struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; ++ ++ if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { ++ f->mask = 0xF; ++ adapter->num_rx_queues = f->indices; ++#ifdef HAVE_TX_MQ ++ adapter->num_tx_queues = f->indices; ++#endif ++ ret = true; ++ } ++ ++ return ret; ++} ++ ++/** ++ * ixgbe_set_fdir_queues: Allocate queues for Flow Director ++ * @adapter: board private structure to initialize ++ * ++ * Flow Director is an advanced Rx filter, attempting to get Rx flows back ++ * to the original CPU that initiated the Tx session. This runs in addition ++ * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the ++ * Rx load across CPUs using RSS. ++ * ++ **/ ++static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) ++{ ++ bool ret = false; ++ struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; ++ ++ f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices); ++ f_fdir->mask = 0; ++ ++ /* Flow Director must have RSS enabled */ ++ if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && ++ ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || ++ (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) { ++ adapter->num_rx_queues = f_fdir->indices; ++#ifdef HAVE_TX_MQ ++ adapter->num_tx_queues = f_fdir->indices; ++#endif ++ ret = true; ++ } else { ++ adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; ++ adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; ++ } ++ return ret; ++} ++ ++/* ++ * ixgbe_set_num_queues: Allocate queues for device, feature dependant ++ * @adapter: board private structure to initialize ++ * ++ * This is the top level queue allocation routine. The order here is very ++ * important, starting with the "most" number of features turned on at once, ++ * and ending with the smallest set of features. This way large combinations ++ * can be allocated if they're turned on, and smaller combinations are the ++ * fallthrough conditions. ++ * ++ **/ + static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) + { +- int nrq = 1, ntq = 1; +- int feature_mask = 0, rss_i, rss_m; +- int dcb_i, dcb_m; +- +- /* Number of supported queues */ +- switch (adapter->hw.mac.type) { +- case ixgbe_mac_82598EB: +- dcb_i = adapter->ring_feature[RING_F_DCB].indices; +- dcb_m = 0; +- rss_i = adapter->ring_feature[RING_F_RSS].indices; +- rss_m = 0; +- feature_mask |= IXGBE_FLAG_RSS_ENABLED; +- feature_mask |= IXGBE_FLAG_DCB_ENABLED; +- +- switch (adapter->flags & feature_mask) { +- case (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_DCB_ENABLED): +- dcb_m = 0x7 << 3; +- rss_i = min(8, rss_i); +- rss_m = 0x7; +- nrq = dcb_i * rss_i; +- ntq = min(MAX_TX_QUEUES, dcb_i * rss_i); +- break; +- case (IXGBE_FLAG_DCB_ENABLED): +- dcb_m = 0x7 << 3; +- nrq = dcb_i; +- ntq = dcb_i; +- break; +- case (IXGBE_FLAG_RSS_ENABLED): +- rss_m = 0xF; +- nrq = rss_i; +- ntq = rss_i; +- break; +- case 0: +- default: +- dcb_i = 0; +- dcb_m = 0; +- rss_i = 0; +- rss_m = 0; +- nrq = 1; +- ntq = 1; +- break; +- } +- +- /* Sanity check, we should never have zero queues */ +- nrq = (nrq ?:1); +- ntq = (ntq ?:1); +- +- adapter->ring_feature[RING_F_DCB].indices = dcb_i; +- adapter->ring_feature[RING_F_DCB].mask = dcb_m; +- adapter->ring_feature[RING_F_RSS].indices = rss_i; +- adapter->ring_feature[RING_F_RSS].mask = rss_m; +- break; +- default: +- nrq = 1; +- ntq = 1; +- break; +- } +- +- adapter->num_rx_queues = nrq; +- adapter->num_tx_queues = ntq; ++ /* Start with base case */ ++ adapter->num_rx_queues = 1; ++ adapter->num_tx_queues = 1; ++ adapter->num_rx_pools = adapter->num_rx_queues; ++ adapter->num_rx_queues_per_pool = 1; ++ ++ if (ixgbe_set_dcb_queues(adapter)) ++ return; ++ ++ if (ixgbe_set_fdir_queues(adapter)) ++ return; ++ ++ ++ if (ixgbe_set_rss_queues(adapter)) ++ return; + } + + static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, +@@ -2446,13 +4033,135 @@ + adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; + kfree(adapter->msix_entries); + adapter->msix_entries = NULL; +- adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; +- adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; +- ixgbe_set_num_queues(adapter); + } else { + adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ +- adapter->num_msix_vectors = vectors; +- } ++ /* ++ * Adjust for only the vectors we'll use, which is minimum ++ * of max_msix_q_vectors + NON_Q_VECTORS, or the number of ++ * vectors we were allocated. ++ */ ++ adapter->num_msix_vectors = min(vectors, ++ adapter->max_msix_q_vectors + NON_Q_VECTORS); ++ } ++} ++ ++/** ++ * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS ++ * @adapter: board private structure to initialize ++ * ++ * Cache the descriptor ring offsets for RSS to the assigned rings. ++ * ++ **/ ++static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) ++{ ++ int i; ++ ++ if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) ++ return false; ++ ++ for (i = 0; i < adapter->num_rx_queues; i++) ++ adapter->rx_ring[i].reg_idx = i; ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ adapter->tx_ring[i].reg_idx = i; ++ ++ return true; ++} ++ ++/** ++ * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB ++ * @adapter: board private structure to initialize ++ * ++ * Cache the descriptor ring offsets for DCB to the assigned rings. ++ * ++ **/ ++static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) ++{ ++ int i; ++ bool ret = false; ++ int dcb_i = adapter->ring_feature[RING_F_DCB].indices; ++ ++ if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) ++ return false; ++ ++ /* the number of queues is assumed to be symmetric */ ++ if (adapter->hw.mac.type == ixgbe_mac_82598EB) { ++ for (i = 0; i < dcb_i; i++) { ++ adapter->rx_ring[i].reg_idx = i << 3; ++ adapter->tx_ring[i].reg_idx = i << 2; ++ } ++ ret = true; ++ } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { ++ if (dcb_i == 8) { ++ /* ++ * Tx TC0 starts at: descriptor queue 0 ++ * Tx TC1 starts at: descriptor queue 32 ++ * Tx TC2 starts at: descriptor queue 64 ++ * Tx TC3 starts at: descriptor queue 80 ++ * Tx TC4 starts at: descriptor queue 96 ++ * Tx TC5 starts at: descriptor queue 104 ++ * Tx TC6 starts at: descriptor queue 112 ++ * Tx TC7 starts at: descriptor queue 120 ++ * ++ * Rx TC0-TC7 are offset by 16 queues each ++ */ ++ for (i = 0; i < 3; i++) { ++ adapter->tx_ring[i].reg_idx = i << 5; ++ adapter->rx_ring[i].reg_idx = i << 4; ++ } ++ for ( ; i < 5; i++) { ++ adapter->tx_ring[i].reg_idx = ((i + 2) << 4); ++ adapter->rx_ring[i].reg_idx = i << 4; ++ } ++ for ( ; i < dcb_i; i++) { ++ adapter->tx_ring[i].reg_idx = ((i + 8) << 3); ++ adapter->rx_ring[i].reg_idx = i << 4; ++ } ++ ret = true; ++ } else if (dcb_i == 4) { ++ /* ++ * Tx TC0 starts at: descriptor queue 0 ++ * Tx TC1 starts at: descriptor queue 64 ++ * Tx TC2 starts at: descriptor queue 96 ++ * Tx TC3 starts at: descriptor queue 112 ++ * ++ * Rx TC0-TC3 are offset by 32 queues each ++ */ ++ adapter->tx_ring[0].reg_idx = 0; ++ adapter->tx_ring[1].reg_idx = 64; ++ adapter->tx_ring[2].reg_idx = 96; ++ adapter->tx_ring[3].reg_idx = 112; ++ for (i = 0 ; i < dcb_i; i++) ++ adapter->rx_ring[i].reg_idx = i << 5; ++ ret = true; ++ } ++ } ++ ++ return ret; ++} ++ ++/** ++ * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director ++ * @adapter: board private structure to initialize ++ * ++ * Cache the descriptor ring offsets for Flow Director to the assigned rings. ++ * ++ **/ ++static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) ++{ ++ int i; ++ bool ret = false; ++ ++ if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && ++ ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || ++ (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) { ++ for (i = 0; i < adapter->num_rx_queues; i++) ++ adapter->rx_ring[i].reg_idx = i; ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ adapter->tx_ring[i].reg_idx = i; ++ ret = true; ++ } ++ ++ return ret; + } + + /** +@@ -2461,61 +4170,26 @@ + * + * Once we know the feature-set enabled for the device, we'll cache + * the register offset the descriptor ring is assigned to. +- **/ +-static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) +-{ +- int feature_mask = 0, rss_i; +- int i, txr_idx, rxr_idx; +- int dcb_i; +- +- /* Number of supported queues */ +- switch (adapter->hw.mac.type) { +- case ixgbe_mac_82598EB: +- dcb_i = adapter->ring_feature[RING_F_DCB].indices; +- rss_i = adapter->ring_feature[RING_F_RSS].indices; +- txr_idx = 0; +- rxr_idx = 0; +- feature_mask |= IXGBE_FLAG_DCB_ENABLED; +- feature_mask |= IXGBE_FLAG_RSS_ENABLED; +- switch (adapter->flags & feature_mask) { +- case (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_DCB_ENABLED): +- for (i = 0; i < dcb_i; i++) { +- int j; +- /* Rx first */ +- for (j = 0; j < adapter->num_rx_queues; j++) { +- adapter->rx_ring[rxr_idx].reg_idx = +- i << 3 | j; +- rxr_idx++; +- } +- /* Tx now */ +- for (j = 0; j < adapter->num_tx_queues; j++) { +- adapter->tx_ring[txr_idx].reg_idx = +- i << 2 | (j >> 1); +- if (j & 1) +- txr_idx++; +- } +- } +- case (IXGBE_FLAG_DCB_ENABLED): +- /* the number of queues is assumed to be symmetric */ +- for (i = 0; i < dcb_i; i++) { +- adapter->rx_ring[i].reg_idx = i << 3; +- adapter->tx_ring[i].reg_idx = i << 2; +- } +- break; +- case (IXGBE_FLAG_RSS_ENABLED): +- for (i = 0; i < adapter->num_rx_queues; i++) +- adapter->rx_ring[i].reg_idx = i; +- for (i = 0; i < adapter->num_tx_queues; i++) +- adapter->tx_ring[i].reg_idx = i; +- break; +- case 0: +- default: +- break; +- } +- break; +- default: +- break; +- } ++ * ++ * Note, the order the various feature calls is important. It must start with ++ * the "most" features enabled at the same time, then trickle down to the ++ * least amount of features turned on at once. ++ **/ ++static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) ++{ ++ /* start with default case */ ++ adapter->rx_ring[0].reg_idx = 0; ++ adapter->tx_ring[0].reg_idx = 0; ++ ++ if (ixgbe_cache_ring_dcb(adapter)) ++ return; ++ ++ if (ixgbe_cache_ring_fdir(adapter)) ++ return; ++ ++ if (ixgbe_cache_ring_rss(adapter)) ++ return; ++ + } + + /** +@@ -2537,12 +4211,17 @@ + + adapter->rx_ring = kcalloc(adapter->num_rx_queues, + sizeof(struct ixgbe_ring), GFP_KERNEL); ++ + if (!adapter->rx_ring) + goto err_rx_ring_allocation; + + for (i = 0; i < adapter->num_tx_queues; i++) { + adapter->tx_ring[i].count = adapter->tx_ring_count; + adapter->tx_ring[i].queue_index = i; ++ if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ++ adapter->tx_ring[i].atr_sample_rate = ++ adapter->atr_sample_rate; ++ adapter->tx_ring[i].atr_count = 0; + } + + for (i = 0; i < adapter->num_rx_queues; i++) { +@@ -2569,8 +4248,12 @@ + **/ + static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) + { ++ struct ixgbe_hw *hw = &adapter->hw; + int err = 0; + int vector, v_budget; ++ ++ if (!(adapter->flags & IXGBE_FLAG_MSIX_CAPABLE)) ++ goto try_msi; + + /* + * It's easy to be greedy for MSI-X vectors, but it really +@@ -2583,60 +4266,176 @@ + + /* + * At the same time, hardware can only support a maximum of +- * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq, +- * we can easily reach upwards of 64 Rx descriptor queues and +- * 32 Tx queues. Thus, we cap it off in those rare cases where +- * the cpu count also exceeds our vector limit. +- */ +- v_budget = min(v_budget, MAX_MSIX_COUNT); ++ * hw.mac->max_msix_vectors vectors. With features ++ * such as RSS and VMDq, we can easily surpass the number of Rx and Tx ++ * descriptor queues supported by our device. Thus, we cap it off in ++ * those rare cases where the cpu count also exceeds our vector limit. ++ */ ++ v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); + + /* A failure in MSI-X entry allocation isn't fatal, but it does + * mean we disable MSI-X capabilities of the adapter. */ + adapter->msix_entries = kcalloc(v_budget, + sizeof(struct msix_entry), GFP_KERNEL); +- if (!adapter->msix_entries) { +- adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; +- adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; +- ixgbe_set_num_queues(adapter); +- kfree(adapter->tx_ring); +- kfree(adapter->rx_ring); +- err = ixgbe_alloc_queues(adapter); +- if (err) { +- DPRINTK(PROBE, ERR, "Unable to allocate memory " +- "for queues\n"); ++ if (adapter->msix_entries) { ++ for (vector = 0; vector < v_budget; vector++) ++ adapter->msix_entries[vector].entry = vector; ++ ++ ixgbe_acquire_msix_vectors(adapter, v_budget); ++ ++ if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) + goto out; +- } +- +- goto try_msi; +- } +- +- for (vector = 0; vector < v_budget; vector++) +- adapter->msix_entries[vector].entry = vector; +- +- ixgbe_acquire_msix_vectors(adapter, v_budget); +- +- if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ++ ++ } ++ ++ adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; ++ adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; ++ adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; ++ adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; ++ adapter->atr_sample_rate = 0; ++ adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; ++ ixgbe_set_num_queues(adapter); ++ ++try_msi: ++ if (!(adapter->flags & IXGBE_FLAG_MSI_CAPABLE)) + goto out; + +-try_msi: + err = pci_enable_msi(adapter->pdev); + if (!err) { + adapter->flags |= IXGBE_FLAG_MSI_ENABLED; + } else { + DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " +- "falling back to legacy. Error: %d\n", err); ++ "falling back to legacy. Error: %d\n", err); + /* reset err */ + err = 0; + } + + out: ++#ifdef HAVE_TX_MQ + /* Notify the stack of the (possibly) reduced Tx Queue count. */ ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ adapter->netdev->egress_subqueue_count = adapter->num_tx_queues; ++#else + adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; +- +- return err; +-} +- +-void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) ++#endif ++#endif /* HAVE_TX_MQ */ ++ return err; ++} ++ ++/** ++ * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors ++ * @adapter: board private structure to initialize ++ * ++ * We allocate one q_vector per queue interrupt. If allocation fails we ++ * return -ENOMEM. ++ **/ ++static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) ++{ ++ int v_idx, num_q_vectors; ++ struct ixgbe_q_vector *q_vector; ++ int rx_vectors; ++#ifdef CONFIG_IXGBE_NAPI ++ int (*poll)(struct napi_struct *, int); ++#endif ++ ++ if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { ++ num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; ++ rx_vectors = adapter->num_rx_queues; ++#ifdef CONFIG_IXGBE_NAPI ++ poll = &ixgbe_clean_rxtx_many; ++#endif ++ } else { ++ num_q_vectors = 1; ++ rx_vectors = 1; ++#ifdef CONFIG_IXGBE_NAPI ++ poll = &ixgbe_poll; ++#endif ++ } ++ ++ for (v_idx = 0; v_idx < num_q_vectors; v_idx++) { ++ q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL); ++ if (!q_vector) ++ goto err_out; ++ q_vector->adapter = adapter; ++ q_vector->eitr = adapter->eitr_param; ++ q_vector->v_idx = v_idx; ++#ifndef IXGBE_NO_LRO ++ if (v_idx < rx_vectors) { ++ int size = sizeof(struct ixgbe_lro_list); ++ q_vector->lrolist = vmalloc(size); ++ if (!q_vector->lrolist) { ++ kfree(q_vector); ++ goto err_out; ++ } ++ memset(q_vector->lrolist, 0, size); ++ ixgbe_lro_ring_init(q_vector->lrolist); ++ } ++#endif ++#ifdef CONFIG_IXGBE_NAPI ++ netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); ++#endif ++ adapter->q_vector[v_idx] = q_vector; ++ } ++ ++ return 0; ++ ++err_out: ++ while (v_idx) { ++ v_idx--; ++ q_vector = adapter->q_vector[v_idx]; ++#ifdef CONFIG_IXGBE_NAPI ++ netif_napi_del(&q_vector->napi); ++#endif ++#ifndef IXGBE_NO_LRO ++ if (q_vector->lrolist) { ++ ixgbe_lro_ring_exit(q_vector->lrolist); ++ vfree(q_vector->lrolist); ++ q_vector->lrolist = NULL; ++ } ++#endif ++ kfree(q_vector); ++ adapter->q_vector[v_idx] = NULL; ++ } ++ return -ENOMEM; ++} ++ ++/** ++ * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors ++ * @adapter: board private structure to initialize ++ * ++ * This function frees the memory allocated to the q_vectors. In addition if ++ * NAPI is enabled it will delete any references to the NAPI struct prior ++ * to freeing the q_vector. ++ **/ ++static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) ++{ ++ int v_idx, num_q_vectors; ++ ++ if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { ++ num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; ++ } else { ++ num_q_vectors = 1; ++ } ++ ++ for (v_idx = 0; v_idx < num_q_vectors; v_idx++) { ++ struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx]; ++ ++ adapter->q_vector[v_idx] = NULL; ++#ifdef CONFIG_IXGBE_NAPI ++ netif_napi_del(&q_vector->napi); ++#endif ++#ifndef IXGBE_NO_LRO ++ if (q_vector->lrolist) { ++ ixgbe_lro_ring_exit(q_vector->lrolist); ++ vfree(q_vector->lrolist); ++ q_vector->lrolist = NULL; ++ } ++#endif ++ kfree(q_vector); ++ } ++} ++ ++static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) + { + if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { + adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; +@@ -2667,32 +4466,57 @@ + /* Number of supported queues */ + ixgbe_set_num_queues(adapter); + ++ err = ixgbe_set_interrupt_capability(adapter); ++ if (err) { ++ DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); ++ goto err_set_interrupt; ++ } ++ ++ err = ixgbe_alloc_q_vectors(adapter); ++ if (err) { ++ DPRINTK(PROBE, ERR, "Unable to allocate memory for queue " ++ "vectors\n"); ++ goto err_alloc_q_vectors; ++ } ++ + err = ixgbe_alloc_queues(adapter); + if (err) { + DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); + goto err_alloc_queues; + } + +- err = ixgbe_set_interrupt_capability(adapter); +- if (err) { +- DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); +- goto err_set_interrupt; +- } +- + DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " +- "Tx Queue count = %u\n", ++ "Tx Queue count = %u\n", + (adapter->num_rx_queues > 1) ? "Enabled" : + "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); + + set_bit(__IXGBE_DOWN, &adapter->state); + + return 0; +- ++err_alloc_queues: ++ ixgbe_free_q_vectors(adapter); ++err_alloc_q_vectors: ++ ixgbe_reset_interrupt_capability(adapter); + err_set_interrupt: ++ return err; ++} ++ ++/** ++ * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings ++ * @adapter: board private structure to clear interrupt scheme on ++ * ++ * We go through and clear interrupt specific resources and reset the structure ++ * to pre-load conditions ++ **/ ++void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) ++{ + kfree(adapter->tx_ring); + kfree(adapter->rx_ring); +-err_alloc_queues: +- return err; ++ adapter->tx_ring = NULL; ++ adapter->rx_ring = NULL; ++ ++ ixgbe_free_q_vectors(adapter); ++ ixgbe_reset_interrupt_capability(adapter); + } + + /** +@@ -2715,25 +4539,26 @@ + static void ixgbe_sfp_task(struct work_struct *work) + { + struct ixgbe_adapter *adapter = container_of(work, +- struct ixgbe_adapter, +- sfp_task); ++ struct ixgbe_adapter, ++ sfp_task); + struct ixgbe_hw *hw = &adapter->hw; + + if ((hw->phy.type == ixgbe_phy_nl) && + (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { + s32 ret = hw->phy.ops.identify_sfp(hw); +- if (ret) ++ if (ret && ret != IXGBE_ERR_SFP_NOT_SUPPORTED) + goto reschedule; + ret = hw->phy.ops.reset(hw); + if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { + DPRINTK(PROBE, ERR, "failed to initialize because an " +- "unsupported SFP+ module type was detected.\n" +- "Reload the driver after installing a " +- "supported module.\n"); ++ "unsupported SFP+ module type was detected.\n" ++ "Reload the driver after installing a " ++ "supported module.\n"); + unregister_netdev(adapter->netdev); ++ adapter->netdev_registered = false; + } else { + DPRINTK(PROBE, INFO, "detected SFP+: %d\n", +- hw->phy.sfp_type); ++ hw->phy.sfp_type); + } + /* don't need this routine any more */ + clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); +@@ -2742,7 +4567,7 @@ + reschedule: + if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) + mod_timer(&adapter->sfp_timer, +- round_jiffies(jiffies + (2 * HZ))); ++ round_jiffies(jiffies + (2 * HZ))); + } + + /** +@@ -2757,62 +4582,100 @@ + { + struct ixgbe_hw *hw = &adapter->hw; + struct pci_dev *pdev = adapter->pdev; +- unsigned int rss; +-#ifdef CONFIG_IXGBE_DCB +- int j; +- struct tc_configuration *tc; +-#endif /* CONFIG_IXGBE_DCB */ ++ int err; + + /* PCI config space info */ + + hw->vendor_id = pdev->vendor; + hw->device_id = pdev->device; +- hw->revision_id = pdev->revision; ++ pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); + hw->subsystem_vendor_id = pdev->subsystem_vendor; + hw->subsystem_device_id = pdev->subsystem_device; + ++ err = ixgbe_init_shared_code(hw); ++ if (err) { ++ DPRINTK(PROBE, ERR, "init_shared_code failed: %d\n", err); ++ goto out; ++ } ++ + /* Set capability flags */ +- rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); +- adapter->ring_feature[RING_F_RSS].indices = rss; +- adapter->flags |= IXGBE_FLAG_RSS_ENABLED; +- if (hw->mac.ops.get_media_type && +- (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) +- adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; +- adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; +- +-#ifdef CONFIG_IXGBE_DCB +- /* Configure DCB traffic classes */ +- for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { +- tc = &adapter->dcb_cfg.tc_config[j]; +- tc->path[DCB_TX_CONFIG].bwg_id = 0; +- tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); +- tc->path[DCB_RX_CONFIG].bwg_id = 0; +- tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); +- tc->dcb_pfc = pfc_disabled; +- } +- adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; +- adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; +- adapter->dcb_cfg.rx_pba_cfg = pba_equal; +- adapter->dcb_cfg.round_robin_enable = false; +- adapter->dcb_set_bitmap = 0x00; ++ switch (hw->mac.type) { ++ case ixgbe_mac_82598EB: ++ if (hw->device_id == IXGBE_DEV_ID_82598AT) ++ adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; ++ adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; ++ adapter->flags |= IXGBE_FLAG_MSI_CAPABLE; ++ adapter->flags |= IXGBE_FLAG_MSIX_CAPABLE; ++ if (adapter->flags & IXGBE_FLAG_MSIX_CAPABLE) ++ adapter->flags |= IXGBE_FLAG_MQ_CAPABLE; ++ if (adapter->flags & IXGBE_FLAG_MQ_CAPABLE) ++ adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; ++#ifdef IXGBE_RSS ++ if (adapter->flags & IXGBE_FLAG_MQ_CAPABLE) ++ adapter->flags |= IXGBE_FLAG_RSS_CAPABLE; ++#endif ++#ifndef IXGBE_NO_HW_RSC ++ adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; ++#endif ++ adapter->max_msix_q_vectors = IXGBE_MAX_MSIX_Q_VECTORS_82598; ++ break; ++ case ixgbe_mac_82599EB: ++#ifndef IXGBE_NO_HW_RSC ++ adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; ++#endif ++ adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; ++ adapter->flags |= IXGBE_FLAG_MSI_CAPABLE; ++ adapter->flags |= IXGBE_FLAG_MSIX_CAPABLE; ++ if (adapter->flags & IXGBE_FLAG_MSIX_CAPABLE) ++ adapter->flags |= IXGBE_FLAG_MQ_CAPABLE; ++ if (adapter->flags & IXGBE_FLAG_MQ_CAPABLE) ++ adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; ++#ifdef IXGBE_RSS ++ if (adapter->flags & IXGBE_FLAG_MQ_CAPABLE) ++ adapter->flags |= IXGBE_FLAG_RSS_CAPABLE; ++#endif ++ adapter->max_msix_q_vectors = IXGBE_MAX_MSIX_Q_VECTORS_82599; ++ break; ++ default: ++ break; ++ } ++ ++ /* Default DCB settings, if applicable */ ++ adapter->ring_feature[RING_F_DCB].indices = 8; ++ if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) { ++ int j; ++ struct tc_configuration *tc; ++ for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { ++ tc = &adapter->dcb_cfg.tc_config[j]; ++ tc->path[DCB_TX_CONFIG].bwg_id = 0; ++ tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); ++ tc->path[DCB_RX_CONFIG].bwg_id = 0; ++ tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); ++ tc->dcb_pfc = pfc_disabled; ++ } ++ adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; ++ adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; ++ adapter->dcb_cfg.rx_pba_cfg = pba_equal; ++ adapter->dcb_cfg.pfc_mode_enable = false; ++ adapter->dcb_cfg.round_robin_enable = false; ++ adapter->dcb_set_bitmap = 0x00; ++ } ++#ifdef CONFIG_DCB + ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, + adapter->ring_feature[RING_F_DCB].indices); +-#endif /* CONFIG_IXGBE_DCB */ ++#endif ++ ++ + + /* default flow control settings */ +- hw->fc.original_type = ixgbe_fc_none; +- hw->fc.type = ixgbe_fc_none; ++ hw->fc.requested_mode = ixgbe_fc_full; ++ hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ ++ adapter->last_lfc_mode = hw->fc.current_mode; + hw->fc.high_water = IXGBE_DEFAULT_FCRTH; + hw->fc.low_water = IXGBE_DEFAULT_FCRTL; + hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; + hw->fc.send_xon = true; +- +- /* select 10G link by default */ +- hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN; +- +- /* enable itr by default in dynamic mode */ +- adapter->itr_setting = 1; +- adapter->eitr_param = 20000; ++ hw->fc.disable_fc_autoneg = false; + + /* set defaults for eitr in MegaBytes */ + adapter->eitr_low = 10; +@@ -2822,18 +4685,12 @@ + adapter->tx_ring_count = IXGBE_DEFAULT_TXD; + adapter->rx_ring_count = IXGBE_DEFAULT_RXD; + +- /* initialize eeprom parameters */ +- if (ixgbe_init_eeprom_params_generic(hw)) { +- dev_err(&pdev->dev, "EEPROM initialization failed\n"); +- return -EIO; +- } +- + /* enable rx csum by default */ + adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; + + set_bit(__IXGBE_DOWN, &adapter->state); +- +- return 0; ++out: ++ return err; + } + + /** +@@ -2856,8 +4713,7 @@ + memset(tx_ring->tx_buffer_info, 0, size); + + /* round up to nearest 4K */ +- tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) + +- sizeof(u32); ++ tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); + tx_ring->size = ALIGN(tx_ring->size, 4096); + + tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, +@@ -2899,7 +4755,6 @@ + DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); + break; + } +- + return err; + } + +@@ -2916,18 +4771,12 @@ + struct pci_dev *pdev = adapter->pdev; + int size; + +-#ifdef CONFIG_IXGBE_LRO +- size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS; +- rx_ring->lro_mgr.lro_arr = vmalloc(size); +- if (!rx_ring->lro_mgr.lro_arr) +- return -ENOMEM; +- memset(rx_ring->lro_mgr.lro_arr, 0, size); +-#endif + size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; + rx_ring->rx_buffer_info = vmalloc(size); + if (!rx_ring->rx_buffer_info) { + DPRINTK(PROBE, ERR, +- "vmalloc allocation failed for the rx desc ring\n"); ++ "Unable to vmalloc buffer memory for " ++ "the receive descriptor ring\n"); + goto alloc_failed; + } + memset(rx_ring->rx_buffer_info, 0, size); +@@ -2940,21 +4789,21 @@ + + if (!rx_ring->desc) { + DPRINTK(PROBE, ERR, +- "Memory allocation failed for the rx desc ring\n"); ++ "Unable to allocate memory for " ++ "the receive descriptor ring\n"); + vfree(rx_ring->rx_buffer_info); ++ rx_ring->rx_buffer_info = NULL; + goto alloc_failed; + } + + rx_ring->next_to_clean = 0; + rx_ring->next_to_use = 0; +- +- return 0; +- ++#ifndef CONFIG_IXGBE_NAPI ++ rx_ring->work_limit = rx_ring->count / 2; ++#endif ++ ++ return 0; + alloc_failed: +-#ifdef CONFIG_IXGBE_LRO +- vfree(rx_ring->lro_mgr.lro_arr); +- rx_ring->lro_mgr.lro_arr = NULL; +-#endif + return -ENOMEM; + } + +@@ -2968,7 +4817,6 @@ + * + * Return 0 on success, negative on failure + **/ +- + static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) + { + int i, err = 0; +@@ -2980,7 +4828,6 @@ + DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); + break; + } +- + return err; + } + +@@ -3017,7 +4864,8 @@ + int i; + + for (i = 0; i < adapter->num_tx_queues; i++) +- ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); ++ if (adapter->tx_ring[i].desc) ++ ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); + } + + /** +@@ -3032,11 +4880,6 @@ + { + struct pci_dev *pdev = adapter->pdev; + +-#ifdef CONFIG_IXGBE_LRO +- vfree(rx_ring->lro_mgr.lro_arr); +- rx_ring->lro_mgr.lro_arr = NULL; +-#endif +- + ixgbe_clean_rx_ring(adapter, rx_ring); + + vfree(rx_ring->rx_buffer_info); +@@ -3058,7 +4901,8 @@ + int i; + + for (i = 0; i < adapter->num_rx_queues; i++) +- ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); ++ if (adapter->rx_ring[i].desc) ++ ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); + } + + /** +@@ -3103,12 +4947,15 @@ + static int ixgbe_open(struct net_device *netdev) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); ++ struct ixgbe_hw *hw = &adapter->hw; + int err; + + /* disallow open during test */ + if (test_bit(__IXGBE_TESTING, &adapter->state)) + return -EBUSY; + ++ netif_carrier_off(netdev); ++ + /* allocate transmit descriptors */ + err = ixgbe_setup_all_tx_resources(adapter); + if (err) +@@ -3121,26 +4968,47 @@ + + ixgbe_configure(adapter); + ++ /* ++ * Map the Tx/Rx rings to the vectors we were allotted. ++ * if request_irq will be called in this function map_rings ++ * must be called *before* up_complete ++ */ ++ ixgbe_map_rings_to_vectors(adapter); ++ ++ err = ixgbe_up_complete(adapter); ++ if (err) ++ goto err_setup_rx; ++ ++ /* clear any pending interrupts, may auto mask */ ++ IXGBE_READ_REG(hw, IXGBE_EICR); ++ + err = ixgbe_request_irq(adapter); + if (err) + goto err_req_irq; + +- err = ixgbe_up_complete(adapter); +- if (err) +- goto err_up; +- +- netif_tx_start_all_queues(netdev); +- +- return 0; +- +-err_up: ++ ixgbe_irq_enable(adapter, true, true); ++ ++ /* ++ * If this adapter has a fan, check to see if we had a failure ++ * before we enabled the interrupt. ++ */ ++ if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { ++ u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); ++ if (esdp & IXGBE_ESDP_SDP1) ++ DPRINTK(DRV, CRIT, ++ "Fan has stopped, replace the adapter\n"); ++ } ++ ++ return 0; ++ ++err_req_irq: ++ ixgbe_down(adapter); + ixgbe_release_hw_control(adapter); + ixgbe_free_irq(adapter); +-err_req_irq: ++err_setup_rx: + ixgbe_free_all_rx_resources(adapter); +-err_setup_rx: ++err_setup_tx: + ixgbe_free_all_tx_resources(adapter); +-err_setup_tx: + ixgbe_reset(adapter); + + return err; +@@ -3172,49 +5040,6 @@ + return 0; + } + +-/** +- * ixgbe_napi_add_all - prep napi structs for use +- * @adapter: private struct +- * helper function to napi_add each possible q_vector->napi +- */ +-void ixgbe_napi_add_all(struct ixgbe_adapter *adapter) +-{ +- int q_idx, q_vectors; +- int (*poll)(struct napi_struct *, int); +- +- if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { +- poll = &ixgbe_clean_rxonly; +- /* Only enable as many vectors as we have rx queues. */ +- q_vectors = adapter->num_rx_queues; +- } else { +- poll = &ixgbe_poll; +- /* only one q_vector for legacy modes */ +- q_vectors = 1; +- } +- +- for (q_idx = 0; q_idx < q_vectors; q_idx++) { +- struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx]; +- netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); +- } +-} +- +-void ixgbe_napi_del_all(struct ixgbe_adapter *adapter) +-{ +- int q_idx; +- int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; +- +- /* legacy and MSI only use one vector */ +- if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) +- q_vectors = 1; +- +- for (q_idx = 0; q_idx < q_vectors; q_idx++) { +- struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx]; +- if (!q_vector->rxr_count) +- continue; +- netif_napi_del(&q_vector->napi); +- } +-} +- + #ifdef CONFIG_PM + static int ixgbe_resume(struct pci_dev *pdev) + { +@@ -3227,23 +5052,23 @@ + err = pci_enable_device(pdev); + if (err) { + printk(KERN_ERR "ixgbe: Cannot enable PCI device from " +- "suspend\n"); ++ "suspend\n"); + return err; + } + pci_set_master(pdev); + +- pci_enable_wake(pdev, PCI_D3hot, 0); +- pci_enable_wake(pdev, PCI_D3cold, 0); ++ pci_wake_from_d3(pdev, false); + + err = ixgbe_init_interrupt_scheme(adapter); + if (err) { + printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " +- "device\n"); ++ "device\n"); + return err; + } + +- ixgbe_napi_add_all(adapter); + ixgbe_reset(adapter); ++ ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); + + if (netif_running(netdev)) { + err = ixgbe_open(adapter->netdev); +@@ -3255,12 +5080,14 @@ + + return 0; + } +- + #endif /* CONFIG_PM */ +-static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) ++static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) + { + struct net_device *netdev = pci_get_drvdata(pdev); + struct ixgbe_adapter *adapter = netdev_priv(netdev); ++ struct ixgbe_hw *hw = &adapter->hw; ++ u32 ctrl, fctrl; ++ u32 wufc = adapter->wol; + #ifdef CONFIG_PM + int retval = 0; + #endif +@@ -3273,34 +5100,84 @@ + ixgbe_free_all_tx_resources(adapter); + ixgbe_free_all_rx_resources(adapter); + } +- ixgbe_reset_interrupt_capability(adapter); +- ixgbe_napi_del_all(adapter); +- kfree(adapter->tx_ring); +- kfree(adapter->rx_ring); ++ ++ ixgbe_clear_interrupt_scheme(adapter); + + #ifdef CONFIG_PM + retval = pci_save_state(pdev); + if (retval) + return retval; +-#endif +- +- pci_enable_wake(pdev, PCI_D3hot, 0); +- pci_enable_wake(pdev, PCI_D3cold, 0); ++ ++#endif ++ if (wufc) { ++ ixgbe_set_rx_mode(netdev); ++ ++ /* turn on all-multi mode if wake on multicast is enabled */ ++ if (wufc & IXGBE_WUFC_MC) { ++ fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); ++ fctrl |= IXGBE_FCTRL_MPE; ++ IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); ++ } ++ ++ ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); ++ ctrl |= IXGBE_CTRL_GIO_DIS; ++ IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); ++ ++ IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); ++ } else { ++ IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); ++ IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); ++ } ++ ++ if (wufc && hw->mac.type == ixgbe_mac_82599EB) ++ pci_wake_from_d3(pdev, true); ++ else ++ pci_wake_from_d3(pdev, false); ++ ++ *enable_wake = !!wufc; + + ixgbe_release_hw_control(adapter); + + pci_disable_device(pdev); + +- pci_set_power_state(pdev, pci_choose_state(pdev, state)); +- +- return 0; +-} +- ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) ++{ ++ int retval; ++ bool wake; ++ ++ retval = __ixgbe_shutdown(pdev, &wake); ++ if (retval) ++ return retval; ++ ++ if (wake) { ++ pci_prepare_to_sleep(pdev); ++ } else { ++ pci_wake_from_d3(pdev, false); ++ pci_set_power_state(pdev, PCI_D3hot); ++ } ++ ++ return 0; ++} ++#endif /* CONFIG_PM */ ++ ++#ifndef USE_REBOOT_NOTIFIER + static void ixgbe_shutdown(struct pci_dev *pdev) + { +- ixgbe_suspend(pdev, PMSG_SUSPEND); +-} +- ++ bool wake; ++ ++ __ixgbe_shutdown(pdev, &wake); ++ ++ if (system_state == SYSTEM_POWER_OFF) { ++ pci_wake_from_d3(pdev, wake); ++ pci_set_power_state(pdev, PCI_D3hot); ++ } ++} ++ ++#endif + /** + * ixgbe_update_stats - Update the board statistics counters. + * @adapter: board private structure +@@ -3310,7 +5187,37 @@ + struct ixgbe_hw *hw = &adapter->hw; + u64 total_mpc = 0; + u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; +- ++#ifndef IXGBE_NO_LRO ++ u32 flushed = 0, coal = 0, recycled = 0; ++ int num_q_vectors = 1; ++ ++ if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ++ num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; ++#endif ++ ++ if (hw->mac.type == ixgbe_mac_82599EB) { ++ u64 rsc_count = 0; ++ for (i = 0; i < 16; i++) ++ adapter->hw_rx_no_dma_resources += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); ++ for (i = 0; i < adapter->num_rx_queues; i++) ++ rsc_count += adapter->rx_ring[i].rsc_count; ++ adapter->rsc_count = rsc_count; ++ } ++ ++#ifndef IXGBE_NO_LRO ++ for (i = 0; i < num_q_vectors; i++) { ++ struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; ++ if (!q_vector || !q_vector->lrolist) ++ continue; ++ flushed += q_vector->lrolist->stats.flushed; ++ coal += q_vector->lrolist->stats.coal; ++ recycled += q_vector->lrolist->stats.recycled; ++ } ++ adapter->lro_stats.flushed = flushed; ++ adapter->lro_stats.coal = coal; ++ adapter->lro_stats.recycled = recycled; ++ ++#endif + adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); + for (i = 0; i < 8; i++) { + /* for packet buffers not used, the register should read 0 */ +@@ -3318,32 +5225,52 @@ + missed_rx += mpc; + adapter->stats.mpc[i] += mpc; + total_mpc += adapter->stats.mpc[i]; +- adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); ++ if (hw->mac.type == ixgbe_mac_82598EB) ++ adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); + adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); + adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); + adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); + adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); +- adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, +- IXGBE_PXONRXC(i)); +- adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, +- IXGBE_PXONTXC(i)); +- adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, +- IXGBE_PXOFFRXC(i)); +- adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, +- IXGBE_PXOFFTXC(i)); ++ if (hw->mac.type == ixgbe_mac_82599EB) { ++ adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, ++ IXGBE_PXONRXCNT(i)); ++ adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, ++ IXGBE_PXOFFRXCNT(i)); ++ } else { ++ adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, ++ IXGBE_PXONRXC(i)); ++ adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, ++ IXGBE_PXOFFRXC(i)); ++ } + } + adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); + /* work around hardware counting issue */ + adapter->stats.gprc -= missed_rx; + + /* 82598 hardware only has a 32 bit counter in the high register */ +- adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); +- adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); +- adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); ++ if (hw->mac.type == ixgbe_mac_82599EB) { ++ adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); ++ IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ ++ adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); ++ IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ ++ adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); ++ IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ ++ adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); ++ adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); ++ adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); ++ adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); ++ } else { ++ adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); ++ adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); ++ adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); ++ adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); ++ adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); ++ } + bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); + adapter->stats.bprc += bprc; + adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); +- adapter->stats.mprc -= bprc; ++ if (hw->mac.type == ixgbe_mac_82598EB) ++ adapter->stats.mprc -= bprc; + adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); + adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); + adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); +@@ -3352,8 +5279,6 @@ + adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); + adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); + adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); +- adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); +- adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); + lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); + adapter->stats.lxontxc += lxon; + lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); +@@ -3401,28 +5326,133 @@ + { + struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; + struct ixgbe_hw *hw = &adapter->hw; +- +- /* Do the watchdog outside of interrupt context due to the lovely +- * delays that some of the newer hardware requires */ +- if (!test_bit(__IXGBE_DOWN, &adapter->state)) { +- /* Cause software interrupt to ensure rx rings are cleaned */ +- if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { +- u32 eics = +- (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1; +- IXGBE_WRITE_REG(hw, IXGBE_EICS, eics); +- } else { +- /* For legacy and MSI interrupts don't set any bits that +- * are enabled for EIAM, because this operation would +- * set *both* EIMS and EICS for any bit in EIAM */ +- IXGBE_WRITE_REG(hw, IXGBE_EICS, +- (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); +- } +- /* Reset the timer */ +- mod_timer(&adapter->watchdog_timer, +- round_jiffies(jiffies + 2 * HZ)); +- } +- ++ u64 eics = 0; ++ int i; ++ ++ /* ++ * Do the watchdog outside of interrupt context due to the lovely ++ * delays that some of the newer hardware requires ++ */ ++ ++ if (test_bit(__IXGBE_DOWN, &adapter->state)) ++ goto watchdog_short_circuit; ++ ++ ++ if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { ++ /* ++ * for legacy and MSI interrupts don't set any bits ++ * that are enabled for EIAM, because this operation ++ * would set *both* EIMS and EICS for any bit in EIAM ++ */ ++ IXGBE_WRITE_REG(hw, IXGBE_EICS, ++ (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); ++ goto watchdog_reschedule; ++ } ++ ++ /* get one bit for every active tx/rx interrupt vector */ ++ for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { ++ struct ixgbe_q_vector *qv = adapter->q_vector[i]; ++ if (qv->rxr_count || qv->txr_count) ++ eics |= ((u64)1 << i); ++ } ++ ++ /* Cause software interrupt to ensure rings are cleaned */ ++ ixgbe_irq_rearm_queues(adapter, eics); ++ ++watchdog_reschedule: ++ /* Reset the timer */ ++ mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ)); ++ ++watchdog_short_circuit: + schedule_work(&adapter->watchdog_task); ++} ++ ++/** ++ * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber ++ * @work: pointer to work_struct containing our data ++ **/ ++static void ixgbe_multispeed_fiber_task(struct work_struct *work) ++{ ++ struct ixgbe_adapter *adapter = container_of(work, ++ struct ixgbe_adapter, ++ multispeed_fiber_task); ++ struct ixgbe_hw *hw = &adapter->hw; ++ u32 autoneg; ++ ++ adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; ++ autoneg = hw->phy.autoneg_advertised; ++ if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) ++ hw->mac.ops.get_link_capabilities(hw, &autoneg, ++ &hw->mac.autoneg); ++ if (hw->mac.ops.setup_link_speed) ++ hw->mac.ops.setup_link_speed(hw, autoneg, true, true); ++ adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; ++ adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; ++} ++ ++/** ++ * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module ++ * @work: pointer to work_struct containing our data ++ **/ ++static void ixgbe_sfp_config_module_task(struct work_struct *work) ++{ ++ struct ixgbe_adapter *adapter = container_of(work, ++ struct ixgbe_adapter, ++ sfp_config_module_task); ++ struct ixgbe_hw *hw = &adapter->hw; ++ u32 err; ++ ++ adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; ++ err = hw->phy.ops.identify_sfp(hw); ++ if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { ++ DPRINTK(PROBE, ERR, "failed to load because an " ++ "unsupported SFP+ module type was detected.\n"); ++ unregister_netdev(adapter->netdev); ++ adapter->netdev_registered = false; ++ return; ++ } ++ /* ++ * A module may be identified correctly, but the EEPROM may not have ++ * support for that module. setup_sfp() will fail in that case, so ++ * we should not allow that module to load. ++ */ ++ err = hw->mac.ops.setup_sfp(hw); ++ if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { ++ DPRINTK(PROBE, ERR, "failed to load because an " ++ "unsupported SFP+ module type was detected.\n"); ++ unregister_netdev(adapter->netdev); ++ adapter->netdev_registered = false; ++ return; ++ } ++ ++ if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) ++ /* This will also work for DA Twinax connections */ ++ schedule_work(&adapter->multispeed_fiber_task); ++ adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; ++} ++ ++/** ++ * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table ++ * @work: pointer to work_struct containing our data ++ **/ ++static void ixgbe_fdir_reinit_task(struct work_struct *work) ++{ ++ struct ixgbe_adapter *adapter = container_of(work, ++ struct ixgbe_adapter, ++ fdir_reinit_task); ++ struct ixgbe_hw *hw = &adapter->hw; ++ int i; ++ ++ if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ set_bit(__IXGBE_FDIR_INIT_DONE, ++ &(adapter->tx_ring[i].reinit_state)); ++ } else { ++ DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, " ++ "ignored adding FDIR ATR filters \n"); ++ } ++ /* Done FDIR Re-initialization, enable transmits */ ++ netif_tx_start_all_queues(adapter->netdev); + } + + /** +@@ -3438,16 +5468,34 @@ + struct ixgbe_hw *hw = &adapter->hw; + u32 link_speed = adapter->link_speed; + bool link_up = adapter->link_up; ++ int i; ++ struct ixgbe_ring *tx_ring; ++ int some_tx_pending = 0; + + adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK; + + if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { +- hw->mac.ops.check_link(hw, &link_speed, &link_up, false); ++ if (hw->mac.ops.check_link) { ++ hw->mac.ops.check_link(hw, &link_speed, &link_up, false); ++ } else { ++ /* always assume link is up, if no check link function */ ++ link_speed = IXGBE_LINK_SPEED_10GB_FULL; ++ link_up = true; ++ } ++ if (link_up) { ++ if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { ++ for (i = 0; i < MAX_TRAFFIC_CLASS; i++) ++ hw->mac.ops.fc_enable(hw, i); ++ } else { ++ hw->mac.ops.fc_enable(hw, 0); ++ } ++ } ++ + if (link_up || + time_after(jiffies, (adapter->link_check_timeout + + IXGBE_TRY_LINK_TIMEOUT))) { ++ adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; + IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); +- adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; + } + adapter->link_up = link_up; + adapter->link_speed = link_speed; +@@ -3455,19 +5503,28 @@ + + if (link_up) { + if (!netif_carrier_ok(netdev)) { +- u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); +- u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); +-#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE) +-#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X) ++ bool flow_rx, flow_tx; ++ ++ if (hw->mac.type == ixgbe_mac_82599EB) { ++ u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); ++ u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); ++ flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); ++ flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); ++ } else { ++ u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); ++ u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); ++ flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); ++ flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); ++ } + DPRINTK(LINK, INFO, "NIC Link is Up %s, " + "Flow Control: %s\n", + (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? + "10 Gbps" : + (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? + "1 Gbps" : "unknown speed")), +- ((FLOW_RX && FLOW_TX) ? "RX/TX" : +- (FLOW_RX ? "RX" : +- (FLOW_TX ? "TX" : "None")))); ++ ((flow_rx && flow_tx) ? "RX/TX" : ++ (flow_rx ? "RX" : ++ (flow_tx ? "TX" : "None")))); + + netif_carrier_on(netdev); + netif_tx_wake_all_queues(netdev); +@@ -3485,14 +5542,39 @@ + } + } + ++ if (!netif_carrier_ok(netdev)) { ++ for (i = 0; i < adapter->num_tx_queues; i++) { ++ tx_ring = &adapter->tx_ring[i]; ++ if (tx_ring->next_to_use != tx_ring->next_to_clean) { ++ some_tx_pending = 1; ++ break; ++ } ++ } ++ ++ if (some_tx_pending) { ++ /* We've lost link, so the controller stops DMA, ++ * but we've got queued Tx work that's never going ++ * to get done, so reset controller to flush Tx. ++ * (Do the reset outside of interrupt context). ++ */ ++ schedule_work(&adapter->reset_task); ++ } ++ } ++ + ixgbe_update_stats(adapter); + adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK; +-} +- +-static int ixgbe_tso(struct ixgbe_adapter *adapter, +- struct ixgbe_ring *tx_ring, struct sk_buff *skb, +- u32 tx_flags, u8 *hdr_len) +-{ ++ ++ if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { ++ /* poll faster when waiting for link */ ++ mod_timer(&adapter->watchdog_timer, jiffies + (HZ/10)); ++ } ++ ++} ++ ++static int ixgbe_tso(struct ixgbe_adapter *adapter, struct ixgbe_ring *tx_ring, ++ struct sk_buff *skb, u32 tx_flags, u8 *hdr_len) ++{ ++#ifdef NETIF_F_TSO + struct ixgbe_adv_tx_context_desc *context_desc; + unsigned int i; + int err; +@@ -3518,6 +5600,7 @@ + IPPROTO_TCP, + 0); + adapter->hw_tso_ctxt++; ++#ifdef NETIF_F_TSO6 + } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { + ipv6_hdr(skb)->payload_len = 0; + tcp_hdr(skb)->check = +@@ -3525,6 +5608,7 @@ + &ipv6_hdr(skb)->daddr, + 0, IPPROTO_TCP, 0); + adapter->hw_tso6_ctxt++; ++#endif + } + + i = tx_ring->next_to_use; +@@ -3535,20 +5619,20 @@ + /* VLAN MACLEN IPLEN */ + if (tx_flags & IXGBE_TX_FLAGS_VLAN) + vlan_macip_lens |= +- (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); ++ (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); + vlan_macip_lens |= ((skb_network_offset(skb)) << + IXGBE_ADVTXD_MACLEN_SHIFT); + *hdr_len += skb_network_offset(skb); + vlan_macip_lens |= +- (skb_transport_header(skb) - skb_network_header(skb)); ++ (skb_transport_header(skb) - skb_network_header(skb)); + *hdr_len += +- (skb_transport_header(skb) - skb_network_header(skb)); ++ (skb_transport_header(skb) - skb_network_header(skb)); + context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); + context_desc->seqnum_seed = 0; + + /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ + type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | +- IXGBE_ADVTXD_DTYP_CTXT); ++ IXGBE_ADVTXD_DTYP_CTXT); + + if (skb->protocol == htons(ETH_P_IP)) + type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; +@@ -3557,7 +5641,7 @@ + + /* MSS L4LEN IDX */ + mss_l4len_idx = +- (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); ++ (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); + mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); + /* use index 1 for TSO */ + mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); +@@ -3573,6 +5657,8 @@ + + return true; + } ++ ++#endif + return false; + } + +@@ -3592,8 +5678,8 @@ + context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); + + if (tx_flags & IXGBE_TX_FLAGS_VLAN) +- vlan_macip_lens |= +- (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); ++ vlan_macip_lens |= (tx_flags & ++ IXGBE_TX_FLAGS_VLAN_MASK); + vlan_macip_lens |= (skb_network_offset(skb) << + IXGBE_ADVTXD_MACLEN_SHIFT); + if (skb->ip_summed == CHECKSUM_PARTIAL) +@@ -3612,14 +5698,16 @@ + type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; + if (ip_hdr(skb)->protocol == IPPROTO_TCP) + type_tucmd_mlhl |= +- IXGBE_ADVTXD_TUCMD_L4T_TCP; ++ IXGBE_ADVTXD_TUCMD_L4T_TCP; + break; ++#ifdef NETIF_F_IPV6_CSUM + case __constant_htons(ETH_P_IPV6): + /* XXX what about other V6 headers?? */ + if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) + type_tucmd_mlhl |= +- IXGBE_ADVTXD_TUCMD_L4T_TCP; ++ IXGBE_ADVTXD_TUCMD_L4T_TCP; + break; ++#endif + default: + if (unlikely(net_ratelimit())) { + DPRINTK(PROBE, WARNING, +@@ -3651,21 +5739,24 @@ + + static int ixgbe_tx_map(struct ixgbe_adapter *adapter, + struct ixgbe_ring *tx_ring, +- struct sk_buff *skb, unsigned int first) ++ struct sk_buff *skb, u32 tx_flags, ++ unsigned int first) + { + struct ixgbe_tx_buffer *tx_buffer_info; +- unsigned int len = skb->len; ++ unsigned int len; ++ unsigned int total = skb->len; + unsigned int offset = 0, size, count = 0, i; ++#ifdef MAX_SKB_FRAGS + unsigned int nr_frags = skb_shinfo(skb)->nr_frags; + unsigned int f; +- +- len -= skb->data_len; ++#endif + + i = tx_ring->next_to_use; + ++ len = min(skb_headlen(skb), total); + while (len) { + tx_buffer_info = &tx_ring->tx_buffer_info[i]; +- size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); ++ size = min(len, (unsigned int)IXGBE_MAX_DATA_PER_TXD); + + tx_buffer_info->length = size; + tx_buffer_info->dma = pci_map_single(adapter->pdev, +@@ -3675,6 +5766,7 @@ + tx_buffer_info->next_to_watch = i; + + len -= size; ++ total -= size; + offset += size; + count++; + i++; +@@ -3682,16 +5774,17 @@ + i = 0; + } + ++#ifdef MAX_SKB_FRAGS + for (f = 0; f < nr_frags; f++) { + struct skb_frag_struct *frag; + + frag = &skb_shinfo(skb)->frags[f]; +- len = frag->size; ++ len = min( (unsigned int)frag->size, total); + offset = frag->page_offset; + + while (len) { + tx_buffer_info = &tx_ring->tx_buffer_info[i]; +- size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); ++ size = min(len, (unsigned int)IXGBE_MAX_DATA_PER_TXD); + + tx_buffer_info->length = size; + tx_buffer_info->dma = pci_map_page(adapter->pdev, +@@ -3703,13 +5796,17 @@ + tx_buffer_info->next_to_watch = i; + + len -= size; ++ total -= size; + offset += size; + count++; + i++; + if (i == tx_ring->count) + i = 0; + } +- } ++ if (total == 0) ++ break; ++ } ++#endif + if (i == 0) + i = tx_ring->count - 1; + else +@@ -3721,13 +5818,14 @@ + } + + static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, +- struct ixgbe_ring *tx_ring, +- int tx_flags, int count, u32 paylen, u8 hdr_len) ++ struct ixgbe_ring *tx_ring, int tx_flags, ++ int count, u32 paylen, u8 hdr_len) + { + union ixgbe_adv_tx_desc *tx_desc = NULL; + struct ixgbe_tx_buffer *tx_buffer_info; + u32 olinfo_status = 0, cmd_type_len = 0; + unsigned int i; ++ + u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; + + cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; +@@ -3752,7 +5850,6 @@ + } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) + olinfo_status |= IXGBE_TXD_POPTS_TXSM << + IXGBE_ADVTXD_POPTS_SHIFT; +- + olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); + + i = tx_ring->next_to_use; +@@ -3761,7 +5858,7 @@ + tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); + tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); + tx_desc->read.cmd_type_len = +- cpu_to_le32(cmd_type_len | tx_buffer_info->length); ++ cpu_to_le32(cmd_type_len | tx_buffer_info->length); + tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); + i++; + if (i == tx_ring->count) +@@ -3780,6 +5877,58 @@ + + tx_ring->next_to_use = i; + writel(i, adapter->hw.hw_addr + tx_ring->tail); ++} ++ ++static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb, ++ int queue, u32 tx_flags) ++{ ++ /* Right now, we support IPv4 only */ ++ struct ixgbe_atr_input atr_input; ++ struct tcphdr *th; ++ struct udphdr *uh; ++ struct iphdr *iph = ip_hdr(skb); ++ struct ethhdr *eth = (struct ethhdr *)skb->data; ++ u16 vlan_id, src_port, dst_port, flex_bytes; ++ u32 src_ipv4_addr, dst_ipv4_addr; ++ u8 l4type = 0; ++ ++ /* check if we're UDP or TCP */ ++ if (iph->protocol == IPPROTO_TCP) { ++ th = tcp_hdr(skb); ++ src_port = th->source; ++ dst_port = th->dest; ++ l4type |= IXGBE_ATR_L4TYPE_TCP; ++ /* l4type IPv4 type is 0, no need to assign */ ++ } else if(iph->protocol == IPPROTO_UDP) { ++ uh = udp_hdr(skb); ++ src_port = uh->source; ++ dst_port = uh->dest; ++ l4type |= IXGBE_ATR_L4TYPE_UDP; ++ /* l4type IPv4 type is 0, no need to assign */ ++ } else { ++ /* Unsupported L4 header, just bail here */ ++ return; ++ } ++ ++ memset(&atr_input, 0, sizeof(struct ixgbe_atr_input)); ++ ++ vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >> ++ IXGBE_TX_FLAGS_VLAN_SHIFT; ++ src_ipv4_addr = iph->saddr; ++ dst_ipv4_addr = iph->daddr; ++ flex_bytes = eth->h_proto; ++ ++ ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id); ++ ixgbe_atr_set_src_port_82599(&atr_input, dst_port); ++ ixgbe_atr_set_dst_port_82599(&atr_input, src_port); ++ ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes); ++ ixgbe_atr_set_l4type_82599(&atr_input, l4type); ++ /* src and dst are inverted, think how the receiver sees them */ ++ ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr); ++ ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr); ++ ++ /* This assumes the Rx queue and Tx queue are bound to the same CPU */ ++ ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue); + } + + static int __ixgbe_maybe_stop_tx(struct net_device *netdev, +@@ -3805,7 +5954,7 @@ + } + + static int ixgbe_maybe_stop_tx(struct net_device *netdev, +- struct ixgbe_ring *tx_ring, int size) ++ struct ixgbe_ring *tx_ring, int size) + { + if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) + return 0; +@@ -3821,42 +5970,64 @@ + u8 hdr_len = 0; + int r_idx = 0, tso; + int count = 0; ++ ++#ifdef MAX_SKB_FRAGS + unsigned int f; +- +- r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping; +- tx_ring = &adapter->tx_ring[r_idx]; +- ++#endif ++#ifdef NETIF_F_HW_VLAN_TX + if (adapter->vlgrp && vlan_tx_tag_present(skb)) { + tx_flags |= vlan_tx_tag_get(skb); ++#ifdef HAVE_TX_MQ + if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { +- tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; +- tx_flags |= (skb->queue_mapping << 13); +- } ++ if (skb->queue_mapping) { ++ tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; ++ tx_flags |= (skb->queue_mapping << 13); ++ } else { ++ skb->queue_mapping = (tx_flags & ++ IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13; ++ } ++ } ++#endif + tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; + tx_flags |= IXGBE_TX_FLAGS_VLAN; ++#ifdef HAVE_TX_MQ + } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { +- tx_flags |= (skb->queue_mapping << 13); +- tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; +- tx_flags |= IXGBE_TX_FLAGS_VLAN; +- } +- /* three things can cause us to need a context descriptor */ ++ if (skb->priority != TC_PRIO_CONTROL) { ++ tx_flags |= (skb->queue_mapping << 13); ++ tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; ++ tx_flags |= IXGBE_TX_FLAGS_VLAN; ++ } else { ++ skb->queue_mapping = ++ adapter->ring_feature[RING_F_DCB].indices-1; ++ } ++#endif ++ } ++#endif ++ ++#ifdef HAVE_TX_MQ ++ r_idx = skb->queue_mapping; ++#endif ++ tx_ring = &adapter->tx_ring[r_idx]; ++ ++ /* four things can cause us to need a context descriptor */ + if (skb_is_gso(skb) || + (skb->ip_summed == CHECKSUM_PARTIAL) || + (tx_flags & IXGBE_TX_FLAGS_VLAN)) + count++; +- + count += TXD_USE_COUNT(skb_headlen(skb)); ++#ifdef MAX_SKB_FRAGS + for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) + count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); + ++#endif + if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { + adapter->tx_busy++; + return NETDEV_TX_BUSY; + } + ++ first = tx_ring->next_to_use; + if (skb->protocol == htons(ETH_P_IP)) + tx_flags |= IXGBE_TX_FLAGS_IPV4; +- first = tx_ring->next_to_use; + tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); + if (tso < 0) { + dev_kfree_skb_any(skb); +@@ -3866,12 +6037,21 @@ + if (tso) + tx_flags |= IXGBE_TX_FLAGS_TSO; + else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && +- (skb->ip_summed == CHECKSUM_PARTIAL)) ++ (skb->ip_summed == CHECKSUM_PARTIAL)) + tx_flags |= IXGBE_TX_FLAGS_CSUM; + ++ /* add the ATR filter if ATR is on */ ++ if (tx_ring->atr_sample_rate) { ++ ++tx_ring->atr_count; ++ if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) && ++ test_bit(__IXGBE_FDIR_INIT_DONE, &tx_ring->reinit_state)) { ++ ixgbe_atr(adapter, skb, tx_ring->queue_index, tx_flags); ++ tx_ring->atr_count = 0; ++ } ++ } + ixgbe_tx_queue(adapter, tx_ring, tx_flags, +- ixgbe_tx_map(adapter, tx_ring, skb, first), +- skb->len, hdr_len); ++ ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first), ++ skb->len, hdr_len); + + netdev->trans_start = jiffies; + +@@ -3914,11 +6094,74 @@ + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); + memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); + +- hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); +- +- return 0; +-} +- ++ if (hw->mac.ops.set_rar) ++ hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); ++ ++ return 0; ++} ++ ++#if defined(HAVE_NETDEV_STORAGE_ADDRESS) && defined(NETDEV_HW_ADDR_T_SAN) ++/** ++ * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding ++ * netdev->dev_addr_list ++ * @netdev: network interface device structure ++ * ++ * Returns non-zero on failure ++ **/ ++static int ixgbe_add_sanmac_netdev(struct net_device *dev) ++{ ++ int err = 0; ++ struct ixgbe_adapter *adapter = netdev_priv(dev); ++ struct ixgbe_mac_info *mac = &adapter->hw.mac; ++ ++ if (is_valid_ether_addr(mac->san_addr)) { ++ rtnl_lock(); ++ err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); ++ rtnl_unlock(); ++ } ++ return err; ++} ++ ++/** ++ * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding ++ * netdev->dev_addr_list ++ * @netdev: network interface device structure ++ * ++ * Returns non-zero on failure ++ **/ ++static int ixgbe_del_sanmac_netdev(struct net_device *dev) ++{ ++ int err = 0; ++ struct ixgbe_adapter *adapter = netdev_priv(dev); ++ struct ixgbe_mac_info *mac = &adapter->hw.mac; ++ ++ if (is_valid_ether_addr(mac->san_addr)) { ++ rtnl_lock(); ++ err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); ++ rtnl_unlock(); ++ } ++ return err; ++} ++ ++#endif /* (HAVE_NETDEV_STORAGE_ADDRESS) && defined(NETDEV_HW_ADDR_T_SAN) */ ++#ifdef ETHTOOL_OPS_COMPAT ++/** ++ * ixgbe_ioctl - ++ * @netdev: ++ * @ifreq: ++ * @cmd: ++ **/ ++static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) ++{ ++ switch (cmd) { ++ case SIOCETHTOOL: ++ return ethtool_ioctl(ifr); ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++ ++#endif + #ifdef CONFIG_NET_POLL_CONTROLLER + /* + * Polling 'interrupt' - used by things like netconsole to send skbs +@@ -3928,33 +6171,106 @@ + static void ixgbe_netpoll(struct net_device *netdev) + { + struct ixgbe_adapter *adapter = netdev_priv(netdev); +- +- disable_irq(adapter->pdev->irq); ++ int i; ++ ++#ifndef CONFIG_IXGBE_NAPI ++ ixgbe_irq_disable(adapter); ++#endif + adapter->flags |= IXGBE_FLAG_IN_NETPOLL; +- ixgbe_intr(adapter->pdev->irq, netdev); ++ if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { ++ int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; ++ for (i = 0; i < num_q_vectors; i++) { ++ struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; ++ ixgbe_msix_clean_many(0, q_vector); ++ } ++ } else { ++ ixgbe_intr(adapter->pdev->irq, netdev); ++ } + adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; +- enable_irq(adapter->pdev->irq); +-} +-#endif +- +-/** +- * ixgbe_link_config - set up initial link with default speed and duplex +- * @hw: pointer to private hardware struct +- * +- * Returns 0 on success, negative on failure +- **/ +-static int ixgbe_link_config(struct ixgbe_hw *hw) +-{ +- u32 autoneg = IXGBE_LINK_SPEED_10GB_FULL; +- +- /* must always autoneg for both 1G and 10G link */ +- hw->mac.autoneg = true; +- +- if ((hw->mac.type == ixgbe_mac_82598EB) && +- (hw->phy.media_type == ixgbe_media_type_copper)) +- autoneg = IXGBE_LINK_SPEED_82598_AUTONEG; +- +- return hw->mac.ops.setup_link_speed(hw, autoneg, true, true); ++#ifndef CONFIG_IXGBE_NAPI ++ ixgbe_irq_enable(adapter, true, true); ++#endif ++} ++ ++#endif ++#ifdef HAVE_NETDEV_SELECT_QUEUE ++static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) ++{ ++ struct ixgbe_adapter *adapter = netdev_priv(dev); ++ ++ if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ++ return smp_processor_id(); ++ ++ if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) ++ return 0; /* all untagged traffic should default to TC 0 */ ++ ++ return skb_tx_hash(dev, skb); ++} ++ ++#endif /* HAVE_NETDEV_SELECT_QUEUE */ ++#ifdef HAVE_NET_DEVICE_OPS ++static const struct net_device_ops ixgbe_netdev_ops = { ++ .ndo_open = &ixgbe_open, ++ .ndo_stop = &ixgbe_close, ++ .ndo_start_xmit = &ixgbe_xmit_frame, ++ .ndo_get_stats = &ixgbe_get_stats, ++ .ndo_set_rx_mode = &ixgbe_set_rx_mode, ++ .ndo_set_multicast_list = &ixgbe_set_rx_mode, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_set_mac_address = &ixgbe_set_mac, ++ .ndo_change_mtu = &ixgbe_change_mtu, ++#ifdef ETHTOOL_OPS_COMPAT ++ .ndo_do_ioctl = &ixgbe_ioctl, ++#endif ++ .ndo_tx_timeout = &ixgbe_tx_timeout, ++ .ndo_vlan_rx_register = &ixgbe_vlan_rx_register, ++ .ndo_vlan_rx_add_vid = &ixgbe_vlan_rx_add_vid, ++ .ndo_vlan_rx_kill_vid = &ixgbe_vlan_rx_kill_vid, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = &ixgbe_netpoll, ++#endif ++ .ndo_select_queue = &ixgbe_select_queue, ++}; ++ ++#endif /* HAVE_NET_DEVICE_OPS */ ++ ++void ixgbe_assign_netdev_ops(struct net_device *dev) ++{ ++ struct ixgbe_adapter *adapter; ++ adapter = netdev_priv(dev); ++#ifdef HAVE_NET_DEVICE_OPS ++ dev->netdev_ops = &ixgbe_netdev_ops; ++#else /* HAVE_NET_DEVICE_OPS */ ++ dev->open = &ixgbe_open; ++ dev->stop = &ixgbe_close; ++ dev->hard_start_xmit = &ixgbe_xmit_frame; ++ dev->get_stats = &ixgbe_get_stats; ++#ifdef HAVE_SET_RX_MODE ++ dev->set_rx_mode = &ixgbe_set_rx_mode; ++#endif ++ dev->set_multicast_list = &ixgbe_set_rx_mode; ++ dev->set_mac_address = &ixgbe_set_mac; ++ dev->change_mtu = &ixgbe_change_mtu; ++#ifdef ETHTOOL_OPS_COMPAT ++ dev->do_ioctl = &ixgbe_ioctl; ++#endif ++#ifdef HAVE_TX_TIMEOUT ++ dev->tx_timeout = &ixgbe_tx_timeout; ++#endif ++#ifdef NETIF_F_HW_VLAN_TX ++ dev->vlan_rx_register = &ixgbe_vlan_rx_register; ++ dev->vlan_rx_add_vid = &ixgbe_vlan_rx_add_vid; ++ dev->vlan_rx_kill_vid = &ixgbe_vlan_rx_kill_vid; ++#endif ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ dev->poll_controller = &ixgbe_netpoll; ++#endif ++#ifdef HAVE_NETDEV_SELECT_QUEUE ++ dev->select_queue = &ixgbe_select_queue; ++#endif /* HAVE_NETDEV_SELECT_QUEUE */ ++#endif /* HAVE_NET_DEVICE_OPS */ ++ ixgbe_set_ethtool_ops(dev); ++ dev->watchdog_timeo = 5 * HZ; + } + + /** +@@ -3973,12 +6289,10 @@ + { + struct net_device *netdev; + struct ixgbe_adapter *adapter = NULL; +- struct ixgbe_hw *hw; +- const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; ++ struct ixgbe_hw *hw = NULL; + static int cards_found; + int i, err, pci_using_dac; +- u16 link_status, link_speed, link_width; +- u32 part_num, eec; ++ u32 part_num; + + err = pci_enable_device(pdev); + if (err) +@@ -4006,10 +6320,35 @@ + goto err_pci_reg; + } + ++ /* ++ * Workaround of Silicon errata on 82598. Disable LOs in the PCI switch ++ * port to which the 82598 is connected to prevent duplicate ++ * completions caused by LOs. We need the mac type so that we only ++ * do this on 82598 devices, ixgbe_set_mac_type does this for us if ++ * we set it's device ID. ++ */ ++ hw = vmalloc(sizeof(struct ixgbe_hw)); ++ if (!hw) { ++ printk(KERN_INFO "Unable to allocate memory for LOs fix " ++ "- not checked\n"); ++ } else { ++ hw->vendor_id = pdev->vendor; ++ hw->device_id = pdev->device; ++ ixgbe_set_mac_type(hw); ++ if (hw->mac.type == ixgbe_mac_82598EB) ++ pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S); ++ vfree(hw); ++ } ++ ++ pci_enable_pcie_error_reporting(pdev); ++ + pci_set_master(pdev); +- pci_save_state(pdev); +- ++ ++#ifdef HAVE_TX_MQ + netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES); ++#else ++ netdev = alloc_etherdev(sizeof(struct ixgbe_adapter)); ++#endif + if (!netdev) { + err = -ENOMEM; + goto err_alloc_etherdev; +@@ -4026,6 +6365,14 @@ + hw->back = adapter; + adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; + ++#ifdef HAVE_PCI_ERS ++ /* ++ * call save state here in standalone driver because it relies on ++ * adapter struct to exist, and needs to call netdev_priv ++ */ ++ pci_save_state(pdev); ++ ++#endif + hw->hw_addr = ioremap(pci_resource_start(pdev, 0), + pci_resource_len(pdev, 0)); + if (!hw->hw_addr) { +@@ -4038,120 +6385,173 @@ + continue; + } + +- netdev->open = &ixgbe_open; +- netdev->stop = &ixgbe_close; +- netdev->hard_start_xmit = &ixgbe_xmit_frame; +- netdev->get_stats = &ixgbe_get_stats; +- netdev->set_rx_mode = &ixgbe_set_rx_mode; +- netdev->set_multicast_list = &ixgbe_set_rx_mode; +- netdev->set_mac_address = &ixgbe_set_mac; +- netdev->change_mtu = &ixgbe_change_mtu; +- ixgbe_set_ethtool_ops(netdev); +- netdev->tx_timeout = &ixgbe_tx_timeout; +- netdev->watchdog_timeo = 5 * HZ; +- netdev->vlan_rx_register = ixgbe_vlan_rx_register; +- netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid; +- netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid; +-#ifdef CONFIG_NET_POLL_CONTROLLER +- netdev->poll_controller = ixgbe_netpoll; +-#endif ++ ixgbe_assign_netdev_ops(netdev); ++ + strcpy(netdev->name, pci_name(pdev)); + + adapter->bd_number = cards_found; + +- /* Setup hw api */ +- memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); +- hw->mac.type = ii->mac; +- +- /* EEPROM */ +- memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); +- eec = IXGBE_READ_REG(hw, IXGBE_EEC); +- /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ +- if (!(eec & (1 << 8))) +- hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; +- +- /* PHY */ +- memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); +- hw->phy.sfp_type = ixgbe_sfp_type_unknown; +- +- /* set up this timer and work struct before calling get_invariants +- * which might start the timer */ ++#ifdef IXGBE_TCP_TIMER ++ adapter->msix_addr = ioremap(pci_resource_start(pdev, 3), ++ pci_resource_len(pdev, 3)); ++ if (!adapter->msix_addr) { ++ err = -EIO; ++ printk("Error in ioremap of BAR3\n"); ++ goto err_map_msix; ++ } ++ ++#endif ++ /* set up this timer and work struct before calling sw_init which ++ * might start the timer */ + init_timer(&adapter->sfp_timer); + adapter->sfp_timer.function = &ixgbe_sfp_timer; + adapter->sfp_timer.data = (unsigned long) adapter; + + INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); + +- err = ii->get_invariants(hw); +- if (err == IXGBE_ERR_SFP_NOT_PRESENT) { +- /* start a kernel thread to watch for a module to arrive */ ++ /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ ++ INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); ++ ++ /* a new SFP+ module arrival, called from GPI SDP2 context */ ++ INIT_WORK(&adapter->sfp_config_module_task, ++ ixgbe_sfp_config_module_task); ++ ++ /* setup the private structure */ ++ err = ixgbe_sw_init(adapter); ++ if (err) ++ goto err_sw_init; ++ ++ /* ++ * If we have a fan, this is as early we know, warn if we ++ * have had a failure. ++ */ ++ if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { ++ u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); ++ if (esdp & IXGBE_ESDP_SDP1) ++ DPRINTK(PROBE, CRIT, ++ "Fan has stopped, replace the adapter\n"); ++ } ++ ++ /* reset_hw fills in the perm_addr as well */ ++ err = hw->mac.ops.reset_hw(hw); ++ if (err == IXGBE_ERR_SFP_NOT_PRESENT && ++ hw->mac.type == ixgbe_mac_82598EB) { ++ /* ++ * Start a kernel thread to watch for a module to arrive. ++ * Only do this for 82598, since 82599 will generate interrupts ++ * on module arrival. ++ */ + set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); + mod_timer(&adapter->sfp_timer, +- round_jiffies(jiffies + (2 * HZ))); ++ round_jiffies(jiffies + (2 * HZ))); + err = 0; + } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { + DPRINTK(PROBE, ERR, "failed to load because an " +- "unsupported SFP+ module type was detected.\n"); +- goto err_hw_init; ++ "unsupported SFP+ module type was detected.\n"); ++ goto err_sw_init; + } else if (err) { +- goto err_hw_init; +- } +- +- /* setup the private structure */ +- err = ixgbe_sw_init(adapter); +- if (err) +- goto err_sw_init; +- +- /* reset_hw fills in the perm_addr as well */ +- err = hw->mac.ops.reset_hw(hw); +- if (err) { +- dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); +- goto err_sw_init; +- } +- ++ DPRINTK(PROBE, ERR, "HW Init failed: %d\n", err); ++ goto err_sw_init; ++ } ++ ++ /* check_options must be called before setup_link_speed to set up ++ * hw->fc completely ++ */ ++ ixgbe_check_options(adapter); ++ ++#ifdef MAX_SKB_FRAGS ++#ifdef NETIF_F_HW_VLAN_TX + netdev->features = NETIF_F_SG | +- NETIF_F_IP_CSUM | +- NETIF_F_HW_VLAN_TX | +- NETIF_F_HW_VLAN_RX | +- NETIF_F_HW_VLAN_FILTER; +- ++ NETIF_F_IP_CSUM | ++ NETIF_F_HW_VLAN_TX | ++ NETIF_F_HW_VLAN_RX | ++ NETIF_F_HW_VLAN_FILTER; ++ ++#else ++ netdev->features = NETIF_F_SG | NETIF_F_IP_CSUM; ++ ++#endif ++#ifdef NETIF_F_IPV6_CSUM + netdev->features |= NETIF_F_IPV6_CSUM; ++#endif ++#ifdef NETIF_F_TSO + netdev->features |= NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 + netdev->features |= NETIF_F_TSO6; +-#ifdef CONFIG_IXGBE_LRO +- netdev->features |= NETIF_F_LRO; +-#endif +- ++#endif /* NETIF_F_TSO6 */ ++#endif /* NETIF_F_TSO */ ++#ifdef NETIF_F_GRO ++ netdev->features |= NETIF_F_GRO; ++#endif /* NETIF_F_GRO */ ++ if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) ++ adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; ++ if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) ++ adapter->flags &= ~(IXGBE_FLAG_FDIR_HASH_CAPABLE ++ | IXGBE_FLAG_FDIR_PERFECT_CAPABLE); ++#ifndef IXGBE_NO_HW_RSC ++ if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) { ++#ifdef NETIF_F_LRO ++ netdev->features |= NETIF_F_LRO; ++#endif ++#ifndef IXGBE_NO_LRO ++ adapter->flags2 &= ~IXGBE_FLAG2_SWLRO_ENABLED; ++#endif ++ adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; ++ } else { ++#endif ++#ifndef IXGBE_NO_LRO ++#ifdef NETIF_F_LRO ++ netdev->features |= NETIF_F_LRO; ++#endif ++ adapter->flags2 |= IXGBE_FLAG2_SWLRO_ENABLED; ++#endif ++#ifndef IXGBE_NO_HW_RSC ++ adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; ++ } ++#endif ++#ifdef HAVE_NETDEV_VLAN_FEATURES ++#ifdef NETIF_F_TSO + netdev->vlan_features |= NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 + netdev->vlan_features |= NETIF_F_TSO6; ++#endif /* NETIF_F_TSO6 */ ++#endif /* NETIF_F_TSO */ + netdev->vlan_features |= NETIF_F_IP_CSUM; + netdev->vlan_features |= NETIF_F_SG; + +- if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) +- adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; +- +-#ifdef CONFIG_IXGBE_DCB ++#endif /* HAVE_NETDEV_VLAN_FEATURES */ ++#ifdef CONFIG_DCB + netdev->dcbnl_ops = &dcbnl_ops; +-#endif /* CONFIG_IXGBE_DCB */ ++#endif + + if (pci_using_dac) + netdev->features |= NETIF_F_HIGHDMA; + ++#endif /* MAX_SKB_FRAGS */ + /* make sure the EEPROM is good */ +- if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { +- dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); ++ if (hw->eeprom.ops.validate_checksum && ++ (hw->eeprom.ops.validate_checksum(hw, NULL) < 0)) { ++ DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n"); + err = -EIO; +- goto err_eeprom; ++ goto err_sw_init; + } + + memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); ++#ifdef ETHTOOL_GPERMADDR + memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); + + if (ixgbe_validate_mac_addr(netdev->perm_addr)) { +- dev_err(&pdev->dev, "invalid MAC address\n"); ++ DPRINTK(PROBE, INFO, "invalid MAC address\n"); + err = -EIO; +- goto err_eeprom; +- } ++ goto err_sw_init; ++ } ++#else ++ if (ixgbe_validate_mac_addr(netdev->dev_addr)) { ++ DPRINTK(PROBE, INFO, "invalid MAC address\n"); ++ err = -EIO; ++ goto err_sw_init; ++ } ++#endif + + init_timer(&adapter->watchdog_timer); + adapter->watchdog_timer.function = &ixgbe_watchdog; +@@ -4164,78 +6564,140 @@ + if (err) + goto err_sw_init; + +- /* print bus type/speed/width info */ +- pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status); +- link_speed = link_status & IXGBE_PCI_LINK_SPEED; +- link_width = link_status & IXGBE_PCI_LINK_WIDTH; +- dev_info(&pdev->dev, "(PCI Express:%s:%s) " +- "%02x:%02x:%02x:%02x:%02x:%02x\n", +- ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" : +- (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" : +- "Unknown"), +- ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" : +- (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" : +- (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" : +- (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" : +- "Unknown"), +- netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2], +- netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]); +- ixgbe_read_pba_num_generic(hw, &part_num); +- dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", +- hw->mac.type, hw->phy.type, +- (part_num >> 8), (part_num & 0xff)); +- +- if (link_width <= IXGBE_PCI_LINK_WIDTH_4) { +- dev_warn(&pdev->dev, "PCI-Express bandwidth available for " +- "this card is not sufficient for optimal " +- "performance.\n"); +- dev_warn(&pdev->dev, "For optimal performance a x8 " +- "PCI-Express slot is required.\n"); +- } ++ switch (pdev->device) { ++ case IXGBE_DEV_ID_82599_KX4: ++ adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | ++ IXGBE_WUFC_MC | IXGBE_WUFC_BC); ++ /* Enable ACPI wakeup in GRC */ ++ IXGBE_WRITE_REG(hw, IXGBE_GRC, ++ (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME)); ++ break; ++ default: ++ adapter->wol = 0; ++ break; ++ } ++ device_init_wakeup(&adapter->pdev->dev, true); ++ device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); ++ ++ /* save off EEPROM version number */ ++ ixgbe_read_eeprom(hw, 0x29, &adapter->eeprom_version); + + /* reset the hardware with the new settings */ +- hw->mac.ops.start_hw(hw); +- +- /* link_config depends on start_hw being called at least once */ +- err = ixgbe_link_config(hw); +- if (err) { +- dev_err(&pdev->dev, "setup_link_speed FAILED %d\n", err); +- goto err_register; +- } +- +- netif_carrier_off(netdev); +- netif_tx_stop_all_queues(netdev); +- +- ixgbe_napi_add_all(adapter); ++ err = hw->mac.ops.start_hw(hw); ++ if (err == IXGBE_ERR_EEPROM_VERSION) { ++ /* We are running on a pre-production device, log a warning */ ++ DPRINTK(PROBE, INFO, "This device is a pre-production adapter/" ++ "LOM. Please be aware there may be issues associated " ++ "with your hardware. If you are experiencing problems " ++ "please contact your Intel or hardware representative " ++ "who provided you with this hardware.\n"); ++ } ++ /* pick up the PCI bus settings for reporting later */ ++ if (hw->mac.ops.get_bus_info) ++ hw->mac.ops.get_bus_info(hw); ++ + + strcpy(netdev->name, "eth%d"); + err = register_netdev(netdev); + if (err) + goto err_register; + +-#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) +- if (dca_add_requester(&pdev->dev) == 0) { +- adapter->flags |= IXGBE_FLAG_DCA_ENABLED; +- /* always use CB2 mode, difference is masked +- * in the CB driver */ +- IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); +- ixgbe_setup_dca(adapter); +- } +-#endif +- +- dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); ++ adapter->netdev_registered = true; ++ ++ /* carrier off reporting is important to ethtool even BEFORE open */ ++ netif_carrier_off(netdev); ++ /* keep stopping all the transmit queues for older kernels */ ++ netif_tx_stop_all_queues(netdev); ++ ++ if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || ++ adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) ++ INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task); ++ ++#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) ++ if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) { ++ err = dca_add_requester(&pdev->dev); ++ switch (err) { ++ case 0: ++ adapter->flags |= IXGBE_FLAG_DCA_ENABLED; ++ ixgbe_setup_dca(adapter); ++ break; ++ /* -19 is returned from the kernel when no provider is found */ ++ case -19: ++ DPRINTK(PROBE, INFO, "No DCA provider found. Please " ++ "start ioatdma for DCA functionality.\n"); ++ break; ++ default: ++ DPRINTK(PROBE, INFO, "DCA registration failed: %d\n", ++ err); ++ break; ++ } ++ } ++ ++#endif ++ /* print all messages at the end so that we use our eth%d name */ ++ /* print bus type/speed/width info */ ++ DPRINTK(PROBE, INFO, "(PCI Express:%s:%s) ", ++ ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s": ++ (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"), ++ (hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : ++ (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : ++ (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : ++ ("Unknown")); ++ ++ /* print the MAC address */ ++ for (i = 0; i < 6; i++) ++ printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':'); ++ ++ ixgbe_read_pba_num(hw, &part_num); ++ if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) ++ DPRINTK(PROBE, INFO, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n", ++ hw->mac.type, hw->phy.type, hw->phy.sfp_type, ++ (part_num >> 8), (part_num & 0xff)); ++ else ++ DPRINTK(PROBE, INFO, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", ++ hw->mac.type, hw->phy.type, ++ (part_num >> 8), (part_num & 0xff)); ++ ++ if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { ++ DPRINTK(PROBE, WARNING, "PCI-Express bandwidth available for " ++ "this card is not sufficient for optimal " ++ "performance.\n"); ++ DPRINTK(PROBE, WARNING, "For optimal performance a x8 " ++ "PCI-Express slot is required.\n"); ++ } ++ ++#ifndef IXGBE_NO_LRO ++ if (adapter->flags2 & IXGBE_FLAG2_SWLRO_ENABLED) ++ DPRINTK(PROBE, INFO, "Internal LRO is enabled \n"); ++ else ++ DPRINTK(PROBE, INFO, "LRO is disabled \n"); ++#endif ++#ifndef IXGBE_NO_HW_RSC ++ if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) ++ DPRINTK(PROBE, INFO, "HW RSC is enabled \n"); ++#endif ++#if defined(HAVE_NETDEV_STORAGE_ADDRESS) && defined(NETDEV_HW_ADDR_T_SAN) ++ /* add san mac addr to netdev */ ++ ixgbe_add_sanmac_netdev(netdev); ++ ++#endif /* (HAVE_NETDEV_STORAGE_ADDRESS) && (NETDEV_HW_ADDR_T_SAN) */ ++ DPRINTK(PROBE, INFO, "Intel(R) 10 Gigabit Network Connection\n"); + cards_found++; + return 0; + + err_register: ++ ixgbe_clear_interrupt_scheme(adapter); + ixgbe_release_hw_control(adapter); +-err_hw_init: + err_sw_init: +- ixgbe_reset_interrupt_capability(adapter); +-err_eeprom: + clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); + del_timer_sync(&adapter->sfp_timer); + cancel_work_sync(&adapter->sfp_task); ++ cancel_work_sync(&adapter->multispeed_fiber_task); ++ cancel_work_sync(&adapter->sfp_config_module_task); ++#ifdef IXGBE_TCP_TIMER ++ iounmap(adapter->msix_addr); ++err_map_msix: ++#endif + iounmap(hw->hw_addr); + err_ioremap: + free_netdev(netdev); +@@ -4262,13 +6724,20 @@ + struct ixgbe_adapter *adapter = netdev_priv(netdev); + + set_bit(__IXGBE_DOWN, &adapter->state); +- /* clear the module not found bit to make sure the worker won't +- * reschedule */ ++ /* ++ * clear the module not found bit to make sure the worker won't ++ * reschedule ++ */ + clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); + del_timer_sync(&adapter->watchdog_timer); + del_timer_sync(&adapter->sfp_timer); + cancel_work_sync(&adapter->watchdog_task); + cancel_work_sync(&adapter->sfp_task); ++ if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || ++ adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) ++ cancel_work_sync(&adapter->fdir_reinit_task); ++ cancel_work_sync(&adapter->multispeed_fiber_task); ++ cancel_work_sync(&adapter->sfp_config_module_task); + flush_scheduled_work(); + + #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) +@@ -4279,26 +6748,50 @@ + } + + #endif +- if (netdev->reg_state == NETREG_REGISTERED) ++#if defined(HAVE_NETDEV_STORAGE_ADDRESS) && defined(NETDEV_HW_ADDR_T_SAN) ++ /* remove the added san mac */ ++ ixgbe_del_sanmac_netdev(netdev); ++ ++#endif /* (HAVE_NETDEV_STORAGE_ADDRESS) && (NETDEV_HW_ADDR_T_SAN) */ ++ if (adapter->netdev_registered) { + unregister_netdev(netdev); +- +- ixgbe_reset_interrupt_capability(adapter); +- ++ adapter->netdev_registered = false; ++ } ++ ++ ixgbe_clear_interrupt_scheme(adapter); + ixgbe_release_hw_control(adapter); + ++#ifdef IXGBE_TCP_TIMER ++ iounmap(adapter->msix_addr); ++#endif + iounmap(adapter->hw.hw_addr); + pci_release_regions(pdev); + + DPRINTK(PROBE, INFO, "complete\n"); +- ixgbe_napi_del_all(adapter); +- kfree(adapter->tx_ring); +- kfree(adapter->rx_ring); +- + free_netdev(netdev); + ++ pci_disable_pcie_error_reporting(pdev); ++ + pci_disable_device(pdev); + } + ++u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) ++{ ++ u16 value; ++ struct ixgbe_adapter *adapter = hw->back; ++ ++ pci_read_config_word(adapter->pdev, reg, &value); ++ return value; ++} ++ ++void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) ++{ ++ struct ixgbe_adapter *adapter = hw->back; ++ ++ pci_write_config_word(adapter->pdev, reg, value); ++} ++ ++#ifdef HAVE_PCI_ERS + /** + * ixgbe_io_error_detected - called when PCI error is detected + * @pdev: Pointer to PCI device +@@ -4311,9 +6804,12 @@ + pci_channel_state_t state) + { + struct net_device *netdev = pci_get_drvdata(pdev); +- struct ixgbe_adapter *adapter = netdev->priv; ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); + + netif_device_detach(netdev); ++ ++ if (state == pci_channel_io_perm_failure) ++ return PCI_ERS_RESULT_DISCONNECT; + + if (netif_running(netdev)) + ixgbe_down(adapter); +@@ -4332,22 +6828,27 @@ + static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) + { + struct net_device *netdev = pci_get_drvdata(pdev); +- struct ixgbe_adapter *adapter = netdev->priv; ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); ++ pci_ers_result_t result; + + if (pci_enable_device(pdev)) { + DPRINTK(PROBE, ERR, +- "Cannot re-enable PCI device after reset.\n"); +- return PCI_ERS_RESULT_DISCONNECT; +- } +- pci_set_master(pdev); +- pci_restore_state(pdev); +- +- pci_enable_wake(pdev, PCI_D3hot, 0); +- pci_enable_wake(pdev, PCI_D3cold, 0); +- +- ixgbe_reset(adapter); +- +- return PCI_ERS_RESULT_RECOVERED; ++ "Cannot re-enable PCI device after reset.\n"); ++ result = PCI_ERS_RESULT_DISCONNECT; ++ } else { ++ pci_set_master(pdev); ++ pci_restore_state(pdev); ++ ++ pci_wake_from_d3(pdev, false); ++ ++ ixgbe_reset(adapter); ++ IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); ++ result = PCI_ERS_RESULT_RECOVERED; ++ } ++ ++ pci_cleanup_aer_uncorrect_error_status(pdev); ++ ++ return result; + } + + /** +@@ -4360,7 +6861,7 @@ + static void ixgbe_io_resume(struct pci_dev *pdev) + { + struct net_device *netdev = pci_get_drvdata(pdev); +- struct ixgbe_adapter *adapter = netdev->priv; ++ struct ixgbe_adapter *adapter = netdev_priv(netdev); + + if (netif_running(netdev)) { + if (ixgbe_up(adapter)) { +@@ -4378,6 +6879,7 @@ + .resume = ixgbe_io_resume, + }; + ++#endif + static struct pci_driver ixgbe_driver = { + .name = ixgbe_driver_name, + .id_table = ixgbe_pci_tbl, +@@ -4387,9 +6889,21 @@ + .suspend = ixgbe_suspend, + .resume = ixgbe_resume, + #endif ++#ifndef USE_REBOOT_NOTIFIER + .shutdown = ixgbe_shutdown, ++#endif ++#ifdef HAVE_PCI_ERS + .err_handler = &ixgbe_err_handler ++#endif + }; ++ ++bool ixgbe_is_ixgbe(struct pci_dev *pcidev) ++{ ++ if (pci_dev_driver(pcidev) != &ixgbe_driver) ++ return false; ++ else ++ return true; ++} + + /** + * ixgbe_init_module - Driver Registration Routine +@@ -4399,16 +6913,21 @@ + **/ + static int __init ixgbe_init_module(void) + { +- printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, +- ixgbe_driver_string, ixgbe_driver_version); +- +- printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); +- ++ int ret; ++ printk(KERN_INFO "ixgbe: %s - version %s\n", ixgbe_driver_string, ++ ixgbe_driver_version); ++ ++ printk(KERN_INFO "%s\n", ixgbe_copyright); ++ ++#ifndef CONFIG_DCB ++ ixgbe_dcb_netlink_register(); ++#endif + #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) + dca_register_notify(&dca_notifier); + + #endif +- return pci_register_driver(&ixgbe_driver); ++ ret = pci_register_driver(&ixgbe_driver); ++ return ret; + } + + module_init(ixgbe_init_module); +@@ -4424,6 +6943,9 @@ + #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) + dca_unregister_notify(&dca_notifier); + #endif ++#ifndef CONFIG_DCB ++ ixgbe_dcb_netlink_unregister(); ++#endif + pci_unregister_driver(&ixgbe_driver); + } + +@@ -4439,7 +6961,7 @@ + return ret_val ? NOTIFY_BAD : NOTIFY_DONE; + } + #endif /* CONFIG_DCA or CONFIG_DCA_MODULE */ +- + module_exit(ixgbe_exit_module); + + /* ixgbe_main.c */ ++ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_osdep.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/ixgbe/ixgbe_osdep.h Wed Aug 05 11:05:50 2009 +0100 +@@ -0,0 +1,107 @@ ++/******************************************************************************* ++ ++ Intel 10 Gigabit PCI Express Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++ ++/* glue for the OS independent part of ixgbe ++ * includes register access macros ++ */ ++ ++#ifndef _IXGBE_OSDEP_H_ ++#define _IXGBE_OSDEP_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include "kcompat.h" ++ ++ ++#ifndef msleep ++#define msleep(x) do { if(in_interrupt()) { \ ++ /* Don't mdelay in interrupt context! */ \ ++ BUG(); \ ++ } else { \ ++ msleep(x); \ ++ } } while (0) ++ ++#endif ++ ++#undef ASSERT ++ ++#ifdef DBG ++#define hw_dbg(hw, S, A...) printk(KERN_DEBUG S, ## A) ++#else ++#define hw_dbg(hw, S, A...) do {} while (0) ++#endif ++ ++#ifdef DBG ++#define IXGBE_WRITE_REG(a, reg, value) do {\ ++ switch (reg) { \ ++ case IXGBE_EIMS: \ ++ case IXGBE_EIMC: \ ++ case IXGBE_EIAM: \ ++ case IXGBE_EIAC: \ ++ case IXGBE_EICR: \ ++ case IXGBE_EICS: \ ++ printk("%s: Reg - 0x%05X, value - 0x%08X\n", __FUNCTION__, \ ++ reg, (u32)(value)); \ ++ default: \ ++ break; \ ++ } \ ++ writel((value), ((a)->hw_addr + (reg))); \ ++} while (0) ++#else ++#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg))) ++#endif ++ ++#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg)) ++ ++#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \ ++ writel((value), ((a)->hw_addr + (reg) + ((offset) << 2)))) ++ ++#define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \ ++ readl((a)->hw_addr + (reg) + ((offset) << 2))) ++ ++#ifndef writeq ++#define writeq(val, addr) writel((u32) (val), addr); \ ++ writel((u32) (val >> 32), (addr + 4)); ++#endif ++ ++#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg))) ++ ++#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS) ++struct ixgbe_hw; ++extern u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg); ++extern void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value); ++#define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg_word ++#define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg_word ++#define IXGBE_EEPROM_GRANT_ATTEMPS 100 ++#define IXGBE_HTONL(_i) htonl(_i) ++#define IXGBE_HTONS(_i) htons(_i) ++ ++#endif /* _IXGBE_OSDEP_H_ */ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_param.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/ixgbe/ixgbe_param.c Wed Aug 05 11:05:50 2009 +0100 +@@ -0,0 +1,959 @@ ++/******************************************************************************* ++ ++ Intel 10 Gigabit PCI Express Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include ++#include ++ ++#include "ixgbe.h" ++ ++/* This is the only thing that needs to be changed to adjust the ++ * maximum number of ports that the driver can manage. ++ */ ++ ++#define IXGBE_MAX_NIC 8 ++ ++#define OPTION_UNSET -1 ++#define OPTION_DISABLED 0 ++#define OPTION_ENABLED 1 ++ ++/* All parameters are treated the same, as an integer array of values. ++ * This macro just reduces the need to repeat the same declaration code ++ * over and over (plus this helps to avoid typo bugs). ++ */ ++ ++#define IXGBE_PARAM_INIT { [0 ... IXGBE_MAX_NIC] = OPTION_UNSET } ++#ifndef module_param_array ++/* Module Parameters are always initialized to -1, so that the driver ++ * can tell the difference between no user specified value or the ++ * user asking for the default value. ++ * The true default values are loaded in when ixgbe_check_options is called. ++ * ++ * This is a GCC extension to ANSI C. ++ * See the item "Labeled Elements in Initializers" in the section ++ * "Extensions to the C Language Family" of the GCC documentation. ++ */ ++ ++#define IXGBE_PARAM(X, desc) \ ++ static const int __devinitdata X[IXGBE_MAX_NIC+1] = IXGBE_PARAM_INIT; \ ++ MODULE_PARM(X, "1-" __MODULE_STRING(IXGBE_MAX_NIC) "i"); \ ++ MODULE_PARM_DESC(X, desc); ++#else ++#define IXGBE_PARAM(X, desc) \ ++ static int __devinitdata X[IXGBE_MAX_NIC+1] = IXGBE_PARAM_INIT; \ ++ static unsigned int num_##X; \ ++ module_param_array_named(X, X, int, &num_##X, 0); \ ++ MODULE_PARM_DESC(X, desc); ++#endif ++ ++/* Interrupt Type ++ * ++ * Valid Range: 0-2 ++ * - 0 - Legacy Interrupt ++ * - 1 - MSI Interrupt ++ * - 2 - MSI-X Interrupt(s) ++ * ++ * Default Value: 2 ++ */ ++IXGBE_PARAM(InterruptType, "Change Interrupt Mode (0=Legacy, 1=MSI, 2=MSI-X), default 2"); ++#define IXGBE_INT_LEGACY 0 ++#define IXGBE_INT_MSI 1 ++#define IXGBE_INT_MSIX 2 ++#define IXGBE_DEFAULT_INT IXGBE_INT_MSIX ++ ++/* MQ - Multiple Queue enable/disable ++ * ++ * Valid Range: 0, 1 ++ * - 0 - disables MQ ++ * - 1 - enables MQ ++ * ++ * Default Value: 1 ++ */ ++ ++IXGBE_PARAM(MQ, "Disable or enable Multiple Queues, default 1"); ++ ++#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) ++/* DCA - Direct Cache Access (DCA) Control ++ * ++ * This option allows the device to hint to DCA enabled processors ++ * which CPU should have its cache warmed with the data being ++ * transferred over PCIe. This can increase performance by reducing ++ * cache misses. ixgbe hardware supports DCA for: ++ * tx descriptor writeback ++ * rx descriptor writeback ++ * rx data ++ * rx data header only (in packet split mode) ++ * ++ * enabling option 2 can cause cache thrash in some tests, particularly ++ * if the CPU is completely utilized ++ * ++ * Valid Range: 0 - 2 ++ * - 0 - disables DCA ++ * - 1 - enables DCA ++ * - 2 - enables DCA with rx data included ++ * ++ * Default Value: 2 ++ */ ++ ++#define IXGBE_MAX_DCA 2 ++ ++IXGBE_PARAM(DCA, "Disable or enable Direct Cache Access, 0=disabled, 1=descriptor only, 2=descriptor and data"); ++ ++#endif ++/* RSS - Receive-Side Scaling (RSS) Descriptor Queues ++ * ++ * Valid Range: 0-16 ++ * - 0 - disables RSS ++ * - 1 - enables RSS and sets the Desc. Q's to min(16, num_online_cpus()). ++ * - 2-16 - enables RSS and sets the Desc. Q's to the specified value. ++ * ++ * Default Value: 1 ++ */ ++ ++IXGBE_PARAM(RSS, "Number of Receive-Side Scaling Descriptor Queues, default 1=number of cpus"); ++ ++ ++ ++/* Interrupt Throttle Rate (interrupts/sec) ++ * ++ * Valid Range: 956-488281 (0=off, 1=dynamic) ++ * ++ * Default Value: 8000 ++ */ ++#define DEFAULT_ITR 8000 ++IXGBE_PARAM(InterruptThrottleRate, "Maximum interrupts per second, per vector, (956-488281), default 8000"); ++#define MAX_ITR IXGBE_MAX_INT_RATE ++#define MIN_ITR IXGBE_MIN_INT_RATE ++ ++#ifndef IXGBE_NO_LLI ++/* LLIPort (Low Latency Interrupt TCP Port) ++ * ++ * Valid Range: 0 - 65535 ++ * ++ * Default Value: 0 (disabled) ++ */ ++IXGBE_PARAM(LLIPort, "Low Latency Interrupt TCP Port (0-65535)"); ++ ++#define DEFAULT_LLIPORT 0 ++#define MAX_LLIPORT 0xFFFF ++#define MIN_LLIPORT 0 ++ ++/* LLIPush (Low Latency Interrupt on TCP Push flag) ++ * ++ * Valid Range: 0,1 ++ * ++ * Default Value: 0 (disabled) ++ */ ++IXGBE_PARAM(LLIPush, "Low Latency Interrupt on TCP Push flag (0,1)"); ++ ++#define DEFAULT_LLIPUSH 0 ++#define MAX_LLIPUSH 1 ++#define MIN_LLIPUSH 0 ++ ++/* LLISize (Low Latency Interrupt on Packet Size) ++ * ++ * Valid Range: 0 - 1500 ++ * ++ * Default Value: 0 (disabled) ++ */ ++IXGBE_PARAM(LLISize, "Low Latency Interrupt on Packet Size (0-1500)"); ++ ++#define DEFAULT_LLISIZE 0 ++#define MAX_LLISIZE 1500 ++#define MIN_LLISIZE 0 ++ ++/* LLIEType (Low Latency Interrupt Ethernet Type) ++ * ++ * Valid Range: 0 - 0x8fff ++ * ++ * Default Value: 0 (disabled) ++ */ ++IXGBE_PARAM(LLIEType, "Low Latency Interrupt Ethernet Protocol Type"); ++ ++#define DEFAULT_LLIETYPE 0 ++#define MAX_LLIETYPE 0x8fff ++#define MIN_LLIETYPE 0 ++ ++/* LLIVLANP (Low Latency Interrupt on VLAN priority threshold) ++ * ++ * Valid Range: 0 - 7 ++ * ++ * Default Value: 0 (disabled) ++ */ ++IXGBE_PARAM(LLIVLANP, "Low Latency Interrupt on VLAN priority threshold"); ++ ++#define DEFAULT_LLIVLANP 0 ++#define MAX_LLIVLANP 7 ++#define MIN_LLIVLANP 0 ++ ++#endif /* IXGBE_NO_LLI */ ++/* Rx buffer mode ++ * ++ * Valid Range: 0-2 0 = 1buf_mode_always, 1 = ps_mode_always and 2 = optimal ++ * ++ * Default Value: 2 ++ */ ++IXGBE_PARAM(RxBufferMode, "0=1 descriptor per packet,\n" ++ "\t\t\t1=use packet split, multiple descriptors per jumbo frame\n" ++ "\t\t\t2 (default)=use 1buf mode for 1500 mtu, packet split for jumbo"); ++ ++#define IXGBE_RXBUFMODE_1BUF_ALWAYS 0 ++#define IXGBE_RXBUFMODE_PS_ALWAYS 1 ++#define IXGBE_RXBUFMODE_OPTIMAL 2 ++#define IXGBE_DEFAULT_RXBUFMODE IXGBE_RXBUFMODE_OPTIMAL ++ ++/* Flow Director filtering mode ++ * ++ * Valid Range: 0-2 0 = off, 1 = Hashing (ATR), and 2 = perfect filters ++ * ++ * Default Value: 1 (ATR) ++ */ ++IXGBE_PARAM(FdirMode, "Flow Director filtering modes:\n" ++ "\t\t\t0 = Filtering off\n" ++ "\t\t\t1 = Signature Hashing filters (SW ATR)\n" ++ "\t\t\t2 = Perfect Filters"); ++ ++#define IXGBE_FDIR_FILTER_OFF 0 ++#define IXGBE_FDIR_FILTER_HASH 1 ++#define IXGBE_FDIR_FILTER_PERFECT 2 ++#define IXGBE_DEFAULT_FDIR_FILTER IXGBE_FDIR_FILTER_HASH ++ ++/* Flow Director packet buffer allocation level ++ * ++ * Valid Range: 0-2 0 = 8k hash/2k perfect, 1 = 16k hash/4k perfect, ++ * 2 = 32k hash/8k perfect ++ * ++ * Default Value: 0 ++ */ ++IXGBE_PARAM(FdirPballoc, "Flow Director packet buffer allocation level:\n" ++ "\t\t\t0 = 8k hash filters or 2k perfect filters\n" ++ "\t\t\t1 = 16k hash filters or 4k perfect filters\n" ++ "\t\t\t2 = 32k hash filters or 8k perfect filters"); ++ ++#define IXGBE_FDIR_PBALLOC_64K 0 ++#define IXGBE_FDIR_PBALLOC_128K 1 ++#define IXGBE_FDIR_PBALLOC_256K 2 ++#define IXGBE_DEFAULT_FDIR_PBALLOC IXGBE_FDIR_PBALLOC_64K ++ ++/* Software ATR packet sample rate ++ * ++ * Valid Range: 0-100 0 = off, 1-100 = rate of Tx packet inspection ++ * ++ * Default Value: 20 ++ */ ++IXGBE_PARAM(AtrSampleRate, "Software ATR Tx packet sample rate"); ++ ++#define IXGBE_MAX_ATR_SAMPLE_RATE 100 ++#define IXGBE_MIN_ATR_SAMPLE_RATE 1 ++#define IXGBE_ATR_SAMPLE_RATE_OFF 0 ++#define IXGBE_DEFAULT_ATR_SAMPLE_RATE 20 ++ ++struct ixgbe_option { ++ enum { enable_option, range_option, list_option } type; ++ const char *name; ++ const char *err; ++ int def; ++ union { ++ struct { /* range_option info */ ++ int min; ++ int max; ++ } r; ++ struct { /* list_option info */ ++ int nr; ++ const struct ixgbe_opt_list { ++ int i; ++ char *str; ++ } *p; ++ } l; ++ } arg; ++}; ++ ++static int __devinit ixgbe_validate_option(unsigned int *value, ++ struct ixgbe_option *opt) ++{ ++ if (*value == OPTION_UNSET) { ++ *value = opt->def; ++ return 0; ++ } ++ ++ switch (opt->type) { ++ case enable_option: ++ switch (*value) { ++ case OPTION_ENABLED: ++ printk(KERN_INFO "ixgbe: %s Enabled\n", opt->name); ++ return 0; ++ case OPTION_DISABLED: ++ printk(KERN_INFO "ixgbe: %s Disabled\n", opt->name); ++ return 0; ++ } ++ break; ++ case range_option: ++ if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { ++ printk(KERN_INFO "ixgbe: %s set to %d\n", opt->name, *value); ++ return 0; ++ } ++ break; ++ case list_option: { ++ int i; ++ const struct ixgbe_opt_list *ent; ++ ++ for (i = 0; i < opt->arg.l.nr; i++) { ++ ent = &opt->arg.l.p[i]; ++ if (*value == ent->i) { ++ if (ent->str[0] != '\0') ++ printk(KERN_INFO "%s\n", ent->str); ++ return 0; ++ } ++ } ++ } ++ break; ++ default: ++ BUG(); ++ } ++ ++ printk(KERN_INFO "ixgbe: Invalid %s specified (%d), %s\n", ++ opt->name, *value, opt->err); ++ *value = opt->def; ++ return -1; ++} ++ ++#define LIST_LEN(l) (sizeof(l) / sizeof(l[0])) ++ ++/** ++ * ixgbe_check_options - Range Checking for Command Line Parameters ++ * @adapter: board private structure ++ * ++ * This routine checks all command line parameters for valid user ++ * input. If an invalid value is given, or if no user specified ++ * value exists, a default value is used. The final value is stored ++ * in a variable in the adapter structure. ++ **/ ++void __devinit ixgbe_check_options(struct ixgbe_adapter *adapter) ++{ ++ int bd = adapter->bd_number; ++ u32 *aflags = &adapter->flags; ++ struct ixgbe_ring_feature *feature = adapter->ring_feature; ++ ++ if (bd >= IXGBE_MAX_NIC) { ++ printk(KERN_NOTICE ++ "Warning: no configuration for board #%d\n", bd); ++ printk(KERN_NOTICE "Using defaults for all values\n"); ++#ifndef module_param_array ++ bd = IXGBE_MAX_NIC; ++#endif ++ } ++ ++ { /* Interrupt Type */ ++ unsigned int i_type; ++ static struct ixgbe_option opt = { ++ .type = range_option, ++ .name = "Interrupt Type", ++ .err = ++ "using default of "__MODULE_STRING(IXGBE_DEFAULT_INT), ++ .def = IXGBE_DEFAULT_INT, ++ .arg = { .r = { .min = IXGBE_INT_LEGACY, ++ .max = IXGBE_INT_MSIX}} ++ }; ++ ++#ifdef module_param_array ++ if (num_InterruptType > bd) { ++#endif ++ i_type = InterruptType[bd]; ++ ixgbe_validate_option(&i_type, &opt); ++ switch (i_type) { ++ case IXGBE_INT_MSIX: ++ if (!(*aflags & IXGBE_FLAG_MSIX_CAPABLE)) ++ printk(KERN_INFO ++ "Ignoring MSI-X setting; " ++ "support unavailable\n"); ++ break; ++ case IXGBE_INT_MSI: ++ if (!(*aflags & IXGBE_FLAG_MSI_CAPABLE)) { ++ printk(KERN_INFO ++ "Ignoring MSI setting; " ++ "support unavailable\n"); ++ } else { ++ *aflags &= ~IXGBE_FLAG_MSIX_CAPABLE; ++ *aflags &= ~IXGBE_FLAG_DCB_CAPABLE; ++ } ++ break; ++ case IXGBE_INT_LEGACY: ++ default: ++ *aflags &= ~IXGBE_FLAG_MSIX_CAPABLE; ++ *aflags &= ~IXGBE_FLAG_MSI_CAPABLE; ++ *aflags &= ~IXGBE_FLAG_DCB_CAPABLE; ++ break; ++ } ++#ifdef module_param_array ++ } else { ++ *aflags |= IXGBE_FLAG_MSIX_CAPABLE; ++ *aflags |= IXGBE_FLAG_MSI_CAPABLE; ++ } ++#endif ++ } ++ { /* Multiple Queue Support */ ++ static struct ixgbe_option opt = { ++ .type = enable_option, ++ .name = "Multiple Queue Support", ++ .err = "defaulting to Enabled", ++ .def = OPTION_ENABLED ++ }; ++ ++#ifdef module_param_array ++ if (num_MQ > bd) { ++#endif ++ unsigned int mq = MQ[bd]; ++ ixgbe_validate_option(&mq, &opt); ++ if (mq) ++ *aflags |= IXGBE_FLAG_MQ_CAPABLE; ++ else ++ *aflags &= ~IXGBE_FLAG_MQ_CAPABLE; ++#ifdef module_param_array ++ } else { ++ if (opt.def == OPTION_ENABLED) ++ *aflags |= IXGBE_FLAG_MQ_CAPABLE; ++ else ++ *aflags &= ~IXGBE_FLAG_MQ_CAPABLE; ++ } ++#endif ++ /* Check Interoperability */ ++ if ((*aflags & IXGBE_FLAG_MQ_CAPABLE) && ++ !(*aflags & IXGBE_FLAG_MSIX_CAPABLE)) { ++ DPRINTK(PROBE, INFO, ++ "Multiple queues are not supported while MSI-X " ++ "is disabled. Disabling Multiple Queues.\n"); ++ *aflags &= ~IXGBE_FLAG_MQ_CAPABLE; ++ } ++ } ++#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) ++ { /* Direct Cache Access (DCA) */ ++ static struct ixgbe_option opt = { ++ .type = range_option, ++ .name = "Direct Cache Access (DCA)", ++ .err = "defaulting to Enabled", ++ .def = IXGBE_MAX_DCA, ++ .arg = { .r = { .min = OPTION_DISABLED, ++ .max = IXGBE_MAX_DCA}} ++ }; ++ unsigned int dca = opt.def; ++ ++#ifdef module_param_array ++ if (num_DCA > bd) { ++#endif ++ dca = DCA[bd]; ++ ixgbe_validate_option(&dca, &opt); ++ if (!dca) ++ *aflags &= ~IXGBE_FLAG_DCA_CAPABLE; ++ ++ /* Check Interoperability */ ++ if (!(*aflags & IXGBE_FLAG_DCA_CAPABLE)) { ++ DPRINTK(PROBE, INFO, "DCA is disabled\n"); ++ *aflags &= ~IXGBE_FLAG_DCA_ENABLED; ++ } ++ ++ if (dca == IXGBE_MAX_DCA) { ++ DPRINTK(PROBE, INFO, ++ "DCA enabled for rx data\n"); ++ adapter->flags |= IXGBE_FLAG_DCA_ENABLED_DATA; ++ } ++#ifdef module_param_array ++ } else { ++ /* make sure to clear the capability flag if the ++ * option is disabled by default above */ ++ if (opt.def == OPTION_DISABLED) ++ *aflags &= ~IXGBE_FLAG_DCA_CAPABLE; ++ } ++#endif ++ if (dca == IXGBE_MAX_DCA) ++ adapter->flags |= IXGBE_FLAG_DCA_ENABLED_DATA; ++ } ++#endif /* CONFIG_DCA or CONFIG_DCA_MODULE */ ++ { /* Receive-Side Scaling (RSS) */ ++ static struct ixgbe_option opt = { ++ .type = range_option, ++ .name = "Receive-Side Scaling (RSS)", ++ .err = "using default.", ++ .def = OPTION_ENABLED, ++ .arg = { .r = { .min = OPTION_DISABLED, ++ .max = IXGBE_MAX_RSS_INDICES}} ++ }; ++ unsigned int rss = RSS[bd]; ++ ++#ifdef module_param_array ++ if (num_RSS > bd) { ++#endif ++ switch (rss) { ++ case 1: ++ /* ++ * Base it off num_online_cpus() with ++ * a hardware limit cap. ++ */ ++ rss = min(IXGBE_MAX_RSS_INDICES, ++ (int)num_online_cpus()); ++ break; ++ default: ++ ixgbe_validate_option(&rss, &opt); ++ break; ++ } ++ feature[RING_F_RSS].indices = rss; ++ if (rss) ++ *aflags |= IXGBE_FLAG_RSS_ENABLED; ++ else ++ *aflags &= ~IXGBE_FLAG_RSS_ENABLED; ++#ifdef module_param_array ++ } else { ++ if (opt.def == OPTION_DISABLED) { ++ *aflags &= ~IXGBE_FLAG_RSS_ENABLED; ++ } else { ++ rss = min(IXGBE_MAX_RSS_INDICES, ++ (int)num_online_cpus()); ++ feature[RING_F_RSS].indices = rss; ++ if (rss) ++ *aflags |= IXGBE_FLAG_RSS_ENABLED; ++ else ++ *aflags &= ~IXGBE_FLAG_RSS_ENABLED; ++ } ++ } ++#endif ++ /* Check Interoperability */ ++ if (*aflags & IXGBE_FLAG_RSS_ENABLED) { ++ if (!(*aflags & IXGBE_FLAG_RSS_CAPABLE)) { ++ DPRINTK(PROBE, INFO, ++ "RSS is not supported on this " ++ "hardware. Disabling RSS.\n"); ++ *aflags &= ~IXGBE_FLAG_RSS_ENABLED; ++ feature[RING_F_RSS].indices = 0; ++ } else if (!(*aflags & IXGBE_FLAG_MQ_CAPABLE)) { ++ DPRINTK(PROBE, INFO, ++ "RSS is not supported while multiple " ++ "queues are disabled. " ++ "Disabling RSS.\n"); ++ *aflags &= ~IXGBE_FLAG_RSS_ENABLED; ++ *aflags &= ~IXGBE_FLAG_DCB_CAPABLE; ++ feature[RING_F_RSS].indices = 0; ++ } ++ } ++ } ++ { /* Interrupt Throttling Rate */ ++ static struct ixgbe_option opt = { ++ .type = range_option, ++ .name = "Interrupt Throttling Rate (ints/sec)", ++ .err = "using default of "__MODULE_STRING(DEFAULT_ITR), ++ .def = DEFAULT_ITR, ++ .arg = { .r = { .min = MIN_ITR, ++ .max = MAX_ITR }} ++ }; ++ ++#ifdef module_param_array ++ if (num_InterruptThrottleRate > bd) { ++#endif ++ u32 eitr = InterruptThrottleRate[bd]; ++ switch (eitr) { ++ case 0: ++ DPRINTK(PROBE, INFO, "%s turned off\n", ++ opt.name); ++ /* ++ * zero is a special value, we don't want to ++ * turn off ITR completely, just set it to an ++ * insane interrupt rate ++ */ ++ adapter->eitr_param = IXGBE_MAX_INT_RATE; ++ adapter->itr_setting = 0; ++ break; ++ case 1: ++ DPRINTK(PROBE, INFO, "dynamic interrupt " ++ "throttling enabled\n"); ++ adapter->eitr_param = 20000; ++ adapter->itr_setting = 1; ++ break; ++ default: ++ ixgbe_validate_option(&eitr, &opt); ++ adapter->eitr_param = eitr; ++ /* the first bit is used as control */ ++ adapter->itr_setting = eitr & ~1; ++ break; ++ } ++#ifdef module_param_array ++ } else { ++ adapter->eitr_param = DEFAULT_ITR; ++ adapter->itr_setting = DEFAULT_ITR; ++ } ++#endif ++ } ++#ifndef IXGBE_NO_LLI ++ { /* Low Latency Interrupt TCP Port*/ ++ static struct ixgbe_option opt = { ++ .type = range_option, ++ .name = "Low Latency Interrupt TCP Port", ++ .err = "using default of " ++ __MODULE_STRING(DEFAULT_LLIPORT), ++ .def = DEFAULT_LLIPORT, ++ .arg = { .r = { .min = MIN_LLIPORT, ++ .max = MAX_LLIPORT }} ++ }; ++ ++#ifdef module_param_array ++ if (num_LLIPort > bd) { ++#endif ++ adapter->lli_port = LLIPort[bd]; ++ if (adapter->lli_port) { ++ ixgbe_validate_option(&adapter->lli_port, &opt); ++ } else { ++ DPRINTK(PROBE, INFO, "%s turned off\n", ++ opt.name); ++ } ++#ifdef module_param_array ++ } else { ++ adapter->lli_port = opt.def; ++ } ++#endif ++ } ++ { /* Low Latency Interrupt on Packet Size */ ++ static struct ixgbe_option opt = { ++ .type = range_option, ++ .name = "Low Latency Interrupt on Packet Size", ++ .err = "using default of " ++ __MODULE_STRING(DEFAULT_LLISIZE), ++ .def = DEFAULT_LLISIZE, ++ .arg = { .r = { .min = MIN_LLISIZE, ++ .max = MAX_LLISIZE }} ++ }; ++ ++#ifdef module_param_array ++ if (num_LLISize > bd) { ++#endif ++ adapter->lli_size = LLISize[bd]; ++ if (adapter->lli_size) { ++ ixgbe_validate_option(&adapter->lli_size, &opt); ++ } else { ++ DPRINTK(PROBE, INFO, "%s turned off\n", ++ opt.name); ++ } ++#ifdef module_param_array ++ } else { ++ adapter->lli_size = opt.def; ++ } ++#endif ++ } ++ { /*Low Latency Interrupt on TCP Push flag*/ ++ static struct ixgbe_option opt = { ++ .type = enable_option, ++ .name = "Low Latency Interrupt on TCP Push flag", ++ .err = "defaulting to Disabled", ++ .def = OPTION_DISABLED ++ }; ++ ++#ifdef module_param_array ++ if (num_LLIPush > bd) { ++#endif ++ unsigned int lli_push = LLIPush[bd]; ++ ixgbe_validate_option(&lli_push, &opt); ++ if (lli_push) ++ *aflags |= IXGBE_FLAG_LLI_PUSH; ++ else ++ *aflags &= ~IXGBE_FLAG_LLI_PUSH; ++#ifdef module_param_array ++ } else { ++ if (opt.def == OPTION_ENABLED) ++ *aflags |= IXGBE_FLAG_LLI_PUSH; ++ else ++ *aflags &= ~IXGBE_FLAG_LLI_PUSH; ++ } ++#endif ++ } ++ { /* Low Latency Interrupt EtherType*/ ++ static struct ixgbe_option opt = { ++ .type = range_option, ++ .name = "Low Latency Interrupt on Ethernet Protocol Type", ++ .err = "using default of " ++ __MODULE_STRING(DEFAULT_LLIETYPE), ++ .def = DEFAULT_LLIETYPE, ++ .arg = { .r = { .min = MIN_LLIETYPE, ++ .max = MAX_LLIETYPE }} ++ }; ++ ++#ifdef module_param_array ++ if (num_LLIEType > bd) { ++#endif ++ adapter->lli_etype = LLIEType[bd]; ++ if (adapter->lli_etype) { ++ ixgbe_validate_option(&adapter->lli_etype, &opt); ++ } else { ++ DPRINTK(PROBE, INFO, "%s turned off\n", ++ opt.name); ++ } ++#ifdef module_param_array ++ } else { ++ adapter->lli_etype = opt.def; ++ } ++#endif ++ } ++ { /* LLI VLAN Priority */ ++ static struct ixgbe_option opt = { ++ .type = range_option, ++ .name = "Low Latency Interrupt on VLAN priority threashold", ++ .err = "using default of " ++ __MODULE_STRING(DEFAULT_LLIVLANP), ++ .def = DEFAULT_LLIVLANP, ++ .arg = { .r = { .min = MIN_LLIVLANP, ++ .max = MAX_LLIVLANP }} ++ }; ++ ++#ifdef module_param_array ++ if (num_LLIVLANP > bd) { ++#endif ++ adapter->lli_vlan_pri = LLIVLANP[bd]; ++ if (adapter->lli_vlan_pri) { ++ ixgbe_validate_option(&adapter->lli_vlan_pri, &opt); ++ } else { ++ DPRINTK(PROBE, INFO, "%s turned off\n", ++ opt.name); ++ } ++#ifdef module_param_array ++ } else { ++ adapter->lli_vlan_pri = opt.def; ++ } ++#endif ++ } ++#endif /* IXGBE_NO_LLI */ ++ { /* Rx buffer mode */ ++ unsigned int rx_buf_mode; ++ static struct ixgbe_option opt = { ++ .type = range_option, ++ .name = "Rx buffer mode", ++ .err = "using default of " ++ __MODULE_STRING(IXGBE_DEFAULT_RXBUFMODE), ++ .def = IXGBE_DEFAULT_RXBUFMODE, ++ .arg = {.r = {.min = IXGBE_RXBUFMODE_1BUF_ALWAYS, ++ .max = IXGBE_RXBUFMODE_OPTIMAL}} ++ }; ++ ++#ifdef module_param_array ++ if (num_RxBufferMode > bd) { ++#endif ++ rx_buf_mode = RxBufferMode[bd]; ++ ixgbe_validate_option(&rx_buf_mode, &opt); ++ switch (rx_buf_mode) { ++ case IXGBE_RXBUFMODE_OPTIMAL: ++ *aflags |= IXGBE_FLAG_RX_1BUF_CAPABLE; ++ *aflags |= IXGBE_FLAG_RX_PS_CAPABLE; ++ break; ++ case IXGBE_RXBUFMODE_PS_ALWAYS: ++ *aflags |= IXGBE_FLAG_RX_PS_CAPABLE; ++ break; ++ case IXGBE_RXBUFMODE_1BUF_ALWAYS: ++ *aflags |= IXGBE_FLAG_RX_1BUF_CAPABLE; ++ default: ++ break; ++ } ++#ifdef module_param_array ++ } else { ++ *aflags |= IXGBE_FLAG_RX_1BUF_CAPABLE; ++ *aflags |= IXGBE_FLAG_RX_PS_CAPABLE; ++ } ++#endif ++ } ++ { /* Flow Director filtering mode */ ++ unsigned int fdir_filter_mode; ++ static struct ixgbe_option opt = { ++ .type = range_option, ++ .name = "Flow Director filtering mode", ++ .err = "using default of " ++ __MODULE_STRING(IXGBE_DEFAULT_FDIR_FILTER), ++ .def = IXGBE_DEFAULT_FDIR_FILTER, ++ .arg = {.r = {.min = IXGBE_FDIR_FILTER_OFF, ++ .max = IXGBE_FDIR_FILTER_PERFECT}} ++ }; ++ ++ *aflags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; ++ *aflags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; ++ if (adapter->hw.mac.type == ixgbe_mac_82598EB) ++ goto no_flow_director; ++#ifdef module_param_array ++ if (num_FdirMode > bd) { ++#endif ++#ifdef HAVE_TX_MQ ++ fdir_filter_mode = FdirMode[bd]; ++#else ++ fdir_filter_mode = IXGBE_FDIR_FILTER_OFF; ++#endif /* HAVE_TX_MQ */ ++ ixgbe_validate_option(&fdir_filter_mode, &opt); ++ ++ switch (fdir_filter_mode) { ++ case IXGBE_FDIR_FILTER_OFF: ++ DPRINTK(PROBE, INFO, "Flow Director disabled\n"); ++ break; ++ case IXGBE_FDIR_FILTER_HASH: ++ *aflags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; ++ *aflags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; ++ feature[RING_F_FDIR].indices = ++ IXGBE_MAX_FDIR_INDICES; ++ DPRINTK(PROBE, INFO, ++ "Flow Director hash filtering enabled\n"); ++ break; ++ case IXGBE_FDIR_FILTER_PERFECT: ++ *aflags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; ++ *aflags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; ++ feature[RING_F_FDIR].indices = ++ IXGBE_MAX_FDIR_INDICES; ++ spin_lock_init(&adapter->fdir_perfect_lock); ++ DPRINTK(PROBE, INFO, ++ "Flow Director perfect filtering enabled\n"); ++ break; ++ default: ++ break; ++ } ++#ifdef module_param_array ++ } else { ++#ifdef HAVE_TX_MQ ++ *aflags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; ++ feature[RING_F_FDIR].indices = IXGBE_MAX_FDIR_INDICES; ++ DPRINTK(PROBE, INFO, ++ "Flow Director hash filtering enabled\n"); ++#else ++ *aflags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; ++ *aflags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; ++ feature[RING_F_FDIR].indices = 0; ++ DPRINTK(PROBE, INFO, ++ "Flow Director hash filtering disabled\n"); ++#endif /* HAVE_TX_MQ */ ++ } ++ /* Check interoperability */ ++ if ((*aflags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || ++ (*aflags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { ++ if (!(*aflags & IXGBE_FLAG_MQ_CAPABLE)) { ++ DPRINTK(PROBE, INFO, ++ "Flow Director is not supported " ++ "while multiple queues are disabled. " ++ "Disabling Flow Director\n"); ++ *aflags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; ++ *aflags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; ++ } ++ } ++#endif ++no_flow_director: ++ /* empty code line with semi-colon */ ; ++ } ++ { /* Flow Director packet buffer allocation */ ++ unsigned int fdir_pballoc_mode; ++ static struct ixgbe_option opt = { ++ .type = range_option, ++ .name = "Flow Director packet buffer allocation", ++ .err = "using default of " ++ __MODULE_STRING(IXGBE_DEFAULT_FDIR_PBALLOC), ++ .def = IXGBE_DEFAULT_FDIR_PBALLOC, ++ .arg = {.r = {.min = IXGBE_FDIR_PBALLOC_64K, ++ .max = IXGBE_FDIR_PBALLOC_256K}} ++ }; ++ char pstring[10]; ++ ++ if ((adapter->hw.mac.type == ixgbe_mac_82598EB) || ++ (!(*aflags & (IXGBE_FLAG_FDIR_HASH_CAPABLE | ++ IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) ++ goto no_fdir_pballoc; ++#ifdef module_param_array ++ if (num_FdirPballoc > bd) { ++#endif ++ fdir_pballoc_mode = FdirPballoc[bd]; ++ ixgbe_validate_option(&fdir_pballoc_mode, &opt); ++ switch (fdir_pballoc_mode) { ++ case IXGBE_FDIR_PBALLOC_64K: ++ adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; ++ sprintf(pstring, "64kB"); ++ break; ++ case IXGBE_FDIR_PBALLOC_128K: ++ adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_128K; ++ sprintf(pstring, "128kB"); ++ break; ++ case IXGBE_FDIR_PBALLOC_256K: ++ adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_256K; ++ sprintf(pstring, "256kB"); ++ break; ++ default: ++ break; ++ } ++ DPRINTK(PROBE, INFO, ++ "Flow Director allocated %s of packet buffer\n", ++ pstring); ++ ++#ifdef module_param_array ++ } else { ++ adapter->fdir_pballoc = opt.def; ++ DPRINTK(PROBE, INFO, ++ "Flow Director allocated 64kB of packet buffer\n"); ++ ++ } ++#endif ++no_fdir_pballoc: ++ /* empty code line with semi-colon */ ; ++ } ++ { /* Flow Director ATR Tx sample packet rate */ ++ static struct ixgbe_option opt = { ++ .type = range_option, ++ .name = "Software ATR Tx packet sample rate", ++ .err = "using default of " ++ __MODULE_STRING(IXGBE_DEFAULT_ATR_SAMPLE_RATE), ++ .def = IXGBE_DEFAULT_ATR_SAMPLE_RATE, ++ .arg = {.r = {.min = IXGBE_ATR_SAMPLE_RATE_OFF, ++ .max = IXGBE_MAX_ATR_SAMPLE_RATE}} ++ }; ++ static const char atr_string[] = ++ "ATR Tx Packet sample rate set to"; ++ ++ adapter->atr_sample_rate = IXGBE_ATR_SAMPLE_RATE_OFF; ++ if (adapter->hw.mac.type == ixgbe_mac_82598EB) ++ goto no_fdir_sample; ++ ++ /* no sample rate for perfect filtering */ ++ if (*aflags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) ++ goto no_fdir_sample; ++#ifdef module_param_array ++ if (num_AtrSampleRate > bd) { ++#endif ++ /* Only enable the sample rate if hashing (ATR) is on */ ++ if (*aflags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ++ adapter->atr_sample_rate = AtrSampleRate[bd]; ++ ++ if (adapter->atr_sample_rate) { ++ ixgbe_validate_option(&adapter->atr_sample_rate, ++ &opt); ++ DPRINTK(PROBE, INFO, "%s %d\n", atr_string, ++ adapter->atr_sample_rate); ++ } ++#ifdef module_param_array ++ } else { ++ /* Only enable the sample rate if hashing (ATR) is on */ ++ if (*aflags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ++ adapter->atr_sample_rate = opt.def; ++ ++ DPRINTK(PROBE, INFO, "%s default of %d\n", atr_string, ++ adapter->atr_sample_rate); ++ } ++#endif ++no_fdir_sample: ++ /* empty code line with semi-colon */ ; ++ } ++} +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_phy.c +--- a/drivers/net/ixgbe/ixgbe_phy.c Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe_phy.c Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -25,16 +25,52 @@ + + *******************************************************************************/ + +-#include +-#include +-#include +- ++#include "ixgbe_api.h" + #include "ixgbe_common.h" + #include "ixgbe_phy.h" + +-static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); +-static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); +-static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); ++static void ixgbe_i2c_start(struct ixgbe_hw *hw); ++static void ixgbe_i2c_stop(struct ixgbe_hw *hw); ++static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); ++static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); ++static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); ++static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); ++static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); ++static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); ++static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); ++static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); ++static bool ixgbe_get_i2c_data(u32 *i2cctl); ++void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); ++ ++/** ++ * ixgbe_init_phy_ops_generic - Inits PHY function ptrs ++ * @hw: pointer to the hardware structure ++ * ++ * Initialize the function pointers. ++ **/ ++s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) ++{ ++ struct ixgbe_phy_info *phy = &hw->phy; ++ ++ /* PHY */ ++ phy->ops.identify = &ixgbe_identify_phy_generic; ++ phy->ops.reset = &ixgbe_reset_phy_generic; ++ phy->ops.read_reg = &ixgbe_read_phy_reg_generic; ++ phy->ops.write_reg = &ixgbe_write_phy_reg_generic; ++ phy->ops.setup_link = &ixgbe_setup_phy_link_generic; ++ phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; ++ phy->ops.check_link = NULL; ++ phy->ops.get_firmware_version = NULL; ++ phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; ++ phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; ++ phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; ++ phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; ++ phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; ++ phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic; ++ phy->sfp_type = ixgbe_sfp_type_unknown; ++ ++ return 0; ++} + + /** + * ixgbe_identify_phy_generic - Get physical layer module +@@ -46,6 +82,7 @@ + { + s32 status = IXGBE_ERR_PHY_ADDR_INVALID; + u32 phy_addr; ++ u16 ext_ability = 0; + + if (hw->phy.type == ixgbe_phy_unknown) { + for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { +@@ -54,10 +91,29 @@ + ixgbe_get_phy_id(hw); + hw->phy.type = + ixgbe_get_phy_type_from_id(hw->phy.id); ++ ++ if (hw->phy.type == ixgbe_phy_unknown) { ++ hw->phy.ops.read_reg(hw, ++ IXGBE_MDIO_PHY_EXT_ABILITY, ++ IXGBE_MDIO_PMA_PMD_DEV_TYPE, ++ &ext_ability); ++ if (ext_ability & ++ IXGBE_MDIO_PHY_10GBASET_ABILITY || ++ ext_ability & ++ IXGBE_MDIO_PHY_1000BASET_ABILITY) ++ hw->phy.type = ++ ixgbe_phy_cu_unknown; ++ else ++ hw->phy.type = ++ ixgbe_phy_generic; ++ } ++ + status = 0; + break; + } + } ++ if (status != 0) ++ hw->phy.addr = 0; + } else { + status = 0; + } +@@ -70,7 +126,7 @@ + * @hw: pointer to hardware structure + * + **/ +-static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) ++bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) + { + u16 phy_id = 0; + bool valid = false; +@@ -90,7 +146,7 @@ + * @hw: pointer to hardware structure + * + **/ +-static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) ++s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) + { + u32 status; + u16 phy_id_high = 0; +@@ -116,13 +172,16 @@ + * @hw: pointer to hardware structure + * + **/ +-static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) ++enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) + { + enum ixgbe_phy_type phy_type; + + switch (phy_id) { + case TN1010_PHY_ID: + phy_type = ixgbe_phy_tn; ++ break; ++ case AQ1002_PHY_ID: ++ phy_type = ixgbe_phy_aq; + break; + case QT2022_PHY_ID: + phy_type = ixgbe_phy_qt; +@@ -135,6 +194,7 @@ + break; + } + ++ hw_dbg(hw, "phy type found is %d\n", phy_type); + return phy_type; + } + +@@ -144,13 +204,40 @@ + **/ + s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) + { ++ u32 i; ++ u16 ctrl = 0; ++ s32 status = 0; ++ ++ if (hw->phy.type == ixgbe_phy_unknown) ++ status = ixgbe_identify_phy_generic(hw); ++ ++ if (status != 0 || hw->phy.type == ixgbe_phy_none) ++ goto out; ++ + /* + * Perform soft PHY reset to the PHY_XS. + * This will cause a soft reset to the PHY + */ +- return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, +- IXGBE_MDIO_PHY_XS_DEV_TYPE, +- IXGBE_MDIO_PHY_XS_RESET); ++ hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, ++ IXGBE_MDIO_PHY_XS_DEV_TYPE, ++ IXGBE_MDIO_PHY_XS_RESET); ++ ++ /* Poll for reset bit to self-clear indicating reset is complete */ ++ for (i = 0; i < 500; i++) { ++ msleep(1); ++ hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, ++ IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); ++ if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) ++ break; ++ } ++ ++ if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { ++ status = IXGBE_ERR_RESET_FAILED; ++ hw_dbg(hw, "PHY reset polling failed to complete.\n"); ++ } ++ ++out: ++ return status; + } + + /** +@@ -343,34 +430,68 @@ + } + + /** +- * ixgbe_setup_phy_link_generic - Set and restart autoneg +- * @hw: pointer to hardware structure ++ * ixgbe_setup_phy_link_generic - Set and restart autoneg ++ * @hw: pointer to hardware structure + * +- * Restart autonegotiation and PHY and waits for completion. ++ * Restart autonegotiation and PHY and waits for completion. + **/ + s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) + { +- s32 status = IXGBE_NOT_IMPLEMENTED; ++ s32 status = 0; + u32 time_out; + u32 max_time_out = 10; + u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; ++ bool autoneg = false; ++ ixgbe_link_speed speed; + +- /* +- * Set advertisement settings in PHY based on autoneg_advertised +- * settings. If autoneg_advertised = 0, then advertise default values +- * tnx devices cannot be "forced" to a autoneg 10G and fail. But can +- * for a 1G. +- */ +- hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, +- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); ++ ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); + +- if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL) +- autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */ +- else +- autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */ ++ if (speed & IXGBE_LINK_SPEED_10GB_FULL) { ++ /* Set or unset auto-negotiation 10G advertisement */ ++ hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ++ &autoneg_reg); + +- hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, +- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); ++ autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; ++ if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) ++ autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; ++ ++ hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ++ autoneg_reg); ++ } ++ ++ if (speed & IXGBE_LINK_SPEED_1GB_FULL) { ++ /* Set or unset auto-negotiation 1G advertisement */ ++ hw->phy.ops.read_reg(hw, ++ IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ++ &autoneg_reg); ++ ++ autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; ++ if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) ++ autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; ++ ++ hw->phy.ops.write_reg(hw, ++ IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ++ autoneg_reg); ++ } ++ ++ if (speed & IXGBE_LINK_SPEED_100_FULL) { ++ /* Set or unset auto-negotiation 100M advertisement */ ++ hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ++ &autoneg_reg); ++ ++ autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; ++ if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) ++ autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; ++ ++ hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ++ autoneg_reg); ++ } + + /* Restart PHY autonegotiation and wait for completion */ + hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, +@@ -391,13 +512,14 @@ + + autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; + if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { +- status = 0; + break; + } + } + +- if (time_out == max_time_out) ++ if (time_out == max_time_out) { + status = IXGBE_ERR_LINK_SETUP; ++ hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out"); ++ } + + return status; + } +@@ -426,6 +548,9 @@ + if (speed & IXGBE_LINK_SPEED_1GB_FULL) + hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; + ++ if (speed & IXGBE_LINK_SPEED_100_FULL) ++ hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; ++ + /* Setup link based on the new speed settings */ + hw->phy.ops.setup_link(hw); + +@@ -433,258 +558,37 @@ + } + + /** +- * ixgbe_reset_phy_nl - Performs a PHY reset ++ * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities + * @hw: pointer to hardware structure ++ * @speed: pointer to link speed ++ * @autoneg: boolean auto-negotiation value ++ * ++ * Determines the link capabilities by reading the AUTOC register. + **/ +-s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) ++s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, ++ ixgbe_link_speed *speed, ++ bool *autoneg) + { +- u16 phy_offset, control, eword, edata, block_crc; +- bool end_data = false; +- u16 list_offset, data_offset; +- u16 phy_data = 0; +- s32 ret_val = 0; +- u32 i; ++ s32 status = IXGBE_ERR_LINK_SETUP; ++ u16 speed_ability; + +- hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, +- IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); ++ *speed = 0; ++ *autoneg = true; + +- /* reset the PHY and poll for completion */ +- hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, +- IXGBE_MDIO_PHY_XS_DEV_TYPE, +- (phy_data | IXGBE_MDIO_PHY_XS_RESET)); ++ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, ++ IXGBE_MDIO_PMA_PMD_DEV_TYPE, ++ &speed_ability); + +- for (i = 0; i < 100; i++) { +- hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, +- IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); +- if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) +- break; +- msleep(10); ++ if (status == 0) { ++ if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) ++ *speed |= IXGBE_LINK_SPEED_10GB_FULL; ++ if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) ++ *speed |= IXGBE_LINK_SPEED_1GB_FULL; ++ if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) ++ *speed |= IXGBE_LINK_SPEED_100_FULL; + } + +- if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { +- hw_dbg(hw, "PHY reset did not complete.\n"); +- ret_val = IXGBE_ERR_PHY; +- goto out; +- } +- +- /* Get init offsets */ +- ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, +- &data_offset); +- if (ret_val != 0) +- goto out; +- +- ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); +- data_offset++; +- while (!end_data) { +- /* +- * Read control word from PHY init contents offset +- */ +- ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); +- control = (eword & IXGBE_CONTROL_MASK_NL) >> +- IXGBE_CONTROL_SHIFT_NL; +- edata = eword & IXGBE_DATA_MASK_NL; +- switch (control) { +- case IXGBE_DELAY_NL: +- data_offset++; +- hw_dbg(hw, "DELAY: %d MS\n", edata); +- msleep(edata); +- break; +- case IXGBE_DATA_NL: +- hw_dbg(hw, "DATA: \n"); +- data_offset++; +- hw->eeprom.ops.read(hw, data_offset++, +- &phy_offset); +- for (i = 0; i < edata; i++) { +- hw->eeprom.ops.read(hw, data_offset, &eword); +- hw->phy.ops.write_reg(hw, phy_offset, +- IXGBE_TWINAX_DEV, eword); +- hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, +- phy_offset); +- data_offset++; +- phy_offset++; +- } +- break; +- case IXGBE_CONTROL_NL: +- data_offset++; +- hw_dbg(hw, "CONTROL: \n"); +- if (edata == IXGBE_CONTROL_EOL_NL) { +- hw_dbg(hw, "EOL\n"); +- end_data = true; +- } else if (edata == IXGBE_CONTROL_SOL_NL) { +- hw_dbg(hw, "SOL\n"); +- } else { +- hw_dbg(hw, "Bad control value\n"); +- ret_val = IXGBE_ERR_PHY; +- goto out; +- } +- break; +- default: +- hw_dbg(hw, "Bad control type\n"); +- ret_val = IXGBE_ERR_PHY; +- goto out; +- } +- } +- +-out: +- return ret_val; +-} +- +-/** +- * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns +- * the PHY type. +- * @hw: pointer to hardware structure +- * +- * Searches for and identifies the SFP module. Assigns appropriate PHY type. +- **/ +-s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) +-{ +- s32 status = IXGBE_ERR_PHY_ADDR_INVALID; +- u32 vendor_oui = 0; +- u8 identifier = 0; +- u8 comp_codes_1g = 0; +- u8 comp_codes_10g = 0; +- u8 oui_bytes[4] = {0, 0, 0, 0}; +- u8 transmission_media = 0; +- +- status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, +- &identifier); +- +- if (status == IXGBE_ERR_SFP_NOT_PRESENT) { +- hw->phy.sfp_type = ixgbe_sfp_type_not_present; +- goto out; +- } +- +- if (identifier == IXGBE_SFF_IDENTIFIER_SFP) { +- hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, +- &comp_codes_1g); +- hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, +- &comp_codes_10g); +- hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA, +- &transmission_media); +- +- /* ID Module +- * ============ +- * 0 SFP_DA_CU +- * 1 SFP_SR +- * 2 SFP_LR +- */ +- if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE) +- hw->phy.sfp_type = ixgbe_sfp_type_da_cu; +- else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) +- hw->phy.sfp_type = ixgbe_sfp_type_sr; +- else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) +- hw->phy.sfp_type = ixgbe_sfp_type_lr; +- else +- hw->phy.sfp_type = ixgbe_sfp_type_unknown; +- +- /* Determine PHY vendor */ +- if (hw->phy.type == ixgbe_phy_unknown) { +- hw->phy.id = identifier; +- hw->phy.ops.read_i2c_eeprom(hw, +- IXGBE_SFF_VENDOR_OUI_BYTE0, +- &oui_bytes[0]); +- hw->phy.ops.read_i2c_eeprom(hw, +- IXGBE_SFF_VENDOR_OUI_BYTE1, +- &oui_bytes[1]); +- hw->phy.ops.read_i2c_eeprom(hw, +- IXGBE_SFF_VENDOR_OUI_BYTE2, +- &oui_bytes[2]); +- +- vendor_oui = +- ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | +- (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | +- (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); +- +- switch (vendor_oui) { +- case IXGBE_SFF_VENDOR_OUI_TYCO: +- if (transmission_media & +- IXGBE_SFF_TWIN_AX_CAPABLE) +- hw->phy.type = ixgbe_phy_tw_tyco; +- break; +- case IXGBE_SFF_VENDOR_OUI_FTL: +- hw->phy.type = ixgbe_phy_sfp_ftl; +- break; +- case IXGBE_SFF_VENDOR_OUI_AVAGO: +- hw->phy.type = ixgbe_phy_sfp_avago; +- break; +- default: +- if (transmission_media & +- IXGBE_SFF_TWIN_AX_CAPABLE) +- hw->phy.type = ixgbe_phy_tw_unknown; +- else +- hw->phy.type = ixgbe_phy_sfp_unknown; +- break; +- } +- } +- status = 0; +- } +- +-out: + return status; +-} +- +-/** +- * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see +- * if it supports a given SFP+ module type, if so it returns the offsets to the +- * phy init sequence block. +- * @hw: pointer to hardware structure +- * @list_offset: offset to the SFP ID list +- * @data_offset: offset to the SFP data block +- **/ +-s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, +- u16 *list_offset, +- u16 *data_offset) +-{ +- u16 sfp_id; +- +- if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) +- return IXGBE_ERR_SFP_NOT_SUPPORTED; +- +- if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) +- return IXGBE_ERR_SFP_NOT_PRESENT; +- +- if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && +- (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) +- return IXGBE_ERR_SFP_NOT_SUPPORTED; +- +- /* Read offset to PHY init contents */ +- hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); +- +- if ((!*list_offset) || (*list_offset == 0xFFFF)) +- return IXGBE_ERR_PHY; +- +- /* Shift offset to first ID word */ +- (*list_offset)++; +- +- /* +- * Find the matching SFP ID in the EEPROM +- * and program the init sequence +- */ +- hw->eeprom.ops.read(hw, *list_offset, &sfp_id); +- +- while (sfp_id != IXGBE_PHY_INIT_END_NL) { +- if (sfp_id == hw->phy.sfp_type) { +- (*list_offset)++; +- hw->eeprom.ops.read(hw, *list_offset, data_offset); +- if ((!*data_offset) || (*data_offset == 0xFFFF)) { +- hw_dbg(hw, "SFP+ module not supported\n"); +- return IXGBE_ERR_SFP_NOT_SUPPORTED; +- } else { +- break; +- } +- } else { +- (*list_offset) += 2; +- if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) +- return IXGBE_ERR_PHY; +- } +- } +- +- if (sfp_id == IXGBE_PHY_INIT_END_NL) { +- hw_dbg(hw, "No matching SFP+ module found\n"); +- return IXGBE_ERR_SFP_NOT_SUPPORTED; +- } +- +- return 0; + } + + /** +@@ -736,6 +640,100 @@ + } + + /** ++ * ixgbe_setup_phy_link_tnx - Set and restart autoneg ++ * @hw: pointer to hardware structure ++ * ++ * Restart autonegotiation and PHY and waits for completion. ++ **/ ++s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) ++{ ++ s32 status = 0; ++ u32 time_out; ++ u32 max_time_out = 10; ++ u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; ++ bool autoneg = false; ++ ixgbe_link_speed speed; ++ ++ ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); ++ ++ if (speed & IXGBE_LINK_SPEED_10GB_FULL) { ++ /* Set or unset auto-negotiation 10G advertisement */ ++ hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ++ &autoneg_reg); ++ ++ autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; ++ if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) ++ autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; ++ ++ hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ++ autoneg_reg); ++ } ++ ++ if (speed & IXGBE_LINK_SPEED_1GB_FULL) { ++ /* Set or unset auto-negotiation 1G advertisement */ ++ hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ++ &autoneg_reg); ++ ++ autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; ++ if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) ++ autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; ++ ++ hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ++ autoneg_reg); ++ } ++ ++ if (speed & IXGBE_LINK_SPEED_100_FULL) { ++ /* Set or unset auto-negotiation 100M advertisement */ ++ hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ++ &autoneg_reg); ++ ++ autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; ++ if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) ++ autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; ++ ++ hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ++ autoneg_reg); ++ } ++ ++ /* Restart PHY autonegotiation and wait for completion */ ++ hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); ++ ++ autoneg_reg |= IXGBE_MII_RESTART; ++ ++ hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); ++ ++ /* Wait for autonegotiation to finish */ ++ for (time_out = 0; time_out < max_time_out; time_out++) { ++ udelay(10); ++ /* Restart PHY autonegotiation and wait for completion */ ++ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, ++ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ++ &autoneg_reg); ++ ++ autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; ++ if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { ++ break; ++ } ++ } ++ ++ if (time_out == max_time_out) { ++ status = IXGBE_ERR_LINK_SETUP; ++ hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out"); ++ } ++ ++ return status; ++} ++ ++ ++/** + * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version + * @hw: pointer to hardware structure + * @firmware_version: pointer to the PHY Firmware Version +@@ -752,3 +750,897 @@ + return status; + } + ++ ++/** ++ * ixgbe_get_phy_firmware_version_aq - Gets the PHY Firmware Version ++ * @hw: pointer to hardware structure ++ * @firmware_version: pointer to the PHY Firmware Version ++ **/ ++s32 ixgbe_get_phy_firmware_version_aq(struct ixgbe_hw *hw, ++ u16 *firmware_version) ++{ ++ s32 status = 0; ++ ++ status = hw->phy.ops.read_reg(hw, AQ_FW_REV, ++ IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ++ firmware_version); ++ ++ return status; ++} ++ ++/** ++ * ixgbe_reset_phy_nl - Performs a PHY reset ++ * @hw: pointer to hardware structure ++ **/ ++s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) ++{ ++ u16 phy_offset, control, eword, edata, block_crc; ++ bool end_data = false; ++ u16 list_offset, data_offset; ++ u16 phy_data = 0; ++ s32 ret_val = 0; ++ u32 i; ++ ++ hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, ++ IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); ++ ++ /* reset the PHY and poll for completion */ ++ hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, ++ IXGBE_MDIO_PHY_XS_DEV_TYPE, ++ (phy_data | IXGBE_MDIO_PHY_XS_RESET)); ++ ++ for (i = 0; i < 100; i++) { ++ hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, ++ IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); ++ if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) ++ break; ++ msleep(10); ++ } ++ ++ if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { ++ hw_dbg(hw, "PHY reset did not complete.\n"); ++ ret_val = IXGBE_ERR_PHY; ++ goto out; ++ } ++ ++ /* Get init offsets */ ++ ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, ++ &data_offset); ++ if (ret_val != 0) ++ goto out; ++ ++ ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); ++ data_offset++; ++ while (!end_data) { ++ /* ++ * Read control word from PHY init contents offset ++ */ ++ ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); ++ control = (eword & IXGBE_CONTROL_MASK_NL) >> ++ IXGBE_CONTROL_SHIFT_NL; ++ edata = eword & IXGBE_DATA_MASK_NL; ++ switch (control) { ++ case IXGBE_DELAY_NL: ++ data_offset++; ++ hw_dbg(hw, "DELAY: %d MS\n", edata); ++ msleep(edata); ++ break; ++ case IXGBE_DATA_NL: ++ hw_dbg(hw, "DATA: \n"); ++ data_offset++; ++ hw->eeprom.ops.read(hw, data_offset++, ++ &phy_offset); ++ for (i = 0; i < edata; i++) { ++ hw->eeprom.ops.read(hw, data_offset, &eword); ++ hw->phy.ops.write_reg(hw, phy_offset, ++ IXGBE_TWINAX_DEV, eword); ++ hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, ++ phy_offset); ++ data_offset++; ++ phy_offset++; ++ } ++ break; ++ case IXGBE_CONTROL_NL: ++ data_offset++; ++ hw_dbg(hw, "CONTROL: \n"); ++ if (edata == IXGBE_CONTROL_EOL_NL) { ++ hw_dbg(hw, "EOL\n"); ++ end_data = true; ++ } else if (edata == IXGBE_CONTROL_SOL_NL) { ++ hw_dbg(hw, "SOL\n"); ++ } else { ++ hw_dbg(hw, "Bad control value\n"); ++ ret_val = IXGBE_ERR_PHY; ++ goto out; ++ } ++ break; ++ default: ++ hw_dbg(hw, "Bad control type\n"); ++ ret_val = IXGBE_ERR_PHY; ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * ixgbe_identify_sfp_module_generic - Identifies SFP modules ++ * @hw: pointer to hardware structure ++ * ++ * Searches for and identifies the SFP module and assigns appropriate PHY type. ++ **/ ++s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) ++{ ++ s32 status = IXGBE_ERR_PHY_ADDR_INVALID; ++ u32 vendor_oui = 0; ++ enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; ++ u8 identifier = 0; ++ u8 comp_codes_1g = 0; ++ u8 comp_codes_10g = 0; ++ u8 oui_bytes[3] = {0, 0, 0}; ++ u8 cable_tech = 0; ++ u16 enforce_sfp = 0; ++ ++ if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { ++ hw->phy.sfp_type = ixgbe_sfp_type_not_present; ++ status = IXGBE_ERR_SFP_NOT_PRESENT; ++ goto out; ++ } ++ ++ status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, ++ &identifier); ++ ++ if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) { ++ status = IXGBE_ERR_SFP_NOT_PRESENT; ++ hw->phy.sfp_type = ixgbe_sfp_type_not_present; ++ if (hw->phy.type != ixgbe_phy_nl) { ++ hw->phy.id = 0; ++ hw->phy.type = ixgbe_phy_unknown; ++ } ++ goto out; ++ } ++ ++ /* LAN ID is needed for sfp_type determination */ ++ hw->mac.ops.set_lan_id(hw); ++ ++ if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { ++ hw->phy.type = ixgbe_phy_sfp_unsupported; ++ status = IXGBE_ERR_SFP_NOT_SUPPORTED; ++ } else { ++ hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, ++ &comp_codes_1g); ++ hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, ++ &comp_codes_10g); ++ hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY, ++ &cable_tech); ++ ++ /* ID Module ++ * ========= ++ * 0 SFP_DA_CU ++ * 1 SFP_SR ++ * 2 SFP_LR ++ * 3 SFP_DA_CORE0 - 82599-specific ++ * 4 SFP_DA_CORE1 - 82599-specific ++ * 5 SFP_SR/LR_CORE0 - 82599-specific ++ * 6 SFP_SR/LR_CORE1 - 82599-specific ++ */ ++ if (hw->mac.type == ixgbe_mac_82598EB) { ++ if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) ++ hw->phy.sfp_type = ixgbe_sfp_type_da_cu; ++ else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) ++ hw->phy.sfp_type = ixgbe_sfp_type_sr; ++ else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) ++ hw->phy.sfp_type = ixgbe_sfp_type_lr; ++ else ++ hw->phy.sfp_type = ixgbe_sfp_type_unknown; ++ } else if (hw->mac.type == ixgbe_mac_82599EB) { ++ if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) ++ if (hw->bus.lan_id == 0) ++ hw->phy.sfp_type = ++ ixgbe_sfp_type_da_cu_core0; ++ else ++ hw->phy.sfp_type = ++ ixgbe_sfp_type_da_cu_core1; ++ else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) ++ if (hw->bus.lan_id == 0) ++ hw->phy.sfp_type = ++ ixgbe_sfp_type_srlr_core0; ++ else ++ hw->phy.sfp_type = ++ ixgbe_sfp_type_srlr_core1; ++ else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) ++ if (hw->bus.lan_id == 0) ++ hw->phy.sfp_type = ++ ixgbe_sfp_type_srlr_core0; ++ else ++ hw->phy.sfp_type = ++ ixgbe_sfp_type_srlr_core1; ++ else ++ hw->phy.sfp_type = ixgbe_sfp_type_unknown; ++ } ++ ++ if (hw->phy.sfp_type != stored_sfp_type) ++ hw->phy.sfp_setup_needed = true; ++ ++ /* Determine if the SFP+ PHY is dual speed or not. */ ++ hw->phy.multispeed_fiber = false; ++ if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && ++ (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || ++ ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && ++ (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) ++ hw->phy.multispeed_fiber = true; ++ /* Determine PHY vendor */ ++ if (hw->phy.type != ixgbe_phy_nl) { ++ hw->phy.id = identifier; ++ hw->phy.ops.read_i2c_eeprom(hw, ++ IXGBE_SFF_VENDOR_OUI_BYTE0, ++ &oui_bytes[0]); ++ hw->phy.ops.read_i2c_eeprom(hw, ++ IXGBE_SFF_VENDOR_OUI_BYTE1, ++ &oui_bytes[1]); ++ hw->phy.ops.read_i2c_eeprom(hw, ++ IXGBE_SFF_VENDOR_OUI_BYTE2, ++ &oui_bytes[2]); ++ ++ vendor_oui = ++ ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | ++ (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | ++ (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); ++ ++ switch (vendor_oui) { ++ case IXGBE_SFF_VENDOR_OUI_TYCO: ++ if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) ++ hw->phy.type = ixgbe_phy_tw_tyco; ++ break; ++ case IXGBE_SFF_VENDOR_OUI_FTL: ++ hw->phy.type = ixgbe_phy_sfp_ftl; ++ break; ++ case IXGBE_SFF_VENDOR_OUI_AVAGO: ++ hw->phy.type = ixgbe_phy_sfp_avago; ++ break; ++ case IXGBE_SFF_VENDOR_OUI_INTEL: ++ hw->phy.type = ixgbe_phy_sfp_intel; ++ break; ++ default: ++ if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) ++ hw->phy.type = ixgbe_phy_tw_unknown; ++ else ++ hw->phy.type = ixgbe_phy_sfp_unknown; ++ break; ++ } ++ } ++ ++ /* All passive DA cables are supported */ ++ if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { ++ status = 0; ++ goto out; ++ } ++ ++ /* 1G SFP modules are not supported */ ++ if (comp_codes_10g == 0) { ++ hw->phy.type = ixgbe_phy_sfp_unsupported; ++ status = IXGBE_ERR_SFP_NOT_SUPPORTED; ++ goto out; ++ } ++ ++ /* Anything else 82598-based is supported */ ++ if (hw->mac.type == ixgbe_mac_82598EB) { ++ status = 0; ++ goto out; ++ } ++ ++ ixgbe_get_device_caps(hw, &enforce_sfp); ++ if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { ++ /* Make sure we're a supported PHY type */ ++ if (hw->phy.type == ixgbe_phy_sfp_intel) { ++ status = 0; ++ } else { ++ hw_dbg(hw, "SFP+ module not supported\n"); ++ hw->phy.type = ixgbe_phy_sfp_unsupported; ++ status = IXGBE_ERR_SFP_NOT_SUPPORTED; ++ } ++ } else { ++ status = 0; ++ } ++ } ++ ++out: ++ return status; ++} ++ ++/** ++ * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence ++ * @hw: pointer to hardware structure ++ * @list_offset: offset to the SFP ID list ++ * @data_offset: offset to the SFP data block ++ * ++ * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if ++ * so it returns the offsets to the phy init sequence block. ++ **/ ++s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, ++ u16 *list_offset, ++ u16 *data_offset) ++{ ++ u16 sfp_id; ++ ++ if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) ++ return IXGBE_ERR_SFP_NOT_SUPPORTED; ++ ++ if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) ++ return IXGBE_ERR_SFP_NOT_PRESENT; ++ ++ if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && ++ (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) ++ return IXGBE_ERR_SFP_NOT_SUPPORTED; ++ ++ /* Read offset to PHY init contents */ ++ hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); ++ ++ if ((!*list_offset) || (*list_offset == 0xFFFF)) ++ return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; ++ ++ /* Shift offset to first ID word */ ++ (*list_offset)++; ++ ++ /* ++ * Find the matching SFP ID in the EEPROM ++ * and program the init sequence ++ */ ++ hw->eeprom.ops.read(hw, *list_offset, &sfp_id); ++ ++ while (sfp_id != IXGBE_PHY_INIT_END_NL) { ++ if (sfp_id == hw->phy.sfp_type) { ++ (*list_offset)++; ++ hw->eeprom.ops.read(hw, *list_offset, data_offset); ++ if ((!*data_offset) || (*data_offset == 0xFFFF)) { ++ hw_dbg(hw, "SFP+ module not supported\n"); ++ return IXGBE_ERR_SFP_NOT_SUPPORTED; ++ } else { ++ break; ++ } ++ } else { ++ (*list_offset) += 2; ++ if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) ++ return IXGBE_ERR_PHY; ++ } ++ } ++ ++ if (sfp_id == IXGBE_PHY_INIT_END_NL) { ++ hw_dbg(hw, "No matching SFP+ module found\n"); ++ return IXGBE_ERR_SFP_NOT_SUPPORTED; ++ } ++ ++ return 0; ++} ++ ++/** ++ * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface ++ * @hw: pointer to hardware structure ++ * @byte_offset: EEPROM byte offset to read ++ * @eeprom_data: value read ++ * ++ * Performs byte read operation to SFP module's EEPROM over I2C interface. ++ **/ ++s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, ++ u8 *eeprom_data) ++{ ++ return hw->phy.ops.read_i2c_byte(hw, byte_offset, ++ IXGBE_I2C_EEPROM_DEV_ADDR, ++ eeprom_data); ++} ++ ++/** ++ * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface ++ * @hw: pointer to hardware structure ++ * @byte_offset: EEPROM byte offset to write ++ * @eeprom_data: value to write ++ * ++ * Performs byte write operation to SFP module's EEPROM over I2C interface. ++ **/ ++s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, ++ u8 eeprom_data) ++{ ++ return hw->phy.ops.write_i2c_byte(hw, byte_offset, ++ IXGBE_I2C_EEPROM_DEV_ADDR, ++ eeprom_data); ++} ++ ++/** ++ * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C ++ * @hw: pointer to hardware structure ++ * @byte_offset: byte offset to read ++ * @data: value read ++ * ++ * Performs byte read operation to SFP module's EEPROM over I2C interface at ++ * a specified deivce address. ++ **/ ++s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ++ u8 dev_addr, u8 *data) ++{ ++ s32 status = 0; ++ u32 max_retry = 10; ++ u32 retry = 0; ++ u16 swfw_mask = 0; ++ bool nack = 1; ++ ++ if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) ++ swfw_mask = IXGBE_GSSR_PHY1_SM; ++ else ++ swfw_mask = IXGBE_GSSR_PHY0_SM; ++ ++ ++ do { ++ if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) { ++ status = IXGBE_ERR_SWFW_SYNC; ++ goto read_byte_out; ++ } ++ ++ ixgbe_i2c_start(hw); ++ ++ /* Device Address and write indication */ ++ status = ixgbe_clock_out_i2c_byte(hw, dev_addr); ++ if (status != 0) ++ goto fail; ++ ++ status = ixgbe_get_i2c_ack(hw); ++ if (status != 0) ++ goto fail; ++ ++ status = ixgbe_clock_out_i2c_byte(hw, byte_offset); ++ if (status != 0) ++ goto fail; ++ ++ status = ixgbe_get_i2c_ack(hw); ++ if (status != 0) ++ goto fail; ++ ++ ixgbe_i2c_start(hw); ++ ++ /* Device Address and read indication */ ++ status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); ++ if (status != 0) ++ goto fail; ++ ++ status = ixgbe_get_i2c_ack(hw); ++ if (status != 0) ++ goto fail; ++ ++ status = ixgbe_clock_in_i2c_byte(hw, data); ++ if (status != 0) ++ goto fail; ++ ++ status = ixgbe_clock_out_i2c_bit(hw, nack); ++ if (status != 0) ++ goto fail; ++ ++ ixgbe_i2c_stop(hw); ++ break; ++ ++fail: ++ ixgbe_release_swfw_sync(hw, swfw_mask); ++ msleep(100); ++ ixgbe_i2c_bus_clear(hw); ++ retry++; ++ if (retry < max_retry) ++ hw_dbg(hw, "I2C byte read error - Retrying.\n"); ++ else ++ hw_dbg(hw, "I2C byte read error.\n"); ++ ++ } while (retry < max_retry); ++ ++ ixgbe_release_swfw_sync(hw, swfw_mask); ++ ++read_byte_out: ++ return status; ++} ++ ++/** ++ * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C ++ * @hw: pointer to hardware structure ++ * @byte_offset: byte offset to write ++ * @data: value to write ++ * ++ * Performs byte write operation to SFP module's EEPROM over I2C interface at ++ * a specified device address. ++ **/ ++s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ++ u8 dev_addr, u8 data) ++{ ++ s32 status = 0; ++ u32 max_retry = 1; ++ u32 retry = 0; ++ u16 swfw_mask = 0; ++ ++ if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) ++ swfw_mask = IXGBE_GSSR_PHY1_SM; ++ else ++ swfw_mask = IXGBE_GSSR_PHY0_SM; ++ ++ if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) { ++ status = IXGBE_ERR_SWFW_SYNC; ++ goto write_byte_out; ++ } ++ ++ do { ++ ixgbe_i2c_start(hw); ++ ++ status = ixgbe_clock_out_i2c_byte(hw, dev_addr); ++ if (status != 0) ++ goto fail; ++ ++ status = ixgbe_get_i2c_ack(hw); ++ if (status != 0) ++ goto fail; ++ ++ status = ixgbe_clock_out_i2c_byte(hw, byte_offset); ++ if (status != 0) ++ goto fail; ++ ++ status = ixgbe_get_i2c_ack(hw); ++ if (status != 0) ++ goto fail; ++ ++ status = ixgbe_clock_out_i2c_byte(hw, data); ++ if (status != 0) ++ goto fail; ++ ++ status = ixgbe_get_i2c_ack(hw); ++ if (status != 0) ++ goto fail; ++ ++ ixgbe_i2c_stop(hw); ++ break; ++ ++fail: ++ ixgbe_i2c_bus_clear(hw); ++ retry++; ++ if (retry < max_retry) ++ hw_dbg(hw, "I2C byte write error - Retrying.\n"); ++ else ++ hw_dbg(hw, "I2C byte write error.\n"); ++ } while (retry < max_retry); ++ ++ ixgbe_release_swfw_sync(hw, swfw_mask); ++ ++write_byte_out: ++ return status; ++} ++ ++/** ++ * ixgbe_i2c_start - Sets I2C start condition ++ * @hw: pointer to hardware structure ++ * ++ * Sets I2C start condition (High -> Low on SDA while SCL is High) ++ **/ ++static void ixgbe_i2c_start(struct ixgbe_hw *hw) ++{ ++ u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); ++ ++ /* Start condition must begin with data and clock high */ ++ ixgbe_set_i2c_data(hw, &i2cctl, 1); ++ ixgbe_raise_i2c_clk(hw, &i2cctl); ++ ++ /* Setup time for start condition (4.7us) */ ++ udelay(IXGBE_I2C_T_SU_STA); ++ ++ ixgbe_set_i2c_data(hw, &i2cctl, 0); ++ ++ /* Hold time for start condition (4us) */ ++ udelay(IXGBE_I2C_T_HD_STA); ++ ++ ixgbe_lower_i2c_clk(hw, &i2cctl); ++ ++ /* Minimum low period of clock is 4.7 us */ ++ udelay(IXGBE_I2C_T_LOW); ++ ++} ++ ++/** ++ * ixgbe_i2c_stop - Sets I2C stop condition ++ * @hw: pointer to hardware structure ++ * ++ * Sets I2C stop condition (Low -> High on SDA while SCL is High) ++ **/ ++static void ixgbe_i2c_stop(struct ixgbe_hw *hw) ++{ ++ u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); ++ ++ /* Stop condition must begin with data low and clock high */ ++ ixgbe_set_i2c_data(hw, &i2cctl, 0); ++ ixgbe_raise_i2c_clk(hw, &i2cctl); ++ ++ /* Setup time for stop condition (4us) */ ++ udelay(IXGBE_I2C_T_SU_STO); ++ ++ ixgbe_set_i2c_data(hw, &i2cctl, 1); ++ ++ /* bus free time between stop and start (4.7us)*/ ++ udelay(IXGBE_I2C_T_BUF); ++} ++ ++/** ++ * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C ++ * @hw: pointer to hardware structure ++ * @data: data byte to clock in ++ * ++ * Clocks in one byte data via I2C data/clock ++ **/ ++static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) ++{ ++ s32 status = 0; ++ s32 i; ++ bool bit = 0; ++ ++ for (i = 7; i >= 0; i--) { ++ status = ixgbe_clock_in_i2c_bit(hw, &bit); ++ *data |= bit<= 0; i--) { ++ bit = (data >> i) & 0x1; ++ status = ixgbe_clock_out_i2c_bit(hw, bit); ++ ++ if (status != 0) ++ break; ++ } ++ ++ /* Release SDA line (set high) */ ++ i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); ++ i2cctl |= IXGBE_I2C_DATA_OUT; ++ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); ++ ++ return status; ++} ++ ++/** ++ * ixgbe_get_i2c_ack - Polls for I2C ACK ++ * @hw: pointer to hardware structure ++ * ++ * Clocks in/out one bit via I2C data/clock ++ **/ ++static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) ++{ ++ s32 status; ++ u32 i = 0; ++ u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); ++ u32 timeout = 10; ++ bool ack = 1; ++ ++ status = ixgbe_raise_i2c_clk(hw, &i2cctl); ++ ++ if (status != 0) ++ goto out; ++ ++ /* Minimum high period of clock is 4us */ ++ udelay(IXGBE_I2C_T_HIGH); ++ ++ /* Poll for ACK. Note that ACK in I2C spec is ++ * transition from 1 to 0 */ ++ for (i = 0; i < timeout; i++) { ++ i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); ++ ack = ixgbe_get_i2c_data(&i2cctl); ++ ++ udelay(1); ++ if (ack == 0) ++ break; ++ } ++ ++ if (ack == 1) { ++ hw_dbg(hw, "I2C ack was not received.\n"); ++ status = IXGBE_ERR_I2C; ++ } ++ ++ ixgbe_lower_i2c_clk(hw, &i2cctl); ++ ++ /* Minimum low period of clock is 4.7 us */ ++ udelay(IXGBE_I2C_T_LOW); ++ ++out: ++ return status; ++} ++ ++/** ++ * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock ++ * @hw: pointer to hardware structure ++ * @data: read data value ++ * ++ * Clocks in one bit via I2C data/clock ++ **/ ++static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) ++{ ++ s32 status; ++ u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); ++ ++ status = ixgbe_raise_i2c_clk(hw, &i2cctl); ++ ++ /* Minimum high period of clock is 4us */ ++ udelay(IXGBE_I2C_T_HIGH); ++ ++ i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); ++ *data = ixgbe_get_i2c_data(&i2cctl); ++ ++ ixgbe_lower_i2c_clk(hw, &i2cctl); ++ ++ /* Minimum low period of clock is 4.7 us */ ++ udelay(IXGBE_I2C_T_LOW); ++ ++ return status; ++} ++ ++/** ++ * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock ++ * @hw: pointer to hardware structure ++ * @data: data value to write ++ * ++ * Clocks out one bit via I2C data/clock ++ **/ ++static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) ++{ ++ s32 status; ++ u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); ++ ++ status = ixgbe_set_i2c_data(hw, &i2cctl, data); ++ if (status == 0) { ++ status = ixgbe_raise_i2c_clk(hw, &i2cctl); ++ ++ /* Minimum high period of clock is 4us */ ++ udelay(IXGBE_I2C_T_HIGH); ++ ++ ixgbe_lower_i2c_clk(hw, &i2cctl); ++ ++ /* Minimum low period of clock is 4.7 us. ++ * This also takes care of the data hold time. ++ */ ++ udelay(IXGBE_I2C_T_LOW); ++ } else { ++ status = IXGBE_ERR_I2C; ++ hw_dbg(hw, "I2C data was not set to %X\n", data); ++ } ++ ++ return status; ++} ++/** ++ * ixgbe_raise_i2c_clk - Raises the I2C SCL clock ++ * @hw: pointer to hardware structure ++ * @i2cctl: Current value of I2CCTL register ++ * ++ * Raises the I2C clock line '0'->'1' ++ **/ ++static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) ++{ ++ s32 status = 0; ++ ++ *i2cctl |= IXGBE_I2C_CLK_OUT; ++ ++ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); ++ ++ /* SCL rise time (1000ns) */ ++ udelay(IXGBE_I2C_T_RISE); ++ ++ return status; ++} ++ ++/** ++ * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock ++ * @hw: pointer to hardware structure ++ * @i2cctl: Current value of I2CCTL register ++ * ++ * Lowers the I2C clock line '1'->'0' ++ **/ ++static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) ++{ ++ ++ *i2cctl &= ~IXGBE_I2C_CLK_OUT; ++ ++ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); ++ ++ /* SCL fall time (300ns) */ ++ udelay(IXGBE_I2C_T_FALL); ++} ++ ++/** ++ * ixgbe_set_i2c_data - Sets the I2C data bit ++ * @hw: pointer to hardware structure ++ * @i2cctl: Current value of I2CCTL register ++ * @data: I2C data value (0 or 1) to set ++ * ++ * Sets the I2C data bit ++ **/ ++static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) ++{ ++ s32 status = 0; ++ ++ if (data) ++ *i2cctl |= IXGBE_I2C_DATA_OUT; ++ else ++ *i2cctl &= ~IXGBE_I2C_DATA_OUT; ++ ++ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); ++ ++ /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ ++ udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); ++ ++ /* Verify data was set correctly */ ++ *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); ++ if (data != ixgbe_get_i2c_data(i2cctl)) { ++ status = IXGBE_ERR_I2C; ++ hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); ++ } ++ ++ return status; ++} ++ ++/** ++ * ixgbe_get_i2c_data - Reads the I2C SDA data bit ++ * @hw: pointer to hardware structure ++ * @i2cctl: Current value of I2CCTL register ++ * ++ * Returns the I2C data bit value ++ **/ ++static bool ixgbe_get_i2c_data(u32 *i2cctl) ++{ ++ bool data; ++ ++ if (*i2cctl & IXGBE_I2C_DATA_IN) ++ data = 1; ++ else ++ data = 0; ++ ++ return data; ++} ++ ++/** ++ * ixgbe_i2c_bus_clear - Clears the I2C bus ++ * @hw: pointer to hardware structure ++ * ++ * Clears the I2C bus by sending nine clock pulses. ++ * Used when data line is stuck low. ++ **/ ++void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) ++{ ++ u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); ++ u32 i; ++ ++ ixgbe_i2c_start(hw); ++ ++ ixgbe_set_i2c_data(hw, &i2cctl, 1); ++ ++ for (i = 0; i < 9; i++) { ++ ixgbe_raise_i2c_clk(hw, &i2cctl); ++ ++ /* Min high period of clock is 4us */ ++ udelay(IXGBE_I2C_T_HIGH); ++ ++ ixgbe_lower_i2c_clk(hw, &i2cctl); ++ ++ /* Min low period of clock is 4.7us*/ ++ udelay(IXGBE_I2C_T_LOW); ++ } ++ ++ ixgbe_i2c_start(hw); ++ ++ /* Put the i2c bus back to default state */ ++ ixgbe_i2c_stop(hw); ++} +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_phy.h +--- a/drivers/net/ixgbe/ixgbe_phy.h Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe_phy.h Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -39,11 +39,12 @@ + #define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27 + #define IXGBE_SFF_1GBE_COMP_CODES 0x6 + #define IXGBE_SFF_10GBE_COMP_CODES 0x3 +-#define IXGBE_SFF_TRANSMISSION_MEDIA 0x9 ++#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8 + + /* Bitmasks */ +-#define IXGBE_SFF_TWIN_AX_CAPABLE 0x80 ++#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 + #define IXGBE_SFF_1GBASESX_CAPABLE 0x1 ++#define IXGBE_SFF_1GBASELX_CAPABLE 0x2 + #define IXGBE_SFF_10GBASESR_CAPABLE 0x10 + #define IXGBE_SFF_10GBASELR_CAPABLE 0x20 + #define IXGBE_I2C_EEPROM_READ_MASK 0x100 +@@ -54,14 +55,15 @@ + #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 + + /* Bit-shift macros */ +-#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 12 +-#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 8 +-#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 4 ++#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24 ++#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16 ++#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8 + + /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ + #define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 + #define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 + #define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 ++#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100 + + /* I2C SDA and SCL timing parameters for standard mode */ + #define IXGBE_I2C_T_HD_STA 4 +@@ -77,6 +79,9 @@ + + + s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); ++bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); ++enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); ++s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); + s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); + s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); + s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, +@@ -88,18 +93,31 @@ + ixgbe_link_speed speed, + bool autoneg, + bool autoneg_wait_to_complete); ++s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, ++ ixgbe_link_speed *speed, ++ bool *autoneg); + + /* PHY specific */ + s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, + ixgbe_link_speed *speed, + bool *link_up); ++s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw); + s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, + u16 *firmware_version); ++s32 ixgbe_get_phy_firmware_version_aq(struct ixgbe_hw *hw, ++ u16 *firmware_version); + +-/* PHY specific */ + s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); + s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); + s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, +- u16 *list_offset, +- u16 *data_offset); ++ u16 *list_offset, ++ u16 *data_offset); ++s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ++ u8 dev_addr, u8 *data); ++s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ++ u8 dev_addr, u8 data); ++s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, ++ u8 *eeprom_data); ++s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, ++ u8 eeprom_data); + #endif /* _IXGBE_PHY_H_ */ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_sysfs.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/ixgbe/ixgbe_sysfs.c Wed Aug 05 11:05:50 2009 +0100 +@@ -0,0 +1,29 @@ ++/******************************************************************************* ++ ++ Intel 10 Gigabit PCI Express Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "ixgbe.h" ++ +diff -r 1efe16c57de3 drivers/net/ixgbe/ixgbe_type.h +--- a/drivers/net/ixgbe/ixgbe_type.h Wed Aug 05 11:03:48 2009 +0100 ++++ b/drivers/net/ixgbe/ixgbe_type.h Wed Aug 05 11:05:50 2009 +0100 +@@ -1,7 +1,7 @@ + /******************************************************************************* + + Intel 10 Gigabit PCI Express Linux driver +- Copyright(c) 1999 - 2008 Intel Corporation. ++ Copyright(c) 1999 - 2009 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, +@@ -28,21 +28,28 @@ + #ifndef _IXGBE_TYPE_H_ + #define _IXGBE_TYPE_H_ + +-#include ++#include "ixgbe_osdep.h" ++ + + /* Vendor ID */ + #define IXGBE_INTEL_VENDOR_ID 0x8086 + + /* Device IDs */ ++#define IXGBE_DEV_ID_82598 0x10B6 ++#define IXGBE_DEV_ID_82598_BX 0x1508 + #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 + #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 ++#define IXGBE_DEV_ID_82598AT 0x10C8 ++#define IXGBE_DEV_ID_82598AT2 0x150B + #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB +-#define IXGBE_DEV_ID_82598AT 0x10C8 + #define IXGBE_DEV_ID_82598EB_CX4 0x10DD + #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC + #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 + #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 + #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 ++#define IXGBE_DEV_ID_82599_KX4 0x10F7 ++#define IXGBE_DEV_ID_82599_SFP 0x10FB ++#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC + + /* General Registers */ + #define IXGBE_CTRL 0x00000 +@@ -50,9 +57,12 @@ + #define IXGBE_CTRL_EXT 0x00018 + #define IXGBE_ESDP 0x00020 + #define IXGBE_EODSDP 0x00028 ++#define IXGBE_I2CCTL 0x00028 + #define IXGBE_LEDCTL 0x00200 + #define IXGBE_FRTIMER 0x00048 + #define IXGBE_TCPTIMER 0x0004C ++#define IXGBE_CORESPARE 0x00600 ++#define IXGBE_EXVET 0x05078 + + /* NVM Registers */ + #define IXGBE_EEC 0x10010 +@@ -66,6 +76,19 @@ + #define IXGBE_FLOP 0x1013C + #define IXGBE_GRC 0x10200 + ++/* General Receive Control */ ++#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ ++#define IXGBE_GRC_APME 0x00000002 /* Advanced Power Management Enable */ ++ ++#define IXGBE_VPDDIAG0 0x10204 ++#define IXGBE_VPDDIAG1 0x10208 ++ ++/* I2CCTL Bit Masks */ ++#define IXGBE_I2C_CLK_IN 0x00000001 ++#define IXGBE_I2C_CLK_OUT 0x00000002 ++#define IXGBE_I2C_DATA_IN 0x00000004 ++#define IXGBE_I2C_DATA_OUT 0x00000008 ++ + /* Interrupt Registers */ + #define IXGBE_EICR 0x00800 + #define IXGBE_EICS 0x00808 +@@ -73,28 +96,66 @@ + #define IXGBE_EIMC 0x00888 + #define IXGBE_EIAC 0x00810 + #define IXGBE_EIAM 0x00890 +-#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : (0x012300 + ((_i) * 4))) ++#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) ++#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) ++#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) ++#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) ++/* 82599 EITR is only 12 bits, with the lower 3 always zero */ ++/* ++ * 82598 EITR is 16 bits but set the limits based on the max ++ * supported by all ixgbe hardware ++ */ ++#define IXGBE_MAX_INT_RATE 488281 ++#define IXGBE_MIN_INT_RATE 956 ++#define IXGBE_MAX_EITR 0x00000FF8 ++#define IXGBE_MIN_EITR 8 ++#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ ++ (0x012300 + (((_i) - 24) * 4))) ++#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 ++#define IXGBE_EITR_LLI_MOD 0x00008000 ++#define IXGBE_EITR_CNT_WDIS 0x80000000 + #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ ++#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ ++#define IXGBE_EITRSEL 0x00894 + #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ + #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ + #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) + #define IXGBE_GPIE 0x00898 + + /* Flow Control Registers */ ++#define IXGBE_FCADBUL 0x03210 ++#define IXGBE_FCADBUH 0x03214 ++#define IXGBE_FCAMACL 0x04328 ++#define IXGBE_FCAMACH 0x0432C ++#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ ++#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ + #define IXGBE_PFCTOP 0x03008 + #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ + #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ + #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ + #define IXGBE_FCRTV 0x032A0 ++#define IXGBE_FCCFG 0x03D00 + #define IXGBE_TFCS 0x0CE00 + + /* Receive DMA Registers */ +-#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : (0x0D000 + ((_i - 64) * 0x40))) +-#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : (0x0D004 + ((_i - 64) * 0x40))) +-#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : (0x0D008 + ((_i - 64) * 0x40))) +-#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : (0x0D010 + ((_i - 64) * 0x40))) +-#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : (0x0D018 + ((_i - 64) * 0x40))) +-#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : (0x0D028 + ((_i - 64) * 0x40))) ++#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ ++ (0x0D000 + ((_i - 64) * 0x40))) ++#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ ++ (0x0D004 + ((_i - 64) * 0x40))) ++#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ ++ (0x0D008 + ((_i - 64) * 0x40))) ++#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ ++ (0x0D010 + ((_i - 64) * 0x40))) ++#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ ++ (0x0D018 + ((_i - 64) * 0x40))) ++#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ ++ (0x0D028 + ((_i - 64) * 0x40))) ++#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ ++ (0x0D02C + ((_i - 64) * 0x40))) ++#define IXGBE_RSCDBU 0x03028 ++#define IXGBE_RDDCC 0x02F20 ++#define IXGBE_RXMEMWRAP 0x03190 ++#define IXGBE_STARCTRL 0x03024 + /* + * Split and Replication Receive Control Registers + * 00-15 : 0x02100 + n*4 +@@ -114,6 +175,7 @@ + (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ + (0x0D00C + ((_i - 64) * 0x40)))) + #define IXGBE_RDRXCTL 0x02F00 ++#define IXGBE_RDRXCTL_RSC_PUSH 0x80 + #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) + /* 8 of these 0x03C00 - 0x03C1C */ + #define IXGBE_RXCTRL 0x03000 +@@ -127,10 +189,15 @@ + #define IXGBE_DRECCCTL_DISABLE 0 + /* Multicast Table Array - 128 entries */ + #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) +-#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x0A200 + ((_i) * 8))) +-#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x0A204 + ((_i) * 8))) ++#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ ++ (0x0A200 + ((_i) * 8))) ++#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ ++ (0x0A204 + ((_i) * 8))) ++#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) ++#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) + /* Packet split receive type */ +-#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : (0x0EA00 + ((_i) * 4))) ++#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ ++ (0x0EA00 + ((_i) * 4))) + /* array of 4096 1-bit vlan filters */ + #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) + /*array of 4096 4-bit vlan vmdq indices */ +@@ -139,6 +206,28 @@ + #define IXGBE_VLNCTRL 0x05088 + #define IXGBE_MCSTCTRL 0x05090 + #define IXGBE_MRQC 0x05818 ++#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ ++#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ ++#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ ++#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ ++#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ ++#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ ++#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */ ++#define IXGBE_RQTC 0x0EC70 ++#define IXGBE_MTQC 0x08120 ++#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */ ++#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */ ++#define IXGBE_VT_CTL 0x051B0 ++#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) ++#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) ++#define IXGBE_QDE 0x2F04 ++#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */ ++#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) ++#define IXGBE_VMRCTL(_i) (0x0F600 + ((_i) * 4)) ++#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) ++#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) ++#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ ++#define IXGBE_LLITHRESH 0x0EC90 + #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ + #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ + #define IXGBE_IMIRVP 0x05AC0 +@@ -146,6 +235,33 @@ + #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ + #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ + ++/* Flow Director registers */ ++#define IXGBE_FDIRCTRL 0x0EE00 ++#define IXGBE_FDIRHKEY 0x0EE68 ++#define IXGBE_FDIRSKEY 0x0EE6C ++#define IXGBE_FDIRDIP4M 0x0EE3C ++#define IXGBE_FDIRSIP4M 0x0EE40 ++#define IXGBE_FDIRTCPM 0x0EE44 ++#define IXGBE_FDIRUDPM 0x0EE48 ++#define IXGBE_FDIRIP6M 0x0EE74 ++#define IXGBE_FDIRM 0x0EE70 ++ ++/* Flow Director Stats registers */ ++#define IXGBE_FDIRFREE 0x0EE38 ++#define IXGBE_FDIRLEN 0x0EE4C ++#define IXGBE_FDIRUSTAT 0x0EE50 ++#define IXGBE_FDIRFSTAT 0x0EE54 ++#define IXGBE_FDIRMATCH 0x0EE58 ++#define IXGBE_FDIRMISS 0x0EE5C ++ ++/* Flow Director Programming registers */ ++#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */ ++#define IXGBE_FDIRIPSA 0x0EE18 ++#define IXGBE_FDIRIPDA 0x0EE1C ++#define IXGBE_FDIRPORT 0x0EE20 ++#define IXGBE_FDIRVLAN 0x0EE24 ++#define IXGBE_FDIRHASH 0x0EE28 ++#define IXGBE_FDIRCMD 0x0EE2C + + /* Transmit DMA registers */ + #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/ +@@ -158,7 +274,23 @@ + #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) + #define IXGBE_DTXCTL 0x07E00 + ++#define IXGBE_DMATXCTL 0x04A80 ++#define IXGBE_PFDTXGSWC 0x08220 ++#define IXGBE_DTXMXSZRQ 0x08100 ++#define IXGBE_DTXTCPFLGL 0x04A88 ++#define IXGBE_DTXTCPFLGH 0x04A8C ++#define IXGBE_LBDRPEN 0x0CA00 ++#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */ ++ ++#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ ++#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ ++#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ ++#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ ++ ++#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ + #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */ ++/* Tx DCA Control register : 128 of these (0-127) */ ++#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) + #define IXGBE_TIPG 0x0CB00 + #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ + #define IXGBE_MNGTXMAP 0x0CD10 +@@ -175,9 +307,69 @@ + + #define IXGBE_WUPL 0x05900 + #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ +-#define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */ ++#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */ ++#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host ++ * Filter Table */ + +-/* Music registers */ ++#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 ++#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 ++ ++/* Each Flexible Filter is at most 128 (0x80) bytes in length */ ++#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 ++#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ ++#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ ++ ++/* Definitions for power management and wakeup registers */ ++/* Wake Up Control */ ++#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ ++#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ ++#define IXGBE_WUC_ADVD3WUC 0x00000010 /* D3Cold wake up cap. enable*/ ++ ++/* Wake Up Filter Control */ ++#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ ++#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ ++#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ ++#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ ++#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ ++#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ ++#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ ++#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ ++#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */ ++ ++#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ ++#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ ++#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ ++#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ ++#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ ++#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ ++#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ ++#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ ++#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */ ++#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all 6 wakeup filters*/ ++#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ ++ ++/* Wake Up Status */ ++#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC ++#define IXGBE_WUS_MAG IXGBE_WUFC_MAG ++#define IXGBE_WUS_EX IXGBE_WUFC_EX ++#define IXGBE_WUS_MC IXGBE_WUFC_MC ++#define IXGBE_WUS_BC IXGBE_WUFC_BC ++#define IXGBE_WUS_ARP IXGBE_WUFC_ARP ++#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4 ++#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6 ++#define IXGBE_WUS_MNG IXGBE_WUFC_MNG ++#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0 ++#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1 ++#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2 ++#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3 ++#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4 ++#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5 ++#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS ++ ++/* Wake Up Packet Length */ ++#define IXGBE_WUPL_LENGTH_MASK 0xFFFF ++ ++/* DCB registers */ + #define IXGBE_RMCS 0x03D00 + #define IXGBE_DPMCS 0x07F40 + #define IXGBE_PDPMCS 0x0CD00 +@@ -190,6 +382,181 @@ + #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ + + ++/* Security Control Registers */ ++#define IXGBE_SECTXCTRL 0x08800 ++#define IXGBE_SECTXSTAT 0x08804 ++#define IXGBE_SECTXBUFFAF 0x08808 ++#define IXGBE_SECTXMINIFG 0x08810 ++#define IXGBE_SECTXSTAT 0x08804 ++#define IXGBE_SECRXCTRL 0x08D00 ++#define IXGBE_SECRXSTAT 0x08D04 ++ ++/* Security Bit Fields and Masks */ ++#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001 ++#define IXGBE_SECTXCTRL_TX_DIS 0x00000002 ++#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004 ++ ++#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001 ++#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002 ++ ++#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001 ++#define IXGBE_SECRXCTRL_RX_DIS 0x00000002 ++ ++#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001 ++#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002 ++ ++/* LinkSec (MacSec) Registers */ ++#define IXGBE_LSECTXCAP 0x08A00 ++#define IXGBE_LSECRXCAP 0x08F00 ++#define IXGBE_LSECTXCTRL 0x08A04 ++#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ ++#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ ++#define IXGBE_LSECTXSA 0x08A10 ++#define IXGBE_LSECTXPN0 0x08A14 ++#define IXGBE_LSECTXPN1 0x08A18 ++#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ ++#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ ++#define IXGBE_LSECRXCTRL 0x08F04 ++#define IXGBE_LSECRXSCL 0x08F08 ++#define IXGBE_LSECRXSCH 0x08F0C ++#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ ++#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ ++#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) ++#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */ ++#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */ ++#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */ ++#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */ ++#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */ ++#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */ ++#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */ ++#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */ ++#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */ ++#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */ ++#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */ ++#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */ ++#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */ ++#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */ ++#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ ++#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ ++#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ ++#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */ ++#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */ ++ ++/* LinkSec (MacSec) Bit Fields and Masks */ ++#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000 ++#define IXGBE_LSECTXCAP_SUM_SHIFT 16 ++#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000 ++#define IXGBE_LSECRXCAP_SUM_SHIFT 16 ++ ++#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003 ++#define IXGBE_LSECTXCTRL_DISABLE 0x0 ++#define IXGBE_LSECTXCTRL_AUTH 0x1 ++#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2 ++#define IXGBE_LSECTXCTRL_AISCI 0x00000020 ++#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 ++#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8 ++ ++#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C ++#define IXGBE_LSECRXCTRL_EN_SHIFT 2 ++#define IXGBE_LSECRXCTRL_DISABLE 0x0 ++#define IXGBE_LSECRXCTRL_CHECK 0x1 ++#define IXGBE_LSECRXCTRL_STRICT 0x2 ++#define IXGBE_LSECRXCTRL_DROP 0x3 ++#define IXGBE_LSECRXCTRL_PLSH 0x00000040 ++#define IXGBE_LSECRXCTRL_RP 0x00000080 ++#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 ++ ++/* IpSec Registers */ ++#define IXGBE_IPSTXIDX 0x08900 ++#define IXGBE_IPSTXSALT 0x08904 ++#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ ++#define IXGBE_IPSRXIDX 0x08E00 ++#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ ++#define IXGBE_IPSRXSPI 0x08E14 ++#define IXGBE_IPSRXIPIDX 0x08E18 ++#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ ++#define IXGBE_IPSRXSALT 0x08E2C ++#define IXGBE_IPSRXMOD 0x08E30 ++ ++#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 ++ ++/* DCB registers */ ++#define IXGBE_RTRPCS 0x02430 ++#define IXGBE_RTTDCS 0x04900 ++#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ ++#define IXGBE_RTTPCS 0x0CD00 ++#define IXGBE_RTRUP2TC 0x03020 ++#define IXGBE_RTTUP2TC 0x0C800 ++#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */ ++#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */ ++#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */ ++#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */ ++#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ ++#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ ++#define IXGBE_RTTDQSEL 0x04904 ++#define IXGBE_RTTDT1C 0x04908 ++#define IXGBE_RTTDT1S 0x0490C ++#define IXGBE_RTTDTECC 0x04990 ++#define IXGBE_RTTDTECC_NO_BCN 0x00000100 ++ ++#define IXGBE_RTTBCNRC 0x04984 ++ ++ ++/* FCoE DMA Context Registers */ ++#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ ++#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ ++#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ ++#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ ++#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */ ++#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4)) ++#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ ++#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */ ++#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */ ++#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ ++#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ ++#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 ++#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 ++#define IXGBE_FCBUFF_OFFSET_SHIFT 16 ++#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */ ++#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */ ++#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ ++#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ ++#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 ++/* FCoE SOF/EOF */ ++#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */ ++#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */ ++#define IXGBE_REOFF 0x05158 /* Rx FC EOF */ ++#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */ ++/* FCoE Filter Context Registers */ ++#define IXGBE_FCFLT 0x05108 /* FC FLT Context */ ++#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ ++#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ ++#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */ ++#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */ ++#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ ++#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ ++#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */ ++#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */ ++#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */ ++/* FCoE Receive Control */ ++#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ ++#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */ ++#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */ ++#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */ ++#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */ ++#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */ ++#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */ ++#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */ ++#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */ ++#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ ++#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 ++/* FCoE Redirection */ ++#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */ ++#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */ ++#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ ++#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */ ++#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */ ++#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */ + + /* Stats registers */ + #define IXGBE_CRCERRS 0x04000 +@@ -204,6 +571,11 @@ + #define IXGBE_LXONRXC 0x0CF60 + #define IXGBE_LXOFFTXC 0x03F68 + #define IXGBE_LXOFFRXC 0x0CF68 ++#define IXGBE_LXONRXCNT 0x041A4 ++#define IXGBE_LXOFFRXCNT 0x041A8 ++#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */ ++#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */ ++#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */ + #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ + #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ + #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ +@@ -243,14 +615,29 @@ + #define IXGBE_MPTC 0x040F0 + #define IXGBE_BPTC 0x040F4 + #define IXGBE_XEC 0x04120 ++#define IXGBE_SSVPC 0x08780 + +-#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */ +-#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : (0x08600 + ((_i) * 4))) ++#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) ++#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ ++ (0x08600 + ((_i) * 4))) ++#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) + + #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ + #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ + #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ + #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ ++#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ ++#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ ++#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ ++#define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */ ++#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ ++#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ ++#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ ++#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ ++#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ ++#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ ++#define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */ ++#define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */ + + /* Management */ + #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ +@@ -263,6 +650,9 @@ + #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ + #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ + #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ ++#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ ++#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ ++#define IXGBE_LSWFW 0x15014 + + /* ARC Subsystem registers */ + #define IXGBE_HICR 0x15F00 +@@ -295,16 +685,63 @@ + #define IXGBE_DCA_ID 0x11070 + #define IXGBE_DCA_CTRL 0x11074 + ++/* PCI-E registers 82599-Specific */ ++#define IXGBE_GCR_EXT 0x11050 ++#define IXGBE_GSCL_5_82599 0x11030 ++#define IXGBE_GSCL_6_82599 0x11034 ++#define IXGBE_GSCL_7_82599 0x11038 ++#define IXGBE_GSCL_8_82599 0x1103C ++#define IXGBE_PHYADR_82599 0x11040 ++#define IXGBE_PHYDAT_82599 0x11044 ++#define IXGBE_PHYCTL_82599 0x11048 ++#define IXGBE_PBACLR_82599 0x11068 ++#define IXGBE_CIAA_82599 0x11088 ++#define IXGBE_CIAD_82599 0x1108C ++#define IXGBE_INTRPT_CSR_82599 0x110B0 ++#define IXGBE_INTRPT_MASK_82599 0x110B8 ++#define IXGBE_CDQ_MBR_82599 0x110B4 ++#define IXGBE_MISC_REG_82599 0x110F0 ++#define IXGBE_ECC_CTRL_0_82599 0x11100 ++#define IXGBE_ECC_CTRL_1_82599 0x11104 ++#define IXGBE_ECC_STATUS_82599 0x110E0 ++#define IXGBE_BAR_CTRL_82599 0x110F4 ++ ++/* PCI Express Control */ ++#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 ++#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 ++#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 ++#define IXGBE_GCR_CAP_VER2 0x00040000 ++ ++/* Time Sync Registers */ ++#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ ++#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ ++#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */ ++#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */ ++#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */ ++#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */ ++#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */ ++#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */ ++#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */ ++#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */ ++#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */ ++#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */ ++#define IXGBE_RXUDP 0x08C1C /* Time Sync Rx UDP Port - RW */ ++ + /* Diagnostic Registers */ + #define IXGBE_RDSTATCTL 0x02C20 + #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ + #define IXGBE_RDHMPN 0x02F08 + #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) + #define IXGBE_RDPROBE 0x02F20 ++#define IXGBE_RDMAM 0x02F30 ++#define IXGBE_RDMAD 0x02F34 + #define IXGBE_TDSTATCTL 0x07C20 + #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ + #define IXGBE_TDHMPN 0x07F08 ++#define IXGBE_TDHMPN2 0x082FC ++#define IXGBE_TXDESCIC 0x082CC + #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) ++#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4)) + #define IXGBE_TDPROBE 0x07F20 + #define IXGBE_TXBUFCTRL 0x0C600 + #define IXGBE_TXBUFDATA0 0x0C610 +@@ -332,6 +769,20 @@ + #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ + #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ + #define IXGBE_PCIEECCCTL 0x1106C ++#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ ++#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ ++#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ ++#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ ++#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ ++#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ ++#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ ++#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ ++#define IXGBE_PCIEECCCTL0 0x11100 ++#define IXGBE_PCIEECCCTL1 0x11104 ++#define IXGBE_RXDBUECC 0x03F70 ++#define IXGBE_TXDBUECC 0x0CF70 ++#define IXGBE_RXDBUEST 0x03F74 ++#define IXGBE_TXDBUEST 0x0CF74 + #define IXGBE_PBTXECC 0x0C300 + #define IXGBE_PBRXECC 0x03300 + #define IXGBE_GHECCR 0x110B0 +@@ -357,24 +808,74 @@ + #define IXGBE_MSRWD 0x04260 + #define IXGBE_MLADD 0x04264 + #define IXGBE_MHADD 0x04268 ++#define IXGBE_MAXFRS 0x04268 + #define IXGBE_TREG 0x0426C + #define IXGBE_PCSS1 0x04288 + #define IXGBE_PCSS2 0x0428C + #define IXGBE_XPCSS 0x04290 ++#define IXGBE_MFLCN 0x04294 + #define IXGBE_SERDESC 0x04298 + #define IXGBE_MACS 0x0429C + #define IXGBE_AUTOC 0x042A0 + #define IXGBE_LINKS 0x042A4 ++#define IXGBE_LINKS2 0x04324 + #define IXGBE_AUTOC2 0x042A8 + #define IXGBE_AUTOC3 0x042AC + #define IXGBE_ANLP1 0x042B0 + #define IXGBE_ANLP2 0x042B4 + #define IXGBE_ATLASCTL 0x04800 ++#define IXGBE_MMNGC 0x042D0 ++#define IXGBE_ANLPNP1 0x042D4 ++#define IXGBE_ANLPNP2 0x042D8 ++#define IXGBE_KRPCSFC 0x042E0 ++#define IXGBE_KRPCSS 0x042E4 ++#define IXGBE_FECS1 0x042E8 ++#define IXGBE_FECS2 0x042EC ++#define IXGBE_SMADARCTL 0x14F10 ++#define IXGBE_MPVC 0x04318 ++#define IXGBE_SGMIIC 0x04314 ++ ++/* Omer CORECTL */ ++#define IXGBE_CORECTL 0x014F00 ++/* BARCTRL */ ++#define IXGBE_BARCTRL 0x110F4 ++#define IXGBE_BARCTRL_FLSIZE 0x0700 ++#define IXGBE_BARCTRL_CSRSIZE 0x2000 ++ ++/* RSCCTL Bit Masks */ ++#define IXGBE_RSCCTL_RSCEN 0x01 ++#define IXGBE_RSCCTL_MAXDESC_1 0x00 ++#define IXGBE_RSCCTL_MAXDESC_4 0x04 ++#define IXGBE_RSCCTL_MAXDESC_8 0x08 ++#define IXGBE_RSCCTL_MAXDESC_16 0x0C ++ ++/* RSCDBU Bit Masks */ ++#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F ++#define IXGBE_RSCDBU_RSCACKDIS 0x00000080 + + /* RDRXCTL Bit Masks */ + #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */ ++#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ + #define IXGBE_RDRXCTL_MVMEN 0x00000020 + #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ ++#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ ++#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ ++#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */ ++ ++/* RQTC Bit Masks and Shifts */ ++#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) ++#define IXGBE_RQTC_TC0_MASK (0x7 << 0) ++#define IXGBE_RQTC_TC1_MASK (0x7 << 4) ++#define IXGBE_RQTC_TC2_MASK (0x7 << 8) ++#define IXGBE_RQTC_TC3_MASK (0x7 << 12) ++#define IXGBE_RQTC_TC4_MASK (0x7 << 16) ++#define IXGBE_RQTC_TC5_MASK (0x7 << 20) ++#define IXGBE_RQTC_TC6_MASK (0x7 << 24) ++#define IXGBE_RQTC_TC7_MASK (0x7 << 28) ++ ++/* PSRTYPE.RQPL Bit masks and shift */ ++#define IXGBE_PSRTYPE_RQPL_MASK 0x7 ++#define IXGBE_PSRTYPE_RQPL_SHIFT 29 + + /* CTRL Bit Masks */ + #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ +@@ -389,6 +890,7 @@ + #define IXGBE_MHADD_MFS_SHIFT 16 + + /* Extended Device Control */ ++#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */ + #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ + #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ + #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ +@@ -401,11 +903,18 @@ + #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ + + #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ ++#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ ++#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ + #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ + #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ + #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ ++#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */ ++#define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */ ++#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */ + + #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ ++#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ ++#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ + #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ + #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ + #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ +@@ -449,6 +958,8 @@ + #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 + #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 + ++/* Omer bit masks */ ++#define IXGBE_CORECTL_WRITE_CMD 0x00010000 + + /* Device Type definitions for new protocol MDIO commands */ + #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 +@@ -476,18 +987,30 @@ + #define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ + #define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ + #define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ ++#define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */ ++#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */ ++#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */ ++#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */ ++#define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */ + +-#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Address Reg */ ++#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ + #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ + #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ + + /* MII clause 22/28 definitions */ + #define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 + +-#define IXGBE_MII_SPEED_SELECTION_REG 0x10 +-#define IXGBE_MII_RESTART 0x200 +-#define IXGBE_MII_AUTONEG_COMPLETE 0x20 +-#define IXGBE_MII_AUTONEG_REG 0x0 ++#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */ ++#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ ++#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ ++#define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */ ++#define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/ ++#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ ++#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ ++#define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */ ++#define IXGBE_MII_RESTART 0x200 ++#define IXGBE_MII_AUTONEG_COMPLETE 0x20 ++#define IXGBE_MII_AUTONEG_REG 0x0 + + #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 + #define IXGBE_MAX_PHY_ADDR 32 +@@ -495,11 +1018,14 @@ + /* PHY IDs*/ + #define TN1010_PHY_ID 0x00A19410 + #define TNX_FW_REV 0xB ++#define AQ1002_PHY_ID 0x03A1B420 ++#define AQ_FW_REV 0x20 + #define QT2022_PHY_ID 0x0043A400 + #define ATH_PHY_ID 0x03429050 + + /* PHY Types */ + #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 ++ + /* Special PHY Init Routine */ + #define IXGBE_PHY_INIT_OFFSET_NL 0x002B + #define IXGBE_PHY_INIT_END_NL 0xFFFF +@@ -515,11 +1041,17 @@ + /* General purpose Interrupt Enable */ + #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ + #define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ ++#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */ + #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ + #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ + #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ + #define IXGBE_GPIE_EIAME 0x40000000 + #define IXGBE_GPIE_PBA_SUPPORT 0x80000000 ++#define IXGBE_GPIE_RSC_DELAY_SHIFT 11 ++#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */ ++#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */ ++#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */ ++#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */ + + /* Transmit Flow Control status */ + #define IXGBE_TFCS_TXOFF 0x00000001 +@@ -560,6 +1092,25 @@ + #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 + #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 + ++/* VT_CTL bitmasks */ ++#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ ++#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ ++#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ ++#define IXGBE_VT_CTL_POOL_SHIFT 7 ++#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) ++ ++/* VMOLR bitmasks */ ++#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ ++#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ ++#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ ++#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ ++#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ ++ ++/* VFRE bitmask */ ++#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF ++ ++#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ ++ + /* RDHMPN and TDHMPN bitmasks */ + #define IXGBE_RDHMPN_RDICADDR 0x007FF800 + #define IXGBE_RDHMPN_RDICRDREQ 0x00800000 +@@ -568,13 +1119,48 @@ + #define IXGBE_TDHMPN_TDICRDREQ 0x00800000 + #define IXGBE_TDHMPN_TDICADDR_SHIFT 11 + ++#define IXGBE_RDMAM_MEM_SEL_SHIFT 13 ++#define IXGBE_RDMAM_DWORD_SHIFT 9 ++#define IXGBE_RDMAM_DESC_COMP_FIFO 1 ++#define IXGBE_RDMAM_DFC_CMD_FIFO 2 ++#define IXGBE_RDMAM_RSC_HEADER_ADDR 3 ++#define IXGBE_RDMAM_TCN_STATUS_RAM 4 ++#define IXGBE_RDMAM_WB_COLL_FIFO 5 ++#define IXGBE_RDMAM_QSC_CNT_RAM 6 ++#define IXGBE_RDMAM_QSC_FCOE_RAM 7 ++#define IXGBE_RDMAM_QSC_QUEUE_CNT 8 ++#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA ++#define IXGBE_RDMAM_QSC_RSC_RAM 0xB ++#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135 ++#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4 ++#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48 ++#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7 ++#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32 ++#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4 ++#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256 ++#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9 ++#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8 ++#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4 ++#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64 ++#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4 ++#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512 ++#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5 ++#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32 ++#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4 ++#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128 ++#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8 ++#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32 ++#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8 ++ ++#define IXGBE_TXDESCIC_READY 0x80000000 ++ + /* Receive Checksum Control */ + #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ + #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ + + /* FCRTL Bit Masks */ +-#define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */ +-#define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */ ++#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */ ++#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */ + + /* PAP bit masks*/ + #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ +@@ -584,19 +1170,29 @@ + /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ + #define IXGBE_RMCS_RAC 0x00000004 + #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ +-#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */ +-#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */ ++#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ ++#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ + #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ + ++/* FCCFG Bit Masks */ ++#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */ ++#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */ + + /* Interrupt register bitmasks */ + + /* Extended Interrupt Cause Read */ + #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ ++#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */ ++#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */ ++#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */ ++#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */ + #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ ++#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */ + #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ + #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ + #define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ ++#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */ ++#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */ + #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ + #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ + #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ +@@ -604,10 +1200,16 @@ + + /* Extended Interrupt Cause Set */ + #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ ++#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ ++#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */ ++#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */ ++#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ + #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ + #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ + #define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ + #define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ ++#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ ++#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */ + #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ + #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ + #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ +@@ -615,10 +1217,16 @@ + + /* Extended Interrupt Mask Set */ + #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ ++#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ ++#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ ++#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */ ++#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ + #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ + #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ + #define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ + #define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ ++#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ ++#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */ + #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ + #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ + #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ +@@ -626,10 +1234,16 @@ + + /* Extended Interrupt Mask Clear */ + #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ ++#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ ++#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ ++#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */ ++#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ + #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ + #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ + #define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ + #define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ ++#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ ++#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */ + #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ + #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ + #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ +@@ -652,12 +1266,45 @@ + #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ + #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ + #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ ++#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */ ++#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */ ++#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */ ++#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */ ++#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ ++#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ ++#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ ++#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */ ++#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ ++#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ ++#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ ++#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */ ++#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */ ++ ++#define IXGBE_MAX_FTQF_FILTERS 128 ++#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003 ++#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000 ++#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001 ++#define IXGBE_FTQF_PROTOCOL_SCTP 2 ++#define IXGBE_FTQF_PRIORITY_MASK 0x00000007 ++#define IXGBE_FTQF_PRIORITY_SHIFT 2 ++#define IXGBE_FTQF_POOL_MASK 0x0000003F ++#define IXGBE_FTQF_POOL_SHIFT 8 ++#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F ++#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25 ++#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E ++#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D ++#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B ++#define IXGBE_FTQF_DEST_PORT_MASK 0x17 ++#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F ++#define IXGBE_FTQF_POOL_MASK_EN 0x40000000 ++#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 + + /* Interrupt clear mask */ + #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF + + /* Interrupt Vector Allocation Registers */ + #define IXGBE_IVAR_REG_NUM 25 ++#define IXGBE_IVAR_REG_NUM_82599 64 + #define IXGBE_IVAR_TXRX_ENTRY 96 + #define IXGBE_IVAR_RX_ENTRY 64 + #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) +@@ -671,6 +1318,32 @@ + + #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ + ++/* ETYPE Queue Filter/Select Bit Masks */ ++#define IXGBE_MAX_ETQF_FILTERS 8 ++#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */ ++#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */ ++#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ ++#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ ++#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */ ++ ++#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ ++#define IXGBE_ETQS_RX_QUEUE_SHIFT 16 ++#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */ ++#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */ ++ ++/* ++ * ETQF filter list: one static filter per filter consumer. This is ++ * to avoid filter collisions later. Add new filters ++ * here!! ++ * ++ * Current filters: ++ * EAPOL 802.1x (0x888e): Filter 0 ++ * FCoE (0x8906): Filter 2 ++ * 1588 (0x88f7): Filter 3 ++ */ ++#define IXGBE_ETQF_FILTER_EAPOL 0 ++#define IXGBE_ETQF_FILTER_FCOE 2 ++#define IXGBE_ETQF_FILTER_1588 3 + /* VLAN Control Bit Masks */ + #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ + #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ +@@ -678,21 +1351,31 @@ + #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ + #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ + ++/* VLAN pool filtering masks */ ++#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */ ++#define IXGBE_VLVF_ENTRIES 64 ++#define IXGBE_VLVF_VLANID_MASK 0x00000FFF + + #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ + + /* STATUS Bit Masks */ +-#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ +-#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ ++#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ ++#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ ++#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ + + #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ + #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ + + /* ESDP Bit Masks */ +-#define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */ +-#define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */ ++#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */ ++#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */ ++#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */ ++#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */ ++#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */ ++#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */ ++#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */ + #define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */ +-#define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */ ++#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */ + + /* LEDCTL Bit Masks */ + #define IXGBE_LED_IVRT_BASE 0x00000040 +@@ -715,6 +1398,7 @@ + #define IXGBE_LED_OFF 0xF + + /* AUTOC Bit Masks */ ++#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000 + #define IXGBE_AUTOC_KX4_SUPP 0x80000000 + #define IXGBE_AUTOC_KX_SUPP 0x40000000 + #define IXGBE_AUTOC_PAUSE 0x30000000 +@@ -723,9 +1407,17 @@ + #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 + #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 + #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 ++#define IXGBE_AUTOC_FECA 0x00040000 ++#define IXGBE_AUTOC_FECR 0x00020000 ++#define IXGBE_AUTOC_KR_SUPP 0x00010000 + #define IXGBE_AUTOC_AN_RESTART 0x00001000 + #define IXGBE_AUTOC_FLU 0x00000001 + #define IXGBE_AUTOC_LMS_SHIFT 13 ++#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT) ++#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT) ++#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT) ++#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) ++#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT) + #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) + #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) + #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) +@@ -734,15 +1426,24 @@ + #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) + #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) + +-#define IXGBE_AUTOC_1G_PMA_PMD 0x00000200 +-#define IXGBE_AUTOC_10G_PMA_PMD 0x00000180 +-#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 +-#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 ++#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200 ++#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 ++#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 ++#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 + #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) + #define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) + #define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) + #define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) + #define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) ++#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) ++#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) ++ ++#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 ++#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 ++#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 ++#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) ++#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) ++#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) + + /* LINKS Bit Masks */ + #define IXGBE_LINKS_KX_AN_COMP 0x80000000 +@@ -752,6 +1453,7 @@ + #define IXGBE_LINKS_RX_MODE 0x06000000 + #define IXGBE_LINKS_TX_MODE 0x01800000 + #define IXGBE_LINKS_XGXS_EN 0x00400000 ++#define IXGBE_LINKS_SGMII_EN 0x02000000 + #define IXGBE_LINKS_PCS_1G_EN 0x00200000 + #define IXGBE_LINKS_1G_AN_EN 0x00100000 + #define IXGBE_LINKS_KX_AN_IDLE 0x00080000 +@@ -761,8 +1463,32 @@ + #define IXGBE_LINKS_TL_FAULT 0x00001000 + #define IXGBE_LINKS_SIGNAL 0x00000F00 + ++#define IXGBE_LINKS_SPEED_82599 0x30000000 ++#define IXGBE_LINKS_SPEED_10G_82599 0x30000000 ++#define IXGBE_LINKS_SPEED_1G_82599 0x20000000 ++#define IXGBE_LINKS_SPEED_100_82599 0x10000000 + #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ + #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ ++ ++/* PCS1GLSTA Bit Masks */ ++#define IXGBE_PCS1GLSTA_LINK_OK 1 ++#define IXGBE_PCS1GLSTA_SYNK_OK 0x10 ++#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 ++#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 ++#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 ++#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 ++#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 ++ ++#define IXGBE_PCS1GANA_SYM_PAUSE 0x80 ++#define IXGBE_PCS1GANA_ASM_PAUSE 0x100 ++ ++/* PCS1GLCTL Bit Masks */ ++#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ ++#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 ++#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 ++#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 ++#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 ++#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 + + /* SW Semaphore Register bitmasks */ + #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ +@@ -815,6 +1541,14 @@ + #define IXGBE_FW_PTR 0x0F + #define IXGBE_PBANUM0_PTR 0x15 + #define IXGBE_PBANUM1_PTR 0x16 ++#define IXGBE_SAN_MAC_ADDR_PTR 0x28 ++#define IXGBE_DEVICE_CAPS 0x2C ++#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 ++#define IXGBE_PCIE_MSIX_82599_CAPS 0x72 ++#define IXGBE_PCIE_MSIX_82598_CAPS 0x62 ++ ++/* MSI-X capability fields masks */ ++#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF + + /* Legacy EEPROM word offsets */ + #define IXGBE_ISCSI_BOOT_CAPS 0x0033 +@@ -853,8 +1587,21 @@ + #define IXGBE_EERD_ATTEMPTS 100000 + #endif + ++#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */ ++#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ ++#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ ++#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ ++ ++#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 ++#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 ++#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 ++#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 ++#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 ++#define IXGBE_FW_PATCH_VERSION_4 0x7 ++ + /* PCI Bus Info */ + #define IXGBE_PCI_LINK_STATUS 0xB2 ++#define IXGBE_PCI_DEVICE_CONTROL2 0xC8 + #define IXGBE_PCI_LINK_WIDTH 0x3F0 + #define IXGBE_PCI_LINK_WIDTH_1 0x10 + #define IXGBE_PCI_LINK_WIDTH_2 0x20 +@@ -863,6 +1610,9 @@ + #define IXGBE_PCI_LINK_SPEED 0xF + #define IXGBE_PCI_LINK_SPEED_2500 0x1 + #define IXGBE_PCI_LINK_SPEED_5000 0x2 ++#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E ++#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 ++#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 + + /* Number of 100 microseconds we wait for PCI Express master disable */ + #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 +@@ -902,6 +1652,7 @@ + /* Transmit Config masks */ + #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ + #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ ++#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ + /* Enable short packet padding to 64 bytes */ + #define IXGBE_TX_PAD_ENABLE 0x00000400 + #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ +@@ -915,6 +1666,7 @@ + #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ + #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ + #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ ++#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ + + #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ + #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ +@@ -925,9 +1677,23 @@ + /* Receive Priority Flow Control Enable */ + #define IXGBE_FCTRL_RPFCE 0x00004000 + #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ ++#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */ ++#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ ++#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ ++#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ + + /* Multiple Receive Queue Control */ + #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ ++#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ ++#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */ ++#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ ++#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ ++#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ ++#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ ++#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ ++#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ ++#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ ++#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ + #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 + #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 + #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 +@@ -938,6 +1704,12 @@ + #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 + #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 + #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 ++#define IXGBE_MRQC_L3L4TXSWEN 0x00008000 ++ ++/* Queue Drop Enable */ ++#define IXGBE_QDE_ENABLE 0x00000001 ++#define IXGBE_QDE_IDX_MASK 0x00007F00 ++#define IXGBE_QDE_IDX_SHIFT 8 + + #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ + #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ +@@ -949,10 +1721,26 @@ + #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ + #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ + ++#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000 ++#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 ++#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 ++#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000 ++#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 ++/* Multiple Transmit Queue Command Register */ ++#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */ ++#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */ ++#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */ ++#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */ ++#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */ ++#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */ ++ + /* Receive Descriptor bit definitions */ + #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ + #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ ++#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ + #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ ++#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ ++#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 + #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ + #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ + #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ +@@ -961,6 +1749,10 @@ + #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ + #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ + #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ ++#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */ ++#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ ++#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ ++#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ + #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ + #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ + #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ +@@ -969,6 +1761,13 @@ + #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ + #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ + #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ ++#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */ ++#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ ++#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */ ++#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */ ++#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */ ++#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */ ++#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */ + #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ + #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ + #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ +@@ -983,9 +1782,30 @@ + #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ + #define IXGBE_RXD_CFI_SHIFT 12 + ++#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ ++#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ ++#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ ++#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ ++#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */ ++#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ ++#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ ++#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ ++#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ ++#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ ++#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ ++ ++/* PSRTYPE bit definitions */ ++#define IXGBE_PSRTYPE_TCPHDR 0x00000010 ++#define IXGBE_PSRTYPE_UDPHDR 0x00000020 ++#define IXGBE_PSRTYPE_IPV4HDR 0x00000100 ++#define IXGBE_PSRTYPE_IPV6HDR 0x00000200 ++#define IXGBE_PSRTYPE_L2HDR 0x00001000 + + /* SRRCTL bit definitions */ + #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ ++#define IXGBE_SRRCTL_RDMTS_SHIFT 22 ++#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 ++#define IXGBE_SRRCTL_DROP_EN 0x10000000 + #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F + #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 + #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 +@@ -1000,7 +1820,10 @@ + + #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F + #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 ++#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 + #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 ++#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 ++#define IXGBE_RXDADV_RSCCNT_SHIFT 17 + #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 + #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 + #define IXGBE_RXDADV_SPH 0x8000 +@@ -1027,6 +1850,20 @@ + #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ + #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ + #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ ++#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ ++#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ ++#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ ++#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ ++#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ ++#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ ++ ++/* Security Processing bit Indication */ ++#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000 ++#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 ++#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 ++#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 ++#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 ++ + /* Masks to determine if packets should be dropped due to frame errors */ + #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ + IXGBE_RXD_ERR_CE | \ +@@ -1056,6 +1893,105 @@ + #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ + #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT + ++/* SR-IOV specific macros */ ++#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4) ++#define IXGBE_MBVFICR(_i) (0x00710 + (_i * 4)) ++#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600)) ++#define IXGBE_VFLREC(_i) (0x00700 + (_i * 4)) ++ ++/* Little Endian defines */ ++#ifndef __le16 ++#define __le16 u16 ++#endif ++#ifndef __le32 ++#define __le32 u32 ++#endif ++#ifndef __le64 ++#define __le64 u64 ++ ++#endif ++#ifndef __be16 ++/* Big Endian defines */ ++#define __be16 u16 ++#define __be32 u32 ++#define __be64 u64 ++ ++#endif ++enum ixgbe_fdir_pballoc_type { ++ IXGBE_FDIR_PBALLOC_64K = 0, ++ IXGBE_FDIR_PBALLOC_128K, ++ IXGBE_FDIR_PBALLOC_256K, ++}; ++#define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16 ++ ++/* Flow Director register values */ ++#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 ++#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 ++#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 ++#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 ++#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 ++#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 ++#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 ++#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 ++#define IXGBE_FDIRCTRL_FLEX_SHIFT 16 ++#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 ++#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 ++#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 ++#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 ++ ++#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16 ++#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16 ++#define IXGBE_FDIRIP6M_DIPM_SHIFT 16 ++#define IXGBE_FDIRM_VLANID 0x00000001 ++#define IXGBE_FDIRM_VLANP 0x00000002 ++#define IXGBE_FDIRM_POOL 0x00000004 ++#define IXGBE_FDIRM_L3P 0x00000008 ++#define IXGBE_FDIRM_L4P 0x00000010 ++#define IXGBE_FDIRM_FLEX 0x00000020 ++#define IXGBE_FDIRM_DIPv6 0x00000040 ++ ++#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF ++#define IXGBE_FDIRFREE_FREE_SHIFT 0 ++#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000 ++#define IXGBE_FDIRFREE_COLL_SHIFT 16 ++#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F ++#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0 ++#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000 ++#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16 ++#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF ++#define IXGBE_FDIRUSTAT_ADD_SHIFT 0 ++#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000 ++#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16 ++#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF ++#define IXGBE_FDIRFSTAT_FADD_SHIFT 0 ++#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00 ++#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8 ++#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16 ++#define IXGBE_FDIRVLAN_FLEX_SHIFT 16 ++#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15 ++#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16 ++ ++#define IXGBE_FDIRCMD_CMD_MASK 0x00000003 ++#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 ++#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 ++#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 ++#define IXGBE_FDIRCMD_CMD_QUERY_REM_HASH 0x00000007 ++#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 ++#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 ++#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 ++#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040 ++#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060 ++#define IXGBE_FDIRCMD_IPV6 0x00000080 ++#define IXGBE_FDIRCMD_CLEARHT 0x00000100 ++#define IXGBE_FDIRCMD_DROP 0x00000200 ++#define IXGBE_FDIRCMD_INT 0x00000400 ++#define IXGBE_FDIRCMD_LAST 0x00000800 ++#define IXGBE_FDIRCMD_COLLISION 0x00001000 ++#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000 ++#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16 ++#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24 ++#define IXGBE_FDIR_INIT_DONE_POLL 10 ++#define IXGBE_FDIRCMD_CMD_POLL 10 + + /* Transmit Descriptor - Legacy */ + struct ixgbe_legacy_tx_desc { +@@ -1143,6 +2079,9 @@ + + /* Adv Transmit Descriptor Config Masks */ + #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ ++#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */ ++#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ ++#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ + #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ + #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ + #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ +@@ -1177,6 +2116,19 @@ + #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ + #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ + #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/ ++#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ ++#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ ++#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ ++#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ ++#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ ++#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ ++#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ ++#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */ ++#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */ ++#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ ++#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ ++#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ ++#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */ + #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ + #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ + +@@ -1190,13 +2142,17 @@ + #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 + #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ + IXGBE_LINK_SPEED_10GB_FULL) ++#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ ++ IXGBE_LINK_SPEED_1GB_FULL | \ ++ IXGBE_LINK_SPEED_10GB_FULL) ++ + + /* Physical layer type */ + typedef u32 ixgbe_physical_layer; + #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 + #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001 + #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002 +-#define IXGBE_PHYSICAL_LAYER_100BASE_T 0x0004 ++#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004 + #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008 + #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010 + #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020 +@@ -1205,7 +2161,47 @@ + #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100 + #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200 + #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400 ++#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800 ++#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000 + ++/* Software ATR hash keys */ ++#define IXGBE_ATR_BUCKET_HASH_KEY 0xE214AD3D ++#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x14364D17 ++ ++/* Software ATR input stream offsets and masks */ ++#define IXGBE_ATR_VLAN_OFFSET 0 ++#define IXGBE_ATR_SRC_IPV6_OFFSET 2 ++#define IXGBE_ATR_SRC_IPV4_OFFSET 14 ++#define IXGBE_ATR_DST_IPV6_OFFSET 18 ++#define IXGBE_ATR_DST_IPV4_OFFSET 30 ++#define IXGBE_ATR_SRC_PORT_OFFSET 34 ++#define IXGBE_ATR_DST_PORT_OFFSET 36 ++#define IXGBE_ATR_FLEX_BYTE_OFFSET 38 ++#define IXGBE_ATR_VM_POOL_OFFSET 40 ++#define IXGBE_ATR_L4TYPE_OFFSET 41 ++ ++#define IXGBE_ATR_L4TYPE_MASK 0x3 ++#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4 ++#define IXGBE_ATR_L4TYPE_UDP 0x1 ++#define IXGBE_ATR_L4TYPE_TCP 0x2 ++#define IXGBE_ATR_L4TYPE_SCTP 0x3 ++#define IXGBE_ATR_HASH_MASK 0x7fff ++ ++/* Flow Director ATR input struct. */ ++struct ixgbe_atr_input { ++ /* Byte layout in order, all values with MSB first: ++ * ++ * vlan_id - 2 bytes ++ * src_ip - 16 bytes ++ * dst_ip - 16 bytes ++ * src_port - 2 bytes ++ * dst_port - 2 bytes ++ * flex_bytes - 2 bytes ++ * vm_pool - 1 byte ++ * l4type - 1 byte ++ */ ++ u8 byte_stream[42]; ++}; + + enum ixgbe_eeprom_type { + ixgbe_eeprom_uninitialized = 0, +@@ -1216,12 +2212,16 @@ + enum ixgbe_mac_type { + ixgbe_mac_unknown = 0, + ixgbe_mac_82598EB, ++ ixgbe_mac_82599EB, + ixgbe_num_macs + }; + + enum ixgbe_phy_type { + ixgbe_phy_unknown = 0, ++ ixgbe_phy_none, + ixgbe_phy_tn, ++ ixgbe_phy_aq, ++ ixgbe_phy_cu_unknown, + ixgbe_phy_qt, + ixgbe_phy_xaui, + ixgbe_phy_nl, +@@ -1230,6 +2230,8 @@ + ixgbe_phy_sfp_avago, + ixgbe_phy_sfp_ftl, + ixgbe_phy_sfp_unknown, ++ ixgbe_phy_sfp_intel, ++ ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/ + ixgbe_phy_generic + }; + +@@ -1241,11 +2243,19 @@ + * 0 SFP_DA_CU + * 1 SFP_SR + * 2 SFP_LR ++ * 3 SFP_DA_CU_CORE0 - 82599-specific ++ * 4 SFP_DA_CU_CORE1 - 82599-specific ++ * 5 SFP_SR/LR_CORE0 - 82599-specific ++ * 6 SFP_SR/LR_CORE1 - 82599-specific + */ + enum ixgbe_sfp_type { + ixgbe_sfp_type_da_cu = 0, + ixgbe_sfp_type_sr = 1, + ixgbe_sfp_type_lr = 2, ++ ixgbe_sfp_type_da_cu_core0 = 3, ++ ixgbe_sfp_type_da_cu_core1 = 4, ++ ixgbe_sfp_type_srlr_core0 = 5, ++ ixgbe_sfp_type_srlr_core1 = 6, + ixgbe_sfp_type_not_present = 0xFFFE, + ixgbe_sfp_type_unknown = 0xFFFF + }; +@@ -1259,21 +2269,67 @@ + }; + + /* Flow Control Settings */ +-enum ixgbe_fc_type { ++enum ixgbe_fc_mode { + ixgbe_fc_none = 0, + ixgbe_fc_rx_pause, + ixgbe_fc_tx_pause, + ixgbe_fc_full, ++#ifdef CONFIG_DCB ++ ixgbe_fc_pfc, ++#endif + ixgbe_fc_default ++}; ++ ++/* PCI bus types */ ++enum ixgbe_bus_type { ++ ixgbe_bus_type_unknown = 0, ++ ixgbe_bus_type_pci, ++ ixgbe_bus_type_pcix, ++ ixgbe_bus_type_pci_express, ++ ixgbe_bus_type_reserved ++}; ++ ++/* PCI bus speeds */ ++enum ixgbe_bus_speed { ++ ixgbe_bus_speed_unknown = 0, ++ ixgbe_bus_speed_33, ++ ixgbe_bus_speed_66, ++ ixgbe_bus_speed_100, ++ ixgbe_bus_speed_120, ++ ixgbe_bus_speed_133, ++ ixgbe_bus_speed_2500, ++ ixgbe_bus_speed_5000, ++ ixgbe_bus_speed_reserved ++}; ++ ++/* PCI bus widths */ ++enum ixgbe_bus_width { ++ ixgbe_bus_width_unknown = 0, ++ ixgbe_bus_width_pcie_x1, ++ ixgbe_bus_width_pcie_x2, ++ ixgbe_bus_width_pcie_x4 = 4, ++ ixgbe_bus_width_pcie_x8 = 8, ++ ixgbe_bus_width_32, ++ ixgbe_bus_width_64, ++ ixgbe_bus_width_reserved + }; + + struct ixgbe_addr_filter_info { + u32 num_mc_addrs; + u32 rar_used_count; +- u32 mc_addr_in_rar_count; + u32 mta_in_use; + u32 overflow_promisc; + bool user_set_promisc; ++}; ++ ++/* Bus parameters */ ++struct ixgbe_bus_info { ++ enum ixgbe_bus_speed speed; ++ enum ixgbe_bus_width width; ++ enum ixgbe_bus_type type; ++ ++ u16 func; ++ u16 lan_id; + }; + + /* Flow control parameters */ +@@ -1283,8 +2339,10 @@ + u16 pause_time; /* Flow Control Pause timer */ + bool send_xon; /* Flow control send XON */ + bool strict_ieee; /* Strict IEEE mode */ +- enum ixgbe_fc_type type; /* Type of flow control */ +- enum ixgbe_fc_type original_type; ++ bool disable_fc_autoneg; /* Do not autonegotiate FC */ ++ bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ ++ enum ixgbe_fc_mode current_mode; /* FC mode in effect */ ++ enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */ + }; + + /* Statistics counters collected by the MAC */ +@@ -1344,6 +2402,21 @@ + u64 qptc[16]; + u64 qbrc[16]; + u64 qbtc[16]; ++ u64 qprdc[16]; ++ u64 pxon2offc[8]; ++ u64 fdirustat_add; ++ u64 fdirustat_remove; ++ u64 fdirfstat_fadd; ++ u64 fdirfstat_fremove; ++ u64 fdirmatch; ++ u64 fdirmiss; ++ u64 fccrc; ++ u64 fclast; ++ u64 fcoerpdc; ++ u64 fcoeprc; ++ u64 fcoeptc; ++ u64 fcoedwrc; ++ u64 fcoedwtc; + }; + + /* forward declaration */ +@@ -1368,12 +2441,20 @@ + s32 (*start_hw)(struct ixgbe_hw *); + s32 (*clear_hw_cntrs)(struct ixgbe_hw *); + enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); +- s32 (*get_supported_physical_layer)(struct ixgbe_hw *); ++ u32 (*get_supported_physical_layer)(struct ixgbe_hw *); + s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); ++ s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); ++ s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *); ++ s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); + s32 (*stop_adapter)(struct ixgbe_hw *); + s32 (*get_bus_info)(struct ixgbe_hw *); ++ void (*set_lan_id)(struct ixgbe_hw *); + s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); + s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); ++ s32 (*setup_sfp)(struct ixgbe_hw *); ++ s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); ++ s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16); ++ void (*release_swfw_sync)(struct ixgbe_hw *, u16); + + /* Link */ + s32 (*setup_link)(struct ixgbe_hw *); +@@ -1392,6 +2473,7 @@ + /* RAR, Multicast, VLAN */ + s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); + s32 (*clear_rar)(struct ixgbe_hw *, u32); ++ s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32); + s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); + s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); + s32 (*init_rx_addrs)(struct ixgbe_hw *); +@@ -1406,12 +2488,13 @@ + s32 (*init_uta_tables)(struct ixgbe_hw *); + + /* Flow Control */ +- s32 (*setup_fc)(struct ixgbe_hw *, s32); ++ s32 (*fc_enable)(struct ixgbe_hw *, s32); + }; + + struct ixgbe_phy_operations { + s32 (*identify)(struct ixgbe_hw *); + s32 (*identify_sfp)(struct ixgbe_hw *); ++ s32 (*init)(struct ixgbe_hw *); + s32 (*reset)(struct ixgbe_hw *); + s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); + s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); +@@ -1424,12 +2507,13 @@ + s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); + s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); + s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); ++ void (*i2c_bus_clear)(struct ixgbe_hw *); + }; + + struct ixgbe_eeprom_info { + struct ixgbe_eeprom_operations ops; + enum ixgbe_eeprom_type type; +- u32 semaphore_delay; ++ u32 semaphore_delay; + u16 word_size; + u16 address_bits; + }; +@@ -1439,17 +2523,22 @@ + enum ixgbe_mac_type type; + u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; + u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; ++ u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; + s32 mc_filter_type; + u32 mcft_size; + u32 vft_size; + u32 num_rar_entries; ++ u32 rar_highwater; + u32 max_tx_queues; + u32 max_rx_queues; +- u32 link_attach_type; +- u32 link_mode_select; +- bool link_settings_loaded; ++ u32 max_msix_vectors; ++ bool msix_vectors_from_pcie; ++ u32 orig_autoc; ++ u32 orig_autoc2; ++ bool orig_link_settings_stored; + bool autoneg; +- bool autoneg_failed; ++ bool autoneg_succeeded; ++ bool autotry_restart; + }; + + struct ixgbe_phy_info { +@@ -1458,36 +2547,34 @@ + u32 addr; + u32 id; + enum ixgbe_sfp_type sfp_type; ++ bool sfp_setup_needed; + u32 revision; + enum ixgbe_media_type media_type; + bool reset_disable; + ixgbe_autoneg_advertised autoneg_advertised; + bool autoneg_wait_to_complete; ++ bool multispeed_fiber; + }; + + struct ixgbe_hw { +- u8 __iomem *hw_addr; +- void *back; +- struct ixgbe_mac_info mac; +- struct ixgbe_addr_filter_info addr_ctrl; +- struct ixgbe_fc_info fc; +- struct ixgbe_phy_info phy; +- struct ixgbe_eeprom_info eeprom; +- u16 device_id; +- u16 vendor_id; +- u16 subsystem_device_id; +- u16 subsystem_vendor_id; +- u8 revision_id; +- bool adapter_stopped; ++ u8 __iomem *hw_addr; ++ void *back; ++ struct ixgbe_mac_info mac; ++ struct ixgbe_addr_filter_info addr_ctrl; ++ struct ixgbe_fc_info fc; ++ struct ixgbe_phy_info phy; ++ struct ixgbe_eeprom_info eeprom; ++ struct ixgbe_bus_info bus; ++ u16 device_id; ++ u16 vendor_id; ++ u16 subsystem_device_id; ++ u16 subsystem_vendor_id; ++ u8 revision_id; ++ bool adapter_stopped; + }; + +-struct ixgbe_info { +- enum ixgbe_mac_type mac; +- s32 (*get_invariants)(struct ixgbe_hw *); +- struct ixgbe_mac_operations *mac_ops; +- struct ixgbe_eeprom_operations *eeprom_ops; +- struct ixgbe_phy_operations *phy_ops; +-}; ++#define ixgbe_call_func(hw, func, params, error) \ ++ (func != NULL) ? func params : error + + + /* Error Codes */ +@@ -1511,6 +2598,11 @@ + #define IXGBE_ERR_I2C -18 + #define IXGBE_ERR_SFP_NOT_SUPPORTED -19 + #define IXGBE_ERR_SFP_NOT_PRESENT -20 ++#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 ++#define IXGBE_ERR_NO_SAN_ADDR_PTR -22 ++#define IXGBE_ERR_FDIR_REINIT_FAILED -23 ++#define IXGBE_ERR_EEPROM_VERSION -24 + #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF + ++ + #endif /* _IXGBE_TYPE_H_ */ +diff -r 1efe16c57de3 drivers/net/ixgbe/kcompat.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/ixgbe/kcompat.c Wed Aug 05 11:05:50 2009 +0100 +@@ -0,0 +1,564 @@ ++/******************************************************************************* ++ ++ Intel 10 Gigabit PCI Express Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "ixgbe.h" ++#include "kcompat.h" ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,21) ) ++struct sk_buff * ++_kc_skb_pad(struct sk_buff *skb, int pad) ++{ ++ struct sk_buff *nskb; ++ ++ /* If the skbuff is non linear tailroom is always zero.. */ ++ if(skb_tailroom(skb) >= pad) ++ { ++ memset(skb->data+skb->len, 0, pad); ++ return skb; ++ } ++ ++ nskb = skb_copy_expand(skb, skb_headroom(skb), skb_tailroom(skb) + pad, GFP_ATOMIC); ++ kfree_skb(skb); ++ if(nskb) ++ memset(nskb->data+nskb->len, 0, pad); ++ return nskb; ++} ++#endif /* < 2.4.21 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) ) ++ ++/**************************************/ ++/* PCI DMA MAPPING */ ++ ++#if defined(CONFIG_HIGHMEM) ++ ++#ifndef PCI_DRAM_OFFSET ++#define PCI_DRAM_OFFSET 0 ++#endif ++ ++u64 ++_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, ++ size_t size, int direction) ++{ ++ return (((u64) (page - mem_map) << PAGE_SHIFT) + offset + ++ PCI_DRAM_OFFSET); ++} ++ ++#else /* CONFIG_HIGHMEM */ ++ ++u64 ++_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, ++ size_t size, int direction) ++{ ++ return pci_map_single(dev, (void *)page_address(page) + offset, size, ++ direction); ++} ++ ++#endif /* CONFIG_HIGHMEM */ ++ ++void ++_kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, ++ int direction) ++{ ++ return pci_unmap_single(dev, dma_addr, size, direction); ++} ++ ++#endif /* 2.4.13 => 2.4.3 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) ) ++ ++/**************************************/ ++/* PCI DRIVER API */ ++ ++int ++_kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask) ++{ ++ if (!pci_dma_supported(dev, mask)) ++ return -EIO; ++ dev->dma_mask = mask; ++ return 0; ++} ++ ++int ++_kc_pci_request_regions(struct pci_dev *dev, char *res_name) ++{ ++ int i; ++ ++ for (i = 0; i < 6; i++) { ++ if (pci_resource_len(dev, i) == 0) ++ continue; ++ ++ if (pci_resource_flags(dev, i) & IORESOURCE_IO) { ++ if (!request_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) { ++ pci_release_regions(dev); ++ return -EBUSY; ++ } ++ } else if (pci_resource_flags(dev, i) & IORESOURCE_MEM) { ++ if (!request_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) { ++ pci_release_regions(dev); ++ return -EBUSY; ++ } ++ } ++ } ++ return 0; ++} ++ ++void ++_kc_pci_release_regions(struct pci_dev *dev) ++{ ++ int i; ++ ++ for (i = 0; i < 6; i++) { ++ if (pci_resource_len(dev, i) == 0) ++ continue; ++ ++ if (pci_resource_flags(dev, i) & IORESOURCE_IO) ++ release_region(pci_resource_start(dev, i), pci_resource_len(dev, i)); ++ ++ else if (pci_resource_flags(dev, i) & IORESOURCE_MEM) ++ release_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i)); ++ } ++} ++ ++/**************************************/ ++/* NETWORK DRIVER API */ ++ ++struct net_device * ++_kc_alloc_etherdev(int sizeof_priv) ++{ ++ struct net_device *dev; ++ int alloc_size; ++ ++ alloc_size = sizeof(*dev) + sizeof_priv + IFNAMSIZ + 31; ++ dev = kmalloc(alloc_size, GFP_KERNEL); ++ if (!dev) ++ return NULL; ++ memset(dev, 0, alloc_size); ++ ++ if (sizeof_priv) ++ dev->priv = (void *) (((unsigned long)(dev + 1) + 31) & ~31); ++ dev->name[0] = '\0'; ++ ether_setup(dev); ++ ++ return dev; ++} ++ ++int ++_kc_is_valid_ether_addr(u8 *addr) ++{ ++ const char zaddr[6] = { 0, }; ++ ++ return !(addr[0] & 1) && memcmp(addr, zaddr, 6); ++} ++ ++#endif /* 2.4.3 => 2.4.0 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) ) ++ ++int ++_kc_pci_set_power_state(struct pci_dev *dev, int state) ++{ ++ return 0; ++} ++ ++int ++_kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable) ++{ ++ return 0; ++} ++ ++#endif /* 2.4.6 => 2.4.3 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) ++void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, ++ int off, int size) ++{ ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ frag->page = page; ++ frag->page_offset = off; ++ frag->size = size; ++ skb_shinfo(skb)->nr_frags = i + 1; ++} ++ ++/* ++ * Original Copyright: ++ * find_next_bit.c: fallback find next bit implementation ++ * ++ * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. ++ * Written by David Howells (dhowells@redhat.com) ++ */ ++ ++/** ++ * find_next_bit - find the next set bit in a memory region ++ * @addr: The address to base the search on ++ * @offset: The bitnumber to start searching at ++ * @size: The maximum size to search ++ */ ++unsigned long find_next_bit(const unsigned long *addr, unsigned long size, ++ unsigned long offset) ++{ ++ const unsigned long *p = addr + BITOP_WORD(offset); ++ unsigned long result = offset & ~(BITS_PER_LONG-1); ++ unsigned long tmp; ++ ++ if (offset >= size) ++ return size; ++ size -= result; ++ offset %= BITS_PER_LONG; ++ if (offset) { ++ tmp = *(p++); ++ tmp &= (~0UL << offset); ++ if (size < BITS_PER_LONG) ++ goto found_first; ++ if (tmp) ++ goto found_middle; ++ size -= BITS_PER_LONG; ++ result += BITS_PER_LONG; ++ } ++ while (size & ~(BITS_PER_LONG-1)) { ++ if ((tmp = *(p++))) ++ goto found_middle; ++ result += BITS_PER_LONG; ++ size -= BITS_PER_LONG; ++ } ++ if (!size) ++ return result; ++ tmp = *p; ++ ++found_first: ++ tmp &= (~0UL >> (BITS_PER_LONG - size)); ++ if (tmp == 0UL) /* Are any bits set? */ ++ return result + size; /* Nope. */ ++found_middle: ++ return result + ffs(tmp); ++} ++ ++#endif /* 2.6.0 => 2.4.6 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) ) ++void *_kc_kzalloc(size_t size, int flags) ++{ ++ void *ret = kmalloc(size, flags); ++ if (ret) ++ memset(ret, 0, size); ++ return ret; ++} ++#endif /* <= 2.6.13 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ) ++struct sk_buff *_kc_netdev_alloc_skb(struct net_device *dev, ++ unsigned int length) ++{ ++ /* 16 == NET_PAD_SKB */ ++ struct sk_buff *skb; ++ skb = alloc_skb(length + 16, GFP_ATOMIC); ++ if (likely(skb != NULL)) { ++ skb_reserve(skb, 16); ++ skb->dev = dev; ++ } ++ return skb; ++} ++#endif /* <= 2.6.17 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ) ++int _kc_pci_save_state(struct pci_dev *pdev) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int size = PCI_CONFIG_SPACE_LEN, i; ++ u16 pcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP); ++ u16 pcie_link_status; ++ ++ if (pcie_cap_offset) { ++ if (!pci_read_config_word(pdev, ++ pcie_cap_offset + PCIE_LINK_STATUS, ++ &pcie_link_status)) ++ size = PCIE_CONFIG_SPACE_LEN; ++ } ++ pci_config_space_ich8lan(); ++#ifdef HAVE_PCI_ERS ++ if (adapter->config_space == NULL) ++#else ++ WARN_ON(adapter->config_space != NULL); ++#endif ++ adapter->config_space = kmalloc(size, GFP_KERNEL); ++ if (!adapter->config_space) { ++ printk(KERN_ERR "Out of memory in pci_save_state\n"); ++ return -ENOMEM; ++ } ++ for (i = 0; i < (size / 4); i++) ++ pci_read_config_dword(pdev, i * 4, &adapter->config_space[i]); ++ return 0; ++} ++ ++void _kc_pci_restore_state(struct pci_dev * pdev) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int size = PCI_CONFIG_SPACE_LEN, i; ++ u16 pcie_cap_offset; ++ u16 pcie_link_status; ++ ++ if (adapter->config_space != NULL) { ++ pcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP); ++ if (pcie_cap_offset && ++ !pci_read_config_word(pdev, ++ pcie_cap_offset + PCIE_LINK_STATUS, ++ &pcie_link_status)) ++ size = PCIE_CONFIG_SPACE_LEN; ++ ++ pci_config_space_ich8lan(); ++ for (i = 0; i < (size / 4); i++) ++ pci_write_config_dword(pdev, i * 4, adapter->config_space[i]); ++#ifndef HAVE_PCI_ERS ++ kfree(adapter->config_space); ++ adapter->config_space = NULL; ++#endif ++ } ++} ++ ++#ifdef HAVE_PCI_ERS ++void _kc_free_netdev(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ ++ if (adapter->config_space != NULL) ++ kfree(adapter->config_space); ++#ifdef CONFIG_SYSFS ++ if (netdev->reg_state == NETREG_UNINITIALIZED) { ++ kfree((char *)netdev - netdev->padded); ++ } else { ++ BUG_ON(netdev->reg_state != NETREG_UNREGISTERED); ++ netdev->reg_state = NETREG_RELEASED; ++ class_device_put(&netdev->class_dev); ++ } ++#else ++ kfree((char *)netdev - netdev->padded); ++#endif ++} ++#endif ++#endif /* <= 2.6.18 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ) ++ ++int ixgbe_dcb_netlink_register() ++{ ++ return 0; ++} ++ ++int ixgbe_dcb_netlink_unregister() ++{ ++ return 0; ++} ++#endif /* < 2.6.23 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ) ++#ifdef NAPI ++struct net_device *napi_to_poll_dev(struct napi_struct *napi) ++{ ++ struct adapter_q_vector *q_vector = container_of(napi, ++ struct adapter_q_vector, ++ napi); ++ return &q_vector->poll_dev; ++} ++ ++int __kc_adapter_clean(struct net_device *netdev, int *budget) ++{ ++ int work_done; ++ int work_to_do = min(*budget, netdev->quota); ++ /* kcompat.h netif_napi_add puts napi struct in "fake netdev->priv" */ ++ struct napi_struct *napi = netdev->priv; ++ work_done = napi->poll(napi, work_to_do); ++ *budget -= work_done; ++ netdev->quota -= work_done; ++ return (work_done >= work_to_do) ? 1 : 0; ++} ++#endif /* NAPI */ ++#endif /* <= 2.6.24 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) ++#ifdef HAVE_TX_MQ ++void _kc_netif_tx_stop_all_queues(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int i; ++ ++ netif_stop_queue(netdev); ++ if (netif_is_multiqueue(netdev)) ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ netif_stop_subqueue(netdev, i); ++} ++void _kc_netif_tx_wake_all_queues(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int i; ++ ++ netif_wake_queue(netdev); ++ if (netif_is_multiqueue(netdev)) ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ netif_wake_subqueue(netdev, i); ++} ++void _kc_netif_tx_start_all_queues(struct net_device *netdev) ++{ ++ struct adapter_struct *adapter = netdev_priv(netdev); ++ int i; ++ ++ netif_start_queue(netdev); ++ if (netif_is_multiqueue(netdev)) ++ for (i = 0; i < adapter->num_tx_queues; i++) ++ netif_start_subqueue(netdev, i); ++} ++#endif /* HAVE_TX_MQ */ ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) ++ ++int ++_kc_pci_prepare_to_sleep(struct pci_dev *dev) ++{ ++ pci_power_t target_state; ++ int error; ++ ++ target_state = pci_choose_state(dev, PMSG_SUSPEND); ++ ++ pci_enable_wake(dev, target_state, true); ++ ++ error = pci_set_power_state(dev, target_state); ++ ++ if (error) ++ pci_enable_wake(dev, target_state, false); ++ ++ return error; ++} ++ ++int ++_kc_pci_wake_from_d3(struct pci_dev *dev, bool enable) ++{ ++ int err; ++ ++ err = pci_enable_wake(dev, PCI_D3cold, enable); ++ if (err) ++ goto out; ++ ++ err = pci_enable_wake(dev, PCI_D3hot, enable); ++ ++out: ++ return err; ++} ++#endif /* < 2.6.28 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) ) ++void _kc_pci_disable_link_state(struct pci_dev *pdev, int state) ++{ ++ struct pci_dev *parent = pdev->bus->self; ++ u16 link_state; ++ int pos; ++ ++ if (!parent) ++ return; ++ ++ pos = pci_find_capability(parent, PCI_CAP_ID_EXP); ++ if (pos) { ++ pci_read_config_word(parent, pos + PCI_EXP_LNKCTL, &link_state); ++ link_state &= ~state; ++ pci_write_config_word(parent, pos + PCI_EXP_LNKCTL, link_state); ++ } ++} ++#endif /* < 2.6.29 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ) ++#ifdef HAVE_NETDEV_SELECT_QUEUE ++#include ++static u32 _kc_simple_tx_hashrnd; ++static u32 _kc_simple_tx_hashrnd_initialized; ++ ++u16 _kc_skb_tx_hash(struct net_device *dev, struct sk_buff *skb) ++{ ++ u32 addr1, addr2, ports; ++ u32 hash, ihl; ++ u8 ip_proto = 0; ++ ++ if (unlikely(!_kc_simple_tx_hashrnd_initialized)) { ++ get_random_bytes(&_kc_simple_tx_hashrnd, 4); ++ _kc_simple_tx_hashrnd_initialized = 1; ++ } ++ ++ switch (skb->protocol) { ++ case htons(ETH_P_IP): ++ if (!(ip_hdr(skb)->frag_off & htons(IP_MF | IP_OFFSET))) ++ ip_proto = ip_hdr(skb)->protocol; ++ addr1 = ip_hdr(skb)->saddr; ++ addr2 = ip_hdr(skb)->daddr; ++ ihl = ip_hdr(skb)->ihl; ++ break; ++ case htons(ETH_P_IPV6): ++ ip_proto = ipv6_hdr(skb)->nexthdr; ++ addr1 = ipv6_hdr(skb)->saddr.s6_addr32[3]; ++ addr2 = ipv6_hdr(skb)->daddr.s6_addr32[3]; ++ ihl = (40 >> 2); ++ break; ++ default: ++ return 0; ++ } ++ ++ ++ switch (ip_proto) { ++ case IPPROTO_TCP: ++ case IPPROTO_UDP: ++ case IPPROTO_DCCP: ++ case IPPROTO_ESP: ++ case IPPROTO_AH: ++ case IPPROTO_SCTP: ++ case IPPROTO_UDPLITE: ++ ports = *((u32 *) (skb_network_header(skb) + (ihl * 4))); ++ break; ++ ++ default: ++ ports = 0; ++ break; ++ } ++ ++ hash = jhash_3words(addr1, addr2, ports, _kc_simple_tx_hashrnd); ++ ++ return (u16) (((u64) hash * dev->real_num_tx_queues) >> 32); ++} ++#endif /* HAVE_NETDEV_SELECT_QUEUE */ ++#endif /* < 2.6.30 */ +diff -r 1efe16c57de3 drivers/net/ixgbe/kcompat.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/ixgbe/kcompat.h Wed Aug 05 11:05:50 2009 +0100 +@@ -0,0 +1,1805 @@ ++/******************************************************************************* ++ ++ Intel 10 Gigabit PCI Express Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _KCOMPAT_H_ ++#define _KCOMPAT_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* NAPI enable/disable flags here */ ++/* enable NAPI for ixgbe by default */ ++#undef CONFIG_IXGBE_NAPI ++#define CONFIG_IXGBE_NAPI ++#define NAPI ++#ifdef CONFIG_IXGBE_NAPI ++#undef NAPI ++#define NAPI ++#endif /* CONFIG_IXGBE_NAPI */ ++#ifdef IXGBE_NAPI ++#undef NAPI ++#define NAPI ++#endif /* IXGBE_NAPI */ ++#ifdef IXGBE_NO_NAPI ++#undef NAPI ++#endif /* IXGBE_NO_NAPI */ ++ ++#define adapter_struct ixgbe_adapter ++#define adapter_q_vector ixgbe_q_vector ++ ++/* and finally set defines so that the code sees the changes */ ++#ifdef NAPI ++#ifndef CONFIG_IXGBE_NAPI ++#define CONFIG_IXGBE_NAPI ++#endif ++#else ++#undef CONFIG_IXGBE_NAPI ++#endif /* NAPI */ ++ ++/* MSI compatibility code for all kernels and drivers */ ++#ifdef DISABLE_PCI_MSI ++#undef CONFIG_PCI_MSI ++#endif ++#ifndef CONFIG_PCI_MSI ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) ) ++struct msix_entry { ++ u16 vector; /* kernel uses to write allocated vector */ ++ u16 entry; /* driver uses to specify entry, OS writes */ ++}; ++#endif ++#define pci_enable_msi(a) -ENOTSUPP ++#define pci_disable_msi(a) do {} while (0) ++#define pci_enable_msix(a, b, c) -ENOTSUPP ++#define pci_disable_msix(a) do {} while (0) ++#define msi_remove_pci_irq_vectors(a) do {} while (0) ++#endif /* CONFIG_PCI_MSI */ ++#ifdef DISABLE_PM ++#undef CONFIG_PM ++#endif ++ ++#ifdef DISABLE_NET_POLL_CONTROLLER ++#undef CONFIG_NET_POLL_CONTROLLER ++#endif ++ ++#ifndef PMSG_SUSPEND ++#define PMSG_SUSPEND 3 ++#endif ++ ++/* generic boolean compatibility */ ++#undef TRUE ++#undef FALSE ++#define TRUE true ++#define FALSE false ++#ifdef GCC_VERSION ++#if ( GCC_VERSION < 3000 ) ++#define _Bool char ++#endif ++#else ++#define _Bool char ++#endif ++#ifndef bool ++#define bool _Bool ++#define true 1 ++#define false 0 ++#endif ++ ++ ++#ifndef module_param ++#define module_param(v,t,p) MODULE_PARM(v, "i"); ++#endif ++ ++#ifndef DMA_64BIT_MASK ++#define DMA_64BIT_MASK 0xffffffffffffffffULL ++#endif ++ ++#ifndef DMA_32BIT_MASK ++#define DMA_32BIT_MASK 0x00000000ffffffffULL ++#endif ++ ++#ifndef PCI_CAP_ID_EXP ++#define PCI_CAP_ID_EXP 0x10 ++#endif ++ ++#ifndef PCIE_LINK_STATE_L0S ++#define PCIE_LINK_STATE_L0S 1 ++#endif ++ ++#ifndef mmiowb ++#ifdef CONFIG_IA64 ++#define mmiowb() asm volatile ("mf.a" ::: "memory") ++#else ++#define mmiowb() ++#endif ++#endif ++ ++#ifndef SET_NETDEV_DEV ++#define SET_NETDEV_DEV(net, pdev) ++#endif ++ ++#ifndef HAVE_FREE_NETDEV ++#define free_netdev(x) kfree(x) ++#endif ++ ++#ifdef HAVE_POLL_CONTROLLER ++#define CONFIG_NET_POLL_CONTROLLER ++#endif ++ ++#ifndef NETDEV_TX_OK ++#define NETDEV_TX_OK 0 ++#endif ++ ++#ifndef NETDEV_TX_BUSY ++#define NETDEV_TX_BUSY 1 ++#endif ++ ++#ifndef NETDEV_TX_LOCKED ++#define NETDEV_TX_LOCKED -1 ++#endif ++ ++#define VMDQ_P(p) (p) ++ ++#ifndef SKB_DATAREF_SHIFT ++/* if we do not have the infrastructure to detect if skb_header is cloned ++ just return false in all cases */ ++#define skb_header_cloned(x) 0 ++#endif ++ ++#ifndef NETIF_F_GSO ++#define gso_size tso_size ++#define gso_segs tso_segs ++#endif ++ ++#ifndef NETIF_F_GRO ++#define vlan_gro_receive(_napi, _vlgrp, _vlan, _skb) \ ++ vlan_hwaccel_receive_skb(_skb, _vlgrp, _vlan) ++#define napi_gro_receive(_napi, _skb) netif_receive_skb(_skb) ++#endif ++ ++#ifndef NETIF_F_SCTP_CSUM ++#define NETIF_F_SCTP_CSUM 0 ++#endif ++ ++#ifndef CHECKSUM_PARTIAL ++#define CHECKSUM_PARTIAL CHECKSUM_HW ++#define CHECKSUM_COMPLETE CHECKSUM_HW ++#endif ++ ++#ifndef __read_mostly ++#define __read_mostly ++#endif ++ ++#ifndef HAVE_NETIF_MSG ++#define HAVE_NETIF_MSG 1 ++enum { ++ NETIF_MSG_DRV = 0x0001, ++ NETIF_MSG_PROBE = 0x0002, ++ NETIF_MSG_LINK = 0x0004, ++ NETIF_MSG_TIMER = 0x0008, ++ NETIF_MSG_IFDOWN = 0x0010, ++ NETIF_MSG_IFUP = 0x0020, ++ NETIF_MSG_RX_ERR = 0x0040, ++ NETIF_MSG_TX_ERR = 0x0080, ++ NETIF_MSG_TX_QUEUED = 0x0100, ++ NETIF_MSG_INTR = 0x0200, ++ NETIF_MSG_TX_DONE = 0x0400, ++ NETIF_MSG_RX_STATUS = 0x0800, ++ NETIF_MSG_PKTDATA = 0x1000, ++ NETIF_MSG_HW = 0x2000, ++ NETIF_MSG_WOL = 0x4000, ++}; ++ ++#else ++#define NETIF_MSG_HW 0x2000 ++#define NETIF_MSG_WOL 0x4000 ++#endif /* HAVE_NETIF_MSG */ ++ ++#ifndef MII_RESV1 ++#define MII_RESV1 0x17 /* Reserved... */ ++#endif ++ ++#ifndef unlikely ++#define unlikely(_x) _x ++#define likely(_x) _x ++#endif ++ ++#ifndef WARN_ON ++#define WARN_ON(x) ++#endif ++ ++#ifndef PCI_DEVICE ++#define PCI_DEVICE(vend,dev) \ ++ .vendor = (vend), .device = (dev), \ ++ .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID ++#endif ++ ++#ifndef num_online_cpus ++#define num_online_cpus() smp_num_cpus ++#endif ++ ++#ifndef _LINUX_RANDOM_H ++#include ++#endif ++ ++#ifndef DECLARE_BITMAP ++#ifndef BITS_TO_LONGS ++#define BITS_TO_LONGS(bits) (((bits)+BITS_PER_LONG-1)/BITS_PER_LONG) ++#endif ++#define DECLARE_BITMAP(name,bits) long name[BITS_TO_LONGS(bits)] ++#endif ++ ++#ifndef VLAN_HLEN ++#define VLAN_HLEN 4 ++#endif ++ ++#ifndef VLAN_ETH_HLEN ++#define VLAN_ETH_HLEN 18 ++#endif ++ ++#ifndef VLAN_ETH_FRAME_LEN ++#define VLAN_ETH_FRAME_LEN 1518 ++#endif ++ ++#ifndef DCA_GET_TAG_TWO_ARGS ++#define dca3_get_tag(a,b) dca_get_tag(b) ++#endif ++ ++/*****************************************************************************/ ++/* Installations with ethtool version without eeprom, adapter id, or statistics ++ * support */ ++ ++#ifndef ETH_GSTRING_LEN ++#define ETH_GSTRING_LEN 32 ++#endif ++ ++#ifndef ETHTOOL_GSTATS ++#define ETHTOOL_GSTATS 0x1d ++#undef ethtool_drvinfo ++#define ethtool_drvinfo k_ethtool_drvinfo ++struct k_ethtool_drvinfo { ++ u32 cmd; ++ char driver[32]; ++ char version[32]; ++ char fw_version[32]; ++ char bus_info[32]; ++ char reserved1[32]; ++ char reserved2[16]; ++ u32 n_stats; ++ u32 testinfo_len; ++ u32 eedump_len; ++ u32 regdump_len; ++}; ++ ++struct ethtool_stats { ++ u32 cmd; ++ u32 n_stats; ++ u64 data[0]; ++}; ++#endif /* ETHTOOL_GSTATS */ ++ ++#ifndef ETHTOOL_PHYS_ID ++#define ETHTOOL_PHYS_ID 0x1c ++#endif /* ETHTOOL_PHYS_ID */ ++ ++#ifndef ETHTOOL_GSTRINGS ++#define ETHTOOL_GSTRINGS 0x1b ++enum ethtool_stringset { ++ ETH_SS_TEST = 0, ++ ETH_SS_STATS, ++}; ++struct ethtool_gstrings { ++ u32 cmd; /* ETHTOOL_GSTRINGS */ ++ u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/ ++ u32 len; /* number of strings in the string set */ ++ u8 data[0]; ++}; ++#endif /* ETHTOOL_GSTRINGS */ ++ ++#ifndef ETHTOOL_TEST ++#define ETHTOOL_TEST 0x1a ++enum ethtool_test_flags { ++ ETH_TEST_FL_OFFLINE = (1 << 0), ++ ETH_TEST_FL_FAILED = (1 << 1), ++}; ++struct ethtool_test { ++ u32 cmd; ++ u32 flags; ++ u32 reserved; ++ u32 len; ++ u64 data[0]; ++}; ++#endif /* ETHTOOL_TEST */ ++ ++#ifndef ETHTOOL_GEEPROM ++#define ETHTOOL_GEEPROM 0xb ++#undef ETHTOOL_GREGS ++struct ethtool_eeprom { ++ u32 cmd; ++ u32 magic; ++ u32 offset; ++ u32 len; ++ u8 data[0]; ++}; ++ ++struct ethtool_value { ++ u32 cmd; ++ u32 data; ++}; ++#endif /* ETHTOOL_GEEPROM */ ++ ++#ifndef ETHTOOL_GLINK ++#define ETHTOOL_GLINK 0xa ++#endif /* ETHTOOL_GLINK */ ++ ++#ifndef ETHTOOL_GREGS ++#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers */ ++#define ethtool_regs _kc_ethtool_regs ++/* for passing big chunks of data */ ++struct _kc_ethtool_regs { ++ u32 cmd; ++ u32 version; /* driver-specific, indicates different chips/revs */ ++ u32 len; /* bytes */ ++ u8 data[0]; ++}; ++#endif /* ETHTOOL_GREGS */ ++ ++#ifndef ETHTOOL_GMSGLVL ++#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */ ++#endif ++#ifndef ETHTOOL_SMSGLVL ++#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level, priv. */ ++#endif ++#ifndef ETHTOOL_NWAY_RST ++#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation, priv */ ++#endif ++#ifndef ETHTOOL_GLINK ++#define ETHTOOL_GLINK 0x0000000a /* Get link status */ ++#endif ++#ifndef ETHTOOL_GEEPROM ++#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */ ++#endif ++#ifndef ETHTOOL_SEEPROM ++#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */ ++#endif ++#ifndef ETHTOOL_GCOALESCE ++#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */ ++/* for configuring coalescing parameters of chip */ ++#define ethtool_coalesce _kc_ethtool_coalesce ++struct _kc_ethtool_coalesce { ++ u32 cmd; /* ETHTOOL_{G,S}COALESCE */ ++ ++ /* How many usecs to delay an RX interrupt after ++ * a packet arrives. If 0, only rx_max_coalesced_frames ++ * is used. ++ */ ++ u32 rx_coalesce_usecs; ++ ++ /* How many packets to delay an RX interrupt after ++ * a packet arrives. If 0, only rx_coalesce_usecs is ++ * used. It is illegal to set both usecs and max frames ++ * to zero as this would cause RX interrupts to never be ++ * generated. ++ */ ++ u32 rx_max_coalesced_frames; ++ ++ /* Same as above two parameters, except that these values ++ * apply while an IRQ is being serviced by the host. Not ++ * all cards support this feature and the values are ignored ++ * in that case. ++ */ ++ u32 rx_coalesce_usecs_irq; ++ u32 rx_max_coalesced_frames_irq; ++ ++ /* How many usecs to delay a TX interrupt after ++ * a packet is sent. If 0, only tx_max_coalesced_frames ++ * is used. ++ */ ++ u32 tx_coalesce_usecs; ++ ++ /* How many packets to delay a TX interrupt after ++ * a packet is sent. If 0, only tx_coalesce_usecs is ++ * used. It is illegal to set both usecs and max frames ++ * to zero as this would cause TX interrupts to never be ++ * generated. ++ */ ++ u32 tx_max_coalesced_frames; ++ ++ /* Same as above two parameters, except that these values ++ * apply while an IRQ is being serviced by the host. Not ++ * all cards support this feature and the values are ignored ++ * in that case. ++ */ ++ u32 tx_coalesce_usecs_irq; ++ u32 tx_max_coalesced_frames_irq; ++ ++ /* How many usecs to delay in-memory statistics ++ * block updates. Some drivers do not have an in-memory ++ * statistic block, and in such cases this value is ignored. ++ * This value must not be zero. ++ */ ++ u32 stats_block_coalesce_usecs; ++ ++ /* Adaptive RX/TX coalescing is an algorithm implemented by ++ * some drivers to improve latency under low packet rates and ++ * improve throughput under high packet rates. Some drivers ++ * only implement one of RX or TX adaptive coalescing. Anything ++ * not implemented by the driver causes these values to be ++ * silently ignored. ++ */ ++ u32 use_adaptive_rx_coalesce; ++ u32 use_adaptive_tx_coalesce; ++ ++ /* When the packet rate (measured in packets per second) ++ * is below pkt_rate_low, the {rx,tx}_*_low parameters are ++ * used. ++ */ ++ u32 pkt_rate_low; ++ u32 rx_coalesce_usecs_low; ++ u32 rx_max_coalesced_frames_low; ++ u32 tx_coalesce_usecs_low; ++ u32 tx_max_coalesced_frames_low; ++ ++ /* When the packet rate is below pkt_rate_high but above ++ * pkt_rate_low (both measured in packets per second) the ++ * normal {rx,tx}_* coalescing parameters are used. ++ */ ++ ++ /* When the packet rate is (measured in packets per second) ++ * is above pkt_rate_high, the {rx,tx}_*_high parameters are ++ * used. ++ */ ++ u32 pkt_rate_high; ++ u32 rx_coalesce_usecs_high; ++ u32 rx_max_coalesced_frames_high; ++ u32 tx_coalesce_usecs_high; ++ u32 tx_max_coalesced_frames_high; ++ ++ /* How often to do adaptive coalescing packet rate sampling, ++ * measured in seconds. Must not be zero. ++ */ ++ u32 rate_sample_interval; ++}; ++#endif /* ETHTOOL_GCOALESCE */ ++ ++#ifndef ETHTOOL_SCOALESCE ++#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */ ++#endif ++#ifndef ETHTOOL_GRINGPARAM ++#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */ ++/* for configuring RX/TX ring parameters */ ++#define ethtool_ringparam _kc_ethtool_ringparam ++struct _kc_ethtool_ringparam { ++ u32 cmd; /* ETHTOOL_{G,S}RINGPARAM */ ++ ++ /* Read only attributes. These indicate the maximum number ++ * of pending RX/TX ring entries the driver will allow the ++ * user to set. ++ */ ++ u32 rx_max_pending; ++ u32 rx_mini_max_pending; ++ u32 rx_jumbo_max_pending; ++ u32 tx_max_pending; ++ ++ /* Values changeable by the user. The valid values are ++ * in the range 1 to the "*_max_pending" counterpart above. ++ */ ++ u32 rx_pending; ++ u32 rx_mini_pending; ++ u32 rx_jumbo_pending; ++ u32 tx_pending; ++}; ++#endif /* ETHTOOL_GRINGPARAM */ ++ ++#ifndef ETHTOOL_SRINGPARAM ++#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters, priv. */ ++#endif ++#ifndef ETHTOOL_GPAUSEPARAM ++#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */ ++/* for configuring link flow control parameters */ ++#define ethtool_pauseparam _kc_ethtool_pauseparam ++struct _kc_ethtool_pauseparam { ++ u32 cmd; /* ETHTOOL_{G,S}PAUSEPARAM */ ++ ++ /* If the link is being auto-negotiated (via ethtool_cmd.autoneg ++ * being true) the user may set 'autoneg' here non-zero to have the ++ * pause parameters be auto-negotiated too. In such a case, the ++ * {rx,tx}_pause values below determine what capabilities are ++ * advertised. ++ * ++ * If 'autoneg' is zero or the link is not being auto-negotiated, ++ * then {rx,tx}_pause force the driver to use/not-use pause ++ * flow control. ++ */ ++ u32 autoneg; ++ u32 rx_pause; ++ u32 tx_pause; ++}; ++#endif /* ETHTOOL_GPAUSEPARAM */ ++ ++#ifndef ETHTOOL_SPAUSEPARAM ++#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */ ++#endif ++#ifndef ETHTOOL_GRXCSUM ++#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_SRXCSUM ++#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_GTXCSUM ++#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_STXCSUM ++#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_GSG ++#define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable ++ * (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_SSG ++#define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable ++ * (ethtool_value). */ ++#endif ++#ifndef ETHTOOL_TEST ++#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test, priv. */ ++#endif ++#ifndef ETHTOOL_GSTRINGS ++#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */ ++#endif ++#ifndef ETHTOOL_PHYS_ID ++#define ETHTOOL_PHYS_ID 0x0000001c /* identify the NIC */ ++#endif ++#ifndef ETHTOOL_GSTATS ++#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */ ++#endif ++#ifndef ETHTOOL_GTSO ++#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */ ++#endif ++#ifndef ETHTOOL_STSO ++#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */ ++#endif ++ ++#ifndef ETHTOOL_BUSINFO_LEN ++#define ETHTOOL_BUSINFO_LEN 32 ++#endif ++ ++/*****************************************************************************/ ++/* 2.4.3 => 2.4.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) ) ++ ++/**************************************/ ++/* PCI DRIVER API */ ++ ++#ifndef pci_set_dma_mask ++#define pci_set_dma_mask _kc_pci_set_dma_mask ++extern int _kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask); ++#endif ++ ++#ifndef pci_request_regions ++#define pci_request_regions _kc_pci_request_regions ++extern int _kc_pci_request_regions(struct pci_dev *pdev, char *res_name); ++#endif ++ ++#ifndef pci_release_regions ++#define pci_release_regions _kc_pci_release_regions ++extern void _kc_pci_release_regions(struct pci_dev *pdev); ++#endif ++ ++/**************************************/ ++/* NETWORK DRIVER API */ ++ ++#ifndef alloc_etherdev ++#define alloc_etherdev _kc_alloc_etherdev ++extern struct net_device * _kc_alloc_etherdev(int sizeof_priv); ++#endif ++ ++#ifndef is_valid_ether_addr ++#define is_valid_ether_addr _kc_is_valid_ether_addr ++extern int _kc_is_valid_ether_addr(u8 *addr); ++#endif ++ ++/**************************************/ ++/* MISCELLANEOUS */ ++ ++#ifndef INIT_TQUEUE ++#define INIT_TQUEUE(_tq, _routine, _data) \ ++ do { \ ++ INIT_LIST_HEAD(&(_tq)->list); \ ++ (_tq)->sync = 0; \ ++ (_tq)->routine = _routine; \ ++ (_tq)->data = _data; \ ++ } while (0) ++#endif ++ ++#endif /* 2.4.3 => 2.4.0 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,5) ) ++/* Generic MII registers. */ ++#define MII_BMCR 0x00 /* Basic mode control register */ ++#define MII_BMSR 0x01 /* Basic mode status register */ ++#define MII_PHYSID1 0x02 /* PHYS ID 1 */ ++#define MII_PHYSID2 0x03 /* PHYS ID 2 */ ++#define MII_ADVERTISE 0x04 /* Advertisement control reg */ ++#define MII_LPA 0x05 /* Link partner ability reg */ ++#define MII_EXPANSION 0x06 /* Expansion register */ ++/* Basic mode control register. */ ++#define BMCR_FULLDPLX 0x0100 /* Full duplex */ ++#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ ++/* Basic mode status register. */ ++#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ ++#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ ++#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ ++#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ ++#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ ++#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ ++/* Advertisement control register. */ ++#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ ++#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ ++#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ ++#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ ++#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ ++#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ++ ADVERTISE_100HALF | ADVERTISE_100FULL) ++/* Expansion register for auto-negotiation. */ ++#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ ++#endif ++ ++/*****************************************************************************/ ++/* 2.4.6 => 2.4.3 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) ) ++ ++#ifndef pci_set_power_state ++#define pci_set_power_state _kc_pci_set_power_state ++extern int _kc_pci_set_power_state(struct pci_dev *dev, int state); ++#endif ++ ++#ifndef pci_enable_wake ++#define pci_enable_wake _kc_pci_enable_wake ++extern int _kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable); ++#endif ++ ++#ifndef pci_disable_device ++#define pci_disable_device _kc_pci_disable_device ++extern void _kc_pci_disable_device(struct pci_dev *pdev); ++#endif ++ ++/* PCI PM entry point syntax changed, so don't support suspend/resume */ ++#undef CONFIG_PM ++ ++#endif /* 2.4.6 => 2.4.3 */ ++ ++#ifndef HAVE_PCI_SET_MWI ++#define pci_set_mwi(X) pci_write_config_word(X, \ ++ PCI_COMMAND, adapter->hw.bus.pci_cmd_word | \ ++ PCI_COMMAND_INVALIDATE); ++#define pci_clear_mwi(X) pci_write_config_word(X, \ ++ PCI_COMMAND, adapter->hw.bus.pci_cmd_word & \ ++ ~PCI_COMMAND_INVALIDATE); ++#endif ++ ++/*****************************************************************************/ ++/* 2.4.10 => 2.4.9 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,10) ) ++ ++/**************************************/ ++/* MODULE API */ ++ ++#ifndef MODULE_LICENSE ++ #define MODULE_LICENSE(X) ++#endif ++ ++/**************************************/ ++/* OTHER */ ++ ++#undef min ++#define min(x,y) ({ \ ++ const typeof(x) _x = (x); \ ++ const typeof(y) _y = (y); \ ++ (void) (&_x == &_y); \ ++ _x < _y ? _x : _y; }) ++ ++#undef max ++#define max(x,y) ({ \ ++ const typeof(x) _x = (x); \ ++ const typeof(y) _y = (y); \ ++ (void) (&_x == &_y); \ ++ _x > _y ? _x : _y; }) ++ ++#define min_t(type,x,y) ({ \ ++ type _x = (x); \ ++ type _y = (y); \ ++ _x < _y ? _x : _y; }) ++ ++#define max_t(type,x,y) ({ \ ++ type _x = (x); \ ++ type _y = (y); \ ++ _x > _y ? _x : _y; }) ++ ++#ifndef list_for_each_safe ++#define list_for_each_safe(pos, n, head) \ ++ for (pos = (head)->next, n = pos->next; pos != (head); \ ++ pos = n, n = pos->next) ++#endif ++ ++#endif /* 2.4.10 -> 2.4.6 */ ++ ++ ++/*****************************************************************************/ ++/* 2.4.13 => 2.4.10 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) ) ++ ++/**************************************/ ++/* PCI DMA MAPPING */ ++ ++#ifndef virt_to_page ++ #define virt_to_page(v) (mem_map + (virt_to_phys(v) >> PAGE_SHIFT)) ++#endif ++ ++#ifndef pci_map_page ++#define pci_map_page _kc_pci_map_page ++extern u64 _kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, size_t size, int direction); ++#endif ++ ++#ifndef pci_unmap_page ++#define pci_unmap_page _kc_pci_unmap_page ++extern void _kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, int direction); ++#endif ++ ++/* pci_set_dma_mask takes dma_addr_t, which is only 32-bits prior to 2.4.13 */ ++ ++#undef DMA_32BIT_MASK ++#define DMA_32BIT_MASK 0xffffffff ++#undef DMA_64BIT_MASK ++#define DMA_64BIT_MASK 0xffffffff ++ ++/**************************************/ ++/* OTHER */ ++ ++#ifndef cpu_relax ++#define cpu_relax() rep_nop() ++#endif ++ ++struct vlan_ethhdr { ++ unsigned char h_dest[ETH_ALEN]; ++ unsigned char h_source[ETH_ALEN]; ++ unsigned short h_vlan_proto; ++ unsigned short h_vlan_TCI; ++ unsigned short h_vlan_encapsulated_proto; ++}; ++#endif /* 2.4.13 => 2.4.10 */ ++ ++/*****************************************************************************/ ++/* 2.4.17 => 2.4.12 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17) ) ++ ++#ifndef __devexit_p ++ #define __devexit_p(x) &(x) ++#endif ++ ++#endif /* 2.4.17 => 2.4.13 */ ++ ++/*****************************************************************************/ ++/* 2.4.20 => 2.4.19 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,20) ) ++ ++/* we won't support NAPI on less than 2.4.20 */ ++#ifdef NAPI ++#undef NAPI ++#undef CONFIG_IXGBE_NAPI ++#endif ++ ++#endif /* 2.4.20 => 2.4.19 */ ++ ++/*****************************************************************************/ ++/* < 2.4.21 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,21) ) ++#define skb_pad(x,y) _kc_skb_pad(x, y) ++struct sk_buff * _kc_skb_pad(struct sk_buff *skb, int pad); ++#endif /* < 2.4.21 */ ++ ++/*****************************************************************************/ ++/* 2.4.22 => 2.4.17 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) ) ++#define pci_name(x) ((x)->slot_name) ++#endif ++ ++/*****************************************************************************/ ++/* 2.4.22 => 2.4.17 */ ++ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) ) ++#ifndef IXGBE_NO_LRO ++/* Don't enable LRO for these legacy kernels */ ++#define IXGBE_NO_LRO ++#endif ++#endif ++ ++/*****************************************************************************/ ++/*****************************************************************************/ ++/* 2.4.23 => 2.4.22 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23) ) ++/*****************************************************************************/ ++#ifdef NAPI ++#ifndef netif_poll_disable ++#define netif_poll_disable(x) _kc_netif_poll_disable(x) ++static inline void _kc_netif_poll_disable(struct net_device *netdev) ++{ ++ while (test_and_set_bit(__LINK_STATE_RX_SCHED, &netdev->state)) { ++ /* No hurry */ ++ current->state = TASK_INTERRUPTIBLE; ++ schedule_timeout(1); ++ } ++} ++#endif ++ ++#ifndef netif_poll_enable ++#define netif_poll_enable(x) _kc_netif_poll_enable(x) ++static inline void _kc_netif_poll_enable(struct net_device *netdev) ++{ ++ clear_bit(__LINK_STATE_RX_SCHED, &netdev->state); ++} ++#endif ++#endif /* NAPI */ ++#ifndef netif_tx_disable ++#define netif_tx_disable(x) _kc_netif_tx_disable(x) ++static inline void _kc_netif_tx_disable(struct net_device *dev) ++{ ++ spin_lock_bh(&dev->xmit_lock); ++ netif_stop_queue(dev); ++ spin_unlock_bh(&dev->xmit_lock); ++} ++#endif ++#endif /* 2.4.23 => 2.4.22 */ ++ ++/*****************************************************************************/ ++/* 2.6.4 => 2.6.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,25) || \ ++ ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \ ++ LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) ) ++#define ETHTOOL_OPS_COMPAT ++#endif /* 2.6.4 => 2.6.0 */ ++ ++/*****************************************************************************/ ++/* 2.5.71 => 2.4.x */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,71) ) ++#define sk_protocol protocol ++#define pci_get_device pci_find_device ++#endif /* 2.5.70 => 2.4.x */ ++ ++/*****************************************************************************/ ++/* < 2.4.27 or 2.6.0 <= 2.6.5 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) || \ ++ ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \ ++ LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) ) ++ ++#ifndef netif_msg_init ++#define netif_msg_init _kc_netif_msg_init ++static inline u32 _kc_netif_msg_init(int debug_value, int default_msg_enable_bits) ++{ ++ /* use default */ ++ if (debug_value < 0 || debug_value >= (sizeof(u32) * 8)) ++ return default_msg_enable_bits; ++ if (debug_value == 0) /* no output */ ++ return 0; ++ /* set low N bits */ ++ return (1 << debug_value) -1; ++} ++#endif ++ ++#endif /* < 2.4.27 or 2.6.0 <= 2.6.5 */ ++/*****************************************************************************/ ++#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \ ++ (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \ ++ ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) ))) ++#define netdev_priv(x) x->priv ++#endif ++ ++/*****************************************************************************/ ++/* <= 2.5.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ) ++#undef pci_register_driver ++#define pci_register_driver pci_module_init ++ ++#define dev_err(__unused_dev, format, arg...) \ ++ printk(KERN_ERR "%s: " format, pci_name(adapter->pdev) , ## arg) ++#define dev_warn(__unused_dev, format, arg...) \ ++ printk(KERN_WARNING "%s: " format, pci_name(pdev) , ## arg) ++ ++/* hlist_* code - double linked lists */ ++struct hlist_head { ++ struct hlist_node *first; ++}; ++ ++struct hlist_node { ++ struct hlist_node *next, **pprev; ++}; ++ ++static inline void __hlist_del(struct hlist_node *n) ++{ ++ struct hlist_node *next = n->next; ++ struct hlist_node **pprev = n->pprev; ++ *pprev = next; ++ if (next) ++ next->pprev = pprev; ++} ++ ++static inline void hlist_del(struct hlist_node *n) ++{ ++ __hlist_del(n); ++ n->next = NULL; ++ n->pprev = NULL; ++} ++ ++static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) ++{ ++ struct hlist_node *first = h->first; ++ n->next = first; ++ if (first) ++ first->pprev = &n->next; ++ h->first = n; ++ n->pprev = &h->first; ++} ++ ++static inline int hlist_empty(const struct hlist_head *h) ++{ ++ return !h->first; ++} ++#define HLIST_HEAD_INIT { .first = NULL } ++#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL } ++#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL) ++static inline void INIT_HLIST_NODE(struct hlist_node *h) ++{ ++ h->next = NULL; ++ h->pprev = NULL; ++} ++#define hlist_entry(ptr, type, member) container_of(ptr,type,member) ++ ++#define hlist_for_each_entry(tpos, pos, head, member) \ ++ for (pos = (head)->first; \ ++ pos && ({ prefetch(pos->next); 1;}) && \ ++ ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ ++ pos = pos->next) ++ ++#define hlist_for_each_entry_safe(tpos, pos, n, head, member) \ ++ for (pos = (head)->first; \ ++ pos && ({ n = pos->next; 1; }) && \ ++ ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ ++ pos = n) ++ ++/* we ignore GFP here */ ++#define dma_alloc_coherent(dv, sz, dma, gfp) \ ++ pci_alloc_consistent(pdev, (sz), (dma)) ++#define dma_free_coherent(dv, sz, addr, dma_addr) \ ++ pci_free_consistent(pdev, (sz), (addr), (dma_addr)) ++ ++#ifndef might_sleep ++#define might_sleep() ++#endif ++ ++#endif /* <= 2.5.0 */ ++ ++/*****************************************************************************/ ++/* 2.5.28 => 2.4.23 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) ) ++ ++static inline void _kc_synchronize_irq(void) ++{ ++ synchronize_irq(); ++} ++#undef synchronize_irq ++#define synchronize_irq(X) _kc_synchronize_irq() ++ ++#include ++#define work_struct tq_struct ++#undef INIT_WORK ++#define INIT_WORK(a,b) INIT_TQUEUE(a,(void (*)(void *))b,a) ++#undef container_of ++#define container_of list_entry ++#define schedule_work schedule_task ++#define flush_scheduled_work flush_scheduled_tasks ++#define cancel_work_sync(x) flush_scheduled_work() ++ ++#endif /* 2.5.28 => 2.4.17 */ ++ ++/*****************************************************************************/ ++/* 2.6.0 => 2.5.28 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) ++#define MODULE_INFO(version, _version) ++#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT ++#define CONFIG_E1000_DISABLE_PACKET_SPLIT 1 ++#endif ++#define CONFIG_IGB_DISABLE_PACKET_SPLIT 1 ++ ++#define pci_set_consistent_dma_mask(dev,mask) 1 ++ ++#undef dev_put ++#define dev_put(dev) __dev_put(dev) ++ ++#ifndef skb_fill_page_desc ++#define skb_fill_page_desc _kc_skb_fill_page_desc ++extern void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int off, int size); ++#endif ++ ++#undef ALIGN ++#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1)) ++ ++#ifndef page_count ++#define page_count(p) atomic_read(&(p)->count) ++#endif ++ ++/* find_first_bit and find_next bit are not defined for most ++ * 2.4 kernels (except for the redhat 2.4.21 kernels ++ */ ++#include ++#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG) ++#undef find_next_bit ++#define find_next_bit _kc_find_next_bit ++extern unsigned long _kc_find_next_bit(const unsigned long *addr, ++ unsigned long size, ++ unsigned long offset); ++#define find_first_bit(addr, size) find_next_bit((addr), (size), 0) ++ ++#endif /* 2.6.0 => 2.5.28 */ ++ ++/*****************************************************************************/ ++/* 2.6.4 => 2.6.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) ++#define MODULE_VERSION(_version) MODULE_INFO(version, _version) ++#endif /* 2.6.4 => 2.6.0 */ ++ ++/*****************************************************************************/ ++/* 2.6.5 => 2.6.0 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) ++#define pci_dma_sync_single_for_cpu pci_dma_sync_single ++#define pci_dma_sync_single_for_device pci_dma_sync_single_for_cpu ++#endif /* 2.6.5 => 2.6.0 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,6) ) ++/* taken from 2.6 include/linux/bitmap.h */ ++#undef bitmap_zero ++#define bitmap_zero _kc_bitmap_zero ++static inline void _kc_bitmap_zero(unsigned long *dst, int nbits) ++{ ++ if (nbits <= BITS_PER_LONG) ++ *dst = 0UL; ++ else { ++ int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long); ++ memset(dst, 0, len); ++ } ++} ++#define random_ether_addr _kc_random_ether_addr ++static inline void _kc_random_ether_addr(u8 *addr) ++{ ++ get_random_bytes(addr, ETH_ALEN); ++ addr[0] &= 0xfe; /* clear multicast */ ++ addr[0] |= 0x02; /* set local assignment */ ++} ++#endif /* < 2.6.6 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) ) ++#undef if_mii ++#define if_mii _kc_if_mii ++static inline struct mii_ioctl_data *_kc_if_mii(struct ifreq *rq) ++{ ++ return (struct mii_ioctl_data *) &rq->ifr_ifru; ++} ++#endif /* < 2.6.7 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) ) ++#ifndef PCI_EXP_DEVCTL ++#define PCI_EXP_DEVCTL 8 ++#endif ++#ifndef PCI_EXP_DEVCTL_CERE ++#define PCI_EXP_DEVCTL_CERE 0x0001 ++#endif ++#define msleep(x) do { set_current_state(TASK_UNINTERRUPTIBLE); \ ++ schedule_timeout((x * HZ)/1000 + 2); \ ++ } while (0) ++ ++#endif /* < 2.6.8 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)) ++#include ++#define __iomem ++ ++#ifndef kcalloc ++#define kcalloc(n, size, flags) _kc_kzalloc(((n) * (size)), flags) ++extern void *_kc_kzalloc(size_t size, int flags); ++#endif ++#define MSEC_PER_SEC 1000L ++static inline unsigned int _kc_jiffies_to_msecs(const unsigned long j) ++{ ++#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) ++ return (MSEC_PER_SEC / HZ) * j; ++#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) ++ return (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC); ++#else ++ return (j * MSEC_PER_SEC) / HZ; ++#endif ++} ++static inline unsigned long _kc_msecs_to_jiffies(const unsigned int m) ++{ ++ if (m > _kc_jiffies_to_msecs(MAX_JIFFY_OFFSET)) ++ return MAX_JIFFY_OFFSET; ++#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) ++ return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ); ++#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) ++ return m * (HZ / MSEC_PER_SEC); ++#else ++ return (m * HZ + MSEC_PER_SEC - 1) / MSEC_PER_SEC; ++#endif ++} ++ ++#define msleep_interruptible _kc_msleep_interruptible ++static inline unsigned long _kc_msleep_interruptible(unsigned int msecs) ++{ ++ unsigned long timeout = _kc_msecs_to_jiffies(msecs) + 1; ++ ++ while (timeout && !signal_pending(current)) { ++ __set_current_state(TASK_INTERRUPTIBLE); ++ timeout = schedule_timeout(timeout); ++ } ++ return _kc_jiffies_to_msecs(timeout); ++} ++ ++/* Basic mode control register. */ ++#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ ++ ++#ifndef __le16 ++#define __le16 u16 ++#endif ++#ifndef __le32 ++#define __le32 u32 ++#endif ++#ifndef __le64 ++#define __le64 u64 ++#endif ++#ifndef __be16 ++#define __be16 u16 ++#endif ++ ++#ifdef pci_dma_mapping_error ++#undef pci_dma_mapping_error ++#endif ++#define pci_dma_mapping_error _kc_pci_dma_mapping_error ++static inline int _kc_pci_dma_mapping_error(struct pci_dev *pdev, ++ dma_addr_t dma_addr) ++{ ++ return dma_addr == 0; ++} ++#endif /* < 2.6.9 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ) ++#ifdef module_param_array_named ++#undef module_param_array_named ++#define module_param_array_named(name, array, type, nump, perm) \ ++ static struct kparam_array __param_arr_##name \ ++ = { ARRAY_SIZE(array), nump, param_set_##type, param_get_##type, \ ++ sizeof(array[0]), array }; \ ++ module_param_call(name, param_array_set, param_array_get, \ ++ &__param_arr_##name, perm) ++#endif /* module_param_array_named */ ++#endif /* < 2.6.10 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) ) ++#define PCI_D0 0 ++#define PCI_D1 1 ++#define PCI_D2 2 ++#define PCI_D3hot 3 ++#define PCI_D3cold 4 ++typedef int pci_power_t; ++#define pci_choose_state(pdev,state) state ++#define PMSG_SUSPEND 3 ++#define PCI_EXP_LNKCTL 16 ++ ++#undef NETIF_F_LLTX ++ ++#ifndef ARCH_HAS_PREFETCH ++#define prefetch(X) ++#endif ++ ++#ifndef NET_IP_ALIGN ++#define NET_IP_ALIGN 2 ++#endif ++ ++#define KC_USEC_PER_SEC 1000000L ++#define usecs_to_jiffies _kc_usecs_to_jiffies ++static inline unsigned int _kc_jiffies_to_usecs(const unsigned long j) ++{ ++#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ) ++ return (KC_USEC_PER_SEC / HZ) * j; ++#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC) ++ return (j + (HZ / KC_USEC_PER_SEC) - 1)/(HZ / KC_USEC_PER_SEC); ++#else ++ return (j * KC_USEC_PER_SEC) / HZ; ++#endif ++} ++static inline unsigned long _kc_usecs_to_jiffies(const unsigned int m) ++{ ++ if (m > _kc_jiffies_to_usecs(MAX_JIFFY_OFFSET)) ++ return MAX_JIFFY_OFFSET; ++#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ) ++ return (m + (KC_USEC_PER_SEC / HZ) - 1) / (KC_USEC_PER_SEC / HZ); ++#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC) ++ return m * (HZ / KC_USEC_PER_SEC); ++#else ++ return (m * HZ + KC_USEC_PER_SEC - 1) / KC_USEC_PER_SEC; ++#endif ++} ++#endif /* < 2.6.11 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,12) ) ++#include ++#define USE_REBOOT_NOTIFIER ++ ++/* Generic MII registers. */ ++#define MII_CTRL1000 0x09 /* 1000BASE-T control */ ++#define MII_STAT1000 0x0a /* 1000BASE-T status */ ++/* Advertisement control register. */ ++#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ ++#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymmetric pause */ ++/* 1000BASE-T Control register */ ++#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ ++#endif /* < 2.6.12 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) ) ++#define pm_message_t u32 ++#ifndef kzalloc ++#define kzalloc _kc_kzalloc ++extern void *_kc_kzalloc(size_t size, int flags); ++#endif ++ ++/* Generic MII registers. */ ++#define MII_ESTATUS 0x0f /* Extended Status */ ++/* Basic mode status register. */ ++#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ ++/* Extended status register. */ ++#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ ++#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ ++#endif /* < 2.6.14 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) ) ++#ifndef device_can_wakeup ++#define device_can_wakeup(dev) (1) ++#endif ++#ifndef device_set_wakeup_enable ++#define device_set_wakeup_enable(dev, val) do{}while(0) ++#endif ++#ifndef device_init_wakeup ++#define device_init_wakeup(dev,val) do {} while (0) ++#endif ++#endif /* < 2.6.15 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) ) ++#undef DEFINE_MUTEX ++#define DEFINE_MUTEX(x) DECLARE_MUTEX(x) ++#define mutex_lock(x) down_interruptible(x) ++#define mutex_unlock(x) up(x) ++ ++#undef HAVE_PCI_ERS ++#else /* 2.6.16 and above */ ++#undef HAVE_PCI_ERS ++#define HAVE_PCI_ERS ++#endif /* < 2.6.16 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ) ++ ++#ifndef IRQ_HANDLED ++#define irqreturn_t void ++#define IRQ_HANDLED ++#define IRQ_NONE ++#endif ++ ++#ifndef IRQF_PROBE_SHARED ++#ifdef SA_PROBEIRQ ++#define IRQF_PROBE_SHARED SA_PROBEIRQ ++#else ++#define IRQF_PROBE_SHARED 0 ++#endif ++#endif ++ ++#ifndef IRQF_SHARED ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#ifndef ARRAY_SIZE ++#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) ++#endif ++ ++#ifndef netdev_alloc_skb ++#define netdev_alloc_skb _kc_netdev_alloc_skb ++extern struct sk_buff *_kc_netdev_alloc_skb(struct net_device *dev, ++ unsigned int length); ++#endif ++ ++#ifndef skb_is_gso ++#ifdef NETIF_F_TSO ++#define skb_is_gso _kc_skb_is_gso ++static inline int _kc_skb_is_gso(const struct sk_buff *skb) ++{ ++ return skb_shinfo(skb)->gso_size; ++} ++#else ++#define skb_is_gso(a) 0 ++#endif ++#endif ++ ++#endif /* < 2.6.18 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ) ++ ++#ifndef DIV_ROUND_UP ++#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) ++#endif ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) ) ++#ifndef RHEL_RELEASE_CODE ++#define RHEL_RELEASE_CODE 0 ++#endif ++#ifndef RHEL_RELEASE_VERSION ++#define RHEL_RELEASE_VERSION(a,b) 0 ++#endif ++#ifndef AX_RELEASE_CODE ++#define AX_RELEASE_CODE 0 ++#endif ++#ifndef AX_RELEASE_VERSION ++#define AX_RELEASE_VERSION(a,b) 0 ++#endif ++#if (!(( RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,4) ) && ( RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0) ) || ( RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,0) ) || (AX_RELEASE_CODE > AX_RELEASE_VERSION(3,0)))) ++typedef irqreturn_t (*irq_handler_t)(int, void*, struct pt_regs *); ++#endif ++#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0)) ++#undef CONFIG_INET_LRO ++#undef CONFIG_INET_LRO_MODULE ++#undef CONFIG_FCOE ++#undef CONFIG_FCOE_MODULE ++#endif ++typedef irqreturn_t (*new_handler_t)(int, void*); ++static inline irqreturn_t _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id) ++#else /* 2.4.x */ ++typedef void (*irq_handler_t)(int, void*, struct pt_regs *); ++typedef void (*new_handler_t)(int, void*); ++static inline int _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id) ++#endif /* >= 2.5.x */ ++{ ++ irq_handler_t new_handler = (irq_handler_t) handler; ++ return request_irq(irq, new_handler, flags, devname, dev_id); ++} ++ ++#undef request_irq ++#define request_irq(irq, handler, flags, devname, dev_id) _kc_request_irq((irq), (handler), (flags), (devname), (dev_id)) ++ ++#define irq_handler_t new_handler_t ++/* pci_restore_state and pci_save_state handles MSI/PCIE from 2.6.19 */ ++#define PCIE_CONFIG_SPACE_LEN 256 ++#define PCI_CONFIG_SPACE_LEN 64 ++#define PCIE_LINK_STATUS 0x12 ++#define pci_config_space_ich8lan() do {} while(0) ++#undef pci_save_state ++extern int _kc_pci_save_state(struct pci_dev *); ++#define pci_save_state(pdev) _kc_pci_save_state(pdev) ++#undef pci_restore_state ++extern void _kc_pci_restore_state(struct pci_dev *); ++#define pci_restore_state(pdev) _kc_pci_restore_state(pdev) ++#ifdef HAVE_PCI_ERS ++#undef free_netdev ++extern void _kc_free_netdev(struct net_device *); ++#define free_netdev(netdev) _kc_free_netdev(netdev) ++#endif ++static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev) ++{ ++ return 0; ++} ++#define pci_disable_pcie_error_reporting(dev) do {} while (0) ++#define pci_cleanup_aer_uncorrect_error_status(dev) do {} while (0) ++#else /* 2.6.19 */ ++#include ++#endif /* < 2.6.19 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ) ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,28) ) ++#undef INIT_WORK ++#define INIT_WORK(_work, _func) \ ++do { \ ++ INIT_LIST_HEAD(&(_work)->entry); \ ++ (_work)->pending = 0; \ ++ (_work)->func = (void (*)(void *))_func; \ ++ (_work)->data = _work; \ ++ init_timer(&(_work)->timer); \ ++} while (0) ++#endif ++ ++#ifndef PCI_VDEVICE ++#define PCI_VDEVICE(ven, dev) \ ++ PCI_VENDOR_ID_##ven, (dev), \ ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0 ++#endif ++ ++#ifndef round_jiffies ++#define round_jiffies(x) x ++#endif ++ ++#define csum_offset csum ++ ++#endif /* < 2.6.20 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) ) ++#define to_net_dev(class) container_of(class, struct net_device, class_dev) ++#define NETDEV_CLASS_DEV ++#define vlan_group_get_device(vg, id) (vg->vlan_devices[id]) ++#define vlan_group_set_device(vg, id, dev) if (vg) vg->vlan_devices[id] = dev; ++#define pci_channel_offline(pdev) (pdev->error_state && \ ++ pdev->error_state != pci_channel_io_normal) ++#define pci_request_selected_regions(pdev, bars, name) \ ++ pci_request_regions(pdev, name) ++#define pci_release_selected_regions(pdev, bars) pci_release_regions(pdev); ++#endif /* < 2.6.21 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) ) ++#define tcp_hdr(skb) (skb->h.th) ++#define tcp_hdrlen(skb) (skb->h.th->doff << 2) ++#define skb_transport_offset(skb) (skb->h.raw - skb->data) ++#define skb_transport_header(skb) (skb->h.raw) ++#define ipv6_hdr(skb) (skb->nh.ipv6h) ++#define ip_hdr(skb) (skb->nh.iph) ++#define skb_network_offset(skb) (skb->nh.raw - skb->data) ++#define skb_network_header(skb) (skb->nh.raw) ++#define skb_tail_pointer(skb) skb->tail ++#define skb_copy_to_linear_data_offset(skb, offset, from, len) \ ++ memcpy(skb->data + offset, from, len) ++#define skb_network_header_len(skb) (skb->h.raw - skb->nh.raw) ++#define pci_register_driver pci_module_init ++#define skb_mac_header(skb) skb->mac.raw ++ ++#ifdef NETIF_F_MULTI_QUEUE ++#ifndef alloc_etherdev_mq ++#define alloc_etherdev_mq(_a, _b) alloc_etherdev(_a) ++#endif ++#endif /* NETIF_F_MULTI_QUEUE */ ++ ++#ifndef ETH_FCS_LEN ++#define ETH_FCS_LEN 4 ++#endif ++#define cancel_work_sync(x) flush_scheduled_work() ++#ifndef udp_hdr ++#define udp_hdr _udp_hdr ++static inline struct udphdr *_udp_hdr(const struct sk_buff *skb) ++{ ++ return (struct udphdr *)skb_transport_header(skb); ++} ++#endif ++#else /* 2.6.22 */ ++#define ETH_TYPE_TRANS_SETS_DEV ++#endif /* < 2.6.22 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) ) ++#undef ETHTOOL_GPERMADDR ++#endif /* > 2.6.22 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ) ++#define netif_subqueue_stopped(_a, _b) 0 ++#endif /* < 2.6.23 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ) ++/* if GRO is supported then the napi struct must already exist */ ++#ifndef NETIF_F_GRO ++/* NAPI API changes in 2.6.24 break everything */ ++struct napi_struct { ++ /* used to look up the real NAPI polling routine */ ++ int (*poll)(struct napi_struct *, int); ++ struct net_device *dev; ++ int weight; ++}; ++#endif ++ ++#ifdef NAPI ++extern int __kc_adapter_clean(struct net_device *, int *); ++extern struct net_device *napi_to_poll_dev(struct napi_struct *napi); ++#define napi_enable(napi) do { \ ++ struct napi_struct *_napi = (napi); \ ++ /* abuse if_port as a counter */ \ ++ if (!_napi->dev->if_port) { \ ++ netif_poll_enable(_napi->dev); \ ++ } \ ++ ++_napi->dev->if_port; \ ++ netif_poll_enable(napi_to_poll_dev(_napi)); \ ++ } while (0) ++#define napi_disable(napi) do { \ ++ struct napi_struct *_napi = (napi); \ ++ netif_poll_disable(napi_to_poll_dev(_napi)); \ ++ --_napi->dev->if_port; \ ++ if (!_napi->dev->if_port) \ ++ netif_poll_disable(_napi->dev); \ ++ } while (0) ++#define netif_napi_add(_netdev, _napi, _poll, _weight) \ ++ do { \ ++ struct napi_struct *__napi = (_napi); \ ++ struct net_device *poll_dev = napi_to_poll_dev(__napi); \ ++ poll_dev->poll = &(__kc_adapter_clean); \ ++ poll_dev->priv = (_napi); \ ++ poll_dev->weight = (_weight); \ ++ set_bit(__LINK_STATE_RX_SCHED, &poll_dev->state); \ ++ set_bit(__LINK_STATE_START, &poll_dev->state);\ ++ dev_hold(poll_dev); \ ++ _netdev->poll = &(__kc_adapter_clean); \ ++ _netdev->weight = (_weight); \ ++ __napi->poll = &(_poll); \ ++ __napi->weight = (_weight); \ ++ __napi->dev = (_netdev); \ ++ set_bit(__LINK_STATE_RX_SCHED, &(_netdev)->state); \ ++ } while (0) ++#define netif_napi_del(_napi) \ ++ do { \ ++ struct net_device *poll_dev = napi_to_poll_dev(_napi); \ ++ WARN_ON(!test_bit(__LINK_STATE_RX_SCHED, &poll_dev->state)); \ ++ dev_put(poll_dev); \ ++ memset(poll_dev, 0, sizeof(struct net_device));\ ++ } while (0) ++#define napi_schedule_prep(_napi) \ ++ (netif_running((_napi)->dev) && netif_rx_schedule_prep(napi_to_poll_dev(_napi))) ++#define napi_schedule(_napi) netif_rx_schedule(napi_to_poll_dev(_napi)) ++#define __napi_schedule(_napi) __netif_rx_schedule(napi_to_poll_dev(_napi)) ++#define napi_complete(_napi) netif_rx_complete(napi_to_poll_dev(_napi)) ++#else /* NAPI */ ++#define netif_napi_add(_netdev, _napi, _poll, _weight) \ ++ do { \ ++ struct napi_struct *__napi = _napi; \ ++ _netdev->poll = &(_poll); \ ++ _netdev->weight = (_weight); \ ++ __napi->poll = &(_poll); \ ++ __napi->weight = (_weight); \ ++ __napi->dev = (_netdev); \ ++ } while (0) ++#define netif_napi_del(_a) do {} while (0) ++#endif /* NAPI */ ++ ++#undef dev_get_by_name ++#define dev_get_by_name(_a, _b) dev_get_by_name(_b) ++#define __netif_subqueue_stopped(_a, _b) netif_subqueue_stopped(_a, _b) ++#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) ++#else /* < 2.6.24 */ ++#define HAVE_NETDEV_NAPI_LIST ++#endif /* < 2.6.24 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,24) ) ++#include ++#endif /* > 2.6.24 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) ) ++#define PM_QOS_CPU_DMA_LATENCY 1 ++ ++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18) ) ++#include ++#define PM_QOS_DEFAULT_VALUE INFINITE_LATENCY ++#define pm_qos_add_requirement(pm_qos_class, name, value) \ ++ set_acceptable_latency(name, value) ++#define pm_qos_remove_requirement(pm_qos_class, name) \ ++ remove_acceptable_latency(name) ++#define pm_qos_update_requirement(pm_qos_class, name, value) \ ++ modify_acceptable_latency(name, value) ++#else ++#define PM_QOS_DEFAULT_VALUE -1 ++#define pm_qos_add_requirement(pm_qos_class, name, value) ++#define pm_qos_remove_requirement(pm_qos_class, name) ++#define pm_qos_update_requirement(pm_qos_class, name, value) { \ ++ if (value != PM_QOS_DEFAULT_VALUE) { \ ++ printk(KERN_WARNING "%s: unable to set PM QoS requirement\n", \ ++ pci_name(adapter->pdev)); \ ++ } \ ++} ++#endif /* > 2.6.18 */ ++ ++#define pci_enable_device_mem(pdev) pci_enable_device(pdev) ++ ++#endif /* < 2.6.25 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) ) ++#ifdef NETIF_F_TSO ++#ifdef NETIF_F_TSO6 ++#define netif_set_gso_max_size(_netdev, size) \ ++ do { \ ++ if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { \ ++ _netdev->features &= ~NETIF_F_TSO; \ ++ _netdev->features &= ~NETIF_F_TSO6; \ ++ } else { \ ++ _netdev->features |= NETIF_F_TSO; \ ++ _netdev->features |= NETIF_F_TSO6; \ ++ } \ ++ } while (0) ++#else /* NETIF_F_TSO6 */ ++#define netif_set_gso_max_size(_netdev, size) \ ++ do { \ ++ if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ ++ _netdev->features &= ~NETIF_F_TSO; \ ++ else \ ++ _netdev->features |= NETIF_F_TSO; \ ++ } while (0) ++#endif /* NETIF_F_TSO6 */ ++#else ++#define netif_set_gso_max_size(_netdev, size) do {} while (0) ++#endif /* NETIF_F_TSO */ ++#else /* < 2.6.26 */ ++#include ++#define HAVE_NETDEV_VLAN_FEATURES ++#endif /* < 2.6.26 */ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) ) ++#if (((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) && defined(CONFIG_PM)) || ((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) && defined(CONFIG_PM_SLEEP))) ++#undef device_set_wakeup_enable ++#define device_set_wakeup_enable(dev, val) \ ++ do { \ ++ u16 pmc = 0; \ ++ int pm = pci_find_capability(adapter->pdev, PCI_CAP_ID_PM); \ ++ if (pm) { \ ++ pci_read_config_word(adapter->pdev, pm + PCI_PM_PMC, \ ++ &pmc); \ ++ } \ ++ (dev)->power.can_wakeup = !!(pmc >> 11); \ ++ (dev)->power.should_wakeup = (val && (pmc >> 11)); \ ++ } while (0) ++#endif /* 2.6.15-2.6.22 and CONFIG_PM or 2.6.23-2.6.25 and CONFIG_PM_SLEEP */ ++#endif /* 2.6.15 through 2.6.27 */ ++#ifndef netif_napi_del ++#define netif_napi_del(_a) do {} while (0) ++#ifdef NAPI ++#ifdef CONFIG_NETPOLL ++#undef netif_napi_del ++#define netif_napi_del(_a) list_del(&(_a)->dev_list); ++#endif ++#endif ++#endif /* netif_napi_del */ ++#ifndef pci_dma_mapping_error ++#define pci_dma_mapping_error(pdev, dma_addr) pci_dma_mapping_error(dma_addr) ++#endif ++ ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++#define HAVE_TX_MQ ++#endif ++ ++#ifdef HAVE_TX_MQ ++extern void _kc_netif_tx_stop_all_queues(struct net_device *); ++extern void _kc_netif_tx_wake_all_queues(struct net_device *); ++extern void _kc_netif_tx_start_all_queues(struct net_device *); ++#define netif_tx_stop_all_queues(a) _kc_netif_tx_stop_all_queues(a) ++#define netif_tx_wake_all_queues(a) _kc_netif_tx_wake_all_queues(a) ++#define netif_tx_start_all_queues(a) _kc_netif_tx_start_all_queues(a) ++#undef netif_stop_subqueue ++#define netif_stop_subqueue(_ndev,_qi) do { \ ++ if (netif_is_multiqueue((_ndev))) \ ++ netif_stop_subqueue((_ndev), (_qi)); \ ++ else \ ++ netif_stop_queue((_ndev)); \ ++ } while (0) ++#undef netif_start_subqueue ++#define netif_start_subqueue(_ndev,_qi) do { \ ++ if (netif_is_multiqueue((_ndev))) \ ++ netif_start_subqueue((_ndev), (_qi)); \ ++ else \ ++ netif_start_queue((_ndev)); \ ++ } while (0) ++#else /* HAVE_TX_MQ */ ++#define netif_tx_stop_all_queues(a) netif_stop_queue(a) ++#define netif_tx_wake_all_queues(a) netif_wake_queue(a) ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12) ) ++#define netif_tx_start_all_queues(a) netif_start_queue(a) ++#else ++#define netif_tx_start_all_queues(a) do {} while (0) ++#endif ++#define netif_stop_subqueue(_ndev,_qi) netif_stop_queue((_ndev)) ++#define netif_start_subqueue(_ndev,_qi) netif_start_queue((_ndev)) ++#endif /* HAVE_TX_MQ */ ++#ifndef NETIF_F_MULTI_QUEUE ++#define NETIF_F_MULTI_QUEUE 0 ++#define netif_is_multiqueue(a) 0 ++#define netif_wake_subqueue(a, b) ++#endif /* NETIF_F_MULTI_QUEUE */ ++#else /* < 2.6.27 */ ++#define HAVE_TX_MQ ++#define HAVE_NETDEV_SELECT_QUEUE ++#endif /* < 2.6.27 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) ++#define pci_ioremap_bar(pdev, bar) ioremap(pci_resource_start(pdev, bar), \ ++ pci_resource_len(pdev, bar)) ++#define pci_wake_from_d3 _kc_pci_wake_from_d3 ++#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep ++extern int _kc_pci_wake_from_d3(struct pci_dev *dev, bool enable); ++extern int _kc_pci_prepare_to_sleep(struct pci_dev *dev); ++#endif /* < 2.6.28 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) ) ++#define pci_request_selected_regions_exclusive(pdev, bars, name) \ ++ pci_request_selected_regions(pdev, bars, name) ++extern void _kc_pci_disable_link_state(struct pci_dev *dev, int state); ++#define pci_disable_link_state(p, s) _kc_pci_disable_link_state(p, s) ++#else /* < 2.6.29 */ ++#ifdef CONFIG_DCB ++#define HAVE_PFC_MODE_ENABLE ++#endif /* CONFIG_DCB */ ++#endif /* < 2.6.29 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ) ++#undef CONFIG_FCOE ++#undef CONFIG_FCOE_MODULE ++extern u16 _kc_skb_tx_hash(struct net_device *dev, struct sk_buff *skb); ++#define skb_tx_hash(n, s) _kc_skb_tx_hash(n, s) ++#define skb_record_rx_queue(a, b) do {} while (0) ++#else ++#define HAVE_ASPM_QUIRKS ++#endif /* < 2.6.30 */ ++ ++/*****************************************************************************/ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31) ) ++#define ETH_P_1588 0x88F7 ++#else ++#ifndef HAVE_NETDEV_STORAGE_ADDRESS ++#define HAVE_NETDEV_STORAGE_ADDRESS ++#endif ++#ifndef HAVE_NETDEV_HW_ADDR ++#define HAVE_NETDEV_HW_ADDR ++#endif ++#endif /* < 2.6.31 */ ++#endif /* _KCOMPAT_H_ */ +diff -r 1efe16c57de3 drivers/net/ixgbe/kcompat_ethtool.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/ixgbe/kcompat_ethtool.c Wed Aug 05 11:05:50 2009 +0100 +@@ -0,0 +1,1168 @@ ++/******************************************************************************* ++ ++ Intel 10 Gigabit PCI Express Linux driver ++ Copyright(c) 1999 - 2009 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ e1000-devel Mailing List ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * net/core/ethtool.c - Ethtool ioctl handler ++ * Copyright (c) 2003 Matthew Wilcox ++ * ++ * This file is where we call all the ethtool_ops commands to get ++ * the information ethtool needs. We fall back to calling do_ioctl() ++ * for drivers which haven't been converted to ethtool_ops yet. ++ * ++ * It's GPL, stupid. ++ * ++ * Modification by sfeldma@pobox.com to work as backward compat ++ * solution for pre-ethtool_ops kernels. ++ * - copied struct ethtool_ops from ethtool.h ++ * - defined SET_ETHTOOL_OPS ++ * - put in some #ifndef NETIF_F_xxx wrappers ++ * - changes refs to dev->ethtool_ops to ethtool_ops ++ * - changed dev_ethtool to ethtool_ioctl ++ * - remove EXPORT_SYMBOL()s ++ * - added _kc_ prefix in built-in ethtool_op_xxx ops. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "kcompat.h" ++ ++#undef SUPPORTED_10000baseT_Full ++#define SUPPORTED_10000baseT_Full (1 << 12) ++#undef ADVERTISED_10000baseT_Full ++#define ADVERTISED_10000baseT_Full (1 << 12) ++#undef SPEED_10000 ++#define SPEED_10000 10000 ++ ++#undef ethtool_ops ++#define ethtool_ops _kc_ethtool_ops ++ ++struct _kc_ethtool_ops { ++ int (*get_settings)(struct net_device *, struct ethtool_cmd *); ++ int (*set_settings)(struct net_device *, struct ethtool_cmd *); ++ void (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *); ++ int (*get_regs_len)(struct net_device *); ++ void (*get_regs)(struct net_device *, struct ethtool_regs *, void *); ++ void (*get_wol)(struct net_device *, struct ethtool_wolinfo *); ++ int (*set_wol)(struct net_device *, struct ethtool_wolinfo *); ++ u32 (*get_msglevel)(struct net_device *); ++ void (*set_msglevel)(struct net_device *, u32); ++ int (*nway_reset)(struct net_device *); ++ u32 (*get_link)(struct net_device *); ++ int (*get_eeprom_len)(struct net_device *); ++ int (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); ++ int (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); ++ int (*get_coalesce)(struct net_device *, struct ethtool_coalesce *); ++ int (*set_coalesce)(struct net_device *, struct ethtool_coalesce *); ++ void (*get_ringparam)(struct net_device *, struct ethtool_ringparam *); ++ int (*set_ringparam)(struct net_device *, struct ethtool_ringparam *); ++ void (*get_pauseparam)(struct net_device *, ++ struct ethtool_pauseparam*); ++ int (*set_pauseparam)(struct net_device *, ++ struct ethtool_pauseparam*); ++ u32 (*get_rx_csum)(struct net_device *); ++ int (*set_rx_csum)(struct net_device *, u32); ++ u32 (*get_tx_csum)(struct net_device *); ++ int (*set_tx_csum)(struct net_device *, u32); ++ u32 (*get_sg)(struct net_device *); ++ int (*set_sg)(struct net_device *, u32); ++ u32 (*get_tso)(struct net_device *); ++ int (*set_tso)(struct net_device *, u32); ++ int (*self_test_count)(struct net_device *); ++ void (*self_test)(struct net_device *, struct ethtool_test *, u64 *); ++ void (*get_strings)(struct net_device *, u32 stringset, u8 *); ++ int (*phys_id)(struct net_device *, u32); ++ int (*get_stats_count)(struct net_device *); ++ void (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, ++ u64 *); ++} *ethtool_ops = NULL; ++ ++#undef SET_ETHTOOL_OPS ++#define SET_ETHTOOL_OPS(netdev, ops) (ethtool_ops = (ops)) ++ ++/* ++ * Some useful ethtool_ops methods that are device independent. If we find that ++ * all drivers want to do the same thing here, we can turn these into dev_() ++ * function calls. ++ */ ++ ++#undef ethtool_op_get_link ++#define ethtool_op_get_link _kc_ethtool_op_get_link ++u32 _kc_ethtool_op_get_link(struct net_device *dev) ++{ ++ return netif_carrier_ok(dev) ? 1 : 0; ++} ++ ++#undef ethtool_op_get_tx_csum ++#define ethtool_op_get_tx_csum _kc_ethtool_op_get_tx_csum ++u32 _kc_ethtool_op_get_tx_csum(struct net_device *dev) ++{ ++#ifdef NETIF_F_IP_CSUM ++ return (dev->features & NETIF_F_IP_CSUM) != 0; ++#else ++ return 0; ++#endif ++} ++ ++#undef ethtool_op_set_tx_csum ++#define ethtool_op_set_tx_csum _kc_ethtool_op_set_tx_csum ++int _kc_ethtool_op_set_tx_csum(struct net_device *dev, u32 data) ++{ ++#ifdef NETIF_F_IP_CSUM ++ if (data) ++#ifdef NETIF_F_IPV6_CSUM ++ dev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); ++ else ++ dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); ++#else ++ dev->features |= NETIF_F_IP_CSUM; ++ else ++ dev->features &= ~NETIF_F_IP_CSUM; ++#endif ++#endif ++ ++ return 0; ++} ++ ++#undef ethtool_op_get_sg ++#define ethtool_op_get_sg _kc_ethtool_op_get_sg ++u32 _kc_ethtool_op_get_sg(struct net_device *dev) ++{ ++#ifdef NETIF_F_SG ++ return (dev->features & NETIF_F_SG) != 0; ++#else ++ return 0; ++#endif ++} ++ ++#undef ethtool_op_set_sg ++#define ethtool_op_set_sg _kc_ethtool_op_set_sg ++int _kc_ethtool_op_set_sg(struct net_device *dev, u32 data) ++{ ++#ifdef NETIF_F_SG ++ if (data) ++ dev->features |= NETIF_F_SG; ++ else ++ dev->features &= ~NETIF_F_SG; ++#endif ++ ++ return 0; ++} ++ ++#undef ethtool_op_get_tso ++#define ethtool_op_get_tso _kc_ethtool_op_get_tso ++u32 _kc_ethtool_op_get_tso(struct net_device *dev) ++{ ++#ifdef NETIF_F_TSO ++ return (dev->features & NETIF_F_TSO) != 0; ++#else ++ return 0; ++#endif ++} ++ ++#undef ethtool_op_set_tso ++#define ethtool_op_set_tso _kc_ethtool_op_set_tso ++int _kc_ethtool_op_set_tso(struct net_device *dev, u32 data) ++{ ++#ifdef NETIF_F_TSO ++ if (data) ++ dev->features |= NETIF_F_TSO; ++ else ++ dev->features &= ~NETIF_F_TSO; ++#endif ++ ++ return 0; ++} ++ ++/* Handlers for each ethtool command */ ++ ++static int ethtool_get_settings(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_cmd cmd = { ETHTOOL_GSET }; ++ int err; ++ ++ if (!ethtool_ops->get_settings) ++ return -EOPNOTSUPP; ++ ++ err = ethtool_ops->get_settings(dev, &cmd); ++ if (err < 0) ++ return err; ++ ++ if (copy_to_user(useraddr, &cmd, sizeof(cmd))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_settings(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_cmd cmd; ++ ++ if (!ethtool_ops->set_settings) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&cmd, useraddr, sizeof(cmd))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_settings(dev, &cmd); ++} ++ ++static int ethtool_get_drvinfo(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_drvinfo info; ++ struct ethtool_ops *ops = ethtool_ops; ++ ++ if (!ops->get_drvinfo) ++ return -EOPNOTSUPP; ++ ++ memset(&info, 0, sizeof(info)); ++ info.cmd = ETHTOOL_GDRVINFO; ++ ops->get_drvinfo(dev, &info); ++ ++ if (ops->self_test_count) ++ info.testinfo_len = ops->self_test_count(dev); ++ if (ops->get_stats_count) ++ info.n_stats = ops->get_stats_count(dev); ++ if (ops->get_regs_len) ++ info.regdump_len = ops->get_regs_len(dev); ++ if (ops->get_eeprom_len) ++ info.eedump_len = ops->get_eeprom_len(dev); ++ ++ if (copy_to_user(useraddr, &info, sizeof(info))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_get_regs(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_regs regs; ++ struct ethtool_ops *ops = ethtool_ops; ++ void *regbuf; ++ int reglen, ret; ++ ++ if (!ops->get_regs || !ops->get_regs_len) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(®s, useraddr, sizeof(regs))) ++ return -EFAULT; ++ ++ reglen = ops->get_regs_len(dev); ++ if (regs.len > reglen) ++ regs.len = reglen; ++ ++ regbuf = kmalloc(reglen, GFP_USER); ++ if (!regbuf) ++ return -ENOMEM; ++ ++ ops->get_regs(dev, ®s, regbuf); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, ®s, sizeof(regs))) ++ goto out; ++ useraddr += offsetof(struct ethtool_regs, data); ++ if (copy_to_user(useraddr, regbuf, reglen)) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(regbuf); ++ return ret; ++} ++ ++static int ethtool_get_wol(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_wolinfo wol = { ETHTOOL_GWOL }; ++ ++ if (!ethtool_ops->get_wol) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_wol(dev, &wol); ++ ++ if (copy_to_user(useraddr, &wol, sizeof(wol))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_wol(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_wolinfo wol; ++ ++ if (!ethtool_ops->set_wol) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&wol, useraddr, sizeof(wol))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_wol(dev, &wol); ++} ++ ++static int ethtool_get_msglevel(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GMSGLVL }; ++ ++ if (!ethtool_ops->get_msglevel) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_msglevel(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_msglevel(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_msglevel) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ ethtool_ops->set_msglevel(dev, edata.data); ++ return 0; ++} ++ ++static int ethtool_nway_reset(struct net_device *dev) ++{ ++ if (!ethtool_ops->nway_reset) ++ return -EOPNOTSUPP; ++ ++ return ethtool_ops->nway_reset(dev); ++} ++ ++static int ethtool_get_link(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ ++ if (!ethtool_ops->get_link) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_link(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_get_eeprom(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_eeprom eeprom; ++ struct ethtool_ops *ops = ethtool_ops; ++ u8 *data; ++ int ret; ++ ++ if (!ops->get_eeprom || !ops->get_eeprom_len) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) ++ return -EFAULT; ++ ++ /* Check for wrap and zero */ ++ if (eeprom.offset + eeprom.len <= eeprom.offset) ++ return -EINVAL; ++ ++ /* Check for exceeding total eeprom len */ ++ if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev)) ++ return -EINVAL; ++ ++ data = kmalloc(eeprom.len, GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ret = -EFAULT; ++ if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len)) ++ goto out; ++ ++ ret = ops->get_eeprom(dev, &eeprom, data); ++ if (ret) ++ goto out; ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &eeprom, sizeof(eeprom))) ++ goto out; ++ if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len)) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_set_eeprom(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_eeprom eeprom; ++ struct ethtool_ops *ops = ethtool_ops; ++ u8 *data; ++ int ret; ++ ++ if (!ops->set_eeprom || !ops->get_eeprom_len) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) ++ return -EFAULT; ++ ++ /* Check for wrap and zero */ ++ if (eeprom.offset + eeprom.len <= eeprom.offset) ++ return -EINVAL; ++ ++ /* Check for exceeding total eeprom len */ ++ if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev)) ++ return -EINVAL; ++ ++ data = kmalloc(eeprom.len, GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ret = -EFAULT; ++ if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len)) ++ goto out; ++ ++ ret = ops->set_eeprom(dev, &eeprom, data); ++ if (ret) ++ goto out; ++ ++ if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len)) ++ ret = -EFAULT; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_get_coalesce(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_coalesce coalesce = { ETHTOOL_GCOALESCE }; ++ ++ if (!ethtool_ops->get_coalesce) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_coalesce(dev, &coalesce); ++ ++ if (copy_to_user(useraddr, &coalesce, sizeof(coalesce))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_coalesce(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_coalesce coalesce; ++ ++ if (!ethtool_ops->get_coalesce) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&coalesce, useraddr, sizeof(coalesce))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_coalesce(dev, &coalesce); ++} ++ ++static int ethtool_get_ringparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_ringparam ringparam = { ETHTOOL_GRINGPARAM }; ++ ++ if (!ethtool_ops->get_ringparam) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_ringparam(dev, &ringparam); ++ ++ if (copy_to_user(useraddr, &ringparam, sizeof(ringparam))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_ringparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_ringparam ringparam; ++ ++ if (!ethtool_ops->get_ringparam) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&ringparam, useraddr, sizeof(ringparam))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_ringparam(dev, &ringparam); ++} ++ ++static int ethtool_get_pauseparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_pauseparam pauseparam = { ETHTOOL_GPAUSEPARAM }; ++ ++ if (!ethtool_ops->get_pauseparam) ++ return -EOPNOTSUPP; ++ ++ ethtool_ops->get_pauseparam(dev, &pauseparam); ++ ++ if (copy_to_user(useraddr, &pauseparam, sizeof(pauseparam))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_pauseparam(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_pauseparam pauseparam; ++ ++ if (!ethtool_ops->get_pauseparam) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&pauseparam, useraddr, sizeof(pauseparam))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_pauseparam(dev, &pauseparam); ++} ++ ++static int ethtool_get_rx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GRXCSUM }; ++ ++ if (!ethtool_ops->get_rx_csum) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_rx_csum(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_rx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_rx_csum) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ ethtool_ops->set_rx_csum(dev, edata.data); ++ return 0; ++} ++ ++static int ethtool_get_tx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GTXCSUM }; ++ ++ if (!ethtool_ops->get_tx_csum) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_tx_csum(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_tx_csum(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_tx_csum) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_tx_csum(dev, edata.data); ++} ++ ++static int ethtool_get_sg(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GSG }; ++ ++ if (!ethtool_ops->get_sg) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_sg(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_sg(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_sg) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_sg(dev, edata.data); ++} ++ ++static int ethtool_get_tso(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata = { ETHTOOL_GTSO }; ++ ++ if (!ethtool_ops->get_tso) ++ return -EOPNOTSUPP; ++ ++ edata.data = ethtool_ops->get_tso(dev); ++ ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++} ++ ++static int ethtool_set_tso(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_value edata; ++ ++ if (!ethtool_ops->set_tso) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&edata, useraddr, sizeof(edata))) ++ return -EFAULT; ++ ++ return ethtool_ops->set_tso(dev, edata.data); ++} ++ ++static int ethtool_self_test(struct net_device *dev, char *useraddr) ++{ ++ struct ethtool_test test; ++ struct ethtool_ops *ops = ethtool_ops; ++ u64 *data; ++ int ret; ++ ++ if (!ops->self_test || !ops->self_test_count) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&test, useraddr, sizeof(test))) ++ return -EFAULT; ++ ++ test.len = ops->self_test_count(dev); ++ data = kmalloc(test.len * sizeof(u64), GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ops->self_test(dev, &test, data); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &test, sizeof(test))) ++ goto out; ++ useraddr += sizeof(test); ++ if (copy_to_user(useraddr, data, test.len * sizeof(u64))) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_get_strings(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_gstrings gstrings; ++ struct ethtool_ops *ops = ethtool_ops; ++ u8 *data; ++ int ret; ++ ++ if (!ops->get_strings) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&gstrings, useraddr, sizeof(gstrings))) ++ return -EFAULT; ++ ++ switch (gstrings.string_set) { ++ case ETH_SS_TEST: ++ if (!ops->self_test_count) ++ return -EOPNOTSUPP; ++ gstrings.len = ops->self_test_count(dev); ++ break; ++ case ETH_SS_STATS: ++ if (!ops->get_stats_count) ++ return -EOPNOTSUPP; ++ gstrings.len = ops->get_stats_count(dev); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ data = kmalloc(gstrings.len * ETH_GSTRING_LEN, GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ops->get_strings(dev, gstrings.string_set, data); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &gstrings, sizeof(gstrings))) ++ goto out; ++ useraddr += sizeof(gstrings); ++ if (copy_to_user(useraddr, data, gstrings.len * ETH_GSTRING_LEN)) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++static int ethtool_phys_id(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_value id; ++ ++ if (!ethtool_ops->phys_id) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&id, useraddr, sizeof(id))) ++ return -EFAULT; ++ ++ return ethtool_ops->phys_id(dev, id.data); ++} ++ ++static int ethtool_get_stats(struct net_device *dev, void *useraddr) ++{ ++ struct ethtool_stats stats; ++ struct ethtool_ops *ops = ethtool_ops; ++ u64 *data; ++ int ret; ++ ++ if (!ops->get_ethtool_stats || !ops->get_stats_count) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(&stats, useraddr, sizeof(stats))) ++ return -EFAULT; ++ ++ stats.n_stats = ops->get_stats_count(dev); ++ data = kmalloc(stats.n_stats * sizeof(u64), GFP_USER); ++ if (!data) ++ return -ENOMEM; ++ ++ ops->get_ethtool_stats(dev, &stats, data); ++ ++ ret = -EFAULT; ++ if (copy_to_user(useraddr, &stats, sizeof(stats))) ++ goto out; ++ useraddr += sizeof(stats); ++ if (copy_to_user(useraddr, data, stats.n_stats * sizeof(u64))) ++ goto out; ++ ret = 0; ++ ++out: ++ kfree(data); ++ return ret; ++} ++ ++/* The main entry point in this file. Called from net/core/dev.c */ ++ ++#define ETHTOOL_OPS_COMPAT ++int ethtool_ioctl(struct ifreq *ifr) ++{ ++ struct net_device *dev = __dev_get_by_name(ifr->ifr_name); ++ void *useraddr = (void *) ifr->ifr_data; ++ u32 ethcmd; ++ ++ /* ++ * XXX: This can be pushed down into the ethtool_* handlers that ++ * need it. Keep existing behavior for the moment. ++ */ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++ if (!dev || !netif_device_present(dev)) ++ return -ENODEV; ++ ++ if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd))) ++ return -EFAULT; ++ ++ switch (ethcmd) { ++ case ETHTOOL_GSET: ++ return ethtool_get_settings(dev, useraddr); ++ case ETHTOOL_SSET: ++ return ethtool_set_settings(dev, useraddr); ++ case ETHTOOL_GDRVINFO: ++ return ethtool_get_drvinfo(dev, useraddr); ++ case ETHTOOL_GREGS: ++ return ethtool_get_regs(dev, useraddr); ++ case ETHTOOL_GWOL: ++ return ethtool_get_wol(dev, useraddr); ++ case ETHTOOL_SWOL: ++ return ethtool_set_wol(dev, useraddr); ++ case ETHTOOL_GMSGLVL: ++ return ethtool_get_msglevel(dev, useraddr); ++ case ETHTOOL_SMSGLVL: ++ return ethtool_set_msglevel(dev, useraddr); ++ case ETHTOOL_NWAY_RST: ++ return ethtool_nway_reset(dev); ++ case ETHTOOL_GLINK: ++ return ethtool_get_link(dev, useraddr); ++ case ETHTOOL_GEEPROM: ++ return ethtool_get_eeprom(dev, useraddr); ++ case ETHTOOL_SEEPROM: ++ return ethtool_set_eeprom(dev, useraddr); ++ case ETHTOOL_GCOALESCE: ++ return ethtool_get_coalesce(dev, useraddr); ++ case ETHTOOL_SCOALESCE: ++ return ethtool_set_coalesce(dev, useraddr); ++ case ETHTOOL_GRINGPARAM: ++ return ethtool_get_ringparam(dev, useraddr); ++ case ETHTOOL_SRINGPARAM: ++ return ethtool_set_ringparam(dev, useraddr); ++ case ETHTOOL_GPAUSEPARAM: ++ return ethtool_get_pauseparam(dev, useraddr); ++ case ETHTOOL_SPAUSEPARAM: ++ return ethtool_set_pauseparam(dev, useraddr); ++ case ETHTOOL_GRXCSUM: ++ return ethtool_get_rx_csum(dev, useraddr); ++ case ETHTOOL_SRXCSUM: ++ return ethtool_set_rx_csum(dev, useraddr); ++ case ETHTOOL_GTXCSUM: ++ return ethtool_get_tx_csum(dev, useraddr); ++ case ETHTOOL_STXCSUM: ++ return ethtool_set_tx_csum(dev, useraddr); ++ case ETHTOOL_GSG: ++ return ethtool_get_sg(dev, useraddr); ++ case ETHTOOL_SSG: ++ return ethtool_set_sg(dev, useraddr); ++ case ETHTOOL_GTSO: ++ return ethtool_get_tso(dev, useraddr); ++ case ETHTOOL_STSO: ++ return ethtool_set_tso(dev, useraddr); ++ case ETHTOOL_TEST: ++ return ethtool_self_test(dev, useraddr); ++ case ETHTOOL_GSTRINGS: ++ return ethtool_get_strings(dev, useraddr); ++ case ETHTOOL_PHYS_ID: ++ return ethtool_phys_id(dev, useraddr); ++ case ETHTOOL_GSTATS: ++ return ethtool_get_stats(dev, useraddr); ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return -EOPNOTSUPP; ++} ++ ++#define mii_if_info _kc_mii_if_info ++struct _kc_mii_if_info { ++ int phy_id; ++ int advertising; ++ int phy_id_mask; ++ int reg_num_mask; ++ ++ unsigned int full_duplex : 1; /* is full duplex? */ ++ unsigned int force_media : 1; /* is autoneg. disabled? */ ++ ++ struct net_device *dev; ++ int (*mdio_read) (struct net_device *dev, int phy_id, int location); ++ void (*mdio_write) (struct net_device *dev, int phy_id, int location, int val); ++}; ++ ++struct ethtool_cmd; ++struct mii_ioctl_data; ++ ++#undef mii_link_ok ++#define mii_link_ok _kc_mii_link_ok ++#undef mii_nway_restart ++#define mii_nway_restart _kc_mii_nway_restart ++#undef mii_ethtool_gset ++#define mii_ethtool_gset _kc_mii_ethtool_gset ++#undef mii_ethtool_sset ++#define mii_ethtool_sset _kc_mii_ethtool_sset ++#undef mii_check_link ++#define mii_check_link _kc_mii_check_link ++#undef generic_mii_ioctl ++#define generic_mii_ioctl _kc_generic_mii_ioctl ++extern int _kc_mii_link_ok (struct mii_if_info *mii); ++extern int _kc_mii_nway_restart (struct mii_if_info *mii); ++extern int _kc_mii_ethtool_gset(struct mii_if_info *mii, ++ struct ethtool_cmd *ecmd); ++extern int _kc_mii_ethtool_sset(struct mii_if_info *mii, ++ struct ethtool_cmd *ecmd); ++extern void _kc_mii_check_link (struct mii_if_info *mii); ++extern int _kc_generic_mii_ioctl(struct mii_if_info *mii_if, ++ struct mii_ioctl_data *mii_data, int cmd, ++ unsigned int *duplex_changed); ++ ++ ++struct _kc_pci_dev_ext { ++ struct pci_dev *dev; ++ void *pci_drvdata; ++ struct pci_driver *driver; ++}; ++ ++struct _kc_net_dev_ext { ++ struct net_device *dev; ++ unsigned int carrier; ++}; ++ ++ ++/**************************************/ ++/* mii support */ ++ ++int _kc_mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) ++{ ++ struct net_device *dev = mii->dev; ++ u32 advert, bmcr, lpa, nego; ++ ++ ecmd->supported = ++ (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | ++ SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | ++ SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII); ++ ++ /* only supports twisted-pair */ ++ ecmd->port = PORT_MII; ++ ++ /* only supports internal transceiver */ ++ ecmd->transceiver = XCVR_INTERNAL; ++ ++ /* this isn't fully supported at higher layers */ ++ ecmd->phy_address = mii->phy_id; ++ ++ ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII; ++ advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE); ++ if (advert & ADVERTISE_10HALF) ++ ecmd->advertising |= ADVERTISED_10baseT_Half; ++ if (advert & ADVERTISE_10FULL) ++ ecmd->advertising |= ADVERTISED_10baseT_Full; ++ if (advert & ADVERTISE_100HALF) ++ ecmd->advertising |= ADVERTISED_100baseT_Half; ++ if (advert & ADVERTISE_100FULL) ++ ecmd->advertising |= ADVERTISED_100baseT_Full; ++ ++ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); ++ lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA); ++ if (bmcr & BMCR_ANENABLE) { ++ ecmd->advertising |= ADVERTISED_Autoneg; ++ ecmd->autoneg = AUTONEG_ENABLE; ++ ++ nego = mii_nway_result(advert & lpa); ++ if (nego == LPA_100FULL || nego == LPA_100HALF) ++ ecmd->speed = SPEED_100; ++ else ++ ecmd->speed = SPEED_10; ++ if (nego == LPA_100FULL || nego == LPA_10FULL) { ++ ecmd->duplex = DUPLEX_FULL; ++ mii->full_duplex = 1; ++ } else { ++ ecmd->duplex = DUPLEX_HALF; ++ mii->full_duplex = 0; ++ } ++ } else { ++ ecmd->autoneg = AUTONEG_DISABLE; ++ ++ ecmd->speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; ++ ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; ++ } ++ ++ /* ignore maxtxpkt, maxrxpkt for now */ ++ ++ return 0; ++} ++ ++int _kc_mii_ethtool_sset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) ++{ ++ struct net_device *dev = mii->dev; ++ ++ if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) ++ return -EINVAL; ++ if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) ++ return -EINVAL; ++ if (ecmd->port != PORT_MII) ++ return -EINVAL; ++ if (ecmd->transceiver != XCVR_INTERNAL) ++ return -EINVAL; ++ if (ecmd->phy_address != mii->phy_id) ++ return -EINVAL; ++ if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE) ++ return -EINVAL; ++ ++ /* ignore supported, maxtxpkt, maxrxpkt */ ++ ++ if (ecmd->autoneg == AUTONEG_ENABLE) { ++ u32 bmcr, advert, tmp; ++ ++ if ((ecmd->advertising & (ADVERTISED_10baseT_Half | ++ ADVERTISED_10baseT_Full | ++ ADVERTISED_100baseT_Half | ++ ADVERTISED_100baseT_Full)) == 0) ++ return -EINVAL; ++ ++ /* advertise only what has been requested */ ++ advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE); ++ tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4); ++ if (ADVERTISED_10baseT_Half) ++ tmp |= ADVERTISE_10HALF; ++ if (ADVERTISED_10baseT_Full) ++ tmp |= ADVERTISE_10FULL; ++ if (ADVERTISED_100baseT_Half) ++ tmp |= ADVERTISE_100HALF; ++ if (ADVERTISED_100baseT_Full) ++ tmp |= ADVERTISE_100FULL; ++ if (advert != tmp) { ++ mii->mdio_write(dev, mii->phy_id, MII_ADVERTISE, tmp); ++ mii->advertising = tmp; ++ } ++ ++ /* turn on autonegotiation, and force a renegotiate */ ++ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); ++ bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); ++ mii->mdio_write(dev, mii->phy_id, MII_BMCR, bmcr); ++ ++ mii->force_media = 0; ++ } else { ++ u32 bmcr, tmp; ++ ++ /* turn off auto negotiation, set speed and duplexity */ ++ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); ++ tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX); ++ if (ecmd->speed == SPEED_100) ++ tmp |= BMCR_SPEED100; ++ if (ecmd->duplex == DUPLEX_FULL) { ++ tmp |= BMCR_FULLDPLX; ++ mii->full_duplex = 1; ++ } else ++ mii->full_duplex = 0; ++ if (bmcr != tmp) ++ mii->mdio_write(dev, mii->phy_id, MII_BMCR, tmp); ++ ++ mii->force_media = 1; ++ } ++ return 0; ++} ++ ++int _kc_mii_link_ok (struct mii_if_info *mii) ++{ ++ /* first, a dummy read, needed to latch some MII phys */ ++ mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); ++ if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS) ++ return 1; ++ return 0; ++} ++ ++int _kc_mii_nway_restart (struct mii_if_info *mii) ++{ ++ int bmcr; ++ int r = -EINVAL; ++ ++ /* if autoneg is off, it's an error */ ++ bmcr = mii->mdio_read(mii->dev, mii->phy_id, MII_BMCR); ++ ++ if (bmcr & BMCR_ANENABLE) { ++ bmcr |= BMCR_ANRESTART; ++ mii->mdio_write(mii->dev, mii->phy_id, MII_BMCR, bmcr); ++ r = 0; ++ } ++ ++ return r; ++} ++ ++void _kc_mii_check_link (struct mii_if_info *mii) ++{ ++ int cur_link = mii_link_ok(mii); ++ int prev_link = netif_carrier_ok(mii->dev); ++ ++ if (cur_link && !prev_link) ++ netif_carrier_on(mii->dev); ++ else if (prev_link && !cur_link) ++ netif_carrier_off(mii->dev); ++} ++ ++int _kc_generic_mii_ioctl(struct mii_if_info *mii_if, ++ struct mii_ioctl_data *mii_data, int cmd, ++ unsigned int *duplex_chg_out) ++{ ++ int rc = 0; ++ unsigned int duplex_changed = 0; ++ ++ if (duplex_chg_out) ++ *duplex_chg_out = 0; ++ ++ mii_data->phy_id &= mii_if->phy_id_mask; ++ mii_data->reg_num &= mii_if->reg_num_mask; ++ ++ switch(cmd) { ++ case SIOCDEVPRIVATE: /* binary compat, remove in 2.5 */ ++ case SIOCGMIIPHY: ++ mii_data->phy_id = mii_if->phy_id; ++ /* fall through */ ++ ++ case SIOCDEVPRIVATE + 1:/* binary compat, remove in 2.5 */ ++ case SIOCGMIIREG: ++ mii_data->val_out = ++ mii_if->mdio_read(mii_if->dev, mii_data->phy_id, ++ mii_data->reg_num); ++ break; ++ ++ case SIOCDEVPRIVATE + 2:/* binary compat, remove in 2.5 */ ++ case SIOCSMIIREG: { ++ u16 val = mii_data->val_in; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++ if (mii_data->phy_id == mii_if->phy_id) { ++ switch(mii_data->reg_num) { ++ case MII_BMCR: { ++ unsigned int new_duplex = 0; ++ if (val & (BMCR_RESET|BMCR_ANENABLE)) ++ mii_if->force_media = 0; ++ else ++ mii_if->force_media = 1; ++ if (mii_if->force_media && ++ (val & BMCR_FULLDPLX)) ++ new_duplex = 1; ++ if (mii_if->full_duplex != new_duplex) { ++ duplex_changed = 1; ++ mii_if->full_duplex = new_duplex; ++ } ++ break; ++ } ++ case MII_ADVERTISE: ++ mii_if->advertising = val; ++ break; ++ default: ++ /* do nothing */ ++ break; ++ } ++ } ++ ++ mii_if->mdio_write(mii_if->dev, mii_data->phy_id, ++ mii_data->reg_num, val); ++ break; ++ } ++ ++ default: ++ rc = -EOPNOTSUPP; ++ break; ++ } ++ ++ if ((rc == 0) && (duplex_chg_out) && (duplex_changed)) ++ *duplex_chg_out = 1; ++ ++ return rc; ++} ++ diff --git a/master/kernel-configuration b/master/kernel-configuration index 58d3ebf..8b183cd 100644 --- a/master/kernel-configuration +++ b/master/kernel-configuration @@ -1,6 +1,6 @@ -diff -r dc440f671899 buildconfigs/conf.linux-kdump/kdump +diff -r 2e812c9cff82 buildconfigs/conf.linux-kdump/kdump --- /dev/null Thu Jan 01 00:00:00 1970 +0000 -+++ b/buildconfigs/conf.linux-kdump/kdump Wed Jul 08 11:03:49 2009 +0100 ++++ b/buildconfigs/conf.linux-kdump/kdump Thu Oct 08 09:05:30 2009 +0100 @@ -0,0 +1,107 @@ +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set @@ -109,14 +109,14 @@ diff -r dc440f671899 buildconfigs/conf.linux-kdump/kdump +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_KDB is not set -diff -r dc440f671899 buildconfigs/linux-defconfig_utility_x86_32 +diff -r 2e812c9cff82 buildconfigs/linux-defconfig_utility_x86_32 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 -+++ b/buildconfigs/linux-defconfig_utility_x86_32 Wed Jul 08 11:03:49 2009 +0100 -@@ -0,0 +1,1021 @@ ++++ b/buildconfigs/linux-defconfig_utility_x86_32 Thu Oct 08 09:05:30 2009 +0100 +@@ -0,0 +1,1024 @@ +# +# Automatically generated make config: don't edit -+# Linux kernel version: 2.6.27.19 -+# Thu Mar 26 15:31:21 2009 ++# Linux kernel version: 2.6.27.29-0.1.1 ++# Thu Oct 8 09:04:45 2009 +# +# CONFIG_64BIT is not set +CONFIG_X86_32=y @@ -278,6 +278,7 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_utility_x86_32 +# CONFIG_X86_64_XEN is not set +# CONFIG_X86_VSMP is not set +# CONFIG_X86_RDC321X is not set ++CONFIG_XEN_SAVE_RESTORE=y +# CONFIG_M386 is not set +# CONFIG_M486 is not set +# CONFIG_M586 is not set @@ -351,6 +352,7 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_utility_x86_32 +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_HIGHPTE is not set +CONFIG_SECCOMP=y +# CONFIG_SECCOMP_DISABLE_TSC is not set @@ -563,6 +565,7 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_utility_x86_32 +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y ++# CONFIG_MLX4_EN is not set + +# +# Wireless LAN @@ -1134,14 +1137,14 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_utility_x86_32 +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y -diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_32 +diff -r 2e812c9cff82 buildconfigs/linux-defconfig_xen_x86_32 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 -+++ b/buildconfigs/linux-defconfig_xen_x86_32 Wed Jul 08 11:03:49 2009 +0100 -@@ -0,0 +1,2640 @@ ++++ b/buildconfigs/linux-defconfig_xen_x86_32 Thu Oct 08 09:05:30 2009 +0100 +@@ -0,0 +1,2644 @@ +# +# Automatically generated make config: don't edit -+# Linux kernel version: 2.6.27.23-0.1.1 -+# Wed Jul 8 11:01:59 2009 ++# Linux kernel version: 2.6.27.29-0.1.1 ++# Tue Oct 6 11:17:32 2009 +# +# CONFIG_64BIT is not set +CONFIG_X86_32=y @@ -1398,6 +1401,7 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_32 +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_HIGHPTE is not set +CONFIG_MTRR=y +# CONFIG_X86_PAT is not set @@ -2073,7 +2077,7 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_32 +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m -+# CONFIG_SCSI_DH_ALUA is not set ++CONFIG_SCSI_DH_ALUA=m +# CONFIG_SCSI_BNX2_ISCSI is not set +CONFIG_ATA=m +# CONFIG_ATA_NONSTANDARD is not set @@ -2320,10 +2324,14 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_32 +CONFIG_IXGBE_LRO=y +CONFIG_IXGB=m +CONFIG_S2IO=m ++CONFIG_VXGE=m ++# CONFIG_VXGE_DEBUG_TRACE_ALL is not set +CONFIG_MYRI10GE=m -+# CONFIG_NETXEN_NIC is not set ++CONFIG_NETXEN_NIC=m +# CONFIG_NIU is not set -+# CONFIG_MLX4_CORE is not set ++CONFIG_MLX4_CORE=m ++CONFIG_MLX4_EN=m ++CONFIG_MLX4_DEBUG=y +CONFIG_TEHUTI=m +CONFIG_BNX2X=m +CONFIG_SFC=m @@ -2523,7 +2531,7 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_32 +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m -+# CONFIG_IPMI_SI is not set ++CONFIG_IPMI_SI=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_HW_RANDOM=y @@ -2706,8 +2714,8 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_32 +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_CORETEMP=m -+# CONFIG_SENSORS_IBMAEM is not set -+# CONFIG_SENSORS_IBMPEX is not set ++CONFIG_SENSORS_IBMAEM=m ++CONFIG_SENSORS_IBMPEX=m +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m @@ -3658,7 +3666,6 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_32 +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set -+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 +# CONFIG_SECURITY_APPARMOR is not set +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m @@ -3778,9 +3785,9 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_32 +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_CHECK_SIGNATURE=y -diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_64 +diff -r 2e812c9cff82 buildconfigs/linux-defconfig_xen_x86_64 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 -+++ b/buildconfigs/linux-defconfig_xen_x86_64 Wed Jul 08 11:03:49 2009 +0100 ++++ b/buildconfigs/linux-defconfig_xen_x86_64 Thu Oct 08 09:05:30 2009 +0100 @@ -0,0 +1,2589 @@ +# +# Automatically generated make config: don't edit @@ -4624,7 +4631,7 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_64 +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m -+# CONFIG_SCSI_CXGB3_ISCSI is not set ++CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_ACARD=m @@ -4694,7 +4701,7 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_64 +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m -+# CONFIG_SCSI_DH_ALUA is not set ++CONFIG_SCSI_DH_ALUA=m +# CONFIG_SCSI_BNX2_ISCSI is not set +CONFIG_ATA=m +# CONFIG_ATA_NONSTANDARD is not set @@ -4940,7 +4947,7 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_64 +CONFIG_IXGB=m +CONFIG_S2IO=m +CONFIG_MYRI10GE=m -+# CONFIG_NETXEN_NIC is not set ++CONFIG_NETXEN_NIC=m +# CONFIG_NIU is not set +# CONFIG_MLX4_CORE is not set +CONFIG_TEHUTI=m @@ -5141,7 +5148,7 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_64 +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m -+# CONFIG_IPMI_SI is not set ++CONFIG_IPMI_SI=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_HW_RANDOM=y @@ -5315,8 +5322,8 @@ diff -r dc440f671899 buildconfigs/linux-defconfig_xen_x86_64 +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_CORETEMP=m -+# CONFIG_SENSORS_IBMAEM is not set -+# CONFIG_SENSORS_IBMPEX is not set ++CONFIG_SENSORS_IBMAEM=m ++CONFIG_SENSORS_IBMPEX=m +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m diff --git a/master/kexec-larger-max-pfn-for-oldmem.patch b/master/kexec-larger-max-pfn-for-oldmem.patch new file mode 100644 index 0000000..f8dc95b --- /dev/null +++ b/master/kexec-larger-max-pfn-for-oldmem.patch @@ -0,0 +1,50 @@ +Support larger maximum pfn for accessing oldmem so we can get at all +the RAM which the 64 bit hypervisor could see. + + +diff -r b17a2706e17c arch/x86/kernel/e820.c +--- a/arch/x86/kernel/e820.c Thu Jul 23 10:01:55 2009 +0100 ++++ b/arch/x86/kernel/e820.c Fri Jul 24 12:07:39 2009 +0100 +@@ -1056,7 +1056,6 @@ + { + int i; + unsigned long last_pfn = 0; +- unsigned long max_arch_pfn = MAX_ARCH_PFN; + + for (i = 0; i < e820.nr_map; i++) { + struct e820entry *ei = &e820.map[i]; +@@ -1079,11 +1078,7 @@ + last_pfn = end_pfn; + } + +- if (last_pfn > max_arch_pfn) +- last_pfn = max_arch_pfn; +- +- printk(KERN_INFO "last_pfn = %#lx max_arch_pfn = %#lx\n", +- last_pfn, max_arch_pfn); ++ printk(KERN_INFO "last_pfn = %#lx\n", last_pfn); + return last_pfn; + } + unsigned long __init e820_end_of_ram_pfn(void) +@@ -1095,6 +1090,12 @@ + { + return e820_end_pfn(1UL<<(32 - PAGE_SHIFT), E820_RAM); + } ++ ++unsigned long __init e820_end_of_kdump_ram_pfn(void) ++{ ++ return e820_end_pfn(~0UL, E820_RAM); ++} ++ + /* + * Finds an active region in the address range from start_pfn to last_pfn and + * returns its range in ei_startpfn and ei_endpfn for the e820 entry. +@@ -1210,7 +1211,7 @@ + * the real mem size before original memory map is + * reset. + */ +- saved_max_pfn = e820_end_of_ram_pfn(); ++ saved_max_pfn = e820_end_of_kdump_ram_pfn(); + #endif + e820.nr_map = 0; + userdef = 1; diff --git a/master/linux-2.6.18-xen.hg-918.71a61b393cdf b/master/linux-2.6.18-xen.hg-918.71a61b393cdf new file mode 100644 index 0000000..ae927a7 --- /dev/null +++ b/master/linux-2.6.18-xen.hg-918.71a61b393cdf @@ -0,0 +1,35 @@ +# HG changeset patch +# User Keir Fraser +# Date 1248080624 -3600 +# Node ID 71a61b393cdf313c15b077f6128e9e3f5b9b680c +# Parent b420e936c022dd90eaf0b4c0e063fe829659f56c +blkback: pagemap bug fixes + +Signed-off-by: Jake Wires + +diff -r b420e936c022 -r 71a61b393cdf drivers/xen/blkback/blkback.c +--- a/drivers/xen/blkback/blkback.c Wed Jul 15 09:10:37 2009 +0100 ++++ b/drivers/xen/blkback/blkback.c Mon Jul 20 10:03:44 2009 +0100 +@@ -453,6 +453,11 @@ + DPRINTK("invalid buffer -- could not remap it\n"); + map[i].handle = BLKBACK_INVALID_HANDLE; + ret |= 1; ++ } else { ++ blkback_pagemap_set(vaddr_pagenr(pending_req, i), ++ virt_to_page(vaddr(pending_req, i)), ++ blkif->domid, req->handle, ++ req->seg[i].gref); + } + + pending_handle(pending_req, i) = map[i].handle; +@@ -465,10 +470,6 @@ + FOREIGN_FRAME(map[i].dev_bus_addr >> PAGE_SHIFT)); + seg[i].buf = map[i].dev_bus_addr | + (req->seg[i].first_sect << 9); +- blkback_pagemap_set(vaddr_pagenr(pending_req, i), +- virt_to_page(vaddr(pending_req, i)), +- blkif->domid, req->handle, +- req->seg[i].gref); + } + + if (ret) diff --git a/master/linux-2.6.27.25-0.1.1.patch b/master/linux-2.6.27.25-0.1.1.patch new file mode 100644 index 0000000..0cf0cd6 --- /dev/null +++ b/master/linux-2.6.27.25-0.1.1.patch @@ -0,0 +1,8029 @@ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/powerpc/platforms/pseries/lpar.c linux-2.6.27.25-0.1.1/arch/powerpc/platforms/pseries/lpar.c +--- linux-2.6.27.23-0.1.1/arch/powerpc/platforms/pseries/lpar.c 2009-06-16 13:54:04.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/powerpc/platforms/pseries/lpar.c 2009-07-24 10:24:21.000000000 +0100 +@@ -609,3 +609,55 @@ void __init hpte_init_lpar(void) + ppc_md.flush_hash_range = pSeries_lpar_flush_hash_range; + ppc_md.hpte_clear_all = pSeries_lpar_hptab_clear; + } ++ ++#ifdef CONFIG_PPC_SMLPAR ++#define CMO_FREE_HINT_DEFAULT 1 ++static int cmo_free_hint_flag = CMO_FREE_HINT_DEFAULT; ++ ++static int __init cmo_free_hint(char *str) ++{ ++ char *parm; ++ parm = strstrip(str); ++ ++ if (strcasecmp(parm, "no") == 0 || strcasecmp(parm, "off") == 0) { ++ printk(KERN_INFO "cmo_free_hint: CMO free page hinting is not active.\n"); ++ cmo_free_hint_flag = 0; ++ return 1; ++ } ++ ++ cmo_free_hint_flag = 1; ++ printk(KERN_INFO "cmo_free_hint: CMO free page hinting is active.\n"); ++ ++ if (strcasecmp(parm, "yes") == 0 || strcasecmp(parm, "on") == 0) ++ return 1; ++ ++ return 0; ++} ++ ++__setup("cmo_free_hint=", cmo_free_hint); ++ ++static void pSeries_set_page_state(struct page *page, int order, ++ unsigned long state) ++{ ++ int i, j; ++ unsigned long cmo_page_sz, addr; ++ ++ cmo_page_sz = cmo_get_page_size(); ++ addr = __pa((unsigned long)page_address(page)); ++ ++ for (i = 0; i < (1 << order); i++, addr += PAGE_SIZE) { ++ for (j = 0; j < PAGE_SIZE; j += cmo_page_sz) ++ plpar_hcall_norets(H_PAGE_INIT, state, addr + j, 0); ++ } ++} ++ ++void arch_free_page(struct page *page, int order) ++{ ++ if (!cmo_free_hint_flag || !firmware_has_feature(FW_FEATURE_CMO)) ++ return; ++ ++ pSeries_set_page_state(page, order, H_PAGE_SET_UNUSED); ++} ++EXPORT_SYMBOL(arch_free_page); ++ ++#endif +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/sparc/kernel/of_device.c linux-2.6.27.25-0.1.1/arch/sparc/kernel/of_device.c +--- linux-2.6.27.23-0.1.1/arch/sparc/kernel/of_device.c 2009-06-16 13:53:52.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/sparc/kernel/of_device.c 2009-07-24 10:24:15.000000000 +0100 +@@ -223,8 +223,25 @@ static unsigned long of_bus_pci_get_flag + + static int of_bus_sbus_match(struct device_node *np) + { +- return !strcmp(np->name, "sbus") || +- !strcmp(np->name, "sbi"); ++ struct device_node *dp = np; ++ ++ while (dp) { ++ if (!strcmp(dp->name, "sbus") || ++ !strcmp(dp->name, "sbi")) ++ return 1; ++ ++ /* Have a look at use_1to1_mapping(). We're trying ++ * to match SBUS if that's the top-level bus and we ++ * don't have some intervening real bus that provides ++ * ranges based translations. ++ */ ++ if (of_find_property(dp, "ranges", NULL) != NULL) ++ break; ++ ++ dp = dp->parent; ++ } ++ ++ return 0; + } + + static void of_bus_sbus_count_cells(struct device_node *child, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/sparc64/kernel/irq.c linux-2.6.27.25-0.1.1/arch/sparc64/kernel/irq.c +--- linux-2.6.27.23-0.1.1/arch/sparc64/kernel/irq.c 2009-06-16 13:53:58.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/sparc64/kernel/irq.c 2009-07-24 10:24:18.000000000 +0100 +@@ -318,17 +318,25 @@ static void sun4u_set_affinity(unsigned + sun4u_irq_enable(virt_irq); + } + ++/* Don't do anything. The desc->status check for IRQ_DISABLED in ++ * handler_irq() will skip the handler call and that will leave the ++ * interrupt in the sent state. The next ->enable() call will hit the ++ * ICLR register to reset the state machine. ++ * ++ * This scheme is necessary, instead of clearing the Valid bit in the ++ * IMAP register, to handle the case of IMAP registers being shared by ++ * multiple INOs (and thus ICLR registers). Since we use a different ++ * virtual IRQ for each shared IMAP instance, the generic code thinks ++ * there is only one user so it prematurely calls ->disable() on ++ * free_irq(). ++ * ++ * We have to provide an explicit ->disable() method instead of using ++ * NULL to get the default. The reason is that if the generic code ++ * sees that, it also hooks up a default ->shutdown method which ++ * invokes ->mask() which we do not want. See irq_chip_set_defaults(). ++ */ + static void sun4u_irq_disable(unsigned int virt_irq) + { +- struct irq_handler_data *data = get_irq_chip_data(virt_irq); +- +- if (likely(data)) { +- unsigned long imap = data->imap; +- unsigned long tmp = upa_readq(imap); +- +- tmp &= ~IMAP_VALID; +- upa_writeq(tmp, imap); +- } + } + + static void sun4u_irq_eoi(unsigned int virt_irq) +@@ -739,7 +747,8 @@ void handler_irq(int irq, struct pt_regs + + desc = irq_desc + virt_irq; + +- desc->handle_irq(virt_irq, desc); ++ if (!(desc->status & IRQ_DISABLED)) ++ desc->handle_irq(virt_irq, desc); + + bucket_pa = next_pa; + } +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/sparc64/kernel/kgdb.c linux-2.6.27.25-0.1.1/arch/sparc64/kernel/kgdb.c +--- linux-2.6.27.23-0.1.1/arch/sparc64/kernel/kgdb.c 2009-06-16 13:53:58.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/sparc64/kernel/kgdb.c 2009-07-24 10:24:18.000000000 +0100 +@@ -108,7 +108,7 @@ void gdb_regs_to_pt_regs(unsigned long * + } + + #ifdef CONFIG_SMP +-void smp_kgdb_capture_client(struct pt_regs *regs) ++void smp_kgdb_capture_client(int irq, struct pt_regs *regs) + { + unsigned long flags; + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/sparc64/kernel/of_device.c linux-2.6.27.25-0.1.1/arch/sparc64/kernel/of_device.c +--- linux-2.6.27.23-0.1.1/arch/sparc64/kernel/of_device.c 2009-06-16 13:53:58.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/sparc64/kernel/of_device.c 2009-07-24 10:24:18.000000000 +0100 +@@ -278,8 +278,25 @@ static unsigned long of_bus_pci_get_flag + + static int of_bus_sbus_match(struct device_node *np) + { +- return !strcmp(np->name, "sbus") || +- !strcmp(np->name, "sbi"); ++ struct device_node *dp = np; ++ ++ while (dp) { ++ if (!strcmp(dp->name, "sbus") || ++ !strcmp(dp->name, "sbi")) ++ return 1; ++ ++ /* Have a look at use_1to1_mapping(). We're trying ++ * to match SBUS if that's the top-level bus and we ++ * don't have some intervening real bus that provides ++ * ranges based translations. ++ */ ++ if (of_find_property(dp, "ranges", NULL) != NULL) ++ break; ++ ++ dp = dp->parent; ++ } ++ ++ return 0; + } + + static void of_bus_sbus_count_cells(struct device_node *child, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/sparc64/kernel/pci_common.c linux-2.6.27.25-0.1.1/arch/sparc64/kernel/pci_common.c +--- linux-2.6.27.23-0.1.1/arch/sparc64/kernel/pci_common.c 2009-06-16 13:53:58.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/sparc64/kernel/pci_common.c 2009-07-24 10:24:18.000000000 +0100 +@@ -368,7 +368,7 @@ static void pci_register_iommu_region(st + const u32 *vdma = of_get_property(pbm->prom_node, "virtual-dma", NULL); + + if (vdma) { +- struct resource *rp = kmalloc(sizeof(*rp), GFP_KERNEL); ++ struct resource *rp = kzalloc(sizeof(*rp), GFP_KERNEL); + + if (!rp) { + prom_printf("Cannot allocate IOMMU resource.\n"); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/sparc64/kernel/smp.c linux-2.6.27.25-0.1.1/arch/sparc64/kernel/smp.c +--- linux-2.6.27.23-0.1.1/arch/sparc64/kernel/smp.c 2009-06-16 13:53:58.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/sparc64/kernel/smp.c 2009-07-24 10:24:18.000000000 +0100 +@@ -118,9 +118,9 @@ void __cpuinit smp_callin(void) + while (!cpu_isset(cpuid, smp_commenced_mask)) + rmb(); + +- ipi_call_lock(); ++ ipi_call_lock_irq(); + cpu_set(cpuid, cpu_online_map); +- ipi_call_unlock(); ++ ipi_call_unlock_irq(); + + /* idle thread is expected to have preempt disabled */ + preempt_disable(); +@@ -1031,7 +1031,7 @@ void smp_fetch_global_regs(void) + * If the address space is non-shared (ie. mm->count == 1) we avoid + * cross calls when we want to flush the currently running process's + * tlb state. This is done by clearing all cpu bits except the current +- * processor's in current->active_mm->cpu_vm_mask and performing the ++ * processor's in current->mm->cpu_vm_mask and performing the + * flush locally only. This will force any subsequent cpus which run + * this task to flush the context from the local tlb if the process + * migrates to another cpu (again). +@@ -1074,7 +1074,7 @@ void smp_flush_tlb_pending(struct mm_str + u32 ctx = CTX_HWBITS(mm->context); + int cpu = get_cpu(); + +- if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1) ++ if (mm == current->mm && atomic_read(&mm->mm_users) == 1) + mm->cpu_vm_mask = cpumask_of_cpu(cpu); + else + smp_cross_call_masked(&xcall_flush_tlb_pending, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/sparc64/kernel/ttable.S linux-2.6.27.25-0.1.1/arch/sparc64/kernel/ttable.S +--- linux-2.6.27.23-0.1.1/arch/sparc64/kernel/ttable.S 2009-06-16 13:53:58.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/sparc64/kernel/ttable.S 2009-07-24 10:24:18.000000000 +0100 +@@ -63,7 +63,13 @@ tl0_irq6: TRAP_IRQ(smp_call_function_sin + #else + tl0_irq6: BTRAP(0x46) + #endif +-tl0_irq7: BTRAP(0x47) BTRAP(0x48) BTRAP(0x49) ++tl0_irq7: BTRAP(0x47) ++#ifdef CONFIG_KGDB ++tl0_irq8: TRAP_IRQ(smp_kgdb_capture_client, 8) ++#else ++tl0_irq8: BTRAP(0x48) ++#endif ++tl0_irq9: BTRAP(0x49) + tl0_irq10: BTRAP(0x4a) BTRAP(0x4b) BTRAP(0x4c) BTRAP(0x4d) + tl0_irq14: TRAP_IRQ(timer_interrupt, 14) + tl0_irq15: TRAP_IRQ(perfctr_irq, 15) +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/sparc64/mm/ultra.S linux-2.6.27.25-0.1.1/arch/sparc64/mm/ultra.S +--- linux-2.6.27.23-0.1.1/arch/sparc64/mm/ultra.S 2009-06-16 13:53:58.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/sparc64/mm/ultra.S 2009-07-24 10:24:18.000000000 +0100 +@@ -681,28 +681,8 @@ xcall_new_mmu_context_version: + #ifdef CONFIG_KGDB + .globl xcall_kgdb_capture + xcall_kgdb_capture: +-661: rdpr %pstate, %g2 +- wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate +- .section .sun4v_2insn_patch, "ax" +- .word 661b +- nop +- nop +- .previous +- +- rdpr %pil, %g2 +- wrpr %g0, 15, %pil +- sethi %hi(109f), %g7 +- ba,pt %xcc, etrap_irq +-109: or %g7, %lo(109b), %g7 +-#ifdef CONFIG_TRACE_IRQFLAGS +- call trace_hardirqs_off +- nop +-#endif +- call smp_kgdb_capture_client +- add %sp, PTREGS_OFF, %o0 +- /* Has to be a non-v9 branch due to the large distance. */ +- ba rtrap_xcall +- ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 ++ wr %g0, (1 << PIL_KGDB_CAPTURE), %set_softint ++ retry + #endif + + #endif /* CONFIG_SMP */ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/x86/kernel/cpu/mcheck/mce_64.c linux-2.6.27.25-0.1.1/arch/x86/kernel/cpu/mcheck/mce_64.c +--- linux-2.6.27.23-0.1.1/arch/x86/kernel/cpu/mcheck/mce_64.c 2009-06-16 13:53:34.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/x86/kernel/cpu/mcheck/mce_64.c 2009-07-24 10:24:11.000000000 +0100 +@@ -352,32 +352,33 @@ void mce_log_therm_throt_event(unsigned + */ + + static int check_interval = 5 * 60; /* 5 minutes */ +-static int next_interval; /* in jiffies */ +-static void mcheck_timer(struct work_struct *work); +-static DECLARE_DELAYED_WORK(mcheck_work, mcheck_timer); ++static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ ++static void mcheck_timer(unsigned long); ++static DEFINE_PER_CPU(struct timer_list, mce_timer); + +-static void mcheck_check_cpu(void *info) ++static void mcheck_timer(unsigned long data) + { ++ struct timer_list *t = &per_cpu(mce_timer, data); ++ int *n; ++ ++ WARN_ON(smp_processor_id() != data); ++ + if (mce_available(¤t_cpu_data)) + do_machine_check(NULL, 0); +-} +- +-static void mcheck_timer(struct work_struct *work) +-{ +- on_each_cpu(mcheck_check_cpu, NULL, 1); + + /* + * Alert userspace if needed. If we logged an MCE, reduce the + * polling interval, otherwise increase the polling interval. + */ ++ n = &__get_cpu_var(next_interval); + if (mce_notify_user()) { +- next_interval = max(next_interval/2, HZ/100); ++ *n = max(*n/2, HZ/100); + } else { +- next_interval = min(next_interval * 2, +- (int)round_jiffies_relative(check_interval*HZ)); ++ *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); + } + +- schedule_delayed_work(&mcheck_work, next_interval); ++ t->expires = jiffies + *n; ++ add_timer(t); + } + + /* +@@ -425,16 +426,11 @@ static struct notifier_block mce_idle_no + + static __init int periodic_mcheck_init(void) + { +- next_interval = check_interval * HZ; +- if (next_interval) +- schedule_delayed_work(&mcheck_work, +- round_jiffies_relative(next_interval)); +- idle_notifier_register(&mce_idle_notifier); +- return 0; ++ idle_notifier_register(&mce_idle_notifier); ++ return 0; + } + __initcall(periodic_mcheck_init); + +- + /* + * Initialize Machine Checks for a CPU. + */ +@@ -504,6 +500,19 @@ static void __cpuinit mce_cpu_features(s + } + } + ++static void mce_init_timer(void) ++{ ++ struct timer_list *t = &__get_cpu_var(mce_timer); ++ int *n = &__get_cpu_var(next_interval); ++ ++ *n = check_interval * HZ; ++ if (!*n) ++ return; ++ setup_timer(t, mcheck_timer, smp_processor_id()); ++ t->expires = round_jiffies(jiffies + *n); ++ add_timer(t); ++} ++ + /* + * Called for each booted CPU to set up machine checks. + * Must be called with preempt off. +@@ -521,6 +530,7 @@ void __cpuinit mcheck_init(struct cpuinf + + mce_init(NULL); + mce_cpu_features(c); ++ mce_init_timer(); + } + + /* +@@ -740,17 +750,18 @@ static int mce_resume(struct sys_device + return 0; + } + ++static void mce_cpu_restart(void *data) ++{ ++ del_timer_sync(&__get_cpu_var(mce_timer)); ++ if (mce_available(¤t_cpu_data)) ++ mce_init(NULL); ++ mce_init_timer(); ++} ++ + /* Reinit MCEs after user configuration changes */ + static void mce_restart(void) + { +- if (next_interval) +- cancel_delayed_work(&mcheck_work); +- /* Timer race is harmless here */ +- on_each_cpu(mce_init, NULL, 1); +- next_interval = check_interval * HZ; +- if (next_interval) +- schedule_delayed_work(&mcheck_work, +- round_jiffies_relative(next_interval)); ++ on_each_cpu(mce_cpu_restart, NULL, 1); + } + + static struct sysdev_class mce_sysclass = { +@@ -879,6 +890,7 @@ static int __cpuinit mce_cpu_callback(st + unsigned long action, void *hcpu) + { + unsigned int cpu = (unsigned long)hcpu; ++ struct timer_list *t = &per_cpu(mce_timer, cpu); + + switch (action) { + case CPU_ONLINE: +@@ -893,6 +905,16 @@ static int __cpuinit mce_cpu_callback(st + threshold_cpu_callback(action, cpu); + mce_remove_device(cpu); + break; ++ case CPU_DOWN_PREPARE: ++ case CPU_DOWN_PREPARE_FROZEN: ++ del_timer_sync(t); ++ break; ++ case CPU_DOWN_FAILED: ++ case CPU_DOWN_FAILED_FROZEN: ++ t->expires = round_jiffies(jiffies + ++ __get_cpu_var(next_interval)); ++ add_timer_on(t, cpu); ++ break; + } + return NOTIFY_OK; + } +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/x86/kernel/reboot.c linux-2.6.27.25-0.1.1/arch/x86/kernel/reboot.c +--- linux-2.6.27.23-0.1.1/arch/x86/kernel/reboot.c 2009-06-16 13:39:58.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/x86/kernel/reboot.c 2009-07-24 10:24:11.000000000 +0100 +@@ -172,6 +172,24 @@ static struct dmi_system_id __initdata r + DMI_MATCH(DMI_BOARD_NAME, "0KW626"), + }, + }, ++ { /* Handle problems with rebooting on Dell Optiplex 330 with 0KP561 */ ++ .callback = set_bios_reboot, ++ .ident = "Dell OptiPlex 330", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), ++ DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 330"), ++ DMI_MATCH(DMI_BOARD_NAME, "0KP561"), ++ }, ++ }, ++ { /* Handle problems with rebooting on Dell Optiplex 360 with 0T656F */ ++ .callback = set_bios_reboot, ++ .ident = "Dell OptiPlex 360", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), ++ DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 360"), ++ DMI_MATCH(DMI_BOARD_NAME, "0T656F"), ++ }, ++ }, + { /* Handle problems with rebooting on Dell 2400's */ + .callback = set_bios_reboot, + .ident = "Dell PowerEdge 2400", +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/x86/mm/hugetlbpage.c linux-2.6.27.25-0.1.1/arch/x86/mm/hugetlbpage.c +--- linux-2.6.27.23-0.1.1/arch/x86/mm/hugetlbpage.c 2009-06-16 13:53:34.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/x86/mm/hugetlbpage.c 2009-07-24 10:24:11.000000000 +0100 +@@ -26,12 +26,16 @@ static unsigned long page_table_shareabl + unsigned long sbase = saddr & PUD_MASK; + unsigned long s_end = sbase + PUD_SIZE; + ++ /* Allow segments to share if only one is marked locked */ ++ unsigned long vm_flags = vma->vm_flags & ~VM_LOCKED; ++ unsigned long svm_flags = svma->vm_flags & ~VM_LOCKED; ++ + /* + * match the virtual addresses, permission and the alignment of the + * page table page. + */ + if (pmd_index(addr) != pmd_index(saddr) || +- vma->vm_flags != svma->vm_flags || ++ vm_flags != svm_flags || + sbase < svma->vm_start || svma->vm_end < s_end) + return 0; + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/x86/mm/init_64-xen.c linux-2.6.27.25-0.1.1/arch/x86/mm/init_64-xen.c +--- linux-2.6.27.23-0.1.1/arch/x86/mm/init_64-xen.c 2009-06-16 13:39:58.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/x86/mm/init_64-xen.c 2009-07-24 10:24:11.000000000 +0100 +@@ -420,9 +420,9 @@ phys_pte_init(pte_t *pte_page, unsigned + for(i = pte_index(addr); i < PTRS_PER_PTE; i++, addr += PAGE_SIZE, pte++) { + unsigned long pteval = addr | __PAGE_KERNEL; + +- if (addr >= (after_bootmem +- ? end +- : xen_start_info->nr_pages << PAGE_SHIFT)) ++ if (addr >= end || ++ (!after_bootmem && ++ (addr >> PAGE_SHIFT) >= xen_start_info->nr_pages)) + break; + + if (__pte_val(*pte)) +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/x86/mm/pageattr.c linux-2.6.27.25-0.1.1/arch/x86/mm/pageattr.c +--- linux-2.6.27.23-0.1.1/arch/x86/mm/pageattr.c 2009-06-16 13:39:58.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/x86/mm/pageattr.c 2009-07-24 10:24:11.000000000 +0100 +@@ -564,6 +564,17 @@ static int split_large_page(pte_t *kpte, + * primary protection behavior: + */ + __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); ++ ++ /* ++ * Intel Atom errata AAH41 workaround. ++ * ++ * The real fix should be in hw or in a microcode update, but ++ * we also probabilistically try to reduce the window of having ++ * a large TLB mixed with 4K TLBs while instruction fetches are ++ * going on. ++ */ ++ __flush_tlb_all(); ++ + base = NULL; + + out_unlock: +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/arch/x86/pci/mmconfig-shared.c linux-2.6.27.25-0.1.1/arch/x86/pci/mmconfig-shared.c +--- linux-2.6.27.23-0.1.1/arch/x86/pci/mmconfig-shared.c 2009-06-16 13:39:58.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/arch/x86/pci/mmconfig-shared.c 2009-07-24 10:24:11.000000000 +0100 +@@ -255,7 +255,7 @@ static acpi_status __init check_mcfg_res + if (!fixmem32) + return AE_OK; + if ((mcfg_res->start >= fixmem32->address) && +- (mcfg_res->end <= (fixmem32->address + ++ (mcfg_res->end < (fixmem32->address + + fixmem32->address_length))) { + mcfg_res->flags = 1; + return AE_CTRL_TERMINATE; +@@ -272,7 +272,7 @@ static acpi_status __init check_mcfg_res + return AE_OK; + + if ((mcfg_res->start >= address.minimum) && +- (mcfg_res->end <= (address.minimum + address.address_length))) { ++ (mcfg_res->end < (address.minimum + address.address_length))) { + mcfg_res->flags = 1; + return AE_CTRL_TERMINATE; + } +@@ -298,7 +298,7 @@ static int __init is_acpi_reserved(u64 s + struct resource mcfg_res; + + mcfg_res.start = start; +- mcfg_res.end = end; ++ mcfg_res.end = end - 1; + mcfg_res.flags = 0; + + acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/block/blktrace.c linux-2.6.27.25-0.1.1/block/blktrace.c +--- linux-2.6.27.23-0.1.1/block/blktrace.c 2009-06-16 13:54:10.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/block/blktrace.c 2009-07-24 10:24:24.000000000 +0100 +@@ -181,59 +181,12 @@ EXPORT_SYMBOL_GPL(__blk_add_trace); + + static struct dentry *blk_tree_root; + static DEFINE_MUTEX(blk_tree_mutex); +-static unsigned int root_users; +- +-static inline void blk_remove_root(void) +-{ +- if (blk_tree_root) { +- debugfs_remove(blk_tree_root); +- blk_tree_root = NULL; +- } +-} +- +-static void blk_remove_tree(struct dentry *dir) +-{ +- mutex_lock(&blk_tree_mutex); +- debugfs_remove(dir); +- if (--root_users == 0) +- blk_remove_root(); +- mutex_unlock(&blk_tree_mutex); +-} +- +-static struct dentry *blk_create_tree(const char *blk_name) +-{ +- struct dentry *dir = NULL; +- int created = 0; +- +- mutex_lock(&blk_tree_mutex); +- +- if (!blk_tree_root) { +- blk_tree_root = debugfs_create_dir("block", NULL); +- if (!blk_tree_root) +- goto err; +- created = 1; +- } +- +- dir = debugfs_create_dir(blk_name, blk_tree_root); +- if (dir) +- root_users++; +- else { +- /* Delete root only if we created it */ +- if (created) +- blk_remove_root(); +- } +- +-err: +- mutex_unlock(&blk_tree_mutex); +- return dir; +-} + + static void blk_trace_cleanup(struct blk_trace *bt) + { +- relay_close(bt->rchan); + debugfs_remove(bt->msg_file); + debugfs_remove(bt->dropped_file); +- blk_remove_tree(bt->dir); ++ relay_close(bt->rchan); + free_percpu(bt->sequence); + free_percpu(bt->msg_data); + kfree(bt); +@@ -336,7 +289,18 @@ static int blk_subbuf_start_callback(str + + static int blk_remove_buf_file_callback(struct dentry *dentry) + { ++ struct dentry *parent = dentry->d_parent; + debugfs_remove(dentry); ++ ++ /* ++ * this will fail for all but the last file, but that is ok. what we ++ * care about is the top level buts->name directory going away, when ++ * the last trace file is gone. Then we don't have to rmdir() that ++ * manually on trace stop, so it nicely solves the issue with ++ * force killing of running traces. ++ */ ++ ++ debugfs_remove(parent); + return 0; + } + +@@ -393,7 +357,15 @@ int do_blk_trace_setup(struct request_qu + goto err; + + ret = -ENOENT; +- dir = blk_create_tree(buts->name); ++ ++ if (!blk_tree_root) { ++ blk_tree_root = debugfs_create_dir("block", NULL); ++ if (!blk_tree_root) ++ return -ENOMEM; ++ } ++ ++ dir = debugfs_create_dir(buts->name, blk_tree_root); ++ + if (!dir) + goto err; + +@@ -436,8 +408,6 @@ int do_blk_trace_setup(struct request_qu + + return 0; + err: +- if (dir) +- blk_remove_tree(dir); + if (bt) { + if (bt->msg_file) + debugfs_remove(bt->msg_file); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/Documentation/filesystems/Locking linux-2.6.27.25-0.1.1/Documentation/filesystems/Locking +--- linux-2.6.27.23-0.1.1/Documentation/filesystems/Locking 2009-06-16 13:55:08.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/Documentation/filesystems/Locking 2009-07-24 10:24:48.000000000 +0100 +@@ -524,23 +524,31 @@ prototypes: + void (*open)(struct vm_area_struct*); + void (*close)(struct vm_area_struct*); + int (*fault)(struct vm_area_struct*, struct vm_fault *); +- int (*page_mkwrite)(struct vm_area_struct *, struct page *); ++ int (*page_mkwrite)(struct vm_area_struct *, struct vm_fault *); + int (*access)(struct vm_area_struct *, unsigned long, void*, int, int); + + locking rules: + BKL mmap_sem PageLocked(page) + open: no yes + close: no yes +-fault: no yes +-page_mkwrite: no yes no ++fault: no yes can return with page locked ++page_mkwrite: no yes can return with page locked + access: no yes + +- ->page_mkwrite() is called when a previously read-only page is +-about to become writeable. The file system is responsible for +-protecting against truncate races. Once appropriate action has been +-taking to lock out truncate, the page range should be verified to be +-within i_size. The page mapping should also be checked that it is not +-NULL. ++ ->fault() is called when a previously not present pte is about ++to be faulted in. The filesystem must find and return the page associated ++with the passed in "pgoff" in the vm_fault structure. If it is possible that ++the page may be truncated and/or invalidated, then the filesystem must lock ++the page, then ensure it is not already truncated (the page lock will block ++subsequent truncate), and then return with VM_FAULT_LOCKED, and the page ++locked. The VM will unlock the page. ++ ++ ->page_mkwrite() is called when a previously read-only pte is ++about to become writeable. The filesystem again must ensure that there are ++no truncate/invalidate races, and then return with the page locked. If ++the page has been truncated, the filesystem should not look up a new page ++like the ->fault() handler, but simply return with VM_FAULT_NOPAGE, which ++will cause the VM to retry the fault. + + ->access() is called when get_user_pages() fails in + acces_process_vm(), typically used to debug a process through +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/Documentation/kernel-parameters.txt linux-2.6.27.25-0.1.1/Documentation/kernel-parameters.txt +--- linux-2.6.27.23-0.1.1/Documentation/kernel-parameters.txt 2009-06-16 13:55:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/Documentation/kernel-parameters.txt 2009-07-24 10:24:48.000000000 +0100 +@@ -482,6 +482,13 @@ and is between 256 and 4096 characters. + Also note the kernel might malfunction if you disable + some critical bits. + ++ cmo_free_hint= [PPC] Format: { yes | no } ++ Specify whether pages are marked as being inactive ++ when they are freed. This is used in CMO environments ++ to determine OS memory pressure for page stealing by ++ a hypervisor. ++ Default: yes ++ + code_bytes [IA32/X86_64] How many bytes of object code to print + in an oops report. + Range: 0 - 8192 +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/acpi/processor_idle.c linux-2.6.27.25-0.1.1/drivers/acpi/processor_idle.c +--- linux-2.6.27.23-0.1.1/drivers/acpi/processor_idle.c 2009-06-16 13:54:32.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/acpi/processor_idle.c 2009-07-24 10:24:34.000000000 +0100 +@@ -252,6 +252,9 @@ static void acpi_timer_check_state(int s + struct acpi_processor_power *pwr = &pr->power; + u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; + ++ if (boot_cpu_has(X86_FEATURE_AMDC1E)) ++ type = ACPI_STATE_C1; ++ + /* + * Check, if one of the previous states already marked the lapic + * unstable +@@ -1110,6 +1113,7 @@ static int acpi_processor_power_verify(s + switch (cx->type) { + case ACPI_STATE_C1: + cx->valid = 1; ++ acpi_timer_check_state(i, pr, cx); + break; + + case ACPI_STATE_C2: +@@ -1428,20 +1432,22 @@ static int acpi_idle_enter_c1(struct cpu + + /* Do not access any ACPI IO ports in suspend path */ + if (acpi_idle_suspend) { +- acpi_safe_halt(); + local_irq_enable(); ++ cpu_relax(); + return 0; + } + + if (pr->flags.bm_check) + acpi_idle_update_bm_rld(pr, cx); + ++ acpi_state_timer_broadcast(pr, cx, 1); + t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); + acpi_idle_do_entry(cx); + t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); + + local_irq_enable(); + cx->usage++; ++ acpi_state_timer_broadcast(pr, cx, 0); + + return ticks_elapsed_in_us(t1, t2); + } +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/acpi/video_detect.c linux-2.6.27.25-0.1.1/drivers/acpi/video_detect.c +--- linux-2.6.27.23-0.1.1/drivers/acpi/video_detect.c 2009-06-16 13:54:32.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/acpi/video_detect.c 2009-07-24 10:24:34.000000000 +0100 +@@ -142,6 +142,25 @@ find_video(acpi_handle handle, u32 lvl, + return AE_OK; + } + ++static int set_dmi_blacklisting(const struct dmi_system_id *id) ++{ ++ printk(KERN_NOTICE "%s detected - adjusting backlight video\n", ++ id->ident); ++ acpi_video_support |= (long)id->driver_data; ++ return 0; ++} ++ ++static struct dmi_system_id video_backlight_blacklist[] = { ++ { set_dmi_blacklisting, ++ "HP 6530b", { ++ DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "6530b") ++ }, ++ (void *) ACPI_VIDEO_BACKLIGHT_DMI_VENDOR ++ }, ++ {}, ++}; ++ + /* + * Returns the video capabilities of a specific ACPI graphics device + * +@@ -176,6 +195,7 @@ long acpi_video_get_capabilities(acpi_ha + * ACPI_VIDEO_BACKLIGHT_DMI_VENDOR; + *} + */ ++ dmi_check_system(video_backlight_blacklist); + } else { + status = acpi_bus_get_device(graphics_handle, &tmp_dev); + if (ACPI_FAILURE(status)) { +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/char/random.c linux-2.6.27.25-0.1.1/drivers/char/random.c +--- linux-2.6.27.23-0.1.1/drivers/char/random.c 2009-06-16 13:54:32.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/char/random.c 2009-07-24 10:24:34.000000000 +0100 +@@ -1626,15 +1626,20 @@ EXPORT_SYMBOL(secure_dccp_sequence_numbe + * value is not cryptographically secure but for several uses the cost of + * depleting entropy is too high + */ ++DEFINE_PER_CPU(__u32 [4], get_random_int_hash); + unsigned int get_random_int(void) + { +- /* +- * Use IP's RNG. It suits our purpose perfectly: it re-keys itself +- * every second, from the entropy pool (and thus creates a limited +- * drain on it), and uses halfMD4Transform within the second. We +- * also mix it with jiffies and the PID: +- */ +- return secure_ip_id((__force __be32)(current->pid + jiffies)); ++ struct keydata *keyptr; ++ __u32 *hash = get_cpu_var(get_random_int_hash); ++ int ret; ++ ++ keyptr = get_keyptr(); ++ hash[0] += current->pid + jiffies + get_cycles(); ++ ++ ret = half_md4_transform(hash, keyptr->secret); ++ put_cpu_var(get_random_int_hash); ++ ++ return ret; + } + + /* +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/char/tpm/tpm_bios.c linux-2.6.27.25-0.1.1/drivers/char/tpm/tpm_bios.c +--- linux-2.6.27.23-0.1.1/drivers/char/tpm/tpm_bios.c 2009-06-16 13:54:32.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/char/tpm/tpm_bios.c 2009-07-24 10:24:34.000000000 +0100 +@@ -214,7 +214,8 @@ static int get_event_name(char *dest, st + unsigned char * event_entry) + { + const char *name = ""; +- char data[40] = ""; ++ /* 41 so there is room for 40 data and 1 nul */ ++ char data[41] = ""; + int i, n_len = 0, d_len = 0; + struct tcpa_pc_event *pc_event; + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/hwmon/lm78.c linux-2.6.27.25-0.1.1/drivers/hwmon/lm78.c +--- linux-2.6.27.23-0.1.1/drivers/hwmon/lm78.c 2009-06-16 13:54:40.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/hwmon/lm78.c 2009-07-24 10:24:34.000000000 +0100 +@@ -178,7 +178,7 @@ static struct platform_driver lm78_isa_d + .name = "lm78", + }, + .probe = lm78_isa_probe, +- .remove = lm78_isa_remove, ++ .remove = __devexit_p(lm78_isa_remove), + }; + + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/i2c/algos/i2c-algo-bit.c linux-2.6.27.25-0.1.1/drivers/i2c/algos/i2c-algo-bit.c +--- linux-2.6.27.23-0.1.1/drivers/i2c/algos/i2c-algo-bit.c 2009-06-16 13:54:17.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/i2c/algos/i2c-algo-bit.c 2009-07-24 10:24:24.000000000 +0100 +@@ -104,7 +104,7 @@ static int sclhi(struct i2c_algo_bit_dat + * chips may hold it low ("clock stretching") while they + * are processing data internally. + */ +- if (time_after_eq(jiffies, start + adap->timeout)) ++ if (time_after(jiffies, start + adap->timeout)) + return -ETIMEDOUT; + cond_resched(); + } +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/i2c/algos/i2c-algo-pca.c linux-2.6.27.25-0.1.1/drivers/i2c/algos/i2c-algo-pca.c +--- linux-2.6.27.23-0.1.1/drivers/i2c/algos/i2c-algo-pca.c 2009-06-16 13:54:17.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/i2c/algos/i2c-algo-pca.c 2009-07-24 10:24:24.000000000 +0100 +@@ -270,10 +270,21 @@ static int pca_xfer(struct i2c_adapter * + + case 0x30: /* Data byte in I2CDAT has been transmitted; NOT ACK has been received */ + DEB2("NOT ACK received after data byte\n"); ++ pca_stop(adap); + goto out; + + case 0x38: /* Arbitration lost during SLA+W, SLA+R or data bytes */ + DEB2("Arbitration lost\n"); ++ /* ++ * The PCA9564 data sheet (2006-09-01) says "A ++ * START condition will be transmitted when the ++ * bus becomes free (STOP or SCL and SDA high)" ++ * when the STA bit is set (p. 11). ++ * ++ * In case this won't work, try pca_reset() ++ * instead. ++ */ ++ pca_start(adap); + goto out; + + case 0x58: /* Data byte has been received; NOT ACK has been returned */ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/ide/ide-tape.c linux-2.6.27.25-0.1.1/drivers/ide/ide-tape.c +--- linux-2.6.27.23-0.1.1/drivers/ide/ide-tape.c 2009-06-16 13:54:17.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/ide/ide-tape.c 2009-07-24 10:24:24.000000000 +0100 +@@ -652,7 +652,8 @@ static void ide_tape_callback(ide_drive_ + if (readpos[0] & 0x4) { + printk(KERN_INFO "ide-tape: Block location is unknown" + "to the tape\n"); +- clear_bit(IDE_AFLAG_ADDRESS_VALID, &drive->atapi_flags); ++ clear_bit(ilog2(IDE_AFLAG_ADDRESS_VALID), ++ &drive->atapi_flags); + uptodate = 0; + } else { + debug_log(DBG_SENSE, "Block Location - %u\n", +@@ -660,7 +661,8 @@ static void ide_tape_callback(ide_drive_ + + tape->partition = readpos[1]; + tape->first_frame = be32_to_cpup((__be32 *)&readpos[4]); +- set_bit(IDE_AFLAG_ADDRESS_VALID, &drive->atapi_flags); ++ set_bit(ilog2(IDE_AFLAG_ADDRESS_VALID), ++ &drive->atapi_flags); + } + } + +@@ -736,7 +738,7 @@ static void idetape_retry_pc(ide_drive_t + pc = idetape_next_pc_storage(drive); + rq = idetape_next_rq_storage(drive); + idetape_create_request_sense_cmd(pc); +- set_bit(IDE_AFLAG_IGNORE_DSC, &drive->atapi_flags); ++ drive->atapi_flags |= IDE_AFLAG_IGNORE_DSC; + idetape_queue_pc_head(drive, pc, rq); + } + +@@ -1013,14 +1015,14 @@ static ide_startstop_t idetape_do_reques + stat = hwif->tp_ops->read_status(hwif); + + if (!drive->dsc_overlap && !(rq->cmd[13] & REQ_IDETAPE_PC2)) +- set_bit(IDE_AFLAG_IGNORE_DSC, &drive->atapi_flags); ++ drive->atapi_flags |= IDE_AFLAG_IGNORE_DSC; + + if (drive->post_reset == 1) { +- set_bit(IDE_AFLAG_IGNORE_DSC, &drive->atapi_flags); ++ drive->atapi_flags |= IDE_AFLAG_IGNORE_DSC; + drive->post_reset = 0; + } + +- if (!test_and_clear_bit(IDE_AFLAG_IGNORE_DSC, &drive->atapi_flags) && ++ if (!(drive->atapi_flags & IDE_AFLAG_IGNORE_DSC) && + (stat & SEEK_STAT) == 0) { + if (postponed_rq == NULL) { + tape->dsc_polling_start = jiffies; +@@ -1041,7 +1043,9 @@ static ide_startstop_t idetape_do_reques + tape->dsc_poll_freq = IDETAPE_DSC_MA_SLOW; + idetape_postpone_request(drive); + return ide_stopped; +- } ++ } else ++ drive->atapi_flags &= ~IDE_AFLAG_IGNORE_DSC; ++ + if (rq->cmd[13] & REQ_IDETAPE_READ) { + pc = idetape_next_pc_storage(drive); + ide_tape_create_rw_cmd(tape, pc, rq, READ_6); +@@ -1292,7 +1296,7 @@ static int idetape_wait_ready(ide_drive_ + int load_attempted = 0; + + /* Wait for the tape to become ready */ +- set_bit(IDE_AFLAG_MEDIUM_PRESENT, &drive->atapi_flags); ++ set_bit(ilog2(IDE_AFLAG_MEDIUM_PRESENT), &drive->atapi_flags); + timeout += jiffies; + while (time_before(jiffies, timeout)) { + idetape_create_test_unit_ready_cmd(&pc); +@@ -1385,7 +1389,7 @@ static void __ide_tape_discard_merge_buf + if (tape->chrdev_dir != IDETAPE_DIR_READ) + return; + +- clear_bit(IDE_AFLAG_FILEMARK, &drive->atapi_flags); ++ clear_bit(ilog2(IDE_AFLAG_FILEMARK), &drive->atapi_flags); + tape->merge_bh_size = 0; + if (tape->merge_bh != NULL) { + ide_tape_kfree_buffer(tape); +@@ -1624,7 +1628,7 @@ static int idetape_add_chrdev_read_reque + debug_log(DBG_PROCS, "Enter %s, %d blocks\n", __func__, blocks); + + /* If we are at a filemark, return a read length of 0 */ +- if (test_bit(IDE_AFLAG_FILEMARK, &drive->atapi_flags)) ++ if (test_bit(ilog2(IDE_AFLAG_FILEMARK), &drive->atapi_flags)) + return 0; + + idetape_init_read(drive); +@@ -1734,7 +1738,8 @@ static int idetape_space_over_filemarks( + + if (tape->chrdev_dir == IDETAPE_DIR_READ) { + tape->merge_bh_size = 0; +- if (test_and_clear_bit(IDE_AFLAG_FILEMARK, &drive->atapi_flags)) ++ if (test_and_clear_bit(ilog2(IDE_AFLAG_FILEMARK), ++ &drive->atapi_flags)) + ++count; + ide_tape_discard_merge_buffer(drive, 0); + } +@@ -1789,7 +1794,7 @@ static ssize_t idetape_chrdev_read(struc + debug_log(DBG_CHRDEV, "Enter %s, count %Zd\n", __func__, count); + + if (tape->chrdev_dir != IDETAPE_DIR_READ) { +- if (test_bit(IDE_AFLAG_DETECT_BS, &drive->atapi_flags)) ++ if (test_bit(ilog2(IDE_AFLAG_DETECT_BS), &drive->atapi_flags)) + if (count > tape->blk_size && + (count % tape->blk_size) == 0) + tape->user_bs_factor = count / tape->blk_size; +@@ -1829,7 +1834,8 @@ static ssize_t idetape_chrdev_read(struc + tape->merge_bh_size = bytes_read-temp; + } + finish: +- if (!actually_read && test_bit(IDE_AFLAG_FILEMARK, &drive->atapi_flags)) { ++ if (!actually_read && test_bit(ilog2(IDE_AFLAG_FILEMARK), ++ &drive->atapi_flags)) { + debug_log(DBG_SENSE, "%s: spacing over filemark\n", tape->name); + + idetape_space_over_filemarks(drive, MTFSF, 1); +@@ -2015,7 +2021,8 @@ static int idetape_mtioctop(ide_drive_t + !IDETAPE_LU_LOAD_MASK); + retval = idetape_queue_pc_tail(drive, &pc); + if (!retval) +- clear_bit(IDE_AFLAG_MEDIUM_PRESENT, &drive->atapi_flags); ++ clear_bit(ilog2(IDE_AFLAG_MEDIUM_PRESENT), ++ &drive->atapi_flags); + return retval; + case MTNOP: + ide_tape_discard_merge_buffer(drive, 0); +@@ -2038,9 +2045,11 @@ static int idetape_mtioctop(ide_drive_t + mt_count % tape->blk_size) + return -EIO; + tape->user_bs_factor = mt_count / tape->blk_size; +- clear_bit(IDE_AFLAG_DETECT_BS, &drive->atapi_flags); ++ clear_bit(ilog2(IDE_AFLAG_DETECT_BS), ++ &drive->atapi_flags); + } else +- set_bit(IDE_AFLAG_DETECT_BS, &drive->atapi_flags); ++ set_bit(ilog2(IDE_AFLAG_DETECT_BS), ++ &drive->atapi_flags); + return 0; + case MTSEEK: + ide_tape_discard_merge_buffer(drive, 0); +@@ -2190,20 +2199,20 @@ static int idetape_chrdev_open(struct in + + filp->private_data = tape; + +- if (test_and_set_bit(IDE_AFLAG_BUSY, &drive->atapi_flags)) { ++ if (test_and_set_bit(ilog2(IDE_AFLAG_BUSY), &drive->atapi_flags)) { + retval = -EBUSY; + goto out_put_tape; + } + + retval = idetape_wait_ready(drive, 60 * HZ); + if (retval) { +- clear_bit(IDE_AFLAG_BUSY, &drive->atapi_flags); ++ clear_bit(ilog2(IDE_AFLAG_BUSY), &drive->atapi_flags); + printk(KERN_ERR "ide-tape: %s: drive not ready\n", tape->name); + goto out_put_tape; + } + + idetape_read_position(drive); +- if (!test_bit(IDE_AFLAG_ADDRESS_VALID, &drive->atapi_flags)) ++ if (!test_bit(ilog2(IDE_AFLAG_ADDRESS_VALID), &drive->atapi_flags)) + (void)idetape_rewind_tape(drive); + + /* Read block size and write protect status from drive. */ +@@ -2219,7 +2228,7 @@ static int idetape_chrdev_open(struct in + if (tape->write_prot) { + if ((filp->f_flags & O_ACCMODE) == O_WRONLY || + (filp->f_flags & O_ACCMODE) == O_RDWR) { +- clear_bit(IDE_AFLAG_BUSY, &drive->atapi_flags); ++ clear_bit(ilog2(IDE_AFLAG_BUSY), &drive->atapi_flags); + retval = -EROFS; + goto out_put_tape; + } +@@ -2279,7 +2288,8 @@ static int idetape_chrdev_release(struct + ide_tape_discard_merge_buffer(drive, 1); + } + +- if (minor < 128 && test_bit(IDE_AFLAG_MEDIUM_PRESENT, &drive->atapi_flags)) ++ if (minor < 128 && test_bit(ilog2(IDE_AFLAG_MEDIUM_PRESENT), ++ &drive->atapi_flags)) + (void) idetape_rewind_tape(drive); + if (tape->chrdev_dir == IDETAPE_DIR_NONE) { + if (tape->door_locked == DOOR_LOCKED) { +@@ -2289,7 +2299,7 @@ static int idetape_chrdev_release(struct + } + } + } +- clear_bit(IDE_AFLAG_BUSY, &drive->atapi_flags); ++ clear_bit(ilog2(IDE_AFLAG_BUSY), &drive->atapi_flags); + ide_tape_put(tape); + unlock_kernel(); + return 0; +@@ -2474,7 +2484,7 @@ static void idetape_setup(ide_drive_t *d + + /* Command packet DRQ type */ + if (((gcw[0] & 0x60) >> 5) == 1) +- set_bit(IDE_AFLAG_DRQ_INTERRUPT, &drive->atapi_flags); ++ set_bit(ilog2(IDE_AFLAG_DRQ_INTERRUPT), &drive->atapi_flags); + + idetape_get_inquiry_results(drive); + idetape_get_mode_sense_results(drive); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/infiniband/ulp/ipoib/ipoib_cm.c linux-2.6.27.25-0.1.1/drivers/infiniband/ulp/ipoib/ipoib_cm.c +--- linux-2.6.27.23-0.1.1/drivers/infiniband/ulp/ipoib/ipoib_cm.c 2009-06-16 13:54:40.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/infiniband/ulp/ipoib/ipoib_cm.c 2009-07-24 10:24:34.000000000 +0100 +@@ -200,6 +200,7 @@ static void ipoib_cm_free_rx_ring(struct + ipoib_cm_dma_unmap_rx(priv, IPOIB_CM_RX_SG - 1, + rx_ring[i].mapping); + dev_kfree_skb_any(rx_ring[i].skb); ++ rx_ring[i].skb = NULL; + } + + vfree(rx_ring); +@@ -736,6 +737,7 @@ void ipoib_cm_send(struct net_device *de + if (unlikely(ib_dma_mapping_error(priv->ca, addr))) { + ++dev->stats.tx_errors; + dev_kfree_skb_any(skb); ++ tx_req->skb = NULL; + return; + } + +@@ -747,6 +749,7 @@ void ipoib_cm_send(struct net_device *de + ++dev->stats.tx_errors; + ib_dma_unmap_single(priv->ca, addr, skb->len, DMA_TO_DEVICE); + dev_kfree_skb_any(skb); ++ tx_req->skb = NULL; + } else { + dev->trans_start = jiffies; + ++tx->tx_head; +@@ -785,6 +788,7 @@ void ipoib_cm_handle_tx_wc(struct net_de + dev->stats.tx_bytes += tx_req->skb->len; + + dev_kfree_skb_any(tx_req->skb); ++ tx_req->skb = NULL; + + spin_lock_irqsave(&priv->tx_lock, flags); + ++tx->tx_tail; +@@ -1179,6 +1183,7 @@ timeout: + ib_dma_unmap_single(priv->ca, tx_req->mapping, tx_req->skb->len, + DMA_TO_DEVICE); + dev_kfree_skb_any(tx_req->skb); ++ tx_req->skb = NULL; + ++p->tx_tail; + spin_lock_irqsave(&priv->tx_lock, flags); + if (unlikely(--priv->tx_outstanding == ipoib_sendq_size >> 1) && +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/infiniband/ulp/ipoib/ipoib_ib.c linux-2.6.27.25-0.1.1/drivers/infiniband/ulp/ipoib/ipoib_ib.c +--- linux-2.6.27.23-0.1.1/drivers/infiniband/ulp/ipoib/ipoib_ib.c 2009-06-16 13:54:40.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/infiniband/ulp/ipoib/ipoib_ib.c 2009-07-24 10:24:34.000000000 +0100 +@@ -377,12 +377,14 @@ static void ipoib_ib_handle_tx_wc(struct + + tx_req = &priv->tx_ring[wr_id]; + +- ipoib_dma_unmap_tx(priv->ca, tx_req); ++ if (tx_req->skb) { ++ struct sk_buff *skb = tx_req->skb; + +- ++dev->stats.tx_packets; +- dev->stats.tx_bytes += tx_req->skb->len; +- +- dev_kfree_skb_any(tx_req->skb); ++ ipoib_dma_unmap_tx(priv->ca, tx_req); ++ ++dev->stats.tx_packets; ++ dev->stats.tx_bytes += skb->len; ++ dev_kfree_skb_any(skb); ++ } + + ++priv->tx_tail; + if (unlikely(--priv->tx_outstanding == ipoib_sendq_size >> 1) && +@@ -571,6 +573,7 @@ void ipoib_send(struct net_device *dev, + if (unlikely(ipoib_dma_map_tx(priv->ca, tx_req))) { + ++dev->stats.tx_errors; + dev_kfree_skb_any(skb); ++ tx_req->skb = NULL; + return; + } + +@@ -593,6 +596,7 @@ void ipoib_send(struct net_device *dev, + --priv->tx_outstanding; + ipoib_dma_unmap_tx(priv->ca, tx_req); + dev_kfree_skb_any(skb); ++ tx_req->skb = NULL; + if (netif_queue_stopped(dev)) + netif_wake_queue(dev); + } else { +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/leds/ledtrig-default-on.c linux-2.6.27.25-0.1.1/drivers/leds/ledtrig-default-on.c +--- linux-2.6.27.23-0.1.1/drivers/leds/ledtrig-default-on.c 2009-06-16 13:54:33.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/leds/ledtrig-default-on.c 2009-07-24 10:24:34.000000000 +0100 +@@ -23,7 +23,7 @@ static void defon_trig_activate(struct l + } + + static struct led_trigger defon_led_trigger = { +- .name = "default::on", ++ .name = "default-on", + .activate = defon_trig_activate, + }; + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/md/bitmap.c linux-2.6.27.25-0.1.1/drivers/md/bitmap.c +--- linux-2.6.27.23-0.1.1/drivers/md/bitmap.c 2009-06-16 13:54:17.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/md/bitmap.c 2009-07-24 10:24:24.000000000 +0100 +@@ -265,7 +265,6 @@ static mdk_rdev_t *next_active_rdev(mdk_ + list_for_each_continue_rcu(pos, &mddev->disks) { + rdev = list_entry(pos, mdk_rdev_t, same_set); + if (rdev->raid_disk >= 0 && +- test_bit(In_sync, &rdev->flags) && + !test_bit(Faulty, &rdev->flags)) { + /* this is a usable devices */ + atomic_inc(&rdev->nr_pending); +@@ -985,6 +984,9 @@ static int bitmap_init_from_disk(struct + oldindex = index; + oldpage = page; + ++ bitmap->filemap[bitmap->file_pages++] = page; ++ bitmap->last_page_size = count; ++ + if (outofdate) { + /* + * if bitmap is out of date, dirty the +@@ -997,15 +999,9 @@ static int bitmap_init_from_disk(struct + write_page(bitmap, page, 1); + + ret = -EIO; +- if (bitmap->flags & BITMAP_WRITE_ERROR) { +- /* release, page not in filemap yet */ +- put_page(page); ++ if (bitmap->flags & BITMAP_WRITE_ERROR) + goto err; +- } + } +- +- bitmap->filemap[bitmap->file_pages++] = page; +- bitmap->last_page_size = count; + } + paddr = kmap_atomic(page, KM_USER0); + if (bitmap->flags & BITMAP_HOSTENDIAN) +@@ -1015,9 +1011,11 @@ static int bitmap_init_from_disk(struct + kunmap_atomic(paddr, KM_USER0); + if (b) { + /* if the disk bit is set, set the memory bit */ +- bitmap_set_memory_bits(bitmap, i << CHUNK_BLOCK_SHIFT(bitmap), +- ((i+1) << (CHUNK_BLOCK_SHIFT(bitmap)) >= start) +- ); ++ int needed = ((sector_t)(i+1) << (CHUNK_BLOCK_SHIFT(bitmap)) ++ >= start); ++ bitmap_set_memory_bits(bitmap, ++ (sector_t)i << CHUNK_BLOCK_SHIFT(bitmap), ++ needed); + bit_cnt++; + set_page_attr(bitmap, page, BITMAP_PAGE_CLEAN); + } +@@ -1153,8 +1151,9 @@ void bitmap_daemon_work(struct bitmap *b + spin_lock_irqsave(&bitmap->lock, flags); + clear_page_attr(bitmap, page, BITMAP_PAGE_CLEAN); + } +- bmc = bitmap_get_counter(bitmap, j << CHUNK_BLOCK_SHIFT(bitmap), +- &blocks, 0); ++ bmc = bitmap_get_counter(bitmap, ++ (sector_t)j << CHUNK_BLOCK_SHIFT(bitmap), ++ &blocks, 0); + if (bmc) { + /* + if (j < 100) printk("bitmap: j=%lu, *bmc = 0x%x\n", j, *bmc); +@@ -1168,7 +1167,8 @@ void bitmap_daemon_work(struct bitmap *b + } else if (*bmc == 1) { + /* we can clear the bit */ + *bmc = 0; +- bitmap_count_page(bitmap, j << CHUNK_BLOCK_SHIFT(bitmap), ++ bitmap_count_page(bitmap, ++ (sector_t)j << CHUNK_BLOCK_SHIFT(bitmap), + -1); + + /* clear the bit */ +@@ -1306,6 +1306,9 @@ void bitmap_endwrite(struct bitmap *bitm + PRINTK(KERN_DEBUG "dec write-behind count %d/%d\n", + atomic_read(&bitmap->behind_writes), bitmap->max_write_behind); + } ++ if (bitmap->mddev->degraded) ++ /* Never clear bits or update events_cleared when degraded */ ++ success = 0; + + while (sectors) { + int blocks; +@@ -1508,7 +1511,7 @@ void bitmap_dirty_bits(struct bitmap *bi + unsigned long chunk; + + for (chunk = s; chunk <= e; chunk++) { +- sector_t sec = chunk << CHUNK_BLOCK_SHIFT(bitmap); ++ sector_t sec = (sector_t)chunk << CHUNK_BLOCK_SHIFT(bitmap); + bitmap_set_memory_bits(bitmap, sec, 1); + bitmap_file_set_bit(bitmap, sec); + } +@@ -1584,7 +1587,7 @@ void bitmap_destroy(mddev_t *mddev) + int bitmap_create(mddev_t *mddev) + { + struct bitmap *bitmap; +- unsigned long blocks = mddev->resync_max_sectors; ++ sector_t blocks = mddev->resync_max_sectors; + unsigned long chunks; + unsigned long pages; + struct file *file = mddev->bitmap_file; +@@ -1626,8 +1629,8 @@ int bitmap_create(mddev_t *mddev) + bitmap->chunkshift = ffz(~bitmap->chunksize); + + /* now that chunksize and chunkshift are set, we can use these macros */ +- chunks = (blocks + CHUNK_BLOCK_RATIO(bitmap) - 1) / +- CHUNK_BLOCK_RATIO(bitmap); ++ chunks = (blocks + CHUNK_BLOCK_RATIO(bitmap) - 1) >> ++ CHUNK_BLOCK_SHIFT(bitmap); + pages = (chunks + PAGE_COUNTER_RATIO - 1) / PAGE_COUNTER_RATIO; + + BUG_ON(!pages); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/md/md.c linux-2.6.27.25-0.1.1/drivers/md/md.c +--- linux-2.6.27.23-0.1.1/drivers/md/md.c 2009-06-16 13:54:17.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/md/md.c 2009-07-24 10:24:24.000000000 +0100 +@@ -305,9 +305,14 @@ static inline int mddev_trylock(mddev_t + return mutex_trylock(&mddev->reconfig_mutex); + } + ++static struct attribute_group md_redundancy_group; + static inline void mddev_unlock(mddev_t * mddev) + { + mutex_unlock(&mddev->reconfig_mutex); ++ if (unlikely(mddev->private == &md_redundancy_group)) { ++ sysfs_remove_group(&mddev->kobj, &md_redundancy_group); ++ mddev->private = NULL; ++ } + + md_wakeup_thread(mddev->thread); + } +@@ -1512,6 +1517,9 @@ static int bind_rdev_to_array(mdk_rdev_t + list_add_rcu(&rdev->same_set, &mddev->disks); + bd_claim_by_disk(rdev->bdev, rdev->bdev->bd_holder, mddev->gendisk); + md_integrity_check(rdev, mddev); ++ ++ /* May as well allow recovery to be retried once */ ++ clear_bit(MD_RECOVERY_DISABLED, &mddev->recovery); + return 0; + + fail: +@@ -1941,6 +1949,7 @@ state_store(mdk_rdev_t *rdev, const char + * -writemostly - clears write_mostly + * blocked - sets the Blocked flag + * -blocked - clears the Blocked flag ++ * insync - sets Insync providing device isn't active + */ + int err = -EINVAL; + if (cmd_match(buf, "faulty") && rdev->mddev->pers) { +@@ -1973,6 +1982,9 @@ state_store(mdk_rdev_t *rdev, const char + md_wakeup_thread(rdev->mddev->thread); + + err = 0; ++ } else if (cmd_match(buf, "insync") && rdev->raid_disk == -1) { ++ set_bit(In_sync, &rdev->flags); ++ err = 0; + } + if (!err) + sysfs_notify(&rdev->kobj, NULL, "state"); +@@ -2046,7 +2058,7 @@ slot_store(mdk_rdev_t *rdev, const char + mdk_rdev_t *rdev2; + struct list_head *tmp; + /* Activating a spare .. or possibly reactivating +- * if we every get bitmaps working here. ++ * if we ever get bitmaps working here. + */ + + if (rdev->raid_disk != -1) +@@ -2454,12 +2466,11 @@ safe_delay_store(mddev_t *mddev, const c + int i; + unsigned long msec; + char buf[30]; +- char *e; ++ + /* remove a period, and count digits after it */ + if (len >= sizeof(buf)) + return -EINVAL; +- strlcpy(buf, cbuf, len); +- buf[len] = 0; ++ strlcpy(buf, cbuf, sizeof(buf)); + for (i=0; iwrite_lock); +- } else { +- mddev->ro = 0; +- mddev->recovery_cp = MaxSector; +- err = do_md_run(mddev); +- } ++ } else ++ err = -EINVAL; + break; + case active: + if (mddev->pers) { +@@ -3581,22 +3588,12 @@ static int do_md_run(mddev_t * mddev) + return -EINVAL; + } + /* +- * chunk-size has to be a power of 2 and multiples of PAGE_SIZE ++ * chunk-size has to be a power of 2 + */ + if ( (1 << ffz(~chunk_size)) != chunk_size) { + printk(KERN_ERR "chunk_size of %d not valid\n", chunk_size); + return -EINVAL; + } +- if (chunk_size < PAGE_SIZE) { +- if (mddev->level != 0 && mddev->level != 1) { +- printk(KERN_ERR "too small chunk_size: %d < %ld\n", +- chunk_size, PAGE_SIZE); +- return -EINVAL; +- } else { +- printk(KERN_ERR "too small chunk_size: %d < %ld, but continuing anyway on raid%d. Good luck!\n", +- chunk_size, PAGE_SIZE, mddev->level); +- } +- } + + /* devices must have minimum size of one chunk */ + rdev_for_each(rdev, tmp, mddev) { +@@ -3880,6 +3877,7 @@ static int do_md_stop(mddev_t * mddev, i + { + int err = 0; + struct gendisk *disk = mddev->gendisk; ++ mdk_rdev_t *rdev; + + if (atomic_read(&mddev->openers) > is_open) { + printk("md: %s still in use.\n",mdname(mddev)); +@@ -3915,14 +3913,20 @@ static int do_md_stop(mddev_t * mddev, i + mddev->queue->merge_bvec_fn = NULL; + mddev->queue->unplug_fn = NULL; + mddev->queue->backing_dev_info.congested_fn = NULL; +- if (mddev->pers->sync_request) +- sysfs_remove_group(&mddev->kobj, &md_redundancy_group); +- + module_put(mddev->pers->owner); ++ if (mddev->pers->sync_request) ++ mddev->private = &md_redundancy_group; + mddev->pers = NULL; + /* tell userspace to handle 'inactive' */ + sysfs_notify(&mddev->kobj, NULL, "array_state"); + ++ list_for_each_entry(rdev, &mddev->disks, same_set) ++ if (rdev->raid_disk >= 0) { ++ char nm[20]; ++ sprintf(nm, "rd%d", rdev->raid_disk); ++ sysfs_remove_link(&mddev->kobj, nm); ++ } ++ + set_capacity(disk, 0); + mddev->changed = 1; + +@@ -3943,8 +3947,6 @@ static int do_md_stop(mddev_t * mddev, i + * Free resources if final stop + */ + if (mode == 0) { +- mdk_rdev_t *rdev; +- struct list_head *tmp; + + printk(KERN_INFO "md: %s stopped.\n", mdname(mddev)); + +@@ -3956,13 +3958,6 @@ static int do_md_stop(mddev_t * mddev, i + } + mddev->bitmap_offset = 0; + +- rdev_for_each(rdev, tmp, mddev) +- if (rdev->raid_disk >= 0) { +- char nm[20]; +- sprintf(nm, "rd%d", rdev->raid_disk); +- sysfs_remove_link(&mddev->kobj, nm); +- } +- + /* make sure all md_delayed_delete calls have finished */ + flush_scheduled_work(); + +@@ -4357,6 +4352,8 @@ static int add_new_disk(mddev_t * mddev, + clear_bit(In_sync, &rdev->flags); /* just to be sure */ + if (info->state & (1<flags); ++ else ++ clear_bit(WriteMostly, &rdev->flags); + + rdev->raid_disk = -1; + err = bind_rdev_to_array(rdev, mddev); +@@ -5259,37 +5256,38 @@ static void status_unused(struct seq_fil + + static void status_resync(struct seq_file *seq, mddev_t * mddev) + { +- sector_t max_blocks, resync, res; +- unsigned long dt, db, rt; ++ sector_t max_sectors, resync, res; ++ unsigned long dt, db; ++ sector_t rt; + int scale; + unsigned int per_milli; + +- resync = (mddev->curr_resync - atomic_read(&mddev->recovery_active))/2; ++ resync = mddev->curr_resync - atomic_read(&mddev->recovery_active); + + if (test_bit(MD_RECOVERY_SYNC, &mddev->recovery)) +- max_blocks = mddev->resync_max_sectors >> 1; ++ max_sectors = mddev->resync_max_sectors; + else +- max_blocks = mddev->size; ++ max_sectors = mddev->size; + + /* + * Should not happen. + */ +- if (!max_blocks) { ++ if (!max_sectors) { + MD_BUG(); + return; + } + /* Pick 'scale' such that (resync>>scale)*1000 will fit +- * in a sector_t, and (max_blocks>>scale) will fit in a ++ * in a sector_t, and (max_sectors>>scale) will fit in a + * u32, as those are the requirements for sector_div. + * Thus 'scale' must be at least 10 + */ + scale = 10; + if (sizeof(sector_t) > sizeof(unsigned long)) { +- while ( max_blocks/2 > (1ULL<<(scale+32))) ++ while ( max_sectors/2 > (1ULL<<(scale+32))) + scale++; + } + res = (resync>>scale)*1000; +- sector_div(res, (u32)((max_blocks>>scale)+1)); ++ sector_div(res, (u32)((max_sectors>>scale)+1)); + + per_milli = res; + { +@@ -5310,25 +5308,35 @@ static void status_resync(struct seq_fil + (test_bit(MD_RECOVERY_SYNC, &mddev->recovery) ? + "resync" : "recovery"))), + per_milli/10, per_milli % 10, +- (unsigned long long) resync, +- (unsigned long long) max_blocks); ++ (unsigned long long) resync/2, ++ (unsigned long long) max_sectors/2); + + /* +- * We do not want to overflow, so the order of operands and +- * the * 100 / 100 trick are important. We do a +1 to be +- * safe against division by zero. We only estimate anyway. +- * + * dt: time from mark until now + * db: blocks written from mark until now + * rt: remaining time ++ * ++ * rt is a sector_t, so could be 32bit or 64bit. ++ * So we divide before multiply in case it is 32bit and close ++ * to the limit. ++ * We scale the divisor (db) by 32 to avoid loosing precision ++ * near the end of resync when the number of remaining sectors ++ * is close to 'db'. ++ * We then divide rt by 32 after multiplying by db to compensate. ++ * The '+1' avoids division by zero if db is very small. + */ + dt = ((jiffies - mddev->resync_mark) / HZ); + if (!dt) dt++; + db = (mddev->curr_mark_cnt - atomic_read(&mddev->recovery_active)) + - mddev->resync_mark_cnt; +- rt = (dt * ((unsigned long)(max_blocks-resync) / (db/2/100+1)))/100; + +- seq_printf(seq, " finish=%lu.%lumin", rt / 60, (rt % 60)/6); ++ rt = max_sectors - resync; /* number of remaining sectors */ ++ sector_div(rt, db/32+1); ++ rt *= dt; ++ rt >>= 5; ++ ++ seq_printf(seq, " finish=%lu.%lumin", (unsigned long)rt / 60, ++ ((unsigned long)rt % 60)/6); + + seq_printf(seq, " speed=%ldK/sec", db/2/dt); + } +@@ -5588,11 +5596,11 @@ int unregister_md_personality(struct mdk + return 0; + } + +-static int is_mddev_idle(mddev_t *mddev) ++static int is_mddev_idle(mddev_t *mddev, int init) + { + mdk_rdev_t * rdev; + int idle; +- long curr_events; ++ int curr_events; + + idle = 1; + rcu_read_lock(); +@@ -5623,7 +5631,7 @@ static int is_mddev_idle(mddev_t *mddev) + * always make curr_events less than last_events. + * + */ +- if (curr_events - rdev->last_events > 4096) { ++ if (init || curr_events - (int)rdev->last_events > 64) { + rdev->last_events = curr_events; + idle = 0; + } +@@ -5867,7 +5875,7 @@ void md_do_sync(mddev_t *mddev) + "(but not more than %d KB/sec) for %s.\n", + speed_max(mddev), desc); + +- is_mddev_idle(mddev); /* this also initializes IO event counters */ ++ is_mddev_idle(mddev, 1); /* this initializes IO event counters */ + + io_sectors = 0; + for (m = 0; m < SYNC_MARKS; m++) { +@@ -5969,7 +5977,7 @@ void md_do_sync(mddev_t *mddev) + + if (currspeed > speed_min(mddev)) { + if ((currspeed > speed_max(mddev)) || +- !is_mddev_idle(mddev)) { ++ !is_mddev_idle(mddev, 0)) { + msleep(500); + goto repeat; + } +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/md/raid10.c linux-2.6.27.25-0.1.1/drivers/md/raid10.c +--- linux-2.6.27.23-0.1.1/drivers/md/raid10.c 2009-06-16 13:40:23.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/md/raid10.c 2009-07-24 10:24:24.000000000 +0100 +@@ -1802,17 +1802,17 @@ static sector_t sync_request(mddev_t *md + r10_bio->sector = sect; + + raid10_find_phys(conf, r10_bio); +- /* Need to check if this section will still be ++ ++ /* Need to check if the array will still be + * degraded + */ +- for (j=0; jcopies;j++) { +- int d = r10_bio->devs[j].devnum; +- if (conf->mirrors[d].rdev == NULL || +- test_bit(Faulty, &conf->mirrors[d].rdev->flags)) { ++ for (j=0; jraid_disks; j++) ++ if (conf->mirrors[j].rdev == NULL || ++ test_bit(Faulty, &conf->mirrors[j].rdev->flags)) { + still_degraded = 1; + break; + } +- } ++ + must_sync = bitmap_start_sync(mddev->bitmap, sect, + &sync_blocks, still_degraded); + +@@ -2025,8 +2025,9 @@ static int run(mddev_t *mddev) + int nc, fc, fo; + sector_t stride, size; + +- if (mddev->chunk_size == 0) { +- printk(KERN_ERR "md/raid10: non-zero chunk size required.\n"); ++ if (mddev->chunk_size < PAGE_SIZE) { ++ printk(KERN_ERR "md/raid10: chunk size must be " ++ "at least PAGE_SIZE(%ld).\n", PAGE_SIZE); + return -EINVAL; + } + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/md/raid5.c linux-2.6.27.25-0.1.1/drivers/md/raid5.c +--- linux-2.6.27.23-0.1.1/drivers/md/raid5.c 2009-06-16 13:54:17.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/md/raid5.c 2009-07-24 10:24:24.000000000 +0100 +@@ -135,12 +135,42 @@ static inline void raid5_set_bi_hw_segme + bio->bi_phys_segments = raid5_bi_phys_segments(bio) || (cnt << 16); + } + ++/* Find first data disk in a raid6 stripe */ ++static inline int raid6_d0(struct stripe_head *sh) ++{ ++ if (sh->ddf_layout) ++ /* ddf always start from first device */ ++ return 0; ++ /* md starts just after Q block */ ++ if (sh->qd_idx == sh->disks - 1) ++ return 0; ++ else ++ return sh->qd_idx + 1; ++} + static inline int raid6_next_disk(int disk, int raid_disks) + { + disk++; + return (disk < raid_disks) ? disk : 0; + } + ++/* When walking through the disks in a raid5, starting at raid6_d0, ++ * We need to map each disk to a 'slot', where the data disks are slot ++ * 0 .. raid_disks-3, the parity disk is raid_disks-2 and the Q disk ++ * is raid_disks-1. This help does that mapping. ++ */ ++static int raid6_idx_to_slot(int idx, struct stripe_head *sh, ++ int *count, int syndrome_disks) ++{ ++ int slot; ++ ++ if (idx == sh->pd_idx) ++ return syndrome_disks; ++ if (idx == sh->qd_idx) ++ return syndrome_disks + 1; ++ slot = (*count)++; ++ return slot; ++} ++ + static void return_io(struct bio *return_bi) + { + struct bio *bi = return_bi; +@@ -198,6 +228,7 @@ static void __release_stripe(raid5_conf_ + } + } + } ++ + static void release_stripe(struct stripe_head *sh) + { + raid5_conf_t *conf = sh->raid_conf; +@@ -276,8 +307,10 @@ static int grow_buffers(struct stripe_he + } + + static void raid5_build_block (struct stripe_head *sh, int i); ++static void stripe_set_idx(sector_t stripe, raid5_conf_t *conf, int previous, ++ struct stripe_head *sh); + +-static void init_stripe(struct stripe_head *sh, sector_t sector, int pd_idx, int disks) ++static void init_stripe(struct stripe_head *sh, sector_t sector, int previous) + { + raid5_conf_t *conf = sh->raid_conf; + int i; +@@ -292,11 +325,11 @@ static void init_stripe(struct stripe_he + + remove_hash(sh); + ++ sh->disks = previous ? conf->previous_raid_disks : conf->raid_disks; + sh->sector = sector; +- sh->pd_idx = pd_idx; ++ stripe_set_idx(sector, conf, previous, sh); + sh->state = 0; + +- sh->disks = disks; + + for (i = sh->disks; i--; ) { + struct r5dev *dev = &sh->dev[i]; +@@ -332,10 +365,12 @@ static struct stripe_head *__find_stripe + static void unplug_slaves(mddev_t *mddev); + static void raid5_unplug_device(struct request_queue *q); + +-static struct stripe_head *get_active_stripe(raid5_conf_t *conf, sector_t sector, int disks, +- int pd_idx, int noblock) ++static struct stripe_head * ++get_active_stripe(raid5_conf_t *conf, sector_t sector, ++ int previous, int noblock) + { + struct stripe_head *sh; ++ int disks = previous ? conf->previous_raid_disks : conf->raid_disks; + + pr_debug("get_stripe, sector %llu\n", (unsigned long long)sector); + +@@ -363,7 +398,7 @@ static struct stripe_head *get_active_st + ); + conf->inactive_blocked = 0; + } else +- init_stripe(sh, sector, pd_idx, disks); ++ init_stripe(sh, sector, previous); + } else { + if (atomic_read(&sh->count)) { + BUG_ON(!list_empty(&sh->lru)); +@@ -1071,7 +1106,7 @@ static void shrink_stripes(raid5_conf_t + + static void raid5_end_read_request(struct bio * bi, int error) + { +- struct stripe_head *sh = bi->bi_private; ++ struct stripe_head *sh = bi->bi_private; + raid5_conf_t *conf = sh->raid_conf; + int disks = sh->disks, i; + int uptodate = test_bit(BIO_UPTODATE, &bi->bi_flags); +@@ -1153,7 +1188,7 @@ static void raid5_end_read_request(struc + + static void raid5_end_write_request (struct bio *bi, int error) + { +- struct stripe_head *sh = bi->bi_private; ++ struct stripe_head *sh = bi->bi_private; + raid5_conf_t *conf = sh->raid_conf; + int disks = sh->disks, i; + int uptodate = test_bit(BIO_UPTODATE, &bi->bi_flags); +@@ -1232,15 +1267,20 @@ static void error(mddev_t *mddev, mdk_rd + * Input: a 'big' sector number, + * Output: index of the data and parity disk, and the sector # in them. + */ +-static sector_t raid5_compute_sector(sector_t r_sector, unsigned int raid_disks, +- unsigned int data_disks, unsigned int * dd_idx, +- unsigned int * pd_idx, raid5_conf_t *conf) ++static sector_t raid5_compute_sector(raid5_conf_t *conf, sector_t r_sector, ++ int previous, int *dd_idx, ++ struct stripe_head *sh) + { + long stripe; + unsigned long chunk_number; + unsigned int chunk_offset; ++ int pd_idx, qd_idx; ++ int ddf_layout = 0; + sector_t new_sector; + int sectors_per_chunk = conf->chunk_size >> 9; ++ int raid_disks = previous ? conf->previous_raid_disks ++ : conf->raid_disks; ++ int data_disks = raid_disks - conf->max_degraded; + + /* First compute the information on this sector */ + +@@ -1264,68 +1304,170 @@ static sector_t raid5_compute_sector(sec + /* + * Select the parity disk based on the user selected algorithm. + */ ++ pd_idx = qd_idx = ~0; + switch(conf->level) { + case 4: +- *pd_idx = data_disks; ++ pd_idx = data_disks; + break; + case 5: + switch (conf->algorithm) { + case ALGORITHM_LEFT_ASYMMETRIC: +- *pd_idx = data_disks - stripe % raid_disks; +- if (*dd_idx >= *pd_idx) ++ pd_idx = data_disks - stripe % raid_disks; ++ if (*dd_idx >= pd_idx) + (*dd_idx)++; + break; + case ALGORITHM_RIGHT_ASYMMETRIC: +- *pd_idx = stripe % raid_disks; +- if (*dd_idx >= *pd_idx) ++ pd_idx = stripe % raid_disks; ++ if (*dd_idx >= pd_idx) + (*dd_idx)++; + break; + case ALGORITHM_LEFT_SYMMETRIC: +- *pd_idx = data_disks - stripe % raid_disks; +- *dd_idx = (*pd_idx + 1 + *dd_idx) % raid_disks; ++ pd_idx = data_disks - stripe % raid_disks; ++ *dd_idx = (pd_idx + 1 + *dd_idx) % raid_disks; + break; + case ALGORITHM_RIGHT_SYMMETRIC: +- *pd_idx = stripe % raid_disks; +- *dd_idx = (*pd_idx + 1 + *dd_idx) % raid_disks; ++ pd_idx = stripe % raid_disks; ++ *dd_idx = (pd_idx + 1 + *dd_idx) % raid_disks; ++ break; ++ case ALGORITHM_PARITY_0: ++ pd_idx = 0; ++ (*dd_idx)++; ++ break; ++ case ALGORITHM_PARITY_N: ++ pd_idx = data_disks; + break; + default: + printk(KERN_ERR "raid5: unsupported algorithm %d\n", + conf->algorithm); ++ BUG(); + } + break; + case 6: + +- /**** FIX THIS ****/ + switch (conf->algorithm) { + case ALGORITHM_LEFT_ASYMMETRIC: +- *pd_idx = raid_disks - 1 - (stripe % raid_disks); +- if (*pd_idx == raid_disks-1) +- (*dd_idx)++; /* Q D D D P */ +- else if (*dd_idx >= *pd_idx) ++ pd_idx = raid_disks - 1 - (stripe % raid_disks); ++ qd_idx = pd_idx + 1; ++ if (pd_idx == raid_disks-1) { ++ (*dd_idx)++; /* Q D D D P */ ++ qd_idx = 0; ++ } else if (*dd_idx >= pd_idx) + (*dd_idx) += 2; /* D D P Q D */ + break; + case ALGORITHM_RIGHT_ASYMMETRIC: +- *pd_idx = stripe % raid_disks; +- if (*pd_idx == raid_disks-1) +- (*dd_idx)++; /* Q D D D P */ +- else if (*dd_idx >= *pd_idx) ++ pd_idx = stripe % raid_disks; ++ qd_idx = pd_idx + 1; ++ if (pd_idx == raid_disks-1) { ++ (*dd_idx)++; /* Q D D D P */ ++ qd_idx = 0; ++ } else if (*dd_idx >= pd_idx) + (*dd_idx) += 2; /* D D P Q D */ + break; + case ALGORITHM_LEFT_SYMMETRIC: +- *pd_idx = raid_disks - 1 - (stripe % raid_disks); +- *dd_idx = (*pd_idx + 2 + *dd_idx) % raid_disks; ++ pd_idx = raid_disks - 1 - (stripe % raid_disks); ++ qd_idx = (pd_idx + 1) % raid_disks; ++ *dd_idx = (pd_idx + 2 + *dd_idx) % raid_disks; + break; + case ALGORITHM_RIGHT_SYMMETRIC: +- *pd_idx = stripe % raid_disks; +- *dd_idx = (*pd_idx + 2 + *dd_idx) % raid_disks; ++ pd_idx = stripe % raid_disks; ++ qd_idx = (pd_idx + 1) % raid_disks; ++ *dd_idx = (pd_idx + 2 + *dd_idx) % raid_disks; ++ break; ++ ++ case ALGORITHM_PARITY_0: ++ pd_idx = 0; ++ qd_idx = 1; ++ (*dd_idx) += 2; ++ break; ++ case ALGORITHM_PARITY_N: ++ pd_idx = data_disks; ++ qd_idx = data_disks + 1; ++ break; ++ ++ case ALGORITHM_ROTATING_ZERO_RESTART: ++ /* Exactly the same as RIGHT_ASYMMETRIC, but or ++ * of blocks for computing Q is different. ++ */ ++ pd_idx = stripe % raid_disks; ++ qd_idx = pd_idx + 1; ++ if (pd_idx == raid_disks-1) { ++ (*dd_idx)++; /* Q D D D P */ ++ qd_idx = 0; ++ } else if (*dd_idx >= pd_idx) ++ (*dd_idx) += 2; /* D D P Q D */ ++ ddf_layout = 1; + break; ++ ++ case ALGORITHM_ROTATING_N_RESTART: ++ /* Same a left_asymmetric, by first stripe is ++ * D D D P Q rather than ++ * Q D D D P ++ */ ++ pd_idx = raid_disks - 1 - ((stripe + 1) % raid_disks); ++ qd_idx = pd_idx + 1; ++ if (pd_idx == raid_disks-1) { ++ (*dd_idx)++; /* Q D D D P */ ++ qd_idx = 0; ++ } else if (*dd_idx >= pd_idx) ++ (*dd_idx) += 2; /* D D P Q D */ ++ ddf_layout = 1; ++ break; ++ ++ case ALGORITHM_ROTATING_N_CONTINUE: ++ /* Same as left_symmetric but Q is before P */ ++ pd_idx = raid_disks - 1 - (stripe % raid_disks); ++ qd_idx = (pd_idx + raid_disks - 1) % raid_disks; ++ *dd_idx = (pd_idx + 1 + *dd_idx) % raid_disks; ++ ddf_layout = 1; ++ break; ++ ++ case ALGORITHM_LEFT_ASYMMETRIC_6: ++ /* RAID5 left_asymmetric, with Q on last device */ ++ pd_idx = data_disks - stripe % (raid_disks-1); ++ if (*dd_idx >= pd_idx) ++ (*dd_idx)++; ++ qd_idx = raid_disks - 1; ++ break; ++ ++ case ALGORITHM_RIGHT_ASYMMETRIC_6: ++ pd_idx = stripe % (raid_disks-1); ++ if (*dd_idx >= pd_idx) ++ (*dd_idx)++; ++ qd_idx = raid_disks - 1; ++ break; ++ ++ case ALGORITHM_LEFT_SYMMETRIC_6: ++ pd_idx = data_disks - stripe % (raid_disks-1); ++ *dd_idx = (pd_idx + 1 + *dd_idx) % (raid_disks-1); ++ qd_idx = raid_disks - 1; ++ break; ++ ++ case ALGORITHM_RIGHT_SYMMETRIC_6: ++ pd_idx = stripe % (raid_disks-1); ++ *dd_idx = (pd_idx + 1 + *dd_idx) % (raid_disks-1); ++ qd_idx = raid_disks - 1; ++ break; ++ ++ case ALGORITHM_PARITY_0_6: ++ pd_idx = 0; ++ (*dd_idx)++; ++ qd_idx = raid_disks - 1; ++ break; ++ ++ + default: + printk (KERN_CRIT "raid6: unsupported algorithm %d\n", + conf->algorithm); ++ BUG(); + } + break; + } + ++ if (sh) { ++ sh->pd_idx = pd_idx; ++ sh->qd_idx = qd_idx; ++ sh->ddf_layout = ddf_layout; ++ } + /* + * Finally, compute the new sector number + */ +@@ -1343,8 +1485,9 @@ static sector_t compute_blocknr(struct s + int sectors_per_chunk = conf->chunk_size >> 9; + sector_t stripe; + int chunk_offset; +- int chunk_number, dummy1, dummy2, dd_idx = i; ++ int chunk_number, dummy1, dd_idx = i; + sector_t r_sector; ++ struct stripe_head sh2; + + + chunk_offset = sector_div(new_sector, sectors_per_chunk); +@@ -1368,19 +1511,27 @@ static sector_t compute_blocknr(struct s + i += raid_disks; + i -= (sh->pd_idx + 1); + break; ++ case ALGORITHM_PARITY_0: ++ i -= 1; ++ break; ++ case ALGORITHM_PARITY_N: ++ break; + default: + printk(KERN_ERR "raid5: unsupported algorithm %d\n", + conf->algorithm); ++ BUG(); + } + break; + case 6: +- if (i == raid6_next_disk(sh->pd_idx, raid_disks)) ++ if (i == sh->qd_idx) + return 0; /* It is the Q disk */ + switch (conf->algorithm) { + case ALGORITHM_LEFT_ASYMMETRIC: + case ALGORITHM_RIGHT_ASYMMETRIC: +- if (sh->pd_idx == raid_disks-1) +- i--; /* Q D D D P */ ++ case ALGORITHM_ROTATING_ZERO_RESTART: ++ case ALGORITHM_ROTATING_N_RESTART: ++ if (sh->pd_idx == raid_disks-1) ++ i--; /* Q D D D P */ + else if (i > sh->pd_idx) + i -= 2; /* D D P Q D */ + break; +@@ -1395,9 +1546,35 @@ static sector_t compute_blocknr(struct s + i -= (sh->pd_idx + 2); + } + break; ++ case ALGORITHM_PARITY_0: ++ i -= 2; ++ break; ++ case ALGORITHM_PARITY_N: ++ break; ++ case ALGORITHM_ROTATING_N_CONTINUE: ++ if (sh->pd_idx == 0) ++ i--; /* P D D D Q */ ++ else if (i > sh->pd_idx) ++ i -= 2; /* D D Q P D */ ++ break; ++ case ALGORITHM_LEFT_ASYMMETRIC_6: ++ case ALGORITHM_RIGHT_ASYMMETRIC_6: ++ if (i > sh->pd_idx) ++ i--; ++ break; ++ case ALGORITHM_LEFT_SYMMETRIC_6: ++ case ALGORITHM_RIGHT_SYMMETRIC_6: ++ if (i < sh->pd_idx) ++ i += data_disks + 1; ++ i -= (sh->pd_idx + 1); ++ break; ++ case ALGORITHM_PARITY_0_6: ++ i -= 1; ++ break; + default: + printk (KERN_CRIT "raid6: unsupported algorithm %d\n", + conf->algorithm); ++ BUG(); + } + break; + } +@@ -1405,8 +1582,11 @@ static sector_t compute_blocknr(struct s + chunk_number = stripe * data_disks + i; + r_sector = (sector_t)chunk_number * sectors_per_chunk + chunk_offset; + +- check = raid5_compute_sector (r_sector, raid_disks, data_disks, &dummy1, &dummy2, conf); +- if (check != sh->sector || dummy1 != dd_idx || dummy2 != sh->pd_idx) { ++ check = raid5_compute_sector (conf, r_sector, ++ (raid_disks != conf->raid_disks), ++ &dummy1, &sh2); ++ if (check != sh->sector || dummy1 != dd_idx || sh2.pd_idx != sh->pd_idx ++ || sh2.qd_idx != sh->qd_idx) { + printk(KERN_ERR "compute_blocknr: map not correct\n"); + return 0; + } +@@ -1474,13 +1654,15 @@ static void copy_data(int frombio, struc + static void compute_parity6(struct stripe_head *sh, int method) + { + raid6_conf_t *conf = sh->raid_conf; +- int i, pd_idx = sh->pd_idx, qd_idx, d0_idx, disks = sh->disks, count; ++ int i, pd_idx, qd_idx, d0_idx, disks = sh->disks, count; ++ int syndrome_disks = sh->ddf_layout ? disks : (disks - 2); + struct bio *chosen; + /**** FIX THIS: This could be very bad if disks is close to 256 ****/ +- void *ptrs[disks]; ++ void *ptrs[syndrome_disks+2]; + +- qd_idx = raid6_next_disk(pd_idx, disks); +- d0_idx = raid6_next_disk(qd_idx, disks); ++ pd_idx = sh->pd_idx; ++ qd_idx = sh->qd_idx; ++ d0_idx = raid6_d0(sh); + + pr_debug("compute_parity, stripe %llu, method %d\n", + (unsigned long long)sh->sector, method); +@@ -1518,24 +1700,29 @@ static void compute_parity6(struct strip + set_bit(R5_UPTODATE, &sh->dev[i].flags); + } + +-// switch(method) { +-// case RECONSTRUCT_WRITE: +-// case CHECK_PARITY: +-// case UPDATE_PARITY: +- /* Note that unlike RAID-5, the ordering of the disks matters greatly. */ +- /* FIX: Is this ordering of drives even remotely optimal? */ +- count = 0; +- i = d0_idx; +- do { +- ptrs[count++] = page_address(sh->dev[i].page); +- if (count <= disks-2 && !test_bit(R5_UPTODATE, &sh->dev[i].flags)) +- printk("block %d/%d not uptodate on parity calc\n", i,count); +- i = raid6_next_disk(i, disks); +- } while ( i != d0_idx ); +-// break; +-// } ++ /* Note that unlike RAID-5, the ordering of the disks matters greatly.*/ + +- raid6_call.gen_syndrome(disks, STRIPE_SIZE, ptrs); ++ for (i = 0; i < disks; i++) ++ ptrs[i] = (void *)raid6_empty_zero_page; ++ ++ count = 0; ++ i = d0_idx; ++ do { ++ int slot = raid6_idx_to_slot(i, sh, &count, syndrome_disks); ++ ++ ptrs[slot] = page_address(sh->dev[i].page); ++ if (slot < syndrome_disks && ++ !test_bit(R5_UPTODATE, &sh->dev[i].flags)) { ++ printk(KERN_ERR "block %d/%d not uptodate " ++ "on parity calc\n", i, count); ++ BUG(); ++ } ++ ++ i = raid6_next_disk(i, disks); ++ } while (i != d0_idx); ++ BUG_ON(count != syndrome_disks); ++ ++ raid6_call.gen_syndrome(syndrome_disks+2, STRIPE_SIZE, ptrs); + + switch(method) { + case RECONSTRUCT_WRITE: +@@ -1557,8 +1744,7 @@ static void compute_block_1(struct strip + { + int i, count, disks = sh->disks; + void *ptr[MAX_XOR_BLOCKS], *dest, *p; +- int pd_idx = sh->pd_idx; +- int qd_idx = raid6_next_disk(pd_idx, disks); ++ int qd_idx = sh->qd_idx; + + pr_debug("compute_block_1, stripe %llu, idx %d\n", + (unsigned long long)sh->sector, dd_idx); +@@ -1594,63 +1780,65 @@ static void compute_block_1(struct strip + static void compute_block_2(struct stripe_head *sh, int dd_idx1, int dd_idx2) + { + int i, count, disks = sh->disks; +- int pd_idx = sh->pd_idx; +- int qd_idx = raid6_next_disk(pd_idx, disks); +- int d0_idx = raid6_next_disk(qd_idx, disks); +- int faila, failb; +- +- /* faila and failb are disk numbers relative to d0_idx */ +- /* pd_idx become disks-2 and qd_idx become disks-1 */ +- faila = (dd_idx1 < d0_idx) ? dd_idx1+(disks-d0_idx) : dd_idx1-d0_idx; +- failb = (dd_idx2 < d0_idx) ? dd_idx2+(disks-d0_idx) : dd_idx2-d0_idx; ++ int syndrome_disks = sh->ddf_layout ? disks : disks-2; ++ int d0_idx = raid6_d0(sh); ++ int faila = -1, failb = -1; ++ /**** FIX THIS: This could be very bad if disks is close to 256 ****/ ++ void *ptrs[syndrome_disks+2]; ++ ++ for (i = 0; i < disks ; i++) ++ ptrs[i] = (void *)raid6_empty_zero_page; ++ count = 0; ++ i = d0_idx; ++ do { ++ int slot = raid6_idx_to_slot(i, sh, &count, syndrome_disks); ++ ++ ptrs[slot] = page_address(sh->dev[i].page); ++ ++ if (i == dd_idx1) ++ faila = slot; ++ if (i == dd_idx2) ++ failb = slot; ++ i = raid6_next_disk(i, disks); ++ } while (i != d0_idx); ++ BUG_ON(count != syndrome_disks); + + BUG_ON(faila == failb); + if ( failb < faila ) { int tmp = faila; faila = failb; failb = tmp; } + + pr_debug("compute_block_2, stripe %llu, idx %d,%d (%d,%d)\n", +- (unsigned long long)sh->sector, dd_idx1, dd_idx2, faila, failb); ++ (unsigned long long)sh->sector, dd_idx1, dd_idx2, ++ faila, failb); + +- if ( failb == disks-1 ) { ++ if (failb == syndrome_disks+1) { + /* Q disk is one of the missing disks */ +- if ( faila == disks-2 ) { ++ if (faila == syndrome_disks) { + /* Missing P+Q, just recompute */ + compute_parity6(sh, UPDATE_PARITY); + return; + } else { + /* We're missing D+Q; recompute D from P */ +- compute_block_1(sh, (dd_idx1 == qd_idx) ? dd_idx2 : dd_idx1, 0); ++ compute_block_1(sh, ((dd_idx1 == sh->qd_idx) ? ++ dd_idx2 : dd_idx1), ++ 0); + compute_parity6(sh, UPDATE_PARITY); /* Is this necessary? */ + return; + } + } + +- /* We're missing D+P or D+D; build pointer table */ +- { +- /**** FIX THIS: This could be very bad if disks is close to 256 ****/ +- void *ptrs[disks]; +- +- count = 0; +- i = d0_idx; +- do { +- ptrs[count++] = page_address(sh->dev[i].page); +- i = raid6_next_disk(i, disks); +- if (i != dd_idx1 && i != dd_idx2 && +- !test_bit(R5_UPTODATE, &sh->dev[i].flags)) +- printk("compute_2 with missing block %d/%d\n", count, i); +- } while ( i != d0_idx ); +- +- if ( failb == disks-2 ) { +- /* We're missing D+P. */ +- raid6_datap_recov(disks, STRIPE_SIZE, faila, ptrs); +- } else { +- /* We're missing D+D. */ +- raid6_2data_recov(disks, STRIPE_SIZE, faila, failb, ptrs); +- } +- +- /* Both the above update both missing blocks */ +- set_bit(R5_UPTODATE, &sh->dev[dd_idx1].flags); +- set_bit(R5_UPTODATE, &sh->dev[dd_idx2].flags); ++ /* We're missing D+P or D+D; */ ++ if (failb == syndrome_disks) { ++ /* We're missing D+P. */ ++ raid6_datap_recov(syndrome_disks+2, STRIPE_SIZE, faila, ptrs); ++ } else { ++ /* We're missing D+D. */ ++ raid6_2data_recov(syndrome_disks+2, STRIPE_SIZE, faila, failb, ++ ptrs); + } ++ ++ /* Both the above update both missing blocks */ ++ set_bit(R5_UPTODATE, &sh->dev[dd_idx1].flags); ++ set_bit(R5_UPTODATE, &sh->dev[dd_idx2].flags); + } + + static void +@@ -1805,17 +1993,19 @@ static int page_is_zero(struct page *p) + memcmp(a, a+4, STRIPE_SIZE-4)==0); + } + +-static int stripe_to_pdidx(sector_t stripe, raid5_conf_t *conf, int disks) ++static void stripe_set_idx(sector_t stripe, raid5_conf_t *conf, int previous, ++ struct stripe_head *sh) + { + int sectors_per_chunk = conf->chunk_size >> 9; +- int pd_idx, dd_idx; ++ int dd_idx; + int chunk_offset = sector_div(stripe, sectors_per_chunk); ++ int disks = previous ? conf->previous_raid_disks : conf->raid_disks; + +- raid5_compute_sector(stripe * (disks - conf->max_degraded) ++ raid5_compute_sector(conf, ++ stripe * (disks - conf->max_degraded) + *sectors_per_chunk + chunk_offset, +- disks, disks - conf->max_degraded, +- &dd_idx, &pd_idx, conf); +- return pd_idx; ++ previous, ++ &dd_idx, sh); + } + + static void +@@ -2473,16 +2663,13 @@ static void handle_stripe_expansion(raid + clear_bit(STRIPE_EXPAND_SOURCE, &sh->state); + for (i = 0; i < sh->disks; i++) + if (i != sh->pd_idx && (!r6s || i != r6s->qd_idx)) { +- int dd_idx, pd_idx, j; ++ int dd_idx, j; + struct stripe_head *sh2; + + sector_t bn = compute_blocknr(sh, i); +- sector_t s = raid5_compute_sector(bn, conf->raid_disks, +- conf->raid_disks - +- conf->max_degraded, &dd_idx, +- &pd_idx, conf); +- sh2 = get_active_stripe(conf, s, conf->raid_disks, +- pd_idx, 1); ++ sector_t s = raid5_compute_sector(conf, bn, 0, ++ &dd_idx, NULL); ++ sh2 = get_active_stripe(conf, s, 0, 1); + if (sh2 == NULL) + /* so far only the early blocks of this stripe + * have been requested. When later blocks +@@ -2505,8 +2692,7 @@ static void handle_stripe_expansion(raid + set_bit(R5_UPTODATE, &sh2->dev[dd_idx].flags); + for (j = 0; j < conf->raid_disks; j++) + if (j != sh2->pd_idx && +- (!r6s || j != raid6_next_disk(sh2->pd_idx, +- sh2->disks)) && ++ (!r6s || j != sh2->qd_idx) && + !test_bit(R5_Expanded, &sh2->dev[j].flags)) + break; + if (j == conf->raid_disks) { +@@ -2768,8 +2954,7 @@ static bool handle_stripe5(struct stripe + !sh->reconstruct_state) { + /* Need to write out all blocks after computing parity */ + sh->disks = conf->raid_disks; +- sh->pd_idx = stripe_to_pdidx(sh->sector, conf, +- conf->raid_disks); ++ stripe_set_idx(sh->sector, conf, 0, sh); + schedule_reconstruction5(sh, &s, 1, 1); + } else if (s.expanded && !sh->reconstruct_state && s.locked == 0) { + clear_bit(STRIPE_EXPAND_READY, &sh->state); +@@ -2810,7 +2995,7 @@ static bool handle_stripe6(struct stripe + struct r5dev *dev, *pdev, *qdev; + mdk_rdev_t *blocked_rdev = NULL; + +- r6s.qd_idx = raid6_next_disk(pd_idx, disks); ++ r6s.qd_idx = sh->qd_idx; + pr_debug("handling stripe %llu, state=%#lx cnt=%d, " + "pd_idx=%d, qd_idx=%d\n", + (unsigned long long)sh->sector, sh->state, +@@ -2987,8 +3172,7 @@ static bool handle_stripe6(struct stripe + if (s.expanded && test_bit(STRIPE_EXPANDING, &sh->state)) { + /* Need to write out all blocks after computing P&Q */ + sh->disks = conf->raid_disks; +- sh->pd_idx = stripe_to_pdidx(sh->sector, conf, +- conf->raid_disks); ++ stripe_set_idx(sh->sector, conf, 0, sh); + compute_parity6(sh, RECONSTRUCT_WRITE); + for (i = conf->raid_disks ; i-- ; ) { + set_bit(R5_LOCKED, &sh->dev[i].flags); +@@ -3260,9 +3444,7 @@ static int chunk_aligned_read(struct req + { + mddev_t *mddev = q->queuedata; + raid5_conf_t *conf = mddev_to_conf(mddev); +- const unsigned int raid_disks = conf->raid_disks; +- const unsigned int data_disks = raid_disks - conf->max_degraded; +- unsigned int dd_idx, pd_idx; ++ unsigned int dd_idx; + struct bio* align_bi; + mdk_rdev_t *rdev; + +@@ -3271,7 +3453,7 @@ static int chunk_aligned_read(struct req + return 0; + } + /* +- * use bio_clone to make a copy of the bio ++ * use bio_clone to make a copy of the bio + */ + align_bi = bio_clone(raid_bio, GFP_NOIO); + if (!align_bi) +@@ -3285,12 +3467,9 @@ static int chunk_aligned_read(struct req + /* + * compute position + */ +- align_bi->bi_sector = raid5_compute_sector(raid_bio->bi_sector, +- raid_disks, +- data_disks, +- &dd_idx, +- &pd_idx, +- conf); ++ align_bi->bi_sector = raid5_compute_sector(conf, raid_bio->bi_sector, ++ 0, ++ &dd_idx, NULL); + + rcu_read_lock(); + rdev = rcu_dereference(conf->disks[dd_idx].rdev); +@@ -3382,7 +3561,7 @@ static int make_request(struct request_q + { + mddev_t *mddev = q->queuedata; + raid5_conf_t *conf = mddev_to_conf(mddev); +- unsigned int dd_idx, pd_idx; ++ int dd_idx; + sector_t new_sector; + sector_t logical_sector, last_sector; + struct stripe_head *sh; +@@ -3402,7 +3581,7 @@ static int make_request(struct request_q + if (rw == READ && + mddev->reshape_position == MaxSector && + chunk_aligned_read(q,bi)) +- return 0; ++ return 0; + + logical_sector = bi->bi_sector & ~((sector_t)STRIPE_SECTORS-1); + last_sector = bi->bi_sector + (bi->bi_size>>9); +@@ -3412,8 +3591,10 @@ static int make_request(struct request_q + for (;logical_sector < last_sector; logical_sector += STRIPE_SECTORS) { + DEFINE_WAIT(w); + int disks, data_disks; ++ int previous; + + retry: ++ previous = 0; + prepare_to_wait(&conf->wait_for_overlap, &w, TASK_UNINTERRUPTIBLE); + if (likely(conf->expand_progress == MaxSector)) + disks = conf->raid_disks; +@@ -3428,9 +3609,10 @@ static int make_request(struct request_q + */ + spin_lock_irq(&conf->device_lock); + disks = conf->raid_disks; +- if (logical_sector >= conf->expand_progress) ++ if (logical_sector >= conf->expand_progress) { + disks = conf->previous_raid_disks; +- else { ++ previous = 1; ++ } else { + if (logical_sector >= conf->expand_lo) { + spin_unlock_irq(&conf->device_lock); + schedule(); +@@ -3441,13 +3623,15 @@ static int make_request(struct request_q + } + data_disks = disks - conf->max_degraded; + +- new_sector = raid5_compute_sector(logical_sector, disks, data_disks, +- &dd_idx, &pd_idx, conf); ++ new_sector = raid5_compute_sector(conf, logical_sector, ++ previous, ++ &dd_idx, NULL); + pr_debug("raid5: make_request, sector %llu logical %llu\n", + (unsigned long long)new_sector, + (unsigned long long)logical_sector); + +- sh = get_active_stripe(conf, new_sector, disks, pd_idx, (bi->bi_rw&RWA_MASK)); ++ sh = get_active_stripe(conf, new_sector, previous, ++ (bi->bi_rw&RWA_MASK)); + if (sh) { + if (unlikely(conf->expand_progress != MaxSector)) { + /* expansion might have moved on while waiting for a +@@ -3529,7 +3713,6 @@ static sector_t reshape_request(mddev_t + */ + raid5_conf_t *conf = (raid5_conf_t *) mddev->private; + struct stripe_head *sh; +- int pd_idx; + sector_t first_sector, last_sector; + int raid_disks = conf->previous_raid_disks; + int data_disks = raid_disks - conf->max_degraded; +@@ -3581,9 +3764,7 @@ static sector_t reshape_request(mddev_t + for (i=0; i < conf->chunk_size/512; i+= STRIPE_SECTORS) { + int j; + int skipped = 0; +- pd_idx = stripe_to_pdidx(sector_nr+i, conf, conf->raid_disks); +- sh = get_active_stripe(conf, sector_nr+i, +- conf->raid_disks, pd_idx, 0); ++ sh = get_active_stripe(conf, sector_nr+i, 0, 0); + set_bit(STRIPE_EXPANDING, &sh->state); + atomic_inc(&conf->reshape_stripes); + /* If any of this stripe is beyond the end of the old +@@ -3594,7 +3775,7 @@ static sector_t reshape_request(mddev_t + if (j == sh->pd_idx) + continue; + if (conf->level == 6 && +- j == raid6_next_disk(sh->pd_idx, sh->disks)) ++ j == sh->qd_idx) + continue; + s = compute_blocknr(sh, j); + if (s < mddev->array_sectors) { +@@ -3620,21 +3801,16 @@ static sector_t reshape_request(mddev_t + * block on the destination stripes. + */ + first_sector = +- raid5_compute_sector(sector_nr*(new_data_disks), +- raid_disks, data_disks, +- &dd_idx, &pd_idx, conf); ++ raid5_compute_sector(conf, sector_nr*(new_data_disks), ++ 1, &dd_idx, NULL); + last_sector = +- raid5_compute_sector((sector_nr+conf->chunk_size/512) +- *(new_data_disks) -1, +- raid_disks, data_disks, +- &dd_idx, &pd_idx, conf); ++ raid5_compute_sector(conf, ((sector_nr+conf->chunk_size/512) ++ *(new_data_disks) - 1), ++ 1, &dd_idx, NULL); + if (last_sector >= (mddev->size<<1)) + last_sector = (mddev->size<<1)-1; + while (first_sector <= last_sector) { +- pd_idx = stripe_to_pdidx(first_sector, conf, +- conf->previous_raid_disks); +- sh = get_active_stripe(conf, first_sector, +- conf->previous_raid_disks, pd_idx, 0); ++ sh = get_active_stripe(conf, first_sector, 1, 0); + set_bit(STRIPE_EXPAND_SOURCE, &sh->state); + set_bit(STRIPE_HANDLE, &sh->state); + release_stripe(sh); +@@ -3667,8 +3843,6 @@ static inline sector_t sync_request(mdde + { + raid5_conf_t *conf = (raid5_conf_t *) mddev->private; + struct stripe_head *sh; +- int pd_idx; +- int raid_disks = conf->raid_disks; + sector_t max_sector = mddev->size << 1; + int sync_blocks; + int still_degraded = 0; +@@ -3723,10 +3897,9 @@ static inline sector_t sync_request(mdde + + bitmap_cond_end_sync(mddev->bitmap, sector_nr); + +- pd_idx = stripe_to_pdidx(sector_nr, conf, raid_disks); +- sh = get_active_stripe(conf, sector_nr, raid_disks, pd_idx, 1); ++ sh = get_active_stripe(conf, sector_nr, 0, 1); + if (sh == NULL) { +- sh = get_active_stripe(conf, sector_nr, raid_disks, pd_idx, 0); ++ sh = get_active_stripe(conf, sector_nr, 0, 0); + /* make sure we don't swamp the stripe cache if someone else + * is trying to get access + */ +@@ -3768,19 +3941,15 @@ static int retry_aligned_read(raid5_con + * it will be only one 'dd_idx' and only need one call to raid5_compute_sector. + */ + struct stripe_head *sh; +- int dd_idx, pd_idx; ++ int dd_idx; + sector_t sector, logical_sector, last_sector; + int scnt = 0; + int remaining; + int handled = 0; + + logical_sector = raid_bio->bi_sector & ~((sector_t)STRIPE_SECTORS-1); +- sector = raid5_compute_sector( logical_sector, +- conf->raid_disks, +- conf->raid_disks - conf->max_degraded, +- &dd_idx, +- &pd_idx, +- conf); ++ sector = raid5_compute_sector(conf, logical_sector, ++ 0, &dd_idx, NULL); + last_sector = raid_bio->bi_sector + (raid_bio->bi_size>>9); + + for (; logical_sector < last_sector; +@@ -3792,7 +3961,7 @@ static int retry_aligned_read(raid5_con + /* already done this stripe */ + continue; + +- sh = get_active_stripe(conf, sector, conf->raid_disks, pd_idx, 1); ++ sh = get_active_stripe(conf, sector, 0, 1); + + if (!sh) { + /* failed to get a stripe - must wait */ +@@ -4008,6 +4177,19 @@ static int run(mddev_t *mddev) + mdname(mddev), mddev->level); + return -EIO; + } ++ if ((mddev->level == 5 && !algorithm_valid_raid5(mddev->layout)) || ++ (mddev->level == 6 && !algorithm_valid_raid6(mddev->layout))) { ++ printk(KERN_ERR "raid5: %s: layout %d not supported\n", ++ mdname(mddev), mddev->layout); ++ return -EIO; ++ } ++ ++ if (mddev->chunk_size < PAGE_SIZE) { ++ printk(KERN_ERR "md/raid5: chunk_size must be at least " ++ "PAGE_SIZE but %d < %ld\n", ++ mddev->chunk_size, PAGE_SIZE); ++ return -EINVAL; ++ } + + if (mddev->reshape_position != MaxSector) { + /* Check that we can continue the reshape. +@@ -4017,7 +4199,7 @@ static int run(mddev_t *mddev) + */ + sector_t here_new, here_old; + int old_disks; +- int max_degraded = (mddev->level == 5 ? 1 : 2); ++ int max_degraded = (mddev->level == 6 ? 2 : 1); + + if (mddev->new_level != mddev->level || + mddev->new_layout != mddev->layout || +@@ -4152,12 +4334,6 @@ static int run(mddev_t *mddev) + conf->chunk_size, mdname(mddev)); + goto abort; + } +- if (conf->algorithm > ALGORITHM_RIGHT_SYMMETRIC) { +- printk(KERN_ERR +- "raid5: unsupported parity algorithm %d for %s\n", +- conf->algorithm, mdname(mddev)); +- goto abort; +- } + if (mddev->degraded > conf->max_degraded) { + printk(KERN_ERR "raid5: not enough operational devices for %s" + " (%d/%d failed)\n", +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/media/video/cx88/cx88-input.c linux-2.6.27.25-0.1.1/drivers/media/video/cx88/cx88-input.c +--- linux-2.6.27.23-0.1.1/drivers/media/video/cx88/cx88-input.c 2009-06-16 13:54:48.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/media/video/cx88/cx88-input.c 2009-07-24 10:24:34.000000000 +0100 +@@ -48,8 +48,7 @@ struct cx88_IR { + + /* poll external decoder */ + int polling; +- struct work_struct work; +- struct timer_list timer; ++ struct delayed_work work; + u32 gpio_addr; + u32 last_gpio; + u32 mask_keycode; +@@ -143,27 +142,19 @@ static void cx88_ir_handle_key(struct cx + } + } + +-static void ir_timer(unsigned long data) +-{ +- struct cx88_IR *ir = (struct cx88_IR *)data; +- +- schedule_work(&ir->work); +-} +- + static void cx88_ir_work(struct work_struct *work) + { +- struct cx88_IR *ir = container_of(work, struct cx88_IR, work); ++ struct cx88_IR *ir = container_of(work, struct cx88_IR, work.work); + + cx88_ir_handle_key(ir); +- mod_timer(&ir->timer, jiffies + msecs_to_jiffies(ir->polling)); ++ schedule_delayed_work(&ir->work, msecs_to_jiffies(ir->polling)); + } + + void cx88_ir_start(struct cx88_core *core, struct cx88_IR *ir) + { + if (ir->polling) { +- setup_timer(&ir->timer, ir_timer, (unsigned long)ir); +- INIT_WORK(&ir->work, cx88_ir_work); +- schedule_work(&ir->work); ++ INIT_DELAYED_WORK(&ir->work, cx88_ir_work); ++ schedule_delayed_work(&ir->work, 0); + } + if (ir->sampling) { + core->pci_irqmask |= PCI_INT_IR_SMPINT; +@@ -179,10 +170,8 @@ void cx88_ir_stop(struct cx88_core *core + core->pci_irqmask &= ~PCI_INT_IR_SMPINT; + } + +- if (ir->polling) { +- del_timer_sync(&ir->timer); +- flush_scheduled_work(); +- } ++ if (ir->polling) ++ cancel_delayed_work_sync(&ir->work); + } + + /* ---------------------------------------------------------------------- */ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/media/video/uvc/uvc_ctrl.c linux-2.6.27.25-0.1.1/drivers/media/video/uvc/uvc_ctrl.c +--- linux-2.6.27.23-0.1.1/drivers/media/video/uvc/uvc_ctrl.c 2009-06-16 13:54:48.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/media/video/uvc/uvc_ctrl.c 2009-07-24 10:24:34.000000000 +0100 +@@ -588,6 +588,10 @@ int uvc_query_v4l2_ctrl(struct uvc_video + __u8 *data; + int ret; + ++ if ((video->dev->quirks & UVC_QUIRK_HUE_EPIPE) && ++ (v4l2_ctrl->id == V4L2_CID_HUE)) ++ return -EINVAL; ++ + ctrl = uvc_find_control(video, v4l2_ctrl->id, &mapping); + if (ctrl == NULL) + return -EINVAL; +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/media/video/uvc/uvc_driver.c linux-2.6.27.25-0.1.1/drivers/media/video/uvc/uvc_driver.c +--- linux-2.6.27.23-0.1.1/drivers/media/video/uvc/uvc_driver.c 2009-06-16 13:40:54.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/media/video/uvc/uvc_driver.c 2009-07-24 10:24:34.000000000 +0100 +@@ -1948,6 +1948,14 @@ static struct usb_device_id uvc_ids[] = + .bInterfaceSubClass = 1, + .bInterfaceProtocol = 0, + .driver_info = UVC_QUIRK_PROBE_MINMAX }, ++ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE ++ | USB_DEVICE_ID_MATCH_INT_INFO, ++ .idVendor = 0x5986, ++ .idProduct = 0x0241, ++ .bInterfaceClass = USB_CLASS_VIDEO, ++ .bInterfaceSubClass = 1, ++ .bInterfaceProtocol = 0, ++ .driver_info = UVC_QUIRK_HUE_EPIPE }, + /* Generic USB Video Class */ + { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, 0) }, + {} +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/media/video/uvc/uvcvideo.h linux-2.6.27.25-0.1.1/drivers/media/video/uvc/uvcvideo.h +--- linux-2.6.27.23-0.1.1/drivers/media/video/uvc/uvcvideo.h 2009-06-16 13:54:48.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/media/video/uvc/uvcvideo.h 2009-07-24 10:24:34.000000000 +0100 +@@ -314,6 +314,7 @@ struct uvc_xu_control { + #define UVC_QUIRK_BUILTIN_ISIGHT 0x00000008 + #define UVC_QUIRK_STREAM_NO_FID 0x00000010 + #define UVC_QUIRK_IGNORE_SELECTOR_UNIT 0x00000020 ++#define UVC_QUIRK_HUE_EPIPE 0x00000100 + + /* Format flags */ + #define UVC_FMT_FLAG_COMPRESSED 0x00000001 +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/atl1e/atl1e_ethtool.c linux-2.6.27.25-0.1.1/drivers/net/atl1e/atl1e_ethtool.c +--- linux-2.6.27.23-0.1.1/drivers/net/atl1e/atl1e_ethtool.c 2009-06-16 13:54:24.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/atl1e/atl1e_ethtool.c 2009-07-24 10:24:29.000000000 +0100 +@@ -365,6 +365,8 @@ static int atl1e_set_wol(struct net_devi + if (wol->wolopts & WAKE_PHY) + adapter->wol |= AT_WUFC_LNKC; + ++ device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); ++ + return 0; + } + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/bnx2.c linux-2.6.27.25-0.1.1/drivers/net/bnx2.c +--- linux-2.6.27.23-0.1.1/drivers/net/bnx2.c 2009-06-16 13:54:24.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/bnx2.c 2009-07-24 10:24:29.000000000 +0100 +@@ -2578,6 +2578,7 @@ bnx2_get_hw_tx_cons(struct bnx2_napi *bn + /* Tell compiler that status block fields can change. */ + barrier(); + cons = *bnapi->hw_tx_cons_ptr; ++ barrier(); + if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT)) + cons++; + return cons; +@@ -2851,6 +2852,7 @@ bnx2_get_hw_rx_cons(struct bnx2_napi *bn + /* Tell compiler that status block fields can change. */ + barrier(); + cons = *bnapi->hw_rx_cons_ptr; ++ barrier(); + if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)) + cons++; + return cons; +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/bnx2x.h linux-2.6.27.25-0.1.1/drivers/net/bnx2x.h +--- linux-2.6.27.23-0.1.1/drivers/net/bnx2x.h 2009-06-16 13:54:24.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/bnx2x.h 2009-07-24 10:24:29.000000000 +0100 +@@ -152,7 +152,7 @@ struct sw_rx_page { + #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) + #define SGE_PAGE_SIZE PAGE_SIZE + #define SGE_PAGE_SHIFT PAGE_SHIFT +-#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN(addr) ++#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))addr) + + #define BCM_RX_ETH_PAYLOAD_ALIGN 64 + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/bnx2x_init.h linux-2.6.27.25-0.1.1/drivers/net/bnx2x_init.h +--- linux-2.6.27.23-0.1.1/drivers/net/bnx2x_init.h 2009-06-16 13:54:24.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/bnx2x_init.h 2009-07-24 10:24:29.000000000 +0100 +@@ -150,7 +150,6 @@ static void bnx2x_init_ind_wr(struct bnx + + static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len) + { +-#ifdef USE_DMAE + int offset = 0; + + if (bp->dmae_ready) { +@@ -164,9 +163,6 @@ static void bnx2x_write_big_buf(struct b + addr + offset, len); + } else + bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len); +-#else +- bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len); +-#endif + } + + static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/bnx2x_main.c linux-2.6.27.25-0.1.1/drivers/net/bnx2x_main.c +--- linux-2.6.27.23-0.1.1/drivers/net/bnx2x_main.c 2009-06-16 13:54:24.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/bnx2x_main.c 2009-07-24 10:24:29.000000000 +0100 +@@ -57,7 +57,7 @@ + #include "bnx2x.h" + #include "bnx2x_init.h" + +-#define DRV_MODULE_VERSION "1.45.26" ++#define DRV_MODULE_VERSION "1.45.27" + #define DRV_MODULE_RELDATE "2009/01/26" + #define BNX2X_BC_VER 0x040200 + +@@ -4038,10 +4038,10 @@ static void bnx2x_zero_sb(struct bnx2x * + { + int port = BP_PORT(bp); + +- bnx2x_init_fill(bp, BAR_USTRORM_INTMEM + ++ bnx2x_init_fill(bp, USTORM_INTMEM_ADDR + + USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, + sizeof(struct ustorm_status_block)/4); +- bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM + ++ bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR + + CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, + sizeof(struct cstorm_status_block)/4); + } +@@ -4095,18 +4095,18 @@ static void bnx2x_zero_def_sb(struct bnx + { + int func = BP_FUNC(bp); + +- bnx2x_init_fill(bp, BAR_USTRORM_INTMEM + ++ bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR + ++ TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, ++ sizeof(struct tstorm_def_status_block)/4); ++ bnx2x_init_fill(bp, USTORM_INTMEM_ADDR + + USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, + sizeof(struct ustorm_def_status_block)/4); +- bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM + ++ bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR + + CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, + sizeof(struct cstorm_def_status_block)/4); +- bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM + ++ bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR + + XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, + sizeof(struct xstorm_def_status_block)/4); +- bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM + +- TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, +- sizeof(struct tstorm_def_status_block)/4); + } + + static void bnx2x_init_def_sb(struct bnx2x *bp, +@@ -4521,7 +4521,8 @@ static void bnx2x_init_context(struct bn + (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA | + USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING); + context->ustorm_st_context.common.sge_buff_size = +- (u16)(BCM_PAGE_SIZE*PAGES_PER_SGE); ++ (u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE, ++ (u32)0xffff); + context->ustorm_st_context.common.sge_page_base_hi = + U64_HI(fp->rx_sge_mapping); + context->ustorm_st_context.common.sge_page_base_lo = +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/bonding/bond_alb.c linux-2.6.27.25-0.1.1/drivers/net/bonding/bond_alb.c +--- linux-2.6.27.23-0.1.1/drivers/net/bonding/bond_alb.c 2009-06-16 13:54:24.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/bonding/bond_alb.c 2009-07-24 10:24:29.000000000 +0100 +@@ -1716,9 +1716,6 @@ int bond_alb_set_mac_address(struct net_ + } + } + +- write_unlock_bh(&bond->curr_slave_lock); +- read_unlock(&bond->lock); +- + if (swap_slave) { + alb_swap_mac_addr(bond, swap_slave, bond->curr_active_slave); + alb_fasten_mac_swap(bond, swap_slave, bond->curr_active_slave); +@@ -1726,16 +1723,15 @@ int bond_alb_set_mac_address(struct net_ + alb_set_slave_mac_addr(bond->curr_active_slave, bond_dev->dev_addr, + bond->alb_info.rlb_enabled); + ++ read_lock(&bond->lock); + alb_send_learning_packets(bond->curr_active_slave, bond_dev->dev_addr); + if (bond->alb_info.rlb_enabled) { + /* inform clients mac address has changed */ + rlb_req_update_slave_clients(bond, bond->curr_active_slave); + } ++ read_unlock(&bond->lock); + } + +- read_lock(&bond->lock); +- write_lock_bh(&bond->curr_slave_lock); +- + return 0; + } + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/cxgb3/cxgb3_main.c linux-2.6.27.25-0.1.1/drivers/net/cxgb3/cxgb3_main.c +--- linux-2.6.27.23-0.1.1/drivers/net/cxgb3/cxgb3_main.c 2009-06-16 13:54:24.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/cxgb3/cxgb3_main.c 2009-07-24 10:24:29.000000000 +0100 +@@ -1222,6 +1222,9 @@ static int cxgb_close(struct net_device + struct port_info *pi = netdev_priv(dev); + struct adapter *adapter = pi->adapter; + ++ if (!adapter->open_device_map) ++ return 0; ++ + t3_port_intr_disable(adapter, pi->port_id); + netif_stop_queue(dev); + pi->phy.ops->power_down(&pi->phy, 1); +@@ -2738,6 +2741,9 @@ static pci_ers_result_t t3_io_error_dete + struct adapter *adapter = pci_get_drvdata(pdev); + int ret; + ++ if (state == pci_channel_io_perm_failure) ++ return PCI_ERS_RESULT_DISCONNECT; ++ + ret = t3_adapter_error(adapter, 0); + + /* Request a slot reset. */ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/e1000/e1000_main.c linux-2.6.27.25-0.1.1/drivers/net/e1000/e1000_main.c +--- linux-2.6.27.23-0.1.1/drivers/net/e1000/e1000_main.c 2009-06-16 13:54:24.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/e1000/e1000_main.c 2009-07-24 10:24:29.000000000 +0100 +@@ -4133,8 +4133,9 @@ static bool e1000_clean_rx_irq(struct e1 + PCI_DMA_FROMDEVICE); + + length = le16_to_cpu(rx_desc->length); +- +- if (unlikely(!(status & E1000_RXD_STAT_EOP))) { ++ /* !EOP means multiple descriptors were used to store a single ++ * packet, also make sure the frame isn't just CRC only */ ++ if (unlikely(!(status & E1000_RXD_STAT_EOP) || (length <= 4))) { + /* All receives must fit into a single buffer */ + E1000_DBG("%s: Receive packet consumed multiple" + " buffers\n", netdev->name); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/ehea/ehea.h linux-2.6.27.25-0.1.1/drivers/net/ehea/ehea.h +--- linux-2.6.27.23-0.1.1/drivers/net/ehea/ehea.h 2009-06-16 13:40:30.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/ehea/ehea.h 2009-07-24 10:24:29.000000000 +0100 +@@ -40,7 +40,7 @@ + #include + + #define DRV_NAME "ehea" +-#define DRV_VERSION "EHEA_0094-03" ++#define DRV_VERSION "EHEA_0094-02" + + /* eHEA capability flags */ + #define DLPAR_PORT_ADD_REM 1 +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/igb/igb_ethtool.c linux-2.6.27.25-0.1.1/drivers/net/igb/igb_ethtool.c +--- linux-2.6.27.23-0.1.1/drivers/net/igb/igb_ethtool.c 2009-06-16 13:54:17.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/igb/igb_ethtool.c 2009-07-24 10:24:29.000000000 +0100 +@@ -2025,9 +2025,9 @@ static struct ethtool_ops igb_ethtool_op + .get_ethtool_stats = igb_get_ethtool_stats, + .get_coalesce = igb_get_coalesce, + .set_coalesce = igb_set_coalesce, +-#ifdef NETIF_F_LRO +- .get_flags = ethtool_op_get_flags, +- .set_flags = ethtool_op_set_flags, ++ .get_flags = ethtool_op_get_flags, ++#ifdef CONFIG_IGB_LRO ++ .set_flags = ethtool_op_set_flags, + #endif + }; + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/macvlan.c linux-2.6.27.25-0.1.1/drivers/net/macvlan.c +--- linux-2.6.27.23-0.1.1/drivers/net/macvlan.c 2009-06-16 13:54:24.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/macvlan.c 2009-07-24 10:24:29.000000000 +0100 +@@ -328,7 +328,8 @@ static u32 macvlan_ethtool_get_rx_csum(s + const struct macvlan_dev *vlan = netdev_priv(dev); + struct net_device *lowerdev = vlan->lowerdev; + +- if (lowerdev->ethtool_ops->get_rx_csum == NULL) ++ if (lowerdev->ethtool_ops == NULL || ++ lowerdev->ethtool_ops->get_rx_csum == NULL) + return 0; + return lowerdev->ethtool_ops->get_rx_csum(lowerdev); + } +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/myri10ge/myri10ge.c linux-2.6.27.25-0.1.1/drivers/net/myri10ge/myri10ge.c +--- linux-2.6.27.23-0.1.1/drivers/net/myri10ge/myri10ge.c 2009-06-16 13:54:24.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/myri10ge/myri10ge.c 2009-07-24 10:24:29.000000000 +0100 +@@ -2379,6 +2379,7 @@ static int myri10ge_open(struct net_devi + lro_mgr->lro_arr = ss->rx_done.lro_desc; + lro_mgr->get_frag_header = myri10ge_get_frag_header; + lro_mgr->max_aggr = myri10ge_lro_max_pkts; ++ lro_mgr->frag_align_pad = 2; + if (lro_mgr->max_aggr > MAX_SKB_FRAGS) + lro_mgr->max_aggr = MAX_SKB_FRAGS; + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/r8169.c linux-2.6.27.25-0.1.1/drivers/net/r8169.c +--- linux-2.6.27.23-0.1.1/drivers/net/r8169.c 2009-06-16 13:40:30.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/r8169.c 2009-07-24 10:24:29.000000000 +0100 +@@ -66,7 +66,6 @@ static const int multicast_filter_limit + #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ + #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ + #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ +-#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ + #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ + #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ + +@@ -2141,10 +2140,10 @@ static u16 rtl_rw_cpluscmd(void __iomem + return cmd; + } + +-static void rtl_set_rx_max_size(void __iomem *ioaddr) ++static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) + { + /* Low hurts. Let's disable the filtering. */ +- RTL_W16(RxMaxSize, 16383); ++ RTL_W16(RxMaxSize, rx_buf_sz); + } + + static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) +@@ -2191,7 +2190,7 @@ static void rtl_hw_start_8169(struct net + + RTL_W8(EarlyTxThres, EarlyTxThld); + +- rtl_set_rx_max_size(ioaddr); ++ rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); + + if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || + (tp->mac_version == RTL_GIGA_MAC_VER_02) || +@@ -2294,7 +2293,7 @@ static void rtl_hw_start_8168(struct net + + RTL_W8(EarlyTxThres, EarlyTxThld); + +- rtl_set_rx_max_size(ioaddr); ++ rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); + + rtl_set_rx_tx_config_registers(tp); + +@@ -2425,7 +2424,7 @@ static void rtl_hw_start_8101(struct net + + RTL_W8(EarlyTxThres, EarlyTxThld); + +- rtl_set_rx_max_size(ioaddr); ++ rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); + + tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/wireless/iwlwifi/iwl-agn.c linux-2.6.27.25-0.1.1/drivers/net/wireless/iwlwifi/iwl-agn.c +--- linux-2.6.27.23-0.1.1/drivers/net/wireless/iwlwifi/iwl-agn.c 2009-06-16 13:54:24.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/wireless/iwlwifi/iwl-agn.c 2009-07-24 10:24:29.000000000 +0100 +@@ -3227,9 +3227,7 @@ static void iwl4965_mac_update_tkip_key( + struct iwl_priv *priv = hw->priv; + u8 sta_id = IWL_INVALID_STATION; + unsigned long flags; +- __le16 key_flags = 0; + int i; +- DECLARE_MAC_BUF(mac); + + IWL_DEBUG_MAC80211("enter\n"); + +@@ -3246,16 +3244,8 @@ static void iwl4965_mac_update_tkip_key( + return; + } + +- key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK); +- key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); +- key_flags &= ~STA_KEY_FLG_INVALID; +- +- if (sta_id == priv->hw_params.bcast_sta_id) +- key_flags |= STA_KEY_MULTICAST_MSK; +- + spin_lock_irqsave(&priv->sta_lock, flags); + +- priv->stations[sta_id].sta.key.key_flags = key_flags; + priv->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32; + + for (i = 0; i < 5; i++) +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/net/wireless/iwlwifi/iwl-sta.c linux-2.6.27.25-0.1.1/drivers/net/wireless/iwlwifi/iwl-sta.c +--- linux-2.6.27.23-0.1.1/drivers/net/wireless/iwlwifi/iwl-sta.c 2009-06-16 13:54:24.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/net/wireless/iwlwifi/iwl-sta.c 2009-07-24 10:24:29.000000000 +0100 +@@ -688,6 +688,14 @@ static int iwl_set_tkip_dynamic_key_info + { + unsigned long flags; + int ret = 0; ++ __le16 key_flags = 0; ++ ++ key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK); ++ key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); ++ key_flags &= ~STA_KEY_FLG_INVALID; ++ ++ if (sta_id == priv->hw_params.bcast_sta_id) ++ key_flags |= STA_KEY_MULTICAST_MSK; + + keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; + keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; +@@ -707,6 +715,9 @@ static int iwl_set_tkip_dynamic_key_info + WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, + "no space for new kew"); + ++ priv->stations[sta_id].sta.key.key_flags = key_flags; ++ ++ + /* This copy is acutally not needed: we get the key with each TX */ + memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, 16); + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/s390/net/qeth_core_mpc.c linux-2.6.27.25-0.1.1/drivers/s390/net/qeth_core_mpc.c +--- linux-2.6.27.23-0.1.1/drivers/s390/net/qeth_core_mpc.c 2009-06-16 13:54:40.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/s390/net/qeth_core_mpc.c 2009-07-24 10:24:34.000000000 +0100 +@@ -181,6 +181,8 @@ static struct ipa_rc_msg qeth_ipa_rc_msg + {IPA_RC_L2_ADDR_TABLE_FULL, "Layer2 address table full"}, + {IPA_RC_L2_DUP_LAYER3_MAC, "Duplicate with layer 3 MAC"}, + {IPA_RC_L2_GMAC_NOT_FOUND, "GMAC not found"}, ++ {IPA_RC_L2_MAC_NOT_AUTH_BY_HYP, "L2 mac not authorized by hypervisor"}, ++ {IPA_RC_L2_MAC_NOT_AUTH_BY_ADP, "L2 mac not authorized by adapter"}, + {IPA_RC_L2_MAC_NOT_FOUND, "L2 mac address not found"}, + {IPA_RC_L2_INVALID_VLAN_ID, "L2 invalid vlan id"}, + {IPA_RC_L2_DUP_VLAN_ID, "L2 duplicate vlan id"}, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/s390/net/qeth_core_mpc.h linux-2.6.27.25-0.1.1/drivers/s390/net/qeth_core_mpc.h +--- linux-2.6.27.23-0.1.1/drivers/s390/net/qeth_core_mpc.h 2009-06-16 13:54:40.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/s390/net/qeth_core_mpc.h 2009-07-24 10:24:34.000000000 +0100 +@@ -168,6 +168,8 @@ enum qeth_ipa_return_codes { + IPA_RC_L2_ADDR_TABLE_FULL = 0x2006, + IPA_RC_L2_DUP_LAYER3_MAC = 0x200a, + IPA_RC_L2_GMAC_NOT_FOUND = 0x200b, ++ IPA_RC_L2_MAC_NOT_AUTH_BY_HYP = 0x200c, ++ IPA_RC_L2_MAC_NOT_AUTH_BY_ADP = 0x200d, + IPA_RC_L2_MAC_NOT_FOUND = 0x2010, + IPA_RC_L2_INVALID_VLAN_ID = 0x2015, + IPA_RC_L2_DUP_VLAN_ID = 0x2016, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/s390/net/qeth_l2_main.c linux-2.6.27.25-0.1.1/drivers/s390/net/qeth_l2_main.c +--- linux-2.6.27.23-0.1.1/drivers/s390/net/qeth_l2_main.c 2009-06-16 13:40:46.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/s390/net/qeth_l2_main.c 2009-07-24 10:24:34.000000000 +0100 +@@ -504,6 +504,30 @@ static int qeth_l2_send_setmac_cb(struct + if (cmd->hdr.return_code) { + QETH_DBF_TEXT_(TRACE, 2, "L2er%x", cmd->hdr.return_code); + card->info.mac_bits &= ~QETH_LAYER2_MAC_REGISTERED; ++ switch (cmd->hdr.return_code) { ++ case IPA_RC_L2_DUP_MAC: ++ case IPA_RC_L2_DUP_LAYER3_MAC: ++ dev_warn(&card->gdev->dev, ++ "MAC address " ++ "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " ++ "already exists\n", ++ card->dev->dev_addr[0], card->dev->dev_addr[1], ++ card->dev->dev_addr[2], card->dev->dev_addr[3], ++ card->dev->dev_addr[4], card->dev->dev_addr[5]); ++ break; ++ case IPA_RC_L2_MAC_NOT_AUTH_BY_HYP: ++ case IPA_RC_L2_MAC_NOT_AUTH_BY_ADP: ++ dev_warn(&card->gdev->dev, ++ "MAC address " ++ "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " ++ "is not authorized\n", ++ card->dev->dev_addr[0], card->dev->dev_addr[1], ++ card->dev->dev_addr[2], card->dev->dev_addr[3], ++ card->dev->dev_addr[4], card->dev->dev_addr[5]); ++ break; ++ default: ++ break; ++ } + cmd->hdr.return_code = -EIO; + } else { + card->info.mac_bits |= QETH_LAYER2_MAC_REGISTERED; +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/s390/net/qeth_l3_main.c linux-2.6.27.25-0.1.1/drivers/s390/net/qeth_l3_main.c +--- linux-2.6.27.23-0.1.1/drivers/s390/net/qeth_l3_main.c 2009-06-16 13:40:46.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/s390/net/qeth_l3_main.c 2009-07-24 10:24:34.000000000 +0100 +@@ -1939,16 +1939,22 @@ static inline __u16 qeth_l3_rebuild_skb( + hdr->hdr.l3.vlan_id : *((u16 *)&hdr->hdr.l3.dest_addr[12]); + } + +- skb->ip_summed = card->options.checksum_type; +- if (card->options.checksum_type == HW_CHECKSUMMING) { ++ switch (card->options.checksum_type) { ++ case SW_CHECKSUMMING: ++ skb->ip_summed = CHECKSUM_NONE; ++ break; ++ case NO_CHECKSUMMING: ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ break; ++ case HW_CHECKSUMMING: + if ((hdr->hdr.l3.ext_flags & +- (QETH_HDR_EXT_CSUM_HDR_REQ | +- QETH_HDR_EXT_CSUM_TRANSP_REQ)) == +- (QETH_HDR_EXT_CSUM_HDR_REQ | +- QETH_HDR_EXT_CSUM_TRANSP_REQ)) ++ (QETH_HDR_EXT_CSUM_HDR_REQ | ++ QETH_HDR_EXT_CSUM_TRANSP_REQ)) == ++ (QETH_HDR_EXT_CSUM_HDR_REQ | ++ QETH_HDR_EXT_CSUM_TRANSP_REQ)) + skb->ip_summed = CHECKSUM_UNNECESSARY; + else +- skb->ip_summed = SW_CHECKSUMMING; ++ skb->ip_summed = CHECKSUM_NONE; + } + + return vlan_id; +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/scsi/3w-xxxx.c linux-2.6.27.25-0.1.1/drivers/scsi/3w-xxxx.c +--- linux-2.6.27.23-0.1.1/drivers/scsi/3w-xxxx.c 2009-06-16 13:54:40.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/scsi/3w-xxxx.c 2009-07-24 10:24:34.000000000 +0100 +@@ -6,7 +6,7 @@ + Arnaldo Carvalho de Melo + Brad Strand + +- Copyright (C) 1999-2007 3ware Inc. ++ Copyright (C) 1999-2009 3ware Inc. + + Kernel compatiblity By: Andre Hedrick + Non-Copyright (C) 2000 Andre Hedrick +@@ -1294,7 +1294,8 @@ static void tw_unmap_scsi_data(struct pc + { + dprintk(KERN_WARNING "3w-xxxx: tw_unmap_scsi_data()\n"); + +- scsi_dma_unmap(cmd); ++ if (cmd->SCp.phase == TW_PHASE_SGLIST) ++ scsi_dma_unmap(cmd); + } /* End tw_unmap_scsi_data() */ + + /* This function will reset a device extension */ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/scsi/3w-xxxx.h linux-2.6.27.25-0.1.1/drivers/scsi/3w-xxxx.h +--- linux-2.6.27.23-0.1.1/drivers/scsi/3w-xxxx.h 2009-06-16 13:54:40.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/scsi/3w-xxxx.h 2009-07-24 10:24:34.000000000 +0100 +@@ -6,7 +6,7 @@ + Arnaldo Carvalho de Melo + Brad Strand + +- Copyright (C) 1999-2007 3ware Inc. ++ Copyright (C) 1999-2009 3ware Inc. + + Kernel compatiblity By: Andre Hedrick + Non-Copyright (C) 2000 Andre Hedrick +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/scsi/device_handler/scsi_dh_rdac.c linux-2.6.27.25-0.1.1/drivers/scsi/device_handler/scsi_dh_rdac.c +--- linux-2.6.27.23-0.1.1/drivers/scsi/device_handler/scsi_dh_rdac.c 2009-06-16 13:40:47.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/scsi/device_handler/scsi_dh_rdac.c 2009-07-24 10:24:34.000000000 +0100 +@@ -607,6 +607,8 @@ static const struct scsi_dh_devlist rdac + {"SGI", "TP9500", 0}, + {"SGI", "IS", 0}, + {"STK", "OPENstorage D280", 0}, ++ {"STK", "FLEXLINE 380", 0}, ++ {"SUN", "STK6580_6780", 0}, + {"SUN", "CSM200_R", 0}, + {"SUN", "LCSM100_F", 0}, + {"DELL", "MD3000", 0}, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/scsi/libiscsi.c linux-2.6.27.25-0.1.1/drivers/scsi/libiscsi.c +--- linux-2.6.27.23-0.1.1/drivers/scsi/libiscsi.c 2009-06-16 13:40:47.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/scsi/libiscsi.c 2009-07-24 10:24:34.000000000 +0100 +@@ -413,11 +413,6 @@ static void fail_command(struct iscsi_co + conn->session->queued_cmdsn--; + else + conn->session->tt->cleanup_task(conn, task); +- /* +- * Check if cleanup_task dropped the lock and the command completed, +- */ +- if (!task->sc) +- return; + + sc->result = err; + if (!scsi_bidi_cmnd(sc)) +@@ -1247,13 +1242,7 @@ int iscsi_queuecommand(struct scsi_cmnd + goto fault; + } + +- /* +- * ISCSI_STATE_FAILED is a temp. state. The recovery +- * code will decide what is best to do with command queued +- * during this time +- */ +- if (session->state != ISCSI_STATE_LOGGED_IN && +- session->state != ISCSI_STATE_FAILED) { ++ if (session->state != ISCSI_STATE_LOGGED_IN) { + /* + * to handle the race between when we set the recovery state + * and block the session we requeue here (commands could +@@ -1261,12 +1250,15 @@ int iscsi_queuecommand(struct scsi_cmnd + * up because the block code is not locked) + */ + switch (session->state) { ++ case ISCSI_STATE_FAILED: + case ISCSI_STATE_IN_RECOVERY: + reason = FAILURE_SESSION_IN_RECOVERY; +- goto reject; ++ sc->result = DID_IMM_RETRY << 16; ++ break; + case ISCSI_STATE_LOGGING_OUT: + reason = FAILURE_SESSION_LOGGING_OUT; +- goto reject; ++ sc->result = DID_IMM_RETRY << 16; ++ break; + case ISCSI_STATE_RECOVERY_FAILED: + reason = FAILURE_SESSION_RECOVERY_TIMEOUT; + sc->result = DID_TRANSPORT_FAILFAST << 16; +@@ -1498,8 +1490,11 @@ static void fail_all_commands(struct isc + { + struct iscsi_task *task, *tmp; + +- if (conn->task && (conn->task->sc->device->lun == lun || lun == -1)) +- conn->task = NULL; ++ if (conn->task) { ++ if (lun == -1 || ++ (conn->task->sc && conn->task->sc->device->lun == lun)) ++ conn->task = NULL; ++ } + + /* flush pending */ + list_for_each_entry_safe(task, tmp, &conn->xmitqueue, running) { +@@ -1836,10 +1831,10 @@ int iscsi_eh_device_reset(struct scsi_cm + + iscsi_suspend_tx(conn); + +- spin_lock(&session->lock); ++ spin_lock_bh(&session->lock); + fail_all_commands(conn, sc->device->lun, DID_ERROR); + conn->tmf_state = TMF_INITIAL; +- spin_unlock(&session->lock); ++ spin_unlock_bh(&session->lock); + + iscsi_start_tx(conn); + goto done; +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/scsi/scsi_devinfo.c linux-2.6.27.25-0.1.1/drivers/scsi/scsi_devinfo.c +--- linux-2.6.27.23-0.1.1/drivers/scsi/scsi_devinfo.c 2009-06-16 13:54:40.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/scsi/scsi_devinfo.c 2009-07-24 10:24:34.000000000 +0100 +@@ -152,7 +152,7 @@ static struct { + {"DGC", "RAID", NULL, BLIST_SPARSELUN}, /* Dell PV 650F, storage on LUN 0 */ + {"DGC", "DISK", NULL, BLIST_SPARSELUN}, /* Dell PV 650F, no storage on LUN 0 */ + {"EMC", "Invista", "*", BLIST_SPARSELUN | BLIST_LARGELUN}, +- {"EMC", "SYMMETRIX", NULL, BLIST_SPARSELUN | BLIST_LARGELUN | BLIST_FORCELUN}, ++ {"EMC", "SYMMETRIX", NULL, BLIST_SPARSELUN | BLIST_LARGELUN | BLIST_REPORTLUN2}, + {"EMULEX", "MD21/S2 ESDI", NULL, BLIST_SINGLELUN}, + {"easyRAID", "16P", NULL, BLIST_NOREPORTLUN}, + {"easyRAID", "X6P", NULL, BLIST_NOREPORTLUN}, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/serial/icom.c linux-2.6.27.25-0.1.1/drivers/serial/icom.c +--- linux-2.6.27.23-0.1.1/drivers/serial/icom.c 2009-06-16 13:54:54.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/serial/icom.c 2009-07-24 10:24:36.000000000 +0100 +@@ -1482,8 +1482,8 @@ static void icom_remove_adapter(struct i + + free_irq(icom_adapter->pci_dev->irq, (void *) icom_adapter); + iounmap(icom_adapter->base_addr); +- icom_free_adapter(icom_adapter); + pci_release_regions(icom_adapter->pci_dev); ++ icom_free_adapter(icom_adapter); + } + + static void icom_kref_release(struct kref *kref) +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/serial/mpc52xx_uart.c linux-2.6.27.25-0.1.1/drivers/serial/mpc52xx_uart.c +--- linux-2.6.27.23-0.1.1/drivers/serial/mpc52xx_uart.c 2009-06-16 13:54:54.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/serial/mpc52xx_uart.c 2009-07-24 10:24:36.000000000 +0100 +@@ -515,7 +515,7 @@ mpc52xx_uart_startup(struct uart_port *p + + /* Request IRQ */ + ret = request_irq(port->irq, mpc52xx_uart_int, +- IRQF_DISABLED | IRQF_SAMPLE_RANDOM | IRQF_SHARED, ++ IRQF_DISABLED | IRQF_SAMPLE_RANDOM, + "mpc52xx_psc_uart", port); + if (ret) + return ret; +@@ -1000,7 +1000,7 @@ mpc52xx_console_setup(struct console *co + pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n", + co, co->index, options); + +- if ((co->index < 0) || (co->index > MPC52xx_PSC_MAXNUM)) { ++ if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) { + pr_debug("PSC%x out of range\n", co->index); + return -EINVAL; + } +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/usb/gadget/usbstring.c linux-2.6.27.25-0.1.1/drivers/usb/gadget/usbstring.c +--- linux-2.6.27.23-0.1.1/drivers/usb/gadget/usbstring.c 2009-06-16 13:54:32.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/usb/gadget/usbstring.c 2009-07-24 10:24:29.000000000 +0100 +@@ -38,7 +38,7 @@ static int utf8_to_utf16le(const char *s + uchar = (c & 0x1f) << 6; + + c = (u8) *s++; +- if ((c & 0xc0) != 0xc0) ++ if ((c & 0xc0) != 0x80) + goto fail; + c &= 0x3f; + uchar |= c; +@@ -49,13 +49,13 @@ static int utf8_to_utf16le(const char *s + uchar = (c & 0x0f) << 12; + + c = (u8) *s++; +- if ((c & 0xc0) != 0xc0) ++ if ((c & 0xc0) != 0x80) + goto fail; + c &= 0x3f; + uchar |= c << 6; + + c = (u8) *s++; +- if ((c & 0xc0) != 0xc0) ++ if ((c & 0xc0) != 0x80) + goto fail; + c &= 0x3f; + uchar |= c; +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/usb/host/isp1760-hcd.c linux-2.6.27.25-0.1.1/drivers/usb/host/isp1760-hcd.c +--- linux-2.6.27.23-0.1.1/drivers/usb/host/isp1760-hcd.c 2009-06-16 13:54:24.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/usb/host/isp1760-hcd.c 2009-07-24 10:24:29.000000000 +0100 +@@ -1645,6 +1645,7 @@ static int isp1760_urb_dequeue(struct us + u32 reg_base, or_reg, skip_reg; + unsigned long flags; + struct ptd ptd; ++ packet_enqueue *pe; + + switch (usb_pipetype(urb->pipe)) { + case PIPE_ISOCHRONOUS: +@@ -1656,6 +1657,7 @@ static int isp1760_urb_dequeue(struct us + reg_base = INT_REGS_OFFSET; + or_reg = HC_INT_IRQ_MASK_OR_REG; + skip_reg = HC_INT_PTD_SKIPMAP_REG; ++ pe = enqueue_an_INT_packet; + break; + + default: +@@ -1663,6 +1665,7 @@ static int isp1760_urb_dequeue(struct us + reg_base = ATL_REGS_OFFSET; + or_reg = HC_ATL_IRQ_MASK_OR_REG; + skip_reg = HC_ATL_PTD_SKIPMAP_REG; ++ pe = enqueue_an_ATL_packet; + break; + } + +@@ -1674,6 +1677,7 @@ static int isp1760_urb_dequeue(struct us + u32 skip_map; + u32 or_map; + struct isp1760_qtd *qtd; ++ struct isp1760_qh *qh = ints->qh; + + skip_map = isp1760_readl(hcd->regs + skip_reg); + skip_map |= 1 << i; +@@ -1686,8 +1690,7 @@ static int isp1760_urb_dequeue(struct us + priv_write_copy(priv, (u32 *)&ptd, hcd->regs + reg_base + + i * sizeof(ptd), sizeof(ptd)); + qtd = ints->qtd; +- +- clean_up_qtdlist(qtd); ++ qtd = clean_up_qtdlist(qtd); + + free_mem(priv, ints->payload); + +@@ -1698,7 +1701,24 @@ static int isp1760_urb_dequeue(struct us + ints->payload = 0; + + isp1760_urb_done(priv, urb, status); ++ if (qtd) ++ pe(hcd, qh, qtd); + break; ++ ++ } else if (ints->qtd) { ++ struct isp1760_qtd *qtd, *prev_qtd = ints->qtd; ++ ++ for (qtd = ints->qtd->hw_next; qtd; qtd = qtd->hw_next) { ++ if (qtd->urb == urb) { ++ prev_qtd->hw_next = clean_up_qtdlist(qtd); ++ isp1760_urb_done(priv, urb, status); ++ break; ++ } ++ prev_qtd = qtd; ++ } ++ /* we found the urb before the end of the list */ ++ if (qtd) ++ break; + } + ints++; + } +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/usb/serial/ti_usb_3410_5052.c linux-2.6.27.25-0.1.1/drivers/usb/serial/ti_usb_3410_5052.c +--- linux-2.6.27.23-0.1.1/drivers/usb/serial/ti_usb_3410_5052.c 2009-06-16 13:54:32.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/usb/serial/ti_usb_3410_5052.c 2009-07-24 10:24:29.000000000 +0100 +@@ -240,7 +240,6 @@ static struct usb_device_id ti_id_table_ + { USB_DEVICE(TI_VENDOR_ID, TI_5152_BOOT_PRODUCT_ID) }, + { USB_DEVICE(TI_VENDOR_ID, TI_5052_EEPROM_PRODUCT_ID) }, + { USB_DEVICE(TI_VENDOR_ID, TI_5052_FIRMWARE_PRODUCT_ID) }, +- { USB_DEVICE(IBM_VENDOR_ID, IBM_4543_PRODUCT_ID) }, + }; + + static struct usb_device_id ti_id_table_combined[14+2*TI_EXTRA_VID_PID_COUNT+1] = { +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/video/fb_defio.c linux-2.6.27.25-0.1.1/drivers/video/fb_defio.c +--- linux-2.6.27.23-0.1.1/drivers/video/fb_defio.c 2009-06-16 13:54:48.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/video/fb_defio.c 2009-07-24 10:24:34.000000000 +0100 +@@ -70,8 +70,9 @@ EXPORT_SYMBOL_GPL(fb_deferred_io_fsync); + + /* vm_ops->page_mkwrite handler */ + static int fb_deferred_io_mkwrite(struct vm_area_struct *vma, +- struct page *page) ++ struct vm_fault *vmf) + { ++ struct page *page = vmf->page; + struct fb_info *info = vma->vm_private_data; + struct fb_deferred_io *fbdefio = info->fbdefio; + struct page *cur; +@@ -111,7 +112,7 @@ page_already_added: + + static struct vm_operations_struct fb_deferred_io_vm_ops = { + .fault = fb_deferred_io_fault, +- .page_mkwrite = fb_deferred_io_mkwrite, ++ ._pmkw.page_mkwrite2 = fb_deferred_io_mkwrite, + }; + + static int fb_deferred_io_set_page_dirty(struct page *page) +@@ -128,7 +129,7 @@ static const struct address_space_operat + static int fb_deferred_io_mmap(struct fb_info *info, struct vm_area_struct *vma) + { + vma->vm_ops = &fb_deferred_io_vm_ops; +- vma->vm_flags |= ( VM_IO | VM_RESERVED | VM_DONTEXPAND ); ++ vma->vm_flags |= ( VM_IO | VM_RESERVED | VM_DONTEXPAND | VM_PAGE_MKWRITE2 ); + vma->vm_private_data = info; + return 0; + } +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/xen/blkfront/blkfront.c linux-2.6.27.25-0.1.1/drivers/xen/blkfront/blkfront.c +--- linux-2.6.27.23-0.1.1/drivers/xen/blkfront/blkfront.c 2009-06-16 13:40:39.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/xen/blkfront/blkfront.c 2009-07-24 10:24:34.000000000 +0100 +@@ -285,8 +285,10 @@ static void backend_changed(struct xenbu + break; + + case XenbusStateClosing: +- if (!info->gd) ++ if (!info->gd) { ++ xenbus_frontend_closed(dev); + break; ++ } + bd = bdget_disk(info->gd, 0); + if (bd == NULL) + xenbus_dev_fatal(dev, -ENODEV, "bdget failed"); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/drivers/xen/core/spinlock.c linux-2.6.27.25-0.1.1/drivers/xen/core/spinlock.c +--- linux-2.6.27.23-0.1.1/drivers/xen/core/spinlock.c 2009-06-16 13:40:39.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/drivers/xen/core/spinlock.c 2009-07-24 10:24:29.000000000 +0100 +@@ -5,6 +5,8 @@ + * portions of this file. + */ + ++#if CONFIG_XEN_COMPAT >= 0x030200 ++ + #include + #include + #include +@@ -160,3 +162,5 @@ void xen_spin_kick(raw_spinlock_t *lock, + } + } + EXPORT_SYMBOL(xen_spin_kick); ++ ++#endif /* CONFIG_XEN_COMPAT >= 0x030200 */ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/buffer.c linux-2.6.27.25-0.1.1/fs/buffer.c +--- linux-2.6.27.23-0.1.1/fs/buffer.c 2009-06-16 13:39:37.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/buffer.c 2009-07-24 10:23:52.000000000 +0100 +@@ -2413,6 +2413,51 @@ int block_commit_write(struct page *page + * unlock the page. + */ + int ++block_page_mkwrite2(struct vm_area_struct *vma, struct vm_fault *vmf, ++ get_block_t get_block) ++{ ++ struct page *page = vmf->page; ++ struct inode *inode = vma->vm_file->f_path.dentry->d_inode; ++ unsigned long end; ++ loff_t size; ++ int ret = VM_FAULT_NOPAGE; /* make the VM retry the fault */ ++ ++ lock_page(page); ++ size = i_size_read(inode); ++ if ((page->mapping != inode->i_mapping) || ++ (page_offset(page) > size)) { ++ /* page got truncated out from underneath us */ ++ unlock_page(page); ++ goto out; ++ } ++ ++ /* page is wholly or partially inside EOF */ ++ if (((page->index + 1) << PAGE_CACHE_SHIFT) > size) ++ end = size & ~PAGE_CACHE_MASK; ++ else ++ end = PAGE_CACHE_SIZE; ++ ++ ret = block_prepare_write(page, 0, end, get_block); ++ if (!ret) ++ ret = block_commit_write(page, 0, end); ++ ++ if (unlikely(ret)) { ++ unlock_page(page); ++ if (ret == -ENOMEM) ++ ret = VM_FAULT_OOM; ++ else /* -ENOSPC, -EIO, etc */ ++ ret = VM_FAULT_SIGBUS; ++ } else ++ ret = VM_FAULT_LOCKED; ++ ++out: ++ return ret; ++} ++ ++/* ++ * XXX: ABI hack ++ */ ++int + block_page_mkwrite(struct vm_area_struct *vma, struct page *page, + get_block_t get_block) + { +@@ -3366,6 +3411,7 @@ EXPORT_SYMBOL(__wait_on_buffer); + EXPORT_SYMBOL(block_commit_write); + EXPORT_SYMBOL(block_prepare_write); + EXPORT_SYMBOL(block_page_mkwrite); ++EXPORT_SYMBOL(block_page_mkwrite2); + EXPORT_SYMBOL(block_read_full_page); + EXPORT_SYMBOL(block_sync_page); + EXPORT_SYMBOL(block_truncate_page); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/cifs/cifssmb.c linux-2.6.27.25-0.1.1/fs/cifs/cifssmb.c +--- linux-2.6.27.23-0.1.1/fs/cifs/cifssmb.c 2009-06-16 13:39:36.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/cifs/cifssmb.c 2009-07-24 10:23:52.000000000 +0100 +@@ -91,23 +91,22 @@ static int + cifs_strncpy_to_host(char **dst, const char *src, const int maxlen, + const bool is_unicode, const struct nls_table *nls_codepage) + { +- int plen; ++ int src_len, dst_len; + + if (is_unicode) { +- plen = UniStrnlen((wchar_t *)src, maxlen); +- *dst = kmalloc(plen + 2, GFP_KERNEL); ++ src_len = UniStrnlen((wchar_t *)src, maxlen); ++ *dst = kmalloc((4 * src_len) + 2, GFP_KERNEL); + if (!*dst) + goto cifs_strncpy_to_host_ErrExit; +- cifs_strfromUCS_le(*dst, (__le16 *)src, plen, nls_codepage); ++ dst_len = cifs_strfromUCS_le(*dst, (__le16 *)src, src_len, nls_codepage); ++ (*dst)[dst_len + 1] = 0; + } else { +- plen = strnlen(src, maxlen); +- *dst = kmalloc(plen + 2, GFP_KERNEL); ++ src_len = strnlen(src, maxlen); ++ *dst = kmalloc(src_len + 1, GFP_KERNEL); + if (!*dst) + goto cifs_strncpy_to_host_ErrExit; +- strncpy(*dst, src, plen); ++ strlcpy(*dst, src, src_len + 1); + } +- (*dst)[plen] = 0; +- (*dst)[plen+1] = 0; /* harmless for ASCII case, needed for Unicode */ + return 0; + + cifs_strncpy_to_host_ErrExit: +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/cifs/cifs_unicode.h linux-2.6.27.25-0.1.1/fs/cifs/cifs_unicode.h +--- linux-2.6.27.23-0.1.1/fs/cifs/cifs_unicode.h 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/cifs/cifs_unicode.h 2009-07-24 10:23:52.000000000 +0100 +@@ -64,6 +64,13 @@ int cifs_strtoUCS(__le16 *, const char * + #endif + + /* ++ * To be safe - for UCS to UTF-8 with strings loaded with the rare long ++ * characters alloc more to account for such multibyte target UTF-8 ++ * characters. ++ */ ++#define UNICODE_NAME_MAX ((4 * NAME_MAX) + 2) ++ ++/* + * UniStrcat: Concatenate the second string to the first + * + * Returns: +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/cifs/connect.c linux-2.6.27.25-0.1.1/fs/cifs/connect.c +--- linux-2.6.27.23-0.1.1/fs/cifs/connect.c 2009-06-16 13:39:36.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/cifs/connect.c 2009-07-24 10:23:52.000000000 +0100 +@@ -3549,16 +3549,12 @@ CIFSTCon(unsigned int xid, struct cifsSe + BCC(smb_buffer_response)) { + kfree(tcon->nativeFileSystem); + tcon->nativeFileSystem = +- kzalloc(2*(length + 1), GFP_KERNEL); ++ kzalloc((4 * length) + 2, GFP_KERNEL); + if (tcon->nativeFileSystem) + cifs_strfromUCS_le( + tcon->nativeFileSystem, + (__le16 *) bcc_ptr, + length, nls_codepage); +- bcc_ptr += 2 * length; +- bcc_ptr[0] = 0; /* null terminate the string */ +- bcc_ptr[1] = 0; +- bcc_ptr += 2; + } + /* else do not bother copying these information fields*/ + } else { +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/cifs/misc.c linux-2.6.27.25-0.1.1/fs/cifs/misc.c +--- linux-2.6.27.23-0.1.1/fs/cifs/misc.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/cifs/misc.c 2009-07-24 10:23:52.000000000 +0100 +@@ -685,14 +685,15 @@ cifs_convertUCSpath(char *target, const + NLS_MAX_CHARSET_SIZE); + if (len > 0) { + j += len; +- continue; ++ goto overrun_chk; + } else { + target[j] = '?'; + } + } + j++; + /* make sure we do not overrun callers allocated temp buffer */ +- if (j >= (2 * NAME_MAX)) ++overrun_chk: ++ if (j >= UNICODE_NAME_MAX) + break; + } + cUCS_out: +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/cifs/readdir.c linux-2.6.27.25-0.1.1/fs/cifs/readdir.c +--- linux-2.6.27.23-0.1.1/fs/cifs/readdir.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/cifs/readdir.c 2009-07-24 10:23:52.000000000 +0100 +@@ -1075,7 +1075,7 @@ int cifs_readdir(struct file *file, void + with the rare long characters alloc more to account for + such multibyte target UTF-8 characters. cifs_unicode.c, + which actually does the conversion, has the same limit */ +- tmp_buf = kmalloc((2 * NAME_MAX) + 4, GFP_KERNEL); ++ tmp_buf = kmalloc(UNICODE_NAME_MAX, GFP_KERNEL); + for (i = 0; (i < num_to_fill) && (rc == 0); i++) { + if (current_entry == NULL) { + /* evaluate whether this case is an error */ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/eventpoll.c linux-2.6.27.25-0.1.1/fs/eventpoll.c +--- linux-2.6.27.23-0.1.1/fs/eventpoll.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/eventpoll.c 2009-07-24 10:23:52.000000000 +0100 +@@ -1132,7 +1132,7 @@ error_return: + + SYSCALL_DEFINE1(epoll_create, int, size) + { +- if (size < 0) ++ if (size <= 0) + return -EINVAL; + + return sys_epoll_create1(0); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/ext4/file.c linux-2.6.27.25-0.1.1/fs/ext4/file.c +--- linux-2.6.27.23-0.1.1/fs/ext4/file.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/ext4/file.c 2009-07-24 10:23:52.000000000 +0100 +@@ -125,7 +125,7 @@ force_commit: + + static struct vm_operations_struct ext4_file_vm_ops = { + .fault = filemap_fault, +- .page_mkwrite = ext4_page_mkwrite, ++ ._pmkw.page_mkwrite2 = ext4_page_mkwrite, + }; + + static int ext4_file_mmap(struct file *file, struct vm_area_struct *vma) +@@ -136,7 +136,7 @@ static int ext4_file_mmap(struct file *f + return -ENOEXEC; + file_accessed(file); + vma->vm_ops = &ext4_file_vm_ops; +- vma->vm_flags |= VM_CAN_NONLINEAR; ++ vma->vm_flags |= VM_CAN_NONLINEAR | VM_PAGE_MKWRITE2; + return 0; + } + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/fcntl.c linux-2.6.27.25-0.1.1/fs/fcntl.c +--- linux-2.6.27.23-0.1.1/fs/fcntl.c 2009-06-16 13:39:37.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/fcntl.c 2009-07-24 10:23:52.000000000 +0100 +@@ -118,6 +118,7 @@ SYSCALL_DEFINE2(dup2, unsigned int, oldf + if (unlikely(newfd == oldfd)) { /* corner case */ + struct files_struct *files = current->files; + int retval = oldfd; ++ + rcu_read_lock(); + if (!fcheck_files(files, oldfd)) + retval = -EBADF; +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/fuse/file.c linux-2.6.27.25-0.1.1/fs/fuse/file.c +--- linux-2.6.27.23-0.1.1/fs/fuse/file.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/fuse/file.c 2009-07-24 10:23:52.000000000 +0100 +@@ -1219,8 +1219,9 @@ static void fuse_vma_close(struct vm_are + * - sync(2) + * - try_to_free_pages() with order > PAGE_ALLOC_COSTLY_ORDER + */ +-static int fuse_page_mkwrite(struct vm_area_struct *vma, struct page *page) ++static int fuse_page_mkwrite(struct vm_area_struct *vma, struct vm_fault *vmf) + { ++ struct page *page = vmf->page; + /* + * Don't use page->mapping as it may become NULL from a + * concurrent truncate. +@@ -1234,7 +1235,7 @@ static int fuse_page_mkwrite(struct vm_a + static struct vm_operations_struct fuse_file_vm_ops = { + .close = fuse_vma_close, + .fault = filemap_fault, +- .page_mkwrite = fuse_page_mkwrite, ++ ._pmkw.page_mkwrite2 = fuse_page_mkwrite, + }; + + static int fuse_file_mmap(struct file *file, struct vm_area_struct *vma) +@@ -1254,6 +1255,7 @@ static int fuse_file_mmap(struct file *f + spin_unlock(&fc->lock); + } + file_accessed(file); ++ vma->vm_flags |= VM_PAGE_MKWRITE2; + vma->vm_ops = &fuse_file_vm_ops; + return 0; + } +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/gfs2/ops_file.c linux-2.6.27.25-0.1.1/fs/gfs2/ops_file.c +--- linux-2.6.27.23-0.1.1/fs/gfs2/ops_file.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/gfs2/ops_file.c 2009-07-24 10:23:52.000000000 +0100 +@@ -338,8 +338,9 @@ static int gfs2_allocate_page_backing(st + * blocks allocated on disk to back that page. + */ + +-static int gfs2_page_mkwrite(struct vm_area_struct *vma, struct page *page) ++static int gfs2_page_mkwrite(struct vm_area_struct *vma, struct vm_fault *vmf) + { ++ struct page *page = vmf->page; + struct inode *inode = vma->vm_file->f_path.dentry->d_inode; + struct gfs2_inode *ip = GFS2_I(inode); + struct gfs2_sbd *sdp = GFS2_SB(inode); +@@ -411,12 +412,16 @@ out_unlock: + gfs2_glock_dq(&gh); + out: + gfs2_holder_uninit(&gh); ++ if (ret == -ENOMEM) ++ ret = VM_FAULT_OOM; ++ else if (ret) ++ ret = VM_FAULT_SIGBUS; + return ret; + } + + static struct vm_operations_struct gfs2_vm_ops = { + .fault = filemap_fault, +- .page_mkwrite = gfs2_page_mkwrite, ++ ._pmkw.page_mkwrite2 = gfs2_page_mkwrite, + }; + + +@@ -441,6 +446,7 @@ static int gfs2_mmap(struct file *file, + return error; + } + ++ vma->vm_flags |= VM_PAGE_MKWRITE2; + vma->vm_ops = &gfs2_vm_ops; + + gfs2_glock_dq_uninit(&i_gh); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/jbd/commit.c linux-2.6.27.25-0.1.1/fs/jbd/commit.c +--- linux-2.6.27.23-0.1.1/fs/jbd/commit.c 2009-06-16 13:53:04.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/jbd/commit.c 2009-07-24 10:23:52.000000000 +0100 +@@ -238,7 +238,7 @@ write_out_data: + spin_lock(&journal->j_list_lock); + } + /* Someone already cleaned up the buffer? */ +- if (!buffer_jbd(bh) ++ if (!buffer_jbd(bh) || bh2jh(bh) != jh + || jh->b_transaction != commit_transaction + || jh->b_jlist != BJ_SyncData) { + jbd_unlock_bh_state(bh); +@@ -463,7 +463,9 @@ void journal_commit_transaction(journal_ + spin_lock(&journal->j_list_lock); + continue; + } +- if (buffer_jbd(bh) && jh->b_jlist == BJ_Locked) { ++ if (buffer_jbd(bh) && bh2jh(bh) == jh && ++ jh->b_transaction == commit_transaction && ++ jh->b_jlist == BJ_Locked) { + __journal_unfile_buffer(jh); + jbd_unlock_bh_state(bh); + journal_remove_journal_head(bh); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/Kconfig linux-2.6.27.25-0.1.1/fs/Kconfig +--- linux-2.6.27.23-0.1.1/fs/Kconfig 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/Kconfig 2009-07-24 10:23:52.000000000 +0100 +@@ -518,6 +518,15 @@ config OCFS2_COMPAT_JBD + is backwards compatible with JBD. It is safe to say N here. + However, if you really want to use the original JBD, say Y here. + ++config OCFS2_FS_POSIX_ACL ++ bool "OCFS2 POSIX Access Control Lists" ++ depends on OCFS2_FS ++ select FS_POSIX_ACL ++ default n ++ help ++ Posix Access Control Lists (ACLs) support permissions for users and ++ groups beyond the owner/group/world scheme. ++ + endif # BLOCK + + config DNOTIFY +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/lockd/svclock.c linux-2.6.27.25-0.1.1/fs/lockd/svclock.c +--- linux-2.6.27.23-0.1.1/fs/lockd/svclock.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/lockd/svclock.c 2009-07-24 10:23:52.000000000 +0100 +@@ -326,6 +326,8 @@ static void nlmsvc_freegrantargs(struct + { + if (call->a_args.lock.oh.data != call->a_owner) + kfree(call->a_args.lock.oh.data); ++ ++ locks_release_private(&call->a_args.lock.fl); + } + + /* +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/locks.c linux-2.6.27.25-0.1.1/fs/locks.c +--- linux-2.6.27.23-0.1.1/fs/locks.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/locks.c 2009-07-24 10:23:52.000000000 +0100 +@@ -151,7 +151,7 @@ static struct file_lock *locks_alloc_loc + return kmem_cache_alloc(filelock_cache, GFP_KERNEL); + } + +-static void locks_release_private(struct file_lock *fl) ++void locks_release_private(struct file_lock *fl) + { + if (fl->fl_ops) { + if (fl->fl_ops->fl_release_private) +@@ -165,6 +165,7 @@ static void locks_release_private(struct + } + + } ++EXPORT_SYMBOL_GPL(locks_release_private); + + /* Free a lock which is not in use. */ + static void locks_free_lock(struct file_lock *fl) +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/nfs/dir.c linux-2.6.27.25-0.1.1/fs/nfs/dir.c +--- linux-2.6.27.23-0.1.1/fs/nfs/dir.c 2009-06-16 13:39:31.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/nfs/dir.c 2009-07-24 10:23:52.000000000 +0100 +@@ -1613,8 +1613,7 @@ static int nfs_rename(struct inode *old_ + } else if (atomic_read(&new_dentry->d_count) > 1) + /* dentry still busy? */ + goto out; +- } else +- nfs_drop_nlink(new_inode); ++ } + + go_ahead: + /* +@@ -1627,10 +1626,8 @@ go_ahead: + } + nfs_inode_return_delegation(old_inode); + +- if (new_inode != NULL) { ++ if (new_inode != NULL) + nfs_inode_return_delegation(new_inode); +- d_delete(new_dentry); +- } + + error = NFS_PROTO(old_dir)->rename(old_dir, &old_dentry->d_name, + new_dir, &new_dentry->d_name); +@@ -1639,6 +1636,8 @@ out: + if (rehash) + d_rehash(rehash); + if (!error) { ++ if (new_inode != NULL) ++ nfs_drop_nlink(new_inode); + d_move(old_dentry, new_dentry); + nfs_set_verifier(new_dentry, + nfs_save_change_attribute(new_dir)); +@@ -1932,7 +1931,8 @@ int nfs_permission(struct inode *inode, + case S_IFREG: + /* NFSv4 has atomic_open... */ + if (nfs_server_capable(inode, NFS_CAP_ATOMIC_OPEN) +- && (mask & MAY_OPEN)) ++ && (mask & MAY_OPEN) ++ && !(mask & MAY_EXEC)) + goto out; + break; + case S_IFDIR: +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/nfs/file.c linux-2.6.27.25-0.1.1/fs/nfs/file.c +--- linux-2.6.27.23-0.1.1/fs/nfs/file.c 2009-06-16 13:53:04.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/nfs/file.c 2009-07-24 10:23:52.000000000 +0100 +@@ -304,7 +304,7 @@ nfs_file_mmap(struct file * file, struct + status = nfs_revalidate_mapping(inode, file->f_mapping); + if (!status) { + vma->vm_ops = &nfs_file_vm_ops; +- vma->vm_flags |= VM_CAN_NONLINEAR; ++ vma->vm_flags |= VM_CAN_NONLINEAR | VM_PAGE_MKWRITE2; + file_accessed(file); + } + return status; +@@ -466,8 +466,9 @@ const struct address_space_operations nf + #endif + }; + +-static int nfs_vm_page_mkwrite(struct vm_area_struct *vma, struct page *page) ++static int nfs_vm_page_mkwrite(struct vm_area_struct *vma, struct vm_fault *vmf) + { ++ struct page *page = vmf->page; + struct file *filp = vma->vm_file; + struct dentry *dentry = filp->f_path.dentry; + unsigned pagelen; +@@ -494,16 +495,16 @@ static int nfs_vm_page_mkwrite(struct vm + goto out_unlock; + + ret = nfs_updatepage(filp, page, 0, pagelen); +- if (ret == 0) +- ret = pagelen; + out_unlock: ++ if (!ret) ++ return VM_FAULT_LOCKED; + unlock_page(page); +- return ret; ++ return VM_FAULT_SIGBUS; + } + + static struct vm_operations_struct nfs_file_vm_ops = { + .fault = filemap_fault, +- .page_mkwrite = nfs_vm_page_mkwrite, ++ ._pmkw.page_mkwrite2 = nfs_vm_page_mkwrite, + }; + + static int nfs_need_sync_write(struct file *filp, struct inode *inode) +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/nfsd/nfs4xdr.c linux-2.6.27.25-0.1.1/fs/nfsd/nfs4xdr.c +--- linux-2.6.27.23-0.1.1/fs/nfsd/nfs4xdr.c 2009-06-16 13:39:36.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/nfsd/nfs4xdr.c 2009-07-24 10:23:52.000000000 +0100 +@@ -1833,6 +1833,15 @@ nfsd4_encode_dirent_fattr(struct nfsd4_r + dentry = lookup_one_len(name, cd->rd_fhp->fh_dentry, namlen); + if (IS_ERR(dentry)) + return nfserrno(PTR_ERR(dentry)); ++ if (!dentry->d_inode) { ++ /* ++ * nfsd_buffered_readdir drops the i_mutex between ++ * readdir and calling this callback, leaving a window ++ * where this directory entry could have gone away. ++ */ ++ dput(dentry); ++ return nfserr_noent; ++ } + + exp_get(exp); + /* +@@ -1895,6 +1904,7 @@ nfsd4_encode_dirent(void *ccdv, const ch + struct nfsd4_readdir *cd = container_of(ccd, struct nfsd4_readdir, common); + int buflen; + __be32 *p = cd->buffer; ++ __be32 *cookiep; + __be32 nfserr = nfserr_toosmall; + + /* In nfsv4, "." and ".." never make it onto the wire.. */ +@@ -1911,7 +1921,7 @@ nfsd4_encode_dirent(void *ccdv, const ch + goto fail; + + *p++ = xdr_one; /* mark entry present */ +- cd->offset = p; /* remember pointer */ ++ cookiep = p; + p = xdr_encode_hyper(p, NFS_OFFSET_MAX); /* offset of next entry */ + p = xdr_encode_array(p, name, namlen); /* name length & name */ + +@@ -1925,6 +1935,8 @@ nfsd4_encode_dirent(void *ccdv, const ch + goto fail; + case nfserr_dropit: + goto fail; ++ case nfserr_noent: ++ goto skip_entry; + default: + /* + * If the client requested the RDATTR_ERROR attribute, +@@ -1943,6 +1955,8 @@ nfsd4_encode_dirent(void *ccdv, const ch + } + cd->buflen -= (p - cd->buffer); + cd->buffer = p; ++ cd->offset = cookiep; ++skip_entry: + cd->common.err = nfs_ok; + return 0; + fail: +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/ocfs2/file.c linux-2.6.27.25-0.1.1/fs/ocfs2/file.c +--- linux-2.6.27.23-0.1.1/fs/ocfs2/file.c 2009-06-16 13:39:36.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/ocfs2/file.c 2009-07-24 10:23:52.000000000 +0100 +@@ -1919,6 +1919,23 @@ out_sems: + return written ? written : ret; + } + ++static int ocfs2_splice_to_file(struct pipe_inode_info *pipe, ++ struct file *out, ++ struct splice_desc_ext *esd) ++{ ++ int ret; ++ struct splice_desc *sd = esd->sd; ++ ++ ret = ocfs2_prepare_inode_for_write(out->f_path.dentry, &sd->pos, ++ sd->total_len, 0, NULL); ++ if (ret < 0) { ++ mlog_errno(ret); ++ return ret; ++ } ++ ++ return splice_from_pipe_feed(pipe, esd, pipe_to_file); ++} ++ + static ssize_t ocfs2_file_splice_write(struct pipe_inode_info *pipe, + struct file *out, + loff_t *ppos, +@@ -1926,38 +1943,77 @@ static ssize_t ocfs2_file_splice_write(s + unsigned int flags) + { + int ret; +- struct inode *inode = out->f_path.dentry->d_inode; ++ struct address_space *mapping = out->f_mapping; ++ struct inode *inode = mapping->host; ++ struct splice_desc sd = { ++ .total_len = len, ++ .flags = flags, ++ .pos = *ppos, ++ .u.file = out, ++ }; ++ struct splice_desc_ext esd = { .sd = &sd }; + + mlog_entry("(0x%p, 0x%p, %u, '%.*s')\n", out, pipe, + (unsigned int)len, + out->f_path.dentry->d_name.len, + out->f_path.dentry->d_name.name); + +- mutex_lock_nested(&inode->i_mutex, I_MUTEX_PARENT); +- +- ret = ocfs2_rw_lock(inode, 1); +- if (ret < 0) { +- mlog_errno(ret); +- goto out; +- } ++ if (pipe->inode) ++ mutex_lock_nested(&pipe->inode->i_mutex, I_MUTEX_PARENT); + +- ret = ocfs2_prepare_inode_for_write(out->f_path.dentry, ppos, len, 0, +- NULL); +- if (ret < 0) { +- mlog_errno(ret); +- goto out_unlock; +- } ++ splice_from_pipe_begin(&esd); ++ do { ++ ret = splice_from_pipe_next(pipe, &esd); ++ if (ret <= 0) ++ break; ++ ++ mutex_lock_nested(&inode->i_mutex, I_MUTEX_CHILD); ++ ret = ocfs2_rw_lock(inode, 1); ++ if (ret < 0) ++ mlog_errno(ret); ++ else { ++ ret = ocfs2_splice_to_file(pipe, out, &esd); ++ ocfs2_rw_unlock(inode, 1); ++ } ++ mutex_unlock(&inode->i_mutex); ++ } while (ret > 0); ++ splice_from_pipe_end(pipe, &esd); + + if (pipe->inode) +- mutex_lock_nested(&pipe->inode->i_mutex, I_MUTEX_CHILD); +- ret = generic_file_splice_write_nolock(pipe, out, ppos, len, flags); +- if (pipe->inode) + mutex_unlock(&pipe->inode->i_mutex); + +-out_unlock: +- ocfs2_rw_unlock(inode, 1); +-out: +- mutex_unlock(&inode->i_mutex); ++ if (esd.num_spliced) ++ ret = esd.num_spliced; ++ ++ if (ret > 0) { ++ unsigned long nr_pages; ++ ++ *ppos += ret; ++ nr_pages = (ret + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT; ++ ++ /* ++ * If file or inode is SYNC and we actually wrote some data, ++ * sync it. ++ */ ++ if (unlikely((out->f_flags & O_SYNC) || IS_SYNC(inode))) { ++ int err; ++ ++ mutex_lock(&inode->i_mutex); ++ err = ocfs2_rw_lock(inode, 1); ++ if (err < 0) { ++ mlog_errno(err); ++ } else { ++ err = generic_osync_inode(inode, mapping, ++ OSYNC_METADATA|OSYNC_DATA); ++ ocfs2_rw_unlock(inode, 1); ++ } ++ mutex_unlock(&inode->i_mutex); ++ ++ if (err) ++ ret = err; ++ } ++ balance_dirty_pages_ratelimited_nr(mapping, nr_pages); ++ } + + mlog_exit(ret); + return ret; +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/ocfs2/mmap.c linux-2.6.27.25-0.1.1/fs/ocfs2/mmap.c +--- linux-2.6.27.23-0.1.1/fs/ocfs2/mmap.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/ocfs2/mmap.c 2009-07-24 10:23:52.000000000 +0100 +@@ -154,8 +154,9 @@ out: + return ret; + } + +-static int ocfs2_page_mkwrite(struct vm_area_struct *vma, struct page *page) ++static int ocfs2_page_mkwrite(struct vm_area_struct *vma, struct vm_fault *vmf) + { ++ struct page *page = vmf->page; + struct inode *inode = vma->vm_file->f_path.dentry->d_inode; + struct buffer_head *di_bh = NULL; + sigset_t blocked, oldset; +@@ -196,13 +197,14 @@ out: + ret2 = ocfs2_vm_op_unblock_sigs(&oldset); + if (ret2 < 0) + mlog_errno(ret2); +- ++ if (ret) ++ ret = VM_FAULT_SIGBUS; + return ret; + } + + static struct vm_operations_struct ocfs2_file_vm_ops = { + .fault = ocfs2_fault, +- .page_mkwrite = ocfs2_page_mkwrite, ++ ._pmkw.page_mkwrite2 = ocfs2_page_mkwrite, + }; + + int ocfs2_mmap(struct file *file, struct vm_area_struct *vma) +@@ -218,7 +220,7 @@ int ocfs2_mmap(struct file *file, struct + ocfs2_inode_unlock(file->f_dentry->d_inode, lock_level); + out: + vma->vm_ops = &ocfs2_file_vm_ops; +- vma->vm_flags |= VM_CAN_NONLINEAR; ++ vma->vm_flags |= VM_CAN_NONLINEAR | VM_PAGE_MKWRITE2; + return 0; + } + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/splice.c linux-2.6.27.25-0.1.1/fs/splice.c +--- linux-2.6.27.23-0.1.1/fs/splice.c 2009-06-16 13:39:37.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/splice.c 2009-07-24 10:23:52.000000000 +0100 +@@ -553,8 +553,8 @@ static int pipe_to_sendpage(struct pipe_ + * SPLICE_F_MOVE isn't set, or we cannot move the page, we simply create + * a new page in the output file page cache and fill/dirty that. + */ +-static int pipe_to_file(struct pipe_inode_info *pipe, struct pipe_buffer *buf, +- struct splice_desc *sd) ++int pipe_to_file(struct pipe_inode_info *pipe, struct pipe_buffer *buf, ++ struct splice_desc *sd) + { + struct file *file = sd->u.file; + struct address_space *mapping = file->f_mapping; +@@ -598,108 +598,182 @@ static int pipe_to_file(struct pipe_inod + out: + return ret; + } ++EXPORT_SYMBOL(pipe_to_file); ++ ++static void wakeup_pipe_writers(struct pipe_inode_info *pipe) ++{ ++ smp_mb(); ++ if (waitqueue_active(&pipe->wait)) ++ wake_up_interruptible(&pipe->wait); ++ kill_fasync(&pipe->fasync_writers, SIGIO, POLL_OUT); ++} + + /** +- * __splice_from_pipe - splice data from a pipe to given actor ++ * splice_from_pipe_feed - feed available data from a pipe to a file + * @pipe: pipe to splice from + * @sd: information to @actor + * @actor: handler that splices the data + * + * Description: +- * This function does little more than loop over the pipe and call +- * @actor to do the actual moving of a single struct pipe_buffer to +- * the desired destination. See pipe_to_file, pipe_to_sendpage, or +- * pipe_to_user. ++ ++ * This function loops over the pipe and calls @actor to do the ++ * actual moving of a single struct pipe_buffer to the desired ++ * destination. It returns when there's no more buffers left in ++ * the pipe or if the requested number of bytes (@sd->total_len) ++ * have been copied. It returns a positive number (one) if the ++ * pipe needs to be filled with more data, zero if the required ++ * number of bytes have been copied and -errno on error. + * ++ * This, together with splice_from_pipe_{begin,end,next}, may be ++ * used to implement the functionality of __splice_from_pipe() when ++ * locking is required around copying the pipe buffers to the ++ * destination. + */ +-ssize_t __splice_from_pipe(struct pipe_inode_info *pipe, struct splice_desc *sd, +- splice_actor *actor) ++int splice_from_pipe_feed(struct pipe_inode_info *pipe, struct splice_desc_ext *esd, ++ splice_actor *actor) + { +- int ret, do_wakeup, err; ++ int ret; ++ struct splice_desc *sd = esd->sd; + +- ret = 0; +- do_wakeup = 0; ++ while (pipe->nrbufs) { ++ struct pipe_buffer *buf = pipe->bufs + pipe->curbuf; ++ const struct pipe_buf_operations *ops = buf->ops; ++ ++ sd->len = buf->len; ++ if (sd->len > sd->total_len) ++ sd->len = sd->total_len; ++ ++ ret = actor(pipe, buf, sd); ++ if (ret <= 0) { ++ if (ret == -ENODATA) ++ ret = 0; ++ return ret; ++ } ++ buf->offset += ret; ++ buf->len -= ret; ++ ++ esd->num_spliced += ret; ++ sd->len -= ret; ++ sd->pos += ret; ++ sd->total_len -= ret; + +- for (;;) { +- if (pipe->nrbufs) { +- struct pipe_buffer *buf = pipe->bufs + pipe->curbuf; +- const struct pipe_buf_operations *ops = buf->ops; +- +- sd->len = buf->len; +- if (sd->len > sd->total_len) +- sd->len = sd->total_len; +- +- err = actor(pipe, buf, sd); +- if (err <= 0) { +- if (!ret && err != -ENODATA) +- ret = err; ++ if (!buf->len) { ++ buf->ops = NULL; ++ ops->release(pipe, buf); ++ pipe->curbuf = (pipe->curbuf + 1) & (PIPE_BUFFERS - 1); ++ pipe->nrbufs--; ++ if (pipe->inode) ++ esd->need_wakeup = true; ++ } + +- break; +- } ++ if (!sd->total_len) ++ return 0; ++ } + +- ret += err; +- buf->offset += err; +- buf->len -= err; +- +- sd->len -= err; +- sd->pos += err; +- sd->total_len -= err; +- if (sd->len) +- continue; +- +- if (!buf->len) { +- buf->ops = NULL; +- ops->release(pipe, buf); +- pipe->curbuf = (pipe->curbuf + 1) & (PIPE_BUFFERS - 1); +- pipe->nrbufs--; +- if (pipe->inode) +- do_wakeup = 1; +- } ++ return 1; ++} ++EXPORT_SYMBOL(splice_from_pipe_feed); + +- if (!sd->total_len) +- break; +- } ++/** ++ * splice_from_pipe_next - wait for some data to splice from ++ * @pipe: pipe to splice from ++ * @sd: information about the splice operation ++ * ++ * Description: ++ * This function will wait for some data and return a positive ++ * value (one) if pipe buffers are available. It will return zero ++ * or -errno if no more data needs to be spliced. ++ */ ++int splice_from_pipe_next(struct pipe_inode_info *pipe, struct splice_desc_ext *esd) ++{ ++ struct splice_desc *sd = esd->sd; + +- if (pipe->nrbufs) +- continue; ++ while (!pipe->nrbufs) { + if (!pipe->writers) +- break; +- if (!pipe->waiting_writers) { +- if (ret) +- break; +- } ++ return 0; + +- if (sd->flags & SPLICE_F_NONBLOCK) { +- if (!ret) +- ret = -EAGAIN; +- break; +- } ++ if (!pipe->waiting_writers && esd->num_spliced) ++ return 0; + +- if (signal_pending(current)) { +- if (!ret) +- ret = -ERESTARTSYS; +- break; +- } ++ if (sd->flags & SPLICE_F_NONBLOCK) ++ return -EAGAIN; ++ ++ if (signal_pending(current)) ++ return -ERESTARTSYS; + +- if (do_wakeup) { +- smp_mb(); +- if (waitqueue_active(&pipe->wait)) +- wake_up_interruptible_sync(&pipe->wait); +- kill_fasync(&pipe->fasync_writers, SIGIO, POLL_OUT); +- do_wakeup = 0; ++ if (esd->need_wakeup) { ++ wakeup_pipe_writers(pipe); ++ esd->need_wakeup = false; + } + + pipe_wait(pipe); + } + +- if (do_wakeup) { +- smp_mb(); +- if (waitqueue_active(&pipe->wait)) +- wake_up_interruptible(&pipe->wait); +- kill_fasync(&pipe->fasync_writers, SIGIO, POLL_OUT); +- } ++ return 1; ++} ++EXPORT_SYMBOL(splice_from_pipe_next); + +- return ret; ++/** ++ * splice_from_pipe_begin - start splicing from pipe ++ * @pipe: pipe to splice from ++ * ++ * Description: ++ * This function should be called before a loop containing ++ * splice_from_pipe_next() and splice_from_pipe_feed() to ++ * initialize the necessary fields of @sd. ++ */ ++void splice_from_pipe_begin(struct splice_desc_ext *esd) ++{ ++ esd->num_spliced = 0; ++ esd->need_wakeup = false; ++} ++EXPORT_SYMBOL(splice_from_pipe_begin); ++ ++/** ++ * splice_from_pipe_end - finish splicing from pipe ++ * @pipe: pipe to splice from ++ * @sd: information about the splice operation ++ * ++ * Description: ++ * This function will wake up pipe writers if necessary. It should ++ * be called after a loop containing splice_from_pipe_next() and ++ * splice_from_pipe_feed(). ++ */ ++void splice_from_pipe_end(struct pipe_inode_info *pipe, struct splice_desc_ext *esd) ++{ ++ if (esd->need_wakeup) ++ wakeup_pipe_writers(pipe); ++} ++EXPORT_SYMBOL(splice_from_pipe_end); ++ ++/** ++ * __splice_from_pipe - splice data from a pipe to given actor ++ * @pipe: pipe to splice from ++ * @sd: information to @actor ++ * @actor: handler that splices the data ++ * ++ * Description: ++ * This function does little more than loop over the pipe and call ++ * @actor to do the actual moving of a single struct pipe_buffer to ++ * the desired destination. See pipe_to_file, pipe_to_sendpage, or ++ * pipe_to_user. ++ * ++ */ ++ssize_t __splice_from_pipe(struct pipe_inode_info *pipe, struct splice_desc *sd, ++ splice_actor *actor) ++{ ++ int ret; ++ struct splice_desc_ext esd = { .sd = sd }; ++ ++ splice_from_pipe_begin(&esd); ++ do { ++ ret = splice_from_pipe_next(pipe, &esd); ++ if (ret > 0) ++ ret = splice_from_pipe_feed(pipe, &esd, actor); ++ } while (ret > 0); ++ splice_from_pipe_end(pipe, &esd); ++ ++ return esd.num_spliced ? esd.num_spliced : ret; + } + EXPORT_SYMBOL(__splice_from_pipe); + +@@ -713,7 +787,7 @@ EXPORT_SYMBOL(__splice_from_pipe); + * @actor: handler that splices the data + * + * Description: +- * See __splice_from_pipe. This function locks the input and output inodes, ++ * See __splice_from_pipe. This function locks the pipe inode, + * otherwise it's identical to __splice_from_pipe(). + * + */ +@@ -722,7 +796,6 @@ ssize_t splice_from_pipe(struct pipe_ino + splice_actor *actor) + { + ssize_t ret; +- struct inode *inode = out->f_mapping->host; + struct splice_desc sd = { + .total_len = len, + .flags = flags, +@@ -730,24 +803,11 @@ ssize_t splice_from_pipe(struct pipe_ino + .u.file = out, + }; + +- /* +- * The actor worker might be calling ->prepare_write and +- * ->commit_write. Most of the time, these expect i_mutex to +- * be held. Since this may result in an ABBA deadlock with +- * pipe->inode, we have to order lock acquiry here. +- * +- * Outer lock must be inode->i_mutex, as pipe_wait() will +- * release and reacquire pipe->inode->i_mutex, AND inode must +- * never be a pipe. +- */ +- WARN_ON(S_ISFIFO(inode->i_mode)); +- mutex_lock_nested(&inode->i_mutex, I_MUTEX_PARENT); + if (pipe->inode) +- mutex_lock_nested(&pipe->inode->i_mutex, I_MUTEX_CHILD); ++ mutex_lock(&pipe->inode->i_mutex); + ret = __splice_from_pipe(pipe, &sd, actor); + if (pipe->inode) + mutex_unlock(&pipe->inode->i_mutex); +- mutex_unlock(&inode->i_mutex); + + return ret; + } +@@ -836,19 +896,32 @@ generic_file_splice_write(struct pipe_in + .pos = *ppos, + .u.file = out, + }; ++ struct splice_desc_ext esd = { .sd = &sd }; + ssize_t ret; + +- WARN_ON(S_ISFIFO(inode->i_mode)); +- mutex_lock_nested(&inode->i_mutex, I_MUTEX_PARENT); +- ret = file_remove_suid(out); +- if (likely(!ret)) { +- if (pipe->inode) +- mutex_lock_nested(&pipe->inode->i_mutex, I_MUTEX_CHILD); +- ret = __splice_from_pipe(pipe, &sd, pipe_to_file); +- if (pipe->inode) +- mutex_unlock(&pipe->inode->i_mutex); +- } +- mutex_unlock(&inode->i_mutex); ++ if (pipe->inode) ++ mutex_lock_nested(&pipe->inode->i_mutex, I_MUTEX_PARENT); ++ ++ splice_from_pipe_begin(&esd); ++ do { ++ ret = splice_from_pipe_next(pipe, &esd); ++ if (ret <= 0) ++ break; ++ ++ mutex_lock_nested(&inode->i_mutex, I_MUTEX_CHILD); ++ ret = file_remove_suid(out); ++ if (!ret) ++ ret = splice_from_pipe_feed(pipe, &esd, pipe_to_file); ++ mutex_unlock(&inode->i_mutex); ++ } while (ret > 0); ++ splice_from_pipe_end(pipe, &esd); ++ ++ if (pipe->inode) ++ mutex_unlock(&pipe->inode->i_mutex); ++ ++ if (esd.num_spliced) ++ ret = esd.num_spliced; ++ + if (ret > 0) { + unsigned long nr_pages; + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/ubifs/file.c linux-2.6.27.25-0.1.1/fs/ubifs/file.c +--- linux-2.6.27.23-0.1.1/fs/ubifs/file.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/ubifs/file.c 2009-07-24 10:23:52.000000000 +0100 +@@ -1140,8 +1140,9 @@ static int ubifs_releasepage(struct page + * mmap()d file has taken write protection fault and is being made + * writable. UBIFS must ensure page is budgeted for. + */ +-static int ubifs_vm_page_mkwrite(struct vm_area_struct *vma, struct page *page) ++static int ubifs_vm_page_mkwrite(struct vm_area_struct *vma, struct vm_fault *vmf) + { ++ struct page *page = vmf->page; + struct inode *inode = vma->vm_file->f_path.dentry->d_inode; + struct ubifs_info *c = inode->i_sb->s_fs_info; + struct timespec now = ubifs_current_time(inode); +@@ -1153,7 +1154,7 @@ static int ubifs_vm_page_mkwrite(struct + ubifs_assert(!(inode->i_sb->s_flags & MS_RDONLY)); + + if (unlikely(c->ro_media)) +- return -EROFS; ++ return VM_FAULT_SIGBUS; /* -EROFS */ + + /* + * We have not locked @page so far so we may budget for changing the +@@ -1186,7 +1187,7 @@ static int ubifs_vm_page_mkwrite(struct + if (err == -ENOSPC) + ubifs_warn("out of space for mmapped file " + "(inode number %lu)", inode->i_ino); +- return err; ++ return VM_FAULT_SIGBUS; + } + + lock_page(page); +@@ -1226,12 +1227,14 @@ static int ubifs_vm_page_mkwrite(struct + out_unlock: + unlock_page(page); + ubifs_release_budget(c, &req); ++ if (err) ++ err = VM_FAULT_SIGBUS; + return err; + } + + static struct vm_operations_struct ubifs_file_vm_ops = { + .fault = filemap_fault, +- .page_mkwrite = ubifs_vm_page_mkwrite, ++ ._pmkw.page_mkwrite2 = ubifs_vm_page_mkwrite, + }; + + static int ubifs_file_mmap(struct file *file, struct vm_area_struct *vma) +@@ -1243,6 +1246,7 @@ static int ubifs_file_mmap(struct file * + if (err) + return err; + vma->vm_ops = &ubifs_file_vm_ops; ++ vma->vm_flags |= VM_PAGE_MKWRITE2; + return 0; + } + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/xfs/linux-2.6/xfs_file.c linux-2.6.27.25-0.1.1/fs/xfs/linux-2.6/xfs_file.c +--- linux-2.6.27.23-0.1.1/fs/xfs/linux-2.6/xfs_file.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/xfs/linux-2.6/xfs_file.c 2009-07-24 10:23:52.000000000 +0100 +@@ -390,7 +390,7 @@ xfs_file_mmap( + struct vm_area_struct *vma) + { + vma->vm_ops = &xfs_file_vm_ops; +- vma->vm_flags |= VM_CAN_NONLINEAR; ++ vma->vm_flags |= VM_CAN_NONLINEAR | VM_PAGE_MKWRITE2; + + #ifdef HAVE_DMAPI + if (XFS_M(filp->f_path.dentry->d_inode->i_sb)->m_flags & XFS_MOUNT_DMAPI) +@@ -493,9 +493,9 @@ xfs_file_open_exec( + STATIC int + xfs_vm_page_mkwrite( + struct vm_area_struct *vma, +- struct page *page) ++ struct vm_fault *vmf) + { +- return block_page_mkwrite(vma, page, xfs_get_blocks); ++ return block_page_mkwrite2(vma, vmf, xfs_get_blocks); + } + + const struct file_operations xfs_file_operations = { +@@ -551,13 +551,13 @@ const struct file_operations xfs_dir_fil + + static struct vm_operations_struct xfs_file_vm_ops = { + .fault = filemap_fault, +- .page_mkwrite = xfs_vm_page_mkwrite, ++ ._pmkw.page_mkwrite2 = xfs_vm_page_mkwrite, + }; + + #ifdef HAVE_DMAPI + static struct vm_operations_struct xfs_dmapi_file_vm_ops = { + .fault = xfs_vm_fault, +- .page_mkwrite = xfs_vm_page_mkwrite, ++ ._pmkw.page_mkwrite2 = xfs_vm_page_mkwrite, + #ifdef HAVE_VMOP_MPROTECT + .mprotect = xfs_vm_mprotect, + #endif +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/xfs/quota/xfs_dquot.c linux-2.6.27.25-0.1.1/fs/xfs/quota/xfs_dquot.c +--- linux-2.6.27.23-0.1.1/fs/xfs/quota/xfs_dquot.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/xfs/quota/xfs_dquot.c 2009-07-24 10:23:52.000000000 +0100 +@@ -101,7 +101,7 @@ xfs_qm_dqinit( + if (brandnewdquot) { + dqp->dq_flnext = dqp->dq_flprev = dqp; + mutex_init(&dqp->q_qlock); +- sv_init(&dqp->q_pinwait, SV_DEFAULT, "pdq"); ++ init_waitqueue_head(&dqp->q_pinwait); + + /* + * Because we want to use a counting completion, complete +@@ -131,7 +131,7 @@ xfs_qm_dqinit( + dqp->q_res_bcount = 0; + dqp->q_res_icount = 0; + dqp->q_res_rtbcount = 0; +- dqp->q_pincount = 0; ++ atomic_set(&dqp->q_pincount, 0); + dqp->q_hash = NULL; + ASSERT(dqp->dq_flnext == dqp->dq_flprev); + +@@ -1489,7 +1489,7 @@ xfs_qm_dqpurge( + "xfs_qm_dqpurge: dquot %p flush failed", dqp); + xfs_dqflock(dqp); + } +- ASSERT(dqp->q_pincount == 0); ++ ASSERT(atomic_read(&dqp->q_pincount) == 0); + ASSERT(XFS_FORCED_SHUTDOWN(mp) || + !(dqp->q_logitem.qli_item.li_flags & XFS_LI_IN_AIL)); + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/xfs/quota/xfs_dquot.h linux-2.6.27.25-0.1.1/fs/xfs/quota/xfs_dquot.h +--- linux-2.6.27.23-0.1.1/fs/xfs/quota/xfs_dquot.h 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/xfs/quota/xfs_dquot.h 2009-07-24 10:23:52.000000000 +0100 +@@ -83,8 +83,9 @@ typedef struct xfs_dquot { + xfs_qcnt_t q_res_rtbcount;/* total realtime blks used+reserved */ + mutex_t q_qlock; /* quota lock */ + struct completion q_flush; /* flush completion queue */ +- uint q_pincount; /* pin count for this dquot */ +- sv_t q_pinwait; /* sync var for pinning */ ++ atomic_t q_pincount; /* dquot pin count */ ++ wait_queue_head_t q_pinwait; /* dquot pinning wait queue */ ++ + #ifdef XFS_DQUOT_TRACE + struct ktrace *q_trace; /* trace header structure */ + #endif +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/xfs/quota/xfs_dquot_item.c linux-2.6.27.25-0.1.1/fs/xfs/quota/xfs_dquot_item.c +--- linux-2.6.27.23-0.1.1/fs/xfs/quota/xfs_dquot_item.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/xfs/quota/xfs_dquot_item.c 2009-07-24 10:23:52.000000000 +0100 +@@ -88,25 +88,23 @@ xfs_qm_dquot_logitem_format( + + /* + * Increment the pin count of the given dquot. +- * This value is protected by pinlock spinlock in the xQM structure. + */ + STATIC void + xfs_qm_dquot_logitem_pin( + xfs_dq_logitem_t *logitem) + { +- xfs_dquot_t *dqp; ++ xfs_dquot_t *dqp = logitem->qli_dquot; + +- dqp = logitem->qli_dquot; + ASSERT(XFS_DQ_IS_LOCKED(dqp)); +- spin_lock(&(XFS_DQ_TO_QINF(dqp)->qi_pinlock)); +- dqp->q_pincount++; +- spin_unlock(&(XFS_DQ_TO_QINF(dqp)->qi_pinlock)); ++ atomic_inc(&dqp->q_pincount); ++ + } + + /* + * Decrement the pin count of the given dquot, and wake up + * anyone in xfs_dqwait_unpin() if the count goes to 0. The +- * dquot must have been previously pinned with a call to xfs_dqpin(). ++ * dquot must have been previously pinned with a call to ++ * xfs_qm_dquot_logitem_pin(). + */ + /* ARGSUSED */ + STATIC void +@@ -114,16 +112,12 @@ xfs_qm_dquot_logitem_unpin( + xfs_dq_logitem_t *logitem, + int stale) + { +- xfs_dquot_t *dqp; ++xfs_dquot_t *dqp = logitem->qli_dquot; ++ ++ ASSERT(atomic_read(&dqp->q_pincount) > 0); ++ if (atomic_dec_and_test(&dqp->q_pincount)) ++ wake_up(&dqp->q_pinwait); + +- dqp = logitem->qli_dquot; +- ASSERT(dqp->q_pincount > 0); +- spin_lock(&(XFS_DQ_TO_QINF(dqp)->qi_pinlock)); +- dqp->q_pincount--; +- if (dqp->q_pincount == 0) { +- sv_broadcast(&dqp->q_pinwait); +- } +- spin_unlock(&(XFS_DQ_TO_QINF(dqp)->qi_pinlock)); + } + + /* ARGSUSED */ +@@ -193,7 +187,7 @@ xfs_qm_dqunpin_wait( + xfs_dquot_t *dqp) + { + ASSERT(XFS_DQ_IS_LOCKED(dqp)); +- if (dqp->q_pincount == 0) { ++ if (atomic_read(&dqp->q_pincount) == 0) { + return; + } + +@@ -201,13 +195,7 @@ xfs_qm_dqunpin_wait( + * Give the log a push so we don't wait here too long. + */ + xfs_log_force(dqp->q_mount, (xfs_lsn_t)0, XFS_LOG_FORCE); +- spin_lock(&(XFS_DQ_TO_QINF(dqp)->qi_pinlock)); +- if (dqp->q_pincount == 0) { +- spin_unlock(&(XFS_DQ_TO_QINF(dqp)->qi_pinlock)); +- return; +- } +- sv_wait(&(dqp->q_pinwait), PINOD, +- &(XFS_DQ_TO_QINF(dqp)->qi_pinlock), s); ++ wait_event(dqp->q_pinwait, (atomic_read(&dqp->q_pincount) == 0)); + } + + /* +@@ -310,7 +298,7 @@ xfs_qm_dquot_logitem_trylock( + uint retval; + + dqp = qip->qli_dquot; +- if (dqp->q_pincount > 0) ++ if (atomic_read(&dqp->q_pincount) > 0) + return (XFS_ITEM_PINNED); + + if (! xfs_qm_dqlock_nowait(dqp)) +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/xfs/quota/xfs_qm.c linux-2.6.27.25-0.1.1/fs/xfs/quota/xfs_qm.c +--- linux-2.6.27.23-0.1.1/fs/xfs/quota/xfs_qm.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/xfs/quota/xfs_qm.c 2009-07-24 10:23:52.000000000 +0100 +@@ -1137,7 +1137,6 @@ xfs_qm_init_quotainfo( + return error; + } + +- spin_lock_init(&qinf->qi_pinlock); + xfs_qm_list_init(&qinf->qi_dqlist, "mpdqlist", 0); + qinf->qi_dqreclaims = 0; + +@@ -1234,7 +1233,6 @@ xfs_qm_destroy_quotainfo( + */ + xfs_qm_rele_quotafs_ref(mp); + +- spinlock_destroy(&qi->qi_pinlock); + xfs_qm_list_destroy(&qi->qi_dqlist); + + if (qi->qi_uquotaip) { +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/xfs/quota/xfs_qm.h linux-2.6.27.25-0.1.1/fs/xfs/quota/xfs_qm.h +--- linux-2.6.27.23-0.1.1/fs/xfs/quota/xfs_qm.h 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/xfs/quota/xfs_qm.h 2009-07-24 10:23:52.000000000 +0100 +@@ -106,7 +106,6 @@ typedef struct xfs_qm { + typedef struct xfs_quotainfo { + xfs_inode_t *qi_uquotaip; /* user quota inode */ + xfs_inode_t *qi_gquotaip; /* group quota inode */ +- spinlock_t qi_pinlock; /* dquot pinning lock */ + xfs_dqlist_t qi_dqlist; /* all dquots in filesys */ + int qi_dqreclaims; /* a change here indicates + a removal in the dqlist */ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/fs/xfs/xfs_fsops.c linux-2.6.27.25-0.1.1/fs/xfs/xfs_fsops.c +--- linux-2.6.27.23-0.1.1/fs/xfs/xfs_fsops.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/fs/xfs/xfs_fsops.c 2009-07-24 10:23:52.000000000 +0100 +@@ -160,7 +160,7 @@ xfs_growfs_data_private( + nagcount = new + (nb_mod != 0); + if (nb_mod && nb_mod < XFS_MIN_AG_BLOCKS) { + nagcount--; +- nb = nagcount * mp->m_sb.sb_agblocks; ++ nb = (xfs_rfsblock_t)nagcount * mp->m_sb.sb_agblocks; + if (nb < mp->m_sb.sb_dblocks) + return XFS_ERROR(EINVAL); + } +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/include/linux/buffer_head.h linux-2.6.27.25-0.1.1/include/linux/buffer_head.h +--- linux-2.6.27.23-0.1.1/include/linux/buffer_head.h 2009-06-16 13:55:22.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/include/linux/buffer_head.h 2009-07-24 10:24:51.000000000 +0100 +@@ -225,6 +225,8 @@ int generic_cont_expand_simple(struct in + int block_commit_write(struct page *page, unsigned from, unsigned to); + int block_page_mkwrite(struct vm_area_struct *vma, struct page *page, + get_block_t get_block); ++int block_page_mkwrite2(struct vm_area_struct *vma, struct vm_fault *vmf, ++ get_block_t get_block); + void block_sync_page(struct page *); + sector_t generic_block_bmap(struct address_space *, sector_t, get_block_t *); + int block_truncate_page(struct address_space *, loff_t, get_block_t *); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/include/linux/fs.h linux-2.6.27.25-0.1.1/include/linux/fs.h +--- linux-2.6.27.23-0.1.1/include/linux/fs.h 2009-06-16 13:41:15.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/include/linux/fs.h 2009-07-24 10:24:51.000000000 +0100 +@@ -1034,6 +1034,7 @@ extern void locks_copy_lock(struct file_ + extern void __locks_copy_lock(struct file_lock *, const struct file_lock *); + extern void locks_remove_posix(struct file *, fl_owner_t); + extern void locks_remove_flock(struct file *); ++extern void locks_release_private(struct file_lock *); + extern void posix_test_lock(struct file *, struct file_lock *); + extern int posix_lock_file(struct file *, struct file_lock *, struct file_lock *); + extern int posix_lock_file_wait(struct file *, struct file_lock *); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/include/linux/mm.h linux-2.6.27.25-0.1.1/include/linux/mm.h +--- linux-2.6.27.23-0.1.1/include/linux/mm.h 2009-06-16 13:41:15.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/include/linux/mm.h 2009-07-24 10:24:51.000000000 +0100 +@@ -116,6 +116,7 @@ extern unsigned int kobjsize(const void + #ifdef CONFIG_XEN + #define VM_FOREIGN 0x40000000 /* Has pages belonging to another VM */ + #endif ++#define VM_PAGE_MKWRITE2 0x80000000 /* Uses page_mkwrite2 rather than page_mkwrite */ + + #ifndef VM_STACK_DEFAULT_FLAGS /* arch can override this */ + #define VM_STACK_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS +@@ -141,6 +142,7 @@ extern pgprot_t protection_map[16]; + + #define FAULT_FLAG_WRITE 0x01 /* Fault was a write access */ + #define FAULT_FLAG_NONLINEAR 0x02 /* Fault was via a nonlinear mapping */ ++#define FAULT_FLAG_MKWRITE 0x04 /* Fault was mkwrite of existing pte */ + + + /* +@@ -177,9 +179,22 @@ struct vm_operations_struct { + #define HAVE_VMOP_MPROTECT + int (*mprotect)(struct vm_area_struct * area, unsigned int newflags); + +- /* notification that a previously read-only page is about to become +- * writable, if an error is returned it will cause a SIGBUS */ +- int (*page_mkwrite)(struct vm_area_struct *vma, struct page *page); ++#ifdef __GENKSYMS__ ++ int (*page_mkwrite)(struct vm_area_struct *, struct page *); ++#else ++ union { ++ /* ++ * XXX: this is an ABI compatibility hack. ++ * Using the fixed page_mkwrite2 call requires VM_PAGE_MKWRITE2 to be ++ * set in vma->vm_flags ++ */ ++ ++ /* notification that a previously read-only page is about to become ++ * writable, if an error is returned it will cause a SIGBUS */ ++ int (*page_mkwrite)(struct vm_area_struct *, struct page *); ++ int (*page_mkwrite2)(struct vm_area_struct *vma, struct vm_fault *vmf); ++ } _pmkw; ++#endif + + /* called by access_process_vm when get_user_pages() fails, typically + * for use by special VMAs that can switch between memory and hardware +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/include/linux/raid/raid5.h linux-2.6.27.25-0.1.1/include/linux/raid/raid5.h +--- linux-2.6.27.23-0.1.1/include/linux/raid/raid5.h 2009-06-16 13:55:16.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/include/linux/raid/raid5.h 2009-07-24 10:24:51.000000000 +0100 +@@ -197,15 +197,17 @@ enum reconstruct_states { + + struct stripe_head { + struct hlist_node hash; +- struct list_head lru; /* inactive_list or handle_list */ +- struct raid5_private_data *raid_conf; +- sector_t sector; /* sector of this row */ +- int pd_idx; /* parity disk index */ +- unsigned long state; /* state flags */ +- atomic_t count; /* nr of active thread/requests */ ++ struct list_head lru; /* inactive_list or handle_list */ ++ struct raid5_private_data *raid_conf; ++ sector_t sector; /* sector of this row */ ++ short pd_idx; /* parity disk index */ ++ short qd_idx; /* 'Q' disk index for raid6 */ ++ short ddf_layout;/* use DDF ordering to calculate Q */ ++ unsigned long state; /* state flags */ ++ atomic_t count; /* nr of active thread/requests */ + spinlock_t lock; + int bm_seq; /* sequence number for bitmap flushes */ +- int disks; /* disks in stripe */ ++ int disks; /* disks in stripe */ + enum check_states check_state; + enum reconstruct_states reconstruct_state; + /* stripe_operations +@@ -394,9 +396,62 @@ typedef struct raid5_private_data raid5_ + /* + * Our supported algorithms + */ +-#define ALGORITHM_LEFT_ASYMMETRIC 0 +-#define ALGORITHM_RIGHT_ASYMMETRIC 1 +-#define ALGORITHM_LEFT_SYMMETRIC 2 +-#define ALGORITHM_RIGHT_SYMMETRIC 3 ++#define ALGORITHM_LEFT_ASYMMETRIC 0 /* Rotating Parity N with Data Restart */ ++#define ALGORITHM_RIGHT_ASYMMETRIC 1 /* Rotating Parity 0 with Data Restart */ ++#define ALGORITHM_LEFT_SYMMETRIC 2 /* Rotating Parity N with Data Continuation */ ++#define ALGORITHM_RIGHT_SYMMETRIC 3 /* Rotating Parity 0 with Data Continuation */ + ++/* Define non-rotating (raid4) algorithms. These allow ++ * conversion of raid4 to raid5. ++ */ ++#define ALGORITHM_PARITY_0 4 /* P or P,Q are initial devices */ ++#define ALGORITHM_PARITY_N 5 /* P or P,Q are final devices. */ ++ ++/* DDF RAID6 layouts differ from md/raid6 layouts in two ways. ++ * Firstly, the exact positioning of the parity block is slightly ++ * different between the 'LEFT_*' modes of md and the "_N_*" modes ++ * of DDF. ++ * Secondly, or order of datablocks over which the Q syndrome is computed ++ * is different. ++ * Consequently we have different layouts for DDF/raid6 than md/raid6. ++ * These layouts are from the DDFv1.2 spec. ++ * Interestingly DDFv1.2-Errata-A does not specify N_CONTINUE but ++ * leaves RLQ=3 as 'Vendor Specific' ++ */ ++ ++#define ALGORITHM_ROTATING_ZERO_RESTART 8 /* DDF PRL=6 RLQ=1 */ ++#define ALGORITHM_ROTATING_N_RESTART 9 /* DDF PRL=6 RLQ=2 */ ++#define ALGORITHM_ROTATING_N_CONTINUE 10 /*DDF PRL=6 RLQ=3 */ ++ ++ ++/* For every RAID5 algorithm we define a RAID6 algorithm ++ * with exactly the same layout for data and parity, and ++ * with the Q block always on the last device (N-1). ++ * This allows trivial conversion from RAID5 to RAID6 ++ */ ++#define ALGORITHM_LEFT_ASYMMETRIC_6 16 ++#define ALGORITHM_RIGHT_ASYMMETRIC_6 17 ++#define ALGORITHM_LEFT_SYMMETRIC_6 18 ++#define ALGORITHM_RIGHT_SYMMETRIC_6 19 ++#define ALGORITHM_PARITY_0_6 20 ++#define ALGORITHM_PARITY_N_6 ALGORITHM_PARITY_N ++ ++static inline int algorithm_valid_raid5(int layout) ++{ ++ return (layout >= 0) && ++ (layout <= 5); ++} ++static inline int algorithm_valid_raid6(int layout) ++{ ++ return (layout >= 0 && layout <= 5) ++ || ++ (layout == 8 || layout == 10) ++ || ++ (layout >= 16 && layout <= 20); ++} ++ ++static inline int algorithm_is_DDF(int layout) ++{ ++ return layout >= 8 && layout <= 10; ++} + #endif +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/include/linux/splice.h linux-2.6.27.25-0.1.1/include/linux/splice.h +--- linux-2.6.27.23-0.1.1/include/linux/splice.h 2009-06-16 13:55:21.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/include/linux/splice.h 2009-07-24 10:24:51.000000000 +0100 +@@ -38,6 +38,12 @@ struct splice_desc { + loff_t pos; /* file position */ + }; + ++struct splice_desc_ext { ++ struct splice_desc *sd; ++ size_t num_spliced; /* number of bytes already spliced */ ++ bool need_wakeup; /* need to wake up writer */ ++}; ++ + struct partial_page { + unsigned int offset; + unsigned int len; +@@ -66,6 +72,16 @@ extern ssize_t splice_from_pipe(struct p + splice_actor *); + extern ssize_t __splice_from_pipe(struct pipe_inode_info *, + struct splice_desc *, splice_actor *); ++extern int splice_from_pipe_feed(struct pipe_inode_info *, struct splice_desc_ext *, ++ splice_actor *); ++extern int splice_from_pipe_next(struct pipe_inode_info *, ++ struct splice_desc_ext *); ++extern void splice_from_pipe_begin(struct splice_desc_ext *); ++extern void splice_from_pipe_end(struct pipe_inode_info *, ++ struct splice_desc_ext *); ++extern int pipe_to_file(struct pipe_inode_info *, struct pipe_buffer *, ++ struct splice_desc *); ++ + extern ssize_t splice_to_pipe(struct pipe_inode_info *, + struct splice_pipe_desc *); + extern ssize_t splice_direct_to_actor(struct file *, struct splice_desc *, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/lib/string_helpers.c linux-2.6.27.25-0.1.1/lib/string_helpers.c +--- linux-2.6.27.23-0.1.1/lib/string_helpers.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/lib/string_helpers.c 2009-07-24 10:23:52.000000000 +0100 +@@ -23,7 +23,7 @@ + int string_get_size(u64 size, const enum string_size_units units, + char *buf, int len) + { +- const char *units_10[] = { "B", "KB", "MB", "GB", "TB", "PB", ++ const char *units_10[] = { "B", "kB", "MB", "GB", "TB", "PB", + "EB", "ZB", "YB", NULL}; + const char *units_2[] = {"B", "KiB", "MiB", "GiB", "TiB", "PiB", + "EiB", "ZiB", "YiB", NULL }; +@@ -31,7 +31,7 @@ int string_get_size(u64 size, const enum + [STRING_UNITS_10] = units_10, + [STRING_UNITS_2] = units_2, + }; +- const int divisor[] = { ++ const unsigned int divisor[] = { + [STRING_UNITS_10] = 1000, + [STRING_UNITS_2] = 1024, + }; +@@ -40,23 +40,27 @@ int string_get_size(u64 size, const enum + char tmp[8]; + + tmp[0] = '\0'; +- +- for (i = 0; size > divisor[units] && units_str[units][i]; i++) +- remainder = do_div(size, divisor[units]); +- +- sf_cap = size; +- for (j = 0; sf_cap*10 < 1000; j++) +- sf_cap *= 10; +- +- if (j) { +- remainder *= 1000; +- do_div(remainder, divisor[units]); +- snprintf(tmp, sizeof(tmp), ".%03lld", +- (unsigned long long)remainder); +- tmp[j+1] = '\0'; ++ i = 0; ++ if (size >= divisor[units]) { ++ while (size >= divisor[units] && units_str[units][i]) { ++ remainder = do_div(size, divisor[units]); ++ i++; ++ } ++ ++ sf_cap = size; ++ for (j = 0; sf_cap*10 < 1000; j++) ++ sf_cap *= 10; ++ ++ if (j) { ++ remainder *= 1000; ++ do_div(remainder, divisor[units]); ++ snprintf(tmp, sizeof(tmp), ".%03lld", ++ (unsigned long long)remainder); ++ tmp[j+1] = '\0'; ++ } + } + +- snprintf(buf, len, "%lld%s%s", (unsigned long long)size, ++ snprintf(buf, len, "%lld%s %s", (unsigned long long)size, + tmp, units_str[units][i]); + + return 0; +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/Makefile linux-2.6.27.25-0.1.1/Makefile +--- linux-2.6.27.23-0.1.1/Makefile 2009-06-16 13:40:23.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/Makefile 2009-07-24 10:25:05.000000000 +0100 +@@ -1,7 +1,7 @@ + VERSION = 2 + PATCHLEVEL = 6 + SUBLEVEL = 27 +-EXTRAVERSION = .23-0.1.1 ++EXTRAVERSION = .25-0.1.1 + NAME = Trembling Tortoise + + # *DOCUMENTATION* +@@ -1016,8 +1016,9 @@ endef + # directory for generated filesas used by some architectures. + define create-symlink + if [ ! -L include/asm ]; then \ +- if [ -d arch/$(SRCARCH)/include/asm ]; then \ ++ if [ -d $(srctree)/arch/$(SRCARCH)/include/asm ]; then \ + echo ' SYMLINK $@ -> arch/$(SRCARCH)/include/asm'; \ ++ mkdir -p arch/$(SRCARCH)/include/asm; \ + ln -fsn ../arch/$(SRCARCH)/include/asm $@; \ + else \ + echo ' SYMLINK $@ -> include/asm-$(SRCARCH)'; \ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/mm/hugetlb.c linux-2.6.27.25-0.1.1/mm/hugetlb.c +--- linux-2.6.27.23-0.1.1/mm/hugetlb.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/mm/hugetlb.c 2009-07-24 10:23:52.000000000 +0100 +@@ -287,7 +287,7 @@ void resv_map_release(struct kref *ref) + static struct resv_map *vma_resv_map(struct vm_area_struct *vma) + { + VM_BUG_ON(!is_vm_hugetlb_page(vma)); +- if (!(vma->vm_flags & VM_SHARED)) ++ if (!(vma->vm_flags & VM_MAYSHARE)) + return (struct resv_map *)(get_vma_private_data(vma) & + ~HPAGE_RESV_MASK); + return 0; +@@ -296,7 +296,7 @@ static struct resv_map *vma_resv_map(str + static void set_vma_resv_map(struct vm_area_struct *vma, struct resv_map *map) + { + VM_BUG_ON(!is_vm_hugetlb_page(vma)); +- VM_BUG_ON(vma->vm_flags & VM_SHARED); ++ VM_BUG_ON(vma->vm_flags & VM_MAYSHARE); + + set_vma_private_data(vma, (get_vma_private_data(vma) & + HPAGE_RESV_MASK) | (unsigned long)map); +@@ -305,7 +305,7 @@ static void set_vma_resv_map(struct vm_a + static void set_vma_resv_flags(struct vm_area_struct *vma, unsigned long flags) + { + VM_BUG_ON(!is_vm_hugetlb_page(vma)); +- VM_BUG_ON(vma->vm_flags & VM_SHARED); ++ VM_BUG_ON(vma->vm_flags & VM_MAYSHARE); + + set_vma_private_data(vma, get_vma_private_data(vma) | flags); + } +@@ -324,7 +324,7 @@ static void decrement_hugepage_resv_vma( + if (vma->vm_flags & VM_NORESERVE) + return; + +- if (vma->vm_flags & VM_SHARED) { ++ if (vma->vm_flags & VM_MAYSHARE) { + /* Shared mappings always use reserves */ + h->resv_huge_pages--; + } else if (is_vma_resv_set(vma, HPAGE_RESV_OWNER)) { +@@ -340,14 +340,14 @@ static void decrement_hugepage_resv_vma( + void reset_vma_resv_huge_pages(struct vm_area_struct *vma) + { + VM_BUG_ON(!is_vm_hugetlb_page(vma)); +- if (!(vma->vm_flags & VM_SHARED)) ++ if (!(vma->vm_flags & VM_MAYSHARE)) + vma->vm_private_data = (void *)0; + } + + /* Returns true if the VMA has associated reserve pages */ + static int vma_has_reserves(struct vm_area_struct *vma) + { +- if (vma->vm_flags & VM_SHARED) ++ if (vma->vm_flags & VM_MAYSHARE) + return 1; + if (is_vma_resv_set(vma, HPAGE_RESV_OWNER)) + return 1; +@@ -899,7 +899,7 @@ static int vma_needs_reservation(struct + struct address_space *mapping = vma->vm_file->f_mapping; + struct inode *inode = mapping->host; + +- if (vma->vm_flags & VM_SHARED) { ++ if (vma->vm_flags & VM_MAYSHARE) { + pgoff_t idx = vma_hugecache_offset(h, vma, addr); + return region_chg(&inode->i_mapping->private_list, + idx, idx + 1); +@@ -924,7 +924,7 @@ static void vma_commit_reservation(struc + struct address_space *mapping = vma->vm_file->f_mapping; + struct inode *inode = mapping->host; + +- if (vma->vm_flags & VM_SHARED) { ++ if (vma->vm_flags & VM_MAYSHARE) { + pgoff_t idx = vma_hugecache_offset(h, vma, addr); + region_add(&inode->i_mapping->private_list, idx, idx + 1); + +@@ -1894,7 +1894,7 @@ retry_avoidcopy: + * at the time of fork() could consume its reserves on COW instead + * of the full address range. + */ +- if (!(vma->vm_flags & VM_SHARED) && ++ if (!(vma->vm_flags & VM_MAYSHARE) && + is_vma_resv_set(vma, HPAGE_RESV_OWNER) && + old_page != pagecache_page) + outside_reserve = 1; +@@ -2001,7 +2001,7 @@ retry: + clear_huge_page(page, address, huge_page_size(h)); + __SetPageUptodate(page); + +- if (vma->vm_flags & VM_SHARED) { ++ if (vma->vm_flags & VM_MAYSHARE) { + int err; + struct inode *inode = mapping->host; + +@@ -2105,7 +2105,7 @@ int hugetlb_fault(struct mm_struct *mm, + goto out_unlock; + } + +- if (!(vma->vm_flags & VM_SHARED)) ++ if (!(vma->vm_flags & VM_MAYSHARE)) + pagecache_page = hugetlbfs_pagecache_page(h, + vma, address); + } +@@ -2256,7 +2256,7 @@ int hugetlb_reserve_pages(struct inode * + * to reserve the full area even if read-only as mprotect() may be + * called to make the mapping read-write. Assume !vma is a shm mapping + */ +- if (!vma || vma->vm_flags & VM_SHARED) ++ if (!vma || vma->vm_flags & VM_MAYSHARE) + chg = region_chg(&inode->i_mapping->private_list, from, to); + else { + struct resv_map *resv_map = resv_map_alloc(); +@@ -2285,7 +2285,7 @@ int hugetlb_reserve_pages(struct inode * + hugetlb_put_quota(inode->i_mapping, chg); + goto end; + } +- if (!vma || vma->vm_flags & VM_SHARED) ++ if (!vma || vma->vm_flags & VM_MAYSHARE) + region_add(&inode->i_mapping->private_list, from, to); + end: + trace_hugetlb_pages_reserve(inode, from, to, ret); +@@ -2299,6 +2299,7 @@ void hugetlb_unreserve_pages(struct inod + + trace_hugetlb_pages_unreserve(inode, offset, freed); + chg = region_truncate(&inode->i_mapping->private_list, offset); ++ + spin_lock(&inode->i_lock); + inode->i_blocks -= blocks_per_huge_page(h); + spin_unlock(&inode->i_lock); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/mm/memory.c linux-2.6.27.25-0.1.1/mm/memory.c +--- linux-2.6.27.23-0.1.1/mm/memory.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/mm/memory.c 2009-07-24 10:23:52.000000000 +0100 +@@ -1932,7 +1932,16 @@ static int do_wp_page(struct mm_struct * + * read-only shared pages can get COWed by + * get_user_pages(.write=1, .force=1). + */ +- if (vma->vm_ops && vma->vm_ops->page_mkwrite) { ++ if (vma->vm_ops && vma->vm_ops->_pmkw.page_mkwrite) { ++ struct vm_fault vmf; ++ int tmp; ++ ++ vmf.virtual_address = (void __user *)(address & ++ PAGE_MASK); ++ vmf.pgoff = old_page->index; ++ vmf.flags = FAULT_FLAG_WRITE|FAULT_FLAG_MKWRITE; ++ vmf.page = old_page; ++ + /* + * Notify the address space that the page is about to + * become writable so that it can prohibit this or wait +@@ -1944,8 +1953,42 @@ static int do_wp_page(struct mm_struct * + page_cache_get(old_page); + pte_unmap_unlock(page_table, ptl); + +- if (vma->vm_ops->page_mkwrite(vma, old_page) < 0) +- goto unwritable_page; ++ if (likely(vma->vm_flags & VM_PAGE_MKWRITE2)) { ++ tmp = vma->vm_ops->_pmkw.page_mkwrite2(vma, &vmf); ++ if (unlikely(tmp & ++ (VM_FAULT_ERROR | VM_FAULT_NOPAGE))) { ++ ret = tmp; ++ goto unwritable_page; ++ } ++ if (unlikely(!(tmp & VM_FAULT_LOCKED))) { ++ lock_page(old_page); ++ if (!old_page->mapping) { ++ ret = 0; /* retry the fault */ ++ unlock_page(old_page); ++ goto unwritable_page; ++ } ++ } else ++ VM_BUG_ON(!PageLocked(old_page)); ++ } else { ++ tmp = vma->vm_ops->_pmkw.page_mkwrite(vma, old_page); ++ lock_page(old_page); ++ if (!old_page->mapping) { ++ /* ++ * page_mkwrite API is broken, it returns error even ++ * if the page was invalidated. So if it was, then ++ * clear that error here so we don't get a SIGBUS. ++ */ ++ ret = 0; /* retry the fault */ ++ unlock_page(old_page); ++ goto unwritable_page; ++ } ++ if (tmp) { ++ /* can't distinguish OOM from SIGBUS, but oh well */ ++ ret = VM_FAULT_SIGBUS; ++ unlock_page(old_page); ++ goto unwritable_page; ++ } ++ } + + /* + * Since we dropped the lock we need to revalidate +@@ -1955,9 +1998,11 @@ static int do_wp_page(struct mm_struct * + */ + page_table = pte_offset_map_lock(mm, pmd, address, + &ptl); +- page_cache_release(old_page); +- if (!pte_same(*page_table, orig_pte)) ++ if (!pte_same(*page_table, orig_pte)) { ++ unlock_page(old_page); ++ page_cache_release(old_page); + goto unlock; ++ } + + page_mkwrite = 1; + } +@@ -2061,9 +2106,6 @@ gotten: + unlock: + pte_unmap_unlock(page_table, ptl); + if (dirty_page) { +- if (vma->vm_file) +- file_update_time(vma->vm_file); +- + /* + * Yes, Virginia, this is actually required to prevent a race + * with clear_page_dirty_for_io() from clearing the page dirty +@@ -2072,21 +2114,46 @@ unlock: + * + * do_no_page is protected similarly. + */ +- wait_on_page_locked(dirty_page); +- set_page_dirty_balance(dirty_page, page_mkwrite); ++ if (!page_mkwrite) { ++ wait_on_page_locked(dirty_page); ++ set_page_dirty_balance(dirty_page, page_mkwrite); ++ } + put_page(dirty_page); ++ if (page_mkwrite) { ++ struct address_space *mapping = dirty_page->mapping; ++ ++ set_page_dirty(dirty_page); ++ unlock_page(dirty_page); ++ page_cache_release(dirty_page); ++ if (mapping) { ++ /* ++ * Some device drivers do not set page.mapping ++ * but still dirty their pages ++ */ ++ balance_dirty_pages_ratelimited(mapping); ++ } ++ } ++ ++ /* file_update_time outside page_lock */ ++ if (vma->vm_file) ++ file_update_time(vma->vm_file); + } + return ret; + oom_free_new: + page_cache_release(new_page); + oom: +- if (old_page) ++ if (old_page) { ++ if (page_mkwrite) { ++ unlock_page(old_page); ++ page_cache_release(old_page); ++ } + page_cache_release(old_page); ++ } + return VM_FAULT_OOM; + + unwritable_page: + page_cache_release(old_page); +- return VM_FAULT_SIGBUS; ++ return ret; + } + + /* +@@ -2603,25 +2670,41 @@ static int __do_fault(struct mm_struct * + * address space wants to know that the page is about + * to become writable + */ +- if (vma->vm_ops->page_mkwrite) { ++ if (vma->vm_ops->_pmkw.page_mkwrite) { ++ int tmp; ++ + unlock_page(page); +- if (vma->vm_ops->page_mkwrite(vma, page) < 0) { +- ret = VM_FAULT_SIGBUS; +- anon = 1; /* no anon but release vmf.page */ +- goto out_unlocked; +- } +- lock_page(page); +- /* +- * XXX: this is not quite right (racy vs +- * invalidate) to unlock and relock the page +- * like this, however a better fix requires +- * reworking page_mkwrite locking API, which +- * is better done later. +- */ +- if (!page->mapping) { +- ret = 0; +- anon = 1; /* no anon but release vmf.page */ +- goto out; ++ vmf.flags = FAULT_FLAG_WRITE|FAULT_FLAG_MKWRITE; ++ ++ if (likely(vma->vm_flags & VM_PAGE_MKWRITE2)) { ++ tmp = vma->vm_ops->_pmkw.page_mkwrite2(vma, &vmf); ++ if (unlikely(tmp & ++ (VM_FAULT_ERROR | VM_FAULT_NOPAGE))) { ++ ret = tmp; ++ goto unwritable_page; ++ } ++ if (unlikely(!(tmp & VM_FAULT_LOCKED))) { ++ lock_page(page); ++ if (!page->mapping) { ++ ret = 0; /* retry the fault */ ++ unlock_page(page); ++ goto unwritable_page; ++ } ++ } else ++ VM_BUG_ON(!PageLocked(page)); ++ } else { ++ tmp = vma->vm_ops->_pmkw.page_mkwrite(vma, page); ++ lock_page(page); ++ if (!page->mapping) { ++ ret = 0; /* retry the fault */ ++ unlock_page(page); ++ goto unwritable_page; ++ } ++ if (tmp) { ++ ret = VM_FAULT_SIGBUS; ++ unlock_page(page); ++ goto unwritable_page; ++ } + } + page_mkwrite = 1; + } +@@ -2679,19 +2762,35 @@ static int __do_fault(struct mm_struct * + pte_unmap_unlock(page_table, ptl); + + out: +- unlock_page(vmf.page); +-out_unlocked: +- if (anon) +- page_cache_release(vmf.page); +- else if (dirty_page) { +- if (vma->vm_file) +- file_update_time(vma->vm_file); ++ if (dirty_page) { ++ struct address_space *mapping = page->mapping; + +- set_page_dirty_balance(dirty_page, page_mkwrite); ++ if (set_page_dirty(dirty_page)) ++ page_mkwrite = 1; ++ unlock_page(dirty_page); + put_page(dirty_page); ++ if (page_mkwrite && mapping) { ++ /* ++ * Some device drivers do not set page.mapping but still ++ * dirty their pages ++ */ ++ balance_dirty_pages_ratelimited(mapping); ++ } ++ ++ /* file_update_time outside page_lock */ ++ if (vma->vm_file) ++ file_update_time(vma->vm_file); ++ } else { ++ unlock_page(vmf.page); ++ if (anon) ++ page_cache_release(vmf.page); + } + + return ret; ++ ++unwritable_page: ++ page_cache_release(page); ++ return ret; + } + + static int do_linear_fault(struct mm_struct *mm, struct vm_area_struct *vma, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/mm/mmap.c linux-2.6.27.25-0.1.1/mm/mmap.c +--- linux-2.6.27.23-0.1.1/mm/mmap.c 2009-06-16 13:39:37.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/mm/mmap.c 2009-07-24 10:23:52.000000000 +0100 +@@ -1068,7 +1068,7 @@ int vma_wants_writenotify(struct vm_area + return 0; + + /* The backer wishes to know when pages are first written to? */ +- if (vma->vm_ops && vma->vm_ops->page_mkwrite) ++ if (vma->vm_ops && vma->vm_ops->_pmkw.page_mkwrite) + return 1; + + /* The open routine did something to the protections already? */ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/mm/vmscan.c linux-2.6.27.25-0.1.1/mm/vmscan.c +--- linux-2.6.27.23-0.1.1/mm/vmscan.c 2009-06-16 13:53:09.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/mm/vmscan.c 2009-07-24 10:23:52.000000000 +0100 +@@ -1988,7 +1988,7 @@ int zone_reclaim_mode __read_mostly; + * of a node considered for each zone_reclaim. 4 scans 1/16th of + * a zone. + */ +-#define ZONE_RECLAIM_PRIORITY 4 ++#define ZONE_RECLAIM_PRIORITY 0 + + /* + * Percentage of pages in a zone that must be unmapped for zone_reclaim to +@@ -2052,6 +2052,8 @@ static int __zone_reclaim(struct zone *z + + slab_reclaimable = zone_page_state(zone, NR_SLAB_RECLAIMABLE); + if (slab_reclaimable > zone->min_slab_pages) { ++ unsigned long lru_pages = zone_page_state(zone, NR_ACTIVE) ++ + zone_page_state(zone, NR_INACTIVE); + /* + * shrink_slab() does not currently allow us to determine how + * many pages were freed in this zone. So we take the current +@@ -2062,10 +2064,7 @@ static int __zone_reclaim(struct zone *z + * Note that shrink_slab will free memory on all zones and may + * take a long time. + */ +- while (shrink_slab(sc.nr_scanned, gfp_mask, order) && +- zone_page_state(zone, NR_SLAB_RECLAIMABLE) > +- slab_reclaimable - nr_pages) +- ; ++ shrink_slab(sc.nr_scanned, gfp_mask, lru_pages); + + /* + * Update nr_reclaimed by the number of slab pages we +@@ -2120,10 +2119,7 @@ int zone_reclaim(struct zone *zone, gfp_ + if (node_state(node_id, N_CPU) && node_id != numa_node_id()) + return 0; + +- if (zone_test_and_set_flag(zone, ZONE_RECLAIM_LOCKED)) +- return 0; + ret = __zone_reclaim(zone, gfp_mask, order); +- zone_clear_flag(zone, ZONE_RECLAIM_LOCKED); + + return ret; + } +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/net/core/pktgen.c linux-2.6.27.25-0.1.1/net/core/pktgen.c +--- linux-2.6.27.23-0.1.1/net/core/pktgen.c 2009-06-16 13:53:17.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/net/core/pktgen.c 2009-07-24 10:24:01.000000000 +0100 +@@ -2449,7 +2449,7 @@ static inline void free_SAs(struct pktge + if (pkt_dev->cflows) { + /* let go of the SAs if we have them */ + int i = 0; +- for (; i < pkt_dev->nflows; i++){ ++ for (; i < pkt_dev->cflows; i++) { + struct xfrm_state *x = pkt_dev->flows[i].x; + if (x) { + xfrm_state_put(x); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/net/ipv4/tcp_input.c linux-2.6.27.25-0.1.1/net/ipv4/tcp_input.c +--- linux-2.6.27.23-0.1.1/net/ipv4/tcp_input.c 2009-06-16 13:53:17.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/net/ipv4/tcp_input.c 2009-07-24 10:24:01.000000000 +0100 +@@ -931,6 +931,8 @@ static void tcp_init_metrics(struct sock + tcp_bound_rto(sk); + if (inet_csk(sk)->icsk_rto < TCP_TIMEOUT_INIT && !tp->rx_opt.saw_tstamp) + goto reset; ++ ++cwnd: + tp->snd_cwnd = tcp_init_cwnd(tp, dst); + tp->snd_cwnd_stamp = tcp_time_stamp; + return; +@@ -945,6 +947,7 @@ reset: + tp->mdev = tp->mdev_max = tp->rttvar = TCP_TIMEOUT_INIT; + inet_csk(sk)->icsk_rto = TCP_TIMEOUT_INIT; + } ++ goto cwnd; + } + + static void tcp_update_reordering(struct sock *sk, const int metric, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/net/iucv/af_iucv.c linux-2.6.27.25-0.1.1/net/iucv/af_iucv.c +--- linux-2.6.27.23-0.1.1/net/iucv/af_iucv.c 2009-06-16 13:39:42.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/net/iucv/af_iucv.c 2009-07-24 10:24:01.000000000 +0100 +@@ -503,9 +503,15 @@ static int iucv_sock_connect(struct sock + } + + if (sk->sk_state == IUCV_DISCONN) { +- release_sock(sk); +- return -ECONNREFUSED; ++ err = -ECONNREFUSED; + } ++ ++ if (err) { ++ iucv_path_sever(iucv->path, NULL); ++ iucv_path_free(iucv->path); ++ iucv->path = NULL; ++ } ++ + done: + release_sock(sk); + return err; +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/security/selinux/hooks.c linux-2.6.27.25-0.1.1/security/selinux/hooks.c +--- linux-2.6.27.23-0.1.1/security/selinux/hooks.c 2009-06-16 13:41:02.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/security/selinux/hooks.c 2009-07-24 10:24:36.000000000 +0100 +@@ -4475,7 +4475,7 @@ static int selinux_ip_postroute_iptables + if (err) + return err; + +- if (send_perm != 0) ++ if (!send_perm) + return 0; + + err = sel_netport_sid(sk->sk_protocol, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/pci/hda/hda_codec.c linux-2.6.27.25-0.1.1/sound/pci/hda/hda_codec.c +--- linux-2.6.27.23-0.1.1/sound/pci/hda/hda_codec.c 2009-06-16 13:40:23.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/pci/hda/hda_codec.c 2009-07-24 10:24:24.000000000 +0100 +@@ -55,6 +55,7 @@ static struct hda_vendor_id hda_vendor_i + { 0x1002, "ATI" }, + { 0x1057, "Motorola" }, + { 0x1095, "Silicon Image" }, ++ { 0x10de, "Nvidia" }, + { 0x10ec, "Realtek" }, + { 0x1106, "VIA" }, + { 0x111d, "IDT" }, +@@ -64,7 +65,9 @@ static struct hda_vendor_id hda_vendor_i + { 0x14f1, "Conexant" }, + { 0x17e8, "Chrontel" }, + { 0x1854, "LG" }, ++ { 0x1aec, "Wolfson Microelectronics" }, + { 0x434d, "C-Media" }, ++ { 0x8086, "Intel" }, + { 0x8384, "SigmaTel" }, + {} /* terminator */ + }; +@@ -97,6 +100,9 @@ static const struct hda_codec_preset *hd + #ifdef CONFIG_SND_HDA_CODEC_NVHDMI + snd_hda_preset_nvhdmi, + #endif ++#ifdef CONFIG_SND_HDA_CODEC_INTELHDMI ++ snd_hda_preset_intelhdmi, ++#endif + NULL + }; + +@@ -124,6 +130,83 @@ make_codec_cmd(struct hda_codec *codec, + return val; + } + ++const char *snd_hda_get_jack_location(u32 cfg) ++{ ++ static char *bases[7] = { ++ "N/A", "Rear", "Front", "Left", "Right", "Top", "Bottom", ++ }; ++ static unsigned char specials_idx[] = { ++ 0x07, 0x08, ++ 0x17, 0x18, 0x19, ++ 0x37, 0x38 ++ }; ++ static char *specials[] = { ++ "Rear Panel", "Drive Bar", ++ "Riser", "HDMI", "ATAPI", ++ "Mobile-In", "Mobile-Out" ++ }; ++ int i; ++ cfg = (cfg & AC_DEFCFG_LOCATION) >> AC_DEFCFG_LOCATION_SHIFT; ++ if ((cfg & 0x0f) < 7) ++ return bases[cfg & 0x0f]; ++ for (i = 0; i < ARRAY_SIZE(specials_idx); i++) { ++ if (cfg == specials_idx[i]) ++ return specials[i]; ++ } ++ return "UNKNOWN"; ++} ++ ++const char *snd_hda_get_jack_connectivity(u32 cfg) ++{ ++ static char *jack_locations[4] = { "Ext", "Int", "Sep", "Oth" }; ++ ++ return jack_locations[(cfg >> (AC_DEFCFG_LOCATION_SHIFT + 4)) & 3]; ++} ++ ++const char *snd_hda_get_jack_type(u32 cfg) ++{ ++ static char *jack_types[16] = { ++ "Line Out", "Speaker", "HP Out", "CD", ++ "SPDIF Out", "Digital Out", "Modem Line", "Modem Hand", ++ "Line In", "Aux", "Mic", "Telephony", ++ "SPDIF In", "Digitial In", "Reserved", "Other" ++ }; ++ ++ return jack_types[(cfg & AC_DEFCFG_DEVICE) ++ >> AC_DEFCFG_DEVICE_SHIFT]; ++} ++ ++/* ++ * Send and receive a verb ++ */ ++static int codec_exec_verb(struct hda_codec *codec, unsigned int cmd, ++ unsigned int *res) ++{ ++ struct hda_bus *bus = codec->bus; ++ int err; ++ ++ if (res) ++ *res = -1; ++ again: ++ snd_hda_power_up(codec); ++ mutex_lock(&bus->cmd_mutex); ++ err = bus->ops.command(bus, cmd); ++ if (!err && res) ++ *res = bus->ops.get_response(bus); ++ mutex_unlock(&bus->cmd_mutex); ++ snd_hda_power_down(codec); ++ if (res && *res == -1 && bus->rirb_error) { ++ if (bus->response_reset) { ++ snd_printd("hda_codec: resetting BUS due to " ++ "fatal communication error\n"); ++ bus->ops.bus_reset(bus); ++ } ++ goto again; ++ } ++ bus->response_reset = 0; ++ return err; ++} ++ + /** + * snd_hda_codec_read - send a command and get the response + * @codec: the HDA codec +@@ -140,27 +223,9 @@ unsigned int snd_hda_codec_read(struct h + int direct, + unsigned int verb, unsigned int parm) + { +- struct hda_bus *bus = codec->bus; +- unsigned int cmd, res; +- int repeated = 0; +- +- cmd = make_codec_cmd(codec, nid, direct, verb, parm); +- snd_hda_power_up(codec); +- mutex_lock(&bus->cmd_mutex); +- again: +- if (!bus->ops.command(bus, cmd)) { +- res = bus->ops.get_response(bus); +- if (res == -1 && bus->rirb_error) { +- if (repeated++ < 1) { +- snd_printd(KERN_WARNING "hda_codec: " +- "Trying verb 0x%08x again\n", cmd); +- goto again; +- } +- } +- } else +- res = (unsigned int)-1; +- mutex_unlock(&bus->cmd_mutex); +- snd_hda_power_down(codec); ++ unsigned cmd = make_codec_cmd(codec, nid, direct, verb, parm); ++ unsigned int res; ++ codec_exec_verb(codec, cmd, &res); + return res; + } + +@@ -179,17 +244,10 @@ unsigned int snd_hda_codec_read(struct h + int snd_hda_codec_write(struct hda_codec *codec, hda_nid_t nid, int direct, + unsigned int verb, unsigned int parm) + { +- struct hda_bus *bus = codec->bus; ++ unsigned int cmd = make_codec_cmd(codec, nid, direct, verb, parm); + unsigned int res; +- int err; +- +- res = make_codec_cmd(codec, nid, direct, verb, parm); +- snd_hda_power_up(codec); +- mutex_lock(&bus->cmd_mutex); +- err = bus->ops.command(bus, res); +- mutex_unlock(&bus->cmd_mutex); +- snd_hda_power_down(codec); +- return err; ++ return codec_exec_verb(codec, cmd, ++ codec->bus->sync_write ? &res : NULL); + } + + /** +@@ -427,6 +485,28 @@ static int snd_hda_bus_dev_free(struct s + return snd_hda_bus_free(bus); + } + ++/* ++ * backward-compatible ops ++ */ ++static int old_bus_ops_command(struct hda_codec *codec, hda_nid_t nid, ++ int direct, unsigned int verb, unsigned int parm) ++{ ++ unsigned int cmd = make_codec_cmd(codec, nid, direct, verb, parm); ++ return codec->bus->ops.command(codec->bus, cmd); ++} ++ ++static unsigned int old_bus_ops_get_response(struct hda_codec *codec) ++{ ++ return codec->bus->ops.get_response(codec->bus); ++} ++ ++#ifdef CONFIG_SND_HDA_POWER_SAVE ++static void old_bus_ops_pm_notify(struct hda_codec *codec) ++{ ++ codec->bus->ops.pm_notify(codec->bus); ++} ++#endif ++ + /** + * snd_hda_bus_new - create a HDA bus + * @card: the card entry +@@ -462,6 +542,12 @@ int __devinit snd_hda_bus_new(struct snd + bus->pci = temp->pci; + bus->modelname = temp->modelname; + bus->ops = temp->ops; ++ bus->old_ops.command = old_bus_ops_command; ++ bus->old_ops.get_response = old_bus_ops_get_response; ++ bus->old_ops.private_free = bus->ops.private_free; ++#ifdef CONFIG_SND_HDA_POWER_SAVE ++ bus->old_ops.pm_notify = old_bus_ops_pm_notify; ++#endif + + mutex_init(&bus->cmd_mutex); + INIT_LIST_HEAD(&bus->codec_list); +@@ -1645,6 +1731,8 @@ int snd_hda_create_spdif_out_ctls(struct + } + for (dig_mix = dig_mixes; dig_mix->name; dig_mix++) { + kctl = snd_ctl_new1(dig_mix, codec); ++ if (!kctl) ++ return -ENOMEM; + kctl->id.index = idx; + kctl->private_value = nid; + err = snd_ctl_add(codec->bus->card, kctl); +@@ -1792,6 +1880,8 @@ int snd_hda_create_spdif_in_ctls(struct + } + for (dig_mix = dig_in_ctls; dig_mix->name; dig_mix++) { + kctl = snd_ctl_new1(dig_mix, codec); ++ if (!kctl) ++ return -ENOMEM; + kctl->private_value = nid; + err = snd_ctl_add(codec->bus->card, kctl); + if (err < 0) +@@ -1829,24 +1919,22 @@ int snd_hda_create_spdif_in_ctls(struct + int snd_hda_codec_write_cache(struct hda_codec *codec, hda_nid_t nid, + int direct, unsigned int verb, unsigned int parm) + { +- struct hda_bus *bus = codec->bus; +- unsigned int res; +- int err; ++ int err = snd_hda_codec_write(codec, nid, direct, verb, parm); ++ struct hda_cache_head *c; ++ u32 key; + +- res = make_codec_cmd(codec, nid, direct, verb, parm); +- snd_hda_power_up(codec); +- mutex_lock(&bus->cmd_mutex); +- err = bus->ops.command(bus, res); +- if (!err) { +- struct hda_cache_head *c; +- u32 key = build_cmd_cache_key(nid, verb); +- c = get_alloc_hash(&codec->cmd_cache, key); +- if (c) +- c->val = parm; +- } +- mutex_unlock(&bus->cmd_mutex); +- snd_hda_power_down(codec); +- return err; ++ if (err < 0) ++ return err; ++ /* parm may contain the verb stuff for get/set amp */ ++ verb = verb | (parm >> 8); ++ parm &= 0xff; ++ key = build_cmd_cache_key(nid, verb); ++ mutex_lock(&codec->bus->cmd_mutex); ++ c = get_alloc_hash(&codec->cmd_cache, key); ++ if (c) ++ c->val = parm; ++ mutex_unlock(&codec->bus->cmd_mutex); ++ return 0; + } + + /* resume the all commands from the cache */ +@@ -3221,11 +3309,10 @@ const char *auto_pin_cfg_labels[AUTO_PIN + /** + * snd_hda_suspend - suspend the codecs + * @bus: the HDA bus +- * @state: suspsend state + * + * Returns 0 if successful. + */ +-int snd_hda_suspend(struct hda_bus *bus, pm_message_t state) ++int snd_hda_suspend(struct hda_bus *bus) + { + struct hda_codec *codec; + +@@ -3272,3 +3359,34 @@ int snd_hda_codecs_inuse(struct hda_bus + } + #endif + #endif ++ ++/* ++ * used by hda_proc.c and hda_eld.c ++ */ ++void snd_print_pcm_rates(int pcm, char *buf, int buflen) ++{ ++ static unsigned int rates[] = { ++ 8000, 11025, 16000, 22050, 32000, 44100, 48000, 88200, ++ 96000, 176400, 192000, 384000 ++ }; ++ int i, j; ++ ++ for (i = 0, j = 0; i < ARRAY_SIZE(rates); i++) ++ if (pcm & (1 << i)) ++ j += snprintf(buf + j, buflen - j, " %d", rates[i]); ++ ++ buf[j] = '\0'; /* necessary when j == 0 */ ++} ++ ++void snd_print_pcm_bits(int pcm, char *buf, int buflen) ++{ ++ static unsigned int bits[] = { 8, 16, 20, 24, 32 }; ++ int i, j; ++ ++ for (i = 0, j = 0; i < ARRAY_SIZE(bits); i++) ++ if (pcm & (AC_SUPPCM_BITS_8 << i)) ++ j += snprintf(buf + j, buflen - j, " %d", bits[i]); ++ ++ buf[j] = '\0'; /* necessary when j == 0 */ ++} ++ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/pci/hda/hda_codec.h linux-2.6.27.25-0.1.1/sound/pci/hda/hda_codec.h +--- linux-2.6.27.23-0.1.1/sound/pci/hda/hda_codec.h 2009-06-16 13:40:23.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/pci/hda/hda_codec.h 2009-07-24 10:24:24.000000000 +0100 +@@ -541,12 +541,25 @@ struct hda_bus_ops { + unsigned int (*get_response)(struct hda_bus *bus); + /* free the private data */ + void (*private_free)(struct hda_bus *); ++ /* reset bus for retry verb */ ++ void (*bus_reset)(struct hda_bus *bus); + #ifdef CONFIG_SND_HDA_POWER_SAVE + /* notify power-up/down from codec to controller */ + void (*pm_notify)(struct hda_bus *bus); + #endif + }; + ++/* old hda_bus_ops struct -- just for really evil binary compatibility issues */ ++struct hda_old_bus_ops { ++ int (*command)(struct hda_codec *codec, hda_nid_t nid, int direct, ++ unsigned int verb, unsigned int parm); ++ unsigned int (*get_response)(struct hda_codec *codec); ++ void (*private_free)(struct hda_bus *); ++#ifdef CONFIG_SND_HDA_POWER_SAVE ++ void (*pm_notify)(struct hda_codec *codec); ++#endif ++}; ++ + /* template to pass to the bus constructor */ + struct hda_bus_template { + void *private_data; +@@ -568,7 +581,7 @@ struct hda_bus { + void *private_data; + struct pci_dev *pci; + const char *modelname; +- struct hda_bus_ops ops; ++ struct hda_old_bus_ops old_ops; /* old ops; for binary compatibility */ + + /* codec linked list */ + struct list_head codec_list; +@@ -579,14 +592,24 @@ struct hda_bus { + + /* unsolicited event queue */ + struct hda_bus_unsolicited *unsol; +- char workq_name[16]; +- struct workqueue_struct *workq; /* common workqueue for codecs */ + + struct snd_info_entry *proc; + + /* misc op flags */ + unsigned int needs_damn_long_delay :1; ++ unsigned int allow_bus_reset:1; /* allow bus reset at fatal error */ ++ unsigned int sync_write:1; /* sync after verb write */ ++ /* status for codec/controller */ + unsigned int rirb_error:1; /* error in codec communication */ ++ unsigned int response_reset:1; /* controller was reset */ ++ unsigned int in_reset:1; /* during reset operation */ ++ ++ /* real ops */ ++ struct hda_bus_ops ops; ++ ++ /* additional workq stuff */ ++ char workq_name[16]; ++ struct workqueue_struct *workq; /* common workqueue for codecs */ + }; + + /* +@@ -828,11 +851,18 @@ void snd_hda_get_codec_name(struct hda_c + * power management + */ + #ifdef CONFIG_PM +-int snd_hda_suspend(struct hda_bus *bus, pm_message_t state); ++int snd_hda_suspend(struct hda_bus *bus); + int snd_hda_resume(struct hda_bus *bus); + #endif + + /* ++ * get widget information ++ */ ++const char *snd_hda_get_jack_connectivity(u32 cfg); ++const char *snd_hda_get_jack_type(u32 cfg); ++const char *snd_hda_get_jack_location(u32 cfg); ++ ++/* + * power saving + */ + #ifdef CONFIG_SND_HDA_POWER_SAVE +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/pci/hda/hda_eld.c linux-2.6.27.25-0.1.1/sound/pci/hda/hda_eld.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/pci/hda/hda_eld.c 2009-07-24 10:24:24.000000000 +0100 +@@ -0,0 +1,592 @@ ++/* ++ * Generic routines and proc interface for ELD(EDID Like Data) information ++ * ++ * Copyright(c) 2008 Intel Corporation. ++ * ++ * Authors: ++ * Wu Fengguang ++ * ++ * This driver is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This driver is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include "hda_codec.h" ++#include "hda_local.h" ++ ++enum eld_versions { ++ ELD_VER_CEA_861D = 2, ++ ELD_VER_PARTIAL = 31, ++}; ++ ++enum cea_edid_versions { ++ CEA_EDID_VER_NONE = 0, ++ CEA_EDID_VER_CEA861 = 1, ++ CEA_EDID_VER_CEA861A = 2, ++ CEA_EDID_VER_CEA861BCD = 3, ++ CEA_EDID_VER_RESERVED = 4, ++}; ++ ++static char *cea_speaker_allocation_names[] = { ++ /* 0 */ "FL/FR", ++ /* 1 */ "LFE", ++ /* 2 */ "FC", ++ /* 3 */ "RL/RR", ++ /* 4 */ "RC", ++ /* 5 */ "FLC/FRC", ++ /* 6 */ "RLC/RRC", ++ /* 7 */ "FLW/FRW", ++ /* 8 */ "FLH/FRH", ++ /* 9 */ "TC", ++ /* 10 */ "FCH", ++}; ++ ++static char *eld_connection_type_names[4] = { ++ "HDMI", ++ "DisplayPort", ++ "2-reserved", ++ "3-reserved" ++}; ++ ++enum cea_audio_coding_types { ++ AUDIO_CODING_TYPE_REF_STREAM_HEADER = 0, ++ AUDIO_CODING_TYPE_LPCM = 1, ++ AUDIO_CODING_TYPE_AC3 = 2, ++ AUDIO_CODING_TYPE_MPEG1 = 3, ++ AUDIO_CODING_TYPE_MP3 = 4, ++ AUDIO_CODING_TYPE_MPEG2 = 5, ++ AUDIO_CODING_TYPE_AACLC = 6, ++ AUDIO_CODING_TYPE_DTS = 7, ++ AUDIO_CODING_TYPE_ATRAC = 8, ++ AUDIO_CODING_TYPE_SACD = 9, ++ AUDIO_CODING_TYPE_EAC3 = 10, ++ AUDIO_CODING_TYPE_DTS_HD = 11, ++ AUDIO_CODING_TYPE_MLP = 12, ++ AUDIO_CODING_TYPE_DST = 13, ++ AUDIO_CODING_TYPE_WMAPRO = 14, ++ AUDIO_CODING_TYPE_REF_CXT = 15, ++ /* also include valid xtypes below */ ++ AUDIO_CODING_TYPE_HE_AAC = 15, ++ AUDIO_CODING_TYPE_HE_AAC2 = 16, ++ AUDIO_CODING_TYPE_MPEG_SURROUND = 17, ++}; ++ ++enum cea_audio_coding_xtypes { ++ AUDIO_CODING_XTYPE_HE_REF_CT = 0, ++ AUDIO_CODING_XTYPE_HE_AAC = 1, ++ AUDIO_CODING_XTYPE_HE_AAC2 = 2, ++ AUDIO_CODING_XTYPE_MPEG_SURROUND = 3, ++ AUDIO_CODING_XTYPE_FIRST_RESERVED = 4, ++}; ++ ++static char *cea_audio_coding_type_names[] = { ++ /* 0 */ "undefined", ++ /* 1 */ "LPCM", ++ /* 2 */ "AC-3", ++ /* 3 */ "MPEG1", ++ /* 4 */ "MP3", ++ /* 5 */ "MPEG2", ++ /* 6 */ "AAC-LC", ++ /* 7 */ "DTS", ++ /* 8 */ "ATRAC", ++ /* 9 */ "DSD (One Bit Audio)", ++ /* 10 */ "E-AC-3/DD+ (Dolby Digital Plus)", ++ /* 11 */ "DTS-HD", ++ /* 12 */ "MLP (Dolby TrueHD)", ++ /* 13 */ "DST", ++ /* 14 */ "WMAPro", ++ /* 15 */ "HE-AAC", ++ /* 16 */ "HE-AACv2", ++ /* 17 */ "MPEG Surround", ++}; ++ ++/* ++ * The following two lists are shared between ++ * - HDMI audio InfoFrame (source to sink) ++ * - CEA E-EDID Extension (sink to source) ++ */ ++ ++/* ++ * SS1:SS0 index => sample size ++ */ ++static int cea_sample_sizes[4] = { ++ 0, /* 0: Refer to Stream Header */ ++ AC_SUPPCM_BITS_16, /* 1: 16 bits */ ++ AC_SUPPCM_BITS_20, /* 2: 20 bits */ ++ AC_SUPPCM_BITS_24, /* 3: 24 bits */ ++}; ++ ++/* ++ * SF2:SF1:SF0 index => sampling frequency ++ */ ++static int cea_sampling_frequencies[8] = { ++ 0, /* 0: Refer to Stream Header */ ++ SNDRV_PCM_RATE_32000, /* 1: 32000Hz */ ++ SNDRV_PCM_RATE_44100, /* 2: 44100Hz */ ++ SNDRV_PCM_RATE_48000, /* 3: 48000Hz */ ++ SNDRV_PCM_RATE_88200, /* 4: 88200Hz */ ++ SNDRV_PCM_RATE_96000, /* 5: 96000Hz */ ++ SNDRV_PCM_RATE_176400, /* 6: 176400Hz */ ++ SNDRV_PCM_RATE_192000, /* 7: 192000Hz */ ++}; ++ ++static unsigned char hdmi_get_eld_byte(struct hda_codec *codec, hda_nid_t nid, ++ int byte_index) ++{ ++ unsigned int val; ++ ++ val = snd_hda_codec_read(codec, nid, 0, ++ AC_VERB_GET_HDMI_ELDD, byte_index); ++ ++#ifdef BE_PARANOID ++ printk(KERN_INFO "HDMI: ELD data byte %d: 0x%x\n", byte_index, val); ++#endif ++ ++ if ((val & AC_ELDD_ELD_VALID) == 0) { ++ snd_printd(KERN_INFO "HDMI: invalid ELD data byte %d\n", ++ byte_index); ++ val = 0; ++ } ++ ++ return val & AC_ELDD_ELD_DATA; ++} ++ ++#define GRAB_BITS(buf, byte, lowbit, bits) \ ++({ \ ++ BUILD_BUG_ON(lowbit > 7); \ ++ BUILD_BUG_ON(bits > 8); \ ++ BUILD_BUG_ON(bits <= 0); \ ++ \ ++ (buf[byte] >> (lowbit)) & ((1 << (bits)) - 1); \ ++}) ++ ++static void hdmi_update_short_audio_desc(struct cea_sad *a, ++ const unsigned char *buf) ++{ ++ int i; ++ int val; ++ ++ val = GRAB_BITS(buf, 1, 0, 7); ++ a->rates = 0; ++ for (i = 0; i < 7; i++) ++ if (val & (1 << i)) ++ a->rates |= cea_sampling_frequencies[i + 1]; ++ ++ a->channels = GRAB_BITS(buf, 0, 0, 3); ++ a->channels++; ++ ++ a->format = GRAB_BITS(buf, 0, 3, 4); ++ switch (a->format) { ++ case AUDIO_CODING_TYPE_REF_STREAM_HEADER: ++ snd_printd(KERN_INFO ++ "HDMI: audio coding type 0 not expected\n"); ++ break; ++ ++ case AUDIO_CODING_TYPE_LPCM: ++ val = GRAB_BITS(buf, 2, 0, 3); ++ a->sample_bits = 0; ++ for (i = 0; i < 3; i++) ++ if (val & (1 << i)) ++ a->sample_bits |= cea_sample_sizes[i + 1]; ++ break; ++ ++ case AUDIO_CODING_TYPE_AC3: ++ case AUDIO_CODING_TYPE_MPEG1: ++ case AUDIO_CODING_TYPE_MP3: ++ case AUDIO_CODING_TYPE_MPEG2: ++ case AUDIO_CODING_TYPE_AACLC: ++ case AUDIO_CODING_TYPE_DTS: ++ case AUDIO_CODING_TYPE_ATRAC: ++ a->max_bitrate = GRAB_BITS(buf, 2, 0, 8); ++ a->max_bitrate *= 8000; ++ break; ++ ++ case AUDIO_CODING_TYPE_SACD: ++ break; ++ ++ case AUDIO_CODING_TYPE_EAC3: ++ break; ++ ++ case AUDIO_CODING_TYPE_DTS_HD: ++ break; ++ ++ case AUDIO_CODING_TYPE_MLP: ++ break; ++ ++ case AUDIO_CODING_TYPE_DST: ++ break; ++ ++ case AUDIO_CODING_TYPE_WMAPRO: ++ a->profile = GRAB_BITS(buf, 2, 0, 3); ++ break; ++ ++ case AUDIO_CODING_TYPE_REF_CXT: ++ a->format = GRAB_BITS(buf, 2, 3, 5); ++ if (a->format == AUDIO_CODING_XTYPE_HE_REF_CT || ++ a->format >= AUDIO_CODING_XTYPE_FIRST_RESERVED) { ++ snd_printd(KERN_INFO ++ "HDMI: audio coding xtype %d not expected\n", ++ a->format); ++ a->format = 0; ++ } else ++ a->format += AUDIO_CODING_TYPE_HE_AAC - ++ AUDIO_CODING_XTYPE_HE_AAC; ++ break; ++ } ++} ++ ++/* ++ * Be careful, ELD buf could be totally rubbish! ++ */ ++static int hdmi_update_eld(struct hdmi_eld *e, ++ const unsigned char *buf, int size) ++{ ++ int mnl; ++ int i; ++ ++ e->eld_ver = GRAB_BITS(buf, 0, 3, 5); ++ if (e->eld_ver != ELD_VER_CEA_861D && ++ e->eld_ver != ELD_VER_PARTIAL) { ++ snd_printd(KERN_INFO "HDMI: Unknown ELD version %d\n", ++ e->eld_ver); ++ goto out_fail; ++ } ++ ++ e->eld_size = size; ++ e->baseline_len = GRAB_BITS(buf, 2, 0, 8); ++ mnl = GRAB_BITS(buf, 4, 0, 5); ++ e->cea_edid_ver = GRAB_BITS(buf, 4, 5, 3); ++ ++ e->support_hdcp = GRAB_BITS(buf, 5, 0, 1); ++ e->support_ai = GRAB_BITS(buf, 5, 1, 1); ++ e->conn_type = GRAB_BITS(buf, 5, 2, 2); ++ e->sad_count = GRAB_BITS(buf, 5, 4, 4); ++ ++ e->aud_synch_delay = GRAB_BITS(buf, 6, 0, 8) * 2; ++ e->spk_alloc = GRAB_BITS(buf, 7, 0, 7); ++ ++ e->port_id = get_unaligned_le64(buf + 8); ++ ++ /* not specified, but the spec's tendency is little endian */ ++ e->manufacture_id = get_unaligned_le16(buf + 16); ++ e->product_id = get_unaligned_le16(buf + 18); ++ ++ if (mnl > ELD_MAX_MNL) { ++ snd_printd(KERN_INFO "HDMI: MNL is reserved value %d\n", mnl); ++ goto out_fail; ++ } else if (ELD_FIXED_BYTES + mnl > size) { ++ snd_printd(KERN_INFO "HDMI: out of range MNL %d\n", mnl); ++ goto out_fail; ++ } else ++ strlcpy(e->monitor_name, buf + ELD_FIXED_BYTES, mnl); ++ ++ for (i = 0; i < e->sad_count; i++) { ++ if (ELD_FIXED_BYTES + mnl + 3 * (i + 1) > size) { ++ snd_printd(KERN_INFO "HDMI: out of range SAD %d\n", i); ++ goto out_fail; ++ } ++ hdmi_update_short_audio_desc(e->sad + i, ++ buf + ELD_FIXED_BYTES + mnl + 3 * i); ++ } ++ ++ return 0; ++ ++out_fail: ++ e->eld_ver = 0; ++ return -EINVAL; ++} ++ ++static int hdmi_present_sense(struct hda_codec *codec, hda_nid_t nid) ++{ ++ return snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PIN_SENSE, 0); ++} ++ ++static int hdmi_eld_valid(struct hda_codec *codec, hda_nid_t nid) ++{ ++ int eldv; ++ int present; ++ ++ present = hdmi_present_sense(codec, nid); ++ eldv = (present & AC_PINSENSE_ELDV); ++ present = (present & AC_PINSENSE_PRESENCE); ++ ++#ifdef CONFIG_SND_DEBUG_VERBOSE ++ printk(KERN_INFO "HDMI: sink_present = %d, eld_valid = %d\n", ++ !!present, !!eldv); ++#endif ++ ++ return eldv && present; ++} ++ ++int snd_hdmi_get_eld_size(struct hda_codec *codec, hda_nid_t nid) ++{ ++ return snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_HDMI_DIP_SIZE, ++ AC_DIPSIZE_ELD_BUF); ++} ++ ++int snd_hdmi_get_eld(struct hdmi_eld *eld, ++ struct hda_codec *codec, hda_nid_t nid) ++{ ++ int i; ++ int ret; ++ int size; ++ unsigned char *buf; ++ ++ if (!hdmi_eld_valid(codec, nid)) ++ return -ENOENT; ++ ++ size = snd_hdmi_get_eld_size(codec, nid); ++ if (size == 0) { ++ /* wfg: workaround for ASUS P5E-VM HDMI board */ ++ snd_printd(KERN_INFO "HDMI: ELD buf size is 0, force 128\n"); ++ size = 128; ++ } ++ if (size < ELD_FIXED_BYTES || size > PAGE_SIZE) { ++ snd_printd(KERN_INFO "HDMI: invalid ELD buf size %d\n", size); ++ return -ERANGE; ++ } ++ ++ buf = kmalloc(size, GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ for (i = 0; i < size; i++) ++ buf[i] = hdmi_get_eld_byte(codec, nid, i); ++ ++ ret = hdmi_update_eld(eld, buf, size); ++ ++ kfree(buf); ++ return ret; ++} ++ ++static void hdmi_show_short_audio_desc(struct cea_sad *a) ++{ ++ char buf[SND_PRINT_RATES_ADVISED_BUFSIZE]; ++ char buf2[8 + SND_PRINT_BITS_ADVISED_BUFSIZE] = ", bits ="; ++ ++ if (!a->format) ++ return; ++ ++ snd_print_pcm_rates(a->rates, buf, sizeof(buf)); ++ ++ if (a->format == AUDIO_CODING_TYPE_LPCM) ++ snd_print_pcm_bits(a->sample_bits, buf2 + 8, sizeof(buf2 - 8)); ++ else if (a->max_bitrate) ++ snprintf(buf2, sizeof(buf2), ++ ", max bitrate = %d", a->max_bitrate); ++ else ++ buf2[0] = '\0'; ++ ++ printk(KERN_INFO "HDMI: supports coding type %s:" ++ " channels = %d, rates =%s%s\n", ++ cea_audio_coding_type_names[a->format], ++ a->channels, ++ buf, ++ buf2); ++} ++ ++void snd_print_channel_allocation(int spk_alloc, char *buf, int buflen) ++{ ++ int i, j; ++ ++ for (i = 0, j = 0; i < ARRAY_SIZE(cea_speaker_allocation_names); i++) { ++ if (spk_alloc & (1 << i)) ++ j += snprintf(buf + j, buflen - j, " %s", ++ cea_speaker_allocation_names[i]); ++ } ++ buf[j] = '\0'; /* necessary when j == 0 */ ++} ++ ++void snd_hdmi_show_eld(struct hdmi_eld *e) ++{ ++ int i; ++ ++ printk(KERN_INFO "HDMI: detected monitor %s at connection type %s\n", ++ e->monitor_name, ++ eld_connection_type_names[e->conn_type]); ++ ++ if (e->spk_alloc) { ++ char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE]; ++ snd_print_channel_allocation(e->spk_alloc, buf, sizeof(buf)); ++ printk(KERN_INFO "HDMI: available speakers:%s\n", buf); ++ } ++ ++ for (i = 0; i < e->sad_count; i++) ++ hdmi_show_short_audio_desc(e->sad + i); ++} ++ ++#ifdef CONFIG_PROC_FS ++ ++static void hdmi_print_sad_info(int i, struct cea_sad *a, ++ struct snd_info_buffer *buffer) ++{ ++ char buf[SND_PRINT_RATES_ADVISED_BUFSIZE]; ++ ++ snd_iprintf(buffer, "sad%d_coding_type\t[0x%x] %s\n", ++ i, a->format, cea_audio_coding_type_names[a->format]); ++ snd_iprintf(buffer, "sad%d_channels\t\t%d\n", i, a->channels); ++ ++ snd_print_pcm_rates(a->rates, buf, sizeof(buf)); ++ snd_iprintf(buffer, "sad%d_rates\t\t[0x%x]%s\n", i, a->rates, buf); ++ ++ if (a->format == AUDIO_CODING_TYPE_LPCM) { ++ snd_print_pcm_bits(a->sample_bits, buf, sizeof(buf)); ++ snd_iprintf(buffer, "sad%d_bits\t\t[0x%x]%s\n", ++ i, a->sample_bits, buf); ++ } ++ ++ if (a->max_bitrate) ++ snd_iprintf(buffer, "sad%d_max_bitrate\t%d\n", ++ i, a->max_bitrate); ++ ++ if (a->profile) ++ snd_iprintf(buffer, "sad%d_profile\t\t%d\n", i, a->profile); ++} ++ ++static void hdmi_print_eld_info(struct snd_info_entry *entry, ++ struct snd_info_buffer *buffer) ++{ ++ struct hdmi_eld *e = entry->private_data; ++ char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE]; ++ int i; ++ static char *eld_versoin_names[32] = { ++ "reserved", ++ "reserved", ++ "CEA-861D or below", ++ [3 ... 30] = "reserved", ++ [31] = "partial" ++ }; ++ static char *cea_edid_version_names[8] = { ++ "no CEA EDID Timing Extension block present", ++ "CEA-861", ++ "CEA-861-A", ++ "CEA-861-B, C or D", ++ [4 ... 7] = "reserved" ++ }; ++ ++ snd_iprintf(buffer, "monitor_name\t\t%s\n", e->monitor_name); ++ snd_iprintf(buffer, "connection_type\t\t%s\n", ++ eld_connection_type_names[e->conn_type]); ++ snd_iprintf(buffer, "eld_version\t\t[0x%x] %s\n", e->eld_ver, ++ eld_versoin_names[e->eld_ver]); ++ snd_iprintf(buffer, "edid_version\t\t[0x%x] %s\n", e->cea_edid_ver, ++ cea_edid_version_names[e->cea_edid_ver]); ++ snd_iprintf(buffer, "manufacture_id\t\t0x%x\n", e->manufacture_id); ++ snd_iprintf(buffer, "product_id\t\t0x%x\n", e->product_id); ++ snd_iprintf(buffer, "port_id\t\t\t0x%llx\n", (long long)e->port_id); ++ snd_iprintf(buffer, "support_hdcp\t\t%d\n", e->support_hdcp); ++ snd_iprintf(buffer, "support_ai\t\t%d\n", e->support_ai); ++ snd_iprintf(buffer, "audio_sync_delay\t%d\n", e->aud_synch_delay); ++ ++ snd_print_channel_allocation(e->spk_alloc, buf, sizeof(buf)); ++ snd_iprintf(buffer, "speakers\t\t[0x%x]%s\n", e->spk_alloc, buf); ++ ++ snd_iprintf(buffer, "sad_count\t\t%d\n", e->sad_count); ++ ++ for (i = 0; i < e->sad_count; i++) ++ hdmi_print_sad_info(i, e->sad + i, buffer); ++} ++ ++static void hdmi_write_eld_info(struct snd_info_entry *entry, ++ struct snd_info_buffer *buffer) ++{ ++ struct hdmi_eld *e = entry->private_data; ++ char line[64]; ++ char name[64]; ++ char *sname; ++ long long val; ++ int n; ++ ++ while (!snd_info_get_line(buffer, line, sizeof(line))) { ++ if (sscanf(line, "%s %llx", name, &val) != 2) ++ continue; ++ /* ++ * We don't allow modification to these fields: ++ * monitor_name manufacture_id product_id ++ * eld_version edid_version ++ */ ++ if (!strcmp(name, "connection_type")) ++ e->conn_type = val; ++ else if (!strcmp(name, "port_id")) ++ e->port_id = val; ++ else if (!strcmp(name, "support_hdcp")) ++ e->support_hdcp = val; ++ else if (!strcmp(name, "support_ai")) ++ e->support_ai = val; ++ else if (!strcmp(name, "audio_sync_delay")) ++ e->aud_synch_delay = val; ++ else if (!strcmp(name, "speakers")) ++ e->spk_alloc = val; ++ else if (!strcmp(name, "sad_count")) ++ e->sad_count = val; ++ else if (!strncmp(name, "sad", 3)) { ++ sname = name + 4; ++ n = name[3] - '0'; ++ if (name[4] >= '0' && name[4] <= '9') { ++ sname++; ++ n = 10 * n + name[4] - '0'; ++ } ++ if (n < 0 || n > 31) /* double the CEA limit */ ++ continue; ++ if (!strcmp(sname, "_coding_type")) ++ e->sad[n].format = val; ++ else if (!strcmp(sname, "_channels")) ++ e->sad[n].channels = val; ++ else if (!strcmp(sname, "_rates")) ++ e->sad[n].rates = val; ++ else if (!strcmp(sname, "_bits")) ++ e->sad[n].sample_bits = val; ++ else if (!strcmp(sname, "_max_bitrate")) ++ e->sad[n].max_bitrate = val; ++ else if (!strcmp(sname, "_profile")) ++ e->sad[n].profile = val; ++ if (n >= e->sad_count) ++ e->sad_count = n + 1; ++ } ++ } ++} ++ ++ ++int snd_hda_eld_proc_new(struct hda_codec *codec, struct hdmi_eld *eld) ++{ ++ char name[32]; ++ struct snd_info_entry *entry; ++ int err; ++ ++ snprintf(name, sizeof(name), "eld#%d", codec->addr); ++ err = snd_card_proc_new(codec->bus->card, name, &entry); ++ if (err < 0) ++ return err; ++ ++ snd_info_set_text_ops(entry, eld, hdmi_print_eld_info); ++ entry->c.text.write = hdmi_write_eld_info; ++ entry->mode |= S_IWUSR; ++ eld->proc_entry = entry; ++ ++ return 0; ++} ++ ++void snd_hda_eld_proc_free(struct hda_codec *codec, struct hdmi_eld *eld) ++{ ++#if 0 /* we don't support hwdep reconfig yet */ ++ if (!codec->bus->shutdown && eld->proc_entry) { ++ snd_device_free(codec->bus->card, eld->proc_entry); ++ eld->proc_entry = NULL; ++ } ++#endif ++} ++ ++#endif /* CONFIG_PROC_FS */ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/pci/hda/hda_intel.c linux-2.6.27.25-0.1.1/sound/pci/hda/hda_intel.c +--- linux-2.6.27.23-0.1.1/sound/pci/hda/hda_intel.c 2009-06-16 13:40:23.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/pci/hda/hda_intel.c 2009-07-24 10:24:24.000000000 +0100 +@@ -292,6 +292,8 @@ enum { + /* Define VIA HD Audio Device ID*/ + #define VIA_HDAC_DEVICE_ID 0x3288 + ++/* HD Audio class code */ ++#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 + + /* + */ +@@ -304,9 +306,6 @@ struct azx_dev { + unsigned int period_bytes; /* size of the period in bytes */ + unsigned int frags; /* number for period in the play buffer */ + unsigned int fifo_size; /* FIFO size */ +- unsigned int start_flag: 1; /* stream full start flag */ +- unsigned long start_jiffies; /* start + minimum jiffies */ +- unsigned long min_jiffies; /* minimum jiffies before position is valid */ + + void __iomem *sd_addr; /* stream descriptor pointer */ + +@@ -325,6 +324,7 @@ struct azx_dev { + unsigned int opened :1; + unsigned int running :1; + unsigned int irq_pending :1; ++ unsigned int irq_ignore :1; /* not used; just placeholder for compat */ + /* + * For VIA: + * A flag to ensure DMA position is 0 +@@ -333,6 +333,14 @@ struct azx_dev { + unsigned int insufficient :1; + }; + ++/* new stuff; moved here to keep bloody binary compatibility */ ++struct azx_dev_ext { ++ unsigned int start_flag: 1; /* stream full start flag */ ++ unsigned long start_jiffies; /* start + minimum jiffies */ ++ unsigned long min_jiffies; /* minimum jiffies before position is valid */ ++ ++}; ++ + /* CORB/RIRB */ + struct azx_rb { + u32 *buf; /* CORB/RIRB buffer +@@ -375,7 +383,6 @@ struct azx { + + /* HD codec */ + unsigned short codec_mask; +- int codec_probe_mask; /* copied from probe_mask option */ + struct hda_bus *bus; + + /* CORB/RIRB */ +@@ -405,6 +412,10 @@ struct azx { + + /* reboot notifier (for mysterious hangup problem at power-down) */ + struct notifier_block reboot_notifier; ++ ++ /* moved here for binary compatibility */ ++ struct azx_dev_ext *azx_dev_ext; ++ int codec_probe_mask; /* copied from probe_mask option */ + }; + + /* driver types */ +@@ -418,6 +429,7 @@ enum { + AZX_DRIVER_ULI, + AZX_DRIVER_NVIDIA, + AZX_DRIVER_TERA, ++ AZX_DRIVER_GENERIC, + AZX_NUM_DRIVERS, /* keep this as last entry */ + }; + +@@ -431,6 +443,7 @@ static char *driver_short_names[] __devi + [AZX_DRIVER_ULI] = "HDA ULI M5461", + [AZX_DRIVER_NVIDIA] = "HDA NVidia", + [AZX_DRIVER_TERA] = "HDA Teradici", ++ [AZX_DRIVER_GENERIC] = "HD-Audio Generic", + }; + + /* +@@ -616,10 +629,8 @@ static unsigned int azx_rirb_get_respons + chip->irq = -1; + pci_disable_msi(chip->pci); + chip->msi = 0; +- if (azx_acquire_irq(chip, 1) < 0) { +- bus->rirb_error = 1; ++ if (azx_acquire_irq(chip, 1) < 0) + return -1; +- } + goto again; + } + +@@ -639,12 +650,23 @@ static unsigned int azx_rirb_get_respons + return -1; + } + +- snd_printk(KERN_ERR "hda_intel: azx_get_response timeout (ERROR): " +- "last cmd=0x%08x\n", chip->last_cmd); +- spin_lock_irq(&chip->reg_lock); +- chip->rirb.cmds = 0; /* reset the index */ ++ /* a fatal communication error; need either to reset or to fallback ++ * to the single_cmd mode ++ */ + bus->rirb_error = 1; +- spin_unlock_irq(&chip->reg_lock); ++ if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { ++ bus->response_reset = 1; ++ return -1; /* give a chance to retry */ ++ } ++ ++ snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " ++ "switching to single_cmd mode: last cmd=0x%08x\n", ++ chip->last_cmd); ++ chip->single_cmd = 1; ++ bus->response_reset = 0; ++ /* re-initialize CORB/RIRB */ ++ azx_free_cmd_io(chip); ++ azx_init_cmd_io(chip); + return -1; + } + +@@ -658,12 +680,34 @@ static unsigned int azx_rirb_get_respons + * I left the codes, however, for debugging/testing purposes. + */ + ++/* receive a response */ ++static int azx_single_wait_for_response(struct azx *chip) ++{ ++ int timeout = 50; ++ ++ while (timeout--) { ++ /* check IRV busy bit */ ++ if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { ++ /* reuse rirb.res as the response return value */ ++ chip->rirb.res = azx_readl(chip, IR); ++ return 0; ++ } ++ udelay(1); ++ } ++ if (printk_ratelimit()) ++ snd_printd(SFX "get_response timeout: IRS=0x%x\n", ++ azx_readw(chip, IRS)); ++ chip->rirb.res = -1; ++ return -EIO; ++} ++ + /* send a command */ + static int azx_single_send_cmd(struct hda_bus *bus, u32 val) + { + struct azx *chip = bus->private_data; + int timeout = 50; + ++ bus->rirb_error = 0; + while (timeout--) { + /* check ICB busy bit */ + if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { +@@ -673,7 +717,7 @@ static int azx_single_send_cmd(struct hd + azx_writel(chip, IC, val); + azx_writew(chip, IRS, azx_readw(chip, IRS) | + ICH6_IRS_BUSY); +- return 0; ++ return azx_single_wait_for_response(chip); + } + udelay(1); + } +@@ -687,18 +731,7 @@ static int azx_single_send_cmd(struct hd + static unsigned int azx_single_get_response(struct hda_bus *bus) + { + struct azx *chip = bus->private_data; +- int timeout = 50; +- +- while (timeout--) { +- /* check IRV busy bit */ +- if (azx_readw(chip, IRS) & ICH6_IRS_VALID) +- return azx_readl(chip, IR); +- udelay(1); +- } +- if (printk_ratelimit()) +- snd_printd(SFX "get_response timeout: IRS=0x%x\n", +- azx_readw(chip, IRS)); +- return (unsigned int)-1; ++ return chip->rirb.res; + } + + /* +@@ -886,8 +919,7 @@ static void azx_init_chip(struct azx *ch + azx_int_enable(chip); + + /* initialize the codec command I/O */ +- if (!chip->single_cmd) +- azx_init_cmd_io(chip); ++ azx_init_cmd_io(chip); + + /* program the position buffer */ + azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); +@@ -1003,7 +1035,7 @@ static irqreturn_t azx_interrupt(int irq + /* clear rirb int */ + status = azx_readb(chip, RIRBSTS); + if (status & RIRB_INT_MASK) { +- if (!chip->single_cmd && (status & RIRB_INT_RESPONSE)) ++ if (status & RIRB_INT_RESPONSE) + azx_update_rirb(chip); + azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); + } +@@ -1215,6 +1247,23 @@ static int probe_codec(struct azx *chip, + + static void azx_stop_chip(struct azx *chip); + ++static void azx_bus_reset(struct hda_bus *bus) ++{ ++ struct azx *chip = bus->private_data; ++ int i; ++ ++ bus->in_reset = 1; ++ azx_stop_chip(chip); ++ azx_init_chip(chip); ++ if (chip->initialized) { ++ for (i = 0; i < AZX_MAX_PCMS; i++) ++ snd_pcm_suspend_all(chip->pcm[i]); ++ snd_hda_suspend(chip->bus); ++ snd_hda_resume(chip->bus); ++ } ++ bus->in_reset = 0; ++} ++ + /* + * Codec initialization + */ +@@ -1236,6 +1285,7 @@ static int __devinit azx_codec_create(st + bus_temp.pci = chip->pci; + bus_temp.ops.command = azx_send_cmd; + bus_temp.ops.get_response = azx_get_response; ++ bus_temp.ops.bus_reset = azx_bus_reset; + #ifdef CONFIG_SND_HDA_POWER_SAVE + bus_temp.ops.pm_notify = azx_power_notify; + #endif +@@ -1456,6 +1506,7 @@ static int azx_pcm_prepare(struct snd_pc + struct azx_pcm *apcm = snd_pcm_substream_chip(substream); + struct azx *chip = apcm->chip; + struct azx_dev *azx_dev = get_azx_dev(substream); ++ struct azx_dev_ext *azx_dev_ext; + struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; + struct snd_pcm_runtime *runtime = substream->runtime; + unsigned int bufsize, period_bytes, format_val; +@@ -1490,7 +1541,8 @@ static int azx_pcm_prepare(struct snd_pc + return err; + } + +- azx_dev->min_jiffies = (runtime->period_size * HZ) / ++ azx_dev_ext = &chip->azx_dev_ext[azx_dev->index]; ++ azx_dev_ext->min_jiffies = (runtime->period_size * HZ) / + (runtime->rate * 2); + azx_setup_controller(chip, azx_dev); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) +@@ -1507,6 +1559,7 @@ static int azx_pcm_trigger(struct snd_pc + struct azx_pcm *apcm = snd_pcm_substream_chip(substream); + struct azx *chip = apcm->chip; + struct azx_dev *azx_dev; ++ struct azx_dev_ext *azx_dev_ext; + struct snd_pcm_substream *s; + int rstart = 0, start, nsync = 0, sbits = 0; + int nwait, timeout; +@@ -1545,9 +1598,10 @@ static int azx_pcm_trigger(struct snd_pc + if (s->pcm->card != substream->pcm->card) + continue; + azx_dev = get_azx_dev(s); ++ azx_dev_ext = &chip->azx_dev_ext[azx_dev->index]; + if (rstart) { +- azx_dev->start_flag = 1; +- azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies; ++ azx_dev_ext->start_flag = 1; ++ azx_dev_ext->start_jiffies = jiffies + azx_dev_ext->min_jiffies; + } + if (start) + azx_stream_start(chip, azx_dev); +@@ -1697,11 +1751,12 @@ static snd_pcm_uframes_t azx_pcm_pointer + static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) + { + unsigned int pos; ++ struct azx_dev_ext *azx_dev_ext = &chip->azx_dev_ext[azx_dev->index]; + +- if (azx_dev->start_flag && +- time_before_eq(jiffies, azx_dev->start_jiffies)) ++ if (azx_dev_ext->start_flag && ++ time_before_eq(jiffies, azx_dev_ext->start_jiffies)) + return -1; /* bogus (too early) interrupt */ +- azx_dev->start_flag = 0; ++ azx_dev_ext->start_flag = 0; + + pos = azx_get_position(chip, azx_dev); + if (chip->position_fix == POS_FIX_AUTO) { +@@ -2001,7 +2056,7 @@ static int azx_suspend(struct pci_dev *p + for (i = 0; i < AZX_MAX_PCMS; i++) + snd_pcm_suspend_all(chip->pcm[i]); + if (chip->initialized) +- snd_hda_suspend(chip->bus, state); ++ snd_hda_suspend(chip->bus); + azx_stop_chip(chip); + if (chip->irq >= 0) { + free_irq(chip->irq, chip); +@@ -2103,6 +2158,7 @@ static int azx_free(struct azx *chip) + pci_release_regions(chip->pci); + pci_disable_device(chip->pci); + kfree(chip->azx_dev); ++ kfree(chip->azx_dev_ext); + kfree(chip); + + return 0; +@@ -2323,6 +2379,7 @@ static int __devinit azx_create(struct s + chip->playback_streams = ATIHDMI_NUM_PLAYBACK; + chip->capture_streams = ATIHDMI_NUM_CAPTURE; + break; ++ case AZX_DRIVER_GENERIC: + default: + chip->playback_streams = ICH6_NUM_PLAYBACK; + chip->capture_streams = ICH6_NUM_CAPTURE; +@@ -2334,7 +2391,9 @@ static int __devinit azx_create(struct s + chip->num_streams = chip->playback_streams + chip->capture_streams; + chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), + GFP_KERNEL); +- if (!chip->azx_dev) { ++ chip->azx_dev_ext = kcalloc(chip->num_streams, ++ sizeof(*chip->azx_dev_ext), GFP_KERNEL); ++ if (!chip->azx_dev || !chip->azx_dev_ext) { + snd_printk(KERN_ERR "cannot malloc azx_dev\n"); + goto errout; + } +@@ -2358,11 +2417,9 @@ static int __devinit azx_create(struct s + goto errout; + } + /* allocate CORB/RIRB */ +- if (!chip->single_cmd) { +- err = azx_alloc_cmd_io(chip); +- if (err < 0) +- goto errout; +- } ++ err = azx_alloc_cmd_io(chip); ++ if (err < 0) ++ goto errout; + + /* initialize streams */ + azx_init_stream(chip); +@@ -2534,12 +2591,17 @@ static struct pci_device_id azx_ids[] = + { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA }, + { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA }, + { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA }, +- { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA }, +- { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA }, +- { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA }, +- { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA }, ++ { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA }, ++ { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA }, ++ { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA }, ++ { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA }, + /* Teradici */ + { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA }, ++ /* AMD Generic, PCI class code and Vendor ID for HD Audio */ ++ { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), ++ .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, ++ .class_mask = 0xffffff, ++ .driver_data = AZX_DRIVER_GENERIC }, + { 0, } + }; + MODULE_DEVICE_TABLE(pci, azx_ids); +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/pci/hda/hda_local.h linux-2.6.27.25-0.1.1/sound/pci/hda/hda_local.h +--- linux-2.6.27.23-0.1.1/sound/pci/hda/hda_local.h 2009-06-16 13:54:10.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/pci/hda/hda_local.h 2009-07-24 10:24:24.000000000 +0100 +@@ -284,6 +284,12 @@ int snd_hda_codec_proc_new(struct hda_co + static inline int snd_hda_codec_proc_new(struct hda_codec *codec) { return 0; } + #endif + ++#define SND_PRINT_RATES_ADVISED_BUFSIZE 80 ++void snd_print_pcm_rates(int pcm, char *buf, int buflen); ++ ++#define SND_PRINT_BITS_ADVISED_BUFSIZE 16 ++void snd_print_pcm_bits(int pcm, char *buf, int buflen); ++ + /* + * Misc + */ +@@ -436,4 +442,66 @@ int snd_hda_check_amp_list_power(struct + #define get_amp_index(kc) (((kc)->private_value >> 19) & 0xf) + #define get_amp_offset(kc) (((kc)->private_value >> 23) & 0x3f) + ++/* ++ * CEA Short Audio Descriptor data ++ */ ++struct cea_sad { ++ int channels; ++ int format; /* (format == 0) indicates invalid SAD */ ++ int rates; ++ int sample_bits; /* for LPCM */ ++ int max_bitrate; /* for AC3...ATRAC */ ++ int profile; /* for WMAPRO */ ++}; ++ ++#define ELD_FIXED_BYTES 20 ++#define ELD_MAX_MNL 16 ++#define ELD_MAX_SAD 16 ++ ++/* ++ * ELD: EDID Like Data ++ */ ++struct hdmi_eld { ++ int eld_size; ++ int baseline_len; ++ int eld_ver; /* (eld_ver == 0) indicates invalid ELD */ ++ int cea_edid_ver; ++ char monitor_name[ELD_MAX_MNL + 1]; ++ int manufacture_id; ++ int product_id; ++ u64 port_id; ++ int support_hdcp; ++ int support_ai; ++ int conn_type; ++ int aud_synch_delay; ++ int spk_alloc; ++ int sad_count; ++ struct cea_sad sad[ELD_MAX_SAD]; ++#ifdef CONFIG_PROC_FS ++ struct snd_info_entry *proc_entry; ++#endif ++}; ++ ++int snd_hdmi_get_eld_size(struct hda_codec *codec, hda_nid_t nid); ++int snd_hdmi_get_eld(struct hdmi_eld *, struct hda_codec *, hda_nid_t); ++void snd_hdmi_show_eld(struct hdmi_eld *eld); ++ ++#ifdef CONFIG_PROC_FS ++int snd_hda_eld_proc_new(struct hda_codec *codec, struct hdmi_eld *eld); ++void snd_hda_eld_proc_free(struct hda_codec *codec, struct hdmi_eld *eld); ++#else ++static inline int snd_hda_eld_proc_new(struct hda_codec *codec, ++ struct hdmi_eld *eld) ++{ ++ return 0; ++} ++static inline void snd_hda_eld_proc_free(struct hda_codec *codec, ++ struct hdmi_eld *eld) ++{ ++} ++#endif ++ ++#define SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE 80 ++void snd_print_channel_allocation(int spk_alloc, char *buf, int buflen); ++ + #endif /* __SOUND_HDA_LOCAL_H */ +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/pci/hda/hda_patch.h linux-2.6.27.25-0.1.1/sound/pci/hda/hda_patch.h +--- linux-2.6.27.23-0.1.1/sound/pci/hda/hda_patch.h 2009-06-16 13:54:10.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/pci/hda/hda_patch.h 2009-07-24 10:24:24.000000000 +0100 +@@ -20,3 +20,5 @@ extern struct hda_codec_preset snd_hda_p + extern struct hda_codec_preset snd_hda_preset_via[]; + /* NVIDIA HDMI codecs */ + extern struct hda_codec_preset snd_hda_preset_nvhdmi[]; ++/* Intel HDMI codecs */ ++extern struct hda_codec_preset snd_hda_preset_intelhdmi[]; +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/pci/hda/hda_proc.c linux-2.6.27.25-0.1.1/sound/pci/hda/hda_proc.c +--- linux-2.6.27.23-0.1.1/sound/pci/hda/hda_proc.c 2009-06-16 13:54:10.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/pci/hda/hda_proc.c 2009-07-24 10:24:24.000000000 +0100 +@@ -91,31 +91,21 @@ static void print_amp_vals(struct snd_in + + static void print_pcm_rates(struct snd_info_buffer *buffer, unsigned int pcm) + { +- static unsigned int rates[] = { +- 8000, 11025, 16000, 22050, 32000, 44100, 48000, 88200, +- 96000, 176400, 192000, 384000 +- }; +- int i; ++ char buf[SND_PRINT_RATES_ADVISED_BUFSIZE]; + + pcm &= AC_SUPPCM_RATES; + snd_iprintf(buffer, " rates [0x%x]:", pcm); +- for (i = 0; i < ARRAY_SIZE(rates); i++) +- if (pcm & (1 << i)) +- snd_iprintf(buffer, " %d", rates[i]); +- snd_iprintf(buffer, "\n"); ++ snd_print_pcm_rates(pcm, buf, sizeof(buf)); ++ snd_iprintf(buffer, "%s\n", buf); + } + + static void print_pcm_bits(struct snd_info_buffer *buffer, unsigned int pcm) + { +- static unsigned int bits[] = { 8, 16, 20, 24, 32 }; +- int i; ++ char buf[SND_PRINT_BITS_ADVISED_BUFSIZE]; + +- pcm = (pcm >> 16) & 0xff; +- snd_iprintf(buffer, " bits [0x%x]:", pcm); +- for (i = 0; i < ARRAY_SIZE(bits); i++) +- if (pcm & (1 << i)) +- snd_iprintf(buffer, " %d", bits[i]); +- snd_iprintf(buffer, "\n"); ++ snd_iprintf(buffer, " bits [0x%x]:", (pcm >> 16) & 0xff); ++ snd_print_pcm_bits(pcm, buf, sizeof(buf)); ++ snd_iprintf(buffer, "%s\n", buf); + } + + static void print_pcm_formats(struct snd_info_buffer *buffer, +@@ -145,32 +135,6 @@ static void print_pcm_caps(struct snd_in + print_pcm_formats(buffer, stream); + } + +-static const char *get_jack_location(u32 cfg) +-{ +- static char *bases[7] = { +- "N/A", "Rear", "Front", "Left", "Right", "Top", "Bottom", +- }; +- static unsigned char specials_idx[] = { +- 0x07, 0x08, +- 0x17, 0x18, 0x19, +- 0x37, 0x38 +- }; +- static char *specials[] = { +- "Rear Panel", "Drive Bar", +- "Riser", "HDMI", "ATAPI", +- "Mobile-In", "Mobile-Out" +- }; +- int i; +- cfg = (cfg & AC_DEFCFG_LOCATION) >> AC_DEFCFG_LOCATION_SHIFT; +- if ((cfg & 0x0f) < 7) +- return bases[cfg & 0x0f]; +- for (i = 0; i < ARRAY_SIZE(specials_idx); i++) { +- if (cfg == specials_idx[i]) +- return specials[i]; +- } +- return "UNKNOWN"; +-} +- + static const char *get_jack_connection(u32 cfg) + { + static char *names[16] = { +@@ -206,13 +170,6 @@ static void print_pin_caps(struct snd_in + int *supports_vref) + { + static char *jack_conns[4] = { "Jack", "N/A", "Fixed", "Both" }; +- static char *jack_types[16] = { +- "Line Out", "Speaker", "HP Out", "CD", +- "SPDIF Out", "Digital Out", "Modem Line", "Modem Hand", +- "Line In", "Aux", "Mic", "Telephony", +- "SPDIF In", "Digitial In", "Reserved", "Other" +- }; +- static char *jack_locations[4] = { "Ext", "Int", "Sep", "Oth" }; + unsigned int caps, val; + + caps = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP); +@@ -236,8 +193,6 @@ static void print_pin_caps(struct snd_in + else + snd_iprintf(buffer, " HDMI"); + } +- if (caps & AC_PINCAP_LR_SWAP) +- snd_iprintf(buffer, " R/L"); + if (caps & AC_PINCAP_TRIG_REQ) + snd_iprintf(buffer, " Trigger"); + if (caps & AC_PINCAP_IMP_SENSE) +@@ -276,9 +231,9 @@ static void print_pin_caps(struct snd_in + caps = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONFIG_DEFAULT, 0); + snd_iprintf(buffer, " Pin Default 0x%08x: [%s] %s at %s %s\n", caps, + jack_conns[(caps & AC_DEFCFG_PORT_CONN) >> AC_DEFCFG_PORT_CONN_SHIFT], +- jack_types[(caps & AC_DEFCFG_DEVICE) >> AC_DEFCFG_DEVICE_SHIFT], +- jack_locations[(caps >> (AC_DEFCFG_LOCATION_SHIFT + 4)) & 3], +- get_jack_location(caps)); ++ snd_hda_get_jack_type(caps), ++ snd_hda_get_jack_connectivity(caps), ++ snd_hda_get_jack_location(caps)); + snd_iprintf(buffer, " Conn = %s, Color = %s\n", + get_jack_connection(caps), + get_jack_color(caps)); +@@ -444,7 +399,10 @@ static void print_conn_list(struct snd_i + { + int c, curr = -1; + +- if (conn_len > 1 && wid_type != AC_WID_AUD_MIX) ++ if (conn_len > 1 && ++ wid_type != AC_WID_AUD_MIX && ++ wid_type != AC_WID_VOL_KNB && ++ wid_type != AC_WID_POWER) + curr = snd_hda_codec_read(codec, nid, 0, + AC_VERB_GET_CONNECT_SEL, 0); + snd_iprintf(buffer, " Connection: %d\n", conn_len); +@@ -502,12 +460,13 @@ static void print_gpio(struct snd_info_b + for (i = 0; i < max; ++i) + snd_iprintf(buffer, + " IO[%d]: enable=%d, dir=%d, wake=%d, " +- "sticky=%d, data=%d\n", i, ++ "sticky=%d, data=%d, unsol=%d\n", i, + (enable & (1< ++ * Wu Fengguang ++ * ++ * Maintained by: ++ * Wu Fengguang ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at your option) ++ * any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software Foundation, ++ * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include "hda_codec.h" ++#include "hda_local.h" ++#include "hda_patch.h" ++ ++#define CVT_NID 0x02 /* audio converter */ ++#define PIN_NID 0x03 /* HDMI output pin */ ++ ++#define INTEL_HDMI_EVENT_TAG 0x08 ++ ++struct intel_hdmi_spec { ++ struct hda_multi_out multiout; ++ struct hda_pcm pcm_rec; ++ struct hdmi_eld sink_eld; ++}; ++ ++static struct hda_verb pinout_enable_verb[] = { ++ {PIN_NID, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT}, ++ {} /* terminator */ ++}; ++ ++static struct hda_verb unsolicited_response_verb[] = { ++ {PIN_NID, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | ++ INTEL_HDMI_EVENT_TAG}, ++ {} ++}; ++ ++static struct hda_verb def_chan_map[] = { ++ {CVT_NID, AC_VERB_SET_HDMI_CHAN_SLOT, 0x00}, ++ {CVT_NID, AC_VERB_SET_HDMI_CHAN_SLOT, 0x11}, ++ {CVT_NID, AC_VERB_SET_HDMI_CHAN_SLOT, 0x22}, ++ {CVT_NID, AC_VERB_SET_HDMI_CHAN_SLOT, 0x33}, ++ {CVT_NID, AC_VERB_SET_HDMI_CHAN_SLOT, 0x44}, ++ {CVT_NID, AC_VERB_SET_HDMI_CHAN_SLOT, 0x55}, ++ {CVT_NID, AC_VERB_SET_HDMI_CHAN_SLOT, 0x66}, ++ {CVT_NID, AC_VERB_SET_HDMI_CHAN_SLOT, 0x77}, ++ {} ++}; ++ ++ ++struct hdmi_audio_infoframe { ++ u8 type; /* 0x84 */ ++ u8 ver; /* 0x01 */ ++ u8 len; /* 0x0a */ ++ ++ u8 checksum; /* PB0 */ ++ u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ ++ u8 SS01_SF24; ++ u8 CXT04; ++ u8 CA; ++ u8 LFEPBL01_LSV36_DM_INH7; ++ u8 reserved[5]; /* PB6 - PB10 */ ++}; ++ ++/* ++ * CEA speaker placement: ++ * ++ * FLH FCH FRH ++ * FLW FL FLC FC FRC FR FRW ++ * ++ * LFE ++ * TC ++ * ++ * RL RLC RC RRC RR ++ * ++ * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to ++ * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC. ++ */ ++enum cea_speaker_placement { ++ FL = (1 << 0), /* Front Left */ ++ FC = (1 << 1), /* Front Center */ ++ FR = (1 << 2), /* Front Right */ ++ FLC = (1 << 3), /* Front Left Center */ ++ FRC = (1 << 4), /* Front Right Center */ ++ RL = (1 << 5), /* Rear Left */ ++ RC = (1 << 6), /* Rear Center */ ++ RR = (1 << 7), /* Rear Right */ ++ RLC = (1 << 8), /* Rear Left Center */ ++ RRC = (1 << 9), /* Rear Right Center */ ++ LFE = (1 << 10), /* Low Frequency Effect */ ++ FLW = (1 << 11), /* Front Left Wide */ ++ FRW = (1 << 12), /* Front Right Wide */ ++ FLH = (1 << 13), /* Front Left High */ ++ FCH = (1 << 14), /* Front Center High */ ++ FRH = (1 << 15), /* Front Right High */ ++ TC = (1 << 16), /* Top Center */ ++}; ++ ++/* ++ * ELD SA bits in the CEA Speaker Allocation data block ++ */ ++static int eld_speaker_allocation_bits[] = { ++ [0] = FL | FR, ++ [1] = LFE, ++ [2] = FC, ++ [3] = RL | RR, ++ [4] = RC, ++ [5] = FLC | FRC, ++ [6] = RLC | RRC, ++ /* the following are not defined in ELD yet */ ++ [7] = FLW | FRW, ++ [8] = FLH | FRH, ++ [9] = TC, ++ [10] = FCH, ++}; ++ ++struct cea_channel_speaker_allocation { ++ int ca_index; ++ int speakers[8]; ++ ++ /* derived values, just for convenience */ ++ int channels; ++ int spk_mask; ++}; ++ ++/* ++ * This is an ordered list! ++ * ++ * The preceding ones have better chances to be selected by ++ * hdmi_setup_channel_allocation(). ++ */ ++static struct cea_channel_speaker_allocation channel_allocations[] = { ++/* channel: 8 7 6 5 4 3 2 1 */ ++{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, ++ /* 2.1 */ ++{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, ++ /* Dolby Surround */ ++{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, ++{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, ++{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, ++{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, ++{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, ++{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, ++{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, ++{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, ++{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, ++ /* 5.1 */ ++{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, ++{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, ++{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, ++{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, ++ /* 6.1 */ ++{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, ++{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, ++{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, ++{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, ++ /* 7.1 */ ++{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, ++{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, ++{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, ++{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, ++{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, ++{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, ++{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, ++{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, ++{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, ++{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, ++{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, ++{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, ++{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, ++{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } }, ++{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } }, ++{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } }, ++{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } }, ++{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } }, ++{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } }, ++{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } }, ++{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } }, ++{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } }, ++{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } }, ++{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } }, ++{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } }, ++{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } }, ++{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } }, ++{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } }, ++{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } }, ++{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } }, ++{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } }, ++}; ++ ++/* ++ * HDMI routines ++ */ ++ ++#ifdef BE_PARANOID ++static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t nid, ++ int *packet_index, int *byte_index) ++{ ++ int val; ++ ++ val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_HDMI_DIP_INDEX, 0); ++ ++ *packet_index = val >> 5; ++ *byte_index = val & 0x1f; ++} ++#endif ++ ++static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t nid, ++ int packet_index, int byte_index) ++{ ++ int val; ++ ++ val = (packet_index << 5) | (byte_index & 0x1f); ++ ++ snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); ++} ++ ++static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t nid, ++ unsigned char val) ++{ ++ snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); ++} ++ ++static void hdmi_enable_output(struct hda_codec *codec) ++{ ++ /* Unmute */ ++ if (get_wcaps(codec, PIN_NID) & AC_WCAP_OUT_AMP) ++ snd_hda_codec_write(codec, PIN_NID, 0, ++ AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); ++ /* Enable pin out */ ++ snd_hda_sequence_write(codec, pinout_enable_verb); ++} ++ ++/* ++ * Enable Audio InfoFrame Transmission ++ */ ++static void hdmi_start_infoframe_trans(struct hda_codec *codec) ++{ ++ hdmi_set_dip_index(codec, PIN_NID, 0x0, 0x0); ++ snd_hda_codec_write(codec, PIN_NID, 0, AC_VERB_SET_HDMI_DIP_XMIT, ++ AC_DIPXMIT_BEST); ++} ++ ++/* ++ * Disable Audio InfoFrame Transmission ++ */ ++static void hdmi_stop_infoframe_trans(struct hda_codec *codec) ++{ ++ hdmi_set_dip_index(codec, PIN_NID, 0x0, 0x0); ++ snd_hda_codec_write(codec, PIN_NID, 0, AC_VERB_SET_HDMI_DIP_XMIT, ++ AC_DIPXMIT_DISABLE); ++} ++ ++static int hdmi_get_channel_count(struct hda_codec *codec) ++{ ++ return 1 + snd_hda_codec_read(codec, CVT_NID, 0, ++ AC_VERB_GET_CVT_CHAN_COUNT, 0); ++} ++ ++static void hdmi_set_channel_count(struct hda_codec *codec, int chs) ++{ ++ snd_hda_codec_write(codec, CVT_NID, 0, ++ AC_VERB_SET_CVT_CHAN_COUNT, chs - 1); ++ ++ if (chs != hdmi_get_channel_count(codec)) ++ snd_printd(KERN_INFO "HDMI channel count: expect %d, get %d\n", ++ chs, hdmi_get_channel_count(codec)); ++} ++ ++static void hdmi_debug_channel_mapping(struct hda_codec *codec) ++{ ++#ifdef CONFIG_SND_DEBUG_VERBOSE ++ int i; ++ int slot; ++ ++ for (i = 0; i < 8; i++) { ++ slot = snd_hda_codec_read(codec, CVT_NID, 0, ++ AC_VERB_GET_HDMI_CHAN_SLOT, i); ++ printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n", ++ slot >> 4, slot & 0x7); ++ } ++#endif ++} ++ ++static void hdmi_parse_eld(struct hda_codec *codec) ++{ ++ struct intel_hdmi_spec *spec = codec->spec; ++ struct hdmi_eld *eld = &spec->sink_eld; ++ ++ if (!snd_hdmi_get_eld(eld, codec, PIN_NID)) ++ snd_hdmi_show_eld(eld); ++} ++ ++ ++/* ++ * Audio InfoFrame routines ++ */ ++ ++static void hdmi_debug_dip_size(struct hda_codec *codec) ++{ ++#ifdef CONFIG_SND_DEBUG_VERBOSE ++ int i; ++ int size; ++ ++ size = snd_hdmi_get_eld_size(codec, PIN_NID); ++ printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size); ++ ++ for (i = 0; i < 8; i++) { ++ size = snd_hda_codec_read(codec, PIN_NID, 0, ++ AC_VERB_GET_HDMI_DIP_SIZE, i); ++ printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size); ++ } ++#endif ++} ++ ++static void hdmi_clear_dip_buffers(struct hda_codec *codec) ++{ ++#ifdef BE_PARANOID ++ int i, j; ++ int size; ++ int pi, bi; ++ for (i = 0; i < 8; i++) { ++ size = snd_hda_codec_read(codec, PIN_NID, 0, ++ AC_VERB_GET_HDMI_DIP_SIZE, i); ++ if (size == 0) ++ continue; ++ ++ hdmi_set_dip_index(codec, PIN_NID, i, 0x0); ++ for (j = 1; j < 1000; j++) { ++ hdmi_write_dip_byte(codec, PIN_NID, 0x0); ++ hdmi_get_dip_index(codec, PIN_NID, &pi, &bi); ++ if (pi != i) ++ snd_printd(KERN_INFO "dip index %d: %d != %d\n", ++ bi, pi, i); ++ if (bi == 0) /* byte index wrapped around */ ++ break; ++ } ++ snd_printd(KERN_INFO ++ "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", ++ i, size, j); ++ } ++#endif ++} ++ ++static void hdmi_fill_audio_infoframe(struct hda_codec *codec, ++ struct hdmi_audio_infoframe *ai) ++{ ++ u8 *params = (u8 *)ai; ++ u8 sum = 0; ++ int i; ++ ++ hdmi_debug_dip_size(codec); ++ hdmi_clear_dip_buffers(codec); /* be paranoid */ ++ ++ for (i = 0; i < sizeof(ai); i++) ++ sum += params[i]; ++ ai->checksum = - sum; ++ ++ hdmi_set_dip_index(codec, PIN_NID, 0x0, 0x0); ++ for (i = 0; i < sizeof(ai); i++) ++ hdmi_write_dip_byte(codec, PIN_NID, params[i]); ++} ++ ++/* ++ * Compute derived values in channel_allocations[]. ++ */ ++static void init_channel_allocations(void) ++{ ++ int i, j; ++ struct cea_channel_speaker_allocation *p; ++ ++ for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { ++ p = channel_allocations + i; ++ p->channels = 0; ++ p->spk_mask = 0; ++ for (j = 0; j < ARRAY_SIZE(p->speakers); j++) ++ if (p->speakers[j]) { ++ p->channels++; ++ p->spk_mask |= p->speakers[j]; ++ } ++ } ++} ++ ++/* ++ * The transformation takes two steps: ++ * ++ * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask ++ * spk_mask => (channel_allocations[]) => ai->CA ++ * ++ * TODO: it could select the wrong CA from multiple candidates. ++*/ ++static int hdmi_setup_channel_allocation(struct hda_codec *codec, ++ struct hdmi_audio_infoframe *ai) ++{ ++ struct intel_hdmi_spec *spec = codec->spec; ++ struct hdmi_eld *eld = &spec->sink_eld; ++ int i; ++ int spk_mask = 0; ++ int channels = 1 + (ai->CC02_CT47 & 0x7); ++ char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE]; ++ ++ /* ++ * CA defaults to 0 for basic stereo audio ++ */ ++ if (channels <= 2) ++ return 0; ++ ++ /* ++ * HDMI sink's ELD info cannot always be retrieved for now, e.g. ++ * in console or for audio devices. Assume the highest speakers ++ * configuration, to _not_ prohibit multi-channel audio playback. ++ */ ++ if (!eld->spk_alloc) ++ eld->spk_alloc = 0xffff; ++ ++ /* ++ * expand ELD's speaker allocation mask ++ * ++ * ELD tells the speaker mask in a compact(paired) form, ++ * expand ELD's notions to match the ones used by Audio InfoFrame. ++ */ ++ for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { ++ if (eld->spk_alloc & (1 << i)) ++ spk_mask |= eld_speaker_allocation_bits[i]; ++ } ++ ++ /* search for the first working match in the CA table */ ++ for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { ++ if (channels == channel_allocations[i].channels && ++ (spk_mask & channel_allocations[i].spk_mask) == ++ channel_allocations[i].spk_mask) { ++ ai->CA = channel_allocations[i].ca_index; ++ break; ++ } ++ } ++ ++ snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf)); ++ snd_printdd(KERN_INFO ++ "HDMI: select CA 0x%x for %d-channel allocation: %s\n", ++ ai->CA, channels, buf); ++ ++ return ai->CA; ++} ++ ++static void hdmi_setup_channel_mapping(struct hda_codec *codec, ++ struct hdmi_audio_infoframe *ai) ++{ ++ if (!ai->CA) ++ return; ++ ++ /* ++ * TODO: adjust channel mapping if necessary ++ * ALSA sequence is front/surr/clfe/side? ++ */ ++ ++ snd_hda_sequence_write(codec, def_chan_map); ++ hdmi_debug_channel_mapping(codec); ++} ++ ++ ++static void hdmi_setup_audio_infoframe(struct hda_codec *codec, ++ struct snd_pcm_substream *substream) ++{ ++ struct hdmi_audio_infoframe ai = { ++ .type = 0x84, ++ .ver = 0x01, ++ .len = 0x0a, ++ .CC02_CT47 = substream->runtime->channels - 1, ++ }; ++ ++ hdmi_setup_channel_allocation(codec, &ai); ++ hdmi_setup_channel_mapping(codec, &ai); ++ ++ hdmi_fill_audio_infoframe(codec, &ai); ++ hdmi_start_infoframe_trans(codec); ++} ++ ++ ++/* ++ * Unsolicited events ++ */ ++ ++static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) ++{ ++ int pind = !!(res & AC_UNSOL_RES_PD); ++ int eldv = !!(res & AC_UNSOL_RES_ELDV); ++ ++ printk(KERN_INFO ++ "HDMI hot plug event: Presence_Detect=%d ELD_Valid=%d\n", ++ pind, eldv); ++ ++ if (pind && eldv) { ++ hdmi_parse_eld(codec); ++ /* TODO: do real things about ELD */ ++ } ++} ++ ++static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) ++{ ++ int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; ++ int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); ++ int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); ++ ++ printk(KERN_INFO ++ "HDMI content protection event: SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", ++ subtag, ++ cp_state, ++ cp_ready); ++ ++ /* TODO */ ++ if (cp_state) ++ ; ++ if (cp_ready) ++ ; ++} ++ ++ ++static void intel_hdmi_unsol_event(struct hda_codec *codec, unsigned int res) ++{ ++ int tag = res >> AC_UNSOL_RES_TAG_SHIFT; ++ int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; ++ ++ if (tag != INTEL_HDMI_EVENT_TAG) { ++ snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag); ++ return; ++ } ++ ++ if (subtag == 0) ++ hdmi_intrinsic_event(codec, res); ++ else ++ hdmi_non_intrinsic_event(codec, res); ++} ++ ++/* ++ * Callbacks ++ */ ++ ++static int intel_hdmi_playback_pcm_open(struct hda_pcm_stream *hinfo, ++ struct hda_codec *codec, ++ struct snd_pcm_substream *substream) ++{ ++ struct intel_hdmi_spec *spec = codec->spec; ++ ++ return snd_hda_multi_out_dig_open(codec, &spec->multiout); ++} ++ ++static int intel_hdmi_playback_pcm_close(struct hda_pcm_stream *hinfo, ++ struct hda_codec *codec, ++ struct snd_pcm_substream *substream) ++{ ++ struct intel_hdmi_spec *spec = codec->spec; ++ ++ hdmi_stop_infoframe_trans(codec); ++ ++ return snd_hda_multi_out_dig_close(codec, &spec->multiout); ++} ++ ++static int intel_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, ++ struct hda_codec *codec, ++ unsigned int stream_tag, ++ unsigned int format, ++ struct snd_pcm_substream *substream) ++{ ++ struct intel_hdmi_spec *spec = codec->spec; ++ ++ snd_hda_multi_out_dig_prepare(codec, &spec->multiout, stream_tag, ++ format, substream); ++ ++ hdmi_set_channel_count(codec, substream->runtime->channels); ++ ++ hdmi_setup_audio_infoframe(codec, substream); ++ ++ return 0; ++} ++ ++static struct hda_pcm_stream intel_hdmi_pcm_playback = { ++ .substreams = 1, ++ .channels_min = 2, ++ .channels_max = 8, ++ .nid = CVT_NID, /* NID to query formats and rates and setup streams */ ++ .ops = { ++ .open = intel_hdmi_playback_pcm_open, ++ .close = intel_hdmi_playback_pcm_close, ++ .prepare = intel_hdmi_playback_pcm_prepare ++ }, ++}; ++ ++static int intel_hdmi_build_pcms(struct hda_codec *codec) ++{ ++ struct intel_hdmi_spec *spec = codec->spec; ++ struct hda_pcm *info = &spec->pcm_rec; ++ ++ codec->num_pcms = 1; ++ codec->pcm_info = info; ++ ++ info->name = "INTEL HDMI"; ++ info->pcm_type = HDA_PCM_TYPE_HDMI; ++ info->stream[SNDRV_PCM_STREAM_PLAYBACK] = intel_hdmi_pcm_playback; ++ ++ return 0; ++} ++ ++static int intel_hdmi_build_controls(struct hda_codec *codec) ++{ ++ struct intel_hdmi_spec *spec = codec->spec; ++ int err; ++ ++ err = snd_hda_create_spdif_out_ctls(codec, spec->multiout.dig_out_nid); ++ if (err < 0) ++ return err; ++ ++ return 0; ++} ++ ++static int intel_hdmi_init(struct hda_codec *codec) ++{ ++ hdmi_enable_output(codec); ++ ++ snd_hda_sequence_write(codec, unsolicited_response_verb); ++ ++ return 0; ++} ++ ++static void intel_hdmi_free(struct hda_codec *codec) ++{ ++ struct intel_hdmi_spec *spec = codec->spec; ++ ++ snd_hda_eld_proc_free(codec, &spec->sink_eld); ++ kfree(spec); ++} ++ ++static struct hda_codec_ops intel_hdmi_patch_ops = { ++ .init = intel_hdmi_init, ++ .free = intel_hdmi_free, ++ .build_pcms = intel_hdmi_build_pcms, ++ .build_controls = intel_hdmi_build_controls, ++ .unsol_event = intel_hdmi_unsol_event, ++}; ++ ++static int patch_intel_hdmi(struct hda_codec *codec) ++{ ++ struct intel_hdmi_spec *spec; ++ ++ spec = kzalloc(sizeof(*spec), GFP_KERNEL); ++ if (spec == NULL) ++ return -ENOMEM; ++ ++ spec->multiout.num_dacs = 0; /* no analog */ ++ spec->multiout.max_channels = 8; ++ spec->multiout.dig_out_nid = CVT_NID; ++ ++ codec->spec = spec; ++ codec->patch_ops = intel_hdmi_patch_ops; ++ ++ snd_hda_eld_proc_new(codec, &spec->sink_eld); ++ ++ init_channel_allocations(); ++ ++ return 0; ++} ++ ++/* ++ * patch entries ++ */ ++struct hda_codec_preset snd_hda_preset_intelhdmi[] = { ++ { .id = 0x808629fb, .name = "G45 DEVCL", .patch = patch_intel_hdmi }, ++ { .id = 0x80862801, .name = "G45 DEVBLC", .patch = patch_intel_hdmi }, ++ { .id = 0x80862802, .name = "G45 DEVCTG", .patch = patch_intel_hdmi }, ++ { .id = 0x80862803, .name = "G45 DEVELK", .patch = patch_intel_hdmi }, ++ { .id = 0x80862804, .name = "G45 DEVIBX", .patch = patch_intel_hdmi }, ++ { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_intel_hdmi }, ++ {} /* terminator */ ++}; +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/pci/hda/patch_nvhdmi.c linux-2.6.27.25-0.1.1/sound/pci/hda/patch_nvhdmi.c +--- linux-2.6.27.23-0.1.1/sound/pci/hda/patch_nvhdmi.c 2009-06-16 13:54:10.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/pci/hda/patch_nvhdmi.c 2009-07-24 10:24:24.000000000 +0100 +@@ -159,7 +159,10 @@ static int patch_nvhdmi(struct hda_codec + * patch entries + */ + struct hda_codec_preset snd_hda_preset_nvhdmi[] = { +- { .id = 0x10de0002, .name = "NVIDIA MCP78 HDMI", .patch = patch_nvhdmi }, +- { .id = 0x10de0007, .name = "NVIDIA MCP7A HDMI", .patch = patch_nvhdmi }, ++ { .id = 0x10de0002, .name = "MCP78 HDMI", .patch = patch_nvhdmi }, ++ { .id = 0x10de0006, .name = "MCP78 HDMI", .patch = patch_nvhdmi }, ++ { .id = 0x10de0007, .name = "MCP7A HDMI", .patch = patch_nvhdmi }, ++ { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi }, ++ { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi }, + {} /* terminator */ + }; +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/pci/hda/patch_realtek.c linux-2.6.27.25-0.1.1/sound/pci/hda/patch_realtek.c +--- linux-2.6.27.23-0.1.1/sound/pci/hda/patch_realtek.c 2009-06-16 13:40:23.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/pci/hda/patch_realtek.c 2009-07-24 10:24:24.000000000 +0100 +@@ -11990,7 +11990,6 @@ static struct snd_kcontrol_new alc269_qu + }, + HDA_CODEC_VOLUME("Mic Playback Volume", 0x0b, 0x0, HDA_INPUT), + HDA_CODEC_MUTE("Mic Playback Switch", 0x0b, 0x0, HDA_INPUT), +- HDA_CODEC_VOLUME("Mic Boost", 0x18, 0, HDA_INPUT), + HDA_CODEC_VOLUME("Internal Mic Playback Volume", 0x0b, 0x01, HDA_INPUT), + HDA_CODEC_MUTE("Internal Mic Playback Switch", 0x0b, 0x01, HDA_INPUT), + HDA_CODEC_VOLUME("Internal Mic Boost", 0x19, 0, HDA_INPUT), +@@ -12519,7 +12518,7 @@ static struct alc_config_preset alc269_p + .input_mux = &alc269_capture_source, + }, + [ALC269_QUANTA_FL1] = { +- .mixers = { alc269_quanta_fl1_mixer }, ++ .mixers = { alc269_quanta_fl1_mixer, alc269_epc_capture_mixer }, + .init_verbs = { alc269_init_verbs, alc269_quanta_fl1_verbs }, + .num_dacs = ARRAY_SIZE(alc269_dac_nids), + .dac_nids = alc269_dac_nids, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/pci/hda/patch_sigmatel.c linux-2.6.27.25-0.1.1/sound/pci/hda/patch_sigmatel.c +--- linux-2.6.27.23-0.1.1/sound/pci/hda/patch_sigmatel.c 2009-06-16 13:40:23.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/pci/hda/patch_sigmatel.c 2009-07-24 10:24:24.000000000 +0100 +@@ -4804,6 +4804,15 @@ again: + codec->slave_dig_outs = stac92hd71bxx_slave_dig_outs; + } + ++ /* Some HP machines seem to have unstable codec communications ++ * especially with ATI fglrx driver. For recovering from the ++ * CORB/RIRB stall, allow the BUS reset and keep always sync ++ */ ++ if (spec->board_config == STAC_HP_DV5) { ++ codec->bus->sync_write = 1; ++ codec->bus->allow_bus_reset = 1; ++ } ++ + spec->aloopback_mask = 0x50; + spec->aloopback_shift = 0; + +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/pci/Kconfig linux-2.6.27.25-0.1.1/sound/pci/Kconfig +--- linux-2.6.27.23-0.1.1/sound/pci/Kconfig 2009-06-16 13:54:10.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/pci/Kconfig 2009-07-24 10:24:24.000000000 +0100 +@@ -573,6 +573,18 @@ config SND_HDA_CODEC_NVHDMI + Say Y here to include NVIDIA HDMI HD-audio codec support in + snd-hda-intel driver, such as NVIDIA MCP78 HDMI. + ++config SND_HDA_CODEC_INTELHDMI ++ bool "Build INTEL HDMI HD-audio codec support" ++ depends on SND_HDA_INTEL ++ default y ++ help ++ Say Y here to include INTEL HDMI HD-audio codec support in ++ snd-hda-intel driver, such as Eaglelake integrated HDMI. ++ ++config SND_HDA_ELD ++ def_bool y ++ depends on SND_HDA_CODEC_INTELHDMI ++ + config SND_HDA_CODEC_CONEXANT + bool "Build Conexant HD-audio codec support" + depends on SND_HDA_INTEL +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/usb/usbaudio.c linux-2.6.27.25-0.1.1/sound/usb/usbaudio.c +--- linux-2.6.27.23-0.1.1/sound/usb/usbaudio.c 2009-06-16 13:40:23.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/usb/usbaudio.c 2009-07-24 10:24:24.000000000 +0100 +@@ -3367,7 +3367,7 @@ static int snd_usb_create_quirk(struct s + [QUIRK_MIDI_YAMAHA] = snd_usb_create_midi_interface, + [QUIRK_MIDI_MIDIMAN] = snd_usb_create_midi_interface, + [QUIRK_MIDI_NOVATION] = snd_usb_create_midi_interface, +- [QUIRK_MIDI_RAW] = snd_usb_create_midi_interface, ++ [QUIRK_MIDI_FASTLANE] = snd_usb_create_midi_interface, + [QUIRK_MIDI_EMAGIC] = snd_usb_create_midi_interface, + [QUIRK_MIDI_CME] = snd_usb_create_midi_interface, + [QUIRK_AUDIO_STANDARD_INTERFACE] = create_standard_audio_quirk, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/usb/usbaudio.h linux-2.6.27.25-0.1.1/sound/usb/usbaudio.h +--- linux-2.6.27.23-0.1.1/sound/usb/usbaudio.h 2009-06-16 13:54:10.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/usb/usbaudio.h 2009-07-24 10:24:24.000000000 +0100 +@@ -153,7 +153,7 @@ enum quirk_type { + QUIRK_MIDI_YAMAHA, + QUIRK_MIDI_MIDIMAN, + QUIRK_MIDI_NOVATION, +- QUIRK_MIDI_RAW, ++ QUIRK_MIDI_FASTLANE, + QUIRK_MIDI_EMAGIC, + QUIRK_MIDI_CME, + QUIRK_AUDIO_STANDARD_INTERFACE, +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/usb/usbmidi.c linux-2.6.27.25-0.1.1/sound/usb/usbmidi.c +--- linux-2.6.27.23-0.1.1/sound/usb/usbmidi.c 2009-06-16 13:40:23.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/usb/usbmidi.c 2009-07-24 10:24:24.000000000 +0100 +@@ -1733,8 +1733,18 @@ int snd_usb_create_midi_interface(struct + umidi->usb_protocol_ops = &snd_usbmidi_novation_ops; + err = snd_usbmidi_detect_per_port_endpoints(umidi, endpoints); + break; +- case QUIRK_MIDI_RAW: ++ case QUIRK_MIDI_FASTLANE: + umidi->usb_protocol_ops = &snd_usbmidi_raw_ops; ++ /* ++ * Interface 1 contains isochronous endpoints, but with the same ++ * numbers as in interface 0. Since it is interface 1 that the ++ * USB core has most recently seen, these descriptors are now ++ * associated with the endpoint numbers. This will foul up our ++ * attempts to submit bulk/interrupt URBs to the endpoints in ++ * interface 0, so we have to make sure that the USB core looks ++ * again at interface 0 by calling usb_set_interface() on it. ++ */ ++ usb_set_interface(umidi->chip->dev, 0, 0); + err = snd_usbmidi_detect_per_port_endpoints(umidi, endpoints); + break; + case QUIRK_MIDI_EMAGIC: +diff -purN -X linux-2.6.27.25-0.1.1/Documentation/dontdiff linux-2.6.27.23-0.1.1/sound/usb/usbquirks.h linux-2.6.27.25-0.1.1/sound/usb/usbquirks.h +--- linux-2.6.27.23-0.1.1/sound/usb/usbquirks.h 2009-06-16 13:54:10.000000000 +0100 ++++ linux-2.6.27.25-0.1.1/sound/usb/usbquirks.h 2009-07-24 10:24:24.000000000 +0100 +@@ -1756,7 +1756,7 @@ YAMAHA_DEVICE(0x7010, "UB99"), + .data = & (const struct snd_usb_audio_quirk[]) { + { + .ifnum = 0, +- .type = QUIRK_MIDI_RAW ++ .type = QUIRK_MIDI_FASTLANE + }, + { + .ifnum = 1, +--- a/buildconfigs/Rules.mk Wed May 06 15:47:13 2009 +0100 ++++ b/buildconfigs/Rules.mk Wed May 06 16:56:12 2009 +0100 +@@ -2,7 +2,7 @@ + XEN_TARGET_X86_PAE ?= y + + LINUX_SERIES = 2.6 +-LINUX_VER = 2.6.27.23-0.1.1 ++LINUX_VER = 2.6.27.25-0.1.1 + + EXTRAVERSION ?= xen + diff --git a/master/linux-2.6.27.29-0.1.1.patch b/master/linux-2.6.27.29-0.1.1.patch new file mode 100644 index 0000000..b028d80 --- /dev/null +++ b/master/linux-2.6.27.29-0.1.1.patch @@ -0,0 +1,90475 @@ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/ia64/pci/pci.c linux-2.6.27.29-0.1.1/arch/ia64/pci/pci.c +--- linux-2.6.27.25-0.1.1/arch/ia64/pci/pci.c 2009-08-05 09:42:41.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/ia64/pci/pci.c 2009-08-27 12:44:03.000000000 +0100 +@@ -750,3 +750,30 @@ static int __init pcibios_init(void) + } + + subsys_initcall(pcibios_init); ++ ++#include ++ ++u64 ia64_dma_get_required_mask(struct device *dev) ++{ ++ u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT); ++ u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT)); ++ u64 mask; ++ ++ if (!high_totalram) { ++ /* convert to mask just covering totalram */ ++ low_totalram = (1 << (fls(low_totalram) - 1)); ++ low_totalram += low_totalram - 1; ++ mask = low_totalram; ++ } else { ++ high_totalram = (1 << (fls(high_totalram) - 1)); ++ high_totalram += high_totalram - 1; ++ mask = (((u64)high_totalram) << 32) + 0xffffffff; ++ } ++ return mask; ++} ++EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask); ++ ++u64 ia64_dma_get_required_mask_wrapper(struct device *dev) ++{ ++ return platform_dma_get_required_mask(dev); ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/ia64/sn/pci/pci_dma.c linux-2.6.27.29-0.1.1/arch/ia64/sn/pci/pci_dma.c +--- linux-2.6.27.25-0.1.1/arch/ia64/sn/pci/pci_dma.c 2009-08-05 09:42:37.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/ia64/sn/pci/pci_dma.c 2009-08-27 12:44:03.000000000 +0100 +@@ -356,6 +356,12 @@ int sn_dma_mapping_error(struct device * + } + EXPORT_SYMBOL(sn_dma_mapping_error); + ++u64 sn_dma_get_required_mask(struct device *dev) ++{ ++ return DMA_64BIT_MASK; ++} ++EXPORT_SYMBOL_GPL(sn_dma_get_required_mask); ++ + char *sn_pci_get_legacy_mem(struct pci_bus *bus) + { + if (!SN_PCIBUS_BUSSOFT(bus)) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/powerpc/kernel/fpu.S linux-2.6.27.29-0.1.1/arch/powerpc/kernel/fpu.S +--- linux-2.6.27.25-0.1.1/arch/powerpc/kernel/fpu.S 2009-08-05 09:42:53.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/powerpc/kernel/fpu.S 2009-08-27 12:44:15.000000000 +0100 +@@ -145,6 +145,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX) + beq 1f + PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) + li r3,MSR_FP|MSR_FE0|MSR_FE1 ++#ifdef CONFIG_VSX ++BEGIN_FTR_SECTION ++ oris r3,r3,MSR_VSX@h ++END_FTR_SECTION_IFSET(CPU_FTR_VSX) ++#endif + andc r4,r4,r3 /* disable FP for previous task */ + PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) + 1: +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/powerpc/kernel/misc_64.S linux-2.6.27.29-0.1.1/arch/powerpc/kernel/misc_64.S +--- linux-2.6.27.25-0.1.1/arch/powerpc/kernel/misc_64.S 2009-08-05 09:42:53.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/powerpc/kernel/misc_64.S 2009-08-27 12:44:15.000000000 +0100 +@@ -493,7 +493,15 @@ _GLOBAL(giveup_altivec) + stvx vr0,r4,r3 + beq 1f + ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) ++#ifdef CONFIG_VSX ++BEGIN_FTR_SECTION ++ lis r3,(MSR_VEC|MSR_VSX)@h ++FTR_SECTION_ELSE ++ lis r3,MSR_VEC@h ++ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX) ++#else + lis r3,MSR_VEC@h ++#endif + andc r4,r4,r3 /* disable FP for previous task */ + std r4,_MSR-STACK_FRAME_OVERHEAD(r5) + 1: +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/powerpc/mm/hash_utils_64.c linux-2.6.27.29-0.1.1/arch/powerpc/mm/hash_utils_64.c +--- linux-2.6.27.25-0.1.1/arch/powerpc/mm/hash_utils_64.c 2009-08-05 09:42:48.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/powerpc/mm/hash_utils_64.c 2009-08-27 12:44:12.000000000 +0100 +@@ -514,7 +514,7 @@ static int __init htab_dt_scan_pftsize(u + + static unsigned long __init htab_get_table_size(void) + { +- unsigned long mem_size, rnd_mem_size, pteg_count; ++ unsigned long mem_size, rnd_mem_size, pteg_count, psize; + + /* If hash size isn't already provided by the platform, we try to + * retrieve it from the device-tree. If it's not there neither, we +@@ -532,7 +532,8 @@ static unsigned long __init htab_get_tab + rnd_mem_size <<= 1; + + /* # pages / 2 */ +- pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11); ++ psize = mmu_psize_defs[mmu_virtual_psize].shift; ++ pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11); + + return pteg_count << 7; + } +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/powerpc/platforms/pseries/eeh_driver.c linux-2.6.27.29-0.1.1/arch/powerpc/platforms/pseries/eeh_driver.c +--- linux-2.6.27.25-0.1.1/arch/powerpc/platforms/pseries/eeh_driver.c 2009-08-05 09:42:53.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/powerpc/platforms/pseries/eeh_driver.c 2009-08-27 12:44:12.000000000 +0100 +@@ -79,6 +79,40 @@ static int irq_in_use(unsigned int irq) + return rc; + } + ++/** ++ * eeh_disable_irq - disable interrupt for the recovering device ++ */ ++static void eeh_disable_irq(struct pci_dev *dev) ++{ ++ struct device_node *dn = pci_device_to_OF_node(dev); ++ ++ /* Don't disable MSI and MSI-X interrupts. They are ++ * effectively disabled by the DMA Stopped state ++ * when an EEH error occurs. ++ */ ++ if (dev->msi_enabled || dev->msix_enabled) ++ return; ++ ++ if (!irq_in_use(dev->irq)) ++ return; ++ ++ PCI_DN(dn)->eeh_mode |= EEH_MODE_IRQ_DISABLED; ++ disable_irq_nosync(dev->irq); ++} ++ ++/** ++ * eeh_enable_irq - enable interrupt for the recovering device ++ */ ++static void eeh_enable_irq(struct pci_dev *dev) ++{ ++ struct device_node *dn = pci_device_to_OF_node(dev); ++ ++ if ((PCI_DN(dn)->eeh_mode) & EEH_MODE_IRQ_DISABLED) { ++ PCI_DN(dn)->eeh_mode &= ~EEH_MODE_IRQ_DISABLED; ++ enable_irq(dev->irq); ++ } ++} ++ + /* ------------------------------------------------------- */ + /** + * eeh_report_error - report pci error to each device driver +@@ -98,11 +132,8 @@ static void eeh_report_error(struct pci_ + if (!driver) + return; + +- if (irq_in_use (dev->irq)) { +- struct device_node *dn = pci_device_to_OF_node(dev); +- PCI_DN(dn)->eeh_mode |= EEH_MODE_IRQ_DISABLED; +- disable_irq_nosync(dev->irq); +- } ++ eeh_disable_irq(dev); ++ + if (!driver->err_handler || + !driver->err_handler->error_detected) + return; +@@ -147,15 +178,14 @@ static void eeh_report_reset(struct pci_ + { + enum pci_ers_result rc, *res = userdata; + struct pci_driver *driver = dev->driver; +- struct device_node *dn = pci_device_to_OF_node(dev); + + if (!driver) + return; + +- if ((PCI_DN(dn)->eeh_mode) & EEH_MODE_IRQ_DISABLED) { +- PCI_DN(dn)->eeh_mode &= ~EEH_MODE_IRQ_DISABLED; +- enable_irq(dev->irq); +- } ++ dev->error_state = pci_channel_io_normal; ++ ++ eeh_enable_irq(dev); ++ + if (!driver->err_handler || + !driver->err_handler->slot_reset) + return; +@@ -174,17 +204,14 @@ static void eeh_report_reset(struct pci_ + static void eeh_report_resume(struct pci_dev *dev, void *userdata) + { + struct pci_driver *driver = dev->driver; +- struct device_node *dn = pci_device_to_OF_node(dev); + + dev->error_state = pci_channel_io_normal; + + if (!driver) + return; + +- if ((PCI_DN(dn)->eeh_mode) & EEH_MODE_IRQ_DISABLED) { +- PCI_DN(dn)->eeh_mode &= ~EEH_MODE_IRQ_DISABLED; +- enable_irq(dev->irq); +- } ++ eeh_enable_irq(dev); ++ + if (!driver->err_handler || + !driver->err_handler->resume) + return; +@@ -208,15 +235,12 @@ static void eeh_report_failure(struct pc + if (!driver) + return; + +- if (irq_in_use (dev->irq)) { +- struct device_node *dn = pci_device_to_OF_node(dev); +- PCI_DN(dn)->eeh_mode |= EEH_MODE_IRQ_DISABLED; +- disable_irq_nosync(dev->irq); +- } +- if (!driver->err_handler) +- return; +- if (!driver->err_handler->error_detected) ++ eeh_disable_irq(dev); ++ ++ if (!driver->err_handler || ++ !driver->err_handler->error_detected) + return; ++ + driver->err_handler->error_detected(dev, pci_channel_io_perm_failure); + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/x86/kernel/acpi/processor_extcntl_xen.c linux-2.6.27.29-0.1.1/arch/x86/kernel/acpi/processor_extcntl_xen.c +--- linux-2.6.27.25-0.1.1/arch/x86/kernel/acpi/processor_extcntl_xen.c 2009-08-05 09:42:37.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/x86/kernel/acpi/processor_extcntl_xen.c 2009-08-27 12:44:03.000000000 +0100 +@@ -44,9 +44,6 @@ static int xen_cx_notifier(struct acpi_p + struct xen_processor_cx *data, *buf; + struct acpi_processor_cx *cx; + +- if (action == PROCESSOR_PM_CHANGE) +- return -EINVAL; +- + /* Convert to Xen defined structure and hypercall */ + buf = kzalloc(pr->power.count * sizeof(struct xen_processor_cx), + GFP_KERNEL); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/x86/kernel/cpu/common_64-xen.c linux-2.6.27.29-0.1.1/arch/x86/kernel/cpu/common_64-xen.c +--- linux-2.6.27.25-0.1.1/arch/x86/kernel/cpu/common_64-xen.c 2009-08-05 09:49:18.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/x86/kernel/cpu/common_64-xen.c 2009-08-27 12:44:03.000000000 +0100 +@@ -615,7 +615,7 @@ void __cpuinit syscall_init(void) + }; + + if (HYPERVISOR_callback_op(CALLBACKOP_register, &cstar)) +- printk(KERN_WARN "Unable to register CSTAR callback\n"); ++ printk(KERN_WARNING "Unable to register CSTAR callback\n"); + #endif + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/x86/kernel/i386_ksyms_32.c linux-2.6.27.29-0.1.1/arch/x86/kernel/i386_ksyms_32.c +--- linux-2.6.27.25-0.1.1/arch/x86/kernel/i386_ksyms_32.c 2009-08-05 09:42:37.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/x86/kernel/i386_ksyms_32.c 2009-08-27 12:44:03.000000000 +0100 +@@ -8,6 +8,10 @@ + #ifdef CONFIG_FTRACE + /* mcount is defined in assembly */ + EXPORT_SYMBOL(mcount); ++#else ++/* export a stub for kabi compatibility */ ++void mcount(void) { } ++EXPORT_SYMBOL(mcount); + #endif + + /* Networking helper routines. */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/x86/kernel/pci-gart_64.c linux-2.6.27.29-0.1.1/arch/x86/kernel/pci-gart_64.c +--- linux-2.6.27.25-0.1.1/arch/x86/kernel/pci-gart_64.c 2009-08-05 09:42:37.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/x86/kernel/pci-gart_64.c 2009-08-27 12:44:03.000000000 +0100 +@@ -658,8 +658,6 @@ static __init int init_k8_gatt(struct ag + memset(gatt, 0, gatt_size); + agp_gatt_table = gatt; + +- enable_gart_translations(); +- + error = sysdev_class_register(&gart_sysdev_class); + if (!error) + error = sysdev_register(&device_gart); +@@ -828,6 +826,14 @@ void __init gart_iommu_init(void) + wbinvd(); + + /* ++ * Now all caches are flushed and we can safely enable ++ * GART hardware. Doing it early leaves the possibility ++ * of stale cache entries that can lead to GART PTE ++ * errors. ++ */ ++ enable_gart_translations(); ++ ++ /* + * Try to workaround a bug (thanks to BenH): + * Set unmapped entries to a scratch page instead of 0. + * Any prefetches that hit unmapped entries won't get an bus abort +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/x86/kernel/reboot.c linux-2.6.27.29-0.1.1/arch/x86/kernel/reboot.c +--- linux-2.6.27.25-0.1.1/arch/x86/kernel/reboot.c 2009-08-27 12:59:03.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/x86/kernel/reboot.c 2009-08-27 12:44:03.000000000 +0100 +@@ -172,22 +172,22 @@ static struct dmi_system_id __initdata r + DMI_MATCH(DMI_BOARD_NAME, "0KW626"), + }, + }, +- { /* Handle problems with rebooting on Dell Optiplex 330 with 0KP561 */ ++ { /* Handle problems with rebooting on Dell Optiplex 360 with 0T656F */ + .callback = set_bios_reboot, +- .ident = "Dell OptiPlex 330", ++ .ident = "Dell OptiPlex 360", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), +- DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 330"), +- DMI_MATCH(DMI_BOARD_NAME, "0KP561"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 360"), ++ DMI_MATCH(DMI_BOARD_NAME, "0T656F"), + }, + }, +- { /* Handle problems with rebooting on Dell Optiplex 360 with 0T656F */ ++ { /* Handle problems with rebooting on Dell Optiplex 330 with 0KP561 */ + .callback = set_bios_reboot, +- .ident = "Dell OptiPlex 360", ++ .ident = "Dell OptiPlex 330", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), +- DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 360"), +- DMI_MATCH(DMI_BOARD_NAME, "0T656F"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 330"), ++ DMI_MATCH(DMI_BOARD_NAME, "0KP561"), + }, + }, + { /* Handle problems with rebooting on Dell 2400's */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/x86/kernel/setup.c linux-2.6.27.29-0.1.1/arch/x86/kernel/setup.c +--- linux-2.6.27.25-0.1.1/arch/x86/kernel/setup.c 2009-08-05 09:49:18.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/x86/kernel/setup.c 2009-08-27 12:44:03.000000000 +0100 +@@ -251,15 +251,13 @@ static inline void copy_edd(void) + + #ifdef CONFIG_BLK_DEV_INITRD + +-#ifdef CONFIG_X86_32 +- + #define MAX_MAP_CHUNK (NR_FIX_BTMAPS << PAGE_SHIFT) + static void __init relocate_initrd(void) + { + + u64 ramdisk_image = boot_params.hdr.ramdisk_image; + u64 ramdisk_size = boot_params.hdr.ramdisk_size; +- u64 end_of_lowmem = max_low_pfn << PAGE_SHIFT; ++ u64 end_of_lowmem = max_low_pfn_mapped << PAGE_SHIFT; + u64 ramdisk_here; + unsigned long slop, clen, mapaddr; + char *p, *q; +@@ -315,14 +313,13 @@ static void __init relocate_initrd(void) + ramdisk_image, ramdisk_image + ramdisk_size - 1, + ramdisk_here, ramdisk_here + ramdisk_size - 1); + } +-#endif + + static void __init reserve_initrd(void) + { + u64 ramdisk_image = boot_params.hdr.ramdisk_image; + u64 ramdisk_size = boot_params.hdr.ramdisk_size; + u64 ramdisk_end = ramdisk_image + ramdisk_size; +- u64 end_of_lowmem = max_low_pfn << PAGE_SHIFT; ++ u64 end_of_lowmem = max_low_pfn_mapped << PAGE_SHIFT; + + if (!boot_params.hdr.type_of_loader || + !ramdisk_image || !ramdisk_size) +@@ -352,14 +349,8 @@ static void __init reserve_initrd(void) + return; + } + +-#ifdef CONFIG_X86_32 + relocate_initrd(); +-#else +- printk(KERN_ERR "initrd extends beyond end of memory " +- "(0x%08llx > 0x%08llx)\ndisabling initrd\n", +- ramdisk_end, end_of_lowmem); +- initrd_start = 0; +-#endif ++ + free_early(ramdisk_image, ramdisk_end); + } + #else +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/x86/kernel/setup-xen.c linux-2.6.27.29-0.1.1/arch/x86/kernel/setup-xen.c +--- linux-2.6.27.25-0.1.1/arch/x86/kernel/setup-xen.c 2009-08-05 09:49:18.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/x86/kernel/setup-xen.c 2009-08-27 12:44:03.000000000 +0100 +@@ -286,15 +286,13 @@ static inline void copy_edd(void) + + #ifdef CONFIG_BLK_DEV_INITRD + +-#if defined(CONFIG_X86_32) && !defined(CONFIG_XEN) +- + #define MAX_MAP_CHUNK (NR_FIX_BTMAPS << PAGE_SHIFT) + static void __init relocate_initrd(void) + { +- ++#ifndef CONFIG_XEN + u64 ramdisk_image = boot_params.hdr.ramdisk_image; + u64 ramdisk_size = boot_params.hdr.ramdisk_size; +- u64 end_of_lowmem = max_low_pfn << PAGE_SHIFT; ++ u64 end_of_lowmem = max_low_pfn_mapped << PAGE_SHIFT; + u64 ramdisk_here; + unsigned long slop, clen, mapaddr; + char *p, *q; +@@ -349,8 +347,14 @@ static void __init relocate_initrd(void) + " %08llx - %08llx\n", + ramdisk_image, ramdisk_image + ramdisk_size - 1, + ramdisk_here, ramdisk_here + ramdisk_size - 1); +-} ++#else ++ printk(KERN_ERR "initrd extends beyond end of memory " ++ "(0x%08lx > 0x%08lx)\ndisabling initrd\n", ++ __pa(xen_start_info->mod_start) + xen_start_info->mod_len, ++ max_low_pfn_mapped << PAGE_SHIFT); ++ initrd_start = 0; + #endif ++} + + static void __init reserve_initrd(void) + { +@@ -358,7 +362,7 @@ static void __init reserve_initrd(void) + u64 ramdisk_image = boot_params.hdr.ramdisk_image; + u64 ramdisk_size = boot_params.hdr.ramdisk_size; + u64 ramdisk_end = ramdisk_image + ramdisk_size; +- u64 end_of_lowmem = max_low_pfn << PAGE_SHIFT; ++ u64 end_of_lowmem = max_low_pfn_mapped << PAGE_SHIFT; + + if (!boot_params.hdr.type_of_loader || + !ramdisk_image || !ramdisk_size) +@@ -367,7 +371,7 @@ static void __init reserve_initrd(void) + unsigned long ramdisk_image = __pa(xen_start_info->mod_start); + unsigned long ramdisk_size = xen_start_info->mod_len; + unsigned long ramdisk_end = ramdisk_image + ramdisk_size; +- unsigned long end_of_lowmem = max_low_pfn << PAGE_SHIFT; ++ unsigned long end_of_lowmem = max_low_pfn_mapped << PAGE_SHIFT; + + if (!xen_start_info->mod_start || !ramdisk_size) + return; /* No initrd provided by bootloader */ +@@ -400,14 +404,8 @@ static void __init reserve_initrd(void) + return; + } + +-#if defined(CONFIG_X86_32) && !defined(CONFIG_XEN) + relocate_initrd(); +-#else +- printk(KERN_ERR "initrd extends beyond end of memory " +- "(0x%08lx > 0x%08lx)\ndisabling initrd\n", +- ramdisk_end, end_of_lowmem); +- initrd_start = 0; +-#endif ++ + free_early(ramdisk_image, ramdisk_end); + } + #else +@@ -849,6 +847,9 @@ void __init setup_arch(char **cmdline_p) + + finish_e820_parsing(); + ++ if (efi_enabled) ++ efi_init(); ++ + if (is_initial_xendomain()) { + dmi_scan_machine(); + dmi_check_system(bad_bios_dmi_table); +@@ -864,8 +865,6 @@ void __init setup_arch(char **cmdline_p) + insert_resource(&iomem_resource, &data_resource); + insert_resource(&iomem_resource, &bss_resource); + +- if (efi_enabled) +- efi_init(); + + #ifdef CONFIG_X86_32 + if (ppro_with_ram_bug()) { +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/x86/kernel/x8664_ksyms_64.c linux-2.6.27.29-0.1.1/arch/x86/kernel/x8664_ksyms_64.c +--- linux-2.6.27.25-0.1.1/arch/x86/kernel/x8664_ksyms_64.c 2009-08-05 09:42:37.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/x86/kernel/x8664_ksyms_64.c 2009-08-27 12:44:03.000000000 +0100 +@@ -15,6 +15,10 @@ + #ifdef CONFIG_FTRACE + /* mcount is defined in assembly */ + EXPORT_SYMBOL(mcount); ++#else ++/* export a stub for kabi compatibility */ ++void mcount(void) { } ++EXPORT_SYMBOL(mcount); + #endif + + EXPORT_SYMBOL(kernel_thread); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/x86/mm/gup.c linux-2.6.27.29-0.1.1/arch/x86/mm/gup.c +--- linux-2.6.27.25-0.1.1/arch/x86/mm/gup.c 2009-08-05 09:42:37.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/x86/mm/gup.c 2009-08-27 12:44:00.000000000 +0100 +@@ -231,10 +231,15 @@ int get_user_pages_fast(unsigned long st + start &= PAGE_MASK; + addr = start; + len = (unsigned long) nr_pages << PAGE_SHIFT; ++ + end = start + len; +- if (unlikely(!access_ok(write ? VERIFY_WRITE : VERIFY_READ, +- start, len))) ++ if (end < start) ++ goto slow_irqon; ++ ++#ifdef CONFIG_X86_64 ++ if (end >> 47) + goto slow_irqon; ++#endif + + /* + * XXX: batch / limit 'nr', to avoid large irq off latency +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/x86/mm/pageattr-xen.c linux-2.6.27.29-0.1.1/arch/x86/mm/pageattr-xen.c +--- linux-2.6.27.25-0.1.1/arch/x86/mm/pageattr-xen.c 2009-08-05 09:49:15.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/x86/mm/pageattr-xen.c 2009-08-27 12:44:03.000000000 +0100 +@@ -584,6 +584,17 @@ static int split_large_page(pte_t *kpte, + mk_pte(base, PAGE_KERNEL_RO), 0)) + BUG(); + __set_pmd_pte(kpte, address, level, mk_pte(base, __pgprot(_KERNPG_TABLE))); ++ ++ /* ++ * Intel Atom errata AAH41 workaround. ++ * ++ * The real fix should be in hw or in a microcode update, but ++ * we also probabilistically try to reduce the window of having ++ * a large TLB mixed with 4K TLBs while instruction fetches are ++ * going on. ++ */ ++ __flush_tlb_all(); ++ + base = NULL; + + out_unlock: +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/arch/x86/mm/srat_64.c linux-2.6.27.29-0.1.1/arch/x86/mm/srat_64.c +--- linux-2.6.27.25-0.1.1/arch/x86/mm/srat_64.c 2009-08-05 09:49:15.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/arch/x86/mm/srat_64.c 2009-08-27 12:44:00.000000000 +0100 +@@ -87,8 +87,10 @@ static __init void bad_srat(void) + found_add_area = 0; + for (i = 0; i < MAX_LOCAL_APIC; i++) + apicid_to_node[i] = NUMA_NO_NODE; +- for (i = 0; i < MAX_NUMNODES; i++) +- nodes_add[i].start = nodes[i].end = 0; ++ for (i = 0; i < MAX_NUMNODES; i++) { ++ nodes[i].start = nodes[i].end = 0; ++ nodes_add[i].start = nodes_add[i].end = 0; ++ } + remove_all_active_ranges(); + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/block/blk-merge.c linux-2.6.27.29-0.1.1/block/blk-merge.c +--- linux-2.6.27.25-0.1.1/block/blk-merge.c 2009-08-05 09:42:53.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/block/blk-merge.c 2009-08-27 12:44:15.000000000 +0100 +@@ -376,6 +376,12 @@ static int attempt_merge(struct request_ + if (blk_integrity_rq(req) != blk_integrity_rq(next)) + return 0; + ++ /* don't merge requests of different failfast settings */ ++ if (blk_failfast_dev(req) != blk_failfast_dev(next) || ++ blk_failfast_transport(req) != blk_failfast_transport(next) || ++ blk_failfast_driver(req) != blk_failfast_driver(next)) ++ return 0; ++ + /* + * If we are allowed to merge, then append bio list + * from next to rq and release next. merge_requests_fn +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/block/elevator.c linux-2.6.27.29-0.1.1/block/elevator.c +--- linux-2.6.27.25-0.1.1/block/elevator.c 2009-08-05 09:42:53.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/block/elevator.c 2009-08-27 12:44:15.000000000 +0100 +@@ -99,6 +99,14 @@ int elv_rq_merge_ok(struct request *rq, + if (bio_integrity(bio) != blk_integrity_rq(rq)) + return 0; + ++ /* ++ * Don't merge if failfast settings don't match ++ */ ++ if (!bio_failfast_dev(bio) != !blk_failfast_dev(rq) || ++ !bio_failfast_transport(bio) != !blk_failfast_transport(rq) || ++ !bio_failfast_driver(bio) != !blk_failfast_driver(rq)) ++ return 0; ++ + if (!elv_iosched_allow_merge(rq, bio)) + return 0; + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/Documentation/DMA-API.txt linux-2.6.27.29-0.1.1/Documentation/DMA-API.txt +--- linux-2.6.27.25-0.1.1/Documentation/DMA-API.txt 2009-08-05 09:43:27.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/Documentation/DMA-API.txt 2009-08-27 12:44:42.000000000 +0100 +@@ -170,16 +170,15 @@ Returns: 0 if successful and a negative + u64 + dma_get_required_mask(struct device *dev) + +-After setting the mask with dma_set_mask(), this API returns the +-actual mask (within that already set) that the platform actually +-requires to operate efficiently. Usually this means the returned mask ++This API returns the mask that the platform requires to ++operate efficiently. Usually this means the returned mask + is the minimum required to cover all of memory. Examining the + required mask gives drivers with variable descriptor sizes the + opportunity to use smaller descriptors as necessary. + + Requesting the required mask does not alter the current mask. If you +-wish to take advantage of it, you should issue another dma_set_mask() +-call to lower the mask again. ++wish to take advantage of it, you should issue a dma_set_mask() ++call to set the mask to the value returned. + + + Part Id - Streaming DMA mappings +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/acpi/ec.c linux-2.6.27.29-0.1.1/drivers/acpi/ec.c +--- linux-2.6.27.25-0.1.1/drivers/acpi/ec.c 2009-08-05 09:49:39.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/acpi/ec.c 2009-08-27 12:44:24.000000000 +0100 +@@ -1017,7 +1017,8 @@ int __init acpi_ec_ecdt_probe(void) + * which needs it, has fake EC._INI method, so use it as flag. + * Keep boot_ec struct as it will be needed soon. + */ +- if (ACPI_FAILURE(acpi_get_handle(boot_ec->handle, "_INI", &dummy))) ++ if (!dmi_name_in_vendors("ASUS") || ++ ACPI_FAILURE(acpi_get_handle(boot_ec->handle, "_INI", &dummy))) + return -ENODEV; + install: + if (!ec_install_handlers(boot_ec)) { +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/acpi/processor_core.c linux-2.6.27.29-0.1.1/drivers/acpi/processor_core.c +--- linux-2.6.27.25-0.1.1/drivers/acpi/processor_core.c 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/acpi/processor_core.c 2009-08-27 12:44:24.000000000 +0100 +@@ -625,7 +625,16 @@ static int acpi_processor_get_info(struc + return -ENODEV; + } + } +- ++ /* ++ * On some boxes several processors use the same processor bus id. ++ * But they are located in different scope. For example: ++ * \_SB.SCK0.CPU0 ++ * \_SB.SCK1.CPU0 ++ * Rename the processor device bus id. And the new bus id will be ++ * generated as the following format: ++ * CPU+CPU ID. ++ */ ++ sprintf(acpi_device_bid(device), "CPU%X", pr->id); + ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Processor [%d:%d]\n", pr->id, + pr->acpi_id)); + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/ata/ahci.c linux-2.6.27.29-0.1.1/drivers/ata/ahci.c +--- linux-2.6.27.25-0.1.1/drivers/ata/ahci.c 2009-08-05 09:49:38.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/ata/ahci.c 2009-08-27 12:44:15.000000000 +0100 +@@ -1735,7 +1735,8 @@ static int ahci_sb600_softreset(struct a + irq_sts = readl(port_mmio + PORT_IRQ_STAT); + if (irq_sts & PORT_IRQ_BAD_PMP) { + ata_link_printk(link, KERN_WARNING, +- "failed due to HW bug, retry pmp=0\n"); ++ "applying SB600 PMP SRST workaround " ++ "and retrying\n"); + rc = ahci_do_softreset(link, class, 0, deadline, + ahci_check_ready); + } +@@ -2441,6 +2442,8 @@ static void ahci_print_info(struct ata_h + speed_s = "1.5"; + else if (speed == 2) + speed_s = "3"; ++ else if (speed == 3) ++ speed_s = "6"; + else + speed_s = "?"; + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/ata/libata-core.c linux-2.6.27.29-0.1.1/drivers/ata/libata-core.c +--- linux-2.6.27.25-0.1.1/drivers/ata/libata-core.c 2009-08-05 09:49:38.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/ata/libata-core.c 2009-08-27 12:44:15.000000000 +0100 +@@ -930,6 +930,7 @@ static const char *sata_spd_string(unsig + static const char * const spd_str[] = { + "1.5 Gbps", + "3.0 Gbps", ++ "6.0 Gbps", + }; + + if (spd == 0 || (spd - 1) >= ARRAY_SIZE(spd_str)) +@@ -4131,6 +4132,9 @@ static const struct ata_blacklist_entry + { "WDC WD2500JD-00HBB0", "WD-WMAL71490727", ATA_HORKAGE_BROKEN_HPA }, + { "MAXTOR 6L080L4", "A93.0500", ATA_HORKAGE_BROKEN_HPA }, + ++ /* this one allows HPA unlocking but fails IOs on the area */ ++ { "OCZ-VERTEX", "1.30", ATA_HORKAGE_BROKEN_HPA }, ++ + /* Devices which report 1 sector over size HPA */ + { "ST340823A", NULL, ATA_HORKAGE_HPA_SIZE, }, + { "ST320413A", NULL, ATA_HORKAGE_HPA_SIZE, }, +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/base/platform.c linux-2.6.27.29-0.1.1/drivers/base/platform.c +--- linux-2.6.27.25-0.1.1/drivers/base/platform.c 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/base/platform.c 2009-08-27 12:44:24.000000000 +0100 +@@ -931,4 +931,13 @@ u64 dma_get_required_mask(struct device + return mask; + } + EXPORT_SYMBOL_GPL(dma_get_required_mask); ++#else ++#ifdef __ia64__ ++u64 ia64_dma_get_required_mask_wrapper(struct device *dev); ++u64 dma_get_required_mask(struct device *dev) ++{ ++ return ia64_dma_get_required_mask_wrapper(dev); ++} ++EXPORT_SYMBOL_GPL(dma_get_required_mask); ++#endif + #endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/base/power/power.h linux-2.6.27.29-0.1.1/drivers/base/power/power.h +--- linux-2.6.27.25-0.1.1/drivers/base/power/power.h 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/base/power/power.h 2009-08-27 12:44:24.000000000 +0100 +@@ -1,6 +1,9 @@ + static inline void device_pm_init(struct device *dev) + { + dev->power.status = DPM_ON; ++#ifdef CONFIG_PM_SLEEP ++ INIT_LIST_HEAD(&dev->power.entry); ++#endif + } + + #ifdef CONFIG_PM_SLEEP +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/block/cciss.c linux-2.6.27.29-0.1.1/drivers/block/cciss.c +--- linux-2.6.27.25-0.1.1/drivers/block/cciss.c 2009-08-05 09:43:14.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/block/cciss.c 2009-08-27 12:44:29.000000000 +0100 +@@ -214,31 +214,27 @@ static struct block_device_operations cc + /* + * Enqueuing and dequeuing functions for cmdlists. + */ +-static inline void addQ(CommandList_struct **Qptr, CommandList_struct *c) ++static inline void addQ(struct hlist_head *list, CommandList_struct *c) + { +- if (*Qptr == NULL) { +- *Qptr = c; +- c->next = c->prev = c; +- } else { +- c->prev = (*Qptr)->prev; +- c->next = (*Qptr); +- (*Qptr)->prev->next = c; +- (*Qptr)->prev = c; +- } ++ hlist_add_head(&c->list, list); + } + +-static inline CommandList_struct *removeQ(CommandList_struct **Qptr, +- CommandList_struct *c) ++static inline void removeQ(CommandList_struct *c) + { +- if (c && c->next != c) { +- if (*Qptr == c) +- *Qptr = c->next; +- c->prev->next = c->next; +- c->next->prev = c->prev; +- } else { +- *Qptr = NULL; ++ /* ++ * After kexec/dump some commands might still ++ * be in flight, which the firmware will try ++ * to complete. Resetting the firmware doesn't work ++ * with old fw revisions, so we have to mark ++ * them off as 'stale' to prevent the driver from ++ * falling over. ++ */ ++ if (unlikely(hlist_unhashed(&c->list))) { ++ c->cmd_type = CMD_MSG_STALE; ++ return; + } +- return c; ++ ++ hlist_del_init(&c->list); + } + + #include "cciss_scsi.c" /* For SCSI tape support */ +@@ -505,6 +501,7 @@ static CommandList_struct *cmd_alloc(ctl + c->cmdindex = i; + } + ++ INIT_HLIST_NODE(&c->list); + c->busaddr = (__u32) cmd_dma_handle; + temp64.val = (__u64) err_dma_handle; + c->ErrDesc.Addr.lower = temp64.val32.lower; +@@ -2549,7 +2546,8 @@ static void start_io(ctlr_info_t *h) + { + CommandList_struct *c; + +- while ((c = h->reqQ) != NULL) { ++ while (!hlist_empty(&h->reqQ)) { ++ c = hlist_entry(h->reqQ.first, CommandList_struct, list); + /* can't do anything if fifo is full */ + if ((h->access.fifo_full(h))) { + printk(KERN_WARNING "cciss: fifo full\n"); +@@ -2557,14 +2555,14 @@ static void start_io(ctlr_info_t *h) + } + + /* Get the first entry from the Request Q */ +- removeQ(&(h->reqQ), c); ++ removeQ(c); + h->Qdepth--; + + /* Tell the controller execute command */ + h->access.submit_command(h, c); + + /* Put job onto the completed Q */ +- addQ(&(h->cmpQ), c); ++ addQ(&h->cmpQ, c); + } + } + +@@ -2577,7 +2575,7 @@ static inline void resend_cciss_cmd(ctlr + memset(c->err_info, 0, sizeof(ErrorInfo_struct)); + + /* add it to software queue and then send it to the controller */ +- addQ(&(h->reqQ), c); ++ addQ(&h->reqQ, c); + h->Qdepth++; + if (h->Qdepth > h->maxQsinceinit) + h->maxQsinceinit = h->Qdepth; +@@ -2898,7 +2896,7 @@ static void do_cciss_request(struct requ + + spin_lock_irq(q->queue_lock); + +- addQ(&(h->reqQ), c); ++ addQ(&h->reqQ, c); + h->Qdepth++; + if (h->Qdepth > h->maxQsinceinit) + h->maxQsinceinit = h->Qdepth; +@@ -2986,16 +2984,12 @@ static irqreturn_t do_cciss_intr(int irq + a = c->busaddr; + + } else { ++ struct hlist_node *tmp; ++ + a &= ~3; +- if ((c = h->cmpQ) == NULL) { +- printk(KERN_WARNING +- "cciss: Completion of %08x ignored\n", +- a1); +- continue; +- } +- while (c->busaddr != a) { +- c = c->next; +- if (c == h->cmpQ) ++ c = NULL; ++ hlist_for_each_entry(c, tmp, &h->cmpQ, list) { ++ if (c->busaddr == a) + break; + } + } +@@ -3003,8 +2997,8 @@ static irqreturn_t do_cciss_intr(int irq + * If we've found the command, take it off the + * completion Q and free it + */ +- if (c->busaddr == a) { +- removeQ(&h->cmpQ, c); ++ if (c && c->busaddr == a) { ++ removeQ(c); + if (c->cmd_type == CMD_RWREQ) { + complete_command(h, c, 0); + } else if (c->cmd_type == CMD_IOCTL_PEND) { +@@ -3423,6 +3417,8 @@ static int __devinit cciss_init_one(stru + return -1; + + hba[i]->busy_initializing = 1; ++ INIT_HLIST_HEAD(&hba[i]->cmpQ); ++ INIT_HLIST_HEAD(&hba[i]->reqQ); + + if (cciss_pci_init(hba[i], pdev) != 0) + goto clean1; +@@ -3730,16 +3726,19 @@ static void fail_all_cmds(unsigned long + pci_disable_device(h->pdev); /* Make sure it is really dead. */ + + /* move everything off the request queue onto the completed queue */ +- while ((c = h->reqQ) != NULL) { +- removeQ(&(h->reqQ), c); ++ while (!hlist_empty(&h->reqQ)) { ++ c = hlist_entry(h->reqQ.first, CommandList_struct, list); ++ removeQ(c); + h->Qdepth--; +- addQ(&(h->cmpQ), c); ++ addQ(&h->cmpQ, c); + } + + /* Now, fail everything on the completed queue with a HW error */ +- while ((c = h->cmpQ) != NULL) { +- removeQ(&h->cmpQ, c); +- c->err_info->CommandStatus = CMD_HARDWARE_ERR; ++ while (!hlist_empty(&h->cmpQ)) { ++ c = hlist_entry(h->cmpQ.first, CommandList_struct, list); ++ removeQ(c); ++ if (c->cmd_type != CMD_MSG_STALE) ++ c->err_info->CommandStatus = CMD_HARDWARE_ERR; + if (c->cmd_type == CMD_RWREQ) { + complete_command(h, c, 0); + } else if (c->cmd_type == CMD_IOCTL_PEND) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/block/cciss_cmd.h linux-2.6.27.29-0.1.1/drivers/block/cciss_cmd.h +--- linux-2.6.27.25-0.1.1/drivers/block/cciss_cmd.h 2009-08-05 09:43:14.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/block/cciss_cmd.h 2009-08-27 12:44:29.000000000 +0100 +@@ -249,6 +249,7 @@ typedef struct _ErrorInfo_struct { + #define CMD_SCSI 0x03 + #define CMD_MSG_DONE 0x04 + #define CMD_MSG_TIMEOUT 0x05 ++#define CMD_MSG_STALE 0xff + + /* This structure needs to be divisible by 8 for new + * indexing method. +@@ -265,8 +266,7 @@ typedef struct _CommandList_struct { + int ctlr; + int cmd_type; + long cmdindex; +- struct _CommandList_struct *prev; +- struct _CommandList_struct *next; ++ struct hlist_node list; + struct request * rq; + struct completion *waiting; + int retry_count; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/block/cciss.h linux-2.6.27.29-0.1.1/drivers/block/cciss.h +--- linux-2.6.27.25-0.1.1/drivers/block/cciss.h 2009-08-05 09:43:14.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/block/cciss.h 2009-08-27 12:44:29.000000000 +0100 +@@ -89,8 +89,8 @@ struct ctlr_info + struct access_method access; + + /* queue and queue Info */ +- CommandList_struct *reqQ; +- CommandList_struct *cmpQ; ++ struct hlist_head reqQ; ++ struct hlist_head cmpQ; + unsigned int Qdepth; + unsigned int maxQsinceinit; + unsigned int maxSG; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/block/floppy.c linux-2.6.27.29-0.1.1/drivers/block/floppy.c +--- linux-2.6.27.25-0.1.1/drivers/block/floppy.c 2009-08-05 09:43:14.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/block/floppy.c 2009-08-27 12:44:29.000000000 +0100 +@@ -177,6 +177,7 @@ static int print_unex = 1; + #include + #include + #include ++#include + #include /* for invalidate_buffers() */ + #include + +@@ -551,6 +552,8 @@ static void process_fd_request(void); + static void recalibrate_floppy(void); + static void floppy_shutdown(unsigned long); + ++static int floppy_request_regions(int); ++static void floppy_release_regions(int); + static int floppy_grab_irq_and_dma(void); + static void floppy_release_irq_and_dma(void); + +@@ -3317,7 +3320,10 @@ static inline int set_geometry(unsigned + if (!capable(CAP_SYS_ADMIN)) + return -EPERM; + mutex_lock(&open_lock); +- LOCK_FDC(drive, 1); ++ if (lock_fdc(drive, 1)) { ++ mutex_unlock(&open_lock); ++ return -EINTR; ++ } + floppy_type[type] = *g; + floppy_type[type].name = "user format"; + for (cnt = type << 2; cnt < (type << 2) + 4; cnt++) +@@ -4273,8 +4279,7 @@ static int __init floppy_init(void) + FDCS->rawcmd = 2; + if (user_reset_fdc(-1, FD_RESET_ALWAYS, 0)) { + /* free ioports reserved by floppy_grab_irq_and_dma() */ +- release_region(FDCS->address + 2, 4); +- release_region(FDCS->address + 7, 1); ++ floppy_release_regions(fdc); + FDCS->address = -1; + FDCS->version = FDC_NONE; + continue; +@@ -4283,8 +4288,7 @@ static int __init floppy_init(void) + FDCS->version = get_fdc_version(); + if (FDCS->version == FDC_NONE) { + /* free ioports reserved by floppy_grab_irq_and_dma() */ +- release_region(FDCS->address + 2, 4); +- release_region(FDCS->address + 7, 1); ++ floppy_release_regions(fdc); + FDCS->address = -1; + continue; + } +@@ -4357,6 +4361,47 @@ out_put_disk: + + static DEFINE_SPINLOCK(floppy_usage_lock); + ++static const struct io_region { ++ int offset; ++ int size; ++} io_regions[] = { ++ { 2, 1 }, ++ /* address + 3 is sometimes reserved by pnp bios for motherboard */ ++ { 4, 2 }, ++ /* address + 6 is reserved, and may be taken by IDE. ++ * Unfortunately, Adaptec doesn't know this :-(, */ ++ { 7, 1 }, ++}; ++ ++static void floppy_release_allocated_regions(int fdc, const struct io_region *p) ++{ ++ while (p != io_regions) { ++ p--; ++ release_region(FDCS->address + p->offset, p->size); ++ } ++} ++ ++#define ARRAY_END(X) (&((X)[ARRAY_SIZE(X)])) ++ ++static int floppy_request_regions(int fdc) ++{ ++ const struct io_region *p; ++ ++ for (p = io_regions; p < ARRAY_END(io_regions); p++) { ++ if (!request_region(FDCS->address + p->offset, p->size, "floppy")) { ++ DPRINT("Floppy io-port 0x%04lx in use\n", FDCS->address + p->offset); ++ floppy_release_allocated_regions(fdc, p); ++ return -EBUSY; ++ } ++ } ++ return 0; ++} ++ ++static void floppy_release_regions(int fdc) ++{ ++ floppy_release_allocated_regions(fdc, ARRAY_END(io_regions)); ++} ++ + static int floppy_grab_irq_and_dma(void) + { + unsigned long flags; +@@ -4398,18 +4443,8 @@ static int floppy_grab_irq_and_dma(void) + + for (fdc = 0; fdc < N_FDC; fdc++) { + if (FDCS->address != -1) { +- if (!request_region(FDCS->address + 2, 4, "floppy")) { +- DPRINT("Floppy io-port 0x%04lx in use\n", +- FDCS->address + 2); +- goto cleanup1; +- } +- if (!request_region(FDCS->address + 7, 1, "floppy DIR")) { +- DPRINT("Floppy io-port 0x%04lx in use\n", +- FDCS->address + 7); +- goto cleanup2; +- } +- /* address + 6 is reserved, and may be taken by IDE. +- * Unfortunately, Adaptec doesn't know this :-(, */ ++ if (floppy_request_regions(fdc)) ++ goto cleanup; + } + } + for (fdc = 0; fdc < N_FDC; fdc++) { +@@ -4431,15 +4466,11 @@ static int floppy_grab_irq_and_dma(void) + fdc = 0; + irqdma_allocated = 1; + return 0; +-cleanup2: +- release_region(FDCS->address + 2, 4); +-cleanup1: ++cleanup: + fd_free_irq(); + fd_free_dma(); +- while (--fdc >= 0) { +- release_region(FDCS->address + 2, 4); +- release_region(FDCS->address + 7, 1); +- } ++ while (--fdc >= 0) ++ floppy_release_regions(fdc); + spin_lock_irqsave(&floppy_usage_lock, flags); + usage_count--; + spin_unlock_irqrestore(&floppy_usage_lock, flags); +@@ -4500,10 +4531,8 @@ static void floppy_release_irq_and_dma(v + #endif + old_fdc = fdc; + for (fdc = 0; fdc < N_FDC; fdc++) +- if (FDCS->address != -1) { +- release_region(FDCS->address + 2, 4); +- release_region(FDCS->address + 7, 1); +- } ++ if (FDCS->address != -1) ++ floppy_release_regions(fdc); + fdc = old_fdc; + } + +@@ -4572,6 +4601,13 @@ MODULE_AUTHOR("Alain L. Knaff"); + MODULE_SUPPORTED_DEVICE("fd"); + MODULE_LICENSE("GPL"); + ++/* This doesn't actually get used other than for module information */ ++static const struct pnp_device_id floppy_pnpids[] = { ++ { "PNP0700", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(pnp, floppy_pnpids); ++ + #else + + __setup("floppy=", floppy_setup); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/char/moxa.c linux-2.6.27.29-0.1.1/drivers/char/moxa.c +--- linux-2.6.27.25-0.1.1/drivers/char/moxa.c 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/char/moxa.c 2009-08-27 12:44:24.000000000 +0100 +@@ -1158,6 +1158,11 @@ static int moxa_open(struct tty_struct * + return -ENODEV; + } + ++ if (port % MAX_PORTS_PER_BOARD >= brd->numPorts) { ++ retval = -ENODEV; ++ goto out_unlock; ++ } ++ + ch = &brd->ports[port % MAX_PORTS_PER_BOARD]; + ch->port.count++; + tty->driver_data = ch; +@@ -1182,8 +1187,8 @@ static int moxa_open(struct tty_struct * + moxa_close_port(ch); + } else + ch->port.flags |= ASYNC_NORMAL_ACTIVE; ++out_unlock: + mutex_unlock(&moxa_openlock); +- + return retval; + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/char/mxser.c linux-2.6.27.29-0.1.1/drivers/char/mxser.c +--- linux-2.6.27.25-0.1.1/drivers/char/mxser.c 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/char/mxser.c 2009-08-27 12:44:24.000000000 +0100 +@@ -2790,7 +2790,7 @@ static int __init mxser_module_init(void + continue; + + brd = &mxser_boards[m]; +- retval = mxser_get_ISA_conf(!ioaddr[b], brd); ++ retval = mxser_get_ISA_conf(ioaddr[b], brd); + if (retval <= 0) { + brd->info = NULL; + continue; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/char/pcmcia/cm4000_cs.c linux-2.6.27.29-0.1.1/drivers/char/pcmcia/cm4000_cs.c +--- linux-2.6.27.25-0.1.1/drivers/char/pcmcia/cm4000_cs.c 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/char/pcmcia/cm4000_cs.c 2009-08-27 12:44:24.000000000 +0100 +@@ -1575,7 +1575,8 @@ static long cmm_ioctl(struct file *filp, + clear_bit(LOCK_IO, &dev->flags); + wake_up_interruptible(&dev->ioq); + +- return 0; ++ rc = 0; ++ break; + case CM_IOCSPTS: + { + struct ptsreq krnptsreq; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/firmware/memmap.c linux-2.6.27.29-0.1.1/drivers/firmware/memmap.c +--- linux-2.6.27.25-0.1.1/drivers/firmware/memmap.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/firmware/memmap.c 2009-08-27 12:44:31.000000000 +0100 +@@ -31,8 +31,12 @@ + * information is necessary as for the resource tree. + */ + struct firmware_map_entry { +- uint64_t start; /* start of the memory range */ +- uint64_t end; /* end of the memory range (incl.) */ ++ /* ++ * start and end must be u64 rather than resource_size_t, because e820 ++ * resources can lie at addresses above 4G. ++ */ ++ u64 start; /* start of the memory range */ ++ u64 end; /* end of the memory range (incl.) */ + const char *type; /* type of the memory range */ + struct list_head list; /* entry for the linked list */ + struct kobject kobj; /* kobject for each entry */ +@@ -101,7 +105,7 @@ static LIST_HEAD(map_entries); + * Common implementation of firmware_map_add() and firmware_map_add_early() + * which expects a pre-allocated struct firmware_map_entry. + **/ +-static int firmware_map_add_entry(uint64_t start, uint64_t end, ++static int firmware_map_add_entry(u64 start, u64 end, + const char *type, + struct firmware_map_entry *entry) + { +@@ -132,7 +136,7 @@ static int firmware_map_add_entry(uint64 + * + * Returns 0 on success, or -ENOMEM if no memory could be allocated. + **/ +-int firmware_map_add(uint64_t start, uint64_t end, const char *type) ++int firmware_map_add(u64 start, u64 end, const char *type) + { + struct firmware_map_entry *entry; + +@@ -156,8 +160,7 @@ int firmware_map_add(uint64_t start, uin + * + * Returns 0 on success, or -ENOMEM if no memory could be allocated. + **/ +-int __init firmware_map_add_early(uint64_t start, uint64_t end, +- const char *type) ++int __init firmware_map_add_early(u64 start, u64 end, const char *type) + { + struct firmware_map_entry *entry; + +@@ -174,12 +177,14 @@ int __init firmware_map_add_early(uint64 + + static ssize_t start_show(struct firmware_map_entry *entry, char *buf) + { +- return snprintf(buf, PAGE_SIZE, "0x%llx\n", entry->start); ++ return snprintf(buf, PAGE_SIZE, "0x%llx\n", ++ (unsigned long long)entry->start); + } + + static ssize_t end_show(struct firmware_map_entry *entry, char *buf) + { +- return snprintf(buf, PAGE_SIZE, "0x%llx\n", entry->end); ++ return snprintf(buf, PAGE_SIZE, "0x%llx\n", ++ (unsigned long long)entry->end); + } + + static ssize_t type_show(struct firmware_map_entry *entry, char *buf) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/hid/usbhid/hiddev.c linux-2.6.27.29-0.1.1/drivers/hid/usbhid/hiddev.c +--- linux-2.6.27.25-0.1.1/drivers/hid/usbhid/hiddev.c 2009-08-05 09:42:57.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/hid/usbhid/hiddev.c 2009-08-27 12:44:15.000000000 +0100 +@@ -484,8 +484,10 @@ static noinline int hiddev_ioctl_usage(s + goto goodreturn; + + case HIDIOCGCOLLECTIONINDEX: ++ i = field->usage[uref->usage_index].collection_index; ++ unlock_kernel(); + kfree(uref_multi); +- return field->usage[uref->usage_index].collection_index; ++ return i; + case HIDIOCGUSAGES: + for (i = 0; i < uref_multi->num_values; i++) + uref_multi->values[i] = +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/hwmon/max6650.c linux-2.6.27.29-0.1.1/drivers/hwmon/max6650.c +--- linux-2.6.27.25-0.1.1/drivers/hwmon/max6650.c 2009-08-05 09:43:14.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/hwmon/max6650.c 2009-08-27 12:44:29.000000000 +0100 +@@ -407,6 +407,7 @@ static ssize_t set_div(struct device *de + data->count = 3; + break; + default: ++ mutex_unlock(&data->update_lock); + dev_err(&client->dev, + "illegal value for fan divider (%d)\n", div); + return -EINVAL; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/infiniband/hw/mlx4/qp.c linux-2.6.27.29-0.1.1/drivers/infiniband/hw/mlx4/qp.c +--- linux-2.6.27.25-0.1.1/drivers/infiniband/hw/mlx4/qp.c 2009-08-05 09:43:14.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/infiniband/hw/mlx4/qp.c 2009-08-27 12:44:29.000000000 +0100 +@@ -1563,12 +1563,16 @@ int mlx4_ib_post_send(struct ib_qp *ibqp + break; + + case IB_WR_LOCAL_INV: ++ ctrl->srcrb_flags |= ++ cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); + set_local_inv_seg(wqe, wr->ex.invalidate_rkey); + wqe += sizeof (struct mlx4_wqe_local_inval_seg); + size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; + break; + + case IB_WR_FAST_REG_MR: ++ ctrl->srcrb_flags |= ++ cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); + set_fmr_seg(wqe, wr); + wqe += sizeof (struct mlx4_wqe_fmr_seg); + size += sizeof (struct mlx4_wqe_fmr_seg) / 16; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/input/misc/wistron_btns.c linux-2.6.27.29-0.1.1/drivers/input/misc/wistron_btns.c +--- linux-2.6.27.25-0.1.1/drivers/input/misc/wistron_btns.c 2009-08-05 09:43:14.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/input/misc/wistron_btns.c 2009-08-27 12:44:29.000000000 +0100 +@@ -627,6 +627,15 @@ static struct dmi_system_id dmi_ids[] __ + }, + { + .callback = dmi_matched, ++ .ident = "Maxdata Pro 7000 DX", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "MAXDATA"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "Pro 7000"), ++ }, ++ .driver_data = keymap_fs_amilo_pro_v2000 ++ }, ++ { ++ .callback = dmi_matched, + .ident = "Fujitsu N3510", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/isdn/gigaset/ev-layer.c linux-2.6.27.29-0.1.1/drivers/isdn/gigaset/ev-layer.c +--- linux-2.6.27.25-0.1.1/drivers/isdn/gigaset/ev-layer.c 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/isdn/gigaset/ev-layer.c 2009-08-27 12:44:29.000000000 +0100 +@@ -307,32 +307,33 @@ struct reply_t gigaset_tab_cid_m10x[] = + {RSP_OK, 604,604, -1, 605, 5, {ACT_CMD+AT_MSN}}, + {RSP_OK, 605,605, -1, 606, 5, {ACT_CMD+AT_ISO}}, + {RSP_NULL, 605,605, -1, 606, 5, {ACT_CMD+AT_ISO}}, +- {RSP_OK, 606,606, -1, 607, 5, {0}, "+VLS=17\r"}, /* set "Endgeraetemodus" */ ++ {RSP_OK, 606,606, -1, 607, 5, {0}, "+VLS=17\r"}, + {RSP_OK, 607,607, -1, 608,-1}, +- //{RSP_ZSAU, 608,608,ZSAU_PROCEEDING, 608, 0, {ACT_ERROR}},//DELETE + {RSP_ZSAU, 608,608,ZSAU_PROCEEDING, 609, 5, {ACT_CMD+AT_DIAL}}, + {RSP_OK, 609,609, -1, 650, 0, {ACT_DIALING}}, + +- {RSP_ZVLS, 608,608, 17, -1,-1, {ACT_DEBUG}}, +- {RSP_ZCTP, 609,609, -1, -1,-1, {ACT_DEBUG}}, +- {RSP_ZCPN, 609,609, -1, -1,-1, {ACT_DEBUG}}, + {RSP_ERROR, 601,609, -1, 0, 0, {ACT_ABORTDIAL}}, + {EV_TIMEOUT, 601,609, -1, 0, 0, {ACT_ABORTDIAL}}, + +- /* dialing */ +- {RSP_ZCTP, 650,650, -1, -1,-1, {ACT_DEBUG}}, +- {RSP_ZCPN, 650,650, -1, -1,-1, {ACT_DEBUG}}, +- {RSP_ZSAU, 650,650,ZSAU_CALL_DELIVERED, -1,-1, {ACT_DEBUG}}, /* some devices don't send this */ +- +- /* connection established */ +- {RSP_ZSAU, 650,650,ZSAU_ACTIVE, 800,-1, {ACT_CONNECT}}, //FIXME -> DLE1 +- {RSP_ZSAU, 750,750,ZSAU_ACTIVE, 800,-1, {ACT_CONNECT}}, //FIXME -> DLE1 +- +- {EV_BC_OPEN, 800,800, -1, 800,-1, {ACT_NOTIFY_BC_UP}}, //FIXME new constate + timeout ++ /* optional dialing responses */ ++ {EV_BC_OPEN, 650,650, -1, 651,-1}, ++ {RSP_ZVLS, 608,651, 17, -1,-1, {ACT_DEBUG}}, ++ {RSP_ZCTP, 609,651, -1, -1,-1, {ACT_DEBUG}}, ++ {RSP_ZCPN, 609,651, -1, -1,-1, {ACT_DEBUG}}, ++ {RSP_ZSAU, 650,651,ZSAU_CALL_DELIVERED, -1,-1, {ACT_DEBUG}}, ++ ++ /* connect */ ++ {RSP_ZSAU, 650,650,ZSAU_ACTIVE, 800,-1, {ACT_CONNECT}}, ++ {RSP_ZSAU, 651,651,ZSAU_ACTIVE, 800,-1, {ACT_CONNECT, ++ ACT_NOTIFY_BC_UP}}, ++ {RSP_ZSAU, 750,750,ZSAU_ACTIVE, 800,-1, {ACT_CONNECT}}, ++ {RSP_ZSAU, 751,751,ZSAU_ACTIVE, 800,-1, {ACT_CONNECT, ++ ACT_NOTIFY_BC_UP}}, ++ {EV_BC_OPEN, 800,800, -1, 800,-1, {ACT_NOTIFY_BC_UP}}, + + /* remote hangup */ +- {RSP_ZSAU, 650,650,ZSAU_DISCONNECT_IND, 0, 0, {ACT_REMOTEREJECT}}, +- {RSP_ZSAU, 750,750,ZSAU_DISCONNECT_IND, 0, 0, {ACT_REMOTEHUP}}, ++ {RSP_ZSAU, 650,651,ZSAU_DISCONNECT_IND, 0, 0, {ACT_REMOTEREJECT}}, ++ {RSP_ZSAU, 750,751,ZSAU_DISCONNECT_IND, 0, 0, {ACT_REMOTEHUP}}, + {RSP_ZSAU, 800,800,ZSAU_DISCONNECT_IND, 0, 0, {ACT_REMOTEHUP}}, + + /* hangup */ +@@ -371,7 +372,8 @@ struct reply_t gigaset_tab_cid_m10x[] = + {RSP_ZSAU, 700,729,ZSAU_ACTIVE, 0, 0, {ACT_ABORTACCEPT}}, + {RSP_ZSAU, 700,729,ZSAU_DISCONNECT_IND, 0, 0, {ACT_ABORTACCEPT}}, + +- {EV_TIMEOUT, 750,750, -1, 0, 0, {ACT_CONNTIMEOUT}}, ++ {EV_BC_OPEN, 750,750, -1, 751,-1}, ++ {EV_TIMEOUT, 750,751, -1, 0, 0, {ACT_CONNTIMEOUT}}, + + /* B channel closed (general case) */ + {EV_BC_CLOSED, -1, -1, -1, -1,-1, {ACT_NOTIFY_BC_DOWN}}, //FIXME +@@ -914,12 +916,6 @@ static void bchannel_down(struct bc_stat + + static void bchannel_up(struct bc_state *bcs) + { +- if (!(bcs->chstate & CHS_D_UP)) { +- dev_notice(bcs->cs->dev, "%s: D channel not up\n", __func__); +- bcs->chstate |= CHS_D_UP; +- gigaset_i4l_channel_cmd(bcs, ISDN_STAT_DCONN); +- } +- + if (bcs->chstate & CHS_B_UP) { + dev_notice(bcs->cs->dev, "%s: B channel already up\n", + __func__); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/isdn/hisax/hfc_pci.c linux-2.6.27.29-0.1.1/drivers/isdn/hisax/hfc_pci.c +--- linux-2.6.27.25-0.1.1/drivers/isdn/hisax/hfc_pci.c 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/isdn/hisax/hfc_pci.c 2009-08-27 12:44:24.000000000 +0100 +@@ -82,8 +82,9 @@ release_io_hfcpci(struct IsdnCardState * + Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); + pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, 0); /* disable memory mapped ports + busmaster */ + del_timer(&cs->hw.hfcpci.timer); +- kfree(cs->hw.hfcpci.share_start); +- cs->hw.hfcpci.share_start = NULL; ++ pci_free_consistent(cs->hw.hfcpci.dev, 0x8000, ++ cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma); ++ cs->hw.hfcpci.fifos = NULL; + iounmap((void *)cs->hw.hfcpci.pci_io); + } + +@@ -1663,8 +1664,19 @@ setup_hfcpci(struct IsdnCard *card) + dev_hfcpci); + i++; + if (tmp_hfcpci) { ++ dma_addr_t dma_mask = DMA_BIT_MASK(32) & ~0x7fffUL; + if (pci_enable_device(tmp_hfcpci)) + continue; ++ if (pci_set_dma_mask(tmp_hfcpci, dma_mask)) { ++ printk(KERN_WARNING ++ "HiSax hfc_pci: No suitable DMA available.\n"); ++ continue; ++ } ++ if (pci_set_consistent_dma_mask(tmp_hfcpci, dma_mask)) { ++ printk(KERN_WARNING ++ "HiSax hfc_pci: No suitable consistent DMA available.\n"); ++ continue; ++ } + pci_set_master(tmp_hfcpci); + if ((card->para[0]) && (card->para[0] != (tmp_hfcpci->resource[ 0].start & PCI_BASE_ADDRESS_IO_MASK))) + continue; +@@ -1693,22 +1705,29 @@ setup_hfcpci(struct IsdnCard *card) + printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n"); + return (0); + } ++ + /* Allocate memory for FIFOS */ +- /* Because the HFC-PCI needs a 32K physical alignment, we */ +- /* need to allocate the double mem and align the address */ +- if (!(cs->hw.hfcpci.share_start = kmalloc(65536, GFP_KERNEL))) { +- printk(KERN_WARNING "HFC-PCI: Error allocating memory for FIFO!\n"); ++ cs->hw.hfcpci.fifos = pci_alloc_consistent(cs->hw.hfcpci.dev, ++ 0x8000, &cs->hw.hfcpci.dma); ++ if (!cs->hw.hfcpci.fifos) { ++ printk(KERN_WARNING "HFC-PCI: Error allocating FIFO memory!\n"); ++ return 0; ++ } ++ if (cs->hw.hfcpci.dma & 0x7fff) { ++ printk(KERN_WARNING ++ "HFC-PCI: Error DMA memory not on 32K boundary (%lx)\n", ++ (u_long)cs->hw.hfcpci.dma); ++ pci_free_consistent(cs->hw.hfcpci.dev, 0x8000, ++ cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma); + return 0; + } +- cs->hw.hfcpci.fifos = (void *) +- (((ulong) cs->hw.hfcpci.share_start) & ~0x7FFF) + 0x8000; +- pci_write_config_dword(cs->hw.hfcpci.dev, 0x80, (u_int) virt_to_bus(cs->hw.hfcpci.fifos)); ++ pci_write_config_dword(cs->hw.hfcpci.dev, 0x80, (u32)cs->hw.hfcpci.dma); + cs->hw.hfcpci.pci_io = ioremap((ulong) cs->hw.hfcpci.pci_io, 256); + printk(KERN_INFO +- "HFC-PCI: defined at mem %p fifo %p(%#x) IRQ %d HZ %d\n", ++ "HFC-PCI: defined at mem %p fifo %p(%lx) IRQ %d HZ %d\n", + cs->hw.hfcpci.pci_io, + cs->hw.hfcpci.fifos, +- (u_int) virt_to_bus(cs->hw.hfcpci.fifos), ++ (u_long)cs->hw.hfcpci.dma, + cs->irq, HZ); + + spin_lock_irqsave(&cs->lock, flags); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/isdn/hisax/hisax.h linux-2.6.27.29-0.1.1/drivers/isdn/hisax/hisax.h +--- linux-2.6.27.25-0.1.1/drivers/isdn/hisax/hisax.h 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/isdn/hisax/hisax.h 2009-08-27 12:44:24.000000000 +0100 +@@ -694,7 +694,7 @@ struct hfcPCI_hw { + int nt_timer; + struct pci_dev *dev; + unsigned char *pci_io; /* start of PCI IO memory */ +- void *share_start; /* shared memory for Fifos start */ ++ dma_addr_t dma; /* dma handle for Fifos */ + void *fifos; /* FIFO memory */ + int last_bfifo_cnt[2]; /* marker saving last b-fifo frame count */ + struct timer_list timer; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/md/dm-mpath.c linux-2.6.27.29-0.1.1/drivers/md/dm-mpath.c +--- linux-2.6.27.25-0.1.1/drivers/md/dm-mpath.c 2009-08-05 09:49:38.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/md/dm-mpath.c 2009-08-27 12:44:15.000000000 +0100 +@@ -55,6 +55,8 @@ struct priority_group { + struct list_head pgpaths; + }; + ++#define FEATURE_NO_PARTITIONS 1 ++ + /* Multipath context */ + struct multipath { + struct list_head list; +@@ -79,6 +81,7 @@ struct multipath { + unsigned saved_queue_if_no_path;/* Saved state during suspension */ + unsigned pg_init_retries; /* Number of times to retry pg_init */ + unsigned pg_init_count; /* Number of times pg_init called */ ++ unsigned features; /* Additional selected features */ + + struct work_struct process_queued_ios; + struct list_head queued_ios; +@@ -462,9 +465,10 @@ static void process_queued_ios(struct wo + m->pg_init_count++; + m->pg_init_required = 0; + list_for_each_entry(tmp, &pgpath->pg->pgpaths, list) { +- /* Skip disabled paths */ +- if (!tmp->path.dev) ++ /* Skip disabled or failed paths */ ++ if (!tmp->path.dev || !tmp->is_active) + continue; ++ + queue_work(kmpath_handlerd, &tmp->activate_path); + m->pg_init_in_progress++; + } +@@ -565,6 +569,12 @@ static int parse_path_selector(struct ar + return -EINVAL; + } + ++ if (ps_argc > as->argc) { ++ dm_put_path_selector(pst); ++ ti->error = "not enough arguments for path selector"; ++ return -EINVAL; ++ } ++ + r = pst->create(&pg->ps, ps_argc, as->argv); + if (r) { + dm_put_path_selector(pst); +@@ -750,6 +760,11 @@ static int parse_hw_handler(struct arg_s + if (!hw_argc) + return 0; + ++ if (hw_argc > as->argc) { ++ ti->error = "not enough arguments for hardware handler"; ++ return -EINVAL; ++ } ++ + m->hw_handler_name = kstrdup(shift(as), GFP_KERNEL); + request_module("scsi_dh_%s", m->hw_handler_name); + if (scsi_dh_handler_exist(m->hw_handler_name) == 0) { +@@ -791,6 +806,10 @@ static int parse_features(struct arg_set + continue; + } + ++ if (!strnicmp(param_name, MESG_STR("no_partitions"))) { ++ m->features |= FEATURE_NO_PARTITIONS; ++ continue; ++ } + if (!strnicmp(param_name, MESG_STR("pg_init_retries")) && + (argc >= 1)) { + r = read_param(_params + 1, shift(as), +@@ -1310,11 +1329,14 @@ static int multipath_status(struct dm_ta + DMEMIT("2 %u %u ", m->queue_size, m->pg_init_count); + else { + DMEMIT("%u ", m->queue_if_no_path + +- (m->pg_init_retries > 0) * 2); ++ (m->pg_init_retries > 0) * 2 + ++ (m->features & FEATURE_NO_PARTITIONS)); + if (m->queue_if_no_path) + DMEMIT("queue_if_no_path "); + if (m->pg_init_retries) + DMEMIT("pg_init_retries %u ", m->pg_init_retries); ++ if (m->features & FEATURE_NO_PARTITIONS) ++ DMEMIT("no_partitions "); + } + + if (!m->hw_handler_name || type == STATUSTYPE_INFO) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/md/linear.c linux-2.6.27.29-0.1.1/drivers/md/linear.c +--- linux-2.6.27.25-0.1.1/drivers/md/linear.c 2009-08-05 09:42:57.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/md/linear.c 2009-08-27 12:44:15.000000000 +0100 +@@ -295,7 +295,8 @@ static int linear_add(mddev_t *mddev, md + mddev->private = newconf; + mddev->raid_disks++; + mddev->array_sectors = newconf->array_sectors; +- set_capacity(mddev->gendisk, mddev->array_sectors); ++ if (mddev->queue->end_sector == 0) ++ set_capacity(mddev->gendisk, mddev->array_sectors); + return 0; + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/md/md.c linux-2.6.27.29-0.1.1/drivers/md/md.c +--- linux-2.6.27.25-0.1.1/drivers/md/md.c 2009-08-27 12:59:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/md/md.c 2009-08-27 12:44:15.000000000 +0100 +@@ -287,6 +287,7 @@ static mddev_t * mddev_find(dev_t unit) + kfree(new); + return NULL; + } ++ new->queue->end_sector = 0; + /* Can be unlocked because the queue is new: no concurrency */ + queue_flag_set_unlocked(QUEUE_FLAG_CLUSTER, new->queue); + +@@ -1757,6 +1758,7 @@ static void md_update_sb(mddev_t * mddev + int sync_req; + int nospares = 0; + ++ mddev->utime = get_seconds(); + if (mddev->external) + return; + repeat: +@@ -1786,7 +1788,6 @@ repeat: + nospares = 0; + + sync_req = mddev->in_sync; +- mddev->utime = get_seconds(); + + /* If this is just a dirty<->clean transition, and the array is clean + * and 'events' is odd, we can roll back to the previous clean state */ +@@ -2140,6 +2141,25 @@ rdev_size_show(mdk_rdev_t *rdev, char *p + return sprintf(page, "%llu\n", (unsigned long long)rdev->size); + } + ++static int strict_blocks_to_sectors(const char *buf, sector_t *sectors) ++{ ++ unsigned long long blocks; ++ sector_t new; ++ ++ if (strict_strtoull(buf, 10, &blocks) < 0) ++ return -EINVAL; ++ ++ if (blocks & 1ULL << (8 * sizeof(blocks) - 1)) ++ return -EINVAL; /* sector conversion overflow */ ++ ++ new = blocks * 2; ++ if (new != blocks * 2) ++ return -EINVAL; /* unsigned long long to sector_t overflow */ ++ ++ *sectors = new; ++ return 0; ++} ++ + static int overlaps(sector_t s1, sector_t l1, sector_t s2, sector_t l2) + { + /* check if two start/length pairs overlap */ +@@ -3324,7 +3344,8 @@ suspend_lo_store(mddev_t *mddev, const c + char *e; + unsigned long long new = simple_strtoull(buf, &e, 10); + +- if (mddev->pers->quiesce == NULL) ++ if (mddev->pers == NULL || ++ mddev->pers->quiesce == NULL) + return -EINVAL; + if (buf == e || (*e && *e != '\n')) + return -EINVAL; +@@ -3352,7 +3373,8 @@ suspend_hi_store(mddev_t *mddev, const c + char *e; + unsigned long long new = simple_strtoull(buf, &e, 10); + +- if (mddev->pers->quiesce == NULL) ++ if (mddev->pers == NULL || ++ mddev->pers->quiesce == NULL) + return -EINVAL; + if (buf == e || (*e && *e != '\n')) + return -EINVAL; +@@ -3399,6 +3421,55 @@ static struct md_sysfs_entry md_reshape_ + __ATTR(reshape_position, S_IRUGO|S_IWUSR, reshape_position_show, + reshape_position_store); + ++static ssize_t ++array_size_show(mddev_t *mddev, char *page) ++{ ++ if (mddev->queue->end_sector) ++ return sprintf(page, "%llu\n", ++ (unsigned long long)mddev->queue->end_sector/2); ++ else ++ return sprintf(page, "default\n"); ++} ++ ++static ssize_t ++array_size_store(mddev_t *mddev, const char *buf, size_t len) ++{ ++ sector_t sectors; ++ ++ if (strncmp(buf, "default", 7) == 0) { ++ sectors = mddev->array_sectors; ++ ++ mddev->queue->end_sector = 0; ++ } else { ++ if (strict_blocks_to_sectors(buf, §ors) < 0) ++ return -EINVAL; ++ if (sectors < 2) ++ return -EINVAL; ++ if (mddev->pers && mddev->array_sectors < sectors) ++ return -E2BIG; ++ ++ mddev->queue->end_sector = sectors; ++ } ++ ++ set_capacity(mddev->gendisk, sectors); ++ if (mddev->pers) { ++ struct block_device *bdev = bdget_disk(mddev->gendisk, 0); ++ ++ if (bdev) { ++ mutex_lock(&bdev->bd_inode->i_mutex); ++ i_size_write(bdev->bd_inode, ++ (loff_t)sectors << 9); ++ mutex_unlock(&bdev->bd_inode->i_mutex); ++ bdput(bdev); ++ } ++ } ++ ++ return len; ++} ++ ++static struct md_sysfs_entry md_array_size = ++__ATTR(array_size, S_IRUGO|S_IWUSR, array_size_show, ++ array_size_store); + + static struct attribute *md_default_attrs[] = { + &md_level.attr, +@@ -3412,6 +3483,7 @@ static struct attribute *md_default_attr + &md_safe_delay.attr, + &md_array_state.attr, + &md_reshape_position.attr, ++ &md_array_size.attr, + NULL, + }; + +@@ -3723,7 +3795,15 @@ static int do_md_run(mddev_t * mddev) + err = mddev->pers->run(mddev); + if (err) + printk(KERN_ERR "md: pers->run() failed ...\n"); +- else if (mddev->pers->sync_request) { ++ else if (mddev->queue->end_sector && ++ mddev->queue->end_sector > mddev->array_sectors) { ++ printk(KERN_ERR ++ "md: invalid array_size %llu > default size %llu\n", ++ (unsigned long long)mddev->queue->end_sector / 2, ++ (unsigned long long)mddev->array_sectors / 2); ++ err = -EINVAL; ++ mddev->pers->stop(mddev); ++ } else if (mddev->pers->sync_request) { + err = bitmap_create(mddev); + if (err) { + printk(KERN_ERR "%s: failed to create bitmap (%d)\n", +@@ -3766,7 +3846,10 @@ static int do_md_run(mddev_t * mddev) + if (mddev->flags) + md_update_sb(mddev, 0); + +- set_capacity(disk, mddev->array_sectors); ++ if (mddev->queue->end_sector) ++ set_capacity(disk, mddev->queue->end_sector); ++ else ++ set_capacity(disk, mddev->array_sectors); + + /* If we call blk_queue_make_request here, it will + * re-initialise max_sectors etc which may have been +@@ -3809,6 +3892,7 @@ static int do_md_run(mddev_t * mddev) + md_wakeup_thread(mddev->thread); + md_wakeup_thread(mddev->sync_thread); /* possibly kick off a reshape */ + ++ revalidate_disk(mddev->gendisk); + mddev->changed = 1; + md_new_event(mddev); + sysfs_notify(&mddev->kobj, NULL, "array_state"); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/md/raid1.c linux-2.6.27.29-0.1.1/drivers/md/raid1.c +--- linux-2.6.27.25-0.1.1/drivers/md/raid1.c 2009-08-05 09:49:38.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/md/raid1.c 2009-08-27 12:44:15.000000000 +0100 +@@ -2108,12 +2108,14 @@ static int raid1_resize(mddev_t *mddev, + * worth it. + */ + mddev->array_sectors = sectors; +- set_capacity(mddev->gendisk, mddev->array_sectors); +- mddev->changed = 1; +- if (mddev->array_sectors / 2 > mddev->size && +- mddev->recovery_cp == MaxSector) { +- mddev->recovery_cp = mddev->size << 1; +- set_bit(MD_RECOVERY_NEEDED, &mddev->recovery); ++ if (mddev->queue->end_sector == 0) { ++ set_capacity(mddev->gendisk, mddev->array_sectors); ++ mddev->changed = 1; ++ if (mddev->array_sectors / 2 > mddev->size && ++ mddev->recovery_cp == MaxSector) { ++ mddev->recovery_cp = mddev->size << 1; ++ set_bit(MD_RECOVERY_NEEDED, &mddev->recovery); ++ } + } + mddev->size = mddev->array_sectors / 2; + mddev->resync_max_sectors = sectors; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/md/raid5.c linux-2.6.27.29-0.1.1/drivers/md/raid5.c +--- linux-2.6.27.25-0.1.1/drivers/md/raid5.c 2009-08-27 12:59:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/md/raid5.c 2009-08-27 12:44:15.000000000 +0100 +@@ -3651,6 +3651,7 @@ static int make_request(struct request_q + spin_unlock_irq(&conf->device_lock); + if (must_retry) { + release_stripe(sh); ++ schedule(); + goto retry; + } + } +@@ -4649,7 +4650,8 @@ static int raid5_resize(mddev_t *mddev, + sectors &= ~((sector_t)mddev->chunk_size/512 - 1); + mddev->array_sectors = sectors * (mddev->raid_disks + - conf->max_degraded); +- set_capacity(mddev->gendisk, mddev->array_sectors); ++ if (mddev->queue->end_sector == 0) ++ set_capacity(mddev->gendisk, mddev->array_sectors); + mddev->changed = 1; + if (sectors/2 > mddev->size && mddev->recovery_cp == MaxSector) { + mddev->recovery_cp = mddev->size << 1; +@@ -4787,11 +4789,13 @@ static void end_reshape(raid5_conf_t *co + if (!test_bit(MD_RECOVERY_INTR, &conf->mddev->recovery)) { + conf->mddev->array_sectors = 2 * conf->mddev->size * + (conf->raid_disks - conf->max_degraded); +- set_capacity(conf->mddev->gendisk, conf->mddev->array_sectors); ++ if (conf->mddev->queue->end_sector == 0) ++ set_capacity(conf->mddev->gendisk, ++ conf->mddev->array_sectors); + conf->mddev->changed = 1; + + bdev = bdget_disk(conf->mddev->gendisk, 0); +- if (bdev) { ++ if (bdev && conf->mddev->queue->end_sector == 0) { + mutex_lock(&bdev->bd_inode->i_mutex); + i_size_write(bdev->bd_inode, + (loff_t)conf->mddev->array_sectors << 9); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/bnx2.c linux-2.6.27.29-0.1.1/drivers/net/bnx2.c +--- linux-2.6.27.25-0.1.1/drivers/net/bnx2.c 2009-08-27 12:59:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/bnx2.c 2009-08-27 12:44:15.000000000 +0100 +@@ -2819,7 +2819,7 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2 + if (i == pages - 1) + frag_len -= 4; + +- skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); ++ skb_add_rx_frag(skb, i, rx_pg->page, 0, frag_len); + rx_pg->page = NULL; + + err = bnx2_alloc_rx_page(bp, rxr, +@@ -2833,7 +2833,6 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2 + } + + frag_size -= frag_len; +- skb_add_rx_frag(skb, i, rx_pg->page, 0, frag_len); + + pg_prod = NEXT_RX_BD(pg_prod); + pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons)); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/bonding/bond_sysfs.c linux-2.6.27.29-0.1.1/drivers/net/bonding/bond_sysfs.c +--- linux-2.6.27.25-0.1.1/drivers/net/bonding/bond_sysfs.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/bonding/bond_sysfs.c 2009-08-27 12:44:24.000000000 +0100 +@@ -1464,6 +1464,7 @@ int bond_create_sysfs(void) + printk(KERN_ERR + "network device named %s already exists in sysfs", + class_attr_bonding_masters.attr.name); ++ ret = 0; + } + + return ret; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/e1000e/82571.c linux-2.6.27.29-0.1.1/drivers/net/e1000e/82571.c +--- linux-2.6.27.25-0.1.1/drivers/net/e1000e/82571.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/e1000e/82571.c 2009-08-27 12:44:15.000000000 +0100 +@@ -68,6 +68,7 @@ static s32 e1000_setup_link_82571(struct + static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); + static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); + static s32 e1000_led_on_82574(struct e1000_hw *hw); ++static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); + + /** + * e1000_init_phy_params_82571 - Init PHY func ptrs. +@@ -206,6 +207,9 @@ static s32 e1000_init_mac_params_82571(s + struct e1000_hw *hw = &adapter->hw; + struct e1000_mac_info *mac = &hw->mac; + struct e1000_mac_operations *func = &mac->ops; ++ u32 swsm = 0; ++ u32 swsm2 = 0; ++ bool force_clear_smbi = false; + + /* Set media type */ + switch (adapter->pdev->device) { +@@ -269,6 +273,50 @@ static s32 e1000_init_mac_params_82571(s + break; + } + ++ /* ++ * Ensure that the inter-port SWSM.SMBI lock bit is clear before ++ * first NVM or PHY acess. This should be done for single-port ++ * devices, and for one port only on dual-port devices so that ++ * for those devices we can still use the SMBI lock to synchronize ++ * inter-port accesses to the PHY & NVM. ++ */ ++ switch (hw->mac.type) { ++ case e1000_82571: ++ case e1000_82572: ++ swsm2 = er32(SWSM2); ++ ++ if (!(swsm2 & E1000_SWSM2_LOCK)) { ++ /* Only do this for the first interface on this card */ ++ ew32(SWSM2, ++ swsm2 | E1000_SWSM2_LOCK); ++ force_clear_smbi = true; ++ } else ++ force_clear_smbi = false; ++ break; ++ default: ++ force_clear_smbi = true; ++ break; ++ } ++ ++ if (force_clear_smbi) { ++ /* Make sure SWSM.SMBI is clear */ ++ swsm = er32(SWSM); ++ if (swsm & E1000_SWSM_SMBI) { ++ /* This bit should not be set on a first interface, and ++ * indicates that the bootagent or EFI code has ++ * improperly left this bit enabled ++ */ ++ hw_dbg(hw, "Please update your 82571 Bootagent\n"); ++ } ++ ew32(SWSM, swsm & ~E1000_SWSM_SMBI); ++ } ++ ++ /* ++ * Initialze device specific counter of SMBI acquisition ++ * timeouts. ++ */ ++ hw->dev_spec.e82571.smb_counter = 0; ++ + return 0; + } + +@@ -402,11 +450,37 @@ static s32 e1000_get_phy_id_82571(struct + static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) + { + u32 swsm; +- s32 timeout = hw->nvm.word_size + 1; ++ s32 sw_timeout = hw->nvm.word_size + 1; ++ s32 fw_timeout = hw->nvm.word_size + 1; + s32 i = 0; + ++ /* ++ * If we have timedout 3 times on trying to acquire ++ * the inter-port SMBI semaphore, there is old code ++ * operating on the other port, and it is not ++ * releasing SMBI. Modify the number of times that ++ * we try for the semaphore to interwork with this ++ * older code. ++ */ ++ if (hw->dev_spec.e82571.smb_counter > 2) ++ sw_timeout = 1; ++ ++ /* Get the SW semaphore */ ++ while (i < sw_timeout) { ++ swsm = er32(SWSM); ++ if (!(swsm & E1000_SWSM_SMBI)) ++ break; ++ ++ udelay(50); ++ i++; ++ } ++ ++ if (i == sw_timeout) { ++ hw_dbg(hw, "Driver can't access device - SMBI bit is set.\n"); ++ hw->dev_spec.e82571.smb_counter++; ++ } + /* Get the FW semaphore. */ +- for (i = 0; i < timeout; i++) { ++ for (i = 0; i < fw_timeout; i++) { + swsm = er32(SWSM); + ew32(SWSM, swsm | E1000_SWSM_SWESMBI); + +@@ -417,9 +491,9 @@ static s32 e1000_get_hw_semaphore_82571( + udelay(50); + } + +- if (i == timeout) { ++ if (i == fw_timeout) { + /* Release semaphores */ +- e1000e_put_hw_semaphore(hw); ++ e1000_put_hw_semaphore_82571(hw); + hw_dbg(hw, "Driver can't access the NVM\n"); + return -E1000_ERR_NVM; + } +@@ -438,9 +512,7 @@ static void e1000_put_hw_semaphore_82571 + u32 swsm; + + swsm = er32(SWSM); +- +- swsm &= ~E1000_SWSM_SWESMBI; +- ++ swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); + ew32(SWSM, swsm); + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/e1000e/defines.h linux-2.6.27.29-0.1.1/drivers/net/e1000e/defines.h +--- linux-2.6.27.25-0.1.1/drivers/net/e1000e/defines.h 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/e1000e/defines.h 2009-08-27 12:44:15.000000000 +0100 +@@ -359,6 +359,8 @@ + #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ + #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ + ++#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ ++ + /* Interrupt Cause Read */ + #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ + #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/e1000e/hw.h linux-2.6.27.29-0.1.1/drivers/net/e1000e/hw.h +--- linux-2.6.27.25-0.1.1/drivers/net/e1000e/hw.h 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/e1000e/hw.h 2009-08-27 12:44:15.000000000 +0100 +@@ -209,6 +209,7 @@ enum e1e_registers { + E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */ + E1000_SWSM = 0x05B50, /* SW Semaphore */ + E1000_FWSM = 0x05B54, /* FW Semaphore */ ++ E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */ + E1000_HICR = 0x08F00, /* Host Interface Control */ + }; + +@@ -856,6 +857,7 @@ struct e1000_fc_info { + struct e1000_dev_spec_82571 { + bool laa_is_present; + bool alt_mac_addr_is_present; ++ u32 smb_counter; + }; + + struct e1000_shadow_ram { +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/e100.c linux-2.6.27.29-0.1.1/drivers/net/e100.c +--- linux-2.6.27.25-0.1.1/drivers/net/e100.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/e100.c 2009-08-27 12:44:15.000000000 +0100 +@@ -1840,6 +1840,9 @@ static int e100_rx_indicate(struct nic * + + if (ioread8(&nic->csr->scb.status) & rus_no_res) + nic->ru_running = RU_SUSPENDED; ++ pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr, ++ sizeof(struct rfd), ++ PCI_DMA_BIDIRECTIONAL); + return -ENODATA; + } + +@@ -2322,7 +2325,8 @@ static int e100_set_wol(struct net_devic + { + struct nic *nic = netdev_priv(netdev); + +- if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0) ++ if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) || ++ !device_can_wakeup(&nic->pdev->dev)) + return -EOPNOTSUPP; + + if(wol->wolopts) +@@ -2330,6 +2334,8 @@ static int e100_set_wol(struct net_devic + else + nic->flags &= ~wol_magic; + ++ device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts); ++ + e100_exec_cb(nic, NULL, e100_configure); + + return 0; +@@ -2734,8 +2740,10 @@ static int __devinit e100_probe(struct p + + /* Wol magic packet can be enabled from eeprom */ + if((nic->mac >= mac_82558_D101_A4) && +- (nic->eeprom[eeprom_id] & eeprom_id_wol)) ++ (nic->eeprom[eeprom_id] & eeprom_id_wol)) { + nic->flags |= wol_magic; ++ device_set_wakeup_enable(&pdev->dev, true); ++ } + + /* ack any pending wake events, disable PME */ + pci_pme_active(pdev, false); +@@ -2794,11 +2802,10 @@ static int e100_suspend(struct pci_dev * + pci_save_state(pdev); + + if ((nic->flags & wol_magic) | e100_asf(nic)) { +- pci_enable_wake(pdev, PCI_D3hot, 1); +- pci_enable_wake(pdev, PCI_D3cold, 1); ++ if (pci_enable_wake(pdev, PCI_D3cold, true)) ++ pci_enable_wake(pdev, PCI_D3hot, true); + } else { +- pci_enable_wake(pdev, PCI_D3hot, 0); +- pci_enable_wake(pdev, PCI_D3cold, 0); ++ pci_enable_wake(pdev, PCI_D3hot, false); + } + + pci_disable_device(pdev); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/hamradio/6pack.c linux-2.6.27.29-0.1.1/drivers/net/hamradio/6pack.c +--- linux-2.6.27.25-0.1.1/drivers/net/hamradio/6pack.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/hamradio/6pack.c 2009-08-27 12:44:15.000000000 +0100 +@@ -397,13 +397,14 @@ static DEFINE_RWLOCK(disc_data_lock); + + static struct sixpack *sp_get(struct tty_struct *tty) + { ++ unsigned long flags; + struct sixpack *sp; + +- read_lock(&disc_data_lock); ++ read_lock_irqsave(&disc_data_lock, flags); + sp = tty->disc_data; + if (sp) + atomic_inc(&sp->refcnt); +- read_unlock(&disc_data_lock); ++ read_unlock_irqrestore(&disc_data_lock, flags); + + return sp; + } +@@ -687,12 +688,13 @@ out: + */ + static void sixpack_close(struct tty_struct *tty) + { ++ unsigned long flags; + struct sixpack *sp; + +- write_lock(&disc_data_lock); ++ write_lock_irqsave(&disc_data_lock, flags); + sp = tty->disc_data; + tty->disc_data = NULL; +- write_unlock(&disc_data_lock); ++ write_unlock_irqrestore(&disc_data_lock, flags); + if (!sp) + return; + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/hamradio/mkiss.c linux-2.6.27.29-0.1.1/drivers/net/hamradio/mkiss.c +--- linux-2.6.27.25-0.1.1/drivers/net/hamradio/mkiss.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/hamradio/mkiss.c 2009-08-27 12:44:15.000000000 +0100 +@@ -246,15 +246,16 @@ static int kiss_esc_crc(unsigned char *s + /* Send one completely decapsulated AX.25 packet to the AX.25 layer. */ + static void ax_bump(struct mkiss *ax) + { ++ unsigned long flags; + struct sk_buff *skb; + int count; + +- spin_lock_bh(&ax->buflock); ++ spin_lock_irqsave(&ax->buflock, flags); + if (ax->rbuff[0] > 0x0f) { + if (ax->rbuff[0] & 0x80) { + if (check_crc_16(ax->rbuff, ax->rcount) < 0) { + ax->stats.rx_errors++; +- spin_unlock_bh(&ax->buflock); ++ spin_unlock_irqrestore(&ax->buflock, flags); + + return; + } +@@ -269,7 +270,7 @@ static void ax_bump(struct mkiss *ax) + } else if (ax->rbuff[0] & 0x20) { + if (check_crc_flex(ax->rbuff, ax->rcount) < 0) { + ax->stats.rx_errors++; +- spin_unlock_bh(&ax->buflock); ++ spin_unlock_irqrestore(&ax->buflock, flags); + return; + } + if (ax->crcmode != CRC_MODE_FLEX && ax->crcauto) { +@@ -296,7 +297,7 @@ static void ax_bump(struct mkiss *ax) + printk(KERN_ERR "mkiss: %s: memory squeeze, dropping packet.\n", + ax->dev->name); + ax->stats.rx_dropped++; +- spin_unlock_bh(&ax->buflock); ++ spin_unlock_irqrestore(&ax->buflock, flags); + return; + } + +@@ -306,11 +307,13 @@ static void ax_bump(struct mkiss *ax) + ax->dev->last_rx = jiffies; + ax->stats.rx_packets++; + ax->stats.rx_bytes += count; +- spin_unlock_bh(&ax->buflock); ++ spin_unlock_irqrestore(&ax->buflock, flags); + } + + static void kiss_unesc(struct mkiss *ax, unsigned char s) + { ++ unsigned long flags; ++ + switch (s) { + case END: + /* drop keeptest bit = VSV */ +@@ -337,18 +340,18 @@ static void kiss_unesc(struct mkiss *ax, + break; + } + +- spin_lock_bh(&ax->buflock); ++ spin_lock_irqsave(&ax->buflock, flags); + if (!test_bit(AXF_ERROR, &ax->flags)) { + if (ax->rcount < ax->buffsize) { + ax->rbuff[ax->rcount++] = s; +- spin_unlock_bh(&ax->buflock); ++ spin_unlock_irqrestore(&ax->buflock, flags); + return; + } + + ax->stats.rx_over_errors++; + set_bit(AXF_ERROR, &ax->flags); + } +- spin_unlock_bh(&ax->buflock); ++ spin_unlock_irqrestore(&ax->buflock, flags); + } + + static int ax_set_mac_address(struct net_device *dev, void *addr) +@@ -370,6 +373,7 @@ static void ax_changedmtu(struct mkiss * + { + struct net_device *dev = ax->dev; + unsigned char *xbuff, *rbuff, *oxbuff, *orbuff; ++ unsigned long flags; + int len; + + len = dev->mtu * 2; +@@ -395,7 +399,7 @@ static void ax_changedmtu(struct mkiss * + return; + } + +- spin_lock_bh(&ax->buflock); ++ spin_lock_irqsave(&ax->buflock, flags); + + oxbuff = ax->xbuff; + ax->xbuff = xbuff; +@@ -426,7 +430,7 @@ static void ax_changedmtu(struct mkiss * + ax->mtu = dev->mtu + 73; + ax->buffsize = len; + +- spin_unlock_bh(&ax->buflock); ++ spin_unlock_irqrestore(&ax->buflock, flags); + + kfree(oxbuff); + kfree(orbuff); +@@ -436,6 +440,7 @@ static void ax_changedmtu(struct mkiss * + static void ax_encaps(struct net_device *dev, unsigned char *icp, int len) + { + struct mkiss *ax = netdev_priv(dev); ++ unsigned long flags; + unsigned char *p; + int actual, count; + +@@ -452,7 +457,7 @@ static void ax_encaps(struct net_device + + p = icp; + +- spin_lock_bh(&ax->buflock); ++ spin_lock_irqsave(&ax->buflock, flags); + if ((*p & 0x0f) != 0) { + /* Configuration Command (kissparms(1). + * Protocol spec says: never append CRC. +@@ -482,7 +487,7 @@ static void ax_encaps(struct net_device + ax->crcauto = (cmd ? 0 : 1); + printk(KERN_INFO "mkiss: %s: crc mode %s %d\n", ax->dev->name, (len) ? "set to" : "is", cmd); + } +- spin_unlock_bh(&ax->buflock); ++ spin_unlock_irqrestore(&ax->buflock, flags); + netif_start_queue(dev); + + return; +@@ -515,7 +520,7 @@ static void ax_encaps(struct net_device + count = kiss_esc(p, (unsigned char *)ax->xbuff, len); + } + } +- spin_unlock_bh(&ax->buflock); ++ spin_unlock_irqrestore(&ax->buflock, flags); + + set_bit(TTY_DO_WRITE_WAKEUP, &ax->tty->flags); + actual = ax->tty->ops->write(ax->tty, ax->xbuff, count); +@@ -711,13 +716,14 @@ static DEFINE_RWLOCK(disc_data_lock); + + static struct mkiss *mkiss_get(struct tty_struct *tty) + { ++ unsigned long flags; + struct mkiss *ax; + +- read_lock(&disc_data_lock); ++ read_lock_irqsave(&disc_data_lock, flags); + ax = tty->disc_data; + if (ax) + atomic_inc(&ax->refcnt); +- read_unlock(&disc_data_lock); ++ read_unlock_irqrestore(&disc_data_lock, flags); + + return ax; + } +@@ -816,12 +822,13 @@ out: + + static void mkiss_close(struct tty_struct *tty) + { ++ unsigned long flags; + struct mkiss *ax; + +- write_lock(&disc_data_lock); ++ write_lock_irqsave(&disc_data_lock, flags); + ax = tty->disc_data; + tty->disc_data = NULL; +- write_unlock(&disc_data_lock); ++ write_unlock_irqrestore(&disc_data_lock, flags); + + if (!ax) + return; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/ppp_async.c linux-2.6.27.29-0.1.1/drivers/net/ppp_async.c +--- linux-2.6.27.25-0.1.1/drivers/net/ppp_async.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/ppp_async.c 2009-08-27 12:44:15.000000000 +0100 +@@ -132,13 +132,15 @@ static DEFINE_RWLOCK(disc_data_lock); + + static struct asyncppp *ap_get(struct tty_struct *tty) + { ++ unsigned long flags; + struct asyncppp *ap; + +- read_lock(&disc_data_lock); ++ read_lock_irqsave(&disc_data_lock, flags); + ap = tty->disc_data; + if (ap != NULL) + atomic_inc(&ap->refcnt); +- read_unlock(&disc_data_lock); ++ read_unlock_irqrestore(&disc_data_lock, flags); ++ + return ap; + } + +@@ -212,12 +214,13 @@ ppp_asynctty_open(struct tty_struct *tty + static void + ppp_asynctty_close(struct tty_struct *tty) + { ++ unsigned long flags; + struct asyncppp *ap; + +- write_lock_irq(&disc_data_lock); ++ write_lock_irqsave(&disc_data_lock, flags); + ap = tty->disc_data; + tty->disc_data = NULL; +- write_unlock_irq(&disc_data_lock); ++ write_unlock_irqrestore(&disc_data_lock, flags); + if (!ap) + return; + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/ppp_synctty.c linux-2.6.27.29-0.1.1/drivers/net/ppp_synctty.c +--- linux-2.6.27.25-0.1.1/drivers/net/ppp_synctty.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/ppp_synctty.c 2009-08-27 12:44:15.000000000 +0100 +@@ -182,13 +182,15 @@ static DEFINE_RWLOCK(disc_data_lock); + + static struct syncppp *sp_get(struct tty_struct *tty) + { ++ unsigned long flags; + struct syncppp *ap; + +- read_lock(&disc_data_lock); ++ read_lock_irqsave(&disc_data_lock, flags); + ap = tty->disc_data; + if (ap != NULL) + atomic_inc(&ap->refcnt); +- read_unlock(&disc_data_lock); ++ read_unlock_irqrestore(&disc_data_lock, flags); ++ + return ap; + } + +@@ -259,12 +261,13 @@ ppp_sync_open(struct tty_struct *tty) + static void + ppp_sync_close(struct tty_struct *tty) + { ++ unsigned long flags; + struct syncppp *ap; + +- write_lock_irq(&disc_data_lock); ++ write_lock_irqsave(&disc_data_lock, flags); + ap = tty->disc_data; + tty->disc_data = NULL; +- write_unlock_irq(&disc_data_lock); ++ write_unlock_irqrestore(&disc_data_lock, flags); + if (!ap) + return; + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/r8169.c linux-2.6.27.29-0.1.1/drivers/net/r8169.c +--- linux-2.6.27.25-0.1.1/drivers/net/r8169.c 2009-08-27 12:59:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/r8169.c 2009-08-27 12:44:15.000000000 +0100 +@@ -3133,54 +3133,64 @@ static irqreturn_t rtl8169_interrupt(int + int handled = 0; + int status; + ++ /* loop handling interrupts until we have no new ones or ++ * we hit a invalid/hotplug case. ++ */ + status = RTL_R16(IntrStatus); ++ while (status && status != 0xffff) { ++ handled = 1; + +- /* hotplug/major error/no more work/shared irq */ +- if ((status == 0xffff) || !status) +- goto out; +- +- handled = 1; ++ /* Handle all of the error cases first. These will reset ++ * the chip, so just exit the loop. ++ */ ++ if (unlikely(!netif_running(dev))) { ++ rtl8169_asic_down(ioaddr); ++ break; ++ } + +- if (unlikely(!netif_running(dev))) { +- rtl8169_asic_down(ioaddr); +- goto out; +- } ++ /* Work around for rx fifo overflow */ ++ if (unlikely(status & RxFIFOOver) && ++ (tp->mac_version == RTL_GIGA_MAC_VER_11)) { ++ netif_stop_queue(dev); ++ rtl8169_tx_timeout(dev); ++ break; ++ } + +- status &= tp->intr_mask; +- RTL_W16(IntrStatus, +- (status & RxFIFOOver) ? (status | RxOverflow) : status); ++ if (unlikely(status & SYSErr)) { ++ rtl8169_pcierr_interrupt(dev); ++ break; ++ } + +- if (!(status & tp->intr_event)) +- goto out; ++ if (status & LinkChg) ++ rtl8169_check_link_status(dev, tp, ioaddr); + +- /* Work around for rx fifo overflow */ +- if (unlikely(status & RxFIFOOver) && +- (tp->mac_version == RTL_GIGA_MAC_VER_11)) { +- netif_stop_queue(dev); +- rtl8169_tx_timeout(dev); +- goto out; +- } ++ /* We need to see the lastest version of tp->intr_mask to ++ * avoid ignoring an MSI interrupt and having to wait for ++ * another event which may never come. ++ */ ++ smp_rmb(); ++ if (status & tp->intr_mask & tp->napi_event) { ++ RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); ++ tp->intr_mask = ~tp->napi_event; ++ ++ if (likely(napi_schedule_prep(&tp->napi))) ++ __napi_schedule(&tp->napi); ++ else if (netif_msg_intr(tp)) { ++ printk(KERN_INFO "%s: interrupt %04x in poll\n", ++ dev->name, status); ++ } ++ } + +- if (unlikely(status & SYSErr)) { +- rtl8169_pcierr_interrupt(dev); +- goto out; ++ /* We only get a new MSI interrupt when all active irq ++ * sources on the chip have been acknowledged. So, ack ++ * everything we've seen and check if new sources have become ++ * active to avoid blocking all interrupts from the chip. ++ */ ++ RTL_W16(IntrStatus, ++ (status & RxFIFOOver) ? (status | RxOverflow) : status); ++ status = RTL_R16(IntrStatus); + } + +- if (status & LinkChg) +- rtl8169_check_link_status(dev, tp, ioaddr); +- +- if (status & tp->napi_event) { +- RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); +- tp->intr_mask = ~tp->napi_event; +- +- if (likely(netif_rx_schedule_prep(dev, &tp->napi))) +- __netif_rx_schedule(dev, &tp->napi); +- else if (netif_msg_intr(tp)) { +- printk(KERN_INFO "%s: interrupt %04x in poll\n", +- dev->name, status); +- } +- } +-out: + return IRQ_RETVAL(handled); + } + +@@ -3196,13 +3206,15 @@ static int rtl8169_poll(struct napi_stru + + if (work_done < budget) { + netif_rx_complete(dev, napi); +- tp->intr_mask = 0xffff; +- /* +- * 20040426: the barrier is not strictly required but the +- * behavior of the irq handler could be less predictable +- * without it. Btw, the lack of flush for the posted pci +- * write is safe - FR ++ ++ /* We need for force the visibility of tp->intr_mask ++ * for other CPUs, as we can loose an MSI interrupt ++ * and potentially wait for a retransmit timeout if we don't. ++ * The posted write to IntrMask is safe, as it will ++ * eventually make it to the chip and we won't loose anything ++ * until it does. + */ ++ tp->intr_mask = 0xffff; + smp_wmb(); + RTL_W16(IntrMask, tp->intr_event); + } +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/sfc/falcon.c linux-2.6.27.29-0.1.1/drivers/net/sfc/falcon.c +--- linux-2.6.27.25-0.1.1/drivers/net/sfc/falcon.c 2009-08-05 09:42:57.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/sfc/falcon.c 2009-08-27 12:44:15.000000000 +0100 +@@ -36,12 +36,18 @@ + + /** + * struct falcon_nic_data - Falcon NIC state ++ * @sram_cfg: SRAM configuration value ++ * @tx_dc_base: Base address in SRAM of TX queue descriptor caches ++ * @rx_dc_base: Base address in SRAM of RX queue descriptor caches + * @next_buffer_table: First available buffer table id + * @resources: Resource information for driverlink client + * @pci_dev2: The secondary PCI device if present + * @i2c_data: Operations and state for I2C bit-bashing algorithm + */ + struct falcon_nic_data { ++ int sram_cfg; ++ unsigned tx_dc_base; ++ unsigned rx_dc_base; + #ifndef CONFIG_SFC_DRIVERLINK + unsigned next_buffer_table; + #else +@@ -69,11 +75,11 @@ static int disable_dma_stats; + */ + #define TX_DC_ENTRIES 16 + #define TX_DC_ENTRIES_ORDER 0 +-#define TX_DC_BASE 0x130000 ++#define TX_DC_INTERNAL_BASE 0x130000 + + #define RX_DC_ENTRIES 64 + #define RX_DC_ENTRIES_ORDER 2 +-#define RX_DC_BASE 0x100000 ++#define RX_DC_INTERNAL_BASE 0x100000 + + /* RX FIFO XOFF watermark + * +@@ -454,9 +460,17 @@ void falcon_push_buffers(struct efx_tx_q + int falcon_probe_tx(struct efx_tx_queue *tx_queue) + { + struct efx_nic *efx = tx_queue->efx; +- return falcon_alloc_special_buffer(efx, &tx_queue->txd, +- FALCON_TXD_RING_SIZE * +- sizeof(efx_qword_t)); ++ int rc = falcon_alloc_special_buffer(efx, &tx_queue->txd, ++ FALCON_TXD_RING_SIZE * ++ sizeof(efx_qword_t)); ++#ifdef CONFIG_SFC_DRIVERLINK ++ if (rc == 0) { ++ struct falcon_nic_data *nic_data = efx->nic_data; ++ nic_data->resources.txq_min = max(nic_data->resources.txq_min, ++ (unsigned)tx_queue->queue + 1); ++ } ++#endif ++ return rc; + } + + int falcon_init_tx(struct efx_tx_queue *tx_queue) +@@ -643,9 +657,17 @@ void falcon_notify_rx_desc(struct efx_rx + int falcon_probe_rx(struct efx_rx_queue *rx_queue) + { + struct efx_nic *efx = rx_queue->efx; +- return falcon_alloc_special_buffer(efx, &rx_queue->rxd, +- FALCON_RXD_RING_SIZE * +- sizeof(efx_qword_t)); ++ int rc = falcon_alloc_special_buffer(efx, &rx_queue->rxd, ++ FALCON_RXD_RING_SIZE * ++ sizeof(efx_qword_t)); ++#ifdef CONFIG_SFC_DRIVERLINK ++ if (rc == 0) { ++ struct falcon_nic_data *nic_data = efx->nic_data; ++ nic_data->resources.rxq_min = max(nic_data->resources.rxq_min, ++ (unsigned)rx_queue->queue + 1); ++ } ++#endif ++ return rc; + } + + int falcon_init_rx(struct efx_rx_queue *rx_queue) +@@ -1276,9 +1298,18 @@ int falcon_probe_eventq(struct efx_chann + { + struct efx_nic *efx = channel->efx; + unsigned int evq_size; ++ int rc; + + evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t); +- return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size); ++ rc = falcon_alloc_special_buffer(efx, &channel->eventq, evq_size); ++#ifdef CONFIG_SFC_DRIVERLINK ++ if (rc == 0) { ++ struct falcon_nic_data *nic_data = efx->nic_data; ++ nic_data->resources.evq_int_min = max(nic_data->resources.evq_int_min, ++ (unsigned)channel->evqnum + 1); ++ } ++#endif ++ return rc; + } + + int falcon_init_eventq(struct efx_channel *channel) +@@ -2285,19 +2316,22 @@ fail5: + */ + static int falcon_reset_sram(struct efx_nic *efx) + { ++ struct falcon_nic_data *nic_data = efx->nic_data; + efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; +- int count; ++ int count, onchip, sram_cfg_val; + + /* Set the SRAM wake/sleep GPIO appropriately. */ ++ onchip = (nic_data->sram_cfg == SRM_NB_BSZ_ONCHIP_ONLY); + falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER); + EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1); +- EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1); ++ EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, onchip); + falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER); + + /* Initiate SRAM reset */ ++ sram_cfg_val = onchip ? 0 : nic_data->sram_cfg; + EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, + SRAM_OOB_BT_INIT_EN, 1, +- SRM_NUM_BANKS_AND_BANK_SIZE, 0); ++ SRM_NUM_BANKS_AND_BANK_SIZE, sram_cfg_val); + falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER); + + /* Wait for SRAM reset to complete */ +@@ -2324,12 +2358,14 @@ static int falcon_reset_sram(struct efx_ + /* Extract non-volatile configuration */ + static int falcon_probe_nvconfig(struct efx_nic *efx) + { ++ struct falcon_nic_data *nic_data = efx->nic_data; + struct falcon_nvconfig *nvconfig; + efx_oword_t nic_stat; + int device_id; + unsigned addr_len; + size_t offset, len; + int magic_num, struct_ver, board_rev; ++ bool onchip_sram; + int rc; + + /* Find the boot device. */ +@@ -2370,18 +2406,41 @@ static int falcon_probe_nvconfig(struct + efx->phy_type = PHY_TYPE_NONE; + efx->mii.phy_id = PHY_ADDR_INVALID; + board_rev = 0; ++ onchip_sram = true; + } else { + struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2; + + efx->phy_type = v2->port0_phy_type; + efx->mii.phy_id = v2->port0_phy_addr; + board_rev = le16_to_cpu(v2->board_revision); ++#ifdef CONFIG_SFC_DRIVERLINK ++ onchip_sram = EFX_OWORD_FIELD(nvconfig->nic_stat_reg, ++ ONCHIP_SRAM); ++#else ++ /* We have no use for external SRAM */ ++ onchip_sram = true; ++#endif + } + + EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id); + + efx_set_board_info(efx, board_rev); + ++ /* Read the SRAM configuration. The register is initialised ++ * automatically but might may been reset since boot. ++ */ ++ if (onchip_sram) { ++ nic_data->sram_cfg = SRM_NB_BSZ_ONCHIP_ONLY; ++ } else { ++ nic_data->sram_cfg = ++ EFX_OWORD_FIELD(nvconfig->srm_cfg_reg, ++ SRM_NUM_BANKS_AND_BANK_SIZE); ++ WARN_ON(nic_data->sram_cfg == SRM_NB_BSZ_RESERVED); ++ /* Replace invalid setting with the smallest defaults */ ++ if (nic_data->sram_cfg == SRM_NB_BSZ_DEFAULT) ++ nic_data->sram_cfg = SRM_NB_BSZ_1BANKS_2M; ++ } ++ + out: + kfree(nvconfig); + return rc; +@@ -2392,9 +2451,9 @@ static int falcon_probe_nvconfig(struct + * should live. */ + static int falcon_dimension_resources(struct efx_nic *efx) + { ++ struct falcon_nic_data *nic_data = efx->nic_data; + #ifdef CONFIG_SFC_DRIVERLINK + unsigned internal_dcs_entries; +- struct falcon_nic_data *nic_data = efx->nic_data; + struct efx_dl_falcon_resources *res = &nic_data->resources; + + /* Fill out the driverlink resource list */ +@@ -2427,16 +2486,64 @@ static int falcon_dimension_resources(st + break; + } + +- /* Internal SRAM only for now */ +- res->rxq_lim = internal_dcs_entries / RX_DC_ENTRIES; +- res->txq_lim = internal_dcs_entries / TX_DC_ENTRIES; +- res->buffer_table_lim = 8192; ++ if (nic_data->sram_cfg == SRM_NB_BSZ_ONCHIP_ONLY) { ++ res->rxq_lim = internal_dcs_entries / RX_DC_ENTRIES; ++ res->txq_lim = internal_dcs_entries / TX_DC_ENTRIES; ++ res->buffer_table_lim = 8192; ++ nic_data->tx_dc_base = TX_DC_INTERNAL_BASE; ++ nic_data->rx_dc_base = RX_DC_INTERNAL_BASE; ++ } else { ++ unsigned sram_bytes, vnic_bytes, max_vnics, n_vnics, dcs; ++ ++ /* Determine how much SRAM we have to play with. We have ++ * to fit buffer table and descriptor caches in. ++ */ ++ switch (nic_data->sram_cfg) { ++ case SRM_NB_BSZ_1BANKS_2M: ++ default: ++ sram_bytes = 2 * 1024 * 1024; ++ break; ++ case SRM_NB_BSZ_1BANKS_4M: ++ case SRM_NB_BSZ_2BANKS_4M: ++ sram_bytes = 4 * 1024 * 1024; ++ break; ++ case SRM_NB_BSZ_1BANKS_8M: ++ case SRM_NB_BSZ_2BANKS_8M: ++ sram_bytes = 8 * 1024 * 1024; ++ break; ++ case SRM_NB_BSZ_2BANKS_16M: ++ sram_bytes = 16 * 1024 * 1024; ++ break; ++ } ++ /* For each VNIC allow at least 512 buffer table entries ++ * and descriptor cache for an rxq and txq. Buffer table ++ * space for evqs and dmaqs is relatively trivial, so not ++ * considered in this calculation. ++ */ ++ vnic_bytes = 512 * 8 + RX_DC_ENTRIES * 8 + TX_DC_ENTRIES * 8; ++ max_vnics = sram_bytes / vnic_bytes; ++ for (n_vnics = 1; n_vnics < res->evq_timer_min + max_vnics;) ++ n_vnics *= 2; ++ res->rxq_lim = n_vnics; ++ res->txq_lim = n_vnics; ++ ++ dcs = n_vnics * TX_DC_ENTRIES * 8; ++ nic_data->tx_dc_base = sram_bytes - dcs; ++ dcs = n_vnics * RX_DC_ENTRIES * 8; ++ nic_data->rx_dc_base = nic_data->tx_dc_base - dcs; ++ res->buffer_table_lim = nic_data->rx_dc_base / 8; ++ } + + if (FALCON_IS_DUAL_FUNC(efx)) + res->flags |= EFX_DL_FALCON_DUAL_FUNC; + + if (EFX_INT_MODE_USE_MSI(efx)) + res->flags |= EFX_DL_FALCON_USE_MSI; ++#else ++ /* We ignore external SRAM */ ++ EFX_BUG_ON_PARANOID(nic_data->sram_cfg != SRM_NB_BSZ_ONCHIP_ONLY); ++ nic_data->tx_dc_base = TX_DC_INTERNAL_BASE; ++ nic_data->rx_dc_base = RX_DC_INTERNAL_BASE; + #endif + + return 0; +@@ -2586,6 +2693,7 @@ int falcon_probe_nic(struct efx_nic *efx + */ + int falcon_init_nic(struct efx_nic *efx) + { ++ struct falcon_nic_data *nic_data = efx->nic_data; + efx_oword_t temp; + unsigned thresh; + int rc; +@@ -2599,9 +2707,10 @@ int falcon_init_nic(struct efx_nic *efx) + ADR_REGION3, (3 << 16)); + falcon_write(efx, &temp, ADR_REGION_REG_KER); + +- /* Use on-chip SRAM */ ++ /* Use on-chip SRAM if wanted. */ + falcon_read(efx, &temp, NIC_STAT_REG); +- EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1); ++ EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, ++ nic_data->sram_cfg == SRM_NB_BSZ_ONCHIP_ONLY); + falcon_write(efx, &temp, NIC_STAT_REG); + + /* Set buffer table mode */ +@@ -2613,9 +2722,9 @@ int falcon_init_nic(struct efx_nic *efx) + return rc; + + /* Set positions of descriptor caches in SRAM. */ +- EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8); ++ EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, nic_data->tx_dc_base / 8); + falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER); +- EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8); ++ EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, nic_data->rx_dc_base / 8); + falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER); + + /* Set TX descriptor cache size. */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/sky2.c linux-2.6.27.29-0.1.1/drivers/net/sky2.c +--- linux-2.6.27.25-0.1.1/drivers/net/sky2.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/sky2.c 2009-08-27 12:44:15.000000000 +0100 +@@ -2389,7 +2389,7 @@ static int sky2_status_intr(struct sky2_ + if (likely(status >> 16 == (status & 0xffff))) { + skb = sky2->rx_ring[sky2->rx_next].skb; + skb->ip_summed = CHECKSUM_COMPLETE; +- skb->csum = status & 0xffff; ++ skb->csum = le16_to_cpu(status); + } else { + printk(KERN_NOTICE PFX "%s: hardware receive " + "checksum problem (status = %#x)\n", +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/tulip/interrupt.c linux-2.6.27.29-0.1.1/drivers/net/tulip/interrupt.c +--- linux-2.6.27.25-0.1.1/drivers/net/tulip/interrupt.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/tulip/interrupt.c 2009-08-27 12:44:15.000000000 +0100 +@@ -140,6 +140,7 @@ int tulip_poll(struct napi_struct *napi, + /* If we own the next entry, it is a new packet. Send it up. */ + while ( ! (tp->rx_ring[entry].status & cpu_to_le32(DescOwned))) { + s32 status = le32_to_cpu(tp->rx_ring[entry].status); ++ short pkt_len; + + if (tp->dirty_rx + RX_RING_SIZE == tp->cur_rx) + break; +@@ -151,8 +152,28 @@ int tulip_poll(struct napi_struct *napi, + if (++work_done >= budget) + goto not_done; + +- if ((status & 0x38008300) != 0x0300) { +- if ((status & 0x38000300) != 0x0300) { ++ /* ++ * Omit the four octet CRC from the length. ++ * (May not be considered valid until we have ++ * checked status for RxLengthOver2047 bits) ++ */ ++ pkt_len = ((status >> 16) & 0x7ff) - 4; ++ ++ /* ++ * Maximum pkt_len is 1518 (1514 + vlan header) ++ * Anything higher than this is always invalid ++ * regardless of RxLengthOver2047 bits ++ */ ++ ++ if ((status & (RxLengthOver2047 | ++ RxDescCRCError | ++ RxDescCollisionSeen | ++ RxDescRunt | ++ RxDescDescErr | ++ RxWholePkt)) != RxWholePkt ++ || pkt_len > 1518) { ++ if ((status & (RxLengthOver2047 | ++ RxWholePkt)) != RxWholePkt) { + /* Ingore earlier buffers. */ + if ((status & 0xffff) != 0x7fff) { + if (tulip_debug > 1) +@@ -161,30 +182,23 @@ int tulip_poll(struct napi_struct *napi, + dev->name, status); + tp->stats.rx_length_errors++; + } +- } else if (status & RxDescFatalErr) { ++ } else { + /* There was a fatal error. */ + if (tulip_debug > 2) + printk(KERN_DEBUG "%s: Receive error, Rx status %8.8x.\n", + dev->name, status); + tp->stats.rx_errors++; /* end of a packet.*/ +- if (status & 0x0890) tp->stats.rx_length_errors++; ++ if (pkt_len > 1518 || ++ (status & RxDescRunt)) ++ tp->stats.rx_length_errors++; ++ + if (status & 0x0004) tp->stats.rx_frame_errors++; + if (status & 0x0002) tp->stats.rx_crc_errors++; + if (status & 0x0001) tp->stats.rx_fifo_errors++; + } + } else { +- /* Omit the four octet CRC from the length. */ +- short pkt_len = ((status >> 16) & 0x7ff) - 4; + struct sk_buff *skb; + +-#ifndef final_version +- if (pkt_len > 1518) { +- printk(KERN_WARNING "%s: Bogus packet size of %d (%#x).\n", +- dev->name, pkt_len, pkt_len); +- pkt_len = 1518; +- tp->stats.rx_length_errors++; +- } +-#endif + /* Check if the packet is long enough to accept without copying + to a minimally-sized skbuff. */ + if (pkt_len < tulip_rx_copybreak +@@ -357,14 +371,35 @@ static int tulip_rx(struct net_device *d + /* If we own the next entry, it is a new packet. Send it up. */ + while ( ! (tp->rx_ring[entry].status & cpu_to_le32(DescOwned))) { + s32 status = le32_to_cpu(tp->rx_ring[entry].status); ++ short pkt_len; + + if (tulip_debug > 5) + printk(KERN_DEBUG "%s: In tulip_rx(), entry %d %8.8x.\n", + dev->name, entry, status); + if (--rx_work_limit < 0) + break; +- if ((status & 0x38008300) != 0x0300) { +- if ((status & 0x38000300) != 0x0300) { ++ ++ /* ++ Omit the four octet CRC from the length. ++ (May not be considered valid until we have ++ checked status for RxLengthOver2047 bits) ++ */ ++ pkt_len = ((status >> 16) & 0x7ff) - 4; ++ /* ++ Maximum pkt_len is 1518 (1514 + vlan header) ++ Anything higher than this is always invalid ++ regardless of RxLengthOver2047 bits ++ */ ++ ++ if ((status & (RxLengthOver2047 | ++ RxDescCRCError | ++ RxDescCollisionSeen | ++ RxDescRunt | ++ RxDescDescErr | ++ RxWholePkt)) != RxWholePkt ++ || pkt_len > 1518) { ++ if ((status & (RxLengthOver2047 | ++ RxWholePkt)) != RxWholePkt) { + /* Ingore earlier buffers. */ + if ((status & 0xffff) != 0x7fff) { + if (tulip_debug > 1) +@@ -373,31 +408,22 @@ static int tulip_rx(struct net_device *d + dev->name, status); + tp->stats.rx_length_errors++; + } +- } else if (status & RxDescFatalErr) { ++ } else { + /* There was a fatal error. */ + if (tulip_debug > 2) + printk(KERN_DEBUG "%s: Receive error, Rx status %8.8x.\n", + dev->name, status); + tp->stats.rx_errors++; /* end of a packet.*/ +- if (status & 0x0890) tp->stats.rx_length_errors++; ++ if (pkt_len > 1518 || ++ (status & RxDescRunt)) ++ tp->stats.rx_length_errors++; + if (status & 0x0004) tp->stats.rx_frame_errors++; + if (status & 0x0002) tp->stats.rx_crc_errors++; + if (status & 0x0001) tp->stats.rx_fifo_errors++; + } + } else { +- /* Omit the four octet CRC from the length. */ +- short pkt_len = ((status >> 16) & 0x7ff) - 4; + struct sk_buff *skb; + +-#ifndef final_version +- if (pkt_len > 1518) { +- printk(KERN_WARNING "%s: Bogus packet size of %d (%#x).\n", +- dev->name, pkt_len, pkt_len); +- pkt_len = 1518; +- tp->stats.rx_length_errors++; +- } +-#endif +- + /* Check if the packet is long enough to accept without copying + to a minimally-sized skbuff. */ + if (pkt_len < tulip_rx_copybreak +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/tulip/tulip.h linux-2.6.27.29-0.1.1/drivers/net/tulip/tulip.h +--- linux-2.6.27.25-0.1.1/drivers/net/tulip/tulip.h 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/tulip/tulip.h 2009-08-27 12:44:15.000000000 +0100 +@@ -201,8 +201,38 @@ enum desc_status_bits { + DescStartPkt = 0x20000000, + DescEndRing = 0x02000000, + DescUseLink = 0x01000000, +- RxDescFatalErr = 0x008000, ++ ++ /* ++ * Error summary flag is logical or of 'CRC Error', 'Collision Seen', ++ * 'Frame Too Long', 'Runt' and 'Descriptor Error' flags generated ++ * within tulip chip. ++ */ ++ RxDescErrorSummary = 0x8000, ++ RxDescCRCError = 0x0002, ++ RxDescCollisionSeen = 0x0040, ++ ++ /* ++ * 'Frame Too Long' flag is set if packet length including CRC exceeds ++ * 1518. However, a full sized VLAN tagged frame is 1522 bytes ++ * including CRC. ++ * ++ * The tulip chip does not block oversized frames, and if this flag is ++ * set on a receive descriptor it does not indicate the frame has been ++ * truncated. The receive descriptor also includes the actual length. ++ * Therefore we can safety ignore this flag and check the length ++ * ourselves. ++ */ ++ RxDescFrameTooLong = 0x0080, ++ RxDescRunt = 0x0800, ++ RxDescDescErr = 0x4000, + RxWholePkt = 0x00000300, ++ /* ++ * Top three bits of 14 bit frame length (status bits 27-29) should ++ * never be set as that would make frame over 2047 bytes. The Receive ++ * Watchdog flag (bit 4) may indicate the length is over 2048 and the ++ * length field is invalid. ++ */ ++ RxLengthOver2047 = 0x38000010 + }; + + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/usb/cdc_subset.c linux-2.6.27.29-0.1.1/drivers/net/usb/cdc_subset.c +--- linux-2.6.27.25-0.1.1/drivers/net/usb/cdc_subset.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/usb/cdc_subset.c 2009-08-27 12:44:15.000000000 +0100 +@@ -307,9 +307,10 @@ static const struct usb_device_id produc + USB_DEVICE (0x1286, 0x8001), // "blob" bootloader + .driver_info = (unsigned long) &blob_info, + }, { +- // Linux Ethernet/RNDIS gadget on pxa210/25x/26x, second config +- // e.g. Gumstix, current OpenZaurus, ... +- USB_DEVICE_VER (0x0525, 0xa4a2, 0x0203, 0x0203), ++ // Linux Ethernet/RNDIS gadget, mostly on PXA, second config ++ // e.g. Gumstix, current OpenZaurus, ... or anything else ++ // that just enables this gadget option. ++ USB_DEVICE (0x0525, 0xa4a2), + .driver_info = (unsigned long) &linuxdev_info, + }, + #endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/usb/pegasus.c linux-2.6.27.29-0.1.1/drivers/net/usb/pegasus.c +--- linux-2.6.27.25-0.1.1/drivers/net/usb/pegasus.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/usb/pegasus.c 2009-08-27 12:44:15.000000000 +0100 +@@ -295,7 +295,7 @@ static int update_eth_regs_async(pegasus + + pegasus->dr.bRequestType = PEGASUS_REQT_WRITE; + pegasus->dr.bRequest = PEGASUS_REQ_SET_REGS; +- pegasus->dr.wValue = 0; ++ pegasus->dr.wValue = cpu_to_le16(0); + pegasus->dr.wIndex = cpu_to_le16(EthCtrl0); + pegasus->dr.wLength = cpu_to_le16(3); + pegasus->ctrl_urb->transfer_buffer_length = 3; +@@ -444,11 +444,12 @@ static int write_eprom_word(pegasus_t * + int i; + __u8 tmp, d[4] = { 0x3f, 0, 0, EPROM_WRITE }; + int ret; ++ __le16 le_data = cpu_to_le16(data); + + set_registers(pegasus, EpromOffset, 4, d); + enable_eprom_write(pegasus); + set_register(pegasus, EpromOffset, index); +- set_registers(pegasus, EpromData, 2, &data); ++ set_registers(pegasus, EpromData, 2, &le_data); + set_register(pegasus, EpromCtrl, EPROM_WRITE); + + for (i = 0; i < REG_TIMEOUT; i++) { +@@ -918,29 +919,32 @@ static struct net_device_stats *pegasus_ + + static inline void disable_net_traffic(pegasus_t * pegasus) + { +- int tmp = 0; ++ __le16 tmp = cpu_to_le16(0); + +- set_registers(pegasus, EthCtrl0, 2, &tmp); ++ set_registers(pegasus, EthCtrl0, sizeof(tmp), &tmp); + } + + static inline void get_interrupt_interval(pegasus_t * pegasus) + { +- __u8 data[2]; ++ u16 data; ++ u8 interval; + +- read_eprom_word(pegasus, 4, (__u16 *) data); ++ read_eprom_word(pegasus, 4, &data); ++ interval = data >> 8; + if (pegasus->usb->speed != USB_SPEED_HIGH) { +- if (data[1] < 0x80) { ++ if (interval < 0x80) { + if (netif_msg_timer(pegasus)) + dev_info(&pegasus->intf->dev, "intr interval " + "changed from %ums to %ums\n", +- data[1], 0x80); +- data[1] = 0x80; ++ interval, 0x80); ++ interval = 0x80; ++ data = (data & 0x00FF) | ((u16)interval << 8); + #ifdef PEGASUS_WRITE_EEPROM +- write_eprom_word(pegasus, 4, *(__u16 *) data); ++ write_eprom_word(pegasus, 4, data); + #endif + } + } +- pegasus->intr_interval = data[1]; ++ pegasus->intr_interval = interval; + } + + static void set_carrier(struct net_device *net) +@@ -1293,7 +1297,8 @@ static int pegasus_blacklisted(struct us + /* Special quirk to keep the driver from handling the Belkin Bluetooth + * dongle which happens to have the same ID. + */ +- if ((udd->idVendor == VENDOR_BELKIN && udd->idProduct == 0x0121) && ++ if ((udd->idVendor == cpu_to_le16(VENDOR_BELKIN)) && ++ (udd->idProduct == cpu_to_le16(0x0121)) && + (udd->bDeviceClass == USB_CLASS_WIRELESS_CONTROLLER) && + (udd->bDeviceProtocol == 1)) + return 1; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/net/wireless/strip.c linux-2.6.27.29-0.1.1/drivers/net/wireless/strip.c +--- linux-2.6.27.25-0.1.1/drivers/net/wireless/strip.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/net/wireless/strip.c 2009-08-27 12:44:15.000000000 +0100 +@@ -856,6 +856,7 @@ static int strip_change_mtu(struct net_d + unsigned char *orbuff = strip_info->rx_buff; + unsigned char *osbuff = strip_info->sx_buff; + unsigned char *otbuff = strip_info->tx_buff; ++ unsigned long flags; + + if (new_mtu > MAX_SEND_MTU) { + printk(KERN_ERR +@@ -864,11 +865,11 @@ static int strip_change_mtu(struct net_d + return -EINVAL; + } + +- spin_lock_bh(&strip_lock); ++ spin_lock_irqsave(&strip_lock, flags); + if (!allocate_buffers(strip_info, new_mtu)) { + printk(KERN_ERR "%s: unable to grow strip buffers, MTU change cancelled.\n", + strip_info->dev->name); +- spin_unlock_bh(&strip_lock); ++ spin_unlock_irqrestore(&strip_lock, flags); + return -ENOMEM; + } + +@@ -892,7 +893,7 @@ static int strip_change_mtu(struct net_d + } + } + strip_info->tx_head = strip_info->tx_buff; +- spin_unlock_bh(&strip_lock); ++ spin_unlock_irqrestore(&strip_lock, flags); + + printk(KERN_NOTICE "%s: strip MTU changed fom %d to %d.\n", + strip_info->dev->name, old_mtu, strip_info->mtu); +@@ -981,10 +982,13 @@ static void strip_seq_neighbours(struct + const MetricomNodeTable * table, + const char *title) + { +- /* We wrap this in a do/while loop, so if the table changes */ +- /* while we're reading it, we just go around and try again. */ ++ unsigned long flags; + struct timeval t; + ++ /* ++ * We wrap this in a do/while loop, so if the table changes ++ * while we're reading it, we just go around and try again. ++ */ + do { + int i; + t = table->timestamp; +@@ -993,9 +997,9 @@ static void strip_seq_neighbours(struct + for (i = 0; i < table->num_nodes; i++) { + MetricomNode node; + +- spin_lock_bh(&strip_lock); ++ spin_lock_irqsave(&strip_lock, flags); + node = table->node[i]; +- spin_unlock_bh(&strip_lock); ++ spin_unlock_irqrestore(&strip_lock, flags); + seq_printf(seq, " %s\n", node.c); + } + } while (table->timestamp.tv_sec != t.tv_sec +@@ -1535,6 +1539,7 @@ static void strip_send(struct strip *str + static int strip_xmit(struct sk_buff *skb, struct net_device *dev) + { + struct strip *strip_info = netdev_priv(dev); ++ unsigned long flags; + + if (!netif_running(dev)) { + printk(KERN_ERR "%s: xmit call when iface is down\n", +@@ -1573,11 +1578,11 @@ static int strip_xmit(struct sk_buff *sk + strip_info->dev->name, sx_pps_count / 8); + } + +- spin_lock_bh(&strip_lock); ++ spin_lock_irqsave(&strip_lock, flags); + + strip_send(strip_info, skb); + +- spin_unlock_bh(&strip_lock); ++ spin_unlock_irqrestore(&strip_lock, flags); + + if (skb) + dev_kfree_skb(skb); +@@ -2263,12 +2268,13 @@ static void strip_receive_buf(struct tty + { + struct strip *strip_info = (struct strip *) tty->disc_data; + const unsigned char *end = cp + count; ++ unsigned long flags; + + if (!strip_info || strip_info->magic != STRIP_MAGIC + || !netif_running(strip_info->dev)) + return; + +- spin_lock_bh(&strip_lock); ++ spin_lock_irqsave(&strip_lock, flags); + #if 0 + { + struct timeval tv; +@@ -2335,7 +2341,7 @@ static void strip_receive_buf(struct tty + } + cp++; + } +- spin_unlock_bh(&strip_lock); ++ spin_unlock_irqrestore(&strip_lock, flags); + } + + +@@ -2525,9 +2531,11 @@ static void strip_dev_setup(struct net_d + + static void strip_free(struct strip *strip_info) + { +- spin_lock_bh(&strip_lock); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&strip_lock, flags); + list_del_rcu(&strip_info->list); +- spin_unlock_bh(&strip_lock); ++ spin_unlock_irqrestore(&strip_lock, flags); + + strip_info->magic = 0; + +@@ -2541,6 +2549,7 @@ static void strip_free(struct strip *str + static struct strip *strip_alloc(void) + { + struct list_head *n; ++ unsigned long flags; + struct net_device *dev; + struct strip *strip_info; + +@@ -2564,7 +2573,7 @@ static struct strip *strip_alloc(void) + strip_info->idle_timer.function = strip_IdleTask; + + +- spin_lock_bh(&strip_lock); ++ spin_lock_irqsave(&strip_lock, flags); + rescan: + /* + * Search the list to find where to put our new entry +@@ -2583,7 +2592,7 @@ static struct strip *strip_alloc(void) + sprintf(dev->name, "st%ld", dev->base_addr); + + list_add_tail_rcu(&strip_info->list, &strip_list); +- spin_unlock_bh(&strip_lock); ++ spin_unlock_irqrestore(&strip_lock, flags); + + return strip_info; + } +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/parport/parport_pc.c linux-2.6.27.29-0.1.1/drivers/parport/parport_pc.c +--- linux-2.6.27.25-0.1.1/drivers/parport/parport_pc.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/parport/parport_pc.c 2009-08-27 12:44:31.000000000 +0100 +@@ -1413,11 +1413,13 @@ static void __devinit decode_smsc(int ef + + static void __devinit winbond_check(int io, int key) + { +- int devid,devrev,oldid,x_devid,x_devrev,x_oldid; ++ int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid; + + if (!request_region(io, 3, __func__)) + return; + ++ origval = inb(io); /* Save original value */ ++ + /* First probe without key */ + outb(0x20,io); + x_devid=inb(io+1); +@@ -1437,6 +1439,8 @@ static void __devinit winbond_check(int + oldid=inb(io+1); + outb(0xaa,io); /* Magic Seal */ + ++ outb(origval, io); /* in case we poked some entirely different hardware */ ++ + if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) + goto out; /* protection against false positives */ + +@@ -1447,11 +1451,15 @@ out: + + static void __devinit winbond_check2(int io,int key) + { +- int devid,devrev,oldid,x_devid,x_devrev,x_oldid; ++ int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid; + + if (!request_region(io, 3, __func__)) + return; + ++ origval[0] = inb(io); /* Save original values */ ++ origval[1] = inb(io + 1); ++ origval[2] = inb(io + 2); ++ + /* First probe without the key */ + outb(0x20,io+2); + x_devid=inb(io+2); +@@ -1470,6 +1478,10 @@ static void __devinit winbond_check2(int + oldid=inb(io+2); + outb(0xaa,io); /* Magic Seal */ + ++ outb(origval[0], io); /* in case we poked some entirely different hardware */ ++ outb(origval[1], io + 1); ++ outb(origval[2], io + 2); ++ + if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) + goto out; /* protection against false positives */ + +@@ -1480,11 +1492,13 @@ out: + + static void __devinit smsc_check(int io, int key) + { +- int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev; ++ int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev; + + if (!request_region(io, 3, __func__)) + return; + ++ origval = inb(io); /* Save original value */ ++ + /* First probe without the key */ + outb(0x0d,io); + x_oldid=inb(io+1); +@@ -1508,6 +1522,8 @@ static void __devinit smsc_check(int io, + rev=inb(io+1); + outb(0xaa,io); /* Magic Seal */ + ++ outb(origval, io); /* in case we poked some entirely different hardware */ ++ + if ((x_id == id) && (x_oldrev == oldrev) && + (x_oldid == oldid) && (x_rev == rev)) + goto out; /* protection against false positives */ +@@ -1544,11 +1560,12 @@ static void __devinit detect_and_report_ + static void __devinit detect_and_report_it87(void) + { + u16 dev; +- u8 r; ++ u8 origval, r; + if (verbose_probing) + printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n"); +- if (!request_region(0x2e, 1, __func__)) ++ if (!request_region(0x2e, 2, __func__)) + return; ++ origval = inb(0x2e); /* Save original value */ + outb(0x87, 0x2e); + outb(0x01, 0x2e); + outb(0x55, 0x2e); +@@ -1568,8 +1585,10 @@ static void __devinit detect_and_report_ + outb(r | 8, 0x2F); + outb(0x02, 0x2E); /* Lock */ + outb(0x02, 0x2F); ++ } else { ++ outb(origval, 0x2e); /* Oops, sorry to disturb */ + } +- release_region(0x2e, 1); ++ release_region(0x2e, 2); + } + #endif /* CONFIG_PARPORT_PC_SUPERIO */ + +@@ -2192,6 +2211,9 @@ struct parport *parport_pc_probe_port (u + if (IS_ERR(pdev)) + return NULL; + dev = &pdev->dev; ++ ++ dev->coherent_dma_mask = DMA_BIT_MASK(24); ++ dev->dma_mask = &dev->coherent_dma_mask; + } + + ops = kmalloc(sizeof (struct parport_operations), GFP_KERNEL); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/parport/parport_serial.c linux-2.6.27.29-0.1.1/drivers/parport/parport_serial.c +--- linux-2.6.27.25-0.1.1/drivers/parport/parport_serial.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/parport/parport_serial.c 2009-08-27 12:44:31.000000000 +0100 +@@ -30,6 +30,7 @@ enum parport_pc_pci_cards { + titan_210l, + netmos_9xx5_combo, + netmos_9855, ++ netmos_9855_2p, + avlab_1s1p, + avlab_1s2p, + avlab_2s1p, +@@ -62,7 +63,7 @@ struct parport_pc_pci { + struct parport_pc_pci *card, int failed); + }; + +-static int __devinit netmos_parallel_init(struct pci_dev *dev, struct parport_pc_pci *card, int autoirq, int autodma) ++static int __devinit netmos_parallel_init(struct pci_dev *dev, struct parport_pc_pci *par, int autoirq, int autodma) + { + /* the rule described below doesn't hold for this device */ + if (dev->device == PCI_DEVICE_ID_NETMOS_9835 && +@@ -74,9 +75,17 @@ static int __devinit netmos_parallel_ini + * and serial ports. The form is 0x00PS, where

is the number of + * parallel ports and is the number of serial ports. + */ +- card->numports = (dev->subsystem_device & 0xf0) >> 4; +- if (card->numports > ARRAY_SIZE(card->addr)) +- card->numports = ARRAY_SIZE(card->addr); ++ par->numports = (dev->subsystem_device & 0xf0) >> 4; ++ if (par->numports > ARRAY_SIZE(par->addr)) ++ par->numports = ARRAY_SIZE(par->addr); ++ /* ++ * This function is currently only called for cards with up to ++ * one parallel port. ++ * Parallel port BAR is either before or after serial ports BARS; ++ * hence, lo should be either 0 or equal to the number of serial ports. ++ */ ++ if (par->addr[0].lo != 0) ++ par->addr[0].lo = dev->subsystem_device & 0xf; + return 0; + } + +@@ -84,7 +93,8 @@ static struct parport_pc_pci cards[] __d + /* titan_110l */ { 1, { { 3, -1 }, } }, + /* titan_210l */ { 1, { { 3, -1 }, } }, + /* netmos_9xx5_combo */ { 1, { { 2, -1 }, }, netmos_parallel_init }, +- /* netmos_9855 */ { 1, { { 2, -1 }, }, netmos_parallel_init }, ++ /* netmos_9855 */ { 1, { { 0, -1 }, }, netmos_parallel_init }, ++ /* netmos_9855_2p */ { 2, { { 0, -1 }, { 2, -1 }, } }, + /* avlab_1s1p */ { 1, { { 1, 2}, } }, + /* avlab_1s2p */ { 2, { { 1, 2}, { 3, 4 },} }, + /* avlab_2s1p */ { 1, { { 2, 3}, } }, +@@ -110,6 +120,10 @@ static struct pci_device_id parport_seri + { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9845, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo }, + { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855, ++ 0x1000, 0x0020, 0, 0, netmos_9855_2p }, ++ { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855, ++ 0x1000, 0x0022, 0, 0, netmos_9855_2p }, ++ { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 }, + /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/ + { PCI_VENDOR_ID_AFAVLAB, 0x2110, +@@ -192,6 +206,12 @@ static struct pciserial_board pci_parpor + .uart_offset = 8, + }, + [netmos_9855] = { ++ .flags = FL_BASE2 | FL_BASE_BARS, ++ .num_ports = 1, ++ .base_baud = 115200, ++ .uart_offset = 8, ++ }, ++ [netmos_9855_2p] = { + .flags = FL_BASE4 | FL_BASE_BARS, + .num_ports = 1, + .base_baud = 115200, +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/pci/iova.c linux-2.6.27.29-0.1.1/drivers/pci/iova.c +--- linux-2.6.27.25-0.1.1/drivers/pci/iova.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/pci/iova.c 2009-08-27 12:44:24.000000000 +0100 +@@ -1,9 +1,19 @@ + /* +- * Copyright (c) 2006, Intel Corporation. ++ * Copyright © 2006-2009, Intel Corporation. + * +- * This file is released under the GPLv2. ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. + * +- * Copyright (C) 2006-2008 Intel Corporation + * Author: Anil S Keshavamurthy + */ + +@@ -123,7 +133,15 @@ move_left: + /* Insert the new_iova into domain rbtree by holding writer lock */ + /* Add new node and rebalance tree. */ + { +- struct rb_node **entry = &((prev)), *parent = NULL; ++ struct rb_node **entry, *parent = NULL; ++ ++ /* If we have 'prev', it's a valid place to start the ++ insertion. Otherwise, start from the root. */ ++ if (prev) ++ entry = &prev; ++ else ++ entry = &iovad->rbroot.rb_node; ++ + /* Figure out where to put new node */ + while (*entry) { + struct iova *this = container_of(*entry, +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/pci/pci.c linux-2.6.27.29-0.1.1/drivers/pci/pci.c +--- linux-2.6.27.25-0.1.1/drivers/pci/pci.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/pci/pci.c 2009-08-27 12:44:24.000000000 +0100 +@@ -478,6 +478,8 @@ pci_raw_set_power_state(struct pci_dev * + pmcsr &= ~PCI_PM_CTRL_STATE_MASK; + pmcsr |= state; + break; ++ case PCI_D3hot: ++ case PCI_D3cold: + case PCI_UNKNOWN: /* Boot-up */ + if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot + && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) +@@ -1189,15 +1191,14 @@ pci_power_t pci_target_state(struct pci_ + default: + target_state = state; + } ++ } else if (!dev->pm_cap) { ++ target_state = PCI_D0; + } else if (device_may_wakeup(&dev->dev)) { + /* + * Find the deepest state from which the device can generate + * wake-up events, make it the target state and enable device + * to generate PME#. + */ +- if (!dev->pm_cap) +- return PCI_POWER_ERROR; +- + if (dev->pme_support) { + while (target_state + && !(dev->pme_support & (1 << target_state))) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/pci/pcie/aspm.c linux-2.6.27.29-0.1.1/drivers/pci/pcie/aspm.c +--- linux-2.6.27.25-0.1.1/drivers/pci/pcie/aspm.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/pci/pcie/aspm.c 2009-08-27 12:44:24.000000000 +0100 +@@ -633,6 +633,10 @@ void pcie_aspm_init_link_state(struct pc + if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && + pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) + return; ++ /* VIA has a strange chipset, root port is under a bridge */ ++ if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT && ++ pdev->bus->self) ++ return; + down_read(&pci_bus_sem); + if (list_empty(&pdev->subordinate->devices)) + goto out; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/pnp/pnpacpi/core.c linux-2.6.27.29-0.1.1/drivers/pnp/pnpacpi/core.c +--- linux-2.6.27.25-0.1.1/drivers/pnp/pnpacpi/core.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/pnp/pnpacpi/core.c 2009-08-27 12:44:24.000000000 +0100 +@@ -84,7 +84,6 @@ static int pnpacpi_set_resources(struct + acpi_handle handle = dev->data; + struct acpi_buffer buffer; + int ret; +- acpi_status status; + + dev_dbg(&dev->dev, "set resources\n"); + ret = pnpacpi_build_resource_template(dev, &buffer); +@@ -95,21 +94,29 @@ static int pnpacpi_set_resources(struct + kfree(buffer.pointer); + return ret; + } +- status = acpi_set_current_resources(handle, &buffer); +- if (ACPI_FAILURE(status)) ++ if (ACPI_FAILURE(acpi_set_current_resources(handle, &buffer))) + ret = -EINVAL; ++ else if (acpi_bus_power_manageable(handle)) ++ ret = acpi_bus_set_power(handle, ACPI_STATE_D0); + kfree(buffer.pointer); + return ret; + } + + static int pnpacpi_disable_resources(struct pnp_dev *dev) + { +- acpi_status status; ++ acpi_handle handle = dev->data; ++ int ret; ++ ++ dev_dbg(&dev->dev, "disable resources\n"); + + /* acpi_unregister_gsi(pnp_irq(dev, 0)); */ +- status = acpi_evaluate_object((acpi_handle) dev->data, +- "_DIS", NULL, NULL); +- return ACPI_FAILURE(status) ? -ENODEV : 0; ++ ret = 0; ++ if (acpi_bus_power_manageable(handle)) ++ acpi_bus_set_power(handle, ACPI_STATE_D3); ++ /* continue even if acpi_bus_set_power() fails */ ++ if (ACPI_FAILURE(acpi_evaluate_object(handle, "_DIS", NULL, NULL))) ++ ret = -ENODEV; ++ return ret; + } + + #ifdef CONFIG_ACPI_SLEEP +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/s390/cio/device_fsm.c linux-2.6.27.29-0.1.1/drivers/s390/cio/device_fsm.c +--- linux-2.6.27.25-0.1.1/drivers/s390/cio/device_fsm.c 2009-08-05 09:49:48.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/s390/cio/device_fsm.c 2009-08-27 12:44:29.000000000 +0100 +@@ -739,6 +739,17 @@ static void ccw_device_generic_notoper(s + } + + /* ++ * Handle path verification event in offline state. ++ */ ++static void ccw_device_offline_verify(struct ccw_device *cdev, ++ enum dev_event dev_event) ++{ ++ struct subchannel *sch = to_subchannel(cdev->dev.parent); ++ ++ css_schedule_eval(sch->schid); ++} ++ ++/* + * Handle path verification event. + */ + static void +@@ -1155,7 +1166,7 @@ fsm_func_t *dev_jumptable[NR_DEV_STATES] + [DEV_EVENT_NOTOPER] = ccw_device_generic_notoper, + [DEV_EVENT_INTERRUPT] = ccw_device_offline_irq, + [DEV_EVENT_TIMEOUT] = ccw_device_nop, +- [DEV_EVENT_VERIFY] = ccw_device_nop, ++ [DEV_EVENT_VERIFY] = ccw_device_offline_verify, + }, + [DEV_STATE_VERIFY] = { + [DEV_EVENT_NOTOPER] = ccw_device_generic_notoper, +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/s390/crypto/ap_bus.c linux-2.6.27.29-0.1.1/drivers/s390/crypto/ap_bus.c +--- linux-2.6.27.25-0.1.1/drivers/s390/crypto/ap_bus.c 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/s390/crypto/ap_bus.c 2009-08-27 12:44:29.000000000 +0100 +@@ -930,10 +930,16 @@ ap_config_timeout(unsigned long ptr) + */ + static inline void ap_schedule_poll_timer(void) + { ++ ktime_t hr_time; + if (hrtimer_is_queued(&ap_poll_timer)) + return; +- hrtimer_start(&ap_poll_timer, ktime_set(0, poll_timeout), +- HRTIMER_MODE_ABS); ++ ++ if (ktime_to_ns(hrtimer_get_remaining(&ap_poll_timer)) <= 0) { ++ hr_time = ktime_set(0, poll_timeout); ++ hrtimer_forward_now(&ap_poll_timer, hr_time); ++ hrtimer_restart(&ap_poll_timer); ++ } ++ return; + } + + /** +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_aux.c linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_aux.c +--- linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_aux.c 2009-08-05 09:49:48.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_aux.c 2009-08-27 12:44:29.000000000 +0100 +@@ -553,6 +553,7 @@ void zfcp_adapter_dequeue(struct zfcp_ad + + cancel_work_sync(&adapter->scan_work); + cancel_work_sync(&adapter->stat_work); ++ zfcp_fc_wka_port_force_offline(&adapter->nsp); + zfcp_adapter_scsi_unregister(adapter); + sysfs_remove_group(&adapter->ccw_device->dev.kobj, + &zfcp_sysfs_adapter_attrs); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_dbf.c linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_dbf.c +--- linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_dbf.c 2009-08-05 09:49:48.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_dbf.c 2009-08-27 12:44:29.000000000 +0100 +@@ -563,13 +563,11 @@ static const char *zfcp_rec_dbf_ids[] = + [71] = "adapter recovery escalation after failed adapter recovery", + [72] = "port recovery follow-up after successful physical port " + "recovery", +- [73] = "adapter recovery escalation after failed physical port " +- "recovery", ++ [73] = "physical port recovery retry after failure", + [74] = "unit recovery follow-up after successful port recovery", +- [75] = "physical port recovery escalation after failed port " +- "recovery", +- [76] = "port recovery escalation after failed unit recovery", +- [77] = "", ++ [75] = "port recovery retry after failure", ++ [76] = "unit recovery retry after failure", ++ [77] = "adapter reopen from queue stall", + [78] = "duplicate request id", + [79] = "link down", + [80] = "exclusive read-only unit access unsupported", +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_def.h linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_def.h +--- linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_def.h 2009-08-05 09:49:48.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_def.h 2009-08-27 12:44:29.000000000 +0100 +@@ -260,6 +260,7 @@ struct zfcp_ls_adisc { + #define ZFCP_STATUS_PORT_PHYS_CLOSING 0x00000004 + #define ZFCP_STATUS_PORT_NO_WWPN 0x00000008 + #define ZFCP_STATUS_PORT_INVALID_WWPN 0x00000020 ++#define ZFCP_STATUS_PORT_LINK_TEST 0x00000040 + + /* well known address (WKA) port status*/ + enum zfcp_wka_status { +@@ -621,9 +622,6 @@ struct zfcp_fsf_req_qtcb { + + /********************** ZFCP SPECIFIC DEFINES ********************************/ + +-#define ZFCP_REQ_AUTO_CLEANUP 0x00000002 +-#define ZFCP_REQ_NO_QTCB 0x00000008 +- + #define ZFCP_SET 0x00000100 + #define ZFCP_CLEAR 0x00000200 + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_erp.c linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_erp.c +--- linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_erp.c 2009-08-05 09:49:48.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_erp.c 2009-08-27 12:44:29.000000000 +0100 +@@ -549,40 +549,35 @@ static void _zfcp_erp_unit_reopen_all(st + _zfcp_erp_unit_reopen(unit, clear, id, ref); + } + +-static void zfcp_erp_strategy_followup_actions(struct zfcp_erp_action *act) ++static void zfcp_erp_strategy_followup_failed(struct zfcp_erp_action *act) + { +- struct zfcp_adapter *adapter = act->adapter; +- struct zfcp_port *port = act->port; +- struct zfcp_unit *unit = act->unit; +- u32 status = act->status; +- +- /* initiate follow-up actions depending on success of finished action */ + switch (act->action) { +- + case ZFCP_ERP_ACTION_REOPEN_ADAPTER: +- if (status == ZFCP_ERP_SUCCEEDED) +- _zfcp_erp_port_reopen_all(adapter, 0, 70, NULL); +- else +- _zfcp_erp_adapter_reopen(adapter, 0, 71, NULL); ++ _zfcp_erp_adapter_reopen(act->adapter, 0, 71, NULL); + break; +- + case ZFCP_ERP_ACTION_REOPEN_PORT_FORCED: +- if (status == ZFCP_ERP_SUCCEEDED) +- _zfcp_erp_port_reopen(port, 0, 72, NULL); +- else +- _zfcp_erp_adapter_reopen(adapter, 0, 73, NULL); ++ _zfcp_erp_port_forced_reopen(act->port, 0, 73, NULL); + break; +- + case ZFCP_ERP_ACTION_REOPEN_PORT: +- if (status == ZFCP_ERP_SUCCEEDED) +- _zfcp_erp_unit_reopen_all(port, 0, 74, NULL); +- else +- _zfcp_erp_port_forced_reopen(port, 0, 75, NULL); ++ _zfcp_erp_port_reopen(act->port, 0, 75, NULL); + break; +- + case ZFCP_ERP_ACTION_REOPEN_UNIT: +- if (status != ZFCP_ERP_SUCCEEDED) +- _zfcp_erp_port_reopen(unit->port, 0, 76, NULL); ++ _zfcp_erp_unit_reopen(act->unit, 0, 76, NULL); ++ break; ++ } ++} ++ ++static void zfcp_erp_strategy_followup_success(struct zfcp_erp_action *act) ++{ ++ switch (act->action) { ++ case ZFCP_ERP_ACTION_REOPEN_ADAPTER: ++ _zfcp_erp_port_reopen_all(act->adapter, 0, 70, NULL); ++ break; ++ case ZFCP_ERP_ACTION_REOPEN_PORT_FORCED: ++ _zfcp_erp_port_reopen(act->port, 0, 72, NULL); ++ break; ++ case ZFCP_ERP_ACTION_REOPEN_PORT: ++ _zfcp_erp_unit_reopen_all(act->port, 0, 74, NULL); + break; + } + } +@@ -801,7 +796,7 @@ static int zfcp_erp_port_forced_strategy + return ZFCP_ERP_FAILED; + + case ZFCP_ERP_STEP_PHYS_PORT_CLOSING: +- if (status & ZFCP_STATUS_PORT_PHYS_OPEN) ++ if (!(status & ZFCP_STATUS_PORT_PHYS_OPEN)) + return ZFCP_ERP_SUCCEEDED; + } + return ZFCP_ERP_FAILED; +@@ -855,10 +850,10 @@ void zfcp_erp_port_strategy_open_lookup( + + retval = zfcp_fc_ns_gid_pn(&port->erp_action); + if (retval == -ENOMEM) +- zfcp_erp_notify(&port->erp_action, ZFCP_ERP_NOMEM); ++ zfcp_erp_notify(&port->erp_action, ZFCP_STATUS_ERP_LOWMEM); + port->erp_action.step = ZFCP_ERP_STEP_NAMESERVER_LOOKUP; + if (retval) +- zfcp_erp_notify(&port->erp_action, ZFCP_ERP_FAILED); ++ zfcp_erp_notify(&port->erp_action, 0); + zfcp_port_put(port); + } + +@@ -1297,7 +1292,10 @@ static int zfcp_erp_strategy(struct zfcp + retval = zfcp_erp_strategy_statechange(erp_action, retval); + if (retval == ZFCP_ERP_EXIT) + goto unlock; +- zfcp_erp_strategy_followup_actions(erp_action); ++ if (retval == ZFCP_ERP_SUCCEEDED) ++ zfcp_erp_strategy_followup_success(erp_action); ++ if (retval == ZFCP_ERP_FAILED) ++ zfcp_erp_strategy_followup_failed(erp_action); + + unlock: + write_unlock(&adapter->erp_lock); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_ext.h linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_ext.h +--- linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_ext.h 2009-08-05 09:49:48.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_ext.h 2009-08-27 12:44:29.000000000 +0100 +@@ -127,16 +127,13 @@ extern int zfcp_status_read_refill(struc + extern int zfcp_fsf_send_ct(struct zfcp_send_ct *, mempool_t *, + struct zfcp_erp_action *); + extern int zfcp_fsf_send_els(struct zfcp_send_els *); +-extern int zfcp_fsf_send_fcp_command_task(struct zfcp_adapter *, +- struct zfcp_unit *, +- struct scsi_cmnd *, int, int); ++extern int zfcp_fsf_send_fcp_command_task(struct zfcp_unit *, ++ struct scsi_cmnd *); + extern void zfcp_fsf_req_complete(struct zfcp_fsf_req *); + extern void zfcp_fsf_req_free(struct zfcp_fsf_req *); +-extern struct zfcp_fsf_req *zfcp_fsf_send_fcp_ctm(struct zfcp_adapter *, +- struct zfcp_unit *, u8, int); ++extern struct zfcp_fsf_req *zfcp_fsf_send_fcp_ctm(struct zfcp_unit *, u8); + extern struct zfcp_fsf_req *zfcp_fsf_abort_fcp_command(unsigned long, +- struct zfcp_adapter *, +- struct zfcp_unit *, int); ++ struct zfcp_unit *); + + /* zfcp_qdio.c */ + extern int zfcp_qdio_allocate(struct zfcp_adapter *); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_fc.c linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_fc.c +--- linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_fc.c 2009-08-05 09:49:48.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_fc.c 2009-08-27 12:44:29.000000000 +0100 +@@ -56,11 +56,9 @@ static int zfcp_wka_port_get(struct zfcp + + mutex_unlock(&wka_port->mutex); + +- wait_event_timeout( +- wka_port->completion_wq, +- wka_port->status == ZFCP_WKA_PORT_ONLINE || +- wka_port->status == ZFCP_WKA_PORT_OFFLINE, +- HZ >> 1); ++ wait_event(wka_port->completion_wq, ++ wka_port->status == ZFCP_WKA_PORT_ONLINE || ++ wka_port->status == ZFCP_WKA_PORT_OFFLINE); + + if (wka_port->status == ZFCP_WKA_PORT_ONLINE) { + atomic_inc(&wka_port->refcount); +@@ -391,6 +389,7 @@ static void zfcp_fc_adisc_handler(unsign + zfcp_scsi_schedule_rport_register(port); + + out: ++ atomic_clear_mask(ZFCP_STATUS_PORT_LINK_TEST, &port->status); + zfcp_port_put(port); + kfree(adisc); + } +@@ -437,13 +436,21 @@ void zfcp_fc_link_test_work(struct work_ + port->rport_task = RPORT_DEL; + zfcp_scsi_rport_work(&port->rport_work); + ++ /* only issue one test command at one time per port */ ++ if (atomic_read(&port->status) & ZFCP_STATUS_PORT_LINK_TEST) ++ goto out; ++ ++ atomic_set_mask(ZFCP_STATUS_PORT_LINK_TEST, &port->status); ++ + retval = zfcp_fc_adisc(port); + if (retval == 0) + return; + + /* send of ADISC was not possible */ ++ atomic_clear_mask(ZFCP_STATUS_PORT_LINK_TEST, &port->status); + zfcp_erp_port_forced_reopen(port, 0, 65, NULL); + ++out: + zfcp_port_put(port); + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_fsf.c linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_fsf.c +--- linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_fsf.c 2009-08-05 09:49:48.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_fsf.c 2009-08-27 12:44:29.000000000 +0100 +@@ -11,6 +11,9 @@ + #include + #include "zfcp_ext.h" + ++#define ZFCP_REQ_AUTO_CLEANUP 0x00000002 ++#define ZFCP_REQ_NO_QTCB 0x00000008 ++ + static void zfcp_fsf_request_timeout_handler(unsigned long data) + { + struct zfcp_adapter *adapter = (struct zfcp_adapter *) data; +@@ -668,8 +671,11 @@ static int zfcp_fsf_req_sbal_get(struct + zfcp_fsf_sbal_check(adapter), 5 * HZ); + if (ret > 0) + return 0; +- if (!ret) ++ if (!ret) { + atomic_inc(&adapter->qdio_outb_full); ++ /* assume hanging outbound queue, try queue recovery */ ++ zfcp_erp_adapter_reopen(adapter, 0, 77, NULL); ++ } + + spin_lock_bh(&adapter->req_q_lock); + return -EIO; +@@ -908,27 +914,22 @@ static void zfcp_fsf_abort_fcp_command_h + /** + * zfcp_fsf_abort_fcp_command - abort running SCSI command + * @old_req_id: unsigned long +- * @adapter: pointer to struct zfcp_adapter + * @unit: pointer to struct zfcp_unit +- * @req_flags: integer specifying the request flags + * Returns: pointer to struct zfcp_fsf_req +- * +- * FIXME(design): should be watched by a timeout !!! + */ + + struct zfcp_fsf_req *zfcp_fsf_abort_fcp_command(unsigned long old_req_id, +- struct zfcp_adapter *adapter, +- struct zfcp_unit *unit, +- int req_flags) ++ struct zfcp_unit *unit) + { + struct qdio_buffer_element *sbale; + struct zfcp_fsf_req *req = NULL; ++ struct zfcp_adapter *adapter = unit->port->adapter; + + spin_lock_bh(&adapter->req_q_lock); + if (zfcp_fsf_req_sbal_get(adapter)) + goto out; + req = zfcp_fsf_req_create(adapter, FSF_QTCB_ABORT_FCP_CMND, +- req_flags, adapter->pool.fsf_req_abort); ++ 0, adapter->pool.fsf_req_abort); + if (IS_ERR(req)) { + req = NULL; + goto out; +@@ -1009,6 +1010,23 @@ skip_fsfstatus: + send_ct->handler(send_ct->handler_data); + } + ++static void zfcp_fsf_setup_ct_els_unchained(struct qdio_buffer_element *sbale, ++ struct scatterlist *sg_req, ++ struct scatterlist *sg_resp) ++{ ++ sbale[0].flags |= SBAL_FLAGS0_TYPE_WRITE_READ; ++ sbale[2].addr = sg_virt(sg_req); ++ sbale[2].length = sg_req->length; ++ sbale[3].addr = sg_virt(sg_resp); ++ sbale[3].length = sg_resp->length; ++ sbale[3].flags |= SBAL_FLAGS_LAST_ENTRY; ++} ++ ++static int zfcp_fsf_one_sbal(struct scatterlist *sg) ++{ ++ return sg_is_last(sg) && sg->length <= PAGE_SIZE; ++} ++ + static int zfcp_fsf_setup_ct_els_sbals(struct zfcp_fsf_req *req, + struct scatterlist *sg_req, + struct scatterlist *sg_resp, +@@ -1019,16 +1037,16 @@ static int zfcp_fsf_setup_ct_els_sbals(s + int bytes; + + if (!(feat & FSF_FEATURE_ELS_CT_CHAINED_SBALS)) { +- if (sg_req->length > PAGE_SIZE || sg_resp->length > PAGE_SIZE || +- !sg_is_last(sg_req) || !sg_is_last(sg_resp)) ++ if (!zfcp_fsf_one_sbal(sg_req) || !zfcp_fsf_one_sbal(sg_resp)) + return -EOPNOTSUPP; + +- sbale[0].flags |= SBAL_FLAGS0_TYPE_WRITE_READ; +- sbale[2].addr = sg_virt(sg_req); +- sbale[2].length = sg_req->length; +- sbale[3].addr = sg_virt(sg_resp); +- sbale[3].length = sg_resp->length; +- sbale[3].flags |= SBAL_FLAGS_LAST_ENTRY; ++ zfcp_fsf_setup_ct_els_unchained(sbale, sg_req, sg_resp); ++ return 0; ++ } ++ ++ /* use single, unchained SBAL if it can hold the request */ ++ if (zfcp_fsf_one_sbal(sg_req) && zfcp_fsf_one_sbal(sg_resp)) { ++ zfcp_fsf_setup_ct_els_unchained(sbale, sg_req, sg_resp); + return 0; + } + +@@ -1598,10 +1616,10 @@ static void zfcp_fsf_open_wka_port_handl + case FSF_ACCESS_DENIED: + wka_port->status = ZFCP_WKA_PORT_OFFLINE; + break; +- case FSF_PORT_ALREADY_OPEN: +- break; + case FSF_GOOD: + wka_port->handle = header->port_handle; ++ /* fall through */ ++ case FSF_PORT_ALREADY_OPEN: + wka_port->status = ZFCP_WKA_PORT_ONLINE; + } + out: +@@ -2314,21 +2332,17 @@ static void zfcp_set_fcp_dl(struct fcp_c + + /** + * zfcp_fsf_send_fcp_command_task - initiate an FCP command (for a SCSI command) +- * @adapter: adapter where scsi command is issued + * @unit: unit where command is sent to + * @scsi_cmnd: scsi command to be sent +- * @timer: timer to be started when request is initiated +- * @req_flags: flags for fsf_request + */ +-int zfcp_fsf_send_fcp_command_task(struct zfcp_adapter *adapter, +- struct zfcp_unit *unit, +- struct scsi_cmnd *scsi_cmnd, +- int use_timer, int req_flags) ++int zfcp_fsf_send_fcp_command_task(struct zfcp_unit *unit, ++ struct scsi_cmnd *scsi_cmnd) + { + struct zfcp_fsf_req *req; + struct fcp_cmnd_iu *fcp_cmnd_iu; + unsigned int sbtype; + int real_bytes, retval = -EIO; ++ struct zfcp_adapter *adapter = unit->port->adapter; + + if (unlikely(!(atomic_read(&unit->status) & + ZFCP_STATUS_COMMON_UNBLOCKED))) +@@ -2339,7 +2353,8 @@ int zfcp_fsf_send_fcp_command_task(struc + atomic_inc(&adapter->qdio_outb_full); + goto out; + } +- req = zfcp_fsf_req_create(adapter, FSF_QTCB_FCP_CMND, req_flags, ++ req = zfcp_fsf_req_create(adapter, FSF_QTCB_FCP_CMND, ++ ZFCP_REQ_AUTO_CLEANUP, + adapter->pool.fsf_req_scsi); + if (IS_ERR(req)) { + retval = PTR_ERR(req); +@@ -2421,9 +2436,6 @@ int zfcp_fsf_send_fcp_command_task(struc + + zfcp_set_fcp_dl(fcp_cmnd_iu, real_bytes); + +- if (use_timer) +- zfcp_fsf_start_timer(req, ZFCP_FSF_REQUEST_TIMEOUT); +- + retval = zfcp_fsf_req_send(req); + if (unlikely(retval)) + goto failed_scsi_cmnd; +@@ -2441,19 +2453,16 @@ out: + + /** + * zfcp_fsf_send_fcp_ctm - send SCSI task management command +- * @adapter: pointer to struct zfcp-adapter + * @unit: pointer to struct zfcp_unit + * @tm_flags: unsigned byte for task management flags +- * @req_flags: int request flags + * Returns: on success pointer to struct fsf_req, NULL otherwise + */ +-struct zfcp_fsf_req *zfcp_fsf_send_fcp_ctm(struct zfcp_adapter *adapter, +- struct zfcp_unit *unit, +- u8 tm_flags, int req_flags) ++struct zfcp_fsf_req *zfcp_fsf_send_fcp_ctm(struct zfcp_unit *unit, u8 tm_flags) + { + struct qdio_buffer_element *sbale; + struct zfcp_fsf_req *req = NULL; + struct fcp_cmnd_iu *fcp_cmnd_iu; ++ struct zfcp_adapter *adapter = unit->port->adapter; + + if (unlikely(!(atomic_read(&unit->status) & + ZFCP_STATUS_COMMON_UNBLOCKED))) +@@ -2462,7 +2471,7 @@ struct zfcp_fsf_req *zfcp_fsf_send_fcp_c + spin_lock_bh(&adapter->req_q_lock); + if (zfcp_fsf_req_sbal_get(adapter)) + goto out; +- req = zfcp_fsf_req_create(adapter, FSF_QTCB_FCP_CMND, req_flags, ++ req = zfcp_fsf_req_create(adapter, FSF_QTCB_FCP_CMND, 0, + adapter->pool.fsf_req_scsi); + if (IS_ERR(req)) { + req = NULL; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_scsi.c linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_scsi.c +--- linux-2.6.27.25-0.1.1/drivers/s390/scsi/zfcp_scsi.c 2009-08-05 09:49:48.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/s390/scsi/zfcp_scsi.c 2009-08-27 12:44:29.000000000 +0100 +@@ -11,6 +11,10 @@ + #include "zfcp_ext.h" + #include + ++static unsigned int default_depth = 32; ++module_param_named(queue_depth, default_depth, uint, 0600); ++MODULE_PARM_DESC(queue_depth, "Default queue depth for new SCSI devices"); ++ + /* Find start of Sense Information in FCP response unit*/ + char *zfcp_get_fcp_sns_info_ptr(struct fcp_rsp_iu *fcp_rsp_iu) + { +@@ -23,6 +27,12 @@ char *zfcp_get_fcp_sns_info_ptr(struct f + return fcp_sns_info_ptr; + } + ++static int zfcp_scsi_change_queue_depth(struct scsi_device *sdev, int depth) ++{ ++ scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), depth); ++ return sdev->queue_depth; ++} ++ + static void zfcp_scsi_slave_destroy(struct scsi_device *sdpnt) + { + struct zfcp_unit *unit = (struct zfcp_unit *) sdpnt->hostdata; +@@ -34,7 +44,7 @@ static void zfcp_scsi_slave_destroy(stru + static int zfcp_scsi_slave_configure(struct scsi_device *sdp) + { + if (sdp->tagged_supported) +- scsi_adjust_queue_depth(sdp, MSG_SIMPLE_TAG, 32); ++ scsi_adjust_queue_depth(sdp, MSG_SIMPLE_TAG, default_depth); + else + scsi_adjust_queue_depth(sdp, 0, 1); + return 0; +@@ -94,8 +104,7 @@ static int zfcp_scsi_queuecommand(struct + return 0;; + } + +- ret = zfcp_fsf_send_fcp_command_task(adapter, unit, scpnt, 0, +- ZFCP_REQ_AUTO_CLEANUP); ++ ret = zfcp_fsf_send_fcp_command_task(unit, scpnt); + if (unlikely(ret == -EBUSY)) + return SCSI_MLQUEUE_DEVICE_BUSY; + else if (unlikely(ret < 0)) +@@ -153,79 +162,91 @@ out: + + static int zfcp_scsi_eh_abort_handler(struct scsi_cmnd *scpnt) + { +- struct Scsi_Host *scsi_host; +- struct zfcp_adapter *adapter; +- struct zfcp_unit *unit; +- struct zfcp_fsf_req *fsf_req; ++ struct Scsi_Host *scsi_host = scpnt->device->host; ++ struct zfcp_adapter *adapter = ++ (struct zfcp_adapter *) scsi_host->hostdata[0]; ++ struct zfcp_unit *unit = scpnt->device->hostdata; ++ struct zfcp_fsf_req *old_req, *abrt_req; + unsigned long flags; + unsigned long old_req_id = (unsigned long) scpnt->host_scribble; + int retval = SUCCESS; +- +- scsi_host = scpnt->device->host; +- adapter = (struct zfcp_adapter *) scsi_host->hostdata[0]; +- unit = scpnt->device->hostdata; ++ int retry = 3; + + /* avoid race condition between late normal completion and abort */ + write_lock_irqsave(&adapter->abort_lock, flags); + +- /* Check whether corresponding fsf_req is still pending */ + spin_lock(&adapter->req_list_lock); +- fsf_req = zfcp_reqlist_find(adapter, old_req_id); ++ old_req = zfcp_reqlist_find(adapter, old_req_id); + spin_unlock(&adapter->req_list_lock); +- if (!fsf_req) { ++ if (!old_req) { + write_unlock_irqrestore(&adapter->abort_lock, flags); +- zfcp_scsi_dbf_event_abort("lte1", adapter, scpnt, NULL, 0); +- return FAILED; /* completion could be in progress */ ++ zfcp_scsi_dbf_event_abort("lte1", adapter, scpnt, NULL, ++ old_req_id); ++ return SUCCESS; + } +- fsf_req->data = NULL; ++ old_req->data = NULL; + + /* don't access old fsf_req after releasing the abort_lock */ + write_unlock_irqrestore(&adapter->abort_lock, flags); + +- fsf_req = zfcp_fsf_abort_fcp_command(old_req_id, adapter, unit, 0); +- if (!fsf_req) { +- zfcp_scsi_dbf_event_abort("nres", adapter, scpnt, NULL, +- old_req_id); +- retval = FAILED; +- return retval; ++ while (retry--) { ++ abrt_req = zfcp_fsf_abort_fcp_command(old_req_id, unit); ++ if (abrt_req) ++ break; ++ ++ zfcp_erp_wait(adapter); ++ if (!(atomic_read(&adapter->status) & ++ ZFCP_STATUS_COMMON_RUNNING)) { ++ zfcp_scsi_dbf_event_abort("nres", adapter, scpnt, NULL, ++ old_req_id); ++ return SUCCESS; ++ } + } ++ if (!abrt_req) ++ return FAILED; + +- __wait_event(fsf_req->completion_wq, +- fsf_req->status & ZFCP_STATUS_FSFREQ_COMPLETED); ++ wait_event(abrt_req->completion_wq, ++ abrt_req->status & ZFCP_STATUS_FSFREQ_COMPLETED); + +- if (fsf_req->status & ZFCP_STATUS_FSFREQ_ABORTSUCCEEDED) { +- zfcp_scsi_dbf_event_abort("okay", adapter, scpnt, fsf_req, 0); +- } else if (fsf_req->status & ZFCP_STATUS_FSFREQ_ABORTNOTNEEDED) { +- zfcp_scsi_dbf_event_abort("lte2", adapter, scpnt, fsf_req, 0); +- } else { +- zfcp_scsi_dbf_event_abort("fail", adapter, scpnt, fsf_req, 0); ++ if (abrt_req->status & ZFCP_STATUS_FSFREQ_ABORTSUCCEEDED) ++ zfcp_scsi_dbf_event_abort("okay", adapter, scpnt, abrt_req, 0); ++ else if (abrt_req->status & ZFCP_STATUS_FSFREQ_ABORTNOTNEEDED) ++ zfcp_scsi_dbf_event_abort("lte2", adapter, scpnt, abrt_req, 0); ++ else { ++ zfcp_scsi_dbf_event_abort("fail", adapter, scpnt, abrt_req, 0); + retval = FAILED; + } +- zfcp_fsf_req_free(fsf_req); +- ++ zfcp_fsf_req_free(abrt_req); + return retval; + } + +-static int zfcp_task_mgmt_function(struct zfcp_unit *unit, u8 tm_flags, +- struct scsi_cmnd *scpnt) ++static int zfcp_task_mgmt_function(struct scsi_cmnd *scpnt, u8 tm_flags) + { ++ struct zfcp_unit *unit = scpnt->device->hostdata; + struct zfcp_adapter *adapter = unit->port->adapter; + struct zfcp_fsf_req *fsf_req; + int retval = SUCCESS; ++ int retry = 3; + +- /* issue task management function */ +- fsf_req = zfcp_fsf_send_fcp_ctm(adapter, unit, tm_flags, 0); +- if (!fsf_req) { +- zfcp_scsi_dbf_event_devreset("nres", tm_flags, unit, scpnt); +- return FAILED; ++ while (retry--) { ++ fsf_req = zfcp_fsf_send_fcp_ctm(unit, tm_flags); ++ if (fsf_req) ++ break; ++ ++ zfcp_erp_wait(adapter); ++ if (!(atomic_read(&adapter->status) & ++ ZFCP_STATUS_COMMON_RUNNING)) { ++ zfcp_scsi_dbf_event_devreset("nres", tm_flags, unit, ++ scpnt); ++ return SUCCESS; ++ } + } ++ if (!fsf_req) ++ return FAILED; + +- __wait_event(fsf_req->completion_wq, +- fsf_req->status & ZFCP_STATUS_FSFREQ_COMPLETED); ++ wait_event(fsf_req->completion_wq, ++ fsf_req->status & ZFCP_STATUS_FSFREQ_COMPLETED); + +- /* +- * check completion status of task management function +- */ + if (fsf_req->status & ZFCP_STATUS_FSFREQ_TMFUNCFAILED) { + zfcp_scsi_dbf_event_devreset("fail", tm_flags, unit, scpnt); + retval = FAILED; +@@ -236,39 +257,24 @@ static int zfcp_task_mgmt_function(struc + zfcp_scsi_dbf_event_devreset("okay", tm_flags, unit, scpnt); + + zfcp_fsf_req_free(fsf_req); +- + return retval; + } + + static int zfcp_scsi_eh_device_reset_handler(struct scsi_cmnd *scpnt) + { +- struct zfcp_unit *unit = scpnt->device->hostdata; +- +- if (!unit) { +- WARN_ON(1); +- return SUCCESS; +- } +- return zfcp_task_mgmt_function(unit, FCP_LOGICAL_UNIT_RESET, scpnt); ++ return zfcp_task_mgmt_function(scpnt, FCP_LOGICAL_UNIT_RESET); + } + + static int zfcp_scsi_eh_target_reset_handler(struct scsi_cmnd *scpnt) + { +- struct zfcp_unit *unit = scpnt->device->hostdata; +- +- if (!unit) { +- WARN_ON(1); +- return SUCCESS; +- } +- return zfcp_task_mgmt_function(unit, FCP_TARGET_RESET, scpnt); ++ return zfcp_task_mgmt_function(scpnt, FCP_TARGET_RESET); + } + + static int zfcp_scsi_eh_host_reset_handler(struct scsi_cmnd *scpnt) + { +- struct zfcp_unit *unit; +- struct zfcp_adapter *adapter; ++ struct zfcp_unit *unit = scpnt->device->hostdata; ++ struct zfcp_adapter *adapter = unit->port->adapter; + +- unit = scpnt->device->hostdata; +- adapter = unit->port->adapter; + zfcp_erp_adapter_reopen(adapter, 0, 141, scpnt); + zfcp_erp_wait(adapter); + +@@ -529,6 +535,9 @@ static void zfcp_scsi_rport_register(str + struct fc_rport_identifiers ids; + struct fc_rport *rport; + ++ if (port->rport) ++ return; ++ + ids.node_name = port->wwnn; + ids.port_name = port->wwpn; + ids.port_id = port->d_id; +@@ -552,8 +561,10 @@ static void zfcp_scsi_rport_block(struct + { + struct fc_rport *rport = port->rport; + +- if (rport) ++ if (rport) { + fc_remote_port_delete(rport); ++ port->rport = NULL; ++ } + } + + void zfcp_scsi_schedule_rport_register(struct zfcp_port *port) +@@ -652,6 +663,7 @@ struct zfcp_data zfcp_data = { + .name = "zfcp", + .module = THIS_MODULE, + .proc_name = "zfcp", ++ .change_queue_depth = zfcp_scsi_change_queue_depth, + .slave_alloc = zfcp_scsi_slave_alloc, + .slave_configure = zfcp_scsi_slave_configure, + .slave_destroy = zfcp_scsi_slave_destroy, +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/scsi/scsi_scan.c linux-2.6.27.29-0.1.1/drivers/scsi/scsi_scan.c +--- linux-2.6.27.25-0.1.1/drivers/scsi/scsi_scan.c 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/scsi/scsi_scan.c 2009-08-27 12:44:29.000000000 +0100 +@@ -425,6 +425,7 @@ static struct scsi_target *scsi_alloc_ta + INIT_LIST_HEAD(&starget->devices); + starget->state = STARGET_CREATED; + starget->scsi_level = SCSI_2; ++ starget->max_target_blocked = SCSI_DEFAULT_TARGET_BLOCKED; + retry: + spin_lock_irqsave(shost->host_lock, flags); + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/scsi/zalon.c linux-2.6.27.29-0.1.1/drivers/scsi/zalon.c +--- linux-2.6.27.25-0.1.1/drivers/scsi/zalon.c 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/scsi/zalon.c 2009-08-27 12:44:29.000000000 +0100 +@@ -134,7 +134,7 @@ zalon_probe(struct parisc_device *dev) + + host = ncr_attach(&zalon7xx_template, unit, &device); + if (!host) +- goto fail; ++ return -ENODEV; + + if (request_irq(dev->irq, ncr53c8xx_intr, IRQF_SHARED, "zalon", host)) { + printk(KERN_ERR "%s: irq problem with %d, detaching\n ", +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/BlkVsc.c linux-2.6.27.29-0.1.1/drivers/staging/hv/BlkVsc.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/BlkVsc.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,107 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Hank Janssen ++ * ++ */ ++ ++ ++#include "StorVsc.c" ++ ++static const char* gBlkDriverName="blkvsc"; ++ ++//{32412632-86cb-44a2-9b5c-50d1417354f5} ++static const GUID gBlkVscDeviceType={ ++ .Data = {0x32, 0x26, 0x41, 0x32, 0xcb, 0x86, 0xa2, 0x44, 0x9b, 0x5c, 0x50, 0xd1, 0x41, 0x73, 0x54, 0xf5} ++}; ++ ++// Static routines ++static int ++BlkVscOnDeviceAdd( ++ DEVICE_OBJECT *Device, ++ void *AdditionalInfo ++ ); ++ ++ ++int ++BlkVscInitialize( ++ DRIVER_OBJECT *Driver ++ ) ++{ ++ STORVSC_DRIVER_OBJECT* storDriver = (STORVSC_DRIVER_OBJECT*)Driver; ++ int ret=0; ++ ++ DPRINT_ENTER(BLKVSC); ++ ++ // Make sure we are at least 2 pages since 1 page is used for control ++ ASSERT(storDriver->RingBufferSize >= (PAGE_SIZE << 1)); ++ ++ Driver->name = gBlkDriverName; ++ memcpy(&Driver->deviceType, &gBlkVscDeviceType, sizeof(GUID)); ++ ++ storDriver->RequestExtSize = sizeof(STORVSC_REQUEST_EXTENSION); ++ // Divide the ring buffer data size (which is 1 page less than the ring buffer size since that page is reserved for the ring buffer indices) ++ // by the max request size (which is VMBUS_CHANNEL_PACKET_MULITPAGE_BUFFER + VSTOR_PACKET + UINT64) ++ storDriver->MaxOutstandingRequestsPerChannel = ++ ((storDriver->RingBufferSize - PAGE_SIZE) / ALIGN_UP(MAX_MULTIPAGE_BUFFER_PACKET + sizeof(VSTOR_PACKET) + sizeof(UINT64),sizeof(UINT64))); ++ ++ DPRINT_INFO(BLKVSC, "max io outstd %u", storDriver->MaxOutstandingRequestsPerChannel); ++ ++ // Setup the dispatch table ++ storDriver->Base.OnDeviceAdd = BlkVscOnDeviceAdd; ++ storDriver->Base.OnDeviceRemove = StorVscOnDeviceRemove; ++ storDriver->Base.OnCleanup = StorVscOnCleanup; ++ ++ storDriver->OnIORequest = StorVscOnIORequest; ++ ++ DPRINT_EXIT(BLKVSC); ++ ++ return ret; ++} ++ ++int ++BlkVscOnDeviceAdd( ++ DEVICE_OBJECT *Device, ++ void *AdditionalInfo ++ ) ++{ ++ int ret=0; ++ STORVSC_DEVICE_INFO *deviceInfo = (STORVSC_DEVICE_INFO*)AdditionalInfo; ++ ++ DPRINT_ENTER(BLKVSC); ++ ++ ret = StorVscOnDeviceAdd(Device, AdditionalInfo); ++ ++ if (ret != 0) ++ { ++ DPRINT_EXIT(BLKVSC); ++ ++ return ret; ++ } ++ ++ // We need to use the device instance guid to set the path and target id. For IDE devices, the ++ // device instance id is formatted as - - 8899 - 000000000000. ++ deviceInfo->PathId = Device->deviceInstance.Data[3] << 24 | Device->deviceInstance.Data[2] << 16 | ++ Device->deviceInstance.Data[1] << 8 |Device->deviceInstance.Data[0]; ++ ++ deviceInfo->TargetId = Device->deviceInstance.Data[5] << 8 | Device->deviceInstance.Data[4]; ++ ++ DPRINT_EXIT(BLKVSC); ++ ++ return ret; ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/blkvsc_drv.c linux-2.6.27.29-0.1.1/drivers/staging/hv/blkvsc_drv.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/blkvsc_drv.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,1548 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Hank Janssen ++ * ++ */ ++ ++#define KERNEL_2_6_27 ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "include/logging.h" ++#include "include/vmbus.h" ++ ++#include "include/StorVscApi.h" ++ ++// ++// #defines ++// ++#define BLKVSC_MINORS 64 ++ ++// ++// Data types ++// ++enum blkvsc_device_type { ++ UNKNOWN_DEV_TYPE, ++ HARDDISK_TYPE, ++ DVD_TYPE, ++}; ++ ++// This request ties the struct request and struct blkvsc_request/STORVSC_REQUEST together ++// A struct request may be represented by 1 or more struct blkvsc_request ++struct blkvsc_request_group { ++ int outstanding; ++ int status; ++ ++ struct list_head blkvsc_req_list; // list of blkvsc_requests ++}; ++ ++ ++struct blkvsc_request { ++ struct list_head req_entry; // blkvsc_request_group.blkvsc_req_list ++ ++ struct list_head pend_entry; // block_device_context.pending_list ++ ++ struct request *req; // This may be null if we generate a request internally ++ struct block_device_context *dev; ++ struct blkvsc_request_group *group; // The group this request is part of. Maybe null ++ ++ wait_queue_head_t wevent; ++ int cond; ++ ++ int write; ++ sector_t sector_start; ++ unsigned long sector_count; ++ ++ unsigned char sense_buffer[SCSI_SENSE_BUFFERSIZE]; ++ unsigned char cmd_len; ++ unsigned char cmnd[MAX_COMMAND_SIZE]; ++ ++ STORVSC_REQUEST request; ++ // !!!DO NOT ADD ANYTHING BELOW HERE!!! Otherwise, memory can overlap, because - ++ // The extension buffer falls right here and is pointed to by request.Extension; ++}; ++ ++// Per device structure ++struct block_device_context { ++ struct device_context *device_ctx; // point back to our device context ++ struct kmem_cache *request_pool; ++ spinlock_t lock; ++ struct gendisk *gd; ++ enum blkvsc_device_type device_type; ++ struct list_head pending_list; ++ ++ unsigned char device_id[64]; ++ unsigned int device_id_len; ++ int num_outstanding_reqs; ++ int shutting_down; ++ int media_not_present; ++ unsigned int sector_size; ++ sector_t capacity; ++ unsigned int port; ++ unsigned char path; ++ unsigned char target; ++ int users; ++}; ++ ++// Per driver ++struct blkvsc_driver_context { ++ // !! These must be the first 2 fields !! ++ struct driver_context drv_ctx; ++ STORVSC_DRIVER_OBJECT drv_obj; ++}; ++ ++// Static decl ++static int blkvsc_probe(struct device *dev); ++static int blkvsc_remove(struct device *device); ++static void blkvsc_shutdown(struct device *device); ++ ++static int blkvsc_open(struct inode *inode, struct file *filep); ++static int blkvsc_release(struct inode *inode, struct file *filep); ++static int blkvsc_media_changed(struct gendisk *gd); ++static int blkvsc_revalidate_disk(struct gendisk *gd); ++static int blkvsc_getgeo(struct block_device *bd, struct hd_geometry *hg); ++static int blkvsc_ioctl(struct inode *inode, struct file *filep, unsigned cmd, unsigned long arg); ++ ++static void blkvsc_request(struct request_queue *queue); ++static void blkvsc_request_completion(STORVSC_REQUEST* request); ++static int blkvsc_do_request(struct block_device_context *blkdev, struct request *req); ++static int blkvsc_submit_request(struct blkvsc_request *blkvsc_req, void (*request_completion)(STORVSC_REQUEST*) ); ++static void blkvsc_init_rw(struct blkvsc_request *blkvsc_req); ++static void blkvsc_cmd_completion(STORVSC_REQUEST* request); ++static int blkvsc_do_inquiry(struct block_device_context *blkdev); ++static int blkvsc_do_read_capacity(struct block_device_context *blkdev); ++static int blkvsc_do_read_capacity16(struct block_device_context *blkdev); ++static int blkvsc_do_flush(struct block_device_context *blkdev); ++static int blkvsc_cancel_pending_reqs(struct block_device_context *blkdev); ++static int blkvsc_do_pending_reqs(struct block_device_context *blkdev); ++ ++ ++static int blkvsc_ringbuffer_size = BLKVSC_RING_BUFFER_SIZE; ++ ++// The one and only one ++static struct blkvsc_driver_context g_blkvsc_drv; ++ ++ ++static struct block_device_operations block_ops = ++{ ++ .owner = THIS_MODULE, ++ .open = blkvsc_open, ++ .release = blkvsc_release, ++ .media_changed = blkvsc_media_changed, ++ .revalidate_disk = blkvsc_revalidate_disk, ++ .getgeo = blkvsc_getgeo, ++ .ioctl = blkvsc_ioctl, ++}; ++ ++/*++ ++ ++Name: blkvsc_drv_init() ++ ++Desc: BlkVsc driver initialization. ++ ++--*/ ++int blkvsc_drv_init(PFN_DRIVERINITIALIZE pfn_drv_init) ++{ ++ int ret=0; ++ STORVSC_DRIVER_OBJECT *storvsc_drv_obj=&g_blkvsc_drv.drv_obj; ++ struct driver_context *drv_ctx=&g_blkvsc_drv.drv_ctx; ++ ++ DPRINT_ENTER(BLKVSC_DRV); ++ ++ vmbus_get_interface(&storvsc_drv_obj->Base.VmbusChannelInterface); ++ ++ storvsc_drv_obj->RingBufferSize = blkvsc_ringbuffer_size; ++ ++ // Callback to client driver to complete the initialization ++ pfn_drv_init(&storvsc_drv_obj->Base); ++ ++ drv_ctx->driver.name = storvsc_drv_obj->Base.name; ++ memcpy(&drv_ctx->class_id, &storvsc_drv_obj->Base.deviceType, sizeof(GUID)); ++ ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++ drv_ctx->driver.probe = blkvsc_probe; ++ drv_ctx->driver.remove = blkvsc_remove; ++#else ++ drv_ctx->probe = blkvsc_probe; ++ drv_ctx->remove = blkvsc_remove; ++ drv_ctx->shutdown = blkvsc_shutdown; ++#endif ++ ++ // The driver belongs to vmbus ++ vmbus_child_driver_register(drv_ctx); ++ ++ DPRINT_EXIT(BLKVSC_DRV); ++ ++ return ret; ++} ++ ++ ++static int blkvsc_drv_exit_cb(struct device *dev, void *data) ++{ ++ struct device **curr = (struct device **)data; ++ *curr = dev; ++ return 1; // stop iterating ++} ++ ++/*++ ++ ++Name: blkvsc_drv_exit() ++ ++Desc: ++ ++--*/ ++void blkvsc_drv_exit(void) ++{ ++ STORVSC_DRIVER_OBJECT *storvsc_drv_obj=&g_blkvsc_drv.drv_obj; ++ struct driver_context *drv_ctx=&g_blkvsc_drv.drv_ctx; ++ ++ struct device *current_dev=NULL; ++ ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++#define driver_for_each_device(drv, start, data, fn) \ ++ struct list_head *ptr, *n; \ ++ list_for_each_safe(ptr, n, &((drv)->devices)) {\ ++ struct device *curr_dev;\ ++ curr_dev = list_entry(ptr, struct device, driver_list);\ ++ fn(curr_dev, data);\ ++ } ++#endif // KERNEL_2_6_9 ++ ++ DPRINT_ENTER(BLKVSC_DRV); ++ ++ while (1) ++ { ++ current_dev = NULL; ++ ++ // Get the device ++ driver_for_each_device(&drv_ctx->driver, NULL, (void*)¤t_dev, blkvsc_drv_exit_cb); ++ ++ if (current_dev == NULL) ++ break; ++ ++ // Initiate removal from the top-down ++ device_unregister(current_dev); ++ } ++ ++ if (storvsc_drv_obj->Base.OnCleanup) ++ storvsc_drv_obj->Base.OnCleanup(&storvsc_drv_obj->Base); ++ ++ vmbus_child_driver_unregister(drv_ctx); ++ ++ DPRINT_EXIT(BLKVSC_DRV); ++ ++ return; ++} ++ ++/*++ ++ ++Name: blkvsc_probe() ++ ++Desc: Add a new device for this driver ++ ++--*/ ++static int blkvsc_probe(struct device *device) ++{ ++ int ret=0; ++ ++ struct driver_context *driver_ctx = driver_to_driver_context(device->driver); ++ struct blkvsc_driver_context *blkvsc_drv_ctx = (struct blkvsc_driver_context*)driver_ctx; ++ STORVSC_DRIVER_OBJECT* storvsc_drv_obj = &blkvsc_drv_ctx->drv_obj; ++ ++ struct device_context *device_ctx = device_to_device_context(device); ++ DEVICE_OBJECT* device_obj = &device_ctx->device_obj; ++ ++ struct block_device_context *blkdev=NULL; ++ STORVSC_DEVICE_INFO device_info; ++ int major=0; ++ int devnum=0; ++ ++ static int ide0_registered=0; ++ static int ide1_registered=0; ++ ++ DPRINT_ENTER(BLKVSC_DRV); ++ ++ DPRINT_DBG(BLKVSC_DRV, "blkvsc_probe - enter"); ++ ++ if (!storvsc_drv_obj->Base.OnDeviceAdd) ++ { ++ DPRINT_ERR(BLKVSC_DRV, "OnDeviceAdd() not set"); ++ ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ blkdev = kzalloc(sizeof(struct block_device_context), GFP_KERNEL); ++ if (!blkdev) ++ { ++ ret = -ENOMEM; ++ goto Cleanup; ++ } ++ ++ INIT_LIST_HEAD(&blkdev->pending_list); ++ ++ // Initialize what we can here ++ spin_lock_init(&blkdev->lock); ++ ++ ASSERT(sizeof(struct blkvsc_request_group) <= sizeof(struct blkvsc_request)); ++ ++#ifdef KERNEL_2_6_27 ++ blkdev->request_pool = kmem_cache_create(dev_name(&device_ctx->device), ++ sizeof(struct blkvsc_request) + storvsc_drv_obj->RequestExtSize, 0, ++ SLAB_HWCACHE_ALIGN, NULL); ++#else ++ blkdev->request_pool = kmem_cache_create(device_ctx->device.bus_id, ++ sizeof(struct blkvsc_request) + storvsc_drv_obj->RequestExtSize, 0, ++ SLAB_HWCACHE_ALIGN, NULL, NULL); ++#endif ++ if (!blkdev->request_pool) ++ { ++ ret = -ENOMEM; ++ goto Cleanup; ++ } ++ ++ ++ // Call to the vsc driver to add the device ++ ret = storvsc_drv_obj->Base.OnDeviceAdd(device_obj, &device_info); ++ if (ret != 0) ++ { ++ DPRINT_ERR(BLKVSC_DRV, "unable to add blkvsc device"); ++ goto Cleanup; ++ } ++ ++ blkdev->device_ctx = device_ctx; ++ blkdev->target = device_info.TargetId; // this identified the device 0 or 1 ++ blkdev->path = device_info.PathId; // this identified the ide ctrl 0 or 1 ++ ++ dev_set_drvdata(device, blkdev); ++ ++ // Calculate the major and device num ++ if (blkdev->path == 0) ++ { ++ major = IDE0_MAJOR; ++ devnum = blkdev->path + blkdev->target; // 0 or 1 ++ ++ if (!ide0_registered) ++ { ++ ret = register_blkdev(major, "ide"); ++ if (ret != 0) ++ { ++ DPRINT_ERR(BLKVSC_DRV, "register_blkdev() failed! ret %d", ret); ++ goto Remove; ++ } ++ ++ ide0_registered = 1; ++ } ++ } ++ else if (blkdev->path == 1) ++ { ++ major = IDE1_MAJOR; ++ devnum = blkdev->path + blkdev->target + 1; // 2 or 3 ++ ++ if (!ide1_registered) ++ { ++ ret = register_blkdev(major, "ide"); ++ if (ret != 0) ++ { ++ DPRINT_ERR(BLKVSC_DRV, "register_blkdev() failed! ret %d", ret); ++ goto Remove; ++ } ++ ++ ide1_registered = 1; ++ } ++ ++ } ++ else ++ { ++ DPRINT_ERR(BLKVSC_DRV, "invalid pathid"); ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ DPRINT_INFO(BLKVSC_DRV, "blkvsc registered for major %d!!", major); ++ ++ blkdev->gd = alloc_disk(BLKVSC_MINORS); ++ if (!blkdev->gd) ++ { ++ DPRINT_ERR(BLKVSC_DRV, "register_blkdev() failed! ret %d", ret); ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ blkdev->gd->queue = blk_init_queue(blkvsc_request, &blkdev->lock); ++ ++ blk_queue_max_segment_size(blkdev->gd->queue, PAGE_SIZE); ++ blk_queue_max_phys_segments(blkdev->gd->queue, MAX_MULTIPAGE_BUFFER_COUNT); ++ blk_queue_max_hw_segments(blkdev->gd->queue, MAX_MULTIPAGE_BUFFER_COUNT); ++ blk_queue_segment_boundary(blkdev->gd->queue, PAGE_SIZE-1); ++ blk_queue_bounce_limit(blkdev->gd->queue, BLK_BOUNCE_ANY); ++ blk_queue_dma_alignment(blkdev->gd->queue, 511); ++ ++ blkdev->gd->major = major; ++ if (devnum == 1 || devnum == 3) ++ blkdev->gd->first_minor = BLKVSC_MINORS; ++ else ++ blkdev->gd->first_minor = 0; ++ blkdev->gd->fops = &block_ops; ++ blkdev->gd->private_data = blkdev; ++ sprintf(blkdev->gd->disk_name, "hd%c", 'a'+ devnum); ++ ++ blkvsc_do_inquiry(blkdev); ++ if (blkdev->device_type == DVD_TYPE) ++ { ++ set_disk_ro(blkdev->gd, 1); ++ blkdev->gd->flags |= GENHD_FL_REMOVABLE; ++ blkvsc_do_read_capacity(blkdev); ++ } ++ else ++ { ++ blkvsc_do_read_capacity16(blkdev); ++ } ++ ++ set_capacity(blkdev->gd, blkdev->capacity * (blkdev->sector_size/512)); ++ blk_queue_hardsect_size(blkdev->gd->queue, blkdev->sector_size); ++ // go! ++ add_disk(blkdev->gd); ++ ++ DPRINT_INFO(BLKVSC_DRV, "%s added!! capacity %llu sector_size %d", blkdev->gd->disk_name, blkdev->capacity, blkdev->sector_size); ++ ++ return ret; ++ ++Remove: ++ storvsc_drv_obj->Base.OnDeviceRemove(device_obj); ++ ++Cleanup: ++ if (blkdev) ++ { ++ if (blkdev->request_pool) ++ { ++ kmem_cache_destroy(blkdev->request_pool); ++ blkdev->request_pool = NULL; ++ } ++ kfree(blkdev); ++ blkdev = NULL; ++ } ++ ++ DPRINT_EXIT(BLKVSC_DRV); ++ ++ return ret; ++} ++ ++static void blkvsc_shutdown(struct device *device) ++{ ++ struct block_device_context *blkdev = dev_get_drvdata(device); ++ unsigned long flags; ++ ++ if (!blkdev) ++ return; ++ ++ DPRINT_DBG(BLKVSC_DRV, "blkvsc_shutdown - users %d disk %s\n", blkdev->users, blkdev->gd->disk_name); ++ ++ spin_lock_irqsave(&blkdev->lock, flags); ++ ++ blkdev->shutting_down = 1; ++ ++ blk_stop_queue(blkdev->gd->queue); ++ ++ spin_unlock_irqrestore(&blkdev->lock, flags); ++ ++ while (blkdev->num_outstanding_reqs) ++ { ++ DPRINT_INFO(STORVSC, "waiting for %d requests to complete...", blkdev->num_outstanding_reqs); ++ ++ udelay(100); ++ } ++ ++ blkvsc_do_flush(blkdev); ++ ++ spin_lock_irqsave(&blkdev->lock, flags); ++ ++ blkvsc_cancel_pending_reqs(blkdev); ++ ++ spin_unlock_irqrestore(&blkdev->lock, flags); ++} ++ ++static int blkvsc_do_flush(struct block_device_context *blkdev) ++{ ++ struct blkvsc_request *blkvsc_req=NULL; ++ ++ DPRINT_DBG(BLKVSC_DRV, "blkvsc_do_flush()\n"); ++ ++ if (blkdev->device_type != HARDDISK_TYPE) ++ return 0; ++ ++ blkvsc_req = kmem_cache_alloc(blkdev->request_pool, GFP_KERNEL); ++ if (!blkvsc_req) ++ { ++ return -ENOMEM; ++ } ++ ++ memset(blkvsc_req, 0, sizeof(struct blkvsc_request)); ++ init_waitqueue_head(&blkvsc_req->wevent); ++ blkvsc_req->dev = blkdev; ++ blkvsc_req->req = NULL; ++ blkvsc_req->write = 0; ++ ++ blkvsc_req->request.DataBuffer.PfnArray[0] = 0; ++ blkvsc_req->request.DataBuffer.Offset = 0; ++ blkvsc_req->request.DataBuffer.Length = 0; ++ ++ blkvsc_req->cmnd[0] = SYNCHRONIZE_CACHE; ++ blkvsc_req->cmd_len = 10; ++ ++ // Set this here since the completion routine may be invoked and completed before we return ++ blkvsc_req->cond =0; ++ blkvsc_submit_request(blkvsc_req, blkvsc_cmd_completion); ++ ++ wait_event_interruptible(blkvsc_req->wevent, blkvsc_req->cond); ++ ++ kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req); ++ ++ return 0; ++} ++ ++// Do a scsi INQUIRY cmd here to get the device type (ie disk or dvd) ++static int blkvsc_do_inquiry(struct block_device_context *blkdev) ++{ ++ struct blkvsc_request *blkvsc_req=NULL; ++ struct page *page_buf; ++ unsigned char *buf; ++ unsigned char device_type; ++ ++ DPRINT_DBG(BLKVSC_DRV, "blkvsc_do_inquiry()\n"); ++ ++ blkvsc_req = kmem_cache_alloc(blkdev->request_pool, GFP_KERNEL); ++ if (!blkvsc_req) ++ { ++ return -ENOMEM; ++ } ++ ++ memset(blkvsc_req, 0, sizeof(struct blkvsc_request)); ++ page_buf = alloc_page(GFP_KERNEL); ++ if (!page_buf) ++ { ++ kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req); ++ return -ENOMEM; ++ } ++ ++ init_waitqueue_head(&blkvsc_req->wevent); ++ blkvsc_req->dev = blkdev; ++ blkvsc_req->req = NULL; ++ blkvsc_req->write = 0; ++ ++ blkvsc_req->request.DataBuffer.PfnArray[0] = page_to_pfn(page_buf); ++ blkvsc_req->request.DataBuffer.Offset = 0; ++ blkvsc_req->request.DataBuffer.Length = 64; ++ ++ blkvsc_req->cmnd[0] = INQUIRY; ++ blkvsc_req->cmnd[1] = 0x1; // Get product data ++ blkvsc_req->cmnd[2] = 0x83; // mode page 83 ++ blkvsc_req->cmnd[4] = 64; ++ blkvsc_req->cmd_len = 6; ++ ++ // Set this here since the completion routine may be invoked and completed before we return ++ blkvsc_req->cond =0; ++ ++ blkvsc_submit_request(blkvsc_req, blkvsc_cmd_completion); ++ ++ DPRINT_DBG(BLKVSC_DRV, "waiting %p to complete - cond %d\n", blkvsc_req, blkvsc_req->cond); ++ ++ wait_event_interruptible(blkvsc_req->wevent, blkvsc_req->cond); ++ ++ buf = kmap(page_buf); ++ ++ //PrintBytes(buf, 64); ++ // be to le ++ device_type = buf[0] & 0x1F; ++ ++ if (device_type == 0x0) ++ { ++ blkdev->device_type = HARDDISK_TYPE; ++ } ++ else if (device_type == 0x5) ++ { ++ blkdev->device_type = DVD_TYPE; ++ } ++ else ++ { ++ // TODO: this is currently unsupported device type ++ blkdev->device_type = UNKNOWN_DEV_TYPE; ++ } ++ ++ DPRINT_DBG(BLKVSC_DRV, "device type %d \n", device_type); ++ ++ blkdev->device_id_len = buf[7]; ++ if (blkdev->device_id_len > 64) ++ blkdev->device_id_len = 64; ++ ++ memcpy(blkdev->device_id, &buf[8], blkdev->device_id_len); ++ //PrintBytes(blkdev->device_id, blkdev->device_id_len); ++ ++ kunmap(page_buf); ++ ++ __free_page(page_buf); ++ ++ kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req); ++ ++ return 0; ++} ++ ++// Do a scsi READ_CAPACITY cmd here to get the size of the disk ++static int blkvsc_do_read_capacity(struct block_device_context *blkdev) ++{ ++ struct blkvsc_request *blkvsc_req=NULL; ++ struct page *page_buf; ++ unsigned char *buf; ++ struct scsi_sense_hdr sense_hdr; ++ ++ DPRINT_DBG(BLKVSC_DRV, "blkvsc_do_read_capacity()\n"); ++ ++ blkdev->sector_size = 0; ++ blkdev->capacity = 0; ++ blkdev->media_not_present = 0; // assume a disk is present ++ ++ blkvsc_req = kmem_cache_alloc(blkdev->request_pool, GFP_KERNEL); ++ if (!blkvsc_req) ++ { ++ return -ENOMEM; ++ } ++ ++ memset(blkvsc_req, 0, sizeof(struct blkvsc_request)); ++ page_buf = alloc_page(GFP_KERNEL); ++ if (!page_buf) ++ { ++ kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req); ++ return -ENOMEM; ++ } ++ ++ init_waitqueue_head(&blkvsc_req->wevent); ++ blkvsc_req->dev = blkdev; ++ blkvsc_req->req = NULL; ++ blkvsc_req->write = 0; ++ ++ blkvsc_req->request.DataBuffer.PfnArray[0] = page_to_pfn(page_buf); ++ blkvsc_req->request.DataBuffer.Offset = 0; ++ blkvsc_req->request.DataBuffer.Length = 8; ++ ++ blkvsc_req->cmnd[0] = READ_CAPACITY; ++ blkvsc_req->cmd_len = 16; ++ ++ // Set this here since the completion routine may be invoked and completed before we return ++ blkvsc_req->cond =0; ++ ++ blkvsc_submit_request(blkvsc_req, blkvsc_cmd_completion); ++ ++ DPRINT_DBG(BLKVSC_DRV, "waiting %p to complete - cond %d\n", blkvsc_req, blkvsc_req->cond); ++ ++ wait_event_interruptible(blkvsc_req->wevent, blkvsc_req->cond); ++ ++ // check error ++ if (blkvsc_req->request.Status) ++ { ++ scsi_normalize_sense(blkvsc_req->sense_buffer, SCSI_SENSE_BUFFERSIZE, &sense_hdr); ++ ++ if (sense_hdr.asc == 0x3A) // Medium not present ++ { ++ blkdev->media_not_present = 1; ++ } ++ ++ return 0; ++ } ++ buf = kmap(page_buf); ++ ++ // be to le ++ blkdev->capacity = ((buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]) + 1; ++ blkdev->sector_size = (buf[4] << 24) | (buf[5] << 16) | (buf[6] << 8) | buf[7]; ++ ++ kunmap(page_buf); ++ ++ __free_page(page_buf); ++ ++ kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req); ++ ++ return 0; ++} ++ ++ ++static int blkvsc_do_read_capacity16(struct block_device_context *blkdev) ++{ ++ struct blkvsc_request *blkvsc_req=NULL; ++ struct page *page_buf; ++ unsigned char *buf; ++ struct scsi_sense_hdr sense_hdr; ++ ++ DPRINT_DBG(BLKVSC_DRV, "blkvsc_do_read_capacity16()\n"); ++ ++ blkdev->sector_size = 0; ++ blkdev->capacity = 0; ++ blkdev->media_not_present = 0; // assume a disk is present ++ ++ blkvsc_req = kmem_cache_alloc(blkdev->request_pool, GFP_KERNEL); ++ if (!blkvsc_req) ++ { ++ return -ENOMEM; ++ } ++ ++ memset(blkvsc_req, 0, sizeof(struct blkvsc_request)); ++ page_buf = alloc_page(GFP_KERNEL); ++ if (!page_buf) ++ { ++ kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req); ++ return -ENOMEM; ++ } ++ ++ init_waitqueue_head(&blkvsc_req->wevent); ++ blkvsc_req->dev = blkdev; ++ blkvsc_req->req = NULL; ++ blkvsc_req->write = 0; ++ ++ blkvsc_req->request.DataBuffer.PfnArray[0] = page_to_pfn(page_buf); ++ blkvsc_req->request.DataBuffer.Offset = 0; ++ blkvsc_req->request.DataBuffer.Length = 12; ++ ++ blkvsc_req->cmnd[0] = 0x9E; //READ_CAPACITY16; ++ blkvsc_req->cmd_len = 16; ++ ++ // Set this here since the completion routine may be invoked and completed before we return ++ blkvsc_req->cond =0; ++ ++ blkvsc_submit_request(blkvsc_req, blkvsc_cmd_completion); ++ ++ DPRINT_DBG(BLKVSC_DRV, "waiting %p to complete - cond %d\n", blkvsc_req, blkvsc_req->cond); ++ ++ wait_event_interruptible(blkvsc_req->wevent, blkvsc_req->cond); ++ ++ // check error ++ if (blkvsc_req->request.Status) ++ { ++ scsi_normalize_sense(blkvsc_req->sense_buffer, SCSI_SENSE_BUFFERSIZE, &sense_hdr); ++ ++ if (sense_hdr.asc == 0x3A) // Medium not present ++ { ++ blkdev->media_not_present = 1; ++ } ++ ++ return 0; ++ } ++ buf = kmap(page_buf); ++ ++ // be to le ++ blkdev->capacity = be64_to_cpu(*(unsigned long long*) &buf[0]) + 1; ++ blkdev->sector_size = be32_to_cpu(*(unsigned int*)&buf[8]); ++ ++ //blkdev->capacity = ((buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]) + 1; ++ //blkdev->sector_size = (buf[4] << 24) | (buf[5] << 16) | (buf[6] << 8) | buf[7]; ++ ++ kunmap(page_buf); ++ ++ __free_page(page_buf); ++ ++ kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req); ++ ++ return 0; ++} ++ ++/*++ ++ ++Name: blkvsc_remove() ++ ++Desc: Callback when our device is removed ++ ++--*/ ++static int blkvsc_remove(struct device *device) ++{ ++ int ret=0; ++ ++ struct driver_context *driver_ctx = driver_to_driver_context(device->driver); ++ struct blkvsc_driver_context *blkvsc_drv_ctx = (struct blkvsc_driver_context*)driver_ctx; ++ STORVSC_DRIVER_OBJECT* storvsc_drv_obj = &blkvsc_drv_ctx->drv_obj; ++ ++ struct device_context *device_ctx = device_to_device_context(device); ++ DEVICE_OBJECT* device_obj = &device_ctx->device_obj; ++ struct block_device_context *blkdev = dev_get_drvdata(device); ++ unsigned long flags; ++ ++ DPRINT_ENTER(BLKVSC_DRV); ++ ++ DPRINT_DBG(BLKVSC_DRV, "blkvsc_remove()\n"); ++ ++ if (!storvsc_drv_obj->Base.OnDeviceRemove) ++ { ++ DPRINT_EXIT(BLKVSC_DRV); ++ return -1; ++ } ++ ++ // Call to the vsc driver to let it know that the device is being removed ++ ret = storvsc_drv_obj->Base.OnDeviceRemove(device_obj); ++ if (ret != 0) ++ { ++ // TODO: ++ DPRINT_ERR(BLKVSC_DRV, "unable to remove blkvsc device (ret %d)", ret); ++ } ++ ++ // Get to a known state ++ spin_lock_irqsave(&blkdev->lock, flags); ++ ++ blkdev->shutting_down = 1; ++ ++ blk_stop_queue(blkdev->gd->queue); ++ ++ spin_unlock_irqrestore(&blkdev->lock, flags); ++ ++ while (blkdev->num_outstanding_reqs) ++ { ++ DPRINT_INFO(STORVSC, "waiting for %d requests to complete...", blkdev->num_outstanding_reqs); ++ ++ udelay(100); ++ } ++ ++ blkvsc_do_flush(blkdev); ++ ++ spin_lock_irqsave(&blkdev->lock, flags); ++ ++ blkvsc_cancel_pending_reqs(blkdev); ++ ++ spin_unlock_irqrestore(&blkdev->lock, flags); ++ ++ blk_cleanup_queue(blkdev->gd->queue); ++ ++ del_gendisk(blkdev->gd); ++ ++ kmem_cache_destroy(blkdev->request_pool); ++ ++ kfree(blkdev); ++ ++ DPRINT_EXIT(BLKVSC_DRV); ++ ++ return ret; ++} ++ ++static void blkvsc_init_rw(struct blkvsc_request *blkvsc_req) ++{ ++ ASSERT(blkvsc_req->req); ++ ASSERT(blkvsc_req->sector_count <= (MAX_MULTIPAGE_BUFFER_COUNT*8)); ++ ++ blkvsc_req->cmd_len = 16; ++ ++ if (blkvsc_req->sector_start > 0xffffffff) ++ { ++ if (rq_data_dir(blkvsc_req->req)) ++ { ++ blkvsc_req->write = 1; ++ blkvsc_req->cmnd[0] = WRITE_16; ++ } ++ else ++ { ++ blkvsc_req->write = 0; ++ blkvsc_req->cmnd[0] = READ_16; ++ } ++ ++ blkvsc_req->cmnd[1] |= blk_fua_rq(blkvsc_req->req) ? 0x8 : 0; ++ ++ *(unsigned long long*)&blkvsc_req->cmnd[2] = cpu_to_be64(blkvsc_req->sector_start); ++ *(unsigned int*)&blkvsc_req->cmnd[10] = cpu_to_be32(blkvsc_req->sector_count); ++ } ++ else if ((blkvsc_req->sector_count > 0xff) || (blkvsc_req->sector_start > 0x1fffff)) ++ { ++ if (rq_data_dir(blkvsc_req->req)) ++ { ++ blkvsc_req->write = 1; ++ blkvsc_req->cmnd[0] = WRITE_10; ++ } ++ else ++ { ++ blkvsc_req->write = 0; ++ blkvsc_req->cmnd[0] = READ_10; ++ } ++ ++ blkvsc_req->cmnd[1] |= blk_fua_rq(blkvsc_req->req) ? 0x8 : 0; ++ ++ *(unsigned int *)&blkvsc_req->cmnd[2] = cpu_to_be32(blkvsc_req->sector_start); ++ *(unsigned short*)&blkvsc_req->cmnd[7] = cpu_to_be16(blkvsc_req->sector_count); ++ } ++ else ++ { ++ if (rq_data_dir(blkvsc_req->req)) ++ { ++ blkvsc_req->write = 1; ++ blkvsc_req->cmnd[0] = WRITE_6; ++ } ++ else ++ { ++ blkvsc_req->write = 0; ++ blkvsc_req->cmnd[0] = READ_6; ++ } ++ ++ *(unsigned int *)&blkvsc_req->cmnd[1] = cpu_to_be32(blkvsc_req->sector_start) >> 8; ++ blkvsc_req->cmnd[1] &= 0x1f; ++ blkvsc_req->cmnd[4] = (unsigned char) blkvsc_req->sector_count; ++ } ++} ++ ++static int blkvsc_submit_request(struct blkvsc_request *blkvsc_req, void (*request_completion)(STORVSC_REQUEST*) ) ++{ ++ struct block_device_context *blkdev = blkvsc_req->dev; ++ struct device_context *device_ctx=blkdev->device_ctx; ++ struct driver_context *driver_ctx = driver_to_driver_context(device_ctx->device.driver); ++ struct blkvsc_driver_context *blkvsc_drv_ctx = (struct blkvsc_driver_context*)driver_ctx; ++ STORVSC_DRIVER_OBJECT* storvsc_drv_obj = &blkvsc_drv_ctx->drv_obj; ++ int ret =0; ++ ++ STORVSC_REQUEST *storvsc_req; ++ ++ DPRINT_DBG(BLKVSC_DRV, "blkvsc_submit_request() - req %p type %s start_sector %llu count %d offset %d len %d\n", ++ blkvsc_req, ++ (blkvsc_req->write)?"WRITE":"READ", ++ blkvsc_req->sector_start, ++ blkvsc_req->sector_count, ++ blkvsc_req->request.DataBuffer.Offset, ++ blkvsc_req->request.DataBuffer.Length); ++ ++ /*for (i=0; i < (blkvsc_req->request.DataBuffer.Length >> 12); i++) ++ { ++ DPRINT_DBG(BLKVSC_DRV, "blkvsc_submit_request() - req %p pfn[%d] %llx\n", ++ blkvsc_req, ++ i, ++ blkvsc_req->request.DataBuffer.PfnArray[i]); ++ }*/ ++ ++ storvsc_req = &blkvsc_req->request; ++ storvsc_req->Extension = (void*)((unsigned long)blkvsc_req + sizeof(struct blkvsc_request)); ++ ++ storvsc_req->Type = blkvsc_req->write? WRITE_TYPE : READ_TYPE; ++ ++ storvsc_req->OnIOCompletion = request_completion; ++ storvsc_req->Context = blkvsc_req; ++ ++ storvsc_req->Host = blkdev->port; ++ storvsc_req->Bus = blkdev->path; ++ storvsc_req->TargetId = blkdev->target; ++ storvsc_req->LunId = 0; // this is not really used at all ++ ++ storvsc_req->CdbLen = blkvsc_req->cmd_len; ++ storvsc_req->Cdb = blkvsc_req->cmnd; ++ ++ storvsc_req->SenseBuffer = blkvsc_req->sense_buffer; ++ storvsc_req->SenseBufferSize = SCSI_SENSE_BUFFERSIZE; ++ ++ ret = storvsc_drv_obj->OnIORequest(&blkdev->device_ctx->device_obj, &blkvsc_req->request); ++ if (ret == 0) ++ { ++ blkdev->num_outstanding_reqs++; ++ } ++ ++ return ret; ++} ++ ++// ++// We break the request into 1 or more blkvsc_requests and submit them. ++// If we cant submit them all, we put them on the pending_list. The ++// blkvsc_request() will work on the pending_list. ++// ++static int blkvsc_do_request(struct block_device_context *blkdev, struct request *req) ++{ ++ struct bio *bio=NULL; ++ struct bio_vec *bvec=NULL; ++ struct bio_vec *prev_bvec=NULL; ++ ++ struct blkvsc_request *blkvsc_req=NULL; ++ struct blkvsc_request *tmp; ++ int databuf_idx=0; ++ int seg_idx=0; ++ ++ sector_t start_sector; ++ unsigned long num_sectors = 0; ++ int ret=0; ++ int pending=0; ++ struct blkvsc_request_group *group=NULL; ++ ++ DPRINT_DBG(BLKVSC_DRV, "blkdev %p req %p sect %llu \n", blkdev, req, req->sector); ++ ++ // Create a group to tie req to list of blkvsc_reqs ++ group = (struct blkvsc_request_group*)kmem_cache_alloc(blkdev->request_pool, GFP_ATOMIC); ++ if (!group) ++ { ++ return -ENOMEM; ++ } ++ ++ INIT_LIST_HEAD(&group->blkvsc_req_list); ++ group->outstanding = group->status = 0; ++ ++ start_sector = req->sector; ++ ++ // foreach bio in the request ++ if (req->bio) ++ for (bio = req->bio; bio; bio = bio->bi_next) ++ { ++ // Map this bio into an existing or new storvsc request ++ bio_for_each_segment (bvec, bio, seg_idx) ++ { ++ DPRINT_DBG(BLKVSC_DRV, "bio_for_each_segment() - req %p bio %p bvec %p seg_idx %d databuf_idx %d\n", ++ req, bio, bvec, seg_idx, databuf_idx); ++ ++ // Get a new storvsc request ++ if ( (!blkvsc_req) || // 1st-time ++ (databuf_idx >= MAX_MULTIPAGE_BUFFER_COUNT) || ++ (bvec->bv_offset != 0) || // hole at the begin of page ++ (prev_bvec && (prev_bvec->bv_len != PAGE_SIZE)) ) // hold at the end of page ++ { ++ // submit the prev one ++ if (blkvsc_req) ++ { ++ blkvsc_req->sector_start = start_sector; ++ sector_div(blkvsc_req->sector_start, (blkdev->sector_size >> 9)); ++ ++ blkvsc_req->sector_count = num_sectors / (blkdev->sector_size >> 9); ++ ++ blkvsc_init_rw(blkvsc_req); ++ } ++ ++ // Create new blkvsc_req to represent the current bvec ++ blkvsc_req = kmem_cache_alloc(blkdev->request_pool, GFP_ATOMIC); ++ if (!blkvsc_req) ++ { ++ // free up everything ++ list_for_each_entry_safe(blkvsc_req, tmp, &group->blkvsc_req_list, req_entry) ++ { ++ list_del(&blkvsc_req->req_entry); ++ kmem_cache_free(blkdev->request_pool, blkvsc_req); ++ } ++ ++ kmem_cache_free(blkdev->request_pool, group); ++ return -ENOMEM; ++ } ++ ++ memset(blkvsc_req, 0, sizeof(struct blkvsc_request)); ++ ++ blkvsc_req->dev = blkdev; ++ blkvsc_req->req = req; ++ blkvsc_req->request.DataBuffer.Offset = bvec->bv_offset; ++ blkvsc_req->request.DataBuffer.Length = 0; ++ ++ // Add to the group ++ blkvsc_req->group = group; ++ blkvsc_req->group->outstanding++; ++ list_add_tail(&blkvsc_req->req_entry, &blkvsc_req->group->blkvsc_req_list); ++ ++ start_sector += num_sectors; ++ num_sectors = 0; ++ databuf_idx = 0; ++ } ++ ++ // Add the curr bvec/segment to the curr blkvsc_req ++ blkvsc_req->request.DataBuffer.PfnArray[databuf_idx] = page_to_pfn(bvec->bv_page); ++ blkvsc_req->request.DataBuffer.Length += bvec->bv_len; ++ ++ prev_bvec = bvec; ++ ++ databuf_idx++; ++ num_sectors += bvec->bv_len >> 9; ++ ++ } // bio_for_each_segment ++ ++ } // rq_for_each_bio ++ ++ // Handle the last one ++ if (blkvsc_req) ++ { ++ DPRINT_DBG(BLKVSC_DRV, "blkdev %p req %p group %p count %d\n", blkdev, req, blkvsc_req->group, blkvsc_req->group->outstanding); ++ ++ blkvsc_req->sector_start = start_sector; ++ sector_div(blkvsc_req->sector_start, (blkdev->sector_size >> 9)); ++ ++ blkvsc_req->sector_count = num_sectors / (blkdev->sector_size >> 9); ++ ++ blkvsc_init_rw(blkvsc_req); ++ } ++ ++ list_for_each_entry(blkvsc_req, &group->blkvsc_req_list, req_entry) ++ { ++ if (pending) ++ { ++ DPRINT_DBG(BLKVSC_DRV, "adding blkvsc_req to pending_list - blkvsc_req %p start_sect %llu sect_count %d (%llu %d)\n", ++ blkvsc_req, blkvsc_req->sector_start, blkvsc_req->sector_count, start_sector, num_sectors); ++ ++ list_add_tail(&blkvsc_req->pend_entry, &blkdev->pending_list); ++ } ++ else ++ { ++ ret = blkvsc_submit_request(blkvsc_req, blkvsc_request_completion); ++ if (ret == -1) ++ { ++ pending = 1; ++ list_add_tail(&blkvsc_req->pend_entry, &blkdev->pending_list); ++ } ++ ++ DPRINT_DBG(BLKVSC_DRV, "submitted blkvsc_req %p start_sect %llu sect_count %d (%llu %d) ret %d\n", ++ blkvsc_req, blkvsc_req->sector_start, blkvsc_req->sector_count, start_sector, num_sectors, ret); ++ } ++ } ++ ++ return pending; ++} ++ ++static void blkvsc_cmd_completion(STORVSC_REQUEST* request) ++{ ++ struct blkvsc_request *blkvsc_req=(struct blkvsc_request*)request->Context; ++ struct block_device_context *blkdev = (struct block_device_context*)blkvsc_req->dev; ++ ++ struct scsi_sense_hdr sense_hdr; ++ ++ DPRINT_DBG(BLKVSC_DRV, "blkvsc_cmd_completion() - req %p\n", blkvsc_req); ++ ++ blkdev->num_outstanding_reqs--; ++ ++ if (blkvsc_req->request.Status) ++ { ++ if (scsi_normalize_sense(blkvsc_req->sense_buffer, SCSI_SENSE_BUFFERSIZE, &sense_hdr)) ++ { ++ scsi_print_sense_hdr("blkvsc", &sense_hdr); ++ } ++ } ++ ++ blkvsc_req->cond =1; ++ wake_up_interruptible(&blkvsc_req->wevent); ++} ++ ++static void blkvsc_request_completion(STORVSC_REQUEST* request) ++{ ++ struct blkvsc_request *blkvsc_req=(struct blkvsc_request*)request->Context; ++ struct block_device_context *blkdev = (struct block_device_context*)blkvsc_req->dev; ++ unsigned long flags; ++ struct blkvsc_request *comp_req, *tmp; ++ ++ ASSERT(blkvsc_req->group); ++ ++ DPRINT_DBG(BLKVSC_DRV, "blkdev %p blkvsc_req %p group %p type %s sect_start %llu sect_count %d len %d group outstd %d total outstd %d\n", ++ blkdev, ++ blkvsc_req, ++ blkvsc_req->group, ++ (blkvsc_req->write)?"WRITE":"READ", ++ blkvsc_req->sector_start, ++ blkvsc_req->sector_count, ++ blkvsc_req->request.DataBuffer.Length, ++ blkvsc_req->group->outstanding, ++ blkdev->num_outstanding_reqs); ++ ++ spin_lock_irqsave(&blkdev->lock, flags); ++ ++ blkdev->num_outstanding_reqs--; ++ blkvsc_req->group->outstanding--; ++ ++ // Only start processing when all the blkvsc_reqs are completed. This guarantees no out-of-order ++ // blkvsc_req completion when calling end_that_request_first() ++ if (blkvsc_req->group->outstanding == 0) ++ { ++ list_for_each_entry_safe(comp_req, tmp, &blkvsc_req->group->blkvsc_req_list, req_entry) ++ { ++ DPRINT_DBG(BLKVSC_DRV, "completing blkvsc_req %p sect_start %llu sect_count %d \n", ++ comp_req, ++ comp_req->sector_start, ++ comp_req->sector_count); ++ ++ list_del(&comp_req->req_entry); ++ ++#ifdef KERNEL_2_6_27 ++ if (!__blk_end_request( ++ comp_req->req, ++ (!comp_req->request.Status ? 0: -EIO), ++ comp_req->sector_count * blkdev->sector_size)) ++ { ++ //All the sectors have been xferred ie the request is done ++ DPRINT_DBG(BLKVSC_DRV, "req %p COMPLETED\n", comp_req->req); ++ kmem_cache_free(blkdev->request_pool, comp_req->group); ++ } ++#else ++ if (!end_that_request_first(comp_req->req, !comp_req->request.Status, (comp_req->sector_count * (blkdev->sector_size >> 9)))) ++ { ++ //All the sectors have been xferred ie the request is done ++ DPRINT_DBG(BLKVSC_DRV, "req %p COMPLETED\n", comp_req->req); ++ ++ end_that_request_last(comp_req->req, !comp_req->request.Status); ++ ++ kmem_cache_free(blkdev->request_pool, comp_req->group); ++ } ++#endif ++ ++ kmem_cache_free(blkdev->request_pool, comp_req); ++ } ++ ++ if (!blkdev->shutting_down) ++ { ++ blkvsc_do_pending_reqs(blkdev); ++ blk_start_queue(blkdev->gd->queue); ++ blkvsc_request(blkdev->gd->queue); ++ } ++ } ++ ++ spin_unlock_irqrestore(&blkdev->lock, flags); ++} ++ ++static int blkvsc_cancel_pending_reqs(struct block_device_context *blkdev) ++{ ++ struct blkvsc_request *pend_req, *tmp; ++ struct blkvsc_request *comp_req, *tmp2; ++ ++ int ret=0; ++ ++ DPRINT_DBG(BLKVSC_DRV, "blkvsc_cancel_pending_reqs()"); ++ ++ // Flush the pending list first ++ list_for_each_entry_safe(pend_req, tmp, &blkdev->pending_list, pend_entry) ++ { ++ // The pend_req could be part of a partially completed request. If so, complete those req first ++ // until we hit the pend_req ++ list_for_each_entry_safe(comp_req, tmp2, &pend_req->group->blkvsc_req_list, req_entry) ++ { ++ DPRINT_DBG(BLKVSC_DRV, "completing blkvsc_req %p sect_start %llu sect_count %d \n", ++ comp_req, ++ comp_req->sector_start, ++ comp_req->sector_count); ++ ++ if (comp_req == pend_req) ++ break; ++ ++ list_del(&comp_req->req_entry); ++ ++ if (comp_req->req) ++ { ++#ifdef KERNEL_2_6_27 ++ ret = __blk_end_request( ++ comp_req->req, ++ (!comp_req->request.Status ? 0 : -EIO), ++ comp_req->sector_count * blkdev->sector_size); ++#else ++ ret = end_that_request_first(comp_req->req, !comp_req->request.Status, (comp_req->sector_count * (blkdev->sector_size >> 9))); ++#endif ++ ASSERT(ret != 0); ++ } ++ ++ kmem_cache_free(blkdev->request_pool, comp_req); ++ } ++ ++ DPRINT_DBG(BLKVSC_DRV, "cancelling pending request - %p\n", pend_req); ++ ++ list_del(&pend_req->pend_entry); ++ ++ list_del(&pend_req->req_entry); ++ ++ if (comp_req->req) ++ { ++#ifdef KERNEL_2_6_27 ++ if (!__blk_end_request( ++ pend_req->req, ++ -EIO, ++ pend_req->sector_count * blkdev->sector_size)) ++ { ++ //All the sectors have been xferred ie the request is done ++ DPRINT_DBG(BLKVSC_DRV, "blkvsc_cancel_pending_reqs() - req %p COMPLETED\n", pend_req->req); ++ kmem_cache_free(blkdev->request_pool, pend_req->group); ++ } ++#else ++ if (!end_that_request_first(pend_req->req, 0, (pend_req->sector_count * (blkdev->sector_size >> 9)))) ++ { ++ //All the sectors have been xferred ie the request is done ++ DPRINT_DBG(BLKVSC_DRV, "blkvsc_cancel_pending_reqs() - req %p COMPLETED\n", pend_req->req); ++ ++ end_that_request_last(pend_req->req, 0); ++ ++ kmem_cache_free(blkdev->request_pool, pend_req->group); ++ } ++#endif ++ } ++ ++ kmem_cache_free(blkdev->request_pool, pend_req); ++ } ++ ++ return ret; ++} ++ ++static int blkvsc_do_pending_reqs(struct block_device_context *blkdev) ++{ ++ struct blkvsc_request *pend_req, *tmp; ++ int ret=0; ++ ++ // Flush the pending list first ++ list_for_each_entry_safe(pend_req, tmp, &blkdev->pending_list, pend_entry) ++ { ++ DPRINT_DBG(BLKVSC_DRV, "working off pending_list - %p\n", pend_req); ++ ++ ret = blkvsc_submit_request(pend_req, blkvsc_request_completion); ++ if (ret != 0) ++ { ++ break; ++ } ++ else ++ { ++ list_del(&pend_req->pend_entry); ++ } ++ } ++ ++ return ret; ++} ++ ++static void blkvsc_request(struct request_queue *queue) ++{ ++ struct block_device_context *blkdev = NULL; ++ struct request *req; ++ int ret=0; ++ ++ DPRINT_DBG(BLKVSC_DRV, "- enter \n"); ++ while ((req = elv_next_request(queue)) != NULL) ++ { ++ DPRINT_DBG(BLKVSC_DRV, "- req %p\n", req); ++ ++ blkdev = req->rq_disk->private_data; ++ if (blkdev->shutting_down || !blk_fs_request(req) || blkdev->media_not_present) { ++ end_request(req, 0); ++ continue; ++ } ++ ++ ret = blkvsc_do_pending_reqs(blkdev); ++ ++ if (ret != 0) ++ { ++ DPRINT_DBG(BLKVSC_DRV, "- stop queue - pending_list not empty\n"); ++ blk_stop_queue(queue); ++ break; ++ } ++ ++ blkdev_dequeue_request(req); ++ ++ ret = blkvsc_do_request(blkdev, req); ++ if (ret > 0) ++ { ++ DPRINT_DBG(BLKVSC_DRV, "- stop queue - no room\n"); ++ blk_stop_queue(queue); ++ break; ++ } ++ else if (ret < 0) ++ { ++ DPRINT_DBG(BLKVSC_DRV, "- stop queue - no mem\n"); ++ blk_requeue_request(queue, req); ++ blk_stop_queue(queue); ++ break; ++ } ++ } ++} ++ ++static int blkvsc_open(struct inode *inode, struct file *filep) ++{ ++ struct block_device_context *blkdev = inode->i_bdev->bd_disk->private_data; ++ ++ DPRINT_DBG(BLKVSC_DRV, "- users %d disk %s\n", blkdev->users, blkdev->gd->disk_name); ++ ++ spin_lock(&blkdev->lock); ++ ++ if (!blkdev->users && blkdev->device_type == DVD_TYPE) ++ { ++ spin_unlock(&blkdev->lock); ++ check_disk_change(inode->i_bdev); ++ spin_lock(&blkdev->lock); ++ } ++ ++ blkdev->users++; ++ ++ spin_unlock(&blkdev->lock); ++ return 0; ++} ++ ++static int blkvsc_release(struct inode *inode, struct file *filep) ++{ ++ struct block_device_context *blkdev = inode->i_bdev->bd_disk->private_data; ++ ++ DPRINT_DBG(BLKVSC_DRV, "- users %d disk %s\n", blkdev->users, blkdev->gd->disk_name); ++ ++ spin_lock(&blkdev->lock); ++ if (blkdev->users == 1) ++ { ++ spin_unlock(&blkdev->lock); ++ blkvsc_do_flush(blkdev); ++ spin_lock(&blkdev->lock); ++ } ++ ++ blkdev->users--; ++ ++ spin_unlock(&blkdev->lock); ++ return 0; ++} ++ ++static int blkvsc_media_changed(struct gendisk *gd) ++{ ++ DPRINT_DBG(BLKVSC_DRV, "- enter\n"); ++ ++ return 1; ++} ++ ++static int blkvsc_revalidate_disk(struct gendisk *gd) ++{ ++ struct block_device_context *blkdev = gd->private_data; ++ ++ DPRINT_DBG(BLKVSC_DRV, "- enter\n"); ++ ++ if (blkdev->device_type == DVD_TYPE) ++ { ++ blkvsc_do_read_capacity(blkdev); ++ set_capacity(blkdev->gd, blkdev->capacity * (blkdev->sector_size/512)); ++ blk_queue_hardsect_size(gd->queue, blkdev->sector_size); ++ } ++ return 0; ++} ++ ++int blkvsc_getgeo(struct block_device *bd, struct hd_geometry *hg) ++{ ++ sector_t total_sectors = get_capacity(bd->bd_disk); ++ sector_t cylinder_times_heads=0; ++ sector_t temp=0; ++ ++ int sectors_per_track=0; ++ int heads=0; ++ int cylinders=0; ++ int rem=0; ++ ++ if (total_sectors > (65535 * 16 * 255)) { ++ total_sectors = (65535 * 16 * 255); ++ } ++ ++ if (total_sectors >= (65535 * 16 * 63)) { ++ sectors_per_track = 255; ++ heads = 16; ++ ++ cylinder_times_heads = total_sectors; ++ rem = sector_div(cylinder_times_heads, sectors_per_track); // sector_div stores the quotient in cylinder_times_heads ++ } ++ else ++ { ++ sectors_per_track = 17; ++ ++ cylinder_times_heads = total_sectors; ++ rem = sector_div(cylinder_times_heads, sectors_per_track); // sector_div stores the quotient in cylinder_times_heads ++ ++ temp = cylinder_times_heads + 1023; ++ rem = sector_div(temp, 1024); // sector_div stores the quotient in temp ++ ++ heads = temp; ++ ++ if (heads < 4) { ++ heads = 4; ++ } ++ ++ if (cylinder_times_heads >= (heads * 1024) || (heads > 16)) { ++ sectors_per_track = 31; ++ heads = 16; ++ ++ cylinder_times_heads = total_sectors; ++ rem = sector_div(cylinder_times_heads, sectors_per_track); // sector_div stores the quotient in cylinder_times_heads ++ } ++ ++ if (cylinder_times_heads >= (heads * 1024)) { ++ sectors_per_track = 63; ++ heads = 16; ++ ++ cylinder_times_heads = total_sectors; ++ rem = sector_div(cylinder_times_heads, sectors_per_track); // sector_div stores the quotient in cylinder_times_heads ++ } ++ } ++ ++ temp = cylinder_times_heads; ++ rem = sector_div(temp, heads); // sector_div stores the quotient in temp ++ cylinders = temp; ++ ++ hg->heads = heads; ++ hg->sectors = sectors_per_track; ++ hg->cylinders = cylinders; ++ ++ DPRINT_INFO(BLKVSC_DRV, "CHS (%d, %d, %d)", cylinders, heads, sectors_per_track); ++ ++ return 0; ++} ++ ++static int blkvsc_ioctl(struct inode *inode, struct file *filep, unsigned cmd, unsigned long arg) ++{ ++ struct block_device *bd = inode->i_bdev; ++ struct block_device_context *blkdev = bd->bd_disk->private_data; ++ int ret=0; ++ ++ switch (cmd) ++ { ++ // TODO: I think there is certain format for HDIO_GET_IDENTITY rather than just ++ // a GUID. Commented it out for now. ++ /*case HDIO_GET_IDENTITY: ++ DPRINT_INFO(BLKVSC_DRV, "HDIO_GET_IDENTITY\n"); ++ ++ if (copy_to_user((void __user *)arg, blkdev->device_id, blkdev->device_id_len)) ++ { ++ ret = -EFAULT; ++ } ++ ++ break;*/ ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++ ++MODULE_LICENSE("GPL"); ++ ++static int __init blkvsc_init(void) ++{ ++ int ret; ++ ++ ASSERT(sizeof(sector_t) == 8); // Make sure CONFIG_LBD is set ++ ++ DPRINT_ENTER(BLKVSC_DRV); ++ ++ DPRINT_INFO(BLKVSC_DRV, "Blkvsc initializing...."); ++ ++ ret = blkvsc_drv_init(BlkVscInitialize); ++ ++ DPRINT_EXIT(BLKVSC_DRV); ++ ++ return ret; ++} ++ ++static void __exit blkvsc_exit(void) ++{ ++ DPRINT_ENTER(BLKVSC_DRV); ++ ++ blkvsc_drv_exit(); ++ ++ DPRINT_ENTER(BLKVSC_DRV); ++} ++ ++module_param(blkvsc_ringbuffer_size, int, S_IRUGO); ++ ++module_init(blkvsc_init); ++module_exit(blkvsc_exit); ++ ++// eof +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/Channel.c linux-2.6.27.29-0.1.1/drivers/staging/hv/Channel.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/Channel.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,1199 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#include "include/osd.h" ++#include "include/logging.h" ++ ++#include "VmbusPrivate.h" ++ ++// ++// Internal routines ++// ++static int ++VmbusChannelCreateGpadlHeader( ++ PVOID Kbuffer, // must be phys and virt contiguous ++ UINT32 Size, // page-size multiple ++ VMBUS_CHANNEL_MSGINFO **msgInfo, ++ UINT32 *MessageCount ++ ); ++ ++static void ++DumpVmbusChannel( ++ VMBUS_CHANNEL *Channel ++ ); ++ ++ ++static void ++VmbusChannelSetEvent( ++ VMBUS_CHANNEL *Channel ++ ); ++ ++ ++#if 0 ++static void ++DumpMonitorPage( ++ HV_MONITOR_PAGE *MonitorPage ++ ) ++{ ++ int i=0; ++ int j=0; ++ ++ DPRINT_DBG(VMBUS, "monitorPage - %p, trigger state - %d", MonitorPage, MonitorPage->TriggerState); ++ ++ for (i=0; i<4; i++) ++ { ++ DPRINT_DBG(VMBUS, "trigger group (%d) - %llx", i, MonitorPage->TriggerGroup[i].AsUINT64); ++ } ++ ++ for (i=0; i<4; i++) ++ { ++ for (j=0; j<32; j++) ++ { ++ DPRINT_DBG(VMBUS, "latency (%d)(%d) - %llx", i, j, MonitorPage->Latency[i][j]); ++ } ++ } ++ for (i=0; i<4; i++) ++ { ++ for (j=0; j<32; j++) ++ { ++ DPRINT_DBG(VMBUS, "param-conn id (%d)(%d) - %d", i, j, MonitorPage->Parameter[i][j].ConnectionId.AsUINT32); ++ DPRINT_DBG(VMBUS, "param-flag (%d)(%d) - %d", i, j, MonitorPage->Parameter[i][j].FlagNumber); ++ ++ } ++ } ++} ++#endif ++ ++/*++ ++ ++Name: ++ VmbusChannelSetEvent() ++ ++Description: ++ Trigger an event notification on the specified channel. ++ ++--*/ ++static void ++VmbusChannelSetEvent( ++ VMBUS_CHANNEL *Channel ++ ) ++{ ++ HV_MONITOR_PAGE *monitorPage; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ if (Channel->OfferMsg.MonitorAllocated) ++ { ++ // Each UINT32 represents 32 channels ++ BitSet((UINT32*)gVmbusConnection.SendInterruptPage + (Channel->OfferMsg.ChildRelId >> 5), Channel->OfferMsg.ChildRelId & 31); ++ ++ monitorPage = (HV_MONITOR_PAGE*)gVmbusConnection.MonitorPages; ++ monitorPage++; // Get the child to parent monitor page ++ ++ BitSet((UINT32*) &monitorPage->TriggerGroup[Channel->MonitorGroup].Pending, Channel->MonitorBit); ++ } ++ else ++ { ++ VmbusSetEvent(Channel->OfferMsg.ChildRelId); ++ } ++ ++ DPRINT_EXIT(VMBUS); ++} ++ ++#if 0 ++static void ++VmbusChannelClearEvent( ++ VMBUS_CHANNEL *Channel ++ ) ++{ ++ HV_MONITOR_PAGE *monitorPage; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ if (Channel->OfferMsg.MonitorAllocated) ++ { ++ // Each UINT32 represents 32 channels ++ BitClear((UINT32*)gVmbusConnection.SendInterruptPage + (Channel->OfferMsg.ChildRelId >> 5), Channel->OfferMsg.ChildRelId & 31); ++ ++ monitorPage = (HV_MONITOR_PAGE*)gVmbusConnection.MonitorPages; ++ monitorPage++; // Get the child to parent monitor page ++ ++ BitClear((UINT32*) &monitorPage->TriggerGroup[Channel->MonitorGroup].Pending, Channel->MonitorBit); ++ } ++ ++ DPRINT_EXIT(VMBUS); ++} ++ ++#endif ++/*++; ++ ++Name: ++ VmbusChannelGetDebugInfo() ++ ++Description: ++ Retrieve various channel debug info ++ ++--*/ ++void ++VmbusChannelGetDebugInfo( ++ VMBUS_CHANNEL *Channel, ++ VMBUS_CHANNEL_DEBUG_INFO *DebugInfo ++ ) ++{ ++ HV_MONITOR_PAGE *monitorPage; ++ UINT8 monitorGroup = (UINT8)Channel->OfferMsg.MonitorId / 32; ++ UINT8 monitorOffset = (UINT8)Channel->OfferMsg.MonitorId % 32; ++ //UINT32 monitorBit = 1 << monitorOffset; ++ ++ DebugInfo->RelId = Channel->OfferMsg.ChildRelId; ++ DebugInfo->State = Channel->State; ++ memcpy(&DebugInfo->InterfaceType, &Channel->OfferMsg.Offer.InterfaceType, sizeof(GUID)); ++ memcpy(&DebugInfo->InterfaceInstance, &Channel->OfferMsg.Offer.InterfaceInstance, sizeof(GUID)); ++ ++ monitorPage = (HV_MONITOR_PAGE*)gVmbusConnection.MonitorPages; ++ ++ DebugInfo->MonitorId = Channel->OfferMsg.MonitorId; ++ ++ DebugInfo->ServerMonitorPending = monitorPage->TriggerGroup[monitorGroup].Pending; ++ DebugInfo->ServerMonitorLatency = monitorPage->Latency[monitorGroup][ monitorOffset]; ++ DebugInfo->ServerMonitorConnectionId = monitorPage->Parameter[monitorGroup][ monitorOffset].ConnectionId.u.Id; ++ ++ monitorPage++; ++ ++ DebugInfo->ClientMonitorPending = monitorPage->TriggerGroup[monitorGroup].Pending; ++ DebugInfo->ClientMonitorLatency = monitorPage->Latency[monitorGroup][ monitorOffset]; ++ DebugInfo->ClientMonitorConnectionId = monitorPage->Parameter[monitorGroup][ monitorOffset].ConnectionId.u.Id; ++ ++ RingBufferGetDebugInfo(&Channel->Inbound, &DebugInfo->Inbound); ++ RingBufferGetDebugInfo(&Channel->Outbound, &DebugInfo->Outbound); ++} ++ ++ ++/*++; ++ ++Name: ++ VmbusChannelOpen() ++ ++Description: ++ Open the specified channel. ++ ++--*/ ++int ++VmbusChannelOpen( ++ VMBUS_CHANNEL *NewChannel, ++ UINT32 SendRingBufferSize, ++ UINT32 RecvRingBufferSize, ++ PVOID UserData, ++ UINT32 UserDataLen, ++ PFN_CHANNEL_CALLBACK pfnOnChannelCallback, ++ PVOID Context ++ ) ++{ ++ int ret=0; ++ VMBUS_CHANNEL_OPEN_CHANNEL* openMsg; ++ VMBUS_CHANNEL_MSGINFO* openInfo; ++ void *in, *out; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ // Aligned to page size ++ ASSERT(!(SendRingBufferSize & (PAGE_SIZE -1))); ++ ASSERT(!(RecvRingBufferSize & (PAGE_SIZE -1))); ++ ++ NewChannel->OnChannelCallback = pfnOnChannelCallback; ++ NewChannel->ChannelCallbackContext = Context; ++ ++ // Allocate the ring buffer ++ out = PageAlloc((SendRingBufferSize + RecvRingBufferSize) >> PAGE_SHIFT); ++ //out = MemAllocZeroed(sendRingBufferSize + recvRingBufferSize); ++ ASSERT(out); ++ ASSERT(((ULONG_PTR)out & (PAGE_SIZE-1)) == 0); ++ ++ in = (void*)((ULONG_PTR)out + SendRingBufferSize); ++ ++ NewChannel->RingBufferPages = out; ++ NewChannel->RingBufferPageCount = (SendRingBufferSize + RecvRingBufferSize) >> PAGE_SHIFT; ++ ++ RingBufferInit(&NewChannel->Outbound, out, SendRingBufferSize); ++ ++ RingBufferInit(&NewChannel->Inbound, in, RecvRingBufferSize); ++ ++ // Establish the gpadl for the ring buffer ++ DPRINT_DBG(VMBUS, "Establishing ring buffer's gpadl for channel %p...", NewChannel); ++ ++ NewChannel->RingBufferGpadlHandle = 0; ++ ++ ret = VmbusChannelEstablishGpadl(NewChannel, ++ NewChannel->Outbound.RingBuffer, ++ SendRingBufferSize + RecvRingBufferSize, ++ &NewChannel->RingBufferGpadlHandle); ++ ++ DPRINT_DBG(VMBUS, "channel %p ", ++ NewChannel, ++ NewChannel->OfferMsg.ChildRelId, ++ NewChannel->RingBufferGpadlHandle, ++ NewChannel->Outbound.RingBuffer, ++ NewChannel->Outbound.RingSize, ++ NewChannel->Inbound.RingBuffer, ++ NewChannel->Inbound.RingSize, ++ SendRingBufferSize); ++ ++ // Create and init the channel open message ++ openInfo = ++ (VMBUS_CHANNEL_MSGINFO*)MemAlloc(sizeof(VMBUS_CHANNEL_MSGINFO) + sizeof(VMBUS_CHANNEL_OPEN_CHANNEL)); ++ ASSERT(openInfo != NULL); ++ ++ openInfo->WaitEvent = WaitEventCreate(); ++ ++ openMsg = (VMBUS_CHANNEL_OPEN_CHANNEL*)openInfo->Msg; ++ openMsg->Header.MessageType = ChannelMessageOpenChannel; ++ openMsg->OpenId = NewChannel->OfferMsg.ChildRelId; // FIXME ++ openMsg->ChildRelId = NewChannel->OfferMsg.ChildRelId; ++ openMsg->RingBufferGpadlHandle = NewChannel->RingBufferGpadlHandle; ++ ASSERT(openMsg->RingBufferGpadlHandle); ++ openMsg->DownstreamRingBufferPageOffset = SendRingBufferSize >> PAGE_SHIFT; ++ openMsg->ServerContextAreaGpadlHandle = 0; // TODO ++ ++ ASSERT(UserDataLen <= MAX_USER_DEFINED_BYTES); ++ if (UserDataLen) ++ { ++ memcpy(openMsg->UserData, UserData, UserDataLen); ++ } ++ ++ SpinlockAcquire(gVmbusConnection.ChannelMsgLock); ++ INSERT_TAIL_LIST(&gVmbusConnection.ChannelMsgList, &openInfo->MsgListEntry); ++ SpinlockRelease(gVmbusConnection.ChannelMsgLock); ++ ++ DPRINT_DBG(VMBUS, "Sending channel open msg..."); ++ ++ ret = VmbusPostMessage(openMsg, sizeof(VMBUS_CHANNEL_OPEN_CHANNEL)); ++ if (ret != 0) ++ { ++ DPRINT_ERR(VMBUS, "unable to open channel - %d", ret); ++ goto Cleanup; ++ } ++ ++ // FIXME: Need to time-out here ++ WaitEventWait(openInfo->WaitEvent); ++ ++ if (openInfo->Response.OpenResult.Status == 0) ++ { ++ DPRINT_INFO(VMBUS, "channel <%p> open success!!", NewChannel); ++ } ++ else ++ { ++ DPRINT_INFO(VMBUS, "channel <%p> open failed - %d!!", NewChannel, openInfo->Response.OpenResult.Status); ++ } ++ ++Cleanup: ++ SpinlockAcquire(gVmbusConnection.ChannelMsgLock); ++ REMOVE_ENTRY_LIST(&openInfo->MsgListEntry); ++ SpinlockRelease(gVmbusConnection.ChannelMsgLock); ++ ++ WaitEventClose(openInfo->WaitEvent); ++ MemFree(openInfo); ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return 0; ++} ++ ++/*++; ++ ++Name: ++ DumpGpadlBody() ++ ++Description: ++ Dump the gpadl body message to the console for debugging purposes. ++ ++--*/ ++static void DumpGpadlBody( ++ VMBUS_CHANNEL_GPADL_BODY *Gpadl, ++ UINT32 Len) ++{ ++ int i=0; ++ int pfnCount=0; ++ ++ pfnCount = (Len - sizeof(VMBUS_CHANNEL_GPADL_BODY))/ sizeof(UINT64); ++ DPRINT_DBG(VMBUS, "gpadl body - len %d pfn count %d", Len, pfnCount); ++ ++ for (i=0; i< pfnCount; i++) ++ { ++ DPRINT_DBG(VMBUS, "gpadl body - %d) pfn %llu", i, Gpadl->Pfn[i]); ++ } ++} ++ ++ ++/*++; ++ ++Name: ++ DumpGpadlHeader() ++ ++Description: ++ Dump the gpadl header message to the console for debugging purposes. ++ ++--*/ ++static void DumpGpadlHeader( ++ VMBUS_CHANNEL_GPADL_HEADER *Gpadl ++ ) ++{ ++ int i=0,j=0; ++ int pageCount=0; ++ ++ ++ DPRINT_DBG(VMBUS, "gpadl header - relid %d, range count %d, range buflen %d", ++ Gpadl->ChildRelId, ++ Gpadl->RangeCount, ++ Gpadl->RangeBufLen); ++ for (i=0; i< Gpadl->RangeCount; i++) ++ { ++ pageCount = Gpadl->Range[i].ByteCount >> PAGE_SHIFT; ++ pageCount = (pageCount > 26)? 26 : pageCount; ++ ++ DPRINT_DBG(VMBUS, "gpadl range %d - len %d offset %d page count %d", ++ i, Gpadl->Range[i].ByteCount, Gpadl->Range[i].ByteOffset, pageCount); ++ ++ for (j=0; j< pageCount; j++) ++ { ++ DPRINT_DBG(VMBUS, "%d) pfn %llu", j, Gpadl->Range[i].PfnArray[j]); ++ } ++ } ++} ++ ++/*++; ++ ++Name: ++ VmbusChannelCreateGpadlHeader() ++ ++Description: ++ Creates a gpadl for the specified buffer ++ ++--*/ ++static int ++VmbusChannelCreateGpadlHeader( ++ PVOID Kbuffer, // from kmalloc() ++ UINT32 Size, // page-size multiple ++ VMBUS_CHANNEL_MSGINFO **MsgInfo, ++ UINT32 *MessageCount) ++{ ++ int i; ++ int pageCount; ++ unsigned long long pfn; ++ VMBUS_CHANNEL_GPADL_HEADER* gpaHeader; ++ VMBUS_CHANNEL_GPADL_BODY* gpadlBody; ++ VMBUS_CHANNEL_MSGINFO* msgHeader; ++ VMBUS_CHANNEL_MSGINFO* msgBody; ++ UINT32 msgSize; ++ ++ int pfnSum, pfnCount, pfnLeft, pfnCurr, pfnSize; ++ ++ //ASSERT( (kbuffer & (PAGE_SIZE-1)) == 0); ++ ASSERT( (Size & (PAGE_SIZE-1)) == 0); ++ ++ pageCount = Size >> PAGE_SHIFT; ++ pfn = GetPhysicalAddress(Kbuffer) >> PAGE_SHIFT; ++ ++ // do we need a gpadl body msg ++ pfnSize = MAX_SIZE_CHANNEL_MESSAGE - sizeof(VMBUS_CHANNEL_GPADL_HEADER) - sizeof(GPA_RANGE); ++ pfnCount = pfnSize / sizeof(UINT64); ++ ++ if (pageCount > pfnCount) // we need a gpadl body ++ { ++ // fill in the header ++ msgSize = sizeof(VMBUS_CHANNEL_MSGINFO) + sizeof(VMBUS_CHANNEL_GPADL_HEADER) + sizeof(GPA_RANGE) + pfnCount*sizeof(UINT64); ++ msgHeader = MemAllocZeroed(msgSize); ++ ++ INITIALIZE_LIST_HEAD(&msgHeader->SubMsgList); ++ msgHeader->MessageSize=msgSize; ++ ++ gpaHeader = (VMBUS_CHANNEL_GPADL_HEADER*)msgHeader->Msg; ++ gpaHeader->RangeCount = 1; ++ gpaHeader->RangeBufLen = sizeof(GPA_RANGE) + pageCount*sizeof(UINT64); ++ gpaHeader->Range[0].ByteOffset = 0; ++ gpaHeader->Range[0].ByteCount = Size; ++ for (i=0; iRange[0].PfnArray[i] = pfn+i; ++ } ++ *MsgInfo = msgHeader; ++ *MessageCount = 1; ++ ++ pfnSum = pfnCount; ++ pfnLeft = pageCount - pfnCount; ++ ++ // how many pfns can we fit ++ pfnSize = MAX_SIZE_CHANNEL_MESSAGE - sizeof(VMBUS_CHANNEL_GPADL_BODY); ++ pfnCount = pfnSize / sizeof(UINT64); ++ ++ // fill in the body ++ while (pfnLeft) ++ { ++ if (pfnLeft > pfnCount) ++ { ++ pfnCurr = pfnCount; ++ } ++ else ++ { ++ pfnCurr = pfnLeft; ++ } ++ ++ msgSize = sizeof(VMBUS_CHANNEL_MSGINFO) + sizeof(VMBUS_CHANNEL_GPADL_BODY) + pfnCurr*sizeof(UINT64); ++ msgBody = MemAllocZeroed(msgSize); ++ ASSERT(msgBody); ++ msgBody->MessageSize = msgSize; ++ (*MessageCount)++; ++ gpadlBody = (VMBUS_CHANNEL_GPADL_BODY*)msgBody->Msg; ++ ++ // FIXME: Gpadl is UINT32 and we are using a pointer which could be 64-bit ++ //gpadlBody->Gpadl = kbuffer; ++ for (i=0; iPfn[i] = pfn + pfnSum + i; ++ } ++ ++ // add to msg header ++ INSERT_TAIL_LIST(&msgHeader->SubMsgList, &msgBody->MsgListEntry); ++ pfnSum += pfnCurr; ++ pfnLeft -= pfnCurr; ++ } ++ } ++ else ++ { ++ // everything fits in a header ++ msgSize = sizeof(VMBUS_CHANNEL_MSGINFO) + sizeof(VMBUS_CHANNEL_GPADL_HEADER) + sizeof(GPA_RANGE) + pageCount*sizeof(UINT64); ++ msgHeader = MemAllocZeroed(msgSize); ++ msgHeader->MessageSize=msgSize; ++ ++ gpaHeader = (VMBUS_CHANNEL_GPADL_HEADER*)msgHeader->Msg; ++ gpaHeader->RangeCount = 1; ++ gpaHeader->RangeBufLen = sizeof(GPA_RANGE) + pageCount*sizeof(UINT64); ++ gpaHeader->Range[0].ByteOffset = 0; ++ gpaHeader->Range[0].ByteCount = Size; ++ for (i=0; iRange[0].PfnArray[i] = pfn+i; ++ } ++ ++ *MsgInfo = msgHeader; ++ *MessageCount = 1; ++ } ++ ++ return 0; ++} ++ ++ ++/*++; ++ ++Name: ++ VmbusChannelEstablishGpadl() ++ ++Description: ++ Estabish a GPADL for the specified buffer ++ ++--*/ ++int ++VmbusChannelEstablishGpadl( ++ VMBUS_CHANNEL *Channel, ++ PVOID Kbuffer, // from kmalloc() ++ UINT32 Size, // page-size multiple ++ UINT32 *GpadlHandle ++ ) ++{ ++ int ret=0; ++ VMBUS_CHANNEL_GPADL_HEADER* gpadlMsg; ++ VMBUS_CHANNEL_GPADL_BODY* gpadlBody; ++ //VMBUS_CHANNEL_GPADL_CREATED* gpadlCreated; ++ ++ VMBUS_CHANNEL_MSGINFO *msgInfo; ++ VMBUS_CHANNEL_MSGINFO *subMsgInfo; ++ ++ UINT32 msgCount; ++ LIST_ENTRY* anchor; ++ LIST_ENTRY* curr; ++ UINT32 nextGpadlHandle; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ nextGpadlHandle = gVmbusConnection.NextGpadlHandle; ++ InterlockedIncrement((int*)&gVmbusConnection.NextGpadlHandle); ++ ++ VmbusChannelCreateGpadlHeader(Kbuffer, Size, &msgInfo, &msgCount); ++ ASSERT(msgInfo != NULL); ++ ASSERT(msgCount >0); ++ ++ msgInfo->WaitEvent = WaitEventCreate(); ++ gpadlMsg = (VMBUS_CHANNEL_GPADL_HEADER*)msgInfo->Msg; ++ gpadlMsg->Header.MessageType = ChannelMessageGpadlHeader; ++ gpadlMsg->ChildRelId = Channel->OfferMsg.ChildRelId; ++ gpadlMsg->Gpadl = nextGpadlHandle; ++ ++ DumpGpadlHeader(gpadlMsg); ++ ++ SpinlockAcquire(gVmbusConnection.ChannelMsgLock); ++ INSERT_TAIL_LIST(&gVmbusConnection.ChannelMsgList, &msgInfo->MsgListEntry); ++ SpinlockRelease(gVmbusConnection.ChannelMsgLock); ++ ++ DPRINT_DBG(VMBUS, "buffer %p, size %d msg cnt %d", Kbuffer, Size, msgCount); ++ ++ DPRINT_DBG(VMBUS, "Sending GPADL Header - len %d", msgInfo->MessageSize - sizeof(VMBUS_CHANNEL_MSGINFO)); ++ ++ ret = VmbusPostMessage(gpadlMsg, msgInfo->MessageSize - sizeof(VMBUS_CHANNEL_MSGINFO)); ++ if (ret != 0) ++ { ++ DPRINT_ERR(VMBUS, "Unable to open channel - %d", ret); ++ goto Cleanup; ++ } ++ ++ if (msgCount>1) ++ { ++ ITERATE_LIST_ENTRIES(anchor, curr, &msgInfo->SubMsgList) ++ { ++ subMsgInfo = (VMBUS_CHANNEL_MSGINFO*) curr; ++ gpadlBody = (VMBUS_CHANNEL_GPADL_BODY*)subMsgInfo->Msg; ++ ++ gpadlBody->Header.MessageType = ChannelMessageGpadlBody; ++ gpadlBody->Gpadl = nextGpadlHandle; ++ ++ DPRINT_DBG(VMBUS, "Sending GPADL Body - len %d", subMsgInfo->MessageSize - sizeof(VMBUS_CHANNEL_MSGINFO)); ++ ++ DumpGpadlBody(gpadlBody, subMsgInfo->MessageSize - sizeof(VMBUS_CHANNEL_MSGINFO)); ++ ret = VmbusPostMessage(gpadlBody, subMsgInfo->MessageSize - sizeof(VMBUS_CHANNEL_MSGINFO)); ++ ASSERT(ret == 0); ++ } ++ } ++ WaitEventWait(msgInfo->WaitEvent); ++ ++ // At this point, we received the gpadl created msg ++ DPRINT_DBG(VMBUS, "Received GPADL created (relid %d, status %d handle %x)", ++ Channel->OfferMsg.ChildRelId, ++ msgInfo->Response.GpadlCreated.CreationStatus, ++ gpadlMsg->Gpadl); ++ ++ *GpadlHandle = gpadlMsg->Gpadl; ++ ++Cleanup: ++ SpinlockAcquire(gVmbusConnection.ChannelMsgLock); ++ REMOVE_ENTRY_LIST(&msgInfo->MsgListEntry); ++ SpinlockRelease(gVmbusConnection.ChannelMsgLock); ++ ++ WaitEventClose(msgInfo->WaitEvent); ++ MemFree(msgInfo); ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++} ++ ++ ++ ++/*++; ++ ++Name: ++ VmbusChannelTeardownGpadl() ++ ++Description: ++ Teardown the specified GPADL handle ++ ++--*/ ++int ++VmbusChannelTeardownGpadl( ++ VMBUS_CHANNEL *Channel, ++ UINT32 GpadlHandle ++ ) ++{ ++ int ret=0; ++ VMBUS_CHANNEL_GPADL_TEARDOWN *msg; ++ VMBUS_CHANNEL_MSGINFO* info; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ ASSERT(GpadlHandle != 0); ++ ++ info = ++ (VMBUS_CHANNEL_MSGINFO*)MemAlloc(sizeof(VMBUS_CHANNEL_MSGINFO) + sizeof(VMBUS_CHANNEL_GPADL_TEARDOWN)); ++ ASSERT(info != NULL); ++ ++ info->WaitEvent = WaitEventCreate(); ++ ++ msg = (VMBUS_CHANNEL_GPADL_TEARDOWN*)info->Msg; ++ ++ msg->Header.MessageType = ChannelMessageGpadlTeardown; ++ msg->ChildRelId = Channel->OfferMsg.ChildRelId; ++ msg->Gpadl = GpadlHandle; ++ ++ SpinlockAcquire(gVmbusConnection.ChannelMsgLock); ++ INSERT_TAIL_LIST(&gVmbusConnection.ChannelMsgList, &info->MsgListEntry); ++ SpinlockRelease(gVmbusConnection.ChannelMsgLock); ++ ++ ret = VmbusPostMessage(msg, sizeof(VMBUS_CHANNEL_GPADL_TEARDOWN)); ++ if (ret != 0) ++ { ++ // TODO: ++ } ++ ++ WaitEventWait(info->WaitEvent); ++ ++ // Received a torndown response ++ SpinlockAcquire(gVmbusConnection.ChannelMsgLock); ++ REMOVE_ENTRY_LIST(&info->MsgListEntry); ++ SpinlockRelease(gVmbusConnection.ChannelMsgLock); ++ ++ WaitEventClose(info->WaitEvent); ++ MemFree(info); ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelClose() ++ ++Description: ++ Close the specified channel ++ ++--*/ ++VOID ++VmbusChannelClose( ++ VMBUS_CHANNEL *Channel ++ ) ++{ ++ int ret=0; ++ VMBUS_CHANNEL_CLOSE_CHANNEL* msg; ++ VMBUS_CHANNEL_MSGINFO* info; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ // Stop callback and cancel the timer asap ++ Channel->OnChannelCallback = NULL; ++ TimerStop(Channel->PollTimer); ++ ++ // Send a closing message ++ info = ++ (VMBUS_CHANNEL_MSGINFO*)MemAlloc(sizeof(VMBUS_CHANNEL_MSGINFO) + sizeof(VMBUS_CHANNEL_CLOSE_CHANNEL)); ++ ASSERT(info != NULL); ++ ++ //info->waitEvent = WaitEventCreate(); ++ ++ msg = (VMBUS_CHANNEL_CLOSE_CHANNEL*)info->Msg; ++ msg->Header.MessageType = ChannelMessageCloseChannel; ++ msg->ChildRelId = Channel->OfferMsg.ChildRelId; ++ ++ ret = VmbusPostMessage(msg, sizeof(VMBUS_CHANNEL_CLOSE_CHANNEL)); ++ if (ret != 0) ++ { ++ // TODO: ++ } ++ ++ // Tear down the gpadl for the channel's ring buffer ++ if (Channel->RingBufferGpadlHandle) ++ { ++ VmbusChannelTeardownGpadl(Channel, Channel->RingBufferGpadlHandle); ++ } ++ ++ // TODO: Send a msg to release the childRelId ++ ++ // Cleanup the ring buffers for this channel ++ RingBufferCleanup(&Channel->Outbound); ++ RingBufferCleanup(&Channel->Inbound); ++ ++ PageFree(Channel->RingBufferPages, Channel->RingBufferPageCount); ++ ++ MemFree(info); ++ ++ // If we are closing the channel during an error path in opening the channel, don't free the channel ++ // since the caller will free the channel ++ if (Channel->State == CHANNEL_OPEN_STATE) ++ { ++ SpinlockAcquire(gVmbusConnection.ChannelLock); ++ REMOVE_ENTRY_LIST(&Channel->ListEntry); ++ SpinlockRelease(gVmbusConnection.ChannelLock); ++ ++ FreeVmbusChannel(Channel); ++ } ++ ++ DPRINT_EXIT(VMBUS); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelSendPacket() ++ ++Description: ++ Send the specified buffer on the given channel ++ ++--*/ ++int ++VmbusChannelSendPacket( ++ VMBUS_CHANNEL *Channel, ++ const PVOID Buffer, ++ UINT32 BufferLen, ++ UINT64 RequestId, ++ VMBUS_PACKET_TYPE Type, ++ UINT32 Flags ++) ++{ ++ int ret=0; ++ VMPACKET_DESCRIPTOR desc; ++ UINT32 packetLen = sizeof(VMPACKET_DESCRIPTOR) + BufferLen; ++ UINT32 packetLenAligned = ALIGN_UP(packetLen, sizeof(UINT64)); ++ SG_BUFFER_LIST bufferList[3]; ++ UINT64 alignedData=0; ++ ++ DPRINT_ENTER(VMBUS); ++ DPRINT_DBG(VMBUS, "channel %p buffer %p len %d", Channel, Buffer, BufferLen); ++ ++ DumpVmbusChannel(Channel); ++ ++ ASSERT((packetLenAligned - packetLen) < sizeof(UINT64)); ++ ++ // Setup the descriptor ++ desc.Type = Type;//VmbusPacketTypeDataInBand; ++ desc.Flags = Flags;//VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED; ++ desc.DataOffset8 = sizeof(VMPACKET_DESCRIPTOR) >> 3; // in 8-bytes granularity ++ desc.Length8 = (UINT16)(packetLenAligned >> 3); ++ desc.TransactionId = RequestId; ++ ++ bufferList[0].Data = &desc; ++ bufferList[0].Length = sizeof(VMPACKET_DESCRIPTOR); ++ ++ bufferList[1].Data = Buffer; ++ bufferList[1].Length = BufferLen; ++ ++ bufferList[2].Data = &alignedData; ++ bufferList[2].Length = packetLenAligned - packetLen; ++ ++ ret = RingBufferWrite( ++ &Channel->Outbound, ++ bufferList, ++ 3); ++ ++ // TODO: We should determine if this is optional ++ if (ret == 0 && !GetRingBufferInterruptMask(&Channel->Outbound)) ++ { ++ VmbusChannelSetEvent(Channel); ++ } ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelSendPacketPageBuffer() ++ ++Description: ++ Send a range of single-page buffer packets using a GPADL Direct packet type. ++ ++--*/ ++int ++VmbusChannelSendPacketPageBuffer( ++ VMBUS_CHANNEL *Channel, ++ PAGE_BUFFER PageBuffers[], ++ UINT32 PageCount, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT64 RequestId ++) ++{ ++ int ret=0; ++ int i=0; ++ VMBUS_CHANNEL_PACKET_PAGE_BUFFER desc; ++ UINT32 descSize; ++ UINT32 packetLen; ++ UINT32 packetLenAligned; ++ SG_BUFFER_LIST bufferList[3]; ++ UINT64 alignedData=0; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ ASSERT(PageCount <= MAX_PAGE_BUFFER_COUNT); ++ ++ DumpVmbusChannel(Channel); ++ ++ // Adjust the size down since VMBUS_CHANNEL_PACKET_PAGE_BUFFER is the largest size we support ++ descSize = sizeof(VMBUS_CHANNEL_PACKET_PAGE_BUFFER) - ((MAX_PAGE_BUFFER_COUNT - PageCount)*sizeof(PAGE_BUFFER)); ++ packetLen = descSize + BufferLen; ++ packetLenAligned = ALIGN_UP(packetLen, sizeof(UINT64)); ++ ++ ASSERT((packetLenAligned - packetLen) < sizeof(UINT64)); ++ ++ // Setup the descriptor ++ desc.Type = VmbusPacketTypeDataUsingGpaDirect; ++ desc.Flags = VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED; ++ desc.DataOffset8 = descSize >> 3; // in 8-bytes grandularity ++ desc.Length8 = (UINT16)(packetLenAligned >> 3); ++ desc.TransactionId = RequestId; ++ desc.RangeCount = PageCount; ++ ++ for (i=0; iOutbound, ++ bufferList, ++ 3); ++ ++ // TODO: We should determine if this is optional ++ if (ret == 0 && !GetRingBufferInterruptMask(&Channel->Outbound)) ++ { ++ VmbusChannelSetEvent(Channel); ++ } ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++} ++ ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelSendPacketMultiPageBuffer() ++ ++Description: ++ Send a multi-page buffer packet using a GPADL Direct packet type. ++ ++--*/ ++int ++VmbusChannelSendPacketMultiPageBuffer( ++ VMBUS_CHANNEL *Channel, ++ MULTIPAGE_BUFFER *MultiPageBuffer, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT64 RequestId ++) ++{ ++ int ret=0; ++ VMBUS_CHANNEL_PACKET_MULITPAGE_BUFFER desc; ++ UINT32 descSize; ++ UINT32 packetLen; ++ UINT32 packetLenAligned; ++ SG_BUFFER_LIST bufferList[3]; ++ UINT64 alignedData=0; ++ UINT32 PfnCount = NUM_PAGES_SPANNED(MultiPageBuffer->Offset, MultiPageBuffer->Length); ++ ++ DPRINT_ENTER(VMBUS); ++ ++ DumpVmbusChannel(Channel); ++ ++ DPRINT_DBG(VMBUS, "data buffer - offset %u len %u pfn count %u", MultiPageBuffer->Offset, MultiPageBuffer->Length, PfnCount); ++ ++ ASSERT(PfnCount > 0); ++ ASSERT(PfnCount <= MAX_MULTIPAGE_BUFFER_COUNT); ++ ++ // Adjust the size down since VMBUS_CHANNEL_PACKET_MULITPAGE_BUFFER is the largest size we support ++ descSize = sizeof(VMBUS_CHANNEL_PACKET_MULITPAGE_BUFFER) - ((MAX_MULTIPAGE_BUFFER_COUNT - PfnCount)*sizeof(UINT64)); ++ packetLen = descSize + BufferLen; ++ packetLenAligned = ALIGN_UP(packetLen, sizeof(UINT64)); ++ ++ ASSERT((packetLenAligned - packetLen) < sizeof(UINT64)); ++ ++ // Setup the descriptor ++ desc.Type = VmbusPacketTypeDataUsingGpaDirect; ++ desc.Flags = VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED; ++ desc.DataOffset8 = descSize >> 3; // in 8-bytes grandularity ++ desc.Length8 = (UINT16)(packetLenAligned >> 3); ++ desc.TransactionId = RequestId; ++ desc.RangeCount = 1; ++ ++ desc.Range.Length = MultiPageBuffer->Length; ++ desc.Range.Offset = MultiPageBuffer->Offset; ++ ++ memcpy(desc.Range.PfnArray, MultiPageBuffer->PfnArray, PfnCount*sizeof(UINT64)); ++ ++ bufferList[0].Data = &desc; ++ bufferList[0].Length = descSize; ++ ++ bufferList[1].Data = Buffer; ++ bufferList[1].Length = BufferLen; ++ ++ bufferList[2].Data = &alignedData; ++ bufferList[2].Length = packetLenAligned - packetLen; ++ ++ ret = RingBufferWrite( ++ &Channel->Outbound, ++ bufferList, ++ 3); ++ ++ // TODO: We should determine if this is optional ++ if (ret == 0 && !GetRingBufferInterruptMask(&Channel->Outbound)) ++ { ++ VmbusChannelSetEvent(Channel); ++ } ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelRecvPacket() ++ ++Description: ++ Retrieve the user packet on the specified channel ++ ++--*/ ++// TODO: Do we ever receive a gpa direct packet other than the ones we send ? ++int ++VmbusChannelRecvPacket( ++ VMBUS_CHANNEL *Channel, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT32* BufferActualLen, ++ UINT64* RequestId ++ ) ++{ ++ VMPACKET_DESCRIPTOR desc; ++ UINT32 packetLen; ++ UINT32 userLen; ++ int ret; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ *BufferActualLen = 0; ++ *RequestId = 0; ++ ++ SpinlockAcquire(Channel->InboundLock); ++ ++ ret = RingBufferPeek(&Channel->Inbound, &desc, sizeof(VMPACKET_DESCRIPTOR)); ++ if (ret != 0) ++ { ++ SpinlockRelease(Channel->InboundLock); ++ ++ //DPRINT_DBG(VMBUS, "nothing to read!!"); ++ DPRINT_EXIT(VMBUS); ++ return 0; ++ } ++ ++ //VmbusChannelClearEvent(Channel); ++ ++ packetLen = desc.Length8 << 3; ++ userLen = packetLen - (desc.DataOffset8 << 3); ++ //ASSERT(userLen > 0); ++ ++ DPRINT_DBG(VMBUS, "packet received on channel %p relid %d ", ++ Channel, ++ Channel->OfferMsg.ChildRelId, ++ desc.Type, ++ desc.Flags, ++ desc.TransactionId, packetLen, userLen); ++ ++ *BufferActualLen = userLen; ++ ++ if (userLen > BufferLen) ++ { ++ SpinlockRelease(Channel->InboundLock); ++ ++ DPRINT_ERR(VMBUS, "buffer too small - got %d needs %d", BufferLen, userLen); ++ DPRINT_EXIT(VMBUS); ++ ++ return -1; ++ } ++ ++ *RequestId = desc.TransactionId; ++ ++ // Copy over the packet to the user buffer ++ ret = RingBufferRead(&Channel->Inbound, Buffer, userLen, (desc.DataOffset8 << 3)); ++ ++ SpinlockRelease(Channel->InboundLock); ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return 0; ++} ++ ++/*++ ++ ++Name: ++ VmbusChannelRecvPacketRaw() ++ ++Description: ++ Retrieve the raw packet on the specified channel ++ ++--*/ ++int ++VmbusChannelRecvPacketRaw( ++ VMBUS_CHANNEL *Channel, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT32* BufferActualLen, ++ UINT64* RequestId ++ ) ++{ ++ VMPACKET_DESCRIPTOR desc; ++ UINT32 packetLen; ++ UINT32 userLen; ++ int ret; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ *BufferActualLen = 0; ++ *RequestId = 0; ++ ++ SpinlockAcquire(Channel->InboundLock); ++ ++ ret = RingBufferPeek(&Channel->Inbound, &desc, sizeof(VMPACKET_DESCRIPTOR)); ++ if (ret != 0) ++ { ++ SpinlockRelease(Channel->InboundLock); ++ ++ //DPRINT_DBG(VMBUS, "nothing to read!!"); ++ DPRINT_EXIT(VMBUS); ++ return 0; ++ } ++ ++ //VmbusChannelClearEvent(Channel); ++ ++ packetLen = desc.Length8 << 3; ++ userLen = packetLen - (desc.DataOffset8 << 3); ++ ++ DPRINT_DBG(VMBUS, "packet received on channel %p relid %d ", ++ Channel, ++ Channel->OfferMsg.ChildRelId, ++ desc.Type, ++ desc.Flags, ++ desc.TransactionId, packetLen, userLen); ++ ++ *BufferActualLen = packetLen; ++ ++ if (packetLen > BufferLen) ++ { ++ SpinlockRelease(Channel->InboundLock); ++ ++ DPRINT_ERR(VMBUS, "buffer too small - needed %d bytes but got space for only %d bytes", packetLen, BufferLen); ++ DPRINT_EXIT(VMBUS); ++ return -2; ++ } ++ ++ *RequestId = desc.TransactionId; ++ ++ // Copy over the entire packet to the user buffer ++ ret = RingBufferRead(&Channel->Inbound, Buffer, packetLen, 0); ++ ++ SpinlockRelease(Channel->InboundLock); ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return 0; ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelOnChannelEvent() ++ ++Description: ++ Channel event callback ++ ++--*/ ++void ++VmbusChannelOnChannelEvent( ++ VMBUS_CHANNEL *Channel ++ ) ++{ ++ DumpVmbusChannel(Channel); ++ ASSERT(Channel->OnChannelCallback); ++#ifdef ENABLE_POLLING ++ TimerStop(Channel->PollTimer); ++ Channel->OnChannelCallback(Channel->ChannelCallbackContext); ++ TimerStart(Channel->PollTimer, 100 /* 100us */); ++#else ++ Channel->OnChannelCallback(Channel->ChannelCallbackContext); ++#endif ++} ++ ++/*++ ++ ++Name: ++ VmbusChannelOnTimer() ++ ++Description: ++ Timer event callback ++ ++--*/ ++void ++VmbusChannelOnTimer( ++ void *Context ++ ) ++{ ++ VMBUS_CHANNEL *channel = (VMBUS_CHANNEL*)Context; ++ ++ if (channel->OnChannelCallback) ++ { ++ channel->OnChannelCallback(channel->ChannelCallbackContext); ++#ifdef ENABLE_POLLING ++ TimerStart(channel->PollTimer, 100 /* 100us */); ++#endif ++ } ++} ++ ++ ++/*++ ++ ++Name: ++ DumpVmbusChannel() ++ ++Description: ++ Dump vmbus channel info to the console ++ ++--*/ ++static void ++DumpVmbusChannel( ++ VMBUS_CHANNEL *Channel ++ ) ++{ ++ DPRINT_DBG(VMBUS, "Channel (%d)", Channel->OfferMsg.ChildRelId); ++ DumpRingInfo(&Channel->Outbound, "Outbound "); ++ DumpRingInfo(&Channel->Inbound, "Inbound "); ++} ++ ++ ++// eof +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/Channel.h linux-2.6.27.29-0.1.1/drivers/staging/hv/Channel.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/Channel.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,157 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _CHANNEL_H_ ++#define _CHANNEL_H_ ++ ++#include "include/osd.h" ++#include "ChannelMgmt.h" ++ ++#pragma pack(push,1) ++ ++ ++// The format must be the same as VMDATA_GPA_DIRECT ++typedef struct _VMBUS_CHANNEL_PACKET_PAGE_BUFFER { ++ UINT16 Type; ++ UINT16 DataOffset8; ++ UINT16 Length8; ++ UINT16 Flags; ++ UINT64 TransactionId; ++ UINT32 Reserved; ++ UINT32 RangeCount; ++ PAGE_BUFFER Range[MAX_PAGE_BUFFER_COUNT]; ++} VMBUS_CHANNEL_PACKET_PAGE_BUFFER; ++ ++ ++// The format must be the same as VMDATA_GPA_DIRECT ++typedef struct _VMBUS_CHANNEL_PACKET_MULITPAGE_BUFFER { ++ UINT16 Type; ++ UINT16 DataOffset8; ++ UINT16 Length8; ++ UINT16 Flags; ++ UINT64 TransactionId; ++ UINT32 Reserved; ++ UINT32 RangeCount; // Always 1 in this case ++ MULTIPAGE_BUFFER Range; ++} VMBUS_CHANNEL_PACKET_MULITPAGE_BUFFER; ++ ++#pragma pack(pop) ++ ++// ++// Routines ++// ++ ++INTERNAL int ++VmbusChannelOpen( ++ VMBUS_CHANNEL *Channel, ++ UINT32 SendRingBufferSize, ++ UINT32 RecvRingBufferSize, ++ PVOID UserData, ++ UINT32 UserDataLen, ++ PFN_CHANNEL_CALLBACK pfnOnChannelCallback, ++ PVOID Context ++ ); ++ ++INTERNAL void ++VmbusChannelClose( ++ VMBUS_CHANNEL *Channel ++ ); ++ ++INTERNAL int ++VmbusChannelSendPacket( ++ VMBUS_CHANNEL *Channel, ++ const PVOID Buffer, ++ UINT32 BufferLen, ++ UINT64 RequestId, ++ VMBUS_PACKET_TYPE Type, ++ UINT32 Flags ++); ++ ++INTERNAL int ++VmbusChannelSendPacketPageBuffer( ++ VMBUS_CHANNEL *Channel, ++ PAGE_BUFFER PageBuffers[], ++ UINT32 PageCount, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT64 RequestId ++ ); ++ ++INTERNAL int ++VmbusChannelSendPacketMultiPageBuffer( ++ VMBUS_CHANNEL *Channel, ++ MULTIPAGE_BUFFER *MultiPageBuffer, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT64 RequestId ++); ++ ++INTERNAL int ++VmbusChannelEstablishGpadl( ++ VMBUS_CHANNEL *Channel, ++ PVOID Kbuffer, // from kmalloc() ++ UINT32 Size, // page-size multiple ++ UINT32 *GpadlHandle ++ ); ++ ++INTERNAL int ++VmbusChannelTeardownGpadl( ++ VMBUS_CHANNEL *Channel, ++ UINT32 GpadlHandle ++ ); ++ ++INTERNAL int ++VmbusChannelRecvPacket( ++ VMBUS_CHANNEL *Channel, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT32* BufferActualLen, ++ UINT64* RequestId ++ ); ++ ++INTERNAL int ++VmbusChannelRecvPacketRaw( ++ VMBUS_CHANNEL *Channel, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT32* BufferActualLen, ++ UINT64* RequestId ++ ); ++ ++INTERNAL void ++VmbusChannelOnChannelEvent( ++ VMBUS_CHANNEL *Channel ++ ); ++ ++INTERNAL void ++VmbusChannelGetDebugInfo( ++ VMBUS_CHANNEL *Channel, ++ VMBUS_CHANNEL_DEBUG_INFO *DebugInfo ++ ); ++ ++INTERNAL void ++VmbusChannelOnTimer( ++ void *Context ++ ); ++#endif //_CHANNEL_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/ChannelInterface.c linux-2.6.27.29-0.1.1/drivers/staging/hv/ChannelInterface.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/ChannelInterface.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,222 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++#include "VmbusPrivate.h" ++ ++INTERNAL int ++IVmbusChannelOpen( ++ PDEVICE_OBJECT Device, ++ UINT32 SendBufferSize, ++ UINT32 RecvRingBufferSize, ++ PVOID UserData, ++ UINT32 UserDataLen, ++ VMBUS_CHANNEL_CALLBACK ChannelCallback, ++ PVOID Context ++ ) ++{ ++ return VmbusChannelOpen( (VMBUS_CHANNEL*)Device->context, ++ SendBufferSize, ++ RecvRingBufferSize, ++ UserData, ++ UserDataLen, ++ ChannelCallback, ++ Context); ++} ++ ++ ++INTERNAL void ++IVmbusChannelClose( ++ PDEVICE_OBJECT Device ++ ) ++{ ++ VmbusChannelClose((VMBUS_CHANNEL*)Device->context); ++} ++ ++ ++INTERNAL int ++IVmbusChannelSendPacket( ++ PDEVICE_OBJECT Device, ++ const PVOID Buffer, ++ UINT32 BufferLen, ++ UINT64 RequestId, ++ UINT32 Type, ++ UINT32 Flags ++ ) ++{ ++ return VmbusChannelSendPacket((VMBUS_CHANNEL*)Device->context, ++ Buffer, ++ BufferLen, ++ RequestId, ++ Type, ++ Flags); ++} ++ ++INTERNAL int ++IVmbusChannelSendPacketPageBuffer( ++ PDEVICE_OBJECT Device, ++ PAGE_BUFFER PageBuffers[], ++ UINT32 PageCount, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT64 RequestId ++ ) ++{ ++ return VmbusChannelSendPacketPageBuffer((VMBUS_CHANNEL*)Device->context, ++ PageBuffers, ++ PageCount, ++ Buffer, ++ BufferLen, ++ RequestId); ++} ++ ++INTERNAL int ++IVmbusChannelSendPacketMultiPageBuffer( ++ PDEVICE_OBJECT Device, ++ MULTIPAGE_BUFFER *MultiPageBuffer, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT64 RequestId ++ ) ++{ ++ return VmbusChannelSendPacketMultiPageBuffer((VMBUS_CHANNEL*)Device->context, ++ MultiPageBuffer, ++ Buffer, ++ BufferLen, ++ RequestId); ++} ++ ++INTERNAL int ++IVmbusChannelRecvPacket ( ++ PDEVICE_OBJECT Device, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT32* BufferActualLen, ++ UINT64* RequestId ++ ) ++{ ++ return VmbusChannelRecvPacket((VMBUS_CHANNEL*)Device->context, ++ Buffer, ++ BufferLen, ++ BufferActualLen, ++ RequestId); ++} ++ ++INTERNAL int ++IVmbusChannelRecvPacketRaw( ++ PDEVICE_OBJECT Device, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT32* BufferActualLen, ++ UINT64* RequestId ++ ) ++{ ++ return VmbusChannelRecvPacketRaw((VMBUS_CHANNEL*)Device->context, ++ Buffer, ++ BufferLen, ++ BufferActualLen, ++ RequestId); ++} ++ ++INTERNAL int ++IVmbusChannelEstablishGpadl( ++ PDEVICE_OBJECT Device, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT32* GpadlHandle ++ ) ++{ ++ return VmbusChannelEstablishGpadl((VMBUS_CHANNEL*)Device->context, ++ Buffer, ++ BufferLen, ++ GpadlHandle); ++} ++ ++INTERNAL int ++IVmbusChannelTeardownGpadl( ++ PDEVICE_OBJECT Device, ++ UINT32 GpadlHandle ++ ) ++{ ++ return VmbusChannelTeardownGpadl((VMBUS_CHANNEL*)Device->context, ++ GpadlHandle); ++ ++} ++ ++INTERNAL void ++GetChannelInterface( ++ VMBUS_CHANNEL_INTERFACE *ChannelInterface ++ ) ++{ ++ ChannelInterface->Open = IVmbusChannelOpen; ++ ChannelInterface->Close = IVmbusChannelClose; ++ ChannelInterface->SendPacket = IVmbusChannelSendPacket; ++ ChannelInterface->SendPacketPageBuffer = IVmbusChannelSendPacketPageBuffer; ++ ChannelInterface->SendPacketMultiPageBuffer = IVmbusChannelSendPacketMultiPageBuffer; ++ ChannelInterface->RecvPacket = IVmbusChannelRecvPacket; ++ ChannelInterface->RecvPacketRaw = IVmbusChannelRecvPacketRaw; ++ ChannelInterface->EstablishGpadl = IVmbusChannelEstablishGpadl; ++ ChannelInterface->TeardownGpadl = IVmbusChannelTeardownGpadl; ++ ChannelInterface->GetInfo = GetChannelInfo; ++} ++ ++ ++INTERNAL void ++GetChannelInfo( ++ PDEVICE_OBJECT Device, ++ DEVICE_INFO *DeviceInfo ++ ) ++{ ++ VMBUS_CHANNEL_DEBUG_INFO debugInfo; ++ ++ if (Device->context) ++ { ++ VmbusChannelGetDebugInfo((VMBUS_CHANNEL*)Device->context, &debugInfo); ++ ++ DeviceInfo->ChannelId = debugInfo.RelId; ++ DeviceInfo->ChannelState = debugInfo.State; ++ memcpy(&DeviceInfo->ChannelType, &debugInfo.InterfaceType, sizeof(GUID)); ++ memcpy(&DeviceInfo->ChannelInstance, &debugInfo.InterfaceInstance, sizeof(GUID)); ++ ++ DeviceInfo->MonitorId = debugInfo.MonitorId; ++ ++ DeviceInfo->ServerMonitorPending = debugInfo.ServerMonitorPending; ++ DeviceInfo->ServerMonitorLatency = debugInfo.ServerMonitorLatency; ++ DeviceInfo->ServerMonitorConnectionId = debugInfo.ServerMonitorConnectionId; ++ ++ DeviceInfo->ClientMonitorPending = debugInfo.ClientMonitorPending; ++ DeviceInfo->ClientMonitorLatency = debugInfo.ClientMonitorLatency; ++ DeviceInfo->ClientMonitorConnectionId = debugInfo.ClientMonitorConnectionId; ++ ++ DeviceInfo->Inbound.InterruptMask = debugInfo.Inbound.CurrentInterruptMask; ++ DeviceInfo->Inbound.ReadIndex = debugInfo.Inbound.CurrentReadIndex; ++ DeviceInfo->Inbound.WriteIndex = debugInfo.Inbound.CurrentWriteIndex; ++ DeviceInfo->Inbound.BytesAvailToRead = debugInfo.Inbound.BytesAvailToRead; ++ DeviceInfo->Inbound.BytesAvailToWrite = debugInfo.Inbound.BytesAvailToWrite; ++ ++ DeviceInfo->Outbound.InterruptMask = debugInfo.Outbound.CurrentInterruptMask; ++ DeviceInfo->Outbound.ReadIndex = debugInfo.Outbound.CurrentReadIndex; ++ DeviceInfo->Outbound.WriteIndex = debugInfo.Outbound.CurrentWriteIndex; ++ DeviceInfo->Outbound.BytesAvailToRead = debugInfo.Outbound.BytesAvailToRead; ++ DeviceInfo->Outbound.BytesAvailToWrite = debugInfo.Outbound.BytesAvailToWrite; ++ } ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/ChannelInterface.h linux-2.6.27.29-0.1.1/drivers/staging/hv/ChannelInterface.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/ChannelInterface.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,41 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _CHANNEL_INTERFACE_H_ ++#define _CHANNEL_INTERFACE_H_ ++ ++#include "include/VmbusApi.h" ++ ++INTERNAL void ++GetChannelInterface( ++ VMBUS_CHANNEL_INTERFACE *ChannelInterface ++ ); ++ ++INTERNAL void ++GetChannelInfo( ++ PDEVICE_OBJECT Device, ++ DEVICE_INFO *DeviceInfo ++ ); ++ ++#endif // _CHANNEL_INTERFACE_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/ChannelMgmt.c linux-2.6.27.29-0.1.1/drivers/staging/hv/ChannelMgmt.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/ChannelMgmt.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,826 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#include "include/osd.h" ++#include "include/logging.h" ++ ++#include "VmbusPrivate.h" ++ ++// ++// Defines ++// ++ ++// ++// Data types ++// ++ ++typedef void (*PFN_CHANNEL_MESSAGE_HANDLER)(VMBUS_CHANNEL_MESSAGE_HEADER* msg); ++ ++typedef struct _VMBUS_CHANNEL_MESSAGE_TABLE_ENTRY { ++ VMBUS_CHANNEL_MESSAGE_TYPE messageType; ++ PFN_CHANNEL_MESSAGE_HANDLER messageHandler; ++} VMBUS_CHANNEL_MESSAGE_TABLE_ENTRY; ++ ++// ++// Internal routines ++// ++ ++static void ++VmbusChannelOnOffer( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ); ++static void ++VmbusChannelOnOpenResult( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ); ++ ++static void ++VmbusChannelOnOfferRescind( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ); ++ ++static void ++VmbusChannelOnGpadlCreated( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ); ++ ++static void ++VmbusChannelOnGpadlTorndown( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ); ++ ++static void ++VmbusChannelOnOffersDelivered( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ); ++ ++static void ++VmbusChannelOnVersionResponse( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ); ++ ++static void ++VmbusChannelProcessOffer( ++ PVOID context ++ ); ++ ++static void ++VmbusChannelProcessRescindOffer( ++ PVOID context ++ ); ++ ++ ++// ++// Globals ++// ++ ++#define MAX_NUM_DEVICE_CLASSES_SUPPORTED 4 ++ ++const GUID gSupportedDeviceClasses[MAX_NUM_DEVICE_CLASSES_SUPPORTED]= { ++ //{ba6163d9-04a1-4d29-b605-72e2ffb1dc7f} ++ {.Data = {0xd9, 0x63, 0x61, 0xba, 0xa1, 0x04, 0x29, 0x4d, 0xb6, 0x05, 0x72, 0xe2, 0xff, 0xb1, 0xdc, 0x7f}},// Storage - SCSI ++ //{F8615163-DF3E-46c5-913F-F2D2F965ED0E} ++ {.Data = {0x63, 0x51, 0x61, 0xF8, 0x3E, 0xDF, 0xc5, 0x46, 0x91, 0x3F, 0xF2, 0xD2, 0xF9, 0x65, 0xED, 0x0E}}, // Network ++ //{CFA8B69E-5B4A-4cc0-B98B-8BA1A1F3F95A} ++ {.Data = {0x9E, 0xB6, 0xA8, 0xCF, 0x4A, 0x5B, 0xc0, 0x4c, 0xB9, 0x8B, 0x8B, 0xA1, 0xA1, 0xF3, 0xF9, 0x5A}}, // Input ++ //{32412632-86cb-44a2-9b5c-50d1417354f5} ++ {.Data = {0x32, 0x26, 0x41, 0x32, 0xcb, 0x86, 0xa2, 0x44, 0x9b, 0x5c, 0x50, 0xd1, 0x41, 0x73, 0x54, 0xf5}}, // IDE ++ ++}; ++ ++// Channel message dispatch table ++VMBUS_CHANNEL_MESSAGE_TABLE_ENTRY gChannelMessageTable[ChannelMessageCount]= { ++ {ChannelMessageInvalid, NULL}, ++ {ChannelMessageOfferChannel, VmbusChannelOnOffer}, ++ {ChannelMessageRescindChannelOffer, VmbusChannelOnOfferRescind}, ++ {ChannelMessageRequestOffers, NULL}, ++ {ChannelMessageAllOffersDelivered, VmbusChannelOnOffersDelivered}, ++ {ChannelMessageOpenChannel, NULL}, ++ {ChannelMessageOpenChannelResult, VmbusChannelOnOpenResult}, ++ {ChannelMessageCloseChannel, NULL}, ++ {ChannelMessageGpadlHeader, NULL}, ++ {ChannelMessageGpadlBody, NULL}, ++ {ChannelMessageGpadlCreated, VmbusChannelOnGpadlCreated}, ++ {ChannelMessageGpadlTeardown, NULL}, ++ {ChannelMessageGpadlTorndown, VmbusChannelOnGpadlTorndown}, ++ {ChannelMessageRelIdReleased, NULL}, ++ {ChannelMessageInitiateContact, NULL}, ++ {ChannelMessageVersionResponse, VmbusChannelOnVersionResponse}, ++ {ChannelMessageUnload, NULL}, ++}; ++ ++/*++ ++ ++Name: ++ AllocVmbusChannel() ++ ++Description: ++ Allocate and initialize a vmbus channel object ++ ++--*/ ++VMBUS_CHANNEL* AllocVmbusChannel(void) ++{ ++ VMBUS_CHANNEL* channel; ++ ++ channel = (VMBUS_CHANNEL*) MemAllocAtomic(sizeof(VMBUS_CHANNEL)); ++ if (!channel) ++ { ++ return NULL; ++ } ++ ++ memset(channel, 0,sizeof(VMBUS_CHANNEL)); ++ channel->InboundLock = SpinlockCreate(); ++ if (!channel->InboundLock) ++ { ++ MemFree(channel); ++ return NULL; ++ } ++ ++ channel->PollTimer = TimerCreate(VmbusChannelOnTimer, channel); ++ if (!channel->PollTimer) ++ { ++ SpinlockClose(channel->InboundLock); ++ MemFree(channel); ++ return NULL; ++ } ++ ++ //channel->dataWorkQueue = WorkQueueCreate("data"); ++ channel->ControlWQ = WorkQueueCreate("control"); ++ if (!channel->ControlWQ) ++ { ++ TimerClose(channel->PollTimer); ++ SpinlockClose(channel->InboundLock); ++ MemFree(channel); ++ return NULL; ++ } ++ ++ return channel; ++} ++ ++/*++ ++ ++Name: ++ ReleaseVmbusChannel() ++ ++Description: ++ Release the vmbus channel object itself ++ ++--*/ ++static inline void ReleaseVmbusChannel(void* Context) ++{ ++ VMBUS_CHANNEL* channel = (VMBUS_CHANNEL*)Context; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ DPRINT_DBG(VMBUS, "releasing channel (%p)", channel); ++ WorkQueueClose(channel->ControlWQ); ++ DPRINT_DBG(VMBUS, "channel released (%p)", channel); ++ ++ MemFree(channel); ++ ++ DPRINT_EXIT(VMBUS); ++} ++ ++/*++ ++ ++Name: ++ FreeVmbusChannel() ++ ++Description: ++ Release the resources used by the vmbus channel object ++ ++--*/ ++void FreeVmbusChannel(VMBUS_CHANNEL* Channel) ++{ ++ SpinlockClose(Channel->InboundLock); ++ TimerClose(Channel->PollTimer); ++ ++ // We have to release the channel's workqueue/thread in the vmbus's workqueue/thread context ++ // ie we can't destroy ourselves. ++ WorkQueueQueueWorkItem(gVmbusConnection.WorkQueue, ReleaseVmbusChannel, (void*)Channel); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelProcessOffer() ++ ++Description: ++ Process the offer by creating a channel/device associated with this offer ++ ++--*/ ++static void ++VmbusChannelProcessOffer( ++ PVOID context ++ ) ++{ ++ int ret=0; ++ VMBUS_CHANNEL* newChannel=(VMBUS_CHANNEL*)context; ++ LIST_ENTRY* anchor; ++ LIST_ENTRY* curr; ++ BOOL fNew=TRUE; ++ VMBUS_CHANNEL* channel; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ // Make sure this is a new offer ++ SpinlockAcquire(gVmbusConnection.ChannelLock); ++ ++ ITERATE_LIST_ENTRIES(anchor, curr, &gVmbusConnection.ChannelList) ++ { ++ channel = CONTAINING_RECORD(curr, VMBUS_CHANNEL, ListEntry); ++ ++ if (!memcmp(&channel->OfferMsg.Offer.InterfaceType, &newChannel->OfferMsg.Offer.InterfaceType,sizeof(GUID)) && ++ !memcmp(&channel->OfferMsg.Offer.InterfaceInstance, &newChannel->OfferMsg.Offer.InterfaceInstance, sizeof(GUID))) ++ { ++ fNew = FALSE; ++ break; ++ } ++ } ++ ++ if (fNew) ++ { ++ INSERT_TAIL_LIST(&gVmbusConnection.ChannelList, &newChannel->ListEntry); ++ } ++ SpinlockRelease(gVmbusConnection.ChannelLock); ++ ++ if (!fNew) ++ { ++ DPRINT_DBG(VMBUS, "Ignoring duplicate offer for relid (%d)", newChannel->OfferMsg.ChildRelId); ++ FreeVmbusChannel(newChannel); ++ DPRINT_EXIT(VMBUS); ++ return; ++ } ++ ++ // Start the process of binding this offer to the driver ++ // We need to set the DeviceObject field before calling VmbusChildDeviceAdd() ++ newChannel->DeviceObject = VmbusChildDeviceCreate( ++ newChannel->OfferMsg.Offer.InterfaceType, ++ newChannel->OfferMsg.Offer.InterfaceInstance, ++ newChannel); ++ ++ DPRINT_DBG(VMBUS, "child device object allocated - %p", newChannel->DeviceObject); ++ ++ // Add the new device to the bus. This will kick off device-driver binding ++ // which eventually invokes the device driver's AddDevice() method. ++ ret = VmbusChildDeviceAdd(newChannel->DeviceObject); ++ if (ret != 0) ++ { ++ DPRINT_ERR(VMBUS, "unable to add child device object (relid %d)", ++ newChannel->OfferMsg.ChildRelId); ++ ++ SpinlockAcquire(gVmbusConnection.ChannelLock); ++ REMOVE_ENTRY_LIST(&newChannel->ListEntry); ++ SpinlockRelease(gVmbusConnection.ChannelLock); ++ ++ FreeVmbusChannel(newChannel); ++ } ++ else ++ { ++ // This state is used to indicate a successful open so that when we do close the channel normally, ++ // we can cleanup properly ++ newChannel->State = CHANNEL_OPEN_STATE; ++ } ++ DPRINT_EXIT(VMBUS); ++} ++ ++/*++ ++ ++Name: ++ VmbusChannelProcessRescindOffer() ++ ++Description: ++ Rescind the offer by initiating a device removal ++ ++--*/ ++static void ++VmbusChannelProcessRescindOffer( ++ PVOID context ++ ) ++{ ++ VMBUS_CHANNEL* channel=(VMBUS_CHANNEL*)context; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ VmbusChildDeviceRemove(channel->DeviceObject); ++ ++ DPRINT_EXIT(VMBUS); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelOnOffer() ++ ++Description: ++ Handler for channel offers from vmbus in parent partition. We ignore all offers except ++ network and storage offers. For each network and storage offers, we create a channel object ++ and queue a work item to the channel object to process the offer synchronously ++ ++--*/ ++static void ++VmbusChannelOnOffer( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ) ++{ ++ VMBUS_CHANNEL_OFFER_CHANNEL* offer = (VMBUS_CHANNEL_OFFER_CHANNEL*)hdr; ++ VMBUS_CHANNEL* newChannel; ++ ++ GUID *guidType; ++ GUID *guidInstance; ++ int i; ++ int fSupported=0; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ for (i=0; iOffer.InterfaceType, &gSupportedDeviceClasses[i], sizeof(GUID)) == 0) ++ { ++ fSupported = 1; ++ break; ++ } ++ } ++ ++ if (!fSupported) ++ { ++ DPRINT_DBG(VMBUS, "Ignoring channel offer notification for child relid %d", offer->ChildRelId); ++ DPRINT_EXIT(VMBUS); ++ ++ return; ++ } ++ ++ guidType = &offer->Offer.InterfaceType; ++ guidInstance = &offer->Offer.InterfaceInstance; ++ ++ DPRINT_INFO(VMBUS, "Channel offer notification - child relid %d monitor id %d allocated %d, " ++ "type {%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x} " ++ "instance {%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}", ++ offer->ChildRelId, ++ offer->MonitorId, ++ offer->MonitorAllocated, ++ guidType->Data[3], guidType->Data[2], guidType->Data[1], guidType->Data[0], guidType->Data[5], guidType->Data[4], guidType->Data[7], guidType->Data[6], guidType->Data[8], guidType->Data[9], guidType->Data[10], guidType->Data[11], guidType->Data[12], guidType->Data[13], guidType->Data[14], guidType->Data[15], ++ guidInstance->Data[3], guidInstance->Data[2], guidInstance->Data[1], guidInstance->Data[0], guidInstance->Data[5], guidInstance->Data[4], guidInstance->Data[7], guidInstance->Data[6], guidInstance->Data[8], guidInstance->Data[9], guidInstance->Data[10], guidInstance->Data[11], guidInstance->Data[12], guidInstance->Data[13], guidInstance->Data[14], guidInstance->Data[15]); ++ ++ // Allocate the channel object and save this offer. ++ newChannel = AllocVmbusChannel(); ++ if (!newChannel) ++ { ++ DPRINT_ERR(VMBUS, "unable to allocate channel object"); ++ return; ++ } ++ ++ DPRINT_DBG(VMBUS, "channel object allocated - %p", newChannel); ++ ++ memcpy(&newChannel->OfferMsg, offer, sizeof(VMBUS_CHANNEL_OFFER_CHANNEL)); ++ newChannel->MonitorGroup = (UINT8)offer->MonitorId / 32; ++ newChannel->MonitorBit = (UINT8)offer->MonitorId % 32; ++ ++ // TODO: Make sure the offer comes from our parent partition ++ WorkQueueQueueWorkItem(newChannel->ControlWQ, VmbusChannelProcessOffer, newChannel); ++ ++ DPRINT_EXIT(VMBUS); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelOnOfferRescind() ++ ++Description: ++ Rescind offer handler. We queue a work item to process this offer ++ synchronously ++ ++--*/ ++static void ++VmbusChannelOnOfferRescind( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ) ++{ ++ VMBUS_CHANNEL_RESCIND_OFFER* rescind = (VMBUS_CHANNEL_RESCIND_OFFER*)hdr; ++ VMBUS_CHANNEL* channel; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ channel = GetChannelFromRelId(rescind->ChildRelId); ++ if (channel == NULL) ++ { ++ DPRINT_DBG(VMBUS, "channel not found for relId %d", rescind->ChildRelId); ++ return; ++ } ++ ++ WorkQueueQueueWorkItem(channel->ControlWQ, VmbusChannelProcessRescindOffer, channel); ++ ++ DPRINT_EXIT(VMBUS); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelOnOffersDelivered() ++ ++Description: ++ This is invoked when all offers have been delivered. ++ Nothing to do here. ++ ++--*/ ++static void ++VmbusChannelOnOffersDelivered( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ) ++{ ++ DPRINT_ENTER(VMBUS); ++ DPRINT_EXIT(VMBUS); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelOnOpenResult() ++ ++Description: ++ Open result handler. This is invoked when we received a response ++ to our channel open request. Find the matching request, copy the ++ response and signal the requesting thread. ++ ++--*/ ++static void ++VmbusChannelOnOpenResult( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ) ++{ ++ VMBUS_CHANNEL_OPEN_RESULT* result = (VMBUS_CHANNEL_OPEN_RESULT*)hdr; ++ LIST_ENTRY* anchor; ++ LIST_ENTRY* curr; ++ VMBUS_CHANNEL_MSGINFO* msgInfo; ++ VMBUS_CHANNEL_MESSAGE_HEADER* requestHeader; ++ VMBUS_CHANNEL_OPEN_CHANNEL* openMsg; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ DPRINT_DBG(VMBUS, "vmbus open result - %d", result->Status); ++ ++ // Find the open msg, copy the result and signal/unblock the wait event ++ SpinlockAcquire(gVmbusConnection.ChannelMsgLock); ++ ++ ITERATE_LIST_ENTRIES(anchor, curr, &gVmbusConnection.ChannelMsgList) ++ { ++ msgInfo = (VMBUS_CHANNEL_MSGINFO*) curr; ++ requestHeader = (VMBUS_CHANNEL_MESSAGE_HEADER*)msgInfo->Msg; ++ ++ if (requestHeader->MessageType == ChannelMessageOpenChannel) ++ { ++ openMsg = (VMBUS_CHANNEL_OPEN_CHANNEL*)msgInfo->Msg; ++ if (openMsg->ChildRelId == result->ChildRelId && ++ openMsg->OpenId == result->OpenId) ++ { ++ memcpy(&msgInfo->Response.OpenResult, result, sizeof(VMBUS_CHANNEL_OPEN_RESULT)); ++ WaitEventSet(msgInfo->WaitEvent); ++ break; ++ } ++ } ++ } ++ SpinlockRelease(gVmbusConnection.ChannelMsgLock); ++ ++ DPRINT_EXIT(VMBUS); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelOnGpadlCreated() ++ ++Description: ++ GPADL created handler. This is invoked when we received a response ++ to our gpadl create request. Find the matching request, copy the ++ response and signal the requesting thread. ++ ++--*/ ++static void ++VmbusChannelOnGpadlCreated( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ) ++{ ++ VMBUS_CHANNEL_GPADL_CREATED *gpadlCreated = (VMBUS_CHANNEL_GPADL_CREATED*)hdr; ++ LIST_ENTRY *anchor; ++ LIST_ENTRY *curr; ++ VMBUS_CHANNEL_MSGINFO *msgInfo; ++ VMBUS_CHANNEL_MESSAGE_HEADER *requestHeader; ++ VMBUS_CHANNEL_GPADL_HEADER *gpadlHeader; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ DPRINT_DBG(VMBUS, "vmbus gpadl created result - %d", gpadlCreated->CreationStatus); ++ ++ // Find the establish msg, copy the result and signal/unblock the wait event ++ SpinlockAcquire(gVmbusConnection.ChannelMsgLock); ++ ++ ITERATE_LIST_ENTRIES(anchor, curr, &gVmbusConnection.ChannelMsgList) ++ { ++ msgInfo = (VMBUS_CHANNEL_MSGINFO*) curr; ++ requestHeader = (VMBUS_CHANNEL_MESSAGE_HEADER*)msgInfo->Msg; ++ ++ if (requestHeader->MessageType == ChannelMessageGpadlHeader) ++ { ++ gpadlHeader = (VMBUS_CHANNEL_GPADL_HEADER*)requestHeader; ++ ++ if ((gpadlCreated->ChildRelId == gpadlHeader->ChildRelId) && ++ (gpadlCreated->Gpadl == gpadlHeader->Gpadl)) ++ { ++ memcpy(&msgInfo->Response.GpadlCreated, gpadlCreated, sizeof(VMBUS_CHANNEL_GPADL_CREATED)); ++ WaitEventSet(msgInfo->WaitEvent); ++ break; ++ } ++ } ++ } ++ SpinlockRelease(gVmbusConnection.ChannelMsgLock); ++ ++ DPRINT_EXIT(VMBUS); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelOnGpadlTorndown() ++ ++Description: ++ GPADL torndown handler. This is invoked when we received a response ++ to our gpadl teardown request. Find the matching request, copy the ++ response and signal the requesting thread. ++ ++--*/ ++static void ++VmbusChannelOnGpadlTorndown( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ) ++{ ++ VMBUS_CHANNEL_GPADL_TORNDOWN* gpadlTorndown = (VMBUS_CHANNEL_GPADL_TORNDOWN*)hdr; ++ LIST_ENTRY* anchor; ++ LIST_ENTRY* curr; ++ VMBUS_CHANNEL_MSGINFO* msgInfo; ++ VMBUS_CHANNEL_MESSAGE_HEADER *requestHeader; ++ VMBUS_CHANNEL_GPADL_TEARDOWN *gpadlTeardown; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ // Find the open msg, copy the result and signal/unblock the wait event ++ SpinlockAcquire(gVmbusConnection.ChannelMsgLock); ++ ++ ITERATE_LIST_ENTRIES(anchor, curr, &gVmbusConnection.ChannelMsgList) ++ { ++ msgInfo = (VMBUS_CHANNEL_MSGINFO*) curr; ++ requestHeader = (VMBUS_CHANNEL_MESSAGE_HEADER*)msgInfo->Msg; ++ ++ if (requestHeader->MessageType == ChannelMessageGpadlTeardown) ++ { ++ gpadlTeardown = (VMBUS_CHANNEL_GPADL_TEARDOWN*)requestHeader; ++ ++ if (gpadlTorndown->Gpadl == gpadlTeardown->Gpadl) ++ { ++ memcpy(&msgInfo->Response.GpadlTorndown, gpadlTorndown, sizeof(VMBUS_CHANNEL_GPADL_TORNDOWN)); ++ WaitEventSet(msgInfo->WaitEvent); ++ break; ++ } ++ } ++ } ++ SpinlockRelease(gVmbusConnection.ChannelMsgLock); ++ ++ DPRINT_EXIT(VMBUS); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelOnVersionResponse() ++ ++Description: ++ Version response handler. This is invoked when we received a response ++ to our initiate contact request. Find the matching request, copy the ++ response and signal the requesting thread. ++ ++--*/ ++static void ++VmbusChannelOnVersionResponse( ++ PVMBUS_CHANNEL_MESSAGE_HEADER hdr ++ ) ++{ ++ LIST_ENTRY* anchor; ++ LIST_ENTRY* curr; ++ VMBUS_CHANNEL_MSGINFO *msgInfo; ++ VMBUS_CHANNEL_MESSAGE_HEADER *requestHeader; ++ VMBUS_CHANNEL_INITIATE_CONTACT *initiate; ++ VMBUS_CHANNEL_VERSION_RESPONSE *versionResponse = (VMBUS_CHANNEL_VERSION_RESPONSE*)hdr; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ SpinlockAcquire(gVmbusConnection.ChannelMsgLock); ++ ++ ITERATE_LIST_ENTRIES(anchor, curr, &gVmbusConnection.ChannelMsgList) ++ { ++ msgInfo = (VMBUS_CHANNEL_MSGINFO*) curr; ++ requestHeader = (VMBUS_CHANNEL_MESSAGE_HEADER*)msgInfo->Msg; ++ ++ if (requestHeader->MessageType == ChannelMessageInitiateContact) ++ { ++ initiate = (VMBUS_CHANNEL_INITIATE_CONTACT*)requestHeader; ++ memcpy(&msgInfo->Response.VersionResponse, versionResponse, sizeof(VMBUS_CHANNEL_VERSION_RESPONSE)); ++ WaitEventSet(msgInfo->WaitEvent); ++ } ++ } ++ SpinlockRelease(gVmbusConnection.ChannelMsgLock); ++ ++ DPRINT_EXIT(VMBUS); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusOnChannelMessage() ++ ++Description: ++ Handler for channel protocol messages. ++ This is invoked in the vmbus worker thread context. ++ ++--*/ ++VOID ++VmbusOnChannelMessage( ++ void *Context ++ ) ++{ ++ HV_MESSAGE *msg=(HV_MESSAGE*)Context; ++ VMBUS_CHANNEL_MESSAGE_HEADER* hdr; ++ int size; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ hdr = (VMBUS_CHANNEL_MESSAGE_HEADER*)msg->u.Payload; ++ size=msg->Header.PayloadSize; ++ ++ DPRINT_DBG(VMBUS, "message type %d size %d", hdr->MessageType, size); ++ ++ if (hdr->MessageType >= ChannelMessageCount) ++ { ++ DPRINT_ERR(VMBUS, "Received invalid channel message type %d size %d", hdr->MessageType, size); ++ PrintBytes((unsigned char *)msg->u.Payload, size); ++ MemFree(msg); ++ return; ++ } ++ ++ if (gChannelMessageTable[hdr->MessageType].messageHandler) ++ { ++ gChannelMessageTable[hdr->MessageType].messageHandler(hdr); ++ } ++ else ++ { ++ DPRINT_ERR(VMBUS, "Unhandled channel message type %d", hdr->MessageType); ++ } ++ ++ // Free the msg that was allocated in VmbusOnMsgDPC() ++ MemFree(msg); ++ DPRINT_EXIT(VMBUS); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChannelRequestOffers() ++ ++Description: ++ Send a request to get all our pending offers. ++ ++--*/ ++int ++VmbusChannelRequestOffers( ++ VOID ++ ) ++{ ++ int ret=0; ++ VMBUS_CHANNEL_MESSAGE_HEADER* msg; ++ VMBUS_CHANNEL_MSGINFO* msgInfo; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ msgInfo = ++ (VMBUS_CHANNEL_MSGINFO*)MemAlloc(sizeof(VMBUS_CHANNEL_MSGINFO) + sizeof(VMBUS_CHANNEL_MESSAGE_HEADER)); ++ ASSERT(msgInfo != NULL); ++ ++ msgInfo->WaitEvent = WaitEventCreate(); ++ msg = (VMBUS_CHANNEL_MESSAGE_HEADER*)msgInfo->Msg; ++ ++ msg->MessageType = ChannelMessageRequestOffers; ++ ++ /*SpinlockAcquire(gVmbusConnection.channelMsgLock); ++ INSERT_TAIL_LIST(&gVmbusConnection.channelMsgList, &msgInfo->msgListEntry); ++ SpinlockRelease(gVmbusConnection.channelMsgLock);*/ ++ ++ ret = VmbusPostMessage(msg, sizeof(VMBUS_CHANNEL_MESSAGE_HEADER)); ++ if (ret != 0) ++ { ++ DPRINT_ERR(VMBUS, "Unable to request offers - %d", ret); ++ ++ /*SpinlockAcquire(gVmbusConnection.channelMsgLock); ++ REMOVE_ENTRY_LIST(&msgInfo->msgListEntry); ++ SpinlockRelease(gVmbusConnection.channelMsgLock);*/ ++ ++ goto Cleanup; ++ } ++ //WaitEventWait(msgInfo->waitEvent); ++ ++ /*SpinlockAcquire(gVmbusConnection.channelMsgLock); ++ REMOVE_ENTRY_LIST(&msgInfo->msgListEntry); ++ SpinlockRelease(gVmbusConnection.channelMsgLock);*/ ++ ++ ++Cleanup: ++ if (msgInfo) ++ { ++ WaitEventClose(msgInfo->WaitEvent); ++ MemFree(msgInfo); ++ } ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++} ++ ++/*++ ++ ++Name: ++ VmbusChannelReleaseUnattachedChannels() ++ ++Description: ++ Release channels that are unattached/unconnected ie (no drivers associated) ++ ++--*/ ++void ++VmbusChannelReleaseUnattachedChannels( ++ VOID ++ ) ++{ ++ LIST_ENTRY *entry; ++ VMBUS_CHANNEL *channel; ++ VMBUS_CHANNEL *start=NULL; ++ ++ SpinlockAcquire(gVmbusConnection.ChannelLock); ++ ++ while (!IsListEmpty(&gVmbusConnection.ChannelList)) ++ { ++ entry = TOP_LIST_ENTRY(&gVmbusConnection.ChannelList); ++ channel = CONTAINING_RECORD(entry, VMBUS_CHANNEL, ListEntry); ++ ++ if (channel == start) ++ break; ++ ++ if (!channel->DeviceObject->Driver) ++ { ++ REMOVE_ENTRY_LIST(&channel->ListEntry); ++ DPRINT_INFO(VMBUS, "Releasing unattached device object %p", channel->DeviceObject); ++ ++ VmbusChildDeviceRemove(channel->DeviceObject); ++ FreeVmbusChannel(channel); ++ } ++ else ++ { ++ if (!start) ++ { ++ start = channel; ++ } ++ } ++ } ++ ++ SpinlockRelease(gVmbusConnection.ChannelLock); ++} ++ ++// eof ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/ChannelMgmt.h linux-2.6.27.29-0.1.1/drivers/staging/hv/ChannelMgmt.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/ChannelMgmt.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,156 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _CHANNEL_MGMT_H_ ++#define _CHANNEL_MGMT_H_ ++ ++#include "include/osd.h" ++#include "include/List.h" ++#include "RingBuffer.h" ++ ++#include "include/VmbusChannelInterface.h" ++#include "include/ChannelMessages.h" ++ ++ ++ ++typedef void (*PFN_CHANNEL_CALLBACK)(PVOID context); ++ ++typedef enum { ++ CHANNEL_OFFER_STATE, ++ CHANNEL_OPENING_STATE, ++ CHANNEL_OPEN_STATE, ++} VMBUS_CHANNEL_STATE; ++ ++typedef struct _VMBUS_CHANNEL { ++ LIST_ENTRY ListEntry; ++ ++ DEVICE_OBJECT* DeviceObject; ++ ++ HANDLE PollTimer; // SA-111 workaround ++ ++ VMBUS_CHANNEL_STATE State; ++ ++ VMBUS_CHANNEL_OFFER_CHANNEL OfferMsg; ++ // These are based on the OfferMsg.MonitorId. Save it here for easy access. ++ UINT8 MonitorGroup; ++ UINT8 MonitorBit; ++ ++ UINT32 RingBufferGpadlHandle; ++ ++ // Allocated memory for ring buffer ++ VOID* RingBufferPages; ++ UINT32 RingBufferPageCount; ++ RING_BUFFER_INFO Outbound; // send to parent ++ RING_BUFFER_INFO Inbound; // receive from parent ++ HANDLE InboundLock; ++ HANDLE ControlWQ; ++ ++ // Channel callback are invoked in this workqueue context ++ //HANDLE dataWorkQueue; ++ ++ PFN_CHANNEL_CALLBACK OnChannelCallback; ++ PVOID ChannelCallbackContext; ++ ++} VMBUS_CHANNEL; ++ ++ ++typedef struct _VMBUS_CHANNEL_DEBUG_INFO { ++ UINT32 RelId; ++ VMBUS_CHANNEL_STATE State; ++ GUID InterfaceType; ++ GUID InterfaceInstance; ++ UINT32 MonitorId; ++ UINT32 ServerMonitorPending; ++ UINT32 ServerMonitorLatency; ++ UINT32 ServerMonitorConnectionId; ++ UINT32 ClientMonitorPending; ++ UINT32 ClientMonitorLatency; ++ UINT32 ClientMonitorConnectionId; ++ ++ RING_BUFFER_DEBUG_INFO Inbound; ++ RING_BUFFER_DEBUG_INFO Outbound; ++} VMBUS_CHANNEL_DEBUG_INFO; ++ ++ ++typedef union { ++ VMBUS_CHANNEL_VERSION_SUPPORTED VersionSupported; ++ VMBUS_CHANNEL_OPEN_RESULT OpenResult; ++ VMBUS_CHANNEL_GPADL_TORNDOWN GpadlTorndown; ++ VMBUS_CHANNEL_GPADL_CREATED GpadlCreated; ++ VMBUS_CHANNEL_VERSION_RESPONSE VersionResponse; ++} VMBUS_CHANNEL_MESSAGE_RESPONSE; ++ ++ ++// Represents each channel msg on the vmbus connection ++// This is a variable-size data structure depending on ++// the msg type itself ++typedef struct _VMBUS_CHANNEL_MSGINFO { ++ // Bookkeeping stuff ++ LIST_ENTRY MsgListEntry; ++ ++ // So far, this is only used to handle gpadl body message ++ LIST_ENTRY SubMsgList; ++ ++ // Synchronize the request/response if needed ++ HANDLE WaitEvent; ++ ++ VMBUS_CHANNEL_MESSAGE_RESPONSE Response; ++ ++ UINT32 MessageSize; ++ // The channel message that goes out on the "wire". ++ // It will contain at minimum the VMBUS_CHANNEL_MESSAGE_HEADER header ++ unsigned char Msg[0]; ++} VMBUS_CHANNEL_MSGINFO; ++ ++ ++// ++// Routines ++// ++ ++INTERNAL VMBUS_CHANNEL* ++AllocVmbusChannel( ++ void ++ ); ++ ++INTERNAL void ++FreeVmbusChannel( ++ VMBUS_CHANNEL *Channel ++ ); ++ ++INTERNAL void ++VmbusOnChannelMessage( ++ void *Context ++ ); ++ ++INTERNAL int ++VmbusChannelRequestOffers( ++ void ++ ); ++ ++INTERNAL void ++VmbusChannelReleaseUnattachedChannels( ++ void ++ ); ++ ++#endif //_CHANNEL_MGMT_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/Connection.c linux-2.6.27.29-0.1.1/drivers/staging/hv/Connection.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/Connection.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,432 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#include "include/logging.h" ++ ++#include "VmbusPrivate.h" ++ ++// ++// Globals ++// ++ ++ ++VMBUS_CONNECTION gVmbusConnection = { ++ .ConnectState = Disconnected, ++ .NextGpadlHandle = 0xE1E10, ++}; ++ ++ ++/*++ ++ ++Name: ++ VmbusConnect() ++ ++Description: ++ Sends a connect request on the partition service connection ++ ++--*/ ++int ++VmbusConnect( ++ ) ++{ ++ int ret=0; ++ VMBUS_CHANNEL_MSGINFO *msgInfo=NULL; ++ VMBUS_CHANNEL_INITIATE_CONTACT *msg; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ // Make sure we are not connecting or connected ++ if (gVmbusConnection.ConnectState != Disconnected) ++ return -1; ++ ++ // Initialize the vmbus connection ++ gVmbusConnection.ConnectState = Connecting; ++ gVmbusConnection.WorkQueue = WorkQueueCreate("vmbusQ"); ++ ++ INITIALIZE_LIST_HEAD(&gVmbusConnection.ChannelMsgList); ++ gVmbusConnection.ChannelMsgLock = SpinlockCreate(); ++ ++ INITIALIZE_LIST_HEAD(&gVmbusConnection.ChannelList); ++ gVmbusConnection.ChannelLock = SpinlockCreate(); ++ ++ // Setup the vmbus event connection for channel interrupt abstraction stuff ++ gVmbusConnection.InterruptPage = PageAlloc(1); ++ if (gVmbusConnection.InterruptPage == NULL) ++ { ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ gVmbusConnection.RecvInterruptPage = gVmbusConnection.InterruptPage; ++ gVmbusConnection.SendInterruptPage = (void*)((ULONG_PTR)gVmbusConnection.InterruptPage + (PAGE_SIZE >> 1)); ++ ++ // Setup the monitor notification facility. The 1st page for parent->child and the 2nd page for child->parent ++ gVmbusConnection.MonitorPages = PageAlloc(2); ++ if (gVmbusConnection.MonitorPages == NULL) ++ { ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ msgInfo = (VMBUS_CHANNEL_MSGINFO*)MemAllocZeroed(sizeof(VMBUS_CHANNEL_MSGINFO) + sizeof(VMBUS_CHANNEL_INITIATE_CONTACT)); ++ if (msgInfo == NULL) ++ { ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ msgInfo->WaitEvent = WaitEventCreate(); ++ msg = (VMBUS_CHANNEL_INITIATE_CONTACT*)msgInfo->Msg; ++ ++ msg->Header.MessageType = ChannelMessageInitiateContact; ++ msg->VMBusVersionRequested = VMBUS_REVISION_NUMBER; ++ msg->InterruptPage = GetPhysicalAddress(gVmbusConnection.InterruptPage); ++ msg->MonitorPage1 = GetPhysicalAddress(gVmbusConnection.MonitorPages); ++ msg->MonitorPage2 = GetPhysicalAddress((PVOID)((ULONG_PTR)gVmbusConnection.MonitorPages + PAGE_SIZE)); ++ ++ // Add to list before we send the request since we may receive the response ++ // before returning from this routine ++ SpinlockAcquire(gVmbusConnection.ChannelMsgLock); ++ INSERT_TAIL_LIST(&gVmbusConnection.ChannelMsgList, &msgInfo->MsgListEntry); ++ SpinlockRelease(gVmbusConnection.ChannelMsgLock); ++ ++ DPRINT_DBG(VMBUS, "Vmbus connection - interrupt pfn %llx, monitor1 pfn %llx,, monitor2 pfn %llx", ++ msg->InterruptPage, msg->MonitorPage1, msg->MonitorPage2); ++ ++ DPRINT_DBG(VMBUS, "Sending channel initiate msg..."); ++ ++ ret = VmbusPostMessage(msg, sizeof(VMBUS_CHANNEL_INITIATE_CONTACT)); ++ if (ret != 0) ++ { ++ REMOVE_ENTRY_LIST(&msgInfo->MsgListEntry); ++ goto Cleanup; ++ } ++ ++ // Wait for the connection response ++ WaitEventWait(msgInfo->WaitEvent); ++ ++ REMOVE_ENTRY_LIST(&msgInfo->MsgListEntry); ++ ++ // Check if successful ++ if (msgInfo->Response.VersionResponse.VersionSupported) ++ { ++ DPRINT_INFO(VMBUS, "Vmbus connected!!"); ++ gVmbusConnection.ConnectState = Connected; ++ ++ } ++ else ++ { ++ DPRINT_ERR(VMBUS, "Vmbus connection failed!!...current version (%d) not supported", VMBUS_REVISION_NUMBER); ++ ret = -1; ++ ++ goto Cleanup; ++ } ++ ++ ++ WaitEventClose(msgInfo->WaitEvent); ++ MemFree(msgInfo); ++ DPRINT_EXIT(VMBUS); ++ ++ return 0; ++ ++Cleanup: ++ ++ gVmbusConnection.ConnectState = Disconnected; ++ ++ WorkQueueClose(gVmbusConnection.WorkQueue); ++ SpinlockClose(gVmbusConnection.ChannelLock); ++ SpinlockClose(gVmbusConnection.ChannelMsgLock); ++ ++ if (gVmbusConnection.InterruptPage) ++ { ++ PageFree(gVmbusConnection.InterruptPage, 1); ++ gVmbusConnection.InterruptPage = NULL; ++ } ++ ++ if (gVmbusConnection.MonitorPages) ++ { ++ PageFree(gVmbusConnection.MonitorPages, 2); ++ gVmbusConnection.MonitorPages = NULL; ++ } ++ ++ if (msgInfo) ++ { ++ if (msgInfo->WaitEvent) ++ WaitEventClose(msgInfo->WaitEvent); ++ ++ MemFree(msgInfo); ++ } ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusDisconnect() ++ ++Description: ++ Sends a disconnect request on the partition service connection ++ ++--*/ ++int ++VmbusDisconnect( ++ VOID ++ ) ++{ ++ int ret=0; ++ VMBUS_CHANNEL_UNLOAD *msg; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ // Make sure we are connected ++ if (gVmbusConnection.ConnectState != Connected) ++ return -1; ++ ++ msg = MemAllocZeroed(sizeof(VMBUS_CHANNEL_UNLOAD)); ++ ++ msg->MessageType = ChannelMessageUnload; ++ ++ ret = VmbusPostMessage(msg, sizeof(VMBUS_CHANNEL_UNLOAD)); ++ ++ if (ret != 0) ++ { ++ goto Cleanup; ++ } ++ ++ PageFree(gVmbusConnection.InterruptPage, 1); ++ ++ // TODO: iterate thru the msg list and free up ++ ++ SpinlockClose(gVmbusConnection.ChannelMsgLock); ++ ++ WorkQueueClose(gVmbusConnection.WorkQueue); ++ ++ gVmbusConnection.ConnectState = Disconnected; ++ ++ DPRINT_INFO(VMBUS, "Vmbus disconnected!!"); ++ ++Cleanup: ++ if (msg) ++ { ++ MemFree(msg); ++ } ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: ++ GetChannelFromRelId() ++ ++Description: ++ Get the channel object given its child relative id (ie channel id) ++ ++--*/ ++VMBUS_CHANNEL* ++GetChannelFromRelId( ++ UINT32 relId ++ ) ++{ ++ VMBUS_CHANNEL* channel; ++ VMBUS_CHANNEL* foundChannel=NULL; ++ LIST_ENTRY* anchor; ++ LIST_ENTRY* curr; ++ ++ SpinlockAcquire(gVmbusConnection.ChannelLock); ++ ITERATE_LIST_ENTRIES(anchor, curr, &gVmbusConnection.ChannelList) ++ { ++ channel = CONTAINING_RECORD(curr, VMBUS_CHANNEL, ListEntry); ++ ++ if (channel->OfferMsg.ChildRelId == relId) ++ { ++ foundChannel = channel; ++ break; ++ } ++ } ++ SpinlockRelease(gVmbusConnection.ChannelLock); ++ ++ return foundChannel; ++} ++ ++ ++ ++/*++ ++ ++Name: ++ VmbusProcessChannelEvent() ++ ++Description: ++ Process a channel event notification ++ ++--*/ ++static void ++VmbusProcessChannelEvent( ++ PVOID context ++ ) ++{ ++ VMBUS_CHANNEL* channel; ++ UINT32 relId = (UINT32)(ULONG_PTR)context; ++ ++ ASSERT(relId > 0); ++ ++ // Find the channel based on this relid and invokes ++ // the channel callback to process the event ++ channel = GetChannelFromRelId(relId); ++ ++ if (channel) ++ { ++ VmbusChannelOnChannelEvent(channel); ++ //WorkQueueQueueWorkItem(channel->dataWorkQueue, VmbusChannelOnChannelEvent, (void*)channel); ++ } ++ else ++ { ++ DPRINT_ERR(VMBUS, "channel not found for relid - %d.", relId); ++ } ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusOnEvents() ++ ++Description: ++ Handler for events ++ ++--*/ ++VOID ++VmbusOnEvents( ++ VOID ++ ) ++{ ++ int dword; ++ //int maxdword = PAGE_SIZE >> 3; // receive size is 1/2 page and divide that by 4 bytes ++ int maxdword = MAX_NUM_CHANNELS_SUPPORTED >> 5; ++ int bit; ++ int relid; ++ UINT32* recvInterruptPage = gVmbusConnection.RecvInterruptPage; ++ //VMBUS_CHANNEL_MESSAGE* receiveMsg; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ // Check events ++ if (recvInterruptPage) ++ { ++ for (dword = 0; dword < maxdword; dword++) ++ { ++ if (recvInterruptPage[dword]) ++ { ++ for (bit = 0; bit < 32; bit++) ++ { ++ if (BitTestAndClear(&recvInterruptPage[dword], bit)) ++ { ++ relid = (dword << 5) + bit; ++ ++ DPRINT_DBG(VMBUS, "event detected for relid - %d", relid); ++ ++ if (relid == 0) // special case - vmbus channel protocol msg ++ { ++ DPRINT_DBG(VMBUS, "invalid relid - %d", relid); ++ ++ continue; } ++ else ++ { ++ //QueueWorkItem(VmbusProcessEvent, (void*)relid); ++ //ret = WorkQueueQueueWorkItem(gVmbusConnection.workQueue, VmbusProcessChannelEvent, (void*)relid); ++ VmbusProcessChannelEvent((void*)(ULONG_PTR)relid); ++ } ++ } ++ } ++ } ++ } ++ } ++ DPRINT_EXIT(VMBUS); ++ ++ return; ++} ++ ++/*++ ++ ++Name: ++ VmbusPostMessage() ++ ++Description: ++ Send a msg on the vmbus's message connection ++ ++--*/ ++int ++VmbusPostMessage( ++ PVOID buffer, ++ SIZE_T bufferLen ++ ) ++{ ++ int ret=0; ++ HV_CONNECTION_ID connId; ++ ++ ++ connId.AsUINT32 =0; ++ connId.u.Id = VMBUS_MESSAGE_CONNECTION_ID; ++ ret = HvPostMessage( ++ connId, ++ 1, ++ buffer, ++ bufferLen); ++ ++ return ret; ++} ++ ++/*++ ++ ++Name: ++ VmbusSetEvent() ++ ++Description: ++ Send an event notification to the parent ++ ++--*/ ++int ++VmbusSetEvent(UINT32 childRelId) ++{ ++ int ret=0; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ // Each UINT32 represents 32 channels ++ BitSet((UINT32*)gVmbusConnection.SendInterruptPage + (childRelId >> 5), childRelId & 31); ++ ret = HvSignalEvent(); ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++} ++ ++// EOF +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/Hv.c linux-2.6.27.29-0.1.1/drivers/staging/hv/Hv.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/Hv.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,672 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#include "include/logging.h" ++#include "VmbusPrivate.h" ++ ++// ++// Globals ++// ++ ++// The one and only ++HV_CONTEXT gHvContext={ ++ .SynICInitialized = FALSE, ++ .HypercallPage = NULL, ++ .SignalEventParam = NULL, ++ .SignalEventBuffer = NULL, ++}; ++ ++ ++/*++ ++ ++Name: ++ HvQueryHypervisorPresence() ++ ++Description: ++ Query the cpuid for presense of windows hypervisor ++ ++--*/ ++static int ++HvQueryHypervisorPresence ( ++ void ++ ) ++{ ++ unsigned int eax; ++ unsigned int ebx; ++ unsigned int ecx; ++ unsigned int edx; ++ unsigned int op; ++ ++ eax = 0; ++ ebx = 0; ++ ecx = 0; ++ edx = 0; ++ op = HvCpuIdFunctionVersionAndFeatures; ++ do_cpuid(op, &eax, &ebx, &ecx, &edx); ++ ++ return (ecx & HV_PRESENT_BIT); ++} ++ ++ ++/*++ ++ ++Name: ++ HvQueryHypervisorInfo() ++ ++Description: ++ Get version info of the windows hypervisor ++ ++--*/ ++static int ++HvQueryHypervisorInfo ( ++ void ++ ) ++{ ++ unsigned int eax; ++ unsigned int ebx; ++ unsigned int ecx; ++ unsigned int edx; ++ unsigned int maxLeaf; ++ unsigned int op; ++ ++ // ++ // Its assumed that this is called after confirming that Viridian is present. ++ // Query id and revision. ++ // ++ ++ eax = 0; ++ ebx = 0; ++ ecx = 0; ++ edx = 0; ++ op = HvCpuIdFunctionHvVendorAndMaxFunction; ++ do_cpuid(op, &eax, &ebx, &ecx, &edx); ++ ++ DPRINT_INFO(VMBUS, "Vendor ID: %c%c%c%c%c%c%c%c%c%c%c%c", ++ (ebx & 0xFF), ++ ((ebx >> 8) & 0xFF), ++ ((ebx >> 16) & 0xFF), ++ ((ebx >> 24) & 0xFF), ++ (ecx & 0xFF), ++ ((ecx >> 8) & 0xFF), ++ ((ecx >> 16) & 0xFF), ++ ((ecx >> 24) & 0xFF), ++ (edx & 0xFF), ++ ((edx >> 8) & 0xFF), ++ ((edx >> 16) & 0xFF), ++ ((edx >> 24) & 0xFF)); ++ ++ maxLeaf = eax; ++ eax = 0; ++ ebx = 0; ++ ecx = 0; ++ edx = 0; ++ op = HvCpuIdFunctionHvInterface; ++ do_cpuid(op, &eax, &ebx, &ecx, &edx); ++ ++ DPRINT_INFO(VMBUS, "Interface ID: %c%c%c%c", ++ (eax & 0xFF), ++ ((eax >> 8) & 0xFF), ++ ((eax >> 16) & 0xFF), ++ ((eax >> 24) & 0xFF)); ++ ++ if (maxLeaf >= HvCpuIdFunctionMsHvVersion) { ++ eax = 0; ++ ebx = 0; ++ ecx = 0; ++ edx = 0; ++ op = HvCpuIdFunctionMsHvVersion; ++ do_cpuid(op, &eax, &ebx, &ecx, &edx); ++ DPRINT_INFO(VMBUS, "OS Build:%d-%d.%d-%d-%d.%d", ++ eax, ++ ebx >> 16, ++ ebx & 0xFFFF, ++ ecx, ++ edx >> 24, ++ edx & 0xFFFFFF); ++ } ++ return maxLeaf; ++} ++ ++ ++/*++ ++ ++Name: ++ HvDoHypercall() ++ ++Description: ++ Invoke the specified hypercall ++ ++--*/ ++static UINT64 ++HvDoHypercall ( ++ UINT64 Control, ++ void* Input, ++ void* Output ++ ) ++{ ++#ifdef CONFIG_X86_64 ++ UINT64 hvStatus=0; ++ UINT64 inputAddress = (Input)? GetPhysicalAddress(Input) : 0; ++ UINT64 outputAddress = (Output)? GetPhysicalAddress(Output) : 0; ++ volatile void* hypercallPage = gHvContext.HypercallPage; ++ ++ DPRINT_DBG(VMBUS, "Hypercall ", ++ Control, ++ inputAddress, ++ Input, ++ outputAddress, ++ Output, ++ hypercallPage); ++ ++ __asm__ __volatile__ ("mov %0, %%r8" : : "r" (outputAddress): "r8"); ++ __asm__ __volatile__ ("call *%3" : "=a"(hvStatus): "c" (Control), "d" (inputAddress), "m" (hypercallPage)); ++ ++ DPRINT_DBG(VMBUS, "Hypercall ", hvStatus); ++ ++ return hvStatus; ++ ++#else ++ ++ UINT32 controlHi = Control >> 32; ++ UINT32 controlLo = Control & 0xFFFFFFFF; ++ UINT32 hvStatusHi = 1; ++ UINT32 hvStatusLo = 1; ++ UINT64 inputAddress = (Input) ? GetPhysicalAddress(Input) : 0; ++ UINT32 inputAddressHi = inputAddress >> 32; ++ UINT32 inputAddressLo = inputAddress & 0xFFFFFFFF; ++ UINT64 outputAddress = (Output) ?GetPhysicalAddress(Output) : 0; ++ UINT32 outputAddressHi = outputAddress >> 32; ++ UINT32 outputAddressLo = outputAddress & 0xFFFFFFFF; ++ volatile void* hypercallPage = gHvContext.HypercallPage; ++ ++ DPRINT_DBG(VMBUS, "Hypercall ", ++ Control, ++ Input, ++ Output); ++ ++ __asm__ __volatile__ ("call *%8" : "=d"(hvStatusHi), "=a"(hvStatusLo) : "d" (controlHi), "a" (controlLo), "b" (inputAddressHi), "c" (inputAddressLo), "D"(outputAddressHi), "S"(outputAddressLo), "m" (hypercallPage)); ++ ++ ++ DPRINT_DBG(VMBUS, "Hypercall ", hvStatusLo | ((UINT64)hvStatusHi << 32)); ++ ++ return (hvStatusLo | ((UINT64)hvStatusHi << 32)); ++#endif // x86_64 ++} ++ ++/*++ ++ ++Name: ++ HvInit() ++ ++Description: ++ Main initialization routine. This routine must be called ++ before any other routines in here are called ++ ++--*/ ++static int ++HvInit ( ++ void ++ ) ++{ ++ int ret=0; ++ int maxLeaf; ++ HV_X64_MSR_HYPERCALL_CONTENTS hypercallMsr; ++ void* virtAddr=0; ++ ULONG_PTR physAddr=0; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ memset(gHvContext.synICEventPage, 0, sizeof(HANDLE)*MAX_NUM_CPUS); ++ memset(gHvContext.synICMessagePage, 0, sizeof(HANDLE)*MAX_NUM_CPUS); ++ ++ if (!HvQueryHypervisorPresence()) ++ { ++ DPRINT_ERR(VMBUS, "No Windows hypervisor detected!!"); ++ goto Cleanup; ++ } ++ ++ DPRINT_INFO(VMBUS, "Windows hypervisor detected! Retrieving more info..."); ++ ++ maxLeaf = HvQueryHypervisorInfo(); ++ //HvQueryHypervisorFeatures(maxLeaf); ++ ++ // Determine if we are running on xenlinux (ie x2v shim) or native linux ++ gHvContext.GuestId = ReadMsr(HV_X64_MSR_GUEST_OS_ID); ++ ++ if (gHvContext.GuestId == 0) ++ { ++ // Write our OS info ++ WriteMsr(HV_X64_MSR_GUEST_OS_ID, HV_LINUX_GUEST_ID); ++ ++ gHvContext.GuestId = HV_LINUX_GUEST_ID; ++ } ++ ++ // See if the hypercall page is already set ++ hypercallMsr.AsUINT64 = ReadMsr(HV_X64_MSR_HYPERCALL); ++ ++ if (gHvContext.GuestId == HV_LINUX_GUEST_ID) ++ { ++ // Allocate the hypercall page memory ++ //virtAddr = PageAlloc(1); ++ virtAddr = VirtualAllocExec(PAGE_SIZE); ++ ++ if (!virtAddr) ++ { ++ DPRINT_ERR(VMBUS, "unable to allocate hypercall page!!"); ++ goto Cleanup; ++ } ++ ++ hypercallMsr.Enable = 1; ++ //hypercallMsr.GuestPhysicalAddress = Logical2PhysicalAddr(virtAddr) >> PAGE_SHIFT; ++ hypercallMsr.GuestPhysicalAddress = Virtual2Physical(virtAddr) >> PAGE_SHIFT; ++ WriteMsr(HV_X64_MSR_HYPERCALL, hypercallMsr.AsUINT64); ++ ++ // Confirm that hypercall page did get setup. ++ hypercallMsr.AsUINT64 = 0; ++ hypercallMsr.AsUINT64 = ReadMsr(HV_X64_MSR_HYPERCALL); ++ ++ if (!hypercallMsr.Enable) ++ { ++ DPRINT_ERR(VMBUS, "unable to set hypercall page!!"); ++ goto Cleanup; ++ } ++ ++ gHvContext.HypercallPage = virtAddr; ++ } ++ else ++ { ++ DPRINT_ERR(VMBUS, "Unknown guest id (0x%llx)!!", gHvContext.GuestId); ++ goto Cleanup; ++ } ++ ++ DPRINT_INFO(VMBUS, "Hypercall page VA=0x%08x, PA=0x%08x", ++ (unsigned long)gHvContext.HypercallPage, ++ (unsigned long)hypercallMsr.GuestPhysicalAddress << PAGE_SHIFT); ++ ++ // Setup the global signal event param for the signal event hypercall ++ gHvContext.SignalEventBuffer = MemAlloc(sizeof(HV_INPUT_SIGNAL_EVENT_BUFFER)); ++ if (!gHvContext.SignalEventBuffer) ++ { ++ goto Cleanup; ++ } ++ ++ gHvContext.SignalEventParam = (PHV_INPUT_SIGNAL_EVENT)(ALIGN_UP((ULONG_PTR)gHvContext.SignalEventBuffer, HV_HYPERCALL_PARAM_ALIGN)); ++ gHvContext.SignalEventParam->ConnectionId.AsUINT32 = 0; ++ gHvContext.SignalEventParam->ConnectionId.u.Id = VMBUS_EVENT_CONNECTION_ID; ++ gHvContext.SignalEventParam->FlagNumber = 0; ++ gHvContext.SignalEventParam->RsvdZ = 0; ++ ++ //DPRINT_DBG(VMBUS, "My id %llu", HvGetCurrentPartitionId()); ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++ ++Cleanup: ++ if (virtAddr) ++ { ++ if (hypercallMsr.Enable) ++ { ++ hypercallMsr.AsUINT64 = 0; ++ WriteMsr(HV_X64_MSR_HYPERCALL, hypercallMsr.AsUINT64); ++ } ++ ++ VirtualFree(virtAddr); ++ } ++ ret = -1; ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: ++ HvCleanup() ++ ++Description: ++ Cleanup routine. This routine is called normally during driver unloading or exiting. ++ ++--*/ ++void ++HvCleanup ( ++ void ++ ) ++{ ++ HV_X64_MSR_HYPERCALL_CONTENTS hypercallMsr; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ if (gHvContext.SignalEventBuffer) ++ { ++ MemFree(gHvContext.SignalEventBuffer); ++ gHvContext.SignalEventBuffer = NULL; ++ gHvContext.SignalEventParam = NULL; ++ } ++ ++ if (gHvContext.GuestId == HV_LINUX_GUEST_ID) ++ { ++ if (gHvContext.HypercallPage) ++ { ++ hypercallMsr.AsUINT64 = 0; ++ WriteMsr(HV_X64_MSR_HYPERCALL, hypercallMsr.AsUINT64); ++ VirtualFree(gHvContext.HypercallPage); ++ gHvContext.HypercallPage = NULL; ++ } ++ } ++ ++ DPRINT_EXIT(VMBUS); ++ ++} ++ ++ ++/*++ ++ ++Name: ++ HvPostMessage() ++ ++Description: ++ Post a message using the hypervisor message IPC. This ++ involves a hypercall. ++ ++--*/ ++HV_STATUS ++HvPostMessage( ++ HV_CONNECTION_ID connectionId, ++ HV_MESSAGE_TYPE messageType, ++ PVOID payload, ++ SIZE_T payloadSize ++ ) ++{ ++ struct alignedInput { ++ UINT64 alignment8; ++ HV_INPUT_POST_MESSAGE msg; ++ }; ++ ++ PHV_INPUT_POST_MESSAGE alignedMsg; ++ HV_STATUS status; ++ ULONG_PTR addr; ++ ++ if (payloadSize > HV_MESSAGE_PAYLOAD_BYTE_COUNT) ++ { ++ return -1; ++ } ++ ++ addr = (ULONG_PTR)MemAllocAtomic(sizeof(struct alignedInput)); ++ ++ if (!addr) ++ { ++ return -1; ++ } ++ ++ alignedMsg = (PHV_INPUT_POST_MESSAGE)(ALIGN_UP(addr, HV_HYPERCALL_PARAM_ALIGN)); ++ ++ alignedMsg->ConnectionId = connectionId; ++ alignedMsg->MessageType = messageType; ++ alignedMsg->PayloadSize = payloadSize; ++ memcpy((void*)alignedMsg->Payload, payload, payloadSize); ++ ++ status = HvDoHypercall(HvCallPostMessage, alignedMsg, 0) & 0xFFFF; ++ ++ MemFree((void*)addr); ++ ++ return status; ++} ++ ++ ++/*++ ++ ++Name: ++ HvSignalEvent() ++ ++Description: ++ Signal an event on the specified connection using the hypervisor event IPC. This ++ involves a hypercall. ++ ++--*/ ++HV_STATUS ++HvSignalEvent( ++ ) ++{ ++ HV_STATUS status; ++ ++ status = HvDoHypercall(HvCallSignalEvent, gHvContext.SignalEventParam, 0) & 0xFFFF; ++ ++ return status; ++} ++ ++ ++/*++ ++ ++Name: ++ HvSynicInit() ++ ++Description: ++ Initialize the Synthethic Interrupt Controller. If it is already initialized by ++ another entity (ie x2v shim), we need to retrieve the initialized message and event pages. ++ Otherwise, we create and initialize the message and event pages. ++ ++--*/ ++int ++HvSynicInit ( ++ UINT32 irqVector ++ ) ++{ ++ UINT64 version; ++ HV_SYNIC_SIMP simp; ++ HV_SYNIC_SIEFP siefp; ++ HV_SYNIC_SINT sharedSint; ++ HV_SYNIC_SCONTROL sctrl; ++ UINT64 guestID; ++ int ret=0; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ if (!gHvContext.HypercallPage) ++ { ++ DPRINT_EXIT(VMBUS); ++ return ret; ++ } ++ ++ // Check the version ++ version = ReadMsr(HV_X64_MSR_SVERSION); ++ ++ DPRINT_INFO(VMBUS, "SynIC version: %llx", version); ++ ++ // TODO: Handle SMP ++ if (gHvContext.GuestId == HV_XENLINUX_GUEST_ID) ++ { ++ DPRINT_INFO(VMBUS, "Skipping SIMP and SIEFP setup since it is already set."); ++ ++ simp.AsUINT64 = ReadMsr(HV_X64_MSR_SIMP); ++ siefp.AsUINT64 = ReadMsr(HV_X64_MSR_SIEFP); ++ ++ DPRINT_DBG(VMBUS, "Simp: %llx, Sifep: %llx", simp.AsUINT64, siefp.AsUINT64); ++ ++ // Determine if we are running on xenlinux (ie x2v shim) or native linux ++ guestID = ReadMsr(HV_X64_MSR_GUEST_OS_ID); ++ ++ if (guestID == HV_LINUX_GUEST_ID) ++ { ++ gHvContext.synICMessagePage[0] = GetVirtualAddress(simp.BaseSimpGpa << PAGE_SHIFT); ++ gHvContext.synICEventPage[0] = GetVirtualAddress(siefp.BaseSiefpGpa << PAGE_SHIFT); ++ } ++ else ++ { ++ DPRINT_ERR(VMBUS, "unknown guest id!!"); ++ goto Cleanup; ++ } ++ DPRINT_DBG(VMBUS, "MAPPED: Simp: %p, Sifep: %p", gHvContext.synICMessagePage[0], gHvContext.synICEventPage[0]); ++ } ++ else ++ { ++ gHvContext.synICMessagePage[0] = PageAlloc(1); ++ if (gHvContext.synICMessagePage[0] == NULL) ++ { ++ DPRINT_ERR(VMBUS, "unable to allocate SYNIC message page!!"); ++ goto Cleanup; ++ } ++ ++ gHvContext.synICEventPage[0] = PageAlloc(1); ++ if (gHvContext.synICEventPage[0] == NULL) ++ { ++ DPRINT_ERR(VMBUS, "unable to allocate SYNIC event page!!"); ++ goto Cleanup; ++ } ++ ++ // ++ // Setup the Synic's message page ++ // ++ simp.AsUINT64 = ReadMsr(HV_X64_MSR_SIMP); ++ simp.SimpEnabled = 1; ++ simp.BaseSimpGpa = GetPhysicalAddress(gHvContext.synICMessagePage[0]) >> PAGE_SHIFT; ++ ++ DPRINT_DBG(VMBUS, "HV_X64_MSR_SIMP msr set to: %llx", simp.AsUINT64); ++ ++ WriteMsr(HV_X64_MSR_SIMP, simp.AsUINT64); ++ ++ // ++ // Setup the Synic's event page ++ // ++ siefp.AsUINT64 = ReadMsr(HV_X64_MSR_SIEFP); ++ siefp.SiefpEnabled = 1; ++ siefp.BaseSiefpGpa = GetPhysicalAddress(gHvContext.synICEventPage[0]) >> PAGE_SHIFT; ++ ++ DPRINT_DBG(VMBUS, "HV_X64_MSR_SIEFP msr set to: %llx", siefp.AsUINT64); ++ ++ WriteMsr(HV_X64_MSR_SIEFP, siefp.AsUINT64); ++ } ++ // ++ // Setup the interception SINT. ++ // ++ //WriteMsr((HV_X64_MSR_SINT0 + HV_SYNIC_INTERCEPTION_SINT_INDEX), ++ // interceptionSint.AsUINT64); ++ ++ // ++ // Setup the shared SINT. ++ // ++ sharedSint.AsUINT64 = ReadMsr(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT); ++ ++ sharedSint.AsUINT64 = 0; ++ sharedSint.Vector = irqVector; //HV_SHARED_SINT_IDT_VECTOR + 0x20; ++ sharedSint.Masked = FALSE; ++ sharedSint.AutoEoi = TRUE; ++ ++ DPRINT_DBG(VMBUS, "HV_X64_MSR_SINT1 msr set to: %llx", sharedSint.AsUINT64); ++ ++ WriteMsr(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, sharedSint.AsUINT64); ++ ++ // Enable the global synic bit ++ sctrl.AsUINT64 = ReadMsr(HV_X64_MSR_SCONTROL); ++ sctrl.Enable = 1; ++ ++ WriteMsr(HV_X64_MSR_SCONTROL, sctrl.AsUINT64); ++ ++ gHvContext.SynICInitialized = TRUE; ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++ ++Cleanup: ++ ret = -1; ++ ++ if (gHvContext.GuestId == HV_LINUX_GUEST_ID) ++ { ++ if (gHvContext.synICEventPage[0]) ++ { ++ PageFree(gHvContext.synICEventPage[0],1); ++ } ++ ++ if (gHvContext.synICMessagePage[0]) ++ { ++ PageFree(gHvContext.synICMessagePage[0], 1); ++ } ++ } ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++ ++} ++ ++/*++ ++ ++Name: ++ HvSynicCleanup() ++ ++Description: ++ Cleanup routine for HvSynicInit(). ++ ++--*/ ++VOID ++HvSynicCleanup( ++ VOID ++ ) ++{ ++ HV_SYNIC_SINT sharedSint; ++ HV_SYNIC_SIMP simp; ++ HV_SYNIC_SIEFP siefp; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ if (!gHvContext.SynICInitialized) ++ { ++ DPRINT_EXIT(VMBUS); ++ return; ++ } ++ ++ sharedSint.AsUINT64 = ReadMsr(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT); ++ ++ sharedSint.Masked = 1; ++ ++ // Disable the interrupt ++ WriteMsr(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, sharedSint.AsUINT64); ++ ++ // Disable and free the resources only if we are running as native linux ++ // since in xenlinux, we are sharing the resources with the x2v shim ++ if (gHvContext.GuestId == HV_LINUX_GUEST_ID) ++ { ++ simp.AsUINT64 = ReadMsr(HV_X64_MSR_SIMP); ++ simp.SimpEnabled = 0; ++ simp.BaseSimpGpa = 0; ++ ++ WriteMsr(HV_X64_MSR_SIMP, simp.AsUINT64); ++ ++ siefp.AsUINT64 = ReadMsr(HV_X64_MSR_SIEFP); ++ siefp.SiefpEnabled = 0; ++ siefp.BaseSiefpGpa = 0; ++ ++ WriteMsr(HV_X64_MSR_SIEFP, siefp.AsUINT64); ++ ++ PageFree(gHvContext.synICMessagePage[0], 1); ++ PageFree(gHvContext.synICEventPage[0], 1); ++ } ++ ++ DPRINT_EXIT(VMBUS); ++} ++ ++ ++// eof +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/Hv.h linux-2.6.27.29-0.1.1/drivers/staging/hv/Hv.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/Hv.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,184 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef __HV_H__ ++#define __HV_H__ ++ ++#include "include/osd.h" ++ ++#include "include/HvTypes.h" ++#include "include/HvStatus.h" ++//#include "HvVmApi.h" ++//#include "HvKeApi.h" ++//#include "HvMmApi.h" ++//#include "HvCpuApi.h" ++#include "include/HvHalApi.h" ++#include "include/HvVpApi.h" ++//#include "HvTrApi.h" ++#include "include/HvSynicApi.h" ++//#include "HvAmApi.h" ++//#include "HvHkApi.h" ++//#include "HvValApi.h" ++#include "include/HvHcApi.h" ++#include "include/HvPtApi.h" ++ ++enum ++{ ++ VMBUS_MESSAGE_CONNECTION_ID = 1, ++ VMBUS_MESSAGE_PORT_ID = 1, ++ VMBUS_EVENT_CONNECTION_ID = 2, ++ VMBUS_EVENT_PORT_ID = 2, ++ VMBUS_MONITOR_CONNECTION_ID = 3, ++ VMBUS_MONITOR_PORT_ID = 3, ++ VMBUS_MESSAGE_SINT = 2 ++}; ++// ++// #defines ++// ++#define HV_PRESENT_BIT 0x80000000 ++ ++#define HV_XENLINUX_GUEST_ID_LO 0x00000000 ++#define HV_XENLINUX_GUEST_ID_HI 0x0B00B135 ++#define HV_XENLINUX_GUEST_ID (((UINT64)HV_XENLINUX_GUEST_ID_HI << 32) | HV_XENLINUX_GUEST_ID_LO) ++ ++#define HV_LINUX_GUEST_ID_LO 0x00000000 ++#define HV_LINUX_GUEST_ID_HI 0xB16B00B5 ++#define HV_LINUX_GUEST_ID (((UINT64)HV_LINUX_GUEST_ID_HI << 32) | HV_LINUX_GUEST_ID_LO) ++ ++#define HV_CPU_POWER_MANAGEMENT (1 << 0) ++#define HV_RECOMMENDATIONS_MAX 4 ++ ++#define HV_X64_MAX 5 ++#define HV_CAPS_MAX 8 ++ ++ ++#define HV_HYPERCALL_PARAM_ALIGN sizeof(UINT64) ++ ++// ++// Service definitions ++// ++#define HV_SERVICE_PARENT_PORT (0) ++#define HV_SERVICE_PARENT_CONNECTION (0) ++ ++#define HV_SERVICE_CONNECT_RESPONSE_SUCCESS (0) ++#define HV_SERVICE_CONNECT_RESPONSE_INVALID_PARAMETER (1) ++#define HV_SERVICE_CONNECT_RESPONSE_UNKNOWN_SERVICE (2) ++#define HV_SERVICE_CONNECT_RESPONSE_CONNECTION_REJECTED (3) ++ ++#define HV_SERVICE_CONNECT_REQUEST_MESSAGE_ID (1) ++#define HV_SERVICE_CONNECT_RESPONSE_MESSAGE_ID (2) ++#define HV_SERVICE_DISCONNECT_REQUEST_MESSAGE_ID (3) ++#define HV_SERVICE_DISCONNECT_RESPONSE_MESSAGE_ID (4) ++#define HV_SERVICE_MAX_MESSAGE_ID (4) ++ ++#define HV_SERVICE_PROTOCOL_VERSION (0x0010) ++#define HV_CONNECT_PAYLOAD_BYTE_COUNT 64 ++ ++//#define VMBUS_REVISION_NUMBER 6 ++//#define VMBUS_PORT_ID 11 // Our local vmbus's port and connection id. Anything >0 is fine ++ ++// 628180B8-308D-4c5e-B7DB-1BEB62E62EF4 ++static const GUID VMBUS_SERVICE_ID = {.Data = {0xb8, 0x80, 0x81, 0x62, 0x8d, 0x30, 0x5e, 0x4c, 0xb7, 0xdb, 0x1b, 0xeb, 0x62, 0xe6, 0x2e, 0xf4} }; ++ ++#define MAX_NUM_CPUS 1 ++ ++ ++typedef struct { ++ UINT64 Align8; ++ HV_INPUT_SIGNAL_EVENT Event; ++} HV_INPUT_SIGNAL_EVENT_BUFFER; ++ ++typedef struct { ++ UINT64 GuestId; // XenLinux or native Linux. If XenLinux, the hypercall and synic pages has already been initialized ++ void* HypercallPage; ++ ++ BOOL SynICInitialized; ++ // This is used as an input param to HvCallSignalEvent hypercall. The input param is immutable ++ // in our usage and must be dynamic mem (vs stack or global). ++ HV_INPUT_SIGNAL_EVENT_BUFFER *SignalEventBuffer; ++ HV_INPUT_SIGNAL_EVENT *SignalEventParam; // 8-bytes aligned of the buffer above ++ ++ HANDLE synICMessagePage[MAX_NUM_CPUS]; ++ HANDLE synICEventPage[MAX_NUM_CPUS]; ++} HV_CONTEXT; ++ ++extern HV_CONTEXT gHvContext; ++ ++ ++// ++// Inline routines ++// ++static inline unsigned long long ReadMsr(int msr) ++{ ++ unsigned long long val; ++ ++ RDMSR(msr, val); ++ ++ return val; ++} ++ ++static inline void WriteMsr(int msr, UINT64 val) ++{ ++ WRMSR(msr, val); ++ ++ return; ++} ++ ++// ++// Hv Interface ++// ++INTERNAL int ++HvInit( ++ VOID ++ ); ++ ++INTERNAL VOID ++HvCleanup( ++ VOID ++ ); ++ ++INTERNAL HV_STATUS ++HvPostMessage( ++ HV_CONNECTION_ID connectionId, ++ HV_MESSAGE_TYPE messageType, ++ PVOID payload, ++ SIZE_T payloadSize ++ ); ++ ++INTERNAL HV_STATUS ++HvSignalEvent( ++ VOID ++ ); ++ ++INTERNAL int ++HvSynicInit( ++ UINT32 irqVector ++ ); ++ ++INTERNAL VOID ++HvSynicCleanup( ++ VOID ++ ); ++ ++#endif // __HV_H__ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/ChannelMessages.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/ChannelMessages.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/ChannelMessages.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,312 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#pragma once ++ ++#include "VmbusPacketFormat.h" ++ ++#define C_ASSERT(x) ++typedef UINT32 NTSTATUS; ++ ++#pragma pack(push,1) ++ ++// ++// Version 1 messages ++// ++ ++typedef enum _VMBUS_CHANNEL_MESSAGE_TYPE ++{ ++ ChannelMessageInvalid = 0, ++ ChannelMessageOfferChannel = 1, ++ ChannelMessageRescindChannelOffer = 2, ++ ChannelMessageRequestOffers = 3, ++ ChannelMessageAllOffersDelivered = 4, ++ ChannelMessageOpenChannel = 5, ++ ChannelMessageOpenChannelResult = 6, ++ ChannelMessageCloseChannel = 7, ++ ChannelMessageGpadlHeader = 8, ++ ChannelMessageGpadlBody = 9, ++ ChannelMessageGpadlCreated = 10, ++ ChannelMessageGpadlTeardown = 11, ++ ChannelMessageGpadlTorndown = 12, ++ ChannelMessageRelIdReleased = 13, ++ ChannelMessageInitiateContact = 14, ++ ChannelMessageVersionResponse = 15, ++ ChannelMessageUnload = 16, ++#ifdef VMBUS_FEATURE_PARENT_OR_PEER_MEMORY_MAPPED_INTO_A_CHILD ++ ChannelMessageViewRangeAdd = 17, ++ ChannelMessageViewRangeRemove = 18, ++#endif ++ ChannelMessageCount ++} VMBUS_CHANNEL_MESSAGE_TYPE, *PVMBUS_CHANNEL_MESSAGE_TYPE; ++ ++// begin_wpp config ++// CUSTOM_TYPE(ChannelMessageType, ItemEnum(_VMBUS_CHANNEL_MESSAGE_TYPE)); ++// end_wpp ++ ++typedef struct _VMBUS_CHANNEL_MESSAGE_HEADER ++{ ++ VMBUS_CHANNEL_MESSAGE_TYPE MessageType; ++ UINT32 Padding; ++} VMBUS_CHANNEL_MESSAGE_HEADER, *PVMBUS_CHANNEL_MESSAGE_HEADER; ++ ++// Query VMBus Version parameters ++typedef struct _VMBUS_CHANNEL_QUERY_VMBUS_VERSION ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ UINT32 Version; ++} VMBUS_CHANNEL_QUERY_VMBUS_VERSION, *PVMBUS_CHANNEL_QUERY_VMBUS_VERSION; ++ ++// VMBus Version Supported parameters ++typedef struct _VMBUS_CHANNEL_VERSION_SUPPORTED ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ BOOLEAN VersionSupported; ++} VMBUS_CHANNEL_VERSION_SUPPORTED, *PVMBUS_CHANNEL_VERSION_SUPPORTED; ++ ++// Offer Channel parameters ++typedef struct _VMBUS_CHANNEL_OFFER_CHANNEL ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ VMBUS_CHANNEL_OFFER Offer; ++ UINT32 ChildRelId; ++ UINT8 MonitorId; ++ BOOLEAN MonitorAllocated; ++} VMBUS_CHANNEL_OFFER_CHANNEL, *PVMBUS_CHANNEL_OFFER_CHANNEL; ++ ++// ++// Make sure VMBUS_CHANNEL_OFFER_CHANNEL fits into Synic message. ++// ++C_ASSERT(sizeof(VMBUS_CHANNEL_OFFER_CHANNEL) <= MAXIMUM_SYNIC_MESSAGE_BYTES); ++ ++// Rescind Offer parameters ++typedef struct _VMBUS_CHANNEL_RESCIND_OFFER ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ UINT32 ChildRelId; ++} VMBUS_CHANNEL_RESCIND_OFFER, *PVMBUS_CHANNEL_RESCIND_OFFER; ++ ++// Request Offer -- no parameters, SynIC message contains the partition ID ++// Set Snoop -- no parameters, SynIC message contains the partition ID ++// Clear Snoop -- no parameters, SynIC message contains the partition ID ++// All Offers Delivered -- no parameters, SynIC message contains the partition ID ++// Flush Client -- no parameters, SynIC message contains the partition ID ++ ++// Open Channel parameters ++typedef struct _VMBUS_CHANNEL_OPEN_CHANNEL ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ ++ // ++ // Identifies the specific VMBus channel that is being opened. ++ // ++ UINT32 ChildRelId; ++ ++ // ++ // ID making a particular open request at a channel offer unique. ++ // ++ UINT32 OpenId; ++ ++ // ++ // GPADL for the channel's ring buffer. ++ // ++ GPADL_HANDLE RingBufferGpadlHandle; ++ ++ // ++ // GPADL for the channel's server context save area. ++ // ++ GPADL_HANDLE ServerContextAreaGpadlHandle; ++ ++ // ++ // The upstream ring buffer begins at offset zero in the memory described ++ // by RingBufferGpadlHandle. The downstream ring buffer follows it at this ++ // offset (in pages). ++ // ++ UINT32 DownstreamRingBufferPageOffset; ++ ++ // ++ // User-specific data to be passed along to the server endpoint. ++ // ++ UCHAR UserData[MAX_USER_DEFINED_BYTES]; ++ ++} VMBUS_CHANNEL_OPEN_CHANNEL, *PVMBUS_CHANNEL_OPEN_CHANNEL; ++ ++// Reopen Channel parameters; ++typedef VMBUS_CHANNEL_OPEN_CHANNEL VMBUS_CHANNEL_REOPEN_CHANNEL, *PVMBUS_CHANNEL_REOPEN_CHANNEL; ++ ++// Open Channel Result parameters ++typedef struct _VMBUS_CHANNEL_OPEN_RESULT ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ UINT32 ChildRelId; ++ UINT32 OpenId; ++ NTSTATUS Status; ++} VMBUS_CHANNEL_OPEN_RESULT, *PVMBUS_CHANNEL_OPEN_RESULT; ++ ++// Close channel parameters; ++typedef struct _VMBUS_CHANNEL_CLOSE_CHANNEL ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ UINT32 ChildRelId; ++} VMBUS_CHANNEL_CLOSE_CHANNEL, *PVMBUS_CHANNEL_CLOSE_CHANNEL; ++ ++// Channel Message GPADL ++#define GPADL_TYPE_RING_BUFFER 1 ++#define GPADL_TYPE_SERVER_SAVE_AREA 2 ++#define GPADL_TYPE_TRANSACTION 8 ++ ++// ++// The number of PFNs in a GPADL message is defined by the number of pages ++// that would be spanned by ByteCount and ByteOffset. If the implied number ++// of PFNs won't fit in this packet, there will be a follow-up packet that ++// contains more. ++// ++ ++typedef struct _VMBUS_CHANNEL_GPADL_HEADER ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ UINT32 ChildRelId; ++ UINT32 Gpadl; ++ UINT16 RangeBufLen; ++ UINT16 RangeCount; ++ GPA_RANGE Range[0]; ++} VMBUS_CHANNEL_GPADL_HEADER, *PVMBUS_CHANNEL_GPADL_HEADER; ++ ++ ++// ++// This is the followup packet that contains more PFNs. ++// ++ ++typedef struct _VMBUS_CHANNEL_GPADL_BODY ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ UINT32 MessageNumber; ++ UINT32 Gpadl; ++ UINT64 Pfn[0]; ++} VMBUS_CHANNEL_GPADL_BODY, *PVMBUS_CHANNEL_GPADL_BODY; ++ ++ ++typedef struct _VMBUS_CHANNEL_GPADL_CREATED ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ UINT32 ChildRelId; ++ UINT32 Gpadl; ++ UINT32 CreationStatus; ++} VMBUS_CHANNEL_GPADL_CREATED, *PVMBUS_CHANNEL_GPADL_CREATED; ++ ++typedef struct _VMBUS_CHANNEL_GPADL_TEARDOWN ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ UINT32 ChildRelId; ++ UINT32 Gpadl; ++} VMBUS_CHANNEL_GPADL_TEARDOWN, *PVMBUS_CHANNEL_GPADL_TEARDOWN; ++ ++typedef struct _VMBUS_CHANNEL_GPADL_TORNDOWN ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ UINT32 Gpadl; ++} VMBUS_CHANNEL_GPADL_TORNDOWN, *PVMBUS_CHANNEL_GPADL_TORNDOWN; ++ ++#ifdef VMBUS_FEATURE_PARENT_OR_PEER_MEMORY_MAPPED_INTO_A_CHILD ++typedef struct _VMBUS_CHANNEL_VIEW_RANGE_ADD ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ PHYSICAL_ADDRESS ViewRangeBase; ++ UINT64 ViewRangeLength; ++ UINT32 ChildRelId; ++} VMBUS_CHANNEL_VIEW_RANGE_ADD, *PVMBUS_CHANNEL_VIEW_RANGE_ADD; ++ ++typedef struct _VMBUS_CHANNEL_VIEW_RANGE_REMOVE ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ PHYSICAL_ADDRESS ViewRangeBase; ++ UINT32 ChildRelId; ++} VMBUS_CHANNEL_VIEW_RANGE_REMOVE, *PVMBUS_CHANNEL_VIEW_RANGE_REMOVE; ++#endif ++ ++typedef struct _VMBUS_CHANNEL_RELID_RELEASED ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ UINT32 ChildRelId; ++} VMBUS_CHANNEL_RELID_RELEASED, *PVMBUS_CHANNEL_RELID_RELEASED; ++ ++typedef struct _VMBUS_CHANNEL_INITIATE_CONTACT ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ UINT32 VMBusVersionRequested; ++ UINT32 Padding2; ++ UINT64 InterruptPage; ++ UINT64 MonitorPage1; ++ UINT64 MonitorPage2; ++} VMBUS_CHANNEL_INITIATE_CONTACT, *PVMBUS_CHANNEL_INITIATE_CONTACT; ++ ++typedef struct _VMBUS_CHANNEL_VERSION_RESPONSE ++{ ++ VMBUS_CHANNEL_MESSAGE_HEADER Header; ++ BOOLEAN VersionSupported; ++} VMBUS_CHANNEL_VERSION_RESPONSE, *PVMBUS_CHANNEL_VERSION_RESPONSE; ++ ++typedef VMBUS_CHANNEL_MESSAGE_HEADER VMBUS_CHANNEL_UNLOAD, *PVMBUS_CHANNEL_UNLOAD; ++ ++// ++// Kind of a table to use the preprocessor to get us the right type for a ++// specified message ID. Used with ChAllocateSendMessage() ++// ++#define ChannelMessageQueryVmbusVersion_TYPE VMBUS_CHANNEL_MESSAGE_HEADER ++#define ChannelMessageVmbusVersionSupported_TYPE VMBUS_CHANNEL_VERSION_SUPPORTED ++#define ChannelMessageOfferChannel_TYPE VMBUS_CHANNEL_OFFER_CHANNEL ++#define ChannelMessageRescindChannelOffer_TYPE VMBUS_CHANNEL_RESCIND_OFFER ++#define ChannelMessageRequestOffers_TYPE VMBUS_CHANNEL_MESSAGE_HEADER ++#define ChannelMessageAllOffersDelivered_TYPE VMBUS_CHANNEL_MESSAGE_HEADER ++#define ChannelMessageOpenChannel_TYPE VMBUS_CHANNEL_OPEN_CHANNEL ++#define ChannelMessageOpenChannelResult_TYPE VMBUS_CHANNEL_OPEN_RESULT ++#define ChannelMessageCloseChannel_TYPE VMBUS_CHANNEL_CLOSE_CHANNEL ++#define ChannelMessageAllGpadlsUnmapped_TYPE VMBUS_CHANNEL_CLOSE_CHANNEL ++#define ChannelMessageGpadlHeader_TYPE VMBUS_CHANNEL_GPADL_HEADER ++#define ChannelMessageGpadlBody_TYPE VMBUS_CHANNEL_GPADL_BODY ++#define ChannelMessageGpadlCreated_TYPE VMBUS_CHANNEL_GPADL_CREATED ++#define ChannelMessageGpadlTeardown_TYPE VMBUS_CHANNEL_GPADL_TEARDOWN ++#define ChannelMessageGpadlTorndown_TYPE VMBUS_CHANNEL_GPADL_TORNDOWN ++#define ChannelMessageViewRangeAdd_TYPE VMBUS_CHANNEL_VIEW_RANGE_ADD ++#define ChannelMessageViewRangeRemove_TYPE VMBUS_CHANNEL_VIEW_RANGE_REMOVE ++#define ChannelMessageRelIdReleased_TYPE VMBUS_CHANNEL_RELID_RELEASED ++#define ChannelMessageInitiateContact_TYPE VMBUS_CHANNEL_INITIATE_CONTACT ++#define ChannelMessageVersionResponse_TYPE VMBUS_CHANNEL_VERSION_RESPONSE ++#define ChannelMessageUnload_TYPE VMBUS_CHANNEL_UNLOAD ++ ++// ++// Preprocessor wrapper to ChAllocateSendMessageSize() converting the return ++// value to the correct pointer and calculate the needed size. ++// ++// Argument: ++// ++// Id - the numberic ID (type VMBUS_CHANNEL_MESSAGE_TYPE) of the message to ++// send. ++// ++#define ChAllocateSendMessage(Id, Fn, Context) \ ++ (Id##_TYPE*)ChAllocateSendMessageSized(sizeof(Id##_TYPE), Id, Fn, Context) ++ ++ ++#pragma pack(pop) ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/HvHalApi.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvHalApi.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvHalApi.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,32 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#pragma once ++ ++ ++// ++// Time in the hypervisor is measured in 100 nanosecond units ++// ++typedef UINT64 HV_NANO100_TIME, *PHV_NANO100_TIME; ++typedef UINT64 HV_NANO100_DURATION, *PHV_NANO100_DURATION; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/HvHcApi.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvHcApi.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvHcApi.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,60 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#pragma once ++ ++// ++// Declare the various hypercall operations. ++// ++typedef enum _HV_CALL_CODE ++{ ++ ++ HvCallPostMessage = 0x005c, ++ HvCallSignalEvent = 0x005d, ++ ++} HV_CALL_CODE, *PHV_CALL_CODE; ++// ++// Definition of the HvPostMessage hypercall input structure. ++// ++ ++typedef struct _HV_INPUT_POST_MESSAGE ++{ ++ HV_CONNECTION_ID ConnectionId; ++ UINT32 Reserved; ++ HV_MESSAGE_TYPE MessageType; ++ UINT32 PayloadSize; ++ UINT64 Payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; ++} HV_INPUT_POST_MESSAGE, *PHV_INPUT_POST_MESSAGE; ++ ++ ++// ++// Definition of the HvSignalEvent hypercall input structure. ++// ++ ++typedef struct _HV_INPUT_SIGNAL_EVENT ++{ ++ HV_CONNECTION_ID ConnectionId; ++ UINT16 FlagNumber; ++ UINT16 RsvdZ; ++} HV_INPUT_SIGNAL_EVENT, *PHV_INPUT_SIGNAL_EVENT; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/HvPtApi.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvPtApi.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvPtApi.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,86 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#pragma once ++ ++// ++// Versioning definitions used for guests reporting themselves to the ++// hypervisor, and visa versa. ++// ================================================================== ++// ++ ++// ++// Version info reported by guest OS's ++// ++typedef enum _HV_GUEST_OS_VENDOR ++{ ++ HvGuestOsVendorMicrosoft = 0x0001 ++ ++} HV_GUEST_OS_VENDOR, *PHV_GUEST_OS_VENDOR; ++ ++typedef enum _HV_GUEST_OS_MICROSOFT_IDS ++{ ++ HvGuestOsMicrosoftUndefined = 0x00, ++ HvGuestOsMicrosoftMSDOS = 0x01, ++ HvGuestOsMicrosoftWindows3x = 0x02, ++ HvGuestOsMicrosoftWindows9x = 0x03, ++ HvGuestOsMicrosoftWindowsNT = 0x04, ++ HvGuestOsMicrosoftWindowsCE = 0x05 ++ ++} HV_GUEST_OS_MICROSOFT_IDS, *PHV_GUEST_OS_MICROSOFT_IDS; ++ ++// ++// Declare the MSR used to identify the guest OS. ++// ++#define HV_X64_MSR_GUEST_OS_ID 0x40000000 ++ ++typedef union _HV_X64_MSR_GUEST_OS_ID_CONTENTS ++{ ++ UINT64 AsUINT64; ++ struct ++ { ++ UINT64 BuildNumber : 16; ++ UINT64 ServiceVersion : 8; // Service Pack, etc. ++ UINT64 MinorVersion : 8; ++ UINT64 MajorVersion : 8; ++ UINT64 OsId : 8; // HV_GUEST_OS_MICROSOFT_IDS (If Vendor=MS) ++ UINT64 VendorId : 16; // HV_GUEST_OS_VENDOR ++ }; ++} HV_X64_MSR_GUEST_OS_ID_CONTENTS, *PHV_X64_MSR_GUEST_OS_ID_CONTENTS; ++ ++// ++// Declare the MSR used to setup pages used to communicate with the hypervisor. ++// ++#define HV_X64_MSR_HYPERCALL 0x40000001 ++ ++typedef union _HV_X64_MSR_HYPERCALL_CONTENTS ++{ ++ UINT64 AsUINT64; ++ struct ++ { ++ UINT64 Enable : 1; ++ UINT64 Reserved : 11; ++ UINT64 GuestPhysicalAddress : 52; ++ }; ++} HV_X64_MSR_HYPERCALL_CONTENTS, *PHV_X64_MSR_HYPERCALL_CONTENTS; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/HvStatus.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvStatus.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvStatus.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,718 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++// begin_hvgdk ++// ++// Status codes for hypervisor operations. ++// ++typedef UINT16 HV_STATUS, *PHV_STATUS; ++ ++// ++// MessageId: HV_STATUS_SUCCESS ++// ++// MessageText: ++// ++// The specified hypercall succeeded ++// ++#define HV_STATUS_SUCCESS ((HV_STATUS)0x0000) ++ ++// ++// MessageId: HV_STATUS_INVALID_HYPERCALL_CODE ++// ++// MessageText: ++// ++// The hypervisor does not support the operation because the specified hypercall code is not supported. ++// ++#define HV_STATUS_INVALID_HYPERCALL_CODE ((HV_STATUS)0x0002) ++ ++// ++// MessageId: HV_STATUS_INVALID_HYPERCALL_INPUT ++// ++// MessageText: ++// ++// The hypervisor does not support the operation because the encoding for the hypercall input register is not supported. ++// ++#define HV_STATUS_INVALID_HYPERCALL_INPUT ((HV_STATUS)0x0003) ++ ++// ++// MessageId: HV_STATUS_INVALID_ALIGNMENT ++// ++// MessageText: ++// ++// The hypervisor could not perform the operation beacuse a parameter has an invalid alignment. ++// ++#define HV_STATUS_INVALID_ALIGNMENT ((HV_STATUS)0x0004) ++ ++// ++// MessageId: HV_STATUS_INVALID_PARAMETER ++// ++// MessageText: ++// ++// The hypervisor could not perform the operation beacuse an invalid parameter was specified. ++// ++#define HV_STATUS_INVALID_PARAMETER ((HV_STATUS)0x0005) ++ ++// ++// MessageId: HV_STATUS_ACCESS_DENIED ++// ++// MessageText: ++// ++// Access to the specified object was denied. ++// ++#define HV_STATUS_ACCESS_DENIED ((HV_STATUS)0x0006) ++ ++// ++// MessageId: HV_STATUS_INVALID_PARTITION_STATE ++// ++// MessageText: ++// ++// The hypervisor could not perform the operation because the partition is entering or in an invalid state. ++// ++#define HV_STATUS_INVALID_PARTITION_STATE ((HV_STATUS)0x0007) ++ ++// ++// MessageId: HV_STATUS_OPERATION_DENIED ++// ++// MessageText: ++// ++// The operation is not allowed in the current state. ++// ++#define HV_STATUS_OPERATION_DENIED ((HV_STATUS)0x0008) ++ ++// ++// MessageId: HV_STATUS_UNKNOWN_PROPERTY ++// ++// MessageText: ++// ++// The hypervisor does not recognize the specified partition property. ++// ++#define HV_STATUS_UNKNOWN_PROPERTY ((HV_STATUS)0x0009) ++ ++// ++// MessageId: HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE ++// ++// MessageText: ++// ++// The specified value of a partition property is out of range or violates an invariant. ++// ++#define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE ((HV_STATUS)0x000A) ++ ++// ++// MessageId: HV_STATUS_INSUFFICIENT_MEMORY ++// ++// MessageText: ++// ++// There is not enough memory in the hypervisor pool to complete the operation. ++// ++#define HV_STATUS_INSUFFICIENT_MEMORY ((HV_STATUS)0x000B) ++ ++// ++// MessageId: HV_STATUS_PARTITION_TOO_DEEP ++// ++// MessageText: ++// ++// The maximum partition depth has been exceeded for the partition hierarchy. ++// ++#define HV_STATUS_PARTITION_TOO_DEEP ((HV_STATUS)0x000C) ++ ++// ++// MessageId: HV_STATUS_INVALID_PARTITION_ID ++// ++// MessageText: ++// ++// A partition with the specified partition Id does not exist. ++// ++#define HV_STATUS_INVALID_PARTITION_ID ((HV_STATUS)0x000D) ++ ++// ++// MessageId: HV_STATUS_INVALID_VP_INDEX ++// ++// MessageText: ++// ++// The hypervisor could not perform the operation because the specified VP index is invalid. ++// ++#define HV_STATUS_INVALID_VP_INDEX ((HV_STATUS)0x000E) ++ ++// ++// MessageId: HV_STATUS_NOT_FOUND ++// ++// MessageText: ++// ++// The iteration is complete; no addition items in the iteration could be found. ++// ++#define HV_STATUS_NOT_FOUND ((HV_STATUS)0x0010) ++ ++// ++// MessageId: HV_STATUS_INVALID_PORT_ID ++// ++// MessageText: ++// ++// The hypervisor could not perform the operation because the specified port identifier is invalid. ++// ++#define HV_STATUS_INVALID_PORT_ID ((HV_STATUS)0x0011) ++ ++// ++// MessageId: HV_STATUS_INVALID_CONNECTION_ID ++// ++// MessageText: ++// ++// The hypervisor could not perform the operation because the specified connection identifier is invalid. ++// ++#define HV_STATUS_INVALID_CONNECTION_ID ((HV_STATUS)0x0012) ++ ++// ++// MessageId: HV_STATUS_INSUFFICIENT_BUFFERS ++// ++// MessageText: ++// ++// You did not supply enough message buffers to send a message. ++// ++#define HV_STATUS_INSUFFICIENT_BUFFERS ((HV_STATUS)0x0013) ++ ++// ++// MessageId: HV_STATUS_NOT_ACKNOWLEDGED ++// ++// MessageText: ++// ++// The previous virtual interrupt has not been acknowledged. ++// ++#define HV_STATUS_NOT_ACKNOWLEDGED ((HV_STATUS)0x0014) ++ ++// ++// MessageId: HV_STATUS_INVALID_VP_STATE ++// ++// MessageText: ++// ++// A virtual processor is not in the correct state for the performance of the indicated operation. ++// ++#define HV_STATUS_INVALID_VP_STATE ((HV_STATUS)0x0015) ++ ++// ++// MessageId: HV_STATUS_ACKNOWLEDGED ++// ++// MessageText: ++// ++// The previous virtual interrupt has already been acknowledged. ++// ++#define HV_STATUS_ACKNOWLEDGED ((HV_STATUS)0x0016) ++ ++// ++// MessageId: HV_STATUS_INVALID_SAVE_RESTORE_STATE ++// ++// MessageText: ++// ++// The indicated partition is not in a valid state for saving or restoring. ++// ++#define HV_STATUS_INVALID_SAVE_RESTORE_STATE ((HV_STATUS)0x0017) ++ ++// ++// MessageId: HV_STATUS_INVALID_SYNIC_STATE ++// ++// MessageText: ++// ++// The hypervisor could not complete the operation because a required feature of the synthetic interrupt controller (SynIC) was disabled. ++// ++#define HV_STATUS_INVALID_SYNIC_STATE ((HV_STATUS)0x0018) ++ ++// ++// MessageId: HV_STATUS_OBJECT_IN_USE ++// ++// MessageText: ++// ++// The hypervisor could not perform the operation because the object or value was either already in use or being used for a purpose that would not permit completing the operation. ++// ++#define HV_STATUS_OBJECT_IN_USE ((HV_STATUS)0x0019) ++ ++// ++// MessageId: HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO ++// ++// MessageText: ++// ++// The proximity domain information is invalid. ++// ++#define HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO ((HV_STATUS)0x001A) ++ ++// ++// MessageId: HV_STATUS_NO_DATA ++// ++// MessageText: ++// ++// An attempt to retrieve debugging data failed because none was available. ++// ++#define HV_STATUS_NO_DATA ((HV_STATUS)0x001B) ++ ++// ++// MessageId: HV_STATUS_INACTIVE ++// ++// MessageText: ++// ++// The physical connection being used for debuggging has not recorded any receive activity since the last operation. ++// ++#define HV_STATUS_INACTIVE ((HV_STATUS)0x001C) ++ ++// ++// MessageId: HV_STATUS_NO_RESOURCES ++// ++// MessageText: ++// ++// There are not enough resources to complete the operation. ++// ++#define HV_STATUS_NO_RESOURCES ((HV_STATUS)0x001D) ++ ++// ++// MessageId: HV_STATUS_FEATURE_UNAVAILABLE ++// ++// MessageText: ++// ++// A hypervisor feature is not available to the user. ++// ++#define HV_STATUS_FEATURE_UNAVAILABLE ((HV_STATUS)0x001E) ++ ++// end_hvgdk ++ ++// ++// MessageId: HV_STATUS_UNSUCCESSFUL ++// ++// MessageText: ++// ++// {Operation Failed} ++// The requested operation was unsuccessful. ++// ++#define HV_STATUS_UNSUCCESSFUL ((HV_STATUS)0x1001) ++ ++// ++// MessageId: HV_STATUS_INSUFFICIENT_BUFFER ++// ++// MessageText: ++// ++// The specified buffer was too small to contain all of the requested data. ++// ++#define HV_STATUS_INSUFFICIENT_BUFFER ((HV_STATUS)0x1002) ++ ++// ++// MessageId: HV_STATUS_GPA_NOT_PRESENT ++// ++// MessageText: ++// ++// The guest physical address is not currently associated with a system physical address. ++// ++#define HV_STATUS_GPA_NOT_PRESENT ((HV_STATUS)0x1003) ++ ++// ++// MessageId: HV_STATUS_GUEST_PAGE_FAULT ++// ++// MessageText: ++// ++// The operation would have resulted in a page fault in the guest. ++// ++#define HV_STATUS_GUEST_PAGE_FAULT ((HV_STATUS)0x1004) ++ ++// ++// MessageId: HV_STATUS_RUNDOWN_DISABLED ++// ++// MessageText: ++// ++// The operation cannot proceed as the rundown object was marked disabled. ++// ++#define HV_STATUS_RUNDOWN_DISABLED ((HV_STATUS)0x1005) ++ ++// ++// MessageId: HV_STATUS_KEY_ALREADY_EXISTS ++// ++// MessageText: ++// ++// The entry cannot be added as another entry with the same key already exists. ++// ++#define HV_STATUS_KEY_ALREADY_EXISTS ((HV_STATUS)0x1006) ++ ++// ++// MessageId: HV_STATUS_GPA_INTERCEPT ++// ++// MessageText: ++// ++// The operation resulted an intercept on a region of guest physical memory. ++// ++#define HV_STATUS_GPA_INTERCEPT ((HV_STATUS)0x1007) ++ ++// ++// MessageId: HV_STATUS_GUEST_GENERAL_PROTECTION_FAULT ++// ++// MessageText: ++// ++// The operation would have resulted in a general protection fault in the guest. ++// ++#define HV_STATUS_GUEST_GENERAL_PROTECTION_FAULT ((HV_STATUS)0x1008) ++ ++// ++// MessageId: HV_STATUS_GUEST_STACK_FAULT ++// ++// MessageText: ++// ++// The operation would have resulted in a stack fault in the guest. ++// ++#define HV_STATUS_GUEST_STACK_FAULT ((HV_STATUS)0x1009) ++ ++// ++// MessageId: HV_STATUS_GUEST_INVALID_OPCODE_FAULT ++// ++// MessageText: ++// ++// The operation would have resulted in an invalid opcode fault in the guest. ++// ++#define HV_STATUS_GUEST_INVALID_OPCODE_FAULT ((HV_STATUS)0x100A) ++ ++// ++// MessageId: HV_STATUS_FINALIZE_INCOMPLETE ++// ++// MessageText: ++// ++// The partition is not completely finalized. ++// ++#define HV_STATUS_FINALIZE_INCOMPLETE ((HV_STATUS)0x100B) ++ ++// ++// MessageId: HV_STATUS_GUEST_MACHINE_CHECK_ABORT ++// ++// MessageText: ++// ++// The operation would have resulted in an machine check abort in the guest. ++// ++#define HV_STATUS_GUEST_MACHINE_CHECK_ABORT ((HV_STATUS)0x100C) ++ ++// ++// MessageId: HV_STATUS_ILLEGAL_OVERLAY_ACCESS ++// ++// MessageText: ++// ++// An illegal access was attempted to an overlay page. ++// ++#define HV_STATUS_ILLEGAL_OVERLAY_ACCESS ((HV_STATUS)0x100D) ++ ++// ++// MessageId: HV_STATUS_INSUFFICIENT_SYSTEM_VA ++// ++// MessageText: ++// ++// There is not enough system VA space available to satisfy the request, ++// ++#define HV_STATUS_INSUFFICIENT_SYSTEM_VA ((HV_STATUS)0x100E) ++ ++// ++// MessageId: HV_STATUS_VIRTUAL_ADDRESS_NOT_MAPPED ++// ++// MessageText: ++// ++// The passed virtual address was not mapped in the hypervisor address space. ++// ++#define HV_STATUS_VIRTUAL_ADDRESS_NOT_MAPPED ((HV_STATUS)0x100F) ++ ++// ++// MessageId: HV_STATUS_NOT_IMPLEMENTED ++// ++// MessageText: ++// ++// The requested operation is not implemented in this version of the hypervisor. ++// ++#define HV_STATUS_NOT_IMPLEMENTED ((HV_STATUS)0x1010) ++ ++// ++// MessageId: HV_STATUS_VMX_INSTRUCTION_FAILED ++// ++// MessageText: ++// ++// The requested VMX instruction failed to complete succesfully. ++// ++#define HV_STATUS_VMX_INSTRUCTION_FAILED ((HV_STATUS)0x1011) ++ ++// ++// MessageId: HV_STATUS_VMX_INSTRUCTION_FAILED_WITH_STATUS ++// ++// MessageText: ++// ++// The requested VMX instruction failed to complete succesfully indicating status. ++// ++#define HV_STATUS_VMX_INSTRUCTION_FAILED_WITH_STATUS ((HV_STATUS)0x1012) ++ ++// ++// MessageId: HV_STATUS_MSR_ACCESS_FAILED ++// ++// MessageText: ++// ++// The requested access to the model specific register failed. ++// ++#define HV_STATUS_MSR_ACCESS_FAILED ((HV_STATUS)0x1013) ++ ++// ++// MessageId: HV_STATUS_CR_ACCESS_FAILED ++// ++// MessageText: ++// ++// The requested access to the control register failed. ++// ++#define HV_STATUS_CR_ACCESS_FAILED ((HV_STATUS)0x1014) ++ ++// ++// MessageId: HV_STATUS_TIMEOUT ++// ++// MessageText: ++// ++// The specified timeout expired before the operation completed. ++// ++#define HV_STATUS_TIMEOUT ((HV_STATUS)0x1016) ++ ++// ++// MessageId: HV_STATUS_MSR_INTERCEPT ++// ++// MessageText: ++// ++// The requested access to the model specific register generated an intercept. ++// ++#define HV_STATUS_MSR_INTERCEPT ((HV_STATUS)0x1017) ++ ++// ++// MessageId: HV_STATUS_CPUID_INTERCEPT ++// ++// MessageText: ++// ++// The CPUID instruction generated an intercept. ++// ++#define HV_STATUS_CPUID_INTERCEPT ((HV_STATUS)0x1018) ++ ++// ++// MessageId: HV_STATUS_REPEAT_INSTRUCTION ++// ++// MessageText: ++// ++// The current instruction should be repeated and the instruction pointer not advanced. ++// ++#define HV_STATUS_REPEAT_INSTRUCTION ((HV_STATUS)0x1019) ++ ++// ++// MessageId: HV_STATUS_PAGE_PROTECTION_VIOLATION ++// ++// MessageText: ++// ++// The current instruction should be repeated and the instruction pointer not advanced. ++// ++#define HV_STATUS_PAGE_PROTECTION_VIOLATION ((HV_STATUS)0x101A) ++ ++// ++// MessageId: HV_STATUS_PAGE_TABLE_INVALID ++// ++// MessageText: ++// ++// The current instruction should be repeated and the instruction pointer not advanced. ++// ++#define HV_STATUS_PAGE_TABLE_INVALID ((HV_STATUS)0x101B) ++ ++// ++// MessageId: HV_STATUS_PAGE_NOT_PRESENT ++// ++// MessageText: ++// ++// The current instruction should be repeated and the instruction pointer not advanced. ++// ++#define HV_STATUS_PAGE_NOT_PRESENT ((HV_STATUS)0x101C) ++ ++// ++// MessageId: HV_STATUS_IO_INTERCEPT ++// ++// MessageText: ++// ++// The requested access to the I/O port generated an intercept. ++// ++#define HV_STATUS_IO_INTERCEPT ((HV_STATUS)0x101D) ++ ++// ++// MessageId: HV_STATUS_NOTHING_TO_DO ++// ++// MessageText: ++// ++// There is nothing to do. ++// ++#define HV_STATUS_NOTHING_TO_DO ((HV_STATUS)0x101E) ++ ++// ++// MessageId: HV_STATUS_THREAD_TERMINATING ++// ++// MessageText: ++// ++// The requested thread is terminating. ++// ++#define HV_STATUS_THREAD_TERMINATING ((HV_STATUS)0x101F) ++ ++// ++// MessageId: HV_STATUS_SECTION_ALREADY_CONSTRUCTED ++// ++// MessageText: ++// ++// The specified section was already constructed. ++// ++#define HV_STATUS_SECTION_ALREADY_CONSTRUCTED ((HV_STATUS)0x1020) ++ ++// ++// MessageId: HV_STATUS_SECTION_NOT_ALREADY_CONSTRUCTED ++// ++// MessageText: ++// ++// The specified section was not already constructed. ++// ++#define HV_STATUS_SECTION_NOT_ALREADY_CONSTRUCTED ((HV_STATUS)0x1021) ++ ++// ++// MessageId: HV_STATUS_PAGE_ALREADY_COMMITTED ++// ++// MessageText: ++// ++// The specified virtual address was already backed by physical memory. ++// ++#define HV_STATUS_PAGE_ALREADY_COMMITTED ((HV_STATUS)0x1022) ++ ++// ++// MessageId: HV_STATUS_PAGE_NOT_ALREADY_COMMITTED ++// ++// MessageText: ++// ++// The specified virtual address was not already backed by physical memory. ++// ++#define HV_STATUS_PAGE_NOT_ALREADY_COMMITTED ((HV_STATUS)0x1023) ++ ++// ++// MessageId: HV_STATUS_COMMITTED_PAGES_REMAIN ++// ++// MessageText: ++// ++// Committed pages remain in the section. ++// ++#define HV_STATUS_COMMITTED_PAGES_REMAIN ((HV_STATUS)0x1024) ++ ++// ++// MessageId: HV_STATUS_NO_REMAINING_COMMITTED_PAGES ++// ++// MessageText: ++// ++// No additional committed pages beyond the specified page exist in the section. ++// ++#define HV_STATUS_NO_REMAINING_COMMITTED_PAGES ((HV_STATUS)0x1025) ++ ++// ++// MessageId: HV_STATUS_INSUFFICIENT_COMPARTMENT_VA ++// ++// MessageText: ++// ++// The VA space of the compartment is exhausted. ++// ++#define HV_STATUS_INSUFFICIENT_COMPARTMENT_VA ((HV_STATUS)0x1026) ++ ++// ++// MessageId: HV_STATUS_DEREF_SPA_LIST_FULL ++// ++// MessageText: ++// ++// The SPA dereference list is full, and there are additional entries ++// to be added to it. ++// ++#define HV_STATUS_DEREF_SPA_LIST_FULL ((HV_STATUS)0x1027) ++ ++// ++// MessageId: HV_STATUS_GPA_OUT_OF_RANGE ++// ++// MessageText: ++// ++// The supplied GPA is out of range. ++// ++#define HV_STATUS_GPA_OUT_OF_RANGE ((HV_STATUS)0x1027) ++ ++// ++// MessageId: HV_STATUS_NONVOLATILE_XMM_STALE ++// ++// MessageText: ++// ++// The XMM register that was being accessed is stale. ++// ++#define HV_STATUS_NONVOLATILE_XMM_STALE ((HV_STATUS)0x1028) ++ ++// ++// MessageId: HV_STATUS_UNSUPPORTED_PROCESSOR ++// ++// MessageText: ++// ++// The hypervisor does not support the processors in this system. ++// ++#define HV_STATUS_UNSUPPORTED_PROCESSOR ((HV_STATUS)0x1029) ++ ++// ++// MessageId: HV_STATUS_INSUFFICIENT_CROM_SPACE ++// ++// MessageText: ++// ++// Insufficient space existed for copying over the CROM contents. ++// ++#define HV_STATUS_INSUFFICIENT_CROM_SPACE ((HV_STATUS)0x2000) ++ ++// ++// MessageId: HV_STATUS_BAD_CROM_FORMAT ++// ++// MessageText: ++// ++// The contents of the CROM failed validation attempts. ++// ++#define HV_STATUS_BAD_CROM_FORMAT ((HV_STATUS)0x2001) ++ ++// ++// MessageId: HV_STATUS_UNSUPPORTED_CROM_FORMAT ++// ++// MessageText: ++// ++// The contents of the CROM contain contents the parser doesn't support. ++// ++#define HV_STATUS_UNSUPPORTED_CROM_FORMAT ((HV_STATUS)0x2002) ++ ++// ++// MessageId: HV_STATUS_UNSUPPORTED_CONTROLLER ++// ++// MessageText: ++// ++// The register format of the OHCI controller specified for debugging is not supported. ++// ++#define HV_STATUS_UNSUPPORTED_CONTROLLER ((HV_STATUS)0x2003) ++ ++// ++// MessageId: HV_STATUS_CROM_TOO_LARGE ++// ++// MessageText: ++// ++// The CROM contents were to large to copy over. ++// ++#define HV_STATUS_CROM_TOO_LARGE ((HV_STATUS)0x2004) ++ ++// ++// MessageId: HV_STATUS_CONTROLLER_IN_USE ++// ++// MessageText: ++// ++// The OHCI controller specified for debugging cannot be used as it is already in use. ++// ++#define HV_STATUS_CONTROLLER_IN_USE ((HV_STATUS)0x2005) ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/HvSynicApi.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvSynicApi.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvSynicApi.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,490 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++#pragma once ++ ++// ++// Define the virtual APIC registers ++// ++#define HV_X64_MSR_EOI (0x40000070) ++#define HV_X64_MSR_ICR (0x40000071) ++#define HV_X64_MSR_TPR (0x40000072) ++#define HV_X64_MSR_APIC_ASSIST_PAGE (0x40000073) ++ ++// ++// Define version of the synthetic interrupt controller. ++// ++ ++#define HV_SYNIC_VERSION (1) ++ ++ ++// ++// Define synthetic interrupt controller model specific registers. ++// ++ ++#define HV_X64_MSR_SCONTROL (0x40000080) ++#define HV_X64_MSR_SVERSION (0x40000081) ++#define HV_X64_MSR_SIEFP (0x40000082) ++#define HV_X64_MSR_SIMP (0x40000083) ++#define HV_X64_MSR_EOM (0x40000084) ++#define HV_X64_MSR_SINT0 (0x40000090) ++#define HV_X64_MSR_SINT1 (0x40000091) ++#define HV_X64_MSR_SINT2 (0x40000092) ++#define HV_X64_MSR_SINT3 (0x40000093) ++#define HV_X64_MSR_SINT4 (0x40000094) ++#define HV_X64_MSR_SINT5 (0x40000095) ++#define HV_X64_MSR_SINT6 (0x40000096) ++#define HV_X64_MSR_SINT7 (0x40000097) ++#define HV_X64_MSR_SINT8 (0x40000098) ++#define HV_X64_MSR_SINT9 (0x40000099) ++#define HV_X64_MSR_SINT10 (0x4000009A) ++#define HV_X64_MSR_SINT11 (0x4000009B) ++#define HV_X64_MSR_SINT12 (0x4000009C) ++#define HV_X64_MSR_SINT13 (0x4000009D) ++#define HV_X64_MSR_SINT14 (0x4000009E) ++#define HV_X64_MSR_SINT15 (0x4000009F) ++ ++// ++// Define the expected SynIC version. ++// ++#define HV_SYNIC_VERSION_1 (0x1) ++ ++// ++// Define synthetic interrupt controller message constants. ++// ++ ++#define HV_MESSAGE_SIZE (256) ++#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) ++#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) ++#define HV_ANY_VP (0xFFFFFFFF) ++ ++// ++// Define synthetic interrupt controller flag constants. ++// ++ ++#define HV_EVENT_FLAGS_COUNT (256 * 8) ++#define HV_EVENT_FLAGS_BYTE_COUNT (256) ++#define HV_EVENT_FLAGS_DWORD_COUNT (256 / sizeof(UINT32)) ++ ++// ++// Define hypervisor message types. ++// ++typedef enum _HV_MESSAGE_TYPE ++{ ++ HvMessageTypeNone = 0x00000000, ++ ++ // ++ // Memory access messages. ++ // ++ HvMessageTypeUnmappedGpa = 0x80000000, ++ HvMessageTypeGpaIntercept = 0x80000001, ++ ++ // ++ // Timer notification messages. ++ // ++ HvMessageTimerExpired = 0x80000010, ++ ++ // ++ // Error messages. ++ // ++ HvMessageTypeInvalidVpRegisterValue = 0x80000020, ++ HvMessageTypeUnrecoverableException = 0x80000021, ++ HvMessageTypeUnsupportedFeature = 0x80000022, ++ ++ // ++ // Trace buffer complete messages. ++ // ++ HvMessageTypeEventLogBufferComplete = 0x80000040, ++ ++ // ++ // Platform-specific processor intercept messages. ++ // ++ HvMessageTypeX64IoPortIntercept = 0x80010000, ++ HvMessageTypeX64MsrIntercept = 0x80010001, ++ HvMessageTypeX64CpuidIntercept = 0x80010002, ++ HvMessageTypeX64ExceptionIntercept = 0x80010003, ++ HvMessageTypeX64ApicEoi = 0x80010004, ++ HvMessageTypeX64LegacyFpError = 0x80010005 ++ ++} HV_MESSAGE_TYPE, *PHV_MESSAGE_TYPE; ++ ++// ++// Define the number of synthetic interrupt sources. ++// ++ ++#define HV_SYNIC_SINT_COUNT (16) ++#define HV_SYNIC_STIMER_COUNT (4) ++ ++// ++// Define the synthetic interrupt source index type. ++// ++ ++typedef UINT32 HV_SYNIC_SINT_INDEX, *PHV_SYNIC_SINT_INDEX; ++ ++// ++// Define partition identifier type. ++// ++ ++typedef UINT64 HV_PARTITION_ID, *PHV_PARTITION_ID; ++ ++// ++// Define invalid partition identifier. ++// ++#define HV_PARTITION_ID_INVALID ((HV_PARTITION_ID) 0x0) ++ ++// ++// Define connection identifier type. ++// ++ ++typedef union _HV_CONNECTION_ID ++{ ++ UINT32 AsUINT32; ++ ++ struct ++ { ++ UINT32 Id:24; ++ UINT32 Reserved:8; ++ } u; ++ ++} HV_CONNECTION_ID, *PHV_CONNECTION_ID; ++ ++// ++// Define port identifier type. ++// ++ ++typedef union _HV_PORT_ID ++{ ++ UINT32 AsUINT32; ++ ++ struct ++ { ++ UINT32 Id:24; ++ UINT32 Reserved:8; ++ } u ; ++ ++} HV_PORT_ID, *PHV_PORT_ID; ++ ++// ++// Define port type. ++// ++ ++typedef enum _HV_PORT_TYPE ++{ ++ HvPortTypeMessage = 1, ++ HvPortTypeEvent = 2, ++ HvPortTypeMonitor = 3 ++} HV_PORT_TYPE, *PHV_PORT_TYPE; ++ ++// ++// Define port information structure. ++// ++ ++typedef struct _HV_PORT_INFO ++{ ++ HV_PORT_TYPE PortType; ++ UINT32 Padding; ++ ++ union ++ { ++ struct ++ { ++ HV_SYNIC_SINT_INDEX TargetSint; ++ HV_VP_INDEX TargetVp; ++ UINT64 RsvdZ; ++ } MessagePortInfo; ++ ++ struct ++ { ++ HV_SYNIC_SINT_INDEX TargetSint; ++ HV_VP_INDEX TargetVp; ++ UINT16 BaseFlagNumber; ++ UINT16 FlagCount; ++ UINT32 RsvdZ; ++ } EventPortInfo; ++ ++ struct ++ { ++ HV_GPA MonitorAddress; ++ UINT64 RsvdZ; ++ } MonitorPortInfo; ++ }; ++} HV_PORT_INFO, *PHV_PORT_INFO; ++ ++typedef const HV_PORT_INFO *PCHV_PORT_INFO; ++ ++typedef struct _HV_CONNECTION_INFO ++{ ++ HV_PORT_TYPE PortType; ++ UINT32 Padding; ++ ++ union ++ { ++ struct ++ { ++ UINT64 RsvdZ; ++ } MessageConnectionInfo; ++ ++ struct ++ { ++ UINT64 RsvdZ; ++ } EventConnectionInfo; ++ ++ struct ++ { ++ HV_GPA MonitorAddress; ++ } MonitorConnectionInfo; ++ }; ++} HV_CONNECTION_INFO, *PHV_CONNECTION_INFO; ++ ++typedef const HV_CONNECTION_INFO *PCHV_CONNECTION_INFO; ++ ++// ++// Define synthetic interrupt controller message flags. ++// ++ ++typedef union _HV_MESSAGE_FLAGS ++{ ++ UINT8 AsUINT8; ++ struct ++ { ++ UINT8 MessagePending:1; ++ UINT8 Reserved:7; ++ }; ++} HV_MESSAGE_FLAGS, *PHV_MESSAGE_FLAGS; ++ ++ ++// ++// Define synthetic interrupt controller message header. ++// ++ ++typedef struct _HV_MESSAGE_HEADER ++{ ++ HV_MESSAGE_TYPE MessageType; ++ UINT8 PayloadSize; ++ HV_MESSAGE_FLAGS MessageFlags; ++ UINT8 Reserved[2]; ++ union ++ { ++ HV_PARTITION_ID Sender; ++ HV_PORT_ID Port; ++ }; ++ ++} HV_MESSAGE_HEADER, *PHV_MESSAGE_HEADER; ++ ++// ++// Define timer message payload structure. ++// ++typedef struct _HV_TIMER_MESSAGE_PAYLOAD ++{ ++ UINT32 TimerIndex; ++ UINT32 Reserved; ++ HV_NANO100_TIME ExpirationTime; // When the timer expired ++ HV_NANO100_TIME DeliveryTime; // When the message was delivered ++} HV_TIMER_MESSAGE_PAYLOAD, *PHV_TIMER_MESSAGE_PAYLOAD; ++ ++// ++// Define synthetic interrupt controller message format. ++// ++ ++typedef struct _HV_MESSAGE ++{ ++ HV_MESSAGE_HEADER Header; ++ union ++ { ++ UINT64 Payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; ++ } u ; ++} HV_MESSAGE, *PHV_MESSAGE; ++ ++// ++// Define the number of message buffers associated with each port. ++// ++ ++#define HV_PORT_MESSAGE_BUFFER_COUNT (16) ++ ++// ++// Define the synthetic interrupt message page layout. ++// ++ ++typedef struct _HV_MESSAGE_PAGE ++{ ++ volatile HV_MESSAGE SintMessage[HV_SYNIC_SINT_COUNT]; ++} HV_MESSAGE_PAGE, *PHV_MESSAGE_PAGE; ++ ++ ++// ++// Define the synthetic interrupt controller event flags format. ++// ++ ++typedef union _HV_SYNIC_EVENT_FLAGS ++{ ++ UINT8 Flags8[HV_EVENT_FLAGS_BYTE_COUNT]; ++ UINT32 Flags32[HV_EVENT_FLAGS_DWORD_COUNT]; ++} HV_SYNIC_EVENT_FLAGS, *PHV_SYNIC_EVENT_FLAGS; ++ ++ ++// ++// Define the synthetic interrupt flags page layout. ++// ++ ++typedef struct _HV_SYNIC_EVENT_FLAGS_PAGE ++{ ++ volatile HV_SYNIC_EVENT_FLAGS SintEventFlags[HV_SYNIC_SINT_COUNT]; ++} HV_SYNIC_EVENT_FLAGS_PAGE, *PHV_SYNIC_EVENT_FLAGS_PAGE; ++ ++ ++// ++// Define SynIC control register. ++// ++typedef union _HV_SYNIC_SCONTROL ++{ ++ UINT64 AsUINT64; ++ struct ++ { ++ UINT64 Enable:1; ++ UINT64 Reserved:63; ++ }; ++} HV_SYNIC_SCONTROL, *PHV_SYNIC_SCONTROL; ++ ++// ++// Define synthetic interrupt source. ++// ++ ++typedef union _HV_SYNIC_SINT ++{ ++ UINT64 AsUINT64; ++ struct ++ { ++ UINT64 Vector :8; ++ UINT64 Reserved1 :8; ++ UINT64 Masked :1; ++ UINT64 AutoEoi :1; ++ UINT64 Reserved2 :46; ++ }; ++} HV_SYNIC_SINT, *PHV_SYNIC_SINT; ++ ++// ++// Define the format of the SIMP register ++// ++ ++typedef union _HV_SYNIC_SIMP ++{ ++ UINT64 AsUINT64; ++ struct ++ { ++ UINT64 SimpEnabled : 1; ++ UINT64 Preserved : 11; ++ UINT64 BaseSimpGpa : 52; ++ }; ++} HV_SYNIC_SIMP, *PHV_SYNIC_SIMP; ++ ++// ++// Define the format of the SIEFP register ++// ++ ++typedef union _HV_SYNIC_SIEFP ++{ ++ UINT64 AsUINT64; ++ struct ++ { ++ UINT64 SiefpEnabled : 1; ++ UINT64 Preserved : 11; ++ UINT64 BaseSiefpGpa : 52; ++ }; ++} HV_SYNIC_SIEFP, *PHV_SYNIC_SIEFP; ++ ++// ++// Definitions for the monitored notification facility ++// ++ ++typedef union _HV_MONITOR_TRIGGER_GROUP ++{ ++ UINT64 AsUINT64; ++ ++ struct ++ { ++ UINT32 Pending; ++ UINT32 Armed; ++ }; ++ ++} HV_MONITOR_TRIGGER_GROUP, *PHV_MONITOR_TRIGGER_GROUP; ++ ++typedef struct _HV_MONITOR_PARAMETER ++{ ++ HV_CONNECTION_ID ConnectionId; ++ UINT16 FlagNumber; ++ UINT16 RsvdZ; ++} HV_MONITOR_PARAMETER, *PHV_MONITOR_PARAMETER; ++ ++typedef union _HV_MONITOR_TRIGGER_STATE ++{ ++ UINT32 AsUINT32; ++ ++ struct ++ { ++ UINT32 GroupEnable : 4; ++ UINT32 RsvdZ : 28; ++ }; ++ ++} HV_MONITOR_TRIGGER_STATE, *PHV_MONITOR_TRIGGER_STATE; ++ ++// ++// HV_MONITOR_PAGE Layout ++// ------------------------------------------------------ ++// | 0 | TriggerState (4 bytes) | Rsvd1 (4 bytes) | ++// | 8 | TriggerGroup[0] | ++// | 10 | TriggerGroup[1] | ++// | 18 | TriggerGroup[2] | ++// | 20 | TriggerGroup[3] | ++// | 28 | Rsvd2[0] | ++// | 30 | Rsvd2[1] | ++// | 38 | Rsvd2[2] | ++// | 40 | NextCheckTime[0][0] | NextCheckTime[0][1] | ++// | ... | ++// | 240 | Latency[0][0..3] | ++// | 340 | Rsvz3[0] | ++// | 440 | Parameter[0][0] | ++// | 448 | Parameter[0][1] | ++// | ... | ++// | 840 | Rsvd4[0] | ++// ------------------------------------------------------ ++ ++typedef struct _HV_MONITOR_PAGE ++{ ++ HV_MONITOR_TRIGGER_STATE TriggerState; ++ UINT32 RsvdZ1; ++ ++ HV_MONITOR_TRIGGER_GROUP TriggerGroup[4]; ++ UINT64 RsvdZ2[3]; ++ ++ INT32 NextCheckTime[4][32]; ++ ++ UINT16 Latency[4][32]; ++ UINT64 RsvdZ3[32]; ++ ++ HV_MONITOR_PARAMETER Parameter[4][32]; ++ ++ UINT8 RsvdZ4[1984]; ++ ++} HV_MONITOR_PAGE, *PHV_MONITOR_PAGE; ++ ++typedef volatile HV_MONITOR_PAGE* PVHV_MONITOR_PAGE; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/HvTypes.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvTypes.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvTypes.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,31 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#pragma once ++ ++typedef UINT64 HV_GPA, *PHV_GPA; ++ ++#define HV_X64_PAGE_SIZE (4096) ++#define HV_PAGE_SIZE HV_X64_PAGE_SIZE ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/HvVpApi.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvVpApi.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/HvVpApi.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,51 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#pragma once ++// ++// Virtual Processor Indices ++// ++typedef UINT32 HV_VP_INDEX, *PHV_VP_INDEX; ++ ++// ++// The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent ++// is set by CPUID(HvCpuIdFunctionVersionAndFeatures). ++// ========================================================================== ++// ++ ++typedef enum _HV_CPUID_FUNCTION ++{ ++ HvCpuIdFunctionVersionAndFeatures = 0x00000001, ++ HvCpuIdFunctionHvVendorAndMaxFunction = 0x40000000, ++ HvCpuIdFunctionHvInterface = 0x40000001, ++ ++ // ++ // The remaining functions depend on the value of HvCpuIdFunctionInterface ++ // ++ HvCpuIdFunctionMsHvVersion = 0x40000002, ++ HvCpuIdFunctionMsHvFeatures = 0x40000003, ++ HvCpuIdFunctionMsHvEnlightenmentInformation = 0x40000004, ++ HvCpuIdFunctionMsHvImplementationLimits = 0x40000005 ++ ++} HV_CPUID_FUNCTION, *PHV_CPUID_FUNCTION; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/List.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/List.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/List.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,269 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _LIST_H_ ++#define _LIST_H_ ++ ++#include "osd.h" ++/* ++ * ++ * Doubly-linked list manipulation routines. Implemented as macros ++ * but logically these are procedures. ++ * ++ */ ++ ++typedef DLIST_ENTRY LIST_ENTRY; ++typedef DLIST_ENTRY *PLIST_ENTRY; ++ ++//typedef struct LIST_ENTRY { ++// struct LIST_ENTRY * volatile Flink; ++// struct LIST_ENTRY * volatile Blink; ++//} LIST_ENTRY, *PLIST_ENTRY; ++ ++ ++ ++/* ++ * VOID ++ * InitializeListHead( ++ * PLIST_ENTRY ListHead ++ * ); ++ */ ++#define INITIALIZE_LIST_HEAD InitializeListHead ++ ++#define InitializeListHead(ListHead) (\ ++ (ListHead)->Flink = (ListHead)->Blink = (ListHead)) ++ ++ ++/* ++ * BOOLEAN ++ * IsListEmpty( ++ * PLIST_ENTRY ListHead ++ * ); ++ */ ++#define IS_LIST_EMPTY IsListEmpty ++ ++#define IsListEmpty(ListHead) \ ++ ((ListHead)->Flink == (ListHead)) ++ ++ ++/* ++ * PLIST_ENTRY ++ * NextListEntry( ++ * PLIST_ENTRY Entry ++ * ); ++ */ ++#define NEXT_LIST_ENTRY NextListEntry ++ ++#define NextListEntry(Entry) \ ++ (Entry)->Flink ++ ++ ++/* ++ * PLIST_ENTRY ++ * PrevListEntry( ++ * PLIST_ENTRY Entry ++ * ); ++ */ ++#define PREV_LIST_ENTRY PrevListEntry ++ ++#define PrevListEntry(Entry) \ ++ (Entry)->Blink ++ ++ ++/* ++ * PLIST_ENTRY ++ * TopListEntry( ++ * PLIST_ENTRY ListHead ++ * ); ++ */ ++#define TOP_LIST_ENTRY TopListEntry ++ ++#define TopListEntry(ListHead) \ ++ (ListHead)->Flink ++ ++ ++ ++/* ++ * PLIST_ENTRY ++ * RemoveHeadList( ++ * PLIST_ENTRY ListHead ++ * ); ++ */ ++ ++#define REMOVE_HEAD_LIST RemoveHeadList ++ ++#define RemoveHeadList(ListHead) \ ++ (ListHead)->Flink;\ ++ {RemoveEntryList((ListHead)->Flink)} ++ ++ ++/* ++ * PLIST_ENTRY ++ * RemoveTailList( ++ * PLIST_ENTRY ListHead ++ * ); ++ */ ++#define REMOVE_TAIL_LIST RemoveTailList ++ ++#define RemoveTailList(ListHead) \ ++ (ListHead)->Blink;\ ++ {RemoveEntryList((ListHead)->Blink)} ++ ++ ++/* ++ * VOID ++ * RemoveEntryList( ++ * PLIST_ENTRY Entry ++ * ); ++ */ ++#define REMOVE_ENTRY_LIST RemoveEntryList ++ ++#define RemoveEntryList(Entry) {\ ++ PLIST_ENTRY _EX_Flink = (Entry)->Flink;\ ++ PLIST_ENTRY _EX_Blink = (Entry)->Blink;\ ++ _EX_Blink->Flink = _EX_Flink;\ ++ _EX_Flink->Blink = _EX_Blink;\ ++ } ++ ++ ++/* ++ * VOID ++ * AttachList( ++ * PLIST_ENTRY ListHead, ++ * PLIST_ENTRY ListEntry ++ * ); ++ */ ++#define ATTACH_LIST AttachList ++ ++#define AttachList(ListHead,ListEntry) {\ ++ PLIST_ENTRY _EX_ListHead = (ListHead);\ ++ PLIST_ENTRY _EX_Blink = (ListHead)->Blink;\ ++ (ListEntry)->Blink->Flink = _EX_ListHead;\ ++ _EX_Blink->Flink = (ListEntry);\ ++ _EX_ListHead->Blink = (ListEntry)->Blink;\ ++ (ListEntry)->Blink = _EX_Blink;\ ++ } ++ ++ ++ ++/* ++ * VOID ++ * InsertTailList( ++ * PLIST_ENTRY ListHead, ++ * PLIST_ENTRY Entry ++ * ); ++ */ ++ ++#define INSERT_TAIL_LIST InsertTailList ++ ++#define InsertTailList(ListHead,Entry) {\ ++ PLIST_ENTRY _EX_ListHead = (ListHead);\ ++ PLIST_ENTRY _EX_Blink = (ListHead)->Blink;\ ++ (Entry)->Flink = _EX_ListHead;\ ++ (Entry)->Blink = _EX_Blink;\ ++ _EX_Blink->Flink = (Entry);\ ++ _EX_ListHead->Blink = (Entry);\ ++ } ++ ++ ++/* ++ * VOID ++ * InsertHeadList( ++ * PLIST_ENTRY ListHead, ++ * PLIST_ENTRY Entry ++ * ); ++ */ ++#define INSERT_HEAD_LIST InsertHeadList ++ ++#define InsertHeadList(ListHead,Entry) {\ ++ PLIST_ENTRY _EX_ListHead = (ListHead);\ ++ PLIST_ENTRY _EX_Flink = (ListHead)->Flink;\ ++ (Entry)->Flink = _EX_Flink;\ ++ (Entry)->Blink = _EX_ListHead;\ ++ _EX_Flink->Blink = (Entry);\ ++ _EX_ListHead->Flink = (Entry);\ ++ } ++ ++ ++/* ++ * VOID ++ * IterateListEntries( ++ * PLIST_ENTRY anchor, ++ * PLIST_ENTRY index, ++ * PLIST_ENTRY listp ++ * ); ++ */ ++ ++#define ITERATE_LIST_ENTRIES IterateListEntries ++ ++#define IterateListEntries(anchor, index, listp) \ ++ (anchor) = (LIST_ENTRY *)(listp); \ ++ for((index) = (anchor)->Flink; (index) != (anchor); (index) = (index)->Flink) ++ ++ ++ ++/* ++ * PSINGLE_LIST_ENTRY ++ * PopEntryList( ++ * PSINGLE_LIST_ENTRY ListHead ++ * ); ++ */ ++ ++#define POP_ENTRY_LIST PopEntryList ++ ++#define PopEntryList(ListHead) \ ++ (ListHead)->Next;\ ++ {\ ++ PSINGLE_LIST_ENTRY FirstEntry;\ ++ FirstEntry = (ListHead)->Next;\ ++ if (FirstEntry != NULL) { \ ++ (ListHead)->Next = FirstEntry->Next;\ ++ } \ ++ } ++ ++ ++ ++/* ++ * VOID ++ * PushEntryList( ++ * PSINGLE_LIST_ENTRY ListHead, ++ * PSINGLE_LIST_ENTRY Entry ++ * ); ++ */ ++ ++#define PUSH_ENTRY_LIST PushEntryList ++ ++#define PushEntryList(ListHead,Entry) \ ++ (Entry)->Next = (ListHead)->Next; \ ++ (ListHead)->Next = (Entry) ++ ++#ifndef CONTAINING_RECORD ++#define CONTAINING_RECORD(address, type, field) ((type *)( \ ++ (PCHAR)(address) - \ ++ (PCHAR)(&((type *)0)->field))) ++#endif /* CONTAINING_RECORD */ ++ ++#endif /* _LIST_H_ */ ++ ++/* EOF */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/logging.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/logging.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/logging.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,134 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _LOGGING_H_ ++#define _LOGGING_H_ ++ ++//#include ++//#include ++ ++#include "osd.h" ++ ++#define VMBUS 0x0001 ++#define STORVSC 0x0002 ++#define NETVSC 0x0004 ++#define INPUTVSC 0x0008 ++#define BLKVSC 0x0010 ++#define VMBUS_DRV 0x0100 ++#define STORVSC_DRV 0x0200 ++#define NETVSC_DRV 0x0400 ++#define INPUTVSC_DRV 0x0800 ++#define BLKVSC_DRV 0x1000 ++ ++#define ALL_MODULES (VMBUS |\ ++ STORVSC |\ ++ NETVSC |\ ++ INPUTVSC |\ ++ BLKVSC |\ ++ VMBUS_DRV |\ ++ STORVSC_DRV |\ ++ NETVSC_DRV |\ ++ INPUTVSC_DRV|\ ++ BLKVSC_DRV) ++ ++// Logging Level ++#define CRITICAL_LVL 2 ++#define ERROR_LVL 3 ++#define WARNING_LVL 4 ++#define INFO_LVL 6 ++#define DEBUG_LVL 7 ++#define DEBUG_LVL_ENTEREXIT 8 ++#define DEBUG_RING_LVL 9 ++ ++extern unsigned int vmbus_loglevel; ++ ++#define ASSERT(expr) \ ++ if (!(expr)) { \ ++ LogMsg("<%d>Assertion failed! %s,%s,%s,line=%d\n", CRITICAL_LVL, #expr,__FILE__,__FUNCTION__,__LINE__); \ ++ __asm__ __volatile__("int3"); \ ++ } ++ ++#define DPRINT(mod, lvl, fmt, args...) do {\ ++ if (mod & (HIWORD(vmbus_loglevel))) \ ++ (lvl <= LOWORD(vmbus_loglevel))?(LogMsg("<%d>" #mod": %s() " fmt "\n", DEBUG_LVL, __FUNCTION__, ## args)):(0);\ ++ } while (0) ++ ++#define DPRINT_DBG(mod, fmt, args...) do {\ ++ if (mod & (HIWORD(vmbus_loglevel))) \ ++ (DEBUG_LVL <= LOWORD(vmbus_loglevel))?(LogMsg("<%d>" #mod": %s() " fmt "\n", DEBUG_LVL, __FUNCTION__, ## args)):(0);\ ++ } while (0) ++ ++#define DPRINT_INFO(mod, fmt, args...) do {\ ++ if (mod & (HIWORD(vmbus_loglevel))) \ ++ (INFO_LVL <= LOWORD(vmbus_loglevel))?(LogMsg("<%d>" #mod": " fmt "\n", INFO_LVL, ## args)):(0);\ ++ } while (0) ++ ++#define DPRINT_WARN(mod, fmt, args...) do {\ ++ if (mod & (HIWORD(vmbus_loglevel))) \ ++ (WARNING_LVL <= LOWORD(vmbus_loglevel))?(LogMsg("<%d>" #mod": WARNING! " fmt "\n", WARNING_LVL, ## args)):(0);\ ++ } while (0) ++ ++#define DPRINT_ERR(mod, fmt, args...) do {\ ++ if (mod & (HIWORD(vmbus_loglevel))) \ ++ (ERROR_LVL <= LOWORD(vmbus_loglevel))?(LogMsg("<%d>" #mod": %s() ERROR!! " fmt "\n", ERROR_LVL, __FUNCTION__, ## args)):(0);\ ++ } while (0) ++ ++#ifdef DEBUG ++#define DPRINT_ENTER(mod) do {\ ++ if (mod & (HIWORD(vmbus_loglevel))) \ ++ (DEBUG_LVL_ENTEREXIT <= LOWORD(vmbus_loglevel))?(LogMsg("<%d>" "["#mod"]: %s() enter\n", DEBUG_LVL, __FUNCTION__)):(0);\ ++ } while (0) ++ ++#define DPRINT_EXIT(mod) do {\ ++ if (mod & (HIWORD(vmbus_loglevel))) \ ++ (DEBUG_LVL_ENTEREXIT <= LOWORD(vmbus_loglevel))?(LogMsg("<%d>" "["#mod"]: %s() exit\n", DEBUG_LVL, __FUNCTION__)):(0);\ ++ } while (0) ++#else ++#define DPRINT_ENTER(mod) ++#define DPRINT_EXIT(mod) ++#endif ++ ++static inline void PrintBytes(const unsigned char* bytes, int len) ++{ ++ int i=0; ++ ++ LogMsg("\n<< "); ++ for (i=0; i< len; i++) ++ { ++ LogMsg("0x%x ", bytes[i]); ++ } ++ LogMsg(">>\n"); ++} ++ ++// ++// Inline ++// ++//static inline void GuidToStr(const GUID g, char *str) ++//{ ++// sprintf(str, "{%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}", ++// g[3], g[2], g[1], g[0], g[5], g[4], g[7], g[6], g[8], g[9], g[10], g[11], g[12], g[13], g[14], g[15]); ++// ++//} ++ ++#endif //_LOGGING_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/NetVscApi.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/NetVscApi.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/NetVscApi.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,145 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _NETVSC_API_H_ ++#define _NETVSC_API_H_ ++ ++#include "VmbusApi.h" ++ ++// ++// Defines ++// ++#define NETVSC_DEVICE_RING_BUFFER_SIZE 64*PAGE_SIZE ++ ++#define HW_MACADDR_LEN 6 ++ ++// ++// Fwd declaration ++// ++typedef struct _NETVSC_PACKET *PNETVSC_PACKET; ++ ++ ++// ++// Data types ++// ++ ++typedef int (*PFN_ON_OPEN)(DEVICE_OBJECT *Device); ++typedef int (*PFN_ON_CLOSE)(DEVICE_OBJECT *Device); ++ ++typedef void (*PFN_QUERY_LINKSTATUS)(DEVICE_OBJECT *Device); ++typedef int (*PFN_ON_SEND)(DEVICE_OBJECT *dev, PNETVSC_PACKET packet); ++typedef void (*PFN_ON_SENDRECVCOMPLETION)(PVOID Context); ++ ++typedef int (*PFN_ON_RECVCALLBACK)(DEVICE_OBJECT *dev, PNETVSC_PACKET packet); ++typedef void (*PFN_ON_LINKSTATUS_CHANGED)(DEVICE_OBJECT *dev, UINT32 Status); ++ ++// Represent the xfer page packet which contains 1 or more netvsc packet ++typedef struct _XFERPAGE_PACKET { ++ DLIST_ENTRY ListEntry; ++ ++ // # of netvsc packets this xfer packet contains ++ UINT32 Count; ++} XFERPAGE_PACKET; ++ ++ ++// The number of pages which are enough to cover jumbo frame buffer. ++#define NETVSC_PACKET_MAXPAGE 4 ++ ++// Represent netvsc packet which contains 1 RNDIS and 1 ethernet frame within the RNDIS ++typedef struct _NETVSC_PACKET { ++ // Bookkeeping stuff ++ DLIST_ENTRY ListEntry; ++ ++ DEVICE_OBJECT *Device; ++ BOOL IsDataPacket; ++ ++ // Valid only for receives when we break a xfer page packet into multiple netvsc packets ++ XFERPAGE_PACKET *XferPagePacket; ++ ++ union { ++ struct{ ++ UINT64 ReceiveCompletionTid; ++ PVOID ReceiveCompletionContext; ++ PFN_ON_SENDRECVCOMPLETION OnReceiveCompletion; ++ } Recv; ++ struct{ ++ UINT64 SendCompletionTid; ++ PVOID SendCompletionContext; ++ PFN_ON_SENDRECVCOMPLETION OnSendCompletion; ++ } Send; ++ } Completion; ++ ++ // This points to the memory after PageBuffers ++ PVOID Extension; ++ ++ UINT32 TotalDataBufferLength; ++ // Points to the send/receive buffer where the ethernet frame is ++ UINT32 PageBufferCount; ++ PAGE_BUFFER PageBuffers[NETVSC_PACKET_MAXPAGE]; ++ ++} NETVSC_PACKET; ++ ++ ++// Represents the net vsc driver ++typedef struct _NETVSC_DRIVER_OBJECT { ++ DRIVER_OBJECT Base; // Must be the first field ++ ++ UINT32 RingBufferSize; ++ UINT32 RequestExtSize; ++ ++ // Additional num of page buffers to allocate ++ UINT32 AdditionalRequestPageBufferCount; ++ ++ // This is set by the caller to allow us to callback when we receive a packet ++ // from the "wire" ++ PFN_ON_RECVCALLBACK OnReceiveCallback; ++ ++ PFN_ON_LINKSTATUS_CHANGED OnLinkStatusChanged; ++ ++ // Specific to this driver ++ PFN_ON_OPEN OnOpen; ++ PFN_ON_CLOSE OnClose; ++ PFN_ON_SEND OnSend; ++ //PFN_ON_RECVCOMPLETION OnReceiveCompletion; ++ ++ //PFN_QUERY_LINKSTATUS QueryLinkStatus; ++ ++ void* Context; ++} NETVSC_DRIVER_OBJECT; ++ ++ ++typedef struct _NETVSC_DEVICE_INFO { ++ UCHAR MacAddr[6]; ++ BOOL LinkState; // 0 - link up, 1 - link down ++} NETVSC_DEVICE_INFO; ++ ++// ++// Interface ++// ++int ++NetVscInitialize( ++ DRIVER_OBJECT* drv ++ ); ++ ++#endif // _NETVSC_API_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/nvspprotocol.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/nvspprotocol.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/nvspprotocol.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,306 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#pragma once ++ ++#include "VmbusChannelInterface.h" ++ ++#define NVSP_INVALID_PROTOCOL_VERSION ((UINT32)0xFFFFFFFF) ++ ++#define NVSP_PROTOCOL_VERSION_1 2 ++#define NVSP_MIN_PROTOCOL_VERSION NVSP_PROTOCOL_VERSION_1 ++#define NVSP_MAX_PROTOCOL_VERSION NVSP_PROTOCOL_VERSION_1 ++ ++typedef enum _NVSP_MESSAGE_TYPE ++{ ++ NvspMessageTypeNone = 0, ++ ++ // ++ // Init Messages ++ // ++ NvspMessageTypeInit = 1, ++ NvspMessageTypeInitComplete = 2, ++ ++ NvspVersionMessageStart = 100, ++ ++ // ++ // Version 1 Messages ++ // ++ NvspMessage1TypeSendNdisVersion = NvspVersionMessageStart, ++ ++ NvspMessage1TypeSendReceiveBuffer, ++ NvspMessage1TypeSendReceiveBufferComplete, ++ NvspMessage1TypeRevokeReceiveBuffer, ++ ++ NvspMessage1TypeSendSendBuffer, ++ NvspMessage1TypeSendSendBufferComplete, ++ NvspMessage1TypeRevokeSendBuffer, ++ ++ NvspMessage1TypeSendRNDISPacket, ++ NvspMessage1TypeSendRNDISPacketComplete, ++ ++ // ++ // This should be set to the number of messages for the version ++ // with the maximum number of messages. ++ // ++ NvspNumMessagePerVersion = 9, ++ ++} NVSP_MESSAGE_TYPE, *PNVSP_MESSAGE_TYPE; ++ ++typedef enum _NVSP_STATUS ++{ ++ NvspStatusNone = 0, ++ NvspStatusSuccess, ++ NvspStatusFailure, ++ NvspStatusProtocolVersionRangeTooNew, ++ NvspStatusProtocolVersionRangeTooOld, ++ NvspStatusInvalidRndisPacket, ++ NvspStatusBusy, ++ NvspStatusMax, ++} NVSP_STATUS, *PNVSP_STATUS; ++ ++#pragma pack(push, 1) ++ ++typedef struct _NVSP_MESSAGE_HEADER ++{ ++ UINT32 MessageType; ++} NVSP_MESSAGE_HEADER, *PNVSP_MESSAGE_HEADER; ++ ++// ++// Init Messages ++// ++ ++// ++// This message is used by the VSC to initialize the channel ++// after the channels has been opened. This message should ++// never include anything other then versioning (i.e. this ++// message will be the same for ever). ++// ++typedef struct _NVSP_MESSAGE_INIT ++{ ++ UINT32 MinProtocolVersion; ++ UINT32 MaxProtocolVersion; ++} NVSP_MESSAGE_INIT, *PNVSP_MESSAGE_INIT; ++ ++// ++// This message is used by the VSP to complete the initialization ++// of the channel. This message should never include anything other ++// then versioning (i.e. this message will be the same for ever). ++// ++typedef struct _NVSP_MESSAGE_INIT_COMPLETE ++{ ++ UINT32 NegotiatedProtocolVersion; ++ UINT32 MaximumMdlChainLength; ++ UINT32 Status; ++} NVSP_MESSAGE_INIT_COMPLETE, *PNVSP_MESSAGE_INIT_COMPLETE; ++ ++typedef union _NVSP_MESSAGE_INIT_UBER ++{ ++ NVSP_MESSAGE_INIT Init; ++ NVSP_MESSAGE_INIT_COMPLETE InitComplete; ++} NVSP_MESSAGE_INIT_UBER; ++ ++// ++// Version 1 Messages ++// ++ ++// ++// This message is used by the VSC to send the NDIS version ++// to the VSP. The VSP can use this information when handling ++// OIDs sent by the VSC. ++// ++typedef struct _NVSP_1_MESSAGE_SEND_NDIS_VERSION ++{ ++ UINT32 NdisMajorVersion; ++ UINT32 NdisMinorVersion; ++} NVSP_1_MESSAGE_SEND_NDIS_VERSION, *PNVSP_1_MESSAGE_SEND_NDIS_VERSION; ++ ++// ++// This message is used by the VSC to send a receive buffer ++// to the VSP. The VSP can then use the receive buffer to ++// send data to the VSC. ++// ++typedef struct _NVSP_1_MESSAGE_SEND_RECEIVE_BUFFER ++{ ++ GPADL_HANDLE GpadlHandle; ++ UINT16 Id; ++} NVSP_1_MESSAGE_SEND_RECEIVE_BUFFER, *PNVSP_1_MESSAGE_SEND_RECEIVE_BUFFER; ++ ++typedef struct _NVSP_1_RECEIVE_BUFFER_SECTION ++{ ++ UINT32 Offset; ++ UINT32 SubAllocationSize; ++ UINT32 NumSubAllocations; ++ UINT32 EndOffset; ++} NVSP_1_RECEIVE_BUFFER_SECTION, *PNVSP_1_RECEIVE_BUFFER_SECTION; ++ ++// ++// This message is used by the VSP to acknowledge a receive ++// buffer send by the VSC. This message must be sent by the ++// VSP before the VSP uses the receive buffer. ++// ++typedef struct _NVSP_1_MESSAGE_SEND_RECEIVE_BUFFER_COMPLETE ++{ ++ UINT32 Status; ++ UINT32 NumSections; ++ ++ // ++ // The receive buffer is split into two parts, a large ++ // suballocation section and a small suballocation ++ // section. These sections are then suballocated by a ++ // certain size. ++ // ++ // For example, the following break up of the receive ++ // buffer has 6 large suballocations and 10 small ++ // suballocations. ++ // ++ // | Large Section | | Small Section | ++ // ------------------------------------------------------------ ++ // | | | | | | | | | | | | | | | | | | ++ // | | ++ // LargeOffset SmallOffset ++ // ++ NVSP_1_RECEIVE_BUFFER_SECTION Sections[1]; ++ ++} NVSP_1_MESSAGE_SEND_RECEIVE_BUFFER_COMPLETE, *PNVSP_1_MESSAGE_SEND_RECEIVE_BUFFER_COMPLETE; ++ ++// ++// This message is sent by the VSC to revoke the receive buffer. ++// After the VSP completes this transaction, the vsp should never ++// use the receive buffer again. ++// ++typedef struct _NVSP_1_MESSAGE_REVOKE_RECEIVE_BUFFER ++{ ++ UINT16 Id; ++} NVSP_1_MESSAGE_REVOKE_RECEIVE_BUFFER, *PNVSP_1_MESSAGE_REVOKE_RECEIVE_BUFFER; ++ ++// ++// This message is used by the VSC to send a send buffer ++// to the VSP. The VSC can then use the send buffer to ++// send data to the VSP. ++// ++typedef struct _NVSP_1_MESSAGE_SEND_SEND_BUFFER ++{ ++ GPADL_HANDLE GpadlHandle; ++ UINT16 Id; ++} NVSP_1_MESSAGE_SEND_SEND_BUFFER, *PNVSP_1_MESSAGE_SEND_SEND_BUFFER; ++ ++// ++// This message is used by the VSP to acknowledge a send ++// buffer sent by the VSC. This message must be sent by the ++// VSP before the VSP uses the sent buffer. ++// ++typedef struct _NVSP_1_MESSAGE_SEND_SEND_BUFFER_COMPLETE ++{ ++ UINT32 Status; ++ ++ // ++ // The VSC gets to choose the size of the send buffer and ++ // the VSP gets to choose the sections size of the buffer. ++ // This was done to enable dynamic reconfigurations when ++ // the cost of GPA-direct buffers decreases. ++ // ++ UINT32 SectionSize; ++} NVSP_1_MESSAGE_SEND_SEND_BUFFER_COMPLETE, *PNVSP_1_MESSAGE_SEND_SEND_BUFFER_COMPLETE; ++ ++// ++// This message is sent by the VSC to revoke the send buffer. ++// After the VSP completes this transaction, the vsp should never ++// use the send buffer again. ++// ++typedef struct _NVSP_1_MESSAGE_REVOKE_SEND_BUFFER ++{ ++ UINT16 Id; ++} NVSP_1_MESSAGE_REVOKE_SEND_BUFFER, *PNVSP_1_MESSAGE_REVOKE_SEND_BUFFER; ++ ++// ++// This message is used by both the VSP and the VSC to send ++// a RNDIS message to the opposite channel endpoint. ++// ++typedef struct _NVSP_1_MESSAGE_SEND_RNDIS_PACKET ++{ ++ // ++ // This field is specified by RNIDS. They assume there's ++ // two different channels of communication. However, ++ // the Network VSP only has one. Therefore, the channel ++ // travels with the RNDIS packet. ++ // ++ UINT32 ChannelType; ++ ++ // ++ // This field is used to send part or all of the data ++ // through a send buffer. This values specifies an ++ // index into the send buffer. If the index is ++ // 0xFFFFFFFF, then the send buffer is not being used ++ // and all of the data was sent through other VMBus ++ // mechanisms. ++ // ++ UINT32 SendBufferSectionIndex; ++ UINT32 SendBufferSectionSize; ++} NVSP_1_MESSAGE_SEND_RNDIS_PACKET, *PNVSP_1_MESSAGE_SEND_RNDIS_PACKET; ++ ++// ++// This message is used by both the VSP and the VSC to complete ++// a RNDIS message to the opposite channel endpoint. At this ++// point, the initiator of this message cannot use any resources ++// associated with the original RNDIS packet. ++// ++typedef struct _NVSP_1_MESSAGE_SEND_RNDIS_PACKET_COMPLETE ++{ ++ UINT32 Status; ++} NVSP_1_MESSAGE_SEND_RNDIS_PACKET_COMPLETE, *PNVSP_1_MESSAGE_SEND_RNDIS_PACKET_COMPLETE; ++ ++typedef union _NVSP_MESSAGE_1_UBER ++{ ++ NVSP_1_MESSAGE_SEND_NDIS_VERSION SendNdisVersion; ++ ++ NVSP_1_MESSAGE_SEND_RECEIVE_BUFFER SendReceiveBuffer; ++ NVSP_1_MESSAGE_SEND_RECEIVE_BUFFER_COMPLETE SendReceiveBufferComplete; ++ NVSP_1_MESSAGE_REVOKE_RECEIVE_BUFFER RevokeReceiveBuffer; ++ ++ NVSP_1_MESSAGE_SEND_SEND_BUFFER SendSendBuffer; ++ NVSP_1_MESSAGE_SEND_SEND_BUFFER_COMPLETE SendSendBufferComplete; ++ NVSP_1_MESSAGE_REVOKE_SEND_BUFFER RevokeSendBuffer; ++ ++ NVSP_1_MESSAGE_SEND_RNDIS_PACKET SendRNDISPacket; ++ NVSP_1_MESSAGE_SEND_RNDIS_PACKET_COMPLETE SendRNDISPacketComplete; ++} NVSP_1_MESSAGE_UBER; ++ ++typedef union _NVSP_ALL_MESSAGES ++{ ++ NVSP_MESSAGE_INIT_UBER InitMessages; ++ NVSP_1_MESSAGE_UBER Version1Messages; ++ ++} NVSP_ALL_MESSAGES; ++ ++// ++// ALL Messages ++// ++typedef struct _NVSP_MESSAGE ++{ ++ NVSP_MESSAGE_HEADER Header; ++ NVSP_ALL_MESSAGES Messages; ++} NVSP_MESSAGE, *PNVSP_MESSAGE; ++ ++#pragma pack(pop) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/osd.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/osd.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/osd.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,263 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _OSD_H_ ++#define _OSD_H_ ++ ++// ++// Defines ++// ++ ++#ifndef PAGE_SIZE ++#define PAGE_SIZE 0x1000 ++#endif ++ ++#ifndef PAGE_SHIFT ++#define PAGE_SHIFT 12 ++#endif ++ ++#ifndef memcpy ++#define memcpy __builtin_memcpy ++#endif ++ ++#ifndef memset ++#define memset __builtin_memset ++#endif ++ ++#ifndef memcmp ++#define memcmp __builtin_memcmp ++#endif ++ ++#ifndef strcpy ++#define strcpy __builtin_strcpy ++#endif ++ ++// ++//#ifndef sprintf ++//#define sprintf __builtin_sprintf ++//#endif ++ ++#define STRUCT_PACKED __attribute__((__packed__)) ++#define STRUCT_ALIGNED(x) __attribute__((__aligned__(x))) ++ ++#define UNUSED_VAR(v) v __attribute__((__unused__)) ++ ++#define ALIGN_UP(value, align) ( ((value) & (align-1))? ( ((value) + (align-1)) & ~(align-1) ): (value) ) ++#define ALIGN_DOWN(value, align) ( (value) & ~(align-1) ) ++#define NUM_PAGES_SPANNED(addr, len) ( (ALIGN_UP(addr+len, PAGE_SIZE) - ALIGN_DOWN(addr, PAGE_SIZE)) >> PAGE_SHIFT ) ++ ++#define MIN(a, b) ((a) < (b)? (a): (b)) ++#define MAX(a, b) ((a) > (b)? (a): (b)) ++ ++#define LOWORD(dw) ((unsigned short) (dw)) ++#define HIWORD(dw) ((unsigned short) (((unsigned int) (dw) >> 16) & 0xFFFF)) ++ ++#define FIELD_OFFSET(t, f) ((unsigned int)(unsigned long)&(((t *)0)->f)) ++ ++#ifdef FALSE ++#undef FALSE ++#endif ++#define FALSE 0 ++ ++#ifdef TRUE ++#undef TRUE ++#endif ++#define TRUE 1 ++ ++#ifndef NULL ++#define NULL (void *)0 ++#endif ++ ++typedef struct _DLIST_ENTRY { ++ struct _DLIST_ENTRY *Flink; ++ struct _DLIST_ENTRY *Blink; ++} DLIST_ENTRY; ++ ++// ++// unsigned types ++// ++typedef unsigned char UINT8; ++typedef unsigned short UINT16; ++typedef unsigned int UINT32; ++#ifdef __x86_64__ ++typedef unsigned long UINT64; ++#else ++typedef unsigned long long UINT64; ++#endif ++ ++typedef unsigned long long ULONGLONG; ++typedef unsigned int ULONG; ++typedef unsigned short USHORT; ++typedef unsigned char UCHAR; ++ ++// ++// signed types ++// ++typedef char INT8; ++typedef short INT16; ++typedef int INT32; ++#ifdef __x86_64__ ++typedef long INT64; ++#else ++typedef long long INT64; ++#endif ++ ++typedef int LONG; ++typedef char CHAR; ++typedef long long LONGLONG; ++ ++// ++// Other types ++// ++typedef unsigned long SIZE_T; ++typedef void VOID; ++//typedef unsigned char GUID[16]; ++typedef void* PVOID; ++typedef unsigned char BOOL; ++typedef unsigned char BOOLEAN; ++typedef void* HANDLE; ++typedef UINT32 DWORD; ++typedef char* PCHAR; ++typedef unsigned char BYTE; ++ ++typedef unsigned long ULONG_PTR; ++ ++typedef struct { ++ unsigned char Data[16]; ++} GUID; ++ ++typedef void (*PFN_WORKITEM_CALLBACK)(void* context); ++typedef void (*PFN_TIMER_CALLBACK)(void* context); ++ ++ ++#ifdef __x86_64__ ++ ++#define RDMSR(reg, v) { \ ++ UINT32 h, l; \ ++ __asm__ __volatile__("rdmsr" \ ++ : "=a" (l), "=d" (h) \ ++ : "c" (reg)); \ ++ v = (((UINT64)h) << 32) | l; \ ++} ++ ++#define WRMSR(reg, v) { \ ++ UINT32 h, l; \ ++ l = (UINT32)(((UINT64)(v)) & 0xFFFFFFFF); \ ++ h = (UINT32)((((UINT64)(v)) >> 32) & 0xFFFFFFFF); \ ++ __asm__ __volatile__("wrmsr" \ ++ : /* no outputs */ \ ++ : "c" (reg), "a" (l), "d" (h)); \ ++} ++ ++#else ++ ++#define RDMSR(reg, v) \ ++ __asm__ __volatile__("rdmsr" \ ++ : "=A" (v) \ ++ : "c" (reg)) ++ ++#define WRMSR(reg, v) \ ++ __asm__ __volatile__("wrmsr" \ ++ : /* no outputs */ \ ++ : "c" (reg), "A" ((UINT64)v)) ++ ++#endif ++ ++ ++static inline void do_cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) ++{ ++ __asm__ __volatile__("cpuid" : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (op), "c" (ecx)); ++} ++ ++// ++// Osd routines ++// ++extern void LogMsg(const char *fmt, ...); ++ ++extern void BitSet(unsigned int* addr, int value); ++extern void BitClear(unsigned int* addr, int value); ++extern int BitTest(unsigned int* addr, int value); ++extern int BitTestAndClear(unsigned int* addr, int value); ++extern int BitTestAndSet(unsigned int* addr, int value); ++ ++extern int InterlockedIncrement(int *val); ++extern int InterlockedDecrement(int *val); ++extern int InterlockedCompareExchange(int *val, int new, int curr); ++ ++extern void Sleep(unsigned long usecs); ++ ++extern void* VirtualAllocExec(unsigned int size); ++extern void VirtualFree(void* VirtAddr); ++ ++extern void* PageAlloc(unsigned int count); ++extern void PageFree(void* page, unsigned int count); ++ ++extern void* MemMapIO(unsigned long phys, unsigned long size); ++extern void MemUnmapIO(void* virt); ++ ++extern void* MemAlloc(unsigned int size); ++extern void* MemAllocZeroed(unsigned int size); ++extern void* MemAllocAtomic(unsigned int size); ++extern void MemFree(void* buf); ++extern void MemoryFence(VOID); ++ ++extern HANDLE TimerCreate(PFN_TIMER_CALLBACK pfnTimerCB, void* context); ++extern void TimerClose(HANDLE hTimer); ++extern int TimerStop(HANDLE hTimer); ++extern void TimerStart(HANDLE hTimer, UINT32 expirationInUs); ++extern SIZE_T GetTickCount(void); ++ ++extern HANDLE WaitEventCreate(void); ++extern void WaitEventClose(HANDLE hWait); ++extern void WaitEventSet(HANDLE hWait); ++extern int WaitEventWait(HANDLE hWait); ++ ++// If >0, hWait got signaled. If ==0, timeout. If < 0, error ++extern int WaitEventWaitEx(HANDLE hWait, UINT32 TimeoutInMs); ++ ++extern HANDLE SpinlockCreate(void); ++extern void SpinlockClose(HANDLE hSpin); ++extern void SpinlockAcquire(HANDLE hSpin); ++extern void SpinlockRelease(HANDLE hSpin); ++ ++ ++#define GetVirtualAddress Physical2LogicalAddr ++void* Physical2LogicalAddr(ULONG_PTR PhysAddr); ++ ++#define GetPhysicalAddress Logical2PhysicalAddr ++ULONG_PTR Logical2PhysicalAddr(PVOID LogicalAddr); ++ ++ULONG_PTR Virtual2Physical(PVOID VirtAddr); ++ ++void* PageMapVirtualAddress(unsigned long Pfn); ++void PageUnmapVirtualAddress(void* VirtAddr); ++ ++ ++extern HANDLE WorkQueueCreate(char* name); ++extern void WorkQueueClose(HANDLE hWorkQueue); ++extern int WorkQueueQueueWorkItem(HANDLE hWorkQueue, PFN_WORKITEM_CALLBACK workItem, void* context); ++ ++extern void QueueWorkItem(PFN_WORKITEM_CALLBACK workItem, void* context); ++ ++#endif // _OSD_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/rndis.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/rndis.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/rndis.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,836 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _RNDIS_H_ ++#define _RNDIS_H_ ++ ++// ++// Basic types ++// ++typedef UINT32 RNDIS_REQUEST_ID; ++typedef UINT32 RNDIS_HANDLE; ++typedef UINT32 RNDIS_STATUS; ++typedef UINT32 RNDIS_REQUEST_TYPE; ++typedef UINT32 RNDIS_OID; ++typedef UINT32 RNDIS_CLASS_ID; ++typedef UINT32 RNDIS_MEDIUM; ++typedef UINT32 *PRNDIS_REQUEST_ID; ++typedef UINT32 *PRNDIS_HANDLE; ++typedef UINT32 *PRNDIS_STATUS; ++typedef UINT32 *PRNDIS_REQUEST_TYPE; ++typedef UINT32 *PRNDIS_OID; ++typedef UINT32 *PRNDIS_CLASS_ID; ++typedef UINT32 *PRNDIS_MEDIUM; ++typedef UINT32 RNDIS_AF; ++ ++// ++// Status codes ++// ++ ++#ifndef STATUS_SUCCESS ++#define STATUS_SUCCESS (0x00000000L) ++#endif ++ ++#ifndef STATUS_UNSUCCESSFUL ++#define STATUS_UNSUCCESSFUL (0xC0000001L) ++#endif ++ ++#ifndef STATUS_PENDING ++#define STATUS_PENDING (0x00000103L) ++#endif ++ ++#ifndef STATUS_INSUFFICIENT_RESOURCES ++#define STATUS_INSUFFICIENT_RESOURCES (0xC000009AL) ++#endif ++ ++#ifndef STATUS_BUFFER_OVERFLOW ++#define STATUS_BUFFER_OVERFLOW (0x80000005L) ++#endif ++ ++#ifndef STATUS_NOT_SUPPORTED ++#define STATUS_NOT_SUPPORTED (0xC00000BBL) ++#endif ++ ++#define RNDIS_STATUS_SUCCESS ((RNDIS_STATUS)STATUS_SUCCESS) ++#define RNDIS_STATUS_PENDING ((RNDIS_STATUS)STATUS_PENDING) ++#define RNDIS_STATUS_NOT_RECOGNIZED ((RNDIS_STATUS)0x00010001L) ++#define RNDIS_STATUS_NOT_COPIED ((RNDIS_STATUS)0x00010002L) ++#define RNDIS_STATUS_NOT_ACCEPTED ((RNDIS_STATUS)0x00010003L) ++#define RNDIS_STATUS_CALL_ACTIVE ((RNDIS_STATUS)0x00010007L) ++ ++#define RNDIS_STATUS_ONLINE ((RNDIS_STATUS)0x40010003L) ++#define RNDIS_STATUS_RESET_START ((RNDIS_STATUS)0x40010004L) ++#define RNDIS_STATUS_RESET_END ((RNDIS_STATUS)0x40010005L) ++#define RNDIS_STATUS_RING_STATUS ((RNDIS_STATUS)0x40010006L) ++#define RNDIS_STATUS_CLOSED ((RNDIS_STATUS)0x40010007L) ++#define RNDIS_STATUS_WAN_LINE_UP ((RNDIS_STATUS)0x40010008L) ++#define RNDIS_STATUS_WAN_LINE_DOWN ((RNDIS_STATUS)0x40010009L) ++#define RNDIS_STATUS_WAN_FRAGMENT ((RNDIS_STATUS)0x4001000AL) ++#define RNDIS_STATUS_MEDIA_CONNECT ((RNDIS_STATUS)0x4001000BL) ++#define RNDIS_STATUS_MEDIA_DISCONNECT ((RNDIS_STATUS)0x4001000CL) ++#define RNDIS_STATUS_HARDWARE_LINE_UP ((RNDIS_STATUS)0x4001000DL) ++#define RNDIS_STATUS_HARDWARE_LINE_DOWN ((RNDIS_STATUS)0x4001000EL) ++#define RNDIS_STATUS_INTERFACE_UP ((RNDIS_STATUS)0x4001000FL) ++#define RNDIS_STATUS_INTERFACE_DOWN ((RNDIS_STATUS)0x40010010L) ++#define RNDIS_STATUS_MEDIA_BUSY ((RNDIS_STATUS)0x40010011L) ++#define RNDIS_STATUS_MEDIA_SPECIFIC_INDICATION ((RNDIS_STATUS)0x40010012L) ++#define RNDIS_STATUS_WW_INDICATION RNDIS_STATUS_MEDIA_SPECIFIC_INDICATION ++#define RNDIS_STATUS_LINK_SPEED_CHANGE ((RNDIS_STATUS)0x40010013L) ++ ++#define RNDIS_STATUS_NOT_RESETTABLE ((RNDIS_STATUS)0x80010001L) ++#define RNDIS_STATUS_SOFT_ERRORS ((RNDIS_STATUS)0x80010003L) ++#define RNDIS_STATUS_HARD_ERRORS ((RNDIS_STATUS)0x80010004L) ++#define RNDIS_STATUS_BUFFER_OVERFLOW ((RNDIS_STATUS)STATUS_BUFFER_OVERFLOW) ++ ++#define RNDIS_STATUS_FAILURE ((RNDIS_STATUS)STATUS_UNSUCCESSFUL) ++#define RNDIS_STATUS_RESOURCES ((RNDIS_STATUS)STATUS_INSUFFICIENT_RESOURCES) ++#define RNDIS_STATUS_CLOSING ((RNDIS_STATUS)0xC0010002L) ++#define RNDIS_STATUS_BAD_VERSION ((RNDIS_STATUS)0xC0010004L) ++#define RNDIS_STATUS_BAD_CHARACTERISTICS ((RNDIS_STATUS)0xC0010005L) ++#define RNDIS_STATUS_ADAPTER_NOT_FOUND ((RNDIS_STATUS)0xC0010006L) ++#define RNDIS_STATUS_OPEN_FAILED ((RNDIS_STATUS)0xC0010007L) ++#define RNDIS_STATUS_DEVICE_FAILED ((RNDIS_STATUS)0xC0010008L) ++#define RNDIS_STATUS_MULTICAST_FULL ((RNDIS_STATUS)0xC0010009L) ++#define RNDIS_STATUS_MULTICAST_EXISTS ((RNDIS_STATUS)0xC001000AL) ++#define RNDIS_STATUS_MULTICAST_NOT_FOUND ((RNDIS_STATUS)0xC001000BL) ++#define RNDIS_STATUS_REQUEST_ABORTED ((RNDIS_STATUS)0xC001000CL) ++#define RNDIS_STATUS_RESET_IN_PROGRESS ((RNDIS_STATUS)0xC001000DL) ++#define RNDIS_STATUS_CLOSING_INDICATING ((RNDIS_STATUS)0xC001000EL) ++#define RNDIS_STATUS_NOT_SUPPORTED ((RNDIS_STATUS)STATUS_NOT_SUPPORTED) ++#define RNDIS_STATUS_INVALID_PACKET ((RNDIS_STATUS)0xC001000FL) ++#define RNDIS_STATUS_OPEN_LIST_FULL ((RNDIS_STATUS)0xC0010010L) ++#define RNDIS_STATUS_ADAPTER_NOT_READY ((RNDIS_STATUS)0xC0010011L) ++#define RNDIS_STATUS_ADAPTER_NOT_OPEN ((RNDIS_STATUS)0xC0010012L) ++#define RNDIS_STATUS_NOT_INDICATING ((RNDIS_STATUS)0xC0010013L) ++#define RNDIS_STATUS_INVALID_LENGTH ((RNDIS_STATUS)0xC0010014L) ++#define RNDIS_STATUS_INVALID_DATA ((RNDIS_STATUS)0xC0010015L) ++#define RNDIS_STATUS_BUFFER_TOO_SHORT ((RNDIS_STATUS)0xC0010016L) ++#define RNDIS_STATUS_INVALID_OID ((RNDIS_STATUS)0xC0010017L) ++#define RNDIS_STATUS_ADAPTER_REMOVED ((RNDIS_STATUS)0xC0010018L) ++#define RNDIS_STATUS_UNSUPPORTED_MEDIA ((RNDIS_STATUS)0xC0010019L) ++#define RNDIS_STATUS_GROUP_ADDRESS_IN_USE ((RNDIS_STATUS)0xC001001AL) ++#define RNDIS_STATUS_FILE_NOT_FOUND ((RNDIS_STATUS)0xC001001BL) ++#define RNDIS_STATUS_ERROR_READING_FILE ((RNDIS_STATUS)0xC001001CL) ++#define RNDIS_STATUS_ALREADY_MAPPED ((RNDIS_STATUS)0xC001001DL) ++#define RNDIS_STATUS_RESOURCE_CONFLICT ((RNDIS_STATUS)0xC001001EL) ++#define RNDIS_STATUS_NO_CABLE ((RNDIS_STATUS)0xC001001FL) ++ ++#define RNDIS_STATUS_INVALID_SAP ((RNDIS_STATUS)0xC0010020L) ++#define RNDIS_STATUS_SAP_IN_USE ((RNDIS_STATUS)0xC0010021L) ++#define RNDIS_STATUS_INVALID_ADDRESS ((RNDIS_STATUS)0xC0010022L) ++#define RNDIS_STATUS_VC_NOT_ACTIVATED ((RNDIS_STATUS)0xC0010023L) ++#define RNDIS_STATUS_DEST_OUT_OF_ORDER ((RNDIS_STATUS)0xC0010024L) ++#define RNDIS_STATUS_VC_NOT_AVAILABLE ((RNDIS_STATUS)0xC0010025L) ++#define RNDIS_STATUS_CELLRATE_NOT_AVAILABLE ((RNDIS_STATUS)0xC0010026L) ++#define RNDIS_STATUS_INCOMPATABLE_QOS ((RNDIS_STATUS)0xC0010027L) ++#define RNDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((RNDIS_STATUS)0xC0010028L) ++#define RNDIS_STATUS_NO_ROUTE_TO_DESTINATION ((RNDIS_STATUS)0xC0010029L) ++ ++#define RNDIS_STATUS_TOKEN_RING_OPEN_ERROR ((RNDIS_STATUS)0xC0011000L) ++ ++ ++// ++// Object Identifiers used by NdisRequest Query/Set Information ++// ++ ++// ++// General Objects ++// ++ ++#define RNDIS_OID_GEN_SUPPORTED_LIST 0x00010101 ++#define RNDIS_OID_GEN_HARDWARE_STATUS 0x00010102 ++#define RNDIS_OID_GEN_MEDIA_SUPPORTED 0x00010103 ++#define RNDIS_OID_GEN_MEDIA_IN_USE 0x00010104 ++#define RNDIS_OID_GEN_MAXIMUM_LOOKAHEAD 0x00010105 ++#define RNDIS_OID_GEN_MAXIMUM_FRAME_SIZE 0x00010106 ++#define RNDIS_OID_GEN_LINK_SPEED 0x00010107 ++#define RNDIS_OID_GEN_TRANSMIT_BUFFER_SPACE 0x00010108 ++#define RNDIS_OID_GEN_RECEIVE_BUFFER_SPACE 0x00010109 ++#define RNDIS_OID_GEN_TRANSMIT_BLOCK_SIZE 0x0001010A ++#define RNDIS_OID_GEN_RECEIVE_BLOCK_SIZE 0x0001010B ++#define RNDIS_OID_GEN_VENDOR_ID 0x0001010C ++#define RNDIS_OID_GEN_VENDOR_DESCRIPTION 0x0001010D ++#define RNDIS_OID_GEN_CURRENT_PACKET_FILTER 0x0001010E ++#define RNDIS_OID_GEN_CURRENT_LOOKAHEAD 0x0001010F ++#define RNDIS_OID_GEN_DRIVER_VERSION 0x00010110 ++#define RNDIS_OID_GEN_MAXIMUM_TOTAL_SIZE 0x00010111 ++#define RNDIS_OID_GEN_PROTOCOL_OPTIONS 0x00010112 ++#define RNDIS_OID_GEN_MAC_OPTIONS 0x00010113 ++#define RNDIS_OID_GEN_MEDIA_CONNECT_STATUS 0x00010114 ++#define RNDIS_OID_GEN_MAXIMUM_SEND_PACKETS 0x00010115 ++#define RNDIS_OID_GEN_VENDOR_DRIVER_VERSION 0x00010116 ++#define RNDIS_OID_GEN_NETWORK_LAYER_ADDRESSES 0x00010118 ++#define RNDIS_OID_GEN_TRANSPORT_HEADER_OFFSET 0x00010119 ++#define RNDIS_OID_GEN_MACHINE_NAME 0x0001021A ++#define RNDIS_OID_GEN_RNDIS_CONFIG_PARAMETER 0x0001021B ++ ++#define RNDIS_OID_GEN_XMIT_OK 0x00020101 ++#define RNDIS_OID_GEN_RCV_OK 0x00020102 ++#define RNDIS_OID_GEN_XMIT_ERROR 0x00020103 ++#define RNDIS_OID_GEN_RCV_ERROR 0x00020104 ++#define RNDIS_OID_GEN_RCV_NO_BUFFER 0x00020105 ++ ++#define RNDIS_OID_GEN_DIRECTED_BYTES_XMIT 0x00020201 ++#define RNDIS_OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202 ++#define RNDIS_OID_GEN_MULTICAST_BYTES_XMIT 0x00020203 ++#define RNDIS_OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204 ++#define RNDIS_OID_GEN_BROADCAST_BYTES_XMIT 0x00020205 ++#define RNDIS_OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206 ++#define RNDIS_OID_GEN_DIRECTED_BYTES_RCV 0x00020207 ++#define RNDIS_OID_GEN_DIRECTED_FRAMES_RCV 0x00020208 ++#define RNDIS_OID_GEN_MULTICAST_BYTES_RCV 0x00020209 ++#define RNDIS_OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A ++#define RNDIS_OID_GEN_BROADCAST_BYTES_RCV 0x0002020B ++#define RNDIS_OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C ++ ++#define RNDIS_OID_GEN_RCV_CRC_ERROR 0x0002020D ++#define RNDIS_OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E ++ ++#define RNDIS_OID_GEN_GET_TIME_CAPS 0x0002020F ++#define RNDIS_OID_GEN_GET_NETCARD_TIME 0x00020210 ++ ++// ++// These are connection-oriented general OIDs. ++// These replace the above OIDs for connection-oriented media. ++// ++#define RNDIS_OID_GEN_CO_SUPPORTED_LIST 0x00010101 ++#define RNDIS_OID_GEN_CO_HARDWARE_STATUS 0x00010102 ++#define RNDIS_OID_GEN_CO_MEDIA_SUPPORTED 0x00010103 ++#define RNDIS_OID_GEN_CO_MEDIA_IN_USE 0x00010104 ++#define RNDIS_OID_GEN_CO_LINK_SPEED 0x00010105 ++#define RNDIS_OID_GEN_CO_VENDOR_ID 0x00010106 ++#define RNDIS_OID_GEN_CO_VENDOR_DESCRIPTION 0x00010107 ++#define RNDIS_OID_GEN_CO_DRIVER_VERSION 0x00010108 ++#define RNDIS_OID_GEN_CO_PROTOCOL_OPTIONS 0x00010109 ++#define RNDIS_OID_GEN_CO_MAC_OPTIONS 0x0001010A ++#define RNDIS_OID_GEN_CO_MEDIA_CONNECT_STATUS 0x0001010B ++#define RNDIS_OID_GEN_CO_VENDOR_DRIVER_VERSION 0x0001010C ++#define RNDIS_OID_GEN_CO_MINIMUM_LINK_SPEED 0x0001010D ++ ++#define RNDIS_OID_GEN_CO_GET_TIME_CAPS 0x00010201 ++#define RNDIS_OID_GEN_CO_GET_NETCARD_TIME 0x00010202 ++ ++// ++// These are connection-oriented statistics OIDs. ++// ++#define RNDIS_OID_GEN_CO_XMIT_PDUS_OK 0x00020101 ++#define RNDIS_OID_GEN_CO_RCV_PDUS_OK 0x00020102 ++#define RNDIS_OID_GEN_CO_XMIT_PDUS_ERROR 0x00020103 ++#define RNDIS_OID_GEN_CO_RCV_PDUS_ERROR 0x00020104 ++#define RNDIS_OID_GEN_CO_RCV_PDUS_NO_BUFFER 0x00020105 ++ ++ ++#define RNDIS_OID_GEN_CO_RCV_CRC_ERROR 0x00020201 ++#define RNDIS_OID_GEN_CO_TRANSMIT_QUEUE_LENGTH 0x00020202 ++#define RNDIS_OID_GEN_CO_BYTES_XMIT 0x00020203 ++#define RNDIS_OID_GEN_CO_BYTES_RCV 0x00020204 ++#define RNDIS_OID_GEN_CO_BYTES_XMIT_OUTSTANDING 0x00020205 ++#define RNDIS_OID_GEN_CO_NETCARD_LOAD 0x00020206 ++ ++// ++// These are objects for Connection-oriented media call-managers. ++// ++#define RNDIS_OID_CO_ADD_PVC 0xFF000001 ++#define RNDIS_OID_CO_DELETE_PVC 0xFF000002 ++#define RNDIS_OID_CO_GET_CALL_INFORMATION 0xFF000003 ++#define RNDIS_OID_CO_ADD_ADDRESS 0xFF000004 ++#define RNDIS_OID_CO_DELETE_ADDRESS 0xFF000005 ++#define RNDIS_OID_CO_GET_ADDRESSES 0xFF000006 ++#define RNDIS_OID_CO_ADDRESS_CHANGE 0xFF000007 ++#define RNDIS_OID_CO_SIGNALING_ENABLED 0xFF000008 ++#define RNDIS_OID_CO_SIGNALING_DISABLED 0xFF000009 ++ ++ ++// ++// 802.3 Objects (Ethernet) ++// ++ ++#define RNDIS_OID_802_3_PERMANENT_ADDRESS 0x01010101 ++#define RNDIS_OID_802_3_CURRENT_ADDRESS 0x01010102 ++#define RNDIS_OID_802_3_MULTICAST_LIST 0x01010103 ++#define RNDIS_OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 ++#define RNDIS_OID_802_3_MAC_OPTIONS 0x01010105 ++ ++// ++// ++#define NDIS_802_3_MAC_OPTION_PRIORITY 0x00000001 ++ ++#define RNDIS_OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101 ++#define RNDIS_OID_802_3_XMIT_ONE_COLLISION 0x01020102 ++#define RNDIS_OID_802_3_XMIT_MORE_COLLISIONS 0x01020103 ++ ++#define RNDIS_OID_802_3_XMIT_DEFERRED 0x01020201 ++#define RNDIS_OID_802_3_XMIT_MAX_COLLISIONS 0x01020202 ++#define RNDIS_OID_802_3_RCV_OVERRUN 0x01020203 ++#define RNDIS_OID_802_3_XMIT_UNDERRUN 0x01020204 ++#define RNDIS_OID_802_3_XMIT_HEARTBEAT_FAILURE 0x01020205 ++#define RNDIS_OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206 ++#define RNDIS_OID_802_3_XMIT_LATE_COLLISIONS 0x01020207 ++ ++ ++// ++// Remote NDIS message types ++// ++#define REMOTE_NDIS_PACKET_MSG 0x00000001 ++#define REMOTE_NDIS_INITIALIZE_MSG 0x00000002 ++#define REMOTE_NDIS_HALT_MSG 0x00000003 ++#define REMOTE_NDIS_QUERY_MSG 0x00000004 ++#define REMOTE_NDIS_SET_MSG 0x00000005 ++#define REMOTE_NDIS_RESET_MSG 0x00000006 ++#define REMOTE_NDIS_INDICATE_STATUS_MSG 0x00000007 ++#define REMOTE_NDIS_KEEPALIVE_MSG 0x00000008 ++ ++#define REMOTE_CONDIS_MP_CREATE_VC_MSG 0x00008001 ++#define REMOTE_CONDIS_MP_DELETE_VC_MSG 0x00008002 ++#define REMOTE_CONDIS_MP_ACTIVATE_VC_MSG 0x00008005 ++#define REMOTE_CONDIS_MP_DEACTIVATE_VC_MSG 0x00008006 ++#define REMOTE_CONDIS_INDICATE_STATUS_MSG 0x00008007 ++ ++ ++// Remote NDIS message completion types ++#define REMOTE_NDIS_INITIALIZE_CMPLT 0x80000002 ++#define REMOTE_NDIS_QUERY_CMPLT 0x80000004 ++#define REMOTE_NDIS_SET_CMPLT 0x80000005 ++#define REMOTE_NDIS_RESET_CMPLT 0x80000006 ++#define REMOTE_NDIS_KEEPALIVE_CMPLT 0x80000008 ++ ++#define REMOTE_CONDIS_MP_CREATE_VC_CMPLT 0x80008001 ++#define REMOTE_CONDIS_MP_DELETE_VC_CMPLT 0x80008002 ++#define REMOTE_CONDIS_MP_ACTIVATE_VC_CMPLT 0x80008005 ++#define REMOTE_CONDIS_MP_DEACTIVATE_VC_CMPLT 0x80008006 ++ ++// ++// Reserved message type for private communication between lower-layer ++// host driver and remote device, if necessary. ++// ++#define REMOTE_NDIS_BUS_MSG 0xff000001 ++ ++ ++ ++// ++// Defines for DeviceFlags in RNDIS_INITIALIZE_COMPLETE ++// ++#define RNDIS_DF_CONNECTIONLESS 0x00000001 ++#define RNDIS_DF_CONNECTION_ORIENTED 0x00000002 ++#define RNDIS_DF_RAW_DATA 0x00000004 ++ ++// ++// Remote NDIS medium types. ++// ++#define RNdisMedium802_3 0x00000000 ++#define RNdisMedium802_5 0x00000001 ++#define RNdisMediumFddi 0x00000002 ++#define RNdisMediumWan 0x00000003 ++#define RNdisMediumLocalTalk 0x00000004 ++#define RNdisMediumArcnetRaw 0x00000006 ++#define RNdisMediumArcnet878_2 0x00000007 ++#define RNdisMediumAtm 0x00000008 ++#define RNdisMediumWirelessWan 0x00000009 ++#define RNdisMediumIrda 0x0000000a ++#define RNdisMediumCoWan 0x0000000b ++#define RNdisMediumMax 0x0000000d // Not a real medium, defined as an upper-bound ++ ++// ++// Remote NDIS medium connection states. ++// ++#define RNdisMediaStateConnected 0x00000000 ++#define RNdisMediaStateDisconnected 0x00000001 ++ ++// ++// Remote NDIS version numbers ++// ++#define RNDIS_MAJOR_VERSION 0x00000001 ++#define RNDIS_MINOR_VERSION 0x00000000 ++ ++// ++// NdisInitialize message ++// ++typedef struct _RNDIS_INITIALIZE_REQUEST ++{ ++ RNDIS_REQUEST_ID RequestId; ++ UINT32 MajorVersion; ++ UINT32 MinorVersion; ++ UINT32 MaxTransferSize; ++} RNDIS_INITIALIZE_REQUEST, *PRNDIS_INITIALIZE_REQUEST; ++ ++ ++// ++// Response to NdisInitialize ++// ++typedef struct _RNDIS_INITIALIZE_COMPLETE ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_STATUS Status; ++ UINT32 MajorVersion; ++ UINT32 MinorVersion; ++ UINT32 DeviceFlags; ++ RNDIS_MEDIUM Medium; ++ UINT32 MaxPacketsPerMessage; ++ UINT32 MaxTransferSize; ++ UINT32 PacketAlignmentFactor; ++ UINT32 AFListOffset; ++ UINT32 AFListSize; ++} RNDIS_INITIALIZE_COMPLETE, *PRNDIS_INITIALIZE_COMPLETE; ++ ++ ++// ++// Call manager devices only: Information about an address family ++// supported by the device is appended to the response to NdisInitialize. ++// ++typedef struct _RNDIS_CO_ADDRESS_FAMILY ++{ ++ RNDIS_AF AddressFamily; ++ UINT32 MajorVersion; ++ UINT32 MinorVersion; ++} RNDIS_CO_ADDRESS_FAMILY, *PRNDIS_CO_ADDRESS_FAMILY; ++ ++ ++// ++// NdisHalt message ++// ++typedef struct _RNDIS_HALT_REQUEST ++{ ++ RNDIS_REQUEST_ID RequestId; ++} RNDIS_HALT_REQUEST, *PRNDIS_HALT_REQUEST; ++ ++ ++// ++// NdisQueryRequest message ++// ++typedef struct _RNDIS_QUERY_REQUEST ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_OID Oid; ++ UINT32 InformationBufferLength; ++ UINT32 InformationBufferOffset; ++ RNDIS_HANDLE DeviceVcHandle; ++} RNDIS_QUERY_REQUEST, *PRNDIS_QUERY_REQUEST; ++ ++ ++// ++// Response to NdisQueryRequest ++// ++typedef struct _RNDIS_QUERY_COMPLETE ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_STATUS Status; ++ UINT32 InformationBufferLength; ++ UINT32 InformationBufferOffset; ++} RNDIS_QUERY_COMPLETE, *PRNDIS_QUERY_COMPLETE; ++ ++ ++// ++// NdisSetRequest message ++// ++typedef struct _RNDIS_SET_REQUEST ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_OID Oid; ++ UINT32 InformationBufferLength; ++ UINT32 InformationBufferOffset; ++ RNDIS_HANDLE DeviceVcHandle; ++} RNDIS_SET_REQUEST, *PRNDIS_SET_REQUEST; ++ ++ ++// ++// Response to NdisSetRequest ++// ++typedef struct _RNDIS_SET_COMPLETE ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_STATUS Status; ++} RNDIS_SET_COMPLETE, *PRNDIS_SET_COMPLETE; ++ ++ ++// ++// NdisReset message ++// ++typedef struct _RNDIS_RESET_REQUEST ++{ ++ UINT32 Reserved; ++} RNDIS_RESET_REQUEST, *PRNDIS_RESET_REQUEST; ++ ++// ++// Response to NdisReset ++// ++typedef struct _RNDIS_RESET_COMPLETE ++{ ++ RNDIS_STATUS Status; ++ UINT32 AddressingReset; ++} RNDIS_RESET_COMPLETE, *PRNDIS_RESET_COMPLETE; ++ ++ ++// ++// NdisMIndicateStatus message ++// ++typedef struct _RNDIS_INDICATE_STATUS ++{ ++ RNDIS_STATUS Status; ++ UINT32 StatusBufferLength; ++ UINT32 StatusBufferOffset; ++} RNDIS_INDICATE_STATUS, *PRNDIS_INDICATE_STATUS; ++ ++ ++// ++// Diagnostic information passed as the status buffer in ++// RNDIS_INDICATE_STATUS messages signifying error conditions. ++// ++typedef struct _RNDIS_DIAGNOSTIC_INFO ++{ ++ RNDIS_STATUS DiagStatus; ++ UINT32 ErrorOffset; ++} RNDIS_DIAGNOSTIC_INFO, *PRNDIS_DIAGNOSTIC_INFO; ++ ++ ++ ++// ++// NdisKeepAlive message ++// ++typedef struct _RNDIS_KEEPALIVE_REQUEST ++{ ++ RNDIS_REQUEST_ID RequestId; ++} RNDIS_KEEPALIVE_REQUEST, *PRNDIS_KEEPALIVE_REQUEST; ++ ++ ++// ++// Response to NdisKeepAlive ++// ++typedef struct _RNDIS_KEEPALIVE_COMPLETE ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_STATUS Status; ++} RNDIS_KEEPALIVE_COMPLETE, *PRNDIS_KEEPALIVE_COMPLETE; ++ ++ ++// ++// Data message. All Offset fields contain byte offsets from the beginning ++// of the RNDIS_PACKET structure. All Length fields are in bytes. ++// VcHandle is set to 0 for connectionless data, otherwise it ++// contains the VC handle. ++// ++typedef struct _RNDIS_PACKET ++{ ++ UINT32 DataOffset; ++ UINT32 DataLength; ++ UINT32 OOBDataOffset; ++ UINT32 OOBDataLength; ++ UINT32 NumOOBDataElements; ++ UINT32 PerPacketInfoOffset; ++ UINT32 PerPacketInfoLength; ++ RNDIS_HANDLE VcHandle; ++ UINT32 Reserved; ++} RNDIS_PACKET, *PRNDIS_PACKET; ++ ++// ++// Optional Out of Band data associated with a Data message. ++// ++typedef struct _RNDIS_OOBD ++{ ++ UINT32 Size; ++ RNDIS_CLASS_ID Type; ++ UINT32 ClassInformationOffset; ++} RNDIS_OOBD, *PRNDIS_OOBD; ++ ++// ++// Packet extension field contents associated with a Data message. ++// ++typedef struct _RNDIS_PER_PACKET_INFO ++{ ++ UINT32 Size; ++ UINT32 Type; ++ UINT32 PerPacketInformationOffset; ++} RNDIS_PER_PACKET_INFO, *PRNDIS_PER_PACKET_INFO; ++ ++ ++// ++// Format of Information buffer passed in a SetRequest for the OID ++// OID_GEN_RNDIS_CONFIG_PARAMETER. ++// ++typedef struct _RNDIS_CONFIG_PARAMETER_INFO ++{ ++ UINT32 ParameterNameOffset; ++ UINT32 ParameterNameLength; ++ UINT32 ParameterType; ++ UINT32 ParameterValueOffset; ++ UINT32 ParameterValueLength; ++} RNDIS_CONFIG_PARAMETER_INFO, *PRNDIS_CONFIG_PARAMETER_INFO; ++ ++// ++// Values for ParameterType in RNDIS_CONFIG_PARAMETER_INFO ++// ++#define RNDIS_CONFIG_PARAM_TYPE_INTEGER 0 ++#define RNDIS_CONFIG_PARAM_TYPE_STRING 2 ++ ++ ++// ++// CONDIS Miniport messages for connection oriented devices ++// that do not implement a call manager. ++// ++ ++// ++// CoNdisMiniportCreateVc message ++// ++typedef struct _RCONDIS_MP_CREATE_VC ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_HANDLE NdisVcHandle; ++} RCONDIS_MP_CREATE_VC, *PRCONDIS_MP_CREATE_VC; ++ ++// ++// Response to CoNdisMiniportCreateVc ++// ++typedef struct _RCONDIS_MP_CREATE_VC_COMPLETE ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_HANDLE DeviceVcHandle; ++ RNDIS_STATUS Status; ++} RCONDIS_MP_CREATE_VC_COMPLETE, *PRCONDIS_MP_CREATE_VC_COMPLETE; ++ ++ ++// ++// CoNdisMiniportDeleteVc message ++// ++typedef struct _RCONDIS_MP_DELETE_VC ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_HANDLE DeviceVcHandle; ++} RCONDIS_MP_DELETE_VC, *PRCONDIS_MP_DELETE_VC; ++ ++// ++// Response to CoNdisMiniportDeleteVc ++// ++typedef struct _RCONDIS_MP_DELETE_VC_COMPLETE ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_STATUS Status; ++} RCONDIS_MP_DELETE_VC_COMPLETE, *PRCONDIS_MP_DELETE_VC_COMPLETE; ++ ++ ++// ++// CoNdisMiniportQueryRequest message ++// ++typedef struct _RCONDIS_MP_QUERY_REQUEST ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_REQUEST_TYPE RequestType; ++ RNDIS_OID Oid; ++ RNDIS_HANDLE DeviceVcHandle; ++ UINT32 InformationBufferLength; ++ UINT32 InformationBufferOffset; ++} RCONDIS_MP_QUERY_REQUEST, *PRCONDIS_MP_QUERY_REQUEST; ++ ++ ++// ++// CoNdisMiniportSetRequest message ++// ++typedef struct _RCONDIS_MP_SET_REQUEST ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_REQUEST_TYPE RequestType; ++ RNDIS_OID Oid; ++ RNDIS_HANDLE DeviceVcHandle; ++ UINT32 InformationBufferLength; ++ UINT32 InformationBufferOffset; ++} RCONDIS_MP_SET_REQUEST, *PRCONDIS_MP_SET_REQUEST; ++ ++ ++// ++// CoNdisIndicateStatus message ++// ++typedef struct _RCONDIS_INDICATE_STATUS ++{ ++ RNDIS_HANDLE NdisVcHandle; ++ RNDIS_STATUS Status; ++ UINT32 StatusBufferLength; ++ UINT32 StatusBufferOffset; ++} RCONDIS_INDICATE_STATUS, *PRCONDIS_INDICATE_STATUS; ++ ++ ++// ++// CONDIS Call/VC parameters ++// ++ ++typedef struct _RCONDIS_SPECIFIC_PARAMETERS ++{ ++ UINT32 ParameterType; ++ UINT32 ParameterLength; ++ UINT32 ParameterOffset; ++} RCONDIS_SPECIFIC_PARAMETERS, *PRCONDIS_SPECIFIC_PARAMETERS; ++ ++typedef struct _RCONDIS_MEDIA_PARAMETERS ++{ ++ UINT32 Flags; ++ UINT32 Reserved1; ++ UINT32 Reserved2; ++ RCONDIS_SPECIFIC_PARAMETERS MediaSpecific; ++} RCONDIS_MEDIA_PARAMETERS, *PRCONDIS_MEDIA_PARAMETERS; ++ ++ ++typedef struct _RNDIS_FLOWSPEC ++{ ++ UINT32 TokenRate; ++ UINT32 TokenBucketSize; ++ UINT32 PeakBandwidth; ++ UINT32 Latency; ++ UINT32 DelayVariation; ++ UINT32 ServiceType; ++ UINT32 MaxSduSize; ++ UINT32 MinimumPolicedSize; ++} RNDIS_FLOWSPEC, *PRNDIS_FLOWSPEC; ++ ++typedef struct _RCONDIS_CALL_MANAGER_PARAMETERS ++{ ++ RNDIS_FLOWSPEC Transmit; ++ RNDIS_FLOWSPEC Receive; ++ RCONDIS_SPECIFIC_PARAMETERS CallMgrSpecific; ++} RCONDIS_CALL_MANAGER_PARAMETERS, *PRCONDIS_CALL_MANAGER_PARAMETERS; ++ ++// ++// CoNdisMiniportActivateVc message ++// ++typedef struct _RCONDIS_MP_ACTIVATE_VC_REQUEST ++{ ++ RNDIS_REQUEST_ID RequestId; ++ UINT32 Flags; ++ RNDIS_HANDLE DeviceVcHandle; ++ UINT32 MediaParamsOffset; ++ UINT32 MediaParamsLength; ++ UINT32 CallMgrParamsOffset; ++ UINT32 CallMgrParamsLength; ++} RCONDIS_MP_ACTIVATE_VC_REQUEST, *PRCONDIS_MP_ACTIVATE_VC_REQUEST; ++ ++// ++// Response to CoNdisMiniportActivateVc ++// ++typedef struct _RCONDIS_MP_ACTIVATE_VC_COMPLETE ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_STATUS Status; ++} RCONDIS_MP_ACTIVATE_VC_COMPLETE, *PRCONDIS_MP_ACTIVATE_VC_COMPLETE; ++ ++ ++// ++// CoNdisMiniportDeactivateVc message ++// ++typedef struct _RCONDIS_MP_DEACTIVATE_VC_REQUEST ++{ ++ RNDIS_REQUEST_ID RequestId; ++ UINT32 Flags; ++ RNDIS_HANDLE DeviceVcHandle; ++} RCONDIS_MP_DEACTIVATE_VC_REQUEST, *PRCONDIS_MP_DEACTIVATE_VC_REQUEST; ++ ++// ++// Response to CoNdisMiniportDeactivateVc ++// ++typedef struct _RCONDIS_MP_DEACTIVATE_VC_COMPLETE ++{ ++ RNDIS_REQUEST_ID RequestId; ++ RNDIS_STATUS Status; ++} RCONDIS_MP_DEACTIVATE_VC_COMPLETE, *PRCONDIS_MP_DEACTIVATE_VC_COMPLETE; ++ ++ ++// ++// union with all of the RNDIS messages ++// ++typedef union _RNDIS_MESSAGE_CONTAINER ++{ ++ RNDIS_PACKET Packet; ++ RNDIS_INITIALIZE_REQUEST InitializeRequest; ++ RNDIS_HALT_REQUEST HaltRequest; ++ RNDIS_QUERY_REQUEST QueryRequest; ++ RNDIS_SET_REQUEST SetRequest; ++ RNDIS_RESET_REQUEST ResetRequest; ++ RNDIS_KEEPALIVE_REQUEST KeepaliveRequest; ++ RNDIS_INDICATE_STATUS IndicateStatus; ++ RNDIS_INITIALIZE_COMPLETE InitializeComplete; ++ RNDIS_QUERY_COMPLETE QueryComplete; ++ RNDIS_SET_COMPLETE SetComplete; ++ RNDIS_RESET_COMPLETE ResetComplete; ++ RNDIS_KEEPALIVE_COMPLETE KeepaliveComplete; ++ RCONDIS_MP_CREATE_VC CoMiniportCreateVc; ++ RCONDIS_MP_DELETE_VC CoMiniportDeleteVc; ++ RCONDIS_INDICATE_STATUS CoIndicateStatus; ++ RCONDIS_MP_ACTIVATE_VC_REQUEST CoMiniportActivateVc; ++ RCONDIS_MP_DEACTIVATE_VC_REQUEST CoMiniportDeactivateVc; ++ RCONDIS_MP_CREATE_VC_COMPLETE CoMiniportCreateVcComplete; ++ RCONDIS_MP_DELETE_VC_COMPLETE CoMiniportDeleteVcComplete; ++ RCONDIS_MP_ACTIVATE_VC_COMPLETE CoMiniportActivateVcComplete; ++ RCONDIS_MP_DEACTIVATE_VC_COMPLETE CoMiniportDeactivateVcComplete; ++ ++ ++} RNDIS_MESSAGE_CONTAINER, *PRNDIS_MESSAGE_CONTAINER; ++ ++// ++// Remote NDIS message format ++// ++typedef __struct_bcount(MessageLength) struct _RNDIS_MESSAGE ++{ ++ UINT32 NdisMessageType; ++ ++ // ++ // Total length of this message, from the beginning ++ // of the RNDIS_MESSAGE struct, in bytes. ++ // ++ UINT32 MessageLength; ++ ++ // Actual message ++ RNDIS_MESSAGE_CONTAINER Message; ++ ++} RNDIS_MESSAGE, *PRNDIS_MESSAGE; ++ ++ ++ ++// ++// Handy macros ++ ++// get the size of an RNDIS message. Pass in the message type, ++// RNDIS_SET_REQUEST, RNDIS_PACKET for example ++#define RNDIS_MESSAGE_SIZE(Message) \ ++ (sizeof(Message) + (sizeof(RNDIS_MESSAGE) - sizeof(RNDIS_MESSAGE_CONTAINER))) ++ ++// get pointer to info buffer with message pointer ++#define MESSAGE_TO_INFO_BUFFER(Message) \ ++ (((PUCHAR)(Message)) + Message->InformationBufferOffset) ++ ++// get pointer to status buffer with message pointer ++#define MESSAGE_TO_STATUS_BUFFER(Message) \ ++ (((PUCHAR)(Message)) + Message->StatusBufferOffset) ++ ++// get pointer to OOBD buffer with message pointer ++#define MESSAGE_TO_OOBD_BUFFER(Message) \ ++ (((PUCHAR)(Message)) + Message->OOBDataOffset) ++ ++// get pointer to data buffer with message pointer ++#define MESSAGE_TO_DATA_BUFFER(Message) \ ++ (((PUCHAR)(Message)) + Message->PerPacketInfoOffset) ++ ++// get pointer to contained message from NDIS_MESSAGE pointer ++#define RNDIS_MESSAGE_PTR_TO_MESSAGE_PTR(RndisMessage) \ ++ ((PVOID) &RndisMessage->Message) ++ ++// get pointer to contained message from NDIS_MESSAGE pointer ++#define RNDIS_MESSAGE_RAW_PTR_TO_MESSAGE_PTR(RndisMessage) \ ++ ((PVOID) RndisMessage) ++ ++#endif // _RNDIS_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/StorVscApi.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/StorVscApi.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/StorVscApi.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,137 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _STORVSC_API_H_ ++#define _STORVSC_API_H_ ++ ++#include "VmbusApi.h" ++ ++// ++// Defines ++// ++ ++#define STORVSC_RING_BUFFER_SIZE 10*PAGE_SIZE ++#define BLKVSC_RING_BUFFER_SIZE 20*PAGE_SIZE ++ ++#define STORVSC_MAX_IO_REQUESTS 64 ++ ++// In Hyper-V, each port/path/target maps to 1 scsi host adapter. ++// In reality, the path/target is not used (ie always set to 0) so ++// our scsi host adapter essentially has 1 bus with 1 target that contains ++// up to 256 luns. ++ ++#define STORVSC_MAX_LUNS_PER_TARGET 64 ++#define STORVSC_MAX_TARGETS 1 ++#define STORVSC_MAX_CHANNELS 1 ++ ++ ++// Fwd decl ++// ++//struct VMBUS_CHANNEL; ++typedef struct _STORVSC_REQUEST* PSTORVSC_REQUEST; ++ ++// ++// Data types ++// ++typedef int (*PFN_ON_IO_REQUEST)(PDEVICE_OBJECT Device, PSTORVSC_REQUEST Request); ++typedef void (*PFN_ON_IO_REQUEST_COMPLTN)(PSTORVSC_REQUEST Request); ++ ++typedef int (*PFN_ON_HOST_RESET)(PDEVICE_OBJECT Device); ++typedef void (*PFN_ON_HOST_RESCAN)(PDEVICE_OBJECT Device); ++ ++ ++// Matches Windows-end ++typedef enum _STORVSC_REQUEST_TYPE{ ++ WRITE_TYPE, ++ READ_TYPE, ++ UNKNOWN_TYPE, ++} STORVSC_REQUEST_TYPE; ++ ++ ++typedef struct _STORVSC_REQUEST { ++ STORVSC_REQUEST_TYPE Type; ++ UINT32 Host; ++ UINT32 Bus; ++ UINT32 TargetId; ++ UINT32 LunId; ++ UINT8* Cdb; ++ UINT32 CdbLen; ++ UINT32 Status; ++ UINT32 BytesXfer; ++ ++ UCHAR* SenseBuffer; ++ UINT32 SenseBufferSize; ++ ++ PVOID Context; ++ ++ PFN_ON_IO_REQUEST_COMPLTN OnIOCompletion; ++ ++ // This points to the memory after DataBuffer ++ PVOID Extension; ++ ++ MULTIPAGE_BUFFER DataBuffer; ++} STORVSC_REQUEST; ++ ++ ++// Represents the block vsc driver ++typedef struct _STORVSC_DRIVER_OBJECT { ++ DRIVER_OBJECT Base; // Must be the first field ++ ++ // Set by caller (in bytes) ++ UINT32 RingBufferSize; ++ ++ // Allocate this much private extension for each I/O request ++ UINT32 RequestExtSize; ++ ++ // Maximum # of requests in flight per channel/device ++ UINT32 MaxOutstandingRequestsPerChannel; ++ ++ // Set by the caller to allow us to re-enumerate the bus on the host ++ PFN_ON_HOST_RESCAN OnHostRescan; ++ ++ // Specific to this driver ++ PFN_ON_IO_REQUEST OnIORequest; ++ PFN_ON_HOST_RESET OnHostReset; ++ ++} STORVSC_DRIVER_OBJECT; ++ ++typedef struct _STORVSC_DEVICE_INFO { ++ ULONG PortNumber; ++ UCHAR PathId; ++ UCHAR TargetId; ++} STORVSC_DEVICE_INFO; ++ ++// ++// Interface ++// ++int ++StorVscInitialize( ++ DRIVER_OBJECT *Driver ++ ); ++ ++int ++BlkVscInitialize( ++ DRIVER_OBJECT *Driver ++ ); ++#endif // _STORVSC_API_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/VmbusApi.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/VmbusApi.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/VmbusApi.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,262 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _VMBUS_API_H_ ++#define _VMBUS_API_H_ ++ ++#include "osd.h" ++ ++// ++// Defines ++// ++ ++#define MAX_PAGE_BUFFER_COUNT 16 ++#define MAX_MULTIPAGE_BUFFER_COUNT 32 // 128K ++ ++ ++// ++// Fwd declarations ++// ++typedef struct _DRIVER_OBJECT *PDRIVER_OBJECT; ++typedef struct _DEVICE_OBJECT *PDEVICE_OBJECT; ++ ++// ++// Data types ++// ++ ++#pragma pack(push,1) ++ ++// Single-page buffer ++typedef struct _PAGE_BUFFER { ++ UINT32 Length; ++ UINT32 Offset; ++ UINT64 Pfn; ++} PAGE_BUFFER; ++ ++// Multiple-page buffer ++typedef struct _MULTIPAGE_BUFFER { ++ // Length and Offset determines the # of pfns in the array ++ UINT32 Length; ++ UINT32 Offset; ++ UINT64 PfnArray[MAX_MULTIPAGE_BUFFER_COUNT]; ++}MULTIPAGE_BUFFER; ++ ++//0x18 includes the proprietary packet header ++#define MAX_PAGE_BUFFER_PACKET (0x18 + (sizeof(PAGE_BUFFER) * MAX_PAGE_BUFFER_COUNT)) ++#define MAX_MULTIPAGE_BUFFER_PACKET (0x18 + sizeof(MULTIPAGE_BUFFER)) ++ ++ ++#pragma pack(pop) ++ ++// All drivers ++typedef int (*PFN_ON_DEVICEADD)(PDEVICE_OBJECT Device, void* AdditionalInfo); ++typedef int (*PFN_ON_DEVICEREMOVE)(PDEVICE_OBJECT Device); ++typedef char** (*PFN_ON_GETDEVICEIDS)(void); ++typedef void (*PFN_ON_CLEANUP)(PDRIVER_OBJECT Driver); ++ ++// Vmbus extensions ++//typedef int (*PFN_ON_MATCH)(PDEVICE_OBJECT dev, PDRIVER_OBJECT drv); ++//typedef int (*PFN_ON_PROBE)(PDEVICE_OBJECT dev); ++typedef int (*PFN_ON_ISR)(PDRIVER_OBJECT drv); ++typedef void (*PFN_ON_DPC)(PDRIVER_OBJECT drv); ++typedef void (*PFN_GET_CHANNEL_OFFERS)(void); ++ ++typedef PDEVICE_OBJECT (*PFN_ON_CHILDDEVICE_CREATE)(GUID DeviceType, GUID DeviceInstance, void *Context); ++typedef void (*PFN_ON_CHILDDEVICE_DESTROY)(PDEVICE_OBJECT Device); ++typedef int (*PFN_ON_CHILDDEVICE_ADD)(PDEVICE_OBJECT RootDevice, PDEVICE_OBJECT ChildDevice); ++typedef void (*PFN_ON_CHILDDEVICE_REMOVE)(PDEVICE_OBJECT Device); ++ ++// Vmbus channel interface ++typedef void (*VMBUS_CHANNEL_CALLBACK)(PVOID context); ++ ++typedef int (*VMBUS_CHANNEL_OPEN)( ++ PDEVICE_OBJECT Device, ++ UINT32 SendBufferSize, ++ UINT32 RecvRingBufferSize, ++ PVOID UserData, ++ UINT32 UserDataLen, ++ VMBUS_CHANNEL_CALLBACK ChannelCallback, ++ PVOID Context ++ ); ++ ++typedef void (*VMBUS_CHANNEL_CLOSE)( ++ PDEVICE_OBJECT Device ++ ); ++ ++typedef int (*VMBUS_CHANNEL_SEND_PACKET)( ++ PDEVICE_OBJECT Device, ++ const PVOID Buffer, ++ UINT32 BufferLen, ++ UINT64 RequestId, ++ UINT32 Type, ++ UINT32 Flags ++); ++ ++typedef int (*VMBUS_CHANNEL_SEND_PACKET_PAGEBUFFER)( ++ PDEVICE_OBJECT Device, ++ PAGE_BUFFER PageBuffers[], ++ UINT32 PageCount, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT64 RequestId ++ ); ++ ++typedef int (*VMBUS_CHANNEL_SEND_PACKET_MULTIPAGEBUFFER)( ++ PDEVICE_OBJECT Device, ++ MULTIPAGE_BUFFER *MultiPageBuffer, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT64 RequestId ++); ++ ++typedef int (*VMBUS_CHANNEL_RECV_PACKET)( ++ PDEVICE_OBJECT Device, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT32* BufferActualLen, ++ UINT64* RequestId ++ ); ++ ++typedef int (*VMBUS_CHANNEL_RECV_PACKET_PAW)( ++ PDEVICE_OBJECT Device, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT32* BufferActualLen, ++ UINT64* RequestId ++ ); ++ ++typedef int (*VMBUS_CHANNEL_ESTABLISH_GPADL)( ++ PDEVICE_OBJECT Device, ++ PVOID Buffer, // from kmalloc() ++ UINT32 BufferLen, // page-size multiple ++ UINT32* GpadlHandle ++ ); ++ ++typedef int (*VMBUS_CHANNEL_TEARDOWN_GPADL)( ++ PDEVICE_OBJECT Device, ++ UINT32 GpadlHandle ++ ); ++ ++ ++typedef struct _PORT_INFO { ++ UINT32 InterruptMask; ++ UINT32 ReadIndex; ++ UINT32 WriteIndex; ++ UINT32 BytesAvailToRead; ++ UINT32 BytesAvailToWrite; ++} PORT_INFO; ++ ++ ++typedef struct _DEVICE_INFO { ++ UINT32 ChannelId; ++ UINT32 ChannelState; ++ GUID ChannelType; ++ GUID ChannelInstance; ++ ++ UINT32 MonitorId; ++ UINT32 ServerMonitorPending; ++ UINT32 ServerMonitorLatency; ++ UINT32 ServerMonitorConnectionId; ++ UINT32 ClientMonitorPending; ++ UINT32 ClientMonitorLatency; ++ UINT32 ClientMonitorConnectionId; ++ ++ PORT_INFO Inbound; ++ PORT_INFO Outbound; ++} DEVICE_INFO; ++ ++typedef void (*VMBUS_GET_CHANNEL_INFO)(PDEVICE_OBJECT Device, DEVICE_INFO* DeviceInfo); ++ ++typedef struct _VMBUS_CHANNEL_INTERFACE { ++ VMBUS_CHANNEL_OPEN Open; ++ VMBUS_CHANNEL_CLOSE Close; ++ VMBUS_CHANNEL_SEND_PACKET SendPacket; ++ VMBUS_CHANNEL_SEND_PACKET_PAGEBUFFER SendPacketPageBuffer; ++ VMBUS_CHANNEL_SEND_PACKET_MULTIPAGEBUFFER SendPacketMultiPageBuffer; ++ VMBUS_CHANNEL_RECV_PACKET RecvPacket; ++ VMBUS_CHANNEL_RECV_PACKET_PAW RecvPacketRaw; ++ VMBUS_CHANNEL_ESTABLISH_GPADL EstablishGpadl; ++ VMBUS_CHANNEL_TEARDOWN_GPADL TeardownGpadl; ++ VMBUS_GET_CHANNEL_INFO GetInfo; ++} VMBUS_CHANNEL_INTERFACE; ++ ++typedef void (*VMBUS_GET_CHANNEL_INTERFACE)(VMBUS_CHANNEL_INTERFACE *Interface); ++ ++// Base driver object ++typedef struct _DRIVER_OBJECT { ++ const char* name; ++ GUID deviceType; // the device type supported by this driver ++ ++ PFN_ON_DEVICEADD OnDeviceAdd; ++ PFN_ON_DEVICEREMOVE OnDeviceRemove; ++ PFN_ON_GETDEVICEIDS OnGetDeviceIds; // device ids supported by this driver ++ PFN_ON_CLEANUP OnCleanup; ++ ++ VMBUS_CHANNEL_INTERFACE VmbusChannelInterface; ++} DRIVER_OBJECT; ++ ++ ++// Base device object ++typedef struct _DEVICE_OBJECT { ++ DRIVER_OBJECT* Driver; // the driver for this device ++ char name[64]; ++ GUID deviceType; // the device type id of this device ++ GUID deviceInstance; // the device instance id of this device ++ void* context; ++ void* Extension; // Device extension; ++} DEVICE_OBJECT; ++ ++ ++// Vmbus driver object ++typedef struct _VMBUS_DRIVER_OBJECT { ++ DRIVER_OBJECT Base; // !! Must be the 1st field !! ++ ++ // Set by the caller ++ PFN_ON_CHILDDEVICE_CREATE OnChildDeviceCreate; ++ PFN_ON_CHILDDEVICE_DESTROY OnChildDeviceDestroy; ++ PFN_ON_CHILDDEVICE_ADD OnChildDeviceAdd; ++ PFN_ON_CHILDDEVICE_REMOVE OnChildDeviceRemove; ++ ++ // Set by the callee ++ //PFN_ON_MATCH OnMatch; ++ //PFN_ON_PROBE OnProbe; ++ PFN_ON_ISR OnIsr; ++ PFN_ON_DPC OnMsgDpc; ++ PFN_ON_DPC OnEventDpc; ++ PFN_GET_CHANNEL_OFFERS GetChannelOffers; ++ ++ VMBUS_GET_CHANNEL_INTERFACE GetChannelInterface; ++ VMBUS_GET_CHANNEL_INFO GetChannelInfo; ++} VMBUS_DRIVER_OBJECT; ++ ++ ++// ++// Interface ++// ++int ++VmbusInitialize( ++ DRIVER_OBJECT* drv ++ ); ++ ++#endif // _VMBUS_API_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/VmbusChannelInterface.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/VmbusChannelInterface.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/VmbusChannelInterface.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,131 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#pragma once ++// allow nameless unions ++//#pragma warning(disable : 4201) ++ ++// ++// A revision number of vmbus that is used for ensuring both ends on a ++// partition are using compatible versions. ++// ++#define VMBUS_REVISION_NUMBER 13 ++ ++// ++// Make maximum size of pipe payload of 16K ++// ++#define MAX_PIPE_DATA_PAYLOAD (sizeof(BYTE) * 16384) ++ ++// ++// Define PipeMode values. ++// ++#define VMBUS_PIPE_TYPE_BYTE 0x00000000 ++#define VMBUS_PIPE_TYPE_MESSAGE 0x00000004 ++ ++// ++// The size of the user defined data buffer for non-pipe offers. ++// ++#define MAX_USER_DEFINED_BYTES 120 ++ ++// ++// The size of the user defined data buffer for pipe offers. ++// ++#define MAX_PIPE_USER_DEFINED_BYTES 116 ++ ++ ++// ++// At the center of the Channel Management library is ++// the Channel Offer. This struct contains the ++// fundamental information about an offer. ++// ++#pragma pack(push,1) ++ ++typedef struct ++{ ++ ++ GUID InterfaceType; ++ GUID InterfaceInstance; ++ UINT64 InterruptLatencyIn100nsUnits; ++ UINT32 InterfaceRevision; ++ UINT32 ServerContextAreaSize; // in bytes ++ UINT16 ChannelFlags; ++ UINT16 MmioMegabytes; // in bytes * 1024 * 1024 ++ ++ union ++ { ++ // ++ // Non-pipes: The user has MAX_USER_DEFINED_BYTES bytes. ++ // ++ struct ++ { ++ UCHAR UserDefined[MAX_USER_DEFINED_BYTES]; ++ } Standard; ++ ++ // ++ // Pipes: The following sructure is an integrated pipe protocol, which ++ // is implemented on top of standard user-defined data. Pipe clients ++ // have MAX_PIPE_USER_DEFINED_BYTES left for their own use. ++ // ++ struct ++ { ++ UINT32 PipeMode; ++ UCHAR UserDefined[MAX_PIPE_USER_DEFINED_BYTES]; ++ } Pipe; ++ } u; ++ UINT32 Padding; ++} VMBUS_CHANNEL_OFFER, *PVMBUS_CHANNEL_OFFER; ++#pragma pack(pop) ++ ++ ++// ++// Verify the MAX_PIPE_USER_DEFINED_BYTES value. ++// ++//C_ASSERT(MAX_PIPE_USER_DEFINED_BYTES == ++// MAX_USER_DEFINED_BYTES - ++// (FIELD_OFFSET(VMBUS_CHANNEL_OFFER, u.Pipe.UserDefined) - ++// FIELD_OFFSET(VMBUS_CHANNEL_OFFER, u.Standard.UserDefined))); ++// ++ ++typedef UINT32 GPADL_HANDLE; ++ ++// ++// Server Flags ++// ++ ++#define VMBUS_CHANNEL_ENUMERATE_DEVICE_INTERFACE 1 ++#define VMBUS_CHANNEL_SERVER_SUPPORTS_TRANSFER_PAGES 2 ++#define VMBUS_CHANNEL_SERVER_SUPPORTS_GPADLS 4 ++#define VMBUS_CHANNEL_NAMED_PIPE_MODE 0x10 ++#define VMBUS_CHANNEL_LOOPBACK_OFFER 0x100 ++#define VMBUS_CHANNEL_PARENT_OFFER 0x200 ++#define VMBUS_CHANNEL_REQUEST_MONITORED_NOTIFICATION 0x400 ++ ++// ++// TEMPTEMP -- move this next define to devioctl.h some day ++// ++ ++#ifndef FILE_DEVICE_VMBUS ++#define FILE_DEVICE_VMBUS 0x0000003E ++#endif ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/vmbus.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/vmbus.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/vmbus.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,111 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _VMBUS_H_ ++#define _VMBUS_H_ ++ ++#include ++ ++#include "VmbusApi.h" ++ ++// ++// Data types ++// ++ ++typedef int (*PFN_DRIVERINITIALIZE)(DRIVER_OBJECT *drv); ++typedef int (*PFN_DRIVEREXIT)(DRIVER_OBJECT *drv); ++ ++struct driver_context { ++ GUID class_id; ++ ++ struct device_driver driver; ++ ++ // Use these methods instead of the struct device_driver so 2.6 kernel stops complaining ++ int (*probe)(struct device *); ++ int (*remove)(struct device *); ++ void (*shutdown)(struct device *); ++}; ++ ++struct device_context { ++ struct work_struct probe_failed_work_item; ++ GUID class_id; ++ GUID device_id; ++ int probe_error; ++ struct device device; ++ DEVICE_OBJECT device_obj; ++}; ++ ++ ++// ++// Global ++// ++ ++// ++// Inlines ++// ++static inline struct device_context *to_device_context(DEVICE_OBJECT *device_obj) ++{ ++ return container_of(device_obj, struct device_context, device_obj); ++} ++ ++static inline struct device_context *device_to_device_context(struct device *device) ++{ ++ return container_of(device, struct device_context, device); ++} ++ ++static inline struct driver_context *driver_to_driver_context(struct device_driver *driver) ++{ ++ return container_of(driver, struct driver_context, driver); ++} ++ ++#if defined(KERNEL_2_6_5) ++static inline void* kzalloc(int size, int flags) ++{ ++ void *p; ++ p = kmalloc(size, flags); ++ if (p) memset(p, 0, size); ++ ++ return p; ++} ++#endif // KERNEL_2_6_5 ++ ++// ++// Vmbus interface ++// ++void ++vmbus_child_driver_register( ++ struct driver_context* driver_ctx ++ ); ++ ++void ++vmbus_child_driver_unregister( ++ struct driver_context *driver_ctx ++ ); ++ ++void ++vmbus_get_interface( ++ VMBUS_CHANNEL_INTERFACE *interface ++ ); ++ ++#endif // _VMBUS_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/VmbusPacketFormat.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/VmbusPacketFormat.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/VmbusPacketFormat.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,322 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#pragma once ++ ++//#ifndef PAGE_SIZE ++//#if defined(_IA64_) ++//#error This does not work for IA64 ++//#else ++//#define PAGE_SIZE 0x1000 ++//#endif ++//#endif ++ ++// allow nameless unions ++//#pragma warning(disable : 4201) ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ volatile UINT32 In; // Offset in bytes from the ring base ++ volatile UINT32 Out; // Offset in bytes from the ring base ++ }; ++ volatile LONGLONG InOut; ++ }; ++ ++ // ++ // If the receiving endpoint sets this to some non-zero value, the sending ++ // endpoint should not send any interrupts. ++ // ++ ++ volatile UINT32 InterruptMask; ++ ++} VMRCB, *PVMRCB; ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ VMRCB Control; ++ }; ++ ++ UINT8 Reserved[PAGE_SIZE]; ++ }; ++ ++ // ++ // Beginning of the ring data. Note: It must be guaranteed that ++ // this data does not share a page with the control structure. ++ // ++ UINT8 Data[1]; ++} VMRING, *PVMRING; ++ ++#pragma pack(push, 1) ++ ++typedef struct ++{ ++ UINT16 Type; ++ UINT16 DataOffset8; ++ UINT16 Length8; ++ UINT16 Flags; ++ UINT64 TransactionId; ++} VMPACKET_DESCRIPTOR, *PVMPACKET_DESCRIPTOR; ++ ++typedef UINT32 PREVIOUS_PACKET_OFFSET, *PPREVIOUS_PACKET_OFFSET; ++ ++typedef struct ++{ ++ PREVIOUS_PACKET_OFFSET PreviousPacketStartOffset; ++ VMPACKET_DESCRIPTOR Descriptor; ++} VMPACKET_HEADER, *PVMPACKET_HEADER; ++ ++typedef struct ++{ ++ UINT32 ByteCount; ++ UINT32 ByteOffset; ++} VMTRANSFER_PAGE_RANGE, *PVMTRANSFER_PAGE_RANGE; ++ ++#ifdef __cplusplus ++ ++typedef struct _VMTRANSFER_PAGE_PACKET_HEADER : VMPACKET_DESCRIPTOR { ++ ++#else ++ ++typedef struct VMTRANSFER_PAGE_PACKET_HEADER { ++ ++ VMPACKET_DESCRIPTOR d; ++ ++#endif ++ ++ UINT16 TransferPageSetId; ++ BOOLEAN SenderOwnsSet; ++ UINT8 Reserved; ++ UINT32 RangeCount; ++ VMTRANSFER_PAGE_RANGE Ranges[1]; ++ ++} VMTRANSFER_PAGE_PACKET_HEADER, *PVMTRANSFER_PAGE_PACKET_HEADER; ++ ++ ++#ifdef __cplusplus ++ ++typedef struct _VMGPADL_PACKET_HEADER : VMPACKET_DESCRIPTOR { ++ ++#else ++ ++typedef struct _VMGPADL_PACKET_HEADER { ++ ++ VMPACKET_DESCRIPTOR d; ++ ++#endif ++ ++ ++ UINT32 Gpadl; ++ UINT32 Reserved; ++ ++} VMGPADL_PACKET_HEADER, *PVMGPADL_PACKET_HEADER; ++ ++#ifdef __cplusplus ++ ++typedef struct _VMADD_REMOVE_TRANSFER_PAGE_SET : VMPACKET_DESCRIPTOR { ++ ++#else ++ ++typedef struct _VMADD_REMOVE_TRANSFER_PAGE_SET { ++ ++ VMPACKET_DESCRIPTOR d; ++ ++#endif ++ ++ UINT32 Gpadl; ++ UINT16 TransferPageSetId; ++ UINT16 Reserved; ++ ++} VMADD_REMOVE_TRANSFER_PAGE_SET, *PVMADD_REMOVE_TRANSFER_PAGE_SET; ++ ++#pragma pack(pop) ++ ++// ++// This structure defines a range in guest physical space that can be made ++// to look virtually contiguous. ++// ++ ++typedef struct _GPA_RANGE { ++ ++ UINT32 ByteCount; ++ UINT32 ByteOffset; ++ UINT64 PfnArray[0]; ++ ++} GPA_RANGE, *PGPA_RANGE; ++ ++ ++ ++#pragma pack(push, 1) ++ ++// ++// This is the format for an Establish Gpadl packet, which contains a handle ++// by which this GPADL will be known and a set of GPA ranges associated with ++// it. This can be converted to a MDL by the guest OS. If there are multiple ++// GPA ranges, then the resulting MDL will be "chained," representing multiple ++// VA ranges. ++// ++ ++#ifdef __cplusplus ++ ++typedef struct _VMESTABLISH_GPADL : VMPACKET_DESCRIPTOR { ++ ++#else ++ ++typedef struct _VMESTABLISH_GPADL { ++ ++ VMPACKET_DESCRIPTOR d; ++ ++#endif ++ ++ UINT32 Gpadl; ++ UINT32 RangeCount; ++ GPA_RANGE Range[1]; ++ ++} VMESTABLISH_GPADL, *PVMESTABLISH_GPADL; ++ ++ ++// ++// This is the format for a Teardown Gpadl packet, which indicates that the ++// GPADL handle in the Establish Gpadl packet will never be referenced again. ++// ++ ++#ifdef __cplusplus ++ ++typedef struct _VMTEARDOWN_GPADL : VMPACKET_DESCRIPTOR { ++ ++#else ++ ++typedef struct _VMTEARDOWN_GPADL { ++ ++ VMPACKET_DESCRIPTOR d; ++ ++#endif ++ ++ UINT32 Gpadl; ++ UINT32 Reserved; // for alignment to a 8-byte boundary ++} VMTEARDOWN_GPADL, *PVMTEARDOWN_GPADL; ++ ++ ++// ++// This is the format for a GPA-Direct packet, which contains a set of GPA ++// ranges, in addition to commands and/or data. ++// ++ ++#ifdef __cplusplus ++ ++typedef struct _VMDATA_GPA_DIRECT : VMPACKET_DESCRIPTOR { ++ ++#else ++ ++typedef struct _VMDATA_GPA_DIRECT { ++ ++ VMPACKET_DESCRIPTOR d; ++ ++#endif ++ ++ UINT32 Reserved; ++ UINT32 RangeCount; ++ GPA_RANGE Range[1]; ++ ++} VMDATA_GPA_DIRECT, *PVMDATA_GPA_DIRECT; ++ ++ ++ ++// ++// This is the format for a Additional Data Packet. ++// ++ ++#ifdef __cplusplus ++ ++typedef struct _VMADDITIONAL_DATA : VMPACKET_DESCRIPTOR { ++ ++#else ++ ++typedef struct _VMADDITIONAL_DATA { ++ ++ VMPACKET_DESCRIPTOR d; ++ ++#endif ++ ++ UINT64 TotalBytes; ++ UINT32 ByteOffset; ++ UINT32 ByteCount; ++ UCHAR Data[1]; ++ ++} VMADDITIONAL_DATA, *PVMADDITIONAL_DATA; ++ ++ ++#pragma pack(pop) ++ ++typedef union { ++ VMPACKET_DESCRIPTOR SimpleHeader; ++ VMTRANSFER_PAGE_PACKET_HEADER TransferPageHeader; ++ VMGPADL_PACKET_HEADER GpadlHeader; ++ VMADD_REMOVE_TRANSFER_PAGE_SET AddRemoveTransferPageHeader; ++ VMESTABLISH_GPADL EstablishGpadlHeader; ++ VMTEARDOWN_GPADL TeardownGpadlHeader; ++ VMDATA_GPA_DIRECT DataGpaDirectHeader; ++} VMPACKET_LARGEST_POSSIBLE_HEADER, *PVMPACKET_LARGEST_POSSIBLE_HEADER; ++ ++#define VMPACKET_DATA_START_ADDRESS(__packet) \ ++ (PVOID)(((PUCHAR)__packet) + ((PVMPACKET_DESCRIPTOR)__packet)->DataOffset8 * 8) ++ ++#define VMPACKET_DATA_LENGTH(__packet) \ ++ ((((PVMPACKET_DESCRIPTOR)__packet)->Length8 - ((PVMPACKET_DESCRIPTOR)__packet)->DataOffset8) * 8) ++ ++#define VMPACKET_TRANSFER_MODE(__packet) ((PVMPACKET_DESCRIPTOR)__packet)->Type ++ ++typedef enum { ++ VmbusServerEndpoint = 0, ++ VmbusClientEndpoint, ++ VmbusEndpointMaximum ++} ENDPOINT_TYPE, *PENDPOINT_TYPE; ++ ++typedef enum { ++ VmbusPacketTypeInvalid = 0x0, ++ VmbusPacketTypeSynch = 0x1, ++ VmbusPacketTypeAddTransferPageSet = 0x2, ++ VmbusPacketTypeRemoveTransferPageSet = 0x3, ++ VmbusPacketTypeEstablishGpadl = 0x4, ++ VmbusPacketTypeTearDownGpadl = 0x5, ++ VmbusPacketTypeDataInBand = 0x6, ++ VmbusPacketTypeDataUsingTransferPages = 0x7, ++ VmbusPacketTypeDataUsingGpadl = 0x8, ++ VmbusPacketTypeDataUsingGpaDirect = 0x9, ++ VmbusPacketTypeCancelRequest = 0xa, ++ VmbusPacketTypeCompletion = 0xb, ++ VmbusPacketTypeDataUsingAdditionalPackets = 0xc, ++ VmbusPacketTypeAdditionalData = 0xd ++} VMBUS_PACKET_TYPE, *PVMBUS_PACKET_TYPE; ++ ++#define VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED 1 ++ ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/include/vstorage.h linux-2.6.27.29-0.1.1/drivers/staging/hv/include/vstorage.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/include/vstorage.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,309 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#pragma once ++ ++//#include ++//#include ++ ++#define C_ASSERT(x) ++// ++// public interface to the server ++// ++ ++// ++// Storvsp device interface guid ++// ++ ++ ++// ++// Protocol versions. ++// ++ ++// ++// vstorage.w revision number. This is used in the case of a version match, ++// to alert the user that structure sizes may be mismatched even though the ++// protocol versions match. ++// ++ ++#define REVISION_STRING(REVISION_) #REVISION_ ++#define FILL_VMSTOR_REVISION(RESULT_LVALUE_) \ ++{ \ ++ char *revisionString = REVISION_STRING($Revision: 6 $) + 11; \ ++ RESULT_LVALUE_ = 0; \ ++ while (*revisionString >= '0' && *revisionString <= '9') \ ++ { \ ++ RESULT_LVALUE_ *= 10; \ ++ RESULT_LVALUE_ += *revisionString - '0'; \ ++ revisionString++; \ ++ } \ ++} ++ ++// ++// Major/minor macros. Minor version is in LSB, meaning that earlier flat ++// version numbers will be interpreted as "0.x" (i.e., 1 becomes 0.1). ++// ++ ++#define VMSTOR_PROTOCOL_MAJOR(VERSION_) (((VERSION_) >> 8) & 0xff) ++#define VMSTOR_PROTOCOL_MINOR(VERSION_) (((VERSION_) ) & 0xff) ++#define VMSTOR_PROTOCOL_VERSION(MAJOR_, MINOR_) ((((MAJOR_) & 0xff) << 8) | \ ++ (((MINOR_) & 0xff) )) ++ ++// ++// Invalid version. ++// ++ ++#define VMSTOR_INVALID_PROTOCOL_VERSION -1 ++ ++// ++// Version history: ++// V1 Beta 0.1 ++// V1 RC < 2008/1/31 1.0 ++// V1 RC > 2008/1/31 2.0 ++// ++#define VMSTOR_PROTOCOL_VERSION_CURRENT VMSTOR_PROTOCOL_VERSION(2, 0) ++ ++ ++// ++// This will get replaced with the max transfer length that is possible on ++// the host adapter. ++// The max transfer length will be published when we offer a vmbus channel. ++// ++ ++#define MAX_TRANSFER_LENGTH 0x40000 ++#define DEFAULT_PACKET_SIZE (sizeof(VMDATA_GPA_DIRECT) + \ ++ sizeof(VSTOR_PACKET) + \ ++ (sizeof(UINT64) * (MAX_TRANSFER_LENGTH / PAGE_SIZE))) ++ ++ ++ ++// ++// Packet structure describing virtual storage requests. ++// ++ ++typedef enum ++{ ++ VStorOperationCompleteIo = 1, ++ VStorOperationRemoveDevice = 2, ++ VStorOperationExecuteSRB = 3, ++ VStorOperationResetLun = 4, ++ VStorOperationResetAdapter = 5, ++ VStorOperationResetBus = 6, ++ VStorOperationBeginInitialization = 7, ++ VStorOperationEndInitialization = 8, ++ VStorOperationQueryProtocolVersion = 9, ++ VStorOperationQueryProperties = 10, ++ VStorOperationMaximum = 10 ++ ++} VSTOR_PACKET_OPERATION; ++ ++ ++// ++// Platform neutral description of a scsi request - ++// this remains the same across the write regardless of 32/64 bit ++// note: it's patterned off the SCSI_PASS_THROUGH structure ++// ++ ++ ++#pragma pack(push,1) ++ ++ ++#define CDB16GENERIC_LENGTH 0x10 ++ ++#ifndef SENSE_BUFFER_SIZE ++#define SENSE_BUFFER_SIZE 0x12 ++#endif ++C_ASSERT(SENSE_BUFFER_SIZE == 0x12); ++ ++#define MAX_DATA_BUFFER_LENGTH_WITH_PADDING 0x14 ++ ++ ++typedef struct ++{ ++ USHORT Length; ++ UCHAR SrbStatus; ++ UCHAR ScsiStatus; ++ ++ UCHAR PortNumber; ++ UCHAR PathId; ++ UCHAR TargetId; ++ UCHAR Lun; ++ ++ UCHAR CdbLength; ++ UCHAR SenseInfoLength; ++ UCHAR DataIn; ++ UCHAR Reserved; ++ ++ ULONG DataTransferLength; ++ ++ union ++ { ++ UCHAR Cdb[CDB16GENERIC_LENGTH]; ++ ++ UCHAR SenseData[SENSE_BUFFER_SIZE]; ++ ++ UCHAR ReservedArray[MAX_DATA_BUFFER_LENGTH_WITH_PADDING]; ++ }; ++ ++} VMSCSI_REQUEST, *PVMSCSI_REQUEST; ++ ++C_ASSERT((sizeof(VMSCSI_REQUEST) % 4) == 0); ++ ++ ++// ++// This structure is sent during the intialization phase to get the different ++// properties of the channel. ++// ++ ++typedef struct ++{ ++ USHORT ProtocolVersion; ++ UCHAR PathId; ++ UCHAR TargetId; ++ ++ // ++ // Note: port number is only really known on the client side ++ // ++ ULONG PortNumber; ++ ++ ULONG Flags; ++ ++ ULONG MaxTransferBytes; ++ ++ // ++ // This id is unique for each channel and will correspond with ++ // vendor specific data in the inquirydata ++ // ++ ++ ULONGLONG UniqueId; ++ ++} VMSTORAGE_CHANNEL_PROPERTIES, *PVMSTORAGE_CHANNEL_PROPERTIES; ++ ++C_ASSERT((sizeof(VMSTORAGE_CHANNEL_PROPERTIES) % 4) == 0); ++ ++ ++// ++// This structure is sent during the storage protocol negotiations. ++// ++ ++typedef struct ++{ ++ // ++ // Major (MSW) and minor (LSW) version numbers. ++ // ++ ++ USHORT MajorMinor; ++ ++ ++ // ++ // Revision number is auto-incremented whenever this file is changed ++ // (See FILL_VMSTOR_REVISION macro above). Mismatch does not definitely ++ // indicate incompatibility--but it does indicate mismatched builds. ++ // ++ ++ USHORT Revision; ++ ++} VMSTORAGE_PROTOCOL_VERSION, *PVMSTORAGE_PROTOCOL_VERSION; ++ ++C_ASSERT((sizeof(VMSTORAGE_PROTOCOL_VERSION) % 4) == 0); ++ ++ ++// ++// Channel Property Flags ++// ++ ++#define STORAGE_CHANNEL_REMOVABLE_FLAG 0x1 ++#define STORAGE_CHANNEL_EMULATED_IDE_FLAG 0x2 ++ ++ ++typedef struct _VSTOR_PACKET ++{ ++ // ++ // Requested operation type ++ // ++ ++ VSTOR_PACKET_OPERATION Operation; ++ ++ // ++ // Flags - see below for values ++ // ++ ++ ULONG Flags; ++ ++ // ++ // Status of the request returned from the server side. ++ // ++ ++ ULONG Status; ++ ++ // ++ // Data payload area ++ // ++ ++ union ++ { ++ // ++ // Structure used to forward SCSI commands from the client to the server. ++ // ++ ++ VMSCSI_REQUEST VmSrb; ++ ++ // ++ // Structure used to query channel properties. ++ // ++ ++ VMSTORAGE_CHANNEL_PROPERTIES StorageChannelProperties; ++ ++ // ++ // Used during version negotiations. ++ // ++ ++ VMSTORAGE_PROTOCOL_VERSION Version; ++ }; ++ ++} VSTOR_PACKET, *PVSTOR_PACKET; ++ ++C_ASSERT((sizeof(VSTOR_PACKET) % 4) == 0); ++ ++// ++// Packet flags ++// ++ ++// ++// This flag indicates that the server should send back a completion for this ++// packet. ++// ++ ++#define REQUEST_COMPLETION_FLAG 0x1 ++ ++// ++// This is the set of flags that the vsc can set in any packets it sends ++// ++ ++#define VSC_LEGAL_FLAGS (REQUEST_COMPLETION_FLAG) ++ ++ ++#pragma pack(pop) ++ ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/Kconfig linux-2.6.27.29-0.1.1/drivers/staging/hv/Kconfig +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/Kconfig 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,28 @@ ++config HYPERV ++ tristate "Microsoft Hyper-V client drivers" ++ depends on X86 && !XEN ++ default n ++ help ++ Select this option to run Linux as a Hyper-V client operating ++ system. ++ ++config HYPERV_STORAGE ++ tristate "Microsoft Hyper-V virtual storage driver" ++ depends on HYPERV && SCSI ++ default n ++ help ++ Select this option to enable the Hyper-V virtual storage driver. ++ ++config HYPERV_BLOCK ++ tristate "Microsoft Hyper-V virtual block driver" ++ depends on HYPERV && BLOCK ++ default n ++ help ++ Select this option to enable the Hyper-V virtual block driver. ++ ++config HYPERV_NET ++ tristate "Microsoft Hyper-V virtual network driver" ++ depends on HYPERV && NET ++ default n ++ help ++ Select this option to enable the Hyper-V virtual network driver. +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/Makefile linux-2.6.27.29-0.1.1/drivers/staging/hv/Makefile +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/Makefile 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,9 @@ ++obj-$(CONFIG_HYPERV) += hv_vmbus.o ++obj-$(CONFIG_HYPERV_STORAGE) += hv_storvsc.o ++obj-$(CONFIG_HYPERV_BLOCK) += hv_blkvsc.o ++obj-$(CONFIG_HYPERV_NET) += hv_netvsc.o ++ ++hv_vmbus-objs := vmbus_drv.o osd.o Sources.o ++hv_storvsc-objs := storvsc_drv.o osd.o StorVsc.o ++hv_blkvsc-objs := blkvsc_drv.o osd.o BlkVsc.o ++hv_netvsc-objs := netvsc_drv.o osd.o NetVsc.o RndisFilter.o +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/NetVsc.c linux-2.6.27.29-0.1.1/drivers/staging/hv/NetVsc.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/NetVsc.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,1500 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Hank Janssen ++ * ++ */ ++ ++#define KERNEL_2_6_27 ++ ++#include "include/logging.h" ++#include "NetVsc.h" ++#include "RndisFilter.h" ++ ++ ++// ++// Globals ++// ++static const char* gDriverName="netvsc"; ++ ++// {F8615163-DF3E-46c5-913F-F2D2F965ED0E} ++static const GUID gNetVscDeviceType={ ++ .Data = {0x63, 0x51, 0x61, 0xF8, 0x3E, 0xDF, 0xc5, 0x46, 0x91, 0x3F, 0xF2, 0xD2, 0xF9, 0x65, 0xED, 0x0E} ++}; ++ ++ ++// ++// Internal routines ++// ++static int ++NetVscOnDeviceAdd( ++ DEVICE_OBJECT *Device, ++ void *AdditionalInfo ++ ); ++ ++static int ++NetVscOnDeviceRemove( ++ DEVICE_OBJECT *Device ++ ); ++ ++static void ++NetVscOnCleanup( ++ DRIVER_OBJECT *Driver ++ ); ++ ++static void ++NetVscOnChannelCallback( ++ PVOID context ++ ); ++ ++static int ++NetVscInitializeSendBufferWithNetVsp( ++ DEVICE_OBJECT *Device ++ ); ++ ++static int ++NetVscInitializeReceiveBufferWithNetVsp( ++ DEVICE_OBJECT *Device ++ ); ++ ++static int ++NetVscDestroySendBuffer( ++ NETVSC_DEVICE *NetDevice ++ ); ++ ++static int ++NetVscDestroyReceiveBuffer( ++ NETVSC_DEVICE *NetDevice ++ ); ++ ++static int ++NetVscConnectToVsp( ++ DEVICE_OBJECT *Device ++ ); ++ ++static void ++NetVscOnSendCompletion( ++ DEVICE_OBJECT *Device, ++ VMPACKET_DESCRIPTOR *Packet ++ ); ++ ++static int ++NetVscOnSend( ++ DEVICE_OBJECT *Device, ++ NETVSC_PACKET *Packet ++ ); ++ ++static void ++NetVscOnReceive( ++ DEVICE_OBJECT *Device, ++ VMPACKET_DESCRIPTOR *Packet ++ ); ++ ++static void ++NetVscOnReceiveCompletion( ++ PVOID Context ++ ); ++ ++static void ++NetVscSendReceiveCompletion( ++ DEVICE_OBJECT *Device, ++ UINT64 TransactionId ++ ); ++ ++static inline NETVSC_DEVICE* AllocNetDevice(DEVICE_OBJECT *Device) ++{ ++ NETVSC_DEVICE *netDevice; ++ ++ netDevice = MemAllocZeroed(sizeof(NETVSC_DEVICE)); ++ if (!netDevice) ++ return NULL; ++ ++ // Set to 2 to allow both inbound and outbound traffic ++ InterlockedCompareExchange(&netDevice->RefCount, 2, 0); ++ ++ netDevice->Device = Device; ++ Device->Extension = netDevice; ++ ++ return netDevice; ++} ++ ++static inline void FreeNetDevice(NETVSC_DEVICE *Device) ++{ ++ ASSERT(Device->RefCount == 0); ++ Device->Device->Extension = NULL; ++ MemFree(Device); ++} ++ ++ ++// Get the net device object iff exists and its refcount > 1 ++static inline NETVSC_DEVICE* GetOutboundNetDevice(DEVICE_OBJECT *Device) ++{ ++ NETVSC_DEVICE *netDevice; ++ ++ netDevice = (NETVSC_DEVICE*)Device->Extension; ++ if (netDevice && netDevice->RefCount > 1) ++ { ++ InterlockedIncrement(&netDevice->RefCount); ++ } ++ else ++ { ++ netDevice = NULL; ++ } ++ ++ return netDevice; ++} ++ ++// Get the net device object iff exists and its refcount > 0 ++static inline NETVSC_DEVICE* GetInboundNetDevice(DEVICE_OBJECT *Device) ++{ ++ NETVSC_DEVICE *netDevice; ++ ++ netDevice = (NETVSC_DEVICE*)Device->Extension; ++ if (netDevice && netDevice->RefCount) ++ { ++ InterlockedIncrement(&netDevice->RefCount); ++ } ++ else ++ { ++ netDevice = NULL; ++ } ++ ++ return netDevice; ++} ++ ++static inline void PutNetDevice(DEVICE_OBJECT *Device) ++{ ++ NETVSC_DEVICE *netDevice; ++ ++ netDevice = (NETVSC_DEVICE*)Device->Extension; ++ ASSERT(netDevice); ++ ++ InterlockedDecrement(&netDevice->RefCount); ++} ++ ++static inline NETVSC_DEVICE* ReleaseOutboundNetDevice(DEVICE_OBJECT *Device) ++{ ++ NETVSC_DEVICE *netDevice; ++ ++ netDevice = (NETVSC_DEVICE*)Device->Extension; ++ if (netDevice == NULL) ++ return NULL; ++ ++ // Busy wait until the ref drop to 2, then set it to 1 ++ while (InterlockedCompareExchange(&netDevice->RefCount, 1, 2) != 2) ++ { ++ Sleep(100); ++ } ++ ++ return netDevice; ++} ++ ++static inline NETVSC_DEVICE* ReleaseInboundNetDevice(DEVICE_OBJECT *Device) ++{ ++ NETVSC_DEVICE *netDevice; ++ ++ netDevice = (NETVSC_DEVICE*)Device->Extension; ++ if (netDevice == NULL) ++ return NULL; ++ ++ // Busy wait until the ref drop to 1, then set it to 0 ++ while (InterlockedCompareExchange(&netDevice->RefCount, 0, 1) != 1) ++ { ++ Sleep(100); ++ } ++ ++ Device->Extension = NULL; ++ return netDevice; ++} ++ ++/*++; ++ ++ ++Name: ++ NetVscInitialize() ++ ++Description: ++ Main entry point ++ ++--*/ ++int ++NetVscInitialize( ++ DRIVER_OBJECT *drv ++ ) ++{ ++ NETVSC_DRIVER_OBJECT* driver = (NETVSC_DRIVER_OBJECT*)drv; ++ int ret=0; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ DPRINT_DBG(NETVSC, "sizeof(NETVSC_PACKET)=%d, sizeof(NVSP_MESSAGE)=%d, sizeof(VMTRANSFER_PAGE_PACKET_HEADER)=%d", ++ sizeof(NETVSC_PACKET), sizeof(NVSP_MESSAGE), sizeof(VMTRANSFER_PAGE_PACKET_HEADER)); ++ ++ // Make sure we are at least 2 pages since 1 page is used for control ++ ASSERT(driver->RingBufferSize >= (PAGE_SIZE << 1)); ++ ++ drv->name = gDriverName; ++ memcpy(&drv->deviceType, &gNetVscDeviceType, sizeof(GUID)); ++ ++ // Make sure it is set by the caller ++ ASSERT(driver->OnReceiveCallback); ++ ASSERT(driver->OnLinkStatusChanged); ++ ++ // Setup the dispatch table ++ driver->Base.OnDeviceAdd = NetVscOnDeviceAdd; ++ driver->Base.OnDeviceRemove = NetVscOnDeviceRemove; ++ driver->Base.OnCleanup = NetVscOnCleanup; ++ ++ driver->OnSend = NetVscOnSend; ++ ++ RndisFilterInit(driver); ++ ++ DPRINT_EXIT(NETVSC); ++ ++ return ret; ++} ++ ++static int ++NetVscInitializeReceiveBufferWithNetVsp( ++ DEVICE_OBJECT *Device ++ ) ++{ ++ int ret=0; ++ NETVSC_DEVICE *netDevice; ++ NVSP_MESSAGE *initPacket; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ netDevice = GetOutboundNetDevice(Device); ++ if (!netDevice) ++ { ++ DPRINT_ERR(NETVSC, "unable to get net device...device being destroyed?"); ++ DPRINT_EXIT(NETVSC); ++ return -1; ++ } ++ ASSERT(netDevice->ReceiveBufferSize > 0); ++ ASSERT((netDevice->ReceiveBufferSize & (PAGE_SIZE-1)) == 0); // page-size grandularity ++ ++ netDevice->ReceiveBuffer = PageAlloc(netDevice->ReceiveBufferSize >> PAGE_SHIFT); ++ if (!netDevice->ReceiveBuffer) ++ { ++ DPRINT_ERR(NETVSC, "unable to allocate receive buffer of size %d", netDevice->ReceiveBufferSize); ++ ret = -1; ++ goto Cleanup; ++ } ++ ASSERT(((ULONG_PTR)netDevice->ReceiveBuffer & (PAGE_SIZE-1)) == 0); // page-aligned buffer ++ ++ DPRINT_INFO(NETVSC, "Establishing receive buffer's GPADL..."); ++ ++ // Establish the gpadl handle for this buffer on this channel. ++ // Note: This call uses the vmbus connection rather than the channel to establish ++ // the gpadl handle. ++ ret = Device->Driver->VmbusChannelInterface.EstablishGpadl(Device, ++ netDevice->ReceiveBuffer, ++ netDevice->ReceiveBufferSize, ++ &netDevice->ReceiveBufferGpadlHandle); ++ ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC, "unable to establish receive buffer's gpadl"); ++ goto Cleanup; ++ } ++ ++ //WaitEventWait(ext->ChannelInitEvent); ++ ++ // Notify the NetVsp of the gpadl handle ++ DPRINT_INFO(NETVSC, "Sending NvspMessage1TypeSendReceiveBuffer..."); ++ ++ initPacket = &netDevice->ChannelInitPacket; ++ ++ memset(initPacket, 0, sizeof(NVSP_MESSAGE)); ++ ++ initPacket->Header.MessageType = NvspMessage1TypeSendReceiveBuffer; ++ initPacket->Messages.Version1Messages.SendReceiveBuffer.GpadlHandle = netDevice->ReceiveBufferGpadlHandle; ++ initPacket->Messages.Version1Messages.SendReceiveBuffer.Id = NETVSC_RECEIVE_BUFFER_ID; ++ ++ // Send the gpadl notification request ++ ret = Device->Driver->VmbusChannelInterface.SendPacket(Device, ++ initPacket, ++ sizeof(NVSP_MESSAGE), ++ (ULONG_PTR)initPacket, ++ VmbusPacketTypeDataInBand, ++ VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED); ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC, "unable to send receive buffer's gpadl to netvsp"); ++ goto Cleanup; ++ } ++ ++ WaitEventWait(netDevice->ChannelInitEvent); ++ ++ // Check the response ++ if (initPacket->Messages.Version1Messages.SendReceiveBufferComplete.Status != NvspStatusSuccess) ++ { ++ DPRINT_ERR(NETVSC, ++ "Unable to complete receive buffer initialzation with NetVsp - status %d", ++ initPacket->Messages.Version1Messages.SendReceiveBufferComplete.Status); ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ // Parse the response ++ ASSERT(netDevice->ReceiveSectionCount == 0); ++ ASSERT(netDevice->ReceiveSections == NULL); ++ ++ netDevice->ReceiveSectionCount = initPacket->Messages.Version1Messages.SendReceiveBufferComplete.NumSections; ++ ++ netDevice->ReceiveSections = MemAlloc(netDevice->ReceiveSectionCount * sizeof(NVSP_1_RECEIVE_BUFFER_SECTION)); ++ if (netDevice->ReceiveSections == NULL) ++ { ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ memcpy(netDevice->ReceiveSections, ++ initPacket->Messages.Version1Messages.SendReceiveBufferComplete.Sections, ++ netDevice->ReceiveSectionCount * sizeof(NVSP_1_RECEIVE_BUFFER_SECTION)); ++ ++ DPRINT_INFO(NETVSC, ++ "Receive sections info (count %d, offset %d, endoffset %d, suballoc size %d, num suballocs %d)", ++ netDevice->ReceiveSectionCount, netDevice->ReceiveSections[0].Offset, netDevice->ReceiveSections[0].EndOffset, ++ netDevice->ReceiveSections[0].SubAllocationSize, netDevice->ReceiveSections[0].NumSubAllocations); ++ ++ ++ //For 1st release, there should only be 1 section that represents the entire receive buffer ++ if (netDevice->ReceiveSectionCount != 1 || ++ netDevice->ReceiveSections->Offset != 0 ) ++ { ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ goto Exit; ++ ++Cleanup: ++ NetVscDestroyReceiveBuffer(netDevice); ++ ++Exit: ++ PutNetDevice(Device); ++ DPRINT_EXIT(NETVSC); ++ return ret; ++} ++ ++ ++static int ++NetVscInitializeSendBufferWithNetVsp( ++ DEVICE_OBJECT *Device ++ ) ++{ ++ int ret=0; ++ NETVSC_DEVICE *netDevice; ++ NVSP_MESSAGE *initPacket; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ netDevice = GetOutboundNetDevice(Device); ++ if (!netDevice) ++ { ++ DPRINT_ERR(NETVSC, "unable to get net device...device being destroyed?"); ++ DPRINT_EXIT(NETVSC); ++ return -1; ++ } ++ ASSERT(netDevice->SendBufferSize > 0); ++ ASSERT((netDevice->SendBufferSize & (PAGE_SIZE-1)) == 0); // page-size grandularity ++ ++ netDevice->SendBuffer = PageAlloc(netDevice->SendBufferSize >> PAGE_SHIFT); ++ if (!netDevice->SendBuffer) ++ { ++ DPRINT_ERR(NETVSC, "unable to allocate send buffer of size %d", netDevice->SendBufferSize); ++ ret = -1; ++ goto Cleanup; ++ } ++ ASSERT(((ULONG_PTR)netDevice->SendBuffer & (PAGE_SIZE-1)) == 0); // page-aligned buffer ++ ++ DPRINT_INFO(NETVSC, "Establishing send buffer's GPADL..."); ++ ++ // Establish the gpadl handle for this buffer on this channel. ++ // Note: This call uses the vmbus connection rather than the channel to establish ++ // the gpadl handle. ++ ret = Device->Driver->VmbusChannelInterface.EstablishGpadl(Device, ++ netDevice->SendBuffer, ++ netDevice->SendBufferSize, ++ &netDevice->SendBufferGpadlHandle); ++ ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC, "unable to establish send buffer's gpadl"); ++ goto Cleanup; ++ } ++ ++ //WaitEventWait(ext->ChannelInitEvent); ++ ++ // Notify the NetVsp of the gpadl handle ++ DPRINT_INFO(NETVSC, "Sending NvspMessage1TypeSendSendBuffer..."); ++ ++ initPacket = &netDevice->ChannelInitPacket; ++ ++ memset(initPacket, 0, sizeof(NVSP_MESSAGE)); ++ ++ initPacket->Header.MessageType = NvspMessage1TypeSendSendBuffer; ++ initPacket->Messages.Version1Messages.SendReceiveBuffer.GpadlHandle = netDevice->SendBufferGpadlHandle; ++ initPacket->Messages.Version1Messages.SendReceiveBuffer.Id = NETVSC_SEND_BUFFER_ID; ++ ++ // Send the gpadl notification request ++ ret = Device->Driver->VmbusChannelInterface.SendPacket(Device, ++ initPacket, ++ sizeof(NVSP_MESSAGE), ++ (ULONG_PTR)initPacket, ++ VmbusPacketTypeDataInBand, ++ VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED); ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC, "unable to send receive buffer's gpadl to netvsp"); ++ goto Cleanup; ++ } ++ ++ WaitEventWait(netDevice->ChannelInitEvent); ++ ++ // Check the response ++ if (initPacket->Messages.Version1Messages.SendSendBufferComplete.Status != NvspStatusSuccess) ++ { ++ DPRINT_ERR(NETVSC, ++ "Unable to complete send buffer initialzation with NetVsp - status %d", ++ initPacket->Messages.Version1Messages.SendSendBufferComplete.Status); ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ netDevice->SendSectionSize = initPacket->Messages.Version1Messages.SendSendBufferComplete.SectionSize; ++ ++ goto Exit; ++ ++Cleanup: ++ NetVscDestroySendBuffer(netDevice); ++ ++Exit: ++ PutNetDevice(Device); ++ DPRINT_EXIT(NETVSC); ++ return ret; ++} ++ ++static int ++NetVscDestroyReceiveBuffer( ++ NETVSC_DEVICE *NetDevice ++ ) ++{ ++ NVSP_MESSAGE *revokePacket; ++ int ret=0; ++ ++ ++ DPRINT_ENTER(NETVSC); ++ ++ // If we got a section count, it means we received a SendReceiveBufferComplete msg ++ // (ie sent NvspMessage1TypeSendReceiveBuffer msg) therefore, we need to send a revoke msg here ++ if (NetDevice->ReceiveSectionCount) ++ { ++ DPRINT_INFO(NETVSC, "Sending NvspMessage1TypeRevokeReceiveBuffer..."); ++ ++ // Send the revoke receive buffer ++ revokePacket = &NetDevice->RevokePacket; ++ memset(revokePacket, 0, sizeof(NVSP_MESSAGE)); ++ ++ revokePacket->Header.MessageType = NvspMessage1TypeRevokeReceiveBuffer; ++ revokePacket->Messages.Version1Messages.RevokeReceiveBuffer.Id = NETVSC_RECEIVE_BUFFER_ID; ++ ++ ret = NetDevice->Device->Driver->VmbusChannelInterface.SendPacket(NetDevice->Device, ++ revokePacket, ++ sizeof(NVSP_MESSAGE), ++ (ULONG_PTR)revokePacket, ++ VmbusPacketTypeDataInBand, ++ 0); ++ // If we failed here, we might as well return and have a leak rather than continue and a bugchk ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC, "unable to send revoke receive buffer to netvsp"); ++ DPRINT_EXIT(NETVSC); ++ return -1; ++ } ++ } ++ ++ // Teardown the gpadl on the vsp end ++ if (NetDevice->ReceiveBufferGpadlHandle) ++ { ++ DPRINT_INFO(NETVSC, "Tearing down receive buffer's GPADL..."); ++ ++ ret = NetDevice->Device->Driver->VmbusChannelInterface.TeardownGpadl(NetDevice->Device, ++ NetDevice->ReceiveBufferGpadlHandle); ++ ++ // If we failed here, we might as well return and have a leak rather than continue and a bugchk ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC, "unable to teardown receive buffer's gpadl"); ++ DPRINT_EXIT(NETVSC); ++ return -1; ++ } ++ NetDevice->ReceiveBufferGpadlHandle = 0; ++ } ++ ++ if (NetDevice->ReceiveBuffer) ++ { ++ DPRINT_INFO(NETVSC, "Freeing up receive buffer..."); ++ ++ // Free up the receive buffer ++ PageFree(NetDevice->ReceiveBuffer, NetDevice->ReceiveBufferSize >> PAGE_SHIFT); ++ NetDevice->ReceiveBuffer = NULL; ++ } ++ ++ if (NetDevice->ReceiveSections) ++ { ++ MemFree(NetDevice->ReceiveSections); ++ NetDevice->ReceiveSections = NULL; ++ NetDevice->ReceiveSectionCount = 0; ++ } ++ ++ DPRINT_EXIT(NETVSC); ++ ++ return ret; ++} ++ ++ ++ ++ ++static int ++NetVscDestroySendBuffer( ++ NETVSC_DEVICE *NetDevice ++ ) ++{ ++ NVSP_MESSAGE *revokePacket; ++ int ret=0; ++ ++ ++ DPRINT_ENTER(NETVSC); ++ ++ // If we got a section count, it means we received a SendReceiveBufferComplete msg ++ // (ie sent NvspMessage1TypeSendReceiveBuffer msg) therefore, we need to send a revoke msg here ++ if (NetDevice->SendSectionSize) ++ { ++ DPRINT_INFO(NETVSC, "Sending NvspMessage1TypeRevokeSendBuffer..."); ++ ++ // Send the revoke send buffer ++ revokePacket = &NetDevice->RevokePacket; ++ memset(revokePacket, 0, sizeof(NVSP_MESSAGE)); ++ ++ revokePacket->Header.MessageType = NvspMessage1TypeRevokeSendBuffer; ++ revokePacket->Messages.Version1Messages.RevokeSendBuffer.Id = NETVSC_SEND_BUFFER_ID; ++ ++ ret = NetDevice->Device->Driver->VmbusChannelInterface.SendPacket(NetDevice->Device, ++ revokePacket, ++ sizeof(NVSP_MESSAGE), ++ (ULONG_PTR)revokePacket, ++ VmbusPacketTypeDataInBand, ++ 0); ++ // If we failed here, we might as well return and have a leak rather than continue and a bugchk ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC, "unable to send revoke send buffer to netvsp"); ++ DPRINT_EXIT(NETVSC); ++ return -1; ++ } ++ } ++ ++ // Teardown the gpadl on the vsp end ++ if (NetDevice->SendBufferGpadlHandle) ++ { ++ DPRINT_INFO(NETVSC, "Tearing down send buffer's GPADL..."); ++ ++ ret = NetDevice->Device->Driver->VmbusChannelInterface.TeardownGpadl(NetDevice->Device, ++ NetDevice->SendBufferGpadlHandle); ++ ++ // If we failed here, we might as well return and have a leak rather than continue and a bugchk ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC, "unable to teardown send buffer's gpadl"); ++ DPRINT_EXIT(NETVSC); ++ return -1; ++ } ++ NetDevice->SendBufferGpadlHandle = 0; ++ } ++ ++ if (NetDevice->SendBuffer) ++ { ++ DPRINT_INFO(NETVSC, "Freeing up send buffer..."); ++ ++ // Free up the receive buffer ++ PageFree(NetDevice->SendBuffer, NetDevice->SendBufferSize >> PAGE_SHIFT); ++ NetDevice->SendBuffer = NULL; ++ } ++ ++ DPRINT_EXIT(NETVSC); ++ ++ return ret; ++} ++ ++ ++ ++static int ++NetVscConnectToVsp( ++ DEVICE_OBJECT *Device ++ ) ++{ ++ int ret=0; ++ NETVSC_DEVICE *netDevice; ++ NVSP_MESSAGE *initPacket; ++ int ndisVersion; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ netDevice = GetOutboundNetDevice(Device); ++ if (!netDevice) ++ { ++ DPRINT_ERR(NETVSC, "unable to get net device...device being destroyed?"); ++ DPRINT_EXIT(NETVSC); ++ return -1; ++ } ++ ++ initPacket = &netDevice->ChannelInitPacket; ++ ++ memset(initPacket, 0, sizeof(NVSP_MESSAGE)); ++ initPacket->Header.MessageType = NvspMessageTypeInit; ++ initPacket->Messages.InitMessages.Init.MinProtocolVersion = NVSP_MIN_PROTOCOL_VERSION; ++ initPacket->Messages.InitMessages.Init.MaxProtocolVersion = NVSP_MAX_PROTOCOL_VERSION; ++ ++ DPRINT_INFO(NETVSC, "Sending NvspMessageTypeInit..."); ++ ++ // Send the init request ++ ret = Device->Driver->VmbusChannelInterface.SendPacket(Device, ++ initPacket, ++ sizeof(NVSP_MESSAGE), ++ (ULONG_PTR)initPacket, ++ VmbusPacketTypeDataInBand, ++ VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED); ++ ++ if( ret != 0) ++ { ++ DPRINT_ERR(NETVSC, "unable to send NvspMessageTypeInit"); ++ goto Cleanup; ++ } ++ ++ WaitEventWait(netDevice->ChannelInitEvent); ++ ++ // Now, check the response ++ //ASSERT(initPacket->Messages.InitMessages.InitComplete.MaximumMdlChainLength <= MAX_MULTIPAGE_BUFFER_COUNT); ++ DPRINT_INFO(NETVSC, "NvspMessageTypeInit status(%d) max mdl chain (%d)", ++ initPacket->Messages.InitMessages.InitComplete.Status, ++ initPacket->Messages.InitMessages.InitComplete.MaximumMdlChainLength); ++ ++ if (initPacket->Messages.InitMessages.InitComplete.Status != NvspStatusSuccess) ++ { ++ DPRINT_ERR(NETVSC, "unable to initialize with netvsp (status 0x%x)", initPacket->Messages.InitMessages.InitComplete.Status); ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ if (initPacket->Messages.InitMessages.InitComplete.NegotiatedProtocolVersion != NVSP_PROTOCOL_VERSION_1) ++ { ++ DPRINT_ERR(NETVSC, "unable to initialize with netvsp (version expected 1 got %d)", ++ initPacket->Messages.InitMessages.InitComplete.NegotiatedProtocolVersion); ++ ret = -1; ++ goto Cleanup; ++ } ++ DPRINT_INFO(NETVSC, "Sending NvspMessage1TypeSendNdisVersion..."); ++ ++ // Send the ndis version ++ memset(initPacket, 0, sizeof(NVSP_MESSAGE)); ++ ++ ndisVersion = 0x00050000; ++ ++ initPacket->Header.MessageType = NvspMessage1TypeSendNdisVersion; ++ initPacket->Messages.Version1Messages.SendNdisVersion.NdisMajorVersion = (ndisVersion & 0xFFFF0000) >> 16; ++ initPacket->Messages.Version1Messages.SendNdisVersion.NdisMinorVersion = ndisVersion & 0xFFFF; ++ ++ // Send the init request ++ ret = Device->Driver->VmbusChannelInterface.SendPacket(Device, ++ initPacket, ++ sizeof(NVSP_MESSAGE), ++ (ULONG_PTR)initPacket, ++ VmbusPacketTypeDataInBand, ++ 0); ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC, "unable to send NvspMessage1TypeSendNdisVersion"); ++ ret = -1; ++ goto Cleanup; ++ } ++ // ++ // BUGBUG - We have to wait for the above msg since the netvsp uses KMCL which acknowledges packet (completion packet) ++ // since our Vmbus always set the VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED flag ++ //WaitEventWait(NetVscChannel->ChannelInitEvent); ++ ++ // Post the big receive buffer to NetVSP ++ ret = NetVscInitializeReceiveBufferWithNetVsp(Device); ++ if (ret == 0) ++ { ++ ret = NetVscInitializeSendBufferWithNetVsp(Device); ++ } ++ ++Cleanup: ++ PutNetDevice(Device); ++ DPRINT_EXIT(NETVSC); ++ return ret; ++} ++ ++static void ++NetVscDisconnectFromVsp( ++ NETVSC_DEVICE *NetDevice ++ ) ++{ ++ DPRINT_ENTER(NETVSC); ++ ++ NetVscDestroyReceiveBuffer(NetDevice); ++ NetVscDestroySendBuffer(NetDevice); ++ ++ DPRINT_EXIT(NETVSC); ++} ++ ++ ++/*++ ++ ++Name: ++ NetVscOnDeviceAdd() ++ ++Description: ++ Callback when the device belonging to this driver is added ++ ++--*/ ++int ++NetVscOnDeviceAdd( ++ DEVICE_OBJECT *Device, ++ void *AdditionalInfo ++ ) ++{ ++ int ret=0; ++ int i; ++ ++ NETVSC_DEVICE* netDevice; ++ NETVSC_PACKET* packet; ++ LIST_ENTRY *entry; ++ ++ NETVSC_DRIVER_OBJECT *netDriver = (NETVSC_DRIVER_OBJECT*) Device->Driver;; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ netDevice = AllocNetDevice(Device); ++ if (!netDevice) ++ { ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ DPRINT_DBG(NETVSC, "netvsc channel object allocated - %p", netDevice); ++ ++ // Initialize the NetVSC channel extension ++ netDevice->ReceiveBufferSize = NETVSC_RECEIVE_BUFFER_SIZE; ++ netDevice->ReceivePacketListLock = SpinlockCreate(); ++ ++ netDevice->SendBufferSize = NETVSC_SEND_BUFFER_SIZE; ++ ++ INITIALIZE_LIST_HEAD(&netDevice->ReceivePacketList); ++ ++ for (i=0; i < NETVSC_RECEIVE_PACKETLIST_COUNT; i++) ++ { ++ packet = MemAllocZeroed(sizeof(NETVSC_PACKET) + (NETVSC_RECEIVE_SG_COUNT* sizeof(PAGE_BUFFER))); ++ if (!packet) ++ { ++ DPRINT_DBG(NETVSC, "unable to allocate netvsc pkts for receive pool (wanted %d got %d)", NETVSC_RECEIVE_PACKETLIST_COUNT, i); ++ break; ++ } ++ ++ INSERT_TAIL_LIST(&netDevice->ReceivePacketList, &packet->ListEntry); ++ } ++ netDevice->ChannelInitEvent = WaitEventCreate(); ++ ++ // Open the channel ++ ret = Device->Driver->VmbusChannelInterface.Open(Device, ++ netDriver->RingBufferSize, ++ netDriver->RingBufferSize, ++ NULL, 0, ++ NetVscOnChannelCallback, ++ Device ++ ); ++ ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC, "unable to open channel: %d", ret); ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ // Channel is opened ++ DPRINT_INFO(NETVSC, "*** NetVSC channel opened successfully! ***"); ++ ++ // Connect with the NetVsp ++ ret = NetVscConnectToVsp(Device); ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC, "unable to connect to NetVSP - %d", ret); ++ ret = -1; ++ goto Close; ++ } ++ ++ DPRINT_INFO(NETVSC, "*** NetVSC channel handshake result - %d ***", ret); ++ ++ DPRINT_EXIT(NETVSC); ++ return ret; ++ ++Close: ++ // Now, we can close the channel safely ++ Device->Driver->VmbusChannelInterface.Close(Device); ++ ++Cleanup: ++ ++ if (netDevice) ++ { ++ WaitEventClose(netDevice->ChannelInitEvent); ++ ++ while (!IsListEmpty(&netDevice->ReceivePacketList)) ++ { ++ entry = REMOVE_HEAD_LIST(&netDevice->ReceivePacketList); ++ packet = CONTAINING_RECORD(entry, NETVSC_PACKET, ListEntry); ++ MemFree(packet); ++ } ++ ++ SpinlockClose(netDevice->ReceivePacketListLock); ++ ++ ReleaseOutboundNetDevice(Device); ++ ReleaseInboundNetDevice(Device); ++ ++ FreeNetDevice(netDevice); ++ } ++ ++ DPRINT_EXIT(NETVSC); ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: ++ NetVscOnDeviceRemove() ++ ++Description: ++ Callback when the root bus device is removed ++ ++--*/ ++int ++NetVscOnDeviceRemove( ++ DEVICE_OBJECT *Device ++ ) ++{ ++ NETVSC_DEVICE *netDevice; ++ NETVSC_PACKET *netvscPacket; ++ int ret=0; ++ LIST_ENTRY *entry; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ DPRINT_INFO(NETVSC, "Disabling outbound traffic on net device (%p)...", Device->Extension); ++ ++ // Stop outbound traffic ie sends and receives completions ++ netDevice = ReleaseOutboundNetDevice(Device); ++ if (!netDevice) ++ { ++ DPRINT_ERR(NETVSC, "No net device present!!"); ++ return -1; ++ } ++ ++ // Wait for all send completions ++ while (netDevice->NumOutstandingSends) ++ { ++ DPRINT_INFO(NETVSC, "waiting for %d requests to complete...", netDevice->NumOutstandingSends); ++ ++ Sleep(100); ++ } ++ ++ DPRINT_INFO(NETVSC, "Disconnecting from netvsp..."); ++ ++ NetVscDisconnectFromVsp(netDevice); ++ ++ DPRINT_INFO(NETVSC, "Disabling inbound traffic on net device (%p)...", Device->Extension); ++ ++ // Stop inbound traffic ie receives and sends completions ++ netDevice = ReleaseInboundNetDevice(Device); ++ ++ // At this point, no one should be accessing netDevice except in here ++ DPRINT_INFO(NETVSC, "net device (%p) safe to remove", netDevice); ++ ++ // Now, we can close the channel safely ++ Device->Driver->VmbusChannelInterface.Close(Device); ++ ++ // Release all resources ++ while (!IsListEmpty(&netDevice->ReceivePacketList)) ++ { ++ entry = REMOVE_HEAD_LIST(&netDevice->ReceivePacketList); ++ netvscPacket = CONTAINING_RECORD(entry, NETVSC_PACKET, ListEntry); ++ ++ MemFree(netvscPacket); ++ } ++ ++ SpinlockClose(netDevice->ReceivePacketListLock); ++ WaitEventClose(netDevice->ChannelInitEvent); ++ FreeNetDevice(netDevice); ++ ++ DPRINT_EXIT(NETVSC); ++ return ret; ++} ++ ++ ++ ++/*++ ++ ++Name: ++ NetVscOnCleanup() ++ ++Description: ++ Perform any cleanup when the driver is removed ++ ++--*/ ++void ++NetVscOnCleanup( ++ DRIVER_OBJECT *drv ++ ) ++{ ++ DPRINT_ENTER(NETVSC); ++ ++ DPRINT_EXIT(NETVSC); ++} ++ ++static void ++NetVscOnSendCompletion( ++ DEVICE_OBJECT *Device, ++ VMPACKET_DESCRIPTOR *Packet ++ ) ++{ ++ NETVSC_DEVICE* netDevice; ++ NVSP_MESSAGE *nvspPacket; ++ NETVSC_PACKET *nvscPacket; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ netDevice = GetInboundNetDevice(Device); ++ if (!netDevice) ++ { ++ DPRINT_ERR(NETVSC, "unable to get net device...device being destroyed?"); ++ DPRINT_EXIT(NETVSC); ++ return; ++ } ++ ++ nvspPacket = (NVSP_MESSAGE*)((ULONG_PTR)Packet + (Packet->DataOffset8 << 3)); ++ ++ DPRINT_DBG(NETVSC, "send completion packet - type %d", nvspPacket->Header.MessageType); ++ ++ if (nvspPacket->Header.MessageType == NvspMessageTypeInitComplete || ++ nvspPacket->Header.MessageType == NvspMessage1TypeSendReceiveBufferComplete || ++ nvspPacket->Header.MessageType == NvspMessage1TypeSendSendBufferComplete) ++ { ++ // Copy the response back ++ memcpy(&netDevice->ChannelInitPacket, nvspPacket, sizeof(NVSP_MESSAGE)); ++ WaitEventSet(netDevice->ChannelInitEvent); ++ } ++ else if (nvspPacket->Header.MessageType == NvspMessage1TypeSendRNDISPacketComplete) ++ { ++ // Get the send context ++ nvscPacket = (NETVSC_PACKET *)(ULONG_PTR)Packet->TransactionId; ++ ASSERT(nvscPacket); ++ ++ // Notify the layer above us ++ nvscPacket->Completion.Send.OnSendCompletion(nvscPacket->Completion.Send.SendCompletionContext); ++ ++ InterlockedDecrement(&netDevice->NumOutstandingSends); ++ } ++ else ++ { ++ DPRINT_ERR(NETVSC, "Unknown send completion packet type - %d received!!", nvspPacket->Header.MessageType); ++ } ++ ++ PutNetDevice(Device); ++ DPRINT_EXIT(NETVSC); ++} ++ ++ ++ ++static int ++NetVscOnSend( ++ DEVICE_OBJECT *Device, ++ NETVSC_PACKET *Packet ++ ) ++{ ++ NETVSC_DEVICE* netDevice; ++ int ret=0; ++ ++ NVSP_MESSAGE sendMessage; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ netDevice = GetOutboundNetDevice(Device); ++ if (!netDevice) ++ { ++ DPRINT_ERR(NETVSC, "net device (%p) shutting down...ignoring outbound packets", netDevice); ++ DPRINT_EXIT(NETVSC); ++ return -2; ++ } ++ ++ sendMessage.Header.MessageType = NvspMessage1TypeSendRNDISPacket; ++ if (Packet->IsDataPacket) ++ sendMessage.Messages.Version1Messages.SendRNDISPacket.ChannelType = 0;// 0 is RMC_DATA; ++ else ++ sendMessage.Messages.Version1Messages.SendRNDISPacket.ChannelType = 1;// 1 is RMC_CONTROL; ++ ++ // Not using send buffer section ++ sendMessage.Messages.Version1Messages.SendRNDISPacket.SendBufferSectionIndex = 0xFFFFFFFF; ++ sendMessage.Messages.Version1Messages.SendRNDISPacket.SendBufferSectionSize = 0; ++ ++ if (Packet->PageBufferCount) ++ { ++ ret = Device->Driver->VmbusChannelInterface.SendPacketPageBuffer(Device, ++ Packet->PageBuffers, ++ Packet->PageBufferCount, ++ &sendMessage, ++ sizeof(NVSP_MESSAGE), ++ (ULONG_PTR)Packet); ++ } ++ else ++ { ++ ret = Device->Driver->VmbusChannelInterface.SendPacket(Device, ++ &sendMessage, ++ sizeof(NVSP_MESSAGE), ++ (ULONG_PTR)Packet, ++ VmbusPacketTypeDataInBand, ++ VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED); ++ ++ } ++ ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC, "Unable to send packet %p ret %d", Packet, ret); ++ } ++ ++ InterlockedIncrement(&netDevice->NumOutstandingSends); ++ PutNetDevice(Device); ++ ++ DPRINT_EXIT(NETVSC); ++ return ret; ++} ++ ++ ++static void ++NetVscOnReceive( ++ DEVICE_OBJECT *Device, ++ VMPACKET_DESCRIPTOR *Packet ++ ) ++{ ++ NETVSC_DEVICE* netDevice; ++ VMTRANSFER_PAGE_PACKET_HEADER *vmxferpagePacket; ++ NVSP_MESSAGE *nvspPacket; ++ NETVSC_PACKET *netvscPacket=NULL; ++ LIST_ENTRY* entry; ++ ULONG_PTR start; ++ ULONG_PTR end, endVirtual; ++ //NETVSC_DRIVER_OBJECT *netvscDriver; ++ XFERPAGE_PACKET *xferpagePacket=NULL; ++ LIST_ENTRY listHead; ++ ++ int i=0, j=0; ++ int count=0, bytesRemain=0; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ netDevice = GetInboundNetDevice(Device); ++ if (!netDevice) ++ { ++ DPRINT_ERR(NETVSC, "unable to get net device...device being destroyed?"); ++ DPRINT_EXIT(NETVSC); ++ return; ++ } ++ ++ // All inbound packets other than send completion should be xfer page packet ++ if (Packet->Type != VmbusPacketTypeDataUsingTransferPages) ++ { ++ DPRINT_ERR(NETVSC, "Unknown packet type received - %d", Packet->Type); ++ PutNetDevice(Device); ++ return; ++ } ++ ++ nvspPacket = (NVSP_MESSAGE*)((ULONG_PTR)Packet + (Packet->DataOffset8 << 3)); ++ ++ // Make sure this is a valid nvsp packet ++ if (nvspPacket->Header.MessageType != NvspMessage1TypeSendRNDISPacket ) ++ { ++ DPRINT_ERR(NETVSC, "Unknown nvsp packet type received - %d", nvspPacket->Header.MessageType); ++ PutNetDevice(Device); ++ return; ++ } ++ ++ DPRINT_DBG(NETVSC, "NVSP packet received - type %d", nvspPacket->Header.MessageType); ++ ++ vmxferpagePacket = (VMTRANSFER_PAGE_PACKET_HEADER*)Packet; ++ ++ if (vmxferpagePacket->TransferPageSetId != NETVSC_RECEIVE_BUFFER_ID) ++ { ++ DPRINT_ERR(NETVSC, "Invalid xfer page set id - expecting %x got %x", NETVSC_RECEIVE_BUFFER_ID, vmxferpagePacket->TransferPageSetId); ++ PutNetDevice(Device); ++ return; ++ } ++ ++ DPRINT_DBG(NETVSC, "xfer page - range count %d", vmxferpagePacket->RangeCount); ++ ++ INITIALIZE_LIST_HEAD(&listHead); ++ ++ // Grab free packets (range count + 1) to represent this xfer page packet. +1 to represent ++ // the xfer page packet itself. We grab it here so that we know exactly how many we can fulfil ++ SpinlockAcquire(netDevice->ReceivePacketListLock); ++ while (!IsListEmpty(&netDevice->ReceivePacketList)) ++ { ++ entry = REMOVE_HEAD_LIST(&netDevice->ReceivePacketList); ++ netvscPacket = CONTAINING_RECORD(entry, NETVSC_PACKET, ListEntry); ++ ++ INSERT_TAIL_LIST(&listHead, &netvscPacket->ListEntry); ++ ++ if (++count == vmxferpagePacket->RangeCount + 1) ++ break; ++ } ++ SpinlockRelease(netDevice->ReceivePacketListLock); ++ ++ // We need at least 2 netvsc pkts (1 to represent the xfer page and at least 1 for the range) ++ // i.e. we can handled some of the xfer page packet ranges... ++ if (count < 2) ++ { ++ DPRINT_ERR(NETVSC, "Got only %d netvsc pkt...needed %d pkts. Dropping this xfer page packet completely!", count, vmxferpagePacket->RangeCount+1); ++ ++ // Return it to the freelist ++ SpinlockAcquire(netDevice->ReceivePacketListLock); ++ for (i=count; i != 0; i--) ++ { ++ entry = REMOVE_HEAD_LIST(&listHead); ++ netvscPacket = CONTAINING_RECORD(entry, NETVSC_PACKET, ListEntry); ++ ++ INSERT_TAIL_LIST(&netDevice->ReceivePacketList, &netvscPacket->ListEntry); ++ } ++ SpinlockRelease(netDevice->ReceivePacketListLock); ++ ++ NetVscSendReceiveCompletion(Device, vmxferpagePacket->d.TransactionId); ++ ++ PutNetDevice(Device); ++ return; ++ } ++ ++ // Remove the 1st packet to represent the xfer page packet itself ++ entry = REMOVE_HEAD_LIST(&listHead); ++ xferpagePacket = CONTAINING_RECORD(entry, XFERPAGE_PACKET, ListEntry); ++ xferpagePacket->Count = count - 1; // This is how much we can satisfy ++ ASSERT(xferpagePacket->Count > 0 && xferpagePacket->Count <= vmxferpagePacket->RangeCount); ++ ++ if (xferpagePacket->Count != vmxferpagePacket->RangeCount) ++ { ++ DPRINT_INFO(NETVSC, "Needed %d netvsc pkts to satisy this xfer page...got %d", vmxferpagePacket->RangeCount, xferpagePacket->Count); ++ } ++ ++ // Each range represents 1 RNDIS pkt that contains 1 ethernet frame ++ for (i=0; i < (count - 1); i++) ++ { ++ entry = REMOVE_HEAD_LIST(&listHead); ++ netvscPacket = CONTAINING_RECORD(entry, NETVSC_PACKET, ListEntry); ++ ++ // Initialize the netvsc packet ++ netvscPacket->XferPagePacket = xferpagePacket; ++ netvscPacket->Completion.Recv.OnReceiveCompletion = NetVscOnReceiveCompletion; ++ netvscPacket->Completion.Recv.ReceiveCompletionContext = netvscPacket; ++ netvscPacket->Device = Device; ++ netvscPacket->Completion.Recv.ReceiveCompletionTid = vmxferpagePacket->d.TransactionId; // Save this so that we can send it back ++ ++ netvscPacket->TotalDataBufferLength = vmxferpagePacket->Ranges[i].ByteCount; ++ netvscPacket->PageBufferCount = 1; ++ ++ ASSERT(vmxferpagePacket->Ranges[i].ByteOffset + vmxferpagePacket->Ranges[i].ByteCount < netDevice->ReceiveBufferSize); ++ ++ netvscPacket->PageBuffers[0].Length = vmxferpagePacket->Ranges[i].ByteCount; ++ ++ start = GetPhysicalAddress((void*)((ULONG_PTR)netDevice->ReceiveBuffer + vmxferpagePacket->Ranges[i].ByteOffset)); ++ ++ netvscPacket->PageBuffers[0].Pfn = start >> PAGE_SHIFT; ++ endVirtual = (ULONG_PTR)netDevice->ReceiveBuffer ++ + vmxferpagePacket->Ranges[i].ByteOffset ++ + vmxferpagePacket->Ranges[i].ByteCount -1; ++ end = GetPhysicalAddress((void*)endVirtual); ++ ++ // Calculate the page relative offset ++ netvscPacket->PageBuffers[0].Offset = vmxferpagePacket->Ranges[i].ByteOffset & (PAGE_SIZE -1); ++ if ((end >> PAGE_SHIFT) != (start>>PAGE_SHIFT)) { ++ //Handle frame across multiple pages: ++ netvscPacket->PageBuffers[0].Length = ++ (netvscPacket->PageBuffers[0].Pfn <TotalDataBufferLength - netvscPacket->PageBuffers[0].Length; ++ for (j=1; jPageBuffers[j].Offset = 0; ++ if (bytesRemain <= PAGE_SIZE) { ++ netvscPacket->PageBuffers[j].Length = bytesRemain; ++ bytesRemain = 0; ++ } else { ++ netvscPacket->PageBuffers[j].Length = PAGE_SIZE; ++ bytesRemain -= PAGE_SIZE; ++ } ++ netvscPacket->PageBuffers[j].Pfn = ++ GetPhysicalAddress((void*)(endVirtual - bytesRemain)) >> PAGE_SHIFT; ++ netvscPacket->PageBufferCount++; ++ if (bytesRemain == 0) ++ break; ++ } ++ ASSERT(bytesRemain == 0); ++ } ++ DPRINT_DBG(NETVSC, "[%d] - (abs offset %u len %u) => (pfn %llx, offset %u, len %u)", ++ i, ++ vmxferpagePacket->Ranges[i].ByteOffset, ++ vmxferpagePacket->Ranges[i].ByteCount, ++ netvscPacket->PageBuffers[0].Pfn, ++ netvscPacket->PageBuffers[0].Offset, ++ netvscPacket->PageBuffers[0].Length); ++ ++ // Pass it to the upper layer ++ ((NETVSC_DRIVER_OBJECT*)Device->Driver)->OnReceiveCallback(Device, netvscPacket); ++ ++ NetVscOnReceiveCompletion(netvscPacket->Completion.Recv.ReceiveCompletionContext); ++ } ++ ++ ASSERT(IsListEmpty(&listHead)); ++ ++ PutNetDevice(Device); ++ DPRINT_EXIT(NETVSC); ++} ++ ++ ++static void ++NetVscSendReceiveCompletion( ++ DEVICE_OBJECT *Device, ++ UINT64 TransactionId ++ ) ++{ ++ NVSP_MESSAGE recvcompMessage; ++ int retries=0; ++ int ret=0; ++ ++ DPRINT_DBG(NETVSC, "Sending receive completion pkt - %llx", TransactionId); ++ ++ recvcompMessage.Header.MessageType = NvspMessage1TypeSendRNDISPacketComplete; ++ ++ // FIXME: Pass in the status ++ recvcompMessage.Messages.Version1Messages.SendRNDISPacketComplete.Status = NvspStatusSuccess; ++ ++retry_send_cmplt: ++ // Send the completion ++ ret = Device->Driver->VmbusChannelInterface.SendPacket(Device, ++ &recvcompMessage, ++ sizeof(NVSP_MESSAGE), ++ TransactionId, ++ VmbusPacketTypeCompletion, ++ 0); ++ if (ret == 0) // success ++ { ++ // no-op ++ } ++ else if (ret == -1) // no more room...wait a bit and attempt to retry 3 times ++ { ++ retries++; ++ DPRINT_ERR(NETVSC, "unable to send receive completion pkt (tid %llx)...retrying %d", TransactionId, retries); ++ ++ if (retries < 4) ++ { ++ Sleep(100); ++ goto retry_send_cmplt; ++ } ++ else ++ { ++ DPRINT_ERR(NETVSC, "unable to send receive completion pkt (tid %llx)...give up retrying", TransactionId); ++ } ++ } ++ else ++ { ++ DPRINT_ERR(NETVSC, "unable to send receive completion pkt - %llx", TransactionId); ++ } ++} ++ ++// ++// Send a receive completion packet to RNDIS device (ie NetVsp) ++// ++static void ++NetVscOnReceiveCompletion( ++ PVOID Context) ++{ ++ NETVSC_PACKET *packet = (NETVSC_PACKET*)Context; ++ DEVICE_OBJECT *device = (DEVICE_OBJECT*)packet->Device; ++ NETVSC_DEVICE* netDevice; ++ UINT64 transactionId=0; ++ BOOL fSendReceiveComp = FALSE; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ ASSERT(packet->XferPagePacket); ++ ++ // Even though it seems logical to do a GetOutboundNetDevice() here to send out receive completion, ++ // we are using GetInboundNetDevice() since we may have disable outbound traffic already. ++ netDevice = GetInboundNetDevice(device); ++ if (!netDevice) ++ { ++ DPRINT_ERR(NETVSC, "unable to get net device...device being destroyed?"); ++ DPRINT_EXIT(NETVSC); ++ return; ++ } ++ ++ // Overloading use of the lock. ++ SpinlockAcquire(netDevice->ReceivePacketListLock); ++ ++ ASSERT(packet->XferPagePacket->Count > 0); ++ packet->XferPagePacket->Count--; ++ ++ // Last one in the line that represent 1 xfer page packet. ++ // Return the xfer page packet itself to the freelist ++ if (packet->XferPagePacket->Count == 0) ++ { ++ fSendReceiveComp = TRUE; ++ transactionId = packet->Completion.Recv.ReceiveCompletionTid; ++ ++ INSERT_TAIL_LIST(&netDevice->ReceivePacketList, &packet->XferPagePacket->ListEntry); ++ } ++ ++ // Put the packet back ++ INSERT_TAIL_LIST(&netDevice->ReceivePacketList, &packet->ListEntry); ++ SpinlockRelease(netDevice->ReceivePacketListLock); ++ ++ // Send a receive completion for the xfer page packet ++ if (fSendReceiveComp) ++ { ++ NetVscSendReceiveCompletion(device, transactionId); ++ } ++ ++ PutNetDevice(device); ++ DPRINT_EXIT(NETVSC); ++} ++ ++ ++ ++void ++NetVscOnChannelCallback( ++ PVOID Context ++ ) ++{ ++ const int netPacketSize=2048; ++ int ret=0; ++ DEVICE_OBJECT *device=(DEVICE_OBJECT*)Context; ++ NETVSC_DEVICE *netDevice; ++ ++ UINT32 bytesRecvd; ++ UINT64 requestId; ++ UCHAR packet[netPacketSize]; ++ VMPACKET_DESCRIPTOR *desc; ++ UCHAR *buffer=packet; ++ int bufferlen=netPacketSize; ++ ++ ++ DPRINT_ENTER(NETVSC); ++ ++ ASSERT(device); ++ ++ netDevice = GetInboundNetDevice(device); ++ if (!netDevice) ++ { ++ DPRINT_ERR(NETVSC, "net device (%p) shutting down...ignoring inbound packets", netDevice); ++ DPRINT_EXIT(NETVSC); ++ return; ++ } ++ ++ do ++ { ++ ret = device->Driver->VmbusChannelInterface.RecvPacketRaw(device, ++ buffer, ++ bufferlen, ++ &bytesRecvd, ++ &requestId); ++ ++ if (ret == 0) ++ { ++ if (bytesRecvd > 0) ++ { ++ DPRINT_DBG(NETVSC, "receive %d bytes, tid %llx", bytesRecvd, requestId); ++ ++ desc = (VMPACKET_DESCRIPTOR*)buffer; ++ switch (desc->Type) ++ { ++ case VmbusPacketTypeCompletion: ++ NetVscOnSendCompletion(device, desc); ++ break; ++ ++ case VmbusPacketTypeDataUsingTransferPages: ++ NetVscOnReceive(device, desc); ++ break; ++ ++ default: ++ DPRINT_ERR(NETVSC, "unhandled packet type %d, tid %llx len %d\n", desc->Type, requestId, bytesRecvd); ++ break; ++ } ++ ++ // reset ++ if (bufferlen > netPacketSize) ++ { ++ MemFree(buffer); ++ ++ buffer = packet; ++ bufferlen = netPacketSize; ++ } ++ } ++ else ++ { ++ //DPRINT_DBG(NETVSC, "nothing else to read..."); ++ ++ // reset ++ if (bufferlen > netPacketSize) ++ { ++ MemFree(buffer); ++ ++ buffer = packet; ++ bufferlen = netPacketSize; ++ } ++ ++ break; ++ } ++ } ++ else if (ret == -2) // Handle large packet ++ { ++ buffer = MemAllocAtomic(bytesRecvd); ++ if (buffer == NULL) ++ { ++ // Try again next time around ++ DPRINT_ERR(NETVSC, "unable to allocate buffer of size (%d)!!", bytesRecvd); ++ break; ++ } ++ ++ bufferlen = bytesRecvd; ++ } ++ else ++ { ++ ASSERT(0); ++ } ++ } while (1); ++ ++ PutNetDevice(device); ++ DPRINT_EXIT(NETVSC); ++ return; ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/netvsc_drv.c linux-2.6.27.29-0.1.1/drivers/staging/hv/netvsc_drv.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/netvsc_drv.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,721 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Hank Janssen ++ * ++ */ ++ ++#define KERNEL_2_6_27 ++ ++#include ++#include ++#include ++#include ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++#include ++#else ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "include/logging.h" ++#include "include/vmbus.h" ++ ++#include "include/NetVscApi.h" ++ ++MODULE_LICENSE("GPL"); ++ ++// ++// Static decl ++// ++static int netvsc_probe(struct device *device); ++static int netvsc_remove(struct device *device); ++static int netvsc_open(struct net_device *net); ++static void netvsc_xmit_completion(void *context); ++static int netvsc_start_xmit (struct sk_buff *skb, struct net_device *net); ++static int netvsc_recv_callback(DEVICE_OBJECT *device_obj, NETVSC_PACKET* Packet); ++static int netvsc_close(struct net_device *net); ++static struct net_device_stats *netvsc_get_stats(struct net_device *net); ++static void netvsc_linkstatus_callback(DEVICE_OBJECT *device_obj, unsigned int status); ++ ++// ++// Data types ++// ++struct net_device_context { ++ struct device_context *device_ctx; // point back to our device context ++ struct net_device_stats stats; ++}; ++ ++struct netvsc_driver_context { ++ // !! These must be the first 2 fields !! ++ struct driver_context drv_ctx; ++ NETVSC_DRIVER_OBJECT drv_obj; ++}; ++ ++// ++// Globals ++// ++ ++static int netvsc_ringbuffer_size = NETVSC_DEVICE_RING_BUFFER_SIZE; ++ ++// The one and only one ++static struct netvsc_driver_context g_netvsc_drv; ++ ++// ++// Routines ++// ++ ++/*++ ++ ++Name: netvsc_drv_init() ++ ++Desc: NetVsc driver initialization ++ ++--*/ ++int netvsc_drv_init(PFN_DRIVERINITIALIZE pfn_drv_init) ++{ ++ int ret=0; ++ NETVSC_DRIVER_OBJECT *net_drv_obj=&g_netvsc_drv.drv_obj; ++ struct driver_context *drv_ctx=&g_netvsc_drv.drv_ctx; ++ ++ DPRINT_ENTER(NETVSC_DRV); ++ ++ vmbus_get_interface(&net_drv_obj->Base.VmbusChannelInterface); ++ ++ net_drv_obj->RingBufferSize = netvsc_ringbuffer_size; ++ net_drv_obj->OnReceiveCallback = netvsc_recv_callback; ++ net_drv_obj->OnLinkStatusChanged = netvsc_linkstatus_callback; ++ ++ // Callback to client driver to complete the initialization ++ pfn_drv_init(&net_drv_obj->Base); ++ ++ drv_ctx->driver.name = net_drv_obj->Base.name; ++ memcpy(&drv_ctx->class_id, &net_drv_obj->Base.deviceType, sizeof(GUID)); ++ ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++ drv_ctx->driver.probe = netvsc_probe; ++ drv_ctx->driver.remove = netvsc_remove; ++#else ++ drv_ctx->probe = netvsc_probe; ++ drv_ctx->remove = netvsc_remove; ++#endif ++ ++ // The driver belongs to vmbus ++ vmbus_child_driver_register(drv_ctx); ++ ++ DPRINT_EXIT(NETVSC_DRV); ++ ++ return ret; ++} ++ ++/*++ ++ ++Name: netvsc_get_stats() ++ ++Desc: Get the network stats ++ ++--*/ ++static struct net_device_stats *netvsc_get_stats(struct net_device *net) ++{ ++ struct net_device_context *net_device_ctx = netdev_priv(net); ++ ++ return &net_device_ctx->stats; ++} ++ ++/*++ ++ ++Name: netvsc_set_multicast_list() ++ ++Desc: Set the multicast list ++ ++Remark: No-op here ++--*/ ++static void netvsc_set_multicast_list(UNUSED_VAR(struct net_device *net)) ++{ ++} ++ ++ ++/*++ ++ ++Name: netvsc_probe() ++ ++Desc: Add the specified new device to this driver ++ ++--*/ ++static int netvsc_probe(struct device *device) ++{ ++ int ret=0; ++ ++ struct driver_context *driver_ctx = driver_to_driver_context(device->driver); ++ struct netvsc_driver_context *net_drv_ctx = (struct netvsc_driver_context*)driver_ctx; ++ NETVSC_DRIVER_OBJECT *net_drv_obj = &net_drv_ctx->drv_obj; ++ ++ struct device_context *device_ctx = device_to_device_context(device); ++ DEVICE_OBJECT *device_obj = &device_ctx->device_obj; ++ ++ struct net_device *net = NULL; ++ struct net_device_context *net_device_ctx; ++ NETVSC_DEVICE_INFO device_info; ++ ++ DPRINT_ENTER(NETVSC_DRV); ++ ++ if (!net_drv_obj->Base.OnDeviceAdd) ++ { ++ return -1; ++ } ++ ++ net = alloc_netdev(sizeof(struct net_device_context), "seth%d", ether_setup); ++ //net = alloc_etherdev(sizeof(struct net_device_context)); ++ if (!net) ++ { ++ return -1; ++ } ++ ++ // Set initial state ++ netif_carrier_off(net); ++ netif_stop_queue(net); ++ ++ net_device_ctx = netdev_priv(net); ++ net_device_ctx->device_ctx = device_ctx; ++ device->driver_data = net; ++ ++ // Notify the netvsc driver of the new device ++ ret = net_drv_obj->Base.OnDeviceAdd(device_obj, (void*)&device_info); ++ if (ret != 0) ++ { ++ free_netdev(net); ++ device->driver_data = NULL; ++ ++ DPRINT_ERR(NETVSC_DRV, "unable to add netvsc device (ret %d)", ret); ++ return ret; ++ } ++ ++ // If carrier is still off ie we did not get a link status callback, update it if necessary ++ // FIXME: We should use a atomic or test/set instead to avoid getting out of sync with the device's link status ++ if (!netif_carrier_ok(net)) ++ { ++ if (!device_info.LinkState) ++ { ++ netif_carrier_on(net); ++ } ++ } ++ ++ memcpy(net->dev_addr, device_info.MacAddr, ETH_ALEN); ++ ++ net->open = netvsc_open; ++ net->hard_start_xmit = netvsc_start_xmit; ++ net->stop = netvsc_close; ++ net->get_stats = netvsc_get_stats; ++ net->set_multicast_list = netvsc_set_multicast_list; ++ ++#if !defined(KERNEL_2_6_27) ++ SET_MODULE_OWNER(net); ++#endif ++ SET_NETDEV_DEV(net, device); ++ ++ ret = register_netdev(net); ++ if (ret != 0) ++ { ++ // Remove the device and release the resource ++ net_drv_obj->Base.OnDeviceRemove(device_obj); ++ free_netdev(net); ++ } ++ ++ DPRINT_EXIT(NETVSC_DRV); ++ ++ return ret; ++} ++ ++static int netvsc_remove(struct device *device) ++{ ++ int ret=0; ++ struct driver_context *driver_ctx = driver_to_driver_context(device->driver); ++ struct netvsc_driver_context *net_drv_ctx = (struct netvsc_driver_context*)driver_ctx; ++ NETVSC_DRIVER_OBJECT *net_drv_obj = &net_drv_ctx->drv_obj; ++ ++ struct device_context *device_ctx = device_to_device_context(device); ++ struct net_device *net = (struct net_device *)device_ctx->device.driver_data; ++ DEVICE_OBJECT *device_obj = &device_ctx->device_obj; ++ ++ DPRINT_ENTER(NETVSC_DRV); ++ ++ if (net == NULL) ++ { ++ DPRINT_INFO(NETVSC, "no net device to remove"); ++ DPRINT_EXIT(NETVSC_DRV); ++ return 0; ++ } ++ ++ if (!net_drv_obj->Base.OnDeviceRemove) ++ { ++ DPRINT_EXIT(NETVSC_DRV); ++ return -1; ++ } ++ ++ // Stop outbound asap ++ netif_stop_queue(net); ++ //netif_carrier_off(net); ++ ++ unregister_netdev(net); ++ ++ // Call to the vsc driver to let it know that the device is being removed ++ ret = net_drv_obj->Base.OnDeviceRemove(device_obj); ++ if (ret != 0) ++ { ++ // TODO: ++ DPRINT_ERR(NETVSC, "unable to remove vsc device (ret %d)", ret); ++ } ++ ++ free_netdev(net); ++ ++ DPRINT_EXIT(NETVSC_DRV); ++ ++ return ret; ++} ++ ++/*++ ++ ++Name: netvsc_open() ++ ++Desc: Open the specified interface device ++ ++--*/ ++static int netvsc_open(struct net_device *net) ++{ ++ int ret=0; ++ struct net_device_context *net_device_ctx = netdev_priv(net); ++ struct driver_context *driver_ctx = driver_to_driver_context(net_device_ctx->device_ctx->device.driver); ++ struct netvsc_driver_context *net_drv_ctx = (struct netvsc_driver_context*)driver_ctx; ++ NETVSC_DRIVER_OBJECT *net_drv_obj = &net_drv_ctx->drv_obj; ++ ++ DEVICE_OBJECT *device_obj = &net_device_ctx->device_ctx->device_obj; ++ ++ DPRINT_ENTER(NETVSC_DRV); ++ ++ if (netif_carrier_ok(net)) ++ { ++ memset(&net_device_ctx->stats, 0 , sizeof(struct net_device_stats)); ++ ++ // Open up the device ++ ret = net_drv_obj->OnOpen(device_obj); ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC_DRV, "unable to open device (ret %d).", ret); ++ return ret; ++ } ++ ++ netif_start_queue(net); ++ } ++ else ++ { ++ DPRINT_ERR(NETVSC_DRV, "unable to open device...link is down."); ++ } ++ ++ DPRINT_EXIT(NETVSC_DRV); ++ return ret; ++} ++ ++/*++ ++ ++Name: netvsc_close() ++ ++Desc: Close the specified interface device ++ ++--*/ ++static int netvsc_close(struct net_device *net) ++{ ++ int ret=0; ++ struct net_device_context *net_device_ctx = netdev_priv(net); ++ struct driver_context *driver_ctx = driver_to_driver_context(net_device_ctx->device_ctx->device.driver); ++ struct netvsc_driver_context *net_drv_ctx = (struct netvsc_driver_context*)driver_ctx; ++ NETVSC_DRIVER_OBJECT *net_drv_obj = &net_drv_ctx->drv_obj; ++ ++ DEVICE_OBJECT *device_obj = &net_device_ctx->device_ctx->device_obj; ++ ++ DPRINT_ENTER(NETVSC_DRV); ++ ++ netif_stop_queue(net); ++ ++ ret = net_drv_obj->OnClose(device_obj); ++ if (ret != 0) ++ { ++ DPRINT_ERR(NETVSC_DRV, "unable to close device (ret %d).", ret); ++ } ++ ++ DPRINT_EXIT(NETVSC_DRV); ++ ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: netvsc_xmit_completion() ++ ++Desc: Send completion processing ++ ++--*/ ++static void netvsc_xmit_completion(void *context) ++{ ++ NETVSC_PACKET *packet = (NETVSC_PACKET *)context; ++ struct sk_buff *skb = (struct sk_buff *)(ULONG_PTR)packet->Completion.Send.SendCompletionTid; ++ struct net_device* net; ++ ++ DPRINT_ENTER(NETVSC_DRV); ++ ++ kfree(packet); ++ ++ if (skb) ++ { ++ net = skb->dev; ++ ++ dev_kfree_skb_any(skb); ++ ++ if (netif_queue_stopped(net)) ++ { ++ DPRINT_INFO(NETVSC_DRV, "net device (%p) waking up...", net); ++ ++ netif_wake_queue(net); ++ } ++ } ++ ++ DPRINT_EXIT(NETVSC_DRV); ++} ++ ++/*++ ++ ++Name: netvsc_start_xmit() ++ ++Desc: Start a send ++ ++--*/ ++static int netvsc_start_xmit (struct sk_buff *skb, struct net_device *net) ++{ ++ int ret=0; ++ struct net_device_context *net_device_ctx = netdev_priv(net); ++ struct driver_context *driver_ctx = driver_to_driver_context(net_device_ctx->device_ctx->device.driver); ++ struct netvsc_driver_context *net_drv_ctx = (struct netvsc_driver_context*)driver_ctx; ++ NETVSC_DRIVER_OBJECT *net_drv_obj = &net_drv_ctx->drv_obj; ++ ++ int i=0; ++ NETVSC_PACKET* packet; ++ int num_frags; ++ int retries=0; ++ ++ DPRINT_ENTER(NETVSC_DRV); ++ ++ // Support only 1 chain of frags ++ ASSERT(skb_shinfo(skb)->frag_list == NULL); ++ ASSERT(skb->dev == net); ++ ++ DPRINT_DBG(NETVSC_DRV, "xmit packet - len %d data_len %d", skb->len, skb->data_len); ++ ++ // Add 1 for skb->data and any additional ones requested ++ num_frags = skb_shinfo(skb)->nr_frags + 1 + net_drv_obj->AdditionalRequestPageBufferCount; ++ ++ // Allocate a netvsc packet based on # of frags. ++ packet = kzalloc(sizeof(NETVSC_PACKET) + (num_frags * sizeof(PAGE_BUFFER)) + net_drv_obj->RequestExtSize, GFP_ATOMIC); ++ if (!packet) ++ { ++ DPRINT_ERR(NETVSC_DRV, "unable to allocate NETVSC_PACKET"); ++ return -1; ++ } ++ ++ packet->Extension = (void*)(unsigned long)packet + sizeof(NETVSC_PACKET) + (num_frags * sizeof(PAGE_BUFFER)) ; ++ ++ // Setup the rndis header ++ packet->PageBufferCount = num_frags; ++ ++ // TODO: Flush all write buffers/ memory fence ??? ++ //wmb(); ++ ++ // Initialize it from the skb ++ ASSERT(skb->data); ++ packet->TotalDataBufferLength = skb->len; ++ ++ // Start filling in the page buffers starting at AdditionalRequestPageBufferCount offset ++ packet->PageBuffers[net_drv_obj->AdditionalRequestPageBufferCount].Pfn = virt_to_phys(skb->data) >> PAGE_SHIFT; ++ packet->PageBuffers[net_drv_obj->AdditionalRequestPageBufferCount].Offset = (unsigned long)skb->data & (PAGE_SIZE -1); ++ packet->PageBuffers[net_drv_obj->AdditionalRequestPageBufferCount].Length = skb->len - skb->data_len; ++ ++ ASSERT((skb->len - skb->data_len) <= PAGE_SIZE); ++ ++ for (i=net_drv_obj->AdditionalRequestPageBufferCount+1; iPageBuffers[i].Pfn = page_to_pfn(skb_shinfo(skb)->frags[i-(net_drv_obj->AdditionalRequestPageBufferCount+1)].page); ++ packet->PageBuffers[i].Offset = skb_shinfo(skb)->frags[i-(net_drv_obj->AdditionalRequestPageBufferCount+1)].page_offset; ++ packet->PageBuffers[i].Length = skb_shinfo(skb)->frags[i-(net_drv_obj->AdditionalRequestPageBufferCount+1)].size; ++ } ++ ++ // Set the completion routine ++ packet->Completion.Send.OnSendCompletion = netvsc_xmit_completion; ++ packet->Completion.Send.SendCompletionContext = packet; ++ packet->Completion.Send.SendCompletionTid = (ULONG_PTR)skb; ++ ++retry_send: ++ ret = net_drv_obj->OnSend(&net_device_ctx->device_ctx->device_obj, packet); ++ ++ if (ret == 0) ++ { ++#ifdef KERNEL_2_6_5 ++#define NETDEV_TX_OK 0 ++#define NETDEV_TX_BUSY 0 ++#endif ++ ret = NETDEV_TX_OK; ++ net_device_ctx->stats.tx_bytes += skb->len; ++ net_device_ctx->stats.tx_packets++; ++ } ++ else ++ { ++ retries++; ++ if (retries < 4) ++ { ++ DPRINT_ERR(NETVSC_DRV, "unable to send...retrying %d...", retries); ++ udelay(100); ++ goto retry_send; ++ } ++ ++ // no more room or we are shutting down ++ DPRINT_ERR(NETVSC_DRV, "unable to send (%d)...marking net device (%p) busy", ret, net); ++ DPRINT_INFO(NETVSC_DRV, "net device (%p) stopping", net); ++ ++ ret = NETDEV_TX_BUSY; ++ net_device_ctx->stats.tx_dropped++; ++ ++ netif_stop_queue(net); ++ ++ // Null it since the caller will free it instead of the completion routine ++ packet->Completion.Send.SendCompletionTid = 0; ++ ++ // Release the resources since we will not get any send completion ++ netvsc_xmit_completion((void*)packet); ++ } ++ ++ DPRINT_DBG(NETVSC_DRV, "# of xmits %lu total size %lu", net_device_ctx->stats.tx_packets, net_device_ctx->stats.tx_bytes); ++ ++ DPRINT_EXIT(NETVSC_DRV); ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: netvsc_linkstatus_callback() ++ ++Desc: Link up/down notification ++ ++--*/ ++static void netvsc_linkstatus_callback(DEVICE_OBJECT *device_obj, unsigned int status) ++{ ++ struct device_context* device_ctx = to_device_context(device_obj); ++ struct net_device* net = (struct net_device *)device_ctx->device.driver_data; ++ ++ DPRINT_ENTER(NETVSC_DRV); ++ ++ if (!net) ++ { ++ DPRINT_ERR(NETVSC_DRV, "got link status but net device not initialized yet"); ++ return; ++ } ++ ++ if (status == 1) ++ { ++ netif_carrier_on(net); ++ netif_wake_queue(net); ++ } ++ else ++ { ++ netif_carrier_off(net); ++ netif_stop_queue(net); ++ } ++ DPRINT_EXIT(NETVSC_DRV); ++} ++ ++ ++/*++ ++ ++Name: netvsc_recv_callback() ++ ++Desc: Callback when we receive a packet from the "wire" on the specify device ++ ++--*/ ++static int netvsc_recv_callback(DEVICE_OBJECT *device_obj, NETVSC_PACKET* packet) ++{ ++ int ret=0; ++ struct device_context *device_ctx = to_device_context(device_obj); ++ struct net_device *net = (struct net_device *)device_ctx->device.driver_data; ++ struct net_device_context *net_device_ctx; ++ ++ struct sk_buff *skb; ++ void *data; ++ int i=0; ++ unsigned long flags; ++ ++ DPRINT_ENTER(NETVSC_DRV); ++ ++ if (!net) ++ { ++ DPRINT_ERR(NETVSC_DRV, "got receive callback but net device not initialized yet"); ++ return 0; ++ } ++ ++ net_device_ctx = netdev_priv(net); ++ ++ // Allocate a skb - TODO preallocate this ++ //skb = alloc_skb(packet->TotalDataBufferLength, GFP_ATOMIC); ++ skb = dev_alloc_skb(packet->TotalDataBufferLength + 2); // Pad 2-bytes to align IP header to 16 bytes ++ ASSERT(skb); ++ skb_reserve(skb, 2); ++ skb->dev = net; ++ ++ // for kmap_atomic ++ local_irq_save(flags); ++ ++ // Copy to skb. This copy is needed here since the memory pointed by NETVSC_PACKET ++ // cannot be deallocated ++ for (i=0; iPageBufferCount; i++) ++ { ++ data = kmap_atomic(pfn_to_page(packet->PageBuffers[i].Pfn), KM_IRQ1); ++ data = (void*)(unsigned long)data + packet->PageBuffers[i].Offset; ++ ++ memcpy(skb_put(skb, packet->PageBuffers[i].Length), data, packet->PageBuffers[i].Length); ++ ++ kunmap_atomic((void*)((unsigned long)data - packet->PageBuffers[i].Offset), KM_IRQ1); ++ } ++ ++ local_irq_restore(flags); ++ ++ skb->protocol = eth_type_trans(skb, net); ++ ++ skb->ip_summed = CHECKSUM_NONE; ++ ++ // Pass the skb back up. Network stack will deallocate the skb when it is done ++ ret = netif_rx(skb); ++ ++ switch (ret) ++ { ++ case NET_RX_DROP: ++ net_device_ctx->stats.rx_dropped++; ++ break; ++ default: ++ net_device_ctx->stats.rx_packets++; ++ net_device_ctx->stats.rx_bytes += skb->len; ++ break; ++ ++ } ++ DPRINT_DBG(NETVSC_DRV, "# of recvs %lu total size %lu", net_device_ctx->stats.rx_packets, net_device_ctx->stats.rx_bytes); ++ ++ DPRINT_EXIT(NETVSC_DRV); ++ ++ return 0; ++} ++ ++static int netvsc_drv_exit_cb(struct device *dev, void *data) ++{ ++ struct device **curr = (struct device **)data; ++ *curr = dev; ++ return 1; // stop iterating ++} ++ ++/*++ ++ ++Name: netvsc_drv_exit() ++ ++Desc: ++ ++--*/ ++void netvsc_drv_exit(void) ++{ ++ NETVSC_DRIVER_OBJECT *netvsc_drv_obj=&g_netvsc_drv.drv_obj; ++ struct driver_context *drv_ctx=&g_netvsc_drv.drv_ctx; ++ ++ struct device *current_dev=NULL; ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++#define driver_for_each_device(drv, start, data, fn) \ ++ struct list_head *ptr, *n; \ ++ list_for_each_safe(ptr, n, &((drv)->devices)) {\ ++ struct device *curr_dev;\ ++ curr_dev = list_entry(ptr, struct device, driver_list);\ ++ fn(curr_dev, data);\ ++ } ++#endif ++ ++ DPRINT_ENTER(NETVSC_DRV); ++ ++ while (1) ++ { ++ current_dev = NULL; ++ ++ // Get the device ++ driver_for_each_device(&drv_ctx->driver, NULL, (void*)¤t_dev, netvsc_drv_exit_cb); ++ ++ if (current_dev == NULL) ++ break; ++ ++ // Initiate removal from the top-down ++ DPRINT_INFO(NETVSC_DRV, "unregistering device (%p)...", current_dev); ++ ++ device_unregister(current_dev); ++ } ++ ++ if (netvsc_drv_obj->Base.OnCleanup) ++ netvsc_drv_obj->Base.OnCleanup(&netvsc_drv_obj->Base); ++ ++ vmbus_child_driver_unregister(drv_ctx); ++ ++ DPRINT_EXIT(NETVSC_DRV); ++ ++ return; ++} ++ ++static int __init netvsc_init(void) ++{ ++ int ret; ++ ++ DPRINT_ENTER(NETVSC_DRV); ++ DPRINT_INFO(NETVSC_DRV, "Netvsc initializing...."); ++ ++ ret = netvsc_drv_init(NetVscInitialize); ++ ++ DPRINT_EXIT(NETVSC_DRV); ++ ++ return ret; ++} ++ ++static void __exit netvsc_exit(void) ++{ ++ DPRINT_ENTER(NETVSC_DRV); ++ ++ netvsc_drv_exit(); ++ ++ DPRINT_EXIT(NETVSC_DRV); ++} ++ ++module_param(netvsc_ringbuffer_size, int, S_IRUGO); ++ ++module_init(netvsc_init); ++module_exit(netvsc_exit); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/NetVsc.h linux-2.6.27.29-0.1.1/drivers/staging/hv/NetVsc.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/NetVsc.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,91 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _NETVSC_H_ ++#define _NETVSC_H_ ++ ++#include "include/VmbusPacketFormat.h" ++#include "include/nvspprotocol.h" ++ ++#include "include/List.h" ++ ++#include "include/NetVscApi.h" ++// ++// #defines ++// ++//#define NVSC_MIN_PROTOCOL_VERSION 1 ++//#define NVSC_MAX_PROTOCOL_VERSION 1 ++ ++#define NETVSC_SEND_BUFFER_SIZE 64*1024 // 64K ++#define NETVSC_SEND_BUFFER_ID 0xface ++ ++ ++#define NETVSC_RECEIVE_BUFFER_SIZE 1024*1024 // 1MB ++ ++#define NETVSC_RECEIVE_BUFFER_ID 0xcafe ++ ++#define NETVSC_RECEIVE_SG_COUNT 1 ++ ++// Preallocated receive packets ++#define NETVSC_RECEIVE_PACKETLIST_COUNT 256 ++ ++// ++// Data types ++// ++ ++// Per netvsc channel-specific ++typedef struct _NETVSC_DEVICE { ++ DEVICE_OBJECT *Device; ++ ++ int RefCount; ++ ++ int NumOutstandingSends; ++ // List of free preallocated NETVSC_PACKET to represent receive packet ++ LIST_ENTRY ReceivePacketList; ++ HANDLE ReceivePacketListLock; ++ ++ // Send buffer allocated by us but manages by NetVSP ++ PVOID SendBuffer; ++ UINT32 SendBufferSize; ++ UINT32 SendBufferGpadlHandle; ++ UINT32 SendSectionSize; ++ ++ // Receive buffer allocated by us but manages by NetVSP ++ PVOID ReceiveBuffer; ++ UINT32 ReceiveBufferSize; ++ UINT32 ReceiveBufferGpadlHandle; ++ UINT32 ReceiveSectionCount; ++ PNVSP_1_RECEIVE_BUFFER_SECTION ReceiveSections; ++ ++ // Used for NetVSP initialization protocol ++ HANDLE ChannelInitEvent; ++ NVSP_MESSAGE ChannelInitPacket; ++ ++ NVSP_MESSAGE RevokePacket; ++ //UCHAR HwMacAddr[HW_MACADDR_LEN]; ++ ++ // Holds rndis device info ++ void *Extension; ++} NETVSC_DEVICE; ++ ++#endif // _NETVSC_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/osd.c linux-2.6.27.29-0.1.1/drivers/staging/hv/osd.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/osd.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,501 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++#define KERNEL_2_6_27 ++ ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "include/osd.h" ++ ++// ++// Data types ++// ++typedef struct _TIMER { ++ struct timer_list timer; ++ PFN_TIMER_CALLBACK callback; ++ void* context; ++}TIMER; ++ ++ ++typedef struct _WAITEVENT { ++ int condition; ++ wait_queue_head_t event; ++} WAITEVENT; ++ ++typedef struct _SPINLOCK { ++ spinlock_t lock; ++ unsigned long flags; ++} SPINLOCK; ++ ++typedef struct _WORKQUEUE { ++ struct workqueue_struct *queue; ++} WORKQUEUE; ++ ++typedef struct _WORKITEM { ++ struct work_struct work; ++ PFN_WORKITEM_CALLBACK callback; ++ void* context; ++} WORKITEM; ++ ++ ++// ++// Global ++// ++ ++void LogMsg(const char *fmt, ...) ++{ ++#ifdef KERNEL_2_6_5 ++ char buf[1024]; ++#endif ++ va_list args; ++ ++ va_start(args, fmt); ++#ifdef KERNEL_2_6_5 ++ vsnprintf(buf, 1024, fmt, args); ++ va_end(args); ++ printk(buf); ++#else ++ vprintk(fmt, args); ++ va_end(args); ++#endif ++} ++ ++void BitSet(unsigned int* addr, int bit) ++{ ++ set_bit(bit, (unsigned long*)addr); ++} ++ ++int BitTest(unsigned int* addr, int bit) ++{ ++ return test_bit(bit, (unsigned long*)addr); ++} ++ ++void BitClear(unsigned int* addr, int bit) ++{ ++ clear_bit(bit, (unsigned long*)addr); ++} ++ ++int BitTestAndClear(unsigned int* addr, int bit) ++{ ++ return test_and_clear_bit(bit, (unsigned long*)addr); ++} ++ ++int BitTestAndSet(unsigned int* addr, int bit) ++{ ++ return test_and_set_bit(bit, (unsigned long*)addr); ++} ++ ++ ++int InterlockedIncrement(int *val) ++{ ++#ifdef KERNEL_2_6_5 ++ int i; ++ local_irq_disable(); ++ i = atomic_read((atomic_t*)val); ++ atomic_set((atomic_t*)val, i+1); ++ local_irq_enable(); ++ return i+1; ++#else ++ return atomic_inc_return((atomic_t*)val); ++#endif ++} ++ ++int InterlockedDecrement(int *val) ++{ ++#ifdef KERNEL_2_6_5 ++ int i; ++ local_irq_disable(); ++ i = atomic_read((atomic_t*)val); ++ atomic_set((atomic_t*)val, i-1); ++ local_irq_enable(); ++ return i-1; ++#else ++ return atomic_dec_return((atomic_t*)val); ++#endif ++} ++ ++#ifndef atomic_cmpxchg ++#define atomic_cmpxchg(v, old, new) ((int)cmpxchg(&((v)->counter), old, new)) ++#endif ++int InterlockedCompareExchange(int *val, int new, int curr) ++{ ++ //return ((int)cmpxchg(((atomic_t*)val), curr, new)); ++ return atomic_cmpxchg((atomic_t*)val, curr, new); ++ ++} ++ ++void Sleep(unsigned long usecs) ++{ ++ udelay(usecs); ++} ++ ++void* VirtualAllocExec(unsigned int size) ++{ ++#ifdef __x86_64__ ++ return __vmalloc(size, GFP_KERNEL, PAGE_KERNEL_EXEC); ++#else ++ return __vmalloc(size, GFP_KERNEL, __pgprot(__PAGE_KERNEL & (~_PAGE_NX))); ++#endif ++} ++ ++void VirtualFree(void* VirtAddr) ++{ ++ return vfree(VirtAddr); ++} ++ ++void* PageAlloc(unsigned int count) ++{ ++ void *p; ++ p = (void *)__get_free_pages(GFP_KERNEL, get_order(count * PAGE_SIZE)); ++ if (p) memset(p, 0, count * PAGE_SIZE); ++ return p; ++ ++ //struct page* page = alloc_page(GFP_KERNEL|__GFP_ZERO); ++ //void *p; ++ ++ ////BUGBUG: We need to use kmap in case we are in HIMEM region ++ //p = page_address(page); ++ //if (p) memset(p, 0, PAGE_SIZE); ++ //return p; ++} ++ ++void PageFree(void* page, unsigned int count) ++{ ++ free_pages((unsigned long)page, get_order(count * PAGE_SIZE)); ++ /*struct page* p = virt_to_page(page); ++ __free_page(p);*/ ++} ++ ++ ++void* PageMapVirtualAddress(unsigned long Pfn) ++{ ++ return kmap_atomic(pfn_to_page(Pfn), KM_IRQ0); ++} ++ ++void PageUnmapVirtualAddress(void* VirtAddr) ++{ ++ kunmap_atomic(VirtAddr, KM_IRQ0); ++} ++ ++void* MemAlloc(unsigned int size) ++{ ++ return kmalloc(size, GFP_KERNEL); ++} ++ ++void* MemAllocZeroed(unsigned int size) ++{ ++ void *p = kmalloc(size, GFP_KERNEL); ++ if (p) memset(p, 0, size); ++ return p; ++} ++ ++void* MemAllocAtomic(unsigned int size) ++{ ++ return kmalloc(size, GFP_ATOMIC); ++} ++ ++void MemFree(void* buf) ++{ ++ kfree(buf); ++} ++ ++void *MemMapIO(unsigned long phys, unsigned long size) ++{ ++#if X2V_LINUX ++#ifdef __x86_64__ ++ return (void*)(phys + 0xFFFF83000C000000); ++#else // i386 ++ return (void*)(phys + 0xfb000000); ++#endif ++#else ++ return (void*)GetVirtualAddress(phys); //return ioremap_nocache(phys, size); ++#endif ++} ++ ++void MemUnmapIO(void *virt) ++{ ++ //iounmap(virt); ++} ++ ++void MemoryFence() ++{ ++ mb(); ++} ++ ++void TimerCallback(unsigned long data) ++{ ++ TIMER* t = (TIMER*)data; ++ ++ t->callback(t->context); ++} ++ ++HANDLE TimerCreate(PFN_TIMER_CALLBACK pfnTimerCB, void* context) ++{ ++ TIMER* t = kmalloc(sizeof(TIMER), GFP_KERNEL); ++ if (!t) ++ { ++ return NULL; ++ } ++ ++ t->callback = pfnTimerCB; ++ t->context = context; ++ ++ init_timer(&t->timer); ++ t->timer.data = (unsigned long)t; ++ t->timer.function = TimerCallback; ++ ++ return t; ++} ++ ++void TimerStart(HANDLE hTimer, UINT32 expirationInUs) ++{ ++ TIMER* t = (TIMER* )hTimer; ++ ++ t->timer.expires = jiffies + usecs_to_jiffies(expirationInUs); ++ add_timer(&t->timer); ++} ++ ++int TimerStop(HANDLE hTimer) ++{ ++ TIMER* t = (TIMER* )hTimer; ++ ++ return del_timer(&t->timer); ++} ++ ++void TimerClose(HANDLE hTimer) ++{ ++ TIMER* t = (TIMER* )hTimer; ++ ++ del_timer(&t->timer); ++ kfree(t); ++} ++ ++SIZE_T GetTickCount(void) ++{ ++ return jiffies; ++} ++ ++signed long long GetTimestamp(void) ++{ ++ struct timeval t; ++ ++ do_gettimeofday(&t); ++ ++ return timeval_to_ns(&t); ++} ++ ++HANDLE WaitEventCreate(void) ++{ ++ WAITEVENT* wait = kmalloc(sizeof(WAITEVENT), GFP_KERNEL); ++ if (!wait) ++ { ++ return NULL; ++ } ++ ++ wait->condition = 0; ++ init_waitqueue_head(&wait->event); ++ return wait; ++} ++ ++void WaitEventClose(HANDLE hWait) ++{ ++ WAITEVENT* waitEvent = (WAITEVENT* )hWait; ++ kfree(waitEvent); ++} ++ ++void WaitEventSet(HANDLE hWait) ++{ ++ WAITEVENT* waitEvent = (WAITEVENT* )hWait; ++ waitEvent->condition = 1; ++ wake_up_interruptible(&waitEvent->event); ++} ++ ++int WaitEventWait(HANDLE hWait) ++{ ++ int ret=0; ++ WAITEVENT* waitEvent = (WAITEVENT* )hWait; ++ ++ ret= wait_event_interruptible(waitEvent->event, ++ waitEvent->condition); ++ waitEvent->condition = 0; ++ return ret; ++} ++ ++int WaitEventWaitEx(HANDLE hWait, UINT32 TimeoutInMs) ++{ ++ int ret=0; ++ WAITEVENT* waitEvent = (WAITEVENT* )hWait; ++ ++ ret= wait_event_interruptible_timeout(waitEvent->event, ++ waitEvent->condition, ++ msecs_to_jiffies(TimeoutInMs)); ++ waitEvent->condition = 0; ++ return ret; ++} ++ ++HANDLE SpinlockCreate(VOID) ++{ ++ SPINLOCK* spin = kmalloc(sizeof(SPINLOCK), GFP_KERNEL); ++ if (!spin) ++ { ++ return NULL; ++ } ++ spin_lock_init(&spin->lock); ++ ++ return spin; ++} ++ ++VOID SpinlockAcquire(HANDLE hSpin) ++{ ++ SPINLOCK* spin = (SPINLOCK* )hSpin; ++ ++ spin_lock_irqsave(&spin->lock, spin->flags); ++} ++ ++VOID SpinlockRelease(HANDLE hSpin) ++{ ++ SPINLOCK* spin = (SPINLOCK* )hSpin; ++ ++ spin_unlock_irqrestore(&spin->lock, spin->flags); ++} ++ ++VOID SpinlockClose(HANDLE hSpin) ++{ ++ SPINLOCK* spin = (SPINLOCK* )hSpin; ++ kfree(spin); ++} ++ ++void* Physical2LogicalAddr(ULONG_PTR PhysAddr) ++{ ++ void* logicalAddr = phys_to_virt(PhysAddr); ++ BUG_ON(!virt_addr_valid(logicalAddr)); ++ return logicalAddr; ++} ++ ++ULONG_PTR Logical2PhysicalAddr(PVOID LogicalAddr) ++{ ++ BUG_ON(!virt_addr_valid(LogicalAddr)); ++ return virt_to_phys(LogicalAddr); ++} ++ ++ ++ULONG_PTR Virtual2Physical(PVOID VirtAddr) ++{ ++ ULONG_PTR pfn = vmalloc_to_pfn(VirtAddr); ++ ++ return pfn << PAGE_SHIFT; ++} ++ ++#ifdef KERNEL_2_6_27 ++void WorkItemCallback(struct work_struct *work) ++#else ++void WorkItemCallback(void* work) ++#endif ++{ ++ WORKITEM* w = (WORKITEM*)work; ++ ++ w->callback(w->context); ++ ++ kfree(w); ++} ++ ++HANDLE WorkQueueCreate(char* name) ++{ ++ WORKQUEUE *wq = kmalloc(sizeof(WORKQUEUE), GFP_KERNEL); ++ if (!wq) ++ { ++ return NULL; ++ } ++ wq->queue = create_workqueue(name); ++ ++ return wq; ++} ++ ++void WorkQueueClose(HANDLE hWorkQueue) ++{ ++ WORKQUEUE *wq = (WORKQUEUE *)hWorkQueue; ++ ++ destroy_workqueue(wq->queue); ++ ++ return; ++} ++ ++int WorkQueueQueueWorkItem(HANDLE hWorkQueue, PFN_WORKITEM_CALLBACK workItem, void* context) ++{ ++ WORKQUEUE *wq = (WORKQUEUE *)hWorkQueue; ++ ++ WORKITEM* w = kmalloc(sizeof(WORKITEM), GFP_ATOMIC); ++ if (!w) ++ { ++ return -1; ++ } ++ ++ w->callback = workItem, ++ w->context = context; ++#ifdef KERNEL_2_6_27 ++ INIT_WORK(&w->work, WorkItemCallback); ++#else ++ INIT_WORK(&w->work, WorkItemCallback, w); ++#endif ++ return queue_work(wq->queue, &w->work); ++} ++ ++void QueueWorkItem(PFN_WORKITEM_CALLBACK workItem, void* context) ++{ ++ WORKITEM* w = kmalloc(sizeof(WORKITEM), GFP_ATOMIC); ++ if (!w) ++ { ++ return; ++ } ++ ++ w->callback = workItem, ++ w->context = context; ++#ifdef KERNEL_2_6_27 ++ INIT_WORK(&w->work, WorkItemCallback); ++#else ++ INIT_WORK(&w->work, WorkItemCallback, w); ++#endif ++ schedule_work(&w->work); ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/RingBuffer.c linux-2.6.27.29-0.1.1/drivers/staging/hv/RingBuffer.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/RingBuffer.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,630 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#include "include/logging.h" ++#include "RingBuffer.h" ++ ++// ++// #defines ++// ++ ++// Amount of space to write to ++#define BYTES_AVAIL_TO_WRITE(r, w, z) ((w) >= (r))?((z) - ((w) - (r))):((r) - (w)) ++ ++ ++/*++ ++ ++Name: ++ GetRingBufferAvailBytes() ++ ++Description: ++ Get number of bytes available to read and to write to ++ for the specified ring buffer ++ ++--*/ ++static inline void ++GetRingBufferAvailBytes(RING_BUFFER_INFO *rbi, UINT32 *read, UINT32 *write) ++{ ++ UINT32 read_loc,write_loc; ++ ++ // Capture the read/write indices before they changed ++ read_loc = rbi->RingBuffer->ReadIndex; ++ write_loc = rbi->RingBuffer->WriteIndex; ++ ++ *write = BYTES_AVAIL_TO_WRITE(read_loc, write_loc, rbi->RingDataSize); ++ *read = rbi->RingDataSize - *write; ++} ++ ++/*++ ++ ++Name: ++ GetNextWriteLocation() ++ ++Description: ++ Get the next write location for the specified ring buffer ++ ++--*/ ++static inline UINT32 ++GetNextWriteLocation(RING_BUFFER_INFO* RingInfo) ++{ ++ UINT32 next = RingInfo->RingBuffer->WriteIndex; ++ ++ ASSERT(next < RingInfo->RingDataSize); ++ ++ return next; ++} ++ ++/*++ ++ ++Name: ++ SetNextWriteLocation() ++ ++Description: ++ Set the next write location for the specified ring buffer ++ ++--*/ ++static inline void ++SetNextWriteLocation(RING_BUFFER_INFO* RingInfo, UINT32 NextWriteLocation) ++{ ++ RingInfo->RingBuffer->WriteIndex = NextWriteLocation; ++} ++ ++/*++ ++ ++Name: ++ GetNextReadLocation() ++ ++Description: ++ Get the next read location for the specified ring buffer ++ ++--*/ ++static inline UINT32 ++GetNextReadLocation(RING_BUFFER_INFO* RingInfo) ++{ ++ UINT32 next = RingInfo->RingBuffer->ReadIndex; ++ ++ ASSERT(next < RingInfo->RingDataSize); ++ ++ return next; ++} ++ ++/*++ ++ ++Name: ++ GetNextReadLocationWithOffset() ++ ++Description: ++ Get the next read location + offset for the specified ring buffer. ++ This allows the caller to skip ++ ++--*/ ++static inline UINT32 ++GetNextReadLocationWithOffset(RING_BUFFER_INFO* RingInfo, UINT32 Offset) ++{ ++ UINT32 next = RingInfo->RingBuffer->ReadIndex; ++ ++ ASSERT(next < RingInfo->RingDataSize); ++ next += Offset; ++ next %= RingInfo->RingDataSize; ++ ++ return next; ++} ++ ++/*++ ++ ++Name: ++ SetNextReadLocation() ++ ++Description: ++ Set the next read location for the specified ring buffer ++ ++--*/ ++static inline void ++SetNextReadLocation(RING_BUFFER_INFO* RingInfo, UINT32 NextReadLocation) ++{ ++ RingInfo->RingBuffer->ReadIndex = NextReadLocation; ++} ++ ++ ++/*++ ++ ++Name: ++ GetRingBuffer() ++ ++Description: ++ Get the start of the ring buffer ++ ++--*/ ++static inline PVOID ++GetRingBuffer(RING_BUFFER_INFO* RingInfo) ++{ ++ return (PVOID)RingInfo->RingBuffer->Buffer; ++} ++ ++ ++/*++ ++ ++Name: ++ GetRingBufferSize() ++ ++Description: ++ Get the size of the ring buffer ++ ++--*/ ++static inline UINT32 ++GetRingBufferSize(RING_BUFFER_INFO* RingInfo) ++{ ++ return RingInfo->RingDataSize; ++} ++ ++/*++ ++ ++Name: ++ GetRingBufferIndices() ++ ++Description: ++ Get the read and write indices as UINT64 of the specified ring buffer ++ ++--*/ ++static inline UINT64 ++GetRingBufferIndices(RING_BUFFER_INFO* RingInfo) ++{ ++ return ((UINT64)RingInfo->RingBuffer->WriteIndex << 32) || RingInfo->RingBuffer->ReadIndex; ++} ++ ++ ++/*++ ++ ++Name: ++ DumpRingInfo() ++ ++Description: ++ Dump out to console the ring buffer info ++ ++--*/ ++void ++DumpRingInfo(RING_BUFFER_INFO* RingInfo, char *Prefix) ++{ ++ UINT32 bytesAvailToWrite; ++ UINT32 bytesAvailToRead; ++ ++ GetRingBufferAvailBytes(RingInfo, &bytesAvailToRead, &bytesAvailToWrite); ++ ++ DPRINT(VMBUS, DEBUG_RING_LVL, "%s <>", ++ Prefix, ++ RingInfo, ++ RingInfo->RingBuffer->Buffer, ++ bytesAvailToWrite, ++ bytesAvailToRead, ++ RingInfo->RingBuffer->ReadIndex, ++ RingInfo->RingBuffer->WriteIndex); ++} ++ ++// ++// Internal routines ++// ++static UINT32 ++CopyToRingBuffer( ++ RING_BUFFER_INFO *RingInfo, ++ UINT32 StartWriteOffset, ++ PVOID Src, ++ UINT32 SrcLen); ++ ++static UINT32 ++CopyFromRingBuffer( ++ RING_BUFFER_INFO *RingInfo, ++ PVOID Dest, ++ UINT32 DestLen, ++ UINT32 StartReadOffset); ++ ++ ++ ++/*++ ++ ++Name: ++ RingBufferGetDebugInfo() ++ ++Description: ++ Get various debug metrics for the specified ring buffer ++ ++--*/ ++void ++RingBufferGetDebugInfo( ++ RING_BUFFER_INFO *RingInfo, ++ RING_BUFFER_DEBUG_INFO *DebugInfo ++ ) ++{ ++ UINT32 bytesAvailToWrite; ++ UINT32 bytesAvailToRead; ++ ++ if (RingInfo->RingBuffer) ++ { ++ GetRingBufferAvailBytes(RingInfo, &bytesAvailToRead, &bytesAvailToWrite); ++ ++ DebugInfo->BytesAvailToRead = bytesAvailToRead; ++ DebugInfo->BytesAvailToWrite = bytesAvailToWrite; ++ DebugInfo->CurrentReadIndex = RingInfo->RingBuffer->ReadIndex; ++ DebugInfo->CurrentWriteIndex = RingInfo->RingBuffer->WriteIndex; ++ ++ DebugInfo->CurrentInterruptMask = RingInfo->RingBuffer->InterruptMask; ++ } ++} ++ ++ ++/*++ ++ ++Name: ++ GetRingBufferInterruptMask() ++ ++Description: ++ Get the interrupt mask for the specified ring buffer ++ ++--*/ ++UINT32 ++GetRingBufferInterruptMask( ++ RING_BUFFER_INFO *rbi ++ ) ++{ ++ return rbi->RingBuffer->InterruptMask; ++} ++ ++/*++ ++ ++Name: ++ RingBufferInit() ++ ++Description: ++ Initialize the ring buffer ++ ++--*/ ++int ++RingBufferInit( ++ RING_BUFFER_INFO *RingInfo, ++ VOID *Buffer, ++ UINT32 BufferLen ++ ) ++{ ++ ASSERT(sizeof(RING_BUFFER) == PAGE_SIZE); ++ ++ memset(RingInfo, 0, sizeof(RING_BUFFER_INFO)); ++ ++ RingInfo->RingBuffer = (RING_BUFFER*)Buffer; ++ RingInfo->RingBuffer->ReadIndex = RingInfo->RingBuffer->WriteIndex = 0; ++ ++ RingInfo->RingSize = BufferLen; ++ RingInfo->RingDataSize = BufferLen - sizeof(RING_BUFFER); ++ ++ RingInfo->RingLock = SpinlockCreate(); ++ ++ return 0; ++} ++ ++/*++ ++ ++Name: ++ RingBufferCleanup() ++ ++Description: ++ Cleanup the ring buffer ++ ++--*/ ++void ++RingBufferCleanup( ++ RING_BUFFER_INFO* RingInfo ++ ) ++{ ++ SpinlockClose(RingInfo->RingLock); ++} ++ ++/*++ ++ ++Name: ++ RingBufferWrite() ++ ++Description: ++ Write to the ring buffer ++ ++--*/ ++int ++RingBufferWrite( ++ RING_BUFFER_INFO* OutRingInfo, ++ SG_BUFFER_LIST SgBuffers[], ++ UINT32 SgBufferCount ++ ) ++{ ++ int i=0; ++ UINT32 byteAvailToWrite; ++ UINT32 byteAvailToRead; ++ UINT32 totalBytesToWrite=0; ++ ++ volatile UINT32 nextWriteLocation; ++ UINT64 prevIndices=0; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ for (i=0; i < SgBufferCount; i++) ++ { ++ totalBytesToWrite += SgBuffers[i].Length; ++ } ++ ++ totalBytesToWrite += sizeof(UINT64); ++ ++ SpinlockAcquire(OutRingInfo->RingLock); ++ ++ GetRingBufferAvailBytes(OutRingInfo, &byteAvailToRead, &byteAvailToWrite); ++ ++ DPRINT_DBG(VMBUS, "Writing %u bytes...", totalBytesToWrite); ++ ++ //DumpRingInfo(OutRingInfo, "BEFORE "); ++ ++ // If there is only room for the packet, assume it is full. Otherwise, the next time around, we think the ring buffer ++ // is empty since the read index == write index ++ if (byteAvailToWrite <= totalBytesToWrite) ++ { ++ DPRINT_DBG(VMBUS, "No more space left on outbound ring buffer (needed %u, avail %u)", totalBytesToWrite, byteAvailToWrite); ++ ++ SpinlockRelease(OutRingInfo->RingLock); ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return -1; ++ } ++ ++ // Write to the ring buffer ++ nextWriteLocation = GetNextWriteLocation(OutRingInfo); ++ ++ for (i=0; i < SgBufferCount; i++) ++ { ++ nextWriteLocation = CopyToRingBuffer(OutRingInfo, ++ nextWriteLocation, ++ SgBuffers[i].Data, ++ SgBuffers[i].Length); ++ } ++ ++ // Set previous packet start ++ prevIndices = GetRingBufferIndices(OutRingInfo); ++ ++ nextWriteLocation = CopyToRingBuffer(OutRingInfo, ++ nextWriteLocation, ++ &prevIndices, ++ sizeof(UINT64)); ++ ++ // Make sure we flush all writes before updating the writeIndex ++ MemoryFence(); ++ ++ // Now, update the write location ++ SetNextWriteLocation(OutRingInfo, nextWriteLocation); ++ ++ //DumpRingInfo(OutRingInfo, "AFTER "); ++ ++ SpinlockRelease(OutRingInfo->RingLock); ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return 0; ++} ++ ++ ++/*++ ++ ++Name: ++ RingBufferPeek() ++ ++Description: ++ Read without advancing the read index ++ ++--*/ ++int ++RingBufferPeek( ++ RING_BUFFER_INFO* InRingInfo, ++ void* Buffer, ++ UINT32 BufferLen ++ ) ++{ ++ UINT32 bytesAvailToWrite; ++ UINT32 bytesAvailToRead; ++ UINT32 nextReadLocation=0; ++ ++ SpinlockAcquire(InRingInfo->RingLock); ++ ++ GetRingBufferAvailBytes(InRingInfo, &bytesAvailToRead, &bytesAvailToWrite); ++ ++ // Make sure there is something to read ++ if (bytesAvailToRead < BufferLen ) ++ { ++ //DPRINT_DBG(VMBUS, "got callback but not enough to read !!", bytesAvailToRead, BufferLen); ++ ++ SpinlockRelease(InRingInfo->RingLock); ++ ++ return -1; ++ } ++ ++ // Convert to byte offset ++ nextReadLocation = GetNextReadLocation(InRingInfo); ++ ++ nextReadLocation = CopyFromRingBuffer(InRingInfo, ++ Buffer, ++ BufferLen, ++ nextReadLocation); ++ ++ SpinlockRelease(InRingInfo->RingLock); ++ ++ return 0; ++} ++ ++ ++/*++ ++ ++Name: ++ RingBufferRead() ++ ++Description: ++ Read and advance the read index ++ ++--*/ ++int ++RingBufferRead( ++ RING_BUFFER_INFO* InRingInfo, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT32 Offset ++ ) ++{ ++ UINT32 bytesAvailToWrite; ++ UINT32 bytesAvailToRead; ++ UINT32 nextReadLocation=0; ++ UINT64 prevIndices=0; ++ ++ ASSERT(BufferLen > 0); ++ ++ SpinlockAcquire(InRingInfo->RingLock); ++ ++ GetRingBufferAvailBytes(InRingInfo, &bytesAvailToRead, &bytesAvailToWrite); ++ ++ DPRINT_DBG(VMBUS, "Reading %u bytes...", BufferLen); ++ ++ //DumpRingInfo(InRingInfo, "BEFORE "); ++ ++ // Make sure there is something to read ++ if (bytesAvailToRead < BufferLen ) ++ { ++ DPRINT_DBG(VMBUS, "got callback but not enough to read !!", bytesAvailToRead, BufferLen); ++ ++ SpinlockRelease(InRingInfo->RingLock); ++ ++ return -1; ++ } ++ ++ nextReadLocation = GetNextReadLocationWithOffset(InRingInfo, Offset); ++ ++ nextReadLocation = CopyFromRingBuffer(InRingInfo, ++ Buffer, ++ BufferLen, ++ nextReadLocation); ++ ++ nextReadLocation = CopyFromRingBuffer(InRingInfo, ++ &prevIndices, ++ sizeof(UINT64), ++ nextReadLocation); ++ ++ // Make sure all reads are done before we update the read index since ++ // the writer may start writing to the read area once the read index is updated ++ MemoryFence(); ++ ++ // Update the read index ++ SetNextReadLocation(InRingInfo, nextReadLocation); ++ ++ //DumpRingInfo(InRingInfo, "AFTER "); ++ ++ SpinlockRelease(InRingInfo->RingLock); ++ ++ return 0; ++} ++ ++ ++/*++ ++ ++Name: ++ CopyToRingBuffer() ++ ++Description: ++ Helper routine to copy from source to ring buffer. ++ Assume there is enough room. Handles wrap-around in dest case only!! ++ ++--*/ ++UINT32 ++CopyToRingBuffer( ++ RING_BUFFER_INFO *RingInfo, ++ UINT32 StartWriteOffset, ++ PVOID Src, ++ UINT32 SrcLen) ++{ ++ PVOID ringBuffer=GetRingBuffer(RingInfo); ++ UINT32 ringBufferSize=GetRingBufferSize(RingInfo); ++ UINT32 fragLen; ++ ++ if (SrcLen > ringBufferSize - StartWriteOffset) // wrap-around detected! ++ { ++ DPRINT_DBG(VMBUS, "wrap-around detected!"); ++ ++ fragLen = ringBufferSize - StartWriteOffset; ++ memcpy(ringBuffer + StartWriteOffset, Src, fragLen); ++ memcpy(ringBuffer, Src + fragLen, SrcLen - fragLen); ++ } ++ else ++ { ++ memcpy(ringBuffer + StartWriteOffset, Src, SrcLen); ++ } ++ ++ StartWriteOffset += SrcLen; ++ StartWriteOffset %= ringBufferSize; ++ ++ return StartWriteOffset; ++} ++ ++ ++/*++ ++ ++Name: ++ CopyFromRingBuffer() ++ ++Description: ++ Helper routine to copy to source from ring buffer. ++ Assume there is enough room. Handles wrap-around in src case only!! ++ ++--*/ ++UINT32 ++CopyFromRingBuffer( ++ RING_BUFFER_INFO *RingInfo, ++ PVOID Dest, ++ UINT32 DestLen, ++ UINT32 StartReadOffset) ++{ ++ PVOID ringBuffer=GetRingBuffer(RingInfo); ++ UINT32 ringBufferSize=GetRingBufferSize(RingInfo); ++ ++ UINT32 fragLen; ++ ++ if (DestLen > ringBufferSize - StartReadOffset) // wrap-around detected at the src ++ { ++ DPRINT_DBG(VMBUS, "src wrap-around detected!"); ++ ++ fragLen = ringBufferSize - StartReadOffset; ++ ++ memcpy(Dest, ringBuffer + StartReadOffset, fragLen); ++ memcpy(Dest + fragLen, ringBuffer, DestLen - fragLen); ++ } ++ else ++ { ++ memcpy(Dest, ringBuffer + StartReadOffset, DestLen); ++ } ++ ++ StartReadOffset += DestLen; ++ StartReadOffset %= ringBufferSize; ++ ++ return StartReadOffset; ++} ++ ++ ++// eof +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/RingBuffer.h linux-2.6.27.29-0.1.1/drivers/staging/hv/RingBuffer.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/RingBuffer.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,123 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _RING_BUFFER_H_ ++#define _RING_BUFFER_H_ ++ ++#include "include/osd.h" ++ ++typedef struct _SG_BUFFER_LIST { ++ PVOID Data; ++ UINT32 Length; ++} SG_BUFFER_LIST; ++ ++typedef struct _RING_BUFFER { ++ volatile UINT32 WriteIndex; // Offset in bytes from the start of ring data below ++ volatile UINT32 ReadIndex; // Offset in bytes from the start of ring data below ++ ++ volatile UINT32 InterruptMask; ++ UINT8 Reserved[4084]; // Pad it to PAGE_SIZE so that data starts on page boundary ++ // NOTE: The InterruptMask field is used only for channels but since our vmbus connection ++ // also uses this data structure and its data starts here, we commented out this field. ++ // volatile UINT32 InterruptMask; ++ // Ring data starts here + RingDataStartOffset !!! DO NOT place any fields below this !!! ++ UINT8 Buffer[0]; ++} STRUCT_PACKED RING_BUFFER; ++ ++typedef struct _RING_BUFFER_INFO { ++ RING_BUFFER* RingBuffer; ++ UINT32 RingSize; // Include the shared header ++ HANDLE RingLock; ++ ++ UINT32 RingDataSize; // < ringSize ++ UINT32 RingDataStartOffset; ++ ++} RING_BUFFER_INFO; ++ ++ ++typedef struct _RING_BUFFER_DEBUG_INFO { ++ UINT32 CurrentInterruptMask; ++ UINT32 CurrentReadIndex; ++ UINT32 CurrentWriteIndex; ++ UINT32 BytesAvailToRead; ++ UINT32 BytesAvailToWrite; ++}RING_BUFFER_DEBUG_INFO; ++ ++ ++// ++// Interface ++// ++ ++INTERNAL int ++RingBufferInit( ++ RING_BUFFER_INFO *RingInfo, ++ PVOID Buffer, ++ UINT32 BufferLen ++ ); ++ ++INTERNAL void ++RingBufferCleanup( ++ RING_BUFFER_INFO *RingInfo ++ ); ++ ++INTERNAL int ++RingBufferWrite( ++ RING_BUFFER_INFO *RingInfo, ++ SG_BUFFER_LIST SgBuffers[], ++ UINT32 SgBufferCount ++ ); ++ ++INTERNAL int ++RingBufferPeek( ++ RING_BUFFER_INFO *RingInfo, ++ PVOID Buffer, ++ UINT32 BufferLen ++ ); ++ ++INTERNAL int ++RingBufferRead( ++ RING_BUFFER_INFO *RingInfo, ++ PVOID Buffer, ++ UINT32 BufferLen, ++ UINT32 Offset ++ ); ++ ++INTERNAL UINT32 ++GetRingBufferInterruptMask( ++ RING_BUFFER_INFO *RingInfo ++ ); ++ ++INTERNAL void ++DumpRingInfo( ++ RING_BUFFER_INFO* RingInfo, ++ char *Prefix ++ ); ++ ++INTERNAL void ++RingBufferGetDebugInfo( ++ RING_BUFFER_INFO *RingInfo, ++ RING_BUFFER_DEBUG_INFO *DebugInfo ++ ); ++ ++#endif // _RING_BUFFER_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/RndisFilter.c linux-2.6.27.29-0.1.1/drivers/staging/hv/RndisFilter.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/RndisFilter.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,1163 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++#define KERNEL_2_6_27 ++ ++#include "include/logging.h" ++ ++#include "include/NetVscApi.h" ++#include "RndisFilter.h" ++ ++// ++// Data types ++// ++ ++typedef struct _RNDIS_FILTER_DRIVER_OBJECT { ++ // The original driver ++ NETVSC_DRIVER_OBJECT InnerDriver; ++ ++} RNDIS_FILTER_DRIVER_OBJECT; ++ ++typedef enum { ++ RNDIS_DEV_UNINITIALIZED = 0, ++ RNDIS_DEV_INITIALIZING, ++ RNDIS_DEV_INITIALIZED, ++ RNDIS_DEV_DATAINITIALIZED, ++} RNDIS_DEVICE_STATE; ++ ++typedef struct _RNDIS_DEVICE { ++ NETVSC_DEVICE *NetDevice; ++ ++ RNDIS_DEVICE_STATE State; ++ UINT32 LinkStatus; ++ UINT32 NewRequestId; ++ ++ HANDLE RequestLock; ++ LIST_ENTRY RequestList; ++ ++ UCHAR HwMacAddr[HW_MACADDR_LEN]; ++} RNDIS_DEVICE; ++ ++ ++typedef struct _RNDIS_REQUEST { ++ LIST_ENTRY ListEntry; ++ HANDLE WaitEvent; ++ ++ // FIXME: We assumed a fixed size response here. If we do ever need to handle a bigger response, ++ // we can either define a max response message or add a response buffer variable above this field ++ RNDIS_MESSAGE ResponseMessage; ++ ++ // Simplify allocation by having a netvsc packet inline ++ NETVSC_PACKET Packet; ++ PAGE_BUFFER Buffer; ++ // FIXME: We assumed a fixed size request here. ++ RNDIS_MESSAGE RequestMessage; ++} RNDIS_REQUEST; ++ ++ ++typedef struct _RNDIS_FILTER_PACKET { ++ void *CompletionContext; ++ PFN_ON_SENDRECVCOMPLETION OnCompletion; ++ ++ RNDIS_MESSAGE Message; ++} RNDIS_FILTER_PACKET; ++ ++// ++// Internal routines ++// ++static int ++RndisFilterSendRequest( ++ RNDIS_DEVICE *Device, ++ RNDIS_REQUEST *Request ++ ); ++ ++static void ++RndisFilterReceiveResponse( ++ RNDIS_DEVICE *Device, ++ RNDIS_MESSAGE *Response ++ ); ++ ++static void ++RndisFilterReceiveIndicateStatus( ++ RNDIS_DEVICE *Device, ++ RNDIS_MESSAGE *Response ++ ); ++ ++static void ++RndisFilterReceiveData( ++ RNDIS_DEVICE *Device, ++ RNDIS_MESSAGE *Message, ++ NETVSC_PACKET *Packet ++ ); ++ ++static int ++RndisFilterOnReceive( ++ DEVICE_OBJECT *Device, ++ NETVSC_PACKET *Packet ++ ); ++ ++static int ++RndisFilterQueryDevice( ++ RNDIS_DEVICE *Device, ++ UINT32 Oid, ++ VOID *Result, ++ UINT32 *ResultSize ++ ); ++ ++static inline int ++RndisFilterQueryDeviceMac( ++ RNDIS_DEVICE *Device ++ ); ++ ++static inline int ++RndisFilterQueryDeviceLinkStatus( ++ RNDIS_DEVICE *Device ++ ); ++ ++static int ++RndisFilterSetPacketFilter( ++ RNDIS_DEVICE *Device, ++ UINT32 NewFilter ++ ); ++ ++static int ++RndisFilterInitDevice( ++ RNDIS_DEVICE *Device ++ ); ++ ++static int ++RndisFilterOpenDevice( ++ RNDIS_DEVICE *Device ++ ); ++ ++static int ++RndisFilterCloseDevice( ++ RNDIS_DEVICE *Device ++ ); ++ ++static int ++RndisFilterOnDeviceAdd( ++ DEVICE_OBJECT *Device, ++ void *AdditionalInfo ++ ); ++ ++static int ++RndisFilterOnDeviceRemove( ++ DEVICE_OBJECT *Device ++ ); ++ ++static void ++RndisFilterOnCleanup( ++ DRIVER_OBJECT *Driver ++ ); ++ ++static int ++RndisFilterOnOpen( ++ DEVICE_OBJECT *Device ++ ); ++ ++static int ++RndisFilterOnClose( ++ DEVICE_OBJECT *Device ++ ); ++ ++static int ++RndisFilterOnSend( ++ DEVICE_OBJECT *Device, ++ NETVSC_PACKET *Packet ++ ); ++ ++static void ++RndisFilterOnSendCompletion( ++ void *Context ++ ); ++ ++static void ++RndisFilterOnSendRequestCompletion( ++ void *Context ++ ); ++ ++// ++// Global var ++// ++ ++// The one and only ++RNDIS_FILTER_DRIVER_OBJECT gRndisFilter; ++ ++static inline RNDIS_DEVICE* GetRndisDevice(void) ++{ ++ RNDIS_DEVICE *device; ++ ++ device = MemAllocZeroed(sizeof(RNDIS_DEVICE)); ++ if (!device) ++ { ++ return NULL; ++ } ++ ++ device->RequestLock = SpinlockCreate(); ++ if (!device->RequestLock) ++ { ++ MemFree(device); ++ return NULL; ++ } ++ ++ INITIALIZE_LIST_HEAD(&device->RequestList); ++ ++ device->State = RNDIS_DEV_UNINITIALIZED; ++ ++ return device; ++} ++ ++static inline void PutRndisDevice(RNDIS_DEVICE *Device) ++{ ++ SpinlockClose(Device->RequestLock); ++ MemFree(Device); ++} ++ ++static inline RNDIS_REQUEST* GetRndisRequest(RNDIS_DEVICE *Device, UINT32 MessageType, UINT32 MessageLength) ++{ ++ RNDIS_REQUEST *request; ++ RNDIS_MESSAGE *rndisMessage; ++ RNDIS_SET_REQUEST *set; ++ ++ request = MemAllocZeroed(sizeof(RNDIS_REQUEST)); ++ if (!request) ++ { ++ return NULL; ++ } ++ ++ request->WaitEvent = WaitEventCreate(); ++ if (!request->WaitEvent) ++ { ++ MemFree(request); ++ return NULL; ++ } ++ ++ rndisMessage = &request->RequestMessage; ++ rndisMessage->NdisMessageType = MessageType; ++ rndisMessage->MessageLength = MessageLength; ++ ++ // Set the request id. This field is always after the rndis header for request/response packet types so ++ // we just used the SetRequest as a template ++ set = &rndisMessage->Message.SetRequest; ++ set->RequestId = InterlockedIncrement((int*)&Device->NewRequestId); ++ ++ // Add to the request list ++ SpinlockAcquire(Device->RequestLock); ++ INSERT_TAIL_LIST(&Device->RequestList, &request->ListEntry); ++ SpinlockRelease(Device->RequestLock); ++ ++ return request; ++} ++ ++static inline void PutRndisRequest(RNDIS_DEVICE *Device, RNDIS_REQUEST *Request) ++{ ++ SpinlockAcquire(Device->RequestLock); ++ REMOVE_ENTRY_LIST(&Request->ListEntry); ++ SpinlockRelease(Device->RequestLock); ++ ++ WaitEventClose(Request->WaitEvent); ++ MemFree(Request); ++} ++ ++static inline void DumpRndisMessage(RNDIS_MESSAGE *RndisMessage) ++{ ++ switch (RndisMessage->NdisMessageType) ++ { ++ case REMOTE_NDIS_PACKET_MSG: ++ DPRINT_DBG(NETVSC, "REMOTE_NDIS_PACKET_MSG (len %u, data offset %u data len %u, # oob %u, oob offset %u, oob len %u, pkt offset %u, pkt len %u", ++ RndisMessage->MessageLength, ++ RndisMessage->Message.Packet.DataOffset, ++ RndisMessage->Message.Packet.DataLength, ++ RndisMessage->Message.Packet.NumOOBDataElements, ++ RndisMessage->Message.Packet.OOBDataOffset, ++ RndisMessage->Message.Packet.OOBDataLength, ++ RndisMessage->Message.Packet.PerPacketInfoOffset, ++ RndisMessage->Message.Packet.PerPacketInfoLength); ++ break; ++ ++ case REMOTE_NDIS_INITIALIZE_CMPLT: ++ DPRINT_DBG(NETVSC, "REMOTE_NDIS_INITIALIZE_CMPLT (len %u, id 0x%x, status 0x%x, major %d, minor %d, device flags %d, max xfer size 0x%x, max pkts %u, pkt aligned %u)", ++ RndisMessage->MessageLength, ++ RndisMessage->Message.InitializeComplete.RequestId, ++ RndisMessage->Message.InitializeComplete.Status, ++ RndisMessage->Message.InitializeComplete.MajorVersion, ++ RndisMessage->Message.InitializeComplete.MinorVersion, ++ RndisMessage->Message.InitializeComplete.DeviceFlags, ++ RndisMessage->Message.InitializeComplete.MaxTransferSize, ++ RndisMessage->Message.InitializeComplete.MaxPacketsPerMessage, ++ RndisMessage->Message.InitializeComplete.PacketAlignmentFactor); ++ break; ++ ++ case REMOTE_NDIS_QUERY_CMPLT: ++ DPRINT_DBG(NETVSC, "REMOTE_NDIS_QUERY_CMPLT (len %u, id 0x%x, status 0x%x, buf len %u, buf offset %u)", ++ RndisMessage->MessageLength, ++ RndisMessage->Message.QueryComplete.RequestId, ++ RndisMessage->Message.QueryComplete.Status, ++ RndisMessage->Message.QueryComplete.InformationBufferLength, ++ RndisMessage->Message.QueryComplete.InformationBufferOffset); ++ break; ++ ++ case REMOTE_NDIS_SET_CMPLT: ++ DPRINT_DBG(NETVSC, "REMOTE_NDIS_SET_CMPLT (len %u, id 0x%x, status 0x%x)", ++ RndisMessage->MessageLength, ++ RndisMessage->Message.SetComplete.RequestId, ++ RndisMessage->Message.SetComplete.Status); ++ break; ++ ++ case REMOTE_NDIS_INDICATE_STATUS_MSG: ++ DPRINT_DBG(NETVSC, "REMOTE_NDIS_INDICATE_STATUS_MSG (len %u, status 0x%x, buf len %u, buf offset %u)", ++ RndisMessage->MessageLength, ++ RndisMessage->Message.IndicateStatus.Status, ++ RndisMessage->Message.IndicateStatus.StatusBufferLength, ++ RndisMessage->Message.IndicateStatus.StatusBufferOffset); ++ break; ++ ++ default: ++ DPRINT_DBG(NETVSC, "0x%x (len %u)", ++ RndisMessage->NdisMessageType, ++ RndisMessage->MessageLength); ++ break; ++ } ++} ++ ++static int ++RndisFilterSendRequest( ++ RNDIS_DEVICE *Device, ++ RNDIS_REQUEST *Request ++ ) ++{ ++ int ret=0; ++ NETVSC_PACKET *packet; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ // Setup the packet to send it ++ packet = &Request->Packet; ++ ++ packet->IsDataPacket = FALSE; ++ packet->TotalDataBufferLength = Request->RequestMessage.MessageLength; ++ packet->PageBufferCount = 1; ++ ++ packet->PageBuffers[0].Pfn = GetPhysicalAddress(&Request->RequestMessage) >> PAGE_SHIFT; ++ packet->PageBuffers[0].Length = Request->RequestMessage.MessageLength; ++ packet->PageBuffers[0].Offset = (ULONG_PTR)&Request->RequestMessage & (PAGE_SIZE -1); ++ ++ packet->Completion.Send.SendCompletionContext = Request;//packet; ++ packet->Completion.Send.OnSendCompletion = RndisFilterOnSendRequestCompletion; ++ packet->Completion.Send.SendCompletionTid = (ULONG_PTR)Device; ++ ++ ret = gRndisFilter.InnerDriver.OnSend(Device->NetDevice->Device, packet); ++ DPRINT_EXIT(NETVSC); ++ return ret; ++} ++ ++ ++static void ++RndisFilterReceiveResponse( ++ RNDIS_DEVICE *Device, ++ RNDIS_MESSAGE *Response ++ ) ++{ ++ LIST_ENTRY *anchor; ++ LIST_ENTRY *curr; ++ RNDIS_REQUEST *request=NULL; ++ BOOL found=FALSE; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ SpinlockAcquire(Device->RequestLock); ++ ITERATE_LIST_ENTRIES(anchor, curr, &Device->RequestList) ++ { ++ request = CONTAINING_RECORD(curr, RNDIS_REQUEST, ListEntry); ++ ++ // All request/response message contains RequestId as the 1st field ++ if (request->RequestMessage.Message.InitializeRequest.RequestId == Response->Message.InitializeComplete.RequestId) ++ { ++ DPRINT_DBG(NETVSC, "found rndis request for this response (id 0x%x req type 0x%x res type 0x%x)", ++ request->RequestMessage.Message.InitializeRequest.RequestId, request->RequestMessage.NdisMessageType, Response->NdisMessageType); ++ ++ found = TRUE; ++ break; ++ } ++ } ++ SpinlockRelease(Device->RequestLock); ++ ++ if (found) ++ { ++ if (Response->MessageLength <= sizeof(RNDIS_MESSAGE)) ++ { ++ memcpy(&request->ResponseMessage, Response, Response->MessageLength); ++ } ++ else ++ { ++ DPRINT_ERR(NETVSC, "rndis response buffer overflow detected (size %u max %u)", Response->MessageLength, sizeof(RNDIS_FILTER_PACKET)); ++ ++ if (Response->NdisMessageType == REMOTE_NDIS_RESET_CMPLT) // does not have a request id field ++ { ++ request->ResponseMessage.Message.ResetComplete.Status = STATUS_BUFFER_OVERFLOW; ++ } ++ else ++ { ++ request->ResponseMessage.Message.InitializeComplete.Status = STATUS_BUFFER_OVERFLOW; ++ } ++ } ++ ++ WaitEventSet(request->WaitEvent); ++ } ++ else ++ { ++ DPRINT_ERR(NETVSC, "no rndis request found for this response (id 0x%x res type 0x%x)", ++ Response->Message.InitializeComplete.RequestId, Response->NdisMessageType); ++ } ++ ++ DPRINT_EXIT(NETVSC); ++} ++ ++static void ++RndisFilterReceiveIndicateStatus( ++ RNDIS_DEVICE *Device, ++ RNDIS_MESSAGE *Response ++ ) ++{ ++ RNDIS_INDICATE_STATUS *indicate = &Response->Message.IndicateStatus; ++ ++ if (indicate->Status == RNDIS_STATUS_MEDIA_CONNECT) ++ { ++ gRndisFilter.InnerDriver.OnLinkStatusChanged(Device->NetDevice->Device, 1); ++ } ++ else if (indicate->Status == RNDIS_STATUS_MEDIA_DISCONNECT) ++ { ++ gRndisFilter.InnerDriver.OnLinkStatusChanged(Device->NetDevice->Device, 0); ++ } ++ else ++ { ++ // TODO: ++ } ++} ++ ++static void ++RndisFilterReceiveData( ++ RNDIS_DEVICE *Device, ++ RNDIS_MESSAGE *Message, ++ NETVSC_PACKET *Packet ++ ) ++{ ++ RNDIS_PACKET *rndisPacket; ++ UINT32 dataOffset; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ // empty ethernet frame ?? ++ ASSERT(Packet->PageBuffers[0].Length > RNDIS_MESSAGE_SIZE(RNDIS_PACKET)); ++ ++ rndisPacket = &Message->Message.Packet; ++ ++ // FIXME: Handle multiple rndis pkt msgs that maybe enclosed in this ++ // netvsc packet (ie TotalDataBufferLength != MessageLength) ++ ++ // Remove the rndis header and pass it back up the stack ++ dataOffset = RNDIS_HEADER_SIZE + rndisPacket->DataOffset; ++ ++ Packet->TotalDataBufferLength -= dataOffset; ++ Packet->PageBuffers[0].Offset += dataOffset; ++ Packet->PageBuffers[0].Length -= dataOffset; ++ ++ Packet->IsDataPacket = TRUE; ++ ++ gRndisFilter.InnerDriver.OnReceiveCallback(Device->NetDevice->Device, Packet); ++ ++ DPRINT_EXIT(NETVSC); ++} ++ ++static int ++RndisFilterOnReceive( ++ DEVICE_OBJECT *Device, ++ NETVSC_PACKET *Packet ++ ) ++{ ++ NETVSC_DEVICE *netDevice = (NETVSC_DEVICE*)Device->Extension; ++ RNDIS_DEVICE *rndisDevice; ++ RNDIS_MESSAGE rndisMessage; ++ RNDIS_MESSAGE *rndisHeader; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ ASSERT(netDevice); ++ //Make sure the rndis device state is initialized ++ if (!netDevice->Extension) ++ { ++ DPRINT_ERR(NETVSC, "got rndis message but no rndis device...dropping this message!"); ++ DPRINT_EXIT(NETVSC); ++ return -1; ++ } ++ ++ rndisDevice = (RNDIS_DEVICE*)netDevice->Extension; ++ if (rndisDevice->State == RNDIS_DEV_UNINITIALIZED) ++ { ++ DPRINT_ERR(NETVSC, "got rndis message but rndis device uninitialized...dropping this message!"); ++ DPRINT_EXIT(NETVSC); ++ return -1; ++ } ++ ++ rndisHeader = (RNDIS_MESSAGE*)PageMapVirtualAddress(Packet->PageBuffers[0].Pfn); ++ ++ rndisHeader = (void*)((ULONG_PTR)rndisHeader + Packet->PageBuffers[0].Offset); ++ ++ // Make sure we got a valid rndis message ++ // FIXME: There seems to be a bug in set completion msg where its MessageLength is 16 bytes but ++ // the ByteCount field in the xfer page range shows 52 bytes ++#if 0 ++ if ( Packet->TotalDataBufferLength != rndisHeader->MessageLength ) ++ { ++ PageUnmapVirtualAddress((void*)(ULONG_PTR)rndisHeader - Packet->PageBuffers[0].Offset); ++ ++ DPRINT_ERR(NETVSC, "invalid rndis message? (expected %u bytes got %u)...dropping this message!", ++ rndisHeader->MessageLength, Packet->TotalDataBufferLength); ++ DPRINT_EXIT(NETVSC); ++ return -1; ++ } ++#endif ++ ++ if ((rndisHeader->NdisMessageType != REMOTE_NDIS_PACKET_MSG) && (rndisHeader->MessageLength > sizeof(RNDIS_MESSAGE))) ++ { ++ DPRINT_ERR(NETVSC, "incoming rndis message buffer overflow detected (got %u, max %u)...marking it an error!", ++ rndisHeader->MessageLength, sizeof(RNDIS_MESSAGE)); ++ } ++ ++ memcpy(&rndisMessage, rndisHeader, (rndisHeader->MessageLength > sizeof(RNDIS_MESSAGE))?sizeof(RNDIS_MESSAGE):rndisHeader->MessageLength); ++ ++ PageUnmapVirtualAddress((void*)(ULONG_PTR)rndisHeader - Packet->PageBuffers[0].Offset); ++ ++ DumpRndisMessage(&rndisMessage); ++ ++ switch (rndisMessage.NdisMessageType) ++ { ++ // data msg ++ case REMOTE_NDIS_PACKET_MSG: ++ RndisFilterReceiveData(rndisDevice, &rndisMessage, Packet); ++ break; ++ ++ // completion msgs ++ case REMOTE_NDIS_INITIALIZE_CMPLT: ++ case REMOTE_NDIS_QUERY_CMPLT: ++ case REMOTE_NDIS_SET_CMPLT: ++ //case REMOTE_NDIS_RESET_CMPLT: ++ //case REMOTE_NDIS_KEEPALIVE_CMPLT: ++ RndisFilterReceiveResponse(rndisDevice, &rndisMessage); ++ break; ++ ++ // notification msgs ++ case REMOTE_NDIS_INDICATE_STATUS_MSG: ++ RndisFilterReceiveIndicateStatus(rndisDevice, &rndisMessage); ++ break; ++ default: ++ DPRINT_ERR(NETVSC, "unhandled rndis message (type %u len %u)", rndisMessage.NdisMessageType, rndisMessage.MessageLength); ++ break; ++ } ++ ++ DPRINT_EXIT(NETVSC); ++ return 0; ++} ++ ++ ++static int ++RndisFilterQueryDevice( ++ RNDIS_DEVICE *Device, ++ UINT32 Oid, ++ VOID *Result, ++ UINT32 *ResultSize ++ ) ++{ ++ RNDIS_REQUEST *request; ++ UINT32 inresultSize = *ResultSize; ++ RNDIS_QUERY_REQUEST *query; ++ RNDIS_QUERY_COMPLETE *queryComplete; ++ int ret=0; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ ASSERT(Result); ++ ++ *ResultSize = 0; ++ request = GetRndisRequest(Device, REMOTE_NDIS_QUERY_MSG, RNDIS_MESSAGE_SIZE(RNDIS_QUERY_REQUEST)); ++ if (!request) ++ { ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ // Setup the rndis query ++ query = &request->RequestMessage.Message.QueryRequest; ++ query->Oid = Oid; ++ query->InformationBufferOffset = sizeof(RNDIS_QUERY_REQUEST); ++ query->InformationBufferLength = 0; ++ query->DeviceVcHandle = 0; ++ ++ ret = RndisFilterSendRequest(Device, request); ++ if (ret != 0) ++ { ++ goto Cleanup; ++ } ++ ++ WaitEventWait(request->WaitEvent); ++ ++ // Copy the response back ++ queryComplete = &request->ResponseMessage.Message.QueryComplete; ++ ++ if (queryComplete->InformationBufferLength > inresultSize) ++ { ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ memcpy(Result, ++ (void*)((ULONG_PTR)queryComplete + queryComplete->InformationBufferOffset), ++ queryComplete->InformationBufferLength); ++ ++ *ResultSize = queryComplete->InformationBufferLength; ++ ++Cleanup: ++ if (request) ++ { ++ PutRndisRequest(Device, request); ++ } ++ DPRINT_EXIT(NETVSC); ++ ++ return ret; ++} ++ ++static inline int ++RndisFilterQueryDeviceMac( ++ RNDIS_DEVICE *Device ++ ) ++{ ++ UINT32 size=HW_MACADDR_LEN; ++ ++ return RndisFilterQueryDevice(Device, ++ RNDIS_OID_802_3_PERMANENT_ADDRESS, ++ Device->HwMacAddr, ++ &size); ++} ++ ++static inline int ++RndisFilterQueryDeviceLinkStatus( ++ RNDIS_DEVICE *Device ++ ) ++{ ++ UINT32 size=sizeof(UINT32); ++ ++ return RndisFilterQueryDevice(Device, ++ RNDIS_OID_GEN_MEDIA_CONNECT_STATUS, ++ &Device->LinkStatus, ++ &size); ++} ++ ++static int ++RndisFilterSetPacketFilter( ++ RNDIS_DEVICE *Device, ++ UINT32 NewFilter ++ ) ++{ ++ RNDIS_REQUEST *request; ++ RNDIS_SET_REQUEST *set; ++ RNDIS_SET_COMPLETE *setComplete; ++ UINT32 status; ++ int ret; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ ASSERT(RNDIS_MESSAGE_SIZE(RNDIS_SET_REQUEST) + sizeof(UINT32) <= sizeof(RNDIS_MESSAGE)); ++ ++ request = GetRndisRequest(Device, REMOTE_NDIS_SET_MSG, RNDIS_MESSAGE_SIZE(RNDIS_SET_REQUEST) + sizeof(UINT32)); ++ if (!request) ++ { ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ // Setup the rndis set ++ set = &request->RequestMessage.Message.SetRequest; ++ set->Oid = RNDIS_OID_GEN_CURRENT_PACKET_FILTER; ++ set->InformationBufferLength = sizeof(UINT32); ++ set->InformationBufferOffset = sizeof(RNDIS_SET_REQUEST); ++ ++ memcpy((void*)(ULONG_PTR)set + sizeof(RNDIS_SET_REQUEST), &NewFilter, sizeof(UINT32)); ++ ++ ret = RndisFilterSendRequest(Device, request); ++ if (ret != 0) ++ { ++ goto Cleanup; ++ } ++ ++ ret = WaitEventWaitEx(request->WaitEvent, 2000/*2sec*/); ++ if (!ret) ++ { ++ ret = -1; ++ DPRINT_ERR(NETVSC, "timeout before we got a set response..."); ++ // We cant deallocate the request since we may still receive a send completion for it. ++ goto Exit; ++ } ++ else ++ { ++ if (ret > 0) ++ { ++ ret = 0; ++ } ++ setComplete = &request->ResponseMessage.Message.SetComplete; ++ status = setComplete->Status; ++ } ++ ++Cleanup: ++ if (request) ++ { ++ PutRndisRequest(Device, request); ++ } ++Exit: ++ DPRINT_EXIT(NETVSC); ++ ++ return ret; ++} ++ ++int ++RndisFilterInit( ++ NETVSC_DRIVER_OBJECT *Driver ++ ) ++{ ++ DPRINT_ENTER(NETVSC); ++ ++ DPRINT_DBG(NETVSC, "sizeof(RNDIS_FILTER_PACKET) == %d", sizeof(RNDIS_FILTER_PACKET)); ++ ++ Driver->RequestExtSize = sizeof(RNDIS_FILTER_PACKET); ++ Driver->AdditionalRequestPageBufferCount = 1; // For rndis header ++ ++ //Driver->Context = rndisDriver; ++ ++ memset(&gRndisFilter, 0, sizeof(RNDIS_FILTER_DRIVER_OBJECT)); ++ ++ /*rndisDriver->Driver = Driver; ++ ++ ASSERT(Driver->OnLinkStatusChanged); ++ rndisDriver->OnLinkStatusChanged = Driver->OnLinkStatusChanged;*/ ++ ++ // Save the original dispatch handlers before we override it ++ gRndisFilter.InnerDriver.Base.OnDeviceAdd = Driver->Base.OnDeviceAdd; ++ gRndisFilter.InnerDriver.Base.OnDeviceRemove = Driver->Base.OnDeviceRemove; ++ gRndisFilter.InnerDriver.Base.OnCleanup = Driver->Base.OnCleanup; ++ ++ ASSERT(Driver->OnSend); ++ ASSERT(Driver->OnReceiveCallback); ++ gRndisFilter.InnerDriver.OnSend = Driver->OnSend; ++ gRndisFilter.InnerDriver.OnReceiveCallback = Driver->OnReceiveCallback; ++ gRndisFilter.InnerDriver.OnLinkStatusChanged = Driver->OnLinkStatusChanged; ++ ++ // Override ++ Driver->Base.OnDeviceAdd = RndisFilterOnDeviceAdd; ++ Driver->Base.OnDeviceRemove = RndisFilterOnDeviceRemove; ++ Driver->Base.OnCleanup = RndisFilterOnCleanup; ++ Driver->OnSend = RndisFilterOnSend; ++ Driver->OnOpen = RndisFilterOnOpen; ++ Driver->OnClose = RndisFilterOnClose; ++ //Driver->QueryLinkStatus = RndisFilterQueryDeviceLinkStatus; ++ Driver->OnReceiveCallback = RndisFilterOnReceive; ++ ++ DPRINT_EXIT(NETVSC); ++ ++ return 0; ++} ++ ++static int ++RndisFilterInitDevice( ++ RNDIS_DEVICE *Device ++ ) ++{ ++ RNDIS_REQUEST *request; ++ RNDIS_INITIALIZE_REQUEST *init; ++ RNDIS_INITIALIZE_COMPLETE *initComplete; ++ UINT32 status; ++ int ret; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ request = GetRndisRequest(Device, REMOTE_NDIS_INITIALIZE_MSG, RNDIS_MESSAGE_SIZE(RNDIS_INITIALIZE_REQUEST)); ++ if (!request) ++ { ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ // Setup the rndis set ++ init = &request->RequestMessage.Message.InitializeRequest; ++ init->MajorVersion = RNDIS_MAJOR_VERSION; ++ init->MinorVersion = RNDIS_MINOR_VERSION; ++ init->MaxTransferSize = 2048; // FIXME: Use 1536 - rounded ethernet frame size ++ ++ Device->State = RNDIS_DEV_INITIALIZING; ++ ++ ret = RndisFilterSendRequest(Device, request); ++ if (ret != 0) ++ { ++ Device->State = RNDIS_DEV_UNINITIALIZED; ++ goto Cleanup; ++ } ++ ++ WaitEventWait(request->WaitEvent); ++ ++ initComplete = &request->ResponseMessage.Message.InitializeComplete; ++ status = initComplete->Status; ++ if (status == RNDIS_STATUS_SUCCESS) ++ { ++ Device->State = RNDIS_DEV_INITIALIZED; ++ ret = 0; ++ } ++ else ++ { ++ Device->State = RNDIS_DEV_UNINITIALIZED; ++ ret = -1; ++ } ++ ++Cleanup: ++ if (request) ++ { ++ PutRndisRequest(Device, request); ++ } ++ DPRINT_EXIT(NETVSC); ++ ++ return ret; ++} ++ ++static void ++RndisFilterHaltDevice( ++ RNDIS_DEVICE *Device ++ ) ++{ ++ RNDIS_REQUEST *request; ++ RNDIS_HALT_REQUEST *halt; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ // Attempt to do a rndis device halt ++ request = GetRndisRequest(Device, REMOTE_NDIS_HALT_MSG, RNDIS_MESSAGE_SIZE(RNDIS_HALT_REQUEST)); ++ if (!request) ++ { ++ goto Cleanup; ++ } ++ ++ // Setup the rndis set ++ halt = &request->RequestMessage.Message.HaltRequest; ++ halt->RequestId = InterlockedIncrement((int*)&Device->NewRequestId); ++ ++ // Ignore return since this msg is optional. ++ RndisFilterSendRequest(Device, request); ++ ++ Device->State = RNDIS_DEV_UNINITIALIZED; ++ ++Cleanup: ++ if (request) ++ { ++ PutRndisRequest(Device, request); ++ } ++ DPRINT_EXIT(NETVSC); ++ return; ++} ++ ++ ++static int ++RndisFilterOpenDevice( ++ RNDIS_DEVICE *Device ++ ) ++{ ++ int ret=0; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ if (Device->State != RNDIS_DEV_INITIALIZED) ++ return 0; ++ ++ ret = RndisFilterSetPacketFilter(Device, NDIS_PACKET_TYPE_BROADCAST|NDIS_PACKET_TYPE_DIRECTED); ++ if (ret == 0) ++ { ++ Device->State = RNDIS_DEV_DATAINITIALIZED; ++ } ++ ++ DPRINT_EXIT(NETVSC); ++ return ret; ++} ++ ++static int ++RndisFilterCloseDevice( ++ RNDIS_DEVICE *Device ++ ) ++{ ++ int ret; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ if (Device->State != RNDIS_DEV_DATAINITIALIZED) ++ return 0; ++ ++ ret = RndisFilterSetPacketFilter(Device, 0); ++ if (ret == 0) ++ { ++ Device->State = RNDIS_DEV_INITIALIZED; ++ } ++ ++ DPRINT_EXIT(NETVSC); ++ ++ return ret; ++} ++ ++ ++int ++RndisFilterOnDeviceAdd( ++ DEVICE_OBJECT *Device, ++ void *AdditionalInfo ++ ) ++{ ++ int ret; ++ NETVSC_DEVICE *netDevice; ++ RNDIS_DEVICE *rndisDevice; ++ NETVSC_DEVICE_INFO *deviceInfo = (NETVSC_DEVICE_INFO*)AdditionalInfo; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ //rndisDevice = MemAlloc(sizeof(RNDIS_DEVICE)); ++ rndisDevice = GetRndisDevice(); ++ if (!rndisDevice) ++ { ++ DPRINT_EXIT(NETVSC); ++ return -1; ++ } ++ ++ DPRINT_DBG(NETVSC, "rndis device object allocated - %p", rndisDevice); ++ ++ // Let the inner driver handle this first to create the netvsc channel ++ // NOTE! Once the channel is created, we may get a receive callback ++ // (RndisFilterOnReceive()) before this call is completed ++ ret = gRndisFilter.InnerDriver.Base.OnDeviceAdd(Device, AdditionalInfo); ++ if (ret != 0) ++ { ++ PutRndisDevice(rndisDevice); ++ DPRINT_EXIT(NETVSC); ++ return ret; ++ } ++ ++ // ++ // Initialize the rndis device ++ // ++ netDevice = (NETVSC_DEVICE*)Device->Extension; ++ ASSERT(netDevice); ++ ASSERT(netDevice->Device); ++ ++ netDevice->Extension = rndisDevice; ++ rndisDevice->NetDevice = netDevice; ++ ++ // Send the rndis initialization message ++ ret = RndisFilterInitDevice(rndisDevice); ++ if (ret != 0) ++ { ++ // TODO: If rndis init failed, we will need to shut down the channel ++ } ++ ++ // Get the mac address ++ ret = RndisFilterQueryDeviceMac(rndisDevice); ++ if (ret != 0) ++ { ++ // TODO: shutdown rndis device and the channel ++ } ++ ++ DPRINT_INFO(NETVSC, "Device 0x%p mac addr %02x%02x%02x%02x%02x%02x", ++ rndisDevice, ++ rndisDevice->HwMacAddr[0], ++ rndisDevice->HwMacAddr[1], ++ rndisDevice->HwMacAddr[2], ++ rndisDevice->HwMacAddr[3], ++ rndisDevice->HwMacAddr[4], ++ rndisDevice->HwMacAddr[5]); ++ ++ memcpy(deviceInfo->MacAddr, rndisDevice->HwMacAddr, HW_MACADDR_LEN); ++ ++ RndisFilterQueryDeviceLinkStatus(rndisDevice); ++ ++ deviceInfo->LinkState = rndisDevice->LinkStatus; ++ DPRINT_INFO(NETVSC, "Device 0x%p link state %s", rndisDevice, ((deviceInfo->LinkState)?("down"):("up"))); ++ ++ DPRINT_EXIT(NETVSC); ++ ++ return ret; ++} ++ ++ ++static int ++RndisFilterOnDeviceRemove( ++ DEVICE_OBJECT *Device ++ ) ++{ ++ NETVSC_DEVICE *netDevice = (NETVSC_DEVICE*)Device->Extension; ++ RNDIS_DEVICE *rndisDevice = (RNDIS_DEVICE*)netDevice->Extension; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ // Halt and release the rndis device ++ RndisFilterHaltDevice(rndisDevice); ++ ++ PutRndisDevice(rndisDevice); ++ netDevice->Extension = NULL; ++ ++ // Pass control to inner driver to remove the device ++ gRndisFilter.InnerDriver.Base.OnDeviceRemove(Device); ++ ++ DPRINT_EXIT(NETVSC); ++ ++ return 0; ++} ++ ++ ++static void ++RndisFilterOnCleanup( ++ DRIVER_OBJECT *Driver ++ ) ++{ ++ DPRINT_ENTER(NETVSC); ++ ++ DPRINT_EXIT(NETVSC); ++} ++ ++static int ++RndisFilterOnOpen( ++ DEVICE_OBJECT *Device ++ ) ++{ ++ int ret; ++ NETVSC_DEVICE *netDevice = (NETVSC_DEVICE*)Device->Extension; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ ASSERT(netDevice); ++ ret = RndisFilterOpenDevice((RNDIS_DEVICE*)netDevice->Extension); ++ ++ DPRINT_EXIT(NETVSC); ++ ++ return ret; ++} ++ ++static int ++RndisFilterOnClose( ++ DEVICE_OBJECT *Device ++ ) ++{ ++ int ret; ++ NETVSC_DEVICE *netDevice = (NETVSC_DEVICE*)Device->Extension; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ ASSERT(netDevice); ++ ret = RndisFilterCloseDevice((RNDIS_DEVICE*)netDevice->Extension); ++ ++ DPRINT_EXIT(NETVSC); ++ ++ return ret; ++} ++ ++ ++static int ++RndisFilterOnSend( ++ DEVICE_OBJECT *Device, ++ NETVSC_PACKET *Packet ++ ) ++{ ++ int ret=0; ++ RNDIS_FILTER_PACKET *filterPacket; ++ RNDIS_MESSAGE *rndisMessage; ++ RNDIS_PACKET *rndisPacket; ++ UINT32 rndisMessageSize; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ // Add the rndis header ++ filterPacket = (RNDIS_FILTER_PACKET*)Packet->Extension; ++ ASSERT(filterPacket); ++ ++ memset(filterPacket, 0, sizeof(RNDIS_FILTER_PACKET)); ++ ++ rndisMessage = &filterPacket->Message; ++ rndisMessageSize = RNDIS_MESSAGE_SIZE(RNDIS_PACKET); ++ ++ rndisMessage->NdisMessageType = REMOTE_NDIS_PACKET_MSG; ++ rndisMessage->MessageLength = Packet->TotalDataBufferLength + rndisMessageSize; ++ ++ rndisPacket = &rndisMessage->Message.Packet; ++ rndisPacket->DataOffset = sizeof(RNDIS_PACKET); ++ rndisPacket->DataLength = Packet->TotalDataBufferLength; ++ ++ Packet->IsDataPacket = TRUE; ++ Packet->PageBuffers[0].Pfn = GetPhysicalAddress(rndisMessage) >> PAGE_SHIFT; ++ Packet->PageBuffers[0].Offset = (ULONG_PTR)rndisMessage & (PAGE_SIZE-1); ++ Packet->PageBuffers[0].Length = rndisMessageSize; ++ ++ // Save the packet send completion and context ++ filterPacket->OnCompletion = Packet->Completion.Send.OnSendCompletion; ++ filterPacket->CompletionContext = Packet->Completion.Send.SendCompletionContext; ++ ++ // Use ours ++ Packet->Completion.Send.OnSendCompletion = RndisFilterOnSendCompletion; ++ Packet->Completion.Send.SendCompletionContext = filterPacket; ++ ++ ret = gRndisFilter.InnerDriver.OnSend(Device, Packet); ++ if (ret != 0) ++ { ++ // Reset the completion to originals to allow retries from above ++ Packet->Completion.Send.OnSendCompletion = filterPacket->OnCompletion; ++ Packet->Completion.Send.SendCompletionContext = filterPacket->CompletionContext; ++ } ++ ++ DPRINT_EXIT(NETVSC); ++ ++ return ret; ++} ++ ++static void ++RndisFilterOnSendCompletion( ++ void *Context) ++{ ++ RNDIS_FILTER_PACKET *filterPacket = (RNDIS_FILTER_PACKET *)Context; ++ ++ DPRINT_ENTER(NETVSC); ++ ++ // Pass it back to the original handler ++ filterPacket->OnCompletion(filterPacket->CompletionContext); ++ ++ DPRINT_EXIT(NETVSC); ++} ++ ++ ++static void ++RndisFilterOnSendRequestCompletion( ++ void *Context ++ ) ++{ ++ DPRINT_ENTER(NETVSC); ++ ++ // Noop ++ DPRINT_EXIT(NETVSC); ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/RndisFilter.h linux-2.6.27.29-0.1.1/drivers/staging/hv/RndisFilter.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/RndisFilter.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,61 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _RNDISFILTER_H_ ++#define _RNDISFILTER_H_ ++ ++#define __struct_bcount(x) ++ ++#include "include/osd.h" ++#include "NetVsc.h" ++ ++#include "include/rndis.h" ++ ++#define RNDIS_HEADER_SIZE (sizeof(RNDIS_MESSAGE) - sizeof(RNDIS_MESSAGE_CONTAINER)) ++ ++#define NDIS_PACKET_TYPE_DIRECTED 0x00000001 ++#define NDIS_PACKET_TYPE_MULTICAST 0x00000002 ++#define NDIS_PACKET_TYPE_ALL_MULTICAST 0x00000004 ++#define NDIS_PACKET_TYPE_BROADCAST 0x00000008 ++#define NDIS_PACKET_TYPE_SOURCE_ROUTING 0x00000010 ++#define NDIS_PACKET_TYPE_PROMISCUOUS 0x00000020 ++#define NDIS_PACKET_TYPE_SMT 0x00000040 ++#define NDIS_PACKET_TYPE_ALL_LOCAL 0x00000080 ++#define NDIS_PACKET_TYPE_GROUP 0x00000100 ++#define NDIS_PACKET_TYPE_ALL_FUNCTIONAL 0x00000200 ++#define NDIS_PACKET_TYPE_FUNCTIONAL 0x00000400 ++#define NDIS_PACKET_TYPE_MAC_FRAME 0x00000800 ++ ++ ++ ++// ++// Interface ++// ++int ++RndisFilterInit( ++ NETVSC_DRIVER_OBJECT *Driver ++ ); ++ ++ ++#endif // _RNDISFILTER_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/Sources.c linux-2.6.27.29-0.1.1/drivers/staging/hv/Sources.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/Sources.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,32 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++#define KERNEL_2_6_27 ++ ++#include "Vmbus.c" ++#include "Hv.c" ++#include "Connection.c" ++#include "Channel.c" ++#include "ChannelMgmt.c" ++#include "ChannelInterface.c" ++#include "RingBuffer.c" +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/StorVsc.c linux-2.6.27.29-0.1.1/drivers/staging/hv/StorVsc.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/StorVsc.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,968 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++#define KERNEL_2_6_27 ++ ++#include "include/logging.h" ++ ++#include "include/StorVscApi.h" ++#include "include/VmbusPacketFormat.h" ++#include "include/vstorage.h" ++ ++ ++// ++// #defines ++// ++ ++// ++// Data types ++// ++ ++typedef struct _STORVSC_REQUEST_EXTENSION { ++ //LIST_ENTRY ListEntry; ++ ++ STORVSC_REQUEST *Request; ++ DEVICE_OBJECT *Device; ++ ++ // Synchronize the request/response if needed ++ HANDLE WaitEvent; ++ ++ VSTOR_PACKET VStorPacket; ++} STORVSC_REQUEST_EXTENSION; ++ ++ ++// A storvsc device is a device object that contains a vmbus channel ++typedef struct _STORVSC_DEVICE{ ++ DEVICE_OBJECT *Device; ++ ++ int RefCount; // 0 indicates the device is being destroyed ++ ++ int NumOutstandingRequests; ++ ++ // Each unique Port/Path/Target represents 1 channel ie scsi controller. In reality, the pathid, targetid is always 0 ++ // and the port is set by us ++ ULONG PortNumber; ++ UCHAR PathId; ++ UCHAR TargetId; ++ ++ //LIST_ENTRY OutstandingRequestList; ++ //HANDLE OutstandingRequestLock; ++ ++ // Used for vsc/vsp channel reset process ++ STORVSC_REQUEST_EXTENSION InitRequest; ++ ++ STORVSC_REQUEST_EXTENSION ResetRequest; ++ ++} STORVSC_DEVICE; ++ ++ ++// ++// Globals ++// ++static const char* gDriverName="storvsc"; ++ ++//{ba6163d9-04a1-4d29-b605-72e2ffb1dc7f} ++static const GUID gStorVscDeviceType={ ++ .Data = {0xd9, 0x63, 0x61, 0xba, 0xa1, 0x04, 0x29, 0x4d, 0xb6, 0x05, 0x72, 0xe2, 0xff, 0xb1, 0xdc, 0x7f} ++}; ++ ++// ++// Internal routines ++// ++static int ++StorVscOnDeviceAdd( ++ DEVICE_OBJECT *Device, ++ void *AdditionalInfo ++ ); ++ ++static int ++StorVscOnDeviceRemove( ++ DEVICE_OBJECT *Device ++ ); ++ ++static int ++StorVscOnIORequest( ++ DEVICE_OBJECT *Device, ++ STORVSC_REQUEST *Request ++ ); ++ ++static int ++StorVscOnHostReset( ++ DEVICE_OBJECT *Device ++ ); ++ ++static void ++StorVscOnCleanup( ++ DRIVER_OBJECT *Device ++ ); ++ ++static void ++StorVscOnChannelCallback( ++ PVOID Context ++ ); ++ ++static void ++StorVscOnIOCompletion( ++ DEVICE_OBJECT *Device, ++ VSTOR_PACKET *VStorPacket, ++ STORVSC_REQUEST_EXTENSION *RequestExt ++ ); ++ ++static void ++StorVscOnReceive( ++ DEVICE_OBJECT *Device, ++ VSTOR_PACKET *VStorPacket, ++ STORVSC_REQUEST_EXTENSION *RequestExt ++ ); ++ ++static int ++StorVscConnectToVsp( ++ DEVICE_OBJECT *Device ++ ); ++ ++static inline STORVSC_DEVICE* AllocStorDevice(DEVICE_OBJECT *Device) ++{ ++ STORVSC_DEVICE *storDevice; ++ ++ storDevice = MemAllocZeroed(sizeof(STORVSC_DEVICE)); ++ if (!storDevice) ++ return NULL; ++ ++ // Set to 2 to allow both inbound and outbound traffics ++ // (ie GetStorDevice() and MustGetStorDevice()) to proceed. ++ InterlockedCompareExchange(&storDevice->RefCount, 2, 0); ++ ++ storDevice->Device = Device; ++ Device->Extension = storDevice; ++ ++ return storDevice; ++} ++ ++static inline void FreeStorDevice(STORVSC_DEVICE *Device) ++{ ++ ASSERT(Device->RefCount == 0); ++ MemFree(Device); ++} ++ ++// Get the stordevice object iff exists and its refcount > 1 ++static inline STORVSC_DEVICE* GetStorDevice(DEVICE_OBJECT *Device) ++{ ++ STORVSC_DEVICE *storDevice; ++ ++ storDevice = (STORVSC_DEVICE*)Device->Extension; ++ if (storDevice && storDevice->RefCount > 1) ++ { ++ InterlockedIncrement(&storDevice->RefCount); ++ } ++ else ++ { ++ storDevice = NULL; ++ } ++ ++ return storDevice; ++} ++ ++// Get the stordevice object iff exists and its refcount > 0 ++static inline STORVSC_DEVICE* MustGetStorDevice(DEVICE_OBJECT *Device) ++{ ++ STORVSC_DEVICE *storDevice; ++ ++ storDevice = (STORVSC_DEVICE*)Device->Extension; ++ if (storDevice && storDevice->RefCount) ++ { ++ InterlockedIncrement(&storDevice->RefCount); ++ } ++ else ++ { ++ storDevice = NULL; ++ } ++ ++ return storDevice; ++} ++ ++static inline void PutStorDevice(DEVICE_OBJECT *Device) ++{ ++ STORVSC_DEVICE *storDevice; ++ ++ storDevice = (STORVSC_DEVICE*)Device->Extension; ++ ASSERT(storDevice); ++ ++ InterlockedDecrement(&storDevice->RefCount); ++ ASSERT(storDevice->RefCount); ++} ++ ++// Drop ref count to 1 to effectively disable GetStorDevice() ++static inline STORVSC_DEVICE* ReleaseStorDevice(DEVICE_OBJECT *Device) ++{ ++ STORVSC_DEVICE *storDevice; ++ ++ storDevice = (STORVSC_DEVICE*)Device->Extension; ++ ASSERT(storDevice); ++ ++ // Busy wait until the ref drop to 2, then set it to 1 ++ while (InterlockedCompareExchange(&storDevice->RefCount, 1, 2) != 2) ++ { ++ Sleep(100); ++ } ++ ++ return storDevice; ++} ++ ++// Drop ref count to 0. No one can use StorDevice object. ++static inline STORVSC_DEVICE* FinalReleaseStorDevice(DEVICE_OBJECT *Device) ++{ ++ STORVSC_DEVICE *storDevice; ++ ++ storDevice = (STORVSC_DEVICE*)Device->Extension; ++ ASSERT(storDevice); ++ ++ // Busy wait until the ref drop to 1, then set it to 0 ++ while (InterlockedCompareExchange(&storDevice->RefCount, 0, 1) != 1) ++ { ++ Sleep(100); ++ } ++ ++ Device->Extension = NULL; ++ return storDevice; ++} ++ ++/*++; ++ ++ ++Name: ++ StorVscInitialize() ++ ++Description: ++ Main entry point ++ ++--*/ ++int ++StorVscInitialize( ++ DRIVER_OBJECT *Driver ++ ) ++{ ++ STORVSC_DRIVER_OBJECT* storDriver = (STORVSC_DRIVER_OBJECT*)Driver; ++ int ret=0; ++ ++ DPRINT_ENTER(STORVSC); ++ ++ DPRINT_DBG(STORVSC, "sizeof(STORVSC_REQUEST)=%d sizeof(STORVSC_REQUEST_EXTENSION)=%d sizeof(VSTOR_PACKET)=%d, sizeof(VMSCSI_REQUEST)=%d", ++ sizeof(STORVSC_REQUEST), sizeof(STORVSC_REQUEST_EXTENSION), sizeof(VSTOR_PACKET), sizeof(VMSCSI_REQUEST)); ++ ++ // Make sure we are at least 2 pages since 1 page is used for control ++ ASSERT(storDriver->RingBufferSize >= (PAGE_SIZE << 1)); ++ ++ Driver->name = gDriverName; ++ memcpy(&Driver->deviceType, &gStorVscDeviceType, sizeof(GUID)); ++ ++ storDriver->RequestExtSize = sizeof(STORVSC_REQUEST_EXTENSION); ++ ++ // Divide the ring buffer data size (which is 1 page less than the ring buffer size since that page is reserved for the ring buffer indices) ++ // by the max request size (which is VMBUS_CHANNEL_PACKET_MULITPAGE_BUFFER + VSTOR_PACKET + UINT64) ++ storDriver->MaxOutstandingRequestsPerChannel = ++ ((storDriver->RingBufferSize - PAGE_SIZE) / ALIGN_UP(MAX_MULTIPAGE_BUFFER_PACKET + sizeof(VSTOR_PACKET) + sizeof(UINT64),sizeof(UINT64))); ++ ++ DPRINT_INFO(STORVSC, "max io %u, currently %u\n", storDriver->MaxOutstandingRequestsPerChannel, STORVSC_MAX_IO_REQUESTS); ++ ++ // Setup the dispatch table ++ storDriver->Base.OnDeviceAdd = StorVscOnDeviceAdd; ++ storDriver->Base.OnDeviceRemove = StorVscOnDeviceRemove; ++ storDriver->Base.OnCleanup = StorVscOnCleanup; ++ ++ storDriver->OnIORequest = StorVscOnIORequest; ++ storDriver->OnHostReset = StorVscOnHostReset; ++ ++ DPRINT_EXIT(STORVSC); ++ ++ return ret; ++} ++ ++/*++ ++ ++Name: ++ StorVscOnDeviceAdd() ++ ++Description: ++ Callback when the device belonging to this driver is added ++ ++--*/ ++int ++StorVscOnDeviceAdd( ++ DEVICE_OBJECT *Device, ++ void *AdditionalInfo ++ ) ++{ ++ int ret=0; ++ STORVSC_DEVICE *storDevice; ++ //VMSTORAGE_CHANNEL_PROPERTIES *props; ++ STORVSC_DEVICE_INFO *deviceInfo = (STORVSC_DEVICE_INFO*)AdditionalInfo; ++ ++ DPRINT_ENTER(STORVSC); ++ ++ storDevice = AllocStorDevice(Device); ++ if (!storDevice) ++ { ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ // Save the channel properties to our storvsc channel ++ //props = (VMSTORAGE_CHANNEL_PROPERTIES*) channel->offerMsg.Offer.u.Standard.UserDefined; ++ ++ // FIXME: ++ // If we support more than 1 scsi channel, we need to set the port number here ++ // to the scsi channel but how do we get the scsi channel prior to the bus scan ++ /*storChannel->PortNumber = 0; ++ storChannel->PathId = props->PathId; ++ storChannel->TargetId = props->TargetId;*/ ++ ++ storDevice->PortNumber = deviceInfo->PortNumber; ++ // Send it back up ++ ret = StorVscConnectToVsp(Device); ++ ++ //deviceInfo->PortNumber = storDevice->PortNumber; ++ deviceInfo->PathId = storDevice->PathId; ++ deviceInfo->TargetId = storDevice->TargetId; ++ ++ DPRINT_DBG(STORVSC, "assigned port %u, path %u target %u\n", storDevice->PortNumber, storDevice->PathId, storDevice->TargetId); ++ ++Cleanup: ++ DPRINT_EXIT(STORVSC); ++ ++ return ret; ++} ++ ++static int StorVscChannelInit(DEVICE_OBJECT *Device) ++{ ++ int ret=0; ++ STORVSC_DEVICE *storDevice; ++ STORVSC_REQUEST_EXTENSION *request; ++ VSTOR_PACKET *vstorPacket; ++ ++ storDevice = GetStorDevice(Device); ++ if (!storDevice) ++ { ++ DPRINT_ERR(STORVSC, "unable to get stor device...device being destroyed?"); ++ DPRINT_EXIT(STORVSC); ++ return -1; ++ } ++ ++ request = &storDevice->InitRequest; ++ vstorPacket = &request->VStorPacket; ++ ++ // Now, initiate the vsc/vsp initialization protocol on the open channel ++ ++ memset(request, sizeof(STORVSC_REQUEST_EXTENSION), 0); ++ request->WaitEvent = WaitEventCreate(); ++ ++ vstorPacket->Operation = VStorOperationBeginInitialization; ++ vstorPacket->Flags = REQUEST_COMPLETION_FLAG; ++ ++ /*SpinlockAcquire(gDriverExt.packetListLock); ++ INSERT_TAIL_LIST(&gDriverExt.packetList, &packet->listEntry.entry); ++ SpinlockRelease(gDriverExt.packetListLock);*/ ++ ++ DPRINT_INFO(STORVSC, "BEGIN_INITIALIZATION_OPERATION..."); ++ ++ ret = Device->Driver->VmbusChannelInterface.SendPacket(Device, ++ vstorPacket, ++ sizeof(VSTOR_PACKET), ++ (ULONG_PTR)request, ++ VmbusPacketTypeDataInBand, ++ VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED); ++ if ( ret != 0) ++ { ++ DPRINT_ERR(STORVSC, "unable to send BEGIN_INITIALIZATION_OPERATION"); ++ goto Cleanup; ++ } ++ ++ WaitEventWait(request->WaitEvent); ++ ++ if (vstorPacket->Operation != VStorOperationCompleteIo || vstorPacket->Status != 0) ++ { ++ DPRINT_ERR(STORVSC, "BEGIN_INITIALIZATION_OPERATION failed (op %d status 0x%x)", vstorPacket->Operation, vstorPacket->Status); ++ goto Cleanup; ++ } ++ ++ DPRINT_INFO(STORVSC, "QUERY_PROTOCOL_VERSION_OPERATION..."); ++ ++ // reuse the packet for version range supported ++ memset(vstorPacket, sizeof(VSTOR_PACKET), 0); ++ vstorPacket->Operation = VStorOperationQueryProtocolVersion; ++ vstorPacket->Flags = REQUEST_COMPLETION_FLAG; ++ ++ vstorPacket->Version.MajorMinor = VMSTOR_PROTOCOL_VERSION_CURRENT; ++ FILL_VMSTOR_REVISION(vstorPacket->Version.Revision); ++ ++ ret = Device->Driver->VmbusChannelInterface.SendPacket(Device, ++ vstorPacket, ++ sizeof(VSTOR_PACKET), ++ (ULONG_PTR)request, ++ VmbusPacketTypeDataInBand, ++ VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED); ++ if ( ret != 0) ++ { ++ DPRINT_ERR(STORVSC, "unable to send BEGIN_INITIALIZATION_OPERATION"); ++ goto Cleanup; ++ } ++ ++ WaitEventWait(request->WaitEvent); ++ ++ // TODO: Check returned version ++ if (vstorPacket->Operation != VStorOperationCompleteIo || vstorPacket->Status != 0) ++ { ++ DPRINT_ERR(STORVSC, "QUERY_PROTOCOL_VERSION_OPERATION failed (op %d status 0x%x)", vstorPacket->Operation, vstorPacket->Status); ++ goto Cleanup; ++ } ++ ++ // Query channel properties ++ DPRINT_INFO(STORVSC, "QUERY_PROPERTIES_OPERATION..."); ++ ++ memset(vstorPacket, sizeof(VSTOR_PACKET), 0); ++ vstorPacket->Operation = VStorOperationQueryProperties; ++ vstorPacket->Flags = REQUEST_COMPLETION_FLAG; ++ vstorPacket->StorageChannelProperties.PortNumber = storDevice->PortNumber; ++ ++ ret = Device->Driver->VmbusChannelInterface.SendPacket(Device, ++ vstorPacket, ++ sizeof(VSTOR_PACKET), ++ (ULONG_PTR)request, ++ VmbusPacketTypeDataInBand, ++ VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED); ++ ++ if ( ret != 0) ++ { ++ DPRINT_ERR(STORVSC, "unable to send QUERY_PROPERTIES_OPERATION"); ++ goto Cleanup; ++ } ++ ++ WaitEventWait(request->WaitEvent); ++ ++ // TODO: Check returned version ++ if (vstorPacket->Operation != VStorOperationCompleteIo || vstorPacket->Status != 0) ++ { ++ DPRINT_ERR(STORVSC, "QUERY_PROPERTIES_OPERATION failed (op %d status 0x%x)", vstorPacket->Operation, vstorPacket->Status); ++ goto Cleanup; ++ } ++ ++ //storDevice->PortNumber = vstorPacket->StorageChannelProperties.PortNumber; ++ storDevice->PathId = vstorPacket->StorageChannelProperties.PathId; ++ storDevice->TargetId = vstorPacket->StorageChannelProperties.TargetId; ++ ++ DPRINT_DBG(STORVSC, "channel flag 0x%x, max xfer len 0x%x", vstorPacket->StorageChannelProperties.Flags, vstorPacket->StorageChannelProperties.MaxTransferBytes); ++ ++ DPRINT_INFO(STORVSC, "END_INITIALIZATION_OPERATION..."); ++ ++ memset(vstorPacket, sizeof(VSTOR_PACKET), 0); ++ vstorPacket->Operation = VStorOperationEndInitialization; ++ vstorPacket->Flags = REQUEST_COMPLETION_FLAG; ++ ++ ret = Device->Driver->VmbusChannelInterface.SendPacket(Device, ++ vstorPacket, ++ sizeof(VSTOR_PACKET), ++ (ULONG_PTR)request, ++ VmbusPacketTypeDataInBand, ++ VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED); ++ ++ if ( ret != 0) ++ { ++ DPRINT_ERR(STORVSC, "unable to send END_INITIALIZATION_OPERATION"); ++ goto Cleanup; ++ } ++ ++ WaitEventWait(request->WaitEvent); ++ ++ if (vstorPacket->Operation != VStorOperationCompleteIo || vstorPacket->Status != 0) ++ { ++ DPRINT_ERR(STORVSC, "END_INITIALIZATION_OPERATION failed (op %d status 0x%x)", vstorPacket->Operation, vstorPacket->Status); ++ goto Cleanup; ++ } ++ ++ DPRINT_INFO(STORVSC, "**** storage channel up and running!! ****"); ++ ++Cleanup: ++ if (request->WaitEvent) ++ { ++ WaitEventClose(request->WaitEvent); ++ request->WaitEvent = NULL; ++ } ++ ++ PutStorDevice(Device); ++ ++ DPRINT_EXIT(STORVSC); ++ return ret; ++} ++ ++ ++int ++StorVscConnectToVsp( ++ DEVICE_OBJECT *Device ++ ) ++{ ++ int ret=0; ++ VMSTORAGE_CHANNEL_PROPERTIES props; ++ ++ STORVSC_DRIVER_OBJECT *storDriver = (STORVSC_DRIVER_OBJECT*) Device->Driver;; ++ ++ memset(&props, sizeof(VMSTORAGE_CHANNEL_PROPERTIES), 0); ++ ++ // Open the channel ++ ret = Device->Driver->VmbusChannelInterface.Open(Device, ++ storDriver->RingBufferSize, ++ storDriver->RingBufferSize, ++ (PVOID)&props, ++ sizeof(VMSTORAGE_CHANNEL_PROPERTIES), ++ StorVscOnChannelCallback, ++ Device ++ ); ++ ++ DPRINT_DBG(STORVSC, "storage props: path id %d, tgt id %d, max xfer %d", props.PathId, props.TargetId, props.MaxTransferBytes); ++ ++ if (ret != 0) ++ { ++ DPRINT_ERR(STORVSC, "unable to open channel: %d", ret); ++ return -1; ++ } ++ ++ ret = StorVscChannelInit(Device); ++ ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: ++ StorVscOnDeviceRemove() ++ ++Description: ++ Callback when the our device is being removed ++ ++--*/ ++int ++StorVscOnDeviceRemove( ++ DEVICE_OBJECT *Device ++ ) ++{ ++ STORVSC_DEVICE *storDevice; ++ int ret=0; ++ ++ DPRINT_ENTER(STORVSC); ++ ++ DPRINT_INFO(STORVSC, "disabling storage device (%p)...", Device->Extension); ++ ++ storDevice = ReleaseStorDevice(Device); ++ ++ // At this point, all outbound traffic should be disable. We only allow inbound traffic (responses) to proceed ++ // so that outstanding requests can be completed. ++ while (storDevice->NumOutstandingRequests) ++ { ++ DPRINT_INFO(STORVSC, "waiting for %d requests to complete...", storDevice->NumOutstandingRequests); ++ ++ Sleep(100); ++ } ++ ++ DPRINT_INFO(STORVSC, "removing storage device (%p)...", Device->Extension); ++ ++ storDevice = FinalReleaseStorDevice(Device); ++ ++ DPRINT_INFO(STORVSC, "storage device (%p) safe to remove", storDevice); ++ ++ // Close the channel ++ Device->Driver->VmbusChannelInterface.Close(Device); ++ ++ FreeStorDevice(storDevice); ++ ++ DPRINT_EXIT(STORVSC); ++ return ret; ++} ++ ++ ++//static void ++//StorVscOnTargetRescan( ++// void *Context ++// ) ++//{ ++// DEVICE_OBJECT *device=(DEVICE_OBJECT*)Context; ++// STORVSC_DRIVER_OBJECT *storDriver; ++// ++// DPRINT_ENTER(STORVSC); ++// ++// storDriver = (STORVSC_DRIVER_OBJECT*) device->Driver; ++// storDriver->OnHostRescan(device); ++// ++// DPRINT_EXIT(STORVSC); ++//} ++ ++int ++StorVscOnHostReset( ++ DEVICE_OBJECT *Device ++ ) ++{ ++ int ret=0; ++ ++ STORVSC_DEVICE *storDevice; ++ STORVSC_REQUEST_EXTENSION *request; ++ VSTOR_PACKET *vstorPacket; ++ ++ DPRINT_ENTER(STORVSC); ++ ++ DPRINT_INFO(STORVSC, "resetting host adapter..."); ++ ++ storDevice = GetStorDevice(Device); ++ if (!storDevice) ++ { ++ DPRINT_ERR(STORVSC, "unable to get stor device...device being destroyed?"); ++ DPRINT_EXIT(STORVSC); ++ return -1; ++ } ++ ++ request = &storDevice->ResetRequest; ++ vstorPacket = &request->VStorPacket; ++ ++ request->WaitEvent = WaitEventCreate(); ++ ++ vstorPacket->Operation = VStorOperationResetBus; ++ vstorPacket->Flags = REQUEST_COMPLETION_FLAG; ++ vstorPacket->VmSrb.PathId = storDevice->PathId; ++ ++ ret = Device->Driver->VmbusChannelInterface.SendPacket(Device, ++ vstorPacket, ++ sizeof(VSTOR_PACKET), ++ (ULONG_PTR)&storDevice->ResetRequest, ++ VmbusPacketTypeDataInBand, ++ VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED); ++ if (ret != 0) ++ { ++ DPRINT_ERR(STORVSC, "Unable to send reset packet %p ret %d", vstorPacket, ret); ++ goto Cleanup; ++ } ++ ++ // FIXME: Add a timeout ++ WaitEventWait(request->WaitEvent); ++ ++ WaitEventClose(request->WaitEvent); ++ DPRINT_INFO(STORVSC, "host adapter reset completed"); ++ ++ // At this point, all outstanding requests in the adapter should have been flushed out and return to us ++ ++Cleanup: ++ PutStorDevice(Device); ++ DPRINT_EXIT(STORVSC); ++ return ret; ++} ++ ++/*++ ++ ++Name: ++ StorVscOnIORequest() ++ ++Description: ++ Callback to initiate an I/O request ++ ++--*/ ++int ++StorVscOnIORequest( ++ DEVICE_OBJECT *Device, ++ STORVSC_REQUEST *Request ++ ) ++{ ++ STORVSC_DEVICE *storDevice; ++ STORVSC_REQUEST_EXTENSION* requestExtension = (STORVSC_REQUEST_EXTENSION*) Request->Extension; ++ VSTOR_PACKET* vstorPacket =&requestExtension->VStorPacket; ++ int ret=0; ++ ++ DPRINT_ENTER(STORVSC); ++ ++ storDevice = GetStorDevice(Device); ++ ++ DPRINT_DBG(STORVSC, "enter - Device %p, DeviceExt %p, Request %p, Extension %p", ++ Device, storDevice, Request, requestExtension); ++ ++ DPRINT_DBG(STORVSC, "req %p len %d bus %d, target %d, lun %d cdblen %d", ++ Request, Request->DataBuffer.Length, Request->Bus, Request->TargetId, Request->LunId, Request->CdbLen); ++ ++ if (!storDevice) ++ { ++ DPRINT_ERR(STORVSC, "unable to get stor device...device being destroyed?"); ++ DPRINT_EXIT(STORVSC); ++ return -2; ++ } ++ ++ //PrintBytes(Request->Cdb, Request->CdbLen); ++ ++ requestExtension->Request = Request; ++ requestExtension->Device = Device; ++ ++ memset(vstorPacket, 0 , sizeof(VSTOR_PACKET)); ++ ++ vstorPacket->Flags |= REQUEST_COMPLETION_FLAG; ++ ++ vstorPacket->VmSrb.Length = sizeof(VMSCSI_REQUEST); ++ ++ vstorPacket->VmSrb.PortNumber = Request->Host; ++ vstorPacket->VmSrb.PathId = Request->Bus; ++ vstorPacket->VmSrb.TargetId = Request->TargetId; ++ vstorPacket->VmSrb.Lun = Request->LunId; ++ ++ vstorPacket->VmSrb.SenseInfoLength = SENSE_BUFFER_SIZE; ++ ++ // Copy over the scsi command descriptor block ++ vstorPacket->VmSrb.CdbLength = Request->CdbLen; ++ memcpy(&vstorPacket->VmSrb.Cdb, Request->Cdb, Request->CdbLen); ++ ++ vstorPacket->VmSrb.DataIn = Request->Type; ++ vstorPacket->VmSrb.DataTransferLength = Request->DataBuffer.Length; ++ ++ vstorPacket->Operation = VStorOperationExecuteSRB; ++ ++ DPRINT_DBG(STORVSC, "srb - len %d port %d, path %d, target %d, lun %d senselen %d cdblen %d", ++ vstorPacket->VmSrb.Length, ++ vstorPacket->VmSrb.PortNumber, ++ vstorPacket->VmSrb.PathId, ++ vstorPacket->VmSrb.TargetId, ++ vstorPacket->VmSrb.Lun, ++ vstorPacket->VmSrb.SenseInfoLength, ++ vstorPacket->VmSrb.CdbLength); ++ ++ if (requestExtension->Request->DataBuffer.Length) ++ { ++ ret = Device->Driver->VmbusChannelInterface.SendPacketMultiPageBuffer(Device, ++ &requestExtension->Request->DataBuffer, ++ vstorPacket, ++ sizeof(VSTOR_PACKET), ++ (ULONG_PTR)requestExtension); ++ } ++ else ++ { ++ ret = Device->Driver->VmbusChannelInterface.SendPacket(Device, ++ vstorPacket, ++ sizeof(VSTOR_PACKET), ++ (ULONG_PTR)requestExtension, ++ VmbusPacketTypeDataInBand, ++ VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED); ++ } ++ ++ if (ret != 0) ++ { ++ DPRINT_DBG(STORVSC, "Unable to send packet %p ret %d", vstorPacket, ret); ++ } ++ ++ InterlockedIncrement(&storDevice->NumOutstandingRequests); ++ ++ PutStorDevice(Device); ++ ++ DPRINT_EXIT(STORVSC); ++ return ret; ++} ++ ++/*++ ++ ++Name: ++ StorVscOnCleanup() ++ ++Description: ++ Perform any cleanup when the driver is removed ++ ++--*/ ++void ++StorVscOnCleanup( ++ DRIVER_OBJECT *Driver ++ ) ++{ ++ DPRINT_ENTER(STORVSC); ++ DPRINT_EXIT(STORVSC); ++} ++ ++ ++static void ++StorVscOnIOCompletion( ++ DEVICE_OBJECT *Device, ++ VSTOR_PACKET *VStorPacket, ++ STORVSC_REQUEST_EXTENSION *RequestExt ++ ) ++{ ++ STORVSC_REQUEST *request; ++ STORVSC_DEVICE *storDevice; ++ ++ DPRINT_ENTER(STORVSC); ++ ++ storDevice = MustGetStorDevice(Device); ++ if (!storDevice) ++ { ++ DPRINT_ERR(STORVSC, "unable to get stor device...device being destroyed?"); ++ DPRINT_EXIT(STORVSC); ++ return; ++ } ++ ++ DPRINT_DBG(STORVSC, "IO_COMPLETE_OPERATION - request extension %p completed bytes xfer %u", ++ RequestExt, VStorPacket->VmSrb.DataTransferLength); ++ ++ ASSERT(RequestExt != NULL); ++ ASSERT(RequestExt->Request != NULL); ++ ++ request = RequestExt->Request; ++ ++ ASSERT(request->OnIOCompletion != NULL); ++ ++ // Copy over the status...etc ++ request->Status = VStorPacket->VmSrb.ScsiStatus; ++ ++ if (request->Status != 0 || VStorPacket->VmSrb.SrbStatus != 1) ++ { ++ DPRINT_WARN(STORVSC, "cmd 0x%x scsi status 0x%x srb status 0x%x\n", ++ request->Cdb[0], ++ VStorPacket->VmSrb.ScsiStatus, ++ VStorPacket->VmSrb.SrbStatus); ++ } ++ ++ if ((request->Status & 0xFF) == 0x02) // CHECK_CONDITION ++ { ++ if (VStorPacket->VmSrb.SrbStatus & 0x80) // autosense data available ++ { ++ DPRINT_WARN(STORVSC, "storvsc pkt %p autosense data valid - len %d\n", ++ RequestExt, VStorPacket->VmSrb.SenseInfoLength); ++ ++ ASSERT(VStorPacket->VmSrb.SenseInfoLength <= request->SenseBufferSize); ++ memcpy(request->SenseBuffer, ++ VStorPacket->VmSrb.SenseData, ++ VStorPacket->VmSrb.SenseInfoLength); ++ ++ request->SenseBufferSize = VStorPacket->VmSrb.SenseInfoLength; ++ } ++ } ++ ++ // TODO: ++ request->BytesXfer = VStorPacket->VmSrb.DataTransferLength; ++ ++ request->OnIOCompletion(request); ++ ++ InterlockedDecrement(&storDevice->NumOutstandingRequests); ++ ++ PutStorDevice(Device); ++ ++ DPRINT_EXIT(STORVSC); ++} ++ ++ ++static void ++StorVscOnReceive( ++ DEVICE_OBJECT *Device, ++ VSTOR_PACKET *VStorPacket, ++ STORVSC_REQUEST_EXTENSION *RequestExt ++ ) ++{ ++ switch(VStorPacket->Operation) ++ { ++ case VStorOperationCompleteIo: ++ ++ DPRINT_DBG(STORVSC, "IO_COMPLETE_OPERATION"); ++ StorVscOnIOCompletion(Device, VStorPacket, RequestExt); ++ break; ++ ++ //case ENUMERATE_DEVICE_OPERATION: ++ ++ // DPRINT_INFO(STORVSC, "ENUMERATE_DEVICE_OPERATION"); ++ ++ // StorVscOnTargetRescan(Device); ++ // break; ++ ++ case VStorOperationRemoveDevice: ++ ++ DPRINT_INFO(STORVSC, "REMOVE_DEVICE_OPERATION"); ++ // TODO: ++ break; ++ ++ default: ++ DPRINT_INFO(STORVSC, "Unknown operation received - %d", VStorPacket->Operation); ++ break; ++ } ++} ++ ++void ++StorVscOnChannelCallback( ++ PVOID Context ++ ) ++{ ++ int ret=0; ++ DEVICE_OBJECT *device = (DEVICE_OBJECT*)Context; ++ STORVSC_DEVICE *storDevice; ++ UINT32 bytesRecvd; ++ UINT64 requestId; ++ UCHAR packet[ALIGN_UP(sizeof(VSTOR_PACKET),8)]; ++ STORVSC_REQUEST_EXTENSION *request; ++ ++ DPRINT_ENTER(STORVSC); ++ ++ ASSERT(device); ++ ++ storDevice = MustGetStorDevice(device); ++ if (!storDevice) ++ { ++ DPRINT_ERR(STORVSC, "unable to get stor device...device being destroyed?"); ++ DPRINT_EXIT(STORVSC); ++ return; ++ } ++ ++ do ++ { ++ ret = device->Driver->VmbusChannelInterface.RecvPacket(device, ++ packet, ++ ALIGN_UP(sizeof(VSTOR_PACKET),8), ++ &bytesRecvd, ++ &requestId); ++ if (ret == 0 && bytesRecvd > 0) ++ { ++ DPRINT_DBG(STORVSC, "receive %d bytes - tid %llx", bytesRecvd, requestId); ++ ++ //ASSERT(bytesRecvd == sizeof(VSTOR_PACKET)); ++ ++ request = (STORVSC_REQUEST_EXTENSION*)(ULONG_PTR)requestId; ++ ASSERT(request); ++ ++ //if (vstorPacket.Flags & SYNTHETIC_FLAG) ++ if ((request == &storDevice->InitRequest) || (request == &storDevice->ResetRequest)) ++ { ++ //DPRINT_INFO(STORVSC, "reset completion - operation %u status %u", vstorPacket.Operation, vstorPacket.Status); ++ ++ memcpy(&request->VStorPacket, packet, sizeof(VSTOR_PACKET)); ++ ++ WaitEventSet(request->WaitEvent); ++ } ++ else ++ { ++ StorVscOnReceive(device, (VSTOR_PACKET*)packet, request); ++ } ++ } ++ else ++ { ++ //DPRINT_DBG(STORVSC, "nothing else to read..."); ++ break; ++ } ++ } while (1); ++ ++ PutStorDevice(device); ++ ++ DPRINT_EXIT(STORVSC); ++ return; ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/storvsc_drv.c linux-2.6.27.29-0.1.1/drivers/staging/hv/storvsc_drv.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/storvsc_drv.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,1414 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++#define KERNEL_2_6_27 ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef KERNEL_2_6_5 ++#else ++#include ++#endif ++ ++#include "include/logging.h" ++#include "include/vmbus.h" ++ ++#include "include/StorVscApi.h" ++ ++// ++// #defines ++// ++ ++// ++// Data types ++// ++struct host_device_context { ++ struct work_struct host_rescan_work; //must be 1st field ++ struct device_context *device_ctx; // point back to our device context ++#ifdef KERNEL_2_6_27 ++ struct kmem_cache *request_pool; ++#else ++ kmem_cache_t *request_pool; ++#endif ++ unsigned int port; ++ unsigned char path; ++ unsigned char target; ++}; ++ ++struct storvsc_cmd_request { ++ struct list_head entry; ++ struct scsi_cmnd *cmd; ++ ++ unsigned int bounce_sgl_count; ++ struct scatterlist *bounce_sgl; ++ ++ STORVSC_REQUEST request; ++ // !!!DO NOT ADD ANYTHING BELOW HERE!!! ++ // The extension buffer falls right here and is pointed to by request.Extension; ++}; ++ ++struct storvsc_driver_context { ++ // !! These must be the first 2 fields !! ++ struct driver_context drv_ctx; ++ STORVSC_DRIVER_OBJECT drv_obj; ++}; ++ ++// Static decl ++static int storvsc_probe(struct device *dev); ++static int storvsc_queuecommand(struct scsi_cmnd *scmnd, void (*done)(struct scsi_cmnd *)); ++static int storvsc_device_alloc(struct scsi_device *); ++static int storvsc_device_configure(struct scsi_device *); ++static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd); ++#ifdef KERNEL_2_6_27 ++static void storvsc_host_rescan_callback(struct work_struct *work); ++#else ++static void storvsc_host_rescan_callback(void* context); ++#endif ++static void storvsc_host_rescan(DEVICE_OBJECT* device_obj); ++static int storvsc_remove(struct device *dev); ++ ++static struct scatterlist *create_bounce_buffer(struct scatterlist *sgl, unsigned int sg_count, unsigned int len); ++static void destroy_bounce_buffer(struct scatterlist *sgl, unsigned int sg_count); ++static int do_bounce_buffer(struct scatterlist *sgl, unsigned int sg_count); ++static unsigned int copy_from_bounce_buffer(struct scatterlist *orig_sgl, struct scatterlist *bounce_sgl, unsigned int orig_sgl_count); ++static unsigned int copy_to_bounce_buffer(struct scatterlist *orig_sgl, struct scatterlist *bounce_sgl, unsigned int orig_sgl_count); ++ ++static int storvsc_report_luns(struct scsi_device *sdev, unsigned int luns[], unsigned int *lun_count); ++static int storvsc_get_chs(struct scsi_device *sdev, struct block_device * bdev, sector_t capacity, int *info); ++ ++ ++static int storvsc_ringbuffer_size = STORVSC_RING_BUFFER_SIZE; ++ ++// The one and only one ++static struct storvsc_driver_context g_storvsc_drv; ++ ++// Scsi driver ++static struct scsi_host_template scsi_driver = { ++ .module = THIS_MODULE, ++ .name = "storvsc_host_t", ++ .bios_param = storvsc_get_chs, ++ .queuecommand = storvsc_queuecommand, ++ .eh_host_reset_handler = storvsc_host_reset_handler, ++ .slave_alloc = storvsc_device_alloc, ++ .slave_configure = storvsc_device_configure, ++ .cmd_per_lun = 1, ++ .can_queue = STORVSC_MAX_IO_REQUESTS*STORVSC_MAX_TARGETS, // 64 max_queue * 1 target ++ .this_id = -1, ++ // no use setting to 0 since ll_blk_rw reset it to 1 ++ .sg_tablesize = MAX_MULTIPAGE_BUFFER_COUNT,// currently 32 ++ // ENABLE_CLUSTERING allows mutiple physically contig bio_vecs to merge into 1 sg element. If set, we must ++ // limit the max_segment_size to PAGE_SIZE, otherwise we may get 1 sg element that represents multiple ++ // physically contig pfns (ie sg[x].length > PAGE_SIZE). ++ .use_clustering = ENABLE_CLUSTERING, ++ // Make sure we dont get a sg segment crosses a page boundary ++ .dma_boundary = PAGE_SIZE-1, ++}; ++ ++ ++/*++ ++ ++Name: storvsc_drv_init() ++ ++Desc: StorVsc driver initialization. ++ ++--*/ ++int storvsc_drv_init(PFN_DRIVERINITIALIZE pfn_drv_init) ++{ ++ int ret=0; ++ STORVSC_DRIVER_OBJECT *storvsc_drv_obj=&g_storvsc_drv.drv_obj; ++ struct driver_context *drv_ctx=&g_storvsc_drv.drv_ctx; ++ ++ DPRINT_ENTER(STORVSC_DRV); ++ ++ vmbus_get_interface(&storvsc_drv_obj->Base.VmbusChannelInterface); ++ ++ storvsc_drv_obj->RingBufferSize = storvsc_ringbuffer_size; ++ storvsc_drv_obj->OnHostRescan = storvsc_host_rescan; ++ ++ // Callback to client driver to complete the initialization ++ pfn_drv_init(&storvsc_drv_obj->Base); ++ ++ DPRINT_INFO(STORVSC_DRV, "request extension size %u, max outstanding reqs %u", storvsc_drv_obj->RequestExtSize, storvsc_drv_obj->MaxOutstandingRequestsPerChannel); ++ ++ if (storvsc_drv_obj->MaxOutstandingRequestsPerChannel < STORVSC_MAX_IO_REQUESTS) ++ { ++ DPRINT_ERR(STORVSC_DRV, "The number of outstanding io requests (%d) is larger than that supported (%d) internally.", ++ STORVSC_MAX_IO_REQUESTS, storvsc_drv_obj->MaxOutstandingRequestsPerChannel); ++ return -1; ++ } ++ ++ drv_ctx->driver.name = storvsc_drv_obj->Base.name; ++ memcpy(&drv_ctx->class_id, &storvsc_drv_obj->Base.deviceType, sizeof(GUID)); ++ ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++ drv_ctx->driver.probe = storvsc_probe; ++ drv_ctx->driver.remove = storvsc_remove; ++#else ++ drv_ctx->probe = storvsc_probe; ++ drv_ctx->remove = storvsc_remove; ++#endif ++ ++ // The driver belongs to vmbus ++ vmbus_child_driver_register(drv_ctx); ++ ++ DPRINT_EXIT(STORVSC_DRV); ++ ++ return ret; ++} ++ ++ ++static int storvsc_drv_exit_cb(struct device *dev, void *data) ++{ ++ struct device **curr = (struct device **)data; ++ *curr = dev; ++ return 1; // stop iterating ++} ++ ++/*++ ++ ++Name: storvsc_drv_exit() ++ ++Desc: ++ ++--*/ ++void storvsc_drv_exit(void) ++{ ++ STORVSC_DRIVER_OBJECT *storvsc_drv_obj=&g_storvsc_drv.drv_obj; ++ struct driver_context *drv_ctx=&g_storvsc_drv.drv_ctx; ++ ++ struct device *current_dev=NULL; ++ ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++#define driver_for_each_device(drv, start, data, fn) \ ++ struct list_head *ptr, *n; \ ++ list_for_each_safe(ptr, n, &((drv)->devices)) {\ ++ struct device *curr_dev;\ ++ curr_dev = list_entry(ptr, struct device, driver_list);\ ++ fn(curr_dev, data);\ ++ } ++#endif // KERNEL_2_6_9 ++ ++ DPRINT_ENTER(STORVSC_DRV); ++ ++ while (1) ++ { ++ current_dev = NULL; ++ ++ // Get the device ++ driver_for_each_device(&drv_ctx->driver, NULL, (void*)¤t_dev, storvsc_drv_exit_cb); ++ ++ if (current_dev == NULL) ++ break; ++ ++ // Initiate removal from the top-down ++ device_unregister(current_dev); ++ } ++ ++ if (storvsc_drv_obj->Base.OnCleanup) ++ storvsc_drv_obj->Base.OnCleanup(&storvsc_drv_obj->Base); ++ ++ vmbus_child_driver_unregister(drv_ctx); ++ ++ DPRINT_EXIT(STORVSC_DRV); ++ ++ return; ++} ++ ++/*++ ++ ++Name: storvsc_probe() ++ ++Desc: Add a new device for this driver ++ ++--*/ ++static int storvsc_probe(struct device *device) ++{ ++ int ret=0; ++ ++ struct driver_context *driver_ctx = driver_to_driver_context(device->driver); ++ struct storvsc_driver_context *storvsc_drv_ctx = (struct storvsc_driver_context*)driver_ctx; ++ STORVSC_DRIVER_OBJECT* storvsc_drv_obj = &storvsc_drv_ctx->drv_obj; ++ ++ struct device_context *device_ctx = device_to_device_context(device); ++ DEVICE_OBJECT* device_obj = &device_ctx->device_obj; ++ ++ struct Scsi_Host *host; ++ struct host_device_context *host_device_ctx; ++ STORVSC_DEVICE_INFO device_info; ++ ++ DPRINT_ENTER(STORVSC_DRV); ++ ++ if (!storvsc_drv_obj->Base.OnDeviceAdd) ++ return -1; ++ ++ host = scsi_host_alloc(&scsi_driver, sizeof(struct host_device_context)); ++ if (!host) ++ { ++ DPRINT_ERR(STORVSC_DRV, "unable to allocate scsi host object"); ++ return -ENOMEM; ++ } ++ ++ dev_set_drvdata(device, host); ++ ++ host_device_ctx = (struct host_device_context*)host->hostdata; ++ memset(host_device_ctx, 0, sizeof(struct host_device_context)); ++ ++ host_device_ctx->port = host->host_no; ++ host_device_ctx->device_ctx = device_ctx; ++ ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++#elif defined(KERNEL_2_6_27) ++ INIT_WORK(&host_device_ctx->host_rescan_work, storvsc_host_rescan_callback); ++#else ++ INIT_WORK(&host_device_ctx->host_rescan_work, storvsc_host_rescan_callback, device_obj); ++#endif ++ ++#if defined(KERNEL_2_6_27) ++ host_device_ctx->request_pool = ++ kmem_cache_create ++ (dev_name(&device_ctx->device), ++ sizeof(struct storvsc_cmd_request) + storvsc_drv_obj->RequestExtSize, ++ 0, ++ SLAB_HWCACHE_ALIGN, NULL); ++#else ++ host_device_ctx->request_pool = ++ kmem_cache_create ++ (device_ctx->device.bus_id, ++ sizeof(struct storvsc_cmd_request) + storvsc_drv_obj->RequestExtSize, ++ 0, ++ SLAB_HWCACHE_ALIGN, NULL, NULL); ++#endif ++ ++ if (!host_device_ctx->request_pool) ++ { ++ scsi_host_put(host); ++ DPRINT_EXIT(STORVSC_DRV); ++ ++ return -ENOMEM; ++ } ++ ++ device_info.PortNumber = host->host_no; ++ // Call to the vsc driver to add the device ++ ret = storvsc_drv_obj->Base.OnDeviceAdd(device_obj, (void*)&device_info); ++ if (ret != 0) ++ { ++ DPRINT_ERR(STORVSC_DRV, "unable to add scsi vsc device"); ++ kmem_cache_destroy(host_device_ctx->request_pool); ++ scsi_host_put(host); ++ DPRINT_EXIT(STORVSC_DRV); ++ ++ return -1; ++ } ++ ++ //host_device_ctx->port = device_info.PortNumber; ++ host_device_ctx->path = device_info.PathId; ++ host_device_ctx->target = device_info.TargetId; ++ ++ host->max_lun = STORVSC_MAX_LUNS_PER_TARGET; // max # of devices per target ++ host->max_id = STORVSC_MAX_TARGETS; // max # of targets per channel ++ host->max_channel = STORVSC_MAX_CHANNELS -1; // max # of channels ++ ++ // Register the HBA and start the scsi bus scan ++ ret = scsi_add_host(host, device); ++ if (ret != 0) ++ { ++ DPRINT_ERR(STORVSC_DRV, "unable to add scsi host device"); ++ ++ storvsc_drv_obj->Base.OnDeviceRemove(device_obj); ++ ++ kmem_cache_destroy(host_device_ctx->request_pool); ++ scsi_host_put(host); ++ DPRINT_EXIT(STORVSC_DRV); ++ ++ return -1; ++ } ++ ++ scsi_scan_host(host); ++ ++ DPRINT_EXIT(STORVSC_DRV); ++ ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: storvsc_remove() ++ ++Desc: Callback when our device is removed ++ ++--*/ ++static int storvsc_remove(struct device *device) ++{ ++ int ret=0; ++ ++ struct driver_context *driver_ctx = driver_to_driver_context(device->driver); ++ struct storvsc_driver_context *storvsc_drv_ctx = (struct storvsc_driver_context*)driver_ctx; ++ STORVSC_DRIVER_OBJECT* storvsc_drv_obj = &storvsc_drv_ctx->drv_obj; ++ ++ struct device_context *device_ctx = device_to_device_context(device); ++ DEVICE_OBJECT* device_obj = &device_ctx->device_obj; ++ ++ struct Scsi_Host *host = dev_get_drvdata(device); ++ struct host_device_context *host_device_ctx=(struct host_device_context*)host->hostdata; ++ ++ ++ DPRINT_ENTER(STORVSC_DRV); ++ ++ if (!storvsc_drv_obj->Base.OnDeviceRemove) ++ { ++ DPRINT_EXIT(STORVSC_DRV); ++ return -1; ++ } ++ ++ // Call to the vsc driver to let it know that the device is being removed ++ ret = storvsc_drv_obj->Base.OnDeviceRemove(device_obj); ++ if (ret != 0) ++ { ++ // TODO: ++ DPRINT_ERR(STORVSC, "unable to remove vsc device (ret %d)", ret); ++ } ++ ++ if (host_device_ctx->request_pool) ++ { ++ kmem_cache_destroy(host_device_ctx->request_pool); ++ host_device_ctx->request_pool = NULL; ++ } ++ ++ DPRINT_INFO(STORVSC, "removing host adapter (%p)...", host); ++ scsi_remove_host(host); ++ ++ DPRINT_INFO(STORVSC, "releasing host adapter (%p)...", host); ++ scsi_host_put(host); ++ ++ DPRINT_EXIT(STORVSC_DRV); ++ ++ return ret; ++} ++ ++/*++ ++ ++Name: storvsc_commmand_completion() ++ ++Desc: Command completion processing ++ ++--*/ ++static void storvsc_commmand_completion(STORVSC_REQUEST* request) ++{ ++ struct storvsc_cmd_request *cmd_request = (struct storvsc_cmd_request*)request->Context; ++ struct scsi_cmnd *scmnd = cmd_request->cmd; ++ struct host_device_context *host_device_ctx = (struct host_device_context*)scmnd->device->host->hostdata; ++ void (*scsi_done_fn)(struct scsi_cmnd *); ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++#else ++ struct scsi_sense_hdr sense_hdr; ++#endif ++ ++ ASSERT(request == &cmd_request->request); ++ ASSERT((unsigned long)scmnd->host_scribble == (unsigned long)cmd_request); ++ ASSERT(scmnd); ++ ASSERT(scmnd->scsi_done); ++ ++ DPRINT_ENTER(STORVSC_DRV); ++ ++ if (cmd_request->bounce_sgl_count)// using bounce buffer ++ { ++ //printk("copy_from_bounce_buffer\n"); ++ ++ // FIXME: We can optimize on writes by just skipping this ++#ifdef KERNEL_2_6_27 ++ copy_from_bounce_buffer(scsi_sglist(scmnd), cmd_request->bounce_sgl, scsi_sg_count(scmnd)); ++#else ++ copy_from_bounce_buffer(scmnd->request_buffer, cmd_request->bounce_sgl, scmnd->use_sg); ++#endif ++ destroy_bounce_buffer(cmd_request->bounce_sgl, cmd_request->bounce_sgl_count); ++ } ++ ++ scmnd->result = request->Status; ++ ++ if (scmnd->result) ++ { ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++ DPRINT_INFO(STORVSC_DRV, "scsi result nonzero - %d", scmnd->result); ++#else ++ if (scsi_normalize_sense(scmnd->sense_buffer, request->SenseBufferSize, &sense_hdr)) ++ { ++ scsi_print_sense_hdr("storvsc", &sense_hdr); ++ } ++#endif ++ } ++ ++ ASSERT(request->BytesXfer <= request->DataBuffer.Length); ++#ifdef KERNEL_2_6_27 ++ scsi_set_resid(scmnd, request->DataBuffer.Length - request->BytesXfer); ++#else ++ scmnd->resid = request->DataBuffer.Length - request->BytesXfer; ++#endif ++ ++ scsi_done_fn = scmnd->scsi_done; ++ ++ scmnd->host_scribble = NULL; ++ scmnd->scsi_done = NULL; ++ ++ // !!DO NOT MODIFY the scmnd after this call ++ scsi_done_fn(scmnd); ++ ++ kmem_cache_free(host_device_ctx->request_pool, cmd_request); ++ ++ DPRINT_EXIT(STORVSC_DRV); ++} ++ ++static int do_bounce_buffer(struct scatterlist *sgl, unsigned int sg_count) ++{ ++ int i=0; ++ ++ // No need to check ++ if (sg_count < 2) ++ return -1; ++ ++ // We have at least 2 sg entries ++ for ( i=0; i> PAGE_SHIFT; ++ ++ bounce_sgl = kzalloc(num_pages * sizeof(struct scatterlist), GFP_ATOMIC); ++ if (!bounce_sgl) ++ { ++ return NULL; ++ } ++ ++ for(i=0; idevice->host->hostdata; ++ struct device_context *device_ctx=host_device_ctx->device_ctx; ++ struct driver_context *driver_ctx = driver_to_driver_context(device_ctx->device.driver); ++ struct storvsc_driver_context *storvsc_drv_ctx = (struct storvsc_driver_context*)driver_ctx; ++ STORVSC_DRIVER_OBJECT* storvsc_drv_obj = &storvsc_drv_ctx->drv_obj; ++ ++ STORVSC_REQUEST *request; ++ struct storvsc_cmd_request *cmd_request; ++ unsigned int request_size=0; ++ int i; ++ struct scatterlist *sgl; ++ ++ DPRINT_ENTER(STORVSC_DRV); ++ ++#ifdef KERNEL_2_6_27 ++ DPRINT_DBG(STORVSC_DRV, "scmnd %p dir %d, use_sg %d buf %p len %d queue depth %d tagged %d", ++ scmnd, ++ scmnd->sc_data_direction, ++ scsi_sg_count(scmnd), ++ scsi_sglist(scmnd), ++ scsi_bufflen(scmnd), ++ scmnd->device->queue_depth, ++ scmnd->device->tagged_supported); ++#else ++ DPRINT_DBG(STORVSC_DRV, "scmnd %p dir %d, use_sg %d buf %p len %d queue depth %d tagged %d", ++ scmnd, ++ scmnd->sc_data_direction, ++ scmnd->use_sg, ++ scmnd->request_buffer, ++ scmnd->request_bufflen, ++ scmnd->device->queue_depth, ++ scmnd->device->tagged_supported); ++#endif ++ ++ // If retrying, no need to prep the cmd ++ if (scmnd->host_scribble) ++ { ++ ASSERT(scmnd->scsi_done != NULL); ++ ++ cmd_request = (struct storvsc_cmd_request* )scmnd->host_scribble; ++ DPRINT_INFO(STORVSC_DRV, "retrying scmnd %p cmd_request %p", scmnd, cmd_request); ++ ++ goto retry_request; ++ } ++ ++ ASSERT(scmnd->scsi_done == NULL); ++ ASSERT(scmnd->host_scribble == NULL); ++ ++ scmnd->scsi_done = done; ++ ++ request_size = sizeof(struct storvsc_cmd_request); ++ ++ cmd_request = kmem_cache_alloc(host_device_ctx->request_pool, GFP_ATOMIC); ++ if (!cmd_request) ++ { ++ DPRINT_ERR(STORVSC_DRV, "scmnd (%p) - unable to allocate storvsc_cmd_request...marking queue busy", scmnd); ++ ++ scmnd->scsi_done = NULL; ++ return SCSI_MLQUEUE_DEVICE_BUSY; ++ } ++ ++ // Setup the cmd request ++ cmd_request->bounce_sgl_count = 0; ++ cmd_request->bounce_sgl = NULL; ++ cmd_request->cmd = scmnd; ++ ++ scmnd->host_scribble = (unsigned char*)cmd_request; ++ ++ request = &cmd_request->request; ++ ++ request->Extension = (void*)((unsigned long)cmd_request + request_size); ++ DPRINT_DBG(STORVSC_DRV, "req %p size %d ext %d", request, request_size, storvsc_drv_obj->RequestExtSize); ++ ++ // Build the SRB ++ switch(scmnd->sc_data_direction) ++ { ++ case DMA_TO_DEVICE: ++ request->Type = WRITE_TYPE; ++ break; ++ case DMA_FROM_DEVICE: ++ request->Type = READ_TYPE; ++ break; ++ default: ++ request->Type = UNKNOWN_TYPE; ++ break; ++ } ++ ++ request->OnIOCompletion = storvsc_commmand_completion; ++ request->Context = cmd_request;//scmnd; ++ ++ //request->PortId = scmnd->device->channel; ++ request->Host = host_device_ctx->port; ++ request->Bus = scmnd->device->channel; ++ request->TargetId = scmnd->device->id; ++ request->LunId = scmnd->device->lun; ++ ++ ASSERT(scmnd->cmd_len <= 16); ++ request->CdbLen = scmnd->cmd_len; ++ request->Cdb = scmnd->cmnd; ++ ++ request->SenseBuffer = scmnd->sense_buffer; ++ request->SenseBufferSize = SCSI_SENSE_BUFFERSIZE; ++ ++ ++#ifdef KERNEL_2_6_27 ++ request->DataBuffer.Length = scsi_bufflen(scmnd); ++ if (scsi_sg_count(scmnd)) ++#else ++ request->DataBuffer.Length = scmnd->request_bufflen; ++ if (scmnd->use_sg) ++#endif ++ { ++#ifdef KERNEL_2_6_27 ++ sgl = (struct scatterlist*)scsi_sglist(scmnd); ++#else ++ sgl = (struct scatterlist*)(scmnd->request_buffer); ++#endif ++ ++ // check if we need to bounce the sgl ++#ifdef KERNEL_2_6_27 ++ if (do_bounce_buffer(sgl, scsi_sg_count(scmnd)) != -1) ++#else ++ if (do_bounce_buffer(sgl, scmnd->use_sg) != -1) ++#endif ++ { ++ DPRINT_INFO(STORVSC_DRV, "need to bounce buffer for this scmnd %p", scmnd); ++#ifdef KERNEL_2_6_27 ++ cmd_request->bounce_sgl = create_bounce_buffer(sgl, scsi_sg_count(scmnd), scsi_bufflen(scmnd)); ++#else ++ cmd_request->bounce_sgl = create_bounce_buffer( ++ sgl, ++ scmnd->use_sg, scmnd->request_bufflen); ++#endif ++ if (!cmd_request->bounce_sgl) ++ { ++ DPRINT_ERR(STORVSC_DRV, "unable to create bounce buffer for this scmnd %p", scmnd); ++ ++ scmnd->scsi_done = NULL; ++ scmnd->host_scribble = NULL; ++ kmem_cache_free(host_device_ctx->request_pool, cmd_request); ++ ++ return SCSI_MLQUEUE_HOST_BUSY; ++ } ++ ++#ifdef KERNEL_2_6_27 ++ cmd_request->bounce_sgl_count = ALIGN_UP(scsi_bufflen(scmnd), PAGE_SIZE) >> PAGE_SHIFT; ++#else ++ cmd_request->bounce_sgl_count = ALIGN_UP(scmnd->request_bufflen, PAGE_SIZE) >> PAGE_SHIFT; ++#endif ++ ++ //printk("bouncing buffer allocated %p original buffer %p\n", bounce_sgl, sgl); ++ //printk("copy_to_bounce_buffer\n"); ++ // FIXME: We can optimize on reads by just skipping this ++#ifdef KERNEL_2_6_27 ++ copy_to_bounce_buffer(sgl, cmd_request->bounce_sgl, scsi_sg_count(scmnd)); ++#else ++ copy_to_bounce_buffer(sgl, cmd_request->bounce_sgl, scmnd->use_sg); ++#endif ++ ++ sgl = cmd_request->bounce_sgl; ++ } ++ ++ request->DataBuffer.Offset = sgl[0].offset; ++ ++#ifdef KERNEL_2_6_27 ++ for (i = 0; i < scsi_sg_count(scmnd); i++ ) ++#else ++ for (i = 0; i < scmnd->use_sg; i++ ) ++#endif ++ { ++ DPRINT_DBG(STORVSC_DRV, "sgl[%d] len %d offset %d \n", i, sgl[i].length, sgl[i].offset); ++#ifdef KERNEL_2_6_27 ++ request->DataBuffer.PfnArray[i] = page_to_pfn(sg_page((&sgl[i]))); ++#else ++ request->DataBuffer.PfnArray[i] = page_to_pfn(sgl[i].page); ++#endif ++ } ++ } ++ ++#ifdef KERNEL_2_6_27 ++ else if (scsi_sglist(scmnd)) ++ { ++ ASSERT(scsi_bufflen(scmnd) <= PAGE_SIZE); ++ request->DataBuffer.Offset = virt_to_phys(scsi_sglist(scmnd)) & (PAGE_SIZE-1); ++ request->DataBuffer.PfnArray[0] = virt_to_phys(scsi_sglist(scmnd)) >> PAGE_SHIFT; ++ } ++ else ++ { ++ ASSERT(scsi_bufflen(scmnd) == 0); ++ } ++#else ++ else if (scmnd->request_buffer) ++ { ++ ASSERT(scmnd->request_bufflen <= PAGE_SIZE); ++ request->DataBuffer.Offset = virt_to_phys(scmnd->request_buffer) & (PAGE_SIZE-1); ++ request->DataBuffer.PfnArray[0] = virt_to_phys(scmnd->request_buffer) >> PAGE_SHIFT; ++ } ++ else ++ { ++ ASSERT(scmnd->request_bufflen == 0); ++ } ++#endif ++ ++retry_request: ++ ++ // Invokes the vsc to start an IO ++ ret = storvsc_drv_obj->OnIORequest(&device_ctx->device_obj, &cmd_request->request); ++ if (ret == -1) // no more space ++ { ++ DPRINT_ERR(STORVSC_DRV, "scmnd (%p) - queue FULL...marking queue busy", scmnd); ++ ++ if (cmd_request->bounce_sgl_count) ++ { ++ // FIXME: We can optimize on writes by just skipping this ++#ifdef KERNEL_2_6_27 ++ copy_from_bounce_buffer(scsi_sglist(scmnd), cmd_request->bounce_sgl, scsi_sg_count(scmnd)); ++#else ++ copy_from_bounce_buffer( ++ scmnd->request_buffer, ++ cmd_request->bounce_sgl, ++ scmnd->use_sg); ++#endif ++ destroy_bounce_buffer(cmd_request->bounce_sgl, cmd_request->bounce_sgl_count); ++ } ++ ++ kmem_cache_free(host_device_ctx->request_pool, cmd_request); ++ ++ scmnd->scsi_done = NULL; ++ scmnd->host_scribble = NULL; ++ ++ ret = SCSI_MLQUEUE_DEVICE_BUSY; ++ } ++ ++ DPRINT_EXIT(STORVSC_DRV); ++ ++ return ret; ++} ++ ++#ifdef KERNEL_2_6_27 ++static int storvsc_merge_bvec(struct request_queue *q, struct bvec_merge_data *bmd, struct bio_vec *bvec) ++{ ++ return bvec->bv_len; //checking done by caller. ++} ++#else ++static int storvsc_merge_bvec(struct request_queue *q, struct bio *bio, struct bio_vec *bvec) ++{ ++ // Check if we are adding a new bvec ++ if (bio->bi_vcnt > 0) ++ { ++ //printk("storvsc_merge_bvec() - cnt %u offset %u len %u\n", bio->bi_vcnt, bvec->bv_offset, bvec->bv_len); ++ ++ struct bio_vec *prev = &bio->bi_io_vec[bio->bi_vcnt - 1]; ++ if (bvec == prev) ++ return bvec->bv_len; // success ++ ++ // Adding new bvec. Make sure the prev one is a complete page ++ if (prev->bv_len == PAGE_SIZE && prev->bv_offset == 0) ++ { ++ return bvec->bv_len; // success ++ } ++ else ++ { ++ // Dont reject if the new bvec starts off from the prev one since ++ // they will be merge into 1 bvec or blk_rq_map_sg() will merge them into 1 sg element ++ if ((bvec->bv_page == prev->bv_page) && ++ (bvec->bv_offset == prev->bv_offset + prev->bv_len)) ++ { ++ return bvec->bv_len; // success ++ } ++ else ++ { ++ DPRINT_INFO(STORVSC_DRV, "detected holes in bio request (%p) - cnt %u offset %u len %u", bio, bio->bi_vcnt, bvec->bv_offset, bvec->bv_len); ++ return 0; // dont add the bvec to this bio since we dont allow holes in the middle of a multi-pages bio ++ } ++ } ++ } ++ ++ return bvec->bv_len; // success ++ ++} ++ ++#endif ++ ++/*++ ++ ++Name: storvsc_device_configure() ++ ++Desc: Configure the specified scsi device ++ ++--*/ ++static int storvsc_device_alloc(struct scsi_device *sdevice) ++{ ++#ifdef KERNEL_2_6_5 ++#else ++ DPRINT_DBG(STORVSC_DRV, "sdev (%p) - setting device flag to %d", sdevice, BLIST_SPARSELUN); ++ // This enables luns to be located sparsely. Otherwise, we may not discovered them. ++ sdevice->sdev_bflags |= BLIST_SPARSELUN | BLIST_LARGELUN; ++#endif ++ return 0; ++} ++ ++static int storvsc_device_configure(struct scsi_device *sdevice) ++{ ++ DPRINT_INFO(STORVSC_DRV, "sdev (%p) - curr queue depth %d", sdevice, sdevice->queue_depth); ++ ++ DPRINT_INFO(STORVSC_DRV, "sdev (%p) - setting queue depth to %d", sdevice, STORVSC_MAX_IO_REQUESTS); ++ scsi_adjust_queue_depth(sdevice, MSG_SIMPLE_TAG, STORVSC_MAX_IO_REQUESTS); ++ ++ DPRINT_INFO(STORVSC_DRV, "sdev (%p) - setting max segment size to %d", sdevice, PAGE_SIZE); ++ blk_queue_max_segment_size(sdevice->request_queue, PAGE_SIZE); ++ ++ DPRINT_INFO(STORVSC_DRV, "sdev (%p) - adding merge bio vec routine", sdevice); ++ blk_queue_merge_bvec(sdevice->request_queue, storvsc_merge_bvec); ++ ++ blk_queue_bounce_limit(sdevice->request_queue, BLK_BOUNCE_ANY); ++ //sdevice->timeout = (2000 * HZ);//(75 * HZ); ++ ++ return 0; ++} ++ ++/*++ ++ ++Name: storvsc_host_reset_handler() ++ ++Desc: Reset the scsi HBA ++ ++--*/ ++static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd) ++{ ++ int ret=SUCCESS; ++ struct host_device_context *host_device_ctx = (struct host_device_context*)scmnd->device->host->hostdata; ++ struct device_context *device_ctx = host_device_ctx->device_ctx; ++ struct driver_context *driver_ctx = driver_to_driver_context(device_ctx->device.driver); ++ struct storvsc_driver_context *storvsc_drv_ctx = (struct storvsc_driver_context*)driver_ctx; ++ ++ STORVSC_DRIVER_OBJECT *storvsc_drv_obj = &storvsc_drv_ctx->drv_obj; ++ ++ DPRINT_ENTER(STORVSC_DRV); ++ ++ DPRINT_INFO(STORVSC_DRV, "sdev (%p) dev obj (%p) - host resetting...", scmnd->device, &device_ctx->device_obj); ++ ++ // Invokes the vsc to reset the host/bus ++ ASSERT(storvsc_drv_obj->OnHostReset); ++ ret = storvsc_drv_obj->OnHostReset(&device_ctx->device_obj); ++ if (ret != 0) ++ { ++ DPRINT_EXIT(STORVSC_DRV); ++ return ret; ++ } ++ ++ DPRINT_INFO(STORVSC_DRV, "sdev (%p) dev obj (%p) - host reseted", scmnd->device, &device_ctx->device_obj); ++ ++ DPRINT_EXIT(STORVSC_DRV); ++ ++ return ret; ++} ++ ++/*++ ++ ++Name: storvsc_host_rescan ++ ++Desc: Rescan the scsi HBA ++ ++--*/ ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++#else ++ ++#ifdef KERNEL_2_6_27 ++static void storvsc_host_rescan_callback(struct work_struct *work) ++{ ++ DEVICE_OBJECT* device_obj = ++ &((struct host_device_context*)work)->device_ctx->device_obj; ++#else ++static void storvsc_host_rescan_callback(void* context) ++{ ++ ++ DEVICE_OBJECT* device_obj = (DEVICE_OBJECT*)context; ++#endif ++ struct device_context* device_ctx = to_device_context(device_obj); ++ struct Scsi_Host *host = dev_get_drvdata(&device_ctx->device); ++ struct scsi_device *sdev; ++ struct host_device_context *host_device_ctx; ++ struct scsi_device **sdevs_remove_list; ++ unsigned int sdevs_count=0; ++ unsigned int found; ++ unsigned int i; ++ unsigned int lun_count=0; ++ unsigned int *lun_list; ++ ++ DPRINT_ENTER(STORVSC_DRV); ++ ++ host_device_ctx = (struct host_device_context*)host->hostdata; ++ lun_list = kzalloc(sizeof(unsigned int)*STORVSC_MAX_LUNS_PER_TARGET, GFP_ATOMIC); ++ if (!lun_list) ++ { ++ DPRINT_ERR(STORVSC_DRV, "unable to allocate lun list"); ++ return; ++ } ++ ++ sdevs_remove_list = kzalloc(sizeof(void*)*STORVSC_MAX_LUNS_PER_TARGET, GFP_ATOMIC); ++ if (!sdevs_remove_list) ++ { ++ kfree(lun_list); ++ DPRINT_ERR(STORVSC_DRV, "unable to allocate lun remove list"); ++ return; ++ } ++ ++ DPRINT_INFO(STORVSC_DRV, "rescanning host for new scsi devices...", device_obj, host_device_ctx->target, host_device_ctx->path); ++ ++ // Rescan for new device ++ scsi_scan_target(&host->shost_gendev, host_device_ctx->path, host_device_ctx->target, SCAN_WILD_CARD, 1); ++ ++ DPRINT_INFO(STORVSC_DRV, "rescanning host for removed scsi device..."); ++ ++ // Use the 1st device to send the report luns cmd ++ shost_for_each_device(sdev, host) ++ { ++ lun_count=STORVSC_MAX_LUNS_PER_TARGET; ++ storvsc_report_luns(sdev, lun_list, &lun_count); ++ ++ DPRINT_INFO(STORVSC_DRV, "report luns on scsi device (%p) found %u luns ", sdev, lun_count); ++ DPRINT_INFO(STORVSC_DRV, "existing luns on scsi device (%p) host (%d)", sdev, host->host_no); ++ ++ scsi_device_put(sdev); ++ break; ++ } ++ ++ for (i=0; ilun == lun_list[i]) ++ { ++ found = 1; ++ break; ++ } ++ } ++ if (!found) ++ { ++ DPRINT_INFO(STORVSC_DRV, "lun (%u) does not exists", sdev->lun); ++ sdevs_remove_list[sdevs_count++] = sdev; ++ } ++ } ++ ++ // Now remove the devices ++ for (i=0; i< sdevs_count; i++) ++ { ++ DPRINT_INFO(STORVSC_DRV, "removing scsi device (%p) lun (%u)...", ++ sdevs_remove_list[i], sdevs_remove_list[i]->lun); ++ ++ // make sure it is not removed from underneath us ++ if (!scsi_device_get(sdevs_remove_list[i])) ++ { ++ scsi_remove_device(sdevs_remove_list[i]); ++ scsi_device_put(sdevs_remove_list[i]); ++ } ++ } ++ ++ DPRINT_INFO(STORVSC_DRV, "rescan completed on dev obj (%p) target (%u) bus (%u)", device_obj, host_device_ctx->target, host_device_ctx->path); ++ ++ kfree(lun_list); ++ kfree(sdevs_remove_list); ++ ++ DPRINT_EXIT(STORVSC_DRV); ++} ++ ++static int storvsc_report_luns(struct scsi_device *sdev, unsigned int luns[], unsigned int *lun_count) ++{ ++ int i,j; ++ unsigned int lun=0; ++ unsigned int num_luns; ++ int result; ++ unsigned char *data; ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++#else ++ struct scsi_sense_hdr sshdr; ++#endif ++ unsigned char cmd[16]={0}; ++ unsigned int report_len = 8*(STORVSC_MAX_LUNS_PER_TARGET+1); // Add 1 to cover the report_lun header ++ unsigned long long *report_luns; ++ const unsigned int in_lun_count = *lun_count; ++ ++ *lun_count = 0; ++ ++ report_luns = kzalloc(report_len, GFP_ATOMIC); ++ if (!report_luns) ++ { ++ return -ENOMEM; ++ } ++ ++ cmd[0] = REPORT_LUNS; ++ ++ // cmd length ++ *(unsigned int*)&cmd[6] = cpu_to_be32(report_len); ++ ++ result = scsi_execute_req(sdev, cmd, DMA_FROM_DEVICE, (unsigned char*)report_luns, report_len, &sshdr, 30*HZ, 3); ++ if (result != 0) ++ { ++ kfree(report_luns); ++ return -EBUSY; ++ } ++ ++ // get the length from the first four bytes ++ report_len = be32_to_cpu(*(unsigned int*)&report_luns[0]); ++ ++ num_luns = (report_len / sizeof(unsigned long long)); ++ if (num_luns > in_lun_count) ++ { ++ kfree(report_luns); ++ return -EINVAL; ++ } ++ ++ *lun_count = num_luns; ++ ++ DPRINT_DBG(STORVSC_DRV, "report luns on scsi device (%p) found %u luns ", sdev, num_luns); ++ ++ // lun id starts at 1 ++ for (i=1; i< num_luns+1; i++) ++ { ++ lun = 0; ++ data = (unsigned char*)&report_luns[i]; ++ for (j = 0; j < sizeof(lun); j += 2) ++ { ++ lun = lun | (((data[j] << 8) | data[j + 1]) << (j * 8)); ++ } ++ ++ luns[i-1] = lun; ++ } ++ ++ kfree(report_luns); ++ return 0; ++} ++#endif // KERNEL_2_6_9 ++ ++static void storvsc_host_rescan(DEVICE_OBJECT* device_obj) ++{ ++ struct device_context* device_ctx = to_device_context(device_obj); ++ struct Scsi_Host *host = dev_get_drvdata(&device_ctx->device); ++ struct host_device_context *host_device_ctx; ++ ++ DPRINT_ENTER(STORVSC_DRV); ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++ DPRINT_ERR(STORVSC_DRV, "rescan not supported on 2.6.9 kernels!! You will need to reboot if you have added or removed the scsi lun device"); ++#else ++ ++ host_device_ctx = (struct host_device_context*)host->hostdata; ++ ++ DPRINT_INFO(STORVSC_DRV, "initiating rescan on dev obj (%p) target (%u) bus (%u)...", device_obj, host_device_ctx->target, host_device_ctx->path); ++ ++ // We need to queue this since the scanning may block and the caller may be in an intr context ++ //scsi_queue_work(host, &host_device_ctx->host_rescan_work); ++ schedule_work(&host_device_ctx->host_rescan_work); ++#endif // KERNEL_2_6_9 ++ DPRINT_EXIT(STORVSC_DRV); ++} ++ ++static int storvsc_get_chs(struct scsi_device *sdev, struct block_device * bdev, sector_t capacity, int *info) ++{ ++ sector_t total_sectors = capacity; ++ sector_t cylinder_times_heads=0; ++ sector_t temp=0; ++ ++ int sectors_per_track=0; ++ int heads=0; ++ int cylinders=0; ++ int rem=0; ++ ++ if (total_sectors > (65535 * 16 * 255)) { ++ total_sectors = (65535 * 16 * 255); ++ } ++ ++ if (total_sectors >= (65535 * 16 * 63)) { ++ sectors_per_track = 255; ++ heads = 16; ++ ++ cylinder_times_heads = total_sectors; ++ rem = sector_div(cylinder_times_heads, sectors_per_track); // sector_div stores the quotient in cylinder_times_heads ++ } ++ else ++ { ++ sectors_per_track = 17; ++ ++ cylinder_times_heads = total_sectors; ++ rem = sector_div(cylinder_times_heads, sectors_per_track); // sector_div stores the quotient in cylinder_times_heads ++ ++ temp = cylinder_times_heads + 1023; ++ rem = sector_div(temp, 1024); // sector_div stores the quotient in temp ++ ++ heads = temp; ++ ++ if (heads < 4) { ++ heads = 4; ++ } ++ ++ if (cylinder_times_heads >= (heads * 1024) || (heads > 16)) { ++ sectors_per_track = 31; ++ heads = 16; ++ ++ cylinder_times_heads = total_sectors; ++ rem = sector_div(cylinder_times_heads, sectors_per_track); // sector_div stores the quotient in cylinder_times_heads ++ } ++ ++ if (cylinder_times_heads >= (heads * 1024)) { ++ sectors_per_track = 63; ++ heads = 16; ++ ++ cylinder_times_heads = total_sectors; ++ rem = sector_div(cylinder_times_heads, sectors_per_track); // sector_div stores the quotient in cylinder_times_heads ++ } ++ } ++ ++ temp = cylinder_times_heads; ++ rem = sector_div(temp, heads); // sector_div stores the quotient in temp ++ cylinders = temp; ++ ++ info[0] = heads; ++ info[1] = sectors_per_track; ++ info[2] = cylinders; ++ ++ DPRINT_INFO(STORVSC_DRV, "CHS (%d, %d, %d)", cylinders, heads, sectors_per_track); ++ ++ return 0; ++} ++ ++MODULE_LICENSE("GPL"); ++ ++static int __init storvsc_init(void) ++{ ++ int ret; ++ ++ DPRINT_ENTER(STORVSC_DRV); ++ ++ DPRINT_INFO(STORVSC_DRV, "Storvsc initializing...."); ++ ++ ret = storvsc_drv_init(StorVscInitialize); ++ ++ DPRINT_EXIT(STORVSC_DRV); ++ ++ return ret; ++} ++ ++static void __exit storvsc_exit(void) ++{ ++ DPRINT_ENTER(STORVSC_DRV); ++ ++ storvsc_drv_exit(); ++ ++ DPRINT_ENTER(STORVSC_DRV); ++} ++ ++module_param(storvsc_ringbuffer_size, int, S_IRUGO); ++ ++module_init(storvsc_init); ++module_exit(storvsc_exit); ++ ++// eof +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/TODO linux-2.6.27.29-0.1.1/drivers/staging/hv/TODO +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/TODO 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,15 @@ ++TODO: ++ - fix checkpatch warnings/errors ++ - fix sparse issues ++ - remove compatibility layer ++ - fix HANDLE usage to be "real" pointers ++ - audit the vmbus to verify it is working properly with the ++ driver model ++ - see if the vmbus can be merged with the other virtual busses ++ in the kernel ++ - audit the network driver ++ - audit the block driver ++ - audit the scsi driver ++ ++Please send patches for this code to Greg Kroah-Hartman ++and Hank Janssen +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/VersionInfo.h linux-2.6.27.29-0.1.1/drivers/staging/hv/VersionInfo.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/VersionInfo.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,29 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#pragma once ++ ++const char VersionDate[]=__DATE__; ++const char VersionTime[]=__TIME__; ++const char VersionDesc[]= "Version 2.0"; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/Vmbus.c linux-2.6.27.29-0.1.1/drivers/staging/hv/Vmbus.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/Vmbus.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,508 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#include "include/logging.h" ++#include "VersionInfo.h" ++#include "VmbusPrivate.h" ++ ++// ++// Globals ++// ++static const char* gDriverName="vmbus"; ++ ++// Windows vmbus does not defined this. We defined this to be consistent with other devices ++//{c5295816-f63a-4d5f-8d1a-4daf999ca185} ++static const GUID gVmbusDeviceType={ ++ .Data = {0x16, 0x58, 0x29, 0xc5, 0x3a, 0xf6, 0x5f, 0x4d, 0x8d, 0x1a, 0x4d, 0xaf, 0x99, 0x9c, 0xa1, 0x85} ++}; ++ ++//{ac3760fc-9adf-40aa-9427-a70ed6de95c5} ++static const GUID gVmbusDeviceId={ ++ .Data = {0xfc, 0x60, 0x37, 0xac, 0xdf, 0x9a, 0xaa, 0x40, 0x94, 0x27, 0xa7, 0x0e, 0xd6, 0xde, 0x95, 0xc5} ++}; ++ ++static DRIVER_OBJECT* gDriver; // vmbus driver object ++static DEVICE_OBJECT* gDevice; // vmbus root device ++ ++ ++// ++// Internal routines ++// ++ ++static void ++VmbusGetChannelInterface( ++ VMBUS_CHANNEL_INTERFACE *Interface ++ ); ++ ++static void ++VmbusGetChannelInfo( ++ DEVICE_OBJECT *DeviceObject, ++ DEVICE_INFO *DeviceInfo ++ ); ++ ++static void ++VmbusGetChannelOffers( ++ void ++ ); ++ ++static int ++VmbusOnDeviceAdd( ++ DEVICE_OBJECT *Device, ++ void *AdditionalInfo ++ ); ++ ++static int ++VmbusOnDeviceRemove( ++ DEVICE_OBJECT* dev ++ ); ++ ++static void ++VmbusOnCleanup( ++ DRIVER_OBJECT* drv ++ ); ++ ++static int ++VmbusOnISR( ++ DRIVER_OBJECT* drv ++ ); ++ ++static void ++VmbusOnMsgDPC( ++ DRIVER_OBJECT* drv ++ ); ++ ++static void ++VmbusOnEventDPC( ++ DRIVER_OBJECT* drv ++ ); ++ ++/*++; ++ ++Name: ++ VmbusInitialize() ++ ++Description: ++ Main entry point ++ ++--*/ ++int ++VmbusInitialize( ++ DRIVER_OBJECT* drv ++ ) ++{ ++ VMBUS_DRIVER_OBJECT* driver = (VMBUS_DRIVER_OBJECT*)drv; ++ int ret=0; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ DPRINT_INFO(VMBUS, "+++++++ Build Date=%s %s +++++++", VersionDate, VersionTime); ++ DPRINT_INFO(VMBUS, "+++++++ Build Description=%s +++++++", VersionDesc); ++ ++ DPRINT_INFO(VMBUS, "+++++++ Vmbus supported version = %d +++++++", VMBUS_REVISION_NUMBER); ++ DPRINT_INFO(VMBUS, "+++++++ Vmbus using SINT %d +++++++", VMBUS_MESSAGE_SINT); ++ ++ DPRINT_DBG(VMBUS, "sizeof(VMBUS_CHANNEL_PACKET_PAGE_BUFFER)=%d, sizeof(VMBUS_CHANNEL_PACKET_MULITPAGE_BUFFER)=%d", ++ sizeof(VMBUS_CHANNEL_PACKET_PAGE_BUFFER), sizeof(VMBUS_CHANNEL_PACKET_MULITPAGE_BUFFER)); ++ ++ drv->name = gDriverName; ++ memcpy(&drv->deviceType, &gVmbusDeviceType, sizeof(GUID)); ++ ++ // Setup dispatch table ++ driver->Base.OnDeviceAdd = VmbusOnDeviceAdd; ++ driver->Base.OnDeviceRemove = VmbusOnDeviceRemove; ++ driver->Base.OnCleanup = VmbusOnCleanup; ++ driver->OnIsr = VmbusOnISR; ++ driver->OnMsgDpc = VmbusOnMsgDPC; ++ driver->OnEventDpc = VmbusOnEventDPC; ++ driver->GetChannelOffers = VmbusGetChannelOffers; ++ driver->GetChannelInterface = VmbusGetChannelInterface; ++ driver->GetChannelInfo = VmbusGetChannelInfo; ++ ++ // Hypervisor initialization...setup hypercall page..etc ++ ret = HvInit(); ++ if (ret != 0) ++ { ++ DPRINT_ERR(VMBUS, "Unable to initialize the hypervisor - 0x%x", ret); ++ } ++ ++ gDriver = drv; ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++} ++ ++ ++/*++; ++ ++Name: ++ VmbusGetChannelOffers() ++ ++Description: ++ Retrieve the channel offers from the parent partition ++ ++--*/ ++ ++static void ++VmbusGetChannelOffers(void) ++{ ++ DPRINT_ENTER(VMBUS); ++ VmbusChannelRequestOffers(); ++ DPRINT_EXIT(VMBUS); ++} ++ ++ ++/*++; ++ ++Name: ++ VmbusGetChannelInterface() ++ ++Description: ++ Get the channel interface ++ ++--*/ ++static void ++VmbusGetChannelInterface( ++ VMBUS_CHANNEL_INTERFACE *Interface ++ ) ++{ ++ GetChannelInterface(Interface); ++} ++ ++ ++/*++; ++ ++Name: ++ VmbusGetChannelInterface() ++ ++Description: ++ Get the device info for the specified device object ++ ++--*/ ++static void ++VmbusGetChannelInfo( ++ DEVICE_OBJECT *DeviceObject, ++ DEVICE_INFO *DeviceInfo ++ ) ++{ ++ GetChannelInfo(DeviceObject, DeviceInfo); ++} ++ ++ ++ ++/*++ ++ ++Name: ++ VmbusCreateChildDevice() ++ ++Description: ++ Creates the child device on the bus that represents the channel offer ++ ++--*/ ++ ++DEVICE_OBJECT* ++VmbusChildDeviceCreate( ++ GUID DeviceType, ++ GUID DeviceInstance, ++ void *Context) ++{ ++ VMBUS_DRIVER_OBJECT* vmbusDriver = (VMBUS_DRIVER_OBJECT*)gDriver; ++ ++ return vmbusDriver->OnChildDeviceCreate( ++ DeviceType, ++ DeviceInstance, ++ Context); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChildDeviceAdd() ++ ++Description: ++ Registers the child device with the vmbus ++ ++--*/ ++int ++VmbusChildDeviceAdd( ++ DEVICE_OBJECT* ChildDevice) ++{ ++ VMBUS_DRIVER_OBJECT* vmbusDriver = (VMBUS_DRIVER_OBJECT*)gDriver; ++ ++ return vmbusDriver->OnChildDeviceAdd(gDevice, ChildDevice); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusChildDeviceRemove() ++ ++Description: ++ Unregisters the child device from the vmbus ++ ++--*/ ++void ++VmbusChildDeviceRemove( ++ DEVICE_OBJECT* ChildDevice) ++{ ++ VMBUS_DRIVER_OBJECT* vmbusDriver = (VMBUS_DRIVER_OBJECT*)gDriver; ++ ++ vmbusDriver->OnChildDeviceRemove(ChildDevice); ++} ++ ++/*++ ++ ++Name: ++ VmbusChildDeviceDestroy() ++ ++Description: ++ Release the child device from the vmbus ++ ++--*/ ++//void ++//VmbusChildDeviceDestroy( ++// DEVICE_OBJECT* ChildDevice ++// ) ++//{ ++// VMBUS_DRIVER_OBJECT* vmbusDriver = (VMBUS_DRIVER_OBJECT*)gDriver; ++// ++// vmbusDriver->OnChildDeviceDestroy(ChildDevice); ++//} ++ ++/*++ ++ ++Name: ++ VmbusOnDeviceAdd() ++ ++Description: ++ Callback when the root bus device is added ++ ++--*/ ++static int ++VmbusOnDeviceAdd( ++ DEVICE_OBJECT *dev, ++ void *AdditionalInfo ++ ) ++{ ++ UINT32 *irqvector = (UINT32*) AdditionalInfo; ++ int ret=0; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ gDevice = dev; ++ ++ memcpy(&gDevice->deviceType, &gVmbusDeviceType, sizeof(GUID)); ++ memcpy(&gDevice->deviceInstance, &gVmbusDeviceId, sizeof(GUID)); ++ ++ //strcpy(dev->name, "vmbus"); ++ // SynIC setup... ++ ret = HvSynicInit(*irqvector); ++ ++ // Connect to VMBus in the root partition ++ ret = VmbusConnect(); ++ ++ //VmbusSendEvent(device->localPortId+1); ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusOnDeviceRemove() ++ ++Description: ++ Callback when the root bus device is removed ++ ++--*/ ++int VmbusOnDeviceRemove( ++ DEVICE_OBJECT* dev ++ ) ++{ ++ int ret=0; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ VmbusChannelReleaseUnattachedChannels(); ++ ++ VmbusDisconnect(); ++ ++ HvSynicCleanup(); ++ ++ DPRINT_EXIT(VMBUS); ++ ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusOnCleanup() ++ ++Description: ++ Perform any cleanup when the driver is removed ++ ++--*/ ++void ++VmbusOnCleanup( ++ DRIVER_OBJECT* drv ++ ) ++{ ++ //VMBUS_DRIVER_OBJECT* driver = (VMBUS_DRIVER_OBJECT*)drv; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ HvCleanup(); ++ ++ DPRINT_EXIT(VMBUS); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusOnMsgDPC() ++ ++Description: ++ DPC routine to handle messages from the hypervisior ++ ++--*/ ++void ++VmbusOnMsgDPC( ++ DRIVER_OBJECT* drv ++ ) ++{ ++ void *page_addr = gHvContext.synICMessagePage[0]; ++ ++ HV_MESSAGE* msg = (HV_MESSAGE*)page_addr + VMBUS_MESSAGE_SINT; ++ HV_MESSAGE *copied; ++ while (1) ++ { ++ if (msg->Header.MessageType == HvMessageTypeNone) // no msg ++ { ++ break; ++ } ++ else ++ { ++ copied = MemAllocAtomic(sizeof(HV_MESSAGE)); ++ if (copied == NULL) ++ { ++ continue; ++ } ++ ++ memcpy(copied, msg, sizeof(HV_MESSAGE)); ++ WorkQueueQueueWorkItem(gVmbusConnection.WorkQueue, VmbusOnChannelMessage, (void*)copied); ++ } ++ ++ msg->Header.MessageType = HvMessageTypeNone; ++ ++ // Make sure the write to MessageType (ie set to HvMessageTypeNone) happens ++ // before we read the MessagePending and EOMing. Otherwise, the EOMing will not deliver ++ // any more messages since there is no empty slot ++ MemoryFence(); ++ ++ if (msg->Header.MessageFlags.MessagePending) ++ { ++ // This will cause message queue rescan to possibly deliver another msg from the hypervisor ++ WriteMsr(HV_X64_MSR_EOM, 0); ++ } ++ } ++} ++ ++/*++ ++ ++Name: ++ VmbusOnEventDPC() ++ ++Description: ++ DPC routine to handle events from the hypervisior ++ ++--*/ ++void ++VmbusOnEventDPC( ++ DRIVER_OBJECT* drv ++ ) ++{ ++ // TODO: Process any events ++ VmbusOnEvents(); ++} ++ ++ ++/*++ ++ ++Name: ++ VmbusOnISR() ++ ++Description: ++ ISR routine ++ ++--*/ ++int ++VmbusOnISR( ++ DRIVER_OBJECT* drv ++ ) ++{ ++ //VMBUS_DRIVER_OBJECT* driver = (VMBUS_DRIVER_OBJECT*)drv; ++ ++ int ret=0; ++ //struct page* page; ++ void *page_addr; ++ HV_MESSAGE* msg; ++ HV_SYNIC_EVENT_FLAGS* event; ++ ++ //page = SynICMessagePage[0]; ++ //page_addr = page_address(page); ++ page_addr = gHvContext.synICMessagePage[0]; ++ msg = (HV_MESSAGE*)page_addr + VMBUS_MESSAGE_SINT; ++ ++ DPRINT_ENTER(VMBUS); ++ ++ // Check if there are actual msgs to be process ++ if (msg->Header.MessageType != HvMessageTypeNone) ++ { ++ DPRINT_DBG(VMBUS, "received msg type %d size %d", msg->Header.MessageType, msg->Header.PayloadSize); ++ ret |= 0x1; ++ } ++ ++ // TODO: Check if there are events to be process ++ page_addr = gHvContext.synICEventPage[0]; ++ event = (HV_SYNIC_EVENT_FLAGS*)page_addr + VMBUS_MESSAGE_SINT; ++ ++ // Since we are a child, we only need to check bit 0 ++ if (BitTestAndClear(&event->Flags32[0], 0)) ++ { ++ DPRINT_DBG(VMBUS, "received event %d", event->Flags32[0]); ++ ret |= 0x2; ++ } ++ ++ DPRINT_EXIT(VMBUS); ++ return ret; ++} ++ ++// eof +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/vmbus_drv.c linux-2.6.27.29-0.1.1/drivers/staging/hv/vmbus_drv.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/vmbus_drv.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,1229 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++#define KERNEL_2_6_27 ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "include/logging.h" ++#include "include/vmbus.h" ++ ++// ++// Defines ++// ++ ++// FIXME! We need to do this dynamically for PIC and APIC system ++#define VMBUS_IRQ 0x5 ++#ifdef KERNEL_2_6_27 ++#define VMBUS_IRQ_VECTOR IRQ5_VECTOR ++#endif ++// ++// Data types ++// ++ ++// Main vmbus driver data structure ++struct vmbus_driver_context { ++ // !! These must be the first 2 fields !! ++ // The driver field is not used in here. Instead, the bus field is ++ // used to represent the driver ++ struct driver_context drv_ctx; ++ VMBUS_DRIVER_OBJECT drv_obj; ++ ++ struct bus_type bus; ++ struct tasklet_struct msg_dpc; ++ struct tasklet_struct event_dpc; ++ ++ // The bus root device ++ struct device_context device_ctx; ++}; ++ ++// ++// Static decl ++// ++static int vmbus_match(struct device *device, struct device_driver *driver); ++static int vmbus_probe(struct device *device); ++static int vmbus_remove(struct device *device); ++static void vmbus_shutdown(struct device *device); ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++#elif defined(KERNEL_2_6_27) ++static int vmbus_uevent(struct device *device, struct kobj_uevent_env *env); ++#else ++static int vmbus_uevent(struct device *device, char **envp, int num_envp, char *buffer, int buffer_size); ++#endif ++static void vmbus_msg_dpc(unsigned long data); ++static void vmbus_event_dpc(unsigned long data); ++ ++#ifdef KERNEL_2_6_27 ++static irqreturn_t vmbus_isr(int irq, void* dev_id); ++#else ++static int vmbus_isr(int irq, void* dev_id, struct pt_regs *regs); ++#endif ++ ++static void vmbus_device_release(struct device *device); ++static void vmbus_bus_release(struct device *device); ++ ++static DEVICE_OBJECT* vmbus_child_device_create(GUID type, GUID instance, void* context); ++static void vmbus_child_device_destroy(DEVICE_OBJECT* device_obj); ++static int vmbus_child_device_register(DEVICE_OBJECT* root_device_obj, DEVICE_OBJECT* child_device_obj); ++static void vmbus_child_device_unregister(DEVICE_OBJECT* child_device_obj); ++static void vmbus_child_device_get_info(DEVICE_OBJECT *device_obj, DEVICE_INFO *device_info); ++ ++//static ssize_t vmbus_show_class_id(struct device *dev, struct device_attribute *attr, char *buf); ++//static ssize_t vmbus_show_device_id(struct device *dev, struct device_attribute *attr, char *buf); ++ ++static ssize_t vmbus_show_device_attr(struct device *dev, struct device_attribute *dev_attr, char *buf); ++ ++// ++// Global ++// ++ ++// Global logging setting ++ ++//unsigned int vmbus_loglevel= (((VMBUS | VMBUS_DRV)<<16) | DEBUG_LVL_ENTEREXIT); ++//unsigned int vmbus_loglevel= (ALL_MODULES << 16 | DEBUG_LVL_ENTEREXIT); ++unsigned int vmbus_loglevel= (ALL_MODULES << 16 | INFO_LVL); ++EXPORT_SYMBOL(vmbus_loglevel); ++ ++static int vmbus_irq = VMBUS_IRQ; ++ ++// Setup /proc/sys/bus/vmbus/vmbus_loglevel ++// Allow usage of sysctl cmd to set the logging level ++static struct ctl_table_header *vmbus_ctl_table_hdr; ++ ++static ctl_table vmbus_dev_ctl_table[] = { ++ { .ctl_name = 8461, ++ .procname = "vmbus_loglevel", ++ .data = &vmbus_loglevel, ++ .maxlen = sizeof(vmbus_loglevel), ++ .mode = 0644, ++ .proc_handler = &proc_dointvec }, ++ { } ++}; ++ ++static ctl_table vmbus_ctl_table[] = { ++ { .ctl_name = CTL_DEV, ++ .procname = "vmbus", ++ .mode = 0555, ++ .child = vmbus_dev_ctl_table }, ++ { } ++}; ++ ++static ctl_table vmus_root_ctl_table[] = { ++ { .ctl_name = CTL_BUS, ++ .procname = "bus", ++ .mode = 0555, ++ .child = vmbus_ctl_table }, ++ { } ++}; ++ ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++#else ++// ++// Set up per device attributes in /sys/bus/vmbus/devices/ ++// ++static struct device_attribute vmbus_device_attrs[] = { ++ __ATTR(id, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(state, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(class_id, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(device_id, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(monitor_id, S_IRUGO, vmbus_show_device_attr, NULL), ++ ++ __ATTR(server_monitor_pending, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(server_monitor_latency, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(server_monitor_conn_id, S_IRUGO, vmbus_show_device_attr, NULL), ++ ++ __ATTR(client_monitor_pending, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(client_monitor_latency, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(client_monitor_conn_id, S_IRUGO, vmbus_show_device_attr, NULL), ++ ++ __ATTR(out_intr_mask, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(out_read_index, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(out_write_index, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(out_read_bytes_avail, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(out_write_bytes_avail, S_IRUGO, vmbus_show_device_attr, NULL), ++ ++ __ATTR(in_intr_mask, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(in_read_index, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(in_write_index, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(in_read_bytes_avail, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR(in_write_bytes_avail, S_IRUGO, vmbus_show_device_attr, NULL), ++ __ATTR_NULL ++}; ++#endif ++ ++// The one and only one ++static struct vmbus_driver_context g_vmbus_drv={ ++ .bus.name = "vmbus", ++ .bus.match = vmbus_match, ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++#else ++ .bus.shutdown = vmbus_shutdown, ++ .bus.remove = vmbus_remove, ++ .bus.probe = vmbus_probe, ++ .bus.uevent = vmbus_uevent, ++ .bus.dev_attrs = vmbus_device_attrs, ++#endif ++}; ++ ++// ++// Routines ++// ++ ++ ++/*++ ++ ++Name: vmbus_show_device_attr() ++ ++Desc: Show the device attribute in sysfs. This is invoked when user does a "cat /sys/bus/vmbus/devices//" ++ ++--*/ ++static ssize_t vmbus_show_device_attr(struct device *dev, struct device_attribute *dev_attr, char *buf) ++{ ++ struct device_context *device_ctx = device_to_device_context(dev); ++ DEVICE_INFO device_info; ++ ++ memset(&device_info, 0, sizeof(DEVICE_INFO)); ++ ++ vmbus_child_device_get_info(&device_ctx->device_obj, &device_info); ++ ++ if (!strcmp(dev_attr->attr.name, "class_id")) ++ { ++ return sprintf(buf, "{%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}\n", ++ device_info.ChannelType.Data[3], device_info.ChannelType.Data[2], device_info.ChannelType.Data[1], device_info.ChannelType.Data[0], ++ device_info.ChannelType.Data[5], device_info.ChannelType.Data[4], ++ device_info.ChannelType.Data[7], device_info.ChannelType.Data[6], ++ device_info.ChannelType.Data[8], device_info.ChannelType.Data[9], device_info.ChannelType.Data[10], device_info.ChannelType.Data[11], device_info.ChannelType.Data[12], device_info.ChannelType.Data[13], device_info.ChannelType.Data[14], device_info.ChannelType.Data[15]); ++ ++ } ++ else if (!strcmp(dev_attr->attr.name, "device_id")) ++ { ++ return sprintf(buf, "{%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}\n", ++ device_info.ChannelInstance.Data[3], device_info.ChannelInstance.Data[2], device_info.ChannelInstance.Data[1], device_info.ChannelInstance.Data[0], ++ device_info.ChannelInstance.Data[5], device_info.ChannelInstance.Data[4], ++ device_info.ChannelInstance.Data[7], device_info.ChannelInstance.Data[6], ++ device_info.ChannelInstance.Data[8], device_info.ChannelInstance.Data[9], device_info.ChannelInstance.Data[10], device_info.ChannelInstance.Data[11], device_info.ChannelInstance.Data[12], device_info.ChannelInstance.Data[13], device_info.ChannelInstance.Data[14], device_info.ChannelInstance.Data[15]); ++ } ++ else if (!strcmp(dev_attr->attr.name, "state")) ++ { ++ return sprintf(buf, "%d\n", device_info.ChannelState); ++ } ++ else if (!strcmp(dev_attr->attr.name, "id")) ++ { ++ return sprintf(buf, "%d\n", device_info.ChannelId); ++ } ++ else if (!strcmp(dev_attr->attr.name, "out_intr_mask")) ++ { ++ return sprintf(buf, "%d\n", device_info.Outbound.InterruptMask); ++ } ++ else if (!strcmp(dev_attr->attr.name, "out_read_index")) ++ { ++ return sprintf(buf, "%d\n", device_info.Outbound.ReadIndex); ++ } ++ else if (!strcmp(dev_attr->attr.name, "out_write_index")) ++ { ++ return sprintf(buf, "%d\n", device_info.Outbound.WriteIndex); ++ } ++ else if (!strcmp(dev_attr->attr.name, "out_read_bytes_avail")) ++ { ++ return sprintf(buf, "%d\n", device_info.Outbound.BytesAvailToRead); ++ } ++ else if (!strcmp(dev_attr->attr.name, "out_write_bytes_avail")) ++ { ++ return sprintf(buf, "%d\n", device_info.Outbound.BytesAvailToWrite); ++ } ++ else if (!strcmp(dev_attr->attr.name, "in_intr_mask")) ++ { ++ return sprintf(buf, "%d\n", device_info.Inbound.InterruptMask); ++ } ++ else if (!strcmp(dev_attr->attr.name, "in_read_index")) ++ { ++ return sprintf(buf, "%d\n", device_info.Inbound.ReadIndex); ++ } ++ else if (!strcmp(dev_attr->attr.name, "in_write_index")) ++ { ++ return sprintf(buf, "%d\n", device_info.Inbound.WriteIndex); ++ } ++ else if (!strcmp(dev_attr->attr.name, "in_read_bytes_avail")) ++ { ++ return sprintf(buf, "%d\n", device_info.Inbound.BytesAvailToRead); ++ } ++ else if (!strcmp(dev_attr->attr.name, "in_write_bytes_avail")) ++ { ++ return sprintf(buf, "%d\n", device_info.Inbound.BytesAvailToWrite); ++ } ++ else if (!strcmp(dev_attr->attr.name, "monitor_id")) ++ { ++ return sprintf(buf, "%d\n", device_info.MonitorId); ++ } ++ else if (!strcmp(dev_attr->attr.name, "server_monitor_pending")) ++ { ++ return sprintf(buf, "%d\n", device_info.ServerMonitorPending); ++ } ++ else if (!strcmp(dev_attr->attr.name, "server_monitor_latency")) ++ { ++ return sprintf(buf, "%d\n", device_info.ServerMonitorLatency); ++ } ++ else if (!strcmp(dev_attr->attr.name, "server_monitor_conn_id")) ++ { ++ return sprintf(buf, "%d\n", device_info.ServerMonitorConnectionId); ++ } ++ else if (!strcmp(dev_attr->attr.name, "client_monitor_pending")) ++ { ++ return sprintf(buf, "%d\n", device_info.ClientMonitorPending); ++ } ++ else if (!strcmp(dev_attr->attr.name, "client_monitor_latency")) ++ { ++ return sprintf(buf, "%d\n", device_info.ClientMonitorLatency); ++ } ++ else if (!strcmp(dev_attr->attr.name, "client_monitor_conn_id")) ++ { ++ return sprintf(buf, "%d\n", device_info.ClientMonitorConnectionId); ++ } ++ else ++ { ++ return 0; ++ } ++} ++ ++/*++ ++ ++Name: vmbus_show_class_id() ++ ++Desc: Show the device class id in sysfs ++ ++--*/ ++//static ssize_t vmbus_show_class_id(struct device *dev, struct device_attribute *attr, char *buf) ++//{ ++// struct device_context *device_ctx = device_to_device_context(dev); ++// return sprintf(buf, "{%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}\n", ++// device_ctx->class_id[3], device_ctx->class_id[2], device_ctx->class_id[1], device_ctx->class_id[0], ++// device_ctx->class_id[5], device_ctx->class_id[4], ++// device_ctx->class_id[7], device_ctx->class_id[6], ++// device_ctx->class_id[8], device_ctx->class_id[9], device_ctx->class_id[10], device_ctx->class_id[11], device_ctx->class_id[12], device_ctx->class_id[13], device_ctx->class_id[14], device_ctx->class_id[15]); ++//} ++ ++/*++ ++ ++Name: vmbus_show_device_id() ++ ++Desc: Show the device instance id in sysfs ++ ++--*/ ++//static ssize_t vmbus_show_device_id(struct device *dev, struct device_attribute *attr, char *buf) ++//{ ++// struct device_context *device_ctx = device_to_device_context(dev); ++// return sprintf(buf, "{%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}\n", ++// device_ctx->device_id[3], device_ctx->device_id[2], device_ctx->device_id[1], device_ctx->device_id[0], ++// device_ctx->device_id[5], device_ctx->device_id[4], ++// device_ctx->device_id[7], device_ctx->device_id[6], ++// device_ctx->device_id[8], device_ctx->device_id[9], device_ctx->device_id[10], device_ctx->device_id[11], device_ctx->device_id[12], device_ctx->device_id[13], device_ctx->device_id[14], device_ctx->device_id[15]); ++//} ++ ++/*++ ++ ++Name: vmbus_bus_init() ++ ++Desc: Main vmbus driver initialization routine. Here, we ++ - initialize the vmbus driver context ++ - setup various driver entry points ++ - invoke the vmbus hv main init routine ++ - get the irq resource ++ - invoke the vmbus to add the vmbus root device ++ - setup the vmbus root device ++ - retrieve the channel offers ++--*/ ++int vmbus_bus_init(PFN_DRIVERINITIALIZE pfn_drv_init) ++{ ++ int ret=0; ++ unsigned int vector=0; ++ ++ struct vmbus_driver_context *vmbus_drv_ctx=&g_vmbus_drv; ++ VMBUS_DRIVER_OBJECT *vmbus_drv_obj=&g_vmbus_drv.drv_obj; ++ ++ struct device_context *dev_ctx=&g_vmbus_drv.device_ctx; ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ // Set this up to allow lower layer to callback to add/remove child devices on the bus ++ vmbus_drv_obj->OnChildDeviceCreate = vmbus_child_device_create; ++ vmbus_drv_obj->OnChildDeviceDestroy = vmbus_child_device_destroy; ++ vmbus_drv_obj->OnChildDeviceAdd = vmbus_child_device_register; ++ vmbus_drv_obj->OnChildDeviceRemove = vmbus_child_device_unregister; ++ ++ // Call to bus driver to initialize ++ ret = pfn_drv_init(&vmbus_drv_obj->Base); ++ if (ret != 0) ++ { ++ DPRINT_ERR(VMBUS_DRV, "Unable to initialize vmbus (%d)", ret); ++ goto cleanup; ++ } ++ ++ // Sanity checks ++ if (!vmbus_drv_obj->Base.OnDeviceAdd) ++ { ++ DPRINT_ERR(VMBUS_DRV, "OnDeviceAdd() routine not set"); ++ ret = -1; ++ goto cleanup; ++ } ++ ++ vmbus_drv_ctx->bus.name = vmbus_drv_obj->Base.name; ++ ++ // Initialize the bus context ++ tasklet_init(&vmbus_drv_ctx->msg_dpc, vmbus_msg_dpc, (unsigned long)vmbus_drv_obj); ++ tasklet_init(&vmbus_drv_ctx->event_dpc, vmbus_event_dpc, (unsigned long)vmbus_drv_obj); ++ ++ // Now, register the bus driver with LDM ++ bus_register(&vmbus_drv_ctx->bus); ++ ++ // Get the interrupt resource ++#ifdef KERNEL_2_6_27 ++ ret = request_irq(vmbus_irq, ++ vmbus_isr, ++ IRQF_SAMPLE_RANDOM, ++ vmbus_drv_obj->Base.name, ++ NULL); ++#else ++ ret = request_irq(vmbus_irq, ++ vmbus_isr, ++ SA_SAMPLE_RANDOM, ++ vmbus_drv_obj->Base.name, ++ NULL); ++#endif ++ ++ if (ret != 0) ++ { ++ DPRINT_ERR(VMBUS_DRV, "ERROR - Unable to request IRQ %d", vmbus_irq); ++ ++ bus_unregister(&vmbus_drv_ctx->bus); ++ ++ ret = -1; ++ goto cleanup; ++ } ++#ifdef KERNEL_2_6_27 ++ vector = VMBUS_IRQ_VECTOR; ++#else ++#if X2V_LINUX ++ vector = vmbus_irq + FIRST_DEVICE_VECTOR - 2; ++#else ++ vector = vmbus_irq + FIRST_EXTERNAL_VECTOR; ++#endif ++#endif ++ ++ DPRINT_INFO(VMBUS_DRV, "irq 0x%x vector 0x%x", vmbus_irq, vector); ++ ++ // Call to bus driver to add the root device ++ memset(dev_ctx, 0, sizeof(struct device_context)); ++ ++ ret = vmbus_drv_obj->Base.OnDeviceAdd(&dev_ctx->device_obj, &vector); ++ if (ret != 0) ++ { ++ DPRINT_ERR(VMBUS_DRV, "ERROR - Unable to add vmbus root device"); ++ ++ free_irq(vmbus_irq, NULL); ++ ++ bus_unregister(&vmbus_drv_ctx->bus); ++ ++ ret = -1; ++ goto cleanup; ++ } ++ //strcpy(dev_ctx->device.bus_id, dev_ctx->device_obj.name); ++ dev_set_name(&dev_ctx->device, "vmbus_0_0"); ++ memcpy(&dev_ctx->class_id, &dev_ctx->device_obj.deviceType, sizeof(GUID)); ++ memcpy(&dev_ctx->device_id, &dev_ctx->device_obj.deviceInstance, sizeof(GUID)); ++ ++ // No need to bind a driver to the root device. ++ dev_ctx->device.parent = NULL; ++ dev_ctx->device.bus = &vmbus_drv_ctx->bus; //NULL; // vmbus_remove() does not get invoked ++ ++ // Setup the device dispatch table ++ dev_ctx->device.release = vmbus_bus_release; ++ ++ // Setup the bus as root device ++ device_register(&dev_ctx->device); ++ ++ vmbus_drv_obj->GetChannelOffers(); ++ ++cleanup: ++ DPRINT_EXIT(VMBUS_DRV); ++ ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: vmbus_bus_exit() ++ ++Desc: Terminate the vmbus driver. This routine is opposite of vmbus_bus_init() ++ ++--*/ ++void vmbus_bus_exit(void) ++{ ++ VMBUS_DRIVER_OBJECT *vmbus_drv_obj=&g_vmbus_drv.drv_obj; ++ struct vmbus_driver_context *vmbus_drv_ctx=&g_vmbus_drv; ++ ++ struct device_context *dev_ctx=&g_vmbus_drv.device_ctx; ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ // Remove the root device ++ if (vmbus_drv_obj->Base.OnDeviceRemove) ++ vmbus_drv_obj->Base.OnDeviceRemove(&dev_ctx->device_obj); ++ ++ if (vmbus_drv_obj->Base.OnCleanup) ++ vmbus_drv_obj->Base.OnCleanup(&vmbus_drv_obj->Base); ++ ++ // Unregister the root bus device ++ device_unregister(&dev_ctx->device); ++ ++ bus_unregister(&vmbus_drv_ctx->bus); ++ ++ free_irq(vmbus_irq, NULL); ++ ++ tasklet_kill(&vmbus_drv_ctx->msg_dpc); ++ tasklet_kill(&vmbus_drv_ctx->event_dpc); ++ ++ DPRINT_EXIT(VMBUS_DRV); ++ ++ return; ++} ++ ++/*++ ++ ++Name: vmbus_child_driver_register() ++ ++Desc: Register a vmbus's child driver ++ ++--*/ ++void vmbus_child_driver_register(struct driver_context* driver_ctx) ++{ ++ VMBUS_DRIVER_OBJECT *vmbus_drv_obj=&g_vmbus_drv.drv_obj; ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ DPRINT_INFO(VMBUS_DRV, "child driver (%p) registering - name %s", driver_ctx, driver_ctx->driver.name); ++ ++ // The child driver on this vmbus ++ driver_ctx->driver.bus = &g_vmbus_drv.bus; ++ ++ driver_register(&driver_ctx->driver); ++ ++ vmbus_drv_obj->GetChannelOffers(); ++ ++ DPRINT_EXIT(VMBUS_DRV); ++} ++ ++EXPORT_SYMBOL(vmbus_child_driver_register); ++ ++/*++ ++ ++Name: vmbus_child_driver_unregister() ++ ++Desc: Unregister a vmbus's child driver ++ ++--*/ ++void vmbus_child_driver_unregister(struct driver_context* driver_ctx) ++{ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ DPRINT_INFO(VMBUS_DRV, "child driver (%p) unregistering - name %s", driver_ctx, driver_ctx->driver.name); ++ ++ driver_unregister(&driver_ctx->driver); ++ ++ driver_ctx->driver.bus = NULL; ++ ++ DPRINT_EXIT(VMBUS_DRV); ++} ++ ++EXPORT_SYMBOL(vmbus_child_driver_unregister); ++ ++/*++ ++ ++Name: vmbus_get_interface() ++ ++Desc: Get the vmbus channel interface. This is invoked by child/client driver that sits ++ above vmbus ++--*/ ++void vmbus_get_interface(VMBUS_CHANNEL_INTERFACE *interface) ++{ ++ VMBUS_DRIVER_OBJECT *vmbus_drv_obj=&g_vmbus_drv.drv_obj; ++ ++ vmbus_drv_obj->GetChannelInterface(interface); ++} ++ ++EXPORT_SYMBOL(vmbus_get_interface); ++ ++ ++/*++ ++ ++Name: vmbus_child_device_get_info() ++ ++Desc: Get the vmbus child device info. This is invoked to display various device attributes in sysfs. ++--*/ ++static void vmbus_child_device_get_info(DEVICE_OBJECT *device_obj, DEVICE_INFO *device_info) ++{ ++ VMBUS_DRIVER_OBJECT *vmbus_drv_obj=&g_vmbus_drv.drv_obj; ++ ++ vmbus_drv_obj->GetChannelInfo(device_obj, device_info); ++} ++ ++ ++/*++ ++ ++Name: vmbus_child_device_create() ++ ++Desc: Creates and registers a new child device on the vmbus. ++ ++--*/ ++static DEVICE_OBJECT* vmbus_child_device_create(GUID type, GUID instance, void* context) ++{ ++ struct device_context *child_device_ctx; ++ DEVICE_OBJECT* child_device_obj; ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ // Allocate the new child device ++ child_device_ctx = kzalloc(sizeof(struct device_context), GFP_KERNEL); ++ if (!child_device_ctx) ++ { ++ DPRINT_ERR(VMBUS_DRV, "unable to allocate device_context for child device"); ++ DPRINT_EXIT(VMBUS_DRV); ++ ++ return NULL; ++ } ++ ++ DPRINT_DBG(VMBUS_DRV, "child device (%p) allocated - " ++ "type {%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}," ++ "id {%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}", ++ &child_device_ctx->device, ++ type.Data[3], type.Data[2], type.Data[1], type.Data[0], type.Data[5], type.Data[4], type.Data[7], type.Data[6], type.Data[8], type.Data[9], type.Data[10], type.Data[11], type.Data[12], type.Data[13], type.Data[14], type.Data[15], ++ instance.Data[3], instance.Data[2], instance.Data[1], instance.Data[0], instance.Data[5], instance.Data[4], instance.Data[7], instance.Data[6], instance.Data[8], instance.Data[9], instance.Data[10], instance.Data[11], instance.Data[12], instance.Data[13], instance.Data[14], instance.Data[15]); ++ ++ child_device_obj = &child_device_ctx->device_obj; ++ child_device_obj->context = context; ++ memcpy(&child_device_obj->deviceType, &type, sizeof(GUID)); ++ memcpy(&child_device_obj->deviceInstance, &instance, sizeof(GUID)); ++ ++ memcpy(&child_device_ctx->class_id, &type, sizeof(GUID)); ++ memcpy(&child_device_ctx->device_id, &instance, sizeof(GUID)); ++ ++ DPRINT_EXIT(VMBUS_DRV); ++ ++ return child_device_obj; ++} ++ ++/*++ ++ ++Name: vmbus_child_device_register() ++ ++Desc: Register the child device on the specified bus ++ ++--*/ ++static int vmbus_child_device_register(DEVICE_OBJECT* root_device_obj, DEVICE_OBJECT* child_device_obj) ++{ ++ int ret=0; ++ struct device_context *root_device_ctx = to_device_context(root_device_obj); ++ struct device_context *child_device_ctx = to_device_context(child_device_obj); ++ static int device_num=0; ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ DPRINT_DBG(VMBUS_DRV, "child device (%p) registering", child_device_ctx); ++ // ++ // Make sure we are not registered already ++ // ++ if (strlen(dev_name(&child_device_ctx->device)) != 0) ++ { ++ DPRINT_ERR(VMBUS_DRV, "child device (%p) already registered - busid %s", child_device_ctx, dev_name(&child_device_ctx->device)); ++ ++ ret = -1; ++ goto Cleanup; ++ } ++ ++ // Set the device bus id. Otherwise, device_register()will fail. ++ dev_set_name(&child_device_ctx->device, "vmbus_0_%d", InterlockedIncrement(&device_num)); ++ ++ // The new device belongs to this bus ++ child_device_ctx->device.bus = &g_vmbus_drv.bus; //device->dev.bus; ++ child_device_ctx->device.parent = &root_device_ctx->device; ++ child_device_ctx->device.release = vmbus_device_release; ++ ++ // Register with the LDM. This will kick off the driver/device binding...which will ++ // eventually call vmbus_match() and vmbus_probe() ++ ret = device_register(&child_device_ctx->device); ++ ++ // vmbus_probe() error does not get propergate to device_register(). ++ ret = child_device_ctx->probe_error; ++ ++ if (ret) ++ DPRINT_ERR(VMBUS_DRV, "unable to register child device (%p) (%d)", &child_device_ctx->device); ++ else ++ DPRINT_INFO(VMBUS_DRV, "child device (%p) registered", &child_device_ctx->device); ++ ++Cleanup: ++ DPRINT_EXIT(VMBUS_DRV); ++ ++ return ret; ++} ++ ++/*++ ++ ++Name: vmbus_child_device_unregister() ++ ++Desc: Remove the specified child device from the vmbus. ++ ++--*/ ++static void vmbus_child_device_unregister(DEVICE_OBJECT* device_obj) ++{ ++ struct device_context *device_ctx = to_device_context(device_obj); ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ DPRINT_INFO(VMBUS_DRV, "unregistering child device (%p)", &device_ctx->device); ++ ++ // Kick off the process of unregistering the device. ++ // This will call vmbus_remove() and eventually vmbus_device_release() ++ device_unregister(&device_ctx->device); ++ ++ DPRINT_INFO(VMBUS_DRV, "child device (%p) unregistered", &device_ctx->device); ++ ++ DPRINT_EXIT(VMBUS_DRV); ++} ++ ++ ++/*++ ++ ++Name: vmbus_child_device_destroy() ++ ++Desc: Destroy the specified child device on the vmbus. ++ ++--*/ ++static void vmbus_child_device_destroy(DEVICE_OBJECT* device_obj) ++{ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ DPRINT_EXIT(VMBUS_DRV); ++} ++ ++/*++ ++ ++Name: vmbus_uevent() ++ ++Desc: This routine is invoked when a device is added or removed on the vmbus to generate a uevent to udev in the ++ userspace. The udev will then look at its rule and the uevent generated here to load the appropriate driver ++ ++--*/ ++#if defined(KERNEL_2_6_5) || defined(KERNEL_2_6_9) ++#elif defined(KERNEL_2_6_27) ++static int vmbus_uevent(struct device *device, struct kobj_uevent_env *env) ++{ ++ struct device_context *device_ctx = device_to_device_context(device); ++ int i=0; ++ int len=0; ++ int ret; ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ DPRINT_INFO(VMBUS_DRV, "generating uevent - VMBUS_DEVICE_CLASS_GUID={%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}", ++ device_ctx->class_id.Data[3], device_ctx->class_id.Data[2], device_ctx->class_id.Data[1], device_ctx->class_id.Data[0], ++ device_ctx->class_id.Data[5], device_ctx->class_id.Data[4], ++ device_ctx->class_id.Data[7], device_ctx->class_id.Data[6], ++ device_ctx->class_id.Data[8], device_ctx->class_id.Data[9], device_ctx->class_id.Data[10], device_ctx->class_id.Data[11], ++ device_ctx->class_id.Data[12], device_ctx->class_id.Data[13], device_ctx->class_id.Data[14], device_ctx->class_id.Data[15]); ++ ++ env->envp_idx = i; ++ env->buflen = len; ++ ret = add_uevent_var(env, ++ "VMBUS_DEVICE_CLASS_GUID={%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}", ++ device_ctx->class_id.Data[3], device_ctx->class_id.Data[2], device_ctx->class_id.Data[1], device_ctx->class_id.Data[0], ++ device_ctx->class_id.Data[5], device_ctx->class_id.Data[4], ++ device_ctx->class_id.Data[7], device_ctx->class_id.Data[6], ++ device_ctx->class_id.Data[8], device_ctx->class_id.Data[9], device_ctx->class_id.Data[10], device_ctx->class_id.Data[11], ++ device_ctx->class_id.Data[12], device_ctx->class_id.Data[13], device_ctx->class_id.Data[14], device_ctx->class_id.Data[15]); ++ ++ if (ret) ++ { ++ return ret; ++ } ++ ++ ret = add_uevent_var(env, ++ "VMBUS_DEVICE_DEVICE_GUID={%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}", ++ device_ctx->device_id.Data[3], device_ctx->device_id.Data[2], device_ctx->device_id.Data[1], device_ctx->device_id.Data[0], ++ device_ctx->device_id.Data[5], device_ctx->device_id.Data[4], ++ device_ctx->device_id.Data[7], device_ctx->device_id.Data[6], ++ device_ctx->device_id.Data[8], device_ctx->device_id.Data[9], device_ctx->device_id.Data[10], device_ctx->device_id.Data[11], ++ device_ctx->device_id.Data[12], device_ctx->device_id.Data[13], device_ctx->device_id.Data[14], device_ctx->device_id.Data[15]); ++ ++ if (ret) ++ { ++ return ret; ++ } ++ ++ env->envp[env->envp_idx] = NULL; ++ ++ DPRINT_EXIT(VMBUS_DRV); ++ ++ return 0; ++} ++ ++#else ++static int vmbus_uevent(struct device *device, char **envp, int num_envp, char *buffer, int buffer_size) ++{ ++ struct device_context *device_ctx = device_to_device_context(device); ++ int i=0; ++ int len=0; ++ int ret; ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ DPRINT_INFO(VMBUS_DRV, "generating uevent - VMBUS_DEVICE_CLASS_GUID={%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}", ++ device_ctx->class_id.Data[3], device_ctx->class_id.Data[2], device_ctx->class_id.Data[1], device_ctx->class_id.Data[0], ++ device_ctx->class_id.Data[5], device_ctx->class_id.Data[4], ++ device_ctx->class_id.Data[7], device_ctx->class_id.Data[6], ++ device_ctx->class_id.Data[8], device_ctx->class_id.Data[9], device_ctx->class_id.Data[10], device_ctx->class_id.Data[11], ++ device_ctx->class_id.Data[12], device_ctx->class_id.Data[13], device_ctx->class_id.Data[14], device_ctx->class_id.Data[15]); ++ ++ ret = add_uevent_var(envp, num_envp, &i, buffer, buffer_size, &len, ++ "VMBUS_DEVICE_CLASS_GUID={%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}", ++ device_ctx->class_id.Data[3], device_ctx->class_id.Data[2], device_ctx->class_id.Data[1], device_ctx->class_id.Data[0], ++ device_ctx->class_id.Data[5], device_ctx->class_id.Data[4], ++ device_ctx->class_id.Data[7], device_ctx->class_id.Data[6], ++ device_ctx->class_id.Data[8], device_ctx->class_id.Data[9], device_ctx->class_id.Data[10], device_ctx->class_id.Data[11], ++ device_ctx->class_id.Data[12], device_ctx->class_id.Data[13], device_ctx->class_id.Data[14], device_ctx->class_id.Data[15]); ++ ++ if (ret) ++ { ++ return ret; ++ } ++ ++ ret = add_uevent_var(envp, num_envp, &i, buffer, buffer_size, &len, ++ "VMBUS_DEVICE_DEVICE_GUID={%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x%02x%02x}", ++ device_ctx->device_id.Data[3], device_ctx->device_id.Data[2], device_ctx->device_id.Data[1], device_ctx->device_id.Data[0], ++ device_ctx->device_id.Data[5], device_ctx->device_id.Data[4], ++ device_ctx->device_id.Data[7], device_ctx->device_id.Data[6], ++ device_ctx->device_id.Data[8], device_ctx->device_id.Data[9], device_ctx->device_id.Data[10], device_ctx->device_id.Data[11], ++ device_ctx->device_id.Data[12], device_ctx->device_id.Data[13], device_ctx->device_id.Data[14], device_ctx->device_id.Data[15]); ++ ++ if (ret) ++ { ++ return ret; ++ } ++ ++ envp[i] = NULL; ++ ++ DPRINT_EXIT(VMBUS_DRV); ++ ++ return 0; ++} ++#endif ++ ++/*++ ++ ++Name: vmbus_match() ++ ++Desc: Attempt to match the specified device to the specified driver ++ ++--*/ ++static int vmbus_match(struct device *device, struct device_driver *driver) ++{ ++ int match=0; ++ struct driver_context *driver_ctx = driver_to_driver_context(driver); ++ struct device_context *device_ctx = device_to_device_context(device); ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ // We found our driver ? ++ if (memcmp(&device_ctx->class_id, &driver_ctx->class_id, sizeof(GUID)) == 0) ++ { ++ // !! NOTE: The driver_ctx is not a vmbus_drv_ctx. We typecast it here to access the ++ // DRIVER_OBJECT field ++ struct vmbus_driver_context *vmbus_drv_ctx = (struct vmbus_driver_context*)driver_ctx; ++ device_ctx->device_obj.Driver = &vmbus_drv_ctx->drv_obj.Base; ++ DPRINT_INFO(VMBUS_DRV, "device object (%p) set to driver object (%p)", &device_ctx->device_obj, device_ctx->device_obj.Driver); ++ ++ match = 1; ++ } ++ ++ DPRINT_EXIT(VMBUS_DRV); ++ ++ return match; ++} ++ ++ ++/*++ ++ ++Name: vmbus_probe_failed_cb() ++ ++Desc: Callback when a driver probe failed in vmbus_probe(). We need a callback because ++ we cannot invoked device_unregister() inside vmbus_probe() since vmbus_probe() may be ++ invoked inside device_register() i.e. we cannot call device_unregister() inside ++ device_register() ++--*/ ++#ifdef KERNEL_2_6_27 ++static void vmbus_probe_failed_cb(struct work_struct *context) ++#else ++static void vmbus_probe_failed_cb(void* context) ++#endif ++{ ++ struct device_context *device_ctx = (struct device_context*)context; ++ ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ // Kick off the process of unregistering the device. ++ // This will call vmbus_remove() and eventually vmbus_device_release() ++ device_unregister(&device_ctx->device); ++ ++ //put_device(&device_ctx->device); ++ DPRINT_EXIT(VMBUS_DRV); ++} ++ ++ ++/*++ ++ ++Name: vmbus_probe() ++ ++Desc: Add the new vmbus's child device ++ ++--*/ ++static int vmbus_probe(struct device *child_device) ++{ ++ int ret=0; ++ struct driver_context *driver_ctx = driver_to_driver_context(child_device->driver); ++ struct device_context *device_ctx = device_to_device_context(child_device); ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ // Let the specific open-source driver handles the probe if it can ++ if (driver_ctx->probe) ++ { ++ ret = device_ctx->probe_error = driver_ctx->probe(child_device); ++ if (ret != 0) ++ { ++ DPRINT_ERR(VMBUS_DRV, "probe() failed for device %s (%p) on driver %s (%d)...", dev_name(child_device), child_device, child_device->driver->name, ret); ++ ++#ifdef KERNEL_2_6_27 ++ INIT_WORK(&device_ctx->probe_failed_work_item, vmbus_probe_failed_cb); ++#else ++ INIT_WORK(&device_ctx->probe_failed_work_item, vmbus_probe_failed_cb, device_ctx); ++#endif ++ schedule_work(&device_ctx->probe_failed_work_item); ++ } ++ } ++ else ++ { ++ DPRINT_ERR(VMBUS_DRV, "probe() method not set for driver - %s", child_device->driver->name); ++ ret = -1; ++ } ++ ++ DPRINT_EXIT(VMBUS_DRV); ++ return ret; ++} ++ ++ ++/*++ ++ ++Name: vmbus_remove() ++ ++Desc: Remove a vmbus device ++ ++--*/ ++static int vmbus_remove(struct device *child_device) ++{ ++ int ret=0; ++ struct driver_context *driver_ctx; ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ // Special case root bus device ++ if (child_device->parent == NULL) ++ { ++ // No-op since it is statically defined and handle in vmbus_bus_exit() ++ DPRINT_EXIT(VMBUS_DRV); ++ return 0; ++ } ++ ++ if (child_device->driver) ++ { ++ driver_ctx = driver_to_driver_context(child_device->driver); ++ ++ // Let the specific open-source driver handles the removal if it can ++ if (driver_ctx->remove) ++ { ++ ret = driver_ctx->remove(child_device); ++ } ++ else ++ { ++ DPRINT_ERR(VMBUS_DRV, "remove() method not set for driver - %s", child_device->driver->name); ++ ret = -1; ++ } ++ } ++ else ++ { ++ ++ } ++ ++ DPRINT_EXIT(VMBUS_DRV); ++ ++ return 0; ++} ++ ++/*++ ++ ++Name: vmbus_shutdown() ++ ++Desc: Shutdown a vmbus device ++ ++--*/ ++static void vmbus_shutdown(struct device *child_device) ++{ ++ struct driver_context *driver_ctx; ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ // Special case root bus device ++ if (child_device->parent == NULL) ++ { ++ // No-op since it is statically defined and handle in vmbus_bus_exit() ++ DPRINT_EXIT(VMBUS_DRV); ++ return; ++ } ++ ++ // The device may not be attached yet ++ if (!child_device->driver) ++ { ++ DPRINT_EXIT(VMBUS_DRV); ++ return; ++ } ++ ++ driver_ctx = driver_to_driver_context(child_device->driver); ++ ++ // Let the specific open-source driver handles the removal if it can ++ if (driver_ctx->shutdown) ++ { ++ driver_ctx->shutdown(child_device); ++ } ++ ++ DPRINT_EXIT(VMBUS_DRV); ++ ++ return; ++} ++ ++/*++ ++ ++Name: vmbus_bus_release() ++ ++Desc: Final callback release of the vmbus root device ++ ++--*/ ++static void vmbus_bus_release(struct device *device) ++{ ++ DPRINT_ENTER(VMBUS_DRV); ++ DPRINT_EXIT(VMBUS_DRV); ++} ++ ++/*++ ++ ++Name: vmbus_device_release() ++ ++Desc: Final callback release of the vmbus child device ++ ++--*/ ++static void vmbus_device_release(struct device *device) ++{ ++ struct device_context *device_ctx = device_to_device_context(device); ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ //vmbus_child_device_destroy(&device_ctx->device_obj); ++ kfree(device_ctx); ++ ++ // !!DO NOT REFERENCE device_ctx anymore at this point!! ++ ++ DPRINT_EXIT(VMBUS_DRV); ++ ++ return; ++} ++ ++/*++ ++ ++Name: vmbus_msg_dpc() ++ ++Desc: Tasklet routine to handle hypervisor messages ++ ++--*/ ++static void vmbus_msg_dpc(unsigned long data) ++{ ++ VMBUS_DRIVER_OBJECT* vmbus_drv_obj = (VMBUS_DRIVER_OBJECT*)data; ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ ASSERT(vmbus_drv_obj->OnMsgDpc != NULL); ++ ++ // Call to bus driver to handle interrupt ++ vmbus_drv_obj->OnMsgDpc(&vmbus_drv_obj->Base); ++ ++ DPRINT_EXIT(VMBUS_DRV); ++} ++ ++/*++ ++ ++Name: vmbus_msg_dpc() ++ ++Desc: Tasklet routine to handle hypervisor events ++ ++--*/ ++static void vmbus_event_dpc(unsigned long data) ++{ ++ VMBUS_DRIVER_OBJECT* vmbus_drv_obj = (VMBUS_DRIVER_OBJECT*)data; ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ ASSERT(vmbus_drv_obj->OnEventDpc != NULL); ++ ++ // Call to bus driver to handle interrupt ++ vmbus_drv_obj->OnEventDpc(&vmbus_drv_obj->Base); ++ ++ DPRINT_EXIT(VMBUS_DRV); ++} ++ ++/*++ ++ ++Name: vmbus_msg_dpc() ++ ++Desc: ISR routine ++ ++--*/ ++#ifdef KERNEL_2_6_27 ++static irqreturn_t vmbus_isr(int irq, void* dev_id) ++#else ++static int vmbus_isr(int irq, void* dev_id, struct pt_regs *regs) ++#endif ++{ ++ int ret=0; ++ VMBUS_DRIVER_OBJECT* vmbus_driver_obj = &g_vmbus_drv.drv_obj; ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ ASSERT(vmbus_driver_obj->OnIsr != NULL); ++ ++ // Call to bus driver to handle interrupt ++ ret = vmbus_driver_obj->OnIsr(&vmbus_driver_obj->Base); ++ ++ // Schedules a dpc if necessary ++ if (ret > 0) ++ { ++ if (test_bit(0, (unsigned long*)&ret)) ++ { ++ tasklet_schedule(&g_vmbus_drv.msg_dpc); ++ } ++ ++ if (test_bit(1, (unsigned long*)&ret)) ++ { ++ tasklet_schedule(&g_vmbus_drv.event_dpc); ++ } ++ ++ DPRINT_EXIT(VMBUS_DRV); ++ return IRQ_HANDLED; ++ } ++ else ++ { ++ DPRINT_EXIT(VMBUS_DRV); ++ return IRQ_NONE; ++ } ++} ++ ++MODULE_LICENSE("GPL"); ++ ++ ++/*++ ++ ++Name: vmbus_init() ++ ++Desc: Main vmbus driver entry routine ++ ++--*/ ++static int __init vmbus_init(void) ++{ ++ int ret=0; ++ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ DPRINT_INFO(VMBUS_DRV, ++ "Vmbus initializing.... current log level 0x%x (%x,%x)", ++ vmbus_loglevel, HIWORD(vmbus_loglevel), LOWORD(vmbus_loglevel)); ++#ifdef KERNEL_2_6_27 ++//Todo: it is used for loglevel, to be ported to new kernel. ++#else ++ vmbus_ctl_table_hdr = register_sysctl_table(vmus_root_ctl_table, 0); ++ if (!vmbus_ctl_table_hdr) ++ { ++ DPRINT_EXIT(VMBUS_DRV); ++ return -ENOMEM; ++ } ++#endif ++ ++ ret = vmbus_bus_init(VmbusInitialize); ++ ++ DPRINT_EXIT(VMBUS_DRV); ++ return ret; ++} ++ ++ ++ ++/*++ ++ ++Name: vmbus_init() ++ ++Desc: Main vmbus driver exit routine ++ ++--*/ ++static void __exit vmbus_exit(void) ++{ ++ DPRINT_ENTER(VMBUS_DRV); ++ ++ vmbus_bus_exit(); ++#ifdef KERNEL_2_6_27 ++//Todo: it is used for loglevel, to be ported to new kernel. ++#else ++ unregister_sysctl_table(vmbus_ctl_table_hdr); ++#endif ++ DPRINT_EXIT(VMBUS_DRV); ++ ++ return; ++} ++ ++#if defined(KERNEL_2_6_5) ++#else ++module_param(vmbus_irq, int, S_IRUGO); ++module_param(vmbus_loglevel, int, S_IRUGO); ++#endif ++ ++module_init(vmbus_init); ++module_exit(vmbus_exit); ++// eof +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/hv/VmbusPrivate.h linux-2.6.27.29-0.1.1/drivers/staging/hv/VmbusPrivate.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/hv/VmbusPrivate.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,170 @@ ++/* ++ * ++ * Copyright (c) 2009, Microsoft Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ * ++ * Authors: ++ * Haiyang Zhang ++ * Hank Janssen ++ * ++ */ ++ ++ ++#ifndef _VMBUS_PRIVATE_H_ ++#define _VMBUS_PRIVATE_H_ ++ ++#ifndef INTERNAL ++#define INTERNAL static ++#endif ++ ++#include "Hv.h" ++#include "include/VmbusApi.h" ++#include "Channel.h" ++#include "ChannelMgmt.h" ++#include "ChannelInterface.h" ++//#include "ChannelMessages.h" ++#include "RingBuffer.h" ++//#include "Packet.h" ++#include "include/List.h" ++ ++// ++// Defines ++// ++ ++// Maximum channels is determined by the size of the interrupt page which is PAGE_SIZE. 1/2 of PAGE_SIZE is for ++// send endpoint interrupt and the other is receive endpoint interrupt ++#define MAX_NUM_CHANNELS (PAGE_SIZE >> 1) << 3 // 16348 channels ++ ++// The value here must be in multiple of 32 ++// TODO: Need to make this configurable ++#define MAX_NUM_CHANNELS_SUPPORTED 256 ++ ++// ++// Data types ++// ++ ++typedef enum { ++ Disconnected, ++ Connecting, ++ Connected, ++ Disconnecting ++} VMBUS_CONNECT_STATE; ++ ++#define MAX_SIZE_CHANNEL_MESSAGE HV_MESSAGE_PAYLOAD_BYTE_COUNT ++ ++typedef struct _VMBUS_CONNECTION { ++ ++ VMBUS_CONNECT_STATE ConnectState; ++ ++ UINT32 NextGpadlHandle; ++ ++ // Represents channel interrupts. Each bit position ++ // represents a channel. ++ // When a channel sends an interrupt via VMBUS, it ++ // finds its bit in the sendInterruptPage, set it and ++ // calls Hv to generate a port event. The other end ++ // receives the port event and parse the recvInterruptPage ++ // to see which bit is set ++ VOID* InterruptPage; ++ VOID* SendInterruptPage; ++ VOID* RecvInterruptPage; ++ ++ // 2 pages - 1st page for parent->child notification and 2nd is child->parent notification ++ VOID* MonitorPages; ++ LIST_ENTRY ChannelMsgList; ++ HANDLE ChannelMsgLock; ++ ++ // List of channels ++ LIST_ENTRY ChannelList; ++ HANDLE ChannelLock; ++ ++ HANDLE WorkQueue; ++} VMBUS_CONNECTION; ++ ++ ++typedef struct _VMBUS_MSGINFO { ++ // Bookkeeping stuff ++ LIST_ENTRY MsgListEntry; ++ ++ // Synchronize the request/response if needed ++ HANDLE WaitEvent; ++ ++ // The message itself ++ unsigned char Msg[0]; ++} VMBUS_MSGINFO; ++ ++ ++// ++// Externs ++// ++extern VMBUS_CONNECTION gVmbusConnection; ++ ++// ++// General vmbus interface ++// ++INTERNAL DEVICE_OBJECT* ++VmbusChildDeviceCreate( ++ GUID deviceType, ++ GUID deviceInstance, ++ void *context); ++ ++INTERNAL int ++VmbusChildDeviceAdd( ++ DEVICE_OBJECT* Device); ++ ++INTERNAL void ++VmbusChildDeviceRemove( ++ DEVICE_OBJECT* Device); ++ ++//INTERNAL void ++//VmbusChildDeviceDestroy( ++// DEVICE_OBJECT*); ++ ++INTERNAL VMBUS_CHANNEL* ++GetChannelFromRelId( ++ UINT32 relId ++ ); ++ ++// ++// Connection interface ++// ++INTERNAL int ++VmbusConnect( ++ VOID ++ ); ++ ++INTERNAL int ++VmbusDisconnect( ++ VOID ++ ); ++ ++INTERNAL int ++VmbusPostMessage( ++ PVOID buffer, ++ SIZE_T bufSize ++ ); ++ ++INTERNAL int ++VmbusSetEvent( ++ UINT32 childRelId ++ ); ++ ++INTERNAL VOID ++VmbusOnEvents( ++ VOID ++ ); ++ ++ ++#endif // _VMBUS_PRIVATE_H_ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/Kconfig linux-2.6.27.29-0.1.1/drivers/staging/Kconfig +--- linux-2.6.27.25-0.1.1/drivers/staging/Kconfig 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/Kconfig 2009-08-27 12:44:29.000000000 +0100 +@@ -57,4 +57,8 @@ source "drivers/staging/benet/Kconfig" + + source "drivers/staging/rtl8187se/Kconfig" + ++source "drivers/staging/rtl8192e/Kconfig" ++ ++source "drivers/staging/hv/Kconfig" ++ + endif # STAGING +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/Makefile linux-2.6.27.29-0.1.1/drivers/staging/Makefile +--- linux-2.6.27.25-0.1.1/drivers/staging/Makefile 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/Makefile 2009-08-27 12:44:29.000000000 +0100 +@@ -20,3 +20,5 @@ obj-$(CONFIG_RT2870) += rt2870/ + obj-$(CONFIG_RT3070) += rt3070/ + obj-$(CONFIG_BENET) += benet/ + obj-$(CONFIG_RTL8187SE) += rtl8187se/ ++obj-$(CONFIG_RTL8192E) += rtl8192e/ ++obj-$(CONFIG_HYPERV) += hv/ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/2860_main_dev.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/2860_main_dev.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/2860_main_dev.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/2860_main_dev.c 2009-08-27 12:44:31.000000000 +0100 +@@ -90,12 +90,10 @@ void init_thread_task(PRTMP_ADAPTER pAd) + static void __exit rt2860_cleanup_module(void); + static int __init rt2860_init_module(void); + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + #ifdef CONFIG_PM + static int rt2860_suspend(struct pci_dev *pci_dev, pm_message_t state); + static int rt2860_resume(struct pci_dev *pci_dev); + #endif // CONFIG_PM // +-#endif + + + // +@@ -128,22 +126,15 @@ static struct pci_driver rt2860_driver = + name: "rt2860", + id_table: rt2860_pci_tbl, + probe: rt2860_init_one, +-#if LINUX_VERSION_CODE >= 0x20412 + remove: __devexit_p(rt2860_remove_one), +-#else +- remove: __devexit(rt2860_remove_one), +-#endif + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + #ifdef CONFIG_PM + suspend: rt2860_suspend, + resume: rt2860_resume, + #endif +-#endif + }; + + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + #ifdef CONFIG_PM + + VOID RT2860RejectPendingPackets( +@@ -170,7 +161,7 @@ static int rt2860_suspend( + } + else + { +- pAd = (PRTMP_ADAPTER)net_dev->priv; ++ pAd = net_dev->ml_priv; + + /* we can not use IFF_UP because ra0 down but ra1 up */ + /* and 1 suspend/resume function for 1 module, not for each interface */ +@@ -249,7 +240,7 @@ static int rt2860_resume( + DBGPRINT(RT_DEBUG_ERROR, ("net_dev == NULL!\n")); + } + else +- pAd = (PRTMP_ADAPTER)net_dev->priv; ++ pAd = net_dev->ml_priv; + + if (pAd != NULL) + { +@@ -284,16 +275,11 @@ static int rt2860_resume( + return 0; + } + #endif // CONFIG_PM // +-#endif + + + static INT __init rt2860_init_module(VOID) + { +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + return pci_register_driver(&rt2860_driver); +-#else +- return pci_module_init(&rt2860_driver); +-#endif + } + + +@@ -336,7 +322,7 @@ static VOID __devexit rt2860_remove_one( + IN struct pci_dev *pci_dev) + { + struct net_device *net_dev = pci_get_drvdata(pci_dev); +- RTMP_ADAPTER *pAd = net_dev->priv; ++ RTMP_ADAPTER *pAd = net_dev->ml_priv; + + DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_remove_one\n")); + +@@ -374,11 +360,7 @@ static VOID __devexit rt2860_remove_one( + } + + // Free pre-allocated net_device memory +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + free_netdev(net_dev); +-#else +- kfree(net_dev); +-#endif + } + + // +@@ -758,16 +740,13 @@ static void ac0_dma_done_tasklet(unsigne + int print_int_count; + + IRQ_HANDLE_TYPE +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)) + rt2860_interrupt(int irq, void *dev_instance) +-#else +-rt2860_interrupt(int irq, void *dev_instance, struct pt_regs *regs) +-#endif + { + struct net_device *net_dev = (struct net_device *) dev_instance; +- PRTMP_ADAPTER pAd = (PRTMP_ADAPTER) net_dev->priv; ++ PRTMP_ADAPTER pAd = net_dev->ml_priv; + INT_SOURCE_CSR_STRUC IntSource; + POS_COOKIE pObj; ++ BOOLEAN bOldValue; + + pObj = (POS_COOKIE) pAd->OS_Cookie; + +@@ -800,20 +779,19 @@ rt2860_interrupt(int irq, void *dev_inst + // RT2661 => when ASIC is sleeping, MAC register cannot be read and written. + // RT2860 => when ASIC is sleeping, MAC register can be read and written. + ++ bOldValue = pAd->bPCIclkOff; ++ pAd->bPCIclkOff = FALSE; + { + RTMP_IO_READ32(pAd, INT_SOURCE_CSR, &IntSource.word); + RTMP_IO_WRITE32(pAd, INT_SOURCE_CSR, IntSource.word); // write 1 to clear + } ++ pAd->bPCIclkOff = bOldValue; + + // Do nothing if Reset in progress + if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS) || + RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) + { +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) +- return IRQ_HANDLED; +-#else +- return; +-#endif ++ return IRQ_HANDLED; + } + + // +@@ -822,8 +800,6 @@ rt2860_interrupt(int irq, void *dev_inst + // The priority can be adjust by altering processing if statement + // + +- pAd->bPCIclkOff = FALSE; +- + // If required spinlock, each interrupt service routine has to acquire + // and release itself. + // +@@ -832,11 +808,8 @@ rt2860_interrupt(int irq, void *dev_inst + if (IntSource.word == 0xffffffff) + { + RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST | fRTMP_ADAPTER_HALT_IN_PROGRESS); +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) +- return IRQ_HANDLED; +-#else +- return; +-#endif ++ printk("snowpin - IntSource.word == 0xffffffff\n"); ++ return IRQ_HANDLED; + } + + if (IntSource.word & TxCoherent) +@@ -970,10 +943,7 @@ rt2860_interrupt(int irq, void *dev_inst + } + #endif // CONFIG_STA_SUPPORT // + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + return IRQ_HANDLED; +-#endif +- + } + + /* +@@ -1022,15 +992,11 @@ BOOLEAN RT28XXNetDevInit( + IN RTMP_ADAPTER *pAd) + { + struct pci_dev *pci_dev = (struct pci_dev *)_dev_p; +- CHAR *print_name; ++ const CHAR *print_name; + ULONG csr_addr; + + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) +- print_name = pci_dev ? pci_name(pci_dev) : "rt2860"; +-#else +- print_name = pci_dev ? pci_dev->slot_name : "rt2860"; +-#endif // LINUX_VERSION_CODE // ++ print_name = pci_dev ? pci_name(pci_dev) : "rt2860"; + + net_dev->base_addr = 0; + net_dev->irq = 0; +@@ -1202,7 +1168,7 @@ VOID RT28xx_UpdateBeaconToAsic( + UCHAR bcn_idx = 0; + + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s() : No valid Interface be found.\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s() : No valid Interface be found.\n", __func__)); + return; + } + +@@ -1300,7 +1266,7 @@ VOID rt2860_stop(struct net_device *net_ + DBGPRINT(RT_DEBUG_ERROR, ("net_dev == NULL!\n")); + } + else +- pAd = (PRTMP_ADAPTER)net_dev->priv; ++ pAd = net_dev->ml_priv; + + if (pAd != NULL) + { +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/ba_action.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/ba_action.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/ba_action.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/ba_action.c 2009-08-27 12:44:31.000000000 +0100 +@@ -599,7 +599,7 @@ VOID BAOriSessionAdd( + + pBAEntry->ORIBATimer.TimerValue = 0; //pFrame->TimeOutValue; + +- DBGPRINT(RT_DEBUG_TRACE,("%s : TXBAbitmap = %x, BAWinSize = %d, TimeOut = %ld\n", __FUNCTION__, pEntry->TXBAbitmap, ++ DBGPRINT(RT_DEBUG_TRACE,("%s : TXBAbitmap = %x, BAWinSize = %d, TimeOut = %ld\n", __func__, pEntry->TXBAbitmap, + pBAEntry->BAWinSize, pBAEntry->ORIBATimer.TimerValue)); + + // SEND BAR ; +@@ -673,7 +673,7 @@ BOOLEAN BARecSessionAdd( + ba_refresh_reordering_mpdus(pAd, pBAEntry); + } + +- DBGPRINT(RT_DEBUG_TRACE,("%s(%ld): Idx = %d, BAWinSize(req %d) = %d\n", __FUNCTION__, pAd->BATable.numAsRecipient, Idx, ++ DBGPRINT(RT_DEBUG_TRACE,("%s(%ld): Idx = %d, BAWinSize(req %d) = %d\n", __func__, pAd->BATable.numAsRecipient, Idx, + pFrame->BaParm.BufSize, BAWinSize)); + + // Start fill in parameters. +@@ -915,7 +915,7 @@ VOID BAOriSessionTearDown( + return; + } + +- DBGPRINT(RT_DEBUG_TRACE,("%s===>Wcid=%d.TID=%d \n", __FUNCTION__, Wcid, TID)); ++ DBGPRINT(RT_DEBUG_TRACE,("%s===>Wcid=%d.TID=%d \n", __func__, Wcid, TID)); + + pBAEntry = &pAd->BATable.BAOriEntry[Idx]; + DBGPRINT(RT_DEBUG_TRACE,("\t===>Idx = %ld, Wcid=%d.TID=%d, ORI_BA_Status = %d \n", Idx, Wcid, TID, pBAEntry->ORI_BA_Status)); +@@ -974,7 +974,7 @@ VOID BARecSessionTearDown( + if (Idx == 0) + return; + +- DBGPRINT(RT_DEBUG_TRACE,("%s===>Wcid=%d.TID=%d \n", __FUNCTION__, Wcid, TID)); ++ DBGPRINT(RT_DEBUG_TRACE,("%s===>Wcid=%d.TID=%d \n", __func__, Wcid, TID)); + + + pBAEntry = &pAd->BATable.BARecEntry[Idx]; +@@ -1185,7 +1185,7 @@ VOID PeerAddBAReqAction( + PULONG ptemp; + PMAC_TABLE_ENTRY pMacEntry; + +- DBGPRINT(RT_DEBUG_TRACE, ("%s ==> (Wcid = %d)\n", __FUNCTION__, Elem->Wcid)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s ==> (Wcid = %d)\n", __func__, Elem->Wcid)); + + //hex_dump("AddBAReq", Elem->Msg, Elem->MsgLen); + +@@ -1269,7 +1269,7 @@ VOID PeerAddBAReqAction( + MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, FrameLen); + MlmeFreeMemory(pAd, pOutBuffer); + +- DBGPRINT(RT_DEBUG_TRACE, ("%s(%d): TID(%d), BufSize(%d) <== \n", __FUNCTION__, Elem->Wcid, ADDframe.BaParm.TID, ++ DBGPRINT(RT_DEBUG_TRACE, ("%s(%d): TID(%d), BufSize(%d) <== \n", __func__, Elem->Wcid, ADDframe.BaParm.TID, + ADDframe.BaParm.BufSize)); + } + +@@ -1288,7 +1288,7 @@ VOID PeerAddBARspAction( + if (Elem->Wcid >= MAX_LEN_OF_MAC_TABLE) + return; + +- DBGPRINT(RT_DEBUG_TRACE, ("%s ==> Wcid(%d)\n", __FUNCTION__, Elem->Wcid)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s ==> Wcid(%d)\n", __func__, Elem->Wcid)); + + //hex_dump("PeerAddBARspAction()", Elem->Msg, Elem->MsgLen); + +@@ -1329,7 +1329,7 @@ VOID PeerDelBAAction( + //PUCHAR pOutBuffer = NULL; + PFRAME_DELBA_REQ pDelFrame = NULL; + +- DBGPRINT(RT_DEBUG_TRACE,("%s ==>\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE,("%s ==>\n", __func__)); + //DELBA Request from unknown peer, ignore this. + if (PeerDelBAActionSanity(pAd, Elem->Wcid, Elem->Msg, Elem->MsgLen)) + { +@@ -1366,7 +1366,7 @@ BOOLEAN CntlEnqueueForRecv( + + TID = (UCHAR)pFrame->BARControl.TID; + +- DBGPRINT(RT_DEBUG_TRACE, ("%s(): BAR-Wcid(%ld), Tid (%d)\n", __FUNCTION__, Wcid, TID)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s(): BAR-Wcid(%ld), Tid (%d)\n", __func__, Wcid, TID)); + //hex_dump("BAR", (PCHAR) pFrame, MsgLen); + // Do nothing if the driver is starting halt state. + // This might happen when timer already been fired before cancel timer with mlmehalt +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/cmm_data_2860.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/cmm_data_2860.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/cmm_data_2860.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/cmm_data_2860.c 2009-08-27 12:44:31.000000000 +0100 +@@ -634,7 +634,7 @@ VOID RT28xxPciAsicRadioOff( + } + + // Once go into this function, disable tx because don't want too many packets in queue to prevent HW stops. +- pAd->bPCIclkOffDisableTx = TRUE; ++ RTMP_SET_PSFLAG(pAd, fRTMP_PS_DISABLE_TX); + + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) + { +@@ -651,7 +651,7 @@ VOID RT28xxPciAsicRadioOff( + { + DBGPRINT(RT_DEBUG_TRACE, ("TbTTTime = 0x%x , give up this sleep. \n", TbTTTime)); + OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE); +- pAd->bPCIclkOffDisableTx = FALSE; ++ RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_DISABLE_TX); + return; + } + else +@@ -688,18 +688,25 @@ VOID RT28xxPciAsicRadioOff( + if (i >= 50) + { + DBGPRINT(RT_DEBUG_TRACE, ("DMA keeps busy. return on RT28xxPciAsicRadioOff ()\n")); +- pAd->bPCIclkOffDisableTx = FALSE; + RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &DmaCfg.word); + DmaCfg.field.EnableTxDMA = 1; + RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, DmaCfg.word); ++ pAd->CheckDmaBusyCount++; + return; + } ++ else ++ { ++ pAd->CheckDmaBusyCount = 0; ++ } + + RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF); + + // Set to 1R. +- tempBBP_R3 = (pAd->StaCfg.BBPR3 & 0xE7); +- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, tempBBP_R3); ++ if (pAd->Antenna.field.RxPath > 1) ++ { ++ tempBBP_R3 = (pAd->StaCfg.BBPR3 & 0xE7); ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, tempBBP_R3); ++ } + + // In Radio Off, we turn off RF clk, So now need to call ASICSwitchChannel again. + if (INFRA_ON(pAd) && (pAd->CommonCfg.CentralChannel != pAd->CommonCfg.Channel) +@@ -714,8 +721,15 @@ VOID RT28xxPciAsicRadioOff( + AsicTurnOffRFClk(pAd, pAd->CommonCfg.Channel); + } + +- // When PCI clock is off, don't want to service interrupt. +- RTMP_IO_WRITE32(pAd, INT_MASK_CSR, AutoWakeupInt); ++ if (Level != RTMP_HALT) ++ { ++ // Change Interrupt bitmask. ++ RTMP_IO_WRITE32(pAd, INT_MASK_CSR, AutoWakeupInt); ++ } ++ else ++ { ++ NICDisableInterrupt(pAd); ++ } + + RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx); + // Disable MAC Rx +@@ -726,7 +740,8 @@ VOID RT28xxPciAsicRadioOff( + // 2. Send Sleep command + RTMP_IO_WRITE32(pAd, H2M_MAILBOX_STATUS, 0xffffffff); + RTMP_IO_WRITE32(pAd, H2M_MAILBOX_CID, 0xffffffff); +- AsicSendCommandToMcu(pAd, 0x30, PowerSafeCID, 0xff, 0x00); // send POWER-SAVE command to MCU. Timeout unit:40us. ++ // send POWER-SAVE command to MCU. high-byte = 1 save power as much as possible. high byte = 0 save less power ++ AsicSendCommandToMcu(pAd, 0x30, PowerSafeCID, 0xff, 0x1); + // 2-1. Wait command success + // Status = 1 : success, Status = 2, already sleep, Status = 3, Maybe MAC is busy so can't finish this task. + brc = AsicCheckCommanOk(pAd, PowerSafeCID); +@@ -734,7 +749,7 @@ VOID RT28xxPciAsicRadioOff( + if (brc == FALSE) + { + // try again +- AsicSendCommandToMcu(pAd, 0x30, PowerSafeCID, 0xff, 0x00); // send POWER-SAVE command to MCU. Timeout unit:40us. ++ AsicSendCommandToMcu(pAd, 0x30, PowerSafeCID, 0xff, 0x01); // send POWER-SAVE command to MCU. Timeout unit:40us. + //RTMPusecDelay(200); + brc = AsicCheckCommanOk(pAd, PowerSafeCID); + } +@@ -759,7 +774,7 @@ VOID RT28xxPciAsicRadioOff( + do + { + RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &DmaCfg.word); +- if (DmaCfg.field.RxDMABusy == 0) ++ if ((DmaCfg.field.RxDMABusy == 0) && (DmaCfg.field.TxDMABusy == 0)) + break; + RTMPusecDelay(20); + i++; +@@ -767,13 +782,12 @@ VOID RT28xxPciAsicRadioOff( + + if (i >= 50) + { ++ pAd->CheckDmaBusyCount++; + DBGPRINT(RT_DEBUG_TRACE, ("DMA Rx keeps busy. on RT28xxPciAsicRadioOff ()\n")); + } +- // disable DMA Rx. ++ else + { +- RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &DmaCfg.word); +- DmaCfg.field.EnableRxDMA = 0; +- RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, DmaCfg.word); ++ pAd->CheckDmaBusyCount = 0; + } + + if (Level == DOT11POWERSAVE) +@@ -799,7 +813,7 @@ VOID RT28xxPciAsicRadioOff( + if (Level == RTMP_HALT) + { + if ((brc == TRUE) && (i < 50)) +- RTMPPCIeLinkCtrlSetting(pAd, 1); ++ RTMPPCIeLinkCtrlSetting(pAd, 0); + } + // 4. Set PCI configuration Space Link Comtrol fields. Only Radio Off needs to call this function + else +@@ -808,7 +822,7 @@ VOID RT28xxPciAsicRadioOff( + RTMPPCIeLinkCtrlSetting(pAd, 3); + } + +- pAd->bPCIclkOffDisableTx = FALSE; ++ RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_DISABLE_TX); + } + + +@@ -835,7 +849,8 @@ BOOLEAN RT28xxPciAsicRadioOn( + { + pAd->Mlme.bPsPollTimerRunning = FALSE; + RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled); +- if ((Level == GUIRADIO_OFF) || (Level == GUI_IDLE_POWER_SAVE)) ++ if ((Level == GUIRADIO_OFF) || (Level == GUI_IDLE_POWER_SAVE) ++ || (RTMP_TEST_PSFLAG(pAd, fRTMP_PS_SET_PCI_CLK_OFF_COMMAND))) + { + DBGPRINT(RT_DEBUG_TRACE, ("RT28xxPciAsicRadioOn ()\n")); + // 1. Set PCI Link Control in Configuration Space. +@@ -845,15 +860,14 @@ BOOLEAN RT28xxPciAsicRadioOn( + } + + pAd->bPCIclkOff = FALSE; +- ++ RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0x3a80); + // 2. Send wake up command. +- AsicSendCommandToMcu(pAd, 0x31, PowerWakeCID, 0x00, 0x00); ++ AsicSendCommandToMcu(pAd, 0x31, PowerWakeCID, 0x00, 0x02); + + // 2-1. wait command ok. + brv = AsicCheckCommanOk(pAd, PowerWakeCID); + if (brv) + { +- //RTMP_IO_WRITE32(pAd, INT_MASK_CSR, (DELAYINTMASK|RxINT)); + NICEnableInterrupt(pAd); + + // 3. Enable Tx DMA. +@@ -893,13 +907,10 @@ BOOLEAN RT28xxPciAsicRadioOn( + + VOID RT28xxPciStaAsicForceWakeup( + IN PRTMP_ADAPTER pAd, +- IN BOOLEAN bFromTx) ++ IN UCHAR Level) + { + AUTO_WAKEUP_STRUC AutoWakeupCfg; + +- if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) +- return; +- + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WAKEUP_NOW)) + { + DBGPRINT(RT_DEBUG_TRACE, ("waking up now!\n")); +@@ -907,38 +918,48 @@ VOID RT28xxPciStaAsicForceWakeup( + } + + OPSTATUS_SET_FLAG(pAd, fOP_STATUS_WAKEUP_NOW); ++ RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_GO_TO_SLEEP_NOW); + + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) + { + // Support PCIe Advance Power Save +- if (bFromTx == TRUE) ++ if (((Level == FROM_TX) && (pAd->Mlme.bPsPollTimerRunning == TRUE)) || ++ (Level == RTMP_HALT)) + { + pAd->Mlme.bPsPollTimerRunning = FALSE; + RTMPPCIeLinkCtrlValueRestore(pAd, RESTORE_WAKEUP); +- RTMPusecDelay(3000); ++ RTMPusecDelay(5000); + DBGPRINT(RT_DEBUG_TRACE, ("=======AsicForceWakeup===bFromTx\n")); + } + + AutoWakeupCfg.word = 0; + RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word); + +- if (RT28xxPciAsicRadioOn(pAd, DOT11POWERSAVE)) +- { +- // In Radio Off, we turn off RF clk, So now need to call ASICSwitchChannel again. +- if (INFRA_ON(pAd) && (pAd->CommonCfg.CentralChannel != pAd->CommonCfg.Channel) +- && (pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth == BW_40)) +- { +- // Must using 40MHz. +- AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel, FALSE); +- AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel); +- } +- else +- { +- // Must using 20MHz. +- AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE); +- AsicLockChannel(pAd, pAd->CommonCfg.Channel); +- } +- } ++ // If this is called from Halt. ALWAYS force wakeup!!! ++ if (Level == RTMP_HALT) ++ { ++ RT28xxPciAsicRadioOn(pAd, RTMP_HALT); ++ } ++ else ++ { ++ if (RT28xxPciAsicRadioOn(pAd, DOT11POWERSAVE)) ++ { ++ // In Radio Off, we turn off RF clk, So now need to call ASICSwitchChannel again. ++ if (INFRA_ON(pAd) && (pAd->CommonCfg.CentralChannel != pAd->CommonCfg.Channel) ++ && (pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth == BW_40)) ++ { ++ // Must using 40MHz. ++ AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel, FALSE); ++ AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel); ++ } ++ else ++ { ++ // Must using 20MHz. ++ AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE); ++ AsicLockChannel(pAd, pAd->CommonCfg.Channel); ++ } ++ } ++ } + } + else + { +@@ -1002,7 +1023,7 @@ VOID RT28xxPciStaAsicSleepThenAutoWakeup + AutoWakeupCfg.field.AutoLeadTime = 5; + RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word); + AsicSendCommandToMcu(pAd, 0x30, 0xff, 0xff, 0x00); // send POWER-SAVE command to MCU. Timeout 40us. +- DBGPRINT(RT_DEBUG_TRACE, ("<-- %s, TbttNumToNextWakeUp=%d \n", __FUNCTION__, TbttNumToNextWakeUp)); ++ DBGPRINT(RT_DEBUG_TRACE, ("<-- %s, TbttNumToNextWakeUp=%d \n", __func__, TbttNumToNextWakeUp)); + } + OPSTATUS_SET_FLAG(pAd, fOP_STATUS_DOZE); + } +@@ -1115,13 +1136,14 @@ VOID RT28xxPciMlmeRadioOn( + if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) + return; + +- DBGPRINT(RT_DEBUG_TRACE,("%s===>\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE,("%s===>\n", __func__)); + + if ((pAd->OpMode == OPMODE_AP) || + ((pAd->OpMode == OPMODE_STA) && (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)))) + { + NICResetFromError(pAd); + ++ /* + RTMPRingCleanUp(pAd, QID_AC_BK); + RTMPRingCleanUp(pAd, QID_AC_BE); + RTMPRingCleanUp(pAd, QID_AC_VI); +@@ -1129,6 +1151,7 @@ VOID RT28xxPciMlmeRadioOn( + RTMPRingCleanUp(pAd, QID_HCCA); + RTMPRingCleanUp(pAd, QID_MGMT); + RTMPRingCleanUp(pAd, QID_RX); ++ */ + + // Enable Tx/Rx + RTMPEnableRxTx(pAd); +@@ -1162,20 +1185,25 @@ VOID RT28xxPciMlmeRadioOFF( + WPDMA_GLO_CFG_STRUC GloCfg; + UINT32 i; + ++ if (pAd->StaCfg.bRadio == TRUE) ++ { ++ DBGPRINT(RT_DEBUG_TRACE,("-->MlmeRadioOff() return on bRadio == TRUE; \n")); ++ return; ++ } ++ + if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) + return; + +- DBGPRINT(RT_DEBUG_TRACE,("%s===>\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE,("%s===>\n", __func__)); + + // Set LED + RTMPSetLED(pAd, LED_RADIO_OFF); +- // Set Radio off flag +- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF); + + #ifdef CONFIG_STA_SUPPORT + IF_DEV_CONFIG_OPMODE_ON_STA(pAd) + { + BOOLEAN Cancelled; ++ + if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS)) + { + RTMPCancelTimer(&pAd->MlmeAux.ScanTimer, &Cancelled); +@@ -1185,6 +1213,15 @@ VOID RT28xxPciMlmeRadioOFF( + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) + { + BOOLEAN Cancelled; ++ ++ // Always radio on since the NIC needs to set the MCU command (LED_RADIO_OFF). ++ if ((pAd->OpMode == OPMODE_STA) && ++ (IDLE_ON(pAd)) && ++ (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF))) ++ { ++ RT28xxPciAsicRadioOn(pAd, GUI_IDLE_POWER_SAVE); ++ } ++ + pAd->Mlme.bPsPollTimerRunning = FALSE; + RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled); + RTMPCancelTimer(&pAd->Mlme.RadioOnOffTimer, &Cancelled); +@@ -1197,9 +1234,26 @@ VOID RT28xxPciMlmeRadioOFF( + //========================================== + // Clean up old bss table + BssTableInit(&pAd->ScanTab); ++ ++ RTMPRingCleanUp(pAd, QID_AC_BK); ++ RTMPRingCleanUp(pAd, QID_AC_BE); ++ RTMPRingCleanUp(pAd, QID_AC_VI); ++ RTMPRingCleanUp(pAd, QID_AC_VO); ++ RTMPRingCleanUp(pAd, QID_HCCA); ++ RTMPRingCleanUp(pAd, QID_MGMT); ++ RTMPRingCleanUp(pAd, QID_RX); ++ ++ if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) ++ { ++ RTMPSetTimer(&pAd->Mlme.RadioOnOffTimer, 500); ++ return; ++ } + } + #endif // CONFIG_STA_SUPPORT // + ++ // Set Radio off flag ++ RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF); ++ + // Disable Tx/Rx DMA + RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word); // disable DMA + GloCfg.field.EnableTxDMA = 0; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/cmm_data.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/cmm_data.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/cmm_data.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/cmm_data.c 2009-08-27 12:44:31.000000000 +0100 +@@ -105,9 +105,7 @@ NDIS_STATUS MiniportMMRequest( + PNDIS_PACKET pPacket; + NDIS_STATUS Status = NDIS_STATUS_SUCCESS; + ULONG FreeNum; +-#ifdef RT2860 + unsigned long IrqFlags = 0; +-#endif // RT2860 // + UCHAR IrqState; + UCHAR rtmpHwHdr[TXINFO_SIZE + TXWI_SIZE]; //RTMP_HW_HDR_LEN]; + +@@ -118,10 +116,9 @@ NDIS_STATUS MiniportMMRequest( + // 2860C use Tx Ring + + IrqState = pAd->irq_disabled; +-#ifdef RT2860 ++ + if ((pAd->MACVersion == 0x28600100) && (!IrqState)) + RTMP_IRQ_LOCK(&pAd->irq_lock, IrqFlags); +-#endif // RT2860 // + + do + { +@@ -175,17 +172,14 @@ NDIS_STATUS MiniportMMRequest( + + } while (FALSE); + +-#ifdef RT2860 + // 2860C use Tx Ring + if ((pAd->MACVersion == 0x28600100) && (!IrqState)) + RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags); +-#endif // RT2860 // + + return Status; + } + + +-#ifdef RT2860 + NDIS_STATUS MiniportMMRequestUnlock( + IN PRTMP_ADAPTER pAd, + IN UCHAR QueIdx, +@@ -253,7 +247,6 @@ NDIS_STATUS MiniportMMRequestUnlock( + + return Status; + } +-#endif // RT2860 // + + + /* +@@ -290,17 +283,14 @@ NDIS_STATUS MlmeHardTransmit( + return NDIS_STATUS_FAILURE; + } + +-#ifdef RT2860 + if ( pAd->MACVersion == 0x28600100 ) + return MlmeHardTransmitTxRing(pAd,QueIdx,pPacket); + else +-#endif // RT2860 // + return MlmeHardTransmitMgmtRing(pAd,QueIdx,pPacket); + + } + + +-#ifdef RT2860 + NDIS_STATUS MlmeHardTransmitTxRing( + IN PRTMP_ADAPTER pAd, + IN UCHAR QueIdx, +@@ -366,7 +356,7 @@ NDIS_STATUS MlmeHardTransmitTxRing( + { + // outgoing frame always wakeup PHY to prevent frame lost + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) +- AsicForceWakeup(pAd, TRUE); ++ AsicForceWakeup(pAd, FROM_TX); + } + #endif // CONFIG_STA_SUPPORT // + pFirstTxWI =(PTXWI_STRUC)pSrcBufVA; +@@ -509,7 +499,6 @@ NDIS_STATUS MlmeHardTransmitTxRing( + + return NDIS_STATUS_SUCCESS; + } +-#endif // RT2860 // + + + NDIS_STATUS MlmeHardTransmitMgmtRing( +@@ -541,7 +530,7 @@ NDIS_STATUS MlmeHardTransmitMgmtRing( + { + // outgoing frame always wakeup PHY to prevent frame lost + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) +- AsicForceWakeup(pAd, TRUE); ++ AsicForceWakeup(pAd, FROM_TX); + } + #endif // CONFIG_STA_SUPPORT // + +@@ -943,9 +932,6 @@ BOOLEAN RTMP_FillTxBlkInfo( + } + + return TRUE; +- +-FillTxBlkErr: +- return FALSE; + } + + +@@ -1079,7 +1065,6 @@ VOID RTMPDeQueuePacket( + break; + } + +-#ifdef RT2860 + FreeNumber[QueIdx] = GET_TXRING_FREENO(pAd, QueIdx); + + #ifdef DBG_DIAGNOSE +@@ -1104,7 +1089,6 @@ VOID RTMPDeQueuePacket( + RTMPFreeTXDUponTxDmaDone(pAd, QueIdx); + FreeNumber[QueIdx] = GET_TXRING_FREENO(pAd, QueIdx); + } +-#endif // RT2860 // + + // probe the Queue Head + pQueue = &pAd->TxSwQueue[QueIdx]; +@@ -1183,12 +1167,10 @@ VOID RTMPDeQueuePacket( + Status = STAHardTransmit(pAd, pTxBlk, QueIdx); + #endif // CONFIG_STA_SUPPORT // + +-#ifdef RT2860 + DEQUEUE_UNLOCK(&pAd->irq_lock, bIntContext, IrqFlags); + // static rate also need NICUpdateFifoStaCounters() function. + //if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED)) + NICUpdateFifoStaCounters(pAd); +-#endif // RT2860 // + } + + RT28XX_STOP_DEQUEUE(pAd, QueIdx, IrqFlags); +@@ -1767,7 +1749,6 @@ PQUEUE_HEADER RTMPCheckTxSwQueue( + } + + +-#ifdef RT2860 + BOOLEAN RTMPFreeTXDUponTxDmaDone( + IN PRTMP_ADAPTER pAd, + IN UCHAR QueIdx) +@@ -2312,7 +2293,6 @@ VOID DBGPRINT_RX_RING( + DBGPRINT_RAW(RT_DEBUG_TRACE,(" RxSwReadIdx [%d]=", AC0freeIdx)); + DBGPRINT_RAW(RT_DEBUG_TRACE,(" pending-NDIS=%ld\n", pAd->RalinkCounters.PendingNdisPacketCount)); + } +-#endif // RT2860 // + + /* + ======================================================================== +@@ -2637,9 +2617,7 @@ MAC_TABLE_ENTRY *MacTableInsertEntry( + pEntry->AuthMode = pAd->StaCfg.AuthMode; + pEntry->WepStatus = pAd->StaCfg.WepStatus; + pEntry->PrivacyFilter = Ndis802_11PrivFilterAcceptAll; +-#ifdef RT2860 + AsicRemovePairwiseKeyEntry(pAd, pEntry->apidx, (UCHAR)i); +-#endif // RT2860 // + } + #endif // CONFIG_STA_SUPPORT // + } +@@ -2790,7 +2768,7 @@ BOOLEAN MacTableDeleteEntry( + } + else + { +- printk("\n%s: Impossible Wcid = %d !!!!!\n", __FUNCTION__, wcid); ++ printk("\n%s: Impossible Wcid = %d !!!!!\n", __func__, wcid); + } + } + +@@ -2826,9 +2804,7 @@ VOID MacTableReset( + + for (i=1; iMacTab.Content[i].ValidAsCLI == TRUE) + { + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/cmm_info.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/cmm_info.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/cmm_info.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/cmm_info.c 2009-08-27 12:44:31.000000000 +0100 +@@ -814,7 +814,6 @@ INT Show_DescInfo_Proc( + IN PRTMP_ADAPTER pAd, + IN PUCHAR arg) + { +-#ifdef RT2860 + INT i, QueIdx=0; + PRT28XX_RXD_STRUC pRxD; + PTXD_STRUC pTxD; +@@ -845,7 +844,6 @@ INT Show_DescInfo_Proc( + hex_dump("Rx Descriptor", (char *)pRxD, 16); + printk("pRxD->DDONE = %x\n", pRxD->DDONE); + } +-#endif // RT2860 // + + return TRUE; + } +@@ -1803,9 +1801,7 @@ VOID RTMPAddWcidAttributeEntry( + } + + // For key index and ext IV bit, so only need to update the position(offset+3). +-#ifdef RT2860 + RTMP_IO_WRITE8(pAd, offset+3, IVEIV); +-#endif // RT2860 // + + DBGPRINT(RT_DEBUG_TRACE,("RTMPAddWcidAttributeEntry: WCID #%d, KeyIndex #%d, Alg=%s\n",Wcid, KeyIdx, CipherName[CipherAlg])); + DBGPRINT(RT_DEBUG_TRACE,(" WCIDAttri = 0x%x \n", WCIDAttri)); +@@ -2039,7 +2035,7 @@ VOID RTMPIoctlGetMacTable( + wrq->u.data.length = sizeof(RT_802_11_MAC_TABLE); + if (copy_to_user(wrq->u.data.pointer, &MacTab, wrq->u.data.length)) + { +- DBGPRINT(RT_DEBUG_TRACE, ("%s: copy_to_user() fail\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s: copy_to_user() fail\n", __func__)); + } + + msg = (CHAR *) kmalloc(sizeof(CHAR)*(MAX_LEN_OF_MAC_TABLE*MAC_LINE_LEN), MEM_ALLOC_FLAG); +@@ -2827,9 +2823,7 @@ INT Set_OpMode_Proc( + + Value = simple_strtol(arg, 0, 10); + +-#ifdef RT2860 + if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE)) +-#endif // RT2860 // + { + DBGPRINT(RT_DEBUG_ERROR, ("Can not switch operate mode on interface up !! \n")); + return FALSE; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/cmm_sync.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/cmm_sync.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/cmm_sync.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/cmm_sync.c 2009-08-27 12:44:31.000000000 +0100 +@@ -470,7 +470,7 @@ VOID ScanNextChannel( + { + // BBP and RF are not accessible in PS mode, we has to wake them up first + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) +- AsicForceWakeup(pAd, TRUE); ++ AsicForceWakeup(pAd, FROM_TX); + + // leave PSM during scanning. otherwise we may lost ProbeRsp & BEACON + if (pAd->StaCfg.Psm == PWR_SAVE) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/cmm_wpa.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/cmm_wpa.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/cmm_wpa.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/cmm_wpa.c 2009-08-27 12:44:31.000000000 +0100 +@@ -39,8 +39,10 @@ + // WPA OUI + UCHAR OUI_WPA_NONE_AKM[4] = {0x00, 0x50, 0xF2, 0x00}; + UCHAR OUI_WPA_VERSION[4] = {0x00, 0x50, 0xF2, 0x01}; ++UCHAR OUI_WPA_WEP40[4] = {0x00, 0x50, 0xF2, 0x01}; + UCHAR OUI_WPA_TKIP[4] = {0x00, 0x50, 0xF2, 0x02}; + UCHAR OUI_WPA_CCMP[4] = {0x00, 0x50, 0xF2, 0x04}; ++UCHAR OUI_WPA_WEP104[4] = {0x00, 0x50, 0xF2, 0x05}; + UCHAR OUI_WPA_8021X_AKM[4] = {0x00, 0x50, 0xF2, 0x01}; + UCHAR OUI_WPA_PSK_AKM[4] = {0x00, 0x50, 0xF2, 0x02}; + // WPA2 OUI +@@ -49,6 +51,7 @@ UCHAR OUI_WPA2_TKIP[4] = {0 + UCHAR OUI_WPA2_CCMP[4] = {0x00, 0x0F, 0xAC, 0x04}; + UCHAR OUI_WPA2_8021X_AKM[4] = {0x00, 0x0F, 0xAC, 0x01}; + UCHAR OUI_WPA2_PSK_AKM[4] = {0x00, 0x0F, 0xAC, 0x02}; ++UCHAR OUI_WPA2_WEP104[4] = {0x00, 0x0F, 0xAC, 0x05}; + // MSA OUI + UCHAR OUI_MSA_8021X_AKM[4] = {0x00, 0x0F, 0xAC, 0x05}; // Not yet final - IEEE 802.11s-D1.06 + UCHAR OUI_MSA_PSK_AKM[4] = {0x00, 0x0F, 0xAC, 0x06}; // Not yet final - IEEE 802.11s-D1.06 +@@ -367,6 +370,24 @@ static VOID RTMPInsertRsnIeCipher( + break; + } + ++#ifdef CONFIG_STA_SUPPORT ++ if ((pAd->OpMode == OPMODE_STA) && ++ (pAd->StaCfg.GroupCipher != Ndis802_11Encryption2Enabled) && ++ (pAd->StaCfg.GroupCipher != Ndis802_11Encryption3Enabled)) ++ { ++ UINT GroupCipher = pAd->StaCfg.GroupCipher; ++ switch(GroupCipher) ++ { ++ case Ndis802_11GroupWEP40Enabled: ++ NdisMoveMemory(pRsnie_cipher->mcast, OUI_WPA2_WEP40, 4); ++ break; ++ case Ndis802_11GroupWEP104Enabled: ++ NdisMoveMemory(pRsnie_cipher->mcast, OUI_WPA2_WEP104, 4); ++ break; ++ } ++ } ++#endif // CONFIG_STA_SUPPORT // ++ + // swap for big-endian platform + pRsnie_cipher->version = cpu2le16(pRsnie_cipher->version); + pRsnie_cipher->ucount = cpu2le16(pRsnie_cipher->ucount); +@@ -427,11 +448,28 @@ static VOID RTMPInsertRsnIeCipher( + break; + } + ++#ifdef CONFIG_STA_SUPPORT ++ if ((pAd->OpMode == OPMODE_STA) && ++ (pAd->StaCfg.GroupCipher != Ndis802_11Encryption2Enabled) && ++ (pAd->StaCfg.GroupCipher != Ndis802_11Encryption3Enabled)) ++ { ++ UINT GroupCipher = pAd->StaCfg.GroupCipher; ++ switch(GroupCipher) ++ { ++ case Ndis802_11GroupWEP40Enabled: ++ NdisMoveMemory(pRsnie_cipher->mcast, OUI_WPA_WEP40, 4); ++ break; ++ case Ndis802_11GroupWEP104Enabled: ++ NdisMoveMemory(pRsnie_cipher->mcast, OUI_WPA_WEP104, 4); ++ break; ++ } ++ } ++#endif // CONFIG_STA_SUPPORT // ++ + // swap for big-endian platform + pRsnie_cipher->version = cpu2le16(pRsnie_cipher->version); + pRsnie_cipher->ucount = cpu2le16(pRsnie_cipher->ucount); + } +- + } + + /* +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/dfs.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/dfs.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/dfs.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/dfs.c 2009-08-27 12:44:31.000000000 +0100 +@@ -428,7 +428,7 @@ INT Set_ChMovingTime_Proc( + + pAd->CommonCfg.RadarDetect.ChMovingTime = Value; + +- DBGPRINT(RT_DEBUG_TRACE, ("%s:: %d\n", __FUNCTION__, ++ DBGPRINT(RT_DEBUG_TRACE, ("%s:: %d\n", __func__, + pAd->CommonCfg.RadarDetect.ChMovingTime)); + + return TRUE; +@@ -444,7 +444,7 @@ INT Set_LongPulseRadarTh_Proc( + + pAd->CommonCfg.RadarDetect.LongPulseRadarTh = Value; + +- DBGPRINT(RT_DEBUG_TRACE, ("%s:: %d\n", __FUNCTION__, ++ DBGPRINT(RT_DEBUG_TRACE, ("%s:: %d\n", __func__, + pAd->CommonCfg.RadarDetect.LongPulseRadarTh)); + + return TRUE; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/mlme.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/mlme.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/mlme.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/mlme.c 2009-08-27 12:44:31.000000000 +0100 +@@ -527,7 +527,6 @@ NDIS_STATUS MlmeInit( + + + #ifdef CONFIG_STA_SUPPORT +-#ifdef RT2860 + IF_DEV_CONFIG_OPMODE_ON_STA(pAd) + { + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) +@@ -537,7 +536,6 @@ NDIS_STATUS MlmeInit( + RTMPInitTimer(pAd, &pAd->Mlme.RadioOnOffTimer, GET_TIMER_FUNCTION(RadioOnExec), pAd, FALSE); + } + } +-#endif // RT2860 // + #endif // CONFIG_STA_SUPPORT // + + } while (FALSE); +@@ -711,13 +709,11 @@ VOID MlmeHalt( + RTMPCancelTimer(&pAd->MlmeAux.AuthTimer, &Cancelled); + RTMPCancelTimer(&pAd->MlmeAux.BeaconTimer, &Cancelled); + RTMPCancelTimer(&pAd->MlmeAux.ScanTimer, &Cancelled); +-#ifdef RT2860 + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) + { + RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled); + RTMPCancelTimer(&pAd->Mlme.RadioOnOffTimer, &Cancelled); + } +-#endif // RT2860 // + + #ifdef QOS_DLS_SUPPORT + for (i=0; iStaCfg.WepStatus)); ++ //If the STA security setting is OPEN or WEP, pAd->StaCfg.WpaSupplicantUP = 0. ++ //If the STA security setting is WPAPSK or WPA2PSK, pAd->StaCfg.WpaSupplicantUP = 1. ++ if(pAd->StaCfg.WepStatus<2) ++ { ++ pAd->StaCfg.WpaSupplicantUP = 0; ++ } ++ else ++ { ++ pAd->StaCfg.WpaSupplicantUP = 1; ++ } ++ + #ifdef CONFIG_STA_SUPPORT +-#ifdef RT2860 + IF_DEV_CONFIG_OPMODE_ON_STA(pAd) + { + // If Hardware controlled Radio enabled, we have to check GPIO pin2 every 2 second. + // Move code to here, because following code will return when radio is off +- if ((pAd->Mlme.PeriodicRound % (MLME_TASK_EXEC_MULTIPLE * 2) == 0) && (pAd->StaCfg.bHardwareRadio == TRUE) && ++ if ((pAd->Mlme.PeriodicRound % (MLME_TASK_EXEC_MULTIPLE * 2) == 0) && ++ (pAd->StaCfg.bHardwareRadio == TRUE) && ++ (RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_START_UP)) && + (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) && +- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) && +- (pAd->bPCIclkOff == FALSE)) ++ (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS))) + { + UINT32 data = 0; + + // Read GPIO pin2 as Hardware controlled radio state +- RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &data); ++ RTMP_IO_FORCE_READ32(pAd, GPIO_CTRL_CFG, &data); + if (data & 0x04) + { + pAd->StaCfg.bHwRadio = TRUE; +@@ -849,7 +858,6 @@ VOID MlmePeriodicExec( + } + } + } +-#endif // RT2860 // + #endif // CONFIG_STA_SUPPORT // + + // Do nothing if the driver is starting halt state. +@@ -860,6 +868,45 @@ VOID MlmePeriodicExec( + fRTMP_ADAPTER_RESET_IN_PROGRESS)))) + return; + ++ IF_DEV_CONFIG_OPMODE_ON_STA(pAd) ++ { ++ if ((pAd->RalinkCounters.LastReceivedByteCount == pAd->RalinkCounters.ReceivedByteCount) && (pAd->StaCfg.bRadio == TRUE)) ++ { ++ // If ReceiveByteCount doesn't change, increase SameRxByteCount by 1. ++ pAd->SameRxByteCount++; ++ } ++ else ++ pAd->SameRxByteCount = 0; ++ ++ // If after BBP, still not work...need to check to reset PBF&MAC. ++ if (pAd->SameRxByteCount == 702) ++ { ++ pAd->SameRxByteCount = 0; ++ AsicResetPBF(pAd); ++ AsicResetMAC(pAd); ++ } ++ ++ // If SameRxByteCount keeps happens for 2 second in infra mode, or for 60 seconds in idle mode. ++ if (((INFRA_ON(pAd)) && (pAd->SameRxByteCount > 20)) || ((IDLE_ON(pAd)) && (pAd->SameRxByteCount > 600))) ++ { ++ if ((pAd->StaCfg.bRadio == TRUE) && (pAd->SameRxByteCount < 700)) ++ { ++ DBGPRINT(RT_DEBUG_TRACE, ("---> SameRxByteCount = %lu !!!!!!!!!!!!!!! \n", pAd->SameRxByteCount)); ++ pAd->SameRxByteCount = 700; ++ AsicResetBBP(pAd); ++ } ++ } ++ ++ // Update lastReceiveByteCount. ++ pAd->RalinkCounters.LastReceivedByteCount = pAd->RalinkCounters.ReceivedByteCount; ++ ++ if ((pAd->CheckDmaBusyCount > 3) && (IDLE_ON(pAd))) ++ { ++ pAd->CheckDmaBusyCount = 0; ++ AsicResetFromDMABusy(pAd); ++ } ++ } ++ + RT28XX_MLME_PRE_SANITY_CHECK(pAd); + + #ifdef RALINK_ATE +@@ -1022,9 +1069,7 @@ VOID MlmePeriodicExec( + #ifdef CONFIG_STA_SUPPORT + IF_DEV_CONFIG_OPMODE_ON_STA(pAd) + { +-#ifdef RT2860 + if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST) && (pAd->bPCIclkOff == FALSE)) +-#endif // RT2860 // + { + // When Adhoc beacon is enabled and RTS/CTS is enabled, there is a chance that hardware MAC FSM will run into a deadlock + // and sending CTS-to-self over and over. +@@ -1081,6 +1126,19 @@ VOID STAMlmePeriodicExec( + pAd->StaCfg.bBlockAssoc = FALSE; + } + ++ //Baron 2008/07/10 ++ //printk("Baron_Test:\t%s", RTMPGetRalinkEncryModeStr(pAd->StaCfg.WepStatus)); ++ //If the STA security setting is OPEN or WEP, pAd->StaCfg.WpaSupplicantUP = 0. ++ //If the STA security setting is WPAPSK or WPA2PSK, pAd->StaCfg.WpaSupplicantUP = 1. ++ if(pAd->StaCfg.WepStatus<2) ++ { ++ pAd->StaCfg.WpaSupplicantUP = 0; ++ } ++ else ++ { ++ pAd->StaCfg.WpaSupplicantUP = 1; ++ } ++ + if ((pAd->PreMediaState != pAd->IndicateMediaState) && (pAd->CommonCfg.bWirelessEvent)) + { + if (pAd->IndicateMediaState == NdisMediaStateConnected) +@@ -1090,6 +1148,15 @@ VOID STAMlmePeriodicExec( + pAd->PreMediaState = pAd->IndicateMediaState; + } + ++ if ((pAd->OpMode == OPMODE_STA) && (IDLE_ON(pAd)) && ++ (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) && ++ (pAd->Mlme.SyncMachine.CurrState == SYNC_IDLE) && ++ (pAd->Mlme.CntlMachine.CurrState == CNTL_IDLE) && ++ (RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_START_UP)) && ++ (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF))) ++ { ++ RT28xxPciAsicRadioOff(pAd, GUI_IDLE_POWER_SAVE, 0); ++ } + + + +@@ -2781,7 +2848,7 @@ VOID MlmeCheckPsmChange( + if (INFRA_ON(pAd) && + (PowerMode != Ndis802_11PowerModeCAM) && + (pAd->StaCfg.Psm == PWR_ACTIVE) && +- (pAd->Mlme.CntlMachine.CurrState == CNTL_IDLE)) ++ RTMP_TEST_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP)) + { + NdisGetSystemUpTime(&pAd->Mlme.LastSendNULLpsmTime); + pAd->RalinkCounters.RxCountSinceLastNULL = 0; +@@ -4065,7 +4132,9 @@ VOID BssTableSsidSort( + continue; + + // check group cipher +- if (pAd->StaCfg.WepStatus < pInBss->WPA.GroupCipher) ++ if ((pAd->StaCfg.WepStatus < pInBss->WPA.GroupCipher) && ++ (pInBss->WPA.GroupCipher != Ndis802_11GroupWEP40Enabled) && ++ (pInBss->WPA.GroupCipher != Ndis802_11GroupWEP104Enabled)) + continue; + + // check pairwise cipher, skip if none matched +@@ -4084,7 +4153,9 @@ VOID BssTableSsidSort( + continue; + + // check group cipher +- if (pAd->StaCfg.WepStatus < pInBss->WPA2.GroupCipher) ++ if ((pAd->StaCfg.WepStatus < pInBss->WPA.GroupCipher) && ++ (pInBss->WPA2.GroupCipher != Ndis802_11GroupWEP40Enabled) && ++ (pInBss->WPA2.GroupCipher != Ndis802_11GroupWEP104Enabled)) + continue; + + // check pairwise cipher, skip if none matched +@@ -4371,8 +4442,10 @@ VOID BssCipherParse( + switch (*pTmp) + { + case 1: +- case 5: // Although WEP is not allowed in WPA related auth mode, we parse it anyway +- pBss->WPA.GroupCipher = Ndis802_11Encryption1Enabled; ++ pBss->WPA.GroupCipher = Ndis802_11GroupWEP40Enabled; ++ break; ++ case 5: ++ pBss->WPA.GroupCipher = Ndis802_11GroupWEP104Enabled; + break; + case 2: + pBss->WPA.GroupCipher = Ndis802_11Encryption2Enabled; +@@ -4489,8 +4562,10 @@ VOID BssCipherParse( + switch (pCipher->Type) + { + case 1: +- case 5: // Although WEP is not allowed in WPA related auth mode, we parse it anyway +- pBss->WPA2.GroupCipher = Ndis802_11Encryption1Enabled; ++ pBss->WPA2.GroupCipher = Ndis802_11GroupWEP40Enabled; ++ break; ++ case 5: ++ pBss->WPA2.GroupCipher = Ndis802_11GroupWEP104Enabled; + break; + case 2: + pBss->WPA2.GroupCipher = Ndis802_11Encryption2Enabled; +@@ -4953,16 +5028,13 @@ BOOLEAN MlmeDequeue( + VOID MlmeRestartStateMachine( + IN PRTMP_ADAPTER pAd) + { +-#ifdef RT2860 + MLME_QUEUE_ELEM *Elem = NULL; +-#endif // RT2860 // + #ifdef CONFIG_STA_SUPPORT + BOOLEAN Cancelled; + #endif // CONFIG_STA_SUPPORT // + + DBGPRINT(RT_DEBUG_TRACE, ("MlmeRestartStateMachine \n")); + +-#ifdef RT2860 + NdisAcquireSpinLock(&pAd->Mlme.TaskLock); + if(pAd->Mlme.bRunning) + { +@@ -4990,7 +5062,6 @@ VOID MlmeRestartStateMachine( + DBGPRINT_ERR(("MlmeRestartStateMachine: MlmeQueue empty\n")); + } + } +-#endif // RT2860 // + + #ifdef CONFIG_STA_SUPPORT + IF_DEV_CONFIG_OPMODE_ON_STA(pAd) +@@ -5039,12 +5110,10 @@ VOID MlmeRestartStateMachine( + } + #endif // CONFIG_STA_SUPPORT // + +-#ifdef RT2860 + // Remove running state + NdisAcquireSpinLock(&pAd->Mlme.TaskLock); + pAd->Mlme.bRunning = FALSE; + NdisReleaseSpinLock(&pAd->Mlme.TaskLock); +-#endif // RT2860 // + } + + /*! \brief test if the MLME Queue is empty +@@ -6149,6 +6218,12 @@ VOID AsicAdjustTxPower( + ULONG TxPwr[5]; + CHAR Value; + ++ if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) ++ || (pAd->bPCIclkOff == TRUE) ++ || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF) ++ || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS)) ++ return; ++ + if (pAd->CommonCfg.BBPCurrentBW == BW_40) + { + if (pAd->CommonCfg.CentralChannel > 14) +@@ -6493,10 +6568,10 @@ VOID AsicForceSleep( + */ + VOID AsicForceWakeup( + IN PRTMP_ADAPTER pAd, +- IN BOOLEAN bFromTx) ++ IN UCHAR Level) + { + DBGPRINT(RT_DEBUG_TRACE, ("--> AsicForceWakeup \n")); +- RT28XX_STA_FORCE_WAKEUP(pAd, bFromTx); ++ RT28XX_STA_FORCE_WAKEUP(pAd, Level); + } + #endif // CONFIG_STA_SUPPORT // + /* +@@ -6710,7 +6785,6 @@ VOID AsicEnableIbssSync( + csr9.field.bTsfTicking = 0; + RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, csr9.word); + +-#ifdef RT2860 + // move BEACON TXD and frame content to on-chip memory + ptr = (PUCHAR)&pAd->BeaconTxWI; + for (i=0; iCommonCfg.BeaconPeriod << 4; // ASIC register in units of 1/16 TU +@@ -7097,9 +7170,7 @@ VOID AsicAddSharedKeyEntry( + { + ULONG offset; //, csr0; + SHAREDKEY_MODE_STRUC csr1; +-#ifdef RT2860 + INT i; +-#endif // RT2860 // + + DBGPRINT(RT_DEBUG_TRACE, ("AsicAddSharedKeyEntry BssIndex=%d, KeyIdx=%d\n", BssIndex,KeyIdx)); + //============================================================================================ +@@ -7121,7 +7192,6 @@ VOID AsicAddSharedKeyEntry( + // + // fill key material - key + TX MIC + RX MIC + // +-#ifdef RT2860 + offset = SHARED_KEY_TABLE_BASE + (4*BssIndex + KeyIdx)*HW_KEY_ENTRY_SIZE; + for (i=0; iTxTsc; + UCHAR CipherAlg = pCipherKey->CipherAlg; + SHAREDKEY_MODE_STRUC csr1; +-#ifdef RT2860 + UCHAR i; +-#endif // RT2860 // + + DBGPRINT(RT_DEBUG_TRACE, ("==> AsicAddKeyEntry\n")); + // +@@ -7337,7 +7404,6 @@ VOID AsicAddKeyEntry( + // 2.) Set Key to Asic + // + //for (i = 0; i < KeyLen; i++) +-#ifdef RT2860 + for (i = 0; i < MAX_LEN_OF_PEER_KEY; i++) + { + RTMP_IO_WRITE8(pAd, offset + i, pKey[i]); +@@ -7363,7 +7429,6 @@ VOID AsicAddKeyEntry( + RTMP_IO_WRITE8(pAd, offset + i, pRxMic[i]); + } + } +-#endif // RT2860 // + + + // +@@ -7372,7 +7437,6 @@ VOID AsicAddKeyEntry( + // + if (bTxKey) + { +-#ifdef RT2860 + offset = MAC_IVEIV_TABLE_BASE + (WCID * HW_IVEIV_ENTRY_SIZE); + // + // Write IV +@@ -7395,7 +7459,6 @@ VOID AsicAddKeyEntry( + { + RTMP_IO_WRITE8(pAd, offset + i, pTxtsc[i + 2]); + } +-#endif // RT2860 // + + AsicUpdateWCIDAttribute(pAd, WCID, BssIndex, CipherAlg, bUsePairewiseKeyTable); + } +@@ -7461,12 +7524,10 @@ VOID AsicAddPairwiseKeyEntry( + + // EKEY + offset = PAIRWISE_KEY_TABLE_BASE + (WCID * HW_KEY_ENTRY_SIZE); +-#ifdef RT2860 + for (i=0; i= 100) + { +-#ifdef RT2860 + #ifdef RALINK_ATE + if (pAd->ate.bFWLoading == TRUE) + { +@@ -7583,14 +7637,33 @@ BOOLEAN AsicSendCommandToMcu( + } + else + #endif // RALINK_ATE // +-#endif // RT2860 // + { ++ UINT32 Data; ++ ++ // Reset DMA ++ RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &Data); ++ Data |= 0x2; ++ RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, Data); ++ ++ // After Reset DMA, DMA index will become Zero. So Driver need to reset all ring indexs too. ++ // Reset DMA/CPU ring index ++ RTMPRingCleanUp(pAd, QID_AC_BK); ++ RTMPRingCleanUp(pAd, QID_AC_BE); ++ RTMPRingCleanUp(pAd, QID_AC_VI); ++ RTMPRingCleanUp(pAd, QID_AC_VO); ++ RTMPRingCleanUp(pAd, QID_HCCA); ++ RTMPRingCleanUp(pAd, QID_MGMT); ++ RTMPRingCleanUp(pAd, QID_RX); ++ ++ // Clear Reset ++ RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &Data); ++ Data &= 0xfffffffd; ++ RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, Data); + DBGPRINT_ERR(("H2M_MAILBOX still hold by MCU. command fail\n")); + } +- return FALSE; ++ //return FALSE; + } + +-#ifdef RT2860 + #ifdef RALINK_ATE + else if (pAd->ate.bFWLoading == TRUE) + { +@@ -7600,7 +7673,6 @@ BOOLEAN AsicSendCommandToMcu( + j = 0; + } + #endif // RALINK_ATE // +-#endif // RT2860 // + + H2MMailbox.field.Owner = 1; // pass ownership to MCU + H2MMailbox.field.CmdToken = Token; +@@ -7619,7 +7691,6 @@ BOOLEAN AsicSendCommandToMcu( + return TRUE; + } + +-#ifdef RT2860 + BOOLEAN AsicCheckCommanOk( + IN PRTMP_ADAPTER pAd, + IN UCHAR Command) +@@ -7684,7 +7755,6 @@ BOOLEAN AsicCheckCommanOk( + + return FALSE; + } +-#endif // RT2860 // + + /* + ======================================================================== +@@ -8096,10 +8166,8 @@ VOID AsicEvaluateRxAnt( + } + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3); + #ifdef CONFIG_STA_SUPPORT +-#ifdef RT2860 + IF_DEV_CONFIG_OPMODE_ON_STA(pAd) + pAd->StaCfg.BBPR3 = BBPR3; +-#endif // RT2860 // + #endif // CONFIG_STA_SUPPORT // + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED) + ) +@@ -8211,9 +8279,7 @@ VOID AsicRxAntEvalTimeout( + BBPR3 |= (0x0); + } + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3); +-#ifdef RT2860 +- pAd->StaCfg.BBPR3 = BBPR3; +-#endif // RT2860 // ++ pAd->StaCfg.BBPR3 = BBPR3; + } + + #endif // CONFIG_STA_SUPPORT // +@@ -8439,10 +8505,7 @@ VOID AsicStaBbpTuning( + && (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED) + ) + && !(OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) +-#ifdef RT2860 +- && (pAd->bPCIclkOff == FALSE) +-#endif // RT2860 // +- ) ++ && (pAd->bPCIclkOff == FALSE)) + { + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R66, &OrigR66Value); + R66 = OrigR66Value; +@@ -8518,6 +8581,106 @@ VOID AsicStaBbpTuning( + + } + } ++ ++VOID AsicResetFromDMABusy( ++ IN PRTMP_ADAPTER pAd) ++{ ++ UINT32 Data; ++ BOOLEAN bCtrl = FALSE; ++ ++ DBGPRINT(RT_DEBUG_TRACE, ("---> AsicResetFromDMABusy !!!!!!!!!!!!!!!!!!!!!!! \n")); ++ ++ // Be sure restore link control value so we can write register. ++ RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP); ++ if (RTMP_TEST_PSFLAG(pAd, fRTMP_PS_SET_PCI_CLK_OFF_COMMAND)) ++ { ++ DBGPRINT(RT_DEBUG_TRACE,("AsicResetFromDMABusy==>\n")); ++ RTMPPCIeLinkCtrlValueRestore(pAd, RESTORE_HALT); ++ RTMPusecDelay(6000); ++ pAd->bPCIclkOff = FALSE; ++ bCtrl = TRUE; ++ } ++ // Reset DMA ++ RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &Data); ++ Data |= 0x2; ++ RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, Data); ++ ++ // After Reset DMA, DMA index will become Zero. So Driver need to reset all ring indexs too. ++ // Reset DMA/CPU ring index ++ RTMPRingCleanUp(pAd, QID_AC_BK); ++ RTMPRingCleanUp(pAd, QID_AC_BE); ++ RTMPRingCleanUp(pAd, QID_AC_VI); ++ RTMPRingCleanUp(pAd, QID_AC_VO); ++ RTMPRingCleanUp(pAd, QID_HCCA); ++ RTMPRingCleanUp(pAd, QID_MGMT); ++ RTMPRingCleanUp(pAd, QID_RX); ++ ++ // Clear Reset ++ RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &Data); ++ Data &= 0xfffffffd; ++ RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, Data); ++ ++ // If in Radio off, should call RTMPPCIePowerLinkCtrl again. ++ if ((bCtrl == TRUE) && (pAd->StaCfg.bRadio == FALSE)) ++ RTMPPCIeLinkCtrlSetting(pAd, 3); ++ ++ RTMP_SET_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP); ++ RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST | fRTMP_ADAPTER_HALT_IN_PROGRESS); ++ DBGPRINT(RT_DEBUG_TRACE, ("<--- AsicResetFromDMABusy !!!!!!!!!!!!!!!!!!!!!!! \n")); ++} ++ ++VOID AsicResetBBP( ++ IN PRTMP_ADAPTER pAd) ++{ ++ DBGPRINT(RT_DEBUG_TRACE, ("---> Asic HardReset BBP !!!!!!!!!!!!!!!!!!!!!!! \n")); ++ ++ RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0); ++ RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x2); ++ RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0xc); ++ ++ // After hard-reset BBP, initialize all BBP values. ++ NICRestoreBBPValue(pAd); ++ DBGPRINT(RT_DEBUG_TRACE, ("<--- Asic HardReset BBP !!!!!!!!!!!!!!!!!!!!!!! \n")); ++} ++ ++VOID AsicResetMAC( ++ IN PRTMP_ADAPTER pAd) ++{ ++ ULONG Data; ++ ++ DBGPRINT(RT_DEBUG_TRACE, ("---> AsicResetMAC !!!! \n")); ++ RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &Data); ++ Data |= 0x4; ++ RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, Data); ++ Data &= 0xfffffffb; ++ RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, Data); ++ ++ DBGPRINT(RT_DEBUG_TRACE, ("<--- AsicResetMAC !!!! \n")); ++} ++ ++VOID AsicResetPBF( ++ IN PRTMP_ADAPTER pAd) ++{ ++ ULONG Value1, Value2; ++ ULONG Data; ++ ++ RTMP_IO_READ32(pAd, TXRXQ_PCNT, &Value1); ++ RTMP_IO_READ32(pAd, PBF_DBG, &Value2); ++ ++ Value2 &= 0xff; ++ // sum should be equals to 0xff, which is the total buffer size. ++ if ((Value1 + Value2) < 0xff) ++ { ++ DBGPRINT(RT_DEBUG_TRACE, ("---> Asic HardReset PBF !!!! \n")); ++ RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &Data); ++ Data |= 0x8; ++ RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, Data); ++ Data &= 0xfffffff7; ++ RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, Data); ++ ++ DBGPRINT(RT_DEBUG_TRACE, ("<--- Asic HardReset PBF !!!! \n")); ++ } ++} + #endif // CONFIG_STA_SUPPORT // + + VOID RTMPSetAGCInitValue( +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/rtmp_init.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/rtmp_init.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/rtmp_init.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/rtmp_init.c 2009-08-27 12:44:31.000000000 +0100 +@@ -39,6 +39,7 @@ + */ + #include "../rt_config.h" + #include "firmware.h" ++#include + + UCHAR BIT8[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80}; + ULONG BIT32[] = {0x00000001, 0x00000002, 0x00000004, 0x00000008, +@@ -89,20 +90,6 @@ const unsigned short ccitt_16Table[] = { + #define ByteCRC16(v, crc) \ + (unsigned short)((crc << 8) ^ ccitt_16Table[((crc >> 8) ^ (v)) & 255]) + +-unsigned char BitReverse(unsigned char x) +-{ +- int i; +- unsigned char Temp=0; +- for(i=0; ; i++) +- { +- if(x & 0x80) Temp |= 0x80; +- if(i==7) break; +- x <<= 1; +- Temp >>= 1; +- } +- return Temp; +-} +- + // + // BBP register initialization set + // +@@ -162,9 +149,7 @@ RTMP_REG_PAIR MACRegTable[] = { + {GF20_PROT_CFG, 0x01744004}, // set 19:18 --> Short NAV for MIMO PS + {GF40_PROT_CFG, 0x03F44084}, + {MM20_PROT_CFG, 0x01744004}, +-#ifdef RT2860 + {MM40_PROT_CFG, 0x03F54084}, +-#endif // RT2860 // + {TXOP_CTRL_CFG, 0x0000583f, /*0x0000243f*/ /*0x000024bf*/}, //Extension channel backoff. + {TX_RTS_CFG, 0x00092b20}, + {EXP_ACK_TIME, 0x002400ca}, // default value +@@ -201,9 +186,7 @@ RTMP_REG_PAIR STAMACRegTable[] = { + #define FIRMWAREIMAGEV1_LENGTH 0x1000 + #define FIRMWAREIMAGEV2_LENGTH 0x1000 + +-#ifdef RT2860 + #define FIRMWARE_MINOR_VERSION 2 +-#endif // RT2860 // + + + /* +@@ -261,9 +244,7 @@ NDIS_STATUS RTMPAllocAdapterBlock( + + // Init spin locks + NdisAllocateSpinLock(&pAd->MgmtRingLock); +-#ifdef RT2860 + NdisAllocateSpinLock(&pAd->RxRingLock); +-#endif // RT2860 // + + for (index =0 ; index < NUM_OF_TX_RING; index++) + { +@@ -1568,10 +1549,7 @@ VOID NICInitAsicFromEEPROM( + pAd->LedCntl.word = 0x01; + pAd->Led1 = 0x5555; + pAd->Led2 = 0x2221; +- +-#ifdef RT2860 + pAd->Led3 = 0xA9F8; +-#endif // RT2860 // + } + + AsicSendCommandToMcu(pAd, 0x52, 0xff, (UCHAR)pAd->Led1, (UCHAR)(pAd->Led1 >> 8)); +@@ -1607,12 +1585,10 @@ VOID NICInitAsicFromEEPROM( + else + { + RTMPSetLED(pAd, LED_RADIO_ON); +-#ifdef RT2860 + AsicSendCommandToMcu(pAd, 0x30, 0xff, 0xff, 0x02); + AsicSendCommandToMcu(pAd, 0x31, PowerWakeCID, 0x00, 0x00); + // 2-1. wait command ok. + AsicCheckCommanOk(pAd, PowerWakeCID); +-#endif // RT2860 // + } + } + #endif // CONFIG_STA_SUPPORT // +@@ -1690,10 +1666,8 @@ NDIS_STATUS NICInitializeAdapter( + { + NDIS_STATUS Status = NDIS_STATUS_SUCCESS; + WPDMA_GLO_CFG_STRUC GloCfg; +-#ifdef RT2860 + UINT32 Value; + DELAY_INT_CFG_STRUC IntCfg; +-#endif // RT2860 // + ULONG i =0, j=0; + AC_TXOP_CSR0_STRUC csr0; + +@@ -1732,11 +1706,9 @@ retry: + + // asic simulation sequence put this ahead before loading firmware. + // pbf hardware reset +-#ifdef RT2860 + RTMP_IO_WRITE32(pAd, WPDMA_RST_IDX, 0x1003f); // 0x10000 for reset rx, 0x3f resets all 6 tx rings. + RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0xe1f); + RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0xe00); +-#endif // RT2860 // + + // Initialze ASIC for TX & Rx operation + if (NICInitializeAsic(pAd , bHardReset) != NDIS_STATUS_SUCCESS) +@@ -1750,7 +1722,6 @@ retry: + } + + +-#ifdef RT2860 + // Write AC_BK base address register + Value = RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_BK].Cell[0].AllocPa); + RTMP_IO_WRITE32(pAd, TX_BASE_PTR1, Value); +@@ -1823,7 +1794,6 @@ retry: + // Write RX_RING_CSR register + Value = RX_RING_SIZE; + RTMP_IO_WRITE32(pAd, RX_MAX_CNT, Value); +-#endif // RT2860 // + + + // WMM parameter +@@ -1842,7 +1812,6 @@ retry: + RTMP_IO_WRITE32(pAd, WMM_TXOP1_CFG, csr0.word); + + +-#ifdef RT2860 + // 3. Set DMA global configuration except TX_DMA_EN and RX_DMA_EN bits: + i = 0; + do +@@ -1861,7 +1830,6 @@ retry: + + IntCfg.word = 0; + RTMP_IO_WRITE32(pAd, DELAY_INT_CFG, IntCfg.word); +-#endif // RT2860 // + + + // reset action +@@ -1902,7 +1870,6 @@ NDIS_STATUS NICInitializeAsic( + + DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitializeAsic\n")); + +-#ifdef RT2860 + if (bHardReset == TRUE) + { + RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x3); +@@ -1927,7 +1894,6 @@ NDIS_STATUS NICInitializeAsic( + } + } + #endif // CONFIG_STA_SUPPORT // +-#endif // RT2860 // + + + // +@@ -2054,6 +2020,131 @@ NDIS_STATUS NICInitializeAsic( + return NDIS_STATUS_SUCCESS; + } + ++ ++VOID NICRestoreBBPValue( ++ IN PRTMP_ADAPTER pAd) ++{ ++ UCHAR index; ++ UCHAR Value = 0; ++ ULONG Data; ++ ++ DBGPRINT(RT_DEBUG_TRACE, ("---> NICRestoreBBPValue !!!!!!!!!!!!!!!!!!!!!!! \n")); ++ // Initialize BBP register to default value (rtmp_init.c) ++ for (index = 0; index < NUM_BBP_REG_PARMS; index++) ++ { ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBPRegTable[index].Register, BBPRegTable[index].Value); ++ } ++ // copy from (rtmp_init.c) ++ if (pAd->MACVersion == 0x28600100) ++ { ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16); ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x12); ++ } ++ ++ // copy from (connect.c LinkUp function) ++ if (INFRA_ON(pAd)) ++ { ++ // Change to AP channel ++ if ((pAd->CommonCfg.CentralChannel > pAd->CommonCfg.Channel) && (pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth == BW_40)) ++ { ++ // Must using 40MHz. ++ pAd->CommonCfg.BBPCurrentBW = BW_40; ++ AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel, FALSE); ++ AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel); ++ ++ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &Value); ++ Value &= (~0x18); ++ Value |= 0x10; ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, Value); ++ ++ // RX : control channel at lower ++ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value); ++ Value &= (~0x20); ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value); ++ // Record BBPR3 setting, But don't keep R Antenna # information. ++ pAd->StaCfg.BBPR3 = Value; ++ ++ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Data); ++ Data &= 0xfffffffe; ++ RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Data); ++ ++ if (pAd->MACVersion == 0x28600100) ++ { ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A); ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16); ++ DBGPRINT(RT_DEBUG_TRACE, ("!!!rt2860C !!! \n" )); ++ } ++ ++ DBGPRINT(RT_DEBUG_TRACE, ("!!!40MHz Lower LINK UP !!! Control Channel at Below. Central = %d \n", pAd->CommonCfg.CentralChannel )); ++ } ++ else if ((pAd->CommonCfg.CentralChannel < pAd->CommonCfg.Channel) && (pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth == BW_40)) ++ { ++ // Must using 40MHz. ++ pAd->CommonCfg.BBPCurrentBW = BW_40; ++ AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel, FALSE); ++ AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel); ++ ++ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &Value); ++ Value &= (~0x18); ++ Value |= 0x10; ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, Value); ++ ++ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Data); ++ Data |= 0x1; ++ RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Data); ++ ++ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value); ++ Value |= (0x20); ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value); ++ // Record BBPR3 setting, But don't keep R Antenna # information. ++ pAd->StaCfg.BBPR3 = Value; ++ ++ if (pAd->MACVersion == 0x28600100) ++ { ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A); ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16); ++ DBGPRINT(RT_DEBUG_TRACE, ("!!!rt2860C !!! \n" )); ++ } ++ ++ DBGPRINT(RT_DEBUG_TRACE, ("!!!40MHz Upper LINK UP !!! Control Channel at UpperCentral = %d \n", pAd->CommonCfg.CentralChannel )); ++ } ++ else ++ { ++ pAd->CommonCfg.BBPCurrentBW = BW_20; ++ AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE); ++ AsicLockChannel(pAd, pAd->CommonCfg.Channel); ++ ++ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &Value); ++ Value &= (~0x18); ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, Value); ++ ++ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Data); ++ Data &= 0xfffffffe; ++ RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Data); ++ ++ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value); ++ Value &= (~0x20); ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value); ++ // Record BBPR3 setting, But don't keep R Antenna # information. ++ pAd->StaCfg.BBPR3 = Value; ++ ++ if (pAd->MACVersion == 0x28600100) ++ { ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16); ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x08); ++ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x11); ++ DBGPRINT(RT_DEBUG_TRACE, ("!!!rt2860C !!! \n" )); ++ } ++ ++ DBGPRINT(RT_DEBUG_TRACE, ("!!!20MHz LINK UP !!! \n" )); ++ } ++ } ++ ++ DBGPRINT(RT_DEBUG_TRACE, ("<--- NICRestoreBBPValue !!!!!!!!!!!!!!!!!!!!!!! \n")); ++} ++ + /* + ======================================================================== + +@@ -2555,7 +2646,7 @@ NDIS_STATUS NICLoadFirmware( + #ifdef BIN_IN_FILE + #define NICLF_DEFAULT_USE() \ + flg_default_firm_use = TRUE; \ +- printk("%s - Use default firmware!\n", __FUNCTION__); ++ printk("%s - Use default firmware!\n", __func__); + + NDIS_STATUS Status = NDIS_STATUS_SUCCESS; + PUCHAR src; +@@ -2570,7 +2661,7 @@ NDIS_STATUS NICLoadFirmware( + BOOLEAN flg_default_firm_use = FALSE; + + +- DBGPRINT(RT_DEBUG_TRACE, ("===> %s\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE, ("===> %s\n", __func__)); + + /* init */ + pFirmwareImage = NULL; +@@ -2593,7 +2684,7 @@ NDIS_STATUS NICLoadFirmware( + if (pFirmwareImage == NULL) + { + /* allocate fail, use default firmware array in firmware.h */ +- printk("%s - Allocate memory fail!\n", __FUNCTION__); ++ printk("%s - Allocate memory fail!\n", __func__); + NICLF_DEFAULT_USE(); + } + else +@@ -2614,7 +2705,7 @@ NDIS_STATUS NICLoadFirmware( + if (IS_ERR(srcf)) + { + printk("%s - Error %ld opening %s\n", +- __FUNCTION__, -PTR_ERR(srcf), src); ++ __func__, -PTR_ERR(srcf), src); + NICLF_DEFAULT_USE(); + break; + } /* End of if */ +@@ -2622,7 +2713,7 @@ NDIS_STATUS NICLoadFirmware( + /* the object must have a read method */ + if ((srcf->f_op == NULL) || (srcf->f_op->read == NULL)) + { +- printk("%s - %s does not have a write method\n", __FUNCTION__, src); ++ printk("%s - %s does not have a write method\n", __func__, src); + NICLF_DEFAULT_USE(); + break; + } /* End of if */ +@@ -2636,7 +2727,7 @@ NDIS_STATUS NICLoadFirmware( + if (FileLength != MAX_FIRMWARE_IMAGE_SIZE) + { + printk("%s: error file length (=%d) in RT2860AP.BIN\n", +- __FUNCTION__, FileLength); ++ __func__, FileLength); + NICLF_DEFAULT_USE(); + break; + } +@@ -2648,18 +2739,18 @@ NDIS_STATUS NICLoadFirmware( + + /* calculate firmware CRC */ + for(i=0; i<(MAX_FIRMWARE_IMAGE_SIZE-2); i++, ptr++) +- crc = ByteCRC16(BitReverse(*ptr), crc); ++ crc = ByteCRC16(bitrev8(*ptr), crc); + /* End of for */ + + if ((pFirmwareImage[MAX_FIRMWARE_IMAGE_SIZE-2] != \ +- (UCHAR)BitReverse((UCHAR)(crc>>8))) || ++ (UCHAR)bitrev8((UCHAR)(crc>>8))) || + (pFirmwareImage[MAX_FIRMWARE_IMAGE_SIZE-1] != \ +- (UCHAR)BitReverse((UCHAR)crc))) ++ (UCHAR)bitrev8((UCHAR)crc))) + { + /* CRC fail */ + printk("%s: CRC = 0x%02x 0x%02x " + "error, should be 0x%02x 0x%02x\n", +- __FUNCTION__, ++ __func__, + pFirmwareImage[MAX_FIRMWARE_IMAGE_SIZE-2], + pFirmwareImage[MAX_FIRMWARE_IMAGE_SIZE-1], + (UCHAR)(crc>>8), (UCHAR)(crc)); +@@ -2678,7 +2769,7 @@ NDIS_STATUS NICLoadFirmware( + ((FIRMWARE_MAJOR_VERSION << 8) + + FIRMWARE_MINOR_VERSION)) + { +- printk("%s: firmware version too old!\n", __FUNCTION__); ++ printk("%s: firmware version too old!\n", __func__); + NICLF_DEFAULT_USE(); + break; + } /* End of if */ +@@ -2783,7 +2874,7 @@ NDIS_STATUS NICLoadFirmware( + } /* End of if */ + + DBGPRINT(RT_DEBUG_TRACE, +- ("<=== %s (status=%d)\n", __FUNCTION__, Status)); ++ ("<=== %s (status=%d)\n", __func__, Status)); + return Status; + } /* End of NICLoadFirmware */ + +@@ -3041,11 +3132,10 @@ VOID UserCfgInit( + pAd->CommonCfg.BBPCurrentBW = BW_20; + + pAd->LedCntl.word = 0; +-#ifdef RT2860 + pAd->LedIndicatorStregth = 0; + pAd->RLnkCtrlOffset = 0; + pAd->HostLnkCtrlOffset = 0; +-#endif // RT2860 // ++ pAd->CheckDmaBusyCount = 0; + + pAd->bAutoTxAgcA = FALSE; // Default is OFF + pAd->bAutoTxAgcG = FALSE; // Default is OFF +@@ -3305,9 +3395,7 @@ VOID UserCfgInit( + pAd->ate.bRxFer = 0; + pAd->ate.bQATxStart = FALSE; + pAd->ate.bQARxStart = FALSE; +-#ifdef RT2860 + pAd->ate.bFWLoading = FALSE; +-#endif // RT2860 // + #ifdef RALINK_28xx_QA + //pAd->ate.Repeat = 0; + pAd->ate.TxStatus = 0; +@@ -3317,11 +3405,9 @@ VOID UserCfgInit( + + + pAd->CommonCfg.bWiFiTest = FALSE; +-#ifdef RT2860 +- pAd->bPCIclkOff = FALSE; +-#endif // RT2860 // +- ++ pAd->bPCIclkOff = FALSE; + ++ RTMP_SET_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP); + DBGPRINT(RT_DEBUG_TRACE, ("<-- UserCfgInit\n")); + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/spectrum.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/spectrum.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/common/spectrum.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/common/spectrum.c 2009-08-27 12:44:31.000000000 +0100 +@@ -49,7 +49,7 @@ VOID MeasureReqTabInit( + if (pAd->CommonCfg.pMeasureReqTab) + NdisZeroMemory(pAd->CommonCfg.pMeasureReqTab, sizeof(MEASURE_REQ_TAB)); + else +- DBGPRINT(RT_DEBUG_ERROR, ("%s Fail to alloc memory for pAd->CommonCfg.pMeasureReqTab.\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s Fail to alloc memory for pAd->CommonCfg.pMeasureReqTab.\n", __func__)); + + return; + } +@@ -77,7 +77,7 @@ static PMEASURE_REQ_ENTRY MeasureReqLook + + if (pTab == NULL) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s: pMeasureReqTab doesn't exist.\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s: pMeasureReqTab doesn't exist.\n", __func__)); + return NULL; + } + +@@ -114,7 +114,7 @@ static PMEASURE_REQ_ENTRY MeasureReqInse + + if(pTab == NULL) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s: pMeasureReqTab doesn't exist.\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s: pMeasureReqTab doesn't exist.\n", __func__)); + return NULL; + } + +@@ -175,7 +175,7 @@ static PMEASURE_REQ_ENTRY MeasureReqInse + else + { + pEntry = NULL; +- DBGPRINT(RT_DEBUG_ERROR, ("%s: pMeasureReqTab tab full.\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s: pMeasureReqTab tab full.\n", __func__)); + } + + // add this Neighbor entry into HASH table +@@ -210,7 +210,7 @@ static VOID MeasureReqDelete( + + if(pTab == NULL) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s: pMeasureReqTab doesn't exist.\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s: pMeasureReqTab doesn't exist.\n", __func__)); + return; + } + +@@ -267,7 +267,7 @@ VOID TpcReqTabInit( + if (pAd->CommonCfg.pTpcReqTab) + NdisZeroMemory(pAd->CommonCfg.pTpcReqTab, sizeof(TPC_REQ_TAB)); + else +- DBGPRINT(RT_DEBUG_ERROR, ("%s Fail to alloc memory for pAd->CommonCfg.pTpcReqTab.\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s Fail to alloc memory for pAd->CommonCfg.pTpcReqTab.\n", __func__)); + + return; + } +@@ -295,7 +295,7 @@ static PTPC_REQ_ENTRY TpcReqLookUp( + + if (pTab == NULL) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s: pTpcReqTab doesn't exist.\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s: pTpcReqTab doesn't exist.\n", __func__)); + return NULL; + } + +@@ -333,7 +333,7 @@ static PTPC_REQ_ENTRY TpcReqInsert( + + if(pTab == NULL) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s: pTpcReqTab doesn't exist.\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s: pTpcReqTab doesn't exist.\n", __func__)); + return NULL; + } + +@@ -394,7 +394,7 @@ static PTPC_REQ_ENTRY TpcReqInsert( + else + { + pEntry = NULL; +- DBGPRINT(RT_DEBUG_ERROR, ("%s: pTpcReqTab tab full.\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s: pTpcReqTab tab full.\n", __func__)); + } + + // add this Neighbor entry into HASH table +@@ -429,7 +429,7 @@ static VOID TpcReqDelete( + + if(pTab == NULL) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s: pTpcReqTab doesn't exist.\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s: pTpcReqTab doesn't exist.\n", __func__)); + return; + } + +@@ -782,7 +782,7 @@ VOID EnqueueMeasurementReq( + NStatus = MlmeAllocateMemory(pAd, (PVOID)&pOutBuffer); //Get an unused nonpaged memory + if(NStatus != NDIS_STATUS_SUCCESS) + { +- DBGPRINT(RT_DEBUG_TRACE, ("%s() allocate memory failed \n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s() allocate memory failed \n", __func__)); + return; + } + NdisMoveMemory(pOutBuffer, (PCHAR)&ActHdr, sizeof(HEADER_802_11)); +@@ -844,7 +844,7 @@ VOID EnqueueMeasurementRep( + NStatus = MlmeAllocateMemory(pAd, (PVOID)&pOutBuffer); //Get an unused nonpaged memory + if(NStatus != NDIS_STATUS_SUCCESS) + { +- DBGPRINT(RT_DEBUG_TRACE, ("%s() allocate memory failed \n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s() allocate memory failed \n", __func__)); + return; + } + NdisMoveMemory(pOutBuffer, (PCHAR)&ActHdr, sizeof(HEADER_802_11)); +@@ -898,7 +898,7 @@ VOID EnqueueTPCReq( + NStatus = MlmeAllocateMemory(pAd, (PVOID)&pOutBuffer); //Get an unused nonpaged memory + if(NStatus != NDIS_STATUS_SUCCESS) + { +- DBGPRINT(RT_DEBUG_TRACE, ("%s() allocate memory failed \n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s() allocate memory failed \n", __func__)); + return; + } + NdisMoveMemory(pOutBuffer, (PCHAR)&ActHdr, sizeof(HEADER_802_11)); +@@ -950,7 +950,7 @@ VOID EnqueueTPCRep( + NStatus = MlmeAllocateMemory(pAd, (PVOID)&pOutBuffer); //Get an unused nonpaged memory + if(NStatus != NDIS_STATUS_SUCCESS) + { +- DBGPRINT(RT_DEBUG_TRACE, ("%s() allocate memory failed \n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s() allocate memory failed \n", __func__)); + return; + } + NdisMoveMemory(pOutBuffer, (PCHAR)&ActHdr, sizeof(HEADER_802_11)); +@@ -1003,7 +1003,7 @@ VOID EnqueueChSwAnn( + NStatus = MlmeAllocateMemory(pAd, (PVOID)&pOutBuffer); //Get an unused nonpaged memory + if(NStatus != NDIS_STATUS_SUCCESS) + { +- DBGPRINT(RT_DEBUG_TRACE, ("%s() allocate memory failed \n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s() allocate memory failed \n", __func__)); + return; + } + NdisMoveMemory(pOutBuffer, (PCHAR)&ActHdr, sizeof(HEADER_802_11)); +@@ -1596,7 +1596,7 @@ static VOID PeerMeasureReportAction( + + if ((pMeasureReportInfo = kmalloc(sizeof(MEASURE_RPI_REPORT), GFP_ATOMIC)) == NULL) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s unable to alloc memory for measure report buffer (size=%d).\n", __FUNCTION__, sizeof(MEASURE_RPI_REPORT))); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s unable to alloc memory for measure report buffer (size=%zu).\n", __func__, sizeof(MEASURE_RPI_REPORT))); + return; + } + +@@ -1705,7 +1705,7 @@ static VOID PeerTpcRepAction( + { + TpcReqDelete(pAd, pEntry->DialogToken); + DBGPRINT(RT_DEBUG_TRACE, ("%s: DialogToken=%x, TxPwr=%d, LinkMargin=%d\n", +- __FUNCTION__, DialogToken, TpcRepInfo.TxPwr, TpcRepInfo.LinkMargin)); ++ __func__, DialogToken, TpcRepInfo.TxPwr, TpcRepInfo.LinkMargin)); + } + } + +@@ -1821,7 +1821,7 @@ INT Set_MeasureReq_Proc( + MeasureReqType = simple_strtol(thisChar, 0, 16); + if (MeasureReqType > 3) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s: unknow MeasureReqType(%d)\n", __FUNCTION__, MeasureReqType)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s: unknow MeasureReqType(%d)\n", __func__, MeasureReqType)); + return TRUE; + } + break; +@@ -1833,10 +1833,10 @@ INT Set_MeasureReq_Proc( + ArgIdx++; + } + +- DBGPRINT(RT_DEBUG_TRACE, ("%s::Aid = %d, MeasureReqType=%d MeasureCh=%d\n", __FUNCTION__, Aid, MeasureReqType, MeasureCh)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::Aid = %d, MeasureReqType=%d MeasureCh=%d\n", __func__, Aid, MeasureReqType, MeasureCh)); + if (!VALID_WCID(Aid)) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s: unknow sta of Aid(%d)\n", __FUNCTION__, Aid)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s: unknow sta of Aid(%d)\n", __func__, Aid)); + return TRUE; + } + +@@ -1861,10 +1861,10 @@ INT Set_TpcReq_Proc( + + Aid = simple_strtol(arg, 0, 16); + +- DBGPRINT(RT_DEBUG_TRACE, ("%s::Aid = %d\n", __FUNCTION__, Aid)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::Aid = %d\n", __func__, Aid)); + if (!VALID_WCID(Aid)) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s: unknow sta of Aid(%d)\n", __FUNCTION__, Aid)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s: unknow sta of Aid(%d)\n", __func__, Aid)); + return TRUE; + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/config.mk linux-2.6.27.29-0.1.1/drivers/staging/rt2860/config.mk +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/config.mk 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/config.mk 2009-08-27 12:44:31.000000000 +0100 +@@ -108,10 +108,6 @@ ifeq ($(HAS_EXT_BUILD_CHANNEL_LIST),y) + WFLAGS += -DEXT_BUILD_CHANNEL_LIST + endif + +-ifeq ($(CHIPSET),2860) +-WFLAGS +=-DRT2860 +-endif +- + ifeq ($(CHIPSET),2870) + WFLAGS +=-DRT2870 + endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/Makefile linux-2.6.27.29-0.1.1/drivers/staging/rt2860/Makefile +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/Makefile 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/Makefile 2009-08-27 12:44:31.000000000 +0100 +@@ -2,7 +2,6 @@ obj-$(CONFIG_RT2860) += rt2860sta.o + + # TODO: all of these should be removed + EXTRA_CFLAGS += -DLINUX -DAGGREGATION_SUPPORT -DPIGGYBACK_SUPPORT -DWMM_SUPPORT +-EXTRA_CFLAGS += -DRT2860 + EXTRA_CFLAGS += -DCONFIG_STA_SUPPORT + EXTRA_CFLAGS += -DDBG + EXTRA_CFLAGS += -DDOT11_N_SUPPORT +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/oid.h linux-2.6.27.29-0.1.1/drivers/staging/rt2860/oid.h +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/oid.h 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/oid.h 2009-08-27 12:44:31.000000000 +0100 +@@ -544,6 +544,8 @@ typedef enum _NDIS_802_11_WEP_STATUS + Ndis802_11Encryption3KeyAbsent, + Ndis802_11Encryption4Enabled, // TKIP or AES mix + Ndis802_11Encryption4KeyAbsent, ++ Ndis802_11GroupWEP40Enabled, ++ Ndis802_11GroupWEP104Enabled, + } NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS, + NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS; + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt2860.h linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt2860.h +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt2860.h 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt2860.h 2009-08-27 12:44:31.000000000 +0100 +@@ -46,18 +46,10 @@ + Status = NDIS_STATUS_SUCCESS; + + /* function declarations */ +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + #define IRQ_HANDLE_TYPE irqreturn_t +-#else +-#define IRQ_HANDLE_TYPE void +-#endif + + IRQ_HANDLE_TYPE +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)) + rt2860_interrupt(int irq, void *dev_instance); +-#else +-rt2860_interrupt(int irq, void *dev_instance, struct pt_regs *regs); +-#endif + + /* ----------------- Frimware Related MACRO ----------------- */ + #define RT28XX_WRITE_FIRMWARE(_pAd, _pFwImage, _FwLen) \ +@@ -237,12 +229,10 @@ rt2860_interrupt(int irq, void *dev_inst + #define RTMP_MSI_DISABLE(_pAd) + #endif // PCI_MSI_SUPPORT // + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) + #define SA_SHIRQ IRQF_SHARED +-#endif + + #define RT28XX_IRQ_REQUEST(net_dev) \ +-{ PRTMP_ADAPTER _pAd = (PRTMP_ADAPTER)((net_dev)->priv); \ ++{ PRTMP_ADAPTER _pAd = (PRTMP_ADAPTER)((net_dev)->ml_priv); \ + POS_COOKIE _pObj = (POS_COOKIE)(_pAd->OS_Cookie); \ + RTMP_MSI_ENABLE(_pAd); \ + if ((retval = request_irq(_pObj->pci_dev->irq, \ +@@ -251,20 +241,12 @@ rt2860_interrupt(int irq, void *dev_inst + printk("RT2860: request_irq ERROR(%d)\n", retval); \ + return retval; } } + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + #define RT28XX_IRQ_RELEASE(net_dev) \ +-{ PRTMP_ADAPTER _pAd = (PRTMP_ADAPTER)((net_dev)->priv); \ ++{ PRTMP_ADAPTER _pAd = (PRTMP_ADAPTER)((net_dev)->ml_priv); \ + POS_COOKIE _pObj = (POS_COOKIE)(_pAd->OS_Cookie); \ + synchronize_irq(_pObj->pci_dev->irq); \ + free_irq(_pObj->pci_dev->irq, (net_dev)); \ + RTMP_MSI_DISABLE(_pAd); } +-#else +-#define RT28XX_IRQ_RELEASE(net_dev) \ +-{ PRTMP_ADAPTER _pAd = (PRTMP_ADAPTER)((net_dev)->priv); \ +- POS_COOKIE _pObj = (POS_COOKIE)(_pAd->OS_Cookie); \ +- free_irq(_pObj->pci_dev->irq, (net_dev)); \ +- RTMP_MSI_DISABLE(_pAd); } +-#endif + + #define RT28XX_IRQ_INIT(pAd) \ + { pAd->int_enable_reg = ((DELAYINTMASK) | \ +@@ -333,8 +315,8 @@ rt2860_interrupt(int irq, void *dev_inst + reg16 = cpu2le16(Configuration); \ + pci_write_config_word(pci_dev, offset, reg16); \ + +-#define RT28XX_STA_FORCE_WAKEUP(pAd, bFromTx) \ +- RT28xxPciStaAsicForceWakeup(pAd, bFromTx); ++#define RT28XX_STA_FORCE_WAKEUP(pAd, Level) \ ++ RT28xxPciStaAsicForceWakeup(pAd, Level); + + #define RT28XX_STA_SLEEP_THEN_AUTO_WAKEUP(pAd, TbttNumToNextWakeUp) \ + RT28xxPciStaAsicSleepThenAutoWakeup(pAd, TbttNumToNextWakeUp); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt28xx.h linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt28xx.h +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt28xx.h 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt28xx.h 2009-08-27 12:44:31.000000000 +0100 +@@ -1670,11 +1670,9 @@ typedef struct _HW_WCID_ENTRY { // 8-by + #define E2PROM_CSR 0x0004 + #define IO_CNTL_CSR 0x77d0 + +-#ifdef RT2860 + // 8051 firmware image for RT2860 - base address = 0x4000 + #define FIRMWARE_IMAGE_BASE 0x2000 + #define MAX_FIRMWARE_IMAGE_SIZE 0x2000 // 8kbyte +-#endif // RT2860 // + + + // ================================================================ +@@ -2029,7 +2027,6 @@ typedef struct PACKED _TXWI_STRUC { + // + // Rx descriptor format, Rx Ring + // +-#ifdef RT2860 + #ifdef RT_BIG_ENDIAN + typedef struct PACKED _RXD_STRUC { + // Word 0 +@@ -2098,7 +2095,6 @@ typedef struct PACKED _RXD_STRUC { + UINT32 Rsv1:13; + } RXD_STRUC, *PRXD_STRUC, RT28XX_RXD_STRUC, *PRT28XX_RXD_STRUC; + #endif +-#endif // RT2860 // + // + // RXWI wireless information format, in PBF. invisible in driver. + // +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_ate.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_ate.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_ate.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_ate.c 2009-08-27 12:44:31.000000000 +0100 +@@ -68,7 +68,6 @@ static int CheckMCSValid( + IN UCHAR Mode, + IN UCHAR Mcs); + +-#ifdef RT2860 + static VOID ATEWriteTxWI( + IN PRTMP_ADAPTER pAd, + IN PTXWI_STRUC pOutTxWI, +@@ -87,7 +86,6 @@ static VOID ATEWriteTxWI( + IN UCHAR Txopmode, + IN BOOLEAN CfAck, + IN HTTRANSMIT_SETTING *pTransmit); +-#endif // RT2860 // + + + static VOID SetJapanFilter( +@@ -95,7 +93,6 @@ static VOID SetJapanFilter( + + /*=========================end of prototype=========================*/ + +-#ifdef RT2860 + static INT TxDmaBusy( + IN PRTMP_ADAPTER pAd) + { +@@ -153,7 +150,6 @@ static VOID RtmpDmaEnable( + + return; + } +-#endif // RT2860 // + + + static VOID BbpSoftReset( +@@ -291,7 +287,7 @@ static INT ATETxPwrHandler( + Bbp94 = BBPR94_DEFAULT; + } + +- ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R=%ld, BBP_R94=%d)\n", __FUNCTION__, TxPower, R, Bbp94)); ++ ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R=%ld, BBP_R94=%d)\n", __func__, TxPower, R, Bbp94)); + } + else// 5.5 GHz + { +@@ -318,7 +314,7 @@ static INT ATETxPwrHandler( + R = (ULONG) TxPower; + } + +- ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R=%lu)\n", __FUNCTION__, TxPower, R)); ++ ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R=%lu)\n", __func__, TxPower, R)); + } + + if (pAd->ate.Channel <= 14) +@@ -431,7 +427,7 @@ static INT ATETxPwrHandler( + Bbp94 = BBPR94_DEFAULT; + } + +- ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R3=%ld, BBP_R94=%d)\n", __FUNCTION__, TxPower, R, Bbp94)); ++ ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R3=%ld, BBP_R94=%d)\n", __func__, TxPower, R, Bbp94)); + + if (pAd->ate.Channel <= 14) + { +@@ -488,7 +484,6 @@ static INT ATETxPwrHandler( + TRUE if all parameters are OK, FALSE otherwise + ========================================================================== + */ +-#ifdef RT2860 + static INT ATECmdHandler( + IN PRTMP_ADAPTER pAd, + IN PUCHAR arg) +@@ -1297,7 +1292,6 @@ static INT ATECmdHandler( + + return TRUE; + } +-#endif // RT2860 // + /* */ + /* */ + /*=======================End of RT2860=======================*/ +@@ -2098,7 +2092,7 @@ INT Set_ATE_Load_E2P_Proc( + UINT32 FileLength = 0; + UINT32 value = simple_strtol(arg, 0, 10); + +- ATEDBGPRINT(RT_DEBUG_ERROR, ("===> %s (value=%d)\n\n", __FUNCTION__, value)); ++ ATEDBGPRINT(RT_DEBUG_ERROR, ("===> %s (value=%d)\n\n", __func__, value)); + + if (value > 0) + { +@@ -2122,14 +2116,14 @@ INT Set_ATE_Load_E2P_Proc( + + if (IS_ERR(srcf)) + { +- ate_print("%s - Error %ld opening %s\n", __FUNCTION__, -PTR_ERR(srcf), src); ++ ate_print("%s - Error %ld opening %s\n", __func__, -PTR_ERR(srcf), src); + break; + } + + /* the object must have a read method */ + if ((srcf->f_op == NULL) || (srcf->f_op->read == NULL)) + { +- ate_print("%s - %s does not have a read method\n", __FUNCTION__, src); ++ ate_print("%s - %s does not have a read method\n", __func__, src); + break; + } + +@@ -2142,7 +2136,7 @@ INT Set_ATE_Load_E2P_Proc( + if (FileLength != EEPROM_SIZE) + { + ate_print("%s: error file length (=%d) in e2p.bin\n", +- __FUNCTION__, FileLength); ++ __func__, FileLength); + break; + } + else +@@ -2174,7 +2168,7 @@ INT Set_ATE_Load_E2P_Proc( + current->fsuid = orgfsuid; + current->fsgid = orgfsgid; + } +- ATEDBGPRINT(RT_DEBUG_ERROR, ("<=== %s (ret=%d)\n", __FUNCTION__, ret)); ++ ATEDBGPRINT(RT_DEBUG_ERROR, ("<=== %s (ret=%d)\n", __func__, ret)); + + return ret; + +@@ -2187,12 +2181,12 @@ INT Set_ATE_Load_E2P_Proc( + USHORT WriteEEPROM[(EEPROM_SIZE/2)]; + struct iwreq *wrq = (struct iwreq *)arg; + +- ATEDBGPRINT(RT_DEBUG_TRACE, ("===> %s (wrq->u.data.length = %d)\n\n", __FUNCTION__, wrq->u.data.length)); ++ ATEDBGPRINT(RT_DEBUG_TRACE, ("===> %s (wrq->u.data.length = %d)\n\n", __func__, wrq->u.data.length)); + + if (wrq->u.data.length != EEPROM_SIZE) + { + ate_print("%s: error length (=%d) from host\n", +- __FUNCTION__, wrq->u.data.length); ++ __func__, wrq->u.data.length); + return FALSE; + } + else/* (wrq->u.data.length == EEPROM_SIZE) */ +@@ -2211,7 +2205,7 @@ INT Set_ATE_Load_E2P_Proc( + } while(FALSE); + } + +- ATEDBGPRINT(RT_DEBUG_TRACE, ("<=== %s\n", __FUNCTION__)); ++ ATEDBGPRINT(RT_DEBUG_TRACE, ("<=== %s\n", __func__)); + + return TRUE; + +@@ -2907,7 +2901,6 @@ VOID ATEAsicAdjustTxPower( + None + ======================================================================== + */ +-#ifdef RT2860 + static VOID ATEWriteTxWI( + IN PRTMP_ADAPTER pAd, + IN PTXWI_STRUC pOutTxWI, +@@ -2972,7 +2965,6 @@ static VOID ATEWriteTxWI( + + return; + } +-#endif // RT2860 // + + /* + ======================================================================== +@@ -3249,13 +3241,11 @@ VOID RTMPStationStart( + IN PRTMP_ADAPTER pAd) + { + ATEDBGPRINT(RT_DEBUG_TRACE, ("==> RTMPStationStart\n")); +-#ifdef RT2860 +- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE; ++epAd->Mlme.CntlMachine.CurrState = CNTL_IDLE; + // + // We did not cancel this timer when entering ATE mode. + // + // RTMPSetTimer(&pAd->Mlme.PeriodicTimer, MLME_TASK_EXEC_INTV); +-#endif // RT2860 // + ATEDBGPRINT(RT_DEBUG_TRACE, ("<== RTMPStationStart\n")); + } + #endif // CONFIG_STA_SUPPORT // +@@ -3268,7 +3258,6 @@ VOID RTMPStationStart( + This routine should only be used in ATE mode. + ========================================================================== + */ +-#ifdef RT2860 + static INT ATESetUpFrame( + IN PRTMP_ADAPTER pAd, + IN UINT32 TxIdx) +@@ -3353,7 +3342,7 @@ static INT ATESetUpFrame( + if (pPacket == NULL) + { + pAd->ate.TxCount = 0; +- ATEDBGPRINT(RT_DEBUG_TRACE, ("%s fail to alloc packet space.\n", __FUNCTION__)); ++ ATEDBGPRINT(RT_DEBUG_TRACE, ("%s fail to alloc packet space.\n", __func__)); + return -1; + } + pTxRing->Cell[TxIdx].pNextNdisPacket = pPacket; +@@ -3455,7 +3444,6 @@ static INT ATESetUpFrame( + /* */ + /* */ + /*=======================End of RT2860=======================*/ +-#endif // RT2860 // + + + VOID rt_ee_read_all(PRTMP_ADAPTER pAd, USHORT *Data) +@@ -3646,7 +3634,7 @@ VOID RtmpDoAte( + + Command_Id = ntohs(pRaCfg->command_id); + +- ATEDBGPRINT(RT_DEBUG_TRACE,("\n%s: Command_Id = 0x%04x !\n", __FUNCTION__, Command_Id)); ++ ATEDBGPRINT(RT_DEBUG_TRACE,("\n%s: Command_Id = 0x%04x !\n", __func__, Command_Id)); + + switch (Command_Id) + { +@@ -4578,9 +4566,7 @@ VOID RtmpDoAte( + { + if (pAdapter->ate.TxCount == 0) + { +-#ifdef RT2860 + pAdapter->ate.TxCount = 0xFFFFFFFF; +-#endif // RT2860 // + } + ATEDBGPRINT(RT_DEBUG_TRACE,("START TXFRAME\n")); + pAdapter->ate.bQATxStart = TRUE; +@@ -5375,7 +5361,6 @@ TX_START_ERROR: + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = ntohs(value); +-#ifdef RT2860 + /* TX_FRAME_COUNT == 0 means tx infinitely */ + if (value == 0) + { +@@ -5387,7 +5372,6 @@ TX_START_ERROR: + + } + else +-#endif // RT2860 // + { + sprintf((PCHAR)str, "%d", value); + Set_ATE_TX_COUNT_Proc(pAdapter, str); +@@ -5690,7 +5674,7 @@ BOOLEAN SyncTxRxConfig(PRTMP_ADAPTER pAd + pAd->ate.TxAntennaSel = 2; + break; + default: +- DBGPRINT(RT_DEBUG_TRACE, ("%s -- Sth. wrong! : return FALSE; \n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s -- Sth. wrong! : return FALSE; \n", __func__)); + return FALSE; + } + break;/* case BBP_R1 */ +@@ -5728,13 +5712,13 @@ BOOLEAN SyncTxRxConfig(PRTMP_ADAPTER pAd + pAd->ate.RxAntennaSel = 3; + break; + default: +- DBGPRINT(RT_DEBUG_ERROR, ("%s -- Impossible! : return FALSE; \n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s -- Impossible! : return FALSE; \n", __func__)); + return FALSE; + } + break;/* case BBP_R3 */ + + default: +- DBGPRINT(RT_DEBUG_ERROR, ("%s -- Sth. wrong! : return FALSE; \n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s -- Sth. wrong! : return FALSE; \n", __func__)); + return FALSE; + + } +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_ate.h linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_ate.h +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_ate.h 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_ate.h 2009-08-27 12:44:31.000000000 +0100 +@@ -31,12 +31,10 @@ + #ifndef UCOS + #define ate_print printk + #define ATEDBGPRINT DBGPRINT +-#ifdef RT2860 + #define EEPROM_SIZE 0x200 + #ifdef CONFIG_STA_SUPPORT + #define EEPROM_BIN_FILE_NAME "/etc/Wireless/RT2860STA/e2p.bin" + #endif // CONFIG_STA_SUPPORT // +-#endif // RT2860 // + + #else // !UCOS // + #define fATE_LOAD_EEPROM 0x0C43 +@@ -69,7 +67,6 @@ do{ int (*org_remote_display)(char *) + #define ATE_ON(_p) (((_p)->ate.Mode) != ATE_STOP) + + /* RT2880_iNIC will define "RT2860". */ +-#ifdef RT2860 + #define ATE_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) \ + { \ + BBP_CSR_CFG_STRUC BbpCsr; \ +@@ -131,10 +128,8 @@ do{ int (*org_remote_display)(char *) + ATEDBGPRINT(RT_DEBUG_ERROR, ("BBP write R%d fail\n", _I)); \ + } \ + } +-#endif // RT2860 // + + /* RT2880_iNIC will define RT2860. */ +-#ifdef RT2860 + #define EEPROM_SIZE 0x200 + /* iNIC has its own EEPROM_BIN_FILE_NAME */ + #ifndef UCOS +@@ -142,7 +137,6 @@ do{ int (*org_remote_display)(char *) + #define EEPROM_BIN_FILE_NAME "/etc/Wireless/RT2860STA/e2p.bin" + #endif // CONFIG_STA_SUPPORT // + #endif // !UCOS // +-#endif // RT2860 // + + + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_config.h linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_config.h +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_config.h 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_config.h 2009-08-27 12:44:31.000000000 +0100 +@@ -53,9 +53,7 @@ + #include "rtmp_def.h" + #include "rt28xx.h" + +-#ifdef RT2860 + #include "rt2860.h" +-#endif // RT2860 // + + + #include "oid.h" +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_linux.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_linux.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_linux.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_linux.c 2009-08-27 12:44:31.000000000 +0100 +@@ -48,10 +48,8 @@ BUILD_TIMER_FUNCTION(LeapAuthTimeout); + #endif + BUILD_TIMER_FUNCTION(StaQuickResponeForRateUpExec); + BUILD_TIMER_FUNCTION(WpaDisassocApAndBlockAssoc); +-#ifdef RT2860 + BUILD_TIMER_FUNCTION(PsPollWakeExec); + BUILD_TIMER_FUNCTION(RadioOnExec); +-#endif // RT2860 // + #ifdef QOS_DLS_SUPPORT + BUILD_TIMER_FUNCTION(DlsTimeoutAction); + #endif // QOS_DLS_SUPPORT // +@@ -293,9 +291,7 @@ VOID RTMPFreeAdapter( + + NdisFreeSpinLock(&pAd->MgmtRingLock); + +-#ifdef RT2860 + NdisFreeSpinLock(&pAd->RxRingLock); +-#endif // RT2860 // + + for (index =0 ; index < NUM_OF_TX_RING; index++) + { +@@ -406,7 +402,7 @@ NDIS_STATUS RTMPAllocateNdisPacket( + skb_put(GET_OS_PKT_TYPE(pPacket), HeaderLen+DataLen); + + RTMP_SET_PACKET_SOURCE(pPacket, PKTSRC_NDIS); +-// printk("%s : pPacket = %p, len = %d\n", __FUNCTION__, pPacket, GET_OS_PKT_LEN(pPacket)); ++// printk("%s : pPacket = %p, len = %d\n", __func__, pPacket, GET_OS_PKT_LEN(pPacket)); + *ppPacket = pPacket; + return NDIS_STATUS_SUCCESS; + } +@@ -773,13 +769,13 @@ VOID RTMPSendWirelessEvent( + + if (event_table_len == 0) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s : The type(%0x02x) is not valid.\n", __FUNCTION__, type)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s : The type(%0x02x) is not valid.\n", __func__, type)); + return; + } + + if (event >= event_table_len) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s : The event(%0x02x) is not valid.\n", __FUNCTION__, event)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s : The event(%0x02x) is not valid.\n", __func__, event)); + return; + } + +@@ -817,14 +813,14 @@ VOID RTMPSendWirelessEvent( + //send wireless event + wireless_send_event(pAd->net_dev, IWEVCUSTOM, &wrqu, pBuf); + +- //DBGPRINT(RT_DEBUG_TRACE, ("%s : %s\n", __FUNCTION__, pBuf)); ++ //DBGPRINT(RT_DEBUG_TRACE, ("%s : %s\n", __func__, pBuf)); + + kfree(pBuf); + } + else +- DBGPRINT(RT_DEBUG_ERROR, ("%s : Can't allocate memory for wireless event.\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s : Can't allocate memory for wireless event.\n", __func__)); + #else +- DBGPRINT(RT_DEBUG_ERROR, ("%s : The Wireless Extension MUST be v15 or newer.\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s : The Wireless Extension MUST be v15 or newer.\n", __func__)); + #endif /* WIRELESS_EXT >= 15 */ + } + +@@ -848,13 +844,13 @@ void send_monitor_packets( + ASSERT(pRxBlk->pRxPacket); + if (pRxBlk->DataSize < 10) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s : Size is too small! (%d)\n", __FUNCTION__, pRxBlk->DataSize)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s : Size is too small! (%d)\n", __func__, pRxBlk->DataSize)); + goto err_free_sk_buff; + } + + if (pRxBlk->DataSize + sizeof(wlan_ng_prism2_header) > RX_BUFFER_AGGRESIZE) + { +- DBGPRINT(RT_DEBUG_ERROR, ("%s : Size is too large! (%d)\n", __FUNCTION__, pRxBlk->DataSize + sizeof(wlan_ng_prism2_header))); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s : Size is too large! (%zu)\n", __func__, pRxBlk->DataSize + sizeof(wlan_ng_prism2_header))); + goto err_free_sk_buff; + } + +@@ -910,7 +906,7 @@ void send_monitor_packets( + + if (skb_headroom(pOSPkt) < (sizeof(wlan_ng_prism2_header)+ header_len)) { + if (pskb_expand_head(pOSPkt, (sizeof(wlan_ng_prism2_header) + header_len), 0, GFP_ATOMIC)) { +- DBGPRINT(RT_DEBUG_ERROR, ("%s : Reallocate header size of sk_buff fail!\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s : Reallocate header size of sk_buff fail!\n", __func__)); + goto err_free_sk_buff; + } //end if + } //end if +@@ -1005,35 +1001,14 @@ err_free_sk_buff: + + void rtmp_os_thread_init(PUCHAR pThreadName, PVOID pNotify) + { +- +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + daemonize(pThreadName /*"%s",pAd->net_dev->name*/); + + allow_signal(SIGTERM); + allow_signal(SIGKILL); + current->flags |= PF_NOFREEZE; +-#else +- unsigned long flags; +- +- daemonize(); +- reparent_to_init(); +- strcpy(current->comm, pThreadName); +- +- siginitsetinv(¤t->blocked, sigmask(SIGTERM) | sigmask(SIGKILL)); +- +- /* Allow interception of SIGKILL only +- * Don't allow other signals to interrupt the transmission */ +-#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) +- spin_lock_irqsave(¤t->sigmask_lock, flags); +- flush_signals(current); +- recalc_sigpending(current); +- spin_unlock_irqrestore(¤t->sigmask_lock, flags); +-#endif +-#endif + +- /* signal that we've started the thread */ ++ /* signal that we've started the thread */ + complete(pNotify); +- + } + + void RTMP_IndicateMediaState( +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_linux.h linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_linux.h +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_linux.h 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_linux.h 2009-08-27 12:44:31.000000000 +0100 +@@ -65,7 +65,6 @@ + #include + + +-#include + #include + + // load firmware +@@ -90,28 +89,22 @@ typedef int (*HARD_START_XMIT_FUNC)(stru + // add by kathy + + #ifdef CONFIG_STA_SUPPORT +-#ifdef RT2860 + #define STA_PROFILE_PATH "/etc/Wireless/RT2860STA/RT2860STA.dat" + #define STA_RTMP_FIRMWARE_FILE_NAME "/etc/Wireless/RT2860STA/RT2860STA.bin" + #define STA_NIC_DEVICE_NAME "RT2860STA" +-#define STA_DRIVER_VERSION "1.8.0.0" ++#define STA_DRIVER_VERSION "1.8.1.1" + #ifdef MULTIPLE_CARD_SUPPORT + #define CARD_INFO_PATH "/etc/Wireless/RT2860STA/RT2860STACard.dat" + #endif // MULTIPLE_CARD_SUPPORT // +-#endif // RT2860 // + + + #endif // CONFIG_STA_SUPPORT // + +-#ifdef RT2860 + #ifndef PCI_DEVICE + #define PCI_DEVICE(vend,dev) \ + .vendor = (vend), .device = (dev), \ + .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID + #endif // PCI_DEVICE // +-#endif // RT2860 // +- +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + + #define RTMP_TIME_AFTER(a,b) \ + (typecheck(unsigned long, (unsigned long)a) && \ +@@ -123,23 +116,15 @@ typedef int (*HARD_START_XMIT_FUNC)(stru + typecheck(unsigned long, (unsigned long)b) && \ + ((long)(a) - (long)(b) >= 0)) + #define RTMP_TIME_BEFORE(a,b) RTMP_TIME_AFTER_EQ(b,a) +-#else +-#define RTMP_TIME_AFTER(a,b) time_after(a, b) +-#endif + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + #define RT_MOD_INC_USE_COUNT() \ + if (!try_module_get(THIS_MODULE)) \ + { \ +- DBGPRINT(RT_DEBUG_ERROR, ("%s: cannot reserve module\n", __FUNCTION__)); \ ++ DBGPRINT(RT_DEBUG_ERROR, ("%s: cannot reserve module\n", __func__)); \ + return -1; \ + } + + #define RT_MOD_DEC_USE_COUNT() module_put(THIS_MODULE); +-#else +-#define RT_MOD_INC_USE_COUNT() MOD_INC_USE_COUNT; +-#define RT_MOD_DEC_USE_COUNT() MOD_DEC_USE_COUNT; +-#endif + + #define OS_HZ HZ + +@@ -171,21 +156,12 @@ typedef int (*HARD_START_XMIT_FUNC)(stru + #define NDIS_PACKET_TYPE_ALL_MULTICAST 3 + #endif // CONFIG_STA_SUPPORT // + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + typedef struct pid * THREAD_PID; + #define THREAD_PID_INIT_VALUE NULL + #define GET_PID(_v) find_get_pid(_v) + #define GET_PID_NUMBER(_v) pid_nr(_v) + #define CHECK_PID_LEGALITY(_pid) if (pid_nr(_pid) >= 0) + #define KILL_THREAD_PID(_A, _B, _C) kill_pid(_A, _B, _C) +-#else +-typedef pid_t THREAD_PID; +-#define THREAD_PID_INIT_VALUE -1 +-#define GET_PID(_v) _v +-#define GET_PID_NUMBER(_v) _v +-#define CHECK_PID_LEGALITY(_pid) if (_pid >= 0) +-#define KILL_THREAD_PID(_A, _B, _C) kill_proc(_A, _B, _C) +-#endif + + struct os_lock { + spinlock_t lock; +@@ -194,11 +170,9 @@ struct os_lock { + + + struct os_cookie { +-#ifdef RT2860 + struct pci_dev *pci_dev; + struct pci_dev *parent_pci_dev; + dma_addr_t pAd_pa; +-#endif // RT2860 // + + + struct tasklet_struct rx_done_task; +@@ -209,9 +183,7 @@ struct os_cookie { + struct tasklet_struct ac3_dma_done_task; + struct tasklet_struct hcca_dma_done_task; + struct tasklet_struct tbtt_task; +-#ifdef RT2860 + struct tasklet_struct fifo_statistic_full_task; +-#endif // RT2860 // + + + unsigned long apd_pid; //802.1x daemon pid +@@ -266,7 +238,6 @@ void linux_pci_unmap_single(void *handle + + #define RT2860_PCI_DEVICE_ID 0x0601 + +-#ifdef RT2860 + #define PCI_MAP_SINGLE(_handle, _ptr, _size, _sd_idx, _dir) \ + linux_pci_map_single(_handle, _ptr, _size, _sd_idx, _dir) + +@@ -281,7 +252,6 @@ void linux_pci_unmap_single(void *handle + + #define DEV_ALLOC_SKB(_length) \ + dev_alloc_skb(_length) +-#endif // RT2860 // + + + +@@ -401,7 +371,6 @@ extern ULONG RTDebugLevel; + spin_unlock_irqrestore((spinlock_t *)(__lock), ((unsigned long)__irqflag)); \ + } + +-#ifdef RT2860 + #if defined(INF_TWINPASS) || defined(INF_DANUBE) || defined(IKANOS_VX_1X0) + //Patch for ASIC turst read/write bug, needs to remove after metel fix + #define RTMP_IO_READ32(_A, _R, _pV) \ +@@ -413,6 +382,12 @@ extern ULONG RTDebugLevel; + (*_pV = SWAP32(*((UINT32 *)(_pV)))); \ + } \ + } ++#define RTMP_IO_FORCE_READ32(_A, _R, _pV) \ ++{ \ ++ (*_pV = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0))); \ ++ (*_pV = readl((void *)((_A)->CSRBaseAddress + (_R)))); \ ++ (*_pV = SWAP32(*((UINT32 *)(_pV)))); \ ++} + #define RTMP_IO_READ8(_A, _R, _pV) \ + { \ + (*_pV = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0))); \ +@@ -452,6 +427,11 @@ extern ULONG RTDebugLevel; + else \ + *_pV = 0; \ + } ++#define RTMP_IO_FORCE_READ32(_A, _R, _pV) \ ++{ \ ++ (*_pV = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0))); \ ++ (*_pV = readl((void *)((_A)->CSRBaseAddress + (_R)))); \ ++} + #define RTMP_IO_READ8(_A, _R, _pV) \ + { \ + (*_pV = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0))); \ +@@ -492,7 +472,6 @@ extern ULONG RTDebugLevel; + writew((_V), (PUSHORT)((_A)->CSRBaseAddress + (_R))); \ + } + #endif +-#endif // RT2860 // + + + #ifndef wait_event_interruptible_timeout +@@ -544,7 +523,6 @@ typedef void (*TIMER_FUNCTION)(unsigned + #define MlmeAllocateMemory(_pAd, _ppVA) os_alloc_mem(_pAd, _ppVA, MGMT_DMA_BUFFER_SIZE) + #define MlmeFreeMemory(_pAd, _pVA) os_free_mem(_pAd, _pVA) + +-#ifdef RT2860 + #define BUILD_TIMER_FUNCTION(_func) \ + void linux_##_func(unsigned long data) \ + { \ +@@ -554,7 +532,6 @@ void linux_##_func(unsigned long data) + if (pTimer->Repeat) \ + RTMP_OS_Add_Timer(&pTimer->TimerObj, pTimer->TimerValue); \ + } +-#endif // RT2860 // + + + +@@ -907,7 +884,6 @@ int rt28xx_packet_xmit(struct sk_buff *s + + void rtmp_os_thread_init(PUCHAR pThreadName, PVOID pNotify); + +-#ifdef RT2860 + #if !defined(PCI_CAP_ID_EXP) + #define PCI_CAP_ID_EXP 0x10 + #endif +@@ -921,6 +897,5 @@ void rtmp_os_thread_init(PUCHAR pThreadN + #endif + + #define PCIBUS_INTEL_VENDOR 0x8086 +-#endif // RT2860 // + + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_main_dev.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_main_dev.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_main_dev.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_main_dev.c 2009-08-27 12:44:31.000000000 +0100 +@@ -58,11 +58,7 @@ UINT32 CW_MAX_IN_BITS; + + char *mac = ""; // default 00:00:00:00:00:00 + char *hostname = ""; // default CMPC +-#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12) +-MODULE_PARM (mac, "s"); +-#else + module_param (mac, charp, 0); +-#endif + MODULE_PARM_DESC (mac, "rt28xx: wireless mac addr"); + + +@@ -75,9 +71,7 @@ extern void ba_reordering_resource_relea + #endif // DOT11_N_SUPPORT // + extern NDIS_STATUS NICLoadRateSwitchingParams(IN PRTMP_ADAPTER pAd); + +-#ifdef RT2860 + extern void init_thread_task(PRTMP_ADAPTER pAd); +-#endif // RT2860 // + + // public function prototype + INT __devinit rt28xx_probe(IN void *_dev_p, IN void *_dev_id_p, +@@ -87,13 +81,6 @@ INT __devinit rt28xx_probe(IN void *_dev + static int rt28xx_init(IN struct net_device *net_dev); + INT rt28xx_send_packets(IN struct sk_buff *skb_p, IN struct net_device *net_dev); + +-#if LINUX_VERSION_CODE <= 0x20402 // Red Hat 7.1 +-struct net_device *alloc_netdev( +- int sizeof_priv, +- const char *mask, +- void (*setup)(struct net_device *)); +-#endif // LINUX_VERSION_CODE // +- + static void CfgInitHook(PRTMP_ADAPTER pAd); + + #ifdef CONFIG_STA_SUPPORT +@@ -135,7 +122,7 @@ Note: + */ + int MainVirtualIF_close(IN struct net_device *net_dev) + { +- RTMP_ADAPTER *pAd = net_dev->priv; ++ RTMP_ADAPTER *pAd = net_dev->ml_priv; + + // Sanity check for pAd + if (pAd == NULL) +@@ -174,7 +161,7 @@ Note: + */ + int MainVirtualIF_open(IN struct net_device *net_dev) + { +- RTMP_ADAPTER *pAd = net_dev->priv; ++ RTMP_ADAPTER *pAd = net_dev->ml_priv; + + // Sanity check for pAd + if (pAd == NULL) +@@ -216,7 +203,7 @@ Note: + int rt28xx_close(IN PNET_DEV dev) + { + struct net_device * net_dev = (struct net_device *)dev; +- RTMP_ADAPTER *pAd = net_dev->priv; ++ RTMP_ADAPTER *pAd = net_dev->ml_priv; + BOOLEAN Cancelled = FALSE; + UINT32 i = 0; + +@@ -235,15 +222,13 @@ int rt28xx_close(IN PNET_DEV dev) + #ifdef CONFIG_STA_SUPPORT + IF_DEV_CONFIG_OPMODE_ON_STA(pAd) + { +-#ifdef RT2860 +- RTMPPCIeLinkCtrlValueRestore(pAd, RESTORE_CLOSE); +-#endif // RT2860 // +- + // If dirver doesn't wake up firmware here, + // NICLoadFirmware will hang forever when interface is up again. +- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) ++ if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) || ++ RTMP_SET_PSFLAG(pAd, fRTMP_PS_SET_PCI_CLK_OFF_COMMAND) || ++ RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF)) + { +- AsicForceWakeup(pAd, TRUE); ++ AsicForceWakeup(pAd, RTMP_HALT); + } + + #ifdef QOS_DLS_SUPPORT +@@ -323,9 +308,7 @@ int rt28xx_close(IN PNET_DEV dev) + #endif // WPA_SUPPLICANT_SUPPORT // + + MlmeRadioOff(pAd); +-#ifdef RT2860 + pAd->bPCIclkOff = FALSE; +-#endif // RT2860 // + } + #endif // CONFIG_STA_SUPPORT // + +@@ -359,7 +342,6 @@ int rt28xx_close(IN PNET_DEV dev) + TpcReqTabExit(pAd); + + +-#ifdef RT2860 + if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE)) + { + NICDisableInterrupt(pAd); +@@ -375,7 +357,6 @@ int rt28xx_close(IN PNET_DEV dev) + RT28XX_IRQ_RELEASE(net_dev) + RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE); + } +-#endif // RT2860 // + + + // Free Ring or USB buffers +@@ -396,7 +377,7 @@ int rt28xx_close(IN PNET_DEV dev) + + static int rt28xx_init(IN struct net_device *net_dev) + { +- PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)net_dev->priv; ++ PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)net_dev->ml_priv; + UINT index; + UCHAR TmpPhy; + NDIS_STATUS Status; +@@ -439,12 +420,10 @@ static int rt28xx_init(IN struct net_dev + + // Disable interrupts here which is as soon as possible + // This statement should never be true. We might consider to remove it later +-#ifdef RT2860 + if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE)) + { + NICDisableInterrupt(pAd); + } +-#endif // RT2860 // + + Status = RTMPAllocTxRxRingMemory(pAd); + if (Status != NDIS_STATUS_SUCCESS) +@@ -605,8 +584,8 @@ err1: + #endif // DOT11_N_SUPPORT // + RT28XX_IRQ_RELEASE(net_dev); + +- // shall not set priv to NULL here because the priv didn't been free yet. +- //net_dev->priv = 0; ++ // shall not set ml_priv to NULL here because the ml_priv didn't been free yet. ++ //net_dev->ml_priv = 0; + #ifdef INF_AMAZON_SE + err0: + #endif // INF_AMAZON_SE // +@@ -633,7 +612,7 @@ Note: + int rt28xx_open(IN PNET_DEV dev) + { + struct net_device * net_dev = (struct net_device *)dev; +- PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)net_dev->priv; ++ PRTMP_ADAPTER pAd = net_dev->ml_priv; + int retval = 0; + POS_COOKIE pObj; + +@@ -642,7 +621,7 @@ int rt28xx_open(IN PNET_DEV dev) + if (pAd == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -1; + } + +@@ -667,26 +646,6 @@ int rt28xx_open(IN PNET_DEV dev) + #endif // WIRELESS_EXT >= 12 // + #endif // CONFIG_APSTA_MIXED_SUPPORT // + +-#ifdef CONFIG_STA_SUPPORT +-#ifdef RT2860 +- IF_DEV_CONFIG_OPMODE_ON_STA(pAd) +- { +- // If dirver doesn't wake up firmware here, +- // NICLoadFirmware will hang forever when interface is up again. +- // RT2860 PCI +- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) && +- OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) +- { +- AUTO_WAKEUP_STRUC AutoWakeupCfg; +- AsicForceWakeup(pAd, TRUE); +- AutoWakeupCfg.word = 0; +- RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word); +- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE); +- } +- } +-#endif // RT2860 // +-#endif // CONFIG_STA_SUPPORT // +- + // Init + pObj = (POS_COOKIE)pAd->OS_Cookie; + +@@ -753,10 +712,8 @@ int rt28xx_open(IN PNET_DEV dev) + } + + #ifdef CONFIG_STA_SUPPORT +-#ifdef RT2860 + IF_DEV_CONFIG_OPMODE_ON_STA(pAd) + RTMPInitPCIeLinkCtrlValue(pAd); +-#endif // RT2860 // + #endif // CONFIG_STA_SUPPORT // + + return (retval); +@@ -808,9 +765,7 @@ static NDIS_STATUS rt_ieee80211_if_setup + dev->stop = MainVirtualIF_close; //rt28xx_close; + dev->priv_flags = INT_MAIN; + dev->do_ioctl = rt28xx_ioctl; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) +- dev->validate_addr = NULL; +-#endif ++ dev->validate_addr = NULL; + // find available device name + for (i = 0; i < 8; i++) + { +@@ -821,25 +776,11 @@ static NDIS_STATUS rt_ieee80211_if_setup + #endif // MULTIPLE_CARD_SUPPORT // + sprintf(slot_name, "ra%d", i); + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) +- device = dev_get_by_name(dev_net(dev), slot_name); +-#else +- device = dev_get_by_name(dev->nd_net, slot_name); +-#endif +-#else +- device = dev_get_by_name(slot_name); +-#endif +- if (device != NULL) dev_put(device); +-#else +- for (device = dev_base; device != NULL; device = device->next) +- { +- if (strncmp(device->name, slot_name, 4) == 0) +- break; +- } +-#endif +- if(device == NULL) ++ device = dev_get_by_name(dev_net(dev), slot_name); ++ if (device != NULL) ++ dev_put(device); ++ ++ if (device == NULL) + break; + } + +@@ -1252,47 +1193,28 @@ INT __devinit rt28xx_probe( + PRTMP_ADAPTER pAd = (PRTMP_ADAPTER) NULL; + INT status; + PVOID handle; +-#ifdef RT2860 + struct pci_dev *dev_p = (struct pci_dev *)_dev_p; +-#endif // RT2860 // + + + #ifdef CONFIG_STA_SUPPORT + DBGPRINT(RT_DEBUG_TRACE, ("STA Driver version-%s\n", STA_DRIVER_VERSION)); + #endif // CONFIG_STA_SUPPORT // + +-#if LINUX_VERSION_CODE <= 0x20402 // Red Hat 7.1 +- net_dev = alloc_netdev(sizeof(PRTMP_ADAPTER), "eth%d", ether_setup); +-#else + net_dev = alloc_etherdev(sizeof(PRTMP_ADAPTER)); +-#endif + if (net_dev == NULL) + { + printk("alloc_netdev failed\n"); + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) +-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) +- module_put(THIS_MODULE); +-#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) +-#else +- MOD_DEC_USE_COUNT; +-#endif + goto err_out; + } + +-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) +- SET_MODULE_OWNER(net_dev); +-#endif +- + netif_stop_queue(net_dev); + #ifdef NATIVE_WPA_SUPPLICANT_SUPPORT + /* for supporting Network Manager */ + /* Set the sysfs physical device reference for the network logical device + * if set prior to registration will cause a symlink during initialization. + */ +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) + SET_NETDEV_DEV(net_dev, &(dev_p->dev)); +-#endif + #endif // NATIVE_WPA_SUPPLICANT_SUPPORT // + + // Allocate RTMP_ADAPTER miniport adapter structure +@@ -1303,7 +1225,7 @@ INT __devinit rt28xx_probe( + if (status != NDIS_STATUS_SUCCESS) + goto err_out_free_netdev; + +- net_dev->priv = (PVOID)pAd; ++ net_dev->ml_priv = (PVOID)pAd; + pAd->net_dev = net_dev; // must be before RT28XXNetDevInit() + + RT28XXNetDevInit(_dev_p, net_dev, pAd); +@@ -1313,13 +1235,8 @@ INT __devinit rt28xx_probe( + #endif // CONFIG_STA_SUPPORT // + + // Post config +-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +- if (RT28XXProbePostConfig(_dev_p, pAd, argc) == FALSE) +- goto err_out_unmap; +-#else + if (RT28XXProbePostConfig(_dev_p, pAd, 0) == FALSE) + goto err_out_unmap; +-#endif // LINUX_VERSION_CODE // + + #ifdef CONFIG_STA_SUPPORT + pAd->OpMode = OPMODE_STA; +@@ -1362,20 +1279,12 @@ err_out_unmap: + RT28XX_UNMAP(); + + err_out_free_netdev: +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) +- free_netdev(net_dev); +-#else +- kfree(net_dev); +-#endif ++ free_netdev(net_dev); + + err_out: + RT28XX_PUT_DEVICE(dev_p); + +-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +- return (LONG)NULL; +-#else +- return -ENODEV; /* probe fail */ +-#endif // LINUX_VERSION_CODE // ++ return -ENODEV; /* probe fail */ + } /* End of rt28xx_probe */ + + +@@ -1399,7 +1308,7 @@ Note: + int rt28xx_packet_xmit(struct sk_buff *skb) + { + struct net_device *net_dev = skb->dev; +- PRTMP_ADAPTER pAd = (PRTMP_ADAPTER) net_dev->priv; ++ PRTMP_ADAPTER pAd = net_dev->ml_priv; + int status = 0; + PNDIS_PACKET pPacket = (PNDIS_PACKET) skb; + +@@ -1478,7 +1387,7 @@ INT rt28xx_send_packets( + IN struct sk_buff *skb_p, + IN struct net_device *net_dev) + { +- RTMP_ADAPTER *pAd = net_dev->priv; ++ RTMP_ADAPTER *pAd = net_dev->ml_priv; + if (!(net_dev->flags & IFF_UP)) + { + RELEASE_NDIS_PACKET(pAd, (PNDIS_PACKET)skb_p, NDIS_STATUS_FAILURE); +@@ -1495,40 +1404,6 @@ INT rt28xx_send_packets( + + + +-#if LINUX_VERSION_CODE <= 0x20402 // Red Hat 7.1 +-struct net_device *alloc_netdev( +- int sizeof_priv, +- const char *mask, +- void (*setup)(struct net_device *)) +-{ +- struct net_device *dev; +- INT alloc_size; +- +- +- /* ensure 32-byte alignment of the private area */ +- alloc_size = sizeof (*dev) + sizeof_priv + 31; +- +- dev = (struct net_device *) kmalloc(alloc_size, GFP_KERNEL); +- if (dev == NULL) +- { +- DBGPRINT(RT_DEBUG_ERROR, +- ("alloc_netdev: Unable to allocate device memory.\n")); +- return NULL; +- } +- +- memset(dev, 0, alloc_size); +- +- if (sizeof_priv) +- dev->priv = (void *) (((long)(dev + 1) + 31) & ~31); +- +- setup(dev); +- strcpy(dev->name, mask); +- +- return dev; +-} +-#endif // LINUX_VERSION_CODE // +- +- + void CfgInitHook(PRTMP_ADAPTER pAd) + { + pAd->bBroadComHT = TRUE; +@@ -1540,7 +1415,7 @@ void CfgInitHook(PRTMP_ADAPTER pAd) + struct iw_statistics *rt28xx_get_wireless_stats( + IN struct net_device *net_dev) + { +- PRTMP_ADAPTER pAd = (PRTMP_ADAPTER) net_dev->priv; ++ PRTMP_ADAPTER pAd = net_dev->ml_priv; + + + DBGPRINT(RT_DEBUG_TRACE, ("rt28xx_get_wireless_stats --->\n")); +@@ -1592,18 +1467,18 @@ INT rt28xx_ioctl( + + if (net_dev->priv_flags == INT_MAIN) + { +- pAd = net_dev->priv; ++ pAd = net_dev->ml_priv; + } + else + { +- pVirtualAd = net_dev->priv; +- pAd = pVirtualAd->RtmpDev->priv; ++ pVirtualAd = net_dev->ml_priv; ++ pAd = pVirtualAd->RtmpDev->ml_priv; + } + + if (pAd == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +@@ -1640,7 +1515,7 @@ struct net_device_stats *RT28xx_get_ethe + RTMP_ADAPTER *pAd = NULL; + + if (net_dev) +- pAd = net_dev->priv; ++ pAd = net_dev->ml_priv; + + if (pAd) + { +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rtmp_def.h linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rtmp_def.h +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rtmp_def.h 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rtmp_def.h 2009-08-27 12:44:31.000000000 +0100 +@@ -111,7 +111,6 @@ + // Entry number for each DMA descriptor ring + // + +-#ifdef RT2860 + #define TX_RING_SIZE 64 //64 + #define MGMT_RING_SIZE 128 + #define RX_RING_SIZE 128 //64 +@@ -119,7 +118,6 @@ + #define MAX_DMA_DONE_PROCESS TX_RING_SIZE + #define MAX_TX_DONE_PROCESS TX_RING_SIZE //8 + #define LOCAL_TXBUF_SIZE 2 +-#endif // RT2860 // + + + #ifdef MULTIPLE_CARD_SUPPORT +@@ -212,6 +210,19 @@ + #define fOP_STATUS_WAKEUP_NOW 0x00008000 + #define fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE 0x00020000 + ++// ++// RTMP_ADAPTER PSFlags : related to advanced power save. ++// ++// Indicate whether driver can go to sleep mode from now. This flag is useful AFTER link up ++#define fRTMP_PS_CAN_GO_SLEEP 0x00000001 ++// Indicate whether driver has issue a LinkControl command to PCIe L1 ++#define fRTMP_PS_SET_PCI_CLK_OFF_COMMAND 0x00000002 ++// Indicate driver should disable kick off hardware to send packets from now. ++#define fRTMP_PS_DISABLE_TX 0x00000004 ++// Indicate driver should IMMEDIATELY fo to sleep after receiving AP's beacon in which doesn't indicate unicate nor multicast packets for me ++//. This flag is used ONLY in RTMPHandleRxDoneInterrupt routine. ++#define fRTMP_PS_GO_TO_SLEEP_NOW 0x00000008 ++ + #ifdef DOT11N_DRAFT3 + #define fOP_STATUS_SCAN_2040 0x00040000 + #endif // DOT11N_DRAFT3 // +@@ -333,7 +344,7 @@ + /* sanity check for apidx */ + #define MBSS_MR_APIDX_SANITY_CHECK(apidx) \ + { if (apidx > MAX_MBSSID_NUM) { \ +- printk("%s> Error! apidx = %d > MAX_MBSSID_NUM!\n", __FUNCTION__, apidx); \ ++ printk("%s> Error! apidx = %d > MAX_MBSSID_NUM!\n", __func__, apidx); \ + apidx = MAIN_MBSSID; } } + + #define VALID_WCID(_wcid) ((_wcid) > 0 && (_wcid) < MAX_LEN_OF_MAC_TABLE ) +@@ -1514,12 +1525,14 @@ + #define MCAST_HTMIX 3 + #endif // MCAST_RATE_SPECIFIC // + +-// For AsicRadioOff/AsicRadioOn function +-#define DOT11POWERSAVE 0 +-#define GUIRADIO_OFF 1 +-#define RTMP_HALT 2 +-#define GUI_IDLE_POWER_SAVE 3 +-// -- ++// For AsicRadioOff/AsicRadioOn/AsicForceWakeup function ++// This is to indicate from where to call this function. ++#define DOT11POWERSAVE 0 // TO do .11 power save sleep ++#define GUIRADIO_OFF 1 // To perform Radio OFf command from GUI ++#define RTMP_HALT 2 // Called from Halt handler. ++#define GUI_IDLE_POWER_SAVE 3 // Call to sleep before link up with AP ++#define FROM_TX 4 // Force wake up from Tx packet. ++ + + + // definition for WpaSupport flag +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rtmp.h linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rtmp.h +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rtmp.h 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rtmp.h 2009-08-27 12:44:31.000000000 +0100 +@@ -203,9 +203,7 @@ typedef struct _ATE_INFO { + BOOLEAN bRxFer; + BOOLEAN bQATxStart; // Have compiled QA in and use it to ATE tx. + BOOLEAN bQARxStart; // Have compiled QA in and use it to ATE rx. +-#ifdef RT2860 + BOOLEAN bFWLoading; // Reload firmware when ATE is done. +-#endif // RT2860 // + UINT32 RxTotalCnt; + UINT32 RxCntPerSec; + +@@ -366,6 +364,13 @@ typedef struct _QUEUE_HEADER { + #define RTMP_TEST_FLAG(_M, _F) (((_M)->Flags & (_F)) != 0) + #define RTMP_TEST_FLAGS(_M, _F) (((_M)->Flags & (_F)) == (_F)) + ++// Macro for power save flag. ++#define RTMP_SET_PSFLAG(_M, _F) ((_M)->PSFlags |= (_F)) ++#define RTMP_CLEAR_PSFLAG(_M, _F) ((_M)->PSFlags &= ~(_F)) ++#define RTMP_CLEAR_PSFLAGS(_M) ((_M)->PSFlags = 0) ++#define RTMP_TEST_PSFLAG(_M, _F) (((_M)->PSFlags & (_F)) != 0) ++#define RTMP_TEST_PSFLAGS(_M, _F) (((_M)->PSFlags & (_F)) == (_F)) ++ + #define OPSTATUS_SET_FLAG(_pAd, _F) ((_pAd)->CommonCfg.OpStatusFlags |= (_F)) + #define OPSTATUS_CLEAR_FLAG(_pAd, _F) ((_pAd)->CommonCfg.OpStatusFlags &= ~(_F)) + #define OPSTATUS_TEST_FLAG(_pAd, _F) (((_pAd)->CommonCfg.OpStatusFlags & (_F)) != 0) +@@ -478,7 +483,6 @@ typedef struct _QUEUE_HEADER { + // + #define MAX_BUSY_COUNT 100 // Number of retry before failing access BBP & RF indirect register + // +-#ifdef RT2860 + #define RTMP_RF_IO_WRITE32(_A, _V) \ + { \ + PHY_CSR4_STRUC Value; \ +@@ -642,7 +646,6 @@ typedef struct _QUEUE_HEADER { + } \ + } \ + } +-#endif // RT2860 // + + + #define MAP_CHANNEL_ID_TO_KHZ(ch, khz) { \ +@@ -894,7 +897,6 @@ typedef struct _RTMP_SCATTER_GATHER_LIST + // Enqueue this frame to MLME engine + // We need to enqueue the whole frame because MLME need to pass data type + // information from 802.11 header +-#ifdef RT2860 + #define REPORT_MGMT_FRAME_TO_MLME(_pAd, Wcid, _pFrame, _FrameSize, _Rssi0, _Rssi1, _Rssi2, _PlcpSignal) \ + { \ + UINT32 High32TSF, Low32TSF; \ +@@ -902,7 +904,6 @@ typedef struct _RTMP_SCATTER_GATHER_LIST + RTMP_IO_READ32(_pAd, TSF_TIMER_DW0, &Low32TSF); \ + MlmeEnqueueForRecv(_pAd, Wcid, High32TSF, Low32TSF, (UCHAR)_Rssi0, (UCHAR)_Rssi1,(UCHAR)_Rssi2,_FrameSize, _pFrame, (UCHAR)_PlcpSignal); \ + } +-#endif // RT2860 // + + #define NDIS_QUERY_BUFFER(_NdisBuf, _ppVA, _pBufLen) \ + NdisQueryBuffer(_NdisBuf, _ppVA, _pBufLen) +@@ -919,9 +920,10 @@ typedef struct _RTMP_SCATTER_GATHER_LIST + #define STA_PORT_SECURED(_pAd) \ + { \ + _pAd->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED; \ +- NdisAcquireSpinLock(&_pAd->MacTabLock); \ ++ RTMP_SET_PSFLAG(_pAd, fRTMP_PS_CAN_GO_SLEEP); \ ++ NdisAcquireSpinLock(&(_pAd)->MacTabLock); \ + _pAd->MacTab.Content[BSSID_WCID].PortSecured = _pAd->StaCfg.PortSecured; \ +- NdisReleaseSpinLock(&_pAd->MacTabLock); \ ++ NdisReleaseSpinLock(&(_pAd)->MacTabLock); \ + } + #endif // CONFIG_STA_SUPPORT // + +@@ -1000,9 +1002,7 @@ typedef struct _RTMP_REORDERBUF + UCHAR DataOffset; + USHORT Datasize; + ULONG AllocSize; +-#ifdef RT2860 + NDIS_PHYSICAL_ADDRESS AllocPa; // TxBuf physical address +-#endif // RT2860 // + } RTMP_REORDERBUF, *PRTMP_REORDERBUF; + + // +@@ -1101,6 +1101,7 @@ typedef struct _COUNTER_802_11 { + + typedef struct _COUNTER_RALINK { + ULONG TransmittedByteCount; // both successful and failure, used to calculate TX throughput ++ ULONG LastReceivedByteCount; + ULONG ReceivedByteCount; // both CRC okay and CRC error, used to calculate RX throughput + ULONG BeenDisassociatedCount; + ULONG BadCQIAutoRecoveryCount; +@@ -1436,11 +1437,9 @@ typedef struct _MLME_STRUCT { + RALINK_TIMER_STRUCT APSDPeriodicTimer; + RALINK_TIMER_STRUCT LinkDownTimer; + RALINK_TIMER_STRUCT LinkUpTimer; +-#ifdef RT2860 + UCHAR bPsPollTimerRunning; + RALINK_TIMER_STRUCT PsPollTimer; + RALINK_TIMER_STRUCT RadioOnOffTimer; +-#endif // RT2860 // + ULONG PeriodicRound; + ULONG OneSecPeriodicRound; + +@@ -2228,9 +2227,7 @@ typedef struct _STA_ADMIN_CONFIG { + RT_HT_PHY_INFO DesiredHtPhyInfo; + BOOLEAN bAutoTxRateSwitch; + +-#ifdef RT2860 + UCHAR BBPR3; +-#endif // RT2860 // + + #ifdef EXT_BUILD_CHANNEL_LIST + UCHAR IEEE80211dClientMode; +@@ -2663,7 +2660,6 @@ typedef struct _RTMP_ADAPTER + PNET_DEV net_dev; + ULONG VirtualIfCnt; + +-#ifdef RT2860 + USHORT LnkCtrlBitMask; + USHORT RLnkCtrlConfiguration; + USHORT RLnkCtrlOffset; +@@ -2671,7 +2667,9 @@ typedef struct _RTMP_ADAPTER + USHORT HostLnkCtrlOffset; + USHORT PCIePowerSaveLevel; + BOOLEAN bPCIclkOff; // flag that indicate if the PICE power status in Configuration SPace.. +- BOOLEAN bPCIclkOffDisableTx; // ++ ULONG CheckDmaBusyCount; // Check Interrupt Status Register Count. ++ USHORT ThisTbttNumToNextWakeUp; ++ ULONG SameRxByteCount; + + + /*****************************************************************************************/ +@@ -2688,7 +2686,6 @@ typedef struct _RTMP_ADAPTER + RTMP_DMABUF RxDescRing; // Shared memory for RX descriptors + RTMP_DMABUF TxDescRing[NUM_OF_TX_RING]; // Shared memory for Tx descriptors + RTMP_TX_RING TxRing[NUM_OF_TX_RING]; // AC0~4 + HCCA +-#endif // RT2860 // + + + NDIS_SPIN_LOCK irq_lock; +@@ -2721,10 +2718,8 @@ typedef struct _RTMP_ADAPTER + /* Rx related parameters */ + /*****************************************************************************************/ + +-#ifdef RT2860 + RTMP_RX_RING RxRing; + NDIS_SPIN_LOCK RxRingLock; // Rx Ring spinlock +-#endif // RT2860 // + + + +@@ -2895,6 +2890,7 @@ typedef struct _RTMP_ADAPTER + + // flags, see fRTMP_ADAPTER_xxx flags + ULONG Flags; // Represent current device status ++ ULONG PSFlags; // Power Save operation flag. + + // current TX sequence # + USHORT Sequence; +@@ -3181,7 +3177,6 @@ typedef struct _TX_BLK_ + //------------------------------------------------------------------------------------------ + + +-#ifdef RT2860 + // + // Enable & Disable NIC interrupt via writing interrupt mask register + // Since it use ADAPTER structure, it have to be put after structure definition. +@@ -3214,7 +3209,6 @@ __inline VOID NICEnableInterrupt( + //RTMP_IO_WRITE32(pAd, PBF_INT_ENA, 0x00000030); // 1 : enable + RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE); + } +-#endif // RT2860 // + + #ifdef RT_BIG_ENDIAN + static inline VOID WriteBackToDescriptor( +@@ -3291,7 +3285,6 @@ static inline VOID RTMPWIEndianChange( + Call this function when read or update descriptor + ======================================================================== + */ +-#ifdef RT2860 + static inline VOID RTMPDescriptorEndianChange( + IN PUCHAR pData, + IN ULONG DescriptorType) +@@ -3301,7 +3294,6 @@ static inline VOID RTMPDescriptorEndianC + *((UINT32 *)(pData +12)) = SWAP32(*((UINT32 *)(pData + 12))); // Byte 12~15 + *((UINT32 *)(pData + 4)) = SWAP32(*((UINT32 *)(pData + 4))); // Byte 4~7, this must be swapped last + } +-#endif // RT2860 // + + /* + ======================================================================== +@@ -3550,6 +3542,9 @@ NDIS_STATUS NICInitializeAsic( + IN PRTMP_ADAPTER pAd, + IN BOOLEAN bHardReset); + ++VOID NICRestoreBBPValue( ++ IN PRTMP_ADAPTER pAd); ++ + VOID NICIssueReset( + IN PRTMP_ADAPTER pAd); + +@@ -4208,7 +4203,7 @@ VOID AsicForceSleep( + + VOID AsicForceWakeup( + IN PRTMP_ADAPTER pAd, +- IN BOOLEAN bFromTx); ++ IN UCHAR Level); + #endif // CONFIG_STA_SUPPORT // + + VOID AsicSetBssid( +@@ -4304,11 +4299,9 @@ BOOLEAN AsicSendCommandToMcu( + IN UCHAR Arg0, + IN UCHAR Arg1); + +-#ifdef RT2860 + BOOLEAN AsicCheckCommanOk( + IN PRTMP_ADAPTER pAd, + IN UCHAR Command); +-#endif // RT2860 // + + VOID MacAddrRandomBssid( + IN PRTMP_ADAPTER pAd, +@@ -6978,7 +6971,6 @@ void kill_thread_task(PRTMP_ADAPTER pAd) + + void tbtt_tasklet(unsigned long data); + +-#ifdef RT2860 + // + // Function Prototype in cmm_data_2860.c + // +@@ -7069,7 +7061,7 @@ BOOLEAN RT28xxPciAsicRadioOn( + + VOID RT28xxPciStaAsicForceWakeup( + IN PRTMP_ADAPTER pAd, +- IN BOOLEAN bFromTx); ++ IN UCHAR Level); + + VOID RT28xxPciStaAsicSleepThenAutoWakeup( + IN PRTMP_ADAPTER pAd, +@@ -7093,7 +7085,6 @@ VOID RT28xxPciMlmeRadioOn( + + VOID RT28xxPciMlmeRadioOFF( + IN PRTMP_ADAPTER pAd); +-#endif // RT2860 // + + VOID AsicTurnOffRFClk( + IN PRTMP_ADAPTER pAd, +@@ -7132,6 +7123,18 @@ PCHAR RTMPGetRalinkEncryModeStr( + #ifdef CONFIG_STA_SUPPORT + VOID AsicStaBbpTuning( + IN PRTMP_ADAPTER pAd); ++ ++VOID AsicResetFromDMABusy( ++ IN PRTMP_ADAPTER pAd); ++ ++VOID AsicResetBBP( ++ IN PRTMP_ADAPTER pAd); ++ ++VOID AsicResetMAC( ++ IN PRTMP_ADAPTER pAd); ++ ++VOID AsicResetPBF( ++ IN PRTMP_ADAPTER pAd); + #endif // CONFIG_STA_SUPPORT // + + void RTMP_IndicateMediaState( +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_profile.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_profile.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/rt_profile.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/rt_profile.c 2009-08-27 12:44:31.000000000 +0100 +@@ -925,9 +925,11 @@ NDIS_STATUS RTMPReadParametersHook( + + // Save uid and gid used for filesystem access. + // Set user and group to 0 (root) +- orgfsuid = current->fsuid; +- orgfsgid = current->fsgid; +- current->fsuid=current->fsgid = 0; ++ orgfsuid = current_fsuid(); ++ orgfsgid = current_fsgid(); ++ /* Hm, can't really do this nicely anymore, so rely on these files ++ * being set to the proper permission to read them... */ ++ /* current->cred->fsuid = current->cred->fsgid = 0; */ + orgfs = get_fs(); + set_fs(KERNEL_DS); + +@@ -1022,7 +1024,7 @@ NDIS_STATUS RTMPReadParametersHook( + pAd->MlmeAux.SsidLen = pAd->CommonCfg.SsidLen; + NdisZeroMemory(pAd->MlmeAux.Ssid, NDIS_802_11_LENGTH_SSID); + NdisMoveMemory(pAd->MlmeAux.Ssid, tmpbuf, pAd->MlmeAux.SsidLen); +- DBGPRINT(RT_DEBUG_TRACE, ("%s::(SSID=%s)\n", __FUNCTION__, tmpbuf)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::(SSID=%s)\n", __func__, tmpbuf)); + } + } + } +@@ -1041,7 +1043,7 @@ NDIS_STATUS RTMPReadParametersHook( + pAd->StaCfg.BssType = BSS_INFRA; + // Reset Ralink supplicant to not use, it will be set to start when UI set PMK key + pAd->StaCfg.WpaState = SS_NOTUSE; +- DBGPRINT(RT_DEBUG_TRACE, ("%s::(NetworkType=%d)\n", __FUNCTION__, pAd->StaCfg.BssType)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::(NetworkType=%d)\n", __func__, pAd->StaCfg.BssType)); + } + } + #endif // CONFIG_STA_SUPPORT // +@@ -1335,7 +1337,7 @@ NDIS_STATUS RTMPReadParametersHook( + + pAd->StaCfg.PortSecured = WPA_802_1X_PORT_NOT_SECURED; + +- DBGPRINT(RT_DEBUG_TRACE, ("%s::(EncrypType=%d)\n", __FUNCTION__, pAd->StaCfg.WepStatus)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::(EncrypType=%d)\n", __func__, pAd->StaCfg.WepStatus)); + } + #endif // CONFIG_STA_SUPPORT // + } +@@ -1361,7 +1363,7 @@ NDIS_STATUS RTMPReadParametersHook( + pAd->StaCfg.OrigWepStatus = pAd->StaCfg.WepStatus; + pAd->StaCfg.bMixCipher = FALSE; + +- DBGPRINT(RT_DEBUG_TRACE, ("%s::(EncrypType=%d)\n", __FUNCTION__, pAd->StaCfg.WepStatus)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::(EncrypType=%d)\n", __func__, pAd->StaCfg.WepStatus)); + } + #endif // CONFIG_STA_SUPPORT // + } +@@ -1398,7 +1400,7 @@ NDIS_STATUS RTMPReadParametersHook( + else + { + err = 1; +- DBGPRINT(RT_DEBUG_ERROR, ("%s::(WPAPSK key-string required 8 ~ 64 characters!)\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_ERROR, ("%s::(WPAPSK key-string required 8 ~ 64 characters!)\n", __func__)); + } + + if (err == 0) +@@ -1414,7 +1416,7 @@ NDIS_STATUS RTMPReadParametersHook( + pAd->StaCfg.WpaState = SS_NOTUSE; + } + +- DBGPRINT(RT_DEBUG_TRACE, ("%s::(WPAPSK=%s)\n", __FUNCTION__, tmpbuf)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::(WPAPSK=%s)\n", __func__, tmpbuf)); + } + } + } +@@ -1449,7 +1451,7 @@ NDIS_STATUS RTMPReadParametersHook( + IF_DEV_CONFIG_OPMODE_ON_STA(pAd) + { + //PSMode +- if (RTMPGetKeyParameter("PSMode", tmpbuf, 10, buffer)) ++ if (RTMPGetKeyParameter("PSMode", tmpbuf, 32, buffer)) + { + if (pAd->StaCfg.BssType == BSS_INFRA) + { +@@ -1551,8 +1553,11 @@ NDIS_STATUS RTMPReadParametersHook( + } + + set_fs(orgfs); +- current->fsuid = orgfsuid; +- current->fsgid = orgfsgid; ++ ++#if 0 ++ current->cred->fsuid = orgfsuid; ++ current->cred->fsgid = orgfsgid; ++#endif + + kfree(buffer); + kfree(tmpbuf); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta/assoc.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta/assoc.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta/assoc.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta/assoc.c 2009-08-27 12:44:29.000000000 +0100 +@@ -473,12 +473,7 @@ VOID MlmeAssocReqAction( + RSNIe = IE_WPA2; + } + +-#ifdef NATIVE_WPA_SUPPLICANT_SUPPORT +-#ifdef SIOCSIWGENIE +- if (pAd->StaCfg.WpaSupplicantUP != 1) +-#endif // SIOCSIWGENIE // +-#endif // NATIVE_WPA_SUPPLICANT_SUPPORT // +- RTMPMakeRSNIE(pAd, pAd->StaCfg.AuthMode, pAd->StaCfg.WepStatus, BSS0); ++ RTMPMakeRSNIE(pAd, pAd->StaCfg.AuthMode, pAd->StaCfg.WepStatus, BSS0); + + // Check for WPA PMK cache list + if (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2) +@@ -504,17 +499,6 @@ VOID MlmeAssocReqAction( + } + } + +-#ifdef NATIVE_WPA_SUPPLICANT_SUPPORT +-#ifdef SIOCSIWGENIE +- if (pAd->StaCfg.WpaSupplicantUP == 1) +- { +- MakeOutgoingFrame(pOutBuffer + FrameLen, &tmp, +- pAd->StaCfg.RSNIE_Len, pAd->StaCfg.RSN_IE, +- END_OF_ARGS); +- } +- else +-#endif +-#endif // NATIVE_WPA_SUPPLICANT_SUPPORT // + { + MakeOutgoingFrame(pOutBuffer + FrameLen, &tmp, + 1, &RSNIe, +@@ -525,11 +509,6 @@ VOID MlmeAssocReqAction( + + FrameLen += tmp; + +-#ifdef NATIVE_WPA_SUPPLICANT_SUPPORT +-#ifdef SIOCSIWGENIE +- if (pAd->StaCfg.WpaSupplicantUP != 1) +-#endif +-#endif // NATIVE_WPA_SUPPLICANT_SUPPORT // + { + // Append Variable IE + NdisMoveMemory(pAd->StaCfg.ReqVarIEs + VarIesOffset, &RSNIe, 1); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta/connect.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta/connect.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta/connect.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta/connect.c 2009-08-27 12:44:29.000000000 +0100 +@@ -337,6 +337,10 @@ VOID CntlOidSsidProc( + MLME_DISASSOC_REQ_STRUCT DisassocReq; + ULONG Now; + ++ // BBP and RF are not accessible in PS mode, we has to wake them up first ++ if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) ++ AsicForceWakeup(pAd, RTMP_HALT); ++ + // Step 1. record the desired user settings to MlmeAux + NdisZeroMemory(pAd->MlmeAux.Ssid, MAX_LEN_OF_SSID); + NdisMoveMemory(pAd->MlmeAux.Ssid, pOidSsid->Ssid, pOidSsid->SsidLength); +@@ -1240,6 +1244,13 @@ VOID LinkUp( + UCHAR Value = 0, idx; + MAC_TABLE_ENTRY *pEntry = NULL, *pCurrEntry; + ++ if (RTMP_TEST_PSFLAG(pAd, fRTMP_PS_SET_PCI_CLK_OFF_COMMAND)) ++ { ++ RTMPPCIeLinkCtrlValueRestore(pAd, RESTORE_HALT); ++ RTMPusecDelay(6000); ++ pAd->bPCIclkOff = FALSE; ++ } ++ + pEntry = &pAd->MacTab.Content[BSSID_WCID]; + + // +@@ -1264,7 +1275,6 @@ VOID LinkUp( + //rt2860b. Don't know why need this + SwitchBetweenWepAndCkip(pAd); + +-#ifdef RT2860 + // Before power save before link up function, We will force use 1R. + // So after link up, check Rx antenna # again. + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value); +@@ -1282,7 +1292,6 @@ VOID LinkUp( + } + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value); + pAd->StaCfg.BBPR3 = Value; +-#endif // RT2860 // + + if (BssType == BSS_ADHOC) + { +@@ -1330,9 +1339,7 @@ VOID LinkUp( + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value); + Value &= (~0x20); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value); +-#ifdef RT2860 + pAd->StaCfg.BBPR3 = Value; +-#endif // RT2860 // + + RTMP_IO_READ32(pAd, TX_BAND_CFG, &Data); + Data &= 0xfffffffe; +@@ -1367,9 +1374,7 @@ VOID LinkUp( + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value); + Value |= (0x20); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value); +-#ifdef RT2860 + pAd->StaCfg.BBPR3 = Value; +-#endif // RT2860 // + + if (pAd->MACVersion == 0x28600100) + { +@@ -1400,9 +1405,7 @@ VOID LinkUp( + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value); + Value &= (~0x20); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value); +-#ifdef RT2860 + pAd->StaCfg.BBPR3 = Value; +-#endif // RT2860 // + + if (pAd->MACVersion == 0x28600100) + { +@@ -1598,6 +1601,8 @@ VOID LinkUp( + IV = 0; + IV |= (pAd->StaCfg.DefaultKeyId << 30); + AsicUpdateWCIDIVEIV(pAd, BSSID_WCID, IV, 0); ++ ++ RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP); + } + // NOTE: + // the decision of using "short slot time" or not may change dynamically due to +@@ -1919,6 +1924,7 @@ VOID LinkUp( + } + + RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS); ++ RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_GO_TO_SLEEP_NOW); + + #ifdef DOT11_N_SUPPORT + #ifdef DOT11N_DRAFT3 +@@ -1961,6 +1967,7 @@ VOID LinkDown( + IN BOOLEAN IsReqFromAP) + { + UCHAR i, ByteValue = 0; ++ BOOLEAN Cancelled; + + // Do nothing if monitor mode is on + if (MONITOR_ON(pAd)) +@@ -1972,6 +1979,12 @@ VOID LinkDown( + return; + #endif // RALINK_ATE // + ++ RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_GO_TO_SLEEP_NOW); ++ RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled); ++ ++ // Not allow go to sleep within linkdown function. ++ RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP); ++ + if (pAd->CommonCfg.bWirelessEvent) + { + RTMPSendWirelessEvent(pAd, IW_STA_LINKDOWN_EVENT_FLAG, pAd->MacTab.Content[BSSID_WCID].Addr, BSS0, 0); +@@ -1980,7 +1993,6 @@ VOID LinkDown( + DBGPRINT(RT_DEBUG_TRACE, ("!!! LINK DOWN !!!\n")); + OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_AGGREGATION_INUSED); + +-#ifdef RT2860 + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) + { + BOOLEAN Cancelled; +@@ -1988,17 +2000,15 @@ VOID LinkDown( + RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled); + } + +- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) ++ if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) || ++ RTMP_TEST_PSFLAG(pAd, fRTMP_PS_SET_PCI_CLK_OFF_COMMAND) || ++ RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF)) + { +- AUTO_WAKEUP_STRUC AutoWakeupCfg; +- AsicForceWakeup(pAd, TRUE); +- AutoWakeupCfg.word = 0; +- RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word); ++ AsicForceWakeup(pAd, RTMP_HALT); + OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE); + } + + pAd->bPCIclkOff = FALSE; +-#endif // RT2860 // + if (ADHOC_ON(pAd)) // Adhoc mode link down + { + DBGPRINT(RT_DEBUG_TRACE, ("!!! LINK DOWN 1!!!\n")); +@@ -2266,6 +2276,9 @@ VOID LinkDown( + RTMP_IO_WRITE32(pAd, MAX_LEN_CFG, 0x1fff); + RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS); + ++ // Allow go to sleep after linkdown steps. ++ RTMP_SET_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP); ++ + #ifdef WPA_SUPPLICANT_SUPPORT + #ifndef NATIVE_WPA_SUPPLICANT_SUPPORT + if (pAd->StaCfg.WpaSupplicantUP) { +@@ -2510,7 +2523,6 @@ VOID AuthParmFill( + + ========================================================================== + */ +-#ifdef RT2860 + VOID ComposePsPoll( + IN PRTMP_ADAPTER pAd) + { +@@ -2534,7 +2546,6 @@ VOID ComposeNullFrame( + COPY_MAC_ADDR(pAd->NullFrame.Addr2, pAd->CurrentAddress); + COPY_MAC_ADDR(pAd->NullFrame.Addr3, pAd->CommonCfg.Bssid); + } +-#endif // RT2860 // + + + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta/dls.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta/dls.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta/dls.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta/dls.c 2009-08-27 12:44:29.000000000 +0100 +@@ -1419,7 +1419,6 @@ BOOLEAN RTMPRcvFrameDLSCheck( + //AsicAddKeyEntry(pAd, (USHORT)(i + 2), BSS0, 0, &PairwiseKey, TRUE, TRUE); // reserve 0 for multicast, 1 for unicast + //AsicUpdateRxWCIDTable(pAd, (USHORT)(i + 2), pAddr); + // Add Pair-wise key to Asic +-#ifdef RT2860 + AsicAddPairwiseKeyEntry(pAd, + pAd->StaCfg.DLSEntry[i].MacAddr, + (UCHAR)pAd->StaCfg.DLSEntry[i].MacTabMatchWCID, +@@ -1431,7 +1430,6 @@ BOOLEAN RTMPRcvFrameDLSCheck( + PairwiseKey.CipherAlg, + pEntry); + +-#endif // RT2860 // + NdisMoveMemory(&pEntry->PairwiseKey, &PairwiseKey, sizeof(CIPHER_KEY)); + DBGPRINT(RT_DEBUG_TRACE,("DLS - Receive STAKey Message-1 (Peer STA MAC Address STAKey) \n")); + +@@ -1477,7 +1475,6 @@ BOOLEAN RTMPRcvFrameDLSCheck( + //AsicAddKeyEntry(pAd, (USHORT)(i + 2), BSS0, 0, &PairwiseKey, TRUE, TRUE); // reserve 0 for multicast, 1 for unicast + //AsicUpdateRxWCIDTable(pAd, (USHORT)(i + 2), pAddr); + // Add Pair-wise key to Asic +-#ifdef RT2860 + AsicAddPairwiseKeyEntry(pAd, + pAd->StaCfg.DLSEntry[i].MacAddr, + (UCHAR)pAd->StaCfg.DLSEntry[i].MacTabMatchWCID, +@@ -1488,7 +1485,6 @@ BOOLEAN RTMPRcvFrameDLSCheck( + 0, + PairwiseKey.CipherAlg, + pEntry); +-#endif // RT2860 // + NdisMoveMemory(&pEntry->PairwiseKey, &PairwiseKey, sizeof(CIPHER_KEY)); + DBGPRINT(RT_DEBUG_TRACE,("DLS - Receive STAKey Message-1 (Initiator STA MAC Address STAKey)\n")); + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta/rtmp_data.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta/rtmp_data.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta/rtmp_data.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta/rtmp_data.c 2009-08-27 12:44:29.000000000 +0100 +@@ -75,7 +75,6 @@ VOID STARxEAPOLFrameIndicate( + + if (pAd->StaCfg.DesireSharedKey[idx].KeyLen > 0) + { +-#ifdef RT2860 + MAC_TABLE_ENTRY *pEntry = &pAd->MacTab.Content[BSSID_WCID]; + + // Set key material and cipherAlg to Asic +@@ -89,7 +88,6 @@ VOID STARxEAPOLFrameIndicate( + + pAd->IndicateMediaState = NdisMediaStateConnected; + pAd->ExtraInfo = GENERAL_LINK_UP; +-#endif // RT2860 // + // For Preventing ShardKey Table is cleared by remove key procedure. + pAd->SharedKey[BSS0][idx].CipherAlg = CipherAlg; + pAd->SharedKey[BSS0][idx].KeyLen = pAd->StaCfg.DesireSharedKey[idx].KeyLen; +@@ -693,14 +691,12 @@ BOOLEAN STARxDoneInterruptHandle( + break; + } + +-#ifdef RT2860 + if (RxProcessed++ > MAX_RX_PROCESS_CNT) + { + // need to reschedule rx handle + bReschedule = TRUE; + break; + } +-#endif // RT2860 // + + RxProcessed ++; // test + +@@ -811,6 +807,13 @@ BOOLEAN STARxDoneInterruptHandle( + } + } + ++ // fRTMP_PS_GO_TO_SLEEP_NOW is set if receiving beacon. ++ if (RTMP_TEST_PSFLAG(pAd, fRTMP_PS_GO_TO_SLEEP_NOW) && (INFRA_ON(pAd))) ++ { ++ RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_GO_TO_SLEEP_NOW); ++ AsicSleepThenAutoWakeup(pAd, pAd->ThisTbttNumToNextWakeUp); ++ bReschedule = FALSE; ++ } + return bReschedule; + } + +@@ -828,7 +831,7 @@ BOOLEAN STARxDoneInterruptHandle( + VOID RTMPHandleTwakeupInterrupt( + IN PRTMP_ADAPTER pAd) + { +- AsicForceWakeup(pAd, FALSE); ++ AsicForceWakeup(pAd, DOT11POWERSAVE); + } + + /* +@@ -1220,7 +1223,6 @@ NDIS_STATUS STASendPacket( + + ======================================================================== + */ +-#ifdef RT2860 + NDIS_STATUS RTMPFreeTXDRequest( + IN PRTMP_ADAPTER pAd, + IN UCHAR QueIdx, +@@ -1264,7 +1266,6 @@ NDIS_STATUS RTMPFreeTXDRequest( + + return (Status); + } +-#endif // RT2860 // + + + +@@ -1889,7 +1890,8 @@ VOID STA_AMPDU_Frame_Tx( + // + // Kick out Tx + // +- HAL_KickOutTx(pAd, pTxBlk, pTxBlk->QueIdx); ++ if (!RTMP_TEST_PSFLAG(pAd, fRTMP_PS_DISABLE_TX)) ++ HAL_KickOutTx(pAd, pTxBlk, pTxBlk->QueIdx); + + pAd->RalinkCounters.KickTxCount++; + pAd->RalinkCounters.OneSecTxDoneCount++; +@@ -2019,7 +2021,8 @@ VOID STA_AMSDU_Frame_Tx( + // + // Kick out Tx + // +- HAL_KickOutTx(pAd, pTxBlk, pTxBlk->QueIdx); ++ if (!RTMP_TEST_PSFLAG(pAd, fRTMP_PS_DISABLE_TX)) ++ HAL_KickOutTx(pAd, pTxBlk, pTxBlk->QueIdx); + } + #endif // DOT11_N_SUPPORT // + +@@ -2139,7 +2142,8 @@ VOID STA_Legacy_Frame_Tx( + // + // Kick out Tx + // +- HAL_KickOutTx(pAd, pTxBlk, pTxBlk->QueIdx); ++ if (!RTMP_TEST_PSFLAG(pAd, fRTMP_PS_DISABLE_TX)) ++ HAL_KickOutTx(pAd, pTxBlk, pTxBlk->QueIdx); + } + + +@@ -2249,7 +2253,8 @@ VOID STA_ARalink_Frame_Tx( + // + // Kick out Tx + // +- HAL_KickOutTx(pAd, pTxBlk, pTxBlk->QueIdx); ++ if (!RTMP_TEST_PSFLAG(pAd, fRTMP_PS_DISABLE_TX)) ++ HAL_KickOutTx(pAd, pTxBlk, pTxBlk->QueIdx); + + } + +@@ -2526,7 +2531,7 @@ NDIS_STATUS STAHardTransmit( + if ((pAd->StaCfg.Psm == PWR_SAVE) && OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) + { + DBGPRINT_RAW(RT_DEBUG_TRACE, ("AsicForceWakeup At HardTx\n")); +- AsicForceWakeup(pAd, TRUE); ++ AsicForceWakeup(pAd, FROM_TX); + } + + // It should not change PSM bit, when APSD turn on. +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta/sync.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta/sync.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta/sync.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta/sync.c 2009-08-27 12:44:29.000000000 +0100 +@@ -228,7 +228,6 @@ VOID MlmeScanReqAction( + // Increase the scan retry counters. + pAd->StaCfg.ScanCnt++; + +-#ifdef RT2860 + if ((OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) && + (IDLE_ON(pAd)) && + (pAd->StaCfg.bRadio == TRUE) && +@@ -236,7 +235,6 @@ VOID MlmeScanReqAction( + { + RT28xxPciAsicRadioOn(pAd, GUI_IDLE_POWER_SAVE); + } +-#endif // RT2860 // + + // first check the parameter sanity + if (MlmeScanReqSanity(pAd, +@@ -349,7 +347,6 @@ VOID MlmeJoinReqAction( + + DBGPRINT(RT_DEBUG_TRACE, ("SYNC - MlmeJoinReqAction(BSS #%ld)\n", pInfo->BssIdx)); + +-#ifdef RT2860 + if ((OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) && + (IDLE_ON(pAd)) && + (pAd->StaCfg.bRadio == TRUE) && +@@ -357,7 +354,6 @@ VOID MlmeJoinReqAction( + { + RT28xxPciAsicRadioOn(pAd, GUI_IDLE_POWER_SAVE); + } +-#endif // RT2860 // + + // reset all the timers + RTMPCancelTimer(&pAd->MlmeAux.ScanTimer, &TimerCancelled); +@@ -1300,8 +1296,6 @@ VOID PeerBeacon( + { + if (pAd->StaCfg.Adhoc20NJoined == FALSE) + { +- UCHAR ByteValue = 0; +- + pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel; + + pAd->StaCfg.Adhoc20NJoined = TRUE; +@@ -1534,13 +1528,10 @@ VOID PeerBeacon( + // 5. otherwise, put PHY back to sleep to save battery. + if (MessageToMe) + { +-#ifdef RT2860 + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) + { + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, pAd->StaCfg.BBPR3); +- // Turn clk to 80Mhz. + } +-#endif // RT2860 // + if (pAd->CommonCfg.bAPSDCapable && pAd->CommonCfg.APEdcaParm.bAPSDCapable && + pAd->CommonCfg.bAPSDAC_BE && pAd->CommonCfg.bAPSDAC_BK && pAd->CommonCfg.bAPSDAC_VI && pAd->CommonCfg.bAPSDAC_VO) + { +@@ -1551,12 +1542,10 @@ VOID PeerBeacon( + } + else if (BcastFlag && (DtimCount == 0) && OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_RECEIVE_DTIM)) + { +-#ifdef RT2860 + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) + { + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, pAd->StaCfg.BBPR3); + } +-#endif // RT2860 // + } + else if ((pAd->TxSwQueue[QID_AC_BK].Number != 0) || + (pAd->TxSwQueue[QID_AC_BE].Number != 0) || +@@ -1570,12 +1559,10 @@ VOID PeerBeacon( + { + // TODO: consider scheduled HCCA. might not be proper to use traditional DTIM-based power-saving scheme + // can we cheat here (i.e. just check MGMT & AC_BE) for better performance? +-#ifdef RT2860 + if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) + { + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, pAd->StaCfg.BBPR3); + } +-#endif // RT2860 // + } + else + { +@@ -1590,7 +1577,10 @@ VOID PeerBeacon( + + if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) + { +- AsicSleepThenAutoWakeup(pAd, TbttNumToNextWakeUp); ++ // Set a flag to go to sleep . Then after parse this RxDoneInterrupt, will go to sleep mode. ++ RTMP_SET_PSFLAG(pAd, fRTMP_PS_GO_TO_SLEEP_NOW); ++ pAd->ThisTbttNumToNextWakeUp = TbttNumToNextWakeUp; ++ //AsicSleepThenAutoWakeup(pAd, TbttNumToNextWakeUp); + } + } + } +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta/wpa.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta/wpa.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta/wpa.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta/wpa.c 2009-08-27 12:44:29.000000000 +0100 +@@ -1384,6 +1384,10 @@ VOID WpaGroupMsg1Action( + pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId].CipherAlg = CIPHER_TKIP; + else if (pAd->StaCfg.GroupCipher == Ndis802_11Encryption3Enabled) + pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId].CipherAlg = CIPHER_AES; ++ else if (pAd->StaCfg.GroupCipher == Ndis802_11GroupWEP40Enabled) ++ pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId].CipherAlg = CIPHER_WEP64; ++ else if (pAd->StaCfg.GroupCipher == Ndis802_11GroupWEP104Enabled) ++ pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId].CipherAlg = CIPHER_WEP128; + + //hex_dump("Group Key :", pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId].Key, LEN_TKIP_EK); + } +@@ -1760,7 +1764,7 @@ BOOLEAN ParseKeyData( + // Get GTK length - refer to IEEE 802.11i-2004 p.82 + GTKLEN = pKDE->Len -6; + +- if (GTKLEN < LEN_AES_KEY) ++ if (GTKLEN < MIN_LEN_OF_GTK) + { + DBGPRINT(RT_DEBUG_ERROR, ("ERROR: GTK Key length is too short (%d) \n", GTKLEN)); + return FALSE; +@@ -1786,6 +1790,10 @@ BOOLEAN ParseKeyData( + pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId].CipherAlg = CIPHER_TKIP; + else if (pAd->StaCfg.GroupCipher == Ndis802_11Encryption3Enabled) + pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId].CipherAlg = CIPHER_AES; ++ else if (pAd->StaCfg.GroupCipher == Ndis802_11GroupWEP40Enabled) ++ pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId].CipherAlg = CIPHER_WEP64; ++ else if (pAd->StaCfg.GroupCipher == Ndis802_11GroupWEP104Enabled) ++ pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId].CipherAlg = CIPHER_WEP128; + + return TRUE; + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta_ioctl.c linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta_ioctl.c +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/sta_ioctl.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/sta_ioctl.c 2009-08-27 12:44:31.000000000 +0100 +@@ -49,15 +49,9 @@ extern ULONG RTDebugLevel; + + #define GROUP_KEY_NO 4 + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + #define IWE_STREAM_ADD_EVENT(_A, _B, _C, _D, _E) iwe_stream_add_event(_A, _B, _C, _D, _E) + #define IWE_STREAM_ADD_POINT(_A, _B, _C, _D, _E) iwe_stream_add_point(_A, _B, _C, _D, _E) + #define IWE_STREAM_ADD_VALUE(_A, _B, _C, _D, _E, _F) iwe_stream_add_value(_A, _B, _C, _D, _E, _F) +-#else +-#define IWE_STREAM_ADD_EVENT(_A, _B, _C, _D, _E) iwe_stream_add_event(_B, _C, _D, _E) +-#define IWE_STREAM_ADD_POINT(_A, _B, _C, _D, _E) iwe_stream_add_point(_B, _C, _D, _E) +-#define IWE_STREAM_ADD_VALUE(_A, _B, _C, _D, _E, _F) iwe_stream_add_value(_B, _C, _D, _E, _F) +-#endif + + extern UCHAR CipherWpa2Template[]; + extern UCHAR CipherWpaPskTkip[]; +@@ -358,6 +352,20 @@ VOID RTMPAddKey( + + DBGPRINT(RT_DEBUG_TRACE, ("RTMPAddKey ------>\n")); + ++ RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP); ++ if (RTMP_TEST_PSFLAG(pAd, fRTMP_PS_SET_PCI_CLK_OFF_COMMAND)) ++ { ++ if (pAd->StaCfg.bRadio == FALSE) ++ { ++ RTMP_SET_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP); ++ return; ++ } ++ DBGPRINT(RT_DEBUG_TRACE,("RTMPWPAAddKeyProc1==>\n")); ++ RTMPPCIeLinkCtrlValueRestore(pAd, RESTORE_HALT); ++ RTMPusecDelay(6000); ++ pAd->bPCIclkOff = FALSE; ++ } ++ + if (pAd->StaCfg.AuthMode >= Ndis802_11AuthModeWPA) + { + if (pKey->KeyIndex & 0x80000000) +@@ -551,6 +559,8 @@ VOID RTMPAddKey( + } + } + end: ++ RTMP_SET_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP); ++ DBGPRINT(RT_DEBUG_INFO, ("<------ RTMPAddKey\n")); + return; + } + +@@ -571,11 +581,9 @@ rt_ioctl_giwname(struct net_device *dev, + struct iw_request_info *info, + char *name, char *extra) + { +-// PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++// PRTMP_ADAPTER pAdapter = dev->ml_priv; + +-#ifdef RT2860 + strncpy(name, "RT2860 Wireless", IFNAMSIZ); +-#endif // RT2860 // + return 0; + } + +@@ -583,7 +591,7 @@ int rt_ioctl_siwfreq(struct net_device * + struct iw_request_info *info, + struct iw_freq *freq, char *extra) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + int chan = -1; + + //check if the interface is down +@@ -623,19 +631,19 @@ int rt_ioctl_giwfreq(struct net_device * + + if (dev->priv_flags == INT_MAIN) + { +- pAdapter = dev->priv; ++ pAdapter = dev->ml_priv; + } + else + { +- pVirtualAd = dev->priv; ++ pVirtualAd = dev->ml_priv; + if (pVirtualAd && pVirtualAd->RtmpDev) +- pAdapter = pVirtualAd->RtmpDev->priv; ++ pAdapter = pVirtualAd->RtmpDev->ml_priv; + } + + if (pAdapter == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +@@ -653,7 +661,7 @@ int rt_ioctl_siwmode(struct net_device * + struct iw_request_info *info, + __u32 *mode, char *extra) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + + //check if the interface is down + if(!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) +@@ -670,11 +678,9 @@ int rt_ioctl_siwmode(struct net_device * + case IW_MODE_INFRA: + Set_NetworkType_Proc(pAdapter, "Infra"); + break; +-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,20)) + case IW_MODE_MONITOR: + Set_NetworkType_Proc(pAdapter, "Monitor"); + break; +-#endif + default: + DBGPRINT(RT_DEBUG_TRACE, ("===>rt_ioctl_siwmode::SIOCSIWMODE (unknown %d)\n", *mode)); + return -EINVAL; +@@ -695,19 +701,19 @@ int rt_ioctl_giwmode(struct net_device * + + if (dev->priv_flags == INT_MAIN) + { +- pAdapter = dev->priv; ++ pAdapter = dev->ml_priv; + } + else + { +- pVirtualAd = dev->priv; ++ pVirtualAd = dev->ml_priv; + if (pVirtualAd && pVirtualAd->RtmpDev) +- pAdapter = pVirtualAd->RtmpDev->priv; ++ pAdapter = pVirtualAd->RtmpDev->ml_priv; + } + + if (pAdapter == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +@@ -715,12 +721,10 @@ int rt_ioctl_giwmode(struct net_device * + *mode = IW_MODE_ADHOC; + else if (INFRA_ON(pAdapter)) + *mode = IW_MODE_INFRA; +-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,20)) + else if (MONITOR_ON(pAdapter)) + { + *mode = IW_MODE_MONITOR; + } +-#endif + else + *mode = IW_MODE_AUTO; + +@@ -732,7 +736,7 @@ int rt_ioctl_siwsens(struct net_device * + struct iw_request_info *info, + char *name, char *extra) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + + //check if the interface is down + if(!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) +@@ -763,19 +767,19 @@ int rt_ioctl_giwrange(struct net_device + + if (dev->priv_flags == INT_MAIN) + { +- pAdapter = dev->priv; ++ pAdapter = dev->ml_priv; + } + else + { +- pVirtualAd = dev->priv; ++ pVirtualAd = dev->ml_priv; + if (pVirtualAd && pVirtualAd->RtmpDev) +- pAdapter = pVirtualAd->RtmpDev->priv; ++ pAdapter = pVirtualAd->RtmpDev->ml_priv; + } + + if (pAdapter == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +@@ -857,7 +861,7 @@ int rt_ioctl_siwap(struct net_device *de + struct iw_request_info *info, + struct sockaddr *ap_addr, char *extra) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + NDIS_802_11_MAC_ADDRESS Bssid; + + //check if the interface is down +@@ -902,19 +906,19 @@ int rt_ioctl_giwap(struct net_device *de + + if (dev->priv_flags == INT_MAIN) + { +- pAdapter = dev->priv; ++ pAdapter = dev->ml_priv; + } + else + { +- pVirtualAd = dev->priv; ++ pVirtualAd = dev->ml_priv; + if (pVirtualAd && pVirtualAd->RtmpDev) +- pAdapter = pVirtualAd->RtmpDev->priv; ++ pAdapter = pVirtualAd->RtmpDev->ml_priv; + } + + if (pAdapter == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +@@ -984,7 +988,7 @@ int rt_ioctl_iwaplist(struct net_device + struct iw_request_info *info, + struct iw_point *data, char *extra) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + + struct sockaddr addr[IW_MAX_AP]; + struct iw_quality qual[IW_MAX_AP]; +@@ -1020,7 +1024,7 @@ int rt_ioctl_siwscan(struct net_device * + struct iw_request_info *info, + struct iw_point *data, char *extra) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + + ULONG Now; + int Status = NDIS_STATUS_SUCCESS; +@@ -1038,6 +1042,15 @@ int rt_ioctl_siwscan(struct net_device * + return -EINVAL; + } + ++ if ((pAdapter->OpMode == OPMODE_STA) && (IDLE_ON(pAdapter)) ++ && (pAdapter->StaCfg.bRadio == TRUE) ++ && (RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_IDLE_RADIO_OFF))) ++ { ++ RT28xxPciAsicRadioOn(pAdapter, GUI_IDLE_POWER_SAVE); ++ } ++ // Check if still radio off. ++ else if (pAdapter->bPCIclkOff == TRUE) ++ return 0; + + #ifdef WPA_SUPPLICANT_SUPPORT + if (pAdapter->StaCfg.WpaSupplicantUP == WPA_SUPPLICANT_ENABLE) +@@ -1102,7 +1115,7 @@ int rt_ioctl_giwscan(struct net_device * + struct iw_point *data, char *extra) + { + +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + int i=0; + char *current_ev = extra, *previous_ev = extra; + char *end_buf; +@@ -1391,7 +1404,7 @@ int rt_ioctl_siwessid(struct net_device + struct iw_request_info *info, + struct iw_point *data, char *essid) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + + //check if the interface is down + if(!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) +@@ -1437,19 +1450,19 @@ int rt_ioctl_giwessid(struct net_device + + if (dev->priv_flags == INT_MAIN) + { +- pAdapter = dev->priv; ++ pAdapter = dev->ml_priv; + } + else + { +- pVirtualAd = dev->priv; ++ pVirtualAd = dev->ml_priv; + if (pVirtualAd && pVirtualAd->RtmpDev) +- pAdapter = pVirtualAd->RtmpDev->priv; ++ pAdapter = pVirtualAd->RtmpDev->ml_priv; + } + + if (pAdapter == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +@@ -1480,7 +1493,7 @@ int rt_ioctl_siwnickn(struct net_device + struct iw_request_info *info, + struct iw_point *data, char *nickname) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + + //check if the interface is down + if(!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) +@@ -1508,19 +1521,19 @@ int rt_ioctl_giwnickn(struct net_device + + if (dev->priv_flags == INT_MAIN) + { +- pAdapter = dev->priv; ++ pAdapter = dev->ml_priv; + } + else + { +- pVirtualAd = dev->priv; ++ pVirtualAd = dev->ml_priv; + if (pVirtualAd && pVirtualAd->RtmpDev) +- pAdapter = pVirtualAd->RtmpDev->priv; ++ pAdapter = pVirtualAd->RtmpDev->ml_priv; + } + + if (pAdapter == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +@@ -1537,7 +1550,7 @@ int rt_ioctl_siwrts(struct net_device *d + struct iw_request_info *info, + struct iw_param *rts, char *extra) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + u16 val; + + //check if the interface is down +@@ -1571,19 +1584,19 @@ int rt_ioctl_giwrts(struct net_device *d + + if (dev->priv_flags == INT_MAIN) + { +- pAdapter = dev->priv; ++ pAdapter = dev->ml_priv; + } + else + { +- pVirtualAd = dev->priv; ++ pVirtualAd = dev->ml_priv; + if (pVirtualAd && pVirtualAd->RtmpDev) +- pAdapter = pVirtualAd->RtmpDev->priv; ++ pAdapter = pVirtualAd->RtmpDev->ml_priv; + } + + if (pAdapter == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +@@ -1605,7 +1618,7 @@ int rt_ioctl_siwfrag(struct net_device * + struct iw_request_info *info, + struct iw_param *frag, char *extra) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + u16 val; + + //check if the interface is down +@@ -1637,19 +1650,19 @@ int rt_ioctl_giwfrag(struct net_device * + + if (dev->priv_flags == INT_MAIN) + { +- pAdapter = dev->priv; ++ pAdapter = dev->ml_priv; + } + else + { +- pVirtualAd = dev->priv; ++ pVirtualAd = dev->ml_priv; + if (pVirtualAd && pVirtualAd->RtmpDev) +- pAdapter = pVirtualAd->RtmpDev->priv; ++ pAdapter = pVirtualAd->RtmpDev->ml_priv; + } + + if (pAdapter == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +@@ -1673,7 +1686,7 @@ int rt_ioctl_siwencode(struct net_device + struct iw_request_info *info, + struct iw_point *erq, char *extra) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + + //check if the interface is down + if(!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) +@@ -1756,7 +1769,7 @@ int rt_ioctl_siwencode(struct net_device + } + else + /* Don't complain if only change the mode */ +- if(!erq->flags & IW_ENCODE_MODE) { ++ if (!(erq->flags & IW_ENCODE_MODE)) { + return -EINVAL; + } + } +@@ -1780,19 +1793,19 @@ rt_ioctl_giwencode(struct net_device *de + + if (dev->priv_flags == INT_MAIN) + { +- pAdapter = dev->priv; ++ pAdapter = dev->ml_priv; + } + else + { +- pVirtualAd = dev->priv; ++ pVirtualAd = dev->ml_priv; + if (pVirtualAd && pVirtualAd->RtmpDev) +- pAdapter = pVirtualAd->RtmpDev->priv; ++ pAdapter = pVirtualAd->RtmpDev->ml_priv; + } + + if (pAdapter == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +@@ -1860,19 +1873,19 @@ rt_ioctl_setparam(struct net_device *dev + + if (dev->priv_flags == INT_MAIN) + { +- pAdapter = dev->priv; ++ pAdapter = dev->ml_priv; + } + else + { +- pVirtualAd = dev->priv; +- pAdapter = pVirtualAd->RtmpDev->priv; ++ pVirtualAd = dev->ml_priv; ++ pAdapter = pVirtualAd->RtmpDev->ml_priv; + } + pObj = (POS_COOKIE) pAdapter->OS_Cookie; + + if (pAdapter == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +@@ -1928,7 +1941,7 @@ rt_private_get_statistics(struct net_dev + struct iw_point *wrq, char *extra) + { + INT Status = 0; +- PRTMP_ADAPTER pAd = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAd = dev->ml_priv; + + if (extra == NULL) + { +@@ -2055,18 +2068,18 @@ rt_private_show(struct net_device *dev, + u32 subcmd = wrq->flags; + + if (dev->priv_flags == INT_MAIN) +- pAd = dev->priv; ++ pAd = dev->ml_priv; + else + { +- pVirtualAd = dev->priv; +- pAd = pVirtualAd->RtmpDev->priv; ++ pVirtualAd = dev->ml_priv; ++ pAd = pVirtualAd->RtmpDev->ml_priv; + } + pObj = (POS_COOKIE) pAd->OS_Cookie; + + if (pAd == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +@@ -2161,12 +2174,6 @@ rt_private_show(struct net_device *dev, + wrq->length = strlen(extra) + 1; // 1: size of '\0' + break; + case RAIO_ON: +- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS)) +- { +- sprintf(extra, "Scanning\n"); +- wrq->length = strlen(extra) + 1; // 1: size of '\0' +- break; +- } + pAd->StaCfg.bSwRadio = TRUE; + //if (pAd->StaCfg.bRadio != (pAd->StaCfg.bHwRadio && pAd->StaCfg.bSwRadio)) + { +@@ -2200,7 +2207,7 @@ rt_private_show(struct net_device *dev, + } + break; + default: +- DBGPRINT(RT_DEBUG_TRACE, ("%s - unknow subcmd = %d\n", __FUNCTION__, subcmd)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s - unknow subcmd = %d\n", __func__, subcmd)); + break; + } + +@@ -2213,13 +2220,13 @@ int rt_ioctl_siwmlme(struct net_device * + union iwreq_data *wrqu, + char *extra) + { +- PRTMP_ADAPTER pAd = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAd = dev->ml_priv; + struct iw_mlme *pMlme = (struct iw_mlme *)wrqu->data.pointer; + MLME_QUEUE_ELEM MsgElem; + MLME_DISASSOC_REQ_STRUCT DisAssocReq; + MLME_DEAUTH_REQ_STRUCT DeAuthReq; + +- DBGPRINT(RT_DEBUG_TRACE, ("====> %s\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE, ("====> %s\n", __func__)); + + if (pMlme == NULL) + return -EINVAL; +@@ -2228,7 +2235,7 @@ int rt_ioctl_siwmlme(struct net_device * + { + #ifdef IW_MLME_DEAUTH + case IW_MLME_DEAUTH: +- DBGPRINT(RT_DEBUG_TRACE, ("====> %s - IW_MLME_DEAUTH\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE, ("====> %s - IW_MLME_DEAUTH\n", __func__)); + COPY_MAC_ADDR(DeAuthReq.Addr, pAd->CommonCfg.Bssid); + DeAuthReq.Reason = pMlme->reason_code; + MsgElem.MsgLen = sizeof(MLME_DEAUTH_REQ_STRUCT); +@@ -2243,7 +2250,7 @@ int rt_ioctl_siwmlme(struct net_device * + #endif // IW_MLME_DEAUTH // + #ifdef IW_MLME_DISASSOC + case IW_MLME_DISASSOC: +- DBGPRINT(RT_DEBUG_TRACE, ("====> %s - IW_MLME_DISASSOC\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE, ("====> %s - IW_MLME_DISASSOC\n", __func__)); + COPY_MAC_ADDR(DisAssocReq.Addr, pAd->CommonCfg.Bssid); + DisAssocReq.Reason = pMlme->reason_code; + +@@ -2257,7 +2264,7 @@ int rt_ioctl_siwmlme(struct net_device * + break; + #endif // IW_MLME_DISASSOC // + default: +- DBGPRINT(RT_DEBUG_TRACE, ("====> %s - Unknow Command\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE, ("====> %s - Unknow Command\n", __func__)); + break; + } + +@@ -2270,7 +2277,7 @@ int rt_ioctl_siwauth(struct net_device * + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + struct iw_param *param = &wrqu->param; + + //check if the interface is down +@@ -2290,7 +2297,7 @@ int rt_ioctl_siwauth(struct net_device * + else if (param->value == IW_AUTH_WPA_VERSION_WPA2) + pAdapter->StaCfg.AuthMode = Ndis802_11AuthModeWPA2PSK; + +- DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_WPA_VERSION - param->value = %d!\n", __FUNCTION__, param->value)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_WPA_VERSION - param->value = %d!\n", __func__, param->value)); + break; + case IW_AUTH_CIPHER_PAIRWISE: + if (param->value == IW_AUTH_CIPHER_NONE) +@@ -2321,7 +2328,7 @@ int rt_ioctl_siwauth(struct net_device * + pAdapter->StaCfg.OrigWepStatus = pAdapter->StaCfg.WepStatus; + pAdapter->StaCfg.PairCipher = Ndis802_11Encryption3Enabled; + } +- DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_CIPHER_PAIRWISE - param->value = %d!\n", __FUNCTION__, param->value)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_CIPHER_PAIRWISE - param->value = %d!\n", __func__, param->value)); + break; + case IW_AUTH_CIPHER_GROUP: + if (param->value == IW_AUTH_CIPHER_NONE) +@@ -2341,7 +2348,7 @@ int rt_ioctl_siwauth(struct net_device * + { + pAdapter->StaCfg.GroupCipher = Ndis802_11Encryption3Enabled; + } +- DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_CIPHER_GROUP - param->value = %d!\n", __FUNCTION__, param->value)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_CIPHER_GROUP - param->value = %d!\n", __func__, param->value)); + break; + case IW_AUTH_KEY_MGMT: + if (param->value == IW_AUTH_KEY_MGMT_802_1X) +@@ -2370,12 +2377,12 @@ int rt_ioctl_siwauth(struct net_device * + { + STA_PORT_SECURED(pAdapter); + } +- DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_KEY_MGMT - param->value = %d!\n", __FUNCTION__, param->value)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_KEY_MGMT - param->value = %d!\n", __func__, param->value)); + break; + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + break; + case IW_AUTH_PRIVACY_INVOKED: +- DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_PRIVACY_INVOKED - param->value = %d!\n", __FUNCTION__, param->value)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_PRIVACY_INVOKED - param->value = %d!\n", __func__, param->value)); + break; + case IW_AUTH_DROP_UNENCRYPTED: + if (param->value != 0) +@@ -2384,7 +2391,7 @@ int rt_ioctl_siwauth(struct net_device * + { + STA_PORT_SECURED(pAdapter); + } +- DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_WPA_VERSION - param->value = %d!\n", __FUNCTION__, param->value)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_WPA_VERSION - param->value = %d!\n", __func__, param->value)); + break; + case IW_AUTH_80211_AUTH_ALG: + if (param->value & IW_AUTH_ALG_SHARED_KEY) +@@ -2397,10 +2404,10 @@ int rt_ioctl_siwauth(struct net_device * + } + else + return -EINVAL; +- DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_80211_AUTH_ALG - param->value = %d!\n", __FUNCTION__, param->value)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_80211_AUTH_ALG - param->value = %d!\n", __func__, param->value)); + break; + case IW_AUTH_WPA_ENABLED: +- DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_WPA_ENABLED - Driver supports WPA!(param->value = %d)\n", __FUNCTION__, param->value)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_AUTH_WPA_ENABLED - Driver supports WPA!(param->value = %d)\n", __func__, param->value)); + break; + default: + return -EOPNOTSUPP; +@@ -2413,7 +2420,7 @@ int rt_ioctl_giwauth(struct net_device * + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + struct iw_param *param = &wrqu->param; + + //check if the interface is down +@@ -2450,6 +2457,20 @@ void fnSetCipherKey( + IN BOOLEAN bGTK, + IN struct iw_encode_ext *ext) + { ++ RTMP_CLEAR_PSFLAG(pAdapter, fRTMP_PS_CAN_GO_SLEEP); ++ if (RTMP_TEST_PSFLAG(pAdapter, fRTMP_PS_SET_PCI_CLK_OFF_COMMAND)) ++ { ++ if (pAdapter->StaCfg.bRadio == FALSE) ++ { ++ RTMP_SET_PSFLAG(pAdapter, fRTMP_PS_CAN_GO_SLEEP); ++ return; ++ } ++ DBGPRINT(RT_DEBUG_TRACE,("RTMPWPAAddKeyProc1==>\n")); ++ RTMPPCIeLinkCtrlValueRestore(pAdapter, RESTORE_HALT); ++ RTMPusecDelay(6000); ++ pAdapter->bPCIclkOff = FALSE; ++ } ++ + NdisZeroMemory(&pAdapter->SharedKey[BSS0][keyIdx], sizeof(CIPHER_KEY)); + pAdapter->SharedKey[BSS0][keyIdx].KeyLen = LEN_TKIP_EK; + NdisMoveMemory(pAdapter->SharedKey[BSS0][keyIdx].Key, ext->key, LEN_TKIP_EK); +@@ -2480,6 +2501,8 @@ void fnSetCipherKey( + keyIdx, + pAdapter->SharedKey[BSS0][keyIdx].CipherAlg, + &pAdapter->MacTab.Content[BSSID_WCID]); ++ ++ RTMP_SET_PSFLAG(pAdapter, fRTMP_PS_CAN_GO_SLEEP); + } + + int rt_ioctl_siwencodeext(struct net_device *dev, +@@ -2487,7 +2510,7 @@ int rt_ioctl_siwencodeext(struct net_dev + union iwreq_data *wrqu, + char *extra) + { +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + struct iw_point *encoding = &wrqu->encoding; + struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; + int keyIdx, alg = ext->alg; +@@ -2508,7 +2531,7 @@ int rt_ioctl_siwencodeext(struct net_dev + pAdapter->SharedKey[BSS0][keyIdx].CipherAlg = CIPHER_NONE; + AsicRemoveSharedKeyEntry(pAdapter, 0, (UCHAR)keyIdx); + NdisZeroMemory(&pAdapter->SharedKey[BSS0][keyIdx], sizeof(CIPHER_KEY)); +- DBGPRINT(RT_DEBUG_TRACE, ("%s::Remove all keys!(encoding->flags = %x)\n", __FUNCTION__, encoding->flags)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::Remove all keys!(encoding->flags = %x)\n", __func__, encoding->flags)); + } + else + { +@@ -2520,15 +2543,15 @@ int rt_ioctl_siwencodeext(struct net_dev + if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) + { + pAdapter->StaCfg.DefaultKeyId = keyIdx; +- DBGPRINT(RT_DEBUG_TRACE, ("%s::DefaultKeyId = %d\n", __FUNCTION__, pAdapter->StaCfg.DefaultKeyId)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::DefaultKeyId = %d\n", __func__, pAdapter->StaCfg.DefaultKeyId)); + } + + switch (alg) { + case IW_ENCODE_ALG_NONE: +- DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_ENCODE_ALG_NONE\n", __FUNCTION__)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_ENCODE_ALG_NONE\n", __func__)); + break; + case IW_ENCODE_ALG_WEP: +- DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_ENCODE_ALG_WEP - ext->key_len = %d, keyIdx = %d\n", __FUNCTION__, ext->key_len, keyIdx)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_ENCODE_ALG_WEP - ext->key_len = %d, keyIdx = %d\n", __func__, ext->key_len, keyIdx)); + if (ext->key_len == MAX_WEP_KEY_SIZE) + { + pAdapter->SharedKey[BSS0][keyIdx].KeyLen = MAX_WEP_KEY_SIZE; +@@ -2544,9 +2567,24 @@ int rt_ioctl_siwencodeext(struct net_dev + + NdisZeroMemory(pAdapter->SharedKey[BSS0][keyIdx].Key, 16); + NdisMoveMemory(pAdapter->SharedKey[BSS0][keyIdx].Key, ext->key, ext->key_len); ++ ++ if (pAdapter->StaCfg.GroupCipher == Ndis802_11GroupWEP40Enabled || ++ pAdapter->StaCfg.GroupCipher == Ndis802_11GroupWEP104Enabled) ++ { ++ // Set Group key material to Asic ++ AsicAddSharedKeyEntry(pAdapter, BSS0, keyIdx, pAdapter->SharedKey[BSS0][keyIdx].CipherAlg, pAdapter->SharedKey[BSS0][keyIdx].Key, NULL, NULL); ++ ++ // Update WCID attribute table and IVEIV table for this group key table ++ RTMPAddWcidAttributeEntry(pAdapter, BSS0, keyIdx, pAdapter->SharedKey[BSS0][keyIdx].CipherAlg, NULL); ++ ++ STA_PORT_SECURED(pAdapter); ++ ++ // Indicate Connected for GUI ++ pAdapter->IndicateMediaState = NdisMediaStateConnected; ++ } + break; + case IW_ENCODE_ALG_TKIP: +- DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_ENCODE_ALG_TKIP - keyIdx = %d, ext->key_len = %d\n", __FUNCTION__, keyIdx, ext->key_len)); ++ DBGPRINT(RT_DEBUG_TRACE, ("%s::IW_ENCODE_ALG_TKIP - keyIdx = %d, ext->key_len = %d\n", __func__, keyIdx, ext->key_len)); + if (ext->key_len == 32) + { + if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) +@@ -2596,7 +2634,7 @@ rt_ioctl_giwencodeext(struct net_device + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + { +- PRTMP_ADAPTER pAd = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAd = dev->ml_priv; + PCHAR pKey = NULL; + struct iw_point *encoding = &wrqu->encoding; + struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; +@@ -2680,7 +2718,7 @@ int rt_ioctl_siwgenie(struct net_device + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + { +- PRTMP_ADAPTER pAd = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAd = dev->ml_priv; + + if (wrqu->data.length > MAX_LEN_OF_RSNIE || + (wrqu->data.length && extra == NULL)) +@@ -2705,7 +2743,7 @@ int rt_ioctl_giwgenie(struct net_device + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + { +- PRTMP_ADAPTER pAd = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAd = dev->ml_priv; + + if ((pAd->StaCfg.RSNIE_Len == 0) || + (pAd->StaCfg.AuthMode < Ndis802_11AuthModeWPA)) +@@ -2751,7 +2789,7 @@ int rt_ioctl_siwpmksa(struct net_device + union iwreq_data *wrqu, + char *extra) + { +- PRTMP_ADAPTER pAd = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAd = dev->ml_priv; + struct iw_pmksa *pPmksa = (struct iw_pmksa *)wrqu->data.pointer; + INT CachedIdx = 0, idx = 0; + +@@ -2834,7 +2872,7 @@ rt_private_ioctl_bbp(struct net_device * + UINT32 bbpValue; + BOOLEAN bIsPrintAllBBP = FALSE; + INT Status = 0; +- PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAdapter = dev->ml_priv; + + + memset(extra, 0x00, IW_PRIV_SIZE_MASK); +@@ -2961,7 +2999,7 @@ int rt_ioctl_siwrate(struct net_device * + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + { +- PRTMP_ADAPTER pAd = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAd = dev->ml_priv; + UINT32 rate = wrqu->bitrate.value, fixed = wrqu->bitrate.fixed; + + //check if the interface is down +@@ -3019,7 +3057,7 @@ int rt_ioctl_giwrate(struct net_device * + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + { +- PRTMP_ADAPTER pAd = (PRTMP_ADAPTER) dev->priv; ++ PRTMP_ADAPTER pAd = dev->ml_priv; + int rate_index = 0, rate_count = 0; + HTTRANSMIT_SETTING ht_setting; + __s32 ralinkrate[] = +@@ -4259,7 +4297,23 @@ INT RTMPSetInformation( + } + + #ifdef WPA_SUPPLICANT_SUPPORT +- if (pAdapter->StaCfg.PortSecured == WPA_802_1X_PORT_SECURED) ++ if ((pAdapter->StaCfg.WpaSupplicantUP != 0) && ++ (pAdapter->StaCfg.AuthMode >= Ndis802_11AuthModeWPA)) ++ { ++ Key = pWepKey->KeyMaterial; ++ ++ // Set Group key material to Asic ++ AsicAddSharedKeyEntry(pAdapter, BSS0, KeyIdx, CipherAlg, Key, NULL, NULL); ++ ++ // Update WCID attribute table and IVEIV table for this group key table ++ RTMPAddWcidAttributeEntry(pAdapter, BSS0, KeyIdx, CipherAlg, NULL); ++ ++ STA_PORT_SECURED(pAdapter); ++ ++ // Indicate Connected for GUI ++ pAdapter->IndicateMediaState = NdisMediaStateConnected; ++ } ++ else if (pAdapter->StaCfg.PortSecured == WPA_802_1X_PORT_SECURED) + #endif // WPA_SUPPLICANT_SUPPORT + { + Key = pAdapter->SharedKey[BSS0][KeyIdx].Key; +@@ -5265,7 +5319,6 @@ INT RTMPQueryInformation( + case RT_OID_802_11_PRODUCTID: + DBGPRINT(RT_DEBUG_TRACE, ("Query::RT_OID_802_11_PRODUCTID \n")); + +-#ifdef RT2860 + { + + USHORT device_id; +@@ -5275,7 +5328,6 @@ INT RTMPQueryInformation( + DBGPRINT(RT_DEBUG_TRACE, (" pci_dev = NULL\n")); + sprintf(tmp, "%04x %04x\n", NIC_PCI_VENDOR_ID, device_id); + } +-#endif // RT2860 // + wrq->u.data.length = strlen(tmp); + Status = copy_to_user(wrq->u.data.pointer, tmp, wrq->u.data.length); + break; +@@ -5409,19 +5461,19 @@ INT rt28xx_sta_ioctl( + + if (net_dev->priv_flags == INT_MAIN) + { +- pAd = net_dev->priv; ++ pAd = net_dev->ml_priv; + } + else + { +- pVirtualAd = net_dev->priv; +- pAd = pVirtualAd->RtmpDev->priv; ++ pVirtualAd = net_dev->ml_priv; ++ pAd = pVirtualAd->RtmpDev->ml_priv; + } + pObj = (POS_COOKIE) pAd->OS_Cookie; + + if (pAd == NULL) + { + /* if 1st open fail, pAd will be free; +- So the net_dev->priv will be NULL in 2rd open */ ++ So the net_dev->ml_priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/TODO linux-2.6.27.29-0.1.1/drivers/staging/rt2860/TODO +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/TODO 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/TODO 2009-08-27 12:44:29.000000000 +0100 +@@ -1,6 +1,6 @@ + I'm hesitant to add a TODO file here, as the wireless developers would + really have people help them out on the "clean" rt2860 driver that can +-be found at the rt2860.sf.net site. ++be found at the http://rt2x00.serialmonkey.com/ site. + + But, if you wish to clean up this driver instead, here's a short list of + things that need to be done to get it into a more mergable shape: +@@ -8,7 +8,7 @@ things that need to be done to get it in + TODO: + - checkpatch.pl clean + - sparse clean +- - port to in-kernel 80211 stack ++ - port to in-kernel 80211 stack and common rt2x00 infrastructure + - remove reading from /etc/ config files + - review by the wireless developer community + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rt2860/wpa.h linux-2.6.27.29-0.1.1/drivers/staging/rt2860/wpa.h +--- linux-2.6.27.25-0.1.1/drivers/staging/rt2860/wpa.h 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rt2860/wpa.h 2009-08-27 12:44:31.000000000 +0100 +@@ -90,6 +90,7 @@ + #define TKIP_AP_RXMICK_OFFSET (TKIP_AP_TXMICK_OFFSET+LEN_TKIP_TXMICK) + #define TKIP_GTK_LENGTH ((LEN_TKIP_EK)+(LEN_TKIP_RXMICK)+(LEN_TKIP_TXMICK)) + #define LEN_PTK ((LEN_EAP_KEY)+(LEN_TKIP_KEY)) ++#define MIN_LEN_OF_GTK 5 + + // RSN IE Length definition + #define MAX_LEN_OF_RSNIE 90 +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/dot11d.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/dot11d.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/dot11d.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,102 @@ ++#ifndef __INC_DOT11D_H ++#define __INC_DOT11D_H ++ ++#ifdef ENABLE_DOT11D ++#include "ieee80211.h" ++ ++//#define ENABLE_DOT11D ++ ++//#define DOT11D_MAX_CHNL_NUM 83 ++ ++typedef struct _CHNL_TXPOWER_TRIPLE { ++ u8 FirstChnl; ++ u8 NumChnls; ++ u8 MaxTxPowerInDbm; ++}CHNL_TXPOWER_TRIPLE, *PCHNL_TXPOWER_TRIPLE; ++ ++typedef enum _DOT11D_STATE { ++ DOT11D_STATE_NONE = 0, ++ DOT11D_STATE_LEARNED, ++ DOT11D_STATE_DONE, ++}DOT11D_STATE; ++ ++typedef struct _RT_DOT11D_INFO { ++ //DECLARE_RT_OBJECT(RT_DOT11D_INFO); ++ ++ bool bEnabled; // dot11MultiDomainCapabilityEnabled ++ ++ u16 CountryIeLen; // > 0 if CountryIeBuf[] contains valid country information element. ++ u8 CountryIeBuf[MAX_IE_LEN]; ++ u8 CountryIeSrcAddr[6]; // Source AP of the country IE. ++ u8 CountryIeWatchdog; ++ ++ u8 channel_map[MAX_CHANNEL_NUMBER+1]; //!!!Value 0: Invalid, 1: Valid (active scan), 2: Valid (passive scan) ++ //u8 ChnlListLen; // #Bytes valid in ChnlList[]. ++ //u8 ChnlList[DOT11D_MAX_CHNL_NUM]; ++ u8 MaxTxPwrDbmList[MAX_CHANNEL_NUMBER+1]; ++ ++ DOT11D_STATE State; ++}RT_DOT11D_INFO, *PRT_DOT11D_INFO; ++#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 ) ++#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5]) ++#define GET_DOT11D_INFO(__pIeeeDev) ((PRT_DOT11D_INFO)((__pIeeeDev)->pDot11dInfo)) ++ ++#define IS_DOT11D_ENABLE(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->bEnabled ++#define IS_COUNTRY_IE_VALID(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen > 0) ++ ++#define IS_EQUAL_CIE_SRC(__pIeeeDev, __pTa) eqMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa) ++#define UPDATE_CIE_SRC(__pIeeeDev, __pTa) cpMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa) ++ ++#define IS_COUNTRY_IE_CHANGED(__pIeeeDev, __Ie) \ ++ (((__Ie).Length == 0 || (__Ie).Length != GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen) ? \ ++ FALSE : \ ++ (!memcmp(GET_DOT11D_INFO(__pIeeeDev)->CountryIeBuf, (__Ie).Octet, (__Ie).Length))) ++ ++#define CIE_WATCHDOG_TH 1 ++#define GET_CIE_WATCHDOG(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->CountryIeWatchdog ++#define RESET_CIE_WATCHDOG(__pIeeeDev) GET_CIE_WATCHDOG(__pIeeeDev) = 0 ++#define UPDATE_CIE_WATCHDOG(__pIeeeDev) ++GET_CIE_WATCHDOG(__pIeeeDev) ++ ++#define IS_DOT11D_STATE_DONE(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->State == DOT11D_STATE_DONE) ++ ++ ++void ++Dot11d_Init( ++ struct ieee80211_device *dev ++ ); ++ ++void ++Dot11d_Reset( ++ struct ieee80211_device *dev ++ ); ++ ++void ++Dot11d_UpdateCountryIe( ++ struct ieee80211_device *dev, ++ u8 * pTaddr, ++ u16 CoutryIeLen, ++ u8 * pCoutryIe ++ ); ++ ++u8 ++DOT11D_GetMaxTxPwrInDbm( ++ struct ieee80211_device *dev, ++ u8 Channel ++ ); ++ ++void ++DOT11D_ScanComplete( ++ struct ieee80211_device * dev ++ ); ++ ++int IsLegalChannel( ++ struct ieee80211_device * dev, ++ u8 channel ++); ++ ++int ToLegalChannel( ++ struct ieee80211_device * dev, ++ u8 channel ++); ++#endif //ENABLE_DOT11D ++#endif // #ifndef __INC_DOT11D_H +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/aes.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/aes.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/aes.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,469 @@ ++/* ++ * Cryptographic API. ++ * ++ * AES Cipher Algorithm. ++ * ++ * Based on Brian Gladman's code. ++ * ++ * Linux developers: ++ * Alexander Kjeldaas ++ * Herbert Valerio Riedel ++ * Kyle McMartin ++ * Adam J. Richter (conversion to 2.5 API). ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * --------------------------------------------------------------------------- ++ * Copyright (c) 2002, Dr Brian Gladman , Worcester, UK. ++ * All rights reserved. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ * --------------------------------------------------------------------------- ++ */ ++ ++/* Some changes from the Gladman version: ++ s/RIJNDAEL(e_key)/E_KEY/g ++ s/RIJNDAEL(d_key)/D_KEY/g ++*/ ++ ++#include ++#include ++#include ++#include ++//#include ++#include "rtl_crypto.h" ++#include ++ ++#define AES_MIN_KEY_SIZE 16 ++#define AES_MAX_KEY_SIZE 32 ++ ++#define AES_BLOCK_SIZE 16 ++ ++static inline ++u32 generic_rotr32 (const u32 x, const unsigned bits) ++{ ++ const unsigned n = bits % 32; ++ return (x >> n) | (x << (32 - n)); ++} ++ ++static inline ++u32 generic_rotl32 (const u32 x, const unsigned bits) ++{ ++ const unsigned n = bits % 32; ++ return (x << n) | (x >> (32 - n)); ++} ++ ++#define rotl generic_rotl32 ++#define rotr generic_rotr32 ++ ++/* ++ * #define byte(x, nr) ((unsigned char)((x) >> (nr*8))) ++ */ ++inline static u8 ++byte(const u32 x, const unsigned n) ++{ ++ return x >> (n << 3); ++} ++ ++#define u32_in(x) le32_to_cpu(*(const u32 *)(x)) ++#define u32_out(to, from) (*(u32 *)(to) = cpu_to_le32(from)) ++ ++struct aes_ctx { ++ int key_length; ++ u32 E[60]; ++ u32 D[60]; ++}; ++ ++#define E_KEY ctx->E ++#define D_KEY ctx->D ++ ++static u8 pow_tab[256] __initdata; ++static u8 log_tab[256] __initdata; ++static u8 sbx_tab[256] __initdata; ++static u8 isb_tab[256] __initdata; ++static u32 rco_tab[10]; ++static u32 ft_tab[4][256]; ++static u32 it_tab[4][256]; ++ ++static u32 fl_tab[4][256]; ++static u32 il_tab[4][256]; ++ ++static inline u8 __init ++f_mult (u8 a, u8 b) ++{ ++ u8 aa = log_tab[a], cc = aa + log_tab[b]; ++ ++ return pow_tab[cc + (cc < aa ? 1 : 0)]; ++} ++ ++#define ff_mult(a,b) (a && b ? f_mult(a, b) : 0) ++ ++#define f_rn(bo, bi, n, k) \ ++ bo[n] = ft_tab[0][byte(bi[n],0)] ^ \ ++ ft_tab[1][byte(bi[(n + 1) & 3],1)] ^ \ ++ ft_tab[2][byte(bi[(n + 2) & 3],2)] ^ \ ++ ft_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n) ++ ++#define i_rn(bo, bi, n, k) \ ++ bo[n] = it_tab[0][byte(bi[n],0)] ^ \ ++ it_tab[1][byte(bi[(n + 3) & 3],1)] ^ \ ++ it_tab[2][byte(bi[(n + 2) & 3],2)] ^ \ ++ it_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n) ++ ++#define ls_box(x) \ ++ ( fl_tab[0][byte(x, 0)] ^ \ ++ fl_tab[1][byte(x, 1)] ^ \ ++ fl_tab[2][byte(x, 2)] ^ \ ++ fl_tab[3][byte(x, 3)] ) ++ ++#define f_rl(bo, bi, n, k) \ ++ bo[n] = fl_tab[0][byte(bi[n],0)] ^ \ ++ fl_tab[1][byte(bi[(n + 1) & 3],1)] ^ \ ++ fl_tab[2][byte(bi[(n + 2) & 3],2)] ^ \ ++ fl_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n) ++ ++#define i_rl(bo, bi, n, k) \ ++ bo[n] = il_tab[0][byte(bi[n],0)] ^ \ ++ il_tab[1][byte(bi[(n + 3) & 3],1)] ^ \ ++ il_tab[2][byte(bi[(n + 2) & 3],2)] ^ \ ++ il_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n) ++ ++static void __init ++gen_tabs (void) ++{ ++ u32 i, t; ++ u8 p, q; ++ ++ /* log and power tables for GF(2**8) finite field with ++ 0x011b as modular polynomial - the simplest primitive ++ root is 0x03, used here to generate the tables */ ++ ++ for (i = 0, p = 1; i < 256; ++i) { ++ pow_tab[i] = (u8) p; ++ log_tab[p] = (u8) i; ++ ++ p ^= (p << 1) ^ (p & 0x80 ? 0x01b : 0); ++ } ++ ++ log_tab[1] = 0; ++ ++ for (i = 0, p = 1; i < 10; ++i) { ++ rco_tab[i] = p; ++ ++ p = (p << 1) ^ (p & 0x80 ? 0x01b : 0); ++ } ++ ++ for (i = 0; i < 256; ++i) { ++ p = (i ? pow_tab[255 - log_tab[i]] : 0); ++ q = ((p >> 7) | (p << 1)) ^ ((p >> 6) | (p << 2)); ++ p ^= 0x63 ^ q ^ ((q >> 6) | (q << 2)); ++ sbx_tab[i] = p; ++ isb_tab[p] = (u8) i; ++ } ++ ++ for (i = 0; i < 256; ++i) { ++ p = sbx_tab[i]; ++ ++ t = p; ++ fl_tab[0][i] = t; ++ fl_tab[1][i] = rotl (t, 8); ++ fl_tab[2][i] = rotl (t, 16); ++ fl_tab[3][i] = rotl (t, 24); ++ ++ t = ((u32) ff_mult (2, p)) | ++ ((u32) p << 8) | ++ ((u32) p << 16) | ((u32) ff_mult (3, p) << 24); ++ ++ ft_tab[0][i] = t; ++ ft_tab[1][i] = rotl (t, 8); ++ ft_tab[2][i] = rotl (t, 16); ++ ft_tab[3][i] = rotl (t, 24); ++ ++ p = isb_tab[i]; ++ ++ t = p; ++ il_tab[0][i] = t; ++ il_tab[1][i] = rotl (t, 8); ++ il_tab[2][i] = rotl (t, 16); ++ il_tab[3][i] = rotl (t, 24); ++ ++ t = ((u32) ff_mult (14, p)) | ++ ((u32) ff_mult (9, p) << 8) | ++ ((u32) ff_mult (13, p) << 16) | ++ ((u32) ff_mult (11, p) << 24); ++ ++ it_tab[0][i] = t; ++ it_tab[1][i] = rotl (t, 8); ++ it_tab[2][i] = rotl (t, 16); ++ it_tab[3][i] = rotl (t, 24); ++ } ++} ++ ++#define star_x(x) (((x) & 0x7f7f7f7f) << 1) ^ ((((x) & 0x80808080) >> 7) * 0x1b) ++ ++#define imix_col(y,x) \ ++ u = star_x(x); \ ++ v = star_x(u); \ ++ w = star_x(v); \ ++ t = w ^ (x); \ ++ (y) = u ^ v ^ w; \ ++ (y) ^= rotr(u ^ t, 8) ^ \ ++ rotr(v ^ t, 16) ^ \ ++ rotr(t,24) ++ ++/* initialise the key schedule from the user supplied key */ ++ ++#define loop4(i) \ ++{ t = rotr(t, 8); t = ls_box(t) ^ rco_tab[i]; \ ++ t ^= E_KEY[4 * i]; E_KEY[4 * i + 4] = t; \ ++ t ^= E_KEY[4 * i + 1]; E_KEY[4 * i + 5] = t; \ ++ t ^= E_KEY[4 * i + 2]; E_KEY[4 * i + 6] = t; \ ++ t ^= E_KEY[4 * i + 3]; E_KEY[4 * i + 7] = t; \ ++} ++ ++#define loop6(i) \ ++{ t = rotr(t, 8); t = ls_box(t) ^ rco_tab[i]; \ ++ t ^= E_KEY[6 * i]; E_KEY[6 * i + 6] = t; \ ++ t ^= E_KEY[6 * i + 1]; E_KEY[6 * i + 7] = t; \ ++ t ^= E_KEY[6 * i + 2]; E_KEY[6 * i + 8] = t; \ ++ t ^= E_KEY[6 * i + 3]; E_KEY[6 * i + 9] = t; \ ++ t ^= E_KEY[6 * i + 4]; E_KEY[6 * i + 10] = t; \ ++ t ^= E_KEY[6 * i + 5]; E_KEY[6 * i + 11] = t; \ ++} ++ ++#define loop8(i) \ ++{ t = rotr(t, 8); ; t = ls_box(t) ^ rco_tab[i]; \ ++ t ^= E_KEY[8 * i]; E_KEY[8 * i + 8] = t; \ ++ t ^= E_KEY[8 * i + 1]; E_KEY[8 * i + 9] = t; \ ++ t ^= E_KEY[8 * i + 2]; E_KEY[8 * i + 10] = t; \ ++ t ^= E_KEY[8 * i + 3]; E_KEY[8 * i + 11] = t; \ ++ t = E_KEY[8 * i + 4] ^ ls_box(t); \ ++ E_KEY[8 * i + 12] = t; \ ++ t ^= E_KEY[8 * i + 5]; E_KEY[8 * i + 13] = t; \ ++ t ^= E_KEY[8 * i + 6]; E_KEY[8 * i + 14] = t; \ ++ t ^= E_KEY[8 * i + 7]; E_KEY[8 * i + 15] = t; \ ++} ++ ++static int ++aes_set_key(void *ctx_arg, const u8 *in_key, unsigned int key_len, u32 *flags) ++{ ++ struct aes_ctx *ctx = ctx_arg; ++ u32 i, t, u, v, w; ++ ++ if (key_len != 16 && key_len != 24 && key_len != 32) { ++ *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; ++ return -EINVAL; ++ } ++ ++ ctx->key_length = key_len; ++ ++ E_KEY[0] = u32_in (in_key); ++ E_KEY[1] = u32_in (in_key + 4); ++ E_KEY[2] = u32_in (in_key + 8); ++ E_KEY[3] = u32_in (in_key + 12); ++ ++ switch (key_len) { ++ case 16: ++ t = E_KEY[3]; ++ for (i = 0; i < 10; ++i) ++ loop4 (i); ++ break; ++ ++ case 24: ++ E_KEY[4] = u32_in (in_key + 16); ++ t = E_KEY[5] = u32_in (in_key + 20); ++ for (i = 0; i < 8; ++i) ++ loop6 (i); ++ break; ++ ++ case 32: ++ E_KEY[4] = u32_in (in_key + 16); ++ E_KEY[5] = u32_in (in_key + 20); ++ E_KEY[6] = u32_in (in_key + 24); ++ t = E_KEY[7] = u32_in (in_key + 28); ++ for (i = 0; i < 7; ++i) ++ loop8 (i); ++ break; ++ } ++ ++ D_KEY[0] = E_KEY[0]; ++ D_KEY[1] = E_KEY[1]; ++ D_KEY[2] = E_KEY[2]; ++ D_KEY[3] = E_KEY[3]; ++ ++ for (i = 4; i < key_len + 24; ++i) { ++ imix_col (D_KEY[i], E_KEY[i]); ++ } ++ ++ return 0; ++} ++ ++/* encrypt a block of text */ ++ ++#define f_nround(bo, bi, k) \ ++ f_rn(bo, bi, 0, k); \ ++ f_rn(bo, bi, 1, k); \ ++ f_rn(bo, bi, 2, k); \ ++ f_rn(bo, bi, 3, k); \ ++ k += 4 ++ ++#define f_lround(bo, bi, k) \ ++ f_rl(bo, bi, 0, k); \ ++ f_rl(bo, bi, 1, k); \ ++ f_rl(bo, bi, 2, k); \ ++ f_rl(bo, bi, 3, k) ++ ++static void aes_encrypt(void *ctx_arg, u8 *out, const u8 *in) ++{ ++ const struct aes_ctx *ctx = ctx_arg; ++ u32 b0[4], b1[4]; ++ const u32 *kp = E_KEY + 4; ++ ++ b0[0] = u32_in (in) ^ E_KEY[0]; ++ b0[1] = u32_in (in + 4) ^ E_KEY[1]; ++ b0[2] = u32_in (in + 8) ^ E_KEY[2]; ++ b0[3] = u32_in (in + 12) ^ E_KEY[3]; ++ ++ if (ctx->key_length > 24) { ++ f_nround (b1, b0, kp); ++ f_nround (b0, b1, kp); ++ } ++ ++ if (ctx->key_length > 16) { ++ f_nround (b1, b0, kp); ++ f_nround (b0, b1, kp); ++ } ++ ++ f_nround (b1, b0, kp); ++ f_nround (b0, b1, kp); ++ f_nround (b1, b0, kp); ++ f_nround (b0, b1, kp); ++ f_nround (b1, b0, kp); ++ f_nround (b0, b1, kp); ++ f_nround (b1, b0, kp); ++ f_nround (b0, b1, kp); ++ f_nround (b1, b0, kp); ++ f_lround (b0, b1, kp); ++ ++ u32_out (out, b0[0]); ++ u32_out (out + 4, b0[1]); ++ u32_out (out + 8, b0[2]); ++ u32_out (out + 12, b0[3]); ++} ++ ++/* decrypt a block of text */ ++ ++#define i_nround(bo, bi, k) \ ++ i_rn(bo, bi, 0, k); \ ++ i_rn(bo, bi, 1, k); \ ++ i_rn(bo, bi, 2, k); \ ++ i_rn(bo, bi, 3, k); \ ++ k -= 4 ++ ++#define i_lround(bo, bi, k) \ ++ i_rl(bo, bi, 0, k); \ ++ i_rl(bo, bi, 1, k); \ ++ i_rl(bo, bi, 2, k); \ ++ i_rl(bo, bi, 3, k) ++ ++static void aes_decrypt(void *ctx_arg, u8 *out, const u8 *in) ++{ ++ const struct aes_ctx *ctx = ctx_arg; ++ u32 b0[4], b1[4]; ++ const int key_len = ctx->key_length; ++ const u32 *kp = D_KEY + key_len + 20; ++ ++ b0[0] = u32_in (in) ^ E_KEY[key_len + 24]; ++ b0[1] = u32_in (in + 4) ^ E_KEY[key_len + 25]; ++ b0[2] = u32_in (in + 8) ^ E_KEY[key_len + 26]; ++ b0[3] = u32_in (in + 12) ^ E_KEY[key_len + 27]; ++ ++ if (key_len > 24) { ++ i_nround (b1, b0, kp); ++ i_nround (b0, b1, kp); ++ } ++ ++ if (key_len > 16) { ++ i_nround (b1, b0, kp); ++ i_nround (b0, b1, kp); ++ } ++ ++ i_nround (b1, b0, kp); ++ i_nround (b0, b1, kp); ++ i_nround (b1, b0, kp); ++ i_nround (b0, b1, kp); ++ i_nround (b1, b0, kp); ++ i_nround (b0, b1, kp); ++ i_nround (b1, b0, kp); ++ i_nround (b0, b1, kp); ++ i_nround (b1, b0, kp); ++ i_lround (b0, b1, kp); ++ ++ u32_out (out, b0[0]); ++ u32_out (out + 4, b0[1]); ++ u32_out (out + 8, b0[2]); ++ u32_out (out + 12, b0[3]); ++} ++ ++ ++static struct crypto_alg aes_alg = { ++ .cra_name = "aes", ++ .cra_flags = CRYPTO_ALG_TYPE_CIPHER, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct aes_ctx), ++ .cra_module = THIS_MODULE, ++ .cra_list = LIST_HEAD_INIT(aes_alg.cra_list), ++ .cra_u = { ++ .cipher = { ++ .cia_min_keysize = AES_MIN_KEY_SIZE, ++ .cia_max_keysize = AES_MAX_KEY_SIZE, ++ .cia_setkey = aes_set_key, ++ .cia_encrypt = aes_encrypt, ++ .cia_decrypt = aes_decrypt ++ } ++ } ++}; ++ ++static int __init aes_init(void) ++{ ++ gen_tabs(); ++ return crypto_register_alg(&aes_alg); ++} ++ ++static void __exit aes_fini(void) ++{ ++ crypto_unregister_alg(&aes_alg); ++} ++ ++module_init(aes_init); ++module_exit(aes_fini); ++ ++MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm"); ++MODULE_LICENSE("Dual BSD/GPL"); ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/api.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/api.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/api.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,246 @@ ++/* ++ * Scatterlist Cryptographic API. ++ * ++ * Copyright (c) 2002 James Morris ++ * Copyright (c) 2002 David S. Miller (davem@redhat.com) ++ * ++ * Portions derived from Cryptoapi, by Alexander Kjeldaas ++ * and Nettle, by Niels M鰈ler. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at your option) ++ * any later version. ++ * ++ */ ++#include "kmap_types.h" ++ ++#include ++#include ++//#include ++#include "rtl_crypto.h" ++#include ++#include ++#include ++#include "internal.h" ++ ++LIST_HEAD(crypto_alg_list); ++DECLARE_RWSEM(crypto_alg_sem); ++ ++static inline int crypto_alg_get(struct crypto_alg *alg) ++{ ++ return try_inc_mod_count(alg->cra_module); ++} ++ ++static inline void crypto_alg_put(struct crypto_alg *alg) ++{ ++ if (alg->cra_module) ++ __MOD_DEC_USE_COUNT(alg->cra_module); ++} ++ ++struct crypto_alg *crypto_alg_lookup(const char *name) ++{ ++ struct crypto_alg *q, *alg = NULL; ++ ++ if (!name) ++ return NULL; ++ ++ down_read(&crypto_alg_sem); ++ ++ list_for_each_entry(q, &crypto_alg_list, cra_list) { ++ if (!(strcmp(q->cra_name, name))) { ++ if (crypto_alg_get(q)) ++ alg = q; ++ break; ++ } ++ } ++ ++ up_read(&crypto_alg_sem); ++ return alg; ++} ++ ++static int crypto_init_flags(struct crypto_tfm *tfm, u32 flags) ++{ ++ tfm->crt_flags = 0; ++ ++ switch (crypto_tfm_alg_type(tfm)) { ++ case CRYPTO_ALG_TYPE_CIPHER: ++ return crypto_init_cipher_flags(tfm, flags); ++ ++ case CRYPTO_ALG_TYPE_DIGEST: ++ return crypto_init_digest_flags(tfm, flags); ++ ++ case CRYPTO_ALG_TYPE_COMPRESS: ++ return crypto_init_compress_flags(tfm, flags); ++ ++ default: ++ break; ++ } ++ ++ BUG(); ++ return -EINVAL; ++} ++ ++static int crypto_init_ops(struct crypto_tfm *tfm) ++{ ++ switch (crypto_tfm_alg_type(tfm)) { ++ case CRYPTO_ALG_TYPE_CIPHER: ++ return crypto_init_cipher_ops(tfm); ++ ++ case CRYPTO_ALG_TYPE_DIGEST: ++ return crypto_init_digest_ops(tfm); ++ ++ case CRYPTO_ALG_TYPE_COMPRESS: ++ return crypto_init_compress_ops(tfm); ++ ++ default: ++ break; ++ } ++ ++ BUG(); ++ return -EINVAL; ++} ++ ++static void crypto_exit_ops(struct crypto_tfm *tfm) ++{ ++ switch (crypto_tfm_alg_type(tfm)) { ++ case CRYPTO_ALG_TYPE_CIPHER: ++ crypto_exit_cipher_ops(tfm); ++ break; ++ ++ case CRYPTO_ALG_TYPE_DIGEST: ++ crypto_exit_digest_ops(tfm); ++ break; ++ ++ case CRYPTO_ALG_TYPE_COMPRESS: ++ crypto_exit_compress_ops(tfm); ++ break; ++ ++ default: ++ BUG(); ++ ++ } ++} ++ ++struct crypto_tfm *crypto_alloc_tfm(const char *name, u32 flags) ++{ ++ struct crypto_tfm *tfm = NULL; ++ struct crypto_alg *alg; ++ ++ alg = crypto_alg_mod_lookup(name); ++ if (alg == NULL) ++ goto out; ++ ++ tfm = kmalloc(sizeof(*tfm) + alg->cra_ctxsize, GFP_KERNEL); ++ if (tfm == NULL) ++ goto out_put; ++ ++ memset(tfm, 0, sizeof(*tfm) + alg->cra_ctxsize); ++ ++ tfm->__crt_alg = alg; ++ ++ if (crypto_init_flags(tfm, flags)) ++ goto out_free_tfm; ++ ++ if (crypto_init_ops(tfm)) { ++ crypto_exit_ops(tfm); ++ goto out_free_tfm; ++ } ++ ++ goto out; ++ ++out_free_tfm: ++ kfree(tfm); ++ tfm = NULL; ++out_put: ++ crypto_alg_put(alg); ++out: ++ return tfm; ++} ++ ++void crypto_free_tfm(struct crypto_tfm *tfm) ++{ ++ struct crypto_alg *alg = tfm->__crt_alg; ++ int size = sizeof(*tfm) + alg->cra_ctxsize; ++ ++ crypto_exit_ops(tfm); ++ crypto_alg_put(alg); ++ memset(tfm, 0, size); ++ kfree(tfm); ++} ++ ++int crypto_register_alg(struct crypto_alg *alg) ++{ ++ int ret = 0; ++ struct crypto_alg *q; ++ ++ down_write(&crypto_alg_sem); ++ ++ list_for_each_entry(q, &crypto_alg_list, cra_list) { ++ if (!(strcmp(q->cra_name, alg->cra_name))) { ++ ret = -EEXIST; ++ goto out; ++ } ++ } ++ ++ list_add_tail(&alg->cra_list, &crypto_alg_list); ++out: ++ up_write(&crypto_alg_sem); ++ return ret; ++} ++ ++int crypto_unregister_alg(struct crypto_alg *alg) ++{ ++ int ret = -ENOENT; ++ struct crypto_alg *q; ++ ++ BUG_ON(!alg->cra_module); ++ ++ down_write(&crypto_alg_sem); ++ list_for_each_entry(q, &crypto_alg_list, cra_list) { ++ if (alg == q) { ++ list_del(&alg->cra_list); ++ ret = 0; ++ goto out; ++ } ++ } ++out: ++ up_write(&crypto_alg_sem); ++ return ret; ++} ++ ++int crypto_alg_available(const char *name, u32 flags) ++{ ++ int ret = 0; ++ struct crypto_alg *alg = crypto_alg_mod_lookup(name); ++ ++ if (alg) { ++ crypto_alg_put(alg); ++ ret = 1; ++ } ++ ++ return ret; ++} ++ ++static int __init init_crypto(void) ++{ ++ printk(KERN_INFO "Initializing Cryptographic API\n"); ++ crypto_init_proc(); ++ return 0; ++} ++ ++__initcall(init_crypto); ++ ++/* ++EXPORT_SYMBOL_GPL(crypto_register_alg); ++EXPORT_SYMBOL_GPL(crypto_unregister_alg); ++EXPORT_SYMBOL_GPL(crypto_alloc_tfm); ++EXPORT_SYMBOL_GPL(crypto_free_tfm); ++EXPORT_SYMBOL_GPL(crypto_alg_available); ++*/ ++ ++EXPORT_SYMBOL_NOVERS(crypto_register_alg); ++EXPORT_SYMBOL_NOVERS(crypto_unregister_alg); ++EXPORT_SYMBOL_NOVERS(crypto_alloc_tfm); ++EXPORT_SYMBOL_NOVERS(crypto_free_tfm); ++EXPORT_SYMBOL_NOVERS(crypto_alg_available); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/arc4.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/arc4.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/arc4.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,103 @@ ++/* ++ * Cryptographic API ++ * ++ * ARC4 Cipher Algorithm ++ * ++ * Jon Oberheide ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#include ++#include ++#include "rtl_crypto.h" ++ ++#define ARC4_MIN_KEY_SIZE 1 ++#define ARC4_MAX_KEY_SIZE 256 ++#define ARC4_BLOCK_SIZE 1 ++ ++struct arc4_ctx { ++ u8 S[256]; ++ u8 x, y; ++}; ++ ++static int arc4_set_key(void *ctx_arg, const u8 *in_key, unsigned int key_len, u32 *flags) ++{ ++ struct arc4_ctx *ctx = ctx_arg; ++ int i, j = 0, k = 0; ++ ++ ctx->x = 1; ++ ctx->y = 0; ++ ++ for(i = 0; i < 256; i++) ++ ctx->S[i] = i; ++ ++ for(i = 0; i < 256; i++) ++ { ++ u8 a = ctx->S[i]; ++ j = (j + in_key[k] + a) & 0xff; ++ ctx->S[i] = ctx->S[j]; ++ ctx->S[j] = a; ++ if((unsigned int)++k >= key_len) ++ k = 0; ++ } ++ ++ return 0; ++} ++ ++static void arc4_crypt(void *ctx_arg, u8 *out, const u8 *in) ++{ ++ struct arc4_ctx *ctx = ctx_arg; ++ ++ u8 *const S = ctx->S; ++ u8 x = ctx->x; ++ u8 y = ctx->y; ++ u8 a, b; ++ ++ a = S[x]; ++ y = (y + a) & 0xff; ++ b = S[y]; ++ S[x] = b; ++ S[y] = a; ++ x = (x + 1) & 0xff; ++ *out++ = *in ^ S[(a + b) & 0xff]; ++ ++ ctx->x = x; ++ ctx->y = y; ++} ++ ++static struct crypto_alg arc4_alg = { ++ .cra_name = "arc4", ++ .cra_flags = CRYPTO_ALG_TYPE_CIPHER, ++ .cra_blocksize = ARC4_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct arc4_ctx), ++ .cra_module = THIS_MODULE, ++ .cra_list = LIST_HEAD_INIT(arc4_alg.cra_list), ++ .cra_u = { .cipher = { ++ .cia_min_keysize = ARC4_MIN_KEY_SIZE, ++ .cia_max_keysize = ARC4_MAX_KEY_SIZE, ++ .cia_setkey = arc4_set_key, ++ .cia_encrypt = arc4_crypt, ++ .cia_decrypt = arc4_crypt } } ++}; ++ ++static int __init arc4_init(void) ++{ ++ return crypto_register_alg(&arc4_alg); ++} ++ ++ ++static void __exit arc4_exit(void) ++{ ++ crypto_unregister_alg(&arc4_alg); ++} ++ ++module_init(arc4_init); ++module_exit(arc4_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("ARC4 Cipher Algorithm"); ++MODULE_AUTHOR("Jon Oberheide "); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/autoload.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/autoload.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/autoload.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,40 @@ ++/* ++ * Cryptographic API. ++ * ++ * Algorithm autoloader. ++ * ++ * Copyright (c) 2002 James Morris ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at your option) ++ * any later version. ++ * ++ */ ++#include "kmap_types.h" ++ ++#include ++//#include ++#include "rtl_crypto.h" ++#include ++#include ++#include "internal.h" ++ ++/* ++ * A far more intelligent version of this is planned. For now, just ++ * try an exact match on the name of the algorithm. ++ */ ++void crypto_alg_autoload(const char *name) ++{ ++ request_module(name); ++} ++ ++struct crypto_alg *crypto_alg_mod_lookup(const char *name) ++{ ++ struct crypto_alg *alg = crypto_alg_lookup(name); ++ if (alg == NULL) { ++ crypto_alg_autoload(name); ++ alg = crypto_alg_lookup(name); ++ } ++ return alg; ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/cipher.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/cipher.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/cipher.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,299 @@ ++/* ++ * Cryptographic API. ++ * ++ * Cipher operations. ++ * ++ * Copyright (c) 2002 James Morris ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at your option) ++ * any later version. ++ * ++ */ ++#include ++//#include ++#include "rtl_crypto.h" ++#include ++#include ++#include ++#include ++#include "internal.h" ++#include "scatterwalk.h" ++ ++typedef void (cryptfn_t)(void *, u8 *, const u8 *); ++typedef void (procfn_t)(struct crypto_tfm *, u8 *, ++ u8*, cryptfn_t, int enc, void *, int); ++ ++static inline void xor_64(u8 *a, const u8 *b) ++{ ++ ((u32 *)a)[0] ^= ((u32 *)b)[0]; ++ ((u32 *)a)[1] ^= ((u32 *)b)[1]; ++} ++ ++static inline void xor_128(u8 *a, const u8 *b) ++{ ++ ((u32 *)a)[0] ^= ((u32 *)b)[0]; ++ ((u32 *)a)[1] ^= ((u32 *)b)[1]; ++ ((u32 *)a)[2] ^= ((u32 *)b)[2]; ++ ((u32 *)a)[3] ^= ((u32 *)b)[3]; ++} ++ ++ ++/* ++ * Generic encrypt/decrypt wrapper for ciphers, handles operations across ++ * multiple page boundaries by using temporary blocks. In user context, ++ * the kernel is given a chance to schedule us once per block. ++ */ ++static int crypt(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes, cryptfn_t crfn, ++ procfn_t prfn, int enc, void *info) ++{ ++ struct scatter_walk walk_in, walk_out; ++ const unsigned int bsize = crypto_tfm_alg_blocksize(tfm); ++ u8 tmp_src[bsize]; ++ u8 tmp_dst[bsize]; ++ ++ if (!nbytes) ++ return 0; ++ ++ if (nbytes % bsize) { ++ tfm->crt_flags |= CRYPTO_TFM_RES_BAD_BLOCK_LEN; ++ return -EINVAL; ++ } ++ ++ scatterwalk_start(&walk_in, src); ++ scatterwalk_start(&walk_out, dst); ++ ++ for(;;) { ++ u8 *src_p, *dst_p; ++ int in_place; ++ ++ scatterwalk_map(&walk_in, 0); ++ scatterwalk_map(&walk_out, 1); ++ src_p = scatterwalk_whichbuf(&walk_in, bsize, tmp_src); ++ dst_p = scatterwalk_whichbuf(&walk_out, bsize, tmp_dst); ++ in_place = scatterwalk_samebuf(&walk_in, &walk_out, ++ src_p, dst_p); ++ ++ nbytes -= bsize; ++ ++ scatterwalk_copychunks(src_p, &walk_in, bsize, 0); ++ ++ prfn(tfm, dst_p, src_p, crfn, enc, info, in_place); ++ ++ scatterwalk_done(&walk_in, 0, nbytes); ++ ++ scatterwalk_copychunks(dst_p, &walk_out, bsize, 1); ++ scatterwalk_done(&walk_out, 1, nbytes); ++ ++ if (!nbytes) ++ return 0; ++ ++ crypto_yield(tfm); ++ } ++} ++ ++static void cbc_process(struct crypto_tfm *tfm, u8 *dst, u8 *src, ++ cryptfn_t fn, int enc, void *info, int in_place) ++{ ++ u8 *iv = info; ++ ++ /* Null encryption */ ++ if (!iv) ++ return; ++ ++ if (enc) { ++ tfm->crt_u.cipher.cit_xor_block(iv, src); ++ fn(crypto_tfm_ctx(tfm), dst, iv); ++ memcpy(iv, dst, crypto_tfm_alg_blocksize(tfm)); ++ } else { ++ u8 stack[in_place ? crypto_tfm_alg_blocksize(tfm) : 0]; ++ u8 *buf = in_place ? stack : dst; ++ ++ fn(crypto_tfm_ctx(tfm), buf, src); ++ tfm->crt_u.cipher.cit_xor_block(buf, iv); ++ memcpy(iv, src, crypto_tfm_alg_blocksize(tfm)); ++ if (buf != dst) ++ memcpy(dst, buf, crypto_tfm_alg_blocksize(tfm)); ++ } ++} ++ ++static void ecb_process(struct crypto_tfm *tfm, u8 *dst, u8 *src, ++ cryptfn_t fn, int enc, void *info, int in_place) ++{ ++ fn(crypto_tfm_ctx(tfm), dst, src); ++} ++ ++static int setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen) ++{ ++ struct cipher_alg *cia = &tfm->__crt_alg->cra_cipher; ++ ++ if (keylen < cia->cia_min_keysize || keylen > cia->cia_max_keysize) { ++ tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; ++ return -EINVAL; ++ } else ++ return cia->cia_setkey(crypto_tfm_ctx(tfm), key, keylen, ++ &tfm->crt_flags); ++} ++ ++static int ecb_encrypt(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, unsigned int nbytes) ++{ ++ return crypt(tfm, dst, src, nbytes, ++ tfm->__crt_alg->cra_cipher.cia_encrypt, ++ ecb_process, 1, NULL); ++} ++ ++static int ecb_decrypt(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ return crypt(tfm, dst, src, nbytes, ++ tfm->__crt_alg->cra_cipher.cia_decrypt, ++ ecb_process, 1, NULL); ++} ++ ++static int cbc_encrypt(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ return crypt(tfm, dst, src, nbytes, ++ tfm->__crt_alg->cra_cipher.cia_encrypt, ++ cbc_process, 1, tfm->crt_cipher.cit_iv); ++} ++ ++static int cbc_encrypt_iv(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes, u8 *iv) ++{ ++ return crypt(tfm, dst, src, nbytes, ++ tfm->__crt_alg->cra_cipher.cia_encrypt, ++ cbc_process, 1, iv); ++} ++ ++static int cbc_decrypt(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ return crypt(tfm, dst, src, nbytes, ++ tfm->__crt_alg->cra_cipher.cia_decrypt, ++ cbc_process, 0, tfm->crt_cipher.cit_iv); ++} ++ ++static int cbc_decrypt_iv(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes, u8 *iv) ++{ ++ return crypt(tfm, dst, src, nbytes, ++ tfm->__crt_alg->cra_cipher.cia_decrypt, ++ cbc_process, 0, iv); ++} ++ ++static int nocrypt(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ return -ENOSYS; ++} ++ ++static int nocrypt_iv(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes, u8 *iv) ++{ ++ return -ENOSYS; ++} ++ ++int crypto_init_cipher_flags(struct crypto_tfm *tfm, u32 flags) ++{ ++ u32 mode = flags & CRYPTO_TFM_MODE_MASK; ++ ++ tfm->crt_cipher.cit_mode = mode ? mode : CRYPTO_TFM_MODE_ECB; ++ if (flags & CRYPTO_TFM_REQ_WEAK_KEY) ++ tfm->crt_flags = CRYPTO_TFM_REQ_WEAK_KEY; ++ ++ return 0; ++} ++ ++int crypto_init_cipher_ops(struct crypto_tfm *tfm) ++{ ++ int ret = 0; ++ struct cipher_tfm *ops = &tfm->crt_cipher; ++ ++ ops->cit_setkey = setkey; ++ ++ switch (tfm->crt_cipher.cit_mode) { ++ case CRYPTO_TFM_MODE_ECB: ++ ops->cit_encrypt = ecb_encrypt; ++ ops->cit_decrypt = ecb_decrypt; ++ break; ++ ++ case CRYPTO_TFM_MODE_CBC: ++ ops->cit_encrypt = cbc_encrypt; ++ ops->cit_decrypt = cbc_decrypt; ++ ops->cit_encrypt_iv = cbc_encrypt_iv; ++ ops->cit_decrypt_iv = cbc_decrypt_iv; ++ break; ++ ++ case CRYPTO_TFM_MODE_CFB: ++ ops->cit_encrypt = nocrypt; ++ ops->cit_decrypt = nocrypt; ++ ops->cit_encrypt_iv = nocrypt_iv; ++ ops->cit_decrypt_iv = nocrypt_iv; ++ break; ++ ++ case CRYPTO_TFM_MODE_CTR: ++ ops->cit_encrypt = nocrypt; ++ ops->cit_decrypt = nocrypt; ++ ops->cit_encrypt_iv = nocrypt_iv; ++ ops->cit_decrypt_iv = nocrypt_iv; ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ if (ops->cit_mode == CRYPTO_TFM_MODE_CBC) { ++ ++ switch (crypto_tfm_alg_blocksize(tfm)) { ++ case 8: ++ ops->cit_xor_block = xor_64; ++ break; ++ ++ case 16: ++ ops->cit_xor_block = xor_128; ++ break; ++ ++ default: ++ printk(KERN_WARNING "%s: block size %u not supported\n", ++ crypto_tfm_alg_name(tfm), ++ crypto_tfm_alg_blocksize(tfm)); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ ops->cit_ivsize = crypto_tfm_alg_blocksize(tfm); ++ ops->cit_iv = kmalloc(ops->cit_ivsize, GFP_KERNEL); ++ if (ops->cit_iv == NULL) ++ ret = -ENOMEM; ++ } ++ ++out: ++ return ret; ++} ++ ++void crypto_exit_cipher_ops(struct crypto_tfm *tfm) ++{ ++ if (tfm->crt_cipher.cit_iv) ++ kfree(tfm->crt_cipher.cit_iv); ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/compress.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/compress.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/compress.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,64 @@ ++/* ++ * Cryptographic API. ++ * ++ * Compression operations. ++ * ++ * Copyright (c) 2002 James Morris ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at your option) ++ * any later version. ++ * ++ */ ++#include ++//#include ++#include "rtl_crypto.h" ++#include ++#include ++#include ++#include "internal.h" ++ ++static int crypto_compress(struct crypto_tfm *tfm, ++ const u8 *src, unsigned int slen, ++ u8 *dst, unsigned int *dlen) ++{ ++ return tfm->__crt_alg->cra_compress.coa_compress(crypto_tfm_ctx(tfm), ++ src, slen, dst, ++ dlen); ++} ++ ++static int crypto_decompress(struct crypto_tfm *tfm, ++ const u8 *src, unsigned int slen, ++ u8 *dst, unsigned int *dlen) ++{ ++ return tfm->__crt_alg->cra_compress.coa_decompress(crypto_tfm_ctx(tfm), ++ src, slen, dst, ++ dlen); ++} ++ ++int crypto_init_compress_flags(struct crypto_tfm *tfm, u32 flags) ++{ ++ return flags ? -EINVAL : 0; ++} ++ ++int crypto_init_compress_ops(struct crypto_tfm *tfm) ++{ ++ int ret = 0; ++ struct compress_tfm *ops = &tfm->crt_compress; ++ ++ ret = tfm->__crt_alg->cra_compress.coa_init(crypto_tfm_ctx(tfm)); ++ if (ret) ++ goto out; ++ ++ ops->cot_compress = crypto_compress; ++ ops->cot_decompress = crypto_decompress; ++ ++out: ++ return ret; ++} ++ ++void crypto_exit_compress_ops(struct crypto_tfm *tfm) ++{ ++ tfm->__crt_alg->cra_compress.coa_exit(crypto_tfm_ctx(tfm)); ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/crypto_compat.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/crypto_compat.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/crypto_compat.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,90 @@ ++/* ++ * Header file to maintain compatibility among different kernel versions. ++ * ++ * Copyright (c) 2004-2006 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. See README and COPYING for ++ * more details. ++ */ ++ ++#include ++ ++static inline int crypto_cipher_encrypt(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); ++ return tfm->crt_cipher.cit_encrypt(tfm, dst, src, nbytes); ++} ++ ++ ++static inline int crypto_cipher_decrypt(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); ++ return tfm->crt_cipher.cit_decrypt(tfm, dst, src, nbytes); ++} ++ ++#if 0 ++/* ++ * crypto_free_tfm - Free crypto transform ++ * @tfm: Transform to free ++ * ++ * crypto_free_tfm() frees up the transform and any associated resources, ++ * then drops the refcount on the associated algorithm. ++ */ ++void crypto_free_tfm(struct crypto_tfm *tfm) ++{ ++ struct crypto_alg *alg; ++ int size; ++ ++ if (unlikely(!tfm)) ++ return; ++ ++ alg = tfm->__crt_alg; ++ size = sizeof(*tfm) + alg->cra_ctxsize; ++ ++ if (alg->cra_exit) ++ alg->cra_exit(tfm); ++ crypto_exit_ops(tfm); ++ crypto_mod_put(alg); ++ memset(tfm, 0, size); ++ kfree(tfm); ++} ++ ++#endif ++#if 1 ++ struct crypto_tfm *crypto_alloc_tfm(const char *name, u32 flags) ++{ ++ struct crypto_tfm *tfm = NULL; ++ int err; ++ printk("call crypto_alloc_tfm!!!\n"); ++ do { ++ struct crypto_alg *alg; ++ ++ alg = crypto_alg_mod_lookup(name, 0, CRYPTO_ALG_ASYNC); ++ err = PTR_ERR(alg); ++ if (IS_ERR(alg)) ++ continue; ++ ++ tfm = __crypto_alloc_tfm(alg, flags); ++ err = 0; ++ if (IS_ERR(tfm)) { ++ crypto_mod_put(alg); ++ err = PTR_ERR(tfm); ++ tfm = NULL; ++ } ++ } while (err == -EAGAIN && !signal_pending(current)); ++ ++ return tfm; ++} ++#endif ++//EXPORT_SYMBOL_GPL(crypto_alloc_tfm); ++//EXPORT_SYMBOL_GPL(crypto_free_tfm); ++ ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/digest.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/digest.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/digest.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,108 @@ ++/* ++ * Cryptographic API. ++ * ++ * Digest operations. ++ * ++ * Copyright (c) 2002 James Morris ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at your option) ++ * any later version. ++ * ++ */ ++//#include ++#include "rtl_crypto.h" ++#include ++#include ++#include ++#include ++#include "internal.h" ++ ++static void init(struct crypto_tfm *tfm) ++{ ++ tfm->__crt_alg->cra_digest.dia_init(crypto_tfm_ctx(tfm)); ++} ++ ++static void update(struct crypto_tfm *tfm, ++ struct scatterlist *sg, unsigned int nsg) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nsg; i++) { ++ ++ struct page *pg = sg[i].page; ++ unsigned int offset = sg[i].offset; ++ unsigned int l = sg[i].length; ++ ++ do { ++ unsigned int bytes_from_page = min(l, ((unsigned int) ++ (PAGE_SIZE)) - ++ offset); ++ char *p = crypto_kmap(pg, 0) + offset; ++ ++ tfm->__crt_alg->cra_digest.dia_update ++ (crypto_tfm_ctx(tfm), p, ++ bytes_from_page); ++ crypto_kunmap(p, 0); ++ crypto_yield(tfm); ++ offset = 0; ++ pg++; ++ l -= bytes_from_page; ++ } while (l > 0); ++ } ++} ++ ++static void final(struct crypto_tfm *tfm, u8 *out) ++{ ++ tfm->__crt_alg->cra_digest.dia_final(crypto_tfm_ctx(tfm), out); ++} ++ ++static int setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen) ++{ ++ u32 flags; ++ if (tfm->__crt_alg->cra_digest.dia_setkey == NULL) ++ return -ENOSYS; ++ return tfm->__crt_alg->cra_digest.dia_setkey(crypto_tfm_ctx(tfm), ++ key, keylen, &flags); ++} ++ ++static void digest(struct crypto_tfm *tfm, ++ struct scatterlist *sg, unsigned int nsg, u8 *out) ++{ ++ unsigned int i; ++ ++ tfm->crt_digest.dit_init(tfm); ++ ++ for (i = 0; i < nsg; i++) { ++ char *p = crypto_kmap(sg[i].page, 0) + sg[i].offset; ++ tfm->__crt_alg->cra_digest.dia_update(crypto_tfm_ctx(tfm), ++ p, sg[i].length); ++ crypto_kunmap(p, 0); ++ crypto_yield(tfm); ++ } ++ crypto_digest_final(tfm, out); ++} ++ ++int crypto_init_digest_flags(struct crypto_tfm *tfm, u32 flags) ++{ ++ return flags ? -EINVAL : 0; ++} ++ ++int crypto_init_digest_ops(struct crypto_tfm *tfm) ++{ ++ struct digest_tfm *ops = &tfm->crt_digest; ++ ++ ops->dit_init = init; ++ ops->dit_update = update; ++ ops->dit_final = final; ++ ops->dit_digest = digest; ++ ops->dit_setkey = setkey; ++ ++ return crypto_alloc_hmac_block(tfm); ++} ++ ++void crypto_exit_digest_ops(struct crypto_tfm *tfm) ++{ ++ crypto_free_hmac_block(tfm); ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/dot11d.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/dot11d.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/dot11d.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,239 @@ ++#ifdef ENABLE_DOT11D ++//----------------------------------------------------------------------------- ++// File: ++// Dot11d.c ++// ++// Description: ++// Implement 802.11d. ++// ++//----------------------------------------------------------------------------- ++ ++#include "dot11d.h" ++ ++void ++Dot11d_Init(struct ieee80211_device *ieee) ++{ ++ PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(ieee); ++ ++ pDot11dInfo->bEnabled = 0; ++ ++ pDot11dInfo->State = DOT11D_STATE_NONE; ++ pDot11dInfo->CountryIeLen = 0; ++ memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1); ++ memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1); ++ RESET_CIE_WATCHDOG(ieee); ++ ++ printk("Dot11d_Init()\n"); ++} ++ ++// ++// Description: ++// Reset to the state as we are just entering a regulatory domain. ++// ++void ++Dot11d_Reset(struct ieee80211_device *ieee) ++{ ++ u32 i; ++ PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(ieee); ++#if 0 ++ if(!pDot11dInfo->bEnabled) ++ return; ++#endif ++ // Clear old channel map ++ memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1); ++ memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1); ++ // Set new channel map ++ for (i=1; i<=11; i++) { ++ (pDot11dInfo->channel_map)[i] = 1; ++ } ++ for (i=12; i<=14; i++) { ++ (pDot11dInfo->channel_map)[i] = 2; ++ } ++ ++ pDot11dInfo->State = DOT11D_STATE_NONE; ++ pDot11dInfo->CountryIeLen = 0; ++ RESET_CIE_WATCHDOG(ieee); ++ ++ //printk("Dot11d_Reset()\n"); ++} ++ ++// ++// Description: ++// Update country IE from Beacon or Probe Resopnse ++// and configure PHY for operation in the regulatory domain. ++// ++// TODO: ++// Configure Tx power. ++// ++// Assumption: ++// 1. IS_DOT11D_ENABLE() is TRUE. ++// 2. Input IE is an valid one. ++// ++void ++Dot11d_UpdateCountryIe( ++ struct ieee80211_device *dev, ++ u8 * pTaddr, ++ u16 CoutryIeLen, ++ u8 * pCoutryIe ++ ) ++{ ++ PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev); ++ u8 i, j, NumTriples, MaxChnlNum; ++ PCHNL_TXPOWER_TRIPLE pTriple; ++ ++ memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1); ++ memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1); ++ MaxChnlNum = 0; ++ NumTriples = (CoutryIeLen - 3) / 3; // skip 3-byte country string. ++ pTriple = (PCHNL_TXPOWER_TRIPLE)(pCoutryIe + 3); ++ for(i = 0; i < NumTriples; i++) ++ { ++ if(MaxChnlNum >= pTriple->FirstChnl) ++ { // It is not in a monotonically increasing order, so stop processing. ++ printk("Dot11d_UpdateCountryIe(): Invalid country IE, skip it........1\n"); ++ return; ++ } ++ if(MAX_CHANNEL_NUMBER < (pTriple->FirstChnl + pTriple->NumChnls)) ++ { // It is not a valid set of channel id, so stop processing. ++ printk("Dot11d_UpdateCountryIe(): Invalid country IE, skip it........2\n"); ++ return; ++ } ++ ++ for(j = 0 ; j < pTriple->NumChnls; j++) ++ { ++ pDot11dInfo->channel_map[pTriple->FirstChnl + j] = 1; ++ pDot11dInfo->MaxTxPwrDbmList[pTriple->FirstChnl + j] = pTriple->MaxTxPowerInDbm; ++ MaxChnlNum = pTriple->FirstChnl + j; ++ } ++ ++ pTriple = (PCHNL_TXPOWER_TRIPLE)((u8*)pTriple + 3); ++ } ++#if 1 ++ //printk("Dot11d_UpdateCountryIe(): Channel List:\n"); ++ printk("Channel List:"); ++ for(i=1; i<= MAX_CHANNEL_NUMBER; i++) ++ if(pDot11dInfo->channel_map[i] > 0) ++ printk(" %d", i); ++ printk("\n"); ++#endif ++ ++ UPDATE_CIE_SRC(dev, pTaddr); ++ ++ pDot11dInfo->CountryIeLen = CoutryIeLen; ++ memcpy(pDot11dInfo->CountryIeBuf, pCoutryIe,CoutryIeLen); ++ pDot11dInfo->State = DOT11D_STATE_LEARNED; ++} ++ ++ ++u8 ++DOT11D_GetMaxTxPwrInDbm( ++ struct ieee80211_device *dev, ++ u8 Channel ++ ) ++{ ++ PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev); ++ u8 MaxTxPwrInDbm = 255; ++ ++ if(MAX_CHANNEL_NUMBER < Channel) ++ { ++ printk("DOT11D_GetMaxTxPwrInDbm(): Invalid Channel\n"); ++ return MaxTxPwrInDbm; ++ } ++ if(pDot11dInfo->channel_map[Channel]) ++ { ++ MaxTxPwrInDbm = pDot11dInfo->MaxTxPwrDbmList[Channel]; ++ } ++ ++ return MaxTxPwrInDbm; ++} ++ ++ ++void ++DOT11D_ScanComplete( ++ struct ieee80211_device * dev ++ ) ++{ ++ PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev); ++ ++ switch(pDot11dInfo->State) ++ { ++ case DOT11D_STATE_LEARNED: ++ pDot11dInfo->State = DOT11D_STATE_DONE; ++ break; ++ ++ case DOT11D_STATE_DONE: ++ if( GET_CIE_WATCHDOG(dev) == 0 ) ++ { // Reset country IE if previous one is gone. ++ Dot11d_Reset(dev); ++ } ++ break; ++ case DOT11D_STATE_NONE: ++ break; ++ } ++} ++ ++int IsLegalChannel( ++ struct ieee80211_device * dev, ++ u8 channel ++) ++{ ++ PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev); ++ ++ if(MAX_CHANNEL_NUMBER < channel) ++ { ++ printk("IsLegalChannel(): Invalid Channel\n"); ++ return 0; ++ } ++ if(pDot11dInfo->channel_map[channel] > 0) ++ return 1; ++ return 0; ++} ++ ++int ToLegalChannel( ++ struct ieee80211_device * dev, ++ u8 channel ++) ++{ ++ PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev); ++ u8 default_chn = 0; ++ u32 i = 0; ++ ++ for (i=1; i<= MAX_CHANNEL_NUMBER; i++) ++ { ++ if(pDot11dInfo->channel_map[i] > 0) ++ { ++ default_chn = i; ++ break; ++ } ++ } ++ ++ if(MAX_CHANNEL_NUMBER < channel) ++ { ++ printk("IsLegalChannel(): Invalid Channel\n"); ++ return default_chn; ++ } ++ ++ if(pDot11dInfo->channel_map[channel] > 0) ++ return channel; ++ ++ return default_chn; ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++//EXPORT_SYMBOL(Dot11d_Init); ++//EXPORT_SYMBOL(Dot11d_Reset); ++//EXPORT_SYMBOL(Dot11d_UpdateCountryIe); ++//EXPORT_SYMBOL(DOT11D_GetMaxTxPwrInDbm); ++//EXPORT_SYMBOL(DOT11D_ScanComplete); ++//EXPORT_SYMBOL(IsLegalChannel); ++//EXPORT_SYMBOL(ToLegalChannel); ++#else ++EXPORT_SYMBOL_NOVERS(Dot11d_Init); ++EXPORT_SYMBOL_NOVERS(Dot11d_Reset); ++EXPORT_SYMBOL_NOVERS(Dot11d_UpdateCountryIe); ++EXPORT_SYMBOL_NOVERS(DOT11D_GetMaxTxPwrInDbm); ++EXPORT_SYMBOL_NOVERS(DOT11D_ScanComplete); ++EXPORT_SYMBOL_NOVERS(IsLegalChannel); ++EXPORT_SYMBOL_NOVERS(ToLegalChannel); ++#endif ++ ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/dot11d.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/dot11d.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/dot11d.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,102 @@ ++#ifndef __INC_DOT11D_H ++#define __INC_DOT11D_H ++ ++#ifdef ENABLE_DOT11D ++#include "ieee80211.h" ++ ++//#define ENABLE_DOT11D ++ ++//#define DOT11D_MAX_CHNL_NUM 83 ++ ++typedef struct _CHNL_TXPOWER_TRIPLE { ++ u8 FirstChnl; ++ u8 NumChnls; ++ u8 MaxTxPowerInDbm; ++}CHNL_TXPOWER_TRIPLE, *PCHNL_TXPOWER_TRIPLE; ++ ++typedef enum _DOT11D_STATE { ++ DOT11D_STATE_NONE = 0, ++ DOT11D_STATE_LEARNED, ++ DOT11D_STATE_DONE, ++}DOT11D_STATE; ++ ++typedef struct _RT_DOT11D_INFO { ++ //DECLARE_RT_OBJECT(RT_DOT11D_INFO); ++ ++ bool bEnabled; // dot11MultiDomainCapabilityEnabled ++ ++ u16 CountryIeLen; // > 0 if CountryIeBuf[] contains valid country information element. ++ u8 CountryIeBuf[MAX_IE_LEN]; ++ u8 CountryIeSrcAddr[6]; // Source AP of the country IE. ++ u8 CountryIeWatchdog; ++ ++ u8 channel_map[MAX_CHANNEL_NUMBER+1]; //!!!Value 0: Invalid, 1: Valid (active scan), 2: Valid (passive scan) ++ //u8 ChnlListLen; // #Bytes valid in ChnlList[]. ++ //u8 ChnlList[DOT11D_MAX_CHNL_NUM]; ++ u8 MaxTxPwrDbmList[MAX_CHANNEL_NUMBER+1]; ++ ++ DOT11D_STATE State; ++}RT_DOT11D_INFO, *PRT_DOT11D_INFO; ++#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 ) ++#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5]) ++#define GET_DOT11D_INFO(__pIeeeDev) ((PRT_DOT11D_INFO)((__pIeeeDev)->pDot11dInfo)) ++ ++#define IS_DOT11D_ENABLE(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->bEnabled ++#define IS_COUNTRY_IE_VALID(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen > 0) ++ ++#define IS_EQUAL_CIE_SRC(__pIeeeDev, __pTa) eqMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa) ++#define UPDATE_CIE_SRC(__pIeeeDev, __pTa) cpMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa) ++ ++#define IS_COUNTRY_IE_CHANGED(__pIeeeDev, __Ie) \ ++ (((__Ie).Length == 0 || (__Ie).Length != GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen) ? \ ++ FALSE : \ ++ (!memcmp(GET_DOT11D_INFO(__pIeeeDev)->CountryIeBuf, (__Ie).Octet, (__Ie).Length))) ++ ++#define CIE_WATCHDOG_TH 1 ++#define GET_CIE_WATCHDOG(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->CountryIeWatchdog ++#define RESET_CIE_WATCHDOG(__pIeeeDev) GET_CIE_WATCHDOG(__pIeeeDev) = 0 ++#define UPDATE_CIE_WATCHDOG(__pIeeeDev) ++GET_CIE_WATCHDOG(__pIeeeDev) ++ ++#define IS_DOT11D_STATE_DONE(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->State == DOT11D_STATE_DONE) ++ ++ ++void ++Dot11d_Init( ++ struct ieee80211_device *dev ++ ); ++ ++void ++Dot11d_Reset( ++ struct ieee80211_device *dev ++ ); ++ ++void ++Dot11d_UpdateCountryIe( ++ struct ieee80211_device *dev, ++ u8 * pTaddr, ++ u16 CoutryIeLen, ++ u8 * pCoutryIe ++ ); ++ ++u8 ++DOT11D_GetMaxTxPwrInDbm( ++ struct ieee80211_device *dev, ++ u8 Channel ++ ); ++ ++void ++DOT11D_ScanComplete( ++ struct ieee80211_device * dev ++ ); ++ ++int IsLegalChannel( ++ struct ieee80211_device * dev, ++ u8 channel ++); ++ ++int ToLegalChannel( ++ struct ieee80211_device * dev, ++ u8 channel ++); ++#endif //ENABLE_DOT11D ++#endif // #ifndef __INC_DOT11D_H +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/EndianFree.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/EndianFree.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/EndianFree.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,199 @@ ++#ifndef __INC_ENDIANFREE_H ++#define __INC_ENDIANFREE_H ++ ++/* ++ * Call endian free function when ++ * 1. Read/write packet content. ++ * 2. Before write integer to IO. ++ * 3. After read integer from IO. ++ */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) ++#ifndef bool ++typedef enum{false = 0, true} bool; ++#endif ++#endif ++ ++#define __MACHINE_LITTLE_ENDIAN 1234 /* LSB first: i386, vax */ ++#define __MACHINE_BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net, ppc */ ++ ++#define BYTE_ORDER __MACHINE_LITTLE_ENDIAN ++ ++#if BYTE_ORDER == __MACHINE_LITTLE_ENDIAN ++// Convert data ++#define EF1Byte(_val) ((u8)(_val)) ++#define EF2Byte(_val) ((u16)(_val)) ++#define EF4Byte(_val) ((u32)(_val)) ++ ++#else ++// Convert data ++#define EF1Byte(_val) ((u8)(_val)) ++#define EF2Byte(_val) (((((u16)(_val))&0x00ff)<<8)|((((u16)(_val))&0xff00)>>8)) ++#define EF4Byte(_val) (((((u32)(_val))&0x000000ff)<<24)|\ ++ ((((u32)(_val))&0x0000ff00)<<8)|\ ++ ((((u32)(_val))&0x00ff0000)>>8)|\ ++ ((((u32)(_val))&0xff000000)>>24)) ++#endif ++ ++// Read data from memory ++#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr))) ++#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr))) ++#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr))) ++ ++// Write data to memory ++#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val) ++#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val) ++#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val) ++// Convert Host system specific byte ording (litten or big endia) to Network byte ording (big endian). ++// 2006.05.07, by rcnjko. ++#if BYTE_ORDER == __MACHINE_LITTLE_ENDIAN ++#define H2N1BYTE(_val) ((u8)(_val)) ++#define H2N2BYTE(_val) (((((u16)(_val))&0x00ff)<<8)|\ ++ ((((u16)(_val))&0xff00)>>8)) ++#define H2N4BYTE(_val) (((((u32)(_val))&0x000000ff)<<24)|\ ++ ((((u32)(_val))&0x0000ff00)<<8) |\ ++ ((((u32)(_val))&0x00ff0000)>>8) |\ ++ ((((u32)(_val))&0xff000000)>>24)) ++#else ++#define H2N1BYTE(_val) ((u8)(_val)) ++#define H2N2BYTE(_val) ((u16)(_val)) ++#define H2N4BYTE(_val) ((u32)(_val)) ++#endif ++ ++// Convert from Network byte ording (big endian) to Host system specific byte ording (litten or big endia). ++// 2006.05.07, by rcnjko. ++#if BYTE_ORDER == __MACHINE_LITTLE_ENDIAN ++#define N2H1BYTE(_val) ((u8)(_val)) ++#define N2H2BYTE(_val) (((((u16)(_val))&0x00ff)<<8)|\ ++ ((((u16)(_val))&0xff00)>>8)) ++#define N2H4BYTE(_val) (((((u32)(_val))&0x000000ff)<<24)|\ ++ ((((u32)(_val))&0x0000ff00)<<8) |\ ++ ((((u32)(_val))&0x00ff0000)>>8) |\ ++ ((((u32)(_val))&0xff000000)>>24)) ++#else ++#define N2H1BYTE(_val) ((u8)(_val)) ++#define N2H2BYTE(_val) ((u16)(_val)) ++#define N2H4BYTE(_val) ((u32)(_val)) ++#endif ++ ++// ++// Example: ++// BIT_LEN_MASK_32(0) => 0x00000000 ++// BIT_LEN_MASK_32(1) => 0x00000001 ++// BIT_LEN_MASK_32(2) => 0x00000003 ++// BIT_LEN_MASK_32(32) => 0xFFFFFFFF ++// ++#define BIT_LEN_MASK_32(__BitLen) (0xFFFFFFFF >> (32 - (__BitLen))) ++// ++// Example: ++// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 ++// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 ++// ++#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) (BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) ++ ++// ++// Description: ++// Return 4-byte value in host byte ordering from ++// 4-byte pointer in litten-endian system. ++// ++#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) (EF4Byte(*((u32 *)(__pStart)))) ++ ++// ++// Description: ++// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to ++// 4-byte value in host byte ordering. ++// ++#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \ ++ & \ ++ BIT_LEN_MASK_32(__BitLen) \ ++ ) ++ ++// ++// Description: ++// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering ++// and return the result in 4-byte value in host byte ordering. ++// ++#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ ++ & \ ++ ( ~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \ ++ ) ++ ++// ++// Description: ++// Set subfield of little-endian 4-byte value to specified value. ++// ++#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ ++ *((u32 *)(__pStart)) = \ ++ EF4Byte( \ ++ LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ ++ | \ ++ ( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \ ++ ); ++ ++ ++#define BIT_LEN_MASK_16(__BitLen) \ ++ (0xFFFF >> (16 - (__BitLen))) ++ ++#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \ ++ (BIT_LEN_MASK_16(__BitLen) << (__BitOffset)) ++ ++#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ ++ (EF2Byte(*((u16 *)(__pStart)))) ++ ++#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ ( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \ ++ & \ ++ BIT_LEN_MASK_16(__BitLen) \ ++ ) ++ ++#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ ++ & \ ++ ( ~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \ ++ ) ++ ++#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ ++ *((u16 *)(__pStart)) = \ ++ EF2Byte( \ ++ LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ ++ | \ ++ ( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \ ++ ); ++ ++#define BIT_LEN_MASK_8(__BitLen) \ ++ (0xFF >> (8 - (__BitLen))) ++ ++#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \ ++ (BIT_LEN_MASK_8(__BitLen) << (__BitOffset)) ++ ++#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ ++ (EF1Byte(*((u8 *)(__pStart)))) ++ ++#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \ ++ & \ ++ BIT_LEN_MASK_8(__BitLen) \ ++ ) ++ ++#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ ++ & \ ++ ( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \ ++ ) ++ ++#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ ++ *((u8 *)(__pStart)) = \ ++ EF1Byte( \ ++ LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ ++ | \ ++ ( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \ ++ ); ++ ++#endif // #ifndef __INC_ENDIANFREE_H +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,273 @@ ++/* ++ * Host AP crypto routines ++ * ++ * Copyright (c) 2002-2003, Jouni Malinen ++ * Portions Copyright (C) 2004, Intel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. See README and COPYING for ++ * more details. ++ * ++ */ ++ ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ieee80211.h" ++ ++//MODULE_AUTHOR("Jouni Malinen"); ++//MODULE_DESCRIPTION("HostAP crypto"); ++//MODULE_LICENSE("GPL"); ++ ++struct ieee80211_crypto_alg { ++ struct list_head list; ++ struct ieee80211_crypto_ops *ops; ++}; ++ ++ ++struct ieee80211_crypto { ++ struct list_head algs; ++ spinlock_t lock; ++}; ++ ++static struct ieee80211_crypto *hcrypt; ++ ++void ieee80211_crypt_deinit_entries(struct ieee80211_device *ieee, ++ int force) ++{ ++ struct list_head *ptr, *n; ++ struct ieee80211_crypt_data *entry; ++ ++ for (ptr = ieee->crypt_deinit_list.next, n = ptr->next; ++ ptr != &ieee->crypt_deinit_list; ptr = n, n = ptr->next) { ++ entry = list_entry(ptr, struct ieee80211_crypt_data, list); ++ ++ if (atomic_read(&entry->refcnt) != 0 && !force) ++ continue; ++ ++ list_del(ptr); ++ ++ if (entry->ops) { ++ entry->ops->deinit(entry->priv); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) ++ module_put(entry->ops->owner); ++#else ++ __MOD_DEC_USE_COUNT(entry->ops->owner); ++#endif ++ } ++ kfree(entry); ++ } ++} ++ ++void ieee80211_crypt_deinit_handler(unsigned long data) ++{ ++ struct ieee80211_device *ieee = (struct ieee80211_device *)data; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ieee->lock, flags); ++ ieee80211_crypt_deinit_entries(ieee, 0); ++ if (!list_empty(&ieee->crypt_deinit_list)) { ++ printk(KERN_DEBUG "%s: entries remaining in delayed crypt " ++ "deletion list\n", ieee->dev->name); ++ ieee->crypt_deinit_timer.expires = jiffies + HZ; ++ add_timer(&ieee->crypt_deinit_timer); ++ } ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ ++} ++ ++void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee, ++ struct ieee80211_crypt_data **crypt) ++{ ++ struct ieee80211_crypt_data *tmp; ++ unsigned long flags; ++ ++ if (*crypt == NULL) ++ return; ++ ++ tmp = *crypt; ++ *crypt = NULL; ++ ++ /* must not run ops->deinit() while there may be pending encrypt or ++ * decrypt operations. Use a list of delayed deinits to avoid needing ++ * locking. */ ++ ++ spin_lock_irqsave(&ieee->lock, flags); ++ list_add(&tmp->list, &ieee->crypt_deinit_list); ++ if (!timer_pending(&ieee->crypt_deinit_timer)) { ++ ieee->crypt_deinit_timer.expires = jiffies + HZ; ++ add_timer(&ieee->crypt_deinit_timer); ++ } ++ spin_unlock_irqrestore(&ieee->lock, flags); ++} ++ ++int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops) ++{ ++ unsigned long flags; ++ struct ieee80211_crypto_alg *alg; ++ ++ if (hcrypt == NULL) ++ return -1; ++ ++ alg = kmalloc(sizeof(*alg), GFP_KERNEL); ++ if (alg == NULL) ++ return -ENOMEM; ++ ++ memset(alg, 0, sizeof(*alg)); ++ alg->ops = ops; ++ ++ spin_lock_irqsave(&hcrypt->lock, flags); ++ list_add(&alg->list, &hcrypt->algs); ++ spin_unlock_irqrestore(&hcrypt->lock, flags); ++ ++ printk(KERN_DEBUG "ieee80211_crypt: registered algorithm '%s'\n", ++ ops->name); ++ ++ return 0; ++} ++ ++int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops) ++{ ++ unsigned long flags; ++ struct list_head *ptr; ++ struct ieee80211_crypto_alg *del_alg = NULL; ++ ++ if (hcrypt == NULL) ++ return -1; ++ ++ spin_lock_irqsave(&hcrypt->lock, flags); ++ for (ptr = hcrypt->algs.next; ptr != &hcrypt->algs; ptr = ptr->next) { ++ struct ieee80211_crypto_alg *alg = ++ (struct ieee80211_crypto_alg *) ptr; ++ if (alg->ops == ops) { ++ list_del(&alg->list); ++ del_alg = alg; ++ break; ++ } ++ } ++ spin_unlock_irqrestore(&hcrypt->lock, flags); ++ ++ if (del_alg) { ++ printk(KERN_DEBUG "ieee80211_crypt: unregistered algorithm " ++ "'%s'\n", ops->name); ++ kfree(del_alg); ++ } ++ ++ return del_alg ? 0 : -1; ++} ++ ++ ++struct ieee80211_crypto_ops * ieee80211_get_crypto_ops(const char *name) ++{ ++ unsigned long flags; ++ struct list_head *ptr; ++ struct ieee80211_crypto_alg *found_alg = NULL; ++ ++ if (hcrypt == NULL) ++ return NULL; ++ ++ spin_lock_irqsave(&hcrypt->lock, flags); ++ for (ptr = hcrypt->algs.next; ptr != &hcrypt->algs; ptr = ptr->next) { ++ struct ieee80211_crypto_alg *alg = ++ (struct ieee80211_crypto_alg *) ptr; ++ if (strcmp(alg->ops->name, name) == 0) { ++ found_alg = alg; ++ break; ++ } ++ } ++ spin_unlock_irqrestore(&hcrypt->lock, flags); ++ ++ if (found_alg) ++ return found_alg->ops; ++ else ++ return NULL; ++} ++ ++ ++static void * ieee80211_crypt_null_init(int keyidx) { return (void *) 1; } ++static void ieee80211_crypt_null_deinit(void *priv) {} ++ ++static struct ieee80211_crypto_ops ieee80211_crypt_null = { ++ .name = "NULL", ++ .init = ieee80211_crypt_null_init, ++ .deinit = ieee80211_crypt_null_deinit, ++ .encrypt_mpdu = NULL, ++ .decrypt_mpdu = NULL, ++ .encrypt_msdu = NULL, ++ .decrypt_msdu = NULL, ++ .set_key = NULL, ++ .get_key = NULL, ++ .extra_prefix_len = 0, ++ .extra_postfix_len = 0, ++ .owner = THIS_MODULE, ++}; ++ ++ ++int __init ieee80211_crypto_init(void) ++{ ++ int ret = -ENOMEM; ++ ++ hcrypt = kmalloc(sizeof(*hcrypt), GFP_KERNEL); ++ if (!hcrypt) ++ goto out; ++ ++ memset(hcrypt, 0, sizeof(*hcrypt)); ++ INIT_LIST_HEAD(&hcrypt->algs); ++ spin_lock_init(&hcrypt->lock); ++ ++ ret = ieee80211_register_crypto_ops(&ieee80211_crypt_null); ++ if (ret < 0) { ++ kfree(hcrypt); ++ hcrypt = NULL; ++ } ++out: ++ return ret; ++} ++ ++ ++void __exit ieee80211_crypto_deinit(void) ++{ ++ struct list_head *ptr, *n; ++ ++ if (hcrypt == NULL) ++ return; ++ ++ for (ptr = hcrypt->algs.next, n = ptr->next; ptr != &hcrypt->algs; ++ ptr = n, n = ptr->next) { ++ struct ieee80211_crypto_alg *alg = ++ (struct ieee80211_crypto_alg *) ptr; ++ list_del(ptr); ++ printk(KERN_DEBUG "ieee80211_crypt: unregistered algorithm " ++ "'%s' (deinit)\n", alg->ops->name); ++ kfree(alg); ++ } ++ ++ kfree(hcrypt); ++} ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++//EXPORT_SYMBOL(ieee80211_crypt_deinit_entries); ++//EXPORT_SYMBOL(ieee80211_crypt_deinit_handler); ++//EXPORT_SYMBOL(ieee80211_crypt_delayed_deinit); ++ ++//EXPORT_SYMBOL(ieee80211_register_crypto_ops); ++//EXPORT_SYMBOL(ieee80211_unregister_crypto_ops); ++//EXPORT_SYMBOL(ieee80211_get_crypto_ops); ++#else ++EXPORT_SYMBOL_NOVERS(ieee80211_crypt_deinit_entries); ++EXPORT_SYMBOL_NOVERS(ieee80211_crypt_deinit_handler); ++EXPORT_SYMBOL_NOVERS(ieee80211_crypt_delayed_deinit); ++ ++EXPORT_SYMBOL_NOVERS(ieee80211_register_crypto_ops); ++EXPORT_SYMBOL_NOVERS(ieee80211_unregister_crypto_ops); ++EXPORT_SYMBOL_NOVERS(ieee80211_get_crypto_ops); ++#endif ++ ++//module_init(ieee80211_crypto_init); ++//module_exit(ieee80211_crypto_deinit); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,534 @@ ++/* ++ * Host AP crypt: host-based CCMP encryption implementation for Host AP driver ++ * ++ * Copyright (c) 2003-2004, Jouni Malinen ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. See README and COPYING for ++ * more details. ++ */ ++ ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ieee80211.h" ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) ++#include "rtl_crypto.h" ++#else ++#include ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++ #include ++#else ++ #include ++#endif ++//#include ++ ++MODULE_AUTHOR("Jouni Malinen"); ++MODULE_DESCRIPTION("Host AP crypt: CCMP"); ++MODULE_LICENSE("GPL"); ++ ++#ifndef OPENSUSE_SLED ++#define OPENSUSE_SLED 0 ++#endif ++ ++#define AES_BLOCK_LEN 16 ++#define CCMP_HDR_LEN 8 ++#define CCMP_MIC_LEN 8 ++#define CCMP_TK_LEN 16 ++#define CCMP_PN_LEN 6 ++ ++struct ieee80211_ccmp_data { ++ u8 key[CCMP_TK_LEN]; ++ int key_set; ++ ++ u8 tx_pn[CCMP_PN_LEN]; ++ u8 rx_pn[CCMP_PN_LEN]; ++ ++ u32 dot11RSNAStatsCCMPFormatErrors; ++ u32 dot11RSNAStatsCCMPReplays; ++ u32 dot11RSNAStatsCCMPDecryptErrors; ++ ++ int key_idx; ++ ++ struct crypto_tfm *tfm; ++ ++ /* scratch buffers for virt_to_page() (crypto API) */ ++ u8 tx_b0[AES_BLOCK_LEN], tx_b[AES_BLOCK_LEN], ++ tx_e[AES_BLOCK_LEN], tx_s0[AES_BLOCK_LEN]; ++ u8 rx_b0[AES_BLOCK_LEN], rx_b[AES_BLOCK_LEN], rx_a[AES_BLOCK_LEN]; ++}; ++ ++void ieee80211_ccmp_aes_encrypt(struct crypto_tfm *tfm, ++ const u8 pt[16], u8 ct[16]) ++{ ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ struct scatterlist src, dst; ++ ++ src.page = virt_to_page(pt); ++ src.offset = offset_in_page(pt); ++ src.length = AES_BLOCK_LEN; ++ ++ dst.page = virt_to_page(ct); ++ dst.offset = offset_in_page(ct); ++ dst.length = AES_BLOCK_LEN; ++ ++ crypto_cipher_encrypt(tfm, &dst, &src, AES_BLOCK_LEN); ++#else ++ crypto_cipher_encrypt_one((void*)tfm, ct, pt); ++#endif ++} ++ ++static void * ieee80211_ccmp_init(int key_idx) ++{ ++ struct ieee80211_ccmp_data *priv; ++ ++ priv = kmalloc(sizeof(*priv), GFP_ATOMIC); ++ if (priv == NULL) ++ goto fail; ++ memset(priv, 0, sizeof(*priv)); ++ priv->key_idx = key_idx; ++ ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ priv->tfm = crypto_alloc_tfm("aes", 0); ++ if (priv->tfm == NULL) { ++ printk(KERN_DEBUG "ieee80211_crypt_ccmp: could not allocate " ++ "crypto API aes\n"); ++ goto fail; ++ } ++ #else ++ priv->tfm = (void*)crypto_alloc_cipher("aes", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(priv->tfm)) { ++ printk(KERN_DEBUG "ieee80211_crypt_ccmp: could not allocate " ++ "crypto API aes\n"); ++ priv->tfm = NULL; ++ goto fail; ++ } ++ #endif ++ return priv; ++ ++fail: ++ if (priv) { ++ if (priv->tfm) ++ #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) ++ crypto_free_tfm(priv->tfm); ++ #else ++ crypto_free_cipher((void*)priv->tfm); ++ #endif ++ kfree(priv); ++ } ++ ++ return NULL; ++} ++ ++ ++static void ieee80211_ccmp_deinit(void *priv) ++{ ++ struct ieee80211_ccmp_data *_priv = priv; ++ if (_priv && _priv->tfm) ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) ++ crypto_free_tfm(_priv->tfm); ++#else ++ crypto_free_cipher((void*)_priv->tfm); ++#endif ++ kfree(priv); ++} ++ ++ ++static inline void xor_block(u8 *b, u8 *a, size_t len) ++{ ++ int i; ++ for (i = 0; i < len; i++) ++ b[i] ^= a[i]; ++} ++ ++ ++ ++static void ccmp_init_blocks(struct crypto_tfm *tfm, ++ struct ieee80211_hdr_4addr *hdr, ++ u8 *pn, size_t dlen, u8 *b0, u8 *auth, ++ u8 *s0) ++{ ++ u8 *pos, qc = 0; ++ size_t aad_len; ++ u16 fc; ++ int a4_included, qc_included; ++ u8 aad[2 * AES_BLOCK_LEN]; ++ ++ fc = le16_to_cpu(hdr->frame_ctl); ++ a4_included = ((fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) == ++ (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)); ++ /* ++ qc_included = ((WLAN_FC_GET_TYPE(fc) == IEEE80211_FTYPE_DATA) && ++ (WLAN_FC_GET_STYPE(fc) & 0x08)); ++ */ ++ // fixed by David :2006.9.6 ++ qc_included = ((WLAN_FC_GET_TYPE(fc) == IEEE80211_FTYPE_DATA) && ++ (WLAN_FC_GET_STYPE(fc) & 0x80)); ++ aad_len = 22; ++ if (a4_included) ++ aad_len += 6; ++ if (qc_included) { ++ pos = (u8 *) &hdr->addr4; ++ if (a4_included) ++ pos += 6; ++ qc = *pos & 0x0f; ++ aad_len += 2; ++ } ++ /* CCM Initial Block: ++ * Flag (Include authentication header, M=3 (8-octet MIC), ++ * L=1 (2-octet Dlen)) ++ * Nonce: 0x00 | A2 | PN ++ * Dlen */ ++ b0[0] = 0x59; ++ b0[1] = qc; ++ memcpy(b0 + 2, hdr->addr2, ETH_ALEN); ++ memcpy(b0 + 8, pn, CCMP_PN_LEN); ++ b0[14] = (dlen >> 8) & 0xff; ++ b0[15] = dlen & 0xff; ++ ++ /* AAD: ++ * FC with bits 4..6 and 11..13 masked to zero; 14 is always one ++ * A1 | A2 | A3 ++ * SC with bits 4..15 (seq#) masked to zero ++ * A4 (if present) ++ * QC (if present) ++ */ ++ pos = (u8 *) hdr; ++ aad[0] = 0; /* aad_len >> 8 */ ++ aad[1] = aad_len & 0xff; ++ aad[2] = pos[0] & 0x8f; ++ aad[3] = pos[1] & 0xc7; ++ memcpy(aad + 4, hdr->addr1, 3 * ETH_ALEN); ++ pos = (u8 *) &hdr->seq_ctl; ++ aad[22] = pos[0] & 0x0f; ++ aad[23] = 0; /* all bits masked */ ++ memset(aad + 24, 0, 8); ++ if (a4_included) ++ memcpy(aad + 24, hdr->addr4, ETH_ALEN); ++ if (qc_included) { ++ aad[a4_included ? 30 : 24] = qc; ++ /* rest of QC masked */ ++ } ++ ++ /* Start with the first block and AAD */ ++ ieee80211_ccmp_aes_encrypt(tfm, b0, auth); ++ xor_block(auth, aad, AES_BLOCK_LEN); ++ ieee80211_ccmp_aes_encrypt(tfm, auth, auth); ++ xor_block(auth, &aad[AES_BLOCK_LEN], AES_BLOCK_LEN); ++ ieee80211_ccmp_aes_encrypt(tfm, auth, auth); ++ b0[0] &= 0x07; ++ b0[14] = b0[15] = 0; ++ ieee80211_ccmp_aes_encrypt(tfm, b0, s0); ++} ++ ++ ++ ++static int ieee80211_ccmp_encrypt(struct sk_buff *skb, int hdr_len, void *priv) ++{ ++ struct ieee80211_ccmp_data *key = priv; ++ int data_len, i; ++ u8 *pos; ++ struct ieee80211_hdr_4addr *hdr; ++ cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); ++ ++ if (skb_headroom(skb) < CCMP_HDR_LEN || ++ skb_tailroom(skb) < CCMP_MIC_LEN || ++ skb->len < hdr_len) ++ return -1; ++ ++ data_len = skb->len - hdr_len; ++ pos = skb_push(skb, CCMP_HDR_LEN); ++ memmove(pos, pos + CCMP_HDR_LEN, hdr_len); ++ pos += hdr_len; ++// mic = skb_put(skb, CCMP_MIC_LEN); ++ ++ i = CCMP_PN_LEN - 1; ++ while (i >= 0) { ++ key->tx_pn[i]++; ++ if (key->tx_pn[i] != 0) ++ break; ++ i--; ++ } ++ ++ *pos++ = key->tx_pn[5]; ++ *pos++ = key->tx_pn[4]; ++ *pos++ = 0; ++ *pos++ = (key->key_idx << 6) | (1 << 5) /* Ext IV included */; ++ *pos++ = key->tx_pn[3]; ++ *pos++ = key->tx_pn[2]; ++ *pos++ = key->tx_pn[1]; ++ *pos++ = key->tx_pn[0]; ++ ++ ++ hdr = (struct ieee80211_hdr_4addr *) skb->data; ++ if (!tcb_desc->bHwSec) ++ { ++ int blocks, last, len; ++ u8 *mic; ++ u8 *b0 = key->tx_b0; ++ u8 *b = key->tx_b; ++ u8 *e = key->tx_e; ++ u8 *s0 = key->tx_s0; ++ ++ //mic is moved to here by john ++ mic = skb_put(skb, CCMP_MIC_LEN); ++ ++ ccmp_init_blocks(key->tfm, hdr, key->tx_pn, data_len, b0, b, s0); ++ ++ blocks = (data_len + AES_BLOCK_LEN - 1) / AES_BLOCK_LEN; ++ last = data_len % AES_BLOCK_LEN; ++ ++ for (i = 1; i <= blocks; i++) { ++ len = (i == blocks && last) ? last : AES_BLOCK_LEN; ++ /* Authentication */ ++ xor_block(b, pos, len); ++ ieee80211_ccmp_aes_encrypt(key->tfm, b, b); ++ /* Encryption, with counter */ ++ b0[14] = (i >> 8) & 0xff; ++ b0[15] = i & 0xff; ++ ieee80211_ccmp_aes_encrypt(key->tfm, b0, e); ++ xor_block(pos, e, len); ++ pos += len; ++ } ++ ++ for (i = 0; i < CCMP_MIC_LEN; i++) ++ mic[i] = b[i] ^ s0[i]; ++ } ++ return 0; ++} ++ ++ ++static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) ++{ ++ struct ieee80211_ccmp_data *key = priv; ++ u8 keyidx, *pos; ++ struct ieee80211_hdr_4addr *hdr; ++ cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); ++ u8 pn[6]; ++ ++ if (skb->len < hdr_len + CCMP_HDR_LEN + CCMP_MIC_LEN) { ++ key->dot11RSNAStatsCCMPFormatErrors++; ++ return -1; ++ } ++ ++ hdr = (struct ieee80211_hdr_4addr *) skb->data; ++ pos = skb->data + hdr_len; ++ keyidx = pos[3]; ++ if (!(keyidx & (1 << 5))) { ++ if (net_ratelimit()) { ++ printk(KERN_DEBUG "CCMP: received packet without ExtIV" ++ " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2)); ++ } ++ key->dot11RSNAStatsCCMPFormatErrors++; ++ return -2; ++ } ++ keyidx >>= 6; ++ if (key->key_idx != keyidx) { ++ printk(KERN_DEBUG "CCMP: RX tkey->key_idx=%d frame " ++ "keyidx=%d priv=%p\n", key->key_idx, keyidx, priv); ++ return -6; ++ } ++ if (!key->key_set) { ++ if (net_ratelimit()) { ++ printk(KERN_DEBUG "CCMP: received packet from " MAC_FMT ++ " with keyid=%d that does not have a configured" ++ " key\n", MAC_ARG(hdr->addr2), keyidx); ++ } ++ return -3; ++ } ++ ++ pn[0] = pos[7]; ++ pn[1] = pos[6]; ++ pn[2] = pos[5]; ++ pn[3] = pos[4]; ++ pn[4] = pos[1]; ++ pn[5] = pos[0]; ++ pos += 8; ++ ++ if (memcmp(pn, key->rx_pn, CCMP_PN_LEN) <= 0) { ++ if (net_ratelimit()) { ++ printk(KERN_DEBUG "CCMP: replay detected: STA=" MAC_FMT ++ " previous PN %02x%02x%02x%02x%02x%02x " ++ "received PN %02x%02x%02x%02x%02x%02x\n", ++ MAC_ARG(hdr->addr2), MAC_ARG(key->rx_pn), ++ MAC_ARG(pn)); ++ } ++ key->dot11RSNAStatsCCMPReplays++; ++ return -4; ++ } ++ if (!tcb_desc->bHwSec) ++ { ++ size_t data_len = skb->len - hdr_len - CCMP_HDR_LEN - CCMP_MIC_LEN; ++ u8 *mic = skb->data + skb->len - CCMP_MIC_LEN; ++ u8 *b0 = key->rx_b0; ++ u8 *b = key->rx_b; ++ u8 *a = key->rx_a; ++ int i, blocks, last, len; ++ ++ ++ ccmp_init_blocks(key->tfm, hdr, pn, data_len, b0, a, b); ++ xor_block(mic, b, CCMP_MIC_LEN); ++ ++ blocks = (data_len + AES_BLOCK_LEN - 1) / AES_BLOCK_LEN; ++ last = data_len % AES_BLOCK_LEN; ++ ++ for (i = 1; i <= blocks; i++) { ++ len = (i == blocks && last) ? last : AES_BLOCK_LEN; ++ /* Decrypt, with counter */ ++ b0[14] = (i >> 8) & 0xff; ++ b0[15] = i & 0xff; ++ ieee80211_ccmp_aes_encrypt(key->tfm, b0, b); ++ xor_block(pos, b, len); ++ /* Authentication */ ++ xor_block(a, pos, len); ++ ieee80211_ccmp_aes_encrypt(key->tfm, a, a); ++ pos += len; ++ } ++ ++ if (memcmp(mic, a, CCMP_MIC_LEN) != 0) { ++ if (net_ratelimit()) { ++ printk(KERN_DEBUG "CCMP: decrypt failed: STA=" ++ MAC_FMT "\n", MAC_ARG(hdr->addr2)); ++ } ++ key->dot11RSNAStatsCCMPDecryptErrors++; ++ return -5; ++ } ++ ++ memcpy(key->rx_pn, pn, CCMP_PN_LEN); ++ } ++ /* Remove hdr and MIC */ ++ memmove(skb->data + CCMP_HDR_LEN, skb->data, hdr_len); ++ skb_pull(skb, CCMP_HDR_LEN); ++ skb_trim(skb, skb->len - CCMP_MIC_LEN); ++ ++ return keyidx; ++} ++ ++ ++static int ieee80211_ccmp_set_key(void *key, int len, u8 *seq, void *priv) ++{ ++ struct ieee80211_ccmp_data *data = priv; ++ int keyidx; ++ struct crypto_tfm *tfm = data->tfm; ++ ++ keyidx = data->key_idx; ++ memset(data, 0, sizeof(*data)); ++ data->key_idx = keyidx; ++ data->tfm = tfm; ++ if (len == CCMP_TK_LEN) { ++ memcpy(data->key, key, CCMP_TK_LEN); ++ data->key_set = 1; ++ if (seq) { ++ data->rx_pn[0] = seq[5]; ++ data->rx_pn[1] = seq[4]; ++ data->rx_pn[2] = seq[3]; ++ data->rx_pn[3] = seq[2]; ++ data->rx_pn[4] = seq[1]; ++ data->rx_pn[5] = seq[0]; ++ } ++ crypto_cipher_setkey((void*)data->tfm, data->key, CCMP_TK_LEN); ++ } else if (len == 0) ++ data->key_set = 0; ++ else ++ return -1; ++ ++ return 0; ++} ++ ++ ++static int ieee80211_ccmp_get_key(void *key, int len, u8 *seq, void *priv) ++{ ++ struct ieee80211_ccmp_data *data = priv; ++ ++ if (len < CCMP_TK_LEN) ++ return -1; ++ ++ if (!data->key_set) ++ return 0; ++ memcpy(key, data->key, CCMP_TK_LEN); ++ ++ if (seq) { ++ seq[0] = data->tx_pn[5]; ++ seq[1] = data->tx_pn[4]; ++ seq[2] = data->tx_pn[3]; ++ seq[3] = data->tx_pn[2]; ++ seq[4] = data->tx_pn[1]; ++ seq[5] = data->tx_pn[0]; ++ } ++ ++ return CCMP_TK_LEN; ++} ++ ++ ++static char * ieee80211_ccmp_print_stats(char *p, void *priv) ++{ ++ struct ieee80211_ccmp_data *ccmp = priv; ++ p += sprintf(p, "key[%d] alg=CCMP key_set=%d " ++ "tx_pn=%02x%02x%02x%02x%02x%02x " ++ "rx_pn=%02x%02x%02x%02x%02x%02x " ++ "format_errors=%d replays=%d decrypt_errors=%d\n", ++ ccmp->key_idx, ccmp->key_set, ++ MAC_ARG(ccmp->tx_pn), MAC_ARG(ccmp->rx_pn), ++ ccmp->dot11RSNAStatsCCMPFormatErrors, ++ ccmp->dot11RSNAStatsCCMPReplays, ++ ccmp->dot11RSNAStatsCCMPDecryptErrors); ++ ++ return p; ++} ++ ++void ieee80211_ccmp_null(void) ++{ ++// printk("============>%s()\n", __FUNCTION__); ++ return; ++} ++ ++static struct ieee80211_crypto_ops ieee80211_crypt_ccmp = { ++ .name = "CCMP", ++ .init = ieee80211_ccmp_init, ++ .deinit = ieee80211_ccmp_deinit, ++ .encrypt_mpdu = ieee80211_ccmp_encrypt, ++ .decrypt_mpdu = ieee80211_ccmp_decrypt, ++ .encrypt_msdu = NULL, ++ .decrypt_msdu = NULL, ++ .set_key = ieee80211_ccmp_set_key, ++ .get_key = ieee80211_ccmp_get_key, ++ .print_stats = ieee80211_ccmp_print_stats, ++ .extra_prefix_len = CCMP_HDR_LEN, ++ .extra_postfix_len = CCMP_MIC_LEN, ++ .owner = THIS_MODULE, ++}; ++ ++ ++int __init ieee80211_crypto_ccmp_init(void) ++{ ++ return ieee80211_register_crypto_ops(&ieee80211_crypt_ccmp); ++} ++ ++ ++void __exit ieee80211_crypto_ccmp_exit(void) ++{ ++ ieee80211_unregister_crypto_ops(&ieee80211_crypt_ccmp); ++} ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++//EXPORT_SYMBOL(ieee80211_ccmp_null); ++#else ++EXPORT_SYMBOL_NOVERS(ieee80211_ccmp_null); ++#endif ++ ++//module_init(ieee80211_crypto_ccmp_init); ++//module_exit(ieee80211_crypto_ccmp_exit); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,93 @@ ++/* ++ * Original code based on Host AP (software wireless LAN access point) driver ++ * for Intersil Prism2/2.5/3. ++ * ++ * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen ++ * ++ * Copyright (c) 2002-2003, Jouni Malinen ++ * ++ * Adaption to a generic IEEE 802.11 stack by James Ketrenos ++ * ++ * ++ * Copyright (c) 2004, Intel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. See README and COPYING for ++ * more details. ++ */ ++ ++/* ++ * This file defines the interface to the ieee80211 crypto module. ++ */ ++#ifndef IEEE80211_CRYPT_H ++#define IEEE80211_CRYPT_H ++ ++#include ++ ++struct ieee80211_crypto_ops { ++ const char *name; ++ ++ /* init new crypto context (e.g., allocate private data space, ++ * select IV, etc.); returns NULL on failure or pointer to allocated ++ * private data on success */ ++ void * (*init)(int keyidx); ++ ++ /* deinitialize crypto context and free allocated private data */ ++ void (*deinit)(void *priv); ++ ++ /* encrypt/decrypt return < 0 on error or >= 0 on success. The return ++ * value from decrypt_mpdu is passed as the keyidx value for ++ * decrypt_msdu. skb must have enough head and tail room for the ++ * encryption; if not, error will be returned; these functions are ++ * called for all MPDUs (i.e., fragments). ++ */ ++ int (*encrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv); ++ int (*decrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv); ++ ++ /* These functions are called for full MSDUs, i.e. full frames. ++ * These can be NULL if full MSDU operations are not needed. */ ++ int (*encrypt_msdu)(struct sk_buff *skb, int hdr_len, void *priv); ++ int (*decrypt_msdu)(struct sk_buff *skb, int keyidx, int hdr_len, ++ void *priv); ++ ++ int (*set_key)(void *key, int len, u8 *seq, void *priv); ++ int (*get_key)(void *key, int len, u8 *seq, void *priv); ++ ++ /* procfs handler for printing out key information and possible ++ * statistics */ ++ char * (*print_stats)(char *p, void *priv); ++ ++ /* maximum number of bytes added by encryption; encrypt buf is ++ * allocated with extra_prefix_len bytes, copy of in_buf, and ++ * extra_postfix_len; encrypt need not use all this space, but ++ * the result must start at the beginning of the buffer and correct ++ * length must be returned */ ++ int extra_prefix_len, extra_postfix_len; ++ ++ struct module *owner; ++}; ++ ++struct ieee80211_crypt_data { ++ struct list_head list; /* delayed deletion list */ ++ struct ieee80211_crypto_ops *ops; ++ void *priv; ++ atomic_t refcnt; ++}; ++ ++int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops); ++int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops); ++struct ieee80211_crypto_ops * ieee80211_get_crypto_ops(const char *name); ++void ieee80211_crypt_deinit_entries(struct ieee80211_device *, int); ++void ieee80211_crypt_deinit_handler(unsigned long); ++void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee, ++ struct ieee80211_crypt_data **crypt); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) ++#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) ++#endif ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,31)) ++#define crypto_alloc_tfm crypto_alloc_tfm_rsl ++#define crypto_free_tfm crypto_free_tfm_rsl ++#endif ++ ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_tkip.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_tkip.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_tkip.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,1034 @@ ++/* ++ * Host AP crypt: host-based TKIP encryption implementation for Host AP driver ++ * ++ * Copyright (c) 2003-2004, Jouni Malinen ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. See README and COPYING for ++ * more details. ++ */ ++ ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ieee80211.h" ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,20)) ++//#include "crypto_compat.h" ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) ++#include "rtl_crypto.h" ++#else ++#include ++#endif ++//#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++ #include ++#else ++ #include ++#endif ++ ++#include ++ ++MODULE_AUTHOR("Jouni Malinen"); ++MODULE_DESCRIPTION("Host AP crypt: TKIP"); ++MODULE_LICENSE("GPL"); ++ ++#ifndef OPENSUSE_SLED ++#define OPENSUSE_SLED 0 ++#endif ++ ++struct ieee80211_tkip_data { ++#define TKIP_KEY_LEN 32 ++ u8 key[TKIP_KEY_LEN]; ++ int key_set; ++ ++ u32 tx_iv32; ++ u16 tx_iv16; ++ u16 tx_ttak[5]; ++ int tx_phase1_done; ++ ++ u32 rx_iv32; ++ u16 rx_iv16; ++ u16 rx_ttak[5]; ++ int rx_phase1_done; ++ u32 rx_iv32_new; ++ u16 rx_iv16_new; ++ ++ u32 dot11RSNAStatsTKIPReplays; ++ u32 dot11RSNAStatsTKIPICVErrors; ++ u32 dot11RSNAStatsTKIPLocalMICFailures; ++ ++ int key_idx; ++#if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED)) ++ struct crypto_blkcipher *rx_tfm_arc4; ++ struct crypto_hash *rx_tfm_michael; ++ struct crypto_blkcipher *tx_tfm_arc4; ++ struct crypto_hash *tx_tfm_michael; ++#else ++ struct crypto_tfm *tx_tfm_arc4; ++ struct crypto_tfm *tx_tfm_michael; ++ struct crypto_tfm *rx_tfm_arc4; ++ struct crypto_tfm *rx_tfm_michael; ++#endif ++ /* scratch buffers for virt_to_page() (crypto API) */ ++ u8 rx_hdr[16], tx_hdr[16]; ++}; ++ ++static void * ieee80211_tkip_init(int key_idx) ++{ ++ struct ieee80211_tkip_data *priv; ++ ++ priv = kmalloc(sizeof(*priv), GFP_ATOMIC); ++ if (priv == NULL) ++ goto fail; ++ memset(priv, 0, sizeof(*priv)); ++ priv->key_idx = key_idx; ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ priv->tx_tfm_arc4 = crypto_alloc_tfm("arc4", 0); ++ if (priv->tx_tfm_arc4 == NULL) { ++ printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " ++ "crypto API arc4\n"); ++ goto fail; ++ } ++ ++ priv->tx_tfm_michael = crypto_alloc_tfm("michael_mic", 0); ++ if (priv->tx_tfm_michael == NULL) { ++ printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " ++ "crypto API michael_mic\n"); ++ goto fail; ++ } ++ ++ priv->rx_tfm_arc4 = crypto_alloc_tfm("arc4", 0); ++ if (priv->rx_tfm_arc4 == NULL) { ++ printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " ++ "crypto API arc4\n"); ++ goto fail; ++ } ++ ++ priv->rx_tfm_michael = crypto_alloc_tfm("michael_mic", 0); ++ if (priv->rx_tfm_michael == NULL) { ++ printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " ++ "crypto API michael_mic\n"); ++ goto fail; ++ } ++#else ++ priv->tx_tfm_arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0, ++ CRYPTO_ALG_ASYNC); ++ if (IS_ERR(priv->tx_tfm_arc4)) { ++ printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " ++ "crypto API arc4\n"); ++ priv->tx_tfm_arc4 = NULL; ++ goto fail; ++ } ++ ++ priv->tx_tfm_michael = crypto_alloc_hash("michael_mic", 0, ++ CRYPTO_ALG_ASYNC); ++ if (IS_ERR(priv->tx_tfm_michael)) { ++ printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " ++ "crypto API michael_mic\n"); ++ priv->tx_tfm_michael = NULL; ++ goto fail; ++ } ++ ++ priv->rx_tfm_arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0, ++ CRYPTO_ALG_ASYNC); ++ if (IS_ERR(priv->rx_tfm_arc4)) { ++ printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " ++ "crypto API arc4\n"); ++ priv->rx_tfm_arc4 = NULL; ++ goto fail; ++ } ++ ++ priv->rx_tfm_michael = crypto_alloc_hash("michael_mic", 0, ++ CRYPTO_ALG_ASYNC); ++ if (IS_ERR(priv->rx_tfm_michael)) { ++ printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " ++ "crypto API michael_mic\n"); ++ priv->rx_tfm_michael = NULL; ++ goto fail; ++ } ++#endif ++ return priv; ++ ++fail: ++ if (priv) { ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ if (priv->tx_tfm_michael) ++ crypto_free_tfm(priv->tx_tfm_michael); ++ if (priv->tx_tfm_arc4) ++ crypto_free_tfm(priv->tx_tfm_arc4); ++ if (priv->rx_tfm_michael) ++ crypto_free_tfm(priv->rx_tfm_michael); ++ if (priv->rx_tfm_arc4) ++ crypto_free_tfm(priv->rx_tfm_arc4); ++ ++#else ++ if (priv->tx_tfm_michael) ++ crypto_free_hash(priv->tx_tfm_michael); ++ if (priv->tx_tfm_arc4) ++ crypto_free_blkcipher(priv->tx_tfm_arc4); ++ if (priv->rx_tfm_michael) ++ crypto_free_hash(priv->rx_tfm_michael); ++ if (priv->rx_tfm_arc4) ++ crypto_free_blkcipher(priv->rx_tfm_arc4); ++#endif ++ kfree(priv); ++ } ++ ++ return NULL; ++} ++ ++ ++static void ieee80211_tkip_deinit(void *priv) ++{ ++ struct ieee80211_tkip_data *_priv = priv; ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ if (_priv->tx_tfm_michael) ++ crypto_free_tfm(_priv->tx_tfm_michael); ++ if (_priv->tx_tfm_arc4) ++ crypto_free_tfm(_priv->tx_tfm_arc4); ++ if (_priv->rx_tfm_michael) ++ crypto_free_tfm(_priv->rx_tfm_michael); ++ if (_priv->rx_tfm_arc4) ++ crypto_free_tfm(_priv->rx_tfm_arc4); ++#else ++ if (_priv) { ++ if (_priv->tx_tfm_michael) ++ crypto_free_hash(_priv->tx_tfm_michael); ++ if (_priv->tx_tfm_arc4) ++ crypto_free_blkcipher(_priv->tx_tfm_arc4); ++ if (_priv->rx_tfm_michael) ++ crypto_free_hash(_priv->rx_tfm_michael); ++ if (_priv->rx_tfm_arc4) ++ crypto_free_blkcipher(_priv->rx_tfm_arc4); ++ } ++#endif ++ kfree(priv); ++} ++ ++ ++static inline u16 RotR1(u16 val) ++{ ++ return (val >> 1) | (val << 15); ++} ++ ++ ++static inline u8 Lo8(u16 val) ++{ ++ return val & 0xff; ++} ++ ++ ++static inline u8 Hi8(u16 val) ++{ ++ return val >> 8; ++} ++ ++ ++static inline u16 Lo16(u32 val) ++{ ++ return val & 0xffff; ++} ++ ++ ++static inline u16 Hi16(u32 val) ++{ ++ return val >> 16; ++} ++ ++ ++static inline u16 Mk16(u8 hi, u8 lo) ++{ ++ return lo | (((u16) hi) << 8); ++} ++ ++ ++static inline u16 Mk16_le(u16 *v) ++{ ++ return le16_to_cpu(*v); ++} ++ ++ ++static const u16 Sbox[256] = ++{ ++ 0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154, ++ 0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A, ++ 0x8F45, 0x1F9D, 0x8940, 0xFA87, 0xEF15, 0xB2EB, 0x8EC9, 0xFB0B, ++ 0x41EC, 0xB367, 0x5FFD, 0x45EA, 0x23BF, 0x53F7, 0xE496, 0x9B5B, ++ 0x75C2, 0xE11C, 0x3DAE, 0x4C6A, 0x6C5A, 0x7E41, 0xF502, 0x834F, ++ 0x685C, 0x51F4, 0xD134, 0xF908, 0xE293, 0xAB73, 0x6253, 0x2A3F, ++ 0x080C, 0x9552, 0x4665, 0x9D5E, 0x3028, 0x37A1, 0x0A0F, 0x2FB5, ++ 0x0E09, 0x2436, 0x1B9B, 0xDF3D, 0xCD26, 0x4E69, 0x7FCD, 0xEA9F, ++ 0x121B, 0x1D9E, 0x5874, 0x342E, 0x362D, 0xDCB2, 0xB4EE, 0x5BFB, ++ 0xA4F6, 0x764D, 0xB761, 0x7DCE, 0x527B, 0xDD3E, 0x5E71, 0x1397, ++ 0xA6F5, 0xB968, 0x0000, 0xC12C, 0x4060, 0xE31F, 0x79C8, 0xB6ED, ++ 0xD4BE, 0x8D46, 0x67D9, 0x724B, 0x94DE, 0x98D4, 0xB0E8, 0x854A, ++ 0xBB6B, 0xC52A, 0x4FE5, 0xED16, 0x86C5, 0x9AD7, 0x6655, 0x1194, ++ 0x8ACF, 0xE910, 0x0406, 0xFE81, 0xA0F0, 0x7844, 0x25BA, 0x4BE3, ++ 0xA2F3, 0x5DFE, 0x80C0, 0x058A, 0x3FAD, 0x21BC, 0x7048, 0xF104, ++ 0x63DF, 0x77C1, 0xAF75, 0x4263, 0x2030, 0xE51A, 0xFD0E, 0xBF6D, ++ 0x814C, 0x1814, 0x2635, 0xC32F, 0xBEE1, 0x35A2, 0x88CC, 0x2E39, ++ 0x9357, 0x55F2, 0xFC82, 0x7A47, 0xC8AC, 0xBAE7, 0x322B, 0xE695, ++ 0xC0A0, 0x1998, 0x9ED1, 0xA37F, 0x4466, 0x547E, 0x3BAB, 0x0B83, ++ 0x8CCA, 0xC729, 0x6BD3, 0x283C, 0xA779, 0xBCE2, 0x161D, 0xAD76, ++ 0xDB3B, 0x6456, 0x744E, 0x141E, 0x92DB, 0x0C0A, 0x486C, 0xB8E4, ++ 0x9F5D, 0xBD6E, 0x43EF, 0xC4A6, 0x39A8, 0x31A4, 0xD337, 0xF28B, ++ 0xD532, 0x8B43, 0x6E59, 0xDAB7, 0x018C, 0xB164, 0x9CD2, 0x49E0, ++ 0xD8B4, 0xACFA, 0xF307, 0xCF25, 0xCAAF, 0xF48E, 0x47E9, 0x1018, ++ 0x6FD5, 0xF088, 0x4A6F, 0x5C72, 0x3824, 0x57F1, 0x73C7, 0x9751, ++ 0xCB23, 0xA17C, 0xE89C, 0x3E21, 0x96DD, 0x61DC, 0x0D86, 0x0F85, ++ 0xE090, 0x7C42, 0x71C4, 0xCCAA, 0x90D8, 0x0605, 0xF701, 0x1C12, ++ 0xC2A3, 0x6A5F, 0xAEF9, 0x69D0, 0x1791, 0x9958, 0x3A27, 0x27B9, ++ 0xD938, 0xEB13, 0x2BB3, 0x2233, 0xD2BB, 0xA970, 0x0789, 0x33A7, ++ 0x2DB6, 0x3C22, 0x1592, 0xC920, 0x8749, 0xAAFF, 0x5078, 0xA57A, ++ 0x038F, 0x59F8, 0x0980, 0x1A17, 0x65DA, 0xD731, 0x84C6, 0xD0B8, ++ 0x82C3, 0x29B0, 0x5A77, 0x1E11, 0x7BCB, 0xA8FC, 0x6DD6, 0x2C3A, ++}; ++ ++ ++static inline u16 _S_(u16 v) ++{ ++ u16 t = Sbox[Hi8(v)]; ++ return Sbox[Lo8(v)] ^ ((t << 8) | (t >> 8)); ++} ++ ++ ++#define PHASE1_LOOP_COUNT 8 ++ ++ ++static void tkip_mixing_phase1(u16 *TTAK, const u8 *TK, const u8 *TA, u32 IV32) ++{ ++ int i, j; ++ ++ /* Initialize the 80-bit TTAK from TSC (IV32) and TA[0..5] */ ++ TTAK[0] = Lo16(IV32); ++ TTAK[1] = Hi16(IV32); ++ TTAK[2] = Mk16(TA[1], TA[0]); ++ TTAK[3] = Mk16(TA[3], TA[2]); ++ TTAK[4] = Mk16(TA[5], TA[4]); ++ ++ for (i = 0; i < PHASE1_LOOP_COUNT; i++) { ++ j = 2 * (i & 1); ++ TTAK[0] += _S_(TTAK[4] ^ Mk16(TK[1 + j], TK[0 + j])); ++ TTAK[1] += _S_(TTAK[0] ^ Mk16(TK[5 + j], TK[4 + j])); ++ TTAK[2] += _S_(TTAK[1] ^ Mk16(TK[9 + j], TK[8 + j])); ++ TTAK[3] += _S_(TTAK[2] ^ Mk16(TK[13 + j], TK[12 + j])); ++ TTAK[4] += _S_(TTAK[3] ^ Mk16(TK[1 + j], TK[0 + j])) + i; ++ } ++} ++ ++ ++static void tkip_mixing_phase2(u8 *WEPSeed, const u8 *TK, const u16 *TTAK, ++ u16 IV16) ++{ ++ /* Make temporary area overlap WEP seed so that the final copy can be ++ * avoided on little endian hosts. */ ++ u16 *PPK = (u16 *) &WEPSeed[4]; ++ ++ /* Step 1 - make copy of TTAK and bring in TSC */ ++ PPK[0] = TTAK[0]; ++ PPK[1] = TTAK[1]; ++ PPK[2] = TTAK[2]; ++ PPK[3] = TTAK[3]; ++ PPK[4] = TTAK[4]; ++ PPK[5] = TTAK[4] + IV16; ++ ++ /* Step 2 - 96-bit bijective mixing using S-box */ ++ PPK[0] += _S_(PPK[5] ^ Mk16_le((u16 *) &TK[0])); ++ PPK[1] += _S_(PPK[0] ^ Mk16_le((u16 *) &TK[2])); ++ PPK[2] += _S_(PPK[1] ^ Mk16_le((u16 *) &TK[4])); ++ PPK[3] += _S_(PPK[2] ^ Mk16_le((u16 *) &TK[6])); ++ PPK[4] += _S_(PPK[3] ^ Mk16_le((u16 *) &TK[8])); ++ PPK[5] += _S_(PPK[4] ^ Mk16_le((u16 *) &TK[10])); ++ ++ PPK[0] += RotR1(PPK[5] ^ Mk16_le((u16 *) &TK[12])); ++ PPK[1] += RotR1(PPK[0] ^ Mk16_le((u16 *) &TK[14])); ++ PPK[2] += RotR1(PPK[1]); ++ PPK[3] += RotR1(PPK[2]); ++ PPK[4] += RotR1(PPK[3]); ++ PPK[5] += RotR1(PPK[4]); ++ ++ /* Step 3 - bring in last of TK bits, assign 24-bit WEP IV value ++ * WEPSeed[0..2] is transmitted as WEP IV */ ++ WEPSeed[0] = Hi8(IV16); ++ WEPSeed[1] = (Hi8(IV16) | 0x20) & 0x7F; ++ WEPSeed[2] = Lo8(IV16); ++ WEPSeed[3] = Lo8((PPK[5] ^ Mk16_le((u16 *) &TK[0])) >> 1); ++ ++#ifdef __BIG_ENDIAN ++ { ++ int i; ++ for (i = 0; i < 6; i++) ++ PPK[i] = (PPK[i] << 8) | (PPK[i] >> 8); ++ } ++#endif ++} ++ ++ ++static int ieee80211_tkip_encrypt(struct sk_buff *skb, int hdr_len, void *priv) ++{ ++ struct ieee80211_tkip_data *tkey = priv; ++ int len; ++ u8 *pos; ++ struct ieee80211_hdr_4addr *hdr; ++ cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); ++ ++ #if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED)) ++ struct blkcipher_desc desc = {.tfm = tkey->tx_tfm_arc4}; ++ int ret = 0; ++ #endif ++ u8 rc4key[16], *icv; ++ u32 crc; ++ struct scatterlist sg; ++ ++ if (skb_headroom(skb) < 8 || skb_tailroom(skb) < 4 || ++ skb->len < hdr_len) ++ return -1; ++ ++ hdr = (struct ieee80211_hdr_4addr *) skb->data; ++ ++#if 0 ++printk("@@ tkey\n"); ++printk("%x|", ((u32*)tkey->key)[0]); ++printk("%x|", ((u32*)tkey->key)[1]); ++printk("%x|", ((u32*)tkey->key)[2]); ++printk("%x|", ((u32*)tkey->key)[3]); ++printk("%x|", ((u32*)tkey->key)[4]); ++printk("%x|", ((u32*)tkey->key)[5]); ++printk("%x|", ((u32*)tkey->key)[6]); ++printk("%x\n", ((u32*)tkey->key)[7]); ++#endif ++ ++ if (!tcb_desc->bHwSec) ++ { ++ if (!tkey->tx_phase1_done) { ++ tkip_mixing_phase1(tkey->tx_ttak, tkey->key, hdr->addr2, ++ tkey->tx_iv32); ++ tkey->tx_phase1_done = 1; ++ } ++ tkip_mixing_phase2(rc4key, tkey->key, tkey->tx_ttak, tkey->tx_iv16); ++ } ++ else ++ tkey->tx_phase1_done = 1; ++ ++ ++ len = skb->len - hdr_len; ++ pos = skb_push(skb, 8); ++ memmove(pos, pos + 8, hdr_len); ++ pos += hdr_len; ++ ++ if (tcb_desc->bHwSec) ++ { ++ *pos++ = Hi8(tkey->tx_iv16); ++ *pos++ = (Hi8(tkey->tx_iv16) | 0x20) & 0x7F; ++ *pos++ = Lo8(tkey->tx_iv16); ++ } ++ else ++ { ++ *pos++ = rc4key[0]; ++ *pos++ = rc4key[1]; ++ *pos++ = rc4key[2]; ++ } ++ ++ *pos++ = (tkey->key_idx << 6) | (1 << 5) /* Ext IV included */; ++ *pos++ = tkey->tx_iv32 & 0xff; ++ *pos++ = (tkey->tx_iv32 >> 8) & 0xff; ++ *pos++ = (tkey->tx_iv32 >> 16) & 0xff; ++ *pos++ = (tkey->tx_iv32 >> 24) & 0xff; ++ ++ if (!tcb_desc->bHwSec) ++ { ++ icv = skb_put(skb, 4); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ crc = ~crc32_le(~0, pos, len); ++#else ++ crc = ~ether_crc_le(len, pos); ++#endif ++ icv[0] = crc; ++ icv[1] = crc >> 8; ++ icv[2] = crc >> 16; ++ icv[3] = crc >> 24; ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ crypto_cipher_setkey(tkey->tx_tfm_arc4, rc4key, 16); ++ sg.page = virt_to_page(pos); ++ sg.offset = offset_in_page(pos); ++ sg.length = len + 4; ++ crypto_cipher_encrypt(tkey->tx_tfm_arc4, &sg, &sg, len + 4); ++#else ++ crypto_blkcipher_setkey(tkey->tx_tfm_arc4, rc4key, 16); ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ sg.page = virt_to_page(pos); ++ sg.offset = offset_in_page(pos); ++ sg.length = len + 4; ++#else ++ sg_init_one(&sg, pos, len+4); ++#endif ++ ret= crypto_blkcipher_encrypt(&desc, &sg, &sg, len + 4); ++#endif ++ ++ } ++ ++ tkey->tx_iv16++; ++ if (tkey->tx_iv16 == 0) { ++ tkey->tx_phase1_done = 0; ++ tkey->tx_iv32++; ++ } ++ ++ if (!tcb_desc->bHwSec) ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ return 0; ++ #else ++ return ret; ++ #endif ++ else ++ return 0; ++ ++ ++} ++ ++static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) ++{ ++ struct ieee80211_tkip_data *tkey = priv; ++ u8 keyidx, *pos; ++ u32 iv32; ++ u16 iv16; ++ struct ieee80211_hdr_4addr *hdr; ++ cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); ++ #if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED)) ++ struct blkcipher_desc desc = {.tfm = tkey->rx_tfm_arc4}; ++ #endif ++ u8 rc4key[16]; ++ u8 icv[4]; ++ u32 crc; ++ struct scatterlist sg; ++ int plen; ++ if (skb->len < hdr_len + 8 + 4) ++ return -1; ++ ++ hdr = (struct ieee80211_hdr_4addr *) skb->data; ++ pos = skb->data + hdr_len; ++ keyidx = pos[3]; ++ if (!(keyidx & (1 << 5))) { ++ if (net_ratelimit()) { ++ printk(KERN_DEBUG "TKIP: received packet without ExtIV" ++ " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2)); ++ } ++ return -2; ++ } ++ keyidx >>= 6; ++ if (tkey->key_idx != keyidx) { ++ printk(KERN_DEBUG "TKIP: RX tkey->key_idx=%d frame " ++ "keyidx=%d priv=%p\n", tkey->key_idx, keyidx, priv); ++ return -6; ++ } ++ if (!tkey->key_set) { ++ if (net_ratelimit()) { ++ printk(KERN_DEBUG "TKIP: received packet from " MAC_FMT ++ " with keyid=%d that does not have a configured" ++ " key\n", MAC_ARG(hdr->addr2), keyidx); ++ } ++ return -3; ++ } ++ iv16 = (pos[0] << 8) | pos[2]; ++ iv32 = pos[4] | (pos[5] << 8) | (pos[6] << 16) | (pos[7] << 24); ++ pos += 8; ++ ++ if (!tcb_desc->bHwSec) ++ { ++ if (iv32 < tkey->rx_iv32 || ++ (iv32 == tkey->rx_iv32 && iv16 <= tkey->rx_iv16)) { ++ if (net_ratelimit()) { ++ printk(KERN_DEBUG "TKIP: replay detected: STA=" MAC_FMT ++ " previous TSC %08x%04x received TSC " ++ "%08x%04x\n", MAC_ARG(hdr->addr2), ++ tkey->rx_iv32, tkey->rx_iv16, iv32, iv16); ++ } ++ tkey->dot11RSNAStatsTKIPReplays++; ++ return -4; ++ } ++ ++ if (iv32 != tkey->rx_iv32 || !tkey->rx_phase1_done) { ++ tkip_mixing_phase1(tkey->rx_ttak, tkey->key, hdr->addr2, iv32); ++ tkey->rx_phase1_done = 1; ++ } ++ tkip_mixing_phase2(rc4key, tkey->key, tkey->rx_ttak, iv16); ++ ++ plen = skb->len - hdr_len - 12; ++ ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ crypto_cipher_setkey(tkey->rx_tfm_arc4, rc4key, 16); ++ sg.page = virt_to_page(pos); ++ sg.offset = offset_in_page(pos); ++ sg.length = plen + 4; ++ crypto_cipher_decrypt(tkey->rx_tfm_arc4, &sg, &sg, plen + 4); ++#else ++ crypto_blkcipher_setkey(tkey->rx_tfm_arc4, rc4key, 16); ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ sg.page = virt_to_page(pos); ++ sg.offset = offset_in_page(pos); ++ sg.length = plen + 4; ++#else ++ sg_init_one(&sg, pos, plen+4); ++#endif ++ if (crypto_blkcipher_decrypt(&desc, &sg, &sg, plen + 4)) { ++ if (net_ratelimit()) { ++ printk(KERN_DEBUG ": TKIP: failed to decrypt " ++ "received packet from " MAC_FMT "\n", ++ MAC_ARG(hdr->addr2)); ++ } ++ return -7; ++ } ++#endif ++ ++ #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ crc = ~crc32_le(~0, pos, plen); ++ #else ++ crc = ~ether_crc_le(plen, pos); ++ #endif ++ icv[0] = crc; ++ icv[1] = crc >> 8; ++ icv[2] = crc >> 16; ++ icv[3] = crc >> 24; ++ ++ if (memcmp(icv, pos + plen, 4) != 0) { ++ if (iv32 != tkey->rx_iv32) { ++ /* Previously cached Phase1 result was already lost, so ++ * it needs to be recalculated for the next packet. */ ++ tkey->rx_phase1_done = 0; ++ } ++ if (net_ratelimit()) { ++ printk(KERN_DEBUG "TKIP: ICV error detected: STA=" ++ MAC_FMT "\n", MAC_ARG(hdr->addr2)); ++ } ++ tkey->dot11RSNAStatsTKIPICVErrors++; ++ return -5; ++ } ++ ++ } ++ ++ /* Update real counters only after Michael MIC verification has ++ * completed */ ++ tkey->rx_iv32_new = iv32; ++ tkey->rx_iv16_new = iv16; ++ ++ /* Remove IV and ICV */ ++ memmove(skb->data + 8, skb->data, hdr_len); ++ skb_pull(skb, 8); ++ skb_trim(skb, skb->len - 4); ++ ++//john's test ++#ifdef JOHN_DUMP ++if( ((u16*)skb->data)[0] & 0x4000){ ++ printk("@@ rx decrypted skb->data"); ++ int i; ++ for(i=0;ilen;i++){ ++ if( (i%24)==0 ) printk("\n"); ++ printk("%2x ", ((u8*)skb->data)[i]); ++ } ++ printk("\n"); ++} ++#endif /*JOHN_DUMP*/ ++ return keyidx; ++} ++ ++ ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++static int michael_mic(struct crypto_tfm * tfm_michael, u8 *key, u8 *hdr, ++ u8 *data, size_t data_len, u8 *mic) ++{ ++ struct scatterlist sg[2]; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ struct hash_desc desc; ++ int ret = 0; ++#endif ++ ++ if (tfm_michael == NULL){ ++ printk(KERN_WARNING "michael_mic: tfm_michael == NULL\n"); ++ return -1; ++ } ++ sg[0].page = virt_to_page(hdr); ++ sg[0].offset = offset_in_page(hdr); ++ sg[0].length = 16; ++ ++ sg[1].page = virt_to_page(data); ++ sg[1].offset = offset_in_page(data); ++ sg[1].length = data_len; ++ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++ crypto_digest_init(tfm_michael); ++ crypto_digest_setkey(tfm_michael, key, 8); ++ crypto_digest_update(tfm_michael, sg, 2); ++ crypto_digest_final(tfm_michael, mic); ++ return 0; ++#else ++if (crypto_hash_setkey(tkey->tfm_michael, key, 8)) ++ return -1; ++ ++// return 0; ++ desc.tfm = tkey->tfm_michael; ++ desc.flags = 0; ++ ret = crypto_hash_digest(&desc, sg, data_len + 16, mic); ++ return ret; ++#endif ++} ++#else ++static int michael_mic(struct crypto_hash *tfm_michael, u8 * key, u8 * hdr, ++ u8 * data, size_t data_len, u8 * mic) ++{ ++ struct hash_desc desc; ++ struct scatterlist sg[2]; ++ ++ if (tfm_michael == NULL) { ++ printk(KERN_WARNING "michael_mic: tfm_michael == NULL\n"); ++ return -1; ++ } ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ++ sg[0].page = virt_to_page(hdr); ++ sg[0].offset = offset_in_page(hdr); ++ sg[0].length = 16; ++ ++ sg[1].page = virt_to_page(data); ++ sg[1].offset = offset_in_page(data); ++ sg[1].length = data_len; ++#else ++ sg_init_table(sg, 2); ++ sg_set_buf(&sg[0], hdr, 16); ++ sg_set_buf(&sg[1], data, data_len); ++#endif ++ ++ if (crypto_hash_setkey(tfm_michael, key, 8)) ++ return -1; ++ ++ desc.tfm = tfm_michael; ++ desc.flags = 0; ++ return crypto_hash_digest(&desc, sg, data_len + 16, mic); ++} ++#endif ++ ++ ++ ++static void michael_mic_hdr(struct sk_buff *skb, u8 *hdr) ++{ ++ struct ieee80211_hdr_4addr *hdr11; ++ ++ hdr11 = (struct ieee80211_hdr_4addr *) skb->data; ++ switch (le16_to_cpu(hdr11->frame_ctl) & ++ (IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS)) { ++ case IEEE80211_FCTL_TODS: ++ memcpy(hdr, hdr11->addr3, ETH_ALEN); /* DA */ ++ memcpy(hdr + ETH_ALEN, hdr11->addr2, ETH_ALEN); /* SA */ ++ break; ++ case IEEE80211_FCTL_FROMDS: ++ memcpy(hdr, hdr11->addr1, ETH_ALEN); /* DA */ ++ memcpy(hdr + ETH_ALEN, hdr11->addr3, ETH_ALEN); /* SA */ ++ break; ++ case IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS: ++ memcpy(hdr, hdr11->addr3, ETH_ALEN); /* DA */ ++ memcpy(hdr + ETH_ALEN, hdr11->addr4, ETH_ALEN); /* SA */ ++ break; ++ case 0: ++ memcpy(hdr, hdr11->addr1, ETH_ALEN); /* DA */ ++ memcpy(hdr + ETH_ALEN, hdr11->addr2, ETH_ALEN); /* SA */ ++ break; ++ } ++ ++ hdr[12] = 0; /* priority */ ++ ++ hdr[13] = hdr[14] = hdr[15] = 0; /* reserved */ ++} ++ ++ ++static int ieee80211_michael_mic_add(struct sk_buff *skb, int hdr_len, void *priv) ++{ ++ struct ieee80211_tkip_data *tkey = priv; ++ u8 *pos; ++ struct ieee80211_hdr_4addr *hdr; ++ ++ hdr = (struct ieee80211_hdr_4addr *) skb->data; ++ ++ if (skb_tailroom(skb) < 8 || skb->len < hdr_len) { ++ printk(KERN_DEBUG "Invalid packet for Michael MIC add " ++ "(tailroom=%d hdr_len=%d skb->len=%d)\n", ++ skb_tailroom(skb), hdr_len, skb->len); ++ return -1; ++ } ++ ++ michael_mic_hdr(skb, tkey->tx_hdr); ++ ++ // { david, 2006.9.1 ++ // fix the wpa process with wmm enabled. ++ if(IEEE80211_QOS_HAS_SEQ(le16_to_cpu(hdr->frame_ctl))) { ++ tkey->tx_hdr[12] = *(skb->data + hdr_len - 2) & 0x07; ++ } ++ // } ++ pos = skb_put(skb, 8); ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ if (michael_mic(tkey->tx_tfm_michael, &tkey->key[16], tkey->tx_hdr, ++ skb->data + hdr_len, skb->len - 8 - hdr_len, pos)) ++#else ++ if (michael_mic(tkey->tx_tfm_michael, &tkey->key[16], tkey->tx_hdr, ++ skb->data + hdr_len, skb->len - 8 - hdr_len, pos)) ++#endif ++ return -1; ++ ++ return 0; ++} ++ ++ ++#if WIRELESS_EXT >= 18 ++static void ieee80211_michael_mic_failure(struct net_device *dev, ++ struct ieee80211_hdr_4addr *hdr, ++ int keyidx) ++{ ++ union iwreq_data wrqu; ++ struct iw_michaelmicfailure ev; ++ ++ /* TODO: needed parameters: count, keyid, key type, TSC */ ++ memset(&ev, 0, sizeof(ev)); ++ ev.flags = keyidx & IW_MICFAILURE_KEY_ID; ++ if (hdr->addr1[0] & 0x01) ++ ev.flags |= IW_MICFAILURE_GROUP; ++ else ++ ev.flags |= IW_MICFAILURE_PAIRWISE; ++ ev.src_addr.sa_family = ARPHRD_ETHER; ++ memcpy(ev.src_addr.sa_data, hdr->addr2, ETH_ALEN); ++ memset(&wrqu, 0, sizeof(wrqu)); ++ wrqu.data.length = sizeof(ev); ++ wireless_send_event(dev, IWEVMICHAELMICFAILURE, &wrqu, (char *) &ev); ++} ++#elif WIRELESS_EXT >= 15 ++static void ieee80211_michael_mic_failure(struct net_device *dev, ++ struct ieee80211_hdr_4addr *hdr, ++ int keyidx) ++{ ++ union iwreq_data wrqu; ++ char buf[128]; ++ ++ /* TODO: needed parameters: count, keyid, key type, TSC */ ++ sprintf(buf, "MLME-MICHAELMICFAILURE.indication(keyid=%d %scast addr=" ++ MAC_FMT ")", keyidx, hdr->addr1[0] & 0x01 ? "broad" : "uni", ++ MAC_ARG(hdr->addr2)); ++ memset(&wrqu, 0, sizeof(wrqu)); ++ wrqu.data.length = strlen(buf); ++ wireless_send_event(dev, IWEVCUSTOM, &wrqu, buf); ++} ++#else /* WIRELESS_EXT >= 15 */ ++static inline void ieee80211_michael_mic_failure(struct net_device *dev, ++ struct ieee80211_hdr_4addr *hdr, ++ int keyidx) ++{ ++} ++#endif /* WIRELESS_EXT >= 15 */ ++ ++static int ieee80211_michael_mic_verify(struct sk_buff *skb, int keyidx, ++ int hdr_len, void *priv) ++{ ++ struct ieee80211_tkip_data *tkey = priv; ++ u8 mic[8]; ++ struct ieee80211_hdr_4addr *hdr; ++ ++ hdr = (struct ieee80211_hdr_4addr *) skb->data; ++ ++ if (!tkey->key_set) ++ return -1; ++ ++ michael_mic_hdr(skb, tkey->rx_hdr); ++ // { david, 2006.9.1 ++ // fix the wpa process with wmm enabled. ++ if(IEEE80211_QOS_HAS_SEQ(le16_to_cpu(hdr->frame_ctl))) { ++ tkey->rx_hdr[12] = *(skb->data + hdr_len - 2) & 0x07; ++ } ++ // } ++ ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ if (michael_mic(tkey->rx_tfm_michael, &tkey->key[24], tkey->rx_hdr, ++ skb->data + hdr_len, skb->len - 8 - hdr_len, mic)) ++#else ++ if (michael_mic(tkey->rx_tfm_michael, &tkey->key[24], tkey->rx_hdr, ++ skb->data + hdr_len, skb->len - 8 - hdr_len, mic)) ++#endif ++ return -1; ++ if (memcmp(mic, skb->data + skb->len - 8, 8) != 0) { ++ struct ieee80211_hdr_4addr *hdr; ++ hdr = (struct ieee80211_hdr_4addr *) skb->data; ++ printk(KERN_DEBUG "%s: Michael MIC verification failed for " ++ "MSDU from " MAC_FMT " keyidx=%d\n", ++ skb->dev ? skb->dev->name : "N/A", MAC_ARG(hdr->addr2), ++ keyidx); ++ if (skb->dev) ++ ieee80211_michael_mic_failure(skb->dev, hdr, keyidx); ++ tkey->dot11RSNAStatsTKIPLocalMICFailures++; ++ return -1; ++ } ++ ++ /* Update TSC counters for RX now that the packet verification has ++ * completed. */ ++ tkey->rx_iv32 = tkey->rx_iv32_new; ++ tkey->rx_iv16 = tkey->rx_iv16_new; ++ ++ skb_trim(skb, skb->len - 8); ++ ++ return 0; ++} ++ ++ ++static int ieee80211_tkip_set_key(void *key, int len, u8 *seq, void *priv) ++{ ++ struct ieee80211_tkip_data *tkey = priv; ++ int keyidx; ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ struct crypto_tfm *tfm = tkey->tx_tfm_michael; ++ struct crypto_tfm *tfm2 = tkey->tx_tfm_arc4; ++ struct crypto_tfm *tfm3 = tkey->rx_tfm_michael; ++ struct crypto_tfm *tfm4 = tkey->rx_tfm_arc4; ++#else ++ struct crypto_hash *tfm = tkey->tx_tfm_michael; ++ struct crypto_blkcipher *tfm2 = tkey->tx_tfm_arc4; ++ struct crypto_hash *tfm3 = tkey->rx_tfm_michael; ++ struct crypto_blkcipher *tfm4 = tkey->rx_tfm_arc4; ++#endif ++ ++ keyidx = tkey->key_idx; ++ memset(tkey, 0, sizeof(*tkey)); ++ tkey->key_idx = keyidx; ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ tkey->tx_tfm_michael = tfm; ++ tkey->tx_tfm_arc4 = tfm2; ++ tkey->rx_tfm_michael = tfm3; ++ tkey->rx_tfm_arc4 = tfm4; ++#else ++ tkey->tx_tfm_michael = tfm; ++ tkey->tx_tfm_arc4 = tfm2; ++ tkey->rx_tfm_michael = tfm3; ++ tkey->rx_tfm_arc4 = tfm4; ++#endif ++ ++ if (len == TKIP_KEY_LEN) { ++ memcpy(tkey->key, key, TKIP_KEY_LEN); ++ tkey->key_set = 1; ++ tkey->tx_iv16 = 1; /* TSC is initialized to 1 */ ++ if (seq) { ++ tkey->rx_iv32 = (seq[5] << 24) | (seq[4] << 16) | ++ (seq[3] << 8) | seq[2]; ++ tkey->rx_iv16 = (seq[1] << 8) | seq[0]; ++ } ++ } else if (len == 0) ++ tkey->key_set = 0; ++ else ++ return -1; ++ ++ return 0; ++} ++ ++ ++static int ieee80211_tkip_get_key(void *key, int len, u8 *seq, void *priv) ++{ ++ struct ieee80211_tkip_data *tkey = priv; ++ ++ if (len < TKIP_KEY_LEN) ++ return -1; ++ ++ if (!tkey->key_set) ++ return 0; ++ memcpy(key, tkey->key, TKIP_KEY_LEN); ++ ++ if (seq) { ++ /* Return the sequence number of the last transmitted frame. */ ++ u16 iv16 = tkey->tx_iv16; ++ u32 iv32 = tkey->tx_iv32; ++ if (iv16 == 0) ++ iv32--; ++ iv16--; ++ seq[0] = tkey->tx_iv16; ++ seq[1] = tkey->tx_iv16 >> 8; ++ seq[2] = tkey->tx_iv32; ++ seq[3] = tkey->tx_iv32 >> 8; ++ seq[4] = tkey->tx_iv32 >> 16; ++ seq[5] = tkey->tx_iv32 >> 24; ++ } ++ ++ return TKIP_KEY_LEN; ++} ++ ++ ++static char * ieee80211_tkip_print_stats(char *p, void *priv) ++{ ++ struct ieee80211_tkip_data *tkip = priv; ++ p += sprintf(p, "key[%d] alg=TKIP key_set=%d " ++ "tx_pn=%02x%02x%02x%02x%02x%02x " ++ "rx_pn=%02x%02x%02x%02x%02x%02x " ++ "replays=%d icv_errors=%d local_mic_failures=%d\n", ++ tkip->key_idx, tkip->key_set, ++ (tkip->tx_iv32 >> 24) & 0xff, ++ (tkip->tx_iv32 >> 16) & 0xff, ++ (tkip->tx_iv32 >> 8) & 0xff, ++ tkip->tx_iv32 & 0xff, ++ (tkip->tx_iv16 >> 8) & 0xff, ++ tkip->tx_iv16 & 0xff, ++ (tkip->rx_iv32 >> 24) & 0xff, ++ (tkip->rx_iv32 >> 16) & 0xff, ++ (tkip->rx_iv32 >> 8) & 0xff, ++ tkip->rx_iv32 & 0xff, ++ (tkip->rx_iv16 >> 8) & 0xff, ++ tkip->rx_iv16 & 0xff, ++ tkip->dot11RSNAStatsTKIPReplays, ++ tkip->dot11RSNAStatsTKIPICVErrors, ++ tkip->dot11RSNAStatsTKIPLocalMICFailures); ++ return p; ++} ++ ++ ++static struct ieee80211_crypto_ops ieee80211_crypt_tkip = { ++ .name = "TKIP", ++ .init = ieee80211_tkip_init, ++ .deinit = ieee80211_tkip_deinit, ++ .encrypt_mpdu = ieee80211_tkip_encrypt, ++ .decrypt_mpdu = ieee80211_tkip_decrypt, ++ .encrypt_msdu = ieee80211_michael_mic_add, ++ .decrypt_msdu = ieee80211_michael_mic_verify, ++ .set_key = ieee80211_tkip_set_key, ++ .get_key = ieee80211_tkip_get_key, ++ .print_stats = ieee80211_tkip_print_stats, ++ .extra_prefix_len = 4 + 4, /* IV + ExtIV */ ++ .extra_postfix_len = 8 + 4, /* MIC + ICV */ ++ .owner = THIS_MODULE, ++}; ++ ++ ++int __init ieee80211_crypto_tkip_init(void) ++{ ++ return ieee80211_register_crypto_ops(&ieee80211_crypt_tkip); ++} ++ ++ ++void __exit ieee80211_crypto_tkip_exit(void) ++{ ++ ieee80211_unregister_crypto_ops(&ieee80211_crypt_tkip); ++} ++ ++void ieee80211_tkip_null(void) ++{ ++// printk("============>%s()\n", __FUNCTION__); ++ return; ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++//EXPORT_SYMBOL(ieee80211_tkip_null); ++#else ++EXPORT_SYMBOL_NOVERS(ieee80211_tkip_null); ++#endif ++ ++//module_init(ieee80211_crypto_tkip_init); ++//module_exit(ieee80211_crypto_tkip_exit); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_wep.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_wep.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_wep.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,397 @@ ++/* ++ * Host AP crypt: host-based WEP encryption implementation for Host AP driver ++ * ++ * Copyright (c) 2002-2004, Jouni Malinen ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. See README and COPYING for ++ * more details. ++ */ ++ ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ieee80211.h" ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,20)) ++//#include "crypto_compat.h" ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) ++#include "rtl_crypto.h" ++#else ++#include ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++ #include ++#else ++ #include ++#endif ++//#include ++#include ++// ++/* ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) ++#include "rtl_crypto.h" ++#else ++#include ++#endif ++ ++#include ++#include ++*/ ++MODULE_AUTHOR("Jouni Malinen"); ++MODULE_DESCRIPTION("Host AP crypt: WEP"); ++MODULE_LICENSE("GPL"); ++#ifndef OPENSUSE_SLED ++#define OPENSUSE_SLED 0 ++#endif ++ ++struct prism2_wep_data { ++ u32 iv; ++#define WEP_KEY_LEN 13 ++ u8 key[WEP_KEY_LEN + 1]; ++ u8 key_len; ++ u8 key_idx; ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ struct crypto_tfm *tfm; ++ #else ++ struct crypto_blkcipher *tx_tfm; ++ struct crypto_blkcipher *rx_tfm; ++ #endif ++}; ++ ++ ++static void * prism2_wep_init(int keyidx) ++{ ++ struct prism2_wep_data *priv; ++ ++ priv = kmalloc(sizeof(*priv), GFP_ATOMIC); ++ if (priv == NULL) ++ goto fail; ++ memset(priv, 0, sizeof(*priv)); ++ priv->key_idx = keyidx; ++ ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ priv->tfm = crypto_alloc_tfm("arc4", 0); ++ if (priv->tfm == NULL) { ++ printk(KERN_DEBUG "ieee80211_crypt_wep: could not allocate " ++ "crypto API arc4\n"); ++ goto fail; ++ } ++ #else ++ priv->tx_tfm = crypto_alloc_blkcipher("ecb(arc4)", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(priv->tx_tfm)) { ++ printk(KERN_DEBUG "ieee80211_crypt_wep: could not allocate " ++ "crypto API arc4\n"); ++ priv->tx_tfm = NULL; ++ goto fail; ++ } ++ priv->rx_tfm = crypto_alloc_blkcipher("ecb(arc4)", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(priv->rx_tfm)) { ++ printk(KERN_DEBUG "ieee80211_crypt_wep: could not allocate " ++ "crypto API arc4\n"); ++ priv->rx_tfm = NULL; ++ goto fail; ++ } ++ #endif ++ ++ /* start WEP IV from a random value */ ++ get_random_bytes(&priv->iv, 4); ++ ++ return priv; ++ ++fail: ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ if (priv) { ++ if (priv->tfm) ++ crypto_free_tfm(priv->tfm); ++ kfree(priv); ++ } ++ #else ++ if (priv) { ++ if (priv->tx_tfm) ++ crypto_free_blkcipher(priv->tx_tfm); ++ if (priv->rx_tfm) ++ crypto_free_blkcipher(priv->rx_tfm); ++ kfree(priv); ++ } ++ #endif ++ return NULL; ++} ++ ++ ++static void prism2_wep_deinit(void *priv) ++{ ++ struct prism2_wep_data *_priv = priv; ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ if (_priv && _priv->tfm) ++ crypto_free_tfm(_priv->tfm); ++ #else ++ if (_priv) { ++ if (_priv->tx_tfm) ++ crypto_free_blkcipher(_priv->tx_tfm); ++ if (_priv->rx_tfm) ++ crypto_free_blkcipher(_priv->rx_tfm); ++ } ++ #endif ++ kfree(priv); ++} ++ ++/* Perform WEP encryption on given skb that has at least 4 bytes of headroom ++ * for IV and 4 bytes of tailroom for ICV. Both IV and ICV will be transmitted, ++ * so the payload length increases with 8 bytes. ++ * ++ * WEP frame payload: IV + TX key idx, RC4(data), ICV = RC4(CRC32(data)) ++ */ ++static int prism2_wep_encrypt(struct sk_buff *skb, int hdr_len, void *priv) ++{ ++ struct prism2_wep_data *wep = priv; ++ u32 klen, len; ++ u8 key[WEP_KEY_LEN + 3]; ++ u8 *pos; ++ cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); ++ #if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED)) ++ struct blkcipher_desc desc = {.tfm = wep->tx_tfm}; ++ #endif ++ u32 crc; ++ u8 *icv; ++ struct scatterlist sg; ++ if (skb_headroom(skb) < 4 || skb_tailroom(skb) < 4 || ++ skb->len < hdr_len) ++ return -1; ++ ++ len = skb->len - hdr_len; ++ pos = skb_push(skb, 4); ++ memmove(pos, pos + 4, hdr_len); ++ pos += hdr_len; ++ ++ klen = 3 + wep->key_len; ++ ++ wep->iv++; ++ ++ /* Fluhrer, Mantin, and Shamir have reported weaknesses in the key ++ * scheduling algorithm of RC4. At least IVs (KeyByte + 3, 0xff, N) ++ * can be used to speedup attacks, so avoid using them. */ ++ if ((wep->iv & 0xff00) == 0xff00) { ++ u8 B = (wep->iv >> 16) & 0xff; ++ if (B >= 3 && B < klen) ++ wep->iv += 0x0100; ++ } ++ ++ /* Prepend 24-bit IV to RC4 key and TX frame */ ++ *pos++ = key[0] = (wep->iv >> 16) & 0xff; ++ *pos++ = key[1] = (wep->iv >> 8) & 0xff; ++ *pos++ = key[2] = wep->iv & 0xff; ++ *pos++ = wep->key_idx << 6; ++ ++ /* Copy rest of the WEP key (the secret part) */ ++ memcpy(key + 3, wep->key, wep->key_len); ++ ++ if (!tcb_desc->bHwSec) ++ { ++ ++ /* Append little-endian CRC32 and encrypt it to produce ICV */ ++ #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ crc = ~crc32_le(~0, pos, len); ++ #else ++ crc = ~ether_crc_le(len, pos); ++ #endif ++ icv = skb_put(skb, 4); ++ icv[0] = crc; ++ icv[1] = crc >> 8; ++ icv[2] = crc >> 16; ++ icv[3] = crc >> 24; ++ ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ crypto_cipher_setkey(wep->tfm, key, klen); ++ sg.page = virt_to_page(pos); ++ sg.offset = offset_in_page(pos); ++ sg.length = len + 4; ++ crypto_cipher_encrypt(wep->tfm, &sg, &sg, len + 4); ++ return 0; ++ #else ++ crypto_blkcipher_setkey(wep->tx_tfm, key, klen); ++ #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ sg.page = virt_to_page(pos); ++ sg.offset = offset_in_page(pos); ++ sg.length = len + 4; ++ #else ++ sg_init_one(&sg, pos, len+4); ++ #endif ++ return crypto_blkcipher_encrypt(&desc, &sg, &sg, len + 4); ++ #endif ++ } ++ ++ return 0; ++} ++ ++ ++/* Perform WEP decryption on given buffer. Buffer includes whole WEP part of ++ * the frame: IV (4 bytes), encrypted payload (including SNAP header), ++ * ICV (4 bytes). len includes both IV and ICV. ++ * ++ * Returns 0 if frame was decrypted successfully and ICV was correct and -1 on ++ * failure. If frame is OK, IV and ICV will be removed. ++ */ ++static int prism2_wep_decrypt(struct sk_buff *skb, int hdr_len, void *priv) ++{ ++ struct prism2_wep_data *wep = priv; ++ u32 klen, plen; ++ u8 key[WEP_KEY_LEN + 3]; ++ u8 keyidx, *pos; ++ cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); ++ #if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED)) ++ struct blkcipher_desc desc = {.tfm = wep->rx_tfm}; ++ #endif ++ u32 crc; ++ u8 icv[4]; ++ struct scatterlist sg; ++ if (skb->len < hdr_len + 8) ++ return -1; ++ ++ pos = skb->data + hdr_len; ++ key[0] = *pos++; ++ key[1] = *pos++; ++ key[2] = *pos++; ++ keyidx = *pos++ >> 6; ++ if (keyidx != wep->key_idx) ++ return -1; ++ ++ klen = 3 + wep->key_len; ++ ++ /* Copy rest of the WEP key (the secret part) */ ++ memcpy(key + 3, wep->key, wep->key_len); ++ ++ /* Apply RC4 to data and compute CRC32 over decrypted data */ ++ plen = skb->len - hdr_len - 8; ++ ++ if (!tcb_desc->bHwSec) ++ { ++#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) ++ crypto_cipher_setkey(wep->tfm, key, klen); ++ sg.page = virt_to_page(pos); ++ sg.offset = offset_in_page(pos); ++ sg.length = plen + 4; ++ crypto_cipher_decrypt(wep->tfm, &sg, &sg, plen + 4); ++ #else ++ crypto_blkcipher_setkey(wep->rx_tfm, key, klen); ++ #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ sg.page = virt_to_page(pos); ++ sg.offset = offset_in_page(pos); ++ sg.length = plen + 4; ++ #else ++ sg_init_one(&sg, pos, plen+4); ++ #endif ++ if (crypto_blkcipher_decrypt(&desc, &sg, &sg, plen + 4)) ++ return -7; ++ #endif ++ #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ crc = ~crc32_le(~0, pos, plen); ++ #else ++ crc = ~ether_crc_le(plen, pos); ++ #endif ++ icv[0] = crc; ++ icv[1] = crc >> 8; ++ icv[2] = crc >> 16; ++ icv[3] = crc >> 24; ++ if (memcmp(icv, pos + plen, 4) != 0) { ++ /* ICV mismatch - drop frame */ ++ return -2; ++ } ++ } ++ /* Remove IV and ICV */ ++ memmove(skb->data + 4, skb->data, hdr_len); ++ skb_pull(skb, 4); ++ skb_trim(skb, skb->len - 4); ++ ++ return 0; ++} ++ ++ ++static int prism2_wep_set_key(void *key, int len, u8 *seq, void *priv) ++{ ++ struct prism2_wep_data *wep = priv; ++ ++ if (len < 0 || len > WEP_KEY_LEN) ++ return -1; ++ ++ memcpy(wep->key, key, len); ++ wep->key_len = len; ++ ++ return 0; ++} ++ ++ ++static int prism2_wep_get_key(void *key, int len, u8 *seq, void *priv) ++{ ++ struct prism2_wep_data *wep = priv; ++ ++ if (len < wep->key_len) ++ return -1; ++ ++ memcpy(key, wep->key, wep->key_len); ++ ++ return wep->key_len; ++} ++ ++ ++static char * prism2_wep_print_stats(char *p, void *priv) ++{ ++ struct prism2_wep_data *wep = priv; ++ p += sprintf(p, "key[%d] alg=WEP len=%d\n", ++ wep->key_idx, wep->key_len); ++ return p; ++} ++ ++ ++static struct ieee80211_crypto_ops ieee80211_crypt_wep = { ++ .name = "WEP", ++ .init = prism2_wep_init, ++ .deinit = prism2_wep_deinit, ++ .encrypt_mpdu = prism2_wep_encrypt, ++ .decrypt_mpdu = prism2_wep_decrypt, ++ .encrypt_msdu = NULL, ++ .decrypt_msdu = NULL, ++ .set_key = prism2_wep_set_key, ++ .get_key = prism2_wep_get_key, ++ .print_stats = prism2_wep_print_stats, ++ .extra_prefix_len = 4, /* IV */ ++ .extra_postfix_len = 4, /* ICV */ ++ .owner = THIS_MODULE, ++}; ++ ++ ++int __init ieee80211_crypto_wep_init(void) ++{ ++ return ieee80211_register_crypto_ops(&ieee80211_crypt_wep); ++} ++ ++ ++void __exit ieee80211_crypto_wep_exit(void) ++{ ++ ieee80211_unregister_crypto_ops(&ieee80211_crypt_wep); ++} ++ ++void ieee80211_wep_null(void) ++{ ++// printk("============>%s()\n", __FUNCTION__); ++ return; ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++//EXPORT_SYMBOL(ieee80211_wep_null); ++#else ++EXPORT_SYMBOL_NOVERS(ieee80211_wep_null); ++#endif ++ ++//module_init(ieee80211_crypto_wep_init); ++//module_exit(ieee80211_crypto_wep_exit); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,2802 @@ ++/* ++ * Merged with mainline ieee80211.h in Aug 2004. Original ieee802_11 ++ * remains copyright by the original authors ++ * ++ * Portions of the merged code are based on Host AP (software wireless ++ * LAN access point) driver for Intersil Prism2/2.5/3. ++ * ++ * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen ++ * ++ * Copyright (c) 2002-2003, Jouni Malinen ++ * ++ * Adaption to a generic IEEE 802.11 stack by James Ketrenos ++ * ++ * Copyright (c) 2004, Intel Corporation ++ * ++ * Modified for Realtek's wi-fi cards by Andrea Merello ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. See README and COPYING for ++ * more details. ++ */ ++#ifndef IEEE80211_H ++#define IEEE80211_H ++#include /* ETH_ALEN */ ++#include /* ARRAY_SIZE */ ++#include ++#include ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++#include ++#else ++#include ++#include ++#endif ++#include ++#include ++ ++#include ++#include ++ ++#include "rtl819x_HT.h" ++#include "rtl819x_BA.h" ++#include "rtl819x_TS.h" ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) ++#ifndef bool ++typedef enum{false = 0, true} bool; ++#endif ++#endif ++ ++#ifndef IW_MODE_MONITOR ++#define IW_MODE_MONITOR 6 ++#endif ++ ++#ifndef IWEVCUSTOM ++#define IWEVCUSTOM 0x8c02 ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) ++#ifndef __bitwise ++#define __bitwise __attribute__((bitwise)) ++#endif ++typedef __u16 __le16; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27)) ++struct iw_spy_data{ ++ /* --- Standard spy support --- */ ++ int spy_number; ++ u_char spy_address[IW_MAX_SPY][ETH_ALEN]; ++ struct iw_quality spy_stat[IW_MAX_SPY]; ++ /* --- Enhanced spy support (event) */ ++ struct iw_quality spy_thr_low; /* Low threshold */ ++ struct iw_quality spy_thr_high; /* High threshold */ ++ u_char spy_thr_under[IW_MAX_SPY]; ++}; ++#endif ++#endif ++ ++#ifndef container_of ++/** ++ * container_of - cast a member of a structure out to the containing structure ++ * ++ * @ptr: the pointer to the member. ++ * @type: the type of the container struct this is embedded in. ++ * @member: the name of the member within the struct. ++ * ++ */ ++#define container_of(ptr, type, member) ({ \ ++ const typeof( ((type *)0)->member ) *__mptr = (ptr); \ ++ (type *)( (char *)__mptr - offsetof(type,member) );}) ++#endif ++ ++#define KEY_TYPE_NA 0x0 ++#define KEY_TYPE_WEP40 0x1 ++#define KEY_TYPE_TKIP 0x2 ++#define KEY_TYPE_CCMP 0x4 ++#define KEY_TYPE_WEP104 0x5 ++ ++/* added for rtl819x tx procedure */ ++#define MAX_QUEUE_SIZE 0x10 ++ ++// ++// 8190 queue mapping ++// ++#define BK_QUEUE 0 ++#define BE_QUEUE 1 ++#define VI_QUEUE 2 ++#define VO_QUEUE 3 ++#define HCCA_QUEUE 4 ++#define TXCMD_QUEUE 5 ++#define MGNT_QUEUE 6 ++#define HIGH_QUEUE 7 ++#define BEACON_QUEUE 8 ++ ++#define LOW_QUEUE BE_QUEUE ++#define NORMAL_QUEUE MGNT_QUEUE ++ ++//added by amy for ps ++#define SWRF_TIMEOUT 50 ++ ++//added by amy for LEAP related ++#define IE_CISCO_FLAG_POSITION 0x08 // Flag byte: byte 8, numbered from 0. ++#define SUPPORT_CKIP_MIC 0x08 // bit3 ++#define SUPPORT_CKIP_PK 0x10 // bit4 ++/* defined for skb cb field */ ++/* At most 28 byte */ ++typedef struct cb_desc { ++ /* Tx Desc Related flags (8-9) */ ++ u8 bLastIniPkt:1; ++ u8 bCmdOrInit:1; ++ u8 bFirstSeg:1; ++ u8 bLastSeg:1; ++ u8 bEncrypt:1; ++ u8 bTxDisableRateFallBack:1; ++ u8 bTxUseDriverAssingedRate:1; ++ u8 bHwSec:1; //indicate whether use Hw security. WB ++ ++ u8 reserved1; ++ ++ /* Tx Firmware Relaged flags (10-11)*/ ++ u8 bCTSEnable:1; ++ u8 bRTSEnable:1; ++ u8 bUseShortGI:1; ++ u8 bUseShortPreamble:1; ++ u8 bTxEnableFwCalcDur:1; ++ u8 bAMPDUEnable:1; ++ u8 bRTSSTBC:1; ++ u8 RTSSC:1; ++ ++ u8 bRTSBW:1; ++ u8 bPacketBW:1; ++ u8 bRTSUseShortPreamble:1; ++ u8 bRTSUseShortGI:1; ++ u8 bMulticast:1; ++ u8 bBroadcast:1; ++ //u8 reserved2:2; ++ u8 drv_agg_enable:1; ++ u8 reserved2:1; ++ ++ /* Tx Desc related element(12-19) */ ++ u8 rata_index; ++ u8 queue_index; ++ //u8 reserved3; ++ //u8 reserved4; ++ u16 txbuf_size; ++ //u8 reserved5; ++ u8 RATRIndex; ++ u8 reserved6; ++ u8 reserved7; ++ u8 reserved8; ++ ++ /* Tx firmware related element(20-27) */ ++ u8 data_rate; ++ u8 rts_rate; ++ u8 ampdu_factor; ++ u8 ampdu_density; ++ //u8 reserved9; ++ //u8 reserved10; ++ //u8 reserved11; ++ u8 DrvAggrNum; ++ u16 pkt_size; ++ u8 reserved12; ++}cb_desc, *pcb_desc; ++ ++/*--------------------------Define -------------------------------------------*/ ++#define MGN_1M 0x02 ++#define MGN_2M 0x04 ++#define MGN_5_5M 0x0b ++#define MGN_11M 0x16 ++ ++#define MGN_6M 0x0c ++#define MGN_9M 0x12 ++#define MGN_12M 0x18 ++#define MGN_18M 0x24 ++#define MGN_24M 0x30 ++#define MGN_36M 0x48 ++#define MGN_48M 0x60 ++#define MGN_54M 0x6c ++ ++#define MGN_MCS0 0x80 ++#define MGN_MCS1 0x81 ++#define MGN_MCS2 0x82 ++#define MGN_MCS3 0x83 ++#define MGN_MCS4 0x84 ++#define MGN_MCS5 0x85 ++#define MGN_MCS6 0x86 ++#define MGN_MCS7 0x87 ++#define MGN_MCS8 0x88 ++#define MGN_MCS9 0x89 ++#define MGN_MCS10 0x8a ++#define MGN_MCS11 0x8b ++#define MGN_MCS12 0x8c ++#define MGN_MCS13 0x8d ++#define MGN_MCS14 0x8e ++#define MGN_MCS15 0x8f ++ ++//---------------------------------------------------------------------------- ++// 802.11 Management frame Reason Code field ++//---------------------------------------------------------------------------- ++enum _ReasonCode{ ++ unspec_reason = 0x1, ++ auth_not_valid = 0x2, ++ deauth_lv_ss = 0x3, ++ inactivity = 0x4, ++ ap_overload = 0x5, ++ class2_err = 0x6, ++ class3_err = 0x7, ++ disas_lv_ss = 0x8, ++ asoc_not_auth = 0x9, ++ ++ //----MIC_CHECK ++ mic_failure = 0xe, ++ //----END MIC_CHECK ++ ++ // Reason code defined in 802.11i D10.0 p.28. ++ invalid_IE = 0x0d, ++ four_way_tmout = 0x0f, ++ two_way_tmout = 0x10, ++ IE_dismatch = 0x11, ++ invalid_Gcipher = 0x12, ++ invalid_Pcipher = 0x13, ++ invalid_AKMP = 0x14, ++ unsup_RSNIEver = 0x15, ++ invalid_RSNIE = 0x16, ++ auth_802_1x_fail= 0x17, ++ ciper_reject = 0x18, ++ ++ // Reason code defined in 7.3.1.7, 802.1e D13.0, p.42. Added by Annie, 2005-11-15. ++ QoS_unspec = 0x20, // 32 ++ QAP_bandwidth = 0x21, // 33 ++ poor_condition = 0x22, // 34 ++ no_facility = 0x23, // 35 ++ // Where is 36??? ++ req_declined = 0x25, // 37 ++ invalid_param = 0x26, // 38 ++ req_not_honored= 0x27, // 39 ++ TS_not_created = 0x2F, // 47 ++ DL_not_allowed = 0x30, // 48 ++ dest_not_exist = 0x31, // 49 ++ dest_not_QSTA = 0x32, // 50 ++}; ++ ++ ++ ++#define aSifsTime (((priv->ieee80211->current_network.mode == IEEE_A)||(priv->ieee80211->current_network.mode == IEEE_N_24G)||(priv->ieee80211->current_network.mode == IEEE_N_5G))? 16 : 10) ++ ++#define MGMT_QUEUE_NUM 5 ++ ++#define IEEE_CMD_SET_WPA_PARAM 1 ++#define IEEE_CMD_SET_WPA_IE 2 ++#define IEEE_CMD_SET_ENCRYPTION 3 ++#define IEEE_CMD_MLME 4 ++ ++#define IEEE_PARAM_WPA_ENABLED 1 ++#define IEEE_PARAM_TKIP_COUNTERMEASURES 2 ++#define IEEE_PARAM_DROP_UNENCRYPTED 3 ++#define IEEE_PARAM_PRIVACY_INVOKED 4 ++#define IEEE_PARAM_AUTH_ALGS 5 ++#define IEEE_PARAM_IEEE_802_1X 6 ++//It should consistent with the driver_XXX.c ++// David, 2006.9.26 ++#define IEEE_PARAM_WPAX_SELECT 7 ++//Added for notify the encryption type selection ++// David, 2006.9.26 ++#define IEEE_PROTO_WPA 1 ++#define IEEE_PROTO_RSN 2 ++//Added for notify the encryption type selection ++// David, 2006.9.26 ++#define IEEE_WPAX_USEGROUP 0 ++#define IEEE_WPAX_WEP40 1 ++#define IEEE_WPAX_TKIP 2 ++#define IEEE_WPAX_WRAP 3 ++#define IEEE_WPAX_CCMP 4 ++#define IEEE_WPAX_WEP104 5 ++ ++#define IEEE_KEY_MGMT_IEEE8021X 1 ++#define IEEE_KEY_MGMT_PSK 2 ++ ++#define IEEE_MLME_STA_DEAUTH 1 ++#define IEEE_MLME_STA_DISASSOC 2 ++ ++ ++#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2 ++#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3 ++#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4 ++#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5 ++#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6 ++#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7 ++ ++ ++#define IEEE_CRYPT_ALG_NAME_LEN 16 ++ ++#define MAX_IE_LEN 0xff ++ ++// added for kernel conflict ++#define ieee80211_crypt_deinit_entries ieee80211_crypt_deinit_entries_rsl ++#define ieee80211_crypt_deinit_handler ieee80211_crypt_deinit_handler_rsl ++#define ieee80211_crypt_delayed_deinit ieee80211_crypt_delayed_deinit_rsl ++#define ieee80211_register_crypto_ops ieee80211_register_crypto_ops_rsl ++#define ieee80211_unregister_crypto_ops ieee80211_unregister_crypto_ops_rsl ++#define ieee80211_get_crypto_ops ieee80211_get_crypto_ops_rsl ++ ++#define ieee80211_ccmp_null ieee80211_ccmp_null_rsl ++ ++#define ieee80211_tkip_null ieee80211_tkip_null_rsl ++ ++#define ieee80211_wep_null ieee80211_wep_null_rsl ++ ++#define free_ieee80211 free_ieee80211_rsl ++#define alloc_ieee80211 alloc_ieee80211_rsl ++ ++#define ieee80211_rx ieee80211_rx_rsl ++#define ieee80211_rx_mgt ieee80211_rx_mgt_rsl ++ ++#define ieee80211_get_beacon ieee80211_get_beacon_rsl ++#define ieee80211_wake_queue ieee80211_wake_queue_rsl ++#define ieee80211_stop_queue ieee80211_stop_queue_rsl ++#define ieee80211_reset_queue ieee80211_reset_queue_rsl ++#define ieee80211_softmac_stop_protocol ieee80211_softmac_stop_protocol_rsl ++#define ieee80211_softmac_start_protocol ieee80211_softmac_start_protocol_rsl ++#define ieee80211_is_shortslot ieee80211_is_shortslot_rsl ++#define ieee80211_is_54g ieee80211_is_54g_rsl ++#define ieee80211_wpa_supplicant_ioctl ieee80211_wpa_supplicant_ioctl_rsl ++#define ieee80211_ps_tx_ack ieee80211_ps_tx_ack_rsl ++#define ieee80211_softmac_xmit ieee80211_softmac_xmit_rsl ++#define ieee80211_stop_send_beacons ieee80211_stop_send_beacons_rsl ++#define notify_wx_assoc_event notify_wx_assoc_event_rsl ++#define SendDisassociation SendDisassociation_rsl ++#define ieee80211_disassociate ieee80211_disassociate_rsl ++#define ieee80211_start_send_beacons ieee80211_start_send_beacons_rsl ++#define ieee80211_stop_scan ieee80211_stop_scan_rsl ++#define ieee80211_send_probe_requests ieee80211_send_probe_requests_rsl ++#define ieee80211_softmac_scan_syncro ieee80211_softmac_scan_syncro_rsl ++#define ieee80211_start_scan_syncro ieee80211_start_scan_syncro_rsl ++ ++#define ieee80211_wx_get_essid ieee80211_wx_get_essid_rsl ++#define ieee80211_wx_set_essid ieee80211_wx_set_essid_rsl ++#define ieee80211_wx_set_rate ieee80211_wx_set_rate_rsl ++#define ieee80211_wx_get_rate ieee80211_wx_get_rate_rsl ++#define ieee80211_wx_set_wap ieee80211_wx_set_wap_rsl ++#define ieee80211_wx_get_wap ieee80211_wx_get_wap_rsl ++#define ieee80211_wx_set_mode ieee80211_wx_set_mode_rsl ++#define ieee80211_wx_get_mode ieee80211_wx_get_mode_rsl ++#define ieee80211_wx_set_scan ieee80211_wx_set_scan_rsl ++#define ieee80211_wx_get_freq ieee80211_wx_get_freq_rsl ++#define ieee80211_wx_set_freq ieee80211_wx_set_freq_rsl ++#define ieee80211_wx_set_rawtx ieee80211_wx_set_rawtx_rsl ++#define ieee80211_wx_get_name ieee80211_wx_get_name_rsl ++#define ieee80211_wx_set_power ieee80211_wx_set_power_rsl ++#define ieee80211_wx_get_power ieee80211_wx_get_power_rsl ++#define ieee80211_wlan_frequencies ieee80211_wlan_frequencies_rsl ++#define ieee80211_wx_set_rts ieee80211_wx_set_rts_rsl ++#define ieee80211_wx_get_rts ieee80211_wx_get_rts_rsl ++ ++#define ieee80211_txb_free ieee80211_txb_free_rsl ++ ++#define ieee80211_wx_set_gen_ie ieee80211_wx_set_gen_ie_rsl ++#define ieee80211_wx_get_scan ieee80211_wx_get_scan_rsl ++#define ieee80211_wx_set_encode ieee80211_wx_set_encode_rsl ++#define ieee80211_wx_get_encode ieee80211_wx_get_encode_rsl ++#if WIRELESS_EXT >= 18 ++#define ieee80211_wx_set_mlme ieee80211_wx_set_mlme_rsl ++#define ieee80211_wx_set_auth ieee80211_wx_set_auth_rsl ++#define ieee80211_wx_set_encode_ext ieee80211_wx_set_encode_ext_rsl ++#define ieee80211_wx_get_encode_ext ieee80211_wx_get_encode_ext_rsl ++#endif ++ ++ ++typedef struct ieee_param { ++ u32 cmd; ++ u8 sta_addr[ETH_ALEN]; ++ union { ++ struct { ++ u8 name; ++ u32 value; ++ } wpa_param; ++ struct { ++ u32 len; ++ u8 reserved[32]; ++ u8 data[0]; ++ } wpa_ie; ++ struct{ ++ int command; ++ int reason_code; ++ } mlme; ++ struct { ++ u8 alg[IEEE_CRYPT_ALG_NAME_LEN]; ++ u8 set_tx; ++ u32 err; ++ u8 idx; ++ u8 seq[8]; /* sequence counter (set: RX, get: TX) */ ++ u16 key_len; ++ u8 key[0]; ++ } crypt; ++ } u; ++}ieee_param; ++ ++ ++#if WIRELESS_EXT < 17 ++#define IW_QUAL_QUAL_INVALID 0x10 ++#define IW_QUAL_LEVEL_INVALID 0x20 ++#define IW_QUAL_NOISE_INVALID 0x40 ++#define IW_QUAL_QUAL_UPDATED 0x1 ++#define IW_QUAL_LEVEL_UPDATED 0x2 ++#define IW_QUAL_NOISE_UPDATED 0x4 ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) ++static inline void tq_init(struct tq_struct * task, void(*func)(void *), void *data) ++{ ++ task->routine = func; ++ task->data = data; ++ //task->next = NULL; ++ INIT_LIST_HEAD(&task->list); ++ task->sync = 0; ++} ++#endif ++ ++// linux under 2.6.9 release may not support it, so modify it for common use ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)) ++//#define MSECS(t) (1000 * ((t) / HZ) + 1000 * ((t) % HZ) / HZ) ++#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000) ++static inline unsigned long msleep_interruptible_rsl(unsigned int msecs) ++{ ++ unsigned long timeout = MSECS(msecs) + 1; ++ ++ while (timeout) { ++ set_current_state(TASK_INTERRUPTIBLE); ++ timeout = schedule_timeout(timeout); ++ } ++ return timeout; ++} ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,31)) ++static inline void msleep(unsigned int msecs) ++{ ++ unsigned long timeout = MSECS(msecs) + 1; ++ ++ while (timeout) { ++ set_current_state(TASK_UNINTERRUPTIBLE); ++ timeout = schedule_timeout(timeout); ++ } ++} ++#endif ++#else ++#define MSECS(t) msecs_to_jiffies(t) ++#define msleep_interruptible_rsl msleep_interruptible ++#endif ++ ++#define IEEE80211_DATA_LEN 2304 ++/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section ++ 6.2.1.1.2. ++ ++ The figure in section 7.1.2 suggests a body size of up to 2312 ++ bytes is allowed, which is a bit confusing, I suspect this ++ represents the 2304 bytes of real data, plus a possible 8 bytes of ++ WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */ ++#define IEEE80211_1ADDR_LEN 10 ++#define IEEE80211_2ADDR_LEN 16 ++#define IEEE80211_3ADDR_LEN 24 ++#define IEEE80211_4ADDR_LEN 30 ++#define IEEE80211_FCS_LEN 4 ++#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) ++#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) ++#define IEEE80211_MGMT_HDR_LEN 24 ++#define IEEE80211_DATA_HDR3_LEN 24 ++#define IEEE80211_DATA_HDR4_LEN 30 ++ ++#define MIN_FRAG_THRESHOLD 256U ++#define MAX_FRAG_THRESHOLD 2346U ++ ++ ++/* Frame control field constants */ ++#define IEEE80211_FCTL_VERS 0x0003 ++#define IEEE80211_FCTL_FTYPE 0x000c ++#define IEEE80211_FCTL_STYPE 0x00f0 ++#define IEEE80211_FCTL_FRAMETYPE 0x00fc ++#define IEEE80211_FCTL_TODS 0x0100 ++#define IEEE80211_FCTL_FROMDS 0x0200 ++#define IEEE80211_FCTL_DSTODS 0x0300 //added by david ++#define IEEE80211_FCTL_MOREFRAGS 0x0400 ++#define IEEE80211_FCTL_RETRY 0x0800 ++#define IEEE80211_FCTL_PM 0x1000 ++#define IEEE80211_FCTL_MOREDATA 0x2000 ++#define IEEE80211_FCTL_WEP 0x4000 ++#define IEEE80211_FCTL_ORDER 0x8000 ++ ++#define IEEE80211_FTYPE_MGMT 0x0000 ++#define IEEE80211_FTYPE_CTL 0x0004 ++#define IEEE80211_FTYPE_DATA 0x0008 ++ ++/* management */ ++#define IEEE80211_STYPE_ASSOC_REQ 0x0000 ++#define IEEE80211_STYPE_ASSOC_RESP 0x0010 ++#define IEEE80211_STYPE_REASSOC_REQ 0x0020 ++#define IEEE80211_STYPE_REASSOC_RESP 0x0030 ++#define IEEE80211_STYPE_PROBE_REQ 0x0040 ++#define IEEE80211_STYPE_PROBE_RESP 0x0050 ++#define IEEE80211_STYPE_BEACON 0x0080 ++#define IEEE80211_STYPE_ATIM 0x0090 ++#define IEEE80211_STYPE_DISASSOC 0x00A0 ++#define IEEE80211_STYPE_AUTH 0x00B0 ++#define IEEE80211_STYPE_DEAUTH 0x00C0 ++#define IEEE80211_STYPE_MANAGE_ACT 0x00D0 ++ ++/* control */ ++#define IEEE80211_STYPE_PSPOLL 0x00A0 ++#define IEEE80211_STYPE_RTS 0x00B0 ++#define IEEE80211_STYPE_CTS 0x00C0 ++#define IEEE80211_STYPE_ACK 0x00D0 ++#define IEEE80211_STYPE_CFEND 0x00E0 ++#define IEEE80211_STYPE_CFENDACK 0x00F0 ++#define IEEE80211_STYPE_BLOCKACK 0x0094 ++ ++/* data */ ++#define IEEE80211_STYPE_DATA 0x0000 ++#define IEEE80211_STYPE_DATA_CFACK 0x0010 ++#define IEEE80211_STYPE_DATA_CFPOLL 0x0020 ++#define IEEE80211_STYPE_DATA_CFACKPOLL 0x0030 ++#define IEEE80211_STYPE_NULLFUNC 0x0040 ++#define IEEE80211_STYPE_CFACK 0x0050 ++#define IEEE80211_STYPE_CFPOLL 0x0060 ++#define IEEE80211_STYPE_CFACKPOLL 0x0070 ++#define IEEE80211_STYPE_QOS_DATA 0x0080 //added for WMM 2006/8/2 ++#define IEEE80211_STYPE_QOS_NULL 0x00C0 ++ ++#define IEEE80211_SCTL_FRAG 0x000F ++#define IEEE80211_SCTL_SEQ 0xFFF0 ++ ++/* QOS control */ ++#define IEEE80211_QCTL_TID 0x000F ++ ++#define FC_QOS_BIT BIT7 ++#define IsDataFrame(pdu) ( ((pdu[0] & 0x0C)==0x08) ? true : false ) ++#define IsLegacyDataFrame(pdu) (IsDataFrame(pdu) && (!(pdu[0]&FC_QOS_BIT)) ) ++//added by wb. Is this right? ++#define IsQoSDataFrame(pframe) ((*(u16*)pframe&(IEEE80211_STYPE_QOS_DATA|IEEE80211_FTYPE_DATA)) == (IEEE80211_STYPE_QOS_DATA|IEEE80211_FTYPE_DATA)) ++#define Frame_Order(pframe) (*(u16*)pframe&IEEE80211_FCTL_ORDER) ++#define SN_LESS(a, b) (((a-b)&0x800)!=0) ++#define SN_EQUAL(a, b) (a == b) ++#define MAX_DEV_ADDR_SIZE 8 ++typedef enum _ACT_CATEGORY{ ++ ACT_CAT_QOS = 1, ++ ACT_CAT_DLS = 2, ++ ACT_CAT_BA = 3, ++ ACT_CAT_HT = 7, ++ ACT_CAT_WMM = 17, ++} ACT_CATEGORY, *PACT_CATEGORY; ++ ++typedef enum _TS_ACTION{ ++ ACT_ADDTSREQ = 0, ++ ACT_ADDTSRSP = 1, ++ ACT_DELTS = 2, ++ ACT_SCHEDULE = 3, ++} TS_ACTION, *PTS_ACTION; ++ ++typedef enum _BA_ACTION{ ++ ACT_ADDBAREQ = 0, ++ ACT_ADDBARSP = 1, ++ ACT_DELBA = 2, ++} BA_ACTION, *PBA_ACTION; ++ ++typedef enum _InitialGainOpType{ ++ IG_Backup=0, ++ IG_Restore, ++ IG_Max ++}InitialGainOpType; ++ ++/* debug macros */ ++#define CONFIG_IEEE80211_DEBUG ++#ifdef CONFIG_IEEE80211_DEBUG ++extern u32 ieee80211_debug_level; ++#define IEEE80211_DEBUG(level, fmt, args...) \ ++do { if (ieee80211_debug_level & (level)) \ ++ printk(KERN_DEBUG "ieee80211: " fmt, ## args); } while (0) ++//wb added to debug out data buf ++//if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA ++#define IEEE80211_DEBUG_DATA(level, data, datalen) \ ++ do{ if ((ieee80211_debug_level & (level)) == (level)) \ ++ { \ ++ int i; \ ++ u8* pdata = (u8*) data; \ ++ printk(KERN_DEBUG "ieee80211: %s()\n", __FUNCTION__); \ ++ for(i=0; i<(int)(datalen); i++) \ ++ { \ ++ printk("%2x ", pdata[i]); \ ++ if ((i+1)%16 == 0) printk("\n"); \ ++ } \ ++ printk("\n"); \ ++ } \ ++ } while (0) ++#else ++#define IEEE80211_DEBUG(level, fmt, args...) do {} while (0) ++#define IEEE80211_DEBUG_DATA(level, data, datalen) do {} while(0) ++#endif /* CONFIG_IEEE80211_DEBUG */ ++ ++/* debug macros not dependent on CONFIG_IEEE80211_DEBUG */ ++ ++#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" ++#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] ++ ++/* ++ * To use the debug system; ++ * ++ * If you are defining a new debug classification, simply add it to the #define ++ * list here in the form of: ++ * ++ * #define IEEE80211_DL_xxxx VALUE ++ * ++ * shifting value to the left one bit from the previous entry. xxxx should be ++ * the name of the classification (for example, WEP) ++ * ++ * You then need to either add a IEEE80211_xxxx_DEBUG() macro definition for your ++ * classification, or use IEEE80211_DEBUG(IEEE80211_DL_xxxx, ...) whenever you want ++ * to send output to that classification. ++ * ++ * To add your debug level to the list of levels seen when you perform ++ * ++ * % cat /proc/net/ipw/debug_level ++ * ++ * you simply need to add your entry to the ipw_debug_levels array. ++ * ++ * If you do not see debug_level in /proc/net/ipw then you do not have ++ * CONFIG_IEEE80211_DEBUG defined in your kernel configuration ++ * ++ */ ++ ++#define IEEE80211_DL_INFO (1<<0) ++#define IEEE80211_DL_WX (1<<1) ++#define IEEE80211_DL_SCAN (1<<2) ++#define IEEE80211_DL_STATE (1<<3) ++#define IEEE80211_DL_MGMT (1<<4) ++#define IEEE80211_DL_FRAG (1<<5) ++#define IEEE80211_DL_EAP (1<<6) ++#define IEEE80211_DL_DROP (1<<7) ++ ++#define IEEE80211_DL_TX (1<<8) ++#define IEEE80211_DL_RX (1<<9) ++ ++#define IEEE80211_DL_HT (1<<10) //HT ++#define IEEE80211_DL_BA (1<<11) //ba ++#define IEEE80211_DL_TS (1<<12) //TS ++#define IEEE80211_DL_QOS (1<<13) ++#define IEEE80211_DL_REORDER (1<<14) ++#define IEEE80211_DL_IOT (1<<15) ++#define IEEE80211_DL_IPS (1<<16) ++#define IEEE80211_DL_TRACE (1<<29) //trace function, need to user net_ratelimit() together in order not to print too much to the screen ++#define IEEE80211_DL_DATA (1<<30) //use this flag to control whether print data buf out. ++#define IEEE80211_DL_ERR (1<<31) //always open ++#define IEEE80211_ERROR(f, a...) printk(KERN_ERR "ieee80211: " f, ## a) ++#define IEEE80211_WARNING(f, a...) printk(KERN_WARNING "ieee80211: " f, ## a) ++#define IEEE80211_DEBUG_INFO(f, a...) IEEE80211_DEBUG(IEEE80211_DL_INFO, f, ## a) ++ ++#define IEEE80211_DEBUG_WX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_WX, f, ## a) ++#define IEEE80211_DEBUG_SCAN(f, a...) IEEE80211_DEBUG(IEEE80211_DL_SCAN, f, ## a) ++#define IEEE80211_DEBUG_STATE(f, a...) IEEE80211_DEBUG(IEEE80211_DL_STATE, f, ## a) ++#define IEEE80211_DEBUG_MGMT(f, a...) IEEE80211_DEBUG(IEEE80211_DL_MGMT, f, ## a) ++#define IEEE80211_DEBUG_FRAG(f, a...) IEEE80211_DEBUG(IEEE80211_DL_FRAG, f, ## a) ++#define IEEE80211_DEBUG_EAP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_EAP, f, ## a) ++#define IEEE80211_DEBUG_DROP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_DROP, f, ## a) ++#define IEEE80211_DEBUG_TX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_TX, f, ## a) ++#define IEEE80211_DEBUG_RX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_RX, f, ## a) ++#define IEEE80211_DEBUG_QOS(f, a...) IEEE80211_DEBUG(IEEE80211_DL_QOS, f, ## a) ++ ++#ifdef CONFIG_IEEE80211_DEBUG ++/* Added by Annie, 2005-11-22. */ ++#define MAX_STR_LEN 64 ++/* I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.*/ ++#define PRINTABLE(_ch) (_ch>'!' && _ch<'~') ++#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) \ ++ if((_Comp) & level) \ ++ { \ ++ int __i; \ ++ u8 buffer[MAX_STR_LEN]; \ ++ int length = (_Len\n", _Len, buffer); \ ++ } ++#else ++#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) do {} while (0) ++#endif ++ ++#include ++#include /* ARPHRD_ETHER */ ++ ++#ifndef WIRELESS_SPY ++#define WIRELESS_SPY // enable iwspy support ++#endif ++#include // new driver API ++ ++#ifndef ETH_P_PAE ++#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ ++#endif /* ETH_P_PAE */ ++ ++#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */ ++ ++#ifndef ETH_P_80211_RAW ++#define ETH_P_80211_RAW (ETH_P_ECONET + 1) ++#endif ++ ++/* IEEE 802.11 defines */ ++ ++#define P80211_OUI_LEN 3 ++ ++struct ieee80211_snap_hdr { ++ ++ u8 dsap; /* always 0xAA */ ++ u8 ssap; /* always 0xAA */ ++ u8 ctrl; /* always 0x03 */ ++ u8 oui[P80211_OUI_LEN]; /* organizational universal id */ ++ ++} __attribute__ ((packed)); ++ ++#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) ++ ++#define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS) ++#define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE) ++#define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE) ++ ++#define WLAN_FC_GET_FRAMETYPE(fc) ((fc) & IEEE80211_FCTL_FRAMETYPE) ++#define WLAN_GET_SEQ_FRAG(seq) ((seq) & IEEE80211_SCTL_FRAG) ++#define WLAN_GET_SEQ_SEQ(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) ++ ++/* Authentication algorithms */ ++#define WLAN_AUTH_OPEN 0 ++#define WLAN_AUTH_SHARED_KEY 1 ++#define WLAN_AUTH_LEAP 2 ++ ++#define WLAN_AUTH_CHALLENGE_LEN 128 ++ ++#define WLAN_CAPABILITY_BSS (1<<0) ++#define WLAN_CAPABILITY_IBSS (1<<1) ++#define WLAN_CAPABILITY_CF_POLLABLE (1<<2) ++#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3) ++#define WLAN_CAPABILITY_PRIVACY (1<<4) ++#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5) ++#define WLAN_CAPABILITY_PBCC (1<<6) ++#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7) ++#define WLAN_CAPABILITY_SPECTRUM_MGMT (1<<8) ++#define WLAN_CAPABILITY_QOS (1<<9) ++#define WLAN_CAPABILITY_SHORT_SLOT (1<<10) ++#define WLAN_CAPABILITY_DSSS_OFDM (1<<13) ++ ++/* 802.11g ERP information element */ ++#define WLAN_ERP_NON_ERP_PRESENT (1<<0) ++#define WLAN_ERP_USE_PROTECTION (1<<1) ++#define WLAN_ERP_BARKER_PREAMBLE (1<<2) ++ ++/* Status codes */ ++enum ieee80211_statuscode { ++ WLAN_STATUS_SUCCESS = 0, ++ WLAN_STATUS_UNSPECIFIED_FAILURE = 1, ++ WLAN_STATUS_CAPS_UNSUPPORTED = 10, ++ WLAN_STATUS_REASSOC_NO_ASSOC = 11, ++ WLAN_STATUS_ASSOC_DENIED_UNSPEC = 12, ++ WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG = 13, ++ WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION = 14, ++ WLAN_STATUS_CHALLENGE_FAIL = 15, ++ WLAN_STATUS_AUTH_TIMEOUT = 16, ++ WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA = 17, ++ WLAN_STATUS_ASSOC_DENIED_RATES = 18, ++ /* 802.11b */ ++ WLAN_STATUS_ASSOC_DENIED_NOSHORTPREAMBLE = 19, ++ WLAN_STATUS_ASSOC_DENIED_NOPBCC = 20, ++ WLAN_STATUS_ASSOC_DENIED_NOAGILITY = 21, ++ /* 802.11h */ ++ WLAN_STATUS_ASSOC_DENIED_NOSPECTRUM = 22, ++ WLAN_STATUS_ASSOC_REJECTED_BAD_POWER = 23, ++ WLAN_STATUS_ASSOC_REJECTED_BAD_SUPP_CHAN = 24, ++ /* 802.11g */ ++ WLAN_STATUS_ASSOC_DENIED_NOSHORTTIME = 25, ++ WLAN_STATUS_ASSOC_DENIED_NODSSSOFDM = 26, ++ /* 802.11i */ ++ WLAN_STATUS_INVALID_IE = 40, ++ WLAN_STATUS_INVALID_GROUP_CIPHER = 41, ++ WLAN_STATUS_INVALID_PAIRWISE_CIPHER = 42, ++ WLAN_STATUS_INVALID_AKMP = 43, ++ WLAN_STATUS_UNSUPP_RSN_VERSION = 44, ++ WLAN_STATUS_INVALID_RSN_IE_CAP = 45, ++ WLAN_STATUS_CIPHER_SUITE_REJECTED = 46, ++}; ++ ++/* Reason codes */ ++enum ieee80211_reasoncode { ++ WLAN_REASON_UNSPECIFIED = 1, ++ WLAN_REASON_PREV_AUTH_NOT_VALID = 2, ++ WLAN_REASON_DEAUTH_LEAVING = 3, ++ WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY = 4, ++ WLAN_REASON_DISASSOC_AP_BUSY = 5, ++ WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA = 6, ++ WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA = 7, ++ WLAN_REASON_DISASSOC_STA_HAS_LEFT = 8, ++ WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH = 9, ++ /* 802.11h */ ++ WLAN_REASON_DISASSOC_BAD_POWER = 10, ++ WLAN_REASON_DISASSOC_BAD_SUPP_CHAN = 11, ++ /* 802.11i */ ++ WLAN_REASON_INVALID_IE = 13, ++ WLAN_REASON_MIC_FAILURE = 14, ++ WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT = 15, ++ WLAN_REASON_GROUP_KEY_HANDSHAKE_TIMEOUT = 16, ++ WLAN_REASON_IE_DIFFERENT = 17, ++ WLAN_REASON_INVALID_GROUP_CIPHER = 18, ++ WLAN_REASON_INVALID_PAIRWISE_CIPHER = 19, ++ WLAN_REASON_INVALID_AKMP = 20, ++ WLAN_REASON_UNSUPP_RSN_VERSION = 21, ++ WLAN_REASON_INVALID_RSN_IE_CAP = 22, ++ WLAN_REASON_IEEE8021X_FAILED = 23, ++ WLAN_REASON_CIPHER_SUITE_REJECTED = 24, ++}; ++ ++#define IEEE80211_STATMASK_SIGNAL (1<<0) ++#define IEEE80211_STATMASK_RSSI (1<<1) ++#define IEEE80211_STATMASK_NOISE (1<<2) ++#define IEEE80211_STATMASK_RATE (1<<3) ++#define IEEE80211_STATMASK_WEMASK 0x7 ++ ++#define IEEE80211_CCK_MODULATION (1<<0) ++#define IEEE80211_OFDM_MODULATION (1<<1) ++ ++#define IEEE80211_24GHZ_BAND (1<<0) ++#define IEEE80211_52GHZ_BAND (1<<1) ++ ++#define IEEE80211_CCK_RATE_LEN 4 ++#define IEEE80211_CCK_RATE_1MB 0x02 ++#define IEEE80211_CCK_RATE_2MB 0x04 ++#define IEEE80211_CCK_RATE_5MB 0x0B ++#define IEEE80211_CCK_RATE_11MB 0x16 ++#define IEEE80211_OFDM_RATE_LEN 8 ++#define IEEE80211_OFDM_RATE_6MB 0x0C ++#define IEEE80211_OFDM_RATE_9MB 0x12 ++#define IEEE80211_OFDM_RATE_12MB 0x18 ++#define IEEE80211_OFDM_RATE_18MB 0x24 ++#define IEEE80211_OFDM_RATE_24MB 0x30 ++#define IEEE80211_OFDM_RATE_36MB 0x48 ++#define IEEE80211_OFDM_RATE_48MB 0x60 ++#define IEEE80211_OFDM_RATE_54MB 0x6C ++#define IEEE80211_BASIC_RATE_MASK 0x80 ++ ++#define IEEE80211_CCK_RATE_1MB_MASK (1<<0) ++#define IEEE80211_CCK_RATE_2MB_MASK (1<<1) ++#define IEEE80211_CCK_RATE_5MB_MASK (1<<2) ++#define IEEE80211_CCK_RATE_11MB_MASK (1<<3) ++#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4) ++#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5) ++#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6) ++#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7) ++#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8) ++#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9) ++#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10) ++#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11) ++ ++#define IEEE80211_CCK_RATES_MASK 0x0000000F ++#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \ ++ IEEE80211_CCK_RATE_2MB_MASK) ++#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \ ++ IEEE80211_CCK_RATE_5MB_MASK | \ ++ IEEE80211_CCK_RATE_11MB_MASK) ++ ++#define IEEE80211_OFDM_RATES_MASK 0x00000FF0 ++#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \ ++ IEEE80211_OFDM_RATE_12MB_MASK | \ ++ IEEE80211_OFDM_RATE_24MB_MASK) ++#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \ ++ IEEE80211_OFDM_RATE_9MB_MASK | \ ++ IEEE80211_OFDM_RATE_18MB_MASK | \ ++ IEEE80211_OFDM_RATE_36MB_MASK | \ ++ IEEE80211_OFDM_RATE_48MB_MASK | \ ++ IEEE80211_OFDM_RATE_54MB_MASK) ++#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ ++ IEEE80211_CCK_DEFAULT_RATES_MASK) ++ ++#define IEEE80211_NUM_OFDM_RATES 8 ++#define IEEE80211_NUM_CCK_RATES 4 ++#define IEEE80211_OFDM_SHIFT_MASK_A 4 ++ ++ ++/* this is stolen and modified from the madwifi driver*/ ++#define IEEE80211_FC0_TYPE_MASK 0x0c ++#define IEEE80211_FC0_TYPE_DATA 0x08 ++#define IEEE80211_FC0_SUBTYPE_MASK 0xB0 ++#define IEEE80211_FC0_SUBTYPE_QOS 0x80 ++ ++#define IEEE80211_QOS_HAS_SEQ(fc) \ ++ (((fc) & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == \ ++ (IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_QOS)) ++ ++/* this is stolen from ipw2200 driver */ ++#define IEEE_IBSS_MAC_HASH_SIZE 31 ++struct ieee_ibss_seq { ++ u8 mac[ETH_ALEN]; ++ u16 seq_num[17]; ++ u16 frag_num[17]; ++ unsigned long packet_time[17]; ++ struct list_head list; ++}; ++ ++/* NOTE: This data is for statistical purposes; not all hardware provides this ++ * information for frames received. Not setting these will not cause ++ * any adverse affects. */ ++struct ieee80211_rx_stats { ++#if 1 ++ u32 mac_time[2]; ++ s8 rssi; ++ u8 signal; ++ u8 noise; ++ u16 rate; /* in 100 kbps */ ++ u8 received_channel; ++ u8 control; ++ u8 mask; ++ u8 freq; ++ u16 len; ++ u64 tsf; ++ u32 beacon_time; ++ u8 nic_type; ++ u16 Length; ++ // u8 DataRate; // In 0.5 Mbps ++ u8 SignalQuality; // in 0-100 index. ++ s32 RecvSignalPower; // Real power in dBm for this packet, no beautification and aggregation. ++ s8 RxPower; // in dBm Translate from PWdB ++ u8 SignalStrength; // in 0-100 index. ++ u16 bHwError:1; ++ u16 bCRC:1; ++ u16 bICV:1; ++ u16 bShortPreamble:1; ++ u16 Antenna:1; //for rtl8185 ++ u16 Decrypted:1; //for rtl8185, rtl8187 ++ u16 Wakeup:1; //for rtl8185 ++ u16 Reserved0:1; //for rtl8185 ++ u8 AGC; ++ u32 TimeStampLow; ++ u32 TimeStampHigh; ++ bool bShift; ++ bool bIsQosData; // Added by Annie, 2005-12-22. ++ u8 UserPriority; ++ ++ //1!!!!!!!!!!!!!!!!!!!!!!!!!!! ++ //1Attention Please!!!<11n or 8190 specific code should be put below this line> ++ //1!!!!!!!!!!!!!!!!!!!!!!!!!!! ++ ++ u8 RxDrvInfoSize; ++ u8 RxBufShift; ++ bool bIsAMPDU; ++ bool bFirstMPDU; ++ bool bContainHTC; ++ bool RxIs40MHzPacket; ++ u32 RxPWDBAll; ++ u8 RxMIMOSignalStrength[4]; // in 0~100 index ++ s8 RxMIMOSignalQuality[2]; ++ bool bPacketMatchBSSID; ++ bool bIsCCK; ++ bool bPacketToSelf; ++ //added by amy ++ u8* virtual_address; ++ u16 packetlength; // Total packet length: Must equal to sum of all FragLength ++ u16 fraglength; // FragLength should equal to PacketLength in non-fragment case ++ u16 fragoffset; // Data offset for this fragment ++ u16 ntotalfrag; ++ bool bisrxaggrsubframe; ++ bool bPacketBeacon; //cosa add for rssi ++ bool bToSelfBA; //cosa add for rssi ++ char cck_adc_pwdb[4]; //cosa add for rx path selection ++ u16 Seq_Num; ++#endif ++ ++}; ++ ++/* IEEE 802.11 requires that STA supports concurrent reception of at least ++ * three fragmented frames. This define can be increased to support more ++ * concurrent frames, but it should be noted that each entry can consume about ++ * 2 kB of RAM and increasing cache size will slow down frame reassembly. */ ++#define IEEE80211_FRAG_CACHE_LEN 4 ++ ++struct ieee80211_frag_entry { ++ unsigned long first_frag_time; ++ unsigned int seq; ++ unsigned int last_frag; ++ struct sk_buff *skb; ++ u8 src_addr[ETH_ALEN]; ++ u8 dst_addr[ETH_ALEN]; ++}; ++ ++struct ieee80211_stats { ++ unsigned int tx_unicast_frames; ++ unsigned int tx_multicast_frames; ++ unsigned int tx_fragments; ++ unsigned int tx_unicast_octets; ++ unsigned int tx_multicast_octets; ++ unsigned int tx_deferred_transmissions; ++ unsigned int tx_single_retry_frames; ++ unsigned int tx_multiple_retry_frames; ++ unsigned int tx_retry_limit_exceeded; ++ unsigned int tx_discards; ++ unsigned int rx_unicast_frames; ++ unsigned int rx_multicast_frames; ++ unsigned int rx_fragments; ++ unsigned int rx_unicast_octets; ++ unsigned int rx_multicast_octets; ++ unsigned int rx_fcs_errors; ++ unsigned int rx_discards_no_buffer; ++ unsigned int tx_discards_wrong_sa; ++ unsigned int rx_discards_undecryptable; ++ unsigned int rx_message_in_msg_fragments; ++ unsigned int rx_message_in_bad_msg_fragments; ++}; ++ ++struct ieee80211_device; ++ ++#include "ieee80211_crypt.h" ++ ++#define SEC_KEY_1 (1<<0) ++#define SEC_KEY_2 (1<<1) ++#define SEC_KEY_3 (1<<2) ++#define SEC_KEY_4 (1<<3) ++#define SEC_ACTIVE_KEY (1<<4) ++#define SEC_AUTH_MODE (1<<5) ++#define SEC_UNICAST_GROUP (1<<6) ++#define SEC_LEVEL (1<<7) ++#define SEC_ENABLED (1<<8) ++#define SEC_ENCRYPT (1<<9) ++ ++#define SEC_LEVEL_0 0 /* None */ ++#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */ ++#define SEC_LEVEL_2 2 /* Level 1 + TKIP */ ++#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */ ++#define SEC_LEVEL_3 4 /* Level 2 + CCMP */ ++ ++#define SEC_ALG_NONE 0 ++#define SEC_ALG_WEP 1 ++#define SEC_ALG_TKIP 2 ++#define SEC_ALG_CCMP 3 ++ ++#define WEP_KEYS 4 ++#define WEP_KEY_LEN 13 ++#define SCM_KEY_LEN 32 ++#define SCM_TEMPORAL_KEY_LENGTH 16 ++ ++struct ieee80211_security { ++ u16 active_key:2, ++ enabled:1, ++ auth_mode:2, ++ auth_algo:4, ++ unicast_uses_group:1, ++ encrypt:1; ++ u8 key_sizes[WEP_KEYS]; ++ u8 keys[WEP_KEYS][SCM_KEY_LEN]; ++ u8 level; ++ u16 flags; ++} __attribute__ ((packed)); ++ ++ ++/* ++ 802.11 data frame from AP ++ ,-------------------------------------------------------------------. ++Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 | ++ |------|------|---------|---------|---------|------|---------|------| ++Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs | ++ | | tion | (BSSID) | | | ence | data | | ++ `-------------------------------------------------------------------' ++Total: 28-2340 bytes ++*/ ++ ++/* Management Frame Information Element Types */ ++enum ieee80211_mfie { ++ MFIE_TYPE_SSID = 0, ++ MFIE_TYPE_RATES = 1, ++ MFIE_TYPE_FH_SET = 2, ++ MFIE_TYPE_DS_SET = 3, ++ MFIE_TYPE_CF_SET = 4, ++ MFIE_TYPE_TIM = 5, ++ MFIE_TYPE_IBSS_SET = 6, ++ MFIE_TYPE_COUNTRY = 7, ++ MFIE_TYPE_HOP_PARAMS = 8, ++ MFIE_TYPE_HOP_TABLE = 9, ++ MFIE_TYPE_REQUEST = 10, ++ MFIE_TYPE_CHALLENGE = 16, ++ MFIE_TYPE_POWER_CONSTRAINT = 32, ++ MFIE_TYPE_POWER_CAPABILITY = 33, ++ MFIE_TYPE_TPC_REQUEST = 34, ++ MFIE_TYPE_TPC_REPORT = 35, ++ MFIE_TYPE_SUPP_CHANNELS = 36, ++ MFIE_TYPE_CSA = 37, ++ MFIE_TYPE_MEASURE_REQUEST = 38, ++ MFIE_TYPE_MEASURE_REPORT = 39, ++ MFIE_TYPE_QUIET = 40, ++ MFIE_TYPE_IBSS_DFS = 41, ++ MFIE_TYPE_ERP = 42, ++ MFIE_TYPE_RSN = 48, ++ MFIE_TYPE_RATES_EX = 50, ++ MFIE_TYPE_HT_CAP= 45, ++ MFIE_TYPE_HT_INFO= 61, ++ MFIE_TYPE_AIRONET=133, ++ MFIE_TYPE_GENERIC = 221, ++ MFIE_TYPE_QOS_PARAMETER = 222, ++}; ++ ++/* Minimal header; can be used for passing 802.11 frames with sufficient ++ * information to determine what type of underlying data type is actually ++ * stored in the data. */ ++struct ieee80211_hdr { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 payload[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_hdr_1addr { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 payload[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_hdr_2addr { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 payload[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_hdr_3addr { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ __le16 seq_ctl; ++ u8 payload[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_hdr_4addr { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ __le16 seq_ctl; ++ u8 addr4[ETH_ALEN]; ++ u8 payload[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_hdr_3addrqos { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ __le16 seq_ctl; ++ u8 payload[0]; ++ __le16 qos_ctl; ++} __attribute__ ((packed)); ++ ++struct ieee80211_hdr_4addrqos { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ __le16 seq_ctl; ++ u8 addr4[ETH_ALEN]; ++ u8 payload[0]; ++ __le16 qos_ctl; ++} __attribute__ ((packed)); ++ ++struct ieee80211_info_element { ++ u8 id; ++ u8 len; ++ u8 data[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_authentication { ++ struct ieee80211_hdr_3addr header; ++ __le16 algorithm; ++ __le16 transaction; ++ __le16 status; ++ /*challenge*/ ++ struct ieee80211_info_element info_element[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_disassoc { ++ struct ieee80211_hdr_3addr header; ++ __le16 reason; ++} __attribute__ ((packed)); ++ ++struct ieee80211_probe_request { ++ struct ieee80211_hdr_3addr header; ++ /* SSID, supported rates */ ++ struct ieee80211_info_element info_element[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_probe_response { ++ struct ieee80211_hdr_3addr header; ++ u32 time_stamp[2]; ++ __le16 beacon_interval; ++ __le16 capability; ++ /* SSID, supported rates, FH params, DS params, ++ * CF params, IBSS params, TIM (if beacon), RSN */ ++ struct ieee80211_info_element info_element[0]; ++} __attribute__ ((packed)); ++ ++/* Alias beacon for probe_response */ ++#define ieee80211_beacon ieee80211_probe_response ++ ++struct ieee80211_assoc_request_frame { ++ struct ieee80211_hdr_3addr header; ++ __le16 capability; ++ __le16 listen_interval; ++ /* SSID, supported rates, RSN */ ++ struct ieee80211_info_element info_element[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_reassoc_request_frame { ++ struct ieee80211_hdr_3addr header; ++ __le16 capability; ++ __le16 listen_interval; ++ u8 current_ap[ETH_ALEN]; ++ /* SSID, supported rates, RSN */ ++ struct ieee80211_info_element info_element[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_assoc_response_frame { ++ struct ieee80211_hdr_3addr header; ++ __le16 capability; ++ __le16 status; ++ __le16 aid; ++ struct ieee80211_info_element info_element[0]; /* supported rates */ ++} __attribute__ ((packed)); ++ ++struct ieee80211_txb { ++ u8 nr_frags; ++ u8 encrypted; ++ u8 queue_index; ++ u8 rts_included; ++ u16 reserved; ++ __le16 frag_size; ++ __le16 payload_size; ++ struct sk_buff *fragments[0]; ++}; ++ ++#define MAX_TX_AGG_COUNT 16 ++struct ieee80211_drv_agg_txb { ++ u8 nr_drv_agg_frames; ++ struct sk_buff *tx_agg_frames[MAX_TX_AGG_COUNT]; ++}__attribute__((packed)); ++ ++#define MAX_SUBFRAME_COUNT 64 ++struct ieee80211_rxb { ++ u8 nr_subframes; ++ struct sk_buff *subframes[MAX_SUBFRAME_COUNT]; ++ u8 dst[ETH_ALEN]; ++ u8 src[ETH_ALEN]; ++}__attribute__((packed)); ++ ++typedef union _frameqos { ++ u16 shortdata; ++ u8 chardata[2]; ++ struct { ++ u16 tid:4; ++ u16 eosp:1; ++ u16 ack_policy:2; ++ u16 reserved:1; ++ u16 txop:8; ++ }field; ++}frameqos,*pframeqos; ++ ++/* SWEEP TABLE ENTRIES NUMBER*/ ++#define MAX_SWEEP_TAB_ENTRIES 42 ++#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7 ++/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs ++ * only use 8, and then use extended rates for the remaining supported ++ * rates. Other APs, however, stick all of their supported rates on the ++ * main rates information element... */ ++#define MAX_RATES_LENGTH ((u8)12) ++#define MAX_RATES_EX_LENGTH ((u8)16) ++#define MAX_NETWORK_COUNT 128 ++ ++#define MAX_CHANNEL_NUMBER 161 ++#define IEEE80211_SOFTMAC_SCAN_TIME 100 ++//(HZ / 2) ++#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2) ++ ++#define CRC_LENGTH 4U ++ ++#define MAX_WPA_IE_LEN 64 ++ ++#define NETWORK_EMPTY_ESSID (1<<0) ++#define NETWORK_HAS_OFDM (1<<1) ++#define NETWORK_HAS_CCK (1<<2) ++ ++/* QoS structure */ ++#define NETWORK_HAS_QOS_PARAMETERS (1<<3) ++#define NETWORK_HAS_QOS_INFORMATION (1<<4) ++#define NETWORK_HAS_QOS_MASK (NETWORK_HAS_QOS_PARAMETERS | \ ++ NETWORK_HAS_QOS_INFORMATION) ++/* 802.11h */ ++#define NETWORK_HAS_POWER_CONSTRAINT (1<<5) ++#define NETWORK_HAS_CSA (1<<6) ++#define NETWORK_HAS_QUIET (1<<7) ++#define NETWORK_HAS_IBSS_DFS (1<<8) ++#define NETWORK_HAS_TPC_REPORT (1<<9) ++ ++#define NETWORK_HAS_ERP_VALUE (1<<10) ++ ++#define QOS_QUEUE_NUM 4 ++#define QOS_OUI_LEN 3 ++#define QOS_OUI_TYPE 2 ++#define QOS_ELEMENT_ID 221 ++#define QOS_OUI_INFO_SUB_TYPE 0 ++#define QOS_OUI_PARAM_SUB_TYPE 1 ++#define QOS_VERSION_1 1 ++#define QOS_AIFSN_MIN_VALUE 2 ++#if 1 ++struct ieee80211_qos_information_element { ++ u8 elementID; ++ u8 length; ++ u8 qui[QOS_OUI_LEN]; ++ u8 qui_type; ++ u8 qui_subtype; ++ u8 version; ++ u8 ac_info; ++} __attribute__ ((packed)); ++ ++struct ieee80211_qos_ac_parameter { ++ u8 aci_aifsn; ++ u8 ecw_min_max; ++ __le16 tx_op_limit; ++} __attribute__ ((packed)); ++ ++struct ieee80211_qos_parameter_info { ++ struct ieee80211_qos_information_element info_element; ++ u8 reserved; ++ struct ieee80211_qos_ac_parameter ac_params_record[QOS_QUEUE_NUM]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_qos_parameters { ++ __le16 cw_min[QOS_QUEUE_NUM]; ++ __le16 cw_max[QOS_QUEUE_NUM]; ++ u8 aifs[QOS_QUEUE_NUM]; ++ u8 flag[QOS_QUEUE_NUM]; ++ __le16 tx_op_limit[QOS_QUEUE_NUM]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_qos_data { ++ struct ieee80211_qos_parameters parameters; ++ int active; ++ int supported; ++ u8 param_count; ++ u8 old_param_count; ++}; ++ ++struct ieee80211_tim_parameters { ++ u8 tim_count; ++ u8 tim_period; ++} __attribute__ ((packed)); ++ ++//#else ++struct ieee80211_wmm_ac_param { ++ u8 ac_aci_acm_aifsn; ++ u8 ac_ecwmin_ecwmax; ++ u16 ac_txop_limit; ++}; ++ ++struct ieee80211_wmm_ts_info { ++ u8 ac_dir_tid; ++ u8 ac_up_psb; ++ u8 reserved; ++} __attribute__ ((packed)); ++ ++struct ieee80211_wmm_tspec_elem { ++ struct ieee80211_wmm_ts_info ts_info; ++ u16 norm_msdu_size; ++ u16 max_msdu_size; ++ u32 min_serv_inter; ++ u32 max_serv_inter; ++ u32 inact_inter; ++ u32 suspen_inter; ++ u32 serv_start_time; ++ u32 min_data_rate; ++ u32 mean_data_rate; ++ u32 peak_data_rate; ++ u32 max_burst_size; ++ u32 delay_bound; ++ u32 min_phy_rate; ++ u16 surp_band_allow; ++ u16 medium_time; ++}__attribute__((packed)); ++#endif ++enum eap_type { ++ EAP_PACKET = 0, ++ EAPOL_START, ++ EAPOL_LOGOFF, ++ EAPOL_KEY, ++ EAPOL_ENCAP_ASF_ALERT ++}; ++ ++static const char *eap_types[] = { ++ [EAP_PACKET] = "EAP-Packet", ++ [EAPOL_START] = "EAPOL-Start", ++ [EAPOL_LOGOFF] = "EAPOL-Logoff", ++ [EAPOL_KEY] = "EAPOL-Key", ++ [EAPOL_ENCAP_ASF_ALERT] = "EAPOL-Encap-ASF-Alert" ++}; ++ ++static inline const char *eap_get_type(int type) ++{ ++ return ((u32)type >= ARRAY_SIZE(eap_types)) ? "Unknown" : eap_types[type]; ++} ++//added by amy for reorder ++static inline u8 Frame_QoSTID(u8* buf) ++{ ++ struct ieee80211_hdr_3addr *hdr; ++ u16 fc; ++ hdr = (struct ieee80211_hdr_3addr *)buf; ++ fc = le16_to_cpu(hdr->frame_ctl); ++ return (u8)((frameqos*)(buf + (((fc & IEEE80211_FCTL_TODS)&&(fc & IEEE80211_FCTL_FROMDS))? 30 : 24)))->field.tid; ++} ++ ++//added by amy for reorder ++ ++struct eapol { ++ u8 snap[6]; ++ u16 ethertype; ++ u8 version; ++ u8 type; ++ u16 length; ++} __attribute__ ((packed)); ++ ++struct ieee80211_softmac_stats{ ++ unsigned int rx_ass_ok; ++ unsigned int rx_ass_err; ++ unsigned int rx_probe_rq; ++ unsigned int tx_probe_rs; ++ unsigned int tx_beacons; ++ unsigned int rx_auth_rq; ++ unsigned int rx_auth_rs_ok; ++ unsigned int rx_auth_rs_err; ++ unsigned int tx_auth_rq; ++ unsigned int no_auth_rs; ++ unsigned int no_ass_rs; ++ unsigned int tx_ass_rq; ++ unsigned int rx_ass_rq; ++ unsigned int tx_probe_rq; ++ unsigned int reassoc; ++ unsigned int swtxstop; ++ unsigned int swtxawake; ++ unsigned char CurrentShowTxate; ++ unsigned char last_packet_rate; ++ unsigned int txretrycount; ++}; ++ ++#define BEACON_PROBE_SSID_ID_POSITION 12 ++ ++struct ieee80211_info_element_hdr { ++ u8 id; ++ u8 len; ++} __attribute__ ((packed)); ++ ++/* ++ * These are the data types that can make up management packets ++ * ++ u16 auth_algorithm; ++ u16 auth_sequence; ++ u16 beacon_interval; ++ u16 capability; ++ u8 current_ap[ETH_ALEN]; ++ u16 listen_interval; ++ struct { ++ u16 association_id:14, reserved:2; ++ } __attribute__ ((packed)); ++ u32 time_stamp[2]; ++ u16 reason; ++ u16 status; ++*/ ++ ++#define IEEE80211_DEFAULT_TX_ESSID "Penguin" ++#define IEEE80211_DEFAULT_BASIC_RATE 2 //1Mbps ++ ++enum {WMM_all_frame, WMM_two_frame, WMM_four_frame, WMM_six_frame}; ++#define MAX_SP_Len (WMM_all_frame << 4) ++#define IEEE80211_QOS_TID 0x0f ++#define QOS_CTL_NOTCONTAIN_ACK (0x01 << 5) ++ ++#define IEEE80211_DTIM_MBCAST 4 ++#define IEEE80211_DTIM_UCAST 2 ++#define IEEE80211_DTIM_VALID 1 ++#define IEEE80211_DTIM_INVALID 0 ++ ++#define IEEE80211_PS_DISABLED 0 ++#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST ++#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST ++ ++//added by David for QoS 2006/6/30 ++//#define WMM_Hang_8187 ++#ifdef WMM_Hang_8187 ++#undef WMM_Hang_8187 ++#endif ++ ++#define WME_AC_BK 0x00 ++#define WME_AC_BE 0x01 ++#define WME_AC_VI 0x02 ++#define WME_AC_VO 0x03 ++#define WME_ACI_MASK 0x03 ++#define WME_AIFSN_MASK 0x03 ++#define WME_AC_PRAM_LEN 16 ++ ++#define MAX_RECEIVE_BUFFER_SIZE 9100 ++ ++//UP Mapping to AC, using in MgntQuery_SequenceNumber() and maybe for DSCP ++//#define UP2AC(up) ((up<3) ? ((up==0)?1:0) : (up>>1)) ++#if 1 ++#define UP2AC(up) ( \ ++ ((up) < 1) ? WME_AC_BE : \ ++ ((up) < 3) ? WME_AC_BK : \ ++ ((up) < 4) ? WME_AC_BE : \ ++ ((up) < 6) ? WME_AC_VI : \ ++ WME_AC_VO) ++#endif ++//AC Mapping to UP, using in Tx part for selecting the corresponding TX queue ++#define AC2UP(_ac) ( \ ++ ((_ac) == WME_AC_VO) ? 6 : \ ++ ((_ac) == WME_AC_VI) ? 5 : \ ++ ((_ac) == WME_AC_BK) ? 1 : \ ++ 0) ++ ++#define ETHER_ADDR_LEN 6 /* length of an Ethernet address */ ++#define ETHERNET_HEADER_SIZE 14 /* length of two Ethernet address plus ether type*/ ++ ++struct ether_header { ++ u8 ether_dhost[ETHER_ADDR_LEN]; ++ u8 ether_shost[ETHER_ADDR_LEN]; ++ u16 ether_type; ++} __attribute__((packed)); ++ ++#ifndef ETHERTYPE_PAE ++#define ETHERTYPE_PAE 0x888e /* EAPOL PAE/802.1x */ ++#endif ++#ifndef ETHERTYPE_IP ++#define ETHERTYPE_IP 0x0800 /* IP protocol */ ++#endif ++ ++typedef struct _bss_ht{ ++ ++ bool support_ht; ++ ++ // HT related elements ++ u8 ht_cap_buf[32]; ++ u16 ht_cap_len; ++ u8 ht_info_buf[32]; ++ u16 ht_info_len; ++ ++ HT_SPEC_VER ht_spec_ver; ++ //HT_CAPABILITY_ELE bdHTCapEle; ++ //HT_INFORMATION_ELE bdHTInfoEle; ++ ++ bool aggregation; ++ bool long_slot_time; ++}bss_ht, *pbss_ht; ++ ++typedef enum _erp_t{ ++ ERP_NonERPpresent = 0x01, ++ ERP_UseProtection = 0x02, ++ ERP_BarkerPreambleMode = 0x04, ++} erp_t; ++ ++ ++struct ieee80211_network { ++ /* These entries are used to identify a unique network */ ++ u8 bssid[ETH_ALEN]; ++ u8 channel; ++ /* Ensure null-terminated for any debug msgs */ ++ u8 ssid[IW_ESSID_MAX_SIZE + 1]; ++ u8 ssid_len; ++#if 1 ++ struct ieee80211_qos_data qos_data; ++#else ++ // Qos related. Added by Annie, 2005-11-01. ++ BSS_QOS BssQos; ++#endif ++ ++ //added by amy for LEAP ++ bool bWithAironetIE; ++ bool bCkipSupported; ++ bool bCcxRmEnable; ++ u16 CcxRmState[2]; ++ // CCXv4 S59, MBSSID. ++ bool bMBssidValid; ++ u8 MBssidMask; ++ u8 MBssid[6]; ++ // CCX 2 S38, WLAN Device Version Number element. Annie, 2006-08-20. ++ bool bWithCcxVerNum; ++ u8 BssCcxVerNumber; ++ /* These are network statistics */ ++ struct ieee80211_rx_stats stats; ++ u16 capability; ++ u8 rates[MAX_RATES_LENGTH]; ++ u8 rates_len; ++ u8 rates_ex[MAX_RATES_EX_LENGTH]; ++ u8 rates_ex_len; ++ unsigned long last_scanned; ++ u8 mode; ++ u32 flags; ++ u32 last_associate; ++ u32 time_stamp[2]; ++ u16 beacon_interval; ++ u16 listen_interval; ++ u16 atim_window; ++ u8 erp_value; ++ u8 wpa_ie[MAX_WPA_IE_LEN]; ++ size_t wpa_ie_len; ++ u8 rsn_ie[MAX_WPA_IE_LEN]; ++ size_t rsn_ie_len; ++ ++ struct ieee80211_tim_parameters tim; ++ u8 dtim_period; ++ u8 dtim_data; ++ u32 last_dtim_sta_time[2]; ++ ++ //appeded for QoS ++ u8 wmm_info; ++ struct ieee80211_wmm_ac_param wmm_param[4]; ++ u8 QoS_Enable; ++#ifdef THOMAS_TURBO ++ u8 Turbo_Enable;//enable turbo mode, added by thomas ++#endif ++#ifdef ENABLE_DOT11D ++ u16 CountryIeLen; ++ u8 CountryIeBuf[MAX_IE_LEN]; ++#endif ++ // HT Related, by amy, 2008.04.29 ++ BSS_HT bssht; ++ // Add to handle broadcom AP management frame CCK rate. ++ bool broadcom_cap_exist; ++ bool ralink_cap_exist; ++ bool atheros_cap_exist; ++ bool cisco_cap_exist; ++ bool unknown_cap_exist; ++// u8 berp_info; ++ bool berp_info_valid; ++ bool buseprotection; ++ //put at the end of the structure. ++ struct list_head list; ++}; ++ ++#if 1 ++enum ieee80211_state { ++ ++ /* the card is not linked at all */ ++ IEEE80211_NOLINK = 0, ++ ++ /* IEEE80211_ASSOCIATING* are for BSS client mode ++ * the driver shall not perform RX filtering unless ++ * the state is LINKED. ++ * The driver shall just check for the state LINKED and ++ * defaults to NOLINK for ALL the other states (including ++ * LINKED_SCANNING) ++ */ ++ ++ /* the association procedure will start (wq scheduling)*/ ++ IEEE80211_ASSOCIATING, ++ IEEE80211_ASSOCIATING_RETRY, ++ ++ /* the association procedure is sending AUTH request*/ ++ IEEE80211_ASSOCIATING_AUTHENTICATING, ++ ++ /* the association procedure has successfully authentcated ++ * and is sending association request ++ */ ++ IEEE80211_ASSOCIATING_AUTHENTICATED, ++ ++ /* the link is ok. the card associated to a BSS or linked ++ * to a ibss cell or acting as an AP and creating the bss ++ */ ++ IEEE80211_LINKED, ++ ++ /* same as LINKED, but the driver shall apply RX filter ++ * rules as we are in NO_LINK mode. As the card is still ++ * logically linked, but it is doing a syncro site survey ++ * then it will be back to LINKED state. ++ */ ++ IEEE80211_LINKED_SCANNING, ++ ++}; ++#else ++enum ieee80211_state { ++ IEEE80211_UNINITIALIZED = 0, ++ IEEE80211_INITIALIZED, ++ IEEE80211_ASSOCIATING, ++ IEEE80211_ASSOCIATED, ++ IEEE80211_AUTHENTICATING, ++ IEEE80211_AUTHENTICATED, ++ IEEE80211_SHUTDOWN ++}; ++#endif ++ ++#define DEFAULT_MAX_SCAN_AGE (15 * HZ) ++#define DEFAULT_FTS 2346 ++ ++#define CFG_IEEE80211_RESERVE_FCS (1<<0) ++#define CFG_IEEE80211_COMPUTE_FCS (1<<1) ++#define CFG_IEEE80211_RTS (1<<2) ++ ++#define IEEE80211_24GHZ_MIN_CHANNEL 1 ++#define IEEE80211_24GHZ_MAX_CHANNEL 14 ++#define IEEE80211_24GHZ_CHANNELS (IEEE80211_24GHZ_MAX_CHANNEL - \ ++ IEEE80211_24GHZ_MIN_CHANNEL + 1) ++ ++#define IEEE80211_52GHZ_MIN_CHANNEL 34 ++#define IEEE80211_52GHZ_MAX_CHANNEL 165 ++#define IEEE80211_52GHZ_CHANNELS (IEEE80211_52GHZ_MAX_CHANNEL - \ ++ IEEE80211_52GHZ_MIN_CHANNEL + 1) ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,11)) ++extern inline int is_multicast_ether_addr(const u8 *addr) ++{ ++ return ((addr[0] != 0xff) && (0x01 & addr[0])); ++} ++#endif ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13)) ++extern inline int is_broadcast_ether_addr(const u8 *addr) ++{ ++ return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \ ++ (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff)); ++} ++#endif ++ ++typedef struct tx_pending_t{ ++ int frag; ++ struct ieee80211_txb *txb; ++}tx_pending_t; ++ ++typedef struct _bandwidth_autoswitch ++{ ++ long threshold_20Mhzto40Mhz; ++ long threshold_40Mhzto20Mhz; ++ bool bforced_tx20Mhz; ++ bool bautoswitch_enable; ++}bandwidth_autoswitch,*pbandwidth_autoswitch; ++ ++ ++//added by amy for order ++ ++#define REORDER_WIN_SIZE 128 ++#define REORDER_ENTRY_NUM 128 ++typedef struct _RX_REORDER_ENTRY ++{ ++ struct list_head List; ++ u16 SeqNum; ++ struct ieee80211_rxb* prxb; ++} RX_REORDER_ENTRY, *PRX_REORDER_ENTRY; ++//added by amy for order ++typedef enum _Fsync_State{ ++ Default_Fsync, ++ HW_Fsync, ++ SW_Fsync ++}Fsync_State; ++ ++// Power save mode configured. ++typedef enum _RT_PS_MODE ++{ ++ eActive, // Active/Continuous access. ++ eMaxPs, // Max power save mode. ++ eFastPs // Fast power save mode. ++}RT_PS_MODE; ++ ++typedef enum _IPS_CALLBACK_FUNCION ++{ ++ IPS_CALLBACK_NONE = 0, ++ IPS_CALLBACK_MGNT_LINK_REQUEST = 1, ++ IPS_CALLBACK_JOIN_REQUEST = 2, ++}IPS_CALLBACK_FUNCION; ++ ++typedef enum _RT_JOIN_ACTION{ ++ RT_JOIN_INFRA = 1, ++ RT_JOIN_IBSS = 2, ++ RT_START_IBSS = 3, ++ RT_NO_ACTION = 4, ++}RT_JOIN_ACTION; ++ ++typedef struct _IbssParms{ ++ u16 atimWin; ++}IbssParms, *PIbssParms; ++#define MAX_NUM_RATES 264 // Max num of support rates element: 8, Max num of ext. support rate: 255. 061122, by rcnjko. ++ ++// RF state. ++typedef enum _RT_RF_POWER_STATE ++{ ++ eRfOn, ++ eRfSleep, ++ eRfOff ++}RT_RF_POWER_STATE; ++ ++typedef struct _RT_POWER_SAVE_CONTROL ++{ ++ ++ // ++ // Inactive Power Save(IPS) : Disable RF when disconnected ++ // ++ bool bInactivePs; ++ bool bIPSModeBackup; ++ bool bSwRfProcessing; ++ RT_RF_POWER_STATE eInactivePowerState; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ struct work_struct InactivePsWorkItem; ++#else ++ struct tq_struct InactivePsWorkItem; ++#endif ++ struct timer_list InactivePsTimer; ++ ++ // Return point for join action ++ IPS_CALLBACK_FUNCION ReturnPoint; ++ ++ // Recored Parameters for rescheduled JoinRequest ++ bool bTmpBssDesc; ++ RT_JOIN_ACTION tmpJoinAction; ++ struct ieee80211_network tmpBssDesc; ++ ++ // Recored Parameters for rescheduled MgntLinkRequest ++ bool bTmpScanOnly; ++ bool bTmpActiveScan; ++ bool bTmpFilterHiddenAP; ++ bool bTmpUpdateParms; ++ u8 tmpSsidBuf[33]; ++ OCTET_STRING tmpSsid2Scan; ++ bool bTmpSsid2Scan; ++ u8 tmpNetworkType; ++ u8 tmpChannelNumber; ++ u16 tmpBcnPeriod; ++ u8 tmpDtimPeriod; ++ u16 tmpmCap; ++ OCTET_STRING tmpSuppRateSet; ++ u8 tmpSuppRateBuf[MAX_NUM_RATES]; ++ bool bTmpSuppRate; ++ IbssParms tmpIbpm; ++ bool bTmpIbpm; ++ ++ // ++ // Leisre Poswer Save : Disable RF if connected but traffic is not busy ++ // ++ bool bLeisurePs; ++ ++}RT_POWER_SAVE_CONTROL,*PRT_POWER_SAVE_CONTROL; ++ ++typedef u32 RT_RF_CHANGE_SOURCE; ++#define RF_CHANGE_BY_SW BIT31 ++#define RF_CHANGE_BY_HW BIT30 ++#define RF_CHANGE_BY_PS BIT29 ++#define RF_CHANGE_BY_IPS BIT28 ++#define RF_CHANGE_BY_INIT 0 // Do not change the RFOff reason. Defined by Bruce, 2008-01-17. ++ ++#ifdef ENABLE_DOT11D ++typedef enum ++{ ++ COUNTRY_CODE_FCC = 0, ++ COUNTRY_CODE_IC = 1, ++ COUNTRY_CODE_ETSI = 2, ++ COUNTRY_CODE_SPAIN = 3, ++ COUNTRY_CODE_FRANCE = 4, ++ COUNTRY_CODE_MKK = 5, ++ COUNTRY_CODE_MKK1 = 6, ++ COUNTRY_CODE_ISRAEL = 7, ++ COUNTRY_CODE_TELEC, ++ COUNTRY_CODE_MIC, ++ COUNTRY_CODE_GLOBAL_DOMAIN ++}country_code_type_t; ++#endif ++ ++#define RT_MAX_LD_SLOT_NUM 10 ++typedef struct _RT_LINK_DETECT_T{ ++ ++ u32 NumRecvBcnInPeriod; ++ u32 NumRecvDataInPeriod; ++ ++ u32 RxBcnNum[RT_MAX_LD_SLOT_NUM]; // number of Rx beacon / CheckForHang_period to determine link status ++ u32 RxDataNum[RT_MAX_LD_SLOT_NUM]; // number of Rx data / CheckForHang_period to determine link status ++ u16 SlotNum; // number of CheckForHang period to determine link status ++ u16 SlotIndex; ++ ++ u32 NumTxOkInPeriod; ++ u32 NumRxOkInPeriod; ++ bool bBusyTraffic; ++}RT_LINK_DETECT_T, *PRT_LINK_DETECT_T; ++ ++ ++struct ieee80211_device { ++ struct net_device *dev; ++ struct ieee80211_security sec; ++ ++ //hw security related ++// u8 hwsec_support; //support? ++ u8 hwsec_active; //hw security active. ++ bool is_silent_reset; ++ bool is_roaming; ++ bool ieee_up; ++ //added by amy ++ bool bSupportRemoteWakeUp; ++ RT_PS_MODE dot11PowerSaveMode; // Power save mode configured. ++ bool actscanning; ++ bool beinretry; ++ RT_RF_POWER_STATE eRFPowerState; ++ RT_RF_CHANGE_SOURCE RfOffReason; ++ bool is_set_key; ++ //11n spec related I wonder if These info structure need to be moved out of ieee80211_device ++ ++ //11n HT below ++ PRT_HIGH_THROUGHPUT pHTInfo; ++ //struct timer_list SwBwTimer; ++// spinlock_t chnlop_spinlock; ++ spinlock_t bw_spinlock; ++ ++ spinlock_t reorder_spinlock; ++ // for HT operation rate set. we use this one for HT data rate to seperate different descriptors ++ //the way fill this is the same as in the IE ++ u8 Regdot11HTOperationalRateSet[16]; //use RATR format ++ u8 dot11HTOperationalRateSet[16]; //use RATR format ++ u8 RegHTSuppRateSet[16]; ++ u8 HTCurrentOperaRate; ++ u8 HTHighestOperaRate; ++ //wb added for rate operation mode to firmware ++ u8 bTxDisableRateFallBack; ++ u8 bTxUseDriverAssingedRate; ++ atomic_t atm_chnlop; ++ atomic_t atm_swbw; ++// u8 HTHighestOperaRate; ++// u8 HTCurrentOperaRate; ++ ++ // 802.11e and WMM Traffic Stream Info (TX) ++ struct list_head Tx_TS_Admit_List; ++ struct list_head Tx_TS_Pending_List; ++ struct list_head Tx_TS_Unused_List; ++ TX_TS_RECORD TxTsRecord[TOTAL_TS_NUM]; ++ // 802.11e and WMM Traffic Stream Info (RX) ++ struct list_head Rx_TS_Admit_List; ++ struct list_head Rx_TS_Pending_List; ++ struct list_head Rx_TS_Unused_List; ++ RX_TS_RECORD RxTsRecord[TOTAL_TS_NUM]; ++//#ifdef TO_DO_LIST ++ RX_REORDER_ENTRY RxReorderEntry[128]; ++ struct list_head RxReorder_Unused_List; ++//#endif ++ // Qos related. Added by Annie, 2005-11-01. ++// PSTA_QOS pStaQos; ++ u8 ForcedPriority; // Force per-packet priority 1~7. (default: 0, not to force it.) ++ ++ ++ /* Bookkeeping structures */ ++ struct net_device_stats stats; ++ struct ieee80211_stats ieee_stats; ++ struct ieee80211_softmac_stats softmac_stats; ++ ++ /* Probe / Beacon management */ ++ struct list_head network_free_list; ++ struct list_head network_list; ++ struct ieee80211_network *networks; ++ int scans; ++ int scan_age; ++ ++ int iw_mode; /* operating mode (IW_MODE_*) */ ++ struct iw_spy_data spy_data; ++ ++ spinlock_t lock; ++ spinlock_t wpax_suitlist_lock; ++ ++ int tx_headroom; /* Set to size of any additional room needed at front ++ * of allocated Tx SKBs */ ++ u32 config; ++ ++ /* WEP and other encryption related settings at the device level */ ++ int open_wep; /* Set to 1 to allow unencrypted frames */ ++ int auth_mode; ++ int reset_on_keychange; /* Set to 1 if the HW needs to be reset on ++ * WEP key changes */ ++ ++ /* If the host performs {en,de}cryption, then set to 1 */ ++ int host_encrypt; ++ int host_encrypt_msdu; ++ int host_decrypt; ++ /* host performs multicast decryption */ ++ int host_mc_decrypt; ++ ++ /* host should strip IV and ICV from protected frames */ ++ /* meaningful only when hardware decryption is being used */ ++ int host_strip_iv_icv; ++ ++ int host_open_frag; ++ int host_build_iv; ++ int ieee802_1x; /* is IEEE 802.1X used */ ++ ++ /* WPA data */ ++ bool bHalfWirelessN24GMode; ++ int wpa_enabled; ++ int drop_unencrypted; ++ int tkip_countermeasures; ++ int privacy_invoked; ++ size_t wpa_ie_len; ++ u8 *wpa_ie; ++ u8 ap_mac_addr[6]; ++ u16 pairwise_key_type; ++ u16 group_key_type; ++ struct list_head crypt_deinit_list; ++ struct ieee80211_crypt_data *crypt[WEP_KEYS]; ++ int tx_keyidx; /* default TX key index (crypt[tx_keyidx]) */ ++ struct timer_list crypt_deinit_timer; ++ int crypt_quiesced; ++ ++ int bcrx_sta_key; /* use individual keys to override default keys even ++ * with RX of broad/multicast frames */ ++ ++ /* Fragmentation structures */ ++ // each streaming contain a entry ++ struct ieee80211_frag_entry frag_cache[17][IEEE80211_FRAG_CACHE_LEN]; ++ unsigned int frag_next_idx[17]; ++ u16 fts; /* Fragmentation Threshold */ ++#define DEFAULT_RTS_THRESHOLD 2346U ++#define MIN_RTS_THRESHOLD 1 ++#define MAX_RTS_THRESHOLD 2346U ++ u16 rts; /* RTS threshold */ ++ ++ /* Association info */ ++ u8 bssid[ETH_ALEN]; ++ ++ /* This stores infos for the current network. ++ * Either the network we are associated in INFRASTRUCTURE ++ * or the network that we are creating in MASTER mode. ++ * ad-hoc is a mixture ;-). ++ * Note that in infrastructure mode, even when not associated, ++ * fields bssid and essid may be valid (if wpa_set and essid_set ++ * are true) as thy carry the value set by the user via iwconfig ++ */ ++ struct ieee80211_network current_network; ++ ++ enum ieee80211_state state; ++ ++ int short_slot; ++ int reg_mode; ++ int mode; /* A, B, G */ ++ int modulation; /* CCK, OFDM */ ++ int freq_band; /* 2.4Ghz, 5.2Ghz, Mixed */ ++ int abg_true; /* ABG flag */ ++ ++ /* used for forcing the ibss workqueue to terminate ++ * without wait for the syncro scan to terminate ++ */ ++ short sync_scan_hurryup; ++ ++ int perfect_rssi; ++ int worst_rssi; ++ ++ u16 prev_seq_ctl; /* used to drop duplicate frames */ ++ ++ /* map of allowed channels. 0 is dummy */ ++ // FIXME: remeber to default to a basic channel plan depending of the PHY type ++#ifdef ENABLE_DOT11D ++ void* pDot11dInfo; ++ bool bGlobalDomain; ++#else ++ int channel_map[MAX_CHANNEL_NUMBER+1]; ++#endif ++ int rate; /* current rate */ ++ int basic_rate; ++ //FIXME: pleace callback, see if redundant with softmac_features ++ short active_scan; ++ ++ /* this contains flags for selectively enable softmac support */ ++ u16 softmac_features; ++ ++ /* if the sequence control field is not filled by HW */ ++ u16 seq_ctrl[5]; ++ ++ /* association procedure transaction sequence number */ ++ u16 associate_seq; ++ ++ /* AID for RTXed association responses */ ++ u16 assoc_id; ++ ++ /* power save mode related*/ ++ u8 ack_tx_to_ieee; ++ short ps; ++ short sta_sleep; ++ int ps_timeout; ++ int ps_period; ++ struct tasklet_struct ps_task; ++ u32 ps_th; ++ u32 ps_tl; ++ ++ short raw_tx; ++ /* used if IEEE_SOFTMAC_TX_QUEUE is set */ ++ short queue_stop; ++ short scanning; ++ short proto_started; ++ ++ struct semaphore wx_sem; ++ struct semaphore scan_sem; ++ ++ spinlock_t mgmt_tx_lock; ++ spinlock_t beacon_lock; ++ ++ short beacon_txing; ++ ++ short wap_set; ++ short ssid_set; ++ ++ u8 wpax_type_set; //{added by David, 2006.9.28} ++ u32 wpax_type_notify; //{added by David, 2006.9.26} ++ ++ /* QoS related flag */ ++ char init_wmmparam_flag; ++ /* set on initialization */ ++ u8 qos_support; ++ ++ /* for discarding duplicated packets in IBSS */ ++ struct list_head ibss_mac_hash[IEEE_IBSS_MAC_HASH_SIZE]; ++ ++ /* for discarding duplicated packets in BSS */ ++ u16 last_rxseq_num[17]; /* rx seq previous per-tid */ ++ u16 last_rxfrag_num[17];/* tx frag previous per-tid */ ++ unsigned long last_packet_time[17]; ++ ++ /* for PS mode */ ++ unsigned long last_rx_ps_time; ++ ++ /* used if IEEE_SOFTMAC_SINGLE_QUEUE is set */ ++ struct sk_buff *mgmt_queue_ring[MGMT_QUEUE_NUM]; ++ int mgmt_queue_head; ++ int mgmt_queue_tail; ++//{ added for rtl819x ++#define IEEE80211_QUEUE_LIMIT 128 ++ u8 AsocRetryCount; ++ unsigned int hw_header; ++ struct sk_buff_head skb_waitQ[MAX_QUEUE_SIZE]; ++ struct sk_buff_head skb_aggQ[MAX_QUEUE_SIZE]; ++ struct sk_buff_head skb_drv_aggQ[MAX_QUEUE_SIZE]; ++ u32 sta_edca_param[4]; ++ bool aggregation; ++ // Enable/Disable Rx immediate BA capability. ++ bool enable_rx_imm_BA; ++ bool bibsscoordinator; ++ ++ //+by amy for DM ,080515 ++ //Dynamic Tx power for near/far range enable/Disable , by amy , 2008-05-15 ++ bool bdynamic_txpower_enable; ++ ++ bool bCTSToSelfEnable; ++ u8 CTSToSelfTH; ++ ++ u32 fsync_time_interval; ++ u32 fsync_rate_bitmap; ++ u8 fsync_rssi_threshold; ++ bool bfsync_enable; ++ ++ u8 fsync_multiple_timeinterval; // FsyncMultipleTimeInterval * FsyncTimeInterval ++ u32 fsync_firstdiff_ratethreshold; // low threshold ++ u32 fsync_seconddiff_ratethreshold; // decrease threshold ++ Fsync_State fsync_state; ++ bool bis_any_nonbepkts; ++ //20Mhz 40Mhz AutoSwitch Threshold ++ bandwidth_autoswitch bandwidth_auto_switch; ++ //for txpower tracking ++ bool FwRWRF; ++ ++ //added by amy for AP roaming ++ RT_LINK_DETECT_T LinkDetectInfo; ++ //added by amy for ps ++ RT_POWER_SAVE_CONTROL PowerSaveControl; ++//} ++ /* used if IEEE_SOFTMAC_TX_QUEUE is set */ ++ struct tx_pending_t tx_pending; ++ ++ /* used if IEEE_SOFTMAC_ASSOCIATE is set */ ++ struct timer_list associate_timer; ++ ++ /* used if IEEE_SOFTMAC_BEACONS is set */ ++ struct timer_list beacon_timer; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ struct work_struct associate_complete_wq; ++ struct work_struct associate_procedure_wq; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ struct delayed_work softmac_scan_wq; ++ struct delayed_work associate_retry_wq; ++ struct delayed_work start_ibss_wq; ++ struct delayed_work hw_wakeup_wq; ++ struct delayed_work hw_sleep_wq; ++#else ++ struct work_struct softmac_scan_wq; ++ struct work_struct associate_retry_wq; ++ struct work_struct start_ibss_wq; ++ struct work_struct hw_wakeup_wq; ++ struct work_struct hw_sleep_wq; ++#endif ++ struct work_struct wx_sync_scan_wq; ++ struct workqueue_struct *wq; ++#else ++ /* used for periodly scan */ ++ struct timer_list scan_timer; ++ ++ struct tq_struct associate_complete_wq; ++ struct tq_struct associate_retry_wq; ++ struct tq_struct start_ibss_wq; ++ struct tq_struct associate_procedure_wq; ++ struct tq_struct softmac_scan_wq; ++ struct tq_struct wx_sync_scan_wq; ++ ++#endif ++ // Qos related. Added by Annie, 2005-11-01. ++ //STA_QOS StaQos; ++ ++ //u32 STA_EDCA_PARAM[4]; ++ //CHANNEL_ACCESS_SETTING ChannelAccessSetting; ++ ++ ++ /* Callback functions */ ++ void (*set_security)(struct net_device *dev, ++ struct ieee80211_security *sec); ++ ++ /* Used to TX data frame by using txb structs. ++ * this is not used if in the softmac_features ++ * is set the flag IEEE_SOFTMAC_TX_QUEUE ++ */ ++ int (*hard_start_xmit)(struct ieee80211_txb *txb, ++ struct net_device *dev); ++ ++ int (*reset_port)(struct net_device *dev); ++ int (*is_queue_full) (struct net_device * dev, int pri); ++ ++ int (*handle_management) (struct net_device * dev, ++ struct ieee80211_network * network, u16 type); ++ int (*is_qos_active) (struct net_device *dev, struct sk_buff *skb); ++ ++ /* Softmac-generated frames (mamagement) are TXed via this ++ * callback if the flag IEEE_SOFTMAC_SINGLE_QUEUE is ++ * not set. As some cards may have different HW queues that ++ * one might want to use for data and management frames ++ * the option to have two callbacks might be useful. ++ * This fucntion can't sleep. ++ */ ++ int (*softmac_hard_start_xmit)(struct sk_buff *skb, ++ struct net_device *dev); ++ ++ /* used instead of hard_start_xmit (not softmac_hard_start_xmit) ++ * if the IEEE_SOFTMAC_TX_QUEUE feature is used to TX data ++ * frames. I the option IEEE_SOFTMAC_SINGLE_QUEUE is also set ++ * then also management frames are sent via this callback. ++ * This function can't sleep. ++ */ ++ void (*softmac_data_hard_start_xmit)(struct sk_buff *skb, ++ struct net_device *dev,int rate); ++ ++ /* stops the HW queue for DATA frames. Useful to avoid ++ * waste time to TX data frame when we are reassociating ++ * This function can sleep. ++ */ ++ void (*data_hard_stop)(struct net_device *dev); ++ ++ /* OK this is complementar to data_poll_hard_stop */ ++ void (*data_hard_resume)(struct net_device *dev); ++ ++ /* ask to the driver to retune the radio . ++ * This function can sleep. the driver should ensure ++ * the radio has been swithced before return. ++ */ ++ void (*set_chan)(struct net_device *dev,short ch); ++ ++ /* These are not used if the ieee stack takes care of ++ * scanning (IEEE_SOFTMAC_SCAN feature set). ++ * In this case only the set_chan is used. ++ * ++ * The syncro version is similar to the start_scan but ++ * does not return until all channels has been scanned. ++ * this is called in user context and should sleep, ++ * it is called in a work_queue when swithcing to ad-hoc mode ++ * or in behalf of iwlist scan when the card is associated ++ * and root user ask for a scan. ++ * the fucntion stop_scan should stop both the syncro and ++ * background scanning and can sleep. ++ * The fucntion start_scan should initiate the background ++ * scanning and can't sleep. ++ */ ++ void (*scan_syncro)(struct net_device *dev); ++ void (*start_scan)(struct net_device *dev); ++ void (*stop_scan)(struct net_device *dev); ++ ++ /* indicate the driver that the link state is changed ++ * for example it may indicate the card is associated now. ++ * Driver might be interested in this to apply RX filter ++ * rules or simply light the LINK led ++ */ ++ void (*link_change)(struct net_device *dev); ++ ++ /* these two function indicates to the HW when to start ++ * and stop to send beacons. This is used when the ++ * IEEE_SOFTMAC_BEACONS is not set. For now the ++ * stop_send_bacons is NOT guaranteed to be called only ++ * after start_send_beacons. ++ */ ++ void (*start_send_beacons) (struct net_device *dev,u16 tx_rate); ++ void (*stop_send_beacons) (struct net_device *dev); ++ ++ /* power save mode related */ ++ void (*sta_wake_up) (struct net_device *dev); ++// void (*ps_request_tx_ack) (struct net_device *dev); ++ void (*enter_sleep_state) (struct net_device *dev, u32 th, u32 tl); ++ short (*ps_is_queue_empty) (struct net_device *dev); ++#if 0 ++ /* Typical STA methods */ ++ int (*handle_auth) (struct net_device * dev, ++ struct ieee80211_auth * auth); ++ int (*handle_deauth) (struct net_device * dev, ++ struct ieee80211_deauth * auth); ++ int (*handle_action) (struct net_device * dev, ++ struct ieee80211_action * action, ++ struct ieee80211_rx_stats * stats); ++ int (*handle_disassoc) (struct net_device * dev, ++ struct ieee80211_disassoc * assoc); ++#endif ++ int (*handle_beacon) (struct net_device * dev, struct ieee80211_beacon * beacon, struct ieee80211_network * network); ++#if 0 ++ int (*handle_probe_response) (struct net_device * dev, ++ struct ieee80211_probe_response * resp, ++ struct ieee80211_network * network); ++ int (*handle_probe_request) (struct net_device * dev, ++ struct ieee80211_probe_request * req, ++ struct ieee80211_rx_stats * stats); ++#endif ++ int (*handle_assoc_response) (struct net_device * dev, struct ieee80211_assoc_response_frame * resp, struct ieee80211_network * network); ++ ++#if 0 ++ /* Typical AP methods */ ++ int (*handle_assoc_request) (struct net_device * dev); ++ int (*handle_reassoc_request) (struct net_device * dev, ++ struct ieee80211_reassoc_request * req); ++#endif ++ ++ /* check whether Tx hw resouce available */ ++ short (*check_nic_enough_desc)(struct net_device *dev, int queue_index); ++ //added by wb for HT related ++// void (*SwChnlByTimerHandler)(struct net_device *dev, int channel); ++ void (*SetBWModeHandler)(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); ++// void (*UpdateHalRATRTableHandler)(struct net_device* dev, u8* pMcsRate); ++ bool (*GetNmodeSupportBySecCfg)(struct net_device* dev); ++ void (*SetWirelessMode)(struct net_device* dev, u8 wireless_mode); ++ bool (*GetHalfNmodeSupportByAPsHandler)(struct net_device* dev); ++ void (*InitialGainHandler)(struct net_device *dev, u8 Operation); ++ ++ /* This must be the last item so that it points to the data ++ * allocated beyond this structure by alloc_ieee80211 */ ++ u8 priv[0]; ++}; ++ ++#define IEEE_A (1<<0) ++#define IEEE_B (1<<1) ++#define IEEE_G (1<<2) ++#define IEEE_N_24G (1<<4) ++#define IEEE_N_5G (1<<5) ++#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G) ++ ++/* Generate a 802.11 header */ ++ ++/* Uses the channel change callback directly ++ * instead of [start/stop] scan callbacks ++ */ ++#define IEEE_SOFTMAC_SCAN (1<<2) ++ ++/* Perform authentication and association handshake */ ++#define IEEE_SOFTMAC_ASSOCIATE (1<<3) ++ ++/* Generate probe requests */ ++#define IEEE_SOFTMAC_PROBERQ (1<<4) ++ ++/* Generate respones to probe requests */ ++#define IEEE_SOFTMAC_PROBERS (1<<5) ++ ++/* The ieee802.11 stack will manages the netif queue ++ * wake/stop for the driver, taking care of 802.11 ++ * fragmentation. See softmac.c for details. */ ++#define IEEE_SOFTMAC_TX_QUEUE (1<<7) ++ ++/* Uses only the softmac_data_hard_start_xmit ++ * even for TX management frames. ++ */ ++#define IEEE_SOFTMAC_SINGLE_QUEUE (1<<8) ++ ++/* Generate beacons. The stack will enqueue beacons ++ * to the card ++ */ ++#define IEEE_SOFTMAC_BEACONS (1<<6) ++ ++static inline void *ieee80211_priv(struct net_device *dev) ++{ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ return ((struct ieee80211_device *)netdev_priv(dev))->priv; ++#else ++ return ((struct ieee80211_device *)dev->priv)->priv; ++#endif ++} ++ ++extern inline int ieee80211_is_empty_essid(const char *essid, int essid_len) ++{ ++ /* Single white space is for Linksys APs */ ++ if (essid_len == 1 && essid[0] == ' ') ++ return 1; ++ ++ /* Otherwise, if the entire essid is 0, we assume it is hidden */ ++ while (essid_len) { ++ essid_len--; ++ if (essid[essid_len] != '\0') ++ return 0; ++ } ++ ++ return 1; ++} ++ ++extern inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee, int mode) ++{ ++ /* ++ * It is possible for both access points and our device to support ++ * combinations of modes, so as long as there is one valid combination ++ * of ap/device supported modes, then return success ++ * ++ */ ++ if ((mode & IEEE_A) && ++ (ieee->modulation & IEEE80211_OFDM_MODULATION) && ++ (ieee->freq_band & IEEE80211_52GHZ_BAND)) ++ return 1; ++ ++ if ((mode & IEEE_G) && ++ (ieee->modulation & IEEE80211_OFDM_MODULATION) && ++ (ieee->freq_band & IEEE80211_24GHZ_BAND)) ++ return 1; ++ ++ if ((mode & IEEE_B) && ++ (ieee->modulation & IEEE80211_CCK_MODULATION) && ++ (ieee->freq_band & IEEE80211_24GHZ_BAND)) ++ return 1; ++ ++ return 0; ++} ++ ++extern inline int ieee80211_get_hdrlen(u16 fc) ++{ ++ int hdrlen = IEEE80211_3ADDR_LEN; ++ ++ switch (WLAN_FC_GET_TYPE(fc)) { ++ case IEEE80211_FTYPE_DATA: ++ if ((fc & IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS)) ++ hdrlen = IEEE80211_4ADDR_LEN; /* Addr4 */ ++ if(IEEE80211_QOS_HAS_SEQ(fc)) ++ hdrlen += 2; /* QOS ctrl*/ ++ break; ++ case IEEE80211_FTYPE_CTL: ++ switch (WLAN_FC_GET_STYPE(fc)) { ++ case IEEE80211_STYPE_CTS: ++ case IEEE80211_STYPE_ACK: ++ hdrlen = IEEE80211_1ADDR_LEN; ++ break; ++ default: ++ hdrlen = IEEE80211_2ADDR_LEN; ++ break; ++ } ++ break; ++ } ++ ++ return hdrlen; ++} ++ ++static inline u8 *ieee80211_get_payload(struct ieee80211_hdr *hdr) ++{ ++ switch (ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl))) { ++ case IEEE80211_1ADDR_LEN: ++ return ((struct ieee80211_hdr_1addr *)hdr)->payload; ++ case IEEE80211_2ADDR_LEN: ++ return ((struct ieee80211_hdr_2addr *)hdr)->payload; ++ case IEEE80211_3ADDR_LEN: ++ return ((struct ieee80211_hdr_3addr *)hdr)->payload; ++ case IEEE80211_4ADDR_LEN: ++ return ((struct ieee80211_hdr_4addr *)hdr)->payload; ++ } ++ return NULL; ++} ++ ++static inline int ieee80211_is_ofdm_rate(u8 rate) ++{ ++ switch (rate & ~IEEE80211_BASIC_RATE_MASK) { ++ case IEEE80211_OFDM_RATE_6MB: ++ case IEEE80211_OFDM_RATE_9MB: ++ case IEEE80211_OFDM_RATE_12MB: ++ case IEEE80211_OFDM_RATE_18MB: ++ case IEEE80211_OFDM_RATE_24MB: ++ case IEEE80211_OFDM_RATE_36MB: ++ case IEEE80211_OFDM_RATE_48MB: ++ case IEEE80211_OFDM_RATE_54MB: ++ return 1; ++ } ++ return 0; ++} ++ ++static inline int ieee80211_is_cck_rate(u8 rate) ++{ ++ switch (rate & ~IEEE80211_BASIC_RATE_MASK) { ++ case IEEE80211_CCK_RATE_1MB: ++ case IEEE80211_CCK_RATE_2MB: ++ case IEEE80211_CCK_RATE_5MB: ++ case IEEE80211_CCK_RATE_11MB: ++ return 1; ++ } ++ return 0; ++} ++ ++ ++/* ieee80211.c */ ++extern void free_ieee80211(struct net_device *dev); ++extern struct net_device *alloc_ieee80211(int sizeof_priv); ++ ++extern int ieee80211_set_encryption(struct ieee80211_device *ieee); ++ ++/* ieee80211_tx.c */ ++ ++extern int ieee80211_encrypt_fragment( ++ struct ieee80211_device *ieee, ++ struct sk_buff *frag, ++ int hdr_len); ++ ++extern int ieee80211_xmit(struct sk_buff *skb, ++ struct net_device *dev); ++extern void ieee80211_txb_free(struct ieee80211_txb *); ++ ++ ++/* ieee80211_rx.c */ ++extern int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb, ++ struct ieee80211_rx_stats *rx_stats); ++extern void ieee80211_rx_mgt(struct ieee80211_device *ieee, ++ struct ieee80211_hdr_4addr *header, ++ struct ieee80211_rx_stats *stats); ++ ++/* ieee80211_wx.c */ ++extern int ieee80211_wx_get_scan(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *key); ++extern int ieee80211_wx_set_encode(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *key); ++extern int ieee80211_wx_get_encode(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *key); ++#if WIRELESS_EXT >= 18 ++extern int ieee80211_wx_get_encode_ext(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data* wrqu, char *extra); ++extern int ieee80211_wx_set_encode_ext(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data* wrqu, char *extra); ++extern int ieee80211_wx_set_auth(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ struct iw_param *data, char *extra); ++extern int ieee80211_wx_set_mlme(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++#endif ++extern int ieee80211_wx_set_gen_ie(struct ieee80211_device *ieee, u8 *ie, size_t len); ++ ++/* ieee80211_softmac.c */ ++extern short ieee80211_is_54g(struct ieee80211_network net); ++extern short ieee80211_is_shortslot(struct ieee80211_network net); ++extern int ieee80211_rx_frame_softmac(struct ieee80211_device *ieee, struct sk_buff *skb, ++ struct ieee80211_rx_stats *rx_stats, u16 type, ++ u16 stype); ++extern void ieee80211_softmac_new_net(struct ieee80211_device *ieee, struct ieee80211_network *net); ++ ++void SendDisassociation(struct ieee80211_device *ieee, u8* asSta, u8 asRsn); ++extern void ieee80211_softmac_xmit(struct ieee80211_txb *txb, struct ieee80211_device *ieee); ++ ++extern void ieee80211_stop_send_beacons(struct ieee80211_device *ieee); ++extern void notify_wx_assoc_event(struct ieee80211_device *ieee); ++extern void ieee80211_softmac_check_all_nets(struct ieee80211_device *ieee); ++extern void ieee80211_start_bss(struct ieee80211_device *ieee); ++extern void ieee80211_start_master_bss(struct ieee80211_device *ieee); ++extern void ieee80211_start_ibss(struct ieee80211_device *ieee); ++extern void ieee80211_softmac_init(struct ieee80211_device *ieee); ++extern void ieee80211_softmac_free(struct ieee80211_device *ieee); ++extern void ieee80211_associate_abort(struct ieee80211_device *ieee); ++extern void ieee80211_disassociate(struct ieee80211_device *ieee); ++extern void ieee80211_stop_scan(struct ieee80211_device *ieee); ++extern void ieee80211_start_scan_syncro(struct ieee80211_device *ieee); ++extern void ieee80211_check_all_nets(struct ieee80211_device *ieee); ++extern void ieee80211_start_protocol(struct ieee80211_device *ieee); ++extern void ieee80211_stop_protocol(struct ieee80211_device *ieee); ++extern void ieee80211_softmac_start_protocol(struct ieee80211_device *ieee); ++extern void ieee80211_softmac_stop_protocol(struct ieee80211_device *ieee); ++extern void ieee80211_reset_queue(struct ieee80211_device *ieee); ++extern void ieee80211_wake_queue(struct ieee80211_device *ieee); ++extern void ieee80211_stop_queue(struct ieee80211_device *ieee); ++extern struct sk_buff *ieee80211_get_beacon(struct ieee80211_device *ieee); ++extern void ieee80211_start_send_beacons(struct ieee80211_device *ieee); ++extern void ieee80211_stop_send_beacons(struct ieee80211_device *ieee); ++extern int ieee80211_wpa_supplicant_ioctl(struct ieee80211_device *ieee, struct iw_point *p); ++extern void notify_wx_assoc_event(struct ieee80211_device *ieee); ++extern void ieee80211_ps_tx_ack(struct ieee80211_device *ieee, short success); ++ ++extern void softmac_mgmt_xmit(struct sk_buff *skb, struct ieee80211_device *ieee); ++ ++/* ieee80211_crypt_ccmp&tkip&wep.c */ ++extern void ieee80211_tkip_null(void); ++extern void ieee80211_wep_null(void); ++extern void ieee80211_ccmp_null(void); ++ ++/* ieee80211_softmac_wx.c */ ++ ++extern int ieee80211_wx_get_wap(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *ext); ++ ++extern int ieee80211_wx_set_wap(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *awrq, ++ char *extra); ++ ++extern int ieee80211_wx_get_essid(struct ieee80211_device *ieee, struct iw_request_info *a,union iwreq_data *wrqu,char *b); ++ ++extern int ieee80211_wx_set_rate(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_get_rate(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_set_mode(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b); ++ ++extern int ieee80211_wx_set_scan(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b); ++ ++extern int ieee80211_wx_set_essid(struct ieee80211_device *ieee, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_get_mode(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b); ++ ++extern int ieee80211_wx_set_freq(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b); ++ ++extern int ieee80211_wx_get_freq(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b); ++ ++//extern void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++extern void ieee80211_wx_sync_scan_wq(struct work_struct *work); ++#else ++ extern void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee); ++#endif ++ ++ ++extern int ieee80211_wx_set_rawtx(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_get_name(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_set_power(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_get_power(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_set_rts(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_get_rts(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++//HT ++#define MAX_RECEIVE_BUFFER_SIZE 9100 // ++extern void HTDebugHTCapability(u8* CapIE, u8* TitleString ); ++extern void HTDebugHTInfo(u8* InfoIE, u8* TitleString); ++ ++void HTSetConnectBwMode(struct ieee80211_device* ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); ++extern void HTUpdateDefaultSetting(struct ieee80211_device* ieee); ++extern void HTConstructCapabilityElement(struct ieee80211_device* ieee, u8* posHTCap, u8* len, u8 isEncrypt); ++extern void HTConstructInfoElement(struct ieee80211_device* ieee, u8* posHTInfo, u8* len, u8 isEncrypt); ++extern void HTConstructRT2RTAggElement(struct ieee80211_device* ieee, u8* posRT2RTAgg, u8* len); ++extern void HTOnAssocRsp(struct ieee80211_device *ieee); ++extern void HTInitializeHTInfo(struct ieee80211_device* ieee); ++extern void HTInitializeBssDesc(PBSS_HT pBssHT); ++extern void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork); ++extern void HTUpdateSelfAndPeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork); ++extern u8 HTGetHighestMCSRate(struct ieee80211_device* ieee, u8* pMCSRateSet, u8* pMCSFilter); ++extern u8 MCS_FILTER_ALL[]; ++extern u16 MCS_DATA_RATE[2][2][77] ; ++extern u8 HTCCheck(struct ieee80211_device* ieee, u8* pFrame); ++//extern void HTSetConnectBwModeCallback(unsigned long data); ++extern void HTResetIOTSetting(PRT_HIGH_THROUGHPUT pHTInfo); ++extern bool IsHTHalfNmodeAPs(struct ieee80211_device* ieee); ++extern u16 HTHalfMcsToDataRate(struct ieee80211_device* ieee, u8 nMcsRate); ++extern u16 HTMcsToDataRate( struct ieee80211_device* ieee, u8 nMcsRate); ++extern u16 TxCountToDataRate( struct ieee80211_device* ieee, u8 nDataRate); ++//function in BAPROC.c ++extern int ieee80211_rx_ADDBAReq( struct ieee80211_device* ieee, struct sk_buff *skb); ++extern int ieee80211_rx_ADDBARsp( struct ieee80211_device* ieee, struct sk_buff *skb); ++extern int ieee80211_rx_DELBA(struct ieee80211_device* ieee,struct sk_buff *skb); ++extern void TsInitAddBA( struct ieee80211_device* ieee, PTX_TS_RECORD pTS, u8 Policy, u8 bOverwritePending); ++extern void TsInitDelBA( struct ieee80211_device* ieee, PTS_COMMON_INFO pTsCommonInfo, TR_SELECT TxRxSelect); ++extern void BaSetupTimeOut(unsigned long data); ++extern void TxBaInactTimeout(unsigned long data); ++extern void RxBaInactTimeout(unsigned long data); ++extern void ResetBaEntry( PBA_RECORD pBA); ++//function in TS.c ++extern bool GetTs( ++ struct ieee80211_device* ieee, ++ PTS_COMMON_INFO *ppTS, ++ u8* Addr, ++ u8 TID, ++ TR_SELECT TxRxSelect, //Rx:1, Tx:0 ++ bool bAddNewTs ++ ); ++extern void TSInitialize(struct ieee80211_device *ieee); ++extern void TsStartAddBaProcess(struct ieee80211_device* ieee, PTX_TS_RECORD pTxTS); ++extern void RemovePeerTS(struct ieee80211_device* ieee, u8* Addr); ++extern void RemoveAllTS(struct ieee80211_device* ieee); ++void ieee80211_softmac_scan_syncro(struct ieee80211_device *ieee); ++ ++extern const long ieee80211_wlan_frequencies[]; ++ ++extern inline void ieee80211_increment_scans(struct ieee80211_device *ieee) ++{ ++ ieee->scans++; ++} ++ ++extern inline int ieee80211_get_scans(struct ieee80211_device *ieee) ++{ ++ return ieee->scans; ++} ++ ++static inline const char *escape_essid(const char *essid, u8 essid_len) { ++ static char escaped[IW_ESSID_MAX_SIZE * 2 + 1]; ++ const char *s = essid; ++ char *d = escaped; ++ ++ if (ieee80211_is_empty_essid(essid, essid_len)) { ++ memcpy(escaped, "", sizeof("")); ++ return escaped; ++ } ++ ++ essid_len = min(essid_len, (u8)IW_ESSID_MAX_SIZE); ++ while (essid_len--) { ++ if (*s == '\0') { ++ *d++ = '\\'; ++ *d++ = '0'; ++ s++; ++ } else { ++ *d++ = *s++; ++ } ++ } ++ *d = '\0'; ++ return escaped; ++} ++ ++/* For the function is more related to hardware setting, it's better to use the ++ * ieee handler to refer to it. ++ */ ++extern short check_nic_enough_desc(struct net_device *dev, int queue_index); ++extern int ieee80211_data_xmit(struct sk_buff *skb, struct net_device *dev); ++extern int ieee80211_parse_info_param(struct ieee80211_device *ieee, ++ struct ieee80211_info_element *info_element, ++ u16 length, ++ struct ieee80211_network *network, ++ struct ieee80211_rx_stats *stats); ++ ++void ieee80211_indicate_packets(struct ieee80211_device *ieee, struct ieee80211_rxb** prxbIndicateArray,u8 index); ++#define RT_ASOC_RETRY_LIMIT 5 ++#endif /* IEEE80211_H */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_module.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_module.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_module.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,430 @@ ++/******************************************************************************* ++ ++ Copyright(c) 2004 Intel Corporation. All rights reserved. ++ ++ Portions of this file are based on the WEP enablement code provided by the ++ Host AP project hostap-drivers v0.1.3 ++ Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen ++ ++ Copyright (c) 2002-2003, Jouni Malinen ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms of version 2 of the GNU General Public License as ++ published by the Free Software Foundation. ++ ++ This program is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., 59 ++ Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ ++ The full GNU General Public License is included in this distribution in the ++ file called LICENSE. ++ ++ Contact Information: ++ James P. Ketrenos ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ieee80211.h" ++ ++MODULE_DESCRIPTION("802.11 data/management/control stack"); ++MODULE_AUTHOR("Copyright (C) 2004 Intel Corporation "); ++MODULE_LICENSE("GPL"); ++ ++#define DRV_NAME "ieee80211" ++ ++static inline int ieee80211_networks_allocate(struct ieee80211_device *ieee) ++{ ++ if (ieee->networks) ++ return 0; ++ ++ ieee->networks = kmalloc( ++ MAX_NETWORK_COUNT * sizeof(struct ieee80211_network), ++ GFP_KERNEL); ++ if (!ieee->networks) { ++ printk(KERN_WARNING "%s: Out of memory allocating beacons\n", ++ ieee->dev->name); ++ return -ENOMEM; ++ } ++ ++ memset(ieee->networks, 0, ++ MAX_NETWORK_COUNT * sizeof(struct ieee80211_network)); ++ ++ return 0; ++} ++ ++static inline void ieee80211_networks_free(struct ieee80211_device *ieee) ++{ ++ if (!ieee->networks) ++ return; ++ kfree(ieee->networks); ++ ieee->networks = NULL; ++} ++ ++static inline void ieee80211_networks_initialize(struct ieee80211_device *ieee) ++{ ++ int i; ++ ++ INIT_LIST_HEAD(&ieee->network_free_list); ++ INIT_LIST_HEAD(&ieee->network_list); ++ for (i = 0; i < MAX_NETWORK_COUNT; i++) ++ list_add_tail(&ieee->networks[i].list, &ieee->network_free_list); ++} ++ ++ ++struct net_device *alloc_ieee80211(int sizeof_priv) ++{ ++ struct ieee80211_device *ieee; ++ struct net_device *dev; ++ int i,err; ++ ++ IEEE80211_DEBUG_INFO("Initializing...\n"); ++ ++ dev = alloc_etherdev(sizeof(struct ieee80211_device) + sizeof_priv); ++ if (!dev) { ++ IEEE80211_ERROR("Unable to network device.\n"); ++ goto failed; ++ } ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)) ++ ieee = netdev_priv(dev); ++#else ++ ieee = (struct ieee80211_device *)dev->priv; ++#endif ++ dev->hard_start_xmit = ieee80211_xmit; ++ ++ memset(ieee, 0, sizeof(struct ieee80211_device)+sizeof_priv); ++ ieee->dev = dev; ++ ++ err = ieee80211_networks_allocate(ieee); ++ if (err) { ++ IEEE80211_ERROR("Unable to allocate beacon storage: %d\n", ++ err); ++ goto failed; ++ } ++ ieee80211_networks_initialize(ieee); ++ ++ ++ /* Default fragmentation threshold is maximum payload size */ ++ ieee->fts = DEFAULT_FTS; ++ ieee->scan_age = DEFAULT_MAX_SCAN_AGE; ++ ieee->open_wep = 1; ++ ++ /* Default to enabling full open WEP with host based encrypt/decrypt */ ++ ieee->host_encrypt = 1; ++ ieee->host_decrypt = 1; ++ ieee->ieee802_1x = 1; /* Default to supporting 802.1x */ ++ ++ INIT_LIST_HEAD(&ieee->crypt_deinit_list); ++ init_timer(&ieee->crypt_deinit_timer); ++ ieee->crypt_deinit_timer.data = (unsigned long)ieee; ++ ieee->crypt_deinit_timer.function = ieee80211_crypt_deinit_handler; ++ ++ spin_lock_init(&ieee->lock); ++ spin_lock_init(&ieee->wpax_suitlist_lock); ++ spin_lock_init(&ieee->bw_spinlock); ++ spin_lock_init(&ieee->reorder_spinlock); ++ //added by WB ++ atomic_set(&(ieee->atm_chnlop), 0); ++ atomic_set(&(ieee->atm_swbw), 0); ++ ++ ieee->wpax_type_set = 0; ++ ieee->wpa_enabled = 0; ++ ieee->tkip_countermeasures = 0; ++ ieee->drop_unencrypted = 0; ++ ieee->privacy_invoked = 0; ++ ieee->ieee802_1x = 1; ++ ieee->raw_tx = 0; ++ //ieee->hwsec_support = 1; //defalt support hw security. //use module_param instead. ++ ieee->hwsec_active = 0; //disable hwsec, switch it on when necessary. ++ ++ ieee80211_softmac_init(ieee); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)) ++ ieee->pHTInfo = (RT_HIGH_THROUGHPUT*)kzalloc(sizeof(RT_HIGH_THROUGHPUT), GFP_KERNEL); ++#else ++ ieee->pHTInfo = (RT_HIGH_THROUGHPUT*)kmalloc(sizeof(RT_HIGH_THROUGHPUT), GFP_KERNEL); ++ memset(ieee->pHTInfo,0,sizeof(RT_HIGH_THROUGHPUT)); ++#endif ++ if (ieee->pHTInfo == NULL) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't alloc memory for HTInfo\n"); ++ return NULL; ++ } ++ HTUpdateDefaultSetting(ieee); ++ HTInitializeHTInfo(ieee); //may move to other place. ++ TSInitialize(ieee); ++#if 0 ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++ INIT_WORK(&ieee->ht_onAssRsp, (void(*)(void*)) HTOnAssocRsp_wq); ++#else ++ INIT_WORK(&ieee->ht_onAssRsp, (void(*)(void*)) HTOnAssocRsp_wq, ieee); ++#endif ++#endif ++ for (i = 0; i < IEEE_IBSS_MAC_HASH_SIZE; i++) ++ INIT_LIST_HEAD(&ieee->ibss_mac_hash[i]); ++ ++ for (i = 0; i < 17; i++) { ++ ieee->last_rxseq_num[i] = -1; ++ ieee->last_rxfrag_num[i] = -1; ++ ieee->last_packet_time[i] = 0; ++ } ++ ++//These function were added to load crypte module autoly ++ ieee80211_tkip_null(); ++ ieee80211_wep_null(); ++ ieee80211_ccmp_null(); ++ ++ return dev; ++ ++ failed: ++ if (dev) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)) ++ free_netdev(dev); ++#else ++ kfree(dev); ++#endif ++ return NULL; ++} ++ ++ ++void free_ieee80211(struct net_device *dev) ++{ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)) ++ struct ieee80211_device *ieee = netdev_priv(dev); ++#else ++ struct ieee80211_device *ieee = (struct ieee80211_device *)dev->priv; ++#endif ++ int i; ++ //struct list_head *p, *q; ++// del_timer_sync(&ieee->SwBwTimer); ++#if 1 ++ if (ieee->pHTInfo != NULL) ++ { ++ kfree(ieee->pHTInfo); ++ ieee->pHTInfo = NULL; ++ } ++#endif ++ RemoveAllTS(ieee); ++ ieee80211_softmac_free(ieee); ++ del_timer_sync(&ieee->crypt_deinit_timer); ++ ieee80211_crypt_deinit_entries(ieee, 1); ++ ++ for (i = 0; i < WEP_KEYS; i++) { ++ struct ieee80211_crypt_data *crypt = ieee->crypt[i]; ++ if (crypt) { ++ if (crypt->ops) { ++ crypt->ops->deinit(crypt->priv); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) ++ module_put(crypt->ops->owner); ++#else ++ __MOD_DEC_USE_COUNT(crypt->ops->owner); ++#endif ++ } ++ kfree(crypt); ++ ieee->crypt[i] = NULL; ++ } ++ } ++ ++ ieee80211_networks_free(ieee); ++#if 0 ++ for (i = 0; i < IEEE_IBSS_MAC_HASH_SIZE; i++) { ++ list_for_each_safe(p, q, &ieee->ibss_mac_hash[i]) { ++ kfree(list_entry(p, struct ieee_ibss_seq, list)); ++ list_del(p); ++ } ++ } ++ ++#endif ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)) ++ free_netdev(dev); ++#else ++ kfree(dev); ++#endif ++} ++ ++#ifdef CONFIG_IEEE80211_DEBUG ++ ++u32 ieee80211_debug_level = 0; ++static int debug = \ ++ // IEEE80211_DL_INFO | ++ // IEEE80211_DL_WX | ++ // IEEE80211_DL_SCAN | ++ // IEEE80211_DL_STATE | ++ // IEEE80211_DL_MGMT | ++ // IEEE80211_DL_FRAG | ++ // IEEE80211_DL_EAP | ++ // IEEE80211_DL_DROP | ++ // IEEE80211_DL_TX | ++ // IEEE80211_DL_RX | ++ //IEEE80211_DL_QOS | ++ // IEEE80211_DL_HT | ++ // IEEE80211_DL_TS | ++// IEEE80211_DL_BA | ++ // IEEE80211_DL_REORDER| ++// IEEE80211_DL_TRACE | ++ //IEEE80211_DL_DATA | ++ IEEE80211_DL_ERR //awayls open this flags to show error out ++ ; ++struct proc_dir_entry *ieee80211_proc = NULL; ++ ++static int show_debug_level(char *page, char **start, off_t offset, ++ int count, int *eof, void *data) ++{ ++ return snprintf(page, count, "0x%08X\n", ieee80211_debug_level); ++} ++ ++static int store_debug_level(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ char buf[] = "0x00000000"; ++ unsigned long len = min(sizeof(buf) - 1, (u32)count); ++ char *p = (char *)buf; ++ unsigned long val; ++ ++ if (copy_from_user(buf, buffer, len)) ++ return count; ++ buf[len] = 0; ++ if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') { ++ p++; ++ if (p[0] == 'x' || p[0] == 'X') ++ p++; ++ val = simple_strtoul(p, &p, 16); ++ } else ++ val = simple_strtoul(p, &p, 10); ++ if (p == buf) ++ printk(KERN_INFO DRV_NAME ++ ": %s is not in hex or decimal form.\n", buf); ++ else ++ ieee80211_debug_level = val; ++ ++ return strnlen(buf, count); ++} ++ ++extern int ieee80211_crypto_init(void); ++extern void ieee80211_crypto_deinit(void); ++extern int ieee80211_crypto_tkip_init(void); ++extern void ieee80211_crypto_tkip_exit(void); ++extern int ieee80211_crypto_ccmp_init(void); ++extern void ieee80211_crypto_ccmp_exit(void); ++extern int ieee80211_crypto_wep_init(void); ++extern void ieee80211_crypto_wep_exit(void); ++ ++int __init ieee80211_init(void) ++{ ++ struct proc_dir_entry *e; ++ int retval; ++ ++ retval = ieee80211_crypto_init(); ++ if (retval) ++ return retval; ++ retval = ieee80211_crypto_tkip_init(); ++ if (retval) { ++ ieee80211_crypto_deinit(); ++ return retval; ++ } ++ retval = ieee80211_crypto_ccmp_init(); ++ if (retval) { ++ ieee80211_crypto_tkip_exit(); ++ ieee80211_crypto_deinit(); ++ return retval; ++ } ++ retval = ieee80211_crypto_wep_init(); ++ if (retval) { ++ ieee80211_crypto_ccmp_exit(); ++ ieee80211_crypto_tkip_exit(); ++ ieee80211_crypto_deinit(); ++ return retval; ++ } ++ ++ ieee80211_debug_level = debug; ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ ieee80211_proc = create_proc_entry(DRV_NAME, S_IFDIR, proc_net); ++#else ++ ieee80211_proc = create_proc_entry(DRV_NAME, S_IFDIR, init_net.proc_net); ++#endif ++ if (ieee80211_proc == NULL) { ++ IEEE80211_ERROR("Unable to create " DRV_NAME ++ " proc directory\n"); ++ return -EIO; ++ } ++ e = create_proc_entry("debug_level", S_IFREG | S_IRUGO | S_IWUSR, ++ ieee80211_proc); ++ if (!e) { ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ remove_proc_entry(DRV_NAME, proc_net); ++#else ++ remove_proc_entry(DRV_NAME, init_net.proc_net); ++#endif ++ ieee80211_proc = NULL; ++ return -EIO; ++ } ++ e->read_proc = show_debug_level; ++ e->write_proc = store_debug_level; ++ e->data = NULL; ++ ++ return 0; ++} ++ ++void __exit ieee80211_exit(void) ++{ ++ if (ieee80211_proc) { ++ remove_proc_entry("debug_level", ieee80211_proc); ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ remove_proc_entry(DRV_NAME, proc_net); ++#else ++ remove_proc_entry(DRV_NAME, init_net.proc_net); ++#endif ++ ieee80211_proc = NULL; ++ } ++ ieee80211_crypto_wep_exit(); ++ ieee80211_crypto_ccmp_exit(); ++ ieee80211_crypto_tkip_exit(); ++ ieee80211_crypto_deinit(); ++} ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++#include ++module_param(debug, int, 0444); ++MODULE_PARM_DESC(debug, "debug output mask"); ++ ++ ++//module_exit(ieee80211_exit); ++//module_init(ieee80211_init); ++#endif ++#endif ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++//EXPORT_SYMBOL(alloc_ieee80211); ++//EXPORT_SYMBOL(free_ieee80211); ++#else ++EXPORT_SYMBOL_NOVERS(alloc_ieee80211); ++EXPORT_SYMBOL_NOVERS(free_ieee80211); ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_rx.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_rx.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_rx.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,2802 @@ ++/* ++ * Original code based Host AP (software wireless LAN access point) driver ++ * for Intersil Prism2/2.5/3 - hostap.o module, common routines ++ * ++ * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen ++ * ++ * Copyright (c) 2002-2003, Jouni Malinen ++ * Copyright (c) 2004, Intel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. See README and COPYING for ++ * more details. ++ ****************************************************************************** ++ ++ Few modifications for Realtek's Wi-Fi drivers by ++ Andrea Merello ++ ++ A special thanks goes to Realtek for their support ! ++ ++******************************************************************************/ ++ ++ ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ieee80211.h" ++#ifdef ENABLE_DOT11D ++#include "dot11d.h" ++#endif ++static inline void ieee80211_monitor_rx(struct ieee80211_device *ieee, ++ struct sk_buff *skb, ++ struct ieee80211_rx_stats *rx_stats) ++{ ++ struct ieee80211_hdr_4addr *hdr = (struct ieee80211_hdr_4addr *)skb->data; ++ u16 fc = le16_to_cpu(hdr->frame_ctl); ++ ++ skb->dev = ieee->dev; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) ++ skb_reset_mac_header(skb); ++#else ++ skb->mac.raw = skb->data; ++#endif ++ ++ skb_pull(skb, ieee80211_get_hdrlen(fc)); ++ skb->pkt_type = PACKET_OTHERHOST; ++ skb->protocol = __constant_htons(ETH_P_80211_RAW); ++ memset(skb->cb, 0, sizeof(skb->cb)); ++ netif_rx(skb); ++} ++ ++ ++/* Called only as a tasklet (software IRQ) */ ++static struct ieee80211_frag_entry * ++ieee80211_frag_cache_find(struct ieee80211_device *ieee, unsigned int seq, ++ unsigned int frag, u8 tid,u8 *src, u8 *dst) ++{ ++ struct ieee80211_frag_entry *entry; ++ int i; ++ ++ for (i = 0; i < IEEE80211_FRAG_CACHE_LEN; i++) { ++ entry = &ieee->frag_cache[tid][i]; ++ if (entry->skb != NULL && ++ time_after(jiffies, entry->first_frag_time + 2 * HZ)) { ++ IEEE80211_DEBUG_FRAG( ++ "expiring fragment cache entry " ++ "seq=%u last_frag=%u\n", ++ entry->seq, entry->last_frag); ++ dev_kfree_skb_any(entry->skb); ++ entry->skb = NULL; ++ } ++ ++ if (entry->skb != NULL && entry->seq == seq && ++ (entry->last_frag + 1 == frag || frag == -1) && ++ memcmp(entry->src_addr, src, ETH_ALEN) == 0 && ++ memcmp(entry->dst_addr, dst, ETH_ALEN) == 0) ++ return entry; ++ } ++ ++ return NULL; ++} ++ ++/* Called only as a tasklet (software IRQ) */ ++static struct sk_buff * ++ieee80211_frag_cache_get(struct ieee80211_device *ieee, ++ struct ieee80211_hdr_4addr *hdr) ++{ ++ struct sk_buff *skb = NULL; ++ u16 fc = le16_to_cpu(hdr->frame_ctl); ++ u16 sc = le16_to_cpu(hdr->seq_ctl); ++ unsigned int frag = WLAN_GET_SEQ_FRAG(sc); ++ unsigned int seq = WLAN_GET_SEQ_SEQ(sc); ++ struct ieee80211_frag_entry *entry; ++ struct ieee80211_hdr_3addrqos *hdr_3addrqos; ++ struct ieee80211_hdr_4addrqos *hdr_4addrqos; ++ u8 tid; ++ ++ if (((fc & IEEE80211_FCTL_DSTODS) == IEEE80211_FCTL_DSTODS)&&IEEE80211_QOS_HAS_SEQ(fc)) { ++ hdr_4addrqos = (struct ieee80211_hdr_4addrqos *)hdr; ++ tid = le16_to_cpu(hdr_4addrqos->qos_ctl) & IEEE80211_QCTL_TID; ++ tid = UP2AC(tid); ++ tid ++; ++ } else if (IEEE80211_QOS_HAS_SEQ(fc)) { ++ hdr_3addrqos = (struct ieee80211_hdr_3addrqos *)hdr; ++ tid = le16_to_cpu(hdr_3addrqos->qos_ctl) & IEEE80211_QCTL_TID; ++ tid = UP2AC(tid); ++ tid ++; ++ } else { ++ tid = 0; ++ } ++ ++ if (frag == 0) { ++ /* Reserve enough space to fit maximum frame length */ ++ skb = dev_alloc_skb(ieee->dev->mtu + ++ sizeof(struct ieee80211_hdr_4addr) + ++ 8 /* LLC */ + ++ 2 /* alignment */ + ++ 8 /* WEP */ + ++ ETH_ALEN /* WDS */ + ++ (IEEE80211_QOS_HAS_SEQ(fc)?2:0) /* QOS Control */); ++ if (skb == NULL) ++ return NULL; ++ ++ entry = &ieee->frag_cache[tid][ieee->frag_next_idx[tid]]; ++ ieee->frag_next_idx[tid]++; ++ if (ieee->frag_next_idx[tid] >= IEEE80211_FRAG_CACHE_LEN) ++ ieee->frag_next_idx[tid] = 0; ++ ++ if (entry->skb != NULL) ++ dev_kfree_skb_any(entry->skb); ++ ++ entry->first_frag_time = jiffies; ++ entry->seq = seq; ++ entry->last_frag = frag; ++ entry->skb = skb; ++ memcpy(entry->src_addr, hdr->addr2, ETH_ALEN); ++ memcpy(entry->dst_addr, hdr->addr1, ETH_ALEN); ++ } else { ++ /* received a fragment of a frame for which the head fragment ++ * should have already been received */ ++ entry = ieee80211_frag_cache_find(ieee, seq, frag, tid,hdr->addr2, ++ hdr->addr1); ++ if (entry != NULL) { ++ entry->last_frag = frag; ++ skb = entry->skb; ++ } ++ } ++ ++ return skb; ++} ++ ++ ++/* Called only as a tasklet (software IRQ) */ ++static int ieee80211_frag_cache_invalidate(struct ieee80211_device *ieee, ++ struct ieee80211_hdr_4addr *hdr) ++{ ++ u16 fc = le16_to_cpu(hdr->frame_ctl); ++ u16 sc = le16_to_cpu(hdr->seq_ctl); ++ unsigned int seq = WLAN_GET_SEQ_SEQ(sc); ++ struct ieee80211_frag_entry *entry; ++ struct ieee80211_hdr_3addrqos *hdr_3addrqos; ++ struct ieee80211_hdr_4addrqos *hdr_4addrqos; ++ u8 tid; ++ ++ if(((fc & IEEE80211_FCTL_DSTODS) == IEEE80211_FCTL_DSTODS)&&IEEE80211_QOS_HAS_SEQ(fc)) { ++ hdr_4addrqos = (struct ieee80211_hdr_4addrqos *)hdr; ++ tid = le16_to_cpu(hdr_4addrqos->qos_ctl) & IEEE80211_QCTL_TID; ++ tid = UP2AC(tid); ++ tid ++; ++ } else if (IEEE80211_QOS_HAS_SEQ(fc)) { ++ hdr_3addrqos = (struct ieee80211_hdr_3addrqos *)hdr; ++ tid = le16_to_cpu(hdr_3addrqos->qos_ctl) & IEEE80211_QCTL_TID; ++ tid = UP2AC(tid); ++ tid ++; ++ } else { ++ tid = 0; ++ } ++ ++ entry = ieee80211_frag_cache_find(ieee, seq, -1, tid,hdr->addr2, ++ hdr->addr1); ++ ++ if (entry == NULL) { ++ IEEE80211_DEBUG_FRAG( ++ "could not invalidate fragment cache " ++ "entry (seq=%u)\n", seq); ++ return -1; ++ } ++ ++ entry->skb = NULL; ++ return 0; ++} ++ ++ ++ ++/* ieee80211_rx_frame_mgtmt ++ * ++ * Responsible for handling management control frames ++ * ++ * Called by ieee80211_rx */ ++static inline int ++ieee80211_rx_frame_mgmt(struct ieee80211_device *ieee, struct sk_buff *skb, ++ struct ieee80211_rx_stats *rx_stats, u16 type, ++ u16 stype) ++{ ++ /* On the struct stats definition there is written that ++ * this is not mandatory.... but seems that the probe ++ * response parser uses it ++ */ ++ struct ieee80211_hdr_3addr * hdr = (struct ieee80211_hdr_3addr *)skb->data; ++ ++ rx_stats->len = skb->len; ++ ieee80211_rx_mgt(ieee,(struct ieee80211_hdr_4addr *)skb->data,rx_stats); ++ //if ((ieee->state == IEEE80211_LINKED) && (memcmp(hdr->addr3, ieee->current_network.bssid, ETH_ALEN))) ++ if ((memcmp(hdr->addr1, ieee->dev->dev_addr, ETH_ALEN)))//use ADDR1 to perform address matching for Management frames ++ { ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ ++ ieee80211_rx_frame_softmac(ieee, skb, rx_stats, type, stype); ++ ++ dev_kfree_skb_any(skb); ++ ++ return 0; ++ ++ #ifdef NOT_YET ++ if (ieee->iw_mode == IW_MODE_MASTER) { ++ printk(KERN_DEBUG "%s: Master mode not yet suppported.\n", ++ ieee->dev->name); ++ return 0; ++/* ++ hostap_update_sta_ps(ieee, (struct hostap_ieee80211_hdr_4addr *) ++ skb->data);*/ ++ } ++ ++ if (ieee->hostapd && type == IEEE80211_TYPE_MGMT) { ++ if (stype == WLAN_FC_STYPE_BEACON && ++ ieee->iw_mode == IW_MODE_MASTER) { ++ struct sk_buff *skb2; ++ /* Process beacon frames also in kernel driver to ++ * update STA(AP) table statistics */ ++ skb2 = skb_clone(skb, GFP_ATOMIC); ++ if (skb2) ++ hostap_rx(skb2->dev, skb2, rx_stats); ++ } ++ ++ /* send management frames to the user space daemon for ++ * processing */ ++ ieee->apdevstats.rx_packets++; ++ ieee->apdevstats.rx_bytes += skb->len; ++ prism2_rx_80211(ieee->apdev, skb, rx_stats, PRISM2_RX_MGMT); ++ return 0; ++ } ++ ++ if (ieee->iw_mode == IW_MODE_MASTER) { ++ if (type != WLAN_FC_TYPE_MGMT && type != WLAN_FC_TYPE_CTRL) { ++ printk(KERN_DEBUG "%s: unknown management frame " ++ "(type=0x%02x, stype=0x%02x) dropped\n", ++ skb->dev->name, type, stype); ++ return -1; ++ } ++ ++ hostap_rx(skb->dev, skb, rx_stats); ++ return 0; ++ } ++ ++ printk(KERN_DEBUG "%s: hostap_rx_frame_mgmt: management frame " ++ "received in non-Host AP mode\n", skb->dev->name); ++ return -1; ++ #endif ++} ++ ++ ++ ++/* See IEEE 802.1H for LLC/SNAP encapsulation/decapsulation */ ++/* Ethernet-II snap header (RFC1042 for most EtherTypes) */ ++static unsigned char rfc1042_header[] = ++{ 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 }; ++/* Bridge-Tunnel header (for EtherTypes ETH_P_AARP and ETH_P_IPX) */ ++static unsigned char bridge_tunnel_header[] = ++{ 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 }; ++/* No encapsulation header if EtherType < 0x600 (=length) */ ++ ++/* Called by ieee80211_rx_frame_decrypt */ ++static int ieee80211_is_eapol_frame(struct ieee80211_device *ieee, ++ struct sk_buff *skb, size_t hdrlen) ++{ ++ struct net_device *dev = ieee->dev; ++ u16 fc, ethertype; ++ struct ieee80211_hdr_4addr *hdr; ++ u8 *pos; ++ ++ if (skb->len < 24) ++ return 0; ++ ++ hdr = (struct ieee80211_hdr_4addr *) skb->data; ++ fc = le16_to_cpu(hdr->frame_ctl); ++ ++ /* check that the frame is unicast frame to us */ ++ if ((fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) == ++ IEEE80211_FCTL_TODS && ++ memcmp(hdr->addr1, dev->dev_addr, ETH_ALEN) == 0 && ++ memcmp(hdr->addr3, dev->dev_addr, ETH_ALEN) == 0) { ++ /* ToDS frame with own addr BSSID and DA */ ++ } else if ((fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) == ++ IEEE80211_FCTL_FROMDS && ++ memcmp(hdr->addr1, dev->dev_addr, ETH_ALEN) == 0) { ++ /* FromDS frame with own addr as DA */ ++ } else ++ return 0; ++ ++ if (skb->len < 24 + 8) ++ return 0; ++ ++ /* check for port access entity Ethernet type */ ++// pos = skb->data + 24; ++ pos = skb->data + hdrlen; ++ ethertype = (pos[6] << 8) | pos[7]; ++ if (ethertype == ETH_P_PAE) ++ return 1; ++ ++ return 0; ++} ++ ++/* Called only as a tasklet (software IRQ), by ieee80211_rx */ ++static inline int ++ieee80211_rx_frame_decrypt(struct ieee80211_device* ieee, struct sk_buff *skb, ++ struct ieee80211_crypt_data *crypt) ++{ ++ struct ieee80211_hdr_4addr *hdr; ++ int res, hdrlen; ++ ++ if (crypt == NULL || crypt->ops->decrypt_mpdu == NULL) ++ return 0; ++#if 1 ++ if (ieee->hwsec_active) ++ { ++ cb_desc *tcb_desc = (cb_desc *)(skb->cb+ MAX_DEV_ADDR_SIZE); ++ tcb_desc->bHwSec = 1; ++ } ++#endif ++ hdr = (struct ieee80211_hdr_4addr *) skb->data; ++ hdrlen = ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl)); ++ ++#ifdef CONFIG_IEEE80211_CRYPT_TKIP ++ if (ieee->tkip_countermeasures && ++ strcmp(crypt->ops->name, "TKIP") == 0) { ++ if (net_ratelimit()) { ++ printk(KERN_DEBUG "%s: TKIP countermeasures: dropped " ++ "received packet from " MAC_FMT "\n", ++ ieee->dev->name, MAC_ARG(hdr->addr2)); ++ } ++ return -1; ++ } ++#endif ++ ++ atomic_inc(&crypt->refcnt); ++ res = crypt->ops->decrypt_mpdu(skb, hdrlen, crypt->priv); ++ atomic_dec(&crypt->refcnt); ++ if (res < 0) { ++ IEEE80211_DEBUG_DROP( ++ "decryption failed (SA=" MAC_FMT ++ ") res=%d\n", MAC_ARG(hdr->addr2), res); ++ if (res == -2) ++ IEEE80211_DEBUG_DROP("Decryption failed ICV " ++ "mismatch (key %d)\n", ++ skb->data[hdrlen + 3] >> 6); ++ ieee->ieee_stats.rx_discards_undecryptable++; ++ return -1; ++ } ++ ++ return res; ++} ++ ++ ++/* Called only as a tasklet (software IRQ), by ieee80211_rx */ ++static inline int ++ieee80211_rx_frame_decrypt_msdu(struct ieee80211_device* ieee, struct sk_buff *skb, ++ int keyidx, struct ieee80211_crypt_data *crypt) ++{ ++ struct ieee80211_hdr_4addr *hdr; ++ int res, hdrlen; ++ ++ if (crypt == NULL || crypt->ops->decrypt_msdu == NULL) ++ return 0; ++ if (ieee->hwsec_active) ++ { ++ cb_desc *tcb_desc = (cb_desc *)(skb->cb+ MAX_DEV_ADDR_SIZE); ++ tcb_desc->bHwSec = 1; ++ } ++ ++ hdr = (struct ieee80211_hdr_4addr *) skb->data; ++ hdrlen = ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl)); ++ ++ atomic_inc(&crypt->refcnt); ++ res = crypt->ops->decrypt_msdu(skb, keyidx, hdrlen, crypt->priv); ++ atomic_dec(&crypt->refcnt); ++ if (res < 0) { ++ printk(KERN_DEBUG "%s: MSDU decryption/MIC verification failed" ++ " (SA=" MAC_FMT " keyidx=%d)\n", ++ ieee->dev->name, MAC_ARG(hdr->addr2), keyidx); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++ ++/* this function is stolen from ipw2200 driver*/ ++#define IEEE_PACKET_RETRY_TIME (5*HZ) ++static int is_duplicate_packet(struct ieee80211_device *ieee, ++ struct ieee80211_hdr_4addr *header) ++{ ++ u16 fc = le16_to_cpu(header->frame_ctl); ++ u16 sc = le16_to_cpu(header->seq_ctl); ++ u16 seq = WLAN_GET_SEQ_SEQ(sc); ++ u16 frag = WLAN_GET_SEQ_FRAG(sc); ++ u16 *last_seq, *last_frag; ++ unsigned long *last_time; ++ struct ieee80211_hdr_3addrqos *hdr_3addrqos; ++ struct ieee80211_hdr_4addrqos *hdr_4addrqos; ++ u8 tid; ++ ++ ++ //TO2DS and QoS ++ if(((fc & IEEE80211_FCTL_DSTODS) == IEEE80211_FCTL_DSTODS)&&IEEE80211_QOS_HAS_SEQ(fc)) { ++ hdr_4addrqos = (struct ieee80211_hdr_4addrqos *)header; ++ tid = le16_to_cpu(hdr_4addrqos->qos_ctl) & IEEE80211_QCTL_TID; ++ tid = UP2AC(tid); ++ tid ++; ++ } else if(IEEE80211_QOS_HAS_SEQ(fc)) { //QoS ++ hdr_3addrqos = (struct ieee80211_hdr_3addrqos*)header; ++ tid = le16_to_cpu(hdr_3addrqos->qos_ctl) & IEEE80211_QCTL_TID; ++ tid = UP2AC(tid); ++ tid ++; ++ } else { // no QoS ++ tid = 0; ++ } ++ ++ switch (ieee->iw_mode) { ++ case IW_MODE_ADHOC: ++ { ++ struct list_head *p; ++ struct ieee_ibss_seq *entry = NULL; ++ u8 *mac = header->addr2; ++ int index = mac[5] % IEEE_IBSS_MAC_HASH_SIZE; ++ //for (pos = (head)->next; pos != (head); pos = pos->next) ++ //__list_for_each(p, &ieee->ibss_mac_hash[index]) { ++ list_for_each(p, &ieee->ibss_mac_hash[index]) { ++ entry = list_entry(p, struct ieee_ibss_seq, list); ++ if (!memcmp(entry->mac, mac, ETH_ALEN)) ++ break; ++ } ++ // if (memcmp(entry->mac, mac, ETH_ALEN)){ ++ if (p == &ieee->ibss_mac_hash[index]) { ++ entry = kmalloc(sizeof(struct ieee_ibss_seq), GFP_ATOMIC); ++ if (!entry) { ++ printk(KERN_WARNING "Cannot malloc new mac entry\n"); ++ return 0; ++ } ++ memcpy(entry->mac, mac, ETH_ALEN); ++ entry->seq_num[tid] = seq; ++ entry->frag_num[tid] = frag; ++ entry->packet_time[tid] = jiffies; ++ list_add(&entry->list, &ieee->ibss_mac_hash[index]); ++ return 0; ++ } ++ last_seq = &entry->seq_num[tid]; ++ last_frag = &entry->frag_num[tid]; ++ last_time = &entry->packet_time[tid]; ++ break; ++ } ++ ++ case IW_MODE_INFRA: ++ last_seq = &ieee->last_rxseq_num[tid]; ++ last_frag = &ieee->last_rxfrag_num[tid]; ++ last_time = &ieee->last_packet_time[tid]; ++ ++ break; ++ default: ++ return 0; ++ } ++ ++// if(tid != 0) { ++// printk(KERN_WARNING ":)))))))))))%x %x %x, fc(%x)\n", tid, *last_seq, seq, header->frame_ctl); ++// } ++ if ((*last_seq == seq) && ++ time_after(*last_time + IEEE_PACKET_RETRY_TIME, jiffies)) { ++ if (*last_frag == frag){ ++ //printk(KERN_WARNING "[1] go drop!\n"); ++ goto drop; ++ ++ } ++ if (*last_frag + 1 != frag) ++ /* out-of-order fragment */ ++ //printk(KERN_WARNING "[2] go drop!\n"); ++ goto drop; ++ } else ++ *last_seq = seq; ++ ++ *last_frag = frag; ++ *last_time = jiffies; ++ return 0; ++ ++drop: ++// BUG_ON(!(fc & IEEE80211_FCTL_RETRY)); ++// printk("DUP\n"); ++ ++ return 1; ++} ++bool ++AddReorderEntry( ++ PRX_TS_RECORD pTS, ++ PRX_REORDER_ENTRY pReorderEntry ++ ) ++{ ++ struct list_head *pList = &pTS->RxPendingPktList; ++#if 1 ++ while(pList->next != &pTS->RxPendingPktList) ++ { ++ if( SN_LESS(pReorderEntry->SeqNum, ((PRX_REORDER_ENTRY)list_entry(pList->next,RX_REORDER_ENTRY,List))->SeqNum) ) ++ { ++ pList = pList->next; ++ } ++ else if( SN_EQUAL(pReorderEntry->SeqNum, ((PRX_REORDER_ENTRY)list_entry(pList->next,RX_REORDER_ENTRY,List))->SeqNum) ) ++ { ++ return false; ++ } ++ else ++ { ++ break; ++ } ++ } ++#endif ++ pReorderEntry->List.next = pList->next; ++ pReorderEntry->List.next->prev = &pReorderEntry->List; ++ pReorderEntry->List.prev = pList; ++ pList->next = &pReorderEntry->List; ++ ++ return true; ++} ++ ++void ieee80211_indicate_packets(struct ieee80211_device *ieee, struct ieee80211_rxb** prxbIndicateArray,u8 index) ++{ ++ u8 i = 0 , j=0; ++ u16 ethertype; ++// if(index > 1) ++// IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): hahahahhhh, We indicate packet from reorder list, index is %u\n",__FUNCTION__,index); ++ for(j = 0; jnr_subframes; i++) { ++ struct sk_buff *sub_skb = prxb->subframes[i]; ++ ++ /* convert hdr + possible LLC headers into Ethernet header */ ++ ethertype = (sub_skb->data[6] << 8) | sub_skb->data[7]; ++ if (sub_skb->len >= 8 && ++ ((memcmp(sub_skb->data, rfc1042_header, SNAP_SIZE) == 0 && ++ ethertype != ETH_P_AARP && ethertype != ETH_P_IPX) || ++ memcmp(sub_skb->data, bridge_tunnel_header, SNAP_SIZE) == 0)) { ++ /* remove RFC1042 or Bridge-Tunnel encapsulation and ++ * replace EtherType */ ++ skb_pull(sub_skb, SNAP_SIZE); ++ memcpy(skb_push(sub_skb, ETH_ALEN), prxb->src, ETH_ALEN); ++ memcpy(skb_push(sub_skb, ETH_ALEN), prxb->dst, ETH_ALEN); ++ } else { ++ u16 len; ++ /* Leave Ethernet header part of hdr and full payload */ ++ len = htons(sub_skb->len); ++ memcpy(skb_push(sub_skb, 2), &len, 2); ++ memcpy(skb_push(sub_skb, ETH_ALEN), prxb->src, ETH_ALEN); ++ memcpy(skb_push(sub_skb, ETH_ALEN), prxb->dst, ETH_ALEN); ++ } ++ //stats->rx_packets++; ++ //stats->rx_bytes += sub_skb->len; ++ ++ /* Indicat the packets to upper layer */ ++ if (sub_skb) { ++ //printk("0skb_len(%d)\n", skb->len); ++ sub_skb->protocol = eth_type_trans(sub_skb, ieee->dev); ++ memset(sub_skb->cb, 0, sizeof(sub_skb->cb)); ++ sub_skb->dev = ieee->dev; ++ sub_skb->ip_summed = CHECKSUM_NONE; /* 802.11 crc not sufficient */ ++ //skb->ip_summed = CHECKSUM_UNNECESSARY; /* 802.11 crc not sufficient */ ++ ieee->last_rx_ps_time = jiffies; ++ //printk("1skb_len(%d)\n", skb->len); ++ netif_rx(sub_skb); ++ } ++ } ++ kfree(prxb); ++ prxb = NULL; ++ } ++} ++ ++ ++void RxReorderIndicatePacket( struct ieee80211_device *ieee, ++ struct ieee80211_rxb* prxb, ++ PRX_TS_RECORD pTS, ++ u16 SeqNum) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ PRX_REORDER_ENTRY pReorderEntry = NULL; ++ struct ieee80211_rxb* prxbIndicateArray[REORDER_WIN_SIZE]; ++ u8 WinSize = pHTInfo->RxReorderWinSize; ++ u16 WinEnd = (pTS->RxIndicateSeq + WinSize -1)%4096; ++ u8 index = 0; ++ bool bMatchWinStart = false, bPktInBuf = false; ++ IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): Seq is %d,pTS->RxIndicateSeq is %d, WinSize is %d\n",__FUNCTION__,SeqNum,pTS->RxIndicateSeq,WinSize); ++#if 0 ++ if(!list_empty(&ieee->RxReorder_Unused_List)) ++ IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): ieee->RxReorder_Unused_List is nut NULL\n"); ++#endif ++ /* Rx Reorder initialize condition.*/ ++ if(pTS->RxIndicateSeq == 0xffff) { ++ pTS->RxIndicateSeq = SeqNum; ++ } ++ ++ /* Drop out the packet which SeqNum is smaller than WinStart */ ++ if(SN_LESS(SeqNum, pTS->RxIndicateSeq)) { ++ IEEE80211_DEBUG(IEEE80211_DL_REORDER,"Packet Drop! IndicateSeq: %d, NewSeq: %d\n", ++ pTS->RxIndicateSeq, SeqNum); ++ pHTInfo->RxReorderDropCounter++; ++ { ++ int i; ++ for(i =0; i < prxb->nr_subframes; i++) { ++ dev_kfree_skb(prxb->subframes[i]); ++ } ++ kfree(prxb); ++ prxb = NULL; ++ } ++ return; ++ } ++ ++ /* ++ * Sliding window manipulation. Conditions includes: ++ * 1. Incoming SeqNum is equal to WinStart =>Window shift 1 ++ * 2. Incoming SeqNum is larger than the WinEnd => Window shift N ++ */ ++ if(SN_EQUAL(SeqNum, pTS->RxIndicateSeq)) { ++ pTS->RxIndicateSeq = (pTS->RxIndicateSeq + 1) % 4096; ++ bMatchWinStart = true; ++ } else if(SN_LESS(WinEnd, SeqNum)) { ++ if(SeqNum >= (WinSize - 1)) { ++ pTS->RxIndicateSeq = SeqNum + 1 -WinSize; ++ } else { ++ pTS->RxIndicateSeq = 4095 - (WinSize - (SeqNum +1)) + 1; ++ } ++ IEEE80211_DEBUG(IEEE80211_DL_REORDER, "Window Shift! IndicateSeq: %d, NewSeq: %d\n",pTS->RxIndicateSeq, SeqNum); ++ } ++ ++ /* ++ * Indication process. ++ * After Packet dropping and Sliding Window shifting as above, we can now just indicate the packets ++ * with the SeqNum smaller than latest WinStart and buffer other packets. ++ */ ++ /* For Rx Reorder condition: ++ * 1. All packets with SeqNum smaller than WinStart => Indicate ++ * 2. All packets with SeqNum larger than or equal to WinStart => Buffer it. ++ */ ++ if(bMatchWinStart) { ++ /* Current packet is going to be indicated.*/ ++ IEEE80211_DEBUG(IEEE80211_DL_REORDER, "Packets indication!! IndicateSeq: %d, NewSeq: %d\n",\ ++ pTS->RxIndicateSeq, SeqNum); ++ prxbIndicateArray[0] = prxb; ++// printk("========================>%s(): SeqNum is %d\n",__FUNCTION__,SeqNum); ++ index = 1; ++ } else { ++ /* Current packet is going to be inserted into pending list.*/ ++ //IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): We RX no ordered packed, insert to orderd list\n",__FUNCTION__); ++ if(!list_empty(&ieee->RxReorder_Unused_List)) { ++ pReorderEntry = (PRX_REORDER_ENTRY)list_entry(ieee->RxReorder_Unused_List.next,RX_REORDER_ENTRY,List); ++ list_del_init(&pReorderEntry->List); ++ ++ /* Make a reorder entry and insert into a the packet list.*/ ++ pReorderEntry->SeqNum = SeqNum; ++ pReorderEntry->prxb = prxb; ++ // IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): pREorderEntry->SeqNum is %d\n",__FUNCTION__,pReorderEntry->SeqNum); ++ ++#if 1 ++ if(!AddReorderEntry(pTS, pReorderEntry)) { ++ IEEE80211_DEBUG(IEEE80211_DL_REORDER, "%s(): Duplicate packet is dropped!! IndicateSeq: %d, NewSeq: %d\n", ++ __FUNCTION__, pTS->RxIndicateSeq, SeqNum); ++ list_add_tail(&pReorderEntry->List,&ieee->RxReorder_Unused_List); ++ { ++ int i; ++ for(i =0; i < prxb->nr_subframes; i++) { ++ dev_kfree_skb(prxb->subframes[i]); ++ } ++ kfree(prxb); ++ prxb = NULL; ++ } ++ } else { ++ IEEE80211_DEBUG(IEEE80211_DL_REORDER, ++ "Pkt insert into buffer!! IndicateSeq: %d, NewSeq: %d\n",pTS->RxIndicateSeq, SeqNum); ++ } ++#endif ++ } ++ else { ++ /* ++ * Packets are dropped if there is not enough reorder entries. ++ * This part shall be modified!! We can just indicate all the ++ * packets in buffer and get reorder entries. ++ */ ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "RxReorderIndicatePacket(): There is no reorder entry!! Packet is dropped!!\n"); ++ { ++ int i; ++ for(i =0; i < prxb->nr_subframes; i++) { ++ dev_kfree_skb(prxb->subframes[i]); ++ } ++ kfree(prxb); ++ prxb = NULL; ++ } ++ } ++ } ++ ++ /* Check if there is any packet need indicate.*/ ++ while(!list_empty(&pTS->RxPendingPktList)) { ++ IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): start RREORDER indicate\n",__FUNCTION__); ++#if 1 ++ pReorderEntry = (PRX_REORDER_ENTRY)list_entry(pTS->RxPendingPktList.prev,RX_REORDER_ENTRY,List); ++ if( SN_LESS(pReorderEntry->SeqNum, pTS->RxIndicateSeq) || ++ SN_EQUAL(pReorderEntry->SeqNum, pTS->RxIndicateSeq)) ++ { ++ /* This protect buffer from overflow. */ ++ if(index >= REORDER_WIN_SIZE) { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "RxReorderIndicatePacket(): Buffer overflow!! \n"); ++ bPktInBuf = true; ++ break; ++ } ++ ++ list_del_init(&pReorderEntry->List); ++ ++ if(SN_EQUAL(pReorderEntry->SeqNum, pTS->RxIndicateSeq)) ++ pTS->RxIndicateSeq = (pTS->RxIndicateSeq + 1) % 4096; ++ ++ IEEE80211_DEBUG(IEEE80211_DL_REORDER,"Packets indication!! IndicateSeq: %d, NewSeq: %d\n",pTS->RxIndicateSeq, SeqNum); ++ prxbIndicateArray[index] = pReorderEntry->prxb; ++ // printk("========================>%s(): pReorderEntry->SeqNum is %d\n",__FUNCTION__,pReorderEntry->SeqNum); ++ index++; ++ ++ list_add_tail(&pReorderEntry->List,&ieee->RxReorder_Unused_List); ++ } else { ++ bPktInBuf = true; ++ break; ++ } ++#endif ++ } ++ ++ /* Handling pending timer. Set this timer to prevent from long time Rx buffering.*/ ++ if(index>0) { ++ // Cancel previous pending timer. ++ if (timer_pending(&pTS->RxPktPendingTimer)) ++ del_timer_sync(&pTS->RxPktPendingTimer); ++ pTS->RxTimeoutIndicateSeq = 0xffff; ++ ++ // Indicate packets ++ if(index>REORDER_WIN_SIZE){ ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "RxReorderIndicatePacket(): Rx Reorer buffer full!! \n"); ++ return; ++ } ++ ieee80211_indicate_packets(ieee, prxbIndicateArray, index); ++ bPktInBuf = false; ++ } ++ ++#if 1 ++ if(bPktInBuf && pTS->RxTimeoutIndicateSeq==0xffff) { ++ // Set new pending timer. ++ IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): SET rx timeout timer\n", __FUNCTION__); ++ pTS->RxTimeoutIndicateSeq = pTS->RxIndicateSeq; ++#if 0 ++ if(timer_pending(&pTS->RxPktPendingTimer)) ++ del_timer_sync(&pTS->RxPktPendingTimer); ++ pTS->RxPktPendingTimer.expires = jiffies + MSECS(pHTInfo->RxReorderPendingTime); ++ add_timer(&pTS->RxPktPendingTimer); ++#else ++ mod_timer(&pTS->RxPktPendingTimer, jiffies + MSECS(pHTInfo->RxReorderPendingTime)); ++#endif ++ } ++#endif ++} ++ ++u8 parse_subframe(struct sk_buff *skb, ++ struct ieee80211_rx_stats *rx_stats, ++ struct ieee80211_rxb *rxb,u8* src,u8* dst) ++{ ++ struct ieee80211_hdr_3addr *hdr = (struct ieee80211_hdr_3addr* )skb->data; ++ u16 fc = le16_to_cpu(hdr->frame_ctl); ++ ++ u16 LLCOffset= sizeof(struct ieee80211_hdr_3addr); ++ u16 ChkLength; ++ bool bIsAggregateFrame = false; ++ u16 nSubframe_Length; ++ u8 nPadding_Length = 0; ++ u16 SeqNum=0; ++ ++ struct sk_buff *sub_skb; ++ u8 *data_ptr; ++ /* just for debug purpose */ ++ SeqNum = WLAN_GET_SEQ_SEQ(le16_to_cpu(hdr->seq_ctl)); ++ ++ if((IEEE80211_QOS_HAS_SEQ(fc))&&\ ++ (((frameqos *)(skb->data + IEEE80211_3ADDR_LEN))->field.reserved)) { ++ bIsAggregateFrame = true; ++ } ++ ++ if(IEEE80211_QOS_HAS_SEQ(fc)) { ++ LLCOffset += 2; ++ } ++ ++ if(rx_stats->bContainHTC) { ++ LLCOffset += sHTCLng; ++ } ++ //printk("ChkLength = %d\n", LLCOffset); ++ // Null packet, don't indicate it to upper layer ++ ChkLength = LLCOffset;/* + (Frame_WEP(frame)!=0 ?Adapter->MgntInfo.SecurityInfo.EncryptionHeadOverhead:0);*/ ++ ++ if( skb->len <= ChkLength ) { ++ return 0; ++ } ++ ++ skb_pull(skb, LLCOffset); ++ ++ if(!bIsAggregateFrame) { ++ rxb->nr_subframes = 1; ++#ifdef JOHN_NOCPY ++ rxb->subframes[0] = skb; ++#else ++ rxb->subframes[0] = skb_copy(skb, GFP_ATOMIC); ++#endif ++ ++ memcpy(rxb->src,src,ETH_ALEN); ++ memcpy(rxb->dst,dst,ETH_ALEN); ++ //IEEE80211_DEBUG_DATA(IEEE80211_DL_RX,skb->data,skb->len); ++ return 1; ++ } else { ++ rxb->nr_subframes = 0; ++ memcpy(rxb->src,src,ETH_ALEN); ++ memcpy(rxb->dst,dst,ETH_ALEN); ++ while(skb->len > ETHERNET_HEADER_SIZE) { ++ /* Offset 12 denote 2 mac address */ ++ nSubframe_Length = *((u16*)(skb->data + 12)); ++ //==m==>change the length order ++ nSubframe_Length = (nSubframe_Length>>8) + (nSubframe_Length<<8); ++ ++ if(skb->len<(ETHERNET_HEADER_SIZE + nSubframe_Length)) { ++#if 0//cosa ++ RT_ASSERT( ++ (nRemain_Length>=(ETHERNET_HEADER_SIZE + nSubframe_Length)), ++ ("ParseSubframe(): A-MSDU subframe parse error!! Subframe Length: %d\n", nSubframe_Length) ); ++#endif ++ printk("%s: A-MSDU parse error!! pRfd->nTotalSubframe : %d\n",\ ++ __FUNCTION__,rxb->nr_subframes); ++ printk("%s: A-MSDU parse error!! Subframe Length: %d\n",__FUNCTION__, nSubframe_Length); ++ printk("nRemain_Length is %d and nSubframe_Length is : %d\n",skb->len,nSubframe_Length); ++ printk("The Packet SeqNum is %d\n",SeqNum); ++ return 0; ++ } ++ ++ /* move the data point to data content */ ++ skb_pull(skb, ETHERNET_HEADER_SIZE); ++ ++#ifdef JOHN_NOCPY ++ sub_skb = skb_clone(skb, GFP_ATOMIC); ++ sub_skb->len = nSubframe_Length; ++ sub_skb->tail = sub_skb->data + nSubframe_Length; ++#else ++ /* Allocate new skb for releasing to upper layer */ ++ sub_skb = dev_alloc_skb(nSubframe_Length + 12); ++ skb_reserve(sub_skb, 12); ++ data_ptr = (u8 *)skb_put(sub_skb, nSubframe_Length); ++ memcpy(data_ptr,skb->data,nSubframe_Length); ++#endif ++ rxb->subframes[rxb->nr_subframes++] = sub_skb; ++ if(rxb->nr_subframes >= MAX_SUBFRAME_COUNT) { ++ IEEE80211_DEBUG_RX("ParseSubframe(): Too many Subframes! Packets dropped!\n"); ++ break; ++ } ++ skb_pull(skb,nSubframe_Length); ++ ++ if(skb->len != 0) { ++ nPadding_Length = 4 - ((nSubframe_Length + ETHERNET_HEADER_SIZE) % 4); ++ if(nPadding_Length == 4) { ++ nPadding_Length = 0; ++ } ++ ++ if(skb->len < nPadding_Length) { ++ return 0; ++ } ++ ++ skb_pull(skb,nPadding_Length); ++ } ++ } ++#ifdef JOHN_NOCPY ++ dev_kfree_skb(skb); ++#endif ++ //{just for debug added by david ++ //printk("AMSDU::rxb->nr_subframes = %d\n",rxb->nr_subframes); ++ //} ++ return rxb->nr_subframes; ++ } ++} ++ ++/* All received frames are sent to this function. @skb contains the frame in ++ * IEEE 802.11 format, i.e., in the format it was sent over air. ++ * This function is called only as a tasklet (software IRQ). */ ++int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb, ++ struct ieee80211_rx_stats *rx_stats) ++{ ++ struct net_device *dev = ieee->dev; ++ struct ieee80211_hdr_4addr *hdr; ++ //struct ieee80211_hdr_3addrqos *hdr; ++ ++ size_t hdrlen; ++ u16 fc, type, stype, sc; ++ struct net_device_stats *stats; ++ unsigned int frag; ++ u8 *payload; ++ u16 ethertype; ++ //added by amy for reorder ++ u8 TID = 0; ++ u16 SeqNum = 0; ++ PRX_TS_RECORD pTS = NULL; ++ //bool bIsAggregateFrame = false; ++ //added by amy for reorder ++#ifdef NOT_YET ++ struct net_device *wds = NULL; ++ struct sk_buff *skb2 = NULL; ++ struct net_device *wds = NULL; ++ int frame_authorized = 0; ++ int from_assoc_ap = 0; ++ void *sta = NULL; ++#endif ++// u16 qos_ctl = 0; ++ u8 dst[ETH_ALEN]; ++ u8 src[ETH_ALEN]; ++ u8 bssid[ETH_ALEN]; ++ struct ieee80211_crypt_data *crypt = NULL; ++ int keyidx = 0; ++ ++ int i; ++ struct ieee80211_rxb* rxb = NULL; ++ // cheat the the hdr type ++ hdr = (struct ieee80211_hdr_4addr *)skb->data; ++ stats = &ieee->stats; ++ ++ if (skb->len < 10) { ++ printk(KERN_INFO "%s: SKB length < 10\n", ++ dev->name); ++ goto rx_dropped; ++ } ++ ++ fc = le16_to_cpu(hdr->frame_ctl); ++ type = WLAN_FC_GET_TYPE(fc); ++ stype = WLAN_FC_GET_STYPE(fc); ++ sc = le16_to_cpu(hdr->seq_ctl); ++ ++ frag = WLAN_GET_SEQ_FRAG(sc); ++ hdrlen = ieee80211_get_hdrlen(fc); ++ ++ if(HTCCheck(ieee, skb->data)) ++ { ++ if(net_ratelimit()) ++ printk("find HTCControl\n"); ++ hdrlen += 4; ++ rx_stats->bContainHTC = 1; ++ } ++ ++ //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len); ++#ifdef NOT_YET ++#if WIRELESS_EXT > 15 ++ /* Put this code here so that we avoid duplicating it in all ++ * Rx paths. - Jean II */ ++#ifdef IW_WIRELESS_SPY /* defined in iw_handler.h */ ++ /* If spy monitoring on */ ++ if (iface->spy_data.spy_number > 0) { ++ struct iw_quality wstats; ++ wstats.level = rx_stats->rssi; ++ wstats.noise = rx_stats->noise; ++ wstats.updated = 6; /* No qual value */ ++ /* Update spy records */ ++ wireless_spy_update(dev, hdr->addr2, &wstats); ++ } ++#endif /* IW_WIRELESS_SPY */ ++#endif /* WIRELESS_EXT > 15 */ ++ hostap_update_rx_stats(local->ap, hdr, rx_stats); ++#endif ++ ++#if WIRELESS_EXT > 15 ++ if (ieee->iw_mode == IW_MODE_MONITOR) { ++ ieee80211_monitor_rx(ieee, skb, rx_stats); ++ stats->rx_packets++; ++ stats->rx_bytes += skb->len; ++ return 1; ++ } ++#endif ++ if (ieee->host_decrypt) { ++ int idx = 0; ++ if (skb->len >= hdrlen + 3) ++ idx = skb->data[hdrlen + 3] >> 6; ++ crypt = ieee->crypt[idx]; ++#ifdef NOT_YET ++ sta = NULL; ++ ++ /* Use station specific key to override default keys if the ++ * receiver address is a unicast address ("individual RA"). If ++ * bcrx_sta_key parameter is set, station specific key is used ++ * even with broad/multicast targets (this is against IEEE ++ * 802.11, but makes it easier to use different keys with ++ * stations that do not support WEP key mapping). */ ++ ++ if (!(hdr->addr1[0] & 0x01) || local->bcrx_sta_key) ++ (void) hostap_handle_sta_crypto(local, hdr, &crypt, ++ &sta); ++#endif ++ ++ /* allow NULL decrypt to indicate an station specific override ++ * for default encryption */ ++ if (crypt && (crypt->ops == NULL || ++ crypt->ops->decrypt_mpdu == NULL)) ++ crypt = NULL; ++ ++ if (!crypt && (fc & IEEE80211_FCTL_WEP)) { ++ /* This seems to be triggered by some (multicast?) ++ * frames from other than current BSS, so just drop the ++ * frames silently instead of filling system log with ++ * these reports. */ ++ IEEE80211_DEBUG_DROP("Decryption failed (not set)" ++ " (SA=" MAC_FMT ")\n", ++ MAC_ARG(hdr->addr2)); ++ ieee->ieee_stats.rx_discards_undecryptable++; ++ goto rx_dropped; ++ } ++ } ++ ++ if (skb->len < IEEE80211_DATA_HDR3_LEN) ++ goto rx_dropped; ++ ++ // if QoS enabled, should check the sequence for each of the AC ++ if( (ieee->pHTInfo->bCurRxReorderEnable == false) || !ieee->current_network.qos_data.active|| !IsDataFrame(skb->data) || IsLegacyDataFrame(skb->data)){ ++ if (is_duplicate_packet(ieee, hdr)) ++ goto rx_dropped; ++ ++ } ++ else ++ { ++ PRX_TS_RECORD pRxTS = NULL; ++ #if 0 ++ struct ieee80211_hdr_3addr *hdr; ++ u16 fc; ++ hdr = (struct ieee80211_hdr_3addr *)skb->data; ++ fc = le16_to_cpu(hdr->frame_ctl); ++ u8 tmp = (fc & IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS); ++ ++ u8 tid = (*((u8*)skb->data + (((fc& IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS))?30:24)))&0xf; ++ printk("====================>fc:%x, tid:%d, tmp:%d\n", fc, tid, tmp); ++ //u8 tid = (u8)((frameqos*)(buf + ((fc & IEEE80211_FCTL_TODS)&&(fc & IEEE80211_FCTL_FROMDS))? 30 : 24))->field.tid; ++ #endif ++ //IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): QOS ENABLE AND RECEIVE QOS DATA , we will get Ts, tid:%d\n",__FUNCTION__, tid); ++#if 1 ++ if(GetTs( ++ ieee, ++ (PTS_COMMON_INFO*) &pRxTS, ++ hdr->addr2, ++ (u8)Frame_QoSTID((u8*)(skb->data)), ++ RX_DIR, ++ true)) ++ { ++ ++ // IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): pRxTS->RxLastFragNum is %d,frag is %d,pRxTS->RxLastSeqNum is %d,seq is %d\n",__FUNCTION__,pRxTS->RxLastFragNum,frag,pRxTS->RxLastSeqNum,WLAN_GET_SEQ_SEQ(sc)); ++ if( (fc & (1<<11)) && ++ (frag == pRxTS->RxLastFragNum) && ++ (WLAN_GET_SEQ_SEQ(sc) == pRxTS->RxLastSeqNum) ) ++ { ++ goto rx_dropped; ++ } ++ else ++ { ++ pRxTS->RxLastFragNum = frag; ++ pRxTS->RxLastSeqNum = WLAN_GET_SEQ_SEQ(sc); ++ } ++ } ++ else ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "%s(): No TS!! Skip the check!!\n",__FUNCTION__); ++ goto rx_dropped; ++ } ++ } ++#endif ++ if (type == IEEE80211_FTYPE_MGMT) { ++ ++ #if 0 ++ if ( stype == IEEE80211_STYPE_AUTH && ++ fc & IEEE80211_FCTL_WEP && ieee->host_decrypt && ++ (keyidx = hostap_rx_frame_decrypt(ieee, skb, crypt)) < 0) ++ { ++ printk(KERN_DEBUG "%s: failed to decrypt mgmt::auth " ++ "from " MAC_FMT "\n", dev->name, ++ MAC_ARG(hdr->addr2)); ++ /* TODO: could inform hostapd about this so that it ++ * could send auth failure report */ ++ goto rx_dropped; ++ } ++ #endif ++ ++ //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len); ++ if (ieee80211_rx_frame_mgmt(ieee, skb, rx_stats, type, stype)) ++ goto rx_dropped; ++ else ++ goto rx_exit; ++ } ++ ++ /* Data frame - extract src/dst addresses */ ++ switch (fc & (IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS)) { ++ case IEEE80211_FCTL_FROMDS: ++ memcpy(dst, hdr->addr1, ETH_ALEN); ++ memcpy(src, hdr->addr3, ETH_ALEN); ++ memcpy(bssid, hdr->addr2, ETH_ALEN); ++ break; ++ case IEEE80211_FCTL_TODS: ++ memcpy(dst, hdr->addr3, ETH_ALEN); ++ memcpy(src, hdr->addr2, ETH_ALEN); ++ memcpy(bssid, hdr->addr1, ETH_ALEN); ++ break; ++ case IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS: ++ if (skb->len < IEEE80211_DATA_HDR4_LEN) ++ goto rx_dropped; ++ memcpy(dst, hdr->addr3, ETH_ALEN); ++ memcpy(src, hdr->addr4, ETH_ALEN); ++ memcpy(bssid, ieee->current_network.bssid, ETH_ALEN); ++ break; ++ case 0: ++ memcpy(dst, hdr->addr1, ETH_ALEN); ++ memcpy(src, hdr->addr2, ETH_ALEN); ++ memcpy(bssid, hdr->addr3, ETH_ALEN); ++ break; ++ } ++ ++#ifdef NOT_YET ++ if (hostap_rx_frame_wds(ieee, hdr, fc, &wds)) ++ goto rx_dropped; ++ if (wds) { ++ skb->dev = dev = wds; ++ stats = hostap_get_stats(dev); ++ } ++ ++ if (ieee->iw_mode == IW_MODE_MASTER && !wds && ++ (fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) == IEEE80211_FCTL_FROMDS && ++ ieee->stadev && ++ memcmp(hdr->addr2, ieee->assoc_ap_addr, ETH_ALEN) == 0) { ++ /* Frame from BSSID of the AP for which we are a client */ ++ skb->dev = dev = ieee->stadev; ++ stats = hostap_get_stats(dev); ++ from_assoc_ap = 1; ++ } ++#endif ++ ++ dev->last_rx = jiffies; ++ ++#ifdef NOT_YET ++ if ((ieee->iw_mode == IW_MODE_MASTER || ++ ieee->iw_mode == IW_MODE_REPEAT) && ++ !from_assoc_ap) { ++ switch (hostap_handle_sta_rx(ieee, dev, skb, rx_stats, ++ wds != NULL)) { ++ case AP_RX_CONTINUE_NOT_AUTHORIZED: ++ frame_authorized = 0; ++ break; ++ case AP_RX_CONTINUE: ++ frame_authorized = 1; ++ break; ++ case AP_RX_DROP: ++ goto rx_dropped; ++ case AP_RX_EXIT: ++ goto rx_exit; ++ } ++ } ++#endif ++ //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len); ++ /* Nullfunc frames may have PS-bit set, so they must be passed to ++ * hostap_handle_sta_rx() before being dropped here. */ ++ if (stype != IEEE80211_STYPE_DATA && ++ stype != IEEE80211_STYPE_DATA_CFACK && ++ stype != IEEE80211_STYPE_DATA_CFPOLL && ++ stype != IEEE80211_STYPE_DATA_CFACKPOLL&& ++ stype != IEEE80211_STYPE_QOS_DATA//add by David,2006.8.4 ++ ) { ++ if (stype != IEEE80211_STYPE_NULLFUNC) ++ IEEE80211_DEBUG_DROP( ++ "RX: dropped data frame " ++ "with no data (type=0x%02x, " ++ "subtype=0x%02x, len=%d)\n", ++ type, stype, skb->len); ++ goto rx_dropped; ++ } ++ if (memcmp(bssid, ieee->current_network.bssid, ETH_ALEN)) ++ goto rx_dropped; ++ ++ /* skb: hdr + (possibly fragmented, possibly encrypted) payload */ ++ ++ if (ieee->host_decrypt && (fc & IEEE80211_FCTL_WEP) && ++ (keyidx = ieee80211_rx_frame_decrypt(ieee, skb, crypt)) < 0) ++ { ++ printk("decrypt frame error\n"); ++ goto rx_dropped; ++ } ++ ++ ++ hdr = (struct ieee80211_hdr_4addr *) skb->data; ++ ++ /* skb: hdr + (possibly fragmented) plaintext payload */ ++ // PR: FIXME: hostap has additional conditions in the "if" below: ++ // ieee->host_decrypt && (fc & IEEE80211_FCTL_WEP) && ++ if ((frag != 0 || (fc & IEEE80211_FCTL_MOREFRAGS))) { ++ int flen; ++ struct sk_buff *frag_skb = ieee80211_frag_cache_get(ieee, hdr); ++ IEEE80211_DEBUG_FRAG("Rx Fragment received (%u)\n", frag); ++ ++ if (!frag_skb) { ++ IEEE80211_DEBUG(IEEE80211_DL_RX | IEEE80211_DL_FRAG, ++ "Rx cannot get skb from fragment " ++ "cache (morefrag=%d seq=%u frag=%u)\n", ++ (fc & IEEE80211_FCTL_MOREFRAGS) != 0, ++ WLAN_GET_SEQ_SEQ(sc), frag); ++ goto rx_dropped; ++ } ++ flen = skb->len; ++ if (frag != 0) ++ flen -= hdrlen; ++ ++ if (frag_skb->tail + flen > frag_skb->end) { ++ printk(KERN_WARNING "%s: host decrypted and " ++ "reassembled frame did not fit skb\n", ++ dev->name); ++ ieee80211_frag_cache_invalidate(ieee, hdr); ++ goto rx_dropped; ++ } ++ ++ if (frag == 0) { ++ /* copy first fragment (including full headers) into ++ * beginning of the fragment cache skb */ ++ memcpy(skb_put(frag_skb, flen), skb->data, flen); ++ } else { ++ /* append frame payload to the end of the fragment ++ * cache skb */ ++ memcpy(skb_put(frag_skb, flen), skb->data + hdrlen, ++ flen); ++ } ++ dev_kfree_skb_any(skb); ++ skb = NULL; ++ ++ if (fc & IEEE80211_FCTL_MOREFRAGS) { ++ /* more fragments expected - leave the skb in fragment ++ * cache for now; it will be delivered to upper layers ++ * after all fragments have been received */ ++ goto rx_exit; ++ } ++ ++ /* this was the last fragment and the frame will be ++ * delivered, so remove skb from fragment cache */ ++ skb = frag_skb; ++ hdr = (struct ieee80211_hdr_4addr *) skb->data; ++ ieee80211_frag_cache_invalidate(ieee, hdr); ++ } ++ ++ /* skb: hdr + (possible reassembled) full MSDU payload; possibly still ++ * encrypted/authenticated */ ++ if (ieee->host_decrypt && (fc & IEEE80211_FCTL_WEP) && ++ ieee80211_rx_frame_decrypt_msdu(ieee, skb, keyidx, crypt)) ++ { ++ printk("==>decrypt msdu error\n"); ++ goto rx_dropped; ++ } ++ ++ //added by amy for AP roaming ++ ieee->LinkDetectInfo.NumRecvDataInPeriod++; ++ ieee->LinkDetectInfo.NumRxOkInPeriod++; ++ ++ hdr = (struct ieee80211_hdr_4addr *) skb->data; ++ if (crypt && !(fc & IEEE80211_FCTL_WEP) && !ieee->open_wep) { ++ if (/*ieee->ieee802_1x &&*/ ++ ieee80211_is_eapol_frame(ieee, skb, hdrlen)) { ++ ++#ifdef CONFIG_IEEE80211_DEBUG ++ /* pass unencrypted EAPOL frames even if encryption is ++ * configured */ ++ struct eapol *eap = (struct eapol *)(skb->data + ++ 24); ++ IEEE80211_DEBUG_EAP("RX: IEEE 802.1X EAPOL frame: %s\n", ++ eap_get_type(eap->type)); ++#endif ++ } else { ++ IEEE80211_DEBUG_DROP( ++ "encryption configured, but RX " ++ "frame not encrypted (SA=" MAC_FMT ")\n", ++ MAC_ARG(hdr->addr2)); ++ goto rx_dropped; ++ } ++ } ++ ++#ifdef CONFIG_IEEE80211_DEBUG ++ if (crypt && !(fc & IEEE80211_FCTL_WEP) && ++ ieee80211_is_eapol_frame(ieee, skb, hdrlen)) { ++ struct eapol *eap = (struct eapol *)(skb->data + ++ 24); ++ IEEE80211_DEBUG_EAP("RX: IEEE 802.1X EAPOL frame: %s\n", ++ eap_get_type(eap->type)); ++ } ++#endif ++ ++ if (crypt && !(fc & IEEE80211_FCTL_WEP) && !ieee->open_wep && ++ !ieee80211_is_eapol_frame(ieee, skb, hdrlen)) { ++ IEEE80211_DEBUG_DROP( ++ "dropped unencrypted RX data " ++ "frame from " MAC_FMT ++ " (drop_unencrypted=1)\n", ++ MAC_ARG(hdr->addr2)); ++ goto rx_dropped; ++ } ++/* ++ if(ieee80211_is_eapol_frame(ieee, skb, hdrlen)) { ++ printk(KERN_WARNING "RX: IEEE802.1X EPAOL frame!\n"); ++ } ++*/ ++//added by amy for reorder ++#if 1 ++ if(ieee->current_network.qos_data.active && IsQoSDataFrame(skb->data) ++ && !is_multicast_ether_addr(hdr->addr1) && !is_broadcast_ether_addr(hdr->addr1)) ++ { ++ TID = Frame_QoSTID(skb->data); ++ SeqNum = WLAN_GET_SEQ_SEQ(sc); ++ GetTs(ieee,(PTS_COMMON_INFO*) &pTS,hdr->addr2,TID,RX_DIR,true); ++ if(TID !=0 && TID !=3) ++ { ++ ieee->bis_any_nonbepkts = true; ++ } ++ } ++#endif ++//added by amy for reorder ++ /* skb: hdr + (possible reassembled) full plaintext payload */ ++ payload = skb->data + hdrlen; ++ //ethertype = (payload[6] << 8) | payload[7]; ++ rxb = (struct ieee80211_rxb*)kmalloc(sizeof(struct ieee80211_rxb),GFP_ATOMIC); ++ if(rxb == NULL) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR,"%s(): kmalloc rxb error\n",__FUNCTION__); ++ goto rx_dropped; ++ } ++ /* to parse amsdu packets */ ++ /* qos data packets & reserved bit is 1 */ ++ if(parse_subframe(skb,rx_stats,rxb,src,dst) == 0) { ++ /* only to free rxb, and not submit the packets to upper layer */ ++ for(i =0; i < rxb->nr_subframes; i++) { ++ dev_kfree_skb(rxb->subframes[i]); ++ } ++ kfree(rxb); ++ rxb = NULL; ++ goto rx_dropped; ++ } ++ ++ ieee->last_rx_ps_time = jiffies; ++//added by amy for reorder ++ if(ieee->pHTInfo->bCurRxReorderEnable == false ||pTS == NULL){ ++//added by amy for reorder ++ for(i = 0; inr_subframes; i++) { ++ struct sk_buff *sub_skb = rxb->subframes[i]; ++ ++ if (sub_skb) { ++ /* convert hdr + possible LLC headers into Ethernet header */ ++ ethertype = (sub_skb->data[6] << 8) | sub_skb->data[7]; ++ if (sub_skb->len >= 8 && ++ ((memcmp(sub_skb->data, rfc1042_header, SNAP_SIZE) == 0 && ++ ethertype != ETH_P_AARP && ethertype != ETH_P_IPX) || ++ memcmp(sub_skb->data, bridge_tunnel_header, SNAP_SIZE) == 0)) { ++ /* remove RFC1042 or Bridge-Tunnel encapsulation and ++ * replace EtherType */ ++ skb_pull(sub_skb, SNAP_SIZE); ++ memcpy(skb_push(sub_skb, ETH_ALEN), src, ETH_ALEN); ++ memcpy(skb_push(sub_skb, ETH_ALEN), dst, ETH_ALEN); ++ } else { ++ u16 len; ++ /* Leave Ethernet header part of hdr and full payload */ ++ len = htons(sub_skb->len); ++ memcpy(skb_push(sub_skb, 2), &len, 2); ++ memcpy(skb_push(sub_skb, ETH_ALEN), src, ETH_ALEN); ++ memcpy(skb_push(sub_skb, ETH_ALEN), dst, ETH_ALEN); ++ } ++ ++ stats->rx_packets++; ++ stats->rx_bytes += sub_skb->len; ++ if(is_multicast_ether_addr(dst)) { ++ stats->multicast++; ++ } ++ ++ /* Indicat the packets to upper layer */ ++ //printk("0skb_len(%d)\n", skb->len); ++ sub_skb->protocol = eth_type_trans(sub_skb, dev); ++ memset(sub_skb->cb, 0, sizeof(sub_skb->cb)); ++ sub_skb->dev = dev; ++ sub_skb->ip_summed = CHECKSUM_NONE; /* 802.11 crc not sufficient */ ++ //skb->ip_summed = CHECKSUM_UNNECESSARY; /* 802.11 crc not sufficient */ ++ //printk("1skb_len(%d)\n", skb->len); ++ netif_rx(sub_skb); ++ } ++ } ++ kfree(rxb); ++ rxb = NULL; ++ ++ } ++ else ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): REORDER ENABLE AND PTS not NULL, and we will enter RxReorderIndicatePacket()\n",__FUNCTION__); ++ RxReorderIndicatePacket(ieee, rxb, pTS, SeqNum); ++ } ++#ifndef JOHN_NOCPY ++ dev_kfree_skb(skb); ++#endif ++ ++ rx_exit: ++#ifdef NOT_YET ++ if (sta) ++ hostap_handle_sta_release(sta); ++#endif ++ return 1; ++ ++ rx_dropped: ++ if (rxb != NULL) ++ { ++ kfree(rxb); ++ rxb = NULL; ++ } ++ stats->rx_dropped++; ++ ++ /* Returning 0 indicates to caller that we have not handled the SKB-- ++ * so it is still allocated and can be used again by underlying ++ * hardware as a DMA target */ ++ return 0; ++} ++ ++#define MGMT_FRAME_FIXED_PART_LENGTH 0x24 ++ ++static u8 qos_oui[QOS_OUI_LEN] = { 0x00, 0x50, 0xF2 }; ++ ++/* ++* Make ther structure we read from the beacon packet has ++* the right values ++*/ ++static int ieee80211_verify_qos_info(struct ieee80211_qos_information_element ++ *info_element, int sub_type) ++{ ++ ++ if (info_element->qui_subtype != sub_type) ++ return -1; ++ if (memcmp(info_element->qui, qos_oui, QOS_OUI_LEN)) ++ return -1; ++ if (info_element->qui_type != QOS_OUI_TYPE) ++ return -1; ++ if (info_element->version != QOS_VERSION_1) ++ return -1; ++ ++ return 0; ++} ++ ++ ++/* ++ * Parse a QoS parameter element ++ */ ++static int ieee80211_read_qos_param_element(struct ieee80211_qos_parameter_info ++ *element_param, struct ieee80211_info_element ++ *info_element) ++{ ++ int ret = 0; ++ u16 size = sizeof(struct ieee80211_qos_parameter_info) - 2; ++ ++ if ((info_element == NULL) || (element_param == NULL)) ++ return -1; ++ ++ if (info_element->id == QOS_ELEMENT_ID && info_element->len == size) { ++ memcpy(element_param->info_element.qui, info_element->data, ++ info_element->len); ++ element_param->info_element.elementID = info_element->id; ++ element_param->info_element.length = info_element->len; ++ } else ++ ret = -1; ++ if (ret == 0) ++ ret = ieee80211_verify_qos_info(&element_param->info_element, ++ QOS_OUI_PARAM_SUB_TYPE); ++ return ret; ++} ++ ++/* ++ * Parse a QoS information element ++ */ ++static int ieee80211_read_qos_info_element(struct ++ ieee80211_qos_information_element ++ *element_info, struct ieee80211_info_element ++ *info_element) ++{ ++ int ret = 0; ++ u16 size = sizeof(struct ieee80211_qos_information_element) - 2; ++ ++ if (element_info == NULL) ++ return -1; ++ if (info_element == NULL) ++ return -1; ++ ++ if ((info_element->id == QOS_ELEMENT_ID) && (info_element->len == size)) { ++ memcpy(element_info->qui, info_element->data, ++ info_element->len); ++ element_info->elementID = info_element->id; ++ element_info->length = info_element->len; ++ } else ++ ret = -1; ++ ++ if (ret == 0) ++ ret = ieee80211_verify_qos_info(element_info, ++ QOS_OUI_INFO_SUB_TYPE); ++ return ret; ++} ++ ++ ++/* ++ * Write QoS parameters from the ac parameters. ++ */ ++static int ieee80211_qos_convert_ac_to_parameters(struct ++ ieee80211_qos_parameter_info ++ *param_elm, struct ++ ieee80211_qos_parameters ++ *qos_param) ++{ ++ int rc = 0; ++ int i; ++ struct ieee80211_qos_ac_parameter *ac_params; ++ u8 aci; ++ //u8 cw_min; ++ //u8 cw_max; ++ ++ for (i = 0; i < QOS_QUEUE_NUM; i++) { ++ ac_params = &(param_elm->ac_params_record[i]); ++ ++ aci = (ac_params->aci_aifsn & 0x60) >> 5; ++ ++ if(aci >= QOS_QUEUE_NUM) ++ continue; ++ qos_param->aifs[aci] = (ac_params->aci_aifsn) & 0x0f; ++ ++ /* WMM spec P.11: The minimum value for AIFSN shall be 2 */ ++ qos_param->aifs[aci] = (qos_param->aifs[aci] < 2) ? 2:qos_param->aifs[aci]; ++ ++ qos_param->cw_min[aci] = ac_params->ecw_min_max & 0x0F; ++ ++ qos_param->cw_max[aci] = (ac_params->ecw_min_max & 0xF0) >> 4; ++ ++ qos_param->flag[aci] = ++ (ac_params->aci_aifsn & 0x10) ? 0x01 : 0x00; ++ qos_param->tx_op_limit[aci] = le16_to_cpu(ac_params->tx_op_limit); ++ } ++ return rc; ++} ++ ++/* ++ * we have a generic data element which it may contain QoS information or ++ * parameters element. check the information element length to decide ++ * which type to read ++ */ ++static int ieee80211_parse_qos_info_param_IE(struct ieee80211_info_element ++ *info_element, ++ struct ieee80211_network *network) ++{ ++ int rc = 0; ++ struct ieee80211_qos_parameters *qos_param = NULL; ++ struct ieee80211_qos_information_element qos_info_element; ++ ++ rc = ieee80211_read_qos_info_element(&qos_info_element, info_element); ++ ++ if (rc == 0) { ++ network->qos_data.param_count = qos_info_element.ac_info & 0x0F; ++ network->flags |= NETWORK_HAS_QOS_INFORMATION; ++ } else { ++ struct ieee80211_qos_parameter_info param_element; ++ ++ rc = ieee80211_read_qos_param_element(¶m_element, ++ info_element); ++ if (rc == 0) { ++ qos_param = &(network->qos_data.parameters); ++ ieee80211_qos_convert_ac_to_parameters(¶m_element, ++ qos_param); ++ network->flags |= NETWORK_HAS_QOS_PARAMETERS; ++ network->qos_data.param_count = ++ param_element.info_element.ac_info & 0x0F; ++ } ++ } ++ ++ if (rc == 0) { ++ IEEE80211_DEBUG_QOS("QoS is supported\n"); ++ network->qos_data.supported = 1; ++ } ++ return rc; ++} ++ ++#ifdef CONFIG_IEEE80211_DEBUG ++#define MFIE_STRING(x) case MFIE_TYPE_ ##x: return #x ++ ++static const char *get_info_element_string(u16 id) ++{ ++ switch (id) { ++ MFIE_STRING(SSID); ++ MFIE_STRING(RATES); ++ MFIE_STRING(FH_SET); ++ MFIE_STRING(DS_SET); ++ MFIE_STRING(CF_SET); ++ MFIE_STRING(TIM); ++ MFIE_STRING(IBSS_SET); ++ MFIE_STRING(COUNTRY); ++ MFIE_STRING(HOP_PARAMS); ++ MFIE_STRING(HOP_TABLE); ++ MFIE_STRING(REQUEST); ++ MFIE_STRING(CHALLENGE); ++ MFIE_STRING(POWER_CONSTRAINT); ++ MFIE_STRING(POWER_CAPABILITY); ++ MFIE_STRING(TPC_REQUEST); ++ MFIE_STRING(TPC_REPORT); ++ MFIE_STRING(SUPP_CHANNELS); ++ MFIE_STRING(CSA); ++ MFIE_STRING(MEASURE_REQUEST); ++ MFIE_STRING(MEASURE_REPORT); ++ MFIE_STRING(QUIET); ++ MFIE_STRING(IBSS_DFS); ++ // MFIE_STRING(ERP_INFO); ++ MFIE_STRING(RSN); ++ MFIE_STRING(RATES_EX); ++ MFIE_STRING(GENERIC); ++ MFIE_STRING(QOS_PARAMETER); ++ default: ++ return "UNKNOWN"; ++ } ++} ++#endif ++ ++#ifdef ENABLE_DOT11D ++static inline void ieee80211_extract_country_ie( ++ struct ieee80211_device *ieee, ++ struct ieee80211_info_element *info_element, ++ struct ieee80211_network *network, ++ u8 * addr2 ++) ++{ ++ if(IS_DOT11D_ENABLE(ieee)) ++ { ++ if(info_element->len!= 0) ++ { ++ memcpy(network->CountryIeBuf, info_element->data, info_element->len); ++ network->CountryIeLen = info_element->len; ++ ++ if(!IS_COUNTRY_IE_VALID(ieee)) ++ { ++ Dot11d_UpdateCountryIe(ieee, addr2, info_element->len, info_element->data); ++ } ++ } ++ ++ // ++ // 070305, rcnjko: I update country IE watch dog here because ++ // some AP (e.g. Cisco 1242) don't include country IE in their ++ // probe response frame. ++ // ++ if(IS_EQUAL_CIE_SRC(ieee, addr2) ) ++ { ++ UPDATE_CIE_WATCHDOG(ieee); ++ } ++ } ++ ++} ++#endif ++ ++int ieee80211_parse_info_param(struct ieee80211_device *ieee, ++ struct ieee80211_info_element *info_element, ++ u16 length, ++ struct ieee80211_network *network, ++ struct ieee80211_rx_stats *stats) ++{ ++ u8 i; ++ short offset; ++ u16 tmp_htcap_len=0; ++ u16 tmp_htinfo_len=0; ++ u16 ht_realtek_agg_len=0; ++ u8 ht_realtek_agg_buf[MAX_IE_LEN]; ++// u16 broadcom_len = 0; ++#ifdef CONFIG_IEEE80211_DEBUG ++ char rates_str[64]; ++ char *p; ++#endif ++ ++ while (length >= sizeof(*info_element)) { ++ if (sizeof(*info_element) + info_element->len > length) { ++ IEEE80211_DEBUG_MGMT("Info elem: parse failed: " ++ "info_element->len + 2 > left : " ++ "info_element->len+2=%zd left=%d, id=%d.\n", ++ info_element->len + ++ sizeof(*info_element), ++ length, info_element->id); ++ /* We stop processing but don't return an error here ++ * because some misbehaviour APs break this rule. ie. ++ * Orinoco AP1000. */ ++ break; ++ } ++ ++ switch (info_element->id) { ++ case MFIE_TYPE_SSID: ++ if (ieee80211_is_empty_essid(info_element->data, ++ info_element->len)) { ++ network->flags |= NETWORK_EMPTY_ESSID; ++ break; ++ } ++ ++ network->ssid_len = min(info_element->len, ++ (u8) IW_ESSID_MAX_SIZE); ++ memcpy(network->ssid, info_element->data, network->ssid_len); ++ if (network->ssid_len < IW_ESSID_MAX_SIZE) ++ memset(network->ssid + network->ssid_len, 0, ++ IW_ESSID_MAX_SIZE - network->ssid_len); ++ ++ IEEE80211_DEBUG_MGMT("MFIE_TYPE_SSID: '%s' len=%d.\n", ++ network->ssid, network->ssid_len); ++ break; ++ ++ case MFIE_TYPE_RATES: ++#ifdef CONFIG_IEEE80211_DEBUG ++ p = rates_str; ++#endif ++ network->rates_len = min(info_element->len, ++ MAX_RATES_LENGTH); ++ for (i = 0; i < network->rates_len; i++) { ++ network->rates[i] = info_element->data[i]; ++#ifdef CONFIG_IEEE80211_DEBUG ++ p += snprintf(p, sizeof(rates_str) - ++ (p - rates_str), "%02X ", ++ network->rates[i]); ++#endif ++ if (ieee80211_is_ofdm_rate ++ (info_element->data[i])) { ++ network->flags |= NETWORK_HAS_OFDM; ++ if (info_element->data[i] & ++ IEEE80211_BASIC_RATE_MASK) ++ network->flags &= ++ ~NETWORK_HAS_CCK; ++ } ++ } ++ ++ IEEE80211_DEBUG_MGMT("MFIE_TYPE_RATES: '%s' (%d)\n", ++ rates_str, network->rates_len); ++ break; ++ ++ case MFIE_TYPE_RATES_EX: ++#ifdef CONFIG_IEEE80211_DEBUG ++ p = rates_str; ++#endif ++ network->rates_ex_len = min(info_element->len, ++ MAX_RATES_EX_LENGTH); ++ for (i = 0; i < network->rates_ex_len; i++) { ++ network->rates_ex[i] = info_element->data[i]; ++#ifdef CONFIG_IEEE80211_DEBUG ++ p += snprintf(p, sizeof(rates_str) - ++ (p - rates_str), "%02X ", ++ network->rates[i]); ++#endif ++ if (ieee80211_is_ofdm_rate ++ (info_element->data[i])) { ++ network->flags |= NETWORK_HAS_OFDM; ++ if (info_element->data[i] & ++ IEEE80211_BASIC_RATE_MASK) ++ network->flags &= ++ ~NETWORK_HAS_CCK; ++ } ++ } ++ ++ IEEE80211_DEBUG_MGMT("MFIE_TYPE_RATES_EX: '%s' (%d)\n", ++ rates_str, network->rates_ex_len); ++ break; ++ ++ case MFIE_TYPE_DS_SET: ++ IEEE80211_DEBUG_MGMT("MFIE_TYPE_DS_SET: %d\n", ++ info_element->data[0]); ++ network->channel = info_element->data[0]; ++ break; ++ ++ case MFIE_TYPE_FH_SET: ++ IEEE80211_DEBUG_MGMT("MFIE_TYPE_FH_SET: ignored\n"); ++ break; ++ ++ case MFIE_TYPE_CF_SET: ++ IEEE80211_DEBUG_MGMT("MFIE_TYPE_CF_SET: ignored\n"); ++ break; ++ ++ case MFIE_TYPE_TIM: ++ if(info_element->len < 4) ++ break; ++ ++ network->tim.tim_count = info_element->data[0]; ++ network->tim.tim_period = info_element->data[1]; ++ ++ network->dtim_period = info_element->data[1]; ++ if(ieee->state != IEEE80211_LINKED) ++ break; ++#if 0 ++ network->last_dtim_sta_time[0] = stats->mac_time[0]; ++#else ++ //we use jiffies for legacy Power save ++ network->last_dtim_sta_time[0] = jiffies; ++#endif ++ network->last_dtim_sta_time[1] = stats->mac_time[1]; ++ ++ network->dtim_data = IEEE80211_DTIM_VALID; ++ ++ if(info_element->data[0] != 0) ++ break; ++ ++ if(info_element->data[2] & 1) ++ network->dtim_data |= IEEE80211_DTIM_MBCAST; ++ ++ offset = (info_element->data[2] >> 1)*2; ++ ++ //printk("offset1:%x aid:%x\n",offset, ieee->assoc_id); ++ ++ if(ieee->assoc_id < 8*offset || ++ ieee->assoc_id > 8*(offset + info_element->len -3)) ++ ++ break; ++ ++ offset = (ieee->assoc_id / 8) - offset;// + ((aid % 8)? 0 : 1) ; ++ ++ if(info_element->data[3+offset] & (1<<(ieee->assoc_id%8))) ++ network->dtim_data |= IEEE80211_DTIM_UCAST; ++ ++ //IEEE80211_DEBUG_MGMT("MFIE_TYPE_TIM: partially ignored\n"); ++ break; ++ ++ case MFIE_TYPE_ERP: ++ network->erp_value = info_element->data[0]; ++ network->flags |= NETWORK_HAS_ERP_VALUE; ++ IEEE80211_DEBUG_MGMT("MFIE_TYPE_ERP_SET: %d\n", ++ network->erp_value); ++ break; ++ case MFIE_TYPE_IBSS_SET: ++ network->atim_window = info_element->data[0]; ++ IEEE80211_DEBUG_MGMT("MFIE_TYPE_IBSS_SET: %d\n", ++ network->atim_window); ++ break; ++ ++ case MFIE_TYPE_CHALLENGE: ++ IEEE80211_DEBUG_MGMT("MFIE_TYPE_CHALLENGE: ignored\n"); ++ break; ++ ++ case MFIE_TYPE_GENERIC: ++ IEEE80211_DEBUG_MGMT("MFIE_TYPE_GENERIC: %d bytes\n", ++ info_element->len); ++ if (!ieee80211_parse_qos_info_param_IE(info_element, ++ network)) ++ break; ++ ++ if (info_element->len >= 4 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0x50 && ++ info_element->data[2] == 0xf2 && ++ info_element->data[3] == 0x01) { ++ network->wpa_ie_len = min(info_element->len + 2, ++ MAX_WPA_IE_LEN); ++ memcpy(network->wpa_ie, info_element, ++ network->wpa_ie_len); ++ break; ++ } ++ ++#ifdef THOMAS_TURBO ++ if (info_element->len == 7 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0xe0 && ++ info_element->data[2] == 0x4c && ++ info_element->data[3] == 0x01 && ++ info_element->data[4] == 0x02) { ++ network->Turbo_Enable = 1; ++ } ++#endif ++ ++ //for HTcap and HTinfo parameters ++ if(tmp_htcap_len == 0){ ++ if(info_element->len >= 4 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0x90 && ++ info_element->data[2] == 0x4c && ++ info_element->data[3] == 0x033){ ++ ++ tmp_htcap_len = min(info_element->len,(u8)MAX_IE_LEN); ++ if(tmp_htcap_len != 0){ ++ network->bssht.bdHTSpecVer = HT_SPEC_VER_EWC; ++ network->bssht.bdHTCapLen = tmp_htcap_len > sizeof(network->bssht.bdHTCapBuf)?\ ++ sizeof(network->bssht.bdHTCapBuf):tmp_htcap_len; ++ memcpy(network->bssht.bdHTCapBuf,info_element->data,network->bssht.bdHTCapLen); ++ } ++ } ++ if(tmp_htcap_len != 0) ++ network->bssht.bdSupportHT = true; ++ else ++ network->bssht.bdSupportHT = false; ++ } ++ ++ ++ if(tmp_htinfo_len == 0){ ++ if(info_element->len >= 4 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0x90 && ++ info_element->data[2] == 0x4c && ++ info_element->data[3] == 0x034){ ++ ++ tmp_htinfo_len = min(info_element->len,(u8)MAX_IE_LEN); ++ if(tmp_htinfo_len != 0){ ++ network->bssht.bdHTSpecVer = HT_SPEC_VER_EWC; ++ if(tmp_htinfo_len){ ++ network->bssht.bdHTInfoLen = tmp_htinfo_len > sizeof(network->bssht.bdHTInfoBuf)?\ ++ sizeof(network->bssht.bdHTInfoBuf):tmp_htinfo_len; ++ memcpy(network->bssht.bdHTInfoBuf,info_element->data,network->bssht.bdHTInfoLen); ++ } ++ ++ } ++ ++ } ++ } ++ ++ if(ieee->aggregation){ ++ if(network->bssht.bdSupportHT){ ++ if(info_element->len >= 4 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0xe0 && ++ info_element->data[2] == 0x4c && ++ info_element->data[3] == 0x02){ ++ ++ ht_realtek_agg_len = min(info_element->len,(u8)MAX_IE_LEN); ++ memcpy(ht_realtek_agg_buf,info_element->data,info_element->len); ++ ++ } ++ if(ht_realtek_agg_len >= 5){ ++ network->bssht.bdRT2RTAggregation = true; ++ ++ if((ht_realtek_agg_buf[4] == 1) && (ht_realtek_agg_buf[5] & 0x02)) ++ network->bssht.bdRT2RTLongSlotTime = true; ++ } ++ } ++ ++ } ++ ++ //if(tmp_htcap_len !=0 || tmp_htinfo_len != 0) ++ { ++ if((info_element->len >= 3 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0x05 && ++ info_element->data[2] == 0xb5) || ++ (info_element->len >= 3 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0x0a && ++ info_element->data[2] == 0xf7) || ++ (info_element->len >= 3 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0x10 && ++ info_element->data[2] == 0x18)){ ++ ++ network->broadcom_cap_exist = true; ++ ++ } ++ } ++#if 0 ++ if (tmp_htcap_len !=0) ++ { ++ u16 cap_ext = ((PHT_CAPABILITY_ELE)&info_element->data[0])->ExtHTCapInfo; ++ if ((cap_ext & 0x0c00) == 0x0c00) ++ { ++ network->ralink_cap_exist = true; ++ } ++ } ++#endif ++ if(info_element->len >= 3 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0x0c && ++ info_element->data[2] == 0x43) ++ { ++ network->ralink_cap_exist = true; ++ } ++ else ++ network->ralink_cap_exist = false; ++ //added by amy for atheros AP ++ if((info_element->len >= 3 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0x03 && ++ info_element->data[2] == 0x7f) || ++ (info_element->len >= 3 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0x13 && ++ info_element->data[2] == 0x74)) ++ { ++ printk("========>%s(): athros AP is exist\n",__FUNCTION__); ++ network->atheros_cap_exist = true; ++ } ++ else ++ network->atheros_cap_exist = false; ++ ++ if(info_element->len >= 3 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0x40 && ++ info_element->data[2] == 0x96) ++ { ++ network->cisco_cap_exist = true; ++ } ++ else ++ network->cisco_cap_exist = false; ++ //added by amy for LEAP of cisco ++ if(info_element->len > 4 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0x40 && ++ info_element->data[2] == 0x96 && ++ info_element->data[3] == 0x01) ++ { ++ if(info_element->len == 6) ++ { ++ memcpy(network->CcxRmState, &info_element[4], 2); ++ if(network->CcxRmState[0] != 0) ++ { ++ network->bCcxRmEnable = true; ++ } ++ else ++ network->bCcxRmEnable = false; ++ // ++ // CCXv4 Table 59-1 MBSSID Masks. ++ // ++ network->MBssidMask = network->CcxRmState[1] & 0x07; ++ if(network->MBssidMask != 0) ++ { ++ network->bMBssidValid = true; ++ network->MBssidMask = 0xff << (network->MBssidMask); ++ cpMacAddr(network->MBssid, network->bssid); ++ network->MBssid[5] &= network->MBssidMask; ++ } ++ else ++ { ++ network->bMBssidValid = false; ++ } ++ } ++ else ++ { ++ network->bCcxRmEnable = false; ++ } ++ } ++ if(info_element->len > 4 && ++ info_element->data[0] == 0x00 && ++ info_element->data[1] == 0x40 && ++ info_element->data[2] == 0x96 && ++ info_element->data[3] == 0x03) ++ { ++ if(info_element->len == 5) ++ { ++ network->bWithCcxVerNum = true; ++ network->BssCcxVerNumber = info_element->data[4]; ++ } ++ else ++ { ++ network->bWithCcxVerNum = false; ++ network->BssCcxVerNumber = 0; ++ } ++ } ++ break; ++ ++ case MFIE_TYPE_RSN: ++ IEEE80211_DEBUG_MGMT("MFIE_TYPE_RSN: %d bytes\n", ++ info_element->len); ++ network->rsn_ie_len = min(info_element->len + 2, ++ MAX_WPA_IE_LEN); ++ memcpy(network->rsn_ie, info_element, ++ network->rsn_ie_len); ++ break; ++ ++ //HT related element. ++ case MFIE_TYPE_HT_CAP: ++ IEEE80211_DEBUG_SCAN("MFIE_TYPE_HT_CAP: %d bytes\n", ++ info_element->len); ++ tmp_htcap_len = min(info_element->len,(u8)MAX_IE_LEN); ++ if(tmp_htcap_len != 0){ ++ network->bssht.bdHTSpecVer = HT_SPEC_VER_EWC; ++ network->bssht.bdHTCapLen = tmp_htcap_len > sizeof(network->bssht.bdHTCapBuf)?\ ++ sizeof(network->bssht.bdHTCapBuf):tmp_htcap_len; ++ memcpy(network->bssht.bdHTCapBuf,info_element->data,network->bssht.bdHTCapLen); ++ ++ //If peer is HT, but not WMM, call QosSetLegacyWMMParamWithHT() ++ // windows driver will update WMM parameters each beacon received once connected ++ // Linux driver is a bit different. ++ network->bssht.bdSupportHT = true; ++ } ++ else ++ network->bssht.bdSupportHT = false; ++ break; ++ ++ ++ case MFIE_TYPE_HT_INFO: ++ IEEE80211_DEBUG_SCAN("MFIE_TYPE_HT_INFO: %d bytes\n", ++ info_element->len); ++ tmp_htinfo_len = min(info_element->len,(u8)MAX_IE_LEN); ++ if(tmp_htinfo_len){ ++ network->bssht.bdHTSpecVer = HT_SPEC_VER_IEEE; ++ network->bssht.bdHTInfoLen = tmp_htinfo_len > sizeof(network->bssht.bdHTInfoBuf)?\ ++ sizeof(network->bssht.bdHTInfoBuf):tmp_htinfo_len; ++ memcpy(network->bssht.bdHTInfoBuf,info_element->data,network->bssht.bdHTInfoLen); ++ } ++ break; ++ ++ case MFIE_TYPE_AIRONET: ++ IEEE80211_DEBUG_SCAN("MFIE_TYPE_AIRONET: %d bytes\n", ++ info_element->len); ++ if(info_element->len >IE_CISCO_FLAG_POSITION) ++ { ++ network->bWithAironetIE = true; ++ ++ // CCX 1 spec v1.13, A01.1 CKIP Negotiation (page23): ++ // "A Cisco access point advertises support for CKIP in beacon and probe response packets, ++ // by adding an Aironet element and setting one or both of the CKIP negotiation bits." ++ if( (info_element->data[IE_CISCO_FLAG_POSITION]&SUPPORT_CKIP_MIC) || ++ (info_element->data[IE_CISCO_FLAG_POSITION]&SUPPORT_CKIP_PK) ) ++ { ++ network->bCkipSupported = true; ++ } ++ else ++ { ++ network->bCkipSupported = false; ++ } ++ } ++ else ++ { ++ network->bWithAironetIE = false; ++ network->bCkipSupported = false; ++ } ++ break; ++ case MFIE_TYPE_QOS_PARAMETER: ++ printk(KERN_ERR ++ "QoS Error need to parse QOS_PARAMETER IE\n"); ++ break; ++ ++#ifdef ENABLE_DOT11D ++ case MFIE_TYPE_COUNTRY: ++ IEEE80211_DEBUG_SCAN("MFIE_TYPE_COUNTRY: %d bytes\n", ++ info_element->len); ++ //printk("=====>Receive <%s> Country IE\n",network->ssid); ++ ieee80211_extract_country_ie(ieee, info_element, network, network->bssid);//addr2 is same as addr3 when from an AP ++ break; ++#endif ++/* TODO */ ++#if 0 ++ /* 802.11h */ ++ case MFIE_TYPE_POWER_CONSTRAINT: ++ network->power_constraint = info_element->data[0]; ++ network->flags |= NETWORK_HAS_POWER_CONSTRAINT; ++ break; ++ ++ case MFIE_TYPE_CSA: ++ network->power_constraint = info_element->data[0]; ++ network->flags |= NETWORK_HAS_CSA; ++ break; ++ ++ case MFIE_TYPE_QUIET: ++ network->quiet.count = info_element->data[0]; ++ network->quiet.period = info_element->data[1]; ++ network->quiet.duration = info_element->data[2]; ++ network->quiet.offset = info_element->data[3]; ++ network->flags |= NETWORK_HAS_QUIET; ++ break; ++ ++ case MFIE_TYPE_IBSS_DFS: ++ if (network->ibss_dfs) ++ break; ++ network->ibss_dfs = kmemdup(info_element->data, ++ info_element->len, ++ GFP_ATOMIC); ++ if (!network->ibss_dfs) ++ return 1; ++ network->flags |= NETWORK_HAS_IBSS_DFS; ++ break; ++ ++ case MFIE_TYPE_TPC_REPORT: ++ network->tpc_report.transmit_power = ++ info_element->data[0]; ++ network->tpc_report.link_margin = info_element->data[1]; ++ network->flags |= NETWORK_HAS_TPC_REPORT; ++ break; ++#endif ++ default: ++ IEEE80211_DEBUG_MGMT ++ ("Unsupported info element: %s (%d)\n", ++ get_info_element_string(info_element->id), ++ info_element->id); ++ break; ++ } ++ ++ length -= sizeof(*info_element) + info_element->len; ++ info_element = ++ (struct ieee80211_info_element *)&info_element-> ++ data[info_element->len]; ++ } ++ ++ if(!network->atheros_cap_exist && !network->broadcom_cap_exist && ++ !network->cisco_cap_exist && !network->ralink_cap_exist && !network->bssht.bdRT2RTAggregation) ++ { ++ network->unknown_cap_exist = true; ++ } ++ else ++ { ++ network->unknown_cap_exist = false; ++ } ++ return 0; ++} ++ ++static inline u8 ieee80211_SignalStrengthTranslate( ++ u8 CurrSS ++ ) ++{ ++ u8 RetSS; ++ ++ // Step 1. Scale mapping. ++ if(CurrSS >= 71 && CurrSS <= 100) ++ { ++ RetSS = 90 + ((CurrSS - 70) / 3); ++ } ++ else if(CurrSS >= 41 && CurrSS <= 70) ++ { ++ RetSS = 78 + ((CurrSS - 40) / 3); ++ } ++ else if(CurrSS >= 31 && CurrSS <= 40) ++ { ++ RetSS = 66 + (CurrSS - 30); ++ } ++ else if(CurrSS >= 21 && CurrSS <= 30) ++ { ++ RetSS = 54 + (CurrSS - 20); ++ } ++ else if(CurrSS >= 5 && CurrSS <= 20) ++ { ++ RetSS = 42 + (((CurrSS - 5) * 2) / 3); ++ } ++ else if(CurrSS == 4) ++ { ++ RetSS = 36; ++ } ++ else if(CurrSS == 3) ++ { ++ RetSS = 27; ++ } ++ else if(CurrSS == 2) ++ { ++ RetSS = 18; ++ } ++ else if(CurrSS == 1) ++ { ++ RetSS = 9; ++ } ++ else ++ { ++ RetSS = CurrSS; ++ } ++ //RT_TRACE(COMP_DBG, DBG_LOUD, ("##### After Mapping: LastSS: %d, CurrSS: %d, RetSS: %d\n", LastSS, CurrSS, RetSS)); ++ ++ // Step 2. Smoothing. ++ ++ //RT_TRACE(COMP_DBG, DBG_LOUD, ("$$$$$ After Smoothing: LastSS: %d, CurrSS: %d, RetSS: %d\n", LastSS, CurrSS, RetSS)); ++ ++ return RetSS; ++} ++ ++long ieee80211_translate_todbm(u8 signal_strength_index )// 0-100 index. ++{ ++ long signal_power; // in dBm. ++ ++ // Translate to dBm (x=0.5y-95). ++ signal_power = (long)((signal_strength_index + 1) >> 1); ++ signal_power -= 95; ++ ++ return signal_power; ++} ++ ++static inline int ieee80211_network_init( ++ struct ieee80211_device *ieee, ++ struct ieee80211_probe_response *beacon, ++ struct ieee80211_network *network, ++ struct ieee80211_rx_stats *stats) ++{ ++#ifdef CONFIG_IEEE80211_DEBUG ++ //char rates_str[64]; ++ //char *p; ++#endif ++ ++ network->qos_data.active = 0; ++ network->qos_data.supported = 0; ++ network->qos_data.param_count = 0; ++ network->qos_data.old_param_count = 0; ++ ++ /* Pull out fixed field data */ ++ memcpy(network->bssid, beacon->header.addr3, ETH_ALEN); ++ network->capability = le16_to_cpu(beacon->capability); ++ network->last_scanned = jiffies; ++ network->time_stamp[0] = le32_to_cpu(beacon->time_stamp[0]); ++ network->time_stamp[1] = le32_to_cpu(beacon->time_stamp[1]); ++ network->beacon_interval = le32_to_cpu(beacon->beacon_interval); ++ /* Where to pull this? beacon->listen_interval;*/ ++ network->listen_interval = 0x0A; ++ network->rates_len = network->rates_ex_len = 0; ++ network->last_associate = 0; ++ network->ssid_len = 0; ++ network->flags = 0; ++ network->atim_window = 0; ++ network->erp_value = (network->capability & WLAN_CAPABILITY_IBSS) ? ++ 0x3 : 0x0; ++ network->berp_info_valid = false; ++ network->broadcom_cap_exist = false; ++ network->ralink_cap_exist = false; ++ network->atheros_cap_exist = false; ++ network->cisco_cap_exist = false; ++ network->unknown_cap_exist = false; ++#ifdef THOMAS_TURBO ++ network->Turbo_Enable = 0; ++#endif ++#ifdef ENABLE_DOT11D ++ network->CountryIeLen = 0; ++ memset(network->CountryIeBuf, 0, MAX_IE_LEN); ++#endif ++//Initialize HT parameters ++ //ieee80211_ht_initialize(&network->bssht); ++ HTInitializeBssDesc(&network->bssht); ++ if (stats->freq == IEEE80211_52GHZ_BAND) { ++ /* for A band (No DS info) */ ++ network->channel = stats->received_channel; ++ } else ++ network->flags |= NETWORK_HAS_CCK; ++ ++ network->wpa_ie_len = 0; ++ network->rsn_ie_len = 0; ++ ++ if (ieee80211_parse_info_param ++ (ieee,beacon->info_element, stats->len - sizeof(*beacon), network, stats)) ++ return 1; ++ ++ network->mode = 0; ++ if (stats->freq == IEEE80211_52GHZ_BAND) ++ network->mode = IEEE_A; ++ else { ++ if (network->flags & NETWORK_HAS_OFDM) ++ network->mode |= IEEE_G; ++ if (network->flags & NETWORK_HAS_CCK) ++ network->mode |= IEEE_B; ++ } ++ ++ if (network->mode == 0) { ++ IEEE80211_DEBUG_SCAN("Filtered out '%s (" MAC_FMT ")' " ++ "network.\n", ++ escape_essid(network->ssid, ++ network->ssid_len), ++ MAC_ARG(network->bssid)); ++ return 1; ++ } ++ ++ if(network->bssht.bdSupportHT){ ++ if(network->mode == IEEE_A) ++ network->mode = IEEE_N_5G; ++ else if(network->mode & (IEEE_G | IEEE_B)) ++ network->mode = IEEE_N_24G; ++ } ++ if (ieee80211_is_empty_essid(network->ssid, network->ssid_len)) ++ network->flags |= NETWORK_EMPTY_ESSID; ++ ++#if 1 ++ stats->signal = 30 + (stats->SignalStrength * 70) / 100; ++ //stats->signal = ieee80211_SignalStrengthTranslate(stats->signal); ++ stats->noise = ieee80211_translate_todbm((u8)(100-stats->signal)) -25; ++#endif ++ ++ memcpy(&network->stats, stats, sizeof(network->stats)); ++ ++ return 0; ++} ++ ++static inline int is_same_network(struct ieee80211_network *src, ++ struct ieee80211_network *dst, struct ieee80211_device* ieee) ++{ ++ /* A network is only a duplicate if the channel, BSSID, ESSID ++ * and the capability field (in particular IBSS and BSS) all match. ++ * We treat all with the same BSSID and channel ++ * as one network */ ++ return //((src->ssid_len == dst->ssid_len) && ++ (((src->ssid_len == dst->ssid_len) || (ieee->iw_mode == IW_MODE_INFRA)) && ++ (src->channel == dst->channel) && ++ !memcmp(src->bssid, dst->bssid, ETH_ALEN) && ++ //!memcmp(src->ssid, dst->ssid, src->ssid_len) && ++ (!memcmp(src->ssid, dst->ssid, src->ssid_len) || (ieee->iw_mode == IW_MODE_INFRA)) && ++ ((src->capability & WLAN_CAPABILITY_IBSS) == ++ (dst->capability & WLAN_CAPABILITY_IBSS)) && ++ ((src->capability & WLAN_CAPABILITY_BSS) == ++ (dst->capability & WLAN_CAPABILITY_BSS))); ++} ++ ++static inline void update_network(struct ieee80211_network *dst, ++ struct ieee80211_network *src) ++{ ++ int qos_active; ++ u8 old_param; ++ ++ memcpy(&dst->stats, &src->stats, sizeof(struct ieee80211_rx_stats)); ++ dst->capability = src->capability; ++ memcpy(dst->rates, src->rates, src->rates_len); ++ dst->rates_len = src->rates_len; ++ memcpy(dst->rates_ex, src->rates_ex, src->rates_ex_len); ++ dst->rates_ex_len = src->rates_ex_len; ++ if(src->ssid_len > 0) ++ { ++ memset(dst->ssid, 0, dst->ssid_len); ++ dst->ssid_len = src->ssid_len; ++ memcpy(dst->ssid, src->ssid, src->ssid_len); ++ } ++ dst->mode = src->mode; ++ dst->flags = src->flags; ++ dst->time_stamp[0] = src->time_stamp[0]; ++ dst->time_stamp[1] = src->time_stamp[1]; ++ if (src->flags & NETWORK_HAS_ERP_VALUE) ++ { ++ dst->erp_value = src->erp_value; ++ dst->berp_info_valid = src->berp_info_valid = true; ++ } ++ dst->beacon_interval = src->beacon_interval; ++ dst->listen_interval = src->listen_interval; ++ dst->atim_window = src->atim_window; ++ dst->dtim_period = src->dtim_period; ++ dst->dtim_data = src->dtim_data; ++ dst->last_dtim_sta_time[0] = src->last_dtim_sta_time[0]; ++ dst->last_dtim_sta_time[1] = src->last_dtim_sta_time[1]; ++ memcpy(&dst->tim, &src->tim, sizeof(struct ieee80211_tim_parameters)); ++ ++ dst->bssht.bdSupportHT = src->bssht.bdSupportHT; ++ dst->bssht.bdRT2RTAggregation = src->bssht.bdRT2RTAggregation; ++ dst->bssht.bdHTCapLen= src->bssht.bdHTCapLen; ++ memcpy(dst->bssht.bdHTCapBuf,src->bssht.bdHTCapBuf,src->bssht.bdHTCapLen); ++ dst->bssht.bdHTInfoLen= src->bssht.bdHTInfoLen; ++ memcpy(dst->bssht.bdHTInfoBuf,src->bssht.bdHTInfoBuf,src->bssht.bdHTInfoLen); ++ dst->bssht.bdHTSpecVer = src->bssht.bdHTSpecVer; ++ dst->bssht.bdRT2RTLongSlotTime = src->bssht.bdRT2RTLongSlotTime; ++ dst->broadcom_cap_exist = src->broadcom_cap_exist; ++ dst->ralink_cap_exist = src->ralink_cap_exist; ++ dst->atheros_cap_exist = src->atheros_cap_exist; ++ dst->cisco_cap_exist = src->cisco_cap_exist; ++ dst->unknown_cap_exist = src->unknown_cap_exist; ++ memcpy(dst->wpa_ie, src->wpa_ie, src->wpa_ie_len); ++ dst->wpa_ie_len = src->wpa_ie_len; ++ memcpy(dst->rsn_ie, src->rsn_ie, src->rsn_ie_len); ++ dst->rsn_ie_len = src->rsn_ie_len; ++ ++ dst->last_scanned = jiffies; ++ /* qos related parameters */ ++ //qos_active = src->qos_data.active; ++ qos_active = dst->qos_data.active; ++ //old_param = dst->qos_data.old_param_count; ++ old_param = dst->qos_data.param_count; ++ if(dst->flags & NETWORK_HAS_QOS_MASK){ ++ //not update QOS paramter in beacon, as most AP will set all these parameter to 0.//WB ++ // printk("====>%s(), aifs:%x, %x\n", __FUNCTION__, dst->qos_data.parameters.aifs[0], src->qos_data.parameters.aifs[0]); ++ // memcpy(&dst->qos_data, &src->qos_data, ++ // sizeof(struct ieee80211_qos_data)); ++ } ++ else { ++ dst->qos_data.supported = src->qos_data.supported; ++ dst->qos_data.param_count = src->qos_data.param_count; ++ } ++ ++ if(dst->qos_data.supported == 1) { ++ dst->QoS_Enable = 1; ++ if(dst->ssid_len) ++ IEEE80211_DEBUG_QOS ++ ("QoS the network %s is QoS supported\n", ++ dst->ssid); ++ else ++ IEEE80211_DEBUG_QOS ++ ("QoS the network is QoS supported\n"); ++ } ++ dst->qos_data.active = qos_active; ++ dst->qos_data.old_param_count = old_param; ++ ++ /* dst->last_associate is not overwritten */ ++#if 1 ++ dst->wmm_info = src->wmm_info; //sure to exist in beacon or probe response frame. ++ if(src->wmm_param[0].ac_aci_acm_aifsn|| \ ++ src->wmm_param[1].ac_aci_acm_aifsn|| \ ++ src->wmm_param[2].ac_aci_acm_aifsn|| \ ++ src->wmm_param[1].ac_aci_acm_aifsn) { ++ memcpy(dst->wmm_param, src->wmm_param, WME_AC_PRAM_LEN); ++ } ++ //dst->QoS_Enable = src->QoS_Enable; ++#else ++ dst->QoS_Enable = 1;//for Rtl8187 simulation ++#endif ++#ifdef THOMAS_TURBO ++ dst->Turbo_Enable = src->Turbo_Enable; ++#endif ++ ++#ifdef ENABLE_DOT11D ++ dst->CountryIeLen = src->CountryIeLen; ++ memcpy(dst->CountryIeBuf, src->CountryIeBuf, src->CountryIeLen); ++#endif ++ ++ //added by amy for LEAP ++ dst->bWithAironetIE = src->bWithAironetIE; ++ dst->bCkipSupported = src->bCkipSupported; ++ memcpy(dst->CcxRmState,src->CcxRmState,2); ++ dst->bCcxRmEnable = src->bCcxRmEnable; ++ dst->MBssidMask = src->MBssidMask; ++ dst->bMBssidValid = src->bMBssidValid; ++ memcpy(dst->MBssid,src->MBssid,6); ++ dst->bWithCcxVerNum = src->bWithCcxVerNum; ++ dst->BssCcxVerNumber = src->BssCcxVerNumber; ++ ++} ++ ++static inline int is_beacon(__le16 fc) ++{ ++ return (WLAN_FC_GET_STYPE(le16_to_cpu(fc)) == IEEE80211_STYPE_BEACON); ++} ++ ++static inline void ieee80211_process_probe_response( ++ struct ieee80211_device *ieee, ++ struct ieee80211_probe_response *beacon, ++ struct ieee80211_rx_stats *stats) ++{ ++ struct ieee80211_network network; ++ struct ieee80211_network *target; ++ struct ieee80211_network *oldest = NULL; ++#ifdef CONFIG_IEEE80211_DEBUG ++ struct ieee80211_info_element *info_element = &beacon->info_element[0]; ++#endif ++ unsigned long flags; ++ short renew; ++ //u8 wmm_info; ++ ++ memset(&network, 0, sizeof(struct ieee80211_network)); ++ IEEE80211_DEBUG_SCAN( ++ "'%s' (" MAC_FMT "): %c%c%c%c %c%c%c%c-%c%c%c%c %c%c%c%c\n", ++ escape_essid(info_element->data, info_element->len), ++ MAC_ARG(beacon->header.addr3), ++ (beacon->capability & (1<<0xf)) ? '1' : '0', ++ (beacon->capability & (1<<0xe)) ? '1' : '0', ++ (beacon->capability & (1<<0xd)) ? '1' : '0', ++ (beacon->capability & (1<<0xc)) ? '1' : '0', ++ (beacon->capability & (1<<0xb)) ? '1' : '0', ++ (beacon->capability & (1<<0xa)) ? '1' : '0', ++ (beacon->capability & (1<<0x9)) ? '1' : '0', ++ (beacon->capability & (1<<0x8)) ? '1' : '0', ++ (beacon->capability & (1<<0x7)) ? '1' : '0', ++ (beacon->capability & (1<<0x6)) ? '1' : '0', ++ (beacon->capability & (1<<0x5)) ? '1' : '0', ++ (beacon->capability & (1<<0x4)) ? '1' : '0', ++ (beacon->capability & (1<<0x3)) ? '1' : '0', ++ (beacon->capability & (1<<0x2)) ? '1' : '0', ++ (beacon->capability & (1<<0x1)) ? '1' : '0', ++ (beacon->capability & (1<<0x0)) ? '1' : '0'); ++ ++ if (ieee80211_network_init(ieee, beacon, &network, stats)) { ++ IEEE80211_DEBUG_SCAN("Dropped '%s' (" MAC_FMT ") via %s.\n", ++ escape_essid(info_element->data, ++ info_element->len), ++ MAC_ARG(beacon->header.addr3), ++ WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == ++ IEEE80211_STYPE_PROBE_RESP ? ++ "PROBE RESPONSE" : "BEACON"); ++ return; ++ } ++ ++#ifdef ENABLE_DOT11D ++ // For Asus EeePc request, ++ // (1) if wireless adapter receive get any 802.11d country code in AP beacon, ++ // wireless adapter should follow the country code. ++ // (2) If there is no any country code in beacon, ++ // then wireless adapter should do active scan from ch1~11 and ++ // passive scan from ch12~14 ++ ++ if( !IsLegalChannel(ieee, network.channel) ) ++ return; ++ if(ieee->bGlobalDomain) ++ { ++ if (WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP) ++ { ++ // Case 1: Country code ++ if(IS_COUNTRY_IE_VALID(ieee) ) ++ { ++ if( !IsLegalChannel(ieee, network.channel) ) ++ { ++ printk("GetScanInfo(): For Country code, filter probe response at channel(%d).\n", network.channel); ++ return; ++ } ++ } ++ // Case 2: No any country code. ++ else ++ { ++ // Filter over channel ch12~14 ++ if(network.channel > 11) ++ { ++ printk("GetScanInfo(): For Global Domain, filter probe response at channel(%d).\n", network.channel); ++ return; ++ } ++ } ++ } ++ else ++ { ++ // Case 1: Country code ++ if(IS_COUNTRY_IE_VALID(ieee) ) ++ { ++ if( !IsLegalChannel(ieee, network.channel) ) ++ { ++ printk("GetScanInfo(): For Country code, filter beacon at channel(%d).\n",network.channel); ++ return; ++ } ++ } ++ // Case 2: No any country code. ++ else ++ { ++ // Filter over channel ch12~14 ++ if(network.channel > 14) ++ { ++ printk("GetScanInfo(): For Global Domain, filter beacon at channel(%d).\n",network.channel); ++ return; ++ } ++ } ++ } ++ } ++#endif ++ ++ /* The network parsed correctly -- so now we scan our known networks ++ * to see if we can find it in our list. ++ * ++ * NOTE: This search is definitely not optimized. Once its doing ++ * the "right thing" we'll optimize it for efficiency if ++ * necessary */ ++ ++ /* Search for this entry in the list and update it if it is ++ * already there. */ ++ ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ if(is_same_network(&ieee->current_network, &network, ieee)) { ++ update_network(&ieee->current_network, &network); ++ if((ieee->current_network.mode == IEEE_N_24G || ieee->current_network.mode == IEEE_G) ++ && ieee->current_network.berp_info_valid){ ++ if(ieee->current_network.erp_value& ERP_UseProtection) ++ ieee->current_network.buseprotection = true; ++ else ++ ieee->current_network.buseprotection = false; ++ } ++ if(is_beacon(beacon->header.frame_ctl)) ++ { ++ if(ieee->state == IEEE80211_LINKED) ++ ieee->LinkDetectInfo.NumRecvBcnInPeriod++; ++ } ++ else //hidden AP ++ network.flags = (~NETWORK_EMPTY_ESSID & network.flags)|(NETWORK_EMPTY_ESSID & ieee->current_network.flags); ++ } ++ ++ list_for_each_entry(target, &ieee->network_list, list) { ++ if (is_same_network(target, &network, ieee)) ++ break; ++ if ((oldest == NULL) || ++ (target->last_scanned < oldest->last_scanned)) ++ oldest = target; ++ } ++ ++ /* If we didn't find a match, then get a new network slot to initialize ++ * with this beacon's information */ ++ if (&target->list == &ieee->network_list) { ++ if (list_empty(&ieee->network_free_list)) { ++ /* If there are no more slots, expire the oldest */ ++ list_del(&oldest->list); ++ target = oldest; ++ IEEE80211_DEBUG_SCAN("Expired '%s' (" MAC_FMT ") from " ++ "network list.\n", ++ escape_essid(target->ssid, ++ target->ssid_len), ++ MAC_ARG(target->bssid)); ++ } else { ++ /* Otherwise just pull from the free list */ ++ target = list_entry(ieee->network_free_list.next, ++ struct ieee80211_network, list); ++ list_del(ieee->network_free_list.next); ++ } ++ ++ ++#ifdef CONFIG_IEEE80211_DEBUG ++ IEEE80211_DEBUG_SCAN("Adding '%s' (" MAC_FMT ") via %s.\n", ++ escape_essid(network.ssid, ++ network.ssid_len), ++ MAC_ARG(network.bssid), ++ WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == ++ IEEE80211_STYPE_PROBE_RESP ? ++ "PROBE RESPONSE" : "BEACON"); ++#endif ++ memcpy(target, &network, sizeof(*target)); ++ list_add_tail(&target->list, &ieee->network_list); ++ if(ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) ++ ieee80211_softmac_new_net(ieee,&network); ++ } else { ++ IEEE80211_DEBUG_SCAN("Updating '%s' (" MAC_FMT ") via %s.\n", ++ escape_essid(target->ssid, ++ target->ssid_len), ++ MAC_ARG(target->bssid), ++ WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == ++ IEEE80211_STYPE_PROBE_RESP ? ++ "PROBE RESPONSE" : "BEACON"); ++ ++ /* we have an entry and we are going to update it. But this entry may ++ * be already expired. In this case we do the same as we found a new ++ * net and call the new_net handler ++ */ ++ renew = !time_after(target->last_scanned + ieee->scan_age, jiffies); ++ //YJ,add,080819,for hidden ap ++ if(is_beacon(beacon->header.frame_ctl) == 0) ++ network.flags = (~NETWORK_EMPTY_ESSID & network.flags)|(NETWORK_EMPTY_ESSID & target->flags); ++ //if(strncmp(network.ssid, "linksys-c",9) == 0) ++ // printk("====>2 network.ssid=%s FLAG=%d target.ssid=%s FLAG=%d\n", network.ssid, network.flags, target->ssid, target->flags); ++ if(((network.flags & NETWORK_EMPTY_ESSID) == NETWORK_EMPTY_ESSID) \ ++ && (((network.ssid_len > 0) && (strncmp(target->ssid, network.ssid, network.ssid_len)))\ ++ ||((ieee->current_network.ssid_len == network.ssid_len)&&(strncmp(ieee->current_network.ssid, network.ssid, network.ssid_len) == 0)&&(ieee->state == IEEE80211_NOLINK)))) ++ renew = 1; ++ //YJ,add,080819,for hidden ap,end ++ ++ update_network(target, &network); ++ if(renew && (ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE)) ++ ieee80211_softmac_new_net(ieee,&network); ++ } ++ ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ if (is_beacon(beacon->header.frame_ctl)&&is_same_network(&ieee->current_network, &network, ieee)&&\ ++ (ieee->state == IEEE80211_LINKED)) { ++ if(ieee->handle_beacon != NULL) { ++ ieee->handle_beacon(ieee->dev,beacon,&ieee->current_network); ++ } ++ } ++} ++ ++void ieee80211_rx_mgt(struct ieee80211_device *ieee, ++ struct ieee80211_hdr_4addr *header, ++ struct ieee80211_rx_stats *stats) ++{ ++ if(ieee->sta_sleep || (ieee->ps != IEEE80211_PS_DISABLED && ++ ieee->iw_mode == IW_MODE_INFRA && ++ ieee->state == IEEE80211_LINKED)) ++ { ++ tasklet_schedule(&ieee->ps_task); ++ } ++ ++ if(WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_PROBE_RESP && ++ WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_BEACON) ++ ieee->last_rx_ps_time = jiffies; ++ ++ switch (WLAN_FC_GET_STYPE(header->frame_ctl)) { ++ ++ case IEEE80211_STYPE_BEACON: ++ IEEE80211_DEBUG_MGMT("received BEACON (%d)\n", ++ WLAN_FC_GET_STYPE(header->frame_ctl)); ++ IEEE80211_DEBUG_SCAN("Beacon\n"); ++ ieee80211_process_probe_response( ++ ieee, (struct ieee80211_probe_response *)header, stats); ++ break; ++ ++ case IEEE80211_STYPE_PROBE_RESP: ++ IEEE80211_DEBUG_MGMT("received PROBE RESPONSE (%d)\n", ++ WLAN_FC_GET_STYPE(header->frame_ctl)); ++ IEEE80211_DEBUG_SCAN("Probe response\n"); ++ ieee80211_process_probe_response( ++ ieee, (struct ieee80211_probe_response *)header, stats); ++ break; ++ ++ } ++} ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++//EXPORT_SYMBOL(ieee80211_rx_mgt); ++//EXPORT_SYMBOL(ieee80211_rx); ++#else ++EXPORT_SYMBOL_NOVERS(ieee80211_rx_mgt); ++EXPORT_SYMBOL_NOVERS(ieee80211_rx); ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,3548 @@ ++/* IEEE 802.11 SoftMAC layer ++ * Copyright (c) 2005 Andrea Merello ++ * ++ * Mostly extracted from the rtl8180-sa2400 driver for the ++ * in-kernel generic ieee802.11 stack. ++ * ++ * Few lines might be stolen from other part of the ieee80211 ++ * stack. Copyright who own it's copyright ++ * ++ * WPA code stolen from the ipw2200 driver. ++ * Copyright who own it's copyright. ++ * ++ * released under the GPL ++ */ ++ ++ ++#include "ieee80211.h" ++ ++#include ++#include ++#include ++#include ++#ifdef ENABLE_DOT11D ++#include "dot11d.h" ++#endif ++ ++u8 rsn_authen_cipher_suite[16][4] = { ++ {0x00,0x0F,0xAC,0x00}, //Use group key, //Reserved ++ {0x00,0x0F,0xAC,0x01}, //WEP-40 //RSNA default ++ {0x00,0x0F,0xAC,0x02}, //TKIP //NONE //{used just as default} ++ {0x00,0x0F,0xAC,0x03}, //WRAP-historical ++ {0x00,0x0F,0xAC,0x04}, //CCMP ++ {0x00,0x0F,0xAC,0x05}, //WEP-104 ++}; ++ ++short ieee80211_is_54g(struct ieee80211_network net) ++{ ++ return ((net.rates_ex_len > 0) || (net.rates_len > 4)); ++} ++ ++short ieee80211_is_shortslot(struct ieee80211_network net) ++{ ++ return (net.capability & WLAN_CAPABILITY_SHORT_SLOT); ++} ++ ++/* returns the total length needed for pleacing the RATE MFIE ++ * tag and the EXTENDED RATE MFIE tag if needed. ++ * It encludes two bytes per tag for the tag itself and its len ++ */ ++unsigned int ieee80211_MFIE_rate_len(struct ieee80211_device *ieee) ++{ ++ unsigned int rate_len = 0; ++ ++ if (ieee->modulation & IEEE80211_CCK_MODULATION) ++ rate_len = IEEE80211_CCK_RATE_LEN + 2; ++ ++ if (ieee->modulation & IEEE80211_OFDM_MODULATION) ++ ++ rate_len += IEEE80211_OFDM_RATE_LEN + 2; ++ ++ return rate_len; ++} ++ ++/* pleace the MFIE rate, tag to the memory (double) poined. ++ * Then it updates the pointer so that ++ * it points after the new MFIE tag added. ++ */ ++void ieee80211_MFIE_Brate(struct ieee80211_device *ieee, u8 **tag_p) ++{ ++ u8 *tag = *tag_p; ++ ++ if (ieee->modulation & IEEE80211_CCK_MODULATION){ ++ *tag++ = MFIE_TYPE_RATES; ++ *tag++ = 4; ++ *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_1MB; ++ *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_2MB; ++ *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_5MB; ++ *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_11MB; ++ } ++ ++ /* We may add an option for custom rates that specific HW might support */ ++ *tag_p = tag; ++} ++ ++void ieee80211_MFIE_Grate(struct ieee80211_device *ieee, u8 **tag_p) ++{ ++ u8 *tag = *tag_p; ++ ++ if (ieee->modulation & IEEE80211_OFDM_MODULATION){ ++ ++ *tag++ = MFIE_TYPE_RATES_EX; ++ *tag++ = 8; ++ *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_6MB; ++ *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_9MB; ++ *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_12MB; ++ *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_18MB; ++ *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_24MB; ++ *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_36MB; ++ *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_48MB; ++ *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_54MB; ++ ++ } ++ ++ /* We may add an option for custom rates that specific HW might support */ ++ *tag_p = tag; ++} ++ ++ ++void ieee80211_WMM_Info(struct ieee80211_device *ieee, u8 **tag_p) { ++ u8 *tag = *tag_p; ++ ++ *tag++ = MFIE_TYPE_GENERIC; //0 ++ *tag++ = 7; ++ *tag++ = 0x00; ++ *tag++ = 0x50; ++ *tag++ = 0xf2; ++ *tag++ = 0x02;//5 ++ *tag++ = 0x00; ++ *tag++ = 0x01; ++#ifdef SUPPORT_USPD ++ if(ieee->current_network.wmm_info & 0x80) { ++ *tag++ = 0x0f|MAX_SP_Len; ++ } else { ++ *tag++ = MAX_SP_Len; ++ } ++#else ++ *tag++ = MAX_SP_Len; ++#endif ++ *tag_p = tag; ++} ++ ++#ifdef THOMAS_TURBO ++void ieee80211_TURBO_Info(struct ieee80211_device *ieee, u8 **tag_p) { ++ u8 *tag = *tag_p; ++ ++ *tag++ = MFIE_TYPE_GENERIC; //0 ++ *tag++ = 7; ++ *tag++ = 0x00; ++ *tag++ = 0xe0; ++ *tag++ = 0x4c; ++ *tag++ = 0x01;//5 ++ *tag++ = 0x02; ++ *tag++ = 0x11; ++ *tag++ = 0x00; ++ ++ *tag_p = tag; ++ printk(KERN_ALERT "This is enable turbo mode IE process\n"); ++} ++#endif ++ ++void enqueue_mgmt(struct ieee80211_device *ieee, struct sk_buff *skb) ++{ ++ int nh; ++ nh = (ieee->mgmt_queue_head +1) % MGMT_QUEUE_NUM; ++ ++/* ++ * if the queue is full but we have newer frames then ++ * just overwrites the oldest. ++ * ++ * if (nh == ieee->mgmt_queue_tail) ++ * return -1; ++ */ ++ ieee->mgmt_queue_head = nh; ++ ieee->mgmt_queue_ring[nh] = skb; ++ ++ //return 0; ++} ++ ++struct sk_buff *dequeue_mgmt(struct ieee80211_device *ieee) ++{ ++ struct sk_buff *ret; ++ ++ if(ieee->mgmt_queue_tail == ieee->mgmt_queue_head) ++ return NULL; ++ ++ ret = ieee->mgmt_queue_ring[ieee->mgmt_queue_tail]; ++ ++ ieee->mgmt_queue_tail = ++ (ieee->mgmt_queue_tail+1) % MGMT_QUEUE_NUM; ++ ++ return ret; ++} ++ ++void init_mgmt_queue(struct ieee80211_device *ieee) ++{ ++ ieee->mgmt_queue_tail = ieee->mgmt_queue_head = 0; ++} ++ ++u8 MgntQuery_MgntFrameTxRate(struct ieee80211_device *ieee) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ u8 rate; ++ ++ // 2008/01/25 MH For broadcom, MGNT frame set as OFDM 6M. ++ if(pHTInfo->IOTAction & HT_IOT_ACT_MGNT_USE_CCK_6M) ++ rate = 0x0c; ++ else ++ rate = ieee->basic_rate & 0x7f; ++ ++ if(rate == 0){ ++ // 2005.01.26, by rcnjko. ++ if(ieee->mode == IEEE_A|| ++ ieee->mode== IEEE_N_5G|| ++ (ieee->mode== IEEE_N_24G&&!pHTInfo->bCurSuppCCK)) ++ rate = 0x0c; ++ else ++ rate = 0x02; ++ } ++ ++ /* ++ // Data rate of ProbeReq is already decided. Annie, 2005-03-31 ++ if( pMgntInfo->bScanInProgress || (pMgntInfo->bDualModeScanStep!=0) ) ++ { ++ if(pMgntInfo->dot11CurrentWirelessMode==WIRELESS_MODE_A) ++ rate = 0x0c; ++ else ++ rate = 0x02; ++ } ++ */ ++ return rate; ++} ++ ++ ++void ieee80211_sta_wakeup(struct ieee80211_device *ieee, short nl); ++ ++inline void softmac_mgmt_xmit(struct sk_buff *skb, struct ieee80211_device *ieee) ++{ ++ unsigned long flags; ++ short single = ieee->softmac_features & IEEE_SOFTMAC_SINGLE_QUEUE; ++ struct ieee80211_hdr_3addr *header= ++ (struct ieee80211_hdr_3addr *) skb->data; ++ ++ cb_desc *tcb_desc = (cb_desc *)(skb->cb + 8); ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ /* called with 2nd param 0, no mgmt lock required */ ++ ieee80211_sta_wakeup(ieee,0); ++ ++ tcb_desc->queue_index = MGNT_QUEUE; ++ tcb_desc->data_rate = MgntQuery_MgntFrameTxRate(ieee); ++ tcb_desc->RATRIndex = 7; ++ tcb_desc->bTxDisableRateFallBack = 1; ++ tcb_desc->bTxUseDriverAssingedRate = 1; ++ ++ if(single){ ++ if(ieee->queue_stop){ ++ enqueue_mgmt(ieee,skb); ++ }else{ ++ header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0]<<4); ++ ++ if (ieee->seq_ctrl[0] == 0xFFF) ++ ieee->seq_ctrl[0] = 0; ++ else ++ ieee->seq_ctrl[0]++; ++ ++ /* avoid watchdog triggers */ ++ // ieee->dev->trans_start = jiffies; ++ ieee->softmac_data_hard_start_xmit(skb,ieee->dev,ieee->basic_rate); ++ //dev_kfree_skb_any(skb);//edit by thomas ++ } ++ ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ }else{ ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ spin_lock_irqsave(&ieee->mgmt_tx_lock, flags); ++ ++ header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4); ++ ++ if (ieee->seq_ctrl[0] == 0xFFF) ++ ieee->seq_ctrl[0] = 0; ++ else ++ ieee->seq_ctrl[0]++; ++ ++ /* check wether the managed packet queued greater than 5 */ ++ if(!ieee->check_nic_enough_desc(ieee->dev,tcb_desc->queue_index)||\ ++ (skb_queue_len(&ieee->skb_waitQ[tcb_desc->queue_index]) != 0)||\ ++ (ieee->queue_stop) ) { ++ /* insert the skb packet to the management queue */ ++ /* as for the completion function, it does not need ++ * to check it any more. ++ * */ ++ printk("%s():insert to waitqueue!\n",__FUNCTION__); ++ skb_queue_tail(&ieee->skb_waitQ[tcb_desc->queue_index], skb); ++ } else { ++ //printk("TX packet!\n"); ++ ieee->softmac_hard_start_xmit(skb,ieee->dev); ++ //dev_kfree_skb_any(skb);//edit by thomas ++ } ++ spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags); ++ } ++} ++ ++inline void softmac_ps_mgmt_xmit(struct sk_buff *skb, struct ieee80211_device *ieee) ++{ ++ ++ short single = ieee->softmac_features & IEEE_SOFTMAC_SINGLE_QUEUE; ++ struct ieee80211_hdr_3addr *header = ++ (struct ieee80211_hdr_3addr *) skb->data; ++ cb_desc *tcb_desc = (cb_desc *)(skb->cb + 8); ++ ++ tcb_desc->queue_index = MGNT_QUEUE; ++ tcb_desc->data_rate = MgntQuery_MgntFrameTxRate(ieee); ++ tcb_desc->RATRIndex = 7; ++ tcb_desc->bTxDisableRateFallBack = 1; ++ tcb_desc->bTxUseDriverAssingedRate = 1; ++ //printk("=============>%s()\n", __FUNCTION__); ++ if(single){ ++ ++ header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4); ++ ++ if (ieee->seq_ctrl[0] == 0xFFF) ++ ieee->seq_ctrl[0] = 0; ++ else ++ ieee->seq_ctrl[0]++; ++ ++ /* avoid watchdog triggers */ ++ // ieee->dev->trans_start = jiffies; ++ ieee->softmac_data_hard_start_xmit(skb,ieee->dev,ieee->basic_rate); ++ ++ }else{ ++ ++ header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4); ++ ++ if (ieee->seq_ctrl[0] == 0xFFF) ++ ieee->seq_ctrl[0] = 0; ++ else ++ ieee->seq_ctrl[0]++; ++ ++ ieee->softmac_hard_start_xmit(skb,ieee->dev); ++ ++ } ++ //dev_kfree_skb_any(skb);//edit by thomas ++} ++ ++inline struct sk_buff *ieee80211_probe_req(struct ieee80211_device *ieee) ++{ ++ unsigned int len,rate_len; ++ u8 *tag; ++ struct sk_buff *skb; ++ struct ieee80211_probe_request *req; ++ ++ len = ieee->current_network.ssid_len; ++ ++ rate_len = ieee80211_MFIE_rate_len(ieee); ++ ++ skb = dev_alloc_skb(sizeof(struct ieee80211_probe_request) + ++ 2 + len + rate_len + ieee->tx_headroom); ++ if (!skb) ++ return NULL; ++ ++ skb_reserve(skb, ieee->tx_headroom); ++ ++ req = (struct ieee80211_probe_request *) skb_put(skb,sizeof(struct ieee80211_probe_request)); ++ req->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ); ++ req->header.duration_id = 0; //FIXME: is this OK ? ++ ++ memset(req->header.addr1, 0xff, ETH_ALEN); ++ memcpy(req->header.addr2, ieee->dev->dev_addr, ETH_ALEN); ++ memset(req->header.addr3, 0xff, ETH_ALEN); ++ ++ tag = (u8 *) skb_put(skb,len+2+rate_len); ++ ++ *tag++ = MFIE_TYPE_SSID; ++ *tag++ = len; ++ memcpy(tag, ieee->current_network.ssid, len); ++ tag += len; ++ ++ ieee80211_MFIE_Brate(ieee,&tag); ++ ieee80211_MFIE_Grate(ieee,&tag); ++ return skb; ++} ++ ++struct sk_buff *ieee80211_get_beacon_(struct ieee80211_device *ieee); ++void ieee80211_send_beacon(struct ieee80211_device *ieee) ++{ ++ struct sk_buff *skb; ++ if(!ieee->ieee_up) ++ return; ++ //unsigned long flags; ++ skb = ieee80211_get_beacon_(ieee); ++ ++ if (skb){ ++ softmac_mgmt_xmit(skb, ieee); ++ ieee->softmac_stats.tx_beacons++; ++ //dev_kfree_skb_any(skb);//edit by thomas ++ } ++// ieee->beacon_timer.expires = jiffies + ++// (MSECS( ieee->current_network.beacon_interval -5)); ++ ++ //spin_lock_irqsave(&ieee->beacon_lock,flags); ++ if(ieee->beacon_txing && ieee->ieee_up){ ++// if(!timer_pending(&ieee->beacon_timer)) ++// add_timer(&ieee->beacon_timer); ++ mod_timer(&ieee->beacon_timer,jiffies+(MSECS(ieee->current_network.beacon_interval-5))); ++ } ++ //spin_unlock_irqrestore(&ieee->beacon_lock,flags); ++} ++ ++ ++void ieee80211_send_beacon_cb(unsigned long _ieee) ++{ ++ struct ieee80211_device *ieee = ++ (struct ieee80211_device *) _ieee; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ieee->beacon_lock, flags); ++ ieee80211_send_beacon(ieee); ++ spin_unlock_irqrestore(&ieee->beacon_lock, flags); ++} ++ ++ ++void ieee80211_send_probe(struct ieee80211_device *ieee) ++{ ++ struct sk_buff *skb; ++ ++ skb = ieee80211_probe_req(ieee); ++ if (skb){ ++ softmac_mgmt_xmit(skb, ieee); ++ ieee->softmac_stats.tx_probe_rq++; ++ //dev_kfree_skb_any(skb);//edit by thomas ++ } ++} ++ ++void ieee80211_send_probe_requests(struct ieee80211_device *ieee) ++{ ++ if (ieee->active_scan && (ieee->softmac_features & IEEE_SOFTMAC_PROBERQ)){ ++ ieee80211_send_probe(ieee); ++ ieee80211_send_probe(ieee); ++ } ++} ++ ++/* this performs syncro scan blocking the caller until all channels ++ * in the allowed channel map has been checked. ++ */ ++void ieee80211_softmac_scan_syncro(struct ieee80211_device *ieee) ++{ ++ short ch = 0; ++#ifdef ENABLE_DOT11D ++ u8 channel_map[MAX_CHANNEL_NUMBER+1]; ++ memcpy(channel_map, GET_DOT11D_INFO(ieee)->channel_map, MAX_CHANNEL_NUMBER+1); ++#endif ++ down(&ieee->scan_sem); ++ ++ while(1) ++ { ++ ++ do{ ++ ch++; ++ if (ch > MAX_CHANNEL_NUMBER) ++ goto out; /* scan completed */ ++#ifdef ENABLE_DOT11D ++ }while(!channel_map[ch]); ++#else ++ }while(!ieee->channel_map[ch]); ++#endif ++ ++ /* this fuction can be called in two situations ++ * 1- We have switched to ad-hoc mode and we are ++ * performing a complete syncro scan before conclude ++ * there are no interesting cell and to create a ++ * new one. In this case the link state is ++ * IEEE80211_NOLINK until we found an interesting cell. ++ * If so the ieee8021_new_net, called by the RX path ++ * will set the state to IEEE80211_LINKED, so we stop ++ * scanning ++ * 2- We are linked and the root uses run iwlist scan. ++ * So we switch to IEEE80211_LINKED_SCANNING to remember ++ * that we are still logically linked (not interested in ++ * new network events, despite for updating the net list, ++ * but we are temporarly 'unlinked' as the driver shall ++ * not filter RX frames and the channel is changing. ++ * So the only situation in witch are interested is to check ++ * if the state become LINKED because of the #1 situation ++ */ ++ ++ if (ieee->state == IEEE80211_LINKED) ++ goto out; ++ ieee->set_chan(ieee->dev, ch); ++#ifdef ENABLE_DOT11D ++ if(channel_map[ch] == 1) ++#endif ++ ieee80211_send_probe_requests(ieee); ++ ++ /* this prevent excessive time wait when we ++ * need to wait for a syncro scan to end.. ++ */ ++ if(ieee->state < IEEE80211_LINKED) ++ ; ++ else ++ if (ieee->sync_scan_hurryup) ++ goto out; ++ ++ ++ msleep_interruptible_rsl(IEEE80211_SOFTMAC_SCAN_TIME); ++ ++ } ++out: ++ if(ieee->state < IEEE80211_LINKED){ ++ ieee->actscanning = false; ++ up(&ieee->scan_sem); ++ } ++ else{ ++ ieee->sync_scan_hurryup = 0; ++#ifdef ENABLE_DOT11D ++ if(IS_DOT11D_ENABLE(ieee)) ++ DOT11D_ScanComplete(ieee); ++#endif ++ up(&ieee->scan_sem); ++} ++} ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++/* called both by wq with ieee->lock held */ ++void ieee80211_softmac_scan(struct ieee80211_device *ieee) ++{ ++#if 0 ++ short watchdog = 0; ++ do{ ++ ieee->current_network.channel = ++ (ieee->current_network.channel + 1) % MAX_CHANNEL_NUMBER; ++ if (watchdog++ > MAX_CHANNEL_NUMBER) ++ return; /* no good chans */ ++ ++ }while(!ieee->channel_map[ieee->current_network.channel]); ++#endif ++ ++ schedule_task(&ieee->softmac_scan_wq); ++} ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void ieee80211_softmac_scan_wq(struct work_struct *work) ++{ ++ struct delayed_work *dwork = container_of(work, struct delayed_work, work); ++ struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, softmac_scan_wq); ++#else ++void ieee80211_softmac_scan_wq(struct ieee80211_device *ieee) ++{ ++#endif ++ static short watchdog = 0; ++ u8 last_channel = ieee->current_network.channel; ++#ifdef ENABLE_DOT11D ++ u8 channel_map[MAX_CHANNEL_NUMBER+1]; ++ memcpy(channel_map, GET_DOT11D_INFO(ieee)->channel_map, MAX_CHANNEL_NUMBER+1); ++#endif ++ if(!ieee->ieee_up) ++ return; ++ down(&ieee->scan_sem); ++ do{ ++ ieee->current_network.channel = ++ (ieee->current_network.channel + 1) % MAX_CHANNEL_NUMBER; ++ if (watchdog++ > MAX_CHANNEL_NUMBER) ++ { ++ //if current channel is not in channel map, set to default channel. ++ #ifdef ENABLE_DOT11D ++ if (!channel_map[ieee->current_network.channel]); ++ #else ++ if (!ieee->channel_map[ieee->current_network.channel]); ++ #endif ++ ieee->current_network.channel = 6; ++ goto out; /* no good chans */ ++ } ++#ifdef ENABLE_DOT11D ++ }while(!channel_map[ieee->current_network.channel]); ++#else ++ }while(!ieee->channel_map[ieee->current_network.channel]); ++#endif ++ if (ieee->scanning == 0 ) ++ goto out; ++ ieee->set_chan(ieee->dev, ieee->current_network.channel); ++#ifdef ENABLE_DOT11D ++ if(channel_map[ieee->current_network.channel] == 1) ++#endif ++ ieee80211_send_probe_requests(ieee); ++ ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ queue_delayed_work(ieee->wq, &ieee->softmac_scan_wq, IEEE80211_SOFTMAC_SCAN_TIME); ++#else ++ //ieee->scan_timer.expires = jiffies + MSECS(IEEE80211_SOFTMAC_SCAN_TIME); ++ if (ieee->scanning == 1) ++ mod_timer(&ieee->scan_timer,(jiffies + MSECS(IEEE80211_SOFTMAC_SCAN_TIME))); ++#endif ++ ++ up(&ieee->scan_sem); ++ return; ++out: ++#ifdef ENABLE_DOT11D ++ if(IS_DOT11D_ENABLE(ieee)) ++ DOT11D_ScanComplete(ieee); ++#endif ++ ieee->current_network.channel = last_channel; ++ ieee->actscanning = false; ++ watchdog = 0; ++ ieee->scanning = 0; ++ up(&ieee->scan_sem); ++} ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++void ieee80211_softmac_scan_cb(unsigned long _dev) ++{ ++ unsigned long flags; ++ struct ieee80211_device *ieee = (struct ieee80211_device *)_dev; ++ ++ spin_lock_irqsave(&ieee->lock, flags); ++ ieee80211_softmac_scan(ieee); ++ spin_unlock_irqrestore(&ieee->lock, flags); ++} ++#endif ++ ++ ++void ieee80211_beacons_start(struct ieee80211_device *ieee) ++{ ++ unsigned long flags; ++ spin_lock_irqsave(&ieee->beacon_lock,flags); ++ ++ ieee->beacon_txing = 1; ++ ieee80211_send_beacon(ieee); ++ ++ spin_unlock_irqrestore(&ieee->beacon_lock,flags); ++} ++ ++void ieee80211_beacons_stop(struct ieee80211_device *ieee) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ieee->beacon_lock,flags); ++ ++ ieee->beacon_txing = 0; ++ del_timer_sync(&ieee->beacon_timer); ++ ++ spin_unlock_irqrestore(&ieee->beacon_lock,flags); ++ ++} ++ ++ ++void ieee80211_stop_send_beacons(struct ieee80211_device *ieee) ++{ ++ if(ieee->stop_send_beacons) ++ ieee->stop_send_beacons(ieee->dev); ++ if (ieee->softmac_features & IEEE_SOFTMAC_BEACONS) ++ ieee80211_beacons_stop(ieee); ++} ++ ++ ++void ieee80211_start_send_beacons(struct ieee80211_device *ieee) ++{ ++ if(ieee->start_send_beacons) ++ ieee->start_send_beacons(ieee->dev,ieee->basic_rate); ++ if(ieee->softmac_features & IEEE_SOFTMAC_BEACONS) ++ ieee80211_beacons_start(ieee); ++} ++ ++ ++void ieee80211_softmac_stop_scan(struct ieee80211_device *ieee) ++{ ++// unsigned long flags; ++ ++ //ieee->sync_scan_hurryup = 1; ++ ++ down(&ieee->scan_sem); ++// spin_lock_irqsave(&ieee->lock, flags); ++ ++ if (ieee->scanning == 1){ ++ ieee->scanning = 0; ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ cancel_delayed_work(&ieee->softmac_scan_wq); ++#else ++ del_timer_sync(&ieee->scan_timer); ++#endif ++ } ++ ++// spin_unlock_irqrestore(&ieee->lock, flags); ++ up(&ieee->scan_sem); ++} ++ ++void ieee80211_stop_scan(struct ieee80211_device *ieee) ++{ ++ if (ieee->softmac_features & IEEE_SOFTMAC_SCAN) ++ ieee80211_softmac_stop_scan(ieee); ++ else ++ ieee->stop_scan(ieee->dev); ++} ++ ++/* called with ieee->lock held */ ++void ieee80211_start_scan(struct ieee80211_device *ieee) ++{ ++#ifdef ENABLE_DOT11D ++ if(IS_DOT11D_ENABLE(ieee) ) ++ { ++ if(IS_COUNTRY_IE_VALID(ieee)) ++ { ++ RESET_CIE_WATCHDOG(ieee); ++ } ++ } ++#endif ++ if (ieee->softmac_features & IEEE_SOFTMAC_SCAN){ ++ if (ieee->scanning == 0){ ++ ieee->scanning = 1; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ queue_delayed_work(ieee->wq, &ieee->softmac_scan_wq, 0); ++#else ++ ++ queue_work(ieee->wq, &ieee->softmac_scan_wq); ++#endif ++#else ++ ieee80211_softmac_scan(ieee); ++#endif ++ } ++ }else ++ ieee->start_scan(ieee->dev); ++ ++} ++ ++/* called with wx_sem held */ ++void ieee80211_start_scan_syncro(struct ieee80211_device *ieee) ++{ ++#ifdef ENABLE_DOT11D ++ if(IS_DOT11D_ENABLE(ieee) ) ++ { ++ if(IS_COUNTRY_IE_VALID(ieee)) ++ { ++ RESET_CIE_WATCHDOG(ieee); ++ } ++ } ++#endif ++ ieee->sync_scan_hurryup = 0; ++ if (ieee->softmac_features & IEEE_SOFTMAC_SCAN) ++ ieee80211_softmac_scan_syncro(ieee); ++ else ++ ieee->scan_syncro(ieee->dev); ++ ++} ++ ++inline struct sk_buff *ieee80211_authentication_req(struct ieee80211_network *beacon, ++ struct ieee80211_device *ieee, int challengelen) ++{ ++ struct sk_buff *skb; ++ struct ieee80211_authentication *auth; ++ int len = sizeof(struct ieee80211_authentication) + challengelen + ieee->tx_headroom; ++ ++ ++ skb = dev_alloc_skb(len); ++ if (!skb) return NULL; ++ ++ skb_reserve(skb, ieee->tx_headroom); ++ auth = (struct ieee80211_authentication *) ++ skb_put(skb, sizeof(struct ieee80211_authentication)); ++ ++ auth->header.frame_ctl = IEEE80211_STYPE_AUTH; ++ if (challengelen) auth->header.frame_ctl |= IEEE80211_FCTL_WEP; ++ ++ auth->header.duration_id = 0x013a; //FIXME ++ ++ memcpy(auth->header.addr1, beacon->bssid, ETH_ALEN); ++ memcpy(auth->header.addr2, ieee->dev->dev_addr, ETH_ALEN); ++ memcpy(auth->header.addr3, beacon->bssid, ETH_ALEN); ++ ++ //auth->algorithm = ieee->open_wep ? WLAN_AUTH_OPEN : WLAN_AUTH_SHARED_KEY; ++ if(ieee->auth_mode == 0) ++ auth->algorithm = WLAN_AUTH_OPEN; ++ else if(ieee->auth_mode == 1) ++ auth->algorithm = WLAN_AUTH_SHARED_KEY; ++ else if(ieee->auth_mode == 2) ++ auth->algorithm = WLAN_AUTH_OPEN;//0x80; ++ printk("=================>%s():auth->algorithm is %d\n",__FUNCTION__,auth->algorithm); ++ auth->transaction = cpu_to_le16(ieee->associate_seq); ++ ieee->associate_seq++; ++ ++ auth->status = cpu_to_le16(WLAN_STATUS_SUCCESS); ++ ++ return skb; ++ ++} ++ ++ ++static struct sk_buff* ieee80211_probe_resp(struct ieee80211_device *ieee, u8 *dest) ++{ ++ u8 *tag; ++ int beacon_size; ++ struct ieee80211_probe_response *beacon_buf; ++ struct sk_buff *skb = NULL; ++ int encrypt; ++ int atim_len,erp_len; ++ struct ieee80211_crypt_data* crypt; ++ ++ char *ssid = ieee->current_network.ssid; ++ int ssid_len = ieee->current_network.ssid_len; ++ int rate_len = ieee->current_network.rates_len+2; ++ int rate_ex_len = ieee->current_network.rates_ex_len; ++ int wpa_ie_len = ieee->wpa_ie_len; ++ u8 erpinfo_content = 0; ++ ++ u8* tmp_ht_cap_buf; ++ u8 tmp_ht_cap_len=0; ++ u8* tmp_ht_info_buf; ++ u8 tmp_ht_info_len=0; ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ u8* tmp_generic_ie_buf=NULL; ++ u8 tmp_generic_ie_len=0; ++ ++ if(rate_ex_len > 0) rate_ex_len+=2; ++ ++ if(ieee->current_network.capability & WLAN_CAPABILITY_IBSS) ++ atim_len = 4; ++ else ++ atim_len = 0; ++ ++#if 1 ++ if(ieee80211_is_54g(ieee->current_network)) ++ erp_len = 3; ++ else ++ erp_len = 0; ++#else ++ if((ieee->current_network.mode == IEEE_G) ++ ||( ieee->current_network.mode == IEEE_N_24G && ieee->pHTInfo->bCurSuppCCK)) { ++ erp_len = 3; ++ erpinfo_content = 0; ++ if(ieee->current_network.buseprotection) ++ erpinfo_content |= ERP_UseProtection; ++ } ++ else ++ erp_len = 0; ++#endif ++ ++ ++ crypt = ieee->crypt[ieee->tx_keyidx]; ++ ++ ++ encrypt = ieee->host_encrypt && crypt && crypt->ops && ++ ((0 == strcmp(crypt->ops->name, "WEP") || wpa_ie_len)); ++ //HT ralated element ++#if 1 ++ tmp_ht_cap_buf =(u8*) &(ieee->pHTInfo->SelfHTCap); ++ tmp_ht_cap_len = sizeof(ieee->pHTInfo->SelfHTCap); ++ tmp_ht_info_buf =(u8*) &(ieee->pHTInfo->SelfHTInfo); ++ tmp_ht_info_len = sizeof(ieee->pHTInfo->SelfHTInfo); ++ HTConstructCapabilityElement(ieee, tmp_ht_cap_buf, &tmp_ht_cap_len,encrypt); ++ HTConstructInfoElement(ieee,tmp_ht_info_buf,&tmp_ht_info_len, encrypt); ++ ++ ++ if(pHTInfo->bRegRT2RTAggregation) ++ { ++ tmp_generic_ie_buf = ieee->pHTInfo->szRT2RTAggBuffer; ++ tmp_generic_ie_len = sizeof(ieee->pHTInfo->szRT2RTAggBuffer); ++ HTConstructRT2RTAggElement(ieee, tmp_generic_ie_buf, &tmp_generic_ie_len); ++ } ++// printk("===============>tmp_ht_cap_len is %d,tmp_ht_info_len is %d, tmp_generic_ie_len is %d\n",tmp_ht_cap_len,tmp_ht_info_len,tmp_generic_ie_len); ++#endif ++ beacon_size = sizeof(struct ieee80211_probe_response)+2+ ++ ssid_len ++ +3 //channel ++ +rate_len ++ +rate_ex_len ++ +atim_len ++ +erp_len ++ +wpa_ie_len ++ // +tmp_ht_cap_len ++ // +tmp_ht_info_len ++ // +tmp_generic_ie_len ++// +wmm_len+2 ++ +ieee->tx_headroom; ++ skb = dev_alloc_skb(beacon_size); ++ if (!skb) ++ return NULL; ++ skb_reserve(skb, ieee->tx_headroom); ++ beacon_buf = (struct ieee80211_probe_response*) skb_put(skb, (beacon_size - ieee->tx_headroom)); ++ memcpy (beacon_buf->header.addr1, dest,ETH_ALEN); ++ memcpy (beacon_buf->header.addr2, ieee->dev->dev_addr, ETH_ALEN); ++ memcpy (beacon_buf->header.addr3, ieee->current_network.bssid, ETH_ALEN); ++ ++ beacon_buf->header.duration_id = 0; //FIXME ++ beacon_buf->beacon_interval = ++ cpu_to_le16(ieee->current_network.beacon_interval); ++ beacon_buf->capability = ++ cpu_to_le16(ieee->current_network.capability & WLAN_CAPABILITY_IBSS); ++ beacon_buf->capability |= ++ cpu_to_le16(ieee->current_network.capability & WLAN_CAPABILITY_SHORT_PREAMBLE); //add short preamble here ++ ++ if(ieee->short_slot && (ieee->current_network.capability & WLAN_CAPABILITY_SHORT_SLOT)) ++ cpu_to_le16((beacon_buf->capability |= WLAN_CAPABILITY_SHORT_SLOT)); ++ ++ crypt = ieee->crypt[ieee->tx_keyidx]; ++#if 0 ++ encrypt = ieee->host_encrypt && crypt && crypt->ops && ++ (0 == strcmp(crypt->ops->name, "WEP")); ++#endif ++ if (encrypt) ++ beacon_buf->capability |= cpu_to_le16(WLAN_CAPABILITY_PRIVACY); ++ ++ ++ beacon_buf->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_PROBE_RESP); ++ beacon_buf->info_element[0].id = MFIE_TYPE_SSID; ++ beacon_buf->info_element[0].len = ssid_len; ++ ++ tag = (u8*) beacon_buf->info_element[0].data; ++ ++ memcpy(tag, ssid, ssid_len); ++ ++ tag += ssid_len; ++ ++ *(tag++) = MFIE_TYPE_RATES; ++ *(tag++) = rate_len-2; ++ memcpy(tag,ieee->current_network.rates,rate_len-2); ++ tag+=rate_len-2; ++ ++ *(tag++) = MFIE_TYPE_DS_SET; ++ *(tag++) = 1; ++ *(tag++) = ieee->current_network.channel; ++ ++ if(atim_len){ ++ u16 val16; ++ *(tag++) = MFIE_TYPE_IBSS_SET; ++ *(tag++) = 2; ++ //*((u16*)(tag)) = cpu_to_le16(ieee->current_network.atim_window); ++ val16 = cpu_to_le16(ieee->current_network.atim_window); ++ memcpy((u8 *)tag, (u8 *)&val16, 2); ++ tag+=2; ++ } ++ ++ if(erp_len){ ++ *(tag++) = MFIE_TYPE_ERP; ++ *(tag++) = 1; ++ *(tag++) = erpinfo_content; ++ } ++#if 0 ++ //Include High Throuput capability ++ ++ *(tag++) = MFIE_TYPE_HT_CAP; ++ *(tag++) = tmp_ht_cap_len - 2; ++ memcpy(tag, tmp_ht_cap_buf, tmp_ht_cap_len - 2); ++ tag += tmp_ht_cap_len - 2; ++#endif ++ if(rate_ex_len){ ++ *(tag++) = MFIE_TYPE_RATES_EX; ++ *(tag++) = rate_ex_len-2; ++ memcpy(tag,ieee->current_network.rates_ex,rate_ex_len-2); ++ tag+=rate_ex_len-2; ++ } ++ ++#if 0 ++ //Include High Throuput info ++ ++ *(tag++) = MFIE_TYPE_HT_INFO; ++ *(tag++) = tmp_ht_info_len - 2; ++ memcpy(tag, tmp_ht_info_buf, tmp_ht_info_len -2); ++ tag += tmp_ht_info_len - 2; ++#endif ++ if (wpa_ie_len) ++ { ++ if (ieee->iw_mode == IW_MODE_ADHOC) ++ {//as Windows will set pairwise key same as the group key which is not allowed in Linux, so set this for IOT issue. WB 2008.07.07 ++ memcpy(&ieee->wpa_ie[14], &ieee->wpa_ie[8], 4); ++ } ++ memcpy(tag, ieee->wpa_ie, ieee->wpa_ie_len); ++ tag += wpa_ie_len; ++ } ++ ++#if 0 ++ // ++ // Construct Realtek Proprietary Aggregation mode (Set AMPDU Factor to 2, 32k) ++ // ++ if(pHTInfo->bRegRT2RTAggregation) ++ { ++ (*tag++) = 0xdd; ++ (*tag++) = tmp_generic_ie_len - 2; ++ memcpy(tag,tmp_generic_ie_buf,tmp_generic_ie_len -2); ++ tag += tmp_generic_ie_len -2; ++ ++ } ++#endif ++#if 0 ++ if(ieee->qos_support) ++ { ++ (*tag++) = 0xdd; ++ (*tag++) = wmm_len; ++ memcpy(tag,QosOui,wmm_len); ++ tag += wmm_len; ++ } ++#endif ++ //skb->dev = ieee->dev; ++ return skb; ++} ++ ++ ++struct sk_buff* ieee80211_assoc_resp(struct ieee80211_device *ieee, u8 *dest) ++{ ++ struct sk_buff *skb; ++ u8* tag; ++ ++ struct ieee80211_crypt_data* crypt; ++ struct ieee80211_assoc_response_frame *assoc; ++ short encrypt; ++ ++ unsigned int rate_len = ieee80211_MFIE_rate_len(ieee); ++ int len = sizeof(struct ieee80211_assoc_response_frame) + rate_len + ieee->tx_headroom; ++ ++ skb = dev_alloc_skb(len); ++ ++ if (!skb) ++ return NULL; ++ ++ skb_reserve(skb, ieee->tx_headroom); ++ ++ assoc = (struct ieee80211_assoc_response_frame *) ++ skb_put(skb,sizeof(struct ieee80211_assoc_response_frame)); ++ ++ assoc->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP); ++ memcpy(assoc->header.addr1, dest,ETH_ALEN); ++ memcpy(assoc->header.addr3, ieee->dev->dev_addr, ETH_ALEN); ++ memcpy(assoc->header.addr2, ieee->dev->dev_addr, ETH_ALEN); ++ assoc->capability = cpu_to_le16(ieee->iw_mode == IW_MODE_MASTER ? ++ WLAN_CAPABILITY_BSS : WLAN_CAPABILITY_IBSS); ++ ++ ++ if(ieee->short_slot) ++ assoc->capability |= cpu_to_le16(WLAN_CAPABILITY_SHORT_SLOT); ++ ++ if (ieee->host_encrypt) ++ crypt = ieee->crypt[ieee->tx_keyidx]; ++ else crypt = NULL; ++ ++ encrypt = ( crypt && crypt->ops); ++ ++ if (encrypt) ++ assoc->capability |= cpu_to_le16(WLAN_CAPABILITY_PRIVACY); ++ ++ assoc->status = 0; ++ assoc->aid = cpu_to_le16(ieee->assoc_id); ++ if (ieee->assoc_id == 0x2007) ieee->assoc_id=0; ++ else ieee->assoc_id++; ++ ++ tag = (u8*) skb_put(skb, rate_len); ++ ++ ieee80211_MFIE_Brate(ieee, &tag); ++ ieee80211_MFIE_Grate(ieee, &tag); ++ ++ return skb; ++} ++ ++struct sk_buff* ieee80211_auth_resp(struct ieee80211_device *ieee,int status, u8 *dest) ++{ ++ struct sk_buff *skb; ++ struct ieee80211_authentication *auth; ++ int len = ieee->tx_headroom + sizeof(struct ieee80211_authentication)+1; ++ ++ skb = dev_alloc_skb(len); ++ ++ if (!skb) ++ return NULL; ++ ++ skb->len = sizeof(struct ieee80211_authentication); ++ ++ auth = (struct ieee80211_authentication *)skb->data; ++ ++ auth->status = cpu_to_le16(status); ++ auth->transaction = cpu_to_le16(2); ++ auth->algorithm = cpu_to_le16(WLAN_AUTH_OPEN); ++ ++ memcpy(auth->header.addr3, ieee->dev->dev_addr, ETH_ALEN); ++ memcpy(auth->header.addr2, ieee->dev->dev_addr, ETH_ALEN); ++ memcpy(auth->header.addr1, dest, ETH_ALEN); ++ auth->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_AUTH); ++ return skb; ++ ++ ++} ++ ++struct sk_buff* ieee80211_null_func(struct ieee80211_device *ieee,short pwr) ++{ ++ struct sk_buff *skb; ++ struct ieee80211_hdr_3addr* hdr; ++ ++ skb = dev_alloc_skb(sizeof(struct ieee80211_hdr_3addr)); ++ ++ if (!skb) ++ return NULL; ++ ++ hdr = (struct ieee80211_hdr_3addr*)skb_put(skb,sizeof(struct ieee80211_hdr_3addr)); ++ ++ memcpy(hdr->addr1, ieee->current_network.bssid, ETH_ALEN); ++ memcpy(hdr->addr2, ieee->dev->dev_addr, ETH_ALEN); ++ memcpy(hdr->addr3, ieee->current_network.bssid, ETH_ALEN); ++ ++ hdr->frame_ctl = cpu_to_le16(IEEE80211_FTYPE_DATA | ++ IEEE80211_STYPE_NULLFUNC | IEEE80211_FCTL_TODS | ++ (pwr ? IEEE80211_FCTL_PM:0)); ++ ++ return skb; ++ ++ ++} ++ ++ ++void ieee80211_resp_to_assoc_rq(struct ieee80211_device *ieee, u8* dest) ++{ ++ struct sk_buff *buf = ieee80211_assoc_resp(ieee, dest); ++ ++ if (buf) ++ softmac_mgmt_xmit(buf, ieee); ++} ++ ++ ++void ieee80211_resp_to_auth(struct ieee80211_device *ieee, int s, u8* dest) ++{ ++ struct sk_buff *buf = ieee80211_auth_resp(ieee, s, dest); ++ ++ if (buf) ++ softmac_mgmt_xmit(buf, ieee); ++} ++ ++ ++void ieee80211_resp_to_probe(struct ieee80211_device *ieee, u8 *dest) ++{ ++ ++ ++ struct sk_buff *buf = ieee80211_probe_resp(ieee, dest); ++ if (buf) ++ softmac_mgmt_xmit(buf, ieee); ++} ++ ++ ++inline struct sk_buff *ieee80211_association_req(struct ieee80211_network *beacon,struct ieee80211_device *ieee) ++{ ++ struct sk_buff *skb; ++ //unsigned long flags; ++ ++ struct ieee80211_assoc_request_frame *hdr; ++ u8 *tag;//,*rsn_ie; ++ //short info_addr = 0; ++ //int i; ++ //u16 suite_count = 0; ++ //u8 suit_select = 0; ++ //unsigned int wpa_len = beacon->wpa_ie_len; ++ //for HT ++ u8* ht_cap_buf = NULL; ++ u8 ht_cap_len=0; ++ u8* realtek_ie_buf=NULL; ++ u8 realtek_ie_len=0; ++ int wpa_ie_len= ieee->wpa_ie_len; ++ unsigned int ckip_ie_len=0; ++ unsigned int ccxrm_ie_len=0; ++ unsigned int cxvernum_ie_len=0; ++ struct ieee80211_crypt_data* crypt; ++ int encrypt; ++ ++ unsigned int rate_len = ieee80211_MFIE_rate_len(ieee); ++ unsigned int wmm_info_len = beacon->qos_data.supported?9:0; ++#ifdef THOMAS_TURBO ++ unsigned int turbo_info_len = beacon->Turbo_Enable?9:0; ++#endif ++ ++ int len = 0; ++ ++ crypt = ieee->crypt[ieee->tx_keyidx]; ++ encrypt = ieee->host_encrypt && crypt && crypt->ops && ((0 == strcmp(crypt->ops->name,"WEP") || wpa_ie_len)); ++ ++ //Include High Throuput capability && Realtek proprietary ++ if(ieee->pHTInfo->bCurrentHTSupport&&ieee->pHTInfo->bEnableHT) ++ { ++ ht_cap_buf = (u8*)&(ieee->pHTInfo->SelfHTCap); ++ ht_cap_len = sizeof(ieee->pHTInfo->SelfHTCap); ++ HTConstructCapabilityElement(ieee, ht_cap_buf, &ht_cap_len, encrypt); ++ if(ieee->pHTInfo->bCurrentRT2RTAggregation) ++ { ++ realtek_ie_buf = ieee->pHTInfo->szRT2RTAggBuffer; ++ realtek_ie_len = sizeof( ieee->pHTInfo->szRT2RTAggBuffer); ++ HTConstructRT2RTAggElement(ieee, realtek_ie_buf, &realtek_ie_len); ++ ++ } ++ } ++ if(ieee->qos_support){ ++ wmm_info_len = beacon->qos_data.supported?9:0; ++ } ++ ++ ++ if(beacon->bCkipSupported) ++ { ++ ckip_ie_len = 30+2; ++ } ++ if(beacon->bCcxRmEnable) ++ { ++ ccxrm_ie_len = 6+2; ++ } ++ if( beacon->BssCcxVerNumber >= 2 ) ++ { ++ cxvernum_ie_len = 5+2; ++ } ++#ifdef THOMAS_TURBO ++ len = sizeof(struct ieee80211_assoc_request_frame)+ 2 ++ + beacon->ssid_len//essid tagged val ++ + rate_len//rates tagged val ++ + wpa_ie_len ++ + wmm_info_len ++ + turbo_info_len ++ + ht_cap_len ++ + realtek_ie_len ++ + ckip_ie_len ++ + ccxrm_ie_len ++ + cxvernum_ie_len ++ + ieee->tx_headroom; ++#else ++ len = sizeof(struct ieee80211_assoc_request_frame)+ 2 ++ + beacon->ssid_len//essid tagged val ++ + rate_len//rates tagged val ++ + wpa_ie_len ++ + wmm_info_len ++ + ht_cap_len ++ + realtek_ie_len ++ + ckip_ie_len ++ + ccxrm_ie_len ++ + cxvernum_ie_len ++ + ieee->tx_headroom; ++#endif ++ ++ skb = dev_alloc_skb(len); ++ ++ if (!skb) ++ return NULL; ++ ++ skb_reserve(skb, ieee->tx_headroom); ++ ++ hdr = (struct ieee80211_assoc_request_frame *) ++ skb_put(skb, sizeof(struct ieee80211_assoc_request_frame)+2); ++ ++ ++ hdr->header.frame_ctl = IEEE80211_STYPE_ASSOC_REQ; ++ hdr->header.duration_id= 37; //FIXME ++ memcpy(hdr->header.addr1, beacon->bssid, ETH_ALEN); ++ memcpy(hdr->header.addr2, ieee->dev->dev_addr, ETH_ALEN); ++ memcpy(hdr->header.addr3, beacon->bssid, ETH_ALEN); ++ ++ memcpy(ieee->ap_mac_addr, beacon->bssid, ETH_ALEN);//for HW security, John ++ ++ hdr->capability = cpu_to_le16(WLAN_CAPABILITY_BSS); ++ if (beacon->capability & WLAN_CAPABILITY_PRIVACY ) ++ hdr->capability |= cpu_to_le16(WLAN_CAPABILITY_PRIVACY); ++ ++ if (beacon->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) ++ hdr->capability |= cpu_to_le16(WLAN_CAPABILITY_SHORT_PREAMBLE); //add short_preamble here ++ ++ if(ieee->short_slot) ++ hdr->capability |= cpu_to_le16(WLAN_CAPABILITY_SHORT_SLOT); ++ if (wmm_info_len) //QOS ++ hdr->capability |= cpu_to_le16(WLAN_CAPABILITY_QOS); ++ ++ hdr->listen_interval = 0xa; //FIXME ++ ++ hdr->info_element[0].id = MFIE_TYPE_SSID; ++ ++ hdr->info_element[0].len = beacon->ssid_len; ++ tag = skb_put(skb, beacon->ssid_len); ++ memcpy(tag, beacon->ssid, beacon->ssid_len); ++ ++ tag = skb_put(skb, rate_len); ++ ++ ieee80211_MFIE_Brate(ieee, &tag); ++ ieee80211_MFIE_Grate(ieee, &tag); ++ // For CCX 1 S13, CKIP. Added by Annie, 2006-08-14. ++ if( beacon->bCkipSupported ) ++ { ++ static u8 AironetIeOui[] = {0x00, 0x01, 0x66}; // "4500-client" ++ u8 CcxAironetBuf[30]; ++ OCTET_STRING osCcxAironetIE; ++ ++ memset(CcxAironetBuf, 0,30); ++ osCcxAironetIE.Octet = CcxAironetBuf; ++ osCcxAironetIE.Length = sizeof(CcxAironetBuf); ++ // ++ // Ref. CCX test plan v3.61, 3.2.3.1 step 13. ++ // We want to make the device type as "4500-client". 060926, by CCW. ++ // ++ memcpy(osCcxAironetIE.Octet, AironetIeOui, sizeof(AironetIeOui)); ++ ++ // CCX1 spec V1.13, A01.1 CKIP Negotiation (page23): ++ // "The CKIP negotiation is started with the associate request from the client to the access point, ++ // containing an Aironet element with both the MIC and KP bits set." ++ osCcxAironetIE.Octet[IE_CISCO_FLAG_POSITION] |= (SUPPORT_CKIP_PK|SUPPORT_CKIP_MIC) ; ++ tag = skb_put(skb, ckip_ie_len); ++ *tag++ = MFIE_TYPE_AIRONET; ++ *tag++ = osCcxAironetIE.Length; ++ memcpy(tag,osCcxAironetIE.Octet,osCcxAironetIE.Length); ++ tag += osCcxAironetIE.Length; ++ } ++ ++ if(beacon->bCcxRmEnable) ++ { ++ static u8 CcxRmCapBuf[] = {0x00, 0x40, 0x96, 0x01, 0x01, 0x00}; ++ OCTET_STRING osCcxRmCap; ++ ++ osCcxRmCap.Octet = CcxRmCapBuf; ++ osCcxRmCap.Length = sizeof(CcxRmCapBuf); ++ tag = skb_put(skb,ccxrm_ie_len); ++ *tag++ = MFIE_TYPE_GENERIC; ++ *tag++ = osCcxRmCap.Length; ++ memcpy(tag,osCcxRmCap.Octet,osCcxRmCap.Length); ++ tag += osCcxRmCap.Length; ++ } ++ ++ if( beacon->BssCcxVerNumber >= 2 ) ++ { ++ u8 CcxVerNumBuf[] = {0x00, 0x40, 0x96, 0x03, 0x00}; ++ OCTET_STRING osCcxVerNum; ++ CcxVerNumBuf[4] = beacon->BssCcxVerNumber; ++ osCcxVerNum.Octet = CcxVerNumBuf; ++ osCcxVerNum.Length = sizeof(CcxVerNumBuf); ++ tag = skb_put(skb,cxvernum_ie_len); ++ *tag++ = MFIE_TYPE_GENERIC; ++ *tag++ = osCcxVerNum.Length; ++ memcpy(tag,osCcxVerNum.Octet,osCcxVerNum.Length); ++ tag += osCcxVerNum.Length; ++ } ++ //HT cap element ++ if(ieee->pHTInfo->bCurrentHTSupport&&ieee->pHTInfo->bEnableHT){ ++ if(ieee->pHTInfo->ePeerHTSpecVer != HT_SPEC_VER_EWC) ++ { ++ tag = skb_put(skb, ht_cap_len); ++ *tag++ = MFIE_TYPE_HT_CAP; ++ *tag++ = ht_cap_len - 2; ++ memcpy(tag, ht_cap_buf,ht_cap_len -2); ++ tag += ht_cap_len -2; ++ } ++ } ++ ++ ++ //choose what wpa_supplicant gives to associate. ++ tag = skb_put(skb, wpa_ie_len); ++ if (wpa_ie_len){ ++ memcpy(tag, ieee->wpa_ie, ieee->wpa_ie_len); ++ } ++ ++ tag = skb_put(skb,wmm_info_len); ++ if(wmm_info_len) { ++ ieee80211_WMM_Info(ieee, &tag); ++ } ++#ifdef THOMAS_TURBO ++ tag = skb_put(skb,turbo_info_len); ++ if(turbo_info_len) { ++ ieee80211_TURBO_Info(ieee, &tag); ++ } ++#endif ++ ++ if(ieee->pHTInfo->bCurrentHTSupport&&ieee->pHTInfo->bEnableHT){ ++ if(ieee->pHTInfo->ePeerHTSpecVer == HT_SPEC_VER_EWC) ++ { ++ tag = skb_put(skb, ht_cap_len); ++ *tag++ = MFIE_TYPE_GENERIC; ++ *tag++ = ht_cap_len - 2; ++ memcpy(tag, ht_cap_buf,ht_cap_len - 2); ++ tag += ht_cap_len -2; ++ } ++ ++ if(ieee->pHTInfo->bCurrentRT2RTAggregation){ ++ tag = skb_put(skb, realtek_ie_len); ++ *tag++ = MFIE_TYPE_GENERIC; ++ *tag++ = realtek_ie_len - 2; ++ memcpy(tag, realtek_ie_buf,realtek_ie_len -2 ); ++ } ++ } ++// printk("<=====%s(), %p, %p\n", __FUNCTION__, ieee->dev, ieee->dev->dev_addr); ++// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len); ++ return skb; ++} ++ ++void ieee80211_associate_abort(struct ieee80211_device *ieee) ++{ ++ ++ unsigned long flags; ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ ieee->associate_seq++; ++ ++ /* don't scan, and avoid to have the RX path possibily ++ * try again to associate. Even do not react to AUTH or ++ * ASSOC response. Just wait for the retry wq to be scheduled. ++ * Here we will check if there are good nets to associate ++ * with, so we retry or just get back to NO_LINK and scanning ++ */ ++ if (ieee->state == IEEE80211_ASSOCIATING_AUTHENTICATING){ ++ IEEE80211_DEBUG_MGMT("Authentication failed\n"); ++ ieee->softmac_stats.no_auth_rs++; ++ }else{ ++ IEEE80211_DEBUG_MGMT("Association failed\n"); ++ ieee->softmac_stats.no_ass_rs++; ++ } ++ ++ ieee->state = IEEE80211_ASSOCIATING_RETRY; ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ queue_delayed_work(ieee->wq, &ieee->associate_retry_wq, \ ++ IEEE80211_SOFTMAC_ASSOC_RETRY_TIME); ++#else ++ schedule_task(&ieee->associate_retry_wq); ++#endif ++ ++ spin_unlock_irqrestore(&ieee->lock, flags); ++} ++ ++void ieee80211_associate_abort_cb(unsigned long dev) ++{ ++ ieee80211_associate_abort((struct ieee80211_device *) dev); ++} ++ ++ ++void ieee80211_associate_step1(struct ieee80211_device *ieee) ++{ ++ struct ieee80211_network *beacon = &ieee->current_network; ++ struct sk_buff *skb; ++ ++ IEEE80211_DEBUG_MGMT("Stopping scan\n"); ++ ++ ieee->softmac_stats.tx_auth_rq++; ++ skb=ieee80211_authentication_req(beacon, ieee, 0); ++ ++ if (!skb) ++ ieee80211_associate_abort(ieee); ++ else{ ++ ieee->state = IEEE80211_ASSOCIATING_AUTHENTICATING ; ++ IEEE80211_DEBUG_MGMT("Sending authentication request\n"); ++ //printk(KERN_WARNING "Sending authentication request\n"); ++ softmac_mgmt_xmit(skb, ieee); ++ //BUGON when you try to add_timer twice, using mod_timer may be better, john0709 ++ if(!timer_pending(&ieee->associate_timer)){ ++ ieee->associate_timer.expires = jiffies + (HZ / 2); ++ add_timer(&ieee->associate_timer); ++ } ++ //dev_kfree_skb_any(skb);//edit by thomas ++ } ++} ++ ++void ieee80211_auth_challenge(struct ieee80211_device *ieee, u8 *challenge, int chlen) ++{ ++ u8 *c; ++ struct sk_buff *skb; ++ struct ieee80211_network *beacon = &ieee->current_network; ++// int hlen = sizeof(struct ieee80211_authentication); ++ ++ ieee->associate_seq++; ++ ieee->softmac_stats.tx_auth_rq++; ++ ++ skb = ieee80211_authentication_req(beacon, ieee, chlen+2); ++ if (!skb) ++ ieee80211_associate_abort(ieee); ++ else{ ++ c = skb_put(skb, chlen+2); ++ *(c++) = MFIE_TYPE_CHALLENGE; ++ *(c++) = chlen; ++ memcpy(c, challenge, chlen); ++ ++ IEEE80211_DEBUG_MGMT("Sending authentication challenge response\n"); ++ ++ ieee80211_encrypt_fragment(ieee, skb, sizeof(struct ieee80211_hdr_3addr )); ++ ++ softmac_mgmt_xmit(skb, ieee); ++ mod_timer(&ieee->associate_timer, jiffies + (HZ/2)); ++#if 0 ++ ieee->associate_timer.expires = jiffies + (HZ / 2); ++ add_timer(&ieee->associate_timer); ++#endif ++ //dev_kfree_skb_any(skb);//edit by thomas ++ } ++ kfree(challenge); ++} ++ ++void ieee80211_associate_step2(struct ieee80211_device *ieee) ++{ ++ struct sk_buff* skb; ++ struct ieee80211_network *beacon = &ieee->current_network; ++ ++ del_timer_sync(&ieee->associate_timer); ++ ++ IEEE80211_DEBUG_MGMT("Sending association request\n"); ++ ++ ieee->softmac_stats.tx_ass_rq++; ++ skb=ieee80211_association_req(beacon, ieee); ++ if (!skb) ++ ieee80211_associate_abort(ieee); ++ else{ ++ softmac_mgmt_xmit(skb, ieee); ++ mod_timer(&ieee->associate_timer, jiffies + (HZ/2)); ++#if 0 ++ ieee->associate_timer.expires = jiffies + (HZ / 2); ++ add_timer(&ieee->associate_timer); ++#endif ++ //dev_kfree_skb_any(skb);//edit by thomas ++ } ++} ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void ieee80211_associate_complete_wq(struct work_struct *work) ++{ ++ struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, associate_complete_wq); ++#else ++void ieee80211_associate_complete_wq(struct ieee80211_device *ieee) ++{ ++#endif ++ printk(KERN_INFO "Associated successfully\n"); ++ ieee->is_roaming = false; ++ if(ieee80211_is_54g(ieee->current_network) && ++ (ieee->modulation & IEEE80211_OFDM_MODULATION)){ ++ ++ ieee->rate = 108; ++ printk(KERN_INFO"Using G rates:%d\n", ieee->rate); ++ }else{ ++ ieee->rate = 22; ++ printk(KERN_INFO"Using B rates:%d\n", ieee->rate); ++ } ++ if (ieee->pHTInfo->bCurrentHTSupport&&ieee->pHTInfo->bEnableHT) ++ { ++ printk("Successfully associated, ht enabled\n"); ++ HTOnAssocRsp(ieee); ++ } ++ else ++ { ++ printk("Successfully associated, ht not enabled(%d, %d)\n", ieee->pHTInfo->bCurrentHTSupport, ieee->pHTInfo->bEnableHT); ++ memset(ieee->dot11HTOperationalRateSet, 0, 16); ++ //HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); ++ } ++ ieee->LinkDetectInfo.SlotNum = 2 * (1 + ieee->current_network.beacon_interval/500); ++ // To prevent the immediately calling watch_dog after association. ++ if(ieee->LinkDetectInfo.NumRecvBcnInPeriod==0||ieee->LinkDetectInfo.NumRecvDataInPeriod==0 ) ++ { ++ ieee->LinkDetectInfo.NumRecvBcnInPeriod = 1; ++ ieee->LinkDetectInfo.NumRecvDataInPeriod= 1; ++ } ++ ieee->link_change(ieee->dev); ++ if(ieee->is_silent_reset == 0){ ++ printk("============>normal associate\n"); ++ notify_wx_assoc_event(ieee); ++ } ++ else if(ieee->is_silent_reset == 1) ++ { ++ printk("==================>silent reset associate\n"); ++ ieee->is_silent_reset = 0; ++ } ++ ++ if (ieee->data_hard_resume) ++ ieee->data_hard_resume(ieee->dev); ++ netif_carrier_on(ieee->dev); ++} ++ ++void ieee80211_associate_complete(struct ieee80211_device *ieee) ++{ ++// int i; ++// struct net_device* dev = ieee->dev; ++ del_timer_sync(&ieee->associate_timer); ++ ++#if 0 ++ for(i = 0; i < 6; i++) { ++ ieee->seq_ctrl[i] = 0; ++ } ++#endif ++ ieee->state = IEEE80211_LINKED; ++#if 0 ++ if (ieee->pHTInfo->bCurrentHTSupport) ++ { ++ printk("Successfully associated, ht enabled\n"); ++ queue_work(ieee->wq, &ieee->ht_onAssRsp); ++ } ++ else ++ { ++ printk("Successfully associated, ht not enabled\n"); ++ memset(ieee->dot11HTOperationalRateSet, 0, 16); ++ HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); ++ } ++#endif ++ //ieee->UpdateHalRATRTableHandler(dev, ieee->dot11HTOperationalRateSet); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ queue_work(ieee->wq, &ieee->associate_complete_wq); ++#else ++ schedule_task(&ieee->associate_complete_wq); ++#endif ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void ieee80211_associate_procedure_wq(struct work_struct *work) ++{ ++ struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, associate_procedure_wq); ++#else ++void ieee80211_associate_procedure_wq(struct ieee80211_device *ieee) ++{ ++#endif ++ ieee->sync_scan_hurryup = 1; ++ down(&ieee->wx_sem); ++ ++ if (ieee->data_hard_stop) ++ ieee->data_hard_stop(ieee->dev); ++ ++ ieee80211_stop_scan(ieee); ++ printk("===>%s(), chan:%d\n", __FUNCTION__, ieee->current_network.channel); ++ //ieee->set_chan(ieee->dev, ieee->current_network.channel); ++ HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); ++ ++ ieee->associate_seq = 1; ++ ieee80211_associate_step1(ieee); ++ ++ up(&ieee->wx_sem); ++} ++ ++inline void ieee80211_softmac_new_net(struct ieee80211_device *ieee, struct ieee80211_network *net) ++{ ++ u8 tmp_ssid[IW_ESSID_MAX_SIZE+1]; ++ int tmp_ssid_len = 0; ++ ++ short apset,ssidset,ssidbroad,apmatch,ssidmatch; ++ ++ /* we are interested in new new only if we are not associated ++ * and we are not associating / authenticating ++ */ ++ if (ieee->state != IEEE80211_NOLINK) ++ return; ++ ++ if ((ieee->iw_mode == IW_MODE_INFRA) && !(net->capability & WLAN_CAPABILITY_BSS)) ++ return; ++ ++ if ((ieee->iw_mode == IW_MODE_ADHOC) && !(net->capability & WLAN_CAPABILITY_IBSS)) ++ return; ++ ++ ++ if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC){ ++ /* if the user specified the AP MAC, we need also the essid ++ * This could be obtained by beacons or, if the network does not ++ * broadcast it, it can be put manually. ++ */ ++ apset = ieee->wap_set;//(memcmp(ieee->current_network.bssid, zero,ETH_ALEN)!=0 ); ++ ssidset = ieee->ssid_set;//ieee->current_network.ssid[0] != '\0'; ++ ssidbroad = !(net->ssid_len == 0 || net->ssid[0]== '\0'); ++ apmatch = (memcmp(ieee->current_network.bssid, net->bssid, ETH_ALEN)==0); ++ ssidmatch = (ieee->current_network.ssid_len == net->ssid_len)&&\ ++ (!strncmp(ieee->current_network.ssid, net->ssid, net->ssid_len)); ++ ++ ++ if ( /* if the user set the AP check if match. ++ * if the network does not broadcast essid we check the user supplyed ANY essid ++ * if the network does broadcast and the user does not set essid it is OK ++ * if the network does broadcast and the user did set essid chech if essid match ++ */ ++ ( apset && apmatch && ++ ((ssidset && ssidbroad && ssidmatch) || (ssidbroad && !ssidset) || (!ssidbroad && ssidset)) ) || ++ /* if the ap is not set, check that the user set the bssid ++ * and the network does bradcast and that those two bssid matches ++ */ ++ (!apset && ssidset && ssidbroad && ssidmatch) ++ ){ ++ /* if the essid is hidden replace it with the ++ * essid provided by the user. ++ */ ++ if (!ssidbroad){ ++ strncpy(tmp_ssid, ieee->current_network.ssid, IW_ESSID_MAX_SIZE); ++ tmp_ssid_len = ieee->current_network.ssid_len; ++ } ++ memcpy(&ieee->current_network, net, sizeof(struct ieee80211_network)); ++ ++ if (!ssidbroad){ ++ strncpy(ieee->current_network.ssid, tmp_ssid, IW_ESSID_MAX_SIZE); ++ ieee->current_network.ssid_len = tmp_ssid_len; ++ } ++ printk(KERN_INFO"Linking with %s,channel:%d, qos:%d, myHT:%d, networkHT:%d\n",ieee->current_network.ssid,ieee->current_network.channel, ieee->current_network.qos_data.supported, ieee->pHTInfo->bEnableHT, ieee->current_network.bssht.bdSupportHT); ++ ++ //ieee->pHTInfo->IOTAction = 0; ++ HTResetIOTSetting(ieee->pHTInfo); ++ if (ieee->iw_mode == IW_MODE_INFRA){ ++ /* Join the network for the first time */ ++ ieee->AsocRetryCount = 0; ++ //for HT by amy 080514 ++ if((ieee->current_network.qos_data.supported == 1) && ++ // (ieee->pHTInfo->bEnableHT && ieee->current_network.bssht.bdSupportHT)) ++ ieee->current_network.bssht.bdSupportHT) ++/*WB, 2008.09.09:bCurrentHTSupport and bEnableHT two flags are going to put together to check whether we are in HT now, so needn't to check bEnableHT flags here. That's is to say we will set to HT support whenever joined AP has the ability to support HT. And whether we are in HT or not, please check bCurrentHTSupport&&bEnableHT now please.*/ ++ { ++ // ieee->pHTInfo->bCurrentHTSupport = true; ++ HTResetSelfAndSavePeerSetting(ieee, &(ieee->current_network)); ++ } ++ else ++ { ++ ieee->pHTInfo->bCurrentHTSupport = false; ++ } ++ ++ ieee->state = IEEE80211_ASSOCIATING; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ queue_work(ieee->wq, &ieee->associate_procedure_wq); ++#else ++ schedule_task(&ieee->associate_procedure_wq); ++#endif ++ }else{ ++ if(ieee80211_is_54g(ieee->current_network) && ++ (ieee->modulation & IEEE80211_OFDM_MODULATION)){ ++ ieee->rate = 108; ++ ieee->SetWirelessMode(ieee->dev, IEEE_G); ++ printk(KERN_INFO"Using G rates\n"); ++ }else{ ++ ieee->rate = 22; ++ ieee->SetWirelessMode(ieee->dev, IEEE_B); ++ printk(KERN_INFO"Using B rates\n"); ++ } ++ memset(ieee->dot11HTOperationalRateSet, 0, 16); ++ //HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); ++ ieee->state = IEEE80211_LINKED; ++ } ++ ++ } ++ } ++ ++} ++ ++void ieee80211_softmac_check_all_nets(struct ieee80211_device *ieee) ++{ ++ unsigned long flags; ++ struct ieee80211_network *target; ++ ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ list_for_each_entry(target, &ieee->network_list, list) { ++ ++ /* if the state become different that NOLINK means ++ * we had found what we are searching for ++ */ ++ ++ if (ieee->state != IEEE80211_NOLINK) ++ break; ++ ++ if (ieee->scan_age == 0 || time_after(target->last_scanned + ieee->scan_age, jiffies)) ++ ieee80211_softmac_new_net(ieee, target); ++ } ++ ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ ++} ++ ++ ++static inline u16 auth_parse(struct sk_buff *skb, u8** challenge, int *chlen) ++{ ++ struct ieee80211_authentication *a; ++ u8 *t; ++ if (skb->len < (sizeof(struct ieee80211_authentication)-sizeof(struct ieee80211_info_element))){ ++ IEEE80211_DEBUG_MGMT("invalid len in auth resp: %d\n",skb->len); ++ return 0xcafe; ++ } ++ *challenge = NULL; ++ a = (struct ieee80211_authentication*) skb->data; ++ if(skb->len > (sizeof(struct ieee80211_authentication) +3)){ ++ t = skb->data + sizeof(struct ieee80211_authentication); ++ ++ if(*(t++) == MFIE_TYPE_CHALLENGE){ ++ *chlen = *(t++); ++ *challenge = (u8*)kmalloc(*chlen, GFP_ATOMIC); ++ memcpy(*challenge, t, *chlen); ++ } ++ } ++ ++ return cpu_to_le16(a->status); ++ ++} ++ ++ ++int auth_rq_parse(struct sk_buff *skb,u8* dest) ++{ ++ struct ieee80211_authentication *a; ++ ++ if (skb->len < (sizeof(struct ieee80211_authentication)-sizeof(struct ieee80211_info_element))){ ++ IEEE80211_DEBUG_MGMT("invalid len in auth request: %d\n",skb->len); ++ return -1; ++ } ++ a = (struct ieee80211_authentication*) skb->data; ++ ++ memcpy(dest,a->header.addr2, ETH_ALEN); ++ ++ if (le16_to_cpu(a->algorithm) != WLAN_AUTH_OPEN) ++ return WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG; ++ ++ return WLAN_STATUS_SUCCESS; ++} ++ ++static short probe_rq_parse(struct ieee80211_device *ieee, struct sk_buff *skb, u8 *src) ++{ ++ u8 *tag; ++ u8 *skbend; ++ u8 *ssid=NULL; ++ u8 ssidlen = 0; ++ ++ struct ieee80211_hdr_3addr *header = ++ (struct ieee80211_hdr_3addr *) skb->data; ++ ++ if (skb->len < sizeof (struct ieee80211_hdr_3addr )) ++ return -1; /* corrupted */ ++ ++ memcpy(src,header->addr2, ETH_ALEN); ++ ++ skbend = (u8*)skb->data + skb->len; ++ ++ tag = skb->data + sizeof (struct ieee80211_hdr_3addr ); ++ ++ while (tag+1 < skbend){ ++ if (*tag == 0){ ++ ssid = tag+2; ++ ssidlen = *(tag+1); ++ break; ++ } ++ tag++; /* point to the len field */ ++ tag = tag + *(tag); /* point to the last data byte of the tag */ ++ tag++; /* point to the next tag */ ++ } ++ ++ //IEEE80211DMESG("Card MAC address is "MACSTR, MAC2STR(src)); ++ if (ssidlen == 0) return 1; ++ ++ if (!ssid) return 1; /* ssid not found in tagged param */ ++ return (!strncmp(ssid, ieee->current_network.ssid, ssidlen)); ++ ++} ++ ++int assoc_rq_parse(struct sk_buff *skb,u8* dest) ++{ ++ struct ieee80211_assoc_request_frame *a; ++ ++ if (skb->len < (sizeof(struct ieee80211_assoc_request_frame) - ++ sizeof(struct ieee80211_info_element))) { ++ ++ IEEE80211_DEBUG_MGMT("invalid len in auth request:%d \n", skb->len); ++ return -1; ++ } ++ ++ a = (struct ieee80211_assoc_request_frame*) skb->data; ++ ++ memcpy(dest,a->header.addr2,ETH_ALEN); ++ ++ return 0; ++} ++ ++static inline u16 assoc_parse(struct ieee80211_device *ieee, struct sk_buff *skb, int *aid) ++{ ++ struct ieee80211_assoc_response_frame *response_head; ++ u16 status_code; ++ ++ if (skb->len < sizeof(struct ieee80211_assoc_response_frame)){ ++ IEEE80211_DEBUG_MGMT("invalid len in auth resp: %d\n", skb->len); ++ return 0xcafe; ++ } ++ ++ response_head = (struct ieee80211_assoc_response_frame*) skb->data; ++ *aid = le16_to_cpu(response_head->aid) & 0x3fff; ++ ++ status_code = le16_to_cpu(response_head->status); ++ if((status_code==WLAN_STATUS_ASSOC_DENIED_RATES || \ ++ status_code==WLAN_STATUS_CAPS_UNSUPPORTED)&& ++ ((ieee->mode == IEEE_G) && ++ (ieee->current_network.mode == IEEE_N_24G) && ++ (ieee->AsocRetryCount++ < (RT_ASOC_RETRY_LIMIT-1)))) { ++ ieee->pHTInfo->IOTAction |= HT_IOT_ACT_PURE_N_MODE; ++ }else { ++ ieee->AsocRetryCount = 0; ++ } ++ ++ return le16_to_cpu(response_head->status); ++} ++ ++static inline void ++ieee80211_rx_probe_rq(struct ieee80211_device *ieee, struct sk_buff *skb) ++{ ++ u8 dest[ETH_ALEN]; ++ ++ //IEEE80211DMESG("Rx probe"); ++ ieee->softmac_stats.rx_probe_rq++; ++ //DMESG("Dest is "MACSTR, MAC2STR(dest)); ++ if (probe_rq_parse(ieee, skb, dest)){ ++ //IEEE80211DMESG("Was for me!"); ++ ieee->softmac_stats.tx_probe_rs++; ++ ieee80211_resp_to_probe(ieee, dest); ++ } ++} ++ ++static inline void ++ieee80211_rx_auth_rq(struct ieee80211_device *ieee, struct sk_buff *skb) ++{ ++ u8 dest[ETH_ALEN]; ++ int status; ++ //IEEE80211DMESG("Rx probe"); ++ ieee->softmac_stats.rx_auth_rq++; ++ ++ if ((status = auth_rq_parse(skb, dest))!= -1){ ++ ieee80211_resp_to_auth(ieee, status, dest); ++ } ++ //DMESG("Dest is "MACSTR, MAC2STR(dest)); ++ ++} ++ ++static inline void ++ieee80211_rx_assoc_rq(struct ieee80211_device *ieee, struct sk_buff *skb) ++{ ++ ++ u8 dest[ETH_ALEN]; ++ //unsigned long flags; ++ ++ ieee->softmac_stats.rx_ass_rq++; ++ if (assoc_rq_parse(skb,dest) != -1){ ++ ieee80211_resp_to_assoc_rq(ieee, dest); ++ } ++ ++ printk(KERN_INFO"New client associated: "MAC_FMT"\n", MAC_ARG(dest)); ++ //FIXME ++ #if 0 ++ spin_lock_irqsave(&ieee->lock,flags); ++ add_associate(ieee,dest); ++ spin_unlock_irqrestore(&ieee->lock,flags); ++ #endif ++} ++ ++ ++ ++void ieee80211_sta_ps_send_null_frame(struct ieee80211_device *ieee, short pwr) ++{ ++ ++ struct sk_buff *buf = ieee80211_null_func(ieee, pwr); ++ ++ if (buf) ++ softmac_ps_mgmt_xmit(buf, ieee); ++ ++} ++ ++ ++short ieee80211_sta_ps_sleep(struct ieee80211_device *ieee, u32 *time_h, u32 *time_l) ++{ ++ int timeout = ieee->ps_timeout; ++ u8 dtim; ++ /*if(ieee->ps == IEEE80211_PS_DISABLED || ++ ieee->iw_mode != IW_MODE_INFRA || ++ ieee->state != IEEE80211_LINKED) ++ ++ return 0; ++ */ ++ dtim = ieee->current_network.dtim_data; ++ //printk("DTIM\n"); ++ if(!(dtim & IEEE80211_DTIM_VALID)) ++ return 0; ++ timeout = ieee->current_network.beacon_interval; //should we use ps_timeout value or beacon_interval ++ //printk("VALID\n"); ++ ieee->current_network.dtim_data = IEEE80211_DTIM_INVALID; ++ ++ if(dtim & ((IEEE80211_DTIM_UCAST | IEEE80211_DTIM_MBCAST)& ieee->ps)) ++ return 2; ++ ++ if(!time_after(jiffies, ieee->dev->trans_start + MSECS(timeout))) ++ return 0; ++ ++ if(!time_after(jiffies, ieee->last_rx_ps_time + MSECS(timeout))) ++ return 0; ++ ++ if((ieee->softmac_features & IEEE_SOFTMAC_SINGLE_QUEUE ) && ++ (ieee->mgmt_queue_tail != ieee->mgmt_queue_head)) ++ return 0; ++ ++ if(time_l){ ++ *time_l = ieee->current_network.last_dtim_sta_time[0] ++ + (ieee->current_network.beacon_interval); ++ // * ieee->current_network.dtim_period) * 1000; ++ } ++ ++ if(time_h){ ++ *time_h = ieee->current_network.last_dtim_sta_time[1]; ++ if(time_l && *time_l < ieee->current_network.last_dtim_sta_time[0]) ++ *time_h += 1; ++ } ++ ++ return 1; ++ ++ ++} ++ ++inline void ieee80211_sta_ps(struct ieee80211_device *ieee) ++{ ++ ++ u32 th,tl; ++ short sleep; ++ ++ unsigned long flags,flags2; ++ ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ if((ieee->ps == IEEE80211_PS_DISABLED || ++ ieee->iw_mode != IW_MODE_INFRA || ++ ieee->state != IEEE80211_LINKED)){ ++ ++ // #warning CHECK_LOCK_HERE ++ spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2); ++ ++ ieee80211_sta_wakeup(ieee, 1); ++ ++ spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2); ++ } ++ ++ sleep = ieee80211_sta_ps_sleep(ieee,&th, &tl); ++ /* 2 wake, 1 sleep, 0 do nothing */ ++ if(sleep == 0) ++ goto out; ++ ++ if(sleep == 1){ ++ ++ if(ieee->sta_sleep == 1) ++ ieee->enter_sleep_state(ieee->dev,th,tl); ++ ++ else if(ieee->sta_sleep == 0){ ++ // printk("send null 1\n"); ++ spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2); ++ ++ if(ieee->ps_is_queue_empty(ieee->dev)){ ++ ++ ++ ieee->sta_sleep = 2; ++ ++ ieee->ack_tx_to_ieee = 1; ++ ++ ieee80211_sta_ps_send_null_frame(ieee,1); ++ ++ ieee->ps_th = th; ++ ieee->ps_tl = tl; ++ } ++ spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2); ++ ++ } ++ ++ ++ }else if(sleep == 2){ ++//#warning CHECK_LOCK_HERE ++ spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2); ++ ++ ieee80211_sta_wakeup(ieee,1); ++ ++ spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2); ++ } ++ ++out: ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ ++} ++ ++void ieee80211_sta_wakeup(struct ieee80211_device *ieee, short nl) ++{ ++ if(ieee->sta_sleep == 0){ ++ if(nl){ ++ printk("Warning: driver is probably failing to report TX ps error\n"); ++ ieee->ack_tx_to_ieee = 1; ++ ieee80211_sta_ps_send_null_frame(ieee, 0); ++ } ++ return; ++ ++ } ++ ++ if(ieee->sta_sleep == 1) ++ ieee->sta_wake_up(ieee->dev); ++ ++ ieee->sta_sleep = 0; ++ ++ if(nl){ ++ ieee->ack_tx_to_ieee = 1; ++ ieee80211_sta_ps_send_null_frame(ieee, 0); ++ } ++} ++ ++void ieee80211_ps_tx_ack(struct ieee80211_device *ieee, short success) ++{ ++ unsigned long flags,flags2; ++ ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ if(ieee->sta_sleep == 2){ ++ /* Null frame with PS bit set */ ++ if(success){ ++ ieee->sta_sleep = 1; ++ ieee->enter_sleep_state(ieee->dev,ieee->ps_th,ieee->ps_tl); ++ } ++ /* if the card report not success we can't be sure the AP ++ * has not RXed so we can't assume the AP believe us awake ++ */ ++ } ++ /* 21112005 - tx again null without PS bit if lost */ ++ else { ++ ++ if((ieee->sta_sleep == 0) && !success){ ++ spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2); ++ ieee80211_sta_ps_send_null_frame(ieee, 0); ++ spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2); ++ } ++ } ++ spin_unlock_irqrestore(&ieee->lock, flags); ++} ++void ieee80211_process_action(struct ieee80211_device* ieee, struct sk_buff* skb) ++{ ++ struct ieee80211_hdr* header = (struct ieee80211_hdr*)skb->data; ++ u8* act = ieee80211_get_payload(header); ++ u8 tmp = 0; ++// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len); ++ if (act == NULL) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "error to get payload of action frame\n"); ++ return; ++ } ++ tmp = *act; ++ act ++; ++ switch (tmp) ++ { ++ case ACT_CAT_BA: ++ if (*act == ACT_ADDBAREQ) ++ ieee80211_rx_ADDBAReq(ieee, skb); ++ else if (*act == ACT_ADDBARSP) ++ ieee80211_rx_ADDBARsp(ieee, skb); ++ else if (*act == ACT_DELBA) ++ ieee80211_rx_DELBA(ieee, skb); ++ break; ++ default: ++// if (net_ratelimit()) ++// IEEE80211_DEBUG(IEEE80211_DL_BA, "unknown action frame(%d)\n", tmp); ++ break; ++ } ++ return; ++ ++} ++inline int ++ieee80211_rx_frame_softmac(struct ieee80211_device *ieee, struct sk_buff *skb, ++ struct ieee80211_rx_stats *rx_stats, u16 type, ++ u16 stype) ++{ ++ struct ieee80211_hdr_3addr *header = (struct ieee80211_hdr_3addr *) skb->data; ++ u16 errcode; ++ u8* challenge; ++ int chlen=0; ++ int aid; ++ struct ieee80211_assoc_response_frame *assoc_resp; ++// struct ieee80211_info_element *info_element; ++ bool bSupportNmode = true, bHalfSupportNmode = false; //default support N mode, disable halfNmode ++ ++ if(!ieee->proto_started) ++ return 0; ++#if 0 ++ printk("%d, %d, %d, %d\n", ieee->sta_sleep, ieee->ps, ieee->iw_mode, ieee->state); ++ if(ieee->sta_sleep || (ieee->ps != IEEE80211_PS_DISABLED && ++ ieee->iw_mode == IW_MODE_INFRA && ++ ieee->state == IEEE80211_LINKED)) ++ ++ tasklet_schedule(&ieee->ps_task); ++ ++ if(WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_PROBE_RESP && ++ WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_BEACON) ++ ieee->last_rx_ps_time = jiffies; ++#endif ++ ++ switch (WLAN_FC_GET_STYPE(header->frame_ctl)) { ++ ++ case IEEE80211_STYPE_ASSOC_RESP: ++ case IEEE80211_STYPE_REASSOC_RESP: ++ ++ IEEE80211_DEBUG_MGMT("received [RE]ASSOCIATION RESPONSE (%d)\n", ++ WLAN_FC_GET_STYPE(header->frame_ctl)); ++ if ((ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) && ++ ieee->state == IEEE80211_ASSOCIATING_AUTHENTICATED && ++ ieee->iw_mode == IW_MODE_INFRA){ ++ struct ieee80211_network network_resp; ++ struct ieee80211_network *network = &network_resp; ++ ++ if (0 == (errcode=assoc_parse(ieee,skb, &aid))){ ++ ieee->state=IEEE80211_LINKED; ++ ieee->assoc_id = aid; ++ ieee->softmac_stats.rx_ass_ok++; ++ /* station support qos */ ++ /* Let the register setting defaultly with Legacy station */ ++ if(ieee->qos_support) { ++ assoc_resp = (struct ieee80211_assoc_response_frame*)skb->data; ++ memset(network, 0, sizeof(*network)); ++ if (ieee80211_parse_info_param(ieee,assoc_resp->info_element,\ ++ rx_stats->len - sizeof(*assoc_resp),\ ++ network,rx_stats)){ ++ return 1; ++ } ++ else ++ { //filling the PeerHTCap. //maybe not neccesary as we can get its info from current_network. ++ memcpy(ieee->pHTInfo->PeerHTCapBuf, network->bssht.bdHTCapBuf, network->bssht.bdHTCapLen); ++ memcpy(ieee->pHTInfo->PeerHTInfoBuf, network->bssht.bdHTInfoBuf, network->bssht.bdHTInfoLen); ++ } ++ if (ieee->handle_assoc_response != NULL) ++ ieee->handle_assoc_response(ieee->dev, (struct ieee80211_assoc_response_frame*)header, network); ++ } ++ ieee80211_associate_complete(ieee); ++ } else { ++ /* aid could not been allocated */ ++ ieee->softmac_stats.rx_ass_err++; ++ printk( ++ "Association response status code 0x%x\n", ++ errcode); ++ IEEE80211_DEBUG_MGMT( ++ "Association response status code 0x%x\n", ++ errcode); ++ if(ieee->AsocRetryCount < RT_ASOC_RETRY_LIMIT) { ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ queue_work(ieee->wq, &ieee->associate_procedure_wq); ++#else ++ schedule_task(&ieee->associate_procedure_wq); ++#endif ++ } else { ++ ieee80211_associate_abort(ieee); ++ } ++ } ++ } ++ break; ++ ++ case IEEE80211_STYPE_ASSOC_REQ: ++ case IEEE80211_STYPE_REASSOC_REQ: ++ ++ if ((ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) && ++ ieee->iw_mode == IW_MODE_MASTER) ++ ++ ieee80211_rx_assoc_rq(ieee, skb); ++ break; ++ ++ case IEEE80211_STYPE_AUTH: ++ ++ if (ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE){ ++ if (ieee->state == IEEE80211_ASSOCIATING_AUTHENTICATING && ++ ieee->iw_mode == IW_MODE_INFRA){ ++ ++ IEEE80211_DEBUG_MGMT("Received authentication response"); ++ ++ if (0 == (errcode=auth_parse(skb, &challenge, &chlen))){ ++ if(ieee->open_wep || !challenge){ ++ ieee->state = IEEE80211_ASSOCIATING_AUTHENTICATED; ++ ieee->softmac_stats.rx_auth_rs_ok++; ++ if(!(ieee->pHTInfo->IOTAction&HT_IOT_ACT_PURE_N_MODE)) ++ { ++ if (!ieee->GetNmodeSupportBySecCfg(ieee->dev)) ++ { ++ // WEP or TKIP encryption ++ if(IsHTHalfNmodeAPs(ieee)) ++ { ++ bSupportNmode = true; ++ bHalfSupportNmode = true; ++ } ++ else ++ { ++ bSupportNmode = false; ++ bHalfSupportNmode = false; ++ } ++ printk("==========>to link with AP using SEC(%d, %d)", bSupportNmode, bHalfSupportNmode); ++ } ++ } ++ /* Dummy wirless mode setting to avoid encryption issue */ ++ if(bSupportNmode) { ++ //N mode setting ++ ieee->SetWirelessMode(ieee->dev, \ ++ ieee->current_network.mode); ++ }else{ ++ //b/g mode setting ++ /*TODO*/ ++ ieee->SetWirelessMode(ieee->dev, IEEE_G); ++ } ++ ++ if (ieee->current_network.mode == IEEE_N_24G && bHalfSupportNmode == true) ++ { ++ printk("===============>entern half N mode\n"); ++ ieee->bHalfWirelessN24GMode = true; ++ } ++ else ++ ieee->bHalfWirelessN24GMode = false; ++ ++ ieee80211_associate_step2(ieee); ++ }else{ ++ ieee80211_auth_challenge(ieee, challenge, chlen); ++ } ++ }else{ ++ ieee->softmac_stats.rx_auth_rs_err++; ++ IEEE80211_DEBUG_MGMT("Authentication respose status code 0x%x",errcode); ++ ++ printk("Authentication respose status code 0x%x",errcode); ++ ieee80211_associate_abort(ieee); ++ } ++ ++ }else if (ieee->iw_mode == IW_MODE_MASTER){ ++ ieee80211_rx_auth_rq(ieee, skb); ++ } ++ } ++ break; ++ ++ case IEEE80211_STYPE_PROBE_REQ: ++ ++ if ((ieee->softmac_features & IEEE_SOFTMAC_PROBERS) && ++ ((ieee->iw_mode == IW_MODE_ADHOC || ++ ieee->iw_mode == IW_MODE_MASTER) && ++ ieee->state == IEEE80211_LINKED)){ ++ ieee80211_rx_probe_rq(ieee, skb); ++ } ++ break; ++ ++ case IEEE80211_STYPE_DISASSOC: ++ case IEEE80211_STYPE_DEAUTH: ++ /* FIXME for now repeat all the association procedure ++ * both for disassociation and deauthentication ++ */ ++ if ((ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) && ++ ieee->state == IEEE80211_LINKED && ++ ieee->iw_mode == IW_MODE_INFRA){ ++ ++ ieee->state = IEEE80211_ASSOCIATING; ++ ieee->softmac_stats.reassoc++; ++ ieee->is_roaming = true; ++ ieee80211_disassociate(ieee); ++ // notify_wx_assoc_event(ieee); ++ //HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); ++ RemovePeerTS(ieee, header->addr2); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ queue_work(ieee->wq, &ieee->associate_procedure_wq); ++#else ++ schedule_task(&ieee->associate_procedure_wq); ++#endif ++ } ++ break; ++ case IEEE80211_STYPE_MANAGE_ACT: ++ ieee80211_process_action(ieee,skb); ++ break; ++ default: ++ return -1; ++ break; ++ } ++ ++ //dev_kfree_skb_any(skb); ++ return 0; ++} ++ ++/* following are for a simplier TX queue management. ++ * Instead of using netif_[stop/wake]_queue the driver ++ * will uses these two function (plus a reset one), that ++ * will internally uses the kernel netif_* and takes ++ * care of the ieee802.11 fragmentation. ++ * So the driver receives a fragment per time and might ++ * call the stop function when it want without take care ++ * to have enought room to TX an entire packet. ++ * This might be useful if each fragment need it's own ++ * descriptor, thus just keep a total free memory > than ++ * the max fragmentation treshold is not enought.. If the ++ * ieee802.11 stack passed a TXB struct then you needed ++ * to keep N free descriptors where ++ * N = MAX_PACKET_SIZE / MIN_FRAG_TRESHOLD ++ * In this way you need just one and the 802.11 stack ++ * will take care of buffering fragments and pass them to ++ * to the driver later, when it wakes the queue. ++ */ ++void ieee80211_softmac_xmit(struct ieee80211_txb *txb, struct ieee80211_device *ieee) ++{ ++ ++ unsigned int queue_index = txb->queue_index; ++ unsigned long flags; ++ int i; ++ cb_desc *tcb_desc = NULL; ++ ++ spin_lock_irqsave(&ieee->lock,flags); ++ ++ /* called with 2nd parm 0, no tx mgmt lock required */ ++ ieee80211_sta_wakeup(ieee,0); ++ ++ /* update the tx status */ ++// ieee->stats.tx_bytes += txb->payload_size; ++// ieee->stats.tx_packets++; ++ tcb_desc = (cb_desc *)(txb->fragments[0]->cb + MAX_DEV_ADDR_SIZE); ++ if(tcb_desc->bMulticast) { ++ ieee->stats.multicast++; ++ } ++#if 1 ++ /* if xmit available, just xmit it immediately, else just insert it to the wait queue */ ++ for(i = 0; i < txb->nr_frags; i++) { ++#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE ++ if ((skb_queue_len(&ieee->skb_drv_aggQ[queue_index]) != 0) || ++#else ++ if ((skb_queue_len(&ieee->skb_waitQ[queue_index]) != 0) || ++#endif ++ (!ieee->check_nic_enough_desc(ieee->dev,queue_index))||\ ++ (ieee->queue_stop)) { ++ /* insert the skb packet to the wait queue */ ++ /* as for the completion function, it does not need ++ * to check it any more. ++ * */ ++ //printk("error:no descriptor left@queue_index %d\n", queue_index); ++ //ieee80211_stop_queue(ieee); ++#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE ++ skb_queue_tail(&ieee->skb_drv_aggQ[queue_index], txb->fragments[i]); ++#else ++ skb_queue_tail(&ieee->skb_waitQ[queue_index], txb->fragments[i]); ++#endif ++ }else{ ++ ieee->softmac_data_hard_start_xmit( ++ txb->fragments[i], ++ ieee->dev,ieee->rate); ++ //ieee->stats.tx_packets++; ++ //ieee->stats.tx_bytes += txb->fragments[i]->len; ++ //ieee->dev->trans_start = jiffies; ++ } ++ } ++#endif ++ ieee80211_txb_free(txb); ++ ++//exit: ++ spin_unlock_irqrestore(&ieee->lock,flags); ++ ++} ++ ++/* called with ieee->lock acquired */ ++void ieee80211_resume_tx(struct ieee80211_device *ieee) ++{ ++ int i; ++ for(i = ieee->tx_pending.frag; i < ieee->tx_pending.txb->nr_frags; i++) { ++ ++ if (ieee->queue_stop){ ++ ieee->tx_pending.frag = i; ++ return; ++ }else{ ++ ++ ieee->softmac_data_hard_start_xmit( ++ ieee->tx_pending.txb->fragments[i], ++ ieee->dev,ieee->rate); ++ //(i+1)tx_pending.txb->nr_frags); ++ ieee->stats.tx_packets++; ++ // ieee->dev->trans_start = jiffies; ++ } ++ } ++ ++ ++ ieee80211_txb_free(ieee->tx_pending.txb); ++ ieee->tx_pending.txb = NULL; ++} ++ ++ ++void ieee80211_reset_queue(struct ieee80211_device *ieee) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ieee->lock,flags); ++ init_mgmt_queue(ieee); ++ if (ieee->tx_pending.txb){ ++ ieee80211_txb_free(ieee->tx_pending.txb); ++ ieee->tx_pending.txb = NULL; ++ } ++ ieee->queue_stop = 0; ++ spin_unlock_irqrestore(&ieee->lock,flags); ++ ++} ++ ++void ieee80211_wake_queue(struct ieee80211_device *ieee) ++{ ++ ++ unsigned long flags; ++ struct sk_buff *skb; ++ struct ieee80211_hdr_3addr *header; ++ ++ spin_lock_irqsave(&ieee->lock,flags); ++ if (! ieee->queue_stop) goto exit; ++ ++ ieee->queue_stop = 0; ++ ++ if(ieee->softmac_features & IEEE_SOFTMAC_SINGLE_QUEUE){ ++ while (!ieee->queue_stop && (skb = dequeue_mgmt(ieee))){ ++ ++ header = (struct ieee80211_hdr_3addr *) skb->data; ++ ++ header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4); ++ ++ if (ieee->seq_ctrl[0] == 0xFFF) ++ ieee->seq_ctrl[0] = 0; ++ else ++ ieee->seq_ctrl[0]++; ++ ++ ieee->softmac_data_hard_start_xmit(skb,ieee->dev,ieee->basic_rate); ++ //dev_kfree_skb_any(skb);//edit by thomas ++ } ++ } ++ if (!ieee->queue_stop && ieee->tx_pending.txb) ++ ieee80211_resume_tx(ieee); ++ ++ if (!ieee->queue_stop && netif_queue_stopped(ieee->dev)){ ++ ieee->softmac_stats.swtxawake++; ++ netif_wake_queue(ieee->dev); ++ } ++ ++exit : ++ spin_unlock_irqrestore(&ieee->lock,flags); ++} ++ ++ ++void ieee80211_stop_queue(struct ieee80211_device *ieee) ++{ ++ //unsigned long flags; ++ //spin_lock_irqsave(&ieee->lock,flags); ++ ++ if (! netif_queue_stopped(ieee->dev)){ ++ netif_stop_queue(ieee->dev); ++ ieee->softmac_stats.swtxstop++; ++ } ++ ieee->queue_stop = 1; ++ //spin_unlock_irqrestore(&ieee->lock,flags); ++ ++} ++ ++ ++inline void ieee80211_randomize_cell(struct ieee80211_device *ieee) ++{ ++ ++ get_random_bytes(ieee->current_network.bssid, ETH_ALEN); ++ ++ /* an IBSS cell address must have the two less significant ++ * bits of the first byte = 2 ++ */ ++ ieee->current_network.bssid[0] &= ~0x01; ++ ieee->current_network.bssid[0] |= 0x02; ++} ++ ++/* called in user context only */ ++void ieee80211_start_master_bss(struct ieee80211_device *ieee) ++{ ++ ieee->assoc_id = 1; ++ ++ if (ieee->current_network.ssid_len == 0){ ++ strncpy(ieee->current_network.ssid, ++ IEEE80211_DEFAULT_TX_ESSID, ++ IW_ESSID_MAX_SIZE); ++ ++ ieee->current_network.ssid_len = strlen(IEEE80211_DEFAULT_TX_ESSID); ++ ieee->ssid_set = 1; ++ } ++ ++ memcpy(ieee->current_network.bssid, ieee->dev->dev_addr, ETH_ALEN); ++ ++ ieee->set_chan(ieee->dev, ieee->current_network.channel); ++ ieee->state = IEEE80211_LINKED; ++ ieee->link_change(ieee->dev); ++ notify_wx_assoc_event(ieee); ++ ++ if (ieee->data_hard_resume) ++ ieee->data_hard_resume(ieee->dev); ++ ++ netif_carrier_on(ieee->dev); ++} ++ ++void ieee80211_start_monitor_mode(struct ieee80211_device *ieee) ++{ ++ if(ieee->raw_tx){ ++ ++ if (ieee->data_hard_resume) ++ ieee->data_hard_resume(ieee->dev); ++ ++ netif_carrier_on(ieee->dev); ++ } ++} ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void ieee80211_start_ibss_wq(struct work_struct *work) ++{ ++ ++ struct delayed_work *dwork = container_of(work, struct delayed_work, work); ++ struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, start_ibss_wq); ++#else ++void ieee80211_start_ibss_wq(struct ieee80211_device *ieee) ++{ ++#endif ++ /* iwconfig mode ad-hoc will schedule this and return ++ * on the other hand this will block further iwconfig SET ++ * operations because of the wx_sem hold. ++ * Anyway some most set operations set a flag to speed-up ++ * (abort) this wq (when syncro scanning) before sleeping ++ * on the semaphore ++ */ ++ if(!ieee->proto_started){ ++ printk("==========oh driver down return\n"); ++ return; ++ } ++ down(&ieee->wx_sem); ++ ++ if (ieee->current_network.ssid_len == 0){ ++ strcpy(ieee->current_network.ssid,IEEE80211_DEFAULT_TX_ESSID); ++ ieee->current_network.ssid_len = strlen(IEEE80211_DEFAULT_TX_ESSID); ++ ieee->ssid_set = 1; ++ } ++ ++ /* check if we have this cell in our network list */ ++ ieee80211_softmac_check_all_nets(ieee); ++ ++ ++#ifdef ENABLE_DOT11D //if creating an ad-hoc, set its channel to 10 temporarily--this is the requirement for ASUS, not 11D, so disable 11d. ++// if((IS_DOT11D_ENABLE(ieee)) && (ieee->state == IEEE80211_NOLINK)) ++ if (ieee->state == IEEE80211_NOLINK) ++ ieee->current_network.channel = 6; ++#endif ++ /* if not then the state is not linked. Maybe the user swithced to ++ * ad-hoc mode just after being in monitor mode, or just after ++ * being very few time in managed mode (so the card have had no ++ * time to scan all the chans..) or we have just run up the iface ++ * after setting ad-hoc mode. So we have to give another try.. ++ * Here, in ibss mode, should be safe to do this without extra care ++ * (in bss mode we had to make sure no-one tryed to associate when ++ * we had just checked the ieee->state and we was going to start the ++ * scan) beacause in ibss mode the ieee80211_new_net function, when ++ * finds a good net, just set the ieee->state to IEEE80211_LINKED, ++ * so, at worst, we waste a bit of time to initiate an unneeded syncro ++ * scan, that will stop at the first round because it sees the state ++ * associated. ++ */ ++ if (ieee->state == IEEE80211_NOLINK) ++ ieee80211_start_scan_syncro(ieee); ++ ++ /* the network definitively is not here.. create a new cell */ ++ if (ieee->state == IEEE80211_NOLINK){ ++ printk("creating new IBSS cell\n"); ++ if(!ieee->wap_set) ++ ieee80211_randomize_cell(ieee); ++ ++ if(ieee->modulation & IEEE80211_CCK_MODULATION){ ++ ++ ieee->current_network.rates_len = 4; ++ ++ ieee->current_network.rates[0] = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_1MB; ++ ieee->current_network.rates[1] = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_2MB; ++ ieee->current_network.rates[2] = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_5MB; ++ ieee->current_network.rates[3] = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_11MB; ++ ++ }else ++ ieee->current_network.rates_len = 0; ++ ++ if(ieee->modulation & IEEE80211_OFDM_MODULATION){ ++ ieee->current_network.rates_ex_len = 8; ++ ++ ieee->current_network.rates_ex[0] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_6MB; ++ ieee->current_network.rates_ex[1] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_9MB; ++ ieee->current_network.rates_ex[2] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_12MB; ++ ieee->current_network.rates_ex[3] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_18MB; ++ ieee->current_network.rates_ex[4] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_24MB; ++ ieee->current_network.rates_ex[5] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_36MB; ++ ieee->current_network.rates_ex[6] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_48MB; ++ ieee->current_network.rates_ex[7] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_54MB; ++ ++ ieee->rate = 108; ++ }else{ ++ ieee->current_network.rates_ex_len = 0; ++ ieee->rate = 22; ++ } ++ ++ // By default, WMM function will be disabled in IBSS mode ++ ieee->current_network.QoS_Enable = 0; ++ ieee->SetWirelessMode(ieee->dev, IEEE_G); ++ ieee->current_network.atim_window = 0; ++ ieee->current_network.capability = WLAN_CAPABILITY_IBSS; ++ if(ieee->short_slot) ++ ieee->current_network.capability |= WLAN_CAPABILITY_SHORT_SLOT; ++ ++ } ++ ++ ieee->state = IEEE80211_LINKED; ++ ++ ieee->set_chan(ieee->dev, ieee->current_network.channel); ++ ieee->link_change(ieee->dev); ++ ++ notify_wx_assoc_event(ieee); ++ ++ ieee80211_start_send_beacons(ieee); ++ ++ if (ieee->data_hard_resume) ++ ieee->data_hard_resume(ieee->dev); ++ netif_carrier_on(ieee->dev); ++ ++ up(&ieee->wx_sem); ++} ++ ++inline void ieee80211_start_ibss(struct ieee80211_device *ieee) ++{ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ queue_delayed_work(ieee->wq, &ieee->start_ibss_wq, 150); ++#else ++ schedule_task(&ieee->start_ibss_wq); ++#endif ++} ++ ++/* this is called only in user context, with wx_sem held */ ++void ieee80211_start_bss(struct ieee80211_device *ieee) ++{ ++ unsigned long flags; ++#ifdef ENABLE_DOT11D ++ // ++ // Ref: 802.11d 11.1.3.3 ++ // STA shall not start a BSS unless properly formed Beacon frame including a Country IE. ++ // ++ if(IS_DOT11D_ENABLE(ieee) && !IS_COUNTRY_IE_VALID(ieee)) ++ { ++ if(! ieee->bGlobalDomain) ++ { ++ return; ++ } ++ } ++#endif ++ /* check if we have already found the net we ++ * are interested in (if any). ++ * if not (we are disassociated and we are not ++ * in associating / authenticating phase) start the background scanning. ++ */ ++ ieee80211_softmac_check_all_nets(ieee); ++ ++ /* ensure no-one start an associating process (thus setting ++ * the ieee->state to ieee80211_ASSOCIATING) while we ++ * have just cheked it and we are going to enable scan. ++ * The ieee80211_new_net function is always called with ++ * lock held (from both ieee80211_softmac_check_all_nets and ++ * the rx path), so we cannot be in the middle of such function ++ */ ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ if (ieee->state == IEEE80211_NOLINK){ ++ ieee->actscanning = true; ++ ieee80211_start_scan(ieee); ++ } ++ spin_unlock_irqrestore(&ieee->lock, flags); ++} ++ ++/* called only in userspace context */ ++void ieee80211_disassociate(struct ieee80211_device *ieee) ++{ ++ ++ ++ netif_carrier_off(ieee->dev); ++ if (ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE) ++ ieee80211_reset_queue(ieee); ++ ++ if (ieee->data_hard_stop) ++ ieee->data_hard_stop(ieee->dev); ++#ifdef ENABLE_DOT11D ++ if(IS_DOT11D_ENABLE(ieee)) ++ Dot11d_Reset(ieee); ++#endif ++ ieee->state = IEEE80211_NOLINK; ++ ieee->is_set_key = false; ++ ieee->link_change(ieee->dev); ++ //HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); ++ notify_wx_assoc_event(ieee); ++ ++} ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void ieee80211_associate_retry_wq(struct work_struct *work) ++{ ++ struct delayed_work *dwork = container_of(work, struct delayed_work, work); ++ struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, associate_retry_wq); ++#else ++void ieee80211_associate_retry_wq(struct ieee80211_device *ieee) ++{ ++#endif ++ unsigned long flags; ++ ++ down(&ieee->wx_sem); ++ if(!ieee->proto_started) ++ goto exit; ++ ++ if(ieee->state != IEEE80211_ASSOCIATING_RETRY) ++ goto exit; ++ ++ /* until we do not set the state to IEEE80211_NOLINK ++ * there are no possibility to have someone else trying ++ * to start an association procdure (we get here with ++ * ieee->state = IEEE80211_ASSOCIATING). ++ * When we set the state to IEEE80211_NOLINK it is possible ++ * that the RX path run an attempt to associate, but ++ * both ieee80211_softmac_check_all_nets and the ++ * RX path works with ieee->lock held so there are no ++ * problems. If we are still disassociated then start a scan. ++ * the lock here is necessary to ensure no one try to start ++ * an association procedure when we have just checked the ++ * state and we are going to start the scan. ++ */ ++ ieee->beinretry = true; ++ ieee->state = IEEE80211_NOLINK; ++ ++ ieee80211_softmac_check_all_nets(ieee); ++ ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ if(ieee->state == IEEE80211_NOLINK) ++ { ++ ieee->is_roaming= false; ++ ieee->actscanning = true; ++ ieee80211_start_scan(ieee); ++ } ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ ++ ieee->beinretry = false; ++exit: ++ up(&ieee->wx_sem); ++} ++ ++struct sk_buff *ieee80211_get_beacon_(struct ieee80211_device *ieee) ++{ ++ u8 broadcast_addr[] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++ ++ struct sk_buff *skb; ++ struct ieee80211_probe_response *b; ++ ++ skb = ieee80211_probe_resp(ieee, broadcast_addr); ++ ++ if (!skb) ++ return NULL; ++ ++ b = (struct ieee80211_probe_response *) skb->data; ++ b->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_BEACON); ++ ++ return skb; ++ ++} ++ ++struct sk_buff *ieee80211_get_beacon(struct ieee80211_device *ieee) ++{ ++ struct sk_buff *skb; ++ struct ieee80211_probe_response *b; ++ ++ skb = ieee80211_get_beacon_(ieee); ++ if(!skb) ++ return NULL; ++ ++ b = (struct ieee80211_probe_response *) skb->data; ++ b->header.seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4); ++ ++ if (ieee->seq_ctrl[0] == 0xFFF) ++ ieee->seq_ctrl[0] = 0; ++ else ++ ieee->seq_ctrl[0]++; ++ ++ return skb; ++} ++ ++void ieee80211_softmac_stop_protocol(struct ieee80211_device *ieee) ++{ ++ ieee->sync_scan_hurryup = 1; ++ down(&ieee->wx_sem); ++ ieee80211_stop_protocol(ieee); ++ up(&ieee->wx_sem); ++} ++ ++ ++void ieee80211_stop_protocol(struct ieee80211_device *ieee) ++{ ++ if (!ieee->proto_started) ++ return; ++ ++ ieee->proto_started = 0; ++ ++ ieee80211_stop_send_beacons(ieee); ++ del_timer_sync(&ieee->associate_timer); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ cancel_delayed_work(&ieee->associate_retry_wq); ++ cancel_delayed_work(&ieee->start_ibss_wq); ++#endif ++ ieee80211_stop_scan(ieee); ++ ++ ieee80211_disassociate(ieee); ++ RemoveAllTS(ieee); //added as we disconnect from the previous BSS, Remove all TS ++} ++ ++void ieee80211_softmac_start_protocol(struct ieee80211_device *ieee) ++{ ++ ieee->sync_scan_hurryup = 0; ++ down(&ieee->wx_sem); ++ ieee80211_start_protocol(ieee); ++ up(&ieee->wx_sem); ++} ++ ++void ieee80211_start_protocol(struct ieee80211_device *ieee) ++{ ++ short ch = 0; ++ int i = 0; ++ if (ieee->proto_started) ++ return; ++ ++ ieee->proto_started = 1; ++ ++ if (ieee->current_network.channel == 0){ ++ do{ ++ ch++; ++ if (ch > MAX_CHANNEL_NUMBER) ++ return; /* no channel found */ ++#ifdef ENABLE_DOT11D ++ }while(!GET_DOT11D_INFO(ieee)->channel_map[ch]); ++#else ++ }while(!ieee->channel_map[ch]); ++#endif ++ ieee->current_network.channel = ch; ++ } ++ ++ if (ieee->current_network.beacon_interval == 0) ++ ieee->current_network.beacon_interval = 100; ++// printk("===>%s(), chan:%d\n", __FUNCTION__, ieee->current_network.channel); ++// ieee->set_chan(ieee->dev,ieee->current_network.channel); ++ ++ for(i = 0; i < 17; i++) { ++ ieee->last_rxseq_num[i] = -1; ++ ieee->last_rxfrag_num[i] = -1; ++ ieee->last_packet_time[i] = 0; ++ } ++ ++ ieee->init_wmmparam_flag = 0;//reinitialize AC_xx_PARAM registers. ++ ++ ++ /* if the user set the MAC of the ad-hoc cell and then ++ * switch to managed mode, shall we make sure that association ++ * attempts does not fail just because the user provide the essid ++ * and the nic is still checking for the AP MAC ?? ++ */ ++ if (ieee->iw_mode == IW_MODE_INFRA) ++ ieee80211_start_bss(ieee); ++ ++ else if (ieee->iw_mode == IW_MODE_ADHOC) ++ ieee80211_start_ibss(ieee); ++ ++ else if (ieee->iw_mode == IW_MODE_MASTER) ++ ieee80211_start_master_bss(ieee); ++ ++ else if(ieee->iw_mode == IW_MODE_MONITOR) ++ ieee80211_start_monitor_mode(ieee); ++} ++ ++ ++#define DRV_NAME "Ieee80211" ++void ieee80211_softmac_init(struct ieee80211_device *ieee) ++{ ++ int i; ++ memset(&ieee->current_network, 0, sizeof(struct ieee80211_network)); ++ ++ ieee->state = IEEE80211_NOLINK; ++ ieee->sync_scan_hurryup = 0; ++ for(i = 0; i < 5; i++) { ++ ieee->seq_ctrl[i] = 0; ++ } ++#ifdef ENABLE_DOT11D ++ ieee->pDot11dInfo = kmalloc(sizeof(RT_DOT11D_INFO), GFP_ATOMIC); ++ if (!ieee->pDot11dInfo) ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't alloc memory for DOT11D\n"); ++ memset(ieee->pDot11dInfo, 0, sizeof(RT_DOT11D_INFO)); ++#endif ++ //added for AP roaming ++ ieee->LinkDetectInfo.SlotNum = 2; ++ ieee->LinkDetectInfo.NumRecvBcnInPeriod=0; ++ ieee->LinkDetectInfo.NumRecvDataInPeriod=0; ++ ++ ieee->assoc_id = 0; ++ ieee->queue_stop = 0; ++ ieee->scanning = 0; ++ ieee->softmac_features = 0; //so IEEE2100-like driver are happy ++ ieee->wap_set = 0; ++ ieee->ssid_set = 0; ++ ieee->proto_started = 0; ++ ieee->basic_rate = IEEE80211_DEFAULT_BASIC_RATE; ++ ieee->rate = 22; ++ ieee->ps = IEEE80211_PS_DISABLED; ++ ieee->sta_sleep = 0; ++ ieee->Regdot11HTOperationalRateSet[0]= 0xff;//support MCS 0~7 ++ ieee->Regdot11HTOperationalRateSet[1]= 0xff;//support MCS 8~15 ++ ieee->Regdot11HTOperationalRateSet[4]= 0x01; ++ //added by amy ++ ieee->actscanning = false; ++ ieee->beinretry = false; ++ ieee->is_set_key = false; ++ init_mgmt_queue(ieee); ++ ++ ieee->sta_edca_param[0] = 0x0000A403; ++ ieee->sta_edca_param[1] = 0x0000A427; ++ ieee->sta_edca_param[2] = 0x005E4342; ++ ieee->sta_edca_param[3] = 0x002F3262; ++ ieee->aggregation = true; ++ ieee->enable_rx_imm_BA = 1; ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++ init_timer(&ieee->scan_timer); ++ ieee->scan_timer.data = (unsigned long)ieee; ++ ieee->scan_timer.function = ieee80211_softmac_scan_cb; ++#endif ++ ieee->tx_pending.txb = NULL; ++ ++ init_timer(&ieee->associate_timer); ++ ieee->associate_timer.data = (unsigned long)ieee; ++ ieee->associate_timer.function = ieee80211_associate_abort_cb; ++ ++ init_timer(&ieee->beacon_timer); ++ ieee->beacon_timer.data = (unsigned long) ieee; ++ ieee->beacon_timer.function = ieee80211_send_beacon_cb; ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++#ifdef PF_SYNCTHREAD ++ ieee->wq = create_workqueue(DRV_NAME,0); ++#else ++ ieee->wq = create_workqueue(DRV_NAME); ++#endif ++#endif ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_DELAYED_WORK(&ieee->start_ibss_wq,ieee80211_start_ibss_wq); ++ INIT_WORK(&ieee->associate_complete_wq, ieee80211_associate_complete_wq); ++ INIT_WORK(&ieee->associate_procedure_wq, ieee80211_associate_procedure_wq); ++ INIT_DELAYED_WORK(&ieee->softmac_scan_wq,ieee80211_softmac_scan_wq); ++ INIT_DELAYED_WORK(&ieee->associate_retry_wq, ieee80211_associate_retry_wq); ++ INIT_WORK(&ieee->wx_sync_scan_wq,ieee80211_wx_sync_scan_wq); ++ ++#else ++ INIT_WORK(&ieee->start_ibss_wq,(void(*)(void*)) ieee80211_start_ibss_wq,ieee); ++ INIT_WORK(&ieee->associate_retry_wq,(void(*)(void*)) ieee80211_associate_retry_wq,ieee); ++ INIT_WORK(&ieee->associate_complete_wq,(void(*)(void*)) ieee80211_associate_complete_wq,ieee); ++ INIT_WORK(&ieee->associate_procedure_wq,(void(*)(void*)) ieee80211_associate_procedure_wq,ieee); ++ INIT_WORK(&ieee->softmac_scan_wq,(void(*)(void*)) ieee80211_softmac_scan_wq,ieee); ++ INIT_WORK(&ieee->wx_sync_scan_wq,(void(*)(void*)) ieee80211_wx_sync_scan_wq,ieee); ++#endif ++ ++#else ++ tq_init(&ieee->start_ibss_wq,(void(*)(void*)) ieee80211_start_ibss_wq,ieee); ++ tq_init(&ieee->associate_retry_wq,(void(*)(void*)) ieee80211_associate_retry_wq,ieee); ++ tq_init(&ieee->associate_complete_wq,(void(*)(void*)) ieee80211_associate_complete_wq,ieee); ++ tq_init(&ieee->associate_procedure_wq,(void(*)(void*)) ieee80211_associate_procedure_wq,ieee); ++ tq_init(&ieee->softmac_scan_wq,(void(*)(void*)) ieee80211_softmac_scan_wq,ieee); ++ tq_init(&ieee->wx_sync_scan_wq,(void(*)(void*)) ieee80211_wx_sync_scan_wq,ieee); ++#endif ++ sema_init(&ieee->wx_sem, 1); ++ sema_init(&ieee->scan_sem, 1); ++ ++ spin_lock_init(&ieee->mgmt_tx_lock); ++ spin_lock_init(&ieee->beacon_lock); ++ ++ tasklet_init(&ieee->ps_task, ++ (void(*)(unsigned long)) ieee80211_sta_ps, ++ (unsigned long)ieee); ++ ++} ++ ++void ieee80211_softmac_free(struct ieee80211_device *ieee) ++{ ++ down(&ieee->wx_sem); ++#ifdef ENABLE_DOT11D ++ if(NULL != ieee->pDot11dInfo) ++ { ++ kfree(ieee->pDot11dInfo); ++ ieee->pDot11dInfo = NULL; ++ } ++#endif ++ del_timer_sync(&ieee->associate_timer); ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ cancel_delayed_work(&ieee->associate_retry_wq); ++ destroy_workqueue(ieee->wq); ++#endif ++ ++ up(&ieee->wx_sem); ++} ++ ++/******************************************************** ++ * Start of WPA code. * ++ * this is stolen from the ipw2200 driver * ++ ********************************************************/ ++ ++ ++static int ieee80211_wpa_enable(struct ieee80211_device *ieee, int value) ++{ ++ /* This is called when wpa_supplicant loads and closes the driver ++ * interface. */ ++ printk("%s WPA\n",value ? "enabling" : "disabling"); ++ ieee->wpa_enabled = value; ++ return 0; ++} ++ ++ ++void ieee80211_wpa_assoc_frame(struct ieee80211_device *ieee, char *wpa_ie, int wpa_ie_len) ++{ ++ /* make sure WPA is enabled */ ++ ieee80211_wpa_enable(ieee, 1); ++ ++ ieee80211_disassociate(ieee); ++} ++ ++ ++static int ieee80211_wpa_mlme(struct ieee80211_device *ieee, int command, int reason) ++{ ++ ++ int ret = 0; ++ ++ switch (command) { ++ case IEEE_MLME_STA_DEAUTH: ++ // silently ignore ++ break; ++ ++ case IEEE_MLME_STA_DISASSOC: ++ ieee80211_disassociate(ieee); ++ break; ++ ++ default: ++ printk("Unknown MLME request: %d\n", command); ++ ret = -EOPNOTSUPP; ++ } ++ ++ return ret; ++} ++ ++ ++static int ieee80211_wpa_set_wpa_ie(struct ieee80211_device *ieee, ++ struct ieee_param *param, int plen) ++{ ++ u8 *buf; ++ ++ if (param->u.wpa_ie.len > MAX_WPA_IE_LEN || ++ (param->u.wpa_ie.len && param->u.wpa_ie.data == NULL)) ++ return -EINVAL; ++ ++ if (param->u.wpa_ie.len) { ++ buf = kmalloc(param->u.wpa_ie.len, GFP_KERNEL); ++ if (buf == NULL) ++ return -ENOMEM; ++ ++ memcpy(buf, param->u.wpa_ie.data, param->u.wpa_ie.len); ++ kfree(ieee->wpa_ie); ++ ieee->wpa_ie = buf; ++ ieee->wpa_ie_len = param->u.wpa_ie.len; ++ } else { ++ kfree(ieee->wpa_ie); ++ ieee->wpa_ie = NULL; ++ ieee->wpa_ie_len = 0; ++ } ++ ++ ieee80211_wpa_assoc_frame(ieee, ieee->wpa_ie, ieee->wpa_ie_len); ++ return 0; ++} ++ ++#define AUTH_ALG_OPEN_SYSTEM 0x1 ++#define AUTH_ALG_SHARED_KEY 0x2 ++ ++static int ieee80211_wpa_set_auth_algs(struct ieee80211_device *ieee, int value) ++{ ++ ++ struct ieee80211_security sec = { ++ .flags = SEC_AUTH_MODE, ++ }; ++ int ret = 0; ++ ++ if (value & AUTH_ALG_SHARED_KEY) { ++ sec.auth_mode = WLAN_AUTH_SHARED_KEY; ++ ieee->open_wep = 0; ++ ieee->auth_mode = 1; ++ } else if (value & AUTH_ALG_OPEN_SYSTEM){ ++ sec.auth_mode = WLAN_AUTH_OPEN; ++ ieee->open_wep = 1; ++ ieee->auth_mode = 0; ++ } ++ else if (value & IW_AUTH_ALG_LEAP){ ++ sec.auth_mode = WLAN_AUTH_LEAP; ++ ieee->open_wep = 1; ++ ieee->auth_mode = 2; ++ } ++ ++ ++ if (ieee->set_security) ++ ieee->set_security(ieee->dev, &sec); ++ //else ++ // ret = -EOPNOTSUPP; ++ ++ return ret; ++} ++ ++static int ieee80211_wpa_set_param(struct ieee80211_device *ieee, u8 name, u32 value) ++{ ++ int ret=0; ++ unsigned long flags; ++ ++ switch (name) { ++ case IEEE_PARAM_WPA_ENABLED: ++ ret = ieee80211_wpa_enable(ieee, value); ++ break; ++ ++ case IEEE_PARAM_TKIP_COUNTERMEASURES: ++ ieee->tkip_countermeasures=value; ++ break; ++ ++ case IEEE_PARAM_DROP_UNENCRYPTED: { ++ /* HACK: ++ * ++ * wpa_supplicant calls set_wpa_enabled when the driver ++ * is loaded and unloaded, regardless of if WPA is being ++ * used. No other calls are made which can be used to ++ * determine if encryption will be used or not prior to ++ * association being expected. If encryption is not being ++ * used, drop_unencrypted is set to false, else true -- we ++ * can use this to determine if the CAP_PRIVACY_ON bit should ++ * be set. ++ */ ++ struct ieee80211_security sec = { ++ .flags = SEC_ENABLED, ++ .enabled = value, ++ }; ++ ieee->drop_unencrypted = value; ++ /* We only change SEC_LEVEL for open mode. Others ++ * are set by ipw_wpa_set_encryption. ++ */ ++ if (!value) { ++ sec.flags |= SEC_LEVEL; ++ sec.level = SEC_LEVEL_0; ++ } ++ else { ++ sec.flags |= SEC_LEVEL; ++ sec.level = SEC_LEVEL_1; ++ } ++ if (ieee->set_security) ++ ieee->set_security(ieee->dev, &sec); ++ break; ++ } ++ ++ case IEEE_PARAM_PRIVACY_INVOKED: ++ ieee->privacy_invoked=value; ++ break; ++ ++ case IEEE_PARAM_AUTH_ALGS: ++ ret = ieee80211_wpa_set_auth_algs(ieee, value); ++ break; ++ ++ case IEEE_PARAM_IEEE_802_1X: ++ ieee->ieee802_1x=value; ++ break; ++ case IEEE_PARAM_WPAX_SELECT: ++ // added for WPA2 mixed mode ++ spin_lock_irqsave(&ieee->wpax_suitlist_lock,flags); ++ ieee->wpax_type_set = 1; ++ ieee->wpax_type_notify = value; ++ spin_unlock_irqrestore(&ieee->wpax_suitlist_lock,flags); ++ break; ++ ++ default: ++ printk("Unknown WPA param: %d\n",name); ++ ret = -EOPNOTSUPP; ++ } ++ ++ return ret; ++} ++ ++/* implementation borrowed from hostap driver */ ++ ++static int ieee80211_wpa_set_encryption(struct ieee80211_device *ieee, ++ struct ieee_param *param, int param_len) ++{ ++ int ret = 0; ++ ++ struct ieee80211_crypto_ops *ops; ++ struct ieee80211_crypt_data **crypt; ++ ++ struct ieee80211_security sec = { ++ .flags = 0, ++ }; ++ ++ param->u.crypt.err = 0; ++ param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; ++ ++ if (param_len != ++ (int) ((char *) param->u.crypt.key - (char *) param) + ++ param->u.crypt.key_len) { ++ printk("Len mismatch %d, %d\n", param_len, ++ param->u.crypt.key_len); ++ return -EINVAL; ++ } ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { ++ if (param->u.crypt.idx >= WEP_KEYS) ++ return -EINVAL; ++ crypt = &ieee->crypt[param->u.crypt.idx]; ++ } else { ++ return -EINVAL; ++ } ++ ++ if (strcmp(param->u.crypt.alg, "none") == 0) { ++ if (crypt) { ++ sec.enabled = 0; ++ // FIXME FIXME ++ //sec.encrypt = 0; ++ sec.level = SEC_LEVEL_0; ++ sec.flags |= SEC_ENABLED | SEC_LEVEL; ++ ieee80211_crypt_delayed_deinit(ieee, crypt); ++ } ++ goto done; ++ } ++ sec.enabled = 1; ++// FIXME FIXME ++// sec.encrypt = 1; ++ sec.flags |= SEC_ENABLED; ++ ++ /* IPW HW cannot build TKIP MIC, host decryption still needed. */ ++ if (!(ieee->host_encrypt || ieee->host_decrypt) && ++ strcmp(param->u.crypt.alg, "TKIP")) ++ goto skip_host_crypt; ++ ++ ops = ieee80211_get_crypto_ops(param->u.crypt.alg); ++ if (ops == NULL && strcmp(param->u.crypt.alg, "WEP") == 0) { ++ request_module("ieee80211_crypt_wep"); ++ ops = ieee80211_get_crypto_ops(param->u.crypt.alg); ++ //set WEP40 first, it will be modified according to WEP104 or WEP40 at other place ++ } else if (ops == NULL && strcmp(param->u.crypt.alg, "TKIP") == 0) { ++ request_module("ieee80211_crypt_tkip"); ++ ops = ieee80211_get_crypto_ops(param->u.crypt.alg); ++ } else if (ops == NULL && strcmp(param->u.crypt.alg, "CCMP") == 0) { ++ request_module("ieee80211_crypt_ccmp"); ++ ops = ieee80211_get_crypto_ops(param->u.crypt.alg); ++ } ++ if (ops == NULL) { ++ printk("unknown crypto alg '%s'\n", param->u.crypt.alg); ++ param->u.crypt.err = IEEE_CRYPT_ERR_UNKNOWN_ALG; ++ ret = -EINVAL; ++ goto done; ++ } ++ ++ if (*crypt == NULL || (*crypt)->ops != ops) { ++ struct ieee80211_crypt_data *new_crypt; ++ ++ ieee80211_crypt_delayed_deinit(ieee, crypt); ++ ++ new_crypt = (struct ieee80211_crypt_data *) ++ kmalloc(sizeof(*new_crypt), GFP_KERNEL); ++ if (new_crypt == NULL) { ++ ret = -ENOMEM; ++ goto done; ++ } ++ memset(new_crypt, 0, sizeof(struct ieee80211_crypt_data)); ++ new_crypt->ops = ops; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) ++ if (new_crypt->ops && try_module_get(new_crypt->ops->owner)) ++#else ++ if (new_crypt->ops && try_inc_mod_count(new_crypt->ops->owner)) ++#endif ++ new_crypt->priv = ++ new_crypt->ops->init(param->u.crypt.idx); ++ ++ if (new_crypt->priv == NULL) { ++ kfree(new_crypt); ++ param->u.crypt.err = IEEE_CRYPT_ERR_CRYPT_INIT_FAILED; ++ ret = -EINVAL; ++ goto done; ++ } ++ ++ *crypt = new_crypt; ++ } ++ ++ if (param->u.crypt.key_len > 0 && (*crypt)->ops->set_key && ++ (*crypt)->ops->set_key(param->u.crypt.key, ++ param->u.crypt.key_len, param->u.crypt.seq, ++ (*crypt)->priv) < 0) { ++ printk("key setting failed\n"); ++ param->u.crypt.err = IEEE_CRYPT_ERR_KEY_SET_FAILED; ++ ret = -EINVAL; ++ goto done; ++ } ++ ++ skip_host_crypt: ++ if (param->u.crypt.set_tx) { ++ ieee->tx_keyidx = param->u.crypt.idx; ++ sec.active_key = param->u.crypt.idx; ++ sec.flags |= SEC_ACTIVE_KEY; ++ } else ++ sec.flags &= ~SEC_ACTIVE_KEY; ++ ++ if (param->u.crypt.alg != NULL) { ++ memcpy(sec.keys[param->u.crypt.idx], ++ param->u.crypt.key, ++ param->u.crypt.key_len); ++ sec.key_sizes[param->u.crypt.idx] = param->u.crypt.key_len; ++ sec.flags |= (1 << param->u.crypt.idx); ++ ++ if (strcmp(param->u.crypt.alg, "WEP") == 0) { ++ sec.flags |= SEC_LEVEL; ++ sec.level = SEC_LEVEL_1; ++ } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { ++ sec.flags |= SEC_LEVEL; ++ sec.level = SEC_LEVEL_2; ++ } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { ++ sec.flags |= SEC_LEVEL; ++ sec.level = SEC_LEVEL_3; ++ } ++ } ++ done: ++ if (ieee->set_security) ++ ieee->set_security(ieee->dev, &sec); ++ ++ /* Do not reset port if card is in Managed mode since resetting will ++ * generate new IEEE 802.11 authentication which may end up in looping ++ * with IEEE 802.1X. If your hardware requires a reset after WEP ++ * configuration (for example... Prism2), implement the reset_port in ++ * the callbacks structures used to initialize the 802.11 stack. */ ++ if (ieee->reset_on_keychange && ++ ieee->iw_mode != IW_MODE_INFRA && ++ ieee->reset_port && ++ ieee->reset_port(ieee->dev)) { ++ printk("reset_port failed\n"); ++ param->u.crypt.err = IEEE_CRYPT_ERR_CARD_CONF_FAILED; ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ ++inline struct sk_buff *ieee80211_disassociate_skb( ++ struct ieee80211_network *beacon, ++ struct ieee80211_device *ieee, ++ u8 asRsn) ++{ ++ struct sk_buff *skb; ++ struct ieee80211_disassoc *disass; ++ ++ skb = dev_alloc_skb(sizeof(struct ieee80211_disassoc)); ++ if (!skb) ++ return NULL; ++ ++ disass = (struct ieee80211_disassoc *) skb_put(skb,sizeof(struct ieee80211_disassoc)); ++ disass->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_DISASSOC); ++ disass->header.duration_id = 0; ++ ++ memcpy(disass->header.addr1, beacon->bssid, ETH_ALEN); ++ memcpy(disass->header.addr2, ieee->dev->dev_addr, ETH_ALEN); ++ memcpy(disass->header.addr3, beacon->bssid, ETH_ALEN); ++ ++ disass->reason = asRsn; ++ return skb; ++} ++ ++ ++void ++SendDisassociation( ++ struct ieee80211_device *ieee, ++ u8* asSta, ++ u8 asRsn ++) ++{ ++ struct ieee80211_network *beacon = &ieee->current_network; ++ struct sk_buff *skb; ++ skb = ieee80211_disassociate_skb(beacon,ieee,asRsn); ++ if (skb){ ++ softmac_mgmt_xmit(skb, ieee); ++ //dev_kfree_skb_any(skb);//edit by thomas ++ } ++} ++ ++int ieee80211_wpa_supplicant_ioctl(struct ieee80211_device *ieee, struct iw_point *p) ++{ ++ struct ieee_param *param; ++ int ret=0; ++ ++ down(&ieee->wx_sem); ++ //IEEE_DEBUG_INFO("wpa_supplicant: len=%d\n", p->length); ++ ++ if (p->length < sizeof(struct ieee_param) || !p->pointer){ ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ param = (struct ieee_param *)kmalloc(p->length, GFP_KERNEL); ++ if (param == NULL){ ++ ret = -ENOMEM; ++ goto out; ++ } ++ if (copy_from_user(param, p->pointer, p->length)) { ++ kfree(param); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ switch (param->cmd) { ++ ++ case IEEE_CMD_SET_WPA_PARAM: ++ ret = ieee80211_wpa_set_param(ieee, param->u.wpa_param.name, ++ param->u.wpa_param.value); ++ break; ++ ++ case IEEE_CMD_SET_WPA_IE: ++ ret = ieee80211_wpa_set_wpa_ie(ieee, param, p->length); ++ break; ++ ++ case IEEE_CMD_SET_ENCRYPTION: ++ ret = ieee80211_wpa_set_encryption(ieee, param, p->length); ++ break; ++ ++ case IEEE_CMD_MLME: ++ ret = ieee80211_wpa_mlme(ieee, param->u.mlme.command, ++ param->u.mlme.reason_code); ++ break; ++ ++ default: ++ printk("Unknown WPA supplicant request: %d\n",param->cmd); ++ ret = -EOPNOTSUPP; ++ break; ++ } ++ ++ if (ret == 0 && copy_to_user(p->pointer, param, p->length)) ++ ret = -EFAULT; ++ ++ kfree(param); ++out: ++ up(&ieee->wx_sem); ++ ++ return ret; ++} ++ ++void notify_wx_assoc_event(struct ieee80211_device *ieee) ++{ ++ union iwreq_data wrqu; ++ wrqu.ap_addr.sa_family = ARPHRD_ETHER; ++ if (ieee->state == IEEE80211_LINKED) ++ memcpy(wrqu.ap_addr.sa_data, ieee->current_network.bssid, ETH_ALEN); ++ else ++ memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN); ++ wireless_send_event(ieee->dev, SIOCGIWAP, &wrqu, NULL); ++} ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++//EXPORT_SYMBOL(ieee80211_get_beacon); ++//EXPORT_SYMBOL(ieee80211_wake_queue); ++//EXPORT_SYMBOL(ieee80211_stop_queue); ++//EXPORT_SYMBOL(ieee80211_reset_queue); ++//EXPORT_SYMBOL(ieee80211_softmac_stop_protocol); ++//EXPORT_SYMBOL(ieee80211_softmac_start_protocol); ++//EXPORT_SYMBOL(ieee80211_is_shortslot); ++//EXPORT_SYMBOL(ieee80211_is_54g); ++//EXPORT_SYMBOL(ieee80211_wpa_supplicant_ioctl); ++//EXPORT_SYMBOL(ieee80211_ps_tx_ack); ++//EXPORT_SYMBOL(ieee80211_softmac_xmit); ++//EXPORT_SYMBOL(ieee80211_stop_send_beacons); ++//EXPORT_SYMBOL(notify_wx_assoc_event); ++//EXPORT_SYMBOL(SendDisassociation); ++//EXPORT_SYMBOL(ieee80211_disassociate); ++//EXPORT_SYMBOL(ieee80211_start_send_beacons); ++//EXPORT_SYMBOL(ieee80211_stop_scan); ++//EXPORT_SYMBOL(ieee80211_send_probe_requests); ++//EXPORT_SYMBOL(ieee80211_softmac_scan_syncro); ++//EXPORT_SYMBOL(ieee80211_start_scan_syncro); ++#else ++EXPORT_SYMBOL_NOVERS(ieee80211_get_beacon); ++EXPORT_SYMBOL_NOVERS(ieee80211_wake_queue); ++EXPORT_SYMBOL_NOVERS(ieee80211_stop_queue); ++EXPORT_SYMBOL_NOVERS(ieee80211_reset_queue); ++EXPORT_SYMBOL_NOVERS(ieee80211_softmac_stop_protocol); ++EXPORT_SYMBOL_NOVERS(ieee80211_softmac_start_protocol); ++EXPORT_SYMBOL_NOVERS(ieee80211_is_shortslot); ++EXPORT_SYMBOL_NOVERS(ieee80211_is_54g); ++EXPORT_SYMBOL_NOVERS(ieee80211_wpa_supplicant_ioctl); ++EXPORT_SYMBOL_NOVERS(ieee80211_ps_tx_ack); ++EXPORT_SYMBOL_NOVERS(ieee80211_softmac_xmit); ++EXPORT_SYMBOL_NOVERS(ieee80211_stop_send_beacons); ++EXPORT_SYMBOL_NOVERS(notify_wx_assoc_event); ++EXPORT_SYMBOL_NOVERS(SendDisassociation); ++EXPORT_SYMBOL_NOVERS(ieee80211_disassociate); ++EXPORT_SYMBOL_NOVERS(ieee80211_start_send_beacons); ++EXPORT_SYMBOL_NOVERS(ieee80211_stop_scan); ++EXPORT_SYMBOL_NOVERS(ieee80211_send_probe_requests); ++EXPORT_SYMBOL_NOVERS(ieee80211_softmac_scan_syncro); ++EXPORT_SYMBOL_NOVERS(ieee80211_start_scan_syncro); ++#endif ++//EXPORT_SYMBOL(ieee80211_sta_ps_send_null_frame); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac_wx.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac_wx.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac_wx.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,692 @@ ++/* IEEE 802.11 SoftMAC layer ++ * Copyright (c) 2005 Andrea Merello ++ * ++ * Mostly extracted from the rtl8180-sa2400 driver for the ++ * in-kernel generic ieee802.11 stack. ++ * ++ * Some pieces of code might be stolen from ipw2100 driver ++ * copyright of who own it's copyright ;-) ++ * ++ * PS wx handler mostly stolen from hostap, copyright who ++ * own it's copyright ;-) ++ * ++ * released under the GPL ++ */ ++ ++ ++#include "ieee80211.h" ++#ifdef ENABLE_DOT11D ++#include "dot11d.h" ++#endif ++/* FIXME: add A freqs */ ++ ++const long ieee80211_wlan_frequencies[] = { ++ 2412, 2417, 2422, 2427, ++ 2432, 2437, 2442, 2447, ++ 2452, 2457, 2462, 2467, ++ 2472, 2484 ++}; ++ ++ ++int ieee80211_wx_set_freq(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ int ret; ++ struct iw_freq *fwrq = & wrqu->freq; ++ ++ down(&ieee->wx_sem); ++ ++ if(ieee->iw_mode == IW_MODE_INFRA){ ++ ret = -EOPNOTSUPP; ++ goto out; ++ } ++ ++ /* if setting by freq convert to channel */ ++ if (fwrq->e == 1) { ++ if ((fwrq->m >= (int) 2.412e8 && ++ fwrq->m <= (int) 2.487e8)) { ++ int f = fwrq->m / 100000; ++ int c = 0; ++ ++ while ((c < 14) && (f != ieee80211_wlan_frequencies[c])) ++ c++; ++ ++ /* hack to fall through */ ++ fwrq->e = 0; ++ fwrq->m = c + 1; ++ } ++ } ++ ++ if (fwrq->e > 0 || fwrq->m > 14 || fwrq->m < 1 ){ ++ ret = -EOPNOTSUPP; ++ goto out; ++ ++ }else { /* Set the channel */ ++ ++#ifdef ENABLE_DOT11D ++ if (!(GET_DOT11D_INFO(ieee)->channel_map)[fwrq->m]) { ++ ret = -EINVAL; ++ goto out; ++ } ++#endif ++ ieee->current_network.channel = fwrq->m; ++ ieee->set_chan(ieee->dev, ieee->current_network.channel); ++ ++ if(ieee->iw_mode == IW_MODE_ADHOC || ieee->iw_mode == IW_MODE_MASTER) ++ if(ieee->state == IEEE80211_LINKED){ ++ ++ ieee80211_stop_send_beacons(ieee); ++ ieee80211_start_send_beacons(ieee); ++ } ++ } ++ ++ ret = 0; ++out: ++ up(&ieee->wx_sem); ++ return ret; ++} ++ ++ ++int ieee80211_wx_get_freq(struct ieee80211_device *ieee, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ struct iw_freq *fwrq = & wrqu->freq; ++ ++ if (ieee->current_network.channel == 0) ++ return -1; ++ //NM 0.7.0 will not accept channel any more. ++ fwrq->m = ieee80211_wlan_frequencies[ieee->current_network.channel-1] * 100000; ++ fwrq->e = 1; ++// fwrq->m = ieee->current_network.channel; ++// fwrq->e = 0; ++ ++ return 0; ++} ++ ++int ieee80211_wx_get_wap(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ unsigned long flags; ++ wrqu->ap_addr.sa_family = ARPHRD_ETHER; ++ ++ if (ieee->iw_mode == IW_MODE_MONITOR) ++ return -1; ++ ++ /* We want avoid to give to the user inconsistent infos*/ ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ if (ieee->state != IEEE80211_LINKED && ++ ieee->state != IEEE80211_LINKED_SCANNING && ++ ieee->wap_set == 0) ++ ++ memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN); ++ else ++ memcpy(wrqu->ap_addr.sa_data, ++ ieee->current_network.bssid, ETH_ALEN); ++ ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ ++ return 0; ++} ++ ++ ++int ieee80211_wx_set_wap(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *awrq, ++ char *extra) ++{ ++ ++ int ret = 0; ++ u8 zero[] = {0,0,0,0,0,0}; ++ unsigned long flags; ++ ++ short ifup = ieee->proto_started;//dev->flags & IFF_UP; ++ struct sockaddr *temp = (struct sockaddr *)awrq; ++ ++ ieee->sync_scan_hurryup = 1; ++ ++ down(&ieee->wx_sem); ++ /* use ifconfig hw ether */ ++ if (ieee->iw_mode == IW_MODE_MASTER){ ++ ret = -1; ++ goto out; ++ } ++ ++ if (temp->sa_family != ARPHRD_ETHER){ ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ if (ifup) ++ ieee80211_stop_protocol(ieee); ++ ++ /* just to avoid to give inconsistent infos in the ++ * get wx method. not really needed otherwise ++ */ ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ memcpy(ieee->current_network.bssid, temp->sa_data, ETH_ALEN); ++ ieee->wap_set = memcmp(temp->sa_data, zero,ETH_ALEN)!=0; ++ ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ ++ if (ifup) ++ ieee80211_start_protocol(ieee); ++out: ++ up(&ieee->wx_sem); ++ return ret; ++} ++ ++ int ieee80211_wx_get_essid(struct ieee80211_device *ieee, struct iw_request_info *a,union iwreq_data *wrqu,char *b) ++{ ++ int len,ret = 0; ++ unsigned long flags; ++ ++ if (ieee->iw_mode == IW_MODE_MONITOR) ++ return -1; ++ ++ /* We want avoid to give to the user inconsistent infos*/ ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ if (ieee->current_network.ssid[0] == '\0' || ++ ieee->current_network.ssid_len == 0){ ++ ret = -1; ++ goto out; ++ } ++ ++ if (ieee->state != IEEE80211_LINKED && ++ ieee->state != IEEE80211_LINKED_SCANNING && ++ ieee->ssid_set == 0){ ++ ret = -1; ++ goto out; ++ } ++ len = ieee->current_network.ssid_len; ++ wrqu->essid.length = len; ++ strncpy(b,ieee->current_network.ssid,len); ++ wrqu->essid.flags = 1; ++ ++out: ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ ++ return ret; ++ ++} ++ ++int ieee80211_wx_set_rate(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ u32 target_rate = wrqu->bitrate.value; ++ ++ ieee->rate = target_rate/100000; ++ //FIXME: we might want to limit rate also in management protocols. ++ return 0; ++} ++ ++ ++ ++int ieee80211_wx_get_rate(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ u32 tmp_rate; ++#if 0 ++ printk("===>mode:%d, halfNmode:%d\n", ieee->mode, ieee->bHalfWirelessN24GMode); ++ if (ieee->mode & (IEEE_A | IEEE_B | IEEE_G)) ++ tmp_rate = ieee->rate; ++ else if (ieee->mode & IEEE_N_5G) ++ tmp_rate = 580; ++ else if (ieee->mode & IEEE_N_24G) ++ { ++ if (ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) ++ tmp_rate = HTHalfMcsToDataRate(ieee, 15); ++ else ++ tmp_rate = HTMcsToDataRate(ieee, 15); ++ } ++#else ++ tmp_rate = TxCountToDataRate(ieee, ieee->softmac_stats.CurrentShowTxate); ++ ++#endif ++ wrqu->bitrate.value = tmp_rate * 500000; ++ ++ return 0; ++} ++ ++ ++int ieee80211_wx_set_rts(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ if (wrqu->rts.disabled || !wrqu->rts.fixed) ++ ieee->rts = DEFAULT_RTS_THRESHOLD; ++ else ++ { ++ if (wrqu->rts.value < MIN_RTS_THRESHOLD || ++ wrqu->rts.value > MAX_RTS_THRESHOLD) ++ return -EINVAL; ++ ieee->rts = wrqu->rts.value; ++ } ++ return 0; ++} ++ ++int ieee80211_wx_get_rts(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ wrqu->rts.value = ieee->rts; ++ wrqu->rts.fixed = 0; /* no auto select */ ++ wrqu->rts.disabled = (wrqu->rts.value == DEFAULT_RTS_THRESHOLD); ++ return 0; ++} ++int ieee80211_wx_set_mode(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ ++ ieee->sync_scan_hurryup = 1; ++ ++ down(&ieee->wx_sem); ++ ++ if (wrqu->mode == ieee->iw_mode) ++ goto out; ++ ++ if (wrqu->mode == IW_MODE_MONITOR){ ++ ++ ieee->dev->type = ARPHRD_IEEE80211; ++ }else{ ++ ieee->dev->type = ARPHRD_ETHER; ++ } ++ ++ if (!ieee->proto_started){ ++ ieee->iw_mode = wrqu->mode; ++ }else{ ++ ieee80211_stop_protocol(ieee); ++ ieee->iw_mode = wrqu->mode; ++ ieee80211_start_protocol(ieee); ++ } ++ ++out: ++ up(&ieee->wx_sem); ++ return 0; ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++void ieee80211_wx_sync_scan_wq(struct work_struct *work) ++{ ++ struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, wx_sync_scan_wq); ++#else ++void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee) ++{ ++#endif ++ short chan; ++ HT_EXTCHNL_OFFSET chan_offset=0; ++ HT_CHANNEL_WIDTH bandwidth=0; ++ int b40M = 0; ++ static int count = 0; ++ chan = ieee->current_network.channel; ++ netif_carrier_off(ieee->dev); ++ ++ if (ieee->data_hard_stop) ++ ieee->data_hard_stop(ieee->dev); ++ ++ ieee80211_stop_send_beacons(ieee); ++ ++ ieee->state = IEEE80211_LINKED_SCANNING; ++ ieee->link_change(ieee->dev); ++ ieee->InitialGainHandler(ieee->dev,IG_Backup); ++ if (ieee->pHTInfo->bCurrentHTSupport && ieee->pHTInfo->bEnableHT && ieee->pHTInfo->bCurBW40MHz) { ++ b40M = 1; ++ chan_offset = ieee->pHTInfo->CurSTAExtChnlOffset; ++ bandwidth = (HT_CHANNEL_WIDTH)ieee->pHTInfo->bCurBW40MHz; ++ printk("Scan in 40M, force to 20M first:%d, %d\n", chan_offset, bandwidth); ++ ieee->SetBWModeHandler(ieee->dev, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); ++ } ++ ieee80211_start_scan_syncro(ieee); ++ if (b40M) { ++ printk("Scan in 20M, back to 40M\n"); ++ if (chan_offset == HT_EXTCHNL_OFFSET_UPPER) ++ ieee->set_chan(ieee->dev, chan + 2); ++ else if (chan_offset == HT_EXTCHNL_OFFSET_LOWER) ++ ieee->set_chan(ieee->dev, chan - 2); ++ else ++ ieee->set_chan(ieee->dev, chan); ++ ieee->SetBWModeHandler(ieee->dev, bandwidth, chan_offset); ++ } else { ++ ieee->set_chan(ieee->dev, chan); ++ } ++ ++ ieee->InitialGainHandler(ieee->dev,IG_Restore); ++ ieee->state = IEEE80211_LINKED; ++ ieee->link_change(ieee->dev); ++ // To prevent the immediately calling watch_dog after scan. ++ if(ieee->LinkDetectInfo.NumRecvBcnInPeriod==0||ieee->LinkDetectInfo.NumRecvDataInPeriod==0 ) ++ { ++ ieee->LinkDetectInfo.NumRecvBcnInPeriod = 1; ++ ieee->LinkDetectInfo.NumRecvDataInPeriod= 1; ++ } ++ if (ieee->data_hard_resume) ++ ieee->data_hard_resume(ieee->dev); ++ ++ if(ieee->iw_mode == IW_MODE_ADHOC || ieee->iw_mode == IW_MODE_MASTER) ++ ieee80211_start_send_beacons(ieee); ++ ++ netif_carrier_on(ieee->dev); ++ count = 0; ++ up(&ieee->wx_sem); ++ ++} ++ ++int ieee80211_wx_set_scan(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ int ret = 0; ++ ++ down(&ieee->wx_sem); ++ ++ if (ieee->iw_mode == IW_MODE_MONITOR || !(ieee->proto_started)){ ++ ret = -1; ++ goto out; ++ } ++ ++ if ( ieee->state == IEEE80211_LINKED){ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ queue_work(ieee->wq, &ieee->wx_sync_scan_wq); ++#else ++ schedule_task(&ieee->wx_sync_scan_wq); ++#endif ++ /* intentionally forget to up sem */ ++ return 0; ++ } ++ ++out: ++ up(&ieee->wx_sem); ++ return ret; ++} ++ ++int ieee80211_wx_set_essid(struct ieee80211_device *ieee, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret=0,len; ++ short proto_started; ++ unsigned long flags; ++ ++ ieee->sync_scan_hurryup = 1; ++ down(&ieee->wx_sem); ++ ++ proto_started = ieee->proto_started; ++ ++ if (wrqu->essid.length > IW_ESSID_MAX_SIZE){ ++ ret= -E2BIG; ++ goto out; ++ } ++ ++ if (ieee->iw_mode == IW_MODE_MONITOR){ ++ ret= -1; ++ goto out; ++ } ++ ++ if(proto_started) ++ ieee80211_stop_protocol(ieee); ++ ++ ++ /* this is just to be sure that the GET wx callback ++ * has consisten infos. not needed otherwise ++ */ ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ if (wrqu->essid.flags && wrqu->essid.length) { ++ //first flush current network.ssid ++ len = ((wrqu->essid.length-1) < IW_ESSID_MAX_SIZE) ? (wrqu->essid.length-1) : IW_ESSID_MAX_SIZE; ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++ strncpy(ieee->current_network.ssid, extra, len); ++ ieee->current_network.ssid_len = len; ++#if 0 ++ { ++ int i; ++ for (i=0; icurrent_network.ssid, extra, len+1); ++ ieee->current_network.ssid_len = len+1; ++#if 0 ++ { ++ int i; ++ for (i=0; issid_set = 1; ++ } ++ else{ ++ ieee->ssid_set = 0; ++ ieee->current_network.ssid[0] = '\0'; ++ ieee->current_network.ssid_len = 0; ++ } ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ ++ if (proto_started) ++ ieee80211_start_protocol(ieee); ++out: ++ up(&ieee->wx_sem); ++ return ret; ++} ++ ++ int ieee80211_wx_get_mode(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ ++ wrqu->mode = ieee->iw_mode; ++ return 0; ++} ++ ++ int ieee80211_wx_set_rawtx(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int *parms = (int *)extra; ++ int enable = (parms[0] > 0); ++ short prev = ieee->raw_tx; ++ ++ down(&ieee->wx_sem); ++ ++ if(enable) ++ ieee->raw_tx = 1; ++ else ++ ieee->raw_tx = 0; ++ ++ printk(KERN_INFO"raw TX is %s\n", ++ ieee->raw_tx ? "enabled" : "disabled"); ++ ++ if(ieee->iw_mode == IW_MODE_MONITOR) ++ { ++ if(prev == 0 && ieee->raw_tx){ ++ if (ieee->data_hard_resume) ++ ieee->data_hard_resume(ieee->dev); ++ ++ netif_carrier_on(ieee->dev); ++ } ++ ++ if(prev && ieee->raw_tx == 1) ++ netif_carrier_off(ieee->dev); ++ } ++ ++ up(&ieee->wx_sem); ++ ++ return 0; ++} ++ ++int ieee80211_wx_get_name(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ strcpy(wrqu->name, "802.11"); ++ if(ieee->modulation & IEEE80211_CCK_MODULATION){ ++ strcat(wrqu->name, "b"); ++ if(ieee->modulation & IEEE80211_OFDM_MODULATION) ++ strcat(wrqu->name, "/g"); ++ }else if(ieee->modulation & IEEE80211_OFDM_MODULATION) ++ strcat(wrqu->name, "g"); ++ if (ieee->mode & (IEEE_N_24G | IEEE_N_5G)) ++ strcat(wrqu->name, "/n"); ++ ++ if((ieee->state == IEEE80211_LINKED) || ++ (ieee->state == IEEE80211_LINKED_SCANNING)) ++ strcat(wrqu->name," linked"); ++ else if(ieee->state != IEEE80211_NOLINK) ++ strcat(wrqu->name," link.."); ++ ++ ++ return 0; ++} ++ ++ ++/* this is mostly stolen from hostap */ ++int ieee80211_wx_set_power(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++#if 1 ++ if( ++ (!ieee->sta_wake_up) || ++ // (!ieee->ps_request_tx_ack) || ++ (!ieee->enter_sleep_state) || ++ (!ieee->ps_is_queue_empty)){ ++ ++ // printk("ERROR. PS mode is tryied to be use but driver missed a callback\n\n"); ++ ++ return -1; ++ } ++#endif ++ down(&ieee->wx_sem); ++ ++ if (wrqu->power.disabled){ ++ ieee->ps = IEEE80211_PS_DISABLED; ++ goto exit; ++ } ++ if (wrqu->power.flags & IW_POWER_TIMEOUT) { ++ //ieee->ps_period = wrqu->power.value / 1000; ++ ieee->ps_timeout = wrqu->power.value / 1000; ++ } ++ ++ if (wrqu->power.flags & IW_POWER_PERIOD) { ++ ++ //ieee->ps_timeout = wrqu->power.value / 1000; ++ ieee->ps_period = wrqu->power.value / 1000; ++ //wrq->value / 1024; ++ ++ } ++ switch (wrqu->power.flags & IW_POWER_MODE) { ++ case IW_POWER_UNICAST_R: ++ ieee->ps = IEEE80211_PS_UNICAST; ++ break; ++ case IW_POWER_MULTICAST_R: ++ ieee->ps = IEEE80211_PS_MBCAST; ++ break; ++ case IW_POWER_ALL_R: ++ ieee->ps = IEEE80211_PS_UNICAST | IEEE80211_PS_MBCAST; ++ break; ++ ++ case IW_POWER_ON: ++ // ieee->ps = IEEE80211_PS_DISABLED; ++ break; ++ ++ default: ++ ret = -EINVAL; ++ goto exit; ++ ++ } ++exit: ++ up(&ieee->wx_sem); ++ return ret; ++ ++} ++ ++/* this is stolen from hostap */ ++int ieee80211_wx_get_power(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret =0; ++ ++ down(&ieee->wx_sem); ++ ++ if(ieee->ps == IEEE80211_PS_DISABLED){ ++ wrqu->power.disabled = 1; ++ goto exit; ++ } ++ ++ wrqu->power.disabled = 0; ++ ++ if ((wrqu->power.flags & IW_POWER_TYPE) == IW_POWER_TIMEOUT) { ++ wrqu->power.flags = IW_POWER_TIMEOUT; ++ wrqu->power.value = ieee->ps_timeout * 1000; ++ } else { ++// ret = -EOPNOTSUPP; ++// goto exit; ++ wrqu->power.flags = IW_POWER_PERIOD; ++ wrqu->power.value = ieee->ps_period * 1000; ++//ieee->current_network.dtim_period * ieee->current_network.beacon_interval * 1024; ++ } ++ ++ if ((ieee->ps & (IEEE80211_PS_MBCAST | IEEE80211_PS_UNICAST)) == (IEEE80211_PS_MBCAST | IEEE80211_PS_UNICAST)) ++ wrqu->power.flags |= IW_POWER_ALL_R; ++ else if (ieee->ps & IEEE80211_PS_MBCAST) ++ wrqu->power.flags |= IW_POWER_MULTICAST_R; ++ else ++ wrqu->power.flags |= IW_POWER_UNICAST_R; ++ ++exit: ++ up(&ieee->wx_sem); ++ return ret; ++ ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++//EXPORT_SYMBOL(ieee80211_wx_get_essid); ++//EXPORT_SYMBOL(ieee80211_wx_set_essid); ++//EXPORT_SYMBOL(ieee80211_wx_set_rate); ++//EXPORT_SYMBOL(ieee80211_wx_get_rate); ++//EXPORT_SYMBOL(ieee80211_wx_set_wap); ++//EXPORT_SYMBOL(ieee80211_wx_get_wap); ++//EXPORT_SYMBOL(ieee80211_wx_set_mode); ++//EXPORT_SYMBOL(ieee80211_wx_get_mode); ++//EXPORT_SYMBOL(ieee80211_wx_set_scan); ++//EXPORT_SYMBOL(ieee80211_wx_get_freq); ++//EXPORT_SYMBOL(ieee80211_wx_set_freq); ++//EXPORT_SYMBOL(ieee80211_wx_set_rawtx); ++//EXPORT_SYMBOL(ieee80211_wx_get_name); ++//EXPORT_SYMBOL(ieee80211_wx_set_power); ++//EXPORT_SYMBOL(ieee80211_wx_get_power); ++//EXPORT_SYMBOL(ieee80211_wlan_frequencies); ++//EXPORT_SYMBOL(ieee80211_wx_set_rts); ++//EXPORT_SYMBOL(ieee80211_wx_get_rts); ++#else ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_essid); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_essid); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_rate); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_rate); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_wap); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_wap); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_mode); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_mode); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_scan); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_freq); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_freq); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_rawtx); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_name); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_power); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_power); ++EXPORT_SYMBOL_NOVERS(ieee80211_wlan_frequencies); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_rts); ++EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_rts); ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_tx.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_tx.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_tx.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,933 @@ ++/****************************************************************************** ++ ++ Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms of version 2 of the GNU General Public License as ++ published by the Free Software Foundation. ++ ++ This program is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., 59 ++ Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ ++ The full GNU General Public License is included in this distribution in the ++ file called LICENSE. ++ ++ Contact Information: ++ James P. Ketrenos ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++****************************************************************************** ++ ++ Few modifications for Realtek's Wi-Fi drivers by ++ Andrea Merello ++ ++ A special thanks goes to Realtek for their support ! ++ ++******************************************************************************/ ++ ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ieee80211.h" ++ ++ ++/* ++ ++ ++802.11 Data Frame ++ ++ ++802.11 frame_contorl for data frames - 2 bytes ++ ,-----------------------------------------------------------------------------------------. ++bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | a | b | c | d | e | ++ |----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------| ++val | 0 | 0 | 0 | 1 | x | 0 | 0 | 0 | 1 | 0 | x | x | x | x | x | ++ |----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------| ++desc | ^-ver-^ | ^type-^ | ^-----subtype-----^ | to |from |more |retry| pwr |more |wep | ++ | | | x=0 data,x=1 data+ack | DS | DS |frag | | mgm |data | | ++ '-----------------------------------------------------------------------------------------' ++ /\ ++ | ++802.11 Data Frame | ++ ,--------- 'ctrl' expands to >-----------' ++ | ++ ,--'---,-------------------------------------------------------------. ++Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 | ++ |------|------|---------|---------|---------|------|---------|------| ++Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | Frame | fcs | ++ | | tion | (BSSID) | | | ence | data | | ++ `--------------------------------------------------| |------' ++Total: 28 non-data bytes `----.----' ++ | ++ .- 'Frame data' expands to <---------------------------' ++ | ++ V ++ ,---------------------------------------------------. ++Bytes | 1 | 1 | 1 | 3 | 2 | 0-2304 | ++ |------|------|---------|----------|------|---------| ++Desc. | SNAP | SNAP | Control |Eth Tunnel| Type | IP | ++ | DSAP | SSAP | | | | Packet | ++ | 0xAA | 0xAA |0x03 (UI)|0x00-00-F8| | | ++ `-----------------------------------------| | ++Total: 8 non-data bytes `----.----' ++ | ++ .- 'IP Packet' expands, if WEP enabled, to <--' ++ | ++ V ++ ,-----------------------. ++Bytes | 4 | 0-2296 | 4 | ++ |-----|-----------|-----| ++Desc. | IV | Encrypted | ICV | ++ | | IP Packet | | ++ `-----------------------' ++Total: 8 non-data bytes ++ ++ ++802.3 Ethernet Data Frame ++ ++ ,-----------------------------------------. ++Bytes | 6 | 6 | 2 | Variable | 4 | ++ |-------|-------|------|-----------|------| ++Desc. | Dest. | Source| Type | IP Packet | fcs | ++ | MAC | MAC | | | | ++ `-----------------------------------------' ++Total: 18 non-data bytes ++ ++In the event that fragmentation is required, the incoming payload is split into ++N parts of size ieee->fts. The first fragment contains the SNAP header and the ++remaining packets are just data. ++ ++If encryption is enabled, each fragment payload size is reduced by enough space ++to add the prefix and postfix (IV and ICV totalling 8 bytes in the case of WEP) ++So if you have 1500 bytes of payload with ieee->fts set to 500 without ++encryption it will take 3 frames. With WEP it will take 4 frames as the ++payload of each frame is reduced to 492 bytes. ++ ++* SKB visualization ++* ++* ,- skb->data ++* | ++* | ETHERNET HEADER ,-<-- PAYLOAD ++* | | 14 bytes from skb->data ++* | 2 bytes for Type --> ,T. | (sizeof ethhdr) ++* | | | | ++* |,-Dest.--. ,--Src.---. | | | ++* | 6 bytes| | 6 bytes | | | | ++* v | | | | | | ++* 0 | v 1 | v | v 2 ++* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 ++* ^ | ^ | ^ | ++* | | | | | | ++* | | | | `T' <---- 2 bytes for Type ++* | | | | ++* | | '---SNAP--' <-------- 6 bytes for SNAP ++* | | ++* `-IV--' <-------------------- 4 bytes for IV (WEP) ++* ++* SNAP HEADER ++* ++*/ ++ ++static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 }; ++static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 }; ++ ++static inline int ieee80211_put_snap(u8 *data, u16 h_proto) ++{ ++ struct ieee80211_snap_hdr *snap; ++ u8 *oui; ++ ++ snap = (struct ieee80211_snap_hdr *)data; ++ snap->dsap = 0xaa; ++ snap->ssap = 0xaa; ++ snap->ctrl = 0x03; ++ ++ if (h_proto == 0x8137 || h_proto == 0x80f3) ++ oui = P802_1H_OUI; ++ else ++ oui = RFC1042_OUI; ++ snap->oui[0] = oui[0]; ++ snap->oui[1] = oui[1]; ++ snap->oui[2] = oui[2]; ++ ++ *(u16 *)(data + SNAP_SIZE) = htons(h_proto); ++ ++ return SNAP_SIZE + sizeof(u16); ++} ++ ++int ieee80211_encrypt_fragment( ++ struct ieee80211_device *ieee, ++ struct sk_buff *frag, ++ int hdr_len) ++{ ++ struct ieee80211_crypt_data* crypt = ieee->crypt[ieee->tx_keyidx]; ++ int res; ++ ++ if (!(crypt && crypt->ops)) ++ { ++ printk("=========>%s(), crypt is null\n", __FUNCTION__); ++ return -1; ++ } ++#ifdef CONFIG_IEEE80211_CRYPT_TKIP ++ struct ieee80211_hdr *header; ++ ++ if (ieee->tkip_countermeasures && ++ crypt && crypt->ops && strcmp(crypt->ops->name, "TKIP") == 0) { ++ header = (struct ieee80211_hdr *) frag->data; ++ if (net_ratelimit()) { ++ printk(KERN_DEBUG "%s: TKIP countermeasures: dropped " ++ "TX packet to " MAC_FMT "\n", ++ ieee->dev->name, MAC_ARG(header->addr1)); ++ } ++ return -1; ++ } ++#endif ++ /* To encrypt, frame format is: ++ * IV (4 bytes), clear payload (including SNAP), ICV (4 bytes) */ ++ ++ // PR: FIXME: Copied from hostap. Check fragmentation/MSDU/MPDU encryption. ++ /* Host-based IEEE 802.11 fragmentation for TX is not yet supported, so ++ * call both MSDU and MPDU encryption functions from here. */ ++ atomic_inc(&crypt->refcnt); ++ res = 0; ++ if (crypt->ops->encrypt_msdu) ++ res = crypt->ops->encrypt_msdu(frag, hdr_len, crypt->priv); ++ if (res == 0 && crypt->ops->encrypt_mpdu) ++ res = crypt->ops->encrypt_mpdu(frag, hdr_len, crypt->priv); ++ ++ atomic_dec(&crypt->refcnt); ++ if (res < 0) { ++ printk(KERN_INFO "%s: Encryption failed: len=%d.\n", ++ ieee->dev->name, frag->len); ++ ieee->ieee_stats.tx_discards++; ++ return -1; ++ } ++ ++ return 0; ++} ++ ++ ++void ieee80211_txb_free(struct ieee80211_txb *txb) { ++ //int i; ++ if (unlikely(!txb)) ++ return; ++#if 0 ++ for (i = 0; i < txb->nr_frags; i++) ++ if (txb->fragments[i]) ++ dev_kfree_skb_any(txb->fragments[i]); ++#endif ++ kfree(txb); ++} ++ ++struct ieee80211_txb *ieee80211_alloc_txb(int nr_frags, int txb_size, ++ int gfp_mask) ++{ ++ struct ieee80211_txb *txb; ++ int i; ++ txb = kmalloc( ++ sizeof(struct ieee80211_txb) + (sizeof(u8*) * nr_frags), ++ gfp_mask); ++ if (!txb) ++ return NULL; ++ ++ memset(txb, 0, sizeof(struct ieee80211_txb)); ++ txb->nr_frags = nr_frags; ++ txb->frag_size = txb_size; ++ ++ for (i = 0; i < nr_frags; i++) { ++ txb->fragments[i] = dev_alloc_skb(txb_size); ++ if (unlikely(!txb->fragments[i])) { ++ i--; ++ break; ++ } ++ memset(txb->fragments[i]->cb, 0, sizeof(txb->fragments[i]->cb)); ++ } ++ if (unlikely(i != nr_frags)) { ++ while (i >= 0) ++ dev_kfree_skb_any(txb->fragments[i--]); ++ kfree(txb); ++ return NULL; ++ } ++ return txb; ++} ++ ++// Classify the to-be send data packet ++// Need to acquire the sent queue index. ++static int ++ieee80211_classify(struct sk_buff *skb, struct ieee80211_network *network) ++{ ++ struct ethhdr *eth; ++ struct iphdr *ip; ++ eth = (struct ethhdr *)skb->data; ++ if (eth->h_proto != htons(ETH_P_IP)) ++ return 0; ++ ++// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)) ++ ip = ip_hdr(skb); ++#else ++ ip = (struct iphdr*)(skb->data + sizeof(struct ether_header)); ++#endif ++ switch (ip->tos & 0xfc) { ++ case 0x20: ++ return 2; ++ case 0x40: ++ return 1; ++ case 0x60: ++ return 3; ++ case 0x80: ++ return 4; ++ case 0xa0: ++ return 5; ++ case 0xc0: ++ return 6; ++ case 0xe0: ++ return 7; ++ default: ++ return 0; ++ } ++} ++ ++#define SN_LESS(a, b) (((a-b)&0x800)!=0) ++void ieee80211_tx_query_agg_cap(struct ieee80211_device* ieee, struct sk_buff* skb, cb_desc* tcb_desc) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ PTX_TS_RECORD pTxTs = NULL; ++ struct ieee80211_hdr_1addr* hdr = (struct ieee80211_hdr_1addr*)skb->data; ++ ++ if (!pHTInfo->bCurrentHTSupport||!pHTInfo->bEnableHT) ++ return; ++ if (!IsQoSDataFrame(skb->data)) ++ return; ++ ++ if (is_multicast_ether_addr(hdr->addr1) || is_broadcast_ether_addr(hdr->addr1)) ++ return; ++ //check packet and mode later ++#ifdef TO_DO_LIST ++ if(pTcb->PacketLength >= 4096) ++ return; ++ // For RTL819X, if pairwisekey = wep/tkip, we don't aggrregation. ++ if(!Adapter->HalFunc.GetNmodeSupportBySecCfgHandler(Adapter)) ++ return; ++#endif ++#if 1 ++ if(!ieee->GetNmodeSupportBySecCfg(ieee->dev)) ++ { ++ return; ++ } ++#endif ++ if(pHTInfo->bCurrentAMPDUEnable) ++ { ++ if (!GetTs(ieee, (PTS_COMMON_INFO*)(&pTxTs), hdr->addr1, skb->priority, TX_DIR, true)) ++ { ++ printk("===>can't get TS\n"); ++ return; ++ } ++ if (pTxTs->TxAdmittedBARecord.bValid == false) ++ { ++ //as some AP will refuse our action frame until key handshake has been finished. WB ++ if (ieee->wpa_ie_len && (ieee->pairwise_key_type == KEY_TYPE_NA)) ++ ; ++ else ++ TsStartAddBaProcess(ieee, pTxTs); ++ goto FORCED_AGG_SETTING; ++ } ++ else if (pTxTs->bUsingBa == false) ++ { ++ if (SN_LESS(pTxTs->TxAdmittedBARecord.BaStartSeqCtrl.field.SeqNum, (pTxTs->TxCurSeq+1)%4096)) ++ pTxTs->bUsingBa = true; ++ else ++ goto FORCED_AGG_SETTING; ++ } ++ ++ if (ieee->iw_mode == IW_MODE_INFRA) ++ { ++ tcb_desc->bAMPDUEnable = true; ++ tcb_desc->ampdu_factor = pHTInfo->CurrentAMPDUFactor; ++ tcb_desc->ampdu_density = pHTInfo->CurrentMPDUDensity; ++ } ++ } ++FORCED_AGG_SETTING: ++ switch(pHTInfo->ForcedAMPDUMode ) ++ { ++ case HT_AGG_AUTO: ++ break; ++ ++ case HT_AGG_FORCE_ENABLE: ++ tcb_desc->bAMPDUEnable = true; ++ tcb_desc->ampdu_density = pHTInfo->ForcedMPDUDensity; ++ tcb_desc->ampdu_factor = pHTInfo->ForcedAMPDUFactor; ++ break; ++ ++ case HT_AGG_FORCE_DISABLE: ++ tcb_desc->bAMPDUEnable = false; ++ tcb_desc->ampdu_density = 0; ++ tcb_desc->ampdu_factor = 0; ++ break; ++ ++ } ++ return; ++} ++ ++extern void ieee80211_qurey_ShortPreambleMode(struct ieee80211_device* ieee, cb_desc* tcb_desc) ++{ ++ tcb_desc->bUseShortPreamble = false; ++ if (tcb_desc->data_rate == 2) ++ {//// 1M can only use Long Preamble. 11B spec ++ return; ++ } ++ else if (ieee->current_network.capability & WLAN_CAPABILITY_SHORT_PREAMBLE) ++ { ++ tcb_desc->bUseShortPreamble = true; ++ } ++ return; ++} ++extern void ++ieee80211_query_HTCapShortGI(struct ieee80211_device *ieee, cb_desc *tcb_desc) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ ++ tcb_desc->bUseShortGI = false; ++ ++ if(!pHTInfo->bCurrentHTSupport||!pHTInfo->bEnableHT) ++ return; ++ ++ if(pHTInfo->bForcedShortGI) ++ { ++ tcb_desc->bUseShortGI = true; ++ return; ++ } ++ ++ if((pHTInfo->bCurBW40MHz==true) && pHTInfo->bCurShortGI40MHz) ++ tcb_desc->bUseShortGI = true; ++ else if((pHTInfo->bCurBW40MHz==false) && pHTInfo->bCurShortGI20MHz) ++ tcb_desc->bUseShortGI = true; ++} ++ ++void ieee80211_query_BandwidthMode(struct ieee80211_device* ieee, cb_desc *tcb_desc) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ ++ tcb_desc->bPacketBW = false; ++ ++ if(!pHTInfo->bCurrentHTSupport||!pHTInfo->bEnableHT) ++ return; ++ ++ if(tcb_desc->bMulticast || tcb_desc->bBroadcast) ++ return; ++ ++ if((tcb_desc->data_rate & 0x80)==0) // If using legacy rate, it shall use 20MHz channel. ++ return; ++ //BandWidthAutoSwitch is for auto switch to 20 or 40 in long distance ++ if(pHTInfo->bCurBW40MHz && pHTInfo->bCurTxBW40MHz && !ieee->bandwidth_auto_switch.bforced_tx20Mhz) ++ tcb_desc->bPacketBW = true; ++ return; ++} ++ ++void ieee80211_query_protectionmode(struct ieee80211_device* ieee, cb_desc* tcb_desc, struct sk_buff* skb) ++{ ++ // Common Settings ++ tcb_desc->bRTSSTBC = false; ++ tcb_desc->bRTSUseShortGI = false; // Since protection frames are always sent by legacy rate, ShortGI will never be used. ++ tcb_desc->bCTSEnable = false; // Most of protection using RTS/CTS ++ tcb_desc->RTSSC = 0; // 20MHz: Don't care; 40MHz: Duplicate. ++ tcb_desc->bRTSBW = false; // RTS frame bandwidth is always 20MHz ++ ++ if(tcb_desc->bBroadcast || tcb_desc->bMulticast)//only unicast frame will use rts/cts ++ return; ++ ++ if (is_broadcast_ether_addr(skb->data+16)) //check addr3 as infrastructure add3 is DA. ++ return; ++ ++ if (ieee->mode < IEEE_N_24G) //b, g mode ++ { ++ // (1) RTS_Threshold is compared to the MPDU, not MSDU. ++ // (2) If there are more than one frag in this MSDU, only the first frag uses protection frame. ++ // Other fragments are protected by previous fragment. ++ // So we only need to check the length of first fragment. ++ if (skb->len > ieee->rts) ++ { ++ tcb_desc->bRTSEnable = true; ++ tcb_desc->rts_rate = MGN_24M; ++ } ++ else if (ieee->current_network.buseprotection) ++ { ++ // Use CTS-to-SELF in protection mode. ++ tcb_desc->bRTSEnable = true; ++ tcb_desc->bCTSEnable = true; ++ tcb_desc->rts_rate = MGN_24M; ++ } ++ //otherwise return; ++ return; ++ } ++ else ++ {// 11n High throughput case. ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ while (true) ++ { ++ //check ERP protection ++ if (ieee->current_network.buseprotection) ++ {// CTS-to-SELF ++ tcb_desc->bRTSEnable = true; ++ tcb_desc->bCTSEnable = true; ++ tcb_desc->rts_rate = MGN_24M; ++ break; ++ } ++ //check HT op mode ++ if(pHTInfo->bCurrentHTSupport && pHTInfo->bEnableHT) ++ { ++ u8 HTOpMode = pHTInfo->CurrentOpMode; ++ if((pHTInfo->bCurBW40MHz && (HTOpMode == 2 || HTOpMode == 3)) || ++ (!pHTInfo->bCurBW40MHz && HTOpMode == 3) ) ++ { ++ tcb_desc->rts_rate = MGN_24M; // Rate is 24Mbps. ++ tcb_desc->bRTSEnable = true; ++ break; ++ } ++ } ++ //check rts ++ if (skb->len > ieee->rts) ++ { ++ tcb_desc->rts_rate = MGN_24M; // Rate is 24Mbps. ++ tcb_desc->bRTSEnable = true; ++ break; ++ } ++ //to do list: check MIMO power save condition. ++ //check AMPDU aggregation for TXOP ++ if(tcb_desc->bAMPDUEnable) ++ { ++ tcb_desc->rts_rate = MGN_24M; // Rate is 24Mbps. ++ // According to 8190 design, firmware sends CF-End only if RTS/CTS is enabled. However, it degrads ++ // throughput around 10M, so we disable of this mechanism. 2007.08.03 by Emily ++ tcb_desc->bRTSEnable = false; ++ break; ++ } ++ //check IOT action ++ if(pHTInfo->IOTAction & HT_IOT_ACT_FORCED_CTS2SELF) ++ { ++ tcb_desc->bCTSEnable = true; ++ tcb_desc->rts_rate = MGN_24M; ++ tcb_desc->bRTSEnable = true; ++ break; ++ } ++ // Totally no protection case!! ++ goto NO_PROTECTION; ++ } ++ } ++ // For test , CTS replace with RTS ++ if( 0 ) ++ { ++ tcb_desc->bCTSEnable = true; ++ tcb_desc->rts_rate = MGN_24M; ++ tcb_desc->bRTSEnable = true; ++ } ++ if (ieee->current_network.capability & WLAN_CAPABILITY_SHORT_PREAMBLE) ++ tcb_desc->bUseShortPreamble = true; ++ if (ieee->mode == IW_MODE_MASTER) ++ goto NO_PROTECTION; ++ return; ++NO_PROTECTION: ++ tcb_desc->bRTSEnable = false; ++ tcb_desc->bCTSEnable = false; ++ tcb_desc->rts_rate = 0; ++ tcb_desc->RTSSC = 0; ++ tcb_desc->bRTSBW = false; ++} ++ ++ ++void ieee80211_txrate_selectmode(struct ieee80211_device* ieee, cb_desc* tcb_desc) ++{ ++#ifdef TO_DO_LIST ++ if(!IsDataFrame(pFrame)) ++ { ++ pTcb->bTxDisableRateFallBack = TRUE; ++ pTcb->bTxUseDriverAssingedRate = TRUE; ++ pTcb->RATRIndex = 7; ++ return; ++ } ++ ++ if(pMgntInfo->ForcedDataRate!= 0) ++ { ++ pTcb->bTxDisableRateFallBack = TRUE; ++ pTcb->bTxUseDriverAssingedRate = TRUE; ++ return; ++ } ++#endif ++ if(ieee->bTxDisableRateFallBack) ++ tcb_desc->bTxDisableRateFallBack = true; ++ ++ if(ieee->bTxUseDriverAssingedRate) ++ tcb_desc->bTxUseDriverAssingedRate = true; ++ if(!tcb_desc->bTxDisableRateFallBack || !tcb_desc->bTxUseDriverAssingedRate) ++ { ++ if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) ++ tcb_desc->RATRIndex = 0; ++ } ++} ++ ++void ieee80211_query_seqnum(struct ieee80211_device*ieee, struct sk_buff* skb, u8* dst) ++{ ++ if (is_multicast_ether_addr(dst) || is_broadcast_ether_addr(dst)) ++ return; ++ if (IsQoSDataFrame(skb->data)) //we deal qos data only ++ { ++ PTX_TS_RECORD pTS = NULL; ++ if (!GetTs(ieee, (PTS_COMMON_INFO*)(&pTS), dst, skb->priority, TX_DIR, true)) ++ { ++ return; ++ } ++ pTS->TxCurSeq = (pTS->TxCurSeq+1)%4096; ++ } ++} ++ ++int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)) ++ struct ieee80211_device *ieee = netdev_priv(dev); ++#else ++ struct ieee80211_device *ieee = (struct ieee80211_device *)dev->priv; ++#endif ++ struct ieee80211_txb *txb = NULL; ++ struct ieee80211_hdr_3addrqos *frag_hdr; ++ int i, bytes_per_frag, nr_frags, bytes_last_frag, frag_size; ++ unsigned long flags; ++ struct net_device_stats *stats = &ieee->stats; ++ int ether_type = 0, encrypt; ++ int bytes, fc, qos_ctl = 0, hdr_len; ++ struct sk_buff *skb_frag; ++ struct ieee80211_hdr_3addrqos header = { /* Ensure zero initialized */ ++ .duration_id = 0, ++ .seq_ctl = 0, ++ .qos_ctl = 0 ++ }; ++ u8 dest[ETH_ALEN], src[ETH_ALEN]; ++ int qos_actived = ieee->current_network.qos_data.active; ++ ++ struct ieee80211_crypt_data* crypt; ++ ++ cb_desc *tcb_desc; ++ ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ /* If there is no driver handler to take the TXB, dont' bother ++ * creating it... */ ++ if ((!ieee->hard_start_xmit && !(ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE))|| ++ ((!ieee->softmac_data_hard_start_xmit && (ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE)))) { ++ printk(KERN_WARNING "%s: No xmit handler.\n", ++ ieee->dev->name); ++ goto success; ++ } ++ ++ ++ if(likely(ieee->raw_tx == 0)){ ++ if (unlikely(skb->len < SNAP_SIZE + sizeof(u16))) { ++ printk(KERN_WARNING "%s: skb too small (%d).\n", ++ ieee->dev->name, skb->len); ++ goto success; ++ } ++ ++ memset(skb->cb, 0, sizeof(skb->cb)); ++ ether_type = ntohs(((struct ethhdr *)skb->data)->h_proto); ++ ++ crypt = ieee->crypt[ieee->tx_keyidx]; ++ ++ encrypt = !(ether_type == ETH_P_PAE && ieee->ieee802_1x) && ++ ieee->host_encrypt && crypt && crypt->ops; ++ ++ if (!encrypt && ieee->ieee802_1x && ++ ieee->drop_unencrypted && ether_type != ETH_P_PAE) { ++ stats->tx_dropped++; ++ goto success; ++ } ++ #ifdef CONFIG_IEEE80211_DEBUG ++ if (crypt && !encrypt && ether_type == ETH_P_PAE) { ++ struct eapol *eap = (struct eapol *)(skb->data + ++ sizeof(struct ethhdr) - SNAP_SIZE - sizeof(u16)); ++ IEEE80211_DEBUG_EAP("TX: IEEE 802.11 EAPOL frame: %s\n", ++ eap_get_type(eap->type)); ++ } ++ #endif ++ ++ /* Save source and destination addresses */ ++ memcpy(&dest, skb->data, ETH_ALEN); ++ memcpy(&src, skb->data+ETH_ALEN, ETH_ALEN); ++ ++ /* Advance the SKB to the start of the payload */ ++ skb_pull(skb, sizeof(struct ethhdr)); ++ ++ /* Determine total amount of storage required for TXB packets */ ++ bytes = skb->len + SNAP_SIZE + sizeof(u16); ++ ++ if (encrypt) ++ fc = IEEE80211_FTYPE_DATA | IEEE80211_FCTL_WEP; ++ else ++ ++ fc = IEEE80211_FTYPE_DATA; ++ ++ //if(ieee->current_network.QoS_Enable) ++ if(qos_actived) ++ fc |= IEEE80211_STYPE_QOS_DATA; ++ else ++ fc |= IEEE80211_STYPE_DATA; ++ ++ if (ieee->iw_mode == IW_MODE_INFRA) { ++ fc |= IEEE80211_FCTL_TODS; ++ /* To DS: Addr1 = BSSID, Addr2 = SA, ++ Addr3 = DA */ ++ memcpy(&header.addr1, ieee->current_network.bssid, ETH_ALEN); ++ memcpy(&header.addr2, &src, ETH_ALEN); ++ memcpy(&header.addr3, &dest, ETH_ALEN); ++ } else if (ieee->iw_mode == IW_MODE_ADHOC) { ++ /* not From/To DS: Addr1 = DA, Addr2 = SA, ++ Addr3 = BSSID */ ++ memcpy(&header.addr1, dest, ETH_ALEN); ++ memcpy(&header.addr2, src, ETH_ALEN); ++ memcpy(&header.addr3, ieee->current_network.bssid, ETH_ALEN); ++ } ++ ++ header.frame_ctl = cpu_to_le16(fc); ++ ++ /* Determine fragmentation size based on destination (multicast ++ * and broadcast are not fragmented) */ ++ if (is_multicast_ether_addr(header.addr1) || ++ is_broadcast_ether_addr(header.addr1)) { ++ frag_size = MAX_FRAG_THRESHOLD; ++ qos_ctl |= QOS_CTL_NOTCONTAIN_ACK; ++ } ++ else { ++ frag_size = ieee->fts;//default:392 ++ qos_ctl = 0; ++ } ++ ++ //if (ieee->current_network.QoS_Enable) ++ if(qos_actived) ++ { ++ hdr_len = IEEE80211_3ADDR_LEN + 2; ++ ++ skb->priority = ieee80211_classify(skb, &ieee->current_network); ++ qos_ctl |= skb->priority; //set in the ieee80211_classify ++ header.qos_ctl = cpu_to_le16(qos_ctl & IEEE80211_QOS_TID); ++ } else { ++ hdr_len = IEEE80211_3ADDR_LEN; ++ } ++ /* Determine amount of payload per fragment. Regardless of if ++ * this stack is providing the full 802.11 header, one will ++ * eventually be affixed to this fragment -- so we must account for ++ * it when determining the amount of payload space. */ ++ bytes_per_frag = frag_size - hdr_len; ++ if (ieee->config & ++ (CFG_IEEE80211_COMPUTE_FCS | CFG_IEEE80211_RESERVE_FCS)) ++ bytes_per_frag -= IEEE80211_FCS_LEN; ++ ++ /* Each fragment may need to have room for encryptiong pre/postfix */ ++ if (encrypt) ++ bytes_per_frag -= crypt->ops->extra_prefix_len + ++ crypt->ops->extra_postfix_len; ++ ++ /* Number of fragments is the total bytes_per_frag / ++ * payload_per_fragment */ ++ nr_frags = bytes / bytes_per_frag; ++ bytes_last_frag = bytes % bytes_per_frag; ++ if (bytes_last_frag) ++ nr_frags++; ++ else ++ bytes_last_frag = bytes_per_frag; ++ ++ /* When we allocate the TXB we allocate enough space for the reserve ++ * and full fragment bytes (bytes_per_frag doesn't include prefix, ++ * postfix, header, FCS, etc.) */ ++ txb = ieee80211_alloc_txb(nr_frags, frag_size + ieee->tx_headroom, GFP_ATOMIC); ++ if (unlikely(!txb)) { ++ printk(KERN_WARNING "%s: Could not allocate TXB\n", ++ ieee->dev->name); ++ goto failed; ++ } ++ txb->encrypted = encrypt; ++ txb->payload_size = bytes; ++ ++ //if (ieee->current_network.QoS_Enable) ++ if(qos_actived) ++ { ++ txb->queue_index = UP2AC(skb->priority); ++ } else { ++ txb->queue_index = WME_AC_BK;; ++ } ++ ++ ++ ++ for (i = 0; i < nr_frags; i++) { ++ skb_frag = txb->fragments[i]; ++ tcb_desc = (cb_desc *)(skb_frag->cb + MAX_DEV_ADDR_SIZE); ++ if(qos_actived){ ++ skb_frag->priority = skb->priority;//UP2AC(skb->priority); ++ tcb_desc->queue_index = UP2AC(skb->priority); ++ } else { ++ skb_frag->priority = WME_AC_BK; ++ tcb_desc->queue_index = WME_AC_BK; ++ } ++ skb_reserve(skb_frag, ieee->tx_headroom); ++ ++ if (encrypt){ ++ if (ieee->hwsec_active) ++ tcb_desc->bHwSec = 1; ++ else ++ tcb_desc->bHwSec = 0; ++ skb_reserve(skb_frag, crypt->ops->extra_prefix_len); ++ } ++ else ++ { ++ tcb_desc->bHwSec = 0; ++ } ++ frag_hdr = (struct ieee80211_hdr_3addrqos *)skb_put(skb_frag, hdr_len); ++ memcpy(frag_hdr, &header, hdr_len); ++ ++ /* If this is not the last fragment, then add the MOREFRAGS ++ * bit to the frame control */ ++ if (i != nr_frags - 1) { ++ frag_hdr->frame_ctl = cpu_to_le16( ++ fc | IEEE80211_FCTL_MOREFRAGS); ++ bytes = bytes_per_frag; ++ ++ } else { ++ /* The last fragment takes the remaining length */ ++ bytes = bytes_last_frag; ++ } ++ //if(ieee->current_network.QoS_Enable) ++ if(qos_actived) ++ { ++ // add 1 only indicate to corresponding seq number control 2006/7/12 ++ frag_hdr->seq_ctl = cpu_to_le16(ieee->seq_ctrl[UP2AC(skb->priority)+1]<<4 | i); ++ } else { ++ frag_hdr->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0]<<4 | i); ++ } ++ ++ /* Put a SNAP header on the first fragment */ ++ if (i == 0) { ++ ieee80211_put_snap( ++ skb_put(skb_frag, SNAP_SIZE + sizeof(u16)), ++ ether_type); ++ bytes -= SNAP_SIZE + sizeof(u16); ++ } ++ ++ memcpy(skb_put(skb_frag, bytes), skb->data, bytes); ++ ++ /* Advance the SKB... */ ++ skb_pull(skb, bytes); ++ ++ /* Encryption routine will move the header forward in order ++ * to insert the IV between the header and the payload */ ++ if (encrypt) ++ ieee80211_encrypt_fragment(ieee, skb_frag, hdr_len); ++ if (ieee->config & ++ (CFG_IEEE80211_COMPUTE_FCS | CFG_IEEE80211_RESERVE_FCS)) ++ skb_put(skb_frag, 4); ++ } ++ ++ if(qos_actived) ++ { ++ if (ieee->seq_ctrl[UP2AC(skb->priority) + 1] == 0xFFF) ++ ieee->seq_ctrl[UP2AC(skb->priority) + 1] = 0; ++ else ++ ieee->seq_ctrl[UP2AC(skb->priority) + 1]++; ++ } else { ++ if (ieee->seq_ctrl[0] == 0xFFF) ++ ieee->seq_ctrl[0] = 0; ++ else ++ ieee->seq_ctrl[0]++; ++ } ++ }else{ ++ if (unlikely(skb->len < sizeof(struct ieee80211_hdr_3addr))) { ++ printk(KERN_WARNING "%s: skb too small (%d).\n", ++ ieee->dev->name, skb->len); ++ goto success; ++ } ++ ++ txb = ieee80211_alloc_txb(1, skb->len, GFP_ATOMIC); ++ if(!txb){ ++ printk(KERN_WARNING "%s: Could not allocate TXB\n", ++ ieee->dev->name); ++ goto failed; ++ } ++ ++ txb->encrypted = 0; ++ txb->payload_size = skb->len; ++ memcpy(skb_put(txb->fragments[0],skb->len), skb->data, skb->len); ++ } ++ ++ success: ++//WB add to fill data tcb_desc here. only first fragment is considered, need to change, and you may remove to other place. ++ if (txb) ++ { ++#if 1 ++ cb_desc *tcb_desc = (cb_desc *)(txb->fragments[0]->cb + MAX_DEV_ADDR_SIZE); ++ tcb_desc->bTxEnableFwCalcDur = 1; ++ if (is_multicast_ether_addr(header.addr1)) ++ tcb_desc->bMulticast = 1; ++ if (is_broadcast_ether_addr(header.addr1)) ++ tcb_desc->bBroadcast = 1; ++ ieee80211_txrate_selectmode(ieee, tcb_desc); ++ if ( tcb_desc->bMulticast || tcb_desc->bBroadcast) ++ tcb_desc->data_rate = ieee->basic_rate; ++ else ++ //tcb_desc->data_rate = CURRENT_RATE(ieee->current_network.mode, ieee->rate, ieee->HTCurrentOperaRate); ++ tcb_desc->data_rate = CURRENT_RATE(ieee->mode, ieee->rate, ieee->HTCurrentOperaRate); ++ ieee80211_qurey_ShortPreambleMode(ieee, tcb_desc); ++ ieee80211_tx_query_agg_cap(ieee, txb->fragments[0], tcb_desc); ++ ieee80211_query_HTCapShortGI(ieee, tcb_desc); ++ ieee80211_query_BandwidthMode(ieee, tcb_desc); ++ ieee80211_query_protectionmode(ieee, tcb_desc, txb->fragments[0]); ++ ieee80211_query_seqnum(ieee, txb->fragments[0], header.addr1); ++// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, txb->fragments[0]->data, txb->fragments[0]->len); ++ //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, tcb_desc, sizeof(cb_desc)); ++#endif ++ } ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ dev_kfree_skb_any(skb); ++ if (txb) { ++ if (ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE){ ++ ieee80211_softmac_xmit(txb, ieee); ++ }else{ ++ if ((*ieee->hard_start_xmit)(txb, dev) == 0) { ++ stats->tx_packets++; ++ stats->tx_bytes += txb->payload_size; ++ return 0; ++ } ++ ieee80211_txb_free(txb); ++ } ++ } ++ ++ return 0; ++ ++ failed: ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ netif_stop_queue(dev); ++ stats->tx_errors++; ++ return 1; ++ ++} ++ ++//EXPORT_SYMBOL(ieee80211_txb_free); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_wx.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_wx.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/ieee80211_wx.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,1032 @@ ++/****************************************************************************** ++ ++ Copyright(c) 2004 Intel Corporation. All rights reserved. ++ ++ Portions of this file are based on the WEP enablement code provided by the ++ Host AP project hostap-drivers v0.1.3 ++ Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen ++ ++ Copyright (c) 2002-2003, Jouni Malinen ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms of version 2 of the GNU General Public License as ++ published by the Free Software Foundation. ++ ++ This program is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., 59 ++ Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ ++ The full GNU General Public License is included in this distribution in the ++ file called LICENSE. ++ ++ Contact Information: ++ James P. Ketrenos ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++******************************************************************************/ ++#include ++#include ++#include ++#include ++ ++#include "ieee80211.h" ++#if 0 ++static const char *ieee80211_modes[] = { ++ "?", "a", "b", "ab", "g", "ag", "bg", "abg" ++}; ++#endif ++struct modes_unit { ++ char *mode_string; ++ int mode_size; ++}; ++struct modes_unit ieee80211_modes[] = { ++ {"a",1}, ++ {"b",1}, ++ {"g",1}, ++ {"?",1}, ++ {"N-24G",5}, ++ {"N-5G",4}, ++}; ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,20)) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) ++static inline char * ++iwe_stream_add_event_rsl(char * stream, /* Stream of events */ ++ char * ends, /* End of stream */ ++ struct iw_event *iwe, /* Payload */ ++ int event_len) /* Real size of payload */ ++{ ++ /* Check if it's possible */ ++ if((stream + event_len) < ends) { ++ iwe->len = event_len; ++ ndelay(1); //new ++ memcpy(stream, (char *) iwe, event_len); ++ stream += event_len; ++ } ++ return stream; ++} ++#else ++#define iwe_stream_add_event_rsl iwe_stream_add_event ++#endif ++ ++#define MAX_CUSTOM_LEN 64 ++static inline char *rtl819x_translate_scan(struct ieee80211_device *ieee, ++ char *start, char *stop, ++ struct ieee80211_network *network, ++ struct iw_request_info *info) ++{ ++ char custom[MAX_CUSTOM_LEN]; ++ char proto_name[IFNAMSIZ]; ++ char *pname = proto_name; ++ char *p; ++ struct iw_event iwe; ++ int i, j; ++ u16 max_rate, rate; ++ static u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33}; ++ ++ /* First entry *MUST* be the AP MAC address */ ++ iwe.cmd = SIOCGIWAP; ++ iwe.u.ap_addr.sa_family = ARPHRD_ETHER; ++ memcpy(iwe.u.ap_addr.sa_data, network->bssid, ETH_ALEN); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_ADDR_LEN); ++#else ++ start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_ADDR_LEN); ++#endif ++ /* Remaining entries will be displayed in the order we provide them */ ++ ++ /* Add the ESSID */ ++ iwe.cmd = SIOCGIWESSID; ++ iwe.u.data.flags = 1; ++// if (network->flags & NETWORK_EMPTY_ESSID) { ++ if (network->ssid_len == 0) { ++ iwe.u.data.length = sizeof(""); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_point(info, start, stop, &iwe, ""); ++#else ++ start = iwe_stream_add_point(start, stop, &iwe, ""); ++#endif ++ } else { ++ iwe.u.data.length = min(network->ssid_len, (u8)32); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_point(info, start, stop, &iwe, network->ssid); ++#else ++ start = iwe_stream_add_point(start, stop, &iwe, network->ssid); ++#endif ++ } ++ /* Add the protocol name */ ++ iwe.cmd = SIOCGIWNAME; ++ for(i=0; i<(sizeof(ieee80211_modes)/sizeof(ieee80211_modes[0])); i++) { ++ if(network->mode&(1<= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_CHAR_LEN); ++#else ++ start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_CHAR_LEN); ++#endif ++ /* Add mode */ ++ iwe.cmd = SIOCGIWMODE; ++ if (network->capability & ++ (WLAN_CAPABILITY_BSS | WLAN_CAPABILITY_IBSS)) { ++ if (network->capability & WLAN_CAPABILITY_BSS) ++ iwe.u.mode = IW_MODE_MASTER; ++ else ++ iwe.u.mode = IW_MODE_ADHOC; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_UINT_LEN); ++#else ++ start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_UINT_LEN); ++#endif ++ } ++ ++ /* Add frequency/channel */ ++ iwe.cmd = SIOCGIWFREQ; ++/* iwe.u.freq.m = ieee80211_frequency(network->channel, network->mode); ++ iwe.u.freq.e = 3; */ ++ iwe.u.freq.m = network->channel; ++ iwe.u.freq.e = 0; ++ iwe.u.freq.i = 0; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_FREQ_LEN); ++#else ++ start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_FREQ_LEN); ++#endif ++ /* Add encryption capability */ ++ iwe.cmd = SIOCGIWENCODE; ++ if (network->capability & WLAN_CAPABILITY_PRIVACY) ++ iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; ++ else ++ iwe.u.data.flags = IW_ENCODE_DISABLED; ++ iwe.u.data.length = 0; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_point(info, start, stop, &iwe, network->ssid); ++#else ++ start = iwe_stream_add_point(start, stop, &iwe, network->ssid); ++#endif ++ /* Add basic and extended rates */ ++ max_rate = 0; ++ p = custom; ++ p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): "); ++ for (i = 0, j = 0; i < network->rates_len; ) { ++ if (j < network->rates_ex_len && ++ ((network->rates_ex[j] & 0x7F) < ++ (network->rates[i] & 0x7F))) ++ rate = network->rates_ex[j++] & 0x7F; ++ else ++ rate = network->rates[i++] & 0x7F; ++ if (rate > max_rate) ++ max_rate = rate; ++ p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), ++ "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); ++ } ++ for (; j < network->rates_ex_len; j++) { ++ rate = network->rates_ex[j] & 0x7F; ++ p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), ++ "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); ++ if (rate > max_rate) ++ max_rate = rate; ++ } ++ ++ if (network->mode >= IEEE_N_24G)//add N rate here; ++ { ++ PHT_CAPABILITY_ELE ht_cap = NULL; ++ bool is40M = false, isShortGI = false; ++ u8 max_mcs = 0; ++ if (!memcmp(network->bssht.bdHTCapBuf, EWC11NHTCap, 4)) ++ ht_cap = (PHT_CAPABILITY_ELE)&network->bssht.bdHTCapBuf[4]; ++ else ++ ht_cap = (PHT_CAPABILITY_ELE)&network->bssht.bdHTCapBuf[0]; ++ is40M = (ht_cap->ChlWidth)?1:0; ++ isShortGI = (ht_cap->ChlWidth)? ++ ((ht_cap->ShortGI40Mhz)?1:0): ++ ((ht_cap->ShortGI20Mhz)?1:0); ++ ++ max_mcs = HTGetHighestMCSRate(ieee, ht_cap->MCS, MCS_FILTER_ALL); ++ rate = MCS_DATA_RATE[is40M][isShortGI][max_mcs&0x7f]; ++ if (rate > max_rate) ++ max_rate = rate; ++ } ++#if 0 ++ printk("max rate:%d ===basic rate:\n", max_rate); ++ for (i=0;irates_len;i++) ++ printk(" %x", network->rates[i]); ++ printk("\n=======extend rate\n"); ++ for (i=0; irates_ex_len; i++) ++ printk(" %x", network->rates_ex[i]); ++ printk("\n"); ++#endif ++ iwe.cmd = SIOCGIWRATE; ++ iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0; ++ iwe.u.bitrate.value = max_rate * 500000; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_event_rsl(info, start, stop, &iwe, ++ IW_EV_PARAM_LEN); ++#else ++ start = iwe_stream_add_event_rsl(start, stop, &iwe, ++ IW_EV_PARAM_LEN); ++#endif ++ iwe.cmd = IWEVCUSTOM; ++ iwe.u.data.length = p - custom; ++ if (iwe.u.data.length) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_point(info, start, stop, &iwe, custom); ++#else ++ start = iwe_stream_add_point(start, stop, &iwe, custom); ++#endif ++ /* Add quality statistics */ ++ /* TODO: Fix these values... */ ++ iwe.cmd = IWEVQUAL; ++ iwe.u.qual.qual = network->stats.signal; ++ iwe.u.qual.level = network->stats.rssi; ++ iwe.u.qual.noise = network->stats.noise; ++ iwe.u.qual.updated = network->stats.mask & IEEE80211_STATMASK_WEMASK; ++ if (!(network->stats.mask & IEEE80211_STATMASK_RSSI)) ++ iwe.u.qual.updated |= IW_QUAL_LEVEL_INVALID; ++ if (!(network->stats.mask & IEEE80211_STATMASK_NOISE)) ++ iwe.u.qual.updated |= IW_QUAL_NOISE_INVALID; ++ if (!(network->stats.mask & IEEE80211_STATMASK_SIGNAL)) ++ iwe.u.qual.updated |= IW_QUAL_QUAL_INVALID; ++ iwe.u.qual.updated = 7; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_QUAL_LEN); ++#else ++ start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_QUAL_LEN); ++#endif ++ iwe.cmd = IWEVCUSTOM; ++ p = custom; ++ ++ iwe.u.data.length = p - custom; ++ if (iwe.u.data.length) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_point(info, start, stop, &iwe, custom); ++#else ++ start = iwe_stream_add_point(start, stop, &iwe, custom); ++#endif ++#if (WIRELESS_EXT < 18) ++ if (ieee->wpa_enabled && network->wpa_ie_len){ ++ char buf[MAX_WPA_IE_LEN * 2 + 30]; ++ // printk("WPA IE\n"); ++ u8 *p = buf; ++ p += sprintf(p, "wpa_ie="); ++ for (i = 0; i < network->wpa_ie_len; i++) { ++ p += sprintf(p, "%02x", network->wpa_ie[i]); ++ } ++ ++ memset(&iwe, 0, sizeof(iwe)); ++ iwe.cmd = IWEVCUSTOM; ++ iwe.u.data.length = strlen(buf); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_point(info, start, stop, &iwe, buf); ++#else ++ start = iwe_stream_add_point(start, stop, &iwe, buf); ++#endif ++ } ++ ++ if (ieee->wpa_enabled && network->rsn_ie_len){ ++ char buf[MAX_WPA_IE_LEN * 2 + 30]; ++ ++ u8 *p = buf; ++ p += sprintf(p, "rsn_ie="); ++ for (i = 0; i < network->rsn_ie_len; i++) { ++ p += sprintf(p, "%02x", network->rsn_ie[i]); ++ } ++ ++ memset(&iwe, 0, sizeof(iwe)); ++ iwe.cmd = IWEVCUSTOM; ++ iwe.u.data.length = strlen(buf); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_point(info, start, stop, &iwe, buf); ++#else ++ start = iwe_stream_add_point(start, stop, &iwe, buf); ++#endif ++ } ++#else ++ memset(&iwe, 0, sizeof(iwe)); ++ if (network->wpa_ie_len) ++ { ++ char buf[MAX_WPA_IE_LEN]; ++ memcpy(buf, network->wpa_ie, network->wpa_ie_len); ++ iwe.cmd = IWEVGENIE; ++ iwe.u.data.length = network->wpa_ie_len; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_point(info, start, stop, &iwe, buf); ++#else ++ start = iwe_stream_add_point(start, stop, &iwe, buf); ++#endif ++ } ++ memset(&iwe, 0, sizeof(iwe)); ++ if (network->rsn_ie_len) ++ { ++ char buf[MAX_WPA_IE_LEN]; ++ memcpy(buf, network->rsn_ie, network->rsn_ie_len); ++ iwe.cmd = IWEVGENIE; ++ iwe.u.data.length = network->rsn_ie_len; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_point(info, start, stop, &iwe, buf); ++#else ++ start = iwe_stream_add_point(start, stop, &iwe, buf); ++#endif ++ } ++#endif ++ ++ ++ /* Add EXTRA: Age to display seconds since last beacon/probe response ++ * for given network. */ ++ iwe.cmd = IWEVCUSTOM; ++ p = custom; ++ p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), ++ " Last beacon: %lums ago", (jiffies - network->last_scanned) / (HZ / 100)); ++ iwe.u.data.length = p - custom; ++ if (iwe.u.data.length) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++ start = iwe_stream_add_point(info, start, stop, &iwe, custom); ++#else ++ start = iwe_stream_add_point(start, stop, &iwe, custom); ++#endif ++ ++ return start; ++} ++ ++int ieee80211_wx_get_scan(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct ieee80211_network *network; ++ unsigned long flags; ++ ++ char *ev = extra; ++// char *stop = ev + IW_SCAN_MAX_DATA; ++ char *stop = ev + wrqu->data.length;//IW_SCAN_MAX_DATA; ++ //char *stop = ev + IW_SCAN_MAX_DATA; ++ int i = 0; ++ int err = 0; ++ IEEE80211_DEBUG_WX("Getting scan\n"); ++ down(&ieee->wx_sem); ++ spin_lock_irqsave(&ieee->lock, flags); ++ ++ list_for_each_entry(network, &ieee->network_list, list) { ++ i++; ++ if((stop-ev)<200) ++ { ++ err = -E2BIG; ++ break; ++ } ++ if (ieee->scan_age == 0 || ++ time_after(network->last_scanned + ieee->scan_age, jiffies)) ++ ev = rtl819x_translate_scan(ieee, ev, stop, network, info); ++ else ++ IEEE80211_DEBUG_SCAN( ++ "Not showing network '%s (" ++ MAC_FMT ")' due to age (%lums).\n", ++ escape_essid(network->ssid, ++ network->ssid_len), ++ MAC_ARG(network->bssid), ++ (jiffies - network->last_scanned) / (HZ / 100)); ++ } ++ ++ spin_unlock_irqrestore(&ieee->lock, flags); ++ up(&ieee->wx_sem); ++ wrqu->data.length = ev - extra; ++ wrqu->data.flags = 0; ++ ++ IEEE80211_DEBUG_WX("exit: %d networks returned.\n", i); ++ ++ return err; ++} ++ ++int ieee80211_wx_set_encode(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *keybuf) ++{ ++ struct iw_point *erq = &(wrqu->encoding); ++ struct net_device *dev = ieee->dev; ++ struct ieee80211_security sec = { ++ .flags = 0 ++ }; ++ int i, key, key_provided, len; ++ struct ieee80211_crypt_data **crypt; ++ ++ IEEE80211_DEBUG_WX("SET_ENCODE\n"); ++ ++ key = erq->flags & IW_ENCODE_INDEX; ++ if (key) { ++ if (key > WEP_KEYS) ++ return -EINVAL; ++ key--; ++ key_provided = 1; ++ } else { ++ key_provided = 0; ++ key = ieee->tx_keyidx; ++ } ++ ++ IEEE80211_DEBUG_WX("Key: %d [%s]\n", key, key_provided ? ++ "provided" : "default"); ++ crypt = &ieee->crypt[key]; ++ ++ if (erq->flags & IW_ENCODE_DISABLED) { ++ if (key_provided && *crypt) { ++ IEEE80211_DEBUG_WX("Disabling encryption on key %d.\n", ++ key); ++ ieee80211_crypt_delayed_deinit(ieee, crypt); ++ } else ++ IEEE80211_DEBUG_WX("Disabling encryption.\n"); ++ ++ /* Check all the keys to see if any are still configured, ++ * and if no key index was provided, de-init them all */ ++ for (i = 0; i < WEP_KEYS; i++) { ++ if (ieee->crypt[i] != NULL) { ++ if (key_provided) ++ break; ++ ieee80211_crypt_delayed_deinit( ++ ieee, &ieee->crypt[i]); ++ } ++ } ++ ++ if (i == WEP_KEYS) { ++ sec.enabled = 0; ++ sec.level = SEC_LEVEL_0; ++ sec.flags |= SEC_ENABLED | SEC_LEVEL; ++ } ++ ++ goto done; ++ } ++ ++ ++ ++ sec.enabled = 1; ++ sec.flags |= SEC_ENABLED; ++ ++ if (*crypt != NULL && (*crypt)->ops != NULL && ++ strcmp((*crypt)->ops->name, "WEP") != 0) { ++ /* changing to use WEP; deinit previously used algorithm ++ * on this key */ ++ ieee80211_crypt_delayed_deinit(ieee, crypt); ++ } ++ ++ if (*crypt == NULL) { ++ struct ieee80211_crypt_data *new_crypt; ++ ++ /* take WEP into use */ ++ new_crypt = kmalloc(sizeof(struct ieee80211_crypt_data), ++ GFP_KERNEL); ++ if (new_crypt == NULL) ++ return -ENOMEM; ++ memset(new_crypt, 0, sizeof(struct ieee80211_crypt_data)); ++ new_crypt->ops = ieee80211_get_crypto_ops("WEP"); ++ if (!new_crypt->ops) { ++ request_module("ieee80211_crypt_wep"); ++ new_crypt->ops = ieee80211_get_crypto_ops("WEP"); ++ } ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) ++ if (new_crypt->ops && try_module_get(new_crypt->ops->owner)) ++#else ++ if (new_crypt->ops && try_inc_mod_count(new_crypt->ops->owner)) ++#endif ++ new_crypt->priv = new_crypt->ops->init(key); ++ ++ if (!new_crypt->ops || !new_crypt->priv) { ++ kfree(new_crypt); ++ new_crypt = NULL; ++ ++ printk(KERN_WARNING "%s: could not initialize WEP: " ++ "load module ieee80211_crypt_wep\n", ++ dev->name); ++ return -EOPNOTSUPP; ++ } ++ *crypt = new_crypt; ++ } ++ ++ /* If a new key was provided, set it up */ ++ if (erq->length > 0) { ++ len = erq->length <= 5 ? 5 : 13; ++ memcpy(sec.keys[key], keybuf, erq->length); ++ if (len > erq->length) ++ memset(sec.keys[key] + erq->length, 0, ++ len - erq->length); ++ IEEE80211_DEBUG_WX("Setting key %d to '%s' (%d:%d bytes)\n", ++ key, escape_essid(sec.keys[key], len), ++ erq->length, len); ++ sec.key_sizes[key] = len; ++ (*crypt)->ops->set_key(sec.keys[key], len, NULL, ++ (*crypt)->priv); ++ sec.flags |= (1 << key); ++ /* This ensures a key will be activated if no key is ++ * explicitely set */ ++ if (key == sec.active_key) ++ sec.flags |= SEC_ACTIVE_KEY; ++ ieee->tx_keyidx = key; ++ ++ } else { ++ len = (*crypt)->ops->get_key(sec.keys[key], WEP_KEY_LEN, ++ NULL, (*crypt)->priv); ++ if (len == 0) { ++ /* Set a default key of all 0 */ ++ printk("Setting key %d to all zero.\n", ++ key); ++ ++ IEEE80211_DEBUG_WX("Setting key %d to all zero.\n", ++ key); ++ memset(sec.keys[key], 0, 13); ++ (*crypt)->ops->set_key(sec.keys[key], 13, NULL, ++ (*crypt)->priv); ++ sec.key_sizes[key] = 13; ++ sec.flags |= (1 << key); ++ } ++ ++ /* No key data - just set the default TX key index */ ++ if (key_provided) { ++ IEEE80211_DEBUG_WX( ++ "Setting key %d to default Tx key.\n", key); ++ ieee->tx_keyidx = key; ++ sec.active_key = key; ++ sec.flags |= SEC_ACTIVE_KEY; ++ } ++ } ++ ++ done: ++ ieee->open_wep = !(erq->flags & IW_ENCODE_RESTRICTED); ++ ieee->auth_mode = ieee->open_wep ? WLAN_AUTH_OPEN : WLAN_AUTH_SHARED_KEY; ++ sec.auth_mode = ieee->open_wep ? WLAN_AUTH_OPEN : WLAN_AUTH_SHARED_KEY; ++ sec.flags |= SEC_AUTH_MODE; ++ IEEE80211_DEBUG_WX("Auth: %s\n", sec.auth_mode == WLAN_AUTH_OPEN ? ++ "OPEN" : "SHARED KEY"); ++ ++ /* For now we just support WEP, so only set that security level... ++ * TODO: When WPA is added this is one place that needs to change */ ++ sec.flags |= SEC_LEVEL; ++ sec.level = SEC_LEVEL_1; /* 40 and 104 bit WEP */ ++ ++ if (ieee->set_security) ++ ieee->set_security(dev, &sec); ++ ++ /* Do not reset port if card is in Managed mode since resetting will ++ * generate new IEEE 802.11 authentication which may end up in looping ++ * with IEEE 802.1X. If your hardware requires a reset after WEP ++ * configuration (for example... Prism2), implement the reset_port in ++ * the callbacks structures used to initialize the 802.11 stack. */ ++ if (ieee->reset_on_keychange && ++ ieee->iw_mode != IW_MODE_INFRA && ++ ieee->reset_port && ieee->reset_port(dev)) { ++ printk(KERN_DEBUG "%s: reset_port failed\n", dev->name); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++int ieee80211_wx_get_encode(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *keybuf) ++{ ++ struct iw_point *erq = &(wrqu->encoding); ++ int len, key; ++ struct ieee80211_crypt_data *crypt; ++ ++ IEEE80211_DEBUG_WX("GET_ENCODE\n"); ++ ++ if(ieee->iw_mode == IW_MODE_MONITOR) ++ return -1; ++ ++ key = erq->flags & IW_ENCODE_INDEX; ++ if (key) { ++ if (key > WEP_KEYS) ++ return -EINVAL; ++ key--; ++ } else ++ key = ieee->tx_keyidx; ++ ++ crypt = ieee->crypt[key]; ++ erq->flags = key + 1; ++ ++ if (crypt == NULL || crypt->ops == NULL) { ++ erq->length = 0; ++ erq->flags |= IW_ENCODE_DISABLED; ++ return 0; ++ } ++#if 0 ++ if (strcmp(crypt->ops->name, "WEP") != 0) { ++ /* only WEP is supported with wireless extensions, so just ++ * report that encryption is used */ ++ erq->length = 0; ++ erq->flags |= IW_ENCODE_ENABLED; ++ return 0; ++ } ++#endif ++ len = crypt->ops->get_key(keybuf, SCM_KEY_LEN, NULL, crypt->priv); ++ erq->length = (len >= 0 ? len : 0); ++ ++ erq->flags |= IW_ENCODE_ENABLED; ++ ++ if (ieee->open_wep) ++ erq->flags |= IW_ENCODE_OPEN; ++ else ++ erq->flags |= IW_ENCODE_RESTRICTED; ++ ++ return 0; ++} ++#if (WIRELESS_EXT >= 18) ++int ieee80211_wx_set_encode_ext(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ struct net_device *dev = ieee->dev; ++ struct iw_point *encoding = &wrqu->encoding; ++ struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; ++ int i, idx; ++ int group_key = 0; ++ const char *alg, *module; ++ struct ieee80211_crypto_ops *ops; ++ struct ieee80211_crypt_data **crypt; ++ ++ struct ieee80211_security sec = { ++ .flags = 0, ++ }; ++ //printk("======>encoding flag:%x,ext flag:%x, ext alg:%d\n", encoding->flags,ext->ext_flags, ext->alg); ++ idx = encoding->flags & IW_ENCODE_INDEX; ++ if (idx) { ++ if (idx < 1 || idx > WEP_KEYS) ++ return -EINVAL; ++ idx--; ++ } else ++ idx = ieee->tx_keyidx; ++ ++ if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) { ++ ++ crypt = &ieee->crypt[idx]; ++ ++ group_key = 1; ++ } else { ++ /* some Cisco APs use idx>0 for unicast in dynamic WEP */ ++ //printk("not group key, flags:%x, ext->alg:%d\n", ext->ext_flags, ext->alg); ++ if (idx != 0 && ext->alg != IW_ENCODE_ALG_WEP) ++ return -EINVAL; ++ if (ieee->iw_mode == IW_MODE_INFRA) ++ ++ crypt = &ieee->crypt[idx]; ++ ++ else ++ return -EINVAL; ++ } ++ ++ sec.flags |= SEC_ENABLED;// | SEC_ENCRYPT; ++ if ((encoding->flags & IW_ENCODE_DISABLED) || ++ ext->alg == IW_ENCODE_ALG_NONE) { ++ if (*crypt) ++ ieee80211_crypt_delayed_deinit(ieee, crypt); ++ ++ for (i = 0; i < WEP_KEYS; i++) ++ ++ if (ieee->crypt[i] != NULL) ++ ++ break; ++ ++ if (i == WEP_KEYS) { ++ sec.enabled = 0; ++ // sec.encrypt = 0; ++ sec.level = SEC_LEVEL_0; ++ sec.flags |= SEC_LEVEL; ++ } ++ //printk("disabled: flag:%x\n", encoding->flags); ++ goto done; ++ } ++ ++ sec.enabled = 1; ++ // sec.encrypt = 1; ++#if 0 ++ if (group_key ? !ieee->host_mc_decrypt : ++ !(ieee->host_encrypt || ieee->host_decrypt || ++ ieee->host_encrypt_msdu)) ++ goto skip_host_crypt; ++#endif ++ switch (ext->alg) { ++ case IW_ENCODE_ALG_WEP: ++ alg = "WEP"; ++ module = "ieee80211_crypt_wep"; ++ break; ++ case IW_ENCODE_ALG_TKIP: ++ alg = "TKIP"; ++ module = "ieee80211_crypt_tkip"; ++ break; ++ case IW_ENCODE_ALG_CCMP: ++ alg = "CCMP"; ++ module = "ieee80211_crypt_ccmp"; ++ break; ++ default: ++ IEEE80211_DEBUG_WX("%s: unknown crypto alg %d\n", ++ dev->name, ext->alg); ++ ret = -EINVAL; ++ goto done; ++ } ++ printk("alg name:%s\n",alg); ++ ++ ops = ieee80211_get_crypto_ops(alg); ++ if (ops == NULL) { ++ request_module(module); ++ ops = ieee80211_get_crypto_ops(alg); ++ } ++ if (ops == NULL) { ++ IEEE80211_DEBUG_WX("%s: unknown crypto alg %d\n", ++ dev->name, ext->alg); ++ printk("========>unknown crypto alg %d\n", ext->alg); ++ ret = -EINVAL; ++ goto done; ++ } ++ ++ if (*crypt == NULL || (*crypt)->ops != ops) { ++ struct ieee80211_crypt_data *new_crypt; ++ ++ ieee80211_crypt_delayed_deinit(ieee, crypt); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)) ++ new_crypt = kzalloc(sizeof(*new_crypt), GFP_KERNEL); ++#else ++ new_crypt = kmalloc(sizeof(*new_crypt), GFP_KERNEL); ++ memset(new_crypt,0,sizeof(*new_crypt)); ++#endif ++ if (new_crypt == NULL) { ++ ret = -ENOMEM; ++ goto done; ++ } ++ new_crypt->ops = ops; ++ if (new_crypt->ops && try_module_get(new_crypt->ops->owner)) ++ new_crypt->priv = new_crypt->ops->init(idx); ++ if (new_crypt->priv == NULL) { ++ kfree(new_crypt); ++ ret = -EINVAL; ++ goto done; ++ } ++ *crypt = new_crypt; ++ ++ } ++ ++ if (ext->key_len > 0 && (*crypt)->ops->set_key && ++ (*crypt)->ops->set_key(ext->key, ext->key_len, ext->rx_seq, ++ (*crypt)->priv) < 0) { ++ IEEE80211_DEBUG_WX("%s: key setting failed\n", dev->name); ++ printk("key setting failed\n"); ++ ret = -EINVAL; ++ goto done; ++ } ++#if 1 ++ //skip_host_crypt: ++ //printk("skip_host_crypt:ext_flags:%x\n", ext->ext_flags); ++ if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) { ++ ieee->tx_keyidx = idx; ++ sec.active_key = idx; ++ sec.flags |= SEC_ACTIVE_KEY; ++ } ++ ++ if (ext->alg != IW_ENCODE_ALG_NONE) { ++ //memcpy(sec.keys[idx], ext->key, ext->key_len); ++ sec.key_sizes[idx] = ext->key_len; ++ sec.flags |= (1 << idx); ++ if (ext->alg == IW_ENCODE_ALG_WEP) { ++ // sec.encode_alg[idx] = SEC_ALG_WEP; ++ sec.flags |= SEC_LEVEL; ++ sec.level = SEC_LEVEL_1; ++ } else if (ext->alg == IW_ENCODE_ALG_TKIP) { ++ // sec.encode_alg[idx] = SEC_ALG_TKIP; ++ sec.flags |= SEC_LEVEL; ++ sec.level = SEC_LEVEL_2; ++ } else if (ext->alg == IW_ENCODE_ALG_CCMP) { ++ // sec.encode_alg[idx] = SEC_ALG_CCMP; ++ sec.flags |= SEC_LEVEL; ++ sec.level = SEC_LEVEL_3; ++ } ++ /* Don't set sec level for group keys. */ ++ if (group_key) ++ sec.flags &= ~SEC_LEVEL; ++ } ++#endif ++done: ++ if (ieee->set_security) ++ ieee->set_security(ieee->dev, &sec); ++ ++ if (ieee->reset_on_keychange && ++ ieee->iw_mode != IW_MODE_INFRA && ++ ieee->reset_port && ieee->reset_port(dev)) { ++ IEEE80211_DEBUG_WX("%s: reset_port failed\n", dev->name); ++ return -EINVAL; ++ } ++#endif ++ return ret; ++} ++ ++int ieee80211_wx_get_encode_ext(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct iw_point *encoding = &wrqu->encoding; ++ struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; ++ struct ieee80211_crypt_data *crypt; ++ int idx, max_key_len; ++ ++ max_key_len = encoding->length - sizeof(*ext); ++ if (max_key_len < 0) ++ return -EINVAL; ++ ++ idx = encoding->flags & IW_ENCODE_INDEX; ++ if (idx) { ++ if (idx < 1 || idx > WEP_KEYS) ++ return -EINVAL; ++ idx--; ++ } else ++ idx = ieee->tx_keyidx; ++ ++ if (!ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY && ++ ext->alg != IW_ENCODE_ALG_WEP) ++ if (idx != 0 || ieee->iw_mode != IW_MODE_INFRA) ++ return -EINVAL; ++ ++ crypt = ieee->crypt[idx]; ++ encoding->flags = idx + 1; ++ memset(ext, 0, sizeof(*ext)); ++ ++ if (crypt == NULL || crypt->ops == NULL ) { ++ ext->alg = IW_ENCODE_ALG_NONE; ++ ext->key_len = 0; ++ encoding->flags |= IW_ENCODE_DISABLED; ++ } else { ++ if (strcmp(crypt->ops->name, "WEP") == 0 ) ++ ext->alg = IW_ENCODE_ALG_WEP; ++ else if (strcmp(crypt->ops->name, "TKIP")) ++ ext->alg = IW_ENCODE_ALG_TKIP; ++ else if (strcmp(crypt->ops->name, "CCMP")) ++ ext->alg = IW_ENCODE_ALG_CCMP; ++ else ++ return -EINVAL; ++ ext->key_len = crypt->ops->get_key(ext->key, SCM_KEY_LEN, NULL, crypt->priv); ++ encoding->flags |= IW_ENCODE_ENABLED; ++ if (ext->key_len && ++ (ext->alg == IW_ENCODE_ALG_TKIP || ++ ext->alg == IW_ENCODE_ALG_CCMP)) ++ ext->ext_flags |= IW_ENCODE_EXT_TX_SEQ_VALID; ++ ++ } ++ ++ return 0; ++} ++ ++int ieee80211_wx_set_mlme(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ struct iw_mlme *mlme = (struct iw_mlme *) extra; ++ switch (mlme->cmd) { ++ case IW_MLME_DEAUTH: ++ case IW_MLME_DISASSOC: ++ ieee80211_disassociate(ieee); ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++#endif ++ return 0; ++} ++ ++int ieee80211_wx_set_auth(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ struct iw_param *data, char *extra) ++{ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ switch (data->flags & IW_AUTH_INDEX) { ++ case IW_AUTH_WPA_VERSION: ++ /*need to support wpa2 here*/ ++ //printk("wpa version:%x\n", data->value); ++ break; ++ case IW_AUTH_CIPHER_PAIRWISE: ++ case IW_AUTH_CIPHER_GROUP: ++ case IW_AUTH_KEY_MGMT: ++ /* ++ * * Host AP driver does not use these parameters and allows ++ * * wpa_supplicant to control them internally. ++ * */ ++ break; ++ case IW_AUTH_TKIP_COUNTERMEASURES: ++ ieee->tkip_countermeasures = data->value; ++ break; ++ case IW_AUTH_DROP_UNENCRYPTED: ++ ieee->drop_unencrypted = data->value; ++ break; ++ ++ case IW_AUTH_80211_AUTH_ALG: ++ //printk("======>%s():data->value is %d\n",__FUNCTION__,data->value); ++ // ieee->open_wep = (data->value&IW_AUTH_ALG_OPEN_SYSTEM)?1:0; ++ if(data->value & IW_AUTH_ALG_SHARED_KEY){ ++ ieee->open_wep = 0; ++ ieee->auth_mode = 1; ++ } ++ else if(data->value & IW_AUTH_ALG_OPEN_SYSTEM){ ++ ieee->open_wep = 1; ++ ieee->auth_mode = 0; ++ } ++ else if(data->value & IW_AUTH_ALG_LEAP){ ++ ieee->open_wep = 1; ++ ieee->auth_mode = 2; ++ //printk("hahahaa:LEAP\n"); ++ } ++ else ++ return -EINVAL; ++ //printk("open_wep:%d\n", ieee->open_wep); ++ break; ++ ++#if 1 ++ case IW_AUTH_WPA_ENABLED: ++ ieee->wpa_enabled = (data->value)?1:0; ++ //printk("enalbe wpa:%d\n", ieee->wpa_enabled); ++ break; ++ ++#endif ++ case IW_AUTH_RX_UNENCRYPTED_EAPOL: ++ ieee->ieee802_1x = data->value; ++ break; ++ case IW_AUTH_PRIVACY_INVOKED: ++ ieee->privacy_invoked = data->value; ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++#endif ++ return 0; ++} ++#endif ++#if 1 ++int ieee80211_wx_set_gen_ie(struct ieee80211_device *ieee, u8 *ie, size_t len) ++{ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++#if 0 ++ printk("====>%s()\n", __FUNCTION__); ++ { ++ int i; ++ for (i=0; iMAX_WPA_IE_LEN || (len && ie == NULL)) ++ { ++ // printk("return error out, len:%d\n", len); ++ return -EINVAL; ++ } ++ ++ ++ if (len) ++ { ++ if (len != ie[1]+2) ++ { ++ printk("len:%d, ie:%d\n", len, ie[1]); ++ return -EINVAL; ++ } ++ buf = kmalloc(len, GFP_KERNEL); ++ if (buf == NULL) ++ return -ENOMEM; ++ memcpy(buf, ie, len); ++ kfree(ieee->wpa_ie); ++ ieee->wpa_ie = buf; ++ ieee->wpa_ie_len = len; ++ } ++ else{ ++ if (ieee->wpa_ie) ++ kfree(ieee->wpa_ie); ++ ieee->wpa_ie = NULL; ++ ieee->wpa_ie_len = 0; ++ } ++#endif ++ return 0; ++ ++} ++#endif ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++//EXPORT_SYMBOL(ieee80211_wx_set_gen_ie); ++#if (WIRELESS_EXT >= 18) ++//EXPORT_SYMBOL(ieee80211_wx_set_mlme); ++//EXPORT_SYMBOL(ieee80211_wx_set_auth); ++//EXPORT_SYMBOL(ieee80211_wx_set_encode_ext); ++//EXPORT_SYMBOL(ieee80211_wx_get_encode_ext); ++#endif ++//EXPORT_SYMBOL(ieee80211_wx_get_scan); ++//EXPORT_SYMBOL(ieee80211_wx_set_encode); ++//EXPORT_SYMBOL(ieee80211_wx_get_encode); ++#else ++//EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_gen_ie); ++//EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_mlme); ++//EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_auth); ++//EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_encode_ext); ++//EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_scan); ++//EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_encode); ++//EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_encode); ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/internal.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/internal.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/internal.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,115 @@ ++/* ++ * Cryptographic API. ++ * ++ * Copyright (c) 2002 James Morris ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at your option) ++ * any later version. ++ * ++ */ ++#ifndef _CRYPTO_INTERNAL_H ++#define _CRYPTO_INTERNAL_H ++ ++ ++//#include ++#include "rtl_crypto.h" ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,20)) ++#define list_for_each_entry(pos, head, member) \ ++ for (pos = list_entry((head)->next, typeof(*pos), member), \ ++ prefetch(pos->member.next); \ ++ &pos->member != (head); \ ++ pos = list_entry(pos->member.next, typeof(*pos), member), \ ++ prefetch(pos->member.next)) ++ ++static inline void cond_resched(void) ++{ ++ if (need_resched()) { ++ set_current_state(TASK_RUNNING); ++ schedule(); ++ } ++} ++#endif ++ ++extern enum km_type crypto_km_types[]; ++ ++static inline enum km_type crypto_kmap_type(int out) ++{ ++ return crypto_km_types[(in_softirq() ? 2 : 0) + out]; ++} ++ ++static inline void *crypto_kmap(struct page *page, int out) ++{ ++ return kmap_atomic(page, crypto_kmap_type(out)); ++} ++ ++static inline void crypto_kunmap(void *vaddr, int out) ++{ ++ kunmap_atomic(vaddr, crypto_kmap_type(out)); ++} ++ ++static inline void crypto_yield(struct crypto_tfm *tfm) ++{ ++ if (!in_softirq()) ++ cond_resched(); ++} ++ ++static inline void *crypto_tfm_ctx(struct crypto_tfm *tfm) ++{ ++ return (void *)&tfm[1]; ++} ++ ++struct crypto_alg *crypto_alg_lookup(const char *name); ++ ++#ifdef CONFIG_KMOD ++void crypto_alg_autoload(const char *name); ++struct crypto_alg *crypto_alg_mod_lookup(const char *name); ++#else ++static inline struct crypto_alg *crypto_alg_mod_lookup(const char *name) ++{ ++ return crypto_alg_lookup(name); ++} ++#endif ++ ++#ifdef CONFIG_CRYPTO_HMAC ++int crypto_alloc_hmac_block(struct crypto_tfm *tfm); ++void crypto_free_hmac_block(struct crypto_tfm *tfm); ++#else ++static inline int crypto_alloc_hmac_block(struct crypto_tfm *tfm) ++{ ++ return 0; ++} ++ ++static inline void crypto_free_hmac_block(struct crypto_tfm *tfm) ++{ } ++#endif ++ ++#ifdef CONFIG_PROC_FS ++void __init crypto_init_proc(void); ++#else ++static inline void crypto_init_proc(void) ++{ } ++#endif ++ ++int crypto_init_digest_flags(struct crypto_tfm *tfm, u32 flags); ++int crypto_init_cipher_flags(struct crypto_tfm *tfm, u32 flags); ++int crypto_init_compress_flags(struct crypto_tfm *tfm, u32 flags); ++ ++int crypto_init_digest_ops(struct crypto_tfm *tfm); ++int crypto_init_cipher_ops(struct crypto_tfm *tfm); ++int crypto_init_compress_ops(struct crypto_tfm *tfm); ++ ++void crypto_exit_digest_ops(struct crypto_tfm *tfm); ++void crypto_exit_cipher_ops(struct crypto_tfm *tfm); ++void crypto_exit_compress_ops(struct crypto_tfm *tfm); ++ ++#endif /* _CRYPTO_INTERNAL_H */ ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/kmap_types.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/kmap_types.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/kmap_types.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,20 @@ ++#ifndef __KMAP_TYPES_H ++ ++#define __KMAP_TYPES_H ++ ++ ++enum km_type { ++ KM_BOUNCE_READ, ++ KM_SKB_SUNRPC_DATA, ++ KM_SKB_DATA_SOFTIRQ, ++ KM_USER0, ++ KM_USER1, ++ KM_BH_IRQ, ++ KM_SOFTIRQ0, ++ KM_SOFTIRQ1, ++ KM_TYPE_NR ++}; ++ ++#define _ASM_KMAP_TYPES_H ++ ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/michael_mic.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/michael_mic.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/michael_mic.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,194 @@ ++/* ++ * Cryptographic API ++ * ++ * Michael MIC (IEEE 802.11i/TKIP) keyed digest ++ * ++ * Copyright (c) 2004 Jouni Malinen ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++//#include ++#include "rtl_crypto.h" ++ ++ ++struct michael_mic_ctx { ++ u8 pending[4]; ++ size_t pending_len; ++ ++ u32 l, r; ++}; ++ ++ ++static inline u32 rotl(u32 val, int bits) ++{ ++ return (val << bits) | (val >> (32 - bits)); ++} ++ ++ ++static inline u32 rotr(u32 val, int bits) ++{ ++ return (val >> bits) | (val << (32 - bits)); ++} ++ ++ ++static inline u32 xswap(u32 val) ++{ ++ return ((val & 0x00ff00ff) << 8) | ((val & 0xff00ff00) >> 8); ++} ++ ++ ++#define michael_block(l, r) \ ++do { \ ++ r ^= rotl(l, 17); \ ++ l += r; \ ++ r ^= xswap(l); \ ++ l += r; \ ++ r ^= rotl(l, 3); \ ++ l += r; \ ++ r ^= rotr(l, 2); \ ++ l += r; \ ++} while (0) ++ ++ ++static inline u32 get_le32(const u8 *p) ++{ ++ return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); ++} ++ ++ ++static inline void put_le32(u8 *p, u32 v) ++{ ++ p[0] = v; ++ p[1] = v >> 8; ++ p[2] = v >> 16; ++ p[3] = v >> 24; ++} ++ ++ ++static void michael_init(void *ctx) ++{ ++ struct michael_mic_ctx *mctx = ctx; ++ mctx->pending_len = 0; ++} ++ ++ ++static void michael_update(void *ctx, const u8 *data, unsigned int len) ++{ ++ struct michael_mic_ctx *mctx = ctx; ++ ++ if (mctx->pending_len) { ++ int flen = 4 - mctx->pending_len; ++ if (flen > len) ++ flen = len; ++ memcpy(&mctx->pending[mctx->pending_len], data, flen); ++ mctx->pending_len += flen; ++ data += flen; ++ len -= flen; ++ ++ if (mctx->pending_len < 4) ++ return; ++ ++ mctx->l ^= get_le32(mctx->pending); ++ michael_block(mctx->l, mctx->r); ++ mctx->pending_len = 0; ++ } ++ ++ while (len >= 4) { ++ mctx->l ^= get_le32(data); ++ michael_block(mctx->l, mctx->r); ++ data += 4; ++ len -= 4; ++ } ++ ++ if (len > 0) { ++ mctx->pending_len = len; ++ memcpy(mctx->pending, data, len); ++ } ++} ++ ++ ++static void michael_final(void *ctx, u8 *out) ++{ ++ struct michael_mic_ctx *mctx = ctx; ++ u8 *data = mctx->pending; ++ ++ /* Last block and padding (0x5a, 4..7 x 0) */ ++ switch (mctx->pending_len) { ++ case 0: ++ mctx->l ^= 0x5a; ++ break; ++ case 1: ++ mctx->l ^= data[0] | 0x5a00; ++ break; ++ case 2: ++ mctx->l ^= data[0] | (data[1] << 8) | 0x5a0000; ++ break; ++ case 3: ++ mctx->l ^= data[0] | (data[1] << 8) | (data[2] << 16) | ++ 0x5a000000; ++ break; ++ } ++ michael_block(mctx->l, mctx->r); ++ /* l ^= 0; */ ++ michael_block(mctx->l, mctx->r); ++ ++ put_le32(out, mctx->l); ++ put_le32(out + 4, mctx->r); ++} ++ ++ ++static int michael_setkey(void *ctx, const u8 *key, unsigned int keylen, ++ u32 *flags) ++{ ++ struct michael_mic_ctx *mctx = ctx; ++ if (keylen != 8) { ++ if (flags) ++ *flags = CRYPTO_TFM_RES_BAD_KEY_LEN; ++ return -EINVAL; ++ } ++ mctx->l = get_le32(key); ++ mctx->r = get_le32(key + 4); ++ return 0; ++} ++ ++ ++static struct crypto_alg michael_mic_alg = { ++ .cra_name = "michael_mic", ++ .cra_flags = CRYPTO_ALG_TYPE_DIGEST, ++ .cra_blocksize = 8, ++ .cra_ctxsize = sizeof(struct michael_mic_ctx), ++ .cra_module = THIS_MODULE, ++ .cra_list = LIST_HEAD_INIT(michael_mic_alg.cra_list), ++ .cra_u = { .digest = { ++ .dia_digestsize = 8, ++ .dia_init = michael_init, ++ .dia_update = michael_update, ++ .dia_final = michael_final, ++ .dia_setkey = michael_setkey } } ++}; ++ ++ ++static int __init michael_mic_init(void) ++{ ++ return crypto_register_alg(&michael_mic_alg); ++} ++ ++ ++static void __exit michael_mic_exit(void) ++{ ++ crypto_unregister_alg(&michael_mic_alg); ++} ++ ++ ++module_init(michael_mic_init); ++module_exit(michael_mic_exit); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Michael MIC"); ++MODULE_AUTHOR("Jouni Malinen "); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/proc.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/proc.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/proc.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,116 @@ ++/* ++ * Scatterlist Cryptographic API. ++ * ++ * Procfs information. ++ * ++ * Copyright (c) 2002 James Morris ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at your option) ++ * any later version. ++ * ++ */ ++#include ++//#include ++#include "rtl_crypto.h" ++#include ++#include ++#include ++#include "internal.h" ++ ++extern struct list_head crypto_alg_list; ++extern struct rw_semaphore crypto_alg_sem; ++ ++static void *c_start(struct seq_file *m, loff_t *pos) ++{ ++ struct list_head *v; ++ loff_t n = *pos; ++ ++ down_read(&crypto_alg_sem); ++ list_for_each(v, &crypto_alg_list) ++ if (!n--) ++ return list_entry(v, struct crypto_alg, cra_list); ++ return NULL; ++} ++ ++static void *c_next(struct seq_file *m, void *p, loff_t *pos) ++{ ++ struct list_head *v = p; ++ ++ (*pos)++; ++ v = v->next; ++ return (v == &crypto_alg_list) ? ++ NULL : list_entry(v, struct crypto_alg, cra_list); ++} ++ ++static void c_stop(struct seq_file *m, void *p) ++{ ++ up_read(&crypto_alg_sem); ++} ++ ++static int c_show(struct seq_file *m, void *p) ++{ ++ struct crypto_alg *alg = (struct crypto_alg *)p; ++ ++ seq_printf(m, "name : %s\n", alg->cra_name); ++ seq_printf(m, "module : %s\n", ++ (alg->cra_module ? ++ alg->cra_module->name : ++ "kernel")); ++ ++ switch (alg->cra_flags & CRYPTO_ALG_TYPE_MASK) { ++ case CRYPTO_ALG_TYPE_CIPHER: ++ seq_printf(m, "type : cipher\n"); ++ seq_printf(m, "blocksize : %u\n", alg->cra_blocksize); ++ seq_printf(m, "min keysize : %u\n", ++ alg->cra_cipher.cia_min_keysize); ++ seq_printf(m, "max keysize : %u\n", ++ alg->cra_cipher.cia_max_keysize); ++ break; ++ ++ case CRYPTO_ALG_TYPE_DIGEST: ++ seq_printf(m, "type : digest\n"); ++ seq_printf(m, "blocksize : %u\n", alg->cra_blocksize); ++ seq_printf(m, "digestsize : %u\n", ++ alg->cra_digest.dia_digestsize); ++ break; ++ case CRYPTO_ALG_TYPE_COMPRESS: ++ seq_printf(m, "type : compression\n"); ++ break; ++ default: ++ seq_printf(m, "type : unknown\n"); ++ break; ++ } ++ ++ seq_putc(m, '\n'); ++ return 0; ++} ++ ++static struct seq_operations crypto_seq_ops = { ++ .start = c_start, ++ .next = c_next, ++ .stop = c_stop, ++ .show = c_show ++}; ++ ++static int crypto_info_open(struct inode *inode, struct file *file) ++{ ++ return seq_open(file, &crypto_seq_ops); ++} ++ ++static struct file_operations proc_crypto_ops = { ++ .open = crypto_info_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = seq_release ++}; ++ ++void __init crypto_init_proc(void) ++{ ++ struct proc_dir_entry *proc; ++ ++ proc = create_proc_entry("crypto", 0, NULL); ++ if (proc) ++ proc->proc_fops = &proc_crypto_ops; ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_BA.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_BA.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_BA.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,69 @@ ++#ifndef _BATYPE_H_ ++#define _BATYPE_H_ ++ ++#define TOTAL_TXBA_NUM 16 ++#define TOTAL_RXBA_NUM 16 ++ ++#define BA_SETUP_TIMEOUT 200 ++#define BA_INACT_TIMEOUT 60000 ++ ++#define BA_POLICY_DELAYED 0 ++#define BA_POLICY_IMMEDIATE 1 ++ ++#define ADDBA_STATUS_SUCCESS 0 ++#define ADDBA_STATUS_REFUSED 37 ++#define ADDBA_STATUS_INVALID_PARAM 38 ++ ++#define DELBA_REASON_QSTA_LEAVING 36 ++#define DELBA_REASON_END_BA 37 ++#define DELBA_REASON_UNKNOWN_BA 38 ++#define DELBA_REASON_TIMEOUT 39 ++/* whether need define BA Action frames here? ++struct ieee80211_ADDBA_Req{ ++ struct ieee80211_header_data header; ++ u8 category; ++ u8 ++} __attribute__ ((packed)); ++*/ ++//Is this need?I put here just to make it easier to define structure BA_RECORD //WB ++typedef union _SEQUENCE_CONTROL{ ++ u16 ShortData; ++ struct ++ { ++ u16 FragNum:4; ++ u16 SeqNum:12; ++ }field; ++}SEQUENCE_CONTROL, *PSEQUENCE_CONTROL; ++ ++typedef union _BA_PARAM_SET { ++ u8 charData[2]; ++ u16 shortData; ++ struct { ++ u16 AMSDU_Support:1; ++ u16 BAPolicy:1; ++ u16 TID:4; ++ u16 BufferSize:10; ++ } field; ++} BA_PARAM_SET, *PBA_PARAM_SET; ++ ++typedef union _DELBA_PARAM_SET { ++ u8 charData[2]; ++ u16 shortData; ++ struct { ++ u16 Reserved:11; ++ u16 Initiator:1; ++ u16 TID:4; ++ } field; ++} DELBA_PARAM_SET, *PDELBA_PARAM_SET; ++ ++typedef struct _BA_RECORD { ++ struct timer_list Timer; ++ u8 bValid; ++ u8 DialogToken; ++ BA_PARAM_SET BaParamSet; ++ u16 BaTimeoutValue; ++ SEQUENCE_CONTROL BaStartSeqCtrl; ++} BA_RECORD, *PBA_RECORD; ++ ++#endif //end _BATYPE_H_ ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_BAProc.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_BAProc.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_BAProc.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,779 @@ ++/******************************************************************************************************************************** ++ * This file is created to process BA Action Frame. According to 802.11 spec, there are 3 BA action types at all. And as BA is ++ * related to TS, this part need some struture defined in QOS side code. Also TX RX is going to be resturctured, so how to send ++ * ADDBAREQ ADDBARSP and DELBA packet is still on consideration. Temporarily use MANAGE QUEUE instead of Normal Queue. ++ * WB 2008-05-27 ++ * *****************************************************************************************************************************/ ++#include "ieee80211.h" ++#include "rtl819x_BA.h" ++ ++/******************************************************************************************************************** ++ *function: Activate BA entry. And if Time is nozero, start timer. ++ * input: PBA_RECORD pBA //BA entry to be enabled ++ * u16 Time //indicate time delay. ++ * output: none ++********************************************************************************************************************/ ++void ActivateBAEntry(struct ieee80211_device* ieee, PBA_RECORD pBA, u16 Time) ++{ ++ pBA->bValid = true; ++ if(Time != 0) ++ mod_timer(&pBA->Timer, jiffies + MSECS(Time)); ++} ++ ++/******************************************************************************************************************** ++ *function: deactivate BA entry, including its timer. ++ * input: PBA_RECORD pBA //BA entry to be disabled ++ * output: none ++********************************************************************************************************************/ ++void DeActivateBAEntry( struct ieee80211_device* ieee, PBA_RECORD pBA) ++{ ++ pBA->bValid = false; ++ del_timer_sync(&pBA->Timer); ++} ++/******************************************************************************************************************** ++ *function: deactivete BA entry in Tx Ts, and send DELBA. ++ * input: ++ * PTX_TS_RECORD pTxTs //Tx Ts which is to deactivate BA entry. ++ * output: none ++ * notice: As PTX_TS_RECORD structure will be defined in QOS, so wait to be merged. //FIXME ++********************************************************************************************************************/ ++u8 TxTsDeleteBA( struct ieee80211_device* ieee, PTX_TS_RECORD pTxTs) ++{ ++ PBA_RECORD pAdmittedBa = &pTxTs->TxAdmittedBARecord; //These two BA entries must exist in TS structure ++ PBA_RECORD pPendingBa = &pTxTs->TxPendingBARecord; ++ u8 bSendDELBA = false; ++ ++ // Delete pending BA ++ if(pPendingBa->bValid) ++ { ++ DeActivateBAEntry(ieee, pPendingBa); ++ bSendDELBA = true; ++ } ++ ++ // Delete admitted BA ++ if(pAdmittedBa->bValid) ++ { ++ DeActivateBAEntry(ieee, pAdmittedBa); ++ bSendDELBA = true; ++ } ++ ++ return bSendDELBA; ++} ++ ++/******************************************************************************************************************** ++ *function: deactivete BA entry in Tx Ts, and send DELBA. ++ * input: ++ * PRX_TS_RECORD pRxTs //Rx Ts which is to deactivate BA entry. ++ * output: none ++ * notice: As PRX_TS_RECORD structure will be defined in QOS, so wait to be merged. //FIXME, same with above ++********************************************************************************************************************/ ++u8 RxTsDeleteBA( struct ieee80211_device* ieee, PRX_TS_RECORD pRxTs) ++{ ++ PBA_RECORD pBa = &pRxTs->RxAdmittedBARecord; ++ u8 bSendDELBA = false; ++ ++ if(pBa->bValid) ++ { ++ DeActivateBAEntry(ieee, pBa); ++ bSendDELBA = true; ++ } ++ ++ return bSendDELBA; ++} ++ ++/******************************************************************************************************************** ++ *function: reset BA entry ++ * input: ++ * PBA_RECORD pBA //entry to be reset ++ * output: none ++********************************************************************************************************************/ ++void ResetBaEntry( PBA_RECORD pBA) ++{ ++ pBA->bValid = false; ++ pBA->BaParamSet.shortData = 0; ++ pBA->BaTimeoutValue = 0; ++ pBA->DialogToken = 0; ++ pBA->BaStartSeqCtrl.ShortData = 0; ++} ++//These functions need porting here or not? ++/******************************************************************************************************************************* ++ *function: construct ADDBAREQ and ADDBARSP frame here together. ++ * input: u8* Dst //ADDBA frame's destination ++ * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA. ++ * u16 StatusCode //status code in RSP and I will use it to indicate whether it's RSP or REQ(will I?) ++ * u8 type //indicate whether it's RSP(ACT_ADDBARSP) ow REQ(ACT_ADDBAREQ) ++ * output: none ++ * return: sk_buff* skb //return constructed skb to xmit ++*******************************************************************************************************************************/ ++static struct sk_buff* ieee80211_ADDBA(struct ieee80211_device* ieee, u8* Dst, PBA_RECORD pBA, u16 StatusCode, u8 type) ++{ ++ struct sk_buff *skb = NULL; ++ struct ieee80211_hdr_3addr* BAReq = NULL; ++ u8* tag = NULL; ++ u16 tmp = 0; ++ u16 len = ieee->tx_headroom + 9; ++ //category(1) + action field(1) + Dialog Token(1) + BA Parameter Set(2) + BA Timeout Value(2) + BA Start SeqCtrl(2)(or StatusCode(2)) ++ IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), frame(%d) sentd to:"MAC_FMT", ieee->dev:%p\n", __FUNCTION__, type, MAC_ARG(Dst), ieee->dev); ++ if (pBA == NULL||ieee == NULL) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "pBA(%p) is NULL or ieee(%p) is NULL\n", pBA, ieee); ++ return NULL; ++ } ++ skb = dev_alloc_skb(len + sizeof( struct ieee80211_hdr_3addr)); //need to add something others? FIXME ++ if (skb == NULL) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't alloc skb for ADDBA_REQ\n"); ++ return NULL; ++ } ++ ++ memset(skb->data, 0, sizeof( struct ieee80211_hdr_3addr)); //I wonder whether it's necessary. Apparently kernel will not do it when alloc a skb. ++ skb_reserve(skb, ieee->tx_headroom); ++ ++ BAReq = ( struct ieee80211_hdr_3addr *) skb_put(skb,sizeof( struct ieee80211_hdr_3addr)); ++ ++ memcpy(BAReq->addr1, Dst, ETH_ALEN); ++ memcpy(BAReq->addr2, ieee->dev->dev_addr, ETH_ALEN); ++ ++ memcpy(BAReq->addr3, ieee->current_network.bssid, ETH_ALEN); ++ ++ BAReq->frame_ctl = cpu_to_le16(IEEE80211_STYPE_MANAGE_ACT); //action frame ++ ++ //tag += sizeof( struct ieee80211_hdr_3addr); //move to action field ++ tag = (u8*)skb_put(skb, 9); ++ *tag ++= ACT_CAT_BA; ++ *tag ++= type; ++ // Dialog Token ++ *tag ++= pBA->DialogToken; ++ ++ if (ACT_ADDBARSP == type) ++ { ++ // Status Code ++ printk("=====>to send ADDBARSP\n"); ++ tmp = cpu_to_le16(StatusCode); ++ memcpy(tag, (u8*)&tmp, 2); ++ tag += 2; ++ } ++ // BA Parameter Set ++ tmp = cpu_to_le16(pBA->BaParamSet.shortData); ++ memcpy(tag, (u8*)&tmp, 2); ++ tag += 2; ++ // BA Timeout Value ++ tmp = cpu_to_le16(pBA->BaTimeoutValue); ++ memcpy(tag, (u8*)&tmp, 2); ++ tag += 2; ++ ++ if (ACT_ADDBAREQ == type) ++ { ++ // BA Start SeqCtrl ++ memcpy(tag,(u8*)&(pBA->BaStartSeqCtrl), 2); ++ tag += 2; ++ } ++ ++ IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len); ++ return skb; ++ //return NULL; ++} ++ ++#if 0 //I try to merge ADDBA_REQ and ADDBA_RSP frames together.. ++/******************************************************************************************************************** ++ *function: construct ADDBAREQ frame ++ * input: u8* dst //ADDBARsp frame's destination ++ * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA_RSP. ++ * u16 StatusCode //status code. ++ * output: none ++ * return: sk_buff* skb //return constructed skb to xmit ++********************************************************************************************************************/ ++static struct sk_buff* ieee80211_ADDBA_Rsp( IN struct ieee80211_device* ieee, u8* dst, PBA_RECORD pBA, u16 StatusCode) ++{ ++ OCTET_STRING osADDBAFrame, tmp; ++ ++ FillOctetString(osADDBAFrame, Buffer, 0); ++ *pLength = 0; ++ ++ ConstructMaFrameHdr( ++ Adapter, ++ Addr, ++ ACT_CAT_BA, ++ ACT_ADDBARSP, ++ &osADDBAFrame ); ++ ++ // Dialog Token ++ FillOctetString(tmp, &pBA->DialogToken, 1); ++ PacketAppendData(&osADDBAFrame, tmp); ++ ++ // Status Code ++ FillOctetString(tmp, &StatusCode, 2); ++ PacketAppendData(&osADDBAFrame, tmp); ++ ++ // BA Parameter Set ++ FillOctetString(tmp, &pBA->BaParamSet, 2); ++ PacketAppendData(&osADDBAFrame, tmp); ++ ++ // BA Timeout Value ++ FillOctetString(tmp, &pBA->BaTimeoutValue, 2); ++ PacketAppendData(&osADDBAFrame, tmp); ++ ++ *pLength = osADDBAFrame.Length; ++} ++#endif ++ ++/******************************************************************************************************************** ++ *function: construct DELBA frame ++ * input: u8* dst //DELBA frame's destination ++ * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA ++ * TR_SELECT TxRxSelect //TX RX direction ++ * u16 ReasonCode //status code. ++ * output: none ++ * return: sk_buff* skb //return constructed skb to xmit ++********************************************************************************************************************/ ++static struct sk_buff* ieee80211_DELBA( ++ struct ieee80211_device* ieee, ++ u8* dst, ++ PBA_RECORD pBA, ++ TR_SELECT TxRxSelect, ++ u16 ReasonCode ++ ) ++{ ++ DELBA_PARAM_SET DelbaParamSet; ++ struct sk_buff *skb = NULL; ++ struct ieee80211_hdr_3addr* Delba = NULL; ++ u8* tag = NULL; ++ u16 tmp = 0; ++ //len = head len + DELBA Parameter Set(2) + Reason Code(2) ++ u16 len = 6 + ieee->tx_headroom; ++ ++ if (net_ratelimit()) ++ IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), ReasonCode(%d) sentd to:"MAC_FMT"\n", __FUNCTION__, ReasonCode, MAC_ARG(dst)); ++ ++ memset(&DelbaParamSet, 0, 2); ++ ++ DelbaParamSet.field.Initiator = (TxRxSelect==TX_DIR)?1:0; ++ DelbaParamSet.field.TID = pBA->BaParamSet.field.TID; ++ ++ skb = dev_alloc_skb(len + sizeof( struct ieee80211_hdr_3addr)); //need to add something others? FIXME ++ if (skb == NULL) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't alloc skb for ADDBA_REQ\n"); ++ return NULL; ++ } ++// memset(skb->data, 0, len+sizeof( struct ieee80211_hdr_3addr)); ++ skb_reserve(skb, ieee->tx_headroom); ++ ++ Delba = ( struct ieee80211_hdr_3addr *) skb_put(skb,sizeof( struct ieee80211_hdr_3addr)); ++ ++ memcpy(Delba->addr1, dst, ETH_ALEN); ++ memcpy(Delba->addr2, ieee->dev->dev_addr, ETH_ALEN); ++ memcpy(Delba->addr3, ieee->current_network.bssid, ETH_ALEN); ++ Delba->frame_ctl = cpu_to_le16(IEEE80211_STYPE_MANAGE_ACT); //action frame ++ ++ tag = (u8*)skb_put(skb, 6); ++ ++ *tag ++= ACT_CAT_BA; ++ *tag ++= ACT_DELBA; ++ ++ // DELBA Parameter Set ++ tmp = cpu_to_le16(DelbaParamSet.shortData); ++ memcpy(tag, (u8*)&tmp, 2); ++ tag += 2; ++ // Reason Code ++ tmp = cpu_to_le16(ReasonCode); ++ memcpy(tag, (u8*)&tmp, 2); ++ tag += 2; ++ ++ IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len); ++ if (net_ratelimit()) ++ IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "<=====%s()\n", __FUNCTION__); ++ return skb; ++} ++ ++/******************************************************************************************************************** ++ *function: send ADDBAReq frame out ++ * input: u8* dst //ADDBAReq frame's destination ++ * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA ++ * output: none ++ * notice: If any possible, please hide pBA in ieee. And temporarily use Manage Queue as softmac_mgmt_xmit() usually does ++********************************************************************************************************************/ ++void ieee80211_send_ADDBAReq(struct ieee80211_device* ieee, u8* dst, PBA_RECORD pBA) ++{ ++ struct sk_buff *skb = NULL; ++ skb = ieee80211_ADDBA(ieee, dst, pBA, 0, ACT_ADDBAREQ); //construct ACT_ADDBAREQ frames so set statuscode zero. ++ ++ if (skb) ++ { ++ softmac_mgmt_xmit(skb, ieee); ++ //add statistic needed here. ++ //and skb will be freed in softmac_mgmt_xmit(), so omit all dev_kfree_skb_any() outside softmac_mgmt_xmit() ++ //WB ++ } ++ else ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "alloc skb error in function %s()\n", __FUNCTION__); ++ } ++ return; ++} ++ ++/******************************************************************************************************************** ++ *function: send ADDBARSP frame out ++ * input: u8* dst //DELBA frame's destination ++ * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA ++ * u16 StatusCode //RSP StatusCode ++ * output: none ++ * notice: If any possible, please hide pBA in ieee. And temporarily use Manage Queue as softmac_mgmt_xmit() usually does ++********************************************************************************************************************/ ++void ieee80211_send_ADDBARsp(struct ieee80211_device* ieee, u8* dst, PBA_RECORD pBA, u16 StatusCode) ++{ ++ struct sk_buff *skb = NULL; ++ skb = ieee80211_ADDBA(ieee, dst, pBA, StatusCode, ACT_ADDBARSP); //construct ACT_ADDBARSP frames ++ if (skb) ++ { ++ softmac_mgmt_xmit(skb, ieee); ++ //same above ++ } ++ else ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "alloc skb error in function %s()\n", __FUNCTION__); ++ } ++ ++ return; ++ ++} ++/******************************************************************************************************************** ++ *function: send ADDBARSP frame out ++ * input: u8* dst //DELBA frame's destination ++ * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA ++ * TR_SELECT TxRxSelect //TX or RX ++ * u16 ReasonCode //DEL ReasonCode ++ * output: none ++ * notice: If any possible, please hide pBA in ieee. And temporarily use Manage Queue as softmac_mgmt_xmit() usually does ++********************************************************************************************************************/ ++ ++void ieee80211_send_DELBA(struct ieee80211_device* ieee, u8* dst, PBA_RECORD pBA, TR_SELECT TxRxSelect, u16 ReasonCode) ++{ ++ struct sk_buff *skb = NULL; ++ skb = ieee80211_DELBA(ieee, dst, pBA, TxRxSelect, ReasonCode); //construct ACT_ADDBARSP frames ++ if (skb) ++ { ++ softmac_mgmt_xmit(skb, ieee); ++ //same above ++ } ++ else ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "alloc skb error in function %s()\n", __FUNCTION__); ++ } ++ return ; ++} ++ ++/******************************************************************************************************************** ++ *function: RX ADDBAReq ++ * input: struct sk_buff * skb //incoming ADDBAReq skb. ++ * return: 0(pass), other(fail) ++ * notice: As this function need support of QOS, I comment some code out. And when qos is ready, this code need to be support. ++********************************************************************************************************************/ ++int ieee80211_rx_ADDBAReq( struct ieee80211_device* ieee, struct sk_buff *skb) ++{ ++ struct ieee80211_hdr_3addr* req = NULL; ++ u16 rc = 0; ++ u8 * dst = NULL, *pDialogToken = NULL, *tag = NULL; ++ PBA_RECORD pBA = NULL; ++ PBA_PARAM_SET pBaParamSet = NULL; ++ u16* pBaTimeoutVal = NULL; ++ PSEQUENCE_CONTROL pBaStartSeqCtrl = NULL; ++ PRX_TS_RECORD pTS = NULL; ++ ++ if (skb->len < sizeof( struct ieee80211_hdr_3addr) + 9) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, " Invalid skb len in BAREQ(%d / %d)\n", skb->len, (sizeof( struct ieee80211_hdr_3addr) + 9)); ++ return -1; ++ } ++ ++ IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len); ++ ++ req = ( struct ieee80211_hdr_3addr*) skb->data; ++ tag = (u8*)req; ++ dst = (u8*)(&req->addr2[0]); ++ tag += sizeof( struct ieee80211_hdr_3addr); ++ pDialogToken = tag + 2; //category+action ++ pBaParamSet = (PBA_PARAM_SET)(tag + 3); //+DialogToken ++ pBaTimeoutVal = (u16*)(tag + 5); ++ pBaStartSeqCtrl = (PSEQUENCE_CONTROL)(req + 7); ++ ++ printk("====================>rx ADDBAREQ from :"MAC_FMT"\n", MAC_ARG(dst)); ++//some other capability is not ready now. ++ if( (ieee->current_network.qos_data.active == 0) || ++ (ieee->pHTInfo->bCurrentHTSupport == false)) //|| ++ // (ieee->pStaQos->bEnableRxImmBA == false) ) ++ { ++ rc = ADDBA_STATUS_REFUSED; ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "Failed to reply on ADDBA_REQ as some capability is not ready(%d, %d)\n", ieee->current_network.qos_data.active, ieee->pHTInfo->bCurrentHTSupport); ++ goto OnADDBAReq_Fail; ++ } ++ // Search for related traffic stream. ++ // If there is no matched TS, reject the ADDBA request. ++ if( !GetTs( ++ ieee, ++ (PTS_COMMON_INFO*)(&pTS), ++ dst, ++ (u8)(pBaParamSet->field.TID), ++ RX_DIR, ++ true) ) ++ { ++ rc = ADDBA_STATUS_REFUSED; ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't get TS in %s()\n", __FUNCTION__); ++ goto OnADDBAReq_Fail; ++ } ++ pBA = &pTS->RxAdmittedBARecord; ++ // To Determine the ADDBA Req content ++ // We can do much more check here, including BufferSize, AMSDU_Support, Policy, StartSeqCtrl... ++ // I want to check StartSeqCtrl to make sure when we start aggregation!!! ++ // ++ if(pBaParamSet->field.BAPolicy == BA_POLICY_DELAYED) ++ { ++ rc = ADDBA_STATUS_INVALID_PARAM; ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "BA Policy is not correct in %s()\n", __FUNCTION__); ++ goto OnADDBAReq_Fail; ++ } ++ // Admit the ADDBA Request ++ // ++ DeActivateBAEntry(ieee, pBA); ++ pBA->DialogToken = *pDialogToken; ++ pBA->BaParamSet = *pBaParamSet; ++ pBA->BaTimeoutValue = *pBaTimeoutVal; ++ pBA->BaStartSeqCtrl = *pBaStartSeqCtrl; ++ //for half N mode we only aggregate 1 frame ++ if (ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) ++ pBA->BaParamSet.field.BufferSize = 1; ++ else ++ pBA->BaParamSet.field.BufferSize = 32; ++ ActivateBAEntry(ieee, pBA, pBA->BaTimeoutValue); ++ ieee80211_send_ADDBARsp(ieee, dst, pBA, ADDBA_STATUS_SUCCESS); ++ ++ // End of procedure. ++ return 0; ++ ++OnADDBAReq_Fail: ++ { ++ BA_RECORD BA; ++ BA.BaParamSet = *pBaParamSet; ++ BA.BaTimeoutValue = *pBaTimeoutVal; ++ BA.DialogToken = *pDialogToken; ++ BA.BaParamSet.field.BAPolicy = BA_POLICY_IMMEDIATE; ++ ieee80211_send_ADDBARsp(ieee, dst, &BA, rc); ++ return 0; //we send RSP out. ++ } ++ ++} ++ ++/******************************************************************************************************************** ++ *function: RX ADDBARSP ++ * input: struct sk_buff * skb //incoming ADDBAReq skb. ++ * return: 0(pass), other(fail) ++ * notice: As this function need support of QOS, I comment some code out. And when qos is ready, this code need to be support. ++********************************************************************************************************************/ ++int ieee80211_rx_ADDBARsp( struct ieee80211_device* ieee, struct sk_buff *skb) ++{ ++ struct ieee80211_hdr_3addr* rsp = NULL; ++ PBA_RECORD pPendingBA, pAdmittedBA; ++ PTX_TS_RECORD pTS = NULL; ++ u8* dst = NULL, *pDialogToken = NULL, *tag = NULL; ++ u16* pStatusCode = NULL, *pBaTimeoutVal = NULL; ++ PBA_PARAM_SET pBaParamSet = NULL; ++ u16 ReasonCode; ++ ++ if (skb->len < sizeof( struct ieee80211_hdr_3addr) + 9) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, " Invalid skb len in BARSP(%d / %d)\n", skb->len, (sizeof( struct ieee80211_hdr_3addr) + 9)); ++ return -1; ++ } ++ rsp = ( struct ieee80211_hdr_3addr*)skb->data; ++ tag = (u8*)rsp; ++ dst = (u8*)(&rsp->addr2[0]); ++ tag += sizeof( struct ieee80211_hdr_3addr); ++ pDialogToken = tag + 2; ++ pStatusCode = (u16*)(tag + 3); ++ pBaParamSet = (PBA_PARAM_SET)(tag + 5); ++ pBaTimeoutVal = (u16*)(tag + 7); ++ ++ // Check the capability ++ // Since we can always receive A-MPDU, we just check if it is under HT mode. ++ if( ieee->current_network.qos_data.active == 0 || ++ ieee->pHTInfo->bCurrentHTSupport == false || ++ ieee->pHTInfo->bCurrentAMPDUEnable == false ) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "reject to ADDBA_RSP as some capability is not ready(%d, %d, %d)\n",ieee->current_network.qos_data.active, ieee->pHTInfo->bCurrentHTSupport, ieee->pHTInfo->bCurrentAMPDUEnable); ++ ReasonCode = DELBA_REASON_UNKNOWN_BA; ++ goto OnADDBARsp_Reject; ++ } ++ ++ ++ // ++ // Search for related TS. ++ // If there is no TS found, we wil reject ADDBA Rsp by sending DELBA frame. ++ // ++ if (!GetTs( ++ ieee, ++ (PTS_COMMON_INFO*)(&pTS), ++ dst, ++ (u8)(pBaParamSet->field.TID), ++ TX_DIR, ++ false) ) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't get TS in %s()\n", __FUNCTION__); ++ ReasonCode = DELBA_REASON_UNKNOWN_BA; ++ goto OnADDBARsp_Reject; ++ } ++ ++ pTS->bAddBaReqInProgress = false; ++ pPendingBA = &pTS->TxPendingBARecord; ++ pAdmittedBA = &pTS->TxAdmittedBARecord; ++ ++ ++ // ++ // Check if related BA is waiting for setup. ++ // If not, reject by sending DELBA frame. ++ // ++ if((pAdmittedBA->bValid==true)) ++ { ++ // Since BA is already setup, we ignore all other ADDBA Response. ++ IEEE80211_DEBUG(IEEE80211_DL_BA, "OnADDBARsp(): Recv ADDBA Rsp. Drop because already admit it! \n"); ++ return -1; ++ } ++ else if((pPendingBA->bValid == false) ||(*pDialogToken != pPendingBA->DialogToken)) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "OnADDBARsp(): Recv ADDBA Rsp. BA invalid, DELBA! \n"); ++ ReasonCode = DELBA_REASON_UNKNOWN_BA; ++ goto OnADDBARsp_Reject; ++ } ++ else ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_BA, "OnADDBARsp(): Recv ADDBA Rsp. BA is admitted! Status code:%X\n", *pStatusCode); ++ DeActivateBAEntry(ieee, pPendingBA); ++ } ++ ++ ++ if(*pStatusCode == ADDBA_STATUS_SUCCESS) ++ { ++ // ++ // Determine ADDBA Rsp content here. ++ // We can compare the value of BA parameter set that Peer returned and Self sent. ++ // If it is OK, then admitted. Or we can send DELBA to cancel BA mechanism. ++ // ++ if(pBaParamSet->field.BAPolicy == BA_POLICY_DELAYED) ++ { ++ // Since this is a kind of ADDBA failed, we delay next ADDBA process. ++ pTS->bAddBaReqDelayed = true; ++ DeActivateBAEntry(ieee, pAdmittedBA); ++ ReasonCode = DELBA_REASON_END_BA; ++ goto OnADDBARsp_Reject; ++ } ++ ++ ++ // ++ // Admitted condition ++ // ++ pAdmittedBA->DialogToken = *pDialogToken; ++ pAdmittedBA->BaTimeoutValue = *pBaTimeoutVal; ++ pAdmittedBA->BaStartSeqCtrl = pPendingBA->BaStartSeqCtrl; ++ pAdmittedBA->BaParamSet = *pBaParamSet; ++ DeActivateBAEntry(ieee, pAdmittedBA); ++ ActivateBAEntry(ieee, pAdmittedBA, *pBaTimeoutVal); ++ } ++ else ++ { ++ // Delay next ADDBA process. ++ pTS->bAddBaReqDelayed = true; ++ } ++ ++ // End of procedure ++ return 0; ++ ++OnADDBARsp_Reject: ++ { ++ BA_RECORD BA; ++ BA.BaParamSet = *pBaParamSet; ++ ieee80211_send_DELBA(ieee, dst, &BA, TX_DIR, ReasonCode); ++ return 0; ++ } ++ ++} ++ ++/******************************************************************************************************************** ++ *function: RX DELBA ++ * input: struct sk_buff * skb //incoming ADDBAReq skb. ++ * return: 0(pass), other(fail) ++ * notice: As this function need support of QOS, I comment some code out. And when qos is ready, this code need to be support. ++********************************************************************************************************************/ ++int ieee80211_rx_DELBA(struct ieee80211_device* ieee,struct sk_buff *skb) ++{ ++ struct ieee80211_hdr_3addr* delba = NULL; ++ PDELBA_PARAM_SET pDelBaParamSet = NULL; ++ u16* pReasonCode = NULL; ++ u8* dst = NULL; ++ ++ if (skb->len < sizeof( struct ieee80211_hdr_3addr) + 6) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, " Invalid skb len in DELBA(%d / %d)\n", skb->len, (sizeof( struct ieee80211_hdr_3addr) + 6)); ++ return -1; ++ } ++ ++ if(ieee->current_network.qos_data.active == 0 || ++ ieee->pHTInfo->bCurrentHTSupport == false ) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "received DELBA while QOS or HT is not supported(%d, %d)\n",ieee->current_network.qos_data.active, ieee->pHTInfo->bCurrentHTSupport); ++ return -1; ++ } ++ ++ IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len); ++ delba = ( struct ieee80211_hdr_3addr*)skb->data; ++ dst = (u8*)(&delba->addr2[0]); ++ delba += sizeof( struct ieee80211_hdr_3addr); ++ pDelBaParamSet = (PDELBA_PARAM_SET)(delba+2); ++ pReasonCode = (u16*)(delba+4); ++ ++ if(pDelBaParamSet->field.Initiator == 1) ++ { ++ PRX_TS_RECORD pRxTs; ++ ++ if( !GetTs( ++ ieee, ++ (PTS_COMMON_INFO*)&pRxTs, ++ dst, ++ (u8)pDelBaParamSet->field.TID, ++ RX_DIR, ++ false) ) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't get TS for RXTS in %s()\n", __FUNCTION__); ++ return -1; ++ } ++ ++ RxTsDeleteBA(ieee, pRxTs); ++ } ++ else ++ { ++ PTX_TS_RECORD pTxTs; ++ ++ if(!GetTs( ++ ieee, ++ (PTS_COMMON_INFO*)&pTxTs, ++ dst, ++ (u8)pDelBaParamSet->field.TID, ++ TX_DIR, ++ false) ) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't get TS for TXTS in %s()\n", __FUNCTION__); ++ return -1; ++ } ++ ++ pTxTs->bUsingBa = false; ++ pTxTs->bAddBaReqInProgress = false; ++ pTxTs->bAddBaReqDelayed = false; ++ del_timer_sync(&pTxTs->TsAddBaTimer); ++ //PlatformCancelTimer(Adapter, &pTxTs->TsAddBaTimer); ++ TxTsDeleteBA(ieee, pTxTs); ++ } ++ return 0; ++} ++ ++// ++// ADDBA initiate. This can only be called by TX side. ++// ++void ++TsInitAddBA( ++ struct ieee80211_device* ieee, ++ PTX_TS_RECORD pTS, ++ u8 Policy, ++ u8 bOverwritePending ++ ) ++{ ++ PBA_RECORD pBA = &pTS->TxPendingBARecord; ++ ++ if(pBA->bValid==true && bOverwritePending==false) ++ return; ++ ++ // Set parameters to "Pending" variable set ++ DeActivateBAEntry(ieee, pBA); ++ ++ pBA->DialogToken++; // DialogToken: Only keep the latest dialog token ++ pBA->BaParamSet.field.AMSDU_Support = 0; // Do not support A-MSDU with A-MPDU now!! ++ pBA->BaParamSet.field.BAPolicy = Policy; // Policy: Delayed or Immediate ++ pBA->BaParamSet.field.TID = pTS->TsCommonInfo.TSpec.f.TSInfo.field.ucTSID; // TID ++ // BufferSize: This need to be set according to A-MPDU vector ++ pBA->BaParamSet.field.BufferSize = 32; // BufferSize: This need to be set according to A-MPDU vector ++ pBA->BaTimeoutValue = 0; // Timeout value: Set 0 to disable Timer ++ pBA->BaStartSeqCtrl.field.SeqNum = (pTS->TxCurSeq + 3) % 4096; // Block Ack will start after 3 packets later. ++ ++ ActivateBAEntry(ieee, pBA, BA_SETUP_TIMEOUT); ++ ++ ieee80211_send_ADDBAReq(ieee, pTS->TsCommonInfo.Addr, pBA); ++} ++ ++void ++TsInitDelBA( struct ieee80211_device* ieee, PTS_COMMON_INFO pTsCommonInfo, TR_SELECT TxRxSelect) ++{ ++ ++ if(TxRxSelect == TX_DIR) ++ { ++ PTX_TS_RECORD pTxTs = (PTX_TS_RECORD)pTsCommonInfo; ++ ++ if(TxTsDeleteBA(ieee, pTxTs)) ++ ieee80211_send_DELBA( ++ ieee, ++ pTsCommonInfo->Addr, ++ (pTxTs->TxAdmittedBARecord.bValid)?(&pTxTs->TxAdmittedBARecord):(&pTxTs->TxPendingBARecord), ++ TxRxSelect, ++ DELBA_REASON_END_BA); ++ } ++ else if(TxRxSelect == RX_DIR) ++ { ++ PRX_TS_RECORD pRxTs = (PRX_TS_RECORD)pTsCommonInfo; ++ if(RxTsDeleteBA(ieee, pRxTs)) ++ ieee80211_send_DELBA( ++ ieee, ++ pTsCommonInfo->Addr, ++ &pRxTs->RxAdmittedBARecord, ++ TxRxSelect, ++ DELBA_REASON_END_BA ); ++ } ++} ++/******************************************************************************************************************** ++ *function: BA setup timer ++ * input: unsigned long data //acturally we send TX_TS_RECORD or RX_TS_RECORD to these timer ++ * return: NULL ++ * notice: ++********************************************************************************************************************/ ++void BaSetupTimeOut(unsigned long data) ++{ ++ PTX_TS_RECORD pTxTs = (PTX_TS_RECORD)data; ++ ++ pTxTs->bAddBaReqInProgress = false; ++ pTxTs->bAddBaReqDelayed = true; ++ pTxTs->TxPendingBARecord.bValid = false; ++} ++ ++void TxBaInactTimeout(unsigned long data) ++{ ++ PTX_TS_RECORD pTxTs = (PTX_TS_RECORD)data; ++ struct ieee80211_device *ieee = container_of(pTxTs, struct ieee80211_device, TxTsRecord[pTxTs->num]); ++ TxTsDeleteBA(ieee, pTxTs); ++ ieee80211_send_DELBA( ++ ieee, ++ pTxTs->TsCommonInfo.Addr, ++ &pTxTs->TxAdmittedBARecord, ++ TX_DIR, ++ DELBA_REASON_TIMEOUT); ++} ++ ++void RxBaInactTimeout(unsigned long data) ++{ ++ PRX_TS_RECORD pRxTs = (PRX_TS_RECORD)data; ++ struct ieee80211_device *ieee = container_of(pRxTs, struct ieee80211_device, RxTsRecord[pRxTs->num]); ++ ++ RxTsDeleteBA(ieee, pRxTs); ++ ieee80211_send_DELBA( ++ ieee, ++ pRxTs->TsCommonInfo.Addr, ++ &pRxTs->RxAdmittedBARecord, ++ RX_DIR, ++ DELBA_REASON_TIMEOUT); ++ return ; ++} ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_HT.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_HT.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_HT.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,481 @@ ++#ifndef _RTL819XU_HTTYPE_H_ ++#define _RTL819XU_HTTYPE_H_ ++ ++//------------------------------------------------------------ ++// The HT Capability element is present in beacons, association request, ++// reassociation request and probe response frames ++//------------------------------------------------------------ ++ ++// ++// Operation mode value ++// ++#define HT_OPMODE_NO_PROTECT 0 ++#define HT_OPMODE_OPTIONAL 1 ++#define HT_OPMODE_40MHZ_PROTECT 2 ++#define HT_OPMODE_MIXED 3 ++ ++// ++// MIMO Power Save Setings ++// ++#define MIMO_PS_STATIC 0 ++#define MIMO_PS_DYNAMIC 1 ++#define MIMO_PS_NOLIMIT 3 ++ ++ ++// ++// There should be 128 bits to cover all of the MCS rates. However, since ++// 8190 does not support too much rates, one integer is quite enough. ++// ++ ++#define sHTCLng 4 ++ ++ ++#define HT_SUPPORTED_MCS_1SS_BITMAP 0x000000ff ++#define HT_SUPPORTED_MCS_2SS_BITMAP 0x0000ff00 ++#define HT_SUPPORTED_MCS_1SS_2SS_BITMAP HT_MCS_1SS_BITMAP|HT_MCS_1SS_2SS_BITMAP ++ ++ ++typedef enum _HT_MCS_RATE{ ++ HT_MCS0 = 0x00000001, ++ HT_MCS1 = 0x00000002, ++ HT_MCS2 = 0x00000004, ++ HT_MCS3 = 0x00000008, ++ HT_MCS4 = 0x00000010, ++ HT_MCS5 = 0x00000020, ++ HT_MCS6 = 0x00000040, ++ HT_MCS7 = 0x00000080, ++ HT_MCS8 = 0x00000100, ++ HT_MCS9 = 0x00000200, ++ HT_MCS10 = 0x00000400, ++ HT_MCS11 = 0x00000800, ++ HT_MCS12 = 0x00001000, ++ HT_MCS13 = 0x00002000, ++ HT_MCS14 = 0x00004000, ++ HT_MCS15 = 0x00008000, ++ // Do not define MCS32 here although 8190 support MCS32 ++}HT_MCS_RATE,*PHT_MCS_RATE; ++ ++// ++// Represent Channel Width in HT Capabilities ++// ++typedef enum _HT_CHANNEL_WIDTH{ ++ HT_CHANNEL_WIDTH_20 = 0, ++ HT_CHANNEL_WIDTH_20_40 = 1, ++}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH; ++ ++// ++// Represent Extention Channel Offset in HT Capabilities ++// This is available only in 40Mhz mode. ++// ++typedef enum _HT_EXTCHNL_OFFSET{ ++ HT_EXTCHNL_OFFSET_NO_EXT = 0, ++ HT_EXTCHNL_OFFSET_UPPER = 1, ++ HT_EXTCHNL_OFFSET_NO_DEF = 2, ++ HT_EXTCHNL_OFFSET_LOWER = 3, ++}HT_EXTCHNL_OFFSET, *PHT_EXTCHNL_OFFSET; ++ ++typedef enum _CHNLOP{ ++ CHNLOP_NONE = 0, // No Action now ++ CHNLOP_SCAN = 1, // Scan in progress ++ CHNLOP_SWBW = 2, // Bandwidth switching in progress ++ CHNLOP_SWCHNL = 3, // Software Channel switching in progress ++} CHNLOP, *PCHNLOP; ++ ++// Determine if the Channel Operation is in progress ++#define CHHLOP_IN_PROGRESS(_pHTInfo) \ ++ ((_pHTInfo)->ChnlOp > CHNLOP_NONE) ? TRUE : FALSE ++ ++/* ++typedef union _HT_CAPABILITY{ ++ u16 ShortData; ++ u8 CharData[2]; ++ struct ++ { ++ u16 AdvCoding:1; ++ u16 ChlWidth:1; ++ u16 MimoPwrSave:2; ++ u16 GreenField:1; ++ u16 ShortGI20Mhz:1; ++ u16 ShortGI40Mhz:1; ++ u16 STBC:1; ++ u16 BeamForm:1; ++ u16 DelayBA:1; ++ u16 MaxAMSDUSize:1; ++ u16 DssCCk:1; ++ u16 PSMP:1; ++ u16 Rsvd:3; ++ }Field; ++}HT_CAPABILITY, *PHT_CAPABILITY; ++ ++typedef union _HT_CAPABILITY_MACPARA{ ++ u8 ShortData; ++ u8 CharData[1]; ++ struct ++ { ++ u8 MaxRxAMPDU:2; ++ u8 MPDUDensity:2; ++ u8 Rsvd:4; ++ }Field; ++}HT_CAPABILITY_MACPARA, *PHT_CAPABILITY_MACPARA; ++*/ ++ ++typedef enum _HT_ACTION{ ++ ACT_RECOMMAND_WIDTH = 0, ++ ACT_MIMO_PWR_SAVE = 1, ++ ACT_PSMP = 2, ++ ACT_SET_PCO_PHASE = 3, ++ ACT_MIMO_CHL_MEASURE = 4, ++ ACT_RECIPROCITY_CORRECT = 5, ++ ACT_MIMO_CSI_MATRICS = 6, ++ ACT_MIMO_NOCOMPR_STEER = 7, ++ ACT_MIMO_COMPR_STEER = 8, ++ ACT_ANTENNA_SELECT = 9, ++} HT_ACTION, *PHT_ACTION; ++ ++ ++/* 2007/06/07 MH Define sub-carrier mode for 40MHZ. */ ++typedef enum _HT_Bandwidth_40MHZ_Sub_Carrier{ ++ SC_MODE_DUPLICATE = 0, ++ SC_MODE_LOWER = 1, ++ SC_MODE_UPPER = 2, ++ SC_MODE_FULL40MHZ = 3, ++}HT_BW40_SC_E; ++ ++typedef struct _HT_CAPABILITY_ELE{ ++ ++ //HT capability info ++ u8 AdvCoding:1; ++ u8 ChlWidth:1; ++ u8 MimoPwrSave:2; ++ u8 GreenField:1; ++ u8 ShortGI20Mhz:1; ++ u8 ShortGI40Mhz:1; ++ u8 TxSTBC:1; ++ u8 RxSTBC:2; ++ u8 DelayBA:1; ++ u8 MaxAMSDUSize:1; ++ u8 DssCCk:1; ++ u8 PSMP:1; ++ u8 Rsvd1:1; ++ u8 LSigTxopProtect:1; ++ ++ //MAC HT parameters info ++ u8 MaxRxAMPDUFactor:2; ++ u8 MPDUDensity:3; ++ u8 Rsvd2:3; ++ ++ //Supported MCS set ++ u8 MCS[16]; ++ ++ ++ //Extended HT Capability Info ++ u16 ExtHTCapInfo; ++ ++ //TXBF Capabilities ++ u8 TxBFCap[4]; ++ ++ //Antenna Selection Capabilities ++ u8 ASCap; ++ ++} __attribute__ ((packed)) HT_CAPABILITY_ELE, *PHT_CAPABILITY_ELE; ++ ++//------------------------------------------------------------ ++// The HT Information element is present in beacons ++// Only AP is required to include this element ++//------------------------------------------------------------ ++ ++typedef struct _HT_INFORMATION_ELE{ ++ u8 ControlChl; ++ ++ u8 ExtChlOffset:2; ++ u8 RecommemdedTxWidth:1; ++ u8 RIFS:1; ++ u8 PSMPAccessOnly:1; ++ u8 SrvIntGranularity:3; ++ ++ u8 OptMode:2; ++ u8 NonGFDevPresent:1; ++ u8 Revd1:5; ++ u8 Revd2:8; ++ ++ u8 Rsvd3:6; ++ u8 DualBeacon:1; ++ u8 DualCTSProtect:1; ++ ++ u8 SecondaryBeacon:1; ++ u8 LSigTxopProtectFull:1; ++ u8 PcoActive:1; ++ u8 PcoPhase:1; ++ u8 Rsvd4:4; ++ ++ u8 BasicMSC[16]; ++} __attribute__ ((packed)) HT_INFORMATION_ELE, *PHT_INFORMATION_ELE; ++ ++// ++// MIMO Power Save control field. ++// This is appear in MIMO Power Save Action Frame ++// ++typedef struct _MIMOPS_CTRL{ ++ u8 MimoPsEnable:1; ++ u8 MimoPsMode:1; ++ u8 Reserved:6; ++} MIMOPS_CTRL, *PMIMOPS_CTRL; ++ ++typedef enum _HT_SPEC_VER{ ++ HT_SPEC_VER_IEEE = 0, ++ HT_SPEC_VER_EWC = 1, ++}HT_SPEC_VER, *PHT_SPEC_VER; ++ ++typedef enum _HT_AGGRE_MODE_E{ ++ HT_AGG_AUTO = 0, ++ HT_AGG_FORCE_ENABLE = 1, ++ HT_AGG_FORCE_DISABLE = 2, ++}HT_AGGRE_MODE_E, *PHT_AGGRE_MODE_E; ++ ++//------------------------------------------------------------ ++// The Data structure is used to keep HT related variables when card is ++// configured as non-AP STA mode. **Note** Current_xxx should be set ++// to default value in HTInitializeHTInfo() ++//------------------------------------------------------------ ++ ++typedef struct _RT_HIGH_THROUGHPUT{ ++ u8 bEnableHT; ++ u8 bCurrentHTSupport; ++ ++ u8 bRegBW40MHz; // Tx 40MHz channel capablity ++ u8 bCurBW40MHz; // Tx 40MHz channel capability ++ ++ u8 bRegShortGI40MHz; // Tx Short GI for 40Mhz ++ u8 bCurShortGI40MHz; // Tx Short GI for 40MHz ++ ++ u8 bRegShortGI20MHz; // Tx Short GI for 20MHz ++ u8 bCurShortGI20MHz; // Tx Short GI for 20MHz ++ ++ u8 bRegSuppCCK; // Tx CCK rate capability ++ u8 bCurSuppCCK; // Tx CCK rate capability ++ ++ // 802.11n spec version for "peer" ++ HT_SPEC_VER ePeerHTSpecVer; ++ ++ ++ // HT related information for "Self" ++ HT_CAPABILITY_ELE SelfHTCap; // This is HT cap element sent to peer STA, which also indicate HT Rx capabilities. ++ HT_INFORMATION_ELE SelfHTInfo; // This is HT info element sent to peer STA, which also indicate HT Rx capabilities. ++ ++ // HT related information for "Peer" ++ u8 PeerHTCapBuf[32]; ++ u8 PeerHTInfoBuf[32]; ++ ++ ++ // A-MSDU related ++ u8 bAMSDU_Support; // This indicates Tx A-MSDU capability ++ u16 nAMSDU_MaxSize; // This indicates Tx A-MSDU capability ++ u8 bCurrent_AMSDU_Support; // This indicates Tx A-MSDU capability ++ u16 nCurrent_AMSDU_MaxSize; // This indicates Tx A-MSDU capability ++ ++ ++ // AMPDU related <2006.08.10 Emily> ++ u8 bAMPDUEnable; // This indicate Tx A-MPDU capability ++ u8 bCurrentAMPDUEnable; // This indicate Tx A-MPDU capability ++ u8 AMPDU_Factor; // This indicate Tx A-MPDU capability ++ u8 CurrentAMPDUFactor; // This indicate Tx A-MPDU capability ++ u8 MPDU_Density; // This indicate Tx A-MPDU capability ++ u8 CurrentMPDUDensity; // This indicate Tx A-MPDU capability ++ ++ // Forced A-MPDU enable ++ HT_AGGRE_MODE_E ForcedAMPDUMode; ++ u8 ForcedAMPDUFactor; ++ u8 ForcedMPDUDensity; ++ ++ // Forced A-MSDU enable ++ HT_AGGRE_MODE_E ForcedAMSDUMode; ++ u16 ForcedAMSDUMaxSize; ++ ++ u8 bForcedShortGI; ++ ++ u8 CurrentOpMode; ++ ++ // MIMO PS related ++ u8 SelfMimoPs; ++ u8 PeerMimoPs; ++ ++ // 40MHz Channel Offset settings. ++ HT_EXTCHNL_OFFSET CurSTAExtChnlOffset; ++ u8 bCurTxBW40MHz; // If we use 40 MHz to Tx ++ u8 PeerBandwidth; ++ ++ // For Bandwidth Switching ++ u8 bSwBwInProgress; ++ CHNLOP ChnlOp; // software switching channel in progress. By Bruce, 2008-02-15. ++ u8 SwBwStep; ++ //struct timer_list SwBwTimer; //moved to ieee80211_device. as timer_list need include some header file here. ++ ++ // For Realtek proprietary A-MPDU factor for aggregation ++ u8 bRegRT2RTAggregation; ++ u8 bCurrentRT2RTAggregation; ++ u8 bCurrentRT2RTLongSlotTime; ++ u8 szRT2RTAggBuffer[10]; ++ ++ // Rx Reorder control ++ u8 bRegRxReorderEnable; ++ u8 bCurRxReorderEnable; ++ u8 RxReorderWinSize; ++ u8 RxReorderPendingTime; ++ u16 RxReorderDropCounter; ++ ++#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE ++ u8 UsbTxAggrNum; ++#endif ++#ifdef USB_RX_AGGREGATION_SUPPORT ++ u8 UsbRxFwAggrEn; ++ u8 UsbRxFwAggrPageNum; ++ u8 UsbRxFwAggrPacketNum; ++ u8 UsbRxFwAggrTimeout; ++#endif ++ ++ // Add for Broadcom(Linksys) IOT. Joseph ++ u8 bIsPeerBcm; ++ ++ // For IOT issue. ++ u8 IOTPeer; ++ u32 IOTAction; ++} __attribute__ ((packed)) RT_HIGH_THROUGHPUT, *PRT_HIGH_THROUGHPUT; ++ ++ ++//------------------------------------------------------------ ++// The Data structure is used to keep HT related variable for "each Sta" ++// when card is configured as "AP mode" ++//------------------------------------------------------------ ++ ++typedef struct _RT_HTINFO_STA_ENTRY{ ++ u8 bEnableHT; ++ ++ u8 bSupportCck; ++ ++ u16 AMSDU_MaxSize; ++ ++ u8 AMPDU_Factor; ++ u8 MPDU_Density; ++ ++ u8 HTHighestOperaRate; ++ ++ u8 bBw40MHz; ++ ++ u8 MimoPs; ++ ++ u8 McsRateSet[16]; ++ ++ ++}RT_HTINFO_STA_ENTRY, *PRT_HTINFO_STA_ENTRY; ++ ++ ++ ++ ++ ++//------------------------------------------------------------ ++// The Data structure is used to keep HT related variable for "each AP" ++// when card is configured as "STA mode" ++//------------------------------------------------------------ ++ ++typedef struct _BSS_HT{ ++ ++ u8 bdSupportHT; ++ ++ // HT related elements ++ u8 bdHTCapBuf[32]; ++ u16 bdHTCapLen; ++ u8 bdHTInfoBuf[32]; ++ u16 bdHTInfoLen; ++ ++ HT_SPEC_VER bdHTSpecVer; ++ //HT_CAPABILITY_ELE bdHTCapEle; ++ //HT_INFORMATION_ELE bdHTInfoEle; ++ ++ u8 bdRT2RTAggregation; ++ u8 bdRT2RTLongSlotTime; ++} __attribute__ ((packed)) BSS_HT, *PBSS_HT; ++ ++typedef struct _MIMO_RSSI{ ++ u32 EnableAntenna; ++ u32 AntennaA; ++ u32 AntennaB; ++ u32 AntennaC; ++ u32 AntennaD; ++ u32 Average; ++}MIMO_RSSI, *PMIMO_RSSI; ++ ++typedef struct _MIMO_EVM{ ++ u32 EVM1; ++ u32 EVM2; ++}MIMO_EVM, *PMIMO_EVM; ++ ++typedef struct _FALSE_ALARM_STATISTICS{ ++ u32 Cnt_Parity_Fail; ++ u32 Cnt_Rate_Illegal; ++ u32 Cnt_Crc8_fail; ++ u32 Cnt_all; ++}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; ++ ++ ++extern u8 MCS_FILTER_ALL[16]; ++extern u8 MCS_FILTER_1SS[16]; ++ ++/* 2007/07/11 MH Modify the macro. Becaus STA may link with a N-AP. If we set ++ STA in A/B/G mode and AP is still in N mode. The macro will be wrong. We have ++ to add a macro to judge wireless mode. */ ++#define PICK_RATE(_nLegacyRate, _nMcsRate) \ ++ (_nMcsRate==0)?(_nLegacyRate&0x7f):(_nMcsRate) ++/* 2007/07/12 MH We only define legacy and HT wireless mode now. */ ++#define LEGACY_WIRELESS_MODE IEEE_MODE_MASK ++ ++#define CURRENT_RATE(WirelessMode, LegacyRate, HTRate) \ ++ ((WirelessMode & (LEGACY_WIRELESS_MODE))!=0)?\ ++ (LegacyRate):\ ++ (PICK_RATE(LegacyRate, HTRate)) ++ ++ ++ ++// MCS Bw 40 {1~7, 12~15,32} ++#define RATE_ADPT_1SS_MASK 0xFF ++#define RATE_ADPT_2SS_MASK 0xF0 //Skip MCS8~11 because mcs7 > mcs6, 9, 10, 11. 2007.01.16 by Emily ++#define RATE_ADPT_MCS32_MASK 0x01 ++ ++#define IS_11N_MCS_RATE(rate) (rate&0x80) ++ ++typedef enum _HT_AGGRE_SIZE{ ++ HT_AGG_SIZE_8K = 0, ++ HT_AGG_SIZE_16K = 1, ++ HT_AGG_SIZE_32K = 2, ++ HT_AGG_SIZE_64K = 3, ++}HT_AGGRE_SIZE_E, *PHT_AGGRE_SIZE_E; ++ ++/* Indicate different AP vendor for IOT issue */ ++typedef enum _HT_IOT_PEER ++{ ++ HT_IOT_PEER_UNKNOWN = 0, ++ HT_IOT_PEER_REALTEK = 1, ++ HT_IOT_PEER_BROADCOM = 2, ++ HT_IOT_PEER_RALINK = 3, ++ HT_IOT_PEER_ATHEROS = 4, ++ HT_IOT_PEER_CISCO= 5, ++ HT_IOT_PEER_MAX = 6 ++}HT_IOT_PEER_E, *PHTIOT_PEER_E; ++ ++// ++// IOT Action for different AP ++// ++typedef enum _HT_IOT_ACTION{ ++ HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001, ++ HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002, ++ HT_IOT_ACT_DISABLE_MCS14 = 0x00000004, ++ HT_IOT_ACT_DISABLE_MCS15 = 0x00000008, ++ HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010, ++ HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020, ++ HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040, ++ HT_IOT_ACT_CDD_FSYNC = 0x00000080, ++ HT_IOT_ACT_PURE_N_MODE = 0x00000100, ++ HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200, ++}HT_IOT_ACTION_E, *PHT_IOT_ACTION_E; ++ ++#endif //_RTL819XU_HTTYPE_H_ ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_HTProc.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_HTProc.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_HTProc.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,1719 @@ ++ ++//As this function is mainly ported from Windows driver, so leave the name little changed. If any confusion caused, tell me. Created by WB. 2008.05.08 ++#include "ieee80211.h" ++#include "rtl819x_HT.h" ++u8 MCS_FILTER_ALL[16] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; ++ ++u8 MCS_FILTER_1SS[16] = {0xff, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; ++ ++u16 MCS_DATA_RATE[2][2][77] = ++ { { {13, 26, 39, 52, 78, 104, 117, 130, 26, 52, 78 ,104, 156, 208, 234, 260, ++ 39, 78, 117, 234, 312, 351, 390, 52, 104, 156, 208, 312, 416, 468, 520, ++ 0, 78, 104, 130, 117, 156, 195, 104, 130, 130, 156, 182, 182, 208, 156, 195, ++ 195, 234, 273, 273, 312, 130, 156, 181, 156, 181, 208, 234, 208, 234, 260, 260, ++ 286, 195, 234, 273, 234, 273, 312, 351, 312, 351, 390, 390, 429}, // Long GI, 20MHz ++ {14, 29, 43, 58, 87, 116, 130, 144, 29, 58, 87, 116, 173, 231, 260, 289, ++ 43, 87, 130, 173, 260, 347, 390, 433, 58, 116, 173, 231, 347, 462, 520, 578, ++ 0, 87, 116, 144, 130, 173, 217, 116, 144, 144, 173, 202, 202, 231, 173, 217, ++ 217, 260, 303, 303, 347, 144, 173, 202, 173, 202, 231, 260, 231, 260, 289, 289, ++ 318, 217, 260, 303, 260, 303, 347, 390, 347, 390, 433, 433, 477} }, // Short GI, 20MHz ++ { {27, 54, 81, 108, 162, 216, 243, 270, 54, 108, 162, 216, 324, 432, 486, 540, ++ 81, 162, 243, 324, 486, 648, 729, 810, 108, 216, 324, 432, 648, 864, 972, 1080, ++ 12, 162, 216, 270, 243, 324, 405, 216, 270, 270, 324, 378, 378, 432, 324, 405, ++ 405, 486, 567, 567, 648, 270, 324, 378, 324, 378, 432, 486, 432, 486, 540, 540, ++ 594, 405, 486, 567, 486, 567, 648, 729, 648, 729, 810, 810, 891}, // Long GI, 40MHz ++ {30, 60, 90, 120, 180, 240, 270, 300, 60, 120, 180, 240, 360, 480, 540, 600, ++ 90, 180, 270, 360, 540, 720, 810, 900, 120, 240, 360, 480, 720, 960, 1080, 1200, ++ 13, 180, 240, 300, 270, 360, 450, 240, 300, 300, 360, 420, 420, 480, 360, 450, ++ 450, 540, 630, 630, 720, 300, 360, 420, 360, 420, 480, 540, 480, 540, 600, 600, ++ 660, 450, 540, 630, 540, 630, 720, 810, 720, 810, 900, 900, 990} } // Short GI, 40MHz ++ }; ++ ++static u8 UNKNOWN_BORADCOM[3] = {0x00, 0x14, 0xbf}; ++static u8 LINKSYSWRT330_LINKSYSWRT300_BROADCOM[3] = {0x00, 0x1a, 0x70}; ++static u8 LINKSYSWRT350_LINKSYSWRT150_BROADCOM[3] = {0x00, 0x1d, 0x7e}; ++static u8 NETGEAR834Bv2_BROADCOM[3] = {0x00, 0x1b, 0x2f}; ++static u8 BELKINF5D8233V1_RALINK[3] = {0x00, 0x17, 0x3f}; //cosa 03202008 ++static u8 BELKINF5D82334V3_RALINK[3] = {0x00, 0x1c, 0xdf}; ++static u8 PCI_RALINK[3] = {0x00, 0x90, 0xcc}; ++static u8 EDIMAX_RALINK[3] = {0x00, 0x0e, 0x2e}; ++static u8 AIRLINK_RALINK[3] = {0x00, 0x18, 0x02}; ++static u8 DLINK_ATHEROS[3] = {0x00, 0x1c, 0xf0}; ++static u8 CISCO_BROADCOM[3] = {0x00, 0x17, 0x94}; ++ ++// 2008/04/01 MH For Cisco G mode RX TP We need to change FW duration. Shoud we put the ++// code in other place?? ++//static u8 WIFI_CISCO_G_AP[3] = {0x00, 0x40, 0x96}; ++/******************************************************************************************************************** ++ *function: This function update default settings in pHTInfo structure ++ * input: PRT_HIGH_THROUGHPUT pHTInfo ++ * output: none ++ * return: none ++ * notice: These value need be modified if any changes. ++ * *****************************************************************************************************************/ ++void HTUpdateDefaultSetting(struct ieee80211_device* ieee) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ //const typeof( ((struct ieee80211_device *)0)->pHTInfo ) *__mptr = &pHTInfo; ++ ++ //printk("pHTinfo:%p, &pHTinfo:%p, mptr:%p, offsetof:%x\n", pHTInfo, &pHTInfo, __mptr, offsetof(struct ieee80211_device, pHTInfo)); ++ //printk("===>ieee:%p,\n", ieee); ++ // ShortGI support ++ pHTInfo->bRegShortGI20MHz= 1; ++ pHTInfo->bRegShortGI40MHz= 1; ++ ++ // 40MHz channel support ++ pHTInfo->bRegBW40MHz = 1; ++ ++ // CCK rate support in 40MHz channel ++ if(pHTInfo->bRegBW40MHz) ++ pHTInfo->bRegSuppCCK = 1; ++ else ++ pHTInfo->bRegSuppCCK = true; ++ ++ // AMSDU related ++ pHTInfo->nAMSDU_MaxSize = 7935UL; ++ pHTInfo->bAMSDU_Support = 0; ++ ++ // AMPDU related ++ pHTInfo->bAMPDUEnable = 1; ++ pHTInfo->AMPDU_Factor = 2; //// 0: 2n13(8K), 1:2n14(16K), 2:2n15(32K), 3:2n16(64k) ++ pHTInfo->MPDU_Density = 0;// 0: No restriction, 1: 1/8usec, 2: 1/4usec, 3: 1/2usec, 4: 1usec, 5: 2usec, 6: 4usec, 7:8usec ++ ++ // MIMO Power Save ++ pHTInfo->SelfMimoPs = 3;// 0: Static Mimo Ps, 1: Dynamic Mimo Ps, 3: No Limitation, 2: Reserved(Set to 3 automatically.) ++ if(pHTInfo->SelfMimoPs == 2) ++ pHTInfo->SelfMimoPs = 3; ++ // 8190 only. Assign rate operation mode to firmware ++ ieee->bTxDisableRateFallBack = 0; ++ ieee->bTxUseDriverAssingedRate = 0; ++ ++#ifdef TO_DO_LIST ++ // 8190 only. Assign duration operation mode to firmware ++ pMgntInfo->bTxEnableFwCalcDur = (BOOLEAN)pNdisCommon->bRegTxEnableFwCalcDur; ++#endif ++ // 8190 only, Realtek proprietary aggregation mode ++ // Set MPDUDensity=2, 1: Set MPDUDensity=2(32k) for Realtek AP and set MPDUDensity=0(8k) for others ++ pHTInfo->bRegRT2RTAggregation = 1;//0: Set MPDUDensity=2, 1: Set MPDUDensity=2(32k) for Realtek AP and set MPDUDensity=0(8k) for others ++ ++ // For Rx Reorder Control ++ pHTInfo->bRegRxReorderEnable = 1; ++ pHTInfo->RxReorderWinSize = 64; ++ pHTInfo->RxReorderPendingTime = 30; ++ ++#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE ++ pHTInfo->UsbTxAggrNum = 4; ++#endif ++#ifdef USB_RX_AGGREGATION_SUPPORT ++ pHTInfo->UsbRxFwAggrEn = 1; ++ pHTInfo->UsbRxFwAggrPageNum = 24; ++ pHTInfo->UsbRxFwAggrPacketNum = 8; ++ pHTInfo->UsbRxFwAggrTimeout = 16; ////usb rx FW aggregation timeout threshold.It's in units of 64us ++#endif ++ ++ ++} ++/******************************************************************************************************************** ++ *function: This function print out each field on HT capability IE mainly from (Beacon/ProbeRsp/AssocReq) ++ * input: u8* CapIE //Capability IE to be printed out ++ * u8* TitleString //mainly print out caller function ++ * output: none ++ * return: none ++ * notice: Driver should not print out this message by default. ++ * *****************************************************************************************************************/ ++void HTDebugHTCapability(u8* CapIE, u8* TitleString ) ++{ ++ ++ static u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33}; // For 11n EWC definition, 2007.07.17, by Emily ++ PHT_CAPABILITY_ELE pCapELE; ++ ++ if(!memcmp(CapIE, EWC11NHTCap, sizeof(EWC11NHTCap))) ++ { ++ //EWC IE ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "EWC IE in %s()\n", __FUNCTION__); ++ pCapELE = (PHT_CAPABILITY_ELE)(&CapIE[4]); ++ }else ++ pCapELE = (PHT_CAPABILITY_ELE)(&CapIE[0]); ++ ++ IEEE80211_DEBUG(IEEE80211_DL_HT, ". Called by %s\n", TitleString ); ++ ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupported Channel Width = %s\n", (pCapELE->ChlWidth)?"20MHz": "20/40MHz"); ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport Short GI for 20M = %s\n", (pCapELE->ShortGI20Mhz)?"YES": "NO"); ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport Short GI for 40M = %s\n", (pCapELE->ShortGI40Mhz)?"YES": "NO"); ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport TX STBC = %s\n", (pCapELE->TxSTBC)?"YES": "NO"); ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tMax AMSDU Size = %s\n", (pCapELE->MaxAMSDUSize)?"3839": "7935"); ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport CCK in 20/40 mode = %s\n", (pCapELE->DssCCk)?"YES": "NO"); ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tMax AMPDU Factor = %d\n", pCapELE->MaxRxAMPDUFactor); ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tMPDU Density = %d\n", pCapELE->MPDUDensity); ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tMCS Rate Set = [%x][%x][%x][%x][%x]\n", pCapELE->MCS[0],\ ++ pCapELE->MCS[1], pCapELE->MCS[2], pCapELE->MCS[3], pCapELE->MCS[4]); ++ return; ++ ++} ++/******************************************************************************************************************** ++ *function: This function print out each field on HT Information IE mainly from (Beacon/ProbeRsp) ++ * input: u8* InfoIE //Capability IE to be printed out ++ * u8* TitleString //mainly print out caller function ++ * output: none ++ * return: none ++ * notice: Driver should not print out this message by default. ++ * *****************************************************************************************************************/ ++void HTDebugHTInfo(u8* InfoIE, u8* TitleString) ++{ ++ ++ static u8 EWC11NHTInfo[] = {0x00, 0x90, 0x4c, 0x34}; // For 11n EWC definition, 2007.07.17, by Emily ++ PHT_INFORMATION_ELE pHTInfoEle; ++ ++ if(!memcmp(InfoIE, EWC11NHTInfo, sizeof(EWC11NHTInfo))) ++ { ++ // Not EWC IE ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "EWC IE in %s()\n", __FUNCTION__); ++ pHTInfoEle = (PHT_INFORMATION_ELE)(&InfoIE[4]); ++ }else ++ pHTInfoEle = (PHT_INFORMATION_ELE)(&InfoIE[0]); ++ ++ ++ IEEE80211_DEBUG(IEEE80211_DL_HT, ". Called by %s\n", TitleString); ++ ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tPrimary channel = %d\n", pHTInfoEle->ControlChl); ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSenondary channel ="); ++ switch(pHTInfoEle->ExtChlOffset) ++ { ++ case 0: ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "Not Present\n"); ++ break; ++ case 1: ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "Upper channel\n"); ++ break; ++ case 2: ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "Reserved. Eooro!!!\n"); ++ break; ++ case 3: ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "Lower Channel\n"); ++ break; ++ } ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tRecommended channel width = %s\n", (pHTInfoEle->RecommemdedTxWidth)?"20Mhz": "40Mhz"); ++ ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tOperation mode for protection = "); ++ switch(pHTInfoEle->OptMode) ++ { ++ case 0: ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "No Protection\n"); ++ break; ++ case 1: ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "HT non-member protection mode\n"); ++ break; ++ case 2: ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "Suggest to open protection\n"); ++ break; ++ case 3: ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "HT mixed mode\n"); ++ break; ++ } ++ ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "\tBasic MCS Rate Set = [%x][%x][%x][%x][%x]\n", pHTInfoEle->BasicMSC[0],\ ++ pHTInfoEle->BasicMSC[1], pHTInfoEle->BasicMSC[2], pHTInfoEle->BasicMSC[3], pHTInfoEle->BasicMSC[4]); ++ return; ++} ++ ++/* ++* Return: true if station in half n mode and AP supports 40 bw ++*/ ++bool IsHTHalfNmode40Bandwidth(struct ieee80211_device* ieee) ++{ ++ bool retValue = false; ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ ++ if(pHTInfo->bCurrentHTSupport == false ) // wireless is n mode ++ retValue = false; ++ else if(pHTInfo->bRegBW40MHz == false) // station supports 40 bw ++ retValue = false; ++ else if(!ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) // station in half n mode ++ retValue = false; ++ else if(((PHT_CAPABILITY_ELE)(pHTInfo->PeerHTCapBuf))->ChlWidth) // ap support 40 bw ++ retValue = true; ++ else ++ retValue = false; ++ ++ return retValue; ++} ++ ++bool IsHTHalfNmodeSGI(struct ieee80211_device* ieee, bool is40MHz) ++{ ++ bool retValue = false; ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ ++ if(pHTInfo->bCurrentHTSupport == false ) // wireless is n mode ++ retValue = false; ++ else if(!ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) // station in half n mode ++ retValue = false; ++ else if(is40MHz) // ap support 40 bw ++ { ++ if(((PHT_CAPABILITY_ELE)(pHTInfo->PeerHTCapBuf))->ShortGI40Mhz) // ap support 40 bw short GI ++ retValue = true; ++ else ++ retValue = false; ++ } ++ else ++ { ++ if(((PHT_CAPABILITY_ELE)(pHTInfo->PeerHTCapBuf))->ShortGI20Mhz) // ap support 40 bw short GI ++ retValue = true; ++ else ++ retValue = false; ++ } ++ ++ return retValue; ++} ++ ++u16 HTHalfMcsToDataRate(struct ieee80211_device* ieee, u8 nMcsRate) ++{ ++ ++ u8 is40MHz; ++ u8 isShortGI; ++ ++ is40MHz = (IsHTHalfNmode40Bandwidth(ieee))?1:0; ++ isShortGI = (IsHTHalfNmodeSGI(ieee, is40MHz))? 1:0; ++ ++ return MCS_DATA_RATE[is40MHz][isShortGI][(nMcsRate&0x7f)]; ++} ++ ++ ++u16 HTMcsToDataRate( struct ieee80211_device* ieee, u8 nMcsRate) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ ++ u8 is40MHz = (pHTInfo->bCurBW40MHz)?1:0; ++ u8 isShortGI = (pHTInfo->bCurBW40MHz)? ++ ((pHTInfo->bCurShortGI40MHz)?1:0): ++ ((pHTInfo->bCurShortGI20MHz)?1:0); ++ return MCS_DATA_RATE[is40MHz][isShortGI][(nMcsRate&0x7f)]; ++} ++ ++/******************************************************************************************************************** ++ *function: This function returns current datarate. ++ * input: struct ieee80211_device* ieee ++ * u8 nDataRate ++ * output: none ++ * return: tx rate ++ * notice: quite unsure about how to use this function //wb ++ * *****************************************************************************************************************/ ++u16 TxCountToDataRate( struct ieee80211_device* ieee, u8 nDataRate) ++{ ++ //PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ u16 CCKOFDMRate[12] = {0x02 , 0x04 , 0x0b , 0x16 , 0x0c , 0x12 , 0x18 , 0x24 , 0x30 , 0x48 , 0x60 , 0x6c}; ++ u8 is40MHz = 0; ++ u8 isShortGI = 0; ++ ++ if(nDataRate < 12) ++ { ++ return CCKOFDMRate[nDataRate]; ++ } ++ else ++ { ++ if (nDataRate >= 0x10 && nDataRate <= 0x1f)//if(nDataRate > 11 && nDataRate < 28 ) ++ { ++ is40MHz = 0; ++ isShortGI = 0; ++ ++ // nDataRate = nDataRate - 12; ++ } ++ else if(nDataRate >=0x20 && nDataRate <= 0x2f ) //(27, 44) ++ { ++ is40MHz = 1; ++ isShortGI = 0; ++ ++ //nDataRate = nDataRate - 28; ++ } ++ else if(nDataRate >= 0x30 && nDataRate <= 0x3f ) //(43, 60) ++ { ++ is40MHz = 0; ++ isShortGI = 1; ++ ++ //nDataRate = nDataRate - 44; ++ } ++ else if(nDataRate >= 0x40 && nDataRate <= 0x4f ) //(59, 76) ++ { ++ is40MHz = 1; ++ isShortGI = 1; ++ ++ //nDataRate = nDataRate - 60; ++ } ++ return MCS_DATA_RATE[is40MHz][isShortGI][nDataRate&0xf]; ++ } ++} ++ ++ ++ ++bool IsHTHalfNmodeAPs(struct ieee80211_device* ieee) ++{ ++ bool retValue = false; ++ struct ieee80211_network* net = &ieee->current_network; ++#if 0 ++ if(pMgntInfo->bHalfNMode == false) ++ retValue = false; ++ else ++#endif ++ if((memcmp(net->bssid, BELKINF5D8233V1_RALINK, 3)==0) || ++ (memcmp(net->bssid, BELKINF5D82334V3_RALINK, 3)==0) || ++ (memcmp(net->bssid, PCI_RALINK, 3)==0) || ++ (memcmp(net->bssid, EDIMAX_RALINK, 3)==0) || ++ (memcmp(net->bssid, AIRLINK_RALINK, 3)==0) || ++ (net->ralink_cap_exist)) ++ retValue = true; ++ else if((memcmp(net->bssid, UNKNOWN_BORADCOM, 3)==0) || ++ (memcmp(net->bssid, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)|| ++ (memcmp(net->bssid, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3)==0)|| ++ (memcmp(net->bssid, NETGEAR834Bv2_BROADCOM, 3)==0) || ++ (net->broadcom_cap_exist)) ++ retValue = true; ++ else if(net->bssht.bdRT2RTAggregation) ++ retValue = true; ++ else ++ retValue = false; ++ ++ return retValue; ++} ++ ++/******************************************************************************************************************** ++ *function: This function returns peer IOT. ++ * input: struct ieee80211_device* ieee ++ * output: none ++ * return: ++ * notice: ++ * *****************************************************************************************************************/ ++void HTIOTPeerDetermine(struct ieee80211_device* ieee) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ struct ieee80211_network* net = &ieee->current_network; ++ if(net->bssht.bdRT2RTAggregation) ++ pHTInfo->IOTPeer = HT_IOT_PEER_REALTEK; ++ else if(net->broadcom_cap_exist) ++ pHTInfo->IOTPeer = HT_IOT_PEER_BROADCOM; ++ else if((memcmp(net->bssid, UNKNOWN_BORADCOM, 3)==0) || ++ (memcmp(net->bssid, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)|| ++ (memcmp(net->bssid, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3)==0)|| ++ (memcmp(net->bssid, NETGEAR834Bv2_BROADCOM, 3)==0) ) ++ pHTInfo->IOTPeer = HT_IOT_PEER_BROADCOM; ++ else if((memcmp(net->bssid, BELKINF5D8233V1_RALINK, 3)==0) || ++ (memcmp(net->bssid, BELKINF5D82334V3_RALINK, 3)==0) || ++ (memcmp(net->bssid, PCI_RALINK, 3)==0) || ++ (memcmp(net->bssid, EDIMAX_RALINK, 3)==0) || ++ (memcmp(net->bssid, AIRLINK_RALINK, 3)==0) || ++ net->ralink_cap_exist) ++ pHTInfo->IOTPeer = HT_IOT_PEER_RALINK; ++ else if((net->atheros_cap_exist )|| (memcmp(net->bssid, DLINK_ATHEROS, 3) == 0)) ++ pHTInfo->IOTPeer = HT_IOT_PEER_ATHEROS; ++ else if(memcmp(net->bssid, CISCO_BROADCOM, 3)==0) ++ pHTInfo->IOTPeer = HT_IOT_PEER_CISCO; ++ else ++ pHTInfo->IOTPeer = HT_IOT_PEER_UNKNOWN; ++ ++ IEEE80211_DEBUG(IEEE80211_DL_IOT, "Joseph debug!! IOTPEER: %x\n", pHTInfo->IOTPeer); ++} ++/******************************************************************************************************************** ++ *function: Check whether driver should declare received rate up to MCS13 only since some chipset is not good ++ * at receiving MCS14~15 frame from some AP. ++ * input: struct ieee80211_device* ieee ++ * u8 * PeerMacAddr ++ * output: none ++ * return: return 1 if driver should declare MCS13 only(otherwise return 0) ++ * *****************************************************************************************************************/ ++u8 HTIOTActIsDisableMCS14(struct ieee80211_device* ieee, u8* PeerMacAddr) ++{ ++ u8 ret = 0; ++#if 0 ++ // Apply for 819u only ++#if (HAL_CODE_BASE==RTL8192 && DEV_BUS_TYPE==USB_INTERFACE) ++ if((memcmp(PeerMacAddr, UNKNOWN_BORADCOM, 3)==0) || ++ (memcmp(PeerMacAddr, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0) ++ ) ++ { ++ ret = 1; ++ } ++ ++ ++ if(pHTInfo->bCurrentRT2RTAggregation) ++ { ++ // The parameter of pHTInfo->bCurrentRT2RTAggregation must be decided previously ++ ret = 1; ++ } ++#endif ++#endif ++ return ret; ++ } ++ ++ ++/** ++* Function: HTIOTActIsDisableMCS15 ++* ++* Overview: Check whether driver should declare capability of receving MCS15 ++* ++* Input: ++* PADAPTER Adapter, ++* ++* Output: None ++* Return: true if driver should disable MCS15 ++* 2008.04.15 Emily ++*/ ++bool HTIOTActIsDisableMCS15(struct ieee80211_device* ieee) ++{ ++ bool retValue = false; ++ ++#ifdef TODO ++ // Apply for 819u only ++#if (HAL_CODE_BASE==RTL8192) ++ ++#if (DEV_BUS_TYPE == USB_INTERFACE) ++ // Alway disable MCS15 by Jerry Chang's request.by Emily, 2008.04.15 ++ retValue = true; ++#elif (DEV_BUS_TYPE == PCI_INTERFACE) ++ // Enable MCS15 if the peer is Cisco AP. by Emily, 2008.05.12 ++// if(pBssDesc->bCiscoCapExist) ++// retValue = false; ++// else ++ retValue = false; ++#endif ++#endif ++#endif ++ // Jerry Chang suggest that 8190 1x2 does not need to disable MCS15 ++ ++ return retValue; ++} ++ ++/** ++* Function: HTIOTActIsDisableMCSTwoSpatialStream ++* ++* Overview: Check whether driver should declare capability of receving All 2 ss packets ++* ++* Input: ++* PADAPTER Adapter, ++* ++* Output: None ++* Return: true if driver should disable all two spatial stream packet ++* 2008.04.21 Emily ++*/ ++bool HTIOTActIsDisableMCSTwoSpatialStream(struct ieee80211_device* ieee, u8 *PeerMacAddr) ++{ ++ bool retValue = false; ++ ++#ifdef TODO ++ // Apply for 819u only ++//#if (HAL_CODE_BASE==RTL8192) ++ ++ //This rule only apply to Belkin(Ralink) AP ++ if(IS_UNDER_11N_AES_MODE(Adapter)) ++ { ++ if((PlatformCompareMemory(PeerMacAddr, BELKINF5D8233V1_RALINK, 3)==0) || ++ (PlatformCompareMemory(PeerMacAddr, PCI_RALINK, 3)==0) || ++ (PlatformCompareMemory(PeerMacAddr, EDIMAX_RALINK, 3)==0)) ++ { ++ //Set True to disable this function. Disable by default, Emily, 2008.04.23 ++ retValue = false; ++ } ++ } ++ ++//#endif ++#endif ++ return retValue; ++} ++ ++/******************************************************************************************************************** ++ *function: Check whether driver should disable EDCA turbo mode ++ * input: struct ieee80211_device* ieee ++ * u8* PeerMacAddr ++ * output: none ++ * return: return 1 if driver should disable EDCA turbo mode(otherwise return 0) ++ * *****************************************************************************************************************/ ++u8 HTIOTActIsDisableEDCATurbo(struct ieee80211_device* ieee, u8* PeerMacAddr) ++{ ++ u8 retValue = false; // default enable EDCA Turbo mode. ++ // Set specific EDCA parameter for different AP in DM handler. ++ ++ return retValue; ++#if 0 ++ if((memcmp(PeerMacAddr, UNKNOWN_BORADCOM, 3)==0)|| ++ (memcmp(PeerMacAddr, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)|| ++ (memcmp(PeerMacAddr, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3)==0)|| ++ (memcmp(PeerMacAddr, NETGEAR834Bv2_BROADCOM, 3)==0)) ++ ++ { ++ retValue = 1; //Linksys disable EDCA turbo mode ++ } ++ ++ return retValue; ++#endif ++} ++ ++/******************************************************************************************************************** ++ *function: Check whether we need to use OFDM to sned MGNT frame for broadcom AP ++ * input: struct ieee80211_network *network //current network we live ++ * output: none ++ * return: return 1 if true ++ * *****************************************************************************************************************/ ++u8 HTIOTActIsMgntUseCCK6M(struct ieee80211_network *network) ++{ ++ u8 retValue = 0; ++ ++ // 2008/01/25 MH Judeg if we need to use OFDM to sned MGNT frame for broadcom AP. ++ // 2008/01/28 MH We must prevent that we select null bssid to link. ++ ++ if(network->broadcom_cap_exist) ++ { ++ retValue = 1; ++ } ++ ++ return retValue; ++} ++ ++u8 HTIOTActIsCCDFsync(u8* PeerMacAddr) ++{ ++ u8 retValue = 0; ++ if( (memcmp(PeerMacAddr, UNKNOWN_BORADCOM, 3)==0) || ++ (memcmp(PeerMacAddr, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0) || ++ (memcmp(PeerMacAddr, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3) ==0)) ++ { ++ retValue = 1; ++ } ++ ++ return retValue; ++} ++ ++void HTResetIOTSetting( ++ PRT_HIGH_THROUGHPUT pHTInfo ++) ++{ ++ pHTInfo->IOTAction = 0; ++ pHTInfo->IOTPeer = HT_IOT_PEER_UNKNOWN; ++} ++ ++ ++/******************************************************************************************************************** ++ *function: Construct Capablility Element in Beacon... if HTEnable is turned on ++ * input: struct ieee80211_device* ieee ++ * u8* posHTCap //pointer to store Capability Ele ++ * u8* len //store length of CE ++ * u8 IsEncrypt //whether encrypt, needed further ++ * output: none ++ * return: none ++ * notice: posHTCap can't be null and should be initialized before. ++ * *****************************************************************************************************************/ ++void HTConstructCapabilityElement(struct ieee80211_device* ieee, u8* posHTCap, u8* len, u8 IsEncrypt) ++{ ++ PRT_HIGH_THROUGHPUT pHT = ieee->pHTInfo; ++ PHT_CAPABILITY_ELE pCapELE = NULL; ++ //u8 bIsDeclareMCS13; ++ ++ if ((posHTCap == NULL) || (pHT == NULL)) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "posHTCap or pHTInfo can't be null in HTConstructCapabilityElement()\n"); ++ return; ++ } ++ memset(posHTCap, 0, *len); ++ if(pHT->ePeerHTSpecVer == HT_SPEC_VER_EWC) ++ { ++ u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33}; // For 11n EWC definition, 2007.07.17, by Emily ++ memcpy(posHTCap, EWC11NHTCap, sizeof(EWC11NHTCap)); ++ pCapELE = (PHT_CAPABILITY_ELE)&(posHTCap[4]); ++ }else ++ { ++ pCapELE = (PHT_CAPABILITY_ELE)posHTCap; ++ } ++ ++ ++ //HT capability info ++ pCapELE->AdvCoding = 0; // This feature is not supported now!! ++ if(ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) ++ { ++ pCapELE->ChlWidth = 0; ++ } ++ else ++ { ++ pCapELE->ChlWidth = (pHT->bRegBW40MHz?1:0); ++ } ++ ++// pCapELE->ChlWidth = (pHT->bRegBW40MHz?1:0); ++ pCapELE->MimoPwrSave = pHT->SelfMimoPs; ++ pCapELE->GreenField = 0; // This feature is not supported now!! ++ pCapELE->ShortGI20Mhz = 1; // We can receive Short GI!! ++ pCapELE->ShortGI40Mhz = 1; // We can receive Short GI!! ++ //DbgPrint("TX HT cap/info ele BW=%d SG20=%d SG40=%d\n\r", ++ //pCapELE->ChlWidth, pCapELE->ShortGI20Mhz, pCapELE->ShortGI40Mhz); ++ pCapELE->TxSTBC = 1; ++ pCapELE->RxSTBC = 0; ++ pCapELE->DelayBA = 0; // Do not support now!! ++ pCapELE->MaxAMSDUSize = (MAX_RECEIVE_BUFFER_SIZE>=7935)?1:0; ++ pCapELE->DssCCk = ((pHT->bRegBW40MHz)?(pHT->bRegSuppCCK?1:0):0); ++ pCapELE->PSMP = 0; // Do not support now!! ++ pCapELE->LSigTxopProtect = 0; // Do not support now!! ++ ++ ++ //MAC HT parameters info ++ // TODO: Nedd to take care of this part ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "TX HT cap/info ele BW=%d MaxAMSDUSize:%d DssCCk:%d\n", pCapELE->ChlWidth, pCapELE->MaxAMSDUSize, pCapELE->DssCCk); ++ ++ if( IsEncrypt) ++ { ++ pCapELE->MPDUDensity = 7; // 8us ++ pCapELE->MaxRxAMPDUFactor = 2; // 2 is for 32 K and 3 is 64K ++ } ++ else ++ { ++ pCapELE->MaxRxAMPDUFactor = 3; // 2 is for 32 K and 3 is 64K ++ pCapELE->MPDUDensity = 0; // no density ++ } ++ ++ //Supported MCS set ++ memcpy(pCapELE->MCS, ieee->Regdot11HTOperationalRateSet, 16); ++ if(pHT->IOTAction & HT_IOT_ACT_DISABLE_MCS15) ++ pCapELE->MCS[1] &= 0x7f; ++ ++ if(pHT->IOTAction & HT_IOT_ACT_DISABLE_MCS14) ++ pCapELE->MCS[1] &= 0xbf; ++ ++ if(pHT->IOTAction & HT_IOT_ACT_DISABLE_ALL_2SS) ++ pCapELE->MCS[1] &= 0x00; ++ ++ // 2008.06.12 ++ // For RTL819X, if pairwisekey = wep/tkip, ap is ralink, we support only MCS0~7. ++ if(ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) ++ { ++ int i; ++ for(i = 1; i< 16; i++) ++ pCapELE->MCS[i] = 0; ++ } ++ ++ //Extended HT Capability Info ++ memset(&pCapELE->ExtHTCapInfo, 0, 2); ++ ++ ++ //TXBF Capabilities ++ memset(pCapELE->TxBFCap, 0, 4); ++ ++ //Antenna Selection Capabilities ++ pCapELE->ASCap = 0; ++//add 2 to give space for element ID and len when construct frames ++ if(pHT->ePeerHTSpecVer == HT_SPEC_VER_EWC) ++ *len = 30 + 2; ++ else ++ *len = 26 + 2; ++ ++ ++ ++// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA | IEEE80211_DL_HT, posHTCap, *len -2); ++ ++ //Print each field in detail. Driver should not print out this message by default ++// HTDebugHTCapability(posHTCap, (u8*)"HTConstructCapability()"); ++ return; ++ ++} ++/******************************************************************************************************************** ++ *function: Construct Information Element in Beacon... if HTEnable is turned on ++ * input: struct ieee80211_device* ieee ++ * u8* posHTCap //pointer to store Information Ele ++ * u8* len //store len of ++ * u8 IsEncrypt //whether encrypt, needed further ++ * output: none ++ * return: none ++ * notice: posHTCap can't be null and be initialized before. only AP and IBSS sta should do this ++ * *****************************************************************************************************************/ ++void HTConstructInfoElement(struct ieee80211_device* ieee, u8* posHTInfo, u8* len, u8 IsEncrypt) ++{ ++ PRT_HIGH_THROUGHPUT pHT = ieee->pHTInfo; ++ PHT_INFORMATION_ELE pHTInfoEle = (PHT_INFORMATION_ELE)posHTInfo; ++ if ((posHTInfo == NULL) || (pHTInfoEle == NULL)) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "posHTInfo or pHTInfoEle can't be null in HTConstructInfoElement()\n"); ++ return; ++ } ++ ++ memset(posHTInfo, 0, *len); ++ if ( (ieee->iw_mode == IW_MODE_ADHOC) || (ieee->iw_mode == IW_MODE_MASTER)) //ap mode is not currently supported ++ { ++ pHTInfoEle->ControlChl = ieee->current_network.channel; ++ pHTInfoEle->ExtChlOffset = ((pHT->bRegBW40MHz == false)?HT_EXTCHNL_OFFSET_NO_EXT: ++ (ieee->current_network.channel<=6)? ++ HT_EXTCHNL_OFFSET_UPPER:HT_EXTCHNL_OFFSET_LOWER); ++ pHTInfoEle->RecommemdedTxWidth = pHT->bRegBW40MHz; ++ pHTInfoEle->RIFS = 0; ++ pHTInfoEle->PSMPAccessOnly = 0; ++ pHTInfoEle->SrvIntGranularity = 0; ++ pHTInfoEle->OptMode = pHT->CurrentOpMode; ++ pHTInfoEle->NonGFDevPresent = 0; ++ pHTInfoEle->DualBeacon = 0; ++ pHTInfoEle->SecondaryBeacon = 0; ++ pHTInfoEle->LSigTxopProtectFull = 0; ++ pHTInfoEle->PcoActive = 0; ++ pHTInfoEle->PcoPhase = 0; ++ ++ memset(pHTInfoEle->BasicMSC, 0, 16); ++ ++ ++ *len = 22 + 2; //same above ++ ++ } ++ else ++ { ++ //STA should not generate High Throughput Information Element ++ *len = 0; ++ } ++ //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA | IEEE80211_DL_HT, posHTInfo, *len - 2); ++ //HTDebugHTInfo(posHTInfo, "HTConstructInforElement"); ++ return; ++} ++ ++/* ++ * According to experiment, Realtek AP to STA (based on rtl8190) may achieve best performance ++ * if both STA and AP set limitation of aggregation size to 32K, that is, set AMPDU density to 2 ++ * (Ref: IEEE 11n specification). However, if Realtek STA associates to other AP, STA should set ++ * limitation of aggregation size to 8K, otherwise, performance of traffic stream from STA to AP ++ * will be much less than the traffic stream from AP to STA if both of the stream runs concurrently ++ * at the same time. ++ * ++ * Frame Format ++ * Element ID Length OUI Type1 Reserved ++ * 1 byte 1 byte 3 bytes 1 byte 1 byte ++ * ++ * OUI = 0x00, 0xe0, 0x4c, ++ * Type = 0x02 ++ * Reserved = 0x00 ++ * ++ * 2007.8.21 by Emily ++*/ ++/******************************************************************************************************************** ++ *function: Construct Information Element in Beacon... in RT2RT condition ++ * input: struct ieee80211_device* ieee ++ * u8* posRT2RTAgg //pointer to store Information Ele ++ * u8* len //store len ++ * output: none ++ * return: none ++ * notice: ++ * *****************************************************************************************************************/ ++void HTConstructRT2RTAggElement(struct ieee80211_device* ieee, u8* posRT2RTAgg, u8* len) ++{ ++ if (posRT2RTAgg == NULL) { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "posRT2RTAgg can't be null in HTConstructRT2RTAggElement()\n"); ++ return; ++ } ++ memset(posRT2RTAgg, 0, *len); ++ *posRT2RTAgg++ = 0x00; ++ *posRT2RTAgg++ = 0xe0; ++ *posRT2RTAgg++ = 0x4c; ++ *posRT2RTAgg++ = 0x02; ++ *posRT2RTAgg++ = 0x01; ++ *posRT2RTAgg = 0x10;//*posRT2RTAgg = 0x02; ++ ++ if(ieee->bSupportRemoteWakeUp) { ++ *posRT2RTAgg |= 0x08;//RT_HT_CAP_USE_WOW; ++ } ++ ++ *len = 6 + 2; ++ return; ++#ifdef TODO ++#if(HAL_CODE_BASE == RTL8192 && DEV_BUS_TYPE == USB_INTERFACE) ++ /* ++ //Emily. If it is required to Ask Realtek AP to send AMPDU during AES mode, enable this ++ section of code. ++ if(IS_UNDER_11N_AES_MODE(Adapter)) ++ { ++ posRT2RTAgg->Octet[5] |=RT_HT_CAP_USE_AMPDU; ++ }else ++ { ++ posRT2RTAgg->Octet[5] &= 0xfb; ++ } ++ */ ++ ++#else ++ // Do Nothing ++#endif ++ ++ posRT2RTAgg->Length = 6; ++#endif ++ ++ ++ ++ ++} ++ ++ ++/******************************************************************************************************************** ++ *function: Pick the right Rate Adaptive table to use ++ * input: struct ieee80211_device* ieee ++ * u8* pOperateMCS //A pointer to MCS rate bitmap ++ * return: always we return true ++ * notice: ++ * *****************************************************************************************************************/ ++u8 HT_PickMCSRate(struct ieee80211_device* ieee, u8* pOperateMCS) ++{ ++ u8 i; ++ if (pOperateMCS == NULL) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "pOperateMCS can't be null in HT_PickMCSRate()\n"); ++ return false; ++ } ++ ++ switch(ieee->mode) ++ { ++ case IEEE_A: ++ case IEEE_B: ++ case IEEE_G: ++ //legacy rate routine handled at selectedrate ++ ++ //no MCS rate ++ for(i=0;i<=15;i++){ ++ pOperateMCS[i] = 0; ++ } ++ break; ++ ++ case IEEE_N_24G: //assume CCK rate ok ++ case IEEE_N_5G: ++ // Legacy part we only use 6, 5.5,2,1 for N_24G and 6 for N_5G. ++ // Legacy part shall be handled at SelectRateSet(). ++ ++ //HT part ++ // TODO: may be different if we have different number of antenna ++ pOperateMCS[0] &=RATE_ADPT_1SS_MASK; //support MCS 0~7 ++ pOperateMCS[1] &=RATE_ADPT_2SS_MASK; ++ pOperateMCS[3] &=RATE_ADPT_MCS32_MASK; ++ break; ++ ++ //should never reach here ++ default: ++ ++ break; ++ ++ } ++ ++ return true; ++} ++ ++/* ++* Description: ++* This function will get the highest speed rate in input MCS set. ++* ++* /param Adapter Pionter to Adapter entity ++* pMCSRateSet Pointer to MCS rate bitmap ++* pMCSFilter Pointer to MCS rate filter ++* ++* /return Highest MCS rate included in pMCSRateSet and filtered by pMCSFilter. ++* ++*/ ++/******************************************************************************************************************** ++ *function: This function will get the highest speed rate in input MCS set. ++ * input: struct ieee80211_device* ieee ++ * u8* pMCSRateSet //Pointer to MCS rate bitmap ++ * u8* pMCSFilter //Pointer to MCS rate filter ++ * return: Highest MCS rate included in pMCSRateSet and filtered by pMCSFilter ++ * notice: ++ * *****************************************************************************************************************/ ++u8 HTGetHighestMCSRate(struct ieee80211_device* ieee, u8* pMCSRateSet, u8* pMCSFilter) ++{ ++ u8 i, j; ++ u8 bitMap; ++ u8 mcsRate = 0; ++ u8 availableMcsRate[16]; ++ if (pMCSRateSet == NULL || pMCSFilter == NULL) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "pMCSRateSet or pMCSFilter can't be null in HTGetHighestMCSRate()\n"); ++ return false; ++ } ++ for(i=0; i<16; i++) ++ availableMcsRate[i] = pMCSRateSet[i] & pMCSFilter[i]; ++ ++ for(i = 0; i < 16; i++) ++ { ++ if(availableMcsRate[i] != 0) ++ break; ++ } ++ if(i == 16) ++ return false; ++ ++ for(i = 0; i < 16; i++) ++ { ++ if(availableMcsRate[i] != 0) ++ { ++ bitMap = availableMcsRate[i]; ++ for(j = 0; j < 8; j++) ++ { ++ if((bitMap%2) != 0) ++ { ++ if(HTMcsToDataRate(ieee, (8*i+j)) > HTMcsToDataRate(ieee, mcsRate)) ++ mcsRate = (8*i+j); ++ } ++ bitMap = bitMap>>1; ++ } ++ } ++ } ++ return (mcsRate|0x80); ++} ++ ++ ++ ++/* ++** ++**1.Filter our operation rate set with AP's rate set ++**2.shall reference channel bandwidth, STBC, Antenna number ++**3.generate rate adative table for firmware ++**David 20060906 ++** ++** \pHTSupportedCap: the connected STA's supported rate Capability element ++*/ ++u8 HTFilterMCSRate( struct ieee80211_device* ieee, u8* pSupportMCS, u8* pOperateMCS) ++{ ++ ++ u8 i=0; ++ ++ // filter out operational rate set not supported by AP, the lenth of it is 16 ++ for(i=0;i<=15;i++){ ++ pOperateMCS[i] = ieee->Regdot11HTOperationalRateSet[i]&pSupportMCS[i]; ++ } ++ ++ ++ // TODO: adjust our operational rate set according to our channel bandwidth, STBC and Antenna number ++ ++ // TODO: fill suggested rate adaptive rate index and give firmware info using Tx command packet ++ // we also shall suggested the first start rate set according to our singal strength ++ HT_PickMCSRate(ieee, pOperateMCS); ++ ++ // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7. ++ if(ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) ++ pOperateMCS[1] = 0; ++ ++ // ++ // For RTL819X, we support only MCS0~15. ++ // And also, we do not know how to use MCS32 now. ++ // ++ for(i=2; i<=15; i++) ++ pOperateMCS[i] = 0; ++ ++ return true; ++} ++void HTSetConnectBwMode(struct ieee80211_device* ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); ++#if 0 ++//I need move this function to other places, such as rx? ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void HTOnAssocRsp_wq(struct work_struct *work) ++{ ++ struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, ht_onAssRsp); ++#else ++void HTOnAssocRsp_wq(struct ieee80211_device *ieee) ++{ ++#endif ++#endif ++void HTOnAssocRsp(struct ieee80211_device *ieee) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ PHT_CAPABILITY_ELE pPeerHTCap = NULL; ++ PHT_INFORMATION_ELE pPeerHTInfo = NULL; ++ u16 nMaxAMSDUSize = 0; ++ u8* pMcsFilter = NULL; ++ ++ static u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33}; // For 11n EWC definition, 2007.07.17, by Emily ++ static u8 EWC11NHTInfo[] = {0x00, 0x90, 0x4c, 0x34}; // For 11n EWC definition, 2007.07.17, by Emily ++ ++ if( pHTInfo->bCurrentHTSupport == false ) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "<=== HTOnAssocRsp(): HT_DISABLE\n"); ++ return; ++ } ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "===> HTOnAssocRsp_wq(): HT_ENABLE\n"); ++// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, pHTInfo->PeerHTCapBuf, sizeof(HT_CAPABILITY_ELE)); ++// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, pHTInfo->PeerHTInfoBuf, sizeof(HT_INFORMATION_ELE)); ++ ++// HTDebugHTCapability(pHTInfo->PeerHTCapBuf,"HTOnAssocRsp_wq"); ++// HTDebugHTInfo(pHTInfo->PeerHTInfoBuf,"HTOnAssocRsp_wq"); ++ // ++ if(!memcmp(pHTInfo->PeerHTCapBuf,EWC11NHTCap, sizeof(EWC11NHTCap))) ++ pPeerHTCap = (PHT_CAPABILITY_ELE)(&pHTInfo->PeerHTCapBuf[4]); ++ else ++ pPeerHTCap = (PHT_CAPABILITY_ELE)(pHTInfo->PeerHTCapBuf); ++ ++ if(!memcmp(pHTInfo->PeerHTInfoBuf, EWC11NHTInfo, sizeof(EWC11NHTInfo))) ++ pPeerHTInfo = (PHT_INFORMATION_ELE)(&pHTInfo->PeerHTInfoBuf[4]); ++ else ++ pPeerHTInfo = (PHT_INFORMATION_ELE)(pHTInfo->PeerHTInfoBuf); ++ ++ ++ //////////////////////////////////////////////////////// ++ // Configurations: ++ //////////////////////////////////////////////////////// ++ IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_HT, pPeerHTCap, sizeof(HT_CAPABILITY_ELE)); ++// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_HT, pPeerHTInfo, sizeof(HT_INFORMATION_ELE)); ++ // Config Supported Channel Width setting ++ // ++ HTSetConnectBwMode(ieee, (HT_CHANNEL_WIDTH)(pPeerHTCap->ChlWidth), (HT_EXTCHNL_OFFSET)(pPeerHTInfo->ExtChlOffset)); ++ ++// if(pHTInfo->bCurBW40MHz == true) ++ pHTInfo->bCurTxBW40MHz = ((pPeerHTInfo->RecommemdedTxWidth == 1)?true:false); ++ ++ // ++ // Update short GI/ long GI setting ++ // ++ // TODO: ++ pHTInfo->bCurShortGI20MHz= ++ ((pHTInfo->bRegShortGI20MHz)?((pPeerHTCap->ShortGI20Mhz==1)?true:false):false); ++ pHTInfo->bCurShortGI40MHz= ++ ((pHTInfo->bRegShortGI40MHz)?((pPeerHTCap->ShortGI40Mhz==1)?true:false):false); ++ ++ // ++ // Config TX STBC setting ++ // ++ // TODO: ++ ++ // ++ // Config DSSS/CCK mode in 40MHz mode ++ // ++ // TODO: ++ pHTInfo->bCurSuppCCK = ++ ((pHTInfo->bRegSuppCCK)?((pPeerHTCap->DssCCk==1)?true:false):false); ++ ++ ++ // ++ // Config and configure A-MSDU setting ++ // ++ pHTInfo->bCurrent_AMSDU_Support = pHTInfo->bAMSDU_Support; ++ ++ nMaxAMSDUSize = (pPeerHTCap->MaxAMSDUSize==0)?3839:7935; ++ ++ if(pHTInfo->nAMSDU_MaxSize > nMaxAMSDUSize ) ++ pHTInfo->nCurrent_AMSDU_MaxSize = nMaxAMSDUSize; ++ else ++ pHTInfo->nCurrent_AMSDU_MaxSize = pHTInfo->nAMSDU_MaxSize; ++ ++ ++ // ++ // Config A-MPDU setting ++ // ++ pHTInfo->bCurrentAMPDUEnable = pHTInfo->bAMPDUEnable; ++ ++ // <1> Decide AMPDU Factor ++ ++ // By Emily ++ if(!pHTInfo->bRegRT2RTAggregation) ++ { ++ // Decide AMPDU Factor according to protocol handshake ++ if(pHTInfo->AMPDU_Factor > pPeerHTCap->MaxRxAMPDUFactor) ++ pHTInfo->CurrentAMPDUFactor = pPeerHTCap->MaxRxAMPDUFactor; ++ else ++ pHTInfo->CurrentAMPDUFactor = pHTInfo->AMPDU_Factor; ++ ++ }else ++ { ++ // Set MPDU density to 2 to Realtek AP, and set it to 0 for others ++ // Replace MPDU factor declared in original association response frame format. 2007.08.20 by Emily ++#if 0 ++ osTmp= PacketGetElement( asocpdu, EID_Vendor, OUI_SUB_REALTEK_AGG, OUI_SUBTYPE_DONT_CARE); ++ if(osTmp.Length >= 5) //00:e0:4c:02:00 ++#endif ++ if (ieee->current_network.bssht.bdRT2RTAggregation) ++ { ++ if( ieee->pairwise_key_type != KEY_TYPE_NA) ++ // Realtek may set 32k in security mode and 64k for others ++ pHTInfo->CurrentAMPDUFactor = pPeerHTCap->MaxRxAMPDUFactor; ++ else ++ pHTInfo->CurrentAMPDUFactor = HT_AGG_SIZE_64K; ++ }else ++ { ++ if(pPeerHTCap->MaxRxAMPDUFactor < HT_AGG_SIZE_32K) ++ pHTInfo->CurrentAMPDUFactor = pPeerHTCap->MaxRxAMPDUFactor; ++ else ++ pHTInfo->CurrentAMPDUFactor = HT_AGG_SIZE_32K; ++ } ++ } ++ ++ // <2> Set AMPDU Minimum MPDU Start Spacing ++ // 802.11n 3.0 section 9.7d.3 ++#if 1 ++ if(pHTInfo->MPDU_Density > pPeerHTCap->MPDUDensity) ++ pHTInfo->CurrentMPDUDensity = pHTInfo->MPDU_Density; ++ else ++ pHTInfo->CurrentMPDUDensity = pPeerHTCap->MPDUDensity; ++ if(ieee->pairwise_key_type != KEY_TYPE_NA ) ++ pHTInfo->CurrentMPDUDensity = 7; // 8us ++#else ++ if(pHTInfo->MPDU_Density > pPeerHTCap->MPDUDensity) ++ pHTInfo->CurrentMPDUDensity = pHTInfo->MPDU_Density; ++ else ++ pHTInfo->CurrentMPDUDensity = pPeerHTCap->MPDUDensity; ++#endif ++ // Force TX AMSDU ++ ++ // Lanhsin: mark for tmp to avoid deauth by ap from s3 ++ //if(memcmp(pMgntInfo->Bssid, NETGEAR834Bv2_BROADCOM, 3)==0) ++ if(0) ++ { ++ ++ pHTInfo->bCurrentAMPDUEnable = false; ++ pHTInfo->ForcedAMSDUMode = HT_AGG_FORCE_ENABLE; ++ pHTInfo->ForcedAMSDUMaxSize = 7935; ++ ++ pHTInfo->IOTAction |= HT_IOT_ACT_TX_USE_AMSDU_8K; ++ } ++ ++ // Rx Reorder Setting ++ pHTInfo->bCurRxReorderEnable = pHTInfo->bRegRxReorderEnable; ++ ++ // ++ // Filter out unsupported HT rate for this AP ++ // Update RATR table ++ // This is only for 8190 ,8192 or later product which using firmware to handle rate adaptive mechanism. ++ // ++ ++ // Handle Ralink AP bad MCS rate set condition. Joseph. ++ // This fix the bug of Ralink AP. This may be removed in the future. ++ if(pPeerHTCap->MCS[0] == 0) ++ pPeerHTCap->MCS[0] = 0xff; ++ ++ HTFilterMCSRate(ieee, pPeerHTCap->MCS, ieee->dot11HTOperationalRateSet); ++ ++ // ++ // Config MIMO Power Save setting ++ // ++ pHTInfo->PeerMimoPs = pPeerHTCap->MimoPwrSave; ++ if(pHTInfo->PeerMimoPs == MIMO_PS_STATIC) ++ pMcsFilter = MCS_FILTER_1SS; ++ else ++ pMcsFilter = MCS_FILTER_ALL; ++ //WB add for MCS8 bug ++// pMcsFilter = MCS_FILTER_1SS; ++ ieee->HTHighestOperaRate = HTGetHighestMCSRate(ieee, ieee->dot11HTOperationalRateSet, pMcsFilter); ++ ieee->HTCurrentOperaRate = ieee->HTHighestOperaRate; ++ ++ // ++ // Config current operation mode. ++ // ++ pHTInfo->CurrentOpMode = pPeerHTInfo->OptMode; ++ ++ ++ ++} ++ ++void HTSetConnectBwModeCallback(struct ieee80211_device* ieee); ++/******************************************************************************************************************** ++ *function: initialize HT info(struct PRT_HIGH_THROUGHPUT) ++ * input: struct ieee80211_device* ieee ++ * output: none ++ * return: none ++ * notice: This function is called when * (1) MPInitialization Phase * (2) Receiving of Deauthentication from AP ++********************************************************************************************************************/ ++// TODO: Should this funciton be called when receiving of Disassociation? ++void HTInitializeHTInfo(struct ieee80211_device* ieee) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ ++ // ++ // These parameters will be reset when receiving deauthentication packet ++ // ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "===========>%s()\n", __FUNCTION__); ++ pHTInfo->bCurrentHTSupport = false; ++ ++ // 40MHz channel support ++ pHTInfo->bCurBW40MHz = false; ++ pHTInfo->bCurTxBW40MHz = false; ++ ++ // Short GI support ++ pHTInfo->bCurShortGI20MHz = false; ++ pHTInfo->bCurShortGI40MHz = false; ++ pHTInfo->bForcedShortGI = false; ++ ++ // CCK rate support ++ // This flag is set to true to support CCK rate by default. ++ // It will be affected by "pHTInfo->bRegSuppCCK" and AP capabilities only when associate to ++ // 11N BSS. ++ pHTInfo->bCurSuppCCK = true; ++ ++ // AMSDU related ++ pHTInfo->bCurrent_AMSDU_Support = false; ++ pHTInfo->nCurrent_AMSDU_MaxSize = pHTInfo->nAMSDU_MaxSize; ++ ++ // AMPUD related ++ pHTInfo->CurrentMPDUDensity = pHTInfo->MPDU_Density; ++ pHTInfo->CurrentAMPDUFactor = pHTInfo->AMPDU_Factor; ++ ++ ++ ++ // Initialize all of the parameters related to 11n ++ memset((void*)(&(pHTInfo->SelfHTCap)), 0, sizeof(pHTInfo->SelfHTCap)); ++ memset((void*)(&(pHTInfo->SelfHTInfo)), 0, sizeof(pHTInfo->SelfHTInfo)); ++ memset((void*)(&(pHTInfo->PeerHTCapBuf)), 0, sizeof(pHTInfo->PeerHTCapBuf)); ++ memset((void*)(&(pHTInfo->PeerHTInfoBuf)), 0, sizeof(pHTInfo->PeerHTInfoBuf)); ++ ++ pHTInfo->bSwBwInProgress = false; ++ pHTInfo->ChnlOp = CHNLOP_NONE; ++ ++ // Set default IEEE spec for Draft N ++ pHTInfo->ePeerHTSpecVer = HT_SPEC_VER_IEEE; ++ ++ // Realtek proprietary aggregation mode ++ pHTInfo->bCurrentRT2RTAggregation = false; ++ pHTInfo->bCurrentRT2RTLongSlotTime = false; ++ pHTInfo->IOTPeer = 0; ++ pHTInfo->IOTAction = 0; ++ ++ //MCS rate initialized here ++ { ++ u8* RegHTSuppRateSets = &(ieee->RegHTSuppRateSet[0]); ++ RegHTSuppRateSets[0] = 0xFF; //support MCS 0~7 ++ RegHTSuppRateSets[1] = 0xFF; //support MCS 8~15 ++ RegHTSuppRateSets[4] = 0x01; //support MCS 32 ++ } ++} ++/******************************************************************************************************************** ++ *function: initialize Bss HT structure(struct PBSS_HT) ++ * input: PBSS_HT pBssHT //to be initialized ++ * output: none ++ * return: none ++ * notice: This function is called when initialize network structure ++********************************************************************************************************************/ ++void HTInitializeBssDesc(PBSS_HT pBssHT) ++{ ++ ++ pBssHT->bdSupportHT = false; ++ memset(pBssHT->bdHTCapBuf, 0, sizeof(pBssHT->bdHTCapBuf)); ++ pBssHT->bdHTCapLen = 0; ++ memset(pBssHT->bdHTInfoBuf, 0, sizeof(pBssHT->bdHTInfoBuf)); ++ pBssHT->bdHTInfoLen = 0; ++ ++ pBssHT->bdHTSpecVer= HT_SPEC_VER_IEEE; ++ ++ pBssHT->bdRT2RTAggregation = false; ++ pBssHT->bdRT2RTLongSlotTime = false; ++} ++#if 0 ++//below function has merged into ieee80211_network_init() in ieee80211_rx.c ++void ++HTParsingHTCapElement( ++ IN PADAPTER Adapter, ++ IN OCTET_STRING HTCapIE, ++ OUT PRT_WLAN_BSS pBssDesc ++) ++{ ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ ++ if( HTCapIE.Length > sizeof(pBssDesc->BssHT.bdHTCapBuf) ) ++ { ++ RT_TRACE( COMP_HT, DBG_LOUD, ("HTParsingHTCapElement(): HT Capability Element length is too long!\n") ); ++ return; ++ } ++ ++ // TODO: Check the correctness of HT Cap ++ //Print each field in detail. Driver should not print out this message by default ++ if(!pMgntInfo->mActingAsAp && !pMgntInfo->mAssoc) ++ HTDebugHTCapability(DBG_TRACE, Adapter, &HTCapIE, (pu8)"HTParsingHTCapElement()"); ++ ++ HTCapIE.Length = HTCapIE.Length > sizeof(pBssDesc->BssHT.bdHTCapBuf)?\ ++ sizeof(pBssDesc->BssHT.bdHTCapBuf):HTCapIE.Length; //prevent from overflow ++ ++ CopyMem(pBssDesc->BssHT.bdHTCapBuf, HTCapIE.Octet, HTCapIE.Length); ++ pBssDesc->BssHT.bdHTCapLen = HTCapIE.Length; ++ ++} ++ ++ ++void ++HTParsingHTInfoElement( ++ PADAPTER Adapter, ++ OCTET_STRING HTInfoIE, ++ PRT_WLAN_BSS pBssDesc ++) ++{ ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ ++ if( HTInfoIE.Length > sizeof(pBssDesc->BssHT.bdHTInfoBuf)) ++ { ++ RT_TRACE( COMP_HT, DBG_LOUD, ("HTParsingHTInfoElement(): HT Information Element length is too long!\n") ); ++ return; ++ } ++ ++ // TODO: Check the correctness of HT Info ++ //Print each field in detail. Driver should not print out this message by default ++ if(!pMgntInfo->mActingAsAp && !pMgntInfo->mAssoc) ++ HTDebugHTInfo(DBG_TRACE, Adapter, &HTInfoIE, (pu8)"HTParsingHTInfoElement()"); ++ ++ HTInfoIE.Length = HTInfoIE.Length > sizeof(pBssDesc->BssHT.bdHTInfoBuf)?\ ++ sizeof(pBssDesc->BssHT.bdHTInfoBuf):HTInfoIE.Length; //prevent from overflow ++ ++ CopyMem( pBssDesc->BssHT.bdHTInfoBuf, HTInfoIE.Octet, HTInfoIE.Length); ++ pBssDesc->BssHT.bdHTInfoLen = HTInfoIE.Length; ++} ++ ++/* ++ * Get HT related information from beacon and save it in BssDesc ++ * ++ * (1) Parse HTCap, and HTInfo, and record whether it is 11n AP ++ * (2) If peer is HT, but not WMM, call QosSetLegacyWMMParamWithHT() ++ * (3) Check whether peer is Realtek AP (for Realtek proprietary aggregation mode). ++ * Input: ++ * PADAPTER Adapter ++ * ++ * Output: ++ * PRT_TCB BssDesc ++ * ++*/ ++void HTGetValueFromBeaconOrProbeRsp( ++ PADAPTER Adapter, ++ POCTET_STRING pSRCmmpdu, ++ PRT_WLAN_BSS bssDesc ++) ++{ ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo); ++ OCTET_STRING HTCapIE, HTInfoIE, HTRealtekAgg, mmpdu; ++ OCTET_STRING BroadcomElement, CiscoElement; ++ ++ mmpdu.Octet = pSRCmmpdu->Octet; ++ mmpdu.Length = pSRCmmpdu->Length; ++ ++ //2Note: ++ // Mark for IOT testing using Linksys WRT350N, This AP does not contain WMM IE when ++ // it is configured at pure-N mode. ++ // if(bssDesc->BssQos.bdQoSMode & QOS_WMM) ++ // ++ ++ HTInitializeBssDesc (&bssDesc->BssHT); ++ ++ //2<1> Parse HTCap, and HTInfo ++ // Get HT Capability IE: (1) Get IEEE Draft N IE or (2) Get EWC IE ++ HTCapIE = PacketGetElement(mmpdu, EID_HTCapability, OUI_SUB_DONT_CARE, OUI_SUBTYPE_DONT_CARE); ++ if(HTCapIE.Length == 0) ++ { ++ HTCapIE = PacketGetElement(mmpdu, EID_Vendor, OUI_SUB_11N_EWC_HT_CAP, OUI_SUBTYPE_DONT_CARE); ++ if(HTCapIE.Length != 0) ++ bssDesc->BssHT.bdHTSpecVer= HT_SPEC_VER_EWC; ++ } ++ if(HTCapIE.Length != 0) ++ HTParsingHTCapElement(Adapter, HTCapIE, bssDesc); ++ ++ // Get HT Information IE: (1) Get IEEE Draft N IE or (2) Get EWC IE ++ HTInfoIE = PacketGetElement(mmpdu, EID_HTInfo, OUI_SUB_DONT_CARE, OUI_SUBTYPE_DONT_CARE); ++ if(HTInfoIE.Length == 0) ++ { ++ HTInfoIE = PacketGetElement(mmpdu, EID_Vendor, OUI_SUB_11N_EWC_HT_INFO, OUI_SUBTYPE_DONT_CARE); ++ if(HTInfoIE.Length != 0) ++ bssDesc->BssHT.bdHTSpecVer = HT_SPEC_VER_EWC; ++ } ++ if(HTInfoIE.Length != 0) ++ HTParsingHTInfoElement(Adapter, HTInfoIE, bssDesc); ++ ++ //2<2>If peer is HT, but not WMM, call QosSetLegacyWMMParamWithHT() ++ if(HTCapIE.Length != 0) ++ { ++ bssDesc->BssHT.bdSupportHT = true; ++ if(bssDesc->BssQos.bdQoSMode == QOS_DISABLE) ++ QosSetLegacyWMMParamWithHT(Adapter, bssDesc); ++ } ++ else ++ { ++ bssDesc->BssHT.bdSupportHT = false; ++ } ++ ++ //2<3>Check whether the peer is Realtek AP/STA ++ if(pHTInfo->bRegRT2RTAggregation) ++ { ++ if(bssDesc->BssHT.bdSupportHT) ++ { ++ HTRealtekAgg = PacketGetElement(mmpdu, EID_Vendor, OUI_SUB_REALTEK_AGG, OUI_SUBTYPE_DONT_CARE); ++ if(HTRealtekAgg.Length >=5 ) ++ { ++ bssDesc->BssHT.bdRT2RTAggregation = true; ++ ++ if((HTRealtekAgg.Octet[4]==1) && (HTRealtekAgg.Octet[5] & 0x02)) ++ bssDesc->BssHT.bdRT2RTLongSlotTime = true; ++ } ++ } ++ } ++ ++ // ++ // 2008/01/25 MH Get Broadcom AP IE for manamgent frame CCK rate problem. ++ // AP can not receive CCK managemtn from from 92E. ++ // ++ ++ // Initialize every new bss broadcom cap exist as false.. ++ bssDesc->bBroadcomCapExist= false; ++ ++ if(HTCapIE.Length != 0 || HTInfoIE.Length != 0) ++ { ++ u4Byte Length = 0; ++ ++ FillOctetString(BroadcomElement, NULL, 0); ++ ++ BroadcomElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_BROADCOM_IE_1, OUI_SUBTYPE_DONT_CARE); ++ Length += BroadcomElement.Length; ++ BroadcomElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_BROADCOM_IE_2, OUI_SUBTYPE_DONT_CARE); ++ Length += BroadcomElement.Length; ++ BroadcomElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_BROADCOM_IE_3, OUI_SUBTYPE_DONT_CARE); ++ Length += BroadcomElement.Length; ++ ++ if(Length > 0) ++ bssDesc->bBroadcomCapExist = true; ++ } ++ ++ ++ // For Cisco IOT issue ++ CiscoElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_CISCO_IE, OUI_SUBTYPE_DONT_CARE); ++ if(CiscoElement.Length != 0){ // 3: 0x00, 0x40, 0x96 .... ++ bssDesc->bCiscoCapExist = true; ++ }else{ ++ bssDesc->bCiscoCapExist = false; ++ } ++} ++ ++ ++#endif ++/******************************************************************************************************************** ++ *function: initialize Bss HT structure(struct PBSS_HT) ++ * input: struct ieee80211_device *ieee ++ * struct ieee80211_network *pNetwork //usually current network we are live in ++ * output: none ++ * return: none ++ * notice: This function should ONLY be called before association ++********************************************************************************************************************/ ++void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++// u16 nMaxAMSDUSize; ++// PHT_CAPABILITY_ELE pPeerHTCap = (PHT_CAPABILITY_ELE)pNetwork->bssht.bdHTCapBuf; ++// PHT_INFORMATION_ELE pPeerHTInfo = (PHT_INFORMATION_ELE)pNetwork->bssht.bdHTInfoBuf; ++// u8* pMcsFilter; ++ u8 bIOTAction = 0; ++ ++ // ++ // Save Peer Setting before Association ++ // ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "==============>%s()\n", __FUNCTION__); ++ /*unmark bEnableHT flag here is the same reason why unmarked in function ieee80211_softmac_new_net. WB 2008.09.10*/ ++// if( pHTInfo->bEnableHT && pNetwork->bssht.bdSupportHT) ++ if (pNetwork->bssht.bdSupportHT) ++ { ++ pHTInfo->bCurrentHTSupport = true; ++ pHTInfo->ePeerHTSpecVer = pNetwork->bssht.bdHTSpecVer; ++ ++ // Save HTCap and HTInfo information Element ++ if(pNetwork->bssht.bdHTCapLen > 0 && pNetwork->bssht.bdHTCapLen <= sizeof(pHTInfo->PeerHTCapBuf)) ++ memcpy(pHTInfo->PeerHTCapBuf, pNetwork->bssht.bdHTCapBuf, pNetwork->bssht.bdHTCapLen); ++ ++ if(pNetwork->bssht.bdHTInfoLen > 0 && pNetwork->bssht.bdHTInfoLen <= sizeof(pHTInfo->PeerHTInfoBuf)) ++ memcpy(pHTInfo->PeerHTInfoBuf, pNetwork->bssht.bdHTInfoBuf, pNetwork->bssht.bdHTInfoLen); ++ ++ // Check whether RT to RT aggregation mode is enabled ++ if(pHTInfo->bRegRT2RTAggregation) ++ { ++ pHTInfo->bCurrentRT2RTAggregation = pNetwork->bssht.bdRT2RTAggregation; ++ pHTInfo->bCurrentRT2RTLongSlotTime = pNetwork->bssht.bdRT2RTLongSlotTime; ++ } ++ else ++ { ++ pHTInfo->bCurrentRT2RTAggregation = false; ++ pHTInfo->bCurrentRT2RTLongSlotTime = false; ++ } ++ ++ // Determine the IOT Peer Vendor. ++ HTIOTPeerDetermine(ieee); ++ ++ // Decide IOT Action ++ // Must be called after the parameter of pHTInfo->bCurrentRT2RTAggregation is decided ++ pHTInfo->IOTAction = 0; ++ bIOTAction = HTIOTActIsDisableMCS14(ieee, pNetwork->bssid); ++ if(bIOTAction) ++ pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_MCS14; ++ ++ bIOTAction = HTIOTActIsDisableMCS15(ieee); ++ if(bIOTAction) ++ pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_MCS15; ++ ++ bIOTAction = HTIOTActIsDisableMCSTwoSpatialStream(ieee, pNetwork->bssid); ++ if(bIOTAction) ++ pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_ALL_2SS; ++ ++ ++ bIOTAction = HTIOTActIsDisableEDCATurbo(ieee, pNetwork->bssid); ++ if(bIOTAction) ++ pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_EDCA_TURBO; ++ ++ bIOTAction = HTIOTActIsMgntUseCCK6M(pNetwork); ++ if(bIOTAction) ++ pHTInfo->IOTAction |= HT_IOT_ACT_MGNT_USE_CCK_6M; ++ ++ bIOTAction = HTIOTActIsCCDFsync(pNetwork->bssid); ++ if(bIOTAction) ++ pHTInfo->IOTAction |= HT_IOT_ACT_CDD_FSYNC; ++ ++ ++ } ++ else ++ { ++ pHTInfo->bCurrentHTSupport = false; ++ pHTInfo->bCurrentRT2RTAggregation = false; ++ pHTInfo->bCurrentRT2RTLongSlotTime = false; ++ ++ pHTInfo->IOTAction = 0; ++ } ++ ++} ++ ++void HTUpdateSelfAndPeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++// PHT_CAPABILITY_ELE pPeerHTCap = (PHT_CAPABILITY_ELE)pNetwork->bssht.bdHTCapBuf; ++ PHT_INFORMATION_ELE pPeerHTInfo = (PHT_INFORMATION_ELE)pNetwork->bssht.bdHTInfoBuf; ++ ++ if(pHTInfo->bCurrentHTSupport) ++ { ++ // ++ // Config current operation mode. ++ // ++ if(pNetwork->bssht.bdHTInfoLen != 0) ++ pHTInfo->CurrentOpMode = pPeerHTInfo->OptMode; ++ ++ // ++ // ++ // ++ } ++} ++ ++void HTUseDefaultSetting(struct ieee80211_device* ieee) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++// u8 regBwOpMode; ++ ++ if(pHTInfo->bEnableHT) ++ { ++ pHTInfo->bCurrentHTSupport = true; ++ ++ pHTInfo->bCurSuppCCK = pHTInfo->bRegSuppCCK; ++ ++ pHTInfo->bCurBW40MHz = pHTInfo->bRegBW40MHz; ++ ++ pHTInfo->bCurShortGI20MHz= pHTInfo->bRegShortGI20MHz; ++ ++ pHTInfo->bCurShortGI40MHz= pHTInfo->bRegShortGI40MHz; ++ ++ pHTInfo->bCurrent_AMSDU_Support = pHTInfo->bAMSDU_Support; ++ ++ pHTInfo->nCurrent_AMSDU_MaxSize = pHTInfo->nAMSDU_MaxSize; ++ ++ pHTInfo->bCurrentAMPDUEnable = pHTInfo->bAMPDUEnable; ++ ++ pHTInfo->CurrentAMPDUFactor = pHTInfo->AMPDU_Factor; ++ ++ pHTInfo->CurrentMPDUDensity = pHTInfo->CurrentMPDUDensity; ++ ++ // Set BWOpMode register ++ ++ //update RATR index0 ++ HTFilterMCSRate(ieee, ieee->Regdot11HTOperationalRateSet, ieee->dot11HTOperationalRateSet); ++ //function below is not implemented at all. WB ++#ifdef TODO ++ Adapter->HalFunc.InitHalRATRTableHandler( Adapter, &pMgntInfo->dot11OperationalRateSet, pMgntInfo->dot11HTOperationalRateSet); ++#endif ++ ieee->HTHighestOperaRate = HTGetHighestMCSRate(ieee, ieee->dot11HTOperationalRateSet, MCS_FILTER_ALL); ++ ieee->HTCurrentOperaRate = ieee->HTHighestOperaRate; ++ ++ } ++ else ++ { ++ pHTInfo->bCurrentHTSupport = false; ++ } ++ return; ++} ++/******************************************************************************************************************** ++ *function: check whether HT control field exists ++ * input: struct ieee80211_device *ieee ++ * u8* pFrame //coming skb->data ++ * output: none ++ * return: return true if HT control field exists(false otherwise) ++ * notice: ++********************************************************************************************************************/ ++u8 HTCCheck(struct ieee80211_device* ieee, u8* pFrame) ++{ ++ if(ieee->pHTInfo->bCurrentHTSupport) ++ { ++ if( (IsQoSDataFrame(pFrame) && Frame_Order(pFrame)) == 1) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "HT CONTROL FILED EXIST!!\n"); ++ return true; ++ } ++ } ++ return false; ++} ++ ++// ++// This function set bandwidth mode in protocol layer. ++// ++void HTSetConnectBwMode(struct ieee80211_device* ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++// u32 flags = 0; ++ ++ if(pHTInfo->bRegBW40MHz == false) ++ return; ++ ++ ++ ++ // To reduce dummy operation ++// if((pHTInfo->bCurBW40MHz==false && Bandwidth==HT_CHANNEL_WIDTH_20) || ++// (pHTInfo->bCurBW40MHz==true && Bandwidth==HT_CHANNEL_WIDTH_20_40 && Offset==pHTInfo->CurSTAExtChnlOffset)) ++// return; ++ ++// spin_lock_irqsave(&(ieee->bw_spinlock), flags); ++ if(pHTInfo->bSwBwInProgress) { ++// spin_unlock_irqrestore(&(ieee->bw_spinlock), flags); ++ return; ++ } ++ //if in half N mode, set to 20M bandwidth please 09.08.2008 WB. ++ if(Bandwidth==HT_CHANNEL_WIDTH_20_40 && (!ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev))) ++ { ++ // Handle Illegal extention channel offset!! ++ if(ieee->current_network.channel<2 && Offset==HT_EXTCHNL_OFFSET_LOWER) ++ Offset = HT_EXTCHNL_OFFSET_NO_EXT; ++ if(Offset==HT_EXTCHNL_OFFSET_UPPER || Offset==HT_EXTCHNL_OFFSET_LOWER) { ++ pHTInfo->bCurBW40MHz = true; ++ pHTInfo->CurSTAExtChnlOffset = Offset; ++ } else { ++ pHTInfo->bCurBW40MHz = false; ++ pHTInfo->CurSTAExtChnlOffset = HT_EXTCHNL_OFFSET_NO_EXT; ++ } ++ } else { ++ pHTInfo->bCurBW40MHz = false; ++ pHTInfo->CurSTAExtChnlOffset = HT_EXTCHNL_OFFSET_NO_EXT; ++ } ++ ++ pHTInfo->bSwBwInProgress = true; ++ ++ // TODO: 2007.7.13 by Emily Wait 2000ms in order to garantee that switching ++ // bandwidth is executed after scan is finished. It is a temporal solution ++ // because software should ganrantee the last operation of switching bandwidth ++ // is executed properlly. ++ HTSetConnectBwModeCallback(ieee); ++ ++// spin_unlock_irqrestore(&(ieee->bw_spinlock), flags); ++} ++ ++void HTSetConnectBwModeCallback(struct ieee80211_device* ieee) ++{ ++ PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; ++ ++ IEEE80211_DEBUG(IEEE80211_DL_HT, "======>%s()\n", __FUNCTION__); ++ ++ if(pHTInfo->bCurBW40MHz) ++ { ++ if(pHTInfo->CurSTAExtChnlOffset==HT_EXTCHNL_OFFSET_UPPER) ++ ieee->set_chan(ieee->dev, ieee->current_network.channel+2); ++ else if(pHTInfo->CurSTAExtChnlOffset==HT_EXTCHNL_OFFSET_LOWER) ++ ieee->set_chan(ieee->dev, ieee->current_network.channel-2); ++ else ++ ieee->set_chan(ieee->dev, ieee->current_network.channel); ++ ++ ieee->SetBWModeHandler(ieee->dev, HT_CHANNEL_WIDTH_20_40, pHTInfo->CurSTAExtChnlOffset); ++ } else { ++ ieee->set_chan(ieee->dev, ieee->current_network.channel); ++ ieee->SetBWModeHandler(ieee->dev, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); ++ } ++ ++ pHTInfo->bSwBwInProgress = false; ++} ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++//EXPORT_SYMBOL_NOVERS(HTUpdateSelfAndPeerSetting); ++#else ++//EXPORT_SYMBOL(HTUpdateSelfAndPeerSetting); ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_Qos.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_Qos.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_Qos.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,749 @@ ++#ifndef __INC_QOS_TYPE_H ++#define __INC_QOS_TYPE_H ++ ++//#include "EndianFree.h" ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++ ++#define MAX_WMMELE_LENGTH 64 ++ ++// ++// QoS mode. ++// enum 0, 1, 2, 4: since we can use the OR(|) operation. ++// ++// QOS_MODE is redefined for enum can't be ++, | under C++ compiler, 2006.05.17, by rcnjko. ++//typedef enum _QOS_MODE{ ++// QOS_DISABLE = 0, ++// QOS_WMM = 1, ++// QOS_EDCA = 2, ++// QOS_HCCA = 4, ++//}QOS_MODE,*PQOS_MODE; ++// ++typedef u32 QOS_MODE, *PQOS_MODE; ++#define QOS_DISABLE 0 ++#define QOS_WMM 1 ++#define QOS_WMMSA 2 ++#define QOS_EDCA 4 ++#define QOS_HCCA 8 ++#define QOS_WMM_UAPSD 16 //WMM Power Save, 2006-06-14 Isaiah ++ ++#define AC_PARAM_SIZE 4 ++#define WMM_PARAM_ELE_BODY_LEN 18 ++ ++// ++// QoS ACK Policy Field Values ++// Ref: WMM spec 2.1.6: QoS Control Field, p.10. ++// ++typedef enum _ACK_POLICY{ ++ eAckPlc0_ACK = 0x00, ++ eAckPlc1_NoACK = 0x01, ++}ACK_POLICY,*PACK_POLICY; ++ ++#define WMM_PARAM_ELEMENT_SIZE (8+(4*AC_PARAM_SIZE)) ++#if 0 ++#define GET_QOS_CTRL(_pStart) ReadEF2Byte((u8 *)(_pStart) + 24) ++#define SET_QOS_CTRL(_pStart, _value) WriteEF2Byte((u8 *)(_pStart) + 24, _value) ++ ++// WMM control field. ++#define GET_QOS_CTRL_WMM_UP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 3)) ++#define SET_QOS_CTRL_WMM_UP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 3, (u8)(_value)) ++ ++#define GET_QOS_CTRL_WMM_EOSP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1)) ++#define SET_QOS_CTRL_WMM_EOSP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value)) ++ ++#define GET_QOS_CTRL_WMM_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2)) ++#define SET_QOS_CTRL_WMM_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value)) ++ ++// 802.11e control field (by STA, data) ++#define GET_QOS_CTRL_STA_DATA_TID(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 4)) ++#define SET_QOS_CTRL_STA_DATA_TID(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 4, (u8)(_value)) ++ ++#define GET_QOS_CTRL_STA_DATA_QSIZE_FLAG(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1)) ++#define SET_QOS_CTRL_STA_DATA_QSIZE_FLAG(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value)) ++ ++#define GET_QOS_CTRL_STA_DATA_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2)) ++#define SET_QOS_CTRL_STA_DATA_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value)) ++ ++#define GET_QOS_CTRL_STA_DATA_TXOP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 8, 8)) ++#define SET_QOS_CTRL_STA_DATA_TXOP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 8, 8, (u8)(_value)) ++ ++#define GET_QOS_CTRL_STA_DATA_QSIZE(_pStart) GET_QOS_CTRL_STA_DATA_TXOP(_pStart) ++#define SET_QOS_CTRL_STA_DATA_QSIZE(_pStart, _value) SET_QOS_CTRL_STA_DATA_TXOP(_pStart) ++ ++// 802.11e control field (by HC, data) ++#define GET_QOS_CTRL_HC_DATA_TID(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 4)) ++#define SET_QOS_CTRL_HC_DATA_TID(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 4, (u8)(_value)) ++ ++#define GET_QOS_CTRL_HC_DATA_EOSP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1)) ++#define SET_QOS_CTRL_HC_DATA_EOSP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value)) ++ ++#define GET_QOS_CTRL_HC_DATA_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2)) ++#define SET_QOS_CTRL_HC_DATA_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value)) ++ ++#define GET_QOS_CTRL_HC_DATA_PS_BUFSTATE(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 8, 8)) ++#define SET_QOS_CTRL_HC_DATA_PS_BUFSTATE(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 8, 8, (u8)(_value)) ++ ++// 802.11e control field (by HC, CFP) ++#define GET_QOS_CTRL_HC_CFP_TID(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 4)) ++#define SET_QOS_CTRL_HC_CFP_TID(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 4, (u8)(_value)) ++ ++#define GET_QOS_CTRL_HC_CFP_EOSP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1)) ++#define SET_QOS_CTRL_HC_CFP_EOSP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value)) ++ ++#define GET_QOS_CTRL_HC_CFP_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2)) ++#define SET_QOS_CTRL_HC_CFP_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value)) ++ ++#define GET_QOS_CTRL_HC_CFP_TXOP_LIMIT(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 8, 8)) ++#define SET_QOS_CTRL_HC_CFP_TXOP_LIMIT(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 8, 8, (u8)(_value)) ++ ++#define SET_WMM_QOS_INFO_FIELD(_pStart, _val) WriteEF1Byte(_pStart, _val) ++ ++#define GET_WMM_QOS_INFO_FIELD_PARAMETERSET_COUNT(_pStart) LE_BITS_TO_1BYTE(_pStart, 0, 4) ++#define SET_WMM_QOS_INFO_FIELD_PARAMETERSET_COUNT(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 0, 4, _val) ++ ++#define GET_WMM_QOS_INFO_FIELD_AP_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 7, 1) ++#define SET_WMM_QOS_INFO_FIELD_AP_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 7, 1, _val) ++ ++#define GET_WMM_QOS_INFO_FIELD_STA_AC_VO_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 0, 1) ++#define SET_WMM_QOS_INFO_FIELD_STA_AC_VO_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 0, 1, _val) ++ ++#define GET_WMM_QOS_INFO_FIELD_STA_AC_VI_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 1, 1) ++#define SET_WMM_QOS_INFO_FIELD_STA_AC_VI_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 1, 1, _val) ++ ++#define GET_WMM_QOS_INFO_FIELD_STA_AC_BE_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 2, 1) ++#define SET_WMM_QOS_INFO_FIELD_STA_AC_BE_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 2, 1, _val) ++ ++#define GET_WMM_QOS_INFO_FIELD_STA_AC_BK_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 3, 1) ++#define SET_WMM_QOS_INFO_FIELD_STA_AC_BK_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 3, 1, _val) ++ ++#define GET_WMM_QOS_INFO_FIELD_STA_MAX_SP_LEN(_pStart) LE_BITS_TO_1BYTE(_pStart, 5, 2) ++#define SET_WMM_QOS_INFO_FIELD_STA_MAX_SP_LEN(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 5, 2, _val) ++ ++ ++#define WMM_INFO_ELEMENT_SIZE 7 ++ ++#define GET_WMM_INFO_ELE_OUI(_pStart) ((u8 *)(_pStart)) ++#define SET_WMM_INFO_ELE_OUI(_pStart, _pVal) PlatformMoveMemory(_pStart, _pVal, 3); ++ ++#define GET_WMM_INFO_ELE_OUI_TYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+3) ) ) ++#define SET_WMM_INFO_ELE_OUI_TYPE(_pStart, _val) ( *((u8 *)(_pStart)+3) = EF1Byte(_val) ) ++ ++#define GET_WMM_INFO_ELE_OUI_SUBTYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+4) ) ) ++#define SET_WMM_INFO_ELE_OUI_SUBTYPE(_pStart, _val) ( *((u8 *)(_pStart)+4) = EF1Byte(_val) ) ++ ++#define GET_WMM_INFO_ELE_VERSION(_pStart) ( EF1Byte( *((u8 *)(_pStart)+5) ) ) ++#define SET_WMM_INFO_ELE_VERSION(_pStart, _val) ( *((u8 *)(_pStart)+5) = EF1Byte(_val) ) ++ ++#define GET_WMM_INFO_ELE_QOS_INFO_FIELD(_pStart) ( EF1Byte( *((u8 *)(_pStart)+6) ) ) ++#define SET_WMM_INFO_ELE_QOS_INFO_FIELD(_pStart, _val) ( *((u8 *)(_pStart)+6) = EF1Byte(_val) ) ++ ++ ++ ++#define GET_WMM_AC_PARAM_AIFSN(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 0, 4) ) ++#define SET_WMM_AC_PARAM_AIFSN(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 0, 4, _val) ++ ++#define GET_WMM_AC_PARAM_ACM(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 4, 1) ) ++#define SET_WMM_AC_PARAM_ACM(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 4, 1, _val) ++ ++#define GET_WMM_AC_PARAM_ACI(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 5, 2) ) ++#define SET_WMM_AC_PARAM_ACI(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 5, 2, _val) ++ ++#define GET_WMM_AC_PARAM_ACI_AIFSN(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 0, 8) ) ++#define SET_WMM_AC_PARAM_ACI_AIFSN(_pStart, _val) SET_BTIS_TO_LE_4BYTE(_pStart, 0, 8, _val) ++ ++#define GET_WMM_AC_PARAM_ECWMIN(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 8, 4) ) ++#define SET_WMM_AC_PARAM_ECWMIN(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 8, 4, _val) ++ ++#define GET_WMM_AC_PARAM_ECWMAX(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 12, 4) ) ++#define SET_WMM_AC_PARAM_ECWMAX(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 12, 4, _val) ++ ++#define GET_WMM_AC_PARAM_TXOP_LIMIT(_pStart) ( (u16)LE_BITS_TO_4BYTE(_pStart, 16, 16) ) ++#define SET_WMM_AC_PARAM_TXOP_LIMIT(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 16, 16, _val) ++ ++ ++ ++ ++#define GET_WMM_PARAM_ELE_OUI(_pStart) ((u8 *)(_pStart)) ++#define SET_WMM_PARAM_ELE_OUI(_pStart, _pVal) PlatformMoveMemory(_pStart, _pVal, 3) ++ ++#define GET_WMM_PARAM_ELE_OUI_TYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+3) ) ) ++#define SET_WMM_PARAM_ELE_OUI_TYPE(_pStart, _val) ( *((u8 *)(_pStart)+3) = EF1Byte(_val) ) ++ ++#define GET_WMM_PARAM_ELE_OUI_SUBTYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+4) ) ) ++#define SET_WMM_PARAM_ELE_OUI_SUBTYPE(_pStart, _val) ( *((u8 *)(_pStart)+4) = EF1Byte(_val) ) ++ ++#define GET_WMM_PARAM_ELE_VERSION(_pStart) ( EF1Byte( *((u8 *)(_pStart)+5) ) ) ++#define SET_WMM_PARAM_ELE_VERSION(_pStart, _val) ( *((u8 *)(_pStart)+5) = EF1Byte(_val) ) ++ ++#define GET_WMM_PARAM_ELE_QOS_INFO_FIELD(_pStart) ( EF1Byte( *((u8 *)(_pStart)+6) ) ) ++#define SET_WMM_PARAM_ELE_QOS_INFO_FIELD(_pStart, _val) ( *((u8 *)(_pStart)+6) = EF1Byte(_val) ) ++ ++#define GET_WMM_PARAM_ELE_AC_PARAM(_pStart) ( (u8 *)(_pStart)+8 ) ++#define SET_WMM_PARAM_ELE_AC_PARAM(_pStart, _pVal) PlatformMoveMemory((_pStart)+8, _pVal, 16) ++#endif ++ ++// ++// QoS Control Field ++// Ref: ++// 1. WMM spec 2.1.6: QoS Control Field, p.9. ++// 2. 802.11e/D13.0 7.1.3.5, p.26. ++// ++typedef union _QOS_CTRL_FIELD{ ++ u8 charData[2]; ++ u16 shortData; ++ ++ // WMM spec ++ struct ++ { ++ u8 UP:3; ++ u8 usRsvd1:1; ++ u8 EOSP:1; ++ u8 AckPolicy:2; ++ u8 usRsvd2:1; ++ u8 ucRsvdByte; ++ }WMM; ++ ++ // 802.11e: QoS data type frame sent by non-AP QSTAs. ++ struct ++ { ++ u8 TID:4; ++ u8 bIsQsize:1;// 0: BIT[8:15] is TXOP Duration Requested, 1: BIT[8:15] is Queue Size. ++ u8 AckPolicy:2; ++ u8 usRsvd:1; ++ u8 TxopOrQsize; // (BIT4=0)TXOP Duration Requested or (BIT4=1)Queue Size. ++ }BySta; ++ ++ // 802.11e: QoS data, QoS Null, and QoS Data+CF-Ack frames sent by HC. ++ struct ++ { ++ u8 TID:4; ++ u8 EOSP:1; ++ u8 AckPolicy:2; ++ u8 usRsvd:1; ++ u8 PSBufState; // QAP PS Buffer State. ++ }ByHc_Data; ++ ++ // 802.11e: QoS (+) CF-Poll frames sent by HC. ++ struct ++ { ++ u8 TID:4; ++ u8 EOSP:1; ++ u8 AckPolicy:2; ++ u8 usRsvd:1; ++ u8 TxopLimit; // TXOP Limit. ++ }ByHc_CFP; ++ ++}QOS_CTRL_FIELD, *PQOS_CTRL_FIELD; ++ ++ ++// ++// QoS Info Field ++// Ref: ++// 1. WMM spec 2.2.1: WME Information Element, p.11. ++// 2. 8185 QoS code: QOS_INFO [def. in QoS_mp.h] ++// ++typedef union _QOS_INFO_FIELD{ ++ u8 charData; ++ ++ struct ++ { ++ u8 ucParameterSetCount:4; ++ u8 ucReserved:4; ++ }WMM; ++ ++ struct ++ { ++ //Ref WMM_Specification_1-1.pdf, 2006-06-13 Isaiah ++ u8 ucAC_VO_UAPSD:1; ++ u8 ucAC_VI_UAPSD:1; ++ u8 ucAC_BE_UAPSD:1; ++ u8 ucAC_BK_UAPSD:1; ++ u8 ucReserved1:1; ++ u8 ucMaxSPLen:2; ++ u8 ucReserved2:1; ++ ++ }ByWmmPsSta; ++ ++ struct ++ { ++ //Ref WMM_Specification_1-1.pdf, 2006-06-13 Isaiah ++ u8 ucParameterSetCount:4; ++ u8 ucReserved:3; ++ u8 ucApUapsd:1; ++ }ByWmmPsAp; ++ ++ struct ++ { ++ u8 ucAC3_UAPSD:1; ++ u8 ucAC2_UAPSD:1; ++ u8 ucAC1_UAPSD:1; ++ u8 ucAC0_UAPSD:1; ++ u8 ucQAck:1; ++ u8 ucMaxSPLen:2; ++ u8 ucMoreDataAck:1; ++ } By11eSta; ++ ++ struct ++ { ++ u8 ucParameterSetCount:4; ++ u8 ucQAck:1; ++ u8 ucQueueReq:1; ++ u8 ucTXOPReq:1; ++ u8 ucReserved:1; ++ } By11eAp; ++ ++ struct ++ { ++ u8 ucReserved1:4; ++ u8 ucQAck:1; ++ u8 ucReserved2:2; ++ u8 ucMoreDataAck:1; ++ } ByWmmsaSta; ++ ++ struct ++ { ++ u8 ucReserved1:4; ++ u8 ucQAck:1; ++ u8 ucQueueReq:1; ++ u8 ucTXOPReq:1; ++ u8 ucReserved2:1; ++ } ByWmmsaAp; ++ ++ struct ++ { ++ u8 ucAC3_UAPSD:1; ++ u8 ucAC2_UAPSD:1; ++ u8 ucAC1_UAPSD:1; ++ u8 ucAC0_UAPSD:1; ++ u8 ucQAck:1; ++ u8 ucMaxSPLen:2; ++ u8 ucMoreDataAck:1; ++ } ByAllSta; ++ ++ struct ++ { ++ u8 ucParameterSetCount:4; ++ u8 ucQAck:1; ++ u8 ucQueueReq:1; ++ u8 ucTXOPReq:1; ++ u8 ucApUapsd:1; ++ } ByAllAp; ++ ++}QOS_INFO_FIELD, *PQOS_INFO_FIELD; ++ ++#if 0 ++// ++// WMM Information Element ++// Ref: WMM spec 2.2.1: WME Information Element, p.10. ++// ++typedef struct _WMM_INFO_ELEMENT{ ++// u8 ElementID; ++// u8 Length; ++ u8 OUI[3]; ++ u8 OUI_Type; ++ u8 OUI_SubType; ++ u8 Version; ++ QOS_INFO_FIELD QosInfo; ++}WMM_INFO_ELEMENT, *PWMM_INFO_ELEMENT; ++#endif ++ ++// ++// ACI to AC coding. ++// Ref: WMM spec 2.2.2: WME Parameter Element, p.13. ++// ++// AC_CODING is redefined for enum can't be ++, | under C++ compiler, 2006.05.17, by rcnjko. ++//typedef enum _AC_CODING{ ++// AC0_BE = 0, // ACI: 0x00 // Best Effort ++// AC1_BK = 1, // ACI: 0x01 // Background ++// AC2_VI = 2, // ACI: 0x10 // Video ++// AC3_VO = 3, // ACI: 0x11 // Voice ++// AC_MAX = 4, // Max: define total number; Should not to be used as a real enum. ++//}AC_CODING,*PAC_CODING; ++// ++typedef u32 AC_CODING; ++#define AC0_BE 0 // ACI: 0x00 // Best Effort ++#define AC1_BK 1 // ACI: 0x01 // Background ++#define AC2_VI 2 // ACI: 0x10 // Video ++#define AC3_VO 3 // ACI: 0x11 // Voice ++#define AC_MAX 4 // Max: define total number; Should not to be used as a real enum. ++ ++// ++// ACI/AIFSN Field. ++// Ref: WMM spec 2.2.2: WME Parameter Element, p.12. ++// ++typedef union _ACI_AIFSN{ ++ u8 charData; ++ ++ struct ++ { ++ u8 AIFSN:4; ++ u8 ACM:1; ++ u8 ACI:2; ++ u8 Reserved:1; ++ }f; // Field ++}ACI_AIFSN, *PACI_AIFSN; ++ ++// ++// ECWmin/ECWmax field. ++// Ref: WMM spec 2.2.2: WME Parameter Element, p.13. ++// ++typedef union _ECW{ ++ u8 charData; ++ struct ++ { ++ u8 ECWmin:4; ++ u8 ECWmax:4; ++ }f; // Field ++}ECW, *PECW; ++ ++// ++// AC Parameters Record Format. ++// Ref: WMM spec 2.2.2: WME Parameter Element, p.12. ++// ++typedef union _AC_PARAM{ ++ u32 longData; ++ u8 charData[4]; ++ ++ struct ++ { ++ ACI_AIFSN AciAifsn; ++ ECW Ecw; ++ u16 TXOPLimit; ++ }f; // Field ++}AC_PARAM, *PAC_PARAM; ++ ++ ++ ++// ++// QoS element subtype ++// ++typedef enum _QOS_ELE_SUBTYPE{ ++ QOSELE_TYPE_INFO = 0x00, // 0x00: Information element ++ QOSELE_TYPE_PARAM = 0x01, // 0x01: parameter element ++}QOS_ELE_SUBTYPE,*PQOS_ELE_SUBTYPE; ++ ++ ++// ++// Direction Field Values. ++// Ref: WMM spec 2.2.11: WME TSPEC Element, p.18. ++// ++typedef enum _DIRECTION_VALUE{ ++ DIR_UP = 0, // 0x00 // UpLink ++ DIR_DOWN = 1, // 0x01 // DownLink ++ DIR_DIRECT = 2, // 0x10 // DirectLink ++ DIR_BI_DIR = 3, // 0x11 // Bi-Direction ++}DIRECTION_VALUE,*PDIRECTION_VALUE; ++ ++ ++// ++// TS Info field in WMM TSPEC Element. ++// Ref: ++// 1. WMM spec 2.2.11: WME TSPEC Element, p.18. ++// 2. 8185 QoS code: QOS_TSINFO [def. in QoS_mp.h] ++// ++typedef union _QOS_TSINFO{ ++ u8 charData[3]; ++ struct { ++ u8 ucTrafficType:1; //WMM is reserved ++ u8 ucTSID:4; ++ u8 ucDirection:2; ++ u8 ucAccessPolicy:2; //WMM: bit8=0, bit7=1 ++ u8 ucAggregation:1; //WMM is reserved ++ u8 ucPSB:1; //WMMSA is APSD ++ u8 ucUP:3; ++ u8 ucTSInfoAckPolicy:2; //WMM is reserved ++ u8 ucSchedule:1; //WMM is reserved ++ u8 ucReserved:7; ++ }field; ++}QOS_TSINFO, *PQOS_TSINFO; ++ ++// ++// WMM TSPEC Body. ++// Ref: WMM spec 2.2.11: WME TSPEC Element, p.16. ++// ++typedef union _TSPEC_BODY{ ++ u8 charData[55]; ++ ++ struct ++ { ++ QOS_TSINFO TSInfo; //u8 TSInfo[3]; ++ u16 NominalMSDUsize; ++ u16 MaxMSDUsize; ++ u32 MinServiceItv; ++ u32 MaxServiceItv; ++ u32 InactivityItv; ++ u32 SuspenItv; ++ u32 ServiceStartTime; ++ u32 MinDataRate; ++ u32 MeanDataRate; ++ u32 PeakDataRate; ++ u32 MaxBurstSize; ++ u32 DelayBound; ++ u32 MinPhyRate; ++ u16 SurplusBandwidthAllowance; ++ u16 MediumTime; ++ } f; // Field ++}TSPEC_BODY, *PTSPEC_BODY; ++ ++ ++// ++// WMM TSPEC Element. ++// Ref: WMM spec 2.2.11: WME TSPEC Element, p.16. ++// ++typedef struct _WMM_TSPEC{ ++ u8 ID; ++ u8 Length; ++ u8 OUI[3]; ++ u8 OUI_Type; ++ u8 OUI_SubType; ++ u8 Version; ++ TSPEC_BODY Body; ++} WMM_TSPEC, *PWMM_TSPEC; ++ ++// ++// ACM implementation method. ++// Annie, 2005-12-13. ++// ++typedef enum _ACM_METHOD{ ++ eAcmWay0_SwAndHw = 0, // By SW and HW. ++ eAcmWay1_HW = 1, // By HW. ++ eAcmWay2_SW = 2, // By SW. ++}ACM_METHOD,*PACM_METHOD; ++ ++ ++typedef struct _ACM{ ++// u8 RegEnableACM; ++ u64 UsedTime; ++ u64 MediumTime; ++ u8 HwAcmCtl; // TRUE: UsedTime exceed => Do NOT USE this AC. It wll be written to ACM_CONTROL(0xBF BIT 0/1/2 in 8185B). ++}ACM, *PACM; ++ ++typedef u8 AC_UAPSD, *PAC_UAPSD; ++ ++#define GET_VO_UAPSD(_apsd) ((_apsd) & BIT0) ++#define SET_VO_UAPSD(_apsd) ((_apsd) |= BIT0) ++ ++#define GET_VI_UAPSD(_apsd) ((_apsd) & BIT1) ++#define SET_VI_UAPSD(_apsd) ((_apsd) |= BIT1) ++ ++#define GET_BK_UAPSD(_apsd) ((_apsd) & BIT2) ++#define SET_BK_UAPSD(_apsd) ((_apsd) |= BIT2) ++ ++#define GET_BE_UAPSD(_apsd) ((_apsd) & BIT3) ++#define SET_BE_UAPSD(_apsd) ((_apsd) |= BIT3) ++ ++ ++//typedef struct _TCLASS{ ++// TODO ++//} TCLASS, *PTCLASS; ++typedef union _QOS_TCLAS{ ++ ++ struct _TYPE_GENERAL{ ++ u8 Priority; ++ u8 ClassifierType; ++ u8 Mask; ++ } TYPE_GENERAL; ++ ++ struct _TYPE0_ETH{ ++ u8 Priority; ++ u8 ClassifierType; ++ u8 Mask; ++ u8 SrcAddr[6]; ++ u8 DstAddr[6]; ++ u16 Type; ++ } TYPE0_ETH; ++ ++ struct _TYPE1_IPV4{ ++ u8 Priority; ++ u8 ClassifierType; ++ u8 Mask; ++ u8 Version; ++ u8 SrcIP[4]; ++ u8 DstIP[4]; ++ u16 SrcPort; ++ u16 DstPort; ++ u8 DSCP; ++ u8 Protocol; ++ u8 Reserved; ++ } TYPE1_IPV4; ++ ++ struct _TYPE1_IPV6{ ++ u8 Priority; ++ u8 ClassifierType; ++ u8 Mask; ++ u8 Version; ++ u8 SrcIP[16]; ++ u8 DstIP[16]; ++ u16 SrcPort; ++ u16 DstPort; ++ u8 FlowLabel[3]; ++ } TYPE1_IPV6; ++ ++ struct _TYPE2_8021Q{ ++ u8 Priority; ++ u8 ClassifierType; ++ u8 Mask; ++ u16 TagType; ++ } TYPE2_8021Q; ++} QOS_TCLAS, *PQOS_TCLAS; ++ ++//typedef struct _WMM_TSTREAM{ ++// ++//- TSPEC ++//- AC (which to mapping) ++//} WMM_TSTREAM, *PWMM_TSTREAM; ++typedef struct _QOS_TSTREAM{ ++ u8 AC; ++ WMM_TSPEC TSpec; ++ QOS_TCLAS TClass; ++} QOS_TSTREAM, *PQOS_TSTREAM; ++ ++//typedef struct _U_APSD{ ++//- TriggerEnable [4] ++//- MaxSPLength ++//- HighestAcBuffered ++//} U_APSD, *PU_APSD; ++ ++//joseph TODO: ++// UAPSD function should be implemented by 2 data structure ++// "Qos control field" and "Qos info field" ++//typedef struct _QOS_UAPSD{ ++// u8 bTriggerEnable[4]; ++// u8 MaxSPLength; ++// u8 HighestBufAC; ++//} QOS_UAPSD, *PQOS_APSD; ++ ++//---------------------------------------------------------------------------- ++// 802.11 Management frame Status Code field ++//---------------------------------------------------------------------------- ++typedef struct _OCTET_STRING{ ++ u8 *Octet; ++ u16 Length; ++}OCTET_STRING, *POCTET_STRING; ++#if 0 ++#define FillOctetString(_os,_octet,_len) \ ++ (_os).Octet=(u8 *)(_octet); \ ++ (_os).Length=(_len); ++ ++#define WMM_ELEM_HDR_LEN 6 ++#define WMMElemSkipHdr(_osWMMElem) \ ++ (_osWMMElem).Octet += WMM_ELEM_HDR_LEN; \ ++ (_osWMMElem).Length -= WMM_ELEM_HDR_LEN; ++#endif ++// ++// STA QoS data. ++// Ref: DOT11_QOS in 8185 code. [def. in QoS_mp.h] ++// ++typedef struct _STA_QOS{ ++ //DECLARE_RT_OBJECT(STA_QOS); ++ u8 WMMIEBuf[MAX_WMMELE_LENGTH]; ++ u8* WMMIE; ++ ++ // Part 1. Self QoS Mode. ++ QOS_MODE QosCapability; //QoS Capability, 2006-06-14 Isaiah ++ QOS_MODE CurrentQosMode; ++ ++ // For WMM Power Save Mode : ++ // ACs are trigger/delivery enabled or legacy power save enabled. 2006-06-13 Isaiah ++ AC_UAPSD b4ac_Uapsd; //VoUapsd(bit0), ViUapsd(bit1), BkUapsd(bit2), BeUapsd(bit3), ++ AC_UAPSD Curr4acUapsd; ++ u8 bInServicePeriod; ++ u8 MaxSPLength; ++ int NumBcnBeforeTrigger; ++ ++ // Part 2. EDCA Parameter (perAC) ++ u8 * pWMMInfoEle; ++ u8 WMMParamEle[WMM_PARAM_ELEMENT_SIZE]; ++ u8 WMMPELength; ++ ++ // ++ //2 ToDo: remove the Qos Info Field and replace it by the above WMM Info element. ++ // By Bruce, 2008-01-30. ++ // Part 2. EDCA Parameter (perAC) ++ QOS_INFO_FIELD QosInfoField_STA; // Maintained by STA ++ QOS_INFO_FIELD QosInfoField_AP; // Retrieved from AP ++ ++ AC_PARAM CurAcParameters[4]; ++ ++ // Part 3. ACM ++ ACM acm[4]; ++ ACM_METHOD AcmMethod; ++ ++ // Part 4. Per TID (Part 5: TCLASS will be described by TStream) ++ QOS_TSTREAM TStream[16]; ++ WMM_TSPEC TSpec; ++ ++ u32 QBssWirelessMode; ++ ++ // No Ack Setting ++ u8 bNoAck; ++ ++ // Enable/Disable Rx immediate BA capability. ++ u8 bEnableRxImmBA; ++ ++}STA_QOS, *PSTA_QOS; ++ ++// ++// BSS QOS data. ++// Ref: BssDscr in 8185 code. [def. in BssDscr.h] ++// ++typedef struct _BSS_QOS{ ++ QOS_MODE bdQoSMode; ++ ++ u8 bdWMMIEBuf[MAX_WMMELE_LENGTH]; ++ u8* bdWMMIE; ++ ++ QOS_ELE_SUBTYPE EleSubType; ++ ++ u8 * pWMMInfoEle; ++ u8 * pWMMParamEle; ++ ++ QOS_INFO_FIELD QosInfoField; ++ AC_PARAM AcParameter[4]; ++}BSS_QOS, *PBSS_QOS; ++ ++ ++// ++// Ref: sQoSCtlLng and QoSCtl definition in 8185 QoS code. ++//#define QoSCtl (( (Adapter->bRegQoS) && (Adapter->dot11QoS.QoSMode &(QOS_EDCA|QOS_HCCA)) ) ?sQoSCtlLng:0) ++// ++#define sQoSCtlLng 2 ++#define QOS_CTRL_LEN(_QosMode) ((_QosMode > QOS_DISABLE)? sQoSCtlLng : 0) ++ ++ ++//Added by joseph ++//UP Mapping to AC, using in MgntQuery_SequenceNumber() and maybe for DSCP ++//#define UP2AC(up) ((up<3)?((up==0)?1:0):(up>>1)) ++#define IsACValid(ac) ((ac<=7 )?true:false ) ++ ++#endif // #ifndef __INC_QOS_TYPE_H +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_TS.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_TS.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_TS.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,56 @@ ++#ifndef _TSTYPE_H_ ++#define _TSTYPE_H_ ++#include "rtl819x_Qos.h" ++#define TS_SETUP_TIMEOUT 60 // In millisecond ++#define TS_INACT_TIMEOUT 60 ++#define TS_ADDBA_DELAY 60 ++ ++#define TOTAL_TS_NUM 16 ++#define TCLAS_NUM 4 ++ ++// This define the Tx/Rx directions ++typedef enum _TR_SELECT { ++ TX_DIR = 0, ++ RX_DIR = 1, ++} TR_SELECT, *PTR_SELECT; ++ ++typedef struct _TS_COMMON_INFO{ ++ struct list_head List; ++ struct timer_list SetupTimer; ++ struct timer_list InactTimer; ++ u8 Addr[6]; ++ TSPEC_BODY TSpec; ++ QOS_TCLAS TClass[TCLAS_NUM]; ++ u8 TClasProc; ++ u8 TClasNum; ++} TS_COMMON_INFO, *PTS_COMMON_INFO; ++ ++typedef struct _TX_TS_RECORD{ ++ TS_COMMON_INFO TsCommonInfo; ++ u16 TxCurSeq; ++ BA_RECORD TxPendingBARecord; // For BA Originator ++ BA_RECORD TxAdmittedBARecord; // For BA Originator ++// QOS_DL_RECORD DLRecord; ++ u8 bAddBaReqInProgress; ++ u8 bAddBaReqDelayed; ++ u8 bUsingBa; ++ struct timer_list TsAddBaTimer; ++ u8 num; ++} TX_TS_RECORD, *PTX_TS_RECORD; ++ ++typedef struct _RX_TS_RECORD { ++ TS_COMMON_INFO TsCommonInfo; ++ u16 RxIndicateSeq; ++ u16 RxTimeoutIndicateSeq; ++ struct list_head RxPendingPktList; ++ struct timer_list RxPktPendingTimer; ++ BA_RECORD RxAdmittedBARecord; // For BA Recepient ++ u16 RxLastSeqNum; ++ u8 RxLastFragNum; ++ u8 num; ++// QOS_DL_RECORD DLRecord; ++} RX_TS_RECORD, *PRX_TS_RECORD; ++ ++ ++#endif ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_TSProc.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_TSProc.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl819x_TSProc.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,659 @@ ++#include "ieee80211.h" ++#include ++#include "rtl819x_TS.h" ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++#define list_for_each_entry_safe(pos, n, head, member) \ ++ for (pos = list_entry((head)->next, typeof(*pos), member), \ ++ n = list_entry(pos->member.next, typeof(*pos), member); \ ++ &pos->member != (head); \ ++ pos = n, n = list_entry(n->member.next, typeof(*n), member)) ++#endif ++void TsSetupTimeOut(unsigned long data) ++{ ++ // Not implement yet ++ // This is used for WMMSA and ACM , that would send ADDTSReq frame. ++} ++ ++void TsInactTimeout(unsigned long data) ++{ ++ // Not implement yet ++ // This is used for WMMSA and ACM. ++ // This function would be call when TS is no Tx/Rx for some period of time. ++} ++ ++/******************************************************************************************************************** ++ *function: I still not understand this function, so wait for further implementation ++ * input: unsigned long data //acturally we send TX_TS_RECORD or RX_TS_RECORD to these timer ++ * return: NULL ++ * notice: ++********************************************************************************************************************/ ++#if 1 ++void RxPktPendingTimeout(unsigned long data) ++{ ++ PRX_TS_RECORD pRxTs = (PRX_TS_RECORD)data; ++ struct ieee80211_device *ieee = container_of(pRxTs, struct ieee80211_device, RxTsRecord[pRxTs->num]); ++ ++ PRX_REORDER_ENTRY pReorderEntry = NULL; ++ ++ //u32 flags = 0; ++ unsigned long flags = 0; ++ struct ieee80211_rxb *stats_IndicateArray[REORDER_WIN_SIZE]; ++ u8 index = 0; ++ bool bPktInBuf = false; ++ ++ ++ spin_lock_irqsave(&(ieee->reorder_spinlock), flags); ++ //PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK); ++ IEEE80211_DEBUG(IEEE80211_DL_REORDER,"==================>%s()\n",__FUNCTION__); ++ if(pRxTs->RxTimeoutIndicateSeq != 0xffff) ++ { ++ // Indicate the pending packets sequentially according to SeqNum until meet the gap. ++ while(!list_empty(&pRxTs->RxPendingPktList)) ++ { ++ pReorderEntry = (PRX_REORDER_ENTRY)list_entry(pRxTs->RxPendingPktList.prev,RX_REORDER_ENTRY,List); ++ if(index == 0) ++ pRxTs->RxIndicateSeq = pReorderEntry->SeqNum; ++ ++ if( SN_LESS(pReorderEntry->SeqNum, pRxTs->RxIndicateSeq) || ++ SN_EQUAL(pReorderEntry->SeqNum, pRxTs->RxIndicateSeq) ) ++ { ++ list_del_init(&pReorderEntry->List); ++ ++ if(SN_EQUAL(pReorderEntry->SeqNum, pRxTs->RxIndicateSeq)) ++ pRxTs->RxIndicateSeq = (pRxTs->RxIndicateSeq + 1) % 4096; ++ ++ IEEE80211_DEBUG(IEEE80211_DL_REORDER,"RxPktPendingTimeout(): IndicateSeq: %d\n", pReorderEntry->SeqNum); ++ stats_IndicateArray[index] = pReorderEntry->prxb; ++ index++; ++ ++ list_add_tail(&pReorderEntry->List, &ieee->RxReorder_Unused_List); ++ } ++ else ++ { ++ bPktInBuf = true; ++ break; ++ } ++ } ++ } ++ ++ if(index>0) ++ { ++ // Set RxTimeoutIndicateSeq to 0xffff to indicate no pending packets in buffer now. ++ pRxTs->RxTimeoutIndicateSeq = 0xffff; ++ ++ // Indicate packets ++ if(index > REORDER_WIN_SIZE){ ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "RxReorderIndicatePacket(): Rx Reorer buffer full!! \n"); ++ spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags); ++ return; ++ } ++ ieee80211_indicate_packets(ieee, stats_IndicateArray, index); ++ bPktInBuf = false; ++ } ++ ++ if(bPktInBuf && (pRxTs->RxTimeoutIndicateSeq==0xffff)) ++ { ++ pRxTs->RxTimeoutIndicateSeq = pRxTs->RxIndicateSeq; ++#if 0 ++ if(timer_pending(&pRxTs->RxPktPendingTimer)) ++ del_timer_sync(&pRxTs->RxPktPendingTimer); ++ pRxTs->RxPktPendingTimer.expires = jiffies + ieee->pHTInfo->RxReorderPendingTime; ++ add_timer(&pRxTs->RxPktPendingTimer); ++#else ++ mod_timer(&pRxTs->RxPktPendingTimer, jiffies + MSECS(ieee->pHTInfo->RxReorderPendingTime)); ++#endif ++ } ++ spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags); ++ //PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK); ++} ++#endif ++ ++/******************************************************************************************************************** ++ *function: Add BA timer function ++ * input: unsigned long data //acturally we send TX_TS_RECORD or RX_TS_RECORD to these timer ++ * return: NULL ++ * notice: ++********************************************************************************************************************/ ++void TsAddBaProcess(unsigned long data) ++{ ++ PTX_TS_RECORD pTxTs = (PTX_TS_RECORD)data; ++ u8 num = pTxTs->num; ++ struct ieee80211_device *ieee = container_of(pTxTs, struct ieee80211_device, TxTsRecord[num]); ++ ++ TsInitAddBA(ieee, pTxTs, BA_POLICY_IMMEDIATE, false); ++ IEEE80211_DEBUG(IEEE80211_DL_BA, "TsAddBaProcess(): ADDBA Req is started!! \n"); ++} ++ ++ ++void ResetTsCommonInfo(PTS_COMMON_INFO pTsCommonInfo) ++{ ++ memset(pTsCommonInfo->Addr, 0, 6); ++ memset(&pTsCommonInfo->TSpec, 0, sizeof(TSPEC_BODY)); ++ memset(&pTsCommonInfo->TClass, 0, sizeof(QOS_TCLAS)*TCLAS_NUM); ++ pTsCommonInfo->TClasProc = 0; ++ pTsCommonInfo->TClasNum = 0; ++} ++ ++void ResetTxTsEntry(PTX_TS_RECORD pTS) ++{ ++ ResetTsCommonInfo(&pTS->TsCommonInfo); ++ pTS->TxCurSeq = 0; ++ pTS->bAddBaReqInProgress = false; ++ pTS->bAddBaReqDelayed = false; ++ pTS->bUsingBa = false; ++ ResetBaEntry(&pTS->TxAdmittedBARecord); //For BA Originator ++ ResetBaEntry(&pTS->TxPendingBARecord); ++} ++ ++void ResetRxTsEntry(PRX_TS_RECORD pTS) ++{ ++ ResetTsCommonInfo(&pTS->TsCommonInfo); ++ pTS->RxIndicateSeq = 0xffff; // This indicate the RxIndicateSeq is not used now!! ++ pTS->RxTimeoutIndicateSeq = 0xffff; // This indicate the RxTimeoutIndicateSeq is not used now!! ++ ResetBaEntry(&pTS->RxAdmittedBARecord); // For BA Recepient ++} ++ ++void TSInitialize(struct ieee80211_device *ieee) ++{ ++ PTX_TS_RECORD pTxTS = ieee->TxTsRecord; ++ PRX_TS_RECORD pRxTS = ieee->RxTsRecord; ++ PRX_REORDER_ENTRY pRxReorderEntry = ieee->RxReorderEntry; ++ u8 count = 0; ++ IEEE80211_DEBUG(IEEE80211_DL_TS, "==========>%s()\n", __FUNCTION__); ++ // Initialize Tx TS related info. ++ INIT_LIST_HEAD(&ieee->Tx_TS_Admit_List); ++ INIT_LIST_HEAD(&ieee->Tx_TS_Pending_List); ++ INIT_LIST_HEAD(&ieee->Tx_TS_Unused_List); ++ ++ for(count = 0; count < TOTAL_TS_NUM; count++) ++ { ++ // ++ pTxTS->num = count; ++ // The timers for the operation of Traffic Stream and Block Ack. ++ // DLS related timer will be add here in the future!! ++ init_timer(&pTxTS->TsCommonInfo.SetupTimer); ++ pTxTS->TsCommonInfo.SetupTimer.data = (unsigned long)pTxTS; ++ pTxTS->TsCommonInfo.SetupTimer.function = TsSetupTimeOut; ++ ++ init_timer(&pTxTS->TsCommonInfo.InactTimer); ++ pTxTS->TsCommonInfo.InactTimer.data = (unsigned long)pTxTS; ++ pTxTS->TsCommonInfo.InactTimer.function = TsInactTimeout; ++ ++ init_timer(&pTxTS->TsAddBaTimer); ++ pTxTS->TsAddBaTimer.data = (unsigned long)pTxTS; ++ pTxTS->TsAddBaTimer.function = TsAddBaProcess; ++ ++ init_timer(&pTxTS->TxPendingBARecord.Timer); ++ pTxTS->TxPendingBARecord.Timer.data = (unsigned long)pTxTS; ++ pTxTS->TxPendingBARecord.Timer.function = BaSetupTimeOut; ++ ++ init_timer(&pTxTS->TxAdmittedBARecord.Timer); ++ pTxTS->TxAdmittedBARecord.Timer.data = (unsigned long)pTxTS; ++ pTxTS->TxAdmittedBARecord.Timer.function = TxBaInactTimeout; ++ ++ ResetTxTsEntry(pTxTS); ++ list_add_tail(&pTxTS->TsCommonInfo.List, &ieee->Tx_TS_Unused_List); ++ pTxTS++; ++ } ++ ++ // Initialize Rx TS related info. ++ INIT_LIST_HEAD(&ieee->Rx_TS_Admit_List); ++ INIT_LIST_HEAD(&ieee->Rx_TS_Pending_List); ++ INIT_LIST_HEAD(&ieee->Rx_TS_Unused_List); ++ for(count = 0; count < TOTAL_TS_NUM; count++) ++ { ++ pRxTS->num = count; ++ INIT_LIST_HEAD(&pRxTS->RxPendingPktList); ++ ++ init_timer(&pRxTS->TsCommonInfo.SetupTimer); ++ pRxTS->TsCommonInfo.SetupTimer.data = (unsigned long)pRxTS; ++ pRxTS->TsCommonInfo.SetupTimer.function = TsSetupTimeOut; ++ ++ init_timer(&pRxTS->TsCommonInfo.InactTimer); ++ pRxTS->TsCommonInfo.InactTimer.data = (unsigned long)pRxTS; ++ pRxTS->TsCommonInfo.InactTimer.function = TsInactTimeout; ++ ++ init_timer(&pRxTS->RxAdmittedBARecord.Timer); ++ pRxTS->RxAdmittedBARecord.Timer.data = (unsigned long)pRxTS; ++ pRxTS->RxAdmittedBARecord.Timer.function = RxBaInactTimeout; ++ ++ init_timer(&pRxTS->RxPktPendingTimer); ++ pRxTS->RxPktPendingTimer.data = (unsigned long)pRxTS; ++ pRxTS->RxPktPendingTimer.function = RxPktPendingTimeout; ++ ++ ResetRxTsEntry(pRxTS); ++ list_add_tail(&pRxTS->TsCommonInfo.List, &ieee->Rx_TS_Unused_List); ++ pRxTS++; ++ } ++ // Initialize unused Rx Reorder List. ++ INIT_LIST_HEAD(&ieee->RxReorder_Unused_List); ++//#ifdef TO_DO_LIST ++ for(count = 0; count < REORDER_ENTRY_NUM; count++) ++ { ++ list_add_tail( &pRxReorderEntry->List,&ieee->RxReorder_Unused_List); ++ if(count == (REORDER_ENTRY_NUM-1)) ++ break; ++ pRxReorderEntry = &ieee->RxReorderEntry[count+1]; ++ } ++//#endif ++ ++} ++ ++void AdmitTS(struct ieee80211_device *ieee, PTS_COMMON_INFO pTsCommonInfo, u32 InactTime) ++{ ++ del_timer_sync(&pTsCommonInfo->SetupTimer); ++ del_timer_sync(&pTsCommonInfo->InactTimer); ++ ++ if(InactTime!=0) ++ mod_timer(&pTsCommonInfo->InactTimer, jiffies + MSECS(InactTime)); ++} ++ ++ ++PTS_COMMON_INFO SearchAdmitTRStream(struct ieee80211_device *ieee, u8* Addr, u8 TID, TR_SELECT TxRxSelect) ++{ ++ //DIRECTION_VALUE dir; ++ u8 dir; ++ bool search_dir[4] = {0, 0, 0, 0}; ++ struct list_head* psearch_list; //FIXME ++ PTS_COMMON_INFO pRet = NULL; ++ if(ieee->iw_mode == IW_MODE_MASTER) //ap mode ++ { ++ if(TxRxSelect == TX_DIR) ++ { ++ search_dir[DIR_DOWN] = true; ++ search_dir[DIR_BI_DIR]= true; ++ } ++ else ++ { ++ search_dir[DIR_UP] = true; ++ search_dir[DIR_BI_DIR]= true; ++ } ++ } ++ else if(ieee->iw_mode == IW_MODE_ADHOC) ++ { ++ if(TxRxSelect == TX_DIR) ++ search_dir[DIR_UP] = true; ++ else ++ search_dir[DIR_DOWN] = true; ++ } ++ else ++ { ++ if(TxRxSelect == TX_DIR) ++ { ++ search_dir[DIR_UP] = true; ++ search_dir[DIR_BI_DIR]= true; ++ search_dir[DIR_DIRECT]= true; ++ } ++ else ++ { ++ search_dir[DIR_DOWN] = true; ++ search_dir[DIR_BI_DIR]= true; ++ search_dir[DIR_DIRECT]= true; ++ } ++ } ++ ++ if(TxRxSelect == TX_DIR) ++ psearch_list = &ieee->Tx_TS_Admit_List; ++ else ++ psearch_list = &ieee->Rx_TS_Admit_List; ++ ++ //for(dir = DIR_UP; dir <= DIR_BI_DIR; dir++) ++ for(dir = 0; dir <= DIR_BI_DIR; dir++) ++ { ++ if(search_dir[dir] ==false ) ++ continue; ++ list_for_each_entry(pRet, psearch_list, List){ ++ // IEEE80211_DEBUG(IEEE80211_DL_TS, "ADD:"MAC_FMT", TID:%d, dir:%d\n", MAC_ARG(pRet->Addr), pRet->TSpec.f.TSInfo.field.ucTSID, pRet->TSpec.f.TSInfo.field.ucDirection); ++ if (memcmp(pRet->Addr, Addr, 6) == 0) ++ if (pRet->TSpec.f.TSInfo.field.ucTSID == TID) ++ if(pRet->TSpec.f.TSInfo.field.ucDirection == dir) ++ { ++ // printk("Bingo! got it\n"); ++ break; ++ } ++ ++ } ++ if(&pRet->List != psearch_list) ++ break; ++ } ++ ++ if(&pRet->List != psearch_list){ ++ return pRet ; ++ } ++ else ++ return NULL; ++} ++ ++void MakeTSEntry( ++ PTS_COMMON_INFO pTsCommonInfo, ++ u8* Addr, ++ PTSPEC_BODY pTSPEC, ++ PQOS_TCLAS pTCLAS, ++ u8 TCLAS_Num, ++ u8 TCLAS_Proc ++ ) ++{ ++ u8 count; ++ ++ if(pTsCommonInfo == NULL) ++ return; ++ ++ memcpy(pTsCommonInfo->Addr, Addr, 6); ++ ++ if(pTSPEC != NULL) ++ memcpy((u8*)(&(pTsCommonInfo->TSpec)), (u8*)pTSPEC, sizeof(TSPEC_BODY)); ++ ++ for(count = 0; count < TCLAS_Num; count++) ++ memcpy((u8*)(&(pTsCommonInfo->TClass[count])), (u8*)pTCLAS, sizeof(QOS_TCLAS)); ++ ++ pTsCommonInfo->TClasProc = TCLAS_Proc; ++ pTsCommonInfo->TClasNum = TCLAS_Num; ++} ++ ++ ++bool GetTs( ++ struct ieee80211_device* ieee, ++ PTS_COMMON_INFO *ppTS, ++ u8* Addr, ++ u8 TID, ++ TR_SELECT TxRxSelect, //Rx:1, Tx:0 ++ bool bAddNewTs ++ ) ++{ ++ u8 UP = 0; ++ // ++ // We do not build any TS for Broadcast or Multicast stream. ++ // So reject these kinds of search here. ++ // ++ if(is_broadcast_ether_addr(Addr) || is_multicast_ether_addr(Addr)) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "get TS for Broadcast or Multicast\n"); ++ return false; ++ } ++#if 0 ++ if(ieee->pStaQos->CurrentQosMode == QOS_DISABLE) ++ { UP = 0; } //only use one TS ++ else if(ieee->pStaQos->CurrentQosMode & QOS_WMM) ++ { ++#else ++ if (ieee->current_network.qos_data.supported == 0) ++ UP = 0; ++ else ++ { ++#endif ++ // In WMM case: we use 4 TID only ++ if (!IsACValid(TID)) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, " in %s(), TID(%d) is not valid\n", __FUNCTION__, TID); ++ return false; ++ } ++ ++ switch(TID) ++ { ++ case 0: ++ case 3: ++ UP = 0; ++ break; ++ ++ case 1: ++ case 2: ++ UP = 2; ++ break; ++ ++ case 4: ++ case 5: ++ UP = 5; ++ break; ++ ++ case 6: ++ case 7: ++ UP = 7; ++ break; ++ } ++ } ++ ++ *ppTS = SearchAdmitTRStream( ++ ieee, ++ Addr, ++ UP, ++ TxRxSelect); ++ if(*ppTS != NULL) ++ { ++ return true; ++ } ++ else ++ { ++ if(bAddNewTs == false) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_TS, "add new TS failed(tid:%d)\n", UP); ++ return false; ++ } ++ else ++ { ++ // ++ // Create a new Traffic stream for current Tx/Rx ++ // This is for EDCA and WMM to add a new TS. ++ // For HCCA or WMMSA, TS cannot be addmit without negotiation. ++ // ++ TSPEC_BODY TSpec; ++ PQOS_TSINFO pTSInfo = &TSpec.f.TSInfo; ++ struct list_head* pUnusedList = ++ (TxRxSelect == TX_DIR)? ++ (&ieee->Tx_TS_Unused_List): ++ (&ieee->Rx_TS_Unused_List); ++ ++ struct list_head* pAddmitList = ++ (TxRxSelect == TX_DIR)? ++ (&ieee->Tx_TS_Admit_List): ++ (&ieee->Rx_TS_Admit_List); ++ ++ DIRECTION_VALUE Dir = (ieee->iw_mode == IW_MODE_MASTER)? ++ ((TxRxSelect==TX_DIR)?DIR_DOWN:DIR_UP): ++ ((TxRxSelect==TX_DIR)?DIR_UP:DIR_DOWN); ++ IEEE80211_DEBUG(IEEE80211_DL_TS, "to add Ts\n"); ++ if(!list_empty(pUnusedList)) ++ { ++ (*ppTS) = list_entry(pUnusedList->next, TS_COMMON_INFO, List); ++ list_del_init(&(*ppTS)->List); ++ if(TxRxSelect==TX_DIR) ++ { ++ PTX_TS_RECORD tmp = container_of(*ppTS, TX_TS_RECORD, TsCommonInfo); ++ ResetTxTsEntry(tmp); ++ } ++ else{ ++ PRX_TS_RECORD tmp = container_of(*ppTS, RX_TS_RECORD, TsCommonInfo); ++ ResetRxTsEntry(tmp); ++ } ++ ++ IEEE80211_DEBUG(IEEE80211_DL_TS, "to init current TS, UP:%d, Dir:%d, addr:"MAC_FMT"\n", UP, Dir, MAC_ARG(Addr)); ++ // Prepare TS Info releated field ++ pTSInfo->field.ucTrafficType = 0; // Traffic type: WMM is reserved in this field ++ pTSInfo->field.ucTSID = UP; // TSID ++ pTSInfo->field.ucDirection = Dir; // Direction: if there is DirectLink, this need additional consideration. ++ pTSInfo->field.ucAccessPolicy = 1; // Access policy ++ pTSInfo->field.ucAggregation = 0; // Aggregation ++ pTSInfo->field.ucPSB = 0; // Aggregation ++ pTSInfo->field.ucUP = UP; // User priority ++ pTSInfo->field.ucTSInfoAckPolicy = 0; // Ack policy ++ pTSInfo->field.ucSchedule = 0; // Schedule ++ ++ MakeTSEntry(*ppTS, Addr, &TSpec, NULL, 0, 0); ++ AdmitTS(ieee, *ppTS, 0); ++ list_add_tail(&((*ppTS)->List), pAddmitList); ++ // if there is DirectLink, we need to do additional operation here!! ++ ++ return true; ++ } ++ else ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "in function %s() There is not enough TS record to be used!!", __FUNCTION__); ++ return false; ++ } ++ } ++ } ++} ++ ++void RemoveTsEntry( ++ struct ieee80211_device* ieee, ++ PTS_COMMON_INFO pTs, ++ TR_SELECT TxRxSelect ++ ) ++{ ++ //u32 flags = 0; ++ unsigned long flags = 0; ++ del_timer_sync(&pTs->SetupTimer); ++ del_timer_sync(&pTs->InactTimer); ++ TsInitDelBA(ieee, pTs, TxRxSelect); ++ ++ if(TxRxSelect == RX_DIR) ++ { ++//#ifdef TO_DO_LIST ++ PRX_REORDER_ENTRY pRxReorderEntry; ++ PRX_TS_RECORD pRxTS = (PRX_TS_RECORD)pTs; ++ if(timer_pending(&pRxTS->RxPktPendingTimer)) ++ del_timer_sync(&pRxTS->RxPktPendingTimer); ++ ++ while(!list_empty(&pRxTS->RxPendingPktList)) ++ { ++ // PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK); ++ spin_lock_irqsave(&(ieee->reorder_spinlock), flags); ++ //pRxReorderEntry = list_entry(&pRxTS->RxPendingPktList.prev,RX_REORDER_ENTRY,List); ++ pRxReorderEntry = (PRX_REORDER_ENTRY)list_entry(pRxTS->RxPendingPktList.prev,RX_REORDER_ENTRY,List); ++ list_del_init(&pRxReorderEntry->List); ++ { ++ int i = 0; ++ struct ieee80211_rxb * prxb = pRxReorderEntry->prxb; ++ if (unlikely(!prxb)) ++ { ++ spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags); ++ return; ++ } ++ for(i =0; i < prxb->nr_subframes; i++) { ++ dev_kfree_skb(prxb->subframes[i]); ++ } ++ kfree(prxb); ++ prxb = NULL; ++ } ++ list_add_tail(&pRxReorderEntry->List,&ieee->RxReorder_Unused_List); ++ //PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK); ++ spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags); ++ } ++ ++//#endif ++ } ++ else ++ { ++ PTX_TS_RECORD pTxTS = (PTX_TS_RECORD)pTs; ++ del_timer_sync(&pTxTS->TsAddBaTimer); ++ } ++} ++ ++void RemovePeerTS(struct ieee80211_device* ieee, u8* Addr) ++{ ++ PTS_COMMON_INFO pTS, pTmpTS; ++ printk("===========>RemovePeerTS,"MAC_FMT"\n", MAC_ARG(Addr)); ++#if 1 ++ list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Pending_List, List) ++ { ++ if (memcmp(pTS->Addr, Addr, 6) == 0) ++ { ++ RemoveTsEntry(ieee, pTS, TX_DIR); ++ list_del_init(&pTS->List); ++ list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List); ++ } ++ } ++ ++ list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Admit_List, List) ++ { ++ if (memcmp(pTS->Addr, Addr, 6) == 0) ++ { ++ printk("====>remove Tx_TS_admin_list\n"); ++ RemoveTsEntry(ieee, pTS, TX_DIR); ++ list_del_init(&pTS->List); ++ list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List); ++ } ++ } ++ ++ list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Pending_List, List) ++ { ++ if (memcmp(pTS->Addr, Addr, 6) == 0) ++ { ++ RemoveTsEntry(ieee, pTS, RX_DIR); ++ list_del_init(&pTS->List); ++ list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List); ++ } ++ } ++ ++ list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Admit_List, List) ++ { ++ if (memcmp(pTS->Addr, Addr, 6) == 0) ++ { ++ RemoveTsEntry(ieee, pTS, RX_DIR); ++ list_del_init(&pTS->List); ++ list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List); ++ } ++ } ++#endif ++} ++ ++void RemoveAllTS(struct ieee80211_device* ieee) ++{ ++ PTS_COMMON_INFO pTS, pTmpTS; ++#if 1 ++ list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Pending_List, List) ++ { ++ RemoveTsEntry(ieee, pTS, TX_DIR); ++ list_del_init(&pTS->List); ++ list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List); ++ } ++ ++ list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Admit_List, List) ++ { ++ RemoveTsEntry(ieee, pTS, TX_DIR); ++ list_del_init(&pTS->List); ++ list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List); ++ } ++ ++ list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Pending_List, List) ++ { ++ RemoveTsEntry(ieee, pTS, RX_DIR); ++ list_del_init(&pTS->List); ++ list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List); ++ } ++ ++ list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Admit_List, List) ++ { ++ RemoveTsEntry(ieee, pTS, RX_DIR); ++ list_del_init(&pTS->List); ++ list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List); ++ } ++#endif ++} ++ ++void TsStartAddBaProcess(struct ieee80211_device* ieee, PTX_TS_RECORD pTxTS) ++{ ++ if(pTxTS->bAddBaReqInProgress == false) ++ { ++ pTxTS->bAddBaReqInProgress = true; ++#if 1 ++ if(pTxTS->bAddBaReqDelayed) ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_BA, "TsStartAddBaProcess(): Delayed Start ADDBA after 60 sec!!\n"); ++ mod_timer(&pTxTS->TsAddBaTimer, jiffies + MSECS(TS_ADDBA_DELAY)); ++ } ++ else ++ { ++ IEEE80211_DEBUG(IEEE80211_DL_BA,"TsStartAddBaProcess(): Immediately Start ADDBA now!!\n"); ++ mod_timer(&pTxTS->TsAddBaTimer, jiffies+10); //set 10 ticks ++ } ++#endif ++ } ++ else ++ IEEE80211_DEBUG(IEEE80211_DL_ERR, "%s()==>BA timer is already added\n", __FUNCTION__); ++} ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++EXPORT_SYMBOL_NOVERS(RemovePeerTS); ++#else ++//EXPORT_SYMBOL(RemovePeerTS); ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl_crypto.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl_crypto.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/rtl_crypto.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,399 @@ ++/* ++ * Scatterlist Cryptographic API. ++ * ++ * Copyright (c) 2002 James Morris ++ * Copyright (c) 2002 David S. Miller (davem@redhat.com) ++ * ++ * Portions derived from Cryptoapi, by Alexander Kjeldaas ++ * and Nettle, by Niels M鰈ler. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at your option) ++ * any later version. ++ * ++ */ ++#ifndef _LINUX_CRYPTO_H ++#define _LINUX_CRYPTO_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define crypto_register_alg crypto_register_alg_rsl ++#define crypto_unregister_alg crypto_unregister_alg_rsl ++#define crypto_alloc_tfm crypto_alloc_tfm_rsl ++#define crypto_free_tfm crypto_free_tfm_rsl ++#define crypto_alg_available crypto_alg_available_rsl ++ ++/* ++ * Algorithm masks and types. ++ */ ++#define CRYPTO_ALG_TYPE_MASK 0x000000ff ++#define CRYPTO_ALG_TYPE_CIPHER 0x00000001 ++#define CRYPTO_ALG_TYPE_DIGEST 0x00000002 ++#define CRYPTO_ALG_TYPE_COMPRESS 0x00000004 ++ ++/* ++ * Transform masks and values (for crt_flags). ++ */ ++#define CRYPTO_TFM_MODE_MASK 0x000000ff ++#define CRYPTO_TFM_REQ_MASK 0x000fff00 ++#define CRYPTO_TFM_RES_MASK 0xfff00000 ++ ++#define CRYPTO_TFM_MODE_ECB 0x00000001 ++#define CRYPTO_TFM_MODE_CBC 0x00000002 ++#define CRYPTO_TFM_MODE_CFB 0x00000004 ++#define CRYPTO_TFM_MODE_CTR 0x00000008 ++ ++#define CRYPTO_TFM_REQ_WEAK_KEY 0x00000100 ++#define CRYPTO_TFM_RES_WEAK_KEY 0x00100000 ++#define CRYPTO_TFM_RES_BAD_KEY_LEN 0x00200000 ++#define CRYPTO_TFM_RES_BAD_KEY_SCHED 0x00400000 ++#define CRYPTO_TFM_RES_BAD_BLOCK_LEN 0x00800000 ++#define CRYPTO_TFM_RES_BAD_FLAGS 0x01000000 ++ ++/* ++ * Miscellaneous stuff. ++ */ ++#define CRYPTO_UNSPEC 0 ++#define CRYPTO_MAX_ALG_NAME 64 ++ ++struct scatterlist; ++ ++/* ++ * Algorithms: modular crypto algorithm implementations, managed ++ * via crypto_register_alg() and crypto_unregister_alg(). ++ */ ++struct cipher_alg { ++ unsigned int cia_min_keysize; ++ unsigned int cia_max_keysize; ++ int (*cia_setkey)(void *ctx, const u8 *key, ++ unsigned int keylen, u32 *flags); ++ void (*cia_encrypt)(void *ctx, u8 *dst, const u8 *src); ++ void (*cia_decrypt)(void *ctx, u8 *dst, const u8 *src); ++}; ++ ++struct digest_alg { ++ unsigned int dia_digestsize; ++ void (*dia_init)(void *ctx); ++ void (*dia_update)(void *ctx, const u8 *data, unsigned int len); ++ void (*dia_final)(void *ctx, u8 *out); ++ int (*dia_setkey)(void *ctx, const u8 *key, ++ unsigned int keylen, u32 *flags); ++}; ++ ++struct compress_alg { ++ int (*coa_init)(void *ctx); ++ void (*coa_exit)(void *ctx); ++ int (*coa_compress)(void *ctx, const u8 *src, unsigned int slen, ++ u8 *dst, unsigned int *dlen); ++ int (*coa_decompress)(void *ctx, const u8 *src, unsigned int slen, ++ u8 *dst, unsigned int *dlen); ++}; ++ ++#define cra_cipher cra_u.cipher ++#define cra_digest cra_u.digest ++#define cra_compress cra_u.compress ++ ++struct crypto_alg { ++ struct list_head cra_list; ++ u32 cra_flags; ++ unsigned int cra_blocksize; ++ unsigned int cra_ctxsize; ++ const char cra_name[CRYPTO_MAX_ALG_NAME]; ++ ++ union { ++ struct cipher_alg cipher; ++ struct digest_alg digest; ++ struct compress_alg compress; ++ } cra_u; ++ ++ struct module *cra_module; ++}; ++ ++/* ++ * Algorithm registration interface. ++ */ ++int crypto_register_alg(struct crypto_alg *alg); ++int crypto_unregister_alg(struct crypto_alg *alg); ++ ++/* ++ * Algorithm query interface. ++ */ ++int crypto_alg_available(const char *name, u32 flags); ++ ++/* ++ * Transforms: user-instantiated objects which encapsulate algorithms ++ * and core processing logic. Managed via crypto_alloc_tfm() and ++ * crypto_free_tfm(), as well as the various helpers below. ++ */ ++struct crypto_tfm; ++ ++struct cipher_tfm { ++ void *cit_iv; ++ unsigned int cit_ivsize; ++ u32 cit_mode; ++ int (*cit_setkey)(struct crypto_tfm *tfm, ++ const u8 *key, unsigned int keylen); ++ int (*cit_encrypt)(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes); ++ int (*cit_encrypt_iv)(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes, u8 *iv); ++ int (*cit_decrypt)(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes); ++ int (*cit_decrypt_iv)(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes, u8 *iv); ++ void (*cit_xor_block)(u8 *dst, const u8 *src); ++}; ++ ++struct digest_tfm { ++ void (*dit_init)(struct crypto_tfm *tfm); ++ void (*dit_update)(struct crypto_tfm *tfm, ++ struct scatterlist *sg, unsigned int nsg); ++ void (*dit_final)(struct crypto_tfm *tfm, u8 *out); ++ void (*dit_digest)(struct crypto_tfm *tfm, struct scatterlist *sg, ++ unsigned int nsg, u8 *out); ++ int (*dit_setkey)(struct crypto_tfm *tfm, ++ const u8 *key, unsigned int keylen); ++#ifdef CONFIG_CRYPTO_HMAC ++ void *dit_hmac_block; ++#endif ++}; ++ ++struct compress_tfm { ++ int (*cot_compress)(struct crypto_tfm *tfm, ++ const u8 *src, unsigned int slen, ++ u8 *dst, unsigned int *dlen); ++ int (*cot_decompress)(struct crypto_tfm *tfm, ++ const u8 *src, unsigned int slen, ++ u8 *dst, unsigned int *dlen); ++}; ++ ++#define crt_cipher crt_u.cipher ++#define crt_digest crt_u.digest ++#define crt_compress crt_u.compress ++ ++struct crypto_tfm { ++ ++ u32 crt_flags; ++ ++ union { ++ struct cipher_tfm cipher; ++ struct digest_tfm digest; ++ struct compress_tfm compress; ++ } crt_u; ++ ++ struct crypto_alg *__crt_alg; ++}; ++ ++/* ++ * Transform user interface. ++ */ ++ ++/* ++ * crypto_alloc_tfm() will first attempt to locate an already loaded algorithm. ++ * If that fails and the kernel supports dynamically loadable modules, it ++ * will then attempt to load a module of the same name or alias. A refcount ++ * is grabbed on the algorithm which is then associated with the new transform. ++ * ++ * crypto_free_tfm() frees up the transform and any associated resources, ++ * then drops the refcount on the associated algorithm. ++ */ ++struct crypto_tfm *crypto_alloc_tfm(const char *alg_name, u32 tfm_flags); ++void crypto_free_tfm(struct crypto_tfm *tfm); ++ ++/* ++ * Transform helpers which query the underlying algorithm. ++ */ ++static inline const char *crypto_tfm_alg_name(struct crypto_tfm *tfm) ++{ ++ return tfm->__crt_alg->cra_name; ++} ++ ++static inline const char *crypto_tfm_alg_modname(struct crypto_tfm *tfm) ++{ ++ struct crypto_alg *alg = tfm->__crt_alg; ++ ++ if (alg->cra_module) ++ return alg->cra_module->name; ++ else ++ return NULL; ++} ++ ++static inline u32 crypto_tfm_alg_type(struct crypto_tfm *tfm) ++{ ++ return tfm->__crt_alg->cra_flags & CRYPTO_ALG_TYPE_MASK; ++} ++ ++static inline unsigned int crypto_tfm_alg_min_keysize(struct crypto_tfm *tfm) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); ++ return tfm->__crt_alg->cra_cipher.cia_min_keysize; ++} ++ ++static inline unsigned int crypto_tfm_alg_max_keysize(struct crypto_tfm *tfm) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); ++ return tfm->__crt_alg->cra_cipher.cia_max_keysize; ++} ++ ++static inline unsigned int crypto_tfm_alg_ivsize(struct crypto_tfm *tfm) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); ++ return tfm->crt_cipher.cit_ivsize; ++} ++ ++static inline unsigned int crypto_tfm_alg_blocksize(struct crypto_tfm *tfm) ++{ ++ return tfm->__crt_alg->cra_blocksize; ++} ++ ++static inline unsigned int crypto_tfm_alg_digestsize(struct crypto_tfm *tfm) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); ++ return tfm->__crt_alg->cra_digest.dia_digestsize; ++} ++ ++/* ++ * API wrappers. ++ */ ++static inline void crypto_digest_init(struct crypto_tfm *tfm) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); ++ tfm->crt_digest.dit_init(tfm); ++} ++ ++static inline void crypto_digest_update(struct crypto_tfm *tfm, ++ struct scatterlist *sg, ++ unsigned int nsg) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); ++ tfm->crt_digest.dit_update(tfm, sg, nsg); ++} ++ ++static inline void crypto_digest_final(struct crypto_tfm *tfm, u8 *out) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); ++ tfm->crt_digest.dit_final(tfm, out); ++} ++ ++static inline void crypto_digest_digest(struct crypto_tfm *tfm, ++ struct scatterlist *sg, ++ unsigned int nsg, u8 *out) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); ++ tfm->crt_digest.dit_digest(tfm, sg, nsg, out); ++} ++ ++static inline int crypto_digest_setkey(struct crypto_tfm *tfm, ++ const u8 *key, unsigned int keylen) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); ++ if (tfm->crt_digest.dit_setkey == NULL) ++ return -ENOSYS; ++ return tfm->crt_digest.dit_setkey(tfm, key, keylen); ++} ++ ++static inline int crypto_cipher_setkey(struct crypto_tfm *tfm, ++ const u8 *key, unsigned int keylen) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); ++ return tfm->crt_cipher.cit_setkey(tfm, key, keylen); ++} ++ ++static inline int crypto_cipher_encrypt(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); ++ return tfm->crt_cipher.cit_encrypt(tfm, dst, src, nbytes); ++} ++ ++static inline int crypto_cipher_encrypt_iv(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes, u8 *iv) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); ++ BUG_ON(tfm->crt_cipher.cit_mode == CRYPTO_TFM_MODE_ECB); ++ return tfm->crt_cipher.cit_encrypt_iv(tfm, dst, src, nbytes, iv); ++} ++ ++static inline int crypto_cipher_decrypt(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); ++ return tfm->crt_cipher.cit_decrypt(tfm, dst, src, nbytes); ++} ++ ++static inline int crypto_cipher_decrypt_iv(struct crypto_tfm *tfm, ++ struct scatterlist *dst, ++ struct scatterlist *src, ++ unsigned int nbytes, u8 *iv) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); ++ BUG_ON(tfm->crt_cipher.cit_mode == CRYPTO_TFM_MODE_ECB); ++ return tfm->crt_cipher.cit_decrypt_iv(tfm, dst, src, nbytes, iv); ++} ++ ++static inline void crypto_cipher_set_iv(struct crypto_tfm *tfm, ++ const u8 *src, unsigned int len) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); ++ memcpy(tfm->crt_cipher.cit_iv, src, len); ++} ++ ++static inline void crypto_cipher_get_iv(struct crypto_tfm *tfm, ++ u8 *dst, unsigned int len) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); ++ memcpy(dst, tfm->crt_cipher.cit_iv, len); ++} ++ ++static inline int crypto_comp_compress(struct crypto_tfm *tfm, ++ const u8 *src, unsigned int slen, ++ u8 *dst, unsigned int *dlen) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_COMPRESS); ++ return tfm->crt_compress.cot_compress(tfm, src, slen, dst, dlen); ++} ++ ++static inline int crypto_comp_decompress(struct crypto_tfm *tfm, ++ const u8 *src, unsigned int slen, ++ u8 *dst, unsigned int *dlen) ++{ ++ BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_COMPRESS); ++ return tfm->crt_compress.cot_decompress(tfm, src, slen, dst, dlen); ++} ++ ++/* ++ * HMAC support. ++ */ ++#ifdef CONFIG_CRYPTO_HMAC ++void crypto_hmac_init(struct crypto_tfm *tfm, u8 *key, unsigned int *keylen); ++void crypto_hmac_update(struct crypto_tfm *tfm, ++ struct scatterlist *sg, unsigned int nsg); ++void crypto_hmac_final(struct crypto_tfm *tfm, u8 *key, ++ unsigned int *keylen, u8 *out); ++void crypto_hmac(struct crypto_tfm *tfm, u8 *key, unsigned int *keylen, ++ struct scatterlist *sg, unsigned int nsg, u8 *out); ++#endif /* CONFIG_CRYPTO_HMAC */ ++ ++#endif /* _LINUX_CRYPTO_H */ ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/scatterwalk.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/scatterwalk.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/scatterwalk.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,126 @@ ++/* ++ * Cryptographic API. ++ * ++ * Cipher operations. ++ * ++ * Copyright (c) 2002 James Morris ++ * 2002 Adam J. Richter ++ * 2004 Jean-Luc Cooke ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at your option) ++ * any later version. ++ * ++ */ ++#include "kmap_types.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include "internal.h" ++#include "scatterwalk.h" ++ ++enum km_type crypto_km_types[] = { ++ KM_USER0, ++ KM_USER1, ++ KM_SOFTIRQ0, ++ KM_SOFTIRQ1, ++}; ++ ++void *scatterwalk_whichbuf(struct scatter_walk *walk, unsigned int nbytes, void *scratch) ++{ ++ if (nbytes <= walk->len_this_page && ++ (((unsigned long)walk->data) & (PAGE_CACHE_SIZE - 1)) + nbytes <= ++ PAGE_CACHE_SIZE) ++ return walk->data; ++ else ++ return scratch; ++} ++ ++static void memcpy_dir(void *buf, void *sgdata, size_t nbytes, int out) ++{ ++ if (out) ++ memcpy(sgdata, buf, nbytes); ++ else ++ memcpy(buf, sgdata, nbytes); ++} ++ ++void scatterwalk_start(struct scatter_walk *walk, struct scatterlist *sg) ++{ ++ unsigned int rest_of_page; ++ ++ walk->sg = sg; ++ ++ walk->page = sg->page; ++ walk->len_this_segment = sg->length; ++ ++ rest_of_page = PAGE_CACHE_SIZE - (sg->offset & (PAGE_CACHE_SIZE - 1)); ++ walk->len_this_page = min(sg->length, rest_of_page); ++ walk->offset = sg->offset; ++} ++ ++void scatterwalk_map(struct scatter_walk *walk, int out) ++{ ++ walk->data = crypto_kmap(walk->page, out) + walk->offset; ++} ++ ++static void scatterwalk_pagedone(struct scatter_walk *walk, int out, ++ unsigned int more) ++{ ++ /* walk->data may be pointing the first byte of the next page; ++ however, we know we transfered at least one byte. So, ++ walk->data - 1 will be a virtual address in the mapped page. */ ++ ++ if (out) ++ flush_dcache_page(walk->page); ++ ++ if (more) { ++ walk->len_this_segment -= walk->len_this_page; ++ ++ if (walk->len_this_segment) { ++ walk->page++; ++ walk->len_this_page = min(walk->len_this_segment, ++ (unsigned)PAGE_CACHE_SIZE); ++ walk->offset = 0; ++ } ++ else ++ scatterwalk_start(walk, sg_next(walk->sg)); ++ } ++} ++ ++void scatterwalk_done(struct scatter_walk *walk, int out, int more) ++{ ++ crypto_kunmap(walk->data, out); ++ if (walk->len_this_page == 0 || !more) ++ scatterwalk_pagedone(walk, out, more); ++} ++ ++/* ++ * Do not call this unless the total length of all of the fragments ++ * has been verified as multiple of the block size. ++ */ ++int scatterwalk_copychunks(void *buf, struct scatter_walk *walk, ++ size_t nbytes, int out) ++{ ++ if (buf != walk->data) { ++ while (nbytes > walk->len_this_page) { ++ memcpy_dir(buf, walk->data, walk->len_this_page, out); ++ buf += walk->len_this_page; ++ nbytes -= walk->len_this_page; ++ ++ crypto_kunmap(walk->data, out); ++ scatterwalk_pagedone(walk, out, 1); ++ scatterwalk_map(walk, out); ++ } ++ ++ memcpy_dir(buf, walk->data, nbytes, out); ++ } ++ ++ walk->offset += nbytes; ++ walk->len_this_page -= nbytes; ++ walk->len_this_segment -= nbytes; ++ return 0; ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211/scatterwalk.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/scatterwalk.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211/scatterwalk.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,51 @@ ++/* ++ * Cryptographic API. ++ * ++ * Copyright (c) 2002 James Morris ++ * Copyright (c) 2002 Adam J. Richter ++ * Copyright (c) 2004 Jean-Luc Cooke ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at your option) ++ * any later version. ++ * ++ */ ++ ++#ifndef _CRYPTO_SCATTERWALK_H ++#define _CRYPTO_SCATTERWALK_H ++#include ++#include ++ ++struct scatter_walk { ++ struct scatterlist *sg; ++ struct page *page; ++ void *data; ++ unsigned int len_this_page; ++ unsigned int len_this_segment; ++ unsigned int offset; ++}; ++ ++/* Define sg_next is an inline routine now in case we want to change ++ scatterlist to a linked list later. */ ++static inline struct scatterlist *sg_next(struct scatterlist *sg) ++{ ++ return sg + 1; ++} ++ ++static inline int scatterwalk_samebuf(struct scatter_walk *walk_in, ++ struct scatter_walk *walk_out, ++ void *src_p, void *dst_p) ++{ ++ return walk_in->page == walk_out->page && ++ walk_in->offset == walk_out->offset && ++ walk_in->data == src_p && walk_out->data == dst_p; ++} ++ ++void *scatterwalk_whichbuf(struct scatter_walk *walk, unsigned int nbytes, void *scratch); ++void scatterwalk_start(struct scatter_walk *walk, struct scatterlist *sg); ++int scatterwalk_copychunks(void *buf, struct scatter_walk *walk, size_t nbytes, int out); ++void scatterwalk_map(struct scatter_walk *walk, int out); ++void scatterwalk_done(struct scatter_walk *walk, int out, int more); ++ ++#endif /* _CRYPTO_SCATTERWALK_H */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211_crypt.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211_crypt.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211_crypt.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,86 @@ ++/* ++ * Original code based on Host AP (software wireless LAN access point) driver ++ * for Intersil Prism2/2.5/3. ++ * ++ * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen ++ * ++ * Copyright (c) 2002-2003, Jouni Malinen ++ * ++ * Adaption to a generic IEEE 802.11 stack by James Ketrenos ++ * ++ * ++ * Copyright (c) 2004, Intel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. See README and COPYING for ++ * more details. ++ */ ++ ++/* ++ * This file defines the interface to the ieee80211 crypto module. ++ */ ++#ifndef IEEE80211_CRYPT_H ++#define IEEE80211_CRYPT_H ++ ++#include ++ ++struct ieee80211_crypto_ops { ++ const char *name; ++ ++ /* init new crypto context (e.g., allocate private data space, ++ * select IV, etc.); returns NULL on failure or pointer to allocated ++ * private data on success */ ++ void * (*init)(int keyidx); ++ ++ /* deinitialize crypto context and free allocated private data */ ++ void (*deinit)(void *priv); ++ ++ /* encrypt/decrypt return < 0 on error or >= 0 on success. The return ++ * value from decrypt_mpdu is passed as the keyidx value for ++ * decrypt_msdu. skb must have enough head and tail room for the ++ * encryption; if not, error will be returned; these functions are ++ * called for all MPDUs (i.e., fragments). ++ */ ++ int (*encrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv); ++ int (*decrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv); ++ ++ /* These functions are called for full MSDUs, i.e. full frames. ++ * These can be NULL if full MSDU operations are not needed. */ ++ int (*encrypt_msdu)(struct sk_buff *skb, int hdr_len, void *priv); ++ int (*decrypt_msdu)(struct sk_buff *skb, int keyidx, int hdr_len, ++ void *priv); ++ ++ int (*set_key)(void *key, int len, u8 *seq, void *priv); ++ int (*get_key)(void *key, int len, u8 *seq, void *priv); ++ ++ /* procfs handler for printing out key information and possible ++ * statistics */ ++ char * (*print_stats)(char *p, void *priv); ++ ++ /* maximum number of bytes added by encryption; encrypt buf is ++ * allocated with extra_prefix_len bytes, copy of in_buf, and ++ * extra_postfix_len; encrypt need not use all this space, but ++ * the result must start at the beginning of the buffer and correct ++ * length must be returned */ ++ int extra_prefix_len, extra_postfix_len; ++ ++ struct module *owner; ++}; ++ ++struct ieee80211_crypt_data { ++ struct list_head list; /* delayed deletion list */ ++ struct ieee80211_crypto_ops *ops; ++ void *priv; ++ atomic_t refcnt; ++}; ++ ++int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops); ++int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops); ++struct ieee80211_crypto_ops * ieee80211_get_crypto_ops(const char *name); ++void ieee80211_crypt_deinit_entries(struct ieee80211_device *, int); ++void ieee80211_crypt_deinit_handler(unsigned long); ++void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee, ++ struct ieee80211_crypt_data **crypt); ++ ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/ieee80211.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/ieee80211.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,2802 @@ ++/* ++ * Merged with mainline ieee80211.h in Aug 2004. Original ieee802_11 ++ * remains copyright by the original authors ++ * ++ * Portions of the merged code are based on Host AP (software wireless ++ * LAN access point) driver for Intersil Prism2/2.5/3. ++ * ++ * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen ++ * ++ * Copyright (c) 2002-2003, Jouni Malinen ++ * ++ * Adaption to a generic IEEE 802.11 stack by James Ketrenos ++ * ++ * Copyright (c) 2004, Intel Corporation ++ * ++ * Modified for Realtek's wi-fi cards by Andrea Merello ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. See README and COPYING for ++ * more details. ++ */ ++#ifndef IEEE80211_H ++#define IEEE80211_H ++#include /* ETH_ALEN */ ++#include /* ARRAY_SIZE */ ++#include ++#include ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++#include ++#else ++#include ++#include ++#endif ++#include ++#include ++ ++#include ++#include ++ ++#include "ieee80211/rtl819x_HT.h" ++#include "ieee80211/rtl819x_BA.h" ++#include "ieee80211/rtl819x_TS.h" ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) ++#ifndef bool ++typedef enum{false = 0, true} bool; ++#endif ++#endif ++ ++#ifndef IW_MODE_MONITOR ++#define IW_MODE_MONITOR 6 ++#endif ++ ++#ifndef IWEVCUSTOM ++#define IWEVCUSTOM 0x8c02 ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) ++#ifndef __bitwise ++#define __bitwise __attribute__((bitwise)) ++#endif ++typedef __u16 __le16; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27)) ++struct iw_spy_data{ ++ /* --- Standard spy support --- */ ++ int spy_number; ++ u_char spy_address[IW_MAX_SPY][ETH_ALEN]; ++ struct iw_quality spy_stat[IW_MAX_SPY]; ++ /* --- Enhanced spy support (event) */ ++ struct iw_quality spy_thr_low; /* Low threshold */ ++ struct iw_quality spy_thr_high; /* High threshold */ ++ u_char spy_thr_under[IW_MAX_SPY]; ++}; ++#endif ++#endif ++ ++#ifndef container_of ++/** ++ * container_of - cast a member of a structure out to the containing structure ++ * ++ * @ptr: the pointer to the member. ++ * @type: the type of the container struct this is embedded in. ++ * @member: the name of the member within the struct. ++ * ++ */ ++#define container_of(ptr, type, member) ({ \ ++ const typeof( ((type *)0)->member ) *__mptr = (ptr); \ ++ (type *)( (char *)__mptr - offsetof(type,member) );}) ++#endif ++ ++#define KEY_TYPE_NA 0x0 ++#define KEY_TYPE_WEP40 0x1 ++#define KEY_TYPE_TKIP 0x2 ++#define KEY_TYPE_CCMP 0x4 ++#define KEY_TYPE_WEP104 0x5 ++ ++/* added for rtl819x tx procedure */ ++#define MAX_QUEUE_SIZE 0x10 ++ ++// ++// 8190 queue mapping ++// ++#define BK_QUEUE 0 ++#define BE_QUEUE 1 ++#define VI_QUEUE 2 ++#define VO_QUEUE 3 ++#define HCCA_QUEUE 4 ++#define TXCMD_QUEUE 5 ++#define MGNT_QUEUE 6 ++#define HIGH_QUEUE 7 ++#define BEACON_QUEUE 8 ++ ++#define LOW_QUEUE BE_QUEUE ++#define NORMAL_QUEUE MGNT_QUEUE ++ ++//added by amy for ps ++#define SWRF_TIMEOUT 50 ++ ++//added by amy for LEAP related ++#define IE_CISCO_FLAG_POSITION 0x08 // Flag byte: byte 8, numbered from 0. ++#define SUPPORT_CKIP_MIC 0x08 // bit3 ++#define SUPPORT_CKIP_PK 0x10 // bit4 ++/* defined for skb cb field */ ++/* At most 28 byte */ ++typedef struct cb_desc { ++ /* Tx Desc Related flags (8-9) */ ++ u8 bLastIniPkt:1; ++ u8 bCmdOrInit:1; ++ u8 bFirstSeg:1; ++ u8 bLastSeg:1; ++ u8 bEncrypt:1; ++ u8 bTxDisableRateFallBack:1; ++ u8 bTxUseDriverAssingedRate:1; ++ u8 bHwSec:1; //indicate whether use Hw security. WB ++ ++ u8 reserved1; ++ ++ /* Tx Firmware Relaged flags (10-11)*/ ++ u8 bCTSEnable:1; ++ u8 bRTSEnable:1; ++ u8 bUseShortGI:1; ++ u8 bUseShortPreamble:1; ++ u8 bTxEnableFwCalcDur:1; ++ u8 bAMPDUEnable:1; ++ u8 bRTSSTBC:1; ++ u8 RTSSC:1; ++ ++ u8 bRTSBW:1; ++ u8 bPacketBW:1; ++ u8 bRTSUseShortPreamble:1; ++ u8 bRTSUseShortGI:1; ++ u8 bMulticast:1; ++ u8 bBroadcast:1; ++ //u8 reserved2:2; ++ u8 drv_agg_enable:1; ++ u8 reserved2:1; ++ ++ /* Tx Desc related element(12-19) */ ++ u8 rata_index; ++ u8 queue_index; ++ //u8 reserved3; ++ //u8 reserved4; ++ u16 txbuf_size; ++ //u8 reserved5; ++ u8 RATRIndex; ++ u8 reserved6; ++ u8 reserved7; ++ u8 reserved8; ++ ++ /* Tx firmware related element(20-27) */ ++ u8 data_rate; ++ u8 rts_rate; ++ u8 ampdu_factor; ++ u8 ampdu_density; ++ //u8 reserved9; ++ //u8 reserved10; ++ //u8 reserved11; ++ u8 DrvAggrNum; ++ u16 pkt_size; ++ u8 reserved12; ++}cb_desc, *pcb_desc; ++ ++/*--------------------------Define -------------------------------------------*/ ++#define MGN_1M 0x02 ++#define MGN_2M 0x04 ++#define MGN_5_5M 0x0b ++#define MGN_11M 0x16 ++ ++#define MGN_6M 0x0c ++#define MGN_9M 0x12 ++#define MGN_12M 0x18 ++#define MGN_18M 0x24 ++#define MGN_24M 0x30 ++#define MGN_36M 0x48 ++#define MGN_48M 0x60 ++#define MGN_54M 0x6c ++ ++#define MGN_MCS0 0x80 ++#define MGN_MCS1 0x81 ++#define MGN_MCS2 0x82 ++#define MGN_MCS3 0x83 ++#define MGN_MCS4 0x84 ++#define MGN_MCS5 0x85 ++#define MGN_MCS6 0x86 ++#define MGN_MCS7 0x87 ++#define MGN_MCS8 0x88 ++#define MGN_MCS9 0x89 ++#define MGN_MCS10 0x8a ++#define MGN_MCS11 0x8b ++#define MGN_MCS12 0x8c ++#define MGN_MCS13 0x8d ++#define MGN_MCS14 0x8e ++#define MGN_MCS15 0x8f ++ ++//---------------------------------------------------------------------------- ++// 802.11 Management frame Reason Code field ++//---------------------------------------------------------------------------- ++enum _ReasonCode{ ++ unspec_reason = 0x1, ++ auth_not_valid = 0x2, ++ deauth_lv_ss = 0x3, ++ inactivity = 0x4, ++ ap_overload = 0x5, ++ class2_err = 0x6, ++ class3_err = 0x7, ++ disas_lv_ss = 0x8, ++ asoc_not_auth = 0x9, ++ ++ //----MIC_CHECK ++ mic_failure = 0xe, ++ //----END MIC_CHECK ++ ++ // Reason code defined in 802.11i D10.0 p.28. ++ invalid_IE = 0x0d, ++ four_way_tmout = 0x0f, ++ two_way_tmout = 0x10, ++ IE_dismatch = 0x11, ++ invalid_Gcipher = 0x12, ++ invalid_Pcipher = 0x13, ++ invalid_AKMP = 0x14, ++ unsup_RSNIEver = 0x15, ++ invalid_RSNIE = 0x16, ++ auth_802_1x_fail= 0x17, ++ ciper_reject = 0x18, ++ ++ // Reason code defined in 7.3.1.7, 802.1e D13.0, p.42. Added by Annie, 2005-11-15. ++ QoS_unspec = 0x20, // 32 ++ QAP_bandwidth = 0x21, // 33 ++ poor_condition = 0x22, // 34 ++ no_facility = 0x23, // 35 ++ // Where is 36??? ++ req_declined = 0x25, // 37 ++ invalid_param = 0x26, // 38 ++ req_not_honored= 0x27, // 39 ++ TS_not_created = 0x2F, // 47 ++ DL_not_allowed = 0x30, // 48 ++ dest_not_exist = 0x31, // 49 ++ dest_not_QSTA = 0x32, // 50 ++}; ++ ++ ++ ++#define aSifsTime (((priv->ieee80211->current_network.mode == IEEE_A)||(priv->ieee80211->current_network.mode == IEEE_N_24G)||(priv->ieee80211->current_network.mode == IEEE_N_5G))? 16 : 10) ++ ++#define MGMT_QUEUE_NUM 5 ++ ++#define IEEE_CMD_SET_WPA_PARAM 1 ++#define IEEE_CMD_SET_WPA_IE 2 ++#define IEEE_CMD_SET_ENCRYPTION 3 ++#define IEEE_CMD_MLME 4 ++ ++#define IEEE_PARAM_WPA_ENABLED 1 ++#define IEEE_PARAM_TKIP_COUNTERMEASURES 2 ++#define IEEE_PARAM_DROP_UNENCRYPTED 3 ++#define IEEE_PARAM_PRIVACY_INVOKED 4 ++#define IEEE_PARAM_AUTH_ALGS 5 ++#define IEEE_PARAM_IEEE_802_1X 6 ++//It should consistent with the driver_XXX.c ++// David, 2006.9.26 ++#define IEEE_PARAM_WPAX_SELECT 7 ++//Added for notify the encryption type selection ++// David, 2006.9.26 ++#define IEEE_PROTO_WPA 1 ++#define IEEE_PROTO_RSN 2 ++//Added for notify the encryption type selection ++// David, 2006.9.26 ++#define IEEE_WPAX_USEGROUP 0 ++#define IEEE_WPAX_WEP40 1 ++#define IEEE_WPAX_TKIP 2 ++#define IEEE_WPAX_WRAP 3 ++#define IEEE_WPAX_CCMP 4 ++#define IEEE_WPAX_WEP104 5 ++ ++#define IEEE_KEY_MGMT_IEEE8021X 1 ++#define IEEE_KEY_MGMT_PSK 2 ++ ++#define IEEE_MLME_STA_DEAUTH 1 ++#define IEEE_MLME_STA_DISASSOC 2 ++ ++ ++#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2 ++#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3 ++#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4 ++#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5 ++#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6 ++#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7 ++ ++ ++#define IEEE_CRYPT_ALG_NAME_LEN 16 ++ ++#define MAX_IE_LEN 0xff ++ ++// added for kernel conflict ++#define ieee80211_crypt_deinit_entries ieee80211_crypt_deinit_entries_rsl ++#define ieee80211_crypt_deinit_handler ieee80211_crypt_deinit_handler_rsl ++#define ieee80211_crypt_delayed_deinit ieee80211_crypt_delayed_deinit_rsl ++#define ieee80211_register_crypto_ops ieee80211_register_crypto_ops_rsl ++#define ieee80211_unregister_crypto_ops ieee80211_unregister_crypto_ops_rsl ++#define ieee80211_get_crypto_ops ieee80211_get_crypto_ops_rsl ++ ++#define ieee80211_ccmp_null ieee80211_ccmp_null_rsl ++ ++#define ieee80211_tkip_null ieee80211_tkip_null_rsl ++ ++#define ieee80211_wep_null ieee80211_wep_null_rsl ++ ++#define free_ieee80211 free_ieee80211_rsl ++#define alloc_ieee80211 alloc_ieee80211_rsl ++ ++#define ieee80211_rx ieee80211_rx_rsl ++#define ieee80211_rx_mgt ieee80211_rx_mgt_rsl ++ ++#define ieee80211_get_beacon ieee80211_get_beacon_rsl ++#define ieee80211_wake_queue ieee80211_wake_queue_rsl ++#define ieee80211_stop_queue ieee80211_stop_queue_rsl ++#define ieee80211_reset_queue ieee80211_reset_queue_rsl ++#define ieee80211_softmac_stop_protocol ieee80211_softmac_stop_protocol_rsl ++#define ieee80211_softmac_start_protocol ieee80211_softmac_start_protocol_rsl ++#define ieee80211_is_shortslot ieee80211_is_shortslot_rsl ++#define ieee80211_is_54g ieee80211_is_54g_rsl ++#define ieee80211_wpa_supplicant_ioctl ieee80211_wpa_supplicant_ioctl_rsl ++#define ieee80211_ps_tx_ack ieee80211_ps_tx_ack_rsl ++#define ieee80211_softmac_xmit ieee80211_softmac_xmit_rsl ++#define ieee80211_stop_send_beacons ieee80211_stop_send_beacons_rsl ++#define notify_wx_assoc_event notify_wx_assoc_event_rsl ++#define SendDisassociation SendDisassociation_rsl ++#define ieee80211_disassociate ieee80211_disassociate_rsl ++#define ieee80211_start_send_beacons ieee80211_start_send_beacons_rsl ++#define ieee80211_stop_scan ieee80211_stop_scan_rsl ++#define ieee80211_send_probe_requests ieee80211_send_probe_requests_rsl ++#define ieee80211_softmac_scan_syncro ieee80211_softmac_scan_syncro_rsl ++#define ieee80211_start_scan_syncro ieee80211_start_scan_syncro_rsl ++ ++#define ieee80211_wx_get_essid ieee80211_wx_get_essid_rsl ++#define ieee80211_wx_set_essid ieee80211_wx_set_essid_rsl ++#define ieee80211_wx_set_rate ieee80211_wx_set_rate_rsl ++#define ieee80211_wx_get_rate ieee80211_wx_get_rate_rsl ++#define ieee80211_wx_set_wap ieee80211_wx_set_wap_rsl ++#define ieee80211_wx_get_wap ieee80211_wx_get_wap_rsl ++#define ieee80211_wx_set_mode ieee80211_wx_set_mode_rsl ++#define ieee80211_wx_get_mode ieee80211_wx_get_mode_rsl ++#define ieee80211_wx_set_scan ieee80211_wx_set_scan_rsl ++#define ieee80211_wx_get_freq ieee80211_wx_get_freq_rsl ++#define ieee80211_wx_set_freq ieee80211_wx_set_freq_rsl ++#define ieee80211_wx_set_rawtx ieee80211_wx_set_rawtx_rsl ++#define ieee80211_wx_get_name ieee80211_wx_get_name_rsl ++#define ieee80211_wx_set_power ieee80211_wx_set_power_rsl ++#define ieee80211_wx_get_power ieee80211_wx_get_power_rsl ++#define ieee80211_wlan_frequencies ieee80211_wlan_frequencies_rsl ++#define ieee80211_wx_set_rts ieee80211_wx_set_rts_rsl ++#define ieee80211_wx_get_rts ieee80211_wx_get_rts_rsl ++ ++#define ieee80211_txb_free ieee80211_txb_free_rsl ++ ++#define ieee80211_wx_set_gen_ie ieee80211_wx_set_gen_ie_rsl ++#define ieee80211_wx_get_scan ieee80211_wx_get_scan_rsl ++#define ieee80211_wx_set_encode ieee80211_wx_set_encode_rsl ++#define ieee80211_wx_get_encode ieee80211_wx_get_encode_rsl ++#if WIRELESS_EXT >= 18 ++#define ieee80211_wx_set_mlme ieee80211_wx_set_mlme_rsl ++#define ieee80211_wx_set_auth ieee80211_wx_set_auth_rsl ++#define ieee80211_wx_set_encode_ext ieee80211_wx_set_encode_ext_rsl ++#define ieee80211_wx_get_encode_ext ieee80211_wx_get_encode_ext_rsl ++#endif ++ ++ ++typedef struct ieee_param { ++ u32 cmd; ++ u8 sta_addr[ETH_ALEN]; ++ union { ++ struct { ++ u8 name; ++ u32 value; ++ } wpa_param; ++ struct { ++ u32 len; ++ u8 reserved[32]; ++ u8 data[0]; ++ } wpa_ie; ++ struct{ ++ int command; ++ int reason_code; ++ } mlme; ++ struct { ++ u8 alg[IEEE_CRYPT_ALG_NAME_LEN]; ++ u8 set_tx; ++ u32 err; ++ u8 idx; ++ u8 seq[8]; /* sequence counter (set: RX, get: TX) */ ++ u16 key_len; ++ u8 key[0]; ++ } crypt; ++ } u; ++}ieee_param; ++ ++ ++#if WIRELESS_EXT < 17 ++#define IW_QUAL_QUAL_INVALID 0x10 ++#define IW_QUAL_LEVEL_INVALID 0x20 ++#define IW_QUAL_NOISE_INVALID 0x40 ++#define IW_QUAL_QUAL_UPDATED 0x1 ++#define IW_QUAL_LEVEL_UPDATED 0x2 ++#define IW_QUAL_NOISE_UPDATED 0x4 ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) ++static inline void tq_init(struct tq_struct * task, void(*func)(void *), void *data) ++{ ++ task->routine = func; ++ task->data = data; ++ //task->next = NULL; ++ INIT_LIST_HEAD(&task->list); ++ task->sync = 0; ++} ++#endif ++ ++// linux under 2.6.9 release may not support it, so modify it for common use ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)) ++//#define MSECS(t) (1000 * ((t) / HZ) + 1000 * ((t) % HZ) / HZ) ++#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000) ++static inline unsigned long msleep_interruptible_rsl(unsigned int msecs) ++{ ++ unsigned long timeout = MSECS(msecs) + 1; ++ ++ while (timeout) { ++ set_current_state(TASK_INTERRUPTIBLE); ++ timeout = schedule_timeout(timeout); ++ } ++ return timeout; ++} ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,31)) ++static inline void msleep(unsigned int msecs) ++{ ++ unsigned long timeout = MSECS(msecs) + 1; ++ ++ while (timeout) { ++ set_current_state(TASK_UNINTERRUPTIBLE); ++ timeout = schedule_timeout(timeout); ++ } ++} ++#endif ++#else ++#define MSECS(t) msecs_to_jiffies(t) ++#define msleep_interruptible_rsl msleep_interruptible ++#endif ++ ++#define IEEE80211_DATA_LEN 2304 ++/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section ++ 6.2.1.1.2. ++ ++ The figure in section 7.1.2 suggests a body size of up to 2312 ++ bytes is allowed, which is a bit confusing, I suspect this ++ represents the 2304 bytes of real data, plus a possible 8 bytes of ++ WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */ ++#define IEEE80211_1ADDR_LEN 10 ++#define IEEE80211_2ADDR_LEN 16 ++#define IEEE80211_3ADDR_LEN 24 ++#define IEEE80211_4ADDR_LEN 30 ++#define IEEE80211_FCS_LEN 4 ++#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) ++#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) ++#define IEEE80211_MGMT_HDR_LEN 24 ++#define IEEE80211_DATA_HDR3_LEN 24 ++#define IEEE80211_DATA_HDR4_LEN 30 ++ ++#define MIN_FRAG_THRESHOLD 256U ++#define MAX_FRAG_THRESHOLD 2346U ++ ++ ++/* Frame control field constants */ ++#define IEEE80211_FCTL_VERS 0x0003 ++#define IEEE80211_FCTL_FTYPE 0x000c ++#define IEEE80211_FCTL_STYPE 0x00f0 ++#define IEEE80211_FCTL_FRAMETYPE 0x00fc ++#define IEEE80211_FCTL_TODS 0x0100 ++#define IEEE80211_FCTL_FROMDS 0x0200 ++#define IEEE80211_FCTL_DSTODS 0x0300 //added by david ++#define IEEE80211_FCTL_MOREFRAGS 0x0400 ++#define IEEE80211_FCTL_RETRY 0x0800 ++#define IEEE80211_FCTL_PM 0x1000 ++#define IEEE80211_FCTL_MOREDATA 0x2000 ++#define IEEE80211_FCTL_WEP 0x4000 ++#define IEEE80211_FCTL_ORDER 0x8000 ++ ++#define IEEE80211_FTYPE_MGMT 0x0000 ++#define IEEE80211_FTYPE_CTL 0x0004 ++#define IEEE80211_FTYPE_DATA 0x0008 ++ ++/* management */ ++#define IEEE80211_STYPE_ASSOC_REQ 0x0000 ++#define IEEE80211_STYPE_ASSOC_RESP 0x0010 ++#define IEEE80211_STYPE_REASSOC_REQ 0x0020 ++#define IEEE80211_STYPE_REASSOC_RESP 0x0030 ++#define IEEE80211_STYPE_PROBE_REQ 0x0040 ++#define IEEE80211_STYPE_PROBE_RESP 0x0050 ++#define IEEE80211_STYPE_BEACON 0x0080 ++#define IEEE80211_STYPE_ATIM 0x0090 ++#define IEEE80211_STYPE_DISASSOC 0x00A0 ++#define IEEE80211_STYPE_AUTH 0x00B0 ++#define IEEE80211_STYPE_DEAUTH 0x00C0 ++#define IEEE80211_STYPE_MANAGE_ACT 0x00D0 ++ ++/* control */ ++#define IEEE80211_STYPE_PSPOLL 0x00A0 ++#define IEEE80211_STYPE_RTS 0x00B0 ++#define IEEE80211_STYPE_CTS 0x00C0 ++#define IEEE80211_STYPE_ACK 0x00D0 ++#define IEEE80211_STYPE_CFEND 0x00E0 ++#define IEEE80211_STYPE_CFENDACK 0x00F0 ++#define IEEE80211_STYPE_BLOCKACK 0x0094 ++ ++/* data */ ++#define IEEE80211_STYPE_DATA 0x0000 ++#define IEEE80211_STYPE_DATA_CFACK 0x0010 ++#define IEEE80211_STYPE_DATA_CFPOLL 0x0020 ++#define IEEE80211_STYPE_DATA_CFACKPOLL 0x0030 ++#define IEEE80211_STYPE_NULLFUNC 0x0040 ++#define IEEE80211_STYPE_CFACK 0x0050 ++#define IEEE80211_STYPE_CFPOLL 0x0060 ++#define IEEE80211_STYPE_CFACKPOLL 0x0070 ++#define IEEE80211_STYPE_QOS_DATA 0x0080 //added for WMM 2006/8/2 ++#define IEEE80211_STYPE_QOS_NULL 0x00C0 ++ ++#define IEEE80211_SCTL_FRAG 0x000F ++#define IEEE80211_SCTL_SEQ 0xFFF0 ++ ++/* QOS control */ ++#define IEEE80211_QCTL_TID 0x000F ++ ++#define FC_QOS_BIT BIT7 ++#define IsDataFrame(pdu) ( ((pdu[0] & 0x0C)==0x08) ? true : false ) ++#define IsLegacyDataFrame(pdu) (IsDataFrame(pdu) && (!(pdu[0]&FC_QOS_BIT)) ) ++//added by wb. Is this right? ++#define IsQoSDataFrame(pframe) ((*(u16*)pframe&(IEEE80211_STYPE_QOS_DATA|IEEE80211_FTYPE_DATA)) == (IEEE80211_STYPE_QOS_DATA|IEEE80211_FTYPE_DATA)) ++#define Frame_Order(pframe) (*(u16*)pframe&IEEE80211_FCTL_ORDER) ++#define SN_LESS(a, b) (((a-b)&0x800)!=0) ++#define SN_EQUAL(a, b) (a == b) ++#define MAX_DEV_ADDR_SIZE 8 ++typedef enum _ACT_CATEGORY{ ++ ACT_CAT_QOS = 1, ++ ACT_CAT_DLS = 2, ++ ACT_CAT_BA = 3, ++ ACT_CAT_HT = 7, ++ ACT_CAT_WMM = 17, ++} ACT_CATEGORY, *PACT_CATEGORY; ++ ++typedef enum _TS_ACTION{ ++ ACT_ADDTSREQ = 0, ++ ACT_ADDTSRSP = 1, ++ ACT_DELTS = 2, ++ ACT_SCHEDULE = 3, ++} TS_ACTION, *PTS_ACTION; ++ ++typedef enum _BA_ACTION{ ++ ACT_ADDBAREQ = 0, ++ ACT_ADDBARSP = 1, ++ ACT_DELBA = 2, ++} BA_ACTION, *PBA_ACTION; ++ ++typedef enum _InitialGainOpType{ ++ IG_Backup=0, ++ IG_Restore, ++ IG_Max ++}InitialGainOpType; ++ ++/* debug macros */ ++#define CONFIG_IEEE80211_DEBUG ++#ifdef CONFIG_IEEE80211_DEBUG ++extern u32 ieee80211_debug_level; ++#define IEEE80211_DEBUG(level, fmt, args...) \ ++do { if (ieee80211_debug_level & (level)) \ ++ printk(KERN_DEBUG "ieee80211: " fmt, ## args); } while (0) ++//wb added to debug out data buf ++//if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA ++#define IEEE80211_DEBUG_DATA(level, data, datalen) \ ++ do{ if ((ieee80211_debug_level & (level)) == (level)) \ ++ { \ ++ int i; \ ++ u8* pdata = (u8*) data; \ ++ printk(KERN_DEBUG "ieee80211: %s()\n", __FUNCTION__); \ ++ for(i=0; i<(int)(datalen); i++) \ ++ { \ ++ printk("%2x ", pdata[i]); \ ++ if ((i+1)%16 == 0) printk("\n"); \ ++ } \ ++ printk("\n"); \ ++ } \ ++ } while (0) ++#else ++#define IEEE80211_DEBUG(level, fmt, args...) do {} while (0) ++#define IEEE80211_DEBUG_DATA(level, data, datalen) do {} while(0) ++#endif /* CONFIG_IEEE80211_DEBUG */ ++ ++/* debug macros not dependent on CONFIG_IEEE80211_DEBUG */ ++ ++#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" ++#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] ++ ++/* ++ * To use the debug system; ++ * ++ * If you are defining a new debug classification, simply add it to the #define ++ * list here in the form of: ++ * ++ * #define IEEE80211_DL_xxxx VALUE ++ * ++ * shifting value to the left one bit from the previous entry. xxxx should be ++ * the name of the classification (for example, WEP) ++ * ++ * You then need to either add a IEEE80211_xxxx_DEBUG() macro definition for your ++ * classification, or use IEEE80211_DEBUG(IEEE80211_DL_xxxx, ...) whenever you want ++ * to send output to that classification. ++ * ++ * To add your debug level to the list of levels seen when you perform ++ * ++ * % cat /proc/net/ipw/debug_level ++ * ++ * you simply need to add your entry to the ipw_debug_levels array. ++ * ++ * If you do not see debug_level in /proc/net/ipw then you do not have ++ * CONFIG_IEEE80211_DEBUG defined in your kernel configuration ++ * ++ */ ++ ++#define IEEE80211_DL_INFO (1<<0) ++#define IEEE80211_DL_WX (1<<1) ++#define IEEE80211_DL_SCAN (1<<2) ++#define IEEE80211_DL_STATE (1<<3) ++#define IEEE80211_DL_MGMT (1<<4) ++#define IEEE80211_DL_FRAG (1<<5) ++#define IEEE80211_DL_EAP (1<<6) ++#define IEEE80211_DL_DROP (1<<7) ++ ++#define IEEE80211_DL_TX (1<<8) ++#define IEEE80211_DL_RX (1<<9) ++ ++#define IEEE80211_DL_HT (1<<10) //HT ++#define IEEE80211_DL_BA (1<<11) //ba ++#define IEEE80211_DL_TS (1<<12) //TS ++#define IEEE80211_DL_QOS (1<<13) ++#define IEEE80211_DL_REORDER (1<<14) ++#define IEEE80211_DL_IOT (1<<15) ++#define IEEE80211_DL_IPS (1<<16) ++#define IEEE80211_DL_TRACE (1<<29) //trace function, need to user net_ratelimit() together in order not to print too much to the screen ++#define IEEE80211_DL_DATA (1<<30) //use this flag to control whether print data buf out. ++#define IEEE80211_DL_ERR (1<<31) //always open ++#define IEEE80211_ERROR(f, a...) printk(KERN_ERR "ieee80211: " f, ## a) ++#define IEEE80211_WARNING(f, a...) printk(KERN_WARNING "ieee80211: " f, ## a) ++#define IEEE80211_DEBUG_INFO(f, a...) IEEE80211_DEBUG(IEEE80211_DL_INFO, f, ## a) ++ ++#define IEEE80211_DEBUG_WX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_WX, f, ## a) ++#define IEEE80211_DEBUG_SCAN(f, a...) IEEE80211_DEBUG(IEEE80211_DL_SCAN, f, ## a) ++#define IEEE80211_DEBUG_STATE(f, a...) IEEE80211_DEBUG(IEEE80211_DL_STATE, f, ## a) ++#define IEEE80211_DEBUG_MGMT(f, a...) IEEE80211_DEBUG(IEEE80211_DL_MGMT, f, ## a) ++#define IEEE80211_DEBUG_FRAG(f, a...) IEEE80211_DEBUG(IEEE80211_DL_FRAG, f, ## a) ++#define IEEE80211_DEBUG_EAP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_EAP, f, ## a) ++#define IEEE80211_DEBUG_DROP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_DROP, f, ## a) ++#define IEEE80211_DEBUG_TX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_TX, f, ## a) ++#define IEEE80211_DEBUG_RX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_RX, f, ## a) ++#define IEEE80211_DEBUG_QOS(f, a...) IEEE80211_DEBUG(IEEE80211_DL_QOS, f, ## a) ++ ++#ifdef CONFIG_IEEE80211_DEBUG ++/* Added by Annie, 2005-11-22. */ ++#define MAX_STR_LEN 64 ++/* I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.*/ ++#define PRINTABLE(_ch) (_ch>'!' && _ch<'~') ++#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) \ ++ if((_Comp) & level) \ ++ { \ ++ int __i; \ ++ u8 buffer[MAX_STR_LEN]; \ ++ int length = (_Len\n", _Len, buffer); \ ++ } ++#else ++#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) do {} while (0) ++#endif ++ ++#include ++#include /* ARPHRD_ETHER */ ++ ++#ifndef WIRELESS_SPY ++#define WIRELESS_SPY // enable iwspy support ++#endif ++#include // new driver API ++ ++#ifndef ETH_P_PAE ++#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ ++#endif /* ETH_P_PAE */ ++ ++#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */ ++ ++#ifndef ETH_P_80211_RAW ++#define ETH_P_80211_RAW (ETH_P_ECONET + 1) ++#endif ++ ++/* IEEE 802.11 defines */ ++ ++#define P80211_OUI_LEN 3 ++ ++struct ieee80211_snap_hdr { ++ ++ u8 dsap; /* always 0xAA */ ++ u8 ssap; /* always 0xAA */ ++ u8 ctrl; /* always 0x03 */ ++ u8 oui[P80211_OUI_LEN]; /* organizational universal id */ ++ ++} __attribute__ ((packed)); ++ ++#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) ++ ++#define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS) ++#define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE) ++#define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE) ++ ++#define WLAN_FC_GET_FRAMETYPE(fc) ((fc) & IEEE80211_FCTL_FRAMETYPE) ++#define WLAN_GET_SEQ_FRAG(seq) ((seq) & IEEE80211_SCTL_FRAG) ++#define WLAN_GET_SEQ_SEQ(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) ++ ++/* Authentication algorithms */ ++#define WLAN_AUTH_OPEN 0 ++#define WLAN_AUTH_SHARED_KEY 1 ++#define WLAN_AUTH_LEAP 2 ++ ++#define WLAN_AUTH_CHALLENGE_LEN 128 ++ ++#define WLAN_CAPABILITY_BSS (1<<0) ++#define WLAN_CAPABILITY_IBSS (1<<1) ++#define WLAN_CAPABILITY_CF_POLLABLE (1<<2) ++#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3) ++#define WLAN_CAPABILITY_PRIVACY (1<<4) ++#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5) ++#define WLAN_CAPABILITY_PBCC (1<<6) ++#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7) ++#define WLAN_CAPABILITY_SPECTRUM_MGMT (1<<8) ++#define WLAN_CAPABILITY_QOS (1<<9) ++#define WLAN_CAPABILITY_SHORT_SLOT (1<<10) ++#define WLAN_CAPABILITY_DSSS_OFDM (1<<13) ++ ++/* 802.11g ERP information element */ ++#define WLAN_ERP_NON_ERP_PRESENT (1<<0) ++#define WLAN_ERP_USE_PROTECTION (1<<1) ++#define WLAN_ERP_BARKER_PREAMBLE (1<<2) ++ ++/* Status codes */ ++enum ieee80211_statuscode { ++ WLAN_STATUS_SUCCESS = 0, ++ WLAN_STATUS_UNSPECIFIED_FAILURE = 1, ++ WLAN_STATUS_CAPS_UNSUPPORTED = 10, ++ WLAN_STATUS_REASSOC_NO_ASSOC = 11, ++ WLAN_STATUS_ASSOC_DENIED_UNSPEC = 12, ++ WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG = 13, ++ WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION = 14, ++ WLAN_STATUS_CHALLENGE_FAIL = 15, ++ WLAN_STATUS_AUTH_TIMEOUT = 16, ++ WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA = 17, ++ WLAN_STATUS_ASSOC_DENIED_RATES = 18, ++ /* 802.11b */ ++ WLAN_STATUS_ASSOC_DENIED_NOSHORTPREAMBLE = 19, ++ WLAN_STATUS_ASSOC_DENIED_NOPBCC = 20, ++ WLAN_STATUS_ASSOC_DENIED_NOAGILITY = 21, ++ /* 802.11h */ ++ WLAN_STATUS_ASSOC_DENIED_NOSPECTRUM = 22, ++ WLAN_STATUS_ASSOC_REJECTED_BAD_POWER = 23, ++ WLAN_STATUS_ASSOC_REJECTED_BAD_SUPP_CHAN = 24, ++ /* 802.11g */ ++ WLAN_STATUS_ASSOC_DENIED_NOSHORTTIME = 25, ++ WLAN_STATUS_ASSOC_DENIED_NODSSSOFDM = 26, ++ /* 802.11i */ ++ WLAN_STATUS_INVALID_IE = 40, ++ WLAN_STATUS_INVALID_GROUP_CIPHER = 41, ++ WLAN_STATUS_INVALID_PAIRWISE_CIPHER = 42, ++ WLAN_STATUS_INVALID_AKMP = 43, ++ WLAN_STATUS_UNSUPP_RSN_VERSION = 44, ++ WLAN_STATUS_INVALID_RSN_IE_CAP = 45, ++ WLAN_STATUS_CIPHER_SUITE_REJECTED = 46, ++}; ++ ++/* Reason codes */ ++enum ieee80211_reasoncode { ++ WLAN_REASON_UNSPECIFIED = 1, ++ WLAN_REASON_PREV_AUTH_NOT_VALID = 2, ++ WLAN_REASON_DEAUTH_LEAVING = 3, ++ WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY = 4, ++ WLAN_REASON_DISASSOC_AP_BUSY = 5, ++ WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA = 6, ++ WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA = 7, ++ WLAN_REASON_DISASSOC_STA_HAS_LEFT = 8, ++ WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH = 9, ++ /* 802.11h */ ++ WLAN_REASON_DISASSOC_BAD_POWER = 10, ++ WLAN_REASON_DISASSOC_BAD_SUPP_CHAN = 11, ++ /* 802.11i */ ++ WLAN_REASON_INVALID_IE = 13, ++ WLAN_REASON_MIC_FAILURE = 14, ++ WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT = 15, ++ WLAN_REASON_GROUP_KEY_HANDSHAKE_TIMEOUT = 16, ++ WLAN_REASON_IE_DIFFERENT = 17, ++ WLAN_REASON_INVALID_GROUP_CIPHER = 18, ++ WLAN_REASON_INVALID_PAIRWISE_CIPHER = 19, ++ WLAN_REASON_INVALID_AKMP = 20, ++ WLAN_REASON_UNSUPP_RSN_VERSION = 21, ++ WLAN_REASON_INVALID_RSN_IE_CAP = 22, ++ WLAN_REASON_IEEE8021X_FAILED = 23, ++ WLAN_REASON_CIPHER_SUITE_REJECTED = 24, ++}; ++ ++#define IEEE80211_STATMASK_SIGNAL (1<<0) ++#define IEEE80211_STATMASK_RSSI (1<<1) ++#define IEEE80211_STATMASK_NOISE (1<<2) ++#define IEEE80211_STATMASK_RATE (1<<3) ++#define IEEE80211_STATMASK_WEMASK 0x7 ++ ++#define IEEE80211_CCK_MODULATION (1<<0) ++#define IEEE80211_OFDM_MODULATION (1<<1) ++ ++#define IEEE80211_24GHZ_BAND (1<<0) ++#define IEEE80211_52GHZ_BAND (1<<1) ++ ++#define IEEE80211_CCK_RATE_LEN 4 ++#define IEEE80211_CCK_RATE_1MB 0x02 ++#define IEEE80211_CCK_RATE_2MB 0x04 ++#define IEEE80211_CCK_RATE_5MB 0x0B ++#define IEEE80211_CCK_RATE_11MB 0x16 ++#define IEEE80211_OFDM_RATE_LEN 8 ++#define IEEE80211_OFDM_RATE_6MB 0x0C ++#define IEEE80211_OFDM_RATE_9MB 0x12 ++#define IEEE80211_OFDM_RATE_12MB 0x18 ++#define IEEE80211_OFDM_RATE_18MB 0x24 ++#define IEEE80211_OFDM_RATE_24MB 0x30 ++#define IEEE80211_OFDM_RATE_36MB 0x48 ++#define IEEE80211_OFDM_RATE_48MB 0x60 ++#define IEEE80211_OFDM_RATE_54MB 0x6C ++#define IEEE80211_BASIC_RATE_MASK 0x80 ++ ++#define IEEE80211_CCK_RATE_1MB_MASK (1<<0) ++#define IEEE80211_CCK_RATE_2MB_MASK (1<<1) ++#define IEEE80211_CCK_RATE_5MB_MASK (1<<2) ++#define IEEE80211_CCK_RATE_11MB_MASK (1<<3) ++#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4) ++#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5) ++#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6) ++#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7) ++#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8) ++#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9) ++#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10) ++#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11) ++ ++#define IEEE80211_CCK_RATES_MASK 0x0000000F ++#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \ ++ IEEE80211_CCK_RATE_2MB_MASK) ++#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \ ++ IEEE80211_CCK_RATE_5MB_MASK | \ ++ IEEE80211_CCK_RATE_11MB_MASK) ++ ++#define IEEE80211_OFDM_RATES_MASK 0x00000FF0 ++#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \ ++ IEEE80211_OFDM_RATE_12MB_MASK | \ ++ IEEE80211_OFDM_RATE_24MB_MASK) ++#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \ ++ IEEE80211_OFDM_RATE_9MB_MASK | \ ++ IEEE80211_OFDM_RATE_18MB_MASK | \ ++ IEEE80211_OFDM_RATE_36MB_MASK | \ ++ IEEE80211_OFDM_RATE_48MB_MASK | \ ++ IEEE80211_OFDM_RATE_54MB_MASK) ++#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ ++ IEEE80211_CCK_DEFAULT_RATES_MASK) ++ ++#define IEEE80211_NUM_OFDM_RATES 8 ++#define IEEE80211_NUM_CCK_RATES 4 ++#define IEEE80211_OFDM_SHIFT_MASK_A 4 ++ ++ ++/* this is stolen and modified from the madwifi driver*/ ++#define IEEE80211_FC0_TYPE_MASK 0x0c ++#define IEEE80211_FC0_TYPE_DATA 0x08 ++#define IEEE80211_FC0_SUBTYPE_MASK 0xB0 ++#define IEEE80211_FC0_SUBTYPE_QOS 0x80 ++ ++#define IEEE80211_QOS_HAS_SEQ(fc) \ ++ (((fc) & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == \ ++ (IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_QOS)) ++ ++/* this is stolen from ipw2200 driver */ ++#define IEEE_IBSS_MAC_HASH_SIZE 31 ++struct ieee_ibss_seq { ++ u8 mac[ETH_ALEN]; ++ u16 seq_num[17]; ++ u16 frag_num[17]; ++ unsigned long packet_time[17]; ++ struct list_head list; ++}; ++ ++/* NOTE: This data is for statistical purposes; not all hardware provides this ++ * information for frames received. Not setting these will not cause ++ * any adverse affects. */ ++struct ieee80211_rx_stats { ++#if 1 ++ u32 mac_time[2]; ++ s8 rssi; ++ u8 signal; ++ u8 noise; ++ u16 rate; /* in 100 kbps */ ++ u8 received_channel; ++ u8 control; ++ u8 mask; ++ u8 freq; ++ u16 len; ++ u64 tsf; ++ u32 beacon_time; ++ u8 nic_type; ++ u16 Length; ++ // u8 DataRate; // In 0.5 Mbps ++ u8 SignalQuality; // in 0-100 index. ++ s32 RecvSignalPower; // Real power in dBm for this packet, no beautification and aggregation. ++ s8 RxPower; // in dBm Translate from PWdB ++ u8 SignalStrength; // in 0-100 index. ++ u16 bHwError:1; ++ u16 bCRC:1; ++ u16 bICV:1; ++ u16 bShortPreamble:1; ++ u16 Antenna:1; //for rtl8185 ++ u16 Decrypted:1; //for rtl8185, rtl8187 ++ u16 Wakeup:1; //for rtl8185 ++ u16 Reserved0:1; //for rtl8185 ++ u8 AGC; ++ u32 TimeStampLow; ++ u32 TimeStampHigh; ++ bool bShift; ++ bool bIsQosData; // Added by Annie, 2005-12-22. ++ u8 UserPriority; ++ ++ //1!!!!!!!!!!!!!!!!!!!!!!!!!!! ++ //1Attention Please!!!<11n or 8190 specific code should be put below this line> ++ //1!!!!!!!!!!!!!!!!!!!!!!!!!!! ++ ++ u8 RxDrvInfoSize; ++ u8 RxBufShift; ++ bool bIsAMPDU; ++ bool bFirstMPDU; ++ bool bContainHTC; ++ bool RxIs40MHzPacket; ++ u32 RxPWDBAll; ++ u8 RxMIMOSignalStrength[4]; // in 0~100 index ++ s8 RxMIMOSignalQuality[2]; ++ bool bPacketMatchBSSID; ++ bool bIsCCK; ++ bool bPacketToSelf; ++ //added by amy ++ u8* virtual_address; ++ u16 packetlength; // Total packet length: Must equal to sum of all FragLength ++ u16 fraglength; // FragLength should equal to PacketLength in non-fragment case ++ u16 fragoffset; // Data offset for this fragment ++ u16 ntotalfrag; ++ bool bisrxaggrsubframe; ++ bool bPacketBeacon; //cosa add for rssi ++ bool bToSelfBA; //cosa add for rssi ++ char cck_adc_pwdb[4]; //cosa add for rx path selection ++ u16 Seq_Num; ++#endif ++ ++}; ++ ++/* IEEE 802.11 requires that STA supports concurrent reception of at least ++ * three fragmented frames. This define can be increased to support more ++ * concurrent frames, but it should be noted that each entry can consume about ++ * 2 kB of RAM and increasing cache size will slow down frame reassembly. */ ++#define IEEE80211_FRAG_CACHE_LEN 4 ++ ++struct ieee80211_frag_entry { ++ unsigned long first_frag_time; ++ unsigned int seq; ++ unsigned int last_frag; ++ struct sk_buff *skb; ++ u8 src_addr[ETH_ALEN]; ++ u8 dst_addr[ETH_ALEN]; ++}; ++ ++struct ieee80211_stats { ++ unsigned int tx_unicast_frames; ++ unsigned int tx_multicast_frames; ++ unsigned int tx_fragments; ++ unsigned int tx_unicast_octets; ++ unsigned int tx_multicast_octets; ++ unsigned int tx_deferred_transmissions; ++ unsigned int tx_single_retry_frames; ++ unsigned int tx_multiple_retry_frames; ++ unsigned int tx_retry_limit_exceeded; ++ unsigned int tx_discards; ++ unsigned int rx_unicast_frames; ++ unsigned int rx_multicast_frames; ++ unsigned int rx_fragments; ++ unsigned int rx_unicast_octets; ++ unsigned int rx_multicast_octets; ++ unsigned int rx_fcs_errors; ++ unsigned int rx_discards_no_buffer; ++ unsigned int tx_discards_wrong_sa; ++ unsigned int rx_discards_undecryptable; ++ unsigned int rx_message_in_msg_fragments; ++ unsigned int rx_message_in_bad_msg_fragments; ++}; ++ ++struct ieee80211_device; ++ ++#include "ieee80211_crypt.h" ++ ++#define SEC_KEY_1 (1<<0) ++#define SEC_KEY_2 (1<<1) ++#define SEC_KEY_3 (1<<2) ++#define SEC_KEY_4 (1<<3) ++#define SEC_ACTIVE_KEY (1<<4) ++#define SEC_AUTH_MODE (1<<5) ++#define SEC_UNICAST_GROUP (1<<6) ++#define SEC_LEVEL (1<<7) ++#define SEC_ENABLED (1<<8) ++#define SEC_ENCRYPT (1<<9) ++ ++#define SEC_LEVEL_0 0 /* None */ ++#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */ ++#define SEC_LEVEL_2 2 /* Level 1 + TKIP */ ++#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */ ++#define SEC_LEVEL_3 4 /* Level 2 + CCMP */ ++ ++#define SEC_ALG_NONE 0 ++#define SEC_ALG_WEP 1 ++#define SEC_ALG_TKIP 2 ++#define SEC_ALG_CCMP 3 ++ ++#define WEP_KEYS 4 ++#define WEP_KEY_LEN 13 ++#define SCM_KEY_LEN 32 ++#define SCM_TEMPORAL_KEY_LENGTH 16 ++ ++struct ieee80211_security { ++ u16 active_key:2, ++ enabled:1, ++ auth_mode:2, ++ auth_algo:4, ++ unicast_uses_group:1, ++ encrypt:1; ++ u8 key_sizes[WEP_KEYS]; ++ u8 keys[WEP_KEYS][SCM_KEY_LEN]; ++ u8 level; ++ u16 flags; ++} __attribute__ ((packed)); ++ ++ ++/* ++ 802.11 data frame from AP ++ ,-------------------------------------------------------------------. ++Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 | ++ |------|------|---------|---------|---------|------|---------|------| ++Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs | ++ | | tion | (BSSID) | | | ence | data | | ++ `-------------------------------------------------------------------' ++Total: 28-2340 bytes ++*/ ++ ++/* Management Frame Information Element Types */ ++enum ieee80211_mfie { ++ MFIE_TYPE_SSID = 0, ++ MFIE_TYPE_RATES = 1, ++ MFIE_TYPE_FH_SET = 2, ++ MFIE_TYPE_DS_SET = 3, ++ MFIE_TYPE_CF_SET = 4, ++ MFIE_TYPE_TIM = 5, ++ MFIE_TYPE_IBSS_SET = 6, ++ MFIE_TYPE_COUNTRY = 7, ++ MFIE_TYPE_HOP_PARAMS = 8, ++ MFIE_TYPE_HOP_TABLE = 9, ++ MFIE_TYPE_REQUEST = 10, ++ MFIE_TYPE_CHALLENGE = 16, ++ MFIE_TYPE_POWER_CONSTRAINT = 32, ++ MFIE_TYPE_POWER_CAPABILITY = 33, ++ MFIE_TYPE_TPC_REQUEST = 34, ++ MFIE_TYPE_TPC_REPORT = 35, ++ MFIE_TYPE_SUPP_CHANNELS = 36, ++ MFIE_TYPE_CSA = 37, ++ MFIE_TYPE_MEASURE_REQUEST = 38, ++ MFIE_TYPE_MEASURE_REPORT = 39, ++ MFIE_TYPE_QUIET = 40, ++ MFIE_TYPE_IBSS_DFS = 41, ++ MFIE_TYPE_ERP = 42, ++ MFIE_TYPE_RSN = 48, ++ MFIE_TYPE_RATES_EX = 50, ++ MFIE_TYPE_HT_CAP= 45, ++ MFIE_TYPE_HT_INFO= 61, ++ MFIE_TYPE_AIRONET=133, ++ MFIE_TYPE_GENERIC = 221, ++ MFIE_TYPE_QOS_PARAMETER = 222, ++}; ++ ++/* Minimal header; can be used for passing 802.11 frames with sufficient ++ * information to determine what type of underlying data type is actually ++ * stored in the data. */ ++struct ieee80211_hdr { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 payload[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_hdr_1addr { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 payload[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_hdr_2addr { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 payload[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_hdr_3addr { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ __le16 seq_ctl; ++ u8 payload[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_hdr_4addr { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ __le16 seq_ctl; ++ u8 addr4[ETH_ALEN]; ++ u8 payload[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_hdr_3addrqos { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ __le16 seq_ctl; ++ u8 payload[0]; ++ __le16 qos_ctl; ++} __attribute__ ((packed)); ++ ++struct ieee80211_hdr_4addrqos { ++ __le16 frame_ctl; ++ __le16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ __le16 seq_ctl; ++ u8 addr4[ETH_ALEN]; ++ u8 payload[0]; ++ __le16 qos_ctl; ++} __attribute__ ((packed)); ++ ++struct ieee80211_info_element { ++ u8 id; ++ u8 len; ++ u8 data[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_authentication { ++ struct ieee80211_hdr_3addr header; ++ __le16 algorithm; ++ __le16 transaction; ++ __le16 status; ++ /*challenge*/ ++ struct ieee80211_info_element info_element[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_disassoc { ++ struct ieee80211_hdr_3addr header; ++ __le16 reason; ++} __attribute__ ((packed)); ++ ++struct ieee80211_probe_request { ++ struct ieee80211_hdr_3addr header; ++ /* SSID, supported rates */ ++ struct ieee80211_info_element info_element[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_probe_response { ++ struct ieee80211_hdr_3addr header; ++ u32 time_stamp[2]; ++ __le16 beacon_interval; ++ __le16 capability; ++ /* SSID, supported rates, FH params, DS params, ++ * CF params, IBSS params, TIM (if beacon), RSN */ ++ struct ieee80211_info_element info_element[0]; ++} __attribute__ ((packed)); ++ ++/* Alias beacon for probe_response */ ++#define ieee80211_beacon ieee80211_probe_response ++ ++struct ieee80211_assoc_request_frame { ++ struct ieee80211_hdr_3addr header; ++ __le16 capability; ++ __le16 listen_interval; ++ /* SSID, supported rates, RSN */ ++ struct ieee80211_info_element info_element[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_reassoc_request_frame { ++ struct ieee80211_hdr_3addr header; ++ __le16 capability; ++ __le16 listen_interval; ++ u8 current_ap[ETH_ALEN]; ++ /* SSID, supported rates, RSN */ ++ struct ieee80211_info_element info_element[0]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_assoc_response_frame { ++ struct ieee80211_hdr_3addr header; ++ __le16 capability; ++ __le16 status; ++ __le16 aid; ++ struct ieee80211_info_element info_element[0]; /* supported rates */ ++} __attribute__ ((packed)); ++ ++struct ieee80211_txb { ++ u8 nr_frags; ++ u8 encrypted; ++ u8 queue_index; ++ u8 rts_included; ++ u16 reserved; ++ __le16 frag_size; ++ __le16 payload_size; ++ struct sk_buff *fragments[0]; ++}; ++ ++#define MAX_TX_AGG_COUNT 16 ++struct ieee80211_drv_agg_txb { ++ u8 nr_drv_agg_frames; ++ struct sk_buff *tx_agg_frames[MAX_TX_AGG_COUNT]; ++}__attribute__((packed)); ++ ++#define MAX_SUBFRAME_COUNT 64 ++struct ieee80211_rxb { ++ u8 nr_subframes; ++ struct sk_buff *subframes[MAX_SUBFRAME_COUNT]; ++ u8 dst[ETH_ALEN]; ++ u8 src[ETH_ALEN]; ++}__attribute__((packed)); ++ ++typedef union _frameqos { ++ u16 shortdata; ++ u8 chardata[2]; ++ struct { ++ u16 tid:4; ++ u16 eosp:1; ++ u16 ack_policy:2; ++ u16 reserved:1; ++ u16 txop:8; ++ }field; ++}frameqos,*pframeqos; ++ ++/* SWEEP TABLE ENTRIES NUMBER*/ ++#define MAX_SWEEP_TAB_ENTRIES 42 ++#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7 ++/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs ++ * only use 8, and then use extended rates for the remaining supported ++ * rates. Other APs, however, stick all of their supported rates on the ++ * main rates information element... */ ++#define MAX_RATES_LENGTH ((u8)12) ++#define MAX_RATES_EX_LENGTH ((u8)16) ++#define MAX_NETWORK_COUNT 128 ++ ++#define MAX_CHANNEL_NUMBER 161 ++#define IEEE80211_SOFTMAC_SCAN_TIME 100 ++//(HZ / 2) ++#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2) ++ ++#define CRC_LENGTH 4U ++ ++#define MAX_WPA_IE_LEN 64 ++ ++#define NETWORK_EMPTY_ESSID (1<<0) ++#define NETWORK_HAS_OFDM (1<<1) ++#define NETWORK_HAS_CCK (1<<2) ++ ++/* QoS structure */ ++#define NETWORK_HAS_QOS_PARAMETERS (1<<3) ++#define NETWORK_HAS_QOS_INFORMATION (1<<4) ++#define NETWORK_HAS_QOS_MASK (NETWORK_HAS_QOS_PARAMETERS | \ ++ NETWORK_HAS_QOS_INFORMATION) ++/* 802.11h */ ++#define NETWORK_HAS_POWER_CONSTRAINT (1<<5) ++#define NETWORK_HAS_CSA (1<<6) ++#define NETWORK_HAS_QUIET (1<<7) ++#define NETWORK_HAS_IBSS_DFS (1<<8) ++#define NETWORK_HAS_TPC_REPORT (1<<9) ++ ++#define NETWORK_HAS_ERP_VALUE (1<<10) ++ ++#define QOS_QUEUE_NUM 4 ++#define QOS_OUI_LEN 3 ++#define QOS_OUI_TYPE 2 ++#define QOS_ELEMENT_ID 221 ++#define QOS_OUI_INFO_SUB_TYPE 0 ++#define QOS_OUI_PARAM_SUB_TYPE 1 ++#define QOS_VERSION_1 1 ++#define QOS_AIFSN_MIN_VALUE 2 ++#if 1 ++struct ieee80211_qos_information_element { ++ u8 elementID; ++ u8 length; ++ u8 qui[QOS_OUI_LEN]; ++ u8 qui_type; ++ u8 qui_subtype; ++ u8 version; ++ u8 ac_info; ++} __attribute__ ((packed)); ++ ++struct ieee80211_qos_ac_parameter { ++ u8 aci_aifsn; ++ u8 ecw_min_max; ++ __le16 tx_op_limit; ++} __attribute__ ((packed)); ++ ++struct ieee80211_qos_parameter_info { ++ struct ieee80211_qos_information_element info_element; ++ u8 reserved; ++ struct ieee80211_qos_ac_parameter ac_params_record[QOS_QUEUE_NUM]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_qos_parameters { ++ __le16 cw_min[QOS_QUEUE_NUM]; ++ __le16 cw_max[QOS_QUEUE_NUM]; ++ u8 aifs[QOS_QUEUE_NUM]; ++ u8 flag[QOS_QUEUE_NUM]; ++ __le16 tx_op_limit[QOS_QUEUE_NUM]; ++} __attribute__ ((packed)); ++ ++struct ieee80211_qos_data { ++ struct ieee80211_qos_parameters parameters; ++ int active; ++ int supported; ++ u8 param_count; ++ u8 old_param_count; ++}; ++ ++struct ieee80211_tim_parameters { ++ u8 tim_count; ++ u8 tim_period; ++} __attribute__ ((packed)); ++ ++//#else ++struct ieee80211_wmm_ac_param { ++ u8 ac_aci_acm_aifsn; ++ u8 ac_ecwmin_ecwmax; ++ u16 ac_txop_limit; ++}; ++ ++struct ieee80211_wmm_ts_info { ++ u8 ac_dir_tid; ++ u8 ac_up_psb; ++ u8 reserved; ++} __attribute__ ((packed)); ++ ++struct ieee80211_wmm_tspec_elem { ++ struct ieee80211_wmm_ts_info ts_info; ++ u16 norm_msdu_size; ++ u16 max_msdu_size; ++ u32 min_serv_inter; ++ u32 max_serv_inter; ++ u32 inact_inter; ++ u32 suspen_inter; ++ u32 serv_start_time; ++ u32 min_data_rate; ++ u32 mean_data_rate; ++ u32 peak_data_rate; ++ u32 max_burst_size; ++ u32 delay_bound; ++ u32 min_phy_rate; ++ u16 surp_band_allow; ++ u16 medium_time; ++}__attribute__((packed)); ++#endif ++enum eap_type { ++ EAP_PACKET = 0, ++ EAPOL_START, ++ EAPOL_LOGOFF, ++ EAPOL_KEY, ++ EAPOL_ENCAP_ASF_ALERT ++}; ++ ++static const char *eap_types[] = { ++ [EAP_PACKET] = "EAP-Packet", ++ [EAPOL_START] = "EAPOL-Start", ++ [EAPOL_LOGOFF] = "EAPOL-Logoff", ++ [EAPOL_KEY] = "EAPOL-Key", ++ [EAPOL_ENCAP_ASF_ALERT] = "EAPOL-Encap-ASF-Alert" ++}; ++ ++static inline const char *eap_get_type(int type) ++{ ++ return ((u32)type >= ARRAY_SIZE(eap_types)) ? "Unknown" : eap_types[type]; ++} ++//added by amy for reorder ++static inline u8 Frame_QoSTID(u8* buf) ++{ ++ struct ieee80211_hdr_3addr *hdr; ++ u16 fc; ++ hdr = (struct ieee80211_hdr_3addr *)buf; ++ fc = le16_to_cpu(hdr->frame_ctl); ++ return (u8)((frameqos*)(buf + (((fc & IEEE80211_FCTL_TODS)&&(fc & IEEE80211_FCTL_FROMDS))? 30 : 24)))->field.tid; ++} ++ ++//added by amy for reorder ++ ++struct eapol { ++ u8 snap[6]; ++ u16 ethertype; ++ u8 version; ++ u8 type; ++ u16 length; ++} __attribute__ ((packed)); ++ ++struct ieee80211_softmac_stats{ ++ unsigned int rx_ass_ok; ++ unsigned int rx_ass_err; ++ unsigned int rx_probe_rq; ++ unsigned int tx_probe_rs; ++ unsigned int tx_beacons; ++ unsigned int rx_auth_rq; ++ unsigned int rx_auth_rs_ok; ++ unsigned int rx_auth_rs_err; ++ unsigned int tx_auth_rq; ++ unsigned int no_auth_rs; ++ unsigned int no_ass_rs; ++ unsigned int tx_ass_rq; ++ unsigned int rx_ass_rq; ++ unsigned int tx_probe_rq; ++ unsigned int reassoc; ++ unsigned int swtxstop; ++ unsigned int swtxawake; ++ unsigned char CurrentShowTxate; ++ unsigned char last_packet_rate; ++ unsigned int txretrycount; ++}; ++ ++#define BEACON_PROBE_SSID_ID_POSITION 12 ++ ++struct ieee80211_info_element_hdr { ++ u8 id; ++ u8 len; ++} __attribute__ ((packed)); ++ ++/* ++ * These are the data types that can make up management packets ++ * ++ u16 auth_algorithm; ++ u16 auth_sequence; ++ u16 beacon_interval; ++ u16 capability; ++ u8 current_ap[ETH_ALEN]; ++ u16 listen_interval; ++ struct { ++ u16 association_id:14, reserved:2; ++ } __attribute__ ((packed)); ++ u32 time_stamp[2]; ++ u16 reason; ++ u16 status; ++*/ ++ ++#define IEEE80211_DEFAULT_TX_ESSID "Penguin" ++#define IEEE80211_DEFAULT_BASIC_RATE 2 //1Mbps ++ ++enum {WMM_all_frame, WMM_two_frame, WMM_four_frame, WMM_six_frame}; ++#define MAX_SP_Len (WMM_all_frame << 4) ++#define IEEE80211_QOS_TID 0x0f ++#define QOS_CTL_NOTCONTAIN_ACK (0x01 << 5) ++ ++#define IEEE80211_DTIM_MBCAST 4 ++#define IEEE80211_DTIM_UCAST 2 ++#define IEEE80211_DTIM_VALID 1 ++#define IEEE80211_DTIM_INVALID 0 ++ ++#define IEEE80211_PS_DISABLED 0 ++#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST ++#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST ++ ++//added by David for QoS 2006/6/30 ++//#define WMM_Hang_8187 ++#ifdef WMM_Hang_8187 ++#undef WMM_Hang_8187 ++#endif ++ ++#define WME_AC_BK 0x00 ++#define WME_AC_BE 0x01 ++#define WME_AC_VI 0x02 ++#define WME_AC_VO 0x03 ++#define WME_ACI_MASK 0x03 ++#define WME_AIFSN_MASK 0x03 ++#define WME_AC_PRAM_LEN 16 ++ ++#define MAX_RECEIVE_BUFFER_SIZE 9100 ++ ++//UP Mapping to AC, using in MgntQuery_SequenceNumber() and maybe for DSCP ++//#define UP2AC(up) ((up<3) ? ((up==0)?1:0) : (up>>1)) ++#if 1 ++#define UP2AC(up) ( \ ++ ((up) < 1) ? WME_AC_BE : \ ++ ((up) < 3) ? WME_AC_BK : \ ++ ((up) < 4) ? WME_AC_BE : \ ++ ((up) < 6) ? WME_AC_VI : \ ++ WME_AC_VO) ++#endif ++//AC Mapping to UP, using in Tx part for selecting the corresponding TX queue ++#define AC2UP(_ac) ( \ ++ ((_ac) == WME_AC_VO) ? 6 : \ ++ ((_ac) == WME_AC_VI) ? 5 : \ ++ ((_ac) == WME_AC_BK) ? 1 : \ ++ 0) ++ ++#define ETHER_ADDR_LEN 6 /* length of an Ethernet address */ ++#define ETHERNET_HEADER_SIZE 14 /* length of two Ethernet address plus ether type*/ ++ ++struct ether_header { ++ u8 ether_dhost[ETHER_ADDR_LEN]; ++ u8 ether_shost[ETHER_ADDR_LEN]; ++ u16 ether_type; ++} __attribute__((packed)); ++ ++#ifndef ETHERTYPE_PAE ++#define ETHERTYPE_PAE 0x888e /* EAPOL PAE/802.1x */ ++#endif ++#ifndef ETHERTYPE_IP ++#define ETHERTYPE_IP 0x0800 /* IP protocol */ ++#endif ++ ++typedef struct _bss_ht{ ++ ++ bool support_ht; ++ ++ // HT related elements ++ u8 ht_cap_buf[32]; ++ u16 ht_cap_len; ++ u8 ht_info_buf[32]; ++ u16 ht_info_len; ++ ++ HT_SPEC_VER ht_spec_ver; ++ //HT_CAPABILITY_ELE bdHTCapEle; ++ //HT_INFORMATION_ELE bdHTInfoEle; ++ ++ bool aggregation; ++ bool long_slot_time; ++}bss_ht, *pbss_ht; ++ ++typedef enum _erp_t{ ++ ERP_NonERPpresent = 0x01, ++ ERP_UseProtection = 0x02, ++ ERP_BarkerPreambleMode = 0x04, ++} erp_t; ++ ++ ++struct ieee80211_network { ++ /* These entries are used to identify a unique network */ ++ u8 bssid[ETH_ALEN]; ++ u8 channel; ++ /* Ensure null-terminated for any debug msgs */ ++ u8 ssid[IW_ESSID_MAX_SIZE + 1]; ++ u8 ssid_len; ++#if 1 ++ struct ieee80211_qos_data qos_data; ++#else ++ // Qos related. Added by Annie, 2005-11-01. ++ BSS_QOS BssQos; ++#endif ++ ++ //added by amy for LEAP ++ bool bWithAironetIE; ++ bool bCkipSupported; ++ bool bCcxRmEnable; ++ u16 CcxRmState[2]; ++ // CCXv4 S59, MBSSID. ++ bool bMBssidValid; ++ u8 MBssidMask; ++ u8 MBssid[6]; ++ // CCX 2 S38, WLAN Device Version Number element. Annie, 2006-08-20. ++ bool bWithCcxVerNum; ++ u8 BssCcxVerNumber; ++ /* These are network statistics */ ++ struct ieee80211_rx_stats stats; ++ u16 capability; ++ u8 rates[MAX_RATES_LENGTH]; ++ u8 rates_len; ++ u8 rates_ex[MAX_RATES_EX_LENGTH]; ++ u8 rates_ex_len; ++ unsigned long last_scanned; ++ u8 mode; ++ u32 flags; ++ u32 last_associate; ++ u32 time_stamp[2]; ++ u16 beacon_interval; ++ u16 listen_interval; ++ u16 atim_window; ++ u8 erp_value; ++ u8 wpa_ie[MAX_WPA_IE_LEN]; ++ size_t wpa_ie_len; ++ u8 rsn_ie[MAX_WPA_IE_LEN]; ++ size_t rsn_ie_len; ++ ++ struct ieee80211_tim_parameters tim; ++ u8 dtim_period; ++ u8 dtim_data; ++ u32 last_dtim_sta_time[2]; ++ ++ //appeded for QoS ++ u8 wmm_info; ++ struct ieee80211_wmm_ac_param wmm_param[4]; ++ u8 QoS_Enable; ++#ifdef THOMAS_TURBO ++ u8 Turbo_Enable;//enable turbo mode, added by thomas ++#endif ++#ifdef ENABLE_DOT11D ++ u16 CountryIeLen; ++ u8 CountryIeBuf[MAX_IE_LEN]; ++#endif ++ // HT Related, by amy, 2008.04.29 ++ BSS_HT bssht; ++ // Add to handle broadcom AP management frame CCK rate. ++ bool broadcom_cap_exist; ++ bool ralink_cap_exist; ++ bool atheros_cap_exist; ++ bool cisco_cap_exist; ++ bool unknown_cap_exist; ++// u8 berp_info; ++ bool berp_info_valid; ++ bool buseprotection; ++ //put at the end of the structure. ++ struct list_head list; ++}; ++ ++#if 1 ++enum ieee80211_state { ++ ++ /* the card is not linked at all */ ++ IEEE80211_NOLINK = 0, ++ ++ /* IEEE80211_ASSOCIATING* are for BSS client mode ++ * the driver shall not perform RX filtering unless ++ * the state is LINKED. ++ * The driver shall just check for the state LINKED and ++ * defaults to NOLINK for ALL the other states (including ++ * LINKED_SCANNING) ++ */ ++ ++ /* the association procedure will start (wq scheduling)*/ ++ IEEE80211_ASSOCIATING, ++ IEEE80211_ASSOCIATING_RETRY, ++ ++ /* the association procedure is sending AUTH request*/ ++ IEEE80211_ASSOCIATING_AUTHENTICATING, ++ ++ /* the association procedure has successfully authentcated ++ * and is sending association request ++ */ ++ IEEE80211_ASSOCIATING_AUTHENTICATED, ++ ++ /* the link is ok. the card associated to a BSS or linked ++ * to a ibss cell or acting as an AP and creating the bss ++ */ ++ IEEE80211_LINKED, ++ ++ /* same as LINKED, but the driver shall apply RX filter ++ * rules as we are in NO_LINK mode. As the card is still ++ * logically linked, but it is doing a syncro site survey ++ * then it will be back to LINKED state. ++ */ ++ IEEE80211_LINKED_SCANNING, ++ ++}; ++#else ++enum ieee80211_state { ++ IEEE80211_UNINITIALIZED = 0, ++ IEEE80211_INITIALIZED, ++ IEEE80211_ASSOCIATING, ++ IEEE80211_ASSOCIATED, ++ IEEE80211_AUTHENTICATING, ++ IEEE80211_AUTHENTICATED, ++ IEEE80211_SHUTDOWN ++}; ++#endif ++ ++#define DEFAULT_MAX_SCAN_AGE (15 * HZ) ++#define DEFAULT_FTS 2346 ++ ++#define CFG_IEEE80211_RESERVE_FCS (1<<0) ++#define CFG_IEEE80211_COMPUTE_FCS (1<<1) ++#define CFG_IEEE80211_RTS (1<<2) ++ ++#define IEEE80211_24GHZ_MIN_CHANNEL 1 ++#define IEEE80211_24GHZ_MAX_CHANNEL 14 ++#define IEEE80211_24GHZ_CHANNELS (IEEE80211_24GHZ_MAX_CHANNEL - \ ++ IEEE80211_24GHZ_MIN_CHANNEL + 1) ++ ++#define IEEE80211_52GHZ_MIN_CHANNEL 34 ++#define IEEE80211_52GHZ_MAX_CHANNEL 165 ++#define IEEE80211_52GHZ_CHANNELS (IEEE80211_52GHZ_MAX_CHANNEL - \ ++ IEEE80211_52GHZ_MIN_CHANNEL + 1) ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,11)) ++extern inline int is_multicast_ether_addr(const u8 *addr) ++{ ++ return ((addr[0] != 0xff) && (0x01 & addr[0])); ++} ++#endif ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13)) ++extern inline int is_broadcast_ether_addr(const u8 *addr) ++{ ++ return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \ ++ (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff)); ++} ++#endif ++ ++typedef struct tx_pending_t{ ++ int frag; ++ struct ieee80211_txb *txb; ++}tx_pending_t; ++ ++typedef struct _bandwidth_autoswitch ++{ ++ long threshold_20Mhzto40Mhz; ++ long threshold_40Mhzto20Mhz; ++ bool bforced_tx20Mhz; ++ bool bautoswitch_enable; ++}bandwidth_autoswitch,*pbandwidth_autoswitch; ++ ++ ++//added by amy for order ++ ++#define REORDER_WIN_SIZE 128 ++#define REORDER_ENTRY_NUM 128 ++typedef struct _RX_REORDER_ENTRY ++{ ++ struct list_head List; ++ u16 SeqNum; ++ struct ieee80211_rxb* prxb; ++} RX_REORDER_ENTRY, *PRX_REORDER_ENTRY; ++//added by amy for order ++typedef enum _Fsync_State{ ++ Default_Fsync, ++ HW_Fsync, ++ SW_Fsync ++}Fsync_State; ++ ++// Power save mode configured. ++typedef enum _RT_PS_MODE ++{ ++ eActive, // Active/Continuous access. ++ eMaxPs, // Max power save mode. ++ eFastPs // Fast power save mode. ++}RT_PS_MODE; ++ ++typedef enum _IPS_CALLBACK_FUNCION ++{ ++ IPS_CALLBACK_NONE = 0, ++ IPS_CALLBACK_MGNT_LINK_REQUEST = 1, ++ IPS_CALLBACK_JOIN_REQUEST = 2, ++}IPS_CALLBACK_FUNCION; ++ ++typedef enum _RT_JOIN_ACTION{ ++ RT_JOIN_INFRA = 1, ++ RT_JOIN_IBSS = 2, ++ RT_START_IBSS = 3, ++ RT_NO_ACTION = 4, ++}RT_JOIN_ACTION; ++ ++typedef struct _IbssParms{ ++ u16 atimWin; ++}IbssParms, *PIbssParms; ++#define MAX_NUM_RATES 264 // Max num of support rates element: 8, Max num of ext. support rate: 255. 061122, by rcnjko. ++ ++// RF state. ++typedef enum _RT_RF_POWER_STATE ++{ ++ eRfOn, ++ eRfSleep, ++ eRfOff ++}RT_RF_POWER_STATE; ++ ++typedef struct _RT_POWER_SAVE_CONTROL ++{ ++ ++ // ++ // Inactive Power Save(IPS) : Disable RF when disconnected ++ // ++ bool bInactivePs; ++ bool bIPSModeBackup; ++ bool bSwRfProcessing; ++ RT_RF_POWER_STATE eInactivePowerState; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ struct work_struct InactivePsWorkItem; ++#else ++ struct tq_struct InactivePsWorkItem; ++#endif ++ struct timer_list InactivePsTimer; ++ ++ // Return point for join action ++ IPS_CALLBACK_FUNCION ReturnPoint; ++ ++ // Recored Parameters for rescheduled JoinRequest ++ bool bTmpBssDesc; ++ RT_JOIN_ACTION tmpJoinAction; ++ struct ieee80211_network tmpBssDesc; ++ ++ // Recored Parameters for rescheduled MgntLinkRequest ++ bool bTmpScanOnly; ++ bool bTmpActiveScan; ++ bool bTmpFilterHiddenAP; ++ bool bTmpUpdateParms; ++ u8 tmpSsidBuf[33]; ++ OCTET_STRING tmpSsid2Scan; ++ bool bTmpSsid2Scan; ++ u8 tmpNetworkType; ++ u8 tmpChannelNumber; ++ u16 tmpBcnPeriod; ++ u8 tmpDtimPeriod; ++ u16 tmpmCap; ++ OCTET_STRING tmpSuppRateSet; ++ u8 tmpSuppRateBuf[MAX_NUM_RATES]; ++ bool bTmpSuppRate; ++ IbssParms tmpIbpm; ++ bool bTmpIbpm; ++ ++ // ++ // Leisre Poswer Save : Disable RF if connected but traffic is not busy ++ // ++ bool bLeisurePs; ++ ++}RT_POWER_SAVE_CONTROL,*PRT_POWER_SAVE_CONTROL; ++ ++typedef u32 RT_RF_CHANGE_SOURCE; ++#define RF_CHANGE_BY_SW BIT31 ++#define RF_CHANGE_BY_HW BIT30 ++#define RF_CHANGE_BY_PS BIT29 ++#define RF_CHANGE_BY_IPS BIT28 ++#define RF_CHANGE_BY_INIT 0 // Do not change the RFOff reason. Defined by Bruce, 2008-01-17. ++ ++#ifdef ENABLE_DOT11D ++typedef enum ++{ ++ COUNTRY_CODE_FCC = 0, ++ COUNTRY_CODE_IC = 1, ++ COUNTRY_CODE_ETSI = 2, ++ COUNTRY_CODE_SPAIN = 3, ++ COUNTRY_CODE_FRANCE = 4, ++ COUNTRY_CODE_MKK = 5, ++ COUNTRY_CODE_MKK1 = 6, ++ COUNTRY_CODE_ISRAEL = 7, ++ COUNTRY_CODE_TELEC, ++ COUNTRY_CODE_MIC, ++ COUNTRY_CODE_GLOBAL_DOMAIN ++}country_code_type_t; ++#endif ++ ++#define RT_MAX_LD_SLOT_NUM 10 ++typedef struct _RT_LINK_DETECT_T{ ++ ++ u32 NumRecvBcnInPeriod; ++ u32 NumRecvDataInPeriod; ++ ++ u32 RxBcnNum[RT_MAX_LD_SLOT_NUM]; // number of Rx beacon / CheckForHang_period to determine link status ++ u32 RxDataNum[RT_MAX_LD_SLOT_NUM]; // number of Rx data / CheckForHang_period to determine link status ++ u16 SlotNum; // number of CheckForHang period to determine link status ++ u16 SlotIndex; ++ ++ u32 NumTxOkInPeriod; ++ u32 NumRxOkInPeriod; ++ bool bBusyTraffic; ++}RT_LINK_DETECT_T, *PRT_LINK_DETECT_T; ++ ++ ++struct ieee80211_device { ++ struct net_device *dev; ++ struct ieee80211_security sec; ++ ++ //hw security related ++// u8 hwsec_support; //support? ++ u8 hwsec_active; //hw security active. ++ bool is_silent_reset; ++ bool is_roaming; ++ bool ieee_up; ++ //added by amy ++ bool bSupportRemoteWakeUp; ++ RT_PS_MODE dot11PowerSaveMode; // Power save mode configured. ++ bool actscanning; ++ bool beinretry; ++ RT_RF_POWER_STATE eRFPowerState; ++ RT_RF_CHANGE_SOURCE RfOffReason; ++ bool is_set_key; ++ //11n spec related I wonder if These info structure need to be moved out of ieee80211_device ++ ++ //11n HT below ++ PRT_HIGH_THROUGHPUT pHTInfo; ++ //struct timer_list SwBwTimer; ++// spinlock_t chnlop_spinlock; ++ spinlock_t bw_spinlock; ++ ++ spinlock_t reorder_spinlock; ++ // for HT operation rate set. we use this one for HT data rate to seperate different descriptors ++ //the way fill this is the same as in the IE ++ u8 Regdot11HTOperationalRateSet[16]; //use RATR format ++ u8 dot11HTOperationalRateSet[16]; //use RATR format ++ u8 RegHTSuppRateSet[16]; ++ u8 HTCurrentOperaRate; ++ u8 HTHighestOperaRate; ++ //wb added for rate operation mode to firmware ++ u8 bTxDisableRateFallBack; ++ u8 bTxUseDriverAssingedRate; ++ atomic_t atm_chnlop; ++ atomic_t atm_swbw; ++// u8 HTHighestOperaRate; ++// u8 HTCurrentOperaRate; ++ ++ // 802.11e and WMM Traffic Stream Info (TX) ++ struct list_head Tx_TS_Admit_List; ++ struct list_head Tx_TS_Pending_List; ++ struct list_head Tx_TS_Unused_List; ++ TX_TS_RECORD TxTsRecord[TOTAL_TS_NUM]; ++ // 802.11e and WMM Traffic Stream Info (RX) ++ struct list_head Rx_TS_Admit_List; ++ struct list_head Rx_TS_Pending_List; ++ struct list_head Rx_TS_Unused_List; ++ RX_TS_RECORD RxTsRecord[TOTAL_TS_NUM]; ++//#ifdef TO_DO_LIST ++ RX_REORDER_ENTRY RxReorderEntry[128]; ++ struct list_head RxReorder_Unused_List; ++//#endif ++ // Qos related. Added by Annie, 2005-11-01. ++// PSTA_QOS pStaQos; ++ u8 ForcedPriority; // Force per-packet priority 1~7. (default: 0, not to force it.) ++ ++ ++ /* Bookkeeping structures */ ++ struct net_device_stats stats; ++ struct ieee80211_stats ieee_stats; ++ struct ieee80211_softmac_stats softmac_stats; ++ ++ /* Probe / Beacon management */ ++ struct list_head network_free_list; ++ struct list_head network_list; ++ struct ieee80211_network *networks; ++ int scans; ++ int scan_age; ++ ++ int iw_mode; /* operating mode (IW_MODE_*) */ ++ struct iw_spy_data spy_data; ++ ++ spinlock_t lock; ++ spinlock_t wpax_suitlist_lock; ++ ++ int tx_headroom; /* Set to size of any additional room needed at front ++ * of allocated Tx SKBs */ ++ u32 config; ++ ++ /* WEP and other encryption related settings at the device level */ ++ int open_wep; /* Set to 1 to allow unencrypted frames */ ++ int auth_mode; ++ int reset_on_keychange; /* Set to 1 if the HW needs to be reset on ++ * WEP key changes */ ++ ++ /* If the host performs {en,de}cryption, then set to 1 */ ++ int host_encrypt; ++ int host_encrypt_msdu; ++ int host_decrypt; ++ /* host performs multicast decryption */ ++ int host_mc_decrypt; ++ ++ /* host should strip IV and ICV from protected frames */ ++ /* meaningful only when hardware decryption is being used */ ++ int host_strip_iv_icv; ++ ++ int host_open_frag; ++ int host_build_iv; ++ int ieee802_1x; /* is IEEE 802.1X used */ ++ ++ /* WPA data */ ++ bool bHalfWirelessN24GMode; ++ int wpa_enabled; ++ int drop_unencrypted; ++ int tkip_countermeasures; ++ int privacy_invoked; ++ size_t wpa_ie_len; ++ u8 *wpa_ie; ++ u8 ap_mac_addr[6]; ++ u16 pairwise_key_type; ++ u16 group_key_type; ++ struct list_head crypt_deinit_list; ++ struct ieee80211_crypt_data *crypt[WEP_KEYS]; ++ int tx_keyidx; /* default TX key index (crypt[tx_keyidx]) */ ++ struct timer_list crypt_deinit_timer; ++ int crypt_quiesced; ++ ++ int bcrx_sta_key; /* use individual keys to override default keys even ++ * with RX of broad/multicast frames */ ++ ++ /* Fragmentation structures */ ++ // each streaming contain a entry ++ struct ieee80211_frag_entry frag_cache[17][IEEE80211_FRAG_CACHE_LEN]; ++ unsigned int frag_next_idx[17]; ++ u16 fts; /* Fragmentation Threshold */ ++#define DEFAULT_RTS_THRESHOLD 2346U ++#define MIN_RTS_THRESHOLD 1 ++#define MAX_RTS_THRESHOLD 2346U ++ u16 rts; /* RTS threshold */ ++ ++ /* Association info */ ++ u8 bssid[ETH_ALEN]; ++ ++ /* This stores infos for the current network. ++ * Either the network we are associated in INFRASTRUCTURE ++ * or the network that we are creating in MASTER mode. ++ * ad-hoc is a mixture ;-). ++ * Note that in infrastructure mode, even when not associated, ++ * fields bssid and essid may be valid (if wpa_set and essid_set ++ * are true) as thy carry the value set by the user via iwconfig ++ */ ++ struct ieee80211_network current_network; ++ ++ enum ieee80211_state state; ++ ++ int short_slot; ++ int reg_mode; ++ int mode; /* A, B, G */ ++ int modulation; /* CCK, OFDM */ ++ int freq_band; /* 2.4Ghz, 5.2Ghz, Mixed */ ++ int abg_true; /* ABG flag */ ++ ++ /* used for forcing the ibss workqueue to terminate ++ * without wait for the syncro scan to terminate ++ */ ++ short sync_scan_hurryup; ++ ++ int perfect_rssi; ++ int worst_rssi; ++ ++ u16 prev_seq_ctl; /* used to drop duplicate frames */ ++ ++ /* map of allowed channels. 0 is dummy */ ++ // FIXME: remeber to default to a basic channel plan depending of the PHY type ++#ifdef ENABLE_DOT11D ++ void* pDot11dInfo; ++ bool bGlobalDomain; ++#else ++ int channel_map[MAX_CHANNEL_NUMBER+1]; ++#endif ++ int rate; /* current rate */ ++ int basic_rate; ++ //FIXME: pleace callback, see if redundant with softmac_features ++ short active_scan; ++ ++ /* this contains flags for selectively enable softmac support */ ++ u16 softmac_features; ++ ++ /* if the sequence control field is not filled by HW */ ++ u16 seq_ctrl[5]; ++ ++ /* association procedure transaction sequence number */ ++ u16 associate_seq; ++ ++ /* AID for RTXed association responses */ ++ u16 assoc_id; ++ ++ /* power save mode related*/ ++ u8 ack_tx_to_ieee; ++ short ps; ++ short sta_sleep; ++ int ps_timeout; ++ int ps_period; ++ struct tasklet_struct ps_task; ++ u32 ps_th; ++ u32 ps_tl; ++ ++ short raw_tx; ++ /* used if IEEE_SOFTMAC_TX_QUEUE is set */ ++ short queue_stop; ++ short scanning; ++ short proto_started; ++ ++ struct semaphore wx_sem; ++ struct semaphore scan_sem; ++ ++ spinlock_t mgmt_tx_lock; ++ spinlock_t beacon_lock; ++ ++ short beacon_txing; ++ ++ short wap_set; ++ short ssid_set; ++ ++ u8 wpax_type_set; //{added by David, 2006.9.28} ++ u32 wpax_type_notify; //{added by David, 2006.9.26} ++ ++ /* QoS related flag */ ++ char init_wmmparam_flag; ++ /* set on initialization */ ++ u8 qos_support; ++ ++ /* for discarding duplicated packets in IBSS */ ++ struct list_head ibss_mac_hash[IEEE_IBSS_MAC_HASH_SIZE]; ++ ++ /* for discarding duplicated packets in BSS */ ++ u16 last_rxseq_num[17]; /* rx seq previous per-tid */ ++ u16 last_rxfrag_num[17];/* tx frag previous per-tid */ ++ unsigned long last_packet_time[17]; ++ ++ /* for PS mode */ ++ unsigned long last_rx_ps_time; ++ ++ /* used if IEEE_SOFTMAC_SINGLE_QUEUE is set */ ++ struct sk_buff *mgmt_queue_ring[MGMT_QUEUE_NUM]; ++ int mgmt_queue_head; ++ int mgmt_queue_tail; ++//{ added for rtl819x ++#define IEEE80211_QUEUE_LIMIT 128 ++ u8 AsocRetryCount; ++ unsigned int hw_header; ++ struct sk_buff_head skb_waitQ[MAX_QUEUE_SIZE]; ++ struct sk_buff_head skb_aggQ[MAX_QUEUE_SIZE]; ++ struct sk_buff_head skb_drv_aggQ[MAX_QUEUE_SIZE]; ++ u32 sta_edca_param[4]; ++ bool aggregation; ++ // Enable/Disable Rx immediate BA capability. ++ bool enable_rx_imm_BA; ++ bool bibsscoordinator; ++ ++ //+by amy for DM ,080515 ++ //Dynamic Tx power for near/far range enable/Disable , by amy , 2008-05-15 ++ bool bdynamic_txpower_enable; ++ ++ bool bCTSToSelfEnable; ++ u8 CTSToSelfTH; ++ ++ u32 fsync_time_interval; ++ u32 fsync_rate_bitmap; ++ u8 fsync_rssi_threshold; ++ bool bfsync_enable; ++ ++ u8 fsync_multiple_timeinterval; // FsyncMultipleTimeInterval * FsyncTimeInterval ++ u32 fsync_firstdiff_ratethreshold; // low threshold ++ u32 fsync_seconddiff_ratethreshold; // decrease threshold ++ Fsync_State fsync_state; ++ bool bis_any_nonbepkts; ++ //20Mhz 40Mhz AutoSwitch Threshold ++ bandwidth_autoswitch bandwidth_auto_switch; ++ //for txpower tracking ++ bool FwRWRF; ++ ++ //added by amy for AP roaming ++ RT_LINK_DETECT_T LinkDetectInfo; ++ //added by amy for ps ++ RT_POWER_SAVE_CONTROL PowerSaveControl; ++//} ++ /* used if IEEE_SOFTMAC_TX_QUEUE is set */ ++ struct tx_pending_t tx_pending; ++ ++ /* used if IEEE_SOFTMAC_ASSOCIATE is set */ ++ struct timer_list associate_timer; ++ ++ /* used if IEEE_SOFTMAC_BEACONS is set */ ++ struct timer_list beacon_timer; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ struct work_struct associate_complete_wq; ++ struct work_struct associate_procedure_wq; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ struct delayed_work softmac_scan_wq; ++ struct delayed_work associate_retry_wq; ++ struct delayed_work start_ibss_wq; ++ struct delayed_work hw_wakeup_wq; ++ struct delayed_work hw_sleep_wq; ++#else ++ struct work_struct softmac_scan_wq; ++ struct work_struct associate_retry_wq; ++ struct work_struct start_ibss_wq; ++ struct work_struct hw_wakeup_wq; ++ struct work_struct hw_sleep_wq; ++#endif ++ struct work_struct wx_sync_scan_wq; ++ struct workqueue_struct *wq; ++#else ++ /* used for periodly scan */ ++ struct timer_list scan_timer; ++ ++ struct tq_struct associate_complete_wq; ++ struct tq_struct associate_retry_wq; ++ struct tq_struct start_ibss_wq; ++ struct tq_struct associate_procedure_wq; ++ struct tq_struct softmac_scan_wq; ++ struct tq_struct wx_sync_scan_wq; ++ ++#endif ++ // Qos related. Added by Annie, 2005-11-01. ++ //STA_QOS StaQos; ++ ++ //u32 STA_EDCA_PARAM[4]; ++ //CHANNEL_ACCESS_SETTING ChannelAccessSetting; ++ ++ ++ /* Callback functions */ ++ void (*set_security)(struct net_device *dev, ++ struct ieee80211_security *sec); ++ ++ /* Used to TX data frame by using txb structs. ++ * this is not used if in the softmac_features ++ * is set the flag IEEE_SOFTMAC_TX_QUEUE ++ */ ++ int (*hard_start_xmit)(struct ieee80211_txb *txb, ++ struct net_device *dev); ++ ++ int (*reset_port)(struct net_device *dev); ++ int (*is_queue_full) (struct net_device * dev, int pri); ++ ++ int (*handle_management) (struct net_device * dev, ++ struct ieee80211_network * network, u16 type); ++ int (*is_qos_active) (struct net_device *dev, struct sk_buff *skb); ++ ++ /* Softmac-generated frames (mamagement) are TXed via this ++ * callback if the flag IEEE_SOFTMAC_SINGLE_QUEUE is ++ * not set. As some cards may have different HW queues that ++ * one might want to use for data and management frames ++ * the option to have two callbacks might be useful. ++ * This fucntion can't sleep. ++ */ ++ int (*softmac_hard_start_xmit)(struct sk_buff *skb, ++ struct net_device *dev); ++ ++ /* used instead of hard_start_xmit (not softmac_hard_start_xmit) ++ * if the IEEE_SOFTMAC_TX_QUEUE feature is used to TX data ++ * frames. I the option IEEE_SOFTMAC_SINGLE_QUEUE is also set ++ * then also management frames are sent via this callback. ++ * This function can't sleep. ++ */ ++ void (*softmac_data_hard_start_xmit)(struct sk_buff *skb, ++ struct net_device *dev,int rate); ++ ++ /* stops the HW queue for DATA frames. Useful to avoid ++ * waste time to TX data frame when we are reassociating ++ * This function can sleep. ++ */ ++ void (*data_hard_stop)(struct net_device *dev); ++ ++ /* OK this is complementar to data_poll_hard_stop */ ++ void (*data_hard_resume)(struct net_device *dev); ++ ++ /* ask to the driver to retune the radio . ++ * This function can sleep. the driver should ensure ++ * the radio has been swithced before return. ++ */ ++ void (*set_chan)(struct net_device *dev,short ch); ++ ++ /* These are not used if the ieee stack takes care of ++ * scanning (IEEE_SOFTMAC_SCAN feature set). ++ * In this case only the set_chan is used. ++ * ++ * The syncro version is similar to the start_scan but ++ * does not return until all channels has been scanned. ++ * this is called in user context and should sleep, ++ * it is called in a work_queue when swithcing to ad-hoc mode ++ * or in behalf of iwlist scan when the card is associated ++ * and root user ask for a scan. ++ * the fucntion stop_scan should stop both the syncro and ++ * background scanning and can sleep. ++ * The fucntion start_scan should initiate the background ++ * scanning and can't sleep. ++ */ ++ void (*scan_syncro)(struct net_device *dev); ++ void (*start_scan)(struct net_device *dev); ++ void (*stop_scan)(struct net_device *dev); ++ ++ /* indicate the driver that the link state is changed ++ * for example it may indicate the card is associated now. ++ * Driver might be interested in this to apply RX filter ++ * rules or simply light the LINK led ++ */ ++ void (*link_change)(struct net_device *dev); ++ ++ /* these two function indicates to the HW when to start ++ * and stop to send beacons. This is used when the ++ * IEEE_SOFTMAC_BEACONS is not set. For now the ++ * stop_send_bacons is NOT guaranteed to be called only ++ * after start_send_beacons. ++ */ ++ void (*start_send_beacons) (struct net_device *dev); ++ void (*stop_send_beacons) (struct net_device *dev); ++ ++ /* power save mode related */ ++ void (*sta_wake_up) (struct net_device *dev); ++// void (*ps_request_tx_ack) (struct net_device *dev); ++ void (*enter_sleep_state) (struct net_device *dev, u32 th, u32 tl); ++ short (*ps_is_queue_empty) (struct net_device *dev); ++#if 0 ++ /* Typical STA methods */ ++ int (*handle_auth) (struct net_device * dev, ++ struct ieee80211_auth * auth); ++ int (*handle_deauth) (struct net_device * dev, ++ struct ieee80211_deauth * auth); ++ int (*handle_action) (struct net_device * dev, ++ struct ieee80211_action * action, ++ struct ieee80211_rx_stats * stats); ++ int (*handle_disassoc) (struct net_device * dev, ++ struct ieee80211_disassoc * assoc); ++#endif ++ int (*handle_beacon) (struct net_device * dev, struct ieee80211_beacon * beacon, struct ieee80211_network * network); ++#if 0 ++ int (*handle_probe_response) (struct net_device * dev, ++ struct ieee80211_probe_response * resp, ++ struct ieee80211_network * network); ++ int (*handle_probe_request) (struct net_device * dev, ++ struct ieee80211_probe_request * req, ++ struct ieee80211_rx_stats * stats); ++#endif ++ int (*handle_assoc_response) (struct net_device * dev, struct ieee80211_assoc_response_frame * resp, struct ieee80211_network * network); ++ ++#if 0 ++ /* Typical AP methods */ ++ int (*handle_assoc_request) (struct net_device * dev); ++ int (*handle_reassoc_request) (struct net_device * dev, ++ struct ieee80211_reassoc_request * req); ++#endif ++ ++ /* check whether Tx hw resouce available */ ++ short (*check_nic_enough_desc)(struct net_device *dev, int queue_index); ++ //added by wb for HT related ++// void (*SwChnlByTimerHandler)(struct net_device *dev, int channel); ++ void (*SetBWModeHandler)(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); ++// void (*UpdateHalRATRTableHandler)(struct net_device* dev, u8* pMcsRate); ++ bool (*GetNmodeSupportBySecCfg)(struct net_device* dev); ++ void (*SetWirelessMode)(struct net_device* dev, u8 wireless_mode); ++ bool (*GetHalfNmodeSupportByAPsHandler)(struct net_device* dev); ++ void (*InitialGainHandler)(struct net_device *dev, u8 Operation); ++ ++ /* This must be the last item so that it points to the data ++ * allocated beyond this structure by alloc_ieee80211 */ ++ u8 priv[0]; ++}; ++ ++#define IEEE_A (1<<0) ++#define IEEE_B (1<<1) ++#define IEEE_G (1<<2) ++#define IEEE_N_24G (1<<4) ++#define IEEE_N_5G (1<<5) ++#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G) ++ ++/* Generate a 802.11 header */ ++ ++/* Uses the channel change callback directly ++ * instead of [start/stop] scan callbacks ++ */ ++#define IEEE_SOFTMAC_SCAN (1<<2) ++ ++/* Perform authentication and association handshake */ ++#define IEEE_SOFTMAC_ASSOCIATE (1<<3) ++ ++/* Generate probe requests */ ++#define IEEE_SOFTMAC_PROBERQ (1<<4) ++ ++/* Generate respones to probe requests */ ++#define IEEE_SOFTMAC_PROBERS (1<<5) ++ ++/* The ieee802.11 stack will manages the netif queue ++ * wake/stop for the driver, taking care of 802.11 ++ * fragmentation. See softmac.c for details. */ ++#define IEEE_SOFTMAC_TX_QUEUE (1<<7) ++ ++/* Uses only the softmac_data_hard_start_xmit ++ * even for TX management frames. ++ */ ++#define IEEE_SOFTMAC_SINGLE_QUEUE (1<<8) ++ ++/* Generate beacons. The stack will enqueue beacons ++ * to the card ++ */ ++#define IEEE_SOFTMAC_BEACONS (1<<6) ++ ++static inline void *ieee80211_priv(struct net_device *dev) ++{ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ return ((struct ieee80211_device *)netdev_priv(dev))->priv; ++#else ++ return ((struct ieee80211_device *)dev->priv)->priv; ++#endif ++} ++ ++extern inline int ieee80211_is_empty_essid(const char *essid, int essid_len) ++{ ++ /* Single white space is for Linksys APs */ ++ if (essid_len == 1 && essid[0] == ' ') ++ return 1; ++ ++ /* Otherwise, if the entire essid is 0, we assume it is hidden */ ++ while (essid_len) { ++ essid_len--; ++ if (essid[essid_len] != '\0') ++ return 0; ++ } ++ ++ return 1; ++} ++ ++extern inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee, int mode) ++{ ++ /* ++ * It is possible for both access points and our device to support ++ * combinations of modes, so as long as there is one valid combination ++ * of ap/device supported modes, then return success ++ * ++ */ ++ if ((mode & IEEE_A) && ++ (ieee->modulation & IEEE80211_OFDM_MODULATION) && ++ (ieee->freq_band & IEEE80211_52GHZ_BAND)) ++ return 1; ++ ++ if ((mode & IEEE_G) && ++ (ieee->modulation & IEEE80211_OFDM_MODULATION) && ++ (ieee->freq_band & IEEE80211_24GHZ_BAND)) ++ return 1; ++ ++ if ((mode & IEEE_B) && ++ (ieee->modulation & IEEE80211_CCK_MODULATION) && ++ (ieee->freq_band & IEEE80211_24GHZ_BAND)) ++ return 1; ++ ++ return 0; ++} ++ ++extern inline int ieee80211_get_hdrlen(u16 fc) ++{ ++ int hdrlen = IEEE80211_3ADDR_LEN; ++ ++ switch (WLAN_FC_GET_TYPE(fc)) { ++ case IEEE80211_FTYPE_DATA: ++ if ((fc & IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS)) ++ hdrlen = IEEE80211_4ADDR_LEN; /* Addr4 */ ++ if(IEEE80211_QOS_HAS_SEQ(fc)) ++ hdrlen += 2; /* QOS ctrl*/ ++ break; ++ case IEEE80211_FTYPE_CTL: ++ switch (WLAN_FC_GET_STYPE(fc)) { ++ case IEEE80211_STYPE_CTS: ++ case IEEE80211_STYPE_ACK: ++ hdrlen = IEEE80211_1ADDR_LEN; ++ break; ++ default: ++ hdrlen = IEEE80211_2ADDR_LEN; ++ break; ++ } ++ break; ++ } ++ ++ return hdrlen; ++} ++ ++static inline u8 *ieee80211_get_payload(struct ieee80211_hdr *hdr) ++{ ++ switch (ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl))) { ++ case IEEE80211_1ADDR_LEN: ++ return ((struct ieee80211_hdr_1addr *)hdr)->payload; ++ case IEEE80211_2ADDR_LEN: ++ return ((struct ieee80211_hdr_2addr *)hdr)->payload; ++ case IEEE80211_3ADDR_LEN: ++ return ((struct ieee80211_hdr_3addr *)hdr)->payload; ++ case IEEE80211_4ADDR_LEN: ++ return ((struct ieee80211_hdr_4addr *)hdr)->payload; ++ } ++ return NULL; ++} ++ ++static inline int ieee80211_is_ofdm_rate(u8 rate) ++{ ++ switch (rate & ~IEEE80211_BASIC_RATE_MASK) { ++ case IEEE80211_OFDM_RATE_6MB: ++ case IEEE80211_OFDM_RATE_9MB: ++ case IEEE80211_OFDM_RATE_12MB: ++ case IEEE80211_OFDM_RATE_18MB: ++ case IEEE80211_OFDM_RATE_24MB: ++ case IEEE80211_OFDM_RATE_36MB: ++ case IEEE80211_OFDM_RATE_48MB: ++ case IEEE80211_OFDM_RATE_54MB: ++ return 1; ++ } ++ return 0; ++} ++ ++static inline int ieee80211_is_cck_rate(u8 rate) ++{ ++ switch (rate & ~IEEE80211_BASIC_RATE_MASK) { ++ case IEEE80211_CCK_RATE_1MB: ++ case IEEE80211_CCK_RATE_2MB: ++ case IEEE80211_CCK_RATE_5MB: ++ case IEEE80211_CCK_RATE_11MB: ++ return 1; ++ } ++ return 0; ++} ++ ++ ++/* ieee80211.c */ ++extern void free_ieee80211(struct net_device *dev); ++extern struct net_device *alloc_ieee80211(int sizeof_priv); ++ ++extern int ieee80211_set_encryption(struct ieee80211_device *ieee); ++ ++/* ieee80211_tx.c */ ++ ++extern int ieee80211_encrypt_fragment( ++ struct ieee80211_device *ieee, ++ struct sk_buff *frag, ++ int hdr_len); ++ ++extern int ieee80211_xmit(struct sk_buff *skb, ++ struct net_device *dev); ++extern void ieee80211_txb_free(struct ieee80211_txb *); ++ ++ ++/* ieee80211_rx.c */ ++extern int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb, ++ struct ieee80211_rx_stats *rx_stats); ++extern void ieee80211_rx_mgt(struct ieee80211_device *ieee, ++ struct ieee80211_hdr_4addr *header, ++ struct ieee80211_rx_stats *stats); ++ ++/* ieee80211_wx.c */ ++extern int ieee80211_wx_get_scan(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *key); ++extern int ieee80211_wx_set_encode(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *key); ++extern int ieee80211_wx_get_encode(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *key); ++#if WIRELESS_EXT >= 18 ++extern int ieee80211_wx_get_encode_ext(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data* wrqu, char *extra); ++extern int ieee80211_wx_set_encode_ext(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data* wrqu, char *extra); ++extern int ieee80211_wx_set_auth(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ struct iw_param *data, char *extra); ++extern int ieee80211_wx_set_mlme(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++#endif ++extern int ieee80211_wx_set_gen_ie(struct ieee80211_device *ieee, u8 *ie, size_t len); ++ ++/* ieee80211_softmac.c */ ++extern short ieee80211_is_54g(struct ieee80211_network net); ++extern short ieee80211_is_shortslot(struct ieee80211_network net); ++extern int ieee80211_rx_frame_softmac(struct ieee80211_device *ieee, struct sk_buff *skb, ++ struct ieee80211_rx_stats *rx_stats, u16 type, ++ u16 stype); ++extern void ieee80211_softmac_new_net(struct ieee80211_device *ieee, struct ieee80211_network *net); ++ ++void SendDisassociation(struct ieee80211_device *ieee, u8* asSta, u8 asRsn); ++extern void ieee80211_softmac_xmit(struct ieee80211_txb *txb, struct ieee80211_device *ieee); ++ ++extern void ieee80211_stop_send_beacons(struct ieee80211_device *ieee); ++extern void notify_wx_assoc_event(struct ieee80211_device *ieee); ++extern void ieee80211_softmac_check_all_nets(struct ieee80211_device *ieee); ++extern void ieee80211_start_bss(struct ieee80211_device *ieee); ++extern void ieee80211_start_master_bss(struct ieee80211_device *ieee); ++extern void ieee80211_start_ibss(struct ieee80211_device *ieee); ++extern void ieee80211_softmac_init(struct ieee80211_device *ieee); ++extern void ieee80211_softmac_free(struct ieee80211_device *ieee); ++extern void ieee80211_associate_abort(struct ieee80211_device *ieee); ++extern void ieee80211_disassociate(struct ieee80211_device *ieee); ++extern void ieee80211_stop_scan(struct ieee80211_device *ieee); ++extern void ieee80211_start_scan_syncro(struct ieee80211_device *ieee); ++extern void ieee80211_check_all_nets(struct ieee80211_device *ieee); ++extern void ieee80211_start_protocol(struct ieee80211_device *ieee); ++extern void ieee80211_stop_protocol(struct ieee80211_device *ieee); ++extern void ieee80211_softmac_start_protocol(struct ieee80211_device *ieee); ++extern void ieee80211_softmac_stop_protocol(struct ieee80211_device *ieee); ++extern void ieee80211_reset_queue(struct ieee80211_device *ieee); ++extern void ieee80211_wake_queue(struct ieee80211_device *ieee); ++extern void ieee80211_stop_queue(struct ieee80211_device *ieee); ++extern struct sk_buff *ieee80211_get_beacon(struct ieee80211_device *ieee); ++extern void ieee80211_start_send_beacons(struct ieee80211_device *ieee); ++extern void ieee80211_stop_send_beacons(struct ieee80211_device *ieee); ++extern int ieee80211_wpa_supplicant_ioctl(struct ieee80211_device *ieee, struct iw_point *p); ++extern void notify_wx_assoc_event(struct ieee80211_device *ieee); ++extern void ieee80211_ps_tx_ack(struct ieee80211_device *ieee, short success); ++ ++extern void softmac_mgmt_xmit(struct sk_buff *skb, struct ieee80211_device *ieee); ++ ++/* ieee80211_crypt_ccmp&tkip&wep.c */ ++extern void ieee80211_tkip_null(void); ++extern void ieee80211_wep_null(void); ++extern void ieee80211_ccmp_null(void); ++ ++/* ieee80211_softmac_wx.c */ ++ ++extern int ieee80211_wx_get_wap(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *ext); ++ ++extern int ieee80211_wx_set_wap(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *awrq, ++ char *extra); ++ ++extern int ieee80211_wx_get_essid(struct ieee80211_device *ieee, struct iw_request_info *a,union iwreq_data *wrqu,char *b); ++ ++extern int ieee80211_wx_set_rate(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_get_rate(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_set_mode(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b); ++ ++extern int ieee80211_wx_set_scan(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b); ++ ++extern int ieee80211_wx_set_essid(struct ieee80211_device *ieee, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_get_mode(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b); ++ ++extern int ieee80211_wx_set_freq(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b); ++ ++extern int ieee80211_wx_get_freq(struct ieee80211_device *ieee, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b); ++ ++//extern void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++extern void ieee80211_wx_sync_scan_wq(struct work_struct *work); ++#else ++ extern void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee); ++#endif ++ ++ ++extern int ieee80211_wx_set_rawtx(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_get_name(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_set_power(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_get_power(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_set_rts(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++ ++extern int ieee80211_wx_get_rts(struct ieee80211_device *ieee, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++//HT ++#define MAX_RECEIVE_BUFFER_SIZE 9100 // ++extern void HTDebugHTCapability(u8* CapIE, u8* TitleString ); ++extern void HTDebugHTInfo(u8* InfoIE, u8* TitleString); ++ ++void HTSetConnectBwMode(struct ieee80211_device* ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); ++extern void HTUpdateDefaultSetting(struct ieee80211_device* ieee); ++extern void HTConstructCapabilityElement(struct ieee80211_device* ieee, u8* posHTCap, u8* len, u8 isEncrypt); ++extern void HTConstructInfoElement(struct ieee80211_device* ieee, u8* posHTInfo, u8* len, u8 isEncrypt); ++extern void HTConstructRT2RTAggElement(struct ieee80211_device* ieee, u8* posRT2RTAgg, u8* len); ++extern void HTOnAssocRsp(struct ieee80211_device *ieee); ++extern void HTInitializeHTInfo(struct ieee80211_device* ieee); ++extern void HTInitializeBssDesc(PBSS_HT pBssHT); ++extern void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork); ++extern void HTUpdateSelfAndPeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork); ++extern u8 HTGetHighestMCSRate(struct ieee80211_device* ieee, u8* pMCSRateSet, u8* pMCSFilter); ++extern u8 MCS_FILTER_ALL[]; ++extern u16 MCS_DATA_RATE[2][2][77] ; ++extern u8 HTCCheck(struct ieee80211_device* ieee, u8* pFrame); ++//extern void HTSetConnectBwModeCallback(unsigned long data); ++extern void HTResetIOTSetting(PRT_HIGH_THROUGHPUT pHTInfo); ++extern bool IsHTHalfNmodeAPs(struct ieee80211_device* ieee); ++extern u16 HTHalfMcsToDataRate(struct ieee80211_device* ieee, u8 nMcsRate); ++extern u16 HTMcsToDataRate( struct ieee80211_device* ieee, u8 nMcsRate); ++extern u16 TxCountToDataRate( struct ieee80211_device* ieee, u8 nDataRate); ++//function in BAPROC.c ++extern int ieee80211_rx_ADDBAReq( struct ieee80211_device* ieee, struct sk_buff *skb); ++extern int ieee80211_rx_ADDBARsp( struct ieee80211_device* ieee, struct sk_buff *skb); ++extern int ieee80211_rx_DELBA(struct ieee80211_device* ieee,struct sk_buff *skb); ++extern void TsInitAddBA( struct ieee80211_device* ieee, PTX_TS_RECORD pTS, u8 Policy, u8 bOverwritePending); ++extern void TsInitDelBA( struct ieee80211_device* ieee, PTS_COMMON_INFO pTsCommonInfo, TR_SELECT TxRxSelect); ++extern void BaSetupTimeOut(unsigned long data); ++extern void TxBaInactTimeout(unsigned long data); ++extern void RxBaInactTimeout(unsigned long data); ++extern void ResetBaEntry( PBA_RECORD pBA); ++//function in TS.c ++extern bool GetTs( ++ struct ieee80211_device* ieee, ++ PTS_COMMON_INFO *ppTS, ++ u8* Addr, ++ u8 TID, ++ TR_SELECT TxRxSelect, //Rx:1, Tx:0 ++ bool bAddNewTs ++ ); ++extern void TSInitialize(struct ieee80211_device *ieee); ++extern void TsStartAddBaProcess(struct ieee80211_device* ieee, PTX_TS_RECORD pTxTS); ++extern void RemovePeerTS(struct ieee80211_device* ieee, u8* Addr); ++extern void RemoveAllTS(struct ieee80211_device* ieee); ++void ieee80211_softmac_scan_syncro(struct ieee80211_device *ieee); ++ ++extern const long ieee80211_wlan_frequencies[]; ++ ++extern inline void ieee80211_increment_scans(struct ieee80211_device *ieee) ++{ ++ ieee->scans++; ++} ++ ++extern inline int ieee80211_get_scans(struct ieee80211_device *ieee) ++{ ++ return ieee->scans; ++} ++ ++static inline const char *escape_essid(const char *essid, u8 essid_len) { ++ static char escaped[IW_ESSID_MAX_SIZE * 2 + 1]; ++ const char *s = essid; ++ char *d = escaped; ++ ++ if (ieee80211_is_empty_essid(essid, essid_len)) { ++ memcpy(escaped, "", sizeof("")); ++ return escaped; ++ } ++ ++ essid_len = min(essid_len, (u8)IW_ESSID_MAX_SIZE); ++ while (essid_len--) { ++ if (*s == '\0') { ++ *d++ = '\\'; ++ *d++ = '0'; ++ s++; ++ } else { ++ *d++ = *s++; ++ } ++ } ++ *d = '\0'; ++ return escaped; ++} ++ ++/* For the function is more related to hardware setting, it's better to use the ++ * ieee handler to refer to it. ++ */ ++extern short check_nic_enough_desc(struct net_device *dev, int queue_index); ++extern int ieee80211_data_xmit(struct sk_buff *skb, struct net_device *dev); ++extern int ieee80211_parse_info_param(struct ieee80211_device *ieee, ++ struct ieee80211_info_element *info_element, ++ u16 length, ++ struct ieee80211_network *network, ++ struct ieee80211_rx_stats *stats); ++ ++void ieee80211_indicate_packets(struct ieee80211_device *ieee, struct ieee80211_rxb** prxbIndicateArray,u8 index); ++#define RT_ASOC_RETRY_LIMIT 5 ++#endif /* IEEE80211_H */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/Kconfig linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/Kconfig +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/Kconfig 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,6 @@ ++config RTL8192E ++ tristate "RealTek RTL8192E Wireless LAN NIC driver" ++ depends on PCI ++ depends on WIRELESS_EXT ++ default N ++ ---help--- +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/Makefile linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/Makefile +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/Makefile 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,34 @@ ++NIC_SELECT = RTL8192E ++ ++ ++EXTRA_CFLAGS += -DRTL8192E ++EXTRA_CFLAGS += -std=gnu89 ++EXTRA_CFLAGS += -O2 ++EXTRA_CFLAGS += -DTHOMAS_TURBO ++EXTRA_CFLAGS += -DENABLE_DOT11D ++ ++r8192_pci-objs := \ ++ r8192E_core.o \ ++ r8180_93cx6.o \ ++ r8192E_wx.o \ ++ r8190_rtl8256.o \ ++ r819xE_phy.o \ ++ r819xE_firmware.o \ ++ r819xE_cmdpkt.o \ ++ r8192E_dm.o \ ++ ieee80211/ieee80211_rx.o \ ++ ieee80211/ieee80211_softmac.o \ ++ ieee80211/ieee80211_tx.o \ ++ ieee80211/ieee80211_wx.o \ ++ ieee80211/ieee80211_module.o \ ++ ieee80211/ieee80211_softmac_wx.o \ ++ ieee80211/rtl819x_HTProc.o \ ++ ieee80211/rtl819x_TSProc.o \ ++ ieee80211/rtl819x_BAProc.o \ ++ ieee80211/dot11d.o \ ++ ieee80211/ieee80211_crypt.o \ ++ ieee80211/ieee80211_crypt_tkip.o \ ++ ieee80211/ieee80211_crypt_ccmp.o \ ++ ieee80211/ieee80211_crypt_wep.o ++ ++obj-$(CONFIG_RTL8192E) += r8192_pci.o +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r8180_93cx6.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8180_93cx6.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8180_93cx6.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,146 @@ ++/* ++ This files contains card eeprom (93c46 or 93c56) programming routines, ++ memory is addressed by 16 bits words. ++ ++ This is part of rtl8180 OpenSource driver. ++ Copyright (C) Andrea Merello 2004 ++ Released under the terms of GPL (General Public Licence) ++ ++ Parts of this driver are based on the GPL part of the ++ official realtek driver. ++ ++ Parts of this driver are based on the rtl8180 driver skeleton ++ from Patric Schenke & Andres Salomon. ++ ++ Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver. ++ ++ We want to tanks the Authors of those projects and the Ndiswrapper ++ project Authors. ++*/ ++ ++#include "r8180_93cx6.h" ++ ++static void eprom_cs(struct net_device *dev, short bit) ++{ ++ if(bit) ++ write_nic_byte(dev, EPROM_CMD, ++ (1<epromtype==EPROM_93c56){ ++ addr_str[7]=addr & 1; ++ addr_str[6]=addr & (1<<1); ++ addr_str[5]=addr & (1<<2); ++ addr_str[4]=addr & (1<<3); ++ addr_str[3]=addr & (1<<4); ++ addr_str[2]=addr & (1<<5); ++ addr_str[1]=addr & (1<<6); ++ addr_str[0]=addr & (1<<7); ++ addr_len=8; ++ }else{ ++ addr_str[5]=addr & 1; ++ addr_str[4]=addr & (1<<1); ++ addr_str[3]=addr & (1<<2); ++ addr_str[2]=addr & (1<<3); ++ addr_str[1]=addr & (1<<4); ++ addr_str[0]=addr & (1<<5); ++ addr_len=6; ++ } ++ eprom_cs(dev, 1); ++ eprom_ck_cycle(dev); ++ eprom_send_bits_string(dev, read_cmd, 3); ++ eprom_send_bits_string(dev, addr_str, addr_len); ++ ++ //keep chip pin D to low state while reading. ++ //I'm unsure if it is necessary, but anyway shouldn't hurt ++ eprom_w(dev, 0); ++ ++ for(i=0;i<16;i++){ ++ //eeprom needs a clk cycle between writing opcode&adr ++ //and reading data. (eeprom outs a dummy 0) ++ eprom_ck_cycle(dev); ++ ret |= (eprom_r(dev)<<(15-i)); ++ } ++ ++ eprom_cs(dev, 0); ++ eprom_ck_cycle(dev); ++ ++ //disable EPROM programming ++ write_nic_byte(dev, EPROM_CMD, ++ (EPROM_CMD_NORMAL< ++ Released under the terms of GPL (General Public Licence) ++ ++ Parts of this driver are based on the GPL part of the official realtek driver ++ Parts of this driver are based on the rtl8180 driver skeleton from Patric Schenke & Andres Salomon ++ Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver ++ ++ We want to tanks the Authors of such projects and the Ndiswrapper project Authors. ++*/ ++ ++/*This files contains card eeprom (93c46 or 93c56) programming routines*/ ++/*memory is addressed by WORDS*/ ++ ++#include "r8192E.h" ++#include "r8192E_hw.h" ++ ++#define EPROM_DELAY 10 ++ ++#define EPROM_ANAPARAM_ADDRLWORD 0xd ++#define EPROM_ANAPARAM_ADDRHWORD 0xe ++ ++#define EPROM_RFCHIPID 0x6 ++#define EPROM_TXPW_BASE 0x05 ++#define EPROM_RFCHIPID_RTL8225U 5 ++#define EPROM_RF_PARAM 0x4 ++#define EPROM_CONFIG2 0xc ++ ++#define EPROM_VERSION 0x1E ++#define MAC_ADR 0x7 ++ ++#define CIS 0x18 ++ ++#define EPROM_TXPW0 0x16 ++#define EPROM_TXPW2 0x1b ++#define EPROM_TXPW1 0x3d ++ ++ ++u32 eprom_read(struct net_device *dev,u32 addr); //reads a 16 bits word +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r8190_rtl8256.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8190_rtl8256.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8190_rtl8256.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,1161 @@ ++/* ++ This is part of the rtl8192 driver ++ released under the GPL (See file COPYING for details). ++ ++ This files contains programming code for the rtl8256 ++ radio frontend. ++ ++ *Many* thanks to Realtek Corp. for their great support! ++ ++*/ ++ ++#include "r8192E.h" ++#include "r8192E_hw.h" ++#include "r819xE_phyreg.h" ++#include "r819xE_phy.h" ++#include "r8190_rtl8256.h" ++ ++/*-------------------------------------------------------------------------- ++ * Overview: set RF band width (20M or 40M) ++ * Input: struct net_device* dev ++ * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M ++ * Output: NONE ++ * Return: NONE ++ * Note: 8226 support both 20M and 40 MHz ++ *---------------------------------------------------------------------------*/ ++void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) //20M or 40M ++{ ++ u8 eRFPath; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ //for(eRFPath = RF90_PATH_A; eRFPath NumTotalRFPath; eRFPath++) ++ for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ { ++ if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) ++ continue; ++ ++ switch(Bandwidth) ++ { ++ case HT_CHANNEL_WIDTH_20: ++ if(priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE)// 8256 D-cut, E-cut, xiong: consider it later! ++ { ++ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba ++ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7); ++ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021); ++ ++ //cosa add for sd3's request 01/23/2008 ++ //rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab); ++ } ++ else ++ { ++ RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n"); ++ } ++ ++ break; ++ case HT_CHANNEL_WIDTH_20_40: ++ if(priv->card_8192_version == VERSION_8190_BD ||priv->card_8192_version == VERSION_8190_BE)// 8256 D-cut, E-cut, xiong: consider it later! ++ { ++ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba ++ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3ff); ++ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0e1); ++ ++ //cosa add for sd3's request 01/23/2008 ++ #if 0 ++ if(priv->chan == 3 || priv->chan == 9) //I need to set priv->chan whenever current channel changes ++ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b); ++ else ++ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab); ++ #endif ++ } ++ else ++ { ++ RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n"); ++ } ++ ++ ++ break; ++ default: ++ RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ); ++ break; ++ ++ } ++ } ++ return; ++} ++/*-------------------------------------------------------------------------- ++ * Overview: Interface to config 8256 ++ * Input: struct net_device* dev ++ * Output: NONE ++ * Return: NONE ++ *---------------------------------------------------------------------------*/ ++RT_STATUS PHY_RF8256_Config(struct net_device* dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ // Initialize general global value ++ // ++ RT_STATUS rtStatus = RT_STATUS_SUCCESS; ++ // TODO: Extend RF_PATH_C and RF_PATH_D in the future ++ priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH; ++ // Config BB and RF ++ rtStatus = phy_RF8256_Config_ParaFile(dev); ++ ++ return rtStatus; ++} ++/*-------------------------------------------------------------------------- ++ * Overview: Interface to config 8256 ++ * Input: struct net_device* dev ++ * Output: NONE ++ * Return: NONE ++ *---------------------------------------------------------------------------*/ ++RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev) ++{ ++ u32 u4RegValue = 0; ++ u8 eRFPath; ++ RT_STATUS rtStatus = RT_STATUS_SUCCESS; ++ BB_REGISTER_DEFINITION_T *pPhyReg; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u32 RegOffSetToBeCheck = 0x3; ++ u32 RegValueToBeCheck = 0x7f1; ++ u32 RF3_Final_Value = 0; ++ u8 ConstRetryTimes = 5, RetryTimes = 5; ++ u8 ret = 0; ++ //3//----------------------------------------------------------------- ++ //3// <2> Initialize RF ++ //3//----------------------------------------------------------------- ++ for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath NumTotalRFPath; eRFPath++) ++ { ++ if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) ++ continue; ++ ++ pPhyReg = &priv->PHYRegDef[eRFPath]; ++ ++ // Joseph test for shorten RF config ++ // pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord); ++ ++ /*----Store original RFENV control type----*/ ++ switch(eRFPath) ++ { ++ case RF90_PATH_A: ++ case RF90_PATH_C: ++ u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); ++ break; ++ case RF90_PATH_B : ++ case RF90_PATH_D: ++ u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); ++ break; ++ } ++ ++ /*----Set RF_ENV enable----*/ ++ rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); ++ ++ /*----Set RF_ENV output high----*/ ++ rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); ++ ++ /* Set bit number of Address and Data for RF register */ ++ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 ++ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? ++ ++ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf); ++ ++ /*----Check RF block (for FPGA platform only)----*/ ++ // TODO: this function should be removed on ASIC , Emily 2007.2.2 ++ rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath); ++ if(rtStatus!= RT_STATUS_SUCCESS) ++ { ++ RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath); ++ goto phy_RF8256_Config_ParaFile_Fail; ++ } ++ ++ RetryTimes = ConstRetryTimes; ++ RF3_Final_Value = 0; ++ /*----Initialize RF fom connfiguration file----*/ ++ switch(eRFPath) ++ { ++ case RF90_PATH_A: ++ while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) ++ { ++ ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); ++ RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); ++ RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); ++ RetryTimes--; ++ } ++ break; ++ case RF90_PATH_B: ++ while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) ++ { ++ ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); ++ RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); ++ RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); ++ RetryTimes--; ++ } ++ break; ++ case RF90_PATH_C: ++ while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) ++ { ++ ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); ++ RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); ++ RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); ++ RetryTimes--; ++ } ++ break; ++ case RF90_PATH_D: ++ while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) ++ { ++ ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); ++ RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); ++ RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); ++ RetryTimes--; ++ } ++ break; ++ } ++ ++ /*----Restore RFENV control type----*/; ++ switch(eRFPath) ++ { ++ case RF90_PATH_A: ++ case RF90_PATH_C: ++ rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); ++ break; ++ case RF90_PATH_B : ++ case RF90_PATH_D: ++ rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); ++ break; ++ } ++ ++ if(ret){ ++ RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath); ++ goto phy_RF8256_Config_ParaFile_Fail; ++ } ++ ++ } ++ ++ RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ; ++ return RT_STATUS_SUCCESS; ++ ++phy_RF8256_Config_ParaFile_Fail: ++ RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ; ++ return RT_STATUS_FAILURE; ++} ++ ++ ++void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel) ++{ ++ u32 TxAGC=0; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#ifdef RTL8190P ++ u8 byte0, byte1; ++ ++ TxAGC |= ((powerlevel<<8)|powerlevel); ++ TxAGC += priv->CCKTxPowerLevelOriginalOffset; ++ ++ if(priv->bDynamicTxLowPower == true //cosa 04282008 for cck long range ++ /*pMgntInfo->bScanInProgress == TRUE*/ ) //cosa 05/22/2008 for scan ++ { ++ if(priv->CustomerID == RT_CID_819x_Netcore) ++ TxAGC = 0x2222; ++ else ++ TxAGC += ((priv->CckPwEnl<<8)|priv->CckPwEnl); ++ } ++ ++ byte0 = (u8)(TxAGC & 0xff); ++ byte1 = (u8)((TxAGC & 0xff00)>>8); ++ if(byte0 > 0x24) ++ byte0 = 0x24; ++ if(byte1 > 0x24) ++ byte1 = 0x24; ++ if(priv->rf_type == RF_2T4R) //Only 2T4R you have to care the Antenna Tx Power offset ++ { // check antenna C over the max index 0x24 ++ if(priv->RF_C_TxPwDiff > 0) ++ { ++ if( (byte0 + (u8)priv->RF_C_TxPwDiff) > 0x24) ++ byte0 = 0x24 - priv->RF_C_TxPwDiff; ++ if( (byte1 + (u8)priv->RF_C_TxPwDiff) > 0x24) ++ byte1 = 0x24 - priv->RF_C_TxPwDiff; ++ } ++ } ++ TxAGC = (byte1<<8) |byte0; ++ write_nic_dword(dev, CCK_TXAGC, TxAGC); ++#else ++ #ifdef RTL8192E ++ ++ TxAGC = powerlevel; ++ if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range ++ { ++ if(priv->CustomerID == RT_CID_819x_Netcore) ++ TxAGC = 0x22; ++ else ++ TxAGC += priv->CckPwEnl; ++ } ++ if(TxAGC > 0x24) ++ TxAGC = 0x24; ++ rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); ++ #endif ++#endif ++} ++ ++ ++void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ //Joseph TxPower for 8192 testing ++#ifdef RTL8190P ++ u32 TxAGC1=0, TxAGC2=0, TxAGC2_tmp = 0; ++ u8 i, byteVal1[4], byteVal2[4], byteVal3[4]; ++ ++ if(priv->bDynamicTxHighPower == true) //Add by Jacken 2008/03/06 ++ { ++ TxAGC1 |= ((powerlevel<<24)|(powerlevel<<16)|(powerlevel<<8)|powerlevel); ++ //for tx power track ++ TxAGC2_tmp = TxAGC1; ++ ++ TxAGC1 += priv->MCSTxPowerLevelOriginalOffset[0]; ++ TxAGC2 =0x03030303; ++ ++ //for tx power track ++ TxAGC2_tmp += priv->MCSTxPowerLevelOriginalOffset[1]; ++ } ++ else ++ { ++ TxAGC1 |= ((powerlevel<<24)|(powerlevel<<16)|(powerlevel<<8)|powerlevel); ++ TxAGC2 = TxAGC1; ++ ++ TxAGC1 += priv->MCSTxPowerLevelOriginalOffset[0]; ++ TxAGC2 += priv->MCSTxPowerLevelOriginalOffset[1]; ++ ++ TxAGC2_tmp = TxAGC2; ++ ++ } ++ for(i=0; i<4; i++) ++ { ++ byteVal1[i] = (u8)( (TxAGC1 & (0xff<<(i*8))) >>(i*8) ); ++ if(byteVal1[i] > 0x24) ++ byteVal1[i] = 0x24; ++ byteVal2[i] = (u8)( (TxAGC2 & (0xff<<(i*8))) >>(i*8) ); ++ if(byteVal2[i] > 0x24) ++ byteVal2[i] = 0x24; ++ ++ //for tx power track ++ byteVal3[i] = (u8)( (TxAGC2_tmp & (0xff<<(i*8))) >>(i*8) ); ++ if(byteVal3[i] > 0x24) ++ byteVal3[i] = 0x24; ++ } ++ ++ if(priv->rf_type == RF_2T4R) //Only 2T4R you have to care the Antenna Tx Power offset ++ { // check antenna C over the max index 0x24 ++ if(priv->RF_C_TxPwDiff > 0) ++ { ++ for(i=0; i<4; i++) ++ { ++ if( (byteVal1[i] + (u8)priv->RF_C_TxPwDiff) > 0x24) ++ byteVal1[i] = 0x24 - priv->RF_C_TxPwDiff; ++ if( (byteVal2[i] + (u8)priv->RF_C_TxPwDiff) > 0x24) ++ byteVal2[i] = 0x24 - priv->RF_C_TxPwDiff; ++ if( (byteVal3[i] + (u8)priv->RF_C_TxPwDiff) > 0x24) ++ byteVal3[i] = 0x24 - priv->RF_C_TxPwDiff; ++ } ++ } ++ } ++ ++ TxAGC1 = (byteVal1[3]<<24) | (byteVal1[2]<<16) |(byteVal1[1]<<8) |byteVal1[0]; ++ TxAGC2 = (byteVal2[3]<<24) | (byteVal2[2]<<16) |(byteVal2[1]<<8) |byteVal2[0]; ++ ++ //for tx power track ++ TxAGC2_tmp = (byteVal3[3]<<24) | (byteVal3[2]<<16) |(byteVal3[1]<<8) |byteVal3[0]; ++ priv->Pwr_Track = TxAGC2_tmp; ++ //DbgPrint("TxAGC2_tmp = 0x%x\n", TxAGC2_tmp); ++ ++ //DbgPrint("TxAGC1/TxAGC2 = 0x%x/0x%x\n", TxAGC1, TxAGC2); ++ write_nic_dword(dev, MCS_TXAGC, TxAGC1); ++ write_nic_dword(dev, MCS_TXAGC+4, TxAGC2); ++#else ++#ifdef RTL8192E ++ u32 writeVal, powerBase0, powerBase1, writeVal_tmp; ++ u8 index = 0; ++ u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; ++ u8 byte0, byte1, byte2, byte3; ++ ++ powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff; //OFDM rates ++ powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; ++ powerBase1 = powerlevel; //MCS rates ++ powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; ++ ++ for(index=0; index<6; index++) ++ { ++ writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1); ++ byte0 = (u8)(writeVal & 0x7f); ++ byte1 = (u8)((writeVal & 0x7f00)>>8); ++ byte2 = (u8)((writeVal & 0x7f0000)>>16); ++ byte3 = (u8)((writeVal & 0x7f000000)>>24); ++ if(byte0 > 0x24) // Max power index = 0x24 ++ byte0 = 0x24; ++ if(byte1 > 0x24) ++ byte1 = 0x24; ++ if(byte2 > 0x24) ++ byte2 = 0x24; ++ if(byte3 > 0x24) ++ byte3 = 0x24; ++ ++ if(index == 3) ++ { ++ writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; ++ priv->Pwr_Track = writeVal_tmp; ++ } ++ ++ if(priv->bDynamicTxHighPower == true) //Add by Jacken 2008/03/06 //when DM implement, add this ++ { ++ writeVal = 0x03030303; ++ } ++ else ++ { ++ writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; ++ } ++ rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); ++ } ++ ++#endif ++#endif ++ return; ++} ++ ++#define MAX_DOZE_WAITING_TIMES_9x 64 ++static bool ++SetRFPowerState8190( ++ struct net_device* dev, ++ RT_RF_POWER_STATE eRFPowerState ++ ) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl)); ++ bool bResult = true; ++ //u8 eRFPath; ++ u8 i = 0, QueueID = 0; ++ ptx_ring head=NULL,tail=NULL; ++ ++ if(priv->SetRFPowerStateInProgress == true) ++ return false; ++ RT_TRACE(COMP_POWER, "===========> SetRFPowerState8190()!\n"); ++ priv->SetRFPowerStateInProgress = true; ++ ++ switch(priv->rf_chip) ++ { ++ case RF_8256: ++ switch( eRFPowerState ) ++ { ++ case eRfOn: ++ RT_TRACE(COMP_POWER, "SetRFPowerState8190() eRfOn !\n"); ++ //RXTX enable control: On ++ //for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ // PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x2); ++ #ifdef RTL8190P ++ if(priv->rf_type == RF_2T4R) ++ { ++ //enable RF-Chip A/B ++ rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] ++ //enable RF-Chip C/D ++ rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4] ++ //analog to digital on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8] ++ //digital to analog on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0xf); // 0x880[8:5] ++ //rx antenna on ++ rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0xf);// 0xc04[3:0] ++ //rx antenna on ++ rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0xf);// 0xd04[3:0] ++ //analog to digital part2 on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0xf); // 0x880[12:9] ++ } ++ else if(priv->rf_type == RF_1T2R) //RF-C, RF-D ++ { ++ //enable RF-Chip C/D ++ rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4] ++ //analog to digital on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10] ++ //digital to analog on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x180, 0x3); // 0x880[8:7] ++ //rx antenna on ++ rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xc, 0x3);// 0xc04[3:2] ++ //rx antenna on ++ rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xc, 0x3);// 0xd04[3:2] ++ //analog to digital part2 on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1800, 0x3); // 0x880[12:11] ++ } ++ #else ++ write_nic_byte(dev, ANAPAR, 0x37);//160MHz ++ write_nic_byte(dev, MacBlkCtrl, 0x17); // 0x403 ++ mdelay(1); ++ //enable clock 80/88 MHz ++ ++ priv->bHwRfOffAction = 0; ++ //} ++ ++ // Baseband reset 2008.09.30 add ++ write_nic_byte(dev, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0)); ++ ++ //2 AFE ++ // 2008.09.30 add ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x20000000, 0x1); // 0x884 ++ //analog to digital part2 on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] ++ //digital to analog on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x98, 0x13); // 0x880[4:3] ++ //analog to digital on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf03, 0xf03);// 0x88c[9:8] ++ //rx antenna on ++ //PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] ++ //rx antenna on 2008.09.30 mark ++ //PHY_SetBBReg(Adapter, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] ++ ++ //2 RF ++ //enable RF-Chip A/B ++ rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] ++ rtl8192_setBBreg(dev, rFPGA0_XB_RFInterfaceOE, BIT4, 0x1); // 0x864[4] ++ #endif ++ break; ++ ++ // ++ // In current solution, RFSleep=RFOff in order to save power under 802.11 power save. ++ // By Bruce, 2008-01-16. ++ // ++ case eRfSleep: ++ case eRfOff: ++ RT_TRACE(COMP_POWER, "SetRFPowerState8190() eRfOff/Sleep !\n"); ++ if (pPSC->bLeisurePs) ++ { ++ for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) ++ { ++ switch(QueueID) { ++ case MGNT_QUEUE: ++ tail=priv->txmapringtail; ++ head=priv->txmapringhead; ++ break; ++ ++ case BK_QUEUE: ++ tail=priv->txbkpringtail; ++ head=priv->txbkpringhead; ++ break; ++ ++ case BE_QUEUE: ++ tail=priv->txbepringtail; ++ head=priv->txbepringhead; ++ break; ++ ++ case VI_QUEUE: ++ tail=priv->txvipringtail; ++ head=priv->txvipringhead; ++ break; ++ ++ case VO_QUEUE: ++ tail=priv->txvopringtail; ++ head=priv->txvopringhead; ++ break; ++ ++ default: ++ tail=head=NULL; ++ break; ++ } ++ if(tail == head) ++ { ++ //DbgPrint("QueueID = %d", QueueID); ++ QueueID++; ++ continue; ++ } ++ else ++ { ++ RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times BusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); ++ udelay(10); ++ i++; ++ } ++ ++ if(i >= MAX_DOZE_WAITING_TIMES_9x) ++ { ++ RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times BusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); ++ break; ++ } ++ } ++ } ++ #ifdef RTL8190P ++ if(priv->rf_type == RF_2T4R) ++ { ++ //disable RF-Chip A/B ++ rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] ++ } ++ //disable RF-Chip C/D ++ rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x0); // 0x868[4] ++ //analog to digital off, for power save ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] ++ //digital to analog off, for power save ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0x0); // 0x880[8:5] ++ //rx antenna off ++ rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0] ++ //rx antenna off ++ rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0] ++ //analog to digital part2 off, for power save ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0x0); // 0x880[12:9] ++#else //8192E ++ //2 RF ++ //disable RF-Chip A/B ++ rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] ++ rtl8192_setBBreg(dev, rFPGA0_XB_RFInterfaceOE, BIT4, 0x0); // 0x864[4] ++ //2 AFE ++ //analog to digital off, for power save ++ //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf03, 0x0); // 2008.09.30 Modify ++ //digital to analog off, for power save ++ //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3] ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x98, 0x0); // 0x880 2008.09.30 Modify ++ //rx antenna off 2008.09.30 mark ++ //PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0] ++ //rx antenna off 2008.09.30 mark ++ //PHY_SetBBReg(Adapter, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0] ++ //analog to digital part2 off, for power save ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5] ++ // 2008.09.30 add ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x20000000, 0x0); // 0x884 ++ ++ ++ //disable clock 80/88 MHz 2008.09.30 mark ++ //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, 0x4, 0x0); // 0x880[2] ++ //2 BB ++ // Baseband reset 2008.09.30 add ++ write_nic_byte(dev, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0)); // 0x101 ++ //MAC: off ++ write_nic_byte(dev, MacBlkCtrl, 0x0); // 0x403 ++ //slow down cpu/lbus clock from 160MHz to Lower ++ write_nic_byte(dev, ANAPAR, 0x07); // 0x 17 40MHz ++ priv->bHwRfOffAction = 0; ++ //} ++ #endif ++ break; ++ ++ default: ++ bResult = false; ++ RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState); ++ break; ++ } ++ ++ break; ++ ++ default: ++ RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); ++ break; ++ } ++ ++ if(bResult) ++ { ++ // Update current RF state variable. ++ priv->ieee80211->eRFPowerState = eRFPowerState; ++ ++ switch(priv->rf_chip ) ++ { ++ case RF_8256: ++ switch(priv->ieee80211->eRFPowerState) ++ { ++ case eRfOff: ++ // ++ //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015 ++ // ++ if(priv->ieee80211->RfOffReason==RF_CHANGE_BY_IPS ) ++ { ++ #ifdef TO_DO ++ Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK); ++ #endif ++ } ++ else ++ { ++ // Turn off LED if RF is not ON. ++ #ifdef TO_DO ++ Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF); ++ #endif ++ } ++ break; ++ ++ case eRfOn: ++ // Turn on RF we are still linked, which might happen when ++ // we quickly turn off and on HW RF. 2006.05.12, by rcnjko. ++ if( priv->ieee80211->state == IEEE80211_LINKED) ++ { ++ #ifdef TO_DO ++ Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK); ++ #endif ++ } ++ else ++ { ++ // Turn off LED if RF is not ON. ++ #ifdef TO_DO ++ Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); ++ #endif ++ } ++ break; ++ ++ default: ++ // do nothing. ++ break; ++ }// Switch RF state ++ ++ break; ++ ++ default: ++ RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); ++ break; ++ }// Switch RFChipID ++ } ++ ++ priv->SetRFPowerStateInProgress = false; ++ RT_TRACE(COMP_POWER, "<=========== SetRFPowerState8190() bResult = %d!\n", bResult); ++ return bResult; ++} ++ ++ ++ ++// ++// Description: ++// Change RF power state. ++// ++// Assumption: ++// This function must be executed in re-schdulable context, ++// ie. PASSIVE_LEVEL. ++// ++// 050823, by rcnjko. ++// ++static bool ++SetRFPowerState( ++ struct net_device* dev, ++ RT_RF_POWER_STATE eRFPowerState ++ ) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ bool bResult = false; ++ ++ RT_TRACE(COMP_RF,"---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState); ++#ifdef RTL8192E ++ if(eRFPowerState == priv->ieee80211->eRFPowerState && priv->bHwRfOffAction == 0) ++#else ++ if(eRFPowerState == priv->ieee80211->eRFPowerState) ++#endif ++ { ++ RT_TRACE(COMP_POWER, "<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState); ++ return bResult; ++ } ++ ++ bResult = SetRFPowerState8190(dev, eRFPowerState); ++ ++ RT_TRACE(COMP_POWER, "<--------- SetRFPowerState(): bResult(%d)\n", bResult); ++ ++ return bResult; ++} ++ ++static void ++MgntDisconnectIBSS( ++ struct net_device* dev ++) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ //RT_OP_MODE OpMode; ++ u8 i; ++ bool bFilterOutNonAssociatedBSSID = false; ++ ++ //IEEE80211_DEBUG(IEEE80211_DL_TRACE, "XXXXXXXXXX MgntDisconnect IBSS\n"); ++ ++ priv->ieee80211->state = IEEE80211_NOLINK; ++ ++// PlatformZeroMemory( pMgntInfo->Bssid, 6 ); ++ for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i]= 0x55; ++ priv->OpMode = RT_OP_MODE_NO_LINK; ++ write_nic_word(dev, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]); ++ write_nic_dword(dev, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]); ++ { ++ RT_OP_MODE OpMode = priv->OpMode; ++ //LED_CTL_MODE LedAction = LED_CTL_NO_LINK; ++ u8 btMsr = read_nic_byte(dev, MSR); ++ ++ btMsr &= 0xfc; ++ ++ switch(OpMode) ++ { ++ case RT_OP_MODE_INFRASTRUCTURE: ++ btMsr |= MSR_LINK_MANAGED; ++ //LedAction = LED_CTL_LINK; ++ break; ++ ++ case RT_OP_MODE_IBSS: ++ btMsr |= MSR_LINK_ADHOC; ++ // led link set seperate ++ break; ++ ++ case RT_OP_MODE_AP: ++ btMsr |= MSR_LINK_MASTER; ++ //LedAction = LED_CTL_LINK; ++ break; ++ ++ default: ++ btMsr |= MSR_LINK_NONE; ++ break; ++ } ++ ++ write_nic_byte(dev, MSR, btMsr); ++ ++ // LED control ++ //Adapter->HalFunc.LedControlHandler(Adapter, LedAction); ++ } ++ ieee80211_stop_send_beacons(priv->ieee80211); ++ ++ // If disconnect, clear RCR CBSSID bit ++ bFilterOutNonAssociatedBSSID = false; ++ { ++ u32 RegRCR, Type; ++ Type = bFilterOutNonAssociatedBSSID; ++ RegRCR = read_nic_dword(dev,RCR); ++ priv->ReceiveConfig = RegRCR; ++ if (Type == true) ++ RegRCR |= (RCR_CBSSID); ++ else if (Type == false) ++ RegRCR &= (~RCR_CBSSID); ++ ++ { ++ write_nic_dword(dev, RCR,RegRCR); ++ priv->ReceiveConfig = RegRCR; ++ } ++ ++ } ++ //MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE ); ++ notify_wx_assoc_event(priv->ieee80211); ++ ++} ++ ++static void ++MlmeDisassociateRequest( ++ struct net_device* dev, ++ u8* asSta, ++ u8 asRsn ++ ) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 i; ++ ++ RemovePeerTS(priv->ieee80211, asSta); ++ ++ SendDisassociation( priv->ieee80211, asSta, asRsn ); ++ ++ if(memcpy(priv->ieee80211->current_network.bssid,asSta,6) == NULL) ++ { ++ //ShuChen TODO: change media status. ++ //ShuChen TODO: What to do when disassociate. ++ priv->ieee80211->state = IEEE80211_NOLINK; ++ //pMgntInfo->AsocTimestamp = 0; ++ for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x22; ++// pMgntInfo->mBrates.Length = 0; ++// Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) ); ++ priv->OpMode = RT_OP_MODE_NO_LINK; ++ { ++ RT_OP_MODE OpMode = priv->OpMode; ++ //LED_CTL_MODE LedAction = LED_CTL_NO_LINK; ++ u8 btMsr = read_nic_byte(dev, MSR); ++ ++ btMsr &= 0xfc; ++ ++ switch(OpMode) ++ { ++ case RT_OP_MODE_INFRASTRUCTURE: ++ btMsr |= MSR_LINK_MANAGED; ++ //LedAction = LED_CTL_LINK; ++ break; ++ ++ case RT_OP_MODE_IBSS: ++ btMsr |= MSR_LINK_ADHOC; ++ // led link set seperate ++ break; ++ ++ case RT_OP_MODE_AP: ++ btMsr |= MSR_LINK_MASTER; ++ //LedAction = LED_CTL_LINK; ++ break; ++ ++ default: ++ btMsr |= MSR_LINK_NONE; ++ break; ++ } ++ ++ write_nic_byte(dev, MSR, btMsr); ++ ++ // LED control ++ //Adapter->HalFunc.LedControlHandler(Adapter, LedAction); ++ } ++ ieee80211_disassociate(priv->ieee80211); ++ ++ write_nic_word(dev, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]); ++ write_nic_dword(dev, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]); ++ ++ } ++ ++} ++ ++ ++static void ++MgntDisconnectAP( ++ struct net_device* dev, ++ u8 asRsn ++) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ bool bFilterOutNonAssociatedBSSID = false; ++ ++// ++// Commented out by rcnjko, 2005.01.27: ++// I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE(). ++// ++// //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success ++// SecClearAllKeys(Adapter); ++ ++ // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking. ++#ifdef TO_DO ++ if( pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch || ++ (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) ) // In CCKM mode will Clear key ++ { ++ SecClearAllKeys(Adapter); ++ RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key...")) ++ } ++#endif ++ // If disconnect, clear RCR CBSSID bit ++ bFilterOutNonAssociatedBSSID = false; ++ { ++ u32 RegRCR, Type; ++ ++ Type = bFilterOutNonAssociatedBSSID; ++ //Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RCR, (pu1Byte)(&RegRCR)); ++ RegRCR = read_nic_dword(dev,RCR); ++ priv->ReceiveConfig = RegRCR; ++ ++ if (Type == true) ++ RegRCR |= (RCR_CBSSID); ++ else if (Type == false) ++ RegRCR &= (~RCR_CBSSID); ++ ++ write_nic_dword(dev, RCR,RegRCR); ++ priv->ReceiveConfig = RegRCR; ++ ++ ++ } ++ // 2004.10.11, by rcnjko. ++ //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss ); ++ MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn ); ++ ++ priv->ieee80211->state = IEEE80211_NOLINK; ++ //pMgntInfo->AsocTimestamp = 0; ++} ++ ++ ++static bool ++MgntDisconnect( ++ struct net_device* dev, ++ u8 asRsn ++) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ // ++ // Schedule an workitem to wake up for ps mode, 070109, by rcnjko. ++ // ++#ifdef TO_DO ++ if(pMgntInfo->mPss != eAwake) ++ { ++ // ++ // Using AwkaeTimer to prevent mismatch ps state. ++ // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31. ++ // ++ // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) ); ++ PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 ); ++ } ++#endif ++ // Follow 8180 AP mode, 2005.05.30, by rcnjko. ++#ifdef TO_DO ++ if(pMgntInfo->mActingAsAp) ++ { ++ RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> AP_DisassociateAllStation\n")); ++ AP_DisassociateAllStation(Adapter, unspec_reason); ++ return TRUE; ++ } ++#endif ++ // Indication of disassociation event. ++ //DrvIFIndicateDisassociation(Adapter, asRsn); ++ ++ // In adhoc mode, update beacon frame. ++ if( priv->ieee80211->state == IEEE80211_LINKED ) ++ { ++ if( priv->ieee80211->iw_mode == IW_MODE_ADHOC ) ++ { ++ //RT_TRACE(COMP_MLME, "MgntDisconnect() ===> MgntDisconnectIBSS\n"); ++ MgntDisconnectIBSS(dev); ++ } ++ if( priv->ieee80211->iw_mode == IW_MODE_INFRA ) ++ { ++ // We clear key here instead of MgntDisconnectAP() because that ++ // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS, ++ // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is ++ // used to handle disassociation related things to AP, e.g. send Disassoc ++ // frame to AP. 2005.01.27, by rcnjko. ++ //IEEE80211_DEBUG(IEEE80211_DL_TRACE,"MgntDisconnect() ===> MgntDisconnectAP\n"); ++ MgntDisconnectAP(dev, asRsn); ++ } ++ ++ // Inidicate Disconnect, 2005.02.23, by rcnjko. ++ //MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE); ++ } ++ ++ return true; ++} ++ ++// ++// Description: ++// Chang RF Power State. ++// Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE. ++// ++// Assumption: ++// PASSIVE LEVEL. ++// ++bool ++MgntActSet_RF_State( ++ struct net_device* dev, ++ RT_RF_POWER_STATE StateToSet, ++ RT_RF_CHANGE_SOURCE ChangeSource ++ ) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ bool bActionAllowed = false; ++ bool bConnectBySSID = false; ++ RT_RF_POWER_STATE rtState; ++ u16 RFWaitCounter = 0; ++ unsigned long flag; ++ RT_TRACE(COMP_POWER, "===>MgntActSet_RF_State(): StateToSet(%d)\n",StateToSet); ++ ++ //1// ++ //1//<1>Prevent the race condition of RF state change. ++ //1// ++ // Only one thread can change the RF state at one time, and others should wait to be executed. By Bruce, 2007-11-28. ++ ++ while(true) ++ { ++ spin_lock_irqsave(&priv->rf_ps_lock,flag); ++ if(priv->RFChangeInProgress) ++ { ++ spin_unlock_irqrestore(&priv->rf_ps_lock,flag); ++ RT_TRACE(COMP_POWER, "MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet); ++ ++ // Set RF after the previous action is done. ++ while(priv->RFChangeInProgress) ++ { ++ RFWaitCounter ++; ++ RT_TRACE(COMP_POWER, "MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter); ++ udelay(1000); // 1 ms ++ ++ // Wait too long, return FALSE to avoid to be stuck here. ++ if(RFWaitCounter > 100) ++ { ++ RT_TRACE(COMP_ERR, "MgntActSet_RF_State(): Wait too logn to set RF\n"); ++ // TODO: Reset RF state? ++ return false; ++ } ++ } ++ } ++ else ++ { ++ priv->RFChangeInProgress = true; ++ spin_unlock_irqrestore(&priv->rf_ps_lock,flag); ++ break; ++ } ++ } ++ ++ rtState = priv->ieee80211->eRFPowerState; ++ ++ switch(StateToSet) ++ { ++ case eRfOn: ++ // ++ // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or ++ // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02. ++ // ++ ++ priv->ieee80211->RfOffReason &= (~ChangeSource); ++ ++ if(! priv->ieee80211->RfOffReason) ++ { ++ priv->ieee80211->RfOffReason = 0; ++ bActionAllowed = true; ++ ++ ++ if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW ) ++ { ++ bConnectBySSID = true; ++ } ++ } ++ else ++ RT_TRACE(COMP_POWER, "MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", priv->ieee80211->RfOffReason, ChangeSource); ++ ++ break; ++ ++ case eRfOff: ++ ++ if (priv->ieee80211->RfOffReason > RF_CHANGE_BY_IPS) ++ { ++ // ++ // 060808, Annie: ++ // Disconnect to current BSS when radio off. Asked by QuanTa. ++ // ++ // Set all link status falg, by Bruce, 2007-06-26. ++ //MgntActSet_802_11_DISASSOCIATE( Adapter, disas_lv_ss ); ++ MgntDisconnect(dev, disas_lv_ss); ++ ++ // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI. ++ // 2007.05.28, by shien chang. ++ ++ } ++ ++ ++ priv->ieee80211->RfOffReason |= ChangeSource; ++ bActionAllowed = true; ++ break; ++ ++ case eRfSleep: ++ priv->ieee80211->RfOffReason |= ChangeSource; ++ bActionAllowed = true; ++ break; ++ ++ default: ++ break; ++ } ++ ++ if(bActionAllowed) ++ { ++ RT_TRACE(COMP_POWER, "MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->ieee80211->RfOffReason); ++ // Config HW to the specified mode. ++ SetRFPowerState(dev, StateToSet); ++ // Turn on RF. ++ if(StateToSet == eRfOn) ++ { ++ //Adapter->HalFunc.HalEnableRxHandler(Adapter); ++ if(bConnectBySSID) ++ { ++ //MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE ); ++ } ++ } ++ // Turn off RF. ++ else if(StateToSet == eRfOff) ++ { ++ //Adapter->HalFunc.HalDisableRxHandler(Adapter); ++ } ++ } ++ else ++ { ++ RT_TRACE(COMP_POWER, "MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->ieee80211->RfOffReason); ++ } ++ ++ // Release RF spinlock ++ spin_lock_irqsave(&priv->rf_ps_lock,flag); ++ priv->RFChangeInProgress = false; ++ spin_unlock_irqrestore(&priv->rf_ps_lock,flag); ++ ++ RT_TRACE(COMP_POWER, "<===MgntActSet_RF_State()\n"); ++ return bActionAllowed; ++} ++ ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r8190_rtl8256.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8190_rtl8256.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8190_rtl8256.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,28 @@ ++/* ++ This is part of the rtl8180-sa2400 driver ++ released under the GPL (See file COPYING for details). ++ Copyright (c) 2005 Andrea Merello ++ ++ This files contains programming code for the rtl8256 ++ radio frontend. ++ ++ *Many* thanks to Realtek Corp. for their great support! ++ ++*/ ++ ++#ifndef RTL8225H ++#define RTL8225H ++ ++#ifdef RTL8190P ++#define RTL819X_TOTAL_RF_PATH 4 ++#else ++#define RTL819X_TOTAL_RF_PATH 2 //for 8192E ++#endif ++extern void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth); ++extern RT_STATUS PHY_RF8256_Config(struct net_device* dev); ++extern RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev); ++extern void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel); ++extern void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel); ++extern bool MgntActSet_RF_State(struct net_device* dev, RT_RF_POWER_STATE StateToSet, RT_RF_CHANGE_SOURCE ChangeSource); ++ ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r8192E_core.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E_core.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E_core.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,6930 @@ ++/****************************************************************************** ++ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. ++ * Linux device driver for RTL8190P / RTL8192E ++ * ++ * Based on the r8180 driver, which is: ++ * Copyright 2004-2005 Andrea Merello , et al. ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * The full GNU General Public License is included in this distribution in the ++ * file called LICENSE. ++ * ++ * Contact Information: ++ * Jerry chuang ++ */ ++ ++ ++#undef LOOP_TEST ++#undef RX_DONT_PASS_UL ++#undef DEBUG_EPROM ++#undef DEBUG_RX_VERBOSE ++#undef DUMMY_RX ++#undef DEBUG_ZERO_RX ++#undef DEBUG_RX_SKB ++#undef DEBUG_TX_FRAG ++#undef DEBUG_RX_FRAG ++#undef DEBUG_TX_FILLDESC ++#undef DEBUG_TX ++#undef DEBUG_IRQ ++#undef DEBUG_RX ++#undef DEBUG_RXALLOC ++#undef DEBUG_REGISTERS ++#undef DEBUG_RING ++#undef DEBUG_IRQ_TASKLET ++#undef DEBUG_TX_ALLOC ++#undef DEBUG_TX_DESC ++ ++//#define CONFIG_RTL8192_IO_MAP ++#include ++#include "r8192E_hw.h" ++#include "r8192E.h" ++#include "r8190_rtl8256.h" /* RTL8225 Radio frontend */ ++#include "r8180_93cx6.h" /* Card EEPROM */ ++#include "r8192E_wx.h" ++#include "r819xE_phy.h" //added by WB 4.30.2008 ++#include "r819xE_phyreg.h" ++#include "r819xE_cmdpkt.h" ++#include "r8192E_dm.h" ++//#include "r8192xU_phyreg.h" ++//#include ++// FIXME: check if 2.6.7 is ok ++ ++#ifdef CONFIG_PM_RTL ++#include "r8192_pm.h" ++#endif ++ ++#ifdef ENABLE_DOT11D ++#include "dot11d.h" ++#endif ++ ++//set here to open your trace code. //WB ++u32 rt_global_debug_component = \ ++ // COMP_INIT | ++ // COMP_EPROM | ++ // COMP_PHY | ++ // COMP_RF | ++ COMP_FIRMWARE | ++ // COMP_TRACE | ++ // COMP_DOWN | ++ // COMP_SWBW | ++ // COMP_SEC | ++// COMP_QOS | ++// COMP_RATE | ++ // COMP_RECV | ++ // COMP_SEND | ++ // COMP_POWER | ++ // COMP_EVENTS | ++ // COMP_RESET | ++ // COMP_CMDPKT | ++ // COMP_POWER_TRACKING | ++ // COMP_INTR | ++ COMP_ERR ; //always open err flags on ++#ifndef PCI_DEVICE ++#define PCI_DEVICE(vend,dev)\ ++ .vendor=(vend),.device=(dev),\ ++ .subvendor=PCI_ANY_ID,.subdevice=PCI_ANY_ID ++#endif ++static struct pci_device_id rtl8192_pci_id_tbl[] __devinitdata = { ++#ifdef RTL8190P ++ /* Realtek */ ++ /* Dlink */ ++ { PCI_DEVICE(0x10ec, 0x8190) }, ++ /* Corega */ ++ { PCI_DEVICE(0x07aa, 0x0045) }, ++ { PCI_DEVICE(0x07aa, 0x0046) }, ++#else ++ /* Realtek */ ++ { PCI_DEVICE(0x10ec, 0x8192) }, ++ ++ /* Corega */ ++ { PCI_DEVICE(0x07aa, 0x0044) }, ++ { PCI_DEVICE(0x07aa, 0x0047) }, ++#endif ++ {} ++}; ++ ++static char* ifname = "wlan%d"; ++#if 0 ++static int hwseqnum = 0; ++static int hwwep = 0; ++#endif ++static int hwwep = 1; //default use hw. set 0 to use software security ++static int channels = 0x3fff; ++ ++MODULE_LICENSE("GPL"); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++MODULE_VERSION("V 1.1"); ++#endif ++MODULE_DEVICE_TABLE(pci, rtl8192_pci_id_tbl); ++//MODULE_AUTHOR("Andrea Merello "); ++MODULE_DESCRIPTION("Linux driver for Realtek RTL819x WiFi cards"); ++ ++#if 0 ++MODULE_PARM(ifname,"s"); ++MODULE_PARM_DESC(devname," Net interface name, wlan%d=default"); ++ ++MODULE_PARM(hwseqnum,"i"); ++MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default"); ++ ++MODULE_PARM(hwwep,"i"); ++MODULE_PARM_DESC(hwwep," Try to use hardware WEP support. Still broken and not available on all cards"); ++ ++MODULE_PARM(channels,"i"); ++MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI"); ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 9) ++module_param(ifname, charp, S_IRUGO|S_IWUSR ); ++//module_param(hwseqnum,int, S_IRUGO|S_IWUSR); ++module_param(hwwep,int, S_IRUGO|S_IWUSR); ++module_param(channels,int, S_IRUGO|S_IWUSR); ++#else ++MODULE_PARM(ifname, "s"); ++//MODULE_PARM(hwseqnum,"i"); ++MODULE_PARM(hwwep,"i"); ++MODULE_PARM(channels,"i"); ++#endif ++ ++MODULE_PARM_DESC(ifname," Net interface name, wlan%d=default"); ++//MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default"); ++MODULE_PARM_DESC(hwwep," Try to use hardware WEP support. Still broken and not available on all cards"); ++MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI"); ++ ++static int __devinit rtl8192_pci_probe(struct pci_dev *pdev, ++ const struct pci_device_id *id); ++static void __devexit rtl8192_pci_disconnect(struct pci_dev *pdev); ++ ++static struct pci_driver rtl8192_pci_driver = { ++ .name = RTL819xE_MODULE_NAME, /* Driver name */ ++ .id_table = rtl8192_pci_id_tbl, /* PCI_ID table */ ++ .probe = rtl8192_pci_probe, /* probe fn */ ++ .remove = __devexit_p(rtl8192_pci_disconnect), /* remove fn */ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0) ++#ifdef CONFIG_PM_RTL ++ .suspend = rtl8192E_suspend, /* PM suspend fn */ ++ .resume = rtl8192E_resume, /* PM resume fn */ ++#else ++ .suspend = NULL, /* PM suspend fn */ ++ .resume = NULL, /* PM resume fn */ ++#endif ++#endif ++}; ++ ++#ifdef ENABLE_DOT11D ++ ++typedef struct _CHANNEL_LIST ++{ ++ u8 Channel[32]; ++ u8 Len; ++}CHANNEL_LIST, *PCHANNEL_LIST; ++ ++static CHANNEL_LIST ChannelPlan[] = { ++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,149,153,157,161,165},24}, //FCC ++ {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Spain. Change to ETSI. ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //France. Change to ETSI. ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, //MKK //MKK ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22},//MKK1 ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Israel. ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, // For 11a , TELEC ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64}, 22}, //MIC ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14} //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626 ++}; ++ ++static void rtl819x_set_channel_map(u8 channel_plan, struct r8192_priv* priv) ++{ ++ int i, max_chan=-1, min_chan=-1; ++ struct ieee80211_device* ieee = priv->ieee80211; ++ switch (channel_plan) ++ { ++ case COUNTRY_CODE_FCC: ++ case COUNTRY_CODE_IC: ++ case COUNTRY_CODE_ETSI: ++ case COUNTRY_CODE_SPAIN: ++ case COUNTRY_CODE_FRANCE: ++ case COUNTRY_CODE_MKK: ++ case COUNTRY_CODE_MKK1: ++ case COUNTRY_CODE_ISRAEL: ++ case COUNTRY_CODE_TELEC: ++ case COUNTRY_CODE_MIC: ++ { ++ Dot11d_Init(ieee); ++ ieee->bGlobalDomain = false; ++ //acturally 8225 & 8256 rf chip only support B,G,24N mode ++ if ((priv->rf_chip == RF_8225) || (priv->rf_chip == RF_8256)) ++ { ++ min_chan = 1; ++ max_chan = 14; ++ } ++ else ++ { ++ RT_TRACE(COMP_ERR, "unknown rf chip, can't set channel map in function:%s()\n", __FUNCTION__); ++ } ++ if (ChannelPlan[channel_plan].Len != 0){ ++ // Clear old channel map ++ memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map)); ++ // Set new channel map ++ for (i=0;i max_chan) ++ break; ++ GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1; ++ } ++ } ++ break; ++ } ++ case COUNTRY_CODE_GLOBAL_DOMAIN: ++ { ++ GET_DOT11D_INFO(ieee)->bEnabled = 0; //this flag enabled to follow 11d country IE setting, otherwise, it shall follow global domain setting ++ Dot11d_Reset(ieee); ++ ieee->bGlobalDomain = true; ++ break; ++ } ++ default: ++ break; ++ } ++} ++#endif ++ ++ ++#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 ) ++/* 2007/07/25 MH Defien temp tx fw info. */ ++static TX_FWINFO_T Tmp_TxFwInfo; ++ ++ ++#define rx_hal_is_cck_rate(_pdrvinfo)\ ++ (_pdrvinfo->RxRate == DESC90_RATE1M ||\ ++ _pdrvinfo->RxRate == DESC90_RATE2M ||\ ++ _pdrvinfo->RxRate == DESC90_RATE5_5M ||\ ++ _pdrvinfo->RxRate == DESC90_RATE11M) &&\ ++ !_pdrvinfo->RxHT\ ++ ++ ++void CamResetAllEntry(struct net_device *dev) ++{ ++ //u8 ucIndex; ++ u32 ulcommand = 0; ++ ++#if 1 ++ ulcommand |= BIT31|BIT30; ++ write_nic_dword(dev, RWCAM, ulcommand); ++#else ++ for(ucIndex=0;ucIndexbase_addr +x); ++} ++ ++u32 read_nic_dword(struct net_device *dev, int x) ++{ ++ return inl(dev->base_addr +x); ++} ++ ++u16 read_nic_word(struct net_device *dev, int x) ++{ ++ return inw(dev->base_addr +x); ++} ++ ++void write_nic_byte(struct net_device *dev, int x,u8 y) ++{ ++ outb(y&0xff,dev->base_addr +x); ++} ++ ++void write_nic_word(struct net_device *dev, int x,u16 y) ++{ ++ outw(y,dev->base_addr +x); ++} ++ ++void write_nic_dword(struct net_device *dev, int x,u32 y) ++{ ++ outl(y,dev->base_addr +x); ++} ++ ++#else /* RTL_IO_MAP */ ++ ++u8 read_nic_byte(struct net_device *dev, int x) ++{ ++ return 0xff&readb((u8*)dev->mem_start +x); ++} ++ ++u32 read_nic_dword(struct net_device *dev, int x) ++{ ++ return readl((u8*)dev->mem_start +x); ++} ++ ++u16 read_nic_word(struct net_device *dev, int x) ++{ ++ return readw((u8*)dev->mem_start +x); ++} ++ ++void write_nic_byte(struct net_device *dev, int x,u8 y) ++{ ++ writeb(y,(u8*)dev->mem_start +x); ++ udelay(20); ++} ++ ++void write_nic_dword(struct net_device *dev, int x,u32 y) ++{ ++ writel(y,(u8*)dev->mem_start +x); ++ udelay(20); ++} ++ ++void write_nic_word(struct net_device *dev, int x,u16 y) ++{ ++ writew(y,(u8*)dev->mem_start +x); ++ udelay(20); ++} ++ ++#endif /* RTL_IO_MAP */ ++ ++ ++/////////////////////////////////////////////////////////// ++ ++//u8 read_phy_cck(struct net_device *dev, u8 adr); ++//u8 read_phy_ofdm(struct net_device *dev, u8 adr); ++/* this might still called in what was the PHY rtl8185/rtl8192 common code ++ * plans are to possibilty turn it again in one common code... ++ */ ++inline void force_pci_posting(struct net_device *dev) ++{ ++} ++ ++ ++//warning message WB ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++void rtl8192_interrupt(int irq, void *netdev, struct pt_regs *regs); ++#else ++irqreturn_t rtl8192_interrupt(int irq, void *netdev, struct pt_regs *regs); ++#endif ++#else ++irqreturn_t rtl8192_interrupt(int irq, void *netdev); ++#endif ++//static struct net_device_stats *rtl8192_stats(struct net_device *dev); ++void rtl8192_commit(struct net_device *dev); ++//void rtl8192_restart(struct net_device *dev); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void rtl8192_restart(struct work_struct *work); ++//void rtl8192_rq_tx_ack(struct work_struct *work); ++#else ++ void rtl8192_restart(struct net_device *dev); ++// //void rtl8192_rq_tx_ack(struct net_device *dev); ++ #endif ++ ++void watch_dog_timer_callback(unsigned long data); ++#ifdef ENABLE_IPS ++void IPSEnter(struct net_device *dev); ++void IPSLeave(struct net_device *dev); ++void InactivePsWorkItemCallback(struct net_device *dev); ++#endif ++/**************************************************************************** ++ -----------------------------PROCFS STUFF------------------------- ++*****************************************************************************/ ++ ++static struct proc_dir_entry *rtl8192_proc = NULL; ++ ++ ++ ++static int proc_get_stats_ap(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ struct ieee80211_device *ieee = priv->ieee80211; ++ struct ieee80211_network *target; ++ ++ int len = 0; ++ ++ list_for_each_entry(target, &ieee->network_list, list) { ++ ++ len += snprintf(page + len, count - len, ++ "%s ", target->ssid); ++ ++ if(target->wpa_ie_len>0 || target->rsn_ie_len>0){ ++ len += snprintf(page + len, count - len, ++ "WPA\n"); ++ } ++ else{ ++ len += snprintf(page + len, count - len, ++ "non_WPA\n"); ++ } ++ ++ } ++ ++ *eof = 1; ++ return len; ++} ++ ++static int proc_get_registers(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ ++ int len = 0; ++ int i,n; ++ ++ int max=0xff; ++ ++ /* This dump the current register page */ ++ len += snprintf(page + len, count - len, ++ "\n####################page 0##################\n "); ++ ++ for(n=0;n<=max;) ++ { ++ //printk( "\nD: %2x> ", n); ++ len += snprintf(page + len, count - len, ++ "\nD: %2x > ",n); ++ ++ for(i=0;i<16 && n<=max;i++,n++) ++ len += snprintf(page + len, count - len, ++ "%2x ",read_nic_byte(dev,n)); ++ ++ // printk("%2x ",read_nic_byte(dev,n)); ++ } ++ len += snprintf(page + len, count - len,"\n"); ++ len += snprintf(page + len, count - len, ++ "\n####################page 1##################\n "); ++ for(n=0;n<=max;) ++ { ++ //printk( "\nD: %2x> ", n); ++ len += snprintf(page + len, count - len, ++ "\nD: %2x > ",n); ++ ++ for(i=0;i<16 && n<=max;i++,n++) ++ len += snprintf(page + len, count - len, ++ "%2x ",read_nic_byte(dev,0x100|n)); ++ ++ // printk("%2x ",read_nic_byte(dev,n)); ++ } ++ ++ len += snprintf(page + len, count - len, ++ "\n####################page 3##################\n "); ++ for(n=0;n<=max;) ++ { ++ //printk( "\nD: %2x> ", n); ++ len += snprintf(page + len, count - len, ++ "\nD: %2x > ",n); ++ ++ for(i=0;i<16 && n<=max;i++,n++) ++ len += snprintf(page + len, count - len, ++ "%2x ",read_nic_byte(dev,0x300|n)); ++ ++ // printk("%2x ",read_nic_byte(dev,n)); ++ } ++ ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++ ++#if 0 ++static int proc_get_cck_reg(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ ++ int len = 0; ++ int i,n; ++ ++ int max = 0x5F; ++ ++ /* This dump the current register page */ ++ for(n=0;n<=max;) ++ { ++ //printk( "\nD: %2x> ", n); ++ len += snprintf(page + len, count - len, ++ "\nD: %2x > ",n); ++ ++ for(i=0;i<16 && n<=max;i++,n++) ++ len += snprintf(page + len, count - len, ++ "%2x ",read_phy_cck(dev,n)); ++ ++ // printk("%2x ",read_nic_byte(dev,n)); ++ } ++ len += snprintf(page + len, count - len,"\n"); ++ ++ ++ *eof = 1; ++ return len; ++} ++ ++#endif ++ ++#if 0 ++static int proc_get_ofdm_reg(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ ++ struct net_device *dev = data; ++// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ ++ int len = 0; ++ int i,n; ++ ++ //int max=0xff; ++ int max = 0x40; ++ ++ /* This dump the current register page */ ++ for(n=0;n<=max;) ++ { ++ //printk( "\nD: %2x> ", n); ++ len += snprintf(page + len, count - len, ++ "\nD: %2x > ",n); ++ ++ for(i=0;i<16 && n<=max;i++,n++) ++ len += snprintf(page + len, count - len, ++ "%2x ",read_phy_ofdm(dev,n)); ++ ++ // printk("%2x ",read_nic_byte(dev,n)); ++ } ++ len += snprintf(page + len, count - len,"\n"); ++ ++ ++ ++ *eof = 1; ++ return len; ++} ++ ++#endif ++ ++#if 0 ++static int proc_get_stats_hw(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, ++ "NIC int: %lu\n" ++ "Total int: %lu\n", ++ priv->stats.ints, ++ priv->stats.shints); ++ ++ *eof = 1; ++ return len; ++} ++#endif ++ ++static int proc_get_stats_tx(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, ++ "TX VI priority ok int: %lu\n" ++// "TX VI priority error int: %lu\n" ++ "TX VO priority ok int: %lu\n" ++// "TX VO priority error int: %lu\n" ++ "TX BE priority ok int: %lu\n" ++// "TX BE priority error int: %lu\n" ++ "TX BK priority ok int: %lu\n" ++// "TX BK priority error int: %lu\n" ++ "TX MANAGE priority ok int: %lu\n" ++// "TX MANAGE priority error int: %lu\n" ++ "TX BEACON priority ok int: %lu\n" ++ "TX BEACON priority error int: %lu\n" ++ "TX CMDPKT priority ok int: %lu\n" ++// "TX high priority ok int: %lu\n" ++// "TX high priority failed error int: %lu\n" ++// "TX queue resume: %lu\n" ++ "TX queue stopped?: %d\n" ++ "TX fifo overflow: %lu\n" ++// "TX beacon: %lu\n" ++// "TX VI queue: %d\n" ++// "TX VO queue: %d\n" ++// "TX BE queue: %d\n" ++// "TX BK queue: %d\n" ++// "TX HW queue: %d\n" ++// "TX VI dropped: %lu\n" ++// "TX VO dropped: %lu\n" ++// "TX BE dropped: %lu\n" ++// "TX BK dropped: %lu\n" ++ "TX total data packets %lu\n" ++ "TX total data bytes :%lu\n", ++// "TX beacon aborted: %lu\n", ++ priv->stats.txviokint, ++// priv->stats.txvierr, ++ priv->stats.txvookint, ++// priv->stats.txvoerr, ++ priv->stats.txbeokint, ++// priv->stats.txbeerr, ++ priv->stats.txbkokint, ++// priv->stats.txbkerr, ++ priv->stats.txmanageokint, ++// priv->stats.txmanageerr, ++ priv->stats.txbeaconokint, ++ priv->stats.txbeaconerr, ++ priv->stats.txcmdpktokint, ++// priv->stats.txhpokint, ++// priv->stats.txhperr, ++// priv->stats.txresumed, ++ netif_queue_stopped(dev), ++ priv->stats.txoverflow, ++// priv->stats.txbeacon, ++// atomic_read(&(priv->tx_pending[VI_QUEUE])), ++// atomic_read(&(priv->tx_pending[VO_QUEUE])), ++// atomic_read(&(priv->tx_pending[BE_QUEUE])), ++// atomic_read(&(priv->tx_pending[BK_QUEUE])), ++// read_nic_byte(dev, TXFIFOCOUNT), ++// priv->stats.txvidrop, ++// priv->stats.txvodrop, ++ priv->ieee80211->stats.tx_packets, ++ priv->ieee80211->stats.tx_bytes ++ ++ ++// priv->stats.txbedrop, ++// priv->stats.txbkdrop ++ // priv->stats.txdatapkt ++// priv->stats.txbeaconerr ++ ); ++ ++ *eof = 1; ++ return len; ++} ++ ++ ++ ++static int proc_get_stats_rx(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, ++ "RX packets: %lu\n" ++ "RX desc err: %lu\n" ++ "RX rx overflow error: %lu\n" ++ "RX invalid urb error: %lu\n", ++ priv->stats.rxint, ++ priv->stats.rxrdu, ++ priv->stats.rxoverflow, ++ priv->stats.rxurberr); ++ ++ *eof = 1; ++ return len; ++} ++ ++static void rtl8192_proc_module_init(void) ++{ ++ RT_TRACE(COMP_INIT, "Initializing proc filesystem"); ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ rtl8192_proc=create_proc_entry(RTL819xE_MODULE_NAME, S_IFDIR, proc_net); ++#else ++ rtl8192_proc=create_proc_entry(RTL819xE_MODULE_NAME, S_IFDIR, init_net.proc_net); ++#endif ++} ++ ++ ++static void rtl8192_proc_module_remove(void) ++{ ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ remove_proc_entry(RTL819xE_MODULE_NAME, proc_net); ++#else ++ remove_proc_entry(RTL819xE_MODULE_NAME, init_net.proc_net); ++#endif ++} ++ ++ ++static void rtl8192_proc_remove_one(struct net_device *dev) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ ++ printk("dev name=======> %s\n",dev->name); ++ ++ if (priv->dir_dev) { ++ // remove_proc_entry("stats-hw", priv->dir_dev); ++ remove_proc_entry("stats-tx", priv->dir_dev); ++ remove_proc_entry("stats-rx", priv->dir_dev); ++ // remove_proc_entry("stats-ieee", priv->dir_dev); ++ remove_proc_entry("stats-ap", priv->dir_dev); ++ remove_proc_entry("registers", priv->dir_dev); ++ // remove_proc_entry("cck-registers",priv->dir_dev); ++ // remove_proc_entry("ofdm-registers",priv->dir_dev); ++ //remove_proc_entry(dev->name, rtl8192_proc); ++ remove_proc_entry("wlan0", rtl8192_proc); ++ priv->dir_dev = NULL; ++ } ++} ++ ++ ++static void rtl8192_proc_init_one(struct net_device *dev) ++{ ++ struct proc_dir_entry *e; ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ priv->dir_dev = create_proc_entry(dev->name, ++ S_IFDIR | S_IRUGO | S_IXUGO, ++ rtl8192_proc); ++ if (!priv->dir_dev) { ++ RT_TRACE(COMP_ERR, "Unable to initialize /proc/net/rtl8192/%s\n", ++ dev->name); ++ return; ++ } ++ #if 0 ++ e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO, ++ priv->dir_dev, proc_get_stats_hw, dev); ++ ++ if (!e) { ++ DMESGE("Unable to initialize " ++ "/proc/net/rtl8192/%s/stats-hw\n", ++ dev->name); ++ } ++ #endif ++ e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO, ++ priv->dir_dev, proc_get_stats_rx, dev); ++ ++ if (!e) { ++ RT_TRACE(COMP_ERR,"Unable to initialize " ++ "/proc/net/rtl8192/%s/stats-rx\n", ++ dev->name); ++ } ++ ++ ++ e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO, ++ priv->dir_dev, proc_get_stats_tx, dev); ++ ++ if (!e) { ++ RT_TRACE(COMP_ERR, "Unable to initialize " ++ "/proc/net/rtl8192/%s/stats-tx\n", ++ dev->name); ++ } ++ #if 0 ++ e = create_proc_read_entry("stats-ieee", S_IFREG | S_IRUGO, ++ priv->dir_dev, proc_get_stats_ieee, dev); ++ ++ if (!e) { ++ DMESGE("Unable to initialize " ++ "/proc/net/rtl8192/%s/stats-ieee\n", ++ dev->name); ++ } ++ ++ #endif ++ ++ e = create_proc_read_entry("stats-ap", S_IFREG | S_IRUGO, ++ priv->dir_dev, proc_get_stats_ap, dev); ++ ++ if (!e) { ++ RT_TRACE(COMP_ERR, "Unable to initialize " ++ "/proc/net/rtl8192/%s/stats-ap\n", ++ dev->name); ++ } ++ ++ e = create_proc_read_entry("registers", S_IFREG | S_IRUGO, ++ priv->dir_dev, proc_get_registers, dev); ++ if (!e) { ++ RT_TRACE(COMP_ERR, "Unable to initialize " ++ "/proc/net/rtl8192/%s/registers\n", ++ dev->name); ++ } ++#if 0 ++ e = create_proc_read_entry("cck-registers", S_IFREG | S_IRUGO, ++ priv->dir_dev, proc_get_cck_reg, dev); ++ if (!e) { ++ RT_TRACE(COMP_ERR, "Unable to initialize " ++ "/proc/net/rtl8192/%s/cck-registers\n", ++ dev->name); ++ } ++ ++ e = create_proc_read_entry("ofdm-registers", S_IFREG | S_IRUGO, ++ priv->dir_dev, proc_get_ofdm_reg, dev); ++ if (!e) { ++ RT_TRACE(COMP_ERR, "Unable to initialize " ++ "/proc/net/rtl8192/%s/ofdm-registers\n", ++ dev->name); ++ } ++#endif ++} ++/**************************************************************************** ++ -----------------------------MISC STUFF------------------------- ++*****************************************************************************/ ++ ++short check_nic_enough_desc(struct net_device *dev, int prio) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ struct rtl8192_tx_ring *ring = &priv->tx_ring[prio]; ++ ++ /* for now we reserve two free descriptor as a safety boundary ++ * between the tail and the head ++ */ ++ if (ring->entries - skb_queue_len(&ring->queue) >= 2) { ++ return 1; ++ } else { ++ return 0; ++ } ++} ++ ++static void tx_timeout(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ //rtl8192_commit(dev); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ schedule_work(&priv->reset_wq); ++#else ++ schedule_task(&priv->reset_wq); ++#endif ++ printk("TXTIMEOUT"); ++} ++ ++ ++/**************************************************************************** ++ ------------------------------HW STUFF--------------------------- ++*****************************************************************************/ ++ ++ ++static void rtl8192_irq_enable(struct net_device *dev) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ priv->irq_enabled = 1; ++ write_nic_dword(dev,INTA_MASK, priv->irq_mask); ++} ++ ++ ++static void rtl8192_irq_disable(struct net_device *dev) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ ++ write_nic_dword(dev,INTA_MASK,0); ++ force_pci_posting(dev); ++ priv->irq_enabled = 0; ++} ++ ++ ++static void rtl8192_set_mode(struct net_device *dev,int mode) ++{ ++ u8 ecmd; ++ ecmd=read_nic_byte(dev, EPROM_CMD); ++ ecmd=ecmd &~ EPROM_CMD_OPERATING_MODE_MASK; ++ ecmd=ecmd | (mode<ieee80211->state == IEEE80211_LINKED){ ++ ++ if (priv->ieee80211->iw_mode == IW_MODE_INFRA) ++ msr |= (MSR_LINK_MANAGED<ieee80211->iw_mode == IW_MODE_ADHOC) ++ msr |= (MSR_LINK_ADHOC<ieee80211->iw_mode == IW_MODE_MASTER) ++ msr |= (MSR_LINK_MASTER<%s()====ch:%d\n", __FUNCTION__, ch); ++ priv->chan=ch; ++#if 0 ++ if(priv->ieee80211->iw_mode == IW_MODE_ADHOC || ++ priv->ieee80211->iw_mode == IW_MODE_MASTER){ ++ ++ priv->ieee80211->link_state = WLAN_LINK_ASSOCIATED; ++ priv->ieee80211->master_chan = ch; ++ rtl8192_update_beacon_ch(dev); ++ } ++#endif ++ ++ /* this hack should avoid frame TX during channel setting*/ ++ ++ ++ // tx = read_nic_dword(dev,TX_CONF); ++ // tx &= ~TX_LOOPBACK_MASK; ++ ++#ifndef LOOP_TEST ++ //TODO ++ // write_nic_dword(dev,TX_CONF, tx |( TX_LOOPBACK_MAC<rf_set_chan) ++ priv->rf_set_chan(dev,priv->chan); ++ // mdelay(10); ++ // write_nic_dword(dev,TX_CONF,tx | (TX_LOOPBACK_NONE<rx_ring_dma); ++} ++ ++/* the TX_DESC_BASE setting is according to the following queue index ++ * BK_QUEUE ===> 0 ++ * BE_QUEUE ===> 1 ++ * VI_QUEUE ===> 2 ++ * VO_QUEUE ===> 3 ++ * HCCA_QUEUE ===> 4 ++ * TXCMD_QUEUE ===> 5 ++ * MGNT_QUEUE ===> 6 ++ * HIGH_QUEUE ===> 7 ++ * BEACON_QUEUE ===> 8 ++ * */ ++static u32 TX_DESC_BASE[] = {BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA}; ++void rtl8192_tx_enable(struct net_device *dev) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ u32 i; ++ for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) ++ write_nic_dword(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma); ++ ++ ieee80211_reset_queue(priv->ieee80211); ++} ++ ++#if 0 ++void rtl8192_beacon_tx_enable(struct net_device *dev) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ u32 reg; ++ ++ reg = read_nic_dword(priv->ieee80211->dev,INTA_MASK); ++ ++ /* enable Beacon realted interrupt signal */ ++ reg |= (IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER); ++ write_nic_byte(dev,reg); ++} ++#endif ++ ++static void rtl8192_free_rx_ring(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ int i; ++ ++ for (i = 0; i < priv->rxringcount; i++) { ++ struct sk_buff *skb = priv->rx_buf[i]; ++ if (!skb) ++ continue; ++ ++ pci_unmap_single(priv->pdev, ++ *((dma_addr_t *)skb->cb), ++ priv->rxbuffersize, PCI_DMA_FROMDEVICE); ++ kfree_skb(skb); ++ } ++ ++ pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * priv->rxringcount, ++ priv->rx_ring, priv->rx_ring_dma); ++ priv->rx_ring = NULL; ++} ++ ++static void rtl8192_free_tx_ring(struct net_device *dev, unsigned int prio) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ struct rtl8192_tx_ring *ring = &priv->tx_ring[prio]; ++ ++ while (skb_queue_len(&ring->queue)) { ++ tx_desc_819x_pci *entry = &ring->desc[ring->idx]; ++ struct sk_buff *skb = __skb_dequeue(&ring->queue); ++ ++ pci_unmap_single(priv->pdev, le32_to_cpu(entry->TxBuffAddr), ++ skb->len, PCI_DMA_TODEVICE); ++ kfree_skb(skb); ++ ring->idx = (ring->idx + 1) % ring->entries; ++ } ++ ++ pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries, ++ ring->desc, ring->dma); ++ ring->desc = NULL; ++} ++ ++ ++static void rtl8192_beacon_disable(struct net_device *dev) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ u32 reg; ++ ++ reg = read_nic_dword(priv->ieee80211->dev,INTA_MASK); ++ ++ /* disable Beacon realted interrupt signal */ ++ reg &= ~(IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER); ++ write_nic_dword(priv->ieee80211->dev, INTA_MASK, reg); ++} ++ ++void rtl8192_rtx_disable(struct net_device *dev) ++{ ++ u8 cmd; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ int i; ++ ++ cmd=read_nic_byte(dev,CMDR); ++// if(!priv->ieee80211->bSupportRemoteWakeUp) { ++ write_nic_byte(dev, CMDR, cmd &~ \ ++ (CR_TE|CR_RE)); ++// } ++ force_pci_posting(dev); ++ mdelay(30); ++ ++ for(i = 0; i < MAX_QUEUE_SIZE; i++) { ++ skb_queue_purge(&priv->ieee80211->skb_waitQ [i]); ++ } ++ for(i = 0; i < MAX_QUEUE_SIZE; i++) { ++ skb_queue_purge(&priv->ieee80211->skb_aggQ [i]); ++ } ++ ++ ++ skb_queue_purge(&priv->skb_queue); ++ return; ++} ++ ++static void rtl8192_reset(struct net_device *dev) ++{ ++ rtl8192_irq_disable(dev); ++ printk("This is RTL819xP Reset procedure\n"); ++} ++ ++static u16 rtl_rate[] = {10,20,55,110,60,90,120,180,240,360,480,540}; ++inline u16 rtl8192_rate2rate(short rate) ++{ ++ if (rate >11) return 0; ++ return rtl_rate[rate]; ++} ++ ++ ++ ++#if 0 ++void rtl8192_tx_queues_stop(struct net_device *dev) ++{ ++ //struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ u8 dma_poll_mask = (1<dma_poll_mask |= (1<dma_poll_mask); ++ rtl8192_set_mode(dev,EPROM_CMD_NORMAL); ++ #endif ++} ++ ++ ++static void rtl8192_data_hard_resume(struct net_device *dev) ++{ ++ // FIXME !! ++ #if 0 ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ priv->dma_poll_mask &= ~(1<dma_poll_mask); ++ rtl8192_set_mode(dev,EPROM_CMD_NORMAL); ++ #endif ++} ++ ++/* this function TX data frames when the ieee80211 stack requires this. ++ * It checks also if we need to stop the ieee tx queue, eventually do it ++ */ ++static void rtl8192_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, int rate) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ int ret; ++ //unsigned long flags; ++ cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); ++ u8 queue_index = tcb_desc->queue_index; ++ /* shall not be referred by command packet */ ++ assert(queue_index != TXCMD_QUEUE); ++ ++ //spin_lock_irqsave(&priv->tx_lock,flags); ++ ++ memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); ++#if 0 ++ tcb_desc->RATRIndex = 7; ++ tcb_desc->bTxDisableRateFallBack = 1; ++ tcb_desc->bTxUseDriverAssingedRate = 1; ++ tcb_desc->bTxEnableFwCalcDur = 1; ++#endif ++ skb_push(skb, priv->ieee80211->tx_headroom); ++ ret = rtl8192_tx(dev, skb); ++ if(ret != 0) { ++ kfree_skb(skb); ++ }; ++ ++// ++ if(queue_index!=MGNT_QUEUE) { ++ priv->ieee80211->stats.tx_bytes+=(skb->len - priv->ieee80211->tx_headroom); ++ priv->ieee80211->stats.tx_packets++; ++ } ++ ++ //spin_unlock_irqrestore(&priv->tx_lock,flags); ++ ++// return ret; ++ return; ++} ++ ++/* This is a rough attempt to TX a frame ++ * This is called by the ieee 80211 stack to TX management frames. ++ * If the ring is full packet are dropped (for data frame the queue ++ * is stopped before this can happen). ++ */ ++static int rtl8192_hard_start_xmit(struct sk_buff *skb,struct net_device *dev) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ ++ ++ int ret; ++ //unsigned long flags; ++ cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); ++ u8 queue_index = tcb_desc->queue_index; ++ ++ ++ //spin_lock_irqsave(&priv->tx_lock,flags); ++ ++ memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); ++ if(queue_index == TXCMD_QUEUE) { ++ // skb_push(skb, USB_HWDESC_HEADER_LEN); ++ rtl819xE_tx_cmd(dev, skb); ++ ret = 0; ++ //spin_unlock_irqrestore(&priv->tx_lock,flags); ++ return ret; ++ } else { ++ // RT_TRACE(COMP_SEND, "To send management packet\n"); ++ tcb_desc->RATRIndex = 7; ++ tcb_desc->bTxDisableRateFallBack = 1; ++ tcb_desc->bTxUseDriverAssingedRate = 1; ++ tcb_desc->bTxEnableFwCalcDur = 1; ++ skb_push(skb, priv->ieee80211->tx_headroom); ++ ret = rtl8192_tx(dev, skb); ++ if(ret != 0) { ++ kfree_skb(skb); ++ }; ++ } ++ ++// priv->ieee80211->stats.tx_bytes+=skb->len; ++// priv->ieee80211->stats.tx_packets++; ++ ++ //spin_unlock_irqrestore(&priv->tx_lock,flags); ++ ++ return ret; ++ ++} ++ ++ ++void rtl8192_try_wake_queue(struct net_device *dev, int pri); ++ ++static void rtl8192_tx_isr(struct net_device *dev, int prio) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ ++ struct rtl8192_tx_ring *ring = &priv->tx_ring[prio]; ++ ++ while (skb_queue_len(&ring->queue)) { ++ tx_desc_819x_pci *entry = &ring->desc[ring->idx]; ++ struct sk_buff *skb; ++ ++ /* beacon packet will only use the first descriptor defautly, ++ * and the OWN may not be cleared by the hardware ++ * */ ++ if(prio != BEACON_QUEUE) { ++ if(entry->OWN) ++ return; ++ ring->idx = (ring->idx + 1) % ring->entries; ++ } ++ ++ skb = __skb_dequeue(&ring->queue); ++ pci_unmap_single(priv->pdev, le32_to_cpu(entry->TxBuffAddr), ++ skb->len, PCI_DMA_TODEVICE); ++ ++ kfree_skb(skb); ++ } ++ if (prio == MGNT_QUEUE){ ++ if (priv->ieee80211->ack_tx_to_ieee){ ++ if (rtl8192_is_tx_queue_empty(dev)){ ++ priv->ieee80211->ack_tx_to_ieee = 0; ++ ieee80211_ps_tx_ack(priv->ieee80211, 1); ++ } ++ } ++ } ++ ++ if(prio != BEACON_QUEUE) { ++ /* try to deal with the pending packets */ ++ tasklet_schedule(&priv->irq_tx_tasklet); ++ } ++ ++} ++ ++static void rtl8192_stop_beacon(struct net_device *dev) ++{ ++ //rtl8192_beacon_disable(dev); ++} ++ ++static void rtl8192_config_rate(struct net_device* dev, u16* rate_config) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ struct ieee80211_network *net; ++ u8 i=0, basic_rate = 0; ++ net = & priv->ieee80211->current_network; ++ ++ for (i=0; irates_len; i++) ++ { ++ basic_rate = net->rates[i]&0x7f; ++ switch(basic_rate) ++ { ++ case MGN_1M: *rate_config |= RRSR_1M; break; ++ case MGN_2M: *rate_config |= RRSR_2M; break; ++ case MGN_5_5M: *rate_config |= RRSR_5_5M; break; ++ case MGN_11M: *rate_config |= RRSR_11M; break; ++ case MGN_6M: *rate_config |= RRSR_6M; break; ++ case MGN_9M: *rate_config |= RRSR_9M; break; ++ case MGN_12M: *rate_config |= RRSR_12M; break; ++ case MGN_18M: *rate_config |= RRSR_18M; break; ++ case MGN_24M: *rate_config |= RRSR_24M; break; ++ case MGN_36M: *rate_config |= RRSR_36M; break; ++ case MGN_48M: *rate_config |= RRSR_48M; break; ++ case MGN_54M: *rate_config |= RRSR_54M; break; ++ } ++ } ++ for (i=0; irates_ex_len; i++) ++ { ++ basic_rate = net->rates_ex[i]&0x7f; ++ switch(basic_rate) ++ { ++ case MGN_1M: *rate_config |= RRSR_1M; break; ++ case MGN_2M: *rate_config |= RRSR_2M; break; ++ case MGN_5_5M: *rate_config |= RRSR_5_5M; break; ++ case MGN_11M: *rate_config |= RRSR_11M; break; ++ case MGN_6M: *rate_config |= RRSR_6M; break; ++ case MGN_9M: *rate_config |= RRSR_9M; break; ++ case MGN_12M: *rate_config |= RRSR_12M; break; ++ case MGN_18M: *rate_config |= RRSR_18M; break; ++ case MGN_24M: *rate_config |= RRSR_24M; break; ++ case MGN_36M: *rate_config |= RRSR_36M; break; ++ case MGN_48M: *rate_config |= RRSR_48M; break; ++ case MGN_54M: *rate_config |= RRSR_54M; break; ++ } ++ } ++} ++ ++ ++#define SHORT_SLOT_TIME 9 ++#define NON_SHORT_SLOT_TIME 20 ++ ++static void rtl8192_update_cap(struct net_device* dev, u16 cap) ++{ ++ u32 tmp = 0; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ struct ieee80211_network *net = &priv->ieee80211->current_network; ++ priv->short_preamble = cap & WLAN_CAPABILITY_SHORT_PREAMBLE; ++ tmp = priv->basic_rate; ++ if (priv->short_preamble) ++ tmp |= BRSR_AckShortPmb; ++ write_nic_dword(dev, RRSR, tmp); ++ ++ if (net->mode & (IEEE_G|IEEE_N_24G)) ++ { ++ u8 slot_time = 0; ++ if ((cap & WLAN_CAPABILITY_SHORT_SLOT)&&(!priv->ieee80211->pHTInfo->bCurrentRT2RTLongSlotTime)) ++ {//short slot time ++ slot_time = SHORT_SLOT_TIME; ++ } ++ else //long slot time ++ slot_time = NON_SHORT_SLOT_TIME; ++ priv->slot_time = slot_time; ++ write_nic_byte(dev, SLOT_TIME, slot_time); ++ } ++ ++} ++ ++static void rtl8192_net_update(struct net_device *dev) ++{ ++ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ struct ieee80211_network *net; ++ u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf; ++ u16 rate_config = 0; ++ net = &priv->ieee80211->current_network; ++ //update Basic rate: RR, BRSR ++ rtl8192_config_rate(dev, &rate_config); ++ // 2007.01.16, by Emily ++ // Select RRSR (in Legacy-OFDM and CCK) ++ // For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. ++ // We do not use other rates. ++ priv->basic_rate = rate_config &= 0x15f; ++ //BSSID ++ write_nic_dword(dev,BSSIDR,((u32*)net->bssid)[0]); ++ write_nic_word(dev,BSSIDR+4,((u16*)net->bssid)[2]); ++#if 0 ++ //MSR ++ rtl8192_update_msr(dev); ++#endif ++ ++ ++// rtl8192_update_cap(dev, net->capability); ++ if (priv->ieee80211->iw_mode == IW_MODE_ADHOC) ++ { ++ write_nic_word(dev, ATIMWND, 2); ++ write_nic_word(dev, BCN_DMATIME, 256); ++ write_nic_word(dev, BCN_INTERVAL, net->beacon_interval); ++ // write_nic_word(dev, BcnIntTime, 100); ++ //BIT15 of BCN_DRV_EARLY_INT will indicate whether software beacon or hw beacon is applied. ++ write_nic_word(dev, BCN_DRV_EARLY_INT, 10); ++ write_nic_byte(dev, BCN_ERR_THRESH, 100); ++ ++ BcnTimeCfg |= (BcnCW<tx_ring[TXCMD_QUEUE]; ++ mapping = pci_map_single(priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE); ++ ++ spin_lock_irqsave(&priv->irq_th_lock,flags); ++ idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries; ++ entry = &ring->desc[idx]; ++ ++ tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); ++ memset(entry,0,12); ++ entry->LINIP = tcb_desc->bLastIniPkt; ++ entry->FirstSeg = 1;//first segment ++ entry->LastSeg = 1; //last segment ++ if(tcb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) { ++ entry->CmdInit = DESC_PACKET_TYPE_INIT; ++ } else { ++ entry->CmdInit = DESC_PACKET_TYPE_NORMAL; ++ entry->Offset = sizeof(TX_FWINFO_8190PCI) + 8; ++ entry->PktSize = (u16)(tcb_desc->pkt_size + entry->Offset); ++ entry->QueueSelect = QSLT_CMD; ++ entry->TxFWInfoSize = 0x08; ++ entry->RATid = (u8)DESC_PACKET_TYPE_INIT; ++ } ++ entry->TxBufferSize = skb->len; ++ entry->TxBuffAddr = cpu_to_le32(mapping); ++ entry->OWN = 1; ++ ++#ifdef JOHN_DUMP_TXDESC ++ { int i; ++ tx_desc_819x_pci *entry1 = &ring->desc[0]; ++ unsigned int *ptr= (unsigned int *)entry1; ++ printk(":\n"); ++ for (i = 0; i < 8; i++) ++ printk("%8x ", ptr[i]); ++ printk("\n"); ++ } ++#endif ++ __skb_queue_tail(&ring->queue, skb); ++ spin_unlock_irqrestore(&priv->irq_th_lock,flags); ++ ++ write_nic_byte(dev, TPPoll, TPPoll_CQ); ++ ++ return; ++} ++ ++/* ++ * Mapping Software/Hardware descriptor queue id to "Queue Select Field" ++ * in TxFwInfo data structure ++ * 2006.10.30 by Emily ++ * ++ * \param QUEUEID Software Queue ++*/ ++static u8 MapHwQueueToFirmwareQueue(u8 QueueID) ++{ ++ u8 QueueSelect = 0x0; //defualt set to ++ ++ switch(QueueID) { ++ case BE_QUEUE: ++ QueueSelect = QSLT_BE; //or QSelect = pTcb->priority; ++ break; ++ ++ case BK_QUEUE: ++ QueueSelect = QSLT_BK; //or QSelect = pTcb->priority; ++ break; ++ ++ case VO_QUEUE: ++ QueueSelect = QSLT_VO; //or QSelect = pTcb->priority; ++ break; ++ ++ case VI_QUEUE: ++ QueueSelect = QSLT_VI; //or QSelect = pTcb->priority; ++ break; ++ case MGNT_QUEUE: ++ QueueSelect = QSLT_MGNT; ++ break; ++ ++ case BEACON_QUEUE: ++ QueueSelect = QSLT_BEACON; ++ break; ++ ++ // TODO: 2006.10.30 mark other queue selection until we verify it is OK ++ // TODO: Remove Assertions ++//#if (RTL819X_FPGA_VER & RTL819X_FPGA_GUANGAN_070502) ++ case TXCMD_QUEUE: ++ QueueSelect = QSLT_CMD; ++ break; ++//#endif ++ case HIGH_QUEUE: ++ //QueueSelect = QSLT_HIGH; ++ //break; ++ ++ default: ++ RT_TRACE(COMP_ERR, "TransmitTCB(): Impossible Queue Selection: %d \n", QueueID); ++ break; ++ } ++ return QueueSelect; ++} ++ ++static u8 MRateToHwRate8190Pci(u8 rate) ++{ ++ u8 ret = DESC90_RATE1M; ++ ++ switch(rate) { ++ case MGN_1M: ret = DESC90_RATE1M; break; ++ case MGN_2M: ret = DESC90_RATE2M; break; ++ case MGN_5_5M: ret = DESC90_RATE5_5M; break; ++ case MGN_11M: ret = DESC90_RATE11M; break; ++ case MGN_6M: ret = DESC90_RATE6M; break; ++ case MGN_9M: ret = DESC90_RATE9M; break; ++ case MGN_12M: ret = DESC90_RATE12M; break; ++ case MGN_18M: ret = DESC90_RATE18M; break; ++ case MGN_24M: ret = DESC90_RATE24M; break; ++ case MGN_36M: ret = DESC90_RATE36M; break; ++ case MGN_48M: ret = DESC90_RATE48M; break; ++ case MGN_54M: ret = DESC90_RATE54M; break; ++ ++ // HT rate since here ++ case MGN_MCS0: ret = DESC90_RATEMCS0; break; ++ case MGN_MCS1: ret = DESC90_RATEMCS1; break; ++ case MGN_MCS2: ret = DESC90_RATEMCS2; break; ++ case MGN_MCS3: ret = DESC90_RATEMCS3; break; ++ case MGN_MCS4: ret = DESC90_RATEMCS4; break; ++ case MGN_MCS5: ret = DESC90_RATEMCS5; break; ++ case MGN_MCS6: ret = DESC90_RATEMCS6; break; ++ case MGN_MCS7: ret = DESC90_RATEMCS7; break; ++ case MGN_MCS8: ret = DESC90_RATEMCS8; break; ++ case MGN_MCS9: ret = DESC90_RATEMCS9; break; ++ case MGN_MCS10: ret = DESC90_RATEMCS10; break; ++ case MGN_MCS11: ret = DESC90_RATEMCS11; break; ++ case MGN_MCS12: ret = DESC90_RATEMCS12; break; ++ case MGN_MCS13: ret = DESC90_RATEMCS13; break; ++ case MGN_MCS14: ret = DESC90_RATEMCS14; break; ++ case MGN_MCS15: ret = DESC90_RATEMCS15; break; ++ case (0x80|0x20): ret = DESC90_RATEMCS32; break; ++ ++ default: break; ++ } ++ return ret; ++} ++ ++ ++static u8 QueryIsShort(u8 TxHT, u8 TxRate, cb_desc *tcb_desc) ++{ ++ u8 tmp_Short; ++ ++ tmp_Short = (TxHT==1)?((tcb_desc->bUseShortGI)?1:0):((tcb_desc->bUseShortPreamble)?1:0); ++ ++ if(TxHT==1 && TxRate != DESC90_RATEMCS15) ++ tmp_Short = 0; ++ ++ return tmp_Short; ++} ++ ++/* ++ * The tx procedure is just as following, ++ * skb->cb will contain all the following information, ++ * priority, morefrag, rate, &dev. ++ * */ ++short rtl8192_tx(struct net_device *dev, struct sk_buff* skb) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ struct rtl8192_tx_ring *ring; ++ unsigned long flags; ++ cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); ++ tx_desc_819x_pci *pdesc = NULL; ++ TX_FWINFO_8190PCI *pTxFwInfo = NULL; ++ dma_addr_t mapping; ++ bool multi_addr=false,broad_addr=false,uni_addr=false; ++ u8* pda_addr = NULL; ++ int idx; ++ ++ mapping = pci_map_single(priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE); ++ /* collect the tx packets statitcs */ ++ pda_addr = ((u8*)skb->data) + sizeof(TX_FWINFO_8190PCI); ++ if(is_multicast_ether_addr(pda_addr)) ++ multi_addr = true; ++ else if(is_broadcast_ether_addr(pda_addr)) ++ broad_addr = true; ++ else ++ uni_addr = true; ++ ++ if(uni_addr) ++ priv->stats.txbytesunicast += (u8)(skb->len) - sizeof(TX_FWINFO_8190PCI); ++ else if(multi_addr) ++ priv->stats.txbytesmulticast +=(u8)(skb->len) - sizeof(TX_FWINFO_8190PCI); ++ else ++ priv->stats.txbytesbroadcast += (u8)(skb->len) - sizeof(TX_FWINFO_8190PCI); ++ ++ /* fill tx firmware */ ++ pTxFwInfo = (PTX_FWINFO_8190PCI)skb->data; ++ memset(pTxFwInfo,0,sizeof(TX_FWINFO_8190PCI)); ++ pTxFwInfo->TxHT = (tcb_desc->data_rate&0x80)?1:0; ++ pTxFwInfo->TxRate = MRateToHwRate8190Pci((u8)tcb_desc->data_rate); ++ pTxFwInfo->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur; ++ pTxFwInfo->Short = QueryIsShort(pTxFwInfo->TxHT, pTxFwInfo->TxRate, tcb_desc); ++ ++ /* Aggregation related */ ++ if(tcb_desc->bAMPDUEnable) { ++ pTxFwInfo->AllowAggregation = 1; ++ pTxFwInfo->RxMF = tcb_desc->ampdu_factor; ++ pTxFwInfo->RxAMD = tcb_desc->ampdu_density; ++ } else { ++ pTxFwInfo->AllowAggregation = 0; ++ pTxFwInfo->RxMF = 0; ++ pTxFwInfo->RxAMD = 0; ++ } ++ ++ // ++ // Protection mode related ++ // ++ pTxFwInfo->RtsEnable = (tcb_desc->bRTSEnable)?1:0; ++ pTxFwInfo->CtsEnable = (tcb_desc->bCTSEnable)?1:0; ++ pTxFwInfo->RtsSTBC = (tcb_desc->bRTSSTBC)?1:0; ++ pTxFwInfo->RtsHT= (tcb_desc->rts_rate&0x80)?1:0; ++ pTxFwInfo->RtsRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate); ++ pTxFwInfo->RtsBandwidth = 0; ++ pTxFwInfo->RtsSubcarrier = tcb_desc->RTSSC; ++ pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):(tcb_desc->bRTSUseShortGI?1:0); ++ // ++ // Set Bandwidth and sub-channel settings. ++ // ++ if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) ++ { ++ if(tcb_desc->bPacketBW) ++ { ++ pTxFwInfo->TxBandwidth = 1; ++#ifdef RTL8190P ++ pTxFwInfo->TxSubCarrier = 3; ++#else ++ pTxFwInfo->TxSubCarrier = 0; //By SD3's Jerry suggestion, use duplicated mode, cosa 04012008 ++#endif ++ } ++ else ++ { ++ pTxFwInfo->TxBandwidth = 0; ++ pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC; ++ } ++ } else { ++ pTxFwInfo->TxBandwidth = 0; ++ pTxFwInfo->TxSubCarrier = 0; ++ } ++ ++ if (0) ++ { ++ /* 2007/07/25 MH Copy current TX FW info.*/ ++ memcpy((void*)(&Tmp_TxFwInfo), (void*)(pTxFwInfo), sizeof(TX_FWINFO_8190PCI)); ++ printk("&&&&&&&&&&&&&&&&&&&&&&====>print out fwinf\n"); ++ printk("===>enable fwcacl:%d\n", Tmp_TxFwInfo.EnableCPUDur); ++ printk("===>RTS STBC:%d\n", Tmp_TxFwInfo.RtsSTBC); ++ printk("===>RTS Subcarrier:%d\n", Tmp_TxFwInfo.RtsSubcarrier); ++ printk("===>Allow Aggregation:%d\n", Tmp_TxFwInfo.AllowAggregation); ++ printk("===>TX HT bit:%d\n", Tmp_TxFwInfo.TxHT); ++ printk("===>Tx rate:%d\n", Tmp_TxFwInfo.TxRate); ++ printk("===>Received AMPDU Density:%d\n", Tmp_TxFwInfo.RxAMD); ++ printk("===>Received MPDU Factor:%d\n", Tmp_TxFwInfo.RxMF); ++ printk("===>TxBandwidth:%d\n", Tmp_TxFwInfo.TxBandwidth); ++ printk("===>TxSubCarrier:%d\n", Tmp_TxFwInfo.TxSubCarrier); ++ ++ printk("<=====**********************out of print\n"); ++ ++ } ++ spin_lock_irqsave(&priv->irq_th_lock,flags); ++ ring = &priv->tx_ring[tcb_desc->queue_index]; ++ if (tcb_desc->queue_index != BEACON_QUEUE) { ++ idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries; ++ } else { ++ idx = 0; ++ } ++ ++ pdesc = &ring->desc[idx]; ++ if((pdesc->OWN == 1) && (tcb_desc->queue_index != BEACON_QUEUE)) { ++ RT_TRACE(COMP_ERR,"No more TX desc@%d, ring->idx = %d,idx = %d,%x", \ ++ tcb_desc->queue_index,ring->idx, idx,skb->len); ++ return skb->len; ++ } ++ ++ /* fill tx descriptor */ ++ memset((u8*)pdesc,0,12); ++ /*DWORD 0*/ ++ pdesc->LINIP = 0; ++ pdesc->CmdInit = 1; ++ pdesc->Offset = sizeof(TX_FWINFO_8190PCI) + 8; //We must add 8!! Emily ++ pdesc->PktSize = (u16)skb->len-sizeof(TX_FWINFO_8190PCI); ++ ++ /*DWORD 1*/ ++ pdesc->SecCAMID= 0; ++ pdesc->RATid = tcb_desc->RATRIndex; ++ ++ ++ pdesc->NoEnc = 1; ++ pdesc->SecType = 0x0; ++ if (tcb_desc->bHwSec) { ++ static u8 tmp =0; ++ if (!tmp) { ++ printk("==>================hw sec\n"); ++ tmp = 1; ++ } ++ switch (priv->ieee80211->pairwise_key_type) { ++ case KEY_TYPE_WEP40: ++ case KEY_TYPE_WEP104: ++ pdesc->SecType = 0x1; ++ pdesc->NoEnc = 0; ++ break; ++ case KEY_TYPE_TKIP: ++ pdesc->SecType = 0x2; ++ pdesc->NoEnc = 0; ++ break; ++ case KEY_TYPE_CCMP: ++ pdesc->SecType = 0x3; ++ pdesc->NoEnc = 0; ++ break; ++ case KEY_TYPE_NA: ++ pdesc->SecType = 0x0; ++ pdesc->NoEnc = 1; ++ break; ++ } ++ } ++ ++ // ++ // Set Packet ID ++ // ++ pdesc->PktId = 0x0; ++ ++ pdesc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index); ++ pdesc->TxFWInfoSize = sizeof(TX_FWINFO_8190PCI); ++ ++ pdesc->DISFB = tcb_desc->bTxDisableRateFallBack; ++ pdesc->USERATE = tcb_desc->bTxUseDriverAssingedRate; ++ ++ pdesc->FirstSeg =1; ++ pdesc->LastSeg = 1; ++ pdesc->TxBufferSize = skb->len; ++ ++ pdesc->TxBuffAddr = cpu_to_le32(mapping); ++ __skb_queue_tail(&ring->queue, skb); ++ pdesc->OWN = 1; ++ spin_unlock_irqrestore(&priv->irq_th_lock,flags); ++ dev->trans_start = jiffies; ++ write_nic_word(dev,TPPoll,0x01<queue_index); ++ return 0; ++} ++ ++static short rtl8192_alloc_rx_desc_ring(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ rx_desc_819x_pci *entry = NULL; ++ int i; ++ ++ priv->rx_ring = pci_alloc_consistent(priv->pdev, ++ sizeof(*priv->rx_ring) * priv->rxringcount, &priv->rx_ring_dma); ++ ++ if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) { ++ RT_TRACE(COMP_ERR,"Cannot allocate RX ring\n"); ++ return -ENOMEM; ++ } ++ ++ memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * priv->rxringcount); ++ priv->rx_idx = 0; ++ ++ for (i = 0; i < priv->rxringcount; i++) { ++ struct sk_buff *skb = dev_alloc_skb(priv->rxbuffersize); ++ dma_addr_t *mapping; ++ entry = &priv->rx_ring[i]; ++ if (!skb) ++ return 0; ++ priv->rx_buf[i] = skb; ++ mapping = (dma_addr_t *)skb->cb; ++ *mapping = pci_map_single(priv->pdev, skb->tail,//skb_tail_pointer(skb), ++ priv->rxbuffersize, PCI_DMA_FROMDEVICE); ++ ++ entry->BufferAddress = cpu_to_le32(*mapping); ++ ++ entry->Length = priv->rxbuffersize; ++ entry->OWN = 1; ++ } ++ ++ entry->EOR = 1; ++ return 0; ++} ++ ++static int rtl8192_alloc_tx_desc_ring(struct net_device *dev, ++ unsigned int prio, unsigned int entries) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ tx_desc_819x_pci *ring; ++ dma_addr_t dma; ++ int i; ++ ++ ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma); ++ if (!ring || (unsigned long)ring & 0xFF) { ++ RT_TRACE(COMP_ERR, "Cannot allocate TX ring (prio = %d)\n", prio); ++ return -ENOMEM; ++ } ++ ++ memset(ring, 0, sizeof(*ring)*entries); ++ priv->tx_ring[prio].desc = ring; ++ priv->tx_ring[prio].dma = dma; ++ priv->tx_ring[prio].idx = 0; ++ priv->tx_ring[prio].entries = entries; ++ skb_queue_head_init(&priv->tx_ring[prio].queue); ++ ++ for (i = 0; i < entries; i++) ++ ring[i].NextDescAddress = ++ cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring)); ++ ++ return 0; ++} ++ ++ ++static short rtl8192_pci_initdescring(struct net_device *dev) ++{ ++ u32 ret; ++ int i; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ ret = rtl8192_alloc_rx_desc_ring(dev); ++ if (ret) { ++ return ret; ++ } ++ ++ ++ /* general process for other queue */ ++ for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) { ++ if ((ret = rtl8192_alloc_tx_desc_ring(dev, i, priv->txringcount))) ++ goto err_free_rings; ++ } ++ ++#if 0 ++ /* specific process for hardware beacon process */ ++ if ((ret = rtl8192_alloc_tx_desc_ring(dev, MAX_TX_QUEUE_COUNT - 1, 2))) ++ goto err_free_rings; ++#endif ++ ++ return 0; ++ ++err_free_rings: ++ rtl8192_free_rx_ring(dev); ++ for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) ++ if (priv->tx_ring[i].desc) ++ rtl8192_free_tx_ring(dev, i); ++ return 1; ++} ++ ++static void rtl8192_pci_resetdescring(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ int i; ++ ++ /* force the rx_idx to the first one */ ++ if(priv->rx_ring) { ++ rx_desc_819x_pci *entry = NULL; ++ for (i = 0; i < priv->rxringcount; i++) { ++ entry = &priv->rx_ring[i]; ++ entry->OWN = 1; ++ } ++ priv->rx_idx = 0; ++ } ++ ++ /* after reset, release previous pending packet, and force the ++ * tx idx to the first one */ ++ for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) { ++ if (priv->tx_ring[i].desc) { ++ struct rtl8192_tx_ring *ring = &priv->tx_ring[i]; ++ ++ while (skb_queue_len(&ring->queue)) { ++ tx_desc_819x_pci *entry = &ring->desc[ring->idx]; ++ struct sk_buff *skb = __skb_dequeue(&ring->queue); ++ ++ pci_unmap_single(priv->pdev, le32_to_cpu(entry->TxBuffAddr), ++ skb->len, PCI_DMA_TODEVICE); ++ kfree_skb(skb); ++ ring->idx = (ring->idx + 1) % ring->entries; ++ } ++ ring->idx = 0; ++ } ++ } ++} ++ ++#if 1 ++extern void rtl8192_update_ratr_table(struct net_device* dev); ++static void rtl8192_link_change(struct net_device *dev) ++{ ++// int i; ++ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ struct ieee80211_device* ieee = priv->ieee80211; ++ //write_nic_word(dev, BCN_INTR_ITV, net->beacon_interval); ++ if (ieee->state == IEEE80211_LINKED) ++ { ++ rtl8192_net_update(dev); ++ rtl8192_update_ratr_table(dev); ++#if 1 ++ //add this as in pure N mode, wep encryption will use software way, but there is no chance to set this as wep will not set group key in wext. WB.2008.07.08 ++ if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) ++ EnableHWSecurityConfig8192(dev); ++#endif ++ } ++ else ++ { ++ write_nic_byte(dev, 0x173, 0); ++ } ++ /*update timing params*/ ++ //rtl8192_set_chan(dev, priv->chan); ++ //MSR ++ rtl8192_update_msr(dev); ++ ++ // 2007/10/16 MH MAC Will update TSF according to all received beacon, so we have ++ // // To set CBSSID bit when link with any AP or STA. ++ if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) ++ { ++ u32 reg = 0; ++ reg = read_nic_dword(dev, RCR); ++ if (priv->ieee80211->state == IEEE80211_LINKED) ++ priv->ReceiveConfig = reg |= RCR_CBSSID; ++ else ++ priv->ReceiveConfig = reg &= ~RCR_CBSSID; ++ write_nic_dword(dev, RCR, reg); ++ } ++} ++#endif ++ ++ ++static struct ieee80211_qos_parameters def_qos_parameters = { ++ {3,3,3,3},/* cw_min */ ++ {7,7,7,7},/* cw_max */ ++ {2,2,2,2},/* aifs */ ++ {0,0,0,0},/* flags */ ++ {0,0,0,0} /* tx_op_limit */ ++}; ++ ++#if LINUX_VERSION_CODE >=KERNEL_VERSION(2,6,20) ++static void rtl8192_update_beacon(struct work_struct * work) ++{ ++ struct r8192_priv *priv = container_of(work, struct r8192_priv, update_beacon_wq.work); ++ struct net_device *dev = priv->ieee80211->dev; ++#else ++void rtl8192_update_beacon(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#endif ++ struct ieee80211_device* ieee = priv->ieee80211; ++ struct ieee80211_network* net = &ieee->current_network; ++ ++ if (ieee->pHTInfo->bCurrentHTSupport) ++ HTUpdateSelfAndPeerSetting(ieee, net); ++ ieee->pHTInfo->bCurrentRT2RTLongSlotTime = net->bssht.bdRT2RTLongSlotTime; ++ rtl8192_update_cap(dev, net->capability); ++} ++/* ++* background support to run QoS activate functionality ++*/ ++static int WDCAPARA_ADD[] = {EDCAPARA_BE,EDCAPARA_BK,EDCAPARA_VI,EDCAPARA_VO}; ++#if LINUX_VERSION_CODE >=KERNEL_VERSION(2,6,20) ++static void rtl8192_qos_activate(struct work_struct * work) ++{ ++ struct r8192_priv *priv = container_of(work, struct r8192_priv, qos_activate); ++ struct net_device *dev = priv->ieee80211->dev; ++#else ++void rtl8192_qos_activate(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#endif ++ struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters; ++ u8 mode = priv->ieee80211->current_network.mode; ++// u32 size = sizeof(struct ieee80211_qos_parameters); ++ u8 u1bAIFS; ++ u32 u4bAcParam; ++ int i; ++ if (priv == NULL) ++ return; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) ++ down(&priv->mutex); ++#else ++ mutex_lock(&priv->mutex); ++#endif ++ if(priv->ieee80211->state != IEEE80211_LINKED) ++ goto success; ++ RT_TRACE(COMP_QOS,"qos active process with associate response received\n"); ++ /* It better set slot time at first */ ++ /* For we just support b/g mode at present, let the slot time at 9/20 selection */ ++ /* update the ac parameter to related registers */ ++ for(i = 0; i < QOS_QUEUE_NUM; i++) { ++ //Mode G/A: slotTimeTimer = 9; Mode B: 20 ++ u1bAIFS = qos_parameters->aifs[i] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime; ++ u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[i]))<< AC_PARAM_TXOP_LIMIT_OFFSET)| ++ (((u32)(qos_parameters->cw_max[i]))<< AC_PARAM_ECW_MAX_OFFSET)| ++ (((u32)(qos_parameters->cw_min[i]))<< AC_PARAM_ECW_MIN_OFFSET)| ++ ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET)); ++ printk("===>u4bAcParam:%x, ", u4bAcParam); ++ write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam); ++ //write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332); ++ } ++ ++success: ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) ++ up(&priv->mutex); ++#else ++ mutex_unlock(&priv->mutex); ++#endif ++} ++ ++static int rtl8192_qos_handle_probe_response(struct r8192_priv *priv, ++ int active_network, ++ struct ieee80211_network *network) ++{ ++ int ret = 0; ++ u32 size = sizeof(struct ieee80211_qos_parameters); ++ ++ if(priv->ieee80211->state !=IEEE80211_LINKED) ++ return ret; ++ ++ if ((priv->ieee80211->iw_mode != IW_MODE_INFRA)) ++ return ret; ++ ++ if (network->flags & NETWORK_HAS_QOS_MASK) { ++ if (active_network && ++ (network->flags & NETWORK_HAS_QOS_PARAMETERS)) ++ network->qos_data.active = network->qos_data.supported; ++ ++ if ((network->qos_data.active == 1) && (active_network == 1) && ++ (network->flags & NETWORK_HAS_QOS_PARAMETERS) && ++ (network->qos_data.old_param_count != ++ network->qos_data.param_count)) { ++ network->qos_data.old_param_count = ++ network->qos_data.param_count; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ queue_work(priv->priv_wq, &priv->qos_activate); ++#else ++ schedule_task(&priv->qos_activate); ++#endif ++ RT_TRACE (COMP_QOS, "QoS parameters change call " ++ "qos_activate\n"); ++ } ++ } else { ++ memcpy(&priv->ieee80211->current_network.qos_data.parameters,\ ++ &def_qos_parameters, size); ++ ++ if ((network->qos_data.active == 1) && (active_network == 1)) { ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ queue_work(priv->priv_wq, &priv->qos_activate); ++#else ++ schedule_task(&priv->qos_activate); ++#endif ++ RT_TRACE(COMP_QOS, "QoS was disabled call qos_activate \n"); ++ } ++ network->qos_data.active = 0; ++ network->qos_data.supported = 0; ++ } ++ ++ return 0; ++} ++ ++/* handle manage frame frame beacon and probe response */ ++static int rtl8192_handle_beacon(struct net_device * dev, ++ struct ieee80211_beacon * beacon, ++ struct ieee80211_network * network) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ rtl8192_qos_handle_probe_response(priv,1,network); ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ queue_delayed_work(priv->priv_wq, &priv->update_beacon_wq, 0); ++#else ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++ schedule_task(&priv->update_beacon_wq); ++#else ++ queue_work(priv->priv_wq, &priv->update_beacon_wq); ++#endif ++#endif ++ return 0; ++ ++} ++ ++/* ++* handling the beaconing responses. if we get different QoS setting ++* off the network from the associated setting, adjust the QoS ++* setting ++*/ ++static int rtl8192_qos_association_resp(struct r8192_priv *priv, ++ struct ieee80211_network *network) ++{ ++ int ret = 0; ++ unsigned long flags; ++ u32 size = sizeof(struct ieee80211_qos_parameters); ++ int set_qos_param = 0; ++ ++ if ((priv == NULL) || (network == NULL)) ++ return ret; ++ ++ if(priv->ieee80211->state !=IEEE80211_LINKED) ++ return ret; ++ ++ if ((priv->ieee80211->iw_mode != IW_MODE_INFRA)) ++ return ret; ++ ++ spin_lock_irqsave(&priv->ieee80211->lock, flags); ++ if(network->flags & NETWORK_HAS_QOS_PARAMETERS) { ++ memcpy(&priv->ieee80211->current_network.qos_data.parameters,\ ++ &network->qos_data.parameters,\ ++ sizeof(struct ieee80211_qos_parameters)); ++ priv->ieee80211->current_network.qos_data.active = 1; ++#if 0 ++ if((priv->ieee80211->current_network.qos_data.param_count != \ ++ network->qos_data.param_count)) ++#endif ++ { ++ set_qos_param = 1; ++ /* update qos parameter for current network */ ++ priv->ieee80211->current_network.qos_data.old_param_count = \ ++ priv->ieee80211->current_network.qos_data.param_count; ++ priv->ieee80211->current_network.qos_data.param_count = \ ++ network->qos_data.param_count; ++ } ++ } else { ++ memcpy(&priv->ieee80211->current_network.qos_data.parameters,\ ++ &def_qos_parameters, size); ++ priv->ieee80211->current_network.qos_data.active = 0; ++ priv->ieee80211->current_network.qos_data.supported = 0; ++ set_qos_param = 1; ++ } ++ ++ spin_unlock_irqrestore(&priv->ieee80211->lock, flags); ++ ++ RT_TRACE(COMP_QOS, "%s: network->flags = %d,%d\n",__FUNCTION__,network->flags ,priv->ieee80211->current_network.qos_data.active); ++ if (set_qos_param == 1) ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ queue_work(priv->priv_wq, &priv->qos_activate); ++#else ++ schedule_task(&priv->qos_activate); ++#endif ++ ++ ++ return ret; ++} ++ ++ ++static int rtl8192_handle_assoc_response(struct net_device *dev, ++ struct ieee80211_assoc_response_frame *resp, ++ struct ieee80211_network *network) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ rtl8192_qos_association_resp(priv, network); ++ return 0; ++} ++ ++ ++//updateRATRTabel for MCS only. Basic rate is not implement. ++void rtl8192_update_ratr_table(struct net_device* dev) ++ // POCTET_STRING posLegacyRate, ++ // u8* pMcsRate) ++ // PRT_WLAN_STA pEntry) ++{ ++ struct r8192_priv* priv = ieee80211_priv(dev); ++ struct ieee80211_device* ieee = priv->ieee80211; ++ u8* pMcsRate = ieee->dot11HTOperationalRateSet; ++ //struct ieee80211_network *net = &ieee->current_network; ++ u32 ratr_value = 0; ++ u8 rate_index = 0; ++ ++ rtl8192_config_rate(dev, (u16*)(&ratr_value)); ++ ratr_value |= (*(u16*)(pMcsRate)) << 12; ++// switch (net->mode) ++ switch (ieee->mode) ++ { ++ case IEEE_A: ++ ratr_value &= 0x00000FF0; ++ break; ++ case IEEE_B: ++ ratr_value &= 0x0000000F; ++ break; ++ case IEEE_G: ++ ratr_value &= 0x00000FF7; ++ break; ++ case IEEE_N_24G: ++ case IEEE_N_5G: ++ if (ieee->pHTInfo->PeerMimoPs == 0) //MIMO_PS_STATIC ++ ratr_value &= 0x0007F007; ++ else{ ++ if (priv->rf_type == RF_1T2R) ++ ratr_value &= 0x000FF007; ++ else ++ ratr_value &= 0x0F81F007; ++ } ++ break; ++ default: ++ break; ++ } ++ ratr_value &= 0x0FFFFFFF; ++ if(ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI40MHz){ ++ ratr_value |= 0x80000000; ++ }else if(!ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI20MHz){ ++ ratr_value |= 0x80000000; ++ } ++ write_nic_dword(dev, RATR0+rate_index*4, ratr_value); ++ write_nic_byte(dev, UFWP, 1); ++} ++ ++static u8 ccmp_ie[4] = {0x00,0x50,0xf2,0x04}; ++static u8 ccmp_rsn_ie[4] = {0x00, 0x0f, 0xac, 0x04}; ++static bool GetNmodeSupportBySecCfg8190Pci(struct net_device*dev) ++{ ++#if 1 ++ struct r8192_priv* priv = ieee80211_priv(dev); ++ struct ieee80211_device* ieee = priv->ieee80211; ++ int wpa_ie_len= ieee->wpa_ie_len; ++ struct ieee80211_crypt_data* crypt; ++ int encrypt; ++ ++ crypt = ieee->crypt[ieee->tx_keyidx]; ++ encrypt = (ieee->current_network.capability & WLAN_CAPABILITY_PRIVACY) || (ieee->host_encrypt && crypt && crypt->ops && (0 == strcmp(crypt->ops->name,"WEP"))); ++ ++ /* simply judge */ ++ if(encrypt && (wpa_ie_len == 0)) { ++ /* wep encryption, no N mode setting */ ++ return false; ++// } else if((wpa_ie_len != 0)&&(memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) { ++ } else if((wpa_ie_len != 0)) { ++ /* parse pairwise key type */ ++ //if((pairwisekey = WEP40)||(pairwisekey = WEP104)||(pairwisekey = TKIP)) ++ if (((ieee->wpa_ie[0] == 0xdd) && (!memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) || ((ieee->wpa_ie[0] == 0x30) && (!memcmp(&ieee->wpa_ie[10],ccmp_rsn_ie, 4)))) ++ return true; ++ else ++ return false; ++ } else { ++ //RT_TRACE(COMP_ERR,"In %s The GroupEncAlgorithm is [4]\n",__FUNCTION__ ); ++ return true; ++ } ++ ++#if 0 ++ //In here we discuss with SD4 David. He think we still can send TKIP in broadcast group key in MCS rate. ++ //We can't force in G mode if Pairwie key is AES and group key is TKIP ++ if((pSecInfo->GroupEncAlgorithm == WEP104_Encryption) || (pSecInfo->GroupEncAlgorithm == WEP40_Encryption) || ++ (pSecInfo->PairwiseEncAlgorithm == WEP104_Encryption) || ++ (pSecInfo->PairwiseEncAlgorithm == WEP40_Encryption) || (pSecInfo->PairwiseEncAlgorithm == TKIP_Encryption)) ++ { ++ return false; ++ } ++ else ++ return true; ++#endif ++ return true; ++#endif ++} ++ ++static void rtl8192_refresh_supportrate(struct r8192_priv* priv) ++{ ++ struct ieee80211_device* ieee = priv->ieee80211; ++ //we donot consider set support rate for ABG mode, only HT MCS rate is set here. ++ if (ieee->mode == WIRELESS_MODE_N_24G || ieee->mode == WIRELESS_MODE_N_5G) ++ { ++ memcpy(ieee->Regdot11HTOperationalRateSet, ieee->RegHTSuppRateSet, 16); ++ //RT_DEBUG_DATA(COMP_INIT, ieee->RegHTSuppRateSet, 16); ++ //RT_DEBUG_DATA(COMP_INIT, ieee->Regdot11HTOperationalRateSet, 16); ++ } ++ else ++ memset(ieee->Regdot11HTOperationalRateSet, 0, 16); ++ return; ++} ++ ++static u8 rtl8192_getSupportedWireleeMode(struct net_device*dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 ret = 0; ++ switch(priv->rf_chip) ++ { ++ case RF_8225: ++ case RF_8256: ++ case RF_PSEUDO_11N: ++ ret = (WIRELESS_MODE_N_24G|WIRELESS_MODE_G|WIRELESS_MODE_B); ++ break; ++ case RF_8258: ++ ret = (WIRELESS_MODE_A|WIRELESS_MODE_N_5G); ++ break; ++ default: ++ ret = WIRELESS_MODE_B; ++ break; ++ } ++ return ret; ++} ++ ++static void rtl8192_SetWirelessMode(struct net_device* dev, u8 wireless_mode) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 bSupportMode = rtl8192_getSupportedWireleeMode(dev); ++ ++#if 1 ++ if ((wireless_mode == WIRELESS_MODE_AUTO) || ((wireless_mode&bSupportMode)==0)) ++ { ++ if(bSupportMode & WIRELESS_MODE_N_24G) ++ { ++ wireless_mode = WIRELESS_MODE_N_24G; ++ } ++ else if(bSupportMode & WIRELESS_MODE_N_5G) ++ { ++ wireless_mode = WIRELESS_MODE_N_5G; ++ } ++ else if((bSupportMode & WIRELESS_MODE_A)) ++ { ++ wireless_mode = WIRELESS_MODE_A; ++ } ++ else if((bSupportMode & WIRELESS_MODE_G)) ++ { ++ wireless_mode = WIRELESS_MODE_G; ++ } ++ else if((bSupportMode & WIRELESS_MODE_B)) ++ { ++ wireless_mode = WIRELESS_MODE_B; ++ } ++ else{ ++ RT_TRACE(COMP_ERR, "%s(), No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n", __FUNCTION__,bSupportMode); ++ wireless_mode = WIRELESS_MODE_B; ++ } ++ } ++#ifdef TO_DO_LIST //// TODO: this function doesn't work well at this time, we shoud wait for FPGA ++ ActUpdateChannelAccessSetting( pAdapter, pHalData->CurrentWirelessMode, &pAdapter->MgntInfo.Info8185.ChannelAccessSetting ); ++#endif ++ priv->ieee80211->mode = wireless_mode; ++ ++ if ((wireless_mode == WIRELESS_MODE_N_24G) || (wireless_mode == WIRELESS_MODE_N_5G)) ++ priv->ieee80211->pHTInfo->bEnableHT = 1; ++ else ++ priv->ieee80211->pHTInfo->bEnableHT = 0; ++ RT_TRACE(COMP_INIT, "Current Wireless Mode is %x\n", wireless_mode); ++ rtl8192_refresh_supportrate(priv); ++#endif ++ ++} ++//init priv variables here ++ ++static bool GetHalfNmodeSupportByAPs819xPci(struct net_device* dev) ++{ ++ bool Reval; ++ struct r8192_priv* priv = ieee80211_priv(dev); ++ struct ieee80211_device* ieee = priv->ieee80211; ++ ++ if(ieee->bHalfWirelessN24GMode == true) ++ Reval = true; ++ else ++ Reval = false; ++ ++ return Reval; ++} ++ ++short rtl8192_is_tx_queue_empty(struct net_device *dev) ++{ ++ int i=0; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ for (i=0; i<=MGNT_QUEUE; i++) ++ { ++ if ((i== TXCMD_QUEUE) || (i == HCCA_QUEUE) ) ++ continue; ++ if (skb_queue_len(&(&priv->tx_ring[i])->queue) > 0){ ++ printk("===>tx queue is not empty:%d, %d\n", i, skb_queue_len(&(&priv->tx_ring[i])->queue)); ++ return 0; ++ } ++ } ++ return 1; ++} ++#if 0 ++void rtl8192_rq_tx_ack(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ priv->ieee80211->ack_tx_to_ieee = 1; ++} ++#endif ++static void rtl8192_hw_sleep_down(struct net_device *dev) ++{ ++ RT_TRACE(COMP_POWER, "%s()============>come to sleep down\n", __FUNCTION__); ++ MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS); ++} ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++static void rtl8192_hw_sleep_wq (struct work_struct *work) ++{ ++// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq); ++// struct ieee80211_device * ieee = (struct ieee80211_device*) ++// container_of(work, struct ieee80211_device, watch_dog_wq); ++ struct delayed_work *dwork = container_of(work,struct delayed_work,work); ++ struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_sleep_wq); ++ struct net_device *dev = ieee->dev; ++#else ++void rtl8192_hw_sleep_wq(struct net_device* dev) ++{ ++#endif ++ //printk("=========>%s()\n", __FUNCTION__); ++ rtl8192_hw_sleep_down(dev); ++} ++// printk("dev is %d\n",dev); ++// printk("&*&(^*(&(&=========>%s()\n", __FUNCTION__); ++static void rtl8192_hw_wakeup(struct net_device* dev) ++{ ++// u32 flags = 0; ++ ++// spin_lock_irqsave(&priv->ps_lock,flags); ++ RT_TRACE(COMP_POWER, "%s()============>come to wake up\n", __FUNCTION__); ++ MgntActSet_RF_State(dev, eRfOn, RF_CHANGE_BY_PS); ++ //FIXME: will we send package stored while nic is sleep? ++// spin_unlock_irqrestore(&priv->ps_lock,flags); ++} ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void rtl8192_hw_wakeup_wq (struct work_struct *work) ++{ ++// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq); ++// struct ieee80211_device * ieee = (struct ieee80211_device*) ++// container_of(work, struct ieee80211_device, watch_dog_wq); ++ struct delayed_work *dwork = container_of(work,struct delayed_work,work); ++ struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_wakeup_wq); ++ struct net_device *dev = ieee->dev; ++#else ++void rtl8192_hw_wakeup_wq(struct net_device* dev) ++{ ++#endif ++ rtl8192_hw_wakeup(dev); ++ ++} ++ ++#define MIN_SLEEP_TIME 50 ++#define MAX_SLEEP_TIME 10000 ++static void rtl8192_hw_to_sleep(struct net_device *dev, u32 th, u32 tl) ++{ ++ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ u32 rb = jiffies; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->ps_lock,flags); ++ ++ /* Writing HW register with 0 equals to disable ++ * the timer, that is not really what we want ++ */ ++ tl -= MSECS(4+16+7); ++ ++ //if(tl == 0) tl = 1; ++ ++ /* FIXME HACK FIXME HACK */ ++// force_pci_posting(dev); ++ //mdelay(1); ++ ++// rb = read_nic_dword(dev, TSFTR); ++ ++ /* If the interval in witch we are requested to sleep is too ++ * short then give up and remain awake ++ */ ++ if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME)) ++ ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) { ++ spin_unlock_irqrestore(&priv->ps_lock,flags); ++ printk("too short to sleep\n"); ++ return; ++ } ++ ++// write_nic_dword(dev, TimerInt, tl); ++// rb = read_nic_dword(dev, TSFTR); ++ { ++ u32 tmp = (tl>rb)?(tl-rb):(rb-tl); ++ // if (tlieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb ++ } ++ /* if we suspect the TimerInt is gone beyond tl ++ * while setting it, then give up ++ */ ++#if 1 ++ if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))|| ++ ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) { ++ printk("========>too long to sleep:%x, %x, %lx\n", tl, rb, MSECS(MAX_SLEEP_TIME)); ++ spin_unlock_irqrestore(&priv->ps_lock,flags); ++ return; ++ } ++#endif ++// if(priv->rf_sleep) ++// priv->rf_sleep(dev); ++ ++ //printk("<=========%s()\n", __FUNCTION__); ++ queue_delayed_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq,0); ++ spin_unlock_irqrestore(&priv->ps_lock,flags); ++} ++static void rtl8192_init_priv_variable(struct net_device* dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 i; ++ priv->being_init_adapter = false; ++ priv->txbuffsize = 1600;//1024; ++ priv->txfwbuffersize = 4096; ++ priv->txringcount = 64;//32; ++ //priv->txbeaconcount = priv->txringcount; ++ priv->txbeaconcount = 2; ++ priv->rxbuffersize = 9100;//2048;//1024; ++ priv->rxringcount = MAX_RX_COUNT;//64; ++ priv->irq_enabled=0; ++ priv->card_8192 = NIC_8192E; ++ priv->rx_skb_complete = 1; ++ priv->chan = 1; //set to channel 1 ++ priv->RegWirelessMode = WIRELESS_MODE_AUTO; ++ priv->RegChannelPlan = 0xf; ++ priv->nrxAMPDU_size = 0; ++ priv->nrxAMPDU_aggr_num = 0; ++ priv->last_rxdesc_tsf_high = 0; ++ priv->last_rxdesc_tsf_low = 0; ++ priv->ieee80211->mode = WIRELESS_MODE_AUTO; //SET AUTO ++ priv->ieee80211->iw_mode = IW_MODE_INFRA; ++ priv->ieee80211->ieee_up=0; ++ priv->retry_rts = DEFAULT_RETRY_RTS; ++ priv->retry_data = DEFAULT_RETRY_DATA; ++ priv->ieee80211->rts = DEFAULT_RTS_THRESHOLD; ++ priv->ieee80211->rate = 110; //11 mbps ++ priv->ieee80211->short_slot = 1; ++ priv->promisc = (dev->flags & IFF_PROMISC) ? 1:0; ++ priv->bcck_in_ch14 = false; ++ priv->bfsync_processing = false; ++ priv->CCKPresentAttentuation = 0; ++ priv->rfa_txpowertrackingindex = 0; ++ priv->rfc_txpowertrackingindex = 0; ++ priv->CckPwEnl = 6; ++ priv->ScanDelay = 50;//for Scan TODO ++ //added by amy for silent reset ++ priv->ResetProgress = RESET_TYPE_NORESET; ++ priv->bForcedSilentReset = 0; ++ priv->bDisableNormalResetCheck = false; ++ priv->force_reset = false; ++ //added by amy for power save ++ priv->RegRfOff = 0; ++ priv->ieee80211->RfOffReason = 0; ++ priv->RFChangeInProgress = false; ++ priv->bHwRfOffAction = 0; ++ priv->SetRFPowerStateInProgress = false; ++ priv->ieee80211->PowerSaveControl.bInactivePs = true; ++ priv->ieee80211->PowerSaveControl.bIPSModeBackup = false; ++ //just for debug ++ priv->txpower_checkcnt = 0; ++ priv->thermal_readback_index =0; ++ priv->txpower_tracking_callback_cnt = 0; ++ priv->ccktxpower_adjustcnt_ch14 = 0; ++ priv->ccktxpower_adjustcnt_not_ch14 = 0; ++ ++ priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL; ++ priv->ieee80211->iw_mode = IW_MODE_INFRA; ++ priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN | ++ IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ | ++ IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;/* | ++ IEEE_SOFTMAC_BEACONS;*///added by amy 080604 //| //IEEE_SOFTMAC_SINGLE_QUEUE; ++ ++ priv->ieee80211->active_scan = 1; ++ priv->ieee80211->modulation = IEEE80211_CCK_MODULATION | IEEE80211_OFDM_MODULATION; ++ priv->ieee80211->host_encrypt = 1; ++ priv->ieee80211->host_decrypt = 1; ++ //priv->ieee80211->start_send_beacons = NULL;//rtl819xusb_beacon_tx;//-by amy 080604 ++ //priv->ieee80211->stop_send_beacons = NULL;//rtl8192_beacon_stop;//-by amy 080604 ++ priv->ieee80211->start_send_beacons = rtl8192_start_beacon;//+by david 081107 ++ priv->ieee80211->stop_send_beacons = rtl8192_stop_beacon;//+by david 081107 ++ priv->ieee80211->softmac_hard_start_xmit = rtl8192_hard_start_xmit; ++ priv->ieee80211->set_chan = rtl8192_set_chan; ++ priv->ieee80211->link_change = rtl8192_link_change; ++ priv->ieee80211->softmac_data_hard_start_xmit = rtl8192_hard_data_xmit; ++ priv->ieee80211->data_hard_stop = rtl8192_data_hard_stop; ++ priv->ieee80211->data_hard_resume = rtl8192_data_hard_resume; ++ priv->ieee80211->init_wmmparam_flag = 0; ++ priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD; ++ priv->ieee80211->check_nic_enough_desc = check_nic_enough_desc; ++ priv->ieee80211->tx_headroom = sizeof(TX_FWINFO_8190PCI); ++ priv->ieee80211->qos_support = 1; ++ priv->ieee80211->dot11PowerSaveMode = 0; ++ //added by WB ++// priv->ieee80211->SwChnlByTimerHandler = rtl8192_phy_SwChnl; ++ priv->ieee80211->SetBWModeHandler = rtl8192_SetBWMode; ++ priv->ieee80211->handle_assoc_response = rtl8192_handle_assoc_response; ++ priv->ieee80211->handle_beacon = rtl8192_handle_beacon; ++ ++ priv->ieee80211->sta_wake_up = rtl8192_hw_wakeup; ++// priv->ieee80211->ps_request_tx_ack = rtl8192_rq_tx_ack; ++ priv->ieee80211->enter_sleep_state = rtl8192_hw_to_sleep; ++ priv->ieee80211->ps_is_queue_empty = rtl8192_is_tx_queue_empty; ++ //added by david ++ priv->ieee80211->GetNmodeSupportBySecCfg = GetNmodeSupportBySecCfg8190Pci; ++ priv->ieee80211->SetWirelessMode = rtl8192_SetWirelessMode; ++ priv->ieee80211->GetHalfNmodeSupportByAPsHandler = GetHalfNmodeSupportByAPs819xPci; ++ ++ //added by amy ++ priv->ieee80211->InitialGainHandler = InitialGain819xPci; ++ ++ priv->card_type = USB; ++ { ++ priv->ShortRetryLimit = 0x30; ++ priv->LongRetryLimit = 0x30; ++ } ++ priv->EarlyRxThreshold = 7; ++ priv->enable_gpio0 = 0; ++ ++ priv->TransmitConfig = 0; ++ ++ priv->ReceiveConfig = RCR_ADD3 | ++ RCR_AMF | RCR_ADF | //accept management/data ++ RCR_AICV | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko. ++ RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC ++ RCR_AAP | ((u32)7<irq_mask = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK | IMR_BEDOK | IMR_BKDOK |\ ++ IMR_HCCADOK | IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |\ ++ IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 | IMR_RDU | IMR_RXFOVW |\ ++ IMR_TXFOVW | IMR_BcnInt | IMR_TBDOK | IMR_TBDER); ++ ++ priv->AcmControl = 0; ++ priv->pFirmware = (rt_firmware*)vmalloc(sizeof(rt_firmware)); ++ if (priv->pFirmware) ++ memset(priv->pFirmware, 0, sizeof(rt_firmware)); ++ ++ /* rx related queue */ ++ skb_queue_head_init(&priv->rx_queue); ++ skb_queue_head_init(&priv->skb_queue); ++ ++ /* Tx related queue */ ++ for(i = 0; i < MAX_QUEUE_SIZE; i++) { ++ skb_queue_head_init(&priv->ieee80211->skb_waitQ [i]); ++ } ++ for(i = 0; i < MAX_QUEUE_SIZE; i++) { ++ skb_queue_head_init(&priv->ieee80211->skb_aggQ [i]); ++ } ++ priv->rf_set_chan = rtl8192_phy_SwChnl; ++} ++ ++//init lock here ++static void rtl8192_init_priv_lock(struct r8192_priv* priv) ++{ ++ spin_lock_init(&priv->tx_lock); ++ spin_lock_init(&priv->irq_lock);//added by thomas ++ spin_lock_init(&priv->irq_th_lock); ++ spin_lock_init(&priv->rf_ps_lock); ++ spin_lock_init(&priv->ps_lock); ++ //spin_lock_init(&priv->rf_lock); ++ sema_init(&priv->wx_sem,1); ++ sema_init(&priv->rf_sem,1); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) ++ sema_init(&priv->mutex, 1); ++#else ++ mutex_init(&priv->mutex); ++#endif ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++extern void rtl819x_watchdog_wqcallback(struct work_struct *work); ++#else ++extern void rtl819x_watchdog_wqcallback(struct net_device *dev); ++#endif ++ ++void rtl8192_irq_rx_tasklet(struct r8192_priv *priv); ++void rtl8192_irq_tx_tasklet(struct r8192_priv *priv); ++void rtl8192_prepare_beacon(struct r8192_priv *priv); ++//init tasklet and wait_queue here. only 2.6 above kernel is considered ++#define DRV_NAME "wlan0" ++static void rtl8192_init_priv_task(struct net_device* dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++#ifdef PF_SYNCTHREAD ++ priv->priv_wq = create_workqueue(DRV_NAME,0); ++#else ++ priv->priv_wq = create_workqueue(DRV_NAME); ++#endif ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++// INIT_WORK(&priv->reset_wq, (void(*)(void*)) rtl8192_restart); ++ INIT_WORK(&priv->reset_wq, rtl8192_restart); ++// INIT_DELAYED_WORK(&priv->watch_dog_wq, hal_dm_watchdog); ++ INIT_DELAYED_WORK(&priv->watch_dog_wq, rtl819x_watchdog_wqcallback); ++ INIT_DELAYED_WORK(&priv->txpower_tracking_wq, dm_txpower_trackingcallback); ++ INIT_DELAYED_WORK(&priv->rfpath_check_wq, dm_rf_pathcheck_workitemcallback); ++ INIT_DELAYED_WORK(&priv->update_beacon_wq, rtl8192_update_beacon); ++ //INIT_WORK(&priv->SwChnlWorkItem, rtl8192_SwChnl_WorkItem); ++ //INIT_WORK(&priv->SetBWModeWorkItem, rtl8192_SetBWModeWorkItem); ++ INIT_WORK(&priv->qos_activate, rtl8192_qos_activate); ++ INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8192_hw_wakeup_wq); ++ INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq,(void*) rtl8192_hw_sleep_wq); ++ ++#else ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) ++ tq_init(&priv->reset_wq, (void*)rtl8192_restart, dev); ++ tq_init(&priv->watch_dog_wq, (void*)rtl819x_watchdog_wqcallback, dev); ++ tq_init(&priv->txpower_tracking_wq, (void*)dm_txpower_trackingcallback, dev); ++ tq_init(&priv->rfpath_check_wq, (void*)dm_rf_pathcheck_workitemcallback, dev); ++ tq_init(&priv->update_beacon_wq, (void*)rtl8192_update_beacon, dev); ++ //tq_init(&priv->SwChnlWorkItem, (void*) rtl8192_SwChnl_WorkItem, dev); ++ //tq_init(&priv->SetBWModeWorkItem, (void*)rtl8192_SetBWModeWorkItem, dev); ++ tq_init(&priv->qos_activate, (void *)rtl8192_qos_activate, dev); ++ tq_init(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8192_hw_wakeup_wq, dev); ++ tq_init(&priv->ieee80211->hw_sleep_wq,(void*) rtl8192_hw_sleep_wq, dev); ++ ++#else ++ INIT_WORK(&priv->reset_wq,(void(*)(void*)) rtl8192_restart,dev); ++// INIT_WORK(&priv->watch_dog_wq, (void(*)(void*)) hal_dm_watchdog,dev); ++ INIT_WORK(&priv->watch_dog_wq, (void(*)(void*)) rtl819x_watchdog_wqcallback,dev); ++ INIT_WORK(&priv->txpower_tracking_wq, (void(*)(void*)) dm_txpower_trackingcallback,dev); ++ INIT_WORK(&priv->rfpath_check_wq, (void(*)(void*)) dm_rf_pathcheck_workitemcallback,dev); ++ INIT_WORK(&priv->update_beacon_wq, (void(*)(void*))rtl8192_update_beacon,dev); ++ //INIT_WORK(&priv->SwChnlWorkItem, (void(*)(void*)) rtl8192_SwChnl_WorkItem, dev); ++ //INIT_WORK(&priv->SetBWModeWorkItem, (void(*)(void*)) rtl8192_SetBWModeWorkItem, dev); ++ INIT_WORK(&priv->qos_activate, (void(*)(void *))rtl8192_qos_activate, dev); ++ INIT_WORK(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8192_hw_wakeup_wq, dev); ++ INIT_WORK(&priv->ieee80211->hw_sleep_wq,(void*) rtl8192_hw_sleep_wq, dev); ++#endif ++#endif ++ ++ tasklet_init(&priv->irq_rx_tasklet, ++ (void(*)(unsigned long))rtl8192_irq_rx_tasklet, ++ (unsigned long)priv); ++ tasklet_init(&priv->irq_tx_tasklet, ++ (void(*)(unsigned long))rtl8192_irq_tx_tasklet, ++ (unsigned long)priv); ++ tasklet_init(&priv->irq_prepare_beacon_tasklet, ++ (void(*)(unsigned long))rtl8192_prepare_beacon, ++ (unsigned long)priv); ++} ++ ++static void rtl8192_get_eeprom_size(struct net_device* dev) ++{ ++ u16 curCR = 0; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ RT_TRACE(COMP_INIT, "===========>%s()\n", __FUNCTION__); ++ curCR = read_nic_dword(dev, EPROM_CMD); ++ RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD, curCR); ++ //whether need I consider BIT5? ++ priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EPROM_93c56 : EPROM_93c46; ++ RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __FUNCTION__, priv->epromtype); ++} ++ ++//used to swap endian. as ntohl & htonl are not neccessary to swap endian, so use this instead. ++static inline u16 endian_swap(u16* data) ++{ ++ u16 tmp = *data; ++ *data = (tmp >> 8) | (tmp << 8); ++ return *data; ++} ++ ++/* ++ * Note: Adapter->EEPROMAddressSize should be set before this function call. ++ * EEPROM address size can be got through GetEEPROMSize8185() ++*/ ++static void rtl8192_read_eeprom_info(struct net_device* dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ u8 tempval; ++#ifdef RTL8192E ++ u8 ICVer8192, ICVer8256; ++#endif ++ u16 i,usValue, IC_Version; ++ u16 EEPROMId; ++#ifdef RTL8190P ++ u8 offset;//, tmpAFR; ++ u8 EepromTxPower[100]; ++#endif ++ u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01}; ++ RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n"); ++ ++ ++ // TODO: I don't know if we need to apply EF function to EEPROM read function ++ ++ //2 Read EEPROM ID to make sure autoload is success ++ EEPROMId = eprom_read(dev, 0); ++ if( EEPROMId != RTL8190_EEPROM_ID ) ++ { ++ RT_TRACE(COMP_ERR, "EEPROM ID is invalid:%x, %x\n", EEPROMId, RTL8190_EEPROM_ID); ++ priv->AutoloadFailFlag=true; ++ } ++ else ++ { ++ priv->AutoloadFailFlag=false; ++ } ++ ++ // ++ // Assign Chip Version ID ++ // ++ // Read IC Version && Channel Plan ++ if(!priv->AutoloadFailFlag) ++ { ++ // VID, PID ++ priv->eeprom_vid = eprom_read(dev, (EEPROM_VID >> 1)); ++ priv->eeprom_did = eprom_read(dev, (EEPROM_DID >> 1)); ++ ++ usValue = eprom_read(dev, (u16)(EEPROM_Customer_ID>>1)) >> 8 ; ++ priv->eeprom_CustomerID = (u8)( usValue & 0xff); ++ usValue = eprom_read(dev, (EEPROM_ICVersion_ChannelPlan>>1)); ++ priv->eeprom_ChannelPlan = usValue&0xff; ++ IC_Version = ((usValue&0xff00)>>8); ++ ++#ifdef RTL8190P ++ priv->card_8192_version = (VERSION_8190)(IC_Version); ++#else ++ #ifdef RTL8192E ++ ICVer8192 = (IC_Version&0xf); //bit0~3; 1:A cut, 2:B cut, 3:C cut... ++ ICVer8256 = ((IC_Version&0xf0)>>4);//bit4~6, bit7 reserved for other RF chip; 1:A cut, 2:B cut, 3:C cut... ++ RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192); ++ RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256); ++ if(ICVer8192 == 0x2) //B-cut ++ { ++ if(ICVer8256 == 0x5) //E-cut ++ priv->card_8192_version= VERSION_8190_BE; ++ } ++ #endif ++#endif ++ switch(priv->card_8192_version) ++ { ++ case VERSION_8190_BD: ++ case VERSION_8190_BE: ++ break; ++ default: ++ priv->card_8192_version = VERSION_8190_BD; ++ break; ++ } ++ RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", priv->card_8192_version); ++ } ++ else ++ { ++ priv->card_8192_version = VERSION_8190_BD; ++ priv->eeprom_vid = 0; ++ priv->eeprom_did = 0; ++ priv->eeprom_CustomerID = 0; ++ priv->eeprom_ChannelPlan = 0; ++ RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff); ++ } ++ ++ RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid); ++ RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did); ++ RT_TRACE(COMP_INIT,"EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID); ++ ++ //2 Read Permanent MAC address ++ if(!priv->AutoloadFailFlag) ++ { ++ for(i = 0; i < 6; i += 2) ++ { ++ usValue = eprom_read(dev, (u16) ((EEPROM_NODE_ADDRESS_BYTE_0+i)>>1)); ++ *(u16*)(&dev->dev_addr[i]) = usValue; ++ } ++ } else { ++ // when auto load failed, the last address byte set to be a random one. ++ // added by david woo.2007/11/7 ++ memcpy(dev->dev_addr, bMac_Tmp_Addr, 6); ++ #if 0 ++ for(i = 0; i < 6; i++) ++ { ++ Adapter->PermanentAddress[i] = sMacAddr[i]; ++ PlatformEFIOWrite1Byte(Adapter, IDR0+i, sMacAddr[i]); ++ } ++ #endif ++ } ++ ++ RT_TRACE(COMP_INIT, "Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", ++ dev->dev_addr[0], dev->dev_addr[1], ++ dev->dev_addr[2], dev->dev_addr[3], ++ dev->dev_addr[4], dev->dev_addr[5]); ++ ++ //2 TX Power Check EEPROM Fail or not ++ if(priv->card_8192_version > VERSION_8190_BD) { ++ priv->bTXPowerDataReadFromEEPORM = true; ++ } else { ++ priv->bTXPowerDataReadFromEEPORM = false; ++ } ++ ++ // 2007/11/15 MH 8190PCI Default=2T4R, 8192PCIE dafault=1T2R ++ priv->rf_type = RTL819X_DEFAULT_RF_TYPE; ++ ++ if(priv->card_8192_version > VERSION_8190_BD) ++ { ++ // Read RF-indication and Tx Power gain index diff of legacy to HT OFDM rate. ++ if(!priv->AutoloadFailFlag) ++ { ++ tempval = (eprom_read(dev, (EEPROM_RFInd_PowerDiff>>1))) & 0xff; ++ priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf; // bit[3:0] ++ ++ if (tempval&0x80) //RF-indication, bit[7] ++ priv->rf_type = RF_1T2R; ++ else ++ priv->rf_type = RF_2T4R; ++ } ++ else ++ { ++ priv->EEPROMLegacyHTTxPowerDiff = EEPROM_Default_LegacyHTTxPowerDiff; ++ } ++ RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n", ++ priv->EEPROMLegacyHTTxPowerDiff); ++ ++ // Read ThermalMeter from EEPROM ++ if(!priv->AutoloadFailFlag) ++ { ++ priv->EEPROMThermalMeter = (u8)(((eprom_read(dev, (EEPROM_ThermalMeter>>1))) & 0xff00)>>8); ++ } ++ else ++ { ++ priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter; ++ } ++ RT_TRACE(COMP_INIT, "ThermalMeter = %d\n", priv->EEPROMThermalMeter); ++ //vivi, for tx power track ++ priv->TSSI_13dBm = priv->EEPROMThermalMeter *100; ++ ++ if(priv->epromtype == EPROM_93c46) ++ { ++ // Read antenna tx power offset of B/C/D to A and CrystalCap from EEPROM ++ if(!priv->AutoloadFailFlag) ++ { ++ usValue = eprom_read(dev, (EEPROM_TxPwDiff_CrystalCap>>1)); ++ priv->EEPROMAntPwDiff = (usValue&0x0fff); ++ priv->EEPROMCrystalCap = (u8)((usValue&0xf000)>>12); ++ } ++ else ++ { ++ priv->EEPROMAntPwDiff = EEPROM_Default_AntTxPowerDiff; ++ priv->EEPROMCrystalCap = EEPROM_Default_TxPwDiff_CrystalCap; ++ } ++ RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n", priv->EEPROMAntPwDiff); ++ RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n", priv->EEPROMCrystalCap); ++ ++ // ++ // Get per-channel Tx Power Level ++ // ++ for(i=0; i<14; i+=2) ++ { ++ if(!priv->AutoloadFailFlag) ++ { ++ usValue = eprom_read(dev, (u16) ((EEPROM_TxPwIndex_CCK+i)>>1) ); ++ } ++ else ++ { ++ usValue = EEPROM_Default_TxPower; ++ } ++ *((u16*)(&priv->EEPROMTxPowerLevelCCK[i])) = usValue; ++ RT_TRACE(COMP_INIT,"CCK Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelCCK[i]); ++ RT_TRACE(COMP_INIT, "CCK Tx Power Level, Index %d = 0x%02x\n", i+1, priv->EEPROMTxPowerLevelCCK[i+1]); ++ } ++ for(i=0; i<14; i+=2) ++ { ++ if(!priv->AutoloadFailFlag) ++ { ++ usValue = eprom_read(dev, (u16) ((EEPROM_TxPwIndex_OFDM_24G+i)>>1) ); ++ } ++ else ++ { ++ usValue = EEPROM_Default_TxPower; ++ } ++ *((u16*)(&priv->EEPROMTxPowerLevelOFDM24G[i])) = usValue; ++ RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelOFDM24G[i]); ++ RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i+1, priv->EEPROMTxPowerLevelOFDM24G[i+1]); ++ } ++ } ++ else if(priv->epromtype== EPROM_93c56) ++ { ++ #ifdef RTL8190P ++ // Read CrystalCap from EEPROM ++ if(!priv->AutoloadFailFlag) ++ { ++ priv->EEPROMAntPwDiff = EEPROM_Default_AntTxPowerDiff; ++ priv->EEPROMCrystalCap = (u8)(((eprom_read(dev, (EEPROM_C56_CrystalCap>>1))) & 0xf000)>>12); ++ } ++ else ++ { ++ priv->EEPROMAntPwDiff = EEPROM_Default_AntTxPowerDiff; ++ priv->EEPROMCrystalCap = EEPROM_Default_TxPwDiff_CrystalCap; ++ } ++ RT_TRACE(COMP_INIT,"EEPROMAntPwDiff = %d\n", priv->EEPROMAntPwDiff); ++ RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n", priv->EEPROMCrystalCap); ++ ++ // Get Tx Power Level by Channel ++ if(!priv->AutoloadFailFlag) ++ { ++ // Read Tx power of Channel 1 ~ 14 from EEPROM. ++ for(i = 0; i < 12; i+=2) ++ { ++ if (i <6) ++ offset = EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex + i; ++ else ++ offset = EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex + i - 6; ++ usValue = eprom_read(dev, (offset>>1)); ++ *((u16*)(&EepromTxPower[i])) = usValue; ++ } ++ ++ for(i = 0; i < 12; i++) ++ { ++ if (i <= 2) ++ priv->EEPROMRfACCKChnl1TxPwLevel[i] = EepromTxPower[i]; ++ else if ((i >=3 )&&(i <= 5)) ++ priv->EEPROMRfAOfdmChnlTxPwLevel[i-3] = EepromTxPower[i]; ++ else if ((i >=6 )&&(i <= 8)) ++ priv->EEPROMRfCCCKChnl1TxPwLevel[i-6] = EepromTxPower[i]; ++ else ++ priv->EEPROMRfCOfdmChnlTxPwLevel[i-9] = EepromTxPower[i]; ++ } ++ } ++ else ++ { ++ priv->EEPROMRfACCKChnl1TxPwLevel[0] = EEPROM_Default_TxPowerLevel; ++ priv->EEPROMRfACCKChnl1TxPwLevel[1] = EEPROM_Default_TxPowerLevel; ++ priv->EEPROMRfACCKChnl1TxPwLevel[2] = EEPROM_Default_TxPowerLevel; ++ ++ priv->EEPROMRfAOfdmChnlTxPwLevel[0] = EEPROM_Default_TxPowerLevel; ++ priv->EEPROMRfAOfdmChnlTxPwLevel[1] = EEPROM_Default_TxPowerLevel; ++ priv->EEPROMRfAOfdmChnlTxPwLevel[2] = EEPROM_Default_TxPowerLevel; ++ ++ priv->EEPROMRfCCCKChnl1TxPwLevel[0] = EEPROM_Default_TxPowerLevel; ++ priv->EEPROMRfCCCKChnl1TxPwLevel[1] = EEPROM_Default_TxPowerLevel; ++ priv->EEPROMRfCCCKChnl1TxPwLevel[2] = EEPROM_Default_TxPowerLevel; ++ ++ priv->EEPROMRfCOfdmChnlTxPwLevel[0] = EEPROM_Default_TxPowerLevel; ++ priv->EEPROMRfCOfdmChnlTxPwLevel[1] = EEPROM_Default_TxPowerLevel; ++ priv->EEPROMRfCOfdmChnlTxPwLevel[2] = EEPROM_Default_TxPowerLevel; ++ } ++ RT_TRACE(COMP_INIT, "priv->EEPROMRfACCKChnl1TxPwLevel[0] = 0x%x\n", priv->EEPROMRfACCKChnl1TxPwLevel[0]); ++ RT_TRACE(COMP_INIT, "priv->EEPROMRfACCKChnl1TxPwLevel[1] = 0x%x\n", priv->EEPROMRfACCKChnl1TxPwLevel[1]); ++ RT_TRACE(COMP_INIT, "priv->EEPROMRfACCKChnl1TxPwLevel[2] = 0x%x\n", priv->EEPROMRfACCKChnl1TxPwLevel[2]); ++ RT_TRACE(COMP_INIT, "priv->EEPROMRfAOfdmChnlTxPwLevel[0] = 0x%x\n", priv->EEPROMRfAOfdmChnlTxPwLevel[0]); ++ RT_TRACE(COMP_INIT, "priv->EEPROMRfAOfdmChnlTxPwLevel[1] = 0x%x\n", priv->EEPROMRfAOfdmChnlTxPwLevel[1]); ++ RT_TRACE(COMP_INIT, "priv->EEPROMRfAOfdmChnlTxPwLevel[2] = 0x%x\n", priv->EEPROMRfAOfdmChnlTxPwLevel[2]); ++ RT_TRACE(COMP_INIT, "priv->EEPROMRfCCCKChnl1TxPwLevel[0] = 0x%x\n", priv->EEPROMRfCCCKChnl1TxPwLevel[0]); ++ RT_TRACE(COMP_INIT, "priv->EEPROMRfCCCKChnl1TxPwLevel[1] = 0x%x\n", priv->EEPROMRfCCCKChnl1TxPwLevel[1]); ++ RT_TRACE(COMP_INIT, "priv->EEPROMRfCCCKChnl1TxPwLevel[2] = 0x%x\n", priv->EEPROMRfCCCKChnl1TxPwLevel[2]); ++ RT_TRACE(COMP_INIT, "priv->EEPROMRfCOfdmChnlTxPwLevel[0] = 0x%x\n", priv->EEPROMRfCOfdmChnlTxPwLevel[0]); ++ RT_TRACE(COMP_INIT, "priv->EEPROMRfCOfdmChnlTxPwLevel[1] = 0x%x\n", priv->EEPROMRfCOfdmChnlTxPwLevel[1]); ++ RT_TRACE(COMP_INIT, "priv->EEPROMRfCOfdmChnlTxPwLevel[2] = 0x%x\n", priv->EEPROMRfCOfdmChnlTxPwLevel[2]); ++#endif ++ ++ } ++ // ++ // Update HAL variables. ++ // ++ if(priv->epromtype == EPROM_93c46) ++ { ++ for(i=0; i<14; i++) ++ { ++ priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK[i]; ++ priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i]; ++ } ++ priv->LegacyHTTxPowerDiff = priv->EEPROMLegacyHTTxPowerDiff; ++ // Antenna B gain offset to antenna A, bit0~3 ++ priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff & 0xf); ++ // Antenna C gain offset to antenna A, bit4~7 ++ priv->AntennaTxPwDiff[1] = ((priv->EEPROMAntPwDiff & 0xf0)>>4); ++ // Antenna D gain offset to antenna A, bit8~11 ++ priv->AntennaTxPwDiff[2] = ((priv->EEPROMAntPwDiff & 0xf00)>>8); ++ // CrystalCap, bit12~15 ++ priv->CrystalCap = priv->EEPROMCrystalCap; ++ // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2 ++ priv->ThermalMeter[0] = (priv->EEPROMThermalMeter & 0xf); ++ priv->ThermalMeter[1] = ((priv->EEPROMThermalMeter & 0xf0)>>4); ++ } ++ else if(priv->epromtype == EPROM_93c56) ++ { ++ //char cck_pwr_diff_a=0, cck_pwr_diff_c=0; ++ ++ //cck_pwr_diff_a = pHalData->EEPROMRfACCKChnl7TxPwLevel - pHalData->EEPROMRfAOfdmChnlTxPwLevel[1]; ++ //cck_pwr_diff_c = pHalData->EEPROMRfCCCKChnl7TxPwLevel - pHalData->EEPROMRfCOfdmChnlTxPwLevel[1]; ++ for(i=0; i<3; i++) // channel 1~3 use the same Tx Power Level. ++ { ++ priv->TxPowerLevelCCK_A[i] = priv->EEPROMRfACCKChnl1TxPwLevel[0]; ++ priv->TxPowerLevelOFDM24G_A[i] = priv->EEPROMRfAOfdmChnlTxPwLevel[0]; ++ priv->TxPowerLevelCCK_C[i] = priv->EEPROMRfCCCKChnl1TxPwLevel[0]; ++ priv->TxPowerLevelOFDM24G_C[i] = priv->EEPROMRfCOfdmChnlTxPwLevel[0]; ++ } ++ for(i=3; i<9; i++) // channel 4~9 use the same Tx Power Level ++ { ++ priv->TxPowerLevelCCK_A[i] = priv->EEPROMRfACCKChnl1TxPwLevel[1]; ++ priv->TxPowerLevelOFDM24G_A[i] = priv->EEPROMRfAOfdmChnlTxPwLevel[1]; ++ priv->TxPowerLevelCCK_C[i] = priv->EEPROMRfCCCKChnl1TxPwLevel[1]; ++ priv->TxPowerLevelOFDM24G_C[i] = priv->EEPROMRfCOfdmChnlTxPwLevel[1]; ++ } ++ for(i=9; i<14; i++) // channel 10~14 use the same Tx Power Level ++ { ++ priv->TxPowerLevelCCK_A[i] = priv->EEPROMRfACCKChnl1TxPwLevel[2]; ++ priv->TxPowerLevelOFDM24G_A[i] = priv->EEPROMRfAOfdmChnlTxPwLevel[2]; ++ priv->TxPowerLevelCCK_C[i] = priv->EEPROMRfCCCKChnl1TxPwLevel[2]; ++ priv->TxPowerLevelOFDM24G_C[i] = priv->EEPROMRfCOfdmChnlTxPwLevel[2]; ++ } ++ for(i=0; i<14; i++) ++ RT_TRACE(COMP_INIT, "priv->TxPowerLevelCCK_A[%d] = 0x%x\n", i, priv->TxPowerLevelCCK_A[i]); ++ for(i=0; i<14; i++) ++ RT_TRACE(COMP_INIT,"priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n", i, priv->TxPowerLevelOFDM24G_A[i]); ++ for(i=0; i<14; i++) ++ RT_TRACE(COMP_INIT, "priv->TxPowerLevelCCK_C[%d] = 0x%x\n", i, priv->TxPowerLevelCCK_C[i]); ++ for(i=0; i<14; i++) ++ RT_TRACE(COMP_INIT, "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n", i, priv->TxPowerLevelOFDM24G_C[i]); ++ priv->LegacyHTTxPowerDiff = priv->EEPROMLegacyHTTxPowerDiff; ++ priv->AntennaTxPwDiff[0] = 0; ++ priv->AntennaTxPwDiff[1] = 0; ++ priv->AntennaTxPwDiff[2] = 0; ++ priv->CrystalCap = priv->EEPROMCrystalCap; ++ // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2 ++ priv->ThermalMeter[0] = (priv->EEPROMThermalMeter & 0xf); ++ priv->ThermalMeter[1] = ((priv->EEPROMThermalMeter & 0xf0)>>4); ++ } ++ } ++ ++ if(priv->rf_type == RF_1T2R) ++ { ++ RT_TRACE(COMP_INIT, "\n1T2R config\n"); ++ } ++ else if (priv->rf_type == RF_2T4R) ++ { ++ RT_TRACE(COMP_INIT, "\n2T4R config\n"); ++ } ++ ++ // 2008/01/16 MH We can only know RF type in the function. So we have to init ++ // DIG RATR table again. ++ init_rate_adaptive(dev); ++ ++ //1 Make a copy for following variables and we can change them if we want ++ ++ priv->rf_chip= RF_8256; ++ ++ if(priv->RegChannelPlan == 0xf) ++ { ++ priv->ChannelPlan = priv->eeprom_ChannelPlan; ++ } ++ else ++ { ++ priv->ChannelPlan = priv->RegChannelPlan; ++ } ++ ++ // ++ // Used PID and DID to Set CustomerID ++ // ++ if( priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304 ) ++ { ++ priv->CustomerID = RT_CID_DLINK; ++ } ++ ++ switch(priv->eeprom_CustomerID) ++ { ++ case EEPROM_CID_DEFAULT: ++ priv->CustomerID = RT_CID_DEFAULT; ++ break; ++ case EEPROM_CID_CAMEO: ++ priv->CustomerID = RT_CID_819x_CAMEO; ++ break; ++ case EEPROM_CID_RUNTOP: ++ priv->CustomerID = RT_CID_819x_RUNTOP; ++ break; ++ case EEPROM_CID_NetCore: ++ priv->CustomerID = RT_CID_819x_Netcore; ++ break; ++ case EEPROM_CID_TOSHIBA: // Merge by Jacken, 2008/01/31 ++ priv->CustomerID = RT_CID_TOSHIBA; ++ if(priv->eeprom_ChannelPlan&0x80) ++ priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f; ++ else ++ priv->ChannelPlan = 0x0; ++ RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n", ++ priv->ChannelPlan); ++ break; ++ case EEPROM_CID_Nettronix: ++ priv->ScanDelay = 100; //cosa add for scan ++ priv->CustomerID = RT_CID_Nettronix; ++ break; ++ case EEPROM_CID_Pronet: ++ priv->CustomerID = RT_CID_PRONET; ++ break; ++ case EEPROM_CID_DLINK: ++ priv->CustomerID = RT_CID_DLINK; ++ break; ++ ++ case EEPROM_CID_WHQL: ++ //Adapter->bInHctTest = TRUE;//do not supported ++ ++ //priv->bSupportTurboMode = FALSE; ++ //priv->bAutoTurboBy8186 = FALSE; ++ ++ //pMgntInfo->PowerSaveControl.bInactivePs = FALSE; ++ //pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE; ++ //pMgntInfo->PowerSaveControl.bLeisurePs = FALSE; ++ ++ break; ++ default: ++ // value from RegCustomerID ++ break; ++ } ++ ++ //Avoid the channel plan array overflow, by Bruce, 2007-08-27. ++ if(priv->ChannelPlan > CHANNEL_PLAN_LEN - 1) ++ priv->ChannelPlan = 0; //FCC ++ ++ switch(priv->CustomerID) ++ { ++ case RT_CID_DEFAULT: ++ #ifdef RTL8190P ++ priv->LedStrategy = HW_LED; ++ #else ++ #ifdef RTL8192E ++ priv->LedStrategy = SW_LED_MODE1; ++ #endif ++ #endif ++ break; ++ ++ case RT_CID_819x_CAMEO: ++ priv->LedStrategy = SW_LED_MODE2; ++ break; ++ ++ case RT_CID_819x_RUNTOP: ++ priv->LedStrategy = SW_LED_MODE3; ++ break; ++ ++ case RT_CID_819x_Netcore: ++ priv->LedStrategy = SW_LED_MODE4; ++ break; ++ ++ case RT_CID_Nettronix: ++ priv->LedStrategy = SW_LED_MODE5; ++ break; ++ ++ case RT_CID_PRONET: ++ priv->LedStrategy = SW_LED_MODE6; ++ break; ++ ++ case RT_CID_TOSHIBA: //Modify by Jacken 2008/01/31 ++ // Do nothing. ++ //break; ++ ++ default: ++ #ifdef RTL8190P ++ priv->LedStrategy = HW_LED; ++ #else ++ #ifdef RTL8192E ++ priv->LedStrategy = SW_LED_MODE1; ++ #endif ++ #endif ++ break; ++ } ++/* ++ //2008.06.03, for WOL ++ if( priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304) ++ priv->ieee80211->bSupportRemoteWakeUp = TRUE; ++ else ++ priv->ieee80211->bSupportRemoteWakeUp = FALSE; ++*/ ++ RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan); ++ RT_TRACE(COMP_INIT, "ChannelPlan = %d \n", priv->ChannelPlan); ++ RT_TRACE(COMP_INIT, "LedStrategy = %d \n", priv->LedStrategy); ++ RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n"); ++ ++ return ; ++} ++ ++ ++static short rtl8192_get_channel_map(struct net_device * dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#ifdef ENABLE_DOT11D ++ if(priv->ChannelPlan> COUNTRY_CODE_GLOBAL_DOMAIN){ ++ printk("rtl8180_init:Error channel plan! Set to default.\n"); ++ priv->ChannelPlan= 0; ++ } ++ RT_TRACE(COMP_INIT, "Channel plan is %d\n",priv->ChannelPlan); ++ ++ rtl819x_set_channel_map(priv->ChannelPlan, priv); ++#else ++ int ch,i; ++ //Set Default Channel Plan ++ if(!channels){ ++ DMESG("No channels, aborting"); ++ return -1; ++ } ++ ch=channels; ++ priv->ChannelPlan= 0;//hikaru ++ // set channels 1..14 allowed in given locale ++ for (i=1; i<=14; i++) { ++ (priv->ieee80211->channel_map)[i] = (u8)(ch & 0x01); ++ ch >>= 1; ++ } ++#endif ++ return 0; ++} ++ ++static short rtl8192_init(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ memset(&(priv->stats),0,sizeof(struct Stats)); ++ rtl8192_init_priv_variable(dev); ++ rtl8192_init_priv_lock(priv); ++ rtl8192_init_priv_task(dev); ++ rtl8192_get_eeprom_size(dev); ++ rtl8192_read_eeprom_info(dev); ++ rtl8192_get_channel_map(dev); ++ init_hal_dm(dev); ++ init_timer(&priv->watch_dog_timer); ++ priv->watch_dog_timer.data = (unsigned long)dev; ++ priv->watch_dog_timer.function = watch_dog_timer_callback; ++#if defined(IRQF_SHARED) ++ if(request_irq(dev->irq, (void*)rtl8192_interrupt, IRQF_SHARED, dev->name, dev)){ ++#else ++ if(request_irq(dev->irq, (void *)rtl8192_interrupt, SA_SHIRQ, dev->name, dev)){ ++#endif ++ printk("Error allocating IRQ %d",dev->irq); ++ return -1; ++ }else{ ++ priv->irq=dev->irq; ++ printk("IRQ %d",dev->irq); ++ } ++ if(rtl8192_pci_initdescring(dev)!=0){ ++ printk("Endopoints initialization failed"); ++ return -1; ++ } ++ ++ //rtl8192_rx_enable(dev); ++ //rtl8192_adapter_start(dev); ++ return 0; ++} ++ ++/****************************************************************************** ++ *function: This function actually only set RRSR, RATR and BW_OPMODE registers ++ * not to do all the hw config as its name says ++ * input: net_device dev ++ * output: none ++ * return: none ++ * notice: This part need to modified according to the rate set we filtered ++ * ****************************************************************************/ ++static void rtl8192_hwconfig(struct net_device* dev) ++{ ++ u32 regRATR = 0, regRRSR = 0; ++ u8 regBwOpMode = 0, regTmp = 0; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++// Set RRSR, RATR, and BW_OPMODE registers ++ // ++ switch(priv->ieee80211->mode) ++ { ++ case WIRELESS_MODE_B: ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK; ++ regRRSR = RATE_ALL_CCK; ++ break; ++ case WIRELESS_MODE_A: ++ regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_OFDM_AG; ++ regRRSR = RATE_ALL_OFDM_AG; ++ break; ++ case WIRELESS_MODE_G: ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ break; ++ case WIRELESS_MODE_AUTO: ++ case WIRELESS_MODE_N_24G: ++ // It support CCK rate by default. ++ // CCK rate will be filtered out only when associated AP does not support it. ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ break; ++ case WIRELESS_MODE_N_5G: ++ regBwOpMode = BW_OPMODE_5G; ++ regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; ++ regRRSR = RATE_ALL_OFDM_AG; ++ break; ++ } ++ ++ write_nic_byte(dev, BW_OPMODE, regBwOpMode); ++ { ++ u32 ratr_value = 0; ++ ratr_value = regRATR; ++ if (priv->rf_type == RF_1T2R) ++ { ++ ratr_value &= ~(RATE_ALL_OFDM_2SS); ++ } ++ write_nic_dword(dev, RATR0, ratr_value); ++ write_nic_byte(dev, UFWP, 1); ++ } ++ regTmp = read_nic_byte(dev, 0x313); ++ regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff); ++ write_nic_dword(dev, RRSR, regRRSR); ++ ++ // ++ // Set Retry Limit here ++ // ++ write_nic_word(dev, RETRY_LIMIT, ++ priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT | \ ++ priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT); ++ // Set Contention Window here ++ ++ // Set Tx AGC ++ ++ // Set Tx Antenna including Feedback control ++ ++ // Set Auto Rate fallback control ++ ++ ++} ++ ++ ++static RT_STATUS rtl8192_adapter_start(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++// struct ieee80211_device *ieee = priv->ieee80211; ++ u32 ulRegRead; ++ RT_STATUS rtStatus = RT_STATUS_SUCCESS; ++// static char szMACPHYRegFile[] = RTL819X_PHY_MACPHY_REG; ++// static char szMACPHYRegPGFile[] = RTL819X_PHY_MACPHY_REG_PG; ++ //u8 eRFPath; ++ u8 tmpvalue; ++#ifdef RTL8192E ++ u8 ICVersion,SwitchingRegulatorOutput; ++#endif ++ bool bfirmwareok = true; ++#ifdef RTL8190P ++ u8 ucRegRead; ++#endif ++ u32 tmpRegA, tmpRegC, TempCCk; ++ int i =0; ++// u32 dwRegRead = 0; ++ ++ RT_TRACE(COMP_INIT, "====>%s()\n", __FUNCTION__); ++ priv->being_init_adapter = true; ++ rtl8192_pci_resetdescring(dev); ++ // 2007/11/02 MH Before initalizing RF. We can not use FW to do RF-R/W. ++ priv->Rf_Mode = RF_OP_By_SW_3wire; ++#ifdef RTL8192E ++ //dPLL on ++ if(priv->ResetProgress == RESET_TYPE_NORESET) ++ { ++ write_nic_byte(dev, ANAPAR, 0x37); ++ // Accordign to designer's explain, LBUS active will never > 10ms. We delay 10ms ++ // Joseph increae the time to prevent firmware download fail ++ mdelay(500); ++ } ++#endif ++ //PlatformSleepUs(10000); ++ // For any kind of InitializeAdapter process, we shall use system now!! ++ priv->pFirmware->firmware_status = FW_STATUS_0_INIT; ++ ++ // Set to eRfoff in order not to count receive count. ++ if(priv->RegRfOff == TRUE) ++ priv->ieee80211->eRFPowerState = eRfOff; ++ ++ // ++ //3 //Config CPUReset Register ++ //3// ++ //3 Firmware Reset Or Not ++ ulRegRead = read_nic_dword(dev, CPU_GEN); ++ if(priv->pFirmware->firmware_status == FW_STATUS_0_INIT) ++ { //called from MPInitialized. do nothing ++ ulRegRead |= CPU_GEN_SYSTEM_RESET; ++ }else if(priv->pFirmware->firmware_status == FW_STATUS_5_READY) ++ ulRegRead |= CPU_GEN_FIRMWARE_RESET; // Called from MPReset ++ else ++ RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)\n", __FUNCTION__, priv->pFirmware->firmware_status); ++ ++#ifdef RTL8190P ++ //2008.06.03, for WOL 90 hw bug ++ ulRegRead &= (~(CPU_GEN_GPIO_UART)); ++#endif ++ ++ write_nic_dword(dev, CPU_GEN, ulRegRead); ++ //mdelay(100); ++ ++#ifdef RTL8192E ++ ++ //3// ++ //3 //Fix the issue of E-cut high temperature issue ++ //3// ++ // TODO: E cut only ++ ICVersion = read_nic_byte(dev, IC_VERRSION); ++ if(ICVersion >= 0x4) //E-cut only ++ { ++ // HW SD suggest that we should not wirte this register too often, so driver ++ // should readback this register. This register will be modified only when ++ // power on reset ++ SwitchingRegulatorOutput = read_nic_byte(dev, SWREGULATOR); ++ if(SwitchingRegulatorOutput != 0xb8) ++ { ++ write_nic_byte(dev, SWREGULATOR, 0xa8); ++ mdelay(1); ++ write_nic_byte(dev, SWREGULATOR, 0xb8); ++ } ++ } ++#endif ++ ++ ++ //3// ++ //3// Initialize BB before MAC ++ //3// ++ RT_TRACE(COMP_INIT, "BB Config Start!\n"); ++ rtStatus = rtl8192_BBConfig(dev); ++ if(rtStatus != RT_STATUS_SUCCESS) ++ { ++ RT_TRACE(COMP_ERR, "BB Config failed\n"); ++ return rtStatus; ++ } ++ RT_TRACE(COMP_INIT,"BB Config Finished!\n"); ++ ++ //3//Set Loopback mode or Normal mode ++ //3// ++ //2006.12.13 by emily. Note!We should not merge these two CPU_GEN register writings ++ // because setting of System_Reset bit reset MAC to default transmission mode. ++ //Loopback mode or not ++ priv->LoopbackMode = RTL819X_NO_LOOPBACK; ++ //priv->LoopbackMode = RTL819X_MAC_LOOPBACK; ++ if(priv->ResetProgress == RESET_TYPE_NORESET) ++ { ++ ulRegRead = read_nic_dword(dev, CPU_GEN); ++ if(priv->LoopbackMode == RTL819X_NO_LOOPBACK) ++ { ++ ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) | CPU_GEN_NO_LOOPBACK_SET); ++ } ++ else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK ) ++ { ++ ulRegRead |= CPU_CCK_LOOPBACK; ++ } ++ else ++ { ++ RT_TRACE(COMP_ERR,"Serious error: wrong loopback mode setting\n"); ++ } ++ ++ //2008.06.03, for WOL ++ //ulRegRead &= (~(CPU_GEN_GPIO_UART)); ++ write_nic_dword(dev, CPU_GEN, ulRegRead); ++ ++ // 2006.11.29. After reset cpu, we sholud wait for a second, otherwise, it may fail to write registers. Emily ++ udelay(500); ++ } ++ //3Set Hardware(Do nothing now) ++ rtl8192_hwconfig(dev); ++ //2======================================================= ++ // Common Setting for all of the FPGA platform. (part 1) ++ //2======================================================= ++ // If there is changes, please make sure it applies to all of the FPGA version ++ //3 Turn on Tx/Rx ++ write_nic_byte(dev, CMDR, CR_RE|CR_TE); ++ ++ //2Set Tx dma burst ++#ifdef RTL8190P ++ write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<dev_addr)[0]); ++ write_nic_word(dev, MAC4, ((u16*)(dev->dev_addr + 4))[0]); ++ //set RCR ++ write_nic_dword(dev, RCR, priv->ReceiveConfig); ++ ++ //3 Initialize Number of Reserved Pages in Firmware Queue ++ #ifdef TO_DO_LIST ++ if(priv->bInHctTest) ++ { ++ PlatformEFIOWrite4Byte(Adapter, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM << RSVD_FW_QUEUE_PAGE_BK_SHIFT |\ ++ NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM << RSVD_FW_QUEUE_PAGE_BE_SHIFT | \ ++ NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM << RSVD_FW_QUEUE_PAGE_VI_SHIFT | \ ++ NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM <RegWirelessMode); ++ if(priv->ResetProgress == RESET_TYPE_NORESET) ++ rtl8192_SetWirelessMode(dev, priv->ieee80211->mode); ++ //----------------------------------------------------------------------------- ++ // Set up security related. 070106, by rcnjko: ++ // 1. Clear all H/W keys. ++ // 2. Enable H/W encryption/decryption. ++ //----------------------------------------------------------------------------- ++ CamResetAllEntry(dev); ++ { ++ u8 SECR_value = 0x0; ++ SECR_value |= SCR_TxEncEnable; ++ SECR_value |= SCR_RxDecEnable; ++ SECR_value |= SCR_NoSKMC; ++ write_nic_byte(dev, SECR, SECR_value); ++ } ++ //3Beacon related ++ write_nic_word(dev, ATIMWND, 2); ++ write_nic_word(dev, BCN_INTERVAL, 100); ++ for (i=0; icard_8192_version > (u8) VERSION_8190_BD) { ++ rtl8192_phy_getTxPower(dev); ++ rtl8192_phy_setTxPower(dev, priv->chan); ++ } ++ ++ //if D or C cut ++ tmpvalue = read_nic_byte(dev, IC_VERRSION); ++ priv->IC_Cut = tmpvalue; ++ RT_TRACE(COMP_INIT, "priv->IC_Cut = 0x%x\n", priv->IC_Cut); ++ if(priv->IC_Cut >= IC_VersionCut_D) ++ { ++ //pHalData->bDcut = TRUE; ++ if(priv->IC_Cut == IC_VersionCut_D) ++ RT_TRACE(COMP_INIT, "D-cut\n"); ++ if(priv->IC_Cut == IC_VersionCut_E) ++ { ++ RT_TRACE(COMP_INIT, "E-cut\n"); ++ // HW SD suggest that we should not wirte this register too often, so driver ++ // should readback this register. This register will be modified only when ++ // power on reset ++ } ++ } ++ else ++ { ++ //pHalData->bDcut = FALSE; ++ RT_TRACE(COMP_INIT, "Before C-cut\n"); ++ } ++ ++#if 1 ++ //Firmware download ++ RT_TRACE(COMP_INIT, "Load Firmware!\n"); ++ bfirmwareok = init_firmware(dev); ++ if(bfirmwareok != true) { ++ rtStatus = RT_STATUS_FAILURE; ++ return rtStatus; ++ } ++ RT_TRACE(COMP_INIT, "Load Firmware finished!\n"); ++#endif ++ //RF config ++ if(priv->ResetProgress == RESET_TYPE_NORESET) ++ { ++ RT_TRACE(COMP_INIT, "RF Config Started!\n"); ++ rtStatus = rtl8192_phy_RFConfig(dev); ++ if(rtStatus != RT_STATUS_SUCCESS) ++ { ++ RT_TRACE(COMP_ERR, "RF Config failed\n"); ++ return rtStatus; ++ } ++ RT_TRACE(COMP_INIT, "RF Config Finished!\n"); ++ } ++ rtl8192_phy_updateInitGain(dev); ++ ++ /*---- Set CCK and OFDM Block "ON"----*/ ++ rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); ++ rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); ++ ++#ifdef RTL8192E ++ //Enable Led ++ write_nic_byte(dev, 0x87, 0x0); ++#endif ++#ifdef RTL8190P ++ //2008.06.03, for WOL ++ ucRegRead = read_nic_byte(dev, GPE); ++ ucRegRead |= BIT0; ++ write_nic_byte(dev, GPE, ucRegRead); ++ ++ ucRegRead = read_nic_byte(dev, GPO); ++ ucRegRead &= ~BIT0; ++ write_nic_byte(dev, GPO, ucRegRead); ++#endif ++ ++ //2======================================================= ++ // RF Power Save ++ //2======================================================= ++#ifdef ENABLE_IPS ++ ++{ ++ if(priv->RegRfOff == TRUE) ++ { // User disable RF via registry. ++ RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): Turn off RF for RegRfOff ----------\n",__FUNCTION__); ++ MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW); ++#if 0//cosa, ask SD3 willis and he doesn't know what is this for ++ // Those action will be discard in MgntActSet_RF_State because off the same state ++ for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); ++#endif ++ } ++ else if(priv->ieee80211->RfOffReason > RF_CHANGE_BY_PS) ++ { // H/W or S/W RF OFF before sleep. ++ RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): Turn off RF for RfOffReason(%d) ----------\n", __FUNCTION__,priv->ieee80211->RfOffReason); ++ MgntActSet_RF_State(dev, eRfOff, priv->ieee80211->RfOffReason); ++ } ++ else if(priv->ieee80211->RfOffReason >= RF_CHANGE_BY_IPS) ++ { // H/W or S/W RF OFF before sleep. ++ RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): Turn off RF for RfOffReason(%d) ----------\n", __FUNCTION__,priv->ieee80211->RfOffReason); ++ MgntActSet_RF_State(dev, eRfOff, priv->ieee80211->RfOffReason); ++ } ++ else ++ { ++ RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON \n",__FUNCTION__); ++ priv->ieee80211->eRFPowerState = eRfOn; ++ priv->ieee80211->RfOffReason = 0; ++ //DrvIFIndicateCurrentPhyStatus(Adapter); ++ // LED control ++ //Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_ON); ++ ++ // ++ // If inactive power mode is enabled, disable rf while in disconnected state. ++ // But we should still tell upper layer we are in rf on state. ++ // 2007.07.16, by shien chang. ++ // ++ //if(!Adapter->bInHctTest) ++ //IPSEnter(Adapter); ++ ++ } ++} ++#endif ++ if(1){ ++#ifdef RTL8192E ++ // We can force firmware to do RF-R/W ++ if(priv->ieee80211->FwRWRF) ++ priv->Rf_Mode = RF_OP_By_FW; ++ else ++ priv->Rf_Mode = RF_OP_By_SW_3wire; ++#else ++ priv->Rf_Mode = RF_OP_By_SW_3wire; ++#endif ++ } ++#ifdef RTL8190P ++ if(priv->ResetProgress == RESET_TYPE_NORESET) ++ { ++ dm_initialize_txpower_tracking(dev); ++ ++ tmpRegA= rtl8192_QueryBBReg(dev,rOFDM0_XATxIQImbalance,bMaskDWord); ++ tmpRegC= rtl8192_QueryBBReg(dev,rOFDM0_XCTxIQImbalance,bMaskDWord); ++ ++ if(priv->rf_type == RF_2T4R){ ++ for(i = 0; itxbbgain_table[i].txbbgain_value) ++ { ++ priv->rfa_txpowertrackingindex= (u8)i; ++ priv->rfa_txpowertrackingindex_real= (u8)i; ++ priv->rfa_txpowertracking_default = priv->rfa_txpowertrackingindex; ++ break; ++ } ++ } ++ } ++ for(i = 0; itxbbgain_table[i].txbbgain_value) ++ { ++ priv->rfc_txpowertrackingindex= (u8)i; ++ priv->rfc_txpowertrackingindex_real= (u8)i; ++ priv->rfc_txpowertracking_default = priv->rfc_txpowertrackingindex; ++ break; ++ } ++ } ++ TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2); ++ ++ for(i=0 ; icck_txbbgain_table[i].ccktxbb_valuearray[0]) ++ { ++ priv->CCKPresentAttentuation_20Mdefault =(u8) i; ++ break; ++ } ++ } ++ priv->CCKPresentAttentuation_40Mdefault = 0; ++ priv->CCKPresentAttentuation_difference = 0; ++ priv->CCKPresentAttentuation = priv->CCKPresentAttentuation_20Mdefault; ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_initial = %d\n", priv->rfa_txpowertrackingindex); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real__initial = %d\n", priv->rfa_txpowertrackingindex_real); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_initial = %d\n", priv->rfc_txpowertrackingindex); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real_initial = %d\n", priv->rfc_txpowertrackingindex_real); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference_initial = %d\n", priv->CCKPresentAttentuation_difference); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_initial = %d\n", priv->CCKPresentAttentuation); ++ } ++#else ++ #ifdef RTL8192E ++ if(priv->ResetProgress == RESET_TYPE_NORESET) ++ { ++ dm_initialize_txpower_tracking(dev); ++ ++ if(priv->IC_Cut >= IC_VersionCut_D) ++ { ++ tmpRegA= rtl8192_QueryBBReg(dev,rOFDM0_XATxIQImbalance,bMaskDWord); ++ tmpRegC= rtl8192_QueryBBReg(dev,rOFDM0_XCTxIQImbalance,bMaskDWord); ++ for(i = 0; itxbbgain_table[i].txbbgain_value) ++ { ++ priv->rfa_txpowertrackingindex= (u8)i; ++ priv->rfa_txpowertrackingindex_real= (u8)i; ++ priv->rfa_txpowertracking_default = priv->rfa_txpowertrackingindex; ++ break; ++ } ++ } ++ ++ TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2); ++ ++ for(i=0 ; icck_txbbgain_table[i].ccktxbb_valuearray[0]) ++ { ++ priv->CCKPresentAttentuation_20Mdefault =(u8) i; ++ break; ++ } ++ } ++ priv->CCKPresentAttentuation_40Mdefault = 0; ++ priv->CCKPresentAttentuation_difference = 0; ++ priv->CCKPresentAttentuation = priv->CCKPresentAttentuation_20Mdefault; ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_initial = %d\n", priv->rfa_txpowertrackingindex); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real__initial = %d\n", priv->rfa_txpowertrackingindex_real); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference_initial = %d\n", priv->CCKPresentAttentuation_difference); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_initial = %d\n", priv->CCKPresentAttentuation); ++ priv->btxpower_tracking = FALSE;//TEMPLY DISABLE ++ } ++ } ++ #endif ++#endif ++ rtl8192_irq_enable(dev); ++ priv->being_init_adapter = false; ++ return rtStatus; ++ ++} ++ ++void rtl8192_prepare_beacon(struct r8192_priv *priv) ++{ ++ struct sk_buff *skb; ++ //unsigned long flags; ++ cb_desc *tcb_desc; ++ ++ skb = ieee80211_get_beacon(priv->ieee80211); ++ tcb_desc = (cb_desc *)(skb->cb + 8); ++ //printk("===========> %s\n", __FUNCTION__); ++ //spin_lock_irqsave(&priv->tx_lock,flags); ++ /* prepare misc info for the beacon xmit */ ++ tcb_desc->queue_index = BEACON_QUEUE; ++ /* IBSS does not support HT yet, use 1M defautly */ ++ tcb_desc->data_rate = 2; ++ tcb_desc->RATRIndex = 7; ++ tcb_desc->bTxDisableRateFallBack = 1; ++ tcb_desc->bTxUseDriverAssingedRate = 1; ++ ++ skb_push(skb, priv->ieee80211->tx_headroom); ++ if(skb){ ++ rtl8192_tx(priv->ieee80211->dev,skb); ++ } ++ //spin_unlock_irqrestore (&priv->tx_lock, flags); ++} ++ ++#if 0 ++void rtl8192_beacon_tx_enable(struct net_device *dev) ++{ ++ struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); ++ ++ rtl8180_set_mode(dev,EPROM_CMD_CONFIG); ++#ifdef CONFIG_RTL8185B ++ priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_BQ);MgntQuery_MgntFrameTxRateMgntQuery_MgntFrameTxRate ++ write_nic_byte(dev,TPPollStop, priv->dma_poll_mask); ++#else ++ priv->dma_poll_mask &=~(1<dma_poll_mask); ++#endif ++ rtl8180_set_mode(dev,EPROM_CMD_NORMAL); ++} ++#endif ++ ++ ++/* this configures registers for beacon tx and enables it via ++ * rtl8192_beacon_tx_enable(). rtl8192_beacon_tx_disable() might ++ * be used to stop beacon transmission ++ */ ++void rtl8192_start_beacon(struct net_device *dev) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ struct ieee80211_network *net = &priv->ieee80211->current_network; ++ u16 BcnTimeCfg = 0; ++ u16 BcnCW = 6; ++ u16 BcnIFS = 0xf; ++ ++ DMESG("Enabling beacon TX"); ++ //rtl8192_prepare_beacon(dev); ++ rtl8192_irq_disable(dev); ++ //rtl8192_beacon_tx_enable(dev); ++ ++ /* ATIM window */ ++ write_nic_word(dev, ATIMWND, 2); ++ ++ /* Beacon interval (in unit of TU) */ ++ write_nic_word(dev, BCN_INTERVAL, net->beacon_interval); ++ ++ /* ++ * DrvErlyInt (in unit of TU). ++ * (Time to send interrupt to notify driver to c ++ * hange beacon content) ++ * */ ++ write_nic_word(dev, BCN_DRV_EARLY_INT, 10); ++ ++ /* ++ * BcnDMATIM(in unit of us). ++ * Indicates the time before TBTT to perform beacon queue DMA ++ * */ ++ write_nic_word(dev, BCN_DMATIME, 256); ++ ++ /* ++ * Force beacon frame transmission even after receiving ++ * beacon frame from other ad hoc STA ++ * */ ++ write_nic_byte(dev, BCN_ERR_THRESH, 100); ++ ++ /* Set CW and IFS */ ++ BcnTimeCfg |= BcnCW<ieee80211->stats; ++} ++#endif ++ ++ ++ ++static bool HalTxCheckStuck8190Pci(struct net_device *dev) ++{ ++ u16 RegTxCounter = read_nic_word(dev, 0x128); ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ bool bStuck = FALSE; ++ RT_TRACE(COMP_RESET,"%s():RegTxCounter is %d,TxCounter is %d\n",__FUNCTION__,RegTxCounter,priv->TxCounter); ++ if(priv->TxCounter==RegTxCounter) ++ bStuck = TRUE; ++ ++ priv->TxCounter = RegTxCounter; ++ ++ return bStuck; ++} ++ ++/* ++* ++* First added: 2006.11.19 by emily ++*/ ++static RESET_TYPE ++TxCheckStuck(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 QueueID; ++ ptx_ring head=NULL,tail=NULL,txring = NULL; ++ u8 ResetThreshold = NIC_SEND_HANG_THRESHOLD_POWERSAVE; ++ bool bCheckFwTxCnt = false; ++ //unsigned long flags; ++ ++ // ++ // Decide Stuch threshold according to current power save mode ++ // ++ //printk("++++++++++++>%s()\n",__FUNCTION__); ++ switch (priv->ieee80211->dot11PowerSaveMode) ++ { ++ // The threshold value may required to be adjusted . ++ case eActive: // Active/Continuous access. ++ ResetThreshold = NIC_SEND_HANG_THRESHOLD_NORMAL; ++ break; ++ case eMaxPs: // Max power save mode. ++ ResetThreshold = NIC_SEND_HANG_THRESHOLD_POWERSAVE; ++ break; ++ case eFastPs: // Fast power save mode. ++ ResetThreshold = NIC_SEND_HANG_THRESHOLD_POWERSAVE; ++ break; ++ } ++ ++ // ++ // Check whether specific tcb has been queued for a specific time ++ // ++ for(QueueID = 0; QueueID < MAX_TX_QUEUE; QueueID++) ++ { ++ ++ ++ if(QueueID == TXCMD_QUEUE) ++ continue; ++ ++ switch(QueueID) { ++ case MGNT_QUEUE: ++ tail=priv->txmapringtail; ++ head=priv->txmapringhead; ++ break; ++ ++ case BK_QUEUE: ++ tail=priv->txbkpringtail; ++ head=priv->txbkpringhead; ++ break; ++ ++ case BE_QUEUE: ++ tail=priv->txbepringtail; ++ head=priv->txbepringhead; ++ break; ++ ++ case VI_QUEUE: ++ tail=priv->txvipringtail; ++ head=priv->txvipringhead; ++ break; ++ ++ case VO_QUEUE: ++ tail=priv->txvopringtail; ++ head=priv->txvopringhead; ++ break; ++ ++ default: ++ tail=head=NULL; ++ break; ++ } ++ ++ if(tail == head) ++ continue; ++ else ++ { ++ txring = head; ++ if(txring == NULL) ++ { ++ RT_TRACE(COMP_ERR,"%s():txring is NULL , BUG!\n",__FUNCTION__); ++ continue; ++ } ++ txring->nStuckCount++; ++ #if 0 ++ if(txring->nStuckCount > ResetThreshold) ++ { ++ RT_TRACE( COMP_RESET, "<== TxCheckStuck()\n" ); ++ return RESET_TYPE_NORMAL; ++ } ++ #endif ++ bCheckFwTxCnt = TRUE; ++ } ++ } ++#if 1 ++ if(bCheckFwTxCnt) ++ { ++ if(HalTxCheckStuck8190Pci(dev)) ++ { ++ RT_TRACE(COMP_RESET, "TxCheckStuck(): Fw indicates no Tx condition! \n"); ++ return RESET_TYPE_SILENT; ++ } ++ } ++#endif ++ return RESET_TYPE_NORESET; ++} ++ ++ ++static bool HalRxCheckStuck8190Pci(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u16 RegRxCounter = read_nic_word(dev, 0x130); ++ bool bStuck = FALSE; ++ static u8 rx_chk_cnt = 0; ++ RT_TRACE(COMP_RESET,"%s(): RegRxCounter is %d,RxCounter is %d\n",__FUNCTION__,RegRxCounter,priv->RxCounter); ++ // If rssi is small, we should check rx for long time because of bad rx. ++ // or maybe it will continuous silent reset every 2 seconds. ++ rx_chk_cnt++; ++ if(priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) ++ { ++ rx_chk_cnt = 0; //high rssi, check rx stuck right now. ++ } ++ else if(priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High+5) && ++ ((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_40M) || ++ (priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_20M)) ) ++ ++ { ++ if(rx_chk_cnt < 2) ++ { ++ return bStuck; ++ } ++ else ++ { ++ rx_chk_cnt = 0; ++ } ++ } ++ else if(((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdbCurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdbundecorated_smoothed_pwdb >= VeryLowRSSI) ++ { ++ if(rx_chk_cnt < 4) ++ { ++ //DbgPrint("RSSI < %d && RSSI >= %d, no check this time \n", RateAdaptiveTH_Low, VeryLowRSSI); ++ return bStuck; ++ } ++ else ++ { ++ rx_chk_cnt = 0; ++ //DbgPrint("RSSI < %d && RSSI >= %d, check this time \n", RateAdaptiveTH_Low, VeryLowRSSI); ++ } ++ } ++ else ++ { ++ if(rx_chk_cnt < 8) ++ { ++ //DbgPrint("RSSI <= %d, no check this time \n", VeryLowRSSI); ++ return bStuck; ++ } ++ else ++ { ++ rx_chk_cnt = 0; ++ //DbgPrint("RSSI <= %d, check this time \n", VeryLowRSSI); ++ } ++ } ++#if 0 ++ if (rx_chk_cnt < 2) ++ return bStuck; ++ else ++ rx_chk_cnt = 0; ++#endif ++ if(priv->RxCounter==RegRxCounter) ++ bStuck = TRUE; ++ ++ priv->RxCounter = RegRxCounter; ++ ++ return bStuck; ++} ++ ++static RESET_TYPE RxCheckStuck(struct net_device *dev) ++{ ++ ++ if(HalRxCheckStuck8190Pci(dev)) ++ { ++ RT_TRACE(COMP_RESET, "RxStuck Condition\n"); ++ return RESET_TYPE_SILENT; ++ } ++ ++ return RESET_TYPE_NORESET; ++} ++ ++static RESET_TYPE ++rtl819x_ifcheck_resetornot(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ RESET_TYPE TxResetType = RESET_TYPE_NORESET; ++ RESET_TYPE RxResetType = RESET_TYPE_NORESET; ++ RT_RF_POWER_STATE rfState; ++ ++ rfState = priv->ieee80211->eRFPowerState; ++ ++ TxResetType = TxCheckStuck(dev); ++#if 1 ++ if( rfState != eRfOff && ++ /*ADAPTER_TEST_STATUS_FLAG(Adapter, ADAPTER_STATUS_FW_DOWNLOAD_FAILURE)) &&*/ ++ (priv->ieee80211->iw_mode != IW_MODE_ADHOC)) ++ { ++ // If driver is in the status of firmware download failure , driver skips RF initialization and RF is ++ // in turned off state. Driver should check whether Rx stuck and do silent reset. And ++ // if driver is in firmware download failure status, driver should initialize RF in the following ++ // silent reset procedure Emily, 2008.01.21 ++ ++ // Driver should not check RX stuck in IBSS mode because it is required to ++ // set Check BSSID in order to send beacon, however, if check BSSID is ++ // set, STA cannot hear any packet a all. Emily, 2008.04.12 ++ RxResetType = RxCheckStuck(dev); ++ } ++#endif ++ ++ RT_TRACE(COMP_RESET,"%s(): TxResetType is %d, RxResetType is %d\n",__FUNCTION__,TxResetType,RxResetType); ++ if(TxResetType==RESET_TYPE_NORMAL || RxResetType==RESET_TYPE_NORMAL) ++ return RESET_TYPE_NORMAL; ++ else if(TxResetType==RESET_TYPE_SILENT || RxResetType==RESET_TYPE_SILENT) ++ return RESET_TYPE_SILENT; ++ else ++ return RESET_TYPE_NORESET; ++ ++} ++ ++ ++static void CamRestoreAllEntry(struct net_device *dev) ++{ ++ u8 EntryId = 0; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8* MacAddr = priv->ieee80211->current_network.bssid; ++ ++ static u8 CAM_CONST_ADDR[4][6] = { ++ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, ++ {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, ++ {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, ++ {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}}; ++ static u8 CAM_CONST_BROAD[] = ++ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ RT_TRACE(COMP_SEC, "CamRestoreAllEntry: \n"); ++ ++ ++ if ((priv->ieee80211->pairwise_key_type == KEY_TYPE_WEP40)|| ++ (priv->ieee80211->pairwise_key_type == KEY_TYPE_WEP104)) ++ { ++ ++ for(EntryId=0; EntryId<4; EntryId++) ++ { ++ { ++ MacAddr = CAM_CONST_ADDR[EntryId]; ++ setKey(dev, ++ EntryId , ++ EntryId, ++ priv->ieee80211->pairwise_key_type, ++ MacAddr, ++ 0, ++ NULL); ++ } ++ } ++ ++ } ++ else if(priv->ieee80211->pairwise_key_type == KEY_TYPE_TKIP) ++ { ++ ++ { ++ if(priv->ieee80211->iw_mode == IW_MODE_ADHOC) ++ setKey(dev, ++ 4, ++ 0, ++ priv->ieee80211->pairwise_key_type, ++ (u8*)dev->dev_addr, ++ 0, ++ NULL); ++ else ++ setKey(dev, ++ 4, ++ 0, ++ priv->ieee80211->pairwise_key_type, ++ MacAddr, ++ 0, ++ NULL); ++ } ++ } ++ else if(priv->ieee80211->pairwise_key_type == KEY_TYPE_CCMP) ++ { ++ ++ { ++ if(priv->ieee80211->iw_mode == IW_MODE_ADHOC) ++ setKey(dev, ++ 4, ++ 0, ++ priv->ieee80211->pairwise_key_type, ++ (u8*)dev->dev_addr, ++ 0, ++ NULL); ++ else ++ setKey(dev, ++ 4, ++ 0, ++ priv->ieee80211->pairwise_key_type, ++ MacAddr, ++ 0, ++ NULL); ++ } ++ } ++ ++ ++ ++ if(priv->ieee80211->group_key_type == KEY_TYPE_TKIP) ++ { ++ MacAddr = CAM_CONST_BROAD; ++ for(EntryId=1 ; EntryId<4 ; EntryId++) ++ { ++ { ++ setKey(dev, ++ EntryId, ++ EntryId, ++ priv->ieee80211->group_key_type, ++ MacAddr, ++ 0, ++ NULL); ++ } ++ } ++ if(priv->ieee80211->iw_mode == IW_MODE_ADHOC) ++ setKey(dev, ++ 0, ++ 0, ++ priv->ieee80211->group_key_type, ++ CAM_CONST_ADDR[0], ++ 0, ++ NULL); ++ } ++ else if(priv->ieee80211->group_key_type == KEY_TYPE_CCMP) ++ { ++ MacAddr = CAM_CONST_BROAD; ++ for(EntryId=1; EntryId<4 ; EntryId++) ++ { ++ { ++ setKey(dev, ++ EntryId , ++ EntryId, ++ priv->ieee80211->group_key_type, ++ MacAddr, ++ 0, ++ NULL); ++ } ++ } ++ ++ if(priv->ieee80211->iw_mode == IW_MODE_ADHOC) ++ setKey(dev, ++ 0 , ++ 0, ++ priv->ieee80211->group_key_type, ++ CAM_CONST_ADDR[0], ++ 0, ++ NULL); ++ } ++} ++ ++void rtl8192_cancel_deferred_work(struct r8192_priv* priv); ++int _rtl8192_up(struct net_device *dev); ++ ++/* ++ * This function is used to fix Tx/Rx stop bug temporarily. ++ * This function will do "system reset" to NIC when Tx or Rx is stuck. ++ * The method checking Tx/Rx stuck of this function is supported by FW, ++ * which reports Tx and Rx counter to register 0x128 and 0x130. ++ * */ ++static void rtl819x_ifsilentreset(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 reset_times = 0; ++ int reset_status = 0; ++ struct ieee80211_device *ieee = priv->ieee80211; ++ ++ ++ // 2007.07.20. If we need to check CCK stop, please uncomment this line. ++ //bStuck = Adapter->HalFunc.CheckHWStopHandler(Adapter); ++ ++ if(priv->ResetProgress==RESET_TYPE_NORESET) ++ { ++RESET_START: ++ ++ RT_TRACE(COMP_RESET,"=========>Reset progress!! \n"); ++ ++ // Set the variable for reset. ++ priv->ResetProgress = RESET_TYPE_SILENT; ++// rtl8192_close(dev); ++#if 1 ++ down(&priv->wx_sem); ++ if(priv->up == 0) ++ { ++ RT_TRACE(COMP_ERR,"%s():the driver is not up! return\n",__FUNCTION__); ++ up(&priv->wx_sem); ++ return ; ++ } ++ priv->up = 0; ++ RT_TRACE(COMP_RESET,"%s():======>start to down the driver\n",__FUNCTION__); ++ if(!netif_queue_stopped(dev)) ++ netif_stop_queue(dev); ++ ++ dm_backup_dynamic_mechanism_state(dev); ++ ++ rtl8192_irq_disable(dev); ++ rtl8192_cancel_deferred_work(priv); ++ deinit_hal_dm(dev); ++ del_timer_sync(&priv->watch_dog_timer); ++ ieee->sync_scan_hurryup = 1; ++ if(ieee->state == IEEE80211_LINKED) ++ { ++ down(&ieee->wx_sem); ++ printk("ieee->state is IEEE80211_LINKED\n"); ++ ieee80211_stop_send_beacons(priv->ieee80211); ++ del_timer_sync(&ieee->associate_timer); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ cancel_delayed_work(&ieee->associate_retry_wq); ++#endif ++ ieee80211_stop_scan(ieee); ++ netif_carrier_off(dev); ++ up(&ieee->wx_sem); ++ } ++ else{ ++ printk("ieee->state is NOT LINKED\n"); ++ ieee80211_softmac_stop_protocol(priv->ieee80211); ++ } ++ rtl8192_rtx_disable(dev); ++ up(&priv->wx_sem); ++ RT_TRACE(COMP_RESET,"%s():<==========down process is finished\n",__FUNCTION__); ++ RT_TRACE(COMP_RESET,"%s():===========>start to up the driver\n",__FUNCTION__); ++ reset_status = _rtl8192_up(dev); ++ ++ RT_TRACE(COMP_RESET,"%s():<===========up process is finished\n",__FUNCTION__); ++ if(reset_status == -1) ++ { ++ if(reset_times < 3) ++ { ++ reset_times++; ++ goto RESET_START; ++ } ++ else ++ { ++ RT_TRACE(COMP_ERR," ERR!!! %s(): Reset Failed!!\n",__FUNCTION__); ++ } ++ } ++#endif ++ ieee->is_silent_reset = 1; ++#if 1 ++ EnableHWSecurityConfig8192(dev); ++#if 1 ++ if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_INFRA) ++ { ++ ieee->set_chan(ieee->dev, ieee->current_network.channel); ++ ++#if 1 ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ queue_work(ieee->wq, &ieee->associate_complete_wq); ++#else ++ schedule_task(&ieee->associate_complete_wq); ++#endif ++#endif ++ ++ } ++ else if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_ADHOC) ++ { ++ ieee->set_chan(ieee->dev, ieee->current_network.channel); ++ ieee->link_change(ieee->dev); ++ ++ // notify_wx_assoc_event(ieee); ++ ++ ieee80211_start_send_beacons(ieee); ++ ++ if (ieee->data_hard_resume) ++ ieee->data_hard_resume(ieee->dev); ++ netif_carrier_on(ieee->dev); ++ } ++#endif ++ ++ CamRestoreAllEntry(dev); ++ ++ // Restore the previous setting for all dynamic mechanism ++ dm_restore_dynamic_mechanism_state(dev); ++ ++ priv->ResetProgress = RESET_TYPE_NORESET; ++ priv->reset_count++; ++ ++ priv->bForcedSilentReset =false; ++ priv->bResetInProgress = false; ++ ++ // For test --> force write UFWP. ++ write_nic_byte(dev, UFWP, 1); ++ RT_TRACE(COMP_RESET, "Reset finished!! ====>[%d]\n", priv->reset_count); ++#endif ++ } ++} ++ ++#ifdef ENABLE_IPS ++void InactivePsWorkItemCallback(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl)); ++ //u8 index = 0; ++ ++ RT_TRACE(COMP_POWER, "InactivePsWorkItemCallback() ---------> \n"); ++ // ++ // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem ++ // is really scheduled. ++ // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the ++ // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing ++ // blocks the IPS procedure of switching RF. ++ // By Bruce, 2007-12-25. ++ // ++ pPSC->bSwRfProcessing = TRUE; ++ ++ RT_TRACE(COMP_RF, "InactivePsWorkItemCallback(): Set RF to %s.\n", \ ++ pPSC->eInactivePowerState == eRfOff?"OFF":"ON"); ++ ++ ++ MgntActSet_RF_State(dev, pPSC->eInactivePowerState, RF_CHANGE_BY_IPS); ++ ++ // ++ // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20. ++ // ++#if 0 ++ if(pPSC->eInactivePowerState == eRfOn) ++ CamRestoreAllEntry(dev); ++#endif ++ pPSC->bSwRfProcessing = FALSE; ++ RT_TRACE(COMP_POWER, "InactivePsWorkItemCallback() <--------- \n"); ++} ++ ++// ++// Description: ++// Enter the inactive power save mode. RF will be off ++// 2007.08.17, by shien chang. ++// ++void ++IPSEnter(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl)); ++ RT_RF_POWER_STATE rtState; ++ ++ if (pPSC->bInactivePs) ++ { ++ rtState = priv->ieee80211->eRFPowerState; ++ // ++ // Added by Bruce, 2007-12-25. ++ // Do not enter IPS in the following conditions: ++ // (1) RF is already OFF or Sleep ++ // (2) bSwRfProcessing (indicates the IPS is still under going) ++ // (3) Connectted (only disconnected can trigger IPS) ++ // (4) IBSS (send Beacon) ++ // (5) AP mode (send Beacon) ++ // ++ if (rtState == eRfOn && !pPSC->bSwRfProcessing ++ && (priv->ieee80211->state != IEEE80211_LINKED) ) ++ { ++ RT_TRACE(COMP_RF,"IPSEnter(): Turn off RF.\n"); ++ pPSC->eInactivePowerState = eRfOff; ++// queue_work(priv->priv_wq,&(pPSC->InactivePsWorkItem)); ++ InactivePsWorkItemCallback(dev); ++ } ++ } ++} ++ ++// ++// Description: ++// Leave the inactive power save mode, RF will be on. ++// 2007.08.17, by shien chang. ++// ++void ++IPSLeave(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl)); ++ RT_RF_POWER_STATE rtState; ++ ++ if (pPSC->bInactivePs) ++ { ++ rtState = priv->ieee80211->eRFPowerState; ++ if (rtState != eRfOn && !pPSC->bSwRfProcessing && priv->ieee80211->RfOffReason <= RF_CHANGE_BY_IPS) ++ { ++ RT_TRACE(COMP_POWER, "IPSLeave(): Turn on RF.\n"); ++ pPSC->eInactivePowerState = eRfOn; ++// queue_work(priv->priv_wq,&(pPSC->InactivePsWorkItem)); ++ InactivePsWorkItemCallback(dev); ++ } ++ } ++} ++#endif ++ ++static void rtl819x_update_rxcounts( ++ struct r8192_priv *priv, ++ u32* TotalRxBcnNum, ++ u32* TotalRxDataNum ++) ++{ ++ u16 SlotIndex; ++ u8 i; ++ ++ *TotalRxBcnNum = 0; ++ *TotalRxDataNum = 0; ++ ++ SlotIndex = (priv->ieee80211->LinkDetectInfo.SlotIndex++)%(priv->ieee80211->LinkDetectInfo.SlotNum); ++ priv->ieee80211->LinkDetectInfo.RxBcnNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvBcnInPeriod; ++ priv->ieee80211->LinkDetectInfo.RxDataNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvDataInPeriod; ++ for( i=0; iieee80211->LinkDetectInfo.SlotNum; i++ ){ ++ *TotalRxBcnNum += priv->ieee80211->LinkDetectInfo.RxBcnNum[i]; ++ *TotalRxDataNum += priv->ieee80211->LinkDetectInfo.RxDataNum[i]; ++ } ++} ++ ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void rtl819x_watchdog_wqcallback(struct work_struct *work) ++{ ++ struct delayed_work *dwork = container_of(work,struct delayed_work,work); ++ struct r8192_priv *priv = container_of(dwork,struct r8192_priv,watch_dog_wq); ++ struct net_device *dev = priv->ieee80211->dev; ++#else ++extern void rtl819x_watchdog_wqcallback(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#endif ++ struct ieee80211_device* ieee = priv->ieee80211; ++ RESET_TYPE ResetType = RESET_TYPE_NORESET; ++ static u8 check_reset_cnt=0; ++ unsigned long flags; ++ bool bBusyTraffic = false; ++ static u8 last_time = 0; ++ if(!priv->up) ++ return; ++ hal_dm_watchdog(dev); ++#ifdef ENABLE_IPS ++// printk("watch_dog ENABLE_IPS\n"); ++ if(ieee->actscanning == false){ ++ if((ieee->iw_mode != IW_MODE_ADHOC) && (ieee->state == IEEE80211_NOLINK) && (ieee->beinretry == false) && (ieee->eRFPowerState == eRfOn) && !ieee->is_set_key){ ++ if(ieee->PowerSaveControl.ReturnPoint == IPS_CALLBACK_NONE){ ++ printk("====================>haha:IPSEnter()\n"); ++ IPSEnter(dev); ++ //ieee80211_stop_scan(priv->ieee80211); ++ } ++ } ++ } ++#endif ++ {//to get busy traffic condition ++ if(ieee->state == IEEE80211_LINKED) ++ { ++ if( ieee->LinkDetectInfo.NumRxOkInPeriod> 666 || ++ ieee->LinkDetectInfo.NumTxOkInPeriod> 666 ) { ++ bBusyTraffic = true; ++ } ++ ++ } ++ ieee->LinkDetectInfo.NumRxOkInPeriod = 0; ++ ieee->LinkDetectInfo.NumTxOkInPeriod = 0; ++ ieee->LinkDetectInfo.bBusyTraffic = bBusyTraffic; ++ } ++ ++ ++ //added by amy for AP roaming ++ if (1) ++ { ++ if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_INFRA) ++ { ++ u32 TotalRxBcnNum = 0; ++ u32 TotalRxDataNum = 0; ++ ++ rtl819x_update_rxcounts(priv, &TotalRxBcnNum, &TotalRxDataNum); ++ if((TotalRxBcnNum+TotalRxDataNum) == 0) ++ { ++ if( ieee->eRFPowerState == eRfOff) ++ RT_TRACE(COMP_ERR,"========>%s()\n",__FUNCTION__); ++ printk("===>%s(): AP is power off,connect another one\n",__FUNCTION__); ++ // Dot11d_Reset(dev); ++ ieee->state = IEEE80211_ASSOCIATING; ++ notify_wx_assoc_event(priv->ieee80211); ++ RemovePeerTS(priv->ieee80211,priv->ieee80211->current_network.bssid); ++ ieee->is_roaming = true; ++ ieee->is_set_key = false; ++ ieee->link_change(dev); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ queue_work(ieee->wq, &ieee->associate_procedure_wq); ++#else ++ schedule_task(&ieee->associate_procedure_wq); ++#endif ++ } ++ } ++ ieee->LinkDetectInfo.NumRecvBcnInPeriod=0; ++ ieee->LinkDetectInfo.NumRecvDataInPeriod=0; ++ ++ } ++ //check if reset the driver ++ spin_lock_irqsave(&priv->tx_lock,flags); ++ if(check_reset_cnt++ >= 3 && !ieee->is_roaming && (last_time != 1)) ++ { ++ ResetType = rtl819x_ifcheck_resetornot(dev); ++ check_reset_cnt = 3; ++ //DbgPrint("Start to check silent reset\n"); ++ } ++ spin_unlock_irqrestore(&priv->tx_lock,flags); ++ if(!priv->bDisableNormalResetCheck && ResetType == RESET_TYPE_NORMAL) ++ { ++ priv->ResetProgress = RESET_TYPE_NORMAL; ++ RT_TRACE(COMP_RESET,"%s(): NOMAL RESET\n",__FUNCTION__); ++ return; ++ } ++ /* disable silent reset temply 2008.9.11*/ ++#if 1 ++ if( ((priv->force_reset) || (!priv->bDisableNormalResetCheck && ResetType==RESET_TYPE_SILENT))) // This is control by OID set in Pomelo ++ { ++ last_time = 1; ++ rtl819x_ifsilentreset(dev); ++ } ++ else ++ last_time = 0; ++#endif ++ priv->force_reset = false; ++ priv->bForcedSilentReset = false; ++ priv->bResetInProgress = false; ++ RT_TRACE(COMP_TRACE, " <==RtUsbCheckForHangWorkItemCallback()\n"); ++ ++} ++ ++void watch_dog_timer_callback(unsigned long data) ++{ ++ struct r8192_priv *priv = ieee80211_priv((struct net_device *) data); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ queue_delayed_work(priv->priv_wq,&priv->watch_dog_wq,0); ++#else ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++ schedule_task(&priv->watch_dog_wq); ++#else ++ queue_work(priv->priv_wq,&priv->watch_dog_wq); ++#endif ++#endif ++ mod_timer(&priv->watch_dog_timer, jiffies + MSECS(IEEE80211_WATCH_DOG_TIME)); ++ ++} ++int _rtl8192_up(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ //int i; ++ RT_STATUS init_status = RT_STATUS_SUCCESS; ++ priv->up=1; ++ priv->ieee80211->ieee_up=1; ++ RT_TRACE(COMP_INIT, "Bringing up iface"); ++ ++ init_status = rtl8192_adapter_start(dev); ++ if(init_status != RT_STATUS_SUCCESS) ++ { ++ RT_TRACE(COMP_ERR,"ERR!!! %s(): initialization is failed!\n",__FUNCTION__); ++ return -1; ++ } ++ RT_TRACE(COMP_INIT, "start adapter finished\n"); ++#ifdef RTL8192E ++ if(priv->ieee80211->eRFPowerState!=eRfOn) ++ MgntActSet_RF_State(dev, eRfOn, priv->ieee80211->RfOffReason); ++#endif ++ if(priv->ieee80211->state != IEEE80211_LINKED) ++ ieee80211_softmac_start_protocol(priv->ieee80211); ++ ieee80211_reset_queue(priv->ieee80211); ++ watch_dog_timer_callback((unsigned long) dev); ++ if(!netif_queue_stopped(dev)) ++ netif_start_queue(dev); ++ else ++ netif_wake_queue(dev); ++ ++ return 0; ++} ++ ++ ++static int rtl8192_open(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ int ret; ++ ++ down(&priv->wx_sem); ++ ret = rtl8192_up(dev); ++ up(&priv->wx_sem); ++ return ret; ++ ++} ++ ++ ++int rtl8192_up(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ if (priv->up == 1) return -1; ++ ++ return _rtl8192_up(dev); ++} ++ ++ ++static int rtl8192_close(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ int ret; ++ ++ down(&priv->wx_sem); ++ ++ ret = rtl8192_down(dev); ++ ++ up(&priv->wx_sem); ++ ++ return ret; ++ ++} ++ ++int rtl8192_down(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++// int i; ++#if 0 ++ u8 ucRegRead; ++ u32 ulRegRead; ++#endif ++ if (priv->up == 0) return -1; ++ ++ priv->up=0; ++ priv->ieee80211->ieee_up = 0; ++ RT_TRACE(COMP_DOWN, "==========>%s()\n", __FUNCTION__); ++/* FIXME */ ++ if (!netif_queue_stopped(dev)) ++ netif_stop_queue(dev); ++ ++ rtl8192_irq_disable(dev); ++#if 0 ++ if(!priv->ieee80211->bSupportRemoteWakeUp) { ++ MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT); ++ // 2006.11.30. System reset bit ++ ulRegRead = read_nic_dword(dev, CPU_GEN); ++ ulRegRead|=CPU_GEN_SYSTEM_RESET; ++ write_nic_dword(dev, CPU_GEN, ulRegRead); ++ } else { ++ //2008.06.03 for WOL ++ write_nic_dword(dev, WFCRC0, 0xffffffff); ++ write_nic_dword(dev, WFCRC1, 0xffffffff); ++ write_nic_dword(dev, WFCRC2, 0xffffffff); ++#ifdef RTL8190P ++ //GPIO 0 = TRUE ++ ucRegRead = read_nic_byte(dev, GPO); ++ ucRegRead |= BIT0; ++ write_nic_byte(dev, GPO, ucRegRead); ++#endif ++ //Write PMR register ++ write_nic_byte(dev, PMR, 0x5); ++ //Disable tx, enanble rx ++ write_nic_byte(dev, MacBlkCtrl, 0xa); ++ } ++#endif ++// flush_scheduled_work(); ++ rtl8192_cancel_deferred_work(priv); ++ deinit_hal_dm(dev); ++ del_timer_sync(&priv->watch_dog_timer); ++ ++ ieee80211_softmac_stop_protocol(priv->ieee80211); ++#ifdef ENABLE_IPS ++ MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT); ++#endif ++ rtl8192_rtx_disable(dev); ++ memset(&priv->ieee80211->current_network, 0 , offsetof(struct ieee80211_network, list)); ++ ++ RT_TRACE(COMP_DOWN, "<==========%s()\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++ ++void rtl8192_commit(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ if (priv->up == 0) return ; ++ ++ ++ ieee80211_softmac_stop_protocol(priv->ieee80211); ++ ++ rtl8192_irq_disable(dev); ++ rtl8192_rtx_disable(dev); ++ _rtl8192_up(dev); ++} ++ ++/* ++void rtl8192_restart(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++*/ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void rtl8192_restart(struct work_struct *work) ++{ ++ struct r8192_priv *priv = container_of(work, struct r8192_priv, reset_wq); ++ struct net_device *dev = priv->ieee80211->dev; ++#else ++void rtl8192_restart(struct net_device *dev) ++{ ++ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#endif ++ ++ down(&priv->wx_sem); ++ ++ rtl8192_commit(dev); ++ ++ up(&priv->wx_sem); ++} ++ ++static void r8192_set_multicast(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ short promisc; ++ ++ //down(&priv->wx_sem); ++ ++ /* FIXME FIXME */ ++ ++ promisc = (dev->flags & IFF_PROMISC) ? 1:0; ++ ++ if (promisc != priv->promisc) { ++ ; ++ // rtl8192_commit(dev); ++ } ++ ++ priv->promisc = promisc; ++ ++ //schedule_work(&priv->reset_wq); ++ //up(&priv->wx_sem); ++} ++ ++ ++static int r8192_set_mac_adr(struct net_device *dev, void *mac) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ struct sockaddr *addr = mac; ++ ++ down(&priv->wx_sem); ++ ++ memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ schedule_work(&priv->reset_wq); ++#else ++ schedule_task(&priv->reset_wq); ++#endif ++ up(&priv->wx_sem); ++ ++ return 0; ++} ++ ++/* based on ipw2200 driver */ ++static int rtl8192_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ struct iwreq *wrq = (struct iwreq *)rq; ++ int ret=-1; ++ struct ieee80211_device *ieee = priv->ieee80211; ++ u32 key[4]; ++ u8 broadcast_addr[6] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++ struct iw_point *p = &wrq->u.data; ++ struct ieee_param *ipw = NULL;//(struct ieee_param *)wrq->u.data.pointer; ++ ++ down(&priv->wx_sem); ++ ++ ++ if (p->length < sizeof(struct ieee_param) || !p->pointer){ ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ ipw = (struct ieee_param *)kmalloc(p->length, GFP_KERNEL); ++ if (ipw == NULL){ ++ ret = -ENOMEM; ++ goto out; ++ } ++ if (copy_from_user(ipw, p->pointer, p->length)) { ++ kfree(ipw); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ switch (cmd) { ++ case RTL_IOCTL_WPA_SUPPLICANT: ++ //parse here for HW security ++ if (ipw->cmd == IEEE_CMD_SET_ENCRYPTION) ++ { ++ if (ipw->u.crypt.set_tx) ++ { ++ if (strcmp(ipw->u.crypt.alg, "CCMP") == 0) ++ ieee->pairwise_key_type = KEY_TYPE_CCMP; ++ else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0) ++ ieee->pairwise_key_type = KEY_TYPE_TKIP; ++ else if (strcmp(ipw->u.crypt.alg, "WEP") == 0) ++ { ++ if (ipw->u.crypt.key_len == 13) ++ ieee->pairwise_key_type = KEY_TYPE_WEP104; ++ else if (ipw->u.crypt.key_len == 5) ++ ieee->pairwise_key_type = KEY_TYPE_WEP40; ++ } ++ else ++ ieee->pairwise_key_type = KEY_TYPE_NA; ++ ++ if (ieee->pairwise_key_type) ++ { ++ memcpy((u8*)key, ipw->u.crypt.key, 16); ++ EnableHWSecurityConfig8192(dev); ++ //we fill both index entry and 4th entry for pairwise key as in IPW interface, adhoc will only get here, so we need index entry for its default key serching! ++ //added by WB. ++ setKey(dev, 4, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key); ++ if (ieee->auth_mode != 2) //LEAP WEP will never set this. ++ setKey(dev, ipw->u.crypt.idx, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key); ++ } ++ if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) && ieee->pHTInfo->bCurrentHTSupport){ ++ write_nic_byte(dev, 0x173, 1); //fix aes bug ++ } ++ ++ } ++ else //if (ipw->u.crypt.idx) //group key use idx > 0 ++ { ++ memcpy((u8*)key, ipw->u.crypt.key, 16); ++ if (strcmp(ipw->u.crypt.alg, "CCMP") == 0) ++ ieee->group_key_type= KEY_TYPE_CCMP; ++ else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0) ++ ieee->group_key_type = KEY_TYPE_TKIP; ++ else if (strcmp(ipw->u.crypt.alg, "WEP") == 0) ++ { ++ if (ipw->u.crypt.key_len == 13) ++ ieee->group_key_type = KEY_TYPE_WEP104; ++ else if (ipw->u.crypt.key_len == 5) ++ ieee->group_key_type = KEY_TYPE_WEP40; ++ } ++ else ++ ieee->group_key_type = KEY_TYPE_NA; ++ ++ if (ieee->group_key_type) ++ { ++ setKey( dev, ++ ipw->u.crypt.idx, ++ ipw->u.crypt.idx, //KeyIndex ++ ieee->group_key_type, //KeyType ++ broadcast_addr, //MacAddr ++ 0, //DefaultKey ++ key); //KeyContent ++ } ++ } ++ } ++#ifdef JOHN_DEBUG ++ //john's test 0711 ++ { ++ int i; ++ printk("@@ wrq->u pointer = "); ++ for(i=0;iu.data.length;i++){ ++ if(i%10==0) printk("\n"); ++ printk( "%8x|", ((u32*)wrq->u.data.pointer)[i] ); ++ } ++ printk("\n"); ++ } ++#endif /*JOHN_DEBUG*/ ++ ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data); ++ break; ++ ++ default: ++ ret = -EOPNOTSUPP; ++ break; ++ } ++ ++ kfree(ipw); ++out: ++ up(&priv->wx_sem); ++ ++ return ret; ++} ++ ++static u8 HwRateToMRate90(bool bIsHT, u8 rate) ++{ ++ u8 ret_rate = 0x02; ++ ++ if(!bIsHT) { ++ switch(rate) { ++ case DESC90_RATE1M: ret_rate = MGN_1M; break; ++ case DESC90_RATE2M: ret_rate = MGN_2M; break; ++ case DESC90_RATE5_5M: ret_rate = MGN_5_5M; break; ++ case DESC90_RATE11M: ret_rate = MGN_11M; break; ++ case DESC90_RATE6M: ret_rate = MGN_6M; break; ++ case DESC90_RATE9M: ret_rate = MGN_9M; break; ++ case DESC90_RATE12M: ret_rate = MGN_12M; break; ++ case DESC90_RATE18M: ret_rate = MGN_18M; break; ++ case DESC90_RATE24M: ret_rate = MGN_24M; break; ++ case DESC90_RATE36M: ret_rate = MGN_36M; break; ++ case DESC90_RATE48M: ret_rate = MGN_48M; break; ++ case DESC90_RATE54M: ret_rate = MGN_54M; break; ++ ++ default: ++ RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n", rate, bIsHT); ++ break; ++ } ++ ++ } else { ++ switch(rate) { ++ case DESC90_RATEMCS0: ret_rate = MGN_MCS0; break; ++ case DESC90_RATEMCS1: ret_rate = MGN_MCS1; break; ++ case DESC90_RATEMCS2: ret_rate = MGN_MCS2; break; ++ case DESC90_RATEMCS3: ret_rate = MGN_MCS3; break; ++ case DESC90_RATEMCS4: ret_rate = MGN_MCS4; break; ++ case DESC90_RATEMCS5: ret_rate = MGN_MCS5; break; ++ case DESC90_RATEMCS6: ret_rate = MGN_MCS6; break; ++ case DESC90_RATEMCS7: ret_rate = MGN_MCS7; break; ++ case DESC90_RATEMCS8: ret_rate = MGN_MCS8; break; ++ case DESC90_RATEMCS9: ret_rate = MGN_MCS9; break; ++ case DESC90_RATEMCS10: ret_rate = MGN_MCS10; break; ++ case DESC90_RATEMCS11: ret_rate = MGN_MCS11; break; ++ case DESC90_RATEMCS12: ret_rate = MGN_MCS12; break; ++ case DESC90_RATEMCS13: ret_rate = MGN_MCS13; break; ++ case DESC90_RATEMCS14: ret_rate = MGN_MCS14; break; ++ case DESC90_RATEMCS15: ret_rate = MGN_MCS15; break; ++ case DESC90_RATEMCS32: ret_rate = (0x80|0x20); break; ++ ++ default: ++ RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT); ++ break; ++ } ++ } ++ ++ return ret_rate; ++} ++ ++/** ++ * Function: UpdateRxPktTimeStamp ++ * Overview: Recored down the TSF time stamp when receiving a packet ++ * ++ * Input: ++ * PADAPTER Adapter ++ * PRT_RFD pRfd, ++ * ++ * Output: ++ * PRT_RFD pRfd ++ * (pRfd->Status.TimeStampHigh is updated) ++ * (pRfd->Status.TimeStampLow is updated) ++ * Return: ++ * None ++ */ ++static void UpdateRxPktTimeStamp8190 (struct net_device *dev, struct ieee80211_rx_stats *stats) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ ++ if(stats->bIsAMPDU && !stats->bFirstMPDU) { ++ stats->mac_time[0] = priv->LastRxDescTSFLow; ++ stats->mac_time[1] = priv->LastRxDescTSFHigh; ++ } else { ++ priv->LastRxDescTSFLow = stats->mac_time[0]; ++ priv->LastRxDescTSFHigh = stats->mac_time[1]; ++ } ++} ++ ++static long rtl819x_translate_todbm(u8 signal_strength_index)// 0-100 index. ++{ ++ long signal_power; // in dBm. ++ ++ // Translate to dBm (x=0.5y-95). ++ signal_power = (long)((signal_strength_index + 1) >> 1); ++ signal_power -= 95; ++ ++ return signal_power; ++} ++ ++// ++// Description: ++// Update Rx signal related information in the packet reeived ++// to RxStats. User application can query RxStats to realize ++// current Rx signal status. ++// ++// Assumption: ++// In normal operation, user only care about the information of the BSS ++// and we shall invoke this function if the packet received is from the BSS. ++// ++static void ++rtl819x_update_rxsignalstatistics8190pci( ++ struct r8192_priv * priv, ++ struct ieee80211_rx_stats * pprevious_stats ++ ) ++{ ++ int weighting = 0; ++ ++ //2 Update Rx Statistics (such as signal strength and signal quality). ++ ++ // Initila state ++ if(priv->stats.recv_signal_power == 0) ++ priv->stats.recv_signal_power = pprevious_stats->RecvSignalPower; ++ ++ // To avoid the past result restricting the statistics sensitivity, weight the current power (5/6) to speed up the ++ // reaction of smoothed Signal Power. ++ if(pprevious_stats->RecvSignalPower > priv->stats.recv_signal_power) ++ weighting = 5; ++ else if(pprevious_stats->RecvSignalPower < priv->stats.recv_signal_power) ++ weighting = (-5); ++ // ++ // We need more correct power of received packets and the "SignalStrength" of RxStats have been beautified or translated, ++ // so we record the correct power in Dbm here. By Bruce, 2008-03-07. ++ // ++ priv->stats.recv_signal_power = (priv->stats.recv_signal_power * 5 + pprevious_stats->RecvSignalPower + weighting) / 6; ++} ++ ++static void ++rtl8190_process_cck_rxpathsel( ++ struct r8192_priv * priv, ++ struct ieee80211_rx_stats * pprevious_stats ++ ) ++{ ++#ifdef RTL8190P //Only 90P 2T4R need to check ++ char last_cck_adc_pwdb[4]={0,0,0,0}; ++ u8 i; ++//cosa add for Rx path selection ++ if(priv->rf_type == RF_2T4R && DM_RxPathSelTable.Enable) ++ { ++ if(pprevious_stats->bIsCCK && ++ (pprevious_stats->bPacketToSelf ||pprevious_stats->bPacketBeacon)) ++ { ++ /* record the cck adc_pwdb to the sliding window. */ ++ if(priv->stats.cck_adc_pwdb.TotalNum++ >= PHY_RSSI_SLID_WIN_MAX) ++ { ++ priv->stats.cck_adc_pwdb.TotalNum = PHY_RSSI_SLID_WIN_MAX; ++ for(i=RF90_PATH_A; istats.cck_adc_pwdb.elements[i][priv->stats.cck_adc_pwdb.index]; ++ priv->stats.cck_adc_pwdb.TotalVal[i] -= last_cck_adc_pwdb[i]; ++ } ++ } ++ for(i=RF90_PATH_A; istats.cck_adc_pwdb.TotalVal[i] += pprevious_stats->cck_adc_pwdb[i]; ++ priv->stats.cck_adc_pwdb.elements[i][priv->stats.cck_adc_pwdb.index] = pprevious_stats->cck_adc_pwdb[i]; ++ } ++ priv->stats.cck_adc_pwdb.index++; ++ if(priv->stats.cck_adc_pwdb.index >= PHY_RSSI_SLID_WIN_MAX) ++ priv->stats.cck_adc_pwdb.index = 0; ++ ++ for(i=RF90_PATH_A; istats.cck_adc_pwdb.TotalVal[i]/priv->stats.cck_adc_pwdb.TotalNum; ++ } ++ ++ for(i=RF90_PATH_A; icck_adc_pwdb[i] > (char)priv->undecorated_smoothed_cck_adc_pwdb[i]) ++ { ++ priv->undecorated_smoothed_cck_adc_pwdb[i] = ++ ( (priv->undecorated_smoothed_cck_adc_pwdb[i]*(Rx_Smooth_Factor-1)) + ++ (pprevious_stats->cck_adc_pwdb[i])) /(Rx_Smooth_Factor); ++ priv->undecorated_smoothed_cck_adc_pwdb[i] = priv->undecorated_smoothed_cck_adc_pwdb[i] + 1; ++ } ++ else ++ { ++ priv->undecorated_smoothed_cck_adc_pwdb[i] = ++ ( (priv->undecorated_smoothed_cck_adc_pwdb[i]*(Rx_Smooth_Factor-1)) + ++ (pprevious_stats->cck_adc_pwdb[i])) /(Rx_Smooth_Factor); ++ } ++ } ++ } ++ } ++#endif ++} ++ ++ ++/* 2008/01/22 MH We can not delcare RSSI/EVM total value of sliding window to ++ be a local static. Otherwise, it may increase when we return from S3/S4. The ++ value will be kept in memory or disk. We must delcare the value in adapter ++ and it will be reinitialized when return from S3/S4. */ ++static void rtl8192_process_phyinfo(struct r8192_priv * priv, u8* buffer,struct ieee80211_rx_stats * pprevious_stats, struct ieee80211_rx_stats * pcurrent_stats) ++{ ++ bool bcheck = false; ++ u8 rfpath; ++ u32 nspatial_stream, tmp_val; ++ //u8 i; ++ static u32 slide_rssi_index=0, slide_rssi_statistics=0; ++ static u32 slide_evm_index=0, slide_evm_statistics=0; ++ static u32 last_rssi=0, last_evm=0; ++ //cosa add for rx path selection ++// static long slide_cck_adc_pwdb_index=0, slide_cck_adc_pwdb_statistics=0; ++// static char last_cck_adc_pwdb[4]={0,0,0,0}; ++ //cosa add for beacon rssi smoothing ++ static u32 slide_beacon_adc_pwdb_index=0, slide_beacon_adc_pwdb_statistics=0; ++ static u32 last_beacon_adc_pwdb=0; ++ ++ struct ieee80211_hdr_3addr *hdr; ++ u16 sc ; ++ unsigned int frag,seq; ++ hdr = (struct ieee80211_hdr_3addr *)buffer; ++ sc = le16_to_cpu(hdr->seq_ctl); ++ frag = WLAN_GET_SEQ_FRAG(sc); ++ seq = WLAN_GET_SEQ_SEQ(sc); ++ //cosa add 04292008 to record the sequence number ++ pcurrent_stats->Seq_Num = seq; ++ // ++ // Check whether we should take the previous packet into accounting ++ // ++ if(!pprevious_stats->bIsAMPDU) ++ { ++ // if previous packet is not aggregated packet ++ bcheck = true; ++ }else ++ { ++//remve for that we don't use AMPDU to calculate PWDB,because the reported PWDB of some AP is fault. ++#if 0 ++ // if previous packet is aggregated packet, and current packet ++ // (1) is not AMPDU ++ // (2) is the first packet of one AMPDU ++ // that means the previous packet is the last one aggregated packet ++ if( !pcurrent_stats->bIsAMPDU || pcurrent_stats->bFirstMPDU) ++ bcheck = true; ++#endif ++ } ++ ++ if(slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) ++ { ++ slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX; ++ last_rssi = priv->stats.slide_signal_strength[slide_rssi_index]; ++ priv->stats.slide_rssi_total -= last_rssi; ++ } ++ priv->stats.slide_rssi_total += pprevious_stats->SignalStrength; ++ ++ priv->stats.slide_signal_strength[slide_rssi_index++] = pprevious_stats->SignalStrength; ++ if(slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX) ++ slide_rssi_index = 0; ++ ++ // <1> Showed on UI for user, in dbm ++ tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics; ++ priv->stats.signal_strength = rtl819x_translate_todbm((u8)tmp_val); ++ pcurrent_stats->rssi = priv->stats.signal_strength; ++ // ++ // If the previous packet does not match the criteria, neglect it ++ // ++ if(!pprevious_stats->bPacketMatchBSSID) ++ { ++ if(!pprevious_stats->bToSelfBA) ++ return; ++ } ++ ++ if(!bcheck) ++ return; ++ ++ rtl8190_process_cck_rxpathsel(priv,pprevious_stats); ++ ++ // ++ // Check RSSI ++ // ++ priv->stats.num_process_phyinfo++; ++#if 0 ++ /* record the general signal strength to the sliding window. */ ++ if(slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) ++ { ++ slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX; ++ last_rssi = priv->stats.slide_signal_strength[slide_rssi_index]; ++ priv->stats.slide_rssi_total -= last_rssi; ++ } ++ priv->stats.slide_rssi_total += pprevious_stats->SignalStrength; ++ ++ priv->stats.slide_signal_strength[slide_rssi_index++] = pprevious_stats->SignalStrength; ++ if(slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX) ++ slide_rssi_index = 0; ++ ++ // <1> Showed on UI for user, in dbm ++ tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics; ++ priv->stats.signal_strength = rtl819x_translate_todbm((u8)tmp_val); ++ ++#endif ++ // <2> Showed on UI for engineering ++ // hardware does not provide rssi information for each rf path in CCK ++ if(!pprevious_stats->bIsCCK && pprevious_stats->bPacketToSelf) ++ { ++ for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) ++ { ++ if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, rfpath)) ++ continue; ++ RT_TRACE(COMP_DBG,"Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath] = %d \n" ,pprevious_stats->RxMIMOSignalStrength[rfpath] ); ++ //Fixed by Jacken 2008-03-20 ++ if(priv->stats.rx_rssi_percentage[rfpath] == 0) ++ { ++ priv->stats.rx_rssi_percentage[rfpath] = pprevious_stats->RxMIMOSignalStrength[rfpath]; ++ //DbgPrint("MIMO RSSI initialize \n"); ++ } ++ if(pprevious_stats->RxMIMOSignalStrength[rfpath] > priv->stats.rx_rssi_percentage[rfpath]) ++ { ++ priv->stats.rx_rssi_percentage[rfpath] = ++ ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) + ++ (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor); ++ priv->stats.rx_rssi_percentage[rfpath] = priv->stats.rx_rssi_percentage[rfpath] + 1; ++ } ++ else ++ { ++ priv->stats.rx_rssi_percentage[rfpath] = ++ ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) + ++ (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor); ++ } ++ RT_TRACE(COMP_DBG,"Jacken -> priv->RxStats.RxRSSIPercentage[rfPath] = %d \n" ,priv->stats.rx_rssi_percentage[rfpath] ); ++ } ++ } ++ ++ ++ // ++ // Check PWDB. ++ // ++ //cosa add for beacon rssi smoothing by average. ++ if(pprevious_stats->bPacketBeacon) ++ { ++ /* record the beacon pwdb to the sliding window. */ ++ if(slide_beacon_adc_pwdb_statistics++ >= PHY_Beacon_RSSI_SLID_WIN_MAX) ++ { ++ slide_beacon_adc_pwdb_statistics = PHY_Beacon_RSSI_SLID_WIN_MAX; ++ last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index]; ++ priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb; ++ //DbgPrint("slide_beacon_adc_pwdb_index = %d, last_beacon_adc_pwdb = %d, Adapter->RxStats.Slide_Beacon_Total = %d\n", ++ // slide_beacon_adc_pwdb_index, last_beacon_adc_pwdb, Adapter->RxStats.Slide_Beacon_Total); ++ } ++ priv->stats.Slide_Beacon_Total += pprevious_stats->RxPWDBAll; ++ priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] = pprevious_stats->RxPWDBAll; ++ //DbgPrint("slide_beacon_adc_pwdb_index = %d, pPreviousRfd->Status.RxPWDBAll = %d\n", slide_beacon_adc_pwdb_index, pPreviousRfd->Status.RxPWDBAll); ++ slide_beacon_adc_pwdb_index++; ++ if(slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX) ++ slide_beacon_adc_pwdb_index = 0; ++ pprevious_stats->RxPWDBAll = priv->stats.Slide_Beacon_Total/slide_beacon_adc_pwdb_statistics; ++ if(pprevious_stats->RxPWDBAll >= 3) ++ pprevious_stats->RxPWDBAll -= 3; ++ } ++ ++ RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n", ++ pprevious_stats->bIsCCK? "CCK": "OFDM", ++ pprevious_stats->RxPWDBAll); ++ ++ if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA) ++ { ++ if(priv->undecorated_smoothed_pwdb < 0) // initialize ++ { ++ priv->undecorated_smoothed_pwdb = pprevious_stats->RxPWDBAll; ++ //DbgPrint("First pwdb initialize \n"); ++ } ++#if 1 ++ if(pprevious_stats->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) ++ { ++ priv->undecorated_smoothed_pwdb = ++ ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) + ++ (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor); ++ priv->undecorated_smoothed_pwdb = priv->undecorated_smoothed_pwdb + 1; ++ } ++ else ++ { ++ priv->undecorated_smoothed_pwdb = ++ ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) + ++ (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor); ++ } ++#else ++ //Fixed by Jacken 2008-03-20 ++ if(pPreviousRfd->Status.RxPWDBAll > (u32)pHalData->UndecoratedSmoothedPWDB) ++ { ++ pHalData->UndecoratedSmoothedPWDB = ++ ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6; ++ pHalData->UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB + 1; ++ } ++ else ++ { ++ pHalData->UndecoratedSmoothedPWDB = ++ ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6; ++ } ++#endif ++ rtl819x_update_rxsignalstatistics8190pci(priv,pprevious_stats); ++ } ++ ++ // ++ // Check EVM ++ // ++ /* record the general EVM to the sliding window. */ ++ if(pprevious_stats->SignalQuality == 0) ++ { ++ } ++ else ++ { ++ if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA){ ++ if(slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX){ ++ slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX; ++ last_evm = priv->stats.slide_evm[slide_evm_index]; ++ priv->stats.slide_evm_total -= last_evm; ++ } ++ ++ priv->stats.slide_evm_total += pprevious_stats->SignalQuality; ++ ++ priv->stats.slide_evm[slide_evm_index++] = pprevious_stats->SignalQuality; ++ if(slide_evm_index >= PHY_RSSI_SLID_WIN_MAX) ++ slide_evm_index = 0; ++ ++ // <1> Showed on UI for user, in percentage. ++ tmp_val = priv->stats.slide_evm_total/slide_evm_statistics; ++ priv->stats.signal_quality = tmp_val; ++ //cosa add 10/11/2007, Showed on UI for user in Windows Vista, for Link quality. ++ priv->stats.last_signal_strength_inpercent = tmp_val; ++ } ++ ++ // <2> Showed on UI for engineering ++ if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA) ++ { ++ for(nspatial_stream = 0; nspatial_stream<2 ; nspatial_stream++) // 2 spatial stream ++ { ++ if(pprevious_stats->RxMIMOSignalQuality[nspatial_stream] != -1) ++ { ++ if(priv->stats.rx_evm_percentage[nspatial_stream] == 0) // initialize ++ { ++ priv->stats.rx_evm_percentage[nspatial_stream] = pprevious_stats->RxMIMOSignalQuality[nspatial_stream]; ++ } ++ priv->stats.rx_evm_percentage[nspatial_stream] = ++ ( (priv->stats.rx_evm_percentage[nspatial_stream]* (Rx_Smooth_Factor-1)) + ++ (pprevious_stats->RxMIMOSignalQuality[nspatial_stream]* 1)) / (Rx_Smooth_Factor); ++ } ++ } ++ } ++ } ++ ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: rtl819x_query_rxpwrpercentage() ++ * ++ * Overview: ++ * ++ * Input: char antpower ++ * ++ * Output: NONE ++ * ++ * Return: 0-100 percentage ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/26/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++static u8 rtl819x_query_rxpwrpercentage( ++ char antpower ++ ) ++{ ++ if ((antpower <= -100) || (antpower >= 20)) ++ { ++ return 0; ++ } ++ else if (antpower >= 0) ++ { ++ return 100; ++ } ++ else ++ { ++ return (100+antpower); ++ } ++ ++} /* QueryRxPwrPercentage */ ++ ++static u8 ++rtl819x_evm_dbtopercentage( ++ char value ++ ) ++{ ++ char ret_val; ++ ++ ret_val = value; ++ ++ if(ret_val >= 0) ++ ret_val = 0; ++ if(ret_val <= -33) ++ ret_val = -33; ++ ret_val = 0 - ret_val; ++ ret_val*=3; ++ if(ret_val == 99) ++ ret_val = 100; ++ return(ret_val); ++} ++ ++// ++// Description: ++// We want good-looking for signal strength/quality ++// 2007/7/19 01:09, by cosa. ++// ++static long rtl819x_signal_scale_mapping(long currsig) ++{ ++ long retsig; ++ ++ // Step 1. Scale mapping. ++ if(currsig >= 61 && currsig <= 100) ++ { ++ retsig = 90 + ((currsig - 60) / 4); ++ } ++ else if(currsig >= 41 && currsig <= 60) ++ { ++ retsig = 78 + ((currsig - 40) / 2); ++ } ++ else if(currsig >= 31 && currsig <= 40) ++ { ++ retsig = 66 + (currsig - 30); ++ } ++ else if(currsig >= 21 && currsig <= 30) ++ { ++ retsig = 54 + (currsig - 20); ++ } ++ else if(currsig >= 5 && currsig <= 20) ++ { ++ retsig = 42 + (((currsig - 5) * 2) / 3); ++ } ++ else if(currsig == 4) ++ { ++ retsig = 36; ++ } ++ else if(currsig == 3) ++ { ++ retsig = 27; ++ } ++ else if(currsig == 2) ++ { ++ retsig = 18; ++ } ++ else if(currsig == 1) ++ { ++ retsig = 9; ++ } ++ else ++ { ++ retsig = currsig; ++ } ++ ++ return retsig; ++} ++ ++static void rtl8192_query_rxphystatus( ++ struct r8192_priv * priv, ++ struct ieee80211_rx_stats * pstats, ++ prx_desc_819x_pci pdesc, ++ prx_fwinfo_819x_pci pdrvinfo, ++ struct ieee80211_rx_stats * precord_stats, ++ bool bpacket_match_bssid, ++ bool bpacket_toself, ++ bool bPacketBeacon, ++ bool bToSelfBA ++ ) ++{ ++ //PRT_RFD_STATUS pRtRfdStatus = &(pRfd->Status); ++ phy_sts_ofdm_819xpci_t* pofdm_buf; ++ phy_sts_cck_819xpci_t * pcck_buf; ++ phy_ofdm_rx_status_rxsc_sgien_exintfflag* prxsc; ++ u8 *prxpkt; ++ u8 i,max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg; ++ char rx_pwr[4], rx_pwr_all=0; ++ //long rx_avg_pwr = 0; ++ char rx_snrX, rx_evmX; ++ u8 evm, pwdb_all; ++ u32 RSSI, total_rssi=0;//, total_evm=0; ++// long signal_strength_index = 0; ++ u8 is_cck_rate=0; ++ u8 rf_rx_num = 0; ++ ++ /* 2007/07/04 MH For OFDM RSSI. For high power or not. */ ++ static u8 check_reg824 = 0; ++ static u32 reg824_bit9 = 0; ++ ++ priv->stats.numqry_phystatus++; ++ ++ is_cck_rate = rx_hal_is_cck_rate(pdrvinfo); ++ ++ // Record it for next packet processing ++ memset(precord_stats, 0, sizeof(struct ieee80211_rx_stats)); ++ pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = bpacket_match_bssid; ++ pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself; ++ pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;//RX_HAL_IS_CCK_RATE(pDrvInfo); ++ pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon; ++ pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA; ++ /*2007.08.30 requested by SD3 Jerry */ ++ if(check_reg824 == 0) ++ { ++ reg824_bit9 = rtl8192_QueryBBReg(priv->ieee80211->dev, rFPGA0_XA_HSSIParameter2, 0x200); ++ check_reg824 = 1; ++ } ++ ++ ++ prxpkt = (u8*)pdrvinfo; ++ ++ /* Move pointer to the 16th bytes. Phy status start address. */ ++ prxpkt += sizeof(rx_fwinfo_819x_pci); ++ ++ /* Initial the cck and ofdm buffer pointer */ ++ pcck_buf = (phy_sts_cck_819xpci_t *)prxpkt; ++ pofdm_buf = (phy_sts_ofdm_819xpci_t *)prxpkt; ++ ++ pstats->RxMIMOSignalQuality[0] = -1; ++ pstats->RxMIMOSignalQuality[1] = -1; ++ precord_stats->RxMIMOSignalQuality[0] = -1; ++ precord_stats->RxMIMOSignalQuality[1] = -1; ++ ++ if(is_cck_rate) ++ { ++ // ++ // (1)Hardware does not provide RSSI for CCK ++ // ++ ++ // ++ // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) ++ // ++ u8 report;//, cck_agc_rpt; ++#ifdef RTL8190P ++ u8 tmp_pwdb; ++ char cck_adc_pwdb[4]; ++#endif ++ priv->stats.numqry_phystatusCCK++; ++ ++#ifdef RTL8190P //Only 90P 2T4R need to check ++ if(priv->rf_type == RF_2T4R && DM_RxPathSelTable.Enable && bpacket_match_bssid) ++ { ++ for(i=RF90_PATH_A; iadc_pwdb_X[i]; ++ cck_adc_pwdb[i] = (char)tmp_pwdb; ++ cck_adc_pwdb[i] /= 2; ++ pstats->cck_adc_pwdb[i] = precord_stats->cck_adc_pwdb[i] = cck_adc_pwdb[i]; ++ //DbgPrint("RF-%d tmp_pwdb = 0x%x, cck_adc_pwdb = %d", i, tmp_pwdb, cck_adc_pwdb[i]); ++ } ++ } ++#endif ++ ++ if(!reg824_bit9) ++ { ++ report = pcck_buf->cck_agc_rpt & 0xc0; ++ report = report>>6; ++ switch(report) ++ { ++ //Fixed by Jacken from Bryant 2008-03-20 ++ //Original value is -38 , -26 , -14 , -2 ++ //Fixed value is -35 , -23 , -11 , 6 ++ case 0x3: ++ rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & 0x3e); ++ break; ++ case 0x2: ++ rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & 0x3e); ++ break; ++ case 0x1: ++ rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & 0x3e); ++ break; ++ case 0x0: ++ rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e); ++ break; ++ } ++ } ++ else ++ { ++ report = pcck_buf->cck_agc_rpt & 0x60; ++ report = report>>5; ++ switch(report) ++ { ++ case 0x3: ++ rx_pwr_all = -35 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ; ++ break; ++ case 0x2: ++ rx_pwr_all = -23 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1); ++ break; ++ case 0x1: ++ rx_pwr_all = -11 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ; ++ break; ++ case 0x0: ++ rx_pwr_all = -8 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ; ++ break; ++ } ++ } ++ ++ pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all); ++ pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all; ++ pstats->RecvSignalPower = rx_pwr_all; ++ ++ // ++ // (3) Get Signal Quality (EVM) ++ // ++ if(bpacket_match_bssid) ++ { ++ u8 sq; ++ ++ if(pstats->RxPWDBAll > 40) ++ { ++ sq = 100; ++ }else ++ { ++ sq = pcck_buf->sq_rpt; ++ ++ if(pcck_buf->sq_rpt > 64) ++ sq = 0; ++ else if (pcck_buf->sq_rpt < 20) ++ sq = 100; ++ else ++ sq = ((64-sq) * 100) / 44; ++ } ++ pstats->SignalQuality = precord_stats->SignalQuality = sq; ++ pstats->RxMIMOSignalQuality[0] = precord_stats->RxMIMOSignalQuality[0] = sq; ++ pstats->RxMIMOSignalQuality[1] = precord_stats->RxMIMOSignalQuality[1] = -1; ++ } ++ } ++ else ++ { ++ priv->stats.numqry_phystatusHT++; ++ // ++ // (1)Get RSSI for HT rate ++ // ++ for(i=RF90_PATH_A; ibrfpath_rxenable[i]) ++ rf_rx_num++; ++ //else ++ //continue; ++ ++ //Fixed by Jacken from Bryant 2008-03-20 ++ //Original value is 106 ++#ifdef RTL8190P //Modify by Jacken 2008/03/31 ++ rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 106; ++#else ++ rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 110; ++#endif ++ ++ //Get Rx snr value in DB ++ tmp_rxsnr = pofdm_buf->rxsnr_X[i]; ++ rx_snrX = (char)(tmp_rxsnr); ++ rx_snrX /= 2; ++ priv->stats.rxSNRdB[i] = (long)rx_snrX; ++ ++ /* Translate DBM to percentage. */ ++ RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]); ++ if (priv->brfpath_rxenable[i]) ++ total_rssi += RSSI; ++ ++ /* Record Signal Strength for next packet */ ++ if(bpacket_match_bssid) ++ { ++ pstats->RxMIMOSignalStrength[i] =(u8) RSSI; ++ precord_stats->RxMIMOSignalStrength[i] =(u8) RSSI; ++ } ++ } ++ ++ ++ // ++ // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) ++ // ++ //Fixed by Jacken from Bryant 2008-03-20 ++ //Original value is 106 ++ rx_pwr_all = (((pofdm_buf->pwdb_all ) >> 1 )& 0x7f) -106; ++ pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all); ++ ++ pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all; ++ pstats->RxPower = precord_stats->RxPower = rx_pwr_all; ++ pstats->RecvSignalPower = rx_pwr_all; ++ // ++ // (3)EVM of HT rate ++ // ++ if(pdrvinfo->RxHT && pdrvinfo->RxRate>=DESC90_RATEMCS8 && ++ pdrvinfo->RxRate<=DESC90_RATEMCS15) ++ max_spatial_stream = 2; //both spatial stream make sense ++ else ++ max_spatial_stream = 1; //only spatial stream 1 makes sense ++ ++ for(i=0; irxevm_X[i]; ++ rx_evmX = (char)(tmp_rxevm); ++ ++ // Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment ++ // fill most significant bit to "zero" when doing shifting operation which may change a negative ++ // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. ++ rx_evmX /= 2; //dbm ++ ++ evm = rtl819x_evm_dbtopercentage(rx_evmX); ++#if 0 ++ EVM = SignalScaleMapping(EVM);//make it good looking, from 0~100 ++#endif ++ if(bpacket_match_bssid) ++ { ++ if(i==0) // Fill value in RFD, Get the first spatial stream only ++ pstats->SignalQuality = precord_stats->SignalQuality = (u8)(evm & 0xff); ++ pstats->RxMIMOSignalQuality[i] = precord_stats->RxMIMOSignalQuality[i] = (u8)(evm & 0xff); ++ } ++ } ++ ++ ++ /* record rx statistics for debug */ ++ rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg; ++ prxsc = (phy_ofdm_rx_status_rxsc_sgien_exintfflag *)&rxsc_sgien_exflg; ++ if(pdrvinfo->BW) //40M channel ++ priv->stats.received_bwtype[1+prxsc->rxsc]++; ++ else //20M channel ++ priv->stats.received_bwtype[0]++; ++ } ++ ++ //UI BSS List signal strength(in percentage), make it good looking, from 0~100. ++ //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). ++ if(is_cck_rate) ++ { ++ pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)pwdb_all));//PWDB_ALL; ++ ++ } ++ else ++ { ++ //pRfd->Status.SignalStrength = pRecordRfd->Status.SignalStrength = (u1Byte)(SignalScaleMapping(total_rssi/=RF90_PATH_MAX));//(u1Byte)(total_rssi/=RF90_PATH_MAX); ++ // We can judge RX path number now. ++ if (rf_rx_num != 0) ++ pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)(total_rssi/=rf_rx_num))); ++ } ++} /* QueryRxPhyStatus8190Pci */ ++ ++static void ++rtl8192_record_rxdesc_forlateruse( ++ struct ieee80211_rx_stats * psrc_stats, ++ struct ieee80211_rx_stats * ptarget_stats ++) ++{ ++ ptarget_stats->bIsAMPDU = psrc_stats->bIsAMPDU; ++ ptarget_stats->bFirstMPDU = psrc_stats->bFirstMPDU; ++ //ptarget_stats->Seq_Num = psrc_stats->Seq_Num; ++} ++ ++ ++ ++static void TranslateRxSignalStuff819xpci(struct net_device *dev, ++ struct sk_buff *skb, ++ struct ieee80211_rx_stats * pstats, ++ prx_desc_819x_pci pdesc, ++ prx_fwinfo_819x_pci pdrvinfo) ++{ ++ // TODO: We must only check packet for current MAC address. Not finish ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ bool bpacket_match_bssid, bpacket_toself; ++ bool bPacketBeacon=false, bToSelfBA=false; ++ static struct ieee80211_rx_stats previous_stats; ++ struct ieee80211_hdr_3addr *hdr; ++ u16 fc,type; ++ ++ // Get Signal Quality for only RX data queue (but not command queue) ++ ++ u8* tmp_buf; ++ u8 *praddr; ++ ++ /* Get MAC frame start address. */ ++ tmp_buf = skb->data; ++ ++ hdr = (struct ieee80211_hdr_3addr *)tmp_buf; ++ fc = le16_to_cpu(hdr->frame_ctl); ++ type = WLAN_FC_GET_TYPE(fc); ++ praddr = hdr->addr1; ++ ++ /* Check if the received packet is acceptabe. */ ++ bpacket_match_bssid = ((IEEE80211_FTYPE_CTL != type) && ++ (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3)) ++ && (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV)); ++ bpacket_toself = bpacket_match_bssid & (eqMacAddr(praddr, priv->ieee80211->dev->dev_addr)); ++#if 1//cosa ++ if(WLAN_FC_GET_FRAMETYPE(fc)== IEEE80211_STYPE_BEACON) ++ { ++ bPacketBeacon = true; ++ //DbgPrint("Beacon 2, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf); ++ } ++ if(WLAN_FC_GET_FRAMETYPE(fc) == IEEE80211_STYPE_BLOCKACK) ++ { ++ if((eqMacAddr(praddr,dev->dev_addr))) ++ bToSelfBA = true; ++ //DbgPrint("BlockAck, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf); ++ } ++ ++#endif ++ if(bpacket_match_bssid) ++ { ++ priv->stats.numpacket_matchbssid++; ++ } ++ if(bpacket_toself){ ++ priv->stats.numpacket_toself++; ++ } ++ // ++ // Process PHY information for previous packet (RSSI/PWDB/EVM) ++ // ++ // Because phy information is contained in the last packet of AMPDU only, so driver ++ // should process phy information of previous packet ++ rtl8192_process_phyinfo(priv, tmp_buf,&previous_stats, pstats); ++ rtl8192_query_rxphystatus(priv, pstats, pdesc, pdrvinfo, &previous_stats, bpacket_match_bssid, ++ bpacket_toself ,bPacketBeacon, bToSelfBA); ++ rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats); ++ ++} ++ ++ ++static void rtl8192_tx_resume(struct net_device *dev) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ struct ieee80211_device *ieee = priv->ieee80211; ++ struct sk_buff *skb; ++ int queue_index; ++ ++ for(queue_index = BK_QUEUE; queue_index < TXCMD_QUEUE;queue_index++) { ++ while((!skb_queue_empty(&ieee->skb_waitQ[queue_index]))&& ++ (priv->ieee80211->check_nic_enough_desc(dev,queue_index) > 0)) { ++ /* 1. dequeue the packet from the wait queue */ ++ skb = skb_dequeue(&ieee->skb_waitQ[queue_index]); ++ /* 2. tx the packet directly */ ++ ieee->softmac_data_hard_start_xmit(skb,dev,0/* rate useless now*/); ++ #if 0 ++ if(queue_index!=MGNT_QUEUE) { ++ ieee->stats.tx_packets++; ++ ieee->stats.tx_bytes += skb->len; ++ } ++ #endif ++ } ++ } ++} ++ ++void rtl8192_irq_tx_tasklet(struct r8192_priv *priv) ++{ ++ rtl8192_tx_resume(priv->ieee80211->dev); ++} ++ ++/** ++* Function: UpdateReceivedRateHistogramStatistics ++* Overview: Recored down the received data rate ++* ++* Input: ++* PADAPTER Adapter ++* PRT_RFD pRfd, ++* ++* Output: ++* PRT_TCB Adapter ++* (Adapter->RxStats.ReceivedRateHistogram[] is updated) ++* Return: ++* None ++*/ ++static void UpdateReceivedRateHistogramStatistics8190( ++ struct net_device *dev, ++ struct ieee80211_rx_stats* pstats ++ ) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ u32 rcvType=1; //0: Total, 1:OK, 2:CRC, 3:ICV ++ u32 rateIndex; ++ u32 preamble_guardinterval; //1: short preamble/GI, 0: long preamble/GI ++ ++ /* 2007/03/09 MH We will not update rate of packet from rx cmd queue. */ ++ #if 0 ++ if (pRfd->queue_id == CMPK_RX_QUEUE_ID) ++ return; ++ #endif ++ if(pstats->bCRC) ++ rcvType = 2; ++ else if(pstats->bICV) ++ rcvType = 3; ++ ++ if(pstats->bShortPreamble) ++ preamble_guardinterval = 1;// short ++ else ++ preamble_guardinterval = 0;// long ++ ++ switch(pstats->rate) ++ { ++ // ++ // CCK rate ++ // ++ case MGN_1M: rateIndex = 0; break; ++ case MGN_2M: rateIndex = 1; break; ++ case MGN_5_5M: rateIndex = 2; break; ++ case MGN_11M: rateIndex = 3; break; ++ // ++ // Legacy OFDM rate ++ // ++ case MGN_6M: rateIndex = 4; break; ++ case MGN_9M: rateIndex = 5; break; ++ case MGN_12M: rateIndex = 6; break; ++ case MGN_18M: rateIndex = 7; break; ++ case MGN_24M: rateIndex = 8; break; ++ case MGN_36M: rateIndex = 9; break; ++ case MGN_48M: rateIndex = 10; break; ++ case MGN_54M: rateIndex = 11; break; ++ // ++ // 11n High throughput rate ++ // ++ case MGN_MCS0: rateIndex = 12; break; ++ case MGN_MCS1: rateIndex = 13; break; ++ case MGN_MCS2: rateIndex = 14; break; ++ case MGN_MCS3: rateIndex = 15; break; ++ case MGN_MCS4: rateIndex = 16; break; ++ case MGN_MCS5: rateIndex = 17; break; ++ case MGN_MCS6: rateIndex = 18; break; ++ case MGN_MCS7: rateIndex = 19; break; ++ case MGN_MCS8: rateIndex = 20; break; ++ case MGN_MCS9: rateIndex = 21; break; ++ case MGN_MCS10: rateIndex = 22; break; ++ case MGN_MCS11: rateIndex = 23; break; ++ case MGN_MCS12: rateIndex = 24; break; ++ case MGN_MCS13: rateIndex = 25; break; ++ case MGN_MCS14: rateIndex = 26; break; ++ case MGN_MCS15: rateIndex = 27; break; ++ default: rateIndex = 28; break; ++ } ++ priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++; ++ priv->stats.received_rate_histogram[0][rateIndex]++; //total ++ priv->stats.received_rate_histogram[rcvType][rateIndex]++; ++} ++ ++static void rtl8192_rx(struct net_device *dev) ++{ ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ struct ieee80211_hdr_1addr *ieee80211_hdr = NULL; ++ bool unicast_packet = false; ++ struct ieee80211_rx_stats stats = { ++ .signal = 0, ++ .noise = -98, ++ .rate = 0, ++ .freq = IEEE80211_24GHZ_BAND, ++ }; ++ unsigned int count = priv->rxringcount; ++ ++ stats.nic_type = NIC_8192E; ++ ++ while (count--) { ++ rx_desc_819x_pci *pdesc = &priv->rx_ring[priv->rx_idx];//rx descriptor ++ struct sk_buff *skb = priv->rx_buf[priv->rx_idx];//rx pkt ++ ++ if (pdesc->OWN){ ++ /* wait data to be filled by hardware */ ++ return; ++ } else { ++ stats.bICV = pdesc->ICV; ++ stats.bCRC = pdesc->CRC32; ++ stats.bHwError = pdesc->CRC32 | pdesc->ICV; ++ ++ stats.Length = pdesc->Length; ++ if(stats.Length < 24) ++ stats.bHwError |= 1; ++ ++ if(stats.bHwError) { ++ stats.bShift = false; ++ ++ if(pdesc->CRC32) { ++ if (pdesc->Length <500) ++ priv->stats.rxcrcerrmin++; ++ else if (pdesc->Length >1000) ++ priv->stats.rxcrcerrmax++; ++ else ++ priv->stats.rxcrcerrmid++; ++ } ++ goto done; ++ } else { ++ prx_fwinfo_819x_pci pDrvInfo = NULL; ++ struct sk_buff *new_skb = dev_alloc_skb(priv->rxbuffersize); ++ ++ if (unlikely(!new_skb)) { ++ goto done; ++ } ++ ++ stats.RxDrvInfoSize = pdesc->RxDrvInfoSize; ++ stats.RxBufShift = ((pdesc->Shift)&0x03); ++ stats.Decrypted = !pdesc->SWDec; ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ pci_dma_sync_single_for_cpu(priv->pdev, ++#else ++ pci_unmap_single(priv->pdev, ++#endif ++ *((dma_addr_t *)skb->cb), ++ priv->rxbuffersize, ++ PCI_DMA_FROMDEVICE); ++ skb_put(skb, pdesc->Length); ++ pDrvInfo = (rx_fwinfo_819x_pci *)(skb->data + stats.RxBufShift); ++ skb_reserve(skb, stats.RxDrvInfoSize + stats.RxBufShift); ++ ++ stats.rate = HwRateToMRate90((bool)pDrvInfo->RxHT, (u8)pDrvInfo->RxRate); ++ stats.bShortPreamble = pDrvInfo->SPLCP; ++ ++ /* it is debug only. It should be disabled in released driver. ++ * 2007.1.11 by Emily ++ * */ ++ UpdateReceivedRateHistogramStatistics8190(dev, &stats); ++ ++ stats.bIsAMPDU = (pDrvInfo->PartAggr==1); ++ stats.bFirstMPDU = (pDrvInfo->PartAggr==1) && (pDrvInfo->FirstAGGR==1); ++ ++ stats.TimeStampLow = pDrvInfo->TSFL; ++ stats.TimeStampHigh = read_nic_dword(dev, TSFR+4); ++ ++ UpdateRxPktTimeStamp8190(dev, &stats); ++ ++ // ++ // Get Total offset of MPDU Frame Body ++ // ++ if((stats.RxBufShift + stats.RxDrvInfoSize) > 0) ++ stats.bShift = 1; ++ ++ stats.RxIs40MHzPacket = pDrvInfo->BW; ++ ++ /* ???? */ ++ TranslateRxSignalStuff819xpci(dev,skb, &stats, pdesc, pDrvInfo); ++ ++ /* Rx A-MPDU */ ++ if(pDrvInfo->FirstAGGR==1 || pDrvInfo->PartAggr == 1) ++ RT_TRACE(COMP_RXDESC, "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n", ++ pDrvInfo->FirstAGGR, pDrvInfo->PartAggr); ++ skb_trim(skb, skb->len - 4/*sCrcLng*/); ++ /* rx packets statistics */ ++ ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data; ++ unicast_packet = false; ++ ++ if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) { ++ //TODO ++ }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){ ++ //TODO ++ }else { ++ /* unicast packet */ ++ unicast_packet = true; ++ } ++ ++ stats.packetlength = stats.Length-4; ++ stats.fraglength = stats.packetlength; ++ stats.fragoffset = 0; ++ stats.ntotalfrag = 1; ++ ++ if(!ieee80211_rx(priv->ieee80211, skb, &stats)){ ++ dev_kfree_skb_any(skb); ++ } else { ++ priv->stats.rxok++; ++ if(unicast_packet) { ++ priv->stats.rxbytesunicast += skb->len; ++ } ++ } ++ ++ skb = new_skb; ++ priv->rx_buf[priv->rx_idx] = skb; ++ *((dma_addr_t *) skb->cb) = pci_map_single(priv->pdev, skb->tail, priv->rxbuffersize, PCI_DMA_FROMDEVICE); ++// *((dma_addr_t *) skb->cb) = pci_map_single(priv->pdev, skb_tail_pointer(skb), priv->rxbuffersize, PCI_DMA_FROMDEVICE); ++ } ++ ++ } ++done: ++ pdesc->BufferAddress = cpu_to_le32(*((dma_addr_t *)skb->cb)); ++ pdesc->OWN = 1; ++ pdesc->Length = priv->rxbuffersize; ++ if (priv->rx_idx == priv->rxringcount-1) ++ pdesc->EOR = 1; ++ priv->rx_idx = (priv->rx_idx + 1) % priv->rxringcount; ++ } ++ ++} ++ ++void rtl8192_irq_rx_tasklet(struct r8192_priv *priv) ++{ ++ rtl8192_rx(priv->ieee80211->dev); ++ /* unmask RDU */ ++ write_nic_dword(priv->ieee80211->dev, INTA_MASK,read_nic_dword(priv->ieee80211->dev, INTA_MASK) | IMR_RDU); ++} ++ ++#if 0 ++static const struct net_device_ops rtl8192_netdev_ops = { ++ .ndo_open = rtl8192_open, ++ .ndo_stop = rtl8192_close, ++/* .ndo_get_stats = rtl8192_stats, */ ++ .ndo_tx_timeout = tx_timeout, ++ .ndo_do_ioctl = rtl8192_ioctl, ++ .ndo_set_multicast_list = r8192_set_multicast, ++ .ndo_set_mac_address = r8192_set_mac_adr, ++ .ndo_start_xmit = ieee80211_xmit, ++}; ++#endif ++ ++/**************************************************************************** ++ ---------------------------- PCI_STUFF--------------------------- ++*****************************************************************************/ ++ ++static int __devinit rtl8192_pci_probe(struct pci_dev *pdev, ++ const struct pci_device_id *id) ++{ ++ unsigned long ioaddr = 0; ++ struct net_device *dev = NULL; ++ struct r8192_priv *priv= NULL; ++ u8 unit = 0; ++ ++#ifdef CONFIG_RTL8192_IO_MAP ++ unsigned long pio_start, pio_len, pio_flags; ++#else ++ unsigned long pmem_start, pmem_len, pmem_flags; ++#endif //end #ifdef RTL_IO_MAP ++ ++ RT_TRACE(COMP_INIT,"Configuring chip resources"); ++ ++ if( pci_enable_device (pdev) ){ ++ RT_TRACE(COMP_ERR,"Failed to enable PCI device"); ++ return -EIO; ++ } ++ ++ pci_set_master(pdev); ++ //pci_set_wmi(pdev); ++ pci_set_dma_mask(pdev, 0xffffff00ULL); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ pci_set_consistent_dma_mask(pdev,0xffffff00ULL); ++#endif ++ dev = alloc_ieee80211(sizeof(struct r8192_priv)); ++ if (!dev) ++ return -ENOMEM; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ++ SET_MODULE_OWNER(dev); ++#endif ++ ++ pci_set_drvdata(pdev, dev); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ SET_NETDEV_DEV(dev, &pdev->dev); ++#endif ++ priv = ieee80211_priv(dev); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ priv->ieee80211 = netdev_priv(dev); ++#else ++ priv->ieee80211 = (struct ieee80211_device *)dev->priv; ++#endif ++ priv->pdev=pdev; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ if((pdev->subsystem_vendor == PCI_VENDOR_ID_DLINK)&&(pdev->subsystem_device == 0x3304)){ ++ priv->ieee80211->bSupportRemoteWakeUp = 1; ++ } else ++#endif ++ { ++ priv->ieee80211->bSupportRemoteWakeUp = 0; ++ } ++ ++#ifdef CONFIG_RTL8192_IO_MAP ++ ++ pio_start = (unsigned long)pci_resource_start (pdev, 0); ++ pio_len = (unsigned long)pci_resource_len (pdev, 0); ++ pio_flags = (unsigned long)pci_resource_flags (pdev, 0); ++ ++ if (!(pio_flags & IORESOURCE_IO)) { ++ RT_TRACE(COMP_ERR,"region #0 not a PIO resource, aborting"); ++ goto fail; ++ } ++ ++ //DMESG("IO space @ 0x%08lx", pio_start ); ++ if( ! request_region( pio_start, pio_len, RTL819xE_MODULE_NAME ) ){ ++ RT_TRACE(COMP_ERR,"request_region failed!"); ++ goto fail; ++ } ++ ++ ioaddr = pio_start; ++ dev->base_addr = ioaddr; // device I/O address ++ ++#else ++ ++ pmem_start = pci_resource_start(pdev, 1); ++ pmem_len = pci_resource_len(pdev, 1); ++ pmem_flags = pci_resource_flags (pdev, 1); ++ ++ if (!(pmem_flags & IORESOURCE_MEM)) { ++ RT_TRACE(COMP_ERR,"region #1 not a MMIO resource, aborting"); ++ goto fail; ++ } ++ ++ //DMESG("Memory mapped space @ 0x%08lx ", pmem_start); ++ if( ! request_mem_region(pmem_start, pmem_len, RTL819xE_MODULE_NAME)) { ++ RT_TRACE(COMP_ERR,"request_mem_region failed!"); ++ goto fail; ++ } ++ ++ ++ ioaddr = (unsigned long)ioremap_nocache( pmem_start, pmem_len); ++ if( ioaddr == (unsigned long)NULL ){ ++ RT_TRACE(COMP_ERR,"ioremap failed!"); ++ // release_mem_region( pmem_start, pmem_len ); ++ goto fail1; ++ } ++ ++ dev->mem_start = ioaddr; // shared mem start ++ dev->mem_end = ioaddr + pci_resource_len(pdev, 0); // shared mem end ++ ++#endif //end #ifdef RTL_IO_MAP ++ ++ /* We disable the RETRY_TIMEOUT register (0x41) to keep ++ * PCI Tx retries from interfering with C3 CPU state */ ++ pci_write_config_byte(pdev, 0x41, 0x00); ++ ++ ++ pci_read_config_byte(pdev, 0x05, &unit); ++ pci_write_config_byte(pdev, 0x05, unit & (~0x04)); ++ ++ dev->irq = pdev->irq; ++ priv->irq = 0; ++ ++#if 0 ++ dev->netdev_ops = &rtl8192_netdev_ops; ++#endif ++ dev->open = rtl8192_open; ++ dev->stop = rtl8192_close; ++ //dev->hard_start_xmit = rtl8192_8023_hard_start_xmit; ++ dev->tx_timeout = tx_timeout; ++ //dev->wireless_handlers = &r8192_wx_handlers_def; ++ dev->do_ioctl = rtl8192_ioctl; ++ dev->set_multicast_list = r8192_set_multicast; ++ dev->set_mac_address = r8192_set_mac_adr; ++ ++ //DMESG("Oops: i'm coming\n"); ++#if WIRELESS_EXT >= 12 ++#if WIRELESS_EXT < 17 ++ dev->get_wireless_stats = r8192_get_wireless_stats; ++#endif ++ dev->wireless_handlers = (struct iw_handler_def *) &r8192_wx_handlers_def; ++#endif ++ //dev->get_wireless_stats = r8192_get_wireless_stats; ++ dev->type=ARPHRD_ETHER; ++ ++ dev->watchdog_timeo = HZ*3; //modified by john, 0805 ++ ++ if (dev_alloc_name(dev, ifname) < 0){ ++ RT_TRACE(COMP_INIT, "Oops: devname already taken! Trying wlan%%d...\n"); ++ ifname = "wlan%d"; ++ dev_alloc_name(dev, ifname); ++ } ++ ++ RT_TRACE(COMP_INIT, "Driver probe completed1\n"); ++ if(rtl8192_init(dev)!=0){ ++ RT_TRACE(COMP_ERR, "Initialization failed"); ++ goto fail; ++ } ++ ++ netif_carrier_off(dev); ++ netif_stop_queue(dev); ++ ++ register_netdev(dev); ++ RT_TRACE(COMP_INIT, "dev name=======> %s\n",dev->name); ++ rtl8192_proc_init_one(dev); ++ ++ ++ RT_TRACE(COMP_INIT, "Driver probe completed\n"); ++//#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++// return dev; ++//#else ++ return 0; ++//#endif ++ ++fail1: ++ ++#ifdef CONFIG_RTL8180_IO_MAP ++ ++ if( dev->base_addr != 0 ){ ++ ++ release_region(dev->base_addr, ++ pci_resource_len(pdev, 0) ); ++ } ++#else ++ if( dev->mem_start != (unsigned long)NULL ){ ++ iounmap( (void *)dev->mem_start ); ++ release_mem_region( pci_resource_start(pdev, 1), ++ pci_resource_len(pdev, 1) ); ++ } ++#endif //end #ifdef RTL_IO_MAP ++ ++fail: ++ if(dev){ ++ ++ if (priv->irq) { ++ free_irq(dev->irq, dev); ++ dev->irq=0; ++ } ++ free_ieee80211(dev); ++ } ++ ++ pci_disable_device(pdev); ++ ++ DMESG("wlan driver load failed\n"); ++ pci_set_drvdata(pdev, NULL); ++ return -ENODEV; ++ ++} ++ ++/* detach all the work and timer structure declared or inititialized ++ * in r8192_init function. ++ * */ ++void rtl8192_cancel_deferred_work(struct r8192_priv* priv) ++{ ++ /* call cancel_work_sync instead of cancel_delayed_work if and only if Linux_version_code ++ * is or is newer than 2.6.20 and work structure is defined to be struct work_struct. ++ * Otherwise call cancel_delayed_work is enough. ++ * FIXME (2.6.20 shoud 2.6.22, work_struct shoud not cancel) ++ * */ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ cancel_delayed_work(&priv->watch_dog_wq); ++ cancel_delayed_work(&priv->update_beacon_wq); ++ cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq); ++ cancel_delayed_work(&priv->ieee80211->hw_sleep_wq); ++#ifdef RTL8192E ++ cancel_delayed_work(&priv->gpio_change_rf_wq); ++#endif ++#endif ++#if LINUX_VERSION_CODE >=KERNEL_VERSION(2,6,22) ++ cancel_work_sync(&priv->reset_wq); ++ cancel_work_sync(&priv->qos_activate); ++ //cancel_work_sync(&priv->SetBWModeWorkItem); ++ //cancel_work_sync(&priv->SwChnlWorkItem); ++#else ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ cancel_delayed_work(&priv->reset_wq); ++ cancel_delayed_work(&priv->qos_activate); ++ //cancel_delayed_work(&priv->SetBWModeWorkItem); ++ //cancel_delayed_work(&priv->SwChnlWorkItem); ++#endif ++#endif ++ ++} ++ ++ ++static void __devexit rtl8192_pci_disconnect(struct pci_dev *pdev) ++{ ++ struct net_device *dev = pci_get_drvdata(pdev); ++ struct r8192_priv *priv ; ++ ++ if(dev){ ++ ++ unregister_netdev(dev); ++ ++ priv=ieee80211_priv(dev); ++ ++ rtl8192_proc_remove_one(dev); ++ ++ rtl8192_down(dev); ++ if (priv->pFirmware) ++ { ++ vfree(priv->pFirmware); ++ priv->pFirmware = NULL; ++ } ++ // priv->rf_close(dev); ++ // rtl8192_usb_deleteendpoints(dev); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ destroy_workqueue(priv->priv_wq); ++#endif ++ /* redundant with rtl8192_down */ ++ // rtl8192_irq_disable(dev); ++ // rtl8192_reset(dev); ++ // mdelay(10); ++ { ++ u32 i; ++ /* free tx/rx rings */ ++ rtl8192_free_rx_ring(dev); ++ for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) { ++ rtl8192_free_tx_ring(dev, i); ++ } ++ } ++ if(priv->irq){ ++ ++ printk("Freeing irq %d\n",dev->irq); ++ free_irq(dev->irq, dev); ++ priv->irq=0; ++ ++ } ++ ++ ++ ++ // free_beacon_desc_ring(dev,priv->txbeaconcount); ++ ++#ifdef CONFIG_RTL8180_IO_MAP ++ ++ if( dev->base_addr != 0 ){ ++ ++ release_region(dev->base_addr, ++ pci_resource_len(pdev, 0) ); ++ } ++#else ++ if( dev->mem_start != (unsigned long)NULL ){ ++ iounmap( (void *)dev->mem_start ); ++ release_mem_region( pci_resource_start(pdev, 1), ++ pci_resource_len(pdev, 1) ); ++ } ++#endif /*end #ifdef RTL_IO_MAP*/ ++ free_ieee80211(dev); ++ ++ } ++ ++ pci_disable_device(pdev); ++ RT_TRACE(COMP_DOWN, "wlan driver removed\n"); ++} ++ ++extern int ieee80211_init(void); ++extern void ieee80211_exit(void); ++ ++static int __init rtl8192_pci_module_init(void) ++{ ++ int retval; ++ ++ retval = ieee80211_init(); ++ if (retval) ++ return retval; ++ ++ printk(KERN_INFO "\nLinux kernel driver for RTL8192 based WLAN cards\n"); ++ printk(KERN_INFO "Copyright (c) 2007-2008, Realsil Wlan\n"); ++ RT_TRACE(COMP_INIT, "Initializing module"); ++ RT_TRACE(COMP_INIT, "Wireless extensions version %d", WIRELESS_EXT); ++ rtl8192_proc_module_init(); ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)) ++ if(0!=pci_module_init(&rtl8192_pci_driver)) ++#else ++ if(0!=pci_register_driver(&rtl8192_pci_driver)) ++#endif ++ { ++ DMESG("No device found"); ++ /*pci_unregister_driver (&rtl8192_pci_driver);*/ ++ return -ENODEV; ++ } ++ return 0; ++} ++ ++ ++static void __exit rtl8192_pci_module_exit(void) ++{ ++ pci_unregister_driver(&rtl8192_pci_driver); ++ ++ RT_TRACE(COMP_DOWN, "Exiting"); ++ rtl8192_proc_module_remove(); ++ ieee80211_exit(); ++} ++ ++//warning message WB ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++void rtl8192_interrupt(int irq, void *netdev, struct pt_regs *regs) ++#else ++irqreturn_t rtl8192_interrupt(int irq, void *netdev, struct pt_regs *regs) ++#endif ++#else ++irqreturn_t rtl8192_interrupt(int irq, void *netdev) ++#endif ++{ ++ struct net_device *dev = (struct net_device *) netdev; ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ unsigned long flags; ++ u32 inta; ++ /* We should return IRQ_NONE, but for now let me keep this */ ++ if(priv->irq_enabled == 0){ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++ return; ++#else ++ return IRQ_HANDLED; ++#endif ++ } ++ ++ spin_lock_irqsave(&priv->irq_th_lock,flags); ++ ++ //ISR: 4bytes ++ ++ inta = read_nic_dword(dev, ISR);// & priv->IntrMask; ++ write_nic_dword(dev,ISR,inta); // reset int situation ++ ++ priv->stats.shints++; ++ //DMESG("Enter interrupt, ISR value = 0x%08x", inta); ++ if(!inta){ ++ spin_unlock_irqrestore(&priv->irq_th_lock,flags); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++ return; ++#else ++ return IRQ_HANDLED; ++#endif ++ /* ++ most probably we can safely return IRQ_NONE, ++ but for now is better to avoid problems ++ */ ++ } ++ ++ if(inta == 0xffff){ ++ /* HW disappared */ ++ spin_unlock_irqrestore(&priv->irq_th_lock,flags); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++ return; ++#else ++ return IRQ_HANDLED; ++#endif ++ } ++ ++ priv->stats.ints++; ++#ifdef DEBUG_IRQ ++ DMESG("NIC irq %x",inta); ++#endif ++ //priv->irqpending = inta; ++ ++ ++ if(!netif_running(dev)) { ++ spin_unlock_irqrestore(&priv->irq_th_lock,flags); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++ return; ++#else ++ return IRQ_HANDLED; ++#endif ++ } ++ ++ if(inta & IMR_TIMEOUT0){ ++ // write_nic_dword(dev, TimerInt, 0); ++ //DMESG("=================>waking up"); ++ // rtl8180_hw_wakeup(dev); ++ } ++ ++ if(inta & IMR_TBDOK){ ++ RT_TRACE(COMP_INTR, "beacon ok interrupt!\n"); ++ rtl8192_tx_isr(dev, BEACON_QUEUE); ++ priv->stats.txbeaconokint++; ++ } ++ ++ if(inta & IMR_TBDER){ ++ RT_TRACE(COMP_INTR, "beacon ok interrupt!\n"); ++ rtl8192_tx_isr(dev, BEACON_QUEUE); ++ priv->stats.txbeaconerr++; ++ } ++ ++ if(inta & IMR_MGNTDOK ) { ++ RT_TRACE(COMP_INTR, "Manage ok interrupt!\n"); ++ priv->stats.txmanageokint++; ++ rtl8192_tx_isr(dev,MGNT_QUEUE); ++ ++ } ++ ++ if(inta & IMR_COMDOK) ++ { ++ priv->stats.txcmdpktokint++; ++ rtl8192_tx_isr(dev,TXCMD_QUEUE); ++ } ++ ++ if(inta & IMR_ROK){ ++#ifdef DEBUG_RX ++ DMESG("Frame arrived !"); ++#endif ++ priv->stats.rxint++; ++ tasklet_schedule(&priv->irq_rx_tasklet); ++ } ++ ++ if(inta & IMR_BcnInt) { ++ RT_TRACE(COMP_INTR, "prepare beacon for interrupt!\n"); ++ tasklet_schedule(&priv->irq_prepare_beacon_tasklet); ++ } ++ ++ if(inta & IMR_RDU){ ++ RT_TRACE(COMP_INTR, "rx descriptor unavailable!\n"); ++ priv->stats.rxrdu++; ++ /* reset int situation */ ++ write_nic_dword(dev,INTA_MASK,read_nic_dword(dev, INTA_MASK) & ~IMR_RDU); ++ tasklet_schedule(&priv->irq_rx_tasklet); ++ } ++ ++ if(inta & IMR_RXFOVW){ ++ RT_TRACE(COMP_INTR, "rx overflow !\n"); ++ priv->stats.rxoverflow++; ++ tasklet_schedule(&priv->irq_rx_tasklet); ++ } ++ ++ if(inta & IMR_TXFOVW) priv->stats.txoverflow++; ++ ++ if(inta & IMR_BKDOK){ ++ RT_TRACE(COMP_INTR, "BK Tx OK interrupt!\n"); ++ priv->stats.txbkokint++; ++ priv->ieee80211->LinkDetectInfo.NumTxOkInPeriod++; ++ rtl8192_tx_isr(dev,BK_QUEUE); ++ rtl8192_try_wake_queue(dev, BK_QUEUE); ++ } ++ ++ if(inta & IMR_BEDOK){ ++ RT_TRACE(COMP_INTR, "BE TX OK interrupt!\n"); ++ priv->stats.txbeokint++; ++ priv->ieee80211->LinkDetectInfo.NumTxOkInPeriod++; ++ rtl8192_tx_isr(dev,BE_QUEUE); ++ rtl8192_try_wake_queue(dev, BE_QUEUE); ++ } ++ ++ if(inta & IMR_VIDOK){ ++ RT_TRACE(COMP_INTR, "VI TX OK interrupt!\n"); ++ priv->stats.txviokint++; ++ priv->ieee80211->LinkDetectInfo.NumTxOkInPeriod++; ++ rtl8192_tx_isr(dev,VI_QUEUE); ++ rtl8192_try_wake_queue(dev, VI_QUEUE); ++ } ++ ++ if(inta & IMR_VODOK){ ++ priv->stats.txvookint++; ++ priv->ieee80211->LinkDetectInfo.NumTxOkInPeriod++; ++ rtl8192_tx_isr(dev,VO_QUEUE); ++ rtl8192_try_wake_queue(dev, VO_QUEUE); ++ } ++ ++ force_pci_posting(dev); ++ spin_unlock_irqrestore(&priv->irq_th_lock,flags); ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++ return; ++#else ++ return IRQ_HANDLED; ++#endif ++} ++ ++void rtl8192_try_wake_queue(struct net_device *dev, int pri) ++{ ++#if 0 ++ unsigned long flags; ++ short enough_desc; ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ ++ spin_lock_irqsave(&priv->tx_lock,flags); ++ enough_desc = check_nic_enough_desc(dev,pri); ++ spin_unlock_irqrestore(&priv->tx_lock,flags); ++ ++ if(enough_desc) ++ ieee80211_wake_queue(priv->ieee80211); ++#endif ++} ++ ++ ++void EnableHWSecurityConfig8192(struct net_device *dev) ++{ ++ u8 SECR_value = 0x0; ++ // struct ieee80211_device* ieee1 = container_of(&dev, struct ieee80211_device, dev); ++ //printk("==>ieee1:%p, dev:%p\n", ieee1, dev); ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ struct ieee80211_device* ieee = priv->ieee80211; ++ //printk("==>ieee:%p, dev:%p\n", ieee, dev); ++ SECR_value = SCR_TxEncEnable | SCR_RxDecEnable; ++#if 1 ++ if (((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) && (priv->ieee80211->auth_mode != 2)) ++ { ++ SECR_value |= SCR_RxUseDK; ++ SECR_value |= SCR_TxUseDK; ++ } ++ else if ((ieee->iw_mode == IW_MODE_ADHOC) && (ieee->pairwise_key_type & (KEY_TYPE_CCMP | KEY_TYPE_TKIP))) ++ { ++ SECR_value |= SCR_RxUseDK; ++ SECR_value |= SCR_TxUseDK; ++ } ++ ++#endif ++ ++ //add HWSec active enable here. ++//default using hwsec. when peer AP is in N mode only and pairwise_key_type is none_aes(which HT_IOT_ACT_PURE_N_MODE indicates it), use software security. when peer AP is in b,g,n mode mixed and pairwise_key_type is none_aes, use g mode hw security. WB on 2008.7.4 ++ ieee->hwsec_active = 1; ++ ++ if ((ieee->pHTInfo->IOTAction&HT_IOT_ACT_PURE_N_MODE) || !hwwep)//!ieee->hwsec_support) //add hwsec_support flag to totol control hw_sec on/off ++ { ++ ieee->hwsec_active = 0; ++ SECR_value &= ~SCR_RxDecEnable; ++ } ++ ++ RT_TRACE(COMP_SEC,"%s:, hwsec:%d, pairwise_key:%d, SECR_value:%x\n", __FUNCTION__, \ ++ ieee->hwsec_active, ieee->pairwise_key_type, SECR_value); ++ { ++ write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK ); ++ } ++ ++} ++#define TOTAL_CAM_ENTRY 32 ++//#define CAM_CONTENT_COUNT 8 ++void setKey( struct net_device *dev, ++ u8 EntryNo, ++ u8 KeyIndex, ++ u16 KeyType, ++ u8 *MacAddr, ++ u8 DefaultKey, ++ u32 *KeyContent ) ++{ ++ u32 TargetCommand = 0; ++ u32 TargetContent = 0; ++ u16 usConfig = 0; ++ u8 i; ++#ifdef ENABLE_IPS ++ struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); ++ RT_RF_POWER_STATE rtState; ++ rtState = priv->ieee80211->eRFPowerState; ++ if(priv->ieee80211->PowerSaveControl.bInactivePs){ ++ if(rtState == eRfOff){ ++ if(priv->ieee80211->RfOffReason > RF_CHANGE_BY_IPS) ++ { ++ RT_TRACE(COMP_ERR, "%s(): RF is OFF.\n",__FUNCTION__); ++ up(&priv->wx_sem); ++ return ; ++ } ++ else{ ++ IPSLeave(dev); ++ } ++ } ++ } ++ priv->ieee80211->is_set_key = true; ++#endif ++ if (EntryNo >= TOTAL_CAM_ENTRY) ++ RT_TRACE(COMP_ERR, "cam entry exceeds in setKey()\n"); ++ ++ RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d, KeyType:%d, MacAddr"MAC_FMT"\n", dev,EntryNo, KeyIndex, KeyType, MAC_ARG(MacAddr)); ++ ++ if (DefaultKey) ++ usConfig |= BIT15 | (KeyType<<2); ++ else ++ usConfig |= BIT15 | (KeyType<<2) | KeyIndex; ++// usConfig |= BIT15 | (KeyType<<2) | (DefaultKey<<5) | KeyIndex; ++ ++ ++ for(i=0 ; iafter set key, usconfig:%x\n", usConfig); ++} ++// This function seems not ready! WB ++void CamPrintDbgReg(struct net_device* dev) ++{ ++ unsigned long rvalue; ++ unsigned char ucValue; ++ write_nic_dword(dev, DCAM, 0x80000000); ++ msleep(40); ++ rvalue = read_nic_dword(dev, DCAM); //delay_ms(40); ++ RT_TRACE(COMP_SEC, " TX CAM=%8lX ",rvalue); ++ if((rvalue & 0x40000000) != 0x4000000) ++ RT_TRACE(COMP_SEC, "-->TX Key Not Found "); ++ msleep(20); ++ write_nic_dword(dev, DCAM, 0x00000000); //delay_ms(40); ++ rvalue = read_nic_dword(dev, DCAM); //delay_ms(40); ++ RT_TRACE(COMP_SEC, "RX CAM=%8lX ",rvalue); ++ if((rvalue & 0x40000000) != 0x4000000) ++ RT_TRACE(COMP_SEC, "-->CAM Key Not Found "); ++ ucValue = read_nic_byte(dev, SECR); ++ RT_TRACE(COMP_SEC, "WPA_Config=%x \n",ucValue); ++} ++ ++ ++/*************************************************************************** ++ ------------------- module init / exit stubs ---------------- ++****************************************************************************/ ++module_init(rtl8192_pci_module_init); ++module_exit(rtl8192_pci_module_exit); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r8192E_dm.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E_dm.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E_dm.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,4115 @@ ++/*++ ++Copyright-c Realtek Semiconductor Corp. All rights reserved. ++ ++Module Name: ++ r8192U_dm.c ++ ++Abstract: ++ HW dynamic mechanism. ++ ++Major Change History: ++ When Who What ++ ---------- --------------- ------------------------------- ++ 2008-05-14 amy create version 0 porting from windows code. ++ ++--*/ ++#include "r8192E.h" ++#include "r8192E_dm.h" ++#include "r8192E_hw.h" ++#include "r819xE_phy.h" ++#include "r819xE_phyreg.h" ++#include "r8190_rtl8256.h" ++/*---------------------------Define Local Constant---------------------------*/ ++// ++// Indicate different AP vendor for IOT issue. ++// ++#ifdef RTL8190P ++static u32 edca_setting_DL[HT_IOT_PEER_MAX] = ++{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322}; ++static u32 edca_setting_UL[HT_IOT_PEER_MAX] = ++{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322}; ++#else ++#ifdef RTL8192E ++static u32 edca_setting_DL[HT_IOT_PEER_MAX] = ++{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322}; ++static u32 edca_setting_UL[HT_IOT_PEER_MAX] = ++{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322}; ++#else ++static u32 edca_setting_DL[HT_IOT_PEER_MAX] = ++{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f}; ++static u32 edca_setting_UL[HT_IOT_PEER_MAX] = ++{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f}; ++#endif ++#endif ++ ++#define RTK_UL_EDCA 0xa44f ++#define RTK_DL_EDCA 0x5e4322 ++/*---------------------------Define Local Constant---------------------------*/ ++ ++ ++/*------------------------Define global variable-----------------------------*/ ++// Debug variable ? ++dig_t dm_digtable; ++// Store current shoftware write register content for MAC PHY. ++u8 dm_shadow[16][256] = {{0}}; ++// For Dynamic Rx Path Selection by Signal Strength ++DRxPathSel DM_RxPathSelTable; ++/*------------------------Define global variable-----------------------------*/ ++ ++ ++/*------------------------Define local variable------------------------------*/ ++/*------------------------Define local variable------------------------------*/ ++ ++ ++/*--------------------Define export function prototype-----------------------*/ ++extern void init_hal_dm(struct net_device *dev); ++extern void deinit_hal_dm(struct net_device *dev); ++ ++extern void hal_dm_watchdog(struct net_device *dev); ++ ++ ++extern void init_rate_adaptive(struct net_device *dev); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++extern void dm_txpower_trackingcallback(struct work_struct *work); ++#else ++extern void dm_txpower_trackingcallback(struct net_device *dev); ++#endif ++ ++extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14); ++extern void dm_restore_dynamic_mechanism_state(struct net_device *dev); ++extern void dm_backup_dynamic_mechanism_state(struct net_device *dev); ++extern void dm_change_dynamic_initgain_thresh(struct net_device *dev, ++ u32 dm_type, ++ u32 dm_value); ++extern void DM_ChangeFsyncSetting(struct net_device *dev, ++ s32 DM_Type, ++ s32 DM_Value); ++extern void dm_force_tx_fw_info(struct net_device *dev, ++ u32 force_type, ++ u32 force_value); ++extern void dm_init_edca_turbo(struct net_device *dev); ++extern void dm_rf_operation_test_callback(unsigned long data); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work); ++#else ++extern void dm_rf_pathcheck_workitemcallback(struct net_device *dev); ++#endif ++extern void dm_fsync_timer_callback(unsigned long data); ++#if 0 ++extern bool dm_check_lbus_status(struct net_device *dev); ++#endif ++extern void dm_check_fsync(struct net_device *dev); ++extern void dm_shadow_init(struct net_device *dev); ++extern void dm_initialize_txpower_tracking(struct net_device *dev); ++ ++#ifdef RTL8192E ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++extern void dm_gpio_change_rf_callback(struct work_struct *work); ++#else ++extern void dm_gpio_change_rf_callback(struct net_device *dev); ++#endif ++#endif ++ ++ ++ ++/*--------------------Define export function prototype-----------------------*/ ++ ++ ++/*---------------------Define local function prototype-----------------------*/ ++// DM --> Rate Adaptive ++static void dm_check_rate_adaptive(struct net_device *dev); ++ ++// DM --> Bandwidth switch ++static void dm_init_bandwidth_autoswitch(struct net_device *dev); ++static void dm_bandwidth_autoswitch( struct net_device *dev); ++ ++// DM --> TX power control ++//static void dm_initialize_txpower_tracking(struct net_device *dev); ++ ++static void dm_check_txpower_tracking(struct net_device *dev); ++ ++ ++ ++//static void dm_txpower_reset_recovery(struct net_device *dev); ++ ++ ++// DM --> BB init gain restore ++#ifndef RTL8192U ++static void dm_bb_initialgain_restore(struct net_device *dev); ++ ++ ++// DM --> BB init gain backup ++static void dm_bb_initialgain_backup(struct net_device *dev); ++#endif ++ ++// DM --> Dynamic Init Gain by RSSI ++static void dm_dig_init(struct net_device *dev); ++static void dm_ctrl_initgain_byrssi(struct net_device *dev); ++static void dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev); ++static void dm_ctrl_initgain_byrssi_by_driverrssi( struct net_device *dev); ++static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev); ++static void dm_initial_gain(struct net_device *dev); ++static void dm_pd_th(struct net_device *dev); ++static void dm_cs_ratio(struct net_device *dev); ++ ++static void dm_init_ctstoself(struct net_device *dev); ++// DM --> EDCA turboe mode control ++static void dm_check_edca_turbo(struct net_device *dev); ++ ++// DM --> HW RF control ++static void dm_check_rfctrl_gpio(struct net_device *dev); ++ ++#ifndef RTL8190P ++//static void dm_gpio_change_rf(struct net_device *dev); ++#endif ++// DM --> Check PBC ++static void dm_check_pbc_gpio(struct net_device *dev); ++ ++ ++// DM --> Check current RX RF path state ++static void dm_check_rx_path_selection(struct net_device *dev); ++static void dm_init_rxpath_selection(struct net_device *dev); ++static void dm_rxpath_sel_byrssi(struct net_device *dev); ++ ++ ++// DM --> Fsync for broadcom ap ++static void dm_init_fsync(struct net_device *dev); ++static void dm_deInit_fsync(struct net_device *dev); ++ ++//Added by vivi, 20080522 ++static void dm_check_txrateandretrycount(struct net_device *dev); ++ ++/*---------------------Define local function prototype-----------------------*/ ++ ++/*---------------------Define of Tx Power Control For Near/Far Range --------*/ //Add by Jacken 2008/02/18 ++static void dm_init_dynamic_txpower(struct net_device *dev); ++static void dm_dynamic_txpower(struct net_device *dev); ++ ++ ++// DM --> For rate adaptive and DIG, we must send RSSI to firmware ++static void dm_send_rssi_tofw(struct net_device *dev); ++static void dm_ctstoself(struct net_device *dev); ++/*---------------------------Define function prototype------------------------*/ ++//================================================================================ ++// HW Dynamic mechanism interface. ++//================================================================================ ++ ++// ++// Description: ++// Prepare SW resource for HW dynamic mechanism. ++// ++// Assumption: ++// This function is only invoked at driver intialization once. ++// ++// ++void init_hal_dm(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ // Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism. ++ priv->undecorated_smoothed_pwdb = -1; ++ ++ //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. ++ dm_init_dynamic_txpower(dev); ++ init_rate_adaptive(dev); ++ //dm_initialize_txpower_tracking(dev); ++ dm_dig_init(dev); ++ dm_init_edca_turbo(dev); ++ dm_init_bandwidth_autoswitch(dev); ++ dm_init_fsync(dev); ++ dm_init_rxpath_selection(dev); ++ dm_init_ctstoself(dev); ++#ifdef RTL8192E ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++ INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, dm_gpio_change_rf_callback); ++#else ++ INIT_WORK(&priv->gpio_change_rf_wq, (void(*)(void*)) dm_gpio_change_rf_callback,dev); ++#endif ++#endif ++ ++} // InitHalDm ++ ++void deinit_hal_dm(struct net_device *dev) ++{ ++ ++ dm_deInit_fsync(dev); ++ ++} ++ ++ ++#ifdef USB_RX_AGGREGATION_SUPPORT ++void dm_CheckRxAggregation(struct net_device *dev) { ++ struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev); ++ PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; ++ static unsigned long lastTxOkCnt = 0; ++ static unsigned long lastRxOkCnt = 0; ++ unsigned long curTxOkCnt = 0; ++ unsigned long curRxOkCnt = 0; ++ ++/* ++ if (pHalData->bForcedUsbRxAggr) { ++ if (pHalData->ForcedUsbRxAggrInfo == 0) { ++ if (pHalData->bCurrentRxAggrEnable) { ++ Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE); ++ } ++ } else { ++ if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) { ++ Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE); ++ } ++ } ++ return; ++ } ++ ++*/ ++ curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; ++ curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; ++ ++ if((curTxOkCnt + curRxOkCnt) < 15000000) { ++ return; ++ } ++ ++ if(curTxOkCnt > 4*curRxOkCnt) { ++ if (priv->bCurrentRxAggrEnable) { ++ write_nic_dword(dev, 0x1a8, 0); ++ priv->bCurrentRxAggrEnable = false; ++ } ++ }else{ ++ if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) { ++ u32 ulValue; ++ ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) | ++ (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout); ++ /* ++ * If usb rx firmware aggregation is enabled, ++ * when anyone of three threshold conditions above is reached, ++ * firmware will send aggregated packet to driver. ++ */ ++ write_nic_dword(dev, 0x1a8, ulValue); ++ priv->bCurrentRxAggrEnable = true; ++ } ++ } ++ ++ lastTxOkCnt = priv->stats.txbytesunicast; ++ lastRxOkCnt = priv->stats.rxbytesunicast; ++} // dm_CheckEdcaTurbo ++#endif ++ ++ ++ ++void hal_dm_watchdog(struct net_device *dev) ++{ ++ //struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ //static u8 previous_bssid[6] ={0}; ++ ++ /*Add by amy 2008/05/15 ,porting from windows code.*/ ++ dm_check_rate_adaptive(dev); ++ dm_dynamic_txpower(dev); ++ dm_check_txrateandretrycount(dev); ++ ++ dm_check_txpower_tracking(dev); ++ ++ dm_ctrl_initgain_byrssi(dev); ++ dm_check_edca_turbo(dev); ++ dm_bandwidth_autoswitch(dev); ++ ++ dm_check_rfctrl_gpio(dev); ++ dm_check_rx_path_selection(dev); ++ dm_check_fsync(dev); ++ ++ // Add by amy 2008-05-15 porting from windows code. ++ dm_check_pbc_gpio(dev); ++ dm_send_rssi_tofw(dev); ++ dm_ctstoself(dev); ++ ++#ifdef USB_RX_AGGREGATION_SUPPORT ++ dm_CheckRxAggregation(dev); ++#endif ++} //HalDmWatchDog ++ ++ ++/* ++ * Decide Rate Adaptive Set according to distance (signal strength) ++ * 01/11/2008 MHC Modify input arguments and RATR table level. ++ * 01/16/2008 MHC RF_Type is assigned in ReadAdapterInfo(). We must call ++ * the function after making sure RF_Type. ++ */ ++void init_rate_adaptive(struct net_device * dev) ++{ ++ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive; ++ ++ pra->ratr_state = DM_RATR_STA_MAX; ++ pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High; ++ pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5; ++ pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5; ++ ++ pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5; ++ pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M; ++ pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M; ++ ++ if(priv->CustomerID == RT_CID_819x_Netcore) ++ pra->ping_rssi_enable = 1; ++ else ++ pra->ping_rssi_enable = 0; ++ pra->ping_rssi_thresh_for_ra = 15; ++ ++ ++ if (priv->rf_type == RF_2T4R) ++ { ++ // 07/10/08 MH Modify for RA smooth scheme. ++ /* 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.*/ ++ pra->upper_rssi_threshold_ratr = 0x8f0f0000; ++ pra->middle_rssi_threshold_ratr = 0x8f0ff000; ++ pra->low_rssi_threshold_ratr = 0x8f0ff001; ++ pra->low_rssi_threshold_ratr_40M = 0x8f0ff005; ++ pra->low_rssi_threshold_ratr_20M = 0x8f0ff001; ++ pra->ping_rssi_ratr = 0x0000000d;//cosa add for test ++ } ++ else if (priv->rf_type == RF_1T2R) ++ { ++ pra->upper_rssi_threshold_ratr = 0x000f0000; ++ pra->middle_rssi_threshold_ratr = 0x000ff000; ++ pra->low_rssi_threshold_ratr = 0x000ff001; ++ pra->low_rssi_threshold_ratr_40M = 0x000ff005; ++ pra->low_rssi_threshold_ratr_20M = 0x000ff001; ++ pra->ping_rssi_ratr = 0x0000000d;//cosa add for test ++ } ++ ++} // InitRateAdaptive ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: dm_check_rate_adaptive() ++ * ++ * Overview: ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/26/08 amy Create version 0 proting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++static void dm_check_rate_adaptive(struct net_device * dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; ++ prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive; ++ u32 currentRATR, targetRATR = 0; ++ u32 LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0; ++ bool bshort_gi_enabled = false; ++ static u8 ping_rssi_state=0; ++ ++ ++ if(!priv->up) ++ { ++ RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n"); ++ return; ++ } ++ ++ if(pra->rate_adaptive_disabled)//this variable is set by ioctl. ++ return; ++ ++ // TODO: Only 11n mode is implemented currently, ++ if( !(priv->ieee80211->mode == WIRELESS_MODE_N_24G || ++ priv->ieee80211->mode == WIRELESS_MODE_N_5G)) ++ return; ++ ++ if( priv->ieee80211->state == IEEE80211_LINKED ) ++ { ++ // RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t"); ++ ++ // ++ // Check whether Short GI is enabled ++ // ++ bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) || ++ (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz); ++ ++ ++ pra->upper_rssi_threshold_ratr = ++ (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; ++ ++ pra->middle_rssi_threshold_ratr = ++ (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; ++ ++ if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ++ { ++ pra->low_rssi_threshold_ratr = ++ (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; ++ } ++ else ++ { ++ pra->low_rssi_threshold_ratr = ++ (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; ++ } ++ //cosa add for test ++ pra->ping_rssi_ratr = ++ (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; ++ ++ /* 2007/10/08 MH We support RA smooth scheme now. When it is the first ++ time to link with AP. We will not change upper/lower threshold. If ++ STA stay in high or low level, we must change two different threshold ++ to prevent jumping frequently. */ ++ if (pra->ratr_state == DM_RATR_STA_HIGH) ++ { ++ HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra; ++ LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)? ++ (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M); ++ } ++ else if (pra->ratr_state == DM_RATR_STA_LOW) ++ { ++ HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra; ++ LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)? ++ (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M); ++ } ++ else ++ { ++ HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra; ++ LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)? ++ (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M); ++ } ++ ++ //DbgPrint("[DM] THresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA); ++ if(priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA) ++ { ++ //DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB); ++ pra->ratr_state = DM_RATR_STA_HIGH; ++ targetRATR = pra->upper_rssi_threshold_ratr; ++ }else if(priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA) ++ { ++ //DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB); ++ pra->ratr_state = DM_RATR_STA_MIDDLE; ++ targetRATR = pra->middle_rssi_threshold_ratr; ++ }else ++ { ++ //DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB); ++ pra->ratr_state = DM_RATR_STA_LOW; ++ targetRATR = pra->low_rssi_threshold_ratr; ++ } ++ ++ //cosa add for test ++ if(pra->ping_rssi_enable) ++ { ++ //pHalData->UndecoratedSmoothedPWDB = 19; ++ if(priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5)) ++ { ++ if( (priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) || ++ ping_rssi_state ) ++ { ++ //DbgPrint("TestRSSI = %d, set RATR to 0x%x \n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR); ++ pra->ratr_state = DM_RATR_STA_LOW; ++ targetRATR = pra->ping_rssi_ratr; ++ ping_rssi_state = 1; ++ } ++ //else ++ // DbgPrint("TestRSSI is between the range. \n"); ++ } ++ else ++ { ++ //DbgPrint("TestRSSI Recover to 0x%x \n", targetRATR); ++ ping_rssi_state = 0; ++ } ++ } ++ ++ // 2008.04.01 ++#if 1 ++ // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7. ++ if(priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev)) ++ targetRATR &= 0xf00fffff; ++#endif ++ ++ // ++ // Check whether updating of RATR0 is required ++ // ++ currentRATR = read_nic_dword(dev, RATR0); ++ if( targetRATR != currentRATR ) ++ { ++ u32 ratr_value; ++ ratr_value = targetRATR; ++ RT_TRACE(COMP_RATE,"currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR); ++ if(priv->rf_type == RF_1T2R) ++ { ++ ratr_value &= ~(RATE_ALL_OFDM_2SS); ++ } ++ write_nic_dword(dev, RATR0, ratr_value); ++ write_nic_byte(dev, UFWP, 1); ++ ++ pra->last_ratr = targetRATR; ++ } ++ ++ } ++ else ++ { ++ pra->ratr_state = DM_RATR_STA_MAX; ++ } ++ ++} // dm_CheckRateAdaptive ++ ++ ++static void dm_init_bandwidth_autoswitch(struct net_device * dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH; ++ priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW; ++ priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false; ++ priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false; ++ ++} // dm_init_bandwidth_autoswitch ++ ++ ++static void dm_bandwidth_autoswitch(struct net_device * dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ||!priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable){ ++ return; ++ }else{ ++ if(priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz == false){//If send packets in 40 Mhz in 20/40 ++ if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz) ++ priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true; ++ }else{//in force send packets in 20 Mhz in 20/40 ++ if(priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz) ++ priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false; ++ ++ } ++ } ++} // dm_BandwidthAutoSwitch ++ ++//OFDM default at 0db, index=6. ++#ifndef RTL8190P ++static u32 OFDMSwingTable[OFDM_Table_Length] = { ++ 0x7f8001fe, // 0, +6db ++ 0x71c001c7, // 1, +5db ++ 0x65400195, // 2, +4db ++ 0x5a400169, // 3, +3db ++ 0x50800142, // 4, +2db ++ 0x47c0011f, // 5, +1db ++ 0x40000100, // 6, +0db ===> default, upper for higher temprature, lower for low temprature ++ 0x390000e4, // 7, -1db ++ 0x32c000cb, // 8, -2db ++ 0x2d4000b5, // 9, -3db ++ 0x288000a2, // 10, -4db ++ 0x24000090, // 11, -5db ++ 0x20000080, // 12, -6db ++ 0x1c800072, // 13, -7db ++ 0x19800066, // 14, -8db ++ 0x26c0005b, // 15, -9db ++ 0x24400051, // 16, -10db ++ 0x12000048, // 17, -11db ++ 0x10000040 // 18, -12db ++}; ++static u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = { ++ {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0db ===> CCK40M default ++ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 1, -1db ++ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 2, -2db ++ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 3, -3db ++ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 4, -4db ++ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 5, -5db ++ {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 6, -6db ===> CCK20M default ++ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 7, -7db ++ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 8, -8db ++ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 9, -9db ++ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 10, -10db ++ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} // 11, -11db ++}; ++ ++static u8 CCKSwingTable_Ch14[CCK_Table_length][8] = { ++ {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0db ===> CCK40M default ++ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 1, -1db ++ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 2, -2db ++ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 3, -3db ++ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 4, -4db ++ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 5, -5db ++ {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 6, -6db ===> CCK20M default ++ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 7, -7db ++ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 8, -8db ++ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 9, -9db ++ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 10, -10db ++ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} // 11, -11db ++}; ++#endif ++#define Pw_Track_Flag 0x11d ++#define Tssi_Mea_Value 0x13c ++#define Tssi_Report_Value1 0x134 ++#define Tssi_Report_Value2 0x13e ++#define FW_Busy_Flag 0x13f ++static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev) ++ { ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ bool bHighpowerstate, viviflag = FALSE; ++ DCMD_TXCMD_T tx_cmd; ++ u8 powerlevelOFDM24G; ++ int i =0, j = 0, k = 0; ++ u8 RF_Type, tmp_report[5]={0, 0, 0, 0, 0}; ++ u32 Value; ++ u8 Pwr_Flag; ++ u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver=0; ++#ifdef RTL8192U ++ RT_STATUS rtStatus = RT_STATUS_SUCCESS; ++#endif ++// bool rtStatus = true; ++ u32 delta=0; ++ RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__); ++// write_nic_byte(dev, 0x1ba, 0); ++ write_nic_byte(dev, Pw_Track_Flag, 0); ++ write_nic_byte(dev, FW_Busy_Flag, 0); ++ priv->ieee80211->bdynamic_txpower_enable = false; ++ bHighpowerstate = priv->bDynamicTxHighPower; ++ ++ powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24); ++ RF_Type = priv->rf_type; ++ Value = (RF_Type<<8) | powerlevelOFDM24G; ++ ++ RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G); ++ ++ for(j = 0; j<=30; j++) ++{ //fill tx_cmd ++ ++ tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING; ++ tx_cmd.Length = 4; ++ tx_cmd.Value = Value; ++#ifdef RTL8192U ++ rtStatus = SendTxCommandPacket(dev, &tx_cmd, 12); ++ if (rtStatus == RT_STATUS_FAILURE) ++ { ++ RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n"); ++ } ++#else ++ cmpk_message_handle_tx(dev, (u8*)&tx_cmd, DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T)); ++#endif ++ mdelay(1); ++ //DbgPrint("hi, vivi, strange\n"); ++ for(i = 0;i <= 30; i++) ++ { ++ Pwr_Flag = read_nic_byte(dev, Pw_Track_Flag); ++ ++ if (Pwr_Flag == 0) ++ { ++ mdelay(1); ++ continue; ++ } ++ ++ Avg_TSSI_Meas = read_nic_word(dev, Tssi_Mea_Value); ++ ++ if(Avg_TSSI_Meas == 0) ++ { ++ write_nic_byte(dev, Pw_Track_Flag, 0); ++ write_nic_byte(dev, FW_Busy_Flag, 0); ++ return; ++ } ++ ++ for(k = 0;k < 5; k++) ++ { ++ if(k !=4) ++ tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value1+k); ++ else ++ tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value2); ++ ++ RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]); ++ } ++ ++ //check if the report value is right ++ for(k = 0;k < 5; k++) ++ { ++ if(tmp_report[k] <= 20) ++ { ++ viviflag =TRUE; ++ break; ++ } ++ } ++ if(viviflag ==TRUE) ++ { ++ write_nic_byte(dev, Pw_Track_Flag, 0); ++ viviflag = FALSE; ++ RT_TRACE(COMP_POWER_TRACKING, "we filted this data\n"); ++ for(k = 0;k < 5; k++) ++ tmp_report[k] = 0; ++ break; ++ } ++ ++ for(k = 0;k < 5; k++) ++ { ++ Avg_TSSI_Meas_from_driver += tmp_report[k]; ++ } ++ ++ Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5; ++ RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver); ++ TSSI_13dBm = priv->TSSI_13dBm; ++ RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm); ++ ++ //if(abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK) ++ // For MacOS-compatible ++ if(Avg_TSSI_Meas_from_driver > TSSI_13dBm) ++ delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm; ++ else ++ delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver; ++ ++ if(delta <= E_FOR_TX_POWER_TRACK) ++ { ++ priv->ieee80211->bdynamic_txpower_enable = TRUE; ++ write_nic_byte(dev, Pw_Track_Flag, 0); ++ write_nic_byte(dev, FW_Busy_Flag, 0); ++ RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n"); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real); ++#ifdef RTL8190P ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real); ++#endif ++ RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation); ++ return; ++ } ++ else ++ { ++ if(Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK) ++ { ++ if (RF_Type == RF_2T4R) ++ { ++ ++ if((priv->rfa_txpowertrackingindex > 0) &&(priv->rfc_txpowertrackingindex > 0)) ++ { ++ priv->rfa_txpowertrackingindex--; ++ if(priv->rfa_txpowertrackingindex_real > 4) ++ { ++ priv->rfa_txpowertrackingindex_real--; ++ rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); ++ } ++ ++ priv->rfc_txpowertrackingindex--; ++ if(priv->rfc_txpowertrackingindex_real > 4) ++ { ++ priv->rfc_txpowertrackingindex_real--; ++ rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value); ++ } ++ } ++ else ++ { ++ rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value); ++ rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value); ++ } ++ } ++ else ++ { ++ if(priv->rfc_txpowertrackingindex > 0) ++ { ++ priv->rfc_txpowertrackingindex--; ++ if(priv->rfc_txpowertrackingindex_real > 4) ++ { ++ priv->rfc_txpowertrackingindex_real--; ++ rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value); ++ } ++ } ++ else ++ rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value); ++ } ++ } ++ else ++ { ++ if (RF_Type == RF_2T4R) ++ { ++ if((priv->rfa_txpowertrackingindex < TxBBGainTableLength - 1) &&(priv->rfc_txpowertrackingindex < TxBBGainTableLength - 1)) ++ { ++ priv->rfa_txpowertrackingindex++; ++ priv->rfa_txpowertrackingindex_real++; ++ rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); ++ priv->rfc_txpowertrackingindex++; ++ priv->rfc_txpowertrackingindex_real++; ++ rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value); ++ } ++ else ++ { ++ rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value); ++ rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value); ++ } ++ } ++ else ++ { ++ if(priv->rfc_txpowertrackingindex < (TxBBGainTableLength - 1)) ++ { ++ priv->rfc_txpowertrackingindex++; ++ priv->rfc_txpowertrackingindex_real++; ++ rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value); ++ } ++ else ++ rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value); ++ } ++ } ++ if (RF_Type == RF_2T4R) ++ priv->CCKPresentAttentuation_difference ++ = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default; ++ else ++ priv->CCKPresentAttentuation_difference ++ = priv->rfc_txpowertrackingindex - priv->rfc_txpowertracking_default; ++ ++ if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) ++ priv->CCKPresentAttentuation ++ = priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference; ++ else ++ priv->CCKPresentAttentuation ++ = priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference; ++ ++ if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1)) ++ priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1; ++ if(priv->CCKPresentAttentuation < 0) ++ priv->CCKPresentAttentuation = 0; ++ ++ if(1) ++ { ++ if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) ++ { ++ priv->bcck_in_ch14 = TRUE; ++ dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); ++ } ++ else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) ++ { ++ priv->bcck_in_ch14 = FALSE; ++ dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); ++ } ++ else ++ dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); ++ } ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real); ++#ifdef RTL8190P ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real); ++#endif ++ RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference); ++ RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation); ++ ++ if (priv->CCKPresentAttentuation_difference <= -12||priv->CCKPresentAttentuation_difference >= 24) ++ { ++ priv->ieee80211->bdynamic_txpower_enable = TRUE; ++ write_nic_byte(dev, Pw_Track_Flag, 0); ++ write_nic_byte(dev, FW_Busy_Flag, 0); ++ RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n"); ++ return; ++ } ++ ++ ++ } ++ write_nic_byte(dev, Pw_Track_Flag, 0); ++ Avg_TSSI_Meas_from_driver = 0; ++ for(k = 0;k < 5; k++) ++ tmp_report[k] = 0; ++ break; ++ } ++ write_nic_byte(dev, FW_Busy_Flag, 0); ++} ++ priv->ieee80211->bdynamic_txpower_enable = TRUE; ++ write_nic_byte(dev, Pw_Track_Flag, 0); ++} ++#ifndef RTL8190P ++static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev) ++{ ++#define ThermalMeterVal 9 ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u32 tmpRegA, TempCCk; ++ u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval; ++ int i =0, CCKSwingNeedUpdate=0; ++ ++ if(!priv->btxpower_trackingInit) ++ { ++ //Query OFDM default setting ++ tmpRegA= rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord); ++ for(i=0; iOFDM_index= (u8)i; ++ RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n", ++ rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index); ++ } ++ } ++ ++ //Query CCK default setting From 0xa22 ++ TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2); ++ for(i=0 ; iCCK_index =(u8) i; ++ RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n", ++ rCCK0_TxFilter1, TempCCk, priv->CCK_index); ++ break; ++ } ++} ++ priv->btxpower_trackingInit = TRUE; ++ //pHalData->TXPowercount = 0; ++ return; ++ } ++ ++ //========================== ++ // this is only for test, should be masked ++#if 0 ++{ ++ //UINT32 eRFPath; ++ //UINT32 start_rf, end_rf; ++ UINT32 curr_addr; ++ //UINT32 reg_addr; ++ //UINT32 reg_addr_end; ++ UINT32 reg_value; ++ //start_rf = RF90_PATH_A; ++ //end_rf = RF90_PATH_B;//RF90_PATH_MAX; ++ //reg_addr = 0x0; ++ //reg_addr_end = 0x2F; ++ ++ for (curr_addr = 0; curr_addr < 0x2d; curr_addr++) ++ { ++ reg_value = PHY_QueryRFReg( Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, ++ curr_addr, bMaskDWord); ++ } ++ ++ pHalData->TXPowercount = 0; ++ return; ++} ++#endif ++ //========================== ++ ++ // read and filter out unreasonable value ++ tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7] ++ RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d \n", tmpRegA); ++ if(tmpRegA < 3 || tmpRegA > 13) ++ return; ++ if(tmpRegA >= 12) // if over 12, TP will be bad when high temprature ++ tmpRegA = 12; ++ RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d \n", tmpRegA); ++ priv->ThermalMeter[0] = ThermalMeterVal; //We use fixed value by Bryant's suggestion ++ priv->ThermalMeter[1] = ThermalMeterVal; //We use fixed value by Bryant's suggestion ++ ++ //Get current RF-A temprature index ++ if(priv->ThermalMeter[0] >= (u8)tmpRegA) //lower temprature ++ { ++ tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA); ++ tmpCCK40Mindex = tmpCCK20Mindex - 6; ++ if(tmpOFDMindex >= OFDM_Table_Length) ++ tmpOFDMindex = OFDM_Table_Length-1; ++ if(tmpCCK20Mindex >= CCK_Table_length) ++ tmpCCK20Mindex = CCK_Table_length-1; ++ if(tmpCCK40Mindex >= CCK_Table_length) ++ tmpCCK40Mindex = CCK_Table_length-1; ++ } ++ else ++ { ++ tmpval = ((u8)tmpRegA - priv->ThermalMeter[0]); ++ if(tmpval >= 6) // higher temprature ++ tmpOFDMindex = tmpCCK20Mindex = 0; // max to +6dB ++ else ++ tmpOFDMindex = tmpCCK20Mindex = 6 - tmpval; ++ tmpCCK40Mindex = 0; ++ } ++ //DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d", ++ //((u1Byte)tmpRegA - pHalData->ThermalMeter[0]), ++ //tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex); ++ if(priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) //40M ++ tmpCCKindex = tmpCCK40Mindex; ++ else ++ tmpCCKindex = tmpCCK20Mindex; ++ ++ //record for bandwidth swith ++ priv->Record_CCK_20Mindex = tmpCCK20Mindex; ++ priv->Record_CCK_40Mindex = tmpCCK40Mindex; ++ RT_TRACE(COMP_POWER_TRACKING, "Record_CCK_20Mindex / Record_CCK_40Mindex = %d / %d.\n", ++ priv->Record_CCK_20Mindex, priv->Record_CCK_40Mindex); ++ ++ if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) ++ { ++ priv->bcck_in_ch14 = TRUE; ++ CCKSwingNeedUpdate = 1; ++ } ++ else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) ++ { ++ priv->bcck_in_ch14 = FALSE; ++ CCKSwingNeedUpdate = 1; ++ } ++ ++ if(priv->CCK_index != tmpCCKindex) ++{ ++ priv->CCK_index = tmpCCKindex; ++ CCKSwingNeedUpdate = 1; ++ } ++ ++ if(CCKSwingNeedUpdate) ++ { ++ //DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index); ++ dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); ++ } ++ if(priv->OFDM_index != tmpOFDMindex) ++ { ++ priv->OFDM_index = tmpOFDMindex; ++ rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]); ++ RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n", ++ priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]); ++ } ++ priv->txpower_count = 0; ++} ++#endif ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void dm_txpower_trackingcallback(struct work_struct *work) ++{ ++ struct delayed_work *dwork = container_of(work,struct delayed_work,work); ++ struct r8192_priv *priv = container_of(dwork,struct r8192_priv,txpower_tracking_wq); ++ struct net_device *dev = priv->ieee80211->dev; ++#else ++extern void dm_txpower_trackingcallback(struct net_device *dev) ++{ ++#ifndef RTL8190P ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#endif ++#endif ++ ++#ifdef RTL8190P ++ dm_TXPowerTrackingCallback_TSSI(dev); ++#else ++ //if(priv->bDcut == TRUE) ++ if(priv->IC_Cut >= IC_VersionCut_D) ++ dm_TXPowerTrackingCallback_TSSI(dev); ++ else ++ dm_TXPowerTrackingCallback_ThermalMeter(dev); ++#endif ++} ++ ++ ++static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev) ++{ ++ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ //Initial the Tx BB index and mapping value ++ priv->txbbgain_table[0].txbb_iq_amplifygain = 12; ++ priv->txbbgain_table[0].txbbgain_value=0x7f8001fe; ++ priv->txbbgain_table[1].txbb_iq_amplifygain = 11; ++ priv->txbbgain_table[1].txbbgain_value=0x788001e2; ++ priv->txbbgain_table[2].txbb_iq_amplifygain = 10; ++ priv->txbbgain_table[2].txbbgain_value=0x71c001c7; ++ priv->txbbgain_table[3].txbb_iq_amplifygain = 9; ++ priv->txbbgain_table[3].txbbgain_value=0x6b8001ae; ++ priv->txbbgain_table[4].txbb_iq_amplifygain = 8; ++ priv->txbbgain_table[4].txbbgain_value=0x65400195; ++ priv->txbbgain_table[5].txbb_iq_amplifygain = 7; ++ priv->txbbgain_table[5].txbbgain_value=0x5fc0017f; ++ priv->txbbgain_table[6].txbb_iq_amplifygain = 6; ++ priv->txbbgain_table[6].txbbgain_value=0x5a400169; ++ priv->txbbgain_table[7].txbb_iq_amplifygain = 5; ++ priv->txbbgain_table[7].txbbgain_value=0x55400155; ++ priv->txbbgain_table[8].txbb_iq_amplifygain = 4; ++ priv->txbbgain_table[8].txbbgain_value=0x50800142; ++ priv->txbbgain_table[9].txbb_iq_amplifygain = 3; ++ priv->txbbgain_table[9].txbbgain_value=0x4c000130; ++ priv->txbbgain_table[10].txbb_iq_amplifygain = 2; ++ priv->txbbgain_table[10].txbbgain_value=0x47c0011f; ++ priv->txbbgain_table[11].txbb_iq_amplifygain = 1; ++ priv->txbbgain_table[11].txbbgain_value=0x43c0010f; ++ priv->txbbgain_table[12].txbb_iq_amplifygain = 0; ++ priv->txbbgain_table[12].txbbgain_value=0x40000100; ++ priv->txbbgain_table[13].txbb_iq_amplifygain = -1; ++ priv->txbbgain_table[13].txbbgain_value=0x3c8000f2; ++ priv->txbbgain_table[14].txbb_iq_amplifygain = -2; ++ priv->txbbgain_table[14].txbbgain_value=0x390000e4; ++ priv->txbbgain_table[15].txbb_iq_amplifygain = -3; ++ priv->txbbgain_table[15].txbbgain_value=0x35c000d7; ++ priv->txbbgain_table[16].txbb_iq_amplifygain = -4; ++ priv->txbbgain_table[16].txbbgain_value=0x32c000cb; ++ priv->txbbgain_table[17].txbb_iq_amplifygain = -5; ++ priv->txbbgain_table[17].txbbgain_value=0x300000c0; ++ priv->txbbgain_table[18].txbb_iq_amplifygain = -6; ++ priv->txbbgain_table[18].txbbgain_value=0x2d4000b5; ++ priv->txbbgain_table[19].txbb_iq_amplifygain = -7; ++ priv->txbbgain_table[19].txbbgain_value=0x2ac000ab; ++ priv->txbbgain_table[20].txbb_iq_amplifygain = -8; ++ priv->txbbgain_table[20].txbbgain_value=0x288000a2; ++ priv->txbbgain_table[21].txbb_iq_amplifygain = -9; ++ priv->txbbgain_table[21].txbbgain_value=0x26000098; ++ priv->txbbgain_table[22].txbb_iq_amplifygain = -10; ++ priv->txbbgain_table[22].txbbgain_value=0x24000090; ++ priv->txbbgain_table[23].txbb_iq_amplifygain = -11; ++ priv->txbbgain_table[23].txbbgain_value=0x22000088; ++ priv->txbbgain_table[24].txbb_iq_amplifygain = -12; ++ priv->txbbgain_table[24].txbbgain_value=0x20000080; ++ priv->txbbgain_table[25].txbb_iq_amplifygain = -13; ++ priv->txbbgain_table[25].txbbgain_value=0x1a00006c; ++ priv->txbbgain_table[26].txbb_iq_amplifygain = -14; ++ priv->txbbgain_table[26].txbbgain_value=0x1c800072; ++ priv->txbbgain_table[27].txbb_iq_amplifygain = -15; ++ priv->txbbgain_table[27].txbbgain_value=0x18000060; ++ priv->txbbgain_table[28].txbb_iq_amplifygain = -16; ++ priv->txbbgain_table[28].txbbgain_value=0x19800066; ++ priv->txbbgain_table[29].txbb_iq_amplifygain = -17; ++ priv->txbbgain_table[29].txbbgain_value=0x15800056; ++ priv->txbbgain_table[30].txbb_iq_amplifygain = -18; ++ priv->txbbgain_table[30].txbbgain_value=0x26c0005b; ++ priv->txbbgain_table[31].txbb_iq_amplifygain = -19; ++ priv->txbbgain_table[31].txbbgain_value=0x14400051; ++ priv->txbbgain_table[32].txbb_iq_amplifygain = -20; ++ priv->txbbgain_table[32].txbbgain_value=0x24400051; ++ priv->txbbgain_table[33].txbb_iq_amplifygain = -21; ++ priv->txbbgain_table[33].txbbgain_value=0x1300004c; ++ priv->txbbgain_table[34].txbb_iq_amplifygain = -22; ++ priv->txbbgain_table[34].txbbgain_value=0x12000048; ++ priv->txbbgain_table[35].txbb_iq_amplifygain = -23; ++ priv->txbbgain_table[35].txbbgain_value=0x11000044; ++ priv->txbbgain_table[36].txbb_iq_amplifygain = -24; ++ priv->txbbgain_table[36].txbbgain_value=0x10000040; ++ ++ //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29 ++ //This Table is for CH1~CH13 ++ priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36; ++ priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35; ++ priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e; ++ priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25; ++ priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c; ++ priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12; ++ priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09; ++ priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04; ++ ++ priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33; ++ priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32; ++ priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b; ++ priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23; ++ priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a; ++ priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11; ++ priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08; ++ priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04; ++ ++ priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30; ++ priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f; ++ priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29; ++ priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21; ++ priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19; ++ priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10; ++ priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08; ++ priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03; ++ ++ priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d; ++ priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d; ++ priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27; ++ priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f; ++ priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18; ++ priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f; ++ priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08; ++ priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03; ++ ++ priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b; ++ priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a; ++ priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25; ++ priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e; ++ priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16; ++ priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e; ++ priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07; ++ priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03; ++ ++ priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28; ++ priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28; ++ priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22; ++ priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c; ++ priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15; ++ priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d; ++ priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07; ++ priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03; ++ ++ priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26; ++ priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25; ++ priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21; ++ priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b; ++ priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14; ++ priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d; ++ priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06; ++ priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03; ++ ++ priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24; ++ priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23; ++ priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f; ++ priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19; ++ priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13; ++ priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c; ++ priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06; ++ priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03; ++ ++ priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22; ++ priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21; ++ priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d; ++ priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18; ++ priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11; ++ priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b; ++ priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06; ++ priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02; ++ ++ priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20; ++ priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20; ++ priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b; ++ priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16; ++ priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11; ++ priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08; ++ priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05; ++ priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02; ++ ++ priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f; ++ priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e; ++ priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a; ++ priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15; ++ priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10; ++ priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a; ++ priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05; ++ priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02; ++ ++ priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d; ++ priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c; ++ priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18; ++ priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14; ++ priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f; ++ priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a; ++ priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05; ++ priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02; ++ ++ priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b; ++ priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a; ++ priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17; ++ priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13; ++ priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e; ++ priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09; ++ priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04; ++ priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02; ++ ++ priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a; ++ priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19; ++ priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16; ++ priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12; ++ priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d; ++ priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09; ++ priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04; ++ priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02; ++ ++ priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18; ++ priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17; ++ priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15; ++ priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11; ++ priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c; ++ priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08; ++ priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04; ++ priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02; ++ ++ priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17; ++ priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16; ++ priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13; ++ priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10; ++ priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c; ++ priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08; ++ priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04; ++ priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02; ++ ++ priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16; ++ priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15; ++ priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12; ++ priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f; ++ priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b; ++ priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07; ++ priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04; ++ priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01; ++ ++ priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14; ++ priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14; ++ priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11; ++ priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e; ++ priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b; ++ priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07; ++ priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03; ++ priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02; ++ ++ priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13; ++ priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13; ++ priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10; ++ priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d; ++ priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a; ++ priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06; ++ priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03; ++ priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01; ++ ++ priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12; ++ priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12; ++ priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f; ++ priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c; ++ priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09; ++ priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06; ++ priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03; ++ priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01; ++ ++ priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11; ++ priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11; ++ priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f; ++ priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c; ++ priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09; ++ priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06; ++ priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03; ++ priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01; ++ ++ priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10; ++ priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10; ++ priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e; ++ priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b; ++ priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08; ++ priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05; ++ priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03; ++ priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01; ++ ++ priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f; ++ priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f; ++ priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d; ++ priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b; ++ priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08; ++ priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05; ++ priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03; ++ priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01; ++ ++ //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29 ++ //This Table is for CH14 ++ priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36; ++ priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35; ++ priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e; ++ priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b; ++ priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33; ++ priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32; ++ priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b; ++ priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19; ++ priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30; ++ priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f; ++ priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29; ++ priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18; ++ priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d; ++ priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d; ++ priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27; ++ priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17; ++ priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b; ++ priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a; ++ priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25; ++ priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15; ++ priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28; ++ priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28; ++ priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22; ++ priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14; ++ priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26; ++ priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25; ++ priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21; ++ priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13; ++ priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24; ++ priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23; ++ priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f; ++ priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12; ++ priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22; ++ priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21; ++ priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d; ++ priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11; ++ priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20; ++ priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20; ++ priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b; ++ priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10; ++ priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f; ++ priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e; ++ priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a; ++ priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f; ++ priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d; ++ priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c; ++ priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18; ++ priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e; ++ priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b; ++ priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a; ++ priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17; ++ priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e; ++ priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a; ++ priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19; ++ priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16; ++ priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d; ++ priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18; ++ priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17; ++ priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15; ++ priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c; ++ priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17; ++ priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16; ++ priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13; ++ priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b; ++ priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16; ++ priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15; ++ priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12; ++ priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b; ++ priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14; ++ priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14; ++ priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11; ++ priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a; ++ priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13; ++ priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13; ++ priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10; ++ priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a; ++ priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12; ++ priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12; ++ priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f; ++ priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09; ++ priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11; ++ priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11; ++ priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f; ++ priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09; ++ priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10; ++ priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10; ++ priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e; ++ priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08; ++ priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f; ++ priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f; ++ priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d; ++ priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08; ++ priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00; ++ priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00; ++ priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00; ++ priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00; ++ ++ priv->btxpower_tracking = TRUE; ++ priv->txpower_count = 0; ++ priv->btxpower_trackingInit = FALSE; ++ ++} ++#ifndef RTL8190P ++static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ // Tx Power tracking by Theremal Meter require Firmware R/W 3-wire. This mechanism ++ // can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w ++ // 3-wire by driver cause RF goes into wrong state. ++ if(priv->ieee80211->FwRWRF) ++ priv->btxpower_tracking = TRUE; ++ else ++ priv->btxpower_tracking = FALSE; ++ priv->txpower_count = 0; ++ priv->btxpower_trackingInit = FALSE; ++} ++#endif ++ ++void dm_initialize_txpower_tracking(struct net_device *dev) ++{ ++#ifndef RTL8190P ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#endif ++#ifdef RTL8190P ++ dm_InitializeTXPowerTracking_TSSI(dev); ++#else ++ //if(priv->bDcut == TRUE) ++ if(priv->IC_Cut >= IC_VersionCut_D) ++ dm_InitializeTXPowerTracking_TSSI(dev); ++ else ++ dm_InitializeTXPowerTracking_ThermalMeter(dev); ++#endif ++} // dm_InitializeTXPowerTracking ++ ++ ++static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ static u32 tx_power_track_counter = 0; ++ RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__); ++ if(read_nic_byte(dev, 0x11e) ==1) ++ return; ++ if(!priv->btxpower_tracking) ++ return; ++ tx_power_track_counter++; ++ ++ ++ if(tx_power_track_counter > 90) ++ { ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0); ++ #else ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++ schedule_task(&priv->txpower_tracking_wq); ++ #else ++ queue_work(priv->priv_wq,&priv->txpower_tracking_wq); ++ #endif ++ #endif ++ tx_power_track_counter =0; ++ } ++ ++} ++ ++#ifndef RTL8190P ++static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ static u8 TM_Trigger=0; ++#if 0 ++ u1Byte i; ++ u4Byte tmpRegA; ++ for(i=0; i<50; i++) ++ { ++ tmpRegA = PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7] ++ PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); ++ //delay_us(100); ++ PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); ++ //delay_us(100); ++ } ++ DbgPrint("Trigger and readback ThermalMeter, write RF reg0x2 = 0x4d to 0x4f for 50 times\n"); ++#else ++ //DbgPrint("dm_CheckTXPowerTracking() \n"); ++ if(!priv->btxpower_tracking) ++ return; ++ else ++ { ++ if(priv->txpower_count <= 2) ++ { ++ priv->txpower_count++; ++ return; ++ } ++ } ++ ++ if(!TM_Trigger) ++ { ++ //Attention!! You have to wirte all 12bits data to RF, or it may cause RF to crash ++ //actually write reg0x02 bit1=0, then bit1=1. ++ //DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n"); ++ rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); ++ rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); ++ rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); ++ rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); ++ TM_Trigger = 1; ++ return; ++ } ++ else ++ { ++ //DbgPrint("Schedule TxPowerTrackingWorkItem\n"); ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0); ++ #else ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++ schedule_task(&priv->txpower_tracking_wq); ++ #else ++ queue_work(priv->priv_wq,&priv->txpower_tracking_wq); ++ #endif ++ #endif ++ TM_Trigger = 0; ++ } ++#endif ++ } ++#endif ++ ++static void dm_check_txpower_tracking(struct net_device *dev) ++{ ++#ifndef RTL8190P ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ //static u32 tx_power_track_counter = 0; ++#endif ++#ifdef RTL8190P ++ dm_CheckTXPowerTracking_TSSI(dev); ++#else ++ //if(priv->bDcut == TRUE) ++ if(priv->IC_Cut >= IC_VersionCut_D) ++ dm_CheckTXPowerTracking_TSSI(dev); ++ else ++ dm_CheckTXPowerTracking_ThermalMeter(dev); ++#endif ++ ++} // dm_CheckTXPowerTracking ++ ++ ++static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14) ++{ ++ u32 TempVal; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ //Write 0xa22 0xa23 ++ TempVal = 0; ++ if(!bInCH14){ ++ //Write 0xa22 0xa23 ++ TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] + ++ (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ; ++ ++ rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal); ++ //Write 0xa24 ~ 0xa27 ++ TempVal = 0; ++ TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] + ++ (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) + ++ (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+ ++ (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24)); ++ rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal); ++ //Write 0xa28 0xa29 ++ TempVal = 0; ++ TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] + ++ (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ; ++ ++ rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal); ++ } ++ else ++ { ++ TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] + ++ (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ; ++ ++ rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal); ++ //Write 0xa24 ~ 0xa27 ++ TempVal = 0; ++ TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] + ++ (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) + ++ (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+ ++ (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24)); ++ rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal); ++ //Write 0xa28 0xa29 ++ TempVal = 0; ++ TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] + ++ (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ; ++ ++ rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal); ++ } ++ ++ ++} ++#ifndef RTL8190P ++static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14) ++{ ++ u32 TempVal; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ TempVal = 0; ++ if(!bInCH14) ++ { ++ //Write 0xa22 0xa23 ++ TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] + ++ (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8) ; ++ rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); ++ RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", ++ rCCK0_TxFilter1, TempVal); ++ //Write 0xa24 ~ 0xa27 ++ TempVal = 0; ++ TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] + ++ (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) + ++ (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16 )+ ++ (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24); ++ rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); ++ RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", ++ rCCK0_TxFilter2, TempVal); ++ //Write 0xa28 0xa29 ++ TempVal = 0; ++ TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] + ++ (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8) ; ++ ++ rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); ++ RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", ++ rCCK0_DebugPort, TempVal); ++ } ++ else ++ { ++// priv->CCKTxPowerAdjustCntNotCh14++; //cosa add for debug. ++ //Write 0xa22 0xa23 ++ TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] + ++ (CCKSwingTable_Ch14[priv->CCK_index][1]<<8) ; ++ ++ rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); ++ RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", ++ rCCK0_TxFilter1, TempVal); ++ //Write 0xa24 ~ 0xa27 ++ TempVal = 0; ++ TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] + ++ (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) + ++ (CCKSwingTable_Ch14[priv->CCK_index][4]<<16 )+ ++ (CCKSwingTable_Ch14[priv->CCK_index][5]<<24); ++ rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); ++ RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", ++ rCCK0_TxFilter2, TempVal); ++ //Write 0xa28 0xa29 ++ TempVal = 0; ++ TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] + ++ (CCKSwingTable_Ch14[priv->CCK_index][7]<<8) ; ++ ++ rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); ++ RT_TRACE(COMP_POWER_TRACKING,"CCK chnl 14, reg 0x%x = 0x%x\n", ++ rCCK0_DebugPort, TempVal); ++ } ++ } ++#endif ++ ++ ++void dm_cck_txpower_adjust(struct net_device *dev, bool binch14) ++{ // dm_CCKTxPowerAdjust ++#ifndef RTL8190P ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#endif ++#ifdef RTL8190P ++ dm_CCKTxPowerAdjust_TSSI(dev, binch14); ++#else ++ //if(priv->bDcut == TRUE) ++ if(priv->IC_Cut >= IC_VersionCut_D) ++ dm_CCKTxPowerAdjust_TSSI(dev, binch14); ++ else ++ dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14); ++#endif ++} ++ ++ ++#ifndef RTL8192U ++static void dm_txpower_reset_recovery( ++ struct net_device *dev ++) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n"); ++ rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value); ++ RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value); ++ RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",priv->rfa_txpowertrackingindex); ++ RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain); ++ RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n",priv->CCKPresentAttentuation); ++ dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); ++ ++ rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value); ++ RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value); ++ RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv->rfc_txpowertrackingindex); ++ RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain); ++ ++} // dm_TXPowerResetRecovery ++ ++void dm_restore_dynamic_mechanism_state(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u32 reg_ratr = priv->rate_adaptive.last_ratr; ++ ++ if(!priv->up) ++ { ++ RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n"); ++ return; ++ } ++ ++ // ++ // Restore previous state for rate adaptive ++ // ++ if(priv->rate_adaptive.rate_adaptive_disabled) ++ return; ++ // TODO: Only 11n mode is implemented currently, ++ if( !(priv->ieee80211->mode==WIRELESS_MODE_N_24G || ++ priv->ieee80211->mode==WIRELESS_MODE_N_5G)) ++ return; ++ { ++ /* 2007/11/15 MH Copy from 8190PCI. */ ++ u32 ratr_value; ++ ratr_value = reg_ratr; ++ if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled ++ { ++ ratr_value &=~ (RATE_ALL_OFDM_2SS); ++ //DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value); ++ } ++ //DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value); ++ //cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]); ++ write_nic_dword(dev, RATR0, ratr_value); ++ write_nic_byte(dev, UFWP, 1); ++#if 0 // Disable old code. ++ u1Byte index; ++ u4Byte input_value; ++ index = (u1Byte)((((pu4Byte)(val))[0]) >> 28); ++ input_value = (((pu4Byte)(val))[0]) & 0x0fffffff; ++ // TODO: Correct it. Emily 2007.01.11 ++ PlatformEFIOWrite4Byte(Adapter, RATR0+index*4, input_value); ++#endif ++ } ++ //Resore TX Power Tracking Index ++ if(priv->btxpower_trackingInit && priv->btxpower_tracking){ ++ dm_txpower_reset_recovery(dev); ++ } ++ ++ // ++ //Restore BB Initial Gain ++ // ++ dm_bb_initialgain_restore(dev); ++ ++} // DM_RestoreDynamicMechanismState ++ ++static void dm_bb_initialgain_restore(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u32 bit_mask = 0x7f; //Bit0~ Bit6 ++ ++ if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) ++ return; ++ ++ //Disable Initial Gain ++ //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800); ++ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite. ++ rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1); ++ rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1); ++ rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1); ++ rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1); ++ bit_mask = bMaskByte2; ++ rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca); ++ ++ RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); ++ RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); ++ RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); ++ RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); ++ RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); ++ //Enable Initial Gain ++ //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100); ++ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite. ++ ++} // dm_BBInitialGainRestore ++ ++ ++void dm_backup_dynamic_mechanism_state(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ // Fsync to avoid reset ++ priv->bswitch_fsync = false; ++ priv->bfsync_processing = false; ++ //Backup BB InitialGain ++ dm_bb_initialgain_backup(dev); ++ ++} // DM_BackupDynamicMechanismState ++ ++ ++static void dm_bb_initialgain_backup(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u32 bit_mask = bMaskByte0; //Bit0~ Bit6 ++ ++ if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) ++ return; ++ ++ //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800); ++ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite. ++ priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask); ++ priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask); ++ priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask); ++ priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask); ++ bit_mask = bMaskByte2; ++ priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask); ++ ++ RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); ++ RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); ++ RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); ++ RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); ++ RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); ++ ++} // dm_BBInitialGainBakcup ++ ++#endif ++/*----------------------------------------------------------------------------- ++ * Function: dm_change_dynamic_initgain_thresh() ++ * ++ * Overview: ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/29/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++void dm_change_dynamic_initgain_thresh(struct net_device *dev, u32 dm_type, u32 dm_value) ++{ ++ if (dm_type == DIG_TYPE_THRESH_HIGH) ++ { ++ dm_digtable.rssi_high_thresh = dm_value; ++ } ++ else if (dm_type == DIG_TYPE_THRESH_LOW) ++ { ++ dm_digtable.rssi_low_thresh = dm_value; ++ } ++ else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH) ++ { ++ dm_digtable.rssi_high_power_highthresh = dm_value; ++ } ++ else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH) ++ { ++ dm_digtable.rssi_high_power_highthresh = dm_value; ++ } ++ else if (dm_type == DIG_TYPE_ENABLE) ++ { ++ dm_digtable.dig_state = DM_STA_DIG_MAX; ++ dm_digtable.dig_enable_flag = true; ++ } ++ else if (dm_type == DIG_TYPE_DISABLE) ++ { ++ dm_digtable.dig_state = DM_STA_DIG_MAX; ++ dm_digtable.dig_enable_flag = false; ++ } ++ else if (dm_type == DIG_TYPE_DBG_MODE) ++ { ++ if(dm_value >= DM_DBG_MAX) ++ dm_value = DM_DBG_OFF; ++ dm_digtable.dbg_mode = (u8)dm_value; ++ } ++ else if (dm_type == DIG_TYPE_RSSI) ++ { ++ if(dm_value > 100) ++ dm_value = 30; ++ dm_digtable.rssi_val = (long)dm_value; ++ } ++ else if (dm_type == DIG_TYPE_ALGORITHM) ++ { ++ if (dm_value >= DIG_ALGO_MAX) ++ dm_value = DIG_ALGO_BY_FALSE_ALARM; ++ if(dm_digtable.dig_algorithm != (u8)dm_value) ++ dm_digtable.dig_algorithm_switch = 1; ++ dm_digtable.dig_algorithm = (u8)dm_value; ++ } ++ else if (dm_type == DIG_TYPE_BACKOFF) ++ { ++ if(dm_value > 30) ++ dm_value = 30; ++ dm_digtable.backoff_val = (u8)dm_value; ++ } ++ else if(dm_type == DIG_TYPE_RX_GAIN_MIN) ++ { ++ if(dm_value == 0) ++ dm_value = 0x1; ++ dm_digtable.rx_gain_range_min = (u8)dm_value; ++ } ++ else if(dm_type == DIG_TYPE_RX_GAIN_MAX) ++ { ++ if(dm_value > 0x50) ++ dm_value = 0x50; ++ dm_digtable.rx_gain_range_max = (u8)dm_value; ++ } ++} /* DM_ChangeDynamicInitGainThresh */ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: dm_dig_init() ++ * ++ * Overview: Set DIG scheme init value. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/15/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++static void dm_dig_init(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ /* 2007/10/05 MH Disable DIG scheme now. Not tested. */ ++ dm_digtable.dig_enable_flag = true; ++ dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI; ++ dm_digtable.dbg_mode = DM_DBG_OFF; //off=by real rssi value, on=by DM_DigTable.Rssi_val for new dig ++ dm_digtable.dig_algorithm_switch = 0; ++ ++ /* 2007/10/04 MH Define init gain threshol. */ ++ dm_digtable.dig_state = DM_STA_DIG_MAX; ++ dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX; ++ dm_digtable.initialgain_lowerbound_state = false; ++ ++ dm_digtable.rssi_low_thresh = DM_DIG_THRESH_LOW; ++ dm_digtable.rssi_high_thresh = DM_DIG_THRESH_HIGH; ++ ++ dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW; ++ dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH; ++ ++ dm_digtable.rssi_val = 50; //for new dig debug rssi value ++ dm_digtable.backoff_val = DM_DIG_BACKOFF; ++ dm_digtable.rx_gain_range_max = DM_DIG_MAX; ++ if(priv->CustomerID == RT_CID_819x_Netcore) ++ dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore; ++ else ++ dm_digtable.rx_gain_range_min = DM_DIG_MIN; ++ ++} /* dm_dig_init */ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: dm_ctrl_initgain_byrssi() ++ * ++ * Overview: Driver must monitor RSSI and notify firmware to change initial ++ * gain according to different threshold. BB team provide the ++ * suggested solution. ++ * ++ * Input: struct net_device *dev ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/27/2008 amy Create Version 0 porting from windows code. ++ *---------------------------------------------------------------------------*/ ++static void dm_ctrl_initgain_byrssi(struct net_device *dev) ++{ ++ ++ if (dm_digtable.dig_enable_flag == false) ++ return; ++ ++ if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) ++ dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev); ++ else if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) ++ dm_ctrl_initgain_byrssi_by_driverrssi(dev); ++ else ++ return; ++} ++ ++ ++static void dm_ctrl_initgain_byrssi_by_driverrssi( ++ struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 i; ++ static u8 fw_dig=0; ++ ++ if (dm_digtable.dig_enable_flag == false) ++ return; ++ ++ //DbgPrint("Dig by Sw Rssi \n"); ++ if(dm_digtable.dig_algorithm_switch) // if swithed algorithm, we have to disable FW Dig. ++ fw_dig = 0; ++ if(fw_dig <= 3) // execute several times to make sure the FW Dig is disabled ++ {// FW DIG Off ++ for(i=0; i<3; i++) ++ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite. ++ fw_dig++; ++ dm_digtable.dig_state = DM_STA_DIG_OFF; //fw dig off. ++ } ++ ++ if(priv->ieee80211->state == IEEE80211_LINKED) ++ dm_digtable.cur_connect_state = DIG_CONNECT; ++ else ++ dm_digtable.cur_connect_state = DIG_DISCONNECT; ++ ++ //DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d \n", ++ //DM_DigTable.PreConnectState, DM_DigTable.CurConnectState); ++ ++ if(dm_digtable.dbg_mode == DM_DBG_OFF) ++ dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb; ++ //DbgPrint("DM_DigTable.Rssi_val = %d \n", DM_DigTable.Rssi_val); ++ dm_initial_gain(dev); ++ dm_pd_th(dev); ++ dm_cs_ratio(dev); ++ if(dm_digtable.dig_algorithm_switch) ++ dm_digtable.dig_algorithm_switch = 0; ++ dm_digtable.pre_connect_state = dm_digtable.cur_connect_state; ++ ++} /* dm_CtrlInitGainByRssi */ ++ ++static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm( ++ struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ static u32 reset_cnt = 0; ++ u8 i; ++ ++ if (dm_digtable.dig_enable_flag == false) ++ return; ++ ++ if(dm_digtable.dig_algorithm_switch) ++ { ++ dm_digtable.dig_state = DM_STA_DIG_MAX; ++ // Fw DIG On. ++ for(i=0; i<3; i++) ++ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite. ++ dm_digtable.dig_algorithm_switch = 0; ++ } ++ ++ if (priv->ieee80211->state != IEEE80211_LINKED) ++ return; ++ ++ // For smooth, we can not change DIG state. ++ if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) && ++ (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh)) ++ { ++ return; ++ } ++ //DbgPrint("Dig by Fw False Alarm\n"); ++ //if (DM_DigTable.Dig_State == DM_STA_DIG_OFF) ++ /*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d", ++ pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh, ++ DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/ ++ /* 1. When RSSI decrease, We have to judge if it is smaller than a treshold ++ and then execute below step. */ ++ if ((priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh)) ++ { ++ /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters ++ will be reset to init value. We must prevent the condition. */ ++ if (dm_digtable.dig_state == DM_STA_DIG_OFF && ++ (priv->reset_count == reset_cnt)) ++ { ++ return; ++ } ++ else ++ { ++ reset_cnt = priv->reset_count; ++ } ++ ++ // If DIG is off, DIG high power state must reset. ++ dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX; ++ dm_digtable.dig_state = DM_STA_DIG_OFF; ++ ++ // 1.1 DIG Off. ++ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite. ++ ++ // 1.2 Set initial gain. ++ write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17); ++ write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17); ++ write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17); ++ write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17); ++ ++ // 1.3 Lower PD_TH for OFDM. ++ if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ++ { ++ /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ ++ // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. ++ #ifdef RTL8190P ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x40); ++ #else ++ write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00); ++ #endif ++ /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) ++ write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40); ++ */ ++ //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E) ++ ++ ++ //else ++ //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40); ++ } ++ else ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); ++ ++ // 1.4 Lower CS ratio for CCK. ++ write_nic_byte(dev, 0xa0a, 0x08); ++ ++ // 1.5 Higher EDCCA. ++ //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325); ++ return; ++ ++ } ++ ++ /* 2. When RSSI increase, We have to judge if it is larger than a treshold ++ and then execute below step. */ ++ if ((priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) ) ++ { ++ u8 reset_flag = 0; ++ ++ if (dm_digtable.dig_state == DM_STA_DIG_ON && ++ (priv->reset_count == reset_cnt)) ++ { ++ dm_ctrl_initgain_byrssi_highpwr(dev); ++ return; ++ } ++ else ++ { ++ if (priv->reset_count != reset_cnt) ++ reset_flag = 1; ++ ++ reset_cnt = priv->reset_count; ++ } ++ ++ dm_digtable.dig_state = DM_STA_DIG_ON; ++ //DbgPrint("DIG ON\n\r"); ++ ++ // 2.1 Set initial gain. ++ // 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment. ++ if (reset_flag == 1) ++ { ++ write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c); ++ write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c); ++ write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c); ++ write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c); ++ } ++ else ++ { ++ write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20); ++ write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20); ++ write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20); ++ write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20); ++ } ++ ++ // 2.2 Higher PD_TH for OFDM. ++ if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ++ { ++ /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ ++ // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. ++ #ifdef RTL8190P ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); ++ #else ++ write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); ++ #endif ++ /* ++ else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); ++ */ ++ //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E) ++ ++ //else ++ //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42); ++ } ++ else ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); ++ ++ // 2.3 Higher CS ratio for CCK. ++ write_nic_byte(dev, 0xa0a, 0xcd); ++ ++ // 2.4 Lower EDCCA. ++ /* 2008/01/11 MH 90/92 series are the same. */ ++ //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346); ++ ++ // 2.5 DIG On. ++ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite. ++ ++ } ++ ++ dm_ctrl_initgain_byrssi_highpwr(dev); ++ ++} /* dm_CtrlInitGainByRssi */ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: dm_ctrl_initgain_byrssi_highpwr() ++ * ++ * Overview: ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/28/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++static void dm_ctrl_initgain_byrssi_highpwr( ++ struct net_device * dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ static u32 reset_cnt_highpwr = 0; ++ ++ // For smooth, we can not change high power DIG state in the range. ++ if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) && ++ (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh)) ++ { ++ return; ++ } ++ ++ /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if ++ it is larger than a treshold and then execute below step. */ ++ // 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue. ++ if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh) ++ { ++ if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON && ++ (priv->reset_count == reset_cnt_highpwr)) ++ return; ++ else ++ dm_digtable.dig_highpwr_state = DM_STA_DIG_ON; ++ ++ // 3.1 Higher PD_TH for OFDM for high power state. ++ if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ++ { ++ #ifdef RTL8190P ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); ++ #else ++ write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10); ++ #endif ++ ++ /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); ++ */ ++ ++ } ++ else ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x43); ++ } ++ else ++ { ++ if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF&& ++ (priv->reset_count == reset_cnt_highpwr)) ++ return; ++ else ++ dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF; ++ ++ if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh && ++ priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) ++ { ++ // 3.2 Recover PD_TH for OFDM for normal power region. ++ if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ++ { ++ #ifdef RTL8190P ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); ++ #else ++ write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); ++ #endif ++ /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); ++ */ ++ ++ } ++ else ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); ++ } ++ } ++ ++ reset_cnt_highpwr = priv->reset_count; ++ ++} /* dm_CtrlInitGainByRssiHighPwr */ ++ ++ ++static void dm_initial_gain( ++ struct net_device * dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 initial_gain=0; ++ static u8 initialized=0, force_write=0; ++ static u32 reset_cnt=0; ++ ++ if(dm_digtable.dig_algorithm_switch) ++ { ++ initialized = 0; ++ reset_cnt = 0; ++ } ++ ++ if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) ++ { ++ if(dm_digtable.cur_connect_state == DIG_CONNECT) ++ { ++ if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) > dm_digtable.rx_gain_range_max) ++ dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_max; ++ else if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min) ++ dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min; ++ else ++ dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val; ++ } ++ else //current state is disconnected ++ { ++ if(dm_digtable.cur_ig_value == 0) ++ dm_digtable.cur_ig_value = priv->DefaultInitialGain[0]; ++ else ++ dm_digtable.cur_ig_value = dm_digtable.pre_ig_value; ++ } ++ } ++ else // disconnected -> connected or connected -> disconnected ++ { ++ dm_digtable.cur_ig_value = priv->DefaultInitialGain[0]; ++ dm_digtable.pre_ig_value = 0; ++ } ++ //DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue); ++ ++ // if silent reset happened, we should rewrite the values back ++ if(priv->reset_count != reset_cnt) ++ { ++ force_write = 1; ++ reset_cnt = priv->reset_count; ++ } ++ ++ if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1)) ++ force_write = 1; ++ ++ { ++ if((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value) ++ || !initialized || force_write) ++ { ++ initial_gain = (u8)dm_digtable.cur_ig_value; ++ //DbgPrint("Write initial gain = 0x%x\n", initial_gain); ++ // Set initial gain. ++ write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); ++ write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); ++ write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); ++ write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); ++ dm_digtable.pre_ig_value = dm_digtable.cur_ig_value; ++ initialized = 1; ++ force_write = 0; ++ } ++ } ++} ++ ++static void dm_pd_th( ++ struct net_device * dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ static u8 initialized=0, force_write=0; ++ static u32 reset_cnt = 0; ++ ++ if(dm_digtable.dig_algorithm_switch) ++ { ++ initialized = 0; ++ reset_cnt = 0; ++ } ++ ++ if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) ++ { ++ if(dm_digtable.cur_connect_state == DIG_CONNECT) ++ { ++ if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh) ++ dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER; ++ else if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)) ++ dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; ++ else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) && ++ (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh)) ++ dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER; ++ else ++ dm_digtable.curpd_thstate = dm_digtable.prepd_thstate; ++ } ++ else ++ { ++ dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; ++ } ++ } ++ else // disconnected -> connected or connected -> disconnected ++ { ++ dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; ++ } ++ ++ // if silent reset happened, we should rewrite the values back ++ if(priv->reset_count != reset_cnt) ++ { ++ force_write = 1; ++ reset_cnt = priv->reset_count; ++ } ++ ++ { ++ if((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) || ++ (initialized<=3) || force_write) ++ { ++ //DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState); ++ if(dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER) ++ { ++ // Lower PD_TH for OFDM. ++ if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ++ { ++ /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ ++ // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. ++ #ifdef RTL8190P ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x40); ++ #else ++ write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00); ++ #endif ++ /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x40); ++ */ ++ } ++ else ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); ++ } ++ else if(dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER) ++ { ++ // Higher PD_TH for OFDM. ++ if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ++ { ++ /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ ++ // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. ++ #ifdef RTL8190P ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); ++ #else ++ write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); ++ #endif ++ /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); ++ */ ++ } ++ else ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); ++ } ++ else if(dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER) ++ { ++ // Higher PD_TH for OFDM for high power state. ++ if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ++ { ++ #ifdef RTL8190P ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); ++ #else ++ write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10); ++ #endif ++ /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); ++ */ ++ } ++ else ++ write_nic_byte(dev, rOFDM0_RxDetector1, 0x43); ++ } ++ dm_digtable.prepd_thstate = dm_digtable.curpd_thstate; ++ if(initialized <= 3) ++ initialized++; ++ force_write = 0; ++ } ++ } ++} ++ ++static void dm_cs_ratio( ++ struct net_device * dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ static u8 initialized=0,force_write=0; ++ static u32 reset_cnt = 0; ++ ++ if(dm_digtable.dig_algorithm_switch) ++ { ++ initialized = 0; ++ reset_cnt = 0; ++ } ++ ++ if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) ++ { ++ if(dm_digtable.cur_connect_state == DIG_CONNECT) ++ { ++ if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)) ++ dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; ++ else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) ) ++ dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER; ++ else ++ dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state; ++ } ++ else ++ { ++ dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; ++ } ++ } ++ else // disconnected -> connected or connected -> disconnected ++ { ++ dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; ++ } ++ ++ // if silent reset happened, we should rewrite the values back ++ if(priv->reset_count != reset_cnt) ++ { ++ force_write = 1; ++ reset_cnt = priv->reset_count; ++ } ++ ++ ++ { ++ if((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) || ++ !initialized || force_write) ++ { ++ //DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState); ++ if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER) ++ { ++ // Lower CS ratio for CCK. ++ write_nic_byte(dev, 0xa0a, 0x08); ++ } ++ else if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER) ++ { ++ // Higher CS ratio for CCK. ++ write_nic_byte(dev, 0xa0a, 0xcd); ++ } ++ dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state; ++ initialized = 1; ++ force_write = 0; ++ } ++ } ++} ++ ++void dm_init_edca_turbo(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ priv->bcurrent_turbo_EDCA = false; ++ priv->ieee80211->bis_any_nonbepkts = false; ++ priv->bis_cur_rdlstate = false; ++} // dm_init_edca_turbo ++ ++#if 1 ++static void dm_check_edca_turbo( ++ struct net_device * dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; ++ //PSTA_QOS pStaQos = pMgntInfo->pStaQos; ++ ++ // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. ++ static unsigned long lastTxOkCnt = 0; ++ static unsigned long lastRxOkCnt = 0; ++ unsigned long curTxOkCnt = 0; ++ unsigned long curRxOkCnt = 0; ++ ++ // ++ // Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters ++ // should follow the settings from QAP. By Bruce, 2007-12-07. ++ // ++ #if 1 ++ if(priv->ieee80211->state != IEEE80211_LINKED) ++ goto dm_CheckEdcaTurbo_EXIT; ++ #endif ++ // We do not turn on EDCA turbo mode for some AP that has IOT issue ++ if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO) ++ goto dm_CheckEdcaTurbo_EXIT; ++ ++// printk("========>%s():bis_any_nonbepkts is %d\n",__FUNCTION__,priv->bis_any_nonbepkts); ++ // Check the status for current condition. ++ if(!priv->ieee80211->bis_any_nonbepkts) ++ { ++ curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; ++ curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; ++ // For RT-AP, we needs to turn it on when Rx>Tx ++ if(curRxOkCnt > 4*curTxOkCnt) ++ { ++ //printk("%s():curRxOkCnt > 4*curTxOkCnt\n"); ++ if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) ++ { ++ write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]); ++ priv->bis_cur_rdlstate = true; ++ } ++ } ++ else ++ { ++ ++ //printk("%s():curRxOkCnt < 4*curTxOkCnt\n"); ++ if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) ++ { ++ write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]); ++ priv->bis_cur_rdlstate = false; ++ } ++ ++ } ++ ++ priv->bcurrent_turbo_EDCA = true; ++ } ++ else ++ { ++ // ++ // Turn Off EDCA turbo here. ++ // Restore original EDCA according to the declaration of AP. ++ // ++ if(priv->bcurrent_turbo_EDCA) ++ { ++ ++ { ++ u8 u1bAIFS; ++ u32 u4bAcParam; ++ struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters; ++ u8 mode = priv->ieee80211->mode; ++ ++ // For Each time updating EDCA parameter, reset EDCA turbo mode status. ++ dm_init_edca_turbo(dev); ++ u1bAIFS = qos_parameters->aifs[0] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime; ++ u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[0]))<< AC_PARAM_TXOP_LIMIT_OFFSET)| ++ (((u32)(qos_parameters->cw_max[0]))<< AC_PARAM_ECW_MAX_OFFSET)| ++ (((u32)(qos_parameters->cw_min[0]))<< AC_PARAM_ECW_MIN_OFFSET)| ++ ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET)); ++ printk("===>u4bAcParam:%x, ", u4bAcParam); ++ //write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam); ++ write_nic_dword(dev, EDCAPARA_BE, u4bAcParam); ++ ++ // Check ACM bit. ++ // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13. ++ { ++ // TODO: Modified this part and try to set acm control in only 1 IO processing!! ++ ++ PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]); ++ u8 AcmCtrl = read_nic_byte( dev, AcmHwCtrl ); ++ if( pAciAifsn->f.ACM ) ++ { // ACM bit is 1. ++ AcmCtrl |= AcmHw_BeqEn; ++ } ++ else ++ { // ACM bit is 0. ++ AcmCtrl &= (~AcmHw_BeqEn); ++ } ++ ++ RT_TRACE( COMP_QOS,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ) ; ++ write_nic_byte(dev, AcmHwCtrl, AcmCtrl ); ++ } ++ } ++ priv->bcurrent_turbo_EDCA = false; ++ } ++ } ++ ++ ++dm_CheckEdcaTurbo_EXIT: ++ // Set variables for next time. ++ priv->ieee80211->bis_any_nonbepkts = false; ++ lastTxOkCnt = priv->stats.txbytesunicast; ++ lastRxOkCnt = priv->stats.rxbytesunicast; ++} // dm_CheckEdcaTurbo ++#endif ++ ++static void dm_init_ctstoself(struct net_device * dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev); ++ ++ priv->ieee80211->bCTSToSelfEnable = TRUE; ++ priv->ieee80211->CTSToSelfTH = CTSToSelfTHVal; ++} ++ ++static void dm_ctstoself(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev); ++ PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; ++ static unsigned long lastTxOkCnt = 0; ++ static unsigned long lastRxOkCnt = 0; ++ unsigned long curTxOkCnt = 0; ++ unsigned long curRxOkCnt = 0; ++ ++ if(priv->ieee80211->bCTSToSelfEnable != TRUE) ++ { ++ pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF; ++ return; ++ } ++ /* ++ 1. Uplink ++ 2. Linksys350/Linksys300N ++ 3. <50 disable, >55 enable ++ */ ++ ++ if(pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) ++ { ++ curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; ++ curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; ++ if(curRxOkCnt > 4*curTxOkCnt) //downlink, disable CTS to self ++ { ++ pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF; ++ //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n"); ++ } ++ else //uplink ++ { ++ #if 1 ++ pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF; ++ #else ++ if(priv->undecorated_smoothed_pwdb < priv->ieee80211->CTSToSelfTH) // disable CTS to self ++ { ++ pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF; ++ //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled\n"); ++ } ++ else if(priv->undecorated_smoothed_pwdb >= (priv->ieee80211->CTSToSelfTH+5)) // enable CTS to self ++ { ++ pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF; ++ //DbgPrint("dm_CTSToSelf() ==> CTS to self enabled\n"); ++ } ++ #endif ++ } ++ ++ lastTxOkCnt = priv->stats.txbytesunicast; ++ lastRxOkCnt = priv->stats.rxbytesunicast; ++ } ++} ++ ++ ++#if 0 ++/*----------------------------------------------------------------------------- ++ * Function: dm_rf_operation_test_callback() ++ * ++ * Overview: Only for RF operation test now. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/29/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++void dm_rf_operation_test_callback(unsigned long dev) ++{ ++// struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev); ++ u8 erfpath; ++ ++ ++ for(erfpath=0; erfpath<4; erfpath++) ++ { ++ //DbgPrint("Set RF-%d\n\r", eRFPath); ++ //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7); ++ udelay(100); ++ } ++ ++ { ++ //PlatformSetPeriodicTimer(Adapter, &pHalData->RfTest1Timer, 500); ++ } ++ ++ // For test ++ { ++ //u8 i; ++ //PlatformSetPeriodicTimer(Adapter, &pHalData->RfTest1Timer, 500); ++#if 0 ++ for(i=0; i<50; i++) ++ { ++ // Write Test ++ PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); ++ //delay_us(100); ++ PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); ++ //delay_us(100); ++ PHY_SetRFReg(Adapter, RF90_PATH_C, 0x02, bMask12Bits, 0x4d); ++ //delay_us(100); ++ PHY_SetRFReg(Adapter, RF90_PATH_C, 0x02, bMask12Bits, 0x4f); ++ //delay_us(100); ++ ++#if 0 ++ // Read test ++ PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits); ++ //delay_us(100); ++ PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits); ++ //delay_us(100); ++ PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, bMask12Bits); ++ //delay_us(100); ++ PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, bMask12Bits); ++ //delay_us(100); ++ PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x21, bMask12Bits); ++ //delay_us(100); ++ PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x21, bMask12Bits); ++ //delay_us(100); ++#endif ++ } ++#endif ++ } ++ ++} /* DM_RfOperationTestCallBack */ ++#endif ++ ++/*----------------------------------------------------------------------------- ++ * Function: dm_check_rfctrl_gpio() ++ * ++ * Overview: Copy 8187B template for 9xseries. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/28/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++#if 1 ++static void dm_check_rfctrl_gpio(struct net_device * dev) ++{ ++#ifdef RTL8192E ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#endif ++ ++ // Walk around for DTM test, we will not enable HW - radio on/off because r/w ++ // page 1 register before Lextra bus is enabled cause system fails when resuming ++ // from S4. 20080218, Emily ++ ++ // Stop to execute workitem to prevent S3/S4 bug. ++#ifdef RTL8190P ++ return; ++#endif ++#ifdef RTL8192U ++ return; ++#endif ++#ifdef RTL8192E ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0); ++ #else ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++ schedule_task(&priv->gpio_change_rf_wq); ++ #else ++ queue_work(priv->priv_wq,&priv->gpio_change_rf_wq); ++ #endif ++ #endif ++#endif ++ ++} /* dm_CheckRfCtrlGPIO */ ++ ++#endif ++/*----------------------------------------------------------------------------- ++ * Function: dm_check_pbc_gpio() ++ * ++ * Overview: Check if PBC button is pressed. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/28/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++static void dm_check_pbc_gpio(struct net_device *dev) ++{ ++#ifdef RTL8192U ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 tmp1byte; ++ ++ ++ tmp1byte = read_nic_byte(dev,GPI); ++ if(tmp1byte == 0xff) ++ return; ++ ++ if (tmp1byte&BIT6 || tmp1byte&BIT0) ++ { ++ // Here we only set bPbcPressed to TRUE ++ // After trigger PBC, the variable will be set to FALSE ++ RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n"); ++ priv->bpbc_pressed = true; ++ } ++#endif ++ ++} ++ ++#ifdef RTL8192E ++ ++/*----------------------------------------------------------------------------- ++ * Function: dm_GPIOChangeRF ++ * Overview: PCI will not support workitem call back HW radio on-off control. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 02/21/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void dm_gpio_change_rf_callback(struct work_struct *work) ++{ ++ struct delayed_work *dwork = container_of(work,struct delayed_work,work); ++ struct r8192_priv *priv = container_of(dwork,struct r8192_priv,gpio_change_rf_wq); ++ struct net_device *dev = priv->ieee80211->dev; ++#else ++extern void dm_gpio_change_rf_callback(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#endif ++ u8 tmp1byte; ++ RT_RF_POWER_STATE eRfPowerStateToSet; ++ bool bActuallySet = false; ++ ++ bActuallySet=false; ++ ++ if(!priv->up) ++ { ++ RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF),"dm_gpio_change_rf_callback(): Callback function breaks out!!\n"); ++ } ++ else ++ { ++ // 0x108 GPIO input register is read only ++ //set 0x108 B1= 1: RF-ON; 0: RF-OFF. ++ tmp1byte = read_nic_byte(dev,GPI); ++ ++ eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff; ++ ++ if( (priv->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn)) ++ { ++ RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio ON\n"); ++ ++ priv->bHwRadioOff = false; ++ bActuallySet = true; ++ } ++ else if ( (priv->bHwRadioOff == false) && (eRfPowerStateToSet == eRfOff)) ++ { ++ RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio OFF\n"); ++ priv->bHwRadioOff = true; ++ bActuallySet = true; ++ } ++ ++ if(bActuallySet) ++ { ++ priv->bHwRfOffAction = 1; ++ MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW); ++ //DrvIFIndicateCurrentPhyStatus(pAdapter); ++ ++ } ++ else ++ { ++ msleep(2000); ++ } ++ ++ } ++ ++} /* dm_GPIOChangeRF */ ++ ++#endif ++/*----------------------------------------------------------------------------- ++ * Function: DM_RFPathCheckWorkItemCallBack() ++ * ++ * Overview: Check if Current RF RX path is enabled ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 01/30/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void dm_rf_pathcheck_workitemcallback(struct work_struct *work) ++{ ++ struct delayed_work *dwork = container_of(work,struct delayed_work,work); ++ struct r8192_priv *priv = container_of(dwork,struct r8192_priv,rfpath_check_wq); ++ struct net_device *dev =priv->ieee80211->dev; ++#else ++extern void dm_rf_pathcheck_workitemcallback(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#endif ++ //bool bactually_set = false; ++ u8 rfpath = 0, i; ++ ++ ++ /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will ++ always be the same. We only read 0xc04 now. */ ++ rfpath = read_nic_byte(dev, 0xc04); ++ ++ // Check Bit 0-3, it means if RF A-D is enabled. ++ for (i = 0; i < RF90_PATH_MAX; i++) ++ { ++ if (rfpath & (0x01<brfpath_rxenable[i] = 1; ++ else ++ priv->brfpath_rxenable[i] = 0; ++ } ++ if(!DM_RxPathSelTable.Enable) ++ return; ++ ++ dm_rxpath_sel_byrssi(dev); ++} /* DM_RFPathCheckWorkItemCallBack */ ++ ++static void dm_init_rxpath_selection(struct net_device * dev) ++{ ++ u8 i; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ DM_RxPathSelTable.Enable = 1; //default enabled ++ DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low; ++ DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH; ++ if(priv->CustomerID == RT_CID_819x_Netcore) ++ DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; ++ else ++ DM_RxPathSelTable.cck_method = CCK_Rx_Version_1; ++ DM_RxPathSelTable.DbgMode = DM_DBG_OFF; ++ DM_RxPathSelTable.disabledRF = 0; ++ for(i=0; i<4; i++) ++ { ++ DM_RxPathSelTable.rf_rssi[i] = 50; ++ DM_RxPathSelTable.cck_pwdb_sta[i] = -64; ++ DM_RxPathSelTable.rf_enable_rssi_th[i] = 100; ++ } ++} ++ ++static void dm_rxpath_sel_byrssi(struct net_device * dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 i, max_rssi_index=0, min_rssi_index=0, sec_rssi_index=0, rf_num=0; ++ u8 tmp_max_rssi=0, tmp_min_rssi=0, tmp_sec_rssi=0; ++ u8 cck_default_Rx=0x2; //RF-C ++ u8 cck_optional_Rx=0x3;//RF-D ++ long tmp_cck_max_pwdb=0, tmp_cck_min_pwdb=0, tmp_cck_sec_pwdb=0; ++ u8 cck_rx_ver2_max_index=0, cck_rx_ver2_min_index=0, cck_rx_ver2_sec_index=0; ++ u8 cur_rf_rssi; ++ long cur_cck_pwdb; ++ static u8 disabled_rf_cnt=0, cck_Rx_Path_initialized=0; ++ u8 update_cck_rx_path; ++ ++ if(priv->rf_type != RF_2T4R) ++ return; ++ ++ if(!cck_Rx_Path_initialized) ++ { ++ DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf); ++ cck_Rx_Path_initialized = 1; ++ } ++ ++ DM_RxPathSelTable.disabledRF = 0xf; ++ DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(dev, 0xc04)); ++ ++ if(priv->ieee80211->mode == WIRELESS_MODE_B) ++ { ++ DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; //pure B mode, fixed cck version2 ++ //DbgPrint("Pure B mode, use cck rx version2 \n"); ++ } ++ ++ //decide max/sec/min rssi index ++ for (i=0; istats.rx_rssi_percentage[i]; ++ ++ if(priv->brfpath_rxenable[i]) ++ { ++ rf_num++; ++ cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i]; ++ ++ if(rf_num == 1) // find first enabled rf path and the rssi values ++ { //initialize, set all rssi index to the same one ++ max_rssi_index = min_rssi_index = sec_rssi_index = i; ++ tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi; ++ } ++ else if(rf_num == 2) ++ { // we pick up the max index first, and let sec and min to be the same one ++ if(cur_rf_rssi >= tmp_max_rssi) ++ { ++ tmp_max_rssi = cur_rf_rssi; ++ max_rssi_index = i; ++ } ++ else ++ { ++ tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi; ++ sec_rssi_index = min_rssi_index = i; ++ } ++ } ++ else ++ { ++ if(cur_rf_rssi > tmp_max_rssi) ++ { ++ tmp_sec_rssi = tmp_max_rssi; ++ sec_rssi_index = max_rssi_index; ++ tmp_max_rssi = cur_rf_rssi; ++ max_rssi_index = i; ++ } ++ else if(cur_rf_rssi == tmp_max_rssi) ++ { // let sec and min point to the different index ++ tmp_sec_rssi = cur_rf_rssi; ++ sec_rssi_index = i; ++ } ++ else if((cur_rf_rssi < tmp_max_rssi) &&(cur_rf_rssi > tmp_sec_rssi)) ++ { ++ tmp_sec_rssi = cur_rf_rssi; ++ sec_rssi_index = i; ++ } ++ else if(cur_rf_rssi == tmp_sec_rssi) ++ { ++ if(tmp_sec_rssi == tmp_min_rssi) ++ { // let sec and min point to the different index ++ tmp_sec_rssi = cur_rf_rssi; ++ sec_rssi_index = i; ++ } ++ else ++ { ++ // This case we don't need to set any index ++ } ++ } ++ else if((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi)) ++ { ++ // This case we don't need to set any index ++ } ++ else if(cur_rf_rssi == tmp_min_rssi) ++ { ++ if(tmp_sec_rssi == tmp_min_rssi) ++ { // let sec and min point to the different index ++ tmp_min_rssi = cur_rf_rssi; ++ min_rssi_index = i; ++ } ++ else ++ { ++ // This case we don't need to set any index ++ } ++ } ++ else if(cur_rf_rssi < tmp_min_rssi) ++ { ++ tmp_min_rssi = cur_rf_rssi; ++ min_rssi_index = i; ++ } ++ } ++ } ++ } ++ ++ rf_num = 0; ++ // decide max/sec/min cck pwdb index ++ if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) ++ { ++ for (i=0; ibrfpath_rxenable[i]) ++ { ++ rf_num++; ++ cur_cck_pwdb = DM_RxPathSelTable.cck_pwdb_sta[i]; ++ ++ if(rf_num == 1) // find first enabled rf path and the rssi values ++ { //initialize, set all rssi index to the same one ++ cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i; ++ tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb; ++ } ++ else if(rf_num == 2) ++ { // we pick up the max index first, and let sec and min to be the same one ++ if(cur_cck_pwdb >= tmp_cck_max_pwdb) ++ { ++ tmp_cck_max_pwdb = cur_cck_pwdb; ++ cck_rx_ver2_max_index = i; ++ } ++ else ++ { ++ tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb; ++ cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i; ++ } ++ } ++ else ++ { ++ if(cur_cck_pwdb > tmp_cck_max_pwdb) ++ { ++ tmp_cck_sec_pwdb = tmp_cck_max_pwdb; ++ cck_rx_ver2_sec_index = cck_rx_ver2_max_index; ++ tmp_cck_max_pwdb = cur_cck_pwdb; ++ cck_rx_ver2_max_index = i; ++ } ++ else if(cur_cck_pwdb == tmp_cck_max_pwdb) ++ { // let sec and min point to the different index ++ tmp_cck_sec_pwdb = cur_cck_pwdb; ++ cck_rx_ver2_sec_index = i; ++ } ++ else if((cur_cck_pwdb < tmp_cck_max_pwdb) &&(cur_cck_pwdb > tmp_cck_sec_pwdb)) ++ { ++ tmp_cck_sec_pwdb = cur_cck_pwdb; ++ cck_rx_ver2_sec_index = i; ++ } ++ else if(cur_cck_pwdb == tmp_cck_sec_pwdb) ++ { ++ if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb) ++ { // let sec and min point to the different index ++ tmp_cck_sec_pwdb = cur_cck_pwdb; ++ cck_rx_ver2_sec_index = i; ++ } ++ else ++ { ++ // This case we don't need to set any index ++ } ++ } ++ else if((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb)) ++ { ++ // This case we don't need to set any index ++ } ++ else if(cur_cck_pwdb == tmp_cck_min_pwdb) ++ { ++ if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb) ++ { // let sec and min point to the different index ++ tmp_cck_min_pwdb = cur_cck_pwdb; ++ cck_rx_ver2_min_index = i; ++ } ++ else ++ { ++ // This case we don't need to set any index ++ } ++ } ++ else if(cur_cck_pwdb < tmp_cck_min_pwdb) ++ { ++ tmp_cck_min_pwdb = cur_cck_pwdb; ++ cck_rx_ver2_min_index = i; ++ } ++ } ++ ++ } ++ } ++ } ++ ++ ++ // Set CCK Rx path ++ // reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path. ++ update_cck_rx_path = 0; ++ if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) ++ { ++ cck_default_Rx = cck_rx_ver2_max_index; ++ cck_optional_Rx = cck_rx_ver2_sec_index; ++ if(tmp_cck_max_pwdb != -64) ++ update_cck_rx_path = 1; ++ } ++ ++ if(tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2) ++ { ++ if((tmp_max_rssi - tmp_min_rssi) >= DM_RxPathSelTable.diff_TH) ++ { ++ //record the enabled rssi threshold ++ DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5; ++ //disable the BB Rx path, OFDM ++ rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<>i) & 0x1) //disabled rf ++ { ++ if(tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i]) ++ { ++ //enable the BB Rx path ++ //DbgPrint("RF-%d is enabled. \n", 0x1<= KERNEL_VERSION(2,6,20) ++ queue_delayed_work(priv->priv_wq,&priv->rfpath_check_wq,0); ++#else ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++ schedule_task(&priv->rfpath_check_wq); ++#else ++ queue_work(priv->priv_wq,&priv->rfpath_check_wq); ++#endif ++#endif ++} /* dm_CheckRxRFPath */ ++ ++ ++static void dm_init_fsync (struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ priv->ieee80211->fsync_time_interval = 500; ++ priv->ieee80211->fsync_rate_bitmap = 0x0f000800; ++ priv->ieee80211->fsync_rssi_threshold = 30; ++#ifdef RTL8190P ++ priv->ieee80211->bfsync_enable = true; ++#else ++ priv->ieee80211->bfsync_enable = false; ++#endif ++ priv->ieee80211->fsync_multiple_timeinterval = 3; ++ priv->ieee80211->fsync_firstdiff_ratethreshold= 100; ++ priv->ieee80211->fsync_seconddiff_ratethreshold= 200; ++ priv->ieee80211->fsync_state = Default_Fsync; ++ priv->framesyncMonitor = 1; // current default 0xc38 monitor on ++ ++ init_timer(&priv->fsync_timer); ++ priv->fsync_timer.data = (unsigned long)dev; ++ priv->fsync_timer.function = dm_fsync_timer_callback; ++} ++ ++ ++static void dm_deInit_fsync(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ del_timer_sync(&priv->fsync_timer); ++} ++ ++void dm_fsync_timer_callback(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ struct r8192_priv *priv = ieee80211_priv((struct net_device *)data); ++ u32 rate_index, rate_count = 0, rate_count_diff=0; ++ bool bSwitchFromCountDiff = false; ++ bool bDoubleTimeInterval = false; ++ ++ if( priv->ieee80211->state == IEEE80211_LINKED && ++ priv->ieee80211->bfsync_enable && ++ (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) ++ { ++ // Count rate 54, MCS [7], [12, 13, 14, 15] ++ u32 rate_bitmap; ++ for(rate_index = 0; rate_index <= 27; rate_index++) ++ { ++ rate_bitmap = 1 << rate_index; ++ if(priv->ieee80211->fsync_rate_bitmap & rate_bitmap) ++ rate_count+= priv->stats.received_rate_histogram[1][rate_index]; ++ } ++ ++ if(rate_count < priv->rate_record) ++ rate_count_diff = 0xffffffff - rate_count + priv->rate_record; ++ else ++ rate_count_diff = rate_count - priv->rate_record; ++ if(rate_count_diff < priv->rateCountDiffRecord) ++ { ++ ++ u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff; ++ // Contiune count ++ if(DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold) ++ priv->ContiuneDiffCount++; ++ else ++ priv->ContiuneDiffCount = 0; ++ ++ // Contiune count over ++ if(priv->ContiuneDiffCount >=2) ++ { ++ bSwitchFromCountDiff = true; ++ priv->ContiuneDiffCount = 0; ++ } ++ } ++ else ++ { ++ // Stop contiune count ++ priv->ContiuneDiffCount = 0; ++ } ++ ++ //If Count diff <= FsyncRateCountThreshold ++ if(rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold) ++ { ++ bSwitchFromCountDiff = true; ++ priv->ContiuneDiffCount = 0; ++ } ++ priv->rate_record = rate_count; ++ priv->rateCountDiffRecord = rate_count_diff; ++ RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync); ++ // if we never receive those mcs rate and rssi > 30 % then switch fsyn ++ if(priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff) ++ { ++ bDoubleTimeInterval = true; ++ priv->bswitch_fsync = !priv->bswitch_fsync; ++ if(priv->bswitch_fsync) ++ { ++ #ifdef RTL8190P ++ write_nic_byte(dev,0xC36, 0x00); ++ #else ++ write_nic_byte(dev,0xC36, 0x1c); ++ #endif ++ write_nic_byte(dev, 0xC3e, 0x90); ++ } ++ else ++ { ++ #ifdef RTL8190P ++ write_nic_byte(dev, 0xC36, 0x40); ++ #else ++ write_nic_byte(dev, 0xC36, 0x5c); ++ #endif ++ write_nic_byte(dev, 0xC3e, 0x96); ++ } ++ } ++ else if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold) ++ { ++ if(priv->bswitch_fsync) ++ { ++ priv->bswitch_fsync = false; ++ #ifdef RTL8190P ++ write_nic_byte(dev, 0xC36, 0x40); ++ #else ++ write_nic_byte(dev, 0xC36, 0x5c); ++ #endif ++ write_nic_byte(dev, 0xC3e, 0x96); ++ } ++ } ++ if(bDoubleTimeInterval){ ++ if(timer_pending(&priv->fsync_timer)) ++ del_timer_sync(&priv->fsync_timer); ++ priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval); ++ add_timer(&priv->fsync_timer); ++ } ++ else{ ++ if(timer_pending(&priv->fsync_timer)) ++ del_timer_sync(&priv->fsync_timer); ++ priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval); ++ add_timer(&priv->fsync_timer); ++ } ++ } ++ else ++ { ++ // Let Register return to default value; ++ if(priv->bswitch_fsync) ++ { ++ priv->bswitch_fsync = false; ++ #ifdef RTL8190P ++ write_nic_byte(dev, 0xC36, 0x40); ++ #else ++ write_nic_byte(dev, 0xC36, 0x5c); ++ #endif ++ write_nic_byte(dev, 0xC3e, 0x96); ++ } ++ priv->ContiuneDiffCount = 0; ++ #ifdef RTL8190P ++ write_nic_dword(dev, rOFDM0_RxDetector2, 0x164052cd); ++ #else ++ write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); ++ #endif ++ } ++ RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount); ++ RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync); ++} ++ ++static void dm_StartHWFsync(struct net_device *dev) ++{ ++ RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__); ++ write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf); ++ write_nic_byte(dev, 0xc3b, 0x41); ++} ++ ++static void dm_EndSWFsync(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__); ++ del_timer_sync(&(priv->fsync_timer)); ++ ++ // Let Register return to default value; ++ if(priv->bswitch_fsync) ++ { ++ priv->bswitch_fsync = false; ++ ++ #ifdef RTL8190P ++ write_nic_byte(dev, 0xC36, 0x40); ++ #else ++ write_nic_byte(dev, 0xC36, 0x5c); ++#endif ++ ++ write_nic_byte(dev, 0xC3e, 0x96); ++ } ++ ++ priv->ContiuneDiffCount = 0; ++#ifndef RTL8190P ++ write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); ++#endif ++ ++} ++ ++static void dm_StartSWFsync(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u32 rateIndex; ++ u32 rateBitmap; ++ ++ RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__); ++ // Initial rate record to zero, start to record. ++ priv->rate_record = 0; ++ // Initial contiune diff count to zero, start to record. ++ priv->ContiuneDiffCount = 0; ++ priv->rateCountDiffRecord = 0; ++ priv->bswitch_fsync = false; ++ ++ if(priv->ieee80211->mode == WIRELESS_MODE_N_24G) ++ { ++ priv->ieee80211->fsync_firstdiff_ratethreshold= 600; ++ priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff; ++ } ++ else ++ { ++ priv->ieee80211->fsync_firstdiff_ratethreshold= 200; ++ priv->ieee80211->fsync_seconddiff_ratethreshold = 200; ++ } ++ for(rateIndex = 0; rateIndex <= 27; rateIndex++) ++ { ++ rateBitmap = 1 << rateIndex; ++ if(priv->ieee80211->fsync_rate_bitmap & rateBitmap) ++ priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex]; ++ } ++ if(timer_pending(&priv->fsync_timer)) ++ del_timer_sync(&priv->fsync_timer); ++ priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval); ++ add_timer(&priv->fsync_timer); ++ ++#ifndef RTL8190P ++ write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd); ++#endif ++ ++} ++ ++static void dm_EndHWFsync(struct net_device *dev) ++{ ++ RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__); ++ write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); ++ write_nic_byte(dev, 0xc3b, 0x49); ++ ++} ++ ++void dm_check_fsync(struct net_device *dev) ++{ ++#define RegC38_Default 0 ++#define RegC38_NonFsync_Other_AP 1 ++#define RegC38_Fsync_AP_BCM 2 ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ //u32 framesyncC34; ++ static u8 reg_c38_State=RegC38_Default; ++ static u32 reset_cnt=0; ++ ++ RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval); ++ RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold); ++ ++ if( priv->ieee80211->state == IEEE80211_LINKED && ++ (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) ++ { ++ if(priv->ieee80211->bfsync_enable == 0) ++ { ++ switch(priv->ieee80211->fsync_state) ++ { ++ case Default_Fsync: ++ dm_StartHWFsync(dev); ++ priv->ieee80211->fsync_state = HW_Fsync; ++ break; ++ case SW_Fsync: ++ dm_EndSWFsync(dev); ++ dm_StartHWFsync(dev); ++ priv->ieee80211->fsync_state = HW_Fsync; ++ break; ++ case HW_Fsync: ++ default: ++ break; ++ } ++ } ++ else ++ { ++ switch(priv->ieee80211->fsync_state) ++ { ++ case Default_Fsync: ++ dm_StartSWFsync(dev); ++ priv->ieee80211->fsync_state = SW_Fsync; ++ break; ++ case HW_Fsync: ++ dm_EndHWFsync(dev); ++ dm_StartSWFsync(dev); ++ priv->ieee80211->fsync_state = SW_Fsync; ++ break; ++ case SW_Fsync: ++ default: ++ break; ++ ++ } ++ } ++ if(priv->framesyncMonitor) ++ { ++ if(reg_c38_State != RegC38_Fsync_AP_BCM) ++ { //For broadcom AP we write different default value ++ #ifdef RTL8190P ++ write_nic_byte(dev, rOFDM0_RxDetector3, 0x15); ++ #else ++ write_nic_byte(dev, rOFDM0_RxDetector3, 0x95); ++ #endif ++ ++ reg_c38_State = RegC38_Fsync_AP_BCM; ++ } ++ } ++ } ++ else ++ { ++ switch(priv->ieee80211->fsync_state) ++ { ++ case HW_Fsync: ++ dm_EndHWFsync(dev); ++ priv->ieee80211->fsync_state = Default_Fsync; ++ break; ++ case SW_Fsync: ++ dm_EndSWFsync(dev); ++ priv->ieee80211->fsync_state = Default_Fsync; ++ break; ++ case Default_Fsync: ++ default: ++ break; ++ } ++ ++ if(priv->framesyncMonitor) ++ { ++ if(priv->ieee80211->state == IEEE80211_LINKED) ++ { ++ if(priv->undecorated_smoothed_pwdb <= RegC38_TH) ++ { ++ if(reg_c38_State != RegC38_NonFsync_Other_AP) ++ { ++ #ifdef RTL8190P ++ write_nic_byte(dev, rOFDM0_RxDetector3, 0x10); ++ #else ++ write_nic_byte(dev, rOFDM0_RxDetector3, 0x90); ++ #endif ++ ++ reg_c38_State = RegC38_NonFsync_Other_AP; ++ #if 0//cosa ++ if (Adapter->HardwareType == HARDWARE_TYPE_RTL8190P) ++ DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x10); ++ else ++ DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x90); ++ #endif ++ } ++ } ++ else if(priv->undecorated_smoothed_pwdb >= (RegC38_TH+5)) ++ { ++ if(reg_c38_State) ++ { ++ write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); ++ reg_c38_State = RegC38_Default; ++ //DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x \n", pHalData->framesync); ++ } ++ } ++ } ++ else ++ { ++ if(reg_c38_State) ++ { ++ write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); ++ reg_c38_State = RegC38_Default; ++ //DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x \n", pHalData->framesync); ++ } ++ } ++ } ++ } ++ if(priv->framesyncMonitor) ++ { ++ if(priv->reset_count != reset_cnt) ++ { //After silent reset, the reg_c38_State will be returned to default value ++ write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); ++ reg_c38_State = RegC38_Default; ++ reset_cnt = priv->reset_count; ++ //DbgPrint("reg_c38_State = 0 for silent reset. \n"); ++ } ++ } ++ else ++ { ++ if(reg_c38_State) ++ { ++ write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); ++ reg_c38_State = RegC38_Default; ++ //DbgPrint("framesync no monitor, write 0xc38 = 0x%x \n", pHalData->framesync); ++ } ++ } ++} ++ ++#if 0 ++/*----------------------------------------------------------------------------- ++ * Function: DM_CheckLBusStatus() ++ * ++ * Overview: For 9x series, we must make sure LBUS is active for IO. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 02/22/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++extern s1Byte DM_CheckLBusStatus(IN PADAPTER Adapter) ++{ ++ PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; ++ ++#if (HAL_CODE_BASE & RTL819X) ++ ++#if (HAL_CODE_BASE == RTL8192) ++ ++#if( DEV_BUS_TYPE==PCI_INTERFACE) ++ //return (pMgntInfo->bLbusEnable); // For debug only ++ return TRUE; ++#endif ++ ++#if( DEV_BUS_TYPE==USB_INTERFACE) ++ return TRUE; ++#endif ++ ++#endif // #if (HAL_CODE_BASE == RTL8192) ++ ++#if (HAL_CODE_BASE == RTL8190) ++ return TRUE; ++#endif // #if (HAL_CODE_BASE == RTL8190) ++ ++#endif // #if (HAL_CODE_BASE & RTL819X) ++} /* DM_CheckLBusStatus */ ++ ++#endif ++ ++/*----------------------------------------------------------------------------- ++ * Function: dm_shadow_init() ++ * ++ * Overview: Store all NIC MAC/BB register content. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/29/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++void dm_shadow_init(struct net_device *dev) ++{ ++ u8 page; ++ u16 offset; ++ ++ for (page = 0; page < 5; page++) ++ for (offset = 0; offset < 256; offset++) ++ { ++ dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256); ++ //DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]); ++ } ++ ++ for (page = 8; page < 11; page++) ++ for (offset = 0; offset < 256; offset++) ++ dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256); ++ ++ for (page = 12; page < 15; page++) ++ for (offset = 0; offset < 256; offset++) ++ dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256); ++ ++} /* dm_shadow_init */ ++ ++/*---------------------------Define function prototype------------------------*/ ++/*----------------------------------------------------------------------------- ++ * Function: DM_DynamicTxPower() ++ * ++ * Overview: Detect Signal strength to control TX Registry ++ Tx Power Control For Near/Far Range ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 03/06/2008 Jacken Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++static void dm_init_dynamic_txpower(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. ++ priv->ieee80211->bdynamic_txpower_enable = true; //Default to enable Tx Power Control ++ priv->bLastDTPFlag_High = false; ++ priv->bLastDTPFlag_Low = false; ++ priv->bDynamicTxHighPower = false; ++ priv->bDynamicTxLowPower = false; ++} ++ ++static void dm_dynamic_txpower(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ unsigned int txhipower_threshhold=0; ++ unsigned int txlowpower_threshold=0; ++ if(priv->ieee80211->bdynamic_txpower_enable != true) ++ { ++ priv->bDynamicTxHighPower = false; ++ priv->bDynamicTxLowPower = false; ++ return; ++ } ++ //printk("priv->ieee80211->current_network.unknown_cap_exist is %d ,priv->ieee80211->current_network.broadcom_cap_exist is %d\n",priv->ieee80211->current_network.unknown_cap_exist,priv->ieee80211->current_network.broadcom_cap_exist); ++ if((priv->ieee80211->current_network.atheros_cap_exist ) && (priv->ieee80211->mode == IEEE_G)){ ++ txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH; ++ txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW; ++ } ++ else ++ { ++ txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH; ++ txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW; ++ } ++ ++// printk("=======>%s(): txhipower_threshhold is %d,txlowpower_threshold is %d\n",__FUNCTION__,txhipower_threshhold,txlowpower_threshold); ++ ++ RT_TRACE(COMP_TXAGC,"priv->undecorated_smoothed_pwdb = %ld \n" , priv->undecorated_smoothed_pwdb); ++ ++ if(priv->ieee80211->state == IEEE80211_LINKED) ++ { ++ if(priv->undecorated_smoothed_pwdb >= txhipower_threshhold) ++ { ++ priv->bDynamicTxHighPower = true; ++ priv->bDynamicTxLowPower = false; ++ } ++ else ++ { ++ // high power state check ++ if(priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower == true) ++ { ++ priv->bDynamicTxHighPower = false; ++ } ++ // low power state check ++ if(priv->undecorated_smoothed_pwdb < 35) ++ { ++ priv->bDynamicTxLowPower = true; ++ } ++ else if(priv->undecorated_smoothed_pwdb >= 40) ++ { ++ priv->bDynamicTxLowPower = false; ++ } ++ } ++ } ++ else ++ { ++ //pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange; ++ priv->bDynamicTxHighPower = false; ++ priv->bDynamicTxLowPower = false; ++ } ++ ++ if( (priv->bDynamicTxHighPower != priv->bLastDTPFlag_High ) || ++ (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low ) ) ++ { ++ RT_TRACE(COMP_TXAGC,"SetTxPowerLevel8190() channel = %d \n" , priv->ieee80211->current_network.channel); ++ ++ ++ rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel); ++ ++ } ++ priv->bLastDTPFlag_High = priv->bDynamicTxHighPower; ++ priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower; ++ ++} /* dm_dynamic_txpower */ ++ ++//added by vivi, for read tx rate and retrycount ++static void dm_check_txrateandretrycount(struct net_device * dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ struct ieee80211_device* ieee = priv->ieee80211; ++ //for 11n tx rate ++// priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg); ++ ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg); ++ //printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate); ++ //for initial tx rate ++// priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg); ++ ieee->softmac_stats.last_packet_rate = read_nic_byte(dev ,Initial_Tx_Rate_Reg); ++ //for tx tx retry count ++// priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg); ++ ieee->softmac_stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg); ++} ++ ++static void dm_send_rssi_tofw(struct net_device *dev) ++{ ++ DCMD_TXCMD_T tx_cmd; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ // If we test chariot, we should stop the TX command ? ++ // Because 92E will always silent reset when we send tx command. We use register ++ // 0x1e0(byte) to botify driver. ++ write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb); ++ return; ++#if 1 ++ tx_cmd.Op = TXCMD_SET_RX_RSSI; ++ tx_cmd.Length = 4; ++ tx_cmd.Value = priv->undecorated_smoothed_pwdb; ++ ++ cmpk_message_handle_tx(dev, (u8*)&tx_cmd, ++ DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T)); ++#endif ++} ++ ++/*---------------------------Define function prototype------------------------*/ ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r8192E_dm.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E_dm.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E_dm.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,320 @@ ++/***************************************************************************** ++ * Copyright(c) 2007, RealTEK Technology Inc. All Right Reserved. ++ * ++ * Module: Hal819xUsbDM.h (RTL8192 Header H File) ++ * ++ * ++ * Note: For dynamic control definition constant structure. ++ * ++ * ++ * Export: ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * 10/04/2007 MHC Create initial version. ++ * ++ *****************************************************************************/ ++ /* Check to see if the file has been included already. */ ++#ifndef __R8192UDM_H__ ++#define __R8192UDM_H__ ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++#define OFDM_Table_Length 19 ++#define CCK_Table_length 12 ++ ++#define DM_DIG_THRESH_HIGH 40 ++#define DM_DIG_THRESH_LOW 35 ++ ++#define DM_DIG_HIGH_PWR_THRESH_HIGH 75 ++#define DM_DIG_HIGH_PWR_THRESH_LOW 70 ++ ++#define BW_AUTO_SWITCH_HIGH_LOW 25 ++#define BW_AUTO_SWITCH_LOW_HIGH 30 ++ ++#define DM_check_fsync_time_interval 500 ++ ++ ++#define DM_DIG_BACKOFF 12 ++#define DM_DIG_MAX 0x36 ++#define DM_DIG_MIN 0x1c ++#define DM_DIG_MIN_Netcore 0x12 ++ ++#define RxPathSelection_SS_TH_low 30 ++#define RxPathSelection_diff_TH 18 ++ ++#define RateAdaptiveTH_High 50 ++#define RateAdaptiveTH_Low_20M 30 ++#define RateAdaptiveTH_Low_40M 10 ++#define VeryLowRSSI 15 ++#define CTSToSelfTHVal 35 ++ ++//defined by vivi, for tx power track ++#define E_FOR_TX_POWER_TRACK 300 ++//Dynamic Tx Power Control Threshold ++#define TX_POWER_NEAR_FIELD_THRESH_HIGH 68 ++#define TX_POWER_NEAR_FIELD_THRESH_LOW 62 ++//added by amy for atheros AP ++#define TX_POWER_ATHEROAP_THRESH_HIGH 78 ++#define TX_POWER_ATHEROAP_THRESH_LOW 72 ++ ++//defined by vivi, for showing on UI. Newer firmware has changed to 0x1e0 ++#define Current_Tx_Rate_Reg 0x1e0//0x1b8 ++#define Initial_Tx_Rate_Reg 0x1e1 //0x1b9 ++#define Tx_Retry_Count_Reg 0x1ac ++#define RegC38_TH 20 ++#if 0 ++//---------------------------------------------------------------------------- ++// 8190 Rate Adaptive Table Register (offset 0x320, 4 byte) ++//---------------------------------------------------------------------------- ++ ++//CCK ++#define RATR_1M 0x00000001 ++#define RATR_2M 0x00000002 ++#define RATR_55M 0x00000004 ++#define RATR_11M 0x00000008 ++//OFDM ++#define RATR_6M 0x00000010 ++#define RATR_9M 0x00000020 ++#define RATR_12M 0x00000040 ++#define RATR_18M 0x00000080 ++#define RATR_24M 0x00000100 ++#define RATR_36M 0x00000200 ++#define RATR_48M 0x00000400 ++#define RATR_54M 0x00000800 ++//MCS 1 Spatial Stream ++#define RATR_MCS0 0x00001000 ++#define RATR_MCS1 0x00002000 ++#define RATR_MCS2 0x00004000 ++#define RATR_MCS3 0x00008000 ++#define RATR_MCS4 0x00010000 ++#define RATR_MCS5 0x00020000 ++#define RATR_MCS6 0x00040000 ++#define RATR_MCS7 0x00080000 ++//MCS 2 Spatial Stream ++#define RATR_MCS8 0x00100000 ++#define RATR_MCS9 0x00200000 ++#define RATR_MCS10 0x00400000 ++#define RATR_MCS11 0x00800000 ++#define RATR_MCS12 0x01000000 ++#define RATR_MCS13 0x02000000 ++#define RATR_MCS14 0x04000000 ++#define RATR_MCS15 0x08000000 ++// ALL CCK Rate ++#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M ++#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\ ++ |RATR_36M|RATR_48M|RATR_54M ++#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \ ++ RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 ++#endif ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++/*------------------------------Define structure----------------------------*/ ++/* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */ ++typedef struct _dynamic_initial_gain_threshold_ ++{ ++ u8 dig_enable_flag; ++ u8 dig_algorithm; ++ u8 dbg_mode; ++ u8 dig_algorithm_switch; ++ ++ long rssi_low_thresh; ++ long rssi_high_thresh; ++ ++ long rssi_high_power_lowthresh; ++ long rssi_high_power_highthresh; ++ ++ u8 dig_state; ++ u8 dig_highpwr_state; ++ u8 cur_connect_state; ++ u8 pre_connect_state; ++ ++ u8 curpd_thstate; ++ u8 prepd_thstate; ++ u8 curcs_ratio_state; ++ u8 precs_ratio_state; ++ ++ u32 pre_ig_value; ++ u32 cur_ig_value; ++ ++ u8 backoff_val; ++ u8 rx_gain_range_max; ++ u8 rx_gain_range_min; ++ bool initialgain_lowerbound_state; ++ ++ long rssi_val; ++}dig_t; ++ ++typedef enum tag_dynamic_init_gain_state_definition ++{ ++ DM_STA_DIG_OFF = 0, ++ DM_STA_DIG_ON, ++ DM_STA_DIG_MAX ++}dm_dig_sta_e; ++ ++ ++/* 2007/10/08 MH Define RATR state. */ ++typedef enum tag_dynamic_ratr_state_definition ++{ ++ DM_RATR_STA_HIGH = 0, ++ DM_RATR_STA_MIDDLE = 1, ++ DM_RATR_STA_LOW = 2, ++ DM_RATR_STA_MAX ++}dm_ratr_sta_e; ++ ++/* 2007/10/11 MH Define DIG operation type. */ ++typedef enum tag_dynamic_init_gain_operation_type_definition ++{ ++ DIG_TYPE_THRESH_HIGH = 0, ++ DIG_TYPE_THRESH_LOW = 1, ++ DIG_TYPE_THRESH_HIGHPWR_HIGH = 2, ++ DIG_TYPE_THRESH_HIGHPWR_LOW = 3, ++ DIG_TYPE_DBG_MODE = 4, ++ DIG_TYPE_RSSI = 5, ++ DIG_TYPE_ALGORITHM = 6, ++ DIG_TYPE_BACKOFF = 7, ++ DIG_TYPE_PWDB_FACTOR = 8, ++ DIG_TYPE_RX_GAIN_MIN = 9, ++ DIG_TYPE_RX_GAIN_MAX = 10, ++ DIG_TYPE_ENABLE = 20, ++ DIG_TYPE_DISABLE = 30, ++ DIG_OP_TYPE_MAX ++}dm_dig_op_e; ++ ++typedef enum tag_dig_algorithm_definition ++{ ++ DIG_ALGO_BY_FALSE_ALARM = 0, ++ DIG_ALGO_BY_RSSI = 1, ++ DIG_ALGO_MAX ++}dm_dig_alg_e; ++ ++typedef enum tag_dig_dbgmode_definition ++{ ++ DIG_DBG_OFF = 0, ++ DIG_DBG_ON = 1, ++ DIG_DBG_MAX ++}dm_dig_dbg_e; ++ ++typedef enum tag_dig_connect_definition ++{ ++ DIG_DISCONNECT = 0, ++ DIG_CONNECT = 1, ++ DIG_CONNECT_MAX ++}dm_dig_connect_e; ++ ++typedef enum tag_dig_packetdetection_threshold_definition ++{ ++ DIG_PD_AT_LOW_POWER = 0, ++ DIG_PD_AT_NORMAL_POWER = 1, ++ DIG_PD_AT_HIGH_POWER = 2, ++ DIG_PD_MAX ++}dm_dig_pd_th_e; ++ ++typedef enum tag_dig_cck_cs_ratio_state_definition ++{ ++ DIG_CS_RATIO_LOWER = 0, ++ DIG_CS_RATIO_HIGHER = 1, ++ DIG_CS_MAX ++}dm_dig_cs_ratio_e; ++typedef struct _Dynamic_Rx_Path_Selection_ ++{ ++ u8 Enable; ++ u8 DbgMode; ++ u8 cck_method; ++ u8 cck_Rx_path; ++ ++ u8 SS_TH_low; ++ u8 diff_TH; ++ u8 disabledRF; ++ u8 reserved; ++ ++ u8 rf_rssi[4]; ++ u8 rf_enable_rssi_th[4]; ++ long cck_pwdb_sta[4]; ++}DRxPathSel; ++ ++typedef enum tag_CCK_Rx_Path_Method_Definition ++{ ++ CCK_Rx_Version_1 = 0, ++ CCK_Rx_Version_2= 1, ++ CCK_Rx_Version_MAX ++}DM_CCK_Rx_Path_Method; ++ ++typedef enum tag_DM_DbgMode_Definition ++{ ++ DM_DBG_OFF = 0, ++ DM_DBG_ON = 1, ++ DM_DBG_MAX ++}DM_DBG_E; ++ ++typedef struct tag_Tx_Config_Cmd_Format ++{ ++ u32 Op; /* Command packet type. */ ++ u32 Length; /* Command packet length. */ ++ u32 Value; ++}DCMD_TXCMD_T, *PDCMD_TXCMD_T; ++/*------------------------------Define structure----------------------------*/ ++ ++ ++/*------------------------Export global variable----------------------------*/ ++extern dig_t dm_digtable; ++extern u8 dm_shadow[16][256]; ++extern DRxPathSel DM_RxPathSelTable; ++/*------------------------Export global variable----------------------------*/ ++ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++ ++/*--------------------------Exported Function prototype---------------------*/ ++/*--------------------------Exported Function prototype---------------------*/ ++extern void init_hal_dm(struct net_device *dev); ++extern void deinit_hal_dm(struct net_device *dev); ++ ++extern void hal_dm_watchdog(struct net_device *dev); ++ ++ ++extern void init_rate_adaptive(struct net_device *dev); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++extern void dm_txpower_trackingcallback(struct work_struct *work); ++#else ++extern void dm_txpower_trackingcallback(struct net_device *dev); ++#endif ++ ++extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14); ++extern void dm_restore_dynamic_mechanism_state(struct net_device *dev); ++extern void dm_backup_dynamic_mechanism_state(struct net_device *dev); ++extern void dm_change_dynamic_initgain_thresh(struct net_device *dev, ++ u32 dm_type, ++ u32 dm_value); ++extern void DM_ChangeFsyncSetting(struct net_device *dev, ++ s32 DM_Type, ++ s32 DM_Value); ++extern void dm_force_tx_fw_info(struct net_device *dev, ++ u32 force_type, ++ u32 force_value); ++extern void dm_init_edca_turbo(struct net_device *dev); ++extern void dm_rf_operation_test_callback(unsigned long data); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work); ++#else ++extern void dm_rf_pathcheck_workitemcallback(struct net_device *dev); ++#endif ++extern void dm_fsync_timer_callback(unsigned long data); ++#if 0 ++extern bool dm_check_lbus_status(struct net_device *dev); ++#endif ++extern void dm_check_fsync(struct net_device *dev); ++extern void dm_shadow_init(struct net_device *dev); ++extern void dm_initialize_txpower_tracking(struct net_device *dev); ++ ++ ++#endif /*__R8192UDM_H__ */ ++ ++ ++/* End of r8192U_dm.h */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r8192E.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,1554 @@ ++/* ++ This is part of rtl8187 OpenSource driver. ++ Copyright (C) Andrea Merello 2004-2005 ++ Released under the terms of GPL (General Public Licence) ++ ++ Parts of this driver are based on the GPL part of the ++ official realtek driver ++ ++ Parts of this driver are based on the rtl8192 driver skeleton ++ from Patric Schenke & Andres Salomon ++ ++ Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver ++ ++ We want to tanks the Authors of those projects and the Ndiswrapper ++ project Authors. ++*/ ++ ++#ifndef R819xU_H ++#define R819xU_H ++ ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include ++#include ++#include //for rtnl_lock() ++#include ++#include ++#include // Necessary because we use the proc fs ++#include ++#include ++#include ++#include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) ++#include ++#endif ++#include "ieee80211.h" ++ ++ ++ ++ ++#define RTL819xE_MODULE_NAME "rtl819xE" ++//added for HW security, john.0629 ++#define FALSE 0 ++#define TRUE 1 ++#define MAX_KEY_LEN 61 ++#define KEY_BUF_SIZE 5 ++ ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++// Rx smooth factor ++#define Rx_Smooth_Factor 20 ++/* 2007/06/04 MH Define sliding window for RSSI history. */ ++#define PHY_RSSI_SLID_WIN_MAX 100 ++#define PHY_Beacon_RSSI_SLID_WIN_MAX 10 ++ ++#define IC_VersionCut_D 0x3 ++#define IC_VersionCut_E 0x4 ++ ++#if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb. ++#define DMESG(x,a...) printk(KERN_INFO RTL819xE_MODULE_NAME ": " x "\n", ## a) ++#define DMESGW(x,a...) printk(KERN_WARNING RTL819xE_MODULE_NAME ": WW:" x "\n", ## a) ++#define DMESGE(x,a...) printk(KERN_WARNING RTL819xE_MODULE_NAME ": EE:" x "\n", ## a) ++#else ++#define DMESG(x,a...) ++#define DMESGW(x,a...) ++#define DMESGE(x,a...) ++extern u32 rt_global_debug_component; ++#define RT_TRACE(component, x, args...) \ ++do { if(rt_global_debug_component & component) \ ++ printk(KERN_DEBUG RTL819xE_MODULE_NAME ":" x "\n" , \ ++ ##args);\ ++}while(0); ++ ++#define COMP_TRACE BIT0 // For function call tracing. ++#define COMP_DBG BIT1 // Only for temporary debug message. ++#define COMP_INIT BIT2 // during driver initialization / halt / reset. ++ ++ ++#define COMP_RECV BIT3 // Reveive part data path. ++#define COMP_SEND BIT4 // Send part path. ++#define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02. ++#define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related. ++#define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS. ++#define COMP_SWBW BIT8 // For bandwidth switch. ++#define COMP_SEC BIT9// For Security. ++ ++ ++#define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21. ++#define COMP_QOS BIT11 // For QoS. ++ ++#define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling ++#define COMP_RXDESC BIT13 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15. ++#define COMP_PHY BIT14 ++#define COMP_DIG BIT15 // For DIG, 2006.09.25, by rcnjko. ++#define COMP_TXAGC BIT16 // For Tx power, 060928, by rcnjko. ++#define COMP_HALDM BIT17 // For HW Dynamic Mechanism, 061010, by rcnjko. ++#define COMP_POWER_TRACKING BIT18 //FOR 8190 TX POWER TRACKING ++#define COMP_EVENTS BIT19 // Event handling ++ ++#define COMP_RF BIT20 // For RF. ++//1!!!!!!!!!!!!!!!!!!!!!!!!!!! ++//1//1Attention Please!!!<11n or 8190 specific code should be put below this line> ++//1!!!!!!!!!!!!!!!!!!!!!!!!!!! ++ ++#define COMP_FIRMWARE BIT21 //for firmware downloading ++#define COMP_HT BIT22 // For 802.11n HT related information. by Emily 2006-8-11 ++ ++#define COMP_RESET BIT23 ++#define COMP_CMDPKT BIT24 ++#define COMP_SCAN BIT25 ++#define COMP_IPS BIT26 ++#define COMP_DOWN BIT27 // for rm driver module ++#define COMP_INTR BIT28 // for interrupt ++#define COMP_ERR BIT31 // for error out, always on ++#endif ++ ++#define RTL819x_DEBUG ++#ifdef RTL819x_DEBUG ++#define assert(expr) \ ++ if (!(expr)) { \ ++ printk( "Assertion failed! %s,%s,%s,line=%d\n", \ ++ #expr,__FILE__,__FUNCTION__,__LINE__); \ ++ } ++//wb added to debug out data buf ++//if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA ++#define RT_DEBUG_DATA(level, data, datalen) \ ++ do{ if ((rt_global_debug_component & (level)) == (level)) \ ++ { \ ++ int i; \ ++ u8* pdata = (u8*) data; \ ++ printk(KERN_DEBUG RTL819xE_MODULE_NAME ": %s()\n", __FUNCTION__); \ ++ for(i=0; i<(int)(datalen); i++) \ ++ { \ ++ printk("%2x ", pdata[i]); \ ++ if ((i+1)%16 == 0) printk("\n"); \ ++ } \ ++ printk("\n"); \ ++ } \ ++ } while (0) ++#else ++#define assert(expr) do {} while (0) ++#define RT_DEBUG_DATA(level, data, datalen) do {} while(0) ++#endif /* RTL8169_DEBUG */ ++ ++ ++// ++// Queue Select Value in TxDesc ++// ++#define QSLT_BK 0x1 ++#define QSLT_BE 0x0 ++#define QSLT_VI 0x4 ++#define QSLT_VO 0x6 ++#define QSLT_BEACON 0x10 ++#define QSLT_HIGH 0x11 ++#define QSLT_MGNT 0x12 ++#define QSLT_CMD 0x13 ++ ++#define DESC90_RATE1M 0x00 ++#define DESC90_RATE2M 0x01 ++#define DESC90_RATE5_5M 0x02 ++#define DESC90_RATE11M 0x03 ++#define DESC90_RATE6M 0x04 ++#define DESC90_RATE9M 0x05 ++#define DESC90_RATE12M 0x06 ++#define DESC90_RATE18M 0x07 ++#define DESC90_RATE24M 0x08 ++#define DESC90_RATE36M 0x09 ++#define DESC90_RATE48M 0x0a ++#define DESC90_RATE54M 0x0b ++#define DESC90_RATEMCS0 0x00 ++#define DESC90_RATEMCS1 0x01 ++#define DESC90_RATEMCS2 0x02 ++#define DESC90_RATEMCS3 0x03 ++#define DESC90_RATEMCS4 0x04 ++#define DESC90_RATEMCS5 0x05 ++#define DESC90_RATEMCS6 0x06 ++#define DESC90_RATEMCS7 0x07 ++#define DESC90_RATEMCS8 0x08 ++#define DESC90_RATEMCS9 0x09 ++#define DESC90_RATEMCS10 0x0a ++#define DESC90_RATEMCS11 0x0b ++#define DESC90_RATEMCS12 0x0c ++#define DESC90_RATEMCS13 0x0d ++#define DESC90_RATEMCS14 0x0e ++#define DESC90_RATEMCS15 0x0f ++#define DESC90_RATEMCS32 0x20 ++ ++#define RTL819X_DEFAULT_RF_TYPE RF_1T2R ++#define EEPROM_Default_LegacyHTTxPowerDiff 0x4 ++#define IEEE80211_WATCH_DOG_TIME 2000 ++ ++/* For rtl819x */ ++typedef struct _tx_desc_819x_pci { ++ //DWORD 0 ++ u16 PktSize; ++ u8 Offset; ++ u8 Reserved1:3; ++ u8 CmdInit:1; ++ u8 LastSeg:1; ++ u8 FirstSeg:1; ++ u8 LINIP:1; ++ u8 OWN:1; ++ ++ //DWORD 1 ++ u8 TxFWInfoSize; ++ u8 RATid:3; ++ u8 DISFB:1; ++ u8 USERATE:1; ++ u8 MOREFRAG:1; ++ u8 NoEnc:1; ++ u8 PIFS:1; ++ u8 QueueSelect:5; ++ u8 NoACM:1; ++ u8 Resv:2; ++ u8 SecCAMID:5; ++ u8 SecDescAssign:1; ++ u8 SecType:2; ++ ++ //DWORD 2 ++ u16 TxBufferSize; ++ u8 PktId:7; ++ u8 Resv1:1; ++ u8 Reserved2; ++ ++ //DWORD 3 ++ u32 TxBuffAddr; ++ ++ //DWORD 4 ++ u32 NextDescAddress; ++ ++ //DWORD 5,6,7 ++ u32 Reserved5; ++ u32 Reserved6; ++ u32 Reserved7; ++}tx_desc_819x_pci, *ptx_desc_819x_pci; ++ ++ ++typedef struct _tx_desc_cmd_819x_pci { ++ //DWORD 0 ++ u16 PktSize; ++ u8 Reserved1; ++ u8 CmdType:3; ++ u8 CmdInit:1; ++ u8 LastSeg:1; ++ u8 FirstSeg:1; ++ u8 LINIP:1; ++ u8 OWN:1; ++ ++ //DOWRD 1 ++ u16 ElementReport; ++ u16 Reserved2; ++ ++ //DOWRD 2 ++ u16 TxBufferSize; ++ u16 Reserved3; ++ ++ //DWORD 3,4,5 ++ u32 TxBufferAddr; ++ u32 NextDescAddress; ++ u32 Reserved4; ++ u32 Reserved5; ++ u32 Reserved6; ++}tx_desc_cmd_819x_pci, *ptx_desc_cmd_819x_pci; ++ ++ ++typedef struct _tx_fwinfo_819x_pci { ++ //DOWRD 0 ++ u8 TxRate:7; ++ u8 CtsEnable:1; ++ u8 RtsRate:7; ++ u8 RtsEnable:1; ++ u8 TxHT:1; ++ u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS ++ u8 TxBandwidth:1; // This is used for HT MCS rate only. ++ u8 TxSubCarrier:2; // This is used for legacy OFDM rate only. ++ u8 STBC:2; ++ u8 AllowAggregation:1; ++ u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate ++ u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS ++ u8 RtsBandwidth:1; // This is used for HT MCS rate only. ++ u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only. ++ u8 RtsSTBC:2; ++ u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration ++ ++ //DWORD 1 ++ u8 RxMF:2; ++ u8 RxAMD:3; ++ u8 Reserved1:3; ++ u8 Reserved2; ++ u8 Reserved3; ++ u8 Reserved4; ++ ++ //u32 Reserved; ++}tx_fwinfo_819x_pci, *ptx_fwinfo_819x_pci; ++ ++typedef struct rtl8192_rx_info { ++ struct urb *urb; ++ struct net_device *dev; ++ u8 out_pipe; ++}rtl8192_rx_info ; ++typedef struct _rx_desc_819x_pci{ ++ //DOWRD 0 ++ u16 Length:14; ++ u16 CRC32:1; ++ u16 ICV:1; ++ u8 RxDrvInfoSize; ++ u8 Shift:2; ++ u8 PHYStatus:1; ++ u8 SWDec:1; ++ u8 LastSeg:1; ++ u8 FirstSeg:1; ++ u8 EOR:1; ++ u8 OWN:1; ++ ++ //DWORD 1 ++ u32 Reserved2; ++ ++ //DWORD 2 ++ u32 Reserved3; ++ ++ //DWORD 3 ++ u32 BufferAddress; ++ ++}rx_desc_819x_pci, *prx_desc_819x_pci; ++ ++typedef struct _rx_fwinfo_819x_pci{ ++ //DWORD 0 ++ u16 Reserved1:12; ++ u16 PartAggr:1; ++ u16 FirstAGGR:1; ++ u16 Reserved2:2; ++ ++ u8 RxRate:7; ++ u8 RxHT:1; ++ ++ u8 BW:1; ++ u8 SPLCP:1; ++ u8 Reserved3:2; ++ u8 PAM:1; ++ u8 Mcast:1; ++ u8 Bcast:1; ++ u8 Reserved4:1; ++ ++ //DWORD 1 ++ u32 TSFL; ++ ++}rx_fwinfo_819x_pci, *prx_fwinfo_819x_pci; ++ ++#define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */ ++#define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/ ++#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE) ++#define ENCRYPTION_MAX_OVERHEAD 128 ++//#define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb) ++//#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb)) ++#define MAX_FRAGMENT_COUNT 8 ++#define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT) ++ ++#define scrclng 4 // octets for crc32 (FCS, ICV) ++/* 8190 Loopback Mode definition */ ++typedef enum _rtl819x_loopback{ ++ RTL819X_NO_LOOPBACK = 0, ++ RTL819X_MAC_LOOPBACK = 1, ++ RTL819X_DMA_LOOPBACK = 2, ++ RTL819X_CCK_LOOPBACK = 3, ++}rtl819x_loopback_e; ++ ++/* due to rtl8192 firmware */ ++typedef enum _desc_packet_type_e{ ++ DESC_PACKET_TYPE_INIT = 0, ++ DESC_PACKET_TYPE_NORMAL = 1, ++}desc_packet_type_e; ++ ++typedef enum _firmware_source{ ++ FW_SOURCE_IMG_FILE = 0, ++ FW_SOURCE_HEADER_FILE = 1, //from header file ++}firmware_source_e, *pfirmware_source_e; ++ ++typedef enum _firmware_status{ ++ FW_STATUS_0_INIT = 0, ++ FW_STATUS_1_MOVE_BOOT_CODE = 1, ++ FW_STATUS_2_MOVE_MAIN_CODE = 2, ++ FW_STATUS_3_TURNON_CPU = 3, ++ FW_STATUS_4_MOVE_DATA_CODE = 4, ++ FW_STATUS_5_READY = 5, ++}firmware_status_e; ++ ++typedef struct _rt_firmare_seg_container { ++ u16 seg_size; ++ u8 *seg_ptr; ++}fw_seg_container, *pfw_seg_container; ++ ++typedef struct _rt_firmware{ ++ firmware_status_e firmware_status; ++ u16 cmdpacket_frag_thresold; ++#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k ++#define MAX_FW_INIT_STEP 3 ++ u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE]; ++ u16 firmware_buf_size[MAX_FW_INIT_STEP]; ++}rt_firmware, *prt_firmware; ++//+by amy 080507 ++#define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP ++ ++/* Firmware Queue Layout */ ++#define NUM_OF_FIRMWARE_QUEUE 10 ++#define NUM_OF_PAGES_IN_FW 0x100 ++#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa ++#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007 ++#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024 ++#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007 ++#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0 ++#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x2 ++#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10 ++#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0 ++#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4 ++#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd ++#define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000 ++#define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00 ++#define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08 ++#define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10 ++#define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18 ++#define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10 ++#define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08 ++#define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00 ++#define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08 ++ ++//8187B Security ++//#define RWCAM 0xA0 // Software read/write CAM config ++//#define WCAMI 0xA4 // Software write CAM input content ++//#define RCAMO 0xA8 // Output value from CAM according to 0xa0 setting ++#define DCAM 0xAC // Debug CAM Interface ++#define AESMSK_FC 0xB2 // AES Mask register for frame control (0xB2~0xB3). Added by Annie, 2006-03-06. ++ ++ ++#define CAM_CONTENT_COUNT 8 ++//#define CFG_DEFAULT_KEY BIT5 ++#define CFG_VALID BIT15 ++#if 0 ++//---------------------------------------------------------------------------- ++// 8187B WPA Config Register (offset 0xb0, 1 byte) ++//---------------------------------------------------------------------------- ++#define SCR_UseDK 0x01 ++#define SCR_TxSecEnable 0x02 ++#define SCR_RxSecEnable 0x04 ++ ++//---------------------------------------------------------------------------- ++// 8187B CAM Config Setting (offset 0xb0, 1 byte) ++//---------------------------------------------------------------------------- ++#define CAM_VALID 0x8000 ++#define CAM_NOTVALID 0x0000 ++#define CAM_USEDK 0x0020 ++ ++ ++#define CAM_NONE 0x0 ++#define CAM_WEP40 0x01 ++#define CAM_TKIP 0x02 ++#define CAM_AES 0x04 ++#define CAM_WEP104 0x05 ++ ++//#define CAM_SIZE 16 ++#define TOTAL_CAM_ENTRY 16 ++#define CAM_ENTRY_LEN_IN_DW 6 // 6, unit: in u4byte. Added by Annie, 2006-05-25. ++#define CAM_ENTRY_LEN_IN_BYTE (CAM_ENTRY_LEN_IN_DW*sizeof(u32)) // 24, unit: in u1byte. Added by Annie, 2006-05-25. ++ ++#define CAM_CONFIG_USEDK 1 ++#define CAM_CONFIG_NO_USEDK 0 ++ ++#define CAM_WRITE 0x00010000 ++#define CAM_READ 0x00000000 ++#define CAM_POLLINIG 0x80000000 ++ ++//================================================================= ++//================================================================= ++ ++#endif ++#define EPROM_93c46 0 ++#define EPROM_93c56 1 ++ ++#define DEFAULT_FRAG_THRESHOLD 2342U ++#define MIN_FRAG_THRESHOLD 256U ++#define DEFAULT_BEACONINTERVAL 0x64U ++#define DEFAULT_BEACON_ESSID "Rtl819xU" ++ ++#define DEFAULT_SSID "" ++#define DEFAULT_RETRY_RTS 7 ++#define DEFAULT_RETRY_DATA 7 ++#define PRISM_HDR_SIZE 64 ++ ++#define PHY_RSSI_SLID_WIN_MAX 100 ++ ++ ++typedef enum _WIRELESS_MODE { ++ WIRELESS_MODE_UNKNOWN = 0x00, ++ WIRELESS_MODE_A = 0x01, ++ WIRELESS_MODE_B = 0x02, ++ WIRELESS_MODE_G = 0x04, ++ WIRELESS_MODE_AUTO = 0x08, ++ WIRELESS_MODE_N_24G = 0x10, ++ WIRELESS_MODE_N_5G = 0x20 ++} WIRELESS_MODE; ++ ++#define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30 ++ ++typedef struct buffer ++{ ++ struct buffer *next; ++ u32 *buf; ++ dma_addr_t dma; ++ ++} buffer; ++ ++typedef struct rtl_reg_debug{ ++ unsigned int cmd; ++ struct { ++ unsigned char type; ++ unsigned char addr; ++ unsigned char page; ++ unsigned char length; ++ } head; ++ unsigned char buf[0xff]; ++}rtl_reg_debug; ++ ++#if 0 ++ ++typedef struct tx_pendingbuf ++{ ++ struct ieee80211_txb *txb; ++ short ispending; ++ short descfrag; ++} tx_pendigbuf; ++ ++#endif ++ ++typedef struct _rt_9x_tx_rate_history { ++ u32 cck[4]; ++ u32 ofdm[8]; ++ // HT_MCS[0][]: BW=0 SG=0 ++ // HT_MCS[1][]: BW=1 SG=0 ++ // HT_MCS[2][]: BW=0 SG=1 ++ // HT_MCS[3][]: BW=1 SG=1 ++ u32 ht_mcs[4][16]; ++}rt_tx_rahis_t, *prt_tx_rahis_t; ++ ++typedef struct _RT_SMOOTH_DATA_4RF { ++ char elements[4][100];//array to store values ++ u32 index; //index to current array to store ++ u32 TotalNum; //num of valid elements ++ u32 TotalVal[4]; //sum of valid elements ++}RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF; ++ ++typedef enum _tag_TxCmd_Config_Index{ ++ TXCMD_TXRA_HISTORY_CTRL = 0xFF900000, ++ TXCMD_RESET_TX_PKT_BUFF = 0xFF900001, ++ TXCMD_RESET_RX_PKT_BUFF = 0xFF900002, ++ TXCMD_SET_TX_DURATION = 0xFF900003, ++ TXCMD_SET_RX_RSSI = 0xFF900004, ++ TXCMD_SET_TX_PWR_TRACKING = 0xFF900005, ++ TXCMD_XXXX_CTRL, ++}DCMD_TXCMD_OP; ++ ++typedef struct Stats ++{ ++ unsigned long txrdu; ++ unsigned long rxrdu; ++ //unsigned long rxnolast; ++ //unsigned long rxnodata; ++// unsigned long rxreset; ++// unsigned long rxnopointer; ++ unsigned long rxok; ++ unsigned long rxframgment; ++ unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query ++ unsigned long rxurberr; ++ unsigned long rxstaterr; ++ unsigned long rxcrcerrmin;//crc error (0-500) ++ unsigned long rxcrcerrmid;//crc error (500-1000) ++ unsigned long rxcrcerrmax;//crc error (>1000) ++ unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa ++ unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI ++ unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) ++ unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40) ++ unsigned long numpacket_matchbssid; // debug use only. ++ unsigned long numpacket_toself; // debug use only. ++ unsigned long num_process_phyinfo; // debug use only. ++ unsigned long numqry_phystatus; ++ unsigned long numqry_phystatusCCK; ++ unsigned long numqry_phystatusHT; ++ unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate ++ unsigned long txnperr; ++ unsigned long txnpdrop; ++ unsigned long txresumed; ++// unsigned long rxerr; ++ unsigned long rxoverflow; ++ unsigned long rxint; ++ unsigned long txnpokint; ++// unsigned long txhpokint; ++// unsigned long txhperr; ++ unsigned long ints; ++ unsigned long shints; ++ unsigned long txoverflow; ++// unsigned long rxdmafail; ++// unsigned long txbeacon; ++// unsigned long txbeaconerr; ++ unsigned long txlpokint; ++ unsigned long txlpdrop; ++ unsigned long txlperr; ++ unsigned long txbeokint; ++ unsigned long txbedrop; ++ unsigned long txbeerr; ++ unsigned long txbkokint; ++ unsigned long txbkdrop; ++ unsigned long txbkerr; ++ unsigned long txviokint; ++ unsigned long txvidrop; ++ unsigned long txvierr; ++ unsigned long txvookint; ++ unsigned long txvodrop; ++ unsigned long txvoerr; ++ unsigned long txbeaconokint; ++ unsigned long txbeacondrop; ++ unsigned long txbeaconerr; ++ unsigned long txmanageokint; ++ unsigned long txmanagedrop; ++ unsigned long txmanageerr; ++ unsigned long txcmdpktokint; ++ unsigned long txdatapkt; ++ unsigned long txfeedback; ++ unsigned long txfeedbackok; ++ unsigned long txoktotal; ++ unsigned long txokbytestotal; ++ unsigned long txokinperiod; ++ unsigned long txmulticast; ++ unsigned long txbytesmulticast; ++ unsigned long txbroadcast; ++ unsigned long txbytesbroadcast; ++ unsigned long txunicast; ++ unsigned long txbytesunicast; ++ unsigned long rxbytesunicast; ++ unsigned long txfeedbackfail; ++ unsigned long txerrtotal; ++ unsigned long txerrbytestotal; ++ unsigned long txerrmulticast; ++ unsigned long txerrbroadcast; ++ unsigned long txerrunicast; ++ unsigned long txretrycount; ++ unsigned long txfeedbackretry; ++ u8 last_packet_rate; ++ unsigned long slide_signal_strength[100]; ++ unsigned long slide_evm[100]; ++ unsigned long slide_rssi_total; // For recording sliding window's RSSI value ++ unsigned long slide_evm_total; // For recording sliding window's EVM value ++ long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct. ++ long signal_quality; ++ long last_signal_strength_inpercent; ++ long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now. ++ u8 rx_rssi_percentage[4]; ++ u8 rx_evm_percentage[2]; ++ long rxSNRdB[4]; ++ rt_tx_rahis_t txrate; ++ u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi ++ u32 Slide_Beacon_Total; //cosa add for beacon rssi ++ RT_SMOOTH_DATA_4RF cck_adc_pwdb; ++ u32 CurrentShowTxate; ++ ++ ++} Stats; ++ ++ ++// Bandwidth Offset ++#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 ++#define HAL_PRIME_CHNL_OFFSET_LOWER 1 ++#define HAL_PRIME_CHNL_OFFSET_UPPER 2 ++ ++//+by amy 080507 ++ ++typedef struct ChnlAccessSetting { ++ u16 SIFS_Timer; ++ u16 DIFS_Timer; ++ u16 SlotTimeTimer; ++ u16 EIFS_Timer; ++ u16 CWminIndex; ++ u16 CWmaxIndex; ++}*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING; ++ ++typedef struct _BB_REGISTER_DEFINITION{ ++ u32 rfintfs; // set software control: // 0x870~0x877[8 bytes] ++ u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes] ++ u32 rfintfo; // output data: // 0x860~0x86f [16 bytes] ++ u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes] ++ u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes] ++ u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes] ++ u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes] ++ u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] ++ u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] ++ u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes] ++ u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] ++ u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] ++ u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] ++ u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] ++ u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] ++ u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] ++ u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes] ++}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; ++ ++typedef enum _RT_RF_TYPE_819xU{ ++ RF_TYPE_MIN = 0, ++ RF_8225, ++ RF_8256, ++ RF_8258, ++ RF_PSEUDO_11N = 4, ++}RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU; ++ ++ ++typedef struct _rate_adaptive ++{ ++ u8 rate_adaptive_disabled; ++ u8 ratr_state; ++ u16 reserve; ++ ++ u32 high_rssi_thresh_for_ra; ++ u32 high2low_rssi_thresh_for_ra; ++ u8 low2high_rssi_thresh_for_ra40M; ++ u32 low_rssi_thresh_for_ra40M; ++ u8 low2high_rssi_thresh_for_ra20M; ++ u32 low_rssi_thresh_for_ra20M; ++ u32 upper_rssi_threshold_ratr; ++ u32 middle_rssi_threshold_ratr; ++ u32 low_rssi_threshold_ratr; ++ u32 low_rssi_threshold_ratr_40M; ++ u32 low_rssi_threshold_ratr_20M; ++ u8 ping_rssi_enable; //cosa add for test ++ u32 ping_rssi_ratr; //cosa add for test ++ u32 ping_rssi_thresh_for_ra;//cosa add for test ++ u32 last_ratr; ++ ++} rate_adaptive, *prate_adaptive; ++#define TxBBGainTableLength 37 ++#define CCKTxBBGainTableLength 23 ++typedef struct _txbbgain_struct ++{ ++ long txbb_iq_amplifygain; ++ u32 txbbgain_value; ++} txbbgain_struct, *ptxbbgain_struct; ++ ++typedef struct _ccktxbbgain_struct ++{ ++ //The Value is from a22 to a29 one Byte one time is much Safer ++ u8 ccktxbb_valuearray[8]; ++} ccktxbbgain_struct,*pccktxbbgain_struct; ++ ++ ++typedef struct _init_gain ++{ ++ u8 xaagccore1; ++ u8 xbagccore1; ++ u8 xcagccore1; ++ u8 xdagccore1; ++ u8 cca; ++ ++} init_gain, *pinit_gain; ++ ++/* 2007/11/02 MH Define RF mode temporarily for test. */ ++typedef enum tag_Rf_Operatetion_State ++{ ++ RF_STEP_INIT = 0, ++ RF_STEP_NORMAL, ++ RF_STEP_MAX ++}RF_STEP_E; ++ ++typedef enum _RT_STATUS{ ++ RT_STATUS_SUCCESS, ++ RT_STATUS_FAILURE, ++ RT_STATUS_PENDING, ++ RT_STATUS_RESOURCE ++}RT_STATUS,*PRT_STATUS; ++ ++typedef enum _RT_CUSTOMER_ID ++{ ++ RT_CID_DEFAULT = 0, ++ RT_CID_8187_ALPHA0 = 1, ++ RT_CID_8187_SERCOMM_PS = 2, ++ RT_CID_8187_HW_LED = 3, ++ RT_CID_8187_NETGEAR = 4, ++ RT_CID_WHQL = 5, ++ RT_CID_819x_CAMEO = 6, ++ RT_CID_819x_RUNTOP = 7, ++ RT_CID_819x_Senao = 8, ++ RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31. ++ RT_CID_819x_Netcore = 10, ++ RT_CID_Nettronix = 11, ++ RT_CID_DLINK = 12, ++ RT_CID_PRONET = 13, ++ RT_CID_COREGA = 14, ++}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID; ++ ++//================================================================================ ++// LED customization. ++//================================================================================ ++ ++typedef enum _LED_STRATEGY_8190{ ++ SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option. ++ SW_LED_MODE1, // SW control for PCI Express ++ SW_LED_MODE2, // SW control for Cameo. ++ SW_LED_MODE3, // SW contorl for RunTop. ++ SW_LED_MODE4, // SW control for Netcore ++ SW_LED_MODE5, //added by vivi, for led new mode, DLINK ++ SW_LED_MODE6, //added by vivi, for led new mode, PRONET ++ HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes) ++}LED_STRATEGY_8190, *PLED_STRATEGY_8190; ++ ++#define CHANNEL_PLAN_LEN 10 ++ ++#define sCrcLng 4 ++ ++typedef struct _TX_FWINFO_STRUCUTRE{ ++ //DOWRD 0 ++ u8 TxRate:7; ++ u8 CtsEnable:1; ++ u8 RtsRate:7; ++ u8 RtsEnable:1; ++ u8 TxHT:1; ++ u8 Short:1; ++ u8 TxBandwidth:1; ++ u8 TxSubCarrier:2; ++ u8 STBC:2; ++ u8 AllowAggregation:1; ++ u8 RtsHT:1; ++ u8 RtsShort:1; ++ u8 RtsBandwidth:1; ++ u8 RtsSubcarrier:2; ++ u8 RtsSTBC:2; ++ u8 EnableCPUDur:1; ++ ++ //DWORD 1 ++ u32 RxMF:2; ++ u32 RxAMD:3; ++ u32 Reserved1:3; ++ u32 TxAGCOffset:4; ++ u32 TxAGCSign:1; ++ u32 Tx_INFO_RSVD:6; ++ u32 PacketID:13; ++}TX_FWINFO_T; ++ ++ ++typedef struct _TX_FWINFO_8190PCI{ ++ //DOWRD 0 ++ u8 TxRate:7; ++ u8 CtsEnable:1; ++ u8 RtsRate:7; ++ u8 RtsEnable:1; ++ u8 TxHT:1; ++ u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS ++ u8 TxBandwidth:1; // This is used for HT MCS rate only. ++ u8 TxSubCarrier:2; // This is used for legacy OFDM rate only. ++ u8 STBC:2; ++ u8 AllowAggregation:1; ++ u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate ++ u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS ++ u8 RtsBandwidth:1; // This is used for HT MCS rate only. ++ u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only. ++ u8 RtsSTBC:2; ++ u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration ++ ++ //DWORD 1 ++ u32 RxMF:2; ++ u32 RxAMD:3; ++ u32 TxPerPktInfoFeedback:1; // 1: indicate that the transimission info of this packet should be gathered by Firmware and retured by Rx Cmd. ++ u32 Reserved1:2; ++ u32 TxAGCOffset:4; // Only 90 support ++ u32 TxAGCSign:1; // Only 90 support ++ u32 RAW_TXD:1; // MAC will send data in txpktbuffer without any processing,such as CRC check ++ u32 Retry_Limit:4; // CCX Support relative retry limit FW page only support 4 bits now. ++ u32 Reserved2:1; ++ u32 PacketID:13; ++ ++ // DW 2 ++ ++}TX_FWINFO_8190PCI, *PTX_FWINFO_8190PCI; ++ ++typedef struct _phy_ofdm_rx_status_report_819xpci ++{ ++ u8 trsw_gain_X[4]; ++ u8 pwdb_all; ++ u8 cfosho_X[4]; ++ u8 cfotail_X[4]; ++ u8 rxevm_X[2]; ++ u8 rxsnr_X[4]; ++ u8 pdsnr_X[2]; ++ u8 csi_current_X[2]; ++ u8 csi_target_X[2]; ++ u8 sigevm; ++ u8 max_ex_pwr; ++ u8 sgi_en; ++ u8 rxsc_sgien_exflg; ++}phy_sts_ofdm_819xpci_t; ++ ++typedef struct _phy_cck_rx_status_report_819xpci ++{ ++ /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend ++ 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */ ++ u8 adc_pwdb_X[4]; ++ u8 sq_rpt; ++ u8 cck_agc_rpt; ++}phy_sts_cck_819xpci_t; ++ ++typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{ ++ u8 reserved:4; ++ u8 rxsc:2; ++ u8 sgi_en:1; ++ u8 ex_intf_flag:1; ++}phy_ofdm_rx_status_rxsc_sgien_exintfflag; ++ ++typedef enum _RT_OP_MODE{ ++ RT_OP_MODE_AP, ++ RT_OP_MODE_INFRASTRUCTURE, ++ RT_OP_MODE_IBSS, ++ RT_OP_MODE_NO_LINK, ++}RT_OP_MODE, *PRT_OP_MODE; ++ ++ ++/* 2007/11/02 MH Define RF mode temporarily for test. */ ++typedef enum tag_Rf_OpType ++{ ++ RF_OP_By_SW_3wire = 0, ++ RF_OP_By_FW, ++ RF_OP_MAX ++}RF_OpType_E; ++ ++typedef enum _RESET_TYPE { ++ RESET_TYPE_NORESET = 0x00, ++ RESET_TYPE_NORMAL = 0x01, ++ RESET_TYPE_SILENT = 0x02 ++} RESET_TYPE; ++ ++typedef struct _tx_ring{ ++ u32 * desc; ++ u8 nStuckCount; ++ struct _tx_ring * next; ++}__attribute__ ((packed)) tx_ring, * ptx_ring; ++ ++struct rtl8192_tx_ring { ++ tx_desc_819x_pci *desc; ++ dma_addr_t dma; ++ unsigned int idx; ++ unsigned int entries; ++ struct sk_buff_head queue; ++}; ++ ++#define NIC_SEND_HANG_THRESHOLD_NORMAL 4 ++#define NIC_SEND_HANG_THRESHOLD_POWERSAVE 8 ++#define MAX_TX_QUEUE 9 // BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. ++ ++#define MAX_RX_COUNT 64 ++#define MAX_TX_QUEUE_COUNT 9 ++ ++typedef struct r8192_priv ++{ ++ struct pci_dev *pdev; ++ //added for maintain info from eeprom ++ short epromtype; ++ u16 eeprom_vid; ++ u16 eeprom_did; ++ u8 eeprom_CustomerID; ++ u16 eeprom_ChannelPlan; ++ RT_CUSTOMER_ID CustomerID; ++ LED_STRATEGY_8190 LedStrategy; ++ //bool bDcut; ++ u8 IC_Cut; ++ int irq; ++ short irq_enabled; ++ struct ieee80211_device *ieee80211; ++ bool being_init_adapter; ++ u8 Rf_Mode; ++ short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */ ++ u8 card_8192_version; /* if TCR reports card V B/C this discriminates */ ++// short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */ ++ short enable_gpio0; ++ enum card_type {PCI,MINIPCI,CARDBUS,USB/*rtl8187*/}card_type; ++ short hw_plcp_len; ++ short plcp_preamble_mode; ++ u8 ScanDelay; ++ spinlock_t irq_lock; ++ spinlock_t irq_th_lock; ++ spinlock_t tx_lock; ++ spinlock_t rf_ps_lock; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) ++ struct semaphore mutex; ++#else ++ struct mutex mutex; ++#endif ++ spinlock_t rf_lock; //used to lock rf write operation added by wb ++ spinlock_t ps_lock; ++ ++ u32 irq_mask; ++// short irq_enabled; ++// struct net_device *dev; //comment this out. ++ short chan; ++ short sens; ++ short max_sens; ++ u32 rx_prevlen; ++/*RX stuff*/ ++ rx_desc_819x_pci *rx_ring; ++ dma_addr_t rx_ring_dma; ++ unsigned int rx_idx; ++ struct sk_buff *rx_buf[MAX_RX_COUNT]; ++ int rxringcount; ++ u16 rxbuffersize; ++ ++ ++ struct sk_buff *rx_skb; ++ u32 *rxring; ++ u32 *rxringtail; ++ dma_addr_t rxringdma; ++ struct buffer *rxbuffer; ++ struct buffer *rxbufferhead; ++ short rx_skb_complete; ++/*TX stuff*/ ++ struct rtl8192_tx_ring tx_ring[MAX_TX_QUEUE_COUNT]; ++ int txringcount; ++//{ ++ int txbuffsize; ++ int txfwbuffersize; ++ //struct tx_pendingbuf txnp_pending; ++ //struct tasklet_struct irq_tx_tasklet; ++ struct tasklet_struct irq_rx_tasklet; ++ struct tasklet_struct irq_tx_tasklet; ++ struct tasklet_struct irq_prepare_beacon_tasklet; ++ struct buffer *txmapbufs; ++ struct buffer *txbkpbufs; ++ struct buffer *txbepbufs; ++ struct buffer *txvipbufs; ++ struct buffer *txvopbufs; ++ struct buffer *txcmdbufs; ++ struct buffer *txmapbufstail; ++ struct buffer *txbkpbufstail; ++ struct buffer *txbepbufstail; ++ struct buffer *txvipbufstail; ++ struct buffer *txvopbufstail; ++ struct buffer *txcmdbufstail; ++ /* adhoc/master mode stuff */ ++ ptx_ring txbeaconringtail; ++ dma_addr_t txbeaconringdma; ++ ptx_ring txbeaconring; ++ int txbeaconcount; ++ struct buffer *txbeaconbufs; ++ struct buffer *txbeaconbufstail; ++ ptx_ring txmapring; ++ ptx_ring txbkpring; ++ ptx_ring txbepring; ++ ptx_ring txvipring; ++ ptx_ring txvopring; ++ ptx_ring txcmdring; ++ ptx_ring txmapringtail; ++ ptx_ring txbkpringtail; ++ ptx_ring txbepringtail; ++ ptx_ring txvipringtail; ++ ptx_ring txvopringtail; ++ ptx_ring txcmdringtail; ++ ptx_ring txmapringhead; ++ ptx_ring txbkpringhead; ++ ptx_ring txbepringhead; ++ ptx_ring txvipringhead; ++ ptx_ring txvopringhead; ++ ptx_ring txcmdringhead; ++ dma_addr_t txmapringdma; ++ dma_addr_t txbkpringdma; ++ dma_addr_t txbepringdma; ++ dma_addr_t txvipringdma; ++ dma_addr_t txvopringdma; ++ dma_addr_t txcmdringdma; ++ // u8 chtxpwr[15]; //channels from 1 to 14, 0 not used ++// u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used ++// u8 cck_txpwr_base; ++// u8 ofdm_txpwr_base; ++// u8 challow[15]; //channels from 1 to 14, 0 not used ++ short up; ++ short crcmon; //if 1 allow bad crc frame reception in monitor mode ++// short prism_hdr; ++ ++// struct timer_list scan_timer; ++ /*short scanpending; ++ short stopscan;*/ ++// spinlock_t scan_lock; ++// u8 active_probe; ++ //u8 active_scan_num; ++ struct semaphore wx_sem; ++ struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david ++// short hw_wep; ++ ++// short digphy; ++// short antb; ++// short diversity; ++// u8 cs_treshold; ++// short rcr_csense; ++ u8 rf_type; //0 means 1T2R, 1 means 2T4R ++ RT_RF_TYPE_819xU rf_chip; ++ ++// u32 key0[4]; ++ short (*rf_set_sens)(struct net_device *dev,short sens); ++ u8 (*rf_set_chan)(struct net_device *dev,u8 ch); ++ void (*rf_close)(struct net_device *dev); ++ void (*rf_init)(struct net_device *dev); ++ //short rate; ++ short promisc; ++ /*stats*/ ++ struct Stats stats; ++ struct iw_statistics wstats; ++ struct proc_dir_entry *dir_dev; ++ ++ /*RX stuff*/ ++// u32 *rxring; ++// u32 *rxringtail; ++// dma_addr_t rxringdma; ++ ++#ifdef THOMAS_BEACON ++ u32 *oldaddr; ++#endif ++#ifdef THOMAS_TASKLET ++ atomic_t irt_counter;//count for irq_rx_tasklet ++#endif ++#ifdef JACKSON_NEW_RX ++ struct sk_buff **pp_rxskb; ++ int rx_inx; ++#endif ++ ++/* modified by davad for Rx process */ ++ struct sk_buff_head rx_queue; ++ struct sk_buff_head skb_queue; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) ++ struct tq_struct qos_activate; ++#else ++ struct work_struct qos_activate; ++#endif ++ short tx_urb_index; ++ atomic_t tx_pending[0x10];//UART_PRIORITY+1 ++ ++ struct urb *rxurb_task; ++ ++ //2 Tx Related variables ++ u16 ShortRetryLimit; ++ u16 LongRetryLimit; ++ u32 TransmitConfig; ++ u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27. ++ ++ u32 LastRxDescTSFHigh; ++ u32 LastRxDescTSFLow; ++ ++ ++ //2 Rx Related variables ++ u16 EarlyRxThreshold; ++ u32 ReceiveConfig; ++ u8 AcmControl; ++ ++ u8 RFProgType; ++ ++ u8 retry_data; ++ u8 retry_rts; ++ u16 rts; ++ ++ struct ChnlAccessSetting ChannelAccessSetting; ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ struct work_struct reset_wq; ++#else ++ struct tq_struct reset_wq; ++#endif ++ ++/**********************************************************/ ++//for rtl819xPci ++ // Data Rate Config. Added by Annie, 2006-04-13. ++ u16 basic_rate; ++ u8 short_preamble; ++ u8 slot_time; ++ u16 SifsTime; ++/* WirelessMode*/ ++ u8 RegWirelessMode; ++/*Firmware*/ ++ prt_firmware pFirmware; ++ rtl819x_loopback_e LoopbackMode; ++ firmware_source_e firmware_source; ++ bool AutoloadFailFlag; ++ u16 EEPROMTxPowerDiff; ++ u16 EEPROMAntPwDiff; // Antenna gain offset from B/C/D to A ++ u8 EEPROMThermalMeter; ++ u8 EEPROMPwDiff; ++ u8 EEPROMCrystalCap; ++ u8 EEPROM_Def_Ver; ++ u8 EEPROMTxPowerLevelCCK[14];// CCK channel 1~14 ++ // The following definition is for eeprom 93c56 ++ u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7 ++ u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13 ++ u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7 ++ u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13 ++ u8 EEPROMTxPowerLevelCCK_V1[3]; ++ u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14 ++ u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G ++ u8 EEPROMLegacyHTTxPowerDiff; // Legacy to HT rate power diff ++ bool bTXPowerDataReadFromEEPORM; ++/*channel plan*/ ++ u16 RegChannelPlan; // Channel Plan specifed by user, 15: following setting of EEPROM, 0-14: default channel plan index specified by user. ++ u16 ChannelPlan; ++/*PS related*/ ++ bool RegRfOff; ++ // Rf off action for power save ++ u8 bHwRfOffAction; //0:No action, 1:By GPIO, 2:By Disable ++/*PHY related*/ ++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D ++ // Read/write are allow for following hardware information variables ++ u32 MCSTxPowerLevelOriginalOffset[6]; ++ u32 CCKTxPowerLevelOriginalOffset; ++ u8 TxPowerLevelCCK[14]; // CCK channel 1~14 ++ u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14 ++ u8 TxPowerLevelCCK_C[14]; ++ u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14 ++ u8 TxPowerLevelOFDM5G[14]; // OFDM 5G ++ u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14 ++ u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14 ++ u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff ++ u8 TxPowerDiff; ++ char RF_C_TxPwDiff; // Antenna gain offset, rf-c to rf-a ++ u8 AntennaTxPwDiff[3]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D ++ u8 CrystalCap; // CrystalCap. ++ u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 ++ //05/27/2008 cck power enlarge ++ u8 CckPwEnl; ++ u16 TSSI_13dBm; ++ u32 Pwr_Track; ++ u8 CCKPresentAttentuation_20Mdefault; ++ u8 CCKPresentAttentuation_40Mdefault; ++ char CCKPresentAttentuation_difference; ++ char CCKPresentAttentuation; ++ // Use to calculate PWBD. ++ u8 bCckHighPower; ++ long undecorated_smoothed_pwdb; ++ long undecorated_smoothed_cck_adc_pwdb[4]; ++ //for set channel ++ u8 SwChnlInProgress; ++ u8 SwChnlStage; ++ u8 SwChnlStep; ++ u8 SetBWModeInProgress; ++ HT_CHANNEL_WIDTH CurrentChannelBW; ++ ++ // 8190 40MHz mode ++ // ++ u8 nCur40MhzPrimeSC; // Control channel sub-carrier ++ // Joseph test for shorten RF configuration time. ++ // We save RF reg0 in this variable to reduce RF reading. ++ // ++ u32 RfReg0Value[4]; ++ u8 NumTotalRFPath; ++ bool brfpath_rxenable[4]; ++//+by amy 080507 ++ struct timer_list watch_dog_timer; ++ ++//+by amy 080515 for dynamic mechenism ++ //Add by amy Tx Power Control for Near/Far Range 2008/05/15 ++ bool bdynamic_txpower; //bDynamicTxPower ++ bool bDynamicTxHighPower; // Tx high power state ++ bool bDynamicTxLowPower; // Tx low power state ++ bool bLastDTPFlag_High; ++ bool bLastDTPFlag_Low; ++ ++ bool bstore_last_dtpflag; ++ bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index ++ //Add by amy for Rate Adaptive ++ rate_adaptive rate_adaptive; ++ //Add by amy for TX power tracking ++ //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING ++ txbbgain_struct txbbgain_table[TxBBGainTableLength]; ++ u8 txpower_count;//For 6 sec do tracking again ++ bool btxpower_trackingInit; ++ u8 OFDM_index; ++ u8 CCK_index; ++ u8 Record_CCK_20Mindex; ++ u8 Record_CCK_40Mindex; ++ //2007/09/10 Mars Add CCK TX Power Tracking ++ ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength]; ++ ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength]; ++ u8 rfa_txpowertrackingindex; ++ u8 rfa_txpowertrackingindex_real; ++ u8 rfa_txpowertracking_default; ++ u8 rfc_txpowertrackingindex; ++ u8 rfc_txpowertrackingindex_real; ++ u8 rfc_txpowertracking_default; ++ bool btxpower_tracking; ++ bool bcck_in_ch14; ++ ++ //For Backup Initial Gain ++ init_gain initgain_backup; ++ u8 DefaultInitialGain[4]; ++ // For EDCA Turbo mode, Added by amy 080515. ++ bool bis_any_nonbepkts; ++ bool bcurrent_turbo_EDCA; ++ ++ bool bis_cur_rdlstate; ++ struct timer_list fsync_timer; ++ bool bfsync_processing; // 500ms Fsync timer is active or not ++ u32 rate_record; ++ u32 rateCountDiffRecord; ++ u32 ContiuneDiffCount; ++ bool bswitch_fsync; ++ ++ u8 framesync; ++ u32 framesyncC34; ++ u8 framesyncMonitor; ++ //Added by amy 080516 for RX related ++ u16 nrxAMPDU_size; ++ u8 nrxAMPDU_aggr_num; ++ ++ /*Last RxDesc TSF value*/ ++ u32 last_rxdesc_tsf_high; ++ u32 last_rxdesc_tsf_low; ++ ++ //by amy for gpio ++ bool bHwRadioOff; ++ //by amy for ps ++ bool RFChangeInProgress; // RF Chnage in progress, by Bruce, 2007-10-30 ++ bool SetRFPowerStateInProgress; ++ RT_OP_MODE OpMode; ++ //by amy for reset_count ++ u32 reset_count; ++ bool bpbc_pressed; ++ //by amy for debug ++ u32 txpower_checkcnt; ++ u32 txpower_tracking_callback_cnt; ++ u8 thermal_read_val[40]; ++ u8 thermal_readback_index; ++ u32 ccktxpower_adjustcnt_not_ch14; ++ u32 ccktxpower_adjustcnt_ch14; ++ u8 tx_fwinfo_force_subcarriermode; ++ u8 tx_fwinfo_force_subcarrierval; ++ ++ //by amy for silent reset ++ RESET_TYPE ResetProgress; ++ bool bForcedSilentReset; ++ bool bDisableNormalResetCheck; ++ u16 TxCounter; ++ u16 RxCounter; ++ int IrpPendingCount; ++ bool bResetInProgress; ++ bool force_reset; ++ u8 InitialGainOperateType; ++ ++ //define work item by amy 080526 ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ struct delayed_work update_beacon_wq; ++ struct delayed_work watch_dog_wq; ++ struct delayed_work txpower_tracking_wq; ++ struct delayed_work rfpath_check_wq; ++ struct delayed_work gpio_change_rf_wq; ++ struct delayed_work initialgain_operate_wq; ++#else ++ struct work_struct update_beacon_wq; ++ struct work_struct watch_dog_wq; ++ struct work_struct txpower_tracking_wq; ++ struct work_struct rfpath_check_wq; ++ struct work_struct gpio_change_rf_wq; ++ struct work_struct initialgain_operate_wq; ++#endif ++ struct workqueue_struct *priv_wq; ++#else ++ struct tq_struct update_beacon_wq; ++ /* used for periodly scan */ ++ struct tq_struct txpower_tracking_wq; ++ struct tq_struct rfpath_check_wq; ++ struct tq_struct watch_dog_wq; ++ struct tq_struct gpio_change_rf_wq; ++ struct tq_struct initialgain_operate_wq; ++#endif ++}r8192_priv; ++ ++// for rtl8187 ++// now mirging to rtl8187B ++/* ++typedef enum{ ++ LOW_PRIORITY = 0x02, ++ NORM_PRIORITY ++ } priority_t; ++*/ ++//for rtl8187B ++#if 0 ++typedef enum{ ++ BULK_PRIORITY = 0x01, ++ //RSVD0, ++ //RSVD1, ++ LOW_PRIORITY, ++ NORM_PRIORITY, ++ VO_PRIORITY, ++ VI_PRIORITY, //0x05 ++ BE_PRIORITY, ++ BK_PRIORITY, ++ CMD_PRIORITY,//0x8 ++ RSVD3, ++ BEACON_PRIORITY, //0x0A ++ HIGH_PRIORITY, ++ MANAGE_PRIORITY, ++ RSVD4, ++ RSVD5, ++ UART_PRIORITY //0x0F ++} priority_t; ++#endif ++typedef enum{ ++ NIC_8192E = 1, ++ } nic_t; ++ ++ ++#if 0 //defined in Qos.h ++//typedef u32 AC_CODING; ++#define AC0_BE 0 // ACI: 0x00 // Best Effort ++#define AC1_BK 1 // ACI: 0x01 // Background ++#define AC2_VI 2 // ACI: 0x10 // Video ++#define AC3_VO 3 // ACI: 0x11 // Voice ++#define AC_MAX 4 // Max: define total number; Should not to be used as a real enum. ++ ++// ++// ECWmin/ECWmax field. ++// Ref: WMM spec 2.2.2: WME Parameter Element, p.13. ++// ++typedef union _ECW{ ++ u8 charData; ++ struct ++ { ++ u8 ECWmin:4; ++ u8 ECWmax:4; ++ }f; // Field ++}ECW, *PECW; ++ ++// ++// ACI/AIFSN Field. ++// Ref: WMM spec 2.2.2: WME Parameter Element, p.12. ++// ++typedef union _ACI_AIFSN{ ++ u8 charData; ++ ++ struct ++ { ++ u8 AIFSN:4; ++ u8 ACM:1; ++ u8 ACI:2; ++ u8 Reserved:1; ++ }f; // Field ++}ACI_AIFSN, *PACI_AIFSN; ++ ++// ++// AC Parameters Record Format. ++// Ref: WMM spec 2.2.2: WME Parameter Element, p.12. ++// ++typedef union _AC_PARAM{ ++ u32 longData; ++ u8 charData[4]; ++ ++ struct ++ { ++ ACI_AIFSN AciAifsn; ++ ECW Ecw; ++ u16 TXOPLimit; ++ }f; // Field ++}AC_PARAM, *PAC_PARAM; ++ ++#endif ++bool init_firmware(struct net_device *dev); ++void rtl819xE_tx_cmd(struct net_device *dev, struct sk_buff *skb); ++short rtl8192_tx(struct net_device *dev, struct sk_buff* skb); ++u32 read_cam(struct net_device *dev, u8 addr); ++void write_cam(struct net_device *dev, u8 addr, u32 data); ++u8 read_nic_byte(struct net_device *dev, int x); ++u8 read_nic_byte_E(struct net_device *dev, int x); ++u32 read_nic_dword(struct net_device *dev, int x); ++u16 read_nic_word(struct net_device *dev, int x) ; ++void write_nic_byte(struct net_device *dev, int x,u8 y); ++void write_nic_byte_E(struct net_device *dev, int x,u8 y); ++void write_nic_word(struct net_device *dev, int x,u16 y); ++void write_nic_dword(struct net_device *dev, int x,u32 y); ++void force_pci_posting(struct net_device *dev); ++ ++void rtl8192_rtx_disable(struct net_device *); ++void rtl8192_rx_enable(struct net_device *); ++void rtl8192_tx_enable(struct net_device *); ++ ++void rtl8192_disassociate(struct net_device *dev); ++//void fix_rx_fifo(struct net_device *dev); ++void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a); ++ ++void rtl8192_set_anaparam(struct net_device *dev,u32 a); ++void rtl8185_set_anaparam2(struct net_device *dev,u32 a); ++void rtl8192_update_msr(struct net_device *dev); ++int rtl8192_down(struct net_device *dev); ++int rtl8192_up(struct net_device *dev); ++void rtl8192_commit(struct net_device *dev); ++void rtl8192_set_chan(struct net_device *dev,short ch); ++void write_phy(struct net_device *dev, u8 adr, u8 data); ++void write_phy_cck(struct net_device *dev, u8 adr, u32 data); ++void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data); ++void rtl8185_tx_antenna(struct net_device *dev, u8 ant); ++void rtl8187_set_rxconf(struct net_device *dev); ++//short check_nic_enough_desc(struct net_device *dev, priority_t priority); ++void rtl8192_start_beacon(struct net_device *dev); ++void CamResetAllEntry(struct net_device* dev); ++void EnableHWSecurityConfig8192(struct net_device *dev); ++void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent ); ++void CamPrintDbgReg(struct net_device* dev); ++extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14); ++extern void firmware_init_param(struct net_device *dev); ++extern RT_STATUS cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++void rtl8192_hw_wakeup_wq (struct work_struct *work); ++#else ++void rtl8192_hw_wakeup_wq(struct net_device *dev); ++#endif ++ ++short rtl8192_is_tx_queue_empty(struct net_device *dev); ++#ifdef ENABLE_IPS ++void IPSEnter(struct net_device *dev); ++void IPSLeave(struct net_device *dev); ++#endif ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r8192E_hw.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E_hw.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E_hw.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,811 @@ ++/* ++ This is part of rtl8187 OpenSource driver. ++ Copyright (C) Andrea Merello 2004-2005 ++ Released under the terms of GPL (General Public Licence) ++ ++ Parts of this driver are based on the GPL part of the ++ official Realtek driver. ++ Parts of this driver are based on the rtl8180 driver skeleton ++ from Patric Schenke & Andres Salomon. ++ Parts of this driver are based on the Intel Pro Wireless ++ 2100 GPL driver. ++ ++ We want to tanks the Authors of those projects ++ and the Ndiswrapper project Authors. ++*/ ++ ++/* Mariusz Matuszek added full registers definition with Realtek's name */ ++ ++/* this file contains register definitions for the rtl8187 MAC controller */ ++#ifndef R8180_HW ++#define R8180_HW ++ ++typedef enum _VERSION_8190{ ++ // RTL8190 ++ VERSION_8190_BD=0x3, ++ VERSION_8190_BE ++}VERSION_8190,*PVERSION_8190; ++//added for different RF type ++typedef enum _RT_RF_TYPE_DEF ++{ ++ RF_1T2R = 0, ++ RF_2T4R, ++ ++ RF_819X_MAX_TYPE ++}RT_RF_TYPE_DEF; ++ ++typedef enum _BaseBand_Config_Type{ ++ BaseBand_Config_PHY_REG = 0, //Radio Path A ++ BaseBand_Config_AGC_TAB = 1, //Radio Path B ++}BaseBand_Config_Type, *PBaseBand_Config_Type; ++#if 0 ++typedef enum _RT_RF_TYPE_819xU{ ++ RF_TYPE_MIN = 0, ++ RF_8225, ++ RF_8256, ++ RF_8258, ++ RF_PSEUDO_11N = 4, ++}RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU; ++#endif ++#define RTL8187_REQT_READ 0xc0 ++#define RTL8187_REQT_WRITE 0x40 ++#define RTL8187_REQ_GET_REGS 0x05 ++#define RTL8187_REQ_SET_REGS 0x05 ++ ++#define R8180_MAX_RETRY 255 ++#define MAX_TX_URB 5 ++#define MAX_RX_URB 16 ++//#define MAX_RX_NORMAL_URB 3 ++//#define MAX_RX_COMMAND_URB 2 ++#define RX_URB_SIZE 9100 ++ ++#define BB_ANTATTEN_CHAN14 0x0c ++#define BB_ANTENNA_B 0x40 ++ ++#define BB_HOST_BANG (1<<30) ++#define BB_HOST_BANG_EN (1<<2) ++#define BB_HOST_BANG_CLK (1<<1) ++#define BB_HOST_BANG_RW (1<<3) ++#define BB_HOST_BANG_DATA 1 ++ ++//#if (RTL819X_FPGA_VER & RTL819X_FPGA_VIVI_070920) ++#define RTL8190_EEPROM_ID 0x8129 ++#define EEPROM_VID 0x02 ++#define EEPROM_DID 0x04 ++#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C ++ ++#define EEPROM_TxPowerDiff 0x1F ++ ++ ++#define EEPROM_PwDiff 0x21 //0x21 ++#define EEPROM_CrystalCap 0x22 //0x22 ++ ++ ++ ++#define EEPROM_TxPwIndex_CCK_V1 0x29 //0x29~0x2B ++#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C //0x2C~0x2E ++#define EEPROM_TxPwIndex_Ver 0x27 //0x27 ++ ++#define EEPROM_Default_TxPowerDiff 0x0 ++#define EEPROM_Default_ThermalMeter 0x77 ++#define EEPROM_Default_AntTxPowerDiff 0x0 ++#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 ++#define EEPROM_Default_PwDiff 0x4 ++#define EEPROM_Default_CrystalCap 0x5 ++#define EEPROM_Default_TxPower 0x1010 ++#define EEPROM_ICVersion_ChannelPlan 0x7C //0x7C:ChannelPlan, 0x7D:IC_Version ++#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID ++#ifdef RTL8190P ++#define EEPROM_RFInd_PowerDiff 0x14 ++#define EEPROM_ThermalMeter 0x15 ++#define EEPROM_TxPwDiff_CrystalCap 0x16 ++#define EEPROM_TxPwIndex_CCK 0x18 //0x18~0x25 ++#define EEPROM_TxPwIndex_OFDM_24G 0x26 //0x26~0x33 ++#define EEPROM_TxPwIndex_OFDM_5G 0x34 //0x34~0x7B ++#define EEPROM_C56_CrystalCap 0x17 //0x17 ++#define EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex 0x80 //0x80 ++#define EEPROM_C56_RfA_HT_OFDM_TxPwIndex 0x81 //0x81~0x83 ++#define EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex 0xbc //0xb8 ++#define EEPROM_C56_RfC_HT_OFDM_TxPwIndex 0xb9 //0xb9~0xbb ++#else ++#ifdef RTL8192E ++#define EEPROM_RFInd_PowerDiff 0x28 ++#define EEPROM_ThermalMeter 0x29 ++#define EEPROM_TxPwDiff_CrystalCap 0x2A //0x2A~0x2B ++#define EEPROM_TxPwIndex_CCK 0x2C //0x23 ++#define EEPROM_TxPwIndex_OFDM_24G 0x3A //0x24~0x26 ++#endif ++#endif ++#define EEPROM_Default_TxPowerLevel 0x10 ++//#define EEPROM_ChannelPlan 0x7c //0x7C ++#define EEPROM_IC_VER 0x7d //0x7D ++#define EEPROM_CRC 0x7e //0x7E~0x7F ++ ++#define EEPROM_CID_DEFAULT 0x0 ++#define EEPROM_CID_CAMEO 0x1 ++#define EEPROM_CID_RUNTOP 0x2 ++#define EEPROM_CID_Senao 0x3 ++#define EEPROM_CID_TOSHIBA 0x4 // Toshiba setting, Merge by Jacken, 2008/01/31 ++#define EEPROM_CID_NetCore 0x5 ++#define EEPROM_CID_Nettronix 0x6 ++#define EEPROM_CID_Pronet 0x7 ++#define EEPROM_CID_DLINK 0x8 ++#define EEPROM_CID_WHQL 0xFE //added by sherry for dtm, 20080728 ++//#endif ++enum _RTL8192Pci_HW { ++ MAC0 = 0x000, ++ MAC1 = 0x001, ++ MAC2 = 0x002, ++ MAC3 = 0x003, ++ MAC4 = 0x004, ++ MAC5 = 0x005, ++ PCIF = 0x009, // PCI Function Register 0x0009h~0x000bh ++//---------------------------------------------------------------------------- ++// 8190 PCIF bits (Offset 0x009-000b, 24bit) ++//---------------------------------------------------------------------------- ++#define MXDMA2_16bytes 0x000 ++#define MXDMA2_32bytes 0x001 ++#define MXDMA2_64bytes 0x010 ++#define MXDMA2_128bytes 0x011 ++#define MXDMA2_256bytes 0x100 ++#define MXDMA2_512bytes 0x101 ++#define MXDMA2_1024bytes 0x110 ++#define MXDMA2_NoLimit 0x7 ++ ++#define MULRW_SHIFT 3 ++#define MXDMA2_RX_SHIFT 4 ++#define MXDMA2_TX_SHIFT 0 ++ PMR = 0x00c, // Power management register ++ EPROM_CMD = 0x00e, ++#define EPROM_CMD_RESERVED_MASK BIT5 ++#define EPROM_CMD_9356SEL BIT4 ++#define EPROM_CMD_OPERATING_MODE_SHIFT 6 ++#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) ++#define EPROM_CMD_CONFIG 0x3 ++#define EPROM_CMD_NORMAL 0 ++#define EPROM_CMD_LOAD 1 ++#define EPROM_CMD_PROGRAM 2 ++#define EPROM_CS_SHIFT 3 ++#define EPROM_CK_SHIFT 2 ++#define EPROM_W_SHIFT 1 ++#define EPROM_R_SHIFT 0 ++ ++ AFR = 0x010, ++#define AFR_CardBEn (1<<0) ++#define AFR_CLKRUN_SEL (1<<1) ++#define AFR_FuncRegEn (1<<2) ++ ++ ANAPAR = 0x17, ++#define BB_GLOBAL_RESET_BIT 0x1 ++ BB_GLOBAL_RESET = 0x020, // BasebandGlobal Reset Register ++ BSSIDR = 0x02E, // BSSID Register ++ CMDR = 0x037, // Command register ++#define CR_RST 0x10 ++#define CR_RE 0x08 ++#define CR_TE 0x04 ++#define CR_MulRW 0x01 ++ SIFS = 0x03E, // SIFS register ++ TCR = 0x040, // Transmit Configuration Register ++ RCR = 0x044, // Receive Configuration Register ++//---------------------------------------------------------------------------- ++//// 8190 (RCR) Receive Configuration Register (Offset 0x44~47, 32 bit) ++////---------------------------------------------------------------------------- ++#define RCR_FILTER_MASK (BIT0|BIT1|BIT2|BIT3|BIT5|BIT12|BIT18|BIT19|BIT20|BIT21|BIT22|BIT23) ++#define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size. ++#define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2 ++#define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1 ++#define RCR_ENMBID BIT27 // Enable Multiple BssId. ++#define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames ++#define RCR_CBSSID BIT23 // Accept BSSID match packet ++#define RCR_APWRMGT BIT22 // Accept power management packet ++#define RCR_ADD3 BIT21 // Accept address 3 match packet ++#define RCR_AMF BIT20 // Accept management type frame ++#define RCR_ACF BIT19 // Accept control type frame ++#define RCR_ADF BIT18 // Accept data type frame ++#define RCR_RXFTH BIT13 // Rx FIFO Threshold ++#define RCR_AICV BIT12 // Accept ICV error packet ++#define RCR_ACRC32 BIT5 // Accept CRC32 error packet ++#define RCR_AB BIT3 // Accept broadcast packet ++#define RCR_AM BIT2 // Accept multicast packet ++#define RCR_APM BIT1 // Accept physical match packet ++#define RCR_AAP BIT0 // Accept all unicast packet ++#define RCR_MXDMA_OFFSET 8 ++#define RCR_FIFO_OFFSET 13 ++ SLOT_TIME = 0x049, // Slot Time Register ++ ACK_TIMEOUT = 0x04c, // Ack Timeout Register ++ PIFS_TIME = 0x04d, // PIFS time ++ USTIME = 0x04e, // Microsecond Tuning Register, Sets the microsecond time unit used by MAC clock. ++ EDCAPARA_BE = 0x050, // EDCA Parameter of AC BE ++ EDCAPARA_BK = 0x054, // EDCA Parameter of AC BK ++ EDCAPARA_VO = 0x058, // EDCA Parameter of AC VO ++ EDCAPARA_VI = 0x05C, // EDCA Parameter of AC VI ++#define AC_PARAM_TXOP_LIMIT_OFFSET 16 ++#define AC_PARAM_ECW_MAX_OFFSET 12 ++#define AC_PARAM_ECW_MIN_OFFSET 8 ++#define AC_PARAM_AIFS_OFFSET 0 ++ RFPC = 0x05F, // Rx FIFO Packet Count ++ CWRR = 0x060, // Contention Window Report Register ++ BCN_TCFG = 0x062, // Beacon Time Configuration ++#define BCN_TCFG_CW_SHIFT 8 ++#define BCN_TCFG_IFS 0 ++ BCN_INTERVAL = 0x070, // Beacon Interval (TU) ++ ATIMWND = 0x072, // ATIM Window Size (TU) ++ BCN_DRV_EARLY_INT = 0x074, // Driver Early Interrupt Time (TU). Time to send interrupt to notify to change beacon content before TBTT ++#define BCN_DRV_EARLY_INT_SWBCN_SHIFT 8 ++#define BCN_DRV_EARLY_INT_TIME_SHIFT 0 ++ BCN_DMATIME = 0x076, // Beacon DMA and ATIM interrupt time (US). Indicates the time before TBTT to perform beacon queue DMA ++ BCN_ERR_THRESH = 0x078, // Beacon Error Threshold ++ RWCAM = 0x0A0, //IN 8190 Data Sheet is called CAMcmd ++ //---------------------------------------------------------------------------- ++ //// 8190 CAM Command Register (offset 0xA0, 4 byte) ++ ////---------------------------------------------------------------------------- ++#define CAM_CM_SecCAMPolling BIT31 //Security CAM Polling ++#define CAM_CM_SecCAMClr BIT30 //Clear all bits in CAM ++#define CAM_CM_SecCAMWE BIT16 //Security CAM enable ++#define CAM_VALID BIT15 ++#define CAM_NOTVALID 0x0000 ++#define CAM_USEDK BIT5 ++ ++#define CAM_NONE 0x0 ++#define CAM_WEP40 0x01 ++#define CAM_TKIP 0x02 ++#define CAM_AES 0x04 ++#define CAM_WEP104 0x05 ++ ++#define TOTAL_CAM_ENTRY 32 ++ ++#define CAM_CONFIG_USEDK true ++#define CAM_CONFIG_NO_USEDK false ++#define CAM_WRITE BIT16 ++#define CAM_READ 0x00000000 ++#define CAM_POLLINIG BIT31 ++#define SCR_UseDK 0x01 ++ WCAMI = 0x0A4, // Software write CAM input content ++ RCAMO = 0x0A8, // Software read/write CAM config ++ SECR = 0x0B0, //Security Configuration Register ++#define SCR_TxUseDK BIT0 //Force Tx Use Default Key ++#define SCR_RxUseDK BIT1 //Force Rx Use Default Key ++#define SCR_TxEncEnable BIT2 //Enable Tx Encryption ++#define SCR_RxDecEnable BIT3 //Enable Rx Decryption ++#define SCR_SKByA2 BIT4 //Search kEY BY A2 ++#define SCR_NoSKMC BIT5 //No Key Search for Multicast ++ SWREGULATOR = 0x0BD, // Switching Regulator ++ INTA_MASK = 0x0f4, ++//---------------------------------------------------------------------------- ++// 8190 IMR/ISR bits (offset 0xfd, 8bits) ++//---------------------------------------------------------------------------- ++#define IMR8190_DISABLED 0x0 ++#define IMR_ATIMEND BIT28 // ATIM Window End Interrupt ++#define IMR_TBDOK BIT27 // Transmit Beacon OK Interrupt ++#define IMR_TBDER BIT26 // Transmit Beacon Error Interrupt ++#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow ++#define IMR_TIMEOUT0 BIT14 // TimeOut0 ++#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0 ++#define IMR_RXFOVW BIT12 // Receive FIFO Overflow ++#define IMR_RDU BIT11 // Receive Descriptor Unavailable ++#define IMR_RXCMDOK BIT10 // Receive Command Packet OK ++#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup ++#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt ++#define IMR_COMDOK BIT7 // Command Queue DMA OK Interrupt ++#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt ++#define IMR_HCCADOK BIT5 // HCCA Queue DMA OK Interrupt ++#define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt ++#define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt ++#define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt ++#define IMR_VODOK BIT1 // AC_VO DMA Interrupt ++#define IMR_ROK BIT0 // Receive DMA OK Interrupt ++ ISR = 0x0f8, // Interrupt Status Register ++ TPPoll = 0x0fd, // Transmit priority polling register ++#define TPPoll_BKQ BIT0 // BK queue polling ++#define TPPoll_BEQ BIT1 // BE queue polling ++#define TPPoll_VIQ BIT2 // VI queue polling ++#define TPPoll_VOQ BIT3 // VO queue polling ++#define TPPoll_BQ BIT4 // Beacon queue polling ++#define TPPoll_CQ BIT5 // Command queue polling ++#define TPPoll_MQ BIT6 // Management queue polling ++#define TPPoll_HQ BIT7 // High queue polling ++#define TPPoll_HCCAQ BIT8 // HCCA queue polling ++#define TPPoll_StopBK BIT9 // Stop BK queue ++#define TPPoll_StopBE BIT10 // Stop BE queue ++#define TPPoll_StopVI BIT11 // Stop VI queue ++#define TPPoll_StopVO BIT12 // Stop VO queue ++#define TPPoll_StopMgt BIT13 // Stop Mgnt queue ++#define TPPoll_StopHigh BIT14 // Stop High queue ++#define TPPoll_StopHCCA BIT15 // Stop HCCA queue ++#define TPPoll_SHIFT 8 // Queue ID mapping ++ ++ PSR = 0x0ff, // Page Select Register ++#define PSR_GEN 0x0 // Page 0 register general MAC Control ++#define PSR_CPU 0x1 // Page 1 register for CPU ++ CPU_GEN = 0x100, // CPU Reset Register ++ BB_RESET = 0x101, // Baseband Reset ++//---------------------------------------------------------------------------- ++// 8190 CPU General Register (offset 0x100, 4 byte) ++//---------------------------------------------------------------------------- ++#define CPU_CCK_LOOPBACK 0x00030000 ++#define CPU_GEN_SYSTEM_RESET 0x00000001 ++#define CPU_GEN_FIRMWARE_RESET 0x00000008 ++#define CPU_GEN_BOOT_RDY 0x00000010 ++#define CPU_GEN_FIRM_RDY 0x00000020 ++#define CPU_GEN_PUT_CODE_OK 0x00000080 ++#define CPU_GEN_BB_RST 0x00000100 ++#define CPU_GEN_PWR_STB_CPU 0x00000004 ++#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 ++#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 ++#define CPU_GEN_GPIO_UART 0x00007000 ++ ++ LED1Cfg = 0x154,// LED1 Configuration Register ++ LED0Cfg = 0x155,// LED0 Configuration Register ++ ++ AcmAvg = 0x170, // ACM Average Period Register ++ AcmHwCtrl = 0x171, // ACM Hardware Control Register ++//---------------------------------------------------------------------------- ++// ++// 8190 AcmHwCtrl bits (offset 0x171, 1 byte) ++//---------------------------------------------------------------------------- ++#define AcmHw_HwEn BIT0 ++#define AcmHw_BeqEn BIT1 ++#define AcmHw_ViqEn BIT2 ++#define AcmHw_VoqEn BIT3 ++#define AcmHw_BeqStatus BIT4 ++#define AcmHw_ViqStatus BIT5 ++#define AcmHw_VoqStatus BIT6 ++ AcmFwCtrl = 0x172, // ACM Firmware Control Register ++#define AcmFw_BeqStatus BIT0 ++#define AcmFw_ViqStatus BIT1 ++#define AcmFw_VoqStatus BIT2 ++ VOAdmTime = 0x174, // VO Queue Admitted Time Register ++ VIAdmTime = 0x178, // VI Queue Admitted Time Register ++ BEAdmTime = 0x17C, // BE Queue Admitted Time Register ++ RQPN1 = 0x180, // Reserved Queue Page Number , Vo Vi, Be, Bk ++ RQPN2 = 0x184, // Reserved Queue Page Number, HCCA, Cmd, Mgnt, High ++ RQPN3 = 0x188, // Reserved Queue Page Number, Bcn, Public, ++ QPRR = 0x1E0, // Queue Page Report per TID ++ QPNR = 0x1F0, // Queue Packet Number report per TID ++/* there's 9 tx descriptor base address available */ ++ BQDA = 0x200, // Beacon Queue Descriptor Address ++ HQDA = 0x204, // High Priority Queue Descriptor Address ++ CQDA = 0x208, // Command Queue Descriptor Address ++ MQDA = 0x20C, // Management Queue Descriptor Address ++ HCCAQDA = 0x210, // HCCA Queue Descriptor Address ++ VOQDA = 0x214, // VO Queue Descriptor Address ++ VIQDA = 0x218, // VI Queue Descriptor Address ++ BEQDA = 0x21C, // BE Queue Descriptor Address ++ BKQDA = 0x220, // BK Queue Descriptor Address ++/* there's 2 rx descriptor base address availalbe */ ++ RCQDA = 0x224, // Receive command Queue Descriptor Address ++ RDQDA = 0x228, // Receive Queue Descriptor Start Address ++ ++ MAR0 = 0x240, // Multicast filter. ++ MAR4 = 0x244, ++ ++ CCX_PERIOD = 0x250, // CCX Measurement Period Register, in unit of TU. ++ CLM_RESULT = 0x251, // CCA Busy fraction register. ++ NHM_PERIOD = 0x252, // NHM Measurement Period register, in unit of TU. ++ ++ NHM_THRESHOLD0 = 0x253, // Noise Histogram Meashorement0. ++ NHM_THRESHOLD1 = 0x254, // Noise Histogram Meashorement1. ++ NHM_THRESHOLD2 = 0x255, // Noise Histogram Meashorement2. ++ NHM_THRESHOLD3 = 0x256, // Noise Histogram Meashorement3. ++ NHM_THRESHOLD4 = 0x257, // Noise Histogram Meashorement4. ++ NHM_THRESHOLD5 = 0x258, // Noise Histogram Meashorement5. ++ NHM_THRESHOLD6 = 0x259, // Noise Histogram Meashorement6 ++ ++ MCTRL = 0x25A, // Measurement Control ++ ++ NHM_RPI_COUNTER0 = 0x264, // Noise Histogram RPI counter0, the fraction of signal strength < NHM_THRESHOLD0. ++ NHM_RPI_COUNTER1 = 0x265, // Noise Histogram RPI counter1, the fraction of signal strength in (NHM_THRESHOLD0, NHM_THRESHOLD1]. ++ NHM_RPI_COUNTER2 = 0x266, // Noise Histogram RPI counter2, the fraction of signal strength in (NHM_THRESHOLD1, NHM_THRESHOLD2]. ++ NHM_RPI_COUNTER3 = 0x267, // Noise Histogram RPI counter3, the fraction of signal strength in (NHM_THRESHOLD2, NHM_THRESHOLD3]. ++ NHM_RPI_COUNTER4 = 0x268, // Noise Histogram RPI counter4, the fraction of signal strength in (NHM_THRESHOLD3, NHM_THRESHOLD4]. ++ NHM_RPI_COUNTER5 = 0x269, // Noise Histogram RPI counter5, the fraction of signal strength in (NHM_THRESHOLD4, NHM_THRESHOLD5]. ++ NHM_RPI_COUNTER6 = 0x26A, // Noise Histogram RPI counter6, the fraction of signal strength in (NHM_THRESHOLD5, NHM_THRESHOLD6]. ++ NHM_RPI_COUNTER7 = 0x26B, // Noise Histogram RPI counter7, the fraction of signal strength in (NHM_THRESHOLD6, NHM_THRESHOLD7]. ++ WFCRC0 = 0x2f0, ++ WFCRC1 = 0x2f4, ++ WFCRC2 = 0x2f8, ++ ++ BW_OPMODE = 0x300, // Bandwidth operation mode ++#define BW_OPMODE_11J BIT0 ++#define BW_OPMODE_5G BIT1 ++#define BW_OPMODE_20MHZ BIT2 ++ IC_VERRSION = 0x301, //IC_VERSION ++ MSR = 0x303, // Media Status register ++#define MSR_LINK_MASK ((1<<0)|(1<<1)) ++#define MSR_LINK_MANAGED 2 ++#define MSR_LINK_NONE 0 ++#define MSR_LINK_SHIFT 0 ++#define MSR_LINK_ADHOC 1 ++#define MSR_LINK_MASTER 3 ++#define MSR_LINK_ENEDCA (1<<4) ++ RETRY_LIMIT = 0x304, // Retry Limit [15:8]-short, [7:0]-long ++#define RETRY_LIMIT_SHORT_SHIFT 8 ++#define RETRY_LIMIT_LONG_SHIFT 0 ++ TSFR = 0x308, ++ RRSR = 0x310, // Response Rate Set ++#define RRSR_RSC_OFFSET 21 ++#define RRSR_SHORT_OFFSET 23 ++#define RRSR_RSC_DUPLICATE 0x600000 ++#define RRSR_RSC_UPSUBCHNL 0x400000 ++#define RRSR_RSC_LOWSUBCHNL 0x200000 ++#define RRSR_SHORT 0x800000 ++#define RRSR_1M BIT0 ++#define RRSR_2M BIT1 ++#define RRSR_5_5M BIT2 ++#define RRSR_11M BIT3 ++#define RRSR_6M BIT4 ++#define RRSR_9M BIT5 ++#define RRSR_12M BIT6 ++#define RRSR_18M BIT7 ++#define RRSR_24M BIT8 ++#define RRSR_36M BIT9 ++#define RRSR_48M BIT10 ++#define RRSR_54M BIT11 ++#define RRSR_MCS0 BIT12 ++#define RRSR_MCS1 BIT13 ++#define RRSR_MCS2 BIT14 ++#define RRSR_MCS3 BIT15 ++#define RRSR_MCS4 BIT16 ++#define RRSR_MCS5 BIT17 ++#define RRSR_MCS6 BIT18 ++#define RRSR_MCS7 BIT19 ++#define BRSR_AckShortPmb BIT23 // CCK ACK: use Short Preamble or not ++ UFWP = 0x318, ++ RATR0 = 0x320, // Rate Adaptive Table register1 ++//---------------------------------------------------------------------------- ++// 8190 Rate Adaptive Table Register (offset 0x320, 4 byte) ++//---------------------------------------------------------------------------- ++//CCK ++#define RATR_1M 0x00000001 ++#define RATR_2M 0x00000002 ++#define RATR_55M 0x00000004 ++#define RATR_11M 0x00000008 ++//OFDM ++#define RATR_6M 0x00000010 ++#define RATR_9M 0x00000020 ++#define RATR_12M 0x00000040 ++#define RATR_18M 0x00000080 ++#define RATR_24M 0x00000100 ++#define RATR_36M 0x00000200 ++#define RATR_48M 0x00000400 ++#define RATR_54M 0x00000800 ++//MCS 1 Spatial Stream ++#define RATR_MCS0 0x00001000 ++#define RATR_MCS1 0x00002000 ++#define RATR_MCS2 0x00004000 ++#define RATR_MCS3 0x00008000 ++#define RATR_MCS4 0x00010000 ++#define RATR_MCS5 0x00020000 ++#define RATR_MCS6 0x00040000 ++#define RATR_MCS7 0x00080000 ++//MCS 2 Spatial Stream ++#define RATR_MCS8 0x00100000 ++#define RATR_MCS9 0x00200000 ++#define RATR_MCS10 0x00400000 ++#define RATR_MCS11 0x00800000 ++#define RATR_MCS12 0x01000000 ++#define RATR_MCS13 0x02000000 ++#define RATR_MCS14 0x04000000 ++#define RATR_MCS15 0x08000000 ++// ALL CCK Rate ++#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M ++#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|RATR_36M|RATR_48M|RATR_54M ++#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \ ++ RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 ++#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \ ++ RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 ++ ++ ++ DRIVER_RSSI = 0x32c, // Driver tell Firmware current RSSI ++ MCS_TXAGC = 0x340, // MCS AGC ++ CCK_TXAGC = 0x348, // CCK AGC ++// IMR = 0x354, // Interrupt Mask Register ++// IMR_POLL = 0x360, ++ MacBlkCtrl = 0x403, // Mac block on/off control register ++ ++ //Cmd9346CR = 0x00e, ++//#define Cmd9346CR_9356SEL (1<<4) ++#if 0 ++/* 0x0006 - 0x0007 - reserved */ ++ RXFIFOCOUNT = 0x010, ++ TXFIFOCOUNT = 0x012, ++ BQREQ = 0x013, ++/* 0x0010 - 0x0017 - reserved */ ++ TSFTR = 0x018, ++ TLPDA = 0x020, ++ TNPDA = 0x024, ++ THPDA = 0x028, ++ BSSID = 0x02E, ++ RESP_RATE = 0x034, ++ CMD = 0x037, ++#define CMD_RST_SHIFT 4 ++#define CMD_RESERVED_MASK ((1<<1) | (1<<5) | (1<<6) | (1<<7)) ++#define CMD_RX_ENABLE_SHIFT 3 ++#define CMD_TX_ENABLE_SHIFT 2 ++#define CR_RST ((1<< 4)) ++#define CR_RE ((1<< 3)) ++#define CR_TE ((1<< 2)) ++#define CR_MulRW ((1<< 0)) ++ ++ INTA = 0x03e, ++#endif ++ ++/////////////////// ++////////////////// ++#if 0 ++ TX_CONF = 0x040, ++#define TX_CONF_HEADER_AUTOICREMENT_SHIFT 30 ++#define TX_LOOPBACK_SHIFT 17 ++#define TX_LOOPBACK_MAC 1 ++#define TX_LOOPBACK_BASEBAND 2 ++#define TX_LOOPBACK_NONE 0 ++#define TX_LOOPBACK_CONTINUE 3 ++#define TX_LOOPBACK_MASK ((1<<17)|(1<<18)) ++#define TX_LRLRETRY_SHIFT 0 ++#define TX_SRLRETRY_SHIFT 8 ++#define TX_NOICV_SHIFT 19 ++#define TX_NOCRC_SHIFT 16 ++#define TCR_DurProcMode ((1<<30)) ++#define TCR_DISReqQsize ((1<<28)) ++#define TCR_HWVERID_MASK ((1<<27)|(1<<26)|(1<<25)) ++#define TCR_HWVERID_SHIFT 25 ++#define TCR_SWPLCPLEN ((1<<24)) ++#define TCR_PLCP_LEN TCR_SAT // rtl8180 ++#define TCR_MXDMA_MASK ((1<<23)|(1<<22)|(1<<21)) ++#define TCR_MXDMA_1024 6 ++#define TCR_MXDMA_2048 7 ++#define TCR_MXDMA_SHIFT 21 ++#define TCR_DISCW ((1<<20)) ++#define TCR_ICV ((1<<19)) ++#define TCR_LBK ((1<<18)|(1<<17)) ++#define TCR_LBK1 ((1<<18)) ++#define TCR_LBK0 ((1<<17)) ++#define TCR_CRC ((1<<16)) ++#define TCR_SRL_MASK ((1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8)) ++#define TCR_LRL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)) ++#define TCR_PROBE_NOTIMESTAMP_SHIFT 29 //rtl8185 ++ ++ RX_CONF = 0x044, ++#define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \ ++(1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23)) ++#define RX_CHECK_BSSID_SHIFT 23 ++#define ACCEPT_PWR_FRAME_SHIFT 22 ++#define ACCEPT_MNG_FRAME_SHIFT 20 ++#define ACCEPT_CTL_FRAME_SHIFT 19 ++#define ACCEPT_DATA_FRAME_SHIFT 18 ++#define ACCEPT_ICVERR_FRAME_SHIFT 12 ++#define ACCEPT_CRCERR_FRAME_SHIFT 5 ++#define ACCEPT_BCAST_FRAME_SHIFT 3 ++#define ACCEPT_MCAST_FRAME_SHIFT 2 ++#define ACCEPT_ALLMAC_FRAME_SHIFT 0 ++#define ACCEPT_NICMAC_FRAME_SHIFT 1 ++#define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15)) ++#define RX_FIFO_THRESHOLD_SHIFT 13 ++#define RX_FIFO_THRESHOLD_128 3 ++#define RX_FIFO_THRESHOLD_256 4 ++#define RX_FIFO_THRESHOLD_512 5 ++#define RX_FIFO_THRESHOLD_1024 6 ++#define RX_FIFO_THRESHOLD_NONE 7 ++#define RX_AUTORESETPHY_SHIFT 28 ++#define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) ++#define MAX_RX_DMA_2048 7 ++#define MAX_RX_DMA_1024 6 ++#define MAX_RX_DMA_SHIFT 10 ++#define RCR_ONLYERLPKT ((1<<31)) ++#define RCR_CS_SHIFT 29 ++#define RCR_CS_MASK ((1<<30) | (1<<29)) ++#define RCR_ENMARP ((1<<28)) ++#define RCR_CBSSID ((1<<23)) ++#define RCR_APWRMGT ((1<<22)) ++#define RCR_ADD3 ((1<<21)) ++#define RCR_AMF ((1<<20)) ++#define RCR_ACF ((1<<19)) ++#define RCR_ADF ((1<<18)) ++#define RCR_RXFTH ((1<<15)|(1<<14)|(1<<13)) ++#define RCR_RXFTH2 ((1<<15)) ++#define RCR_RXFTH1 ((1<<14)) ++#define RCR_RXFTH0 ((1<<13)) ++#define RCR_AICV ((1<<12)) ++#define RCR_MXDMA ((1<<10)|(1<< 9)|(1<< 8)) ++#define RCR_MXDMA2 ((1<<10)) ++#define RCR_MXDMA1 ((1<< 9)) ++#define RCR_MXDMA0 ((1<< 8)) ++#define RCR_9356SEL ((1<< 6)) ++#define RCR_ACRC32 ((1<< 5)) ++#define RCR_AB ((1<< 3)) ++#define RCR_AM ((1<< 2)) ++#define RCR_APM ((1<< 1)) ++#define RCR_AAP ((1<< 0)) ++ ++ INT_TIMEOUT = 0x048, ++ ++ TX_BEACON_RING_ADDR = 0x04c, ++ ++#endif ++#if 0 ++ CONFIG0 = 0x051, ++#define CONFIG0_WEP104 ((1<<6)) ++#define CONFIG0_LEDGPO_En ((1<<4)) ++#define CONFIG0_Aux_Status ((1<<3)) ++#define CONFIG0_GL ((1<<1)|(1<<0)) ++#define CONFIG0_GL1 ((1<<1)) ++#define CONFIG0_GL0 ((1<<0)) ++ CONFIG1 = 0x052, ++#define CONFIG1_LEDS ((1<<7)|(1<<6)) ++#define CONFIG1_LEDS1 ((1<<7)) ++#define CONFIG1_LEDS0 ((1<<6)) ++#define CONFIG1_LWACT ((1<<4)) ++#define CONFIG1_MEMMAP ((1<<3)) ++#define CONFIG1_IOMAP ((1<<2)) ++#define CONFIG1_VPD ((1<<1)) ++#define CONFIG1_PMEn ((1<<0)) ++ CONFIG2 = 0x053, ++#define CONFIG2_LCK ((1<<7)) ++#define CONFIG2_ANT ((1<<6)) ++#define CONFIG2_DPS ((1<<3)) ++#define CONFIG2_PAPE_sign ((1<<2)) ++#define CONFIG2_PAPE_time ((1<<1)|(1<<0)) ++#define CONFIG2_PAPE_time1 ((1<<1)) ++#define CONFIG2_PAPE_time0 ((1<<0)) ++ ANA_PARAM = 0x054, ++ CONFIG3 = 0x059, ++#define CONFIG3_GNTSel ((1<<7)) ++#define CONFIG3_PARM_En ((1<<6)) ++#define CONFIG3_Magic ((1<<5)) ++#define CONFIG3_CardB_En ((1<<3)) ++#define CONFIG3_CLKRUN_En ((1<<2)) ++#define CONFIG3_FuncRegEn ((1<<1)) ++#define CONFIG3_FBtbEn ((1<<0)) ++#define CONFIG3_CLKRUN_SHIFT 2 ++#define CONFIG3_ANAPARAM_W_SHIFT 6 ++ CONFIG4 = 0x05a, ++#define CONFIG4_VCOPDN ((1<<7)) ++#define CONFIG4_PWROFF ((1<<6)) ++#define CONFIG4_PWRMGT ((1<<5)) ++#define CONFIG4_LWPME ((1<<4)) ++#define CONFIG4_LWPTN ((1<<2)) ++#define CONFIG4_RFTYPE ((1<<1)|(1<<0)) ++#define CONFIG4_RFTYPE1 ((1<<1)) ++#define CONFIG4_RFTYPE0 ((1<<0)) ++ TESTR = 0x05b, ++#define TFPC_AC 0x05C ++ ++#define SCR 0x05F ++ PGSELECT = 0x05e, ++#define PGSELECT_PG_SHIFT 0 ++ SECURITY = 0x05f, ++#define SECURITY_WEP_TX_ENABLE_SHIFT 1 ++#define SECURITY_WEP_RX_ENABLE_SHIFT 0 ++#define SECURITY_ENCRYP_104 1 ++#define SECURITY_ENCRYP_SHIFT 4 ++#define SECURITY_ENCRYP_MASK ((1<<4)|(1<<5)) ++ ++ ANA_PARAM2 = 0x060, ++ BEACON_INTERVAL = 0x070, ++#define BEACON_INTERVAL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)| \ ++(1<<6)|(1<<7)|(1<<8)|(1<<9)) ++ ++ ATIM_WND = 0x072, ++#define ATIM_WND_MASK (0x01FF) ++ ++ BCN_INTR_ITV = 0x074, ++#define BCN_INTR_ITV_MASK (0x01FF) ++ ++ ATIM_INTR_ITV = 0x076, ++#define ATIM_INTR_ITV_MASK (0x01FF) ++ ++ AckTimeOutReg = 0x079, //ACK timeout register, in unit of 4 us. ++ PHY_ADR = 0x07c, ++ PHY_READ = 0x07e, ++ RFPinsOutput = 0x080, ++ RFPinsEnable = 0x082, ++//Page 0 ++ RFPinsSelect = 0x084, ++#define SW_CONTROL_GPIO 0x400 ++ RFPinsInput = 0x086, ++ RF_PARA = 0x088, ++ RF_TIMING = 0x08c, ++ GP_ENABLE = 0x090, ++ GPIO = 0x091, ++ TX_AGC_CTL = 0x09c, ++#define TX_AGC_CTL_PER_PACKET_TXAGC 0x01 ++#define TX_AGC_CTL_PERPACKET_GAIN_SHIFT 0 ++#define TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT 1 ++#define TX_AGC_CTL_FEEDBACK_ANT 2 ++#define TXAGC_CTL_PER_PACKET_ANT_SEL 0x02 ++ OFDM_TXAGC = 0x09e, ++ ANTSEL = 0x09f, ++ ++ ++ ++ SIFS = 0x0b4, ++ DIFS = 0x0b5, ++ SLOT = 0x0b6, ++ CW_CONF = 0x0bc, ++#define CW_CONF_PERPACKET_RETRY_LIMIT 0x02 ++#define CW_CONF_PERPACKET_CW 0x01 ++#define CW_CONF_PERPACKET_RETRY_SHIFT 1 ++#define CW_CONF_PERPACKET_CW_SHIFT 0 ++ CW_VAL = 0x0bd, ++ RATE_FALLBACK = 0x0be, ++#define MAX_RESP_RATE_SHIFT 4 ++#define MIN_RESP_RATE_SHIFT 0 ++#define RATE_FALLBACK_CTL_ENABLE 0x80 ++#define RATE_FALLBACK_CTL_AUTO_STEP0 0x00 ++ ACM_CONTROL = 0x0BF, // ACM Control Registe ++//---------------------------------------------------------------------------- ++// 8187B ACM_CONTROL bits (Offset 0xBF, 1 Byte) ++//---------------------------------------------------------------------------- ++#define VOQ_ACM_EN (0x01 << 7) //BIT7 ++#define VIQ_ACM_EN (0x01 << 6) //BIT6 ++#define BEQ_ACM_EN (0x01 << 5) //BIT5 ++#define ACM_HW_EN (0x01 << 4) //BIT4 ++#define TXOPSEL (0x01 << 3) //BIT3 ++#define VOQ_ACM_CTL (0x01 << 2) //BIT2 // Set to 1 when AC_VO used time reaches or exceeds the admitted time ++#define VIQ_ACM_CTL (0x01 << 1) //BIT1 // Set to 1 when AC_VI used time reaches or exceeds the admitted time ++#define BEQ_ACM_CTL (0x01 << 0) //BIT0 // Set to 1 when AC_BE used time reaches or exceeds the admitted time ++ CONFIG5 = 0x0D8, ++#define CONFIG5_TX_FIFO_OK ((1<<7)) ++#define CONFIG5_RX_FIFO_OK ((1<<6)) ++#define CONFIG5_CALON ((1<<5)) ++#define CONFIG5_EACPI ((1<<2)) ++#define CONFIG5_LANWake ((1<<1)) ++#define CONFIG5_PME_STS ((1<<0)) ++ TX_DMA_POLLING = 0x0fd, ++#define TX_DMA_POLLING_BEACON_SHIFT 7 ++#define TX_DMA_POLLING_HIPRIORITY_SHIFT 6 ++#define TX_DMA_POLLING_NORMPRIORITY_SHIFT 5 ++#define TX_DMA_POLLING_LOWPRIORITY_SHIFT 4 ++#define TX_DMA_STOP_BEACON_SHIFT 3 ++#define TX_DMA_STOP_HIPRIORITY_SHIFT 2 ++#define TX_DMA_STOP_NORMPRIORITY_SHIFT 1 ++#define TX_DMA_STOP_LOWPRIORITY_SHIFT 0 ++ CWR = 0x0DC, ++ RetryCTR = 0x0DE, ++ INT_MIG = 0x0E2, // Interrupt Migration (0xE2 ~ 0xE3) ++ TID_AC_MAP = 0x0E8, // TID to AC Mapping Register ++ ANA_PARAM3 = 0x0EE, ++ ++ ++//page 1 ++ Wakeup0 = 0x084, ++ Wakeup1 = 0x08C, ++ Wakeup2LD = 0x094, ++ Wakeup2HD = 0x09C, ++ Wakeup3LD = 0x0A4, ++ Wakeup3HD = 0x0AC, ++ Wakeup4LD = 0x0B4, ++ Wakeup4HD = 0x0BC, ++ CRC0 = 0x0C4, ++ CRC1 = 0x0C6, ++ CRC2 = 0x0C8, ++ CRC3 = 0x0CA, ++ CRC4 = 0x0CC, ++/* 0x00CE - 0x00D3 - reserved */ ++ ++ RFSW_CTRL = 0x272, // 0x272-0x273. ++ ++/**************************************************************************/ ++ FER = 0x0F0, ++ FEMR = 0x0F4, ++ FPSR = 0x0F8, ++ FFER = 0x0FC, ++ ++ AC_VO_PARAM = 0x0F0, // AC_VO Parameters Record ++ AC_VI_PARAM = 0x0F4, // AC_VI Parameters Record ++ AC_BE_PARAM = 0x0F8, // AC_BE Parameters Record ++ AC_BK_PARAM = 0x0FC, // AC_BK Parameters Record ++ TALLY_SEL = 0x0fc, ++#endif ++} ++; ++//---------------------------------------------------------------------------- ++// 818xB AnaParm & AnaParm2 Register ++//---------------------------------------------------------------------------- ++//#define ANAPARM_ASIC_ON 0x45090658 ++//#define ANAPARM2_ASIC_ON 0x727f3f52 ++ ++#define GPI 0x108 ++#define GPO 0x109 ++#define GPE 0x10a ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r8192E_wx.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E_wx.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E_wx.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,1409 @@ ++/* ++ This file contains wireless extension handlers. ++ ++ This is part of rtl8180 OpenSource driver. ++ Copyright (C) Andrea Merello 2004-2005 ++ Released under the terms of GPL (General Public Licence) ++ ++ Parts of this driver are based on the GPL part ++ of the official realtek driver. ++ ++ Parts of this driver are based on the rtl8180 driver skeleton ++ from Patric Schenke & Andres Salomon. ++ ++ Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver. ++ ++ We want to tanks the Authors of those projects and the Ndiswrapper ++ project Authors. ++*/ ++ ++#include ++#include "r8192E.h" ++#include "r8192E_hw.h" ++#include "r8192E_wx.h" ++#ifdef ENABLE_DOT11D ++#include "dot11d.h" ++#endif ++ ++#define RATE_COUNT 12 ++static u32 rtl8180_rates[] = {1000000,2000000,5500000,11000000, ++ 6000000,9000000,12000000,18000000,24000000,36000000,48000000,54000000}; ++ ++ ++#ifndef ENETDOWN ++#define ENETDOWN 1 ++#endif ++static int r8192_wx_get_freq(struct net_device *dev, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ return ieee80211_wx_get_freq(priv->ieee80211,a,wrqu,b); ++} ++ ++ ++#if 0 ++ ++static int r8192_wx_set_beaconinterval(struct net_device *dev, struct iw_request_info *aa, ++ union iwreq_data *wrqu, char *b) ++{ ++ int *parms = (int *)b; ++ int bi = parms[0]; ++ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ down(&priv->wx_sem); ++ DMESG("setting beacon interval to %x",bi); ++ ++ priv->ieee80211->beacon_interval=bi; ++ rtl8180_commit(dev); ++ up(&priv->wx_sem); ++ ++ return 0; ++} ++ ++ ++static int r8192_wx_set_forceassociate(struct net_device *dev, struct iw_request_info *aa, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv=ieee80211_priv(dev); ++ int *parms = (int *)extra; ++ ++ priv->ieee80211->force_associate = (parms[0] > 0); ++ ++ ++ return 0; ++} ++ ++#endif ++static int r8192_wx_get_mode(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ struct r8192_priv *priv=ieee80211_priv(dev); ++ ++ return ieee80211_wx_get_mode(priv->ieee80211,a,wrqu,b); ++} ++ ++ ++ ++static int r8192_wx_get_rate(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ return ieee80211_wx_get_rate(priv->ieee80211,info,wrqu,extra); ++} ++ ++ ++ ++static int r8192_wx_set_rate(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ down(&priv->wx_sem); ++ ++ ret = ieee80211_wx_set_rate(priv->ieee80211,info,wrqu,extra); ++ ++ up(&priv->wx_sem); ++ ++ return ret; ++} ++ ++ ++static int r8192_wx_set_rts(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ down(&priv->wx_sem); ++ ++ ret = ieee80211_wx_set_rts(priv->ieee80211,info,wrqu,extra); ++ ++ up(&priv->wx_sem); ++ ++ return ret; ++} ++ ++static int r8192_wx_get_rts(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ return ieee80211_wx_get_rts(priv->ieee80211,info,wrqu,extra); ++} ++ ++static int r8192_wx_set_power(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ down(&priv->wx_sem); ++ ++ ret = ieee80211_wx_set_power(priv->ieee80211,info,wrqu,extra); ++ ++ up(&priv->wx_sem); ++ ++ return ret; ++} ++ ++static int r8192_wx_get_power(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ return ieee80211_wx_get_power(priv->ieee80211,info,wrqu,extra); ++} ++ ++#ifdef JOHN_IOCTL ++u16 read_rtl8225(struct net_device *dev, u8 addr); ++void write_rtl8225(struct net_device *dev, u8 adr, u16 data); ++u32 john_read_rtl8225(struct net_device *dev, u8 adr); ++void _write_rtl8225(struct net_device *dev, u8 adr, u16 data); ++ ++static int r8192_wx_read_regs(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 addr; ++ u16 data1; ++ ++ down(&priv->wx_sem); ++ ++ ++ get_user(addr,(u8*)wrqu->data.pointer); ++ data1 = read_rtl8225(dev, addr); ++ wrqu->data.length = data1; ++ ++ up(&priv->wx_sem); ++ return 0; ++ ++} ++ ++static int r8192_wx_write_regs(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 addr; ++ ++ down(&priv->wx_sem); ++ ++ get_user(addr, (u8*)wrqu->data.pointer); ++ write_rtl8225(dev, addr, wrqu->data.length); ++ ++ up(&priv->wx_sem); ++ return 0; ++ ++} ++ ++void rtl8187_write_phy(struct net_device *dev, u8 adr, u32 data); ++u8 rtl8187_read_phy(struct net_device *dev,u8 adr, u32 data); ++ ++static int r8192_wx_read_bb(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 databb; ++#if 0 ++ int i; ++ for(i=0;i<12;i++) printk("%8x\n", read_cam(dev, i) ); ++#endif ++ ++ down(&priv->wx_sem); ++ ++ databb = rtl8187_read_phy(dev, (u8)wrqu->data.length, 0x00000000); ++ wrqu->data.length = databb; ++ ++ up(&priv->wx_sem); ++ return 0; ++} ++ ++void rtl8187_write_phy(struct net_device *dev, u8 adr, u32 data); ++static int r8192_wx_write_bb(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 databb; ++ ++ down(&priv->wx_sem); ++ ++ get_user(databb, (u8*)wrqu->data.pointer); ++ rtl8187_write_phy(dev, wrqu->data.length, databb); ++ ++ up(&priv->wx_sem); ++ return 0; ++ ++} ++ ++ ++static int r8192_wx_write_nicb(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u32 addr; ++ ++ down(&priv->wx_sem); ++ ++ get_user(addr, (u32*)wrqu->data.pointer); ++ write_nic_byte(dev, addr, wrqu->data.length); ++ ++ up(&priv->wx_sem); ++ return 0; ++ ++} ++static int r8192_wx_read_nicb(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u32 addr; ++ u16 data1; ++ ++ down(&priv->wx_sem); ++ ++ get_user(addr,(u32*)wrqu->data.pointer); ++ data1 = read_nic_byte(dev, addr); ++ wrqu->data.length = data1; ++ ++ up(&priv->wx_sem); ++ return 0; ++} ++ ++static int r8192_wx_get_ap_status(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ struct ieee80211_device *ieee = priv->ieee80211; ++ struct ieee80211_network *target; ++ int name_len; ++ ++ down(&priv->wx_sem); ++ ++ //count the length of input ssid ++ for(name_len=0 ; ((char*)wrqu->data.pointer)[name_len]!='\0' ; name_len++); ++ ++ //search for the correspoding info which is received ++ list_for_each_entry(target, &ieee->network_list, list) { ++ if ( (target->ssid_len == name_len) && ++ (strncmp(target->ssid, (char*)wrqu->data.pointer, name_len)==0)){ ++ if(target->wpa_ie_len>0 || target->rsn_ie_len>0 ) ++ //set flags=1 to indicate this ap is WPA ++ wrqu->data.flags = 1; ++ else wrqu->data.flags = 0; ++ ++ ++ break; ++ } ++ } ++ ++ up(&priv->wx_sem); ++ return 0; ++} ++ ++ ++ ++#endif ++ ++static int r8192_wx_set_rawtx(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ int ret; ++ ++ down(&priv->wx_sem); ++ ++ ret = ieee80211_wx_set_rawtx(priv->ieee80211, info, wrqu, extra); ++ ++ up(&priv->wx_sem); ++ ++ return ret; ++ ++} ++ ++static int r8192_wx_force_reset(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ down(&priv->wx_sem); ++ ++ printk("%s(): force reset ! extra is %d\n",__FUNCTION__, *extra); ++ priv->force_reset = *extra; ++ up(&priv->wx_sem); ++ return 0; ++ ++} ++ ++ ++static int r8192_wx_set_crcmon(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ int *parms = (int *)extra; ++ int enable = (parms[0] > 0); ++ short prev = priv->crcmon; ++ ++ down(&priv->wx_sem); ++ ++ if(enable) ++ priv->crcmon=1; ++ else ++ priv->crcmon=0; ++ ++ DMESG("bad CRC in monitor mode are %s", ++ priv->crcmon ? "accepted" : "rejected"); ++ ++ if(prev != priv->crcmon && priv->up){ ++ //rtl8180_down(dev); ++ //rtl8180_up(dev); ++ } ++ ++ up(&priv->wx_sem); ++ ++ return 0; ++} ++ ++static int r8192_wx_set_mode(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ RT_RF_POWER_STATE rtState; ++ int ret; ++ ++ rtState = priv->ieee80211->eRFPowerState; ++ down(&priv->wx_sem); ++#ifdef ENABLE_IPS ++ if(wrqu->mode == IW_MODE_ADHOC){ ++ ++ if(priv->ieee80211->PowerSaveControl.bInactivePs){ ++ if(rtState == eRfOff){ ++ if(priv->ieee80211->RfOffReason > RF_CHANGE_BY_IPS) ++ { ++ RT_TRACE(COMP_ERR, "%s(): RF is OFF.\n",__FUNCTION__); ++ up(&priv->wx_sem); ++ return -1; ++ } ++ else{ ++ printk("=========>%s(): IPSLeave\n",__FUNCTION__); ++ IPSLeave(dev); ++ } ++ } ++ } ++ } ++#endif ++ ret = ieee80211_wx_set_mode(priv->ieee80211,a,wrqu,b); ++ ++ //rtl8187_set_rxconf(dev); ++ ++ up(&priv->wx_sem); ++ return ret; ++} ++ ++struct iw_range_with_scan_capa ++{ ++ /* Informative stuff (to choose between different interface) */ ++ __u32 throughput; /* To give an idea... */ ++ /* In theory this value should be the maximum benchmarked ++ * TCP/IP throughput, because with most of these devices the ++ * bit rate is meaningless (overhead an co) to estimate how ++ * fast the connection will go and pick the fastest one. ++ * I suggest people to play with Netperf or any benchmark... ++ */ ++ ++ /* NWID (or domain id) */ ++ __u32 min_nwid; /* Minimal NWID we are able to set */ ++ __u32 max_nwid; /* Maximal NWID we are able to set */ ++ ++ /* Old Frequency (backward compat - moved lower ) */ ++ __u16 old_num_channels; ++ __u8 old_num_frequency; ++ ++ /* Scan capabilities */ ++ __u8 scan_capa; ++}; ++static int rtl8180_wx_get_range(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct iw_range *range = (struct iw_range *)extra; ++ struct iw_range_with_scan_capa* tmp = (struct iw_range_with_scan_capa*)range; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u16 val; ++ int i; ++ ++ wrqu->data.length = sizeof(*range); ++ memset(range, 0, sizeof(*range)); ++ ++ /* Let's try to keep this struct in the same order as in ++ * linux/include/wireless.h ++ */ ++ ++ /* TODO: See what values we can set, and remove the ones we can't ++ * set, or fill them with some default data. ++ */ ++ ++ /* ~5 Mb/s real (802.11b) */ ++ range->throughput = 5 * 1000 * 1000; ++ ++ // TODO: Not used in 802.11b? ++// range->min_nwid; /* Minimal NWID we are able to set */ ++ // TODO: Not used in 802.11b? ++// range->max_nwid; /* Maximal NWID we are able to set */ ++ ++ /* Old Frequency (backward compat - moved lower ) */ ++// range->old_num_channels; ++// range->old_num_frequency; ++// range->old_freq[6]; /* Filler to keep "version" at the same offset */ ++ if(priv->rf_set_sens != NULL) ++ range->sensitivity = priv->max_sens; /* signal level threshold range */ ++ ++ range->max_qual.qual = 100; ++ /* TODO: Find real max RSSI and stick here */ ++ range->max_qual.level = 0; ++ range->max_qual.noise = -98; ++ range->max_qual.updated = 7; /* Updated all three */ ++ ++ range->avg_qual.qual = 92; /* > 8% missed beacons is 'bad' */ ++ /* TODO: Find real 'good' to 'bad' threshol value for RSSI */ ++ range->avg_qual.level = 20 + -98; ++ range->avg_qual.noise = 0; ++ range->avg_qual.updated = 7; /* Updated all three */ ++ ++ range->num_bitrates = RATE_COUNT; ++ ++ for (i = 0; i < RATE_COUNT && i < IW_MAX_BITRATES; i++) { ++ range->bitrate[i] = rtl8180_rates[i]; ++ } ++ ++ range->min_frag = MIN_FRAG_THRESHOLD; ++ range->max_frag = MAX_FRAG_THRESHOLD; ++ ++ range->min_pmp=0; ++ range->max_pmp = 5000000; ++ range->min_pmt = 0; ++ range->max_pmt = 65535*1000; ++ range->pmp_flags = IW_POWER_PERIOD; ++ range->pmt_flags = IW_POWER_TIMEOUT; ++ range->pm_capa = IW_POWER_PERIOD | IW_POWER_TIMEOUT | IW_POWER_ALL_R; ++ range->we_version_compiled = WIRELESS_EXT; ++ range->we_version_source = 16; ++ ++// range->retry_capa; /* What retry options are supported */ ++// range->retry_flags; /* How to decode max/min retry limit */ ++// range->r_time_flags; /* How to decode max/min retry life */ ++// range->min_retry; /* Minimal number of retries */ ++// range->max_retry; /* Maximal number of retries */ ++// range->min_r_time; /* Minimal retry lifetime */ ++// range->max_r_time; /* Maximal retry lifetime */ ++ ++ ++ for (i = 0, val = 0; i < 14; i++) { ++ ++ // Include only legal frequencies for some countries ++#ifdef ENABLE_DOT11D ++ if ((GET_DOT11D_INFO(priv->ieee80211)->channel_map)[i+1]) { ++#else ++ if ((priv->ieee80211->channel_map)[i+1]) { ++#endif ++ range->freq[val].i = i + 1; ++ range->freq[val].m = ieee80211_wlan_frequencies[i] * 100000; ++ range->freq[val].e = 1; ++ val++; ++ } else { ++ // FIXME: do we need to set anything for channels ++ // we don't use ? ++ } ++ ++ if (val == IW_MAX_FREQUENCIES) ++ break; ++ } ++ range->num_frequency = val; ++ range->num_channels = val; ++#if WIRELESS_EXT > 17 ++ range->enc_capa = IW_ENC_CAPA_WPA|IW_ENC_CAPA_WPA2| ++ IW_ENC_CAPA_CIPHER_TKIP|IW_ENC_CAPA_CIPHER_CCMP; ++#endif ++ tmp->scan_capa = 0x01; ++ return 0; ++} ++ ++ ++static int r8192_wx_set_scan(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ struct ieee80211_device* ieee = priv->ieee80211; ++ RT_RF_POWER_STATE rtState; ++ int ret; ++ rtState = priv->ieee80211->eRFPowerState; ++ if(!priv->up) return -ENETDOWN; ++ if (priv->ieee80211->LinkDetectInfo.bBusyTraffic == true) ++ return -EAGAIN; ++ ++ if (wrqu->data.flags & IW_SCAN_THIS_ESSID) ++ { ++ struct iw_scan_req* req = (struct iw_scan_req*)b; ++ if (req->essid_len) ++ { ++ //printk("==**&*&*&**===>scan set ssid:%s\n", req->essid); ++ ieee->current_network.ssid_len = req->essid_len; ++ memcpy(ieee->current_network.ssid, req->essid, req->essid_len); ++ //printk("=====>network ssid:%s\n", ieee->current_network.ssid); ++ } ++ } ++ ++ down(&priv->wx_sem); ++#ifdef ENABLE_IPS ++ priv->ieee80211->actscanning = true; ++ if(priv->ieee80211->state != IEEE80211_LINKED){ ++ if(priv->ieee80211->PowerSaveControl.bInactivePs){ ++ if(rtState == eRfOff){ ++ if(priv->ieee80211->RfOffReason > RF_CHANGE_BY_IPS) ++ { ++ RT_TRACE(COMP_ERR, "%s(): RF is OFF.\n",__FUNCTION__); ++ up(&priv->wx_sem); ++ return -1; ++ } ++ else{ ++ printk("=========>%s(): IPSLeave\n",__FUNCTION__); ++ IPSLeave(dev); ++ } ++ } ++ } ++ priv->ieee80211->scanning = 0; ++ ieee80211_softmac_scan_syncro(priv->ieee80211); ++ ret = 0; ++ } ++ else ++#else ++ ++ if(priv->ieee80211->state != IEEE80211_LINKED){ ++ priv->ieee80211->scanning = 0; ++ ieee80211_softmac_scan_syncro(priv->ieee80211); ++ ret = 0; ++ } ++ else ++#endif ++ ret = ieee80211_wx_set_scan(priv->ieee80211,a,wrqu,b); ++ ++ up(&priv->wx_sem); ++ return ret; ++} ++ ++ ++static int r8192_wx_get_scan(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ ++ int ret; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ if(!priv->up) return -ENETDOWN; ++ ++ down(&priv->wx_sem); ++ ++ ret = ieee80211_wx_get_scan(priv->ieee80211,a,wrqu,b); ++ ++ up(&priv->wx_sem); ++ ++ return ret; ++} ++ ++static int r8192_wx_set_essid(struct net_device *dev, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ RT_RF_POWER_STATE rtState; ++ int ret; ++ ++ rtState = priv->ieee80211->eRFPowerState; ++ down(&priv->wx_sem); ++#ifdef ENABLE_IPS ++ if(priv->ieee80211->PowerSaveControl.bInactivePs){ ++ if(rtState == eRfOff){ ++ if(priv->ieee80211->RfOffReason > RF_CHANGE_BY_IPS) ++ { ++ RT_TRACE(COMP_ERR, "%s(): RF is OFF.\n",__FUNCTION__); ++ up(&priv->wx_sem); ++ return -1; ++ } ++ else{ ++ printk("=========>%s(): IPSLeave\n",__FUNCTION__); ++ IPSLeave(dev); ++ } ++ } ++ } ++#endif ++ ret = ieee80211_wx_set_essid(priv->ieee80211,a,wrqu,b); ++ ++ up(&priv->wx_sem); ++ ++ return ret; ++} ++ ++ ++ ++ ++static int r8192_wx_get_essid(struct net_device *dev, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ int ret; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ down(&priv->wx_sem); ++ ++ ret = ieee80211_wx_get_essid(priv->ieee80211, a, wrqu, b); ++ ++ up(&priv->wx_sem); ++ ++ return ret; ++} ++ ++ ++static int r8192_wx_set_freq(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ int ret; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ down(&priv->wx_sem); ++ ++ ret = ieee80211_wx_set_freq(priv->ieee80211, a, wrqu, b); ++ ++ up(&priv->wx_sem); ++ return ret; ++} ++ ++static int r8192_wx_get_name(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ return ieee80211_wx_get_name(priv->ieee80211, info, wrqu, extra); ++} ++ ++ ++static int r8192_wx_set_frag(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ if (wrqu->frag.disabled) ++ priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD; ++ else { ++ if (wrqu->frag.value < MIN_FRAG_THRESHOLD || ++ wrqu->frag.value > MAX_FRAG_THRESHOLD) ++ return -EINVAL; ++ ++ priv->ieee80211->fts = wrqu->frag.value & ~0x1; ++ } ++ ++ return 0; ++} ++ ++ ++static int r8192_wx_get_frag(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ wrqu->frag.value = priv->ieee80211->fts; ++ wrqu->frag.fixed = 0; /* no auto select */ ++ wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD); ++ ++ return 0; ++} ++ ++ ++static int r8192_wx_set_wap(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *awrq, ++ char *extra) ++{ ++ ++ int ret; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++// struct sockaddr *temp = (struct sockaddr *)awrq; ++ ++ down(&priv->wx_sem); ++ ++ ret = ieee80211_wx_set_wap(priv->ieee80211,info,awrq,extra); ++ ++ up(&priv->wx_sem); ++ ++ return ret; ++ ++} ++ ++ ++static int r8192_wx_get_wap(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ return ieee80211_wx_get_wap(priv->ieee80211,info,wrqu,extra); ++} ++ ++ ++static int r8192_wx_get_enc(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *key) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ return ieee80211_wx_get_encode(priv->ieee80211, info, wrqu, key); ++} ++ ++static int r8192_wx_set_enc(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *key) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ int ret; ++ ++ struct ieee80211_device *ieee = priv->ieee80211; ++ //u32 TargetContent; ++ u32 hwkey[4]={0,0,0,0}; ++ u8 mask=0xff; ++ u32 key_idx=0; ++ u8 zero_addr[4][6] ={ {0x00,0x00,0x00,0x00,0x00,0x00}, ++ {0x00,0x00,0x00,0x00,0x00,0x01}, ++ {0x00,0x00,0x00,0x00,0x00,0x02}, ++ {0x00,0x00,0x00,0x00,0x00,0x03} }; ++ int i; ++ ++ if(!priv->up) return -ENETDOWN; ++ ++ down(&priv->wx_sem); ++ ++ RT_TRACE(COMP_SEC, "Setting SW wep key"); ++ ret = ieee80211_wx_set_encode(priv->ieee80211,info,wrqu,key); ++ ++ up(&priv->wx_sem); ++ ++ ++ //sometimes, the length is zero while we do not type key value ++ if(wrqu->encoding.length!=0){ ++ ++ for(i=0 ; i<4 ; i++){ ++ hwkey[i] |= key[4*i+0]&mask; ++ if(i==1&&(4*i+1)==wrqu->encoding.length) mask=0x00; ++ if(i==3&&(4*i+1)==wrqu->encoding.length) mask=0x00; ++ hwkey[i] |= (key[4*i+1]&mask)<<8; ++ hwkey[i] |= (key[4*i+2]&mask)<<16; ++ hwkey[i] |= (key[4*i+3]&mask)<<24; ++ } ++ ++ #define CONF_WEP40 0x4 ++ #define CONF_WEP104 0x14 ++ ++ switch(wrqu->encoding.flags & IW_ENCODE_INDEX){ ++ case 0: key_idx = ieee->tx_keyidx; break; ++ case 1: key_idx = 0; break; ++ case 2: key_idx = 1; break; ++ case 3: key_idx = 2; break; ++ case 4: key_idx = 3; break; ++ default: break; ++ } ++ ++ //printk("-------====>length:%d, key_idx:%d, flag:%x\n", wrqu->encoding.length, key_idx, wrqu->encoding.flags); ++ if(wrqu->encoding.length==0x5){ ++ ieee->pairwise_key_type = KEY_TYPE_WEP40; ++ EnableHWSecurityConfig8192(dev); ++ setKey( dev, ++ key_idx, //EntryNo ++ key_idx, //KeyIndex ++ KEY_TYPE_WEP40, //KeyType ++ zero_addr[key_idx], ++ 0, //DefaultKey ++ hwkey); //KeyContent ++ ++#if 0 ++ if(key_idx == 0){ ++ ++ //write_nic_byte(dev, SECR, 7); ++ setKey( dev, ++ 4, //EntryNo ++ key_idx, //KeyIndex ++ KEY_TYPE_WEP40, //KeyType ++ broadcast_addr, //addr ++ 0, //DefaultKey ++ hwkey); //KeyContent ++ } ++#endif ++ } ++ ++ else if(wrqu->encoding.length==0xd){ ++ ieee->pairwise_key_type = KEY_TYPE_WEP104; ++ EnableHWSecurityConfig8192(dev); ++ setKey( dev, ++ key_idx, //EntryNo ++ key_idx, //KeyIndex ++ KEY_TYPE_WEP104, //KeyType ++ zero_addr[key_idx], ++ 0, //DefaultKey ++ hwkey); //KeyContent ++#if 0 ++ if(key_idx == 0){ ++ ++ //write_nic_byte(dev, SECR, 7); ++ setKey( dev, ++ 4, //EntryNo ++ key_idx, //KeyIndex ++ KEY_TYPE_WEP104, //KeyType ++ broadcast_addr, //addr ++ 0, //DefaultKey ++ hwkey); //KeyContent ++ } ++#endif ++ } ++ else printk("wrong type in WEP, not WEP40 and WEP104\n"); ++ ++ ++ } ++ ++#if 0 ++ //consider the setting different key index situation ++ //wrqu->encoding.flags = 801 means that we set key with index "1" ++ if(wrqu->encoding.length==0 && (wrqu->encoding.flags >>8) == 0x8 ){ ++ printk("===>1\n"); ++ //write_nic_byte(dev, SECR, 7); ++ EnableHWSecurityConfig8192(dev); ++ //copy wpa config from default key(key0~key3) to broadcast key(key5) ++ // ++ key_idx = (wrqu->encoding.flags & 0xf)-1 ; ++ write_cam(dev, (4*6), 0xffff0000|read_cam(dev, key_idx*6) ); ++ write_cam(dev, (4*6)+1, 0xffffffff); ++ write_cam(dev, (4*6)+2, read_cam(dev, (key_idx*6)+2) ); ++ write_cam(dev, (4*6)+3, read_cam(dev, (key_idx*6)+3) ); ++ write_cam(dev, (4*6)+4, read_cam(dev, (key_idx*6)+4) ); ++ write_cam(dev, (4*6)+5, read_cam(dev, (key_idx*6)+5) ); ++ } ++#endif ++ ++ return ret; ++} ++ ++ ++static int r8192_wx_set_scan_type(struct net_device *dev, struct iw_request_info *aa, union ++ iwreq_data *wrqu, char *p){ ++ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ int *parms=(int*)p; ++ int mode=parms[0]; ++ ++ priv->ieee80211->active_scan = mode; ++ ++ return 1; ++} ++ ++ ++ ++static int r8192_wx_set_retry(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ int err = 0; ++ ++ down(&priv->wx_sem); ++ ++ if (wrqu->retry.flags & IW_RETRY_LIFETIME || ++ wrqu->retry.disabled){ ++ err = -EINVAL; ++ goto exit; ++ } ++ if (!(wrqu->retry.flags & IW_RETRY_LIMIT)){ ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ if(wrqu->retry.value > R8180_MAX_RETRY){ ++ err= -EINVAL; ++ goto exit; ++ } ++ if (wrqu->retry.flags & IW_RETRY_MAX) { ++ priv->retry_rts = wrqu->retry.value; ++ DMESG("Setting retry for RTS/CTS data to %d", wrqu->retry.value); ++ ++ }else { ++ priv->retry_data = wrqu->retry.value; ++ DMESG("Setting retry for non RTS/CTS data to %d", wrqu->retry.value); ++ } ++ ++ /* FIXME ! ++ * We might try to write directly the TX config register ++ * or to restart just the (R)TX process. ++ * I'm unsure if whole reset is really needed ++ */ ++ ++ rtl8192_commit(dev); ++ /* ++ if(priv->up){ ++ rtl8180_rtx_disable(dev); ++ rtl8180_rx_enable(dev); ++ rtl8180_tx_enable(dev); ++ ++ } ++ */ ++exit: ++ up(&priv->wx_sem); ++ ++ return err; ++} ++ ++static int r8192_wx_get_retry(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ ++ wrqu->retry.disabled = 0; /* can't be disabled */ ++ ++ if ((wrqu->retry.flags & IW_RETRY_TYPE) == ++ IW_RETRY_LIFETIME) ++ return -EINVAL; ++ ++ if (wrqu->retry.flags & IW_RETRY_MAX) { ++ wrqu->retry.flags = IW_RETRY_LIMIT & IW_RETRY_MAX; ++ wrqu->retry.value = priv->retry_rts; ++ } else { ++ wrqu->retry.flags = IW_RETRY_LIMIT & IW_RETRY_MIN; ++ wrqu->retry.value = priv->retry_data; ++ } ++ //DMESG("returning %d",wrqu->retry.value); ++ ++ ++ return 0; ++} ++ ++static int r8192_wx_get_sens(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ if(priv->rf_set_sens == NULL) ++ return -1; /* we have not this support for this radio */ ++ wrqu->sens.value = priv->sens; ++ return 0; ++} ++ ++ ++static int r8192_wx_set_sens(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ short err = 0; ++ down(&priv->wx_sem); ++ //DMESG("attempt to set sensivity to %ddb",wrqu->sens.value); ++ if(priv->rf_set_sens == NULL) { ++ err= -1; /* we have not this support for this radio */ ++ goto exit; ++ } ++ if(priv->rf_set_sens(dev, wrqu->sens.value) == 0) ++ priv->sens = wrqu->sens.value; ++ else ++ err= -EINVAL; ++ ++exit: ++ up(&priv->wx_sem); ++ ++ return err; ++} ++ ++#if (WIRELESS_EXT >= 18) ++#if 0 ++static int r8192_wx_get_enc_ext(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ int ret = 0; ++ ret = ieee80211_wx_get_encode_ext(priv->ieee80211, info, wrqu, extra); ++ return ret; ++} ++#endif ++static int r8192_wx_set_enc_ext(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret=0; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ struct ieee80211_device* ieee = priv->ieee80211; ++ ++ down(&priv->wx_sem); ++ ret = ieee80211_wx_set_encode_ext(ieee, info, wrqu, extra); ++ ++ { ++ u8 broadcast_addr[6] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++ u8 zero[6] = {0}; ++ u32 key[4] = {0}; ++ struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; ++ struct iw_point *encoding = &wrqu->encoding; ++#if 0 ++ static u8 CAM_CONST_ADDR[4][6] = { ++ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, ++ {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, ++ {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, ++ {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}}; ++#endif ++ u8 idx = 0, alg = 0, group = 0; ++ if ((encoding->flags & IW_ENCODE_DISABLED) || ++ ext->alg == IW_ENCODE_ALG_NONE) //none is not allowed to use hwsec WB 2008.07.01 ++ { ++ ieee->pairwise_key_type = ieee->group_key_type = KEY_TYPE_NA; ++ CamResetAllEntry(dev); ++ goto end_hw_sec; ++ } ++ alg = (ext->alg == IW_ENCODE_ALG_CCMP)?KEY_TYPE_CCMP:ext->alg; // as IW_ENCODE_ALG_CCMP is defined to be 3 and KEY_TYPE_CCMP is defined to 4; ++ idx = encoding->flags & IW_ENCODE_INDEX; ++ if (idx) ++ idx --; ++ group = ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY; ++ ++ if ((!group) || (IW_MODE_ADHOC == ieee->iw_mode) || (alg == KEY_TYPE_WEP40)) ++ { ++ if ((ext->key_len == 13) && (alg == KEY_TYPE_WEP40) ) ++ alg = KEY_TYPE_WEP104; ++ ieee->pairwise_key_type = alg; ++ EnableHWSecurityConfig8192(dev); ++ } ++ memcpy((u8*)key, ext->key, 16); //we only get 16 bytes key.why? WB 2008.7.1 ++ ++ if ((alg & KEY_TYPE_WEP40) && (ieee->auth_mode !=2) ) ++ { ++ if (ext->key_len == 13) ++ ieee->pairwise_key_type = alg = KEY_TYPE_WEP104; ++ setKey( dev, ++ idx,//EntryNo ++ idx, //KeyIndex ++ alg, //KeyType ++ zero, //MacAddr ++ 0, //DefaultKey ++ key); //KeyContent ++ } ++ else if (group) ++ { ++ ieee->group_key_type = alg; ++ setKey( dev, ++ idx,//EntryNo ++ idx, //KeyIndex ++ alg, //KeyType ++ broadcast_addr, //MacAddr ++ 0, //DefaultKey ++ key); //KeyContent ++ } ++ else //pairwise key ++ { ++ if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) && ieee->pHTInfo->bCurrentHTSupport){ ++ write_nic_byte(dev, 0x173, 1); //fix aes bug ++ } ++ setKey( dev, ++ 4,//EntryNo ++ idx, //KeyIndex ++ alg, //KeyType ++ (u8*)ieee->ap_mac_addr, //MacAddr ++ 0, //DefaultKey ++ key); //KeyContent ++ } ++ ++ ++ } ++ ++end_hw_sec: ++ up(&priv->wx_sem); ++#endif ++ return ret; ++ ++} ++static int r8192_wx_set_auth(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *data, char *extra) ++{ ++ int ret=0; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ //printk("====>%s()\n", __FUNCTION__); ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ down(&priv->wx_sem); ++ ret = ieee80211_wx_set_auth(priv->ieee80211, info, &(data->param), extra); ++ up(&priv->wx_sem); ++#endif ++ return ret; ++} ++ ++static int r8192_wx_set_mlme(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ //printk("====>%s()\n", __FUNCTION__); ++ ++ int ret=0; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ down(&priv->wx_sem); ++ ret = ieee80211_wx_set_mlme(priv->ieee80211, info, wrqu, extra); ++ up(&priv->wx_sem); ++#endif ++ return ret; ++} ++#endif ++static int r8192_wx_set_gen_ie(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *data, char *extra) ++{ ++ //printk("====>%s(), len:%d\n", __FUNCTION__, data->length); ++ int ret=0; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ down(&priv->wx_sem); ++#if 1 ++ ret = ieee80211_wx_set_gen_ie(priv->ieee80211, extra, data->data.length); ++#endif ++ up(&priv->wx_sem); ++ //printk("<======%s(), ret:%d\n", __FUNCTION__, ret); ++#endif ++ return ret; ++ ++ ++} ++ ++static int dummy(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu,char *b) ++{ ++ return -1; ++} ++ ++ ++static iw_handler r8192_wx_handlers[] = ++{ ++ NULL, /* SIOCSIWCOMMIT */ ++ r8192_wx_get_name, /* SIOCGIWNAME */ ++ dummy, /* SIOCSIWNWID */ ++ dummy, /* SIOCGIWNWID */ ++ r8192_wx_set_freq, /* SIOCSIWFREQ */ ++ r8192_wx_get_freq, /* SIOCGIWFREQ */ ++ r8192_wx_set_mode, /* SIOCSIWMODE */ ++ r8192_wx_get_mode, /* SIOCGIWMODE */ ++ r8192_wx_set_sens, /* SIOCSIWSENS */ ++ r8192_wx_get_sens, /* SIOCGIWSENS */ ++ NULL, /* SIOCSIWRANGE */ ++ rtl8180_wx_get_range, /* SIOCGIWRANGE */ ++ NULL, /* SIOCSIWPRIV */ ++ NULL, /* SIOCGIWPRIV */ ++ NULL, /* SIOCSIWSTATS */ ++ NULL, /* SIOCGIWSTATS */ ++ dummy, /* SIOCSIWSPY */ ++ dummy, /* SIOCGIWSPY */ ++ NULL, /* SIOCGIWTHRSPY */ ++ NULL, /* SIOCWIWTHRSPY */ ++ r8192_wx_set_wap, /* SIOCSIWAP */ ++ r8192_wx_get_wap, /* SIOCGIWAP */ ++#if (WIRELESS_EXT >= 18) ++ r8192_wx_set_mlme, /* MLME-- */ ++#else ++ NULL, ++#endif ++ dummy, /* SIOCGIWAPLIST -- depricated */ ++ r8192_wx_set_scan, /* SIOCSIWSCAN */ ++ r8192_wx_get_scan, /* SIOCGIWSCAN */ ++ r8192_wx_set_essid, /* SIOCSIWESSID */ ++ r8192_wx_get_essid, /* SIOCGIWESSID */ ++ dummy, /* SIOCSIWNICKN */ ++ dummy, /* SIOCGIWNICKN */ ++ NULL, /* -- hole -- */ ++ NULL, /* -- hole -- */ ++ r8192_wx_set_rate, /* SIOCSIWRATE */ ++ r8192_wx_get_rate, /* SIOCGIWRATE */ ++ r8192_wx_set_rts, /* SIOCSIWRTS */ ++ r8192_wx_get_rts, /* SIOCGIWRTS */ ++ r8192_wx_set_frag, /* SIOCSIWFRAG */ ++ r8192_wx_get_frag, /* SIOCGIWFRAG */ ++ dummy, /* SIOCSIWTXPOW */ ++ dummy, /* SIOCGIWTXPOW */ ++ r8192_wx_set_retry, /* SIOCSIWRETRY */ ++ r8192_wx_get_retry, /* SIOCGIWRETRY */ ++ r8192_wx_set_enc, /* SIOCSIWENCODE */ ++ r8192_wx_get_enc, /* SIOCGIWENCODE */ ++ r8192_wx_set_power, /* SIOCSIWPOWER */ ++ r8192_wx_get_power, /* SIOCGIWPOWER */ ++ NULL, /*---hole---*/ ++ NULL, /*---hole---*/ ++ r8192_wx_set_gen_ie,//NULL, /* SIOCSIWGENIE */ ++ NULL, /* SIOCSIWGENIE */ ++#if (WIRELESS_EXT >= 18) ++ r8192_wx_set_auth,//NULL, /* SIOCSIWAUTH */ ++ NULL,//r8192_wx_get_auth,//NULL, /* SIOCSIWAUTH */ ++ r8192_wx_set_enc_ext, /* SIOCSIWENCODEEXT */ ++#else ++ NULL, ++ NULL, ++ NULL, ++#endif ++ NULL,//r8192_wx_get_enc_ext,//NULL, /* SIOCSIWENCODEEXT */ ++ NULL, /* SIOCSIWPMKSA */ ++ NULL, /*---hole---*/ ++ ++}; ++ ++ ++static const struct iw_priv_args r8192_private_args[] = { ++ ++ { ++ SIOCIWFIRSTPRIV + 0x0, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "badcrc" ++ }, ++ ++ { ++ SIOCIWFIRSTPRIV + 0x1, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "activescan" ++ ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x2, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "rawtx" ++ } ++#ifdef JOHN_IOCTL ++ , ++ { ++ SIOCIWFIRSTPRIV + 0x3, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "readRF" ++ } ++ , ++ { ++ SIOCIWFIRSTPRIV + 0x4, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "writeRF" ++ } ++ , ++ { ++ SIOCIWFIRSTPRIV + 0x5, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "readBB" ++ } ++ , ++ { ++ SIOCIWFIRSTPRIV + 0x6, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "writeBB" ++ } ++ , ++ { ++ SIOCIWFIRSTPRIV + 0x7, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "readnicb" ++ } ++ , ++ { ++ SIOCIWFIRSTPRIV + 0x8, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "writenicb" ++ } ++ , ++ { ++ SIOCIWFIRSTPRIV + 0x9, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "apinfo" ++ } ++ ++#endif ++ , ++ { ++ SIOCIWFIRSTPRIV + 0x3, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "forcereset" ++ ++ } ++ ++}; ++ ++ ++static iw_handler r8192_private_handler[] = { ++// r8192_wx_set_monitor, /* SIOCIWFIRSTPRIV */ ++ r8192_wx_set_crcmon, /*SIOCIWSECONDPRIV*/ ++// r8192_wx_set_forceassociate, ++// r8192_wx_set_beaconinterval, ++// r8192_wx_set_monitor_type, ++ r8192_wx_set_scan_type, ++ r8192_wx_set_rawtx, ++#ifdef JOHN_IOCTL ++ r8192_wx_read_regs, ++ r8192_wx_write_regs, ++ r8192_wx_read_bb, ++ r8192_wx_write_bb, ++ r8192_wx_read_nicb, ++ r8192_wx_write_nicb, ++ r8192_wx_get_ap_status ++#endif ++ r8192_wx_force_reset, ++}; ++ ++//#if WIRELESS_EXT >= 17 ++struct iw_statistics *r8192_get_wireless_stats(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ struct ieee80211_device* ieee = priv->ieee80211; ++ struct iw_statistics* wstats = &priv->wstats; ++ int tmp_level = 0; ++ int tmp_qual = 0; ++ int tmp_noise = 0; ++ if(ieee->state < IEEE80211_LINKED) ++ { ++ wstats->qual.qual = 0; ++ wstats->qual.level = 0; ++ wstats->qual.noise = 0; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14)) ++ wstats->qual.updated = IW_QUAL_ALL_UPDATED | IW_QUAL_DBM; ++#else ++ wstats->qual.updated = 0x0f; ++#endif ++ return wstats; ++ } ++ ++ tmp_level = (&ieee->current_network)->stats.rssi; ++ tmp_qual = (&ieee->current_network)->stats.signal; ++ tmp_noise = (&ieee->current_network)->stats.noise; ++ //printk("level:%d, qual:%d, noise:%d\n", tmp_level, tmp_qual, tmp_noise); ++ ++ wstats->qual.level = tmp_level; ++ wstats->qual.qual = tmp_qual; ++ wstats->qual.noise = tmp_noise; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14)) ++ wstats->qual.updated = IW_QUAL_ALL_UPDATED | IW_QUAL_DBM; ++#else ++ wstats->qual.updated = 0x0f; ++#endif ++ return wstats; ++} ++//#endif ++ ++ ++struct iw_handler_def r8192_wx_handlers_def={ ++ .standard = r8192_wx_handlers, ++ .num_standard = sizeof(r8192_wx_handlers) / sizeof(iw_handler), ++ .private = r8192_private_handler, ++ .num_private = sizeof(r8192_private_handler) / sizeof(iw_handler), ++ .num_private_args = sizeof(r8192_private_args) / sizeof(struct iw_priv_args), ++#if WIRELESS_EXT >= 17 ++ .get_wireless_stats = r8192_get_wireless_stats, ++#endif ++ .private_args = (struct iw_priv_args *)r8192_private_args, ++}; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r8192E_wx.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E_wx.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192E_wx.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,22 @@ ++/* ++ This is part of rtl8180 OpenSource driver - v 0.3 ++ Copyright (C) Andrea Merello 2004 ++ Released under the terms of GPL (General Public Licence) ++ ++ Parts of this driver are based on the GPL part of the official realtek driver ++ Parts of this driver are based on the rtl8180 driver skeleton from Patric Schenke & Andres Salomon ++ Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver ++ ++ We want to tanks the Authors of such projects and the Ndiswrapper project Authors. ++*/ ++ ++/* this file (will) contains wireless extension handlers*/ ++ ++#ifndef R8180_WX_H ++#define R8180_WX_H ++//#include ++//#include "ieee80211.h" ++extern struct iw_handler_def r8192_wx_handlers_def; ++/* Enable the rtl819x_core.c to share this function, david 2008.9.22 */ ++extern struct iw_statistics *r8192_get_wireless_stats(struct net_device *dev); ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r8192_pm.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192_pm.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192_pm.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,181 @@ ++/* ++ Power management interface routines. ++ Written by Mariusz Matuszek. ++ This code is currently just a placeholder for later work and ++ does not do anything useful. ++ ++ This is part of rtl8180 OpenSource driver. ++ Copyright (C) Andrea Merello 2004 ++ Released under the terms of GPL (General Public Licence) ++*/ ++ ++#ifdef CONFIG_PM_RTL ++ ++#include "r8192E.h" ++#include "r8192E_hw.h" ++#include "r8192_pm.h" ++#include "r8190_rtl8256.h" ++ ++int rtl8192E_save_state (struct pci_dev *dev, pm_message_t state) ++{ ++ printk(KERN_NOTICE "r8192E save state call (state %u).\n", state.event); ++ return(-EAGAIN); ++} ++ ++ ++int rtl8192E_suspend (struct pci_dev *pdev, pm_message_t state) ++{ ++ struct net_device *dev = pci_get_drvdata(pdev); ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 ucRegRead; ++ u32 ulRegRead; ++ ++ RT_TRACE(COMP_POWER, "============> r8192E suspend call.\n"); ++ if (!netif_running(dev)) ++ goto out_pci_suspend; ++ ++ dev->stop(dev); ++#if 0 ++ ++ netif_carrier_off(dev); ++ ++ ieee80211_softmac_stop_protocol(priv->ieee80211); ++ ++ write_nic_byte(dev,MSR,(read_nic_byte(dev,MSR)&0xfc)|MSR_LINK_NONE); ++ if(!priv->ieee80211->bSupportRemoteWakeUp) { ++ /* disable tx/rx. In 8185 we write 0x10 (Reset bit), ++ * but here we make reference to WMAC and wirte 0x0. ++ * 2006.11.21 Emily ++ */ ++ write_nic_byte(dev, CMDR, 0); ++ } ++ //disable interrupt ++ write_nic_dword(dev,INTA_MASK,0); ++ priv->irq_enabled = 0; ++ write_nic_dword(dev,ISR,read_nic_dword(dev, ISR)); ++ ++ /* need to free DM related functions */ ++#if LINUX_VERSION_CODE >=KERNEL_VERSION(2,6,20) ++ cancel_work_sync(&priv->reset_wq); ++#else ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ cancel_delayed_work(&priv->reset_wq); ++#endif ++#endif ++ del_timer_sync(&priv->fsync_timer); ++ del_timer_sync(&priv->watch_dog_timer); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ cancel_delayed_work(&priv->watch_dog_wq); ++ cancel_delayed_work(&priv->update_beacon_wq); ++#endif ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ cancel_work_sync(&priv->qos_activate); ++#else ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ cancel_delayed_work(&priv->qos_activate); ++#endif ++#endif ++ ++ /* TODO ++#if ((DEV_BUS_TYPE == PCI_INTERFACE) && (HAL_CODE_BASE == RTL8192)) ++pHalData->bHwRfOffAction = 2; ++#endif ++*/ ++#endif ++ // Call MgntActSet_RF_State instead to prevent RF config race condition. ++ // By Bruce, 2008-01-17. ++ // ++ if(!priv->ieee80211->bSupportRemoteWakeUp) { ++ MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT); ++ // 2006.11.30. System reset bit ++ ulRegRead = read_nic_dword(dev, CPU_GEN); ++ ulRegRead|=CPU_GEN_SYSTEM_RESET; ++ write_nic_dword(dev, CPU_GEN, ulRegRead); ++ } else { ++ //2008.06.03 for WOL ++ write_nic_dword(dev, WFCRC0, 0xffffffff); ++ write_nic_dword(dev, WFCRC1, 0xffffffff); ++ write_nic_dword(dev, WFCRC2, 0xffffffff); ++#ifdef RTL8190P ++ //GPIO 0 = TRUE ++ ucRegRead = read_nic_byte(dev, GPO); ++ ucRegRead |= BIT0; ++ write_nic_byte(dev, GPO, ucRegRead); ++#endif ++ //Write PMR register ++ write_nic_byte(dev, PMR, 0x5); ++ //Disable tx, enanble rx ++ write_nic_byte(dev, MacBlkCtrl, 0xa); ++ } ++ ++out_pci_suspend: ++ RT_TRACE(COMP_POWER, "r8192E support WOL call??????????????????????\n"); ++ if(priv->ieee80211->bSupportRemoteWakeUp) { ++ RT_TRACE(COMP_POWER, "r8192E support WOL call!!!!!!!!!!!!!!!!!!.\n"); ++ } ++ netif_device_detach(dev); ++ pci_save_state(pdev); ++ pci_disable_device(pdev); ++ pci_enable_wake(pdev, pci_choose_state(pdev,state),\ ++ priv->ieee80211->bSupportRemoteWakeUp?1:0); ++ pci_set_power_state(pdev,pci_choose_state(pdev,state)); ++ ++ return 0; ++} ++ ++int rtl8192E_resume (struct pci_dev *pdev) ++{ ++ struct net_device *dev = pci_get_drvdata(pdev); ++ //struct r8192_priv *priv = ieee80211_priv(dev); ++ //union iwreq_data wrqu; ++ int err; ++ u32 val; ++ ++ RT_TRACE(COMP_POWER, "================>r8192E resume call."); ++ ++ pci_set_power_state(pdev, PCI_D0); ++ ++ err = pci_enable_device(pdev); ++ if(err) { ++ printk(KERN_ERR "%s: pci_enable_device failed on resume\n", ++ dev->name); ++ return err; ++ } ++ ++ pci_restore_state(pdev); ++ ++ /* ++ * Suspend/Resume resets the PCI configuration space, so we have to ++ * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries ++ * from interfering with C3 CPU state. pci_restore_state won't help ++ * here since it only restores the first 64 bytes pci config header. ++ */ ++ pci_read_config_dword(pdev, 0x40, &val); ++ if ((val & 0x0000ff00) != 0) { ++ pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); ++ } ++ ++ ++ ++ pci_enable_wake(pdev, PCI_D0, 0); ++ ++ if(!netif_running(dev)) ++ goto out; ++ ++ netif_device_attach(dev); ++ ++ dev->open(dev); ++out: ++ RT_TRACE(COMP_POWER, "<================r8192E resume call.\n"); ++ return 0; ++} ++ ++ ++int rtl8192E_enable_wake (struct pci_dev *dev, pm_message_t state, int enable) ++{ ++ printk(KERN_NOTICE "r8192E enable wake call (state %u, enable %d).\n", ++ state.event, enable); ++ return(-EAGAIN); ++} ++ ++#endif //CONFIG_PM_RTL +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r8192_pm.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192_pm.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r8192_pm.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,28 @@ ++/* ++ Power management interface routines. ++ Written by Mariusz Matuszek. ++ This code is currently just a placeholder for later work and ++ does not do anything useful. ++ ++ This is part of rtl8180 OpenSource driver. ++ Copyright (C) Andrea Merello 2004 ++ Released under the terms of GPL (General Public Licence) ++ ++*/ ++ ++#ifdef CONFIG_PM_RTL ++ ++#ifndef R8192E_PM_H ++#define R8192E_PM_H ++ ++#include ++#include ++ ++int rtl8192E_save_state (struct pci_dev *dev, pm_message_t state); ++int rtl8192E_suspend (struct pci_dev *dev, pm_message_t state); ++int rtl8192E_resume (struct pci_dev *dev); ++int rtl8192E_enable_wake (struct pci_dev *dev, pm_message_t state, int enable); ++ ++#endif //R8192E_PM_H ++ ++#endif // CONFIG_PM_RTL +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r819xE_cmdpkt.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_cmdpkt.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_cmdpkt.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,820 @@ ++/****************************************************************************** ++ ++ (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved. ++ ++ Module: r819xusb_cmdpkt.c (RTL8190 TX/RX command packet handler Source C File) ++ ++ Note: The module is responsible for handling TX and RX command packet. ++ 1. TX : Send set and query configuration command packet. ++ 2. RX : Receive tx feedback, beacon state, query configuration ++ command packet. ++ ++ Function: ++ ++ Export: ++ ++ Abbrev: ++ ++ History: ++ Data Who Remark ++ ++ 05/06/2008 amy Create initial version porting from windows driver. ++ ++******************************************************************************/ ++#include "r8192E.h" ++#include "r8192E_hw.h" ++#include "r819xE_cmdpkt.h" ++/*---------------------------Define Local Constant---------------------------*/ ++/* Debug constant*/ ++#define CMPK_DEBOUNCE_CNT 1 ++/* 2007/10/24 MH Add for printing a range of data. */ ++#define CMPK_PRINT(Address)\ ++{\ ++ unsigned char i;\ ++ u32 temp[10];\ ++ \ ++ memcpy(temp, Address, 40);\ ++ for (i = 0; i <40; i+=4)\ ++ printk("\r\n %08x", temp[i]);\ ++}\ ++ ++/*---------------------------Define functions---------------------------------*/ ++/*----------------------------------------------------------------------------- ++ * Function: cmpk_message_handle_tx() ++ * ++ * Overview: Driver internal module can call the API to send message to ++ * firmware side. For example, you can send a debug command packet. ++ * Or you can send a request for FW to modify RLX4181 LBUS HW bank. ++ * Otherwise, you can change MAC/PHT/RF register by firmware at ++ * run time. We do not support message more than one segment now. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/06/2008 amy porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++RT_STATUS cmpk_message_handle_tx( ++ struct net_device *dev, ++ u8* code_virtual_address, ++ u32 packettype, ++ u32 buffer_len) ++{ ++ ++ RT_STATUS rt_status = RT_STATUS_SUCCESS; ++#ifdef RTL8192U ++ return rt_status; ++#else ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u16 frag_threshold; ++ u16 frag_length = 0, frag_offset = 0; ++ rt_firmware *pfirmware = priv->pFirmware; ++ struct sk_buff *skb; ++ unsigned char *seg_ptr; ++ cb_desc *tcb_desc; ++ u8 bLastIniPkt; ++ ++ PTX_FWINFO_8190PCI pTxFwInfo = NULL; ++ int i; ++ ++ //spin_lock_irqsave(&priv->tx_lock,flags); ++ RT_TRACE(COMP_CMDPKT,"%s(),buffer_len is %d\n",__FUNCTION__,buffer_len); ++ firmware_init_param(dev); ++ //Fragmentation might be required ++ frag_threshold = pfirmware->cmdpacket_frag_thresold; ++ do { ++ if((buffer_len - frag_offset) > frag_threshold) { ++ frag_length = frag_threshold ; ++ bLastIniPkt = 0; ++ ++ } else { ++ frag_length =(u16)(buffer_len - frag_offset); ++ bLastIniPkt = 1; ++ ++ } ++ ++ /* Allocate skb buffer to contain firmware info and tx descriptor info ++ * add 4 to avoid packet appending overflow. ++ * */ ++#ifdef RTL8192U ++ skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + frag_length + 4); ++#else ++ skb = dev_alloc_skb(frag_length + priv->ieee80211->tx_headroom + 4); ++#endif ++ if(skb == NULL) { ++ rt_status = RT_STATUS_FAILURE; ++ goto Failed; ++ } ++ ++ memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); ++ tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE); ++ tcb_desc->queue_index = TXCMD_QUEUE; ++ tcb_desc->bCmdOrInit = packettype; ++ tcb_desc->bLastIniPkt = bLastIniPkt; ++ tcb_desc->pkt_size = frag_length; ++ ++#ifdef RTL8192U ++ skb_reserve(skb, USB_HWDESC_HEADER_LEN); ++#endif ++ ++ //seg_ptr = skb_put(skb, frag_length + priv->ieee80211->tx_headroom); ++ seg_ptr = skb_put(skb, priv->ieee80211->tx_headroom); ++ ++ pTxFwInfo = (PTX_FWINFO_8190PCI)seg_ptr; ++ memset(pTxFwInfo,0,sizeof(TX_FWINFO_8190PCI)); ++ memset(pTxFwInfo,0x12,8); ++ ++ seg_ptr +=sizeof(TX_FWINFO_8190PCI); ++ ++ /* ++ * Transform from little endian to big endian ++ * and pending zero ++ */ ++ seg_ptr = skb->tail; ++ for(i=0 ; i < frag_length; i+=4) { ++ *seg_ptr++ = ((i+0)ieee80211->softmac_hard_start_xmit(skb,dev); ++ ++ code_virtual_address += frag_length; ++ frag_offset += frag_length; ++ ++#if 0 ++ { ++ int k; ++ printk("------------tx cmd------------\n"); ++ for(k = 0; ktx_lock,flags); ++ return rt_status; ++ ++ ++#endif ++} /* CMPK_Message_Handle_Tx */ ++ ++/*----------------------------------------------------------------------------- ++ * Function: cmpk_counttxstatistic() ++ * ++ * Overview: ++ * ++ * Input: PADAPTER pAdapter - . ++ * CMPK_TXFB_T *psTx_FB - . ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/12/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++static void ++cmpk_count_txstatistic( ++ struct net_device *dev, ++ cmpk_txfb_t *pstx_fb) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#ifdef ENABLE_PS ++ RT_RF_POWER_STATE rtState; ++ ++ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); ++ ++ // When RF is off, we should not count the packet for hw/sw synchronize ++ // reason, ie. there may be a duration while sw switch is changed and hw ++ // switch is being changed. 2006.12.04, by shien chang. ++ if (rtState == eRfOff) ++ { ++ return; ++ } ++#endif ++ ++#ifdef TODO ++ if(pAdapter->bInHctTest) ++ return; ++#endif ++ /* We can not know the packet length and transmit type: broadcast or uni ++ or multicast. So the relative statistics must be collected in tx ++ feedback info. */ ++ if (pstx_fb->tok) ++ { ++ priv->stats.txfeedbackok++; ++ priv->stats.txoktotal++; ++ priv->stats.txokbytestotal += pstx_fb->pkt_length; ++ priv->stats.txokinperiod++; ++ ++ /* We can not make sure broadcast/multicast or unicast mode. */ ++ if (pstx_fb->pkt_type == PACKET_MULTICAST) ++ { ++ priv->stats.txmulticast++; ++ priv->stats.txbytesmulticast += pstx_fb->pkt_length; ++ } ++ else if (pstx_fb->pkt_type == PACKET_BROADCAST) ++ { ++ priv->stats.txbroadcast++; ++ priv->stats.txbytesbroadcast += pstx_fb->pkt_length; ++ } ++ else ++ { ++ priv->stats.txunicast++; ++ priv->stats.txbytesunicast += pstx_fb->pkt_length; ++ } ++ } ++ else ++ { ++ priv->stats.txfeedbackfail++; ++ priv->stats.txerrtotal++; ++ priv->stats.txerrbytestotal += pstx_fb->pkt_length; ++ ++ /* We can not make sure broadcast/multicast or unicast mode. */ ++ if (pstx_fb->pkt_type == PACKET_MULTICAST) ++ { ++ priv->stats.txerrmulticast++; ++ } ++ else if (pstx_fb->pkt_type == PACKET_BROADCAST) ++ { ++ priv->stats.txerrbroadcast++; ++ } ++ else ++ { ++ priv->stats.txerrunicast++; ++ } ++ } ++ ++ priv->stats.txretrycount += pstx_fb->retry_cnt; ++ priv->stats.txfeedbackretry += pstx_fb->retry_cnt; ++ ++} /* cmpk_CountTxStatistic */ ++ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: cmpk_handle_tx_feedback() ++ * ++ * Overview: The function is responsible for extract the message inside TX ++ * feedbck message from firmware. It will contain dedicated info in ++ * ws-06-0063-rtl8190-command-packet-specification. Please ++ * refer to chapter "TX Feedback Element". We have to read 20 bytes ++ * in the command packet. ++ * ++ * Input: struct net_device * dev ++ * u8 * pmsg - Msg Ptr of the command packet. ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/08/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++static void ++cmpk_handle_tx_feedback( ++ struct net_device *dev, ++ u8 * pmsg) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ cmpk_txfb_t rx_tx_fb; /* */ ++ ++ priv->stats.txfeedback++; ++ ++ /* 0. Display received message. */ ++ //cmpk_Display_Message(CMPK_RX_TX_FB_SIZE, pMsg); ++ ++ /* 1. Extract TX feedback info from RFD to temp structure buffer. */ ++ /* It seems that FW use big endian(MIPS) and DRV use little endian in ++ windows OS. So we have to read the content byte by byte or transfer ++ endian type before copy the message copy. */ ++#if 0 // The TX FEEDBACK packet element address ++ //rx_tx_fb.Element_ID = pMsg[0]; ++ //rx_tx_fb.Length = pMsg[1]; ++ rx_tx_fb.TOK = pMsg[2]>>7; ++ rx_tx_fb.Fail_Reason = (pMsg[2] & 0x70) >> 4; ++ rx_tx_fb.TID = (pMsg[2] & 0x0F); ++ rx_tx_fb.Qos_Pkt = pMsg[3] >> 7; ++ rx_tx_fb.Bandwidth = (pMsg[3] & 0x40) >> 6; ++ rx_tx_fb.Retry_Cnt = pMsg[5]; ++ rx_tx_fb.Pkt_ID = (pMsg[6] << 8) | pMsg[7]; ++ rx_tx_fb.Seq_Num = (pMsg[8] << 8) | pMsg[9]; ++ rx_tx_fb.S_Rate = pMsg[10]; ++ rx_tx_fb.F_Rate = pMsg[11]; ++ rx_tx_fb.S_RTS_Rate = pMsg[12]; ++ rx_tx_fb.F_RTS_Rate = pMsg[13]; ++ rx_tx_fb.pkt_length = (pMsg[14] << 8) | pMsg[15]; ++#endif ++ /* 2007/07/05 MH Use pointer to transfer structure memory. */ ++ //memcpy((UINT8 *)&rx_tx_fb, pMsg, sizeof(CMPK_TXFB_T)); ++ memcpy((u8*)&rx_tx_fb, pmsg, sizeof(cmpk_txfb_t)); ++ /* 2. Use tx feedback info to count TX statistics. */ ++ cmpk_count_txstatistic(dev, &rx_tx_fb); ++#if 0 ++ /* 2007/07/11 MH Assign current operate rate. */ ++ if (pAdapter->RegWirelessMode == WIRELESS_MODE_A || ++ pAdapter->RegWirelessMode == WIRELESS_MODE_B || ++ pAdapter->RegWirelessMode == WIRELESS_MODE_G) ++ { ++ pMgntInfo->CurrentOperaRate = (rx_tx_fb.F_Rate & 0x7F); ++ } ++ else if (pAdapter->RegWirelessMode == WIRELESS_MODE_N_24G || ++ pAdapter->RegWirelessMode == WIRELESS_MODE_N_5G) ++ { ++ pMgntInfo->HTCurrentOperaRate = (rx_tx_fb.F_Rate & 0x8F); ++ } ++#endif ++ /* 2007/01/17 MH Comment previous method for TX statistic function. */ ++ /* Collect info TX feedback packet to fill TCB. */ ++ /* We can not know the packet length and transmit type: broadcast or uni ++ or multicast. */ ++ //CountTxStatistics( pAdapter, &tcb ); ++ ++} /* cmpk_Handle_Tx_Feedback */ ++ ++static void cmdpkt_beacontimerinterrupt_819xusb(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u16 tx_rate; ++ { ++ // ++ // 070117, rcnjko: 87B have to S/W beacon for DTM encryption_cmn. ++ // ++ if((priv->ieee80211->current_network.mode == IEEE_A) || ++ (priv->ieee80211->current_network.mode == IEEE_N_5G) || ++ ((priv->ieee80211->current_network.mode == IEEE_N_24G) && (!priv->ieee80211->pHTInfo->bCurSuppCCK))) ++ { ++ tx_rate = 60; ++ DMESG("send beacon frame tx rate is 6Mbpm\n"); ++ } ++ else ++ { ++ tx_rate =10; ++ DMESG("send beacon frame tx rate is 1Mbpm\n"); ++ } ++ ++ //rtl819xusb_beacon_tx(dev,tx_rate); // HW Beacon ++ ++ } ++ ++} ++ ++ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: cmpk_handle_interrupt_status() ++ * ++ * Overview: The function is responsible for extract the message from ++ * firmware. It will contain dedicated info in ++ * ws-07-0063-v06-rtl819x-command-packet-specification-070315.doc. ++ * Please refer to chapter "Interrupt Status Element". ++ * ++ * Input: struct net_device *dev, ++ * u8* pmsg - Message Pointer of the command packet. ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/12/2008 amy Add this for rtl8192 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++static void ++cmpk_handle_interrupt_status( ++ struct net_device *dev, ++ u8* pmsg) ++{ ++ cmpk_intr_sta_t rx_intr_status; /* */ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ DMESG("---> cmpk_Handle_Interrupt_Status()\n"); ++ ++ /* 0. Display received message. */ ++ //cmpk_Display_Message(CMPK_RX_BEACON_STATE_SIZE, pMsg); ++ ++ /* 1. Extract TX feedback info from RFD to temp structure buffer. */ ++ /* It seems that FW use big endian(MIPS) and DRV use little endian in ++ windows OS. So we have to read the content byte by byte or transfer ++ endian type before copy the message copy. */ ++ //rx_bcn_state.Element_ID = pMsg[0]; ++ //rx_bcn_state.Length = pMsg[1]; ++ rx_intr_status.length = pmsg[1]; ++ if (rx_intr_status.length != (sizeof(cmpk_intr_sta_t) - 2)) ++ { ++ DMESG("cmpk_Handle_Interrupt_Status: wrong length!\n"); ++ return; ++ } ++ ++ ++ // Statistics of beacon for ad-hoc mode. ++ if( priv->ieee80211->iw_mode == IW_MODE_ADHOC) ++ { ++ //2 maybe need endian transform? ++ rx_intr_status.interrupt_status = *((u32 *)(pmsg + 4)); ++ //rx_intr_status.InterruptStatus = N2H4BYTE(*((UINT32 *)(pMsg + 4))); ++ ++ DMESG("interrupt status = 0x%x\n", rx_intr_status.interrupt_status); ++ ++ if (rx_intr_status.interrupt_status & ISR_TxBcnOk) ++ { ++ priv->ieee80211->bibsscoordinator = true; ++ priv->stats.txbeaconokint++; ++ } ++ else if (rx_intr_status.interrupt_status & ISR_TxBcnErr) ++ { ++ priv->ieee80211->bibsscoordinator = false; ++ priv->stats.txbeaconerr++; ++ } ++ ++ if (rx_intr_status.interrupt_status & ISR_BcnTimerIntr) ++ { ++ cmdpkt_beacontimerinterrupt_819xusb(dev); ++ } ++ ++ } ++ ++ // Other informations in interrupt status we need? ++ ++ ++ DMESG("<---- cmpk_handle_interrupt_status()\n"); ++ ++} /* cmpk_handle_interrupt_status */ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: cmpk_handle_query_config_rx() ++ * ++ * Overview: The function is responsible for extract the message from ++ * firmware. It will contain dedicated info in ++ * ws-06-0063-rtl8190-command-packet-specification. Please ++ * refer to chapter "Beacon State Element". ++ * ++ * Input: u8 * pmsg - Message Pointer of the command packet. ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/12/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++static void ++cmpk_handle_query_config_rx( ++ struct net_device *dev, ++ u8* pmsg) ++{ ++ cmpk_query_cfg_t rx_query_cfg; /* */ ++ ++ /* 0. Display received message. */ ++ //cmpk_Display_Message(CMPK_RX_BEACON_STATE_SIZE, pMsg); ++ ++ /* 1. Extract TX feedback info from RFD to temp structure buffer. */ ++ /* It seems that FW use big endian(MIPS) and DRV use little endian in ++ windows OS. So we have to read the content byte by byte or transfer ++ endian type before copy the message copy. */ ++ //rx_query_cfg.Element_ID = pMsg[0]; ++ //rx_query_cfg.Length = pMsg[1]; ++ rx_query_cfg.cfg_action = (pmsg[4] & 0x80000000)>>31; ++ rx_query_cfg.cfg_type = (pmsg[4] & 0x60) >> 5; ++ rx_query_cfg.cfg_size = (pmsg[4] & 0x18) >> 3; ++ rx_query_cfg.cfg_page = (pmsg[6] & 0x0F) >> 0; ++ rx_query_cfg.cfg_offset = pmsg[7]; ++ rx_query_cfg.value = (pmsg[8] << 24) | (pmsg[9] << 16) | ++ (pmsg[10] << 8) | (pmsg[11] << 0); ++ rx_query_cfg.mask = (pmsg[12] << 24) | (pmsg[13] << 16) | ++ (pmsg[14] << 8) | (pmsg[15] << 0); ++ ++} /* cmpk_Handle_Query_Config_Rx */ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: cmpk_count_tx_status() ++ * ++ * Overview: Count aggregated tx status from firmwar of one type rx command ++ * packet element id = RX_TX_STATUS. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/12/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++static void cmpk_count_tx_status( struct net_device *dev, ++ cmpk_tx_status_t *pstx_status) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++#ifdef ENABLE_PS ++ ++ RT_RF_POWER_STATE rtstate; ++ ++ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); ++ ++ // When RF is off, we should not count the packet for hw/sw synchronize ++ // reason, ie. there may be a duration while sw switch is changed and hw ++ // switch is being changed. 2006.12.04, by shien chang. ++ if (rtState == eRfOff) ++ { ++ return; ++ } ++#endif ++ ++ priv->stats.txfeedbackok += pstx_status->txok; ++ priv->stats.txoktotal += pstx_status->txok; ++ ++ priv->stats.txfeedbackfail += pstx_status->txfail; ++ priv->stats.txerrtotal += pstx_status->txfail; ++ ++ priv->stats.txretrycount += pstx_status->txretry; ++ priv->stats.txfeedbackretry += pstx_status->txretry; ++ ++ //pAdapter->TxStats.NumTxOkBytesTotal += psTx_FB->pkt_length; ++ //pAdapter->TxStats.NumTxErrBytesTotal += psTx_FB->pkt_length; ++ //pAdapter->MgntInfo.LinkDetectInfo.NumTxOkInPeriod++; ++ ++ priv->stats.txmulticast += pstx_status->txmcok; ++ priv->stats.txbroadcast += pstx_status->txbcok; ++ priv->stats.txunicast += pstx_status->txucok; ++ ++ priv->stats.txerrmulticast += pstx_status->txmcfail; ++ priv->stats.txerrbroadcast += pstx_status->txbcfail; ++ priv->stats.txerrunicast += pstx_status->txucfail; ++ ++ priv->stats.txbytesmulticast += pstx_status->txmclength; ++ priv->stats.txbytesbroadcast += pstx_status->txbclength; ++ priv->stats.txbytesunicast += pstx_status->txuclength; ++ ++ priv->stats.last_packet_rate = pstx_status->rate; ++} /* cmpk_CountTxStatus */ ++ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: cmpk_handle_tx_status() ++ * ++ * Overview: Firmware add a new tx feedback status to reduce rx command ++ * packet buffer operation load. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/12/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++static void ++cmpk_handle_tx_status( ++ struct net_device *dev, ++ u8* pmsg) ++{ ++ cmpk_tx_status_t rx_tx_sts; /* */ ++ ++ memcpy((void*)&rx_tx_sts, (void*)pmsg, sizeof(cmpk_tx_status_t)); ++ /* 2. Use tx feedback info to count TX statistics. */ ++ cmpk_count_tx_status(dev, &rx_tx_sts); ++ ++} /* cmpk_Handle_Tx_Status */ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: cmpk_handle_tx_rate_history() ++ * ++ * Overview: Firmware add a new tx rate history ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/12/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++static void ++cmpk_handle_tx_rate_history( ++ struct net_device *dev, ++ u8* pmsg) ++{ ++ cmpk_tx_rahis_t *ptxrate; ++// RT_RF_POWER_STATE rtState; ++ u8 i, j; ++ u16 length = sizeof(cmpk_tx_rahis_t); ++ u32 *ptemp; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ ++#ifdef ENABLE_PS ++ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); ++ ++ // When RF is off, we should not count the packet for hw/sw synchronize ++ // reason, ie. there may be a duration while sw switch is changed and hw ++ // switch is being changed. 2006.12.04, by shien chang. ++ if (rtState == eRfOff) ++ { ++ return; ++ } ++#endif ++ ++ ptemp = (u32 *)pmsg; ++ ++ // ++ // Do endian transfer to word alignment(16 bits) for windows system. ++ // You must do different endian transfer for linux and MAC OS ++ // ++ for (i = 0; i < (length/4); i++) ++ { ++ u16 temp1, temp2; ++ ++ temp1 = ptemp[i]&0x0000FFFF; ++ temp2 = ptemp[i]>>16; ++ ptemp[i] = (temp1<<16)|temp2; ++ } ++ ++ ptxrate = (cmpk_tx_rahis_t *)pmsg; ++ ++ if (ptxrate == NULL ) ++ { ++ return; ++ } ++ ++ for (i = 0; i < 16; i++) ++ { ++ // Collect CCK rate packet num ++ if (i < 4) ++ priv->stats.txrate.cck[i] += ptxrate->cck[i]; ++ ++ // Collect OFDM rate packet num ++ if (i< 8) ++ priv->stats.txrate.ofdm[i] += ptxrate->ofdm[i]; ++ ++ for (j = 0; j < 4; j++) ++ priv->stats.txrate.ht_mcs[j][i] += ptxrate->ht_mcs[j][i]; ++ } ++ ++} /* cmpk_Handle_Tx_Rate_History */ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: cmpk_message_handle_rx() ++ * ++ * Overview: In the function, we will capture different RX command packet ++ * info. Every RX command packet element has different message ++ * length and meaning in content. We only support three type of RX ++ * command packet now. Please refer to document ++ * ws-06-0063-rtl8190-command-packet-specification. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/06/2008 amy Create Version 0 porting from windows code. ++ * ++ *---------------------------------------------------------------------------*/ ++u32 cmpk_message_handle_rx(struct net_device *dev, struct ieee80211_rx_stats *pstats) ++{ ++// u32 debug_level = DBG_LOUD; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ int total_length; ++ u8 cmd_length, exe_cnt = 0; ++ u8 element_id; ++ u8 *pcmd_buff; ++ ++ RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx()\n"); ++ ++ /* 0. Check inpt arguments. If is is a command queue message or pointer is ++ null. */ ++ if (/*(prfd->queue_id != CMPK_RX_QUEUE_ID) || */(pstats== NULL)) ++ { ++ /* Print error message. */ ++ /*RT_TRACE(COMP_SEND, DebugLevel, ++ ("\n\r[CMPK]-->Err queue id or pointer"));*/ ++ return 0; /* This is not a command packet. */ ++ } ++ ++ /* 1. Read received command packet message length from RFD. */ ++ total_length = pstats->Length; ++ ++ /* 2. Read virtual address from RFD. */ ++ pcmd_buff = pstats->virtual_address; ++ ++ /* 3. Read command pakcet element id and length. */ ++ element_id = pcmd_buff[0]; ++ /*RT_TRACE(COMP_SEND, DebugLevel, ++ ("\n\r[CMPK]-->element ID=%d Len=%d", element_id, total_length));*/ ++ ++ /* 4. Check every received command packet conent according to different ++ element type. Because FW may aggregate RX command packet to minimize ++ transmit time between DRV and FW.*/ ++ // Add a counter to prevent to locked in the loop too long ++ while (total_length > 0 || exe_cnt++ >100) ++ { ++ /* 2007/01/17 MH We support aggregation of different cmd in the same packet. */ ++ element_id = pcmd_buff[0]; ++ ++ switch(element_id) ++ { ++ case RX_TX_FEEDBACK: ++ ++ RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():RX_TX_FEEDBACK\n"); ++ cmpk_handle_tx_feedback (dev, pcmd_buff); ++ cmd_length = CMPK_RX_TX_FB_SIZE; ++ break; ++ ++ case RX_INTERRUPT_STATUS: ++ ++ RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():RX_INTERRUPT_STATUS\n"); ++ cmpk_handle_interrupt_status(dev, pcmd_buff); ++ cmd_length = sizeof(cmpk_intr_sta_t); ++ break; ++ ++ case BOTH_QUERY_CONFIG: ++ ++ RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():BOTH_QUERY_CONFIG\n"); ++ cmpk_handle_query_config_rx(dev, pcmd_buff); ++ cmd_length = CMPK_BOTH_QUERY_CONFIG_SIZE; ++ break; ++ ++ case RX_TX_STATUS: ++ ++ RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():RX_TX_STATUS\n"); ++ cmpk_handle_tx_status(dev, pcmd_buff); ++ cmd_length = CMPK_RX_TX_STS_SIZE; ++ break; ++ ++ case RX_TX_PER_PKT_FEEDBACK: ++ // You must at lease add a switch case element here, ++ // Otherwise, we will jump to default case. ++ //DbgPrint("CCX Test\r\n"); ++ RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():RX_TX_PER_PKT_FEEDBACK\n"); ++ cmd_length = CMPK_RX_TX_FB_SIZE; ++ break; ++ ++ case RX_TX_RATE_HISTORY: ++ //DbgPrint(" rx tx rate history\r\n"); ++ ++ RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():RX_TX_HISTORY\n"); ++ cmpk_handle_tx_rate_history(dev, pcmd_buff); ++ cmd_length = CMPK_TX_RAHIS_SIZE; ++ break; ++ ++ default: ++ ++ RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():unknow CMD Element\n"); ++ return 1; /* This is a command packet. */ ++ } ++ // 2007/01/22 MH Display received rx command packet info. ++ //cmpk_Display_Message(cmd_length, pcmd_buff); ++ ++ // 2007/01/22 MH Add to display tx statistic. ++ //cmpk_DisplayTxStatistic(pAdapter); ++ ++ /* 2007/03/09 MH Collect sidderent cmd element pkt num. */ ++ priv->stats.rxcmdpkt[element_id]++; ++ ++ total_length -= cmd_length; ++ pcmd_buff += cmd_length; ++ } /* while (total_length > 0) */ ++ return 1; /* This is a command packet. */ ++ ++ RT_TRACE(COMP_EVENTS, "<----cmpk_message_handle_rx()\n"); ++} /* CMPK_Message_Handle_Rx */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r819xE_cmdpkt.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_cmdpkt.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_cmdpkt.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,207 @@ ++#ifndef R819XUSB_CMDPKT_H ++#define R819XUSB_CMDPKT_H ++/* Different command packet have dedicated message length and definition. */ ++#define CMPK_RX_TX_FB_SIZE sizeof(cmpk_txfb_t) //20 ++#define CMPK_TX_SET_CONFIG_SIZE sizeof(cmpk_set_cfg_t) //16 ++#define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(cmpk_set_cfg_t) //16 ++#define CMPK_RX_TX_STS_SIZE sizeof(cmpk_tx_status_t)// ++#define CMPK_RX_DBG_MSG_SIZE sizeof(cmpk_rx_dbginfo_t)// ++#define CMPK_TX_RAHIS_SIZE sizeof(cmpk_tx_rahis_t) ++ ++/* 2008/05/08 amy For USB constant. */ ++#define ISR_TxBcnOk BIT27 // Transmit Beacon OK ++#define ISR_TxBcnErr BIT26 // Transmit Beacon Error ++#define ISR_BcnTimerIntr BIT13 // Beacon Timer Interrupt ++ ++#if 0 ++/* Define packet type. */ ++typedef enum tag_packet_type ++{ ++ PACKET_BROADCAST, ++ PACKET_MULTICAST, ++ PACKET_UNICAST, ++ PACKET_TYPE_MAX ++}cmpk_pkt_type_e; ++#endif ++ ++/* Define element ID of command packet. */ ++ ++/*------------------------------Define structure----------------------------*/ ++/* Define different command packet structure. */ ++/* 1. RX side: TX feedback packet. */ ++typedef struct tag_cmd_pkt_tx_feedback ++{ ++ // DWORD 0 ++ u8 element_id; /* Command packet type. */ ++ u8 length; /* Command packet length. */ ++ /* 2007/07/05 MH Change tx feedback info field. */ ++ /*------TX Feedback Info Field */ ++ u8 TID:4; /* */ ++ u8 fail_reason:3; /* */ ++ u8 tok:1; /* Transmit ok. */ ++ u8 reserve1:4; /* */ ++ u8 pkt_type:2; /* */ ++ u8 bandwidth:1; /* */ ++ u8 qos_pkt:1; /* */ ++ ++ // DWORD 1 ++ u8 reserve2; /* */ ++ /*------TX Feedback Info Field */ ++ u8 retry_cnt; /* */ ++ u16 pkt_id; /* */ ++ ++ // DWORD 3 ++ u16 seq_num; /* */ ++ u8 s_rate; /* Start rate. */ ++ u8 f_rate; /* Final rate. */ ++ ++ // DWORD 4 ++ u8 s_rts_rate; /* */ ++ u8 f_rts_rate; /* */ ++ u16 pkt_length; /* */ ++ ++ // DWORD 5 ++ u16 reserve3; /* */ ++ u16 duration; /* */ ++}cmpk_txfb_t; ++ ++/* 2. RX side: Interrupt status packet. It includes Beacon State, ++ Beacon Timer Interrupt and other useful informations in MAC ISR Reg. */ ++typedef struct tag_cmd_pkt_interrupt_status ++{ ++ u8 element_id; /* Command packet type. */ ++ u8 length; /* Command packet length. */ ++ u16 reserve; ++ u32 interrupt_status; /* Interrupt Status. */ ++}cmpk_intr_sta_t; ++ ++ ++/* 3. TX side: Set configuration packet. */ ++typedef struct tag_cmd_pkt_set_configuration ++{ ++ u8 element_id; /* Command packet type. */ ++ u8 length; /* Command packet length. */ ++ u16 reserve1; /* */ ++ u8 cfg_reserve1:3; ++ u8 cfg_size:2; /* Configuration info. */ ++ u8 cfg_type:2; /* Configuration info. */ ++ u8 cfg_action:1; /* Configuration info. */ ++ u8 cfg_reserve2; /* Configuration info. */ ++ u8 cfg_page:4; /* Configuration info. */ ++ u8 cfg_reserve3:4; /* Configuration info. */ ++ u8 cfg_offset; /* Configuration info. */ ++ u32 value; /* */ ++ u32 mask; /* */ ++}cmpk_set_cfg_t; ++ ++/* 4. Both side : TX/RX query configuraton packet. The query structure is the ++ same as set configuration. */ ++#define cmpk_query_cfg_t cmpk_set_cfg_t ++ ++/* 5. Multi packet feedback status. */ ++typedef struct tag_tx_stats_feedback // PJ quick rxcmd 09042007 ++{ ++ // For endian transfer --> Driver will not the same as firmware structure. ++ // DW 0 ++ u16 reserve1; ++ u8 length; // Command packet length ++ u8 element_id; // Command packet type ++ ++ // DW 1 ++ u16 txfail; // Tx Fail count ++ u16 txok; // Tx ok count ++ ++ // DW 2 ++ u16 txmcok; // tx multicast ++ u16 txretry; // Tx Retry count ++ ++ // DW 3 ++ u16 txucok; // tx unicast ++ u16 txbcok; // tx broadcast ++ ++ // DW 4 ++ u16 txbcfail; // ++ u16 txmcfail; // ++ ++ // DW 5 ++ u16 reserve2; // ++ u16 txucfail; // ++ ++ // DW 6-8 ++ u32 txmclength; ++ u32 txbclength; ++ u32 txuclength; ++ ++ // DW 9 ++ u16 reserve3_23; ++ u8 reserve3_1; ++ u8 rate; ++}__attribute__((packed)) cmpk_tx_status_t; ++ ++/* 6. Debug feedback message. */ ++/* 2007/10/23 MH Define RX debug message */ ++typedef struct tag_rx_debug_message_feedback ++{ ++ // For endian transfer --> for driver ++ // DW 0 ++ u16 reserve1; ++ u8 length; // Command packet length ++ u8 element_id; // Command packet type ++ ++ // DW 1-?? ++ // Variable debug message. ++ ++}cmpk_rx_dbginfo_t; ++ ++/* 2008/03/20 MH Define transmit rate history. For big endian format. */ ++typedef struct tag_tx_rate_history ++{ ++ // For endian transfer --> for driver ++ // DW 0 ++ u8 element_id; // Command packet type ++ u8 length; // Command packet length ++ u16 reserved1; ++ ++ // DW 1-2 CCK rate counter ++ u16 cck[4]; ++ ++ // DW 3-6 ++ u16 ofdm[8]; ++ ++ // DW 7-14 ++ //UINT16 MCS_BW0_SG0[16]; ++ ++ // DW 15-22 ++ //UINT16 MCS_BW1_SG0[16]; ++ ++ // DW 23-30 ++ //UINT16 MCS_BW0_SG1[16]; ++ ++ // DW 31-38 ++ //UINT16 MCS_BW1_SG1[16]; ++ ++ // DW 7-14 BW=0 SG=0 ++ // DW 15-22 BW=1 SG=0 ++ // DW 23-30 BW=0 SG=1 ++ // DW 31-38 BW=1 SG=1 ++ u16 ht_mcs[4][16]; ++ ++}__attribute__((packed)) cmpk_tx_rahis_t; ++ ++typedef enum tag_command_packet_directories ++{ ++ RX_TX_FEEDBACK = 0, ++ RX_INTERRUPT_STATUS = 1, ++ TX_SET_CONFIG = 2, ++ BOTH_QUERY_CONFIG = 3, ++ RX_TX_STATUS = 4, ++ RX_DBGINFO_FEEDBACK = 5, ++ RX_TX_PER_PKT_FEEDBACK = 6, ++ RX_TX_RATE_HISTORY = 7, ++ RX_CMD_ELE_MAX ++}cmpk_element_e; ++ ++extern u32 cmpk_message_handle_rx(struct net_device *dev, struct ieee80211_rx_stats * pstats); ++ ++ ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r819xE_firmware.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_firmware.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_firmware.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,620 @@ ++/************************************************************************************************** ++ * Procedure: Init boot code/firmware code/data session ++ * ++ * Description: This routine will intialize firmware. If any error occurs during the initialization ++ * process, the routine shall terminate immediately and return fail. ++ * NIC driver should call NdisOpenFile only from MiniportInitialize. ++ * ++ * Arguments: The pointer of the adapter ++ ++ * Returns: ++ * NDIS_STATUS_FAILURE - the following initialization process should be terminated ++ * NDIS_STATUS_SUCCESS - if firmware initialization process success ++**************************************************************************************************/ ++//#include "ieee80211.h" ++#include "r8192E.h" ++#include "r8192E_hw.h" ++#ifdef RTL8190P ++#include "r819xP_firmware_img.h" ++#else ++#include "r819xE_firmware_img.h" ++#endif ++#include "r819xE_firmware.h" ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++#include ++#endif ++ ++void firmware_init_param(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ rt_firmware *pfirmware = priv->pFirmware; ++ ++ pfirmware->cmdpacket_frag_thresold = GET_COMMAND_PACKET_FRAG_THRESHOLD(MAX_TRANSMIT_BUFFER_SIZE); ++} ++ ++/* ++ * segment the img and use the ptr and length to remember info on each segment ++ * ++ */ ++static bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, u32 buffer_len) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ bool rt_status = true; ++ u16 frag_threshold; ++ u16 frag_length, frag_offset = 0; ++ //u16 total_size; ++ int i; ++ ++ rt_firmware *pfirmware = priv->pFirmware; ++ struct sk_buff *skb; ++ unsigned char *seg_ptr; ++ cb_desc *tcb_desc; ++ u8 bLastIniPkt; ++ ++ firmware_init_param(dev); ++ //Fragmentation might be required ++ frag_threshold = pfirmware->cmdpacket_frag_thresold; ++ do { ++ if((buffer_len - frag_offset) > frag_threshold) { ++ frag_length = frag_threshold ; ++ bLastIniPkt = 0; ++ ++ } else { ++ frag_length = buffer_len - frag_offset; ++ bLastIniPkt = 1; ++ ++ } ++ ++ /* Allocate skb buffer to contain firmware info and tx descriptor info ++ * add 4 to avoid packet appending overflow. ++ * */ ++ //skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + frag_length + 4); ++ skb = dev_alloc_skb(frag_length + 4); ++ memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); ++ tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE); ++ tcb_desc->queue_index = TXCMD_QUEUE; ++ tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT; ++ tcb_desc->bLastIniPkt = bLastIniPkt; ++ ++ //skb_reserve(skb, USB_HWDESC_HEADER_LEN); ++ seg_ptr = skb->data; ++ /* ++ * Transform from little endian to big endian ++ * and pending zero ++ */ ++ for(i=0 ; i < frag_length; i+=4) { ++ *seg_ptr++ = ((i+0)txbuf_size= (u16)i; ++ skb_put(skb, i); ++ priv->ieee80211->softmac_hard_start_xmit(skb,dev); ++ ++ code_virtual_address += frag_length; ++ frag_offset += frag_length; ++ ++ }while(frag_offset < buffer_len); ++ ++ return rt_status; ++ ++#if 0 ++cmdsend_downloadcode_fail: ++ rt_status = false; ++ RT_TRACE(COMP_ERR, "CmdSendDownloadCode fail !!\n"); ++ return rt_status; ++#endif ++} ++ ++//----------------------------------------------------------------------------- ++// Procedure: Check whether main code is download OK. If OK, turn on CPU ++// ++// Description: CPU register locates in different page against general register. ++// Switch to CPU register in the begin and switch back before return ++// ++// ++// Arguments: The pointer of the adapter ++// ++// Returns: ++// NDIS_STATUS_FAILURE - the following initialization process should be terminated ++// NDIS_STATUS_SUCCESS - if firmware initialization process success ++//----------------------------------------------------------------------------- ++static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev) ++{ ++ bool rt_status = true; ++ int check_putcodeOK_time = 200000, check_bootOk_time = 200000; ++ u32 CPU_status = 0; ++ ++ /* Check whether put code OK */ ++ do { ++ CPU_status = read_nic_dword(dev, CPU_GEN); ++ ++ if(CPU_status&CPU_GEN_PUT_CODE_OK) ++ break; ++ ++ }while(check_putcodeOK_time--); ++ ++ if(!(CPU_status&CPU_GEN_PUT_CODE_OK)) { ++ RT_TRACE(COMP_ERR, "Download Firmware: Put code fail!\n"); ++ goto CPUCheckMainCodeOKAndTurnOnCPU_Fail; ++ } else { ++ RT_TRACE(COMP_FIRMWARE, "Download Firmware: Put code ok!\n"); ++ } ++ ++ /* Turn On CPU */ ++ CPU_status = read_nic_dword(dev, CPU_GEN); ++ write_nic_byte(dev, CPU_GEN, (u8)((CPU_status|CPU_GEN_PWR_STB_CPU)&0xff)); ++ mdelay(1); ++ ++ /* Check whether CPU boot OK */ ++ do { ++ CPU_status = read_nic_dword(dev, CPU_GEN); ++ ++ if(CPU_status&CPU_GEN_BOOT_RDY) ++ break; ++ }while(check_bootOk_time--); ++ ++ if(!(CPU_status&CPU_GEN_BOOT_RDY)) { ++ goto CPUCheckMainCodeOKAndTurnOnCPU_Fail; ++ } else { ++ RT_TRACE(COMP_FIRMWARE, "Download Firmware: Boot ready!\n"); ++ } ++ ++ return rt_status; ++ ++CPUCheckMainCodeOKAndTurnOnCPU_Fail: ++ RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__); ++ rt_status = FALSE; ++ return rt_status; ++} ++ ++static bool CPUcheck_firmware_ready(struct net_device *dev) ++{ ++ ++ bool rt_status = true; ++ int check_time = 200000; ++ u32 CPU_status = 0; ++ ++ /* Check Firmware Ready */ ++ do { ++ CPU_status = read_nic_dword(dev, CPU_GEN); ++ ++ if(CPU_status&CPU_GEN_FIRM_RDY) ++ break; ++ ++ }while(check_time--); ++ ++ if(!(CPU_status&CPU_GEN_FIRM_RDY)) ++ goto CPUCheckFirmwareReady_Fail; ++ else ++ RT_TRACE(COMP_FIRMWARE, "Download Firmware: Firmware ready!\n"); ++ ++ return rt_status; ++ ++CPUCheckFirmwareReady_Fail: ++ RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__); ++ rt_status = false; ++ return rt_status; ++ ++} ++ ++bool init_firmware(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ bool rt_status = TRUE; ++ ++#ifdef RTL8190P ++ u8 *firmware_img_buf[3] = { &rtl8190_fwboot_array[0], ++ &rtl8190_fwmain_array[0], ++ &rtl8190_fwdata_array[0]}; ++ ++ u32 firmware_img_len[3] = { sizeof(rtl8190_fwboot_array), ++ sizeof(rtl8190_fwmain_array), ++ sizeof(rtl8190_fwdata_array)}; ++#else ++ u8 *firmware_img_buf[3] = { &rtl8192e_fwboot_array[0], ++ &rtl8192e_fwmain_array[0], ++ &rtl8192e_fwdata_array[0]}; ++ ++ u32 firmware_img_len[3] = { sizeof(rtl8192e_fwboot_array), ++ sizeof(rtl8192e_fwmain_array), ++ sizeof(rtl8192e_fwdata_array)}; ++#endif ++ u32 file_length = 0; ++ u8 *mapped_file = NULL; ++ u32 init_step = 0; ++ opt_rst_type_e rst_opt = OPT_SYSTEM_RESET; ++ firmware_init_step_e starting_state = FW_INIT_STEP0_BOOT; ++ ++ rt_firmware *pfirmware = priv->pFirmware; ++ const struct firmware *fw_entry; ++#ifdef RTL8190P ++ const char *fw_name[3] = { "RTL8190P/boot.img", ++ "RTL8190P/main.img", ++ "RTL8190P/data.img"}; ++#endif ++#ifdef RTL8192E ++ const char *fw_name[3] = { "RTL8192E/boot.img", ++ "RTL8192E/main.img", ++ "RTL8192E/data.img"}; ++#endif ++ int rc; ++ ++ RT_TRACE(COMP_FIRMWARE, " PlatformInitFirmware()==>\n"); ++ ++ if (pfirmware->firmware_status == FW_STATUS_0_INIT ) { ++ /* it is called by reset */ ++ rst_opt = OPT_SYSTEM_RESET; ++ starting_state = FW_INIT_STEP0_BOOT; ++ // TODO: system reset ++ ++ }else if(pfirmware->firmware_status == FW_STATUS_5_READY) { ++ /* it is called by Initialize */ ++ rst_opt = OPT_FIRMWARE_RESET; ++ starting_state = FW_INIT_STEP2_DATA; ++ }else { ++ RT_TRACE(COMP_FIRMWARE, "PlatformInitFirmware: undefined firmware state\n"); ++ } ++ ++ /* ++ * Download boot, main, and data image for System reset. ++ * Download data image for firmware reseta ++ */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++ priv->firmware_source = FW_SOURCE_HEADER_FILE; ++#else ++ priv->firmware_source = FW_SOURCE_IMG_FILE; ++#endif ++ for(init_step = starting_state; init_step <= FW_INIT_STEP2_DATA; init_step++) { ++ /* ++ * Open Image file, and map file to contineous memory if open file success. ++ * or read image file from array. Default load from IMG file ++ */ ++ if(rst_opt == OPT_SYSTEM_RESET) { ++ switch(priv->firmware_source) { ++ case FW_SOURCE_IMG_FILE: ++ { ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ if(pfirmware->firmware_buf_size[init_step] == 0) { ++ rc = request_firmware(&fw_entry, fw_name[init_step],&priv->pdev->dev); ++ if(rc < 0 ) { ++ RT_TRACE(COMP_FIRMWARE, "request firmware fail!\n"); ++ goto download_firmware_fail; ++ } ++ ++ if(fw_entry->size > sizeof(pfirmware->firmware_buf[init_step])) { ++ RT_TRACE(COMP_FIRMWARE, "img file size exceed the container buffer fail!\n"); ++ goto download_firmware_fail; ++ } ++ ++ if(init_step != FW_INIT_STEP1_MAIN) { ++ memcpy(pfirmware->firmware_buf[init_step],fw_entry->data,fw_entry->size); ++ pfirmware->firmware_buf_size[init_step] = fw_entry->size; ++ ++ } else { ++#ifdef RTL8190P ++ memcpy(pfirmware->firmware_buf[init_step],fw_entry->data,fw_entry->size); ++ pfirmware->firmware_buf_size[init_step] = fw_entry->size; ++ ++#else ++ memset(pfirmware->firmware_buf[init_step],0,128); ++ memcpy(&pfirmware->firmware_buf[init_step][128],fw_entry->data,fw_entry->size); ++ //mapped_file = pfirmware->firmware_buf[init_step]; ++ pfirmware->firmware_buf_size[init_step] = fw_entry->size+128; ++ //file_length = fw_entry->size + 128; ++#endif ++ } ++ //pfirmware->firmware_buf_size = file_length; ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ if(rst_opt == OPT_SYSTEM_RESET) { ++ release_firmware(fw_entry); ++ } ++#endif ++ } ++ mapped_file = pfirmware->firmware_buf[init_step]; ++ file_length = pfirmware->firmware_buf_size[init_step]; ++#endif ++ break; ++ } ++ case FW_SOURCE_HEADER_FILE: ++ mapped_file = firmware_img_buf[init_step]; ++ file_length = firmware_img_len[init_step]; ++ if(init_step == FW_INIT_STEP2_DATA) { ++ memcpy(pfirmware->firmware_buf[init_step], mapped_file, file_length); ++ pfirmware->firmware_buf_size[init_step] = file_length; ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ ++ }else if(rst_opt == OPT_FIRMWARE_RESET ) { ++ /* we only need to download data.img here */ ++ mapped_file = pfirmware->firmware_buf[init_step]; ++ file_length = pfirmware->firmware_buf_size[init_step]; ++ } ++ ++ /* Download image file */ ++ /* The firmware download process is just as following, ++ * 1. that is each packet will be segmented and inserted to the wait queue. ++ * 2. each packet segment will be put in the skb_buff packet. ++ * 3. each skb_buff packet data content will already include the firmware info ++ * and Tx descriptor info ++ * */ ++ rt_status = fw_download_code(dev,mapped_file,file_length); ++ if(rt_status != TRUE) { ++ goto download_firmware_fail; ++ } ++ ++ switch(init_step) { ++ case FW_INIT_STEP0_BOOT: ++ /* Download boot ++ * initialize command descriptor. ++ * will set polling bit when firmware code is also configured ++ */ ++ pfirmware->firmware_status = FW_STATUS_1_MOVE_BOOT_CODE; ++ //mdelay(1000); ++ /* ++ * To initialize IMEM, CPU move code from 0x80000080, ++ * hence, we send 0x80 byte packet ++ */ ++ break; ++ ++ case FW_INIT_STEP1_MAIN: ++ /* Download firmware code. Wait until Boot Ready and Turn on CPU */ ++ pfirmware->firmware_status = FW_STATUS_2_MOVE_MAIN_CODE; ++ ++ /* Check Put Code OK and Turn On CPU */ ++ rt_status = CPUcheck_maincodeok_turnonCPU(dev); ++ if(rt_status != TRUE) { ++ RT_TRACE(COMP_FIRMWARE, "CPUcheck_maincodeok_turnonCPU fail!\n"); ++ goto download_firmware_fail; ++ } ++ ++ pfirmware->firmware_status = FW_STATUS_3_TURNON_CPU; ++ break; ++ ++ case FW_INIT_STEP2_DATA: ++ /* download initial data code */ ++ pfirmware->firmware_status = FW_STATUS_4_MOVE_DATA_CODE; ++ mdelay(1); ++ ++ rt_status = CPUcheck_firmware_ready(dev); ++ if(rt_status != TRUE) { ++ RT_TRACE(COMP_FIRMWARE, "CPUcheck_firmware_ready fail(%d)!\n",rt_status); ++ goto download_firmware_fail; ++ } ++ ++ /* wait until data code is initialized ready.*/ ++ pfirmware->firmware_status = FW_STATUS_5_READY; ++ break; ++ } ++ } ++ ++ RT_TRACE(COMP_FIRMWARE, "Firmware Download Success\n"); ++ //assert(pfirmware->firmware_status == FW_STATUS_5_READY, ("Firmware Download Fail\n")); ++ ++ return rt_status; ++ ++download_firmware_fail: ++ RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__); ++ rt_status = FALSE; ++ return rt_status; ++ ++} ++ ++#if 0 ++/* ++ * Procedure: (1) Transform firmware code from little endian to big endian if required. ++ * (2) Number of bytes in Firmware downloading should be multiple ++ * of 4 bytes. If length is not multiple of 4 bytes, appending of zeros is required ++ * ++ */ ++void CmdAppendZeroAndEndianTransform( ++ u1Byte *pDst, ++ u1Byte *pSrc, ++ u2Byte *pLength) ++{ ++ ++ u2Byte ulAppendBytes = 0, i; ++ u2Byte ulLength = *pLength; ++ ++//test only ++ //memset(pDst, 0xcc, 12); ++ ++ ++ /* Transform from little endian to big endian */ ++//#if DEV_BUS_TYPE==PCI_INTERFACE ++#if 0 ++ for( i=0 ; i<(*pLength) ; i+=4) ++ { ++ if((i+3) < (*pLength)) pDst[i+0] = pSrc[i+3]; ++ if((i+2) < (*pLength)) pDst[i+1] = pSrc[i+2]; ++ if((i+1) < (*pLength)) pDst[i+2] = pSrc[i+1]; ++ if((i+0) < (*pLength)) pDst[i+3] = pSrc[i+0]; ++ } ++#else ++ pDst += USB_HWDESC_HEADER_LEN; ++ ulLength -= USB_HWDESC_HEADER_LEN; ++ ++ for( i=0 ; i0) ++ { ++ ulAppendBytes = 4-((*pLength) % 4); ++ ++ for(i=0 ; iFragLength[0] = (u2Byte)pTcb->BufferList[0].Length; ++ ++ QueueID=pTcb->SpecifiedQueueID; ++#if DEV_BUS_TYPE!=USB_INTERFACE ++ firstDesc=curDesc=Adapter->NextTxDescToFill[QueueID]; ++#endif ++ ++#if DEV_BUS_TYPE!=USB_INTERFACE ++ if(VacancyTxDescNum(Adapter, QueueID) > pTcb->BufferCount) ++#else ++ if(PlatformIsTxQueueAvailable(Adapter, QueueID, pTcb->BufferCount) && ++ RTIsListEmpty(&Adapter->TcbWaitQueue[QueueID])) ++#endif ++ { ++ pTcb->nDescUsed=0; ++ ++ for(i=0 ; iBufferCount ; i++) ++ { ++ Adapter->HalFunc.TxFillCmdDescHandler( ++ Adapter, ++ pTcb, ++ QueueID, //QueueIndex ++ curDesc, //index ++ FragBufferIndex==0, //bFirstSeg ++ FragBufferIndex==(pTcb->FragBufCount[FragIndex]-1), //bLastSeg ++ pTcb->BufferList[i].VirtualAddress, //VirtualAddress ++ pTcb->BufferList[i].PhysicalAddressLow, //PhyAddressLow ++ pTcb->BufferList[i].Length, //BufferLen ++ i!=0, //bSetOwnBit ++ (i==(pTcb->BufferCount-1)) && bLastInitPacket, //bLastInitPacket ++ PacketType, //DescPacketType ++ pTcb->FragLength[FragIndex] //PktLen ++ ); ++ ++ if(FragBufferIndex==(pTcb->FragBufCount[FragIndex]-1)) ++ { // Last segment of the fragment. ++ pTcb->nFragSent++; ++ } ++ ++ FragBufferIndex++; ++ if(FragBufferIndex==pTcb->FragBufCount[FragIndex]) ++ { ++ FragIndex++; ++ FragBufferIndex=0; ++ } ++ ++#if DEV_BUS_TYPE!=USB_INTERFACE ++ curDesc=(curDesc+1)%Adapter->NumTxDesc[QueueID]; ++#endif ++ pTcb->nDescUsed++; ++ } ++ ++#if DEV_BUS_TYPE!=USB_INTERFACE ++ RTInsertTailList(&Adapter->TcbBusyQueue[QueueID], &pTcb->List); ++ IncrementTxDescToFill(Adapter, QueueID, pTcb->nDescUsed); ++ Adapter->HalFunc.SetTxDescOWNHandler(Adapter, QueueID, firstDesc); ++ // TODO: should call poll use QueueID ++ Adapter->HalFunc.TxPollingHandler(Adapter, TXCMD_QUEUE); ++#endif ++ } ++ else ++#if DEV_BUS_TYPE!=USB_INTERFACE ++ goto CmdSendPacket_Fail; ++#else ++ { ++ pTcb->bLastInitPacket = bLastInitPacket; ++ RTInsertTailList(&Adapter->TcbWaitQueue[pTcb->SpecifiedQueueID], &pTcb->List); ++ } ++#endif ++ ++ return rtStatus; ++ ++#if DEV_BUS_TYPE!=USB_INTERFACE ++CmdSendPacket_Fail: ++ rtStatus = RT_STATUS_FAILURE; ++ return rtStatus; ++#endif ++ ++} ++#endif ++ ++ ++ ++ ++#if 0 ++RT_STATUS ++FWSendNullPacket( ++ IN PADAPTER Adapter, ++ IN u4Byte Length ++) ++{ ++ RT_STATUS rtStatus = RT_STATUS_SUCCESS; ++ ++ ++ PRT_TCB pTcb; ++ PRT_TX_LOCAL_BUFFER pBuf; ++ BOOLEAN bLastInitPacket = FALSE; ++ ++ PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); ++ ++#if DEV_BUS_TYPE==USB_INTERFACE ++ Length += USB_HWDESC_HEADER_LEN; ++#endif ++ ++ //Get TCB and local buffer from common pool. (It is shared by CmdQ, MgntQ, and USB coalesce DataQ) ++ if(MgntGetBuffer(Adapter, &pTcb, &pBuf)) ++ { ++ PlatformZeroMemory(pBuf->Buffer.VirtualAddress, Length); ++ rtStatus = CmdSendPacket(Adapter, pTcb, pBuf, Length, DESC_PACKET_TYPE_INIT, bLastInitPacket); //0 : always set LastInitPacket to zero ++//#if HAL_CODE_BASE != RTL8190HW ++// // TODO: for test only ++// ReturnTCB(Adapter, pTcb, RT_STATUS_SUCCESS); ++//#endif ++ if(rtStatus == RT_STATUS_FAILURE) ++ goto CmdSendNullPacket_Fail; ++ }else ++ goto CmdSendNullPacket_Fail; ++ ++ PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); ++ return rtStatus; ++ ++ ++CmdSendNullPacket_Fail: ++ PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); ++ rtStatus = RT_STATUS_FAILURE; ++ RT_ASSERT(rtStatus == RT_STATUS_SUCCESS, ("CmdSendDownloadCode fail !!\n")); ++ return rtStatus; ++} ++#endif ++ ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r819xE_firmware.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_firmware.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_firmware.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,68 @@ ++#ifndef __INC_FIRMWARE_H ++#define __INC_FIRMWARE_H ++ ++#define RTL8190_CPU_START_OFFSET 0x80 ++/* TODO: this definition is TBD */ ++//#define USB_HWDESC_HEADER_LEN 0 ++ ++/* It should be double word alignment */ ++//#if DEV_BUS_TYPE==PCI_INTERFACE ++//#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8 ++//#else ++#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 ) ++//#endif ++ ++typedef enum _firmware_init_step{ ++ FW_INIT_STEP0_BOOT = 0, ++ FW_INIT_STEP1_MAIN = 1, ++ FW_INIT_STEP2_DATA = 2, ++}firmware_init_step_e; ++ ++typedef enum _opt_rst_type{ ++ OPT_SYSTEM_RESET = 0, ++ OPT_FIRMWARE_RESET = 1, ++}opt_rst_type_e; ++ ++#if 0 ++/* CPU related */ ++RT_STATUS ++CPUCheckMainCodeOKAndTurnOnCPU( ++ IN PADAPTER Adapter ++ ); ++ ++RT_STATUS ++CPUCheckFirmwareReady( ++ IN PADAPTER Adapter ++ ); ++ ++/* Firmware related */ ++VOID ++FWInitializeParameters( ++ IN PADAPTER Adapter ++ ); ++ ++RT_STATUS ++FWSendDownloadCode( ++ IN PADAPTER Adapter, ++ IN pu1Byte CodeVirtualAddrress, ++ IN u4Byte BufferLen ++ ); ++ ++RT_STATUS ++FWSendNullPacket( ++ IN PADAPTER Adapter, ++ IN u4Byte Length ++ ); ++ ++RT_STATUS ++CmdSendPacket( ++ PADAPTER Adapter, ++ PRT_TCB pTcb, ++ PRT_TX_LOCAL_BUFFER pBuf, ++ u4Byte BufferLen, ++ u4Byte PacketType, ++ BOOLEAN bLastInitPacket ++ ); ++#endif ++#endif ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r819xE_firmware_img.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_firmware_img.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_firmware_img.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,2778 @@ ++#ifndef __INC_R819XE_FIRMWARE_IMG_H ++#define __INC_R819XE_FIRMWARE_IMG_H ++ ++/*Created on 2008/ 8/28, 11:46*/ ++#include ++ ++static u8 rtl8192e_fwboot_array[] = { ++0x10,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x3c,0x08,0xbf,0xc0,0x25,0x08,0x00,0x08, ++0x3c,0x09,0xb0,0x03,0xad,0x28,0x00,0x20,0x40,0x80,0x68,0x00,0x00,0x00,0x00,0x00, ++0x3c,0x0a,0xd0,0x00,0x40,0x8a,0x60,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01, ++0x25,0x08,0xa8,0x04,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff, ++0x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01,0x01,0x2a,0x10,0x2b, ++0x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x00,0x00,0x25,0x4a,0x00,0x00, ++0x4c,0x8a,0x00,0x00,0x4c,0x89,0x08,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01, ++0x25,0x08,0xa8,0x04,0x3c,0x01,0x80,0x00,0x01,0x21,0x48,0x25,0x3c,0x0a,0xbf,0xc0, ++0x25,0x4a,0x00,0x7c,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0xad,0x00,0x00,0x00, ++0x21,0x08,0x00,0x04,0x01,0x09,0x10,0x2b,0x14,0x40,0xff,0xf8,0x00,0x00,0x00,0x00, ++0x3c,0x08,0x80,0x01,0x25,0x08,0x7f,0xff,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff, ++0x34,0x21,0xff,0xff,0x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01, ++0x01,0x2a,0x10,0x2b,0x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x01, ++0x25,0x4a,0x00,0x00,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff,0x01,0x41,0x50,0x24, ++0x3c,0x09,0x00,0x01,0x35,0x29,0x7f,0xff,0x4c,0x8a,0x20,0x00,0x4c,0x89,0x28,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x08,0x04,0x10, ++0x00,0x00,0x00,0x00,0x40,0x88,0xa0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x3c,0x08,0xbf,0xc0,0x00,0x00,0x00,0x00,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00, ++0x3c,0x0a,0xbf,0xc0,0x25,0x4a,0x01,0x20,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20, ++0x3c,0x08,0xb0,0x03,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x35,0x29,0x00,0x10, ++0xad,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x00,0x25,0x08,0x4b,0x94, ++0x01,0x00,0x00,0x08,0x00,0x00,0x00,0x00,}; ++ ++static u8 rtl8192e_fwmain_array[] = { ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x40,0x04,0x68,0x00,0x40,0x05,0x70,0x00,0x40,0x06,0x40,0x00,0x0c,0x00,0x12,0x98, ++0x00,0x00,0x00,0x00,0x40,0x1a,0x68,0x00,0x33,0x5b,0x00,0x3c,0x17,0x60,0x00,0x09, ++0x00,0x00,0x00,0x00,0x40,0x1b,0x60,0x00,0x00,0x00,0x00,0x00,0x03,0x5b,0xd0,0x24, ++0x40,0x1a,0x70,0x00,0x03,0x40,0x00,0x08,0x42,0x00,0x00,0x10,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0xff,0x34,0x42,0xff,0xff,0x8c,0x43,0x00,0x00, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x00,0xd0, ++0xac,0x62,0x00,0x00,0x00,0x00,0x20,0x21,0x27,0x85,0x8b,0x70,0x00,0x85,0x18,0x21, ++0x24,0x84,0x00,0x01,0x28,0x82,0x00,0x0a,0x14,0x40,0xff,0xfc,0xa0,0x60,0x00,0x00, ++0x27,0x82,0x8b,0x7a,0x24,0x04,0x00,0x06,0x24,0x84,0xff,0xff,0xa4,0x40,0x00,0x00, ++0x04,0x81,0xff,0xfd,0x24,0x42,0x00,0x02,0x24,0x02,0x00,0x03,0xa3,0x82,0x8b,0x70, ++0x24,0x02,0x00,0x0a,0x24,0x03,0x09,0xc4,0xa3,0x82,0x8b,0x72,0x24,0x02,0x00,0x04, ++0x24,0x04,0x00,0x01,0x24,0x05,0x00,0x02,0xa7,0x83,0x8b,0x86,0xa3,0x82,0x8b,0x78, ++0x24,0x03,0x04,0x00,0x24,0x02,0x02,0x00,0xaf,0x83,0x8b,0x8c,0xa3,0x85,0x8b,0x79, ++0xa7,0x82,0x8b,0x7a,0xa7,0x84,0x8b,0x7c,0xaf,0x84,0x8b,0x88,0xa3,0x84,0x8b,0x71, ++0xa3,0x80,0x8b,0x73,0xa3,0x80,0x8b,0x74,0xa3,0x80,0x8b,0x75,0xa3,0x84,0x8b,0x76, ++0xa3,0x85,0x8b,0x77,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x24,0x42,0x01,0x7c,0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00, ++0x27,0x84,0x8b,0x98,0x00,0x00,0x10,0x21,0x24,0x42,0x00,0x01,0x00,0x02,0x16,0x00, ++0x00,0x02,0x16,0x03,0x28,0x43,0x00,0x03,0xac,0x80,0xff,0xfc,0xa0,0x80,0x00,0x00, ++0x14,0x60,0xff,0xf9,0x24,0x84,0x00,0x0c,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x01,0xc0, ++0x3c,0x08,0xb0,0x03,0xac,0x62,0x00,0x00,0x35,0x08,0x00,0x70,0x8d,0x02,0x00,0x00, ++0x00,0xa0,0x48,0x21,0x00,0x04,0x26,0x00,0x00,0x02,0x2a,0x43,0x00,0x06,0x36,0x00, ++0x00,0x07,0x3e,0x00,0x00,0x02,0x12,0x03,0x29,0x23,0x00,0x03,0x00,0x04,0x56,0x03, ++0x00,0x06,0x36,0x03,0x00,0x07,0x3e,0x03,0x30,0x48,0x00,0x01,0x10,0x60,0x00,0x11, ++0x30,0xa5,0x00,0x07,0x24,0x02,0x00,0x02,0x00,0x49,0x10,0x23,0x00,0x45,0x10,0x07, ++0x30,0x42,0x00,0x01,0x10,0x40,0x00,0x66,0x00,0x00,0x00,0x00,0x8f,0xa2,0x00,0x10, ++0x00,0x00,0x00,0x00,0x00,0x02,0x21,0x43,0x11,0x00,0x00,0x10,0x00,0x07,0x20,0x0b, ++0x15,0x20,0x00,0x06,0x24,0x02,0x00,0x01,0x3c,0x02,0xb0,0x05,0x34,0x42,0x01,0x20, ++0xa4,0x44,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x11,0x22,0x00,0x04, ++0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05,0x08,0x00,0x00,0x94,0x34,0x42,0x01,0x24, ++0x3c,0x02,0xb0,0x05,0x08,0x00,0x00,0x94,0x34,0x42,0x01,0x22,0x15,0x20,0x00,0x54, ++0x24,0x02,0x00,0x01,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x74,0x90,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0xaf,0x83,0x8b,0x94,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x70, ++0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x6b,0x00,0x08,0x11,0x60,0x00,0x18, ++0x00,0x09,0x28,0x40,0x00,0x00,0x40,0x21,0x27,0x85,0x8b,0x90,0x8c,0xa3,0x00,0x00, ++0x8c,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x62,0x38,0x23,0x00,0x43,0x10,0x2a, ++0x10,0x40,0x00,0x3d,0x00,0x00,0x00,0x00,0xac,0xa7,0x00,0x00,0x25,0x02,0x00,0x01, ++0x00,0x02,0x16,0x00,0x00,0x02,0x46,0x03,0x29,0x03,0x00,0x03,0x14,0x60,0xff,0xf3, ++0x24,0xa5,0x00,0x0c,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x70,0x90,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x4b,0x10,0x23,0xa0,0x62,0x00,0x00,0x00,0x09,0x28,0x40, ++0x00,0xa9,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x8b,0x98,0x00,0x0a,0x20,0x0b, ++0x00,0x43,0x18,0x21,0x10,0xc0,0x00,0x05,0x00,0x00,0x38,0x21,0x80,0x62,0x00,0x01, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x80,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03,0x00,0xa9,0x10,0x21,0x24,0x07,0x00,0x01, ++0x00,0xa9,0x10,0x21,0x00,0x02,0x30,0x80,0x27,0x82,0x8b,0x98,0xa0,0x67,0x00,0x01, ++0x00,0xc2,0x38,0x21,0x80,0xe3,0x00,0x01,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x07, ++0x00,0x00,0x00,0x00,0x27,0x83,0x8b,0x90,0x00,0xc3,0x18,0x21,0x8c,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x21,0xac,0x62,0x00,0x00,0x27,0x85,0x8b,0x94, ++0x27,0x82,0x8b,0x90,0x00,0xc5,0x28,0x21,0x00,0xc2,0x10,0x21,0x8c,0x43,0x00,0x00, ++0x8c,0xa4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x64,0x18,0x2a,0x14,0x60,0x00,0x03, ++0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,0xa0,0xe2,0x00,0x00,0xa0,0xe0,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0xb7,0xac,0xa0,0x00,0x00, ++0x11,0x22,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x7c, ++0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x83,0x8b,0xac,0x08,0x00,0x00,0xa7, ++0x3c,0x02,0xb0,0x03,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x78,0x90,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0xaf,0x83,0x8b,0xa0,0x08,0x00,0x00,0xa7,0x3c,0x02,0xb0,0x03, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x04,0x10, ++0x3c,0x05,0xb0,0x03,0xac,0x62,0x00,0x00,0x34,0xa5,0x00,0x70,0x8c,0xa2,0x00,0x00, ++0x90,0x84,0x00,0x08,0x3c,0x06,0xb0,0x03,0x00,0x02,0x16,0x00,0x2c,0x83,0x00,0x03, ++0x34,0xc6,0x00,0x72,0x24,0x07,0x00,0x01,0x10,0x60,0x00,0x11,0x00,0x02,0x2f,0xc2, ++0x90,0xc2,0x00,0x00,0x00,0x00,0x18,0x21,0x00,0x02,0x16,0x00,0x10,0xa7,0x00,0x09, ++0x00,0x02,0x16,0x03,0x14,0x80,0x00,0x0c,0x30,0x43,0x00,0x03,0x83,0x82,0x8b,0x98, ++0x00,0x00,0x00,0x00,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0x02,0x16,0x00, ++0x00,0x02,0x1e,0x03,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x72,0xa0,0x43,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0x45,0x00,0x05,0x10,0x87,0x00,0x04, ++0x30,0x43,0x00,0x06,0x93,0x82,0x8b,0xb0,0x08,0x00,0x01,0x1f,0x00,0x43,0x10,0x21, ++0x83,0x82,0x8b,0xa4,0x00,0x00,0x00,0x00,0x00,0x02,0x10,0x40,0x08,0x00,0x01,0x1f, ++0x00,0x45,0x10,0x21,0x10,0x80,0x00,0x05,0x00,0x00,0x18,0x21,0x24,0x63,0x00,0x01, ++0x00,0x64,0x10,0x2b,0x14,0x40,0xff,0xfd,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x04,0xe4, ++0x3c,0x04,0xb0,0x02,0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00,0x34,0x84,0x00,0x08, ++0x24,0x02,0x00,0x01,0xaf,0x84,0x8b,0xc0,0xa3,0x82,0x8b,0xd0,0xa7,0x80,0x8b,0xc4, ++0xa7,0x80,0x8b,0xc6,0xaf,0x80,0x8b,0xc8,0xaf,0x80,0x8b,0xcc,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20, ++0x24,0x42,0x05,0x24,0x3c,0x04,0xb0,0x03,0xac,0x62,0x00,0x00,0x34,0x84,0x00,0xac, ++0x80,0xa2,0x00,0x15,0x8c,0x83,0x00,0x00,0x27,0xbd,0xff,0xf0,0x00,0x43,0x10,0x21, ++0xac,0x82,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x10,0x3c,0x02,0xb0,0x03, ++0x3c,0x03,0x80,0x00,0x34,0x42,0x00,0x20,0x24,0x63,0x05,0x5c,0x27,0xbd,0xff,0xe0, ++0xac,0x43,0x00,0x00,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x18, ++0x8f,0x90,0x8b,0xc0,0x0c,0x00,0x02,0x98,0x00,0x80,0x88,0x21,0x14,0x40,0x00,0x2a, ++0x3c,0x02,0x00,0x80,0x16,0x20,0x00,0x02,0x34,0x42,0x02,0x01,0x24,0x02,0x02,0x01, ++0xae,0x02,0x00,0x00,0x97,0x84,0x8b,0xc4,0x97,0x82,0x8b,0xc6,0x3c,0x03,0xb0,0x02, ++0x00,0x83,0x20,0x21,0x24,0x42,0x00,0x04,0xa7,0x82,0x8b,0xc6,0xa4,0x82,0x00,0x00, ++0x8f,0x84,0x8b,0xc8,0x8f,0x82,0x8b,0xc0,0x93,0x85,0x8b,0x72,0x24,0x84,0x00,0x01, ++0x24,0x42,0x00,0x04,0x24,0x03,0x8f,0xff,0x3c,0x07,0xb0,0x06,0x3c,0x06,0xb0,0x03, ++0x00,0x43,0x10,0x24,0x00,0x85,0x28,0x2a,0x34,0xe7,0x80,0x18,0xaf,0x82,0x8b,0xc0, ++0xaf,0x84,0x8b,0xc8,0x10,0xa0,0x00,0x08,0x34,0xc6,0x01,0x08,0x8f,0x83,0x8b,0xcc, ++0x8f,0x84,0x8b,0x8c,0x8c,0xc2,0x00,0x00,0x00,0x64,0x18,0x21,0x00,0x43,0x10,0x2b, ++0x14,0x40,0x00,0x09,0x00,0x00,0x00,0x00,0x8c,0xe2,0x00,0x00,0x3c,0x03,0x0f,0x00, ++0x3c,0x04,0x04,0x00,0x00,0x43,0x10,0x24,0x10,0x44,0x00,0x03,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x04,0x96,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x27,0xbd,0xff,0xd8,0x3c,0x02,0xb0,0x03, ++0x3c,0x03,0x80,0x00,0x24,0x63,0x06,0x48,0xaf,0xb0,0x00,0x10,0x34,0x42,0x00,0x20, ++0x8f,0x90,0x8b,0xc0,0xac,0x43,0x00,0x00,0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18, ++0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x20,0x00,0x80,0x88,0x21,0x00,0xa0,0x90,0x21, ++0x0c,0x00,0x02,0x98,0x00,0xc0,0x98,0x21,0x24,0x07,0x8f,0xff,0x14,0x40,0x00,0x19, ++0x26,0x03,0x00,0x04,0x24,0x02,0x0e,0x03,0xae,0x02,0x00,0x00,0x00,0x67,0x80,0x24, ++0x26,0x02,0x00,0x04,0xae,0x11,0x00,0x00,0x00,0x47,0x80,0x24,0x97,0x86,0x8b,0xc4, ++0x26,0x03,0x00,0x04,0xae,0x12,0x00,0x00,0x00,0x67,0x80,0x24,0xae,0x13,0x00,0x00, ++0x8f,0x84,0x8b,0xc0,0x3c,0x02,0xb0,0x02,0x97,0x85,0x8b,0xc6,0x00,0xc2,0x30,0x21, ++0x8f,0x82,0x8b,0xc8,0x24,0x84,0x00,0x10,0x24,0xa5,0x00,0x10,0x00,0x87,0x20,0x24, ++0x24,0x42,0x00,0x01,0xa7,0x85,0x8b,0xc6,0xaf,0x84,0x8b,0xc0,0xaf,0x82,0x8b,0xc8, ++0xa4,0xc5,0x00,0x00,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10, ++0x94,0x82,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0xe0,0x00,0x14,0x40,0x00,0x14, ++0x00,0x00,0x00,0x00,0x90,0x82,0x00,0x02,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfc, ++0x00,0x82,0x28,0x21,0x8c,0xa4,0x00,0x00,0x3c,0x02,0x00,0x70,0x8c,0xa6,0x00,0x08, ++0x00,0x82,0x10,0x21,0x2c,0x43,0x00,0x06,0x10,0x60,0x00,0x09,0x3c,0x03,0x80,0x01, ++0x00,0x02,0x10,0x80,0x24,0x63,0x01,0xe8,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0xaf,0x86,0x80,0x14, ++0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18, ++0x8c,0xa4,0x00,0x00,0x0c,0x00,0x17,0x84,0x00,0x00,0x00,0x00,0x08,0x00,0x01,0xdc, ++0x00,0x00,0x00,0x00,0x0c,0x00,0x24,0x49,0x00,0xc0,0x20,0x21,0x08,0x00,0x01,0xdc, ++0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,0x8c,0x44,0x00,0x00, ++0x8f,0x82,0x80,0x18,0x3c,0x03,0x00,0x0f,0x34,0x63,0x42,0x40,0x00,0x43,0x10,0x21, ++0x00,0x82,0x20,0x2b,0x10,0x80,0x00,0x09,0x24,0x03,0x00,0x05,0x8f,0x82,0x83,0x60, ++0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xaf,0x82,0x83,0x60,0x10,0x43,0x00,0x03, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03, ++0x8c,0x63,0x01,0x08,0x24,0x02,0x00,0x01,0xa3,0x82,0x80,0x11,0xaf,0x80,0x83,0x60, ++0xaf,0x83,0x80,0x18,0x08,0x00,0x01,0xf9,0x00,0x00,0x00,0x00,0x30,0x84,0x00,0xff, ++0x14,0x80,0x00,0x2f,0x00,0x00,0x00,0x00,0x8f,0x82,0x80,0x14,0xa3,0x85,0x83,0x93, ++0x10,0x40,0x00,0x2b,0x2c,0xa2,0x00,0x04,0x14,0x40,0x00,0x06,0x00,0x05,0x10,0x40, ++0x24,0xa2,0xff,0xfc,0x2c,0x42,0x00,0x08,0x10,0x40,0x00,0x09,0x24,0xa2,0xff,0xf0, ++0x00,0x05,0x10,0x40,0x27,0x84,0x83,0x9c,0x00,0x44,0x10,0x21,0x94,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,0x03,0xe0,0x00,0x08,0xa4,0x43,0x00,0x00, ++0x2c,0x42,0x00,0x10,0x14,0x40,0x00,0x0a,0x00,0x05,0x10,0x40,0x24,0xa2,0xff,0xe0, ++0x2c,0x42,0x00,0x10,0x14,0x40,0x00,0x06,0x00,0x05,0x10,0x40,0x24,0xa2,0xff,0xd0, ++0x2c,0x42,0x00,0x10,0x10,0x40,0x00,0x09,0x24,0xa2,0xff,0xc0,0x00,0x05,0x10,0x40, ++0x27,0x84,0x83,0x9c,0x00,0x44,0x10,0x21,0x94,0x43,0xff,0xf8,0x00,0x00,0x00,0x00, ++0x24,0x63,0x00,0x01,0x03,0xe0,0x00,0x08,0xa4,0x43,0xff,0xf8,0x2c,0x42,0x00,0x10, ++0x10,0x40,0x00,0x07,0x00,0x05,0x10,0x40,0x27,0x84,0x83,0x9c,0x00,0x44,0x10,0x21, ++0x94,0x43,0xff,0xf8,0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,0xa4,0x43,0xff,0xf8, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8f,0x86,0x8b,0xc0,0x8f,0x82,0x80,0x14, ++0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x10,0x40,0x00,0x2a,0x00,0xc0,0x38,0x21, ++0x24,0x02,0x00,0x07,0x24,0x03,0xff,0x9c,0xa3,0x82,0x83,0x9b,0xa3,0x83,0x83,0x9a, ++0x27,0x8a,0x83,0x98,0x00,0x00,0x20,0x21,0x24,0x09,0x8f,0xff,0x00,0x04,0x10,0x80, ++0x00,0x4a,0x28,0x21,0x8c,0xa2,0x00,0x00,0x24,0xe3,0x00,0x04,0x24,0x88,0x00,0x01, ++0xac,0xe2,0x00,0x00,0x10,0x80,0x00,0x02,0x00,0x69,0x38,0x24,0xac,0xa0,0x00,0x00, ++0x31,0x04,0x00,0xff,0x2c,0x82,0x00,0x27,0x14,0x40,0xff,0xf5,0x00,0x04,0x10,0x80, ++0x97,0x83,0x8b,0xc6,0x97,0x85,0x8b,0xc4,0x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x9c, ++0x00,0xa2,0x28,0x21,0x3c,0x04,0xb0,0x06,0xa7,0x83,0x8b,0xc6,0x34,0x84,0x80,0x18, ++0xa4,0xa3,0x00,0x00,0x8c,0x85,0x00,0x00,0x24,0x02,0x8f,0xff,0x24,0xc6,0x00,0x9c, ++0x3c,0x03,0x0f,0x00,0x00,0xc2,0x30,0x24,0x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00, ++0xaf,0x86,0x8b,0xc0,0x10,0xa2,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x96, ++0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x18,0x8f,0x86,0x8b,0xc0,0x27,0xbd,0xff,0xc8,0x24,0x02,0x00,0x08, ++0x24,0x03,0x00,0x20,0xaf,0xbf,0x00,0x30,0xa3,0xa2,0x00,0x13,0xa3,0xa3,0x00,0x12, ++0xa7,0xa4,0x00,0x10,0x00,0xc0,0x28,0x21,0x27,0xa9,0x00,0x10,0x00,0x00,0x38,0x21, ++0x24,0x08,0x8f,0xff,0x00,0x07,0x10,0x80,0x00,0x49,0x10,0x21,0x8c,0x44,0x00,0x00, ++0x24,0xe3,0x00,0x01,0x30,0x67,0x00,0xff,0x24,0xa2,0x00,0x04,0x2c,0xe3,0x00,0x08, ++0xac,0xa4,0x00,0x00,0x14,0x60,0xff,0xf7,0x00,0x48,0x28,0x24,0x97,0x83,0x8b,0xc6, ++0x97,0x85,0x8b,0xc4,0x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x20,0x00,0xa2,0x28,0x21, ++0x3c,0x04,0xb0,0x06,0xa7,0x83,0x8b,0xc6,0x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00, ++0x8c,0x85,0x00,0x00,0x24,0x02,0x8f,0xff,0x24,0xc6,0x00,0x20,0x3c,0x03,0x0f,0x00, ++0x00,0xc2,0x30,0x24,0x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00,0xaf,0x86,0x8b,0xc0, ++0x10,0xa2,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x96,0x00,0x00,0x00,0x00, ++0x8f,0xbf,0x00,0x30,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38, ++0x93,0x82,0x8b,0xd0,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x11,0x24,0x06,0x00,0x01, ++0x8f,0x82,0x8b,0xc8,0x3c,0x05,0xb0,0x06,0x3c,0x04,0xb0,0x03,0x34,0xa5,0x80,0x18, ++0x34,0x84,0x01,0x08,0x14,0x40,0x00,0x09,0x00,0x00,0x30,0x21,0x97,0x82,0x8b,0xc4, ++0x8c,0x84,0x00,0x00,0x3c,0x03,0xb0,0x02,0x00,0x43,0x10,0x21,0xaf,0x84,0x8b,0xcc, ++0xa7,0x80,0x8b,0xc6,0xac,0x40,0x00,0x00,0xac,0x40,0x00,0x04,0x8c,0xa2,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x00,0xc0,0x10,0x21,0x8f,0x86,0x8b,0xc0,0x8f,0x82,0x8b,0xc8, ++0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x00,0xc0,0x40,0x21,0x14,0x40,0x00,0x0a, ++0x00,0x40,0x50,0x21,0x00,0x00,0x38,0x21,0x27,0x89,0x83,0x68,0x24,0xe2,0x00,0x01, ++0x00,0x07,0x18,0x80,0x30,0x47,0x00,0xff,0x00,0x69,0x18,0x21,0x2c,0xe2,0x00,0x0a, ++0x14,0x40,0xff,0xfa,0xac,0x60,0x00,0x00,0x3c,0x02,0x00,0x80,0x10,0x82,0x00,0x6f, ++0x00,0x00,0x00,0x00,0x97,0x82,0x83,0x6e,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01, ++0xa7,0x82,0x83,0x6e,0x90,0xa3,0x00,0x15,0x97,0x82,0x83,0x70,0x00,0x03,0x1e,0x00, ++0x00,0x03,0x1e,0x03,0x00,0x43,0x10,0x21,0xa7,0x82,0x83,0x70,0x8c,0xa4,0x00,0x20, ++0x3c,0x02,0x00,0x60,0x3c,0x03,0x00,0x20,0x00,0x82,0x20,0x24,0x10,0x83,0x00,0x54, ++0x00,0x00,0x00,0x00,0x14,0x80,0x00,0x47,0x00,0x00,0x00,0x00,0x97,0x82,0x83,0x74, ++0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xa7,0x82,0x83,0x74,0x84,0xa3,0x00,0x06, ++0x8f,0x82,0x83,0x84,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21,0xaf,0x82,0x83,0x84, ++0x25,0x42,0x00,0x01,0x28,0x43,0x27,0x10,0xaf,0x82,0x8b,0xc8,0x10,0x60,0x00,0x09, ++0x24,0x02,0x00,0x04,0x93,0x83,0x80,0x11,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x05, ++0x24,0x02,0x00,0x04,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x18,0x24,0x03,0x00,0x28,0xa3,0x83,0x83,0x6a,0xa3,0x82,0x83,0x6b, ++0x90,0xa2,0x00,0x18,0x93,0x83,0x83,0x93,0x00,0x00,0x38,0x21,0x00,0x02,0x16,0x00, ++0x00,0x02,0x16,0x03,0xa7,0x82,0x83,0x7e,0xa3,0x83,0x83,0x8c,0x27,0x89,0x83,0x68, ++0x24,0x05,0x8f,0xff,0x00,0x07,0x10,0x80,0x00,0x49,0x10,0x21,0x8c,0x44,0x00,0x00, ++0x24,0xe3,0x00,0x01,0x30,0x67,0x00,0xff,0x25,0x02,0x00,0x04,0x2c,0xe3,0x00,0x0a, ++0xad,0x04,0x00,0x00,0x14,0x60,0xff,0xf7,0x00,0x45,0x40,0x24,0x97,0x83,0x8b,0xc6, ++0x97,0x85,0x8b,0xc4,0x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x28,0x00,0xa2,0x28,0x21, ++0x3c,0x04,0xb0,0x06,0xa7,0x83,0x8b,0xc6,0x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00, ++0x8c,0x85,0x00,0x00,0x24,0x02,0x8f,0xff,0x24,0xc6,0x00,0x28,0x3c,0x03,0x0f,0x00, ++0x00,0xc2,0x30,0x24,0x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00,0xaf,0x86,0x8b,0xc0, ++0x10,0xa2,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x96,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x02,0x36,0x00,0x00,0x00,0x00,0xa3,0x80,0x80,0x11,0x08,0x00,0x02,0xe5, ++0x00,0x00,0x00,0x00,0x97,0x82,0x83,0x76,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01, ++0xa7,0x82,0x83,0x76,0x84,0xa3,0x00,0x06,0x8f,0x82,0x83,0x88,0x00,0x00,0x00,0x00, ++0x00,0x43,0x10,0x21,0xaf,0x82,0x83,0x88,0x08,0x00,0x02,0xdd,0x25,0x42,0x00,0x01, ++0x97,0x82,0x83,0x72,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xa7,0x82,0x83,0x72, ++0x84,0xa3,0x00,0x06,0x8f,0x82,0x83,0x80,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21, ++0xaf,0x82,0x83,0x80,0x08,0x00,0x02,0xdd,0x25,0x42,0x00,0x01,0x97,0x82,0x83,0x6c, ++0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xa7,0x82,0x83,0x6c,0x08,0x00,0x02,0xc5, ++0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xd0,0xaf,0xbf,0x00,0x28,0x8c,0xa3,0x00,0x20, ++0x8f,0x8a,0x8b,0xc0,0x3c,0x02,0x00,0x10,0x00,0x62,0x10,0x24,0x00,0xa0,0x38,0x21, ++0x01,0x40,0x48,0x21,0x10,0x40,0x00,0x3d,0x00,0x80,0x28,0x21,0x8c,0xe4,0x00,0x1c, ++0x34,0xa5,0x12,0x06,0xaf,0xa5,0x00,0x10,0x8c,0x82,0x00,0x08,0x00,0x03,0x1c,0x42, ++0x30,0x63,0x00,0x30,0x00,0x02,0x13,0x02,0x30,0x42,0x00,0x40,0x00,0x43,0x10,0x25, ++0x90,0xe6,0x00,0x10,0x90,0xe4,0x00,0x13,0x94,0xe8,0x00,0x0c,0x94,0xe3,0x00,0x1a, ++0x00,0x02,0x16,0x00,0x90,0xe7,0x00,0x12,0x00,0xa2,0x28,0x25,0x24,0x02,0x12,0x34, ++0xa7,0xa2,0x00,0x1c,0x24,0x02,0x56,0x78,0xaf,0xa5,0x00,0x10,0xa3,0xa6,0x00,0x18, ++0xa3,0xa7,0x00,0x1f,0xa7,0xa3,0x00,0x1a,0xa3,0xa4,0x00,0x19,0xa7,0xa8,0x00,0x20, ++0xa7,0xa2,0x00,0x22,0x00,0x00,0x28,0x21,0x27,0xa7,0x00,0x10,0x24,0x06,0x8f,0xff, ++0x00,0x05,0x10,0x80,0x00,0x47,0x10,0x21,0x8c,0x44,0x00,0x00,0x24,0xa3,0x00,0x01, ++0x30,0x65,0x00,0xff,0x25,0x22,0x00,0x04,0x2c,0xa3,0x00,0x05,0xad,0x24,0x00,0x00, ++0x14,0x60,0xff,0xf7,0x00,0x46,0x48,0x24,0x97,0x83,0x8b,0xc6,0x97,0x85,0x8b,0xc4, ++0x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x14,0x00,0xa2,0x28,0x21,0x3c,0x04,0xb0,0x06, ++0xa7,0x83,0x8b,0xc6,0x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00,0x8c,0x85,0x00,0x00, ++0x24,0x02,0x8f,0xff,0x25,0x46,0x00,0x14,0x3c,0x03,0x0f,0x00,0x00,0xc2,0x50,0x24, ++0x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00,0xaf,0x8a,0x8b,0xc0,0x10,0xa2,0x00,0x03, ++0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x96,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x28, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,0x3c,0x05,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xc8,0x00,0x04,0x22,0x00,0x34,0xa5,0x00,0x20, ++0x24,0x42,0x0d,0xfc,0x3c,0x03,0xb0,0x00,0xaf,0xb5,0x00,0x24,0xaf,0xb4,0x00,0x20, ++0xaf,0xb2,0x00,0x18,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x30,0x00,0x83,0x80,0x21, ++0xaf,0xb7,0x00,0x2c,0xaf,0xb6,0x00,0x28,0xaf,0xb3,0x00,0x1c,0xaf,0xb1,0x00,0x14, ++0xac,0xa2,0x00,0x00,0x8e,0x09,0x00,0x00,0x00,0x00,0x90,0x21,0x26,0x10,0x00,0x08, ++0x00,0x09,0xa6,0x02,0x12,0x80,0x00,0x13,0x00,0x00,0xa8,0x21,0x24,0x13,0x00,0x02, ++0x3c,0x16,0x00,0xff,0x3c,0x17,0xff,0x00,0x8e,0x09,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x09,0x12,0x02,0x24,0x42,0x00,0x02,0x31,0x25,0x00,0xff,0x10,0xb3,0x00,0x76, ++0x30,0x51,0x00,0xff,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x18,0x00,0x00,0x00,0x00, ++0x02,0x51,0x10,0x21,0x30,0x52,0xff,0xff,0x02,0x54,0x18,0x2b,0x14,0x60,0xff,0xf2, ++0x02,0x11,0x80,0x21,0x12,0xa0,0x00,0x0a,0x3c,0x02,0xb0,0x06,0x34,0x42,0x80,0x18, ++0x8c,0x43,0x00,0x00,0x3c,0x04,0x0f,0x00,0x3c,0x02,0x04,0x00,0x00,0x64,0x18,0x24, ++0x10,0x62,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x96,0x00,0x00,0x00,0x00, ++0x8f,0xbf,0x00,0x30,0x7b,0xb6,0x01,0x7c,0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0x8e,0x09,0x00,0x04, ++0x24,0x15,0x00,0x01,0x8e,0x06,0x00,0x0c,0x00,0x09,0x11,0x42,0x00,0x09,0x18,0xc2, ++0x30,0x48,0x00,0x03,0x00,0x09,0x14,0x02,0x30,0x6c,0x00,0x03,0x00,0x09,0x26,0x02, ++0x11,0x15,0x00,0x45,0x30,0x43,0x00,0x0f,0x29,0x02,0x00,0x02,0x14,0x40,0x00,0x26, ++0x00,0x00,0x00,0x00,0x11,0x13,0x00,0x0f,0x00,0x00,0x38,0x21,0x00,0x07,0x22,0x02, ++0x30,0x84,0xff,0x00,0x3c,0x03,0x00,0xff,0x00,0x07,0x2e,0x02,0x00,0x07,0x12,0x00, ++0x00,0x43,0x10,0x24,0x00,0xa4,0x28,0x25,0x00,0xa2,0x28,0x25,0x00,0x07,0x1e,0x00, ++0x00,0xa3,0x28,0x25,0x0c,0x00,0x01,0x92,0x01,0x20,0x20,0x21,0x08,0x00,0x03,0xa5, ++0x02,0x51,0x10,0x21,0x11,0x95,0x00,0x0f,0x00,0x00,0x00,0x00,0x11,0x88,0x00,0x07, ++0x00,0x00,0x00,0x00,0x00,0x04,0x10,0x80,0x27,0x83,0x8b,0x70,0x00,0x43,0x10,0x21, ++0x8c,0x47,0x00,0x18,0x08,0x00,0x03,0xcc,0x00,0x07,0x22,0x02,0x00,0x04,0x10,0x40, ++0x27,0x83,0x8b,0x78,0x00,0x43,0x10,0x21,0x94,0x47,0x00,0x02,0x08,0x00,0x03,0xcc, ++0x00,0x07,0x22,0x02,0x27,0x82,0x8b,0x70,0x00,0x82,0x10,0x21,0x90,0x47,0x00,0x00, ++0x08,0x00,0x03,0xcc,0x00,0x07,0x22,0x02,0x15,0x00,0xff,0xdc,0x00,0x00,0x38,0x21, ++0x10,0x75,0x00,0x05,0x00,0x80,0x38,0x21,0x00,0x65,0x18,0x26,0x24,0x82,0x01,0x00, ++0x00,0x00,0x38,0x21,0x00,0x43,0x38,0x0a,0x24,0x02,0x00,0x01,0x11,0x82,0x00,0x0e, ++0x3c,0x02,0xb0,0x03,0x24,0x02,0x00,0x02,0x11,0x82,0x00,0x06,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xb0,0x03,0x00,0xe2,0x10,0x21,0x8c,0x47,0x00,0x00,0x08,0x00,0x03,0xcc, ++0x00,0x07,0x22,0x02,0x3c,0x02,0xb0,0x03,0x00,0xe2,0x10,0x21,0x94,0x43,0x00,0x00, ++0x08,0x00,0x03,0xcb,0x30,0x67,0xff,0xff,0x00,0xe2,0x10,0x21,0x90,0x43,0x00,0x00, ++0x08,0x00,0x03,0xcb,0x30,0x67,0x00,0xff,0x30,0x62,0x00,0x03,0x00,0x02,0x12,0x00, ++0x11,0x95,0x00,0x07,0x00,0x44,0x38,0x21,0x11,0x93,0x00,0x03,0x00,0x00,0x00,0x00, ++0x08,0x00,0x03,0xfd,0x3c,0x02,0xb0,0x0a,0x08,0x00,0x04,0x02,0x3c,0x02,0xb0,0x0a, ++0x08,0x00,0x04,0x06,0x3c,0x02,0xb0,0x0a,0x8e,0x09,0x00,0x04,0x8e,0x02,0x00,0x08, ++0x8e,0x03,0x00,0x0c,0x00,0x09,0x41,0x42,0x00,0x02,0x22,0x02,0x00,0x03,0x3a,0x02, ++0x30,0x84,0xff,0x00,0x30,0xe7,0xff,0x00,0x00,0x02,0x5e,0x02,0x00,0x02,0x32,0x00, ++0x00,0x03,0x56,0x02,0x00,0x03,0x2a,0x00,0x01,0x64,0x58,0x25,0x00,0xd6,0x30,0x24, ++0x01,0x47,0x50,0x25,0x00,0x02,0x16,0x00,0x00,0xb6,0x28,0x24,0x00,0x03,0x1e,0x00, ++0x01,0x66,0x58,0x25,0x01,0x45,0x50,0x25,0x00,0x57,0x10,0x24,0x00,0x77,0x18,0x24, ++0x01,0x62,0x38,0x25,0x01,0x43,0x30,0x25,0x00,0x09,0x10,0xc2,0x00,0x09,0x1c,0x02, ++0x31,0x08,0x00,0x03,0x30,0x4c,0x00,0x03,0x30,0x63,0x00,0x0f,0x00,0x09,0x26,0x02, ++0x00,0xe0,0x58,0x21,0x15,0x00,0x00,0x28,0x00,0xc0,0x50,0x21,0x24,0x02,0x00,0x01, ++0x10,0x62,0x00,0x06,0x00,0x80,0x28,0x21,0x24,0x02,0x00,0x03,0x14,0x62,0xff,0x69, ++0x02,0x51,0x10,0x21,0x24,0x85,0x01,0x00,0x24,0x02,0x00,0x01,0x11,0x82,0x00,0x15, ++0x24,0x02,0x00,0x02,0x11,0x82,0x00,0x0a,0x3c,0x03,0xb0,0x03,0x00,0xa3,0x18,0x21, ++0x8c,0x62,0x00,0x00,0x00,0x0a,0x20,0x27,0x01,0x6a,0x28,0x24,0x00,0x44,0x10,0x24, ++0x00,0x45,0x10,0x25,0xac,0x62,0x00,0x00,0x08,0x00,0x03,0xa5,0x02,0x51,0x10,0x21, ++0x00,0xa3,0x18,0x21,0x94,0x62,0x00,0x00,0x00,0x0a,0x20,0x27,0x01,0x6a,0x28,0x24, ++0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25,0xa4,0x62,0x00,0x00,0x08,0x00,0x03,0xa5, ++0x02,0x51,0x10,0x21,0x3c,0x03,0xb0,0x03,0x00,0xa3,0x18,0x21,0x90,0x62,0x00,0x00, ++0x00,0x0a,0x20,0x27,0x01,0x6a,0x28,0x24,0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25, ++0x08,0x00,0x03,0xa4,0xa0,0x62,0x00,0x00,0x24,0x02,0x00,0x01,0x11,0x02,0x00,0x21, ++0x00,0x00,0x00,0x00,0x15,0x13,0xff,0x42,0x00,0x00,0x00,0x00,0x11,0x82,0x00,0x17, ++0x00,0x00,0x00,0x00,0x11,0x88,0x00,0x0b,0x00,0x00,0x00,0x00,0x27,0x83,0x8b,0x70, ++0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x18,0x00,0x06,0x18,0x27, ++0x00,0xe6,0x28,0x24,0x00,0x43,0x10,0x24,0x00,0x45,0x10,0x25,0x08,0x00,0x03,0xa4, ++0xac,0x82,0x00,0x18,0x27,0x83,0x8b,0x78,0x00,0x04,0x20,0x40,0x00,0x83,0x20,0x21, ++0x94,0x82,0x00,0x02,0x00,0x06,0x18,0x27,0x00,0xe6,0x28,0x24,0x00,0x43,0x10,0x24, ++0x00,0x45,0x10,0x25,0x08,0x00,0x03,0xa4,0xa4,0x82,0x00,0x02,0x27,0x83,0x8b,0x70, ++0x00,0x83,0x18,0x21,0x90,0x62,0x00,0x00,0x00,0x06,0x20,0x27,0x08,0x00,0x04,0x5a, ++0x00,0xe6,0x28,0x24,0x30,0x62,0x00,0x07,0x00,0x02,0x12,0x00,0x11,0x88,0x00,0x0f, ++0x00,0x44,0x10,0x21,0x11,0x93,0x00,0x07,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x0a, ++0x00,0x43,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x06,0x20,0x27,0x08,0x00,0x04,0x47, ++0x00,0xe6,0x28,0x24,0x3c,0x03,0xb0,0x0a,0x00,0x43,0x18,0x21,0x94,0x62,0x00,0x00, ++0x00,0x06,0x20,0x27,0x08,0x00,0x04,0x50,0x00,0xe6,0x28,0x24,0x3c,0x03,0xb0,0x0a, ++0x08,0x00,0x04,0x7d,0x00,0x43,0x18,0x21,0x97,0x85,0x8b,0xc4,0x3c,0x07,0xb0,0x02, ++0x3c,0x04,0xb0,0x03,0x3c,0x02,0x80,0x00,0x00,0xa7,0x28,0x21,0x34,0x84,0x00,0x20, ++0x24,0x42,0x12,0x58,0x24,0x03,0xff,0x80,0xac,0x82,0x00,0x00,0xa0,0xa3,0x00,0x07, ++0x97,0x82,0x8b,0xc6,0x97,0x85,0x8b,0xc4,0x3c,0x06,0xb0,0x06,0x30,0x42,0xff,0xf8, ++0x24,0x42,0x00,0x10,0x00,0xa2,0x10,0x21,0x30,0x42,0x0f,0xff,0x24,0x44,0x00,0x08, ++0x30,0x84,0x0f,0xff,0x00,0x05,0x28,0xc2,0x3c,0x03,0x00,0x40,0x00,0xa3,0x28,0x25, ++0x00,0x87,0x20,0x21,0x34,0xc6,0x80,0x18,0xac,0xc5,0x00,0x00,0xaf,0x84,0x8b,0xc0, ++0xa7,0x82,0x8b,0xc4,0xa7,0x80,0x8b,0xc6,0xaf,0x80,0x8b,0xc8,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x30,0xa5,0x00,0xff,0x30,0x84,0x00,0xff,0x24,0x02,0x00,0x01, ++0x00,0xe0,0x48,0x21,0x30,0xc6,0x00,0xff,0x8f,0xa7,0x00,0x10,0x10,0x82,0x00,0x07, ++0x00,0xa0,0x40,0x21,0x24,0x02,0x00,0x03,0x10,0x82,0x00,0x03,0x00,0x00,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x24,0xa8,0x01,0x00,0x3c,0x03,0xb0,0x03, ++0x24,0x02,0x00,0x01,0x00,0x07,0x20,0x27,0x01,0x27,0x28,0x24,0x10,0xc2,0x00,0x14, ++0x01,0x03,0x18,0x21,0x24,0x02,0x00,0x02,0x10,0xc2,0x00,0x09,0x00,0x07,0x50,0x27, ++0x3c,0x03,0xb0,0x03,0x01,0x03,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x4a,0x10,0x24,0x00,0x45,0x10,0x25,0x08,0x00,0x04,0xe1,0xac,0x62,0x00,0x00, ++0x3c,0x03,0xb0,0x03,0x01,0x03,0x18,0x21,0x94,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x4a,0x10,0x24,0x00,0x45,0x10,0x25,0x03,0xe0,0x00,0x08,0xa4,0x62,0x00,0x00, ++0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25, ++0xa0,0x62,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0x84,0x00,0x07, ++0x00,0x04,0x22,0x00,0x30,0xa5,0x00,0xff,0x00,0x85,0x28,0x21,0x3c,0x02,0xb0,0x0a, ++0x00,0xa2,0x40,0x21,0x30,0xc6,0x00,0xff,0x24,0x02,0x00,0x01,0x8f,0xa4,0x00,0x10, ++0x10,0xc2,0x00,0x14,0x24,0x02,0x00,0x02,0x00,0x04,0x50,0x27,0x10,0xc2,0x00,0x09, ++0x00,0xe4,0x48,0x24,0x3c,0x03,0xb0,0x0a,0x00,0xa3,0x18,0x21,0x8c,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,0x00,0x49,0x10,0x25,0x03,0xe0,0x00,0x08, ++0xac,0x62,0x00,0x00,0x3c,0x03,0xb0,0x0a,0x00,0xa3,0x18,0x21,0x94,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,0x00,0x49,0x10,0x25,0x03,0xe0,0x00,0x08, ++0xa4,0x62,0x00,0x00,0x91,0x02,0x00,0x00,0x00,0x04,0x18,0x27,0x00,0xe4,0x20,0x24, ++0x00,0x43,0x10,0x24,0x00,0x44,0x10,0x25,0x03,0xe0,0x00,0x08,0xa1,0x02,0x00,0x00, ++0x30,0xa9,0x00,0xff,0x27,0x83,0x8b,0x70,0x30,0x85,0x00,0xff,0x24,0x02,0x00,0x01, ++0x00,0x07,0x50,0x27,0x00,0xc7,0x40,0x24,0x11,0x22,0x00,0x17,0x00,0xa3,0x18,0x21, ++0x00,0x05,0x20,0x40,0x27,0x82,0x8b,0x70,0x00,0x05,0x28,0x80,0x27,0x83,0x8b,0x78, ++0x00,0x83,0x50,0x21,0x00,0xa2,0x20,0x21,0x24,0x02,0x00,0x02,0x00,0x07,0x40,0x27, ++0x11,0x22,0x00,0x07,0x00,0xc7,0x28,0x24,0x8c,0x82,0x00,0x18,0x00,0x00,0x00,0x00, ++0x00,0x48,0x10,0x24,0x00,0x45,0x10,0x25,0x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x18, ++0x95,0x42,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x48,0x10,0x24,0x00,0x45,0x10,0x25, ++0x03,0xe0,0x00,0x08,0xa5,0x42,0x00,0x02,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x4a,0x10,0x24,0x00,0x48,0x10,0x25,0x03,0xe0,0x00,0x08,0xa0,0x62,0x00,0x00, ++0x00,0x04,0x32,0x02,0x30,0xc6,0xff,0x00,0x00,0x04,0x16,0x02,0x00,0x04,0x1a,0x00, ++0x3c,0x05,0x00,0xff,0x00,0x65,0x18,0x24,0x00,0x46,0x10,0x25,0x00,0x43,0x10,0x25, ++0x00,0x04,0x26,0x00,0x03,0xe0,0x00,0x08,0x00,0x44,0x10,0x25,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xe8,0x34,0x63,0x00,0x20,0x24,0x42,0x14,0xdc, ++0x3c,0x04,0xb0,0x03,0xaf,0xbf,0x00,0x14,0xac,0x62,0x00,0x00,0xaf,0xb0,0x00,0x10, ++0x34,0x84,0x00,0x2c,0x8c,0x83,0x00,0x00,0xa7,0x80,0xbc,0x00,0x00,0x03,0x12,0x02, ++0x00,0x03,0x2d,0x02,0x30,0x42,0x0f,0xff,0xa3,0x83,0xbc,0x08,0xa7,0x85,0xbc,0x0c, ++0xa7,0x82,0xbc,0x0a,0xa7,0x80,0xbc,0x02,0xa7,0x80,0xbc,0x04,0xa7,0x80,0xbc,0x06, ++0x0c,0x00,0x06,0xd1,0x24,0x04,0x05,0x00,0x3c,0x05,0x08,0x00,0x00,0x45,0x28,0x25, ++0x24,0x04,0x05,0x00,0x0c,0x00,0x06,0xbf,0x00,0x40,0x80,0x21,0x3c,0x02,0xf7,0xff, ++0x34,0x42,0xff,0xff,0x02,0x02,0x80,0x24,0x02,0x00,0x28,0x21,0x0c,0x00,0x06,0xbf, ++0x24,0x04,0x05,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0xb0,0x03,0x34,0x42,0x01,0x08, ++0x34,0x63,0x01,0x18,0x8c,0x45,0x00,0x00,0x8c,0x64,0x00,0x00,0x3c,0x02,0x00,0x0f, ++0x3c,0x03,0x00,0x4c,0x30,0x84,0x02,0x00,0x34,0x63,0x4b,0x40,0xaf,0x85,0xbc,0x10, ++0x10,0x80,0x00,0x06,0x34,0x42,0x42,0x40,0xaf,0x83,0xbc,0x14,0x8f,0xbf,0x00,0x14, ++0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0xaf,0x82,0xbc,0x14, ++0x08,0x00,0x05,0x67,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00, ++0x27,0xbd,0xff,0xc8,0x34,0x63,0x00,0x20,0x24,0x42,0x15,0xb8,0x30,0x84,0x00,0xff, ++0xaf,0xbf,0x00,0x30,0xaf,0xb7,0x00,0x2c,0xaf,0xb6,0x00,0x28,0xaf,0xb5,0x00,0x24, ++0xaf,0xb4,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14, ++0xaf,0xb0,0x00,0x10,0xac,0x62,0x00,0x00,0x10,0x80,0x00,0x1c,0x24,0x02,0x00,0x02, ++0x10,0x82,0x00,0x08,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x30,0x7b,0xb6,0x01,0x7c, ++0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x38,0xa7,0x80,0xbc,0x00,0xa7,0x80,0xbc,0x02,0xa7,0x80,0xbc,0x04, ++0xa7,0x80,0xbc,0x06,0x0c,0x00,0x06,0xd1,0x24,0x04,0x05,0x00,0x3c,0x05,0x08,0x00, ++0x00,0x45,0x28,0x25,0x24,0x04,0x05,0x00,0x0c,0x00,0x06,0xbf,0x00,0x40,0x80,0x21, ++0x3c,0x05,0xf7,0xff,0x34,0xa5,0xff,0xff,0x02,0x05,0x28,0x24,0x0c,0x00,0x06,0xbf, ++0x24,0x04,0x05,0x00,0x08,0x00,0x05,0x82,0x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xd1, ++0x24,0x04,0x05,0xa0,0x24,0x04,0x05,0xa4,0x0c,0x00,0x06,0xd1,0x00,0x02,0xbc,0x02, ++0x24,0x04,0x05,0xa8,0x00,0x02,0xb4,0x02,0x0c,0x00,0x06,0xd1,0x30,0x55,0xff,0xff, ++0x00,0x40,0x80,0x21,0x97,0x84,0xbc,0x00,0x97,0x82,0xbc,0x02,0x97,0x83,0xbc,0x06, ++0x02,0xe4,0x20,0x23,0x02,0xa2,0x10,0x23,0x00,0x82,0x20,0x21,0x97,0x82,0xbc,0x04, ++0x32,0x14,0xff,0xff,0x02,0x83,0x18,0x23,0x02,0xc2,0x10,0x23,0x00,0x82,0x20,0x21, ++0x93,0x82,0xbc,0x08,0x00,0x83,0x20,0x21,0x30,0x84,0xff,0xff,0x00,0x82,0x10,0x2b, ++0x14,0x40,0x00,0xaa,0x00,0x00,0x00,0x00,0x97,0x82,0xbc,0x0c,0x00,0x00,0x00,0x00, ++0x00,0x44,0x10,0x2b,0x14,0x40,0x00,0x7f,0x00,0x00,0x00,0x00,0x97,0x82,0xbc,0x0a, ++0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x2b,0x10,0x40,0x00,0x3a,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x06,0xd1,0x24,0x04,0x04,0x50,0x30,0x51,0x00,0x7f,0x00,0x40,0x80,0x21, ++0x2e,0x22,0x00,0x32,0x10,0x40,0x00,0x13,0x24,0x02,0x00,0x20,0x12,0x22,0x00,0x17, ++0x24,0x02,0xff,0x80,0x02,0x02,0x10,0x24,0x26,0x31,0x00,0x01,0x00,0x51,0x80,0x25, ++0x02,0x00,0x28,0x21,0x0c,0x00,0x06,0xbf,0x24,0x04,0x04,0x50,0x02,0x00,0x28,0x21, ++0x0c,0x00,0x06,0xbf,0x24,0x04,0x04,0x58,0x02,0x00,0x28,0x21,0x0c,0x00,0x06,0xbf, ++0x24,0x04,0x04,0x60,0x02,0x00,0x28,0x21,0x24,0x04,0x04,0x68,0x0c,0x00,0x06,0xbf, ++0x00,0x00,0x00,0x00,0xa7,0x97,0xbc,0x00,0xa7,0x95,0xbc,0x02,0xa7,0x96,0xbc,0x04, ++0xa7,0x94,0xbc,0x06,0x08,0x00,0x05,0x82,0x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xd1, ++0x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0,0x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24, ++0x00,0x02,0x15,0x82,0x24,0x03,0x00,0x03,0x10,0x43,0x00,0x07,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25, ++0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x08,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x2c, ++0x00,0x40,0x90,0x21,0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24, ++0x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x2c,0x08,0x00,0x05,0xc9, ++0x24,0x02,0xff,0x80,0x0c,0x00,0x06,0xd1,0x24,0x04,0x04,0x50,0x30,0x51,0x00,0x7f, ++0x24,0x02,0x00,0x20,0x16,0x22,0xff,0xdb,0x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xd1, ++0x24,0x04,0x02,0x2c,0x34,0x52,0x40,0x00,0x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xbf, ++0x24,0x04,0x02,0x2c,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x58,0x24,0x04,0x02,0x5c, ++0x0c,0x00,0x06,0xd1,0x00,0x02,0x9e,0x02,0x30,0x43,0x00,0xff,0x00,0x13,0x12,0x00, ++0x00,0x43,0x10,0x25,0x2c,0x43,0x00,0x04,0x14,0x60,0x00,0x1d,0x2c,0x42,0x00,0x11, ++0x10,0x40,0x00,0x0b,0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff, ++0x02,0x42,0x90,0x24,0x02,0x40,0x28,0x21,0x24,0x04,0x02,0x2c,0x0c,0x00,0x06,0xbf, ++0x36,0x52,0x80,0x00,0x02,0x40,0x28,0x21,0x08,0x00,0x05,0xd7,0x24,0x04,0x02,0x2c, ++0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0,0x00,0x40,0x28,0x21, ++0x00,0x44,0x10,0x24,0x00,0x02,0x15,0x82,0x24,0x03,0x00,0x02,0x14,0x43,0xff,0xee, ++0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25, ++0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x08,0x08,0x00,0x06,0x13,0x3c,0x02,0xff,0xff, ++0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x08,0x00,0x40,0x28,0x21,0x00,0x02,0x15,0x82, ++0x30,0x42,0x00,0x03,0x24,0x03,0x00,0x03,0x14,0x43,0xff,0xdf,0x3c,0x02,0xff,0x3f, ++0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,0x3c,0x03,0x00,0x80,0x08,0x00,0x06,0x28, ++0x00,0x43,0x28,0x25,0x0c,0x00,0x06,0xd1,0x24,0x04,0x04,0x50,0x30,0x51,0x00,0x7f, ++0x00,0x40,0x80,0x21,0x2e,0x22,0x00,0x32,0x10,0x40,0xff,0x9a,0x24,0x02,0x00,0x20, ++0x12,0x22,0x00,0x04,0x24,0x02,0xff,0x80,0x02,0x02,0x10,0x24,0x08,0x00,0x05,0xcb, ++0x26,0x31,0x00,0x02,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0, ++0x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24,0x00,0x02,0x15,0x82,0x24,0x03,0x00,0x03, ++0x10,0x43,0x00,0x07,0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff, ++0x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x08, ++0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x2c,0x00,0x40,0x90,0x21,0x3c,0x02,0xff,0xff, ++0x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24,0x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xbf, ++0x24,0x04,0x02,0x2c,0x08,0x00,0x06,0x42,0x24,0x02,0xff,0x80,0x0c,0x00,0x06,0xd1, ++0x24,0x04,0x04,0x50,0x00,0x40,0x80,0x21,0x30,0x51,0x00,0x7f,0x24,0x02,0x00,0x20, ++0x12,0x22,0x00,0x1d,0x2e,0x22,0x00,0x21,0x14,0x40,0xff,0x72,0x24,0x02,0xff,0x80, ++0x02,0x02,0x10,0x24,0x26,0x31,0xff,0xff,0x00,0x51,0x80,0x25,0x24,0x04,0x04,0x50, ++0x0c,0x00,0x06,0xbf,0x02,0x00,0x28,0x21,0x24,0x04,0x04,0x58,0x0c,0x00,0x06,0xbf, ++0x02,0x00,0x28,0x21,0x24,0x04,0x04,0x60,0x0c,0x00,0x06,0xbf,0x02,0x00,0x28,0x21, ++0x02,0x00,0x28,0x21,0x0c,0x00,0x06,0xbf,0x24,0x04,0x04,0x68,0x24,0x02,0x00,0x20, ++0x16,0x22,0xff,0x60,0x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x2c, ++0x00,0x40,0x90,0x21,0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,0x02,0x42,0x10,0x24, ++0x08,0x00,0x06,0x19,0x34,0x52,0x80,0x00,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x2c, ++0x34,0x52,0x40,0x00,0x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x2c, ++0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x58,0x24,0x04,0x02,0x5c,0x0c,0x00,0x06,0xd1, ++0x00,0x02,0x9e,0x02,0x30,0x43,0x00,0xff,0x00,0x13,0x12,0x00,0x00,0x43,0x10,0x25, ++0x2c,0x43,0x00,0x04,0x14,0x60,0x00,0x20,0x2c,0x42,0x00,0x11,0x10,0x40,0x00,0x0d, ++0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24, ++0x02,0x40,0x28,0x21,0x24,0x04,0x02,0x2c,0x0c,0x00,0x06,0xbf,0x36,0x52,0x80,0x00, ++0x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x2c,0x08,0x00,0x06,0x66, ++0x2e,0x22,0x00,0x21,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0, ++0x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24,0x00,0x02,0x15,0x82,0x24,0x03,0x00,0x02, ++0x14,0x43,0xff,0xec,0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff, ++0x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x08, ++0x08,0x00,0x06,0x96,0x3c,0x02,0xff,0xff,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x08, ++0x00,0x40,0x28,0x21,0x00,0x02,0x15,0x82,0x30,0x42,0x00,0x03,0x24,0x03,0x00,0x03, ++0x14,0x43,0xff,0xdc,0x3c,0x03,0x00,0x80,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff, ++0x00,0xa2,0x10,0x24,0x08,0x00,0x06,0xae,0x00,0x43,0x28,0x25,0x30,0x83,0x00,0x03, ++0x00,0x04,0x20,0x40,0x00,0x83,0x20,0x23,0x3c,0x02,0xb0,0x0a,0x00,0x82,0x20,0x21, ++0x3c,0x06,0x00,0x01,0xac,0x85,0x00,0x00,0x24,0x07,0x00,0x01,0x00,0x00,0x28,0x21, ++0x34,0xc6,0x86,0x9f,0x8c,0x82,0x10,0x00,0x24,0xa5,0x00,0x01,0x10,0x47,0x00,0x03, ++0x00,0xc5,0x18,0x2b,0x10,0x60,0xff,0xfb,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x30,0x83,0x00,0x03,0x00,0x04,0x20,0x40,0x3c,0x02,0xb0,0x0a, ++0x00,0x83,0x20,0x23,0x00,0x82,0x20,0x21,0x3c,0x06,0x00,0x01,0x24,0x02,0xff,0xff, ++0xac,0x82,0x10,0x00,0x00,0x00,0x28,0x21,0x24,0x07,0x00,0x01,0x34,0xc6,0x86,0x9f, ++0x8c,0x82,0x10,0x00,0x24,0xa5,0x00,0x01,0x10,0x47,0x00,0x03,0x00,0xc5,0x18,0x2b, ++0x10,0x60,0xff,0xfb,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x3c,0x05,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x1b,0x94, ++0x24,0x03,0x00,0x01,0x34,0xa5,0x00,0x20,0x3c,0x06,0xb0,0x03,0xac,0xa2,0x00,0x00, ++0x34,0xc6,0x01,0x04,0xa0,0x83,0x00,0x48,0xa0,0x80,0x00,0x04,0xa0,0x80,0x00,0x05, ++0xa0,0x80,0x00,0x06,0xa0,0x80,0x00,0x07,0xa0,0x80,0x00,0x08,0xa0,0x80,0x00,0x09, ++0xa0,0x80,0x00,0x0a,0xa0,0x80,0x00,0x11,0xa0,0x80,0x00,0x13,0xa0,0x80,0x00,0x49, ++0x94,0xc2,0x00,0x00,0xac,0x80,0x00,0x00,0xa0,0x80,0x00,0x4e,0x00,0x02,0x14,0x00, ++0x00,0x02,0x14,0x03,0x30,0x43,0x00,0xff,0x30,0x42,0xff,0x00,0xa4,0x82,0x00,0x44, ++0xa4,0x83,0x00,0x46,0xac,0x80,0x00,0x24,0xac,0x80,0x00,0x28,0xac,0x80,0x00,0x2c, ++0xac,0x80,0x00,0x30,0xac,0x80,0x00,0x34,0xac,0x80,0x00,0x38,0xac,0x80,0x00,0x3c, ++0x03,0xe0,0x00,0x08,0xac,0x80,0x00,0x40,0x84,0x83,0x00,0x0c,0x3c,0x07,0xb0,0x03, ++0x34,0xe7,0x00,0x20,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80, ++0x27,0x83,0x90,0x04,0x00,0x43,0x10,0x21,0x8c,0x48,0x00,0x18,0x3c,0x02,0x80,0x00, ++0x24,0x42,0x1c,0x28,0xac,0xe2,0x00,0x00,0x8d,0x03,0x00,0x08,0x80,0x82,0x00,0x13, ++0x00,0x05,0x2c,0x00,0x00,0x03,0x1e,0x02,0x00,0x02,0x12,0x00,0x30,0x63,0x00,0x7e, ++0x00,0x62,0x18,0x21,0x00,0x65,0x18,0x21,0x3c,0x02,0xc0,0x00,0x3c,0x05,0xb0,0x05, ++0x34,0x42,0x04,0x00,0x24,0x63,0x00,0x01,0x3c,0x07,0xb0,0x05,0x3c,0x08,0xb0,0x05, ++0x34,0xa5,0x04,0x20,0xac,0xa3,0x00,0x00,0x00,0xc2,0x30,0x21,0x34,0xe7,0x04,0x24, ++0x35,0x08,0x02,0x28,0x24,0x02,0x00,0x01,0x24,0x03,0x00,0x20,0xac,0xe6,0x00,0x00, ++0xac,0x82,0x00,0x3c,0x03,0xe0,0x00,0x08,0xa1,0x03,0x00,0x00,0x27,0xbd,0xff,0xa8, ++0x00,0x07,0x60,0x80,0x27,0x82,0xb4,0x00,0xaf,0xbe,0x00,0x50,0xaf,0xb7,0x00,0x4c, ++0xaf,0xb5,0x00,0x44,0xaf,0xb4,0x00,0x40,0xaf,0xbf,0x00,0x54,0xaf,0xb6,0x00,0x48, ++0xaf,0xb3,0x00,0x3c,0xaf,0xb2,0x00,0x38,0xaf,0xb1,0x00,0x34,0xaf,0xb0,0x00,0x30, ++0x01,0x82,0x10,0x21,0x8c,0x43,0x00,0x00,0x00,0xe0,0x70,0x21,0x3c,0x02,0x80,0x00, ++0x94,0x73,0x00,0x14,0x3c,0x07,0xb0,0x03,0x34,0xe7,0x00,0x20,0x24,0x42,0x1c,0xbc, ++0x3c,0x03,0xb0,0x05,0xac,0xe2,0x00,0x00,0x34,0x63,0x01,0x28,0x90,0x67,0x00,0x00, ++0x00,0x13,0xa8,0xc0,0x02,0xb3,0x18,0x21,0x27,0x82,0x90,0x04,0x00,0x03,0x18,0x80, ++0x00,0x62,0x18,0x21,0x00,0x05,0x2c,0x00,0x00,0x07,0x3e,0x00,0x28,0xc2,0x00,0x03, ++0x00,0xc0,0xa0,0x21,0x00,0x80,0x78,0x21,0x00,0x05,0xbc,0x03,0x8c,0x68,0x00,0x18, ++0x02,0xa0,0x58,0x21,0x10,0x40,0x01,0x81,0x00,0x07,0xf6,0x03,0x00,0xde,0x10,0x07, ++0x30,0x5e,0x00,0x01,0x01,0x73,0x10,0x21,0x27,0x83,0x90,0x08,0x00,0x02,0x10,0x80, ++0x00,0x43,0x10,0x21,0x80,0x4d,0x00,0x06,0x8d,0x03,0x00,0x00,0x8d,0x02,0x00,0x04, ++0x8d,0x0a,0x00,0x08,0x8d,0x03,0x00,0x0c,0xaf,0xa2,0x00,0x20,0x11,0xa0,0x01,0x71, ++0xaf,0xa3,0x00,0x18,0x27,0x82,0xb4,0x00,0x01,0x82,0x10,0x21,0x8c,0x44,0x00,0x00, ++0x00,0x00,0x00,0x00,0x90,0x83,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x04, ++0x14,0x60,0x00,0x12,0x00,0x00,0xb0,0x21,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x46, ++0x90,0x43,0x00,0x00,0x2a,0x84,0x00,0x04,0x10,0x80,0x01,0x56,0x30,0x65,0x00,0x01, ++0x91,0xe2,0x00,0x09,0x00,0x00,0x00,0x00,0x12,0x82,0x00,0x02,0x00,0x00,0x00,0x00, ++0x00,0x00,0x28,0x21,0x14,0xa0,0x00,0x03,0x00,0x00,0x38,0x21,0x13,0xc0,0x00,0x03, ++0x38,0xf6,0x00,0x01,0x24,0x07,0x00,0x01,0x38,0xf6,0x00,0x01,0x01,0x73,0x10,0x21, ++0x00,0x02,0x30,0x80,0x27,0x83,0x90,0x10,0x00,0xc3,0x48,0x21,0x91,0x25,0x00,0x00, ++0x8f,0xa4,0x00,0x20,0x2c,0xa3,0x00,0x04,0x00,0x04,0x11,0xc3,0x30,0x42,0x00,0x01, ++0x00,0x03,0xb0,0x0b,0x12,0xc0,0x00,0xd8,0xaf,0xa2,0x00,0x24,0x93,0x90,0xbb,0xea, ++0x00,0x0a,0x16,0x42,0x30,0x52,0x00,0x3f,0x2e,0x06,0x00,0x0c,0x10,0xc0,0x00,0xc0, ++0x00,0xa0,0x20,0x21,0x2c,0xa2,0x00,0x10,0x14,0x40,0x00,0x04,0x00,0x90,0x10,0x2b, ++0x30,0xa2,0x00,0x07,0x24,0x44,0x00,0x04,0x00,0x90,0x10,0x2b,0x10,0x40,0x00,0x0b, ++0x01,0x73,0x10,0x21,0x27,0x85,0xbb,0x1c,0x00,0x10,0x10,0x40,0x00,0x50,0x10,0x21, ++0x00,0x45,0x10,0x21,0x90,0x50,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x18,0x2b, ++0x14,0x60,0xff,0xfa,0x00,0x10,0x10,0x40,0x01,0x73,0x10,0x21,0x00,0x02,0x10,0x80, ++0x27,0x83,0x90,0x08,0x00,0x43,0x10,0x21,0x31,0xa4,0x00,0x01,0x10,0x80,0x00,0xa5, ++0xa0,0x50,0x00,0x07,0x3c,0x04,0xb0,0x05,0x34,0x84,0x00,0x08,0x24,0x02,0x00,0x01, ++0x3c,0x03,0x80,0x00,0xa1,0xe2,0x00,0x4e,0xac,0x83,0x00,0x00,0x8c,0x85,0x00,0x00, ++0x3c,0x02,0x00,0xf0,0x3c,0x03,0x40,0xf0,0x34,0x42,0xf0,0x00,0x34,0x63,0xf0,0x00, ++0x24,0x17,0x00,0x0e,0x24,0x13,0x01,0x06,0xac,0x82,0x00,0x00,0xac,0x83,0x00,0x00, ++0x27,0x82,0xb4,0x00,0x01,0x82,0x10,0x21,0x8c,0x43,0x00,0x00,0x24,0x05,0x00,0x01, ++0xaf,0xa5,0x00,0x1c,0x90,0x62,0x00,0x16,0x00,0x13,0xa8,0xc0,0x32,0x51,0x00,0x02, ++0x34,0x42,0x00,0x04,0xa0,0x62,0x00,0x16,0x8f,0xa3,0x00,0x20,0x8f,0xa4,0x00,0x18, ++0x00,0x03,0x13,0x43,0x00,0x04,0x1a,0x02,0x30,0x47,0x00,0x01,0x12,0x20,0x00,0x04, ++0x30,0x64,0x07,0xff,0x2e,0x03,0x00,0x04,0x32,0x42,0x00,0x33,0x00,0x43,0x90,0x0b, ++0x8f,0xa5,0x00,0x24,0x8f,0xa6,0x00,0x1c,0x00,0x12,0x10,0x40,0x00,0x05,0x19,0xc0, ++0x00,0x47,0x10,0x21,0x00,0x06,0x2a,0x80,0x00,0x43,0x10,0x21,0x00,0x10,0x32,0x00, ++0x00,0x04,0x24,0x80,0x02,0x65,0x28,0x21,0x00,0xa4,0x28,0x21,0x00,0x46,0x10,0x21, ++0x00,0x17,0x1c,0x00,0x3c,0x04,0xc0,0x00,0x00,0x43,0x30,0x21,0x16,0x80,0x00,0x29, ++0x00,0xa4,0x28,0x21,0x3c,0x02,0xb0,0x05,0x34,0x42,0x04,0x00,0x3c,0x03,0xb0,0x05, ++0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x04,0x34,0x84,0x02,0x28, ++0x24,0x02,0x00,0x01,0xac,0x65,0x00,0x00,0xa0,0x82,0x00,0x00,0x3c,0x02,0xb0,0x09, ++0x34,0x42,0x01,0x46,0x90,0x44,0x00,0x00,0x91,0xe3,0x00,0x09,0x30,0x86,0x00,0x01, ++0x02,0x83,0x18,0x26,0x00,0x03,0x30,0x0b,0x14,0xc0,0x00,0x03,0x00,0x00,0x28,0x21, ++0x13,0xc0,0x00,0x03,0x02,0xb3,0x10,0x21,0x24,0x05,0x00,0x01,0x02,0xb3,0x10,0x21, ++0x27,0x83,0x90,0x08,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x84,0x48,0x00,0x04, ++0x00,0xa0,0x30,0x21,0x00,0xe0,0x20,0x21,0x02,0x80,0x28,0x21,0x02,0xc0,0x38,0x21, ++0x0c,0x00,0x00,0x70,0xaf,0xa8,0x00,0x10,0x7b,0xbe,0x02,0xbc,0x7b,0xb6,0x02,0x7c, ++0x7b,0xb4,0x02,0x3c,0x7b,0xb2,0x01,0xfc,0x7b,0xb0,0x01,0xbc,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x58,0x24,0x02,0x00,0x01,0x12,0x82,0x00,0x3d,0x3c,0x02,0xb0,0x05, ++0x24,0x02,0x00,0x02,0x12,0x82,0x00,0x31,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x03, ++0x12,0x82,0x00,0x25,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x10,0x12,0x82,0x00,0x19, ++0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x11,0x12,0x82,0x00,0x0d,0x3c,0x02,0xb0,0x05, ++0x24,0x02,0x00,0x12,0x16,0x82,0xff,0xd1,0x3c,0x02,0xb0,0x05,0x3c,0x03,0xb0,0x05, ++0x34,0x42,0x04,0x20,0x3c,0x04,0xb0,0x05,0x34,0x63,0x04,0x24,0xac,0x46,0x00,0x00, ++0x34,0x84,0x02,0x28,0xac,0x65,0x00,0x00,0x08,0x00,0x07,0xe6,0x24,0x02,0x00,0x20, ++0x34,0x42,0x04,0x40,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00, ++0x34,0x63,0x04,0x44,0x34,0x84,0x02,0x28,0x24,0x02,0x00,0x40,0x08,0x00,0x07,0xe6, ++0xac,0x65,0x00,0x00,0x34,0x42,0x04,0x28,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05, ++0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x2c,0x34,0x84,0x02,0x28,0x24,0x02,0xff,0x80, ++0x08,0x00,0x07,0xe6,0xac,0x65,0x00,0x00,0x34,0x42,0x04,0x18,0x3c,0x03,0xb0,0x05, ++0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x1c,0x34,0x84,0x02,0x28, ++0x24,0x02,0x00,0x08,0x08,0x00,0x07,0xe6,0xac,0x65,0x00,0x00,0x34,0x42,0x04,0x10, ++0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x14, ++0x34,0x84,0x02,0x28,0x24,0x02,0x00,0x04,0x08,0x00,0x07,0xe6,0xac,0x65,0x00,0x00, ++0x34,0x42,0x04,0x08,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00, ++0x34,0x63,0x04,0x0c,0x34,0x84,0x02,0x28,0x24,0x02,0x00,0x02,0x08,0x00,0x07,0xe6, ++0xac,0x65,0x00,0x00,0x24,0x17,0x00,0x14,0x08,0x00,0x07,0xb8,0x24,0x13,0x01,0x02, ++0x30,0xa2,0x00,0x07,0x24,0x44,0x00,0x0c,0x00,0x90,0x18,0x2b,0x10,0x60,0x00,0x0c, ++0x26,0x02,0x00,0x04,0x27,0x85,0xbb,0x1c,0x00,0x10,0x10,0x40,0x00,0x50,0x10,0x21, ++0x00,0x45,0x10,0x21,0x90,0x50,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x18,0x2b, ++0x14,0x60,0xff,0xfa,0x00,0x10,0x10,0x40,0x2e,0x06,0x00,0x0c,0x26,0x02,0x00,0x04, ++0x08,0x00,0x07,0xa2,0x00,0x46,0x80,0x0a,0x27,0x82,0xb4,0x00,0x01,0x82,0x20,0x21, ++0x8c,0x87,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0xe2,0x00,0x19,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x07,0x00,0x00,0x00,0x00,0x27,0x82,0x90,0x20,0x00,0xc2,0x10,0x21, ++0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x14,0x00,0x00,0x00,0x00, ++0x90,0xe3,0x00,0x16,0x27,0x82,0x90,0x08,0x00,0xc2,0x10,0x21,0x34,0x63,0x00,0x20, ++0x90,0x50,0x00,0x07,0xa0,0xe3,0x00,0x16,0x8c,0x84,0x00,0x00,0x00,0x0a,0x1e,0x42, ++0x24,0x06,0x00,0x01,0x90,0x82,0x00,0x16,0x30,0x71,0x00,0x02,0x30,0x72,0x00,0x3f, ++0x30,0x42,0x00,0xfb,0x24,0x17,0x00,0x18,0x24,0x13,0x01,0x03,0x24,0x15,0x08,0x18, ++0xaf,0xa6,0x00,0x1c,0x08,0x00,0x07,0xc2,0xa0,0x82,0x00,0x16,0x8d,0x02,0x00,0x04, ++0x00,0x0a,0x1c,0x42,0x30,0x42,0x00,0x10,0x14,0x40,0x00,0x15,0x30,0x72,0x00,0x3f, ++0x81,0x22,0x00,0x05,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x11,0x30,0x72,0x00,0x3e, ++0x27,0x83,0x90,0x18,0x00,0xc3,0x18,0x21,0x80,0x64,0x00,0x00,0x27,0x83,0xb5,0x78, ++0x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x23, ++0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x05,0x90,0x43,0x00,0x04, ++0x00,0x00,0x00,0x00,0x00,0x64,0x18,0x24,0x30,0x63,0x00,0x01,0x02,0x43,0x90,0x25, ++0x27,0x85,0xb4,0x00,0x01,0x85,0x28,0x21,0x8c,0xa6,0x00,0x00,0x01,0x73,0x10,0x21, ++0x27,0x83,0x90,0x10,0x90,0xc4,0x00,0x16,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21, ++0x30,0x84,0x00,0xdf,0x90,0x50,0x00,0x00,0xa0,0xc4,0x00,0x16,0x80,0xc6,0x00,0x12, ++0x8c,0xa3,0x00,0x00,0x2d,0xc4,0x00,0x02,0xaf,0xa6,0x00,0x1c,0x90,0x62,0x00,0x16, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfb,0x14,0x80,0x00,0x06,0xa0,0x62,0x00,0x16, ++0x24,0x02,0x00,0x06,0x11,0xc2,0x00,0x03,0x24,0x02,0x00,0x04,0x15,0xc2,0xff,0x0e, ++0x32,0x51,0x00,0x02,0x32,0x51,0x00,0x02,0x2e,0x02,0x00,0x0c,0x14,0x40,0x00,0x0f, ++0x00,0x11,0x18,0x2b,0x32,0x02,0x00,0x0f,0x34,0x42,0x00,0x10,0x00,0x03,0x19,0x00, ++0x00,0x43,0x18,0x21,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xe0,0xa0,0x43,0x00,0x00, ++0x00,0x00,0x20,0x21,0x02,0x00,0x28,0x21,0x0c,0x00,0x02,0x03,0xaf,0xaf,0x00,0x28, ++0x8f,0xaf,0x00,0x28,0x08,0x00,0x07,0xc2,0x00,0x00,0x00,0x00,0x08,0x00,0x08,0xbd, ++0x32,0x03,0x00,0xff,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x42,0x90,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x0f,0x14,0x40,0xfe,0xaa,0x00,0x00,0x00,0x00, ++0x91,0xe2,0x00,0x09,0x00,0x00,0x00,0x00,0x02,0x82,0x10,0x26,0x08,0x00,0x07,0x79, ++0x00,0x02,0x28,0x0b,0x08,0x00,0x07,0x7f,0x00,0x00,0xb0,0x21,0x24,0x02,0x00,0x10, ++0x10,0xc2,0x00,0x08,0x24,0x02,0x00,0x11,0x10,0xc2,0xfe,0x7d,0x00,0x07,0x17,0x83, ++0x24,0x02,0x00,0x12,0x14,0xc2,0xfe,0x7b,0x00,0x07,0x17,0x43,0x08,0x00,0x07,0x59, ++0x30,0x5e,0x00,0x01,0x08,0x00,0x07,0x59,0x00,0x07,0xf7,0xc2,0x00,0x04,0x10,0x40, ++0x27,0x83,0x80,0x1c,0x00,0x43,0x10,0x21,0x00,0x80,0x40,0x21,0x94,0x44,0x00,0x00, ++0x2d,0x07,0x00,0x04,0x24,0xc2,0x00,0x03,0x00,0x47,0x30,0x0a,0x00,0x86,0x00,0x18, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x23,0x8c, ++0xac,0x62,0x00,0x00,0x2d,0x06,0x00,0x10,0x00,0x00,0x20,0x12,0x00,0x04,0x22,0x42, ++0x24,0x84,0x00,0x01,0x24,0x83,0x00,0xc0,0x10,0xe0,0x00,0x0b,0x24,0x82,0x00,0x60, ++0x00,0x40,0x20,0x21,0x00,0x65,0x20,0x0a,0x3c,0x03,0xb0,0x03,0x34,0x63,0x01,0x00, ++0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x00,0x44,0x20,0x04, ++0x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x24,0x85,0x00,0x28,0x24,0x83,0x00,0x24, ++0x31,0x02,0x00,0x08,0x14,0xc0,0xff,0xf4,0x24,0x84,0x00,0x14,0x00,0x60,0x20,0x21, ++0x08,0x00,0x08,0xfa,0x00,0xa2,0x20,0x0b,0x27,0xbd,0xff,0xe0,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0xaf,0xb0,0x00,0x10,0x24,0x42,0x24,0x28,0x00,0x80,0x80,0x21, ++0x34,0x63,0x00,0x20,0x3c,0x04,0xb0,0x03,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14, ++0xaf,0xbf,0x00,0x1c,0x83,0xb1,0x00,0x33,0x83,0xa8,0x00,0x37,0x34,0x84,0x01,0x10, ++0xac,0x62,0x00,0x00,0x2e,0x02,0x00,0x10,0x00,0xe0,0x90,0x21,0x8c,0x87,0x00,0x00, ++0x14,0x40,0x00,0x0c,0x2e,0x02,0x00,0x0c,0x3c,0x02,0x00,0x0f,0x34,0x42,0xf0,0x00, ++0x00,0xe2,0x10,0x24,0x14,0x40,0x00,0x37,0x32,0x02,0x00,0x08,0x32,0x02,0x00,0x07, ++0x27,0x83,0x80,0xcc,0x00,0x43,0x10,0x21,0x90,0x50,0x00,0x00,0x00,0x00,0x00,0x00, ++0x2e,0x02,0x00,0x0c,0x14,0x40,0x00,0x03,0x02,0x00,0x20,0x21,0x32,0x02,0x00,0x0f, ++0x24,0x44,0x00,0x0c,0x00,0x87,0x10,0x06,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x07, ++0x2c,0x82,0x00,0x0c,0x00,0x04,0x10,0x80,0x27,0x83,0xb4,0x50,0x00,0x43,0x10,0x21, ++0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x82,0x00,0x0c,0x14,0x40,0x00,0x05, ++0x00,0x05,0x10,0x40,0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0x82,0x10,0x21, ++0x24,0x44,0x00,0x04,0x15,0x00,0x00,0x02,0x24,0x06,0x00,0x20,0x24,0x06,0x00,0x0e, ++0x0c,0x00,0x08,0xe3,0x00,0x00,0x00,0x00,0x00,0x40,0x30,0x21,0x3c,0x02,0xb0,0x03, ++0x34,0x42,0x01,0x00,0x90,0x43,0x00,0x00,0x2e,0x04,0x00,0x04,0x24,0x02,0x00,0x10, ++0x24,0x05,0x00,0x0a,0x00,0x44,0x28,0x0a,0x30,0x63,0x00,0x01,0x14,0x60,0x00,0x02, ++0x00,0x05,0x10,0x40,0x00,0xa0,0x10,0x21,0x30,0x45,0x00,0xff,0x00,0xc5,0x10,0x21, ++0x24,0x46,0x00,0x46,0x02,0x26,0x18,0x04,0xa6,0x43,0x00,0x00,0x8f,0xbf,0x00,0x1c, ++0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x00,0xc0,0x10,0x21,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x20,0x10,0x40,0xff,0xcf,0x2e,0x02,0x00,0x0c,0x32,0x02,0x00,0x07, ++0x27,0x83,0x80,0xc4,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x00,0x08,0x00,0x09,0x28, ++0x02,0x04,0x80,0x23,0x27,0xbd,0xff,0xb8,0x00,0x05,0x38,0x80,0x27,0x82,0xb4,0x00, ++0xaf,0xbe,0x00,0x40,0xaf,0xb6,0x00,0x38,0xaf,0xb3,0x00,0x2c,0xaf,0xbf,0x00,0x44, ++0xaf,0xb7,0x00,0x3c,0xaf,0xb5,0x00,0x34,0xaf,0xb4,0x00,0x30,0xaf,0xb2,0x00,0x28, ++0xaf,0xb1,0x00,0x24,0xaf,0xb0,0x00,0x20,0x00,0xe2,0x38,0x21,0x8c,0xe6,0x00,0x00, ++0xaf,0xa5,0x00,0x4c,0x3c,0x02,0x80,0x00,0x3c,0x05,0xb0,0x03,0x34,0xa5,0x00,0x20, ++0x24,0x42,0x25,0x84,0x24,0x03,0x00,0x01,0xac,0xa2,0x00,0x00,0xa0,0xc3,0x00,0x12, ++0x8c,0xe5,0x00,0x00,0x94,0xc3,0x00,0x06,0x90,0xa2,0x00,0x16,0xa4,0xc3,0x00,0x14, ++0x27,0x83,0x90,0x00,0x34,0x42,0x00,0x08,0xa0,0xa2,0x00,0x16,0x8c,0xe8,0x00,0x00, ++0xaf,0xa4,0x00,0x48,0x27,0x82,0x90,0x04,0x95,0x11,0x00,0x14,0x00,0x00,0x00,0x00, ++0x00,0x11,0x98,0xc0,0x02,0x71,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x82,0x10,0x21, ++0x8c,0x52,0x00,0x18,0x00,0x83,0x18,0x21,0x84,0x75,0x00,0x06,0x8e,0x45,0x00,0x08, ++0x8e,0x46,0x00,0x04,0x8e,0x47,0x00,0x04,0x00,0x05,0x1c,0x82,0x00,0x06,0x31,0x42, ++0x27,0x82,0x90,0x10,0x30,0x63,0x00,0x01,0x30,0xc6,0x00,0x01,0x00,0x82,0x20,0x21, ++0xa5,0x15,0x00,0x1a,0x00,0x05,0x14,0x42,0xaf,0xa3,0x00,0x18,0xaf,0xa6,0x00,0x1c, ++0x30,0xe7,0x00,0x10,0x30,0x56,0x00,0x01,0x80,0x97,0x00,0x06,0x14,0xe0,0x00,0x47, ++0x00,0x05,0xf7,0xc2,0x80,0x82,0x00,0x05,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x44, ++0x02,0x71,0x10,0x21,0x93,0x90,0xbb,0xe9,0x00,0x00,0x00,0x00,0x2e,0x02,0x00,0x0c, ++0x14,0x40,0x00,0x06,0x02,0x00,0x20,0x21,0x00,0x16,0x10,0x40,0x00,0x43,0x10,0x21, ++0x00,0x02,0x11,0x00,0x02,0x02,0x10,0x21,0x24,0x44,0x00,0x04,0x02,0x71,0x10,0x21, ++0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,0x00,0x80,0x80,0x21, ++0xa0,0x44,0x00,0x03,0xa0,0x44,0x00,0x00,0x02,0x00,0x20,0x21,0x02,0xc0,0x28,0x21, ++0x0c,0x00,0x08,0xe3,0x02,0xa0,0x30,0x21,0x02,0x71,0x18,0x21,0x00,0x03,0x88,0x80, ++0x00,0x40,0xa0,0x21,0x27,0x82,0x90,0x20,0x02,0x22,0x10,0x21,0x8c,0x44,0x00,0x00, ++0x26,0xe3,0x00,0x02,0x00,0x03,0x17,0xc2,0x00,0x62,0x18,0x21,0x00,0x04,0x25,0xc2, ++0x00,0x03,0x18,0x43,0x30,0x84,0x00,0x01,0x00,0x03,0x18,0x40,0x03,0xc4,0x20,0x24, ++0x14,0x80,0x00,0x15,0x02,0x43,0x38,0x21,0x3c,0x08,0xb0,0x03,0x35,0x08,0x00,0x28, ++0x8d,0x03,0x00,0x00,0x8f,0xa6,0x00,0x4c,0x8f,0xa4,0x00,0x48,0x27,0x82,0x90,0x08, ++0x02,0x22,0x10,0x21,0x24,0x63,0x00,0x01,0x02,0xa0,0x28,0x21,0xa4,0x54,0x00,0x04, ++0x00,0xc0,0x38,0x21,0x0c,0x00,0x07,0x2f,0xad,0x03,0x00,0x00,0x7b,0xbe,0x02,0x3c, ++0x7b,0xb6,0x01,0xfc,0x7b,0xb4,0x01,0xbc,0x7b,0xb2,0x01,0x7c,0x7b,0xb0,0x01,0x3c, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x48,0x8f,0xa2,0x00,0x1c,0x8f,0xa6,0x00,0x18, ++0x02,0x00,0x20,0x21,0x02,0xc0,0x28,0x21,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0x0a, ++0xaf,0xa0,0x00,0x14,0x08,0x00,0x09,0xc6,0x02,0x82,0xa0,0x21,0x02,0x71,0x10,0x21, ++0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,0x90,0x50,0x00,0x00, ++0x08,0x00,0x09,0xb2,0xa0,0x50,0x00,0x03,0x27,0xbd,0xff,0xb8,0xaf,0xb1,0x00,0x24, ++0x8f,0xb1,0x00,0x5c,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20, ++0x24,0x42,0x27,0xa8,0xaf,0xbe,0x00,0x40,0xaf,0xb7,0x00,0x3c,0xaf,0xb6,0x00,0x38, ++0xaf,0xb5,0x00,0x34,0xaf,0xb4,0x00,0x30,0xaf,0xa5,0x00,0x4c,0x8f,0xb5,0x00,0x58, ++0xaf,0xbf,0x00,0x44,0xaf,0xb3,0x00,0x2c,0xaf,0xb2,0x00,0x28,0xaf,0xb0,0x00,0x20, ++0x00,0xe0,0xb0,0x21,0xac,0x62,0x00,0x00,0x00,0x80,0xf0,0x21,0x00,0x00,0xb8,0x21, ++0x16,0x20,0x00,0x2b,0x00,0x00,0xa0,0x21,0x27,0x85,0xb4,0x00,0x00,0x07,0x10,0x80, ++0x00,0x45,0x10,0x21,0x8c,0x53,0x00,0x00,0x00,0x15,0x18,0x80,0x00,0x65,0x18,0x21, ++0x92,0x62,0x00,0x16,0x8c,0x72,0x00,0x00,0x30,0x42,0x00,0x03,0x14,0x40,0x00,0x2d, ++0x00,0x00,0x00,0x00,0x92,0x42,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x03, ++0x14,0x40,0x00,0x28,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x34,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x18,0x02,0x20,0x10,0x21,0x8c,0x82,0x00,0x38,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x14,0x02,0x20,0x10,0x21,0x8c,0x82,0x00,0x3c,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x0f,0x3c,0x03,0xb0,0x09,0x3c,0x05,0xb0,0x05,0x34,0x63,0x01,0x44, ++0x34,0xa5,0x02,0x52,0x94,0x66,0x00,0x00,0x90,0xa2,0x00,0x00,0x8f,0xa3,0x00,0x4c, ++0x00,0x00,0x00,0x00,0x00,0x62,0x10,0x06,0x30,0x42,0x00,0x01,0x10,0x40,0x00,0x04, ++0x30,0xc6,0xff,0xff,0x2c,0xc2,0x00,0x41,0x10,0x40,0x00,0x09,0x24,0x05,0x00,0x14, ++0x02,0x20,0x10,0x21,0x7b,0xbe,0x02,0x3c,0x7b,0xb6,0x01,0xfc,0x7b,0xb4,0x01,0xbc, ++0x7b,0xb2,0x01,0x7c,0x7b,0xb0,0x01,0x3c,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x48, ++0x0c,0x00,0x07,0x0a,0x24,0x06,0x01,0x07,0x24,0x02,0x00,0x01,0x08,0x00,0x0a,0x2c, ++0xa3,0xc2,0x00,0x11,0x10,0xc0,0x00,0x1c,0x24,0x02,0x00,0x01,0x10,0xc2,0x00,0x17, ++0x00,0xc0,0x88,0x21,0x96,0x54,0x00,0x1a,0x02,0xa0,0xb8,0x21,0x12,0x20,0xff,0xed, ++0x02,0x20,0x10,0x21,0x27,0x83,0xb4,0x00,0x00,0x17,0x10,0x80,0x00,0x43,0x10,0x21, ++0x8c,0x44,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x28,0x80,0x86,0x00,0x12, ++0x8c,0x62,0x00,0x00,0x00,0x14,0x2c,0x00,0x00,0x05,0x2c,0x03,0x00,0x46,0x10,0x21, ++0x8f,0xa6,0x00,0x4c,0x02,0xe0,0x38,0x21,0x03,0xc0,0x20,0x21,0x0c,0x00,0x07,0x2f, ++0xac,0x62,0x00,0x00,0x08,0x00,0x0a,0x2c,0xaf,0xd1,0x00,0x40,0x96,0x74,0x00,0x1a, ++0x08,0x00,0x0a,0x3f,0x02,0xc0,0xb8,0x21,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08, ++0x8c,0x50,0x00,0x00,0x02,0x60,0x20,0x21,0x0c,0x00,0x1e,0xf3,0x02,0x00,0x28,0x21, ++0x30,0x42,0x00,0xff,0x02,0x00,0x28,0x21,0x02,0x40,0x20,0x21,0x0c,0x00,0x1e,0xf3, ++0xaf,0xa2,0x00,0x18,0x8f,0xa4,0x00,0x18,0x00,0x00,0x00,0x00,0x10,0x80,0x00,0xed, ++0x30,0x50,0x00,0xff,0x12,0x00,0x00,0x18,0x24,0x11,0x00,0x01,0x96,0x63,0x00,0x14, ++0x96,0x44,0x00,0x14,0x27,0x85,0x90,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21, ++0x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x00,0x04,0x18,0xc0,0x8c,0x46,0x00,0x08, ++0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x65,0x18,0x21,0x00,0x06,0x17,0x02, ++0x24,0x04,0x00,0xff,0x8c,0x63,0x00,0x08,0x10,0x44,0x00,0xd6,0x00,0x03,0x17,0x02, ++0x10,0x44,0x00,0xd5,0x3c,0x02,0x80,0x00,0x00,0x66,0x18,0x2b,0x24,0x11,0x00,0x02, ++0x24,0x02,0x00,0x01,0x00,0x43,0x88,0x0a,0x24,0x02,0x00,0x01,0x12,0x22,0x00,0x5a, ++0x24,0x02,0x00,0x02,0x16,0x22,0xff,0xbd,0x00,0x00,0x00,0x00,0x96,0x49,0x00,0x14, ++0x27,0x82,0x90,0x04,0x02,0xa0,0xb8,0x21,0x00,0x09,0x50,0xc0,0x01,0x49,0x18,0x21, ++0x00,0x03,0x40,0x80,0x01,0x02,0x10,0x21,0x8c,0x43,0x00,0x18,0x00,0x00,0x00,0x00, ++0x8c,0x65,0x00,0x08,0x8c,0x62,0x00,0x0c,0x8c,0x62,0x00,0x04,0x00,0x05,0x24,0x42, ++0x00,0x05,0x1c,0x82,0x30,0x42,0x00,0x10,0x30,0x66,0x00,0x01,0x14,0x40,0x00,0x41, ++0x30,0x87,0x00,0x01,0x27,0x82,0x90,0x18,0x01,0x02,0x10,0x21,0x80,0x44,0x00,0x00, ++0x27,0x82,0xb5,0x78,0x00,0x04,0x19,0x00,0x00,0x64,0x18,0x23,0x00,0x03,0x18,0x80, ++0x00,0x64,0x18,0x23,0x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21,0x90,0x45,0x00,0x05, ++0x27,0x84,0xb4,0xa0,0x00,0x64,0x18,0x21,0x90,0x63,0x00,0x00,0x10,0xa0,0x00,0x2b, ++0x2c,0x64,0x00,0x0c,0x14,0x80,0x00,0x04,0x00,0x60,0x10,0x21,0x00,0x06,0x11,0x00, ++0x00,0x62,0x10,0x21,0x24,0x42,0x00,0x24,0x3c,0x01,0xb0,0x03,0xa0,0x22,0x00,0xe1, ++0x14,0x80,0x00,0x06,0x00,0x60,0x28,0x21,0x00,0x07,0x10,0x40,0x00,0x46,0x10,0x21, ++0x00,0x02,0x11,0x00,0x00,0x62,0x10,0x21,0x24,0x45,0x00,0x04,0x01,0x49,0x10,0x21, ++0x27,0x83,0x90,0x10,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0xa0,0x18,0x21, ++0xa0,0x45,0x00,0x03,0xa0,0x45,0x00,0x00,0x24,0x02,0x00,0x08,0x12,0x02,0x00,0x0b, ++0x24,0x02,0x00,0x01,0x00,0x60,0x28,0x21,0x02,0x40,0x20,0x21,0x0c,0x00,0x1f,0x6f, ++0xaf,0xa2,0x00,0x10,0x30,0x54,0xff,0xff,0x92,0x42,0x00,0x16,0x00,0x00,0x00,0x00, ++0x02,0x02,0x10,0x25,0x08,0x00,0x0a,0x3f,0xa2,0x42,0x00,0x16,0x00,0x60,0x28,0x21, ++0x02,0x40,0x20,0x21,0x0c,0x00,0x1f,0x20,0xaf,0xa0,0x00,0x10,0x08,0x00,0x0a,0xc2, ++0x30,0x54,0xff,0xff,0x08,0x00,0x0a,0xaa,0x00,0x60,0x10,0x21,0x14,0x80,0xff,0xfd, ++0x00,0x00,0x00,0x00,0x00,0x06,0x11,0x00,0x00,0x62,0x10,0x21,0x08,0x00,0x0a,0xaa, ++0x24,0x42,0x00,0x04,0x27,0x82,0x90,0x10,0x01,0x02,0x10,0x21,0x90,0x43,0x00,0x00, ++0x08,0x00,0x0a,0xba,0xa0,0x43,0x00,0x03,0x96,0x69,0x00,0x14,0x02,0xc0,0xb8,0x21, ++0x24,0x0b,0x00,0x01,0x00,0x09,0x10,0xc0,0x00,0x49,0x18,0x21,0x00,0x03,0x40,0x80, ++0x00,0x40,0x50,0x21,0x27,0x82,0x90,0x04,0x01,0x02,0x10,0x21,0x8c,0x43,0x00,0x18, ++0x00,0x00,0x00,0x00,0x8c,0x65,0x00,0x08,0x8c,0x62,0x00,0x0c,0x8c,0x62,0x00,0x04, ++0x00,0x05,0x24,0x42,0x00,0x05,0x1c,0x82,0x30,0x42,0x00,0x10,0x30,0x66,0x00,0x01, ++0x10,0x40,0x00,0x0d,0x30,0x87,0x00,0x01,0x27,0x82,0x90,0x18,0x01,0x02,0x10,0x21, ++0x80,0x43,0x00,0x00,0x00,0x00,0x58,0x21,0x00,0x03,0x11,0x00,0x00,0x43,0x10,0x23, ++0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x23,0x00,0x02,0x10,0x80,0x27,0x83,0xb5,0x70, ++0x00,0x43,0x10,0x21,0xa0,0x40,0x00,0x04,0x11,0x60,0x00,0x4f,0x00,0x00,0x00,0x00, ++0x01,0x49,0x10,0x21,0x00,0x02,0x20,0x80,0x27,0x85,0x90,0x10,0x00,0x85,0x10,0x21, ++0x80,0x43,0x00,0x05,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x42,0x01,0x49,0x10,0x21, ++0x27,0x82,0x90,0x18,0x00,0x82,0x10,0x21,0x80,0x44,0x00,0x00,0x27,0x82,0xb5,0x78, ++0x00,0x04,0x19,0x00,0x00,0x64,0x18,0x23,0x00,0x03,0x18,0x80,0x00,0x64,0x18,0x23, ++0x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21,0x90,0x45,0x00,0x05,0x27,0x84,0xb4,0xa0, ++0x00,0x64,0x18,0x21,0x90,0x63,0x00,0x00,0x10,0xa0,0x00,0x2c,0x2c,0x64,0x00,0x0c, ++0x14,0x80,0x00,0x04,0x00,0x60,0x10,0x21,0x00,0x06,0x11,0x00,0x00,0x62,0x10,0x21, ++0x24,0x42,0x00,0x24,0x3c,0x01,0xb0,0x03,0xa0,0x22,0x00,0xe1,0x14,0x80,0x00,0x06, ++0x00,0x60,0x28,0x21,0x00,0x07,0x10,0x40,0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00, ++0x00,0x62,0x10,0x21,0x24,0x45,0x00,0x04,0x01,0x49,0x10,0x21,0x27,0x83,0x90,0x10, ++0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0xa0,0x18,0x21,0xa0,0x45,0x00,0x03, ++0xa0,0x45,0x00,0x00,0x8f,0xa4,0x00,0x18,0x24,0x02,0x00,0x08,0x10,0x82,0x00,0x0c, ++0x00,0x60,0x28,0x21,0x24,0x02,0x00,0x01,0x02,0x60,0x20,0x21,0x0c,0x00,0x1f,0x6f, ++0xaf,0xa2,0x00,0x10,0x8f,0xa3,0x00,0x18,0x30,0x54,0xff,0xff,0x92,0x62,0x00,0x16, ++0x00,0x00,0x00,0x00,0x00,0x62,0x10,0x25,0x08,0x00,0x0a,0x3f,0xa2,0x62,0x00,0x16, ++0x02,0x60,0x20,0x21,0x0c,0x00,0x1f,0x20,0xaf,0xa0,0x00,0x10,0x08,0x00,0x0b,0x31, ++0x00,0x00,0x00,0x00,0x08,0x00,0x0b,0x19,0x00,0x60,0x10,0x21,0x14,0x80,0xff,0xfd, ++0x00,0x00,0x00,0x00,0x00,0x06,0x11,0x00,0x00,0x62,0x10,0x21,0x08,0x00,0x0b,0x19, ++0x24,0x42,0x00,0x04,0x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x90,0x43,0x00,0x00, ++0x08,0x00,0x0b,0x29,0xa0,0x43,0x00,0x03,0x27,0x85,0x90,0x10,0x08,0x00,0x0b,0x45, ++0x01,0x49,0x10,0x21,0x3c,0x02,0x80,0x00,0x00,0x62,0x18,0x26,0x08,0x00,0x0a,0x7a, ++0x00,0xc2,0x30,0x26,0x12,0x00,0xff,0x2d,0x24,0x02,0x00,0x01,0x08,0x00,0x0a,0x7f, ++0x24,0x11,0x00,0x02,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xd0, ++0x24,0x42,0x2d,0x54,0x34,0x63,0x00,0x20,0x3c,0x05,0xb0,0x05,0xaf,0xb3,0x00,0x24, ++0xaf,0xb2,0x00,0x20,0xaf,0xb1,0x00,0x1c,0xaf,0xbf,0x00,0x28,0xaf,0xb0,0x00,0x18, ++0xac,0x62,0x00,0x00,0x34,0xa5,0x02,0x42,0x90,0xa2,0x00,0x00,0x00,0x80,0x90,0x21, ++0x24,0x11,0x00,0x10,0x30,0x53,0x00,0xff,0x24,0x02,0x00,0x10,0x12,0x22,0x00,0xcf, ++0x00,0x00,0x18,0x21,0x24,0x02,0x00,0x11,0x12,0x22,0x00,0xc1,0x24,0x02,0x00,0x12, ++0x12,0x22,0x00,0xb4,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0xad,0xae,0x43,0x00,0x40, ++0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,0x8c,0x44,0x00,0x00,0x3c,0x03,0x00,0x02, ++0x34,0x63,0x00,0xff,0x00,0x83,0x80,0x24,0x00,0x10,0x14,0x43,0x10,0x40,0x00,0x05, ++0x00,0x00,0x00,0x00,0x8e,0x42,0x00,0x34,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x92, ++0x00,0x00,0x00,0x00,0x93,0x83,0x8b,0x71,0x00,0x00,0x00,0x00,0x30,0x62,0x00,0x02, ++0x10,0x40,0x00,0x04,0x32,0x10,0x00,0xff,0x00,0x10,0x11,0xc3,0x14,0x40,0x00,0x86, ++0x00,0x00,0x00,0x00,0x16,0x00,0x00,0x15,0x02,0x00,0x10,0x21,0x26,0x22,0x00,0x01, ++0x30,0x51,0x00,0xff,0x2e,0x23,0x00,0x13,0x14,0x60,0xff,0xdb,0x24,0x03,0x00,0x02, ++0x12,0x63,0x00,0x73,0x24,0x02,0x00,0x05,0x2a,0x62,0x00,0x03,0x10,0x40,0x00,0x58, ++0x24,0x02,0x00,0x04,0x24,0x02,0x00,0x01,0x12,0x62,0x00,0x4b,0x02,0x40,0x20,0x21, ++0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x70,0x00,0xff,0x12,0x00,0x00,0x06,0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x28, ++0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30, ++0x92,0x46,0x00,0x04,0x8e,0x43,0x00,0x24,0x24,0x02,0x00,0x07,0x02,0x40,0x20,0x21, ++0x00,0x00,0x28,0x21,0x24,0x07,0x00,0x06,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xea, ++0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x24,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c, ++0x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,0x16,0x00,0xff,0xec,0x02,0x00,0x10,0x21, ++0x92,0x46,0x00,0x05,0x8e,0x43,0x00,0x28,0x24,0x02,0x00,0x05,0x02,0x40,0x20,0x21, ++0x24,0x05,0x00,0x01,0x24,0x07,0x00,0x04,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xea, ++0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x28,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c, ++0x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,0x16,0x00,0xff,0xdc,0x02,0x00,0x10,0x21, ++0x92,0x46,0x00,0x06,0x8e,0x43,0x00,0x2c,0x24,0x02,0x00,0x03,0x02,0x40,0x20,0x21, ++0x24,0x05,0x00,0x02,0x00,0x00,0x38,0x21,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xea, ++0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x2c,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c, ++0x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,0x16,0x00,0xff,0xcc,0x02,0x00,0x10,0x21, ++0x92,0x46,0x00,0x07,0x8e,0x43,0x00,0x30,0x24,0x02,0x00,0x02,0x02,0x40,0x20,0x21, ++0x24,0x05,0x00,0x03,0x24,0x07,0x00,0x01,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xea, ++0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x30,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c, ++0x08,0x00,0x0b,0x9b,0x30,0x42,0x00,0xff,0x92,0x46,0x00,0x04,0x8e,0x43,0x00,0x24, ++0x24,0x02,0x00,0x07,0x00,0x00,0x28,0x21,0x24,0x07,0x00,0x06,0xaf,0xa2,0x00,0x10, ++0x0c,0x00,0x09,0xea,0xaf,0xa3,0x00,0x14,0x08,0x00,0x0b,0x94,0xae,0x42,0x00,0x24, ++0x12,0x62,0x00,0x0d,0x24,0x02,0x00,0x03,0x24,0x02,0x00,0x08,0x16,0x62,0xff,0xa8, ++0x02,0x40,0x20,0x21,0x92,0x46,0x00,0x07,0x8e,0x42,0x00,0x30,0x24,0x05,0x00,0x03, ++0x24,0x07,0x00,0x01,0xaf,0xa3,0x00,0x10,0x0c,0x00,0x09,0xea,0xaf,0xa2,0x00,0x14, ++0x08,0x00,0x0b,0x94,0xae,0x42,0x00,0x30,0x92,0x46,0x00,0x06,0x8e,0x43,0x00,0x2c, ++0x02,0x40,0x20,0x21,0x24,0x05,0x00,0x02,0x00,0x00,0x38,0x21,0xaf,0xa2,0x00,0x10, ++0x0c,0x00,0x09,0xea,0xaf,0xa3,0x00,0x14,0x08,0x00,0x0b,0x94,0xae,0x42,0x00,0x2c, ++0x92,0x46,0x00,0x05,0x8e,0x43,0x00,0x28,0x02,0x40,0x20,0x21,0x24,0x05,0x00,0x01, ++0x24,0x07,0x00,0x04,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xea,0xaf,0xa3,0x00,0x14, ++0x08,0x00,0x0b,0x94,0xae,0x42,0x00,0x28,0x0c,0x00,0x01,0x57,0x24,0x04,0x00,0x01, ++0x08,0x00,0x0b,0x85,0x00,0x00,0x00,0x00,0x8f,0x84,0xb4,0x40,0xae,0x40,0x00,0x34, ++0x94,0x85,0x00,0x14,0x0c,0x00,0x1b,0x66,0x00,0x00,0x00,0x00,0x93,0x83,0x8b,0x71, ++0x00,0x00,0x00,0x00,0x30,0x62,0x00,0x02,0x10,0x40,0xff,0x69,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x01,0x57,0x00,0x00,0x20,0x21,0x08,0x00,0x0b,0x7d,0x00,0x00,0x00,0x00, ++0x02,0x40,0x20,0x21,0x0c,0x00,0x09,0x61,0x02,0x20,0x28,0x21,0x08,0x00,0x0b,0x71, ++0x3c,0x02,0xb0,0x05,0x8e,0x42,0x00,0x3c,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x4a, ++0x00,0x00,0x00,0x00,0x8f,0x82,0xb4,0x48,0x00,0x00,0x00,0x00,0x90,0x42,0x00,0x0a, ++0x00,0x00,0x00,0x00,0x00,0x02,0x18,0x2b,0x08,0x00,0x0b,0x6e,0xae,0x43,0x00,0x3c, ++0x8e,0x42,0x00,0x38,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x3d,0x24,0x02,0x00,0x12, ++0x8f,0x82,0xb4,0x44,0x00,0x00,0x00,0x00,0x90,0x42,0x00,0x0a,0x00,0x00,0x00,0x00, ++0x00,0x02,0x18,0x2b,0x08,0x00,0x0b,0x6e,0xae,0x43,0x00,0x38,0x8e,0x42,0x00,0x34, ++0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x30,0x24,0x02,0x00,0x11,0x8f,0x82,0xb4,0x40, ++0x00,0x00,0x00,0x00,0x90,0x42,0x00,0x0a,0x00,0x00,0x00,0x00,0x00,0x02,0x18,0x2b, ++0x08,0x00,0x0b,0x6e,0xae,0x43,0x00,0x34,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00, ++0x27,0xbd,0xff,0xe0,0x34,0x63,0x00,0x20,0x24,0x42,0x31,0x08,0x3c,0x08,0xb0,0x03, ++0xaf,0xb1,0x00,0x14,0xac,0x62,0x00,0x00,0x35,0x08,0x01,0x00,0xaf,0xbf,0x00,0x18, ++0xaf,0xb0,0x00,0x10,0x91,0x03,0x00,0x00,0x00,0xa0,0x48,0x21,0x24,0x11,0x00,0x0a, ++0x2c,0xa5,0x00,0x04,0x24,0x02,0x00,0x10,0x00,0x45,0x88,0x0a,0x30,0x63,0x00,0x01, ++0x00,0xc0,0x28,0x21,0x14,0x60,0x00,0x02,0x00,0x11,0x40,0x40,0x02,0x20,0x40,0x21, ++0x84,0x83,0x00,0x0c,0x31,0x11,0x00,0xff,0x01,0x20,0x20,0x21,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x08,0x00,0x43,0x10,0x21, ++0x84,0x43,0x00,0x04,0x24,0x06,0x00,0x0e,0x10,0xe0,0x00,0x06,0x02,0x23,0x80,0x21, ++0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x20,0x0c,0x00,0x08,0xe3,0x00,0x00,0x00,0x00,0x02,0x11,0x18,0x21, ++0x08,0x00,0x0c,0x64,0x00,0x62,0x80,0x21,0x27,0xbd,0xff,0xd0,0xaf,0xbf,0x00,0x28, ++0xaf,0xb4,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,0xaf,0xb5,0x00,0x24, ++0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x84,0x82,0x00,0x0c,0x3c,0x06,0xb0,0x03, ++0x34,0xc6,0x00,0x20,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80, ++0x27,0x82,0x90,0x04,0x00,0x62,0x10,0x21,0x8c,0x55,0x00,0x18,0x3c,0x02,0x80,0x00, ++0x24,0x42,0x31,0xb8,0xac,0xc2,0x00,0x00,0x8e,0xb0,0x00,0x08,0x27,0x82,0x90,0x08, ++0x00,0x62,0x18,0x21,0x90,0x71,0x00,0x07,0x00,0x10,0x86,0x43,0x32,0x10,0x00,0x01, ++0x00,0xa0,0x38,0x21,0x02,0x00,0x30,0x21,0x00,0xa0,0x98,0x21,0x02,0x20,0x28,0x21, ++0x0c,0x00,0x0c,0x42,0x00,0x80,0x90,0x21,0x02,0x20,0x20,0x21,0x02,0x00,0x28,0x21, ++0x24,0x06,0x00,0x14,0x0c,0x00,0x08,0xe3,0x00,0x40,0xa0,0x21,0x86,0x43,0x00,0x0c, ++0x3c,0x09,0xb0,0x09,0x3c,0x08,0xb0,0x09,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21, ++0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,0x80,0x43,0x00,0x06, ++0x3c,0x07,0xb0,0x09,0x3c,0x05,0xb0,0x09,0x28,0x62,0x00,0x00,0x24,0x64,0x00,0x03, ++0x00,0x82,0x18,0x0b,0x00,0x03,0x18,0x83,0x3c,0x02,0xb0,0x09,0x00,0x03,0x18,0x80, ++0x34,0x42,0x01,0x02,0x35,0x29,0x01,0x10,0x35,0x08,0x01,0x14,0x34,0xe7,0x01,0x20, ++0x34,0xa5,0x01,0x24,0xa4,0x54,0x00,0x00,0x12,0x60,0x00,0x11,0x02,0xa3,0xa8,0x21, ++0x8e,0xa2,0x00,0x0c,0x8e,0xa3,0x00,0x08,0x00,0x02,0x14,0x00,0x00,0x03,0x1c,0x02, ++0x00,0x43,0x10,0x21,0xad,0x22,0x00,0x00,0x8e,0xa3,0x00,0x0c,0x00,0x00,0x00,0x00, ++0x00,0x03,0x1c,0x02,0xa5,0x03,0x00,0x00,0x8f,0xbf,0x00,0x28,0x7b,0xb4,0x01,0x3c, ++0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30, ++0x8e,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,0xad,0x22,0x00,0x00,0x8e,0xa4,0x00,0x08, ++0x00,0x00,0x00,0x00,0xa5,0x04,0x00,0x00,0x7a,0xa2,0x00,0x7c,0x00,0x00,0x00,0x00, ++0x00,0x03,0x1c,0x00,0x00,0x02,0x14,0x02,0x00,0x62,0x18,0x21,0xac,0xe3,0x00,0x00, ++0x8e,0xa2,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x02,0x14,0x02,0x08,0x00,0x0c,0xb6, ++0xa4,0xa2,0x00,0x00,0x27,0xbd,0xff,0xe0,0xaf,0xb2,0x00,0x18,0xaf,0xb0,0x00,0x10, ++0xaf,0xbf,0x00,0x1c,0xaf,0xb1,0x00,0x14,0x84,0x82,0x00,0x0c,0x00,0x80,0x90,0x21, ++0x3c,0x05,0xb0,0x03,0x00,0x02,0x20,0xc0,0x00,0x82,0x20,0x21,0x00,0x04,0x20,0x80, ++0x27,0x82,0x90,0x04,0x00,0x82,0x10,0x21,0x8c,0x51,0x00,0x18,0x3c,0x02,0x80,0x00, ++0x34,0xa5,0x00,0x20,0x24,0x42,0x33,0x34,0x27,0x83,0x90,0x08,0xac,0xa2,0x00,0x00, ++0x00,0x83,0x20,0x21,0x3c,0x02,0xb0,0x03,0x90,0x86,0x00,0x07,0x34,0x42,0x01,0x00, ++0x8e,0x23,0x00,0x08,0x90,0x44,0x00,0x00,0x2c,0xc5,0x00,0x04,0x24,0x02,0x00,0x10, ++0x24,0x10,0x00,0x0a,0x00,0x45,0x80,0x0a,0x00,0x03,0x1e,0x43,0x30,0x84,0x00,0x01, ++0x30,0x65,0x00,0x01,0x14,0x80,0x00,0x02,0x00,0x10,0x10,0x40,0x02,0x00,0x10,0x21, ++0x00,0xc0,0x20,0x21,0x24,0x06,0x00,0x20,0x0c,0x00,0x08,0xe3,0x30,0x50,0x00,0xff, ++0x86,0x44,0x00,0x0c,0x27,0x85,0x90,0x10,0x3c,0x06,0xb0,0x09,0x00,0x04,0x18,0xc0, ++0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x65,0x18,0x21,0x80,0x64,0x00,0x06, ++0x00,0x50,0x10,0x21,0x34,0xc6,0x01,0x02,0x24,0x85,0x00,0x03,0x28,0x83,0x00,0x00, ++0x00,0xa3,0x20,0x0b,0x00,0x04,0x20,0x83,0x00,0x04,0x20,0x80,0xa4,0xc2,0x00,0x00, ++0x02,0x24,0x20,0x21,0x8c,0x83,0x00,0x04,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x10, ++0xac,0x43,0x00,0x00,0x8c,0x86,0x00,0x08,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x14, ++0xa4,0x46,0x00,0x00,0x8c,0x85,0x00,0x0c,0x8c,0x82,0x00,0x08,0x3c,0x06,0xb0,0x09, ++0x00,0x05,0x2c,0x00,0x00,0x02,0x14,0x02,0x00,0xa2,0x28,0x21,0x34,0xc6,0x01,0x20, ++0xac,0xc5,0x00,0x00,0x8c,0x83,0x00,0x0c,0x3c,0x05,0xb0,0x09,0x34,0xa5,0x01,0x24, ++0x00,0x03,0x1c,0x02,0xa4,0xa3,0x00,0x00,0x92,0x42,0x00,0x0a,0x3c,0x03,0xb0,0x09, ++0x34,0x63,0x01,0x30,0x00,0x02,0x13,0x00,0x24,0x42,0x00,0x04,0x30,0x42,0xff,0xff, ++0xa4,0x62,0x00,0x00,0x86,0x44,0x00,0x0c,0x27,0x83,0x90,0x18,0x8f,0xbf,0x00,0x1c, ++0x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21, ++0x94,0x44,0x00,0x02,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x3c,0x05,0xb0,0x09, ++0x34,0xa5,0x01,0x32,0xa4,0xa4,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20, ++0x27,0xbd,0xff,0xe0,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,0xaf,0xb0,0x00,0x10, ++0x34,0x42,0x00,0x20,0x00,0xa0,0x80,0x21,0x24,0x63,0x34,0xc0,0x00,0x05,0x2c,0x43, ++0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x18,0xac,0x43,0x00,0x00,0x10,0xa0,0x00,0x05, ++0x00,0x80,0x88,0x21,0x8c,0x82,0x00,0x34,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0xb6, ++0x00,0x00,0x00,0x00,0x32,0x10,0x00,0xff,0x12,0x00,0x00,0x4c,0x00,0x00,0x10,0x21, ++0x24,0x02,0x00,0x08,0x12,0x02,0x00,0xa3,0x2a,0x02,0x00,0x09,0x10,0x40,0x00,0x89, ++0x24,0x02,0x00,0x40,0x24,0x04,0x00,0x02,0x12,0x04,0x00,0x79,0x2a,0x02,0x00,0x03, ++0x10,0x40,0x00,0x69,0x24,0x02,0x00,0x04,0x24,0x02,0x00,0x01,0x12,0x02,0x00,0x5a, ++0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05,0x34,0x42,0x00,0x08,0x3c,0x03,0x80,0x00, ++0xa2,0x20,0x00,0x4e,0xac,0x43,0x00,0x00,0x82,0x24,0x00,0x11,0x92,0x27,0x00,0x11, ++0x10,0x80,0x00,0x4e,0x00,0x00,0x00,0x00,0x92,0x26,0x00,0x0a,0x24,0x02,0x00,0x12, ++0x10,0x46,0x00,0x09,0x30,0xc2,0x00,0xff,0x27,0x83,0xb4,0x00,0x00,0x02,0x10,0x80, ++0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x94,0x83,0x00,0x14, ++0x00,0x00,0x00,0x00,0xa6,0x23,0x00,0x0c,0x3c,0x02,0xb0,0x09,0x34,0x42,0x00,0x40, ++0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x03,0xa2,0x23,0x00,0x10, ++0x14,0x60,0x00,0x2b,0x30,0x65,0x00,0x01,0x30,0xc2,0x00,0xff,0x27,0x83,0xb4,0x00, ++0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x82,0x23,0x00,0x12, ++0x90,0x82,0x00,0x16,0x00,0x00,0x00,0x00,0x00,0x02,0x11,0x42,0x30,0x42,0x00,0x01, ++0x00,0x62,0x18,0x21,0x00,0x03,0x26,0x00,0x14,0x80,0x00,0x18,0xa2,0x23,0x00,0x12, ++0x00,0x07,0x16,0x00,0x14,0x40,0x00,0x11,0x24,0x02,0x00,0x01,0x96,0x23,0x00,0x0c, ++0x27,0x84,0x90,0x10,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80, ++0x00,0x44,0x10,0x21,0x80,0x45,0x00,0x06,0x00,0x03,0x1a,0x00,0x3c,0x02,0xb0,0x00, ++0x00,0x65,0x18,0x21,0x00,0x62,0x18,0x21,0x90,0x64,0x00,0x00,0x90,0x62,0x00,0x04, ++0xa2,0x20,0x00,0x15,0xa3,0x80,0x8b,0xd4,0x24,0x02,0x00,0x01,0x8f,0xbf,0x00,0x18, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x0c,0x00,0x0c,0xcd, ++0x02,0x20,0x20,0x21,0x92,0x27,0x00,0x11,0x08,0x00,0x0d,0x7d,0x00,0x07,0x16,0x00, ++0x0c,0x00,0x0c,0x6e,0x02,0x20,0x20,0x21,0x86,0x23,0x00,0x0c,0x27,0x84,0x90,0x08, ++0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x44,0x20,0x21, ++0x90,0x85,0x00,0x07,0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,0xa2,0x25,0x00,0x13, ++0x90,0x83,0x00,0x07,0x08,0x00,0x0d,0x95,0xa0,0x43,0x00,0x02,0x92,0x26,0x00,0x0a, ++0x08,0x00,0x0d,0x5e,0x30,0xc2,0x00,0xff,0x8e,0x22,0x00,0x24,0x00,0x00,0x00,0x00, ++0x10,0x50,0x00,0x07,0xa2,0x20,0x00,0x08,0x24,0x02,0x00,0x07,0xa2,0x22,0x00,0x0a, ++0x92,0x22,0x00,0x27,0xae,0x20,0x00,0x24,0x08,0x00,0x0d,0x51,0xa2,0x22,0x00,0x04, ++0x08,0x00,0x0d,0xaf,0x24,0x02,0x00,0x06,0x16,0x02,0xff,0x9b,0x3c,0x02,0xb0,0x05, ++0x8e,0x23,0x00,0x2c,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x07,0xa2,0x24,0x00,0x08, ++0x24,0x02,0x00,0x03,0xa2,0x22,0x00,0x0a,0x92,0x22,0x00,0x2f,0xae,0x20,0x00,0x2c, ++0x08,0x00,0x0d,0x51,0xa2,0x22,0x00,0x06,0x08,0x00,0x0d,0xbe,0xa2,0x20,0x00,0x0a, ++0x8e,0x22,0x00,0x28,0x24,0x03,0x00,0x01,0x24,0x04,0x00,0x01,0x10,0x44,0x00,0x07, ++0xa2,0x23,0x00,0x08,0x24,0x02,0x00,0x05,0xa2,0x22,0x00,0x0a,0x92,0x22,0x00,0x2b, ++0xae,0x20,0x00,0x28,0x08,0x00,0x0d,0x51,0xa2,0x22,0x00,0x05,0x08,0x00,0x0d,0xca, ++0x24,0x02,0x00,0x04,0x12,0x02,0x00,0x12,0x2a,0x02,0x00,0x41,0x10,0x40,0x00,0x09, ++0x24,0x02,0x00,0x80,0x24,0x02,0x00,0x20,0x16,0x02,0xff,0x7b,0x3c,0x02,0xb0,0x05, ++0x24,0x02,0x00,0x12,0xa2,0x22,0x00,0x0a,0xa2,0x22,0x00,0x08,0x08,0x00,0x0d,0x51, ++0xae,0x20,0x00,0x3c,0x16,0x02,0xff,0x74,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x10, ++0xa2,0x22,0x00,0x0a,0xa2,0x22,0x00,0x08,0x08,0x00,0x0d,0x51,0xae,0x20,0x00,0x34, ++0x24,0x02,0x00,0x11,0xa2,0x22,0x00,0x0a,0xa2,0x22,0x00,0x08,0x08,0x00,0x0d,0x51, ++0xae,0x20,0x00,0x38,0x8e,0x24,0x00,0x30,0x24,0x02,0x00,0x03,0x24,0x03,0x00,0x01, ++0x10,0x83,0x00,0x07,0xa2,0x22,0x00,0x08,0x24,0x02,0x00,0x02,0xa2,0x22,0x00,0x0a, ++0x92,0x22,0x00,0x33,0xae,0x20,0x00,0x30,0x08,0x00,0x0d,0x51,0xa2,0x22,0x00,0x07, ++0x08,0x00,0x0d,0xf0,0xa2,0x24,0x00,0x0a,0x8f,0x84,0xb4,0x40,0xae,0x20,0x00,0x34, ++0x94,0x85,0x00,0x14,0x0c,0x00,0x1b,0x66,0x32,0x10,0x00,0xff,0x08,0x00,0x0d,0x42, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x37,0xf4, ++0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00,0x80,0xa2,0x00,0x15,0x3c,0x06,0xb0,0x05, ++0x10,0x40,0x00,0x0a,0x34,0xc6,0x02,0x54,0x83,0x83,0x8b,0xd4,0x00,0x00,0x00,0x00, ++0xac,0x83,0x00,0x24,0x8c,0xc2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x17,0x42, ++0x30,0x42,0x00,0x01,0x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x28,0x8c,0x82,0x00,0x2c, ++0x3c,0x06,0xb0,0x05,0x34,0xc6,0x04,0x50,0x00,0x02,0x18,0x43,0x30,0x63,0x00,0x01, ++0x10,0x40,0x00,0x04,0x30,0x45,0x00,0x01,0xac,0x83,0x00,0x28,0x03,0xe0,0x00,0x08, ++0xac,0x85,0x00,0x24,0x90,0xc2,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff, ++0x30,0x43,0x00,0x02,0x30,0x42,0x00,0x01,0xac,0x83,0x00,0x28,0x03,0xe0,0x00,0x08, ++0xac,0x82,0x00,0x24,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xd8, ++0x34,0x63,0x00,0x20,0x24,0x42,0x38,0x84,0xac,0x62,0x00,0x00,0xaf,0xb1,0x00,0x1c, ++0xaf,0xbf,0x00,0x20,0xaf,0xb0,0x00,0x18,0x90,0xa6,0x00,0x0a,0x27,0x83,0xb4,0x00, ++0x00,0xa0,0x88,0x21,0x00,0x06,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x50,0x00,0x00, ++0x80,0xa5,0x00,0x11,0x92,0x03,0x00,0x12,0x10,0xa0,0x00,0x04,0xa2,0x20,0x00,0x15, ++0x24,0x02,0x00,0x12,0x10,0xc2,0x00,0xda,0x00,0x00,0x00,0x00,0x82,0x22,0x00,0x12, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x67,0x00,0x00,0x00,0x00,0xa2,0x20,0x00,0x12, ++0xa2,0x00,0x00,0x19,0x86,0x23,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x20,0x00,0x43,0x10,0x21, ++0xa0,0x40,0x00,0x00,0x92,0x03,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0xdf, ++0xa2,0x03,0x00,0x16,0x82,0x02,0x00,0x12,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x20, ++0x00,0x00,0x00,0x00,0x92,0x23,0x00,0x08,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x45, ++0x24,0x02,0x00,0x01,0xa2,0x20,0x00,0x04,0x92,0x08,0x00,0x04,0x00,0x00,0x00,0x00, ++0x15,0x00,0x00,0x1e,0x24,0x02,0x00,0x01,0x92,0x07,0x00,0x0a,0xa2,0x02,0x00,0x17, ++0x92,0x02,0x00,0x16,0x30,0xe3,0x00,0xff,0x30,0x42,0x00,0xe4,0x10,0x60,0x00,0x03, ++0xa2,0x02,0x00,0x16,0x34,0x42,0x00,0x01,0xa2,0x02,0x00,0x16,0x11,0x00,0x00,0x05, ++0x00,0x00,0x00,0x00,0x92,0x02,0x00,0x16,0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02, ++0xa2,0x02,0x00,0x16,0x92,0x02,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x08, ++0x00,0x00,0x00,0x00,0x96,0x02,0x00,0x06,0x00,0x00,0x00,0x00,0xa6,0x02,0x00,0x14, ++0x8f,0xbf,0x00,0x20,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28, ++0x96,0x02,0x00,0x00,0x08,0x00,0x0e,0x6c,0xa6,0x02,0x00,0x14,0x92,0x07,0x00,0x0a, ++0x00,0x00,0x00,0x00,0x14,0xe0,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x0e,0x58, ++0xa2,0x00,0x00,0x17,0x96,0x04,0x00,0x00,0x96,0x05,0x00,0x06,0x27,0x86,0x90,0x00, ++0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21, ++0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,0x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21, ++0x8c,0x66,0x00,0x08,0x8c,0x45,0x00,0x08,0x3c,0x03,0x80,0x00,0x00,0xc3,0x20,0x24, ++0x10,0x80,0x00,0x08,0x00,0xa3,0x10,0x24,0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21, ++0x10,0x80,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0xa6,0x18,0x2b,0x08,0x00,0x0e,0x58, ++0xa2,0x03,0x00,0x17,0x10,0x40,0xff,0xfd,0x00,0xa6,0x18,0x2b,0x08,0x00,0x0e,0x8c, ++0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x09,0x24,0x02,0x00,0x02,0x10,0x62,0x00,0x05, ++0x24,0x02,0x00,0x03,0x14,0x62,0xff,0xb8,0x00,0x00,0x00,0x00,0x08,0x00,0x0e,0x52, ++0xa2,0x20,0x00,0x07,0x08,0x00,0x0e,0x52,0xa2,0x20,0x00,0x06,0x08,0x00,0x0e,0x52, ++0xa2,0x20,0x00,0x05,0x82,0x22,0x00,0x10,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x69, ++0x2c,0x62,0x00,0x02,0x10,0x40,0x00,0x49,0x3c,0x02,0xb0,0x09,0x92,0x25,0x00,0x08, ++0x00,0x00,0x00,0x00,0x30,0xa6,0x00,0xff,0x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x3b, ++0x2c,0xc2,0x00,0x10,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00, ++0x24,0x02,0x00,0x01,0x00,0xc2,0x10,0x04,0x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24, ++0xa0,0x83,0x00,0x00,0x86,0x23,0x00,0x0c,0x96,0x26,0x00,0x0c,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x00,0x02,0x28,0x80,0x27,0x83,0x90,0x04,0x00,0xa3,0x18,0x21, ++0x8c,0x64,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x04,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0x10,0x10,0x40,0x00,0x18,0x24,0x07,0x00,0x01,0x93,0x82,0x8b,0x71, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x0a,0x24,0x05,0x00,0x24, ++0x00,0x06,0x2c,0x00,0x00,0x05,0x2c,0x03,0x0c,0x00,0x1b,0x66,0x02,0x00,0x20,0x21, ++0x92,0x02,0x00,0x16,0xa2,0x00,0x00,0x12,0x30,0x42,0x00,0xe7,0x08,0x00,0x0e,0x49, ++0xa2,0x02,0x00,0x16,0xf0,0xc5,0x00,0x06,0x00,0x00,0x28,0x12,0x27,0x82,0x90,0x00, ++0x00,0xa2,0x28,0x21,0x0c,0x00,0x01,0x49,0x3c,0x04,0x00,0x80,0x96,0x26,0x00,0x0c, ++0x08,0x00,0x0e,0xc9,0x00,0x06,0x2c,0x00,0x27,0x83,0x90,0x10,0x27,0x82,0x90,0x18, ++0x00,0xa2,0x10,0x21,0x00,0xa3,0x18,0x21,0x90,0x44,0x00,0x00,0x90,0x65,0x00,0x05, ++0x93,0x82,0x80,0x10,0x00,0x00,0x30,0x21,0x0c,0x00,0x21,0x9a,0xaf,0xa2,0x00,0x10, ++0x96,0x26,0x00,0x0c,0x08,0x00,0x0e,0xc3,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xcd, ++0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x30,0xa5,0x00,0x0f, ++0x24,0x02,0x00,0x80,0x08,0x00,0x0e,0xb2,0x00,0xa2,0x10,0x07,0x86,0x26,0x00,0x0c, ++0x3c,0x03,0xb0,0x09,0x34,0x42,0x01,0x72,0x34,0x63,0x01,0x78,0x94,0x47,0x00,0x00, ++0x8c,0x65,0x00,0x00,0x00,0x06,0x10,0xc0,0x00,0x46,0x10,0x21,0x3c,0x04,0xb0,0x09, ++0xae,0x25,0x00,0x1c,0x34,0x84,0x01,0x7c,0x27,0x83,0x90,0x04,0x00,0x02,0x10,0x80, ++0x8c,0x85,0x00,0x00,0x00,0x43,0x10,0x21,0x8c,0x43,0x00,0x18,0xae,0x25,0x00,0x20, ++0xa6,0x27,0x00,0x18,0x8c,0x66,0x00,0x08,0x02,0x20,0x20,0x21,0x0c,0x00,0x0f,0x19, ++0x00,0x00,0x28,0x21,0x86,0x25,0x00,0x18,0x8e,0x26,0x00,0x1c,0x8e,0x27,0x00,0x20, ++0x02,0x20,0x20,0x21,0x0c,0x00,0x1c,0x68,0xaf,0xa2,0x00,0x10,0x08,0x00,0x0e,0x49, ++0xa2,0x02,0x00,0x12,0x92,0x22,0x00,0x08,0x08,0x00,0x0e,0x49,0xa2,0x22,0x00,0x09, ++0xa2,0x20,0x00,0x11,0x80,0x82,0x00,0x50,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x03, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xd0,0xac,0x40,0x00,0x00,0x08,0x00,0x0e,0x49, ++0xa0,0x80,0x00,0x50,0x94,0x8a,0x00,0x0c,0x24,0x03,0x00,0x24,0x00,0x80,0x70,0x21, ++0x3c,0x02,0x80,0x00,0x3c,0x04,0xb0,0x03,0x24,0x42,0x3c,0x64,0xf1,0x43,0x00,0x06, ++0x34,0x84,0x00,0x20,0x00,0x00,0x18,0x12,0x00,0xa0,0x68,0x21,0xac,0x82,0x00,0x00, ++0x27,0x85,0x90,0x10,0x27,0x82,0x90,0x0f,0x27,0xbd,0xff,0xf8,0x00,0x62,0x60,0x21, ++0x00,0x65,0x58,0x21,0x00,0x00,0xc0,0x21,0x11,0xa0,0x00,0xcc,0x00,0x00,0x78,0x21, ++0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21, ++0x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x91,0x87,0x00,0x00,0x80,0x48,0x00,0x04, ++0x03,0xa0,0x60,0x21,0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x00,0x02,0x48,0x80,0x27,0x83,0x90,0x04,0xa3,0xa7,0x00,0x00, ++0x01,0x23,0x18,0x21,0x8c,0x64,0x00,0x18,0x25,0x02,0xff,0xff,0x00,0x48,0x40,0x0b, ++0x8c,0x83,0x00,0x04,0x2d,0x05,0x00,0x07,0x24,0x02,0x00,0x06,0x30,0x63,0x00,0x08, ++0x14,0x60,0x00,0x35,0x00,0x45,0x40,0x0a,0x93,0xa7,0x00,0x00,0x27,0x82,0x90,0x18, ++0x01,0x22,0x10,0x21,0x30,0xe3,0x00,0xf0,0x38,0x63,0x00,0x50,0x30,0xe5,0x00,0xff, ++0x00,0x05,0x20,0x2b,0x00,0x03,0x18,0x2b,0x00,0x64,0x18,0x24,0x90,0x49,0x00,0x00, ++0x10,0x60,0x00,0x16,0x30,0xe4,0x00,0x0f,0x24,0x02,0x00,0x04,0x10,0xa2,0x00,0x9d, ++0x00,0x00,0x00,0x00,0x11,0xa0,0x00,0x3a,0x2c,0xa2,0x00,0x0c,0x10,0x40,0x00,0x02, ++0x24,0x84,0x00,0x0c,0x00,0xe0,0x20,0x21,0x30,0x84,0x00,0xff,0x00,0x04,0x10,0x40, ++0x27,0x83,0xbb,0x1c,0x00,0x44,0x10,0x21,0x00,0x43,0x10,0x21,0x90,0x47,0x00,0x00, ++0x00,0x00,0x00,0x00,0x2c,0xe3,0x00,0x0c,0xa3,0xa7,0x00,0x00,0x10,0x60,0x00,0x02, ++0x24,0xe2,0x00,0x04,0x00,0xe0,0x10,0x21,0xa3,0xa2,0x00,0x00,0x91,0x65,0x00,0x00, ++0x91,0x82,0x00,0x00,0x30,0xa3,0x00,0xff,0x00,0x62,0x10,0x2b,0x10,0x40,0x00,0x0e, ++0x2c,0x62,0x00,0x0c,0x14,0x40,0x00,0x03,0x00,0x60,0x20,0x21,0x30,0xa2,0x00,0x0f, ++0x24,0x44,0x00,0x0c,0x00,0x04,0x10,0x40,0x00,0x44,0x20,0x21,0x27,0x83,0xbb,0x1c, ++0x00,0x83,0x18,0x21,0x90,0x62,0x00,0x02,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x05, ++0x00,0x09,0x11,0x00,0xa1,0x85,0x00,0x00,0x93,0xa2,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x08,0x00,0x49,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x49,0x10,0x23, ++0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,0x27,0x83,0xb4,0xa8,0x00,0x43,0x10,0x21, ++0x90,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x83,0x00,0x0c,0x14,0x60,0x00,0x06, ++0x00,0x80,0x10,0x21,0x00,0x18,0x10,0x40,0x00,0x4f,0x10,0x21,0x00,0x02,0x11,0x00, ++0x00,0x82,0x10,0x21,0x24,0x42,0x00,0x04,0x08,0x00,0x0f,0x7a,0xa1,0x82,0x00,0x00, ++0x8f,0x8d,0x81,0x5c,0x00,0x00,0x00,0x00,0x01,0xa8,0x10,0x21,0x90,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x10,0x60,0xff,0xd1,0x00,0x00,0x28,0x21,0x00,0x06,0x74,0x82, ++0x30,0xe2,0x00,0xff,0x2c,0x42,0x00,0x0c,0x14,0x40,0x00,0x03,0x00,0xe0,0x10,0x21, ++0x30,0xe2,0x00,0x0f,0x24,0x42,0x00,0x0c,0x30,0x44,0x00,0xff,0xa3,0xa2,0x00,0x00, ++0x24,0x02,0x00,0x0c,0x10,0x82,0x00,0x0d,0x00,0x09,0x11,0x00,0x00,0x49,0x10,0x23, ++0x00,0x02,0x10,0x80,0x00,0x04,0x18,0x40,0x00,0x49,0x10,0x23,0x00,0x64,0x18,0x21, ++0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x27,0x84,0xb4,0xa8,0x00,0x44,0x10,0x21, ++0x90,0x47,0x00,0x00,0x00,0x00,0x00,0x00,0xa3,0xa7,0x00,0x00,0x00,0x0a,0x1c,0x00, ++0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80, ++0x27,0x83,0x90,0x04,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x18,0x00,0x00,0x00,0x00, ++0x8c,0x83,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10,0x14,0x60,0x00,0x33, ++0x00,0x06,0x14,0x42,0x00,0x09,0x11,0x00,0x00,0x49,0x10,0x23,0x00,0x02,0x10,0x80, ++0x00,0x49,0x10,0x23,0x27,0x83,0xb5,0x78,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21, ++0x90,0x44,0x00,0x04,0x90,0x43,0x00,0x05,0x00,0x00,0x00,0x00,0x00,0x64,0xc0,0x24, ++0x93,0xa7,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0xe2,0x00,0x0f,0x10,0x40,0x00,0x0f, ++0x31,0xcf,0x00,0x01,0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x84,0x90,0x00,0x00,0x44,0x10,0x21, ++0x84,0x43,0x00,0x06,0x00,0x00,0x00,0x00,0x28,0x63,0x06,0x41,0x14,0x60,0x00,0x04, ++0x30,0xe2,0x00,0xff,0x24,0x07,0x00,0x0f,0xa3,0xa7,0x00,0x00,0x30,0xe2,0x00,0xff, ++0x2c,0x42,0x00,0x0c,0x14,0x40,0x00,0x06,0x00,0xe0,0x10,0x21,0x00,0x18,0x10,0x40, ++0x00,0x4f,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0x47,0x10,0x21,0x24,0x42,0x00,0x04, ++0xa3,0xa2,0x00,0x00,0x00,0x40,0x38,0x21,0x01,0xa8,0x10,0x21,0x90,0x43,0x00,0x00, ++0x24,0xa4,0x00,0x01,0x30,0x85,0xff,0xff,0x00,0xa3,0x18,0x2b,0x14,0x60,0xff,0xad, ++0x30,0xe2,0x00,0xff,0x08,0x00,0x0f,0x67,0x00,0x00,0x00,0x00,0x08,0x00,0x0f,0xc8, ++0x30,0x58,0x00,0x01,0x81,0xc2,0x00,0x48,0x00,0x00,0x00,0x00,0x10,0x40,0xff,0x73, ++0x00,0x00,0x00,0x00,0x08,0x00,0x0f,0x55,0x00,0x00,0x00,0x00,0x00,0x0a,0x1c,0x00, ++0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80, ++0x00,0x45,0x10,0x21,0x80,0x48,0x00,0x05,0x91,0x67,0x00,0x00,0x08,0x00,0x0f,0x35, ++0x03,0xa0,0x58,0x21,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20, ++0x24,0x42,0x40,0x04,0x03,0xe0,0x00,0x08,0xac,0x62,0x00,0x00,0x27,0xbd,0xff,0xc0, ++0xaf,0xb7,0x00,0x34,0xaf,0xb6,0x00,0x30,0xaf,0xb5,0x00,0x2c,0xaf,0xb4,0x00,0x28, ++0xaf,0xb3,0x00,0x24,0xaf,0xb2,0x00,0x20,0xaf,0xbf,0x00,0x3c,0xaf,0xbe,0x00,0x38, ++0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,0x84,0x82,0x00,0x0c,0x27,0x93,0x90,0x04, ++0x3c,0x05,0xb0,0x03,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80, ++0x00,0x73,0x10,0x21,0x8c,0x5e,0x00,0x18,0x3c,0x02,0x80,0x00,0x34,0xa5,0x00,0x20, ++0x24,0x42,0x40,0x1c,0xac,0xa2,0x00,0x00,0x8f,0xd0,0x00,0x08,0x27,0x95,0x90,0x10, ++0x00,0x75,0x18,0x21,0x00,0x00,0x28,0x21,0x02,0x00,0x30,0x21,0x90,0x71,0x00,0x00, ++0x0c,0x00,0x0f,0x19,0x00,0x80,0xb0,0x21,0x00,0x40,0x90,0x21,0x00,0x10,0x14,0x42, ++0x30,0x54,0x00,0x01,0x02,0x40,0x20,0x21,0x00,0x10,0x14,0x82,0x02,0x80,0x28,0x21, ++0x12,0x51,0x00,0x23,0x00,0x10,0xbf,0xc2,0x86,0xc3,0x00,0x0c,0x30,0x50,0x00,0x01, ++0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x55,0x10,0x21, ++0xa0,0x52,0x00,0x00,0x86,0xc3,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x53,0x30,0x21,0x8c,0xc7,0x00,0x18, ++0x27,0x83,0x90,0x00,0x00,0x43,0x10,0x21,0x8c,0xe3,0x00,0x04,0x84,0x46,0x00,0x06, ++0x00,0x03,0x19,0x42,0x0c,0x00,0x08,0xe3,0x30,0x73,0x00,0x01,0x00,0x40,0x88,0x21, ++0x02,0x40,0x20,0x21,0x02,0x80,0x28,0x21,0x16,0xe0,0x00,0x10,0x02,0x00,0x30,0x21, ++0x86,0xc2,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21, ++0x00,0x03,0x18,0x80,0x27,0x82,0x90,0x08,0x00,0x62,0x18,0x21,0xa4,0x71,0x00,0x04, ++0x7b,0xbe,0x01,0xfc,0x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c, ++0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,0x86,0xc3,0x00,0x0c, ++0xaf,0xb3,0x00,0x10,0xaf,0xa0,0x00,0x14,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21, ++0x00,0x02,0x10,0x80,0x00,0x55,0x10,0x21,0x80,0x47,0x00,0x06,0x00,0x00,0x00,0x00, ++0x24,0xe7,0x00,0x02,0x00,0x07,0x17,0xc2,0x00,0xe2,0x38,0x21,0x00,0x07,0x38,0x43, ++0x00,0x07,0x38,0x40,0x0c,0x00,0x09,0x0a,0x03,0xc7,0x38,0x21,0x08,0x00,0x10,0x48, ++0x02,0x22,0x88,0x21,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xd0, ++0x34,0x63,0x00,0x20,0x24,0x42,0x41,0xa4,0xaf,0xb2,0x00,0x20,0xac,0x62,0x00,0x00, ++0xaf,0xbf,0x00,0x28,0xaf,0xb3,0x00,0x24,0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18, ++0x3c,0x02,0xb0,0x03,0x90,0x83,0x00,0x0a,0x34,0x42,0x01,0x04,0x94,0x45,0x00,0x00, ++0x00,0x03,0x18,0x80,0x27,0x82,0xb4,0x00,0x00,0x62,0x18,0x21,0x30,0xa6,0xff,0xff, ++0x8c,0x71,0x00,0x00,0x80,0x85,0x00,0x12,0x30,0xc9,0x00,0xff,0x00,0x06,0x32,0x02, ++0xa4,0x86,0x00,0x44,0xa4,0x89,0x00,0x46,0x82,0x22,0x00,0x12,0x00,0x80,0x90,0x21, ++0x10,0xa0,0x00,0x1b,0xa0,0x80,0x00,0x15,0x00,0xc5,0x10,0x2a,0x10,0x40,0x00,0x14, ++0x00,0x00,0x00,0x00,0xa2,0x20,0x00,0x19,0x84,0x83,0x00,0x0c,0x00,0x00,0x00,0x00, ++0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x20, ++0x00,0x43,0x10,0x21,0xa0,0x40,0x00,0x00,0xa0,0x80,0x00,0x12,0x92,0x22,0x00,0x16, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xdf,0xa2,0x22,0x00,0x16,0x8f,0xbf,0x00,0x28, ++0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30, ++0x0c,0x00,0x10,0x01,0x00,0x00,0x00,0x00,0x08,0x00,0x10,0x97,0x00,0x00,0x00,0x00, ++0x28,0x42,0x00,0x02,0x10,0x40,0x01,0x76,0x00,0x00,0x28,0x21,0x94,0x87,0x00,0x0c, ++0x00,0x00,0x00,0x00,0x00,0xe0,0x10,0x21,0x00,0x02,0x14,0x00,0x00,0x02,0x14,0x03, ++0x00,0x07,0x24,0x00,0x00,0x04,0x24,0x03,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21, ++0x00,0x04,0x28,0xc0,0x00,0xa4,0x28,0x21,0x27,0x82,0x90,0x20,0x00,0x03,0x18,0x80, ++0x00,0x62,0x18,0x21,0x00,0x05,0x28,0x80,0x27,0x82,0x90,0x08,0x00,0xa2,0x10,0x21, ++0x8c,0x68,0x00,0x00,0x80,0x44,0x00,0x06,0x27,0x82,0x90,0x10,0x00,0x08,0x1d,0x02, ++0x00,0xa2,0x28,0x21,0x38,0x84,0x00,0x00,0x30,0x63,0x00,0x01,0x01,0x24,0x30,0x0b, ++0x80,0xaa,0x00,0x04,0x80,0xa9,0x00,0x05,0x10,0x60,0x00,0x02,0x00,0x08,0x14,0x02, ++0x30,0x46,0x00,0x0f,0x15,0x20,0x00,0x28,0x01,0x49,0x10,0x21,0x15,0x40,0x00,0x11, ++0x30,0xe3,0xff,0xff,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa8,0x00,0xff, ++0x2d,0x02,0x00,0x04,0x10,0x40,0x01,0x46,0x2d,0x02,0x00,0x10,0x3c,0x04,0xb0,0x05, ++0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,0x01,0x02,0x10,0x04, ++0x00,0x62,0x18,0x25,0xa0,0x83,0x00,0x00,0x96,0x47,0x00,0x0c,0x00,0x00,0x00,0x00, ++0x30,0xe3,0xff,0xff,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x27,0x84,0x90,0x10, ++0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,0x80,0x45,0x00,0x06,0x00,0x03,0x1a,0x00, ++0x3c,0x04,0xb0,0x00,0x00,0x65,0x18,0x21,0x00,0x64,0x20,0x21,0x94,0x82,0x00,0x00, ++0x82,0x43,0x00,0x10,0x00,0x02,0x14,0x00,0x14,0x60,0x00,0x06,0x00,0x02,0x3c,0x03, ++0x30,0xe2,0x00,0x04,0x14,0x40,0x00,0x04,0x01,0x49,0x10,0x21,0x34,0xe2,0x08,0x00, ++0xa4,0x82,0x00,0x00,0x01,0x49,0x10,0x21,0x00,0x02,0x16,0x00,0x00,0x02,0x16,0x03, ++0x00,0x46,0x10,0x2a,0x10,0x40,0x00,0x7c,0x00,0x00,0x00,0x00,0x82,0x42,0x00,0x10, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0e,0x00,0x00,0x00,0x00,0x86,0x43,0x00,0x0c, ++0x25,0x44,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80, ++0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,0xa0,0x44,0x00,0x04,0x92,0x23,0x00,0x16, ++0x02,0x40,0x20,0x21,0x30,0x63,0x00,0xfb,0x08,0x00,0x10,0x9c,0xa2,0x23,0x00,0x16, ++0x86,0x43,0x00,0x0c,0x25,0x24,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21, ++0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,0xa0,0x44,0x00,0x05, ++0x86,0x45,0x00,0x0c,0x0c,0x00,0x1e,0xea,0x02,0x20,0x20,0x21,0x10,0x40,0x00,0x5a, ++0x00,0x00,0x00,0x00,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa6,0x00,0xff, ++0x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x4c,0x2c,0xc2,0x00,0x10,0x3c,0x04,0xb0,0x05, ++0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,0x00,0xc2,0x10,0x04, ++0x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24,0xa0,0x83,0x00,0x00,0x92,0x45,0x00,0x08, ++0x00,0x00,0x00,0x00,0x30,0xa5,0x00,0xff,0x14,0xa0,0x00,0x33,0x24,0x02,0x00,0x01, ++0xa2,0x40,0x00,0x04,0x92,0x22,0x00,0x04,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x0c, ++0x24,0x02,0x00,0x01,0xa2,0x22,0x00,0x17,0x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00, ++0x10,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0x96,0x22,0x00,0x06,0x08,0x00,0x10,0x97, ++0xa6,0x22,0x00,0x14,0x96,0x22,0x00,0x00,0x08,0x00,0x10,0x97,0xa6,0x22,0x00,0x14, ++0x92,0x22,0x00,0x0a,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03,0x00,0x00,0x00,0x00, ++0x08,0x00,0x11,0x26,0xa2,0x20,0x00,0x17,0x96,0x24,0x00,0x00,0x96,0x25,0x00,0x06, ++0x27,0x86,0x90,0x00,0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x05,0x10,0xc0, ++0x00,0x45,0x10,0x21,0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,0x00,0x02,0x10,0x80, ++0x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08,0x8c,0x44,0x00,0x08,0x3c,0x03,0x80,0x00, ++0x00,0xa3,0x30,0x24,0x10,0xc0,0x00,0x08,0x00,0x83,0x10,0x24,0x10,0x40,0x00,0x04, ++0x00,0x00,0x18,0x21,0x10,0xc0,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b, ++0x08,0x00,0x11,0x26,0xa2,0x23,0x00,0x17,0x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b, ++0x08,0x00,0x11,0x49,0x00,0x00,0x00,0x00,0x10,0xa2,0x00,0x09,0x24,0x02,0x00,0x02, ++0x10,0xa2,0x00,0x05,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xca,0x00,0x00,0x00,0x00, ++0x08,0x00,0x11,0x21,0xa2,0x40,0x00,0x07,0x08,0x00,0x11,0x21,0xa2,0x40,0x00,0x06, ++0x08,0x00,0x11,0x21,0xa2,0x40,0x00,0x05,0x14,0x40,0xff,0xbe,0x3c,0x04,0xb0,0x05, ++0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80, ++0x08,0x00,0x11,0x18,0x00,0xa2,0x10,0x07,0x0c,0x00,0x10,0x07,0x02,0x40,0x20,0x21, ++0x08,0x00,0x10,0x97,0x00,0x00,0x00,0x00,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00, ++0x30,0xa6,0x00,0xff,0x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x99,0x2c,0xc2,0x00,0x10, ++0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01, ++0x00,0xc2,0x10,0x04,0x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24,0xa0,0x83,0x00,0x00, ++0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa5,0x00,0xff,0x14,0xa0,0x00,0x80, ++0x24,0x02,0x00,0x01,0xa2,0x40,0x00,0x04,0x86,0x43,0x00,0x0c,0x27,0x93,0x90,0x04, ++0x96,0x47,0x00,0x0c,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x28,0x80, ++0x00,0xb3,0x18,0x21,0x8c,0x64,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x04, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x10,0x10,0x40,0x00,0x64,0x00,0x00,0x30,0x21, ++0x00,0x07,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21, ++0x00,0x02,0x10,0x80,0x00,0x53,0x10,0x21,0x8c,0x43,0x00,0x18,0x93,0x82,0x8b,0x71, ++0x8c,0x64,0x00,0x04,0x30,0x42,0x00,0x01,0x00,0x04,0x21,0x42,0x14,0x40,0x00,0x4d, ++0x30,0x90,0x00,0x01,0x00,0x07,0x2c,0x00,0x00,0x05,0x2c,0x03,0x0c,0x00,0x1b,0x66, ++0x02,0x20,0x20,0x21,0x96,0x26,0x00,0x06,0x12,0x00,0x00,0x14,0x30,0xc5,0xff,0xff, ++0x02,0x60,0x90,0x21,0x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21,0x00,0x02,0x10,0x80, ++0x00,0x52,0x18,0x21,0x92,0x22,0x00,0x0a,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0b, ++0x02,0x20,0x20,0x21,0x8c,0x63,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x62,0x00,0x04, ++0x00,0x00,0x00,0x00,0x00,0x02,0x11,0x42,0x0c,0x00,0x1b,0x66,0x30,0x50,0x00,0x01, ++0x96,0x26,0x00,0x06,0x16,0x00,0xff,0xef,0x30,0xc5,0xff,0xff,0x92,0x22,0x00,0x04, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x0d,0x24,0x02,0x00,0x01,0xa2,0x22,0x00,0x17, ++0x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x05,0x00,0x00,0x00,0x00, ++0xa6,0x26,0x00,0x14,0x92,0x22,0x00,0x16,0x08,0x00,0x10,0x96,0x30,0x42,0x00,0xc3, ++0x96,0x22,0x00,0x00,0x08,0x00,0x11,0xbd,0xa6,0x22,0x00,0x14,0x92,0x22,0x00,0x0a, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x11,0xb8, ++0xa2,0x20,0x00,0x17,0x96,0x24,0x00,0x00,0x30,0xc5,0xff,0xff,0x00,0x05,0x18,0xc0, ++0x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x00,0x65,0x18,0x21,0x27,0x84,0x90,0x00, ++0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,0x00,0x03,0x18,0x80,0x8c,0x45,0x00,0x08, ++0x00,0x64,0x18,0x21,0x8c,0x64,0x00,0x08,0x3c,0x02,0x80,0x00,0x00,0xa2,0x38,0x24, ++0x10,0xe0,0x00,0x08,0x00,0x82,0x10,0x24,0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21, ++0x10,0xe0,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b,0x08,0x00,0x11,0xb8, ++0xa2,0x23,0x00,0x17,0x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b,0x08,0x00,0x11,0xdc, ++0x00,0x00,0x00,0x00,0x24,0x05,0x00,0x24,0xf0,0xe5,0x00,0x06,0x00,0x00,0x28,0x12, ++0x27,0x82,0x90,0x00,0x00,0xa2,0x28,0x21,0x0c,0x00,0x01,0x49,0x00,0x00,0x20,0x21, ++0x96,0x47,0x00,0x0c,0x08,0x00,0x11,0x9a,0x00,0x07,0x2c,0x00,0x27,0x83,0x90,0x10, ++0x27,0x82,0x90,0x18,0x00,0xa2,0x10,0x21,0x00,0xa3,0x18,0x21,0x90,0x44,0x00,0x00, ++0x90,0x65,0x00,0x05,0x93,0x82,0x80,0x10,0x24,0x07,0x00,0x01,0x0c,0x00,0x21,0x9a, ++0xaf,0xa2,0x00,0x10,0x96,0x47,0x00,0x0c,0x08,0x00,0x11,0x8d,0x00,0x07,0x1c,0x00, ++0x10,0xa2,0x00,0x09,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x05,0x24,0x02,0x00,0x03, ++0x14,0xa2,0xff,0x7d,0x00,0x00,0x00,0x00,0x08,0x00,0x11,0x7e,0xa2,0x40,0x00,0x07, ++0x08,0x00,0x11,0x7e,0xa2,0x40,0x00,0x06,0x08,0x00,0x11,0x7e,0xa2,0x40,0x00,0x05, ++0x14,0x40,0xff,0x71,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00, ++0x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80,0x08,0x00,0x11,0x75,0x00,0xa2,0x10,0x07, ++0x14,0x40,0xfe,0xc3,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00, ++0x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80,0x08,0x00,0x10,0xd0,0x00,0xa2,0x10,0x07, ++0x84,0x83,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21, ++0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x04,0x00,0x43,0x10,0x21,0x8c,0x47,0x00,0x18, ++0x00,0x00,0x00,0x00,0x8c,0xe6,0x00,0x08,0x0c,0x00,0x0f,0x19,0x00,0x00,0x00,0x00, ++0x02,0x40,0x20,0x21,0x00,0x00,0x28,0x21,0x00,0x00,0x30,0x21,0x00,0x00,0x38,0x21, ++0x0c,0x00,0x1c,0x68,0xaf,0xa2,0x00,0x10,0x00,0x02,0x1e,0x00,0x14,0x60,0xfe,0x6b, ++0xa2,0x22,0x00,0x12,0x92,0x43,0x00,0x08,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x40, ++0x24,0x02,0x00,0x01,0xa2,0x40,0x00,0x04,0x92,0x28,0x00,0x04,0x00,0x00,0x00,0x00, ++0x15,0x00,0x00,0x19,0x24,0x02,0x00,0x01,0x92,0x27,0x00,0x0a,0xa2,0x22,0x00,0x17, ++0x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x10,0x00,0x00,0x00,0x00, ++0x96,0x22,0x00,0x06,0x00,0x00,0x00,0x00,0xa6,0x22,0x00,0x14,0x92,0x22,0x00,0x16, ++0x30,0xe3,0x00,0xff,0x30,0x42,0x00,0xc0,0x10,0x60,0x00,0x03,0xa2,0x22,0x00,0x16, ++0x34,0x42,0x00,0x01,0xa2,0x22,0x00,0x16,0x11,0x00,0xfe,0x50,0x00,0x00,0x00,0x00, ++0x92,0x22,0x00,0x16,0x08,0x00,0x10,0x96,0x34,0x42,0x00,0x02,0x96,0x22,0x00,0x00, ++0x08,0x00,0x12,0x3f,0xa6,0x22,0x00,0x14,0x92,0x27,0x00,0x0a,0x00,0x00,0x00,0x00, ++0x14,0xe0,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x12,0x38,0xa2,0x20,0x00,0x17, ++0x96,0x24,0x00,0x00,0x96,0x25,0x00,0x06,0x27,0x86,0x90,0x00,0x00,0x04,0x18,0xc0, ++0x00,0x64,0x18,0x21,0x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21,0x00,0x03,0x18,0x80, ++0x00,0x66,0x18,0x21,0x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08, ++0x8c,0x44,0x00,0x08,0x3c,0x03,0x80,0x00,0x00,0xa3,0x30,0x24,0x10,0xc0,0x00,0x08, ++0x00,0x83,0x10,0x24,0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21,0x10,0xc0,0x00,0x02, ++0x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b,0x08,0x00,0x12,0x38,0xa2,0x23,0x00,0x17, ++0x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b,0x08,0x00,0x12,0x67,0x00,0x00,0x00,0x00, ++0x10,0x62,0x00,0x09,0x24,0x02,0x00,0x02,0x10,0x62,0x00,0x05,0x24,0x02,0x00,0x03, ++0x14,0x62,0xff,0xbd,0x00,0x00,0x00,0x00,0x08,0x00,0x12,0x32,0xa2,0x40,0x00,0x07, ++0x08,0x00,0x12,0x32,0xa2,0x40,0x00,0x06,0x08,0x00,0x12,0x32,0xa2,0x40,0x00,0x05, ++0x3c,0x02,0x80,0x00,0x00,0x82,0x30,0x24,0x10,0xc0,0x00,0x08,0x00,0xa2,0x18,0x24, ++0x10,0x60,0x00,0x04,0x00,0x00,0x10,0x21,0x10,0xc0,0x00,0x02,0x24,0x02,0x00,0x01, ++0x00,0xa4,0x10,0x2b,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x10,0x60,0xff,0xfd, ++0x00,0xa4,0x10,0x2b,0x08,0x00,0x12,0x82,0x00,0x00,0x00,0x00,0x30,0x82,0xff,0xff, ++0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,0x27,0x84,0x90,0x10,0x00,0x03,0x18,0x80, ++0x00,0x64,0x18,0x21,0x80,0x66,0x00,0x06,0x00,0x02,0x12,0x00,0x3c,0x03,0xb0,0x00, ++0x00,0x46,0x10,0x21,0x00,0x45,0x10,0x21,0x03,0xe0,0x00,0x08,0x00,0x43,0x10,0x21, ++0x27,0xbd,0xff,0xe0,0x30,0x82,0x00,0x7c,0x30,0x84,0xff,0x00,0xaf,0xbf,0x00,0x1c, ++0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x14,0x40,0x00,0x41, ++0x00,0x04,0x22,0x03,0x24,0x02,0x00,0x04,0x3c,0x10,0xb0,0x03,0x8e,0x10,0x00,0x00, ++0x10,0x82,0x00,0x32,0x24,0x02,0x00,0x08,0x10,0x82,0x00,0x03,0x32,0x02,0x00,0x20, ++0x08,0x00,0x12,0xa8,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x17,0x3c,0x02,0xb0,0x06, ++0x34,0x42,0x80,0x24,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x67,0x00,0xff, ++0x10,0xe0,0x00,0x23,0x00,0x00,0x88,0x21,0x8f,0x85,0x8f,0xe0,0x00,0x40,0x30,0x21, ++0x94,0xa2,0x00,0x08,0x8c,0xc3,0x00,0x00,0x26,0x31,0x00,0x01,0x24,0x42,0x00,0x02, ++0x30,0x42,0x01,0xff,0x34,0x63,0x01,0x00,0x02,0x27,0x20,0x2a,0xa4,0xa2,0x00,0x08, ++0x14,0x80,0xff,0xf7,0xac,0xc3,0x00,0x00,0x84,0xa3,0x00,0x08,0x3c,0x02,0xb0,0x03, ++0x34,0x42,0x00,0x30,0xac,0x43,0x00,0x00,0x27,0x92,0xb4,0x00,0x24,0x11,0x00,0x12, ++0x8e,0x44,0x00,0x00,0x26,0x31,0xff,0xff,0x90,0x82,0x00,0x10,0x00,0x00,0x00,0x00, ++0x10,0x40,0x00,0x03,0x26,0x52,0x00,0x04,0x0c,0x00,0x18,0xd0,0x00,0x00,0x00,0x00, ++0x06,0x21,0xff,0xf7,0x24,0x02,0xff,0xdf,0x02,0x02,0x80,0x24,0x3c,0x01,0xb0,0x03, ++0x0c,0x00,0x13,0x1c,0xac,0x30,0x00,0x00,0x08,0x00,0x12,0xa8,0x00,0x00,0x00,0x00, ++0x8f,0x85,0x8f,0xe0,0x08,0x00,0x12,0xbe,0x00,0x00,0x00,0x00,0x24,0x02,0xff,0x95, ++0x3c,0x03,0xb0,0x03,0x02,0x02,0x80,0x24,0x34,0x63,0x00,0x30,0x3c,0x01,0xb0,0x03, ++0xac,0x30,0x00,0x00,0x0c,0x00,0x12,0xe5,0xac,0x60,0x00,0x00,0x08,0x00,0x12,0xa8, ++0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x50,0x08,0x00,0x12,0xa8, ++0xac,0x46,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4b,0x94,0x3c,0x0b,0xb0,0x03, ++0xad,0x6a,0x00,0x20,0x3c,0x08,0x80,0x01,0x25,0x08,0x00,0x00,0x3c,0x09,0x80,0x01, ++0x25,0x29,0x03,0x50,0x11,0x09,0x00,0x10,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00, ++0x25,0x4a,0x4b,0xbc,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0x3c,0x08,0xb0,0x06, ++0x35,0x08,0x80,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8d,0x09,0x00,0x00, ++0x00,0x00,0x00,0x00,0x31,0x29,0x00,0x01,0x00,0x00,0x00,0x00,0x24,0x01,0x00,0x01, ++0x15,0x21,0xff,0xf2,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4b,0xf8, ++0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0x3c,0x02,0xb0,0x03,0x8c,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x34,0x63,0x00,0x40,0x00,0x00,0x00,0x00,0xac,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4c,0x24,0x3c,0x0b,0xb0,0x03, ++0xad,0x6a,0x00,0x20,0x3c,0x02,0x80,0x01,0x24,0x42,0x00,0x00,0x3c,0x03,0x80,0x01, ++0x24,0x63,0x03,0x50,0x3c,0x04,0xb0,0x00,0x8c,0x85,0x00,0x00,0x00,0x00,0x00,0x00, ++0xac,0x45,0x00,0x00,0x24,0x42,0x00,0x04,0x24,0x84,0x00,0x04,0x00,0x43,0x08,0x2a, ++0x14,0x20,0xff,0xf9,0x00,0x00,0x00,0x00,0x0c,0x00,0x13,0x1c,0x00,0x00,0x00,0x00, ++0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4c,0x70,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20, ++0x3c,0x02,0x80,0x01,0x24,0x42,0x03,0x50,0x3c,0x03,0x80,0x01,0x24,0x63,0x3f,0x24, ++0xac,0x40,0x00,0x00,0xac,0x40,0x00,0x04,0xac,0x40,0x00,0x08,0xac,0x40,0x00,0x0c, ++0x24,0x42,0x00,0x10,0x00,0x43,0x08,0x2a,0x14,0x20,0xff,0xf9,0x00,0x00,0x00,0x00, ++0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4c,0xb0,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20, ++0x3c,0x1c,0x80,0x01,0x27,0x9c,0x7f,0xf0,0x27,0x9d,0x8b,0xe0,0x00,0x00,0x00,0x00, ++0x27,0x9d,0x8f,0xc8,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4c,0xd4,0x3c,0x0b,0xb0,0x03, ++0xad,0x6a,0x00,0x20,0x40,0x80,0x68,0x00,0x40,0x08,0x60,0x00,0x00,0x00,0x00,0x00, ++0x35,0x08,0xff,0x01,0x40,0x88,0x60,0x00,0x00,0x00,0x00,0x00,0x0c,0x00,0x15,0x62, ++0x00,0x00,0x00,0x00,0x24,0x84,0xf8,0x00,0x30,0x87,0x00,0x03,0x00,0x04,0x30,0x40, ++0x00,0xc7,0x20,0x23,0x3c,0x02,0xb0,0x0a,0x27,0xbd,0xff,0xe0,0x24,0x03,0xff,0xff, ++0x00,0x82,0x20,0x21,0xaf,0xb1,0x00,0x14,0xac,0x83,0x10,0x00,0xaf,0xbf,0x00,0x18, ++0xaf,0xb0,0x00,0x10,0x00,0xa0,0x88,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x10,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0xc7,0x10,0x23,0x3c,0x03,0xb0,0x0a, ++0x00,0x43,0x10,0x21,0x8c,0x50,0x00,0x00,0x0c,0x00,0x13,0x99,0x02,0x20,0x20,0x21, ++0x02,0x11,0x80,0x24,0x00,0x50,0x80,0x06,0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x18, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x27,0xbd,0xff,0xd8, ++0xaf,0xb2,0x00,0x18,0x00,0xa0,0x90,0x21,0x24,0x05,0xff,0xff,0xaf,0xb3,0x00,0x1c, ++0xaf,0xbf,0x00,0x20,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x00,0xc0,0x98,0x21, ++0x12,0x45,0x00,0x23,0x24,0x84,0xf8,0x00,0x30,0x83,0x00,0x03,0x00,0x04,0x10,0x40, ++0x00,0x40,0x88,0x21,0x00,0x60,0x20,0x21,0x00,0x43,0x10,0x23,0x3c,0x03,0xb0,0x0a, ++0x00,0x43,0x10,0x21,0xac,0x45,0x10,0x00,0x00,0x40,0x18,0x21,0x24,0x05,0x00,0x01, ++0x8c,0x62,0x10,0x00,0x00,0x00,0x00,0x00,0x14,0x45,0xff,0xfd,0x3c,0x02,0xb0,0x0a, ++0x02,0x24,0x88,0x23,0x02,0x22,0x88,0x21,0x8e,0x30,0x00,0x00,0x0c,0x00,0x13,0x99, ++0x02,0x40,0x20,0x21,0x00,0x12,0x18,0x27,0x02,0x03,0x80,0x24,0x00,0x53,0x10,0x04, ++0x02,0x02,0x80,0x25,0xae,0x30,0x00,0x00,0x24,0x03,0x00,0x01,0x8e,0x22,0x10,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x20, ++0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28, ++0x30,0x82,0x00,0x03,0x00,0x04,0x18,0x40,0x00,0x62,0x18,0x23,0x3c,0x04,0xb0,0x0a, ++0x00,0x64,0x18,0x21,0xac,0x66,0x00,0x00,0x24,0x04,0x00,0x01,0x8c,0x62,0x10,0x00, ++0x00,0x00,0x00,0x00,0x14,0x44,0xff,0xfd,0x00,0x00,0x00,0x00,0x08,0x00,0x13,0x87, ++0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x21,0x00,0x64,0x10,0x06,0x30,0x42,0x00,0x01, ++0x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,0x2c,0x62,0x00,0x20, ++0x14,0x40,0xff,0xf9,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21, ++0x27,0xbd,0xff,0xe0,0x3c,0x03,0xb0,0x05,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14, ++0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x1c,0x00,0x80,0x90,0x21,0x00,0xa0,0x80,0x21, ++0x00,0xc0,0x88,0x21,0x34,0x63,0x02,0x2e,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0x01,0x14,0x40,0xff,0xfc,0x24,0x04,0x08,0x24,0x3c,0x05,0x00,0xc0, ++0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x03,0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0xc0, ++0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x03,0x3c,0x02,0xc0,0x00,0x00,0x10,0x1c,0x00, ++0x34,0x42,0x04,0x00,0x3c,0x04,0xb0,0x05,0x3c,0x05,0xb0,0x05,0x24,0x63,0x16,0x09, ++0x02,0x22,0x10,0x21,0x34,0x84,0x04,0x20,0x34,0xa5,0x04,0x24,0x3c,0x06,0xb0,0x05, ++0xac,0x83,0x00,0x00,0x24,0x07,0x00,0x01,0xac,0xa2,0x00,0x00,0x34,0xc6,0x02,0x28, ++0x24,0x02,0x00,0x20,0xae,0x47,0x00,0x3c,0x24,0x04,0x08,0x24,0xa0,0xc2,0x00,0x00, ++0x3c,0x05,0x00,0xc0,0xa2,0x47,0x00,0x11,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x01, ++0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0xc0,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x01, ++0x8f,0xbf,0x00,0x1c,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x20,0x24,0x02,0x00,0x06,0xac,0x82,0x00,0x0c,0xa0,0x80,0x00,0x50, ++0xac,0x80,0x00,0x00,0xac,0x80,0x00,0x04,0xac,0x80,0x00,0x08,0xac,0x80,0x00,0x14, ++0xac,0x80,0x00,0x18,0xac,0x80,0x00,0x1c,0xa4,0x80,0x00,0x20,0xac,0x80,0x00,0x24, ++0xac,0x80,0x00,0x28,0xac,0x80,0x00,0x2c,0xa0,0x80,0x00,0x30,0xa0,0x80,0x00,0x31, ++0xac,0x80,0x00,0x34,0xac,0x80,0x00,0x38,0xa0,0x80,0x00,0x3c,0xac,0x82,0x00,0x10, ++0xa0,0x80,0x00,0x44,0xac,0x80,0x00,0x48,0x03,0xe0,0x00,0x08,0xac,0x80,0x00,0x4c, ++0x3c,0x04,0xb0,0x06,0x34,0x84,0x80,0x00,0x8c,0x83,0x00,0x00,0x3c,0x02,0x12,0x00, ++0x3c,0x05,0xb0,0x03,0x00,0x62,0x18,0x25,0x34,0xa5,0x00,0x8b,0x24,0x02,0xff,0x80, ++0xac,0x83,0x00,0x00,0x03,0xe0,0x00,0x08,0xa0,0xa2,0x00,0x00,0x3c,0x04,0xb0,0x03, ++0x34,0x84,0x00,0x0b,0x24,0x02,0x00,0x22,0x3c,0x05,0xb0,0x01,0x3c,0x06,0x45,0x67, ++0x3c,0x0a,0xb0,0x09,0xa0,0x82,0x00,0x00,0x34,0xa5,0x00,0x04,0x34,0xc6,0x89,0xaa, ++0x35,0x4a,0x00,0x04,0x24,0x02,0x01,0x23,0x3c,0x0b,0xb0,0x09,0x3c,0x07,0x01,0x23, ++0x3c,0x0c,0xb0,0x09,0x3c,0x01,0xb0,0x01,0xac,0x20,0x00,0x00,0x27,0xbd,0xff,0xe0, ++0xac,0xa0,0x00,0x00,0x35,0x6b,0x00,0x08,0x3c,0x01,0xb0,0x09,0xac,0x26,0x00,0x00, ++0x34,0xe7,0x45,0x66,0xa5,0x42,0x00,0x00,0x35,0x8c,0x00,0x0c,0x24,0x02,0xcd,0xef, ++0x3c,0x0d,0xb0,0x09,0x3c,0x08,0xcd,0xef,0x3c,0x0e,0xb0,0x09,0xad,0x67,0x00,0x00, ++0xaf,0xb7,0x00,0x1c,0xa5,0x82,0x00,0x00,0xaf,0xb6,0x00,0x18,0xaf,0xb5,0x00,0x14, ++0xaf,0xb4,0x00,0x10,0xaf,0xb3,0x00,0x0c,0xaf,0xb2,0x00,0x08,0xaf,0xb1,0x00,0x04, ++0xaf,0xb0,0x00,0x00,0x35,0xad,0x00,0x10,0x35,0x08,0x01,0x22,0x35,0xce,0x00,0x14, ++0x24,0x02,0x89,0xab,0x3c,0x0f,0xb0,0x09,0x3c,0x09,0x89,0xab,0x3c,0x10,0xb0,0x09, ++0x3c,0x11,0xb0,0x09,0x3c,0x12,0xb0,0x09,0x3c,0x13,0xb0,0x09,0x3c,0x14,0xb0,0x09, ++0x3c,0x15,0xb0,0x09,0x3c,0x16,0xb0,0x09,0x3c,0x17,0xb0,0x09,0xad,0xa8,0x00,0x00, ++0x24,0x03,0xff,0xff,0xa5,0xc2,0x00,0x00,0x35,0xef,0x00,0x18,0x35,0x29,0xcd,0xee, ++0x36,0x10,0x00,0x1c,0x36,0x31,0x00,0x20,0x36,0x52,0x00,0x24,0x36,0x73,0x00,0x28, ++0x36,0x94,0x00,0x2c,0x36,0xb5,0x00,0x30,0x36,0xd6,0x00,0x34,0x36,0xf7,0x00,0x38, ++0x24,0x02,0x45,0x67,0xad,0xe9,0x00,0x00,0xa6,0x02,0x00,0x00,0xae,0x23,0x00,0x00, ++0x8f,0xb0,0x00,0x00,0xa6,0x43,0x00,0x00,0x8f,0xb1,0x00,0x04,0xae,0x63,0x00,0x00, ++0x8f,0xb2,0x00,0x08,0xa6,0x83,0x00,0x00,0x8f,0xb3,0x00,0x0c,0xae,0xa3,0x00,0x00, ++0x8f,0xb4,0x00,0x10,0xa6,0xc3,0x00,0x00,0x8f,0xb5,0x00,0x14,0xae,0xe3,0x00,0x00, ++0x7b,0xb6,0x00,0xfc,0x3c,0x18,0xb0,0x09,0x37,0x18,0x00,0x3c,0xa7,0x03,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00, ++0x34,0x63,0x00,0x20,0x24,0x42,0x51,0x48,0xac,0x62,0x00,0x00,0x8c,0x83,0x00,0x34, ++0x34,0x02,0xff,0xff,0x00,0x43,0x10,0x2a,0x14,0x40,0x01,0x04,0x00,0x80,0x28,0x21, ++0x8c,0x86,0x00,0x08,0x24,0x02,0x00,0x03,0x10,0xc2,0x00,0xf7,0x00,0x00,0x00,0x00, ++0x8c,0xa2,0x00,0x2c,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x4f,0x24,0x02,0x00,0x06, ++0x3c,0x03,0xb0,0x05,0x34,0x63,0x04,0x50,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0xff,0x14,0x40,0x00,0xdd,0xac,0xa2,0x00,0x2c,0x24,0x02,0x00,0x01, ++0x10,0xc2,0x00,0xdc,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xc2,0x00,0xca, ++0x00,0x00,0x00,0x00,0x8c,0xa7,0x00,0x04,0x24,0x02,0x00,0x02,0x10,0xe2,0x00,0xc0, ++0x00,0x00,0x00,0x00,0x8c,0xa2,0x00,0x14,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x09, ++0x24,0x02,0x00,0x01,0x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x60,0x90,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0x10,0x40,0x00,0x05,0xac,0xa2,0x00,0x14, ++0x24,0x02,0x00,0x01,0xac,0xa2,0x00,0x00,0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x14, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xd0,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00, ++0x04,0x61,0x00,0x19,0x3c,0x02,0xb0,0x03,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2e, ++0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x12, ++0x3c,0x02,0xb0,0x03,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x42,0x90,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x0c,0x3c,0x02,0xb0,0x03,0x80,0xa2,0x00,0x50, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x08,0x3c,0x02,0xb0,0x03,0x14,0xc0,0x00,0x07, ++0x34,0x42,0x00,0x3f,0x24,0x02,0x00,0x0e,0x24,0x03,0x00,0x01,0xac,0xa2,0x00,0x00, ++0x03,0xe0,0x00,0x08,0xa0,0xa3,0x00,0x50,0x34,0x42,0x00,0x3f,0x90,0x44,0x00,0x00, ++0x24,0x03,0x00,0x01,0x10,0x64,0x00,0x7f,0x3c,0x03,0xb0,0x05,0x80,0xa2,0x00,0x31, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0a,0x3c,0x02,0xb0,0x06,0x34,0x42,0x80,0x18, ++0x8c,0x43,0x00,0x00,0x3c,0x04,0xf0,0x00,0x3c,0x02,0x80,0x00,0x00,0x64,0x18,0x24, ++0x10,0x62,0x00,0x03,0x24,0x02,0x00,0x09,0x03,0xe0,0x00,0x08,0xac,0xa2,0x00,0x00, ++0x8c,0xa2,0x00,0x40,0x00,0x00,0x00,0x00,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00, ++0x10,0x60,0x00,0x09,0x3c,0x03,0xb0,0x03,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c, ++0x8c,0x43,0x00,0x00,0x3c,0x04,0x00,0x02,0x00,0x64,0x18,0x24,0x14,0x60,0xff,0xf2, ++0x24,0x02,0x00,0x10,0x3c,0x03,0xb0,0x03,0x34,0x63,0x02,0x01,0x90,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x80,0x10,0x40,0x00,0x0e,0x00,0x00,0x00,0x00, ++0x8c,0xa3,0x00,0x0c,0x00,0x00,0x00,0x00,0xac,0xa3,0x00,0x10,0x3c,0x02,0xb0,0x03, ++0x90,0x42,0x02,0x01,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x0f,0xac,0xa2,0x00,0x0c, ++0x90,0xa3,0x00,0x0f,0x24,0x02,0x00,0x0d,0x3c,0x01,0xb0,0x03,0x08,0x00,0x14,0xb2, ++0xa0,0x23,0x02,0x01,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x80,0x90,0x44,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x04,0x1e,0x00,0x00,0x03,0x1e,0x03,0x10,0x60,0x00,0x15, ++0xa0,0xa4,0x00,0x44,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x0b,0x24,0x02,0x00,0x02, ++0x10,0x62,0x00,0x03,0x24,0x03,0x00,0x0d,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x8c,0xa2,0x00,0x0c,0xac,0xa3,0x00,0x00,0x24,0x03,0x00,0x04,0xac,0xa2,0x00,0x10, ++0x03,0xe0,0x00,0x08,0xac,0xa3,0x00,0x0c,0x24,0x02,0x00,0x0d,0xac,0xa2,0x00,0x00, ++0x24,0x03,0x00,0x04,0x24,0x02,0x00,0x06,0xac,0xa3,0x00,0x10,0x03,0xe0,0x00,0x08, ++0xac,0xa2,0x00,0x0c,0x8c,0xa3,0x00,0x38,0x24,0x04,0x00,0x01,0x10,0x64,0x00,0x2d, ++0x24,0x02,0x00,0x02,0x10,0x60,0x00,0x19,0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x10, ++0x24,0x02,0x00,0x04,0x10,0x62,0x00,0x04,0x00,0x00,0x00,0x00,0xac,0xa0,0x00,0x38, ++0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x00,0x10,0xe4,0x00,0x07,0x24,0x02,0x00,0x03, ++0x80,0xa2,0x00,0x30,0x00,0x00,0x00,0x00,0x00,0x02,0x18,0x0b,0xac,0xa3,0x00,0x00, ++0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x38,0x08,0x00,0x15,0x04,0xac,0xa2,0x00,0x00, ++0x10,0xe4,0x00,0x02,0x24,0x02,0x00,0x03,0x24,0x02,0x00,0x0c,0xac,0xa2,0x00,0x00, ++0x24,0x02,0x00,0x04,0x03,0xe0,0x00,0x08,0xac,0xa2,0x00,0x38,0x10,0xe4,0x00,0x0e, ++0x3c,0x03,0xb0,0x06,0x34,0x63,0x80,0x24,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0xff,0x10,0x40,0x00,0x06,0xac,0xa2,0x00,0x18,0x24,0x02,0x00,0x02, ++0xac,0xa2,0x00,0x00,0xac,0xa0,0x00,0x18,0x08,0x00,0x15,0x0d,0x24,0x02,0x00,0x01, ++0x08,0x00,0x15,0x1a,0xac,0xa0,0x00,0x00,0x24,0x02,0x00,0x03,0x08,0x00,0x15,0x1a, ++0xac,0xa2,0x00,0x00,0x24,0x03,0x00,0x0b,0xac,0xa2,0x00,0x38,0x03,0xe0,0x00,0x08, ++0xac,0xa3,0x00,0x00,0x34,0x63,0x02,0x2e,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0x01,0x14,0x40,0xff,0x7d,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x42, ++0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x60,0xff,0x78,0x00,0x00,0x00,0x00, ++0x10,0xc0,0xff,0x81,0x24,0x02,0x00,0x0e,0x08,0x00,0x14,0xa7,0x00,0x00,0x00,0x00, ++0x80,0xa2,0x00,0x30,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x3e,0x24,0x02,0x00,0x04, ++0x08,0x00,0x14,0xb2,0x00,0x00,0x00,0x00,0x84,0xa2,0x00,0x20,0x00,0x00,0x00,0x00, ++0x10,0x40,0xff,0x75,0x24,0x02,0x00,0x06,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e, ++0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff, ++0x00,0x60,0x10,0x21,0x14,0x40,0xff,0x2b,0xa4,0xa3,0x00,0x20,0x08,0x00,0x14,0xb2, ++0x24,0x02,0x00,0x06,0x8c,0xa2,0x00,0x1c,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x66, ++0x24,0x02,0x00,0x05,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2c,0x8c,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0x10,0x40,0xff,0x1b,0xac,0xa2,0x00,0x1c, ++0x08,0x00,0x14,0xb2,0x24,0x02,0x00,0x05,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x02,0x17,0x42,0x30,0x42,0x00,0x01,0x14,0x40,0xff,0x56, ++0x24,0x02,0x00,0x06,0x08,0x00,0x14,0x60,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x0a, ++0x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x00,0x27,0xbd,0xff,0xd8,0xaf,0xb0,0x00,0x10, ++0x27,0x90,0x86,0x58,0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18, ++0x0c,0x00,0x29,0xd5,0xaf,0xb1,0x00,0x14,0xaf,0x90,0x8f,0xe0,0x48,0x02,0x00,0x00, ++0x0c,0x00,0x13,0xf0,0x00,0x00,0x00,0x00,0x0c,0x00,0x18,0x1f,0x02,0x00,0x20,0x21, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x3a,0x94,0x43,0x00,0x00,0x00,0x00,0x00,0x00, ++0xa3,0x83,0x8f,0xe4,0x0c,0x00,0x00,0x34,0x00,0x00,0x00,0x00,0x0c,0x00,0x13,0xfb, ++0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x98,0x0c,0x00,0x27,0x59,0x00,0x00,0x00,0x00, ++0x93,0x84,0x80,0x10,0x0c,0x00,0x21,0x3f,0x00,0x00,0x00,0x00,0x27,0x84,0x89,0x18, ++0x0c,0x00,0x06,0xe5,0x00,0x00,0x00,0x00,0x0c,0x00,0x01,0x39,0x00,0x00,0x00,0x00, ++0x27,0x84,0x84,0x40,0x0c,0x00,0x13,0xd9,0x00,0x00,0x00,0x00,0x27,0x82,0x89,0x4c, ++0xaf,0x82,0x84,0x80,0x0c,0x00,0x00,0x5f,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03, ++0x34,0x63,0x01,0x08,0x3c,0x04,0xb0,0x09,0x3c,0x05,0xb0,0x09,0x8c,0x66,0x00,0x00, ++0x34,0x84,0x01,0x68,0x34,0xa5,0x01,0x40,0x24,0x02,0xc8,0x80,0x24,0x03,0x00,0x0a, ++0xa4,0x82,0x00,0x00,0xa4,0xa3,0x00,0x00,0x3c,0x04,0xb0,0x03,0x8c,0x82,0x00,0x00, ++0x8f,0x85,0x84,0x40,0xaf,0x86,0x84,0x38,0x34,0x42,0x00,0x20,0xac,0x82,0x00,0x00, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x58,0x8c,0x43,0x00,0x00,0x2c,0xa4,0x00,0x11, ++0x34,0x63,0x01,0x00,0xac,0x43,0x00,0x00,0x10,0x80,0xff,0xfa,0x3c,0x02,0xb0,0x03, ++0x3c,0x03,0x80,0x01,0x00,0x05,0x10,0x80,0x24,0x63,0x02,0x00,0x00,0x43,0x10,0x21, ++0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00, ++0x27,0x84,0x84,0x98,0x0c,0x00,0x26,0x8e,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x40, ++0x0c,0x00,0x14,0x52,0x00,0x00,0x00,0x00,0x93,0x83,0x81,0xf1,0x24,0x02,0x00,0x01, ++0x10,0x62,0x00,0x08,0x00,0x00,0x00,0x00,0x8f,0x85,0x84,0x40,0x8f,0x82,0x84,0x74, ++0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xaf,0x82,0x84,0x74,0x08,0x00,0x15,0x9d, ++0x3c,0x02,0xb0,0x03,0x27,0x84,0x84,0x98,0x0c,0x00,0x27,0x0d,0x00,0x00,0x00,0x00, ++0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x98,0x0c,0x00,0x28,0xdd, ++0x00,0x00,0x00,0x00,0xa3,0x82,0x84,0x71,0x8f,0x82,0x84,0x74,0xaf,0x80,0x84,0x40, ++0x24,0x42,0x00,0x01,0xaf,0x82,0x84,0x74,0x08,0x00,0x15,0x9c,0x00,0x00,0x28,0x21, ++0x27,0x84,0x86,0x58,0x0c,0x00,0x19,0x5b,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff, ++0x14,0x40,0x00,0x05,0x3c,0x03,0xb0,0x05,0xaf,0x80,0x84,0x40,0xaf,0x80,0x84,0x44, ++0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00,0x34,0x63,0x04,0x50,0x90,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x6c,0x14,0x40,0x00,0x20, ++0x24,0x02,0x00,0x01,0x8f,0x84,0x84,0x48,0x00,0x00,0x00,0x00,0x10,0x82,0x00,0x20, ++0x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x60,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x54,0x14,0x40,0x00,0x15,0x24,0x02,0x00,0x01, ++0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x07,0x00,0x00,0x00,0x00,0x24,0x05,0x00,0x03, ++0x24,0x02,0x00,0x01,0xaf,0x82,0x84,0x44,0xaf,0x85,0x84,0x40,0x08,0x00,0x15,0xb6, ++0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21, ++0xa7,0x83,0x84,0x60,0x14,0x40,0xff,0xf1,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0xaf,0x82,0x84,0x44,0xaf,0x80,0x84,0x40,0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00, ++0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2c,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x5c,0x14,0x40,0xff,0xf5,0x24,0x02,0x00,0x01, ++0x08,0x00,0x15,0xe1,0x3c,0x03,0xb0,0x09,0x27,0x84,0x86,0x58,0x0c,0x00,0x1a,0xd1, ++0x00,0x00,0x00,0x00,0x83,0x82,0x84,0x70,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xec, ++0x24,0x02,0x00,0x02,0x3c,0x03,0xb0,0x05,0x34,0x63,0x04,0x50,0x90,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x6c,0x14,0x40,0xff,0xe4, ++0x24,0x02,0x00,0x02,0x8f,0x84,0x84,0x48,0x24,0x02,0x00,0x01,0x10,0x82,0x00,0x12, ++0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x04,0x00,0x00,0x00,0x00,0x24,0x05,0x00,0x04, ++0x08,0x00,0x15,0xed,0x24,0x02,0x00,0x02,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e, ++0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff, ++0x00,0x60,0x10,0x21,0xa7,0x83,0x84,0x60,0x14,0x40,0xff,0xf4,0x00,0x00,0x00,0x00, ++0x08,0x00,0x15,0xfc,0x24,0x02,0x00,0x02,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2c, ++0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x5c, ++0x14,0x40,0xff,0xf7,0x00,0x00,0x00,0x00,0x08,0x00,0x16,0x1d,0x24,0x02,0x00,0x02, ++0x27,0x84,0x89,0x18,0x0c,0x00,0x0b,0x55,0x00,0x00,0x00,0x00,0x8f,0x83,0x84,0x44, ++0xaf,0x82,0x84,0x5c,0x38,0x64,0x00,0x02,0x00,0x04,0x18,0x0a,0xaf,0x83,0x84,0x44, ++0x14,0x40,0xff,0xad,0x24,0x05,0x00,0x05,0x8f,0x82,0x89,0x58,0xaf,0x80,0x84,0x40, ++0x10,0x40,0x00,0x02,0x24,0x04,0x00,0x01,0xaf,0x84,0x84,0x48,0x93,0x82,0x89,0x66, ++0x00,0x00,0x00,0x00,0x10,0x40,0xff,0x6c,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05, ++0x34,0x42,0x00,0x08,0x8c,0x43,0x00,0x00,0x3c,0x04,0x20,0x00,0x00,0x64,0x18,0x24, ++0x10,0x60,0xff,0x65,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xa0, ++0x8c,0x43,0x00,0x00,0x3c,0x04,0x80,0x00,0xaf,0x80,0x89,0x40,0x24,0x63,0x00,0x01, ++0xac,0x43,0x00,0x00,0x3c,0x01,0xb0,0x05,0xac,0x24,0x00,0x08,0xaf,0x80,0x89,0x3c, ++0xaf,0x80,0x89,0x44,0xaf,0x80,0x89,0x48,0xaf,0x80,0x89,0x54,0xaf,0x80,0x89,0x4c, ++0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00,0x83,0x82,0x84,0x90,0x00,0x00,0x00,0x00, ++0x10,0x40,0x00,0x02,0x24,0x02,0x00,0x20,0xaf,0x82,0x84,0x5c,0x8f,0x85,0x84,0x5c, ++0x27,0x84,0x89,0x18,0x0c,0x00,0x0d,0x30,0x00,0x00,0x00,0x00,0x00,0x02,0x1e,0x00, ++0xa3,0x82,0x84,0x70,0xaf,0x80,0x84,0x5c,0x10,0x60,0xff,0x8e,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21,0xa7,0x83,0x84,0x60, ++0x10,0x40,0x00,0x04,0x24,0x04,0x00,0x02,0xaf,0x84,0x84,0x48,0x08,0x00,0x15,0xfd, ++0x00,0x00,0x00,0x00,0x08,0x00,0x15,0xee,0x24,0x05,0x00,0x06,0x27,0x84,0x84,0x40, ++0x27,0x85,0x89,0x18,0x0c,0x00,0x0d,0xfd,0x00,0x00,0x00,0x00,0x8f,0x82,0x84,0x64, ++0xaf,0x80,0x84,0x6c,0x14,0x40,0x00,0x19,0x00,0x40,0x18,0x21,0x8f,0x82,0x84,0x68, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x15,0x24,0x02,0x00,0x02,0x8f,0x83,0x84,0x48, ++0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x0b,0x3c,0x02,0x40,0x00,0x8f,0x83,0x84,0x44, ++0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x02,0x24,0x05,0x00,0x03,0x24,0x05,0x00,0x06, ++0xaf,0x85,0x84,0x40,0x24,0x04,0x00,0x03,0xaf,0x84,0x84,0x48,0x08,0x00,0x15,0xb6, ++0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x14,0x3c,0x01,0xb0,0x05,0xac,0x22,0x00,0x00, ++0xaf,0x80,0x84,0x40,0x08,0x00,0x16,0x96,0x24,0x04,0x00,0x03,0x10,0x60,0x00,0x10, ++0x00,0x00,0x00,0x00,0x27,0x85,0x89,0x18,0x27,0x84,0x84,0x40,0x0c,0x00,0x0e,0x21, ++0x00,0x00,0x00,0x00,0x8f,0x83,0x84,0x44,0x24,0x02,0x00,0x01,0xa3,0x80,0x84,0x70, ++0xaf,0x80,0x84,0x48,0x10,0x62,0x00,0x02,0x24,0x05,0x00,0x03,0x24,0x05,0x00,0x04, ++0xaf,0x85,0x84,0x40,0xaf,0x80,0x84,0x64,0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00, ++0x83,0x82,0x84,0x90,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00, ++0x27,0x84,0x89,0x18,0x0c,0x00,0x10,0x69,0x00,0x00,0x00,0x00,0x8f,0x82,0x84,0x44, ++0xa3,0x80,0x84,0x70,0xaf,0x80,0x84,0x40,0xaf,0x80,0x84,0x48,0x14,0x40,0x00,0x03, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0xaf,0x82,0x84,0x44,0xaf,0x80,0x84,0x68, ++0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x40,0x27,0x85,0x89,0x18, ++0x0c,0x00,0x0e,0x21,0x00,0x00,0x00,0x00,0x8f,0x82,0x84,0x44,0xa3,0x80,0x84,0x70, ++0xaf,0x80,0x84,0x40,0xaf,0x80,0x84,0x48,0x14,0x40,0xfe,0xeb,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x02,0xaf,0x82,0x84,0x44,0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00, ++0x27,0x84,0x89,0x18,0x0c,0x00,0x10,0x69,0x00,0x00,0x00,0x00,0x08,0x00,0x16,0xc6, ++0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x98,0x0c,0x00,0x29,0x73,0x00,0x00,0x00,0x00, ++0x08,0x00,0x15,0xc5,0x00,0x00,0x00,0x00,0x0c,0x00,0x24,0x05,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x26,0xff,0x00,0x00,0x00,0x00,0x0c,0x00,0x18,0x11,0x00,0x00,0x00,0x00, ++0x93,0x83,0xbc,0x18,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x2b,0x3c,0x02,0xb0,0x03, ++0x34,0x42,0x01,0x08,0x8c,0x44,0x00,0x00,0x8f,0x83,0xbc,0x10,0x8f,0x82,0xbc,0x14, ++0x00,0x83,0x18,0x23,0x00,0x43,0x10,0x2b,0x10,0x40,0x00,0x23,0x3c,0x02,0xb0,0x03, ++0x24,0x04,0x05,0xa0,0x34,0x42,0x01,0x18,0x8c,0x42,0x00,0x00,0x0c,0x00,0x06,0xd1, ++0x00,0x00,0x00,0x00,0x24,0x04,0x05,0xa4,0x0c,0x00,0x06,0xd1,0x00,0x02,0x84,0x02, ++0x30,0x51,0xff,0xff,0x24,0x04,0x05,0xa8,0x00,0x02,0x94,0x02,0x0c,0x00,0x06,0xd1, ++0x3a,0x10,0xff,0xff,0x3a,0x31,0xff,0xff,0x30,0x42,0xff,0xff,0x2e,0x10,0x00,0x01, ++0x2e,0x31,0x00,0x01,0x3a,0x52,0xff,0xff,0x02,0x11,0x80,0x25,0x2e,0x52,0x00,0x01, ++0x38,0x42,0xff,0xff,0x02,0x12,0x80,0x25,0x2c,0x42,0x00,0x01,0x02,0x02,0x80,0x25, ++0x16,0x00,0x00,0x02,0x24,0x04,0x00,0x02,0x00,0x00,0x20,0x21,0x0c,0x00,0x05,0x6e, ++0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,0x8c,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0xaf,0x83,0xbc,0x10,0x0c,0x00,0x01,0xe9,0x00,0x00,0x00,0x00, ++0xaf,0x80,0x84,0x40,0xaf,0x80,0x84,0x74,0x08,0x00,0x15,0x9c,0x00,0x00,0x28,0x21, ++0x27,0x90,0xb4,0x00,0x24,0x11,0x00,0x12,0x8e,0x04,0x00,0x00,0x00,0x00,0x00,0x00, ++0x90,0x82,0x00,0x10,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x03,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x18,0xd0,0x00,0x00,0x00,0x00,0x26,0x31,0xff,0xff,0x06,0x21,0xff,0xf6, ++0x26,0x10,0x00,0x04,0xaf,0x80,0x84,0x40,0x08,0x00,0x15,0xb7,0x00,0x00,0x28,0x21, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,0x8c,0x44,0x00,0x00,0x8f,0x82,0x84,0x38, ++0x00,0x04,0x19,0xc2,0x00,0x02,0x11,0xc2,0x10,0x62,0xff,0xf6,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x02,0x90,0x43,0x00,0x00,0x3c,0x12,0xb0,0x05, ++0xaf,0x84,0x84,0x38,0x30,0x63,0x00,0xff,0x00,0x03,0x11,0x40,0x00,0x43,0x10,0x23, ++0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0x02,0x99,0x00,0x00,0x00,0x88,0x21, ++0x36,0x52,0x02,0x2c,0x27,0x90,0xb4,0x00,0x8e,0x04,0x00,0x00,0x00,0x00,0x00,0x00, ++0x90,0x83,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x62,0x00,0x03,0x10,0x40,0x00,0x06, ++0x30,0x62,0x00,0x1c,0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0x8f,0x85,0x84,0x38, ++0x0c,0x00,0x1e,0x94,0x02,0x60,0x30,0x21,0x8e,0x42,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0xff,0x14,0x40,0xff,0xd7,0x00,0x00,0x00,0x00,0x26,0x31,0x00,0x01, ++0x2a,0x22,0x00,0x13,0x14,0x40,0xff,0xec,0x26,0x10,0x00,0x04,0x08,0x00,0x17,0x21, ++0x00,0x00,0x00,0x00,0x8f,0x84,0x84,0x4c,0x27,0x85,0x89,0x18,0x0c,0x00,0x17,0xa4, ++0x00,0x00,0x00,0x00,0x8f,0x83,0x84,0x4c,0x24,0x02,0x00,0x04,0x14,0x62,0xfe,0xa5, ++0x00,0x00,0x00,0x00,0x08,0x00,0x15,0xee,0x24,0x05,0x00,0x05,0x3c,0x02,0xb0,0x03, ++0x34,0x42,0x00,0x3f,0x90,0x44,0x00,0x00,0x24,0x03,0x00,0x01,0x10,0x64,0x00,0x08, ++0x00,0x00,0x00,0x00,0x27,0x84,0x89,0x18,0x0c,0x00,0x24,0x2c,0x00,0x00,0x00,0x00, ++0x24,0x05,0x00,0x05,0xaf,0x85,0x84,0x40,0x08,0x00,0x15,0xb7,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x14,0x8c,0x44,0x00,0x00,0x0c,0x00,0x24,0x49, ++0x00,0x00,0x00,0x00,0x08,0x00,0x17,0x65,0x24,0x05,0x00,0x05,0x8f,0x82,0x89,0x4c, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0d,0x00,0x00,0x00,0x00,0x8f,0x84,0xb4,0x40, ++0xaf,0x80,0x89,0x4c,0x94,0x85,0x00,0x14,0x0c,0x00,0x1b,0x66,0x00,0x00,0x00,0x00, ++0x93,0x82,0x8b,0x71,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x02,0x10,0x40,0x00,0x03, ++0x00,0x00,0x00,0x00,0x0c,0x00,0x01,0x57,0x00,0x00,0x20,0x21,0x8f,0x84,0xb4,0x40, ++0x0c,0x00,0x18,0xd0,0x00,0x00,0x00,0x00,0x08,0x00,0x17,0x21,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xff,0x90,0x27,0xbd,0xff,0xe8,0x00,0x80,0x18,0x21,0x34,0x42,0x00,0x01, ++0x27,0x84,0x89,0x18,0x10,0x62,0x00,0x05,0xaf,0xbf,0x00,0x10,0x8f,0xbf,0x00,0x10, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x06,0xe5, ++0x00,0x00,0x00,0x00,0x27,0x84,0x86,0x58,0x0c,0x00,0x18,0x1f,0x00,0x00,0x00,0x00, ++0x27,0x84,0x84,0x40,0x0c,0x00,0x13,0xd9,0x00,0x00,0x00,0x00,0x08,0x00,0x17,0x8b, ++0x00,0x00,0x00,0x00,0x8f,0x82,0x89,0x58,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x05, ++0x00,0x00,0x18,0x21,0x8f,0x82,0x84,0x48,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x02, ++0x00,0x00,0x00,0x00,0x24,0x03,0x00,0x01,0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21, ++0x27,0xbd,0xff,0xe0,0x3c,0x06,0xb0,0x03,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10, ++0x34,0xc6,0x00,0x5f,0xaf,0xbf,0x00,0x18,0x90,0xc3,0x00,0x00,0x3c,0x07,0xb0,0x03, ++0x34,0xe7,0x00,0x5d,0x34,0x63,0x00,0x01,0x3c,0x09,0xb0,0x03,0x24,0x02,0x00,0x01, ++0xa0,0xc3,0x00,0x00,0x00,0x80,0x80,0x21,0xa0,0xe2,0x00,0x00,0x00,0xa0,0x88,0x21, ++0x35,0x29,0x00,0x5e,0x00,0xe0,0x40,0x21,0x24,0x04,0x00,0x01,0x91,0x22,0x00,0x00, ++0x91,0x03,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x83,0x00,0x03,0x30,0x42,0x00,0x01, ++0x14,0x40,0xff,0xfa,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x04,0x12,0x02,0x00,0x2c, ++0x24,0x05,0x0f,0x00,0x24,0x02,0x00,0x06,0x12,0x02,0x00,0x08,0x24,0x05,0x00,0x0f, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x02,0x00,0xa0,0x50,0x00,0x00,0x8f,0xbf,0x00,0x18, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x24,0x04,0x0c,0x04, ++0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x0f,0x24,0x04,0x0d,0x04,0x24,0x05,0x00,0x0f, ++0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x0f,0x24,0x04,0x08,0x80,0x24,0x05,0x1e,0x00, ++0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x0f,0x24,0x04,0x08,0x8c,0x24,0x05,0x0f,0x00, ++0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x0f,0x24,0x04,0x08,0x24,0x3c,0x05,0x00,0x30, ++0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x02,0x24,0x04,0x08,0x2c,0x3c,0x05,0x00,0x30, ++0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x02,0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0x30, ++0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x02,0x24,0x04,0x08,0x3c,0x3c,0x05,0x00,0x30, ++0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x02,0x08,0x00,0x17,0xc5,0x3c,0x02,0xb0,0x03, ++0x24,0x04,0x08,0x8c,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x04,0x24,0x04,0x08,0x80, ++0x24,0x05,0x1e,0x00,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x04,0x24,0x04,0x0c,0x04, ++0x24,0x05,0x00,0x0f,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x04,0x24,0x04,0x0d,0x04, ++0x24,0x05,0x00,0x0f,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x04,0x24,0x04,0x08,0x24, ++0x3c,0x05,0x00,0x30,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x03,0x24,0x04,0x08,0x2c, ++0x3c,0x05,0x00,0x30,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x03,0x24,0x04,0x08,0x34, ++0x3c,0x05,0x00,0x30,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x02,0x3c,0x05,0x00,0x30, ++0x24,0x06,0x00,0x03,0x0c,0x00,0x13,0x5f,0x24,0x04,0x08,0x3c,0x02,0x20,0x20,0x21, ++0x24,0x05,0x00,0x14,0x0c,0x00,0x13,0xa4,0x24,0x06,0x01,0x07,0x08,0x00,0x17,0xc5, ++0x3c,0x02,0xb0,0x03,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x73,0x90,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x02,0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00, ++0xa3,0x80,0x81,0x58,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0xa3,0x82,0x81,0x58,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x00,0x80,0x70,0x21,0x34,0x63,0x00,0x20,0x24,0x42,0x60,0x7c, ++0x3c,0x04,0xb0,0x03,0xac,0x62,0x00,0x00,0x34,0x84,0x00,0x30,0xad,0xc0,0x02,0xb8, ++0x8c,0x83,0x00,0x00,0x24,0x02,0x00,0xff,0xa5,0xc0,0x00,0x0a,0x00,0x00,0x30,0x21, ++0xa7,0x82,0x8f,0xf0,0x27,0x88,0x90,0x00,0xa5,0xc3,0x00,0x08,0x3c,0x07,0xb0,0x08, ++0x30,0xc2,0xff,0xff,0x00,0x02,0x20,0xc0,0x24,0xc3,0x00,0x01,0x00,0x82,0x10,0x21, ++0x00,0x60,0x30,0x21,0x00,0x02,0x10,0x80,0x30,0x63,0xff,0xff,0x00,0x48,0x10,0x21, ++0x00,0x87,0x20,0x21,0x28,0xc5,0x00,0xff,0xac,0x83,0x00,0x00,0x14,0xa0,0xff,0xf4, ++0xa4,0x43,0x00,0x00,0x3c,0x02,0xb0,0x08,0x34,0x03,0xff,0xff,0x25,0xc4,0x00,0x0c, ++0x24,0x0a,0x00,0x02,0x34,0x42,0x07,0xf8,0x3c,0x06,0xb0,0x03,0xa7,0x83,0xb3,0xdc, ++0xac,0x43,0x00,0x00,0xaf,0x84,0xb4,0x00,0x34,0xc6,0x00,0x64,0xa0,0x8a,0x00,0x18, ++0x94,0xc5,0x00,0x00,0x8f,0x82,0xb4,0x00,0x25,0xc4,0x00,0x30,0x24,0x08,0x00,0x03, ++0x3c,0x03,0xb0,0x03,0xa0,0x45,0x00,0x21,0x34,0x63,0x00,0x66,0xaf,0x84,0xb4,0x04, ++0xa0,0x88,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xb4,0x04,0x25,0xc4,0x00,0x54, ++0x25,0xc7,0x00,0x78,0xa0,0x45,0x00,0x21,0xaf,0x84,0xb4,0x08,0xa0,0x88,0x00,0x18, ++0x94,0x65,0x00,0x00,0x8f,0x82,0xb4,0x08,0x25,0xc8,0x00,0x9c,0x24,0x09,0x00,0x01, ++0xa0,0x45,0x00,0x21,0xaf,0x87,0xb4,0x0c,0xa0,0xea,0x00,0x18,0x94,0xc4,0x00,0x00, ++0x8f,0x82,0xb4,0x0c,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x62,0xa0,0x44,0x00,0x21, ++0xaf,0x88,0xb4,0x10,0xa1,0x09,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xb4,0x10, ++0x25,0xc4,0x00,0xc0,0x3c,0x06,0xb0,0x03,0xa0,0x45,0x00,0x21,0xaf,0x84,0xb4,0x14, ++0xa0,0x89,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xb4,0x14,0x25,0xc4,0x00,0xe4, ++0x34,0xc6,0x00,0x60,0xa0,0x45,0x00,0x21,0xaf,0x84,0xb4,0x18,0xa0,0x80,0x00,0x18, ++0x94,0xc5,0x00,0x00,0x8f,0x82,0xb4,0x18,0x25,0xc3,0x01,0x08,0x25,0xc7,0x01,0x2c, ++0xa0,0x45,0x00,0x21,0xaf,0x83,0xb4,0x1c,0xa0,0x60,0x00,0x18,0x94,0xc8,0x00,0x00, ++0x8f,0x82,0xb4,0x1c,0x25,0xc4,0x01,0x50,0x25,0xc5,0x01,0x74,0xa0,0x48,0x00,0x21, ++0x25,0xc6,0x01,0x98,0x25,0xc9,0x01,0xbc,0x25,0xca,0x01,0xe0,0x25,0xcb,0x02,0x04, ++0x25,0xcc,0x02,0x28,0x25,0xcd,0x02,0x4c,0x24,0x02,0x00,0x10,0x3c,0x03,0xb0,0x03, ++0xaf,0x87,0xb4,0x20,0x34,0x63,0x00,0x38,0xa0,0xe0,0x00,0x18,0xaf,0x84,0xb4,0x24, ++0xa0,0x80,0x00,0x18,0xaf,0x85,0xb4,0x28,0xa0,0xa0,0x00,0x18,0xaf,0x86,0xb4,0x2c, ++0xa0,0xc0,0x00,0x18,0xaf,0x89,0xb4,0x30,0xa1,0x20,0x00,0x18,0xaf,0x8a,0xb4,0x34, ++0xa1,0x40,0x00,0x18,0xaf,0x8b,0xb4,0x38,0xa1,0x60,0x00,0x18,0xaf,0x8c,0xb4,0x3c, ++0xa1,0x80,0x00,0x18,0xaf,0x8d,0xb4,0x40,0xa1,0xa2,0x00,0x18,0x94,0x64,0x00,0x00, ++0x8f,0x82,0xb4,0x40,0x25,0xc5,0x02,0x70,0x3c,0x03,0xb0,0x03,0xa0,0x44,0x00,0x21, ++0x24,0x02,0x00,0x11,0xaf,0x85,0xb4,0x44,0x34,0x63,0x00,0x6e,0xa0,0xa2,0x00,0x18, ++0x94,0x64,0x00,0x00,0x8f,0x82,0xb4,0x44,0x25,0xc5,0x02,0x94,0x3c,0x03,0xb0,0x03, ++0xa0,0x44,0x00,0x21,0x24,0x02,0x00,0x12,0xaf,0x85,0xb4,0x48,0x34,0x63,0x00,0x6c, ++0xa0,0xa2,0x00,0x18,0x94,0x64,0x00,0x00,0x8f,0x82,0xb4,0x48,0x24,0x05,0xff,0xff, ++0x24,0x07,0x00,0x01,0xa0,0x44,0x00,0x21,0x24,0x06,0x00,0x12,0x27,0x84,0xb4,0x00, ++0x8c,0x82,0x00,0x00,0x24,0xc6,0xff,0xff,0xa0,0x40,0x00,0x04,0x8c,0x83,0x00,0x00, ++0xa4,0x45,0x00,0x00,0xa4,0x45,0x00,0x02,0xa0,0x60,0x00,0x0a,0x8c,0x82,0x00,0x00, ++0xa4,0x65,0x00,0x06,0xa4,0x65,0x00,0x08,0xa0,0x40,0x00,0x10,0x8c,0x83,0x00,0x00, ++0xa4,0x45,0x00,0x0c,0xa4,0x45,0x00,0x0e,0xa0,0x60,0x00,0x12,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0xa0,0x40,0x00,0x16,0x8c,0x83,0x00,0x00,0xa4,0x45,0x00,0x14, ++0xa0,0x67,0x00,0x17,0x8c,0x82,0x00,0x00,0x24,0x84,0x00,0x04,0xa0,0x40,0x00,0x20, ++0x04,0xc1,0xff,0xe7,0xac,0x40,0x00,0x1c,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,0x34,0x42,0x00,0x20,0x24,0x63,0x63,0x40, ++0xac,0x43,0x00,0x00,0x90,0x82,0x00,0x10,0x00,0x80,0x60,0x21,0x10,0x40,0x00,0x56, ++0x00,0x00,0x70,0x21,0x97,0x82,0x8f,0xf0,0x94,0x8a,0x00,0x0c,0x27,0x87,0x90,0x00, ++0x00,0x02,0x40,0xc0,0x01,0x02,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x47,0x10,0x21, ++0x90,0x8b,0x00,0x18,0xa4,0x4a,0x00,0x00,0x94,0x83,0x00,0x0e,0x39,0x64,0x00,0x10, ++0x2c,0x84,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x34,0x85,0x00,0x02, ++0x39,0x63,0x00,0x11,0x00,0x83,0x28,0x0b,0x34,0xa3,0x00,0x08,0x39,0x64,0x00,0x12, ++0x00,0x02,0x10,0x80,0x00,0xa4,0x18,0x0b,0x00,0x47,0x10,0x21,0x94,0x49,0x00,0x04, ++0x34,0x64,0x00,0x20,0x00,0x6b,0x20,0x0b,0x34,0x83,0x00,0x40,0x39,0x62,0x00,0x01, ++0x00,0x82,0x18,0x0b,0x00,0x09,0x30,0xc0,0x34,0x64,0x00,0x80,0x00,0xc9,0x28,0x21, ++0x39,0x62,0x00,0x02,0x00,0x60,0x68,0x21,0x00,0x82,0x68,0x0a,0x00,0x05,0x28,0x80, ++0x3c,0x02,0xb0,0x08,0x00,0xa7,0x28,0x21,0x00,0xc2,0x30,0x21,0x01,0x02,0x40,0x21, ++0x34,0x03,0xff,0xff,0x35,0xa4,0x01,0x00,0x39,0x62,0x00,0x03,0x2d,0x67,0x00,0x13, ++0xad,0x0a,0x00,0x00,0xa4,0xa3,0x00,0x00,0xac,0xc3,0x00,0x00,0xa7,0x89,0x8f,0xf0, ++0x10,0xe0,0x00,0x0f,0x00,0x82,0x68,0x0a,0x3c,0x03,0x80,0x01,0x00,0x0b,0x10,0x80, ++0x24,0x63,0x02,0x44,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x60, ++0x94,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x14,0x00,0x00,0x02,0x74,0x03, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x3a,0x94,0x44,0x00,0x00,0x93,0x83,0x8f,0xe4, ++0x91,0x82,0x00,0x21,0x01,0xc4,0x20,0x21,0x91,0x85,0x00,0x10,0x00,0x04,0x24,0x00, ++0x00,0x62,0x18,0x21,0x00,0x04,0x74,0x03,0x00,0x6e,0x18,0x23,0x00,0x65,0x10,0x2a, ++0x00,0xa2,0x18,0x0a,0x00,0x0d,0x24,0x00,0x3c,0x02,0xb0,0x06,0x24,0x05,0xff,0xff, ++0x00,0x64,0x18,0x25,0x34,0x42,0x80,0x20,0xac,0x43,0x00,0x00,0xa5,0x85,0x00,0x0e, ++0xa1,0x80,0x00,0x10,0xa5,0x85,0x00,0x0c,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x3c,0x03,0xb0,0x03,0x08,0x00,0x19,0x14,0x34,0x63,0x00,0x62,0x3c,0x03,0xb0,0x03, ++0x08,0x00,0x19,0x14,0x34,0x63,0x00,0x64,0x3c,0x03,0xb0,0x03,0x08,0x00,0x19,0x14, ++0x34,0x63,0x00,0x66,0x3c,0x03,0xb0,0x03,0x08,0x00,0x19,0x14,0x34,0x63,0x00,0x38, ++0x3c,0x03,0xb0,0x03,0x08,0x00,0x19,0x14,0x34,0x63,0x00,0x6e,0x3c,0x03,0xb0,0x03, ++0x08,0x00,0x19,0x14,0x34,0x63,0x00,0x6c,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00, ++0x34,0x63,0x00,0x20,0x24,0x42,0x65,0x08,0x00,0x05,0x28,0x40,0xac,0x62,0x00,0x00, ++0x00,0xa6,0x28,0x21,0x2c,0xe2,0x00,0x10,0x14,0x80,0x00,0x06,0x00,0x00,0x18,0x21, ++0x10,0x40,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0xe0,0x18,0x21,0x03,0xe0,0x00,0x08, ++0x00,0x60,0x10,0x21,0x24,0x02,0x00,0x20,0x10,0xe2,0x00,0x06,0x2c,0xe4,0x00,0x10, ++0x24,0xa2,0x00,0x01,0x10,0x80,0xff,0xf9,0x00,0x02,0x11,0x00,0x08,0x00,0x19,0x4f, ++0x00,0x47,0x18,0x21,0x08,0x00,0x19,0x4f,0x24,0xa3,0x00,0x50,0x27,0xbd,0xff,0xc8, ++0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x30, ++0xaf,0xb7,0x00,0x2c,0xaf,0xb6,0x00,0x28,0xaf,0xb5,0x00,0x24,0xaf,0xb4,0x00,0x20, ++0xaf,0xb0,0x00,0x10,0x00,0x80,0x88,0x21,0x84,0x84,0x00,0x08,0x3c,0x05,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x34,0xa5,0x00,0x20,0x24,0x42,0x65,0x6c,0x3c,0x03,0xb0,0x06, ++0x00,0x04,0x20,0x80,0xac,0xa2,0x00,0x00,0x00,0x83,0x20,0x21,0x3c,0x06,0xb0,0x06, ++0x8c,0x82,0x00,0x00,0x34,0xc6,0x80,0x24,0x8c,0x88,0x00,0x00,0x8c,0xc4,0x00,0x00, ++0x96,0x25,0x00,0x08,0x30,0x52,0xff,0xff,0x00,0x08,0x44,0x02,0x34,0x84,0x01,0x00, ++0x3c,0x02,0xb0,0x00,0x00,0x08,0x18,0xc0,0x00,0x12,0x3a,0x00,0xac,0xc4,0x00,0x00, ++0x00,0xe2,0x38,0x21,0xae,0x32,0x02,0xb8,0x00,0x68,0x18,0x21,0x24,0xa5,0x00,0x02, ++0x8c,0xf6,0x00,0x00,0x30,0xa5,0x01,0xff,0x8c,0xf4,0x00,0x04,0x27,0x86,0x90,0x00, ++0x00,0x03,0x18,0x80,0x00,0x12,0x98,0xc0,0xa6,0x25,0x00,0x08,0x00,0x66,0x18,0x21, ++0x02,0x72,0x10,0x21,0x94,0x65,0x00,0x00,0x00,0x02,0x48,0x80,0x01,0x26,0x30,0x21, ++0x24,0x02,0xff,0xff,0x00,0x14,0x1a,0x02,0x27,0x84,0x90,0x10,0xa4,0xc2,0x00,0x02, ++0x30,0x63,0x00,0x1f,0x24,0x02,0x00,0x10,0x01,0x24,0x20,0x21,0xa4,0xc8,0x00,0x04, ++0x8c,0xf0,0x00,0x08,0xa6,0x23,0x00,0x06,0xa6,0x25,0x00,0x0a,0xa0,0x82,0x00,0x06, ++0x86,0x25,0x00,0x06,0x27,0x82,0x90,0x04,0x01,0x22,0x10,0x21,0x24,0x03,0x00,0x13, ++0x10,0xa3,0x00,0xee,0xac,0x47,0x00,0x18,0x3c,0x03,0xb0,0x03,0x34,0x63,0x01,0x00, ++0xa6,0x20,0x00,0x02,0x3c,0x02,0xb0,0x03,0x90,0x64,0x00,0x00,0x34,0x42,0x01,0x08, ++0x8c,0x45,0x00,0x00,0x00,0x10,0x1b,0xc2,0x00,0x04,0x20,0x82,0x30,0x63,0x00,0x01, ++0xac,0xc5,0x00,0x08,0x10,0x60,0x00,0xc7,0x30,0x97,0x00,0x01,0x00,0x10,0x16,0x82, ++0x30,0x46,0x00,0x01,0x00,0x10,0x12,0x02,0x00,0x10,0x19,0xc2,0x00,0x10,0x26,0x02, ++0x00,0x10,0x2e,0x42,0x30,0x48,0x00,0x7f,0x24,0x02,0x00,0x01,0x30,0x75,0x00,0x01, ++0x30,0x84,0x00,0x01,0x10,0xc2,0x00,0xb3,0x30,0xa3,0x00,0x01,0x00,0x60,0x28,0x21, ++0x0c,0x00,0x19,0x42,0x01,0x00,0x38,0x21,0x02,0x72,0x18,0x21,0x00,0x03,0x18,0x80, ++0x2c,0x46,0x00,0x54,0x27,0x85,0x90,0x10,0x27,0x84,0x90,0x08,0x00,0x06,0x10,0x0a, ++0x00,0x65,0x28,0x21,0x26,0xa6,0x00,0x02,0x00,0x64,0x18,0x21,0xa0,0xa2,0x00,0x02, ++0xa0,0x66,0x00,0x06,0xa0,0x62,0x00,0x07,0xa0,0xa2,0x00,0x01,0x02,0x72,0x28,0x21, ++0x00,0x05,0x28,0x80,0x27,0x82,0x90,0x04,0x00,0xa2,0x58,0x21,0x8d,0x64,0x00,0x18, ++0x00,0x10,0x15,0xc2,0x30,0x42,0x00,0x01,0x8c,0x83,0x00,0x0c,0x27,0x84,0x90,0x20, ++0x00,0xa4,0x48,0x21,0xa6,0x22,0x00,0x00,0xa6,0x36,0x00,0x04,0x8d,0x26,0x00,0x00, ++0x00,0x03,0x19,0x42,0x3c,0x02,0xff,0xef,0x34,0x42,0xff,0xff,0x30,0x63,0x00,0x01, ++0x00,0xc2,0x40,0x24,0x00,0x03,0x1d,0x00,0x01,0x03,0x40,0x25,0x00,0x08,0x15,0x02, ++0x00,0x14,0x19,0x82,0x00,0x14,0x25,0x82,0x00,0x10,0x34,0x42,0x00,0x10,0x3c,0x82, ++0x00,0x10,0x2c,0x02,0x30,0x42,0x00,0x01,0x30,0xcd,0x00,0x01,0x30,0x6c,0x00,0x01, ++0x30,0xe6,0x00,0x01,0x30,0x8a,0x00,0x03,0x32,0x94,0x00,0x07,0x30,0xa5,0x00,0x01, ++0xad,0x28,0x00,0x00,0x10,0x40,0x00,0x0b,0x32,0x07,0x00,0x7f,0x8d,0x64,0x00,0x18, ++0x3c,0x03,0xff,0xf0,0x34,0x63,0xff,0xff,0x8c,0x82,0x00,0x0c,0x01,0x03,0x18,0x24, ++0x00,0x02,0x13,0x82,0x30,0x42,0x00,0x0f,0x00,0x02,0x14,0x00,0x00,0x62,0x18,0x25, ++0xad,0x23,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xc2,0x00,0x6a,0x00,0x00,0x00,0x00, ++0x15,0x80,0x00,0x03,0x00,0x00,0x00,0x00,0x15,0x40,0x00,0x5b,0x24,0x02,0x00,0x01, ++0x96,0x22,0x00,0x04,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x04,0xa6,0x22,0x00,0x04, ++0x00,0xa0,0x20,0x21,0x0c,0x00,0x19,0x42,0x01,0xa0,0x28,0x21,0x02,0x72,0x18,0x21, ++0x00,0x03,0x40,0x80,0x2c,0x45,0x00,0x54,0x27,0x84,0x90,0x10,0x01,0x04,0x20,0x21, ++0x00,0x05,0x10,0x0a,0xa0,0x82,0x00,0x00,0xa0,0x80,0x00,0x04,0xa0,0x80,0x00,0x05, ++0x96,0x23,0x00,0x04,0x27,0x82,0x90,0x00,0x01,0x02,0x10,0x21,0xa4,0x43,0x00,0x06, ++0x27,0x82,0x90,0x04,0x92,0x26,0x00,0x01,0x01,0x02,0x10,0x21,0x8c,0x45,0x00,0x18, ++0x27,0x83,0x90,0x20,0x01,0x03,0x18,0x21,0xa0,0x60,0x00,0x00,0xa0,0x86,0x00,0x07, ++0x94,0xa2,0x00,0x10,0x24,0x03,0x00,0x04,0x30,0x42,0x00,0x0f,0x10,0x43,0x00,0x36, ++0x24,0xa5,0x00,0x10,0x94,0xa3,0x00,0x16,0x27,0x87,0x90,0x18,0x01,0x07,0x10,0x21, ++0xa4,0x43,0x00,0x02,0x94,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01, ++0x14,0x40,0x00,0x24,0x02,0x72,0x20,0x21,0x94,0xa2,0x00,0x00,0x24,0x03,0x00,0xa4, ++0x30,0x42,0x00,0xff,0x10,0x43,0x00,0x1f,0x00,0x00,0x00,0x00,0x94,0xa2,0x00,0x00, ++0x24,0x03,0x00,0x88,0x30,0x42,0x00,0x88,0x10,0x43,0x00,0x14,0x02,0x72,0x18,0x21, ++0x27,0x84,0x90,0x20,0x00,0x03,0x18,0x80,0x00,0x64,0x18,0x21,0x8c,0x62,0x00,0x00, ++0x3c,0x04,0x00,0x80,0x00,0x44,0x10,0x25,0xac,0x62,0x00,0x00,0x02,0x72,0x10,0x21, ++0x00,0x02,0x10,0x80,0x00,0x47,0x10,0x21,0xa0,0x54,0x00,0x00,0x8f,0xbf,0x00,0x30, ++0x7b,0xb6,0x01,0x7c,0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc, ++0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0x94,0xa2,0x00,0x18, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x60,0x10,0x40,0xff,0xe9,0x02,0x72,0x18,0x21, ++0x02,0x72,0x20,0x21,0x27,0x82,0x90,0x20,0x00,0x04,0x20,0x80,0x00,0x82,0x20,0x21, ++0x8c,0x83,0x00,0x00,0x3c,0x02,0xff,0x7f,0x34,0x42,0xff,0xff,0x00,0x62,0x18,0x24, ++0x08,0x00,0x1a,0x37,0xac,0x83,0x00,0x00,0x27,0x87,0x90,0x18,0x01,0x07,0x10,0x21, ++0x08,0x00,0x1a,0x21,0xa4,0x40,0x00,0x02,0x11,0x42,0x00,0x07,0x00,0x00,0x00,0x00, ++0x2d,0x42,0x00,0x02,0x14,0x40,0xff,0xa7,0x00,0xa0,0x20,0x21,0x96,0x22,0x00,0x04, ++0x08,0x00,0x19,0xff,0x24,0x42,0x00,0x0c,0x96,0x22,0x00,0x04,0x08,0x00,0x19,0xff, ++0x24,0x42,0x00,0x08,0x16,0xe6,0xff,0x96,0x3c,0x02,0xff,0xfb,0x8d,0x63,0x00,0x18, ++0x34,0x42,0xff,0xff,0x02,0x02,0x10,0x24,0xac,0x62,0x00,0x08,0x08,0x00,0x19,0xf8, ++0x00,0x00,0x30,0x21,0x16,0xe6,0xff,0x4e,0x00,0x60,0x28,0x21,0x3c,0x02,0xfb,0xff, ++0x34,0x42,0xff,0xff,0x02,0x02,0x10,0x24,0xac,0xe2,0x00,0x08,0x08,0x00,0x19,0xb7, ++0x00,0x00,0x30,0x21,0x93,0x87,0xbb,0x14,0x00,0x10,0x1e,0x42,0x00,0x10,0x26,0x82, ++0x27,0x82,0x90,0x08,0x2c,0xe5,0x00,0x0c,0x01,0x22,0x48,0x21,0x30,0x63,0x00,0x01, ++0x30,0x86,0x00,0x01,0x14,0xa0,0x00,0x06,0x00,0xe0,0x40,0x21,0x00,0x03,0x10,0x40, ++0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0xe2,0x10,0x21,0x24,0x48,0x00,0x04, ++0x02,0x72,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x84,0x90,0x10,0x27,0x83,0x90,0x08, ++0x00,0x44,0x20,0x21,0x00,0x43,0x10,0x21,0xa1,0x28,0x00,0x07,0xa0,0x40,0x00,0x06, ++0xa0,0x80,0x00,0x02,0x08,0x00,0x19,0xc7,0xa0,0x80,0x00,0x01,0x24,0x02,0x00,0x01, ++0xa6,0x22,0x00,0x02,0x0c,0x00,0x01,0xc2,0x00,0xe0,0x20,0x21,0x08,0x00,0x1a,0x3b, ++0x00,0x00,0x00,0x00,0x30,0xa7,0xff,0xff,0x00,0x07,0x18,0xc0,0x00,0x67,0x18,0x21, ++0x3c,0x06,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x6a,0x44,0x27,0x85,0x90,0x10, ++0x00,0x03,0x18,0x80,0x34,0xc6,0x00,0x20,0x00,0x65,0x18,0x21,0xac,0xc2,0x00,0x00, ++0x80,0x62,0x00,0x07,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x29,0x00,0x80,0x28,0x21, ++0x90,0x82,0x00,0x16,0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02,0x30,0x43,0x00,0x01, ++0x14,0x60,0x00,0x02,0xa0,0x82,0x00,0x16,0xa0,0x80,0x00,0x17,0x90,0xa2,0x00,0x04, ++0x3c,0x03,0xb0,0x03,0x27,0x86,0x90,0x00,0x14,0x40,0x00,0x06,0x34,0x63,0x00,0x20, ++0x24,0x02,0x00,0x01,0xa0,0xa2,0x00,0x04,0xa4,0xa7,0x00,0x02,0x03,0xe0,0x00,0x08, ++0xa4,0xa7,0x00,0x00,0x94,0xa4,0x00,0x02,0x3c,0x02,0x80,0x01,0x24,0x42,0x82,0x6c, ++0xac,0x62,0x00,0x00,0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80, ++0x00,0x66,0x18,0x21,0x94,0x62,0x00,0x04,0xa4,0x67,0x00,0x02,0x3c,0x03,0xb0,0x08, ++0x00,0x02,0x20,0xc0,0x00,0x82,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21, ++0x00,0x83,0x20,0x21,0xa4,0x47,0x00,0x00,0xac,0x87,0x00,0x00,0x90,0xa2,0x00,0x04, ++0xa4,0xa7,0x00,0x02,0x24,0x42,0x00,0x01,0x03,0xe0,0x00,0x08,0xa0,0xa2,0x00,0x04, ++0x90,0x82,0x00,0x16,0x24,0x85,0x00,0x06,0x34,0x42,0x00,0x01,0x30,0x43,0x00,0x02, ++0x14,0x60,0xff,0xda,0xa0,0x82,0x00,0x16,0x24,0x02,0x00,0x01,0x08,0x00,0x1a,0xa7, ++0xa0,0x82,0x00,0x17,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x00,0x80,0x38,0x21, ++0x84,0x84,0x00,0x02,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x3c,0x0a,0xb0,0x06, ++0x34,0x63,0x00,0x20,0x24,0x42,0x6b,0x44,0x3c,0x0b,0xb0,0x08,0x27,0x89,0x90,0x00, ++0x34,0x0c,0xff,0xff,0x35,0x4a,0x80,0x20,0x10,0x80,0x00,0x30,0xac,0x62,0x00,0x00, ++0x97,0x82,0x8f,0xf0,0x94,0xe6,0x02,0xba,0x00,0x02,0x18,0xc0,0x00,0x6b,0x28,0x21, ++0xac,0xa6,0x00,0x00,0x8c,0xe4,0x02,0xb8,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80, ++0x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x49,0x10,0x21, ++0x94,0x48,0x00,0x04,0x00,0x69,0x18,0x21,0xa4,0x66,0x00,0x00,0x00,0x08,0x28,0xc0, ++0x00,0xab,0x10,0x21,0xac,0x4c,0x00,0x00,0x8c,0xe4,0x02,0xb8,0x27,0x82,0x90,0x04, ++0x00,0xa8,0x28,0x21,0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80, ++0x00,0x62,0x10,0x21,0x8c,0x46,0x00,0x18,0x27,0x84,0x90,0x10,0x00,0x64,0x18,0x21, ++0x8c,0xc2,0x00,0x00,0x80,0x67,0x00,0x06,0x00,0x05,0x28,0x80,0x30,0x42,0xff,0xff, ++0x00,0x47,0x10,0x21,0x30,0x43,0x00,0xff,0x00,0x03,0x18,0x2b,0x00,0x02,0x12,0x02, ++0x00,0x43,0x10,0x21,0x3c,0x04,0x00,0x04,0x00,0xa9,0x28,0x21,0x00,0x44,0x10,0x25, ++0xa4,0xac,0x00,0x00,0xad,0x42,0x00,0x00,0xa7,0x88,0x8f,0xf0,0x8f,0xbf,0x00,0x10, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x84,0xe3,0x00,0x06, ++0x27,0x82,0xb4,0x00,0x94,0xe5,0x02,0xba,0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21, ++0x8c,0x64,0x00,0x00,0x0c,0x00,0x1a,0x91,0x00,0x00,0x00,0x00,0x08,0x00,0x1b,0x0b, ++0x00,0x00,0x00,0x00,0x94,0x88,0x00,0x00,0x00,0x80,0x58,0x21,0x27,0x8a,0x90,0x00, ++0x00,0x08,0x18,0xc0,0x00,0x68,0x18,0x21,0x3c,0x04,0xb0,0x03,0x00,0x03,0x18,0x80, ++0x3c,0x02,0x80,0x00,0x00,0x6a,0x18,0x21,0x34,0x84,0x00,0x20,0x24,0x42,0x6c,0x64, ++0x30,0xa5,0xff,0xff,0xac,0x82,0x00,0x00,0x94,0x67,0x00,0x02,0x11,0x05,0x00,0x35, ++0x24,0x04,0x00,0x01,0x91,0x66,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x86,0x10,0x2a, ++0x10,0x40,0x00,0x10,0x00,0xc0,0x48,0x21,0x3c,0x0d,0xb0,0x03,0x01,0x40,0x60,0x21, ++0x35,0xad,0x00,0x20,0x10,0xe5,0x00,0x0d,0x24,0x84,0x00,0x01,0x00,0x07,0x10,0xc0, ++0x00,0x47,0x10,0x21,0x00,0x02,0x10,0x80,0x01,0x20,0x30,0x21,0x00,0x4a,0x10,0x21, ++0x00,0x86,0x18,0x2a,0x00,0xe0,0x40,0x21,0x94,0x47,0x00,0x02,0x14,0x60,0xff,0xf5, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x10,0x21,0x00,0x08,0x20,0xc0, ++0x00,0x88,0x20,0x21,0x24,0xc2,0xff,0xff,0x00,0x04,0x20,0x80,0xa1,0x62,0x00,0x04, ++0x00,0x8c,0x20,0x21,0x94,0x83,0x00,0x04,0x00,0x07,0x10,0xc0,0x00,0x47,0x10,0x21, ++0x00,0x02,0x10,0x80,0x00,0x4c,0x10,0x21,0x00,0x03,0x28,0xc0,0x94,0x46,0x00,0x02, ++0x00,0xa3,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x6c,0x18,0x21,0xa4,0x66,0x00,0x00, ++0xa4,0x86,0x00,0x02,0x95,0x64,0x00,0x02,0x3c,0x03,0xb0,0x08,0x3c,0x02,0x80,0x01, ++0x00,0xa3,0x28,0x21,0x24,0x42,0x82,0x6c,0xad,0xa2,0x00,0x00,0x10,0x87,0x00,0x03, ++0xac,0xa6,0x00,0x00,0x03,0xe0,0x00,0x08,0x24,0x02,0x00,0x01,0x08,0x00,0x1b,0x59, ++0xa5,0x68,0x00,0x02,0x91,0x62,0x00,0x04,0xa5,0x67,0x00,0x00,0x24,0x42,0xff,0xff, ++0x30,0x43,0x00,0xff,0x14,0x60,0xff,0xf7,0xa1,0x62,0x00,0x04,0x24,0x02,0xff,0xff, ++0x08,0x00,0x1b,0x59,0xa5,0x62,0x00,0x02,0x00,0x05,0x40,0xc0,0x01,0x05,0x30,0x21, ++0x27,0xbd,0xff,0xd8,0x00,0x06,0x30,0x80,0x27,0x82,0x90,0x04,0xaf,0xb2,0x00,0x18, ++0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb0,0x00,0x10, ++0x00,0xc2,0x10,0x21,0x8c,0x47,0x00,0x18,0x00,0xa0,0x90,0x21,0x3c,0x02,0x80,0x00, ++0x3c,0x05,0xb0,0x03,0x34,0xa5,0x00,0x20,0x24,0x42,0x6d,0x98,0xac,0xa2,0x00,0x00, ++0x27,0x83,0x90,0x10,0x00,0xc3,0x30,0x21,0x8c,0xe2,0x00,0x00,0x80,0xc5,0x00,0x06, ++0x00,0x80,0x88,0x21,0x30,0x42,0xff,0xff,0x00,0x45,0x10,0x21,0x30,0x43,0x00,0xff, ++0x10,0x60,0x00,0x02,0x00,0x02,0x12,0x02,0x24,0x42,0x00,0x01,0x30,0x53,0x00,0xff, ++0x01,0x12,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21, ++0x80,0x44,0x00,0x07,0x00,0x00,0x00,0x00,0x10,0x80,0x00,0x4b,0x26,0x24,0x00,0x06, ++0x32,0x50,0xff,0xff,0x02,0x20,0x20,0x21,0x0c,0x00,0x1b,0x19,0x02,0x00,0x28,0x21, ++0x92,0x22,0x00,0x10,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x2e,0x3c,0x03,0xb0,0x08, ++0x3c,0x09,0x80,0x01,0x27,0x88,0x90,0x00,0xa6,0x32,0x00,0x0c,0x00,0x10,0x20,0xc0, ++0x00,0x90,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x88,0x20,0x21,0x94,0x82,0x00,0x04, ++0x3c,0x03,0xb0,0x08,0x3c,0x07,0xb0,0x03,0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21, ++0x00,0x02,0x10,0x80,0x00,0x48,0x10,0x21,0x00,0xa3,0x28,0x21,0x25,0x26,0x82,0x6c, ++0x34,0x03,0xff,0xff,0x34,0xe7,0x00,0x20,0xac,0xe6,0x00,0x00,0xa4,0x83,0x00,0x02, ++0xa4,0x43,0x00,0x00,0xac,0xa3,0x00,0x00,0x92,0x22,0x00,0x10,0x92,0x23,0x00,0x0a, ++0xa6,0x32,0x00,0x0e,0x02,0x62,0x10,0x21,0x14,0x60,0x00,0x05,0xa2,0x22,0x00,0x10, ++0x92,0x22,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfe,0xa2,0x22,0x00,0x16, ++0x92,0x22,0x00,0x04,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00, ++0x92,0x22,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfd,0xa2,0x22,0x00,0x16, ++0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x28,0x96,0x22,0x00,0x0e,0x27,0x88,0x90,0x00,0x00,0x02,0x20,0xc0, ++0x00,0x82,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x88,0x20,0x21,0x94,0x82,0x00,0x04, ++0x3c,0x06,0xb0,0x03,0x3c,0x09,0x80,0x01,0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21, ++0x00,0x02,0x10,0x80,0x00,0xa3,0x28,0x21,0x00,0x48,0x10,0x21,0x34,0xc6,0x00,0x20, ++0x25,0x23,0x82,0x6c,0xac,0xc3,0x00,0x00,0xa4,0x50,0x00,0x00,0xac,0xb0,0x00,0x00, ++0x08,0x00,0x1b,0x97,0xa4,0x90,0x00,0x02,0x08,0x00,0x1b,0x8e,0x32,0x50,0xff,0xff, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x6f,0x60,0x34,0x63,0x00,0x20, ++0xac,0x62,0x00,0x00,0x90,0x82,0x00,0x04,0x97,0xaa,0x00,0x12,0x00,0x80,0x60,0x21, ++0x30,0xa8,0xff,0xff,0x00,0x4a,0x20,0x23,0x34,0x09,0xff,0xff,0x30,0xcf,0xff,0xff, ++0x30,0xee,0xff,0xff,0x11,0x09,0x00,0x73,0xa1,0x84,0x00,0x04,0x00,0x0e,0xc0,0xc0, ++0x00,0x08,0x10,0xc0,0x00,0x48,0x10,0x21,0x03,0x0e,0x20,0x21,0x27,0x8d,0x90,0x00, ++0x00,0x04,0x20,0x80,0x00,0x02,0x10,0x80,0x00,0x4d,0x10,0x21,0x00,0x8d,0x20,0x21, ++0x94,0x86,0x00,0x02,0x94,0x43,0x00,0x04,0x3c,0x19,0x80,0x01,0xa4,0x46,0x00,0x02, ++0x00,0x03,0x28,0xc0,0x00,0xa3,0x18,0x21,0x94,0x87,0x00,0x02,0x3c,0x02,0xb0,0x08, ++0x00,0x03,0x18,0x80,0x00,0xa2,0x28,0x21,0x00,0x6d,0x18,0x21,0x27,0x22,0x82,0x6c, ++0x3c,0x01,0xb0,0x03,0xac,0x22,0x00,0x20,0xa4,0x66,0x00,0x00,0x10,0xe9,0x00,0x57, ++0xac,0xa6,0x00,0x00,0x01,0xe0,0x30,0x21,0x11,0x40,0x00,0x1d,0x00,0x00,0x48,0x21, ++0x01,0x40,0x38,0x21,0x27,0x8b,0x90,0x04,0x27,0x8a,0x90,0x10,0x00,0x06,0x40,0xc0, ++0x01,0x06,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x6b,0x10,0x21,0x8c,0x44,0x00,0x18, ++0x00,0x6a,0x18,0x21,0x80,0x65,0x00,0x06,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0xff,0xff,0x00,0x45,0x10,0x21,0x30,0x44,0x00,0xff,0x00,0x02,0x12,0x02, ++0x01,0x22,0x18,0x21,0x24,0x62,0x00,0x01,0x14,0x80,0x00,0x02,0x30,0x49,0x00,0xff, ++0x30,0x69,0x00,0xff,0x01,0x06,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x4d,0x10,0x21, ++0x24,0xe7,0xff,0xff,0x94,0x46,0x00,0x02,0x14,0xe0,0xff,0xe9,0x00,0x06,0x40,0xc0, ++0x91,0x82,0x00,0x10,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x20,0x3c,0x06,0xb0,0x03, ++0xa5,0x8f,0x00,0x0c,0x03,0x0e,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x8d,0x20,0x21, ++0x94,0x82,0x00,0x04,0x3c,0x03,0xb0,0x08,0x3c,0x07,0xb0,0x03,0x00,0x02,0x28,0xc0, ++0x00,0xa2,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x4d,0x10,0x21,0x00,0xa3,0x28,0x21, ++0x27,0x26,0x82,0x6c,0x34,0x03,0xff,0xff,0x34,0xe7,0x00,0x20,0xac,0xe6,0x00,0x00, ++0xa4,0x83,0x00,0x02,0xa4,0x43,0x00,0x00,0xac,0xa3,0x00,0x00,0x91,0x82,0x00,0x10, ++0x91,0x83,0x00,0x04,0xa5,0x8e,0x00,0x0e,0x01,0x22,0x10,0x21,0x14,0x60,0x00,0x05, ++0xa1,0x82,0x00,0x10,0x91,0x82,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfd, ++0xa1,0x82,0x00,0x16,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x95,0x82,0x00,0x0e, ++0x3c,0x03,0xb0,0x08,0x00,0x02,0x20,0xc0,0x00,0x82,0x20,0x21,0x00,0x04,0x20,0x80, ++0x00,0x8d,0x20,0x21,0x94,0x82,0x00,0x04,0x34,0xc6,0x00,0x20,0x27,0x27,0x82,0x6c, ++0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0xa3,0x28,0x21, ++0x00,0x4d,0x10,0x21,0xac,0xc7,0x00,0x00,0xa4,0x8f,0x00,0x02,0xa4,0x4f,0x00,0x00, ++0xac,0xaf,0x00,0x00,0x08,0x00,0x1c,0x26,0x03,0x0e,0x20,0x21,0x08,0x00,0x1c,0x01, ++0xa5,0x88,0x00,0x02,0x00,0x0e,0xc0,0xc0,0x03,0x0e,0x10,0x21,0x00,0x02,0x10,0x80, ++0x27,0x8d,0x90,0x00,0x00,0x4d,0x10,0x21,0x94,0x43,0x00,0x02,0x30,0x84,0x00,0xff, ++0x14,0x80,0x00,0x05,0xa5,0x83,0x00,0x00,0x24,0x02,0xff,0xff,0x3c,0x19,0x80,0x01, ++0x08,0x00,0x1c,0x01,0xa5,0x82,0x00,0x02,0x08,0x00,0x1c,0x01,0x3c,0x19,0x80,0x01, ++0x3c,0x08,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0x78,0x35,0x08,0x00,0x20, ++0x24,0x42,0x71,0xa0,0xaf,0xb2,0x00,0x68,0xaf,0xb1,0x00,0x64,0xaf,0xb0,0x00,0x60, ++0xad,0x02,0x00,0x00,0xaf,0xbf,0x00,0x84,0xaf,0xbe,0x00,0x80,0xaf,0xb7,0x00,0x7c, ++0xaf,0xb6,0x00,0x78,0xaf,0xb5,0x00,0x74,0xaf,0xb4,0x00,0x70,0xaf,0xb3,0x00,0x6c, ++0xaf,0xa4,0x00,0x88,0x90,0x83,0x00,0x0a,0x27,0x82,0xb4,0x00,0xaf,0xa6,0x00,0x90, ++0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,0x8c,0x63,0x00,0x00,0xaf,0xa7,0x00,0x94, ++0x27,0x86,0x90,0x04,0xaf,0xa3,0x00,0x1c,0x94,0x63,0x00,0x14,0x30,0xb1,0xff,0xff, ++0x24,0x08,0x00,0x01,0x00,0x03,0x20,0xc0,0xaf,0xa3,0x00,0x18,0x00,0x83,0x18,0x21, ++0xaf,0xa4,0x00,0x54,0x00,0x03,0x18,0x80,0x27,0x84,0x90,0x10,0x00,0x64,0x20,0x21, ++0x80,0x82,0x00,0x06,0x00,0x66,0x18,0x21,0x8c,0x66,0x00,0x18,0x24,0x42,0x00,0x02, ++0x00,0x02,0x1f,0xc2,0x8c,0xc4,0x00,0x08,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43, ++0x00,0x02,0x10,0x40,0x00,0x04,0x2f,0xc2,0x00,0x04,0x1c,0x82,0x00,0xc2,0x38,0x21, ++0x00,0x04,0x24,0x42,0x8f,0xa2,0x00,0x1c,0x30,0x63,0x00,0x01,0x30,0x84,0x00,0x01, ++0xaf,0xa5,0x00,0x3c,0xaf,0xa3,0x00,0x34,0xaf,0xa4,0x00,0x38,0xaf,0xa0,0x00,0x40, ++0xaf,0xa0,0x00,0x44,0xaf,0xa0,0x00,0x50,0xaf,0xa8,0x00,0x20,0x80,0x42,0x00,0x12, ++0x8f,0xb2,0x00,0x18,0xaf,0xa2,0x00,0x28,0x8c,0xd0,0x00,0x0c,0x14,0xa0,0x01,0xe4, ++0x00,0x60,0x30,0x21,0x00,0x10,0x10,0x82,0x30,0x45,0x00,0x07,0x10,0xa0,0x00,0x11, ++0xaf,0xa0,0x00,0x30,0x8f,0xa4,0x00,0x98,0x27,0x82,0x80,0x1c,0x00,0x04,0x18,0x40, ++0x00,0x62,0x18,0x21,0x24,0xa2,0x00,0x06,0x8f,0xa5,0x00,0x20,0x94,0x64,0x00,0x00, ++0x00,0x45,0x10,0x04,0x00,0x44,0x00,0x1a,0x14,0x80,0x00,0x02,0x00,0x00,0x00,0x00, ++0x00,0x07,0x00,0x0d,0x00,0x00,0x10,0x12,0x24,0x42,0x00,0x20,0x30,0x42,0xff,0xfc, ++0xaf,0xa2,0x00,0x30,0x8f,0xa3,0x00,0x18,0x8f,0xa4,0x00,0x28,0x34,0x02,0xff,0xff, ++0xaf,0xa0,0x00,0x2c,0xaf,0xa2,0x00,0x48,0xaf,0xa3,0x00,0x4c,0x00,0x60,0xf0,0x21, ++0x00,0x00,0xb8,0x21,0x18,0x80,0x00,0x48,0xaf,0xa0,0x00,0x24,0x00,0x11,0x89,0x02, ++0xaf,0xb1,0x00,0x58,0x00,0x80,0xa8,0x21,0x00,0x12,0x10,0xc0,0x00,0x52,0x18,0x21, ++0x00,0x03,0x80,0x80,0x27,0x85,0x90,0x00,0x02,0x40,0x20,0x21,0x00,0x40,0xa0,0x21, ++0x02,0x05,0x10,0x21,0x94,0x56,0x00,0x02,0x0c,0x00,0x12,0x8b,0x00,0x00,0x28,0x21, ++0x90,0x42,0x00,0x00,0x24,0x03,0x00,0x08,0x30,0x42,0x00,0x0c,0x10,0x43,0x01,0x9e, ++0x24,0x04,0x00,0x01,0x24,0x02,0x00,0x01,0x10,0x82,0x01,0x7c,0x3c,0x02,0xb0,0x03, ++0x8f,0xa6,0x00,0x88,0x34,0x42,0x01,0x04,0x84,0xc5,0x00,0x0c,0x02,0x92,0x18,0x21, ++0x94,0x46,0x00,0x00,0x00,0x05,0x20,0xc0,0x00,0x85,0x20,0x21,0x00,0x03,0x18,0x80, ++0x27,0x82,0x90,0x10,0x27,0x85,0x90,0x08,0x00,0x65,0x28,0x21,0x00,0x62,0x18,0x21, ++0x80,0x71,0x00,0x05,0x80,0x73,0x00,0x04,0x8f,0xa3,0x00,0x88,0x30,0xd0,0xff,0xff, ++0x00,0x10,0x3a,0x03,0x32,0x08,0x00,0xff,0x27,0x82,0x90,0x20,0x00,0x04,0x20,0x80, ++0x80,0xa6,0x00,0x06,0x00,0x82,0x20,0x21,0xa4,0x67,0x00,0x44,0xa4,0x68,0x00,0x46, ++0x8c,0x84,0x00,0x00,0x38,0xc6,0x00,0x00,0x01,0x00,0x80,0x21,0x00,0x04,0x15,0x02, ++0x30,0x42,0x00,0x01,0x10,0x40,0x00,0x03,0x00,0xe6,0x80,0x0a,0x00,0x04,0x14,0x02, ++0x30,0x50,0x00,0x0f,0x12,0x20,0x01,0x50,0x02,0x40,0x20,0x21,0x02,0x71,0x10,0x21, ++0x00,0x50,0x10,0x2a,0x14,0x40,0x00,0xed,0x02,0x92,0x10,0x21,0x93,0x82,0x8b,0x71, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0xe0,0x02,0x92,0x28,0x21, ++0x26,0xe2,0x00,0x01,0x30,0x57,0xff,0xff,0x02,0x40,0xf0,0x21,0x26,0xb5,0xff,0xff, ++0x16,0xa0,0xff,0xbd,0x02,0xc0,0x90,0x21,0x16,0xe0,0x00,0xd0,0x00,0x00,0x00,0x00, ++0x8f,0xa3,0x00,0x98,0x00,0x00,0x00,0x00,0x2c,0x62,0x00,0x10,0x10,0x40,0x00,0x2e, ++0x00,0x00,0x00,0x00,0x8f,0xa4,0x00,0x24,0x00,0x00,0x00,0x00,0x18,0x80,0x00,0x2a, ++0x24,0x03,0x00,0x01,0x8f,0xa5,0x00,0x1c,0x27,0x84,0x90,0x04,0x94,0xb2,0x00,0x14, ++0xa0,0xa3,0x00,0x12,0x8f,0xa6,0x00,0x3c,0x00,0x12,0x10,0xc0,0x00,0x52,0x10,0x21, ++0x00,0x02,0x80,0x80,0x27,0x82,0x90,0x10,0x02,0x02,0x10,0x21,0x80,0x43,0x00,0x06, ++0x02,0x04,0x20,0x21,0x8c,0x85,0x00,0x18,0x24,0x63,0x00,0x02,0x00,0x03,0x17,0xc2, ++0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x43,0x00,0x03,0x18,0x40,0x14,0xc0,0x00,0x0e, ++0x00,0xa3,0x38,0x21,0x27,0x82,0x90,0x00,0x02,0x02,0x10,0x21,0x94,0x43,0x00,0x06, ++0x8f,0xa8,0x00,0x1c,0x24,0x02,0x00,0x01,0xa5,0x03,0x00,0x1a,0x7b,0xbe,0x04,0x3c, ++0x7b,0xb6,0x03,0xfc,0x7b,0xb4,0x03,0xbc,0x7b,0xb2,0x03,0x7c,0x7b,0xb0,0x03,0x3c, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x88,0x8f,0xa4,0x00,0x98,0x8f,0xa5,0x00,0x38, ++0x8f,0xa6,0x00,0x34,0xaf,0xa0,0x00,0x10,0x0c,0x00,0x09,0x0a,0xaf,0xa0,0x00,0x14, ++0x08,0x00,0x1d,0x2d,0x00,0x00,0x00,0x00,0x8f,0xa3,0x00,0x44,0x93,0x82,0x81,0x58, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x61,0x30,0x69,0x00,0x03,0x8f,0xa4,0x00,0x24, ++0x8f,0xa5,0x00,0x28,0x00,0x00,0x00,0x00,0x00,0x85,0x10,0x2a,0x10,0x40,0x00,0x8f, ++0x00,0x00,0x00,0x00,0x8f,0xa6,0x00,0x1c,0x00,0x00,0x00,0x00,0x90,0xc4,0x00,0x04, ++0x00,0x00,0x00,0x00,0x30,0x83,0x00,0xff,0x00,0xa3,0x10,0x2a,0x10,0x40,0x00,0x87, ++0x00,0x00,0x00,0x00,0x8f,0xa8,0x00,0x24,0x00,0x00,0x00,0x00,0x11,0x00,0x00,0x83, ++0x00,0x65,0x10,0x23,0x00,0xa8,0x18,0x23,0x00,0x62,0x10,0x2a,0x14,0x40,0x00,0x7d, ++0x30,0x63,0x00,0xff,0x00,0x85,0x10,0x23,0x30,0x42,0x00,0xff,0xaf,0xa2,0x00,0x50, ++0x8f,0xa2,0x00,0x50,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x73,0x00,0x00,0xa8,0x21, ++0x27,0x8c,0x90,0x00,0x3c,0x0b,0x80,0xff,0x24,0x10,0x00,0x04,0x27,0x91,0x90,0x04, ++0x35,0x6b,0xff,0xff,0x3c,0x0d,0x7f,0x00,0x27,0x8e,0x90,0x10,0x01,0x80,0x78,0x21, ++0x00,0x12,0x30,0xc0,0x00,0xd2,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x4c,0x10,0x21, ++0x94,0x42,0x00,0x06,0x8f,0xa3,0x00,0x2c,0x8f,0xa4,0x00,0x30,0xaf,0xa2,0x00,0x44, ++0x8f,0xa5,0x00,0x44,0x30,0x49,0x00,0x03,0x02,0x09,0x10,0x23,0x30,0x42,0x00,0x03, ++0x00,0xa2,0x10,0x21,0x8f,0xa8,0x00,0x30,0x24,0x42,0x00,0x04,0x30,0x42,0xff,0xff, ++0x00,0x64,0x38,0x21,0x01,0x02,0x28,0x23,0x00,0x62,0x18,0x21,0x00,0x48,0x10,0x2b, ++0x10,0x40,0x00,0x52,0x00,0x00,0x20,0x21,0x30,0xe7,0xff,0xff,0x30,0xa4,0xff,0xff, ++0xaf,0xa7,0x00,0x2c,0x00,0xd2,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x51,0x18,0x21, ++0x8c,0x65,0x00,0x18,0x00,0x04,0x25,0x40,0x00,0x8d,0x20,0x24,0x8c,0xa8,0x00,0x04, ++0x00,0x4e,0x18,0x21,0x00,0x4f,0x50,0x21,0x01,0x0b,0x40,0x24,0x01,0x04,0x40,0x25, ++0xac,0xa8,0x00,0x04,0x8f,0xa4,0x00,0x98,0x8f,0xa2,0x00,0x50,0x26,0xb5,0x00,0x01, ++0xa0,0x64,0x00,0x00,0x8c,0xa4,0x00,0x08,0x00,0x00,0x00,0x00,0x04,0x81,0x00,0x0c, ++0x02,0xa2,0x30,0x2a,0x80,0x62,0x00,0x06,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x02, ++0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40, ++0x00,0xa2,0x38,0x21,0x8f,0xa5,0x00,0x40,0x00,0x00,0x00,0x00,0xa4,0xe5,0x00,0x00, ++0x95,0x52,0x00,0x02,0x14,0xc0,0xff,0xc7,0x00,0x12,0x30,0xc0,0x8f,0xa4,0x00,0x24, ++0x8f,0xa5,0x00,0x50,0x8f,0xa6,0x00,0x1c,0x8f,0xa3,0x00,0x2c,0x00,0x85,0x80,0x21, ++0xa0,0xd0,0x00,0x12,0x00,0x09,0x10,0x23,0x30,0x42,0x00,0x03,0x8f,0xa8,0x00,0x88, ++0x00,0x62,0x10,0x23,0xa4,0xc2,0x00,0x1a,0x85,0x03,0x00,0x0c,0x00,0x00,0x00,0x00, ++0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x04, ++0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x83,0x00,0x04, ++0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10,0x14,0x60,0xff,0x74,0x02,0x00,0x10,0x21, ++0x8f,0xa3,0x00,0x54,0x8f,0xa4,0x00,0x18,0x8f,0xa5,0x00,0x24,0x00,0x64,0x10,0x21, ++0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x18,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x00, ++0x10,0xa0,0x00,0x03,0x00,0x00,0x30,0x21,0x08,0x00,0x1d,0x33,0x02,0x00,0x10,0x21, ++0x93,0x82,0x80,0x10,0x00,0x00,0x28,0x21,0x00,0x00,0x38,0x21,0x0c,0x00,0x21,0x9a, ++0xaf,0xa2,0x00,0x10,0x08,0x00,0x1d,0x33,0x02,0x00,0x10,0x21,0x30,0x63,0xff,0xff, ++0x08,0x00,0x1d,0x85,0xaf,0xa3,0x00,0x2c,0x8f,0xa8,0x00,0x44,0x08,0x00,0x1d,0xa7, ++0x31,0x09,0x00,0x03,0x08,0x00,0x1d,0x60,0xaf,0xa3,0x00,0x50,0x8f,0xa6,0x00,0x44, ++0xaf,0xa0,0x00,0x50,0x08,0x00,0x1d,0xa7,0x30,0xc9,0x00,0x03,0x8f,0xa5,0x00,0x48, ++0x8f,0xa6,0x00,0x4c,0x8f,0xa4,0x00,0x1c,0x03,0xc0,0x38,0x21,0x0c,0x00,0x1b,0xd8, ++0xaf,0xb7,0x00,0x10,0x08,0x00,0x1d,0x10,0x00,0x00,0x00,0x00,0x00,0x05,0x28,0x80, ++0x27,0x82,0x90,0x00,0x00,0xa2,0x28,0x21,0x00,0x00,0x20,0x21,0x0c,0x00,0x01,0x49, ++0x00,0x00,0x00,0x00,0x08,0x00,0x1d,0x09,0x26,0xe2,0x00,0x01,0x00,0x02,0x80,0x80, ++0x27,0x83,0x90,0x10,0x8f,0xa4,0x00,0x1c,0x02,0x03,0x18,0x21,0x26,0x31,0x00,0x01, ++0x02,0x40,0x28,0x21,0x0c,0x00,0x1e,0xea,0xa0,0x71,0x00,0x05,0x14,0x40,0xff,0x13, ++0x00,0x00,0x00,0x00,0x16,0xe0,0x00,0x4d,0x03,0xc0,0x38,0x21,0x8f,0xa4,0x00,0x24, ++0x8f,0xa5,0x00,0x20,0x24,0x02,0x00,0x01,0x24,0x84,0x00,0x01,0xaf,0xb2,0x00,0x48, ++0xaf,0xb6,0x00,0x4c,0x02,0xc0,0xf0,0x21,0x10,0xa2,0x00,0x41,0xaf,0xa4,0x00,0x24, ++0x27,0x82,0x90,0x00,0x02,0x02,0x10,0x21,0x94,0x42,0x00,0x06,0x8f,0xa4,0x00,0x30, ++0xaf,0xa0,0x00,0x20,0xaf,0xa2,0x00,0x44,0x30,0x49,0x00,0x03,0x8f,0xa8,0x00,0x44, ++0x00,0x09,0x10,0x23,0x30,0x42,0x00,0x03,0x01,0x02,0x10,0x21,0x24,0x42,0x00,0x04, ++0x30,0x42,0xff,0xff,0x00,0x44,0x18,0x2b,0x10,0x60,0x00,0x2b,0x00,0x00,0x00,0x00, ++0x8f,0xa5,0x00,0x2c,0x00,0x82,0x10,0x23,0x00,0xa4,0x18,0x21,0x30,0x63,0xff,0xff, ++0x30,0x44,0xff,0xff,0xaf,0xa3,0x00,0x2c,0x02,0x92,0x28,0x21,0x00,0x05,0x28,0x80, ++0x27,0x82,0x90,0x04,0x00,0xa2,0x10,0x21,0x8c,0x46,0x00,0x18,0x3c,0x03,0x80,0xff, ++0x3c,0x02,0x7f,0x00,0x8c,0xc8,0x00,0x04,0x00,0x04,0x25,0x40,0x34,0x63,0xff,0xff, ++0x00,0x82,0x20,0x24,0x01,0x03,0x40,0x24,0x01,0x04,0x40,0x25,0xac,0xc8,0x00,0x04, ++0x8f,0xa8,0x00,0x98,0x27,0x82,0x90,0x10,0x00,0xa2,0x10,0x21,0xa0,0x48,0x00,0x00, ++0x8c,0xc4,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x04,0x27,0xc2,0x10,0x80,0xfe,0xdb, ++0xaf,0xa4,0x00,0x3c,0x80,0x42,0x00,0x06,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x02, ++0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40, ++0x00,0xc2,0x38,0x21,0x8f,0xa2,0x00,0x40,0x00,0x00,0x00,0x00,0xa4,0xe2,0x00,0x00, ++0x08,0x00,0x1d,0x0c,0x26,0xb5,0xff,0xff,0x8f,0xa6,0x00,0x2c,0x00,0x00,0x20,0x21, ++0x00,0xc2,0x10,0x21,0x30,0x42,0xff,0xff,0x08,0x00,0x1e,0x1a,0xaf,0xa2,0x00,0x2c, ++0x8f,0xa6,0x00,0x1c,0x08,0x00,0x1e,0x04,0xa4,0xd2,0x00,0x14,0x8f,0xa5,0x00,0x48, ++0x8f,0xa6,0x00,0x4c,0x8f,0xa4,0x00,0x1c,0x0c,0x00,0x1b,0xd8,0xaf,0xb7,0x00,0x10, ++0x08,0x00,0x1d,0xfb,0x00,0x00,0xb8,0x21,0x0c,0x00,0x12,0x8b,0x00,0x00,0x28,0x21, ++0x00,0x40,0x18,0x21,0x94,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0x42,0x08,0x00, ++0xa4,0x62,0x00,0x00,0x08,0x00,0x1d,0x00,0x02,0x71,0x10,0x21,0x02,0x92,0x18,0x21, ++0x00,0x03,0x80,0x80,0x27,0x82,0x90,0x04,0x02,0x02,0x10,0x21,0x8c,0x44,0x00,0x18, ++0x00,0x00,0x00,0x00,0x8c,0x83,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10, ++0x10,0x60,0x00,0x09,0x24,0x06,0x00,0x01,0x93,0x82,0x8b,0x71,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0x01,0x10,0x40,0xfe,0xa2,0x3c,0x04,0x00,0x80,0x27,0x85,0x90,0x00, ++0x08,0x00,0x1d,0xeb,0x02,0x05,0x28,0x21,0x27,0x83,0x90,0x18,0x27,0x82,0x90,0x10, ++0x02,0x03,0x18,0x21,0x02,0x02,0x10,0x21,0x90,0x64,0x00,0x00,0x90,0x45,0x00,0x05, ++0x93,0x83,0x80,0x10,0x00,0x00,0x38,0x21,0x0c,0x00,0x21,0x9a,0xaf,0xa3,0x00,0x10, ++0x08,0x00,0x1e,0x62,0x00,0x00,0x00,0x00,0x27,0x82,0x90,0x18,0x02,0x02,0x10,0x21, ++0x94,0x43,0x00,0x02,0x8f,0xa6,0x00,0x58,0x00,0x03,0x19,0x02,0x00,0x66,0x18,0x23, ++0x30,0x63,0x0f,0xff,0x28,0x62,0x00,0x20,0x10,0x40,0x00,0x06,0x28,0x62,0x00,0x40, ++0x8f,0xa8,0x00,0x90,0x00,0x00,0x00,0x00,0x00,0x68,0x10,0x06,0x08,0x00,0x1c,0xd9, ++0x30,0x44,0x00,0x01,0x10,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0x8f,0xa4,0x00,0x94, ++0x08,0x00,0x1e,0x83,0x00,0x64,0x10,0x06,0x08,0x00,0x1c,0xd9,0x00,0x00,0x20,0x21, ++0x8f,0xa4,0x00,0x98,0x8f,0xa5,0x00,0x38,0xaf,0xa0,0x00,0x10,0x0c,0x00,0x09,0x0a, ++0xaf,0xa8,0x00,0x14,0x30,0x42,0xff,0xff,0x08,0x00,0x1c,0xa9,0xaf,0xa2,0x00,0x40, ++0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,0x27,0xbd,0xff,0xe0,0x34,0x42,0x00,0x20, ++0x24,0x63,0x7a,0x50,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x18, ++0xac,0x43,0x00,0x00,0x90,0x82,0x00,0x0a,0x00,0x80,0x80,0x21,0x14,0x40,0x00,0x45, ++0x00,0x00,0x88,0x21,0x92,0x02,0x00,0x04,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x3c, ++0x00,0x00,0x00,0x00,0x12,0x20,0x00,0x18,0x00,0x00,0x00,0x00,0x92,0x02,0x00,0x16, ++0x92,0x05,0x00,0x0a,0x30,0x42,0x00,0xfc,0x10,0xa0,0x00,0x03,0xa2,0x02,0x00,0x16, ++0x34,0x42,0x00,0x01,0xa2,0x02,0x00,0x16,0x92,0x04,0x00,0x04,0x00,0x00,0x00,0x00, ++0x30,0x83,0x00,0xff,0x10,0x60,0x00,0x05,0x00,0x00,0x00,0x00,0x92,0x02,0x00,0x16, ++0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02,0xa2,0x02,0x00,0x16,0x10,0x60,0x00,0x0a, ++0x00,0x00,0x00,0x00,0x14,0xa0,0x00,0x08,0x00,0x00,0x00,0x00,0x96,0x02,0x00,0x00, ++0xa2,0x00,0x00,0x17,0xa6,0x02,0x00,0x14,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x14,0x80,0x00,0x05,0x24,0x02,0x00,0x01, ++0x96,0x03,0x00,0x06,0xa2,0x02,0x00,0x17,0x08,0x00,0x1e,0xbe,0xa6,0x03,0x00,0x14, ++0x96,0x04,0x00,0x00,0x96,0x05,0x00,0x06,0x27,0x86,0x90,0x00,0x00,0x04,0x10,0xc0, ++0x00,0x05,0x18,0xc0,0x00,0x44,0x10,0x21,0x00,0x65,0x18,0x21,0x00,0x02,0x10,0x80, ++0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,0x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08, ++0x8c,0x44,0x00,0x08,0x0c,0x00,0x12,0x7c,0x00,0x00,0x00,0x00,0x30,0x43,0x00,0xff, ++0x10,0x60,0x00,0x04,0xa2,0x02,0x00,0x17,0x96,0x02,0x00,0x06,0x08,0x00,0x1e,0xbe, ++0xa6,0x02,0x00,0x14,0x96,0x02,0x00,0x00,0x08,0x00,0x1e,0xbe,0xa6,0x02,0x00,0x14, ++0x96,0x05,0x00,0x00,0x0c,0x00,0x1e,0xea,0x02,0x00,0x20,0x21,0x08,0x00,0x1e,0xa5, ++0x02,0x22,0x88,0x21,0x94,0x85,0x00,0x06,0x0c,0x00,0x1e,0xea,0x00,0x00,0x00,0x00, ++0x08,0x00,0x1e,0xa1,0x00,0x40,0x88,0x21,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00, ++0x34,0x63,0x00,0x20,0x24,0x42,0x7b,0xa8,0x27,0xbd,0xff,0xf0,0xac,0x62,0x00,0x00, ++0x00,0x00,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x10,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x7b,0xcc,0xac,0x62,0x00,0x00, ++0x90,0x89,0x00,0x0a,0x00,0x80,0x30,0x21,0x11,0x20,0x00,0x05,0x00,0xa0,0x50,0x21, ++0x90,0x82,0x00,0x17,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x1b,0x00,0x00,0x00,0x00, ++0x90,0xc7,0x00,0x04,0x00,0x00,0x00,0x00,0x10,0xe0,0x00,0x1b,0x00,0x00,0x00,0x00, ++0x94,0xc8,0x00,0x00,0x27,0x83,0x90,0x00,0x93,0x85,0x8b,0x70,0x00,0x08,0x10,0xc0, ++0x00,0x48,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x08, ++0x00,0xe5,0x28,0x2b,0x10,0xa0,0x00,0x06,0x01,0x44,0x18,0x23,0x8f,0x82,0x8b,0x88, ++0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x2b,0x10,0x40,0x00,0x05,0x00,0x00,0x00,0x00, ++0x24,0x03,0x00,0x10,0xa4,0xc8,0x00,0x14,0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21, ++0x11,0x20,0x00,0x05,0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x06,0x24,0x03,0x00,0x08, ++0x08,0x00,0x1f,0x16,0xa4,0xc2,0x00,0x14,0x08,0x00,0x1f,0x16,0x00,0x00,0x18,0x21, ++0x27,0xbd,0xff,0xc8,0xaf,0xb5,0x00,0x2c,0xaf,0xb4,0x00,0x28,0xaf,0xb3,0x00,0x24, ++0xaf,0xb0,0x00,0x18,0xaf,0xbf,0x00,0x30,0xaf,0xb2,0x00,0x20,0xaf,0xb1,0x00,0x1c, ++0x94,0x91,0x00,0x06,0x00,0x80,0xa0,0x21,0x3c,0x02,0x80,0x00,0x3c,0x04,0xb0,0x03, ++0x00,0x11,0xa8,0xc0,0x34,0x84,0x00,0x20,0x24,0x42,0x7c,0x80,0x02,0xb1,0x48,0x21, ++0xac,0x82,0x00,0x00,0x00,0x09,0x48,0x80,0x24,0x03,0x00,0x01,0x27,0x82,0x90,0x10, ++0xa2,0x83,0x00,0x12,0x01,0x22,0x10,0x21,0x27,0x84,0x90,0x04,0x01,0x24,0x20,0x21, ++0x80,0x48,0x00,0x06,0x8c,0x8a,0x00,0x18,0x27,0x83,0x90,0x20,0x01,0x23,0x48,0x21, ++0x8d,0x24,0x00,0x00,0x25,0x08,0x00,0x02,0x8d,0x42,0x00,0x00,0x8d,0x49,0x00,0x04, ++0x00,0x08,0x17,0xc2,0x8d,0x43,0x00,0x08,0x01,0x02,0x40,0x21,0x00,0x04,0x25,0xc2, ++0x00,0x08,0x40,0x43,0x30,0x84,0x00,0x01,0x00,0x03,0x1f,0xc2,0x00,0x08,0x40,0x40, ++0x00,0xe0,0x80,0x21,0x00,0x64,0x18,0x24,0x00,0x09,0x49,0x42,0x01,0x48,0x10,0x21, ++0x00,0xa0,0x98,0x21,0x00,0xa0,0x20,0x21,0x00,0x40,0x38,0x21,0x02,0x00,0x28,0x21, ++0x14,0x60,0x00,0x19,0x31,0x29,0x00,0x01,0x94,0x42,0x00,0x00,0x02,0xb1,0x88,0x21, ++0x02,0x00,0x28,0x21,0x00,0x11,0x88,0x80,0x27,0x90,0x90,0x00,0x02,0x30,0x80,0x21, ++0x96,0x03,0x00,0x06,0x30,0x52,0xff,0xff,0x02,0x60,0x20,0x21,0x00,0x60,0x30,0x21, ++0xa6,0x83,0x00,0x1a,0x27,0x82,0x90,0x08,0x0c,0x00,0x08,0xe3,0x02,0x22,0x88,0x21, ++0x00,0x52,0x10,0x21,0x96,0x03,0x00,0x06,0xa6,0x22,0x00,0x04,0x8f,0xbf,0x00,0x30, ++0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x00,0x60,0x10,0x21, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0xaf,0xa9,0x00,0x10,0x0c,0x00,0x09,0x0a, ++0xaf,0xa0,0x00,0x14,0x08,0x00,0x1f,0x54,0x02,0xb1,0x88,0x21,0x27,0xbd,0xff,0xc0, ++0xaf,0xbe,0x00,0x38,0xaf,0xb7,0x00,0x34,0xaf,0xb6,0x00,0x30,0xaf,0xb5,0x00,0x2c, ++0xaf,0xb3,0x00,0x24,0xaf,0xb1,0x00,0x1c,0xaf,0xbf,0x00,0x3c,0xaf,0xb4,0x00,0x28, ++0xaf,0xb2,0x00,0x20,0xaf,0xb0,0x00,0x18,0x94,0x90,0x00,0x00,0x3c,0x08,0xb0,0x03, ++0x35,0x08,0x00,0x20,0x00,0x10,0x10,0xc0,0x00,0x50,0x18,0x21,0x00,0x40,0x88,0x21, ++0x3c,0x02,0x80,0x00,0x00,0x03,0x48,0x80,0x24,0x42,0x7d,0xbc,0x00,0x80,0x98,0x21, ++0x27,0x84,0x90,0x10,0x01,0x24,0x20,0x21,0x93,0xb7,0x00,0x53,0xad,0x02,0x00,0x00, ++0x80,0x83,0x00,0x06,0x27,0x82,0x90,0x04,0x01,0x22,0x10,0x21,0x8c,0x44,0x00,0x18, ++0x24,0x63,0x00,0x02,0x00,0x03,0x17,0xc2,0x8c,0x88,0x00,0x08,0x00,0x62,0x18,0x21, ++0x00,0x03,0x18,0x43,0x00,0x03,0x18,0x40,0xaf,0xa7,0x00,0x4c,0x2c,0xa2,0x00,0x10, ++0x00,0xa0,0xa8,0x21,0x00,0x83,0x50,0x21,0x00,0x08,0x47,0xc2,0x00,0xc0,0x58,0x21, ++0x00,0x00,0xb0,0x21,0x8c,0x92,0x00,0x0c,0x14,0x40,0x00,0x13,0x00,0x00,0xf0,0x21, ++0x92,0x67,0x00,0x04,0x24,0x14,0x00,0x01,0x12,0x87,0x00,0x10,0x02,0x30,0x10,0x21, ++0x27,0x83,0x90,0x18,0x01,0x23,0x18,0x21,0x80,0x64,0x00,0x00,0x27,0x83,0xb5,0x70, ++0x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x23, ++0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x04,0x00,0x00,0x00,0x00, ++0x10,0x80,0x00,0x23,0x00,0x00,0x00,0x00,0x02,0x30,0x10,0x21,0x00,0x02,0x80,0x80, ++0x24,0x04,0x00,0x01,0x27,0x83,0x90,0x20,0xa2,0x64,0x00,0x12,0x02,0x03,0x18,0x21, ++0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x15,0xc2,0x30,0x42,0x00,0x01, ++0x01,0x02,0x10,0x24,0x14,0x40,0x00,0x0e,0x02,0xa0,0x20,0x21,0x27,0x82,0x90,0x00, ++0x02,0x02,0x10,0x21,0x94,0x43,0x00,0x06,0x00,0x00,0x00,0x00,0xa6,0x63,0x00,0x1a, ++0x94,0x42,0x00,0x06,0x7b,0xbe,0x01,0xfc,0x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c, ++0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40, ++0x8f,0xa5,0x00,0x4c,0x01,0x60,0x30,0x21,0x01,0x40,0x38,0x21,0xaf,0xa0,0x00,0x10, ++0x0c,0x00,0x09,0x0a,0xaf,0xa0,0x00,0x14,0x08,0x00,0x1f,0xbb,0x00,0x00,0x00,0x00, ++0x27,0x83,0x90,0x20,0x01,0x23,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x02,0x15,0xc2,0x30,0x42,0x00,0x01,0x01,0x02,0x10,0x24,0x14,0x40,0x00,0xaf, ++0x00,0xa0,0x20,0x21,0x32,0x4f,0x00,0x03,0x00,0x12,0x10,0x82,0x25,0xe3,0x00,0x0d, ++0x30,0x45,0x00,0x07,0x00,0x74,0x78,0x04,0x10,0xa0,0x00,0x0e,0x00,0x00,0x90,0x21, ++0x27,0x82,0x80,0x1c,0x00,0x15,0x18,0x40,0x00,0x62,0x18,0x21,0x94,0x64,0x00,0x00, ++0x24,0xa2,0x00,0x06,0x00,0x54,0x10,0x04,0x00,0x44,0x00,0x1a,0x14,0x80,0x00,0x02, ++0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0d,0x00,0x00,0x10,0x12,0x24,0x42,0x00,0x20, ++0x30,0x52,0xff,0xfc,0x02,0x30,0x10,0x21,0x27,0x83,0x90,0x10,0x00,0x02,0x10,0x80, ++0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x03,0x00,0x00,0x00,0x00,0x30,0x83,0x00,0xff, ++0x2c,0x62,0x00,0x0c,0x14,0x40,0x00,0x04,0x2c,0x62,0x00,0x19,0x30,0x82,0x00,0x0f, ++0x24,0x43,0x00,0x0c,0x2c,0x62,0x00,0x19,0x10,0x40,0x00,0x19,0x24,0x0e,0x00,0x20, ++0x24,0x62,0xff,0xe9,0x2c,0x42,0x00,0x02,0x14,0x40,0x00,0x15,0x24,0x0e,0x00,0x10, ++0x24,0x62,0xff,0xeb,0x2c,0x42,0x00,0x02,0x14,0x40,0x00,0x11,0x24,0x0e,0x00,0x08, ++0x24,0x02,0x00,0x14,0x10,0x62,0x00,0x0e,0x24,0x0e,0x00,0x02,0x24,0x62,0xff,0xef, ++0x2c,0x42,0x00,0x03,0x14,0x40,0x00,0x0a,0x24,0x0e,0x00,0x10,0x24,0x62,0xff,0xf1, ++0x2c,0x42,0x00,0x02,0x14,0x40,0x00,0x06,0x24,0x0e,0x00,0x08,0x24,0x62,0xff,0xf3, ++0x2c,0x42,0x00,0x02,0x24,0x0e,0x00,0x04,0x24,0x03,0x00,0x02,0x00,0x62,0x70,0x0a, ++0x30,0xe2,0x00,0xff,0x00,0x00,0x48,0x21,0x00,0x00,0x68,0x21,0x10,0x40,0x00,0x6d, ++0x00,0x00,0x58,0x21,0x3c,0x14,0x80,0xff,0x27,0x99,0x90,0x00,0x01,0xf2,0xc0,0x23, ++0x36,0x94,0xff,0xff,0x01,0xc9,0x10,0x2a,0x14,0x40,0x00,0x64,0x24,0x03,0x00,0x04, ++0x00,0x10,0x28,0xc0,0x00,0xb0,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x59,0x10,0x21, ++0x94,0x56,0x00,0x06,0x00,0x00,0x00,0x00,0x32,0xcc,0x00,0x03,0x00,0x6c,0x10,0x23, ++0x30,0x42,0x00,0x03,0x02,0xc2,0x10,0x21,0x24,0x42,0x00,0x04,0x30,0x51,0xff,0xff, ++0x02,0x32,0x18,0x2b,0x10,0x60,0x00,0x4d,0x01,0xf1,0x10,0x23,0x02,0x51,0x10,0x23, ++0x01,0x78,0x18,0x2b,0x10,0x60,0x00,0x34,0x30,0x44,0xff,0xff,0x29,0x22,0x00,0x40, ++0x10,0x40,0x00,0x31,0x01,0x72,0x18,0x21,0x25,0x22,0x00,0x01,0x00,0x02,0x16,0x00, ++0x00,0x02,0x4e,0x03,0x00,0xb0,0x10,0x21,0x00,0x02,0x30,0x80,0x27,0x82,0x90,0x04, ++0x30,0x6b,0xff,0xff,0x00,0xc2,0x18,0x21,0x8c,0x67,0x00,0x18,0x00,0x04,0x25,0x40, ++0x3c,0x03,0x7f,0x00,0x8c,0xe2,0x00,0x04,0x00,0x83,0x20,0x24,0x27,0x83,0x90,0x10, ++0x00,0x54,0x10,0x24,0x00,0xc3,0x28,0x21,0x00,0x44,0x10,0x25,0xac,0xe2,0x00,0x04, ++0x16,0xe0,0x00,0x02,0xa0,0xb5,0x00,0x00,0xa0,0xb5,0x00,0x03,0x27,0x84,0x90,0x20, ++0x00,0xc4,0x18,0x21,0x8c,0x62,0x00,0x00,0x8c,0xe8,0x00,0x08,0x00,0x02,0x15,0xc2, ++0x00,0x08,0x47,0xc2,0x30,0x42,0x00,0x01,0x01,0x02,0x10,0x24,0x10,0x40,0x00,0x0a, ++0x00,0x00,0x00,0x00,0x80,0xa2,0x00,0x06,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x02, ++0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40, ++0x00,0xe2,0x50,0x21,0xa5,0x5e,0x00,0x00,0x92,0x62,0x00,0x04,0x25,0xad,0x00,0x01, ++0x27,0x84,0x90,0x00,0x00,0xc4,0x18,0x21,0x01,0xa2,0x10,0x2a,0x94,0x70,0x00,0x02, ++0x14,0x40,0xff,0xb8,0x00,0x00,0x00,0x00,0x96,0x63,0x00,0x14,0x00,0x0c,0x10,0x23, ++0xa2,0x69,0x00,0x12,0x30,0x42,0x00,0x03,0x01,0x62,0x10,0x23,0x00,0x03,0x80,0xc0, ++0x8f,0xa5,0x00,0x4c,0x30,0x4b,0xff,0xff,0x02,0x03,0x80,0x21,0x27,0x82,0x90,0x08, ++0x00,0x10,0x80,0x80,0xa6,0x6b,0x00,0x1a,0x02,0xa0,0x20,0x21,0x01,0x60,0x30,0x21, ++0x01,0x60,0x88,0x21,0x0c,0x00,0x08,0xe3,0x02,0x02,0x80,0x21,0x00,0x5e,0x10,0x21, ++0xa6,0x02,0x00,0x04,0x08,0x00,0x1f,0xc1,0x02,0x20,0x10,0x21,0x01,0x62,0x10,0x2b, ++0x10,0x40,0xff,0xe9,0x00,0x00,0x20,0x21,0x29,0x22,0x00,0x40,0x10,0x40,0xff,0xe6, ++0x01,0x71,0x18,0x21,0x08,0x00,0x20,0x37,0x25,0x22,0x00,0x01,0x08,0x00,0x20,0x66, ++0x32,0xcc,0x00,0x03,0x08,0x00,0x20,0x66,0x00,0x00,0x60,0x21,0x8f,0xa5,0x00,0x4c, ++0x01,0x40,0x38,0x21,0xaf,0xa0,0x00,0x10,0x0c,0x00,0x09,0x0a,0xaf,0xb4,0x00,0x14, ++0x92,0x67,0x00,0x04,0x08,0x00,0x1f,0xd9,0x30,0x5e,0xff,0xff,0x30,0x84,0xff,0xff, ++0x00,0x04,0x30,0xc0,0x00,0xc4,0x20,0x21,0x00,0x04,0x20,0x80,0x27,0x82,0x90,0x00, ++0x3c,0x03,0xb0,0x08,0x30,0xa5,0xff,0xff,0x00,0x82,0x20,0x21,0x00,0xc3,0x30,0x21, ++0xac,0xc5,0x00,0x00,0x03,0xe0,0x00,0x08,0xa4,0x85,0x00,0x00,0x30,0x84,0xff,0xff, ++0x00,0x04,0x30,0xc0,0x00,0xc4,0x30,0x21,0x27,0x88,0x90,0x00,0x00,0x06,0x30,0x80, ++0x00,0xc8,0x30,0x21,0x94,0xc3,0x00,0x04,0x3c,0x02,0xb0,0x08,0x3c,0x07,0xb0,0x03, ++0x00,0x03,0x20,0xc0,0x00,0x83,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x82,0x20,0x21, ++0x3c,0x02,0x80,0x01,0x30,0xa5,0xff,0xff,0x00,0x68,0x18,0x21,0x34,0xe7,0x00,0x20, ++0x24,0x42,0x82,0x6c,0xac,0xe2,0x00,0x00,0xa4,0xc5,0x00,0x02,0xa4,0x65,0x00,0x00, ++0x03,0xe0,0x00,0x08,0xac,0x85,0x00,0x00,0x30,0x84,0xff,0xff,0x00,0x04,0x10,0xc0, ++0x00,0x44,0x10,0x21,0x27,0x89,0x90,0x00,0x00,0x02,0x10,0x80,0x00,0x49,0x10,0x21, ++0x97,0x83,0x8f,0xf0,0x94,0x4a,0x00,0x04,0x3c,0x02,0xb0,0x08,0x00,0x03,0x38,0xc0, ++0x00,0x0a,0x40,0xc0,0x00,0xe3,0x18,0x21,0x01,0x0a,0x28,0x21,0x00,0xe2,0x38,0x21, ++0x01,0x02,0x40,0x21,0x00,0x03,0x18,0x80,0x00,0x05,0x28,0x80,0x3c,0x06,0xb0,0x03, ++0x3c,0x02,0x80,0x01,0x00,0xa9,0x28,0x21,0x00,0x69,0x18,0x21,0x34,0xc6,0x00,0x20, ++0x34,0x09,0xff,0xff,0x24,0x42,0x82,0xc8,0xac,0xc2,0x00,0x00,0xa4,0x64,0x00,0x00, ++0xac,0xe4,0x00,0x00,0xa4,0xa9,0x00,0x00,0xad,0x09,0x00,0x00,0xa7,0x8a,0x8f,0xf0, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01, ++0x34,0x63,0x00,0x20,0x24,0x42,0x83,0x48,0x3c,0x04,0xb0,0x03,0xac,0x62,0x00,0x00, ++0x34,0x84,0x01,0x10,0x8c,0x82,0x00,0x00,0x97,0x83,0x81,0x60,0x30,0x42,0xff,0xff, ++0x10,0x62,0x00,0x16,0x24,0x0a,0x00,0x01,0xa7,0x82,0x81,0x60,0xaf,0x80,0xb4,0x50, ++0x00,0x40,0x28,0x21,0x24,0x06,0x00,0x01,0x27,0x84,0xb4,0x54,0x25,0x43,0xff,0xff, ++0x00,0x66,0x10,0x04,0x00,0xa2,0x10,0x24,0x14,0x40,0x00,0x07,0x00,0x00,0x00,0x00, ++0x8c,0x83,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x66,0x10,0x04,0x00,0xa2,0x10,0x24, ++0x38,0x42,0x00,0x00,0x01,0x42,0x18,0x0a,0x25,0x4a,0x00,0x01,0x2d,0x42,0x00,0x14, ++0xac,0x83,0x00,0x00,0x14,0x40,0xff,0xf1,0x24,0x84,0x00,0x04,0x3c,0x0b,0xb0,0x03, ++0x00,0x00,0x50,0x21,0x3c,0x0c,0x80,0x00,0x27,0x89,0xb4,0xa0,0x35,0x6b,0x01,0x20, ++0x8d,0x68,0x00,0x00,0x8d,0x23,0x00,0x04,0x01,0x0c,0x10,0x24,0x00,0x02,0x17,0xc2, ++0x11,0x03,0x00,0x37,0xa1,0x22,0x00,0xdc,0xa1,0x20,0x00,0xd5,0xa1,0x20,0x00,0xd6, ++0x01,0x20,0x30,0x21,0x00,0x00,0x38,0x21,0x00,0x00,0x28,0x21,0x01,0x20,0x20,0x21, ++0x00,0xa8,0x10,0x06,0x30,0x42,0x00,0x01,0x10,0xe0,0x00,0x10,0xa0,0x82,0x00,0x0a, ++0x90,0x82,0x00,0x07,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x31,0x24,0xa2,0xff,0xff, ++0xa0,0x82,0x00,0x08,0x90,0x82,0x00,0x0a,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x09, ++0x00,0x00,0x00,0x00,0x90,0x83,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0x40, ++0x00,0x43,0x10,0x21,0x00,0x46,0x10,0x21,0xa0,0x45,0x00,0x09,0x90,0x82,0x00,0x0a, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x07,0x00,0x00,0x00,0x00,0x14,0xe0,0x00,0x04, ++0x00,0x00,0x00,0x00,0xa0,0xc5,0x00,0xd5,0x24,0x07,0x00,0x01,0xa0,0x85,0x00,0x08, ++0xa0,0xc5,0x00,0xd6,0x24,0xa5,0x00,0x01,0x2c,0xa2,0x00,0x1c,0x14,0x40,0xff,0xe0, ++0x24,0x84,0x00,0x03,0x90,0xc4,0x00,0xd5,0x00,0x00,0x28,0x21,0x00,0xa4,0x10,0x2b, ++0x10,0x40,0x00,0x0b,0x00,0x00,0x00,0x00,0x00,0xc0,0x18,0x21,0xa0,0x64,0x00,0x08, ++0x90,0xc2,0x00,0xd5,0x24,0xa5,0x00,0x01,0xa0,0x62,0x00,0x09,0x90,0xc4,0x00,0xd5, ++0x00,0x00,0x00,0x00,0x00,0xa4,0x10,0x2b,0x14,0x40,0xff,0xf8,0x24,0x63,0x00,0x03, ++0x25,0x4a,0x00,0x01,0x2d,0x42,0x00,0x08,0xad,0x28,0x00,0x04,0x25,0x6b,0x00,0x04, ++0x14,0x40,0xff,0xbf,0x25,0x29,0x00,0xec,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x90,0x82,0x00,0x05,0x08,0x00,0x21,0x0d,0xa0,0x82,0x00,0x08,0x97,0x85,0x8b,0x7a, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x63,0x00,0x20, ++0x24,0x42,0x84,0xfc,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x62,0x00,0x00, ++0x30,0x90,0x00,0xff,0x00,0x05,0x28,0x42,0x00,0x00,0x48,0x21,0x27,0x8f,0xb4,0xa4, ++0x00,0x00,0x50,0x21,0x00,0x00,0x58,0x21,0x27,0x98,0xb5,0x84,0x27,0x99,0xb5,0x80, ++0x27,0x8e,0xb5,0x7e,0x27,0x8c,0xb4,0xa8,0x27,0x8d,0xb5,0x00,0x27,0x88,0xb5,0x78, ++0x00,0x0a,0x18,0x80,0x01,0x6f,0x10,0x21,0xac,0x40,0x00,0x00,0xac,0x45,0x00,0x58, ++0x00,0x6e,0x20,0x21,0x00,0x78,0x10,0x21,0xa1,0x00,0xff,0xfc,0xad,0x00,0x00,0x00, ++0xa1,0x00,0x00,0x04,0xa1,0x00,0x00,0x05,0xad,0x00,0xff,0xf8,0x00,0x79,0x18,0x21, ++0x24,0x06,0x00,0x01,0x24,0xc6,0xff,0xff,0xa0,0x80,0x00,0x00,0xa4,0x60,0x00,0x00, ++0xac,0x40,0x00,0x00,0x24,0x63,0x00,0x02,0x24,0x42,0x00,0x04,0x04,0xc1,0xff,0xf9, ++0x24,0x84,0x00,0x01,0x00,0x0a,0x10,0x80,0x00,0x4d,0x20,0x21,0x00,0x00,0x30,0x21, ++0x00,0x4c,0x18,0x21,0x27,0x87,0x81,0x64,0x8c,0xe2,0x00,0x00,0x24,0xe7,0x00,0x04, ++0xac,0x82,0x00,0x00,0xa0,0x66,0x00,0x00,0xa0,0x66,0x00,0x01,0x24,0xc6,0x00,0x01, ++0x28,0xc2,0x00,0x1c,0xa0,0x60,0x00,0x02,0x24,0x84,0x00,0x04,0x14,0x40,0xff,0xf6, ++0x24,0x63,0x00,0x03,0x25,0x29,0x00,0x01,0x29,0x22,0x00,0x08,0x25,0x4a,0x00,0x3b, ++0x25,0x08,0x00,0xec,0x14,0x40,0xff,0xd6,0x25,0x6b,0x00,0xec,0xa7,0x80,0x81,0x60, ++0x00,0x00,0x48,0x21,0x27,0x83,0xb4,0x50,0xac,0x69,0x00,0x00,0x25,0x29,0x00,0x01, ++0x29,0x22,0x00,0x0c,0x14,0x40,0xff,0xfc,0x24,0x63,0x00,0x04,0x0c,0x00,0x20,0xd2, ++0x00,0x00,0x00,0x00,0x2e,0x04,0x00,0x14,0x27,0x83,0xb4,0xa0,0x24,0x09,0x00,0x07, ++0x10,0x80,0x00,0x0a,0x00,0x00,0x00,0x00,0x90,0x62,0x00,0xd5,0x25,0x29,0xff,0xff, ++0xa0,0x62,0x00,0x00,0x05,0x21,0xff,0xfa,0x24,0x63,0x00,0xec,0x8f,0xbf,0x00,0x14, ++0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x90,0x62,0x00,0xd6, ++0x08,0x00,0x21,0x90,0x25,0x29,0xff,0xff,0x30,0x84,0x00,0xff,0x00,0x04,0x11,0x00, ++0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80, ++0x27,0x83,0xb4,0xa0,0x00,0x43,0x60,0x21,0x3c,0x04,0xb0,0x03,0x3c,0x02,0x80,0x01, ++0x34,0x84,0x00,0x20,0x24,0x42,0x86,0x68,0x30,0xc6,0x00,0xff,0x93,0xaa,0x00,0x13, ++0x30,0xa5,0x00,0xff,0x30,0xe7,0x00,0xff,0xac,0x82,0x00,0x00,0x10,0xc0,0x00,0xe8, ++0x25,0x8f,0x00,0xd0,0x91,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x42,0xff,0xfc, ++0x2c,0x43,0x00,0x18,0x10,0x60,0x00,0xc7,0x3c,0x03,0x80,0x01,0x00,0x02,0x10,0x80, ++0x24,0x63,0x02,0x90,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x30,0x14,0x40,0x00,0x1c, ++0x00,0x00,0x00,0x00,0x10,0xa0,0x00,0x17,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0x00,0x11,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x0c, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x06,0x00,0x00,0x00,0x00, ++0x8d,0x82,0x00,0xd0,0x00,0x00,0x00,0x00,0x24,0x42,0xff,0xe0,0x03,0xe0,0x00,0x08, ++0xad,0x82,0x00,0xd0,0x8d,0x82,0x00,0xd0,0x08,0x00,0x21,0xcb,0x24,0x42,0xff,0xe8, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x21,0xcb, ++0x24,0x42,0x00,0x01,0x8d,0x82,0x00,0xd0,0x08,0x00,0x21,0xcb,0x24,0x42,0x00,0x02, ++0x10,0xa0,0xff,0xf9,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x0a, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xe9,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0xe6,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0, ++0x08,0x00,0x21,0xcb,0x24,0x42,0xff,0xd0,0x8d,0x82,0x00,0xd0,0x08,0x00,0x21,0xcb, ++0x24,0x42,0xff,0xfc,0x10,0xa0,0xff,0xeb,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0xff,0xe5,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xe0, ++0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xdb,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0, ++0x08,0x00,0x21,0xcb,0x24,0x42,0xff,0xf8,0x2d,0x42,0x00,0x19,0x14,0x40,0xff,0xc5, ++0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xdb,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0xff,0xd5,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xd0, ++0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0xf1,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0, ++0x08,0x00,0x21,0xcb,0x24,0x42,0xff,0xf0,0x2d,0x42,0x00,0x1b,0x10,0x40,0xff,0xf1, ++0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xcb,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0xff,0xc5,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x14,0xa2,0xff,0xb5, ++0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x21,0xcb,0x24,0x42,0xff,0xf4, ++0x2d,0x42,0x00,0x1e,0x10,0x40,0xff,0xe3,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xbd, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xb5,0x24,0x02,0x00,0x02, ++0x10,0xa2,0xff,0xd6,0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xc6,0x24,0x02,0x00,0x03, ++0x2d,0x42,0x00,0x23,0x10,0x40,0xff,0xd7,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xae, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xa9,0x24,0x02,0x00,0x02, ++0x14,0xa2,0xff,0xb7,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0x03,0x00,0x00,0x00,0x00, ++0x2d,0x42,0x00,0x25,0x10,0x40,0xff,0xcb,0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xd8, ++0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x16,0x14,0x40,0x00,0x0e,0x00,0x00,0x00,0x00, ++0x10,0xa0,0xff,0xa0,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x9a, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x95,0x24,0x02,0x00,0x03, ++0x14,0xa2,0xff,0xb6,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x21,0xcb, ++0x24,0x42,0xff,0xfa,0x10,0xa0,0xff,0x93,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0xff,0x8d,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x88, ++0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xf3,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x17, ++0x14,0x40,0xff,0xac,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0x34,0x00,0x00,0x00,0x00, ++0x2d,0x42,0x00,0x19,0x10,0x40,0xff,0xe2,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0x81, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x7b,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x76,0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0x97, ++0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xc8,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0x51, ++0x2d,0x42,0x00,0x1b,0x2d,0x42,0x00,0x1e,0x10,0x40,0xff,0xde,0x00,0x00,0x00,0x00, ++0x10,0xa0,0xff,0x70,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x6a, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x65,0x24,0x02,0x00,0x03, ++0x10,0xa2,0xff,0x96,0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xc8,0x00,0x00,0x00,0x00, ++0x2d,0x42,0x00,0x23,0x14,0x40,0xff,0xf2,0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xf9, ++0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xf7,0x2d,0x42,0x00,0x25,0x08,0x00,0x22,0x2d, ++0x2d,0x42,0x00,0x27,0x10,0xa0,0xff,0x5b,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0xff,0x55,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x50, ++0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0x71,0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xe6, ++0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x27,0x14,0x40,0xff,0xad,0x00,0x00,0x00,0x00, ++0x08,0x00,0x22,0x79,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x2a,0x14,0x40,0xff,0xd8, ++0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xe9,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x2c, ++0x14,0x40,0xff,0x78,0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xbd,0x00,0x00,0x00,0x00, ++0x91,0x86,0x00,0x00,0x91,0x83,0x00,0xd4,0x25,0x8d,0x00,0x5c,0x30,0xc4,0x00,0xff, ++0x00,0x04,0x10,0x40,0x00,0x44,0x10,0x21,0x00,0x04,0x48,0x80,0x01,0x82,0x58,0x21, ++0x01,0x89,0x40,0x21,0x25,0x78,0x00,0x08,0x10,0x60,0x00,0x37,0x25,0x0e,0x00,0x60, ++0x2c,0xa2,0x00,0x03,0x14,0x40,0x00,0x25,0x00,0x00,0x00,0x00,0x91,0x82,0x00,0xdd, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x1e,0x00,0x00,0x00,0x00,0x27,0x87,0x81,0x64, ++0x01,0x27,0x10,0x21,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0xad,0x03,0x00,0x60, ++0x91,0x62,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x40,0x30,0x21,0xa1,0x82,0x00,0x00, ++0x30,0xc2,0x00,0xff,0x00,0x02,0x10,0x80,0x00,0x47,0x10,0x21,0x8c,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x03,0x18,0x42,0xad,0xa3,0x00,0x00,0x91,0x84,0x00,0x00, ++0x8d,0xc5,0x00,0x00,0x00,0x04,0x20,0x80,0x00,0x87,0x10,0x21,0x8c,0x43,0x00,0x00, ++0x00,0x05,0x28,0x40,0x00,0x8c,0x20,0x21,0x00,0x03,0x18,0x80,0x00,0xa3,0x10,0x2b, ++0x00,0x62,0x28,0x0a,0xac,0x85,0x00,0x60,0x03,0xe0,0x00,0x08,0xa1,0x80,0x00,0xd4, ++0x27,0x87,0x81,0x64,0x08,0x00,0x22,0xb0,0xa1,0x80,0x00,0xdd,0x27,0x82,0x81,0xd4, ++0x8d,0x83,0x00,0xd8,0x00,0x82,0x10,0x21,0x90,0x44,0x00,0x00,0x24,0x63,0x00,0x01, ++0x00,0x64,0x20,0x2b,0x14,0x80,0xff,0x02,0xad,0x83,0x00,0xd8,0x8d,0x02,0x00,0x60, ++0xa1,0x80,0x00,0xd4,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43, ++0x03,0xe0,0x00,0x08,0xad,0x82,0x00,0x5c,0x10,0xe0,0x00,0x1d,0x24,0x83,0xff,0xfc, ++0x2c,0x62,0x00,0x18,0x10,0x40,0x01,0x10,0x00,0x03,0x10,0x80,0x3c,0x03,0x80,0x01, ++0x24,0x63,0x02,0xf0,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x30,0x14,0x40,0x00,0x65, ++0x00,0x00,0x00,0x00,0x10,0xa0,0x00,0x60,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0x00,0x5a,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x08, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x51,0x00,0x00,0x00,0x00, ++0x8d,0x82,0x00,0xd0,0x00,0x00,0x00,0x00,0x24,0x42,0xff,0xe0,0xad,0x82,0x00,0xd0, ++0x8d,0xe3,0x00,0x00,0x8d,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21, ++0xad,0xa2,0x00,0x00,0xad,0xe0,0x00,0x00,0x8d,0xa3,0x00,0x00,0x8d,0xc4,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x83,0x10,0x2a,0x10,0x40,0x00,0x22,0x00,0x00,0x00,0x00, ++0x93,0x05,0x00,0x01,0x91,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x45,0x00,0x05, ++0x24,0x02,0x00,0x01,0xa1,0x85,0x00,0x00,0xa1,0x82,0x00,0xd4,0x03,0xe0,0x00,0x08, ++0xad,0x80,0x00,0xd8,0x91,0x82,0x00,0xdd,0x24,0x03,0x00,0x01,0x10,0x43,0x00,0x05, ++0x00,0x00,0x00,0x00,0xa1,0x83,0x00,0xd4,0xad,0x80,0x00,0xd8,0x03,0xe0,0x00,0x08, ++0xa1,0x83,0x00,0xdd,0x00,0x04,0x17,0xc2,0x00,0x82,0x10,0x21,0x00,0x02,0x10,0x43, ++0xad,0xa2,0x00,0x00,0x91,0x83,0x00,0x00,0x27,0x82,0x81,0x64,0x8d,0xc5,0x00,0x00, ++0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,0x8c,0x64,0x00,0x00,0x00,0x05,0x28,0x40, ++0x00,0x04,0x18,0x80,0x00,0xa3,0x10,0x2b,0x00,0x62,0x28,0x0a,0x08,0x00,0x22,0xc2, ++0xad,0xc5,0x00,0x00,0x97,0x82,0x8b,0x7c,0x00,0x00,0x00,0x00,0x00,0x62,0x10,0x2a, ++0x10,0x40,0xfe,0xab,0x00,0x00,0x00,0x00,0x91,0x82,0x00,0xdd,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x15,0x00,0x00,0x00,0x00,0x91,0x83,0x00,0x00,0x27,0x82,0x81,0x64, ++0x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x6c,0x18,0x21, ++0xac,0x64,0x00,0x60,0x93,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x10,0x80, ++0x01,0x82,0x10,0x21,0x24,0x4e,0x00,0x60,0xa1,0x85,0x00,0x00,0x8d,0xc2,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43, ++0x03,0xe0,0x00,0x08,0xad,0xa2,0x00,0x00,0x08,0x00,0x23,0x37,0xa1,0x80,0x00,0xdd, ++0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0xf3,0x24,0x42,0xff,0xe8,0x8d,0x82,0x00,0xd0, ++0x08,0x00,0x22,0xf3,0x24,0x42,0x00,0x01,0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0xf3, ++0x24,0x42,0x00,0x02,0x10,0xa0,0xff,0xf9,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0x00,0x0a,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xa0, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0x9d,0x00,0x00,0x00,0x00, ++0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0xf3,0x24,0x42,0xff,0xd0,0x8d,0x82,0x00,0xd0, ++0x08,0x00,0x22,0xf3,0x24,0x42,0xff,0xfc,0x10,0xa0,0xff,0xeb,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xe5,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02, ++0x10,0xa2,0xff,0x93,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xdd,0x00,0x00,0x00,0x00, ++0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0xf3,0x24,0x42,0xff,0xf8,0x2d,0x42,0x00,0x19, ++0x14,0x40,0xff,0x7c,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xdb,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xd5,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02, ++0x10,0xa2,0xff,0x83,0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0xf1,0x00,0x00,0x00,0x00, ++0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0xf3,0x24,0x42,0xff,0xf0,0x2d,0x42,0x00,0x1b, ++0x10,0x40,0xff,0xf1,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xcb,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xc5,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02, ++0x14,0xa2,0xff,0x6c,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0xf3, ++0x24,0x42,0xff,0xf4,0x2d,0x42,0x00,0x1e,0x10,0x40,0xff,0xe3,0x00,0x00,0x00,0x00, ++0x10,0xa0,0xff,0xbd,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x68, ++0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xd6,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0xee, ++0x24,0x02,0x00,0x03,0x2d,0x42,0x00,0x23,0x10,0x40,0xff,0xd7,0x00,0x00,0x00,0x00, ++0x10,0xa0,0xff,0xae,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x5c, ++0x24,0x02,0x00,0x02,0x14,0xa2,0xff,0xb7,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0x74, ++0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x25,0x10,0x40,0xff,0xcb,0x00,0x00,0x00,0x00, ++0x08,0x00,0x23,0x49,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x16,0x14,0x40,0x00,0x0e, ++0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xa0,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0xff,0x9a,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x48, ++0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xb6,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0, ++0x08,0x00,0x22,0xf3,0x24,0x42,0xff,0xfa,0x10,0xa0,0xff,0x93,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x8d,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02, ++0x10,0xa2,0xff,0x3b,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0x64,0x00,0x00,0x00,0x00, ++0x2d,0x42,0x00,0x17,0x14,0x40,0xff,0xac,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0xa5, ++0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x19,0x10,0x40,0xff,0xe2,0x00,0x00,0x00,0x00, ++0x10,0xa0,0xff,0x81,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x7b, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x29,0x24,0x02,0x00,0x03, ++0x10,0xa2,0xff,0x97,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0xf0,0x00,0x00,0x00,0x00, ++0x08,0x00,0x23,0xc2,0x2d,0x42,0x00,0x1b,0x2d,0x42,0x00,0x1e,0x10,0x40,0xff,0xde, ++0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0x70,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0xff,0x6a,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x18, ++0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0x96,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0xf0, ++0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x23,0x14,0x40,0xff,0xf2,0x00,0x00,0x00,0x00, ++0x08,0x00,0x23,0x6a,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0x68,0x2d,0x42,0x00,0x25, ++0x08,0x00,0x23,0x9e,0x2d,0x42,0x00,0x27,0x10,0xa0,0xff,0x5b,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x55,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02, ++0x10,0xa2,0xff,0x03,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0x71,0x00,0x00,0x00,0x00, ++0x08,0x00,0x23,0x57,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x27,0x14,0x40,0xff,0xad, ++0x00,0x00,0x00,0x00,0x08,0x00,0x23,0xea,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x2a, ++0x14,0x40,0xff,0xd8,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0x5a,0x00,0x00,0x00,0x00, ++0x2d,0x42,0x00,0x2c,0x14,0x40,0xff,0x78,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0xe5, ++0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe8,0x3c,0x02,0xb0,0x03,0xaf,0xbf,0x00,0x14, ++0xaf,0xb0,0x00,0x10,0x34,0x42,0x01,0x18,0x3c,0x03,0xb0,0x03,0x8c,0x50,0x00,0x00, ++0x34,0x63,0x01,0x2c,0x90,0x62,0x00,0x00,0x32,0x05,0x00,0x01,0xa3,0x82,0x80,0x10, ++0x14,0xa0,0x00,0x14,0x30,0x44,0x00,0xff,0x32,0x02,0x01,0x00,0x14,0x40,0x00,0x09, ++0x00,0x00,0x00,0x00,0x32,0x02,0x08,0x00,0x10,0x40,0x00,0x02,0x24,0x02,0x00,0x01, ++0xa3,0x82,0xbc,0x18,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x18,0x0c,0x00,0x05,0x37,0x00,0x00,0x00,0x00,0x26,0x02,0xff,0x00, ++0xa3,0x80,0xbc,0x18,0x3c,0x01,0xb0,0x03,0xac,0x22,0x01,0x18,0x08,0x00,0x24,0x16, ++0x32,0x02,0x08,0x00,0x0c,0x00,0x21,0x3f,0x00,0x00,0x00,0x00,0x26,0x02,0xff,0xff, ++0x3c,0x01,0xb0,0x03,0xac,0x22,0x01,0x18,0x08,0x00,0x24,0x13,0x32,0x02,0x01,0x00, ++0x27,0xbd,0xff,0xe0,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xd0,0xaf,0xbf,0x00,0x18, ++0x8c,0x43,0x00,0x00,0x3c,0x02,0x00,0x40,0x24,0x07,0x0f,0xff,0x00,0x03,0x33,0x02, ++0x00,0x03,0x2d,0x02,0x00,0x03,0x43,0x02,0x30,0x69,0x0f,0xff,0x00,0x62,0x18,0x24, ++0x30,0xa5,0x00,0x03,0x30,0xc6,0x00,0xff,0x10,0x60,0x00,0x08,0x31,0x08,0x00,0xff, ++0x01,0x00,0x30,0x21,0x0c,0x00,0x24,0xdf,0xaf,0xa9,0x00,0x10,0x8f,0xbf,0x00,0x18, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x0c,0x00,0x25,0x31, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0xd4,0x08,0x00,0x24,0x3f, ++0xac,0x62,0x00,0x00,0x27,0xbd,0xff,0xc0,0x3c,0x02,0xb0,0x03,0xaf,0xbe,0x00,0x38, ++0xaf,0xb5,0x00,0x2c,0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,0xaf,0xbf,0x00,0x3c, ++0xaf,0xb7,0x00,0x34,0xaf,0xb6,0x00,0x30,0xaf,0xb4,0x00,0x28,0xaf,0xb3,0x00,0x24, ++0xaf,0xb2,0x00,0x20,0x34,0x42,0x00,0x3f,0x90,0x43,0x00,0x00,0x00,0x80,0x80,0x21, ++0x00,0x00,0xf0,0x21,0x00,0x00,0x88,0x21,0x10,0x60,0x00,0x76,0x00,0x00,0xa8,0x21, ++0x3c,0x01,0xb0,0x03,0xa0,0x20,0x00,0x3f,0x00,0x10,0x12,0x02,0x24,0x04,0x06,0x14, ++0x0c,0x00,0x06,0xd1,0x30,0x54,0x00,0x0f,0x24,0x04,0x06,0x14,0x0c,0x00,0x06,0xd1, ++0xaf,0xa2,0x00,0x10,0x3c,0x03,0x00,0xff,0x34,0x63,0xff,0xff,0x32,0x10,0x00,0x7f, ++0x00,0x43,0x10,0x24,0x00,0x10,0x86,0x00,0x02,0x02,0x80,0x25,0x02,0x00,0x28,0x21, ++0x24,0x04,0x06,0x14,0x3c,0x13,0xbf,0xff,0x0c,0x00,0x06,0xbf,0x3c,0x16,0xb0,0x03, ++0x00,0x00,0x90,0x21,0x3c,0x17,0x40,0x00,0x36,0x73,0xff,0xff,0x36,0xd6,0x00,0x3e, ++0x0c,0x00,0x06,0xd1,0x24,0x04,0x04,0x00,0x00,0x57,0x10,0x25,0x00,0x40,0x28,0x21, ++0x0c,0x00,0x06,0xbf,0x24,0x04,0x04,0x00,0x00,0x00,0x80,0x21,0x0c,0x00,0x25,0xf9, ++0x00,0x00,0x00,0x00,0x26,0x03,0x00,0x01,0x10,0x40,0x00,0x46,0x30,0x70,0x00,0xff, ++0x12,0x00,0xff,0xfa,0x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xd1,0x24,0x04,0x04,0x00, ++0x00,0x53,0x10,0x24,0x00,0x40,0x28,0x21,0x0c,0x00,0x06,0xbf,0x24,0x04,0x04,0x00, ++0x24,0x02,0x00,0x01,0x12,0x82,0x00,0x37,0x00,0x00,0x00,0x00,0x12,0x80,0x00,0x35, ++0x00,0x00,0x00,0x00,0x32,0x31,0x00,0x7f,0x12,0x20,0x00,0x04,0x24,0x03,0x00,0x04, ++0x27,0xc2,0x00,0x01,0x30,0x5e,0x00,0xff,0x02,0xb1,0xa8,0x21,0x12,0x43,0x00,0x2a, ++0x3c,0x03,0xb0,0x03,0x02,0x43,0x10,0x21,0xa0,0x51,0x00,0x34,0x26,0x42,0x00,0x01, ++0x30,0x52,0x00,0xff,0x2e,0x43,0x00,0x05,0x14,0x60,0xff,0xd9,0x00,0x00,0x00,0x00, ++0x8f,0xa5,0x00,0x10,0x0c,0x00,0x06,0xbf,0x24,0x04,0x06,0x14,0x12,0xa0,0x00,0x0e, ++0x3c,0x02,0xb0,0x03,0x13,0xc0,0x00,0x0d,0x34,0x42,0x00,0x3c,0x00,0x15,0x10,0x40, ++0x00,0x55,0x10,0x21,0x00,0x02,0x10,0xc0,0x00,0x55,0x10,0x21,0x00,0x02,0xa8,0x80, ++0x02,0xbe,0x00,0x1b,0x17,0xc0,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0d, ++0x00,0x00,0xa8,0x12,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x3c,0x3c,0x03,0xb0,0x03, ++0x3c,0x04,0xb0,0x03,0xa4,0x55,0x00,0x00,0x34,0x63,0x00,0x1c,0x34,0x84,0x00,0x1d, ++0x24,0x02,0x00,0x01,0xa0,0x60,0x00,0x00,0xa0,0x82,0x00,0x00,0x7b,0xbe,0x01,0xfc, ++0x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,0xa2,0xd1,0x00,0x00,0x08,0x00,0x24,0x98, ++0x26,0x42,0x00,0x01,0x0c,0x00,0x06,0xd1,0x24,0x04,0x04,0xfc,0x08,0x00,0x24,0x8d, ++0x00,0x40,0x88,0x21,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x3c,0x3c,0x04,0xb0,0x03, ++0x3c,0x05,0xb0,0x03,0xa4,0x60,0x00,0x00,0x34,0x84,0x00,0x1c,0x34,0xa5,0x00,0x1d, ++0x24,0x02,0x00,0x02,0x24,0x03,0x00,0x01,0xa0,0x82,0x00,0x00,0x08,0x00,0x24,0xb7, ++0xa0,0xa3,0x00,0x00,0x0c,0x00,0x17,0x99,0x00,0x00,0x00,0x00,0x10,0x40,0xff,0x8b, ++0x00,0x10,0x12,0x02,0x3c,0x02,0xb0,0x03,0x3c,0x04,0xb0,0x03,0x34,0x42,0x00,0x3c, ++0x34,0x84,0x00,0x14,0x24,0x03,0x00,0x01,0xa4,0x40,0x00,0x00,0x3c,0x01,0xb0,0x03, ++0xa0,0x23,0x00,0x3f,0x08,0x00,0x24,0xb7,0xac,0x90,0x00,0x00,0x27,0xbd,0xff,0xd8, ++0xaf,0xb0,0x00,0x10,0x30,0xd0,0x00,0xff,0x2e,0x02,0x00,0x2e,0xaf,0xb2,0x00,0x18, ++0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,0x30,0xb1,0x00,0xff, ++0x14,0x40,0x00,0x06,0x00,0x80,0x90,0x21,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x2e,0x13,0x00,0x10, ++0x24,0x05,0x00,0x14,0x0c,0x00,0x13,0xa4,0x24,0x06,0x01,0x07,0x12,0x60,0x00,0x38, ++0x02,0x00,0x30,0x21,0x8f,0xa2,0x00,0x38,0x30,0xc3,0x00,0x3f,0x3c,0x04,0xb0,0x09, ++0x00,0x02,0x14,0x00,0x00,0x43,0x30,0x25,0x34,0x84,0x01,0x60,0x90,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xfd,0x24,0x02,0x00,0x01,0x12,0x22,0x00,0x2a, ++0x2a,0x22,0x00,0x02,0x14,0x40,0x00,0x24,0x24,0x02,0x00,0x02,0x12,0x22,0x00,0x20, ++0x24,0x02,0x00,0x03,0x12,0x22,0x00,0x19,0x00,0x00,0x00,0x00,0x16,0x60,0xff,0xe2, ++0x24,0x02,0x00,0x01,0x12,0x22,0x00,0x13,0x2a,0x22,0x00,0x02,0x14,0x40,0x00,0x0d, ++0x24,0x02,0x00,0x02,0x12,0x22,0x00,0x09,0x24,0x02,0x00,0x03,0x16,0x22,0xff,0xda, ++0x00,0x00,0x00,0x00,0x24,0x04,0x08,0x4c,0x24,0x05,0xff,0xff,0x0c,0x00,0x13,0x5f, ++0x3c,0x06,0x0c,0xb8,0x08,0x00,0x24,0xea,0x00,0x00,0x00,0x00,0x08,0x00,0x25,0x12, ++0x24,0x04,0x08,0x48,0x16,0x20,0xff,0xd0,0x00,0x00,0x00,0x00,0x08,0x00,0x25,0x12, ++0x24,0x04,0x08,0x40,0x08,0x00,0x25,0x12,0x24,0x04,0x08,0x44,0x24,0x04,0x08,0x4c, ++0x0c,0x00,0x13,0x5f,0x24,0x05,0xff,0xff,0x08,0x00,0x25,0x07,0x00,0x00,0x00,0x00, ++0x08,0x00,0x25,0x20,0x24,0x04,0x08,0x48,0x16,0x20,0xff,0xe0,0x00,0x00,0x00,0x00, ++0x08,0x00,0x25,0x20,0x24,0x04,0x08,0x40,0x08,0x00,0x25,0x20,0x24,0x04,0x08,0x44, ++0x02,0x40,0x20,0x21,0x0c,0x00,0x25,0x71,0x02,0x20,0x28,0x21,0x08,0x00,0x24,0xf5, ++0x00,0x40,0x30,0x21,0x27,0xbd,0xff,0xd8,0x2c,0xc2,0x00,0x2e,0xaf,0xb2,0x00,0x18, ++0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c, ++0x00,0xc0,0x80,0x21,0x30,0xb1,0x00,0xff,0x00,0x80,0x90,0x21,0x14,0x40,0x00,0x07, ++0x00,0x00,0x18,0x21,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc, ++0x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x2e,0x13,0x00,0x10, ++0x24,0x05,0x00,0x14,0x0c,0x00,0x13,0xa4,0x24,0x06,0x01,0x07,0x12,0x60,0x00,0x24, ++0x02,0x00,0x30,0x21,0x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x60,0x90,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xfd,0x30,0xc5,0x00,0x3f,0x0c,0x00,0x25,0xae, ++0x02,0x20,0x20,0x21,0x16,0x60,0x00,0x0a,0x00,0x40,0x80,0x21,0x24,0x02,0x00,0x01, ++0x12,0x22,0x00,0x15,0x2a,0x22,0x00,0x02,0x14,0x40,0x00,0x0f,0x24,0x02,0x00,0x02, ++0x12,0x22,0x00,0x0b,0x24,0x02,0x00,0x03,0x12,0x22,0x00,0x03,0x00,0x00,0x00,0x00, ++0x08,0x00,0x25,0x3d,0x02,0x00,0x18,0x21,0x24,0x04,0x08,0x4c,0x24,0x05,0xff,0xff, ++0x0c,0x00,0x13,0x5f,0x3c,0x06,0x0c,0xb8,0x08,0x00,0x25,0x3d,0x02,0x00,0x18,0x21, ++0x08,0x00,0x25,0x5f,0x24,0x04,0x08,0x48,0x16,0x20,0xff,0xf5,0x00,0x00,0x00,0x00, ++0x08,0x00,0x25,0x5f,0x24,0x04,0x08,0x40,0x08,0x00,0x25,0x5f,0x24,0x04,0x08,0x44, ++0x02,0x40,0x20,0x21,0x0c,0x00,0x25,0x71,0x02,0x20,0x28,0x21,0x08,0x00,0x25,0x49, ++0x00,0x40,0x30,0x21,0x27,0xbd,0xff,0xe8,0x2c,0xc2,0x00,0x1f,0xaf,0xb0,0x00,0x10, ++0xaf,0xbf,0x00,0x14,0x00,0xc0,0x80,0x21,0x14,0x40,0x00,0x1d,0x30,0xa5,0x00,0xff, ++0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x18,0x28,0xa2,0x00,0x02,0x14,0x40,0x00,0x12, ++0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x0e,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x07, ++0x24,0x04,0x08,0x4c,0x26,0x10,0xff,0xe2,0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x14, ++0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x24,0x05,0xff,0xff, ++0x0c,0x00,0x13,0x5f,0x3c,0x06,0x0d,0xf8,0x08,0x00,0x25,0x82,0x26,0x10,0xff,0xe2, ++0x08,0x00,0x25,0x87,0x24,0x04,0x08,0x48,0x14,0xa0,0xff,0xf2,0x24,0x04,0x08,0x40, ++0x08,0x00,0x25,0x88,0x24,0x05,0xff,0xff,0x08,0x00,0x25,0x87,0x24,0x04,0x08,0x44, ++0x2c,0xc2,0x00,0x10,0x14,0x40,0xff,0xec,0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x14, ++0x28,0xa2,0x00,0x02,0x14,0x40,0x00,0x0e,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x0a, ++0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x03,0x24,0x04,0x08,0x4c,0x08,0x00,0x25,0x82, ++0x26,0x10,0xff,0xf1,0x24,0x05,0xff,0xff,0x0c,0x00,0x13,0x5f,0x3c,0x06,0x0d,0xb8, ++0x08,0x00,0x25,0x82,0x26,0x10,0xff,0xf1,0x08,0x00,0x25,0xa1,0x24,0x04,0x08,0x48, ++0x14,0xa0,0xff,0xf6,0x24,0x04,0x08,0x40,0x08,0x00,0x25,0xa2,0x24,0x05,0xff,0xff, ++0x08,0x00,0x25,0xa1,0x24,0x04,0x08,0x44,0x27,0xbd,0xff,0xe8,0x30,0x84,0x00,0xff, ++0x24,0x02,0x00,0x01,0x10,0x82,0x00,0x39,0xaf,0xbf,0x00,0x10,0x28,0x82,0x00,0x02, ++0x14,0x40,0x00,0x27,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x17, ++0x00,0xa0,0x30,0x21,0x24,0x02,0x00,0x03,0x10,0x82,0x00,0x05,0x24,0x04,0x08,0x3c, ++0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18, ++0x0c,0x00,0x13,0x5f,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x3c,0x3c,0x05,0x80,0x00, ++0x0c,0x00,0x13,0x5f,0x00,0x00,0x30,0x21,0x24,0x04,0x08,0x3c,0x3c,0x05,0x80,0x00, ++0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x01,0x24,0x04,0x08,0xac,0x0c,0x00,0x13,0x41, ++0x24,0x05,0x0f,0xff,0x08,0x00,0x25,0xbc,0x00,0x00,0x00,0x00,0x24,0x04,0x08,0x34, ++0x0c,0x00,0x13,0x5f,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x34,0x3c,0x05,0x80,0x00, ++0x0c,0x00,0x13,0x5f,0x00,0x00,0x30,0x21,0x24,0x04,0x08,0x34,0x3c,0x05,0x80,0x00, ++0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x01,0x08,0x00,0x25,0xcb,0x24,0x04,0x08,0xa8, ++0x14,0x80,0xff,0xdf,0x00,0xa0,0x30,0x21,0x24,0x04,0x08,0x24,0x0c,0x00,0x13,0x5f, ++0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x24,0x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5f, ++0x00,0x00,0x30,0x21,0x24,0x04,0x08,0x24,0x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5f, ++0x24,0x06,0x00,0x01,0x08,0x00,0x25,0xcb,0x24,0x04,0x08,0xa0,0x00,0xa0,0x30,0x21, ++0x24,0x04,0x08,0x2c,0x0c,0x00,0x13,0x5f,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x2c, ++0x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5f,0x00,0x00,0x30,0x21,0x24,0x04,0x08,0x2c, ++0x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x01,0x08,0x00,0x25,0xcb, ++0x24,0x04,0x08,0xa4,0x3c,0x05,0x00,0x14,0x3c,0x02,0xb0,0x05,0x34,0x42,0x04,0x20, ++0x3c,0x06,0xc0,0x00,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0x34,0xa5,0x17,0x09, ++0xac,0x45,0x00,0x00,0x34,0xc6,0x05,0x07,0x34,0x63,0x04,0x24,0x34,0x84,0x02,0x28, ++0x3c,0x07,0xb0,0x05,0x24,0x02,0x00,0x20,0xac,0x66,0x00,0x00,0x34,0xe7,0x04,0x50, ++0xa0,0x82,0x00,0x00,0x90,0xe2,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x03, ++0x10,0x40,0xff,0xfc,0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x93,0x85,0x81,0xf1,0x24,0x02,0x00,0x01,0x14,0xa2,0x00,0x53,0x00,0x80,0x40,0x21, ++0x8c,0x89,0x00,0x04,0x3c,0x02,0xb0,0x01,0x01,0x22,0x30,0x21,0x8c,0xc3,0x00,0x04, ++0x3c,0x02,0x01,0x00,0x00,0x62,0x10,0x24,0x10,0x40,0x00,0x4b,0x30,0x62,0x00,0x08, ++0x10,0x45,0x00,0x59,0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x38,0x24,0x03,0x00,0xb4, ++0x30,0x44,0x00,0xff,0x10,0x83,0x00,0x61,0x24,0x02,0x00,0xc4,0x10,0x82,0x00,0x54, ++0x24,0x02,0x00,0x94,0x10,0x82,0x00,0x45,0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x38, ++0x00,0x00,0x00,0x00,0x30,0x47,0xff,0xff,0x30,0xe3,0x40,0xff,0x24,0x02,0x40,0x88, ++0x14,0x62,0x00,0x39,0x30,0xe3,0x03,0x00,0x24,0x02,0x03,0x00,0x10,0x62,0x00,0x38, ++0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x56,0x00,0x00,0x00,0x00,0x30,0x47,0xff,0xff, ++0x30,0xe2,0x00,0x80,0x14,0x40,0x00,0x30,0x3c,0x02,0xb0,0x01,0x01,0x22,0x30,0x21, ++0x94,0xc3,0x00,0x60,0x24,0x02,0x00,0x08,0x14,0x43,0x00,0x3b,0x00,0x00,0x00,0x00, ++0x90,0xc2,0x00,0x62,0x24,0x03,0x00,0x04,0x00,0x02,0x39,0x02,0x10,0xe3,0x00,0x15, ++0x24,0x02,0x00,0x06,0x14,0xe2,0x00,0x34,0x00,0x00,0x00,0x00,0x8d,0x05,0x01,0xac, ++0x94,0xc4,0x00,0x66,0x27,0x82,0x89,0x68,0x00,0x05,0x28,0x80,0x30,0x87,0xff,0xff, ++0x00,0xa2,0x28,0x21,0x00,0x07,0x1a,0x00,0x8c,0xa4,0x00,0x00,0x00,0x07,0x12,0x02, ++0x00,0x43,0x10,0x25,0x24,0x42,0x00,0x5e,0x24,0x03,0xc0,0x00,0x30,0x47,0xff,0xff, ++0x00,0x83,0x20,0x24,0x00,0x87,0x20,0x25,0xac,0xa4,0x00,0x00,0x08,0x00,0x26,0x76, ++0xad,0x07,0x00,0x10,0x8d,0x05,0x01,0xac,0x94,0xc4,0x00,0x64,0x27,0x82,0x89,0x68, ++0x00,0x05,0x28,0x80,0x30,0x87,0xff,0xff,0x00,0xa2,0x28,0x21,0x00,0x07,0x1a,0x00, ++0x8c,0xa4,0x00,0x00,0x00,0x07,0x12,0x02,0x00,0x43,0x10,0x25,0x24,0x42,0x00,0x36, ++0x3c,0x03,0xff,0xff,0x30,0x47,0xff,0xff,0x00,0x83,0x20,0x24,0x00,0x87,0x20,0x25, ++0xac,0xa4,0x00,0x00,0xad,0x07,0x00,0x10,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x94,0xc2,0x00,0x50,0x08,0x00,0x26,0x34,0x30,0x47,0xff,0xff,0x8d,0x04,0x01,0xac, ++0x27,0x83,0x89,0x68,0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x00, ++0x3c,0x03,0xff,0xff,0x00,0x43,0x10,0x24,0x34,0x42,0x00,0x2e,0xac,0x82,0x00,0x00, ++0x24,0x03,0x00,0x2e,0xad,0x03,0x00,0x10,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x8d,0x04,0x01,0xac,0x27,0x83,0x89,0x68,0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21, ++0x8c,0x82,0x00,0x00,0x3c,0x03,0xff,0xff,0x00,0x43,0x10,0x24,0x34,0x42,0x00,0x0e, ++0x24,0x03,0x00,0x0e,0x08,0x00,0x26,0x75,0xac,0x82,0x00,0x00,0x8d,0x04,0x01,0xac, ++0x27,0x83,0x89,0x68,0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x00, ++0x3c,0x03,0xff,0xff,0x00,0x43,0x10,0x24,0x34,0x42,0x00,0x14,0x24,0x03,0x00,0x14, ++0x08,0x00,0x26,0x75,0xac,0x82,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x30,0xc6,0x00,0xff,0x00,0x06,0x48,0x40,0x01,0x26,0x10,0x21,0x00,0x02,0x10,0x80, ++0x27,0x8b,0xbc,0x30,0x27,0x83,0xbc,0x36,0x00,0x4b,0x40,0x21,0x00,0x43,0x10,0x21, ++0x94,0x47,0x00,0x00,0x30,0xa2,0x3f,0xff,0x10,0xe2,0x00,0x29,0x30,0x8a,0xff,0xff, ++0x95,0x02,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0x02,0x11,0x82,0x30,0x42,0x00,0x01, ++0x10,0x43,0x00,0x18,0x00,0x00,0x00,0x00,0x01,0x26,0x10,0x21,0x00,0x02,0x10,0x80, ++0x00,0x4b,0x30,0x21,0x94,0xc4,0x00,0x02,0x27,0x83,0xbc,0x36,0x27,0x85,0xbc,0x34, ++0x00,0x45,0x28,0x21,0x30,0x84,0xff,0xdf,0x00,0x43,0x10,0x21,0xa4,0xc4,0x00,0x02, ++0xa4,0x40,0x00,0x00,0xa4,0xa0,0x00,0x00,0x94,0xc3,0x00,0x02,0x3c,0x04,0xb0,0x01, ++0x01,0x44,0x20,0x21,0x30,0x63,0xff,0xbf,0xa4,0xc3,0x00,0x02,0xa0,0xc0,0x00,0x00, ++0x8c,0x82,0x00,0x04,0x24,0x03,0xf0,0xff,0x00,0x43,0x10,0x24,0x03,0xe0,0x00,0x08, ++0xac,0x82,0x00,0x04,0x24,0x02,0xc0,0x00,0x91,0x04,0x00,0x01,0x00,0xa2,0x10,0x24, ++0x00,0x47,0x28,0x25,0x3c,0x03,0xb0,0x01,0x24,0x02,0x00,0x02,0x14,0x82,0xff,0xe2, ++0x01,0x43,0x18,0x21,0xac,0x65,0x00,0x00,0x08,0x00,0x26,0xa3,0x01,0x26,0x10,0x21, ++0x08,0x00,0x26,0xa3,0x01,0x26,0x10,0x21,0x93,0x83,0x81,0xf1,0x24,0x02,0x00,0x01, ++0x14,0x62,0x00,0x0d,0x3c,0x02,0xb0,0x01,0x8c,0x84,0x00,0x04,0x3c,0x06,0xb0,0x09, ++0x00,0x82,0x20,0x21,0x8c,0x85,0x00,0x08,0x8c,0x83,0x00,0x04,0x3c,0x02,0x01,0x00, ++0x34,0xc6,0x01,0x00,0x00,0x62,0x18,0x24,0x14,0x60,0x00,0x05,0x30,0xa5,0x20,0x00, ++0x24,0x02,0x00,0x06,0xa0,0xc2,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x3c,0x03,0xb0,0x09,0x10,0xa0,0xff,0xfc,0x34,0x63,0x01,0x00,0x24,0x02,0x00,0x0e, ++0x08,0x00,0x26,0xd6,0xa0,0x62,0x00,0x00,0x3c,0x02,0xb0,0x01,0x30,0xa5,0xff,0xff, ++0x00,0xa2,0x28,0x21,0x8c,0xa3,0x00,0x00,0x3c,0x02,0x10,0x00,0x00,0x80,0x30,0x21, ++0x00,0x62,0x18,0x24,0x8c,0xa2,0x00,0x04,0x10,0x60,0x00,0x04,0x00,0x00,0x00,0x00, ++0x30,0x42,0x80,0x00,0x10,0x40,0x00,0x13,0x00,0x00,0x00,0x00,0x8c,0xc2,0x01,0xa8, ++0x00,0x00,0x00,0x00,0x24,0x44,0x00,0x01,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40, ++0x00,0x83,0x10,0x0a,0x93,0x83,0x81,0xf0,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80, ++0x00,0x82,0x20,0x23,0x24,0x63,0xff,0xff,0xac,0xc4,0x01,0xa8,0xa3,0x83,0x81,0xf0, ++0x8c,0xc4,0x01,0xac,0x8c,0xc2,0x01,0xa8,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x26, ++0x00,0x02,0x10,0x2b,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03, ++0x34,0x63,0x00,0x73,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01, ++0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0xa3,0x80,0x81,0xf1,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0xa3,0x82,0x81,0xf1,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x04,0x3c,0x05,0xb0,0x01,0x00,0x80,0x50,0x21, ++0x00,0x45,0x10,0x21,0x8c,0x43,0x00,0x04,0x24,0x02,0x00,0x05,0x00,0x03,0x1a,0x02, ++0x30,0x69,0x00,0x0f,0x11,0x22,0x00,0x0b,0x24,0x02,0x00,0x07,0x11,0x22,0x00,0x09, ++0x24,0x02,0x00,0x0a,0x11,0x22,0x00,0x07,0x24,0x02,0x00,0x0b,0x11,0x22,0x00,0x05, ++0x24,0x02,0x00,0x01,0x93,0x83,0x81,0xf0,0x3c,0x04,0xb0,0x06,0x10,0x62,0x00,0x03, ++0x34,0x84,0x80,0x18,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x02,0x17,0x02,0x14,0x40,0xff,0xfa,0x00,0x00,0x00,0x00, ++0x8d,0x43,0x01,0xa8,0x27,0x82,0x89,0x68,0x00,0x03,0x18,0x80,0x00,0x6a,0x20,0x21, ++0x8c,0x87,0x00,0xa8,0x00,0x62,0x18,0x21,0x8c,0x68,0x00,0x00,0x00,0xe5,0x28,0x21, ++0x8c,0xa9,0x00,0x00,0x3c,0x02,0xff,0xff,0x27,0x83,0x8a,0x68,0x01,0x22,0x10,0x24, ++0x00,0x48,0x10,0x25,0xac,0xa2,0x00,0x00,0x8d,0x44,0x01,0xa8,0x00,0x07,0x30,0xc2, ++0x3c,0x02,0x00,0x80,0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x00,0x06,0x32,0x00, ++0x8c,0xa9,0x00,0x04,0x00,0xc2,0x30,0x25,0x8c,0x82,0x00,0x00,0x3c,0x03,0x80,0x00, ++0x01,0x22,0x10,0x25,0x00,0x43,0x10,0x25,0xac,0xa2,0x00,0x04,0xaf,0x87,0xbc,0x20, ++0x8c,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x82,0xbc,0x28,0x8c,0xa3,0x00,0x04, ++0x3c,0x01,0xb0,0x07,0xac,0x26,0x80,0x18,0x8d,0x42,0x01,0xa8,0xaf,0x83,0xbc,0x24, ++0x93,0x85,0x81,0xf0,0x24,0x44,0x00,0x01,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40, ++0x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x24,0xa5,0xff,0xff, ++0x00,0x82,0x20,0x23,0xad,0x44,0x01,0xa8,0xa3,0x85,0x81,0xf0,0x08,0x00,0x27,0x21, ++0x00,0x00,0x00,0x00,0x3c,0x05,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0xa5,0x00,0x20, ++0x24,0x42,0x9d,0x64,0xac,0xa2,0x00,0x00,0x24,0x02,0x00,0x02,0x24,0x03,0x00,0x20, ++0xac,0x82,0x00,0x64,0x3c,0x02,0x80,0x01,0xac,0x83,0x00,0x60,0xac,0x80,0x00,0x00, ++0xac,0x80,0x00,0x04,0xac,0x80,0x00,0x08,0xac,0x80,0x00,0x4c,0xac,0x80,0x00,0x50, ++0xac,0x80,0x00,0x54,0xac,0x80,0x00,0x0c,0xac,0x80,0x00,0x58,0xa0,0x80,0x00,0x5c, ++0x24,0x42,0x9e,0x28,0x24,0x83,0x00,0x68,0x24,0x05,0x00,0x0f,0x24,0xa5,0xff,0xff, ++0xac,0x62,0x00,0x00,0x04,0xa1,0xff,0xfd,0x24,0x63,0x00,0x04,0x3c,0x02,0x80,0x01, ++0x24,0x42,0x9f,0x10,0xac,0x82,0x00,0x78,0x3c,0x03,0x80,0x01,0x3c,0x02,0x80,0x01, ++0x24,0x63,0xa0,0x9c,0x24,0x42,0xa0,0x08,0xac,0x83,0x00,0x88,0xac,0x82,0x00,0x98, ++0x3c,0x03,0x80,0x01,0x3c,0x02,0x80,0x01,0x24,0x63,0xa1,0x44,0x24,0x42,0xa2,0x5c, ++0xac,0x83,0x00,0xa0,0xac,0x82,0x00,0xa4,0xa0,0x80,0x01,0xba,0xac,0x80,0x01,0xa8, ++0xac,0x80,0x01,0xac,0xac,0x80,0x01,0xb0,0xac,0x80,0x01,0xb4,0xa0,0x80,0x01,0xb8, ++0x03,0xe0,0x00,0x08,0xa0,0x80,0x01,0xb9,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01, ++0x34,0x63,0x00,0x20,0x24,0x42,0x9e,0x28,0x03,0xe0,0x00,0x08,0xac,0x62,0x00,0x00, ++0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x34,0x42,0x00,0x20,0x24,0x63,0x9e,0x40, ++0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x10,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x11, ++0x00,0x80,0x28,0x21,0x8c,0x82,0x00,0x14,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0d, ++0x00,0x00,0x00,0x00,0x8c,0x84,0x00,0x10,0x8c,0xa3,0x00,0x14,0x8c,0xa2,0x00,0x04, ++0x00,0x83,0x20,0x21,0x00,0x44,0x10,0x21,0x30,0x43,0x00,0xff,0x00,0x03,0x18,0x2b, ++0x00,0x02,0x12,0x02,0x00,0x43,0x10,0x21,0x00,0x02,0x12,0x00,0x30,0x42,0x3f,0xff, ++0xac,0xa2,0x00,0x04,0xac,0xa0,0x00,0x00,0xac,0xa0,0x00,0x4c,0xac,0xa0,0x00,0x50, ++0xac,0xa0,0x00,0x54,0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x0c,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,0x24,0x42,0x9e,0xbc,0xac,0x62,0x00,0x00, ++0x8c,0x86,0x00,0x04,0x3c,0x02,0xb0,0x01,0x24,0x03,0x00,0x01,0x00,0xc2,0x10,0x21, ++0x8c,0x45,0x00,0x00,0xac,0x83,0x00,0x4c,0x00,0x05,0x14,0x02,0x30,0xa3,0x3f,0xff, ++0x30,0x42,0x00,0xff,0xac,0x83,0x00,0x10,0xac,0x82,0x00,0x14,0x8c,0x83,0x00,0x14, ++0xac,0x85,0x00,0x40,0x00,0xc3,0x30,0x21,0x03,0xe0,0x00,0x08,0xac,0x86,0x00,0x08, ++0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20, ++0x24,0x63,0x9f,0x10,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00, ++0x8c,0x82,0x00,0x4c,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0a,0x00,0x80,0x80,0x21, ++0xae,0x00,0x00,0x00,0xae,0x00,0x00,0x4c,0xae,0x00,0x00,0x50,0xae,0x00,0x00,0x54, ++0xae,0x00,0x00,0x0c,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x18,0x0c,0x00,0x27,0xaf,0x00,0x00,0x00,0x00,0x08,0x00,0x27,0xd1, ++0xae,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8, ++0x34,0x42,0x00,0x20,0x24,0x63,0x9f,0x74,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14, ++0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x4c,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x16, ++0x00,0x80,0x80,0x21,0x8e,0x03,0x00,0x08,0x3c,0x02,0xb0,0x01,0x8e,0x04,0x00,0x44, ++0x00,0x62,0x18,0x21,0x90,0x65,0x00,0x00,0x24,0x02,0x00,0x01,0xae,0x02,0x00,0x50, ++0x30,0xa3,0x00,0xff,0x00,0x03,0x10,0x82,0x00,0x04,0x23,0x02,0x30,0x84,0x00,0x0f, ++0x30,0x42,0x00,0x03,0x00,0x03,0x19,0x02,0xae,0x04,0x00,0x34,0xae,0x02,0x00,0x2c, ++0xae,0x03,0x00,0x30,0xa2,0x05,0x00,0x48,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x27,0xaf,0x00,0x00,0x00,0x00, ++0x08,0x00,0x27,0xe9,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01, ++0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xa0,0x08,0xaf,0xb0,0x00,0x10, ++0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x50,0x00,0x00,0x00,0x00, ++0x10,0x40,0x00,0x16,0x00,0x80,0x80,0x21,0x92,0x03,0x00,0x44,0x8e,0x02,0x00,0x40, ++0x83,0x85,0x8b,0xd4,0x92,0x04,0x00,0x41,0x30,0x63,0x00,0x01,0x00,0x02,0x16,0x02, ++0xae,0x04,0x00,0x14,0x00,0x00,0x30,0x21,0xae,0x02,0x00,0x18,0x10,0xa0,0x00,0x04, ++0xae,0x03,0x00,0x3c,0x10,0x60,0x00,0x03,0x24,0x02,0x00,0x01,0x24,0x06,0x00,0x01, ++0x24,0x02,0x00,0x01,0xa3,0x86,0x8b,0xd4,0x8f,0xbf,0x00,0x14,0xae,0x02,0x00,0x54, ++0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x27,0xdd, ++0x00,0x00,0x00,0x00,0x08,0x00,0x28,0x0e,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03, ++0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xa0,0x9c, ++0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x50, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x1b,0x00,0x80,0x80,0x21,0x3c,0x02,0xb0,0x03, ++0x8c,0x42,0x00,0x00,0x92,0x04,0x00,0x44,0x8e,0x03,0x00,0x40,0x83,0x86,0x8b,0xd4, ++0x92,0x05,0x00,0x41,0x30,0x42,0x08,0x00,0x30,0x84,0x00,0x01,0x00,0x02,0x12,0xc2, ++0x00,0x03,0x1e,0x02,0x00,0x82,0x20,0x25,0xae,0x05,0x00,0x14,0x00,0x00,0x38,0x21, ++0xae,0x03,0x00,0x18,0x10,0xc0,0x00,0x04,0xae,0x04,0x00,0x3c,0x10,0x80,0x00,0x03, ++0x24,0x02,0x00,0x01,0x24,0x07,0x00,0x01,0x24,0x02,0x00,0x01,0xa3,0x87,0x8b,0xd4, ++0x8f,0xbf,0x00,0x14,0xae,0x02,0x00,0x54,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x18,0x0c,0x00,0x27,0xdd,0x00,0x00,0x00,0x00,0x08,0x00,0x28,0x33, ++0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8, ++0x34,0x42,0x00,0x20,0x24,0x63,0xa1,0x44,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14, ++0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x54,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x37, ++0x00,0x80,0x80,0x21,0x8e,0x04,0x00,0x04,0x8e,0x03,0x00,0x44,0x3c,0x02,0x80,0x00, ++0x3c,0x05,0xb0,0x01,0x34,0x42,0x00,0x10,0x00,0x85,0x20,0x21,0x00,0x62,0x18,0x25, ++0xac,0x83,0x00,0x04,0x8e,0x02,0x00,0x04,0x8e,0x03,0x01,0xac,0x02,0x00,0x20,0x21, ++0x00,0x45,0x10,0x21,0x8c,0x46,0x00,0x00,0x00,0x03,0x18,0x80,0x27,0x82,0x89,0x68, ++0x00,0x62,0x18,0x21,0xac,0x66,0x00,0x00,0x8e,0x02,0x00,0x04,0x8e,0x03,0x01,0xac, ++0x00,0x45,0x10,0x21,0x8c,0x46,0x00,0x04,0x00,0x03,0x18,0x80,0x27,0x82,0x8a,0x68, ++0x00,0x62,0x18,0x21,0x0c,0x00,0x26,0x10,0xac,0x66,0x00,0x00,0x8e,0x03,0x01,0xac, ++0x8e,0x07,0x00,0x04,0x3c,0x06,0xb0,0x03,0x24,0x65,0x00,0x01,0x28,0xa4,0x00,0x00, ++0x24,0x62,0x00,0x40,0x00,0xa4,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80, ++0x00,0x03,0x18,0x80,0x00,0xa2,0x28,0x23,0x00,0x70,0x18,0x21,0xae,0x05,0x01,0xac, ++0xac,0x67,0x00,0xa8,0x34,0xc6,0x00,0x30,0x8c,0xc3,0x00,0x00,0x93,0x82,0x81,0xf0, ++0x02,0x00,0x20,0x21,0x24,0x63,0x00,0x01,0x24,0x42,0x00,0x01,0xac,0xc3,0x00,0x00, ++0xa3,0x82,0x81,0xf0,0x0c,0x00,0x27,0x90,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x14, ++0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x28,0x27, ++0x00,0x00,0x00,0x00,0x08,0x00,0x28,0x5d,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03, ++0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xa2,0x5c, ++0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x54, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x37,0x00,0x80,0x80,0x21,0x8e,0x04,0x00,0x04, ++0x8e,0x03,0x00,0x44,0x3c,0x02,0x80,0x00,0x3c,0x05,0xb0,0x01,0x34,0x42,0x00,0x10, ++0x00,0x85,0x20,0x21,0x00,0x62,0x18,0x25,0xac,0x83,0x00,0x04,0x8e,0x02,0x00,0x04, ++0x8e,0x03,0x01,0xac,0x02,0x00,0x20,0x21,0x00,0x45,0x10,0x21,0x8c,0x46,0x00,0x00, ++0x00,0x03,0x18,0x80,0x27,0x82,0x89,0x68,0x00,0x62,0x18,0x21,0xac,0x66,0x00,0x00, ++0x8e,0x02,0x00,0x04,0x8e,0x03,0x01,0xac,0x00,0x45,0x10,0x21,0x8c,0x46,0x00,0x04, ++0x00,0x03,0x18,0x80,0x27,0x82,0x8a,0x68,0x00,0x62,0x18,0x21,0x0c,0x00,0x26,0x10, ++0xac,0x66,0x00,0x00,0x8e,0x03,0x01,0xac,0x8e,0x07,0x00,0x04,0x3c,0x06,0xb0,0x03, ++0x24,0x65,0x00,0x01,0x28,0xa4,0x00,0x00,0x24,0x62,0x00,0x40,0x00,0xa4,0x10,0x0a, ++0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x03,0x18,0x80,0x00,0xa2,0x28,0x23, ++0x00,0x70,0x18,0x21,0xae,0x05,0x01,0xac,0xac,0x67,0x00,0xa8,0x34,0xc6,0x00,0x30, ++0x8c,0xc3,0x00,0x00,0x93,0x82,0x81,0xf0,0x02,0x00,0x20,0x21,0x24,0x63,0x00,0x01, ++0x24,0x42,0x00,0x01,0xac,0xc3,0x00,0x00,0xa3,0x82,0x81,0xf0,0x0c,0x00,0x27,0x90, ++0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x18,0x0c,0x00,0x28,0x27,0x00,0x00,0x00,0x00,0x08,0x00,0x28,0xa3, ++0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x34,0x42,0x00,0x20, ++0x24,0x63,0xa3,0x74,0x27,0xbd,0xff,0xe0,0xac,0x43,0x00,0x00,0x3c,0x02,0x80,0x01, ++0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x1c, ++0x00,0x80,0x80,0x21,0x24,0x52,0x9e,0x28,0x00,0x00,0x88,0x21,0x3c,0x03,0xb0,0x09, ++0x34,0x63,0x00,0x06,0x8e,0x06,0x00,0x04,0x90,0x62,0x00,0x00,0x00,0x06,0x22,0x02, ++0x00,0x44,0x10,0x23,0x24,0x44,0x00,0x40,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x7f, ++0x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x24,0x84,0xff,0xff, ++0x10,0x44,0x00,0x68,0x00,0x00,0x28,0x21,0x3c,0x02,0xb0,0x01,0x00,0xc2,0x10,0x21, ++0x8c,0x44,0x00,0x04,0x3c,0x03,0x7c,0x00,0x34,0x63,0x00,0xf0,0x00,0x83,0x18,0x24, ++0xae,0x04,0x00,0x44,0x8c,0x44,0x00,0x00,0x10,0x60,0x00,0x69,0x00,0x00,0x38,0x21, ++0x3c,0x09,0xb0,0x03,0x3c,0x06,0x7c,0x00,0x35,0x29,0x00,0x99,0x3c,0x0a,0xb0,0x01, ++0x24,0x08,0x00,0x40,0x34,0xc6,0x00,0xf0,0x3c,0x0b,0xff,0xff,0x3c,0x0c,0x28,0x38, ++0x16,0x20,0x00,0x06,0x24,0xa5,0x00,0x01,0x93,0x82,0x81,0xf6,0x24,0x11,0x00,0x01, ++0x24,0x42,0x00,0x01,0xa1,0x22,0x00,0x00,0xa3,0x82,0x81,0xf6,0x8e,0x02,0x00,0x04, ++0x24,0x07,0x00,0x01,0x24,0x42,0x01,0x00,0x30,0x42,0x3f,0xff,0xae,0x02,0x00,0x04, ++0x00,0x4a,0x10,0x21,0x8c,0x43,0x00,0x04,0x00,0x00,0x00,0x00,0xae,0x03,0x00,0x44, ++0x8c,0x44,0x00,0x00,0x10,0xa8,0x00,0x2d,0x00,0x66,0x18,0x24,0x14,0x60,0xff,0xec, ++0x00,0x8b,0x10,0x24,0x14,0x4c,0xff,0xea,0x24,0x02,0x00,0x01,0x10,0xe2,0x00,0x2f, ++0x3c,0x03,0xb0,0x09,0x8e,0x02,0x00,0x44,0x8e,0x04,0x00,0x60,0x00,0x02,0x1e,0x42, ++0x00,0x02,0x12,0x02,0x30,0x42,0x00,0x0f,0x30,0x63,0x00,0x01,0xae,0x02,0x00,0x00, ++0x10,0x44,0x00,0x1a,0xae,0x03,0x00,0x58,0x8e,0x02,0x00,0x64,0x8e,0x04,0x00,0x58, ++0x00,0x00,0x00,0x00,0x10,0x82,0x00,0x05,0x00,0x00,0x00,0x00,0xae,0x00,0x00,0x4c, ++0xae,0x00,0x00,0x50,0xae,0x00,0x00,0x54,0xae,0x00,0x00,0x0c,0x8e,0x03,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x03,0x10,0x80,0x00,0x50,0x10,0x21,0x8c,0x42,0x00,0x68, ++0x00,0x00,0x00,0x00,0x10,0x52,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x40,0xf8,0x09, ++0x02,0x00,0x20,0x21,0x8e,0x04,0x00,0x58,0x8e,0x03,0x00,0x00,0x00,0x00,0x00,0x00, ++0xae,0x03,0x00,0x60,0x08,0x00,0x28,0xeb,0xae,0x04,0x00,0x64,0x8e,0x02,0x00,0x64, ++0x00,0x00,0x00,0x00,0x14,0x62,0xff,0xe5,0x00,0x00,0x00,0x00,0x7a,0x02,0x0d,0x7c, ++0x8f,0xbf,0x00,0x1c,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x00,0x43,0x10,0x26, ++0x00,0x02,0x10,0x2b,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x34,0x63,0x00,0x06, ++0x8e,0x04,0x00,0x04,0x90,0x62,0x00,0x00,0x00,0x04,0x22,0x02,0x00,0x44,0x10,0x23, ++0x24,0x44,0x00,0x40,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x7f,0x00,0x83,0x10,0x0a, ++0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x82,0x20,0x23,0x14,0x87,0xff,0xc5, ++0x00,0x00,0x00,0x00,0x8e,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x62,0x00,0x03, ++0x14,0x40,0x00,0x05,0x24,0x02,0x00,0x0d,0x10,0x62,0x00,0x03,0x24,0x02,0x00,0x01, ++0x08,0x00,0x29,0x4b,0xa2,0x02,0x00,0x5c,0x08,0x00,0x29,0x4b,0xa2,0x00,0x00,0x5c, ++0x3c,0x02,0xff,0xff,0x00,0x82,0x10,0x24,0x3c,0x03,0x28,0x38,0x14,0x43,0xff,0x94, ++0x24,0x02,0x00,0x01,0x08,0x00,0x29,0x23,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03, ++0x3c,0x03,0x80,0x01,0x34,0x42,0x00,0x20,0x24,0x63,0xa5,0xcc,0xac,0x43,0x00,0x00, ++0x8c,0x83,0x01,0xa8,0x8c,0x82,0x01,0xac,0x00,0x80,0x40,0x21,0x10,0x62,0x00,0x20, ++0x00,0x00,0x20,0x21,0x93,0x82,0x81,0xf1,0x00,0x03,0x28,0x80,0x3c,0x07,0xb0,0x06, ++0x00,0xa8,0x18,0x21,0x24,0x04,0x00,0x01,0x8c,0x66,0x00,0xa8,0x10,0x44,0x00,0x1c, ++0x34,0xe7,0x80,0x18,0x3c,0x05,0xb0,0x01,0xaf,0x86,0xbc,0x20,0x00,0xc5,0x28,0x21, ++0x8c,0xa3,0x00,0x00,0x00,0x06,0x20,0xc2,0x3c,0x02,0x00,0x80,0x00,0x04,0x22,0x00, ++0x00,0x82,0x20,0x25,0xaf,0x83,0xbc,0x28,0x8c,0xa2,0x00,0x04,0xac,0xe4,0x00,0x00, ++0x8d,0x03,0x01,0xa8,0xaf,0x82,0xbc,0x24,0x24,0x64,0x00,0x01,0x04,0x80,0x00,0x0a, ++0x00,0x80,0x10,0x21,0x00,0x02,0x11,0x83,0x8d,0x03,0x01,0xac,0x00,0x02,0x11,0x80, ++0x00,0x82,0x10,0x23,0x00,0x43,0x18,0x26,0xad,0x02,0x01,0xa8,0x00,0x03,0x20,0x2b, ++0x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x08,0x00,0x29,0x95,0x24,0x62,0x00,0x40, ++0x27,0x82,0x89,0x68,0x00,0x06,0x20,0xc2,0x00,0x04,0x22,0x00,0x00,0xa2,0x48,0x21, ++0x3c,0x02,0x00,0x80,0x00,0x82,0x58,0x25,0x93,0x82,0x81,0xf0,0x3c,0x0a,0xb0,0x06, ++0x3c,0x03,0xb0,0x01,0x2c,0x42,0x00,0x02,0x00,0xc3,0x38,0x21,0x35,0x4a,0x80,0x18, ++0x14,0x40,0xff,0xef,0x00,0x00,0x20,0x21,0x8c,0xe5,0x00,0x00,0x8d,0x23,0x00,0x00, ++0x24,0x02,0xc0,0x00,0x00,0xa2,0x10,0x24,0x00,0x43,0x10,0x25,0xac,0xe2,0x00,0x00, ++0x8d,0x04,0x01,0xa8,0x27,0x83,0x8a,0x68,0x8c,0xe5,0x00,0x04,0x00,0x04,0x20,0x80, ++0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x00,0x3c,0x03,0x80,0x00,0x00,0xa2,0x10,0x25, ++0x00,0x43,0x10,0x25,0xac,0xe2,0x00,0x04,0xaf,0x86,0xbc,0x20,0x8c,0xe2,0x00,0x00, ++0x93,0x85,0x81,0xf0,0xaf,0x82,0xbc,0x28,0x8c,0xe3,0x00,0x04,0xad,0x4b,0x00,0x00, ++0x8d,0x02,0x01,0xa8,0xaf,0x83,0xbc,0x24,0x24,0xa5,0xff,0xff,0x24,0x44,0x00,0x01, ++0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40,0x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83, ++0x00,0x02,0x11,0x80,0x00,0x82,0x20,0x23,0xad,0x04,0x01,0xa8,0xa3,0x85,0x81,0xf0, ++0x79,0x02,0x0d,0x7c,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x26,0x08,0x00,0x29,0x9c, ++0x00,0x02,0x20,0x2b,0x3c,0x04,0xb0,0x03,0x3c,0x06,0xb0,0x07,0x3c,0x02,0x80,0x01, ++0x34,0xc6,0x00,0x18,0x34,0x84,0x00,0x20,0x24,0x42,0xa7,0x54,0x24,0x03,0xff,0x83, ++0xac,0x82,0x00,0x00,0xa0,0xc3,0x00,0x00,0x90,0xc4,0x00,0x00,0x27,0xbd,0xff,0xf8, ++0x3c,0x03,0xb0,0x07,0x24,0x02,0xff,0x82,0xa3,0xa4,0x00,0x00,0xa0,0x62,0x00,0x00, ++0x90,0x64,0x00,0x00,0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x08,0xa3,0xa4,0x00,0x01, ++0xa0,0x40,0x00,0x00,0x90,0x43,0x00,0x00,0x24,0x02,0x00,0x03,0x3c,0x05,0xb0,0x07, ++0xa3,0xa3,0x00,0x00,0xa0,0xc2,0x00,0x00,0x90,0xc4,0x00,0x00,0x34,0xa5,0x00,0x10, ++0x24,0x02,0x00,0x06,0x3c,0x03,0xb0,0x07,0xa3,0xa4,0x00,0x00,0x34,0x63,0x00,0x38, ++0xa0,0xa2,0x00,0x00,0x90,0x64,0x00,0x00,0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x20, ++0xa3,0xa4,0x00,0x00,0xa0,0xa0,0x00,0x00,0x90,0xa3,0x00,0x00,0xaf,0x82,0xbf,0x30, ++0xa3,0xa3,0x00,0x00,0xa0,0x40,0x00,0x00,0x90,0x43,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x08,}; ++ ++static u8 rtl8192e_fwdata_array[] = { ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x10,0x00,0x08,0x00, ++0x02,0xe9,0x01,0x74,0x02,0xab,0x01,0xc7,0x01,0x55,0x00,0xe4,0x00,0xab,0x00,0x72, ++0x00,0x55,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x02,0x76,0x01,0x3b, ++0x00,0xd2,0x00,0x9e,0x00,0x69,0x00,0x4f,0x00,0x46,0x00,0x3f,0x01,0x3b,0x00,0x9e, ++0x00,0x69,0x00,0x4f,0x00,0x35,0x00,0x27,0x00,0x23,0x00,0x20,0x01,0x2f,0x00,0x98, ++0x00,0x65,0x00,0x4c,0x00,0x33,0x00,0x26,0x00,0x22,0x00,0x1e,0x00,0x98,0x00,0x4c, ++0x00,0x33,0x00,0x26,0x00,0x19,0x00,0x13,0x00,0x11,0x00,0x0f,0x02,0x39,0x01,0x1c, ++0x00,0xbd,0x00,0x8e,0x00,0x5f,0x00,0x47,0x00,0x3f,0x00,0x39,0x01,0x1c,0x00,0x8e, ++0x00,0x5f,0x00,0x47,0x00,0x2f,0x00,0x23,0x00,0x20,0x00,0x1c,0x01,0x11,0x00,0x89, ++0x00,0x5b,0x00,0x44,0x00,0x2e,0x00,0x22,0x00,0x1e,0x00,0x1b,0x00,0x89,0x00,0x44, ++0x00,0x2e,0x00,0x22,0x00,0x17,0x00,0x11,0x00,0x0f,0x00,0x0e,0x02,0xab,0x02,0xab, ++0x02,0x66,0x02,0x66,0x07,0x06,0x06,0x06,0x05,0x06,0x07,0x08,0x04,0x06,0x07,0x08, ++0x09,0x0a,0x0b,0x0b,0x49,0x6e,0x74,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x54,0x4c, ++0x42,0x4d,0x4f,0x44,0x00,0x00,0x00,0x00,0x54,0x4c,0x42,0x4c,0x5f,0x64,0x61,0x74, ++0x61,0x00,0x54,0x4c,0x42,0x53,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x64,0x45,0x4c, ++0x5f,0x64,0x61,0x74,0x61,0x00,0x41,0x64,0x45,0x53,0x00,0x00,0x00,0x00,0x00,0x00, ++0x45,0x78,0x63,0x43,0x6f,0x64,0x65,0x36,0x00,0x00,0x45,0x78,0x63,0x43,0x6f,0x64, ++0x65,0x37,0x00,0x00,0x53,0x79,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x42,0x70, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x52,0x49,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x43,0x70,0x55,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4f,0x76,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x01,0x0b,0x63, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x2c, ++0x00,0x00,0x00,0x58,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x48,0x00,0x00,0x00,0x60, ++0x00,0x00,0x00,0x90,0x00,0x00,0x00,0xc0,0x00,0x00,0x01,0x20,0x00,0x00,0x01,0x80, ++0x00,0x00,0x01,0xb0,0x00,0x00,0x00,0x34,0x00,0x00,0x00,0x68,0x00,0x00,0x00,0x9c, ++0x00,0x00,0x00,0xd0,0x00,0x00,0x01,0x38,0x00,0x00,0x01,0xa0,0x00,0x00,0x01,0xd4, ++0x00,0x00,0x02,0x08,0x00,0x00,0x00,0x68,0x00,0x00,0x00,0xd0,0x00,0x00,0x01,0x38, ++0x00,0x00,0x01,0xa0,0x00,0x00,0x02,0x6f,0x00,0x00,0x03,0x40,0x00,0x00,0x03,0xa8, ++0x00,0x00,0x04,0x10,0x01,0x01,0x01,0x02,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04, ++0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x02,0x03,0x03,0x04,0x05,0x06,0x07,0x08, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x07,0x6c,0x80,0x00,0x07,0x80, ++0x80,0x00,0x07,0x80,0x80,0x00,0x07,0x70,0x80,0x00,0x07,0x70,0x80,0x00,0x07,0x94, ++0x80,0x00,0x56,0xb0,0x80,0x00,0x57,0x08,0x80,0x00,0x57,0x30,0x80,0x00,0x58,0x28, ++0x80,0x00,0x58,0xe0,0x80,0x00,0x59,0x88,0x80,0x00,0x59,0xfc,0x80,0x00,0x5b,0x08, ++0x80,0x00,0x5b,0x40,0x80,0x00,0x5b,0x54,0x80,0x00,0x5b,0x68,0x80,0x00,0x5c,0x50, ++0x80,0x00,0x5c,0x90,0x80,0x00,0x5d,0x44,0x80,0x00,0x5d,0x6c,0x80,0x00,0x56,0x70, ++0x80,0x00,0x5d,0xbc,0x80,0x00,0x64,0x48,0x80,0x00,0x64,0xc0,0x80,0x00,0x64,0xcc, ++0x80,0x00,0x64,0xd8,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60, ++0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60, ++0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60, ++0x80,0x00,0x64,0x60,0x80,0x00,0x64,0xe4,0x80,0x00,0x64,0xf0,0x80,0x00,0x64,0xfc, ++0x80,0x00,0x87,0xa4,0x80,0x00,0x87,0xa4,0x80,0x00,0x87,0xa4,0x80,0x00,0x87,0xd8, ++0x80,0x00,0x88,0x18,0x80,0x00,0x88,0x50,0x80,0x00,0x88,0x80,0x80,0x00,0x88,0xb0, ++0x80,0x00,0x88,0xc4,0x80,0x00,0x89,0x2c,0x80,0x00,0x89,0x40,0x80,0x00,0x89,0x7c, ++0x80,0x00,0x89,0x84,0x80,0x00,0x89,0xc0,0x80,0x00,0x89,0xd4,0x80,0x00,0x89,0xdc, ++0x80,0x00,0x89,0xe4,0x80,0x00,0x89,0xe4,0x80,0x00,0x89,0xe4,0x80,0x00,0x89,0xe4, ++0x80,0x00,0x8a,0x14,0x80,0x00,0x8a,0x28,0x80,0x00,0x8a,0x3c,0x80,0x00,0x86,0xe8, ++0x80,0x00,0x8d,0x68,0x80,0x00,0x8d,0x68,0x80,0x00,0x8d,0x68,0x80,0x00,0x8d,0x9c, ++0x80,0x00,0x8d,0xdc,0x80,0x00,0x8e,0x14,0x80,0x00,0x8e,0x44,0x80,0x00,0x8e,0x74, ++0x80,0x00,0x8e,0x88,0x80,0x00,0x8e,0xf0,0x80,0x00,0x8f,0x04,0x80,0x00,0x8f,0x40, ++0x80,0x00,0x8f,0x48,0x80,0x00,0x8f,0x84,0x80,0x00,0x8f,0x98,0x80,0x00,0x8f,0xa0, ++0x80,0x00,0x8f,0xa8,0x80,0x00,0x8f,0xa8,0x80,0x00,0x8f,0xa8,0x80,0x00,0x8f,0xa8, ++0x80,0x00,0x8f,0xd8,0x80,0x00,0x8f,0xec,0x80,0x00,0x90,0x00,0x80,0x00,0x8b,0x88, ++}; ++ ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r819xE_phy.c linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_phy.c +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_phy.c 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,3352 @@ ++#include "r8192E.h" ++#include "r8192E_hw.h" ++#include "r819xE_phyreg.h" ++#include "r8190_rtl8256.h" ++#include "r819xE_phy.h" ++#include "r8192E_dm.h" ++#ifdef ENABLE_DOT11D ++#include "dot11d.h" ++#endif ++static u32 RF_CHANNEL_TABLE_ZEBRA[] = { ++ 0, ++ 0x085c, //2412 1 ++ 0x08dc, //2417 2 ++ 0x095c, //2422 3 ++ 0x09dc, //2427 4 ++ 0x0a5c, //2432 5 ++ 0x0adc, //2437 6 ++ 0x0b5c, //2442 7 ++ 0x0bdc, //2447 8 ++ 0x0c5c, //2452 9 ++ 0x0cdc, //2457 10 ++ 0x0d5c, //2462 11 ++ 0x0ddc, //2467 12 ++ 0x0e5c, //2472 13 ++ 0x0f72, //2484 ++}; ++#ifdef RTL8190P ++u32 Rtl8190PciMACPHY_Array[] = { ++0x03c,0xffff0000,0x00000f0f, ++0x340,0xffffffff,0x161a1a1a, ++0x344,0xffffffff,0x12121416, ++0x348,0x0000ffff,0x00001818, ++0x12c,0xffffffff,0x04000802, ++0x318,0x00000fff,0x00000800, ++}; ++u32 Rtl8190PciMACPHY_Array_PG[] = { ++0x03c,0xffff0000,0x00000f0f, ++0x340,0xffffffff,0x0a0c0d0f, ++0x344,0xffffffff,0x06070809, ++0x344,0xffffffff,0x06070809, ++0x348,0x0000ffff,0x00000000, ++0x12c,0xffffffff,0x04000802, ++0x318,0x00000fff,0x00000800, ++}; ++ ++u32 Rtl8190PciAGCTAB_Array[AGCTAB_ArrayLength] = { ++0xc78,0x7d000001, ++0xc78,0x7d010001, ++0xc78,0x7d020001, ++0xc78,0x7d030001, ++0xc78,0x7c040001, ++0xc78,0x7b050001, ++0xc78,0x7a060001, ++0xc78,0x79070001, ++0xc78,0x78080001, ++0xc78,0x77090001, ++0xc78,0x760a0001, ++0xc78,0x750b0001, ++0xc78,0x740c0001, ++0xc78,0x730d0001, ++0xc78,0x720e0001, ++0xc78,0x710f0001, ++0xc78,0x70100001, ++0xc78,0x6f110001, ++0xc78,0x6e120001, ++0xc78,0x6d130001, ++0xc78,0x6c140001, ++0xc78,0x6b150001, ++0xc78,0x6a160001, ++0xc78,0x69170001, ++0xc78,0x68180001, ++0xc78,0x67190001, ++0xc78,0x661a0001, ++0xc78,0x651b0001, ++0xc78,0x641c0001, ++0xc78,0x491d0001, ++0xc78,0x481e0001, ++0xc78,0x471f0001, ++0xc78,0x46200001, ++0xc78,0x45210001, ++0xc78,0x44220001, ++0xc78,0x43230001, ++0xc78,0x28240001, ++0xc78,0x27250001, ++0xc78,0x26260001, ++0xc78,0x25270001, ++0xc78,0x24280001, ++0xc78,0x23290001, ++0xc78,0x222a0001, ++0xc78,0x212b0001, ++0xc78,0x202c0001, ++0xc78,0x0a2d0001, ++0xc78,0x082e0001, ++0xc78,0x062f0001, ++0xc78,0x05300001, ++0xc78,0x04310001, ++0xc78,0x03320001, ++0xc78,0x02330001, ++0xc78,0x01340001, ++0xc78,0x00350001, ++0xc78,0x00360001, ++0xc78,0x00370001, ++0xc78,0x00380001, ++0xc78,0x00390001, ++0xc78,0x003a0001, ++0xc78,0x003b0001, ++0xc78,0x003c0001, ++0xc78,0x003d0001, ++0xc78,0x003e0001, ++0xc78,0x003f0001, ++0xc78,0x7d400001, ++0xc78,0x7d410001, ++0xc78,0x7d420001, ++0xc78,0x7d430001, ++0xc78,0x7c440001, ++0xc78,0x7b450001, ++0xc78,0x7a460001, ++0xc78,0x79470001, ++0xc78,0x78480001, ++0xc78,0x77490001, ++0xc78,0x764a0001, ++0xc78,0x754b0001, ++0xc78,0x744c0001, ++0xc78,0x734d0001, ++0xc78,0x724e0001, ++0xc78,0x714f0001, ++0xc78,0x70500001, ++0xc78,0x6f510001, ++0xc78,0x6e520001, ++0xc78,0x6d530001, ++0xc78,0x6c540001, ++0xc78,0x6b550001, ++0xc78,0x6a560001, ++0xc78,0x69570001, ++0xc78,0x68580001, ++0xc78,0x67590001, ++0xc78,0x665a0001, ++0xc78,0x655b0001, ++0xc78,0x645c0001, ++0xc78,0x495d0001, ++0xc78,0x485e0001, ++0xc78,0x475f0001, ++0xc78,0x46600001, ++0xc78,0x45610001, ++0xc78,0x44620001, ++0xc78,0x43630001, ++0xc78,0x28640001, ++0xc78,0x27650001, ++0xc78,0x26660001, ++0xc78,0x25670001, ++0xc78,0x24680001, ++0xc78,0x23690001, ++0xc78,0x226a0001, ++0xc78,0x216b0001, ++0xc78,0x206c0001, ++0xc78,0x0a6d0001, ++0xc78,0x086e0001, ++0xc78,0x066f0001, ++0xc78,0x05700001, ++0xc78,0x04710001, ++0xc78,0x03720001, ++0xc78,0x02730001, ++0xc78,0x01740001, ++0xc78,0x00750001, ++0xc78,0x00760001, ++0xc78,0x00770001, ++0xc78,0x00780001, ++0xc78,0x00790001, ++0xc78,0x007a0001, ++0xc78,0x007b0001, ++0xc78,0x007c0001, ++0xc78,0x007d0001, ++0xc78,0x007e0001, ++0xc78,0x007f0001, ++0xc78,0x3600001e, ++0xc78,0x3601001e, ++0xc78,0x3602001e, ++0xc78,0x3603001e, ++0xc78,0x3604001e, ++0xc78,0x3605001e, ++0xc78,0x3a06001e, ++0xc78,0x3c07001e, ++0xc78,0x3e08001e, ++0xc78,0x4209001e, ++0xc78,0x430a001e, ++0xc78,0x450b001e, ++0xc78,0x470c001e, ++0xc78,0x480d001e, ++0xc78,0x490e001e, ++0xc78,0x4b0f001e, ++0xc78,0x4c10001e, ++0xc78,0x4d11001e, ++0xc78,0x4d12001e, ++0xc78,0x4e13001e, ++0xc78,0x4f14001e, ++0xc78,0x5015001e, ++0xc78,0x5116001e, ++0xc78,0x5117001e, ++0xc78,0x5218001e, ++0xc78,0x5219001e, ++0xc78,0x531a001e, ++0xc78,0x541b001e, ++0xc78,0x541c001e, ++0xc78,0x551d001e, ++0xc78,0x561e001e, ++0xc78,0x561f001e, ++0xc78,0x5720001e, ++0xc78,0x5821001e, ++0xc78,0x5822001e, ++0xc78,0x5923001e, ++0xc78,0x5924001e, ++0xc78,0x5a25001e, ++0xc78,0x5b26001e, ++0xc78,0x5b27001e, ++0xc78,0x5c28001e, ++0xc78,0x5c29001e, ++0xc78,0x5d2a001e, ++0xc78,0x5d2b001e, ++0xc78,0x5e2c001e, ++0xc78,0x5e2d001e, ++0xc78,0x5f2e001e, ++0xc78,0x602f001e, ++0xc78,0x6030001e, ++0xc78,0x6131001e, ++0xc78,0x6132001e, ++0xc78,0x6233001e, ++0xc78,0x6234001e, ++0xc78,0x6335001e, ++0xc78,0x6336001e, ++0xc78,0x6437001e, ++0xc78,0x6538001e, ++0xc78,0x6639001e, ++0xc78,0x663a001e, ++0xc78,0x673b001e, ++0xc78,0x683c001e, ++0xc78,0x693d001e, ++0xc78,0x6a3e001e, ++0xc78,0x6b3f001e, ++}; ++ ++u32 Rtl8190PciPHY_REGArray[PHY_REGArrayLength] = { ++0x800,0x00050060, ++0x804,0x00000005, ++0x808,0x0000fc00, ++0x80c,0x0000001c, ++0x810,0x801010aa, ++0x814,0x000908c0, ++0x818,0x00000000, ++0x81c,0x00000000, ++0x820,0x00000004, ++0x824,0x00690000, ++0x828,0x00000004, ++0x82c,0x00e90000, ++0x830,0x00000004, ++0x834,0x00690000, ++0x838,0x00000004, ++0x83c,0x00e90000, ++0x840,0x00000000, ++0x844,0x00000000, ++0x848,0x00000000, ++0x84c,0x00000000, ++0x850,0x00000000, ++0x854,0x00000000, ++0x858,0x65a965a9, ++0x85c,0x65a965a9, ++0x860,0x001f0010, ++0x864,0x007f0010, ++0x868,0x001f0010, ++0x86c,0x007f0010, ++0x870,0x0f100f70, ++0x874,0x0f100f70, ++0x878,0x00000000, ++0x87c,0x00000000, ++0x880,0x5c385eb8, ++0x884,0x6357060d, ++0x888,0x0460c341, ++0x88c,0x0000ff00, ++0x890,0x00000000, ++0x894,0xfffffffe, ++0x898,0x4c42382f, ++0x89c,0x00656056, ++0x8b0,0x00000000, ++0x8e0,0x00000000, ++0x8e4,0x00000000, ++0x900,0x00000000, ++0x904,0x00000023, ++0x908,0x00000000, ++0x90c,0x35541545, ++0xa00,0x00d0c7d8, ++0xa04,0xab1f0008, ++0xa08,0x80cd8300, ++0xa0c,0x2e62740f, ++0xa10,0x95009b78, ++0xa14,0x11145008, ++0xa18,0x00881117, ++0xa1c,0x89140fa0, ++0xa20,0x1a1b0000, ++0xa24,0x090e1317, ++0xa28,0x00000204, ++0xa2c,0x00000000, ++0xc00,0x00000040, ++0xc04,0x0000500f, ++0xc08,0x000000e4, ++0xc0c,0x6c6c6c6c, ++0xc10,0x08000000, ++0xc14,0x40000100, ++0xc18,0x08000000, ++0xc1c,0x40000100, ++0xc20,0x08000000, ++0xc24,0x40000100, ++0xc28,0x08000000, ++0xc2c,0x40000100, ++0xc30,0x6de9ac44, ++0xc34,0x164052cd, ++0xc38,0x00070a14, ++0xc3c,0x0a969764, ++0xc40,0x1f7c403f, ++0xc44,0x000100b7, ++0xc48,0xec020000, ++0xc4c,0x00000300, ++0xc50,0x69543420, ++0xc54,0x433c0094, ++0xc58,0x69543420, ++0xc5c,0x433c0094, ++0xc60,0x69543420, ++0xc64,0x433c0094, ++0xc68,0x69543420, ++0xc6c,0x433c0094, ++0xc70,0x2c7f000d, ++0xc74,0x0186175b, ++0xc78,0x0000001f, ++0xc7c,0x00b91612, ++0xc80,0x40000100, ++0xc84,0x00000000, ++0xc88,0x40000100, ++0xc8c,0x08000000, ++0xc90,0x40000100, ++0xc94,0x00000000, ++0xc98,0x40000100, ++0xc9c,0x00000000, ++0xca0,0x00492492, ++0xca4,0x00000000, ++0xca8,0x00000000, ++0xcac,0x00000000, ++0xcb0,0x00000000, ++0xcb4,0x00000000, ++0xcb8,0x00000000, ++0xcbc,0x00492492, ++0xcc0,0x00000000, ++0xcc4,0x00000000, ++0xcc8,0x00000000, ++0xccc,0x00000000, ++0xcd0,0x00000000, ++0xcd4,0x00000000, ++0xcd8,0x64b22427, ++0xcdc,0x00766932, ++0xce0,0x00222222, ++0xd00,0x00000740, ++0xd04,0x0000040f, ++0xd08,0x0000803f, ++0xd0c,0x00000001, ++0xd10,0xa0633333, ++0xd14,0x33333c63, ++0xd18,0x6a8f5b6b, ++0xd1c,0x00000000, ++0xd20,0x00000000, ++0xd24,0x00000000, ++0xd28,0x00000000, ++0xd2c,0xcc979975, ++0xd30,0x00000000, ++0xd34,0x00000000, ++0xd38,0x00000000, ++0xd3c,0x00027293, ++0xd40,0x00000000, ++0xd44,0x00000000, ++0xd48,0x00000000, ++0xd4c,0x00000000, ++0xd50,0x6437140a, ++0xd54,0x024dbd02, ++0xd58,0x00000000, ++0xd5c,0x14032064, ++}; ++u32 Rtl8190PciPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = { ++0x800,0x00050060, ++0x804,0x00000004, ++0x808,0x0000fc00, ++0x80c,0x0000001c, ++0x810,0x801010aa, ++0x814,0x000908c0, ++0x818,0x00000000, ++0x81c,0x00000000, ++0x820,0x00000004, ++0x824,0x00690000, ++0x828,0x00000004, ++0x82c,0x00e90000, ++0x830,0x00000004, ++0x834,0x00690000, ++0x838,0x00000004, ++0x83c,0x00e90000, ++0x840,0x00000000, ++0x844,0x00000000, ++0x848,0x00000000, ++0x84c,0x00000000, ++0x850,0x00000000, ++0x854,0x00000000, ++0x858,0x65a965a9, ++0x85c,0x65a965a9, ++0x860,0x001f0000, ++0x864,0x007f0000, ++0x868,0x001f0010, ++0x86c,0x007f0010, ++0x870,0x0f100f70, ++0x874,0x0f100f70, ++0x878,0x00000000, ++0x87c,0x00000000, ++0x880,0x5c385898, ++0x884,0x6357060d, ++0x888,0x0460c341, ++0x88c,0x0000fc00, ++0x890,0x00000000, ++0x894,0xfffffffe, ++0x898,0x4c42382f, ++0x89c,0x00656056, ++0x8b0,0x00000000, ++0x8e0,0x00000000, ++0x8e4,0x00000000, ++0x900,0x00000000, ++0x904,0x00000023, ++0x908,0x00000000, ++0x90c,0x34441444, ++0xa00,0x00d0c7d8, ++0xa04,0x2b1f0008, ++0xa08,0x80cd8300, ++0xa0c,0x2e62740f, ++0xa10,0x95009b78, ++0xa14,0x11145008, ++0xa18,0x00881117, ++0xa1c,0x89140fa0, ++0xa20,0x1a1b0000, ++0xa24,0x090e1317, ++0xa28,0x00000204, ++0xa2c,0x00000000, ++0xc00,0x00000040, ++0xc04,0x0000500c, ++0xc08,0x000000e4, ++0xc0c,0x6c6c6c6c, ++0xc10,0x08000000, ++0xc14,0x40000100, ++0xc18,0x08000000, ++0xc1c,0x40000100, ++0xc20,0x08000000, ++0xc24,0x40000100, ++0xc28,0x08000000, ++0xc2c,0x40000100, ++0xc30,0x6de9ac44, ++0xc34,0x164052cd, ++0xc38,0x00070a14, ++0xc3c,0x0a969764, ++0xc40,0x1f7c403f, ++0xc44,0x000100b7, ++0xc48,0xec020000, ++0xc4c,0x00000300, ++0xc50,0x69543420, ++0xc54,0x433c0094, ++0xc58,0x69543420, ++0xc5c,0x433c0094, ++0xc60,0x69543420, ++0xc64,0x433c0094, ++0xc68,0x69543420, ++0xc6c,0x433c0094, ++0xc70,0x2c7f000d, ++0xc74,0x0186175b, ++0xc78,0x0000001f, ++0xc7c,0x00b91612, ++0xc80,0x40000100, ++0xc84,0x00000000, ++0xc88,0x40000100, ++0xc8c,0x08000000, ++0xc90,0x40000100, ++0xc94,0x00000000, ++0xc98,0x40000100, ++0xc9c,0x00000000, ++0xca0,0x00492492, ++0xca4,0x00000000, ++0xca8,0x00000000, ++0xcac,0x00000000, ++0xcb0,0x00000000, ++0xcb4,0x00000000, ++0xcb8,0x00000000, ++0xcbc,0x00492492, ++0xcc0,0x00000000, ++0xcc4,0x00000000, ++0xcc8,0x00000000, ++0xccc,0x00000000, ++0xcd0,0x00000000, ++0xcd4,0x00000000, ++0xcd8,0x64b22427, ++0xcdc,0x00766932, ++0xce0,0x00222222, ++0xd00,0x00000740, ++0xd04,0x0000040c, ++0xd08,0x0000803f, ++0xd0c,0x00000001, ++0xd10,0xa0633333, ++0xd14,0x33333c63, ++0xd18,0x6a8f5b6b, ++0xd1c,0x00000000, ++0xd20,0x00000000, ++0xd24,0x00000000, ++0xd28,0x00000000, ++0xd2c,0xcc979975, ++0xd30,0x00000000, ++0xd34,0x00000000, ++0xd38,0x00000000, ++0xd3c,0x00027293, ++0xd40,0x00000000, ++0xd44,0x00000000, ++0xd48,0x00000000, ++0xd4c,0x00000000, ++0xd50,0x6437140a, ++0xd54,0x024dbd02, ++0xd58,0x00000000, ++0xd5c,0x14032064, ++}; ++ ++u32 Rtl8190PciRadioA_Array[RadioA_ArrayLength] = { ++0x019,0x00000003, ++0x000,0x000000bf, ++0x001,0x00000ee0, ++0x002,0x0000004c, ++0x003,0x000007f1, ++0x004,0x00000975, ++0x005,0x00000c58, ++0x006,0x00000ae6, ++0x007,0x000000ca, ++0x008,0x00000e1c, ++0x009,0x000007f0, ++0x00a,0x000009d0, ++0x00b,0x000001ba, ++0x00c,0x00000240, ++0x00e,0x00000020, ++0x00f,0x00000990, ++0x012,0x00000806, ++0x014,0x000005ab, ++0x015,0x00000f80, ++0x016,0x00000020, ++0x017,0x00000597, ++0x018,0x0000050a, ++0x01a,0x00000f80, ++0x01b,0x00000f5e, ++0x01c,0x00000008, ++0x01d,0x00000607, ++0x01e,0x000006cc, ++0x01f,0x00000000, ++0x020,0x000001a5, ++0x01f,0x00000001, ++0x020,0x00000165, ++0x01f,0x00000002, ++0x020,0x000000c6, ++0x01f,0x00000003, ++0x020,0x00000086, ++0x01f,0x00000004, ++0x020,0x00000046, ++0x01f,0x00000005, ++0x020,0x000001e6, ++0x01f,0x00000006, ++0x020,0x000001a6, ++0x01f,0x00000007, ++0x020,0x00000166, ++0x01f,0x00000008, ++0x020,0x000000c7, ++0x01f,0x00000009, ++0x020,0x00000087, ++0x01f,0x0000000a, ++0x020,0x000000f7, ++0x01f,0x0000000b, ++0x020,0x000000d7, ++0x01f,0x0000000c, ++0x020,0x000000b7, ++0x01f,0x0000000d, ++0x020,0x00000097, ++0x01f,0x0000000e, ++0x020,0x00000077, ++0x01f,0x0000000f, ++0x020,0x00000057, ++0x01f,0x00000010, ++0x020,0x00000037, ++0x01f,0x00000011, ++0x020,0x000000fb, ++0x01f,0x00000012, ++0x020,0x000000db, ++0x01f,0x00000013, ++0x020,0x000000bb, ++0x01f,0x00000014, ++0x020,0x000000ff, ++0x01f,0x00000015, ++0x020,0x000000e3, ++0x01f,0x00000016, ++0x020,0x000000c3, ++0x01f,0x00000017, ++0x020,0x000000a3, ++0x01f,0x00000018, ++0x020,0x00000083, ++0x01f,0x00000019, ++0x020,0x00000063, ++0x01f,0x0000001a, ++0x020,0x00000043, ++0x01f,0x0000001b, ++0x020,0x00000023, ++0x01f,0x0000001c, ++0x020,0x00000003, ++0x01f,0x0000001d, ++0x020,0x000001e3, ++0x01f,0x0000001e, ++0x020,0x000001c3, ++0x01f,0x0000001f, ++0x020,0x000001a3, ++0x01f,0x00000020, ++0x020,0x00000183, ++0x01f,0x00000021, ++0x020,0x00000163, ++0x01f,0x00000022, ++0x020,0x00000143, ++0x01f,0x00000023, ++0x020,0x00000123, ++0x01f,0x00000024, ++0x020,0x00000103, ++0x023,0x00000203, ++0x024,0x00000200, ++0x00b,0x000001ba, ++0x02c,0x000003d7, ++0x02d,0x00000ff0, ++0x000,0x00000037, ++0x004,0x00000160, ++0x007,0x00000080, ++0x002,0x0000088d, ++0x0fe,0x00000000, ++0x0fe,0x00000000, ++0x016,0x00000200, ++0x016,0x00000380, ++0x016,0x00000020, ++0x016,0x000001a0, ++0x000,0x000000bf, ++0x00d,0x0000001f, ++0x00d,0x00000c9f, ++0x002,0x0000004d, ++0x000,0x00000cbf, ++0x004,0x00000975, ++0x007,0x00000700, ++}; ++u32 Rtl8190PciRadioB_Array[RadioB_ArrayLength] = { ++0x019,0x00000003, ++0x000,0x000000bf, ++0x001,0x000006e0, ++0x002,0x0000004c, ++0x003,0x000007f1, ++0x004,0x00000975, ++0x005,0x00000c58, ++0x006,0x00000ae6, ++0x007,0x000000ca, ++0x008,0x00000e1c, ++0x000,0x000000b7, ++0x00a,0x00000850, ++0x000,0x000000bf, ++0x00b,0x000001ba, ++0x00c,0x00000240, ++0x00e,0x00000020, ++0x015,0x00000f80, ++0x016,0x00000020, ++0x017,0x00000597, ++0x018,0x0000050a, ++0x01a,0x00000e00, ++0x01b,0x00000f5e, ++0x01d,0x00000607, ++0x01e,0x000006cc, ++0x00b,0x000001ba, ++0x023,0x00000203, ++0x024,0x00000200, ++0x000,0x00000037, ++0x004,0x00000160, ++0x016,0x00000200, ++0x016,0x00000380, ++0x016,0x00000020, ++0x016,0x000001a0, ++0x00d,0x00000ccc, ++0x000,0x000000bf, ++0x002,0x0000004d, ++0x000,0x00000cbf, ++0x004,0x00000975, ++0x007,0x00000700, ++}; ++u32 Rtl8190PciRadioC_Array[RadioC_ArrayLength] = { ++0x019,0x00000003, ++0x000,0x000000bf, ++0x001,0x00000ee0, ++0x002,0x0000004c, ++0x003,0x000007f1, ++0x004,0x00000975, ++0x005,0x00000c58, ++0x006,0x00000ae6, ++0x007,0x000000ca, ++0x008,0x00000e1c, ++0x009,0x000007f0, ++0x00a,0x000009d0, ++0x00b,0x000001ba, ++0x00c,0x00000240, ++0x00e,0x00000020, ++0x00f,0x00000990, ++0x012,0x00000806, ++0x014,0x000005ab, ++0x015,0x00000f80, ++0x016,0x00000020, ++0x017,0x00000597, ++0x018,0x0000050a, ++0x01a,0x00000f80, ++0x01b,0x00000f5e, ++0x01c,0x00000008, ++0x01d,0x00000607, ++0x01e,0x000006cc, ++0x01f,0x00000000, ++0x020,0x000001a5, ++0x01f,0x00000001, ++0x020,0x00000165, ++0x01f,0x00000002, ++0x020,0x000000c6, ++0x01f,0x00000003, ++0x020,0x00000086, ++0x01f,0x00000004, ++0x020,0x00000046, ++0x01f,0x00000005, ++0x020,0x000001e6, ++0x01f,0x00000006, ++0x020,0x000001a6, ++0x01f,0x00000007, ++0x020,0x00000166, ++0x01f,0x00000008, ++0x020,0x000000c7, ++0x01f,0x00000009, ++0x020,0x00000087, ++0x01f,0x0000000a, ++0x020,0x000000f7, ++0x01f,0x0000000b, ++0x020,0x000000d7, ++0x01f,0x0000000c, ++0x020,0x000000b7, ++0x01f,0x0000000d, ++0x020,0x00000097, ++0x01f,0x0000000e, ++0x020,0x00000077, ++0x01f,0x0000000f, ++0x020,0x00000057, ++0x01f,0x00000010, ++0x020,0x00000037, ++0x01f,0x00000011, ++0x020,0x000000fb, ++0x01f,0x00000012, ++0x020,0x000000db, ++0x01f,0x00000013, ++0x020,0x000000bb, ++0x01f,0x00000014, ++0x020,0x000000ff, ++0x01f,0x00000015, ++0x020,0x000000e3, ++0x01f,0x00000016, ++0x020,0x000000c3, ++0x01f,0x00000017, ++0x020,0x000000a3, ++0x01f,0x00000018, ++0x020,0x00000083, ++0x01f,0x00000019, ++0x020,0x00000063, ++0x01f,0x0000001a, ++0x020,0x00000043, ++0x01f,0x0000001b, ++0x020,0x00000023, ++0x01f,0x0000001c, ++0x020,0x00000003, ++0x01f,0x0000001d, ++0x020,0x000001e3, ++0x01f,0x0000001e, ++0x020,0x000001c3, ++0x01f,0x0000001f, ++0x020,0x000001a3, ++0x01f,0x00000020, ++0x020,0x00000183, ++0x01f,0x00000021, ++0x020,0x00000163, ++0x01f,0x00000022, ++0x020,0x00000143, ++0x01f,0x00000023, ++0x020,0x00000123, ++0x01f,0x00000024, ++0x020,0x00000103, ++0x023,0x00000203, ++0x024,0x00000200, ++0x00b,0x000001ba, ++0x02c,0x000003d7, ++0x02d,0x00000ff0, ++0x000,0x00000037, ++0x004,0x00000160, ++0x007,0x00000080, ++0x002,0x0000088d, ++0x0fe,0x00000000, ++0x0fe,0x00000000, ++0x016,0x00000200, ++0x016,0x00000380, ++0x016,0x00000020, ++0x016,0x000001a0, ++0x000,0x000000bf, ++0x00d,0x0000001f, ++0x00d,0x00000c9f, ++0x002,0x0000004d, ++0x000,0x00000cbf, ++0x004,0x00000975, ++0x007,0x00000700, ++}; ++u32 Rtl8190PciRadioD_Array[RadioD_ArrayLength] = { ++0x019,0x00000003, ++0x000,0x000000bf, ++0x001,0x000006e0, ++0x002,0x0000004c, ++0x003,0x000007f1, ++0x004,0x00000975, ++0x005,0x00000c58, ++0x006,0x00000ae6, ++0x007,0x000000ca, ++0x008,0x00000e1c, ++0x000,0x000000b7, ++0x00a,0x00000850, ++0x000,0x000000bf, ++0x00b,0x000001ba, ++0x00c,0x00000240, ++0x00e,0x00000020, ++0x015,0x00000f80, ++0x016,0x00000020, ++0x017,0x00000597, ++0x018,0x0000050a, ++0x01a,0x00000e00, ++0x01b,0x00000f5e, ++0x01d,0x00000607, ++0x01e,0x000006cc, ++0x00b,0x000001ba, ++0x023,0x00000203, ++0x024,0x00000200, ++0x000,0x00000037, ++0x004,0x00000160, ++0x016,0x00000200, ++0x016,0x00000380, ++0x016,0x00000020, ++0x016,0x000001a0, ++0x00d,0x00000ccc, ++0x000,0x000000bf, ++0x002,0x0000004d, ++0x000,0x00000cbf, ++0x004,0x00000975, ++0x007,0x00000700, ++}; ++#endif ++#ifdef RTL8192E ++static u32 Rtl8192PciEMACPHY_Array[] = { ++0x03c,0xffff0000,0x00000f0f, ++0x340,0xffffffff,0x161a1a1a, ++0x344,0xffffffff,0x12121416, ++0x348,0x0000ffff,0x00001818, ++0x12c,0xffffffff,0x04000802, ++0x318,0x00000fff,0x00000100, ++}; ++static u32 Rtl8192PciEMACPHY_Array_PG[] = { ++0x03c,0xffff0000,0x00000f0f, ++0xe00,0xffffffff,0x06090909, ++0xe04,0xffffffff,0x00030306, ++0xe08,0x0000ff00,0x00000000, ++0xe10,0xffffffff,0x0a0c0d0f, ++0xe14,0xffffffff,0x06070809, ++0xe18,0xffffffff,0x0a0c0d0f, ++0xe1c,0xffffffff,0x06070809, ++0x12c,0xffffffff,0x04000802, ++0x318,0x00000fff,0x00000800, ++}; ++static u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLength] = { ++0xc78,0x7d000001, ++0xc78,0x7d010001, ++0xc78,0x7d020001, ++0xc78,0x7d030001, ++0xc78,0x7d040001, ++0xc78,0x7d050001, ++0xc78,0x7c060001, ++0xc78,0x7b070001, ++0xc78,0x7a080001, ++0xc78,0x79090001, ++0xc78,0x780a0001, ++0xc78,0x770b0001, ++0xc78,0x760c0001, ++0xc78,0x750d0001, ++0xc78,0x740e0001, ++0xc78,0x730f0001, ++0xc78,0x72100001, ++0xc78,0x71110001, ++0xc78,0x70120001, ++0xc78,0x6f130001, ++0xc78,0x6e140001, ++0xc78,0x6d150001, ++0xc78,0x6c160001, ++0xc78,0x6b170001, ++0xc78,0x6a180001, ++0xc78,0x69190001, ++0xc78,0x681a0001, ++0xc78,0x671b0001, ++0xc78,0x661c0001, ++0xc78,0x651d0001, ++0xc78,0x641e0001, ++0xc78,0x491f0001, ++0xc78,0x48200001, ++0xc78,0x47210001, ++0xc78,0x46220001, ++0xc78,0x45230001, ++0xc78,0x44240001, ++0xc78,0x43250001, ++0xc78,0x28260001, ++0xc78,0x27270001, ++0xc78,0x26280001, ++0xc78,0x25290001, ++0xc78,0x242a0001, ++0xc78,0x232b0001, ++0xc78,0x222c0001, ++0xc78,0x212d0001, ++0xc78,0x202e0001, ++0xc78,0x0a2f0001, ++0xc78,0x08300001, ++0xc78,0x06310001, ++0xc78,0x05320001, ++0xc78,0x04330001, ++0xc78,0x03340001, ++0xc78,0x02350001, ++0xc78,0x01360001, ++0xc78,0x00370001, ++0xc78,0x00380001, ++0xc78,0x00390001, ++0xc78,0x003a0001, ++0xc78,0x003b0001, ++0xc78,0x003c0001, ++0xc78,0x003d0001, ++0xc78,0x003e0001, ++0xc78,0x003f0001, ++0xc78,0x7d400001, ++0xc78,0x7d410001, ++0xc78,0x7d420001, ++0xc78,0x7d430001, ++0xc78,0x7d440001, ++0xc78,0x7d450001, ++0xc78,0x7c460001, ++0xc78,0x7b470001, ++0xc78,0x7a480001, ++0xc78,0x79490001, ++0xc78,0x784a0001, ++0xc78,0x774b0001, ++0xc78,0x764c0001, ++0xc78,0x754d0001, ++0xc78,0x744e0001, ++0xc78,0x734f0001, ++0xc78,0x72500001, ++0xc78,0x71510001, ++0xc78,0x70520001, ++0xc78,0x6f530001, ++0xc78,0x6e540001, ++0xc78,0x6d550001, ++0xc78,0x6c560001, ++0xc78,0x6b570001, ++0xc78,0x6a580001, ++0xc78,0x69590001, ++0xc78,0x685a0001, ++0xc78,0x675b0001, ++0xc78,0x665c0001, ++0xc78,0x655d0001, ++0xc78,0x645e0001, ++0xc78,0x495f0001, ++0xc78,0x48600001, ++0xc78,0x47610001, ++0xc78,0x46620001, ++0xc78,0x45630001, ++0xc78,0x44640001, ++0xc78,0x43650001, ++0xc78,0x28660001, ++0xc78,0x27670001, ++0xc78,0x26680001, ++0xc78,0x25690001, ++0xc78,0x246a0001, ++0xc78,0x236b0001, ++0xc78,0x226c0001, ++0xc78,0x216d0001, ++0xc78,0x206e0001, ++0xc78,0x0a6f0001, ++0xc78,0x08700001, ++0xc78,0x06710001, ++0xc78,0x05720001, ++0xc78,0x04730001, ++0xc78,0x03740001, ++0xc78,0x02750001, ++0xc78,0x01760001, ++0xc78,0x00770001, ++0xc78,0x00780001, ++0xc78,0x00790001, ++0xc78,0x007a0001, ++0xc78,0x007b0001, ++0xc78,0x007c0001, ++0xc78,0x007d0001, ++0xc78,0x007e0001, ++0xc78,0x007f0001, ++0xc78,0x2e00001e, ++0xc78,0x2e01001e, ++0xc78,0x2e02001e, ++0xc78,0x2e03001e, ++0xc78,0x2e04001e, ++0xc78,0x2e05001e, ++0xc78,0x3006001e, ++0xc78,0x3407001e, ++0xc78,0x3908001e, ++0xc78,0x3c09001e, ++0xc78,0x3f0a001e, ++0xc78,0x420b001e, ++0xc78,0x440c001e, ++0xc78,0x450d001e, ++0xc78,0x460e001e, ++0xc78,0x460f001e, ++0xc78,0x4710001e, ++0xc78,0x4811001e, ++0xc78,0x4912001e, ++0xc78,0x4a13001e, ++0xc78,0x4b14001e, ++0xc78,0x4b15001e, ++0xc78,0x4c16001e, ++0xc78,0x4d17001e, ++0xc78,0x4e18001e, ++0xc78,0x4f19001e, ++0xc78,0x4f1a001e, ++0xc78,0x501b001e, ++0xc78,0x511c001e, ++0xc78,0x521d001e, ++0xc78,0x521e001e, ++0xc78,0x531f001e, ++0xc78,0x5320001e, ++0xc78,0x5421001e, ++0xc78,0x5522001e, ++0xc78,0x5523001e, ++0xc78,0x5624001e, ++0xc78,0x5725001e, ++0xc78,0x5726001e, ++0xc78,0x5827001e, ++0xc78,0x5828001e, ++0xc78,0x5929001e, ++0xc78,0x592a001e, ++0xc78,0x5a2b001e, ++0xc78,0x5b2c001e, ++0xc78,0x5c2d001e, ++0xc78,0x5c2e001e, ++0xc78,0x5d2f001e, ++0xc78,0x5e30001e, ++0xc78,0x5f31001e, ++0xc78,0x6032001e, ++0xc78,0x6033001e, ++0xc78,0x6134001e, ++0xc78,0x6235001e, ++0xc78,0x6336001e, ++0xc78,0x6437001e, ++0xc78,0x6438001e, ++0xc78,0x6539001e, ++0xc78,0x663a001e, ++0xc78,0x673b001e, ++0xc78,0x673c001e, ++0xc78,0x683d001e, ++0xc78,0x693e001e, ++0xc78,0x6a3f001e, ++}; ++static u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLength] = { ++0x0, }; ++static u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = { ++0x800,0x00000000, ++0x804,0x00000001, ++0x808,0x0000fc00, ++0x80c,0x0000001c, ++0x810,0x801010aa, ++0x814,0x008514d0, ++0x818,0x00000040, ++0x81c,0x00000000, ++0x820,0x00000004, ++0x824,0x00690000, ++0x828,0x00000004, ++0x82c,0x00e90000, ++0x830,0x00000004, ++0x834,0x00690000, ++0x838,0x00000004, ++0x83c,0x00e90000, ++0x840,0x00000000, ++0x844,0x00000000, ++0x848,0x00000000, ++0x84c,0x00000000, ++0x850,0x00000000, ++0x854,0x00000000, ++0x858,0x65a965a9, ++0x85c,0x65a965a9, ++0x860,0x001f0010, ++0x864,0x007f0010, ++0x868,0x001f0010, ++0x86c,0x007f0010, ++0x870,0x0f100f70, ++0x874,0x0f100f70, ++0x878,0x00000000, ++0x87c,0x00000000, ++0x880,0x6870e36c, ++0x884,0xe3573600, ++0x888,0x4260c340, ++0x88c,0x0000ff00, ++0x890,0x00000000, ++0x894,0xfffffffe, ++0x898,0x4c42382f, ++0x89c,0x00656056, ++0x8b0,0x00000000, ++0x8e0,0x00000000, ++0x8e4,0x00000000, ++0x900,0x00000000, ++0x904,0x00000023, ++0x908,0x00000000, ++0x90c,0x31121311, ++0xa00,0x00d0c7d8, ++0xa04,0x811f0008, ++0xa08,0x80cd8300, ++0xa0c,0x2e62740f, ++0xa10,0x95009b78, ++0xa14,0x11145008, ++0xa18,0x00881117, ++0xa1c,0x89140fa0, ++0xa20,0x1a1b0000, ++0xa24,0x090e1317, ++0xa28,0x00000204, ++0xa2c,0x00000000, ++0xc00,0x00000040, ++0xc04,0x00005433, ++0xc08,0x000000e4, ++0xc0c,0x6c6c6c6c, ++0xc10,0x08800000, ++0xc14,0x40000100, ++0xc18,0x08000000, ++0xc1c,0x40000100, ++0xc20,0x08000000, ++0xc24,0x40000100, ++0xc28,0x08000000, ++0xc2c,0x40000100, ++0xc30,0x6de9ac44, ++0xc34,0x465c52cd, ++0xc38,0x497f5994, ++0xc3c,0x0a969764, ++0xc40,0x1f7c403f, ++0xc44,0x000100b7, ++0xc48,0xec020000, ++0xc4c,0x00000300, ++0xc50,0x69543420, ++0xc54,0x433c0094, ++0xc58,0x69543420, ++0xc5c,0x433c0094, ++0xc60,0x69543420, ++0xc64,0x433c0094, ++0xc68,0x69543420, ++0xc6c,0x433c0094, ++0xc70,0x2c7f000d, ++0xc74,0x0186175b, ++0xc78,0x0000001f, ++0xc7c,0x00b91612, ++0xc80,0x40000100, ++0xc84,0x20000000, ++0xc88,0x40000100, ++0xc8c,0x20200000, ++0xc90,0x40000100, ++0xc94,0x00000000, ++0xc98,0x40000100, ++0xc9c,0x00000000, ++0xca0,0x00492492, ++0xca4,0x00000000, ++0xca8,0x00000000, ++0xcac,0x00000000, ++0xcb0,0x00000000, ++0xcb4,0x00000000, ++0xcb8,0x00000000, ++0xcbc,0x00492492, ++0xcc0,0x00000000, ++0xcc4,0x00000000, ++0xcc8,0x00000000, ++0xccc,0x00000000, ++0xcd0,0x00000000, ++0xcd4,0x00000000, ++0xcd8,0x64b22427, ++0xcdc,0x00766932, ++0xce0,0x00222222, ++0xd00,0x00000750, ++0xd04,0x00000403, ++0xd08,0x0000907f, ++0xd0c,0x00000001, ++0xd10,0xa0633333, ++0xd14,0x33333c63, ++0xd18,0x6a8f5b6b, ++0xd1c,0x00000000, ++0xd20,0x00000000, ++0xd24,0x00000000, ++0xd28,0x00000000, ++0xd2c,0xcc979975, ++0xd30,0x00000000, ++0xd34,0x00000000, ++0xd38,0x00000000, ++0xd3c,0x00027293, ++0xd40,0x00000000, ++0xd44,0x00000000, ++0xd48,0x00000000, ++0xd4c,0x00000000, ++0xd50,0x6437140a, ++0xd54,0x024dbd02, ++0xd58,0x00000000, ++0xd5c,0x04032064, ++0xe00,0x161a1a1a, ++0xe04,0x12121416, ++0xe08,0x00001800, ++0xe0c,0x00000000, ++0xe10,0x161a1a1a, ++0xe14,0x12121416, ++0xe18,0x161a1a1a, ++0xe1c,0x12121416, ++}; ++static u32 Rtl8192PciERadioA_Array[RadioA_ArrayLength] = { ++0x019,0x00000003, ++0x000,0x000000bf, ++0x001,0x00000ee0, ++0x002,0x0000004c, ++0x003,0x000007f1, ++0x004,0x00000975, ++0x005,0x00000c58, ++0x006,0x00000ae6, ++0x007,0x000000ca, ++0x008,0x00000e1c, ++0x009,0x000007f0, ++0x00a,0x000009d0, ++0x00b,0x000001ba, ++0x00c,0x00000240, ++0x00e,0x00000020, ++0x00f,0x00000990, ++0x012,0x00000806, ++0x014,0x000005ab, ++0x015,0x00000f80, ++0x016,0x00000020, ++0x017,0x00000597, ++0x018,0x0000050a, ++0x01a,0x00000f80, ++0x01b,0x00000f5e, ++0x01c,0x00000008, ++0x01d,0x00000607, ++0x01e,0x000006cc, ++0x01f,0x00000000, ++0x020,0x000001a5, ++0x01f,0x00000001, ++0x020,0x00000165, ++0x01f,0x00000002, ++0x020,0x000000c6, ++0x01f,0x00000003, ++0x020,0x00000086, ++0x01f,0x00000004, ++0x020,0x00000046, ++0x01f,0x00000005, ++0x020,0x000001e6, ++0x01f,0x00000006, ++0x020,0x000001a6, ++0x01f,0x00000007, ++0x020,0x00000166, ++0x01f,0x00000008, ++0x020,0x000000c7, ++0x01f,0x00000009, ++0x020,0x00000087, ++0x01f,0x0000000a, ++0x020,0x000000f7, ++0x01f,0x0000000b, ++0x020,0x000000d7, ++0x01f,0x0000000c, ++0x020,0x000000b7, ++0x01f,0x0000000d, ++0x020,0x00000097, ++0x01f,0x0000000e, ++0x020,0x00000077, ++0x01f,0x0000000f, ++0x020,0x00000057, ++0x01f,0x00000010, ++0x020,0x00000037, ++0x01f,0x00000011, ++0x020,0x000000fb, ++0x01f,0x00000012, ++0x020,0x000000db, ++0x01f,0x00000013, ++0x020,0x000000bb, ++0x01f,0x00000014, ++0x020,0x000000ff, ++0x01f,0x00000015, ++0x020,0x000000e3, ++0x01f,0x00000016, ++0x020,0x000000c3, ++0x01f,0x00000017, ++0x020,0x000000a3, ++0x01f,0x00000018, ++0x020,0x00000083, ++0x01f,0x00000019, ++0x020,0x00000063, ++0x01f,0x0000001a, ++0x020,0x00000043, ++0x01f,0x0000001b, ++0x020,0x00000023, ++0x01f,0x0000001c, ++0x020,0x00000003, ++0x01f,0x0000001d, ++0x020,0x000001e3, ++0x01f,0x0000001e, ++0x020,0x000001c3, ++0x01f,0x0000001f, ++0x020,0x000001a3, ++0x01f,0x00000020, ++0x020,0x00000183, ++0x01f,0x00000021, ++0x020,0x00000163, ++0x01f,0x00000022, ++0x020,0x00000143, ++0x01f,0x00000023, ++0x020,0x00000123, ++0x01f,0x00000024, ++0x020,0x00000103, ++0x023,0x00000203, ++0x024,0x00000100, ++0x00b,0x000001ba, ++0x02c,0x000003d7, ++0x02d,0x00000ff0, ++0x000,0x00000037, ++0x004,0x00000160, ++0x007,0x00000080, ++0x002,0x0000088d, ++0x0fe,0x00000000, ++0x0fe,0x00000000, ++0x016,0x00000200, ++0x016,0x00000380, ++0x016,0x00000020, ++0x016,0x000001a0, ++0x000,0x000000bf, ++0x00d,0x0000001f, ++0x00d,0x00000c9f, ++0x002,0x0000004d, ++0x000,0x00000cbf, ++0x004,0x00000975, ++0x007,0x00000700, ++}; ++static u32 Rtl8192PciERadioB_Array[RadioB_ArrayLength] = { ++0x019,0x00000003, ++0x000,0x000000bf, ++0x001,0x000006e0, ++0x002,0x0000004c, ++0x003,0x000007f1, ++0x004,0x00000975, ++0x005,0x00000c58, ++0x006,0x00000ae6, ++0x007,0x000000ca, ++0x008,0x00000e1c, ++0x000,0x000000b7, ++0x00a,0x00000850, ++0x000,0x000000bf, ++0x00b,0x000001ba, ++0x00c,0x00000240, ++0x00e,0x00000020, ++0x015,0x00000f80, ++0x016,0x00000020, ++0x017,0x00000597, ++0x018,0x0000050a, ++0x01a,0x00000e00, ++0x01b,0x00000f5e, ++0x01d,0x00000607, ++0x01e,0x000006cc, ++0x00b,0x000001ba, ++0x023,0x00000203, ++0x024,0x00000100, ++0x000,0x00000037, ++0x004,0x00000160, ++0x016,0x00000200, ++0x016,0x00000380, ++0x016,0x00000020, ++0x016,0x000001a0, ++0x00d,0x00000ccc, ++0x000,0x000000bf, ++0x002,0x0000004d, ++0x000,0x00000cbf, ++0x004,0x00000975, ++0x007,0x00000700, ++}; ++static u32 Rtl8192PciERadioC_Array[RadioC_ArrayLength] = { ++0x0, }; ++static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = { ++0x0, }; ++#endif ++ ++/*************************Define local function prototype**********************/ ++ ++static u32 phy_FwRFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset); ++static void phy_FwRFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data); ++/*************************Define local function prototype**********************/ ++/****************************************************************************** ++ *function: This function read BB parameters from Header file we gen, ++ * and do register read/write ++ * input: u32 dwBitMask //taget bit pos in the addr to be modified ++ * output: none ++ * return: u32 return the shift bit bit position of the mask ++ * ****************************************************************************/ ++static u32 rtl8192_CalculateBitShift(u32 dwBitMask) ++{ ++ u32 i; ++ for (i=0; i<=31; i++) ++ { ++ if (((dwBitMask>>i)&0x1) == 1) ++ break; ++ } ++ return i; ++} ++/****************************************************************************** ++ *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false. ++ * input: none ++ * output: none ++ * return: 0(illegal, false), 1(legal,true) ++ * ***************************************************************************/ ++u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) ++{ ++ u8 ret = 1; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#ifdef RTL8190P ++ if(priv->rf_type == RF_2T4R) ++ { ++ ret= 1; ++ } ++ else if (priv->rf_type == RF_1T2R) ++ { ++ if(eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) ++ ret = 0; ++ else if(eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) ++ ret = 1; ++ } ++#else ++ #ifdef RTL8192E ++ if (priv->rf_type == RF_2T4R) ++ ret = 0; ++ else if (priv->rf_type == RF_1T2R) ++ { ++ if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) ++ ret = 1; ++ else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) ++ ret = 0; ++ } ++ #endif ++#endif ++ return ret; ++} ++/****************************************************************************** ++ *function: This function set specific bits to BB register ++ * input: net_device dev ++ * u32 dwRegAddr //target addr to be modified ++ * u32 dwBitMask //taget bit pos in the addr to be modified ++ * u32 dwData //value to be write ++ * output: none ++ * return: none ++ * notice: ++ * ****************************************************************************/ ++void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData) ++{ ++ ++ u32 OriginalValue, BitShift, NewValue; ++ ++ if(dwBitMask!= bMaskDWord) ++ {//if not "double word" write ++ OriginalValue = read_nic_dword(dev, dwRegAddr); ++ BitShift = rtl8192_CalculateBitShift(dwBitMask); ++ NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); ++ write_nic_dword(dev, dwRegAddr, NewValue); ++ }else ++ write_nic_dword(dev, dwRegAddr, dwData); ++ return; ++} ++/****************************************************************************** ++ *function: This function reads specific bits from BB register ++ * input: net_device dev ++ * u32 dwRegAddr //target addr to be readback ++ * u32 dwBitMask //taget bit pos in the addr to be readback ++ * output: none ++ * return: u32 Data //the readback register value ++ * notice: ++ * ****************************************************************************/ ++u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) ++{ ++ u32 Ret = 0, OriginalValue, BitShift; ++ ++ OriginalValue = read_nic_dword(dev, dwRegAddr); ++ BitShift = rtl8192_CalculateBitShift(dwBitMask); ++ Ret = (OriginalValue & dwBitMask) >> BitShift; ++ ++ return (Ret); ++} ++/****************************************************************************** ++ *function: This function read register from RF chip ++ * input: net_device dev ++ * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D ++ * u32 Offset //target address to be read ++ * output: none ++ * return: u32 readback value ++ * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information. ++ * ****************************************************************************/ ++static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u32 ret = 0; ++ u32 NewOffset = 0; ++ BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath]; ++ //rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0); ++ //make sure RF register offset is correct ++ Offset &= 0x3f; ++ ++ //switch page for 8256 RF IC ++ if (priv->rf_chip == RF_8256) ++ { ++#ifdef RTL8190P ++ //analog to digital off, for protection ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] ++#else ++ #ifdef RTL8192E ++ //analog to digital off, for protection ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] ++ #endif ++#endif ++ if (Offset >= 31) ++ { ++ priv->RfReg0Value[eRFPath] |= 0x140; ++ //Switch to Reg_Mode2 for Reg 31-45 ++ rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); ++ //modify offset ++ NewOffset = Offset -30; ++ } ++ else if (Offset >= 16) ++ { ++ priv->RfReg0Value[eRFPath] |= 0x100; ++ priv->RfReg0Value[eRFPath] &= (~0x40); ++ //Switch to Reg_Mode 1 for Reg16-30 ++ rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); ++ ++ NewOffset = Offset - 15; ++ } ++ else ++ NewOffset = Offset; ++ } ++ else ++ { ++ RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); ++ NewOffset = Offset; ++ } ++ //put desired read addr to LSSI control Register ++ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); ++ //Issue a posedge trigger ++ // ++ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); ++ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); ++ ++ ++ // TODO: we should not delay such a long time. Ask help from SD3 ++ msleep(1); ++ ++ ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); ++ ++ ++ // Switch back to Reg_Mode0; ++ if(priv->rf_chip == RF_8256) ++ { ++ priv->RfReg0Value[eRFPath] &= 0xebf; ++ ++ rtl8192_setBBreg( ++ dev, ++ pPhyReg->rf3wireOffset, ++ bMaskDWord, ++ (priv->RfReg0Value[eRFPath] << 16)); ++ ++#ifdef RTL8190P ++ if(priv->rf_type == RF_2T4R) ++ { ++ //analog to digital on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8] ++ } ++ else if(priv->rf_type == RF_1T2R) ++ { ++ //analog to digital on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10] ++ } ++#else ++ #ifdef RTL8192E ++ //analog to digital on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] ++ #endif ++#endif ++ } ++ ++ ++ return ret; ++ ++} ++ ++/****************************************************************************** ++ *function: This function write data to RF register ++ * input: net_device dev ++ * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D ++ * u32 Offset //target address to be written ++ * u32 Data //The new register data to be written ++ * output: none ++ * return: none ++ * notice: For RF8256 only. ++ =========================================================== ++ *Reg Mode RegCTL[1] RegCTL[0] Note ++ * (Reg00[12]) (Reg00[10]) ++ *=========================================================== ++ *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) ++ *------------------------------------------------------------------ ++ *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) ++ *------------------------------------------------------------------ ++ * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) ++ *------------------------------------------------------------------ ++ * ****************************************************************************/ ++static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u32 DataAndAddr = 0, NewOffset = 0; ++ BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; ++ ++ Offset &= 0x3f; ++ if (priv->rf_chip == RF_8256) ++ { ++ ++#ifdef RTL8190P ++ //analog to digital off, for protection ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] ++#else ++ #ifdef RTL8192E ++ //analog to digital off, for protection ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] ++ #endif ++#endif ++ ++ if (Offset >= 31) ++ { ++ priv->RfReg0Value[eRFPath] |= 0x140; ++ rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16)); ++ NewOffset = Offset - 30; ++ } ++ else if (Offset >= 16) ++ { ++ priv->RfReg0Value[eRFPath] |= 0x100; ++ priv->RfReg0Value[eRFPath] &= (~0x40); ++ rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); ++ NewOffset = Offset - 15; ++ } ++ else ++ NewOffset = Offset; ++ } ++ else ++ { ++ RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); ++ NewOffset = Offset; ++ } ++ ++ // Put write addr in [5:0] and write data in [31:16] ++ DataAndAddr = (Data<<16) | (NewOffset&0x3f); ++ ++ // Write Operation ++ rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); ++ ++ ++ if(Offset==0x0) ++ priv->RfReg0Value[eRFPath] = Data; ++ ++ // Switch back to Reg_Mode0; ++ if(priv->rf_chip == RF_8256) ++ { ++ if(Offset != 0) ++ { ++ priv->RfReg0Value[eRFPath] &= 0xebf; ++ rtl8192_setBBreg( ++ dev, ++ pPhyReg->rf3wireOffset, ++ bMaskDWord, ++ (priv->RfReg0Value[eRFPath] << 16)); ++ } ++#ifdef RTL8190P ++ if(priv->rf_type == RF_2T4R) ++ { ++ //analog to digital on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8] ++ } ++ else if(priv->rf_type == RF_1T2R) ++ { ++ //analog to digital on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10] ++ } ++#else ++ #ifdef RTL8192E ++ //analog to digital on ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] ++ #endif ++#endif ++ } ++ ++ return; ++} ++ ++/****************************************************************************** ++ *function: This function set specific bits to RF register ++ * input: net_device dev ++ * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D ++ * u32 RegAddr //target addr to be modified ++ * u32 BitMask //taget bit pos in the addr to be modified ++ * u32 Data //value to be write ++ * output: none ++ * return: none ++ * notice: ++ * ****************************************************************************/ ++void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u32 Original_Value, BitShift, New_Value; ++// u8 time = 0; ++ ++ if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) ++ return; ++#ifdef RTL8192E ++ if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter) ++ return; ++#endif ++ //spin_lock_irqsave(&priv->rf_lock, flags); ++ //down(&priv->rf_sem); ++ ++ RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n"); ++ if (priv->Rf_Mode == RF_OP_By_FW) ++ { ++ if (BitMask != bMask12Bits) // RF data is 12 bits only ++ { ++ Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); ++ BitShift = rtl8192_CalculateBitShift(BitMask); ++ New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); ++ ++ phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); ++ }else ++ phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); ++ udelay(200); ++ ++ } ++ else ++ { ++ if (BitMask != bMask12Bits) // RF data is 12 bits only ++ { ++ Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); ++ BitShift = rtl8192_CalculateBitShift(BitMask); ++ New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); ++ ++ rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value); ++ }else ++ rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); ++ } ++ //spin_unlock_irqrestore(&priv->rf_lock, flags); ++ //up(&priv->rf_sem); ++ return; ++} ++ ++/****************************************************************************** ++ *function: This function reads specific bits from RF register ++ * input: net_device dev ++ * u32 RegAddr //target addr to be readback ++ * u32 BitMask //taget bit pos in the addr to be readback ++ * output: none ++ * return: u32 Data //the readback register value ++ * notice: ++ * ****************************************************************************/ ++u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask) ++{ ++ u32 Original_Value, Readback_Value, BitShift; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) ++ return 0; ++#ifdef RTL8192E ++ if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter) ++ return 0; ++#endif ++ down(&priv->rf_sem); ++ if (priv->Rf_Mode == RF_OP_By_FW) ++ { ++ Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); ++ udelay(200); ++ } ++ else ++ { ++ Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); ++ ++ } ++ BitShift = rtl8192_CalculateBitShift(BitMask); ++ Readback_Value = (Original_Value & BitMask) >> BitShift; ++ up(&priv->rf_sem); ++// udelay(200); ++ return (Readback_Value); ++} ++ ++/****************************************************************************** ++ *function: We support firmware to execute RF-R/W. ++ * input: dev ++ * output: none ++ * return: none ++ * notice: ++ * ***************************************************************************/ ++static u32 phy_FwRFSerialRead( ++ struct net_device* dev, ++ RF90_RADIO_PATH_E eRFPath, ++ u32 Offset ) ++{ ++ u32 retValue = 0; ++ u32 Data = 0; ++ u8 time = 0; ++ //DbgPrint("FW RF CTRL\n\r"); ++ /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can ++ not execute the scheme in the initial step. Otherwise, RF-R/W will waste ++ much time. This is only for site survey. */ ++ // 1. Read operation need not insert data. bit 0-11 ++ //Data &= bMask12Bits; ++ // 2. Write RF register address. Bit 12-19 ++ Data |= ((Offset&0xFF)<<12); ++ // 3. Write RF path. bit 20-21 ++ Data |= ((eRFPath&0x3)<<20); ++ // 4. Set RF read indicator. bit 22=0 ++ //Data |= 0x00000; ++ // 5. Trigger Fw to operate the command. bit 31 ++ Data |= 0x80000000; ++ // 6. We can not execute read operation if bit 31 is 1. ++ while (read_nic_dword(dev, QPNR)&0x80000000) ++ { ++ // If FW can not finish RF-R/W for more than ?? times. We must reset FW. ++ if (time++ < 100) ++ { ++ //DbgPrint("FW not finish RF-R Time=%d\n\r", time); ++ udelay(10); ++ } ++ else ++ break; ++ } ++ // 7. Execute read operation. ++ write_nic_dword(dev, QPNR, Data); ++ // 8. Check if firmawre send back RF content. ++ while (read_nic_dword(dev, QPNR)&0x80000000) ++ { ++ // If FW can not finish RF-R/W for more than ?? times. We must reset FW. ++ if (time++ < 100) ++ { ++ //DbgPrint("FW not finish RF-W Time=%d\n\r", time); ++ udelay(10); ++ } ++ else ++ return (0); ++ } ++ retValue = read_nic_dword(dev, RF_DATA); ++ ++ return (retValue); ++ ++} /* phy_FwRFSerialRead */ ++ ++/****************************************************************************** ++ *function: We support firmware to execute RF-R/W. ++ * input: dev ++ * output: none ++ * return: none ++ * notice: ++ * ***************************************************************************/ ++static void ++phy_FwRFSerialWrite( ++ struct net_device* dev, ++ RF90_RADIO_PATH_E eRFPath, ++ u32 Offset, ++ u32 Data ) ++{ ++ u8 time = 0; ++ ++ //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data); ++ /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can ++ not execute the scheme in the initial step. Otherwise, RF-R/W will waste ++ much time. This is only for site survey. */ ++ ++ // 1. Set driver write bit and 12 bit data. bit 0-11 ++ //Data &= bMask12Bits; // Done by uper layer. ++ // 2. Write RF register address. bit 12-19 ++ Data |= ((Offset&0xFF)<<12); ++ // 3. Write RF path. bit 20-21 ++ Data |= ((eRFPath&0x3)<<20); ++ // 4. Set RF write indicator. bit 22=1 ++ Data |= 0x400000; ++ // 5. Trigger Fw to operate the command. bit 31=1 ++ Data |= 0x80000000; ++ ++ // 6. Write operation. We can not write if bit 31 is 1. ++ while (read_nic_dword(dev, QPNR)&0x80000000) ++ { ++ // If FW can not finish RF-R/W for more than ?? times. We must reset FW. ++ if (time++ < 100) ++ { ++ //DbgPrint("FW not finish RF-W Time=%d\n\r", time); ++ udelay(10); ++ } ++ else ++ break; ++ } ++ // 7. No matter check bit. We always force the write. Because FW will ++ // not accept the command. ++ write_nic_dword(dev, QPNR, Data); ++ /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware ++ to finish RF write operation. */ ++ /* 2008/01/17 MH We support delay in firmware side now. */ ++ //delay_us(20); ++ ++} /* phy_FwRFSerialWrite */ ++ ++ ++/****************************************************************************** ++ *function: This function read BB parameters from Header file we gen, ++ * and do register read/write ++ * input: dev ++ * output: none ++ * return: none ++ * notice: BB parameters may change all the time, so please make ++ * sure it has been synced with the newest. ++ * ***************************************************************************/ ++void rtl8192_phy_configmac(struct net_device* dev) ++{ ++ u32 dwArrayLen = 0, i = 0; ++ u32* pdwArray = NULL; ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#ifdef TO_DO_LIST ++if(Adapter->bInHctTest) ++ { ++ RT_TRACE(COMP_PHY, "Rtl819XMACPHY_ArrayDTM\n"); ++ dwArrayLen = MACPHY_ArrayLengthDTM; ++ pdwArray = Rtl819XMACPHY_ArrayDTM; ++ } ++ else if(priv->bTXPowerDataReadFromEEPORM) ++#endif ++ if(priv->bTXPowerDataReadFromEEPORM) ++ { ++ RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); ++ dwArrayLen = MACPHY_Array_PGLength; ++ pdwArray = Rtl819XMACPHY_Array_PG; ++ ++ } ++ else ++ { ++ RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n"); ++ dwArrayLen = MACPHY_ArrayLength; ++ pdwArray = Rtl819XMACPHY_Array; ++ } ++ for(i = 0; ibInHctTest) ++ { ++ AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; ++ Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; ++ ++ if(priv->RF_Type == RF_2T4R) ++ { ++ PHY_REGArrayLen = PHY_REGArrayLengthDTM; ++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; ++ } ++ else if (priv->RF_Type == RF_1T2R) ++ { ++ PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM; ++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM; ++ } ++ } ++ else ++#endif ++ { ++ AGCTAB_ArrayLen = AGCTAB_ArrayLength; ++ Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; ++ if(priv->rf_type == RF_2T4R) ++ { ++ PHY_REGArrayLen = PHY_REGArrayLength; ++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray; ++ } ++ else if (priv->rf_type == RF_1T2R) ++ { ++ PHY_REGArrayLen = PHY_REG_1T2RArrayLength; ++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray; ++ } ++ } ++ ++ if (ConfigType == BaseBand_Config_PHY_REG) ++ { ++ for (i=0; iPHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 ++ priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) ++ priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874 ++ priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) ++ ++ // RF Interface Readback Value ++ priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 ++ priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) ++ priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4 ++ priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) ++ ++ // RF Interface Output (and Enable) ++ priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 ++ priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864 ++ priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868 ++ priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C ++ ++ // RF Interface (Output and) Enable ++ priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) ++ priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) ++ priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) ++ priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) ++ ++ //Addr of LSSI. Wirte RF register by driver ++ priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter ++ priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; ++ priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; ++ priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; ++ ++ // RF parameter ++ priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select ++ priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; ++ priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; ++ priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; ++ ++ // Tx AGC Gain Stage (same for all path. Should we remove this?) ++ priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage ++ priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage ++ priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage ++ priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage ++ ++ // Tranceiver A~D HSSI Parameter-1 ++ priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 ++ priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1 ++ priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1 ++ priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1 ++ ++ // Tranceiver A~D HSSI Parameter-2 ++ priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 ++ priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2 ++ priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2 ++ priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1 ++ ++ // RF switch Control ++ priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control ++ priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; ++ priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; ++ priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; ++ ++ // AGC control 1 ++ priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; ++ priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; ++ priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; ++ priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; ++ ++ // AGC control 2 ++ priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; ++ priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; ++ priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; ++ priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; ++ ++ // RX AFE control 1 ++ priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; ++ priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; ++ priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; ++ priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; ++ ++ // RX AFE control 1 ++ priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; ++ priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; ++ priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; ++ priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; ++ ++ // Tx AFE control 1 ++ priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; ++ priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; ++ priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; ++ priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; ++ ++ // Tx AFE control 2 ++ priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; ++ priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; ++ priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; ++ priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; ++ ++ // Tranceiver LSSI Readback ++ priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; ++ priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; ++ priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; ++ priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; ++ ++} ++/****************************************************************************** ++ *function: This function is to write register and then readback to make sure whether BB and RF is OK ++ * input: net_device dev ++ * HW90_BLOCK_E CheckBlock ++ * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF ++ * output: none ++ * return: return whether BB and RF is ok(0:OK; 1:Fail) ++ * notice: This function may be removed in the ASIC ++ * ***************************************************************************/ ++RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath) ++{ ++ //struct r8192_priv *priv = ieee80211_priv(dev); ++// BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; ++ RT_STATUS ret = RT_STATUS_SUCCESS; ++ u32 i, CheckTimes = 4, dwRegRead = 0; ++ u32 WriteAddr[4]; ++ u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; ++ // Initialize register address offset to be checked ++ WriteAddr[HW90_BLOCK_MAC] = 0x100; ++ WriteAddr[HW90_BLOCK_PHY0] = 0x900; ++ WriteAddr[HW90_BLOCK_PHY1] = 0x800; ++ WriteAddr[HW90_BLOCK_RF] = 0x3; ++ RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock); ++ for(i=0 ; i < CheckTimes ; i++) ++ { ++ ++ // ++ // Write Data to register and readback ++ // ++ switch(CheckBlock) ++ { ++ case HW90_BLOCK_MAC: ++ RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!"); ++ break; ++ ++ case HW90_BLOCK_PHY0: ++ case HW90_BLOCK_PHY1: ++ write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); ++ dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); ++ break; ++ ++ case HW90_BLOCK_RF: ++ WriteData[i] &= 0xfff; ++ rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]); ++ // TODO: we should not delay for such a long time. Ask SD3 ++ mdelay(10); ++ dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); ++ mdelay(10); ++ break; ++ ++ default: ++ ret = RT_STATUS_FAILURE; ++ break; ++ } ++ ++ ++ // ++ // Check whether readback data is correct ++ // ++ if(dwRegRead != WriteData[i]) ++ { ++ RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]); ++ ret = RT_STATUS_FAILURE; ++ break; ++ } ++ } ++ ++ return ret; ++} ++ ++ ++/****************************************************************************** ++ *function: This function initialize BB&RF ++ * input: net_device dev ++ * output: none ++ * return: none ++ * notice: Initialization value may change all the time, so please make ++ * sure it has been synced with the newest. ++ * ***************************************************************************/ ++static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ RT_STATUS rtStatus = RT_STATUS_SUCCESS; ++ u8 bRegValue = 0, eCheckItem = 0; ++ u32 dwRegValue = 0; ++ /************************************** ++ //<1>Initialize BaseBand ++ **************************************/ ++ ++ /*--set BB Global Reset--*/ ++ bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); ++ write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); ++ ++ /*---set BB reset Active---*/ ++ dwRegValue = read_nic_dword(dev, CPU_GEN); ++ write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); ++ ++ /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/ ++ // TODO: this function should be removed on ASIC , Emily 2007.2.2 ++ for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) ++ { ++ rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path ++ if(rtStatus != RT_STATUS_SUCCESS) ++ { ++ RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1); ++ return rtStatus; ++ } ++ } ++ /*---- Set CCK and OFDM Block "OFF"----*/ ++ rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); ++ /*----BB Register Initilazation----*/ ++ //==m==>Set PHY REG From Header<==m== ++ rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); ++ ++ /*----Set BB reset de-Active----*/ ++ dwRegValue = read_nic_dword(dev, CPU_GEN); ++ write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); ++ ++ /*----BB AGC table Initialization----*/ ++ //==m==>Set PHY REG From Header<==m== ++ rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); ++ ++ if (priv->card_8192_version > VERSION_8190_BD) ++ { ++ if(priv->rf_type == RF_2T4R) ++ { ++ // Antenna gain offset from B/C/D to A ++ dwRegValue = ( priv->AntennaTxPwDiff[2]<<8 | ++ priv->AntennaTxPwDiff[1]<<4 | ++ priv->AntennaTxPwDiff[0]); ++ } ++ else ++ dwRegValue = 0x0; //Antenna gain offset doesn't make sense in RF 1T2R. ++ rtl8192_setBBreg(dev, rFPGA0_TxGainStage, ++ (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); ++ ++ ++ //XSTALLCap ++#ifdef RTL8190P ++ dwRegValue = priv->CrystalCap & 0x3; // bit0~1 of crystal cap ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue); ++ dwRegValue = ((priv->CrystalCap & 0xc)>>2); // bit2~3 of crystal cap ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, bXtalCap23, dwRegValue); ++#else ++ #ifdef RTL8192E ++ dwRegValue = priv->CrystalCap; ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue); ++ #endif ++#endif ++ ++ } ++ ++ // Check if the CCK HighPower is turned ON. ++ // This is used to calculate PWDB. ++// priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200)); ++ return rtStatus; ++} ++/****************************************************************************** ++ *function: This function initialize BB&RF ++ * input: net_device dev ++ * output: none ++ * return: none ++ * notice: Initialization value may change all the time, so please make ++ * sure it has been synced with the newest. ++ * ***************************************************************************/ ++RT_STATUS rtl8192_BBConfig(struct net_device* dev) ++{ ++ RT_STATUS rtStatus = RT_STATUS_SUCCESS; ++ rtl8192_InitBBRFRegDef(dev); ++ //config BB&RF. As hardCode based initialization has not been well ++ //implemented, so use file first.FIXME:should implement it for hardcode? ++ rtStatus = rtl8192_BB_Config_ParaFile(dev); ++ return rtStatus; ++} ++ ++/****************************************************************************** ++ *function: This function obtains the initialization value of Tx power Level offset ++ * input: net_device dev ++ * output: none ++ * return: none ++ * ***************************************************************************/ ++void rtl8192_phy_getTxPower(struct net_device* dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#ifdef RTL8190P ++ priv->MCSTxPowerLevelOriginalOffset[0] = ++ read_nic_dword(dev, MCS_TXAGC); ++ priv->MCSTxPowerLevelOriginalOffset[1] = ++ read_nic_dword(dev, (MCS_TXAGC+4)); ++ priv->CCKTxPowerLevelOriginalOffset = ++ read_nic_dword(dev, CCK_TXAGC); ++#else ++ #ifdef RTL8192E ++ priv->MCSTxPowerLevelOriginalOffset[0] = ++ read_nic_dword(dev, rTxAGC_Rate18_06); ++ priv->MCSTxPowerLevelOriginalOffset[1] = ++ read_nic_dword(dev, rTxAGC_Rate54_24); ++ priv->MCSTxPowerLevelOriginalOffset[2] = ++ read_nic_dword(dev, rTxAGC_Mcs03_Mcs00); ++ priv->MCSTxPowerLevelOriginalOffset[3] = ++ read_nic_dword(dev, rTxAGC_Mcs07_Mcs04); ++ priv->MCSTxPowerLevelOriginalOffset[4] = ++ read_nic_dword(dev, rTxAGC_Mcs11_Mcs08); ++ priv->MCSTxPowerLevelOriginalOffset[5] = ++ read_nic_dword(dev, rTxAGC_Mcs15_Mcs12); ++ #endif ++#endif ++ ++ // read rx initial gain ++ priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); ++ priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); ++ priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); ++ priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); ++ RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", ++ priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], ++ priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); ++ ++ // read framesync ++ priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); ++ priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2); ++ RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", ++ rOFDM0_RxDetector3, priv->framesync); ++ // read SIFS (save the value read fome MACPHY_REG.txt) ++ priv->SifsTime = read_nic_word(dev, SIFS); ++ return; ++} ++ ++/****************************************************************************** ++ *function: This function obtains the initialization value of Tx power Level offset ++ * input: net_device dev ++ * output: none ++ * return: none ++ * ***************************************************************************/ ++void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 powerlevel = 0,powerlevelOFDM24G = 0; ++ char ant_pwr_diff; ++ u32 u4RegValue; ++ ++ if(priv->epromtype == EPROM_93c46) ++ { ++ powerlevel = priv->TxPowerLevelCCK[channel-1]; ++ powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; ++ } ++ else if(priv->epromtype == EPROM_93c56) ++ { ++ if(priv->rf_type == RF_1T2R) ++ { ++ powerlevel = priv->TxPowerLevelCCK_C[channel-1]; ++ powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1]; ++ } ++ else if(priv->rf_type == RF_2T4R) ++ { ++ // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-C Tx ++ // Power must be calculated by the antenna diff. ++ // So we have to rewrite Antenna gain offset register here. ++ powerlevel = priv->TxPowerLevelCCK_A[channel-1]; ++ powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1]; ++ ++ ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1] ++ -priv->TxPowerLevelOFDM24G_A[channel-1]; ++ ant_pwr_diff &= 0xf; ++ //DbgPrint(" ant_pwr_diff = 0x%x", (u8)(ant_pwr_diff)); ++ priv->RF_C_TxPwDiff = ant_pwr_diff; ++ ++ priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care ++ priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);// RF-C ++ priv->AntennaTxPwDiff[0] = 0;// RF-B, don't care ++ ++ // Antenna gain offset from B/C/D to A ++ u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 | ++ priv->AntennaTxPwDiff[1]<<4 | ++ priv->AntennaTxPwDiff[0]); ++ ++ rtl8192_setBBreg(dev, rFPGA0_TxGainStage, ++ (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); ++ } ++ } ++#ifdef TODO ++ // ++ // CCX 2 S31, AP control of client transmit power: ++ // 1. We shall not exceed Cell Power Limit as possible as we can. ++ // 2. Tolerance is +/- 5dB. ++ // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit. ++ // ++ // TODO: ++ // 1. 802.11h power contraint ++ // ++ // 071011, by rcnjko. ++ // ++ if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE && ++ pMgntInfo->bWithCcxCellPwr && ++ channel == pMgntInfo->dot11CurrentChannelNumber) ++ { ++ u8 CckCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr); ++ u8 LegacyOfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr); ++ u8 OfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pMgntInfo->CcxCellPwr); ++ ++ RT_TRACE(COMP_TXAGC, DBG_LOUD, ++ ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", ++ pMgntInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx)); ++ RT_TRACE(COMP_TXAGC, DBG_LOUD, ++ ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", ++ channel, powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G)); ++ ++ // CCK ++ if(powerlevel > CckCellPwrIdx) ++ powerlevel = CckCellPwrIdx; ++ // Legacy OFDM, HT OFDM ++ if(powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff > OfdmCellPwrIdx) ++ { ++ if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0) ++ { ++ powerlevelOFDM24G = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff; ++ } ++ else ++ { ++ LegacyOfdmCellPwrIdx = 0; ++ } ++ } ++ ++ RT_TRACE(COMP_TXAGC, DBG_LOUD, ++ ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n", ++ powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G)); ++ } ++ ++ pHalData->CurrentCckTxPwrIdx = powerlevel; ++ pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G; ++#endif ++ switch(priv->rf_chip) ++ { ++ case RF_8225: ++ // PHY_SetRF8225CckTxPower(Adapter, powerlevel); ++ // PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G); ++ break; ++ case RF_8256: ++ PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement ++ PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); ++ break; ++ case RF_8258: ++ break; ++ default: ++ RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __FUNCTION__); ++ break; ++ } ++ return; ++} ++ ++/****************************************************************************** ++ *function: This function check Rf chip to do RF config ++ * input: net_device dev ++ * output: none ++ * return: only 8256 is supported ++ * ***************************************************************************/ ++RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ RT_STATUS rtStatus = RT_STATUS_SUCCESS; ++ switch(priv->rf_chip) ++ { ++ case RF_8225: ++// rtStatus = PHY_RF8225_Config(Adapter); ++ break; ++ case RF_8256: ++ rtStatus = PHY_RF8256_Config(dev); ++ break; ++ ++ case RF_8258: ++ break; ++ case RF_PSEUDO_11N: ++ //rtStatus = PHY_RF8225_Config(Adapter); ++ break; ++ ++ default: ++ RT_TRACE(COMP_ERR, "error chip id\n"); ++ break; ++ } ++ return rtStatus; ++} ++ ++/****************************************************************************** ++ *function: This function update Initial gain ++ * input: net_device dev ++ * output: none ++ * return: As Windows has not implemented this, wait for complement ++ * ***************************************************************************/ ++void rtl8192_phy_updateInitGain(struct net_device* dev) ++{ ++ return; ++} ++ ++/****************************************************************************** ++ *function: This function read RF parameters from general head file, and do RF 3-wire ++ * input: net_device dev ++ * output: none ++ * return: return code show if RF configuration is successful(0:pass, 1:fail) ++ * Note: Delay may be required for RF configuration ++ * ***************************************************************************/ ++u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath) ++{ ++ ++ int i; ++ //u32* pRFArray; ++ u8 ret = 0; ++ ++ switch(eRFPath){ ++ case RF90_PATH_A: ++ for(i = 0;iTxPowerLevelCCK[channel-1]; ++ u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; ++ ++ switch(priv->rf_chip) ++ { ++ case RF_8225: ++#ifdef TO_DO_LIST ++ PHY_SetRF8225CckTxPower(Adapter, powerlevel); ++ PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G); ++#endif ++ break; ++ ++ case RF_8256: ++ PHY_SetRF8256CCKTxPower(dev, powerlevel); ++ PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); ++ break; ++ ++ case RF_8258: ++ break; ++ default: ++ RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n"); ++ break; ++ } ++ return; ++} ++/**************************************************************************************** ++ *function: This function set command table variable(struct SwChnlCmd). ++ * input: SwChnlCmd* CmdTable //table to be set. ++ * u32 CmdTableIdx //variable index in table to be set ++ * u32 CmdTableSz //table size. ++ * SwChnlCmdID CmdID //command ID to set. ++ * u32 Para1 ++ * u32 Para2 ++ * u32 msDelay ++ * output: ++ * return: true if finished, false otherwise ++ * Note: ++ * ************************************************************************************/ ++static u8 rtl8192_phy_SetSwChnlCmdArray( ++ SwChnlCmd* CmdTable, ++ u32 CmdTableIdx, ++ u32 CmdTableSz, ++ SwChnlCmdID CmdID, ++ u32 Para1, ++ u32 Para2, ++ u32 msDelay ++ ) ++{ ++ SwChnlCmd* pCmd; ++ ++ if(CmdTable == NULL) ++ { ++ RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"); ++ return false; ++ } ++ if(CmdTableIdx >= CmdTableSz) ++ { ++ RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", ++ CmdTableIdx, CmdTableSz); ++ return false; ++ } ++ ++ pCmd = CmdTable + CmdTableIdx; ++ pCmd->CmdID = CmdID; ++ pCmd->Para1 = Para1; ++ pCmd->Para2 = Para2; ++ pCmd->msDelay = msDelay; ++ ++ return true; ++} ++/****************************************************************************** ++ *function: This function set channel step by step ++ * input: struct net_device *dev ++ * u8 channel ++ * u8* stage //3 stages ++ * u8* step // ++ * u32* delay //whether need to delay ++ * output: store new stage, step and delay for next step(combine with function above) ++ * return: true if finished, false otherwise ++ * Note: Wait for simpler function to replace it //wb ++ * ***************************************************************************/ ++static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++// PCHANNEL_ACCESS_SETTING pChnlAccessSetting; ++ SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; ++ u32 PreCommonCmdCnt; ++ SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; ++ u32 PostCommonCmdCnt; ++ SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; ++ u32 RfDependCmdCnt; ++ SwChnlCmd *CurrentCmd = NULL; ++ //RF90_RADIO_PATH_E eRFPath; ++ u8 eRFPath; ++// u32 RfRetVal; ++// u8 RetryCnt; ++ ++ RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel); ++// RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel)); ++ ++#ifdef ENABLE_DOT11D ++ if (!IsLegalChannel(priv->ieee80211, channel)) ++ { ++ RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel); ++ return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop. ++ } ++#endif ++ ++ //for(eRFPath = RF90_PATH_A; eRFPath NumTotalRFPath; eRFPath++) ++ //for(eRFPath = 0; eRFPath Fill up pre common command. ++ PreCommonCmdCnt = 0; ++ rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, ++ CmdID_SetTxPowerLevel, 0, 0, 0); ++ rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, ++ CmdID_End, 0, 0, 0); ++ ++ // <2> Fill up post common command. ++ PostCommonCmdCnt = 0; ++ ++ rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, ++ CmdID_End, 0, 0, 0); ++ ++ // <3> Fill up RF dependent command. ++ RfDependCmdCnt = 0; ++ switch( priv->rf_chip ) ++ { ++ case RF_8225: ++ if (!(channel >= 1 && channel <= 14)) ++ { ++ RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel); ++ return false; ++ } ++ rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10); ++ rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_End, 0, 0, 0); ++ break; ++ ++ case RF_8256: ++ // TEST!! This is not the table for 8256!! ++ if (!(channel >= 1 && channel <= 14)) ++ { ++ RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel); ++ return false; ++ } ++ rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_RF_WriteReg, rZebra1_Channel, channel, 10); ++ rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_End, 0, 0, 0); ++ break; ++ ++ case RF_8258: ++ break; ++ ++ default: ++ RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); ++ return false; ++ break; ++ } ++ ++ ++ do{ ++ switch(*stage) ++ { ++ case 0: ++ CurrentCmd=&PreCommonCmd[*step]; ++ break; ++ case 1: ++ CurrentCmd=&RfDependCmd[*step]; ++ break; ++ case 2: ++ CurrentCmd=&PostCommonCmd[*step]; ++ break; ++ } ++ ++ if(CurrentCmd->CmdID==CmdID_End) ++ { ++ if((*stage)==2) ++ { ++ return true; ++ } ++ else ++ { ++ (*stage)++; ++ (*step)=0; ++ continue; ++ } ++ } ++ ++ switch(CurrentCmd->CmdID) ++ { ++ case CmdID_SetTxPowerLevel: ++ if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later! ++ rtl8192_SetTxPowerLevel(dev,channel); ++ break; ++ case CmdID_WritePortUlong: ++ write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); ++ break; ++ case CmdID_WritePortUshort: ++ write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); ++ break; ++ case CmdID_WritePortUchar: ++ write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); ++ break; ++ case CmdID_RF_WriteReg: ++ for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7); ++ break; ++ default: ++ break; ++ } ++ ++ break; ++ }while(true); ++ }/*for(Number of RF paths)*/ ++ ++ (*delay)=CurrentCmd->msDelay; ++ (*step)++; ++ return false; ++} ++ ++/****************************************************************************** ++ *function: This function does acturally set channel work ++ * input: struct net_device *dev ++ * u8 channel ++ * output: none ++ * return: noin ++ * Note: We should not call this function directly ++ * ***************************************************************************/ ++static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u32 delay = 0; ++ ++ while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) ++ { ++ if(delay>0) ++ msleep(delay);//or mdelay? need further consideration ++ if(!priv->up) ++ break; ++ } ++} ++/****************************************************************************** ++ *function: Callback routine of the work item for switch channel. ++ * input: ++ * ++ * output: none ++ * return: noin ++ * ***************************************************************************/ ++void rtl8192_SwChnl_WorkItem(struct net_device *dev) ++{ ++ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n"); ++ ++ RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv); ++ ++ rtl8192_phy_FinishSwChnlNow(dev , priv->chan); ++ ++ RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n"); ++} ++ ++/****************************************************************************** ++ *function: This function scheduled actural workitem to set channel ++ * input: net_device dev ++ * u8 channel //channel to set ++ * output: none ++ * return: return code show if workitem is scheduled(1:pass, 0:fail) ++ * Note: Delay may be required for RF configuration ++ * ***************************************************************************/ ++u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ RT_TRACE(COMP_PHY, "=====>%s()\n", __FUNCTION__); ++ if(!priv->up) ++ return false; ++ if(priv->SwChnlInProgress) ++ return false; ++ ++// if(pHalData->SetBWModeInProgress) ++// return; ++ ++ //-------------------------------------------- ++ switch(priv->ieee80211->mode) ++ { ++ case WIRELESS_MODE_A: ++ case WIRELESS_MODE_N_5G: ++ if (channel<=14){ ++ RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); ++ return false; ++ } ++ break; ++ case WIRELESS_MODE_B: ++ if (channel>14){ ++ RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); ++ return false; ++ } ++ break; ++ case WIRELESS_MODE_G: ++ case WIRELESS_MODE_N_24G: ++ if (channel>14){ ++ RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); ++ return false; ++ } ++ break; ++ } ++ //-------------------------------------------- ++ ++ priv->SwChnlInProgress = true; ++ if(channel == 0) ++ channel = 1; ++ ++ priv->chan=channel; ++ ++ priv->SwChnlStage=0; ++ priv->SwChnlStep=0; ++// schedule_work(&(priv->SwChnlWorkItem)); ++// rtl8192_SwChnl_WorkItem(dev); ++ if(priv->up) { ++// queue_work(priv->priv_wq,&(priv->SwChnlWorkItem)); ++ rtl8192_SwChnl_WorkItem(dev); ++ } ++ priv->SwChnlInProgress = false; ++ return true; ++} ++ ++static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev ) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ switch(priv->CurrentChannelBW) ++ { ++ /* 20 MHz channel*/ ++ case HT_CHANNEL_WIDTH_20: ++ //added by vivi, cck,tx power track, 20080703 ++ priv->CCKPresentAttentuation = ++ priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference; ++ ++ if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1)) ++ priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1; ++ if(priv->CCKPresentAttentuation < 0) ++ priv->CCKPresentAttentuation = 0; ++ ++ RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation); ++ ++ if(priv->ieee80211->current_network.channel== 14 && !priv->bcck_in_ch14) ++ { ++ priv->bcck_in_ch14 = TRUE; ++ dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); ++ } ++ else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) ++ { ++ priv->bcck_in_ch14 = FALSE; ++ dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); ++ } ++ else ++ dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); ++ break; ++ ++ /* 40 MHz channel*/ ++ case HT_CHANNEL_WIDTH_20_40: ++ //added by vivi, cck,tx power track, 20080703 ++ priv->CCKPresentAttentuation = ++ priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference; ++ ++ RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation); ++ if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1)) ++ priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1; ++ if(priv->CCKPresentAttentuation < 0) ++ priv->CCKPresentAttentuation = 0; ++ ++ if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) ++ { ++ priv->bcck_in_ch14 = TRUE; ++ dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); ++ } ++ else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) ++ { ++ priv->bcck_in_ch14 = FALSE; ++ dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); ++ } ++ else ++ dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); ++ break; ++ } ++} ++ ++#ifndef RTL8190P ++static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) ++ priv->bcck_in_ch14 = TRUE; ++ else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) ++ priv->bcck_in_ch14 = FALSE; ++ ++ //write to default index and tx power track will be done in dm. ++ switch(priv->CurrentChannelBW) ++ { ++ /* 20 MHz channel*/ ++ case HT_CHANNEL_WIDTH_20: ++ if(priv->Record_CCK_20Mindex == 0) ++ priv->Record_CCK_20Mindex = 6; //set default value. ++ priv->CCK_index = priv->Record_CCK_20Mindex;//6; ++ RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index); ++ break; ++ ++ /* 40 MHz channel*/ ++ case HT_CHANNEL_WIDTH_20_40: ++ priv->CCK_index = priv->Record_CCK_40Mindex;//0; ++ RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index); ++ break; ++ } ++ dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); ++} ++#endif ++ ++static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev) ++{ ++#ifdef RTL8192E ++ struct r8192_priv *priv = ieee80211_priv(dev); ++#endif ++ ++#ifdef RTL8190P ++ CCK_Tx_Power_Track_BW_Switch_TSSI(dev); ++#else ++ //if(pHalData->bDcut == TRUE) ++ if(priv->IC_Cut >= IC_VersionCut_D) ++ CCK_Tx_Power_Track_BW_Switch_TSSI(dev); ++ else ++ CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev); ++#endif ++} ++ ++ ++// ++/****************************************************************************** ++ *function: Callback routine of the work item for set bandwidth mode. ++ * input: struct net_device *dev ++ * HT_CHANNEL_WIDTH Bandwidth //20M or 40M ++ * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care ++ * output: none ++ * return: none ++ * Note: I doubt whether SetBWModeInProgress flag is necessary as we can ++ * test whether current work in the queue or not.//do I? ++ * ***************************************************************************/ ++void rtl8192_SetBWModeWorkItem(struct net_device *dev) ++{ ++ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u8 regBwOpMode; ++ ++ RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \ ++ priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz") ++ ++ ++ if(priv->rf_chip== RF_PSEUDO_11N) ++ { ++ priv->SetBWModeInProgress= false; ++ return; ++ } ++ if(!priv->up) ++ { ++ priv->SetBWModeInProgress= false; ++ return; ++ } ++ //<1>Set MAC register ++ regBwOpMode = read_nic_byte(dev, BW_OPMODE); ++ ++ switch(priv->CurrentChannelBW) ++ { ++ case HT_CHANNEL_WIDTH_20: ++ regBwOpMode |= BW_OPMODE_20MHZ; ++ // 2007/02/07 Mark by Emily becasue we have not verify whether this register works ++ write_nic_byte(dev, BW_OPMODE, regBwOpMode); ++ break; ++ ++ case HT_CHANNEL_WIDTH_20_40: ++ regBwOpMode &= ~BW_OPMODE_20MHZ; ++ // 2007/02/07 Mark by Emily becasue we have not verify whether this register works ++ write_nic_byte(dev, BW_OPMODE, regBwOpMode); ++ break; ++ ++ default: ++ RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW); ++ break; ++ } ++ ++ //<2>Set PHY related register ++ switch(priv->CurrentChannelBW) ++ { ++ case HT_CHANNEL_WIDTH_20: ++ // Add by Vivi 20071119 ++ rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); ++ rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); ++// rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); ++ ++ // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207 ++// write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); ++// write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); ++// write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); ++ if(!priv->btxpower_tracking) ++ { ++ write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); ++ write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); ++ write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); ++ } ++ else ++ CCK_Tx_Power_Track_BW_Switch(dev); ++ ++#ifdef RTL8190P ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1); ++ rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x44); // 0xc30 is for 8190 only, Emily ++#else ++ #ifdef RTL8192E ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); ++ #endif ++#endif ++ ++ break; ++ case HT_CHANNEL_WIDTH_20_40: ++ // Add by Vivi 20071119 ++ rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); ++ rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); ++ //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); ++ //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); ++ //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); ++ ++ // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207 ++ //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); ++ //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); ++ //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); ++ if(!priv->btxpower_tracking) ++ { ++ write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); ++ write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); ++ write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); ++ } ++ else ++ CCK_Tx_Power_Track_BW_Switch(dev); ++ ++ // Set Control channel to upper or lower. These settings are required only for 40MHz ++ rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); ++ rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); ++ ++ ++#ifdef RTL8190P ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0); ++ rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x42); // 0xc30 is for 8190 only, Emily ++ ++ // Set whether CCK should be sent in upper or lower channel. Suggest by YN. 20071207 ++ // It is set in Tx descriptor for 8192x series ++ if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) ++ { ++ rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x01); ++ }else if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ++ { ++ rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x02); ++ } ++ ++#else ++ #ifdef RTL8192E ++ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); ++ #endif ++#endif ++ break; ++ default: ++ RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW); ++ break; ++ ++ } ++ //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 ++ ++#if 1 ++ //<3>Set RF related register ++ switch( priv->rf_chip ) ++ { ++ case RF_8225: ++#ifdef TO_DO_LIST ++ PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); ++#endif ++ break; ++ ++ case RF_8256: ++ PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); ++ break; ++ ++ case RF_8258: ++ // PHY_SetRF8258Bandwidth(); ++ break; ++ ++ case RF_PSEUDO_11N: ++ // Do Nothing ++ break; ++ ++ default: ++ RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); ++ break; ++ } ++#endif ++ atomic_dec(&(priv->ieee80211->atm_swbw)); ++ priv->SetBWModeInProgress= false; ++ ++ RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()"); ++} ++ ++/****************************************************************************** ++ *function: This function schedules bandwith switch work. ++ * input: struct net_device *dev ++ * HT_CHANNEL_WIDTH Bandwidth //20M or 40M ++ * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care ++ * output: none ++ * return: none ++ * Note: I doubt whether SetBWModeInProgress flag is necessary as we can ++ * test whether current work in the queue or not.//do I? ++ * ***************************************************************************/ ++void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) ++{ ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ ++ ++ if(priv->SetBWModeInProgress) ++ return; ++ ++ atomic_inc(&(priv->ieee80211->atm_swbw)); ++ priv->SetBWModeInProgress= true; ++ ++ priv->CurrentChannelBW = Bandwidth; ++ ++ if(Offset==HT_EXTCHNL_OFFSET_LOWER) ++ priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; ++ else if(Offset==HT_EXTCHNL_OFFSET_UPPER) ++ priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; ++ else ++ priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem)); ++ // schedule_work(&(priv->SetBWModeWorkItem)); ++ rtl8192_SetBWModeWorkItem(dev); ++ ++} ++ ++ ++void InitialGain819xPci(struct net_device *dev, u8 Operation) ++{ ++#define SCAN_RX_INITIAL_GAIN 0x17 ++#define POWER_DETECTION_TH 0x08 ++ struct r8192_priv *priv = ieee80211_priv(dev); ++ u32 BitMask; ++ u8 initial_gain; ++ ++ if(priv->up) ++ { ++ switch(Operation) ++ { ++ case IG_Backup: ++ RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); ++ initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];// ++ BitMask = bMaskByte0; ++ if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) ++ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF ++ priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); ++ priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); ++ priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); ++ priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); ++ BitMask = bMaskByte2; ++ priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); ++ ++ RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); ++ RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); ++ RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); ++ RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); ++ RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); ++ ++ RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); ++ write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); ++ write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); ++ write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); ++ write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); ++ RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); ++ write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); ++ break; ++ case IG_Restore: ++ RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); ++ BitMask = 0x7f; //Bit0~ Bit6 ++ if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) ++ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF ++ ++ rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); ++ rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); ++ rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); ++ rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); ++ BitMask = bMaskByte2; ++ rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); ++ ++ RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); ++ RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); ++ RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); ++ RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); ++ RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); ++ ++ rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel); ++ ++ ++ if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) ++ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON ++ break; ++ default: ++ RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n"); ++ break; ++ } ++ } ++} ++ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r819xE_phy.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_phy.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_phy.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,125 @@ ++#ifndef _R819XU_PHY_H ++#define _R819XU_PHY_H ++/* Channel switch:The size of command tables for switch channel*/ ++#define MAX_PRECMD_CNT 16 ++#define MAX_RFDEPENDCMD_CNT 16 ++#define MAX_POSTCMD_CNT 16 ++ ++#ifdef RTL8190P ++#define MACPHY_Array_PGLength 21 ++#define Rtl819XMACPHY_Array_PG Rtl8190PciMACPHY_Array_PG ++#define Rtl819XMACPHY_Array Rtl8190PciMACPHY_Array ++#define RadioC_ArrayLength 246 ++#define RadioD_ArrayLength 78 ++#define Rtl819XRadioA_Array Rtl8190PciRadioA_Array ++#define Rtl819XRadioB_Array Rtl8190PciRadioB_Array ++#define Rtl819XRadioC_Array Rtl8190PciRadioC_Array ++#define Rtl819XRadioD_Array Rtl8190PciRadioD_Array ++#define Rtl819XAGCTAB_Array Rtl8190PciAGCTAB_Array ++#define PHY_REGArrayLength 280 ++#define Rtl819XPHY_REGArray Rtl8190PciPHY_REGArray ++#define PHY_REG_1T2RArrayLength 280 ++#define Rtl819XPHY_REG_1T2RArray Rtl8190PciPHY_REG_1T2RArray ++#endif ++ ++ #ifdef RTL8192E ++ #define MACPHY_Array_PGLength 30 ++ #define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG ++ #define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array ++ #define RadioC_ArrayLength 1 ++ #define RadioD_ArrayLength 1 ++ #define Rtl819XRadioA_Array Rtl8192PciERadioA_Array ++ #define Rtl819XRadioB_Array Rtl8192PciERadioB_Array ++ #define Rtl819XRadioC_Array Rtl8192PciERadioC_Array ++ #define Rtl819XRadioD_Array Rtl8192PciERadioD_Array ++ #define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array ++ #define PHY_REGArrayLength 1 ++ #define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray ++ #define PHY_REG_1T2RArrayLength 296 ++ #define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray ++ #endif ++#define AGCTAB_ArrayLength 384 ++#define MACPHY_ArrayLength 18 ++ ++#define RadioA_ArrayLength 246 ++#define RadioB_ArrayLength 78 ++ ++ ++typedef enum _SwChnlCmdID{ ++ CmdID_End, ++ CmdID_SetTxPowerLevel, ++ CmdID_BBRegWrite10, ++ CmdID_WritePortUlong, ++ CmdID_WritePortUshort, ++ CmdID_WritePortUchar, ++ CmdID_RF_WriteReg, ++}SwChnlCmdID; ++ ++/*--------------------------------Define structure--------------------------------*/ ++/* 1. Switch channel related */ ++typedef struct _SwChnlCmd{ ++ SwChnlCmdID CmdID; ++ u32 Para1; ++ u32 Para2; ++ u32 msDelay; ++}__attribute__ ((packed)) SwChnlCmd; ++ ++extern u32 rtl819XMACPHY_Array_PG[]; ++extern u32 rtl819XPHY_REG_1T2RArray[]; ++extern u32 rtl819XAGCTAB_Array[]; ++extern u32 rtl819XRadioA_Array[]; ++extern u32 rtl819XRadioB_Array[]; ++extern u32 rtl819XRadioC_Array[]; ++extern u32 rtl819XRadioD_Array[]; ++ ++typedef enum _HW90_BLOCK{ ++ HW90_BLOCK_MAC = 0, ++ HW90_BLOCK_PHY0 = 1, ++ HW90_BLOCK_PHY1 = 2, ++ HW90_BLOCK_RF = 3, ++ HW90_BLOCK_MAXIMUM = 4, // Never use this ++}HW90_BLOCK_E, *PHW90_BLOCK_E; ++ ++typedef enum _RF90_RADIO_PATH{ ++ RF90_PATH_A = 0, //Radio Path A ++ RF90_PATH_B = 1, //Radio Path B ++ RF90_PATH_C = 2, //Radio Path C ++ RF90_PATH_D = 3, //Radio Path D ++ RF90_PATH_MAX //Max RF number 92 support ++}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E; ++ ++#define bMaskByte0 0xff ++#define bMaskByte1 0xff00 ++#define bMaskByte2 0xff0000 ++#define bMaskByte3 0xff000000 ++#define bMaskHWord 0xffff0000 ++#define bMaskLWord 0x0000ffff ++#define bMaskDWord 0xffffffff ++ ++//extern u32 rtl8192_CalculateBitShift(u32 dwBitMask); ++extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath); ++extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData); ++extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask); ++//extern u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset); ++//extern void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); ++extern void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data); ++extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask); ++extern void rtl8192_phy_configmac(struct net_device* dev); ++extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType); ++//extern void rtl8192_InitBBRFRegDef(struct net_device* dev); ++extern RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath); ++//extern RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev); ++extern RT_STATUS rtl8192_BBConfig(struct net_device* dev); ++extern void rtl8192_phy_getTxPower(struct net_device* dev); ++extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel); ++extern RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev); ++extern void rtl8192_phy_updateInitGain(struct net_device* dev); ++extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath); ++ ++extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel); ++extern void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); ++extern void rtl8192_SwChnl_WorkItem(struct net_device *dev); ++extern void rtl8192_SetBWModeWorkItem(struct net_device *dev); ++extern void InitialGain819xPci(struct net_device *dev, u8 Operation); ++ ++#endif +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r819xE_phyreg.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_phyreg.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xE_phyreg.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,878 @@ ++#ifndef _R819XU_PHYREG_H ++#define _R819XU_PHYREG_H ++ ++ ++#define RF_DATA 0x1d4 // FW will write RF data in the register. ++ ++//Register //duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++//page 1 ++#define rPMAC_Reset 0x100 ++#define rPMAC_TxStart 0x104 ++#define rPMAC_TxLegacySIG 0x108 ++#define rPMAC_TxHTSIG1 0x10c ++#define rPMAC_TxHTSIG2 0x110 ++#define rPMAC_PHYDebug 0x114 ++#define rPMAC_TxPacketNum 0x118 ++#define rPMAC_TxIdle 0x11c ++#define rPMAC_TxMACHeader0 0x120 ++#define rPMAC_TxMACHeader1 0x124 ++#define rPMAC_TxMACHeader2 0x128 ++#define rPMAC_TxMACHeader3 0x12c ++#define rPMAC_TxMACHeader4 0x130 ++#define rPMAC_TxMACHeader5 0x134 ++#define rPMAC_TxDataType 0x138 ++#define rPMAC_TxRandomSeed 0x13c ++#define rPMAC_CCKPLCPPreamble 0x140 ++#define rPMAC_CCKPLCPHeader 0x144 ++#define rPMAC_CCKCRC16 0x148 ++#define rPMAC_OFDMRxCRC32OK 0x170 ++#define rPMAC_OFDMRxCRC32Er 0x174 ++#define rPMAC_OFDMRxParityEr 0x178 ++#define rPMAC_OFDMRxCRC8Er 0x17c ++#define rPMAC_CCKCRxRC16Er 0x180 ++#define rPMAC_CCKCRxRC32Er 0x184 ++#define rPMAC_CCKCRxRC32OK 0x188 ++#define rPMAC_TxStatus 0x18c ++ ++//90P ++#define MCS_TXAGC 0x340 // MCS AGC ++#define CCK_TXAGC 0x348 // CCK AGC ++ ++//page8 ++#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC ++#define rFPGA0_TxInfo 0x804 ++#define rFPGA0_PSDFunction 0x808 ++#define rFPGA0_TxGainStage 0x80c ++#define rFPGA0_RFTiming1 0x810 ++#define rFPGA0_RFTiming2 0x814 ++//#define rFPGA0_XC_RFTiming 0x818 ++//#define rFPGA0_XD_RFTiming 0x81c ++#define rFPGA0_XA_HSSIParameter1 0x820 ++#define rFPGA0_XA_HSSIParameter2 0x824 ++#define rFPGA0_XB_HSSIParameter1 0x828 ++#define rFPGA0_XB_HSSIParameter2 0x82c ++#define rFPGA0_XC_HSSIParameter1 0x830 ++#define rFPGA0_XC_HSSIParameter2 0x834 ++#define rFPGA0_XD_HSSIParameter1 0x838 ++#define rFPGA0_XD_HSSIParameter2 0x83c ++#define rFPGA0_XA_LSSIParameter 0x840 ++#define rFPGA0_XB_LSSIParameter 0x844 ++#define rFPGA0_XC_LSSIParameter 0x848 ++#define rFPGA0_XD_LSSIParameter 0x84c ++#define rFPGA0_RFWakeUpParameter 0x850 ++#define rFPGA0_RFSleepUpParameter 0x854 ++#define rFPGA0_XAB_SwitchControl 0x858 ++#define rFPGA0_XCD_SwitchControl 0x85c ++#define rFPGA0_XA_RFInterfaceOE 0x860 ++#define rFPGA0_XB_RFInterfaceOE 0x864 ++#define rFPGA0_XC_RFInterfaceOE 0x868 ++#define rFPGA0_XD_RFInterfaceOE 0x86c ++#define rFPGA0_XAB_RFInterfaceSW 0x870 ++#define rFPGA0_XCD_RFInterfaceSW 0x874 ++#define rFPGA0_XAB_RFParameter 0x878 ++#define rFPGA0_XCD_RFParameter 0x87c ++#define rFPGA0_AnalogParameter1 0x880 ++#define rFPGA0_AnalogParameter2 0x884 ++#define rFPGA0_AnalogParameter3 0x888 ++#define rFPGA0_AnalogParameter4 0x88c ++#define rFPGA0_XA_LSSIReadBack 0x8a0 ++#define rFPGA0_XB_LSSIReadBack 0x8a4 ++#define rFPGA0_XC_LSSIReadBack 0x8a8 ++#define rFPGA0_XD_LSSIReadBack 0x8ac ++#define rFPGA0_PSDReport 0x8b4 ++#define rFPGA0_XAB_RFInterfaceRB 0x8e0 ++#define rFPGA0_XCD_RFInterfaceRB 0x8e4 ++ ++//page 9 ++#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC ++#define rFPGA1_TxBlock 0x904 ++#define rFPGA1_DebugSelect 0x908 ++#define rFPGA1_TxInfo 0x90c ++ ++//page a ++#define rCCK0_System 0xa00 ++#define rCCK0_AFESetting 0xa04 ++#define rCCK0_CCA 0xa08 ++#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level ++#define rCCK0_RxAGC2 0xa10 //AGC & DAGC ++#define rCCK0_RxHP 0xa14 ++#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold ++#define rCCK0_DSPParameter2 0xa1c //SQ threshold ++#define rCCK0_TxFilter1 0xa20 ++#define rCCK0_TxFilter2 0xa24 ++#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 ++#define rCCK0_FalseAlarmReport 0xa2c //0xa2d ++#define rCCK0_TRSSIReport 0xa50 ++#define rCCK0_RxReport 0xa54 //0xa57 ++#define rCCK0_FACounterLower 0xa5c //0xa5b ++#define rCCK0_FACounterUpper 0xa58 //0xa5c ++ ++//page c ++#define rOFDM0_LSTF 0xc00 ++#define rOFDM0_TRxPathEnable 0xc04 ++#define rOFDM0_TRMuxPar 0xc08 ++#define rOFDM0_TRSWIsolation 0xc0c ++#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter ++#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix ++#define rOFDM0_XBRxAFE 0xc18 ++#define rOFDM0_XBRxIQImbalance 0xc1c ++#define rOFDM0_XCRxAFE 0xc20 ++#define rOFDM0_XCRxIQImbalance 0xc24 ++#define rOFDM0_XDRxAFE 0xc28 ++#define rOFDM0_XDRxIQImbalance 0xc2c ++#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD ++#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. ++#define rOFDM0_RxDetector3 0xc38 //Frame Sync. ++#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI ++#define rOFDM0_RxDSP 0xc40 //Rx Sync Path ++#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC ++#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold ++#define rOFDM0_ECCAThreshold 0xc4c // energy CCA ++#define rOFDM0_XAAGCCore1 0xc50 ++#define rOFDM0_XAAGCCore2 0xc54 ++#define rOFDM0_XBAGCCore1 0xc58 ++#define rOFDM0_XBAGCCore2 0xc5c ++#define rOFDM0_XCAGCCore1 0xc60 ++#define rOFDM0_XCAGCCore2 0xc64 ++#define rOFDM0_XDAGCCore1 0xc68 ++#define rOFDM0_XDAGCCore2 0xc6c ++#define rOFDM0_AGCParameter1 0xc70 ++#define rOFDM0_AGCParameter2 0xc74 ++#define rOFDM0_AGCRSSITable 0xc78 ++#define rOFDM0_HTSTFAGC 0xc7c ++#define rOFDM0_XATxIQImbalance 0xc80 ++#define rOFDM0_XATxAFE 0xc84 ++#define rOFDM0_XBTxIQImbalance 0xc88 ++#define rOFDM0_XBTxAFE 0xc8c ++#define rOFDM0_XCTxIQImbalance 0xc90 ++#define rOFDM0_XCTxAFE 0xc94 ++#define rOFDM0_XDTxIQImbalance 0xc98 ++#define rOFDM0_XDTxAFE 0xc9c ++#define rOFDM0_RxHPParameter 0xce0 ++#define rOFDM0_TxPseudoNoiseWgt 0xce4 ++#define rOFDM0_FrameSync 0xcf0 ++#define rOFDM0_DFSReport 0xcf4 ++#define rOFDM0_TxCoeff1 0xca4 ++#define rOFDM0_TxCoeff2 0xca8 ++#define rOFDM0_TxCoeff3 0xcac ++#define rOFDM0_TxCoeff4 0xcb0 ++#define rOFDM0_TxCoeff5 0xcb4 ++#define rOFDM0_TxCoeff6 0xcb8 ++ ++ ++//page d ++#define rOFDM1_LSTF 0xd00 ++#define rOFDM1_TRxPathEnable 0xd04 ++#define rOFDM1_CFO 0xd08 ++#define rOFDM1_CSI1 0xd10 ++#define rOFDM1_SBD 0xd14 ++#define rOFDM1_CSI2 0xd18 ++#define rOFDM1_CFOTracking 0xd2c ++#define rOFDM1_TRxMesaure1 0xd34 ++#define rOFDM1_IntfDet 0xd3c ++#define rOFDM1_PseudoNoiseStateAB 0xd50 ++#define rOFDM1_PseudoNoiseStateCD 0xd54 ++#define rOFDM1_RxPseudoNoiseWgt 0xd58 ++#define rOFDM_PHYCounter1 0xda0 //cca, parity fail ++#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail ++#define rOFDM_PHYCounter3 0xda8 //MCS not support ++#define rOFDM_ShortCFOAB 0xdac ++#define rOFDM_ShortCFOCD 0xdb0 ++#define rOFDM_LongCFOAB 0xdb4 ++#define rOFDM_LongCFOCD 0xdb8 ++#define rOFDM_TailCFOAB 0xdbc ++#define rOFDM_TailCFOCD 0xdc0 ++#define rOFDM_PWMeasure1 0xdc4 ++#define rOFDM_PWMeasure2 0xdc8 ++#define rOFDM_BWReport 0xdcc ++#define rOFDM_AGCReport 0xdd0 ++#define rOFDM_RxSNR 0xdd4 ++#define rOFDM_RxEVMCSI 0xdd8 ++#define rOFDM_SIGReport 0xddc ++ ++//page e ++#define rTxAGC_Rate18_06 0xe00 ++#define rTxAGC_Rate54_24 0xe04 ++#define rTxAGC_CCK_Mcs32 0xe08 ++#define rTxAGC_Mcs03_Mcs00 0xe10 ++#define rTxAGC_Mcs07_Mcs04 0xe14 ++#define rTxAGC_Mcs11_Mcs08 0xe18 ++#define rTxAGC_Mcs15_Mcs12 0xe1c ++ ++ ++//RF ++//Zebra1 ++#define rZebra1_HSSIEnable 0x0 ++#define rZebra1_TRxEnable1 0x1 ++#define rZebra1_TRxEnable2 0x2 ++#define rZebra1_AGC 0x4 ++#define rZebra1_ChargePump 0x5 ++#define rZebra1_Channel 0x7 ++#define rZebra1_TxGain 0x8 ++#define rZebra1_TxLPF 0x9 ++#define rZebra1_RxLPF 0xb ++#define rZebra1_RxHPFCorner 0xc ++ ++//Zebra4 ++#define rGlobalCtrl 0 ++#define rRTL8256_TxLPF 19 ++#define rRTL8256_RxLPF 11 ++ ++//RTL8258 ++#define rRTL8258_TxLPF 0x11 ++#define rRTL8258_RxLPF 0x13 ++#define rRTL8258_RSSILPF 0xa ++ ++//Bit Mask ++//page-1 ++#define bBBResetB 0x100 ++#define bGlobalResetB 0x200 ++#define bOFDMTxStart 0x4 ++#define bCCKTxStart 0x8 ++#define bCRC32Debug 0x100 ++#define bPMACLoopback 0x10 ++#define bTxLSIG 0xffffff ++#define bOFDMTxRate 0xf ++#define bOFDMTxReserved 0x10 ++#define bOFDMTxLength 0x1ffe0 ++#define bOFDMTxParity 0x20000 ++#define bTxHTSIG1 0xffffff ++#define bTxHTMCSRate 0x7f ++#define bTxHTBW 0x80 ++#define bTxHTLength 0xffff00 ++#define bTxHTSIG2 0xffffff ++#define bTxHTSmoothing 0x1 ++#define bTxHTSounding 0x2 ++#define bTxHTReserved 0x4 ++#define bTxHTAggreation 0x8 ++#define bTxHTSTBC 0x30 ++#define bTxHTAdvanceCoding 0x40 ++#define bTxHTShortGI 0x80 ++#define bTxHTNumberHT_LTF 0x300 ++#define bTxHTCRC8 0x3fc00 ++#define bCounterReset 0x10000 ++#define bNumOfOFDMTx 0xffff ++#define bNumOfCCKTx 0xffff0000 ++#define bTxIdleInterval 0xffff ++#define bOFDMService 0xffff0000 ++#define bTxMACHeader 0xffffffff ++#define bTxDataInit 0xff ++#define bTxHTMode 0x100 ++#define bTxDataType 0x30000 ++#define bTxRandomSeed 0xffffffff ++#define bCCKTxPreamble 0x1 ++#define bCCKTxSFD 0xffff0000 ++#define bCCKTxSIG 0xff ++#define bCCKTxService 0xff00 ++#define bCCKLengthExt 0x8000 ++#define bCCKTxLength 0xffff0000 ++#define bCCKTxCRC16 0xffff ++#define bCCKTxStatus 0x1 ++#define bOFDMTxStatus 0x2 ++ ++//page-8 ++#define bRFMOD 0x1 ++#define bJapanMode 0x2 ++#define bCCKTxSC 0x30 ++#define bCCKEn 0x1000000 ++#define bOFDMEn 0x2000000 ++#define bOFDMRxADCPhase 0x10000 ++#define bOFDMTxDACPhase 0x40000 ++#define bXATxAGC 0x3f ++#define bXBTxAGC 0xf00 ++#define bXCTxAGC 0xf000 ++#define bXDTxAGC 0xf0000 ++#define bPAStart 0xf0000000 ++#define bTRStart 0x00f00000 ++#define bRFStart 0x0000f000 ++#define bBBStart 0x000000f0 ++#define bBBCCKStart 0x0000000f ++#define bPAEnd 0xf //Reg0x814 ++#define bTREnd 0x0f000000 ++#define bRFEnd 0x000f0000 ++#define bCCAMask 0x000000f0 //T2R ++#define bR2RCCAMask 0x00000f00 ++#define bHSSI_R2TDelay 0xf8000000 ++#define bHSSI_T2RDelay 0xf80000 ++#define bContTxHSSI 0x400 //chane gain at continue Tx ++#define bIGFromCCK 0x200 ++#define bAGCAddress 0x3f ++#define bRxHPTx 0x7000 ++#define bRxHPT2R 0x38000 ++#define bRxHPCCKIni 0xc0000 ++#define bAGCTxCode 0xc00000 ++#define bAGCRxCode 0x300000 ++#define b3WireDataLength 0x800 ++#define b3WireAddressLength 0x400 ++#define b3WireRFPowerDown 0x1 ++//#define bHWSISelect 0x8 ++#define b5GPAPEPolarity 0x40000000 ++#define b2GPAPEPolarity 0x80000000 ++#define bRFSW_TxDefaultAnt 0x3 ++#define bRFSW_TxOptionAnt 0x30 ++#define bRFSW_RxDefaultAnt 0x300 ++#define bRFSW_RxOptionAnt 0x3000 ++#define bRFSI_3WireData 0x1 ++#define bRFSI_3WireClock 0x2 ++#define bRFSI_3WireLoad 0x4 ++#define bRFSI_3WireRW 0x8 ++#define bRFSI_3Wire 0xf //3-wire total control ++#define bRFSI_RFENV 0x10 ++#define bRFSI_TRSW 0x20 ++#define bRFSI_TRSWB 0x40 ++#define bRFSI_ANTSW 0x100 ++#define bRFSI_ANTSWB 0x200 ++#define bRFSI_PAPE 0x400 ++#define bRFSI_PAPE5G 0x800 ++#define bBandSelect 0x1 ++#define bHTSIG2_GI 0x80 ++#define bHTSIG2_Smoothing 0x01 ++#define bHTSIG2_Sounding 0x02 ++#define bHTSIG2_Aggreaton 0x08 ++#define bHTSIG2_STBC 0x30 ++#define bHTSIG2_AdvCoding 0x40 ++#define bHTSIG2_NumOfHTLTF 0x300 ++#define bHTSIG2_CRC8 0x3fc ++#define bHTSIG1_MCS 0x7f ++#define bHTSIG1_BandWidth 0x80 ++#define bHTSIG1_HTLength 0xffff ++#define bLSIG_Rate 0xf ++#define bLSIG_Reserved 0x10 ++#define bLSIG_Length 0x1fffe ++#define bLSIG_Parity 0x20 ++#define bCCKRxPhase 0x4 ++#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address ++#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal ++#define bLSSIReadBackData 0xfff ++#define bLSSIReadOKFlag 0x1000 ++#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz ++ ++#define bRegulator0Standby 0x1 ++#define bRegulatorPLLStandby 0x2 ++#define bRegulator1Standby 0x4 ++#define bPLLPowerUp 0x8 ++#define bDPLLPowerUp 0x10 ++#define bDA10PowerUp 0x20 ++#define bAD7PowerUp 0x200 ++#define bDA6PowerUp 0x2000 ++#define bXtalPowerUp 0x4000 ++#define b40MDClkPowerUP 0x8000 ++#define bDA6DebugMode 0x20000 ++#define bDA6Swing 0x380000 ++#define bADClkPhase 0x4000000 ++#define b80MClkDelay 0x18000000 ++#define bAFEWatchDogEnable 0x20000000 ++#define bXtalCap 0x0f000000 ++#define bXtalCap01 0xc0000000 ++#define bXtalCap23 0x3 ++#define bXtalCap92x 0x0f000000 ++#define bIntDifClkEnable 0x400 ++#define bExtSigClkEnable 0x800 ++#define bBandgapMbiasPowerUp 0x10000 ++#define bAD11SHGain 0xc0000 ++#define bAD11InputRange 0x700000 ++#define bAD11OPCurrent 0x3800000 ++#define bIPathLoopback 0x4000000 ++#define bQPathLoopback 0x8000000 ++#define bAFELoopback 0x10000000 ++#define bDA10Swing 0x7e0 ++#define bDA10Reverse 0x800 ++#define bDAClkSource 0x1000 ++#define bAD7InputRange 0x6000 ++#define bAD7Gain 0x38000 ++#define bAD7OutputCMMode 0x40000 ++#define bAD7InputCMMode 0x380000 ++#define bAD7Current 0xc00000 ++#define bRegulatorAdjust 0x7000000 ++#define bAD11PowerUpAtTx 0x1 ++#define bDA10PSAtTx 0x10 ++#define bAD11PowerUpAtRx 0x100 ++#define bDA10PSAtRx 0x1000 ++ ++#define bCCKRxAGCFormat 0x200 ++ ++#define bPSDFFTSamplepPoint 0xc000 ++#define bPSDAverageNum 0x3000 ++#define bIQPathControl 0xc00 ++#define bPSDFreq 0x3ff ++#define bPSDAntennaPath 0x30 ++#define bPSDIQSwitch 0x40 ++#define bPSDRxTrigger 0x400000 ++#define bPSDTxTrigger 0x80000000 ++#define bPSDSineToneScale 0x7f000000 ++#define bPSDReport 0xffff ++ ++//page-9 ++#define bOFDMTxSC 0x30000000 ++#define bCCKTxOn 0x1 ++#define bOFDMTxOn 0x2 ++#define bDebugPage 0xfff //reset debug page and also HWord, LWord ++#define bDebugItem 0xff //reset debug page and LWord ++#define bAntL 0x10 ++#define bAntNonHT 0x100 ++#define bAntHT1 0x1000 ++#define bAntHT2 0x10000 ++#define bAntHT1S1 0x100000 ++#define bAntNonHTS1 0x1000000 ++ ++//page-a ++#define bCCKBBMode 0x3 ++#define bCCKTxPowerSaving 0x80 ++#define bCCKRxPowerSaving 0x40 ++#define bCCKSideBand 0x10 ++#define bCCKScramble 0x8 ++#define bCCKAntDiversity 0x8000 ++#define bCCKCarrierRecovery 0x4000 ++#define bCCKTxRate 0x3000 ++#define bCCKDCCancel 0x0800 ++#define bCCKISICancel 0x0400 ++#define bCCKMatchFilter 0x0200 ++#define bCCKEqualizer 0x0100 ++#define bCCKPreambleDetect 0x800000 ++#define bCCKFastFalseCCA 0x400000 ++#define bCCKChEstStart 0x300000 ++#define bCCKCCACount 0x080000 ++#define bCCKcs_lim 0x070000 ++#define bCCKBistMode 0x80000000 ++#define bCCKCCAMask 0x40000000 ++#define bCCKTxDACPhase 0x4 ++#define bCCKRxADCPhase 0x20000000 //r_rx_clk ++#define bCCKr_cp_mode0 0x0100 ++#define bCCKTxDCOffset 0xf0 ++#define bCCKRxDCOffset 0xf ++#define bCCKCCAMode 0xc000 ++#define bCCKFalseCS_lim 0x3f00 ++#define bCCKCS_ratio 0xc00000 ++#define bCCKCorgBit_sel 0x300000 ++#define bCCKPD_lim 0x0f0000 ++#define bCCKNewCCA 0x80000000 ++#define bCCKRxHPofIG 0x8000 ++#define bCCKRxIG 0x7f00 ++#define bCCKLNAPolarity 0x800000 ++#define bCCKRx1stGain 0x7f0000 ++#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity ++#define bCCKRxAGCSatLevel 0x1f000000 ++#define bCCKRxAGCSatCount 0xe0 ++#define bCCKRxRFSettle 0x1f //AGCsamp_dly ++#define bCCKFixedRxAGC 0x8000 ++//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 ++#define bCCKAntennaPolarity 0x2000 ++#define bCCKTxFilterType 0x0c00 ++#define bCCKRxAGCReportType 0x0300 ++#define bCCKRxDAGCEn 0x80000000 ++#define bCCKRxDAGCPeriod 0x20000000 ++#define bCCKRxDAGCSatLevel 0x1f000000 ++#define bCCKTimingRecovery 0x800000 ++#define bCCKTxC0 0x3f0000 ++#define bCCKTxC1 0x3f000000 ++#define bCCKTxC2 0x3f ++#define bCCKTxC3 0x3f00 ++#define bCCKTxC4 0x3f0000 ++#define bCCKTxC5 0x3f000000 ++#define bCCKTxC6 0x3f ++#define bCCKTxC7 0x3f00 ++#define bCCKDebugPort 0xff0000 ++#define bCCKDACDebug 0x0f000000 ++#define bCCKFalseAlarmEnable 0x8000 ++#define bCCKFalseAlarmRead 0x4000 ++#define bCCKTRSSI 0x7f ++#define bCCKRxAGCReport 0xfe ++#define bCCKRxReport_AntSel 0x80000000 ++#define bCCKRxReport_MFOff 0x40000000 ++#define bCCKRxRxReport_SQLoss 0x20000000 ++#define bCCKRxReport_Pktloss 0x10000000 ++#define bCCKRxReport_Lockedbit 0x08000000 ++#define bCCKRxReport_RateError 0x04000000 ++#define bCCKRxReport_RxRate 0x03000000 ++#define bCCKRxFACounterLower 0xff ++#define bCCKRxFACounterUpper 0xff000000 ++#define bCCKRxHPAGCStart 0xe000 ++#define bCCKRxHPAGCFinal 0x1c00 ++ ++#define bCCKRxFalseAlarmEnable 0x8000 ++#define bCCKFACounterFreeze 0x4000 ++ ++#define bCCKTxPathSel 0x10000000 ++#define bCCKDefaultRxPath 0xc000000 ++#define bCCKOptionRxPath 0x3000000 ++ ++//page c ++#define bNumOfSTF 0x3 ++#define bShift_L 0xc0 ++#define bGI_TH 0xc ++#define bRxPathA 0x1 ++#define bRxPathB 0x2 ++#define bRxPathC 0x4 ++#define bRxPathD 0x8 ++#define bTxPathA 0x1 ++#define bTxPathB 0x2 ++#define bTxPathC 0x4 ++#define bTxPathD 0x8 ++#define bTRSSIFreq 0x200 ++#define bADCBackoff 0x3000 ++#define bDFIRBackoff 0xc000 ++#define bTRSSILatchPhase 0x10000 ++#define bRxIDCOffset 0xff ++#define bRxQDCOffset 0xff00 ++#define bRxDFIRMode 0x1800000 ++#define bRxDCNFType 0xe000000 ++#define bRXIQImb_A 0x3ff ++#define bRXIQImb_B 0xfc00 ++#define bRXIQImb_C 0x3f0000 ++#define bRXIQImb_D 0xffc00000 ++#define bDC_dc_Notch 0x60000 ++#define bRxNBINotch 0x1f000000 ++#define bPD_TH 0xf ++#define bPD_TH_Opt2 0xc000 ++#define bPWED_TH 0x700 ++#define bIfMF_Win_L 0x800 ++#define bPD_Option 0x1000 ++#define bMF_Win_L 0xe000 ++#define bBW_Search_L 0x30000 ++#define bwin_enh_L 0xc0000 ++#define bBW_TH 0x700000 ++#define bED_TH2 0x3800000 ++#define bBW_option 0x4000000 ++#define bRatio_TH 0x18000000 ++#define bWindow_L 0xe0000000 ++#define bSBD_Option 0x1 ++#define bFrame_TH 0x1c ++#define bFS_Option 0x60 ++#define bDC_Slope_check 0x80 ++#define bFGuard_Counter_DC_L 0xe00 ++#define bFrame_Weight_Short 0x7000 ++#define bSub_Tune 0xe00000 ++#define bFrame_DC_Length 0xe000000 ++#define bSBD_start_offset 0x30000000 ++#define bFrame_TH_2 0x7 ++#define bFrame_GI2_TH 0x38 ++#define bGI2_Sync_en 0x40 ++#define bSarch_Short_Early 0x300 ++#define bSarch_Short_Late 0xc00 ++#define bSarch_GI2_Late 0x70000 ++#define bCFOAntSum 0x1 ++#define bCFOAcc 0x2 ++#define bCFOStartOffset 0xc ++#define bCFOLookBack 0x70 ++#define bCFOSumWeight 0x80 ++#define bDAGCEnable 0x10000 ++#define bTXIQImb_A 0x3ff ++#define bTXIQImb_B 0xfc00 ++#define bTXIQImb_C 0x3f0000 ++#define bTXIQImb_D 0xffc00000 ++#define bTxIDCOffset 0xff ++#define bTxQDCOffset 0xff00 ++#define bTxDFIRMode 0x10000 ++#define bTxPesudoNoiseOn 0x4000000 ++#define bTxPesudoNoise_A 0xff ++#define bTxPesudoNoise_B 0xff00 ++#define bTxPesudoNoise_C 0xff0000 ++#define bTxPesudoNoise_D 0xff000000 ++#define bCCADropOption 0x20000 ++#define bCCADropThres 0xfff00000 ++#define bEDCCA_H 0xf ++#define bEDCCA_L 0xf0 ++#define bLambda_ED 0x300 ++#define bRxInitialGain 0x7f ++#define bRxAntDivEn 0x80 ++#define bRxAGCAddressForLNA 0x7f00 ++#define bRxHighPowerFlow 0x8000 ++#define bRxAGCFreezeThres 0xc0000 ++#define bRxFreezeStep_AGC1 0x300000 ++#define bRxFreezeStep_AGC2 0xc00000 ++#define bRxFreezeStep_AGC3 0x3000000 ++#define bRxFreezeStep_AGC0 0xc000000 ++#define bRxRssi_Cmp_En 0x10000000 ++#define bRxQuickAGCEn 0x20000000 ++#define bRxAGCFreezeThresMode 0x40000000 ++#define bRxOverFlowCheckType 0x80000000 ++#define bRxAGCShift 0x7f ++#define bTRSW_Tri_Only 0x80 ++#define bPowerThres 0x300 ++#define bRxAGCEn 0x1 ++#define bRxAGCTogetherEn 0x2 ++#define bRxAGCMin 0x4 ++#define bRxHP_Ini 0x7 ++#define bRxHP_TRLNA 0x70 ++#define bRxHP_RSSI 0x700 ++#define bRxHP_BBP1 0x7000 ++#define bRxHP_BBP2 0x70000 ++#define bRxHP_BBP3 0x700000 ++#define bRSSI_H 0x7f0000 //the threshold for high power ++#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity ++#define bRxSettle_TRSW 0x7 ++#define bRxSettle_LNA 0x38 ++#define bRxSettle_RSSI 0x1c0 ++#define bRxSettle_BBP 0xe00 ++#define bRxSettle_RxHP 0x7000 ++#define bRxSettle_AntSW_RSSI 0x38000 ++#define bRxSettle_AntSW 0xc0000 ++#define bRxProcessTime_DAGC 0x300000 ++#define bRxSettle_HSSI 0x400000 ++#define bRxProcessTime_BBPPW 0x800000 ++#define bRxAntennaPowerShift 0x3000000 ++#define bRSSITableSelect 0xc000000 ++#define bRxHP_Final 0x7000000 ++#define bRxHTSettle_BBP 0x7 ++#define bRxHTSettle_HSSI 0x8 ++#define bRxHTSettle_RxHP 0x70 ++#define bRxHTSettle_BBPPW 0x80 ++#define bRxHTSettle_Idle 0x300 ++#define bRxHTSettle_Reserved 0x1c00 ++#define bRxHTRxHPEn 0x8000 ++#define bRxHTAGCFreezeThres 0x30000 ++#define bRxHTAGCTogetherEn 0x40000 ++#define bRxHTAGCMin 0x80000 ++#define bRxHTAGCEn 0x100000 ++#define bRxHTDAGCEn 0x200000 ++#define bRxHTRxHP_BBP 0x1c00000 ++#define bRxHTRxHP_Final 0xe0000000 ++#define bRxPWRatioTH 0x3 ++#define bRxPWRatioEn 0x4 ++#define bRxMFHold 0x3800 ++#define bRxPD_Delay_TH1 0x38 ++#define bRxPD_Delay_TH2 0x1c0 ++#define bRxPD_DC_COUNT_MAX 0x600 ++//#define bRxMF_Hold 0x3800 ++#define bRxPD_Delay_TH 0x8000 ++#define bRxProcess_Delay 0xf0000 ++#define bRxSearchrange_GI2_Early 0x700000 ++#define bRxFrame_Guard_Counter_L 0x3800000 ++#define bRxSGI_Guard_L 0xc000000 ++#define bRxSGI_Search_L 0x30000000 ++#define bRxSGI_TH 0xc0000000 ++#define bDFSCnt0 0xff ++#define bDFSCnt1 0xff00 ++#define bDFSFlag 0xf0000 ++ ++#define bMFWeightSum 0x300000 ++#define bMinIdxTH 0x7f000000 ++ ++#define bDAFormat 0x40000 ++ ++#define bTxChEmuEnable 0x01000000 ++ ++#define bTRSWIsolation_A 0x7f ++#define bTRSWIsolation_B 0x7f00 ++#define bTRSWIsolation_C 0x7f0000 ++#define bTRSWIsolation_D 0x7f000000 ++ ++#define bExtLNAGain 0x7c00 ++ ++//page d ++#define bSTBCEn 0x4 ++#define bAntennaMapping 0x10 ++#define bNss 0x20 ++#define bCFOAntSumD 0x200 ++#define bPHYCounterReset 0x8000000 ++#define bCFOReportGet 0x4000000 ++#define bOFDMContinueTx 0x10000000 ++#define bOFDMSingleCarrier 0x20000000 ++#define bOFDMSingleTone 0x40000000 ++//#define bRxPath1 0x01 ++//#define bRxPath2 0x02 ++//#define bRxPath3 0x04 ++//#define bRxPath4 0x08 ++//#define bTxPath1 0x10 ++//#define bTxPath2 0x20 ++#define bHTDetect 0x100 ++#define bCFOEn 0x10000 ++#define bCFOValue 0xfff00000 ++#define bSigTone_Re 0x3f ++#define bSigTone_Im 0x7f00 ++#define bCounter_CCA 0xffff ++#define bCounter_ParityFail 0xffff0000 ++#define bCounter_RateIllegal 0xffff ++#define bCounter_CRC8Fail 0xffff0000 ++#define bCounter_MCSNoSupport 0xffff ++#define bCounter_FastSync 0xffff ++#define bShortCFO 0xfff ++#define bShortCFOTLength 12 //total ++#define bShortCFOFLength 11 //fraction ++#define bLongCFO 0x7ff ++#define bLongCFOTLength 11 ++#define bLongCFOFLength 11 ++#define bTailCFO 0x1fff ++#define bTailCFOTLength 13 ++#define bTailCFOFLength 12 ++ ++#define bmax_en_pwdB 0xffff ++#define bCC_power_dB 0xffff0000 ++#define bnoise_pwdB 0xffff ++#define bPowerMeasTLength 10 ++#define bPowerMeasFLength 3 ++#define bRx_HT_BW 0x1 ++#define bRxSC 0x6 ++#define bRx_HT 0x8 ++ ++#define bNB_intf_det_on 0x1 ++#define bIntf_win_len_cfg 0x30 ++#define bNB_Intf_TH_cfg 0x1c0 ++ ++#define bRFGain 0x3f ++#define bTableSel 0x40 ++#define bTRSW 0x80 ++ ++#define bRxSNR_A 0xff ++#define bRxSNR_B 0xff00 ++#define bRxSNR_C 0xff0000 ++#define bRxSNR_D 0xff000000 ++#define bSNREVMTLength 8 ++#define bSNREVMFLength 1 ++ ++#define bCSI1st 0xff ++#define bCSI2nd 0xff00 ++#define bRxEVM1st 0xff0000 ++#define bRxEVM2nd 0xff000000 ++ ++#define bSIGEVM 0xff ++#define bPWDB 0xff00 ++#define bSGIEN 0x10000 ++ ++#define bSFactorQAM1 0xf ++#define bSFactorQAM2 0xf0 ++#define bSFactorQAM3 0xf00 ++#define bSFactorQAM4 0xf000 ++#define bSFactorQAM5 0xf0000 ++#define bSFactorQAM6 0xf0000 ++#define bSFactorQAM7 0xf00000 ++#define bSFactorQAM8 0xf000000 ++#define bSFactorQAM9 0xf0000000 ++#define bCSIScheme 0x100000 ++ ++#define bNoiseLvlTopSet 0x3 ++#define bChSmooth 0x4 ++#define bChSmoothCfg1 0x38 ++#define bChSmoothCfg2 0x1c0 ++#define bChSmoothCfg3 0xe00 ++#define bChSmoothCfg4 0x7000 ++#define bMRCMode 0x800000 ++#define bTHEVMCfg 0x7000000 ++ ++#define bLoopFitType 0x1 ++#define bUpdCFO 0x40 ++#define bUpdCFOOffData 0x80 ++#define bAdvUpdCFO 0x100 ++#define bAdvTimeCtrl 0x800 ++#define bUpdClko 0x1000 ++#define bFC 0x6000 ++#define bTrackingMode 0x8000 ++#define bPhCmpEnable 0x10000 ++#define bUpdClkoLTF 0x20000 ++#define bComChCFO 0x40000 ++#define bCSIEstiMode 0x80000 ++#define bAdvUpdEqz 0x100000 ++#define bUChCfg 0x7000000 ++#define bUpdEqz 0x8000000 ++ ++//page e ++#define bTxAGCRate18_06 0x7f7f7f7f ++#define bTxAGCRate54_24 0x7f7f7f7f ++#define bTxAGCRateMCS32 0x7f ++#define bTxAGCRateCCK 0x7f00 ++#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f ++#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f ++#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f ++#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f ++ ++ ++//Rx Pseduo noise ++#define bRxPesudoNoiseOn 0x20000000 ++#define bRxPesudoNoise_A 0xff ++#define bRxPesudoNoise_B 0xff00 ++#define bRxPesudoNoise_C 0xff0000 ++#define bRxPesudoNoise_D 0xff000000 ++#define bPesudoNoiseState_A 0xffff ++#define bPesudoNoiseState_B 0xffff0000 ++#define bPesudoNoiseState_C 0xffff ++#define bPesudoNoiseState_D 0xffff0000 ++ ++//RF ++//Zebra1 ++#define bZebra1_HSSIEnable 0x8 ++#define bZebra1_TRxControl 0xc00 ++#define bZebra1_TRxGainSetting 0x07f ++#define bZebra1_RxCorner 0xc00 ++#define bZebra1_TxChargePump 0x38 ++#define bZebra1_RxChargePump 0x7 ++#define bZebra1_ChannelNum 0xf80 ++#define bZebra1_TxLPFBW 0x400 ++#define bZebra1_RxLPFBW 0x600 ++ ++//Zebra4 ++#define bRTL8256RegModeCtrl1 0x100 ++#define bRTL8256RegModeCtrl0 0x40 ++#define bRTL8256_TxLPFBW 0x18 ++#define bRTL8256_RxLPFBW 0x600 ++ ++//RTL8258 ++#define bRTL8258_TxLPFBW 0xc ++#define bRTL8258_RxLPFBW 0xc00 ++#define bRTL8258_RSSILPFBW 0xc0 ++ ++//byte endable for sb_write ++#define bByte0 0x1 ++#define bByte1 0x2 ++#define bByte2 0x4 ++#define bByte3 0x8 ++#define bWord0 0x3 ++#define bWord1 0xc ++#define bDWord 0xf ++ ++//for PutRegsetting & GetRegSetting BitMask ++#define bMaskByte0 0xff ++#define bMaskByte1 0xff00 ++#define bMaskByte2 0xff0000 ++#define bMaskByte3 0xff000000 ++#define bMaskHWord 0xffff0000 ++#define bMaskLWord 0x0000ffff ++#define bMaskDWord 0xffffffff ++ ++//for PutRFRegsetting & GetRFRegSetting BitMask ++#define bMask12Bits 0xfff ++ ++#define bEnable 0x1 ++#define bDisable 0x0 ++ ++#define LeftAntenna 0x0 ++#define RightAntenna 0x1 ++ ++#define tCheckTxStatus 500 //500ms ++#define tUpdateRxCounter 100 //100ms ++ ++#define rateCCK 0 ++#define rateOFDM 1 ++#define rateHT 2 ++ ++//define Register-End ++#define bPMAC_End 0x1ff ++#define bFPGAPHY0_End 0x8ff ++#define bFPGAPHY1_End 0x9ff ++#define bCCKPHY0_End 0xaff ++#define bOFDMPHY0_End 0xcff ++#define bOFDMPHY1_End 0xdff ++ ++//define max debug item in each debug page ++//#define bMaxItem_FPGA_PHY0 0x9 ++//#define bMaxItem_FPGA_PHY1 0x3 ++//#define bMaxItem_PHY_11B 0x16 ++//#define bMaxItem_OFDM_PHY0 0x29 ++//#define bMaxItem_OFDM_PHY1 0x0 ++ ++#define bPMACControl 0x0 ++#define bWMACControl 0x1 ++#define bWNICControl 0x2 ++ ++#define PathA 0x0 ++#define PathB 0x1 ++#define PathC 0x2 ++#define PathD 0x3 ++ ++#define rRTL8256RxMixerPole 0xb ++#define bZebraRxMixerPole 0x6 ++#define rRTL8256TxBBOPBias 0x9 ++#define bRTL8256TxBBOPBias 0x400 ++#define rRTL8256TxBBBW 19 ++#define bRTL8256TxBBBW 0x18 ++ ++#endif //__INC_HAL8190PCIPHYREG_H +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/staging/rtl8192e/r819xP_firmware_img.h linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xP_firmware_img.h +--- /dev/null 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/staging/rtl8192e/r819xP_firmware_img.h 2009-08-27 12:44:29.000000000 +0100 +@@ -0,0 +1,3637 @@ ++#ifndef __INC_R819XU_FIRMWARE_IMG_H ++#define __INC_R819XU_FIRMWARE_IMG_H ++/*Created on 2008/ 5/19, 6:38*/ ++#include ++ ++u8 rtl8190_fwboot_array[] = { ++0x10,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x3c,0x08,0xbf,0xc0,0x25,0x08,0x00,0x08, ++0x3c,0x09,0xb0,0x03,0xad,0x28,0x00,0x20,0x40,0x80,0x68,0x00,0x00,0x00,0x00,0x00, ++0x3c,0x0a,0xd0,0x00,0x40,0x8a,0x60,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01, ++0x25,0x08,0xd6,0x04,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff, ++0x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01,0x01,0x2a,0x10,0x2b, ++0x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x00,0x00,0x25,0x4a,0x00,0x00, ++0x4c,0x8a,0x00,0x00,0x4c,0x89,0x08,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01, ++0x25,0x08,0xd6,0x04,0x3c,0x01,0x80,0x00,0x01,0x21,0x48,0x25,0x3c,0x0a,0xbf,0xc0, ++0x25,0x4a,0x00,0x7c,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0xad,0x00,0x00,0x00, ++0x21,0x08,0x00,0x04,0x01,0x09,0x10,0x2b,0x14,0x40,0xff,0xf8,0x00,0x00,0x00,0x00, ++0x3c,0x08,0x80,0x01,0x25,0x08,0x7f,0xff,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff, ++0x34,0x21,0xff,0xff,0x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01, ++0x01,0x2a,0x10,0x2b,0x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x01, ++0x25,0x4a,0x00,0x00,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff,0x01,0x41,0x50,0x24, ++0x3c,0x09,0x00,0x01,0x35,0x29,0x7f,0xff,0x4c,0x8a,0x20,0x00,0x4c,0x89,0x28,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x08,0x04,0x10, ++0x00,0x00,0x00,0x00,0x40,0x88,0xa0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x3c,0x08,0xbf,0xc0,0x00,0x00,0x00,0x00,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00, ++0x3c,0x0a,0xbf,0xc0,0x25,0x4a,0x01,0x20,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20, ++0x3c,0x08,0xb0,0x03,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x35,0x29,0x00,0x10, ++0xad,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x00,0x25,0x08,0x6a,0xbc, ++0x01,0x00,0x00,0x08,0x00,0x00,0x00,0x00,}; ++ ++u8 rtl8190_fwmain_array[] = { ++0x40,0x04,0x68,0x00,0x40,0x05,0x70,0x00,0x40,0x06,0x40,0x00,0x0c,0x00,0x1a,0x1e, ++0x00,0x00,0x00,0x00,0x40,0x1a,0x68,0x00,0x33,0x5b,0x00,0x3c,0x17,0x60,0x00,0x09, ++0x00,0x00,0x00,0x00,0x40,0x1b,0x60,0x00,0x00,0x00,0x00,0x00,0x03,0x5b,0xd0,0x24, ++0x40,0x1a,0x70,0x00,0x03,0x40,0x00,0x08,0x42,0x00,0x00,0x10,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0xff,0x34,0x42,0xff,0xff,0x8c,0x43,0x00,0x00, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x00,0xd0, ++0xac,0x62,0x00,0x00,0x00,0x00,0x20,0x21,0x27,0x85,0x94,0x50,0x00,0x85,0x18,0x21, ++0x24,0x84,0x00,0x01,0x28,0x82,0x00,0x0a,0x14,0x40,0xff,0xfc,0xa0,0x60,0x00,0x00, ++0x27,0x82,0x94,0x5a,0x24,0x04,0x00,0x06,0x24,0x84,0xff,0xff,0xa4,0x40,0x00,0x00, ++0x04,0x81,0xff,0xfd,0x24,0x42,0x00,0x02,0x24,0x02,0x00,0x03,0xa3,0x82,0x94,0x50, ++0x24,0x02,0x00,0x0a,0x24,0x03,0x09,0xc4,0xa3,0x82,0x94,0x52,0x24,0x02,0x00,0x04, ++0x24,0x04,0x00,0x01,0x24,0x05,0x00,0x02,0xa7,0x83,0x94,0x66,0xa3,0x82,0x94,0x58, ++0x24,0x03,0x04,0x00,0x24,0x02,0x02,0x00,0xaf,0x83,0x94,0x6c,0xa3,0x85,0x94,0x59, ++0xa7,0x82,0x94,0x5a,0xa7,0x84,0x94,0x5c,0xaf,0x84,0x94,0x68,0xa3,0x84,0x94,0x51, ++0xa3,0x80,0x94,0x53,0xa3,0x80,0x94,0x54,0xa3,0x80,0x94,0x55,0xa3,0x84,0x94,0x56, ++0xa3,0x85,0x94,0x57,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x24,0x42,0x01,0x7c,0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00, ++0x27,0x84,0x94,0x78,0x00,0x00,0x10,0x21,0x24,0x42,0x00,0x01,0x00,0x02,0x16,0x00, ++0x00,0x02,0x16,0x03,0x28,0x43,0x00,0x03,0xac,0x80,0xff,0xfc,0xa0,0x80,0x00,0x00, ++0x14,0x60,0xff,0xf9,0x24,0x84,0x00,0x0c,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x01,0xc0, ++0x3c,0x08,0xb0,0x03,0xac,0x62,0x00,0x00,0x35,0x08,0x00,0x70,0x8d,0x02,0x00,0x00, ++0x00,0xa0,0x48,0x21,0x00,0x04,0x26,0x00,0x00,0x02,0x2a,0x43,0x00,0x06,0x36,0x00, ++0x00,0x07,0x3e,0x00,0x00,0x02,0x12,0x03,0x29,0x23,0x00,0x03,0x00,0x04,0x56,0x03, ++0x00,0x06,0x36,0x03,0x00,0x07,0x3e,0x03,0x30,0x48,0x00,0x01,0x10,0x60,0x00,0x11, ++0x30,0xa5,0x00,0x07,0x24,0x02,0x00,0x02,0x00,0x49,0x10,0x23,0x00,0x45,0x10,0x07, ++0x30,0x42,0x00,0x01,0x10,0x40,0x00,0x66,0x00,0x00,0x00,0x00,0x8f,0xa2,0x00,0x10, ++0x00,0x00,0x00,0x00,0x00,0x02,0x21,0x43,0x11,0x00,0x00,0x10,0x00,0x07,0x20,0x0b, ++0x15,0x20,0x00,0x06,0x24,0x02,0x00,0x01,0x3c,0x02,0xb0,0x05,0x34,0x42,0x01,0x20, ++0xa4,0x44,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x11,0x22,0x00,0x04, ++0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05,0x08,0x00,0x00,0x94,0x34,0x42,0x01,0x24, ++0x3c,0x02,0xb0,0x05,0x08,0x00,0x00,0x94,0x34,0x42,0x01,0x22,0x15,0x20,0x00,0x54, ++0x24,0x02,0x00,0x01,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x74,0x90,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0xaf,0x83,0x94,0x74,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x70, ++0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x6b,0x00,0x08,0x11,0x60,0x00,0x18, ++0x00,0x09,0x28,0x40,0x00,0x00,0x40,0x21,0x27,0x85,0x94,0x70,0x8c,0xa3,0x00,0x00, ++0x8c,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x62,0x38,0x23,0x00,0x43,0x10,0x2a, ++0x10,0x40,0x00,0x3d,0x00,0x00,0x00,0x00,0xac,0xa7,0x00,0x00,0x25,0x02,0x00,0x01, ++0x00,0x02,0x16,0x00,0x00,0x02,0x46,0x03,0x29,0x03,0x00,0x03,0x14,0x60,0xff,0xf3, ++0x24,0xa5,0x00,0x0c,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x70,0x90,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x4b,0x10,0x23,0xa0,0x62,0x00,0x00,0x00,0x09,0x28,0x40, ++0x00,0xa9,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x94,0x78,0x00,0x0a,0x20,0x0b, ++0x00,0x43,0x18,0x21,0x10,0xc0,0x00,0x05,0x00,0x00,0x38,0x21,0x80,0x62,0x00,0x01, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x80,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03,0x00,0xa9,0x10,0x21,0x24,0x07,0x00,0x01, ++0x00,0xa9,0x10,0x21,0x00,0x02,0x30,0x80,0x27,0x82,0x94,0x78,0xa0,0x67,0x00,0x01, ++0x00,0xc2,0x38,0x21,0x80,0xe3,0x00,0x01,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x07, ++0x00,0x00,0x00,0x00,0x27,0x83,0x94,0x70,0x00,0xc3,0x18,0x21,0x8c,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x21,0xac,0x62,0x00,0x00,0x27,0x85,0x94,0x74, ++0x27,0x82,0x94,0x70,0x00,0xc5,0x28,0x21,0x00,0xc2,0x10,0x21,0x8c,0x43,0x00,0x00, ++0x8c,0xa4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x64,0x18,0x2a,0x14,0x60,0x00,0x03, ++0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,0xa0,0xe2,0x00,0x00,0xa0,0xe0,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0xb7,0xac,0xa0,0x00,0x00, ++0x11,0x22,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x7c, ++0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x83,0x94,0x8c,0x08,0x00,0x00,0xa7, ++0x3c,0x02,0xb0,0x03,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x78,0x90,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0xaf,0x83,0x94,0x80,0x08,0x00,0x00,0xa7,0x3c,0x02,0xb0,0x03, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x04,0x10, ++0x3c,0x05,0xb0,0x03,0xac,0x62,0x00,0x00,0x34,0xa5,0x00,0x70,0x8c,0xa2,0x00,0x00, ++0x90,0x84,0x00,0x08,0x3c,0x06,0xb0,0x03,0x00,0x02,0x16,0x00,0x2c,0x83,0x00,0x03, ++0x34,0xc6,0x00,0x72,0x24,0x07,0x00,0x01,0x10,0x60,0x00,0x11,0x00,0x02,0x2f,0xc2, ++0x90,0xc2,0x00,0x00,0x00,0x00,0x18,0x21,0x00,0x02,0x16,0x00,0x10,0xa7,0x00,0x09, ++0x00,0x02,0x16,0x03,0x14,0x80,0x00,0x0c,0x30,0x43,0x00,0x03,0x83,0x82,0x94,0x78, ++0x00,0x00,0x00,0x00,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0x02,0x16,0x00, ++0x00,0x02,0x1e,0x03,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x72,0xa0,0x43,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0x45,0x00,0x05,0x10,0x87,0x00,0x04, ++0x30,0x43,0x00,0x06,0x93,0x82,0x94,0x90,0x08,0x00,0x01,0x1f,0x00,0x43,0x10,0x21, ++0x83,0x82,0x94,0x84,0x00,0x00,0x00,0x00,0x00,0x02,0x10,0x40,0x08,0x00,0x01,0x1f, ++0x00,0x45,0x10,0x21,0x10,0x80,0x00,0x05,0x00,0x00,0x18,0x21,0x24,0x63,0x00,0x01, ++0x00,0x64,0x10,0x2b,0x14,0x40,0xff,0xfd,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x04,0xe4, ++0x3c,0x04,0xb0,0x02,0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00,0x34,0x84,0x00,0x08, ++0x24,0x02,0x00,0x01,0xaf,0x84,0x94,0xa0,0xa3,0x82,0x94,0xb0,0xa7,0x80,0x94,0xa4, ++0xa7,0x80,0x94,0xa6,0xaf,0x80,0x94,0xa8,0xaf,0x80,0x94,0xac,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20, ++0x24,0x42,0x05,0x24,0x3c,0x04,0xb0,0x03,0xac,0x62,0x00,0x00,0x34,0x84,0x00,0xac, ++0x80,0xa2,0x00,0x15,0x8c,0x83,0x00,0x00,0x27,0xbd,0xff,0xf0,0x00,0x43,0x10,0x21, ++0xac,0x82,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x10,0x3c,0x02,0xb0,0x03, ++0x3c,0x03,0x80,0x00,0x34,0x42,0x00,0x20,0x24,0x63,0x05,0x5c,0x27,0xbd,0xff,0xe0, ++0xac,0x43,0x00,0x00,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x18, ++0x8f,0x90,0x94,0xa0,0x0c,0x00,0x02,0x90,0x00,0x80,0x88,0x21,0x14,0x40,0x00,0x2a, ++0x3c,0x02,0x00,0x80,0x16,0x20,0x00,0x02,0x34,0x42,0x02,0x01,0x24,0x02,0x02,0x01, ++0xae,0x02,0x00,0x00,0x97,0x84,0x94,0xa4,0x97,0x82,0x94,0xa6,0x3c,0x03,0xb0,0x02, ++0x00,0x83,0x20,0x21,0x24,0x42,0x00,0x04,0xa7,0x82,0x94,0xa6,0xa4,0x82,0x00,0x00, ++0x8f,0x84,0x94,0xa8,0x8f,0x82,0x94,0xa0,0x93,0x85,0x94,0x52,0x24,0x84,0x00,0x01, ++0x24,0x42,0x00,0x04,0x24,0x03,0x8f,0xff,0x3c,0x07,0xb0,0x06,0x3c,0x06,0xb0,0x03, ++0x00,0x43,0x10,0x24,0x00,0x85,0x28,0x2a,0x34,0xe7,0x80,0x18,0xaf,0x82,0x94,0xa0, ++0xaf,0x84,0x94,0xa8,0x10,0xa0,0x00,0x08,0x34,0xc6,0x01,0x08,0x8f,0x83,0x94,0xac, ++0x8f,0x84,0x94,0x6c,0x8c,0xc2,0x00,0x00,0x00,0x64,0x18,0x21,0x00,0x43,0x10,0x2b, ++0x14,0x40,0x00,0x09,0x00,0x00,0x00,0x00,0x8c,0xe2,0x00,0x00,0x3c,0x03,0x0f,0x00, ++0x3c,0x04,0x04,0x00,0x00,0x43,0x10,0x24,0x10,0x44,0x00,0x03,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x04,0x8e,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x27,0xbd,0xff,0xd8,0x3c,0x02,0xb0,0x03, ++0x3c,0x03,0x80,0x00,0x24,0x63,0x06,0x48,0xaf,0xb0,0x00,0x10,0x34,0x42,0x00,0x20, ++0x8f,0x90,0x94,0xa0,0xac,0x43,0x00,0x00,0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18, ++0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x20,0x00,0x80,0x88,0x21,0x00,0xa0,0x90,0x21, ++0x0c,0x00,0x02,0x90,0x00,0xc0,0x98,0x21,0x24,0x07,0x8f,0xff,0x14,0x40,0x00,0x19, ++0x26,0x03,0x00,0x04,0x24,0x02,0x0e,0x03,0xae,0x02,0x00,0x00,0x00,0x67,0x80,0x24, ++0x26,0x02,0x00,0x04,0xae,0x11,0x00,0x00,0x00,0x47,0x80,0x24,0x97,0x86,0x94,0xa4, ++0x26,0x03,0x00,0x04,0xae,0x12,0x00,0x00,0x00,0x67,0x80,0x24,0xae,0x13,0x00,0x00, ++0x8f,0x84,0x94,0xa0,0x3c,0x02,0xb0,0x02,0x97,0x85,0x94,0xa6,0x00,0xc2,0x30,0x21, ++0x8f,0x82,0x94,0xa8,0x24,0x84,0x00,0x10,0x24,0xa5,0x00,0x10,0x00,0x87,0x20,0x24, ++0x24,0x42,0x00,0x01,0xa7,0x85,0x94,0xa6,0xaf,0x84,0x94,0xa0,0xaf,0x82,0x94,0xa8, ++0xa4,0xc5,0x00,0x00,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10, ++0x94,0x82,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0xe0,0x00,0x14,0x40,0x00,0x14, ++0x00,0x00,0x00,0x00,0x90,0x82,0x00,0x02,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfc, ++0x00,0x82,0x28,0x21,0x8c,0xa4,0x00,0x00,0x3c,0x02,0x00,0x70,0x8c,0xa6,0x00,0x08, ++0x00,0x82,0x10,0x21,0x2c,0x43,0x00,0x06,0x10,0x60,0x00,0x09,0x3c,0x03,0x80,0x01, ++0x00,0x02,0x10,0x80,0x24,0x63,0x08,0x94,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0xaf,0x86,0x80,0x14, ++0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18, ++0x8c,0xa4,0x00,0x00,0x0c,0x00,0x1e,0xfc,0x00,0x00,0x00,0x00,0x08,0x00,0x01,0xdc, ++0x00,0x00,0x00,0x00,0x0c,0x00,0x2b,0x59,0x00,0xc0,0x20,0x21,0x08,0x00,0x01,0xdc, ++0x00,0x00,0x00,0x00,0x87,0x83,0x88,0x06,0x93,0x82,0x80,0x18,0x00,0x00,0x00,0x00, ++0x10,0x62,0x00,0x08,0x00,0x00,0x00,0x00,0x93,0x83,0x88,0x07,0x24,0x02,0x00,0x01, ++0xa3,0x82,0x80,0x11,0xa3,0x83,0x80,0x19,0xa3,0x83,0x80,0x18,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x93,0x82,0x80,0x19,0x00,0x00,0x00,0x00,0x14,0x62,0xff,0xf6, ++0x00,0x00,0x00,0x00,0x08,0x00,0x01,0xf3,0x00,0x00,0x00,0x00,0x30,0x84,0x00,0xff, ++0x14,0x80,0x00,0x2f,0x00,0x00,0x00,0x00,0x8f,0x82,0x80,0x14,0xa3,0x85,0x8b,0xcb, ++0x10,0x40,0x00,0x2b,0x2c,0xa2,0x00,0x04,0x14,0x40,0x00,0x06,0x00,0x05,0x10,0x40, ++0x24,0xa2,0xff,0xfc,0x2c,0x42,0x00,0x08,0x10,0x40,0x00,0x09,0x24,0xa2,0xff,0xf0, ++0x00,0x05,0x10,0x40,0x27,0x84,0x8b,0xd4,0x00,0x44,0x10,0x21,0x94,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,0x03,0xe0,0x00,0x08,0xa4,0x43,0x00,0x00, ++0x2c,0x42,0x00,0x10,0x14,0x40,0x00,0x0a,0x00,0x05,0x10,0x40,0x24,0xa2,0xff,0xe0, ++0x2c,0x42,0x00,0x10,0x14,0x40,0x00,0x06,0x00,0x05,0x10,0x40,0x24,0xa2,0xff,0xd0, ++0x2c,0x42,0x00,0x10,0x10,0x40,0x00,0x09,0x24,0xa2,0xff,0xc0,0x00,0x05,0x10,0x40, ++0x27,0x84,0x8b,0xd4,0x00,0x44,0x10,0x21,0x94,0x43,0xff,0xf8,0x00,0x00,0x00,0x00, ++0x24,0x63,0x00,0x01,0x03,0xe0,0x00,0x08,0xa4,0x43,0xff,0xf8,0x2c,0x42,0x00,0x10, ++0x10,0x40,0x00,0x07,0x00,0x05,0x10,0x40,0x27,0x84,0x8b,0xd4,0x00,0x44,0x10,0x21, ++0x94,0x43,0xff,0xf8,0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,0xa4,0x43,0xff,0xf8, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8f,0x86,0x94,0xa0,0x8f,0x82,0x80,0x14, ++0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x10,0x40,0x00,0x2a,0x00,0xc0,0x38,0x21, ++0x24,0x02,0x00,0x07,0x24,0x03,0xff,0x9c,0xa3,0x82,0x8b,0xd3,0xa3,0x83,0x8b,0xd2, ++0x27,0x8a,0x8b,0xd0,0x00,0x00,0x20,0x21,0x24,0x09,0x8f,0xff,0x00,0x04,0x10,0x80, ++0x00,0x4a,0x28,0x21,0x8c,0xa2,0x00,0x00,0x24,0xe3,0x00,0x04,0x24,0x88,0x00,0x01, ++0xac,0xe2,0x00,0x00,0x10,0x80,0x00,0x02,0x00,0x69,0x38,0x24,0xac,0xa0,0x00,0x00, ++0x31,0x04,0x00,0xff,0x2c,0x82,0x00,0x27,0x14,0x40,0xff,0xf5,0x00,0x04,0x10,0x80, ++0x97,0x83,0x94,0xa6,0x97,0x85,0x94,0xa4,0x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x9c, ++0x00,0xa2,0x28,0x21,0x3c,0x04,0xb0,0x06,0xa7,0x83,0x94,0xa6,0x34,0x84,0x80,0x18, ++0xa4,0xa3,0x00,0x00,0x8c,0x85,0x00,0x00,0x24,0x02,0x8f,0xff,0x24,0xc6,0x00,0x9c, ++0x3c,0x03,0x0f,0x00,0x00,0xc2,0x30,0x24,0x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00, ++0xaf,0x86,0x94,0xa0,0x10,0xa2,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x8e, ++0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x18,0x8f,0x86,0x94,0xa0,0x27,0xbd,0xff,0xc8,0x24,0x02,0x00,0x08, ++0x24,0x03,0x00,0x20,0xaf,0xbf,0x00,0x30,0xa3,0xa2,0x00,0x13,0xa3,0xa3,0x00,0x12, ++0xa7,0xa4,0x00,0x10,0x00,0xc0,0x28,0x21,0x27,0xa9,0x00,0x10,0x00,0x00,0x38,0x21, ++0x24,0x08,0x8f,0xff,0x00,0x07,0x10,0x80,0x00,0x49,0x10,0x21,0x8c,0x44,0x00,0x00, ++0x24,0xe3,0x00,0x01,0x30,0x67,0x00,0xff,0x24,0xa2,0x00,0x04,0x2c,0xe3,0x00,0x08, ++0xac,0xa4,0x00,0x00,0x14,0x60,0xff,0xf7,0x00,0x48,0x28,0x24,0x97,0x83,0x94,0xa6, ++0x97,0x85,0x94,0xa4,0x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x20,0x00,0xa2,0x28,0x21, ++0x3c,0x04,0xb0,0x06,0xa7,0x83,0x94,0xa6,0x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00, ++0x8c,0x85,0x00,0x00,0x24,0x02,0x8f,0xff,0x24,0xc6,0x00,0x20,0x3c,0x03,0x0f,0x00, ++0x00,0xc2,0x30,0x24,0x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00,0xaf,0x86,0x94,0xa0, ++0x10,0xa2,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x8e,0x00,0x00,0x00,0x00, ++0x8f,0xbf,0x00,0x30,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38, ++0x93,0x82,0x94,0xb0,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x11,0x24,0x06,0x00,0x01, ++0x8f,0x82,0x94,0xa8,0x3c,0x05,0xb0,0x06,0x3c,0x04,0xb0,0x03,0x34,0xa5,0x80,0x18, ++0x34,0x84,0x01,0x08,0x14,0x40,0x00,0x09,0x00,0x00,0x30,0x21,0x97,0x82,0x94,0xa4, ++0x8c,0x84,0x00,0x00,0x3c,0x03,0xb0,0x02,0x00,0x43,0x10,0x21,0xaf,0x84,0x94,0xac, ++0xa7,0x80,0x94,0xa6,0xac,0x40,0x00,0x00,0xac,0x40,0x00,0x04,0x8c,0xa2,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x00,0xc0,0x10,0x21,0x8f,0x86,0x94,0xa0,0x8f,0x82,0x94,0xa8, ++0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x00,0xc0,0x40,0x21,0x14,0x40,0x00,0x0a, ++0x00,0x40,0x50,0x21,0x00,0x00,0x38,0x21,0x27,0x89,0x8b,0xa0,0x24,0xe2,0x00,0x01, ++0x00,0x07,0x18,0x80,0x30,0x47,0x00,0xff,0x00,0x69,0x18,0x21,0x2c,0xe2,0x00,0x0a, ++0x14,0x40,0xff,0xfa,0xac,0x60,0x00,0x00,0x3c,0x02,0x00,0x80,0x10,0x82,0x00,0x6f, ++0x00,0x00,0x00,0x00,0x97,0x82,0x8b,0xa6,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01, ++0xa7,0x82,0x8b,0xa6,0x90,0xa3,0x00,0x15,0x97,0x82,0x8b,0xa8,0x00,0x03,0x1e,0x00, ++0x00,0x03,0x1e,0x03,0x00,0x43,0x10,0x21,0xa7,0x82,0x8b,0xa8,0x8c,0xa4,0x00,0x20, ++0x3c,0x02,0x00,0x60,0x3c,0x03,0x00,0x20,0x00,0x82,0x20,0x24,0x10,0x83,0x00,0x54, ++0x00,0x00,0x00,0x00,0x14,0x80,0x00,0x47,0x00,0x00,0x00,0x00,0x97,0x82,0x8b,0xac, ++0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xa7,0x82,0x8b,0xac,0x84,0xa3,0x00,0x06, ++0x8f,0x82,0x8b,0xbc,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21,0xaf,0x82,0x8b,0xbc, ++0x25,0x42,0x00,0x01,0x28,0x43,0x27,0x10,0xaf,0x82,0x94,0xa8,0x10,0x60,0x00,0x09, ++0x24,0x02,0x00,0x04,0x93,0x83,0x80,0x11,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x05, ++0x24,0x02,0x00,0x04,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x18,0x24,0x03,0x00,0x28,0xa3,0x83,0x8b,0xa2,0xa3,0x82,0x8b,0xa3, ++0x90,0xa2,0x00,0x18,0x93,0x83,0x8b,0xcb,0x00,0x00,0x38,0x21,0x00,0x02,0x16,0x00, ++0x00,0x02,0x16,0x03,0xa7,0x82,0x8b,0xb6,0xa3,0x83,0x8b,0xc4,0x27,0x89,0x8b,0xa0, ++0x24,0x05,0x8f,0xff,0x00,0x07,0x10,0x80,0x00,0x49,0x10,0x21,0x8c,0x44,0x00,0x00, ++0x24,0xe3,0x00,0x01,0x30,0x67,0x00,0xff,0x25,0x02,0x00,0x04,0x2c,0xe3,0x00,0x0a, ++0xad,0x04,0x00,0x00,0x14,0x60,0xff,0xf7,0x00,0x45,0x40,0x24,0x97,0x83,0x94,0xa6, ++0x97,0x85,0x94,0xa4,0x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x28,0x00,0xa2,0x28,0x21, ++0x3c,0x04,0xb0,0x06,0xa7,0x83,0x94,0xa6,0x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00, ++0x8c,0x85,0x00,0x00,0x24,0x02,0x8f,0xff,0x24,0xc6,0x00,0x28,0x3c,0x03,0x0f,0x00, ++0x00,0xc2,0x30,0x24,0x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00,0xaf,0x86,0x94,0xa0, ++0x10,0xa2,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x8e,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x02,0x2e,0x00,0x00,0x00,0x00,0xa3,0x80,0x80,0x11,0x08,0x00,0x02,0xdd, ++0x00,0x00,0x00,0x00,0x97,0x82,0x8b,0xae,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01, ++0xa7,0x82,0x8b,0xae,0x84,0xa3,0x00,0x06,0x8f,0x82,0x8b,0xc0,0x00,0x00,0x00,0x00, ++0x00,0x43,0x10,0x21,0xaf,0x82,0x8b,0xc0,0x08,0x00,0x02,0xd5,0x25,0x42,0x00,0x01, ++0x97,0x82,0x8b,0xaa,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xa7,0x82,0x8b,0xaa, ++0x84,0xa3,0x00,0x06,0x8f,0x82,0x8b,0xb8,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21, ++0xaf,0x82,0x8b,0xb8,0x08,0x00,0x02,0xd5,0x25,0x42,0x00,0x01,0x97,0x82,0x8b,0xa4, ++0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xa7,0x82,0x8b,0xa4,0x08,0x00,0x02,0xbd, ++0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xd0,0xaf,0xbf,0x00,0x28,0x8c,0xa3,0x00,0x20, ++0x8f,0x8a,0x94,0xa0,0x3c,0x02,0x00,0x10,0x00,0x62,0x10,0x24,0x00,0xa0,0x38,0x21, ++0x01,0x40,0x48,0x21,0x10,0x40,0x00,0x3d,0x00,0x80,0x28,0x21,0x8c,0xe4,0x00,0x1c, ++0x34,0xa5,0x12,0x06,0xaf,0xa5,0x00,0x10,0x8c,0x82,0x00,0x08,0x00,0x03,0x1c,0x42, ++0x30,0x63,0x00,0x30,0x00,0x02,0x13,0x02,0x30,0x42,0x00,0x40,0x00,0x43,0x10,0x25, ++0x90,0xe6,0x00,0x10,0x90,0xe4,0x00,0x13,0x94,0xe8,0x00,0x0c,0x94,0xe3,0x00,0x1a, ++0x00,0x02,0x16,0x00,0x90,0xe7,0x00,0x12,0x00,0xa2,0x28,0x25,0x24,0x02,0x12,0x34, ++0xa7,0xa2,0x00,0x1c,0x24,0x02,0x56,0x78,0xaf,0xa5,0x00,0x10,0xa3,0xa6,0x00,0x18, ++0xa3,0xa7,0x00,0x1f,0xa7,0xa3,0x00,0x1a,0xa3,0xa4,0x00,0x19,0xa7,0xa8,0x00,0x20, ++0xa7,0xa2,0x00,0x22,0x00,0x00,0x28,0x21,0x27,0xa7,0x00,0x10,0x24,0x06,0x8f,0xff, ++0x00,0x05,0x10,0x80,0x00,0x47,0x10,0x21,0x8c,0x44,0x00,0x00,0x24,0xa3,0x00,0x01, ++0x30,0x65,0x00,0xff,0x25,0x22,0x00,0x04,0x2c,0xa3,0x00,0x05,0xad,0x24,0x00,0x00, ++0x14,0x60,0xff,0xf7,0x00,0x46,0x48,0x24,0x97,0x83,0x94,0xa6,0x97,0x85,0x94,0xa4, ++0x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x14,0x00,0xa2,0x28,0x21,0x3c,0x04,0xb0,0x06, ++0xa7,0x83,0x94,0xa6,0x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00,0x8c,0x85,0x00,0x00, ++0x24,0x02,0x8f,0xff,0x25,0x46,0x00,0x14,0x3c,0x03,0x0f,0x00,0x00,0xc2,0x50,0x24, ++0x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00,0xaf,0x8a,0x94,0xa0,0x10,0xa2,0x00,0x03, ++0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x8e,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x28, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,0x3c,0x05,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xc8,0x00,0x04,0x22,0x00,0x34,0xa5,0x00,0x20, ++0x24,0x42,0x0d,0xdc,0x3c,0x03,0xb0,0x00,0xaf,0xb5,0x00,0x24,0xaf,0xb4,0x00,0x20, ++0xaf,0xb2,0x00,0x18,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x30,0x00,0x83,0x80,0x21, ++0xaf,0xb7,0x00,0x2c,0xaf,0xb6,0x00,0x28,0xaf,0xb3,0x00,0x1c,0xaf,0xb1,0x00,0x14, ++0xac,0xa2,0x00,0x00,0x8e,0x09,0x00,0x00,0x00,0x00,0x90,0x21,0x26,0x10,0x00,0x08, ++0x00,0x09,0xa6,0x02,0x12,0x80,0x00,0x13,0x00,0x00,0xa8,0x21,0x24,0x13,0x00,0x02, ++0x3c,0x16,0x00,0xff,0x3c,0x17,0xff,0x00,0x8e,0x09,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x09,0x12,0x02,0x24,0x42,0x00,0x02,0x31,0x25,0x00,0xff,0x10,0xb3,0x00,0x76, ++0x30,0x51,0x00,0xff,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x18,0x00,0x00,0x00,0x00, ++0x02,0x51,0x10,0x21,0x30,0x52,0xff,0xff,0x02,0x54,0x18,0x2b,0x14,0x60,0xff,0xf2, ++0x02,0x11,0x80,0x21,0x12,0xa0,0x00,0x0a,0x3c,0x02,0xb0,0x06,0x34,0x42,0x80,0x18, ++0x8c,0x43,0x00,0x00,0x3c,0x04,0x0f,0x00,0x3c,0x02,0x04,0x00,0x00,0x64,0x18,0x24, ++0x10,0x62,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x8e,0x00,0x00,0x00,0x00, ++0x8f,0xbf,0x00,0x30,0x7b,0xb6,0x01,0x7c,0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0x8e,0x09,0x00,0x04, ++0x24,0x15,0x00,0x01,0x8e,0x06,0x00,0x0c,0x00,0x09,0x11,0x42,0x00,0x09,0x18,0xc2, ++0x30,0x48,0x00,0x03,0x00,0x09,0x14,0x02,0x30,0x6c,0x00,0x03,0x00,0x09,0x26,0x02, ++0x11,0x15,0x00,0x45,0x30,0x43,0x00,0x0f,0x29,0x02,0x00,0x02,0x14,0x40,0x00,0x26, ++0x00,0x00,0x00,0x00,0x11,0x13,0x00,0x0f,0x00,0x00,0x38,0x21,0x00,0x07,0x22,0x02, ++0x30,0x84,0xff,0x00,0x3c,0x03,0x00,0xff,0x00,0x07,0x2e,0x02,0x00,0x07,0x12,0x00, ++0x00,0x43,0x10,0x24,0x00,0xa4,0x28,0x25,0x00,0xa2,0x28,0x25,0x00,0x07,0x1e,0x00, ++0x00,0xa3,0x28,0x25,0x0c,0x00,0x01,0x92,0x01,0x20,0x20,0x21,0x08,0x00,0x03,0x9d, ++0x02,0x51,0x10,0x21,0x11,0x95,0x00,0x0f,0x00,0x00,0x00,0x00,0x11,0x88,0x00,0x07, ++0x00,0x00,0x00,0x00,0x00,0x04,0x10,0x80,0x27,0x83,0x94,0x50,0x00,0x43,0x10,0x21, ++0x8c,0x47,0x00,0x18,0x08,0x00,0x03,0xc4,0x00,0x07,0x22,0x02,0x00,0x04,0x10,0x40, ++0x27,0x83,0x94,0x58,0x00,0x43,0x10,0x21,0x94,0x47,0x00,0x02,0x08,0x00,0x03,0xc4, ++0x00,0x07,0x22,0x02,0x27,0x82,0x94,0x50,0x00,0x82,0x10,0x21,0x90,0x47,0x00,0x00, ++0x08,0x00,0x03,0xc4,0x00,0x07,0x22,0x02,0x15,0x00,0xff,0xdc,0x00,0x00,0x38,0x21, ++0x10,0x75,0x00,0x05,0x00,0x80,0x38,0x21,0x00,0x65,0x18,0x26,0x24,0x82,0x01,0x00, ++0x00,0x00,0x38,0x21,0x00,0x43,0x38,0x0a,0x24,0x02,0x00,0x01,0x11,0x82,0x00,0x0e, ++0x3c,0x02,0xb0,0x03,0x24,0x02,0x00,0x02,0x11,0x82,0x00,0x06,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xb0,0x03,0x00,0xe2,0x10,0x21,0x8c,0x47,0x00,0x00,0x08,0x00,0x03,0xc4, ++0x00,0x07,0x22,0x02,0x3c,0x02,0xb0,0x03,0x00,0xe2,0x10,0x21,0x94,0x43,0x00,0x00, ++0x08,0x00,0x03,0xc3,0x30,0x67,0xff,0xff,0x00,0xe2,0x10,0x21,0x90,0x43,0x00,0x00, ++0x08,0x00,0x03,0xc3,0x30,0x67,0x00,0xff,0x30,0x62,0x00,0x03,0x00,0x02,0x12,0x00, ++0x11,0x95,0x00,0x07,0x00,0x44,0x38,0x21,0x11,0x93,0x00,0x03,0x00,0x00,0x00,0x00, ++0x08,0x00,0x03,0xf5,0x3c,0x02,0xb0,0x0a,0x08,0x00,0x03,0xfa,0x3c,0x02,0xb0,0x0a, ++0x08,0x00,0x03,0xfe,0x3c,0x02,0xb0,0x0a,0x8e,0x09,0x00,0x04,0x8e,0x02,0x00,0x08, ++0x8e,0x03,0x00,0x0c,0x00,0x09,0x41,0x42,0x00,0x02,0x22,0x02,0x00,0x03,0x3a,0x02, ++0x30,0x84,0xff,0x00,0x30,0xe7,0xff,0x00,0x00,0x02,0x5e,0x02,0x00,0x02,0x32,0x00, ++0x00,0x03,0x56,0x02,0x00,0x03,0x2a,0x00,0x01,0x64,0x58,0x25,0x00,0xd6,0x30,0x24, ++0x01,0x47,0x50,0x25,0x00,0x02,0x16,0x00,0x00,0xb6,0x28,0x24,0x00,0x03,0x1e,0x00, ++0x01,0x66,0x58,0x25,0x01,0x45,0x50,0x25,0x00,0x57,0x10,0x24,0x00,0x77,0x18,0x24, ++0x01,0x62,0x38,0x25,0x01,0x43,0x30,0x25,0x00,0x09,0x10,0xc2,0x00,0x09,0x1c,0x02, ++0x31,0x08,0x00,0x03,0x30,0x4c,0x00,0x03,0x30,0x63,0x00,0x0f,0x00,0x09,0x26,0x02, ++0x00,0xe0,0x58,0x21,0x15,0x00,0x00,0x28,0x00,0xc0,0x50,0x21,0x24,0x02,0x00,0x01, ++0x10,0x62,0x00,0x06,0x00,0x80,0x28,0x21,0x24,0x02,0x00,0x03,0x14,0x62,0xff,0x69, ++0x02,0x51,0x10,0x21,0x24,0x85,0x01,0x00,0x24,0x02,0x00,0x01,0x11,0x82,0x00,0x15, ++0x24,0x02,0x00,0x02,0x11,0x82,0x00,0x0a,0x3c,0x03,0xb0,0x03,0x00,0xa3,0x18,0x21, ++0x8c,0x62,0x00,0x00,0x00,0x0a,0x20,0x27,0x01,0x6a,0x28,0x24,0x00,0x44,0x10,0x24, ++0x00,0x45,0x10,0x25,0xac,0x62,0x00,0x00,0x08,0x00,0x03,0x9d,0x02,0x51,0x10,0x21, ++0x00,0xa3,0x18,0x21,0x94,0x62,0x00,0x00,0x00,0x0a,0x20,0x27,0x01,0x6a,0x28,0x24, ++0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25,0xa4,0x62,0x00,0x00,0x08,0x00,0x03,0x9d, ++0x02,0x51,0x10,0x21,0x3c,0x03,0xb0,0x03,0x00,0xa3,0x18,0x21,0x90,0x62,0x00,0x00, ++0x00,0x0a,0x20,0x27,0x01,0x6a,0x28,0x24,0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25, ++0x08,0x00,0x03,0x9c,0xa0,0x62,0x00,0x00,0x24,0x02,0x00,0x01,0x11,0x02,0x00,0x21, ++0x00,0x00,0x00,0x00,0x15,0x13,0xff,0x42,0x00,0x00,0x00,0x00,0x11,0x82,0x00,0x17, ++0x00,0x00,0x00,0x00,0x11,0x88,0x00,0x0b,0x00,0x00,0x00,0x00,0x27,0x83,0x94,0x50, ++0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x18,0x00,0x06,0x18,0x27, ++0x00,0xe6,0x28,0x24,0x00,0x43,0x10,0x24,0x00,0x45,0x10,0x25,0x08,0x00,0x03,0x9c, ++0xac,0x82,0x00,0x18,0x27,0x83,0x94,0x58,0x00,0x04,0x20,0x40,0x00,0x83,0x20,0x21, ++0x94,0x82,0x00,0x02,0x00,0x06,0x18,0x27,0x00,0xe6,0x28,0x24,0x00,0x43,0x10,0x24, ++0x00,0x45,0x10,0x25,0x08,0x00,0x03,0x9c,0xa4,0x82,0x00,0x02,0x27,0x83,0x94,0x50, ++0x00,0x83,0x18,0x21,0x90,0x62,0x00,0x00,0x00,0x06,0x20,0x27,0x08,0x00,0x04,0x52, ++0x00,0xe6,0x28,0x24,0x30,0x62,0x00,0x07,0x00,0x02,0x12,0x00,0x11,0x88,0x00,0x0f, ++0x00,0x44,0x10,0x21,0x11,0x93,0x00,0x07,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x0a, ++0x00,0x43,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x06,0x20,0x27,0x08,0x00,0x04,0x3f, ++0x00,0xe6,0x28,0x24,0x3c,0x03,0xb0,0x0a,0x00,0x43,0x18,0x21,0x94,0x62,0x00,0x00, ++0x00,0x06,0x20,0x27,0x08,0x00,0x04,0x48,0x00,0xe6,0x28,0x24,0x3c,0x03,0xb0,0x0a, ++0x08,0x00,0x04,0x75,0x00,0x43,0x18,0x21,0x97,0x85,0x94,0xa4,0x3c,0x07,0xb0,0x02, ++0x3c,0x04,0xb0,0x03,0x3c,0x02,0x80,0x00,0x00,0xa7,0x28,0x21,0x34,0x84,0x00,0x20, ++0x24,0x42,0x12,0x38,0x24,0x03,0xff,0x80,0xac,0x82,0x00,0x00,0xa0,0xa3,0x00,0x07, ++0x97,0x82,0x94,0xa6,0x97,0x85,0x94,0xa4,0x3c,0x06,0xb0,0x06,0x30,0x42,0xff,0xf8, ++0x24,0x42,0x00,0x10,0x00,0xa2,0x10,0x21,0x30,0x42,0x0f,0xff,0x24,0x44,0x00,0x08, ++0x30,0x84,0x0f,0xff,0x00,0x05,0x28,0xc2,0x3c,0x03,0x00,0x40,0x00,0xa3,0x28,0x25, ++0x00,0x87,0x20,0x21,0x34,0xc6,0x80,0x18,0xac,0xc5,0x00,0x00,0xaf,0x84,0x94,0xa0, ++0xa7,0x82,0x94,0xa4,0xa7,0x80,0x94,0xa6,0xaf,0x80,0x94,0xa8,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x30,0xa5,0x00,0xff,0x30,0x84,0x00,0xff,0x24,0x02,0x00,0x01, ++0x00,0xe0,0x48,0x21,0x30,0xc6,0x00,0xff,0x8f,0xa7,0x00,0x10,0x10,0x82,0x00,0x07, ++0x00,0xa0,0x40,0x21,0x24,0x02,0x00,0x03,0x10,0x82,0x00,0x03,0x00,0x00,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x24,0xa8,0x01,0x00,0x3c,0x03,0xb0,0x03, ++0x24,0x02,0x00,0x01,0x00,0x07,0x20,0x27,0x01,0x27,0x28,0x24,0x10,0xc2,0x00,0x14, ++0x01,0x03,0x18,0x21,0x24,0x02,0x00,0x02,0x10,0xc2,0x00,0x09,0x00,0x07,0x50,0x27, ++0x3c,0x03,0xb0,0x03,0x01,0x03,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x4a,0x10,0x24,0x00,0x45,0x10,0x25,0x08,0x00,0x04,0xd9,0xac,0x62,0x00,0x00, ++0x3c,0x03,0xb0,0x03,0x01,0x03,0x18,0x21,0x94,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x4a,0x10,0x24,0x00,0x45,0x10,0x25,0x03,0xe0,0x00,0x08,0xa4,0x62,0x00,0x00, ++0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25, ++0xa0,0x62,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0x84,0x00,0x07, ++0x00,0x04,0x22,0x00,0x30,0xa5,0x00,0xff,0x00,0x85,0x28,0x21,0x3c,0x02,0xb0,0x0a, ++0x00,0xa2,0x40,0x21,0x30,0xc6,0x00,0xff,0x24,0x02,0x00,0x01,0x8f,0xa4,0x00,0x10, ++0x10,0xc2,0x00,0x14,0x24,0x02,0x00,0x02,0x00,0x04,0x50,0x27,0x10,0xc2,0x00,0x09, ++0x00,0xe4,0x48,0x24,0x3c,0x03,0xb0,0x0a,0x00,0xa3,0x18,0x21,0x8c,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,0x00,0x49,0x10,0x25,0x03,0xe0,0x00,0x08, ++0xac,0x62,0x00,0x00,0x3c,0x03,0xb0,0x0a,0x00,0xa3,0x18,0x21,0x94,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,0x00,0x49,0x10,0x25,0x03,0xe0,0x00,0x08, ++0xa4,0x62,0x00,0x00,0x91,0x02,0x00,0x00,0x00,0x04,0x18,0x27,0x00,0xe4,0x20,0x24, ++0x00,0x43,0x10,0x24,0x00,0x44,0x10,0x25,0x03,0xe0,0x00,0x08,0xa1,0x02,0x00,0x00, ++0x30,0xa9,0x00,0xff,0x27,0x83,0x94,0x50,0x30,0x85,0x00,0xff,0x24,0x02,0x00,0x01, ++0x00,0x07,0x50,0x27,0x00,0xc7,0x40,0x24,0x11,0x22,0x00,0x17,0x00,0xa3,0x18,0x21, ++0x00,0x05,0x20,0x40,0x27,0x82,0x94,0x50,0x00,0x05,0x28,0x80,0x27,0x83,0x94,0x58, ++0x00,0x83,0x50,0x21,0x00,0xa2,0x20,0x21,0x24,0x02,0x00,0x02,0x00,0x07,0x40,0x27, ++0x11,0x22,0x00,0x07,0x00,0xc7,0x28,0x24,0x8c,0x82,0x00,0x18,0x00,0x00,0x00,0x00, ++0x00,0x48,0x10,0x24,0x00,0x45,0x10,0x25,0x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x18, ++0x95,0x42,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x48,0x10,0x24,0x00,0x45,0x10,0x25, ++0x03,0xe0,0x00,0x08,0xa5,0x42,0x00,0x02,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x4a,0x10,0x24,0x00,0x48,0x10,0x25,0x03,0xe0,0x00,0x08,0xa0,0x62,0x00,0x00, ++0x00,0x04,0x32,0x02,0x30,0xc6,0xff,0x00,0x00,0x04,0x16,0x02,0x00,0x04,0x1a,0x00, ++0x3c,0x05,0x00,0xff,0x00,0x65,0x18,0x24,0x00,0x46,0x10,0x25,0x00,0x43,0x10,0x25, ++0x00,0x04,0x26,0x00,0x03,0xe0,0x00,0x08,0x00,0x44,0x10,0x25,0x3c,0x02,0xb0,0x02, ++0x34,0x42,0x00,0x08,0x3c,0x03,0xb0,0x02,0xaf,0x82,0x8c,0x78,0xaf,0x83,0x8c,0x7c, ++0xa7,0x80,0x8c,0x80,0xa7,0x80,0x8c,0x82,0xaf,0x80,0x8c,0x84,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xd8,0xaf,0xbf,0x00,0x20,0x94,0x82,0x00,0x04, ++0x3c,0x05,0xff,0x8f,0x00,0x80,0x18,0x21,0x30,0x42,0xe0,0x00,0x14,0x40,0x00,0x0a, ++0x34,0xa5,0xff,0xff,0x90,0x84,0x00,0x02,0x00,0x00,0x00,0x00,0x30,0x84,0x00,0xfc, ++0x00,0x64,0x20,0x21,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa2,0x10,0x2b, ++0x10,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x20,0x00,0x00,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x0c,0x00,0x07,0xc9,0x00,0x00,0x00,0x00, ++0x08,0x00,0x05,0x4a,0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xd8,0xaf,0xb2,0x00,0x18, ++0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c, ++0x8f,0x90,0x94,0xa0,0x0c,0x00,0x30,0x54,0x00,0x80,0x90,0x21,0x00,0x40,0x88,0x21, ++0x93,0x82,0x82,0x28,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x1b,0x24,0x02,0x00,0x01, ++0xa3,0x82,0x82,0x28,0x24,0x03,0x00,0x05,0x24,0x02,0x00,0x04,0xa3,0x83,0x8c,0x73, ++0xa3,0x82,0x8c,0x72,0xa7,0x80,0x82,0x2a,0x00,0x00,0x28,0x21,0x27,0x86,0x8c,0x70, ++0x00,0x05,0x10,0x80,0x00,0x46,0x10,0x21,0x8c,0x44,0x00,0x00,0x24,0xa3,0x00,0x01, ++0x30,0x65,0xff,0xff,0xae,0x04,0x00,0x00,0x10,0xa0,0xff,0xfa,0x00,0x05,0x10,0x80, ++0x8f,0x83,0x94,0xa0,0x97,0x82,0x94,0xa6,0x24,0x05,0x8f,0xff,0x24,0x63,0x00,0x04, ++0x00,0x65,0x18,0x24,0x26,0x04,0x00,0x04,0x24,0x42,0x00,0x04,0xaf,0x83,0x94,0xa0, ++0xa7,0x82,0x94,0xa6,0x00,0x85,0x80,0x24,0x97,0x84,0x82,0x2a,0x27,0x93,0x80,0x34, ++0x02,0x40,0x28,0x21,0x00,0x93,0x20,0x21,0x0c,0x00,0x30,0xd8,0x02,0x20,0x30,0x21, ++0x97,0x87,0x82,0x2a,0x24,0x02,0x00,0x52,0x00,0xf1,0x18,0x21,0xa7,0x83,0x82,0x2a, ++0x82,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x82,0x00,0x06,0x00,0x60,0x38,0x21, ++0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x28,0x82,0x43,0x00,0x01,0x24,0x02,0x00,0x54,0x14,0x62,0xff,0xf8, ++0x24,0x02,0x00,0x4c,0x82,0x43,0x00,0x02,0x00,0x00,0x00,0x00,0x14,0x62,0xff,0xf4, ++0x00,0x00,0x00,0x00,0x30,0xe6,0xff,0xff,0x10,0xc0,0x00,0x0c,0x00,0x00,0x28,0x21, ++0x02,0x60,0x48,0x21,0x24,0x08,0x8f,0xff,0x00,0xa9,0x10,0x21,0x8c,0x44,0x00,0x00, ++0x24,0xa3,0x00,0x04,0x30,0x65,0xff,0xff,0x26,0x02,0x00,0x04,0x00,0xa6,0x18,0x2b, ++0xae,0x04,0x00,0x00,0x14,0x60,0xff,0xf8,0x00,0x48,0x80,0x24,0x97,0x83,0x94,0xa6, ++0x97,0x85,0x94,0xa4,0x3c,0x02,0xb0,0x02,0x00,0x67,0x18,0x21,0x00,0xa2,0x28,0x21, ++0x3c,0x04,0xb0,0x06,0xa7,0x83,0x94,0xa6,0x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00, ++0x8f,0x82,0x94,0xa0,0x8c,0x86,0x00,0x00,0x30,0xe5,0xff,0xff,0x24,0x03,0x8f,0xff, ++0x00,0x45,0x10,0x21,0x3c,0x04,0x0f,0x00,0x00,0x43,0x10,0x24,0x00,0xc4,0x30,0x24, ++0x3c,0x03,0x04,0x00,0xaf,0x82,0x94,0xa0,0x10,0xc3,0xff,0xd1,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x04,0x8e,0x00,0x00,0x00,0x00,0xa3,0x80,0x82,0x28,0x08,0x00,0x05,0x88, ++0x00,0x00,0x00,0x00,0x8f,0x82,0x8c,0x7c,0x97,0x83,0x8c,0x80,0x8f,0x87,0x8c,0x78, ++0x3c,0x06,0xff,0xff,0xac,0x43,0x00,0x00,0x8f,0x82,0x8c,0x7c,0x3c,0x03,0x80,0x00, ++0x24,0xe5,0x00,0x08,0xac,0x43,0x00,0x04,0x8f,0x82,0x8c,0x7c,0x34,0xc6,0x1f,0xff, ++0x3c,0x03,0x00,0x40,0x30,0x42,0x0f,0xff,0x3c,0x04,0xb0,0x06,0x00,0x02,0x10,0xc2, ++0x00,0x43,0x10,0x25,0x00,0xa6,0x28,0x24,0x34,0x84,0x80,0x18,0x27,0xbd,0xff,0xf8, ++0xac,0x82,0x00,0x00,0xaf,0x85,0x8c,0x78,0xaf,0x87,0x8c,0x7c,0xa7,0x80,0x8c,0x80, ++0xa7,0x80,0x8c,0x82,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x08,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe0, ++0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x8f,0x91,0x8c,0x78, ++0x00,0x80,0x80,0x21,0xaf,0xbf,0x00,0x1c,0x0c,0x00,0x06,0x78,0x00,0xa0,0x90,0x21, ++0x97,0x82,0x8c,0x80,0x36,0x10,0x12,0x00,0x26,0x2a,0x00,0x04,0x24,0x4c,0x00,0x14, ++0x2c,0x42,0x04,0x01,0x14,0x40,0x00,0x0a,0x24,0x09,0x8f,0xff,0x8f,0x82,0x80,0x20, ++0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xaf,0x82,0x80,0x20,0x8f,0xbf,0x00,0x1c, ++0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20, ++0x8e,0x44,0x00,0x1c,0x86,0x47,0x00,0x06,0x97,0x86,0x8c,0x82,0x8c,0x82,0x00,0x08, ++0x00,0x07,0x3c,0x00,0x8f,0x85,0x8c,0x78,0x00,0x02,0x11,0x02,0x30,0x42,0x40,0x00, ++0x02,0x02,0x80,0x25,0xae,0x30,0x00,0x00,0x8c,0x82,0x00,0x04,0x82,0x43,0x00,0x15, ++0x01,0x49,0x88,0x24,0x00,0x02,0x14,0xc2,0x00,0x03,0x1a,0x00,0x00,0x02,0x14,0x00, ++0x00,0x62,0x80,0x25,0xae,0x30,0x00,0x00,0x92,0x43,0x00,0x13,0x92,0x44,0x00,0x10, ++0x96,0x50,0x00,0x1a,0x00,0x03,0x1c,0x00,0x00,0x04,0x26,0x00,0x02,0x03,0x80,0x25, ++0x26,0x22,0x00,0x04,0x00,0x49,0x88,0x24,0x02,0x04,0x80,0x25,0xae,0x30,0x00,0x00, ++0x92,0x42,0x00,0x0f,0x92,0x43,0x00,0x11,0x26,0x24,0x00,0x04,0x00,0x02,0x12,0x00, ++0x00,0x89,0x88,0x24,0x00,0x62,0x80,0x25,0x02,0x07,0x80,0x25,0x26,0x22,0x00,0x04, ++0xae,0x30,0x00,0x00,0x00,0x49,0x88,0x24,0xae,0x20,0x00,0x00,0x8f,0x82,0x80,0x1c, ++0x24,0xc6,0x00,0x01,0x24,0xa5,0x00,0x14,0x30,0xc8,0xff,0xff,0x3c,0x0b,0xb0,0x03, ++0x00,0xa9,0x28,0x24,0x24,0x42,0x00,0x01,0x2d,0x08,0x00,0x0a,0xaf,0x85,0x8c,0x78, ++0xa7,0x8c,0x8c,0x80,0xaf,0x82,0x80,0x1c,0xa7,0x86,0x8c,0x82,0x11,0x00,0x00,0x07, ++0x35,0x6b,0x01,0x08,0x8f,0x82,0x8c,0x84,0x8d,0x63,0x00,0x00,0x24,0x42,0x04,0x00, ++0x00,0x62,0x18,0x2b,0x14,0x60,0xff,0xc1,0x00,0x00,0x00,0x00,0x0c,0x00,0x05,0xbd, ++0x00,0x00,0x00,0x00,0x08,0x00,0x05,0xf3,0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe8, ++0xaf,0xbf,0x00,0x10,0x0c,0x00,0x06,0x78,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x10, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x27,0xbd,0xff,0xe0, ++0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x1c, ++0x8f,0x90,0x8c,0x78,0x0c,0x00,0x06,0x78,0x00,0x80,0x90,0x21,0x97,0x82,0x8c,0x80, ++0x24,0x11,0x8f,0xff,0x2c,0x42,0x04,0x01,0x14,0x40,0x00,0x06,0x26,0x03,0x00,0x04, ++0x8f,0xbf,0x00,0x1c,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x20,0x24,0x02,0x0e,0x03,0xae,0x02,0x00,0x00,0x00,0x71,0x80,0x24, ++0xae,0x00,0x00,0x00,0x8e,0x44,0x00,0x08,0x26,0x02,0x00,0x04,0x0c,0x00,0x06,0x86, ++0x00,0x51,0x80,0x24,0x97,0x86,0x8c,0x82,0x8f,0x83,0x8c,0x78,0xae,0x02,0x00,0x00, ++0x97,0x82,0x8c,0x80,0x24,0xc6,0x00,0x01,0x8e,0x47,0x00,0x0c,0x24,0x63,0x00,0x10, ++0x30,0xc5,0xff,0xff,0x26,0x04,0x00,0x04,0x3c,0x08,0xb0,0x03,0x00,0x71,0x18,0x24, ++0x00,0x91,0x80,0x24,0x24,0x42,0x00,0x10,0x2c,0xa5,0x00,0x0a,0x35,0x08,0x01,0x08, ++0xae,0x07,0x00,0x00,0xaf,0x83,0x8c,0x78,0xa7,0x82,0x8c,0x80,0xa7,0x86,0x8c,0x82, ++0x10,0xa0,0x00,0x07,0x00,0x00,0x00,0x00,0x8f,0x82,0x8c,0x84,0x8d,0x03,0x00,0x00, ++0x24,0x42,0x04,0x00,0x00,0x62,0x18,0x2b,0x14,0x60,0xff,0xd9,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x05,0xbd,0x00,0x00,0x00,0x00,0x08,0x00,0x06,0x4c,0x00,0x00,0x00,0x00, ++0x97,0x82,0x8c,0x82,0x3c,0x03,0xb0,0x03,0x14,0x40,0x00,0x09,0x34,0x63,0x01,0x08, ++0x8c,0x62,0x00,0x00,0x8f,0x83,0x8c,0x7c,0xa7,0x80,0x8c,0x80,0xaf,0x82,0x8c,0x84, ++0xac,0x60,0x00,0x00,0x8f,0x82,0x8c,0x7c,0x00,0x00,0x00,0x00,0xac,0x40,0x00,0x04, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x04,0x32,0x02,0x30,0xc6,0xff,0x00, ++0x00,0x04,0x16,0x02,0x00,0x04,0x1a,0x00,0x3c,0x05,0x00,0xff,0x00,0x65,0x18,0x24, ++0x00,0x46,0x10,0x25,0x00,0x43,0x10,0x25,0x00,0x04,0x26,0x00,0x03,0xe0,0x00,0x08, ++0x00,0x44,0x10,0x25,0x80,0x82,0x00,0x00,0x90,0x83,0x00,0x00,0x10,0x40,0x00,0x0c, ++0x00,0x80,0x28,0x21,0x24,0x62,0xff,0x9f,0x30,0x42,0x00,0xff,0x2c,0x42,0x00,0x1a, ++0x10,0x40,0x00,0x02,0x24,0x63,0xff,0xe0,0xa0,0xa3,0x00,0x00,0x24,0xa5,0x00,0x01, ++0x90,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xf6,0x00,0x40,0x18,0x21, ++0x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x80,0x82,0x00,0x00,0x90,0x83,0x00,0x00, ++0x10,0x40,0x00,0x0c,0x00,0x80,0x28,0x21,0x24,0x62,0xff,0xbf,0x30,0x42,0x00,0xff, ++0x2c,0x42,0x00,0x1a,0x10,0x40,0x00,0x02,0x24,0x63,0x00,0x20,0xa0,0xa3,0x00,0x00, ++0x24,0xa5,0x00,0x01,0x90,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xf6, ++0x00,0x40,0x18,0x21,0x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x27,0xbd,0xff,0xe8, ++0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0x24,0x10,0xff,0xff,0x0c,0x00,0x2d,0x94, ++0x00,0x00,0x00,0x00,0x10,0x50,0xff,0xfd,0x00,0x02,0x16,0x00,0x00,0x02,0x16,0x03, ++0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18, ++0x27,0xbd,0xff,0xc8,0xaf,0xb3,0x00,0x1c,0x00,0x00,0x98,0x21,0xaf,0xb1,0x00,0x14, ++0x02,0x65,0x88,0x2b,0xaf,0xb6,0x00,0x28,0xaf,0xb5,0x00,0x24,0xaf,0xb0,0x00,0x10, ++0xaf,0xbf,0x00,0x34,0xaf,0xbe,0x00,0x30,0xaf,0xb7,0x00,0x2c,0xaf,0xb4,0x00,0x20, ++0xaf,0xb2,0x00,0x18,0x00,0xa0,0xb0,0x21,0xaf,0xa4,0x00,0x38,0x00,0xc0,0xa8,0x21, ++0x12,0x20,0x00,0x17,0x00,0x80,0x80,0x21,0x24,0x17,0xff,0xff,0x24,0x1e,0x00,0x0a, ++0x0c,0x00,0x2d,0x94,0x00,0x00,0x00,0x00,0x10,0x57,0x00,0x0f,0x00,0x02,0x16,0x00, ++0x00,0x02,0x26,0x03,0x10,0x9e,0x00,0x0e,0x24,0x02,0x00,0x0d,0x10,0x82,0x00,0x34, ++0x24,0x02,0x00,0x08,0x10,0x82,0x00,0x25,0x24,0x02,0x00,0x09,0x10,0x82,0x00,0x13, ++0x00,0x00,0x90,0x21,0xa2,0x04,0x00,0x00,0x26,0x73,0x00,0x01,0x16,0xa0,0x00,0x0b, ++0x26,0x10,0x00,0x01,0x02,0x76,0x88,0x2b,0x16,0x20,0xff,0xed,0x00,0x00,0x00,0x00, ++0x7b,0xbe,0x01,0xbc,0x7b,0xb6,0x01,0x7c,0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0x0c,0x00,0x2d,0x87, ++0x02,0x76,0x88,0x2b,0x08,0x00,0x06,0xe6,0x00,0x00,0x00,0x00,0x24,0x14,0x00,0x20, ++0xa2,0x14,0x00,0x00,0x26,0x52,0x00,0x01,0x24,0x04,0x00,0x20,0x26,0x73,0x00,0x01, ++0x16,0xa0,0x00,0x06,0x26,0x10,0x00,0x01,0x2a,0x42,0x00,0x08,0x10,0x40,0xff,0xea, ++0x02,0x76,0x88,0x2b,0x08,0x00,0x06,0xf5,0xa2,0x14,0x00,0x00,0x0c,0x00,0x2d,0x87, ++0x00,0x00,0x00,0x00,0x08,0x00,0x06,0xfb,0x2a,0x42,0x00,0x08,0x8f,0xa2,0x00,0x38, ++0x00,0x00,0x00,0x00,0x12,0x02,0xff,0xe0,0x00,0x00,0x00,0x00,0x26,0x10,0xff,0xff, ++0x12,0xa0,0xff,0xdc,0x26,0x73,0xff,0xff,0x0c,0x00,0x2d,0x87,0x24,0x04,0x00,0x08, ++0x0c,0x00,0x2d,0x87,0x24,0x04,0x00,0x20,0x08,0x00,0x06,0xef,0x24,0x04,0x00,0x08, ++0x08,0x00,0x06,0xe8,0xa2,0x00,0x00,0x00,0x90,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x02,0x1e,0x00,0x10,0x60,0x00,0x16,0x00,0x00,0x30,0x21,0x24,0x07,0x00,0x20, ++0x00,0x03,0x1e,0x03,0x10,0x67,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x15, ++0x00,0x00,0x00,0x00,0x10,0x67,0x00,0x0b,0x24,0xc6,0x00,0x01,0x10,0x60,0x00,0x0a, ++0x00,0x02,0x1e,0x00,0x24,0x05,0x00,0x20,0x24,0x84,0x00,0x01,0x80,0x83,0x00,0x00, ++0x90,0x82,0x00,0x00,0x10,0x65,0x00,0x03,0x00,0x00,0x00,0x00,0x14,0x60,0xff,0xfa, ++0x00,0x00,0x00,0x00,0x00,0x02,0x1e,0x00,0x14,0x60,0xff,0xed,0x00,0x00,0x00,0x00, ++0x28,0xc3,0x00,0x08,0x24,0x02,0x00,0x07,0x00,0x43,0x30,0x0a,0x03,0xe0,0x00,0x08, ++0x00,0xc0,0x10,0x21,0x24,0x84,0x00,0x01,0x90,0x82,0x00,0x00,0x08,0x00,0x07,0x2a, ++0x00,0x02,0x1e,0x00,0x27,0xbd,0xff,0xe0,0xaf,0xb1,0x00,0x14,0x27,0x91,0x8c,0x88, ++0xaf,0xb0,0x00,0x10,0x24,0x06,0x00,0x20,0x00,0x80,0x80,0x21,0x00,0x00,0x28,0x21, ++0xaf,0xbf,0x00,0x18,0x0c,0x00,0x30,0xce,0x02,0x20,0x20,0x21,0x82,0x02,0x00,0x00, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x1f,0x00,0x00,0x30,0x21,0x02,0x20,0x20,0x21, ++0x24,0x09,0x00,0x20,0x24,0x08,0x00,0x20,0x24,0x07,0x00,0x08,0xac,0x90,0x00,0x00, ++0x82,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x49,0x00,0x0a,0x00,0x00,0x00,0x00, ++0x10,0x40,0x00,0x08,0x24,0x03,0x00,0x20,0x26,0x10,0x00,0x01,0x82,0x02,0x00,0x00, ++0x00,0x00,0x00,0x00,0x10,0x43,0x00,0x03,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xfa, ++0x00,0x00,0x00,0x00,0xa2,0x00,0x00,0x00,0x26,0x10,0x00,0x01,0x82,0x02,0x00,0x00, ++0x92,0x03,0x00,0x00,0x10,0x48,0x00,0x0c,0x24,0x05,0x00,0x20,0x24,0xc6,0x00,0x01, ++0x10,0xc7,0x00,0x04,0x24,0x84,0x00,0x04,0x00,0x03,0x16,0x00,0x14,0x40,0xff,0xe7, ++0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x27,0x82,0x8c,0x88, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x26,0x10,0x00,0x01,0x82,0x02,0x00,0x00, ++0x92,0x03,0x00,0x00,0x10,0x45,0xff,0xfc,0x00,0x00,0x00,0x00,0x08,0x00,0x07,0x5c, ++0x24,0xc6,0x00,0x01,0x00,0x80,0x30,0x21,0x90,0x84,0x00,0x00,0x00,0x00,0x38,0x21, ++0x10,0x80,0x00,0x19,0x24,0xc6,0x00,0x01,0x24,0x82,0xff,0xd0,0x30,0x42,0x00,0xff, ++0x2c,0x43,0x00,0x0a,0x14,0x60,0x00,0x0c,0x00,0x07,0x19,0x00,0x24,0x83,0xff,0x9f, ++0x24,0x82,0xff,0xa9,0x24,0x88,0xff,0xc9,0x2c,0x63,0x00,0x06,0x24,0x84,0xff,0xbf, ++0x2c,0x84,0x00,0x06,0x14,0x60,0x00,0x03,0x30,0x42,0x00,0xff,0x10,0x80,0x00,0x0e, ++0x31,0x02,0x00,0xff,0x00,0x07,0x19,0x00,0x00,0x62,0x18,0x21,0x00,0x67,0x10,0x2b, ++0x14,0x40,0x00,0x07,0x00,0x00,0x20,0x21,0x90,0xc4,0x00,0x00,0x00,0x60,0x38,0x21, ++0x14,0x80,0xff,0xe9,0x24,0xc6,0x00,0x01,0xac,0xa7,0x00,0x00,0x24,0x04,0x00,0x01, ++0x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x08,0x00,0x07,0x8c,0x00,0x00,0x20,0x21, ++0x00,0x00,0x20,0x21,0x27,0x85,0x94,0xc0,0x24,0x82,0x00,0x01,0x00,0x04,0x18,0x80, ++0x30,0x44,0x00,0xff,0x00,0x65,0x18,0x21,0x2c,0x82,0x00,0x0b,0x14,0x40,0xff,0xfa, ++0xac,0x60,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0xaf,0x84,0x8d,0x08, ++0xaf,0x85,0x8d,0x0c,0xaf,0x86,0x8d,0x10,0xaf,0x87,0x8d,0x14,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x8f,0x82,0x84,0x98,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10, ++0x2c,0x43,0x00,0x64,0x24,0x42,0x00,0x01,0x27,0x84,0x8c,0xa8,0xaf,0x82,0x84,0x98, ++0x10,0x60,0x00,0x05,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0xaf,0x80,0x84,0x98,0x0c,0x00,0x07,0xf6, ++0x00,0x00,0x00,0x00,0x00,0x40,0x18,0x21,0x28,0x44,0x00,0x08,0x24,0x02,0x00,0x07, ++0x10,0x62,0x00,0x08,0x00,0x00,0x00,0x00,0x14,0x80,0xff,0xf3,0x24,0x02,0x00,0x08, ++0x27,0x84,0x8c,0xa8,0x14,0x62,0xff,0xf0,0x00,0x00,0x00,0x00,0x0c,0x00,0x1a,0x7e, ++0x00,0x00,0x00,0x00,0x27,0x84,0x8c,0xa8,0x0c,0x00,0x08,0x54,0x00,0x00,0x00,0x00, ++0x8f,0x83,0x84,0x9c,0x3c,0x04,0x80,0x01,0x00,0x60,0x28,0x21,0x24,0x63,0x00,0x01, ++0xaf,0x83,0x84,0x9c,0x0c,0x00,0x1a,0x6b,0x24,0x84,0x04,0x90,0x08,0x00,0x07,0xaa, ++0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xc0,0xaf,0xbf,0x00,0x38,0x8c,0x85,0x00,0x0c, ++0x8c,0x88,0x00,0x08,0x18,0xa0,0x00,0x0e,0x00,0x00,0x30,0x21,0x24,0x87,0x00,0x08, ++0x27,0xa9,0x00,0x10,0x00,0x06,0x10,0x80,0x00,0x06,0x19,0x00,0x00,0x49,0x10,0x21, ++0x14,0xc0,0x00,0x1f,0x00,0x83,0x18,0x21,0xaf,0xa7,0x00,0x10,0x24,0xc2,0x00,0x01, ++0x30,0x46,0x00,0xff,0x00,0xc5,0x18,0x2a,0x14,0x60,0xff,0xf7,0x00,0x06,0x10,0x80, ++0x29,0x02,0x00,0x0a,0x14,0x40,0x00,0x05,0x00,0x08,0x18,0x40,0x8f,0xbf,0x00,0x38, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,0x00,0x68,0x18,0x21, ++0x27,0x82,0x83,0x94,0x00,0x03,0x18,0xc0,0x00,0x62,0x18,0x21,0x8c,0x62,0x00,0x10, ++0x01,0x00,0x20,0x21,0x00,0x40,0xf8,0x09,0x27,0xa6,0x00,0x10,0x8f,0x83,0x84,0xb0, ++0x3c,0x04,0x80,0x01,0x00,0x60,0x28,0x21,0x24,0x63,0x00,0x01,0xaf,0x83,0x84,0xb0, ++0x0c,0x00,0x1a,0x6b,0x24,0x84,0x04,0xa4,0x08,0x00,0x07,0xdf,0x00,0x00,0x00,0x00, ++0x08,0x00,0x07,0xd7,0xac,0x43,0x00,0x00,0x27,0xbd,0xff,0xe0,0xaf,0xb1,0x00,0x14, ++0xaf,0xbf,0x00,0x18,0x00,0x80,0x88,0x21,0x0c,0x00,0x1a,0xa2,0xaf,0xb0,0x00,0x10, ++0x00,0x40,0x20,0x21,0x24,0x02,0xff,0xff,0x10,0x82,0x00,0x1f,0x24,0x03,0x00,0x06, ++0x8f,0x85,0x84,0xc4,0x00,0x00,0x00,0x00,0x14,0xa0,0x00,0x0a,0x24,0x02,0x00,0x08, ++0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x3b,0x28,0x82,0x00,0x03,0x10,0x40,0x00,0x32, ++0x24,0x02,0x00,0x1b,0x24,0x02,0x00,0x01,0x10,0x82,0x00,0x13,0x24,0x03,0x00,0x08, ++0x24,0x02,0x00,0x08,0x10,0x82,0x00,0x23,0x24,0x02,0x00,0x0d,0x10,0x82,0x00,0x18, ++0x02,0x25,0x10,0x21,0x24,0xa3,0x00,0x01,0xa0,0x44,0x00,0x00,0xaf,0x83,0x84,0xc4, ++0x18,0x60,0x00,0x08,0x24,0x02,0x00,0x43,0x82,0x23,0x00,0x00,0x00,0x00,0x00,0x00, ++0x10,0x62,0x00,0x0a,0x00,0x00,0x00,0x00,0x30,0x84,0xff,0xff,0x0c,0x00,0x1a,0x9e, ++0x00,0x00,0x00,0x00,0x24,0x03,0x00,0x06,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc, ++0x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x3c,0x04,0x80,0x01, ++0x0c,0x00,0x1a,0x7e,0x24,0x84,0x04,0xb8,0x08,0x00,0x08,0x1e,0x24,0x03,0x00,0x06, ++0xa0,0x40,0x00,0x00,0x24,0xa5,0x00,0x01,0xaf,0x85,0x84,0xc4,0x0c,0x00,0x1a,0x9e, ++0x24,0x04,0x00,0x0d,0x24,0x03,0x00,0x07,0xaf,0x80,0x84,0xc4,0x08,0x00,0x08,0x1e, ++0x00,0x00,0x00,0x00,0x18,0xa0,0xff,0xeb,0x24,0xa5,0xff,0xff,0xaf,0x85,0x84,0xc4, ++0x0c,0x00,0x1a,0x9e,0x24,0x04,0x00,0x08,0x0c,0x00,0x1a,0x9e,0x24,0x04,0x00,0x20, ++0x08,0x00,0x08,0x1b,0x24,0x04,0x00,0x08,0x14,0x82,0xff,0xd2,0x24,0x02,0x00,0x08, ++0x0c,0x00,0x07,0x90,0x00,0x00,0x00,0x00,0x8f,0x85,0x84,0xc4,0x08,0x00,0x08,0x0c, ++0x24,0x04,0x00,0x0d,0x0c,0x00,0x30,0x54,0x02,0x20,0x20,0x21,0xaf,0x82,0x84,0xc4, ++0x04,0x40,0x00,0x0d,0x00,0x00,0x80,0x21,0x02,0x30,0x10,0x21,0x90,0x44,0x00,0x00, ++0x26,0x10,0x00,0x01,0x00,0x04,0x26,0x00,0x00,0x04,0x26,0x03,0x0c,0x00,0x1a,0x9e, ++0x30,0x84,0xff,0xff,0x8f,0x83,0x84,0xc4,0x00,0x00,0x00,0x00,0x00,0x70,0x18,0x2a, ++0x10,0x60,0xff,0xf6,0x02,0x30,0x10,0x21,0x08,0x00,0x08,0x2e,0x24,0x03,0x00,0x06, ++0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x27,0x83,0x8c,0xe8,0x24,0x02,0x00,0x07, ++0x24,0x42,0xff,0xff,0xac,0x60,0x00,0x00,0x04,0x41,0xff,0xfd,0x24,0x63,0x00,0x04, ++0x0c,0x00,0x08,0x66,0x00,0x00,0x00,0x00,0x8f,0x84,0x8c,0xe8,0x27,0x86,0x8c,0xe8, ++0x0c,0x00,0x08,0x83,0x00,0x40,0x28,0x21,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x27,0xbd,0xff,0xe0,0x00,0x80,0x28,0x21, ++0x27,0x84,0x8c,0xc8,0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x18,0x0c,0x00,0x30,0xe5, ++0xaf,0xb0,0x00,0x10,0x8f,0x85,0x83,0x34,0x27,0x84,0x8c,0xc8,0x0c,0x00,0x30,0xa9, ++0x00,0x00,0x88,0x21,0x10,0x40,0x00,0x0c,0x00,0x00,0x00,0x00,0x27,0x90,0x8c,0xe8, ++0x8f,0x85,0x83,0x34,0x00,0x00,0x20,0x21,0xae,0x02,0x00,0x00,0x0c,0x00,0x30,0xa9, ++0x26,0x31,0x00,0x01,0x26,0x10,0x00,0x04,0x10,0x40,0x00,0x03,0x2a,0x23,0x00,0x64, ++0x14,0x60,0xff,0xf7,0x00,0x00,0x00,0x00,0x02,0x20,0x10,0x21,0x8f,0xbf,0x00,0x18, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x27,0xbd,0xff,0xd0, ++0xaf,0xb6,0x00,0x28,0xaf,0xb5,0x00,0x24,0xaf,0xb4,0x00,0x20,0xaf,0xbf,0x00,0x2c, ++0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10, ++0x00,0xa0,0xa8,0x21,0x00,0x80,0xa0,0x21,0x00,0xc0,0xb0,0x21,0x10,0xa0,0x00,0x1d, ++0x24,0x02,0x00,0x05,0x3c,0x02,0x80,0x00,0x24,0x43,0x2c,0x80,0x8f,0x82,0x83,0xa4, ++0x00,0x00,0x00,0x00,0x10,0x43,0x00,0x1e,0x00,0x00,0x88,0x21,0x00,0x60,0x98,0x21, ++0x00,0x00,0x90,0x21,0x27,0x90,0x83,0xa4,0x8e,0x05,0xff,0xec,0x02,0x80,0x20,0x21, ++0x0c,0x00,0x30,0xed,0x26,0x10,0x00,0x18,0x10,0x40,0x00,0x06,0x02,0x51,0x18,0x21, ++0x8e,0x02,0x00,0x00,0x26,0x31,0x00,0x01,0x14,0x53,0xff,0xf7,0x00,0x11,0x90,0x40, ++0x02,0x51,0x18,0x21,0x27,0x82,0x83,0x94,0x00,0x03,0x18,0xc0,0x00,0x62,0x18,0x21, ++0x8c,0x62,0x00,0x10,0x02,0x20,0x20,0x21,0x02,0xa0,0x28,0x21,0x00,0x40,0xf8,0x09, ++0x02,0xc0,0x30,0x21,0x8f,0xbf,0x00,0x2c,0x8f,0xb6,0x00,0x28,0x7b,0xb4,0x01,0x3c, ++0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30, ++0x08,0x00,0x08,0xa4,0x00,0x00,0x90,0x21,0x27,0xbd,0xff,0xc0,0xaf,0xb5,0x00,0x34, ++0xaf,0xb3,0x00,0x2c,0xaf,0xb1,0x00,0x24,0xaf,0xbf,0x00,0x38,0xaf,0xb4,0x00,0x30, ++0xaf,0xb2,0x00,0x28,0xaf,0xb0,0x00,0x20,0x00,0xc0,0x98,0x21,0x30,0xa5,0x00,0xff, ++0xac,0xc0,0x00,0x00,0x24,0x15,0x00,0x0a,0x00,0x00,0x88,0x21,0x27,0xa8,0x00,0x10, ++0x00,0x91,0x18,0x21,0x80,0x62,0x00,0x00,0x26,0x27,0x00,0x01,0x10,0x40,0x00,0x0c, ++0x01,0x11,0x30,0x21,0x90,0x63,0x00,0x00,0x30,0xf1,0x00,0xff,0x2e,0x22,0x00,0x0a, ++0x14,0x40,0xff,0xf7,0xa0,0xc3,0x00,0x00,0x8f,0xbf,0x00,0x38,0x7b,0xb4,0x01,0xbc, ++0x7b,0xb2,0x01,0x7c,0x7b,0xb0,0x01,0x3c,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40, ++0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x23,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x1f, ++0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x1a,0x00,0x00,0x00,0x00,0x02,0x20,0x90,0x21, ++0x12,0x40,0xff,0xf1,0x00,0x00,0x88,0x21,0x27,0xb4,0x00,0x10,0x02,0x91,0x10,0x21, ++0x90,0x44,0x00,0x00,0x0c,0x00,0x09,0x0a,0x00,0x00,0x00,0x00,0x02,0x51,0x20,0x23, ++0x24,0x84,0xff,0xff,0x30,0x84,0x00,0xff,0x02,0xa0,0x28,0x21,0x0c,0x00,0x08,0xfb, ++0x00,0x40,0x80,0x21,0x02,0x02,0x00,0x18,0x8e,0x63,0x00,0x00,0x26,0x22,0x00,0x01, ++0x30,0x51,0x00,0xff,0x02,0x32,0x20,0x2b,0x00,0x00,0x80,0x12,0x00,0x70,0x18,0x21, ++0x14,0x80,0xff,0xee,0xae,0x63,0x00,0x00,0x08,0x00,0x08,0xce,0x00,0x00,0x00,0x00, ++0x80,0x82,0x00,0x00,0x08,0x00,0x08,0xce,0xae,0x62,0x00,0x00,0x08,0x00,0x08,0xdb, ++0x24,0x15,0x00,0x10,0x08,0x00,0x08,0xdb,0x24,0x15,0x00,0x0a,0x30,0x84,0x00,0xff, ++0x30,0xa5,0x00,0xff,0x24,0x06,0x00,0x01,0x10,0x80,0x00,0x09,0x00,0x00,0x10,0x21, ++0x00,0xc5,0x00,0x18,0x24,0x42,0x00,0x01,0x30,0x42,0x00,0xff,0x00,0x44,0x18,0x2b, ++0x00,0x00,0x30,0x12,0x00,0x00,0x00,0x00,0x14,0x60,0xff,0xfa,0x00,0xc5,0x00,0x18, ++0x03,0xe0,0x00,0x08,0x00,0xc0,0x10,0x21,0x30,0x84,0x00,0xff,0x24,0x83,0xff,0xd0, ++0x30,0x62,0x00,0xff,0x2c,0x42,0x00,0x0a,0x14,0x40,0x00,0x06,0x00,0x00,0x00,0x00, ++0x24,0x82,0xff,0xbf,0x2c,0x42,0x00,0x06,0x14,0x40,0x00,0x02,0x24,0x83,0xff,0xc9, ++0x24,0x83,0xff,0xa9,0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,0x27,0xbd,0xff,0xc8, ++0x24,0x02,0x00,0x01,0xaf,0xbf,0x00,0x30,0xaf,0xb5,0x00,0x2c,0xaf,0xb4,0x00,0x28, ++0xaf,0xb3,0x00,0x24,0xaf,0xb2,0x00,0x20,0xaf,0xb1,0x00,0x1c,0x10,0xa2,0x00,0x3e, ++0xaf,0xb0,0x00,0x18,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x08,0x24,0x05,0x00,0x01, ++0x00,0x00,0x10,0x21,0x8f,0xbf,0x00,0x30,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c, ++0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0x8c,0xc4,0x00,0x04, ++0x0c,0x00,0x08,0xb6,0x27,0xa6,0x00,0x10,0x8f,0xa2,0x00,0x10,0x00,0x00,0x00,0x00, ++0x28,0x42,0x00,0x65,0x14,0x40,0x00,0x06,0x00,0x00,0x00,0x00,0x3c,0x04,0x80,0x01, ++0x0c,0x00,0x1a,0x7e,0x24,0x84,0x04,0xbc,0x08,0x00,0x09,0x25,0x24,0x02,0x00,0x01, ++0x3c,0x04,0x80,0x01,0x0c,0x00,0x1a,0x7e,0x24,0x84,0x04,0xc8,0x8f,0x83,0x83,0xa4, ++0x3c,0x02,0x80,0x00,0x24,0x42,0x2c,0x80,0x10,0x62,0xff,0xe5,0x00,0x40,0x90,0x21, ++0x3c,0x13,0x80,0x01,0x27,0x95,0x83,0x90,0x3c,0x14,0x80,0x01,0x27,0x90,0x83,0x94, ++0x00,0x00,0x88,0x21,0x8e,0x03,0x00,0x08,0x8f,0xa2,0x00,0x10,0x00,0x00,0x00,0x00, ++0x10,0x62,0x00,0x08,0x26,0x64,0x04,0xd4,0x26,0x10,0x00,0x18,0x8e,0x02,0x00,0x10, ++0x00,0x00,0x00,0x00,0x14,0x52,0xff,0xf7,0x26,0x31,0x00,0x18,0x08,0x00,0x09,0x25, ++0x00,0x00,0x10,0x21,0x0c,0x00,0x1a,0x7e,0x00,0x00,0x00,0x00,0x02,0x35,0x10,0x21, ++0x8c,0x44,0x00,0x00,0x0c,0x00,0x1a,0x7e,0x00,0x00,0x00,0x00,0x0c,0x00,0x1a,0x7e, ++0x26,0x84,0x04,0xd8,0x8e,0x04,0x00,0x00,0x0c,0x00,0x1a,0x7e,0x26,0x10,0x00,0x18, ++0x08,0x00,0x09,0x4b,0x00,0x00,0x00,0x00,0x3c,0x04,0x80,0x01,0x0c,0x00,0x1a,0x7e, ++0x24,0x84,0x04,0xdc,0x3c,0x04,0x80,0x01,0x0c,0x00,0x1a,0x6b,0x24,0x84,0x04,0xec, ++0x24,0x11,0x00,0x05,0x3c,0x12,0x80,0x01,0x27,0x90,0x88,0x0e,0x86,0x05,0x00,0x00, ++0x26,0x44,0x05,0x0c,0x0c,0x00,0x1a,0x6b,0x26,0x31,0xff,0xff,0x06,0x21,0xff,0xfb, ++0x26,0x10,0xff,0xfe,0x08,0x00,0x09,0x25,0x00,0x00,0x10,0x21,0x27,0xbd,0xff,0xd0, ++0x28,0xa2,0x00,0x02,0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,0xaf,0xbf,0x00,0x2c, ++0xaf,0xb4,0x00,0x28,0xaf,0xb3,0x00,0x24,0xaf,0xb2,0x00,0x20,0x00,0xa0,0x80,0x21, ++0x14,0x40,0x00,0x51,0x00,0xc0,0x88,0x21,0x8c,0xc4,0x00,0x04,0x24,0x05,0x00,0x02, ++0x0c,0x00,0x08,0xb6,0x27,0xa6,0x00,0x10,0x24,0x02,0x00,0x02,0x12,0x02,0x00,0x48, ++0x24,0x05,0x00,0x01,0x8e,0x24,0x00,0x08,0x0c,0x00,0x08,0xb6,0x27,0xa6,0x00,0x14, ++0x8f,0xa2,0x00,0x14,0x00,0x00,0x00,0x00,0x30,0x42,0x0f,0xff,0xaf,0xa2,0x00,0x14, ++0x7b,0xa4,0x00,0xbc,0x0c,0x00,0x0a,0x06,0x24,0x06,0x00,0x04,0x24,0x03,0x00,0x04, ++0x10,0x43,0x00,0x2a,0x24,0x04,0x00,0x04,0x8f,0xa2,0x00,0x10,0x3c,0x04,0x80,0x01, ++0x24,0x84,0x05,0x10,0x00,0x02,0x19,0x02,0x00,0x03,0x81,0x00,0x8f,0xa3,0x00,0x14, ++0x00,0x50,0x10,0x23,0x00,0x02,0x10,0x82,0x00,0x62,0x18,0x21,0x0c,0x00,0x1a,0x7e, ++0xaf,0xa3,0x00,0x14,0x3c,0x04,0x80,0x01,0x0c,0x00,0x1a,0x7e,0x24,0x84,0x05,0x38, ++0x8f,0xa2,0x00,0x14,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x17,0x00,0x00,0x88,0x21, ++0x3c,0x13,0x80,0x01,0x3c,0x12,0x80,0x01,0x3c,0x14,0x80,0x01,0x0c,0x00,0x2e,0x24, ++0x24,0x04,0x27,0x10,0x32,0x23,0x00,0x03,0x02,0x00,0x28,0x21,0x10,0x60,0x00,0x1c, ++0x26,0x64,0x05,0x64,0x8f,0xa2,0x00,0x10,0x00,0x00,0x00,0x00,0x02,0x02,0x10,0x23, ++0x28,0x42,0xff,0xfd,0x10,0x40,0x00,0x10,0x26,0x44,0x05,0x70,0x0c,0x00,0x1a,0x7e, ++0x26,0x10,0x00,0x04,0x8f,0xa2,0x00,0x14,0x26,0x31,0x00,0x01,0x02,0x22,0x10,0x2b, ++0x14,0x40,0xff,0xee,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x21,0x8f,0xbf,0x00,0x2c, ++0x8f,0xb4,0x00,0x28,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x00,0x80,0x10,0x21, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,0x8e,0x05,0x00,0x00,0x26,0x84,0x05,0x74, ++0x0c,0x00,0x1a,0x6b,0x26,0x10,0x00,0x04,0x08,0x00,0x09,0xb1,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x1a,0x6b,0x00,0x00,0x00,0x00,0x08,0x00,0x09,0xa9,0x00,0x00,0x00,0x00, ++0x08,0x00,0x09,0x87,0x24,0x02,0x00,0x01,0x0c,0x00,0x0b,0x2b,0x00,0x00,0x00,0x00, ++0x08,0x00,0x09,0xb7,0x24,0x04,0x00,0x04,0x27,0xbd,0xff,0xd0,0x28,0xa2,0x00,0x03, ++0xaf,0xb1,0x00,0x24,0xaf,0xb0,0x00,0x20,0xaf,0xbf,0x00,0x28,0x00,0xa0,0x88,0x21, ++0x10,0x40,0x00,0x09,0x00,0xc0,0x80,0x21,0x0c,0x00,0x0b,0x2b,0x00,0x00,0x00,0x00, ++0x24,0x04,0x00,0x04,0x8f,0xbf,0x00,0x28,0x7b,0xb0,0x01,0x3c,0x00,0x80,0x10,0x21, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,0x8c,0xc4,0x00,0x04,0x24,0x05,0x00,0x02, ++0x0c,0x00,0x08,0xb6,0x27,0xa6,0x00,0x10,0x8e,0x04,0x00,0x08,0x24,0x05,0x00,0x02, ++0x0c,0x00,0x08,0xb6,0x27,0xa6,0x00,0x14,0x24,0x02,0x00,0x03,0x12,0x22,0x00,0x1b, ++0x24,0x05,0x00,0x01,0x8e,0x04,0x00,0x0c,0x0c,0x00,0x08,0xb6,0x27,0xa6,0x00,0x18, ++0x8f,0xa4,0x00,0x10,0x8f,0xa5,0x00,0x18,0x0c,0x00,0x0a,0x06,0x24,0x06,0x00,0x04, ++0x24,0x03,0x00,0x04,0x10,0x43,0xff,0xe7,0x24,0x04,0x00,0x04,0x8f,0xa2,0x00,0x18, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0b,0x00,0x00,0x28,0x21,0x8f,0xa2,0x00,0x10, ++0x8f,0xa4,0x00,0x14,0x24,0xa5,0x00,0x01,0xac,0x44,0x00,0x00,0x8f,0xa3,0x00,0x10, ++0x8f,0xa2,0x00,0x18,0x24,0x63,0x00,0x04,0x00,0xa2,0x10,0x2b,0x14,0x40,0xff,0xf7, ++0xaf,0xa3,0x00,0x10,0x08,0x00,0x09,0xd9,0x00,0x00,0x20,0x21,0x24,0x02,0x00,0x01, ++0x08,0x00,0x09,0xec,0xaf,0xa2,0x00,0x18,0x30,0xc6,0x00,0xff,0x00,0xa6,0x00,0x18, ++0x00,0x00,0x28,0x12,0x04,0x81,0x00,0x07,0x00,0x00,0x30,0x21,0x3c,0x02,0x80,0x01, ++0x00,0x85,0x18,0x21,0x34,0x42,0x7f,0xff,0x00,0x43,0x10,0x2b,0x10,0x40,0x00,0x0b, ++0x3c,0x02,0xb0,0x03,0x3c,0x02,0xaf,0xff,0x34,0x42,0xff,0xff,0x00,0x44,0x10,0x2b, ++0x10,0x40,0x00,0x17,0x3c,0x02,0xb0,0x0a,0x00,0x85,0x18,0x21,0x34,0x42,0xff,0xff, ++0x00,0x43,0x10,0x2b,0x14,0x40,0x00,0x12,0x3c,0x02,0xb0,0x03,0x34,0x42,0xff,0xff, ++0x00,0x44,0x10,0x2b,0x10,0x40,0x00,0x06,0x3c,0x02,0xb0,0x07,0x3c,0x02,0xb0,0x04, ++0x34,0x42,0xff,0xff,0x00,0x43,0x10,0x2b,0x10,0x40,0x00,0x09,0x3c,0x02,0xb0,0x07, ++0x34,0x42,0x00,0x3f,0x00,0x44,0x10,0x2b,0x10,0x40,0x00,0x06,0x3c,0x02,0xb0,0x07, ++0x34,0x42,0xff,0xff,0x00,0x43,0x10,0x2b,0x14,0x40,0x00,0x02,0x00,0x00,0x00,0x00, ++0x24,0x06,0x00,0x01,0x14,0xc0,0x00,0x11,0x24,0x02,0x00,0x04,0x3c,0x02,0xb0,0x08, ++0x34,0x42,0x0f,0xff,0x00,0x44,0x10,0x2b,0x14,0x40,0x00,0x08,0x3c,0x02,0x4f,0xf7, ++0x00,0x85,0x20,0x21,0x34,0x42,0xf0,0x00,0x00,0x82,0x20,0x21,0x34,0x03,0xef,0xff, ++0x00,0x64,0x18,0x2b,0x14,0x60,0x00,0x02,0x00,0x00,0x00,0x00,0x24,0x06,0x00,0x02, ++0x10,0xc0,0x00,0x02,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x04,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe0,0x24,0x02,0x00,0x02,0xaf,0xb0,0x00,0x18, ++0xaf,0xbf,0x00,0x1c,0x10,0xa2,0x00,0x23,0x00,0xc0,0x80,0x21,0x28,0xa2,0x00,0x03, ++0x10,0x40,0x00,0x0c,0x24,0x02,0x00,0x03,0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x04, ++0x00,0x00,0x18,0x21,0x0c,0x00,0x0b,0x2b,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x21, ++0x8f,0xbf,0x00,0x1c,0x8f,0xb0,0x00,0x18,0x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x20,0x14,0xa2,0xff,0xf7,0x24,0x05,0x00,0x01,0x8c,0xc4,0x00,0x04, ++0x0c,0x00,0x08,0xb6,0x27,0xa6,0x00,0x10,0x8e,0x04,0x00,0x08,0x24,0x05,0x00,0x02, ++0x0c,0x00,0x08,0xb6,0x27,0xa6,0x00,0x14,0x8f,0xa4,0x00,0x10,0x00,0x00,0x00,0x00, ++0x2c,0x82,0x00,0x0b,0x10,0x40,0xff,0xee,0x24,0x03,0x00,0x04,0x00,0x04,0x10,0x80, ++0x8f,0xa4,0x00,0x14,0x27,0x83,0x94,0xc0,0x00,0x43,0x10,0x21,0x08,0x00,0x0a,0x4f, ++0xac,0x44,0x00,0x00,0x8c,0xc4,0x00,0x04,0x24,0x05,0x00,0x01,0x0c,0x00,0x08,0xb6, ++0x27,0xa6,0x00,0x10,0x8f,0xa5,0x00,0x10,0x27,0x83,0x94,0xc0,0x3c,0x04,0x80,0x01, ++0x00,0x05,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x46,0x00,0x00,0x0c,0x00,0x1a,0x6b, ++0x24,0x84,0x05,0x7c,0x08,0x00,0x0a,0x50,0x00,0x00,0x18,0x21,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xb8,0x28,0xa5,0x00,0x04,0xaf,0xb0,0x00,0x20, ++0xaf,0xbf,0x00,0x40,0xaf,0xb7,0x00,0x3c,0xaf,0xb6,0x00,0x38,0xaf,0xb5,0x00,0x34, ++0xaf,0xb4,0x00,0x30,0xaf,0xb3,0x00,0x2c,0xaf,0xb2,0x00,0x28,0xaf,0xb1,0x00,0x24, ++0x10,0xa0,0x00,0x0b,0x00,0xc0,0x80,0x21,0x0c,0x00,0x0b,0x2b,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x04,0x8f,0xbf,0x00,0x40,0x7b,0xb6,0x01,0xfc,0x7b,0xb4,0x01,0xbc, ++0x7b,0xb2,0x01,0x7c,0x7b,0xb0,0x01,0x3c,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x48, ++0x8c,0xc4,0x00,0x04,0x24,0x05,0x00,0x01,0x0c,0x00,0x08,0xb6,0x27,0xa6,0x00,0x10, ++0x8e,0x04,0x00,0x08,0x24,0x05,0x00,0x01,0x0c,0x00,0x08,0xb6,0x27,0xa6,0x00,0x14, ++0x8e,0x04,0x00,0x0c,0x24,0x05,0x00,0x01,0x0c,0x00,0x08,0xb6,0x27,0xa6,0x00,0x18, ++0x8f,0xa3,0x00,0x18,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x3a,0x24,0x02,0x00,0x01, ++0x10,0x62,0x00,0x33,0x3c,0x04,0x80,0x01,0x97,0xb0,0x00,0x12,0x8f,0xa2,0x00,0x14, ++0x00,0x00,0x00,0x00,0x02,0x02,0x10,0x2b,0x10,0x40,0xff,0xe2,0x3c,0x15,0x80,0x01, ++0x3c,0x02,0x80,0x01,0x24,0x52,0x05,0xbc,0x3c,0x14,0xb0,0x06,0x24,0x13,0x00,0x01, ++0x3c,0x17,0xb0,0x08,0x3c,0x16,0x80,0x01,0x32,0x02,0x00,0x01,0x02,0x00,0x28,0x21, ++0x10,0x40,0x00,0x1f,0x26,0xa4,0x05,0xb0,0x8f,0xa3,0x00,0x18,0x00,0x10,0x10,0xc0, ++0x00,0x54,0x10,0x21,0x10,0x60,0x00,0x14,0x02,0x40,0x20,0x21,0x00,0x10,0x10,0xc0, ++0x00,0x57,0x10,0x21,0x10,0x73,0x00,0x09,0x26,0xc4,0x05,0xc4,0x8f,0xa2,0x00,0x14, ++0x26,0x03,0x00,0x01,0x30,0x70,0xff,0xff,0x02,0x02,0x10,0x2b,0x14,0x40,0xff,0xee, ++0x00,0x00,0x00,0x00,0x08,0x00,0x0a,0x8d,0x00,0x00,0x00,0x00,0x8c,0x51,0x00,0x00, ++0x00,0x00,0x00,0x00,0x32,0x25,0x00,0xff,0x0c,0x00,0x1a,0x6b,0x00,0x00,0x00,0x00, ++0x08,0x00,0x0a,0xbf,0x00,0x00,0x00,0x00,0x8c,0x51,0x00,0x00,0x0c,0x00,0x1a,0x6b, ++0x00,0x11,0x2c,0x02,0x32,0x25,0x00,0xff,0x08,0x00,0x0a,0xca,0x02,0x40,0x20,0x21, ++0x0c,0x00,0x1a,0x6b,0x00,0x00,0x00,0x00,0x08,0x00,0x0a,0xb6,0x00,0x00,0x00,0x00, ++0x24,0x84,0x05,0x90,0x0c,0x00,0x1a,0x7e,0x00,0x00,0x00,0x00,0x08,0x00,0x0a,0xa6, ++0x00,0x00,0x00,0x00,0x3c,0x04,0x80,0x01,0x08,0x00,0x0a,0xd9,0x24,0x84,0x05,0xd0, ++0x00,0xa0,0x10,0x21,0x27,0xbd,0xff,0xd8,0x28,0x42,0x00,0x04,0xaf,0xb0,0x00,0x20, ++0xaf,0xbf,0x00,0x24,0x00,0xc0,0x80,0x21,0x24,0x05,0x00,0x01,0x10,0x40,0x00,0x08, ++0x27,0xa6,0x00,0x10,0x0c,0x00,0x0b,0x2b,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x04, ++0x8f,0xbf,0x00,0x24,0x8f,0xb0,0x00,0x20,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28, ++0x8e,0x04,0x00,0x04,0x0c,0x00,0x08,0xb6,0x00,0x00,0x00,0x00,0x8e,0x04,0x00,0x08, ++0x24,0x05,0x00,0x01,0x0c,0x00,0x08,0xb6,0x27,0xa6,0x00,0x14,0x8e,0x04,0x00,0x0c, ++0x24,0x05,0x00,0x01,0x0c,0x00,0x08,0xb6,0x27,0xa6,0x00,0x18,0x08,0x00,0x0a,0xec, ++0x24,0x02,0x00,0x01,0x24,0x03,0x00,0x01,0x00,0x65,0x10,0x2a,0x27,0xbd,0xff,0xd8, ++0x00,0xa0,0x40,0x21,0x10,0x40,0x00,0x0b,0x00,0xc0,0x38,0x21,0x00,0x03,0x20,0x80, ++0x00,0x87,0x10,0x21,0x8c,0x45,0x00,0x00,0x24,0x63,0x00,0x01,0x30,0x63,0x00,0xff, ++0x8c,0xa6,0x00,0x00,0x00,0x9d,0x20,0x21,0x00,0x68,0x10,0x2a,0x14,0x40,0xff,0xf7, ++0xac,0x86,0xff,0xfc,0x8f,0xa3,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x0b, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0x62,0x00,0x03,0x00,0x00,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x93,0xa2,0x00,0x07,0x00,0x00,0x00,0x00, ++0xa3,0x82,0x87,0x6c,0x08,0x00,0x0b,0x14,0x00,0x00,0x00,0x00,0x93,0xa2,0x00,0x07, ++0x00,0x00,0x00,0x00,0xa3,0x82,0x94,0xb0,0x08,0x00,0x0b,0x14,0x00,0x00,0x00,0x00, ++0x27,0xbd,0xff,0xe8,0x3c,0x04,0x80,0x01,0xaf,0xbf,0x00,0x10,0x18,0xa0,0x00,0x03, ++0x24,0x84,0x05,0xf8,0x0c,0x00,0x1a,0x7e,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x10, ++0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x27,0xbd,0xff,0xe8, ++0xaf,0xb0,0x00,0x10,0x00,0x80,0x80,0x21,0x3c,0x04,0x80,0x01,0xaf,0xbf,0x00,0x14, ++0x0c,0x00,0x1a,0x7e,0x24,0x84,0x06,0x0c,0x00,0x10,0x10,0x40,0x00,0x50,0x10,0x21, ++0x27,0x83,0x83,0x90,0x00,0x02,0x10,0xc0,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x08, ++0x0c,0x00,0x1a,0x7e,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00, ++0x34,0x63,0x00,0x20,0x24,0x42,0x2c,0xf8,0x3c,0x04,0xb0,0x03,0xac,0x62,0x00,0x00, ++0x34,0x84,0x00,0x2c,0x8c,0x86,0x00,0x00,0x3c,0x05,0xb0,0x0a,0x34,0xa5,0x1a,0x00, ++0x00,0x06,0x1a,0x02,0x30,0x63,0x0f,0xff,0x00,0x06,0x25,0x02,0x24,0x02,0xff,0xff, ++0xac,0xa2,0x00,0x00,0xa7,0x83,0xc5,0x4a,0xa7,0x84,0xc5,0x4c,0xa3,0x86,0xc5,0x48, ++0xa7,0x80,0xc5,0x40,0xa7,0x80,0xc5,0x42,0xa7,0x80,0xc5,0x44,0xa7,0x80,0xc5,0x46, ++0x00,0xa0,0x38,0x21,0x24,0x03,0x00,0x01,0x8c,0xe2,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x0a,0x00,0x8c,0x45,0x00,0x00, ++0x3c,0x04,0xb0,0x0a,0x34,0x84,0x1a,0x00,0xa0,0x45,0x00,0x00,0x24,0x03,0x00,0x01, ++0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a, ++0x34,0x42,0x0a,0x00,0x3c,0x04,0xb0,0x0a,0xa0,0x45,0x00,0x00,0x34,0x84,0x1a,0x00, ++0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x04,0xb0,0x03,0x34,0x63,0x01,0x08, ++0x34,0x84,0x01,0x18,0x8c,0x65,0x00,0x00,0x8c,0x82,0x00,0x00,0xaf,0x85,0xc5,0x50, ++0x30,0x42,0x02,0x00,0x10,0x40,0x00,0x06,0x3c,0x02,0x00,0x0f,0x3c,0x02,0x00,0x4c, ++0x34,0x42,0x4b,0x40,0xaf,0x82,0xc5,0x54,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x08,0x00,0x0b,0x79,0x34,0x42,0x42,0x40,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00, ++0x34,0x63,0x00,0x20,0x24,0x42,0x2d,0xf8,0x30,0x84,0x00,0xff,0xac,0x62,0x00,0x00, ++0x14,0x80,0x02,0xb3,0x24,0x02,0x00,0x02,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x1b,0x40, ++0x24,0x02,0xff,0xff,0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01, ++0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a, ++0x34,0x42,0x0b,0x40,0x8c,0x46,0x00,0x00,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x1b,0x48, ++0x24,0x02,0xff,0xff,0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21,0x00,0x06,0x54,0x02, ++0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd, ++0x3c,0x02,0xb0,0x0a,0x34,0x42,0x0b,0x48,0x8c,0x46,0x00,0x00,0x3c,0x03,0xb0,0x0a, ++0x34,0x63,0x1b,0x50,0x24,0x02,0xff,0xff,0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21, ++0x00,0x06,0x64,0x02,0x30,0xcb,0xff,0xff,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x0b,0x50, ++0x8c,0x46,0x00,0x00,0x97,0x84,0xc5,0x40,0x97,0x82,0xc5,0x42,0x97,0x83,0xc5,0x46, ++0x01,0x44,0x20,0x23,0x01,0x62,0x10,0x23,0x00,0x82,0x20,0x21,0x97,0x82,0xc5,0x44, ++0x30,0xcd,0xff,0xff,0x01,0xa3,0x18,0x23,0x01,0x82,0x10,0x23,0x00,0x82,0x20,0x21, ++0x93,0x82,0xc5,0x48,0x00,0x83,0x20,0x21,0x30,0x84,0xff,0xff,0x00,0x82,0x10,0x2b, ++0x10,0x40,0x00,0xec,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x18,0xa0,0x24,0x02,0xff,0xff, ++0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x08,0xa0, ++0x8c,0x46,0x00,0x00,0x24,0x02,0x00,0x20,0x30,0xc8,0x00,0x7f,0x11,0x02,0x00,0x4d, ++0x2d,0x02,0x00,0x21,0x14,0x40,0x00,0x2b,0x24,0x02,0xff,0x80,0x00,0xc2,0x10,0x24, ++0x25,0x08,0xff,0xff,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x08,0xa0,0x00,0x48,0x30,0x25, ++0x3c,0x04,0xb0,0x0a,0xac,0x66,0x00,0x00,0x34,0x84,0x18,0xa0,0x24,0x03,0x00,0x01, ++0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a, ++0x34,0x42,0x08,0xb0,0x3c,0x04,0xb0,0x0a,0xac,0x46,0x00,0x00,0x34,0x84,0x18,0xb0, ++0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd, ++0x3c,0x02,0xb0,0x0a,0x34,0x42,0x08,0xc0,0x3c,0x04,0xb0,0x0a,0xac,0x46,0x00,0x00, ++0x34,0x84,0x18,0xc0,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x08,0xd0,0x3c,0x04,0xb0,0x0a, ++0xac,0x46,0x00,0x00,0x34,0x84,0x18,0xd0,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x24,0x02,0x00,0x20,0x11,0x02,0x00,0x07, ++0x24,0x02,0xff,0xff,0xa7,0x8a,0xc5,0x40,0xa7,0x8b,0xc5,0x42,0xa7,0x8c,0xc5,0x44, ++0xa7,0x8d,0xc5,0x46,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x0a, ++0x34,0x63,0x14,0x58,0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01, ++0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0x00,0x00,0x00, ++0x3c,0x03,0xb0,0x0a,0x34,0x63,0x04,0x58,0x8c,0x69,0x00,0x00,0x3c,0x02,0xff,0xff, ++0x34,0x42,0x3f,0xff,0x01,0x22,0x10,0x24,0x34,0x49,0x80,0x00,0x3c,0x04,0xb0,0x0a, ++0xac,0x69,0x00,0x00,0x34,0x84,0x14,0x58,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0x00,0x00,0x00,0x08,0x00,0x0b,0xf9, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x14,0x58,0x24,0x02,0xff,0xff, ++0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x04,0x58, ++0x8c,0x49,0x00,0x00,0x3c,0x04,0xb0,0x0a,0x34,0x84,0x14,0x58,0x35,0x29,0x40,0x00, ++0xac,0x49,0x00,0x00,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x24,0x02,0xff,0xff,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x14,0xb0, ++0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x04,0xb0, ++0x8c,0x47,0x00,0x00,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x14,0xb8,0x3c,0x05,0xb0,0x0a, ++0x24,0x02,0xff,0xff,0xac,0x62,0x00,0x00,0x34,0xa5,0x14,0xb8,0x00,0x07,0x1e,0x02, ++0x24,0x04,0x00,0x01,0x8c,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x44,0xff,0xfd, ++0x3c,0x02,0xb0,0x0a,0x34,0x42,0x04,0xb8,0x8c,0x47,0x00,0x00,0x00,0x03,0x1a,0x00, ++0x30,0xe2,0x00,0xff,0x00,0x62,0x18,0x25,0x2c,0x62,0x00,0x04,0x10,0x40,0x00,0x3a, ++0x2c,0x62,0x00,0x11,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x14,0x10,0x24,0x02,0xff,0xff, ++0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x04,0x10, ++0x8c,0x47,0x00,0x00,0x24,0x02,0x00,0x03,0x00,0x07,0x1d,0x82,0x30,0x64,0x00,0x03, ++0x10,0x82,0x00,0x1a,0x3c,0x02,0xff,0x3f,0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff, ++0x3c,0x03,0xb0,0x0a,0x34,0x63,0x04,0x58,0x01,0x22,0x48,0x24,0x3c,0x04,0xb0,0x0a, ++0xac,0x69,0x00,0x00,0x34,0x84,0x14,0x58,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x35,0x29,0x80,0x00, ++0x34,0x42,0x04,0x58,0x3c,0x04,0xb0,0x0a,0xac,0x49,0x00,0x00,0x34,0x84,0x14,0x58, ++0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd, ++0x2d,0x02,0x00,0x21,0x08,0x00,0x0b,0xcd,0x00,0x00,0x00,0x00,0x34,0x42,0xff,0xff, ++0x3c,0x03,0x00,0x80,0x00,0xe2,0x10,0x24,0x00,0x43,0x38,0x25,0x3c,0x04,0xb0,0x0a, ++0x3c,0x01,0xb0,0x0a,0xac,0x27,0x04,0x10,0x34,0x84,0x14,0x10,0x24,0x03,0x00,0x01, ++0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xff,0xff, ++0x08,0x00,0x0c,0x60,0x34,0x42,0x3f,0xff,0x14,0x40,0xff,0xd8,0x3c,0x02,0xff,0xff, ++0x3c,0x03,0xb0,0x0a,0x34,0x63,0x14,0x10,0x24,0x02,0xff,0xff,0xac,0x62,0x00,0x00, ++0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x04,0x10,0x8c,0x47,0x00,0x00, ++0x3c,0x05,0x00,0xc0,0x24,0x03,0x00,0x02,0x00,0xe5,0x10,0x24,0x00,0x02,0x25,0x82, ++0x14,0x83,0xff,0xc6,0x3c,0x02,0xff,0xff,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff, ++0x00,0xe2,0x10,0x24,0x00,0x45,0x38,0x25,0x3c,0x04,0xb0,0x0a,0x3c,0x01,0xb0,0x0a, ++0xac,0x27,0x04,0x10,0x34,0x84,0x14,0x10,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xff,0xff,0x08,0x00,0x0c,0x60, ++0x34,0x42,0x3f,0xff,0x97,0x82,0xc5,0x4c,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x2b, ++0x10,0x40,0x00,0x74,0x34,0x63,0x18,0xa0,0x24,0x02,0xff,0xff,0xac,0x62,0x00,0x00, ++0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x08,0xa0,0x8c,0x46,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0xc8,0x00,0x7f,0x2d,0x02,0x00,0x32,0x10,0x40,0xff,0x3d, ++0x24,0x02,0x00,0x20,0x11,0x02,0x00,0x2b,0x24,0x02,0xff,0x80,0x00,0xc2,0x10,0x24, ++0x25,0x08,0x00,0x02,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x08,0xa0,0x00,0x48,0x30,0x25, ++0x3c,0x04,0xb0,0x0a,0xac,0x66,0x00,0x00,0x34,0x84,0x18,0xa0,0x24,0x03,0x00,0x01, ++0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a, ++0x34,0x42,0x08,0xb0,0x3c,0x04,0xb0,0x0a,0xac,0x46,0x00,0x00,0x34,0x84,0x18,0xb0, ++0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd, ++0x3c,0x02,0xb0,0x0a,0x34,0x42,0x08,0xc0,0x3c,0x04,0xb0,0x0a,0xac,0x46,0x00,0x00, ++0x34,0x84,0x18,0xc0,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x08,0xd0,0x3c,0x04,0xb0,0x0a, ++0xac,0x46,0x00,0x00,0x34,0x84,0x18,0xd0,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0x00,0x00,0x00,0x08,0x00,0x0b,0xf9, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x14,0x10,0x24,0x02,0xff,0xff, ++0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x04,0x10, ++0x8c,0x47,0x00,0x00,0x3c,0x05,0x00,0xc0,0x24,0x03,0x00,0x03,0x00,0xe5,0x10,0x24, ++0x00,0x02,0x25,0x82,0x10,0x83,0x00,0x0d,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff, ++0x00,0xe2,0x10,0x24,0x00,0x45,0x38,0x25,0x3c,0x04,0xb0,0x0a,0x3c,0x01,0xb0,0x0a, ++0xac,0x27,0x04,0x10,0x34,0x84,0x14,0x10,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x0a, ++0x34,0x63,0x14,0x58,0x24,0x02,0xff,0xff,0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21, ++0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x04,0x58,0x8c,0x69,0x00,0x00, ++0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,0x01,0x22,0x48,0x24,0x3c,0x04,0xb0,0x0a, ++0xac,0x69,0x00,0x00,0x34,0x84,0x14,0x58,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x24,0x02,0xff,0x80,0x08,0x00,0x0c,0xc0, ++0x00,0xc2,0x10,0x24,0x97,0x82,0xc5,0x4a,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x2b, ++0x10,0x40,0x00,0x75,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x18,0xa0,0x24,0x02,0xff,0xff, ++0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x08,0xa0, ++0x8c,0x46,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0xc8,0x00,0x7f,0x2d,0x02,0x00,0x32, ++0x10,0x40,0xfe,0xc4,0x24,0x02,0x00,0x20,0x11,0x02,0x00,0x2b,0x24,0x02,0xff,0x80, ++0x00,0xc2,0x10,0x24,0x25,0x08,0x00,0x01,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x08,0xa0, ++0x00,0x48,0x30,0x25,0x3c,0x04,0xb0,0x0a,0xac,0x66,0x00,0x00,0x34,0x84,0x18,0xa0, ++0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd, ++0x3c,0x02,0xb0,0x0a,0x34,0x42,0x08,0xb0,0x3c,0x04,0xb0,0x0a,0xac,0x46,0x00,0x00, ++0x34,0x84,0x18,0xb0,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x08,0xc0,0x3c,0x04,0xb0,0x0a, ++0xac,0x46,0x00,0x00,0x34,0x84,0x18,0xc0,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x08,0xd0, ++0x3c,0x04,0xb0,0x0a,0xac,0x46,0x00,0x00,0x34,0x84,0x18,0xd0,0x24,0x03,0x00,0x01, ++0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0x00,0x00,0x00, ++0x08,0x00,0x0b,0xf9,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x14,0x10, ++0x24,0x02,0xff,0xff,0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01, ++0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a, ++0x34,0x42,0x04,0x10,0x8c,0x47,0x00,0x00,0x3c,0x05,0x00,0xc0,0x24,0x03,0x00,0x03, ++0x00,0xe5,0x10,0x24,0x00,0x02,0x25,0x82,0x10,0x83,0x00,0x0d,0x3c,0x02,0xff,0x3f, ++0x34,0x42,0xff,0xff,0x00,0xe2,0x10,0x24,0x00,0x45,0x38,0x25,0x3c,0x04,0xb0,0x0a, ++0x3c,0x01,0xb0,0x0a,0xac,0x27,0x04,0x10,0x34,0x84,0x14,0x10,0x24,0x03,0x00,0x01, ++0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0x00,0x00,0x00, ++0x3c,0x03,0xb0,0x0a,0x34,0x63,0x14,0x58,0x24,0x02,0xff,0xff,0xac,0x62,0x00,0x00, ++0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x04,0x58, ++0x8c,0x69,0x00,0x00,0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,0x01,0x22,0x48,0x24, ++0x3c,0x04,0xb0,0x0a,0xac,0x69,0x00,0x00,0x34,0x84,0x14,0x58,0x24,0x03,0x00,0x01, ++0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x24,0x02,0xff,0x80, ++0x08,0x00,0x0d,0x39,0x00,0xc2,0x10,0x24,0x34,0x63,0x18,0xa0,0x24,0x02,0xff,0xff, ++0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x08,0xa0, ++0x8c,0x46,0x00,0x00,0x24,0x02,0x00,0x20,0x30,0xc8,0x00,0x7f,0x15,0x02,0xfe,0x51, ++0x24,0x02,0xff,0xff,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x14,0x58,0xac,0x62,0x00,0x00, ++0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x04,0x58,0x8c,0x49,0x00,0x00, ++0x3c,0x04,0xb0,0x0a,0x34,0x84,0x14,0x58,0x35,0x29,0x40,0x00,0xac,0x49,0x00,0x00, ++0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd, ++0x24,0x02,0xff,0xff,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x14,0xb0,0xac,0x62,0x00,0x00, ++0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x04,0xb0,0x8c,0x47,0x00,0x00, ++0x3c,0x03,0xb0,0x0a,0x34,0x63,0x14,0xb8,0x3c,0x05,0xb0,0x0a,0x24,0x02,0xff,0xff, ++0xac,0x62,0x00,0x00,0x34,0xa5,0x14,0xb8,0x00,0x07,0x1e,0x02,0x24,0x04,0x00,0x01, ++0x8c,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x44,0xff,0xfd,0x3c,0x02,0xb0,0x0a, ++0x34,0x42,0x04,0xb8,0x8c,0x47,0x00,0x00,0x00,0x03,0x1a,0x00,0x30,0xe2,0x00,0xff, ++0x00,0x62,0x18,0x25,0x2c,0x62,0x00,0x04,0x10,0x40,0x00,0x3a,0x2c,0x62,0x00,0x11, ++0x3c,0x03,0xb0,0x0a,0x34,0x63,0x14,0x10,0x24,0x02,0xff,0xff,0xac,0x62,0x00,0x00, ++0x00,0x60,0x20,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x34,0x42,0x04,0x10,0x8c,0x47,0x00,0x00, ++0x24,0x02,0x00,0x03,0x00,0x07,0x1d,0x82,0x30,0x64,0x00,0x03,0x10,0x82,0x00,0x1a, ++0x3c,0x02,0xff,0x3f,0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,0x3c,0x03,0xb0,0x0a, ++0x34,0x63,0x04,0x58,0x01,0x22,0x48,0x24,0x3c,0x04,0xb0,0x0a,0xac,0x69,0x00,0x00, ++0x34,0x84,0x14,0x58,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x35,0x29,0x80,0x00,0x34,0x42,0x04,0x58, ++0x3c,0x04,0xb0,0x0a,0xac,0x49,0x00,0x00,0x34,0x84,0x14,0x58,0x24,0x03,0x00,0x01, ++0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0x00,0x00,0x00, ++0x08,0x00,0x0b,0xf9,0x00,0x00,0x00,0x00,0x34,0x42,0xff,0xff,0x3c,0x03,0x00,0x80, ++0x00,0xe2,0x10,0x24,0x00,0x43,0x38,0x25,0x3c,0x03,0xb0,0x0a,0x3c,0x01,0xb0,0x0a, ++0xac,0x27,0x04,0x10,0x34,0x63,0x14,0x10,0x24,0x04,0x00,0x01,0x8c,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x44,0xff,0xfd,0x3c,0x02,0xff,0xff,0x08,0x00,0x0d,0xef, ++0x34,0x42,0x3f,0xff,0x14,0x40,0xff,0xd8,0x3c,0x02,0xff,0xff,0x3c,0x03,0xb0,0x0a, ++0x34,0x63,0x14,0x10,0x24,0x02,0xff,0xff,0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21, ++0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd, ++0x3c,0x02,0xb0,0x0a,0x34,0x42,0x04,0x10,0x8c,0x47,0x00,0x00,0x3c,0x05,0x00,0xc0, ++0x24,0x03,0x00,0x02,0x00,0xe5,0x10,0x24,0x00,0x02,0x25,0x82,0x14,0x83,0xff,0xc6, ++0x3c,0x02,0xff,0xff,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,0x00,0xe2,0x10,0x24, ++0x00,0x45,0x38,0x25,0x3c,0x03,0xb0,0x0a,0x3c,0x01,0xb0,0x0a,0xac,0x27,0x04,0x10, ++0x34,0x63,0x14,0x10,0x24,0x04,0x00,0x01,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x44,0xff,0xfd,0x3c,0x02,0xff,0xff,0x08,0x00,0x0d,0xef,0x34,0x42,0x3f,0xff, ++0x10,0x82,0x00,0x03,0x3c,0x03,0xb0,0x0a,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x34,0x63,0x1a,0x00,0x24,0x02,0xff,0xff,0xac,0x62,0x00,0x00,0x00,0x60,0x20,0x21, ++0xa7,0x80,0xc5,0x40,0xa7,0x80,0xc5,0x42,0xa7,0x80,0xc5,0x44,0xa7,0x80,0xc5,0x46, ++0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x0a,0x34,0x63,0x0a,0x00,0x8c,0x66,0x00,0x00, ++0x3c,0x02,0x08,0x00,0x3c,0x04,0xb0,0x0a,0x00,0xc2,0x10,0x25,0xac,0x62,0x00,0x00, ++0x34,0x84,0x1a,0x00,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x3c,0x02,0xf7,0xff,0x3c,0x03,0xb0,0x0a,0x34,0x42,0xff,0xff, ++0x34,0x63,0x0a,0x00,0x00,0xc2,0x10,0x24,0x3c,0x04,0xb0,0x0a,0xac,0x62,0x00,0x00, ++0x34,0x84,0x1a,0x00,0x24,0x03,0x00,0x01,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x43,0xff,0xfd,0x00,0x00,0x00,0x00,0x08,0x00,0x0e,0x3a,0x00,0x00,0x00,0x00, ++0x30,0x83,0x00,0x03,0x00,0x04,0x20,0x40,0x00,0x83,0x20,0x23,0x3c,0x02,0xb0,0x0a, ++0x00,0x82,0x20,0x21,0xac,0x85,0x00,0x00,0x00,0x00,0x18,0x21,0x24,0x63,0x00,0x01, ++0x2c,0x62,0x27,0x10,0x14,0x40,0xff,0xfe,0x24,0x63,0x00,0x01,0x03,0xe0,0x00,0x08, ++0x24,0x63,0xff,0xff,0x30,0x86,0x00,0x03,0x00,0x04,0x28,0x40,0x3c,0x03,0xb0,0x0a, ++0x00,0xa6,0x10,0x23,0x00,0x43,0x10,0x21,0x24,0x04,0xff,0xff,0xac,0x44,0x10,0x00, ++0x00,0x00,0x18,0x21,0x24,0x63,0x00,0x01,0x2c,0x62,0x27,0x10,0x14,0x40,0xff,0xfe, ++0x24,0x63,0x00,0x01,0x24,0x63,0xff,0xff,0x00,0xa6,0x18,0x23,0x3c,0x02,0xb0,0x0a, ++0x00,0x62,0x18,0x21,0x8c,0x62,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x3c,0x05,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x3a,0x10,0x24,0x03,0x00,0x01, ++0x34,0xa5,0x00,0x20,0x3c,0x06,0xb0,0x03,0xac,0xa2,0x00,0x00,0x34,0xc6,0x01,0x04, ++0xa0,0x83,0x00,0x48,0xa0,0x80,0x00,0x04,0xa0,0x80,0x00,0x05,0xa0,0x80,0x00,0x06, ++0xa0,0x80,0x00,0x07,0xa0,0x80,0x00,0x08,0xa0,0x80,0x00,0x09,0xa0,0x80,0x00,0x0a, ++0xa0,0x80,0x00,0x11,0xa0,0x80,0x00,0x13,0xa0,0x80,0x00,0x49,0x94,0xc2,0x00,0x00, ++0xac,0x80,0x00,0x00,0xac,0x80,0x00,0x24,0x00,0x02,0x14,0x00,0x00,0x02,0x14,0x03, ++0x30,0x43,0x00,0xff,0x30,0x42,0xff,0x00,0xa4,0x83,0x00,0x46,0xa4,0x82,0x00,0x44, ++0xac,0x80,0x00,0x28,0xac,0x80,0x00,0x2c,0xac,0x80,0x00,0x30,0xac,0x80,0x00,0x34, ++0xac,0x80,0x00,0x38,0xac,0x80,0x00,0x3c,0x03,0xe0,0x00,0x08,0xac,0x80,0x00,0x40, ++0x84,0x83,0x00,0x0c,0x3c,0x07,0xb0,0x03,0x34,0xe7,0x00,0x20,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x99,0x44,0x00,0x43,0x10,0x21, ++0x8c,0x48,0x00,0x18,0x3c,0x02,0x80,0x00,0x24,0x42,0x3a,0xa0,0xac,0xe2,0x00,0x00, ++0x8d,0x03,0x00,0x08,0x80,0x82,0x00,0x13,0x00,0x05,0x2c,0x00,0x00,0x03,0x1e,0x02, ++0x00,0x02,0x12,0x00,0x30,0x63,0x00,0x7e,0x00,0x62,0x18,0x21,0x00,0x65,0x18,0x21, ++0x3c,0x02,0xc0,0x00,0x3c,0x05,0xb0,0x05,0x34,0x42,0x04,0x00,0x24,0x63,0x00,0x01, ++0x3c,0x07,0xb0,0x05,0x3c,0x08,0xb0,0x05,0x34,0xa5,0x04,0x20,0xac,0xa3,0x00,0x00, ++0x00,0xc2,0x30,0x21,0x34,0xe7,0x04,0x24,0x35,0x08,0x02,0x28,0x24,0x02,0x00,0x01, ++0x24,0x03,0x00,0x20,0xac,0xe6,0x00,0x00,0xac,0x82,0x00,0x3c,0x03,0xe0,0x00,0x08, ++0xa1,0x03,0x00,0x00,0x27,0xbd,0xff,0xb0,0x00,0x07,0x60,0x80,0x27,0x82,0xbd,0x40, ++0xaf,0xb7,0x00,0x44,0xaf,0xb6,0x00,0x40,0xaf,0xb5,0x00,0x3c,0xaf,0xb3,0x00,0x34, ++0xaf,0xbf,0x00,0x4c,0xaf,0xbe,0x00,0x48,0xaf,0xb4,0x00,0x38,0xaf,0xb2,0x00,0x30, ++0xaf,0xb1,0x00,0x2c,0xaf,0xb0,0x00,0x28,0x01,0x82,0x10,0x21,0x8c,0x43,0x00,0x00, ++0x00,0xe0,0x70,0x21,0x3c,0x02,0x80,0x00,0x94,0x71,0x00,0x14,0x3c,0x07,0xb0,0x03, ++0x34,0xe7,0x00,0x20,0x24,0x42,0x3b,0x34,0x3c,0x03,0xb0,0x05,0xac,0xe2,0x00,0x00, ++0x34,0x63,0x01,0x28,0x90,0x67,0x00,0x00,0x00,0x11,0xa8,0xc0,0x02,0xb1,0x18,0x21, ++0x27,0x82,0x99,0x44,0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,0x00,0x05,0x2c,0x00, ++0x00,0x07,0x3e,0x00,0x28,0xc2,0x00,0x03,0x00,0xc0,0x98,0x21,0xaf,0xa4,0x00,0x50, ++0x00,0x05,0xb4,0x03,0x8c,0x68,0x00,0x18,0x02,0xa0,0x58,0x21,0x10,0x40,0x01,0x70, ++0x00,0x07,0xbe,0x03,0x00,0xd7,0x10,0x07,0x30,0x57,0x00,0x01,0x01,0x71,0x10,0x21, ++0x27,0x83,0x99,0x48,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x80,0x4d,0x00,0x06, ++0x8d,0x03,0x00,0x00,0x8d,0x02,0x00,0x04,0x8d,0x0a,0x00,0x08,0x8d,0x03,0x00,0x0c, ++0xaf,0xa2,0x00,0x1c,0x11,0xa0,0x01,0x60,0xaf,0xa3,0x00,0x18,0x27,0x82,0xbd,0x40, ++0x01,0x82,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x83,0x00,0x16, ++0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x04,0x14,0x60,0x00,0x14,0x00,0x00,0xa0,0x21, ++0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x46,0x90,0x43,0x00,0x00,0x2a,0x64,0x00,0x04, ++0x10,0x80,0x01,0x43,0x30,0x65,0x00,0x01,0x8f,0xa3,0x00,0x50,0x00,0x00,0x00,0x00, ++0x90,0x62,0x00,0x09,0x00,0x00,0x00,0x00,0x12,0x62,0x00,0x02,0x00,0x00,0x00,0x00, ++0x00,0x00,0x28,0x21,0x14,0xa0,0x00,0x03,0x00,0x00,0x38,0x21,0x12,0xe0,0x00,0x03, ++0x38,0xf4,0x00,0x01,0x24,0x07,0x00,0x01,0x38,0xf4,0x00,0x01,0x01,0x71,0x10,0x21, ++0x00,0x02,0x30,0x80,0x27,0x83,0x99,0x50,0x00,0xc3,0x48,0x21,0x91,0x25,0x00,0x00, ++0x8f,0xa3,0x00,0x1c,0x00,0x00,0x00,0x00,0x00,0x03,0x11,0xc3,0x2c,0xa3,0x00,0x04, ++0x30,0x42,0x00,0x01,0x00,0x03,0xa0,0x0b,0x12,0x80,0x00,0xc7,0xaf,0xa2,0x00,0x20, ++0x93,0x90,0xc5,0x2a,0x00,0x0a,0x16,0x42,0x30,0x52,0x00,0x3f,0x2e,0x06,0x00,0x0c, ++0x10,0xc0,0x00,0xaf,0x00,0xa0,0x20,0x21,0x2c,0xa2,0x00,0x10,0x14,0x40,0x00,0x04, ++0x00,0x90,0x10,0x2b,0x30,0xa2,0x00,0x07,0x24,0x44,0x00,0x04,0x00,0x90,0x10,0x2b, ++0x10,0x40,0x00,0x0b,0x01,0x71,0x10,0x21,0x27,0x85,0xc4,0x5c,0x00,0x10,0x10,0x40, ++0x00,0x50,0x10,0x21,0x00,0x45,0x10,0x21,0x90,0x50,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x90,0x18,0x2b,0x14,0x60,0xff,0xfa,0x00,0x10,0x10,0x40,0x01,0x71,0x10,0x21, ++0x00,0x02,0x10,0x80,0x27,0x83,0x99,0x48,0x00,0x43,0x10,0x21,0x31,0xa4,0x00,0x01, ++0x10,0x80,0x00,0x94,0xa0,0x50,0x00,0x07,0x24,0x16,0x00,0x0e,0x24,0x11,0x01,0x06, ++0x27,0x82,0xbd,0x40,0x01,0x82,0x10,0x21,0x8c,0x43,0x00,0x00,0x24,0x1e,0x00,0x01, ++0x00,0x11,0xa8,0xc0,0x90,0x62,0x00,0x16,0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x04, ++0xa0,0x62,0x00,0x16,0x8f,0xa5,0x00,0x1c,0x00,0x10,0x32,0x00,0x00,0x05,0x13,0x43, ++0x30,0x47,0x00,0x01,0x8f,0xa2,0x00,0x18,0x8f,0xa5,0x00,0x20,0x00,0x02,0x22,0x02, ++0x00,0x12,0x10,0x40,0x00,0x05,0x19,0xc0,0x30,0x84,0x07,0xff,0x00,0x47,0x10,0x21, ++0x00,0x1e,0x2a,0x80,0x00,0x43,0x10,0x21,0x00,0x04,0x24,0x80,0x02,0x25,0x28,0x21, ++0x00,0xa4,0x28,0x21,0x00,0x46,0x10,0x21,0x00,0x16,0x1c,0x00,0x3c,0x04,0xc0,0x00, ++0x00,0x43,0x30,0x21,0x16,0x60,0x00,0x2b,0x00,0xa4,0x28,0x21,0x3c,0x02,0xb0,0x05, ++0x34,0x42,0x04,0x00,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00, ++0x34,0x63,0x04,0x04,0x34,0x84,0x02,0x28,0x24,0x02,0x00,0x01,0xac,0x65,0x00,0x00, ++0xa0,0x82,0x00,0x00,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x46,0x90,0x44,0x00,0x00, ++0x8f,0xa2,0x00,0x50,0x30,0x86,0x00,0x01,0x90,0x43,0x00,0x09,0x00,0x00,0x00,0x00, ++0x02,0x63,0x18,0x26,0x00,0x03,0x30,0x0b,0x14,0xc0,0x00,0x03,0x00,0x00,0x28,0x21, ++0x12,0xe0,0x00,0x03,0x02,0xb1,0x10,0x21,0x24,0x05,0x00,0x01,0x02,0xb1,0x10,0x21, ++0x27,0x83,0x99,0x48,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x84,0x48,0x00,0x04, ++0x00,0xa0,0x30,0x21,0x00,0xe0,0x20,0x21,0x02,0x60,0x28,0x21,0x02,0x80,0x38,0x21, ++0x0c,0x00,0x00,0x70,0xaf,0xa8,0x00,0x10,0x7b,0xbe,0x02,0x7c,0x7b,0xb6,0x02,0x3c, ++0x7b,0xb4,0x01,0xfc,0x7b,0xb2,0x01,0xbc,0x7b,0xb0,0x01,0x7c,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x50,0x24,0x02,0x00,0x01,0x12,0x62,0x00,0x3d,0x3c,0x02,0xb0,0x05, ++0x24,0x02,0x00,0x02,0x12,0x62,0x00,0x31,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x03, ++0x12,0x62,0x00,0x25,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x10,0x12,0x62,0x00,0x19, ++0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x11,0x12,0x62,0x00,0x0d,0x3c,0x02,0xb0,0x05, ++0x24,0x02,0x00,0x12,0x16,0x62,0xff,0xcf,0x3c,0x02,0xb0,0x05,0x3c,0x03,0xb0,0x05, ++0x34,0x42,0x04,0x20,0x3c,0x04,0xb0,0x05,0x34,0x63,0x04,0x24,0xac,0x46,0x00,0x00, ++0x34,0x84,0x02,0x28,0xac,0x65,0x00,0x00,0x08,0x00,0x0f,0x74,0x24,0x02,0x00,0x20, ++0x34,0x42,0x04,0x40,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00, ++0x34,0x63,0x04,0x44,0x34,0x84,0x02,0x28,0x24,0x02,0x00,0x40,0x08,0x00,0x0f,0x74, ++0xac,0x65,0x00,0x00,0x34,0x42,0x04,0x28,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05, ++0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x2c,0x34,0x84,0x02,0x28,0x24,0x02,0xff,0x80, ++0x08,0x00,0x0f,0x74,0xac,0x65,0x00,0x00,0x34,0x42,0x04,0x18,0x3c,0x03,0xb0,0x05, ++0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x1c,0x34,0x84,0x02,0x28, ++0x24,0x02,0x00,0x08,0x08,0x00,0x0f,0x74,0xac,0x65,0x00,0x00,0x34,0x42,0x04,0x10, ++0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x14, ++0x34,0x84,0x02,0x28,0x24,0x02,0x00,0x04,0x08,0x00,0x0f,0x74,0xac,0x65,0x00,0x00, ++0x34,0x42,0x04,0x08,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00, ++0x34,0x63,0x04,0x0c,0x34,0x84,0x02,0x28,0x24,0x02,0x00,0x02,0x08,0x00,0x0f,0x74, ++0xac,0x65,0x00,0x00,0x24,0x16,0x00,0x14,0x08,0x00,0x0f,0x4c,0x24,0x11,0x01,0x02, ++0x30,0xa2,0x00,0x07,0x24,0x44,0x00,0x0c,0x00,0x90,0x18,0x2b,0x10,0x60,0x00,0x0c, ++0x26,0x02,0x00,0x04,0x27,0x85,0xc4,0x5c,0x00,0x10,0x10,0x40,0x00,0x50,0x10,0x21, ++0x00,0x45,0x10,0x21,0x90,0x50,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x18,0x2b, ++0x14,0x60,0xff,0xfa,0x00,0x10,0x10,0x40,0x2e,0x06,0x00,0x0c,0x26,0x02,0x00,0x04, ++0x08,0x00,0x0f,0x43,0x00,0x46,0x80,0x0a,0x27,0x82,0xbd,0x40,0x01,0x82,0x20,0x21, ++0x8c,0x87,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0xe2,0x00,0x19,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x07,0x00,0x00,0x00,0x00,0x27,0x82,0x99,0x60,0x00,0xc2,0x10,0x21, ++0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x12,0x00,0x00,0x00,0x00, ++0x90,0xe3,0x00,0x16,0x27,0x82,0x99,0x48,0x00,0xc2,0x10,0x21,0x34,0x63,0x00,0x20, ++0x90,0x50,0x00,0x07,0xa0,0xe3,0x00,0x16,0x8c,0x84,0x00,0x00,0x00,0x0a,0x16,0x42, ++0x30,0x52,0x00,0x3f,0x90,0x83,0x00,0x16,0x24,0x16,0x00,0x18,0x24,0x11,0x01,0x03, ++0x30,0x63,0x00,0xfb,0x24,0x1e,0x00,0x01,0x24,0x15,0x08,0x18,0x08,0x00,0x0f,0x55, ++0xa0,0x83,0x00,0x16,0x8d,0x02,0x00,0x04,0x00,0x0a,0x1c,0x42,0x30,0x42,0x00,0x10, ++0x14,0x40,0x00,0x15,0x30,0x72,0x00,0x3f,0x81,0x22,0x00,0x05,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x11,0x30,0x72,0x00,0x3e,0x27,0x83,0x99,0x58,0x00,0xc3,0x18,0x21, ++0x80,0x64,0x00,0x00,0x27,0x83,0xbe,0xb8,0x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23, ++0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21, ++0x90,0x44,0x00,0x05,0x90,0x43,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x64,0x18,0x24, ++0x30,0x63,0x00,0x01,0x02,0x43,0x90,0x25,0x27,0x85,0xbd,0x40,0x01,0x85,0x28,0x21, ++0x8c,0xa6,0x00,0x00,0x01,0x71,0x10,0x21,0x27,0x83,0x99,0x50,0x90,0xc4,0x00,0x16, ++0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x30,0x84,0x00,0xdf,0x90,0x50,0x00,0x00, ++0xa0,0xc4,0x00,0x16,0x8c,0xa3,0x00,0x00,0x2d,0xc4,0x00,0x02,0x80,0xde,0x00,0x12, ++0x90,0x62,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfb,0x14,0x80,0x00,0x06, ++0xa0,0x62,0x00,0x16,0x24,0x02,0x00,0x06,0x11,0xc2,0x00,0x03,0x24,0x02,0x00,0x04, ++0x15,0xc2,0xff,0x14,0x00,0x00,0x00,0x00,0x32,0x42,0x00,0x02,0x2e,0x03,0x00,0x0c, ++0x14,0x60,0x00,0x0d,0x00,0x02,0x20,0x2b,0x32,0x02,0x00,0x0f,0x34,0x42,0x00,0x10, ++0x00,0x04,0x19,0x00,0x00,0x43,0x18,0x21,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xb8, ++0x00,0x00,0x20,0x21,0x02,0x00,0x28,0x21,0x0c,0x00,0x01,0xfb,0xa0,0x43,0x00,0x00, ++0x08,0x00,0x0f,0x55,0x00,0x00,0x00,0x00,0x08,0x00,0x10,0x4a,0x32,0x03,0x00,0xff, ++0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x42,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0x0f,0x14,0x40,0xfe,0xbf,0x00,0x00,0x00,0x00,0x8f,0xa3,0x00,0x50, ++0x00,0x00,0x00,0x00,0x90,0x62,0x00,0x09,0x00,0x00,0x00,0x00,0x02,0x62,0x10,0x26, ++0x08,0x00,0x0f,0x19,0x00,0x02,0x28,0x0b,0x08,0x00,0x0f,0x1f,0x00,0x00,0xa0,0x21, ++0x24,0x02,0x00,0x10,0x10,0xc2,0x00,0x08,0x24,0x02,0x00,0x11,0x10,0xc2,0xfe,0x8e, ++0x00,0x07,0x17,0x83,0x24,0x02,0x00,0x12,0x14,0xc2,0xfe,0x8c,0x00,0x07,0x17,0x43, ++0x08,0x00,0x0e,0xf7,0x30,0x57,0x00,0x01,0x08,0x00,0x0e,0xf7,0x00,0x07,0xbf,0xc2, ++0x00,0x04,0x10,0x40,0x27,0x83,0x86,0x30,0x00,0x43,0x10,0x21,0x00,0x80,0x40,0x21, ++0x94,0x44,0x00,0x00,0x2d,0x07,0x00,0x04,0x24,0xc2,0x00,0x03,0x00,0x47,0x30,0x0a, ++0x00,0x86,0x00,0x18,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20, ++0x24,0x42,0x41,0xc0,0xac,0x62,0x00,0x00,0x2d,0x06,0x00,0x10,0x00,0x00,0x20,0x12, ++0x00,0x04,0x22,0x42,0x24,0x84,0x00,0x01,0x24,0x83,0x00,0xc0,0x10,0xe0,0x00,0x0b, ++0x24,0x82,0x00,0x60,0x00,0x40,0x20,0x21,0x00,0x65,0x20,0x0a,0x3c,0x03,0xb0,0x03, ++0x34,0x63,0x01,0x00,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01, ++0x00,0x44,0x20,0x04,0x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x24,0x85,0x00,0x28, ++0x24,0x83,0x00,0x24,0x31,0x02,0x00,0x08,0x14,0xc0,0xff,0xf4,0x24,0x84,0x00,0x14, ++0x00,0x60,0x20,0x21,0x08,0x00,0x10,0x87,0x00,0xa2,0x20,0x0b,0x27,0xbd,0xff,0xe0, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0xaf,0xb0,0x00,0x10,0x24,0x42,0x42,0x5c, ++0x00,0x80,0x80,0x21,0x34,0x63,0x00,0x20,0x3c,0x04,0xb0,0x03,0xaf,0xb2,0x00,0x18, ++0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x1c,0x83,0xb1,0x00,0x33,0x83,0xa8,0x00,0x37, ++0x34,0x84,0x01,0x10,0xac,0x62,0x00,0x00,0x2e,0x02,0x00,0x10,0x00,0xe0,0x90,0x21, ++0x8c,0x87,0x00,0x00,0x14,0x40,0x00,0x0c,0x2e,0x02,0x00,0x0c,0x3c,0x02,0x00,0x0f, ++0x34,0x42,0xf0,0x00,0x00,0xe2,0x10,0x24,0x14,0x40,0x00,0x37,0x32,0x02,0x00,0x08, ++0x32,0x02,0x00,0x07,0x27,0x83,0x86,0xe0,0x00,0x43,0x10,0x21,0x90,0x50,0x00,0x00, ++0x00,0x00,0x00,0x00,0x2e,0x02,0x00,0x0c,0x14,0x40,0x00,0x03,0x02,0x00,0x20,0x21, ++0x32,0x02,0x00,0x0f,0x24,0x44,0x00,0x0c,0x00,0x87,0x10,0x06,0x30,0x42,0x00,0x01, ++0x14,0x40,0x00,0x07,0x2c,0x82,0x00,0x0c,0x00,0x04,0x10,0x80,0x27,0x83,0xbd,0x90, ++0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x82,0x00,0x0c, ++0x14,0x40,0x00,0x05,0x00,0x05,0x10,0x40,0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00, ++0x00,0x82,0x10,0x21,0x24,0x44,0x00,0x04,0x15,0x00,0x00,0x02,0x24,0x06,0x00,0x20, ++0x24,0x06,0x00,0x0e,0x0c,0x00,0x10,0x70,0x00,0x00,0x00,0x00,0x00,0x40,0x30,0x21, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x00,0x90,0x43,0x00,0x00,0x2e,0x04,0x00,0x04, ++0x24,0x02,0x00,0x10,0x24,0x05,0x00,0x0a,0x00,0x44,0x28,0x0a,0x30,0x63,0x00,0x01, ++0x14,0x60,0x00,0x02,0x00,0x05,0x10,0x40,0x00,0xa0,0x10,0x21,0x30,0x45,0x00,0xff, ++0x00,0xc5,0x10,0x21,0x24,0x46,0x00,0x46,0x02,0x26,0x18,0x04,0xa6,0x43,0x00,0x00, ++0x8f,0xbf,0x00,0x1c,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x00,0xc0,0x10,0x21, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x10,0x40,0xff,0xcf,0x2e,0x02,0x00,0x0c, ++0x32,0x02,0x00,0x07,0x27,0x83,0x86,0xd8,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x00, ++0x08,0x00,0x10,0xb5,0x02,0x04,0x80,0x23,0x27,0xbd,0xff,0xb8,0x00,0x05,0x38,0x80, ++0x27,0x82,0xbd,0x40,0xaf,0xbe,0x00,0x40,0xaf,0xb6,0x00,0x38,0xaf,0xb3,0x00,0x2c, ++0xaf,0xbf,0x00,0x44,0xaf,0xb7,0x00,0x3c,0xaf,0xb5,0x00,0x34,0xaf,0xb4,0x00,0x30, ++0xaf,0xb2,0x00,0x28,0xaf,0xb1,0x00,0x24,0xaf,0xb0,0x00,0x20,0x00,0xe2,0x38,0x21, ++0x8c,0xe6,0x00,0x00,0xaf,0xa5,0x00,0x4c,0x3c,0x02,0x80,0x00,0x3c,0x05,0xb0,0x03, ++0x34,0xa5,0x00,0x20,0x24,0x42,0x43,0xb8,0x24,0x03,0x00,0x01,0xac,0xa2,0x00,0x00, ++0xa0,0xc3,0x00,0x12,0x8c,0xe5,0x00,0x00,0x94,0xc3,0x00,0x06,0x90,0xa2,0x00,0x16, ++0xa4,0xc3,0x00,0x14,0x27,0x83,0x99,0x40,0x34,0x42,0x00,0x08,0xa0,0xa2,0x00,0x16, ++0x8c,0xe8,0x00,0x00,0xaf,0xa4,0x00,0x48,0x27,0x82,0x99,0x44,0x95,0x11,0x00,0x14, ++0x00,0x00,0x00,0x00,0x00,0x11,0x98,0xc0,0x02,0x71,0x20,0x21,0x00,0x04,0x20,0x80, ++0x00,0x82,0x10,0x21,0x8c,0x52,0x00,0x18,0x00,0x83,0x18,0x21,0x84,0x75,0x00,0x06, ++0x8e,0x45,0x00,0x08,0x8e,0x46,0x00,0x04,0x8e,0x47,0x00,0x04,0x00,0x05,0x1c,0x82, ++0x00,0x06,0x31,0x42,0x27,0x82,0x99,0x50,0x30,0x63,0x00,0x01,0x30,0xc6,0x00,0x01, ++0x00,0x82,0x20,0x21,0xa5,0x15,0x00,0x1a,0x00,0x05,0x14,0x42,0xaf,0xa3,0x00,0x18, ++0xaf,0xa6,0x00,0x1c,0x30,0xe7,0x00,0x10,0x30,0x56,0x00,0x01,0x80,0x97,0x00,0x06, ++0x14,0xe0,0x00,0x47,0x00,0x05,0xf7,0xc2,0x80,0x82,0x00,0x05,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x44,0x02,0x71,0x10,0x21,0x93,0x90,0xc5,0x29,0x00,0x00,0x00,0x00, ++0x2e,0x02,0x00,0x0c,0x14,0x40,0x00,0x06,0x02,0x00,0x20,0x21,0x00,0x16,0x10,0x40, ++0x00,0x43,0x10,0x21,0x00,0x02,0x11,0x00,0x02,0x02,0x10,0x21,0x24,0x44,0x00,0x04, ++0x02,0x71,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x99,0x50,0x00,0x43,0x10,0x21, ++0x00,0x80,0x80,0x21,0xa0,0x44,0x00,0x03,0xa0,0x44,0x00,0x00,0x02,0x00,0x20,0x21, ++0x02,0xc0,0x28,0x21,0x0c,0x00,0x10,0x70,0x02,0xa0,0x30,0x21,0x02,0x71,0x18,0x21, ++0x00,0x03,0x88,0x80,0x00,0x40,0xa0,0x21,0x27,0x82,0x99,0x60,0x02,0x22,0x10,0x21, ++0x8c,0x44,0x00,0x00,0x26,0xe3,0x00,0x02,0x00,0x03,0x17,0xc2,0x00,0x62,0x18,0x21, ++0x00,0x04,0x25,0xc2,0x00,0x03,0x18,0x43,0x30,0x84,0x00,0x01,0x00,0x03,0x18,0x40, ++0x03,0xc4,0x20,0x24,0x14,0x80,0x00,0x15,0x02,0x43,0x38,0x21,0x3c,0x08,0xb0,0x03, ++0x35,0x08,0x00,0x28,0x8d,0x03,0x00,0x00,0x8f,0xa6,0x00,0x4c,0x8f,0xa4,0x00,0x48, ++0x27,0x82,0x99,0x48,0x02,0x22,0x10,0x21,0x24,0x63,0x00,0x01,0x02,0xa0,0x28,0x21, ++0xa4,0x54,0x00,0x04,0x00,0xc0,0x38,0x21,0x0c,0x00,0x0e,0xcd,0xad,0x03,0x00,0x00, ++0x7b,0xbe,0x02,0x3c,0x7b,0xb6,0x01,0xfc,0x7b,0xb4,0x01,0xbc,0x7b,0xb2,0x01,0x7c, ++0x7b,0xb0,0x01,0x3c,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x48,0x8f,0xa2,0x00,0x1c, ++0x8f,0xa6,0x00,0x18,0x02,0x00,0x20,0x21,0x02,0xc0,0x28,0x21,0xaf,0xa2,0x00,0x10, ++0x0c,0x00,0x10,0x97,0xaf,0xa0,0x00,0x14,0x08,0x00,0x11,0x53,0x02,0x82,0xa0,0x21, ++0x02,0x71,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x99,0x50,0x00,0x43,0x10,0x21, ++0x90,0x50,0x00,0x00,0x08,0x00,0x11,0x3f,0xa0,0x50,0x00,0x03,0x27,0xbd,0xff,0xb8, ++0xaf,0xb1,0x00,0x24,0x8f,0xb1,0x00,0x5c,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00, ++0x34,0x63,0x00,0x20,0x24,0x42,0x45,0xdc,0xaf,0xbe,0x00,0x40,0xaf,0xb7,0x00,0x3c, ++0xaf,0xb6,0x00,0x38,0xaf,0xb5,0x00,0x34,0xaf,0xb4,0x00,0x30,0xaf,0xa5,0x00,0x4c, ++0x8f,0xb5,0x00,0x58,0xaf,0xbf,0x00,0x44,0xaf,0xb3,0x00,0x2c,0xaf,0xb2,0x00,0x28, ++0xaf,0xb0,0x00,0x20,0x00,0xe0,0xb0,0x21,0xac,0x62,0x00,0x00,0x00,0x80,0xf0,0x21, ++0x00,0x00,0xb8,0x21,0x16,0x20,0x00,0x2b,0x00,0x00,0xa0,0x21,0x27,0x85,0xbd,0x40, ++0x00,0x07,0x10,0x80,0x00,0x45,0x10,0x21,0x8c,0x53,0x00,0x00,0x00,0x15,0x18,0x80, ++0x00,0x65,0x18,0x21,0x92,0x62,0x00,0x16,0x8c,0x72,0x00,0x00,0x30,0x42,0x00,0x03, ++0x14,0x40,0x00,0x2d,0x00,0x00,0x00,0x00,0x92,0x42,0x00,0x16,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0x03,0x14,0x40,0x00,0x28,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x34, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x18,0x02,0x20,0x10,0x21,0x8c,0x82,0x00,0x38, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x14,0x02,0x20,0x10,0x21,0x8c,0x82,0x00,0x3c, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x0f,0x3c,0x03,0xb0,0x09,0x3c,0x05,0xb0,0x05, ++0x34,0x63,0x01,0x44,0x34,0xa5,0x02,0x52,0x94,0x66,0x00,0x00,0x90,0xa2,0x00,0x00, ++0x8f,0xa3,0x00,0x4c,0x00,0x00,0x00,0x00,0x00,0x62,0x10,0x06,0x30,0x42,0x00,0x01, ++0x10,0x40,0x00,0x04,0x30,0xc6,0xff,0xff,0x2c,0xc2,0x00,0x41,0x10,0x40,0x00,0x09, ++0x24,0x05,0x00,0x14,0x02,0x20,0x10,0x21,0x7b,0xbe,0x02,0x3c,0x7b,0xb6,0x01,0xfc, ++0x7b,0xb4,0x01,0xbc,0x7b,0xb2,0x01,0x7c,0x7b,0xb0,0x01,0x3c,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x48,0x0c,0x00,0x0e,0xa8,0x24,0x06,0x01,0x07,0x24,0x02,0x00,0x01, ++0x08,0x00,0x11,0xb9,0xa3,0xc2,0x00,0x11,0x10,0xc0,0x00,0x1c,0x24,0x02,0x00,0x01, ++0x10,0xc2,0x00,0x17,0x00,0xc0,0x88,0x21,0x96,0x54,0x00,0x1a,0x02,0xa0,0xb8,0x21, ++0x12,0x20,0xff,0xed,0x02,0x20,0x10,0x21,0x27,0x83,0xbd,0x40,0x00,0x17,0x10,0x80, ++0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x28, ++0x80,0x86,0x00,0x12,0x8c,0x62,0x00,0x00,0x00,0x14,0x2c,0x00,0x00,0x05,0x2c,0x03, ++0x00,0x46,0x10,0x21,0x8f,0xa6,0x00,0x4c,0x02,0xe0,0x38,0x21,0x03,0xc0,0x20,0x21, ++0x0c,0x00,0x0e,0xcd,0xac,0x62,0x00,0x00,0x08,0x00,0x11,0xb9,0xaf,0xd1,0x00,0x40, ++0x96,0x74,0x00,0x1a,0x08,0x00,0x11,0xcc,0x02,0xc0,0xb8,0x21,0x3c,0x02,0xb0,0x03, ++0x34,0x42,0x01,0x08,0x8c,0x50,0x00,0x00,0x02,0x60,0x20,0x21,0x0c,0x00,0x26,0x64, ++0x02,0x00,0x28,0x21,0x30,0x42,0x00,0xff,0x02,0x00,0x28,0x21,0x02,0x40,0x20,0x21, ++0x0c,0x00,0x26,0x64,0xaf,0xa2,0x00,0x18,0x8f,0xa4,0x00,0x18,0x00,0x00,0x00,0x00, ++0x10,0x80,0x00,0xed,0x30,0x50,0x00,0xff,0x12,0x00,0x00,0x18,0x24,0x11,0x00,0x01, ++0x96,0x63,0x00,0x14,0x96,0x44,0x00,0x14,0x27,0x85,0x99,0x40,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x00,0x04,0x18,0xc0, ++0x8c,0x46,0x00,0x08,0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x65,0x18,0x21, ++0x00,0x06,0x17,0x02,0x24,0x04,0x00,0xff,0x8c,0x63,0x00,0x08,0x10,0x44,0x00,0xd6, ++0x00,0x03,0x17,0x02,0x10,0x44,0x00,0xd5,0x3c,0x02,0x80,0x00,0x00,0x66,0x18,0x2b, ++0x24,0x11,0x00,0x02,0x24,0x02,0x00,0x01,0x00,0x43,0x88,0x0a,0x24,0x02,0x00,0x01, ++0x12,0x22,0x00,0x5a,0x24,0x02,0x00,0x02,0x16,0x22,0xff,0xbd,0x00,0x00,0x00,0x00, ++0x96,0x49,0x00,0x14,0x27,0x82,0x99,0x44,0x02,0xa0,0xb8,0x21,0x00,0x09,0x50,0xc0, ++0x01,0x49,0x18,0x21,0x00,0x03,0x40,0x80,0x01,0x02,0x10,0x21,0x8c,0x43,0x00,0x18, ++0x00,0x00,0x00,0x00,0x8c,0x65,0x00,0x08,0x8c,0x62,0x00,0x0c,0x8c,0x62,0x00,0x04, ++0x00,0x05,0x24,0x42,0x00,0x05,0x1c,0x82,0x30,0x42,0x00,0x10,0x30,0x66,0x00,0x01, ++0x14,0x40,0x00,0x41,0x30,0x87,0x00,0x01,0x27,0x82,0x99,0x58,0x01,0x02,0x10,0x21, ++0x80,0x44,0x00,0x00,0x27,0x82,0xbe,0xb8,0x00,0x04,0x19,0x00,0x00,0x64,0x18,0x23, ++0x00,0x03,0x18,0x80,0x00,0x64,0x18,0x23,0x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21, ++0x90,0x45,0x00,0x05,0x27,0x84,0xbd,0xe0,0x00,0x64,0x18,0x21,0x90,0x63,0x00,0x00, ++0x10,0xa0,0x00,0x2b,0x2c,0x64,0x00,0x0c,0x14,0x80,0x00,0x04,0x00,0x60,0x10,0x21, ++0x00,0x06,0x11,0x00,0x00,0x62,0x10,0x21,0x24,0x42,0x00,0x24,0x3c,0x01,0xb0,0x03, ++0xa0,0x22,0x00,0xb9,0x14,0x80,0x00,0x06,0x00,0x60,0x28,0x21,0x00,0x07,0x10,0x40, ++0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0x62,0x10,0x21,0x24,0x45,0x00,0x04, ++0x01,0x49,0x10,0x21,0x27,0x83,0x99,0x50,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21, ++0x00,0xa0,0x18,0x21,0xa0,0x45,0x00,0x03,0xa0,0x45,0x00,0x00,0x24,0x02,0x00,0x08, ++0x12,0x02,0x00,0x0b,0x24,0x02,0x00,0x01,0x00,0x60,0x28,0x21,0x02,0x40,0x20,0x21, ++0x0c,0x00,0x26,0xe0,0xaf,0xa2,0x00,0x10,0x30,0x54,0xff,0xff,0x92,0x42,0x00,0x16, ++0x00,0x00,0x00,0x00,0x02,0x02,0x10,0x25,0x08,0x00,0x11,0xcc,0xa2,0x42,0x00,0x16, ++0x00,0x60,0x28,0x21,0x02,0x40,0x20,0x21,0x0c,0x00,0x26,0x91,0xaf,0xa0,0x00,0x10, ++0x08,0x00,0x12,0x4f,0x30,0x54,0xff,0xff,0x08,0x00,0x12,0x37,0x00,0x60,0x10,0x21, ++0x14,0x80,0xff,0xfd,0x00,0x00,0x00,0x00,0x00,0x06,0x11,0x00,0x00,0x62,0x10,0x21, ++0x08,0x00,0x12,0x37,0x24,0x42,0x00,0x04,0x27,0x82,0x99,0x50,0x01,0x02,0x10,0x21, ++0x90,0x43,0x00,0x00,0x08,0x00,0x12,0x47,0xa0,0x43,0x00,0x03,0x96,0x69,0x00,0x14, ++0x02,0xc0,0xb8,0x21,0x24,0x0b,0x00,0x01,0x00,0x09,0x10,0xc0,0x00,0x49,0x18,0x21, ++0x00,0x03,0x40,0x80,0x00,0x40,0x50,0x21,0x27,0x82,0x99,0x44,0x01,0x02,0x10,0x21, ++0x8c,0x43,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x65,0x00,0x08,0x8c,0x62,0x00,0x0c, ++0x8c,0x62,0x00,0x04,0x00,0x05,0x24,0x42,0x00,0x05,0x1c,0x82,0x30,0x42,0x00,0x10, ++0x30,0x66,0x00,0x01,0x10,0x40,0x00,0x0d,0x30,0x87,0x00,0x01,0x27,0x82,0x99,0x58, ++0x01,0x02,0x10,0x21,0x80,0x43,0x00,0x00,0x00,0x00,0x58,0x21,0x00,0x03,0x11,0x00, ++0x00,0x43,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x23,0x00,0x02,0x10,0x80, ++0x27,0x83,0xbe,0xb0,0x00,0x43,0x10,0x21,0xa0,0x40,0x00,0x04,0x11,0x60,0x00,0x4f, ++0x00,0x00,0x00,0x00,0x01,0x49,0x10,0x21,0x00,0x02,0x20,0x80,0x27,0x85,0x99,0x50, ++0x00,0x85,0x10,0x21,0x80,0x43,0x00,0x05,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x42, ++0x01,0x49,0x10,0x21,0x27,0x82,0x99,0x58,0x00,0x82,0x10,0x21,0x80,0x44,0x00,0x00, ++0x27,0x82,0xbe,0xb8,0x00,0x04,0x19,0x00,0x00,0x64,0x18,0x23,0x00,0x03,0x18,0x80, ++0x00,0x64,0x18,0x23,0x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21,0x90,0x45,0x00,0x05, ++0x27,0x84,0xbd,0xe0,0x00,0x64,0x18,0x21,0x90,0x63,0x00,0x00,0x10,0xa0,0x00,0x2c, ++0x2c,0x64,0x00,0x0c,0x14,0x80,0x00,0x04,0x00,0x60,0x10,0x21,0x00,0x06,0x11,0x00, ++0x00,0x62,0x10,0x21,0x24,0x42,0x00,0x24,0x3c,0x01,0xb0,0x03,0xa0,0x22,0x00,0xb9, ++0x14,0x80,0x00,0x06,0x00,0x60,0x28,0x21,0x00,0x07,0x10,0x40,0x00,0x46,0x10,0x21, ++0x00,0x02,0x11,0x00,0x00,0x62,0x10,0x21,0x24,0x45,0x00,0x04,0x01,0x49,0x10,0x21, ++0x27,0x83,0x99,0x50,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0xa0,0x18,0x21, ++0xa0,0x45,0x00,0x03,0xa0,0x45,0x00,0x00,0x8f,0xa4,0x00,0x18,0x24,0x02,0x00,0x08, ++0x10,0x82,0x00,0x0c,0x00,0x60,0x28,0x21,0x24,0x02,0x00,0x01,0x02,0x60,0x20,0x21, ++0x0c,0x00,0x26,0xe0,0xaf,0xa2,0x00,0x10,0x8f,0xa3,0x00,0x18,0x30,0x54,0xff,0xff, ++0x92,0x62,0x00,0x16,0x00,0x00,0x00,0x00,0x00,0x62,0x10,0x25,0x08,0x00,0x11,0xcc, ++0xa2,0x62,0x00,0x16,0x02,0x60,0x20,0x21,0x0c,0x00,0x26,0x91,0xaf,0xa0,0x00,0x10, ++0x08,0x00,0x12,0xbe,0x00,0x00,0x00,0x00,0x08,0x00,0x12,0xa6,0x00,0x60,0x10,0x21, ++0x14,0x80,0xff,0xfd,0x00,0x00,0x00,0x00,0x00,0x06,0x11,0x00,0x00,0x62,0x10,0x21, ++0x08,0x00,0x12,0xa6,0x24,0x42,0x00,0x04,0x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21, ++0x90,0x43,0x00,0x00,0x08,0x00,0x12,0xb6,0xa0,0x43,0x00,0x03,0x27,0x85,0x99,0x50, ++0x08,0x00,0x12,0xd2,0x01,0x49,0x10,0x21,0x3c,0x02,0x80,0x00,0x00,0x62,0x18,0x26, ++0x08,0x00,0x12,0x07,0x00,0xc2,0x30,0x26,0x12,0x00,0xff,0x2d,0x24,0x02,0x00,0x01, ++0x08,0x00,0x12,0x0c,0x24,0x11,0x00,0x02,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00, ++0x27,0xbd,0xff,0xd0,0x24,0x42,0x4b,0x88,0x34,0x63,0x00,0x20,0x3c,0x05,0xb0,0x05, ++0xaf,0xb3,0x00,0x24,0xaf,0xb2,0x00,0x20,0xaf,0xb1,0x00,0x1c,0xaf,0xbf,0x00,0x28, ++0xaf,0xb0,0x00,0x18,0xac,0x62,0x00,0x00,0x34,0xa5,0x02,0x42,0x90,0xa2,0x00,0x00, ++0x00,0x80,0x90,0x21,0x24,0x11,0x00,0x10,0x30,0x53,0x00,0xff,0x24,0x02,0x00,0x10, ++0x12,0x22,0x00,0xcf,0x00,0x00,0x18,0x21,0x24,0x02,0x00,0x11,0x12,0x22,0x00,0xc1, ++0x24,0x02,0x00,0x12,0x12,0x22,0x00,0xb4,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0xad, ++0xae,0x43,0x00,0x40,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,0x8c,0x44,0x00,0x00, ++0x3c,0x03,0x00,0x02,0x34,0x63,0x00,0xff,0x00,0x83,0x80,0x24,0x00,0x10,0x14,0x43, ++0x10,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x8e,0x42,0x00,0x34,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x92,0x00,0x00,0x00,0x00,0x93,0x83,0x94,0x51,0x00,0x00,0x00,0x00, ++0x30,0x62,0x00,0x02,0x10,0x40,0x00,0x04,0x32,0x10,0x00,0xff,0x00,0x10,0x11,0xc3, ++0x14,0x40,0x00,0x86,0x00,0x00,0x00,0x00,0x16,0x00,0x00,0x15,0x02,0x00,0x10,0x21, ++0x26,0x22,0x00,0x01,0x30,0x51,0x00,0xff,0x2e,0x23,0x00,0x13,0x14,0x60,0xff,0xdb, ++0x24,0x03,0x00,0x02,0x12,0x63,0x00,0x73,0x24,0x02,0x00,0x05,0x2a,0x62,0x00,0x03, ++0x10,0x40,0x00,0x58,0x24,0x02,0x00,0x04,0x24,0x02,0x00,0x01,0x12,0x62,0x00,0x4b, ++0x02,0x40,0x20,0x21,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,0x8c,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x70,0x00,0xff,0x12,0x00,0x00,0x06,0x02,0x00,0x10,0x21, ++0x8f,0xbf,0x00,0x28,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x30,0x92,0x46,0x00,0x04,0x8e,0x43,0x00,0x24,0x24,0x02,0x00,0x07, ++0x02,0x40,0x20,0x21,0x00,0x00,0x28,0x21,0x24,0x07,0x00,0x06,0xaf,0xa2,0x00,0x10, ++0x0c,0x00,0x11,0x77,0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x24,0x3c,0x02,0xb0,0x05, ++0x8c,0x42,0x02,0x2c,0x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,0x16,0x00,0xff,0xec, ++0x02,0x00,0x10,0x21,0x92,0x46,0x00,0x05,0x8e,0x43,0x00,0x28,0x24,0x02,0x00,0x05, ++0x02,0x40,0x20,0x21,0x24,0x05,0x00,0x01,0x24,0x07,0x00,0x04,0xaf,0xa2,0x00,0x10, ++0x0c,0x00,0x11,0x77,0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x28,0x3c,0x02,0xb0,0x05, ++0x8c,0x42,0x02,0x2c,0x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,0x16,0x00,0xff,0xdc, ++0x02,0x00,0x10,0x21,0x92,0x46,0x00,0x06,0x8e,0x43,0x00,0x2c,0x24,0x02,0x00,0x03, ++0x02,0x40,0x20,0x21,0x24,0x05,0x00,0x02,0x00,0x00,0x38,0x21,0xaf,0xa2,0x00,0x10, ++0x0c,0x00,0x11,0x77,0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x2c,0x3c,0x02,0xb0,0x05, ++0x8c,0x42,0x02,0x2c,0x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,0x16,0x00,0xff,0xcc, ++0x02,0x00,0x10,0x21,0x92,0x46,0x00,0x07,0x8e,0x43,0x00,0x30,0x24,0x02,0x00,0x02, ++0x02,0x40,0x20,0x21,0x24,0x05,0x00,0x03,0x24,0x07,0x00,0x01,0xaf,0xa2,0x00,0x10, ++0x0c,0x00,0x11,0x77,0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x30,0x3c,0x02,0xb0,0x05, ++0x8c,0x42,0x02,0x2c,0x08,0x00,0x13,0x28,0x30,0x42,0x00,0xff,0x92,0x46,0x00,0x04, ++0x8e,0x43,0x00,0x24,0x24,0x02,0x00,0x07,0x00,0x00,0x28,0x21,0x24,0x07,0x00,0x06, ++0xaf,0xa2,0x00,0x10,0x0c,0x00,0x11,0x77,0xaf,0xa3,0x00,0x14,0x08,0x00,0x13,0x21, ++0xae,0x42,0x00,0x24,0x12,0x62,0x00,0x0d,0x24,0x02,0x00,0x03,0x24,0x02,0x00,0x08, ++0x16,0x62,0xff,0xa8,0x02,0x40,0x20,0x21,0x92,0x46,0x00,0x07,0x8e,0x42,0x00,0x30, ++0x24,0x05,0x00,0x03,0x24,0x07,0x00,0x01,0xaf,0xa3,0x00,0x10,0x0c,0x00,0x11,0x77, ++0xaf,0xa2,0x00,0x14,0x08,0x00,0x13,0x21,0xae,0x42,0x00,0x30,0x92,0x46,0x00,0x06, ++0x8e,0x43,0x00,0x2c,0x02,0x40,0x20,0x21,0x24,0x05,0x00,0x02,0x00,0x00,0x38,0x21, ++0xaf,0xa2,0x00,0x10,0x0c,0x00,0x11,0x77,0xaf,0xa3,0x00,0x14,0x08,0x00,0x13,0x21, ++0xae,0x42,0x00,0x2c,0x92,0x46,0x00,0x05,0x8e,0x43,0x00,0x28,0x02,0x40,0x20,0x21, ++0x24,0x05,0x00,0x01,0x24,0x07,0x00,0x04,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x11,0x77, ++0xaf,0xa3,0x00,0x14,0x08,0x00,0x13,0x21,0xae,0x42,0x00,0x28,0x0c,0x00,0x01,0x57, ++0x24,0x04,0x00,0x01,0x08,0x00,0x13,0x12,0x00,0x00,0x00,0x00,0x8f,0x84,0xbd,0x80, ++0xae,0x40,0x00,0x34,0x94,0x85,0x00,0x14,0x0c,0x00,0x22,0xe1,0x00,0x00,0x00,0x00, ++0x93,0x83,0x94,0x51,0x00,0x00,0x00,0x00,0x30,0x62,0x00,0x02,0x10,0x40,0xff,0x69, ++0x00,0x00,0x00,0x00,0x0c,0x00,0x01,0x57,0x00,0x00,0x20,0x21,0x08,0x00,0x13,0x0a, ++0x00,0x00,0x00,0x00,0x02,0x40,0x20,0x21,0x0c,0x00,0x10,0xee,0x02,0x20,0x28,0x21, ++0x08,0x00,0x12,0xfe,0x3c,0x02,0xb0,0x05,0x8e,0x42,0x00,0x3c,0x00,0x00,0x00,0x00, ++0x14,0x40,0xff,0x4a,0x00,0x00,0x00,0x00,0x8f,0x82,0xbd,0x88,0x00,0x00,0x00,0x00, ++0x90,0x42,0x00,0x0a,0x00,0x00,0x00,0x00,0x00,0x02,0x18,0x2b,0x08,0x00,0x12,0xfb, ++0xae,0x43,0x00,0x3c,0x8e,0x42,0x00,0x38,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x3d, ++0x24,0x02,0x00,0x12,0x8f,0x82,0xbd,0x84,0x00,0x00,0x00,0x00,0x90,0x42,0x00,0x0a, ++0x00,0x00,0x00,0x00,0x00,0x02,0x18,0x2b,0x08,0x00,0x12,0xfb,0xae,0x43,0x00,0x38, ++0x8e,0x42,0x00,0x34,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x30,0x24,0x02,0x00,0x11, ++0x8f,0x82,0xbd,0x80,0x00,0x00,0x00,0x00,0x90,0x42,0x00,0x0a,0x00,0x00,0x00,0x00, ++0x00,0x02,0x18,0x2b,0x08,0x00,0x12,0xfb,0xae,0x43,0x00,0x34,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xe0,0x34,0x63,0x00,0x20,0x24,0x42,0x4f,0x3c, ++0x3c,0x08,0xb0,0x03,0xaf,0xb1,0x00,0x14,0xac,0x62,0x00,0x00,0x35,0x08,0x01,0x00, ++0xaf,0xbf,0x00,0x18,0xaf,0xb0,0x00,0x10,0x91,0x03,0x00,0x00,0x00,0xa0,0x48,0x21, ++0x24,0x11,0x00,0x0a,0x2c,0xa5,0x00,0x04,0x24,0x02,0x00,0x10,0x00,0x45,0x88,0x0a, ++0x30,0x63,0x00,0x01,0x00,0xc0,0x28,0x21,0x14,0x60,0x00,0x02,0x00,0x11,0x40,0x40, ++0x02,0x20,0x40,0x21,0x84,0x83,0x00,0x0c,0x31,0x11,0x00,0xff,0x01,0x20,0x20,0x21, ++0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x99,0x48, ++0x00,0x43,0x10,0x21,0x84,0x43,0x00,0x04,0x24,0x06,0x00,0x0e,0x10,0xe0,0x00,0x06, ++0x02,0x23,0x80,0x21,0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x0c,0x00,0x10,0x70,0x00,0x00,0x00,0x00, ++0x02,0x11,0x18,0x21,0x08,0x00,0x13,0xf1,0x00,0x62,0x80,0x21,0x27,0xbd,0xff,0xd0, ++0xaf,0xbf,0x00,0x28,0xaf,0xb4,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18, ++0xaf,0xb5,0x00,0x24,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x84,0x82,0x00,0x0c, ++0x3c,0x06,0xb0,0x03,0x34,0xc6,0x00,0x20,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21, ++0x00,0x03,0x18,0x80,0x27,0x82,0x99,0x44,0x00,0x62,0x10,0x21,0x8c,0x55,0x00,0x18, ++0x3c,0x02,0x80,0x00,0x24,0x42,0x4f,0xec,0xac,0xc2,0x00,0x00,0x8e,0xb0,0x00,0x08, ++0x27,0x82,0x99,0x48,0x00,0x62,0x18,0x21,0x90,0x71,0x00,0x07,0x00,0x10,0x86,0x43, ++0x32,0x10,0x00,0x01,0x00,0xa0,0x38,0x21,0x02,0x00,0x30,0x21,0x00,0xa0,0x98,0x21, ++0x02,0x20,0x28,0x21,0x0c,0x00,0x13,0xcf,0x00,0x80,0x90,0x21,0x02,0x20,0x20,0x21, ++0x02,0x00,0x28,0x21,0x24,0x06,0x00,0x14,0x0c,0x00,0x10,0x70,0x00,0x40,0xa0,0x21, ++0x86,0x43,0x00,0x0c,0x3c,0x09,0xb0,0x09,0x3c,0x08,0xb0,0x09,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x99,0x50,0x00,0x43,0x10,0x21, ++0x80,0x43,0x00,0x06,0x3c,0x07,0xb0,0x09,0x3c,0x05,0xb0,0x09,0x28,0x62,0x00,0x00, ++0x24,0x64,0x00,0x03,0x00,0x82,0x18,0x0b,0x00,0x03,0x18,0x83,0x3c,0x02,0xb0,0x09, ++0x00,0x03,0x18,0x80,0x34,0x42,0x01,0x02,0x35,0x29,0x01,0x10,0x35,0x08,0x01,0x14, ++0x34,0xe7,0x01,0x20,0x34,0xa5,0x01,0x24,0xa4,0x54,0x00,0x00,0x12,0x60,0x00,0x11, ++0x02,0xa3,0xa8,0x21,0x8e,0xa2,0x00,0x0c,0x8e,0xa3,0x00,0x08,0x00,0x02,0x14,0x00, ++0x00,0x03,0x1c,0x02,0x00,0x43,0x10,0x21,0xad,0x22,0x00,0x00,0x8e,0xa3,0x00,0x0c, ++0x00,0x00,0x00,0x00,0x00,0x03,0x1c,0x02,0xa5,0x03,0x00,0x00,0x8f,0xbf,0x00,0x28, ++0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x30,0x8e,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,0xad,0x22,0x00,0x00, ++0x8e,0xa4,0x00,0x08,0x00,0x00,0x00,0x00,0xa5,0x04,0x00,0x00,0x7a,0xa2,0x00,0x7c, ++0x00,0x00,0x00,0x00,0x00,0x03,0x1c,0x00,0x00,0x02,0x14,0x02,0x00,0x62,0x18,0x21, ++0xac,0xe3,0x00,0x00,0x8e,0xa2,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x02,0x14,0x02, ++0x08,0x00,0x14,0x43,0xa4,0xa2,0x00,0x00,0x27,0xbd,0xff,0xe0,0xaf,0xb2,0x00,0x18, ++0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x1c,0xaf,0xb1,0x00,0x14,0x84,0x82,0x00,0x0c, ++0x00,0x80,0x90,0x21,0x3c,0x05,0xb0,0x03,0x00,0x02,0x20,0xc0,0x00,0x82,0x20,0x21, ++0x00,0x04,0x20,0x80,0x27,0x82,0x99,0x44,0x00,0x82,0x10,0x21,0x8c,0x51,0x00,0x18, ++0x3c,0x02,0x80,0x00,0x34,0xa5,0x00,0x20,0x24,0x42,0x51,0x68,0x27,0x83,0x99,0x48, ++0xac,0xa2,0x00,0x00,0x00,0x83,0x20,0x21,0x3c,0x02,0xb0,0x03,0x90,0x86,0x00,0x07, ++0x34,0x42,0x01,0x00,0x8e,0x23,0x00,0x08,0x90,0x44,0x00,0x00,0x2c,0xc5,0x00,0x04, ++0x24,0x02,0x00,0x10,0x24,0x10,0x00,0x0a,0x00,0x45,0x80,0x0a,0x00,0x03,0x1e,0x43, ++0x30,0x84,0x00,0x01,0x30,0x65,0x00,0x01,0x14,0x80,0x00,0x02,0x00,0x10,0x10,0x40, ++0x02,0x00,0x10,0x21,0x00,0xc0,0x20,0x21,0x24,0x06,0x00,0x20,0x0c,0x00,0x10,0x70, ++0x30,0x50,0x00,0xff,0x86,0x44,0x00,0x0c,0x27,0x85,0x99,0x50,0x3c,0x06,0xb0,0x09, ++0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x65,0x18,0x21, ++0x80,0x64,0x00,0x06,0x00,0x50,0x10,0x21,0x34,0xc6,0x01,0x02,0x24,0x85,0x00,0x03, ++0x28,0x83,0x00,0x00,0x00,0xa3,0x20,0x0b,0x00,0x04,0x20,0x83,0x00,0x04,0x20,0x80, ++0xa4,0xc2,0x00,0x00,0x02,0x24,0x20,0x21,0x8c,0x83,0x00,0x04,0x3c,0x02,0xb0,0x09, ++0x34,0x42,0x01,0x10,0xac,0x43,0x00,0x00,0x8c,0x86,0x00,0x08,0x3c,0x02,0xb0,0x09, ++0x34,0x42,0x01,0x14,0xa4,0x46,0x00,0x00,0x8c,0x85,0x00,0x0c,0x8c,0x82,0x00,0x08, ++0x3c,0x06,0xb0,0x09,0x00,0x05,0x2c,0x00,0x00,0x02,0x14,0x02,0x00,0xa2,0x28,0x21, ++0x34,0xc6,0x01,0x20,0xac,0xc5,0x00,0x00,0x8c,0x83,0x00,0x0c,0x3c,0x05,0xb0,0x09, ++0x34,0xa5,0x01,0x24,0x00,0x03,0x1c,0x02,0xa4,0xa3,0x00,0x00,0x92,0x42,0x00,0x0a, ++0x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x30,0x00,0x02,0x13,0x00,0x24,0x42,0x00,0x04, ++0x30,0x42,0xff,0xff,0xa4,0x62,0x00,0x00,0x86,0x44,0x00,0x0c,0x27,0x83,0x99,0x58, ++0x8f,0xbf,0x00,0x1c,0x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x00,0x02,0x10,0x80, ++0x00,0x43,0x10,0x21,0x94,0x44,0x00,0x02,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc, ++0x3c,0x05,0xb0,0x09,0x34,0xa5,0x01,0x32,0xa4,0xa4,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x20,0x27,0xbd,0xff,0xe0,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00, ++0xaf,0xb0,0x00,0x10,0x34,0x42,0x00,0x20,0x00,0xa0,0x80,0x21,0x24,0x63,0x52,0xf4, ++0x00,0x05,0x2c,0x43,0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x18,0xac,0x43,0x00,0x00, ++0x10,0xa0,0x00,0x05,0x00,0x80,0x88,0x21,0x8c,0x82,0x00,0x34,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0xaf,0x00,0x00,0x00,0x00,0x32,0x10,0x00,0xff,0x12,0x00,0x00,0x47, ++0x00,0x00,0x10,0x21,0x24,0x02,0x00,0x08,0x12,0x02,0x00,0x9c,0x2a,0x02,0x00,0x09, ++0x10,0x40,0x00,0x84,0x24,0x02,0x00,0x40,0x24,0x04,0x00,0x02,0x12,0x04,0x00,0x74, ++0x2a,0x02,0x00,0x03,0x10,0x40,0x00,0x64,0x24,0x02,0x00,0x04,0x24,0x02,0x00,0x01, ++0x12,0x02,0x00,0x55,0x00,0x00,0x00,0x00,0x82,0x22,0x00,0x11,0x92,0x27,0x00,0x11, ++0x10,0x40,0x00,0x4e,0x00,0x00,0x00,0x00,0x92,0x26,0x00,0x0a,0x24,0x02,0x00,0x12, ++0x10,0x46,0x00,0x09,0x30,0xc2,0x00,0xff,0x27,0x83,0xbd,0x40,0x00,0x02,0x10,0x80, ++0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x94,0x83,0x00,0x14, ++0x00,0x00,0x00,0x00,0xa6,0x23,0x00,0x0c,0x3c,0x02,0xb0,0x09,0x34,0x42,0x00,0x40, ++0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x03,0xa2,0x23,0x00,0x10, ++0x14,0x60,0x00,0x2b,0x30,0x65,0x00,0x01,0x30,0xc2,0x00,0xff,0x27,0x83,0xbd,0x40, ++0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x82,0x23,0x00,0x12, ++0x90,0x82,0x00,0x16,0x00,0x00,0x00,0x00,0x00,0x02,0x11,0x42,0x30,0x42,0x00,0x01, ++0x00,0x62,0x18,0x21,0x00,0x03,0x26,0x00,0x14,0x80,0x00,0x18,0xa2,0x23,0x00,0x12, ++0x00,0x07,0x16,0x00,0x14,0x40,0x00,0x11,0x24,0x02,0x00,0x01,0x96,0x23,0x00,0x0c, ++0x27,0x84,0x99,0x50,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80, ++0x00,0x44,0x10,0x21,0x80,0x45,0x00,0x06,0x00,0x03,0x1a,0x00,0x3c,0x02,0xb0,0x00, ++0x00,0x65,0x18,0x21,0x00,0x62,0x18,0x21,0x90,0x64,0x00,0x00,0x90,0x62,0x00,0x04, ++0xa2,0x20,0x00,0x15,0xa3,0x80,0x95,0x14,0x24,0x02,0x00,0x01,0x8f,0xbf,0x00,0x18, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x0c,0x00,0x14,0x5a, ++0x02,0x20,0x20,0x21,0x92,0x27,0x00,0x11,0x08,0x00,0x15,0x05,0x00,0x07,0x16,0x00, ++0x0c,0x00,0x13,0xfb,0x02,0x20,0x20,0x21,0x86,0x23,0x00,0x0c,0x27,0x84,0x99,0x48, ++0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x44,0x20,0x21, ++0x90,0x85,0x00,0x07,0x27,0x83,0x99,0x50,0x00,0x43,0x10,0x21,0xa2,0x25,0x00,0x13, ++0x90,0x83,0x00,0x07,0x08,0x00,0x15,0x1d,0xa0,0x43,0x00,0x02,0x92,0x26,0x00,0x0a, ++0x08,0x00,0x14,0xe6,0x30,0xc2,0x00,0xff,0x8e,0x22,0x00,0x24,0x00,0x00,0x00,0x00, ++0x10,0x50,0x00,0x07,0xa2,0x20,0x00,0x08,0x24,0x02,0x00,0x07,0xa2,0x22,0x00,0x0a, ++0x92,0x22,0x00,0x27,0xae,0x20,0x00,0x24,0x08,0x00,0x14,0xde,0xa2,0x22,0x00,0x04, ++0x08,0x00,0x15,0x37,0x24,0x02,0x00,0x06,0x16,0x02,0xff,0x9f,0x24,0x02,0x00,0x01, ++0x8e,0x23,0x00,0x2c,0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x07,0xa2,0x24,0x00,0x08, ++0x24,0x02,0x00,0x03,0xa2,0x22,0x00,0x0a,0x92,0x22,0x00,0x2f,0xae,0x20,0x00,0x2c, ++0x08,0x00,0x14,0xde,0xa2,0x22,0x00,0x06,0x08,0x00,0x15,0x46,0xa2,0x20,0x00,0x0a, ++0x8e,0x22,0x00,0x28,0x24,0x03,0x00,0x01,0x24,0x04,0x00,0x01,0x10,0x44,0x00,0x07, ++0xa2,0x23,0x00,0x08,0x24,0x02,0x00,0x05,0xa2,0x22,0x00,0x0a,0x92,0x22,0x00,0x2b, ++0xae,0x20,0x00,0x28,0x08,0x00,0x14,0xde,0xa2,0x22,0x00,0x05,0x08,0x00,0x15,0x52, ++0x24,0x02,0x00,0x04,0x12,0x02,0x00,0x10,0x2a,0x02,0x00,0x41,0x10,0x40,0x00,0x08, ++0x24,0x02,0x00,0x80,0x24,0x02,0x00,0x20,0x16,0x02,0xff,0x7f,0x24,0x02,0x00,0x12, ++0xa2,0x22,0x00,0x0a,0xa2,0x22,0x00,0x08,0x08,0x00,0x14,0xde,0xae,0x20,0x00,0x3c, ++0x16,0x02,0xff,0x79,0x24,0x02,0x00,0x10,0xa2,0x22,0x00,0x0a,0xa2,0x22,0x00,0x08, ++0x08,0x00,0x14,0xde,0xae,0x20,0x00,0x34,0x24,0x02,0x00,0x11,0xa2,0x22,0x00,0x0a, ++0xa2,0x22,0x00,0x08,0x08,0x00,0x14,0xde,0xae,0x20,0x00,0x38,0x8e,0x24,0x00,0x30, ++0x24,0x02,0x00,0x03,0x24,0x03,0x00,0x01,0x10,0x83,0x00,0x07,0xa2,0x22,0x00,0x08, ++0x24,0x02,0x00,0x02,0xa2,0x22,0x00,0x0a,0x92,0x22,0x00,0x33,0xae,0x20,0x00,0x30, ++0x08,0x00,0x14,0xde,0xa2,0x22,0x00,0x07,0x08,0x00,0x15,0x76,0xa2,0x24,0x00,0x0a, ++0x8f,0x84,0xbd,0x80,0xae,0x20,0x00,0x34,0x94,0x85,0x00,0x14,0x0c,0x00,0x22,0xe1, ++0x32,0x10,0x00,0xff,0x08,0x00,0x14,0xcf,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x24,0x42,0x56,0x0c,0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00, ++0x80,0xa2,0x00,0x15,0x3c,0x06,0xb0,0x05,0x10,0x40,0x00,0x0a,0x34,0xc6,0x02,0x54, ++0x83,0x83,0x95,0x14,0x00,0x00,0x00,0x00,0xac,0x83,0x00,0x24,0x8c,0xc2,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x02,0x17,0x42,0x30,0x42,0x00,0x01,0x03,0xe0,0x00,0x08, ++0xac,0x82,0x00,0x28,0x8c,0x82,0x00,0x2c,0x3c,0x06,0xb0,0x05,0x34,0xc6,0x04,0x50, ++0x00,0x02,0x18,0x43,0x30,0x63,0x00,0x01,0x10,0x40,0x00,0x04,0x30,0x45,0x00,0x01, ++0xac,0x83,0x00,0x28,0x03,0xe0,0x00,0x08,0xac,0x85,0x00,0x24,0x90,0xc2,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0x30,0x43,0x00,0x02,0x30,0x42,0x00,0x01, ++0xac,0x83,0x00,0x28,0x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x24,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xd8,0x34,0x63,0x00,0x20,0x24,0x42,0x56,0x9c, ++0xac,0x62,0x00,0x00,0xaf,0xb1,0x00,0x1c,0xaf,0xbf,0x00,0x20,0xaf,0xb0,0x00,0x18, ++0x90,0xa6,0x00,0x0a,0x27,0x83,0xbd,0x40,0x00,0xa0,0x88,0x21,0x00,0x06,0x10,0x80, ++0x00,0x43,0x10,0x21,0x8c,0x50,0x00,0x00,0x80,0xa5,0x00,0x11,0x92,0x03,0x00,0x12, ++0x10,0xa0,0x00,0x04,0xa2,0x20,0x00,0x15,0x24,0x02,0x00,0x12,0x10,0xc2,0x00,0xda, ++0x00,0x00,0x00,0x00,0x82,0x22,0x00,0x12,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x67, ++0x00,0x00,0x00,0x00,0xa2,0x20,0x00,0x12,0xa2,0x00,0x00,0x19,0x86,0x23,0x00,0x0c, ++0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80, ++0x27,0x83,0x99,0x60,0x00,0x43,0x10,0x21,0xa0,0x40,0x00,0x00,0x92,0x03,0x00,0x16, ++0x00,0x00,0x00,0x00,0x30,0x63,0x00,0xdf,0xa2,0x03,0x00,0x16,0x82,0x02,0x00,0x12, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x92,0x23,0x00,0x08, ++0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x45,0x24,0x02,0x00,0x01,0xa2,0x20,0x00,0x04, ++0x92,0x08,0x00,0x04,0x00,0x00,0x00,0x00,0x15,0x00,0x00,0x1e,0x24,0x02,0x00,0x01, ++0x92,0x07,0x00,0x0a,0xa2,0x02,0x00,0x17,0x92,0x02,0x00,0x16,0x30,0xe3,0x00,0xff, ++0x30,0x42,0x00,0xe4,0x10,0x60,0x00,0x03,0xa2,0x02,0x00,0x16,0x34,0x42,0x00,0x01, ++0xa2,0x02,0x00,0x16,0x11,0x00,0x00,0x05,0x00,0x00,0x00,0x00,0x92,0x02,0x00,0x16, ++0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02,0xa2,0x02,0x00,0x16,0x92,0x02,0x00,0x17, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x08,0x00,0x00,0x00,0x00,0x96,0x02,0x00,0x06, ++0x00,0x00,0x00,0x00,0xa6,0x02,0x00,0x14,0x8f,0xbf,0x00,0x20,0x7b,0xb0,0x00,0xfc, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x96,0x02,0x00,0x00,0x08,0x00,0x15,0xf2, ++0xa6,0x02,0x00,0x14,0x92,0x07,0x00,0x0a,0x00,0x00,0x00,0x00,0x14,0xe0,0x00,0x03, ++0x00,0x00,0x00,0x00,0x08,0x00,0x15,0xde,0xa2,0x00,0x00,0x17,0x96,0x04,0x00,0x00, ++0x96,0x05,0x00,0x06,0x27,0x86,0x99,0x40,0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21, ++0x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21,0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21, ++0x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21,0x8c,0x66,0x00,0x08,0x8c,0x45,0x00,0x08, ++0x3c,0x03,0x80,0x00,0x00,0xc3,0x20,0x24,0x10,0x80,0x00,0x08,0x00,0xa3,0x10,0x24, ++0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21,0x10,0x80,0x00,0x02,0x24,0x03,0x00,0x01, ++0x00,0xa6,0x18,0x2b,0x08,0x00,0x15,0xde,0xa2,0x03,0x00,0x17,0x10,0x40,0xff,0xfd, ++0x00,0xa6,0x18,0x2b,0x08,0x00,0x16,0x12,0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x09, ++0x24,0x02,0x00,0x02,0x10,0x62,0x00,0x05,0x24,0x02,0x00,0x03,0x14,0x62,0xff,0xb8, ++0x00,0x00,0x00,0x00,0x08,0x00,0x15,0xd8,0xa2,0x20,0x00,0x07,0x08,0x00,0x15,0xd8, ++0xa2,0x20,0x00,0x06,0x08,0x00,0x15,0xd8,0xa2,0x20,0x00,0x05,0x82,0x22,0x00,0x10, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x69,0x2c,0x62,0x00,0x02,0x10,0x40,0x00,0x49, ++0x3c,0x02,0xb0,0x09,0x92,0x25,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa6,0x00,0xff, ++0x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x3b,0x2c,0xc2,0x00,0x10,0x3c,0x04,0xb0,0x05, ++0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,0x00,0xc2,0x10,0x04, ++0x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24,0xa0,0x83,0x00,0x00,0x86,0x23,0x00,0x0c, ++0x96,0x26,0x00,0x0c,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x28,0x80, ++0x27,0x83,0x99,0x44,0x00,0xa3,0x18,0x21,0x8c,0x64,0x00,0x18,0x00,0x00,0x00,0x00, ++0x8c,0x82,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x10,0x10,0x40,0x00,0x18, ++0x24,0x07,0x00,0x01,0x93,0x82,0x94,0x51,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01, ++0x14,0x40,0x00,0x0a,0x24,0x05,0x00,0x24,0x00,0x06,0x2c,0x00,0x00,0x05,0x2c,0x03, ++0x0c,0x00,0x22,0xe1,0x02,0x00,0x20,0x21,0x92,0x02,0x00,0x16,0xa2,0x00,0x00,0x12, ++0x30,0x42,0x00,0xe7,0x08,0x00,0x15,0xcf,0xa2,0x02,0x00,0x16,0xf0,0xc5,0x00,0x06, ++0x00,0x00,0x28,0x12,0x27,0x82,0x99,0x40,0x00,0xa2,0x28,0x21,0x0c,0x00,0x01,0x49, ++0x3c,0x04,0x00,0x80,0x96,0x26,0x00,0x0c,0x08,0x00,0x16,0x4f,0x00,0x06,0x2c,0x00, ++0x27,0x83,0x99,0x50,0x27,0x82,0x99,0x58,0x00,0xa2,0x10,0x21,0x00,0xa3,0x18,0x21, ++0x90,0x44,0x00,0x00,0x90,0x65,0x00,0x05,0x93,0x82,0x80,0x10,0x00,0x00,0x30,0x21, ++0x0c,0x00,0x29,0x0b,0xaf,0xa2,0x00,0x10,0x96,0x26,0x00,0x0c,0x08,0x00,0x16,0x49, ++0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xcd,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29, ++0x90,0x83,0x00,0x00,0x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80,0x08,0x00,0x16,0x38, ++0x00,0xa2,0x10,0x07,0x86,0x26,0x00,0x0c,0x3c,0x03,0xb0,0x09,0x34,0x42,0x01,0x72, ++0x34,0x63,0x01,0x78,0x94,0x47,0x00,0x00,0x8c,0x65,0x00,0x00,0x00,0x06,0x10,0xc0, ++0x00,0x46,0x10,0x21,0x3c,0x04,0xb0,0x09,0xae,0x25,0x00,0x1c,0x34,0x84,0x01,0x7c, ++0x27,0x83,0x99,0x44,0x00,0x02,0x10,0x80,0x8c,0x85,0x00,0x00,0x00,0x43,0x10,0x21, ++0x8c,0x43,0x00,0x18,0xae,0x25,0x00,0x20,0xa6,0x27,0x00,0x18,0x8c,0x66,0x00,0x08, ++0x02,0x20,0x20,0x21,0x0c,0x00,0x16,0x9f,0x00,0x00,0x28,0x21,0x86,0x25,0x00,0x18, ++0x8e,0x26,0x00,0x1c,0x8e,0x27,0x00,0x20,0x02,0x20,0x20,0x21,0x0c,0x00,0x23,0xe3, ++0xaf,0xa2,0x00,0x10,0x08,0x00,0x15,0xcf,0xa2,0x02,0x00,0x12,0x92,0x22,0x00,0x08, ++0x08,0x00,0x15,0xcf,0xa2,0x22,0x00,0x09,0xa2,0x20,0x00,0x11,0x80,0x82,0x00,0x50, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x03,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xd0, ++0xac,0x40,0x00,0x00,0x08,0x00,0x15,0xcf,0xa0,0x80,0x00,0x50,0x94,0x8a,0x00,0x0c, ++0x24,0x03,0x00,0x24,0x00,0x80,0x70,0x21,0x3c,0x02,0x80,0x00,0x3c,0x04,0xb0,0x03, ++0x24,0x42,0x5a,0x7c,0xf1,0x43,0x00,0x06,0x34,0x84,0x00,0x20,0x00,0x00,0x18,0x12, ++0x00,0xa0,0x68,0x21,0xac,0x82,0x00,0x00,0x27,0x85,0x99,0x50,0x27,0x82,0x99,0x4f, ++0x27,0xbd,0xff,0xf8,0x00,0x62,0x60,0x21,0x00,0x65,0x58,0x21,0x00,0x00,0xc0,0x21, ++0x11,0xa0,0x00,0xcc,0x00,0x00,0x78,0x21,0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03, ++0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21, ++0x91,0x87,0x00,0x00,0x80,0x48,0x00,0x04,0x03,0xa0,0x60,0x21,0x00,0x0a,0x1c,0x00, ++0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x48,0x80, ++0x27,0x83,0x99,0x44,0xa3,0xa7,0x00,0x00,0x01,0x23,0x18,0x21,0x8c,0x64,0x00,0x18, ++0x25,0x02,0xff,0xff,0x00,0x48,0x40,0x0b,0x8c,0x83,0x00,0x04,0x2d,0x05,0x00,0x07, ++0x24,0x02,0x00,0x06,0x30,0x63,0x00,0x08,0x14,0x60,0x00,0x35,0x00,0x45,0x40,0x0a, ++0x93,0xa7,0x00,0x00,0x27,0x82,0x99,0x58,0x01,0x22,0x10,0x21,0x30,0xe3,0x00,0xf0, ++0x38,0x63,0x00,0x50,0x30,0xe5,0x00,0xff,0x00,0x05,0x20,0x2b,0x00,0x03,0x18,0x2b, ++0x00,0x64,0x18,0x24,0x90,0x49,0x00,0x00,0x10,0x60,0x00,0x16,0x30,0xe4,0x00,0x0f, ++0x24,0x02,0x00,0x04,0x10,0xa2,0x00,0x9d,0x00,0x00,0x00,0x00,0x11,0xa0,0x00,0x3a, ++0x2c,0xa2,0x00,0x0c,0x10,0x40,0x00,0x02,0x24,0x84,0x00,0x0c,0x00,0xe0,0x20,0x21, ++0x30,0x84,0x00,0xff,0x00,0x04,0x10,0x40,0x27,0x83,0xc4,0x5c,0x00,0x44,0x10,0x21, ++0x00,0x43,0x10,0x21,0x90,0x47,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0xe3,0x00,0x0c, ++0xa3,0xa7,0x00,0x00,0x10,0x60,0x00,0x02,0x24,0xe2,0x00,0x04,0x00,0xe0,0x10,0x21, ++0xa3,0xa2,0x00,0x00,0x91,0x65,0x00,0x00,0x91,0x82,0x00,0x00,0x30,0xa3,0x00,0xff, ++0x00,0x62,0x10,0x2b,0x10,0x40,0x00,0x0e,0x2c,0x62,0x00,0x0c,0x14,0x40,0x00,0x03, ++0x00,0x60,0x20,0x21,0x30,0xa2,0x00,0x0f,0x24,0x44,0x00,0x0c,0x00,0x04,0x10,0x40, ++0x00,0x44,0x20,0x21,0x27,0x83,0xc4,0x5c,0x00,0x83,0x18,0x21,0x90,0x62,0x00,0x02, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x05,0x00,0x09,0x11,0x00,0xa1,0x85,0x00,0x00, ++0x93,0xa2,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x08,0x00,0x49,0x10,0x23, ++0x00,0x02,0x10,0x80,0x00,0x49,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21, ++0x27,0x83,0xbd,0xe8,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x00,0x00,0x00,0x00,0x00, ++0x2c,0x83,0x00,0x0c,0x14,0x60,0x00,0x06,0x00,0x80,0x10,0x21,0x00,0x18,0x10,0x40, ++0x00,0x4f,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0x82,0x10,0x21,0x24,0x42,0x00,0x04, ++0x08,0x00,0x17,0x00,0xa1,0x82,0x00,0x00,0x8f,0x8d,0x87,0x70,0x00,0x00,0x00,0x00, ++0x01,0xa8,0x10,0x21,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x60,0xff,0xd1, ++0x00,0x00,0x28,0x21,0x00,0x06,0x74,0x82,0x30,0xe2,0x00,0xff,0x2c,0x42,0x00,0x0c, ++0x14,0x40,0x00,0x03,0x00,0xe0,0x10,0x21,0x30,0xe2,0x00,0x0f,0x24,0x42,0x00,0x0c, ++0x30,0x44,0x00,0xff,0xa3,0xa2,0x00,0x00,0x24,0x02,0x00,0x0c,0x10,0x82,0x00,0x0d, ++0x00,0x09,0x11,0x00,0x00,0x49,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x04,0x18,0x40, ++0x00,0x49,0x10,0x23,0x00,0x64,0x18,0x21,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21, ++0x27,0x84,0xbd,0xe8,0x00,0x44,0x10,0x21,0x90,0x47,0x00,0x00,0x00,0x00,0x00,0x00, ++0xa3,0xa7,0x00,0x00,0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x99,0x44,0x00,0x43,0x10,0x21, ++0x8c,0x44,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x83,0x00,0x04,0x00,0x00,0x00,0x00, ++0x30,0x63,0x00,0x10,0x14,0x60,0x00,0x33,0x00,0x06,0x14,0x42,0x00,0x09,0x11,0x00, ++0x00,0x49,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x49,0x10,0x23,0x27,0x83,0xbe,0xb8, ++0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x04,0x90,0x43,0x00,0x05, ++0x00,0x00,0x00,0x00,0x00,0x64,0xc0,0x24,0x93,0xa7,0x00,0x00,0x00,0x00,0x00,0x00, ++0x2c,0xe2,0x00,0x0f,0x10,0x40,0x00,0x0f,0x31,0xcf,0x00,0x01,0x00,0x0a,0x1c,0x00, ++0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80, ++0x27,0x84,0x99,0x40,0x00,0x44,0x10,0x21,0x84,0x43,0x00,0x06,0x00,0x00,0x00,0x00, ++0x28,0x63,0x06,0x41,0x14,0x60,0x00,0x04,0x30,0xe2,0x00,0xff,0x24,0x07,0x00,0x0f, ++0xa3,0xa7,0x00,0x00,0x30,0xe2,0x00,0xff,0x2c,0x42,0x00,0x0c,0x14,0x40,0x00,0x06, ++0x00,0xe0,0x10,0x21,0x00,0x18,0x10,0x40,0x00,0x4f,0x10,0x21,0x00,0x02,0x11,0x00, ++0x00,0x47,0x10,0x21,0x24,0x42,0x00,0x04,0xa3,0xa2,0x00,0x00,0x00,0x40,0x38,0x21, ++0x01,0xa8,0x10,0x21,0x90,0x43,0x00,0x00,0x24,0xa4,0x00,0x01,0x30,0x85,0xff,0xff, ++0x00,0xa3,0x18,0x2b,0x14,0x60,0xff,0xad,0x30,0xe2,0x00,0xff,0x08,0x00,0x16,0xed, ++0x00,0x00,0x00,0x00,0x08,0x00,0x17,0x4e,0x30,0x58,0x00,0x01,0x81,0xc2,0x00,0x48, ++0x00,0x00,0x00,0x00,0x10,0x40,0xff,0x73,0x00,0x00,0x00,0x00,0x08,0x00,0x16,0xdb, ++0x00,0x00,0x00,0x00,0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x80,0x48,0x00,0x05, ++0x91,0x67,0x00,0x00,0x08,0x00,0x16,0xbb,0x03,0xa0,0x58,0x21,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x5e,0x1c,0x03,0xe0,0x00,0x08, ++0xac,0x62,0x00,0x00,0x27,0xbd,0xff,0xc0,0xaf,0xb7,0x00,0x34,0xaf,0xb6,0x00,0x30, ++0xaf,0xb5,0x00,0x2c,0xaf,0xb4,0x00,0x28,0xaf,0xb3,0x00,0x24,0xaf,0xb2,0x00,0x20, ++0xaf,0xbf,0x00,0x3c,0xaf,0xbe,0x00,0x38,0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18, ++0x84,0x82,0x00,0x0c,0x27,0x93,0x99,0x44,0x3c,0x05,0xb0,0x03,0x00,0x02,0x18,0xc0, ++0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x73,0x10,0x21,0x8c,0x5e,0x00,0x18, ++0x3c,0x02,0x80,0x00,0x34,0xa5,0x00,0x20,0x24,0x42,0x5e,0x34,0xac,0xa2,0x00,0x00, ++0x8f,0xd0,0x00,0x08,0x27,0x95,0x99,0x50,0x00,0x75,0x18,0x21,0x00,0x00,0x28,0x21, ++0x02,0x00,0x30,0x21,0x90,0x71,0x00,0x00,0x0c,0x00,0x16,0x9f,0x00,0x80,0xb0,0x21, ++0x00,0x40,0x90,0x21,0x00,0x10,0x14,0x42,0x30,0x54,0x00,0x01,0x02,0x40,0x20,0x21, ++0x00,0x10,0x14,0x82,0x02,0x80,0x28,0x21,0x12,0x51,0x00,0x23,0x00,0x10,0xbf,0xc2, ++0x86,0xc3,0x00,0x0c,0x30,0x50,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21, ++0x00,0x02,0x10,0x80,0x00,0x55,0x10,0x21,0xa0,0x52,0x00,0x00,0x86,0xc3,0x00,0x0c, ++0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80, ++0x00,0x53,0x30,0x21,0x8c,0xc7,0x00,0x18,0x27,0x83,0x99,0x40,0x00,0x43,0x10,0x21, ++0x8c,0xe3,0x00,0x04,0x84,0x46,0x00,0x06,0x00,0x03,0x19,0x42,0x0c,0x00,0x10,0x70, ++0x30,0x73,0x00,0x01,0x00,0x40,0x88,0x21,0x02,0x40,0x20,0x21,0x02,0x80,0x28,0x21, ++0x16,0xe0,0x00,0x10,0x02,0x00,0x30,0x21,0x86,0xc2,0x00,0x0c,0x00,0x00,0x00,0x00, ++0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80,0x27,0x82,0x99,0x48, ++0x00,0x62,0x18,0x21,0xa4,0x71,0x00,0x04,0x7b,0xbe,0x01,0xfc,0x7b,0xb6,0x01,0xbc, ++0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x40,0x86,0xc3,0x00,0x0c,0xaf,0xb3,0x00,0x10,0xaf,0xa0,0x00,0x14, ++0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x55,0x10,0x21, ++0x80,0x47,0x00,0x06,0x00,0x00,0x00,0x00,0x24,0xe7,0x00,0x02,0x00,0x07,0x17,0xc2, ++0x00,0xe2,0x38,0x21,0x00,0x07,0x38,0x43,0x00,0x07,0x38,0x40,0x0c,0x00,0x10,0x97, ++0x03,0xc7,0x38,0x21,0x08,0x00,0x17,0xce,0x02,0x22,0x88,0x21,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xd0,0x34,0x63,0x00,0x20,0x24,0x42,0x5f,0xbc, ++0xaf,0xb2,0x00,0x20,0xac,0x62,0x00,0x00,0xaf,0xbf,0x00,0x28,0xaf,0xb3,0x00,0x24, ++0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,0x3c,0x02,0xb0,0x03,0x90,0x83,0x00,0x0a, ++0x34,0x42,0x01,0x04,0x94,0x45,0x00,0x00,0x00,0x03,0x18,0x80,0x27,0x82,0xbd,0x40, ++0x00,0x62,0x18,0x21,0x30,0xa6,0xff,0xff,0x8c,0x71,0x00,0x00,0x80,0x85,0x00,0x12, ++0x30,0xc9,0x00,0xff,0x00,0x06,0x32,0x02,0xa4,0x86,0x00,0x44,0xa4,0x89,0x00,0x46, ++0x82,0x22,0x00,0x12,0x00,0x80,0x90,0x21,0x10,0xa0,0x00,0x1b,0xa0,0x80,0x00,0x15, ++0x00,0xc5,0x10,0x2a,0x10,0x40,0x00,0x14,0x00,0x00,0x00,0x00,0xa2,0x20,0x00,0x19, ++0x84,0x83,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21, ++0x00,0x02,0x10,0x80,0x27,0x83,0x99,0x60,0x00,0x43,0x10,0x21,0xa0,0x40,0x00,0x00, ++0xa0,0x80,0x00,0x12,0x92,0x22,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xdf, ++0xa2,0x22,0x00,0x16,0x8f,0xbf,0x00,0x28,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,0x0c,0x00,0x17,0x87,0x00,0x00,0x00,0x00, ++0x08,0x00,0x18,0x1d,0x00,0x00,0x00,0x00,0x28,0x42,0x00,0x02,0x10,0x40,0x01,0x76, ++0x00,0x00,0x28,0x21,0x94,0x87,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0xe0,0x10,0x21, ++0x00,0x02,0x14,0x00,0x00,0x02,0x14,0x03,0x00,0x07,0x24,0x00,0x00,0x04,0x24,0x03, ++0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,0x00,0x04,0x28,0xc0,0x00,0xa4,0x28,0x21, ++0x27,0x82,0x99,0x60,0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,0x00,0x05,0x28,0x80, ++0x27,0x82,0x99,0x48,0x00,0xa2,0x10,0x21,0x8c,0x68,0x00,0x00,0x80,0x44,0x00,0x06, ++0x27,0x82,0x99,0x50,0x00,0x08,0x1d,0x02,0x00,0xa2,0x28,0x21,0x38,0x84,0x00,0x00, ++0x30,0x63,0x00,0x01,0x01,0x24,0x30,0x0b,0x80,0xaa,0x00,0x04,0x80,0xa9,0x00,0x05, ++0x10,0x60,0x00,0x02,0x00,0x08,0x14,0x02,0x30,0x46,0x00,0x0f,0x15,0x20,0x00,0x28, ++0x01,0x49,0x10,0x21,0x15,0x40,0x00,0x11,0x30,0xe3,0xff,0xff,0x92,0x45,0x00,0x08, ++0x00,0x00,0x00,0x00,0x30,0xa8,0x00,0xff,0x2d,0x02,0x00,0x04,0x10,0x40,0x01,0x46, ++0x2d,0x02,0x00,0x10,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00, ++0x24,0x02,0x00,0x01,0x01,0x02,0x10,0x04,0x00,0x62,0x18,0x25,0xa0,0x83,0x00,0x00, ++0x96,0x47,0x00,0x0c,0x00,0x00,0x00,0x00,0x30,0xe3,0xff,0xff,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x27,0x84,0x99,0x50,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21, ++0x80,0x45,0x00,0x06,0x00,0x03,0x1a,0x00,0x3c,0x04,0xb0,0x00,0x00,0x65,0x18,0x21, ++0x00,0x64,0x20,0x21,0x94,0x82,0x00,0x00,0x82,0x43,0x00,0x10,0x00,0x02,0x14,0x00, ++0x14,0x60,0x00,0x06,0x00,0x02,0x3c,0x03,0x30,0xe2,0x00,0x04,0x14,0x40,0x00,0x04, ++0x01,0x49,0x10,0x21,0x34,0xe2,0x08,0x00,0xa4,0x82,0x00,0x00,0x01,0x49,0x10,0x21, ++0x00,0x02,0x16,0x00,0x00,0x02,0x16,0x03,0x00,0x46,0x10,0x2a,0x10,0x40,0x00,0x7c, ++0x00,0x00,0x00,0x00,0x82,0x42,0x00,0x10,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0e, ++0x00,0x00,0x00,0x00,0x86,0x43,0x00,0x0c,0x25,0x44,0x00,0x01,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x99,0x50,0x00,0x43,0x10,0x21, ++0xa0,0x44,0x00,0x04,0x92,0x23,0x00,0x16,0x02,0x40,0x20,0x21,0x30,0x63,0x00,0xfb, ++0x08,0x00,0x18,0x22,0xa2,0x23,0x00,0x16,0x86,0x43,0x00,0x0c,0x25,0x24,0x00,0x01, ++0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x99,0x50, ++0x00,0x43,0x10,0x21,0xa0,0x44,0x00,0x05,0x86,0x45,0x00,0x0c,0x0c,0x00,0x26,0x5b, ++0x02,0x20,0x20,0x21,0x10,0x40,0x00,0x5a,0x00,0x00,0x00,0x00,0x92,0x45,0x00,0x08, ++0x00,0x00,0x00,0x00,0x30,0xa6,0x00,0xff,0x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x4c, ++0x2c,0xc2,0x00,0x10,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00, ++0x24,0x02,0x00,0x01,0x00,0xc2,0x10,0x04,0x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24, ++0xa0,0x83,0x00,0x00,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa5,0x00,0xff, ++0x14,0xa0,0x00,0x33,0x24,0x02,0x00,0x01,0xa2,0x40,0x00,0x04,0x92,0x22,0x00,0x04, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x0c,0x24,0x02,0x00,0x01,0xa2,0x22,0x00,0x17, ++0x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x04,0x00,0x00,0x00,0x00, ++0x96,0x22,0x00,0x06,0x08,0x00,0x18,0x1d,0xa6,0x22,0x00,0x14,0x96,0x22,0x00,0x00, ++0x08,0x00,0x18,0x1d,0xa6,0x22,0x00,0x14,0x92,0x22,0x00,0x0a,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x18,0xac,0xa2,0x20,0x00,0x17, ++0x96,0x24,0x00,0x00,0x96,0x25,0x00,0x06,0x27,0x86,0x99,0x40,0x00,0x04,0x18,0xc0, ++0x00,0x64,0x18,0x21,0x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21,0x00,0x03,0x18,0x80, ++0x00,0x66,0x18,0x21,0x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08, ++0x8c,0x44,0x00,0x08,0x3c,0x03,0x80,0x00,0x00,0xa3,0x30,0x24,0x10,0xc0,0x00,0x08, ++0x00,0x83,0x10,0x24,0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21,0x10,0xc0,0x00,0x02, ++0x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b,0x08,0x00,0x18,0xac,0xa2,0x23,0x00,0x17, ++0x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b,0x08,0x00,0x18,0xcf,0x00,0x00,0x00,0x00, ++0x10,0xa2,0x00,0x09,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x05,0x24,0x02,0x00,0x03, ++0x14,0xa2,0xff,0xca,0x00,0x00,0x00,0x00,0x08,0x00,0x18,0xa7,0xa2,0x40,0x00,0x07, ++0x08,0x00,0x18,0xa7,0xa2,0x40,0x00,0x06,0x08,0x00,0x18,0xa7,0xa2,0x40,0x00,0x05, ++0x14,0x40,0xff,0xbe,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00, ++0x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80,0x08,0x00,0x18,0x9e,0x00,0xa2,0x10,0x07, ++0x0c,0x00,0x17,0x8d,0x02,0x40,0x20,0x21,0x08,0x00,0x18,0x1d,0x00,0x00,0x00,0x00, ++0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa6,0x00,0xff,0x2c,0xc2,0x00,0x04, ++0x10,0x40,0x00,0x99,0x2c,0xc2,0x00,0x10,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29, ++0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,0x00,0xc2,0x10,0x04,0x00,0x02,0x10,0x27, ++0x00,0x62,0x18,0x24,0xa0,0x83,0x00,0x00,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00, ++0x30,0xa5,0x00,0xff,0x14,0xa0,0x00,0x80,0x24,0x02,0x00,0x01,0xa2,0x40,0x00,0x04, ++0x86,0x43,0x00,0x0c,0x27,0x93,0x99,0x44,0x96,0x47,0x00,0x0c,0x00,0x03,0x10,0xc0, ++0x00,0x43,0x10,0x21,0x00,0x02,0x28,0x80,0x00,0xb3,0x18,0x21,0x8c,0x64,0x00,0x18, ++0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x10, ++0x10,0x40,0x00,0x64,0x00,0x00,0x30,0x21,0x00,0x07,0x1c,0x00,0x00,0x03,0x1c,0x03, ++0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x53,0x10,0x21, ++0x8c,0x43,0x00,0x18,0x93,0x82,0x94,0x51,0x8c,0x64,0x00,0x04,0x30,0x42,0x00,0x01, ++0x00,0x04,0x21,0x42,0x14,0x40,0x00,0x4d,0x30,0x90,0x00,0x01,0x00,0x07,0x2c,0x00, ++0x00,0x05,0x2c,0x03,0x0c,0x00,0x22,0xe1,0x02,0x20,0x20,0x21,0x96,0x26,0x00,0x06, ++0x12,0x00,0x00,0x14,0x30,0xc5,0xff,0xff,0x02,0x60,0x90,0x21,0x00,0x05,0x10,0xc0, ++0x00,0x45,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x52,0x18,0x21,0x92,0x22,0x00,0x0a, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0b,0x02,0x20,0x20,0x21,0x8c,0x63,0x00,0x18, ++0x00,0x00,0x00,0x00,0x8c,0x62,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x02,0x11,0x42, ++0x0c,0x00,0x22,0xe1,0x30,0x50,0x00,0x01,0x96,0x26,0x00,0x06,0x16,0x00,0xff,0xef, ++0x30,0xc5,0xff,0xff,0x92,0x22,0x00,0x04,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x0d, ++0x24,0x02,0x00,0x01,0xa2,0x22,0x00,0x17,0x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00, ++0x10,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0xa6,0x26,0x00,0x14,0x92,0x22,0x00,0x16, ++0x08,0x00,0x18,0x1c,0x30,0x42,0x00,0xc3,0x96,0x22,0x00,0x00,0x08,0x00,0x19,0x43, ++0xa6,0x22,0x00,0x14,0x92,0x22,0x00,0x0a,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03, ++0x00,0x00,0x00,0x00,0x08,0x00,0x19,0x3e,0xa2,0x20,0x00,0x17,0x96,0x24,0x00,0x00, ++0x30,0xc5,0xff,0xff,0x00,0x05,0x18,0xc0,0x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21, ++0x00,0x65,0x18,0x21,0x27,0x84,0x99,0x40,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21, ++0x00,0x03,0x18,0x80,0x8c,0x45,0x00,0x08,0x00,0x64,0x18,0x21,0x8c,0x64,0x00,0x08, ++0x3c,0x02,0x80,0x00,0x00,0xa2,0x38,0x24,0x10,0xe0,0x00,0x08,0x00,0x82,0x10,0x24, ++0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21,0x10,0xe0,0x00,0x02,0x24,0x03,0x00,0x01, ++0x00,0x85,0x18,0x2b,0x08,0x00,0x19,0x3e,0xa2,0x23,0x00,0x17,0x10,0x40,0xff,0xfd, ++0x00,0x85,0x18,0x2b,0x08,0x00,0x19,0x62,0x00,0x00,0x00,0x00,0x24,0x05,0x00,0x24, ++0xf0,0xe5,0x00,0x06,0x00,0x00,0x28,0x12,0x27,0x82,0x99,0x40,0x00,0xa2,0x28,0x21, ++0x0c,0x00,0x01,0x49,0x00,0x00,0x20,0x21,0x96,0x47,0x00,0x0c,0x08,0x00,0x19,0x20, ++0x00,0x07,0x2c,0x00,0x27,0x83,0x99,0x50,0x27,0x82,0x99,0x58,0x00,0xa2,0x10,0x21, ++0x00,0xa3,0x18,0x21,0x90,0x44,0x00,0x00,0x90,0x65,0x00,0x05,0x93,0x82,0x80,0x10, ++0x24,0x07,0x00,0x01,0x0c,0x00,0x29,0x0b,0xaf,0xa2,0x00,0x10,0x96,0x47,0x00,0x0c, ++0x08,0x00,0x19,0x13,0x00,0x07,0x1c,0x00,0x10,0xa2,0x00,0x09,0x24,0x02,0x00,0x02, ++0x10,0xa2,0x00,0x05,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0x7d,0x00,0x00,0x00,0x00, ++0x08,0x00,0x19,0x04,0xa2,0x40,0x00,0x07,0x08,0x00,0x19,0x04,0xa2,0x40,0x00,0x06, ++0x08,0x00,0x19,0x04,0xa2,0x40,0x00,0x05,0x14,0x40,0xff,0x71,0x3c,0x04,0xb0,0x05, ++0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80, ++0x08,0x00,0x18,0xfb,0x00,0xa2,0x10,0x07,0x14,0x40,0xfe,0xc3,0x3c,0x04,0xb0,0x05, ++0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80, ++0x08,0x00,0x18,0x56,0x00,0xa2,0x10,0x07,0x84,0x83,0x00,0x0c,0x00,0x00,0x00,0x00, ++0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x99,0x44, ++0x00,0x43,0x10,0x21,0x8c,0x47,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0xe6,0x00,0x08, ++0x0c,0x00,0x16,0x9f,0x00,0x00,0x00,0x00,0x02,0x40,0x20,0x21,0x00,0x00,0x28,0x21, ++0x00,0x00,0x30,0x21,0x00,0x00,0x38,0x21,0x0c,0x00,0x23,0xe3,0xaf,0xa2,0x00,0x10, ++0x00,0x02,0x1e,0x00,0x14,0x60,0xfe,0x6b,0xa2,0x22,0x00,0x12,0x92,0x43,0x00,0x08, ++0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x40,0x24,0x02,0x00,0x01,0xa2,0x40,0x00,0x04, ++0x92,0x28,0x00,0x04,0x00,0x00,0x00,0x00,0x15,0x00,0x00,0x19,0x24,0x02,0x00,0x01, ++0x92,0x27,0x00,0x0a,0xa2,0x22,0x00,0x17,0x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00, ++0x10,0x40,0x00,0x10,0x00,0x00,0x00,0x00,0x96,0x22,0x00,0x06,0x00,0x00,0x00,0x00, ++0xa6,0x22,0x00,0x14,0x92,0x22,0x00,0x16,0x30,0xe3,0x00,0xff,0x30,0x42,0x00,0xc0, ++0x10,0x60,0x00,0x03,0xa2,0x22,0x00,0x16,0x34,0x42,0x00,0x01,0xa2,0x22,0x00,0x16, ++0x11,0x00,0xfe,0x50,0x00,0x00,0x00,0x00,0x92,0x22,0x00,0x16,0x08,0x00,0x18,0x1c, ++0x34,0x42,0x00,0x02,0x96,0x22,0x00,0x00,0x08,0x00,0x19,0xc5,0xa6,0x22,0x00,0x14, ++0x92,0x27,0x00,0x0a,0x00,0x00,0x00,0x00,0x14,0xe0,0x00,0x03,0x00,0x00,0x00,0x00, ++0x08,0x00,0x19,0xbe,0xa2,0x20,0x00,0x17,0x96,0x24,0x00,0x00,0x96,0x25,0x00,0x06, ++0x27,0x86,0x99,0x40,0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x05,0x10,0xc0, ++0x00,0x45,0x10,0x21,0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,0x00,0x02,0x10,0x80, ++0x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08,0x8c,0x44,0x00,0x08,0x3c,0x03,0x80,0x00, ++0x00,0xa3,0x30,0x24,0x10,0xc0,0x00,0x08,0x00,0x83,0x10,0x24,0x10,0x40,0x00,0x04, ++0x00,0x00,0x18,0x21,0x10,0xc0,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b, ++0x08,0x00,0x19,0xbe,0xa2,0x23,0x00,0x17,0x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b, ++0x08,0x00,0x19,0xed,0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x09,0x24,0x02,0x00,0x02, ++0x10,0x62,0x00,0x05,0x24,0x02,0x00,0x03,0x14,0x62,0xff,0xbd,0x00,0x00,0x00,0x00, ++0x08,0x00,0x19,0xb8,0xa2,0x40,0x00,0x07,0x08,0x00,0x19,0xb8,0xa2,0x40,0x00,0x06, ++0x08,0x00,0x19,0xb8,0xa2,0x40,0x00,0x05,0x3c,0x02,0x80,0x00,0x00,0x82,0x30,0x24, ++0x10,0xc0,0x00,0x08,0x00,0xa2,0x18,0x24,0x10,0x60,0x00,0x04,0x00,0x00,0x10,0x21, ++0x10,0xc0,0x00,0x02,0x24,0x02,0x00,0x01,0x00,0xa4,0x10,0x2b,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x10,0x60,0xff,0xfd,0x00,0xa4,0x10,0x2b,0x08,0x00,0x1a,0x08, ++0x00,0x00,0x00,0x00,0x30,0x82,0xff,0xff,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21, ++0x27,0x84,0x99,0x50,0x00,0x03,0x18,0x80,0x00,0x64,0x18,0x21,0x80,0x66,0x00,0x06, ++0x00,0x02,0x12,0x00,0x3c,0x03,0xb0,0x00,0x00,0x46,0x10,0x21,0x00,0x45,0x10,0x21, ++0x03,0xe0,0x00,0x08,0x00,0x43,0x10,0x21,0x27,0xbd,0xff,0xe0,0x30,0x82,0x00,0x7c, ++0x30,0x84,0xff,0x00,0xaf,0xbf,0x00,0x1c,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14, ++0xaf,0xb0,0x00,0x10,0x14,0x40,0x00,0x41,0x00,0x04,0x22,0x03,0x24,0x02,0x00,0x04, ++0x3c,0x10,0xb0,0x03,0x8e,0x10,0x00,0x00,0x10,0x82,0x00,0x32,0x24,0x02,0x00,0x08, ++0x10,0x82,0x00,0x03,0x32,0x02,0x00,0x20,0x08,0x00,0x1a,0x2e,0x00,0x00,0x00,0x00, ++0x10,0x40,0x00,0x17,0x3c,0x02,0xb0,0x06,0x34,0x42,0x80,0x24,0x8c,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x67,0x00,0xff,0x10,0xe0,0x00,0x23,0x00,0x00,0x88,0x21, ++0x8f,0x85,0x99,0x20,0x00,0x40,0x30,0x21,0x94,0xa2,0x00,0x08,0x8c,0xc3,0x00,0x00, ++0x26,0x31,0x00,0x01,0x24,0x42,0x00,0x02,0x30,0x42,0x01,0xff,0x34,0x63,0x01,0x00, ++0x02,0x27,0x20,0x2a,0xa4,0xa2,0x00,0x08,0x14,0x80,0xff,0xf7,0xac,0xc3,0x00,0x00, ++0x84,0xa3,0x00,0x08,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x30,0xac,0x43,0x00,0x00, ++0x27,0x92,0xbd,0x40,0x24,0x11,0x00,0x12,0x8e,0x44,0x00,0x00,0x26,0x31,0xff,0xff, ++0x90,0x82,0x00,0x10,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x03,0x26,0x52,0x00,0x04, ++0x0c,0x00,0x20,0x48,0x00,0x00,0x00,0x00,0x06,0x21,0xff,0xf7,0x24,0x02,0xff,0xdf, ++0x02,0x02,0x80,0x24,0x3c,0x01,0xb0,0x03,0x0c,0x00,0x1a,0xe6,0xac,0x30,0x00,0x00, ++0x08,0x00,0x1a,0x2e,0x00,0x00,0x00,0x00,0x8f,0x85,0x99,0x20,0x08,0x00,0x1a,0x44, ++0x00,0x00,0x00,0x00,0x24,0x02,0xff,0x95,0x3c,0x03,0xb0,0x03,0x02,0x02,0x80,0x24, ++0x34,0x63,0x00,0x30,0x3c,0x01,0xb0,0x03,0xac,0x30,0x00,0x00,0x0c,0x00,0x1a,0xaf, ++0xac,0x60,0x00,0x00,0x08,0x00,0x1a,0x2e,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03, ++0x34,0x42,0x00,0x50,0x08,0x00,0x1a,0x2e,0xac,0x46,0x00,0x00,0xaf,0xa7,0x00,0x0c, ++0xaf,0xa4,0x00,0x00,0xaf,0xa5,0x00,0x04,0xaf,0xa6,0x00,0x08,0x27,0xbd,0xfe,0xe8, ++0x00,0x80,0x28,0x21,0x27,0xa6,0x01,0x1c,0x27,0xa4,0x00,0x10,0xaf,0xbf,0x01,0x14, ++0x0c,0x00,0x2e,0x2c,0xaf,0xb0,0x01,0x10,0x00,0x40,0x80,0x21,0x0c,0x00,0x1a,0x7e, ++0x27,0xa4,0x00,0x10,0x02,0x00,0x10,0x21,0x8f,0xbf,0x01,0x14,0x8f,0xb0,0x01,0x10, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x01,0x18,0x93,0x83,0x87,0x6c,0x27,0xbd,0xff,0xe8, ++0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0x14,0x60,0x00,0x14,0x00,0x80,0x80,0x21, ++0x80,0x82,0x00,0x00,0x90,0x84,0x00,0x00,0x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00, ++0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18, ++0x00,0x04,0x26,0x00,0x00,0x04,0x26,0x03,0x30,0x84,0xff,0xff,0x0c,0x00,0x1a,0x9e, ++0x26,0x10,0x00,0x01,0x92,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x60,0xff,0xf8, ++0x00,0x60,0x20,0x21,0x08,0x00,0x1a,0x88,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x14,0x43,0xff,0xef,0x00,0x00,0x00,0x00,0x0c,0x00,0x05,0x52,0x00,0x00,0x00,0x00, ++0x08,0x00,0x1a,0x88,0x00,0x00,0x00,0x00,0x30,0x84,0xff,0xff,0x48,0x84,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10, ++0x0c,0x00,0x2d,0x94,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x10,0x00,0x02,0x14,0x00, ++0x00,0x02,0x14,0x03,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x03,0xe0,0x00,0x08, ++0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,0x24,0x02,0x00,0x01,0x3c,0x0a,0x80,0x00, ++0x25,0x4a,0x6a,0xbc,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0x3c,0x08,0x80,0x01, ++0x25,0x08,0x00,0x00,0x3c,0x09,0x80,0x01,0x25,0x29,0x0b,0x90,0x11,0x09,0x00,0x10, ++0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x6a,0xe4,0x3c,0x0b,0xb0,0x03, ++0xad,0x6a,0x00,0x20,0x3c,0x08,0xb0,0x06,0x35,0x08,0x80,0x10,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x31,0x29,0x00,0x01, ++0x00,0x00,0x00,0x00,0x24,0x01,0x00,0x01,0x15,0x21,0xff,0xf2,0x00,0x00,0x00,0x00, ++0x3c,0x0a,0x80,0x00,0x25,0x4a,0x6b,0x20,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20, ++0x3c,0x02,0xb0,0x03,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0x63,0x00,0x40, ++0x00,0x00,0x00,0x00,0xac,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00, ++0x25,0x4a,0x6b,0x4c,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0x3c,0x02,0x80,0x01, ++0x24,0x42,0x00,0x00,0x3c,0x03,0x80,0x01,0x24,0x63,0x0b,0x90,0x3c,0x04,0xb0,0x00, ++0x8c,0x85,0x00,0x00,0x00,0x00,0x00,0x00,0xac,0x45,0x00,0x00,0x24,0x42,0x00,0x04, ++0x24,0x84,0x00,0x04,0x00,0x43,0x08,0x2a,0x14,0x20,0xff,0xf9,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x1a,0xe6,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x6b,0x98, ++0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0x3c,0x02,0x80,0x01,0x24,0x42,0x0b,0x90, ++0x3c,0x03,0x80,0x01,0x24,0x63,0x48,0x64,0xac,0x40,0x00,0x00,0xac,0x40,0x00,0x04, ++0xac,0x40,0x00,0x08,0xac,0x40,0x00,0x0c,0x24,0x42,0x00,0x10,0x00,0x43,0x08,0x2a, ++0x14,0x20,0xff,0xf9,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x6b,0xd8, ++0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0x3c,0x1c,0x80,0x01,0x27,0x9c,0x7f,0xf0, ++0x27,0x9d,0x95,0x20,0x00,0x00,0x00,0x00,0x27,0x9d,0x99,0x08,0x3c,0x0a,0x80,0x00, ++0x25,0x4a,0x6b,0xfc,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0x40,0x80,0x68,0x00, ++0x40,0x08,0x60,0x00,0x00,0x00,0x00,0x00,0x35,0x08,0xff,0x01,0x40,0x88,0x60,0x00, ++0x00,0x00,0x00,0x00,0x0c,0x00,0x1d,0x15,0x00,0x00,0x00,0x00,0x24,0x84,0xf8,0x00, ++0x30,0x87,0x00,0x03,0x00,0x04,0x30,0x40,0x00,0xc7,0x20,0x23,0x3c,0x02,0xb0,0x0a, ++0x27,0xbd,0xff,0xe0,0x24,0x03,0xff,0xff,0x00,0x82,0x20,0x21,0xaf,0xb1,0x00,0x14, ++0xac,0x83,0x10,0x00,0xaf,0xbf,0x00,0x18,0xaf,0xb0,0x00,0x10,0x00,0xa0,0x88,0x21, ++0x24,0x03,0x00,0x01,0x8c,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd, ++0x00,0xc7,0x10,0x23,0x3c,0x03,0xb0,0x0a,0x00,0x43,0x10,0x21,0x8c,0x50,0x00,0x00, ++0x0c,0x00,0x1b,0x63,0x02,0x20,0x20,0x21,0x02,0x11,0x80,0x24,0x00,0x50,0x80,0x06, ++0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x20,0x27,0xbd,0xff,0xd8,0xaf,0xb2,0x00,0x18,0x00,0xa0,0x90,0x21, ++0x24,0x05,0xff,0xff,0xaf,0xb3,0x00,0x1c,0xaf,0xbf,0x00,0x20,0xaf,0xb1,0x00,0x14, ++0xaf,0xb0,0x00,0x10,0x00,0xc0,0x98,0x21,0x12,0x45,0x00,0x23,0x24,0x84,0xf8,0x00, ++0x30,0x83,0x00,0x03,0x00,0x04,0x10,0x40,0x00,0x40,0x88,0x21,0x00,0x60,0x20,0x21, ++0x00,0x43,0x10,0x23,0x3c,0x03,0xb0,0x0a,0x00,0x43,0x10,0x21,0xac,0x45,0x10,0x00, ++0x00,0x40,0x18,0x21,0x24,0x05,0x00,0x01,0x8c,0x62,0x10,0x00,0x00,0x00,0x00,0x00, ++0x14,0x45,0xff,0xfd,0x3c,0x02,0xb0,0x0a,0x02,0x24,0x88,0x23,0x02,0x22,0x88,0x21, ++0x8e,0x30,0x00,0x00,0x0c,0x00,0x1b,0x63,0x02,0x40,0x20,0x21,0x00,0x12,0x18,0x27, ++0x02,0x03,0x80,0x24,0x00,0x53,0x10,0x04,0x02,0x02,0x80,0x25,0xae,0x30,0x00,0x00, ++0x24,0x03,0x00,0x01,0x8e,0x22,0x10,0x00,0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd, ++0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x30,0x82,0x00,0x03,0x00,0x04,0x18,0x40, ++0x00,0x62,0x18,0x23,0x3c,0x04,0xb0,0x0a,0x00,0x64,0x18,0x21,0xac,0x66,0x00,0x00, ++0x24,0x04,0x00,0x01,0x8c,0x62,0x10,0x00,0x00,0x00,0x00,0x00,0x14,0x44,0xff,0xfd, ++0x00,0x00,0x00,0x00,0x08,0x00,0x1b,0x51,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x21, ++0x00,0x64,0x10,0x06,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00, ++0x24,0x63,0x00,0x01,0x2c,0x62,0x00,0x20,0x14,0x40,0xff,0xf9,0x00,0x00,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,0x27,0xbd,0xff,0xe0,0x3c,0x03,0xb0,0x05, ++0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x1c, ++0x00,0x80,0x90,0x21,0x00,0xa0,0x80,0x21,0x00,0xc0,0x88,0x21,0x34,0x63,0x02,0x2e, ++0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0xff,0xfc, ++0x24,0x04,0x08,0x24,0x3c,0x05,0x00,0xc0,0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x03, ++0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0xc0,0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x03, ++0x3c,0x02,0xc0,0x00,0x00,0x10,0x1c,0x00,0x34,0x42,0x04,0x00,0x3c,0x04,0xb0,0x05, ++0x3c,0x05,0xb0,0x05,0x24,0x63,0x16,0x09,0x02,0x22,0x10,0x21,0x34,0x84,0x04,0x20, ++0x34,0xa5,0x04,0x24,0x3c,0x06,0xb0,0x05,0xac,0x83,0x00,0x00,0x24,0x07,0x00,0x01, ++0xac,0xa2,0x00,0x00,0x34,0xc6,0x02,0x28,0x24,0x02,0x00,0x20,0xae,0x47,0x00,0x3c, ++0x24,0x04,0x08,0x24,0xa0,0xc2,0x00,0x00,0x3c,0x05,0x00,0xc0,0xa2,0x47,0x00,0x11, ++0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x01,0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0xc0, ++0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x01,0x8f,0xbf,0x00,0x1c,0x8f,0xb2,0x00,0x18, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x24,0x02,0x00,0x06, ++0xac,0x82,0x00,0x0c,0xa0,0x80,0x00,0x50,0xac,0x80,0x00,0x00,0xac,0x80,0x00,0x04, ++0xac,0x80,0x00,0x08,0xac,0x80,0x00,0x14,0xac,0x80,0x00,0x18,0xac,0x80,0x00,0x1c, ++0xa4,0x80,0x00,0x20,0xac,0x80,0x00,0x24,0xac,0x80,0x00,0x28,0xac,0x80,0x00,0x2c, ++0xa0,0x80,0x00,0x30,0xa0,0x80,0x00,0x31,0xac,0x80,0x00,0x34,0xac,0x80,0x00,0x38, ++0xa0,0x80,0x00,0x3c,0xac,0x82,0x00,0x10,0xa0,0x80,0x00,0x44,0xac,0x80,0x00,0x48, ++0x03,0xe0,0x00,0x08,0xac,0x80,0x00,0x4c,0x3c,0x04,0xb0,0x06,0x34,0x84,0x80,0x00, ++0x8c,0x83,0x00,0x00,0x3c,0x02,0x12,0x00,0x3c,0x05,0xb0,0x03,0x00,0x62,0x18,0x25, ++0x34,0xa5,0x00,0x8b,0x24,0x02,0xff,0x80,0xac,0x83,0x00,0x00,0x03,0xe0,0x00,0x08, ++0xa0,0xa2,0x00,0x00,0x3c,0x04,0xb0,0x03,0x34,0x84,0x00,0x0b,0x24,0x02,0x00,0x22, ++0x3c,0x05,0xb0,0x01,0x3c,0x06,0x45,0x67,0x3c,0x0a,0xb0,0x09,0xa0,0x82,0x00,0x00, ++0x34,0xa5,0x00,0x04,0x34,0xc6,0x89,0xaa,0x35,0x4a,0x00,0x04,0x24,0x02,0x01,0x23, ++0x3c,0x0b,0xb0,0x09,0x3c,0x07,0x01,0x23,0x3c,0x0c,0xb0,0x09,0x3c,0x01,0xb0,0x01, ++0xac,0x20,0x00,0x00,0x27,0xbd,0xff,0xe0,0xac,0xa0,0x00,0x00,0x35,0x6b,0x00,0x08, ++0x3c,0x01,0xb0,0x09,0xac,0x26,0x00,0x00,0x34,0xe7,0x45,0x66,0xa5,0x42,0x00,0x00, ++0x35,0x8c,0x00,0x0c,0x24,0x02,0xcd,0xef,0x3c,0x0d,0xb0,0x09,0x3c,0x08,0xcd,0xef, ++0x3c,0x0e,0xb0,0x09,0xad,0x67,0x00,0x00,0xaf,0xb7,0x00,0x1c,0xa5,0x82,0x00,0x00, ++0xaf,0xb6,0x00,0x18,0xaf,0xb5,0x00,0x14,0xaf,0xb4,0x00,0x10,0xaf,0xb3,0x00,0x0c, ++0xaf,0xb2,0x00,0x08,0xaf,0xb1,0x00,0x04,0xaf,0xb0,0x00,0x00,0x35,0xad,0x00,0x10, ++0x35,0x08,0x01,0x22,0x35,0xce,0x00,0x14,0x24,0x02,0x89,0xab,0x3c,0x0f,0xb0,0x09, ++0x3c,0x09,0x89,0xab,0x3c,0x10,0xb0,0x09,0x3c,0x11,0xb0,0x09,0x3c,0x12,0xb0,0x09, ++0x3c,0x13,0xb0,0x09,0x3c,0x14,0xb0,0x09,0x3c,0x15,0xb0,0x09,0x3c,0x16,0xb0,0x09, ++0x3c,0x17,0xb0,0x09,0xad,0xa8,0x00,0x00,0x24,0x03,0xff,0xff,0xa5,0xc2,0x00,0x00, ++0x35,0xef,0x00,0x18,0x35,0x29,0xcd,0xee,0x36,0x10,0x00,0x1c,0x36,0x31,0x00,0x20, ++0x36,0x52,0x00,0x24,0x36,0x73,0x00,0x28,0x36,0x94,0x00,0x2c,0x36,0xb5,0x00,0x30, ++0x36,0xd6,0x00,0x34,0x36,0xf7,0x00,0x38,0x24,0x02,0x45,0x67,0xad,0xe9,0x00,0x00, ++0xa6,0x02,0x00,0x00,0xae,0x23,0x00,0x00,0x8f,0xb0,0x00,0x00,0xa6,0x43,0x00,0x00, ++0x8f,0xb1,0x00,0x04,0xae,0x63,0x00,0x00,0x8f,0xb2,0x00,0x08,0xa6,0x83,0x00,0x00, ++0x8f,0xb3,0x00,0x0c,0xae,0xa3,0x00,0x00,0x8f,0xb4,0x00,0x10,0xa6,0xc3,0x00,0x00, ++0x8f,0xb5,0x00,0x14,0xae,0xe3,0x00,0x00,0x7b,0xb6,0x00,0xfc,0x3c,0x18,0xb0,0x09, ++0x37,0x18,0x00,0x3c,0xa7,0x03,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x70,0x70, ++0xac,0x62,0x00,0x00,0x8c,0x83,0x00,0x34,0x34,0x02,0xff,0xff,0x00,0x43,0x10,0x2a, ++0x14,0x40,0x00,0xed,0x00,0x80,0x28,0x21,0x8c,0x84,0x00,0x08,0x24,0x02,0x00,0x03, ++0x10,0x82,0x00,0xe0,0x00,0x00,0x00,0x00,0x8c,0xa2,0x00,0x2c,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x47,0x24,0x02,0x00,0x06,0x3c,0x03,0xb0,0x05,0x34,0x63,0x04,0x50, ++0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0x14,0x40,0x00,0xc6, ++0xac,0xa2,0x00,0x2c,0x24,0x02,0x00,0x01,0x10,0x82,0x00,0xc5,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x02,0x10,0x82,0x00,0xb3,0x00,0x00,0x00,0x00,0x8c,0xa6,0x00,0x04, ++0x24,0x02,0x00,0x02,0x10,0xc2,0x00,0xa9,0x00,0x00,0x00,0x00,0x8c,0xa2,0x00,0x14, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x09,0x24,0x02,0x00,0x01,0x3c,0x03,0xb0,0x09, ++0x34,0x63,0x01,0x60,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff, ++0x10,0x40,0x00,0x05,0xac,0xa2,0x00,0x14,0x24,0x02,0x00,0x01,0xac,0xa2,0x00,0x00, ++0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x14,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xd0, ++0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x61,0x00,0x16,0x3c,0x03,0xb0,0x05, ++0x34,0x63,0x02,0x2e,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01, ++0x14,0x40,0x00,0x10,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x42,0x90,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x0b,0x00,0x00,0x00,0x00,0x80,0xa2,0x00,0x50, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x07,0x00,0x00,0x00,0x00,0x14,0x80,0x00,0x05, ++0x24,0x02,0x00,0x0e,0x24,0x03,0x00,0x01,0xac,0xa2,0x00,0x00,0x03,0xe0,0x00,0x08, ++0xa0,0xa3,0x00,0x50,0x80,0xa2,0x00,0x31,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0a, ++0x3c,0x02,0xb0,0x06,0x34,0x42,0x80,0x18,0x8c,0x43,0x00,0x00,0x3c,0x04,0xf0,0x00, ++0x3c,0x02,0x80,0x00,0x00,0x64,0x18,0x24,0x10,0x62,0x00,0x03,0x24,0x02,0x00,0x09, ++0x03,0xe0,0x00,0x08,0xac,0xa2,0x00,0x00,0x8c,0xa2,0x00,0x40,0x00,0x00,0x00,0x00, ++0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x09,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,0x8c,0x43,0x00,0x00,0x3c,0x04,0x00,0x02, ++0x00,0x64,0x18,0x24,0x14,0x60,0xff,0xf2,0x24,0x02,0x00,0x10,0x3c,0x03,0xb0,0x03, ++0x34,0x63,0x02,0x01,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x80, ++0x10,0x40,0x00,0x0e,0x00,0x00,0x00,0x00,0x8c,0xa3,0x00,0x0c,0x00,0x00,0x00,0x00, ++0xac,0xa3,0x00,0x10,0x3c,0x02,0xb0,0x03,0x90,0x42,0x02,0x01,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0x0f,0xac,0xa2,0x00,0x0c,0x90,0xa3,0x00,0x0f,0x24,0x02,0x00,0x0d, ++0x3c,0x01,0xb0,0x03,0x08,0x00,0x1c,0x74,0xa0,0x23,0x02,0x01,0x3c,0x02,0xb0,0x09, ++0x34,0x42,0x01,0x80,0x90,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x1e,0x00, ++0x00,0x03,0x1e,0x03,0x10,0x60,0x00,0x15,0xa0,0xa4,0x00,0x44,0x24,0x02,0x00,0x01, ++0x10,0x62,0x00,0x0b,0x24,0x02,0x00,0x02,0x10,0x62,0x00,0x03,0x24,0x03,0x00,0x0d, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8c,0xa2,0x00,0x0c,0xac,0xa3,0x00,0x00, ++0x24,0x03,0x00,0x04,0xac,0xa2,0x00,0x10,0x03,0xe0,0x00,0x08,0xac,0xa3,0x00,0x0c, ++0x24,0x02,0x00,0x0d,0xac,0xa2,0x00,0x00,0x24,0x03,0x00,0x04,0x24,0x02,0x00,0x06, ++0xac,0xa3,0x00,0x10,0x03,0xe0,0x00,0x08,0xac,0xa2,0x00,0x0c,0x8c,0xa3,0x00,0x38, ++0x24,0x04,0x00,0x01,0x10,0x64,0x00,0x2d,0x24,0x02,0x00,0x02,0x10,0x60,0x00,0x19, ++0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x10,0x24,0x02,0x00,0x04,0x10,0x62,0x00,0x04, ++0x00,0x00,0x00,0x00,0xac,0xa0,0x00,0x38,0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x00, ++0x10,0xc4,0x00,0x07,0x24,0x02,0x00,0x03,0x80,0xa2,0x00,0x30,0x00,0x00,0x00,0x00, ++0x00,0x02,0x18,0x0b,0xac,0xa3,0x00,0x00,0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x38, ++0x08,0x00,0x1c,0xc6,0xac,0xa2,0x00,0x00,0x10,0xc4,0x00,0x02,0x24,0x02,0x00,0x03, ++0x24,0x02,0x00,0x0c,0xac,0xa2,0x00,0x00,0x24,0x02,0x00,0x04,0x03,0xe0,0x00,0x08, ++0xac,0xa2,0x00,0x38,0x10,0xc4,0x00,0x0e,0x3c,0x03,0xb0,0x06,0x34,0x63,0x80,0x24, ++0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0x10,0x40,0x00,0x06, ++0xac,0xa2,0x00,0x18,0x24,0x02,0x00,0x02,0xac,0xa2,0x00,0x00,0xac,0xa0,0x00,0x18, ++0x08,0x00,0x1c,0xcf,0x24,0x02,0x00,0x01,0x08,0x00,0x1c,0xdc,0xac,0xa0,0x00,0x00, ++0x24,0x02,0x00,0x03,0x08,0x00,0x1c,0xdc,0xac,0xa2,0x00,0x00,0x24,0x03,0x00,0x0b, ++0xac,0xa2,0x00,0x38,0x03,0xe0,0x00,0x08,0xac,0xa3,0x00,0x00,0x80,0xa2,0x00,0x30, ++0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x55,0x24,0x02,0x00,0x04,0x08,0x00,0x1c,0x74, ++0x00,0x00,0x00,0x00,0x84,0xa2,0x00,0x20,0x00,0x00,0x00,0x00,0x10,0x40,0xff,0x84, ++0x24,0x02,0x00,0x06,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21, ++0x14,0x40,0xff,0x42,0xa4,0xa3,0x00,0x20,0x08,0x00,0x1c,0x74,0x24,0x02,0x00,0x06, ++0x8c,0xa2,0x00,0x1c,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x75,0x24,0x02,0x00,0x05, ++0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2c,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0xff,0x10,0x40,0xff,0x32,0xac,0xa2,0x00,0x1c,0x08,0x00,0x1c,0x74, ++0x24,0x02,0x00,0x05,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x02,0x17,0x42,0x30,0x42,0x00,0x01,0x14,0x40,0xff,0x65,0x24,0x02,0x00,0x06, ++0x08,0x00,0x1c,0x2a,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x0a,0x03,0xe0,0x00,0x08, ++0xac,0x82,0x00,0x00,0x27,0xbd,0xff,0xc8,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10, ++0x27,0x91,0x91,0xf8,0x27,0x90,0x8f,0x38,0xaf,0xbf,0x00,0x30,0xaf,0xb7,0x00,0x2c, ++0xaf,0xb6,0x00,0x28,0xaf,0xb5,0x00,0x24,0xaf,0xb4,0x00,0x20,0xaf,0xb3,0x00,0x1c, ++0x0c,0x00,0x2d,0x21,0xaf,0xb2,0x00,0x18,0x0c,0x00,0x07,0x90,0x00,0x00,0x00,0x00, ++0xaf,0x91,0x95,0x10,0xaf,0x90,0x99,0x20,0x48,0x02,0x00,0x00,0x0c,0x00,0x1b,0xba, ++0x00,0x00,0x00,0x00,0x0c,0x00,0x1f,0x97,0x02,0x00,0x20,0x21,0x3c,0x02,0xb0,0x03, ++0x34,0x42,0x00,0x3a,0x94,0x43,0x00,0x00,0x3a,0x54,0xff,0xff,0xa3,0x83,0x99,0x24, ++0x0c,0x00,0x00,0x34,0x02,0x80,0xa8,0x21,0x0c,0x00,0x1b,0xc5,0x02,0x80,0xb0,0x21, ++0x27,0x84,0x8d,0x78,0x0c,0x00,0x32,0x44,0x02,0x80,0xb8,0x21,0x93,0x84,0x80,0x10, ++0x0c,0x00,0x28,0xb0,0x00,0x00,0x00,0x00,0x0c,0x00,0x0e,0x84,0x02,0x20,0x20,0x21, ++0x0c,0x00,0x01,0x39,0x00,0x00,0x00,0x00,0x27,0x84,0x8d,0x20,0x0c,0x00,0x1b,0xa3, ++0x00,0x00,0x00,0x00,0x27,0x82,0x92,0x2c,0xaf,0x82,0x8d,0x60,0x0c,0x00,0x00,0x5f, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x01,0x08,0x3c,0x04,0xb0,0x09, ++0x3c,0x05,0xb0,0x09,0x8c,0x66,0x00,0x00,0x34,0x84,0x01,0x68,0x24,0x02,0xc8,0x80, ++0x34,0xa5,0x01,0x40,0x24,0x03,0x00,0x0a,0xa4,0x82,0x00,0x00,0xa4,0xa3,0x00,0x00, ++0x3c,0x04,0xb0,0x03,0x8c,0x82,0x00,0x00,0xaf,0x86,0x8d,0x18,0x34,0x42,0x00,0x20, ++0xac,0x82,0x00,0x00,0x0c,0x00,0x07,0xa1,0x00,0x00,0x00,0x00,0x3c,0x04,0xb0,0x05, ++0x0c,0x00,0x2d,0x39,0x34,0x84,0x00,0x04,0x8f,0x83,0x8d,0x20,0x00,0x00,0x00,0x00, ++0x2c,0x62,0x00,0x11,0x10,0x40,0xff,0xf7,0x00,0x03,0x10,0x80,0x3c,0x03,0x80,0x01, ++0x24,0x63,0x08,0xac,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0x27,0x84,0x8d,0x78,0x0c,0x00,0x31,0x79, ++0x00,0x00,0x00,0x00,0x27,0x84,0x8d,0x20,0x0c,0x00,0x1c,0x1c,0x00,0x00,0x00,0x00, ++0x93,0x83,0x88,0x6d,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x07,0x00,0x00,0x00,0x00, ++0x8f,0x82,0x8d,0x54,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xaf,0x82,0x8d,0x54, ++0x08,0x00,0x1d,0x55,0x00,0x00,0x00,0x00,0x27,0x84,0x8d,0x78,0x0c,0x00,0x31,0xf8, ++0x00,0x00,0x00,0x00,0x08,0x00,0x1d,0x70,0x00,0x00,0x00,0x00,0x27,0x84,0x8d,0x78, ++0x0c,0x00,0x33,0xda,0x00,0x00,0x00,0x00,0xa3,0x82,0x8d,0x51,0xaf,0x80,0x8d,0x20, ++0x08,0x00,0x1d,0x70,0x00,0x00,0x00,0x00,0x27,0x84,0x8f,0x38,0x0c,0x00,0x20,0xd3, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0x14,0x40,0x00,0x05,0x3c,0x03,0xb0,0x05, ++0xaf,0x80,0x8d,0x20,0xaf,0x80,0x8d,0x24,0x08,0x00,0x1d,0x70,0x00,0x00,0x00,0x00, ++0x34,0x63,0x04,0x50,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff, ++0xaf,0x82,0x8d,0x4c,0x14,0x40,0x00,0x1e,0x24,0x02,0x00,0x01,0x8f,0x84,0x8d,0x28, ++0x00,0x00,0x00,0x00,0x10,0x82,0x00,0x1d,0x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x60, ++0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x8d,0x34, ++0x14,0x40,0x00,0x13,0x24,0x02,0x00,0x01,0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x07, ++0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x01,0x24,0x03,0x00,0x03,0xaf,0x82,0x8d,0x24, ++0xaf,0x83,0x8d,0x20,0x08,0x00,0x1d,0x70,0x00,0x00,0x00,0x00,0x34,0x42,0x02,0x2e, ++0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff, ++0x00,0x60,0x10,0x21,0xa7,0x83,0x8d,0x40,0x14,0x40,0xff,0xf3,0x24,0x02,0x00,0x01, ++0xaf,0x82,0x8d,0x24,0x08,0x00,0x1d,0x7f,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x05, ++0x34,0x63,0x02,0x2c,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff, ++0xaf,0x82,0x8d,0x3c,0x14,0x40,0xff,0xf6,0x24,0x02,0x00,0x01,0x08,0x00,0x1d,0x97, ++0x3c,0x03,0xb0,0x09,0x27,0x84,0x8f,0x38,0x0c,0x00,0x22,0x4c,0x00,0x00,0x00,0x00, ++0x83,0x82,0x8d,0x50,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xed,0x24,0x02,0x00,0x02, ++0x3c,0x03,0xb0,0x05,0x34,0x63,0x04,0x50,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0xff,0xaf,0x82,0x8d,0x4c,0x14,0x40,0xff,0xe5,0x24,0x02,0x00,0x02, ++0x8f,0x84,0x8d,0x28,0x24,0x02,0x00,0x01,0x10,0x82,0x00,0x12,0x24,0x02,0x00,0x02, ++0x10,0x82,0x00,0x05,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x02,0xaf,0x82,0x8d,0x24, ++0x08,0x00,0x1d,0xa4,0x24,0x03,0x00,0x04,0x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21, ++0xa7,0x83,0x8d,0x40,0x14,0x40,0xff,0xf4,0x00,0x00,0x00,0x00,0x08,0x00,0x1d,0xb0, ++0x24,0x02,0x00,0x02,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2c,0x8c,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x8d,0x3c,0x14,0x40,0xff,0xf7, ++0x00,0x00,0x00,0x00,0x08,0x00,0x1d,0xd0,0x24,0x02,0x00,0x02,0x27,0x84,0x91,0xf8, ++0x0c,0x00,0x12,0xe2,0x00,0x00,0x00,0x00,0x8f,0x83,0x8d,0x24,0xaf,0x82,0x8d,0x3c, ++0x38,0x64,0x00,0x02,0x00,0x04,0x18,0x0a,0xaf,0x83,0x8d,0x24,0x14,0x40,0x00,0x08, ++0x24,0x02,0x00,0x05,0x8f,0x82,0x92,0x38,0xaf,0x80,0x8d,0x20,0x10,0x40,0xff,0x78, ++0x24,0x04,0x00,0x01,0xaf,0x84,0x8d,0x28,0x08,0x00,0x1d,0x70,0x00,0x00,0x00,0x00, ++0xaf,0x82,0x8d,0x20,0x08,0x00,0x1d,0x70,0x00,0x00,0x00,0x00,0x83,0x82,0x8d,0x70, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x02,0x24,0x02,0x00,0x20,0xaf,0x82,0x8d,0x3c, ++0x8f,0x85,0x8d,0x3c,0x27,0x84,0x91,0xf8,0x0c,0x00,0x14,0xbd,0x00,0x00,0x00,0x00, ++0x00,0x02,0x1e,0x00,0xa3,0x82,0x8d,0x50,0xaf,0x80,0x8d,0x3c,0x10,0x60,0xff,0x73, ++0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21,0xa7,0x83,0x8d,0x40, ++0x10,0x40,0xff,0xe7,0x24,0x02,0x00,0x06,0x24,0x04,0x00,0x02,0xaf,0x84,0x8d,0x28, ++0x08,0x00,0x1d,0x7f,0x00,0x00,0x00,0x00,0x27,0x84,0x8d,0x20,0x27,0x85,0x91,0xf8, ++0x0c,0x00,0x15,0x83,0x00,0x00,0x00,0x00,0x8f,0x82,0x8d,0x44,0xaf,0x80,0x8d,0x4c, ++0x14,0x40,0x00,0x18,0x00,0x40,0x18,0x21,0x8f,0x82,0x8d,0x48,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x14,0x24,0x02,0x00,0x02,0x8f,0x83,0x8d,0x28,0x00,0x00,0x00,0x00, ++0x10,0x62,0x00,0x09,0x24,0x02,0x00,0x01,0x8f,0x83,0x8d,0x24,0x00,0x00,0x00,0x00, ++0x10,0x62,0x00,0x02,0x24,0x02,0x00,0x03,0x24,0x02,0x00,0x06,0xaf,0x82,0x8d,0x20, ++0x08,0x00,0x1d,0xf9,0x24,0x04,0x00,0x03,0x3c,0x02,0x40,0x00,0x34,0x42,0x00,0x14, ++0x3c,0x01,0xb0,0x05,0xac,0x22,0x00,0x00,0xaf,0x80,0x8d,0x20,0x08,0x00,0x1d,0xf9, ++0x24,0x04,0x00,0x03,0x10,0x60,0x00,0x10,0x00,0x00,0x00,0x00,0x27,0x84,0x8d,0x20, ++0x27,0x85,0x91,0xf8,0x0c,0x00,0x15,0xa7,0x00,0x00,0x00,0x00,0x8f,0x83,0x8d,0x24, ++0x24,0x02,0x00,0x01,0xa3,0x80,0x8d,0x50,0xaf,0x80,0x8d,0x28,0x10,0x62,0x00,0x02, ++0x24,0x02,0x00,0x03,0x24,0x02,0x00,0x04,0xaf,0x82,0x8d,0x20,0xaf,0x80,0x8d,0x44, ++0x08,0x00,0x1d,0x70,0x00,0x00,0x00,0x00,0x83,0x82,0x8d,0x70,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0x27,0x84,0x91,0xf8,0x0c,0x00,0x17,0xef, ++0x00,0x00,0x00,0x00,0x8f,0x82,0x8d,0x24,0xa3,0x80,0x8d,0x50,0xaf,0x80,0x8d,0x20, ++0xaf,0x80,0x8d,0x28,0x14,0x40,0x00,0x02,0x24,0x02,0x00,0x02,0xaf,0x82,0x8d,0x24, ++0xaf,0x80,0x8d,0x48,0x08,0x00,0x1d,0x70,0x00,0x00,0x00,0x00,0x27,0x84,0x8d,0x20, ++0x27,0x85,0x91,0xf8,0x0c,0x00,0x15,0xa7,0x00,0x00,0x00,0x00,0x8f,0x82,0x8d,0x24, ++0xa3,0x80,0x8d,0x50,0xaf,0x80,0x8d,0x20,0xaf,0x80,0x8d,0x28,0x14,0x40,0xff,0x0c, ++0x24,0x02,0x00,0x02,0xaf,0x82,0x8d,0x24,0x08,0x00,0x1d,0x70,0x00,0x00,0x00,0x00, ++0x27,0x84,0x91,0xf8,0x0c,0x00,0x17,0xef,0x00,0x00,0x00,0x00,0x08,0x00,0x1e,0x5f, ++0x00,0x00,0x00,0x00,0x27,0x84,0x8d,0x78,0x0c,0x00,0x34,0x70,0x00,0x00,0x00,0x00, ++0x08,0x00,0x1d,0x7e,0x00,0x00,0x00,0x00,0x0c,0x00,0x2b,0x15,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x31,0xea,0x00,0x00,0x00,0x00,0x0c,0x00,0x1f,0x89,0x00,0x00,0x00,0x00, ++0x93,0x83,0xc5,0x58,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x1c,0x3c,0x02,0xb0,0x03, ++0x34,0x42,0x01,0x08,0x8c,0x44,0x00,0x00,0x8f,0x83,0xc5,0x50,0x8f,0x82,0xc5,0x54, ++0x00,0x83,0x18,0x23,0x00,0x43,0x10,0x2b,0x10,0x40,0x00,0x14,0x2e,0xa3,0x00,0x01, ++0x2e,0x82,0x00,0x01,0x00,0x43,0x10,0x25,0x2e,0xc4,0x00,0x01,0x00,0x44,0x10,0x25, ++0x2e,0xe3,0x00,0x01,0x3c,0x05,0xb0,0x03,0x00,0x43,0x10,0x25,0x34,0xa5,0x01,0x18, ++0x8c,0xa3,0x00,0x00,0x14,0x40,0x00,0x02,0x24,0x04,0x00,0x02,0x00,0x00,0x20,0x21, ++0x0c,0x00,0x0b,0x7e,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08, ++0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x83,0xc5,0x50,0x0c,0x00,0x01,0xe9, ++0x00,0x00,0x00,0x00,0xaf,0x80,0x8d,0x20,0xaf,0x80,0x8d,0x54,0x08,0x00,0x1d,0x55, ++0x00,0x00,0x00,0x00,0x27,0x90,0xbd,0x40,0x24,0x11,0x00,0x12,0x8e,0x04,0x00,0x00, ++0x00,0x00,0x00,0x00,0x90,0x82,0x00,0x10,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x03, ++0x00,0x00,0x00,0x00,0x0c,0x00,0x20,0x48,0x00,0x00,0x00,0x00,0x26,0x31,0xff,0xff, ++0x06,0x21,0xff,0xf6,0x26,0x10,0x00,0x04,0x08,0x00,0x1d,0x7f,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,0x8c,0x44,0x00,0x00,0x8f,0x82,0x8d,0x18, ++0x00,0x04,0x19,0xc2,0x00,0x02,0x11,0xc2,0x10,0x62,0xfe,0xcc,0x3c,0x02,0xb0,0x03, ++0x34,0x42,0x01,0x02,0x90,0x43,0x00,0x00,0x3c,0x12,0xb0,0x05,0xaf,0x84,0x8d,0x18, ++0x30,0x63,0x00,0xff,0x00,0x03,0x11,0x40,0x00,0x43,0x10,0x23,0x00,0x02,0x10,0x80, ++0x00,0x43,0x10,0x21,0x00,0x02,0x99,0x00,0x00,0x00,0x88,0x21,0x36,0x52,0x02,0x2c, ++0x27,0x90,0xbd,0x40,0x8e,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x83,0x00,0x16, ++0x00,0x00,0x00,0x00,0x30,0x62,0x00,0x03,0x10,0x40,0x00,0x06,0x30,0x62,0x00,0x1c, ++0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0x8f,0x85,0x8d,0x18,0x0c,0x00,0x26,0x05, ++0x02,0x60,0x30,0x21,0x8e,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff, ++0x14,0x40,0xfe,0xae,0x00,0x00,0x00,0x00,0x26,0x31,0x00,0x01,0x2a,0x22,0x00,0x13, ++0x14,0x40,0xff,0xec,0x26,0x10,0x00,0x04,0x08,0x00,0x1d,0x7f,0x00,0x00,0x00,0x00, ++0x8f,0x84,0x8d,0x2c,0x27,0x85,0x91,0xf8,0x0c,0x00,0x1f,0x1c,0x00,0x00,0x00,0x00, ++0x8f,0x83,0x8d,0x2c,0x24,0x02,0x00,0x04,0x14,0x62,0xfe,0xa0,0x24,0x02,0x00,0x05, ++0x08,0x00,0x1d,0xfc,0x00,0x00,0x00,0x00,0x27,0x84,0x91,0xf8,0x0c,0x00,0x2b,0x3c, ++0x00,0x00,0x00,0x00,0x08,0x00,0x1d,0xa4,0x24,0x03,0x00,0x05,0x8f,0x82,0x92,0x2c, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0d,0x00,0x00,0x00,0x00,0x8f,0x84,0xbd,0x80, ++0xaf,0x80,0x92,0x2c,0x94,0x85,0x00,0x14,0x0c,0x00,0x22,0xe1,0x00,0x00,0x00,0x00, ++0x93,0x82,0x94,0x51,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x02,0x10,0x40,0x00,0x03, ++0x00,0x00,0x00,0x00,0x0c,0x00,0x01,0x57,0x00,0x00,0x20,0x21,0x8f,0x84,0xbd,0x80, ++0x0c,0x00,0x20,0x48,0x00,0x00,0x00,0x00,0x08,0x00,0x1d,0x7f,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xff,0x90,0x27,0xbd,0xff,0xe8,0x00,0x80,0x18,0x21,0x34,0x42,0x00,0x01, ++0x27,0x84,0x91,0xf8,0x10,0x62,0x00,0x05,0xaf,0xbf,0x00,0x10,0x8f,0xbf,0x00,0x10, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x0e,0x84, ++0x00,0x00,0x00,0x00,0x27,0x84,0x8f,0x38,0x0c,0x00,0x1f,0x97,0x00,0x00,0x00,0x00, ++0x27,0x84,0x8d,0x20,0x0c,0x00,0x1b,0xa3,0x00,0x00,0x00,0x00,0x08,0x00,0x1f,0x03, ++0x00,0x00,0x00,0x00,0x8f,0x82,0x92,0x38,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x05, ++0x00,0x00,0x18,0x21,0x8f,0x82,0x8d,0x28,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x02, ++0x00,0x00,0x00,0x00,0x24,0x03,0x00,0x01,0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21, ++0x27,0xbd,0xff,0xe0,0x3c,0x06,0xb0,0x03,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10, ++0x34,0xc6,0x00,0x5f,0xaf,0xbf,0x00,0x18,0x90,0xc3,0x00,0x00,0x3c,0x07,0xb0,0x03, ++0x34,0xe7,0x00,0x5d,0x34,0x63,0x00,0x01,0x3c,0x09,0xb0,0x03,0x24,0x02,0x00,0x01, ++0xa0,0xc3,0x00,0x00,0x00,0x80,0x80,0x21,0xa0,0xe2,0x00,0x00,0x00,0xa0,0x88,0x21, ++0x35,0x29,0x00,0x5e,0x00,0xe0,0x40,0x21,0x24,0x04,0x00,0x01,0x91,0x22,0x00,0x00, ++0x91,0x03,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x83,0x00,0x03,0x30,0x42,0x00,0x01, ++0x14,0x40,0xff,0xfa,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x04,0x12,0x02,0x00,0x2c, ++0x24,0x05,0x0f,0x00,0x24,0x02,0x00,0x06,0x12,0x02,0x00,0x08,0x24,0x05,0x00,0x0f, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x02,0x00,0xa0,0x50,0x00,0x00,0x8f,0xbf,0x00,0x18, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x24,0x04,0x0c,0x04, ++0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x0f,0x24,0x04,0x0d,0x04,0x24,0x05,0x00,0x0f, ++0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x0f,0x24,0x04,0x08,0x80,0x24,0x05,0x1e,0x00, ++0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x0f,0x24,0x04,0x08,0x8c,0x24,0x05,0x0f,0x00, ++0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x0f,0x24,0x04,0x08,0x24,0x3c,0x05,0x00,0x30, ++0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x02,0x24,0x04,0x08,0x2c,0x3c,0x05,0x00,0x30, ++0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x02,0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0x30, ++0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x02,0x24,0x04,0x08,0x3c,0x3c,0x05,0x00,0x30, ++0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x02,0x08,0x00,0x1f,0x3d,0x3c,0x02,0xb0,0x03, ++0x24,0x04,0x08,0x8c,0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x04,0x24,0x04,0x08,0x80, ++0x24,0x05,0x1e,0x00,0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x04,0x24,0x04,0x0c,0x04, ++0x24,0x05,0x00,0x0f,0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x04,0x24,0x04,0x0d,0x04, ++0x24,0x05,0x00,0x0f,0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x04,0x24,0x04,0x08,0x24, ++0x3c,0x05,0x00,0x30,0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x03,0x24,0x04,0x08,0x2c, ++0x3c,0x05,0x00,0x30,0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x03,0x24,0x04,0x08,0x34, ++0x3c,0x05,0x00,0x30,0x0c,0x00,0x1b,0x29,0x24,0x06,0x00,0x02,0x3c,0x05,0x00,0x30, ++0x24,0x06,0x00,0x03,0x0c,0x00,0x1b,0x29,0x24,0x04,0x08,0x3c,0x02,0x20,0x20,0x21, ++0x24,0x05,0x00,0x14,0x0c,0x00,0x1b,0x6e,0x24,0x06,0x01,0x07,0x08,0x00,0x1f,0x3d, ++0x3c,0x02,0xb0,0x03,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x73,0x90,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x02,0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00, ++0xa3,0x80,0x87,0x6d,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0xa3,0x82,0x87,0x6d,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x00,0x00,0x80,0x70,0x21,0x34,0x63,0x00,0x20,0x24,0x42,0x7e,0x5c, ++0x3c,0x04,0xb0,0x03,0xac,0x62,0x00,0x00,0x34,0x84,0x00,0x30,0xad,0xc0,0x02,0xb8, ++0x8c,0x83,0x00,0x00,0x24,0x02,0x00,0xff,0xa5,0xc0,0x00,0x0a,0x00,0x00,0x30,0x21, ++0xa7,0x82,0x99,0x30,0x27,0x88,0x99,0x40,0xa5,0xc3,0x00,0x08,0x3c,0x07,0xb0,0x08, ++0x30,0xc2,0xff,0xff,0x00,0x02,0x20,0xc0,0x24,0xc3,0x00,0x01,0x00,0x82,0x10,0x21, ++0x00,0x60,0x30,0x21,0x00,0x02,0x10,0x80,0x30,0x63,0xff,0xff,0x00,0x48,0x10,0x21, ++0x00,0x87,0x20,0x21,0x28,0xc5,0x00,0xff,0xac,0x83,0x00,0x00,0x14,0xa0,0xff,0xf4, ++0xa4,0x43,0x00,0x00,0x3c,0x02,0xb0,0x08,0x34,0x03,0xff,0xff,0x25,0xc4,0x00,0x0c, ++0x24,0x0a,0x00,0x02,0x34,0x42,0x07,0xf8,0x3c,0x06,0xb0,0x03,0xa7,0x83,0xbd,0x1c, ++0xac,0x43,0x00,0x00,0xaf,0x84,0xbd,0x40,0x34,0xc6,0x00,0x64,0xa0,0x8a,0x00,0x18, ++0x94,0xc5,0x00,0x00,0x8f,0x82,0xbd,0x40,0x25,0xc4,0x00,0x30,0x24,0x08,0x00,0x03, ++0x3c,0x03,0xb0,0x03,0xa0,0x45,0x00,0x21,0x34,0x63,0x00,0x66,0xaf,0x84,0xbd,0x44, ++0xa0,0x88,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xbd,0x44,0x25,0xc4,0x00,0x54, ++0x25,0xc7,0x00,0x78,0xa0,0x45,0x00,0x21,0xaf,0x84,0xbd,0x48,0xa0,0x88,0x00,0x18, ++0x94,0x65,0x00,0x00,0x8f,0x82,0xbd,0x48,0x25,0xc8,0x00,0x9c,0x24,0x09,0x00,0x01, ++0xa0,0x45,0x00,0x21,0xaf,0x87,0xbd,0x4c,0xa0,0xea,0x00,0x18,0x94,0xc4,0x00,0x00, ++0x8f,0x82,0xbd,0x4c,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x62,0xa0,0x44,0x00,0x21, ++0xaf,0x88,0xbd,0x50,0xa1,0x09,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xbd,0x50, ++0x25,0xc4,0x00,0xc0,0x3c,0x06,0xb0,0x03,0xa0,0x45,0x00,0x21,0xaf,0x84,0xbd,0x54, ++0xa0,0x89,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xbd,0x54,0x25,0xc4,0x00,0xe4, ++0x34,0xc6,0x00,0x60,0xa0,0x45,0x00,0x21,0xaf,0x84,0xbd,0x58,0xa0,0x80,0x00,0x18, ++0x94,0xc5,0x00,0x00,0x8f,0x82,0xbd,0x58,0x25,0xc3,0x01,0x08,0x25,0xc7,0x01,0x2c, ++0xa0,0x45,0x00,0x21,0xaf,0x83,0xbd,0x5c,0xa0,0x60,0x00,0x18,0x94,0xc8,0x00,0x00, ++0x8f,0x82,0xbd,0x5c,0x25,0xc4,0x01,0x50,0x25,0xc5,0x01,0x74,0xa0,0x48,0x00,0x21, ++0x25,0xc6,0x01,0x98,0x25,0xc9,0x01,0xbc,0x25,0xca,0x01,0xe0,0x25,0xcb,0x02,0x04, ++0x25,0xcc,0x02,0x28,0x25,0xcd,0x02,0x4c,0x24,0x02,0x00,0x10,0x3c,0x03,0xb0,0x03, ++0xaf,0x87,0xbd,0x60,0x34,0x63,0x00,0x38,0xa0,0xe0,0x00,0x18,0xaf,0x84,0xbd,0x64, ++0xa0,0x80,0x00,0x18,0xaf,0x85,0xbd,0x68,0xa0,0xa0,0x00,0x18,0xaf,0x86,0xbd,0x6c, ++0xa0,0xc0,0x00,0x18,0xaf,0x89,0xbd,0x70,0xa1,0x20,0x00,0x18,0xaf,0x8a,0xbd,0x74, ++0xa1,0x40,0x00,0x18,0xaf,0x8b,0xbd,0x78,0xa1,0x60,0x00,0x18,0xaf,0x8c,0xbd,0x7c, ++0xa1,0x80,0x00,0x18,0xaf,0x8d,0xbd,0x80,0xa1,0xa2,0x00,0x18,0x94,0x64,0x00,0x00, ++0x8f,0x82,0xbd,0x80,0x25,0xc5,0x02,0x70,0x3c,0x03,0xb0,0x03,0xa0,0x44,0x00,0x21, ++0x24,0x02,0x00,0x11,0xaf,0x85,0xbd,0x84,0x34,0x63,0x00,0x6e,0xa0,0xa2,0x00,0x18, ++0x94,0x64,0x00,0x00,0x8f,0x82,0xbd,0x84,0x25,0xc5,0x02,0x94,0x3c,0x03,0xb0,0x03, ++0xa0,0x44,0x00,0x21,0x24,0x02,0x00,0x12,0xaf,0x85,0xbd,0x88,0x34,0x63,0x00,0x6c, ++0xa0,0xa2,0x00,0x18,0x94,0x64,0x00,0x00,0x8f,0x82,0xbd,0x88,0x24,0x05,0xff,0xff, ++0x24,0x07,0x00,0x01,0xa0,0x44,0x00,0x21,0x24,0x06,0x00,0x12,0x27,0x84,0xbd,0x40, ++0x8c,0x82,0x00,0x00,0x24,0xc6,0xff,0xff,0xa0,0x40,0x00,0x04,0x8c,0x83,0x00,0x00, ++0xa4,0x45,0x00,0x00,0xa4,0x45,0x00,0x02,0xa0,0x60,0x00,0x0a,0x8c,0x82,0x00,0x00, ++0xa4,0x65,0x00,0x06,0xa4,0x65,0x00,0x08,0xa0,0x40,0x00,0x10,0x8c,0x83,0x00,0x00, ++0xa4,0x45,0x00,0x0c,0xa4,0x45,0x00,0x0e,0xa0,0x60,0x00,0x12,0x8c,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0xa0,0x40,0x00,0x16,0x8c,0x83,0x00,0x00,0xa4,0x45,0x00,0x14, ++0xa0,0x67,0x00,0x17,0x8c,0x82,0x00,0x00,0x24,0x84,0x00,0x04,0xa0,0x40,0x00,0x20, ++0x04,0xc1,0xff,0xe7,0xac,0x40,0x00,0x1c,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x34,0x42,0x00,0x20,0x24,0x63,0x81,0x20, ++0xac,0x43,0x00,0x00,0x90,0x82,0x00,0x10,0x00,0x80,0x60,0x21,0x10,0x40,0x00,0x56, ++0x00,0x00,0x70,0x21,0x97,0x82,0x99,0x30,0x94,0x8a,0x00,0x0c,0x27,0x87,0x99,0x40, ++0x00,0x02,0x40,0xc0,0x01,0x02,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x47,0x10,0x21, ++0x90,0x8b,0x00,0x18,0xa4,0x4a,0x00,0x00,0x94,0x83,0x00,0x0e,0x39,0x64,0x00,0x10, ++0x2c,0x84,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x34,0x85,0x00,0x02, ++0x39,0x63,0x00,0x11,0x00,0x83,0x28,0x0b,0x34,0xa3,0x00,0x08,0x39,0x64,0x00,0x12, ++0x00,0x02,0x10,0x80,0x00,0xa4,0x18,0x0b,0x00,0x47,0x10,0x21,0x94,0x49,0x00,0x04, ++0x34,0x64,0x00,0x20,0x00,0x6b,0x20,0x0b,0x34,0x83,0x00,0x40,0x39,0x62,0x00,0x01, ++0x00,0x82,0x18,0x0b,0x00,0x09,0x30,0xc0,0x34,0x64,0x00,0x80,0x00,0xc9,0x28,0x21, ++0x39,0x62,0x00,0x02,0x00,0x60,0x68,0x21,0x00,0x82,0x68,0x0a,0x00,0x05,0x28,0x80, ++0x3c,0x02,0xb0,0x08,0x00,0xa7,0x28,0x21,0x00,0xc2,0x30,0x21,0x01,0x02,0x40,0x21, ++0x34,0x03,0xff,0xff,0x35,0xa4,0x01,0x00,0x39,0x62,0x00,0x03,0x2d,0x67,0x00,0x13, ++0xad,0x0a,0x00,0x00,0xa4,0xa3,0x00,0x00,0xac,0xc3,0x00,0x00,0xa7,0x89,0x99,0x30, ++0x10,0xe0,0x00,0x0f,0x00,0x82,0x68,0x0a,0x3c,0x03,0x80,0x01,0x00,0x0b,0x10,0x80, ++0x24,0x63,0x08,0xf0,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x60, ++0x94,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x14,0x00,0x00,0x02,0x74,0x03, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x3a,0x94,0x44,0x00,0x00,0x93,0x83,0x99,0x24, ++0x91,0x82,0x00,0x21,0x01,0xc4,0x20,0x21,0x91,0x85,0x00,0x10,0x00,0x04,0x24,0x00, ++0x00,0x62,0x18,0x21,0x00,0x04,0x74,0x03,0x00,0x6e,0x18,0x23,0x00,0x65,0x10,0x2a, ++0x00,0xa2,0x18,0x0a,0x00,0x0d,0x24,0x00,0x3c,0x02,0xb0,0x06,0x24,0x05,0xff,0xff, ++0x00,0x64,0x18,0x25,0x34,0x42,0x80,0x20,0xac,0x43,0x00,0x00,0xa5,0x85,0x00,0x0e, ++0xa1,0x80,0x00,0x10,0xa5,0x85,0x00,0x0c,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x3c,0x03,0xb0,0x03,0x08,0x00,0x20,0x8c,0x34,0x63,0x00,0x62,0x3c,0x03,0xb0,0x03, ++0x08,0x00,0x20,0x8c,0x34,0x63,0x00,0x64,0x3c,0x03,0xb0,0x03,0x08,0x00,0x20,0x8c, ++0x34,0x63,0x00,0x66,0x3c,0x03,0xb0,0x03,0x08,0x00,0x20,0x8c,0x34,0x63,0x00,0x38, ++0x3c,0x03,0xb0,0x03,0x08,0x00,0x20,0x8c,0x34,0x63,0x00,0x6e,0x3c,0x03,0xb0,0x03, ++0x08,0x00,0x20,0x8c,0x34,0x63,0x00,0x6c,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01, ++0x34,0x63,0x00,0x20,0x24,0x42,0x82,0xe8,0x00,0x05,0x28,0x40,0xac,0x62,0x00,0x00, ++0x00,0xa6,0x28,0x21,0x2c,0xe2,0x00,0x10,0x14,0x80,0x00,0x06,0x00,0x00,0x18,0x21, ++0x10,0x40,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0xe0,0x18,0x21,0x03,0xe0,0x00,0x08, ++0x00,0x60,0x10,0x21,0x24,0x02,0x00,0x20,0x10,0xe2,0x00,0x06,0x2c,0xe4,0x00,0x10, ++0x24,0xa2,0x00,0x01,0x10,0x80,0xff,0xf9,0x00,0x02,0x11,0x00,0x08,0x00,0x20,0xc7, ++0x00,0x47,0x18,0x21,0x08,0x00,0x20,0xc7,0x24,0xa3,0x00,0x50,0x27,0xbd,0xff,0xc8, ++0xaf,0xb4,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14, ++0xaf,0xbf,0x00,0x30,0xaf,0xb7,0x00,0x2c,0xaf,0xb6,0x00,0x28,0xaf,0xb5,0x00,0x24, ++0xaf,0xb0,0x00,0x10,0x00,0x80,0x90,0x21,0x84,0x84,0x00,0x08,0x3c,0x05,0xb0,0x03, ++0x3c,0x02,0x80,0x01,0x34,0xa5,0x00,0x20,0x24,0x42,0x83,0x4c,0x3c,0x03,0xb0,0x06, ++0x00,0x04,0x20,0x80,0xac,0xa2,0x00,0x00,0x00,0x83,0x20,0x21,0x3c,0x06,0xb0,0x06, ++0x8c,0x82,0x00,0x00,0x34,0xc6,0x80,0x24,0x8c,0x88,0x00,0x00,0x8c,0xc4,0x00,0x00, ++0x96,0x45,0x00,0x08,0x30,0x53,0xff,0xff,0x00,0x08,0x44,0x02,0x34,0x84,0x01,0x00, ++0x3c,0x02,0xb0,0x00,0x00,0x08,0x18,0xc0,0x00,0x13,0x3a,0x00,0xac,0xc4,0x00,0x00, ++0x00,0xe2,0x38,0x21,0xae,0x53,0x02,0xb8,0x00,0x68,0x18,0x21,0x24,0xa5,0x00,0x02, ++0x8c,0xf6,0x00,0x00,0x30,0xa5,0x01,0xff,0x8c,0xf5,0x00,0x04,0x27,0x86,0x99,0x40, ++0x00,0x03,0x18,0x80,0x00,0x13,0xa0,0xc0,0xa6,0x45,0x00,0x08,0x00,0x66,0x18,0x21, ++0x02,0x93,0x10,0x21,0x00,0x02,0x48,0x80,0x94,0x65,0x00,0x00,0x01,0x26,0x30,0x21, ++0x24,0x02,0xff,0xff,0x00,0x15,0x1a,0x02,0x27,0x84,0x99,0x50,0xa4,0xc2,0x00,0x02, ++0x30,0x63,0x00,0x1f,0x24,0x02,0x00,0x10,0x01,0x24,0x20,0x21,0xa4,0xc8,0x00,0x04, ++0x8c,0xf0,0x00,0x08,0xa6,0x43,0x00,0x06,0xa6,0x45,0x00,0x0a,0xa0,0x82,0x00,0x06, ++0x86,0x43,0x00,0x06,0x27,0x82,0x99,0x44,0x01,0x22,0x88,0x21,0x24,0x02,0x00,0x13, ++0x10,0x62,0x00,0xee,0xae,0x27,0x00,0x18,0x3c,0x03,0xb0,0x03,0x34,0x63,0x01,0x00, ++0xa6,0x40,0x00,0x02,0x3c,0x02,0xb0,0x03,0x90,0x64,0x00,0x00,0x34,0x42,0x01,0x08, ++0x8c,0x45,0x00,0x00,0x00,0x10,0x1b,0xc2,0x00,0x04,0x20,0x82,0x30,0x63,0x00,0x01, ++0xac,0xc5,0x00,0x08,0x10,0x60,0x00,0xc7,0x30,0x97,0x00,0x01,0x00,0x10,0x16,0x82, ++0x30,0x46,0x00,0x01,0x00,0x10,0x12,0x02,0x00,0x10,0x19,0xc2,0x00,0x10,0x26,0x02, ++0x00,0x10,0x2e,0x42,0x30,0x48,0x00,0x7f,0x24,0x02,0x00,0x01,0x30,0x71,0x00,0x01, ++0x30,0x84,0x00,0x01,0x10,0xc2,0x00,0xb3,0x30,0xa3,0x00,0x01,0x00,0x60,0x28,0x21, ++0x0c,0x00,0x20,0xba,0x01,0x00,0x38,0x21,0x02,0x93,0x18,0x21,0x00,0x03,0x18,0x80, ++0x2c,0x46,0x00,0x54,0x27,0x85,0x99,0x50,0x27,0x84,0x99,0x48,0x00,0x06,0x10,0x0a, ++0x00,0x65,0x28,0x21,0x26,0x26,0x00,0x02,0x00,0x64,0x18,0x21,0xa0,0xa2,0x00,0x02, ++0xa0,0x66,0x00,0x06,0xa0,0x62,0x00,0x07,0xa0,0xa2,0x00,0x01,0x02,0x93,0x28,0x21, ++0x00,0x05,0x28,0x80,0x27,0x82,0x99,0x44,0x00,0xa2,0x58,0x21,0x8d,0x64,0x00,0x18, ++0x00,0x10,0x15,0xc2,0x30,0x42,0x00,0x01,0x8c,0x83,0x00,0x0c,0x27,0x84,0x99,0x60, ++0x00,0xa4,0x48,0x21,0xa6,0x42,0x00,0x00,0xa6,0x56,0x00,0x04,0x8d,0x26,0x00,0x00, ++0x00,0x03,0x19,0x42,0x3c,0x02,0xff,0xef,0x34,0x42,0xff,0xff,0x30,0x63,0x00,0x01, ++0x00,0xc2,0x40,0x24,0x00,0x03,0x1d,0x00,0x01,0x03,0x40,0x25,0x00,0x08,0x15,0x02, ++0x00,0x10,0x34,0x42,0x00,0x10,0x3c,0x82,0x00,0x15,0x19,0x82,0x00,0x15,0x25,0x82, ++0x00,0x10,0x2c,0x02,0x30,0x42,0x00,0x01,0x30,0xcd,0x00,0x01,0x30,0x6c,0x00,0x01, ++0x30,0xe6,0x00,0x01,0x30,0x8a,0x00,0x03,0x32,0xb1,0x00,0x07,0x30,0xa5,0x00,0x01, ++0xad,0x28,0x00,0x00,0x10,0x40,0x00,0x0b,0x32,0x07,0x00,0x7f,0x8d,0x64,0x00,0x18, ++0x3c,0x03,0xff,0xf0,0x34,0x63,0xff,0xff,0x8c,0x82,0x00,0x0c,0x01,0x03,0x18,0x24, ++0x00,0x02,0x13,0x82,0x30,0x42,0x00,0x0f,0x00,0x02,0x14,0x00,0x00,0x62,0x18,0x25, ++0xad,0x23,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xc2,0x00,0x6a,0x00,0x00,0x00,0x00, ++0x15,0x80,0x00,0x03,0x00,0x00,0x00,0x00,0x15,0x40,0x00,0x5b,0x24,0x02,0x00,0x01, ++0x96,0x42,0x00,0x04,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x04,0xa6,0x42,0x00,0x04, ++0x00,0xa0,0x20,0x21,0x0c,0x00,0x20,0xba,0x01,0xa0,0x28,0x21,0x02,0x93,0x18,0x21, ++0x00,0x03,0x40,0x80,0x2c,0x45,0x00,0x54,0x27,0x84,0x99,0x50,0x01,0x04,0x20,0x21, ++0x00,0x05,0x10,0x0a,0xa0,0x82,0x00,0x00,0xa0,0x80,0x00,0x04,0xa0,0x80,0x00,0x05, ++0x96,0x43,0x00,0x04,0x27,0x82,0x99,0x40,0x01,0x02,0x10,0x21,0xa4,0x43,0x00,0x06, ++0x27,0x82,0x99,0x44,0x92,0x46,0x00,0x01,0x01,0x02,0x10,0x21,0x8c,0x45,0x00,0x18, ++0x27,0x83,0x99,0x60,0x01,0x03,0x18,0x21,0xa0,0x60,0x00,0x00,0xa0,0x86,0x00,0x07, ++0x94,0xa2,0x00,0x10,0x24,0x03,0x00,0x04,0x30,0x42,0x00,0x0f,0x10,0x43,0x00,0x36, ++0x24,0xa5,0x00,0x10,0x94,0xa3,0x00,0x16,0x27,0x87,0x99,0x58,0x01,0x07,0x10,0x21, ++0xa4,0x43,0x00,0x02,0x94,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01, ++0x14,0x40,0x00,0x24,0x02,0x93,0x20,0x21,0x94,0xa2,0x00,0x00,0x24,0x03,0x00,0xa4, ++0x30,0x42,0x00,0xff,0x10,0x43,0x00,0x1f,0x00,0x00,0x00,0x00,0x94,0xa2,0x00,0x00, ++0x24,0x03,0x00,0x88,0x30,0x42,0x00,0x88,0x10,0x43,0x00,0x14,0x02,0x93,0x18,0x21, ++0x27,0x84,0x99,0x60,0x00,0x03,0x18,0x80,0x00,0x64,0x18,0x21,0x8c,0x62,0x00,0x00, ++0x3c,0x04,0x00,0x80,0x00,0x44,0x10,0x25,0xac,0x62,0x00,0x00,0x02,0x93,0x10,0x21, ++0x00,0x02,0x10,0x80,0x00,0x47,0x10,0x21,0xa0,0x51,0x00,0x00,0x8f,0xbf,0x00,0x30, ++0x7b,0xb6,0x01,0x7c,0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc, ++0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0x94,0xa2,0x00,0x18, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x60,0x10,0x40,0xff,0xe9,0x02,0x93,0x18,0x21, ++0x02,0x93,0x20,0x21,0x27,0x82,0x99,0x60,0x00,0x04,0x20,0x80,0x00,0x82,0x20,0x21, ++0x8c,0x83,0x00,0x00,0x3c,0x02,0xff,0x7f,0x34,0x42,0xff,0xff,0x00,0x62,0x18,0x24, ++0x08,0x00,0x21,0xaf,0xac,0x83,0x00,0x00,0x27,0x87,0x99,0x58,0x01,0x07,0x10,0x21, ++0x08,0x00,0x21,0x99,0xa4,0x40,0x00,0x02,0x11,0x42,0x00,0x07,0x00,0x00,0x00,0x00, ++0x2d,0x42,0x00,0x02,0x14,0x40,0xff,0xa7,0x00,0xa0,0x20,0x21,0x96,0x42,0x00,0x04, ++0x08,0x00,0x21,0x77,0x24,0x42,0x00,0x0c,0x96,0x42,0x00,0x04,0x08,0x00,0x21,0x77, ++0x24,0x42,0x00,0x08,0x16,0xe6,0xff,0x96,0x3c,0x02,0xff,0xfb,0x8d,0x63,0x00,0x18, ++0x34,0x42,0xff,0xff,0x02,0x02,0x10,0x24,0xac,0x62,0x00,0x08,0x08,0x00,0x21,0x70, ++0x00,0x00,0x30,0x21,0x16,0xe6,0xff,0x4e,0x00,0x60,0x28,0x21,0x3c,0x02,0xfb,0xff, ++0x34,0x42,0xff,0xff,0x02,0x02,0x10,0x24,0xac,0xe2,0x00,0x08,0x08,0x00,0x21,0x2f, ++0x00,0x00,0x30,0x21,0x93,0x87,0xc4,0x54,0x00,0x10,0x1e,0x42,0x00,0x10,0x26,0x82, ++0x27,0x82,0x99,0x48,0x2c,0xe5,0x00,0x0c,0x01,0x22,0x48,0x21,0x30,0x63,0x00,0x01, ++0x30,0x86,0x00,0x01,0x14,0xa0,0x00,0x06,0x00,0xe0,0x40,0x21,0x00,0x03,0x10,0x40, ++0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0xe2,0x10,0x21,0x24,0x48,0x00,0x04, ++0x02,0x93,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x84,0x99,0x50,0x27,0x83,0x99,0x48, ++0x00,0x44,0x20,0x21,0x00,0x43,0x10,0x21,0xa1,0x28,0x00,0x07,0xa0,0x40,0x00,0x06, ++0xa0,0x80,0x00,0x02,0x08,0x00,0x21,0x3f,0xa0,0x80,0x00,0x01,0x24,0x02,0x00,0x01, ++0x00,0xe0,0x20,0x21,0x0c,0x00,0x01,0xc2,0xa6,0x42,0x00,0x02,0x8e,0x24,0x00,0x18, ++0x0c,0x00,0x05,0x39,0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xb3,0x00,0x00,0x00,0x00, ++0x30,0xa7,0xff,0xff,0x00,0x07,0x18,0xc0,0x00,0x67,0x18,0x21,0x3c,0x06,0xb0,0x03, ++0x3c,0x02,0x80,0x01,0x24,0x42,0x88,0x30,0x27,0x85,0x99,0x50,0x00,0x03,0x18,0x80, ++0x34,0xc6,0x00,0x20,0x00,0x65,0x18,0x21,0xac,0xc2,0x00,0x00,0x80,0x62,0x00,0x07, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x29,0x00,0x80,0x28,0x21,0x90,0x82,0x00,0x16, ++0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02,0x30,0x43,0x00,0x01,0x14,0x60,0x00,0x02, ++0xa0,0x82,0x00,0x16,0xa0,0x80,0x00,0x17,0x90,0xa2,0x00,0x04,0x3c,0x03,0xb0,0x03, ++0x27,0x86,0x99,0x40,0x14,0x40,0x00,0x06,0x34,0x63,0x00,0x20,0x24,0x02,0x00,0x01, ++0xa0,0xa2,0x00,0x04,0xa4,0xa7,0x00,0x02,0x03,0xe0,0x00,0x08,0xa4,0xa7,0x00,0x00, ++0x94,0xa4,0x00,0x02,0x3c,0x02,0x80,0x01,0x24,0x42,0xa0,0x30,0xac,0x62,0x00,0x00, ++0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21, ++0x94,0x62,0x00,0x04,0xa4,0x67,0x00,0x02,0x3c,0x03,0xb0,0x08,0x00,0x02,0x20,0xc0, ++0x00,0x82,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21,0x00,0x83,0x20,0x21, ++0xa4,0x47,0x00,0x00,0xac,0x87,0x00,0x00,0x90,0xa2,0x00,0x04,0xa4,0xa7,0x00,0x02, ++0x24,0x42,0x00,0x01,0x03,0xe0,0x00,0x08,0xa0,0xa2,0x00,0x04,0x90,0x82,0x00,0x16, ++0x24,0x85,0x00,0x06,0x34,0x42,0x00,0x01,0x30,0x43,0x00,0x02,0x14,0x60,0xff,0xda, ++0xa0,0x82,0x00,0x16,0x24,0x02,0x00,0x01,0x08,0x00,0x22,0x22,0xa0,0x82,0x00,0x17, ++0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x00,0x80,0x38,0x21,0x84,0x84,0x00,0x02, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x3c,0x0a,0xb0,0x06,0x34,0x63,0x00,0x20, ++0x24,0x42,0x89,0x30,0x3c,0x0b,0xb0,0x08,0x27,0x89,0x99,0x40,0x34,0x0c,0xff,0xff, ++0x35,0x4a,0x80,0x20,0x10,0x80,0x00,0x30,0xac,0x62,0x00,0x00,0x97,0x82,0x99,0x30, ++0x94,0xe6,0x02,0xba,0x00,0x02,0x18,0xc0,0x00,0x6b,0x28,0x21,0xac,0xa6,0x00,0x00, ++0x8c,0xe4,0x02,0xb8,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x04,0x10,0xc0, ++0x00,0x44,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x49,0x10,0x21,0x94,0x48,0x00,0x04, ++0x00,0x69,0x18,0x21,0xa4,0x66,0x00,0x00,0x00,0x08,0x28,0xc0,0x00,0xab,0x10,0x21, ++0xac,0x4c,0x00,0x00,0x8c,0xe4,0x02,0xb8,0x27,0x82,0x99,0x44,0x00,0xa8,0x28,0x21, ++0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21, ++0x8c,0x46,0x00,0x18,0x27,0x84,0x99,0x50,0x00,0x64,0x18,0x21,0x8c,0xc2,0x00,0x00, ++0x80,0x67,0x00,0x06,0x00,0x05,0x28,0x80,0x30,0x42,0xff,0xff,0x00,0x47,0x10,0x21, ++0x30,0x43,0x00,0xff,0x00,0x03,0x18,0x2b,0x00,0x02,0x12,0x02,0x00,0x43,0x10,0x21, ++0x3c,0x04,0x00,0x04,0x00,0xa9,0x28,0x21,0x00,0x44,0x10,0x25,0xa4,0xac,0x00,0x00, ++0xad,0x42,0x00,0x00,0xa7,0x88,0x99,0x30,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x84,0xe3,0x00,0x06,0x27,0x82,0xbd,0x40, ++0x94,0xe5,0x02,0xba,0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,0x8c,0x64,0x00,0x00, ++0x0c,0x00,0x22,0x0c,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0x86,0x00,0x00,0x00,0x00, ++0x94,0x88,0x00,0x00,0x00,0x80,0x58,0x21,0x27,0x8a,0x99,0x40,0x00,0x08,0x18,0xc0, ++0x00,0x68,0x18,0x21,0x3c,0x04,0xb0,0x03,0x00,0x03,0x18,0x80,0x3c,0x02,0x80,0x01, ++0x00,0x6a,0x18,0x21,0x34,0x84,0x00,0x20,0x24,0x42,0x8a,0x50,0x30,0xa5,0xff,0xff, ++0xac,0x82,0x00,0x00,0x94,0x67,0x00,0x02,0x11,0x05,0x00,0x35,0x24,0x04,0x00,0x01, ++0x91,0x66,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x86,0x10,0x2a,0x10,0x40,0x00,0x10, ++0x00,0xc0,0x48,0x21,0x3c,0x0d,0xb0,0x03,0x01,0x40,0x60,0x21,0x35,0xad,0x00,0x20, ++0x10,0xe5,0x00,0x0d,0x24,0x84,0x00,0x01,0x00,0x07,0x10,0xc0,0x00,0x47,0x10,0x21, ++0x00,0x02,0x10,0x80,0x01,0x20,0x30,0x21,0x00,0x4a,0x10,0x21,0x00,0x86,0x18,0x2a, ++0x00,0xe0,0x40,0x21,0x94,0x47,0x00,0x02,0x14,0x60,0xff,0xf5,0x00,0x00,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x10,0x21,0x00,0x08,0x20,0xc0,0x00,0x88,0x20,0x21, ++0x24,0xc2,0xff,0xff,0x00,0x04,0x20,0x80,0xa1,0x62,0x00,0x04,0x00,0x8c,0x20,0x21, ++0x94,0x83,0x00,0x04,0x00,0x07,0x10,0xc0,0x00,0x47,0x10,0x21,0x00,0x02,0x10,0x80, ++0x00,0x4c,0x10,0x21,0x00,0x03,0x28,0xc0,0x94,0x46,0x00,0x02,0x00,0xa3,0x18,0x21, ++0x00,0x03,0x18,0x80,0x00,0x6c,0x18,0x21,0xa4,0x66,0x00,0x00,0xa4,0x86,0x00,0x02, ++0x95,0x64,0x00,0x02,0x3c,0x03,0xb0,0x08,0x3c,0x02,0x80,0x01,0x00,0xa3,0x28,0x21, ++0x24,0x42,0xa0,0x30,0xad,0xa2,0x00,0x00,0x10,0x87,0x00,0x03,0xac,0xa6,0x00,0x00, ++0x03,0xe0,0x00,0x08,0x24,0x02,0x00,0x01,0x08,0x00,0x22,0xd4,0xa5,0x68,0x00,0x02, ++0x91,0x62,0x00,0x04,0xa5,0x67,0x00,0x00,0x24,0x42,0xff,0xff,0x30,0x43,0x00,0xff, ++0x14,0x60,0xff,0xf7,0xa1,0x62,0x00,0x04,0x24,0x02,0xff,0xff,0x08,0x00,0x22,0xd4, ++0xa5,0x62,0x00,0x02,0x00,0x05,0x40,0xc0,0x01,0x05,0x30,0x21,0x27,0xbd,0xff,0xd8, ++0x00,0x06,0x30,0x80,0x27,0x82,0x99,0x44,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14, ++0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb0,0x00,0x10,0x00,0xc2,0x10,0x21, ++0x8c,0x47,0x00,0x18,0x00,0xa0,0x90,0x21,0x3c,0x02,0x80,0x01,0x3c,0x05,0xb0,0x03, ++0x34,0xa5,0x00,0x20,0x24,0x42,0x8b,0x84,0xac,0xa2,0x00,0x00,0x27,0x83,0x99,0x50, ++0x00,0xc3,0x30,0x21,0x8c,0xe2,0x00,0x00,0x80,0xc5,0x00,0x06,0x00,0x80,0x88,0x21, ++0x30,0x42,0xff,0xff,0x00,0x45,0x10,0x21,0x30,0x43,0x00,0xff,0x10,0x60,0x00,0x02, ++0x00,0x02,0x12,0x02,0x24,0x42,0x00,0x01,0x30,0x53,0x00,0xff,0x01,0x12,0x10,0x21, ++0x00,0x02,0x10,0x80,0x27,0x83,0x99,0x50,0x00,0x43,0x10,0x21,0x80,0x44,0x00,0x07, ++0x00,0x00,0x00,0x00,0x10,0x80,0x00,0x4b,0x26,0x24,0x00,0x06,0x32,0x50,0xff,0xff, ++0x02,0x20,0x20,0x21,0x0c,0x00,0x22,0x94,0x02,0x00,0x28,0x21,0x92,0x22,0x00,0x10, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x2e,0x3c,0x03,0xb0,0x08,0x3c,0x09,0x80,0x01, ++0x27,0x88,0x99,0x40,0xa6,0x32,0x00,0x0c,0x00,0x10,0x20,0xc0,0x00,0x90,0x20,0x21, ++0x00,0x04,0x20,0x80,0x00,0x88,0x20,0x21,0x94,0x82,0x00,0x04,0x3c,0x03,0xb0,0x08, ++0x3c,0x07,0xb0,0x03,0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21,0x00,0x02,0x10,0x80, ++0x00,0x48,0x10,0x21,0x00,0xa3,0x28,0x21,0x25,0x26,0xa0,0x30,0x34,0x03,0xff,0xff, ++0x34,0xe7,0x00,0x20,0xac,0xe6,0x00,0x00,0xa4,0x83,0x00,0x02,0xa4,0x43,0x00,0x00, ++0xac,0xa3,0x00,0x00,0x92,0x22,0x00,0x10,0x92,0x23,0x00,0x0a,0xa6,0x32,0x00,0x0e, ++0x02,0x62,0x10,0x21,0x14,0x60,0x00,0x05,0xa2,0x22,0x00,0x10,0x92,0x22,0x00,0x16, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfe,0xa2,0x22,0x00,0x16,0x92,0x22,0x00,0x04, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x92,0x22,0x00,0x16, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfd,0xa2,0x22,0x00,0x16,0x8f,0xbf,0x00,0x20, ++0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28, ++0x96,0x22,0x00,0x0e,0x27,0x88,0x99,0x40,0x00,0x02,0x20,0xc0,0x00,0x82,0x20,0x21, ++0x00,0x04,0x20,0x80,0x00,0x88,0x20,0x21,0x94,0x82,0x00,0x04,0x3c,0x06,0xb0,0x03, ++0x3c,0x09,0x80,0x01,0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21,0x00,0x02,0x10,0x80, ++0x00,0xa3,0x28,0x21,0x00,0x48,0x10,0x21,0x34,0xc6,0x00,0x20,0x25,0x23,0xa0,0x30, ++0xac,0xc3,0x00,0x00,0xa4,0x50,0x00,0x00,0xac,0xb0,0x00,0x00,0x08,0x00,0x23,0x12, ++0xa4,0x90,0x00,0x02,0x08,0x00,0x23,0x09,0x32,0x50,0xff,0xff,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x01,0x24,0x42,0x8d,0x4c,0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00, ++0x90,0x82,0x00,0x04,0x97,0xaa,0x00,0x12,0x00,0x80,0x60,0x21,0x30,0xa8,0xff,0xff, ++0x00,0x4a,0x20,0x23,0x34,0x09,0xff,0xff,0x30,0xcf,0xff,0xff,0x30,0xee,0xff,0xff, ++0x11,0x09,0x00,0x73,0xa1,0x84,0x00,0x04,0x00,0x0e,0xc0,0xc0,0x00,0x08,0x10,0xc0, ++0x00,0x48,0x10,0x21,0x03,0x0e,0x20,0x21,0x27,0x8d,0x99,0x40,0x00,0x04,0x20,0x80, ++0x00,0x02,0x10,0x80,0x00,0x4d,0x10,0x21,0x00,0x8d,0x20,0x21,0x94,0x86,0x00,0x02, ++0x94,0x43,0x00,0x04,0x3c,0x19,0x80,0x01,0xa4,0x46,0x00,0x02,0x00,0x03,0x28,0xc0, ++0x00,0xa3,0x18,0x21,0x94,0x87,0x00,0x02,0x3c,0x02,0xb0,0x08,0x00,0x03,0x18,0x80, ++0x00,0xa2,0x28,0x21,0x00,0x6d,0x18,0x21,0x27,0x22,0xa0,0x30,0x3c,0x01,0xb0,0x03, ++0xac,0x22,0x00,0x20,0xa4,0x66,0x00,0x00,0x10,0xe9,0x00,0x57,0xac,0xa6,0x00,0x00, ++0x01,0xe0,0x30,0x21,0x11,0x40,0x00,0x1d,0x00,0x00,0x48,0x21,0x01,0x40,0x38,0x21, ++0x27,0x8b,0x99,0x44,0x27,0x8a,0x99,0x50,0x00,0x06,0x40,0xc0,0x01,0x06,0x18,0x21, ++0x00,0x03,0x18,0x80,0x00,0x6b,0x10,0x21,0x8c,0x44,0x00,0x18,0x00,0x6a,0x18,0x21, ++0x80,0x65,0x00,0x06,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0xff,0xff, ++0x00,0x45,0x10,0x21,0x30,0x44,0x00,0xff,0x00,0x02,0x12,0x02,0x01,0x22,0x18,0x21, ++0x24,0x62,0x00,0x01,0x14,0x80,0x00,0x02,0x30,0x49,0x00,0xff,0x30,0x69,0x00,0xff, ++0x01,0x06,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x4d,0x10,0x21,0x24,0xe7,0xff,0xff, ++0x94,0x46,0x00,0x02,0x14,0xe0,0xff,0xe9,0x00,0x06,0x40,0xc0,0x91,0x82,0x00,0x10, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x20,0x3c,0x06,0xb0,0x03,0xa5,0x8f,0x00,0x0c, ++0x03,0x0e,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x8d,0x20,0x21,0x94,0x82,0x00,0x04, ++0x3c,0x03,0xb0,0x08,0x3c,0x07,0xb0,0x03,0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21, ++0x00,0x02,0x10,0x80,0x00,0x4d,0x10,0x21,0x00,0xa3,0x28,0x21,0x27,0x26,0xa0,0x30, ++0x34,0x03,0xff,0xff,0x34,0xe7,0x00,0x20,0xac,0xe6,0x00,0x00,0xa4,0x83,0x00,0x02, ++0xa4,0x43,0x00,0x00,0xac,0xa3,0x00,0x00,0x91,0x82,0x00,0x10,0x91,0x83,0x00,0x04, ++0xa5,0x8e,0x00,0x0e,0x01,0x22,0x10,0x21,0x14,0x60,0x00,0x05,0xa1,0x82,0x00,0x10, ++0x91,0x82,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfd,0xa1,0x82,0x00,0x16, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x95,0x82,0x00,0x0e,0x3c,0x03,0xb0,0x08, ++0x00,0x02,0x20,0xc0,0x00,0x82,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x8d,0x20,0x21, ++0x94,0x82,0x00,0x04,0x34,0xc6,0x00,0x20,0x27,0x27,0xa0,0x30,0x00,0x02,0x28,0xc0, ++0x00,0xa2,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0xa3,0x28,0x21,0x00,0x4d,0x10,0x21, ++0xac,0xc7,0x00,0x00,0xa4,0x8f,0x00,0x02,0xa4,0x4f,0x00,0x00,0xac,0xaf,0x00,0x00, ++0x08,0x00,0x23,0xa1,0x03,0x0e,0x20,0x21,0x08,0x00,0x23,0x7c,0xa5,0x88,0x00,0x02, ++0x00,0x0e,0xc0,0xc0,0x03,0x0e,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x8d,0x99,0x40, ++0x00,0x4d,0x10,0x21,0x94,0x43,0x00,0x02,0x30,0x84,0x00,0xff,0x14,0x80,0x00,0x05, ++0xa5,0x83,0x00,0x00,0x24,0x02,0xff,0xff,0x3c,0x19,0x80,0x01,0x08,0x00,0x23,0x7c, ++0xa5,0x82,0x00,0x02,0x08,0x00,0x23,0x7c,0x3c,0x19,0x80,0x01,0x3c,0x08,0xb0,0x03, ++0x3c,0x02,0x80,0x01,0x27,0xbd,0xff,0x78,0x35,0x08,0x00,0x20,0x24,0x42,0x8f,0x8c, ++0xaf,0xb2,0x00,0x68,0xaf,0xb1,0x00,0x64,0xaf,0xb0,0x00,0x60,0xad,0x02,0x00,0x00, ++0xaf,0xbf,0x00,0x84,0xaf,0xbe,0x00,0x80,0xaf,0xb7,0x00,0x7c,0xaf,0xb6,0x00,0x78, ++0xaf,0xb5,0x00,0x74,0xaf,0xb4,0x00,0x70,0xaf,0xb3,0x00,0x6c,0xaf,0xa4,0x00,0x88, ++0x90,0x83,0x00,0x0a,0x27,0x82,0xbd,0x40,0xaf,0xa6,0x00,0x90,0x00,0x03,0x18,0x80, ++0x00,0x62,0x18,0x21,0x8c,0x63,0x00,0x00,0xaf,0xa7,0x00,0x94,0x27,0x86,0x99,0x44, ++0xaf,0xa3,0x00,0x1c,0x94,0x63,0x00,0x14,0x30,0xb1,0xff,0xff,0x24,0x08,0x00,0x01, ++0x00,0x03,0x20,0xc0,0xaf,0xa3,0x00,0x18,0x00,0x83,0x18,0x21,0xaf,0xa4,0x00,0x54, ++0x00,0x03,0x18,0x80,0x27,0x84,0x99,0x50,0x00,0x64,0x20,0x21,0x80,0x82,0x00,0x06, ++0x00,0x66,0x18,0x21,0x8c,0x66,0x00,0x18,0x24,0x42,0x00,0x02,0x00,0x02,0x1f,0xc2, ++0x8c,0xc4,0x00,0x08,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40, ++0x00,0x04,0x2f,0xc2,0x00,0x04,0x1c,0x82,0x00,0xc2,0x38,0x21,0x00,0x04,0x24,0x42, ++0x8f,0xa2,0x00,0x1c,0x30,0x63,0x00,0x01,0x30,0x84,0x00,0x01,0xaf,0xa5,0x00,0x3c, ++0xaf,0xa3,0x00,0x34,0xaf,0xa4,0x00,0x38,0xaf,0xa0,0x00,0x40,0xaf,0xa0,0x00,0x44, ++0xaf,0xa0,0x00,0x50,0xaf,0xa8,0x00,0x20,0x80,0x42,0x00,0x12,0x8f,0xb2,0x00,0x18, ++0xaf,0xa2,0x00,0x28,0x8c,0xd0,0x00,0x0c,0x14,0xa0,0x01,0xda,0x00,0x60,0x30,0x21, ++0x00,0x10,0x10,0x82,0x30,0x45,0x00,0x07,0x10,0xa0,0x00,0x11,0xaf,0xa0,0x00,0x30, ++0x8f,0xa4,0x00,0x98,0x27,0x82,0x86,0x30,0x00,0x04,0x18,0x40,0x00,0x62,0x18,0x21, ++0x24,0xa2,0x00,0x05,0x8f,0xa5,0x00,0x20,0x94,0x64,0x00,0x00,0x00,0x45,0x10,0x04, ++0x00,0x44,0x00,0x1a,0x14,0x80,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0d, ++0x00,0x00,0x10,0x12,0x24,0x42,0x00,0x10,0x30,0x42,0xff,0xfc,0xaf,0xa2,0x00,0x30, ++0x8f,0xa3,0x00,0x18,0x8f,0xa4,0x00,0x28,0x34,0x02,0xff,0xff,0xaf,0xa0,0x00,0x2c, ++0xaf,0xa2,0x00,0x48,0xaf,0xa3,0x00,0x4c,0x00,0x60,0xf0,0x21,0x00,0x00,0xb8,0x21, ++0x18,0x80,0x00,0x4e,0xaf,0xa0,0x00,0x24,0x00,0x11,0x89,0x02,0xaf,0xb1,0x00,0x58, ++0x00,0x80,0xa8,0x21,0x00,0x12,0x10,0xc0,0x00,0x52,0x20,0x21,0x00,0x04,0x20,0x80, ++0x00,0x40,0xa0,0x21,0x27,0x82,0x99,0x58,0x00,0x82,0x10,0x21,0x94,0x43,0x00,0x02, ++0x8f,0xa6,0x00,0x58,0x27,0x85,0x99,0x40,0x00,0x03,0x19,0x02,0x00,0x66,0x18,0x23, ++0x30,0x63,0x0f,0xff,0x00,0x85,0x20,0x21,0x28,0x62,0x00,0x20,0x94,0x96,0x00,0x02, ++0x10,0x40,0x01,0xa1,0x28,0x62,0x00,0x40,0x8f,0xa8,0x00,0x90,0x00,0x00,0x00,0x00, ++0x00,0x68,0x10,0x06,0x30,0x43,0x00,0x01,0x24,0x02,0x00,0x01,0x10,0x62,0x01,0x7b, ++0x3c,0x02,0xb0,0x03,0x8f,0xa6,0x00,0x88,0x34,0x42,0x01,0x04,0x84,0xc5,0x00,0x0c, ++0x02,0x92,0x18,0x21,0x94,0x46,0x00,0x00,0x00,0x05,0x20,0xc0,0x00,0x85,0x20,0x21, ++0x00,0x03,0x18,0x80,0x27,0x82,0x99,0x50,0x27,0x85,0x99,0x48,0x00,0x65,0x28,0x21, ++0x00,0x62,0x18,0x21,0x80,0x71,0x00,0x05,0x80,0x73,0x00,0x04,0x8f,0xa3,0x00,0x88, ++0x30,0xd0,0xff,0xff,0x00,0x10,0x3a,0x03,0x32,0x08,0x00,0xff,0x27,0x82,0x99,0x60, ++0x00,0x04,0x20,0x80,0x80,0xa6,0x00,0x06,0x00,0x82,0x20,0x21,0xa4,0x67,0x00,0x44, ++0xa4,0x68,0x00,0x46,0x8c,0x84,0x00,0x00,0x38,0xc6,0x00,0x00,0x01,0x00,0x80,0x21, ++0x00,0x04,0x15,0x02,0x30,0x42,0x00,0x01,0x10,0x40,0x00,0x03,0x00,0xe6,0x80,0x0a, ++0x00,0x04,0x14,0x02,0x30,0x50,0x00,0x0f,0x12,0x20,0x01,0x50,0x02,0x40,0x20,0x21, ++0x02,0x71,0x10,0x21,0x00,0x50,0x10,0x2a,0x14,0x40,0x00,0xed,0x02,0x92,0x10,0x21, ++0x93,0x82,0x94,0x51,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0xe0, ++0x02,0x92,0x28,0x21,0x26,0xe2,0x00,0x01,0x30,0x57,0xff,0xff,0x02,0x40,0xf0,0x21, ++0x26,0xb5,0xff,0xff,0x16,0xa0,0xff,0xb7,0x02,0xc0,0x90,0x21,0x16,0xe0,0x00,0xd0, ++0x00,0x00,0x00,0x00,0x8f,0xa3,0x00,0x98,0x00,0x00,0x00,0x00,0x2c,0x62,0x00,0x10, ++0x10,0x40,0x00,0x2e,0x00,0x00,0x00,0x00,0x8f,0xa4,0x00,0x24,0x00,0x00,0x00,0x00, ++0x18,0x80,0x00,0x2a,0x24,0x03,0x00,0x01,0x8f,0xa5,0x00,0x1c,0x27,0x84,0x99,0x44, ++0x94,0xb2,0x00,0x14,0xa0,0xa3,0x00,0x12,0x8f,0xa6,0x00,0x3c,0x00,0x12,0x10,0xc0, ++0x00,0x52,0x10,0x21,0x00,0x02,0x80,0x80,0x27,0x82,0x99,0x50,0x02,0x02,0x10,0x21, ++0x80,0x43,0x00,0x06,0x02,0x04,0x20,0x21,0x8c,0x85,0x00,0x18,0x24,0x63,0x00,0x02, ++0x00,0x03,0x17,0xc2,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x43,0x00,0x03,0x18,0x40, ++0x14,0xc0,0x00,0x0e,0x00,0xa3,0x38,0x21,0x27,0x82,0x99,0x40,0x02,0x02,0x10,0x21, ++0x94,0x43,0x00,0x06,0x8f,0xa8,0x00,0x1c,0x24,0x02,0x00,0x01,0xa5,0x03,0x00,0x1a, ++0x7b,0xbe,0x04,0x3c,0x7b,0xb6,0x03,0xfc,0x7b,0xb4,0x03,0xbc,0x7b,0xb2,0x03,0x7c, ++0x7b,0xb0,0x03,0x3c,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x88,0x8f,0xa4,0x00,0x98, ++0x8f,0xa5,0x00,0x38,0x8f,0xa6,0x00,0x34,0xaf,0xa0,0x00,0x10,0x0c,0x00,0x10,0x97, ++0xaf,0xa0,0x00,0x14,0x08,0x00,0x24,0xae,0x00,0x00,0x00,0x00,0x8f,0xa3,0x00,0x44, ++0x93,0x82,0x87,0x6d,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x61,0x30,0x69,0x00,0x03, ++0x8f,0xa4,0x00,0x24,0x8f,0xa5,0x00,0x28,0x00,0x00,0x00,0x00,0x00,0x85,0x10,0x2a, ++0x10,0x40,0x00,0x8f,0x00,0x00,0x00,0x00,0x8f,0xa6,0x00,0x1c,0x00,0x00,0x00,0x00, ++0x90,0xc4,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x83,0x00,0xff,0x00,0xa3,0x10,0x2a, ++0x10,0x40,0x00,0x87,0x00,0x00,0x00,0x00,0x8f,0xa8,0x00,0x24,0x00,0x00,0x00,0x00, ++0x11,0x00,0x00,0x83,0x00,0x65,0x10,0x23,0x00,0xa8,0x18,0x23,0x00,0x62,0x10,0x2a, ++0x14,0x40,0x00,0x7d,0x30,0x63,0x00,0xff,0x00,0x85,0x10,0x23,0x30,0x42,0x00,0xff, ++0xaf,0xa2,0x00,0x50,0x8f,0xa2,0x00,0x50,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x73, ++0x00,0x00,0xa8,0x21,0x27,0x8c,0x99,0x40,0x3c,0x0b,0x80,0xff,0x24,0x10,0x00,0x04, ++0x27,0x91,0x99,0x44,0x35,0x6b,0xff,0xff,0x3c,0x0d,0x7f,0x00,0x27,0x8e,0x99,0x50, ++0x01,0x80,0x78,0x21,0x00,0x12,0x30,0xc0,0x00,0xd2,0x10,0x21,0x00,0x02,0x10,0x80, ++0x00,0x4c,0x10,0x21,0x94,0x42,0x00,0x06,0x8f,0xa3,0x00,0x2c,0x8f,0xa4,0x00,0x30, ++0xaf,0xa2,0x00,0x44,0x8f,0xa5,0x00,0x44,0x30,0x49,0x00,0x03,0x02,0x09,0x10,0x23, ++0x30,0x42,0x00,0x03,0x00,0xa2,0x10,0x21,0x8f,0xa8,0x00,0x30,0x24,0x42,0x00,0x04, ++0x30,0x42,0xff,0xff,0x00,0x64,0x38,0x21,0x01,0x02,0x28,0x23,0x00,0x62,0x18,0x21, ++0x00,0x48,0x10,0x2b,0x10,0x40,0x00,0x52,0x00,0x00,0x20,0x21,0x30,0xe7,0xff,0xff, ++0x30,0xa4,0xff,0xff,0xaf,0xa7,0x00,0x2c,0x00,0xd2,0x10,0x21,0x00,0x02,0x10,0x80, ++0x00,0x51,0x18,0x21,0x8c,0x65,0x00,0x18,0x00,0x04,0x25,0x80,0x00,0x8d,0x20,0x24, ++0x8c,0xa8,0x00,0x04,0x00,0x4e,0x18,0x21,0x00,0x4f,0x50,0x21,0x01,0x0b,0x40,0x24, ++0x01,0x04,0x40,0x25,0xac,0xa8,0x00,0x04,0x8f,0xa4,0x00,0x98,0x8f,0xa2,0x00,0x50, ++0x26,0xb5,0x00,0x01,0xa0,0x64,0x00,0x00,0x8c,0xa4,0x00,0x08,0x00,0x00,0x00,0x00, ++0x04,0x81,0x00,0x0c,0x02,0xa2,0x30,0x2a,0x80,0x62,0x00,0x06,0x00,0x00,0x00,0x00, ++0x24,0x42,0x00,0x02,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43, ++0x00,0x02,0x10,0x40,0x00,0xa2,0x38,0x21,0x8f,0xa5,0x00,0x40,0x00,0x00,0x00,0x00, ++0xa4,0xe5,0x00,0x00,0x95,0x52,0x00,0x02,0x14,0xc0,0xff,0xc7,0x00,0x12,0x30,0xc0, ++0x8f,0xa4,0x00,0x24,0x8f,0xa5,0x00,0x50,0x8f,0xa6,0x00,0x1c,0x8f,0xa3,0x00,0x2c, ++0x00,0x85,0x80,0x21,0xa0,0xd0,0x00,0x12,0x00,0x09,0x10,0x23,0x30,0x42,0x00,0x03, ++0x8f,0xa8,0x00,0x88,0x00,0x62,0x10,0x23,0xa4,0xc2,0x00,0x1a,0x85,0x03,0x00,0x0c, ++0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80, ++0x27,0x83,0x99,0x44,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x18,0x00,0x00,0x00,0x00, ++0x8c,0x83,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10,0x14,0x60,0xff,0x74, ++0x02,0x00,0x10,0x21,0x8f,0xa3,0x00,0x54,0x8f,0xa4,0x00,0x18,0x8f,0xa5,0x00,0x24, ++0x00,0x64,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x99,0x58,0x00,0x43,0x10,0x21, ++0x90,0x44,0x00,0x00,0x10,0xa0,0x00,0x03,0x00,0x00,0x30,0x21,0x08,0x00,0x24,0xb4, ++0x02,0x00,0x10,0x21,0x93,0x82,0x80,0x10,0x00,0x00,0x28,0x21,0x00,0x00,0x38,0x21, ++0x0c,0x00,0x29,0x0b,0xaf,0xa2,0x00,0x10,0x08,0x00,0x24,0xb4,0x02,0x00,0x10,0x21, ++0x30,0x63,0xff,0xff,0x08,0x00,0x25,0x06,0xaf,0xa3,0x00,0x2c,0x8f,0xa8,0x00,0x44, ++0x08,0x00,0x25,0x28,0x31,0x09,0x00,0x03,0x08,0x00,0x24,0xe1,0xaf,0xa3,0x00,0x50, ++0x8f,0xa6,0x00,0x44,0xaf,0xa0,0x00,0x50,0x08,0x00,0x25,0x28,0x30,0xc9,0x00,0x03, ++0x8f,0xa5,0x00,0x48,0x8f,0xa6,0x00,0x4c,0x8f,0xa4,0x00,0x1c,0x03,0xc0,0x38,0x21, ++0x0c,0x00,0x23,0x53,0xaf,0xb7,0x00,0x10,0x08,0x00,0x24,0x91,0x00,0x00,0x00,0x00, ++0x00,0x05,0x28,0x80,0x27,0x82,0x99,0x40,0x00,0xa2,0x28,0x21,0x00,0x00,0x20,0x21, ++0x0c,0x00,0x01,0x49,0x00,0x00,0x00,0x00,0x08,0x00,0x24,0x8a,0x26,0xe2,0x00,0x01, ++0x00,0x02,0x80,0x80,0x27,0x83,0x99,0x50,0x8f,0xa4,0x00,0x1c,0x02,0x03,0x18,0x21, ++0x26,0x31,0x00,0x01,0x02,0x40,0x28,0x21,0x0c,0x00,0x26,0x5b,0xa0,0x71,0x00,0x05, ++0x14,0x40,0xff,0x13,0x00,0x00,0x00,0x00,0x16,0xe0,0x00,0x4d,0x03,0xc0,0x38,0x21, ++0x8f,0xa4,0x00,0x24,0x8f,0xa5,0x00,0x20,0x24,0x02,0x00,0x01,0x24,0x84,0x00,0x01, ++0xaf,0xb2,0x00,0x48,0xaf,0xb6,0x00,0x4c,0x02,0xc0,0xf0,0x21,0x10,0xa2,0x00,0x41, ++0xaf,0xa4,0x00,0x24,0x27,0x82,0x99,0x40,0x02,0x02,0x10,0x21,0x94,0x42,0x00,0x06, ++0x8f,0xa4,0x00,0x30,0xaf,0xa0,0x00,0x20,0xaf,0xa2,0x00,0x44,0x30,0x49,0x00,0x03, ++0x8f,0xa8,0x00,0x44,0x00,0x09,0x10,0x23,0x30,0x42,0x00,0x03,0x01,0x02,0x10,0x21, ++0x24,0x42,0x00,0x04,0x30,0x42,0xff,0xff,0x00,0x44,0x18,0x2b,0x10,0x60,0x00,0x2b, ++0x00,0x00,0x00,0x00,0x8f,0xa5,0x00,0x2c,0x00,0x82,0x10,0x23,0x00,0xa4,0x18,0x21, ++0x30,0x63,0xff,0xff,0x30,0x44,0xff,0xff,0xaf,0xa3,0x00,0x2c,0x02,0x92,0x28,0x21, ++0x00,0x05,0x28,0x80,0x27,0x82,0x99,0x44,0x00,0xa2,0x10,0x21,0x8c,0x46,0x00,0x18, ++0x3c,0x03,0x80,0xff,0x3c,0x02,0x7f,0x00,0x8c,0xc8,0x00,0x04,0x00,0x04,0x25,0x80, ++0x34,0x63,0xff,0xff,0x00,0x82,0x20,0x24,0x01,0x03,0x40,0x24,0x01,0x04,0x40,0x25, ++0xac,0xc8,0x00,0x04,0x8f,0xa8,0x00,0x98,0x27,0x82,0x99,0x50,0x00,0xa2,0x10,0x21, ++0xa0,0x48,0x00,0x00,0x8c,0xc4,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x04,0x27,0xc2, ++0x10,0x80,0xfe,0xdb,0xaf,0xa4,0x00,0x3c,0x80,0x42,0x00,0x06,0x00,0x00,0x00,0x00, ++0x24,0x42,0x00,0x02,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43, ++0x00,0x02,0x10,0x40,0x00,0xc2,0x38,0x21,0x8f,0xa2,0x00,0x40,0x00,0x00,0x00,0x00, ++0xa4,0xe2,0x00,0x00,0x08,0x00,0x24,0x8d,0x26,0xb5,0xff,0xff,0x8f,0xa6,0x00,0x2c, ++0x00,0x00,0x20,0x21,0x00,0xc2,0x10,0x21,0x30,0x42,0xff,0xff,0x08,0x00,0x25,0x9b, ++0xaf,0xa2,0x00,0x2c,0x8f,0xa6,0x00,0x1c,0x08,0x00,0x25,0x85,0xa4,0xd2,0x00,0x14, ++0x8f,0xa5,0x00,0x48,0x8f,0xa6,0x00,0x4c,0x8f,0xa4,0x00,0x1c,0x0c,0x00,0x23,0x53, ++0xaf,0xb7,0x00,0x10,0x08,0x00,0x25,0x7c,0x00,0x00,0xb8,0x21,0x0c,0x00,0x1a,0x11, ++0x00,0x00,0x28,0x21,0x94,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0x63,0x08,0x00, ++0xa4,0x43,0x00,0x00,0x08,0x00,0x24,0x81,0x02,0x71,0x10,0x21,0x02,0x92,0x18,0x21, ++0x00,0x03,0x80,0x80,0x27,0x82,0x99,0x44,0x02,0x02,0x10,0x21,0x8c,0x44,0x00,0x18, ++0x00,0x00,0x00,0x00,0x8c,0x83,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10, ++0x10,0x60,0x00,0x09,0x24,0x06,0x00,0x01,0x93,0x82,0x94,0x51,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0x01,0x10,0x40,0xfe,0xa3,0x3c,0x04,0x00,0x80,0x27,0x85,0x99,0x40, ++0x08,0x00,0x25,0x6c,0x02,0x05,0x28,0x21,0x27,0x83,0x99,0x58,0x27,0x82,0x99,0x50, ++0x02,0x03,0x18,0x21,0x02,0x02,0x10,0x21,0x90,0x64,0x00,0x00,0x90,0x45,0x00,0x05, ++0x93,0x83,0x80,0x10,0x00,0x00,0x38,0x21,0x0c,0x00,0x29,0x0b,0xaf,0xa3,0x00,0x10, ++0x08,0x00,0x25,0xe2,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x04,0x00,0x00,0x00,0x00, ++0x8f,0xa4,0x00,0x94,0x08,0x00,0x24,0x59,0x00,0x64,0x10,0x06,0x08,0x00,0x24,0x5a, ++0x00,0x00,0x18,0x21,0x8f,0xa4,0x00,0x98,0x8f,0xa5,0x00,0x38,0xaf,0xa0,0x00,0x10, ++0x0c,0x00,0x10,0x97,0xaf,0xa8,0x00,0x14,0x30,0x42,0xff,0xff,0x08,0x00,0x24,0x24, ++0xaf,0xa2,0x00,0x40,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe0, ++0x34,0x42,0x00,0x20,0x24,0x63,0x98,0x14,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10, ++0xaf,0xbf,0x00,0x18,0xac,0x43,0x00,0x00,0x90,0x82,0x00,0x0a,0x00,0x80,0x80,0x21, ++0x14,0x40,0x00,0x45,0x00,0x00,0x88,0x21,0x92,0x02,0x00,0x04,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x3c,0x00,0x00,0x00,0x00,0x12,0x20,0x00,0x18,0x00,0x00,0x00,0x00, ++0x92,0x02,0x00,0x16,0x92,0x05,0x00,0x0a,0x30,0x42,0x00,0xfc,0x10,0xa0,0x00,0x03, ++0xa2,0x02,0x00,0x16,0x34,0x42,0x00,0x01,0xa2,0x02,0x00,0x16,0x92,0x04,0x00,0x04, ++0x00,0x00,0x00,0x00,0x30,0x83,0x00,0xff,0x10,0x60,0x00,0x05,0x00,0x00,0x00,0x00, ++0x92,0x02,0x00,0x16,0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02,0xa2,0x02,0x00,0x16, ++0x10,0x60,0x00,0x0a,0x00,0x00,0x00,0x00,0x14,0xa0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x96,0x02,0x00,0x00,0xa2,0x00,0x00,0x17,0xa6,0x02,0x00,0x14,0x8f,0xbf,0x00,0x18, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x14,0x80,0x00,0x05, ++0x24,0x02,0x00,0x01,0x96,0x03,0x00,0x06,0xa2,0x02,0x00,0x17,0x08,0x00,0x26,0x2f, ++0xa6,0x03,0x00,0x14,0x96,0x04,0x00,0x00,0x96,0x05,0x00,0x06,0x27,0x86,0x99,0x40, ++0x00,0x04,0x10,0xc0,0x00,0x05,0x18,0xc0,0x00,0x44,0x10,0x21,0x00,0x65,0x18,0x21, ++0x00,0x02,0x10,0x80,0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,0x00,0x46,0x10,0x21, ++0x8c,0x65,0x00,0x08,0x8c,0x44,0x00,0x08,0x0c,0x00,0x1a,0x02,0x00,0x00,0x00,0x00, ++0x30,0x43,0x00,0xff,0x10,0x60,0x00,0x04,0xa2,0x02,0x00,0x17,0x96,0x02,0x00,0x06, ++0x08,0x00,0x26,0x2f,0xa6,0x02,0x00,0x14,0x96,0x02,0x00,0x00,0x08,0x00,0x26,0x2f, ++0xa6,0x02,0x00,0x14,0x96,0x05,0x00,0x00,0x0c,0x00,0x26,0x5b,0x02,0x00,0x20,0x21, ++0x08,0x00,0x26,0x16,0x02,0x22,0x88,0x21,0x94,0x85,0x00,0x06,0x0c,0x00,0x26,0x5b, ++0x00,0x00,0x00,0x00,0x08,0x00,0x26,0x12,0x00,0x40,0x88,0x21,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,0x24,0x42,0x99,0x6c,0x27,0xbd,0xff,0xf0, ++0xac,0x62,0x00,0x00,0x00,0x00,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x10, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,0x24,0x42,0x99,0x90, ++0xac,0x62,0x00,0x00,0x90,0x89,0x00,0x0a,0x00,0x80,0x30,0x21,0x11,0x20,0x00,0x05, ++0x00,0xa0,0x50,0x21,0x90,0x82,0x00,0x17,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x1b, ++0x00,0x00,0x00,0x00,0x90,0xc7,0x00,0x04,0x00,0x00,0x00,0x00,0x10,0xe0,0x00,0x1b, ++0x00,0x00,0x00,0x00,0x94,0xc8,0x00,0x00,0x27,0x83,0x99,0x40,0x93,0x85,0x94,0x50, ++0x00,0x08,0x10,0xc0,0x00,0x48,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21, ++0x8c,0x44,0x00,0x08,0x00,0xe5,0x28,0x2b,0x10,0xa0,0x00,0x06,0x01,0x44,0x18,0x23, ++0x8f,0x82,0x94,0x68,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x2b,0x10,0x40,0x00,0x05, ++0x00,0x00,0x00,0x00,0x24,0x03,0x00,0x10,0xa4,0xc8,0x00,0x14,0x03,0xe0,0x00,0x08, ++0x00,0x60,0x10,0x21,0x11,0x20,0x00,0x05,0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x06, ++0x24,0x03,0x00,0x08,0x08,0x00,0x26,0x87,0xa4,0xc2,0x00,0x14,0x08,0x00,0x26,0x87, ++0x00,0x00,0x18,0x21,0x27,0xbd,0xff,0xc8,0xaf,0xb5,0x00,0x2c,0xaf,0xb4,0x00,0x28, ++0xaf,0xb3,0x00,0x24,0xaf,0xb0,0x00,0x18,0xaf,0xbf,0x00,0x30,0xaf,0xb2,0x00,0x20, ++0xaf,0xb1,0x00,0x1c,0x94,0x91,0x00,0x06,0x00,0x80,0xa0,0x21,0x3c,0x02,0x80,0x01, ++0x3c,0x04,0xb0,0x03,0x00,0x11,0xa8,0xc0,0x34,0x84,0x00,0x20,0x24,0x42,0x9a,0x44, ++0x02,0xb1,0x48,0x21,0xac,0x82,0x00,0x00,0x00,0x09,0x48,0x80,0x24,0x03,0x00,0x01, ++0x27,0x82,0x99,0x50,0xa2,0x83,0x00,0x12,0x01,0x22,0x10,0x21,0x27,0x84,0x99,0x44, ++0x01,0x24,0x20,0x21,0x80,0x48,0x00,0x06,0x8c,0x8a,0x00,0x18,0x27,0x83,0x99,0x60, ++0x01,0x23,0x48,0x21,0x8d,0x24,0x00,0x00,0x25,0x08,0x00,0x02,0x8d,0x42,0x00,0x00, ++0x8d,0x49,0x00,0x04,0x00,0x08,0x17,0xc2,0x8d,0x43,0x00,0x08,0x01,0x02,0x40,0x21, ++0x00,0x04,0x25,0xc2,0x00,0x08,0x40,0x43,0x30,0x84,0x00,0x01,0x00,0x03,0x1f,0xc2, ++0x00,0x08,0x40,0x40,0x00,0xe0,0x80,0x21,0x00,0x64,0x18,0x24,0x00,0x09,0x49,0x42, ++0x01,0x48,0x10,0x21,0x00,0xa0,0x98,0x21,0x00,0xa0,0x20,0x21,0x00,0x40,0x38,0x21, ++0x02,0x00,0x28,0x21,0x14,0x60,0x00,0x19,0x31,0x29,0x00,0x01,0x94,0x42,0x00,0x00, ++0x02,0xb1,0x88,0x21,0x02,0x00,0x28,0x21,0x00,0x11,0x88,0x80,0x27,0x90,0x99,0x40, ++0x02,0x30,0x80,0x21,0x96,0x03,0x00,0x06,0x30,0x52,0xff,0xff,0x02,0x60,0x20,0x21, ++0x00,0x60,0x30,0x21,0xa6,0x83,0x00,0x1a,0x27,0x82,0x99,0x48,0x0c,0x00,0x10,0x70, ++0x02,0x22,0x88,0x21,0x00,0x52,0x10,0x21,0x96,0x03,0x00,0x06,0xa6,0x22,0x00,0x04, ++0x8f,0xbf,0x00,0x30,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc, ++0x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0xaf,0xa9,0x00,0x10, ++0x0c,0x00,0x10,0x97,0xaf,0xa0,0x00,0x14,0x08,0x00,0x26,0xc5,0x02,0xb1,0x88,0x21, ++0x27,0xbd,0xff,0xc0,0xaf,0xbe,0x00,0x38,0xaf,0xb7,0x00,0x34,0xaf,0xb6,0x00,0x30, ++0xaf,0xb5,0x00,0x2c,0xaf,0xb3,0x00,0x24,0xaf,0xb1,0x00,0x1c,0xaf,0xbf,0x00,0x3c, ++0xaf,0xb4,0x00,0x28,0xaf,0xb2,0x00,0x20,0xaf,0xb0,0x00,0x18,0x94,0x90,0x00,0x00, ++0x3c,0x08,0xb0,0x03,0x35,0x08,0x00,0x20,0x00,0x10,0x10,0xc0,0x00,0x50,0x18,0x21, ++0x00,0x40,0x88,0x21,0x3c,0x02,0x80,0x01,0x00,0x03,0x48,0x80,0x24,0x42,0x9b,0x80, ++0x00,0x80,0x98,0x21,0x27,0x84,0x99,0x50,0x01,0x24,0x20,0x21,0x93,0xb7,0x00,0x53, ++0xad,0x02,0x00,0x00,0x80,0x83,0x00,0x06,0x27,0x82,0x99,0x44,0x01,0x22,0x10,0x21, ++0x8c,0x44,0x00,0x18,0x24,0x63,0x00,0x02,0x00,0x03,0x17,0xc2,0x8c,0x88,0x00,0x08, ++0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x43,0x00,0x03,0x18,0x40,0xaf,0xa7,0x00,0x4c, ++0x2c,0xa2,0x00,0x10,0x00,0xa0,0xa8,0x21,0x00,0x83,0x50,0x21,0x00,0x08,0x47,0xc2, ++0x00,0xc0,0x58,0x21,0x00,0x00,0xb0,0x21,0x8c,0x92,0x00,0x0c,0x14,0x40,0x00,0x13, ++0x00,0x00,0xf0,0x21,0x92,0x67,0x00,0x04,0x24,0x14,0x00,0x01,0x12,0x87,0x00,0x10, ++0x02,0x30,0x10,0x21,0x27,0x83,0x99,0x58,0x01,0x23,0x18,0x21,0x80,0x64,0x00,0x00, ++0x27,0x83,0xbe,0xb0,0x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80, ++0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x04, ++0x00,0x00,0x00,0x00,0x10,0x80,0x00,0x23,0x00,0x00,0x00,0x00,0x02,0x30,0x10,0x21, ++0x00,0x02,0x80,0x80,0x24,0x04,0x00,0x01,0x27,0x83,0x99,0x60,0xa2,0x64,0x00,0x12, ++0x02,0x03,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x15,0xc2, ++0x30,0x42,0x00,0x01,0x01,0x02,0x10,0x24,0x14,0x40,0x00,0x0e,0x02,0xa0,0x20,0x21, ++0x27,0x82,0x99,0x40,0x02,0x02,0x10,0x21,0x94,0x43,0x00,0x06,0x00,0x00,0x00,0x00, ++0xa6,0x63,0x00,0x1a,0x94,0x42,0x00,0x06,0x7b,0xbe,0x01,0xfc,0x7b,0xb6,0x01,0xbc, ++0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x40,0x8f,0xa5,0x00,0x4c,0x01,0x60,0x30,0x21,0x01,0x40,0x38,0x21, ++0xaf,0xa0,0x00,0x10,0x0c,0x00,0x10,0x97,0xaf,0xa0,0x00,0x14,0x08,0x00,0x27,0x2c, ++0x00,0x00,0x00,0x00,0x27,0x83,0x99,0x60,0x01,0x23,0x18,0x21,0x8c,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x02,0x15,0xc2,0x30,0x42,0x00,0x01,0x01,0x02,0x10,0x24, ++0x14,0x40,0x00,0xaf,0x00,0xa0,0x20,0x21,0x32,0x4f,0x00,0x03,0x00,0x12,0x10,0x82, ++0x25,0xe3,0x00,0x0d,0x30,0x45,0x00,0x07,0x00,0x74,0x78,0x04,0x10,0xa0,0x00,0x0e, ++0x00,0x00,0x90,0x21,0x27,0x82,0x86,0x30,0x00,0x15,0x18,0x40,0x00,0x62,0x18,0x21, ++0x94,0x64,0x00,0x00,0x24,0xa2,0x00,0x05,0x00,0x54,0x10,0x04,0x00,0x44,0x00,0x1a, ++0x14,0x80,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0d,0x00,0x00,0x10,0x12, ++0x24,0x42,0x00,0x10,0x30,0x52,0xff,0xfc,0x02,0x30,0x10,0x21,0x27,0x83,0x99,0x50, ++0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x03,0x00,0x00,0x00,0x00, ++0x30,0x83,0x00,0xff,0x2c,0x62,0x00,0x0c,0x14,0x40,0x00,0x04,0x2c,0x62,0x00,0x19, ++0x30,0x82,0x00,0x0f,0x24,0x43,0x00,0x0c,0x2c,0x62,0x00,0x19,0x10,0x40,0x00,0x19, ++0x24,0x0e,0x00,0x20,0x24,0x62,0xff,0xe9,0x2c,0x42,0x00,0x02,0x14,0x40,0x00,0x15, ++0x24,0x0e,0x00,0x10,0x24,0x62,0xff,0xeb,0x2c,0x42,0x00,0x02,0x14,0x40,0x00,0x11, ++0x24,0x0e,0x00,0x08,0x24,0x02,0x00,0x14,0x10,0x62,0x00,0x0e,0x24,0x0e,0x00,0x02, ++0x24,0x62,0xff,0xef,0x2c,0x42,0x00,0x03,0x14,0x40,0x00,0x0a,0x24,0x0e,0x00,0x10, ++0x24,0x62,0xff,0xf1,0x2c,0x42,0x00,0x02,0x14,0x40,0x00,0x06,0x24,0x0e,0x00,0x08, ++0x24,0x62,0xff,0xf3,0x2c,0x42,0x00,0x02,0x24,0x0e,0x00,0x04,0x24,0x03,0x00,0x02, ++0x00,0x62,0x70,0x0a,0x30,0xe2,0x00,0xff,0x00,0x00,0x48,0x21,0x00,0x00,0x68,0x21, ++0x10,0x40,0x00,0x6d,0x00,0x00,0x58,0x21,0x3c,0x14,0x80,0xff,0x27,0x99,0x99,0x40, ++0x01,0xf2,0xc0,0x23,0x36,0x94,0xff,0xff,0x01,0xc9,0x10,0x2a,0x14,0x40,0x00,0x64, ++0x24,0x03,0x00,0x04,0x00,0x10,0x28,0xc0,0x00,0xb0,0x10,0x21,0x00,0x02,0x10,0x80, ++0x00,0x59,0x10,0x21,0x94,0x56,0x00,0x06,0x00,0x00,0x00,0x00,0x32,0xcc,0x00,0x03, ++0x00,0x6c,0x10,0x23,0x30,0x42,0x00,0x03,0x02,0xc2,0x10,0x21,0x24,0x42,0x00,0x04, ++0x30,0x51,0xff,0xff,0x02,0x32,0x18,0x2b,0x10,0x60,0x00,0x4d,0x01,0xf1,0x10,0x23, ++0x02,0x51,0x10,0x23,0x01,0x78,0x18,0x2b,0x10,0x60,0x00,0x34,0x30,0x44,0xff,0xff, ++0x29,0x22,0x00,0x40,0x10,0x40,0x00,0x31,0x01,0x72,0x18,0x21,0x25,0x22,0x00,0x01, ++0x00,0x02,0x16,0x00,0x00,0x02,0x4e,0x03,0x00,0xb0,0x10,0x21,0x00,0x02,0x30,0x80, ++0x27,0x82,0x99,0x44,0x30,0x6b,0xff,0xff,0x00,0xc2,0x18,0x21,0x8c,0x67,0x00,0x18, ++0x00,0x04,0x25,0x80,0x3c,0x03,0x7f,0x00,0x8c,0xe2,0x00,0x04,0x00,0x83,0x20,0x24, ++0x27,0x83,0x99,0x50,0x00,0x54,0x10,0x24,0x00,0xc3,0x28,0x21,0x00,0x44,0x10,0x25, ++0xac,0xe2,0x00,0x04,0x16,0xe0,0x00,0x02,0xa0,0xb5,0x00,0x00,0xa0,0xb5,0x00,0x03, ++0x27,0x84,0x99,0x60,0x00,0xc4,0x18,0x21,0x8c,0x62,0x00,0x00,0x8c,0xe8,0x00,0x08, ++0x00,0x02,0x15,0xc2,0x00,0x08,0x47,0xc2,0x30,0x42,0x00,0x01,0x01,0x02,0x10,0x24, ++0x10,0x40,0x00,0x0a,0x00,0x00,0x00,0x00,0x80,0xa2,0x00,0x06,0x00,0x00,0x00,0x00, ++0x24,0x42,0x00,0x02,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43, ++0x00,0x02,0x10,0x40,0x00,0xe2,0x50,0x21,0xa5,0x5e,0x00,0x00,0x92,0x62,0x00,0x04, ++0x25,0xad,0x00,0x01,0x27,0x84,0x99,0x40,0x00,0xc4,0x18,0x21,0x01,0xa2,0x10,0x2a, ++0x94,0x70,0x00,0x02,0x14,0x40,0xff,0xb8,0x00,0x00,0x00,0x00,0x96,0x63,0x00,0x14, ++0x00,0x0c,0x10,0x23,0xa2,0x69,0x00,0x12,0x30,0x42,0x00,0x03,0x01,0x62,0x10,0x23, ++0x00,0x03,0x80,0xc0,0x8f,0xa5,0x00,0x4c,0x30,0x4b,0xff,0xff,0x02,0x03,0x80,0x21, ++0x27,0x82,0x99,0x48,0x00,0x10,0x80,0x80,0xa6,0x6b,0x00,0x1a,0x02,0xa0,0x20,0x21, ++0x01,0x60,0x30,0x21,0x01,0x60,0x88,0x21,0x0c,0x00,0x10,0x70,0x02,0x02,0x80,0x21, ++0x00,0x5e,0x10,0x21,0xa6,0x02,0x00,0x04,0x08,0x00,0x27,0x32,0x02,0x20,0x10,0x21, ++0x01,0x62,0x10,0x2b,0x10,0x40,0xff,0xe9,0x00,0x00,0x20,0x21,0x29,0x22,0x00,0x40, ++0x10,0x40,0xff,0xe6,0x01,0x71,0x18,0x21,0x08,0x00,0x27,0xa8,0x25,0x22,0x00,0x01, ++0x08,0x00,0x27,0xd7,0x32,0xcc,0x00,0x03,0x08,0x00,0x27,0xd7,0x00,0x00,0x60,0x21, ++0x8f,0xa5,0x00,0x4c,0x01,0x40,0x38,0x21,0xaf,0xa0,0x00,0x10,0x0c,0x00,0x10,0x97, ++0xaf,0xb4,0x00,0x14,0x92,0x67,0x00,0x04,0x08,0x00,0x27,0x4a,0x30,0x5e,0xff,0xff, ++0x30,0x84,0xff,0xff,0x00,0x04,0x30,0xc0,0x00,0xc4,0x20,0x21,0x00,0x04,0x20,0x80, ++0x27,0x82,0x99,0x40,0x3c,0x03,0xb0,0x08,0x30,0xa5,0xff,0xff,0x00,0x82,0x20,0x21, ++0x00,0xc3,0x30,0x21,0xac,0xc5,0x00,0x00,0x03,0xe0,0x00,0x08,0xa4,0x85,0x00,0x00, ++0x30,0x84,0xff,0xff,0x00,0x04,0x30,0xc0,0x00,0xc4,0x30,0x21,0x27,0x88,0x99,0x40, ++0x00,0x06,0x30,0x80,0x00,0xc8,0x30,0x21,0x94,0xc3,0x00,0x04,0x3c,0x02,0xb0,0x08, ++0x3c,0x07,0xb0,0x03,0x00,0x03,0x20,0xc0,0x00,0x83,0x18,0x21,0x00,0x03,0x18,0x80, ++0x00,0x82,0x20,0x21,0x3c,0x02,0x80,0x01,0x30,0xa5,0xff,0xff,0x00,0x68,0x18,0x21, ++0x34,0xe7,0x00,0x20,0x24,0x42,0xa0,0x30,0xac,0xe2,0x00,0x00,0xa4,0xc5,0x00,0x02, ++0xa4,0x65,0x00,0x00,0x03,0xe0,0x00,0x08,0xac,0x85,0x00,0x00,0x30,0x84,0xff,0xff, ++0x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x27,0x89,0x99,0x40,0x00,0x02,0x10,0x80, ++0x00,0x49,0x10,0x21,0x97,0x83,0x99,0x30,0x94,0x4a,0x00,0x04,0x3c,0x02,0xb0,0x08, ++0x00,0x03,0x38,0xc0,0x00,0x0a,0x40,0xc0,0x00,0xe3,0x18,0x21,0x01,0x0a,0x28,0x21, ++0x00,0xe2,0x38,0x21,0x01,0x02,0x40,0x21,0x00,0x03,0x18,0x80,0x00,0x05,0x28,0x80, ++0x3c,0x06,0xb0,0x03,0x3c,0x02,0x80,0x01,0x00,0xa9,0x28,0x21,0x00,0x69,0x18,0x21, ++0x34,0xc6,0x00,0x20,0x34,0x09,0xff,0xff,0x24,0x42,0xa0,0x8c,0xac,0xc2,0x00,0x00, ++0xa4,0x64,0x00,0x00,0xac,0xe4,0x00,0x00,0xa4,0xa9,0x00,0x00,0xad,0x09,0x00,0x00, ++0xa7,0x8a,0x99,0x30,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,0x24,0x42,0xa1,0x0c,0x3c,0x04,0xb0,0x03, ++0xac,0x62,0x00,0x00,0x34,0x84,0x01,0x10,0x8c,0x82,0x00,0x00,0x97,0x83,0x87,0x74, ++0x30,0x42,0xff,0xff,0x10,0x62,0x00,0x16,0x24,0x0a,0x00,0x01,0xa7,0x82,0x87,0x74, ++0xaf,0x80,0xbd,0x90,0x00,0x40,0x28,0x21,0x24,0x06,0x00,0x01,0x27,0x84,0xbd,0x94, ++0x25,0x43,0xff,0xff,0x00,0x66,0x10,0x04,0x00,0xa2,0x10,0x24,0x14,0x40,0x00,0x07, ++0x00,0x00,0x00,0x00,0x8c,0x83,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x66,0x10,0x04, ++0x00,0xa2,0x10,0x24,0x38,0x42,0x00,0x00,0x01,0x42,0x18,0x0a,0x25,0x4a,0x00,0x01, ++0x2d,0x42,0x00,0x14,0xac,0x83,0x00,0x00,0x14,0x40,0xff,0xf1,0x24,0x84,0x00,0x04, ++0x3c,0x0b,0xb0,0x03,0x00,0x00,0x50,0x21,0x3c,0x0c,0x80,0x00,0x27,0x89,0xbd,0xe0, ++0x35,0x6b,0x01,0x20,0x8d,0x68,0x00,0x00,0x8d,0x23,0x00,0x04,0x01,0x0c,0x10,0x24, ++0x00,0x02,0x17,0xc2,0x11,0x03,0x00,0x37,0xa1,0x22,0x00,0xdc,0xa1,0x20,0x00,0xd5, ++0xa1,0x20,0x00,0xd6,0x01,0x20,0x30,0x21,0x00,0x00,0x38,0x21,0x00,0x00,0x28,0x21, ++0x01,0x20,0x20,0x21,0x00,0xa8,0x10,0x06,0x30,0x42,0x00,0x01,0x10,0xe0,0x00,0x10, ++0xa0,0x82,0x00,0x0a,0x90,0x82,0x00,0x07,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x31, ++0x24,0xa2,0xff,0xff,0xa0,0x82,0x00,0x08,0x90,0x82,0x00,0x0a,0x00,0x00,0x00,0x00, ++0x10,0x40,0x00,0x09,0x00,0x00,0x00,0x00,0x90,0x83,0x00,0x08,0x00,0x00,0x00,0x00, ++0x00,0x03,0x10,0x40,0x00,0x43,0x10,0x21,0x00,0x46,0x10,0x21,0xa0,0x45,0x00,0x09, ++0x90,0x82,0x00,0x0a,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x07,0x00,0x00,0x00,0x00, ++0x14,0xe0,0x00,0x04,0x00,0x00,0x00,0x00,0xa0,0xc5,0x00,0xd5,0x24,0x07,0x00,0x01, ++0xa0,0x85,0x00,0x08,0xa0,0xc5,0x00,0xd6,0x24,0xa5,0x00,0x01,0x2c,0xa2,0x00,0x1c, ++0x14,0x40,0xff,0xe0,0x24,0x84,0x00,0x03,0x90,0xc4,0x00,0xd5,0x00,0x00,0x28,0x21, ++0x00,0xa4,0x10,0x2b,0x10,0x40,0x00,0x0b,0x00,0x00,0x00,0x00,0x00,0xc0,0x18,0x21, ++0xa0,0x64,0x00,0x08,0x90,0xc2,0x00,0xd5,0x24,0xa5,0x00,0x01,0xa0,0x62,0x00,0x09, ++0x90,0xc4,0x00,0xd5,0x00,0x00,0x00,0x00,0x00,0xa4,0x10,0x2b,0x14,0x40,0xff,0xf8, ++0x24,0x63,0x00,0x03,0x25,0x4a,0x00,0x01,0x2d,0x42,0x00,0x08,0xad,0x28,0x00,0x04, ++0x25,0x6b,0x00,0x04,0x14,0x40,0xff,0xbf,0x25,0x29,0x00,0xec,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x90,0x82,0x00,0x05,0x08,0x00,0x28,0x7e,0xa0,0x82,0x00,0x08, ++0x97,0x85,0x94,0x5a,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x27,0xbd,0xff,0xe8, ++0x34,0x63,0x00,0x20,0x24,0x42,0xa2,0xc0,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14, ++0xac,0x62,0x00,0x00,0x30,0x90,0x00,0xff,0x00,0x05,0x28,0x42,0x00,0x00,0x48,0x21, ++0x27,0x8f,0xbd,0xe4,0x00,0x00,0x50,0x21,0x00,0x00,0x58,0x21,0x27,0x98,0xbe,0xc4, ++0x27,0x99,0xbe,0xc0,0x27,0x8e,0xbe,0xbe,0x27,0x8c,0xbd,0xe8,0x27,0x8d,0xbe,0x40, ++0x27,0x88,0xbe,0xb8,0x00,0x0a,0x18,0x80,0x01,0x6f,0x10,0x21,0xac,0x40,0x00,0x00, ++0xac,0x45,0x00,0x58,0x00,0x6e,0x20,0x21,0x00,0x78,0x10,0x21,0xa1,0x00,0xff,0xfc, ++0xad,0x00,0x00,0x00,0xa1,0x00,0x00,0x04,0xa1,0x00,0x00,0x05,0xad,0x00,0xff,0xf8, ++0x00,0x79,0x18,0x21,0x24,0x06,0x00,0x01,0x24,0xc6,0xff,0xff,0xa0,0x80,0x00,0x00, ++0xa4,0x60,0x00,0x00,0xac,0x40,0x00,0x00,0x24,0x63,0x00,0x02,0x24,0x42,0x00,0x04, ++0x04,0xc1,0xff,0xf9,0x24,0x84,0x00,0x01,0x00,0x0a,0x10,0x80,0x00,0x4d,0x20,0x21, ++0x00,0x00,0x30,0x21,0x00,0x4c,0x18,0x21,0x27,0x87,0x87,0x78,0x8c,0xe2,0x00,0x00, ++0x24,0xe7,0x00,0x04,0xac,0x82,0x00,0x00,0xa0,0x66,0x00,0x00,0xa0,0x66,0x00,0x01, ++0x24,0xc6,0x00,0x01,0x28,0xc2,0x00,0x1c,0xa0,0x60,0x00,0x02,0x24,0x84,0x00,0x04, ++0x14,0x40,0xff,0xf6,0x24,0x63,0x00,0x03,0x25,0x29,0x00,0x01,0x29,0x22,0x00,0x08, ++0x25,0x4a,0x00,0x3b,0x25,0x08,0x00,0xec,0x14,0x40,0xff,0xd6,0x25,0x6b,0x00,0xec, ++0xa7,0x80,0x87,0x74,0x00,0x00,0x48,0x21,0x27,0x83,0xbd,0x90,0xac,0x69,0x00,0x00, ++0x25,0x29,0x00,0x01,0x29,0x22,0x00,0x0c,0x14,0x40,0xff,0xfc,0x24,0x63,0x00,0x04, ++0x0c,0x00,0x28,0x43,0x00,0x00,0x00,0x00,0x2e,0x04,0x00,0x14,0x27,0x83,0xbd,0xe0, ++0x24,0x09,0x00,0x07,0x10,0x80,0x00,0x0a,0x00,0x00,0x00,0x00,0x90,0x62,0x00,0xd5, ++0x25,0x29,0xff,0xff,0xa0,0x62,0x00,0x00,0x05,0x21,0xff,0xfa,0x24,0x63,0x00,0xec, ++0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18, ++0x90,0x62,0x00,0xd6,0x08,0x00,0x29,0x01,0x25,0x29,0xff,0xff,0x30,0x84,0x00,0xff, ++0x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x23, ++0x00,0x02,0x10,0x80,0x27,0x83,0xbd,0xe0,0x00,0x43,0x60,0x21,0x3c,0x04,0xb0,0x03, ++0x3c,0x02,0x80,0x01,0x34,0x84,0x00,0x20,0x24,0x42,0xa4,0x2c,0x30,0xc6,0x00,0xff, ++0x93,0xaa,0x00,0x13,0x30,0xa5,0x00,0xff,0x30,0xe7,0x00,0xff,0xac,0x82,0x00,0x00, ++0x10,0xc0,0x00,0xb8,0x25,0x8f,0x00,0xd0,0x91,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x24,0x42,0xff,0xfc,0x2c,0x43,0x00,0x18,0x10,0x60,0x00,0x9b,0x3c,0x03,0x80,0x01, ++0x00,0x02,0x10,0x80,0x24,0x63,0x09,0x3c,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x2c, ++0x14,0x40,0x00,0x1c,0x00,0x00,0x00,0x00,0x10,0xa0,0x00,0x17,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x11,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02, ++0x10,0xa2,0x00,0x0c,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x06, ++0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x00,0x00,0x00,0x00,0x24,0x42,0xff,0xe0, ++0x03,0xe0,0x00,0x08,0xad,0x82,0x00,0xd0,0x8d,0x82,0x00,0xd0,0x08,0x00,0x29,0x3c, ++0x24,0x42,0xff,0xe8,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0, ++0x08,0x00,0x29,0x3c,0x24,0x42,0x00,0x01,0x8d,0x82,0x00,0xd0,0x08,0x00,0x29,0x3c, ++0x24,0x42,0x00,0x02,0x10,0xa0,0xff,0xf9,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0xff,0xec,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xe9, ++0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x29,0x3c,0x24,0x42,0xff,0xd0, ++0x10,0xa0,0xff,0xf1,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xeb, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xe6,0x24,0x02,0x00,0x03, ++0x14,0xa2,0xff,0xe1,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x29,0x3c, ++0x24,0x42,0xff,0xf8,0x2d,0x42,0x00,0x24,0x14,0x40,0x00,0x0e,0x00,0x00,0x00,0x00, ++0x10,0xa0,0xff,0xe1,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xdb, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xd6,0x24,0x02,0x00,0x03, ++0x10,0xa2,0xff,0xf1,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x29,0x3c, ++0x24,0x42,0xff,0xf0,0x10,0xa0,0xff,0xd1,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0xff,0xcc,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xf7,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xd7,0x00,0x00,0x00,0x00,0x08,0x00,0x29,0x39, ++0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x24,0x10,0x40,0xff,0xe5,0x00,0x00,0x00,0x00, ++0x10,0xa0,0xff,0xc2,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x14,0xa2,0xff,0xca, ++0x00,0x00,0x00,0x00,0x08,0x00,0x29,0x5e,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x29, ++0x10,0x40,0xff,0xdb,0x00,0x00,0x00,0x00,0x08,0x00,0x29,0x49,0x00,0x00,0x00,0x00, ++0x2d,0x42,0x00,0x24,0x14,0x40,0x00,0x0e,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xb6, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xb0,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xab,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xc6, ++0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x29,0x3c,0x24,0x42,0xff,0xfa, ++0x10,0xa0,0xff,0xa9,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xa1, ++0x24,0x02,0x00,0x02,0x14,0xa2,0xff,0x94,0x00,0x00,0x00,0x00,0x08,0x00,0x29,0x5e, ++0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x24,0x10,0x40,0xff,0xe8,0x00,0x00,0x00,0x00, ++0x10,0xa0,0xff,0x9a,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x95, ++0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x90,0x00,0x00,0x00,0x00,0x08,0x00,0x29,0x51, ++0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x2c,0x14,0x40,0xff,0xcd,0x00,0x00,0x00,0x00, ++0x10,0xa0,0xff,0x91,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x8b, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x86,0x00,0x00,0x00,0x00, ++0x08,0x00,0x29,0x5e,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0x87,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x81,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02, ++0x10,0xa2,0xff,0x7c,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0x97,0x00,0x00,0x00,0x00, ++0x8d,0x82,0x00,0xd0,0x08,0x00,0x29,0x3c,0x24,0x42,0xff,0xfc,0x2d,0x42,0x00,0x24, ++0x14,0x40,0xff,0xa4,0x00,0x00,0x00,0x00,0x08,0x00,0x29,0x54,0x00,0x00,0x00,0x00, ++0x2d,0x42,0x00,0x24,0x14,0x40,0xff,0x9f,0x00,0x00,0x00,0x00,0x08,0x00,0x29,0x2e, ++0x00,0x00,0x00,0x00,0x91,0x86,0x00,0x00,0x91,0x83,0x00,0xd4,0x25,0x8d,0x00,0x5c, ++0x30,0xc4,0x00,0xff,0x00,0x04,0x10,0x40,0x00,0x44,0x10,0x21,0x00,0x04,0x48,0x80, ++0x01,0x82,0x58,0x21,0x01,0x89,0x40,0x21,0x25,0x78,0x00,0x08,0x10,0x60,0x00,0x36, ++0x25,0x0e,0x00,0x60,0x10,0xa0,0x00,0x25,0x00,0x00,0x00,0x00,0x91,0x82,0x00,0xdd, ++0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x1e,0x00,0x00,0x00,0x00,0x27,0x87,0x87,0x78, ++0x01,0x27,0x10,0x21,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0xad,0x03,0x00,0x60, ++0x91,0x62,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x40,0x30,0x21,0xa1,0x82,0x00,0x00, ++0x30,0xc2,0x00,0xff,0x00,0x02,0x10,0x80,0x00,0x47,0x10,0x21,0x8c,0x43,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x03,0x18,0x42,0xad,0xa3,0x00,0x00,0x91,0x84,0x00,0x00, ++0x8d,0xc5,0x00,0x00,0x00,0x04,0x20,0x80,0x00,0x87,0x10,0x21,0x8c,0x43,0x00,0x00, ++0x00,0x05,0x28,0x40,0x00,0x8c,0x20,0x21,0x00,0x03,0x1a,0x80,0x00,0xa3,0x10,0x2b, ++0x00,0x62,0x28,0x0a,0xac,0x85,0x00,0x60,0x03,0xe0,0x00,0x08,0xa1,0x80,0x00,0xd4, ++0x27,0x87,0x87,0x78,0x08,0x00,0x29,0xf0,0xa1,0x80,0x00,0xdd,0x27,0x82,0x87,0xe8, ++0x8d,0x83,0x00,0xd8,0x00,0x82,0x10,0x21,0x90,0x44,0x00,0x00,0x24,0x63,0x00,0x01, ++0x00,0x64,0x20,0x2b,0x14,0x80,0xff,0x33,0xad,0x83,0x00,0xd8,0x8d,0x02,0x00,0x60, ++0xa1,0x80,0x00,0xd4,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43, ++0x03,0xe0,0x00,0x08,0xad,0x82,0x00,0x5c,0x10,0xe0,0x00,0x1d,0x24,0x83,0xff,0xfc, ++0x2c,0x62,0x00,0x18,0x10,0x40,0x00,0xe4,0x00,0x03,0x10,0x80,0x3c,0x03,0x80,0x01, ++0x24,0x63,0x09,0x9c,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x2c,0x14,0x40,0x00,0x65, ++0x00,0x00,0x00,0x00,0x10,0xa0,0x00,0x60,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0x00,0x5a,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x08, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x51,0x00,0x00,0x00,0x00, ++0x8d,0x82,0x00,0xd0,0x00,0x00,0x00,0x00,0x24,0x42,0xff,0xe0,0xad,0x82,0x00,0xd0, ++0x8d,0xe3,0x00,0x00,0x8d,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21, ++0xad,0xa2,0x00,0x00,0xad,0xe0,0x00,0x00,0x8d,0xa3,0x00,0x00,0x8d,0xc4,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x83,0x10,0x2a,0x10,0x40,0x00,0x22,0x00,0x00,0x00,0x00, ++0x93,0x05,0x00,0x01,0x91,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x45,0x00,0x05, ++0x24,0x02,0x00,0x01,0xa1,0x85,0x00,0x00,0xa1,0x82,0x00,0xd4,0x03,0xe0,0x00,0x08, ++0xad,0x80,0x00,0xd8,0x91,0x82,0x00,0xdd,0x24,0x03,0x00,0x01,0x10,0x43,0x00,0x05, ++0x00,0x00,0x00,0x00,0xa1,0x83,0x00,0xd4,0xad,0x80,0x00,0xd8,0x03,0xe0,0x00,0x08, ++0xa1,0x83,0x00,0xdd,0x00,0x04,0x17,0xc2,0x00,0x82,0x10,0x21,0x00,0x02,0x10,0x43, ++0xad,0xa2,0x00,0x00,0x91,0x83,0x00,0x00,0x27,0x82,0x87,0x78,0x8d,0xc5,0x00,0x00, ++0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,0x8c,0x64,0x00,0x00,0x00,0x05,0x28,0x40, ++0x00,0x04,0x1a,0x80,0x00,0xa3,0x10,0x2b,0x00,0x62,0x28,0x0a,0x08,0x00,0x2a,0x02, ++0xad,0xc5,0x00,0x00,0x97,0x82,0x94,0x5c,0x00,0x00,0x00,0x00,0x00,0x62,0x10,0x2a, ++0x10,0x40,0xfe,0xdc,0x00,0x00,0x00,0x00,0x91,0x82,0x00,0xdd,0x00,0x00,0x00,0x00, ++0x14,0x40,0x00,0x15,0x00,0x00,0x00,0x00,0x91,0x83,0x00,0x00,0x27,0x82,0x87,0x78, ++0x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x6c,0x18,0x21, ++0xac,0x64,0x00,0x60,0x93,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x10,0x80, ++0x01,0x82,0x10,0x21,0x24,0x4e,0x00,0x60,0xa1,0x85,0x00,0x00,0x8d,0xc2,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43, ++0x03,0xe0,0x00,0x08,0xad,0xa2,0x00,0x00,0x08,0x00,0x2a,0x77,0xa1,0x80,0x00,0xdd, ++0x8d,0x82,0x00,0xd0,0x08,0x00,0x2a,0x33,0x24,0x42,0xff,0xe8,0x8d,0x82,0x00,0xd0, ++0x08,0x00,0x2a,0x33,0x24,0x42,0x00,0x01,0x8d,0x82,0x00,0xd0,0x08,0x00,0x2a,0x33, ++0x24,0x42,0x00,0x02,0x10,0xa0,0xff,0xf9,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0xff,0xa3,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xa0, ++0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x2a,0x33,0x24,0x42,0xff,0xd0, ++0x10,0xa0,0xff,0xf1,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xeb, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x99,0x24,0x02,0x00,0x03, ++0x14,0xa2,0xff,0xe3,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x2a,0x33, ++0x24,0x42,0xff,0xf8,0x2d,0x42,0x00,0x24,0x14,0x40,0x00,0x0e,0x00,0x00,0x00,0x00, ++0x10,0xa0,0xff,0xe1,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xdb, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x89,0x24,0x02,0x00,0x03, ++0x10,0xa2,0xff,0xf1,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x2a,0x33, ++0x24,0x42,0xff,0xf0,0x10,0xa0,0xff,0xd1,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01, ++0x10,0xa2,0xff,0x7f,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xf7,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xd7,0x00,0x00,0x00,0x00,0x08,0x00,0x2a,0x30, ++0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x24,0x10,0x40,0xff,0xe5,0x00,0x00,0x00,0x00, ++0x10,0xa0,0xff,0xc2,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x14,0xa2,0xff,0xca, ++0x00,0x00,0x00,0x00,0x08,0x00,0x2a,0x9e,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x29, ++0x10,0x40,0xff,0xdb,0x00,0x00,0x00,0x00,0x08,0x00,0x2a,0x89,0x00,0x00,0x00,0x00, ++0x2d,0x42,0x00,0x24,0x14,0x40,0x00,0x0e,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xb6, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xb0,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x5e,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xc6, ++0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x2a,0x33,0x24,0x42,0xff,0xfa, ++0x10,0xa0,0xff,0xa9,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x54, ++0x24,0x02,0x00,0x02,0x14,0xa2,0xff,0x4b,0x00,0x00,0x00,0x00,0x08,0x00,0x2a,0x9e, ++0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x24,0x10,0x40,0xff,0xe8,0x00,0x00,0x00,0x00, ++0x10,0xa0,0xff,0x9a,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x48, ++0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x92,0x00,0x00,0x00,0x00,0x08,0x00,0x2a,0x91, ++0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x2c,0x14,0x40,0xff,0xcd,0x00,0x00,0x00,0x00, ++0x10,0xa0,0xff,0x91,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x8b, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x39,0x00,0x00,0x00,0x00, ++0x08,0x00,0x2a,0x9e,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0x87,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x81,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02, ++0x10,0xa2,0xff,0x2f,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0x97,0x00,0x00,0x00,0x00, ++0x8d,0x82,0x00,0xd0,0x08,0x00,0x2a,0x33,0x24,0x42,0xff,0xfc,0x2d,0x42,0x00,0x24, ++0x14,0x40,0xff,0xa4,0x00,0x00,0x00,0x00,0x08,0x00,0x2a,0x94,0x00,0x00,0x00,0x00, ++0x2d,0x42,0x00,0x24,0x14,0x40,0xff,0x9f,0x00,0x00,0x00,0x00,0x08,0x00,0x2a,0x25, ++0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe8,0x3c,0x02,0xb0,0x03,0xaf,0xbf,0x00,0x14, ++0xaf,0xb0,0x00,0x10,0x34,0x42,0x01,0x18,0x3c,0x03,0xb0,0x03,0x8c,0x50,0x00,0x00, ++0x34,0x63,0x01,0x2c,0x90,0x62,0x00,0x00,0x32,0x05,0x00,0x01,0xa3,0x82,0x80,0x10, ++0x14,0xa0,0x00,0x14,0x30,0x44,0x00,0xff,0x32,0x02,0x01,0x00,0x14,0x40,0x00,0x09, ++0x00,0x00,0x00,0x00,0x32,0x02,0x08,0x00,0x10,0x40,0x00,0x02,0x24,0x02,0x00,0x01, ++0xa3,0x82,0xc5,0x58,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x18,0x0c,0x00,0x0b,0x3e,0x00,0x00,0x00,0x00,0x26,0x02,0xff,0x00, ++0xa3,0x80,0xc5,0x58,0x3c,0x01,0xb0,0x03,0xac,0x22,0x01,0x18,0x08,0x00,0x2b,0x26, ++0x32,0x02,0x08,0x00,0x0c,0x00,0x28,0xb0,0x00,0x00,0x00,0x00,0x26,0x02,0xff,0xff, ++0x3c,0x01,0xb0,0x03,0xac,0x22,0x01,0x18,0x08,0x00,0x2b,0x23,0x32,0x02,0x01,0x00, ++0x27,0xbd,0xff,0xe0,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xd0,0xaf,0xbf,0x00,0x18, ++0x8c,0x43,0x00,0x00,0x3c,0x02,0x00,0x40,0x24,0x07,0x0f,0xff,0x00,0x03,0x33,0x02, ++0x00,0x03,0x2d,0x02,0x00,0x03,0x43,0x02,0x30,0x69,0x0f,0xff,0x00,0x62,0x18,0x24, ++0x30,0xa5,0x00,0x03,0x30,0xc6,0x00,0xff,0x10,0x60,0x00,0x08,0x31,0x08,0x00,0xff, ++0x01,0x00,0x30,0x21,0x0c,0x00,0x2b,0xe7,0xaf,0xa9,0x00,0x10,0x8f,0xbf,0x00,0x18, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x0c,0x00,0x2c,0x39, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0xd4,0x08,0x00,0x2b,0x4f, ++0xac,0x62,0x00,0x00,0x27,0xbd,0xff,0xc0,0xaf,0xb6,0x00,0x30,0xaf,0xb3,0x00,0x24, ++0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,0xaf,0xbf,0x00,0x3c,0xaf,0xbe,0x00,0x38, ++0xaf,0xb7,0x00,0x34,0xaf,0xb5,0x00,0x2c,0xaf,0xb4,0x00,0x28,0xaf,0xb2,0x00,0x20, ++0x0c,0x00,0x1f,0x11,0x00,0x80,0x80,0x21,0x00,0x00,0xb0,0x21,0x00,0x00,0x88,0x21, ++0x10,0x40,0x00,0x12,0x00,0x00,0x98,0x21,0x3c,0x02,0xb0,0x03,0x3c,0x03,0xb0,0x03, ++0x3c,0x04,0xb0,0x03,0x24,0x05,0x00,0x01,0x34,0x42,0x00,0xbc,0x34,0x63,0x00,0xbb, ++0x34,0x84,0x00,0xba,0xa4,0x40,0x00,0x00,0xa0,0x65,0x00,0x00,0xa0,0x85,0x00,0x00, ++0x7b,0xbe,0x01,0xfc,0x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c, ++0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,0x3c,0x02,0xb0,0x03, ++0x34,0x42,0x01,0x47,0x90,0x44,0x00,0x00,0x00,0x10,0x1a,0x02,0x3c,0x15,0xfd,0xff, ++0x30,0x84,0x00,0xff,0xa0,0x50,0x00,0x00,0x30,0x74,0x00,0x0f,0xaf,0xa4,0x00,0x10, ++0x00,0x00,0x90,0x21,0x3c,0x17,0x02,0x00,0x36,0xb5,0xff,0xff,0x3c,0x1e,0xb0,0x03, ++0x0c,0x00,0x0e,0x71,0x24,0x04,0x00,0x78,0x00,0x57,0x10,0x25,0x00,0x40,0x28,0x21, ++0x0c,0x00,0x0e,0x64,0x24,0x04,0x00,0x78,0x00,0x00,0x80,0x21,0x0c,0x00,0x2d,0x0a, ++0x00,0x00,0x00,0x00,0x26,0x03,0x00,0x01,0x30,0x70,0x00,0xff,0x10,0x40,0x00,0x47, ++0x2e,0x03,0x00,0x02,0x14,0x60,0xff,0xf9,0x00,0x00,0x00,0x00,0x0c,0x00,0x0e,0x71, ++0x24,0x04,0x00,0x78,0x00,0x55,0x10,0x24,0x00,0x40,0x28,0x21,0x0c,0x00,0x0e,0x64, ++0x24,0x04,0x00,0x78,0x24,0x02,0x00,0x01,0x12,0x82,0x00,0x38,0x24,0x04,0x00,0xe0, ++0x12,0x80,0x00,0x36,0x24,0x04,0x00,0xe4,0x32,0x22,0x00,0x60,0x32,0x23,0x0c,0x00, ++0x00,0x03,0x1a,0x02,0x3c,0x05,0x00,0x60,0x00,0x02,0x11,0x42,0x02,0x25,0x20,0x24, ++0x00,0x43,0x10,0x25,0x3c,0x03,0x04,0x00,0x02,0x23,0x28,0x24,0x00,0x04,0x24,0x42, ++0x00,0x44,0x10,0x25,0x00,0x05,0x2d,0x02,0x00,0x45,0x88,0x25,0x12,0x20,0x00,0x05, ++0x26,0x42,0x00,0x01,0x26,0xc2,0x00,0x01,0x30,0x56,0x00,0xff,0x02,0x71,0x98,0x21, ++0x26,0x42,0x00,0x01,0x02,0x5e,0x20,0x21,0x30,0x52,0x00,0xff,0x2e,0x43,0x00,0x05, ++0xa0,0x91,0x00,0xd8,0x14,0x60,0xff,0xce,0x3c,0x02,0xb0,0x03,0x8f,0xa5,0x00,0x10, ++0x34,0x42,0x01,0x47,0xa0,0x45,0x00,0x00,0x12,0x60,0x00,0x0e,0x3c,0x02,0xb0,0x03, ++0x12,0xc0,0x00,0x0d,0x34,0x42,0x00,0xbc,0x00,0x13,0x10,0x40,0x00,0x53,0x10,0x21, ++0x00,0x02,0x10,0xc0,0x00,0x53,0x10,0x21,0x00,0x02,0x98,0x80,0x02,0x76,0x00,0x1b, ++0x16,0xc0,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0d,0x00,0x00,0x98,0x12, ++0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xbc,0x3c,0x03,0xb0,0x03,0x3c,0x04,0xb0,0x03, ++0xa4,0x53,0x00,0x00,0x34,0x63,0x00,0xbb,0x34,0x84,0x00,0xba,0x24,0x02,0x00,0x01, ++0xa0,0x60,0x00,0x00,0x08,0x00,0x2b,0x74,0xa0,0x82,0x00,0x00,0x0c,0x00,0x0e,0x71, ++0x00,0x00,0x00,0x00,0x08,0x00,0x2b,0xa2,0x00,0x40,0x88,0x21,0x3c,0x03,0xb0,0x03, ++0x34,0x63,0x00,0xbc,0x3c,0x04,0xb0,0x03,0x3c,0x05,0xb0,0x03,0xa4,0x60,0x00,0x00, ++0x34,0x84,0x00,0xbb,0x34,0xa5,0x00,0xba,0x24,0x02,0x00,0x02,0x24,0x03,0x00,0x01, ++0xa0,0x82,0x00,0x00,0x08,0x00,0x2b,0x74,0xa0,0xa3,0x00,0x00,0x27,0xbd,0xff,0xd8, ++0xaf,0xb0,0x00,0x10,0x30,0xd0,0x00,0xff,0x2e,0x02,0x00,0x2e,0xaf,0xb2,0x00,0x18, ++0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,0x30,0xb1,0x00,0xff, ++0x14,0x40,0x00,0x06,0x00,0x80,0x90,0x21,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x2e,0x13,0x00,0x10, ++0x24,0x05,0x00,0x14,0x0c,0x00,0x1b,0x6e,0x24,0x06,0x01,0x07,0x12,0x60,0x00,0x38, ++0x02,0x00,0x30,0x21,0x8f,0xa2,0x00,0x38,0x30,0xc3,0x00,0x3f,0x3c,0x04,0xb0,0x09, ++0x00,0x02,0x14,0x00,0x00,0x43,0x30,0x25,0x34,0x84,0x01,0x60,0x90,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xfd,0x24,0x02,0x00,0x01,0x12,0x22,0x00,0x2a, ++0x2a,0x22,0x00,0x02,0x14,0x40,0x00,0x24,0x24,0x02,0x00,0x02,0x12,0x22,0x00,0x20, ++0x24,0x02,0x00,0x03,0x12,0x22,0x00,0x19,0x00,0x00,0x00,0x00,0x16,0x60,0xff,0xe2, ++0x24,0x02,0x00,0x01,0x12,0x22,0x00,0x13,0x2a,0x22,0x00,0x02,0x14,0x40,0x00,0x0d, ++0x24,0x02,0x00,0x02,0x12,0x22,0x00,0x09,0x24,0x02,0x00,0x03,0x16,0x22,0xff,0xda, ++0x00,0x00,0x00,0x00,0x24,0x04,0x08,0x4c,0x24,0x05,0xff,0xff,0x0c,0x00,0x1b,0x29, ++0x3c,0x06,0x0c,0xb8,0x08,0x00,0x2b,0xf2,0x00,0x00,0x00,0x00,0x08,0x00,0x2c,0x1a, ++0x24,0x04,0x08,0x48,0x16,0x20,0xff,0xd0,0x00,0x00,0x00,0x00,0x08,0x00,0x2c,0x1a, ++0x24,0x04,0x08,0x40,0x08,0x00,0x2c,0x1a,0x24,0x04,0x08,0x44,0x24,0x04,0x08,0x4c, ++0x0c,0x00,0x1b,0x29,0x24,0x05,0xff,0xff,0x08,0x00,0x2c,0x0f,0x00,0x00,0x00,0x00, ++0x08,0x00,0x2c,0x28,0x24,0x04,0x08,0x48,0x16,0x20,0xff,0xe0,0x00,0x00,0x00,0x00, ++0x08,0x00,0x2c,0x28,0x24,0x04,0x08,0x40,0x08,0x00,0x2c,0x28,0x24,0x04,0x08,0x44, ++0x02,0x40,0x20,0x21,0x0c,0x00,0x2c,0x75,0x02,0x20,0x28,0x21,0x08,0x00,0x2b,0xfd, ++0x00,0x40,0x30,0x21,0x27,0xbd,0xff,0xd8,0x2c,0xc2,0x00,0x2e,0xaf,0xb3,0x00,0x1c, ++0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x20,0xaf,0xb2,0x00,0x18, ++0x00,0xc0,0x88,0x21,0x30,0xb0,0x00,0xff,0x00,0x80,0x98,0x21,0x14,0x40,0x00,0x07, ++0x00,0x00,0x18,0x21,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc, ++0x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x2e,0x32,0x00,0x10, ++0x24,0x05,0x00,0x14,0x0c,0x00,0x1b,0x6e,0x24,0x06,0x01,0x07,0x12,0x40,0x00,0x1f, ++0x02,0x20,0x10,0x21,0x30,0x45,0x00,0x3f,0x0c,0x00,0x2c,0xb2,0x02,0x00,0x20,0x21, ++0x16,0x40,0x00,0x0a,0x00,0x40,0x88,0x21,0x24,0x02,0x00,0x01,0x12,0x02,0x00,0x15, ++0x2a,0x02,0x00,0x02,0x14,0x40,0x00,0x0f,0x24,0x02,0x00,0x02,0x12,0x02,0x00,0x0b, ++0x24,0x02,0x00,0x03,0x12,0x02,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x2c,0x45, ++0x02,0x20,0x18,0x21,0x24,0x04,0x08,0x4c,0x24,0x05,0xff,0xff,0x0c,0x00,0x1b,0x29, ++0x3c,0x06,0x0c,0xb8,0x08,0x00,0x2c,0x45,0x02,0x20,0x18,0x21,0x08,0x00,0x2c,0x62, ++0x24,0x04,0x08,0x48,0x16,0x00,0xff,0xf5,0x00,0x00,0x00,0x00,0x08,0x00,0x2c,0x62, ++0x24,0x04,0x08,0x40,0x08,0x00,0x2c,0x62,0x24,0x04,0x08,0x44,0x02,0x60,0x20,0x21, ++0x02,0x20,0x30,0x21,0x0c,0x00,0x2c,0x75,0x02,0x00,0x28,0x21,0x08,0x00,0x2c,0x52, ++0x30,0x45,0x00,0x3f,0x27,0xbd,0xff,0xe8,0x2c,0xc2,0x00,0x1f,0xaf,0xb0,0x00,0x10, ++0xaf,0xbf,0x00,0x14,0x00,0xc0,0x80,0x21,0x14,0x40,0x00,0x1d,0x30,0xa5,0x00,0xff, ++0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x18,0x28,0xa2,0x00,0x02,0x14,0x40,0x00,0x12, ++0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x0e,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x07, ++0x24,0x04,0x08,0x4c,0x26,0x10,0xff,0xe2,0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x14, ++0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x24,0x05,0xff,0xff, ++0x0c,0x00,0x1b,0x29,0x3c,0x06,0x0d,0xf8,0x08,0x00,0x2c,0x86,0x26,0x10,0xff,0xe2, ++0x08,0x00,0x2c,0x8b,0x24,0x04,0x08,0x48,0x14,0xa0,0xff,0xf2,0x24,0x04,0x08,0x40, ++0x08,0x00,0x2c,0x8c,0x24,0x05,0xff,0xff,0x08,0x00,0x2c,0x8b,0x24,0x04,0x08,0x44, ++0x2c,0xc2,0x00,0x10,0x14,0x40,0xff,0xec,0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x14, ++0x28,0xa2,0x00,0x02,0x14,0x40,0x00,0x0e,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x0a, ++0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x03,0x24,0x04,0x08,0x4c,0x08,0x00,0x2c,0x86, ++0x26,0x10,0xff,0xf1,0x24,0x05,0xff,0xff,0x0c,0x00,0x1b,0x29,0x3c,0x06,0x0d,0xb8, ++0x08,0x00,0x2c,0x86,0x26,0x10,0xff,0xf1,0x08,0x00,0x2c,0xa5,0x24,0x04,0x08,0x48, ++0x14,0xa0,0xff,0xf6,0x24,0x04,0x08,0x40,0x08,0x00,0x2c,0xa6,0x24,0x05,0xff,0xff, ++0x08,0x00,0x2c,0xa5,0x24,0x04,0x08,0x44,0x27,0xbd,0xff,0xe0,0x00,0x80,0x10,0x21, ++0x24,0x04,0x00,0x50,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x18, ++0x00,0xa0,0x88,0x21,0x0c,0x00,0x01,0x31,0x30,0x50,0x00,0xff,0x24,0x03,0x00,0x01, ++0x12,0x03,0x00,0x3e,0x02,0x20,0x30,0x21,0x2a,0x02,0x00,0x02,0x14,0x40,0x00,0x2a, ++0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x12,0x02,0x00,0x19,0x24,0x04,0x08,0x34, ++0x24,0x02,0x00,0x03,0x12,0x02,0x00,0x05,0x24,0x04,0x08,0x3c,0x8f,0xbf,0x00,0x18, ++0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x0c,0x00,0x1b,0x29, ++0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x3c,0x3c,0x05,0x80,0x00,0x0c,0x00,0x1b,0x29, ++0x00,0x00,0x30,0x21,0x3c,0x05,0x80,0x00,0x24,0x06,0x00,0x01,0x0c,0x00,0x1b,0x29, ++0x24,0x04,0x08,0x3c,0x0c,0x00,0x01,0x31,0x24,0x04,0x00,0x28,0x24,0x04,0x08,0xac, ++0x0c,0x00,0x1b,0x0b,0x24,0x05,0x0f,0xff,0x08,0x00,0x2c,0xc7,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x1b,0x29,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x34,0x3c,0x05,0x80,0x00, ++0x0c,0x00,0x1b,0x29,0x00,0x00,0x30,0x21,0x3c,0x05,0x80,0x00,0x24,0x06,0x00,0x01, ++0x0c,0x00,0x1b,0x29,0x24,0x04,0x08,0x34,0x0c,0x00,0x01,0x31,0x24,0x04,0x00,0x28, ++0x08,0x00,0x2c,0xd8,0x24,0x04,0x08,0xa8,0x16,0x00,0xff,0xdc,0x02,0x20,0x30,0x21, ++0x24,0x04,0x08,0x24,0x0c,0x00,0x1b,0x29,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x24, ++0x3c,0x05,0x80,0x00,0x0c,0x00,0x1b,0x29,0x00,0x00,0x30,0x21,0x3c,0x05,0x80,0x00, ++0x24,0x06,0x00,0x01,0x0c,0x00,0x1b,0x29,0x24,0x04,0x08,0x24,0x0c,0x00,0x01,0x31, ++0x24,0x04,0x00,0x28,0x08,0x00,0x2c,0xd8,0x24,0x04,0x08,0xa0,0x24,0x04,0x08,0x2c, ++0x0c,0x00,0x1b,0x29,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x2c,0x3c,0x05,0x80,0x00, ++0x0c,0x00,0x1b,0x29,0x00,0x00,0x30,0x21,0x3c,0x05,0x80,0x00,0x24,0x06,0x00,0x01, ++0x0c,0x00,0x1b,0x29,0x24,0x04,0x08,0x2c,0x0c,0x00,0x01,0x31,0x24,0x04,0x00,0x28, ++0x08,0x00,0x2c,0xd8,0x24,0x04,0x08,0xa4,0x3c,0x05,0x00,0x14,0x3c,0x02,0xb0,0x05, ++0x34,0x42,0x04,0x20,0x3c,0x06,0xc0,0x00,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05, ++0x34,0xa5,0x17,0x09,0xac,0x45,0x00,0x00,0x34,0xc6,0x05,0x07,0x34,0x63,0x04,0x24, ++0x34,0x84,0x02,0x28,0x3c,0x07,0xb0,0x05,0x24,0x02,0x00,0x20,0xac,0x66,0x00,0x00, ++0x34,0xe7,0x04,0x50,0xa0,0x82,0x00,0x00,0x90,0xe2,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0x03,0x10,0x40,0xff,0xfc,0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x0c,0x00,0x2d,0xcf, ++0x00,0x00,0x00,0x00,0x0c,0x00,0x2d,0xd1,0x00,0x00,0x00,0x00,0x0c,0x00,0x2d,0xf8, ++0x00,0x00,0x00,0x00,0x3c,0x04,0xb0,0x05,0x34,0x84,0x00,0x04,0x0c,0x00,0x2d,0xd8, ++0x34,0x05,0x9c,0x40,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x18,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08, ++0x24,0x02,0x00,0x01,0x97,0x82,0x88,0x10,0x00,0x00,0x00,0x00,0x2c,0x43,0x00,0x64, ++0x24,0x42,0x00,0x01,0xa7,0x82,0x88,0x10,0x14,0x60,0x00,0x28,0x00,0x80,0x30,0x21, ++0x8c,0x82,0x00,0x00,0x3c,0x03,0x20,0x00,0xa7,0x80,0x88,0x10,0x00,0x43,0x10,0x24, ++0x10,0x40,0x00,0x22,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x00,0x3c,0x03,0x80,0x00, ++0x00,0x43,0x10,0x25,0x97,0x83,0x88,0x04,0xac,0x82,0x00,0x00,0x8c,0x85,0x00,0x00, ++0x24,0x63,0x00,0x01,0x3c,0x02,0x40,0x64,0x34,0x42,0x64,0x00,0x00,0x03,0x24,0x00, ++0x00,0xa2,0x28,0x25,0x00,0x04,0x24,0x03,0x24,0x02,0x00,0x64,0xac,0xc5,0x00,0x00, ++0xa7,0x83,0x88,0x04,0x10,0x82,0x00,0x2b,0x00,0x00,0x00,0x00,0x87,0x82,0x88,0x06, ++0x24,0x03,0x00,0x3c,0x10,0x43,0x00,0x21,0x00,0x00,0x00,0x00,0x87,0x82,0x88,0x08, ++0x00,0x00,0x00,0x00,0x10,0x43,0x00,0x17,0x00,0x00,0x00,0x00,0x87,0x83,0x88,0x0a, ++0x24,0x02,0x00,0x18,0x10,0x62,0x00,0x0d,0x00,0x00,0x00,0x00,0x87,0x83,0x88,0x0c, ++0x24,0x02,0x01,0x6d,0x10,0x62,0x00,0x03,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x97,0x82,0x88,0x0e,0xa7,0x80,0x88,0x0c,0x24,0x42,0x00,0x01, ++0xa7,0x82,0x88,0x0e,0x08,0x00,0x2d,0x67,0x00,0x00,0x00,0x00,0x97,0x82,0x88,0x0c, ++0xa7,0x80,0x88,0x0a,0x24,0x42,0x00,0x01,0xa7,0x82,0x88,0x0c,0x08,0x00,0x2d,0x63, ++0x00,0x00,0x00,0x00,0x97,0x82,0x88,0x0a,0xa7,0x80,0x88,0x08,0x24,0x42,0x00,0x01, ++0xa7,0x82,0x88,0x0a,0x08,0x00,0x2d,0x5f,0x00,0x00,0x00,0x00,0x97,0x82,0x88,0x08, ++0xa7,0x80,0x88,0x06,0x24,0x42,0x00,0x01,0xa7,0x82,0x88,0x08,0x08,0x00,0x2d,0x5b, ++0x00,0x00,0x00,0x00,0x97,0x82,0x88,0x06,0xa7,0x80,0x88,0x04,0x24,0x42,0x00,0x01, ++0xa7,0x82,0x88,0x06,0x08,0x00,0x2d,0x57,0x00,0x00,0x00,0x00,0x00,0x04,0x24,0x00, ++0x3c,0x03,0xb0,0x07,0x00,0x04,0x24,0x03,0x34,0x63,0x00,0x28,0x90,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x40,0x10,0x40,0xff,0xfc,0x00,0x00,0x00,0x00, ++0x3c,0x01,0xb0,0x07,0xa0,0x24,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x10,0x21, ++0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x28,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x63,0x00,0x01,0x10,0x60,0x00,0x06,0x24,0x02,0xff,0xff,0x3c,0x02,0xb0,0x07, ++0x90,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x16,0x00,0x00,0x02,0x16,0x03, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe0,0xaf,0xb0,0x00,0x10, ++0x3c,0x10,0x04,0xc4,0x00,0x04,0x11,0x00,0x36,0x10,0xb4,0x00,0x02,0x02,0x00,0x1b, ++0xaf,0xb1,0x00,0x14,0x3c,0x11,0xb0,0x07,0x36,0x31,0x00,0x18,0x24,0x04,0x00,0x0a, ++0xaf,0xbf,0x00,0x18,0x14,0x40,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0d, ++0x00,0x00,0x80,0x12,0x0c,0x00,0x2e,0x24,0x00,0x00,0x00,0x00,0x92,0x22,0x00,0x00, ++0x24,0x03,0xff,0x80,0x24,0x04,0x00,0x0a,0x00,0x43,0x10,0x25,0x0c,0x00,0x2e,0x24, ++0xa2,0x22,0x00,0x00,0x24,0x04,0x00,0x0a,0x3c,0x01,0xb0,0x07,0xa0,0x30,0x00,0x00, ++0x0c,0x00,0x2e,0x24,0x00,0x10,0x82,0x03,0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x08, ++0xa0,0x50,0x00,0x00,0x0c,0x00,0x2e,0x24,0x24,0x04,0x00,0x0a,0x92,0x22,0x00,0x00, ++0x8f,0xbf,0x00,0x18,0x8f,0xb0,0x00,0x10,0x30,0x42,0x00,0x7f,0xa2,0x22,0x00,0x00, ++0x8f,0xb1,0x00,0x14,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x58,0x8c,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x34,0x42,0x07,0xa4,0x03,0xe0,0x00,0x08,0xac,0x62,0x00,0x00, ++0x27,0xbd,0xff,0xf8,0x00,0x80,0x38,0x21,0x00,0xa0,0x30,0x21,0x00,0x00,0x18,0x21, ++0x00,0x63,0x00,0x18,0x00,0x00,0x10,0x12,0x00,0xc2,0x10,0x2b,0x14,0x40,0x00,0x05, ++0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,0x2c,0x62,0x01,0x00,0x14,0x40,0xff,0xf9, ++0x00,0x63,0x00,0x18,0x24,0x63,0xff,0xff,0x00,0x63,0x00,0x18,0x30,0x63,0x00,0xff, ++0x8c,0xe4,0x00,0x00,0x00,0x03,0x2a,0x00,0x00,0x03,0x1c,0x00,0x00,0x00,0x10,0x12, ++0x00,0xc2,0x10,0x23,0x30,0x42,0x00,0xff,0x00,0x45,0x10,0x21,0x00,0x43,0x10,0x21, ++0x00,0x82,0x20,0x25,0xac,0xe4,0x00,0x00,0x8c,0xe2,0x00,0x00,0x3c,0x03,0x40,0x00, ++0x00,0x43,0x10,0x25,0xac,0xe2,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x08, ++0x27,0xbd,0xff,0xe0,0xaf,0xbf,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10, ++0x3c,0x04,0xb0,0x03,0x8c,0x82,0x00,0x00,0x3c,0x06,0xb0,0x03,0x34,0xc6,0x00,0x08, ++0x34,0x42,0x40,0x00,0xac,0x82,0x00,0x00,0x8c,0x83,0x00,0x00,0x24,0x02,0xcf,0xff, ++0x3c,0x11,0xb0,0x07,0x00,0x62,0x18,0x24,0xac,0x83,0x00,0x00,0x8c,0xc5,0x00,0x00, ++0x3c,0x02,0x00,0xff,0x24,0x04,0x00,0x0a,0x00,0xa2,0x28,0x25,0xac,0xc5,0x00,0x00, ++0x0c,0x00,0x2e,0x24,0x36,0x31,0x00,0x18,0x24,0x02,0xff,0x83,0x3c,0x04,0x00,0x01, ++0xa2,0x22,0x00,0x00,0x0c,0x00,0x2d,0xa2,0x34,0x84,0xc2,0x00,0x0c,0x00,0x2e,0x24, ++0x24,0x04,0x00,0x0a,0x24,0x02,0x00,0x03,0xa2,0x22,0x00,0x00,0x24,0x04,0x00,0x0a, ++0x0c,0x00,0x2e,0x24,0x3c,0x10,0xb0,0x07,0x36,0x10,0x00,0x10,0x24,0x02,0x00,0x06, ++0xa2,0x02,0x00,0x00,0x0c,0x00,0x2e,0x24,0x24,0x04,0x00,0x0a,0xa2,0x00,0x00,0x00, ++0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20, ++0x10,0x80,0x00,0x05,0x00,0x00,0x18,0x21,0x24,0x63,0x00,0x01,0x00,0x64,0x10,0x2b, ++0x14,0x40,0xff,0xfd,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x27,0xbd,0xff,0xc0,0xaf,0xb5,0x00,0x34,0xaf,0xb2,0x00,0x28,0xaf,0xb0,0x00,0x20, ++0xaf,0xbf,0x00,0x38,0xaf,0xb4,0x00,0x30,0xaf,0xb3,0x00,0x2c,0xaf,0xb1,0x00,0x24, ++0xaf,0xa5,0x00,0x44,0x90,0xa7,0x00,0x00,0x00,0x80,0xa8,0x21,0x00,0xc0,0x90,0x21, ++0x00,0x07,0x1e,0x00,0x10,0x60,0x00,0x0f,0x00,0x80,0x80,0x21,0x00,0x03,0x1e,0x03, ++0x24,0x02,0x00,0x25,0x10,0x62,0x00,0x13,0x00,0x00,0x88,0x21,0xa2,0x07,0x00,0x00, ++0x8f,0xa5,0x00,0x44,0x26,0x10,0x00,0x01,0x24,0xa5,0x00,0x01,0xaf,0xa5,0x00,0x44, ++0x90,0xa7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x1e,0x00,0x14,0x60,0xff,0xf3, ++0x00,0x00,0x00,0x00,0x02,0x15,0x10,0x23,0xa2,0x00,0x00,0x00,0x8f,0xbf,0x00,0x38, ++0x7b,0xb4,0x01,0xbc,0x7b,0xb2,0x01,0x7c,0x7b,0xb0,0x01,0x3c,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x40,0x24,0xa5,0x00,0x01,0xaf,0xa5,0x00,0x44,0x80,0xa3,0x00,0x00, ++0x00,0x00,0x00,0x00,0x24,0x63,0xff,0xe0,0x2c,0x62,0x00,0x11,0x10,0x40,0x00,0x11, ++0x00,0xa0,0x38,0x21,0x00,0x03,0x10,0x80,0x3c,0x03,0x80,0x01,0x24,0x63,0x09,0xfc, ++0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08, ++0x00,0x00,0x00,0x00,0x08,0x00,0x2e,0x51,0x36,0x31,0x00,0x10,0x08,0x00,0x2e,0x51, ++0x36,0x31,0x00,0x08,0x08,0x00,0x2e,0x51,0x36,0x31,0x00,0x20,0x08,0x00,0x2e,0x51, ++0x36,0x31,0x00,0x04,0x90,0xe4,0x00,0x00,0x3c,0x02,0x80,0x01,0x24,0x42,0x02,0x1c, ++0x00,0x44,0x10,0x21,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x04, ++0x14,0x60,0x00,0xfd,0x24,0x14,0xff,0xff,0x00,0x04,0x16,0x00,0x00,0x02,0x16,0x03, ++0x24,0x03,0x00,0x2a,0x10,0x43,0x00,0xee,0x26,0x42,0x00,0x03,0x80,0xa3,0x00,0x00, ++0x24,0x02,0x00,0x2e,0x10,0x62,0x00,0xcc,0x24,0x08,0xff,0xff,0x80,0xa3,0x00,0x00, ++0x24,0x02,0x00,0x68,0x10,0x62,0x00,0xc4,0x24,0x06,0xff,0xff,0x24,0x02,0x00,0x6c, ++0x10,0x62,0x00,0xc1,0x24,0x02,0x00,0x4c,0x10,0x62,0x00,0xbf,0x24,0x02,0x00,0x5a, ++0x10,0x62,0x00,0xbd,0x00,0x00,0x00,0x00,0x80,0xa3,0x00,0x00,0x00,0x00,0x00,0x00, ++0x24,0x63,0xff,0xdb,0x2c,0x62,0x00,0x54,0x10,0x40,0x00,0xaa,0x24,0x09,0x00,0x0a, ++0x00,0x03,0x10,0x80,0x3c,0x03,0x80,0x01,0x24,0x63,0x0a,0x40,0x00,0x43,0x10,0x21, ++0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00, ++0x32,0x22,0x00,0x10,0x14,0x40,0x00,0x09,0x24,0x02,0xff,0xfc,0x26,0x94,0xff,0xff, ++0x1a,0x80,0x00,0x05,0x24,0x02,0x00,0x20,0x26,0x94,0xff,0xff,0xa2,0x02,0x00,0x00, ++0x1e,0x80,0xff,0xfd,0x26,0x10,0x00,0x01,0x24,0x02,0xff,0xfc,0x26,0x44,0x00,0x03, ++0x00,0x82,0x90,0x24,0x92,0x42,0x00,0x03,0x26,0x94,0xff,0xff,0x26,0x52,0x00,0x04, ++0xa2,0x02,0x00,0x00,0x1a,0x80,0x00,0x06,0x26,0x10,0x00,0x01,0x24,0x02,0x00,0x20, ++0x26,0x94,0xff,0xff,0xa2,0x02,0x00,0x00,0x1e,0x80,0xff,0xfd,0x26,0x10,0x00,0x01, ++0x8f,0xa5,0x00,0x44,0x08,0x00,0x2e,0x43,0x24,0xa5,0x00,0x01,0x24,0x02,0x00,0x25, ++0x08,0x00,0x2e,0x40,0xa2,0x02,0x00,0x00,0x36,0x31,0x00,0x40,0x24,0x09,0x00,0x10, ++0x24,0x02,0x00,0x4c,0x10,0xc2,0x00,0x2a,0x24,0x02,0x00,0x6c,0x10,0xc2,0x00,0x05, ++0x24,0x02,0x00,0x5a,0x10,0xc2,0x00,0x1f,0x24,0x02,0x00,0x68,0x10,0xc2,0x00,0x13, ++0x24,0x02,0xff,0xfc,0x24,0x02,0xff,0xfc,0x26,0x43,0x00,0x03,0x00,0x62,0x90,0x24, ++0x32,0x22,0x00,0x02,0x8e,0x47,0x00,0x00,0x00,0x00,0x30,0x21,0x10,0x40,0x00,0x03, ++0x26,0x52,0x00,0x04,0x00,0xe0,0x10,0x21,0x00,0x02,0x37,0xc3,0x02,0x00,0x20,0x21, ++0xaf,0xa9,0x00,0x10,0xaf,0xb4,0x00,0x14,0xaf,0xa8,0x00,0x18,0x0c,0x00,0x2f,0x91, ++0xaf,0xb1,0x00,0x1c,0x08,0x00,0x2e,0xac,0x00,0x40,0x80,0x21,0x26,0x43,0x00,0x03, ++0x00,0x62,0x90,0x24,0x32,0x22,0x00,0x02,0x96,0x47,0x00,0x02,0x00,0x00,0x30,0x21, ++0x10,0x40,0xff,0xf2,0x26,0x52,0x00,0x04,0x00,0x07,0x14,0x00,0x08,0x00,0x2e,0xc6, ++0x00,0x02,0x3c,0x03,0x26,0x42,0x00,0x03,0x24,0x03,0xff,0xfc,0x00,0x43,0x90,0x24, ++0x8e,0x47,0x00,0x00,0x00,0x00,0x30,0x21,0x08,0x00,0x2e,0xc7,0x26,0x52,0x00,0x04, ++0x26,0x42,0x00,0x07,0x24,0x03,0xff,0xf8,0x00,0x43,0x90,0x24,0x8e,0x46,0x00,0x00, ++0x8e,0x47,0x00,0x04,0x08,0x00,0x2e,0xc7,0x26,0x52,0x00,0x08,0x08,0x00,0x2e,0xb4, ++0x36,0x31,0x00,0x02,0x26,0x44,0x00,0x03,0x24,0x02,0xff,0xfc,0x00,0x82,0x90,0x24, ++0x8e,0x44,0x00,0x00,0x02,0x15,0x10,0x23,0x26,0x52,0x00,0x04,0x08,0x00,0x2e,0x42, ++0xac,0x82,0x00,0x00,0x08,0x00,0x2e,0xb4,0x24,0x09,0x00,0x08,0x24,0x02,0xff,0xff, ++0x12,0x82,0x00,0x11,0x00,0x00,0x00,0x00,0x26,0x43,0x00,0x03,0x24,0x02,0xff,0xfc, ++0x00,0x62,0x90,0x24,0x8e,0x47,0x00,0x00,0x02,0x00,0x20,0x21,0x24,0x02,0x00,0x10, ++0x00,0x00,0x30,0x21,0xaf,0xa2,0x00,0x10,0xaf,0xb4,0x00,0x14,0xaf,0xa8,0x00,0x18, ++0x0c,0x00,0x2f,0x91,0xaf,0xb1,0x00,0x1c,0x8f,0xa5,0x00,0x44,0x00,0x40,0x80,0x21, ++0x08,0x00,0x2e,0x42,0x26,0x52,0x00,0x04,0x24,0x14,0x00,0x08,0x08,0x00,0x2e,0xf6, ++0x36,0x31,0x00,0x01,0x26,0x42,0x00,0x03,0x24,0x03,0xff,0xfc,0x00,0x43,0x90,0x24, ++0x8e,0x53,0x00,0x00,0x00,0x00,0x00,0x00,0x12,0x60,0x00,0x23,0x26,0x52,0x00,0x04, ++0x02,0x60,0x20,0x21,0x0c,0x00,0x30,0x5f,0x01,0x00,0x28,0x21,0x00,0x40,0x20,0x21, ++0x32,0x22,0x00,0x10,0x14,0x40,0x00,0x09,0x00,0x94,0x10,0x2a,0x10,0x40,0x00,0x07, ++0x26,0x94,0xff,0xff,0x24,0x03,0x00,0x20,0x00,0x94,0x10,0x2a,0xa2,0x03,0x00,0x00, ++0x26,0x94,0xff,0xff,0x14,0x40,0xff,0xfc,0x26,0x10,0x00,0x01,0x18,0x80,0x00,0x07, ++0x00,0x80,0x18,0x21,0x92,0x62,0x00,0x00,0x24,0x63,0xff,0xff,0x26,0x73,0x00,0x01, ++0xa2,0x02,0x00,0x00,0x14,0x60,0xff,0xfb,0x26,0x10,0x00,0x01,0x00,0x94,0x10,0x2a, ++0x10,0x40,0xff,0x83,0x26,0x94,0xff,0xff,0x24,0x03,0x00,0x20,0x00,0x94,0x10,0x2a, ++0xa2,0x03,0x00,0x00,0x26,0x94,0xff,0xff,0x14,0x40,0xff,0xfc,0x26,0x10,0x00,0x01, ++0x08,0x00,0x2e,0xac,0x00,0x00,0x00,0x00,0x3c,0x02,0x80,0x01,0x08,0x00,0x2f,0x10, ++0x24,0x53,0x08,0x04,0x24,0x02,0x00,0x25,0xa2,0x02,0x00,0x00,0x8f,0xa5,0x00,0x44, ++0x00,0x00,0x00,0x00,0x80,0xa2,0x00,0x00,0x90,0xa3,0x00,0x00,0x10,0x40,0x00,0x03, ++0x26,0x10,0x00,0x01,0x08,0x00,0x2e,0x40,0xa2,0x03,0x00,0x00,0x24,0xa5,0xff,0xff, ++0x08,0x00,0x2e,0x42,0xaf,0xa5,0x00,0x44,0x80,0xa6,0x00,0x00,0x24,0xa5,0x00,0x01, ++0x08,0x00,0x2e,0x86,0xaf,0xa5,0x00,0x44,0x24,0xa5,0x00,0x01,0xaf,0xa5,0x00,0x44, ++0x90,0xa4,0x00,0x00,0x3c,0x02,0x80,0x01,0x24,0x42,0x02,0x1c,0x00,0x44,0x10,0x21, ++0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x04,0x14,0x60,0x00,0x0f, ++0x00,0x04,0x16,0x00,0x00,0x02,0x16,0x03,0x24,0x03,0x00,0x2a,0x10,0x43,0x00,0x04, ++0x26,0x42,0x00,0x03,0x29,0x02,0x00,0x00,0x08,0x00,0x2e,0x7b,0x00,0x02,0x40,0x0b, ++0x24,0x03,0xff,0xfc,0x00,0x43,0x90,0x24,0x24,0xa5,0x00,0x01,0x8e,0x48,0x00,0x00, ++0xaf,0xa5,0x00,0x44,0x08,0x00,0x2f,0x55,0x26,0x52,0x00,0x04,0x0c,0x00,0x2f,0x75, ++0x27,0xa4,0x00,0x44,0x8f,0xa5,0x00,0x44,0x08,0x00,0x2f,0x55,0x00,0x40,0x40,0x21, ++0x24,0x03,0xff,0xfc,0x00,0x43,0x90,0x24,0x8e,0x54,0x00,0x00,0x24,0xe5,0x00,0x01, ++0xaf,0xa5,0x00,0x44,0x06,0x81,0xff,0x0d,0x26,0x52,0x00,0x04,0x00,0x14,0xa0,0x23, ++0x08,0x00,0x2e,0x77,0x36,0x31,0x00,0x10,0x0c,0x00,0x2f,0x75,0x27,0xa4,0x00,0x44, ++0x8f,0xa5,0x00,0x44,0x08,0x00,0x2e,0x77,0x00,0x40,0xa0,0x21,0x08,0x00,0x2e,0x51, ++0x36,0x31,0x00,0x01,0x8c,0x86,0x00,0x00,0x3c,0x02,0x80,0x01,0x00,0x80,0x48,0x21, ++0x90,0xc3,0x00,0x00,0x24,0x44,0x02,0x1c,0x00,0x64,0x18,0x21,0x90,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x04,0x10,0x40,0x00,0x10,0x00,0x00,0x38,0x21, ++0x00,0x80,0x40,0x21,0x24,0xc2,0x00,0x01,0x80,0xc5,0x00,0x00,0xad,0x22,0x00,0x00, ++0x90,0x43,0x00,0x00,0x00,0x40,0x30,0x21,0x00,0x07,0x10,0x80,0x00,0x68,0x18,0x21, ++0x90,0x64,0x00,0x00,0x00,0x47,0x10,0x21,0x00,0x02,0x10,0x40,0x00,0x45,0x10,0x21, ++0x30,0x84,0x00,0x04,0x14,0x80,0xff,0xf3,0x24,0x47,0xff,0xd0,0x03,0xe0,0x00,0x08, ++0x00,0xe0,0x10,0x21,0x27,0xbd,0xff,0x98,0xaf,0xb2,0x00,0x50,0x8f,0xb2,0x00,0x84, ++0x3c,0x02,0x80,0x01,0xaf,0xb4,0x00,0x58,0x32,0x43,0x00,0x40,0xaf,0xb1,0x00,0x4c, ++0xaf,0xb0,0x00,0x48,0xaf,0xb7,0x00,0x64,0xaf,0xb6,0x00,0x60,0xaf,0xb5,0x00,0x5c, ++0xaf,0xb3,0x00,0x54,0x00,0x80,0x68,0x21,0x00,0xc0,0x70,0x21,0x00,0xe0,0x78,0x21, ++0x8f,0xb0,0x00,0x78,0x8f,0xb8,0x00,0x7c,0x8f,0xb1,0x00,0x80,0x10,0x60,0x00,0x03, ++0x24,0x54,0x08,0x0c,0x3c,0x02,0x80,0x01,0x24,0x54,0x08,0x34,0x32,0x42,0x00,0x10, ++0x10,0x40,0x00,0x04,0x26,0x02,0xff,0xfe,0x24,0x02,0xff,0xfe,0x02,0x42,0x90,0x24, ++0x26,0x02,0xff,0xfe,0x2c,0x42,0x00,0x23,0x10,0x40,0x00,0x5d,0x00,0x00,0x18,0x21, ++0x32,0x42,0x00,0x01,0x24,0x15,0x00,0x30,0x24,0x03,0x00,0x20,0x32,0x44,0x00,0x02, ++0x00,0x62,0xa8,0x0a,0x10,0x80,0x00,0x07,0x00,0x00,0xb8,0x21,0x05,0xc0,0x00,0x96, ++0x32,0x42,0x00,0x04,0x10,0x40,0x00,0x90,0x32,0x42,0x00,0x08,0x24,0x17,0x00,0x2b, ++0x27,0x18,0xff,0xff,0x32,0x56,0x00,0x20,0x12,0xc0,0x00,0x07,0x01,0xcf,0x10,0x25, ++0x24,0x02,0x00,0x10,0x12,0x02,0x00,0x86,0x27,0x03,0xff,0xff,0x3a,0x02,0x00,0x08, ++0x00,0x62,0xc0,0x0a,0x01,0xcf,0x10,0x25,0x14,0x40,0x00,0x55,0x00,0x00,0xc8,0x21, ++0x24,0x02,0x00,0x30,0x24,0x19,0x00,0x01,0xa3,0xa2,0x00,0x00,0x02,0x39,0x10,0x2a, ++0x03,0x22,0x88,0x0b,0x32,0x43,0x00,0x11,0x14,0x60,0x00,0x0a,0x03,0x11,0xc0,0x23, ++0x03,0x00,0x10,0x21,0x18,0x40,0x00,0x07,0x27,0x18,0xff,0xff,0x24,0x03,0x00,0x20, ++0x03,0x00,0x10,0x21,0xa1,0xa3,0x00,0x00,0x27,0x18,0xff,0xff,0x1c,0x40,0xff,0xfc, ++0x25,0xad,0x00,0x01,0x12,0xe0,0x00,0x03,0x00,0x00,0x00,0x00,0xa1,0xb7,0x00,0x00, ++0x25,0xad,0x00,0x01,0x12,0xc0,0x00,0x07,0x32,0x42,0x00,0x10,0x24,0x02,0x00,0x08, ++0x12,0x02,0x00,0x38,0x24,0x02,0x00,0x10,0x12,0x02,0x00,0x30,0x24,0x02,0x00,0x30, ++0x32,0x42,0x00,0x10,0x14,0x40,0x00,0x0a,0x03,0x31,0x10,0x2a,0x03,0x00,0x10,0x21, ++0x18,0x40,0x00,0x06,0x27,0x18,0xff,0xff,0x03,0x00,0x10,0x21,0xa1,0xb5,0x00,0x00, ++0x27,0x18,0xff,0xff,0x1c,0x40,0xff,0xfc,0x25,0xad,0x00,0x01,0x03,0x31,0x10,0x2a, ++0x10,0x40,0x00,0x07,0x26,0x31,0xff,0xff,0x24,0x03,0x00,0x30,0x03,0x31,0x10,0x2a, ++0xa1,0xa3,0x00,0x00,0x26,0x31,0xff,0xff,0x14,0x40,0xff,0xfc,0x25,0xad,0x00,0x01, ++0x03,0x20,0x10,0x21,0x18,0x40,0x00,0x08,0x27,0x39,0xff,0xff,0x03,0xb9,0x10,0x21, ++0x90,0x43,0x00,0x00,0x03,0x20,0x20,0x21,0x27,0x39,0xff,0xff,0xa1,0xa3,0x00,0x00, ++0x1c,0x80,0xff,0xfa,0x25,0xad,0x00,0x01,0x03,0x00,0x10,0x21,0x18,0x40,0x00,0x07, ++0x27,0x18,0xff,0xff,0x24,0x03,0x00,0x20,0x03,0x00,0x10,0x21,0xa1,0xa3,0x00,0x00, ++0x27,0x18,0xff,0xff,0x1c,0x40,0xff,0xfc,0x25,0xad,0x00,0x01,0x01,0xa0,0x18,0x21, ++0x7b,0xb6,0x03,0x3c,0x7b,0xb4,0x02,0xfc,0x7b,0xb2,0x02,0xbc,0x7b,0xb0,0x02,0x7c, ++0x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x68,0xa1,0xa2,0x00,0x00, ++0x92,0x83,0x00,0x21,0x25,0xad,0x00,0x01,0xa1,0xa3,0x00,0x00,0x08,0x00,0x2f,0xe4, ++0x25,0xad,0x00,0x01,0x24,0x02,0x00,0x30,0x08,0x00,0x30,0x17,0xa1,0xa2,0x00,0x00, ++0x01,0xcf,0x10,0x25,0x10,0x40,0xff,0xad,0x00,0x00,0x60,0x21,0x00,0x0e,0x18,0x02, ++0x03,0x3d,0x98,0x21,0x00,0x60,0x20,0x21,0x01,0xe0,0x38,0x21,0x10,0x60,0x00,0x04, ++0x27,0x39,0x00,0x01,0x00,0x70,0x00,0x1b,0x00,0x00,0x20,0x12,0x00,0x00,0x18,0x10, ++0x00,0x80,0x48,0x21,0x00,0xe0,0x30,0x21,0x01,0x80,0x70,0x21,0x01,0x80,0x28,0x21, ++0x10,0x00,0x00,0x06,0x24,0x04,0x00,0x21,0x00,0x03,0x08,0x40,0x00,0x03,0x2f,0xc2, ++0x00,0x22,0x18,0x25,0x00,0x06,0x30,0x40,0x00,0x0e,0x70,0x40,0x14,0xa0,0x00,0x02, ++0x00,0x70,0x10,0x2b,0x14,0x40,0x00,0x03,0x24,0x84,0xff,0xff,0x00,0x70,0x18,0x23, ++0x25,0xce,0x00,0x01,0x14,0x80,0xff,0xf4,0x00,0x06,0x17,0xc2,0x02,0x83,0x18,0x21, ++0x01,0xc0,0x38,0x21,0x00,0x00,0x50,0x21,0x00,0x09,0x20,0x00,0x00,0x00,0x28,0x21, ++0x90,0x66,0x00,0x00,0x00,0x8a,0x70,0x25,0x00,0xa7,0x78,0x25,0x01,0xcf,0x10,0x25, ++0x14,0x40,0xff,0xda,0xa2,0x66,0x00,0x00,0x08,0x00,0x2f,0xcc,0x02,0x39,0x10,0x2a, ++0x08,0x00,0x2f,0xc5,0x27,0x18,0xff,0xfe,0x10,0x40,0xff,0x73,0x32,0x56,0x00,0x20, ++0x08,0x00,0x2f,0xbc,0x24,0x17,0x00,0x20,0x00,0x0f,0x78,0x23,0x00,0x0e,0x70,0x23, ++0x00,0x0f,0x10,0x2b,0x01,0xc2,0x70,0x23,0x08,0x00,0x2f,0xbc,0x24,0x17,0x00,0x2d, ++0x80,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x06,0x00,0x80,0x18,0x21, ++0x24,0x63,0x00,0x01,0x80,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xfc, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x64,0x10,0x23,0x24,0xa5,0xff,0xff, ++0x24,0x02,0xff,0xff,0x10,0xa2,0x00,0x0d,0x00,0x80,0x18,0x21,0x80,0x82,0x00,0x00, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x09,0x00,0x00,0x00,0x00,0x24,0x06,0xff,0xff, ++0x24,0xa5,0xff,0xff,0x10,0xa6,0x00,0x05,0x24,0x63,0x00,0x01,0x80,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xfa,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x00,0x64,0x10,0x23,0x80,0x82,0x00,0x00,0x90,0x88,0x00,0x00,0x10,0x40,0x00,0x17, ++0x00,0x00,0x48,0x21,0x90,0xa3,0x00,0x00,0x00,0xa0,0x30,0x21,0x10,0x60,0x00,0x0b, ++0x00,0x60,0x38,0x21,0x00,0x08,0x16,0x00,0x00,0x02,0x46,0x03,0x00,0x07,0x16,0x00, ++0x00,0x02,0x16,0x03,0x11,0x02,0x00,0x05,0x24,0xc6,0x00,0x01,0x90,0xc3,0x00,0x00, ++0x00,0x00,0x00,0x00,0x14,0x60,0xff,0xf9,0x00,0x60,0x38,0x21,0x00,0x03,0x16,0x00, ++0x10,0x40,0x00,0x06,0x00,0x00,0x00,0x00,0x24,0x84,0x00,0x01,0x90,0x82,0x00,0x00, ++0x25,0x29,0x00,0x01,0x14,0x40,0xff,0xeb,0x00,0x40,0x40,0x21,0x03,0xe0,0x00,0x08, ++0x01,0x20,0x10,0x21,0x80,0x82,0x00,0x00,0x90,0x87,0x00,0x00,0x10,0x40,0x00,0x17, ++0x00,0x00,0x18,0x21,0x90,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x1e,0x00, ++0x10,0x60,0x00,0x0c,0x00,0xa0,0x30,0x21,0x00,0x07,0x16,0x00,0x00,0x02,0x3e,0x03, ++0x00,0x03,0x16,0x03,0x10,0xe2,0x00,0x0d,0x00,0x80,0x18,0x21,0x24,0xc6,0x00,0x01, ++0x90,0xc2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x1e,0x00,0x14,0x60,0xff,0xf9, ++0x00,0x03,0x16,0x03,0x24,0x84,0x00,0x01,0x90,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x14,0x40,0xff,0xec,0x00,0x40,0x38,0x21,0x00,0x00,0x18,0x21,0x03,0xe0,0x00,0x08, ++0x00,0x60,0x10,0x21,0x27,0xbd,0xff,0xe0,0xaf,0xb0,0x00,0x10,0x8f,0x90,0xc5,0x5c, ++0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x18,0x00,0x84,0x80,0x0b,0x00,0x00,0x30,0x21, ++0x12,0x00,0x00,0x0a,0x00,0xa0,0x88,0x21,0x0c,0x00,0x30,0x71,0x02,0x00,0x20,0x21, ++0x02,0x02,0x80,0x21,0x82,0x02,0x00,0x00,0x02,0x20,0x28,0x21,0x02,0x00,0x20,0x21, ++0x14,0x40,0x00,0x07,0x00,0x00,0x30,0x21,0xaf,0x80,0xc5,0x5c,0x8f,0xbf,0x00,0x18, ++0x7b,0xb0,0x00,0xbc,0x00,0xc0,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20, ++0x0c,0x00,0x30,0x8d,0x00,0x00,0x00,0x00,0x00,0x40,0x18,0x21,0x10,0x40,0x00,0x07, ++0x02,0x00,0x30,0x21,0x80,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x03, ++0x00,0x00,0x00,0x00,0xa0,0x60,0x00,0x00,0x24,0x63,0x00,0x01,0xaf,0x83,0xc5,0x5c, ++0x08,0x00,0x30,0xbb,0x00,0x00,0x00,0x00,0x24,0xc6,0xff,0xff,0x24,0x02,0xff,0xff, ++0x10,0xc2,0x00,0x05,0x00,0x80,0x18,0x21,0x24,0xc6,0xff,0xff,0xa0,0x65,0x00,0x00, ++0x14,0xc2,0xff,0xfd,0x24,0x63,0x00,0x01,0x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21, ++0x24,0xc6,0xff,0xff,0x24,0x02,0xff,0xff,0x10,0xc2,0x00,0x08,0x00,0x80,0x18,0x21, ++0x24,0x07,0xff,0xff,0x90,0xa2,0x00,0x00,0x24,0xc6,0xff,0xff,0x24,0xa5,0x00,0x01, ++0xa0,0x62,0x00,0x00,0x14,0xc7,0xff,0xfb,0x24,0x63,0x00,0x01,0x03,0xe0,0x00,0x08, ++0x00,0x80,0x10,0x21,0x00,0x80,0x18,0x21,0x90,0xa2,0x00,0x00,0x24,0xa5,0x00,0x01, ++0xa0,0x82,0x00,0x00,0x14,0x40,0xff,0xfc,0x24,0x84,0x00,0x01,0x03,0xe0,0x00,0x08, ++0x00,0x60,0x10,0x21,0x90,0x83,0x00,0x00,0x90,0xa2,0x00,0x00,0x24,0x84,0x00,0x01, ++0x00,0x62,0x10,0x23,0x00,0x02,0x16,0x00,0x00,0x02,0x16,0x03,0x14,0x40,0x00,0x03, ++0x24,0xa5,0x00,0x01,0x14,0x60,0xff,0xf7,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x10,0x21,0x93,0x85,0x88,0x6d, ++0x24,0x02,0x00,0x01,0x14,0xa2,0x00,0x53,0x00,0x80,0x40,0x21,0x8c,0x89,0x00,0x04, ++0x3c,0x02,0xb0,0x01,0x01,0x22,0x30,0x21,0x8c,0xc3,0x00,0x04,0x3c,0x02,0x01,0x00, ++0x00,0x62,0x10,0x24,0x10,0x40,0x00,0x4b,0x30,0x62,0x00,0x08,0x10,0x45,0x00,0x59, ++0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x38,0x24,0x03,0x00,0xb4,0x30,0x44,0x00,0xff, ++0x10,0x83,0x00,0x61,0x24,0x02,0x00,0xc4,0x10,0x82,0x00,0x54,0x24,0x02,0x00,0x94, ++0x10,0x82,0x00,0x45,0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x38,0x00,0x00,0x00,0x00, ++0x30,0x47,0xff,0xff,0x30,0xe3,0x40,0xff,0x24,0x02,0x40,0x88,0x14,0x62,0x00,0x39, ++0x30,0xe3,0x03,0x00,0x24,0x02,0x03,0x00,0x10,0x62,0x00,0x38,0x00,0x00,0x00,0x00, ++0x94,0xc2,0x00,0x56,0x00,0x00,0x00,0x00,0x30,0x47,0xff,0xff,0x30,0xe2,0x00,0x80, ++0x14,0x40,0x00,0x30,0x3c,0x02,0xb0,0x01,0x01,0x22,0x30,0x21,0x94,0xc3,0x00,0x60, ++0x24,0x02,0x00,0x08,0x14,0x43,0x00,0x3b,0x00,0x00,0x00,0x00,0x90,0xc2,0x00,0x62, ++0x24,0x03,0x00,0x04,0x00,0x02,0x39,0x02,0x10,0xe3,0x00,0x15,0x24,0x02,0x00,0x06, ++0x14,0xe2,0x00,0x34,0x00,0x00,0x00,0x00,0x8d,0x05,0x01,0xac,0x94,0xc4,0x00,0x66, ++0x27,0x82,0x92,0x48,0x00,0x05,0x28,0x80,0x30,0x87,0xff,0xff,0x00,0xa2,0x28,0x21, ++0x00,0x07,0x1a,0x00,0x8c,0xa4,0x00,0x00,0x00,0x07,0x12,0x02,0x00,0x43,0x10,0x25, ++0x24,0x42,0x00,0x5e,0x24,0x03,0xc0,0x00,0x30,0x47,0xff,0xff,0x00,0x83,0x20,0x24, ++0x00,0x87,0x20,0x25,0xac,0xa4,0x00,0x00,0x08,0x00,0x31,0x61,0xad,0x07,0x00,0x10, ++0x8d,0x05,0x01,0xac,0x94,0xc4,0x00,0x64,0x27,0x82,0x92,0x48,0x00,0x05,0x28,0x80, ++0x30,0x87,0xff,0xff,0x00,0xa2,0x28,0x21,0x00,0x07,0x1a,0x00,0x8c,0xa4,0x00,0x00, ++0x00,0x07,0x12,0x02,0x00,0x43,0x10,0x25,0x24,0x42,0x00,0x36,0x3c,0x03,0xff,0xff, ++0x30,0x47,0xff,0xff,0x00,0x83,0x20,0x24,0x00,0x87,0x20,0x25,0xac,0xa4,0x00,0x00, ++0xad,0x07,0x00,0x10,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x50, ++0x08,0x00,0x31,0x1f,0x30,0x47,0xff,0xff,0x8d,0x04,0x01,0xac,0x27,0x83,0x92,0x48, ++0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x00,0x3c,0x03,0xff,0xff, ++0x00,0x43,0x10,0x24,0x34,0x42,0x00,0x2e,0xac,0x82,0x00,0x00,0x24,0x03,0x00,0x2e, ++0xad,0x03,0x00,0x10,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8d,0x04,0x01,0xac, ++0x27,0x83,0x92,0x48,0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x00, ++0x3c,0x03,0xff,0xff,0x00,0x43,0x10,0x24,0x34,0x42,0x00,0x0e,0x24,0x03,0x00,0x0e, ++0x08,0x00,0x31,0x60,0xac,0x82,0x00,0x00,0x8d,0x04,0x01,0xac,0x27,0x83,0x92,0x48, ++0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x00,0x3c,0x03,0xff,0xff, ++0x00,0x43,0x10,0x24,0x34,0x42,0x00,0x14,0x24,0x03,0x00,0x14,0x08,0x00,0x31,0x60, ++0xac,0x82,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xc6,0x00,0xff, ++0x00,0x06,0x48,0x40,0x01,0x26,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x8b,0xc5,0x70, ++0x27,0x83,0xc5,0x76,0x00,0x4b,0x40,0x21,0x00,0x43,0x10,0x21,0x94,0x47,0x00,0x00, ++0x30,0xa2,0x3f,0xff,0x10,0xe2,0x00,0x29,0x30,0x8a,0xff,0xff,0x95,0x02,0x00,0x02, ++0x24,0x03,0x00,0x01,0x00,0x02,0x11,0x82,0x30,0x42,0x00,0x01,0x10,0x43,0x00,0x18, ++0x00,0x00,0x00,0x00,0x01,0x26,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x4b,0x30,0x21, ++0x94,0xc4,0x00,0x02,0x27,0x83,0xc5,0x76,0x27,0x85,0xc5,0x74,0x00,0x45,0x28,0x21, ++0x30,0x84,0xff,0xdf,0x00,0x43,0x10,0x21,0xa4,0xc4,0x00,0x02,0xa4,0x40,0x00,0x00, ++0xa4,0xa0,0x00,0x00,0x94,0xc3,0x00,0x02,0x3c,0x04,0xb0,0x01,0x01,0x44,0x20,0x21, ++0x30,0x63,0xff,0xbf,0xa4,0xc3,0x00,0x02,0xa0,0xc0,0x00,0x00,0x8c,0x82,0x00,0x04, ++0x24,0x03,0xf0,0xff,0x00,0x43,0x10,0x24,0x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x04, ++0x24,0x02,0xc0,0x00,0x91,0x04,0x00,0x01,0x00,0xa2,0x10,0x24,0x00,0x47,0x28,0x25, ++0x3c,0x03,0xb0,0x01,0x24,0x02,0x00,0x02,0x14,0x82,0xff,0xe2,0x01,0x43,0x18,0x21, ++0xac,0x65,0x00,0x00,0x08,0x00,0x31,0x8e,0x01,0x26,0x10,0x21,0x08,0x00,0x31,0x8e, ++0x01,0x26,0x10,0x21,0x93,0x83,0x88,0x6d,0x24,0x02,0x00,0x01,0x14,0x62,0x00,0x0d, ++0x3c,0x02,0xb0,0x01,0x8c,0x84,0x00,0x04,0x3c,0x06,0xb0,0x09,0x00,0x82,0x20,0x21, ++0x8c,0x85,0x00,0x08,0x8c,0x83,0x00,0x04,0x3c,0x02,0x01,0x00,0x34,0xc6,0x01,0x00, ++0x00,0x62,0x18,0x24,0x14,0x60,0x00,0x05,0x30,0xa5,0x20,0x00,0x24,0x02,0x00,0x06, ++0xa0,0xc2,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x09, ++0x10,0xa0,0xff,0xfc,0x34,0x63,0x01,0x00,0x24,0x02,0x00,0x0e,0x08,0x00,0x31,0xc1, ++0xa0,0x62,0x00,0x00,0x3c,0x02,0xb0,0x01,0x30,0xa5,0xff,0xff,0x00,0xa2,0x28,0x21, ++0x8c,0xa3,0x00,0x00,0x3c,0x02,0x10,0x00,0x00,0x80,0x30,0x21,0x00,0x62,0x18,0x24, ++0x8c,0xa2,0x00,0x04,0x10,0x60,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0x80,0x00, ++0x10,0x40,0x00,0x13,0x00,0x00,0x00,0x00,0x8c,0xc2,0x01,0xa8,0x00,0x00,0x00,0x00, ++0x24,0x44,0x00,0x01,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40,0x00,0x83,0x10,0x0a, ++0x93,0x83,0x88,0x6c,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x82,0x20,0x23, ++0x24,0x63,0xff,0xff,0xac,0xc4,0x01,0xa8,0xa3,0x83,0x88,0x6c,0x8c,0xc4,0x01,0xac, ++0x8c,0xc2,0x01,0xa8,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x26,0x00,0x02,0x10,0x2b, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x73, ++0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x04, ++0x00,0x00,0x00,0x00,0xa3,0x80,0x88,0x6d,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x24,0x02,0x00,0x01,0xa3,0x82,0x88,0x6d,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00, ++0x8c,0x82,0x00,0x04,0x3c,0x05,0xb0,0x01,0x00,0x80,0x50,0x21,0x00,0x45,0x10,0x21, ++0x8c,0x43,0x00,0x04,0x24,0x02,0x00,0x05,0x00,0x03,0x1a,0x02,0x30,0x69,0x00,0x0f, ++0x11,0x22,0x00,0x0b,0x24,0x02,0x00,0x07,0x11,0x22,0x00,0x09,0x24,0x02,0x00,0x0a, ++0x11,0x22,0x00,0x07,0x24,0x02,0x00,0x0b,0x11,0x22,0x00,0x05,0x24,0x02,0x00,0x01, ++0x93,0x83,0x88,0x6c,0x3c,0x04,0xb0,0x06,0x10,0x62,0x00,0x03,0x34,0x84,0x80,0x18, ++0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x02,0x17,0x02,0x14,0x40,0xff,0xfa,0x00,0x00,0x00,0x00,0x8d,0x43,0x01,0xa8, ++0x27,0x82,0x92,0x48,0x00,0x03,0x18,0x80,0x00,0x6a,0x20,0x21,0x8c,0x87,0x00,0xa8, ++0x00,0x62,0x18,0x21,0x8c,0x68,0x00,0x00,0x00,0xe5,0x28,0x21,0x8c,0xa9,0x00,0x00, ++0x3c,0x02,0xff,0xff,0x27,0x83,0x93,0x48,0x01,0x22,0x10,0x24,0x00,0x48,0x10,0x25, ++0xac,0xa2,0x00,0x00,0x8d,0x44,0x01,0xa8,0x00,0x07,0x30,0xc2,0x3c,0x02,0x00,0x80, ++0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x00,0x06,0x32,0x00,0x8c,0xa9,0x00,0x04, ++0x00,0xc2,0x30,0x25,0x8c,0x82,0x00,0x00,0x3c,0x03,0x80,0x00,0x01,0x22,0x10,0x25, ++0x00,0x43,0x10,0x25,0xac,0xa2,0x00,0x04,0xaf,0x87,0xc5,0x60,0x8c,0xa2,0x00,0x00, ++0x00,0x00,0x00,0x00,0xaf,0x82,0xc5,0x68,0x8c,0xa3,0x00,0x04,0x3c,0x01,0xb0,0x07, ++0xac,0x26,0x80,0x18,0x8d,0x42,0x01,0xa8,0xaf,0x83,0xc5,0x64,0x93,0x85,0x88,0x6c, ++0x24,0x44,0x00,0x01,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40,0x00,0x83,0x10,0x0a, ++0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x24,0xa5,0xff,0xff,0x00,0x82,0x20,0x23, ++0xad,0x44,0x01,0xa8,0xa3,0x85,0x88,0x6c,0x08,0x00,0x32,0x0c,0x00,0x00,0x00,0x00, ++0x3c,0x05,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0xa5,0x00,0x20,0x24,0x42,0xc9,0x10, ++0xac,0xa2,0x00,0x00,0x24,0x02,0x00,0x02,0x24,0x03,0x00,0x20,0xac,0x82,0x00,0x64, ++0x3c,0x02,0x80,0x01,0xac,0x83,0x00,0x60,0xac,0x80,0x00,0x00,0xac,0x80,0x00,0x04, ++0xac,0x80,0x00,0x08,0xac,0x80,0x00,0x4c,0xac,0x80,0x00,0x50,0xac,0x80,0x00,0x54, ++0xac,0x80,0x00,0x0c,0xac,0x80,0x00,0x58,0xa0,0x80,0x00,0x5c,0x24,0x42,0xc9,0xd4, ++0x24,0x83,0x00,0x68,0x24,0x05,0x00,0x0f,0x24,0xa5,0xff,0xff,0xac,0x62,0x00,0x00, ++0x04,0xa1,0xff,0xfd,0x24,0x63,0x00,0x04,0x3c,0x02,0x80,0x01,0x24,0x42,0xcb,0x04, ++0xac,0x82,0x00,0x78,0x3c,0x03,0x80,0x01,0x3c,0x02,0x80,0x01,0x24,0x63,0xcc,0x90, ++0x24,0x42,0xcb,0xfc,0xac,0x83,0x00,0x88,0xac,0x82,0x00,0x98,0x3c,0x03,0x80,0x01, ++0x3c,0x02,0x80,0x01,0x24,0x63,0xcd,0x38,0x24,0x42,0xce,0x50,0xac,0x83,0x00,0xa0, ++0xac,0x82,0x00,0xa4,0xa0,0x80,0x01,0xba,0xac,0x80,0x01,0xa8,0xac,0x80,0x01,0xac, ++0xac,0x80,0x01,0xb0,0xac,0x80,0x01,0xb4,0xa0,0x80,0x01,0xb8,0x03,0xe0,0x00,0x08, ++0xa0,0x80,0x01,0xb9,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20, ++0x24,0x42,0xc9,0xd4,0x03,0xe0,0x00,0x08,0xac,0x62,0x00,0x00,0x3c,0x03,0xb0,0x03, ++0x3c,0x02,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x63,0x00,0x20,0x24,0x42,0xc9,0xec, ++0xaf,0xb0,0x00,0x10,0xac,0x62,0x00,0x00,0xaf,0xbf,0x00,0x14,0x8c,0x83,0x00,0x10, ++0x8f,0x82,0x94,0xe8,0x00,0x80,0x80,0x21,0x3c,0x04,0x80,0x01,0x30,0x46,0x00,0x01, ++0x10,0x60,0x00,0x11,0x24,0x84,0x08,0x64,0x8e,0x02,0x00,0x14,0x00,0x00,0x00,0x00, ++0x10,0x40,0x00,0x0d,0x00,0x00,0x00,0x00,0x8e,0x05,0x00,0x10,0x8e,0x03,0x00,0x14, ++0x8e,0x02,0x00,0x04,0x00,0xa3,0x28,0x21,0x00,0x45,0x10,0x21,0x30,0x43,0x00,0xff, ++0x00,0x03,0x18,0x2b,0x00,0x02,0x12,0x02,0x00,0x43,0x10,0x21,0x00,0x02,0x12,0x00, ++0x30,0x42,0x3f,0xff,0xae,0x02,0x00,0x04,0x14,0xc0,0x00,0x0a,0x00,0x00,0x00,0x00, ++0xae,0x00,0x00,0x00,0xae,0x00,0x00,0x4c,0xae,0x00,0x00,0x50,0xae,0x00,0x00,0x54, ++0xae,0x00,0x00,0x0c,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x18,0x8e,0x05,0x00,0x10,0x8e,0x07,0x00,0x04,0x8e,0x06,0x00,0x14, ++0x0c,0x00,0x1a,0x6b,0x00,0x00,0x00,0x00,0x08,0x00,0x32,0x9d,0xae,0x00,0x00,0x00, ++0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,0x24,0x42,0xca,0xb0, ++0xac,0x62,0x00,0x00,0x8c,0x86,0x00,0x04,0x3c,0x02,0xb0,0x01,0x24,0x03,0x00,0x01, ++0x00,0xc2,0x10,0x21,0x8c,0x45,0x00,0x00,0xac,0x83,0x00,0x4c,0x00,0x05,0x14,0x02, ++0x30,0xa3,0x3f,0xff,0x30,0x42,0x00,0xff,0xac,0x83,0x00,0x10,0xac,0x82,0x00,0x14, ++0x8c,0x83,0x00,0x14,0xac,0x85,0x00,0x40,0x00,0xc3,0x30,0x21,0x03,0xe0,0x00,0x08, ++0xac,0x86,0x00,0x08,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8, ++0x34,0x42,0x00,0x20,0x24,0x63,0xcb,0x04,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14, ++0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x4c,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0a, ++0x00,0x80,0x80,0x21,0xae,0x00,0x00,0x00,0xae,0x00,0x00,0x4c,0xae,0x00,0x00,0x50, ++0xae,0x00,0x00,0x54,0xae,0x00,0x00,0x0c,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x32,0xac,0x00,0x00,0x00,0x00, ++0x08,0x00,0x32,0xce,0xae,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01, ++0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xcb,0x68,0xaf,0xb0,0x00,0x10, ++0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x4c,0x00,0x00,0x00,0x00, ++0x10,0x40,0x00,0x16,0x00,0x80,0x80,0x21,0x8e,0x03,0x00,0x08,0x3c,0x02,0xb0,0x01, ++0x8e,0x04,0x00,0x44,0x00,0x62,0x18,0x21,0x90,0x65,0x00,0x00,0x24,0x02,0x00,0x01, ++0xae,0x02,0x00,0x50,0x30,0xa3,0x00,0xff,0x00,0x03,0x10,0x82,0x00,0x04,0x23,0x02, ++0x30,0x84,0x00,0x0f,0x30,0x42,0x00,0x03,0x00,0x03,0x19,0x02,0xae,0x04,0x00,0x34, ++0xae,0x02,0x00,0x2c,0xae,0x03,0x00,0x30,0xa2,0x05,0x00,0x48,0x8f,0xbf,0x00,0x14, ++0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x32,0xac, ++0x00,0x00,0x00,0x00,0x08,0x00,0x32,0xe6,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03, ++0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xcb,0xfc, ++0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x50, ++0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x16,0x00,0x80,0x80,0x21,0x92,0x03,0x00,0x44, ++0x8e,0x02,0x00,0x40,0x83,0x85,0x95,0x14,0x92,0x04,0x00,0x41,0x30,0x63,0x00,0x01, ++0x00,0x02,0x16,0x02,0xae,0x04,0x00,0x14,0x00,0x00,0x30,0x21,0xae,0x02,0x00,0x18, ++0x10,0xa0,0x00,0x04,0xae,0x03,0x00,0x3c,0x10,0x60,0x00,0x03,0x24,0x02,0x00,0x01, ++0x24,0x06,0x00,0x01,0x24,0x02,0x00,0x01,0xa3,0x86,0x95,0x14,0x8f,0xbf,0x00,0x14, ++0xae,0x02,0x00,0x54,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18, ++0x0c,0x00,0x32,0xda,0x00,0x00,0x00,0x00,0x08,0x00,0x33,0x0b,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20, ++0x24,0x63,0xcc,0x90,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00, ++0x8c,0x82,0x00,0x50,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x1b,0x00,0x80,0x80,0x21, ++0x3c,0x02,0xb0,0x03,0x8c,0x42,0x00,0x00,0x92,0x04,0x00,0x44,0x8e,0x03,0x00,0x40, ++0x83,0x86,0x95,0x14,0x92,0x05,0x00,0x41,0x30,0x42,0x08,0x00,0x30,0x84,0x00,0x01, ++0x00,0x02,0x12,0xc2,0x00,0x03,0x1e,0x02,0x00,0x82,0x20,0x25,0xae,0x05,0x00,0x14, ++0x00,0x00,0x38,0x21,0xae,0x03,0x00,0x18,0x10,0xc0,0x00,0x04,0xae,0x04,0x00,0x3c, ++0x10,0x80,0x00,0x03,0x24,0x02,0x00,0x01,0x24,0x07,0x00,0x01,0x24,0x02,0x00,0x01, ++0xa3,0x87,0x95,0x14,0x8f,0xbf,0x00,0x14,0xae,0x02,0x00,0x54,0x8f,0xb0,0x00,0x10, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x32,0xda,0x00,0x00,0x00,0x00, ++0x08,0x00,0x33,0x30,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01, ++0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xcd,0x38,0xaf,0xb0,0x00,0x10, ++0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x54,0x00,0x00,0x00,0x00, ++0x10,0x40,0x00,0x37,0x00,0x80,0x80,0x21,0x8e,0x04,0x00,0x04,0x8e,0x03,0x00,0x44, ++0x3c,0x02,0x80,0x00,0x3c,0x05,0xb0,0x01,0x34,0x42,0x00,0x10,0x00,0x85,0x20,0x21, ++0x00,0x62,0x18,0x25,0xac,0x83,0x00,0x04,0x8e,0x02,0x00,0x04,0x8e,0x03,0x01,0xac, ++0x02,0x00,0x20,0x21,0x00,0x45,0x10,0x21,0x8c,0x46,0x00,0x00,0x00,0x03,0x18,0x80, ++0x27,0x82,0x92,0x48,0x00,0x62,0x18,0x21,0xac,0x66,0x00,0x00,0x8e,0x02,0x00,0x04, ++0x8e,0x03,0x01,0xac,0x00,0x45,0x10,0x21,0x8c,0x46,0x00,0x04,0x00,0x03,0x18,0x80, ++0x27,0x82,0x93,0x48,0x00,0x62,0x18,0x21,0x0c,0x00,0x30,0xfb,0xac,0x66,0x00,0x00, ++0x8e,0x03,0x01,0xac,0x8e,0x07,0x00,0x04,0x3c,0x06,0xb0,0x03,0x24,0x65,0x00,0x01, ++0x28,0xa4,0x00,0x00,0x24,0x62,0x00,0x40,0x00,0xa4,0x10,0x0a,0x00,0x02,0x11,0x83, ++0x00,0x02,0x11,0x80,0x00,0x03,0x18,0x80,0x00,0xa2,0x28,0x23,0x00,0x70,0x18,0x21, ++0xae,0x05,0x01,0xac,0xac,0x67,0x00,0xa8,0x34,0xc6,0x00,0x30,0x8c,0xc3,0x00,0x00, ++0x93,0x82,0x88,0x6c,0x02,0x00,0x20,0x21,0x24,0x63,0x00,0x01,0x24,0x42,0x00,0x01, ++0xac,0xc3,0x00,0x00,0xa3,0x82,0x88,0x6c,0x0c,0x00,0x32,0x7b,0x00,0x00,0x00,0x00, ++0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18, ++0x0c,0x00,0x33,0x24,0x00,0x00,0x00,0x00,0x08,0x00,0x33,0x5a,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20, ++0x24,0x63,0xce,0x50,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00, ++0x8c,0x82,0x00,0x54,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x37,0x00,0x80,0x80,0x21, ++0x8e,0x04,0x00,0x04,0x8e,0x03,0x00,0x44,0x3c,0x02,0x80,0x00,0x3c,0x05,0xb0,0x01, ++0x34,0x42,0x00,0x10,0x00,0x85,0x20,0x21,0x00,0x62,0x18,0x25,0xac,0x83,0x00,0x04, ++0x8e,0x02,0x00,0x04,0x8e,0x03,0x01,0xac,0x02,0x00,0x20,0x21,0x00,0x45,0x10,0x21, ++0x8c,0x46,0x00,0x00,0x00,0x03,0x18,0x80,0x27,0x82,0x92,0x48,0x00,0x62,0x18,0x21, ++0xac,0x66,0x00,0x00,0x8e,0x02,0x00,0x04,0x8e,0x03,0x01,0xac,0x00,0x45,0x10,0x21, ++0x8c,0x46,0x00,0x04,0x00,0x03,0x18,0x80,0x27,0x82,0x93,0x48,0x00,0x62,0x18,0x21, ++0x0c,0x00,0x30,0xfb,0xac,0x66,0x00,0x00,0x8e,0x03,0x01,0xac,0x8e,0x07,0x00,0x04, ++0x3c,0x06,0xb0,0x03,0x24,0x65,0x00,0x01,0x28,0xa4,0x00,0x00,0x24,0x62,0x00,0x40, ++0x00,0xa4,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x03,0x18,0x80, ++0x00,0xa2,0x28,0x23,0x00,0x70,0x18,0x21,0xae,0x05,0x01,0xac,0xac,0x67,0x00,0xa8, ++0x34,0xc6,0x00,0x30,0x8c,0xc3,0x00,0x00,0x93,0x82,0x88,0x6c,0x02,0x00,0x20,0x21, ++0x24,0x63,0x00,0x01,0x24,0x42,0x00,0x01,0xac,0xc3,0x00,0x00,0xa3,0x82,0x88,0x6c, ++0x0c,0x00,0x32,0x7b,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x33,0x24,0x00,0x00,0x00,0x00, ++0x08,0x00,0x33,0xa0,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01, ++0x34,0x42,0x00,0x20,0x24,0x63,0xcf,0x68,0x27,0xbd,0xff,0xe0,0xac,0x43,0x00,0x00, ++0x3c,0x02,0x80,0x01,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10, ++0xaf,0xbf,0x00,0x1c,0x00,0x80,0x80,0x21,0x24,0x52,0xc9,0xd4,0x00,0x00,0x88,0x21, ++0x3c,0x03,0xb0,0x09,0x34,0x63,0x00,0x06,0x8e,0x06,0x00,0x04,0x90,0x62,0x00,0x00, ++0x00,0x06,0x22,0x02,0x00,0x44,0x10,0x23,0x24,0x44,0x00,0x40,0x28,0x83,0x00,0x00, ++0x24,0x42,0x00,0x7f,0x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80, ++0x24,0x84,0xff,0xff,0x10,0x44,0x00,0x68,0x00,0x00,0x28,0x21,0x3c,0x02,0xb0,0x01, ++0x00,0xc2,0x10,0x21,0x8c,0x44,0x00,0x04,0x3c,0x03,0x7c,0x00,0x34,0x63,0x00,0xf0, ++0x00,0x83,0x18,0x24,0xae,0x04,0x00,0x44,0x8c,0x44,0x00,0x00,0x10,0x60,0x00,0x69, ++0x00,0x00,0x38,0x21,0x3c,0x09,0xb0,0x03,0x3c,0x06,0x7c,0x00,0x35,0x29,0x00,0x99, ++0x3c,0x0a,0xb0,0x01,0x24,0x08,0x00,0x40,0x34,0xc6,0x00,0xf0,0x3c,0x0b,0xff,0xff, ++0x3c,0x0c,0x28,0x38,0x16,0x20,0x00,0x06,0x24,0xa5,0x00,0x01,0x93,0x82,0x88,0xa0, ++0x24,0x11,0x00,0x01,0x24,0x42,0x00,0x01,0xa1,0x22,0x00,0x00,0xa3,0x82,0x88,0xa0, ++0x8e,0x02,0x00,0x04,0x24,0x07,0x00,0x01,0x24,0x42,0x01,0x00,0x30,0x42,0x3f,0xff, ++0xae,0x02,0x00,0x04,0x00,0x4a,0x10,0x21,0x8c,0x43,0x00,0x04,0x00,0x00,0x00,0x00, ++0xae,0x03,0x00,0x44,0x8c,0x44,0x00,0x00,0x10,0xa8,0x00,0x2d,0x00,0x66,0x18,0x24, ++0x14,0x60,0xff,0xec,0x00,0x8b,0x10,0x24,0x14,0x4c,0xff,0xea,0x24,0x02,0x00,0x01, ++0x10,0xe2,0x00,0x2f,0x3c,0x03,0xb0,0x09,0x8e,0x02,0x00,0x44,0x8e,0x04,0x00,0x60, ++0x00,0x02,0x1e,0x42,0x00,0x02,0x12,0x02,0x30,0x42,0x00,0x0f,0x30,0x63,0x00,0x01, ++0xae,0x02,0x00,0x00,0x10,0x44,0x00,0x1a,0xae,0x03,0x00,0x58,0x8e,0x02,0x00,0x64, ++0x8e,0x04,0x00,0x58,0x00,0x00,0x00,0x00,0x10,0x82,0x00,0x05,0x00,0x00,0x00,0x00, ++0xae,0x00,0x00,0x4c,0xae,0x00,0x00,0x50,0xae,0x00,0x00,0x54,0xae,0x00,0x00,0x0c, ++0x8e,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0x80,0x00,0x50,0x10,0x21, ++0x8c,0x42,0x00,0x68,0x00,0x00,0x00,0x00,0x10,0x52,0x00,0x06,0x00,0x00,0x00,0x00, ++0x00,0x40,0xf8,0x09,0x02,0x00,0x20,0x21,0x8e,0x04,0x00,0x58,0x8e,0x03,0x00,0x00, ++0x00,0x00,0x00,0x00,0xae,0x03,0x00,0x60,0x08,0x00,0x33,0xe8,0xae,0x04,0x00,0x64, ++0x8e,0x02,0x00,0x64,0x00,0x00,0x00,0x00,0x14,0x62,0xff,0xe5,0x00,0x00,0x00,0x00, ++0x7a,0x02,0x0d,0x7c,0x8f,0xbf,0x00,0x1c,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc, ++0x00,0x43,0x10,0x26,0x00,0x02,0x10,0x2b,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20, ++0x34,0x63,0x00,0x06,0x8e,0x04,0x00,0x04,0x90,0x62,0x00,0x00,0x00,0x04,0x22,0x02, ++0x00,0x44,0x10,0x23,0x24,0x44,0x00,0x40,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x7f, ++0x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x82,0x20,0x23, ++0x14,0x87,0xff,0xc5,0x00,0x00,0x00,0x00,0x8e,0x03,0x00,0x00,0x00,0x00,0x00,0x00, ++0x2c,0x62,0x00,0x03,0x14,0x40,0x00,0x05,0x24,0x02,0x00,0x0d,0x10,0x62,0x00,0x03, ++0x24,0x02,0x00,0x01,0x08,0x00,0x34,0x48,0xa2,0x02,0x00,0x5c,0x08,0x00,0x34,0x48, ++0xa2,0x00,0x00,0x5c,0x3c,0x02,0xff,0xff,0x00,0x82,0x10,0x24,0x3c,0x03,0x28,0x38, ++0x14,0x43,0xff,0x94,0x24,0x02,0x00,0x01,0x08,0x00,0x34,0x20,0x00,0x00,0x00,0x00, ++0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x34,0x42,0x00,0x20,0x24,0x63,0xd1,0xc0, ++0xac,0x43,0x00,0x00,0x8c,0x83,0x01,0xa8,0x8c,0x82,0x01,0xac,0x00,0x80,0x40,0x21, ++0x10,0x62,0x00,0x20,0x00,0x00,0x20,0x21,0x93,0x82,0x88,0x6d,0x00,0x03,0x28,0x80, ++0x3c,0x07,0xb0,0x06,0x00,0xa8,0x18,0x21,0x24,0x04,0x00,0x01,0x8c,0x66,0x00,0xa8, ++0x10,0x44,0x00,0x1c,0x34,0xe7,0x80,0x18,0x3c,0x05,0xb0,0x01,0xaf,0x86,0xc5,0x60, ++0x00,0xc5,0x28,0x21,0x8c,0xa3,0x00,0x00,0x00,0x06,0x20,0xc2,0x3c,0x02,0x00,0x80, ++0x00,0x04,0x22,0x00,0x00,0x82,0x20,0x25,0xaf,0x83,0xc5,0x68,0x8c,0xa2,0x00,0x04, ++0xac,0xe4,0x00,0x00,0x8d,0x03,0x01,0xa8,0xaf,0x82,0xc5,0x64,0x24,0x64,0x00,0x01, ++0x04,0x80,0x00,0x0a,0x00,0x80,0x10,0x21,0x00,0x02,0x11,0x83,0x8d,0x03,0x01,0xac, ++0x00,0x02,0x11,0x80,0x00,0x82,0x10,0x23,0x00,0x43,0x18,0x26,0xad,0x02,0x01,0xa8, ++0x00,0x03,0x20,0x2b,0x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x08,0x00,0x34,0x92, ++0x24,0x62,0x00,0x40,0x27,0x82,0x92,0x48,0x00,0x06,0x20,0xc2,0x00,0x04,0x22,0x00, ++0x00,0xa2,0x48,0x21,0x3c,0x02,0x00,0x80,0x00,0x82,0x58,0x25,0x93,0x82,0x88,0x6c, ++0x3c,0x0a,0xb0,0x06,0x3c,0x03,0xb0,0x01,0x2c,0x42,0x00,0x02,0x00,0xc3,0x38,0x21, ++0x35,0x4a,0x80,0x18,0x14,0x40,0xff,0xef,0x00,0x00,0x20,0x21,0x8c,0xe5,0x00,0x00, ++0x8d,0x23,0x00,0x00,0x24,0x02,0xc0,0x00,0x00,0xa2,0x10,0x24,0x00,0x43,0x10,0x25, ++0xac,0xe2,0x00,0x00,0x8d,0x04,0x01,0xa8,0x27,0x83,0x93,0x48,0x8c,0xe5,0x00,0x04, ++0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x00,0x3c,0x03,0x80,0x00, ++0x00,0xa2,0x10,0x25,0x00,0x43,0x10,0x25,0xac,0xe2,0x00,0x04,0xaf,0x86,0xc5,0x60, ++0x8c,0xe2,0x00,0x00,0x93,0x85,0x88,0x6c,0xaf,0x82,0xc5,0x68,0x8c,0xe3,0x00,0x04, ++0xad,0x4b,0x00,0x00,0x8d,0x02,0x01,0xa8,0xaf,0x83,0xc5,0x64,0x24,0xa5,0xff,0xff, ++0x24,0x44,0x00,0x01,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40,0x00,0x83,0x10,0x0a, ++0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x82,0x20,0x23,0xad,0x04,0x01,0xa8, ++0xa3,0x85,0x88,0x6c,0x79,0x02,0x0d,0x7c,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x26, ++0x08,0x00,0x34,0x99,0x00,0x02,0x20,0x2b,0x90,0x87,0x00,0x00,0x3c,0x02,0x80,0x01, ++0x27,0xbd,0xff,0xe8,0x24,0x48,0x02,0x1c,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14, ++0x01,0x07,0x18,0x21,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x20, ++0x10,0x40,0x00,0x0a,0x00,0x00,0x80,0x21,0x24,0x84,0x00,0x01,0x90,0x87,0x00,0x00, ++0x00,0x00,0x00,0x00,0x01,0x07,0x18,0x21,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0x20,0x14,0x40,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x07,0x16,0x00, ++0x00,0x02,0x16,0x03,0x24,0x03,0x00,0x2d,0x10,0x43,0x00,0x0f,0x00,0x00,0x00,0x00, ++0x0c,0x00,0x34,0xfd,0x00,0x00,0x00,0x00,0x00,0x40,0x18,0x21,0x00,0x02,0x10,0x23, ++0x04,0x61,0x00,0x05,0x00,0x70,0x10,0x0a,0x16,0x00,0x00,0x03,0x3c,0x02,0x80,0x00, ++0x3c,0x02,0x7f,0xff,0x34,0x42,0xff,0xff,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10, ++0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x24,0x10,0xff,0xff,0x08,0x00,0x34,0xec, ++0x24,0x84,0x00,0x01,0x00,0x80,0x38,0x21,0x90,0x84,0x00,0x00,0x3c,0x02,0x80,0x01, ++0x24,0x48,0x02,0x1c,0x01,0x04,0x18,0x21,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00, ++0x30,0x42,0x00,0x20,0x10,0x40,0x00,0x0a,0x00,0x00,0x50,0x21,0x24,0xe7,0x00,0x01, ++0x90,0xe4,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x18,0x21,0x90,0x62,0x00,0x00, ++0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x20,0x14,0x40,0xff,0xf8,0x00,0x00,0x00,0x00, ++0x00,0x04,0x16,0x00,0x00,0x02,0x16,0x03,0x38,0x42,0x00,0x2b,0x24,0xe3,0x00,0x01, ++0x24,0x04,0x00,0x10,0x10,0xc4,0x00,0x38,0x00,0x62,0x38,0x0a,0x90,0xe4,0x00,0x00, ++0x14,0xc0,0x00,0x07,0x00,0x80,0x18,0x21,0x00,0x04,0x16,0x00,0x00,0x02,0x16,0x03, ++0x24,0x03,0x00,0x30,0x10,0x43,0x00,0x25,0x24,0x06,0x00,0x0a,0x00,0x80,0x18,0x21, ++0x00,0x03,0x16,0x00,0x10,0x40,0x00,0x1a,0x30,0x64,0x00,0xff,0x24,0x82,0xff,0xa9, ++0x2c,0x83,0x00,0x61,0x30,0x48,0x00,0xff,0x10,0x60,0x00,0x09,0x2c,0x89,0x00,0x41, ++0x24,0x82,0xff,0xc9,0x30,0x48,0x00,0xff,0x11,0x20,0x00,0x05,0x2c,0x83,0x00,0x3a, ++0x24,0x82,0xff,0xd0,0x14,0x60,0x00,0x02,0x30,0x48,0x00,0xff,0x24,0x08,0x00,0xff, ++0x01,0x06,0x10,0x2a,0x10,0x40,0x00,0x0a,0x01,0x46,0x00,0x18,0x24,0xe7,0x00,0x01, ++0x00,0x00,0x18,0x12,0x00,0x6a,0x10,0x2b,0x14,0x40,0x00,0x0a,0x00,0x68,0x50,0x21, ++0x80,0xe2,0x00,0x00,0x90,0xe3,0x00,0x00,0x14,0x40,0xff,0xe8,0x30,0x64,0x00,0xff, ++0x10,0xa0,0x00,0x02,0x00,0x00,0x00,0x00,0xac,0xa7,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x01,0x40,0x10,0x21,0x03,0xe0,0x00,0x08,0x24,0x02,0xff,0xff,0x24,0x06,0x00,0x08, ++0x80,0xe3,0x00,0x01,0x24,0x02,0x00,0x78,0x10,0x62,0x00,0x03,0x24,0x02,0x00,0x58, ++0x14,0x62,0xff,0xd7,0x00,0x80,0x18,0x21,0x24,0xe7,0x00,0x02,0x90,0xe4,0x00,0x00, ++0x08,0x00,0x35,0x1f,0x24,0x06,0x00,0x10,0x80,0xe3,0x00,0x00,0x24,0x02,0x00,0x30, ++0x90,0xe4,0x00,0x00,0x10,0x62,0xff,0xf2,0x00,0x00,0x00,0x00,0x08,0x00,0x35,0x18, ++0x00,0x00,0x00,0x00,0x3c,0x04,0xb0,0x03,0x3c,0x06,0xb0,0x07,0x3c,0x02,0x80,0x01, ++0x34,0xc6,0x00,0x18,0x34,0x84,0x00,0x20,0x24,0x42,0xd5,0x54,0x24,0x03,0xff,0x83, ++0xac,0x82,0x00,0x00,0xa0,0xc3,0x00,0x00,0x90,0xc4,0x00,0x00,0x27,0xbd,0xff,0xf8, ++0x3c,0x03,0xb0,0x07,0x24,0x02,0xff,0x82,0xa3,0xa4,0x00,0x00,0xa0,0x62,0x00,0x00, ++0x90,0x64,0x00,0x00,0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x08,0xa3,0xa4,0x00,0x01, ++0xa0,0x40,0x00,0x00,0x90,0x43,0x00,0x00,0x24,0x02,0x00,0x03,0x3c,0x05,0xb0,0x07, ++0xa3,0xa3,0x00,0x00,0xa0,0xc2,0x00,0x00,0x90,0xc4,0x00,0x00,0x34,0xa5,0x00,0x10, ++0x24,0x02,0x00,0x06,0x3c,0x03,0xb0,0x07,0xa3,0xa4,0x00,0x00,0x34,0x63,0x00,0x38, ++0xa0,0xa2,0x00,0x00,0x90,0x64,0x00,0x00,0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x20, ++0xa3,0xa4,0x00,0x00,0xa0,0xa0,0x00,0x00,0x90,0xa3,0x00,0x00,0xaf,0x82,0xc8,0x70, ++0xa3,0xa3,0x00,0x00,0xa0,0x40,0x00,0x00,0x90,0x43,0x00,0x00,0x03,0xe0,0x00,0x08, ++0x27,0xbd,0x00,0x08,}; ++ ++u8 rtl8190_fwdata_array[] = { ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x0a,0x0d,0x5b,0x43,0x4d,0x50,0x4b,0x5d,0x00,0x00,0x00,0x00, ++0x80,0x01,0x00,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08,0x08,0x28,0x28,0x28,0x28,0x28,0x08,0x08,0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0xa0,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x04,0x04,0x04,0x04, ++0x04,0x04,0x04,0x04,0x04,0x04,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x41,0x41,0x41, ++0x41,0x41,0x41,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, ++0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x10,0x10,0x10,0x10,0x10,0x10,0x42,0x42,0x42, ++0x42,0x42,0x42,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x10,0x10,0x10,0x10,0x08,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x01,0x01,0x01,0x01, ++0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, ++0x01,0x01,0x01,0x10,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x02,0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x10,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x20,0x09,0x0d,0x0a, ++0x00,0x00,0x00,0x00,0x80,0x01,0x03,0x1c,0x00,0x00,0x00,0x00,0x43,0x6e,0x73,0x64, ++0x31,0x00,0x00,0x00,0x68,0x65,0x6c,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x72,0x34,0x00,0x00,0x77,0x34,0x00,0x00,0x64,0x62,0x67,0x00,0x72,0x61,0x63,0x74, ++0x72,0x6c,0x00,0x00,0x73,0x79,0x73,0x64,0x00,0x00,0x00,0x00,0x73,0x79,0x73,0x63, ++0x74,0x72,0x6c,0x00,0x74,0x78,0x74,0x62,0x6c,0x00,0x00,0x00,0x70,0x72,0x61,0x6e, ++0x67,0x65,0x00,0x00,0x64,0x6d,0x00,0x00,0x75,0x6e,0x6b,0x6e,0x6f,0x77,0x00,0x00, ++0x80,0x01,0x03,0x34,0x80,0x01,0x03,0x3c,0x80,0x01,0x03,0x3c,0x00,0x00,0x00,0x01, ++0x00,0x00,0x00,0x00,0x80,0x00,0x24,0x5c,0x80,0x01,0x03,0x40,0x80,0x01,0x03,0x3c, ++0x80,0x01,0x03,0x3c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x80,0x00,0x25,0xbc, ++0x80,0x01,0x03,0x44,0x80,0x01,0x03,0x3c,0x80,0x01,0x03,0x3c,0x00,0x00,0x00,0x01, ++0x00,0x00,0x00,0x00,0x80,0x00,0x27,0x38,0x80,0x01,0x03,0x48,0x80,0x01,0x03,0x3c, ++0x80,0x01,0x03,0x3c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x80,0x00,0x29,0x04, ++0x80,0x01,0x03,0x4c,0x80,0x01,0x03,0x3c,0x80,0x01,0x03,0x3c,0x00,0x00,0x00,0x01, ++0x00,0x00,0x00,0x00,0x80,0x00,0x29,0xdc,0x80,0x01,0x03,0x54,0x80,0x01,0x03,0x3c, ++0x80,0x01,0x03,0x3c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x80,0x00,0x29,0xe4, ++0x80,0x01,0x03,0x5c,0x80,0x01,0x03,0x3c,0x80,0x01,0x03,0x3c,0x00,0x00,0x00,0x01, ++0x00,0x00,0x00,0x00,0x80,0x00,0x29,0xec,0x80,0x01,0x03,0x64,0x80,0x01,0x03,0x3c, ++0x80,0x01,0x03,0x3c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x80,0x00,0x29,0xf4, ++0x80,0x01,0x03,0x6c,0x80,0x01,0x03,0x3c,0x80,0x01,0x03,0x3c,0x00,0x00,0x00,0x01, ++0x00,0x00,0x00,0x00,0x80,0x00,0x2b,0x80,0x80,0x01,0x03,0x74,0x80,0x01,0x03,0x3c, ++0x80,0x01,0x03,0x3c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x80,0x00,0x2b,0xf4, ++0x80,0x01,0x03,0x78,0x80,0x01,0x03,0x3c,0x80,0x01,0x03,0x3c,0x00,0x00,0x00,0x0f, ++0x00,0x00,0x00,0x01,0x80,0x00,0x2c,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x0a,0x0d,0x52,0x54,0x4c,0x38,0x31,0x39,0x58,0x2d,0x25,0x64,0x3e,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x52,0x54,0x4c,0x38,0x31,0x39,0x58,0x2d,0x25,0x64,0x3e,0x0a, ++0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2a,0x00,0x00,0x00,0x0a,0x0d,0x45,0x72, ++0x72,0x20,0x44,0x49,0x52,0x00,0x00,0x00,0x0a,0x0d,0x44,0x42,0x47,0x20,0x43,0x4d, ++0x44,0x73,0x3a,0x00,0x0a,0x0d,0x5b,0x00,0x5d,0x2d,0x00,0x00,0x0a,0x0d,0x3c,0x31, ++0x2e,0x43,0x4d,0x4e,0x3e,0x20,0x3c,0x32,0x2e,0x3f,0x3e,0x00,0x0a,0x0d,0x20,0x79, ++0x65,0x61,0x72,0x2d,0x64,0x61,0x79,0x2d,0x68,0x6f,0x75,0x72,0x2d,0x6d,0x69,0x6e, ++0x2d,0x73,0x65,0x63,0x2d,0x31,0x30,0x6d,0x73,0x3d,0x00,0x00,0x25,0x64,0x2d,0x00, ++0x0a,0x0d,0x09,0x20,0x20,0x20,0x20,0x20,0x30,0x30,0x20,0x20,0x20,0x20,0x20,0x20, ++0x20,0x30,0x34,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x30,0x38,0x20,0x20,0x20,0x20, ++0x20,0x20,0x20,0x30,0x43,0x00,0x00,0x00,0x0a,0x0d,0x09,0x20,0x20,0x20,0x20,0x20, ++0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d, ++0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d, ++0x3d,0x3d,0x3d,0x00,0x0d,0x0a,0x20,0x30,0x78,0x25,0x30,0x38,0x58,0x20,0x20,0x00, ++0x09,0x00,0x00,0x00,0x25,0x30,0x38,0x58,0x20,0x00,0x00,0x00,0x0a,0x0d,0x44,0x62, ++0x67,0x5f,0x46,0x6c,0x61,0x67,0x25,0x64,0x3d,0x30,0x78,0x25,0x30,0x38,0x78,0x00, ++0x0a,0x0d,0x54,0x58,0x4c,0x4c,0x54,0x09,0x09,0x4e,0x45,0x58,0x54,0x20,0x20,0x20, ++0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x4e,0x45,0x58,0x54,0x0a,0x0d,0x00, ++0x0a,0x0d,0x20,0x50,0x61,0x67,0x65,0x25,0x33,0x64,0x09,0x00,0x25,0x34,0x64,0x20, ++0x20,0x20,0x20,0x00,0x25,0x34,0x64,0x20,0x20,0x20,0x20,0x09,0x00,0x00,0x00,0x00, ++0x0a,0x0d,0x54,0x58,0x4f,0x51,0x54,0x09,0x09,0x48,0x65,0x61,0x64,0x20,0x20,0x20, ++0x20,0x54,0x61,0x69,0x6c,0x20,0x20,0x20,0x20,0x48,0x65,0x61,0x64,0x20,0x20,0x20, ++0x20,0x54,0x61,0x69,0x6c,0x0a,0x0d,0x00,0x0a,0x0d,0x55,0x6e,0x6b,0x6e,0x6f,0x77, ++0x20,0x63,0x6f,0x6d,0x6d,0x61,0x6e,0x64,0x00,0x00,0x00,0x00,0x0a,0x0d,0x45,0x72, ++0x72,0x20,0x41,0x72,0x67,0x0a,0x0d,0x55,0x53,0x41,0x47,0x45,0x3a,0x00,0x00,0x00, ++0x10,0x00,0x08,0x00,0x02,0xe9,0x01,0x74,0x02,0xab,0x01,0xc7,0x01,0x55,0x00,0xe4, ++0x00,0xab,0x00,0x72,0x00,0x55,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x00,0x4c, ++0x02,0x76,0x01,0x3b,0x00,0xd2,0x00,0x9e,0x00,0x69,0x00,0x4f,0x00,0x46,0x00,0x3f, ++0x01,0x3b,0x00,0x9e,0x00,0x69,0x00,0x4f,0x00,0x35,0x00,0x27,0x00,0x23,0x00,0x20, ++0x01,0x2f,0x00,0x98,0x00,0x65,0x00,0x4c,0x00,0x33,0x00,0x26,0x00,0x22,0x00,0x1e, ++0x00,0x98,0x00,0x4c,0x00,0x33,0x00,0x26,0x00,0x19,0x00,0x13,0x00,0x11,0x00,0x0f, ++0x02,0x39,0x01,0x1c,0x00,0xbd,0x00,0x8e,0x00,0x5f,0x00,0x47,0x00,0x3f,0x00,0x39, ++0x01,0x1c,0x00,0x8e,0x00,0x5f,0x00,0x47,0x00,0x2f,0x00,0x23,0x00,0x20,0x00,0x1c, ++0x01,0x11,0x00,0x89,0x00,0x5b,0x00,0x44,0x00,0x2e,0x00,0x22,0x00,0x1e,0x00,0x1b, ++0x00,0x89,0x00,0x44,0x00,0x2e,0x00,0x22,0x00,0x17,0x00,0x11,0x00,0x0f,0x00,0x0e, ++0x02,0xab,0x02,0xab,0x02,0x66,0x02,0x66,0x07,0x06,0x06,0x06,0x05,0x06,0x07,0x08, ++0x04,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0b,0x49,0x6e,0x74,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x54,0x4c,0x42,0x4d,0x4f,0x44,0x00,0x00,0x00,0x00,0x54,0x4c,0x42,0x4c, ++0x5f,0x64,0x61,0x74,0x61,0x00,0x54,0x4c,0x42,0x53,0x00,0x00,0x00,0x00,0x00,0x00, ++0x41,0x64,0x45,0x4c,0x5f,0x64,0x61,0x74,0x61,0x00,0x41,0x64,0x45,0x53,0x00,0x00, ++0x00,0x00,0x00,0x00,0x45,0x78,0x63,0x43,0x6f,0x64,0x65,0x36,0x00,0x00,0x45,0x78, ++0x63,0x43,0x6f,0x64,0x65,0x37,0x00,0x00,0x53,0x79,0x73,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x42,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x52,0x49,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x43,0x70,0x55,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x4f,0x76,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x80,0x01,0x14,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x10, ++0x00,0x00,0x00,0x2c,0x00,0x00,0x00,0x58,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x48, ++0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x90,0x00,0x00,0x00,0xc0,0x00,0x00,0x01,0x20, ++0x00,0x00,0x01,0x20,0x00,0x00,0x01,0x20,0x00,0x00,0x00,0x68,0x00,0x00,0x00,0xd0, ++0x00,0x00,0x01,0x38,0x00,0x00,0x01,0xa0,0x00,0x00,0x02,0x70,0x00,0x00,0x03,0x40, ++0x00,0x00,0x03,0xa8,0x00,0x00,0x04,0x10,0x00,0x00,0x00,0xd0,0x00,0x00,0x01,0xa0, ++0x00,0x00,0x02,0x70,0x00,0x00,0x03,0x40,0x00,0x00,0x04,0xe0,0x00,0x00,0x06,0x80, ++0x00,0x00,0x07,0x50,0x00,0x00,0x08,0x20,0x01,0x01,0x01,0x02,0x01,0x01,0x02,0x02, ++0x03,0x03,0x04,0x04,0x01,0x02,0x02,0x04,0x04,0x06,0x07,0x08,0x02,0x04,0x04,0x07, ++0x07,0x0b,0x0d,0x0e,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x3c,0x4e,0x55,0x4c,0x4c,0x3e,0x00,0x00,0x30,0x31,0x32,0x33, ++0x34,0x35,0x36,0x37,0x38,0x39,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6a, ++0x6b,0x6c,0x6d,0x6e,0x6f,0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7a, ++0x00,0x00,0x00,0x00,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x41,0x42, ++0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,0x50,0x51,0x52, ++0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x5b,0x52,0x58,0x5d,0x20,0x70,0x6b,0x74,0x5f,0x6c,0x65,0x6e, ++0x3d,0x25,0x64,0x20,0x6f,0x66,0x66,0x73,0x65,0x74,0x3d,0x25,0x64,0x20,0x73,0x74, ++0x61,0x72,0x74,0x5f,0x61,0x64,0x64,0x72,0x3d,0x25,0x30,0x38,0x78,0x0a,0x0d,0x00, ++0x00,0x00,0x00,0x00,0x80,0x00,0x07,0x6c,0x80,0x00,0x07,0x80,0x80,0x00,0x07,0x80, ++0x80,0x00,0x07,0x70,0x80,0x00,0x07,0x70,0x80,0x00,0x07,0x94,0x80,0x00,0x75,0x98, ++0x80,0x00,0x75,0xec,0x80,0x00,0x76,0x08,0x80,0x00,0x76,0xf4,0x80,0x00,0x77,0xac, ++0x80,0x00,0x77,0xfc,0x80,0x00,0x78,0x68,0x80,0x00,0x79,0x6c,0x80,0x00,0x79,0xa0, ++0x80,0x00,0x79,0xb4,0x80,0x00,0x79,0xc8,0x80,0x00,0x7a,0x74,0x80,0x00,0x7a,0xb0, ++0x80,0x00,0x7b,0x60,0x80,0x00,0x7b,0x88,0x80,0x00,0x75,0x54,0x80,0x00,0x7b,0x9c, ++0x80,0x00,0x82,0x28,0x80,0x00,0x82,0xa0,0x80,0x00,0x82,0xac,0x80,0x00,0x82,0xb8, ++0x80,0x00,0x82,0x40,0x80,0x00,0x82,0x40,0x80,0x00,0x82,0x40,0x80,0x00,0x82,0x40, ++0x80,0x00,0x82,0x40,0x80,0x00,0x82,0x40,0x80,0x00,0x82,0x40,0x80,0x00,0x82,0x40, ++0x80,0x00,0x82,0x40,0x80,0x00,0x82,0x40,0x80,0x00,0x82,0x40,0x80,0x00,0x82,0x40, ++0x80,0x00,0x82,0xc4,0x80,0x00,0x82,0xd0,0x80,0x00,0x82,0xdc,0x80,0x00,0xa5,0x50, ++0x80,0x00,0xa5,0x50,0x80,0x00,0xa5,0x50,0x80,0x00,0xa5,0x50,0x80,0x00,0xa5,0x50, ++0x80,0x00,0xa5,0x84,0x80,0x00,0xa5,0xf4,0x80,0x00,0xa6,0x1c,0x80,0x00,0xa6,0xf8, ++0x80,0x00,0xa6,0xf8,0x80,0x00,0xa6,0xf8,0x80,0x00,0xa6,0xf8,0x80,0x00,0xa6,0xf8, ++0x80,0x00,0xa6,0x30,0x80,0x00,0xa6,0x94,0x80,0x00,0xa6,0xc4,0x80,0x00,0xa6,0xf8, ++0x80,0x00,0xa6,0xf8,0x80,0x00,0xa6,0xf8,0x80,0x00,0xa6,0xf8,0x80,0x00,0xa6,0xd0, ++0x80,0x00,0xa7,0x2c,0x80,0x00,0xa7,0x40,0x80,0x00,0xa4,0xac,0x80,0x00,0xaa,0x50, ++0x80,0x00,0xaa,0x50,0x80,0x00,0xaa,0x50,0x80,0x00,0xaa,0x50,0x80,0x00,0xaa,0x50, ++0x80,0x00,0xaa,0x84,0x80,0x00,0xaa,0xf4,0x80,0x00,0xab,0x1c,0x80,0x00,0xab,0xf8, ++0x80,0x00,0xab,0xf8,0x80,0x00,0xab,0xf8,0x80,0x00,0xab,0xf8,0x80,0x00,0xab,0xf8, ++0x80,0x00,0xab,0x30,0x80,0x00,0xab,0x94,0x80,0x00,0xab,0xc4,0x80,0x00,0xab,0xf8, ++0x80,0x00,0xab,0xf8,0x80,0x00,0xab,0xf8,0x80,0x00,0xab,0xf8,0x80,0x00,0xab,0xd0, ++0x80,0x00,0xac,0x2c,0x80,0x00,0xac,0x40,0x80,0x00,0xa8,0x88,0x80,0x00,0xb9,0x8c, ++0x80,0x00,0xb9,0xa4,0x80,0x00,0xb9,0xa4,0x80,0x00,0xb9,0x94,0x80,0x00,0xb9,0xa4, ++0x80,0x00,0xb9,0xa4,0x80,0x00,0xb9,0xa4,0x80,0x00,0xb9,0xa4,0x80,0x00,0xb9,0xa4, ++0x80,0x00,0xb9,0xa4,0x80,0x00,0xb9,0xa4,0x80,0x00,0xb9,0x9c,0x80,0x00,0xb9,0xa4, ++0x80,0x00,0xb9,0x84,0x80,0x00,0xb9,0xa4,0x80,0x00,0xb9,0xa4,0x80,0x00,0xbd,0xcc, ++0x80,0x00,0xba,0xbc,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xba,0xc8, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xba,0x50,0x80,0x00,0xbb,0x9c, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbb,0x9c,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbb,0xa4,0x80,0x00,0xbb,0xc4,0x80,0x00,0xbb,0xcc, ++0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0x24,0x80,0x00,0xbc,0xd4, ++0x80,0x00,0xba,0xd0,0x80,0x00,0xbc,0xd4,0x80,0x00,0xbc,0xd4,0x80,0x00,0xba,0xcc, ++}; ++ ++#endif //__INC_R819XU_FIRMWARE_IMG_H +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/usb/core/devio.c linux-2.6.27.29-0.1.1/drivers/usb/core/devio.c +--- linux-2.6.27.25-0.1.1/drivers/usb/core/devio.c 2009-08-05 09:49:39.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/usb/core/devio.c 2009-08-27 12:44:24.000000000 +0100 +@@ -976,7 +976,7 @@ static int proc_do_submiturb(struct dev_ + USBDEVFS_URB_ZERO_PACKET | + USBDEVFS_URB_NO_INTERRUPT)) + return -EINVAL; +- if (!uurb->buffer) ++ if (uurb->buffer_length > 0 && !uurb->buffer) + return -EINVAL; + if (uurb->signr != 0 && (uurb->signr < SIGRTMIN || + uurb->signr > SIGRTMAX)) +@@ -1035,11 +1035,6 @@ static int proc_do_submiturb(struct dev_ + is_in = 0; + uurb->endpoint &= ~USB_DIR_IN; + } +- if (!access_ok(is_in ? VERIFY_WRITE : VERIFY_READ, +- uurb->buffer, uurb->buffer_length)) { +- kfree(dr); +- return -EFAULT; +- } + snoop(&ps->dev->dev, "control urb: bRequest=%02x " + "bRrequestType=%02x wValue=%04x " + "wIndex=%04x wLength=%04x\n", +@@ -1059,9 +1054,6 @@ static int proc_do_submiturb(struct dev_ + uurb->number_of_packets = 0; + if (uurb->buffer_length > MAX_USBFS_BUFFER_SIZE) + return -EINVAL; +- if (!access_ok(is_in ? VERIFY_WRITE : VERIFY_READ, +- uurb->buffer, uurb->buffer_length)) +- return -EFAULT; + snoop(&ps->dev->dev, "bulk urb\n"); + break; + +@@ -1103,28 +1095,35 @@ static int proc_do_submiturb(struct dev_ + return -EINVAL; + if (uurb->buffer_length > MAX_USBFS_BUFFER_SIZE) + return -EINVAL; +- if (!access_ok(is_in ? VERIFY_WRITE : VERIFY_READ, +- uurb->buffer, uurb->buffer_length)) +- return -EFAULT; + snoop(&ps->dev->dev, "interrupt urb\n"); + break; + + default: + return -EINVAL; + } +- as = alloc_async(uurb->number_of_packets); +- if (!as) { ++ if (uurb->buffer_length > 0 && ++ !access_ok(is_in ? VERIFY_WRITE : VERIFY_READ, ++ uurb->buffer, uurb->buffer_length)) { + kfree(isopkt); + kfree(dr); +- return -ENOMEM; ++ return -EFAULT; + } +- as->urb->transfer_buffer = kmalloc(uurb->buffer_length, GFP_KERNEL); +- if (!as->urb->transfer_buffer) { ++ as = alloc_async(uurb->number_of_packets); ++ if (!as) { + kfree(isopkt); + kfree(dr); +- free_async(as); + return -ENOMEM; + } ++ if (uurb->buffer_length > 0) { ++ as->urb->transfer_buffer = kmalloc(uurb->buffer_length, ++ GFP_KERNEL); ++ if (!as->urb->transfer_buffer) { ++ kfree(isopkt); ++ kfree(dr); ++ free_async(as); ++ return -ENOMEM; ++ } ++ } + as->urb->dev = ps->dev; + as->urb->pipe = (uurb->type << 30) | + __create_pipe(ps->dev, uurb->endpoint & 0xf) | +@@ -1166,7 +1165,7 @@ static int proc_do_submiturb(struct dev_ + kfree(isopkt); + as->ps = ps; + as->userurb = arg; +- if (uurb->endpoint & USB_DIR_IN) ++ if (is_in && uurb->buffer_length > 0) + as->userbuffer = uurb->buffer; + else + as->userbuffer = NULL; +@@ -1176,9 +1175,9 @@ static int proc_do_submiturb(struct dev_ + as->uid = current->uid; + as->euid = current->euid; + security_task_getsecid(current, &as->secid); +- if (!is_in) { ++ if (!is_in && uurb->buffer_length > 0) { + if (copy_from_user(as->urb->transfer_buffer, uurb->buffer, +- as->urb->transfer_buffer_length)) { ++ uurb->buffer_length)) { + free_async(as); + return -EFAULT; + } +@@ -1228,22 +1227,22 @@ static int processcompl(struct async *as + if (as->userbuffer) + if (copy_to_user(as->userbuffer, urb->transfer_buffer, + urb->transfer_buffer_length)) +- return -EFAULT; ++ goto err_out; + if (put_user(as->status, &userurb->status)) +- return -EFAULT; ++ goto err_out; + if (put_user(urb->actual_length, &userurb->actual_length)) +- return -EFAULT; ++ goto err_out; + if (put_user(urb->error_count, &userurb->error_count)) +- return -EFAULT; ++ goto err_out; + + if (usb_endpoint_xfer_isoc(&urb->ep->desc)) { + for (i = 0; i < urb->number_of_packets; i++) { + if (put_user(urb->iso_frame_desc[i].actual_length, + &userurb->iso_frame_desc[i].actual_length)) +- return -EFAULT; ++ goto err_out; + if (put_user(urb->iso_frame_desc[i].status, + &userurb->iso_frame_desc[i].status)) +- return -EFAULT; ++ goto err_out; + } + } + +@@ -1252,6 +1251,10 @@ static int processcompl(struct async *as + if (put_user(addr, (void __user * __user *)arg)) + return -EFAULT; + return 0; ++ ++err_out: ++ free_async(as); ++ return -EFAULT; + } + + static struct async *reap_as(struct dev_state *ps) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/usb/gadget/ether.c linux-2.6.27.29-0.1.1/drivers/usb/gadget/ether.c +--- linux-2.6.27.25-0.1.1/drivers/usb/gadget/ether.c 2009-08-05 09:43:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/usb/gadget/ether.c 2009-08-27 12:44:24.000000000 +0100 +@@ -273,15 +273,16 @@ static int __init eth_bind(struct usb_co + /* CDC Subset */ + eth_config_driver.label = "CDC Subset/SAFE"; + +- device_desc.idVendor = cpu_to_le16(SIMPLE_VENDOR_NUM), +- device_desc.idProduct = cpu_to_le16(SIMPLE_PRODUCT_NUM), +- device_desc.bDeviceClass = USB_CLASS_VENDOR_SPEC; ++ device_desc.idVendor = cpu_to_le16(SIMPLE_VENDOR_NUM); ++ device_desc.idProduct = cpu_to_le16(SIMPLE_PRODUCT_NUM); ++ if (!has_rndis()) ++ device_desc.bDeviceClass = USB_CLASS_VENDOR_SPEC; + } + + if (has_rndis()) { + /* RNDIS plus ECM-or-Subset */ +- device_desc.idVendor = cpu_to_le16(RNDIS_VENDOR_NUM), +- device_desc.idProduct = cpu_to_le16(RNDIS_PRODUCT_NUM), ++ device_desc.idVendor = cpu_to_le16(RNDIS_VENDOR_NUM); ++ device_desc.idProduct = cpu_to_le16(RNDIS_PRODUCT_NUM); + device_desc.bNumConfigurations = 2; + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/usb/host/ehci-sched.c linux-2.6.27.29-0.1.1/drivers/usb/host/ehci-sched.c +--- linux-2.6.27.25-0.1.1/drivers/usb/host/ehci-sched.c 2009-08-05 09:49:39.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/usb/host/ehci-sched.c 2009-08-27 12:44:24.000000000 +0100 +@@ -1617,11 +1617,14 @@ itd_complete ( + desc->status = -EPROTO; + + /* HC need not update length with this error */ +- if (!(t & EHCI_ISOC_BABBLE)) +- desc->actual_length = EHCI_ITD_LENGTH (t); ++ if (!(t & EHCI_ISOC_BABBLE)) { ++ desc->actual_length = EHCI_ITD_LENGTH(t); ++ urb->actual_length += desc->actual_length; ++ } + } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) { + desc->status = 0; +- desc->actual_length = EHCI_ITD_LENGTH (t); ++ desc->actual_length = EHCI_ITD_LENGTH(t); ++ urb->actual_length += desc->actual_length; + } else { + /* URB was too late */ + desc->status = -EXDEV; +@@ -2012,7 +2015,8 @@ sitd_complete ( + desc->status = -EPROTO; + } else { + desc->status = 0; +- desc->actual_length = desc->length - SITD_LENGTH (t); ++ desc->actual_length = desc->length - SITD_LENGTH(t); ++ urb->actual_length += desc->actual_length; + } + stream->depth -= stream->interval << 3; + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/usb/serial/ti_usb_3410_5052.c linux-2.6.27.29-0.1.1/drivers/usb/serial/ti_usb_3410_5052.c +--- linux-2.6.27.25-0.1.1/drivers/usb/serial/ti_usb_3410_5052.c 2009-08-27 12:59:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/usb/serial/ti_usb_3410_5052.c 2009-08-27 12:44:24.000000000 +0100 +@@ -1704,7 +1704,7 @@ static int ti_do_download(struct usb_dev + u8 cs = 0; + int done; + struct ti_firmware_header *header; +- int status; ++ int status = 0; + int len; + + for (pos = sizeof(struct ti_firmware_header); pos < size; pos++) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/video/atmel_lcdfb.c linux-2.6.27.29-0.1.1/drivers/video/atmel_lcdfb.c +--- linux-2.6.27.25-0.1.1/drivers/video/atmel_lcdfb.c 2009-08-05 09:43:14.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/video/atmel_lcdfb.c 2009-08-27 12:44:29.000000000 +0100 +@@ -29,14 +29,8 @@ + + /* configurable parameters */ + #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 +-#define ATMEL_LCDC_DMA_BURST_LEN 8 +- +-#if defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9) || \ +- defined(CONFIG_ARCH_AT91SAM9RL) +-#define ATMEL_LCDC_FIFO_SIZE 2048 +-#else +-#define ATMEL_LCDC_FIFO_SIZE 512 +-#endif ++#define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */ ++#define ATMEL_LCDC_FIFO_SIZE 512 /* words */ + + #if defined(CONFIG_ARCH_AT91) + #define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/video/fbmon.c linux-2.6.27.29-0.1.1/drivers/video/fbmon.c +--- linux-2.6.27.25-0.1.1/drivers/video/fbmon.c 2009-08-05 09:43:14.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/video/fbmon.c 2009-08-27 12:44:29.000000000 +0100 +@@ -256,8 +256,8 @@ static void fix_edid(unsigned char *edid + + static int edid_checksum(unsigned char *edid) + { +- unsigned char i, csum = 0, all_null = 0; +- int err = 0, fix = check_edid(edid); ++ unsigned char csum = 0, all_null = 0; ++ int i, err = 0, fix = check_edid(edid); + + if (fix) + fix_edid(edid, fix); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/xen/balloon/balloon.c linux-2.6.27.29-0.1.1/drivers/xen/balloon/balloon.c +--- linux-2.6.27.25-0.1.1/drivers/xen/balloon/balloon.c 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/xen/balloon/balloon.c 2009-08-27 12:44:24.000000000 +0100 +@@ -84,7 +84,7 @@ static unsigned long frame_list[PAGE_SIZ + /* VM /proc information for memory */ + extern unsigned long totalram_pages; + +-#if !defined(MODULE) && defined(CONFIG_HIGHMEM) ++#ifdef CONFIG_HIGHMEM + extern unsigned long totalhigh_pages; + #define inc_totalhigh_pages() (totalhigh_pages++) + #define dec_totalhigh_pages() (totalhigh_pages--) +@@ -188,7 +188,7 @@ static void balloon_alarm(unsigned long + + static unsigned long current_target(void) + { +- unsigned long target = min(bs.target_pages, bs.hard_limit); ++ unsigned long target = bs.target_pages; + if (target > (bs.current_pages + bs.balloon_low + bs.balloon_high)) + target = bs.current_pages + bs.balloon_low + bs.balloon_high; + return target; +@@ -255,26 +255,12 @@ static int increase_reservation(unsigned + } + + set_xen_guest_handle(reservation.extent_start, frame_list); +- reservation.nr_extents = nr_pages; +- rc = HYPERVISOR_memory_op( +- XENMEM_populate_physmap, &reservation); +- if (rc < nr_pages) { +- if (rc > 0) { +- int ret; +- +- /* We hit the Xen hard limit: reprobe. */ +- reservation.nr_extents = rc; +- ret = HYPERVISOR_memory_op(XENMEM_decrease_reservation, +- &reservation); +- BUG_ON(ret != rc); +- } +- if (rc >= 0) +- bs.hard_limit = (bs.current_pages + rc - +- bs.driver_pages); ++ reservation.nr_extents = nr_pages; ++ rc = HYPERVISOR_memory_op(XENMEM_populate_physmap, &reservation); ++ if (rc < 0) + goto out; +- } + +- for (i = 0; i < nr_pages; i++) { ++ for (i = 0; i < rc; i++) { + page = balloon_retrieve(); + BUG_ON(page == NULL); + +@@ -302,13 +288,13 @@ static int increase_reservation(unsigned + balloon_free_page(page); + } + +- bs.current_pages += nr_pages; ++ bs.current_pages += rc; + totalram_pages = bs.current_pages; + + out: + balloon_unlock(flags); + +- return 0; ++ return rc < 0 ? rc : rc != nr_pages; + } + + static int decrease_reservation(unsigned long nr_pages) +@@ -420,7 +406,6 @@ static void balloon_process(struct work_ + void balloon_set_new_target(unsigned long target) + { + /* No need for lock. Not read-modify-write updates. */ +- bs.hard_limit = ~0UL; + bs.target_pages = max(target, balloon_minimum_target()); + schedule_work(&balloon_worker); + } +@@ -500,18 +485,12 @@ static int balloon_read(char *page, char + "Maximum target: %8lu kB\n" + "Low-mem balloon: %8lu kB\n" + "High-mem balloon: %8lu kB\n" +- "Driver pages: %8lu kB\n" +- "Xen hard limit: ", ++ "Driver pages: %8lu kB\n", + PAGES2KB(bs.current_pages), PAGES2KB(bs.target_pages), + PAGES2KB(balloon_minimum_target()), PAGES2KB(num_physpages), + PAGES2KB(bs.balloon_low), PAGES2KB(bs.balloon_high), + PAGES2KB(bs.driver_pages)); + +- if (bs.hard_limit != ~0UL) +- len += sprintf(page + len, "%8lu kB\n", +- PAGES2KB(bs.hard_limit)); +- else +- len += sprintf(page + len, " ??? kB\n"); + + *eof = 1; + return len; +@@ -542,7 +521,6 @@ static int __init balloon_init(void) + bs.balloon_low = 0; + bs.balloon_high = 0; + bs.driver_pages = 0UL; +- bs.hard_limit = ~0UL; + + init_timer(&balloon_timer); + balloon_timer.data = 0; +@@ -700,12 +678,12 @@ static void _free_empty_pages_and_pageve + BUG_ON(page_count(pagevec[i]) != 1); + balloon_append(pagevec[i]); + } ++ if (!free_vec) ++ totalram_pages = bs.current_pages -= nr_pages; + balloon_unlock(flags); + + if (free_vec) + kfree(pagevec); +- else +- totalram_pages = bs.current_pages -= nr_pages; + + schedule_work(&balloon_worker); + } +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/xen/balloon/common.h linux-2.6.27.29-0.1.1/drivers/xen/balloon/common.h +--- linux-2.6.27.25-0.1.1/drivers/xen/balloon/common.h 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/xen/balloon/common.h 2009-08-27 12:44:24.000000000 +0100 +@@ -35,8 +35,6 @@ struct balloon_stats { + /* We aim for 'current allocation' == 'target allocation'. */ + unsigned long current_pages; + unsigned long target_pages; +- /* We may hit the hard limit in Xen. If we do then we remember it. */ +- unsigned long hard_limit; + /* + * Drivers may alter the memory reservation independently, but they + * must inform the balloon driver so we avoid hitting the hard limit. +@@ -47,7 +45,6 @@ struct balloon_stats { + unsigned long balloon_high; + }; + +-extern unsigned long num_physpages; + extern struct balloon_stats balloon_stats; + #define bs balloon_stats + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/xen/balloon/sysfs.c linux-2.6.27.29-0.1.1/drivers/xen/balloon/sysfs.c +--- linux-2.6.27.25-0.1.1/drivers/xen/balloon/sysfs.c 2009-08-05 09:43:09.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/xen/balloon/sysfs.c 2009-08-27 12:44:24.000000000 +0100 +@@ -31,6 +31,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -57,9 +58,6 @@ BALLOON_SHOW(min_kb, "%lu\n", PAGES2KB(b + BALLOON_SHOW(max_kb, "%lu\n", PAGES2KB(num_physpages)); + BALLOON_SHOW(low_kb, "%lu\n", PAGES2KB(bs.balloon_low)); + BALLOON_SHOW(high_kb, "%lu\n", PAGES2KB(bs.balloon_high)); +-BALLOON_SHOW(hard_limit_kb, +- (bs.hard_limit!=~0UL) ? "%lu\n" : "???\n", +- (bs.hard_limit!=~0UL) ? PAGES2KB(bs.hard_limit) : 0); + BALLOON_SHOW(driver_kb, "%lu\n", PAGES2KB(bs.driver_pages)); + + static ssize_t show_target_kb(struct sys_device *dev, +@@ -103,7 +101,6 @@ static struct attribute *balloon_info_at + &attr_max_kb.attr, + &attr_low_kb.attr, + &attr_high_kb.attr, +- &attr_hard_limit_kb.attr, + &attr_driver_kb.attr, + NULL + }; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/drivers/xen/core/spinlock.c linux-2.6.27.29-0.1.1/drivers/xen/core/spinlock.c +--- linux-2.6.27.25-0.1.1/drivers/xen/core/spinlock.c 2009-08-27 12:59:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/drivers/xen/core/spinlock.c 2009-08-27 12:44:24.000000000 +0100 +@@ -68,7 +68,7 @@ int xen_spin_wait(raw_spinlock_t *lock, + struct spinning spinning; + + /* If kicker interrupt not initialized yet, just spin. */ +- if (unlikely(irq < 0)) ++ if (unlikely(irq < 0) || unlikely(!cpu_online(smp_processor_id()))) + return 0; + + token >>= TICKET_SHIFT; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/binfmt_elf.c linux-2.6.27.29-0.1.1/fs/binfmt_elf.c +--- linux-2.6.27.25-0.1.1/fs/binfmt_elf.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/binfmt_elf.c 2009-08-27 12:43:48.000000000 +0100 +@@ -1517,11 +1517,11 @@ static int fill_note_info(struct elfhdr + info->thread = NULL; + + psinfo = kmalloc(sizeof(*psinfo), GFP_KERNEL); +- fill_note(&info->psinfo, "CORE", NT_PRPSINFO, sizeof(*psinfo), psinfo); +- + if (psinfo == NULL) + return 0; + ++ fill_note(&info->psinfo, "CORE", NT_PRPSINFO, sizeof(*psinfo), psinfo); ++ + /* + * Figure out how many notes we're going to need for each thread. + */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/dlm/dir.c linux-2.6.27.29-0.1.1/fs/dlm/dir.c +--- linux-2.6.27.25-0.1.1/fs/dlm/dir.c 2009-08-05 09:48:58.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/dlm/dir.c 2009-08-27 12:43:44.000000000 +0100 +@@ -49,7 +49,8 @@ static struct dlm_direntry *get_free_de( + spin_unlock(&ls->ls_recover_list_lock); + + if (!found) +- de = kzalloc(sizeof(struct dlm_direntry) + len, GFP_KERNEL); ++ de = kzalloc(sizeof(struct dlm_direntry) + len, ++ ls->ls_allocation); + return de; + } + +@@ -211,7 +212,7 @@ int dlm_recover_directory(struct dlm_ls + + dlm_dir_clear(ls); + +- last_name = kmalloc(DLM_RESNAME_MAXLEN, GFP_KERNEL); ++ last_name = kmalloc(DLM_RESNAME_MAXLEN, ls->ls_allocation); + if (!last_name) + goto out; + +@@ -322,7 +323,7 @@ static int get_entry(struct dlm_ls *ls, + if (namelen > DLM_RESNAME_MAXLEN) + return -EINVAL; + +- de = kzalloc(sizeof(struct dlm_direntry) + namelen, GFP_KERNEL); ++ de = kzalloc(sizeof(struct dlm_direntry) + namelen, ls->ls_allocation); + if (!de) + return -ENOMEM; + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/dlm/lock.c linux-2.6.27.29-0.1.1/fs/dlm/lock.c +--- linux-2.6.27.25-0.1.1/fs/dlm/lock.c 2009-08-05 09:48:58.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/dlm/lock.c 2009-08-27 12:43:44.000000000 +0100 +@@ -435,7 +435,7 @@ static int search_rsb(struct dlm_ls *ls, + static int find_rsb(struct dlm_ls *ls, char *name, int namelen, + unsigned int flags, struct dlm_rsb **r_ret) + { +- struct dlm_rsb *r, *tmp; ++ struct dlm_rsb *r = NULL, *tmp; + uint32_t hash, bucket; + int error = -EINVAL; + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/dlm/lockspace.c linux-2.6.27.29-0.1.1/fs/dlm/lockspace.c +--- linux-2.6.27.25-0.1.1/fs/dlm/lockspace.c 2009-08-05 09:48:58.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/dlm/lockspace.c 2009-08-27 12:43:44.000000000 +0100 +@@ -419,16 +419,14 @@ static int new_lockspace(char *name, int + break; + } + ls->ls_create_count++; +- module_put(THIS_MODULE); +- error = 1; /* not an error, return 0 */ ++ *lockspace = ls; ++ error = 1; + break; + } + spin_unlock(&lslist_lock); + +- if (error < 0) +- goto out; + if (error) +- goto ret_zero; ++ goto out; + + error = -ENOMEM; + +@@ -583,7 +581,6 @@ static int new_lockspace(char *name, int + dlm_create_debug_file(ls); + + log_debug(ls, "join complete"); +- ret_zero: + *lockspace = ls; + return 0; + +@@ -628,7 +625,9 @@ int dlm_new_lockspace(char *name, int na + error = new_lockspace(name, namelen, lockspace, flags, lvblen); + if (!error) + ls_count++; +- else if (!ls_count) ++ if (error > 0) ++ error = 0; ++ if (!ls_count) + threads_stop(); + out: + mutex_unlock(&ls_lock); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/dlm/lowcomms.c linux-2.6.27.29-0.1.1/fs/dlm/lowcomms.c +--- linux-2.6.27.25-0.1.1/fs/dlm/lowcomms.c 2009-08-05 09:48:58.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/dlm/lowcomms.c 2009-08-27 12:43:44.000000000 +0100 +@@ -309,6 +309,20 @@ static void lowcomms_state_change(struct + lowcomms_write_space(sk); + } + ++int dlm_lowcomms_connect_node(int nodeid) ++{ ++ struct connection *con; ++ ++ if (nodeid == dlm_our_nodeid()) ++ return 0; ++ ++ con = nodeid2con(nodeid, GFP_NOFS); ++ if (!con) ++ return -ENOMEM; ++ lowcomms_connect_sock(con); ++ return 0; ++} ++ + /* Make a socket active */ + static int add_sock(struct socket *sock, struct connection *con) + { +@@ -486,7 +500,7 @@ static void process_sctp_notification(st + return; + } + +- new_con = nodeid2con(nodeid, GFP_KERNEL); ++ new_con = nodeid2con(nodeid, GFP_NOFS); + if (!new_con) + return; + +@@ -722,7 +736,7 @@ static int tcp_accept_from_sock(struct c + * the same time and the connections cross on the wire. + * In this case we store the incoming one in "othercon" + */ +- newcon = nodeid2con(nodeid, GFP_KERNEL); ++ newcon = nodeid2con(nodeid, GFP_NOFS); + if (!newcon) { + result = -ENOMEM; + goto accept_err; +@@ -732,7 +746,7 @@ static int tcp_accept_from_sock(struct c + struct connection *othercon = newcon->othercon; + + if (!othercon) { +- othercon = kmem_cache_zalloc(con_cache, GFP_KERNEL); ++ othercon = kmem_cache_zalloc(con_cache, GFP_NOFS); + if (!othercon) { + log_print("failed to allocate incoming socket"); + mutex_unlock(&newcon->sock_mutex); +@@ -888,7 +902,7 @@ static void tcp_connect_to_sock(struct c + int result = -EHOSTUNREACH; + struct sockaddr_storage saddr, src_addr; + int addr_len; +- struct socket *sock; ++ struct socket *sock = NULL; + + if (con->nodeid == 0) { + log_print("attempt to connect sock 0 foiled"); +@@ -948,6 +962,8 @@ out_err: + if (con->sock) { + sock_release(con->sock); + con->sock = NULL; ++ } else if (sock) { ++ sock_release(sock); + } + /* + * Some errors are fatal and this list might need adjusting. For other +@@ -1421,7 +1437,7 @@ static int work_start(void) + static void stop_conn(struct connection *con) + { + con->flags |= 0x0F; +- if (con->sock) ++ if (con->sock && con->sock->sk) + con->sock->sk->sk_user_data = NULL; + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/dlm/lowcomms.h linux-2.6.27.29-0.1.1/fs/dlm/lowcomms.h +--- linux-2.6.27.25-0.1.1/fs/dlm/lowcomms.h 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/dlm/lowcomms.h 2009-08-27 12:43:44.000000000 +0100 +@@ -2,7 +2,7 @@ + ******************************************************************************* + ** + ** Copyright (C) Sistina Software, Inc. 1997-2003 All rights reserved. +-** Copyright (C) 2004-2005 Red Hat, Inc. All rights reserved. ++** Copyright (C) 2004-2009 Red Hat, Inc. All rights reserved. + ** + ** This copyrighted material is made available to anyone wishing to use, + ** modify, copy, or redistribute it subject to the terms and conditions +@@ -19,6 +19,7 @@ void dlm_lowcomms_stop(void); + int dlm_lowcomms_close(int nodeid); + void *dlm_lowcomms_get_buffer(int nodeid, int len, gfp_t allocation, char **ppc); + void dlm_lowcomms_commit_buffer(void *mh); ++int dlm_lowcomms_connect_node(int nodeid); + + #endif /* __LOWCOMMS_DOT_H__ */ + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/dlm/member.c linux-2.6.27.29-0.1.1/fs/dlm/member.c +--- linux-2.6.27.25-0.1.1/fs/dlm/member.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/dlm/member.c 2009-08-27 12:43:44.000000000 +0100 +@@ -1,7 +1,7 @@ + /****************************************************************************** + ******************************************************************************* + ** +-** Copyright (C) 2005-2008 Red Hat, Inc. All rights reserved. ++** Copyright (C) 2005-2009 Red Hat, Inc. All rights reserved. + ** + ** This copyrighted material is made available to anyone wishing to use, + ** modify, copy, or redistribute it subject to the terms and conditions +@@ -17,6 +17,7 @@ + #include "recover.h" + #include "rcom.h" + #include "config.h" ++#include "lowcomms.h" + + static void add_ordered_member(struct dlm_ls *ls, struct dlm_member *new) + { +@@ -45,9 +46,9 @@ static void add_ordered_member(struct dl + static int dlm_add_member(struct dlm_ls *ls, int nodeid) + { + struct dlm_member *memb; +- int w; ++ int w, error; + +- memb = kzalloc(sizeof(struct dlm_member), GFP_KERNEL); ++ memb = kzalloc(sizeof(struct dlm_member), ls->ls_allocation); + if (!memb) + return -ENOMEM; + +@@ -57,6 +58,12 @@ static int dlm_add_member(struct dlm_ls + return w; + } + ++ error = dlm_lowcomms_connect_node(nodeid); ++ if (error < 0) { ++ kfree(memb); ++ return error; ++ } ++ + memb->nodeid = nodeid; + memb->weight = w; + add_ordered_member(ls, memb); +@@ -136,7 +143,7 @@ static void make_member_array(struct dlm + + ls->ls_total_weight = total; + +- array = kmalloc(sizeof(int) * total, GFP_KERNEL); ++ array = kmalloc(sizeof(int) * total, ls->ls_allocation); + if (!array) + return; + +@@ -219,7 +226,7 @@ int dlm_recover_members(struct dlm_ls *l + continue; + log_debug(ls, "new nodeid %d is a re-added member", rv->new[i]); + +- memb = kzalloc(sizeof(struct dlm_member), GFP_KERNEL); ++ memb = kzalloc(sizeof(struct dlm_member), ls->ls_allocation); + if (!memb) + return -ENOMEM; + memb->nodeid = rv->new[i]; +@@ -334,7 +341,7 @@ int dlm_ls_start(struct dlm_ls *ls) + int *ids = NULL, *new = NULL; + int error, ids_count = 0, new_count = 0; + +- rv = kzalloc(sizeof(struct dlm_recover), GFP_KERNEL); ++ rv = kzalloc(sizeof(struct dlm_recover), ls->ls_allocation); + if (!rv) + return -ENOMEM; + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/dlm/plock.c linux-2.6.27.29-0.1.1/fs/dlm/plock.c +--- linux-2.6.27.25-0.1.1/fs/dlm/plock.c 2009-08-05 09:48:58.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/dlm/plock.c 2009-08-27 12:43:44.000000000 +0100 +@@ -353,7 +353,7 @@ static ssize_t dev_write(struct file *fi + { + struct dlm_plock_info info; + struct plock_op *op; +- int found = 0; ++ int found = 0, do_callback = 0; + + if (count != sizeof(info)) + return -EINVAL; +@@ -366,21 +366,24 @@ static ssize_t dev_write(struct file *fi + + spin_lock(&ops_lock); + list_for_each_entry(op, &recv_list, list) { +- if (op->info.fsid == info.fsid && op->info.number == info.number && ++ if (op->info.fsid == info.fsid && ++ op->info.number == info.number && + op->info.owner == info.owner) { ++ struct plock_xop *xop = (struct plock_xop *)op; + list_del_init(&op->list); +- found = 1; +- op->done = 1; + memcpy(&op->info, &info, sizeof(info)); ++ if (xop->callback) ++ do_callback = 1; ++ else ++ op->done = 1; ++ found = 1; + break; + } + } + spin_unlock(&ops_lock); + + if (found) { +- struct plock_xop *xop; +- xop = (struct plock_xop *)op; +- if (xop->callback) ++ if (do_callback) + dlm_plock_callback(op); + else + wake_up(&recv_wq); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/dlm/requestqueue.c linux-2.6.27.29-0.1.1/fs/dlm/requestqueue.c +--- linux-2.6.27.25-0.1.1/fs/dlm/requestqueue.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/dlm/requestqueue.c 2009-08-27 12:43:44.000000000 +0100 +@@ -35,7 +35,7 @@ void dlm_add_requestqueue(struct dlm_ls + struct rq_entry *e; + int length = ms->m_header.h_length - sizeof(struct dlm_message); + +- e = kmalloc(sizeof(struct rq_entry) + length, GFP_KERNEL); ++ e = kmalloc(sizeof(struct rq_entry) + length, ls->ls_allocation); + if (!e) { + log_print("dlm_add_requestqueue: out of memory len %d", length); + return; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/ecryptfs/keystore.c linux-2.6.27.29-0.1.1/fs/ecryptfs/keystore.c +--- linux-2.6.27.25-0.1.1/fs/ecryptfs/keystore.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/ecryptfs/keystore.c 2009-08-27 12:43:44.000000000 +0100 +@@ -730,6 +730,13 @@ parse_tag_3_packet(struct ecryptfs_crypt + } + (*new_auth_tok)->session_key.encrypted_key_size = + (body_size - (ECRYPTFS_SALT_SIZE + 5)); ++ if ((*new_auth_tok)->session_key.encrypted_key_size ++ > ECRYPTFS_MAX_ENCRYPTED_KEY_BYTES) { ++ printk(KERN_WARNING "Tag 3 packet contains key larger " ++ "than ECRYPTFS_MAX_ENCRYPTED_KEY_BYTES\n"); ++ rc = -EINVAL; ++ goto out_free; ++ } + if (unlikely(data[(*packet_size)++] != 0x04)) { + printk(KERN_WARNING "Unknown version number [%d]\n", + data[(*packet_size) - 1]); +@@ -876,6 +883,12 @@ parse_tag_11_packet(unsigned char *data, + rc = -EINVAL; + goto out; + } ++ if (unlikely((*tag_11_contents_size) > max_contents_bytes)) { ++ printk(KERN_ERR "Literal data section in tag 11 packet exceeds " ++ "expected size\n"); ++ rc = -EINVAL; ++ goto out; ++ } + if (data[(*packet_size)++] != 0x62) { + printk(KERN_WARNING "Unrecognizable packet\n"); + rc = -EINVAL; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/ext4/extents.c linux-2.6.27.29-0.1.1/fs/ext4/extents.c +--- linux-2.6.27.25-0.1.1/fs/ext4/extents.c 2009-08-05 09:48:58.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/ext4/extents.c 2009-08-27 12:43:48.000000000 +0100 +@@ -1877,12 +1877,16 @@ ext4_ext_rm_leaf(handle_t *handle, struc + ex = EXT_LAST_EXTENT(eh); + + ex_ee_block = le32_to_cpu(ex->ee_block); +- if (ext4_ext_is_uninitialized(ex)) +- uninitialized = 1; + ex_ee_len = ext4_ext_get_actual_len(ex); + + while (ex >= EXT_FIRST_EXTENT(eh) && + ex_ee_block + ex_ee_len > start) { ++ ++ if (ext4_ext_is_uninitialized(ex)) ++ uninitialized = 1; ++ else ++ uninitialized = 0; ++ + ext_debug("remove ext %lu:%u\n", ex_ee_block, ex_ee_len); + path[depth].p_ext = ex; + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/file_table.c linux-2.6.27.29-0.1.1/fs/file_table.c +--- linux-2.6.27.25-0.1.1/fs/file_table.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/file_table.c 2009-08-27 12:43:48.000000000 +0100 +@@ -210,7 +210,8 @@ int init_file(struct file *file, struct + */ + if ((mode & FMODE_WRITE) && !special_file(dentry->d_inode->i_mode)) { + file_take_write(file); +- mnt_clone_write(mnt); ++ error = mnt_clone_write_2(mnt); ++ WARN_ON(error); + } + return error; + } +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/namespace.c linux-2.6.27.29-0.1.1/fs/namespace.c +--- linux-2.6.27.25-0.1.1/fs/namespace.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/namespace.c 2009-08-27 12:43:48.000000000 +0100 +@@ -272,6 +272,9 @@ EXPORT_SYMBOL_GPL(mnt_want_write); + * on a mountpoint that we already know has a write reference + * on it. This allows some optimisation. + * ++ * The caller should really check __mnt_is_readonly before callint ++ * mnt_clone_write. See mnt_clone_write_2. ++ * + * After finished, mnt_drop_write must be called as usual to + * drop the reference. + */ +@@ -284,6 +287,29 @@ void mnt_clone_write(struct vfsmount *mn + EXPORT_SYMBOL_GPL(mnt_clone_write); + + /** ++ * mnt_clone_write_2 - get write access to a mount ++ * @mnt: the mount on which to take a write ++ * ++ * Same as mnt_clone_write, but it performs the __mnt_is_readonly ++ * check itself, and returns -error on failure. This is the preferred ++ * function. This is here to preserve kABI compatibility. ++ * ++ * After finished, mnt_drop_write must be called as usual to ++ * drop the reference. ++ */ ++int mnt_clone_write_2(struct vfsmount *mnt) ++{ ++ /* superblock may be r/o */ ++ if (__mnt_is_readonly(mnt)) ++ return -EROFS; ++ preempt_disable(); ++ inc_mnt_writers(mnt); ++ preempt_enable(); ++ return 0; ++} ++EXPORT_SYMBOL_GPL(mnt_clone_write_2); ++ ++/** + * mnt_want_write_file - get write access to a file's mount + * @file: the file who's mount on which to take a write + * +@@ -292,12 +318,11 @@ EXPORT_SYMBOL_GPL(mnt_clone_write); + */ + int mnt_want_write_file(struct vfsmount *mnt, struct file *file) + { +- if (!(file->f_mode & FMODE_WRITE)) ++ struct inode *inode = file->f_dentry->d_inode; ++ if (!(file->f_mode & FMODE_WRITE) || special_file(inode->i_mode)) + return mnt_want_write(mnt); +- else { +- mnt_clone_write(mnt); +- return 0; +- } ++ else ++ return mnt_clone_write_2(mnt); + } + EXPORT_SYMBOL_GPL(mnt_want_write_file); + +@@ -1914,6 +1939,21 @@ dput_out: + return retval; + } + ++static struct mnt_namespace *alloc_mnt_ns(void) ++{ ++ struct mnt_namespace *new_ns; ++ ++ new_ns = kmalloc(sizeof(struct mnt_namespace), GFP_KERNEL); ++ if (!new_ns) ++ return ERR_PTR(-ENOMEM); ++ atomic_set(&new_ns->count, 1); ++ new_ns->root = NULL; ++ INIT_LIST_HEAD(&new_ns->list); ++ init_waitqueue_head(&new_ns->poll); ++ new_ns->event = 0; ++ return new_ns; ++} ++ + /* + * Allocate a new namespace structure and populate it with contents + * copied from the namespace of the passed in task structure. +@@ -1925,14 +1965,9 @@ static struct mnt_namespace *dup_mnt_ns( + struct vfsmount *rootmnt = NULL, *pwdmnt = NULL; + struct vfsmount *p, *q; + +- new_ns = kmalloc(sizeof(struct mnt_namespace), GFP_KERNEL); +- if (!new_ns) +- return ERR_PTR(-ENOMEM); +- +- atomic_set(&new_ns->count, 1); +- INIT_LIST_HEAD(&new_ns->list); +- init_waitqueue_head(&new_ns->poll); +- new_ns->event = 0; ++ new_ns = alloc_mnt_ns(); ++ if (IS_ERR(new_ns)) ++ return new_ns; + + down_write(&namespace_sem); + /* First pass: copy the tree topology */ +@@ -1996,6 +2031,24 @@ struct mnt_namespace *copy_mnt_ns(unsign + return new_ns; + } + ++/** ++ * create_mnt_ns - creates a private namespace and adds a root filesystem ++ * @mnt: pointer to the new root filesystem mountpoint ++ */ ++struct mnt_namespace *create_mnt_ns(struct vfsmount *mnt) ++{ ++ struct mnt_namespace *new_ns; ++ ++ new_ns = alloc_mnt_ns(); ++ if (!IS_ERR(new_ns)) { ++ mnt->mnt_ns = new_ns; ++ new_ns->root = mnt; ++ list_add(&new_ns->list, &new_ns->root->mnt_list); ++ } ++ return new_ns; ++} ++EXPORT_SYMBOL(create_mnt_ns); ++ + SYSCALL_DEFINE5(mount, char __user *, dev_name, char __user *, dir_name, + char __user *, type, unsigned long, flags, void __user *, data) + { +@@ -2285,10 +2338,14 @@ void __init mnt_init(void) + init_mount_tree(); + } + +-void __put_mnt_ns(struct mnt_namespace *ns) ++void put_mnt_ns(struct mnt_namespace *ns) + { +- struct vfsmount *root = ns->root; ++ struct vfsmount *root; + LIST_HEAD(umount_list); ++ ++ if (!atomic_dec_and_lock(&ns->count, &vfsmount_lock)) ++ return; ++ root = ns->root; + ns->root = NULL; + spin_unlock(&vfsmount_lock); + down_write(&namespace_sem); +@@ -2299,6 +2356,7 @@ void __put_mnt_ns(struct mnt_namespace * + release_mounts(&umount_list); + kfree(ns); + } ++EXPORT_SYMBOL(put_mnt_ns); + + char *d_namespace_path(struct dentry *dentry, struct vfsmount *vfsmnt, + char *buf, int buflen) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/nfs/namespace.c linux-2.6.27.29-0.1.1/fs/nfs/namespace.c +--- linux-2.6.27.25-0.1.1/fs/nfs/namespace.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/nfs/namespace.c 2009-08-27 12:43:44.000000000 +0100 +@@ -65,6 +65,11 @@ char *nfs_path(const char *base, + dentry = dentry->d_parent; + } + spin_unlock(&dcache_lock); ++ if (*end != '/') { ++ if (--buflen < 0) ++ goto Elong; ++ *--end = '/'; ++ } + namelen = strlen(base); + /* Strip off excess slashes in base string */ + while (namelen > 0 && base[namelen - 1] == '/') +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/nfs/super.c linux-2.6.27.29-0.1.1/fs/nfs/super.c +--- linux-2.6.27.25-0.1.1/fs/nfs/super.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/nfs/super.c 2009-08-27 12:43:44.000000000 +0100 +@@ -42,6 +42,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -244,10 +246,14 @@ static const struct super_operations nfs + #ifdef CONFIG_NFS_V4 + static int nfs4_get_sb(struct file_system_type *fs_type, + int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt); ++static int nfs4_remote_get_sb(struct file_system_type *fs_type, ++ int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt); + static int nfs4_xdev_get_sb(struct file_system_type *fs_type, + int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt); + static int nfs4_referral_get_sb(struct file_system_type *fs_type, + int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt); ++static int nfs4_remote_referral_get_sb(struct file_system_type *fs_type, ++ int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt); + static void nfs4_kill_super(struct super_block *sb); + + static struct file_system_type nfs4_fs_type = { +@@ -258,6 +264,14 @@ static struct file_system_type nfs4_fs_t + .fs_flags = FS_RENAME_DOES_D_MOVE|FS_REVAL_DOT|FS_BINARY_MOUNTDATA, + }; + ++static struct file_system_type nfs4_remote_fs_type = { ++ .owner = THIS_MODULE, ++ .name = "nfs4", ++ .get_sb = nfs4_remote_get_sb, ++ .kill_sb = nfs4_kill_super, ++ .fs_flags = FS_RENAME_DOES_D_MOVE|FS_REVAL_DOT|FS_BINARY_MOUNTDATA, ++}; ++ + struct file_system_type nfs4_xdev_fs_type = { + .owner = THIS_MODULE, + .name = "nfs4", +@@ -266,6 +280,14 @@ struct file_system_type nfs4_xdev_fs_typ + .fs_flags = FS_RENAME_DOES_D_MOVE|FS_REVAL_DOT|FS_BINARY_MOUNTDATA, + }; + ++static struct file_system_type nfs4_remote_referral_fs_type = { ++ .owner = THIS_MODULE, ++ .name = "nfs4", ++ .get_sb = nfs4_remote_referral_get_sb, ++ .kill_sb = nfs4_kill_super, ++ .fs_flags = FS_RENAME_DOES_D_MOVE|FS_REVAL_DOT|FS_BINARY_MOUNTDATA, ++}; ++ + struct file_system_type nfs4_referral_fs_type = { + .owner = THIS_MODULE, + .name = "nfs4", +@@ -2294,12 +2316,12 @@ out_no_client_address: + } + + /* +- * Get the superblock for an NFS4 mountpoint ++ * Get the superblock for the NFS4 root partition + */ +-static int nfs4_get_sb(struct file_system_type *fs_type, ++static int nfs4_remote_get_sb(struct file_system_type *fs_type, + int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt) + { +- struct nfs_parsed_mount_data *data; ++ struct nfs_parsed_mount_data *data = raw_data; + struct super_block *s; + struct nfs_server *server; + struct nfs_fh *mntfh; +@@ -2310,18 +2332,12 @@ static int nfs4_get_sb(struct file_syste + }; + int error = -ENOMEM; + +- data = kzalloc(sizeof(*data), GFP_KERNEL); + mntfh = kzalloc(sizeof(*mntfh), GFP_KERNEL); + if (data == NULL || mntfh == NULL) + goto out_free_fh; + + security_init_mnt_opts(&data->lsm_opts); + +- /* Validate the mount data */ +- error = nfs4_validate_mount_data(raw_data, data, dev_name); +- if (error < 0) +- goto out; +- + /* Get a volume representation */ + server = nfs4_create_server(data, mntfh); + if (IS_ERR(server)) { +@@ -2334,7 +2350,7 @@ static int nfs4_get_sb(struct file_syste + compare_super = NULL; + + /* Get a superblock - note that we may end up sharing one that already exists */ +- s = sget(fs_type, compare_super, nfs_set_super, &sb_mntdata); ++ s = sget(&nfs4_fs_type, compare_super, nfs_set_super, &sb_mntdata); + if (IS_ERR(s)) { + error = PTR_ERR(s); + goto out_free; +@@ -2370,13 +2386,9 @@ static int nfs4_get_sb(struct file_syste + error = 0; + + out: +- kfree(data->client_address); +- kfree(data->nfs_server.export_path); +- kfree(data->nfs_server.hostname); + security_free_mnt_opts(&data->lsm_opts); + out_free_fh: + kfree(mntfh); +- kfree(data); + return error; + + out_free: +@@ -2391,6 +2403,125 @@ error_splat_super: + goto out; + } + ++static struct vfsmount *nfs_do_root_mount(struct file_system_type *fs_type, ++ int flags, void *data, const char *hostname) ++{ ++ struct vfsmount *root_mnt; ++ char *root_devname; ++ size_t len; ++ ++ len = strlen(hostname) + 3; ++ root_devname = kmalloc(len, GFP_KERNEL); ++ if (root_devname == NULL) ++ return ERR_PTR(-ENOMEM); ++ snprintf(root_devname, len, "%s:/", hostname); ++ root_mnt = vfs_kern_mount(fs_type, flags, root_devname, data); ++ kfree(root_devname); ++ return root_mnt; ++} ++ ++static void nfs_fix_devname(const struct path *path, struct vfsmount *mnt) ++{ ++ char *page = (char *) __get_free_page(GFP_KERNEL); ++ char *devname, *tmp; ++ ++ if (page == NULL) ++ return; ++ devname = nfs_path(path->mnt->mnt_devname, ++ path->mnt->mnt_root, path->dentry, ++ page, PAGE_SIZE); ++ if (devname == NULL) ++ goto out_freepage; ++ tmp = kstrdup(devname, GFP_KERNEL); ++ if (tmp == NULL) ++ goto out_freepage; ++ kfree(mnt->mnt_devname); ++ mnt->mnt_devname = tmp; ++out_freepage: ++ free_page((unsigned long)page); ++} ++ ++static int nfs_follow_remote_path(struct vfsmount *root_mnt, ++ const char *export_path, struct vfsmount *mnt_target) ++{ ++ struct mnt_namespace *ns_private; ++ struct nameidata nd; ++ struct super_block *s; ++ int ret; ++ ++ ns_private = create_mnt_ns(root_mnt); ++ ret = PTR_ERR(ns_private); ++ if (IS_ERR(ns_private)) ++ goto out_mntput; ++ ++ ret = vfs_path_lookup(root_mnt->mnt_root, root_mnt, ++ export_path, LOOKUP_FOLLOW, &nd); ++ ++ put_mnt_ns(ns_private); ++ ++ if (ret != 0) ++ goto out_err; ++ ++ s = nd.path.mnt->mnt_sb; ++ atomic_inc(&s->s_active); ++ mnt_target->mnt_sb = s; ++ mnt_target->mnt_root = dget(nd.path.dentry); ++ ++ /* Correct the device pathname */ ++ nfs_fix_devname(&nd.path, mnt_target); ++ ++ path_put(&nd.path); ++ down_write(&s->s_umount); ++ return 0; ++out_mntput: ++ mntput(root_mnt); ++out_err: ++ return ret; ++} ++ ++/* ++ * Get the superblock for an NFS4 mountpoint ++ */ ++static int nfs4_get_sb(struct file_system_type *fs_type, ++ int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt) ++{ ++ struct nfs_parsed_mount_data *data; ++ char *export_path; ++ struct vfsmount *root_mnt; ++ int error = -ENOMEM; ++ ++ data = kzalloc(sizeof(*data), GFP_KERNEL); ++ if (data == NULL) ++ goto out_free_data; ++ ++ /* Validate the mount data */ ++ error = nfs4_validate_mount_data(raw_data, data, dev_name); ++ if (error < 0) ++ goto out; ++ ++ export_path = data->nfs_server.export_path; ++ data->nfs_server.export_path = "/"; ++ root_mnt = nfs_do_root_mount(&nfs4_remote_fs_type, flags, data, ++ data->nfs_server.hostname); ++ data->nfs_server.export_path = export_path; ++ ++ error = PTR_ERR(root_mnt); ++ if (IS_ERR(root_mnt)) ++ goto out; ++ ++ error = nfs_follow_remote_path(root_mnt, export_path, mnt); ++ ++out: ++ kfree(data->client_address); ++ kfree(data->nfs_server.export_path); ++ kfree(data->nfs_server.hostname); ++out_free_data: ++ kfree(data); ++ dprintk("<-- nfs4_get_sb() = %d%s\n", error, ++ error != 0 ? " [error]" : ""); ++ return error; ++} ++ + static void nfs4_kill_super(struct super_block *sb) + { + struct nfs_server *server = NFS_SB(sb); +@@ -2486,12 +2617,9 @@ error_splat_super: + return error; + } + +-/* +- * Create an NFS4 server record on referral traversal +- */ +-static int nfs4_referral_get_sb(struct file_system_type *fs_type, int flags, +- const char *dev_name, void *raw_data, +- struct vfsmount *mnt) ++static int nfs4_remote_referral_get_sb(struct file_system_type *fs_type, ++ int flags, const char *dev_name, void *raw_data, ++ struct vfsmount *mnt) + { + struct nfs_clone_mount *data = raw_data; + struct super_block *s; +@@ -2571,4 +2699,36 @@ error_splat_super: + return error; + } + ++/* ++ * Create an NFS4 server record on referral traversal ++ */ ++static int nfs4_referral_get_sb(struct file_system_type *fs_type, ++ int flags, const char *dev_name, void *raw_data, ++ struct vfsmount *mnt) ++{ ++ struct nfs_clone_mount *data = raw_data; ++ char *export_path; ++ struct vfsmount *root_mnt; ++ int error; ++ ++ dprintk("--> nfs4_referral_get_sb()\n"); ++ ++ export_path = data->mnt_path; ++ data->mnt_path = "/"; ++ ++ root_mnt = nfs_do_root_mount(&nfs4_remote_referral_fs_type, ++ flags, data, data->hostname); ++ data->mnt_path = export_path; ++ ++ error = PTR_ERR(root_mnt); ++ if (IS_ERR(root_mnt)) ++ goto out; ++ ++ error = nfs_follow_remote_path(root_mnt, export_path, mnt); ++out: ++ dprintk("<-- nfs4_referral_get_sb() = %d%s\n", error, ++ error != 0 ? " [error]" : ""); ++ return error; ++} ++ + #endif /* CONFIG_NFS_V4 */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/ocfs2/aops.c linux-2.6.27.29-0.1.1/fs/ocfs2/aops.c +--- linux-2.6.27.25-0.1.1/fs/ocfs2/aops.c 2009-08-05 09:49:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/ocfs2/aops.c 2009-08-27 12:43:48.000000000 +0100 +@@ -145,9 +145,11 @@ static int ocfs2_get_block(struct inode + mlog_entry("(0x%p, %llu, 0x%p, %d)\n", inode, + (unsigned long long)iblock, bh_result, create); + +- if (OCFS2_I(inode)->ip_flags & OCFS2_INODE_SYSTEM_FILE) ++ if (OCFS2_I(inode)->ip_flags & OCFS2_INODE_SYSTEM_FILE) { + mlog(ML_NOTICE, "get_block on system inode 0x%p (%lu)\n", + inode, inode->i_ino); ++ dump_stack(); ++ } + + if (S_ISLNK(inode->i_mode)) { + /* this always does I/O for some reason. */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/ocfs2/file.c linux-2.6.27.29-0.1.1/fs/ocfs2/file.c +--- linux-2.6.27.25-0.1.1/fs/ocfs2/file.c 2009-08-27 12:58:49.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/ocfs2/file.c 2009-08-27 12:43:48.000000000 +0100 +@@ -899,9 +899,9 @@ int ocfs2_setattr(struct dentry *dentry, + struct ocfs2_super *osb = OCFS2_SB(sb); + struct buffer_head *bh = NULL; + handle_t *handle = NULL; +- int locked[MAXQUOTAS] = {0, 0}; +- int credits, qtype; +- struct ocfs2_mem_dqinfo *oinfo; ++ int qtype; ++ struct dquot *transfer_from[MAXQUOTAS] = { }; ++ struct dquot *transfer_to[MAXQUOTAS] = { }; + + mlog_entry("(0x%p, '%.*s')\n", dentry, + dentry->d_name.len, dentry->d_name.name); +@@ -974,30 +974,37 @@ int ocfs2_setattr(struct dentry *dentry, + + if ((attr->ia_valid & ATTR_UID && attr->ia_uid != inode->i_uid) || + (attr->ia_valid & ATTR_GID && attr->ia_gid != inode->i_gid)) { +- credits = OCFS2_INODE_UPDATE_CREDITS; ++ /* ++ * Gather pointers to quota structures so that allocation / ++ * freeing of quota structures happens here and not inside ++ * vfs_dq_transfer() where we have problems with lock ordering ++ */ + if (attr->ia_valid & ATTR_UID && attr->ia_uid != inode->i_uid + && OCFS2_HAS_RO_COMPAT_FEATURE(sb, + OCFS2_FEATURE_RO_COMPAT_USRQUOTA)) { +- oinfo = sb_dqinfo(sb, USRQUOTA)->dqi_priv; +- status = ocfs2_lock_global_qf(oinfo, 1); +- if (status < 0) ++ transfer_to[USRQUOTA] = dqget(sb, attr->ia_uid, ++ USRQUOTA); ++ transfer_from[USRQUOTA] = dqget(sb, inode->i_uid, ++ USRQUOTA); ++ if (!transfer_to[USRQUOTA] || !transfer_from[USRQUOTA]) { ++ status = -ESRCH; + goto bail_unlock; +- credits += ocfs2_calc_qinit_credits(sb, USRQUOTA) + +- ocfs2_calc_qdel_credits(sb, USRQUOTA); +- locked[USRQUOTA] = 1; ++ } + } + if (attr->ia_valid & ATTR_GID && attr->ia_gid != inode->i_gid + && OCFS2_HAS_RO_COMPAT_FEATURE(sb, + OCFS2_FEATURE_RO_COMPAT_GRPQUOTA)) { +- oinfo = sb_dqinfo(sb, GRPQUOTA)->dqi_priv; +- status = ocfs2_lock_global_qf(oinfo, 1); +- if (status < 0) ++ transfer_to[GRPQUOTA] = dqget(sb, attr->ia_gid, ++ GRPQUOTA); ++ transfer_from[GRPQUOTA] = dqget(sb, inode->i_gid, ++ GRPQUOTA); ++ if (!transfer_to[GRPQUOTA] || !transfer_from[GRPQUOTA]) { ++ status = -ESRCH; + goto bail_unlock; +- credits += ocfs2_calc_qinit_credits(sb, GRPQUOTA) + +- ocfs2_calc_qdel_credits(sb, GRPQUOTA); +- locked[GRPQUOTA] = 1; ++ } + } +- handle = ocfs2_start_trans(osb, credits); ++ handle = ocfs2_start_trans(osb, OCFS2_INODE_UPDATE_CREDITS + ++ 2 * ocfs2_quota_trans_credits(sb)); + if (IS_ERR(handle)) { + status = PTR_ERR(handle); + mlog_errno(status); +@@ -1035,12 +1042,6 @@ int ocfs2_setattr(struct dentry *dentry, + bail_commit: + ocfs2_commit_trans(osb, handle); + bail_unlock: +- for (qtype = 0; qtype < MAXQUOTAS; qtype++) { +- if (!locked[qtype]) +- continue; +- oinfo = sb_dqinfo(sb, qtype)->dqi_priv; +- ocfs2_unlock_global_qf(oinfo, 1); +- } + ocfs2_inode_unlock(inode, 1); + bail_unlock_rw: + if (size_change) +@@ -1048,6 +1049,12 @@ bail_unlock_rw: + bail: + brelse(bh); + ++ /* Release quota pointers in case we acquired them */ ++ for (qtype = 0; qtype < MAXQUOTAS; qtype++) { ++ dqput(transfer_to[qtype]); ++ dqput(transfer_from[qtype]); ++ } ++ + if (!status && attr->ia_valid & ATTR_MODE) { + status = ocfs2_acl_chmod(inode); + if (status < 0) +@@ -1848,6 +1855,7 @@ relock: + if (ret) + goto out_dio; + ++ count = ocount; + ret = generic_write_checks(file, ppos, &count, + S_ISBLK(inode->i_mode)); + if (ret) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/ocfs2/quota_global.c linux-2.6.27.29-0.1.1/fs/ocfs2/quota_global.c +--- linux-2.6.27.25-0.1.1/fs/ocfs2/quota_global.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/ocfs2/quota_global.c 2009-08-27 12:43:48.000000000 +0100 +@@ -145,14 +145,16 @@ ssize_t ocfs2_quota_write(struct super_b + } + mutex_lock_nested(&gqinode->i_mutex, I_MUTEX_QUOTA); + if (gqinode->i_size < off + len) { ++ loff_t rounded_end = ALIGN(off + len, sb->s_blocksize); ++ + down_write(&OCFS2_I(gqinode)->ip_alloc_sem); +- err = ocfs2_extend_no_holes(gqinode, off + len, off); ++ err = ocfs2_extend_no_holes(gqinode, rounded_end, off); + up_write(&OCFS2_I(gqinode)->ip_alloc_sem); + if (err < 0) + goto out; + err = ocfs2_simple_size_update(gqinode, + oinfo->dqi_gqi_bh, +- off + len); ++ rounded_end); + if (err < 0) + goto out; + } +@@ -275,7 +277,6 @@ int ocfs2_global_read_info(struct super_ + info->dqi_bgrace = le32_to_cpu(dinfo.dqi_bgrace); + info->dqi_igrace = le32_to_cpu(dinfo.dqi_igrace); + oinfo->dqi_syncms = le32_to_cpu(dinfo.dqi_syncms); +- oinfo->dqi_syncjiff = msecs_to_jiffies(oinfo->dqi_syncms); + oinfo->dqi_gi.dqi_blocks = le32_to_cpu(dinfo.dqi_blocks); + oinfo->dqi_gi.dqi_free_blk = le32_to_cpu(dinfo.dqi_free_blk); + oinfo->dqi_gi.dqi_free_entry = le32_to_cpu(dinfo.dqi_free_entry); +@@ -286,7 +287,7 @@ int ocfs2_global_read_info(struct super_ + setup_timer(&oinfo->dqi_sync_timer, qsync_timer_fn, + (unsigned long)oinfo); + mod_timer(&oinfo->dqi_sync_timer, +- round_jiffies(jiffies + oinfo->dqi_syncjiff)); ++ round_jiffies(jiffies+msecs_to_jiffies(oinfo->dqi_syncms))); + out_err: + mlog_exit(status); + return status; +@@ -354,6 +355,7 @@ int ocfs2_global_read_dquot(struct dquot + OCFS2_DQUOT(dquot)->dq_originodes = dquot->dq_dqb.dqb_curinodes; + if (!dquot->dq_off) { /* No real quota entry? */ + /* Upgrade to exclusive lock for allocation */ ++ ocfs2_qinfo_unlock(info, 0); + err = ocfs2_qinfo_lock(info, 1); + if (err < 0) + goto out_qlock; +@@ -368,7 +370,8 @@ int ocfs2_global_read_dquot(struct dquot + out_qlock: + if (ex) + ocfs2_qinfo_unlock(info, 1); +- ocfs2_qinfo_unlock(info, 0); ++ else ++ ocfs2_qinfo_unlock(info, 0); + out: + if (err < 0) + mlog_errno(err); +@@ -543,7 +546,7 @@ static void qsync_timer_fn(unsigned long + + pdflush_operation(ocfs2_do_qsync, oinfo_ptr); + mod_timer(&oinfo->dqi_sync_timer, +- round_jiffies(jiffies + oinfo->dqi_syncjiff)); ++ round_jiffies(jiffies+msecs_to_jiffies(oinfo->dqi_syncms))); + } + + /* +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/ocfs2/quota.h linux-2.6.27.29-0.1.1/fs/ocfs2/quota.h +--- linux-2.6.27.25-0.1.1/fs/ocfs2/quota.h 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/ocfs2/quota.h 2009-08-27 12:43:48.000000000 +0100 +@@ -55,7 +55,6 @@ struct ocfs2_mem_dqinfo { + unsigned int dqi_chunks; /* Number of chunks in local quota file */ + unsigned int dqi_blocks; /* Number of blocks allocated for local quota file */ + unsigned int dqi_syncms; /* How often should we sync with other nodes */ +- unsigned int dqi_syncjiff; /* Precomputed dqi_syncms in jiffies */ + struct list_head dqi_chunk; /* List of chunks */ + struct inode *dqi_gqinode; /* Global quota file inode */ + struct ocfs2_lock_res dqi_gqlock; /* Lock protecting quota information structure */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/ocfs2/quota_local.c linux-2.6.27.29-0.1.1/fs/ocfs2/quota_local.c +--- linux-2.6.27.25-0.1.1/fs/ocfs2/quota_local.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/ocfs2/quota_local.c 2009-08-27 12:43:48.000000000 +0100 +@@ -20,6 +20,7 @@ + #include "sysfile.h" + #include "dlmglue.h" + #include "quota.h" ++#include "uptodate.h" + + /* Number of local quota structures per block */ + static inline unsigned int ol_quota_entries_per_block(struct super_block *sb) +@@ -438,10 +439,6 @@ static int ocfs2_recover_local_quota_fil + + mlog_entry("ino=%lu type=%u", (unsigned long)lqinode->i_ino, type); + +- status = ocfs2_lock_global_qf(oinfo, 1); +- if (status < 0) +- goto out; +- + list_for_each_entry_safe(rchunk, next, &(rec->r_list[type]), rc_list) { + chunk = rchunk->rc_chunk; + hbh = ocfs2_bread(lqinode, ol_quota_chunk_block(sb, chunk), +@@ -471,12 +468,18 @@ static int ocfs2_recover_local_quota_fil + type); + goto out_put_bh; + } ++ status = ocfs2_lock_global_qf(oinfo, 1); ++ if (status < 0) { ++ mlog_errno(status); ++ goto out_put_dquot; ++ } ++ + handle = ocfs2_start_trans(OCFS2_SB(sb), + OCFS2_QSYNC_CREDITS); + if (IS_ERR(handle)) { + status = PTR_ERR(handle); + mlog_errno(status); +- goto out_put_dquot; ++ goto out_drop_lock; + } + mutex_lock(&sb_dqopt(sb)->dqio_mutex); + spin_lock(&dq_data_lock); +@@ -514,6 +517,8 @@ static int ocfs2_recover_local_quota_fil + out_commit: + mutex_unlock(&sb_dqopt(sb)->dqio_mutex); + ocfs2_commit_trans(OCFS2_SB(sb), handle); ++out_drop_lock: ++ ocfs2_unlock_global_qf(oinfo, 1); + out_put_dquot: + dqput(dquot); + out_put_bh: +@@ -528,8 +533,6 @@ out_put_bh: + if (status < 0) + break; + } +- ocfs2_unlock_global_qf(oinfo, 1); +-out: + if (status < 0) + free_recovery_list(&(rec->r_list[type])); + mlog_exit(status); +@@ -645,6 +648,9 @@ static int ocfs2_local_read_info(struct + struct ocfs2_quota_recovery *rec; + int locked = 0; + ++ /* We don't need the lock and we have to acquire quota file locks ++ * which will later depend on this lock */ ++ mutex_unlock(&sb_dqopt(sb)->dqio_mutex); + info->dqi_maxblimit = 0x7fffffffffffffffLL; + info->dqi_maxilimit = 0x7fffffffffffffffLL; + oinfo = kmalloc(sizeof(struct ocfs2_mem_dqinfo), GFP_NOFS); +@@ -723,6 +729,7 @@ static int ocfs2_local_read_info(struct + goto out_err; + } + ++ mutex_lock(&sb_dqopt(sb)->dqio_mutex); + return 0; + out_err: + if (oinfo) { +@@ -736,6 +743,7 @@ out_err: + kfree(oinfo); + } + brelse(bh); ++ mutex_lock(&sb_dqopt(sb)->dqio_mutex); + return -1; + } + +@@ -922,7 +930,7 @@ static struct ocfs2_quota_chunk *ocfs2_l + struct ocfs2_local_disk_chunk *dchunk; + int status; + handle_t *handle; +- struct buffer_head *bh = NULL; ++ struct buffer_head *bh = NULL, *dbh = NULL; + u64 p_blkno; + + /* We are protected by dqio_sem so no locking needed */ +@@ -961,9 +969,11 @@ static struct ocfs2_quota_chunk *ocfs2_l + mlog_errno(status); + goto out; + } ++ ocfs2_set_new_buffer_uptodate(lqinode, bh); ++ + dchunk = (struct ocfs2_local_disk_chunk *)bh->b_data; + +- handle = ocfs2_start_trans(OCFS2_SB(sb), 2); ++ handle = ocfs2_start_trans(OCFS2_SB(sb), 3); + if (IS_ERR(handle)) { + status = PTR_ERR(handle); + mlog_errno(status); +@@ -981,7 +991,6 @@ static struct ocfs2_quota_chunk *ocfs2_l + memset(dchunk->dqc_bitmap, 0, + sb->s_blocksize - sizeof(struct ocfs2_local_disk_chunk) - + OCFS2_QBLK_RESERVED_SPACE); +- set_buffer_uptodate(bh); + unlock_buffer(bh); + status = ocfs2_journal_dirty(handle, bh); + if (status < 0) { +@@ -989,6 +998,38 @@ static struct ocfs2_quota_chunk *ocfs2_l + goto out_trans; + } + ++ /* Initialize new block with structures */ ++ down_read(&OCFS2_I(lqinode)->ip_alloc_sem); ++ status = ocfs2_extent_map_get_blocks(lqinode, oinfo->dqi_blocks + 1, ++ &p_blkno, NULL, NULL); ++ up_read(&OCFS2_I(lqinode)->ip_alloc_sem); ++ if (status < 0) { ++ mlog_errno(status); ++ goto out_trans; ++ } ++ dbh = sb_getblk(sb, p_blkno); ++ if (!dbh) { ++ status = -ENOMEM; ++ mlog_errno(status); ++ goto out_trans; ++ } ++ ocfs2_set_new_buffer_uptodate(lqinode, dbh); ++ status = ocfs2_journal_access(handle, lqinode, dbh, ++ OCFS2_JOURNAL_ACCESS_CREATE); ++ if (status < 0) { ++ mlog_errno(status); ++ goto out_trans; ++ } ++ lock_buffer(dbh); ++ memset(dbh->b_data, 0, sb->s_blocksize - OCFS2_QBLK_RESERVED_SPACE); ++ unlock_buffer(dbh); ++ status = ocfs2_journal_dirty(handle, dbh); ++ if (status < 0) { ++ mlog_errno(status); ++ goto out_trans; ++ } ++ ++ /* Update local quotafile info */ + oinfo->dqi_blocks += 2; + oinfo->dqi_chunks++; + status = ocfs2_local_write_info(sb, type); +@@ -1013,6 +1054,7 @@ out_trans: + ocfs2_commit_trans(OCFS2_SB(sb), handle); + out: + brelse(bh); ++ brelse(dbh); + kmem_cache_free(ocfs2_qf_chunk_cachep, chunk); + return ERR_PTR(status); + } +@@ -1030,6 +1072,8 @@ static struct ocfs2_quota_chunk *ocfs2_e + struct ocfs2_local_disk_chunk *dchunk; + int epb = ol_quota_entries_per_block(sb); + unsigned int chunk_blocks; ++ struct buffer_head *bh; ++ u64 p_blkno; + int status; + handle_t *handle; + +@@ -1057,12 +1101,46 @@ static struct ocfs2_quota_chunk *ocfs2_e + mlog_errno(status); + goto out; + } +- handle = ocfs2_start_trans(OCFS2_SB(sb), 2); ++ ++ /* Get buffer from the just added block */ ++ down_read(&OCFS2_I(lqinode)->ip_alloc_sem); ++ status = ocfs2_extent_map_get_blocks(lqinode, oinfo->dqi_blocks, ++ &p_blkno, NULL, NULL); ++ up_read(&OCFS2_I(lqinode)->ip_alloc_sem); ++ if (status < 0) { ++ mlog_errno(status); ++ goto out; ++ } ++ bh = sb_getblk(sb, p_blkno); ++ if (!bh) { ++ status = -ENOMEM; ++ mlog_errno(status); ++ goto out; ++ } ++ ocfs2_set_new_buffer_uptodate(lqinode, bh); ++ ++ handle = ocfs2_start_trans(OCFS2_SB(sb), 3); + if (IS_ERR(handle)) { + status = PTR_ERR(handle); + mlog_errno(status); + goto out; + } ++ /* Zero created block */ ++ status = ocfs2_journal_access(handle, lqinode, bh, ++ OCFS2_JOURNAL_ACCESS_CREATE); ++ if (status < 0) { ++ mlog_errno(status); ++ goto out_trans; ++ } ++ lock_buffer(bh); ++ memset(bh->b_data, 0, sb->s_blocksize); ++ unlock_buffer(bh); ++ status = ocfs2_journal_dirty(handle, bh); ++ if (status < 0) { ++ mlog_errno(status); ++ goto out_trans; ++ } ++ /* Update chunk header */ + status = ocfs2_journal_access(handle, lqinode, chunk->qc_headerbh, + OCFS2_JOURNAL_ACCESS_WRITE); + if (status < 0) { +@@ -1079,6 +1157,7 @@ static struct ocfs2_quota_chunk *ocfs2_e + mlog_errno(status); + goto out_trans; + } ++ /* Update file header */ + oinfo->dqi_blocks++; + status = ocfs2_local_write_info(sb, type); + if (status < 0) { +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/fs/udf/lowlevel.c linux-2.6.27.29-0.1.1/fs/udf/lowlevel.c +--- linux-2.6.27.25-0.1.1/fs/udf/lowlevel.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/fs/udf/lowlevel.c 2009-08-27 12:43:44.000000000 +0100 +@@ -56,7 +56,12 @@ unsigned long udf_get_last_block(struct + struct block_device *bdev = sb->s_bdev; + unsigned long lblock = 0; + +- if (ioctl_by_bdev(bdev, CDROM_LAST_WRITTEN, (unsigned long) &lblock)) ++ /* ++ * ioctl failed or returned obviously bogus value? ++ * Try using the device size... ++ */ ++ if (ioctl_by_bdev(bdev, CDROM_LAST_WRITTEN, (unsigned long) &lblock) || ++ lblock == 0) + lblock = bdev->bd_inode->i_size >> sb->s_blocksize_bits; + + if (lblock) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/include/linux/firmware-map.h linux-2.6.27.29-0.1.1/include/linux/firmware-map.h +--- linux-2.6.27.25-0.1.1/include/linux/firmware-map.h 2009-08-05 09:43:34.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/include/linux/firmware-map.h 2009-08-27 12:44:48.000000000 +0100 +@@ -24,19 +24,17 @@ + */ + #ifdef CONFIG_FIRMWARE_MEMMAP + +-int firmware_map_add(uint64_t start, uint64_t end, const char *type); +-int firmware_map_add_early(uint64_t start, uint64_t end, const char *type); ++int firmware_map_add(u64 start, u64 end, const char *type); ++int firmware_map_add_early(u64 start, u64 end, const char *type); + + #else /* CONFIG_FIRMWARE_MEMMAP */ + +-static inline int firmware_map_add(uint64_t start, uint64_t end, +- const char *type) ++static inline int firmware_map_add(u64 start, u64 end, const char *type) + { + return 0; + } + +-static inline int firmware_map_add_early(uint64_t start, uint64_t end, +- const char *type) ++static inline int firmware_map_add_early(u64 start, u64 end, const char *type) + { + return 0; + } +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/include/linux/mlx4/qp.h linux-2.6.27.29-0.1.1/include/linux/mlx4/qp.h +--- linux-2.6.27.25-0.1.1/include/linux/mlx4/qp.h 2009-08-05 09:43:31.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/include/linux/mlx4/qp.h 2009-08-27 12:44:46.000000000 +0100 +@@ -165,6 +165,7 @@ enum { + MLX4_WQE_CTRL_IP_CSUM = 1 << 4, + MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, + MLX4_WQE_CTRL_INS_VLAN = 1 << 6, ++ MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, + }; + + struct mlx4_wqe_ctrl_seg { +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/include/linux/mm.h linux-2.6.27.29-0.1.1/include/linux/mm.h +--- linux-2.6.27.25-0.1.1/include/linux/mm.h 2009-08-27 12:59:47.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/include/linux/mm.h 2009-08-27 12:44:46.000000000 +0100 +@@ -599,12 +599,10 @@ static inline void set_page_links(struct + */ + static inline unsigned long round_hint_to_min(unsigned long hint) + { +-#ifdef CONFIG_SECURITY + hint &= PAGE_MASK; + if (((void *)hint != NULL) && + (hint < mmap_min_addr)) + return PAGE_ALIGN(mmap_min_addr); +-#endif + return hint; + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/include/linux/mnt_namespace.h linux-2.6.27.29-0.1.1/include/linux/mnt_namespace.h +--- linux-2.6.27.25-0.1.1/include/linux/mnt_namespace.h 2009-08-05 09:43:31.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/include/linux/mnt_namespace.h 2009-08-27 12:44:46.000000000 +0100 +@@ -22,16 +22,10 @@ struct proc_mounts { + int event; + }; + ++extern struct mnt_namespace *create_mnt_ns(struct vfsmount *mnt); + extern struct mnt_namespace *copy_mnt_ns(unsigned long, struct mnt_namespace *, + struct fs_struct *); +-extern void __put_mnt_ns(struct mnt_namespace *ns); +- +-static inline void put_mnt_ns(struct mnt_namespace *ns) +-{ +- if (atomic_dec_and_lock(&ns->count, &vfsmount_lock)) +- /* releases vfsmount_lock */ +- __put_mnt_ns(ns); +-} ++extern void put_mnt_ns(struct mnt_namespace *ns); + + static inline void exit_mnt_ns(struct task_struct *p) + { +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/include/linux/mount.h linux-2.6.27.29-0.1.1/include/linux/mount.h +--- linux-2.6.27.25-0.1.1/include/linux/mount.h 2009-08-05 09:43:34.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/include/linux/mount.h 2009-08-27 12:44:46.000000000 +0100 +@@ -98,9 +98,12 @@ static inline struct vfsmount *mntget(st + return mnt; + } + ++struct file; ++ + extern int mnt_want_write(struct vfsmount *mnt); + extern int mnt_want_write_file(struct vfsmount *mnt, struct file *file); + extern void mnt_clone_write(struct vfsmount *mnt); ++extern int mnt_clone_write_2(struct vfsmount *mnt); + extern void mnt_drop_write(struct vfsmount *mnt); + extern void mntput_no_expire(struct vfsmount *mnt); + extern void mnt_pin(struct vfsmount *mnt); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/include/linux/oprofile.h linux-2.6.27.29-0.1.1/include/linux/oprofile.h +--- linux-2.6.27.25-0.1.1/include/linux/oprofile.h 2009-08-05 09:50:06.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/include/linux/oprofile.h 2009-08-27 12:44:48.000000000 +0100 +@@ -37,9 +37,12 @@ + #define TRACE_BEGIN_CODE 8 + #define TRACE_END_CODE 9 + #define XEN_ENTER_SWITCH_CODE 10 ++#ifndef CONFIG_XEN + #define SPU_PROFILING_CODE 11 + #define SPU_CTX_SWITCH_CODE 12 +-#define DOMAIN_SWITCH_CODE 13 ++#else ++#define DOMAIN_SWITCH_CODE 11 ++#endif + + struct super_block; + struct dentry; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/include/linux/personality.h linux-2.6.27.29-0.1.1/include/linux/personality.h +--- linux-2.6.27.25-0.1.1/include/linux/personality.h 2009-08-05 09:43:31.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/include/linux/personality.h 2009-08-27 12:44:46.000000000 +0100 +@@ -40,7 +40,10 @@ enum { + * Security-relevant compatibility flags that must be + * cleared upon setuid or setgid exec: + */ +-#define PER_CLEAR_ON_SETID (READ_IMPLIES_EXEC|ADDR_NO_RANDOMIZE) ++#define PER_CLEAR_ON_SETID (READ_IMPLIES_EXEC | \ ++ ADDR_NO_RANDOMIZE | \ ++ ADDR_COMPAT_LAYOUT | \ ++ MMAP_PAGE_ZERO) + + /* + * Personality types. +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/include/linux/sched.h linux-2.6.27.29-0.1.1/include/linux/sched.h +--- linux-2.6.27.25-0.1.1/include/linux/sched.h 2009-08-05 09:50:05.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/include/linux/sched.h 2009-08-27 12:44:46.000000000 +0100 +@@ -203,7 +203,7 @@ extern unsigned long long time_sync_thre + ((task->state & (__TASK_STOPPED | __TASK_TRACED)) != 0) + #define task_contributes_to_load(task) \ + ((task->state & TASK_UNINTERRUPTIBLE) != 0 && \ +- (task->flags & PF_FROZEN) == 0) ++ (task->flags & PF_FREEZING) == 0) + + #define __set_task_state(tsk, state_value) \ + do { (tsk)->state = (state_value); } while (0) +@@ -1512,6 +1512,7 @@ extern cputime_t task_gtime(struct task_ + #define PF_MEMALLOC 0x00000800 /* Allocating memory */ + #define PF_FLUSHER 0x00001000 /* responsible for disk writeback */ + #define PF_USED_MATH 0x00002000 /* if unset the fpu must be initialized before use */ ++#define PF_FREEZING 0x00004000 /* freeze in progress. do not account to load */ + #define PF_NOFREEZE 0x00008000 /* this thread should not be frozen */ + #define PF_FROZEN 0x00010000 /* frozen for system suspend */ + #define PF_FSTRANS 0x00020000 /* inside a filesystem transaction */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/include/linux/security.h linux-2.6.27.29-0.1.1/include/linux/security.h +--- linux-2.6.27.25-0.1.1/include/linux/security.h 2009-08-05 09:43:34.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/include/linux/security.h 2009-08-27 12:44:46.000000000 +0100 +@@ -2214,6 +2214,8 @@ static inline int security_file_mmap(str + unsigned long addr, + unsigned long addr_only) + { ++ if ((addr < mmap_min_addr) && !capable(CAP_SYS_RAWIO)) ++ return -EACCES; + return 0; + } + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/include/linux/topology.h linux-2.6.27.29-0.1.1/include/linux/topology.h +--- linux-2.6.27.25-0.1.1/include/linux/topology.h 2009-08-05 09:43:34.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/include/linux/topology.h 2009-08-27 12:44:46.000000000 +0100 +@@ -99,7 +99,8 @@ int arch_update_cpu_topology(void); + | SD_BALANCE_FORK \ + | SD_BALANCE_EXEC \ + | SD_WAKE_AFFINE \ +- | SD_WAKE_IDLE, \ ++ | SD_WAKE_IDLE \ ++ | SD_SHARE_CPUPOWER, \ + .last_balance = jiffies, \ + .balance_interval = 1, \ + } +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/include/net/x25.h linux-2.6.27.29-0.1.1/include/net/x25.h +--- linux-2.6.27.25-0.1.1/include/net/x25.h 2009-08-05 09:43:31.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/include/net/x25.h 2009-08-27 12:44:42.000000000 +0100 +@@ -187,7 +187,7 @@ extern int x25_addr_ntoa(unsigned char + extern int x25_addr_aton(unsigned char *, struct x25_address *, + struct x25_address *); + extern struct sock *x25_find_socket(unsigned int, struct x25_neigh *); +-extern void x25_destroy_socket(struct sock *); ++extern void x25_destroy_socket_from_timer(struct sock *); + extern int x25_rx_call_request(struct sk_buff *, struct x25_neigh *, unsigned int); + extern void x25_kill_by_neigh(struct x25_neigh *); + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/kernel/acct.c linux-2.6.27.29-0.1.1/kernel/acct.c +--- linux-2.6.27.25-0.1.1/kernel/acct.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/kernel/acct.c 2009-08-27 12:44:31.000000000 +0100 +@@ -215,6 +215,7 @@ static void acct_file_reopen(struct bsd_ + static int acct_on(char *name) + { + struct file *file; ++ struct vfsmount *mnt; + int error; + struct pid_namespace *ns; + struct bsd_acct_struct *acct = NULL; +@@ -256,11 +257,12 @@ static int acct_on(char *name) + acct = NULL; + } + +- mnt_pin(file->f_path.mnt); ++ mnt = file->f_path.mnt; ++ mnt_pin(mnt); + acct_file_reopen(ns->bacct, file, ns); + spin_unlock(&acct_lock); + +- mntput(file->f_path.mnt); /* it's pinned, now give up active reference */ ++ mntput(mnt); /* it's pinned, now give up active reference */ + kfree(acct); + + return 0; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/kernel/freezer.c linux-2.6.27.29-0.1.1/kernel/freezer.c +--- linux-2.6.27.25-0.1.1/kernel/freezer.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/kernel/freezer.c 2009-08-27 12:44:31.000000000 +0100 +@@ -44,12 +44,19 @@ void refrigerator(void) + recalc_sigpending(); /* We sent fake signal, clean it up */ + spin_unlock_irq(¤t->sighand->siglock); + ++ /* prevent accounting of that task to load */ ++ current->flags |= PF_FREEZING; ++ + for (;;) { + set_current_state(TASK_UNINTERRUPTIBLE); + if (!frozen(current)) + break; + schedule(); + } ++ ++ /* Remove the accounting blocker */ ++ current->flags &= ~PF_FREEZING; ++ + pr_debug("%s left refrigerator\n", current->comm); + __set_current_state(save); + } +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/kernel/resource.c linux-2.6.27.29-0.1.1/kernel/resource.c +--- linux-2.6.27.25-0.1.1/kernel/resource.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/kernel/resource.c 2009-08-27 12:44:31.000000000 +0100 +@@ -741,7 +741,7 @@ static int __init reserve_setup(char *st + static struct resource reserve[MAXRESERVE]; + + for (;;) { +- int io_start, io_num; ++ unsigned int io_start, io_num; + int x = reserved; + + if (get_option (&str, &io_start) != 2) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/kernel/signal.c linux-2.6.27.29-0.1.1/kernel/signal.c +--- linux-2.6.27.25-0.1.1/kernel/signal.c 2009-08-05 09:49:55.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/kernel/signal.c 2009-08-27 12:44:31.000000000 +0100 +@@ -2356,11 +2356,9 @@ do_sigaltstack (const stack_t __user *us + stack_t oss; + int error; + +- if (uoss) { +- oss.ss_sp = (void __user *) current->sas_ss_sp; +- oss.ss_size = current->sas_ss_size; +- oss.ss_flags = sas_ss_flags(sp); +- } ++ oss.ss_sp = (void __user *) current->sas_ss_sp; ++ oss.ss_size = current->sas_ss_size; ++ oss.ss_flags = sas_ss_flags(sp); + + if (uss) { + void __user *ss_sp; +@@ -2403,13 +2401,16 @@ do_sigaltstack (const stack_t __user *us + current->sas_ss_size = ss_size; + } + ++ error = 0; + if (uoss) { + error = -EFAULT; +- if (copy_to_user(uoss, &oss, sizeof(oss))) ++ if (!access_ok(VERIFY_WRITE, uoss, sizeof(*uoss))) + goto out; ++ error = __put_user(oss.ss_sp, &uoss->ss_sp) | ++ __put_user(oss.ss_size, &uoss->ss_size) | ++ __put_user(oss.ss_flags, &uoss->ss_flags); + } + +- error = 0; + out: + return error; + } +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/kernel/sysctl.c linux-2.6.27.29-0.1.1/kernel/sysctl.c +--- linux-2.6.27.25-0.1.1/kernel/sysctl.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/kernel/sysctl.c 2009-08-27 12:44:31.000000000 +0100 +@@ -1172,7 +1172,6 @@ static struct ctl_table vm_table[] = { + .strategy = &sysctl_jiffies, + }, + #endif +-#ifdef CONFIG_SECURITY + { + .ctl_name = CTL_UNNUMBERED, + .procname = "mmap_min_addr", +@@ -1181,7 +1180,6 @@ static struct ctl_table vm_table[] = { + .mode = 0644, + .proc_handler = &proc_doulongvec_minmax, + }, +-#endif + #ifdef CONFIG_NUMA + { + .ctl_name = CTL_UNNUMBERED, +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/kernel/time/tick-sched.c linux-2.6.27.29-0.1.1/kernel/time/tick-sched.c +--- linux-2.6.27.25-0.1.1/kernel/time/tick-sched.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/kernel/time/tick-sched.c 2009-08-27 12:44:31.000000000 +0100 +@@ -377,7 +377,9 @@ void tick_nohz_restart_sched_tick(void) + { + int cpu = smp_processor_id(); + struct tick_sched *ts = &per_cpu(tick_cpu_sched, cpu); ++#ifndef CONFIG_VIRT_CPU_ACCOUNTING + unsigned long ticks; ++#endif + ktime_t now; + + local_irq_disable(); +@@ -399,6 +401,7 @@ void tick_nohz_restart_sched_tick(void) + tick_do_update_jiffies64(now); + cpu_clear(cpu, nohz_cpu_mask); + ++#ifndef CONFIG_VIRT_CPU_ACCOUNTING + /* + * We stopped the tick in idle. Update process times would miss the + * time we slept as update_process_times does only a 1 tick +@@ -414,6 +417,7 @@ void tick_nohz_restart_sched_tick(void) + jiffies_to_cputime(ticks)); + sub_preempt_count(HARDIRQ_OFFSET); + } ++#endif + + touch_softlockup_watchdog(); + /* +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/lib/Kconfig.debug linux-2.6.27.29-0.1.1/lib/Kconfig.debug +--- linux-2.6.27.25-0.1.1/lib/Kconfig.debug 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/lib/Kconfig.debug 2009-08-27 12:43:48.000000000 +0100 +@@ -394,7 +394,7 @@ config LOCKDEP + bool + depends on DEBUG_KERNEL && TRACE_IRQFLAGS_SUPPORT && STACKTRACE_SUPPORT && LOCKDEP_SUPPORT + select STACKTRACE +- select FRAME_POINTER if !X86 && !MIPS && !PPC ++ select FRAME_POINTER if !MIPS && !PPC + select KALLSYMS + select KALLSYMS_ALL + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/Makefile linux-2.6.27.29-0.1.1/Makefile +--- linux-2.6.27.25-0.1.1/Makefile 2009-08-27 12:59:59.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/Makefile 2009-08-27 12:45:00.000000000 +0100 +@@ -1,7 +1,7 @@ + VERSION = 2 + PATCHLEVEL = 6 + SUBLEVEL = 27 +-EXTRAVERSION = .25-0.1.1 ++EXTRAVERSION = .29-0.1.1 + NAME = Trembling Tortoise + + # *DOCUMENTATION* +@@ -355,8 +355,8 @@ KBUILD_CPPFLAGS := -D__KERNEL__ $(LINUXI + + KBUILD_CFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \ + -fno-strict-aliasing -fno-common \ +- -Werror-implicit-function-declaration +-KBUILD_CFLAGS += $(call cc-option,-fwrapv) ++ -Werror-implicit-function-declaration \ ++ -fno-delete-null-pointer-checks + KBUILD_AFLAGS := -D__ASSEMBLY__ + + # Warn about unsupported modules in kernels built inside Autobuild +@@ -583,7 +583,7 @@ KBUILD_CFLAGS += $(call cc-option,-Wdecl + KBUILD_CFLAGS += $(call cc-option,-Wno-pointer-sign,) + + # disable invalid "can't wrap" optimzations for signed / pointers +-KBUILD_CFLAGS += $(call cc-option,-fwrapv) ++KBUILD_CFLAGS += $(call cc-option,-fno-strict-overflow) + + # Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments + # But warn user when we do so +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/mm/filemap.c linux-2.6.27.29-0.1.1/mm/filemap.c +--- linux-2.6.27.25-0.1.1/mm/filemap.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/mm/filemap.c 2009-08-27 12:43:48.000000000 +0100 +@@ -2502,6 +2502,7 @@ again: + pagefault_enable(); + flush_dcache_page(page); + ++ mark_page_accessed(page); + status = a_ops->write_end(file, mapping, pos, bytes, copied, + page, fsdata); + if (unlikely(status < 0)) +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/mm/Kconfig linux-2.6.27.29-0.1.1/mm/Kconfig +--- linux-2.6.27.25-0.1.1/mm/Kconfig 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/mm/Kconfig 2009-08-27 12:43:48.000000000 +0100 +@@ -205,3 +205,21 @@ config VIRT_TO_BUS + + config MMU_NOTIFIER + bool ++ ++config DEFAULT_MMAP_MIN_ADDR ++ int "Low address space to protect from user allocation" ++ default 4096 ++ help ++ This is the portion of low virtual memory which should be protected ++ from userspace allocation. Keeping a user from writing to low pages ++ can help reduce the impact of kernel NULL pointer bugs. ++ ++ For most ia64, ppc64 and x86 users with lots of address space ++ a value of 65536 is reasonable and should cause no problems. ++ On arm and other archs it should not be higher than 32768. ++ Programs which use vm86 functionality would either need additional ++ permissions from either the LSM or the capabilities module or have ++ this protection disabled. ++ ++ This value can be changed after boot using the ++ /proc/sys/vm/mmap_min_addr tunable. +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/mm/mmap.c linux-2.6.27.29-0.1.1/mm/mmap.c +--- linux-2.6.27.25-0.1.1/mm/mmap.c 2009-08-27 12:58:49.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/mm/mmap.c 2009-08-27 12:43:48.000000000 +0100 +@@ -87,6 +87,9 @@ int sysctl_max_map_count __read_mostly = + struct percpu_counter vm_committed_as; + int heap_stack_gap __read_mostly = 1; + ++/* amount of vm to protect from userspace access */ ++unsigned long mmap_min_addr = CONFIG_DEFAULT_MMAP_MIN_ADDR; ++ + /* + * Check that a process has enough memory to allocate a new virtual + * mapping. 0 means there is enough memory for the allocation to +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/mm/page_alloc.c linux-2.6.27.29-0.1.1/mm/page_alloc.c +--- linux-2.6.27.25-0.1.1/mm/page_alloc.c 2009-08-05 09:49:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/mm/page_alloc.c 2009-08-27 12:43:48.000000000 +0100 +@@ -859,7 +859,7 @@ static struct page *__rmqueue(struct zon + */ + static int rmqueue_bulk(struct zone *zone, unsigned int order, + unsigned long count, struct list_head *list, +- int migratetype) ++ int migratetype, int cold) + { + int i; + +@@ -878,7 +878,10 @@ static int rmqueue_bulk(struct zone *zon + * merge IO requests if the physical pages are ordered + * properly. + */ +- list_add(&page->lru, list); ++ if (likely(cold == 0)) ++ list_add(&page->lru, list); ++ else ++ list_add_tail(&page->lru, list); + set_page_private(page, migratetype); + list = &page->lru; + } +@@ -1089,7 +1092,8 @@ again: + local_irq_save(flags); + if (!pcp->count) { + pcp->count = rmqueue_bulk(zone, 0, +- pcp->batch, &pcp->list, migratetype); ++ pcp->batch, &pcp->list, ++ migratetype, cold); + if (unlikely(!pcp->count)) + goto failed; + } +@@ -1108,7 +1112,8 @@ again: + /* Allocate more to the pcp list if necessary */ + if (unlikely(&page->lru == &pcp->list)) { + pcp->count += rmqueue_bulk(zone, 0, +- pcp->batch, &pcp->list, migratetype); ++ pcp->batch, &pcp->list, ++ migratetype, cold); + page = list_entry(pcp->list.next, struct page, lru); + } + +@@ -2815,7 +2820,7 @@ bad: + if (dzone == zone) + break; + kfree(zone_pcp(dzone, cpu)); +- zone_pcp(dzone, cpu) = NULL; ++ zone_pcp(dzone, cpu) = &boot_pageset[cpu]; + } + return -ENOMEM; + } +@@ -2830,7 +2835,7 @@ static inline void free_zone_pagesets(in + /* Free per_cpu_pageset if it is slab allocated */ + if (pset != &boot_pageset[cpu]) + kfree(pset); +- zone_pcp(zone, cpu) = NULL; ++ zone_pcp(zone, cpu) = &boot_pageset[cpu]; + } + } + +@@ -4531,6 +4536,8 @@ int percpu_pagelist_fraction_sysctl_hand + if (!write || (ret == -EINVAL)) + return ret; + for_each_zone(zone) { ++ if (!populated_zone(zone)) ++ continue; + for_each_online_cpu(cpu) { + unsigned long high; + high = zone->present_pages / percpu_pagelist_fraction; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/mm/slab.c linux-2.6.27.29-0.1.1/mm/slab.c +--- linux-2.6.27.25-0.1.1/mm/slab.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/mm/slab.c 2009-08-27 12:43:48.000000000 +0100 +@@ -2608,7 +2608,7 @@ void kmem_cache_destroy(struct kmem_cach + } + + if (unlikely(cachep->flags & SLAB_DESTROY_BY_RCU)) +- synchronize_rcu(); ++ rcu_barrier(); + + __kmem_cache_destroy(cachep); + mutex_unlock(&cache_chain_mutex); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/mm/slob.c linux-2.6.27.29-0.1.1/mm/slob.c +--- linux-2.6.27.25-0.1.1/mm/slob.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/mm/slob.c 2009-08-27 12:43:48.000000000 +0100 +@@ -575,6 +575,8 @@ EXPORT_SYMBOL(kmem_cache_create); + + void kmem_cache_destroy(struct kmem_cache *c) + { ++ if (c->flags & SLAB_DESTROY_BY_RCU) ++ rcu_barrier(); + slob_free(c, sizeof(struct kmem_cache)); + } + EXPORT_SYMBOL(kmem_cache_destroy); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/mm/slub.c linux-2.6.27.29-0.1.1/mm/slub.c +--- linux-2.6.27.25-0.1.1/mm/slub.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/mm/slub.c 2009-08-27 12:43:48.000000000 +0100 +@@ -2511,6 +2511,8 @@ static inline int kmem_cache_close(struc + */ + void kmem_cache_destroy(struct kmem_cache *s) + { ++ if (s->flags & SLAB_DESTROY_BY_RCU) ++ rcu_barrier(); + down_write(&slub_lock); + s->refcount--; + if (!s->refcount) { +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/mm/vmalloc.c linux-2.6.27.29-0.1.1/mm/vmalloc.c +--- linux-2.6.27.25-0.1.1/mm/vmalloc.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/mm/vmalloc.c 2009-08-27 12:43:48.000000000 +0100 +@@ -279,8 +279,11 @@ found: + out: + write_unlock(&vmlist_lock); + kfree(area); +- if (printk_ratelimit()) ++ if (printk_ratelimit()) { + printk(KERN_WARNING "allocation failed: out of vmalloc space - use vmalloc= to increase size.\n"); ++ printk(KERN_WARNING "vmalloc size=%lx flags=%lx start=%lx end=%lx node=%d gfp=%lx\n", size, flags, start, end, node, (unsigned long)gfp_mask); ++ dump_stack(); ++ } + return NULL; + } + +@@ -604,7 +607,7 @@ void *vmalloc_user(unsigned long size) + struct vm_struct *area; + void *ret; + +- ret = __vmalloc(size, GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO, PAGE_KERNEL); ++ ret = __vmalloc_node(size, GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO, PAGE_KERNEL, -1, __builtin_return_address(0)); + if (ret) { + write_lock(&vmlist_lock); + area = __find_vm_area(ret); +@@ -651,7 +654,7 @@ EXPORT_SYMBOL(vmalloc_node); + + void *vmalloc_exec(unsigned long size) + { +- return __vmalloc(size, GFP_KERNEL | __GFP_HIGHMEM, PAGE_KERNEL_EXEC); ++ return __vmalloc_node(size, GFP_KERNEL | __GFP_HIGHMEM, PAGE_KERNEL_EXEC, -1, __builtin_return_address(0)); + } + + #if defined(CONFIG_64BIT) && defined(CONFIG_ZONE_DMA32) +@@ -671,7 +674,7 @@ void *vmalloc_exec(unsigned long size) + */ + void *vmalloc_32(unsigned long size) + { +- return __vmalloc(size, GFP_VMALLOC32, PAGE_KERNEL); ++ return __vmalloc_node(size, GFP_VMALLOC32, PAGE_KERNEL, -1, __builtin_return_address(0)); + } + EXPORT_SYMBOL(vmalloc_32); + +@@ -687,7 +690,7 @@ void *vmalloc_32_user(unsigned long size + struct vm_struct *area; + void *ret; + +- ret = __vmalloc(size, GFP_VMALLOC32 | __GFP_ZERO, PAGE_KERNEL); ++ ret = __vmalloc_node(size, GFP_VMALLOC32 | __GFP_ZERO, PAGE_KERNEL, -1, __builtin_return_address(0)); + if (ret) { + write_lock(&vmlist_lock); + area = __find_vm_area(ret); +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/net/ipv4/tcp_ipv4.c linux-2.6.27.29-0.1.1/net/ipv4/tcp_ipv4.c +--- linux-2.6.27.25-0.1.1/net/ipv4/tcp_ipv4.c 2009-08-05 09:42:26.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/net/ipv4/tcp_ipv4.c 2009-08-27 12:43:48.000000000 +0100 +@@ -1364,6 +1364,10 @@ struct sock *tcp_v4_syn_recv_sock(struct + tcp_mtup_init(newsk); + tcp_sync_mss(newsk, dst_mtu(dst)); + newtp->advmss = dst_metric(dst, RTAX_ADVMSS); ++ if (tcp_sk(sk)->rx_opt.user_mss && ++ tcp_sk(sk)->rx_opt.user_mss < newtp->advmss) ++ newtp->advmss = tcp_sk(sk)->rx_opt.user_mss; ++ + tcp_initialize_rcv_mss(newsk); + + #ifdef CONFIG_TCP_MD5SIG +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/net/ipv4/tcp_output.c linux-2.6.27.29-0.1.1/net/ipv4/tcp_output.c +--- linux-2.6.27.25-0.1.1/net/ipv4/tcp_output.c 2009-08-05 09:42:26.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/net/ipv4/tcp_output.c 2009-08-27 12:43:53.000000000 +0100 +@@ -2253,6 +2253,7 @@ struct sk_buff *tcp_make_synack(struct s + struct sk_buff *skb; + struct tcp_md5sig_key *md5; + __u8 *md5_hash_location; ++ int mss; + + skb = sock_wmalloc(sk, MAX_TCP_HEADER + 15, 1, + sk_allocation(sk, GFP_ATOMIC)); +@@ -2264,13 +2265,17 @@ struct sk_buff *tcp_make_synack(struct s + + skb->dst = dst_clone(dst); + ++ mss = dst_metric(dst, RTAX_ADVMSS); ++ if (tp->rx_opt.user_mss && tp->rx_opt.user_mss < mss) ++ mss = tp->rx_opt.user_mss; ++ + if (req->rcv_wnd == 0) { /* ignored for retransmitted syns */ + __u8 rcv_wscale; + /* Set this up on the first call only */ + req->window_clamp = tp->window_clamp ? : dst_metric(dst, RTAX_WINDOW); + /* tcp_full_space because it is guaranteed to be the first packet */ + tcp_select_initial_window(tcp_full_space(sk), +- dst_metric(dst, RTAX_ADVMSS) - (ireq->tstamp_ok ? TCPOLEN_TSTAMP_ALIGNED : 0), ++ mss - (ireq->tstamp_ok ? TCPOLEN_TSTAMP_ALIGNED : 0), + &req->rcv_wnd, + &req->window_clamp, + ireq->wscale_ok, +@@ -2285,8 +2290,7 @@ struct sk_buff *tcp_make_synack(struct s + else + #endif + TCP_SKB_CB(skb)->when = tcp_time_stamp; +- tcp_header_size = tcp_synack_options(sk, req, +- dst_metric(dst, RTAX_ADVMSS), ++ tcp_header_size = tcp_synack_options(sk, req, mss, + skb, &opts, &md5) + + sizeof(struct tcphdr); + +@@ -2355,6 +2359,9 @@ static void tcp_connect_init(struct sock + if (!tp->window_clamp) + tp->window_clamp = dst_metric(dst, RTAX_WINDOW); + tp->advmss = dst_metric(dst, RTAX_ADVMSS); ++ if (tp->rx_opt.user_mss && tp->rx_opt.user_mss < tp->advmss) ++ tp->advmss = tp->rx_opt.user_mss; ++ + tcp_initialize_rcv_mss(sk); + + tcp_select_initial_window(tcp_full_space(sk), +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/net/socket.c linux-2.6.27.29-0.1.1/net/socket.c +--- linux-2.6.27.25-0.1.1/net/socket.c 2009-08-05 09:42:26.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/net/socket.c 2009-08-27 12:43:53.000000000 +0100 +@@ -699,7 +699,7 @@ static ssize_t sock_sendpage(struct file + if (more) + flags |= MSG_MORE; + +- return sock->ops->sendpage(sock, page, offset, size, flags); ++ return kernel_sendpage(sock, page, offset, size, flags); + } + + static ssize_t sock_splice_read(struct file *file, loff_t *ppos, +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/net/sunrpc/clnt.c linux-2.6.27.29-0.1.1/net/sunrpc/clnt.c +--- linux-2.6.27.25-0.1.1/net/sunrpc/clnt.c 2009-08-05 09:42:26.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/net/sunrpc/clnt.c 2009-08-27 12:43:53.000000000 +0100 +@@ -1089,14 +1089,24 @@ static void + call_transmit_status(struct rpc_task *task) + { + task->tk_action = call_status; +- /* +- * Special case: if we've been waiting on the socket's write_space() +- * callback, then don't call xprt_end_transmit(). +- */ +- if (task->tk_status == -EAGAIN) +- return; +- xprt_end_transmit(task); +- rpc_task_force_reencode(task); ++ switch (task->tk_status) { ++ case -EAGAIN: ++ break; ++ default: ++ xprt_end_transmit(task); ++ /* ++ * Special cases: if we've been waiting on the ++ * socket's write_space() callback, or if the ++ * socket just returned a connection error, ++ * then hold onto the transport lock. ++ */ ++ case -ECONNREFUSED: ++ case -ENOTCONN: ++ case -EHOSTDOWN: ++ case -EHOSTUNREACH: ++ case -ENETUNREACH: ++ rpc_task_force_reencode(task); ++ } + } + + /* +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/net/sunrpc/xprtsock.c linux-2.6.27.29-0.1.1/net/sunrpc/xprtsock.c +--- linux-2.6.27.25-0.1.1/net/sunrpc/xprtsock.c 2009-08-05 09:49:07.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/net/sunrpc/xprtsock.c 2009-08-27 12:43:53.000000000 +0100 +@@ -1158,7 +1158,6 @@ static void xs_tcp_state_change(struct s + break; + case TCP_CLOSE_WAIT: + /* The server initiated a shutdown of the socket */ +- set_bit(XPRT_CLOSING, &xprt->state); + xprt_force_disconnect(xprt); + case TCP_SYN_SENT: + xprt->connect_cookie++; +@@ -1171,6 +1170,7 @@ static void xs_tcp_state_change(struct s + xprt->reestablish_timeout = XS_TCP_INIT_REEST_TO; + break; + case TCP_LAST_ACK: ++ set_bit(XPRT_CLOSING, &xprt->state); + smp_mb__before_clear_bit(); + clear_bit(XPRT_CONNECTED, &xprt->state); + smp_mb__after_clear_bit(); +@@ -1629,10 +1629,9 @@ out: + * We need to preserve the port number so the reply cache on the server can + * find our cached RPC replies when we get around to reconnecting. + */ +-static void xs_tcp_reuse_connection(struct rpc_xprt *xprt) ++static void xs_abort_connection(struct rpc_xprt *xprt, struct sock_xprt *transport) + { + int result; +- struct sock_xprt *transport = container_of(xprt, struct sock_xprt, xprt); + struct sockaddr any; + + dprintk("RPC: disconnecting xprt %p to reuse port\n", xprt); +@@ -1649,6 +1648,17 @@ static void xs_tcp_reuse_connection(stru + result); + } + ++static void xs_tcp_reuse_connection(struct rpc_xprt *xprt, struct sock_xprt *transport) ++{ ++ unsigned int state = transport->inet->sk_state; ++ ++ if (state == TCP_CLOSE && transport->sock->state == SS_UNCONNECTED) ++ return; ++ if ((1 << state) & (TCPF_ESTABLISHED|TCPF_SYN_SENT)) ++ return; ++ xs_abort_connection(xprt, transport); ++} ++ + static int xs_tcp_finish_connecting(struct rpc_xprt *xprt, struct socket *sock) + { + struct sock_xprt *transport = container_of(xprt, struct sock_xprt, xprt); +@@ -1725,7 +1735,7 @@ static void xs_tcp_connect_worker4(struc + } + } else + /* "close" the socket, preserving the local port */ +- xs_tcp_reuse_connection(xprt); ++ xs_tcp_reuse_connection(xprt, transport); + + dprintk("RPC: worker connecting xprt %p to address: %s\n", + xprt, xprt->address_strings[RPC_DISPLAY_ALL]); +@@ -1790,7 +1800,7 @@ static void xs_tcp_connect_worker6(struc + } + } else + /* "close" the socket, preserving the local port */ +- xs_tcp_reuse_connection(xprt); ++ xs_tcp_reuse_connection(xprt, transport); + + dprintk("RPC: worker connecting xprt %p to address: %s\n", + xprt, xprt->address_strings[RPC_DISPLAY_ALL]); +@@ -1861,9 +1871,6 @@ static void xs_tcp_connect(struct rpc_ta + { + struct rpc_xprt *xprt = task->tk_xprt; + +- /* Initiate graceful shutdown of the socket if not already done */ +- if (test_bit(XPRT_CONNECTED, &xprt->state)) +- xs_tcp_shutdown(xprt); + /* Exit if we need to wait for socket shutdown to complete */ + if (test_bit(XPRT_CLOSING, &xprt->state)) + return; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/net/x25/af_x25.c linux-2.6.27.29-0.1.1/net/x25/af_x25.c +--- linux-2.6.27.25-0.1.1/net/x25/af_x25.c 2009-08-05 09:49:02.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/net/x25/af_x25.c 2009-08-27 12:43:48.000000000 +0100 +@@ -332,14 +332,14 @@ static unsigned int x25_new_lci(struct x + /* + * Deferred destroy. + */ +-void x25_destroy_socket(struct sock *); ++static void __x25_destroy_socket(struct sock *); + + /* + * handler for deferred kills. + */ + static void x25_destroy_timer(unsigned long data) + { +- x25_destroy_socket((struct sock *)data); ++ x25_destroy_socket_from_timer((struct sock *)data); + } + + /* +@@ -349,12 +349,10 @@ static void x25_destroy_timer(unsigned l + * will touch it and we are (fairly 8-) ) safe. + * Not static as it's used by the timer + */ +-void x25_destroy_socket(struct sock *sk) ++static void __x25_destroy_socket(struct sock *sk) + { + struct sk_buff *skb; + +- sock_hold(sk); +- lock_sock(sk); + x25_stop_heartbeat(sk); + x25_stop_timer(sk); + +@@ -385,7 +383,22 @@ void x25_destroy_socket(struct sock *sk) + /* drop last reference so sock_put will free */ + __sock_put(sk); + } ++} + ++void x25_destroy_socket_from_timer(struct sock *sk) ++{ ++ sock_hold(sk); ++ bh_lock_sock(sk); ++ __x25_destroy_socket(sk); ++ bh_unlock_sock(sk); ++ sock_put(sk); ++} ++ ++static void x25_destroy_socket(struct sock *sk) ++{ ++ sock_hold(sk); ++ lock_sock(sk); ++ __x25_destroy_socket(sk); + release_sock(sk); + sock_put(sk); + } +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/net/x25/x25_timer.c linux-2.6.27.29-0.1.1/net/x25/x25_timer.c +--- linux-2.6.27.25-0.1.1/net/x25/x25_timer.c 2009-08-05 09:42:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/net/x25/x25_timer.c 2009-08-27 12:43:48.000000000 +0100 +@@ -113,7 +113,7 @@ static void x25_heartbeat_expiry(unsigne + (sk->sk_state == TCP_LISTEN && + sock_flag(sk, SOCK_DEAD))) { + bh_unlock_sock(sk); +- x25_destroy_socket(sk); ++ x25_destroy_socket_from_timer(sk); + return; + } + break; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/net/xfrm/xfrm_algo.c linux-2.6.27.29-0.1.1/net/xfrm/xfrm_algo.c +--- linux-2.6.27.25-0.1.1/net/xfrm/xfrm_algo.c 2009-08-05 09:42:26.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/net/xfrm/xfrm_algo.c 2009-08-27 12:43:53.000000000 +0100 +@@ -292,8 +292,8 @@ static struct xfrm_algo_desc ealg_list[] + } + }, + { +- .name = "cbc(cast128)", +- .compat = "cast128", ++ .name = "cbc(cast5)", ++ .compat = "cast5", + + .uinfo = { + .encr = { +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/scripts/Makefile.build linux-2.6.27.29-0.1.1/scripts/Makefile.build +--- linux-2.6.27.25-0.1.1/scripts/Makefile.build 2009-08-05 09:42:57.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/scripts/Makefile.build 2009-08-27 12:44:15.000000000 +0100 +@@ -74,7 +74,8 @@ $(warning kbuild: Makefile.build is incl + endif + + ifeq ($(CONFIG_XEN),y) +-$(objtree)/scripts/Makefile.xen: $(srctree)/scripts/Makefile.xen.awk $(srctree)/scripts/Makefile.build ++Makefile.xen := $(if $(KBUILD_EXTMOD),$(KBUILD_EXTMOD),$(objtree)/scripts)/Makefile.xen ++$(Makefile.xen): $(srctree)/scripts/Makefile.xen.awk $(srctree)/scripts/Makefile.build + @echo ' Updating $@' + $(if $(shell echo a | $(AWK) '{ print gensub(/a/, "AA", "g"); }'),\ + ,$(error 'Your awk program does not define gensub. Use gawk or another awk with gensub')) +@@ -84,7 +85,7 @@ xen-src-single-used-m := $(patsubst $(sr + xen-single-used-m := $(xen-src-single-used-m:-xen.c=.o) + single-used-m := $(filter-out $(xen-single-used-m),$(single-used-m)) + +--include $(objtree)/scripts/Makefile.xen ++-include $(Makefile.xen) + endif + + # =========================================================================== +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/scripts/unifdef.c linux-2.6.27.29-0.1.1/scripts/unifdef.c +--- linux-2.6.27.25-0.1.1/scripts/unifdef.c 2009-08-05 09:42:57.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/scripts/unifdef.c 2009-08-27 12:44:15.000000000 +0100 +@@ -206,7 +206,7 @@ static void done(void); + static void error(const char *); + static int findsym(const char *); + static void flushline(bool); +-static Linetype getline(void); ++static Linetype get_line(void); + static Linetype ifeval(const char **); + static void ignoreoff(void); + static void ignoreon(void); +@@ -512,7 +512,7 @@ process(void) + + for (;;) { + linenum++; +- lineval = getline(); ++ lineval = get_line(); + trans_table[ifstate[depth]][lineval](); + debug("process %s -> %s depth %d", + linetype_name[lineval], +@@ -526,7 +526,7 @@ process(void) + * help from skipcomment(). + */ + static Linetype +-getline(void) ++get_line(void) + { + const char *cp; + int cursym; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/security/Kconfig linux-2.6.27.29-0.1.1/security/Kconfig +--- linux-2.6.27.25-0.1.1/security/Kconfig 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/security/Kconfig 2009-08-27 12:44:31.000000000 +0100 +@@ -101,28 +101,8 @@ config SECURITY_ROOTPLUG + + See for + more information about this module. +- +- If you are unsure how to answer this question, answer N. +- +-config SECURITY_DEFAULT_MMAP_MIN_ADDR +- int "Low address space to protect from user allocation" +- depends on SECURITY +- default 0 +- help +- This is the portion of low virtual memory which should be protected +- from userspace allocation. Keeping a user from writing to low pages +- can help reduce the impact of kernel NULL pointer bugs. +- +- For most ia64, ppc64 and x86 users with lots of address space +- a value of 65536 is reasonable and should cause no problems. +- On arm and other archs it should not be higher than 32768. +- Programs which use vm86 functionality would either need additional +- permissions from either the LSM or the capabilities module or have +- this protection disabled. +- +- This value can be changed after boot using the +- /proc/sys/vm/mmap_min_addr tunable. + ++ If you are unsure how to answer this question, answer N. + + source security/selinux/Kconfig + source security/smack/Kconfig +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/security/security.c linux-2.6.27.29-0.1.1/security/security.c +--- linux-2.6.27.25-0.1.1/security/security.c 2009-08-05 09:43:21.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/security/security.c 2009-08-27 12:44:31.000000000 +0100 +@@ -26,9 +26,6 @@ extern void security_fixup_ops(struct se + + struct security_operations *security_ops; /* Initialized to NULL */ + +-/* amount of vm to protect from userspace access */ +-unsigned long mmap_min_addr = CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR; +- + static inline int verify(struct security_operations *ops) + { + /* verify the security_operations structure exists */ +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/sound/core/seq/seq_midi_event.c linux-2.6.27.29-0.1.1/sound/core/seq/seq_midi_event.c +--- linux-2.6.27.25-0.1.1/sound/core/seq/seq_midi_event.c 2009-08-05 09:42:57.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/sound/core/seq/seq_midi_event.c 2009-08-27 12:44:15.000000000 +0100 +@@ -504,10 +504,10 @@ static int extra_decode_xrpn(struct snd_ + if (dev->nostat && count < 12) + return -ENOMEM; + cmd = MIDI_CMD_CONTROL|(ev->data.control.channel & 0x0f); +- bytes[0] = ev->data.control.param & 0x007f; +- bytes[1] = (ev->data.control.param & 0x3f80) >> 7; +- bytes[2] = ev->data.control.value & 0x007f; +- bytes[3] = (ev->data.control.value & 0x3f80) >> 7; ++ bytes[0] = (ev->data.control.param & 0x3f80) >> 7; ++ bytes[1] = ev->data.control.param & 0x007f; ++ bytes[2] = (ev->data.control.value & 0x3f80) >> 7; ++ bytes[3] = ev->data.control.value & 0x007f; + if (cmd != dev->lastcmd && !dev->nostat) { + if (count < 9) + return -ENOMEM; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/sound/pci/ca0106/ca0106_main.c linux-2.6.27.29-0.1.1/sound/pci/ca0106/ca0106_main.c +--- linux-2.6.27.25-0.1.1/sound/pci/ca0106/ca0106_main.c 2009-08-05 09:42:57.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/sound/pci/ca0106/ca0106_main.c 2009-08-27 12:44:15.000000000 +0100 +@@ -317,9 +317,9 @@ static struct snd_pcm_hardware snd_ca010 + .rate_max = 192000, + .channels_min = 2, + .channels_max = 2, +- .buffer_bytes_max = ((65536 - 64) * 8), ++ .buffer_bytes_max = 65536 - 128, + .period_bytes_min = 64, +- .period_bytes_max = (65536 - 64), ++ .period_bytes_max = 32768 - 64, + .periods_min = 2, + .periods_max = 2, + .fifo_size = 0, +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/sound/pci/ca0106/ca0106_mixer.c linux-2.6.27.29-0.1.1/sound/pci/ca0106/ca0106_mixer.c +--- linux-2.6.27.25-0.1.1/sound/pci/ca0106/ca0106_mixer.c 2009-08-05 09:42:57.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/sound/pci/ca0106/ca0106_mixer.c 2009-08-27 12:44:15.000000000 +0100 +@@ -792,6 +792,9 @@ int __devinit snd_ca0106_mixer(struct sn + snd_ca0106_master_db_scale); + if (!vmaster) + return -ENOMEM; ++ err = snd_ctl_add(card, vmaster); ++ if (err < 0) ++ return err; + add_slaves(card, vmaster, slave_vols); + + if (emu->details->spi_dac == 1) { +@@ -799,6 +802,9 @@ int __devinit snd_ca0106_mixer(struct sn + NULL); + if (!vmaster) + return -ENOMEM; ++ err = snd_ctl_add(card, vmaster); ++ if (err < 0) ++ return err; + add_slaves(card, vmaster, slave_sws); + } + return 0; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/sound/pci/hda/hda_codec.c linux-2.6.27.29-0.1.1/sound/pci/hda/hda_codec.c +--- linux-2.6.27.25-0.1.1/sound/pci/hda/hda_codec.c 2009-08-27 12:59:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/sound/pci/hda/hda_codec.c 2009-08-27 12:44:15.000000000 +0100 +@@ -1979,9 +1979,14 @@ static void hda_set_power_state(struct h + hda_nid_t nid; + int i; + +- snd_hda_codec_write(codec, fg, 0, AC_VERB_SET_POWER_STATE, ++ /* this delay seems necessary to avoid click noise at power-down */ ++ if (power_state == AC_PWRST_D3) ++ msleep(100); ++ snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, + power_state); +- msleep(10); /* partial workaround for "azx_get_response timeout" */ ++ /* partial workaround for "azx_get_response timeout" */ ++ if (power_state == AC_PWRST_D0) ++ msleep(10); + + nid = codec->start_nid; + for (i = 0; i < codec->num_nodes; i++, nid++) { +@@ -3361,6 +3366,43 @@ int snd_hda_codecs_inuse(struct hda_bus + #endif + + /* ++ * generic arrays ++ */ ++ ++/* get a new element from the given array ++ * if it exceeds the pre-allocated array size, re-allocate the array ++ */ ++void *snd_array_new(struct snd_array *array) ++{ ++ if (array->used >= array->alloced) { ++ int num = array->alloced + array->alloc_align; ++ void *nlist; ++ if (num >= 4096) ++ return NULL; ++ nlist = kcalloc(num + 1, array->elem_size, GFP_KERNEL); ++ if (!nlist) ++ return NULL; ++ if (array->list) { ++ memcpy(nlist, array->list, ++ array->elem_size * array->alloced); ++ kfree(array->list); ++ } ++ array->list = nlist; ++ array->alloced = num; ++ } ++ return snd_array_elem(array, array->used++); ++} ++ ++/* free the given array elements */ ++void snd_array_free(struct snd_array *array) ++{ ++ kfree(array->list); ++ array->used = 0; ++ array->alloced = 0; ++ array->list = NULL; ++} ++ ++/* + * used by hda_proc.c and hda_eld.c + */ + void snd_print_pcm_rates(int pcm, char *buf, int buflen) +@@ -3390,3 +3432,18 @@ void snd_print_pcm_bits(int pcm, char *b + buf[j] = '\0'; /* necessary when j == 0 */ + } + ++/* backported */ ++const struct snd_pci_quirk * ++snd_hda_quirk_lookup(struct pci_dev *pci, const struct snd_pci_quirk *list) ++{ ++ const struct snd_pci_quirk *q; ++ ++ for (q = list; q->subvendor; q++) { ++ if (q->subvendor != pci->subsystem_vendor) ++ continue; ++ if (!q->subdevice || ++ (pci->subsystem_device & q->subdevice_mask) == q->subdevice) ++ return q; ++ } ++ return NULL; ++} +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/sound/pci/hda/hda_codec.h linux-2.6.27.29-0.1.1/sound/pci/hda/hda_codec.h +--- linux-2.6.27.25-0.1.1/sound/pci/hda/hda_codec.h 2009-08-27 12:59:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/sound/pci/hda/hda_codec.h 2009-08-27 12:44:15.000000000 +0100 +@@ -26,6 +26,57 @@ + #include + #include + ++ ++/* ++ * quirk with mask; backported ++ */ ++ ++/* PCI quirk list helper */ ++struct snd_hda_quirk { ++ unsigned short subvendor; /* PCI subvendor ID */ ++ unsigned short subdevice; /* PCI subdevice ID */ ++ unsigned short subdevice_mask; /* bitmask to match */ ++ int value; /* value */ ++#ifdef CONFIG_SND_DEBUG_VERBOSE ++ const char *name; /* name of the device (optional) */ ++#endif ++}; ++ ++#define snd_pci_quirk snd_hda_quirk ++#undef _SND_PCI_QUIRK_ID_MASK ++#undef _SND_PCI_QUIRK_ID ++#undef SND_PCI_QUIRK_ID ++#undef SND_PCI_QUIRK ++#undef SND_PCI_QUIRK_MASK ++#undef SND_PCI_QUIRK_VENDOR ++ ++#define _SND_PCI_QUIRK_ID_MASK(vend, mask, dev) \ ++ .subvendor = (vend), .subdevice = (dev), .subdevice_mask = (mask) ++#define _SND_PCI_QUIRK_ID(vend, dev) \ ++ _SND_PCI_QUIRK_ID_MASK(vend, 0xffff, dev) ++#define SND_PCI_QUIRK_ID(vend,dev) {_SND_PCI_QUIRK_ID(vend, dev)} ++#ifdef CONFIG_SND_DEBUG_VERBOSE ++#define SND_PCI_QUIRK(vend,dev,xname,val) \ ++ {_SND_PCI_QUIRK_ID(vend, dev), .value = (val), .name = (xname)} ++#define SND_PCI_QUIRK_VENDOR(vend, xname, val) \ ++ {_SND_PCI_QUIRK_ID_MASK(vend, 0, 0), .value = (val), .name = (xname)} ++#define SND_PCI_QUIRK_MASK(vend, mask, dev, xname, val) \ ++ {_SND_PCI_QUIRK_ID_MASK(vend, mask, dev), \ ++ .value = (val), .name = (xname)} ++#else ++#define SND_PCI_QUIRK(vend,dev,xname,val) \ ++ {_SND_PCI_QUIRK_ID(vend, dev), .value = (val)} ++#define SND_PCI_QUIRK_MASK(vend, mask, dev, xname, val) \ ++ {_SND_PCI_QUIRK_ID_MASK(vend, mask, dev), .value = (val)} ++#define SND_PCI_QUIRK_VENDOR(vend, xname, val) \ ++ {_SND_PCI_QUIRK_ID_MASK(vend, 0, 0), .value = (val)} ++#endif ++ ++const struct snd_pci_quirk * ++snd_hda_quirk_lookup(struct pci_dev *pci, const struct snd_pci_quirk *list); ++ ++#define snd_pci_quirk_lookup snd_hda_quirk_lookup ++ + #if defined(CONFIG_PM) || defined(CONFIG_SND_HDA_POWER_SAVE) + #define SND_HDA_NEEDS_RESUME /* resume control code is required */ + #endif +@@ -520,6 +571,36 @@ enum { + #define HDA_MAX_CODEC_ADDRESS 0x0f + + /* ++ * generic arrays ++ */ ++struct snd_array { ++ unsigned int used; ++ unsigned int alloced; ++ unsigned int elem_size; ++ unsigned int alloc_align; ++ void *list; ++}; ++ ++void *snd_array_new(struct snd_array *array); ++void snd_array_free(struct snd_array *array); ++static inline void snd_array_init(struct snd_array *array, unsigned int size, ++ unsigned int align) ++{ ++ array->elem_size = size; ++ array->alloc_align = align; ++} ++ ++static inline void *snd_array_elem(struct snd_array *array, unsigned int idx) ++{ ++ return array->list + idx * array->elem_size; ++} ++ ++static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) ++{ ++ return (unsigned long)(ptr - array->list) / array->elem_size; ++} ++ ++/* + * Structures + */ + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/sound/pci/hda/patch_analog.c linux-2.6.27.29-0.1.1/sound/pci/hda/patch_analog.c +--- linux-2.6.27.25-0.1.1/sound/pci/hda/patch_analog.c 2009-08-05 09:49:33.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/sound/pci/hda/patch_analog.c 2009-08-27 12:44:15.000000000 +0100 +@@ -3713,9 +3713,30 @@ static struct snd_kcontrol_new ad1884a_l + { } /* end */ + }; + ++static int ad1884a_mobile_master_sw_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct hda_codec *codec = snd_kcontrol_chip(kcontrol); ++ int ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); ++ int mute = (!ucontrol->value.integer.value[0] && ++ !ucontrol->value.integer.value[1]); ++ /* toggle GPIO1 according to the mute state */ ++ snd_hda_codec_write_cache(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, ++ mute ? 0x02 : 0x0); ++ return ret; ++} ++ + static struct snd_kcontrol_new ad1884a_mobile_mixers[] = { + HDA_CODEC_VOLUME("Master Playback Volume", 0x21, 0x0, HDA_OUTPUT), +- HDA_CODEC_MUTE("Master Playback Switch", 0x21, 0x0, HDA_OUTPUT), ++ /*HDA_CODEC_MUTE("Master Playback Switch", 0x21, 0x0, HDA_OUTPUT),*/ ++ { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "Master Playback Switch", ++ .info = snd_hda_mixer_amp_switch_info, ++ .get = snd_hda_mixer_amp_switch_get, ++ .put = ad1884a_mobile_master_sw_put, ++ .private_value = HDA_COMPOSE_AMP_VAL(0x21, 3, 0, HDA_OUTPUT), ++ }, + HDA_CODEC_VOLUME("PCM Playback Volume", 0x20, 0x5, HDA_INPUT), + HDA_CODEC_MUTE("PCM Playback Switch", 0x20, 0x5, HDA_INPUT), + HDA_CODEC_VOLUME("Beep Playback Volume", 0x20, 0x03, HDA_INPUT), +@@ -3838,6 +3859,10 @@ static struct hda_verb ad1884a_mobile_ve + /* unsolicited event for pin-sense */ + {0x11, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | AD1884A_HP_EVENT}, + {0x14, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | AD1884A_MIC_EVENT}, ++ /* allow to touch GPIO1 (for mute control) */ ++ {0x01, AC_VERB_SET_GPIO_MASK, 0x02}, ++ {0x01, AC_VERB_SET_GPIO_DIRECTION, 0x02}, ++ {0x01, AC_VERB_SET_GPIO_DATA, 0x02}, /* first muted */ + { } /* end */ + }; + +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/sound/pci/hda/patch_realtek.c linux-2.6.27.29-0.1.1/sound/pci/hda/patch_realtek.c +--- linux-2.6.27.25-0.1.1/sound/pci/hda/patch_realtek.c 2009-08-27 12:59:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/sound/pci/hda/patch_realtek.c 2009-08-27 12:44:15.000000000 +0100 +@@ -9818,6 +9818,18 @@ static void alc262_lenovo_3000_unsol_eve + alc262_lenovo_3000_automute(codec, 1); + } + ++static int amp_stereo_mute_update(struct hda_codec *codec, hda_nid_t nid, ++ int dir, int idx, long *valp) ++{ ++ int i, change = 0; ++ ++ for (i = 0; i < 2; i++, valp++) ++ change |= snd_hda_codec_amp_update(codec, nid, i, dir, idx, ++ HDA_AMP_MUTE, ++ *valp ? 0 : HDA_AMP_MUTE); ++ return change; ++} ++ + /* bind hp and internal speaker mute (with plug check) */ + static int alc262_fujitsu_master_sw_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +@@ -9826,13 +9838,8 @@ static int alc262_fujitsu_master_sw_put( + long *valp = ucontrol->value.integer.value; + int change; + +- change = snd_hda_codec_amp_stereo(codec, 0x14, HDA_OUTPUT, 0, +- HDA_AMP_MUTE, +- valp ? 0 : HDA_AMP_MUTE); +- change |= snd_hda_codec_amp_stereo(codec, 0x1b, HDA_OUTPUT, 0, +- HDA_AMP_MUTE, +- valp ? 0 : HDA_AMP_MUTE); +- ++ change = amp_stereo_mute_update(codec, 0x14, HDA_OUTPUT, 0, valp); ++ change |= amp_stereo_mute_update(codec, 0x1b, HDA_OUTPUT, 0, valp); + if (change) + alc262_fujitsu_automute(codec, 0); + return change; +@@ -9869,10 +9876,7 @@ static int alc262_lenovo_3000_master_sw_ + long *valp = ucontrol->value.integer.value; + int change; + +- change = snd_hda_codec_amp_stereo(codec, 0x1b, HDA_OUTPUT, 0, +- HDA_AMP_MUTE, +- valp ? 0 : HDA_AMP_MUTE); +- ++ change = amp_stereo_mute_update(codec, 0x1b, HDA_OUTPUT, 0, valp); + if (change) + alc262_lenovo_3000_automute(codec, 0); + return change; +@@ -10962,12 +10966,7 @@ static int alc268_acer_master_sw_put(str + long *valp = ucontrol->value.integer.value; + int change; + +- change = snd_hda_codec_amp_update(codec, 0x14, 0, HDA_OUTPUT, 0, +- HDA_AMP_MUTE, +- valp[0] ? 0 : HDA_AMP_MUTE); +- change |= snd_hda_codec_amp_update(codec, 0x14, 1, HDA_OUTPUT, 0, +- HDA_AMP_MUTE, +- valp[1] ? 0 : HDA_AMP_MUTE); ++ change = amp_stereo_mute_update(codec, 0x14, HDA_OUTPUT, 0, valp); + if (change) + alc268_acer_automute(codec, 0); + return change; +@@ -11422,26 +11421,38 @@ static int alc268_new_analog_output(stru + const char *ctlname, int idx) + { + char name[32]; ++ hda_nid_t dac; + int err; + + sprintf(name, "%s Playback Volume", ctlname); +- if (nid == 0x14) { +- err = add_control(spec, ALC_CTL_WIDGET_VOL, name, +- HDA_COMPOSE_AMP_VAL(0x02, 3, idx, +- HDA_OUTPUT)); +- if (err < 0) +- return err; +- } else if (nid == 0x15) { ++ switch (nid) { ++ case 0x14: ++ case 0x16: ++ dac = 0x02; ++ break; ++ case 0x15: ++ dac = 0x03; ++ break; ++ default: ++ return 0; ++ } ++ if (spec->multiout.dac_nids[0] != dac && ++ spec->multiout.dac_nids[1] != dac) { + err = add_control(spec, ALC_CTL_WIDGET_VOL, name, +- HDA_COMPOSE_AMP_VAL(0x03, 3, idx, ++ HDA_COMPOSE_AMP_VAL(dac, 3, idx, + HDA_OUTPUT)); + if (err < 0) + return err; +- } else +- return -1; ++ spec->multiout.dac_nids[spec->multiout.num_dacs++] = dac; ++ } ++ + sprintf(name, "%s Playback Switch", ctlname); +- err = add_control(spec, ALC_CTL_WIDGET_MUTE, name, ++ if (nid != 0x16) ++ err = add_control(spec, ALC_CTL_WIDGET_MUTE, name, + HDA_COMPOSE_AMP_VAL(nid, 3, idx, HDA_OUTPUT)); ++ else /* mono */ ++ err = add_control(spec, ALC_CTL_WIDGET_MUTE, name, ++ HDA_COMPOSE_AMP_VAL(nid, 2, idx, HDA_OUTPUT)); + if (err < 0) + return err; + return 0; +@@ -11454,14 +11465,19 @@ static int alc268_auto_create_multi_out_ + hda_nid_t nid; + int err; + +- spec->multiout.num_dacs = 2; /* only use one dac */ + spec->multiout.dac_nids = spec->private_dac_nids; +- spec->multiout.dac_nids[0] = 2; +- spec->multiout.dac_nids[1] = 3; + + nid = cfg->line_out_pins[0]; +- if (nid) +- alc268_new_analog_output(spec, nid, "Front", 0); ++ if (nid) { ++ const char *name; ++ if (cfg->line_out_type == AUTO_PIN_SPEAKER_OUT) ++ name = "Speaker"; ++ else ++ name = "Front"; ++ err = alc268_new_analog_output(spec, nid, name, 0); ++ if (err < 0) ++ return err; ++ } + + nid = cfg->speaker_pins[0]; + if (nid == 0x1d) { +@@ -11470,16 +11486,23 @@ static int alc268_auto_create_multi_out_ + HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_INPUT)); + if (err < 0) + return err; ++ } else { ++ err = alc268_new_analog_output(spec, nid, "Speaker", 0); ++ if (err < 0) ++ return err; + } + nid = cfg->hp_pins[0]; +- if (nid) +- alc268_new_analog_output(spec, nid, "Headphone", 0); ++ if (nid) { ++ err = alc268_new_analog_output(spec, nid, "Headphone", 0); ++ if (err < 0) ++ return err; ++ } + + nid = cfg->line_out_pins[1] | cfg->line_out_pins[2]; + if (nid == 0x16) { + err = add_control(spec, ALC_CTL_WIDGET_MUTE, + "Mono Playback Switch", +- HDA_COMPOSE_AMP_VAL(nid, 2, 0, HDA_INPUT)); ++ HDA_COMPOSE_AMP_VAL(nid, 2, 0, HDA_OUTPUT)); + if (err < 0) + return err; + } +@@ -12631,6 +12654,8 @@ static int patch_alc269(struct hda_codec + spec->num_adc_nids = ARRAY_SIZE(alc269_adc_nids); + spec->capsrc_nids = alc269_capsrc_nids; + ++ spec->vmaster_nid = 0x02; ++ + codec->patch_ops = alc_patch_ops; + if (board_config == ALC269_AUTO) + spec->init_hook = alc269_auto_init; +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/sound/pci/hda/patch_sigmatel.c linux-2.6.27.29-0.1.1/sound/pci/hda/patch_sigmatel.c +--- linux-2.6.27.25-0.1.1/sound/pci/hda/patch_sigmatel.c 2009-08-27 12:59:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/sound/pci/hda/patch_sigmatel.c 2009-08-27 12:44:15.000000000 +0100 +@@ -35,14 +35,17 @@ + #include "hda_patch.h" + #include "hda_beep.h" + +-#define NUM_CONTROL_ALLOC 32 +- +-#define STAC_VREF_EVENT 0x00 +-#define STAC_INSERT_EVENT 0x10 +-#define STAC_PWR_EVENT 0x20 +-#define STAC_HP_EVENT 0x30 ++enum { ++ STAC_VREF_EVENT = 1, ++ STAC_INSERT_EVENT, ++ STAC_PWR_EVENT, ++ STAC_HP_EVENT, ++ STAC_LO_EVENT, ++ STAC_MIC_EVENT, ++}; + + enum { ++ STAC_AUTO, + STAC_REF, + STAC_9200_OQO, + STAC_9200_DELL_D21, +@@ -62,6 +65,7 @@ enum { + }; + + enum { ++ STAC_9205_AUTO, + STAC_9205_REF, + STAC_9205_DELL_M42, + STAC_9205_DELL_M43, +@@ -71,6 +75,7 @@ enum { + }; + + enum { ++ STAC_92HD73XX_AUTO, + STAC_92HD73XX_NO_JD, /* no jack-detection */ + STAC_92HD73XX_REF, + STAC_DELL_M6_AMIC, +@@ -81,22 +86,28 @@ enum { + }; + + enum { ++ STAC_92HD83XXX_AUTO, + STAC_92HD83XXX_REF, + STAC_92HD83XXX_PWR_REF, ++ STAC_DELL_S14, + STAC_92HD83XXX_MODELS + }; + + enum { ++ STAC_92HD71BXX_AUTO, + STAC_92HD71BXX_REF, + STAC_DELL_M4_1, + STAC_DELL_M4_2, + STAC_DELL_M4_3, + STAC_HP_M4, + STAC_HP_DV5, ++ STAC_HP_HDX, ++ STAC_HP_DV4_1222NR, + STAC_92HD71BXX_MODELS + }; + + enum { ++ STAC_925x_AUTO, + STAC_925x_REF, + STAC_M1, + STAC_M1_2, +@@ -109,6 +120,7 @@ enum { + }; + + enum { ++ STAC_922X_AUTO, + STAC_D945_REF, + STAC_D945GTP3, + STAC_D945GTP5, +@@ -136,10 +148,12 @@ enum { + }; + + enum { ++ STAC_927X_AUTO, + STAC_D965_REF_NO_JD, /* no jack-detection */ + STAC_D965_REF, + STAC_D965_3ST, + STAC_D965_5ST, ++ STAC_D965_5ST_NO_FP, + STAC_DELL_3ST, + STAC_DELL_BIOS, + STAC_927X_MODELS +@@ -152,6 +166,18 @@ struct sigmatel_event { + int data; + }; + ++struct sigmatel_jack { ++ hda_nid_t nid; ++ int type; ++ struct snd_jack *jack; ++}; ++ ++struct sigmatel_mic_route { ++ hda_nid_t pin; ++ unsigned char mux_idx; ++ unsigned char dmux_idx; ++}; ++ + struct sigmatel_spec { + struct snd_kcontrol_new *mixers[4]; + unsigned int num_mixers; +@@ -163,6 +189,7 @@ struct sigmatel_spec { + unsigned int hp_detect: 1; + unsigned int spdif_mute: 1; + unsigned int check_volume_offset:1; ++ unsigned int auto_mic:1; + + /* gpio lines */ + unsigned int eapd_mask; +@@ -170,23 +197,22 @@ struct sigmatel_spec { + unsigned int gpio_dir; + unsigned int gpio_data; + unsigned int gpio_mute; ++ unsigned int gpio_led; + + /* stream */ + unsigned int stream_delay; + +- /* analog loopback */ +- unsigned char aloopback_mask; +- unsigned char aloopback_shift; +- + /* power management */ + unsigned int num_pwrs; + unsigned int *pwr_mapping; + hda_nid_t *pwr_nids; + hda_nid_t *dac_list; + ++ /* jack detection */ ++ struct snd_array jacks; ++ + /* events */ +- int num_events; +- struct sigmatel_event events[32]; ++ struct snd_array events; + + /* playback */ + struct hda_input_mux *mono_mux; +@@ -210,6 +236,15 @@ struct sigmatel_spec { + unsigned int num_dmuxes; + hda_nid_t *smux_nids; + unsigned int num_smuxes; ++ unsigned int num_analog_muxes; ++ ++ unsigned long *capvols; /* amp-volume attr: HDA_COMPOSE_AMP_VAL() */ ++ unsigned long *capsws; /* amp-mute attr: HDA_COMPOSE_AMP_VAL() */ ++ unsigned int num_caps; /* number of capture volume/switch elements */ ++ ++ struct sigmatel_mic_route ext_mic; ++ struct sigmatel_mic_route int_mic; ++ + const char **spdif_labels; + + hda_nid_t dig_in_nid; +@@ -245,14 +280,12 @@ struct sigmatel_spec { + hda_nid_t line_switch; /* shared line-in for input and output */ + hda_nid_t mic_switch; /* shared mic-in for input and output */ + hda_nid_t hp_switch; /* NID of HP as line-out */ +- unsigned int aloopback; + + struct hda_pcm pcm_rec[2]; /* PCM information */ + + /* dynamic controls and input_mux */ + struct auto_pin_cfg autocfg; +- unsigned int num_kctl_alloc, num_kctl_used; +- struct snd_kcontrol_new *kctl_alloc; ++ struct snd_array kctls; + struct hda_input_mux private_dimux; + struct hda_input_mux private_imux; + struct hda_input_mux private_smux; +@@ -309,14 +342,16 @@ static hda_nid_t stac92hd73xx_smux_nids[ + 0x22, 0x23, + }; + +-#define STAC92HD83XXX_NUM_DMICS 2 +-static hda_nid_t stac92hd83xxx_dmic_nids[STAC92HD83XXX_NUM_DMICS + 1] = { +- 0x11, 0x12, 0 ++#define STAC92HD73XX_NUM_CAPS 2 ++static unsigned long stac92hd73xx_capvols[] = { ++ HDA_COMPOSE_AMP_VAL(0x20, 3, 0, HDA_OUTPUT), ++ HDA_COMPOSE_AMP_VAL(0x21, 3, 0, HDA_OUTPUT), + }; ++#define stac92hd73xx_capsws stac92hd73xx_capvols + + #define STAC92HD83_DAC_COUNT 3 + +-static hda_nid_t stac92hd83xxx_dmux_nids[2] = { ++static hda_nid_t stac92hd83xxx_mux_nids[2] = { + 0x17, 0x18, + }; + +@@ -336,9 +371,12 @@ static unsigned int stac92hd83xxx_pwr_ma + 0x03, 0x0c, 0x20, 0x40, + }; + +-static hda_nid_t stac92hd83xxx_amp_nids[1] = { +- 0xc, ++#define STAC92HD83XXX_NUM_CAPS 2 ++static unsigned long stac92hd83xxx_capvols[] = { ++ HDA_COMPOSE_AMP_VAL(0x17, 3, 0, HDA_OUTPUT), ++ HDA_COMPOSE_AMP_VAL(0x18, 3, 0, HDA_OUTPUT), + }; ++#define stac92hd83xxx_capsws stac92hd83xxx_capvols + + static hda_nid_t stac92hd71bxx_pwr_nids[3] = { + 0x0a, 0x0d, 0x0f +@@ -369,6 +407,13 @@ static hda_nid_t stac92hd71bxx_slave_dig + 0x22, 0 + }; + ++#define STAC92HD71BXX_NUM_CAPS 2 ++static unsigned long stac92hd71bxx_capvols[] = { ++ HDA_COMPOSE_AMP_VAL(0x1c, 3, 0, HDA_OUTPUT), ++ HDA_COMPOSE_AMP_VAL(0x1d, 3, 0, HDA_OUTPUT), ++}; ++#define stac92hd71bxx_capsws stac92hd71bxx_capvols ++ + static hda_nid_t stac925x_adc_nids[1] = { + 0x03, + }; +@@ -390,6 +435,13 @@ static hda_nid_t stac925x_dmux_nids[1] = + 0x14, + }; + ++static unsigned long stac925x_capvols[] = { ++ HDA_COMPOSE_AMP_VAL(0x09, 3, 0, HDA_OUTPUT), ++}; ++static unsigned long stac925x_capsws[] = { ++ HDA_COMPOSE_AMP_VAL(0x14, 3, 0, HDA_OUTPUT), ++}; ++ + static hda_nid_t stac922x_adc_nids[2] = { + 0x06, 0x07, + }; +@@ -398,6 +450,17 @@ static hda_nid_t stac922x_mux_nids[2] = + 0x12, 0x13, + }; + ++#define STAC922X_NUM_CAPS 2 ++static unsigned long stac922x_capvols[] = { ++ HDA_COMPOSE_AMP_VAL(0x17, 3, 0, HDA_INPUT), ++ HDA_COMPOSE_AMP_VAL(0x18, 3, 0, HDA_INPUT), ++}; ++#define stac922x_capsws stac922x_capvols ++ ++static hda_nid_t stac927x_slave_dig_outs[2] = { ++ 0x1f, 0, ++}; ++ + static hda_nid_t stac927x_adc_nids[3] = { + 0x07, 0x08, 0x09 + }; +@@ -423,6 +486,18 @@ static hda_nid_t stac927x_dmic_nids[STAC + 0x13, 0x14, 0 + }; + ++#define STAC927X_NUM_CAPS 3 ++static unsigned long stac927x_capvols[] = { ++ HDA_COMPOSE_AMP_VAL(0x18, 3, 0, HDA_INPUT), ++ HDA_COMPOSE_AMP_VAL(0x19, 3, 0, HDA_INPUT), ++ HDA_COMPOSE_AMP_VAL(0x1a, 3, 0, HDA_INPUT), ++}; ++static unsigned long stac927x_capsws[] = { ++ HDA_COMPOSE_AMP_VAL(0x1b, 3, 0, HDA_OUTPUT), ++ HDA_COMPOSE_AMP_VAL(0x1c, 3, 0, HDA_OUTPUT), ++ HDA_COMPOSE_AMP_VAL(0x1d, 3, 0, HDA_OUTPUT), ++}; ++ + static const char *stac927x_spdif_labels[5] = { + "Digital Playback", "ADAT", "Analog Mux 1", + "Analog Mux 2", "Analog Mux 3" +@@ -449,6 +524,16 @@ static hda_nid_t stac9205_dmic_nids[STAC + 0x17, 0x18, 0 + }; + ++#define STAC9205_NUM_CAPS 2 ++static unsigned long stac9205_capvols[] = { ++ HDA_COMPOSE_AMP_VAL(0x1b, 3, 0, HDA_INPUT), ++ HDA_COMPOSE_AMP_VAL(0x1c, 3, 0, HDA_INPUT), ++}; ++static unsigned long stac9205_capsws[] = { ++ HDA_COMPOSE_AMP_VAL(0x1d, 3, 0, HDA_OUTPUT), ++ HDA_COMPOSE_AMP_VAL(0x1e, 3, 0, HDA_OUTPUT), ++}; ++ + static hda_nid_t stac9200_pin_nids[8] = { + 0x08, 0x09, 0x0d, 0x0e, + 0x0f, 0x10, 0x11, 0x12, +@@ -470,15 +555,21 @@ static hda_nid_t stac92hd73xx_pin_nids[1 + 0x14, 0x22, 0x23 + }; + +-static hda_nid_t stac92hd83xxx_pin_nids[14] = { ++static hda_nid_t stac92hd83xxx_pin_nids[10] = { + 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, +- 0x0f, 0x10, 0x11, 0x12, 0x13, +- 0x1d, 0x1e, 0x1f, 0x20 ++ 0x0f, 0x10, 0x11, 0x1f, 0x20, ++}; ++ ++#define STAC92HD71BXX_NUM_PINS 13 ++static hda_nid_t stac92hd71bxx_pin_nids_4port[STAC92HD71BXX_NUM_PINS] = { ++ 0x0a, 0x0b, 0x0c, 0x0d, 0x00, ++ 0x00, 0x14, 0x18, 0x19, 0x1e, ++ 0x1f, 0x20, 0x27 + }; +-static hda_nid_t stac92hd71bxx_pin_nids[11] = { ++static hda_nid_t stac92hd71bxx_pin_nids_6port[STAC92HD71BXX_NUM_PINS] = { + 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, + 0x0f, 0x14, 0x18, 0x19, 0x1e, +- 0x1f, ++ 0x1f, 0x20, 0x27 + }; + + static hda_nid_t stac927x_pin_nids[14] = { +@@ -521,36 +612,6 @@ static int stac92xx_amp_volume_put(struc + return snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); + } + +-static int stac92xx_dmux_enum_info(struct snd_kcontrol *kcontrol, +- struct snd_ctl_elem_info *uinfo) +-{ +- struct hda_codec *codec = snd_kcontrol_chip(kcontrol); +- struct sigmatel_spec *spec = codec->spec; +- return snd_hda_input_mux_info(spec->dinput_mux, uinfo); +-} +- +-static int stac92xx_dmux_enum_get(struct snd_kcontrol *kcontrol, +- struct snd_ctl_elem_value *ucontrol) +-{ +- struct hda_codec *codec = snd_kcontrol_chip(kcontrol); +- struct sigmatel_spec *spec = codec->spec; +- unsigned int dmux_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); +- +- ucontrol->value.enumerated.item[0] = spec->cur_dmux[dmux_idx]; +- return 0; +-} +- +-static int stac92xx_dmux_enum_put(struct snd_kcontrol *kcontrol, +- struct snd_ctl_elem_value *ucontrol) +-{ +- struct hda_codec *codec = snd_kcontrol_chip(kcontrol); +- struct sigmatel_spec *spec = codec->spec; +- unsigned int dmux_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); +- +- return snd_hda_input_mux_put(codec, spec->dinput_mux, ucontrol, +- spec->dmux_nids[dmux_idx], &spec->cur_dmux[dmux_idx]); +-} +- + static int stac92xx_smux_enum_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) + { +@@ -601,6 +662,40 @@ static int stac92xx_smux_enum_put(struct + return 0; + } + ++static unsigned int stac92xx_vref_set(struct hda_codec *codec, ++ hda_nid_t nid, unsigned int new_vref) ++{ ++ int error; ++ unsigned int pincfg; ++ pincfg = snd_hda_codec_read(codec, nid, 0, ++ AC_VERB_GET_PIN_WIDGET_CONTROL, 0); ++ ++ pincfg &= 0xff; ++ pincfg &= ~(AC_PINCTL_VREFEN | AC_PINCTL_IN_EN | AC_PINCTL_OUT_EN); ++ pincfg |= new_vref; ++ ++ if (new_vref == AC_PINCTL_VREF_HIZ) ++ pincfg |= AC_PINCTL_OUT_EN; ++ else ++ pincfg |= AC_PINCTL_IN_EN; ++ ++ error = snd_hda_codec_write_cache(codec, nid, 0, ++ AC_VERB_SET_PIN_WIDGET_CONTROL, pincfg); ++ if (error < 0) ++ return error; ++ else ++ return 1; ++} ++ ++static unsigned int stac92xx_vref_get(struct hda_codec *codec, hda_nid_t nid) ++{ ++ unsigned int vref; ++ vref = snd_hda_codec_read(codec, nid, 0, ++ AC_VERB_GET_PIN_WIDGET_CONTROL, 0); ++ vref &= AC_PINCTL_VREFEN; ++ return vref; ++} ++ + static int stac92xx_mux_enum_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) + { + struct hda_codec *codec = snd_kcontrol_chip(kcontrol); +@@ -623,9 +718,35 @@ static int stac92xx_mux_enum_put(struct + struct hda_codec *codec = snd_kcontrol_chip(kcontrol); + struct sigmatel_spec *spec = codec->spec; + unsigned int adc_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); ++ const struct hda_input_mux *imux = spec->input_mux; ++ unsigned int idx, prev_idx; + +- return snd_hda_input_mux_put(codec, spec->input_mux, ucontrol, +- spec->mux_nids[adc_idx], &spec->cur_mux[adc_idx]); ++ idx = ucontrol->value.enumerated.item[0]; ++ if (idx >= imux->num_items) ++ idx = imux->num_items - 1; ++ prev_idx = spec->cur_mux[adc_idx]; ++ if (prev_idx == idx) ++ return 0; ++ if (idx < spec->num_analog_muxes) { ++ snd_hda_codec_write_cache(codec, spec->mux_nids[adc_idx], 0, ++ AC_VERB_SET_CONNECT_SEL, ++ imux->items[idx].index); ++ if (prev_idx >= spec->num_analog_muxes) { ++ imux = spec->dinput_mux; ++ /* 0 = analog */ ++ snd_hda_codec_write_cache(codec, ++ spec->dmux_nids[adc_idx], 0, ++ AC_VERB_SET_CONNECT_SEL, ++ imux->items[0].index); ++ } ++ } else { ++ imux = spec->dinput_mux; ++ snd_hda_codec_write_cache(codec, spec->dmux_nids[adc_idx], 0, ++ AC_VERB_SET_CONNECT_SEL, ++ imux->items[idx - 1].index); ++ } ++ spec->cur_mux[adc_idx] = idx; ++ return 1; + } + + static int stac92xx_mono_mux_enum_info(struct snd_kcontrol *kcontrol, +@@ -691,60 +812,6 @@ static int stac92xx_amp_mux_enum_put(str + 0, &spec->cur_amux); + } + +-#define stac92xx_aloopback_info snd_ctl_boolean_mono_info +- +-static int stac92xx_aloopback_get(struct snd_kcontrol *kcontrol, +- struct snd_ctl_elem_value *ucontrol) +-{ +- struct hda_codec *codec = snd_kcontrol_chip(kcontrol); +- unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); +- struct sigmatel_spec *spec = codec->spec; +- +- ucontrol->value.integer.value[0] = !!(spec->aloopback & +- (spec->aloopback_mask << idx)); +- return 0; +-} +- +-static int stac92xx_aloopback_put(struct snd_kcontrol *kcontrol, +- struct snd_ctl_elem_value *ucontrol) +-{ +- struct hda_codec *codec = snd_kcontrol_chip(kcontrol); +- struct sigmatel_spec *spec = codec->spec; +- unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); +- unsigned int dac_mode; +- unsigned int val, idx_val; +- +- idx_val = spec->aloopback_mask << idx; +- if (ucontrol->value.integer.value[0]) +- val = spec->aloopback | idx_val; +- else +- val = spec->aloopback & ~idx_val; +- if (spec->aloopback == val) +- return 0; +- +- spec->aloopback = val; +- +- /* Only return the bits defined by the shift value of the +- * first two bytes of the mask +- */ +- dac_mode = snd_hda_codec_read(codec, codec->afg, 0, +- kcontrol->private_value & 0xFFFF, 0x0); +- dac_mode >>= spec->aloopback_shift; +- +- if (spec->aloopback & idx_val) { +- snd_hda_power_up(codec); +- dac_mode |= idx_val; +- } else { +- snd_hda_power_down(codec); +- dac_mode &= ~idx_val; +- } +- +- snd_hda_codec_write_cache(codec, codec->afg, 0, +- kcontrol->private_value >> 16, dac_mode); +- +- return 1; +-} +- + static struct hda_verb stac9200_core_init[] = { + /* set dac0mux for dac converter */ + { 0x07, AC_VERB_SET_CONNECT_SEL, 0x00}, +@@ -840,9 +907,9 @@ static struct hda_verb stac92hd73xx_10ch + }; + + static struct hda_verb stac92hd83xxx_core_init[] = { +- { 0xa, AC_VERB_SET_CONNECT_SEL, 0x0}, +- { 0xb, AC_VERB_SET_CONNECT_SEL, 0x0}, +- { 0xd, AC_VERB_SET_CONNECT_SEL, 0x1}, ++ { 0xa, AC_VERB_SET_CONNECT_SEL, 0x1}, ++ { 0xb, AC_VERB_SET_CONNECT_SEL, 0x1}, ++ { 0xd, AC_VERB_SET_CONNECT_SEL, 0x0}, + + /* power state controls amps */ + { 0x01, AC_VERB_SET_EAPD, 1 << 2}, +@@ -852,26 +919,12 @@ static struct hda_verb stac92hd83xxx_cor + static struct hda_verb stac92hd71bxx_core_init[] = { + /* set master volume and direct control */ + { 0x28, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff}, +- /* unmute right and left channels for nodes 0x0a, 0xd, 0x0f */ +- { 0x0a, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)}, +- { 0x0d, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)}, +- { 0x0f, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)}, + {} + }; + +-#define HD_DISABLE_PORTF 2 +-static struct hda_verb stac92hd71bxx_analog_core_init[] = { +- /* start of config #1 */ +- +- /* connect port 0f to audio mixer */ +- { 0x0f, AC_VERB_SET_CONNECT_SEL, 0x2}, +- /* unmute right and left channels for node 0x0f */ ++static struct hda_verb stac92hd71bxx_unmute_core_init[] = { ++ /* unmute right and left channels for nodes 0x0f, 0xa, 0x0d */ + { 0x0f, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)}, +- /* start of config #2 */ +- +- /* set master volume and direct control */ +- { 0x28, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff}, +- /* unmute right and left channels for nodes 0x0a, 0xd */ + { 0x0a, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)}, + { 0x0d, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)}, + {} +@@ -952,31 +1005,20 @@ static struct hda_verb stac9205_core_ini + .private_value = HDA_COMPOSE_AMP_VAL(nid, chs, idx, dir) \ + } + +-#define STAC_INPUT_SOURCE(cnt) \ +- { \ +- .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ +- .name = "Input Source", \ +- .count = cnt, \ +- .info = stac92xx_mux_enum_info, \ +- .get = stac92xx_mux_enum_get, \ +- .put = stac92xx_mux_enum_put, \ +- } +- +-#define STAC_ANALOG_LOOPBACK(verb_read, verb_write, cnt) \ ++#define DC_BIAS(xname, idx, nid) \ + { \ + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ +- .name = "Analog Loopback", \ +- .count = cnt, \ +- .info = stac92xx_aloopback_info, \ +- .get = stac92xx_aloopback_get, \ +- .put = stac92xx_aloopback_put, \ +- .private_value = verb_read | (verb_write << 16), \ ++ .name = xname, \ ++ .index = idx, \ ++ .info = stac92xx_dc_bias_info, \ ++ .get = stac92xx_dc_bias_get, \ ++ .put = stac92xx_dc_bias_put, \ ++ .private_value = nid, \ + } + + static struct snd_kcontrol_new stac9200_mixer[] = { + HDA_CODEC_VOLUME("Master Playback Volume", 0xb, 0, HDA_OUTPUT), + HDA_CODEC_MUTE("Master Playback Switch", 0xb, 0, HDA_OUTPUT), +- STAC_INPUT_SOURCE(1), + HDA_CODEC_VOLUME("Capture Volume", 0x0a, 0, HDA_OUTPUT), + HDA_CODEC_MUTE("Capture Switch", 0x0a, 0, HDA_OUTPUT), + { } /* end */ +@@ -1001,26 +1043,10 @@ static struct snd_kcontrol_new stac92hd7 + HDA_CODEC_VOLUME("DAC Mixer Capture Volume", 0x1d, 0x3, HDA_INPUT), + HDA_CODEC_MUTE("DAC Mixer Capture Switch", 0x1d, 0x3, HDA_INPUT), + +- STAC_ANALOG_LOOPBACK(0xFA0, 0x7A1, 3), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x20, 0x0, HDA_OUTPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x20, 0x0, HDA_OUTPUT), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x21, 0x0, HDA_OUTPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x21, 0x0, HDA_OUTPUT), +- + { } /* end */ + }; + + static struct snd_kcontrol_new stac92hd73xx_8ch_mixer[] = { +- STAC_ANALOG_LOOPBACK(0xFA0, 0x7A1, 4), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x20, 0x0, HDA_OUTPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x20, 0x0, HDA_OUTPUT), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x21, 0x0, HDA_OUTPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x21, 0x0, HDA_OUTPUT), +- + HDA_CODEC_VOLUME("Front Mic Mixer Capture Volume", 0x1d, 0, HDA_INPUT), + HDA_CODEC_MUTE("Front Mic Mixer Capture Switch", 0x1d, 0, HDA_INPUT), + +@@ -1039,14 +1065,6 @@ static struct snd_kcontrol_new stac92hd7 + }; + + static struct snd_kcontrol_new stac92hd73xx_10ch_mixer[] = { +- STAC_ANALOG_LOOPBACK(0xFA0, 0x7A1, 5), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x20, 0x0, HDA_OUTPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x20, 0x0, HDA_OUTPUT), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x21, 0x0, HDA_OUTPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x21, 0x0, HDA_OUTPUT), +- + HDA_CODEC_VOLUME("Front Mic Mixer Capture Volume", 0x1d, 0, HDA_INPUT), + HDA_CODEC_MUTE("Front Mic Mixer Capture Switch", 0x1d, 0, HDA_INPUT), + +@@ -1065,130 +1083,12 @@ static struct snd_kcontrol_new stac92hd7 + }; + + +-static struct snd_kcontrol_new stac92hd83xxx_mixer[] = { +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x17, 0x0, HDA_OUTPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x17, 0x0, HDA_OUTPUT), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x18, 0x0, HDA_OUTPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x18, 0x0, HDA_OUTPUT), +- +- HDA_CODEC_VOLUME("DAC0 Capture Volume", 0x1b, 0x3, HDA_INPUT), +- HDA_CODEC_MUTE("DAC0 Capture Switch", 0x1b, 0x3, HDA_INPUT), +- +- HDA_CODEC_VOLUME("DAC1 Capture Volume", 0x1b, 0x4, HDA_INPUT), +- HDA_CODEC_MUTE("DAC1 Capture Switch", 0x1b, 0x4, HDA_INPUT), +- +- HDA_CODEC_VOLUME("Front Mic Capture Volume", 0x1b, 0x0, HDA_INPUT), +- HDA_CODEC_MUTE("Front Mic Capture Switch", 0x1b, 0x0, HDA_INPUT), +- +- HDA_CODEC_VOLUME("Line In Capture Volume", 0x1b, 0x2, HDA_INPUT), +- HDA_CODEC_MUTE("Line In Capture Switch", 0x1b, 0x2, HDA_INPUT), +- +- /* +- HDA_CODEC_VOLUME("Mic Capture Volume", 0x1b, 0x1, HDA_INPUT), +- HDA_CODEC_MUTE("Mic Capture Switch", 0x1b 0x1, HDA_INPUT), +- */ +- { } /* end */ +-}; +- +-static struct snd_kcontrol_new stac92hd71bxx_analog_mixer[] = { +- STAC_INPUT_SOURCE(2), +- STAC_ANALOG_LOOPBACK(0xFA0, 0x7A0, 2), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x1c, 0x0, HDA_OUTPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x1c, 0x0, HDA_OUTPUT), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x1d, 0x0, HDA_OUTPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x1d, 0x0, HDA_OUTPUT), +- /* analog pc-beep replaced with digital beep support */ +- /* +- HDA_CODEC_VOLUME("PC Beep Volume", 0x17, 0x2, HDA_INPUT), +- HDA_CODEC_MUTE("PC Beep Switch", 0x17, 0x2, HDA_INPUT), +- */ +- +- HDA_CODEC_MUTE("Import0 Mux Capture Switch", 0x17, 0x0, HDA_INPUT), +- HDA_CODEC_VOLUME("Import0 Mux Capture Volume", 0x17, 0x0, HDA_INPUT), +- +- HDA_CODEC_MUTE("Import1 Mux Capture Switch", 0x17, 0x1, HDA_INPUT), +- HDA_CODEC_VOLUME("Import1 Mux Capture Volume", 0x17, 0x1, HDA_INPUT), +- +- HDA_CODEC_MUTE("DAC0 Capture Switch", 0x17, 0x3, HDA_INPUT), +- HDA_CODEC_VOLUME("DAC0 Capture Volume", 0x17, 0x3, HDA_INPUT), +- +- HDA_CODEC_MUTE("DAC1 Capture Switch", 0x17, 0x4, HDA_INPUT), +- HDA_CODEC_VOLUME("DAC1 Capture Volume", 0x17, 0x4, HDA_INPUT), +- { } /* end */ +-}; +- +-static struct snd_kcontrol_new stac92hd71bxx_mixer[] = { +- STAC_INPUT_SOURCE(2), +- STAC_ANALOG_LOOPBACK(0xFA0, 0x7A0, 2), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x1c, 0x0, HDA_OUTPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x1c, 0x0, HDA_OUTPUT), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x1d, 0x0, HDA_OUTPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x1d, 0x0, HDA_OUTPUT), +- { } /* end */ +-}; +- + static struct snd_kcontrol_new stac925x_mixer[] = { + HDA_CODEC_VOLUME("Master Playback Volume", 0x0e, 0, HDA_OUTPUT), + HDA_CODEC_MUTE("Master Playback Switch", 0x0e, 0, HDA_OUTPUT), +- STAC_INPUT_SOURCE(1), +- HDA_CODEC_VOLUME("Capture Volume", 0x09, 0, HDA_OUTPUT), +- HDA_CODEC_MUTE("Capture Switch", 0x14, 0, HDA_OUTPUT), +- { } /* end */ +-}; +- +-static struct snd_kcontrol_new stac9205_mixer[] = { +- STAC_INPUT_SOURCE(2), +- STAC_ANALOG_LOOPBACK(0xFE0, 0x7E0, 1), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x1b, 0x0, HDA_INPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x1d, 0x0, HDA_OUTPUT), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x1c, 0x0, HDA_INPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x1e, 0x0, HDA_OUTPUT), + { } /* end */ + }; + +-/* This needs to be generated dynamically based on sequence */ +-static struct snd_kcontrol_new stac922x_mixer[] = { +- STAC_INPUT_SOURCE(2), +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x17, 0x0, HDA_INPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x17, 0x0, HDA_INPUT), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x18, 0x0, HDA_INPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x18, 0x0, HDA_INPUT), +- { } /* end */ +-}; +- +- +-static struct snd_kcontrol_new stac927x_mixer[] = { +- STAC_INPUT_SOURCE(3), +- STAC_ANALOG_LOOPBACK(0xFEB, 0x7EB, 1), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x18, 0x0, HDA_INPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x1b, 0x0, HDA_OUTPUT), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x19, 0x0, HDA_INPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x1c, 0x0, HDA_OUTPUT), +- +- HDA_CODEC_VOLUME_IDX("Capture Volume", 0x2, 0x1A, 0x0, HDA_INPUT), +- HDA_CODEC_MUTE_IDX("Capture Switch", 0x2, 0x1d, 0x0, HDA_OUTPUT), +- { } /* end */ +-}; +- +-static struct snd_kcontrol_new stac_dmux_mixer = { +- .iface = SNDRV_CTL_ELEM_IFACE_MIXER, +- .name = "Digital Input Source", +- /* count set later */ +- .info = stac92xx_dmux_enum_info, +- .get = stac92xx_dmux_enum_get, +- .put = stac92xx_dmux_enum_put, +-}; +- + static struct snd_kcontrol_new stac_smux_mixer = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "IEC958 Playback Source", +@@ -1205,10 +1105,7 @@ static const char *slave_vols[] = { + "LFE Playback Volume", + "Side Playback Volume", + "Headphone Playback Volume", +- "Headphone2 Playback Volume", + "Speaker Playback Volume", +- "External Speaker Playback Volume", +- "Speaker2 Playback Volume", + NULL + }; + +@@ -1219,33 +1116,27 @@ static const char *slave_sws[] = { + "LFE Playback Switch", + "Side Playback Switch", + "Headphone Playback Switch", +- "Headphone2 Playback Switch", + "Speaker Playback Switch", +- "External Speaker Playback Switch", +- "Speaker2 Playback Switch", + "IEC958 Playback Switch", + NULL + }; + ++static void stac92xx_free_kctls(struct hda_codec *codec); ++ + static int stac92xx_build_controls(struct hda_codec *codec) + { + struct sigmatel_spec *spec = codec->spec; + int err; + int i; + +- err = snd_hda_add_new_ctls(codec, spec->mixer); +- if (err < 0) +- return err; +- +- for (i = 0; i < spec->num_mixers; i++) { +- err = snd_hda_add_new_ctls(codec, spec->mixers[i]); ++ if (spec->mixer) { ++ err = snd_hda_add_new_ctls(codec, spec->mixer); + if (err < 0) + return err; + } +- if (spec->num_dmuxes > 0) { +- stac_dmux_mixer.count = spec->num_dmuxes; +- err = snd_ctl_add(codec->bus->card, +- snd_ctl_new1(&stac_dmux_mixer, codec)); ++ ++ for (i = 0; i < spec->num_mixers; i++) { ++ err = snd_hda_add_new_ctls(codec, spec->mixers[i]); + if (err < 0) + return err; + } +@@ -1301,6 +1192,8 @@ static int stac92xx_build_controls(struc + return err; + } + ++ stac92xx_free_kctls(codec); /* no longer needed */ ++ + return 0; + } + +@@ -1454,6 +1347,7 @@ static unsigned int *stac9200_brd_tbl[ST + }; + + static const char *stac9200_models[STAC_9200_MODELS] = { ++ [STAC_AUTO] = "auto", + [STAC_REF] = "ref", + [STAC_9200_OQO] = "oqo", + [STAC_9200_DELL_D21] = "dell-d21", +@@ -1471,10 +1365,16 @@ static const char *stac9200_models[STAC_ + [STAC_9200_PANASONIC] = "panasonic", + }; + ++#ifndef PCI_VENDOR_ID_DFI ++#define PCI_VENDOR_ID_DFI 0x106e ++#endif ++ + static struct snd_pci_quirk stac9200_cfg_tbl[] = { + /* SigmaTel reference board */ + SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, + "DFI LanParty", STAC_REF), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, ++ "DFI LanParty", STAC_REF), + /* Dell laptops have BIOS problem */ + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01a8, + "unknown Dell", STAC_9200_DELL_D21), +@@ -1597,6 +1497,7 @@ static unsigned int *stac925x_brd_tbl[ST + }; + + static const char *stac925x_models[STAC_925x_MODELS] = { ++ [STAC_925x_AUTO] = "auto", + [STAC_REF] = "ref", + [STAC_M1] = "m1", + [STAC_M1_2] = "m1-2", +@@ -1624,6 +1525,7 @@ static struct snd_pci_quirk stac925x_cod + static struct snd_pci_quirk stac925x_cfg_tbl[] = { + /* SigmaTel reference board */ + SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, "DFI LanParty", STAC_REF), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, "DFI LanParty", STAC_REF), + SND_PCI_QUIRK(0x8384, 0x7632, "Stac9202 Reference Board", STAC_REF), + + /* Default table for unknown ID */ +@@ -1655,6 +1557,7 @@ static unsigned int *stac92hd73xx_brd_tb + }; + + static const char *stac92hd73xx_models[STAC_92HD73XX_MODELS] = { ++ [STAC_92HD73XX_AUTO] = "auto", + [STAC_92HD73XX_NO_JD] = "no-jd", + [STAC_92HD73XX_REF] = "ref", + [STAC_DELL_M6_AMIC] = "dell-m6-amic", +@@ -1667,6 +1570,8 @@ static struct snd_pci_quirk stac92hd73xx + /* SigmaTel reference board */ + SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, + "DFI LanParty", STAC_92HD73XX_REF), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, ++ "DFI LanParty", STAC_92HD73XX_REF), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0254, + "Dell Studio 1535", STAC_DELL_M6_DMIC), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0255, +@@ -1687,55 +1592,73 @@ static struct snd_pci_quirk stac92hd73xx + "Dell Studio 1537", STAC_DELL_M6_DMIC), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02a0, + "Dell Studio 17", STAC_DELL_M6_DMIC), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02be, ++ "Dell Studio 1555", STAC_DELL_M6_DMIC), + {} /* terminator */ + }; + +-static unsigned int ref92hd83xxx_pin_configs[14] = { ++static unsigned int ref92hd83xxx_pin_configs[10] = { + 0x02214030, 0x02211010, 0x02a19020, 0x02170130, + 0x01014050, 0x01819040, 0x01014020, 0x90a3014e, +- 0x40f000f0, 0x40f000f0, 0x40f000f0, 0x40f000f0, + 0x01451160, 0x98560170, + }; + ++static unsigned int dell_s14_pin_configs[10] = { ++ 0x02214030, 0x02211010, 0x02a19020, 0x01014050, ++ 0x40f000f0, 0x01819040, 0x40f000f0, 0x90a60160, ++ 0x40f000f0, 0x40f000f0, ++}; ++ + static unsigned int *stac92hd83xxx_brd_tbl[STAC_92HD83XXX_MODELS] = { + [STAC_92HD83XXX_REF] = ref92hd83xxx_pin_configs, + [STAC_92HD83XXX_PWR_REF] = ref92hd83xxx_pin_configs, ++ [STAC_DELL_S14] = dell_s14_pin_configs, + }; + + static const char *stac92hd83xxx_models[STAC_92HD83XXX_MODELS] = { ++ [STAC_92HD83XXX_AUTO] = "auto", + [STAC_92HD83XXX_REF] = "ref", + [STAC_92HD83XXX_PWR_REF] = "mic-ref", ++ [STAC_DELL_S14] = "dell-s14", + }; + + static struct snd_pci_quirk stac92hd83xxx_cfg_tbl[] = { + /* SigmaTel reference board */ + SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, + "DFI LanParty", STAC_92HD83XXX_REF), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, ++ "DFI LanParty", STAC_92HD83XXX_REF), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02ba, ++ "unknown Dell", STAC_DELL_S14), + {} /* terminator */ + }; + +-static unsigned int ref92hd71bxx_pin_configs[11] = { ++static unsigned int ref92hd71bxx_pin_configs[STAC92HD71BXX_NUM_PINS] = { + 0x02214030, 0x02a19040, 0x01a19020, 0x01014010, + 0x0181302e, 0x01014010, 0x01019020, 0x90a000f0, +- 0x90a000f0, 0x01452050, 0x01452050, ++ 0x90a000f0, 0x01452050, 0x01452050, 0x00000000, ++ 0x00000000 + }; + +-static unsigned int dell_m4_1_pin_configs[11] = { ++static unsigned int dell_m4_1_pin_configs[STAC92HD71BXX_NUM_PINS] = { + 0x0421101f, 0x04a11221, 0x40f000f0, 0x90170110, + 0x23a1902e, 0x23014250, 0x40f000f0, 0x90a000f0, +- 0x40f000f0, 0x4f0000f0, 0x4f0000f0, ++ 0x40f000f0, 0x4f0000f0, 0x4f0000f0, 0x00000000, ++ 0x00000000 + }; + +-static unsigned int dell_m4_2_pin_configs[11] = { ++static unsigned int dell_m4_2_pin_configs[STAC92HD71BXX_NUM_PINS] = { + 0x0421101f, 0x04a11221, 0x90a70330, 0x90170110, + 0x23a1902e, 0x23014250, 0x40f000f0, 0x40f000f0, +- 0x40f000f0, 0x044413b0, 0x044413b0, ++ 0x40f000f0, 0x044413b0, 0x044413b0, 0x00000000, ++ 0x00000000 + }; + +-static unsigned int dell_m4_3_pin_configs[11] = { ++static unsigned int dell_m4_3_pin_configs[STAC92HD71BXX_NUM_PINS] = { + 0x0421101f, 0x04a11221, 0x90a70330, 0x90170110, + 0x40f000f0, 0x40f000f0, 0x40f000f0, 0x90a000f0, +- 0x40f000f0, 0x044413b0, 0x044413b0, ++ 0x40f000f0, 0x044413b0, 0x044413b0, 0x00000000, ++ 0x00000000 + }; + + static unsigned int *stac92hd71bxx_brd_tbl[STAC_92HD71BXX_MODELS] = { +@@ -1745,39 +1668,44 @@ static unsigned int *stac92hd71bxx_brd_t + [STAC_DELL_M4_3] = dell_m4_3_pin_configs, + [STAC_HP_M4] = NULL, + [STAC_HP_DV5] = NULL, ++ [STAC_HP_HDX] = NULL, ++ [STAC_HP_DV4_1222NR] = NULL, + }; + + static const char *stac92hd71bxx_models[STAC_92HD71BXX_MODELS] = { ++ [STAC_92HD71BXX_AUTO] = "auto", + [STAC_92HD71BXX_REF] = "ref", + [STAC_DELL_M4_1] = "dell-m4-1", + [STAC_DELL_M4_2] = "dell-m4-2", + [STAC_DELL_M4_3] = "dell-m4-3", + [STAC_HP_M4] = "hp-m4", + [STAC_HP_DV5] = "hp-dv5", ++ [STAC_HP_HDX] = "hp-hdx", ++ [STAC_HP_DV4_1222NR] = "hp-dv4-1222nr", + }; + + static struct snd_pci_quirk stac92hd71bxx_cfg_tbl[] = { + /* SigmaTel reference board */ + SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, + "DFI LanParty", STAC_92HD71BXX_REF), +- SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x308c, +- "HP", STAC_HP_DV5), +- SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x308d, ++ SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, ++ "DFI LanParty", STAC_92HD71BXX_REF), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x30fb, ++ "HP dv4-1222nr", STAC_HP_DV4_1222NR), ++ SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_HP, 0xfff0, 0x3080, + "HP", STAC_HP_DV5), +- SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x30f2, +- "HP dv5", STAC_HP_DV5), +- SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x30f4, +- "HP dv7", STAC_HP_DV5), +- SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x30f7, +- "HP dv4", STAC_HP_DV5), +- SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x30fc, +- "HP dv7", STAC_HP_DV5), +- SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x3600, +- "HP dv5", STAC_HP_DV5), +- SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x3603, +- "HP dv5", STAC_HP_DV5), ++ SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_HP, 0xfff0, 0x30f0, ++ "HP dv4-7", STAC_HP_DV5), ++ SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_HP, 0xfff0, 0x3600, ++ "HP dv4-7", STAC_HP_DV5), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x3610, ++ "HP HDX", STAC_HP_HDX), /* HDX18 */ + SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x361a, +- "unknown HP", STAC_HP_M4), ++ "HP mini 1000", STAC_HP_M4), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x361b, ++ "HP HDX", STAC_HP_HDX), /* HDX16 */ ++ SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_HP, 0xfff0, 0x7010, ++ "HP", STAC_HP_DV5), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0233, + "unknown Dell", STAC_DELL_M4_1), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0234, +@@ -1929,6 +1857,7 @@ static unsigned int *stac922x_brd_tbl[ST + }; + + static const char *stac922x_models[STAC_922X_MODELS] = { ++ [STAC_922X_AUTO] = "auto", + [STAC_D945_REF] = "ref", + [STAC_D945GTP5] = "5stack", + [STAC_D945GTP3] = "3stack", +@@ -1956,6 +1885,8 @@ static struct snd_pci_quirk stac922x_cfg + /* SigmaTel reference board */ + SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, + "DFI LanParty", STAC_D945_REF), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, ++ "DFI LanParty", STAC_D945_REF), + /* Intel 945G based systems */ + SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0101, + "Intel D945G", STAC_D945GTP3), +@@ -2036,31 +1967,7 @@ static struct snd_pci_quirk stac922x_cfg + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d7, + "Dell XPS M1210", STAC_922X_DELL_M82), + /* ECS/PC Chips boards */ +- SND_PCI_QUIRK(0x1019, 0x2144, +- "ECS/PC chips", STAC_ECS_202), +- SND_PCI_QUIRK(0x1019, 0x2608, +- "ECS/PC chips", STAC_ECS_202), +- SND_PCI_QUIRK(0x1019, 0x2633, +- "ECS/PC chips P17G/1333", STAC_ECS_202), +- SND_PCI_QUIRK(0x1019, 0x2811, +- "ECS/PC chips", STAC_ECS_202), +- SND_PCI_QUIRK(0x1019, 0x2812, +- "ECS/PC chips", STAC_ECS_202), +- SND_PCI_QUIRK(0x1019, 0x2813, +- "ECS/PC chips", STAC_ECS_202), +- SND_PCI_QUIRK(0x1019, 0x2814, +- "ECS/PC chips", STAC_ECS_202), +- SND_PCI_QUIRK(0x1019, 0x2815, +- "ECS/PC chips", STAC_ECS_202), +- SND_PCI_QUIRK(0x1019, 0x2816, +- "ECS/PC chips", STAC_ECS_202), +- SND_PCI_QUIRK(0x1019, 0x2817, +- "ECS/PC chips", STAC_ECS_202), +- SND_PCI_QUIRK(0x1019, 0x2818, +- "ECS/PC chips", STAC_ECS_202), +- SND_PCI_QUIRK(0x1019, 0x2819, +- "ECS/PC chips", STAC_ECS_202), +- SND_PCI_QUIRK(0x1019, 0x2820, ++ SND_PCI_QUIRK_MASK(0x1019, 0xf000, 0x2000, + "ECS/PC chips", STAC_ECS_202), + {} /* terminator */ + }; +@@ -2086,6 +1993,13 @@ static unsigned int d965_5st_pin_configs + 0x40000100, 0x40000100 + }; + ++static unsigned int d965_5st_no_fp_pin_configs[14] = { ++ 0x40000100, 0x40000100, 0x0181304e, 0x01014010, ++ 0x01a19040, 0x01011012, 0x01016011, 0x40000100, ++ 0x40000100, 0x40000100, 0x40000100, 0x01442070, ++ 0x40000100, 0x40000100 ++}; ++ + static unsigned int dell_3st_pin_configs[14] = { + 0x02211230, 0x02a11220, 0x01a19040, 0x01114210, + 0x01111212, 0x01116211, 0x01813050, 0x01112214, +@@ -2098,15 +2012,18 @@ static unsigned int *stac927x_brd_tbl[ST + [STAC_D965_REF] = ref927x_pin_configs, + [STAC_D965_3ST] = d965_3st_pin_configs, + [STAC_D965_5ST] = d965_5st_pin_configs, ++ [STAC_D965_5ST_NO_FP] = d965_5st_no_fp_pin_configs, + [STAC_DELL_3ST] = dell_3st_pin_configs, + [STAC_DELL_BIOS] = NULL, + }; + + static const char *stac927x_models[STAC_927X_MODELS] = { ++ [STAC_927X_AUTO] = "auto", + [STAC_D965_REF_NO_JD] = "ref-no-jd", + [STAC_D965_REF] = "ref", + [STAC_D965_3ST] = "3stack", + [STAC_D965_5ST] = "5stack", ++ [STAC_D965_5ST_NO_FP] = "5stack-no-fp", + [STAC_DELL_3ST] = "dell-3stack", + [STAC_DELL_BIOS] = "dell-bios", + }; +@@ -2115,26 +2032,16 @@ static struct snd_pci_quirk stac927x_cfg + /* SigmaTel reference board */ + SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, + "DFI LanParty", STAC_D965_REF), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, ++ "DFI LanParty", STAC_D965_REF), + /* Intel 946 based systems */ + SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x3d01, "Intel D946", STAC_D965_3ST), + SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0xa301, "Intel D946", STAC_D965_3ST), + /* 965 based 3 stack systems */ +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2116, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2115, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2114, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2113, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2112, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2111, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2110, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2009, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2008, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2007, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2006, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2005, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2004, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2003, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2002, "Intel D965", STAC_D965_3ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2001, "Intel D965", STAC_D965_3ST), ++ SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_INTEL, 0xff00, 0x2100, ++ "Intel D965", STAC_D965_3ST), ++ SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_INTEL, 0xff00, 0x2000, ++ "Intel D965", STAC_D965_3ST), + /* Dell 3 stack systems */ + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f7, "Dell XPS M1730", STAC_DELL_3ST), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01dd, "Dell Dimension E520", STAC_DELL_3ST), +@@ -2144,21 +2051,16 @@ static struct snd_pci_quirk stac927x_cfg + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f3, "Dell Inspiron 1420", STAC_DELL_BIOS), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0227, "Dell Vostro 1400 ", STAC_DELL_BIOS), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x022e, "Dell ", STAC_DELL_BIOS), +- SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x022f, "Dell Inspiron 1525", STAC_DELL_3ST), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x022f, "Dell Inspiron 1525", STAC_DELL_BIOS), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0242, "Dell ", STAC_DELL_BIOS), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0243, "Dell ", STAC_DELL_BIOS), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02ff, "Dell ", STAC_DELL_BIOS), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0209, "Dell XPS 1330", STAC_DELL_BIOS), + /* 965 based 5 stack systems */ +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2301, "Intel D965", STAC_D965_5ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2302, "Intel D965", STAC_D965_5ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2303, "Intel D965", STAC_D965_5ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2304, "Intel D965", STAC_D965_5ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2305, "Intel D965", STAC_D965_5ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2501, "Intel D965", STAC_D965_5ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2502, "Intel D965", STAC_D965_5ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2503, "Intel D965", STAC_D965_5ST), +- SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2504, "Intel D965", STAC_D965_5ST), ++ SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_INTEL, 0xff00, 0x2300, ++ "Intel D965", STAC_D965_5ST), ++ SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_INTEL, 0xff00, 0x2500, ++ "Intel D965", STAC_D965_5ST), + {} /* terminator */ + }; + +@@ -2215,6 +2117,7 @@ static unsigned int *stac9205_brd_tbl[ST + }; + + static const char *stac9205_models[STAC_9205_MODELS] = { ++ [STAC_9205_AUTO] = "auto", + [STAC_9205_REF] = "ref", + [STAC_9205_DELL_M42] = "dell-m42", + [STAC_9205_DELL_M43] = "dell-m43", +@@ -2226,6 +2129,10 @@ static struct snd_pci_quirk stac9205_cfg + /* SigmaTel reference board */ + SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, + "DFI LanParty", STAC_9205_REF), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0xfb30, ++ "SigmaTel", STAC_9205_REF), ++ SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, ++ "DFI LanParty", STAC_9205_REF), + /* Dell */ + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f1, + "unknown Dell", STAC_9205_DELL_M42), +@@ -2258,6 +2165,7 @@ static struct snd_pci_quirk stac9205_cfg + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0228, + "Dell Vostro 1500", STAC_9205_DELL_M42), + /* Gateway */ ++ SND_PCI_QUIRK(0x107b, 0x0560, "Gateway T6834c", STAC_9205_EAPD), + SND_PCI_QUIRK(0x107b, 0x0565, "Gateway T1616", STAC_9205_EAPD), + {} /* terminator */ + }; +@@ -2515,10 +2423,18 @@ static int stac92xx_build_pcms(struct hd + return 0; + } + +-static unsigned int stac92xx_get_vref(struct hda_codec *codec, hda_nid_t nid) ++#define snd_hda_query_pin_caps(codec, nid) \ ++ snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP) ++#define snd_hda_codec_get_pincfg(codec, nid) \ ++ snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONFIG_DEFAULT, 0) ++#define snd_hda_codec_set_pincfg(codec, nid, val) \ ++ stac92xx_set_config_reg(codec, nid, val) ++#define get_wcaps_type(wcaps) (((wcaps) & AC_WCAP_TYPE) >> AC_WCAP_TYPE_SHIFT) ++ ++static unsigned int stac92xx_get_default_vref(struct hda_codec *codec, ++ hda_nid_t nid) + { +- unsigned int pincap = snd_hda_param_read(codec, nid, +- AC_PAR_PIN_CAP); ++ unsigned int pincap = snd_hda_query_pin_caps(codec, nid); + pincap = (pincap & AC_PINCAP_VREF) >> AC_PINCAP_VREF_SHIFT; + if (pincap & AC_PINCAP_VREF_100) + return AC_PINCTL_VREF_100; +@@ -2550,8 +2466,7 @@ static int stac92xx_hp_switch_get(struct + return 0; + } + +-static void stac_issue_unsol_event(struct hda_codec *codec, hda_nid_t nid, +- unsigned char type); ++static void stac_issue_unsol_event(struct hda_codec *codec, hda_nid_t nid); + + static int stac92xx_hp_switch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +@@ -2559,25 +2474,119 @@ static int stac92xx_hp_switch_put(struct + struct hda_codec *codec = snd_kcontrol_chip(kcontrol); + struct sigmatel_spec *spec = codec->spec; + int nid = kcontrol->private_value; +- ++ + spec->hp_switch = ucontrol->value.integer.value[0] ? nid : 0; + + /* check to be sure that the ports are upto date with + * switch changes + */ +- stac_issue_unsol_event(codec, nid, STAC_HP_EVENT); ++ stac_issue_unsol_event(codec, nid); ++ + return 1; + } + +-#define stac92xx_io_switch_info snd_ctl_boolean_mono_info ++static int stac92xx_dc_bias_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ int i; ++ static char *texts[] = { ++ "Mic In", "Line In", "Line Out" ++ }; ++ ++ struct hda_codec *codec = snd_kcontrol_chip(kcontrol); ++ struct sigmatel_spec *spec = codec->spec; ++ hda_nid_t nid = kcontrol->private_value; ++ ++ if (nid == spec->mic_switch || nid == spec->line_switch) ++ i = 3; ++ else ++ i = 2; ++ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; ++ uinfo->value.enumerated.items = i; ++ uinfo->count = 1; ++ if (uinfo->value.enumerated.item >= i) ++ uinfo->value.enumerated.item = i-1; ++ strcpy(uinfo->value.enumerated.name, ++ texts[uinfo->value.enumerated.item]); ++ ++ return 0; ++} ++ ++static int stac92xx_dc_bias_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct hda_codec *codec = snd_kcontrol_chip(kcontrol); ++ hda_nid_t nid = kcontrol->private_value; ++ unsigned int vref = stac92xx_vref_get(codec, nid); ++ ++ if (vref == stac92xx_get_default_vref(codec, nid)) ++ ucontrol->value.enumerated.item[0] = 0; ++ else if (vref == AC_PINCTL_VREF_GRD) ++ ucontrol->value.enumerated.item[0] = 1; ++ else if (vref == AC_PINCTL_VREF_HIZ) ++ ucontrol->value.enumerated.item[0] = 2; ++ ++ return 0; ++} ++ ++static int stac92xx_dc_bias_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct hda_codec *codec = snd_kcontrol_chip(kcontrol); ++ unsigned int new_vref = 0; ++ int error; ++ hda_nid_t nid = kcontrol->private_value; ++ ++ if (ucontrol->value.enumerated.item[0] == 0) ++ new_vref = stac92xx_get_default_vref(codec, nid); ++ else if (ucontrol->value.enumerated.item[0] == 1) ++ new_vref = AC_PINCTL_VREF_GRD; ++ else if (ucontrol->value.enumerated.item[0] == 2) ++ new_vref = AC_PINCTL_VREF_HIZ; ++ else ++ return 0; ++ ++ if (new_vref != stac92xx_vref_get(codec, nid)) { ++ error = stac92xx_vref_set(codec, nid, new_vref); ++ return error; ++ } ++ ++ return 0; ++} ++ ++static int stac92xx_io_switch_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ static char *texts[2]; ++ struct hda_codec *codec = snd_kcontrol_chip(kcontrol); ++ struct sigmatel_spec *spec = codec->spec; ++ ++ if (kcontrol->private_value == spec->line_switch) ++ texts[0] = "Line In"; ++ else ++ texts[0] = "Mic In"; ++ texts[1] = "Line Out"; ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; ++ uinfo->value.enumerated.items = 2; ++ uinfo->count = 1; ++ ++ if (uinfo->value.enumerated.item >= 2) ++ uinfo->value.enumerated.item = 1; ++ strcpy(uinfo->value.enumerated.name, ++ texts[uinfo->value.enumerated.item]); ++ ++ return 0; ++} + + static int stac92xx_io_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) + { + struct hda_codec *codec = snd_kcontrol_chip(kcontrol); + struct sigmatel_spec *spec = codec->spec; +- int io_idx = kcontrol-> private_value & 0xff; ++ hda_nid_t nid = kcontrol->private_value; ++ int io_idx = (nid == spec->mic_switch) ? 1 : 0; + +- ucontrol->value.integer.value[0] = spec->io_switch[io_idx]; ++ ucontrol->value.enumerated.item[0] = spec->io_switch[io_idx]; + return 0; + } + +@@ -2585,9 +2594,9 @@ static int stac92xx_io_switch_put(struct + { + struct hda_codec *codec = snd_kcontrol_chip(kcontrol); + struct sigmatel_spec *spec = codec->spec; +- hda_nid_t nid = kcontrol->private_value >> 8; +- int io_idx = kcontrol-> private_value & 0xff; +- unsigned short val = !!ucontrol->value.integer.value[0]; ++ hda_nid_t nid = kcontrol->private_value; ++ int io_idx = (nid == spec->mic_switch) ? 1 : 0; ++ unsigned short val = !!ucontrol->value.enumerated.item[0]; + + spec->io_switch[io_idx] = val; + +@@ -2596,7 +2605,7 @@ static int stac92xx_io_switch_put(struct + else { + unsigned int pinctl = AC_PINCTL_IN_EN; + if (io_idx) /* set VREF for mic */ +- pinctl |= stac92xx_get_vref(codec, nid); ++ pinctl |= stac92xx_get_default_vref(codec, nid); + stac92xx_auto_set_pinctl(codec, nid, pinctl); + } + +@@ -2604,7 +2613,7 @@ static int stac92xx_io_switch_put(struct + * appropriately according to the pin direction + */ + if (spec->hp_detect) +- stac_issue_unsol_event(codec, nid, STAC_HP_EVENT); ++ stac_issue_unsol_event(codec, nid); + + return 1; + } +@@ -2677,7 +2686,8 @@ enum { + STAC_CTL_WIDGET_AMP_VOL, + STAC_CTL_WIDGET_HP_SWITCH, + STAC_CTL_WIDGET_IO_SWITCH, +- STAC_CTL_WIDGET_CLFE_SWITCH ++ STAC_CTL_WIDGET_CLFE_SWITCH, ++ STAC_CTL_WIDGET_DC_BIAS + }; + + static struct snd_kcontrol_new stac92xx_control_templates[] = { +@@ -2689,43 +2699,47 @@ static struct snd_kcontrol_new stac92xx_ + STAC_CODEC_HP_SWITCH(NULL), + STAC_CODEC_IO_SWITCH(NULL, 0), + STAC_CODEC_CLFE_SWITCH(NULL, 0), ++ DC_BIAS(NULL, 0, 0), + }; + + /* add dynamic controls */ +-static int stac92xx_add_control_temp(struct sigmatel_spec *spec, +- struct snd_kcontrol_new *ktemp, +- int idx, const char *name, +- unsigned long val) ++static struct snd_kcontrol_new * ++stac_control_new(struct sigmatel_spec *spec, ++ struct snd_kcontrol_new *ktemp, ++ const char *name) + { + struct snd_kcontrol_new *knew; + +- if (spec->num_kctl_used >= spec->num_kctl_alloc) { +- int num = spec->num_kctl_alloc + NUM_CONTROL_ALLOC; +- +- knew = kcalloc(num + 1, sizeof(*knew), GFP_KERNEL); /* array + terminator */ +- if (! knew) +- return -ENOMEM; +- if (spec->kctl_alloc) { +- memcpy(knew, spec->kctl_alloc, sizeof(*knew) * spec->num_kctl_alloc); +- kfree(spec->kctl_alloc); +- } +- spec->kctl_alloc = knew; +- spec->num_kctl_alloc = num; +- } +- +- knew = &spec->kctl_alloc[spec->num_kctl_used]; ++ snd_array_init(&spec->kctls, sizeof(*knew), 32); ++ knew = snd_array_new(&spec->kctls); ++ if (!knew) ++ return NULL; + *knew = *ktemp; +- knew->index = idx; + knew->name = kstrdup(name, GFP_KERNEL); +- if (!knew->name) +- return -ENOMEM; +- knew->private_value = val; +- spec->num_kctl_used++; +- return 0; ++ if (!knew->name) { ++ /* roolback */ ++ memset(knew, 0, sizeof(*knew)); ++ spec->kctls.alloced--; ++ return NULL; ++ } ++ return knew; + } + +-static inline int stac92xx_add_control_idx(struct sigmatel_spec *spec, +- int type, int idx, const char *name, ++static int stac92xx_add_control_temp(struct sigmatel_spec *spec, ++ struct snd_kcontrol_new *ktemp, ++ int idx, const char *name, ++ unsigned long val) ++{ ++ struct snd_kcontrol_new *knew = stac_control_new(spec, ktemp, name); ++ if (!knew) ++ return -ENOMEM; ++ knew->index = idx; ++ knew->private_value = val; ++ return 0; ++} ++ ++static inline int stac92xx_add_control_idx(struct sigmatel_spec *spec, ++ int type, int idx, const char *name, + unsigned long val) + { + return stac92xx_add_control_temp(spec, +@@ -2741,6 +2755,59 @@ static inline int stac92xx_add_control(s + return stac92xx_add_control_idx(spec, type, 0, name, val); + } + ++static struct snd_kcontrol_new stac_input_src_temp = { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "Input Source", ++ .info = stac92xx_mux_enum_info, ++ .get = stac92xx_mux_enum_get, ++ .put = stac92xx_mux_enum_put, ++}; ++ ++static inline int stac92xx_add_jack_mode_control(struct hda_codec *codec, ++ hda_nid_t nid, int idx) ++{ ++ int def_conf = snd_hda_codec_get_pincfg(codec, nid); ++ int control = 0; ++ struct sigmatel_spec *spec = codec->spec; ++ char name[22]; ++ ++ if (!((get_defcfg_connect(def_conf)) & AC_JACK_PORT_FIXED)) { ++ if (stac92xx_get_default_vref(codec, nid) == AC_PINCTL_VREF_GRD ++ && nid == spec->line_switch) ++ control = STAC_CTL_WIDGET_IO_SWITCH; ++ else if (snd_hda_query_pin_caps(codec, nid) ++ & (AC_PINCAP_VREF_GRD << AC_PINCAP_VREF_SHIFT)) ++ control = STAC_CTL_WIDGET_DC_BIAS; ++ else if (nid == spec->mic_switch) ++ control = STAC_CTL_WIDGET_IO_SWITCH; ++ } ++ ++ if (control) { ++ strcpy(name, auto_pin_cfg_labels[idx]); ++ return stac92xx_add_control(codec->spec, control, ++ strcat(name, " Jack Mode"), nid); ++ } ++ ++ return 0; ++} ++ ++static int stac92xx_add_input_source(struct sigmatel_spec *spec) ++{ ++ struct snd_kcontrol_new *knew; ++ struct hda_input_mux *imux = &spec->private_imux; ++ ++ if (spec->auto_mic) ++ return 0; /* no need for input source */ ++ if (!spec->num_adcs || imux->num_items <= 1) ++ return 0; /* no need for input source control */ ++ knew = stac_control_new(spec, &stac_input_src_temp, ++ stac_input_src_temp.name); ++ if (!knew) ++ return -ENOMEM; ++ knew->count = spec->num_adcs; ++ return 0; ++} ++ + /* check whether the line-input can be used as line-out */ + static hda_nid_t check_line_out_switch(struct hda_codec *codec) + { +@@ -2752,7 +2819,7 @@ static hda_nid_t check_line_out_switch(s + if (cfg->line_out_type != AUTO_PIN_LINE_OUT) + return 0; + nid = cfg->input_pins[AUTO_PIN_LINE]; +- pincap = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP); ++ pincap = snd_hda_query_pin_caps(codec, nid); + if (pincap & AC_PINCAP_OUT) + return nid; + return 0; +@@ -2771,12 +2838,11 @@ static hda_nid_t check_mic_out_switch(st + mic_pin = AUTO_PIN_MIC; + for (;;) { + hda_nid_t nid = cfg->input_pins[mic_pin]; +- def_conf = snd_hda_codec_read(codec, nid, 0, +- AC_VERB_GET_CONFIG_DEFAULT, 0); ++ def_conf = snd_hda_codec_get_pincfg(codec, nid); + /* some laptops have an internal analog microphone + * which can't be used as a output */ + if (get_defcfg_connect(def_conf) != AC_JACK_PORT_FIXED) { +- pincap = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP); ++ pincap = snd_hda_query_pin_caps(codec, nid); + if (pincap & AC_PINCAP_OUT) + return nid; + } +@@ -2824,9 +2890,8 @@ static hda_nid_t get_unassigned_dac(stru + conn_len = snd_hda_get_connections(codec, nid, conn, + HDA_MAX_CONNECTIONS); + for (j = 0; j < conn_len; j++) { +- wcaps = snd_hda_param_read(codec, conn[j], +- AC_PAR_AUDIO_WIDGET_CAP); +- wtype = (wcaps & AC_WCAP_TYPE) >> AC_WCAP_TYPE_SHIFT; ++ wcaps = get_wcaps(codec, conn[j]); ++ wtype = get_wcaps_type(wcaps); + /* we check only analog outputs */ + if (wtype != AC_WID_AUD_OUT || (wcaps & AC_WCAP_DIGITAL)) + continue; +@@ -2840,6 +2905,16 @@ static hda_nid_t get_unassigned_dac(stru + return conn[j]; + } + } ++ /* if all DACs are already assigned, connect to the primary DAC */ ++ if (conn_len > 1) { ++ for (j = 0; j < conn_len; j++) { ++ if (conn[j] == spec->multiout.dac_nids[0]) { ++ snd_hda_codec_write_cache(codec, nid, 0, ++ AC_VERB_SET_CONNECT_SEL, j); ++ break; ++ } ++ } ++ } + return 0; + } + +@@ -2880,6 +2955,26 @@ static int stac92xx_auto_fill_dac_nids(s + add_spec_dacs(spec, dac); + } + ++ for (i = 0; i < cfg->hp_outs; i++) { ++ nid = cfg->hp_pins[i]; ++ dac = get_unassigned_dac(codec, nid); ++ if (dac) { ++ if (!spec->multiout.hp_nid) ++ spec->multiout.hp_nid = dac; ++ else ++ add_spec_extra_dacs(spec, dac); ++ } ++ spec->hp_dacs[i] = dac; ++ } ++ ++ for (i = 0; i < cfg->speaker_outs; i++) { ++ nid = cfg->speaker_pins[i]; ++ dac = get_unassigned_dac(codec, nid); ++ if (dac) ++ add_spec_extra_dacs(spec, dac); ++ spec->speaker_dacs[i] = dac; ++ } ++ + /* add line-in as output */ + nid = check_line_out_switch(codec); + if (nid) { +@@ -2907,26 +3002,6 @@ static int stac92xx_auto_fill_dac_nids(s + } + } + +- for (i = 0; i < cfg->hp_outs; i++) { +- nid = cfg->hp_pins[i]; +- dac = get_unassigned_dac(codec, nid); +- if (dac) { +- if (!spec->multiout.hp_nid) +- spec->multiout.hp_nid = dac; +- else +- add_spec_extra_dacs(spec, dac); +- } +- spec->hp_dacs[i] = dac; +- } +- +- for (i = 0; i < cfg->speaker_outs; i++) { +- nid = cfg->speaker_pins[i]; +- dac = get_unassigned_dac(codec, nid); +- if (dac) +- add_spec_extra_dacs(spec, dac); +- spec->speaker_dacs[i] = dac; +- } +- + snd_printd("stac92xx: dac_nids=%d (0x%x/0x%x/0x%x/0x%x/0x%x)\n", + spec->multiout.num_dacs, + spec->multiout.dac_nids[0], +@@ -2939,8 +3014,8 @@ static int stac92xx_auto_fill_dac_nids(s + } + + /* create volume control/switch for the given prefx type */ +-static int create_controls(struct hda_codec *codec, const char *pfx, +- hda_nid_t nid, int chs) ++static int create_controls_idx(struct hda_codec *codec, const char *pfx, ++ int idx, hda_nid_t nid, int chs) + { + struct sigmatel_spec *spec = codec->spec; + char name[32]; +@@ -2964,19 +3039,22 @@ static int create_controls(struct hda_co + } + + sprintf(name, "%s Playback Volume", pfx); +- err = stac92xx_add_control(spec, STAC_CTL_WIDGET_VOL, name, ++ err = stac92xx_add_control_idx(spec, STAC_CTL_WIDGET_VOL, idx, name, + HDA_COMPOSE_AMP_VAL_OFS(nid, chs, 0, HDA_OUTPUT, + spec->volume_offset)); + if (err < 0) + return err; + sprintf(name, "%s Playback Switch", pfx); +- err = stac92xx_add_control(spec, STAC_CTL_WIDGET_MUTE, name, ++ err = stac92xx_add_control_idx(spec, STAC_CTL_WIDGET_MUTE, idx, name, + HDA_COMPOSE_AMP_VAL(nid, chs, 0, HDA_OUTPUT)); + if (err < 0) + return err; + return 0; + } + ++#define create_controls(codec, pfx, nid, chs) \ ++ create_controls_idx(codec, pfx, 0, nid, chs) ++ + static int add_spec_dacs(struct sigmatel_spec *spec, hda_nid_t nid) + { + if (spec->multiout.num_dacs > 4) { +@@ -3014,12 +3092,6 @@ static int create_multi_out_ctls(struct + static const char *chname[4] = { + "Front", "Surround", NULL /*CLFE*/, "Side" + }; +- static const char *hp_pfxs[] = { +- "Headphone", "Headphone2", "Headphone3", "Headphone4" +- }; +- static const char *speaker_pfxs[] = { +- "Speaker", "External Speaker", "Speaker2", "Speaker3" +- }; + hda_nid_t nid; + int i, err; + unsigned int wid_caps; +@@ -3055,18 +3127,22 @@ static int create_multi_out_ctls(struct + + } else { + const char *name; ++ int idx; + switch (type) { + case AUTO_PIN_HP_OUT: +- name = hp_pfxs[i]; ++ name = "Headphone"; ++ idx = i; + break; + case AUTO_PIN_SPEAKER_OUT: +- name = speaker_pfxs[i]; ++ name = "Speaker"; ++ idx = i; + break; + default: + name = chname[i]; ++ idx = 0; + break; + } +- err = create_controls(codec, name, nid, 3); ++ err = create_controls_idx(codec, name, idx, nid, 3); + if (err < 0) + return err; + } +@@ -3074,12 +3150,29 @@ static int create_multi_out_ctls(struct + return 0; + } + ++static int stac92xx_add_capvol_ctls(struct hda_codec *codec, unsigned long vol, ++ unsigned long sw, int idx) ++{ ++ int err; ++ err = stac92xx_add_control_idx(codec->spec, STAC_CTL_WIDGET_VOL, idx, ++ "Capture Volume", vol); ++ if (err < 0) ++ return err; ++ err = stac92xx_add_control_idx(codec->spec, STAC_CTL_WIDGET_MUTE, idx, ++ "Capture Switch", sw); ++ if (err < 0) ++ return err; ++ return 0; ++} ++ + /* add playback controls from the parsed DAC table */ + static int stac92xx_auto_create_multi_out_ctls(struct hda_codec *codec, + const struct auto_pin_cfg *cfg) + { + struct sigmatel_spec *spec = codec->spec; ++ hda_nid_t nid; + int err; ++ int idx; + + err = create_multi_out_ctls(codec, cfg->line_outs, cfg->line_out_pins, + spec->multiout.dac_nids, +@@ -3096,20 +3189,13 @@ static int stac92xx_auto_create_multi_ou + return err; + } + +- if (spec->line_switch) { +- err = stac92xx_add_control(spec, STAC_CTL_WIDGET_IO_SWITCH, +- "Line In as Output Switch", +- spec->line_switch << 8); +- if (err < 0) +- return err; +- } +- +- if (spec->mic_switch) { +- err = stac92xx_add_control(spec, STAC_CTL_WIDGET_IO_SWITCH, +- "Mic as Output Switch", +- (spec->mic_switch << 8) | 1); +- if (err < 0) +- return err; ++ for (idx = AUTO_PIN_MIC; idx <= AUTO_PIN_FRONT_LINE; idx++) { ++ nid = cfg->input_pins[idx]; ++ if (nid) { ++ err = stac92xx_add_jack_mode_control(codec, nid, idx); ++ if (err < 0) ++ return err; ++ } + } + + return 0; +@@ -3152,7 +3238,7 @@ static int stac92xx_auto_create_mono_out + spec->mono_nid, + con_lst, + HDA_MAX_NUM_INPUTS); +- if (!num_cons || num_cons > ARRAY_SIZE(stac92xx_mono_labels)) ++ if (num_cons <= 0 || num_cons > ARRAY_SIZE(stac92xx_mono_labels)) + return -EINVAL; + + for (i = 0; i < num_cons; i++) { +@@ -3265,19 +3351,33 @@ static int stac92xx_beep_switch_ctl(stru + static int stac92xx_auto_create_mux_input_ctls(struct hda_codec *codec) + { + struct sigmatel_spec *spec = codec->spec; +- int wcaps, nid, i, err = 0; ++ int i, j, err = 0; + + for (i = 0; i < spec->num_muxes; i++) { ++ hda_nid_t nid; ++ unsigned int wcaps; ++ unsigned long val; ++ + nid = spec->mux_nids[i]; + wcaps = get_wcaps(codec, nid); ++ if (!(wcaps & AC_WCAP_OUT_AMP)) ++ continue; + +- if (wcaps & AC_WCAP_OUT_AMP) { +- err = stac92xx_add_control_idx(spec, +- STAC_CTL_WIDGET_VOL, i, "Mux Capture Volume", +- HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT)); +- if (err < 0) +- return err; ++ /* check whether already the same control was created as ++ * normal Capture Volume. ++ */ ++ val = HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT); ++ for (j = 0; j < spec->num_caps; j++) { ++ if (spec->capvols[j] == val) ++ break; + } ++ if (j < spec->num_caps) ++ continue; ++ ++ err = stac92xx_add_control_idx(spec, STAC_CTL_WIDGET_VOL, i, ++ "Mux Capture Volume", val); ++ if (err < 0) ++ return err; + } + return 0; + }; +@@ -3298,7 +3398,7 @@ static int stac92xx_auto_create_spdif_mu + spec->smux_nids[0], + con_lst, + HDA_MAX_NUM_INPUTS); +- if (!num_cons) ++ if (num_cons <= 0) + return -EINVAL; + + if (!labels) +@@ -3319,105 +3419,214 @@ static const char *stac92xx_dmic_labels[ + "Digital Mic 3", "Digital Mic 4" + }; + ++static int get_connection_index(struct hda_codec *codec, hda_nid_t mux, ++ hda_nid_t nid) ++{ ++ hda_nid_t conn[HDA_MAX_NUM_INPUTS]; ++ int i, nums; ++ ++ nums = snd_hda_get_connections(codec, mux, conn, ARRAY_SIZE(conn)); ++ for (i = 0; i < nums; i++) ++ if (conn[i] == nid) ++ return i; ++ return -1; ++} ++ ++/* create a volume assigned to the given pin (only if supported) */ ++static int create_elem_capture_vol(struct hda_codec *codec, hda_nid_t nid, ++ const char *label) ++{ ++ unsigned int caps, nums; ++ char name[32]; ++ ++ if (!(get_wcaps(codec, nid) & AC_WCAP_IN_AMP)) ++ return 0; ++ caps = query_amp_caps(codec, nid, HDA_OUTPUT); ++ nums = (caps & AC_AMPCAP_NUM_STEPS) >> AC_AMPCAP_NUM_STEPS_SHIFT; ++ if (!nums) ++ return 0; ++ snprintf(name, sizeof(name), "%s Capture Volume", label); ++ return stac92xx_add_control(codec->spec, STAC_CTL_WIDGET_VOL, name, ++ HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_INPUT)); ++} ++ + /* create playback/capture controls for input pins on dmic capable codecs */ + static int stac92xx_auto_create_dmic_input_ctls(struct hda_codec *codec, + const struct auto_pin_cfg *cfg) + { + struct sigmatel_spec *spec = codec->spec; ++ struct hda_input_mux *imux = &spec->private_imux; + struct hda_input_mux *dimux = &spec->private_dimux; +- hda_nid_t con_lst[HDA_MAX_NUM_INPUTS]; +- int err, i, j; +- char name[32]; ++ int err, i, active_mics; ++ unsigned int def_conf; + + dimux->items[dimux->num_items].label = stac92xx_dmic_labels[0]; + dimux->items[dimux->num_items].index = 0; + dimux->num_items++; + ++ active_mics = 0; ++ for (i = 0; i < spec->num_dmics; i++) { ++ /* check the validity: sometimes it's a dead vendor-spec node */ ++ if (get_wcaps_type(get_wcaps(codec, spec->dmic_nids[i])) ++ != AC_WID_PIN) ++ continue; ++ def_conf = snd_hda_codec_get_pincfg(codec, spec->dmic_nids[i]); ++ if (get_defcfg_connect(def_conf) != AC_JACK_PORT_NONE) ++ active_mics++; ++ } ++ + for (i = 0; i < spec->num_dmics; i++) { + hda_nid_t nid; + int index; +- int num_cons; +- unsigned int wcaps; +- unsigned int def_conf; ++ const char *label; + +- def_conf = snd_hda_codec_read(codec, +- spec->dmic_nids[i], +- 0, +- AC_VERB_GET_CONFIG_DEFAULT, +- 0); ++ nid = spec->dmic_nids[i]; ++ if (get_wcaps_type(get_wcaps(codec, nid)) != AC_WID_PIN) ++ continue; ++ def_conf = snd_hda_codec_get_pincfg(codec, nid); + if (get_defcfg_connect(def_conf) == AC_JACK_PORT_NONE) + continue; + +- nid = spec->dmic_nids[i]; +- num_cons = snd_hda_get_connections(codec, +- spec->dmux_nids[0], +- con_lst, +- HDA_MAX_NUM_INPUTS); +- for (j = 0; j < num_cons; j++) +- if (con_lst[j] == nid) { +- index = j; +- goto found; +- } +- continue; +-found: +- wcaps = get_wcaps(codec, nid) & +- (AC_WCAP_OUT_AMP | AC_WCAP_IN_AMP); ++ index = get_connection_index(codec, spec->dmux_nids[0], nid); ++ if (index < 0) ++ continue; + +- if (wcaps) { +- sprintf(name, "%s Capture Volume", +- stac92xx_dmic_labels[dimux->num_items]); +- +- err = stac92xx_add_control(spec, +- STAC_CTL_WIDGET_VOL, +- name, +- HDA_COMPOSE_AMP_VAL(nid, 3, 0, +- (wcaps & AC_WCAP_OUT_AMP) ? +- HDA_OUTPUT : HDA_INPUT)); +- if (err < 0) +- return err; +- } ++ if (active_mics == 1) ++ label = "Digital Mic"; ++ else ++ label = stac92xx_dmic_labels[dimux->num_items]; + +- dimux->items[dimux->num_items].label = +- stac92xx_dmic_labels[dimux->num_items]; ++ err = create_elem_capture_vol(codec, nid, label); ++ if (err < 0) ++ return err; ++ ++ dimux->items[dimux->num_items].label = label; + dimux->items[dimux->num_items].index = index; + dimux->num_items++; ++ ++ imux->items[imux->num_items].label = label; ++ imux->items[imux->num_items].index = index; ++ imux->num_items++; ++ } ++ ++ return 0; ++} ++ ++static int check_mic_pin(struct hda_codec *codec, hda_nid_t nid, ++ hda_nid_t *fixed, hda_nid_t *ext) ++{ ++ unsigned int cfg; ++ ++ if (!nid) ++ return 0; ++ cfg = snd_hda_codec_get_pincfg(codec, nid); ++ switch (get_defcfg_connect(cfg)) { ++ case AC_JACK_PORT_FIXED: ++ if (*fixed) ++ return 1; /* already occupied */ ++ *fixed = nid; ++ break; ++ case AC_JACK_PORT_COMPLEX: ++ if (*ext) ++ return 1; /* already occupied */ ++ *ext = nid; ++ break; + } ++ return 0; ++} ++ ++static int set_mic_route(struct hda_codec *codec, ++ struct sigmatel_mic_route *mic, ++ hda_nid_t pin) ++{ ++ struct sigmatel_spec *spec = codec->spec; ++ struct auto_pin_cfg *cfg = &spec->autocfg; ++ int i; + ++ mic->pin = pin; ++ for (i = AUTO_PIN_MIC; i <= AUTO_PIN_FRONT_MIC; i++) ++ if (pin == cfg->input_pins[i]) ++ break; ++ if (i <= AUTO_PIN_FRONT_MIC) { ++ /* analog pin */ ++ mic->dmux_idx = 0; ++ i = get_connection_index(codec, spec->mux_nids[0], pin); ++ if (i < 0) ++ return -1; ++ mic->mux_idx = i; ++ } else if (spec->dmux_nids) { ++ /* digital pin */ ++ mic->mux_idx = 0; ++ i = get_connection_index(codec, spec->dmux_nids[0], pin); ++ if (i < 0) ++ return -1; ++ mic->dmux_idx = i; ++ } + return 0; + } + ++/* return non-zero if the device is for automatic mic switch */ ++static int stac_check_auto_mic(struct hda_codec *codec) ++{ ++ struct sigmatel_spec *spec = codec->spec; ++ struct auto_pin_cfg *cfg = &spec->autocfg; ++ hda_nid_t fixed, ext; ++ int i; ++ ++ for (i = AUTO_PIN_LINE; i < AUTO_PIN_LAST; i++) { ++ if (cfg->input_pins[i]) ++ return 0; /* must be exclusively mics */ ++ } ++ fixed = ext = 0; ++ for (i = AUTO_PIN_MIC; i <= AUTO_PIN_FRONT_MIC; i++) ++ if (check_mic_pin(codec, cfg->input_pins[i], &fixed, &ext)) ++ return 0; ++ for (i = 0; i < spec->num_dmics; i++) ++ if (check_mic_pin(codec, spec->dmic_nids[i], &fixed, &ext)) ++ return 0; ++ if (!fixed || !ext) ++ return 0; ++ if (!(get_wcaps(codec, ext) & AC_WCAP_UNSOL_CAP)) ++ return 0; /* no unsol support */ ++ if (set_mic_route(codec, &spec->ext_mic, ext) || ++ set_mic_route(codec, &spec->int_mic, fixed)) ++ return 0; /* something is wrong */ ++ return 1; ++} ++ + /* create playback/capture controls for input pins */ + static int stac92xx_auto_create_analog_input_ctls(struct hda_codec *codec, const struct auto_pin_cfg *cfg) + { + struct sigmatel_spec *spec = codec->spec; + struct hda_input_mux *imux = &spec->private_imux; +- hda_nid_t con_lst[HDA_MAX_NUM_INPUTS]; +- int i, j, k; ++ int i, j; + + for (i = 0; i < AUTO_PIN_LAST; i++) { +- int index; ++ hda_nid_t nid = cfg->input_pins[i]; ++ int index, err; + +- if (!cfg->input_pins[i]) ++ if (!nid) + continue; + index = -1; + for (j = 0; j < spec->num_muxes; j++) { +- int num_cons; +- num_cons = snd_hda_get_connections(codec, +- spec->mux_nids[j], +- con_lst, +- HDA_MAX_NUM_INPUTS); +- for (k = 0; k < num_cons; k++) +- if (con_lst[k] == cfg->input_pins[i]) { +- index = k; +- goto found; +- } ++ index = get_connection_index(codec, spec->mux_nids[j], ++ nid); ++ if (index >= 0) ++ break; + } +- continue; +- found: ++ if (index < 0) ++ continue; ++ ++ err = create_elem_capture_vol(codec, nid, ++ auto_pin_cfg_labels[i]); ++ if (err < 0) ++ return err; ++ + imux->items[imux->num_items].label = auto_pin_cfg_labels[i]; + imux->items[imux->num_items].index = index; + imux->num_items++; + } ++ spec->num_analog_muxes = imux->num_items; + + if (imux->num_items) { + /* +@@ -3469,7 +3678,7 @@ static int stac92xx_parse_auto_config(st + { + struct sigmatel_spec *spec = codec->spec; + int hp_swap = 0; +- int err; ++ int i, err; + + if ((err = snd_hda_parse_pin_def_config(codec, + &spec->autocfg, +@@ -3509,11 +3718,10 @@ static int stac92xx_parse_auto_config(st + if (snd_hda_get_connections(codec, + spec->autocfg.mono_out_pin, conn_list, 1) && + snd_hda_get_connections(codec, conn_list[0], +- conn_list, 1)) { ++ conn_list, 1) > 0) { + + int wcaps = get_wcaps(codec, conn_list[0]); +- int wid_type = (wcaps & AC_WCAP_TYPE) +- >> AC_WCAP_TYPE_SHIFT; ++ int wid_type = get_wcaps_type(wcaps); + /* LR swap check, some stac925x have a mux that + * changes the DACs output path instead of the + * mono-mux path. +@@ -3578,6 +3786,8 @@ static int stac92xx_parse_auto_config(st + err = snd_hda_attach_beep_device(codec, nid); + if (err < 0) + return err; ++ /* IDT/STAC codecs have linear beep tone parameter */ ++ /*codec->beep->linear_tone = 1;*/ + /* if no beep switch is available, make its own one */ + caps = query_amp_caps(codec, nid, HDA_OUTPUT); + if (codec->beep && +@@ -3602,6 +3812,21 @@ static int stac92xx_parse_auto_config(st + spec->autocfg.line_outs = 0; + } + ++ if (stac_check_auto_mic(codec)) { ++ spec->auto_mic = 1; ++ /* only one capture for auto-mic */ ++ spec->num_adcs = 1; ++ spec->num_caps = 1; ++ spec->num_muxes = 1; ++ } ++ ++ for (i = 0; i < spec->num_caps; i++) { ++ err = stac92xx_add_capvol_ctls(codec, spec->capvols[i], ++ spec->capsws[i], i); ++ if (err < 0) ++ return err; ++ } ++ + err = stac92xx_auto_create_analog_input_ctls(codec, &spec->autocfg); + if (err < 0) + return err; +@@ -3631,6 +3856,10 @@ static int stac92xx_parse_auto_config(st + return err; + } + ++ err = stac92xx_add_input_source(spec); ++ if (err < 0) ++ return err; ++ + spec->multiout.max_channels = spec->multiout.num_dacs * 2; + if (spec->multiout.max_channels > 2) + spec->surr_switch = 1; +@@ -3640,8 +3869,8 @@ static int stac92xx_parse_auto_config(st + if (dig_in && spec->autocfg.dig_in_pin) + spec->dig_in_nid = dig_in; + +- if (spec->kctl_alloc) +- spec->mixers[spec->num_mixers++] = spec->kctl_alloc; ++ if (spec->kctls.list) ++ spec->mixers[spec->num_mixers++] = spec->kctls.list; + + spec->input_mux = &spec->private_imux; + if (!spec->dinput_mux) +@@ -3698,9 +3927,7 @@ static int stac9200_auto_create_lfe_ctls + for (i = 0; i < spec->autocfg.line_outs && lfe_pin == 0x0; i++) { + hda_nid_t pin = spec->autocfg.line_out_pins[i]; + unsigned int defcfg; +- defcfg = snd_hda_codec_read(codec, pin, 0, +- AC_VERB_GET_CONFIG_DEFAULT, +- 0x00); ++ defcfg = snd_hda_codec_get_pincfg(codec, pin); + if (get_defcfg_device(defcfg) == AC_JACK_SPEAKER) { + unsigned int wcaps = get_wcaps(codec, pin); + wcaps &= (AC_WCAP_STEREO | AC_WCAP_OUT_AMP); +@@ -3744,13 +3971,17 @@ static int stac9200_parse_auto_config(st + return err; + } + ++ err = stac92xx_add_input_source(spec); ++ if (err < 0) ++ return err; ++ + if (spec->autocfg.dig_out_pin) + spec->multiout.dig_out_nid = 0x05; + if (spec->autocfg.dig_in_pin) + spec->dig_in_nid = 0x04; + +- if (spec->kctl_alloc) +- spec->mixers[spec->num_mixers++] = spec->kctl_alloc; ++ if (spec->kctls.list) ++ spec->mixers[spec->num_mixers++] = spec->kctls.list; + + spec->input_mux = &spec->private_imux; + spec->dinput_mux = &spec->private_dimux; +@@ -3799,26 +4030,27 @@ static int stac_add_event(struct sigmate + { + struct sigmatel_event *event; + +- if (spec->num_events >= ARRAY_SIZE(spec->events)) ++ snd_array_init(&spec->events, sizeof(*event), 32); ++ event = snd_array_new(&spec->events); ++ if (!event) + return -ENOMEM; +- event = &spec->events[spec->num_events++]; + event->nid = nid; + event->type = type; +- event->tag = spec->num_events; ++ event->tag = spec->events.used; + event->data = data; + + return event->tag; + } + + static struct sigmatel_event *stac_get_event(struct hda_codec *codec, +- hda_nid_t nid, unsigned char type) ++ hda_nid_t nid) + { + struct sigmatel_spec *spec = codec->spec; +- struct sigmatel_event *event = spec->events; ++ struct sigmatel_event *event = spec->events.list; + int i; + +- for (i = 0; i < spec->num_events; i++, event++) { +- if (event->nid == nid && event->type == type) ++ for (i = 0; i < spec->events.used; i++, event++) { ++ if (event->nid == nid) + return event; + } + return NULL; +@@ -3828,34 +4060,42 @@ static struct sigmatel_event *stac_get_e + unsigned char tag) + { + struct sigmatel_spec *spec = codec->spec; +- struct sigmatel_event *event = spec->events; ++ struct sigmatel_event *event = spec->events.list; + int i; + +- for (i = 0; i < spec->num_events; i++, event++) { ++ for (i = 0; i < spec->events.used; i++, event++) { + if (event->tag == tag) + return event; + } + return NULL; + } + +-static void enable_pin_detect(struct hda_codec *codec, hda_nid_t nid, +- unsigned int type) ++/* check if given nid is a valid pin and no other events are assigned ++ * to it. If OK, assign the event, set the unsol flag, and returns 1. ++ * Otherwise, returns zero. ++ */ ++static int enable_pin_detect(struct hda_codec *codec, hda_nid_t nid, ++ unsigned int type) + { + struct sigmatel_event *event; + int tag; + + if (!(get_wcaps(codec, nid) & AC_WCAP_UNSOL_CAP)) +- return; +- event = stac_get_event(codec, nid, type); +- if (event) ++ return 0; ++ event = stac_get_event(codec, nid); ++ if (event) { ++ if (event->type != type) ++ return 0; + tag = event->tag; +- else ++ } else { + tag = stac_add_event(codec->spec, nid, type, 0); +- if (tag < 0) +- return; ++ if (tag < 0) ++ return 0; ++ } + snd_hda_codec_write_cache(codec, nid, 0, + AC_VERB_SET_UNSOLICITED_ENABLE, + AC_USRSP_EN | tag); ++ return 1; + } + + static int is_nid_hp_pin(struct auto_pin_cfg *cfg, hda_nid_t nid) +@@ -3915,46 +4155,65 @@ static int stac92xx_init(struct hda_code + hda_nid_t nid = cfg->hp_pins[i]; + enable_pin_detect(codec, nid, STAC_HP_EVENT); + } ++ if (cfg->line_out_type == AUTO_PIN_LINE_OUT && ++ cfg->speaker_outs > 0) { ++ /* enable pin-detect for line-outs as well */ ++ for (i = 0; i < cfg->line_outs; i++) { ++ hda_nid_t nid = cfg->line_out_pins[i]; ++ enable_pin_detect(codec, nid, STAC_LO_EVENT); ++ } ++ } ++ + /* force to enable the first line-out; the others are set up + * in unsol_event + */ + stac92xx_auto_set_pinctl(codec, spec->autocfg.line_out_pins[0], +- AC_PINCTL_OUT_EN); ++ AC_PINCTL_OUT_EN); + /* fake event to set up pins */ +- stac_issue_unsol_event(codec, spec->autocfg.hp_pins[0], +- STAC_HP_EVENT); ++ stac_issue_unsol_event(codec, spec->autocfg.hp_pins[0]); + } else { + stac92xx_auto_init_multi_out(codec); + stac92xx_auto_init_hp_out(codec); + for (i = 0; i < cfg->hp_outs; i++) + stac_toggle_power_map(codec, cfg->hp_pins[i], 1); + } ++ if (spec->auto_mic) { ++ /* initialize connection to analog input */ ++ if (spec->dmux_nids) ++ snd_hda_codec_write_cache(codec, spec->dmux_nids[0], 0, ++ AC_VERB_SET_CONNECT_SEL, 0); ++ if (enable_pin_detect(codec, spec->ext_mic.pin, STAC_MIC_EVENT)) ++ stac_issue_unsol_event(codec, spec->ext_mic.pin); ++ } + for (i = 0; i < AUTO_PIN_LAST; i++) { + hda_nid_t nid = cfg->input_pins[i]; + if (nid) { + unsigned int pinctl, conf; + if (i == AUTO_PIN_MIC || i == AUTO_PIN_FRONT_MIC) { + /* for mic pins, force to initialize */ +- pinctl = stac92xx_get_vref(codec, nid); ++ pinctl = stac92xx_get_default_vref(codec, nid); + pinctl |= AC_PINCTL_IN_EN; + stac92xx_auto_set_pinctl(codec, nid, pinctl); + } else { + pinctl = snd_hda_codec_read(codec, nid, 0, + AC_VERB_GET_PIN_WIDGET_CONTROL, 0); + /* if PINCTL already set then skip */ +- if (!(pinctl & AC_PINCTL_IN_EN)) { ++ /* Also, if both INPUT and OUTPUT are set, ++ * it must be a BIOS bug; need to override, too ++ */ ++ if (!(pinctl & AC_PINCTL_IN_EN) || ++ (pinctl & AC_PINCTL_OUT_EN)) { ++ pinctl &= ~AC_PINCTL_OUT_EN; + pinctl |= AC_PINCTL_IN_EN; + stac92xx_auto_set_pinctl(codec, nid, + pinctl); + } + } +- conf = snd_hda_codec_read(codec, nid, 0, +- AC_VERB_GET_CONFIG_DEFAULT, 0); ++ conf = snd_hda_codec_get_pincfg(codec, nid); + if (get_defcfg_connect(conf) != AC_JACK_PORT_FIXED) { +- enable_pin_detect(codec, nid, +- STAC_INSERT_EVENT); +- stac_issue_unsol_event(codec, nid, +- STAC_INSERT_EVENT); ++ if (enable_pin_detect(codec, nid, ++ STAC_INSERT_EVENT)) ++ stac_issue_unsol_event(codec, nid); + } + } + } +@@ -3990,8 +4249,7 @@ static int stac92xx_init(struct hda_code + stac_toggle_power_map(codec, nid, 1); + continue; + } +- def_conf = snd_hda_codec_read(codec, nid, 0, +- AC_VERB_GET_CONFIG_DEFAULT, 0); ++ def_conf = snd_hda_codec_get_pincfg(codec, nid); + def_conf = get_defcfg_connect(def_conf); + /* skip any ports that don't have jacks since presence + * detection is useless */ +@@ -4000,32 +4258,35 @@ static int stac92xx_init(struct hda_code + stac_toggle_power_map(codec, nid, 1); + continue; + } +- if (!stac_get_event(codec, nid, STAC_INSERT_EVENT)) { +- enable_pin_detect(codec, nid, STAC_PWR_EVENT); +- stac_issue_unsol_event(codec, nid, STAC_PWR_EVENT); +- } ++ if (enable_pin_detect(codec, nid, STAC_PWR_EVENT)) ++ stac_issue_unsol_event(codec, nid); + } + if (spec->dac_list) + stac92xx_power_down(codec); + return 0; + } + ++static void stac92xx_free_kctls(struct hda_codec *codec) ++{ ++ struct sigmatel_spec *spec = codec->spec; ++ ++ if (spec->kctls.list) { ++ struct snd_kcontrol_new *kctl = spec->kctls.list; ++ int i; ++ for (i = 0; i < spec->kctls.used; i++) ++ kfree(kctl[i].name); ++ } ++ snd_array_free(&spec->kctls); ++} ++ + static void stac92xx_free(struct hda_codec *codec) + { + struct sigmatel_spec *spec = codec->spec; +- int i; + + if (! spec) + return; + +- if (spec->kctl_alloc) { +- for (i = 0; i < spec->num_kctl_used; i++) +- kfree(spec->kctl_alloc[i].name); +- kfree(spec->kctl_alloc); +- } +- +- if (spec->bios_pin_configs) +- kfree(spec->bios_pin_configs); ++ snd_array_free(&spec->events); + + kfree(spec); + snd_hda_detach_beep_device(codec); +@@ -4034,7 +4295,9 @@ static void stac92xx_free(struct hda_cod + static void stac92xx_set_pinctl(struct hda_codec *codec, hda_nid_t nid, + unsigned int flag) + { +- unsigned int pin_ctl = snd_hda_codec_read(codec, nid, ++ unsigned int old_ctl, pin_ctl; ++ ++ pin_ctl = snd_hda_codec_read(codec, nid, + 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0x00); + + if (pin_ctl & AC_PINCTL_IN_EN) { +@@ -4048,14 +4311,17 @@ static void stac92xx_set_pinctl(struct h + return; + } + ++ old_ctl = pin_ctl; + /* if setting pin direction bits, clear the current + direction bits first */ + if (flag & (AC_PINCTL_IN_EN | AC_PINCTL_OUT_EN)) + pin_ctl &= ~(AC_PINCTL_IN_EN | AC_PINCTL_OUT_EN); + +- snd_hda_codec_write_cache(codec, nid, 0, +- AC_VERB_SET_PIN_WIDGET_CONTROL, +- pin_ctl | flag); ++ pin_ctl |= flag; ++ if (old_ctl != pin_ctl) ++ snd_hda_codec_write_cache(codec, nid, 0, ++ AC_VERB_SET_PIN_WIDGET_CONTROL, ++ pin_ctl); + } + + static void stac92xx_reset_pinctl(struct hda_codec *codec, hda_nid_t nid, +@@ -4063,9 +4329,10 @@ static void stac92xx_reset_pinctl(struct + { + unsigned int pin_ctl = snd_hda_codec_read(codec, nid, + 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0x00); +- snd_hda_codec_write_cache(codec, nid, 0, +- AC_VERB_SET_PIN_WIDGET_CONTROL, +- pin_ctl & ~flag); ++ if (pin_ctl & flag) ++ snd_hda_codec_write_cache(codec, nid, 0, ++ AC_VERB_SET_PIN_WIDGET_CONTROL, ++ pin_ctl & ~flag); + } + + static int get_pin_presence(struct hda_codec *codec, hda_nid_t nid) +@@ -4078,6 +4345,48 @@ static int get_pin_presence(struct hda_c + return 0; + } + ++static void stac92xx_line_out_detect(struct hda_codec *codec, ++ int presence) ++{ ++ struct sigmatel_spec *spec = codec->spec; ++ struct auto_pin_cfg *cfg = &spec->autocfg; ++ int i; ++ ++ for (i = 0; i < cfg->line_outs; i++) { ++ if (presence) ++ break; ++ presence = get_pin_presence(codec, cfg->line_out_pins[i]); ++ if (presence) { ++ unsigned int pinctl; ++ pinctl = snd_hda_codec_read(codec, ++ cfg->line_out_pins[i], 0, ++ AC_VERB_GET_PIN_WIDGET_CONTROL, 0); ++ if (pinctl & AC_PINCTL_IN_EN) ++ presence = 0; /* mic- or line-input */ ++ } ++ } ++ ++ if (presence) { ++ /* disable speakers */ ++ for (i = 0; i < cfg->speaker_outs; i++) ++ stac92xx_reset_pinctl(codec, cfg->speaker_pins[i], ++ AC_PINCTL_OUT_EN); ++ if (spec->eapd_mask && spec->eapd_switch) ++ stac_gpio_set(codec, spec->gpio_mask, ++ spec->gpio_dir, spec->gpio_data & ++ ~spec->eapd_mask); ++ } else { ++ /* enable speakers */ ++ for (i = 0; i < cfg->speaker_outs; i++) ++ stac92xx_set_pinctl(codec, cfg->speaker_pins[i], ++ AC_PINCTL_OUT_EN); ++ if (spec->eapd_mask && spec->eapd_switch) ++ stac_gpio_set(codec, spec->gpio_mask, ++ spec->gpio_dir, spec->gpio_data | ++ spec->eapd_mask); ++ } ++} ++ + /* return non-zero if the hp-pin of the given array index isn't + * a jack-detection target + */ +@@ -4130,13 +4439,6 @@ static void stac92xx_hp_detect(struct hd + for (i = 0; i < cfg->line_outs; i++) + stac92xx_reset_pinctl(codec, cfg->line_out_pins[i], + AC_PINCTL_OUT_EN); +- for (i = 0; i < cfg->speaker_outs; i++) +- stac92xx_reset_pinctl(codec, cfg->speaker_pins[i], +- AC_PINCTL_OUT_EN); +- if (spec->eapd_mask && spec->eapd_switch) +- stac_gpio_set(codec, spec->gpio_mask, +- spec->gpio_dir, spec->gpio_data & +- ~spec->eapd_mask); + } else { + /* enable lineouts */ + if (spec->hp_switch) +@@ -4145,14 +4447,8 @@ static void stac92xx_hp_detect(struct hd + for (i = 0; i < cfg->line_outs; i++) + stac92xx_set_pinctl(codec, cfg->line_out_pins[i], + AC_PINCTL_OUT_EN); +- for (i = 0; i < cfg->speaker_outs; i++) +- stac92xx_set_pinctl(codec, cfg->speaker_pins[i], +- AC_PINCTL_OUT_EN); +- if (spec->eapd_mask && spec->eapd_switch) +- stac_gpio_set(codec, spec->gpio_mask, +- spec->gpio_dir, spec->gpio_data | +- spec->eapd_mask); + } ++ stac92xx_line_out_detect(codec, presence); + /* toggle hp outs */ + for (i = 0; i < cfg->hp_outs; i++) { + unsigned int val = AC_PINCTL_OUT_EN | AC_PINCTL_HP_EN; +@@ -4210,10 +4506,28 @@ static void stac92xx_pin_sense(struct hd + stac_toggle_power_map(codec, nid, get_pin_presence(codec, nid)); + } + +-static void stac_issue_unsol_event(struct hda_codec *codec, hda_nid_t nid, +- unsigned char type) ++static void stac92xx_mic_detect(struct hda_codec *codec) ++{ ++ struct sigmatel_spec *spec = codec->spec; ++ struct sigmatel_mic_route *mic; ++ ++ if (get_pin_presence(codec, spec->ext_mic.pin)) ++ mic = &spec->ext_mic; ++ else ++ mic = &spec->int_mic; ++ if (mic->dmux_idx) ++ snd_hda_codec_write_cache(codec, spec->dmux_nids[0], 0, ++ AC_VERB_SET_CONNECT_SEL, ++ mic->dmux_idx); ++ else ++ snd_hda_codec_write_cache(codec, spec->mux_nids[0], 0, ++ AC_VERB_SET_CONNECT_SEL, ++ mic->mux_idx); ++} ++ ++static void stac_issue_unsol_event(struct hda_codec *codec, hda_nid_t nid) + { +- struct sigmatel_event *event = stac_get_event(codec, nid, type); ++ struct sigmatel_event *event = stac_get_event(codec, nid); + if (!event) + return; + codec->patch_ops.unsol_event(codec, (unsigned)event->tag << 26); +@@ -4232,12 +4546,40 @@ static void stac92xx_unsol_event(struct + + switch (event->type) { + case STAC_HP_EVENT: ++ case STAC_LO_EVENT: + stac92xx_hp_detect(codec); +- /* fallthru */ ++ break; ++ case STAC_MIC_EVENT: ++ stac92xx_mic_detect(codec); ++ break; ++ } ++ ++ switch (event->type) { ++ case STAC_HP_EVENT: ++ case STAC_LO_EVENT: ++ case STAC_MIC_EVENT: + case STAC_INSERT_EVENT: + case STAC_PWR_EVENT: + if (spec->num_pwrs > 0) + stac92xx_pin_sense(codec, event->nid); ++ ++ switch (codec->subsystem_id) { ++ case 0x103c308f: ++ if (event->nid == 0xb) { ++ int pin = AC_PINCTL_IN_EN; ++ ++ if (get_pin_presence(codec, 0xa) ++ && get_pin_presence(codec, 0xb)) ++ pin |= AC_PINCTL_VREF_80; ++ if (!get_pin_presence(codec, 0xb)) ++ pin |= AC_PINCTL_VREF_80; ++ ++ /* toggle VREF state based on mic + hp pin ++ * status ++ */ ++ stac92xx_auto_set_pinctl(codec, 0x0a, pin); ++ } ++ } + break; + case STAC_VREF_EVENT: + data = snd_hda_codec_read(codec, codec->afg, 0, +@@ -4254,20 +4596,64 @@ static int stac92xx_resume(struct hda_co + { + struct sigmatel_spec *spec = codec->spec; + +- stac92xx_set_config_regs(codec); + stac92xx_init(codec); + snd_hda_codec_resume_amp(codec); + snd_hda_codec_resume_cache(codec); + /* fake event to set up pins again to override cached values */ + if (spec->hp_detect) +- stac_issue_unsol_event(codec, spec->autocfg.hp_pins[0], +- STAC_HP_EVENT); ++ stac_issue_unsol_event(codec, spec->autocfg.hp_pins[0]); ++ return 0; ++} ++ ++/* ++ * using power check for controlling mute led of HP notebooks ++ * check for mute state only on Speakers (nid = 0x10) ++ * ++ * For this feature CONFIG_SND_HDA_POWER_SAVE is needed, otherwise ++ * the LED is NOT working properly ! ++ * ++ * Changed name to reflect that it now works for any designated ++ * model, not just HP HDX. ++ */ ++ ++#ifdef CONFIG_SND_HDA_POWER_SAVE ++static int stac92xx_hp_check_power_status(struct hda_codec *codec, ++ hda_nid_t nid) ++{ ++ struct sigmatel_spec *spec = codec->spec; ++ ++ if (nid == 0x10) { ++ if (snd_hda_codec_amp_read(codec, nid, 0, HDA_OUTPUT, 0) & ++ HDA_AMP_MUTE) ++ spec->gpio_data &= ~spec->gpio_led; /* orange */ ++ else ++ spec->gpio_data |= spec->gpio_led; /* white */ ++ ++ stac_gpio_set(codec, spec->gpio_mask, ++ spec->gpio_dir, ++ spec->gpio_data); ++ } ++ + return 0; + } ++#endif + + static int stac92xx_suspend(struct hda_codec *codec, pm_message_t state) + { + struct sigmatel_spec *spec = codec->spec; ++ int i; ++ hda_nid_t nid; ++ ++ /* reset each pin before powering down DAC/ADC to avoid click noise */ ++ nid = codec->start_nid; ++ for (i = 0; i < codec->num_nodes; i++, nid++) { ++ unsigned int wcaps = get_wcaps(codec, nid); ++ unsigned int wid_type = get_wcaps_type(wcaps); ++ if (wid_type == AC_WID_PIN) ++ snd_hda_codec_read(codec, nid, 0, ++ AC_VERB_SET_PIN_WIDGET_CONTROL, 0); ++ } ++ + if (spec->eapd_mask) + stac_gpio_set(codec, spec->gpio_mask, + spec->gpio_dir, spec->gpio_data & +@@ -4421,6 +4807,9 @@ static int patch_stac925x(struct hda_cod + + spec->init = stac925x_core_init; + spec->mixer = stac925x_mixer; ++ spec->num_caps = 1; ++ spec->capvols = stac925x_capvols; ++ spec->capsws = stac925x_capsws; + + err = stac92xx_parse_auto_config(codec, 0x8, 0x7); + if (!err) { +@@ -4442,16 +4831,6 @@ static int patch_stac925x(struct hda_cod + return 0; + } + +-static struct hda_input_mux stac92hd73xx_dmux = { +- .num_items = 4, +- .items = { +- { "Analog Inputs", 0x0b }, +- { "Digital Mic 1", 0x09 }, +- { "Digital Mic 2", 0x0a }, +- { "CD", 0x08 }, +- } +-}; +- + static int patch_stac92hd73xx(struct hda_codec *codec) + { + struct sigmatel_spec *spec; +@@ -4506,12 +4885,10 @@ again: + case 0x5: /* 10 Channel */ + spec->mixer = stac92hd73xx_10ch_mixer; + spec->init = stac92hd73xx_10ch_core_init; ++ break; + } + spec->multiout.dac_nids = spec->dac_nids; + +- spec->aloopback_mask = 0x01; +- spec->aloopback_shift = 8; +- + spec->digbeep_nid = 0x1c; + spec->mux_nids = stac92hd73xx_mux_nids; + spec->adc_nids = stac92hd73xx_adc_nids; +@@ -4524,8 +4901,10 @@ again: + spec->num_muxes = ARRAY_SIZE(stac92hd73xx_mux_nids); + spec->num_adcs = ARRAY_SIZE(stac92hd73xx_adc_nids); + spec->num_dmuxes = ARRAY_SIZE(stac92hd73xx_dmux_nids); +- memcpy(&spec->private_dimux, &stac92hd73xx_dmux, +- sizeof(stac92hd73xx_dmux)); ++ ++ spec->num_caps = STAC92HD73XX_NUM_CAPS; ++ spec->capvols = stac92hd73xx_capvols; ++ spec->capsws = stac92hd73xx_capsws; + + switch (spec->board_config) { + case STAC_DELL_EQ: +@@ -4544,20 +4923,17 @@ again: + spec->init = dell_m6_core_init; + switch (spec->board_config) { + case STAC_DELL_M6_AMIC: /* Analog Mics */ +- stac92xx_set_config_reg(codec, 0x0b, 0x90A70170); ++ snd_hda_codec_set_pincfg(codec, 0x0b, 0x90A70170); + spec->num_dmics = 0; +- spec->private_dimux.num_items = 1; + break; + case STAC_DELL_M6_DMIC: /* Digital Mics */ +- stac92xx_set_config_reg(codec, 0x13, 0x90A60160); ++ snd_hda_codec_set_pincfg(codec, 0x13, 0x90A60160); + spec->num_dmics = 1; +- spec->private_dimux.num_items = 2; + break; + case STAC_DELL_M6_BOTH: /* Both */ +- stac92xx_set_config_reg(codec, 0x0b, 0x90A70170); +- stac92xx_set_config_reg(codec, 0x13, 0x90A60160); ++ snd_hda_codec_set_pincfg(codec, 0x0b, 0x90A70170); ++ snd_hda_codec_set_pincfg(codec, 0x13, 0x90A60160); + spec->num_dmics = 1; +- spec->private_dimux.num_items = 2; + break; + } + break; +@@ -4565,13 +4941,13 @@ again: + spec->num_dmics = STAC92HD73XX_NUM_DMICS; + spec->num_smuxes = ARRAY_SIZE(stac92hd73xx_smux_nids); + spec->eapd_switch = 1; ++ break; + } + if (spec->board_config > STAC_92HD73XX_REF) { + /* GPIO0 High = Enable EAPD */ + spec->eapd_mask = spec->gpio_mask = spec->gpio_dir = 0x1; + spec->gpio_data = 0x01; + } +- spec->dinput_mux = &spec->private_dimux; + + spec->num_pwrs = ARRAY_SIZE(stac92hd73xx_pwr_nids); + spec->pwr_nids = stac92hd73xx_pwr_nids; +@@ -4601,21 +4977,13 @@ again: + return 0; + } + +-static struct hda_input_mux stac92hd83xxx_dmux = { +- .num_items = 3, +- .items = { +- { "Analog Inputs", 0x03 }, +- { "Digital Mic 1", 0x04 }, +- { "Digital Mic 2", 0x05 }, +- } +-}; +- + static int patch_stac92hd83xxx(struct hda_codec *codec) + { + struct sigmatel_spec *spec; + hda_nid_t conn[STAC92HD83_DAC_COUNT + 1]; + int err; + int num_dacs; ++ hda_nid_t nid; + + spec = kzalloc(sizeof(*spec), GFP_KERNEL); + if (spec == NULL) +@@ -4625,32 +4993,22 @@ static int patch_stac92hd83xxx(struct hd + codec->slave_dig_outs = stac92hd83xxx_slave_dig_outs; + spec->mono_nid = 0x19; + spec->digbeep_nid = 0x21; +- spec->dmic_nids = stac92hd83xxx_dmic_nids; +- spec->dmux_nids = stac92hd83xxx_dmux_nids; ++ spec->mux_nids = stac92hd83xxx_mux_nids; ++ spec->num_muxes = ARRAY_SIZE(stac92hd83xxx_mux_nids); + spec->adc_nids = stac92hd83xxx_adc_nids; ++ spec->num_adcs = ARRAY_SIZE(stac92hd83xxx_adc_nids); + spec->pwr_nids = stac92hd83xxx_pwr_nids; +- spec->amp_nids = stac92hd83xxx_amp_nids; + spec->pwr_mapping = stac92hd83xxx_pwr_mapping; + spec->num_pwrs = ARRAY_SIZE(stac92hd83xxx_pwr_nids); + spec->multiout.dac_nids = spec->dac_nids; + +- /* set port 0xe to select the last DAC +- */ +- num_dacs = snd_hda_get_connections(codec, 0x0e, +- conn, STAC92HD83_DAC_COUNT + 1) - 1; +- +- snd_hda_codec_write_cache(codec, 0xe, 0, +- AC_VERB_SET_CONNECT_SEL, num_dacs); +- + spec->init = stac92hd83xxx_core_init; +- spec->mixer = stac92hd83xxx_mixer; + spec->num_pins = ARRAY_SIZE(stac92hd83xxx_pin_nids); +- spec->num_dmuxes = ARRAY_SIZE(stac92hd83xxx_dmux_nids); +- spec->num_adcs = ARRAY_SIZE(stac92hd83xxx_adc_nids); +- spec->num_amps = ARRAY_SIZE(stac92hd83xxx_amp_nids); +- spec->num_dmics = STAC92HD83XXX_NUM_DMICS; +- spec->dinput_mux = &stac92hd83xxx_dmux; + spec->pin_nids = stac92hd83xxx_pin_nids; ++ spec->num_caps = STAC92HD83XXX_NUM_CAPS; ++ spec->capvols = stac92hd83xxx_capvols; ++ spec->capsws = stac92hd83xxx_capsws; ++ + spec->board_config = snd_hda_check_board_config(codec, + STAC_92HD83XXX_MODELS, + stac92hd83xxx_models, +@@ -4673,6 +5031,7 @@ again: + switch (codec->vendor_id) { + case 0x111d7604: + case 0x111d7605: ++ case 0x111d76d5: + if (spec->board_config == STAC_92HD83XXX_PWR_REF) + break; + spec->num_pwrs = 0; +@@ -4695,24 +5054,89 @@ again: + return err; + } + ++ switch (spec->board_config) { ++ case STAC_DELL_S14: ++ nid = 0xf; ++ break; ++ default: ++ nid = 0xe; ++ break; ++ } ++ ++ num_dacs = snd_hda_get_connections(codec, nid, ++ conn, STAC92HD83_DAC_COUNT + 1) - 1; ++ if (num_dacs < 0) ++ num_dacs = STAC92HD83_DAC_COUNT; ++ ++ /* set port X to select the last DAC ++ */ ++ snd_hda_codec_write_cache(codec, nid, 0, ++ AC_VERB_SET_CONNECT_SEL, num_dacs); ++ + codec->patch_ops = stac92xx_patch_ops; + + return 0; + } + +-static struct hda_input_mux stac92hd71bxx_dmux = { +- .num_items = 4, +- .items = { +- { "Analog Inputs", 0x00 }, +- { "Mixer", 0x01 }, +- { "Digital Mic 1", 0x02 }, +- { "Digital Mic 2", 0x03 }, ++/* get the pin connection (fixed, none, etc) */ ++static unsigned int stac_get_defcfg_connect(struct hda_codec *codec, int idx) ++{ ++ struct sigmatel_spec *spec = codec->spec; ++ unsigned int cfg; ++ ++ cfg = snd_hda_codec_get_pincfg(codec, spec->pin_nids[idx]); ++ return get_defcfg_connect(cfg); ++} ++ ++static int stac92hd71bxx_connected_ports(struct hda_codec *codec, ++ hda_nid_t *nids, int num_nids) ++{ ++ struct sigmatel_spec *spec = codec->spec; ++ int idx, num; ++ unsigned int def_conf; ++ ++ for (num = 0; num < num_nids; num++) { ++ for (idx = 0; idx < spec->num_pins; idx++) ++ if (spec->pin_nids[idx] == nids[num]) ++ break; ++ if (idx >= spec->num_pins) ++ break; ++ def_conf = stac_get_defcfg_connect(codec, idx); ++ if (def_conf == AC_JACK_PORT_NONE) ++ break; + } +-}; ++ return num; ++} ++ ++static int stac92hd71bxx_connected_smuxes(struct hda_codec *codec, ++ hda_nid_t dig0pin) ++{ ++ struct sigmatel_spec *spec = codec->spec; ++ int idx; ++ ++ for (idx = 0; idx < spec->num_pins; idx++) ++ if (spec->pin_nids[idx] == dig0pin) ++ break; ++ if ((idx + 2) >= spec->num_pins) ++ return 0; ++ ++ /* dig1pin case */ ++ if (stac_get_defcfg_connect(codec, idx + 1) != AC_JACK_PORT_NONE) ++ return 2; ++ ++ /* dig0pin + dig2pin case */ ++ if (stac_get_defcfg_connect(codec, idx + 2) != AC_JACK_PORT_NONE) ++ return 2; ++ if (stac_get_defcfg_connect(codec, idx) != AC_JACK_PORT_NONE) ++ return 1; ++ else ++ return 0; ++} + + static int patch_stac92hd71bxx(struct hda_codec *codec) + { + struct sigmatel_spec *spec; ++ struct hda_verb *unmute_init = stac92hd71bxx_unmute_core_init; + int err = 0; + + spec = kzalloc(sizeof(*spec), GFP_KERNEL); +@@ -4721,11 +5145,21 @@ static int patch_stac92hd71bxx(struct hd + + codec->spec = spec; + codec->patch_ops = stac92xx_patch_ops; +- spec->num_pins = ARRAY_SIZE(stac92hd71bxx_pin_nids); ++ spec->num_pins = STAC92HD71BXX_NUM_PINS; ++ switch (codec->vendor_id) { ++ case 0x111d76b6: ++ case 0x111d76b7: ++ spec->pin_nids = stac92hd71bxx_pin_nids_4port; ++ break; ++ case 0x111d7603: ++ case 0x111d7608: ++ /* On 92HD75Bx 0x27 isn't a pin nid */ ++ spec->num_pins--; ++ /* fallthrough */ ++ default: ++ spec->pin_nids = stac92hd71bxx_pin_nids_6port; ++ } + spec->num_pwrs = ARRAY_SIZE(stac92hd71bxx_pwr_nids); +- spec->pin_nids = stac92hd71bxx_pin_nids; +- memcpy(&spec->private_dimux, &stac92hd71bxx_dmux, +- sizeof(stac92hd71bxx_dmux)); + spec->board_config = snd_hda_check_board_config(codec, + STAC_92HD71BXX_MODELS, + stac92hd71bxx_models, +@@ -4752,14 +5186,25 @@ again: + spec->gpio_data = 0x01; + } + ++ spec->dmic_nids = stac92hd71bxx_dmic_nids; ++ spec->dmux_nids = stac92hd71bxx_dmux_nids; ++ ++ spec->num_caps = STAC92HD71BXX_NUM_CAPS; ++ spec->capvols = stac92hd71bxx_capvols; ++ spec->capsws = stac92hd71bxx_capsws; ++ + switch (codec->vendor_id) { + case 0x111d76b6: /* 4 Port without Analog Mixer */ + case 0x111d76b7: ++ unmute_init++; ++ /* fallthru */ + case 0x111d76b4: /* 6 Port without Analog Mixer */ + case 0x111d76b5: +- spec->mixer = stac92hd71bxx_mixer; + spec->init = stac92hd71bxx_core_init; + codec->slave_dig_outs = stac92hd71bxx_slave_dig_outs; ++ spec->num_dmics = stac92hd71bxx_connected_ports(codec, ++ stac92hd71bxx_dmic_nids, ++ STAC92HD71BXX_NUM_DMICS); + break; + case 0x111d7608: /* 5 Port with Analog Mixer */ + switch (spec->board_config) { +@@ -4783,12 +5228,15 @@ again: + + /* no output amps */ + spec->num_pwrs = 0; +- spec->mixer = stac92hd71bxx_analog_mixer; +- spec->dinput_mux = &spec->private_dimux; +- + /* disable VSW */ +- spec->init = &stac92hd71bxx_analog_core_init[HD_DISABLE_PORTF]; +- stac92xx_set_config_reg(codec, 0xf, 0x40f000f0); ++ spec->init = stac92hd71bxx_core_init; ++ unmute_init++; ++ snd_hda_codec_set_pincfg(codec, 0x0f, 0x40f000f0); ++ snd_hda_codec_set_pincfg(codec, 0x19, 0x40f000f3); ++ stac92hd71bxx_dmic_nids[STAC92HD71BXX_NUM_DMICS - 1] = 0; ++ spec->num_dmics = stac92hd71bxx_connected_ports(codec, ++ stac92hd71bxx_dmic_nids, ++ STAC92HD71BXX_NUM_DMICS - 1); + break; + case 0x111d7603: /* 6 Port with Analog Mixer */ + if ((codec->revision_id & 0xf) == 1) +@@ -4798,12 +5246,17 @@ again: + spec->num_pwrs = 0; + /* fallthru */ + default: +- spec->dinput_mux = &spec->private_dimux; +- spec->mixer = stac92hd71bxx_analog_mixer; +- spec->init = stac92hd71bxx_analog_core_init; ++ spec->init = stac92hd71bxx_core_init; + codec->slave_dig_outs = stac92hd71bxx_slave_dig_outs; ++ spec->num_dmics = stac92hd71bxx_connected_ports(codec, ++ stac92hd71bxx_dmic_nids, ++ STAC92HD71BXX_NUM_DMICS); ++ break; + } + ++ if (get_wcaps(codec, 0xa) & AC_WCAP_IN_AMP) ++ snd_hda_sequence_write_cache(codec, unmute_init); ++ + /* Some HP machines seem to have unstable codec communications + * especially with ATI fglrx driver. For recovering from the + * CORB/RIRB stall, allow the BUS reset and keep always sync +@@ -4813,25 +5266,22 @@ again: + codec->bus->allow_bus_reset = 1; + } + +- spec->aloopback_mask = 0x50; +- spec->aloopback_shift = 0; +- + spec->powerdown_adcs = 1; + spec->digbeep_nid = 0x26; + spec->mux_nids = stac92hd71bxx_mux_nids; + spec->adc_nids = stac92hd71bxx_adc_nids; +- spec->dmic_nids = stac92hd71bxx_dmic_nids; +- spec->dmux_nids = stac92hd71bxx_dmux_nids; + spec->smux_nids = stac92hd71bxx_smux_nids; + spec->pwr_nids = stac92hd71bxx_pwr_nids; + + spec->num_muxes = ARRAY_SIZE(stac92hd71bxx_mux_nids); + spec->num_adcs = ARRAY_SIZE(stac92hd71bxx_adc_nids); ++ spec->num_dmuxes = ARRAY_SIZE(stac92hd71bxx_dmux_nids); ++ spec->num_smuxes = stac92hd71bxx_connected_smuxes(codec, 0x1e); + + switch (spec->board_config) { + case STAC_HP_M4: + /* enable internal microphone */ +- stac92xx_set_config_reg(codec, 0x0e, 0x01813040); ++ snd_hda_codec_set_pincfg(codec, 0x0e, 0x01813040); + stac92xx_auto_set_pinctl(codec, 0x0e, + AC_PINCTL_IN_EN | AC_PINCTL_VREF_80); + /* fallthru */ +@@ -4846,19 +5296,42 @@ again: + spec->num_smuxes = 0; + spec->num_dmuxes = 1; + break; +- default: +- spec->num_dmics = STAC92HD71BXX_NUM_DMICS; +- spec->num_smuxes = ARRAY_SIZE(stac92hd71bxx_smux_nids); +- spec->num_dmuxes = ARRAY_SIZE(stac92hd71bxx_dmux_nids); +- }; ++ case STAC_HP_DV4_1222NR: ++ spec->num_dmics = 1; ++ /* I don't know if it needs 1 or 2 smuxes - will wait for ++ * bug reports to fix if needed ++ */ ++ spec->num_smuxes = 1; ++ spec->num_dmuxes = 1; ++ spec->gpio_led = 0x01; ++ /* fallthrough */ ++ case STAC_HP_DV5: ++ snd_hda_codec_set_pincfg(codec, 0x0d, 0x90170010); ++ stac92xx_auto_set_pinctl(codec, 0x0d, AC_PINCTL_OUT_EN); ++ break; ++ case STAC_HP_HDX: ++ spec->num_dmics = 1; ++ spec->num_dmuxes = 1; ++ spec->num_smuxes = 1; ++ /* orange/white mute led on GPIO3, orange=0, white=1 */ ++ spec->gpio_led = 0x08; ++ break; ++ } ++ ++#ifdef CONFIG_SND_HDA_POWER_SAVE ++ if (spec->gpio_led) { ++ spec->gpio_mask |= spec->gpio_led; ++ spec->gpio_dir |= spec->gpio_led; ++ spec->gpio_data |= spec->gpio_led; ++ /* register check_power_status callback. */ ++ codec->patch_ops.check_power_status = ++ stac92xx_hp_check_power_status; ++ } ++#endif + + spec->multiout.dac_nids = spec->dac_nids; +- if (spec->dinput_mux) +- spec->private_dimux.num_items += +- spec->num_dmics - +- (ARRAY_SIZE(stac92hd71bxx_dmic_nids) - 1); + +- err = stac92xx_parse_auto_config(codec, 0x21, 0x23); ++ err = stac92xx_parse_auto_config(codec, 0x21, 0); + if (!err) { + if (spec->board_config < 0) { + printk(KERN_WARNING "hda_codec: No auto-config is " +@@ -4875,7 +5348,7 @@ again: + } + + return 0; +-}; ++} + + static int patch_stac922x(struct hda_codec *codec) + { +@@ -4953,7 +5426,10 @@ static int patch_stac922x(struct hda_cod + spec->num_pwrs = 0; + + spec->init = stac922x_core_init; +- spec->mixer = stac922x_mixer; ++ ++ spec->num_caps = STAC922X_NUM_CAPS; ++ spec->capvols = stac922x_capvols; ++ spec->capsws = stac922x_capsws; + + spec->multiout.dac_nids = spec->dac_nids; + +@@ -4994,6 +5470,7 @@ static int patch_stac927x(struct hda_cod + return -ENOMEM; + + codec->spec = spec; ++ codec->slave_dig_outs = stac927x_slave_dig_outs; + spec->num_pins = ARRAY_SIZE(stac927x_pin_nids); + spec->pin_nids = stac927x_pin_nids; + spec->board_config = snd_hda_check_board_config(codec, STAC_927X_MODELS, +@@ -5035,32 +5512,37 @@ static int patch_stac927x(struct hda_cod + spec->num_dmics = 0; + + spec->init = d965_core_init; +- spec->mixer = stac927x_mixer; + break; + case STAC_DELL_BIOS: + switch (codec->subsystem_id) { + case 0x10280209: + case 0x1028022e: + /* correct the device field to SPDIF out */ +- stac92xx_set_config_reg(codec, 0x21, 0x01442070); ++ snd_hda_codec_set_pincfg(codec, 0x21, 0x01442070); + break; +- }; ++ } + /* configure the analog microphone on some laptops */ +- stac92xx_set_config_reg(codec, 0x0c, 0x90a79130); ++ snd_hda_codec_set_pincfg(codec, 0x0c, 0x90a79130); + /* correct the front output jack as a hp out */ +- stac92xx_set_config_reg(codec, 0x0f, 0x0227011f); ++ snd_hda_codec_set_pincfg(codec, 0x0f, 0x0227011f); + /* correct the front input jack as a mic */ +- stac92xx_set_config_reg(codec, 0x0e, 0x02a79130); ++ snd_hda_codec_set_pincfg(codec, 0x0e, 0x02a79130); + /* fallthru */ + case STAC_DELL_3ST: + /* GPIO2 High = Enable EAPD */ + spec->eapd_mask = spec->gpio_mask = spec->gpio_dir = 0x04; + spec->gpio_data = 0x04; ++ switch (codec->subsystem_id) { ++ case 0x1028022f: ++ /* correct EAPD to be GPIO0 */ ++ spec->eapd_mask = spec->gpio_mask = 0x01; ++ spec->gpio_dir = spec->gpio_data = 0x01; ++ break; ++ }; + spec->dmic_nids = stac927x_dmic_nids; + spec->num_dmics = STAC927X_NUM_DMICS; + + spec->init = d965_core_init; +- spec->mixer = stac927x_mixer; + spec->dmux_nids = stac927x_dmux_nids; + spec->num_dmuxes = ARRAY_SIZE(stac927x_dmux_nids); + break; +@@ -5073,12 +5555,13 @@ static int patch_stac927x(struct hda_cod + spec->num_dmics = 0; + + spec->init = stac927x_core_init; +- spec->mixer = stac927x_mixer; + } + ++ spec->num_caps = STAC927X_NUM_CAPS; ++ spec->capvols = stac927x_capvols; ++ spec->capsws = stac927x_capsws; ++ + spec->num_pwrs = 0; +- spec->aloopback_mask = 0x40; +- spec->aloopback_shift = 0; + spec->eapd_switch = 1; + + err = stac92xx_parse_auto_config(codec, 0x1e, 0x20); +@@ -5160,10 +5643,11 @@ static int patch_stac9205(struct hda_cod + spec->num_pwrs = 0; + + spec->init = stac9205_core_init; +- spec->mixer = stac9205_mixer; + +- spec->aloopback_mask = 0x40; +- spec->aloopback_shift = 0; ++ spec->num_caps = STAC9205_NUM_CAPS; ++ spec->capvols = stac9205_capvols; ++ spec->capsws = stac9205_capsws; ++ + /* Turn on/off EAPD per HP plugging */ + if (spec->board_config != STAC_9205_EAPD) + spec->eapd_switch = 1; +@@ -5172,8 +5656,8 @@ static int patch_stac9205(struct hda_cod + switch (spec->board_config){ + case STAC_9205_DELL_M43: + /* Enable SPDIF in/out */ +- stac92xx_set_config_reg(codec, 0x1f, 0x01441030); +- stac92xx_set_config_reg(codec, 0x20, 0x1c410030); ++ snd_hda_codec_set_pincfg(codec, 0x1f, 0x01441030); ++ snd_hda_codec_set_pincfg(codec, 0x20, 0x1c410030); + + /* Enable unsol response for GPIO4/Dock HP connection */ + err = stac_add_event(spec, codec->afg, STAC_VREF_EVENT, 0x01); +@@ -5507,6 +5991,7 @@ struct hda_codec_preset snd_hda_preset_s + { .id = 0x83847661, .name = "CXD9872RD/K", .patch = patch_stac9872 }, + { .id = 0x83847662, .name = "STAC9872AK", .patch = patch_stac9872 }, + { .id = 0x83847664, .name = "CXD9872AKD", .patch = patch_stac9872 }, ++ { .id = 0x83847698, .name = "STAC9205", .patch = patch_stac9205 }, + { .id = 0x838476a0, .name = "STAC9205", .patch = patch_stac9205 }, + { .id = 0x838476a1, .name = "STAC9205D", .patch = patch_stac9205 }, + { .id = 0x838476a2, .name = "STAC9204", .patch = patch_stac9205 }, +@@ -5518,6 +6003,7 @@ struct hda_codec_preset snd_hda_preset_s + { .id = 0x111d7603, .name = "92HD75B3X5", .patch = patch_stac92hd71bxx}, + { .id = 0x111d7604, .name = "92HD83C1X5", .patch = patch_stac92hd83xxx}, + { .id = 0x111d7605, .name = "92HD81B1X5", .patch = patch_stac92hd83xxx}, ++ { .id = 0x111d76d5, .name = "92HD81B1C5", .patch = patch_stac92hd83xxx}, + { .id = 0x111d7608, .name = "92HD75B2X5", .patch = patch_stac92hd71bxx}, + { .id = 0x111d7674, .name = "92HD73D1X5", .patch = patch_stac92hd73xx }, + { .id = 0x111d7675, .name = "92HD73C1X5", .patch = patch_stac92hd73xx }, +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/sound/pci/oxygen/virtuoso.c linux-2.6.27.29-0.1.1/sound/pci/oxygen/virtuoso.c +--- linux-2.6.27.25-0.1.1/sound/pci/oxygen/virtuoso.c 2009-08-05 09:49:34.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/sound/pci/oxygen/virtuoso.c 2009-08-27 12:44:15.000000000 +0100 +@@ -376,6 +376,8 @@ static void xonar_d2_resume(struct oxyge + + static void xonar_d1_resume(struct oxygen *chip) + { ++ oxygen_set_bits8(chip, OXYGEN_FUNCTION, OXYGEN_FUNCTION_RESET_CODEC); ++ msleep(1); + cs43xx_init(chip); + xonar_enable_output(chip); + } +diff -purN -X linux-2.6.27.29-0.1.1/Documentation/dontdiff linux-2.6.27.25-0.1.1/sound/usb/usbaudio.c linux-2.6.27.29-0.1.1/sound/usb/usbaudio.c +--- linux-2.6.27.25-0.1.1/sound/usb/usbaudio.c 2009-08-27 12:59:16.000000000 +0100 ++++ linux-2.6.27.29-0.1.1/sound/usb/usbaudio.c 2009-08-27 12:44:15.000000000 +0100 +@@ -2674,7 +2674,7 @@ static int parse_audio_endpoints(struct + struct usb_interface_descriptor *altsd; + int i, altno, err, stream; + int format; +- struct audioformat *fp; ++ struct audioformat *fp = NULL; + unsigned char *fmt, *csep; + int num; + +@@ -2747,6 +2747,18 @@ static int parse_audio_endpoints(struct + continue; + } + ++ /* ++ * Blue Microphones workaround: The last altsetting is identical ++ * with the previous one, except for a larger packet size, but ++ * is actually a mislabeled two-channel setting; ignore it. ++ */ ++ if (fmt[4] == 1 && fmt[5] == 2 && altno == 2 && num == 3 && ++ fp && fp->altsetting == 1 && fp->channels == 1 && ++ fp->format == SNDRV_PCM_FORMAT_S16_LE && ++ le16_to_cpu(get_endpoint(alts, 0)->wMaxPacketSize) == ++ fp->maxpacksize * 2) ++ continue; ++ + csep = snd_usb_find_desc(alts->endpoint[0].extra, alts->endpoint[0].extralen, NULL, USB_DT_CS_ENDPOINT); + /* Creamware Noah has this descriptor after the 2nd endpoint */ + if (!csep && altsd->bNumEndpoints >= 2) +--- a/buildconfigs/Rules.mk Wed May 06 15:47:13 2009 +0100 ++++ b/buildconfigs/Rules.mk Wed May 06 16:56:12 2009 +0100 +@@ -2,7 +2,7 @@ + XEN_TARGET_X86_PAE ?= y + + LINUX_SERIES = 2.6 +-LINUX_VER = 2.6.27.25-0.1.1 ++LINUX_VER = 2.6.27.29-0.1.1 + + EXTRAVERSION ?= xen + diff --git a/master/megaraid_sas-v00.00.04.12-compile-fix.patch b/master/megaraid_sas-v00.00.04.12-compile-fix.patch new file mode 100644 index 0000000..a0c50dc --- /dev/null +++ b/master/megaraid_sas-v00.00.04.12-compile-fix.patch @@ -0,0 +1,21 @@ +diff -r 55e0d5c4a00a drivers/scsi/megaraid/megaraid_sas.c +--- a/drivers/scsi/megaraid/megaraid_sas.c Mon Oct 05 17:20:11 2009 +0100 ++++ b/drivers/scsi/megaraid/megaraid_sas.c Mon Oct 05 17:38:17 2009 +0100 +@@ -1231,7 +1231,7 @@ + pd_index = (sdev->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + sdev->id; + + if (instance->pd_list[pd_index].driveState == MR_PD_STATE_SYSTEM) { +- sdev->timeout = 90 * HZ; ++ blk_queue_rq_timeout(sdev->request_queue, 90 * HZ); + return 0; + } + +@@ -1242,7 +1242,7 @@ + /* + * The RAID firmware may require extended timeouts. + */ +- sdev->timeout = 90 * HZ; ++ blk_queue_rq_timeout(sdev->request_queue, 90 * HZ); + return 0; + } + diff --git a/master/megaraid_sas-v00.00.04.12.patch b/master/megaraid_sas-v00.00.04.12.patch new file mode 100644 index 0000000..e232e4f --- /dev/null +++ b/master/megaraid_sas-v00.00.04.12.patch @@ -0,0 +1,1638 @@ +diff -r 4ebb3df27555 drivers/scsi/megaraid/megaraid_sas.c +--- a/drivers/scsi/megaraid/megaraid_sas.c Mon Oct 05 17:15:05 2009 +0100 ++++ b/drivers/scsi/megaraid/megaraid_sas.c Mon Oct 05 17:19:28 2009 +0100 +@@ -10,7 +10,7 @@ + * 2 of the License, or (at your option) any later version. + * + * FILE : megaraid_sas.c +- * Version : v00.00.04.01-rc1 ++ * Version : v00.00.04.12 + * + * Authors: + * (email-id : megaraidlinux@lsi.com) +@@ -40,6 +40,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -75,6 +76,10 @@ + /* gen2*/ + {PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_SAS0079GEN2)}, + /* gen2*/ ++ {PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_SAS0073SKINNY)}, ++ /* skinny*/ ++ {PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_SAS0071SKINNY)}, ++ /* skinny*/ + {PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_VERDE_ZCR)}, + /* xscale IOP, vega */ + {PCI_DEVICE(PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_PERC5)}, +@@ -88,6 +93,15 @@ + static struct megasas_mgmt_info megasas_mgmt_info; + static struct fasync_struct *megasas_async_queue; + static DEFINE_MUTEX(megasas_async_queue_mutex); ++static DEFINE_MUTEX(megasas_poll_wait_mutex); ++ ++ ++static int megasas_poll_wait_aen; ++static DECLARE_WAIT_QUEUE_HEAD (megasas_poll_wait); ++extern void ++poll_wait(struct file *filp, wait_queue_head_t *q, poll_table *token); ++ ++static u32 support_poll_for_event; + + static u32 megasas_dbg_lvl; + +@@ -215,7 +229,7 @@ + * @regs : MFI register set + */ + static inline void +-megasas_fire_cmd_xscale(dma_addr_t frame_phys_addr,u32 frame_count, struct megasas_register_set __iomem *regs) ++megasas_fire_cmd_xscale(struct megasas_instance *instance, dma_addr_t frame_phys_addr,u32 frame_count, struct megasas_register_set __iomem *regs) + { + writel((frame_phys_addr >> 3)|(frame_count), + &(regs)->inbound_queue_port); +@@ -312,7 +326,7 @@ + * @regs : MFI register set + */ + static inline void +-megasas_fire_cmd_ppc(dma_addr_t frame_phys_addr, u32 frame_count, struct megasas_register_set __iomem *regs) ++megasas_fire_cmd_ppc(struct megasas_instance *instance, dma_addr_t frame_phys_addr, u32 frame_count, struct megasas_register_set __iomem *regs) + { + writel((frame_phys_addr | (frame_count<<1))|1, + &(regs)->inbound_queue_port); +@@ -328,6 +342,102 @@ + }; + + /** ++ * megasas_enable_intr_skinny - Enables interrupts ++ * @regs: MFI register set ++ */ ++static inline void ++megasas_enable_intr_skinny(struct megasas_register_set __iomem * regs) ++{ ++ writel(0xFFFFFFFF, &(regs)->outbound_intr_mask); ++ ++ /* write ~0x00000005 (4 & 1) to the intr mask*/ ++ writel(~MFI_SKINNY_ENABLE_INTERRUPT_MASK, &(regs)->outbound_intr_mask); ++ ++ /* Dummy readl to force pci flush */ ++ readl(®s->outbound_intr_mask); ++} ++ ++/** ++ * megasas_disable_intr_skinny - Disables interrupt ++ * @regs: MFI register set ++ */ ++static inline void ++megasas_disable_intr_skinny(struct megasas_register_set __iomem * regs) ++{ ++ u32 mask = 0xFFFFFFFF; ++ writel(mask, ®s->outbound_intr_mask); ++ /* Dummy readl to force pci flush */ ++ readl(®s->outbound_intr_mask); ++} ++ ++/** ++ * megasas_read_fw_status_reg_skinny - returns the current FW status value ++ * @regs: MFI register set ++ */ ++static u32 ++megasas_read_fw_status_reg_skinny(struct megasas_register_set __iomem * regs) ++{ ++ return readl(&(regs)->outbound_scratch_pad); ++} ++ ++ ++/** ++ * megasas_clear_interrupt_skinny - Check & clear interrupt ++ * @regs: MFI register set ++ */ ++static int ++megasas_clear_intr_skinny(struct megasas_register_set __iomem * regs) ++{ ++ u32 status; ++ /* ++ * Check if it is our interrupt ++ */ ++ status = readl(®s->outbound_intr_status); ++ ++ if (!(status & MFI_SKINNY_ENABLE_INTERRUPT_MASK)) { ++ return 1; ++ } ++ ++ /* ++ * Clear the interrupt by writing back the same value ++ */ ++ writel(status, ®s->outbound_intr_status); ++ ++ /* ++ * dummy read to flush PCI ++ */ ++ readl(®s->outbound_intr_status); ++ ++ return 0; ++} ++/** ++ * megasas_fire_cmd_skinny - Sends command to the FW ++ * @frame_phys_addr : Physical address of cmd ++ * @frame_count : Number of frames for the command ++ * @regs : MFI register set ++ */ ++static inline void ++megasas_fire_cmd_skinny(struct megasas_instance *instance, dma_addr_t frame_phys_addr, u32 frame_count, struct megasas_register_set __iomem *regs) ++{ ++ unsigned long flags; ++ spin_lock_irqsave(&instance->fire_lock, flags); ++ writel(0, &(regs)->inbound_high_queue_port); ++ writel((frame_phys_addr | (frame_count<<1))|1, ++ &(regs)->inbound_low_queue_port); ++ spin_unlock_irqrestore(&instance->fire_lock, flags); ++ /*msleep(5);*/ ++} ++ ++static struct megasas_instance_template megasas_instance_template_skinny = { ++ ++ .fire_cmd = megasas_fire_cmd_skinny, ++ .enable_intr = megasas_enable_intr_skinny, ++ .disable_intr = megasas_disable_intr_skinny, ++ .clear_intr = megasas_clear_intr_skinny, ++ .read_fw_status_reg = megasas_read_fw_status_reg_skinny, ++}; ++ ++/** + * The following functions are defined for gen2 (deviceid : 0x78 0x79) + * controllers + */ +@@ -404,11 +514,14 @@ + * @regs : MFI register set + */ + static inline void +-megasas_fire_cmd_gen2(dma_addr_t frame_phys_addr, u32 frame_count, +- struct megasas_register_set __iomem *regs) +-{ ++megasas_fire_cmd_gen2(struct megasas_instance *instance, dma_addr_t frame_phys_addr, ++ u32 frame_count, struct megasas_register_set __iomem *regs) ++{ ++ unsigned long flags; ++ spin_lock_irqsave(&instance->fire_lock, flags); + writel((frame_phys_addr | (frame_count<<1))|1, + &(regs)->inbound_queue_port); ++ spin_unlock_irqrestore(&instance->fire_lock, flags); + } + + static struct megasas_instance_template megasas_instance_template_gen2 = { +@@ -446,7 +559,7 @@ + /* + * Issue the frame using inbound queue port + */ +- instance->instancet->fire_cmd(cmd->frame_phys_addr ,0,instance->reg_set); ++ instance->instancet->fire_cmd(instance, cmd->frame_phys_addr ,0,instance->reg_set); + + /* + * Wait for cmd_status to change +@@ -477,7 +590,7 @@ + { + cmd->cmd_status = ENODATA; + +- instance->instancet->fire_cmd(cmd->frame_phys_addr ,0,instance->reg_set); ++ instance->instancet->fire_cmd(instance, cmd->frame_phys_addr ,0,instance->reg_set); + + wait_event_timeout(instance->int_cmd_wait_q, (cmd->cmd_status != ENODATA), + MEGASAS_INTERNAL_CMD_WAIT_TIME*HZ); +@@ -522,7 +635,7 @@ + cmd->sync_cmd = 1; + cmd->cmd_status = 0xFF; + +- instance->instancet->fire_cmd(cmd->frame_phys_addr ,0,instance->reg_set); ++ instance->instancet->fire_cmd(instance, cmd->frame_phys_addr ,0,instance->reg_set); + + /* + * Wait for this cmd to complete +@@ -592,6 +705,35 @@ + return sge_count; + } + ++/** ++ * megasas_make_sgl_kinny - Prepares 64-bit SGL ++ * @instance: Adapter soft state ++ * @scp: SCSI command from the mid-layer ++ * @mfi_sgl: SGL to be filled in ++ * ++ * If successful, this function returns the number of SG elements. Otherwise, ++ * it returnes -1. ++ */ ++static int ++megasas_make_sgl_skinny(struct megasas_instance *instance, struct scsi_cmnd *scp, ++ union megasas_sgl *mfi_sgl) ++{ ++ int i; ++ int sge_count; ++ struct scatterlist *os_sgl; ++ ++ sge_count = scsi_dma_map(scp); ++ BUG_ON(sge_count < 0); ++ ++ if (sge_count) { ++ scsi_for_each_sg(scp, os_sgl, sge_count, i) { ++ mfi_sgl->sge_skinny[i].length = sg_dma_len(os_sgl); ++ mfi_sgl->sge_skinny[i].phys_addr = sg_dma_address(os_sgl); ++ } ++ } ++ return sge_count; ++} ++ + /** + * megasas_get_frame_count - Computes the number of frames + * @frame_type : type of frame- io or pthru frame +@@ -600,7 +742,7 @@ + * Returns the number of frames required for numnber of sge's (sge_count) + */ + +-static u32 megasas_get_frame_count(u8 sge_count, u8 frame_type) ++static u32 megasas_get_frame_count(struct megasas_instance *instance, u8 sge_count, u8 frame_type) + { + int num_cnt; + int sge_bytes; +@@ -610,6 +752,11 @@ + sge_sz = (IS_DMA64) ? sizeof(struct megasas_sge64) : + sizeof(struct megasas_sge32); + ++ if (instance->flag_ieee) { ++ sge_sz = sizeof(struct megasas_sge_skinny); ++ ++ } ++ + /* + * Main frame can contain 2 SGEs for 64-bit SGLs and + * 3 SGEs for 32-bit SGLs for ldio & +@@ -617,12 +764,18 @@ + * 2 SGEs for 32-bit SGLs for pthru frame + */ + if (unlikely(frame_type == PTHRU_FRAME)) { +- if (IS_DMA64) ++ if (instance->flag_ieee == 1) { ++ num_cnt = sge_count - 1; ++ ++ } else if (IS_DMA64) + num_cnt = sge_count - 1; + else + num_cnt = sge_count - 2; + } else { +- if (IS_DMA64) ++ if (instance->flag_ieee == 1) { ++ num_cnt = sge_count - 1; ++ ++ } else if (IS_DMA64) + num_cnt = sge_count - 2; + else + num_cnt = sge_count - 3; +@@ -670,6 +823,10 @@ + flags = MFI_FRAME_DIR_READ; + else if (scp->sc_data_direction == PCI_DMA_NONE) + flags = MFI_FRAME_DIR_NONE; ++ ++ if (instance->flag_ieee == 1) { ++ flags |= MFI_FRAME_IEEE; ++ } + + /* + * Prepare the DCDB frame +@@ -687,9 +844,25 @@ + memcpy(pthru->cdb, scp->cmnd, scp->cmd_len); + + /* ++ * If the command is for the tape device, set the ++ * pthru timeout to the os layer timeout value. ++ */ ++ if (scp->device->type == TYPE_TAPE) { ++ if ((scp->request->timeout / HZ) > 0xFFFF) ++ pthru->timeout = 0xFFFF; ++ else ++ pthru->timeout = scp->request->timeout / HZ; ++ } ++ ++ /* + * Construct SGL + */ +- if (IS_DMA64) { ++ if (instance->flag_ieee == 1) { ++ pthru->flags |= MFI_FRAME_SGL64; ++ pthru->sge_count = megasas_make_sgl_skinny(instance, scp, ++ &pthru->sgl); ++ ++ } else if (IS_DMA64) { + pthru->flags |= MFI_FRAME_SGL64; + pthru->sge_count = megasas_make_sgl64(instance, scp, + &pthru->sgl); +@@ -708,7 +881,7 @@ + * Compute the total number of frames this command consumes. FW uses + * this number to pull sufficient number of frames from host memory. + */ +- cmd->frame_count = megasas_get_frame_count(pthru->sge_count, ++ cmd->frame_count = megasas_get_frame_count(instance, pthru->sge_count, + PTHRU_FRAME); + + return cmd->frame_count; +@@ -739,6 +912,10 @@ + else if (scp->sc_data_direction == PCI_DMA_FROMDEVICE) + flags = MFI_FRAME_DIR_READ; + ++ if (instance->flag_ieee == 1) { ++ flags |= MFI_FRAME_IEEE; ++ } ++ + /* + * Prepare the Logical IO frame: 2nd bit is zero for all read cmds + */ +@@ -809,7 +986,12 @@ + /* + * Construct SGL + */ +- if (IS_DMA64) { ++ if (instance->flag_ieee) { ++ ldio->flags |= MFI_FRAME_SGL64; ++ ldio->sge_count = megasas_make_sgl_skinny(instance, scp, ++ &ldio->sgl); ++ ++ } else if (IS_DMA64) { + ldio->flags |= MFI_FRAME_SGL64; + ldio->sge_count = megasas_make_sgl64(instance, scp, &ldio->sgl); + } else +@@ -826,7 +1008,7 @@ + * Compute the total number of frames this command consumes. FW uses + * this number to pull sufficient number of frames from host memory. + */ +- cmd->frame_count = megasas_get_frame_count(ldio->sge_count, IO_FRAME); ++ cmd->frame_count = megasas_get_frame_count(instance, ldio->sge_count, IO_FRAME); + + return cmd->frame_count; + } +@@ -931,6 +1113,7 @@ + u32 frame_count; + struct megasas_cmd *cmd; + struct megasas_instance *instance; ++ unsigned long sec; + + instance = (struct megasas_instance *) + scmd->device->host->hostdata; +@@ -959,6 +1142,22 @@ + default: + break; + } ++ ++ /* If FW is busy donot accept any more cmds */ ++ if(instance->is_busy){ ++ sec = (jiffies - instance->last_time) / HZ; ++ if(sec<10) ++ return SCSI_MLQUEUE_HOST_BUSY; ++ else{ ++ instance->is_busy=0; ++ instance->last_time=0; ++ } ++ } ++ ++ if(scmd->retries>1){ ++ instance->is_busy=1; ++ instance->last_time=jiffies; ++ } + + cmd = megasas_get_cmd(instance); + if (!cmd) +@@ -983,7 +1182,7 @@ + */ + atomic_inc(&instance->fw_outstanding); + +- instance->instancet->fire_cmd(cmd->frame_phys_addr ,cmd->frame_count-1,instance->reg_set); ++ instance->instancet->fire_cmd(instance, cmd->frame_phys_addr ,cmd->frame_count-1,instance->reg_set); + /* + * Check if we have pend cmds to be completed + */ +@@ -1000,8 +1199,27 @@ + return 0; + } + ++static struct megasas_instance *megasas_lookup_instance(u16 host_no) ++{ ++ int i; ++ ++ for (i = 0; i < megasas_mgmt_info.max_index; i++) { ++ ++ if ((megasas_mgmt_info.instance[i]) && ++ (megasas_mgmt_info.instance[i]->host->host_no == host_no)) ++ return megasas_mgmt_info.instance[i]; ++ } ++ ++ return NULL; ++} ++ + static int megasas_slave_configure(struct scsi_device *sdev) + { ++ u16 pd_index = 0; ++ struct megasas_instance *instance ; ++ ++ instance = megasas_lookup_instance(sdev->host->host_no); ++ + /* + * Don't export physical disk devices to the disk driver. + * +@@ -1009,15 +1227,22 @@ + * That will be fixed once LSI engineers have audited the + * firmware for possible issues. + */ +- if (sdev->channel < MEGASAS_MAX_PD_CHANNELS && sdev->type == TYPE_DISK) ++ if (sdev->channel < MEGASAS_MAX_PD_CHANNELS && sdev->type == TYPE_DISK) { ++ pd_index = (sdev->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + sdev->id; ++ ++ if (instance->pd_list[pd_index].driveState == MR_PD_STATE_SYSTEM) { ++ sdev->timeout = 90 * HZ; ++ return 0; ++ } ++ + return -ENXIO; + ++ } ++ + /* + * The RAID firmware may require extended timeouts. + */ +- if (sdev->channel >= MEGASAS_MAX_PD_CHANNELS) +- blk_queue_rq_timeout(sdev->request_queue, +- MEGASAS_DEFAULT_CMD_TIMEOUT * HZ); ++ sdev->timeout = 90 * HZ; + return 0; + } + +@@ -1063,20 +1288,6 @@ + + spin_unlock_irqrestore(&instance->completion_lock, flags); + +- /* +- * Check if we can restore can_queue +- */ +- if (instance->flag & MEGASAS_FW_BUSY +- && time_after(jiffies, instance->last_time + 5 * HZ) +- && atomic_read(&instance->fw_outstanding) < 17) { +- +- spin_lock_irqsave(instance->host->host_lock, flags); +- instance->flag &= ~MEGASAS_FW_BUSY; +- instance->host->can_queue = +- instance->max_fw_cmds - MEGASAS_INT_CMDS; +- +- spin_unlock_irqrestore(instance->host->host_lock, flags); +- } + } + + /** +@@ -1117,8 +1328,15 @@ + * Send signal to FW to stop processing any pending cmds. + * The controller will be taken offline by the OS now. + */ +- writel(MFI_STOP_ADP, ++ if ((instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0073SKINNY) || ++ (instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0071SKINNY)) ++ { ++ writel(MFI_STOP_ADP, ++ &instance->reg_set->reserved_0[0]); ++ } else { ++ writel(MFI_STOP_ADP, + &instance->reg_set->inbound_doorbell); ++ } + megasas_dump_pending_frames(instance); + instance->hw_crit_error = 1; + return FAILED; +@@ -1158,39 +1376,6 @@ + printk(KERN_ERR "megasas: failed to do reset\n"); + + return ret_val; +-} +- +-/** +- * megasas_reset_timer - quiesce the adapter if required +- * @scmd: scsi cmnd +- * +- * Sets the FW busy flag and reduces the host->can_queue if the +- * cmd has not been completed within the timeout period. +- */ +-static enum +-blk_eh_timer_return megasas_reset_timer(struct scsi_cmnd *scmd) +-{ +- struct megasas_cmd *cmd = (struct megasas_cmd *)scmd->SCp.ptr; +- struct megasas_instance *instance; +- unsigned long flags; +- +- if (time_after(jiffies, scmd->jiffies_at_alloc + +- (MEGASAS_DEFAULT_CMD_TIMEOUT * 2) * HZ)) { +- return BLK_EH_NOT_HANDLED; +- } +- +- instance = cmd->instance; +- if (!(instance->flag & MEGASAS_FW_BUSY)) { +- /* FW is busy, throttle IO */ +- spin_lock_irqsave(instance->host->host_lock, flags); +- +- instance->host->can_queue = 16; +- instance->last_time = jiffies; +- instance->flag |= MEGASAS_FW_BUSY; +- +- spin_unlock_irqrestore(instance->host->host_lock, flags); +- } +- return BLK_EH_RESET_TIMER; + } + + /** +@@ -1266,6 +1451,8 @@ + return 0; + } + ++static void megasas_aen_polling(struct work_struct *work); ++ + /** + * megasas_service_aen - Processes an event notification + * @instance: Adapter soft state +@@ -1284,14 +1471,55 @@ + /* + * Don't signal app if it is just an aborted previously registered aen + */ +- if (!cmd->abort_aen) ++ if ((!cmd->abort_aen) && (instance->unload == 0)) { ++ megasas_poll_wait_aen = 1; ++ wake_up(&megasas_poll_wait); + kill_fasync(&megasas_async_queue, SIGIO, POLL_IN); ++ } + else + cmd->abort_aen = 0; +- ++ + instance->aen_cmd = NULL; + megasas_return_cmd(instance, cmd); +-} ++ ++ if ((instance->unload == 0)) { ++ struct megasas_aen_event *ev; ++ ev = kzalloc(sizeof(*ev), GFP_ATOMIC); ++ if (!ev) { ++ printk(KERN_ERR "%s: out of memory\n", __FUNCTION__); ++ } else { ++ ev->instance = instance; ++ INIT_WORK(&ev->hotplug_work, megasas_aen_polling); ++ schedule_delayed_work((struct delayed_work *)&ev->hotplug_work, 0); ++ } ++ } ++} ++ ++static int megasas_slave_alloc(struct scsi_device *sdev) ++{ ++ u16 pd_index = 0; ++ struct megasas_instance *instance ; ++ instance = megasas_lookup_instance(sdev->host->host_no); ++ ++ if ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) && ++ (sdev->type == TYPE_DISK)) { ++ /* ++ * Open the OS scan to the SYSTEM PD ++ */ ++ pd_index = ++ (sdev->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + sdev->id; ++ if ((instance->pd_list[pd_index].driveState == ++ MR_PD_STATE_SYSTEM) && ++ (instance->pd_list[pd_index].driveType == ++ TYPE_DISK)) { ++ return 0; ++ } ++ ++ return -ENXIO; ++ } ++ return 0; ++} ++ + + /* + * Scsi host template for megaraid_sas driver +@@ -1302,11 +1530,11 @@ + .name = "LSI SAS based MegaRAID driver", + .proc_name = "megaraid_sas", + .slave_configure = megasas_slave_configure, ++ .slave_alloc = megasas_slave_alloc, + .queuecommand = megasas_queue_command, + .eh_device_reset_handler = megasas_reset_device, + .eh_bus_reset_handler = megasas_reset_bus_host, + .eh_host_reset_handler = megasas_reset_bus_host, +- .eh_timed_out = megasas_reset_timer, + .bios_param = megasas_bios_param, + .use_clustering = ENABLE_CLUSTERING, + }; +@@ -1370,6 +1598,7 @@ + { + int exception = 0; + struct megasas_header *hdr = &cmd->frame->hdr; ++ int outstanding; + + if (cmd->scmd) + cmd->scmd->SCp.ptr = NULL; +@@ -1482,6 +1711,12 @@ + hdr->cmd); + break; + } ++ ++ if(instance->is_busy){ ++ outstanding = atomic_read(&instance->fw_outstanding); ++ if(outstanding<17) ++ instance->is_busy=0; ++ } + } + + /** +@@ -1536,6 +1771,7 @@ + u8 max_wait; + u32 fw_state; + u32 cur_state; ++ u32 abs_state, curr_abs_state; + + fw_state = instance->instancet->read_fw_status_reg(instance->reg_set) & MFI_STATE_MASK; + +@@ -1544,6 +1780,8 @@ + " state\n"); + + while (fw_state != MFI_STATE_READY) { ++ ++ abs_state = instance->instancet->read_fw_status_reg(instance->reg_set); + + switch (fw_state) { + +@@ -1556,18 +1794,31 @@ + /* + * Set the CLR bit in inbound doorbell + */ +- writel(MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG, +- &instance->reg_set->inbound_doorbell); +- +- max_wait = 2; ++ if ((instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0073SKINNY) || ++ (instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0071SKINNY)) ++ { ++ writel(MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG, ++ &instance->reg_set->reserved_0[0]); ++ } else { ++ writel(MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG, ++ &instance->reg_set->inbound_doorbell); ++ } ++ ++ max_wait = MEGASAS_RESET_WAIT_TIME; + cur_state = MFI_STATE_WAIT_HANDSHAKE; + break; + + case MFI_STATE_BOOT_MESSAGE_PENDING: +- writel(MFI_INIT_HOTPLUG, +- &instance->reg_set->inbound_doorbell); +- +- max_wait = 10; ++ if ((instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0073SKINNY) || ++ (instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0071SKINNY)) ++ { ++ writel(MFI_INIT_HOTPLUG, ++ &instance->reg_set->reserved_0[0]); ++ } else ++ writel(MFI_INIT_HOTPLUG, ++ &instance->reg_set->inbound_doorbell); ++ ++ max_wait = MEGASAS_RESET_WAIT_TIME; + cur_state = MFI_STATE_BOOT_MESSAGE_PENDING; + break; + +@@ -1576,9 +1827,14 @@ + * Bring it to READY state; assuming max wait 10 secs + */ + instance->instancet->disable_intr(instance->reg_set); +- writel(MFI_RESET_FLAGS, &instance->reg_set->inbound_doorbell); +- +- max_wait = 60; ++ if ((instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0073SKINNY) || ++ (instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0071SKINNY)) ++ { ++ writel(MFI_RESET_FLAGS, &instance->reg_set->reserved_0[0]); ++ } else ++ writel(MFI_RESET_FLAGS, &instance->reg_set->inbound_doorbell); ++ ++ max_wait = MEGASAS_RESET_WAIT_TIME; + cur_state = MFI_STATE_OPERATIONAL; + break; + +@@ -1586,32 +1842,32 @@ + /* + * This state should not last for more than 2 seconds + */ +- max_wait = 2; ++ max_wait = MEGASAS_RESET_WAIT_TIME; + cur_state = MFI_STATE_UNDEFINED; + break; + + case MFI_STATE_BB_INIT: +- max_wait = 2; ++ max_wait = MEGASAS_RESET_WAIT_TIME; + cur_state = MFI_STATE_BB_INIT; + break; + + case MFI_STATE_FW_INIT: +- max_wait = 20; ++ max_wait = MEGASAS_RESET_WAIT_TIME; + cur_state = MFI_STATE_FW_INIT; + break; + + case MFI_STATE_FW_INIT_2: +- max_wait = 20; ++ max_wait = MEGASAS_RESET_WAIT_TIME; + cur_state = MFI_STATE_FW_INIT_2; + break; + + case MFI_STATE_DEVICE_SCAN: +- max_wait = 20; ++ max_wait = MEGASAS_RESET_WAIT_TIME; + cur_state = MFI_STATE_DEVICE_SCAN; + break; + + case MFI_STATE_FLUSH_CACHE: +- max_wait = 20; ++ max_wait = MEGASAS_RESET_WAIT_TIME; + cur_state = MFI_STATE_FLUSH_CACHE; + break; + +@@ -1627,8 +1883,9 @@ + for (i = 0; i < (max_wait * 1000); i++) { + fw_state = instance->instancet->read_fw_status_reg(instance->reg_set) & + MFI_STATE_MASK ; +- +- if (fw_state == cur_state) { ++ curr_abs_state = instance->instancet->read_fw_status_reg(instance->reg_set); ++ ++ if (abs_state == curr_abs_state) { + msleep(1); + } else + break; +@@ -1637,7 +1894,7 @@ + /* + * Return error if fw_state hasn't changed after max_wait + */ +- if (fw_state == cur_state) { ++ if (curr_abs_state == abs_state) { + printk(KERN_DEBUG "FW state [%d] hasn't changed " + "in %d secs\n", fw_state, max_wait); + return -ENODEV; +@@ -1714,6 +1971,10 @@ + */ + sge_sz = (IS_DMA64) ? sizeof(struct megasas_sge64) : + sizeof(struct megasas_sge32); ++ ++ if (instance->flag_ieee) { ++ sge_sz = sizeof(struct megasas_sge_skinny); ++ } + + /* + * Calculated the number of 64byte frames required for SGL +@@ -1882,6 +2143,98 @@ + return 0; + } + ++ ++/* ++ * megasas_get_pd_list_info - Returns FW's pd_list structure ++ * @instance: Adapter soft state ++ * @pd_list: pd_list structure ++ * ++ * Issues an internal command (DCMD) to get the FW's controller PD ++ * list structure. This information is mainly used to find out SYSTEM ++ * supported by the FW. ++ */ ++static int ++megasas_get_pd_list(struct megasas_instance *instance) ++{ ++ int ret = 0, pd_index = 0; ++ struct megasas_cmd *cmd; ++ struct megasas_dcmd_frame *dcmd; ++ struct MR_PD_LIST *ci; ++ struct MR_PD_ADDRESS *pd_addr; ++ dma_addr_t ci_h = 0; ++ ++ cmd = megasas_get_cmd(instance); ++ ++ if (!cmd) { ++ printk(KERN_DEBUG "megasas (get_pd_list): Failed to get cmd\n"); ++ return -ENOMEM; ++ } ++ ++ dcmd = &cmd->frame->dcmd; ++ ++ ci = pci_alloc_consistent(instance->pdev, ++ MEGASAS_MAX_PD * sizeof(struct MR_PD_LIST), &ci_h); ++ ++ if (!ci) { ++ printk(KERN_DEBUG "Failed to alloc mem for pd_list\n"); ++ megasas_return_cmd(instance, cmd); ++ return -ENOMEM; ++ } ++ ++ memset(ci, 0, sizeof(*ci)); ++ memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); ++ ++ dcmd->mbox.b[0] = MR_PD_QUERY_TYPE_EXPOSED_TO_HOST; ++ dcmd->mbox.b[1] = 0; ++ dcmd->cmd = MFI_CMD_DCMD; ++ dcmd->cmd_status = 0xFF; ++ dcmd->sge_count = 1; ++ dcmd->flags = MFI_FRAME_DIR_READ; ++ dcmd->timeout = 0; ++ dcmd->data_xfer_len = MEGASAS_MAX_PD * sizeof(struct MR_PD_LIST); ++ dcmd->opcode = MR_DCMD_PD_LIST_QUERY; ++ dcmd->sgl.sge32[0].phys_addr = ci_h; ++ dcmd->sgl.sge32[0].length = MEGASAS_MAX_PD * sizeof(struct MR_PD_LIST); ++ ++ if (!megasas_issue_polled(instance, cmd)) { ++ ret = 0; ++ ++ } else { ++ ret = -1; ++ } ++ ++ /* ++ * the following function will get the instance PD LIST. ++ */ ++ ++ pd_addr = ci->addr; ++ ++ if ( ret == 0 && ++ (ci->count < (MEGASAS_MAX_PD_CHANNELS * MEGASAS_MAX_DEV_PER_CHANNEL))){ ++ ++ memset(instance->pd_list, 0, MEGASAS_MAX_PD * sizeof(struct megasas_pd_list)); ++ ++ for (pd_index = 0; pd_index < ci->count; pd_index++) { ++ ++ instance->pd_list[pd_addr->deviceId].tid =pd_addr->deviceId; ++ instance->pd_list[pd_addr->deviceId].driveType =pd_addr->scsiDevType; ++ instance->pd_list[pd_addr->deviceId].driveState =MR_PD_STATE_SYSTEM; ++ ++ pd_addr++; ++ ++ } ++ ++ } ++ ++ pci_free_consistent(instance->pdev, MEGASAS_MAX_PD * sizeof(struct MR_PD_LIST), ++ ci, ci_h); ++ ++ ++ megasas_return_cmd(instance, cmd); ++ ++ return ret; ++} ++ + /** + * megasas_get_controller_info - Returns FW's controller structure + * @instance: Adapter soft state +@@ -2081,6 +2434,8 @@ + * Map the message registers + */ + if ((instance->pdev->device == PCI_DEVICE_ID_LSI_SAS1078GEN2) || ++ (instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0071SKINNY) || ++ (instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0073SKINNY) || + (instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0079GEN2)) { + instance->base_addr = pci_resource_start(instance->pdev, 1); + } else { +@@ -2111,6 +2466,10 @@ + case PCI_DEVICE_ID_LSI_SAS0079GEN2: + instance->instancet = &megasas_instance_template_gen2; + break; ++ case PCI_DEVICE_ID_LSI_SAS0073SKINNY: ++ case PCI_DEVICE_ID_LSI_SAS0071SKINNY: ++ instance->instancet = &megasas_instance_template_skinny; ++ break; + case PCI_DEVICE_ID_LSI_SAS1064R: + case PCI_DEVICE_ID_DELL_PERC5: + default: +@@ -2128,6 +2487,7 @@ + * Get various operational parameters from status register + */ + instance->max_fw_cmds = instance->instancet->read_fw_status_reg(reg_set) & 0x00FFFF; ++ + /* + * Reduce the max supported cmds by 1. This is to ensure that the + * reply_q_sz (1 more than the max cmd that driver may send) +@@ -2165,6 +2525,13 @@ + + if (megasas_issue_init_mfi(instance)) + goto fail_fw_init; ++ ++ /** for passthrough ++ * the following function will get the PD LIST. ++ */ ++ ++ memset(instance->pd_list, 0, MEGASAS_MAX_PD * sizeof(struct megasas_pd_list)); ++ megasas_get_pd_list(instance); + + ctrl_info = kmalloc(sizeof(struct megasas_ctrl_info), GFP_KERNEL); + +@@ -2408,18 +2775,22 @@ + dcmd->mbox.w[1] = curr_aen.word; + dcmd->sgl.sge32[0].phys_addr = (u32) instance->evt_detail_h; + dcmd->sgl.sge32[0].length = sizeof(struct megasas_evt_detail); +- +- /* +- * Store reference to the cmd used to register for AEN. When an +- * application wants us to register for AEN, we have to abort this +- * cmd and re-register with a new EVENT LOCALE supplied by that app +- */ ++ ++ if ( instance->aen_cmd != NULL ) { ++ megasas_return_cmd(instance, cmd); ++ return 0; ++ } ++ /* ++ * Store reference to the cmd used to register for AEN. When an ++ * application wants us to register for AEN, we have to abort this ++ * cmd and re-register with a new EVENT LOCALE supplied by that app ++ */ + instance->aen_cmd = cmd; + + /* +- * Issue the aen registration frame +- */ +- instance->instancet->fire_cmd(cmd->frame_phys_addr ,0,instance->reg_set); ++ * Issue the aen registration frame ++ */ ++ instance->instancet->fire_cmd(instance, cmd->frame_phys_addr ,0,instance->reg_set); + + return 0; + } +@@ -2465,9 +2836,17 @@ + */ + host->irq = instance->pdev->irq; + host->unique_id = instance->unique_id; +- host->can_queue = instance->max_fw_cmds - MEGASAS_INT_CMDS; ++ if ((instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0073SKINNY) || ++ (instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0071SKINNY)) { ++ host->can_queue = instance->max_fw_cmds - MEGASAS_SKINNY_INT_CMDS; ++ } else ++ host->can_queue = instance->max_fw_cmds - MEGASAS_INT_CMDS; + host->this_id = instance->init_id; +- host->sg_tablesize = instance->max_num_sge; ++ if(instance->flag_ieee) { ++ host->sg_tablesize = 28; ++ } else { ++ host->sg_tablesize = instance->max_num_sge; ++ } + host->max_sectors = instance->max_sectors_per_req; + host->cmd_per_lun = 128; + host->max_channel = MEGASAS_MAX_CHANNELS - 1; +@@ -2572,6 +2951,9 @@ + + *instance->producer = 0; + *instance->consumer = 0; ++ instance->flag_ieee = 0; ++ megasas_poll_wait_aen = 0; ++ instance->is_busy=0; + + instance->evt_detail = pci_alloc_consistent(pdev, + sizeof(struct +@@ -2596,9 +2978,9 @@ + + spin_lock_init(&instance->cmd_pool_lock); + spin_lock_init(&instance->completion_lock); ++ spin_lock_init(&instance->fire_lock); + + mutex_init(&instance->aen_mutex); +- sema_init(&instance->ioctl_sem, MEGASAS_INT_CMDS); + + /* + * Initialize PCI related and misc parameters +@@ -2608,8 +2990,17 @@ + instance->unique_id = pdev->bus->number << 8 | pdev->devfn; + instance->init_id = MEGASAS_DEFAULT_INIT_ID; + ++ if ((instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0073SKINNY) || ++ (instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0071SKINNY)) { ++ instance->flag_ieee = 1; ++ sema_init(&instance->ioctl_sem, MEGASAS_SKINNY_INT_CMDS); ++ ++ } else ++ sema_init(&instance->ioctl_sem, MEGASAS_INT_CMDS); ++ + megasas_dbg_lvl = 0; + instance->flag = 0; ++ instance->unload = 1; + instance->last_time = 0; + + /* +@@ -2655,6 +3046,8 @@ + if (megasas_io_attach(instance)) + goto fail_io_attach; + ++ instance->unload = 0; ++ + return 0; + + fail_start_aen: +@@ -2777,6 +3170,7 @@ + struct megasas_instance *instance; + + instance = pci_get_drvdata(pdev); ++ instance->unload = 1; + host = instance->host; + + if (poll_mode_io) +@@ -2873,6 +3267,7 @@ + megasas_start_timer(instance, &instance->io_completion_timer, + megasas_io_completion_timer, + MEGASAS_COMPLETION_TIMER_INTERVAL); ++ instance->unload = 0; + return 0; + + fail_irq: +@@ -2913,6 +3308,7 @@ + struct megasas_instance *instance; + + instance = pci_get_drvdata(pdev); ++ instance->unload = 1; + host = instance->host; + + if (poll_mode_io) +@@ -2941,7 +3337,7 @@ + instance->instancet->disable_intr(instance->reg_set); + + free_irq(instance->pdev->irq, instance); +- ++ + megasas_release_mfi(instance); + + pci_free_consistent(pdev, sizeof(struct megasas_evt_detail), +@@ -2969,6 +3365,7 @@ + static void megasas_shutdown(struct pci_dev *pdev) + { + struct megasas_instance *instance = pci_get_drvdata(pdev); ++ instance->unload = 1; + megasas_flush_cache(instance); + megasas_shutdown_controller(instance, MR_DCMD_CTRL_SHUTDOWN); + } +@@ -2984,17 +3381,6 @@ + */ + if (!capable(CAP_SYS_ADMIN)) + return -EACCES; +- +- return 0; +-} +- +-/** +- * megasas_mgmt_release - char node "release" entry point +- */ +-static int megasas_mgmt_release(struct inode *inode, struct file *filep) +-{ +- filep->private_data = NULL; +- fasync_helper(-1, filep, 0, &megasas_async_queue); + + return 0; + } +@@ -3024,6 +3410,20 @@ + printk(KERN_DEBUG "megasas: fasync_helper failed [%d]\n", rc); + + return rc; ++} ++ ++/** ++ * megasas_mgmt_poll - char node "poll" entry point ++ * */ ++static unsigned int megasas_mgmt_poll(struct file *file, poll_table *wait) ++{ ++ unsigned int mask = 0; ++ poll_wait(file, &megasas_poll_wait, wait); ++ ++ if (megasas_poll_wait_aen) { ++ mask |= (POLLIN | POLLRDNORM); ++ } ++ return mask; + } + + /** +@@ -3043,7 +3443,7 @@ + int error = 0, i; + void *sense = NULL; + dma_addr_t sense_handle; +- u32 *sense_ptr; ++ unsigned long *sense_ptr; + + memset(kbuff_arr, 0, sizeof(kbuff_arr)); + +@@ -3067,6 +3467,7 @@ + */ + memcpy(cmd->frame, ioc->frame.raw, 2 * MEGAMFI_FRAME_SIZE); + cmd->frame->hdr.context = cmd->index; ++ cmd->frame->hdr.pad_0 = 0; + + /* + * The management interface between applications and the fw uses +@@ -3120,7 +3521,7 @@ + } + + sense_ptr = +- (u32 *) ((unsigned long)cmd->frame + ioc->sense_off); ++ (unsigned long *) ((unsigned long)cmd->frame + ioc->sense_off); + *sense_ptr = sense_handle; + } + +@@ -3151,8 +3552,8 @@ + * sense_ptr points to the location that has the user + * sense buffer address + */ +- sense_ptr = (u32 *) ((unsigned long)ioc->frame.raw + +- ioc->sense_off); ++ sense_ptr = (unsigned long *) ((unsigned long)ioc->frame.raw + ++ ioc->sense_off); + + if (copy_to_user((void __user *)((unsigned long)(*sense_ptr)), + sense, ioc->sense_len)) { +@@ -3188,20 +3589,6 @@ + return error; + } + +-static struct megasas_instance *megasas_lookup_instance(u16 host_no) +-{ +- int i; +- +- for (i = 0; i < megasas_mgmt_info.max_index; i++) { +- +- if ((megasas_mgmt_info.instance[i]) && +- (megasas_mgmt_info.instance[i]->host->host_no == host_no)) +- return megasas_mgmt_info.instance[i]; +- } +- +- return NULL; +-} +- + static int megasas_mgmt_ioctl_fw(struct file *file, unsigned long arg) + { + struct megasas_iocpacket __user *user_ioc = +@@ -3221,6 +3608,17 @@ + + instance = megasas_lookup_instance(ioc->host_no); + if (!instance) { ++ error = -ENODEV; ++ goto out_kfree_ioc; ++ } ++ ++ if (instance->hw_crit_error == 1) { ++ printk("Controller in crit error\n"); ++ error = -ENODEV; ++ goto out_kfree_ioc; ++ } ++ ++ if (instance->unload == 1) { + error = -ENODEV; + goto out_kfree_ioc; + } +@@ -3259,6 +3657,14 @@ + + if (!instance) + return -ENODEV; ++ ++ if (instance->hw_crit_error == 1) { ++ error = -ENODEV; ++ } ++ ++ if (instance->unload == 1) { ++ return -ENODEV; ++ } + + mutex_lock(&instance->aen_mutex); + error = megasas_register_aen(instance, aen.seq_num, +@@ -3346,9 +3752,9 @@ + static const struct file_operations megasas_mgmt_fops = { + .owner = THIS_MODULE, + .open = megasas_mgmt_open, +- .release = megasas_mgmt_release, + .fasync = megasas_mgmt_fasync, + .unlocked_ioctl = megasas_mgmt_ioctl, ++ .poll = megasas_mgmt_poll, + #ifdef CONFIG_COMPAT + .compat_ioctl = megasas_mgmt_compat_ioctl, + #endif +@@ -3390,6 +3796,15 @@ + NULL); + + static ssize_t ++megasas_sysfs_show_support_poll_for_event(struct device_driver *dd, char *buf) ++{ ++ return sprintf(buf, "%u\n", support_poll_for_event); ++} ++ ++static DRIVER_ATTR(support_poll_for_event, S_IRUGO, ++ megasas_sysfs_show_support_poll_for_event, NULL); ++ ++static ssize_t + megasas_sysfs_show_dbg_lvl(struct device_driver *dd, char *buf) + { + return sprintf(buf, "%u\n", megasas_dbg_lvl); +@@ -3463,6 +3878,99 @@ + return retval; + } + ++ ++static void ++megasas_aen_polling(struct work_struct *work) ++{ ++ struct Scsi_Host *host; ++ struct scsi_device *sdev1; ++ u16 pd_index = 0; ++ ++ struct megasas_aen_event *ev = ++ container_of(work, struct megasas_aen_event, hotplug_work); ++ struct megasas_instance *instance = ev->instance; ++ union megasas_evt_class_locale class_locale; ++ int i, j, doscan = 0; ++ u32 seq_num; ++ int error; ++ ++ if (!instance) { ++ printk(KERN_ERR "%s: invalid instance!\n", __FUNCTION__); ++ kfree(ev); ++ return; ++ } ++ ++ host = instance->host; ++ if (instance->evt_detail) { ++ ++ switch (instance->evt_detail->code) { ++ ++ case MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED: ++ doscan = 1; ++ break; ++ default: ++ doscan = 0; ++ break; ++ } ++ } else { ++ printk(KERN_ERR "%s[%d]: invalid evt_detail!\n", ++ __FUNCTION__, instance->host->host_no); ++ kfree(ev); ++ return; ++ } ++ ++ if (doscan) { ++ printk(KERN_INFO "%s[%d]: scanning ...\n", ++ __FUNCTION__, instance->host->host_no); ++ megasas_get_pd_list(instance); ++ for (i=0; i < MEGASAS_MAX_PD_CHANNELS; i++) { ++ for (j = 0; j < MEGASAS_MAX_DEV_PER_CHANNEL; j++) { ++ pd_index = (i * MEGASAS_MAX_DEV_PER_CHANNEL) + j; ++ sdev1 = scsi_device_lookup(host, i, j, 0); ++ if (instance->pd_list[pd_index].driveState == MR_PD_STATE_SYSTEM) { ++ if (!sdev1) { ++ scsi_add_device(host, i, j, 0); ++ } ++ } else { ++ if (sdev1) { ++ scsi_remove_device(sdev1); ++ scsi_device_put(sdev1); ++ } ++ } ++ } ++ } ++ } ++ ++ seq_num = instance->evt_detail->seq_num + 1; ++ ++ /** ++ * Register AEN with FW for latest sequence number plus 1 ++ **/ ++ ++ class_locale.members.reserved = 0; ++ class_locale.members.locale = MR_EVT_LOCALE_ALL; ++ class_locale.members.class = MR_EVT_CLASS_DEBUG; ++ ++ if ( instance->aen_cmd != NULL ) { ++ kfree(ev); ++ return ; ++ } ++ ++ mutex_lock(&instance->aen_mutex); ++ error = megasas_register_aen(instance, seq_num, ++ class_locale.word); ++ mutex_unlock(&instance->aen_mutex); ++ ++ ++ if (error) ++ printk(KERN_ERR "%s[%d]: register aen failed error %x\n", ++ __FUNCTION__, instance->host->host_no, error); ++ ++ kfree(ev); ++ ++} ++ ++ + static DRIVER_ATTR(poll_mode_io, S_IRUGO|S_IWUGO, + megasas_sysfs_show_poll_mode_io, + megasas_sysfs_set_poll_mode_io); +@@ -3480,6 +3988,8 @@ + printk(KERN_INFO "megasas: %s %s\n", MEGASAS_VERSION, + MEGASAS_EXT_VERSION); + ++ support_poll_for_event = 1; ++ + memset(&megasas_mgmt_info, 0, sizeof(megasas_mgmt_info)); + + /* +@@ -3512,6 +4022,12 @@ + &driver_attr_release_date); + if (rval) + goto err_dcf_rel_date; ++ ++ rval = driver_create_file(&megasas_pci_driver.driver, ++ &driver_attr_support_poll_for_event); ++ if (rval) ++ goto err_dcf_support_poll_for_event; ++ + rval = driver_create_file(&megasas_pci_driver.driver, + &driver_attr_dbg_lvl); + if (rval) +@@ -3529,6 +4045,10 @@ + err_dcf_dbg_lvl: + driver_remove_file(&megasas_pci_driver.driver, + &driver_attr_release_date); ++err_dcf_support_poll_for_event: ++ driver_remove_file(&megasas_pci_driver.driver, ++ &driver_attr_support_poll_for_event); ++ + err_dcf_rel_date: + driver_remove_file(&megasas_pci_driver.driver, &driver_attr_version); + err_dcf_attr_ver: +@@ -3548,6 +4068,8 @@ + driver_remove_file(&megasas_pci_driver.driver, + &driver_attr_dbg_lvl); + driver_remove_file(&megasas_pci_driver.driver, ++ &driver_attr_support_poll_for_event); ++ driver_remove_file(&megasas_pci_driver.driver, + &driver_attr_release_date); + driver_remove_file(&megasas_pci_driver.driver, &driver_attr_version); + +diff -r 4ebb3df27555 drivers/scsi/megaraid/megaraid_sas.h +--- a/drivers/scsi/megaraid/megaraid_sas.h Mon Oct 05 17:15:05 2009 +0100 ++++ b/drivers/scsi/megaraid/megaraid_sas.h Mon Oct 05 17:19:28 2009 +0100 +@@ -18,9 +18,9 @@ + /* + * MegaRAID SAS Driver meta data + */ +-#define MEGASAS_VERSION "00.00.04.01" +-#define MEGASAS_RELDATE "July 24, 2008" +-#define MEGASAS_EXT_VERSION "Thu July 24 11:41:51 PST 2008" ++#define MEGASAS_VERSION "00.00.04.12" ++#define MEGASAS_RELDATE "July 20, 2009" ++#define MEGASAS_EXT_VERSION "Mon. July 20, 11:41:51 PST 2009" + + /* + * Device IDs +@@ -30,6 +30,8 @@ + #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 + #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 + #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 ++#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 ++#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 + + /* + * ===================================== +@@ -94,6 +96,7 @@ + #define MFI_FRAME_DIR_WRITE 0x0008 + #define MFI_FRAME_DIR_READ 0x0010 + #define MFI_FRAME_DIR_BOTH 0x0018 ++#define MFI_FRAME_IEEE 0x0020 + + /* + * Definition for cmd_status +@@ -131,6 +134,18 @@ + #define MR_DCMD_CLUSTER 0x08000000 + #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 + #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 ++#define MR_DCMD_PD_LIST_QUERY 0x02010100 ++ ++#define MR_EVT_CFG_CLEARED 0x0004 ++ ++#define MR_EVT_LD_STATE_CHANGE 0x0051 ++#define MR_EVT_PD_INSERTED 0x005b ++#define MR_EVT_PD_REMOVED 0x0070 ++#define MR_EVT_LD_CREATED 0x008a ++#define MR_EVT_LD_DELETED 0x008b ++#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db ++#define MR_EVT_LD_OFFLINE 0x00fc ++#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 + + /* + * MFI command completion codes +@@ -251,8 +266,100 @@ + MR_EVT_ARGS_STR, + MR_EVT_ARGS_TIME, + MR_EVT_ARGS_ECC, ++ MR_EVT_ARGS_LD_PROP, ++ MR_EVT_ARGS_PD_SPARE, ++ MR_EVT_ARGS_PD_INDEX, ++ MR_EVT_ARGS_DIAG_PASS, ++ MR_EVT_ARGS_DIAG_FAIL, ++ MR_EVT_ARGS_PD_LBA_LBA, ++ MR_EVT_ARGS_PORT_PHY, ++ MR_EVT_ARGS_PD_MISSING, ++ MR_EVT_ARGS_PD_ADDRESS, ++ MR_EVT_ARGS_BITMAP, ++ MR_EVT_ARGS_CONNECTOR, ++ MR_EVT_ARGS_PD_PD, ++ MR_EVT_ARGS_PD_FRU, ++ MR_EVT_ARGS_PD_PATHINFO, ++ MR_EVT_ARGS_PD_POWER_STATE, ++ MR_EVT_ARGS_GENERIC, ++}; + ++/* ++ * define constants for device list query options ++ */ ++enum MR_PD_QUERY_TYPE { ++ MR_PD_QUERY_TYPE_ALL = 0, ++ MR_PD_QUERY_TYPE_STATE = 1, ++ MR_PD_QUERY_TYPE_POWER_STATE = 2, ++ MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, ++ MR_PD_QUERY_TYPE_SPEED = 4, ++ MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, ++} __attribute__ ((packed)); ++ ++#define MR_EVT_CFG_CLEARED 0x0004 ++#define MR_EVT_LD_STATE_CHANGE 0x0051 ++#define MR_EVT_PD_INSERTED 0x005b ++#define MR_EVT_PD_REMOVED 0x0070 ++#define MR_EVT_LD_CREATED 0x008a ++#define MR_EVT_LD_DELETED 0x008b ++#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db ++#define MR_EVT_LD_OFFLINE 0x00fc ++#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 ++ ++enum MR_PD_STATE { ++ MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, ++ MR_PD_STATE_UNCONFIGURED_BAD = 0x01, ++ MR_PD_STATE_HOT_SPARE = 0x02, ++ MR_PD_STATE_OFFLINE = 0x10, ++ MR_PD_STATE_FAILED = 0x11, ++ MR_PD_STATE_REBUILD = 0x14, ++ MR_PD_STATE_ONLINE = 0x18, ++ MR_PD_STATE_COPYBACK = 0x20, ++ MR_PD_STATE_SYSTEM = 0x40, + }; ++ ++/* ++ * defines the physical drive address structure ++ */ ++struct MR_PD_ADDRESS { ++ u16 deviceId; ++ u16 enclDeviceId; ++ ++ union { ++ struct { ++ ++ u8 enclIndex; ++ u8 slotNumber; ++ } mrPdAddress; ++ struct { ++ u8 enclPosition; ++ u8 enclConnectorIndex; ++ } mrEnclAddress; ++ }; ++ u8 scsiDevType; ++ union { ++ u8 connectedPortBitmap; ++ u8 connectedPortNumbers; ++ ++ }; ++ u64 sasAddr[2]; ++} __attribute__ ((packed)); ++ ++/* ++ * defines the physical drive list structure ++ */ ++struct MR_PD_LIST { ++ u32 size; ++ u32 count; ++ struct MR_PD_ADDRESS addr[1]; ++} __attribute__ ((packed)); ++ ++ ++struct megasas_pd_list { ++ u16 tid; ++ u8 driveType; ++ u8 driveState; ++} __attribute__ ((packed)); + + /* + * SAS controller properties +@@ -541,6 +648,9 @@ + #define MEGASAS_MAX_LUN 8 + #define MEGASAS_MAX_LD 64 + ++#define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ ++ MEGASAS_MAX_DEV_PER_CHANNEL) ++ + #define MEGASAS_DBG_LVL 1 + + #define MEGASAS_FW_BUSY 1 +@@ -570,6 +680,7 @@ + * is shown below + */ + #define MEGASAS_INT_CMDS 32 ++#define MEGASAS_SKINNY_INT_CMDS 5 + + /* + * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit +@@ -584,6 +695,9 @@ + #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 + #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 + #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) ++#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 ++#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) ++ + + /* + * register set for both 1068 and 1078 controllers +@@ -644,10 +758,19 @@ + + } __attribute__ ((packed)); + ++struct megasas_sge_skinny { ++ ++ u64 phys_addr; ++ u32 length; ++ u32 flag; ++ ++} __attribute__ ((packed)); ++ + union megasas_sgl { + + struct megasas_sge32 sge32[1]; + struct megasas_sge64 sge64[1]; ++ struct megasas_sge_skinny sge_skinny[1]; + + } __attribute__ ((packed)); + +@@ -1061,16 +1184,10 @@ + + } __attribute__ ((packed)); + +- struct megasas_instance_template { +- void (*fire_cmd)(dma_addr_t ,u32 ,struct megasas_register_set __iomem *); +- +- void (*enable_intr)(struct megasas_register_set __iomem *) ; +- void (*disable_intr)(struct megasas_register_set __iomem *); +- +- int (*clear_intr)(struct megasas_register_set __iomem *); +- +- u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); +- }; ++struct megasas_aen_event { ++ struct work_struct hotplug_work; ++ struct megasas_instance *instance; ++}; + + struct megasas_instance { + +@@ -1085,6 +1202,8 @@ + unsigned long base_addr; + struct megasas_register_set __iomem *reg_set; + ++ struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; ++ + s8 init_id; + + u16 max_num_sge; +@@ -1094,6 +1213,7 @@ + struct megasas_cmd **cmd_list; + struct list_head cmd_pool; + spinlock_t cmd_pool_lock; ++ spinlock_t fire_lock; + /* used to synch producer, consumer ptrs in dpc */ + spinlock_t completion_lock; + struct dma_pool *frame_dma_pool; +@@ -1120,10 +1240,24 @@ + struct tasklet_struct isr_tasklet; + + u8 flag; ++ u8 unload; ++ u8 flag_ieee; ++ u8 is_busy; + unsigned long last_time; + + struct timer_list io_completion_timer; + }; ++ ++ struct megasas_instance_template { ++ void (*fire_cmd)(struct megasas_instance *, dma_addr_t ,u32 ,struct megasas_register_set __iomem *); ++ ++ void (*enable_intr)(struct megasas_register_set __iomem *) ; ++ void (*disable_intr)(struct megasas_register_set __iomem *); ++ ++ int (*clear_intr)(struct megasas_register_set __iomem *); ++ ++ u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); ++ }; + + #define MEGASAS_IS_LOGICAL(scp) \ + (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 diff --git a/master/mlnx_en-1.4.1.patch b/master/mlnx_en-1.4.1.patch new file mode 100644 index 0000000..621d98e --- /dev/null +++ b/master/mlnx_en-1.4.1.patch @@ -0,0 +1,9250 @@ +diff -r 4e706462aff6 drivers/net/Kconfig +--- a/drivers/net/Kconfig Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/Kconfig Tue Oct 06 11:20:51 2009 +0100 +@@ -2518,6 +2518,12 @@ + depends on PCI + default n + ++config MLX4_EN ++ tristate "Mellanox MLX4 Ethernet Driver" ++ select MLX4_CORE ++ ---help--- ++ MLX4_EN driver ++ + config MLX4_DEBUG + bool "Verbose debugging output" if (MLX4_CORE && EMBEDDED) + depends on MLX4_CORE +diff -r 4e706462aff6 drivers/net/mlx4/Makefile +--- a/drivers/net/mlx4/Makefile Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/Makefile Tue Oct 06 11:20:51 2009 +0100 +@@ -1,4 +1,8 @@ + obj-$(CONFIG_MLX4_CORE) += mlx4_core.o + + mlx4_core-y := alloc.o catas.o cmd.o cq.o eq.o fw.o icm.o intf.o main.o mcg.o \ +- mr.o pd.o profile.o qp.o reset.o srq.o ++ mr.o pd.o profile.o qp.o reset.o srq.o port.o xrcd.o ++ ++obj-$(CONFIG_MLX4_EN) += mlx4_en.o ++ ++mlx4_en-y := en_main.o en_tx.o en_rx.o en_params.o en_port.o en_cq.o en_resources.o en_netdev.o en_frag.o en_lro.o +diff -r 4e706462aff6 drivers/net/mlx4/alloc.c +--- a/drivers/net/mlx4/alloc.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/alloc.c Tue Oct 06 11:20:51 2009 +0100 +@@ -47,13 +47,16 @@ + + obj = find_next_zero_bit(bitmap->table, bitmap->max, bitmap->last); + if (obj >= bitmap->max) { +- bitmap->top = (bitmap->top + bitmap->max) & bitmap->mask; ++ bitmap->top = (bitmap->top + bitmap->max + bitmap->reserved_top) ++ & bitmap->mask; + obj = find_first_zero_bit(bitmap->table, bitmap->max); + } + + if (obj < bitmap->max) { + set_bit(obj, bitmap->table); +- bitmap->last = (obj + 1) & (bitmap->max - 1); ++ bitmap->last = (obj + 1); ++ if (bitmap->last == bitmap->max) ++ bitmap->last = 0; + obj |= bitmap->top; + } else + obj = -1; +@@ -65,16 +68,86 @@ + + void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj) + { +- obj &= bitmap->max - 1; ++ mlx4_bitmap_free_range(bitmap, obj, 1); ++} ++ ++static unsigned long find_aligned_range(unsigned long *bitmap, ++ u32 start, u32 nbits, ++ int len, int align) ++{ ++ unsigned long end, i; ++ ++again: ++ start = ALIGN(start, align); ++ while ((start < nbits) && test_bit(start, bitmap)) ++ start += align; ++ if (start >= nbits) ++ return -1; ++ ++ end = start+len; ++ if (end > nbits) ++ return -1; ++ for (i = start+1; i < end; i++) { ++ if (test_bit(i, bitmap)) { ++ start = i+1; ++ goto again; ++ } ++ } ++ return start; ++} ++ ++u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align) ++{ ++ u32 obj, i; ++ ++ if (likely(cnt == 1 && align == 1)) ++ return mlx4_bitmap_alloc(bitmap); + + spin_lock(&bitmap->lock); +- clear_bit(obj, bitmap->table); ++ ++ obj = find_aligned_range(bitmap->table, bitmap->last, ++ bitmap->max, cnt, align); ++ if (obj >= bitmap->max) { ++ bitmap->top = (bitmap->top + bitmap->max + bitmap->reserved_top) ++ & bitmap->mask; ++ obj = find_aligned_range(bitmap->table, 0, bitmap->max, ++ cnt, align); ++ } ++ ++ if (obj < bitmap->max) { ++ for (i = 0; i < cnt; i++) ++ set_bit(obj+i, bitmap->table); ++ if (obj == bitmap->last) { ++ bitmap->last = (obj + cnt); ++ if (bitmap->last >= bitmap->max) ++ bitmap->last = 0; ++ } ++ obj |= bitmap->top; ++ } else ++ obj = -1; ++ ++ spin_unlock(&bitmap->lock); ++ ++ return obj; ++} ++ ++void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt) ++{ ++ u32 i; ++ ++ obj &= bitmap->max + bitmap->reserved_top - 1; ++ ++ spin_lock(&bitmap->lock); ++ for (i = 0; i < cnt; i++) ++ clear_bit(obj+i, bitmap->table); + bitmap->last = min(bitmap->last, obj); +- bitmap->top = (bitmap->top + bitmap->max) & bitmap->mask; ++ bitmap->top = (bitmap->top + bitmap->max + bitmap->reserved_top) ++ & bitmap->mask; + spin_unlock(&bitmap->lock); + } + +-int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, u32 reserved) ++int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, ++ u32 reserved_bot, u32 reserved_top) + { + int i; + +@@ -84,14 +157,16 @@ + + bitmap->last = 0; + bitmap->top = 0; +- bitmap->max = num; ++ bitmap->max = num - reserved_top; + bitmap->mask = mask; ++ bitmap->reserved_top = reserved_top; + spin_lock_init(&bitmap->lock); +- bitmap->table = kzalloc(BITS_TO_LONGS(num) * sizeof (long), GFP_KERNEL); ++ bitmap->table = kzalloc(BITS_TO_LONGS(bitmap->max) * ++ sizeof (long), GFP_KERNEL); + if (!bitmap->table) + return -ENOMEM; + +- for (i = 0; i < reserved; ++i) ++ for (i = 0; i < reserved_bot; ++i) + set_bit(i, bitmap->table); + + return 0; +diff -r 4e706462aff6 drivers/net/mlx4/catas.c +--- a/drivers/net/mlx4/catas.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/catas.c Tue Oct 06 11:20:51 2009 +0100 +@@ -45,7 +45,7 @@ + static struct workqueue_struct *catas_wq; + static struct work_struct catas_work; + +-static int internal_err_reset = 0; ++static int internal_err_reset = 1; + module_param(internal_err_reset, int, 0644); + MODULE_PARM_DESC(internal_err_reset, + "Reset device on internal errors if non-zero (default 1)"); +diff -r 4e706462aff6 drivers/net/mlx4/cmd.c +--- a/drivers/net/mlx4/cmd.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/cmd.c Tue Oct 06 11:20:51 2009 +0100 +@@ -106,6 +106,7 @@ + int next; + u64 out_param; + u16 token; ++ u8 fw_status; + }; + + static int mlx4_status_to_errno(u8 status) +@@ -212,6 +213,7 @@ + void __iomem *hcr = priv->cmd.hcr; + int err = 0; + unsigned long end; ++ u32 stat; + + down(&priv->cmd.poll_sem); + +@@ -235,9 +237,10 @@ + __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 | + (u64) be32_to_cpu((__force __be32) + __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4)); +- +- err = mlx4_status_to_errno(be32_to_cpu((__force __be32) +- __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24); ++ stat = be32_to_cpu((__force __be32) __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24; ++ err = mlx4_status_to_errno(stat); ++ if (err) ++ mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n", op, stat); + + out: + up(&priv->cmd.poll_sem); +@@ -254,6 +257,7 @@ + if (token != context->token) + return; + ++ context->fw_status = status; + context->result = mlx4_status_to_errno(status); + context->out_param = out_param; + +@@ -282,14 +286,18 @@ + mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0, + in_modifier, op_modifier, op, context->token, 1); + +- if (!wait_for_completion_timeout(&context->done, msecs_to_jiffies(timeout))) { +- err = -EBUSY; ++ if (!wait_for_completion_timeout(&context->done, msecs_to_jiffies(timeout))) ++ if (!context->done.done) { ++ err = -EBUSY; ++ goto out; ++ } ++ ++ err = context->result; ++ if (err) { ++ mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n", ++ op, context->fw_status); + goto out; + } +- +- err = context->result; +- if (err) +- goto out; + + if (out_is_imm) + *out_param = context->out_param; +diff -r 4e706462aff6 drivers/net/mlx4/cq.c +--- a/drivers/net/mlx4/cq.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/cq.c Tue Oct 06 11:20:51 2009 +0100 +@@ -187,9 +187,25 @@ + } + EXPORT_SYMBOL_GPL(mlx4_cq_resize); + ++static int mlx4_find_least_loaded_vector(struct mlx4_priv *priv) ++{ ++ int i; ++ int index = 0; ++ int min = priv->eq_table.eq[MLX4_EQ_COMP_CPU0].load; ++ ++ for (i = 1; i < priv->dev.caps.num_comp_vectors; i++) { ++ if (priv->eq_table.eq[MLX4_EQ_COMP_CPU0 + i].load < min) { ++ index = i; ++ min = priv->eq_table.eq[MLX4_EQ_COMP_CPU0 + i].load; ++ } ++ } ++ ++ return index; ++} ++ + int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, + struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, +- int collapsed) ++ unsigned vector, int collapsed) + { + struct mlx4_priv *priv = mlx4_priv(dev); + struct mlx4_cq_table *cq_table = &priv->cq_table; +@@ -227,7 +243,17 @@ + + cq_context->flags = cpu_to_be32(!!collapsed << 18); + cq_context->logsize_usrpage = cpu_to_be32((ilog2(nent) << 24) | uar->index); +- cq_context->comp_eqn = priv->eq_table.eq[MLX4_EQ_COMP].eqn; ++ ++ if (vector == MLX4_LEAST_ATTACHED_VECTOR) ++ vector = mlx4_find_least_loaded_vector(priv); ++ else if (vector >= dev->caps.num_comp_vectors) { ++ err = -EINVAL; ++ goto err_radix; ++ } ++ ++ cq->comp_eq_idx = MLX4_EQ_COMP_CPU0 + vector; ++ cq_context->comp_eqn = priv->eq_table.eq[MLX4_EQ_COMP_CPU0 + ++ vector].eqn; + cq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT; + + mtt_addr = mlx4_mtt_addr(dev, mtt); +@@ -240,6 +266,7 @@ + if (err) + goto err_radix; + ++ priv->eq_table.eq[cq->comp_eq_idx].load++; + cq->cons_index = 0; + cq->arm_sn = 1; + cq->uar = uar; +@@ -276,7 +303,8 @@ + if (err) + mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn); + +- synchronize_irq(priv->eq_table.eq[MLX4_EQ_COMP].irq); ++ synchronize_irq(priv->eq_table.eq[cq->comp_eq_idx].irq); ++ priv->eq_table.eq[cq->comp_eq_idx].load--; + + spin_lock_irq(&cq_table->lock); + radix_tree_delete(&cq_table->tree, cq->cqn); +@@ -300,7 +328,7 @@ + INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC); + + err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs, +- dev->caps.num_cqs - 1, dev->caps.reserved_cqs); ++ dev->caps.num_cqs - 1, dev->caps.reserved_cqs, 0); + if (err) + return err; + +diff -r 4e706462aff6 drivers/net/mlx4/en_cq.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/en_cq.c Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,153 @@ ++/* ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++#include ++#include ++#include ++ ++#include "mlx4_en.h" ++ ++static void mlx4_en_cq_event(struct mlx4_cq *cq, enum mlx4_event event) ++{ ++ return; ++} ++ ++ ++int mlx4_en_create_cq(struct mlx4_en_priv *priv, ++ struct mlx4_en_cq *cq, ++ int entries, int ring, enum cq_type mode) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int err; ++ ++ cq->size = entries; ++ if (mode == RX) { ++ cq->buf_size = cq->size * sizeof(struct mlx4_cqe); ++ cq->vector = (ring + priv->port) % ++ mdev->dev->caps.num_comp_vectors; ++ } else { ++ cq->buf_size = sizeof(struct mlx4_cqe); ++ cq->vector = MLX4_LEAST_ATTACHED_VECTOR; ++ } ++ cq->ring = ring; ++ cq->is_tx = mode; ++ if (priv->rx_ring[ring].use_frags) ++ cq->process_cq = mlx4_en_process_rx_cq; ++ else ++ cq->process_cq = mlx4_en_process_rx_cq_skb; ++ spin_lock_init(&cq->lock); ++ ++ err = mlx4_alloc_hwq_res(mdev->dev, &cq->wqres, ++ cq->buf_size, 2 * PAGE_SIZE); ++ if (err) ++ return err; ++ ++ err = mlx4_en_map_buffer(&cq->wqres.buf); ++ if (err) ++ mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size); ++ else ++ cq->buf = (struct mlx4_cqe *) cq->wqres.buf.direct.buf; ++ ++ return err; ++} ++ ++int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int err; ++ ++ cq->dev = mdev->pndev[priv->port]; ++ cq->mcq.set_ci_db = cq->wqres.db.db; ++ cq->mcq.arm_db = cq->wqres.db.db + 1; ++ *cq->mcq.set_ci_db = 0; ++ *cq->mcq.arm_db = 0; ++ memset(cq->buf, 0, cq->buf_size); ++ ++ err = mlx4_cq_alloc(mdev->dev, cq->size, &cq->wqres.mtt, &mdev->priv_uar, ++ cq->wqres.db.dma, &cq->mcq, cq->vector, cq->is_tx); ++ if (err) ++ return err; ++ ++ cq->mcq.comp = cq->is_tx ? mlx4_en_tx_irq : mlx4_en_rx_irq; ++ cq->mcq.event = mlx4_en_cq_event; ++ ++ if (cq->is_tx) { ++ init_timer(&cq->timer); ++ cq->timer.function = mlx4_en_poll_tx_cq; ++ cq->timer.data = (unsigned long) cq; ++ } else { ++ netif_napi_add(cq->dev, &cq->napi, mlx4_en_poll_rx_cq, 64); ++ napi_enable(&cq->napi); ++ } ++ ++ return 0; ++} ++ ++void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ ++ mlx4_en_unmap_buffer(&cq->wqres.buf); ++ mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size); ++ cq->buf_size = 0; ++ cq->buf = NULL; ++} ++ ++void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ ++ if (cq->is_tx) ++ del_timer(&cq->timer); ++ else ++ napi_disable(&cq->napi); ++ ++ mlx4_cq_free(mdev->dev, &cq->mcq); ++} ++ ++/* Set rx cq moderation parameters */ ++int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq) ++{ ++ return mlx4_cq_modify(priv->mdev->dev, &cq->mcq, ++ cq->moder_cnt, cq->moder_time); ++} ++ ++int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq) ++{ ++ mlx4_cq_arm(&cq->mcq, MLX4_CQ_DB_REQ_NOT, priv->mdev->uar_map, ++ &priv->mdev->uar_lock); ++ ++ return 0; ++} ++ ++ +diff -r 4e706462aff6 drivers/net/mlx4/en_frag.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/en_frag.c Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,211 @@ ++/* ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "mlx4_en.h" ++ ++ ++static struct mlx4_en_ipfrag *find_session(struct mlx4_en_rx_ring *ring, ++ struct iphdr *iph) ++{ ++ struct mlx4_en_ipfrag *session; ++ int i; ++ ++ for (i = 0; i < MLX4_EN_NUM_IPFRAG_SESSIONS; i++) { ++ session = &ring->ipfrag[i]; ++ if (session->fragments == NULL) ++ continue; ++ if (session->daddr == iph->daddr && ++ session->saddr == iph->saddr && ++ session->id == iph->id && ++ session->protocol == iph->protocol) { ++ return session; ++ } ++ } ++ return NULL; ++} ++ ++static struct mlx4_en_ipfrag *start_session(struct mlx4_en_rx_ring *ring, ++ struct iphdr *iph) ++{ ++ struct mlx4_en_ipfrag *session; ++ int index = -1; ++ int i; ++ ++ for (i = 0; i < MLX4_EN_NUM_IPFRAG_SESSIONS; i++) { ++ if (ring->ipfrag[i].fragments == NULL) { ++ index = i; ++ break; ++ } ++ } ++ if (index < 0) ++ return NULL; ++ ++ session = &ring->ipfrag[index]; ++ ++ return session; ++} ++ ++ ++static void flush_session(struct mlx4_en_priv *priv, ++ struct mlx4_en_ipfrag *session, ++ u16 more) ++{ ++ struct sk_buff *skb = session->fragments; ++ struct iphdr *iph = ip_hdr(skb); ++ struct net_device *dev = skb->dev; ++ ++ /* Update IP length and checksum */ ++ iph->tot_len = htons(session->total_len); ++ iph->frag_off = htons(more | (session->offset >> 3)); ++ iph->check = 0; ++ iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl); ++ ++ if (session->vlan) ++ vlan_hwaccel_receive_skb(skb, priv->vlgrp, ++ be16_to_cpu(session->sl_vid)); ++ else ++ netif_receive_skb(skb); ++ dev->last_rx = jiffies; ++ session->fragments = NULL; ++ session->last = NULL; ++} ++ ++ ++static inline void frag_append(struct mlx4_en_priv *priv, ++ struct mlx4_en_ipfrag *session, ++ struct sk_buff *skb, ++ unsigned int data_len) ++{ ++ struct sk_buff *parent = session->fragments; ++ ++ /* Update skb bookkeeping */ ++ parent->len += data_len; ++ parent->data_len += data_len; ++ session->total_len += data_len; ++ ++ skb_pull(skb, skb->len - data_len); ++ parent->truesize += skb->truesize; ++ ++ if (session->last) ++ session->last->next = skb; ++ else ++ skb_shinfo(parent)->frag_list = skb; ++ ++ session->last = skb; ++} ++ ++int mlx4_en_rx_frags(struct mlx4_en_priv *priv, struct mlx4_en_rx_ring *ring, ++ struct sk_buff *skb, struct mlx4_cqe *cqe) ++{ ++ struct mlx4_en_ipfrag *session; ++ struct iphdr *iph; ++ u16 ip_len; ++ u16 ip_hlen; ++ int data_len; ++ u16 offset; ++ ++ skb_reset_network_header(skb); ++ skb_reset_transport_header(skb); ++ iph = ip_hdr(skb); ++ ip_len = ntohs(iph->tot_len); ++ ip_hlen = iph->ihl * 4; ++ data_len = ip_len - ip_hlen; ++ offset = ntohs(iph->frag_off); ++ offset &= IP_OFFSET; ++ offset <<= 3; ++ ++ session = find_session(ring, iph); ++ if (unlikely(ip_fast_csum((u8 *)iph, iph->ihl))) { ++ if (session) ++ flush_session(priv, session, IP_MF); ++ return -EINVAL; ++ } ++ if (session) { ++ if (unlikely(session->offset + session->total_len != ++ offset + ip_hlen)) { ++ flush_session(priv, session, IP_MF); ++ goto new_session; ++ } ++ /* Packets smaller then 60 bytes are padded to that size ++ * Need to fix len field of the skb to fit the actual data size ++ * Since ethernet header already removed, the IP total length ++ * is exactly the data size (the skb is linear) ++ */ ++ skb->len = ip_len; ++ ++ frag_append(priv, session, skb, data_len); ++ } else { ++new_session: ++ session = start_session(ring, iph); ++ if (unlikely(!session)) ++ return -ENOSPC; ++ ++ session->fragments = skb; ++ session->daddr = iph->daddr; ++ session->saddr = iph->saddr; ++ session->id = iph->id; ++ session->protocol = iph->protocol; ++ session->total_len = ip_len; ++ session->offset = offset; ++ session->vlan = (priv->vlgrp && ++ (be32_to_cpu(cqe->vlan_my_qpn) & ++ MLX4_CQE_VLAN_PRESENT_MASK)) ? 1 : 0; ++ session->sl_vid = cqe->sl_vid; ++ } ++ if (!(ntohs(iph->frag_off) & IP_MF)) ++ flush_session(priv, session, 0); ++ else if (session->fragments->len + priv->dev->mtu > 65536) ++ flush_session(priv, session, IP_MF); ++ ++ return 0; ++} ++ ++ ++void mlx4_en_flush_frags(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring) ++{ ++ struct mlx4_en_ipfrag *session; ++ int i; ++ ++ for (i = 0; i < MLX4_EN_NUM_IPFRAG_SESSIONS; i++) { ++ session = &ring->ipfrag[i]; ++ if (session->fragments) ++ flush_session(priv, session, IP_MF); ++ } ++} +diff -r 4e706462aff6 drivers/net/mlx4/en_lro.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/en_lro.c Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,540 @@ ++/* ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mlx4_en.h" ++ ++/* LRO hash function - using sum of source and destination port LSBs is ++ * good enough */ ++#define LRO_INDEX(th, size) \ ++ ((*((u8*) &th->source + 1) + *((u8*) &th->dest + 1)) & (size - 1)) ++ ++/* #define CONFIG_MLX4_EN_DEBUG_LRO */ ++ ++#ifdef CONFIG_MLX4_EN_DEBUG_LRO ++static void mlx4_en_lro_validate(struct mlx4_en_priv* priv, struct mlx4_en_lro *lro) ++{ ++ int i; ++ int size, size2; ++ struct sk_buff *skb = lro->skb; ++ skb_frag_t *frags; ++ int len, len2; ++ int cur_skb = 0; ++ ++ /* Sum fragment sizes of first skb */ ++ len = skb->len; ++ size = skb_headlen(skb); ++ frags = skb_shinfo(skb)->frags; ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { ++ size += frags[i].size; ++ } ++ ++ /* Add in fragments of linked skb's */ ++ skb = skb_shinfo(skb)->frag_list; ++ while (skb) { ++ cur_skb++; ++ len2 = skb->len; ++ if (skb_headlen(skb)) { ++ mlx4_err(priv->mdev, "Bad LRO format: non-zero headlen " ++ "in fraglist (skb:%d)\n", cur_skb); ++ return; ++ } ++ ++ size2 = 0; ++ frags = skb_shinfo(skb)->frags; ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { ++ size2 += frags[i].size; ++ } ++ ++ if (size2 != len2) { ++ mlx4_err(priv->mdev, "Bad skb size:%d in LRO fraglist. " ++ "Expected:%d (skb:%d)\n", size2, len2, cur_skb); ++ return; ++ } ++ size += size2; ++ skb = skb->next; ++ } ++ ++ if (size != len) ++ mlx4_err(priv->mdev, "Bad LRO size:%d expected:%d\n", size, len); ++} ++#endif /* MLX4_EN_DEBUG_LRO */ ++ ++static void mlx4_en_lro_flush_single(struct mlx4_en_priv* priv, ++ struct mlx4_en_rx_ring* ring, struct mlx4_en_lro *lro) ++{ ++ struct sk_buff *skb = lro->skb; ++ struct iphdr *iph = (struct iphdr *) skb->data; ++ struct tcphdr *th = (struct tcphdr *)(iph + 1); ++ unsigned int headlen = skb_headlen(skb); ++ __wsum tcp_hdr_csum; ++ u32 *ts; ++ ++ /* Update IP length and checksum */ ++ iph->tot_len = htons(lro->tot_len); ++ iph->check = 0; ++ iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl); ++ ++ /* Update latest TCP ack, window, psh, and timestamp */ ++ th->ack_seq = lro->ack_seq; ++ th->window = lro->window; ++ th->psh = !!lro->psh; ++ if (lro->has_timestamp) { ++ ts = (u32 *) (th + 1); ++ ts[1] = htonl(lro->tsval); ++ ts[2] = lro->tsecr; ++ } ++ th->check = 0; ++ tcp_hdr_csum = csum_partial((u8 *)th, th->doff << 2, 0); ++ lro->data_csum = csum_add(lro->data_csum, tcp_hdr_csum); ++ th->check = csum_tcpudp_magic(iph->saddr, iph->daddr, ++ lro->tot_len - (iph->ihl << 2), ++ IPPROTO_TCP, lro->data_csum); ++ ++ /* Update skb */ ++ skb->len = lro->tot_len; ++ skb->data_len = lro->tot_len - headlen; ++ skb->truesize = skb->len + sizeof(struct sk_buff); ++ skb_shinfo(skb)->gso_size = lro->mss; ++ ++#ifdef CONFIG_MLX4_EN_DEBUG_LRO ++ mlx4_en_lro_validate(priv, lro); ++#endif /* CONFIG_MLX4_EN_DEBUG_LRO */ ++ ++ /* Push it up the stack */ ++ if (priv->vlgrp && lro->has_vlan) ++ vlan_hwaccel_receive_skb(skb, priv->vlgrp, ++ be16_to_cpu(lro->vlan_prio)); ++ else ++ netif_receive_skb(skb); ++ priv->dev->last_rx = jiffies; ++ ++ /* Increment stats */ ++ priv->port_stats.lro_flushed++; ++ ++ /* Move session back to the free list */ ++ hlist_del(&lro->node); ++ hlist_del(&lro->flush_node); ++ hlist_add_head(&lro->node, &ring->lro_free); ++} ++ ++void mlx4_en_lro_flush(struct mlx4_en_priv* priv, struct mlx4_en_rx_ring *ring, u8 all) ++{ ++ struct mlx4_en_lro *lro; ++ struct hlist_node *node, *tmp; ++ ++ hlist_for_each_entry_safe(lro, node, tmp, &ring->lro_flush, flush_node) { ++ if (all || time_after(jiffies, lro->expires)) ++ mlx4_en_lro_flush_single(priv, ring, lro); ++ } ++} ++ ++static inline int mlx4_en_lro_append(struct mlx4_en_priv *priv, ++ struct mlx4_en_lro *lro, ++ struct mlx4_en_rx_desc *rx_desc, ++ struct skb_frag_struct *skb_frags, ++ struct mlx4_en_rx_alloc *page_alloc, ++ unsigned int data_len, ++ int hlen) ++{ ++ struct sk_buff *skb = lro->skb_last; ++ struct skb_shared_info *info; ++ struct skb_frag_struct *frags_copy; ++ int nr_frags; ++ ++ if (skb_shinfo(skb)->nr_frags + priv->num_frags > MAX_SKB_FRAGS) ++ return -ENOMEM; ++ ++ info = skb_shinfo(skb); ++ ++ /* Copy fragments from descriptor ring to skb */ ++ frags_copy = info->frags + info->nr_frags; ++ nr_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags, ++ frags_copy, ++ page_alloc, ++ data_len + hlen); ++ if (!nr_frags) { ++ mlx4_dbg(DRV, priv, "Failed completing rx desc during LRO append\n"); ++ return -ENOMEM; ++ } ++ ++ /* Skip over headers */ ++ frags_copy[0].page_offset += hlen; ++ ++ if (nr_frags == 1) ++ frags_copy[0].size = data_len; ++ else { ++ /* Adjust size of last fragment to match packet length. ++ * Note: if this fragment is also the first one, the ++ * operation is completed in the next line */ ++ frags_copy[nr_frags - 1].size = hlen + data_len - ++ priv->frag_info[nr_frags - 1].frag_prefix_size; ++ ++ /* Adjust size of first fragment */ ++ frags_copy[0].size -= hlen; ++ } ++ ++ /* Update skb bookkeeping */ ++ skb->len += data_len; ++ skb->data_len += data_len; ++ info->nr_frags += nr_frags; ++ return 0; ++} ++ ++static inline struct mlx4_en_lro *mlx4_en_lro_find_session(struct mlx4_en_dev *mdev, ++ struct mlx4_en_rx_ring *ring, ++ struct iphdr *iph, ++ struct tcphdr *th) ++{ ++ struct mlx4_en_lro *lro; ++ struct hlist_node *node; ++ int index = LRO_INDEX(th, mdev->profile.num_lro); ++ struct hlist_head *list = &ring->lro_hash[index]; ++ ++ hlist_for_each_entry(lro, node, list, node) { ++ if (lro->sport_dport == *((u32*) &th->source) && ++ lro->saddr == iph->saddr && ++ lro->daddr == iph->daddr) ++ return lro; ++ } ++ return NULL; ++} ++ ++static inline struct mlx4_en_lro *mlx4_en_lro_alloc_session(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring) ++{ ++ return hlist_empty(&ring->lro_free) ? NULL : ++ hlist_entry(ring->lro_free.first, struct mlx4_en_lro, node); ++} ++ ++static __wsum mlx4_en_lro_tcp_data_csum(struct iphdr *iph, ++ struct tcphdr *th, int len) ++{ ++ __wsum tcp_csum; ++ __wsum tcp_hdr_csum; ++ __wsum tcp_ps_hdr_csum; ++ ++ tcp_csum = ~csum_unfold(th->check); ++ tcp_hdr_csum = csum_partial((u8 *)th, th->doff << 2, tcp_csum); ++ ++ tcp_ps_hdr_csum = csum_tcpudp_nofold(iph->saddr, iph->daddr, ++ len + (th->doff << 2), ++ IPPROTO_TCP, 0); ++ ++ return csum_sub(csum_sub(tcp_csum, tcp_hdr_csum), ++ tcp_ps_hdr_csum); ++} ++ ++int mlx4_en_lro_rx(struct mlx4_en_priv *priv, struct mlx4_en_rx_ring *ring, ++ struct mlx4_en_rx_desc *rx_desc, ++ struct skb_frag_struct *skb_frags, ++ unsigned int length, ++ struct mlx4_cqe *cqe) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_en_lro *lro; ++ struct sk_buff *skb; ++ struct iphdr *iph; ++ struct tcphdr *th; ++ dma_addr_t dma; ++ int tcp_hlen; ++ int tcp_data_len; ++ int hlen; ++ u16 ip_len; ++ void *va; ++ u32 *ts; ++ u32 seq; ++ u32 tsval = (u32) ~0UL; ++ u32 tsecr = 0; ++ u32 ack_seq; ++ u16 window; ++ ++ /* This packet is eligible for LRO if it is: ++ * - DIX Ethernet (type interpretation) ++ * - TCP/IP (v4) ++ * - without IP options ++ * - not an IP fragment */ ++ if (!mlx4_en_can_lro(cqe->status)) ++ return -1; ++ ++ /* Get pointer to TCP header. We already know that the packet is DIX Ethernet/IPv4/TCP ++ * with no VLAN (HW stripped it) and no IP options */ ++ va = page_address(skb_frags[0].page) + skb_frags[0].page_offset; ++ iph = va + ETH_HLEN; ++ th = (struct tcphdr *)(iph + 1); ++ ++ /* Synchronsize headers for processing */ ++ dma = be64_to_cpu(rx_desc->data[0].addr); ++#define MAX_LRO_HEADER (ETH_HLEN + \ ++ sizeof(*iph) + \ ++ sizeof(*th) + \ ++ TCPOLEN_TSTAMP_ALIGNED) ++ dma_sync_single_range_for_cpu(&mdev->pdev->dev, dma, 0, ++ MAX_LRO_HEADER, DMA_FROM_DEVICE); ++ ++ /* We only handle aligned timestamp options */ ++ tcp_hlen = (th->doff << 2); ++ if (tcp_hlen == sizeof(*th) + TCPOLEN_TSTAMP_ALIGNED) { ++ ts = (u32*) (th + 1); ++ if (unlikely(*ts != htonl((TCPOPT_NOP << 24) | ++ (TCPOPT_NOP << 16) | ++ (TCPOPT_TIMESTAMP << 8) | ++ TCPOLEN_TIMESTAMP))) ++ goto sync_device; ++ tsval = ntohl(ts[1]); ++ tsecr = ts[2]; ++ } else if (tcp_hlen != sizeof(*th)) ++ goto sync_device; ++ ++ ++ /* At this point we know we have a TCP packet that is likely to be ++ * eligible for LRO. Therefore, see now if we have an oustanding ++ * session that corresponds to this packet so we could flush it if ++ * something still prevents LRO */ ++ lro = mlx4_en_lro_find_session(mdev, ring, iph, th); ++ ++ /* ensure no bits set besides ack or psh */ ++ if (th->fin || th->syn || th->rst || th->urg || th->ece || ++ th->cwr || !th->ack) { ++ if (lro) { ++ /* First flush session to keep packets in-order */ ++ mlx4_en_lro_flush_single(priv, ring, lro); ++ } ++ goto sync_device; ++ } ++ ++ /* Get ip length and verify that the frame is big enough */ ++ ip_len = ntohs(iph->tot_len); ++ if (unlikely(length < ETH_HLEN + ip_len)) { ++ mlx4_warn(mdev, "Cannot LRO - ip payload exceeds frame!\n"); ++ goto sync_device; ++ } ++ ++ /* Get TCP payload length */ ++ tcp_data_len = ip_len - tcp_hlen - sizeof(struct iphdr); ++ seq = ntohl(th->seq); ++ if (!tcp_data_len) ++ goto flush_session; ++ ++ if (lro) { ++ /* Check VLAN tag */ ++ if (cqe->vlan_my_qpn & MLX4_CQE_VLAN_PRESENT_MASK) { ++ if (cqe->sl_vid != lro->vlan_prio || !lro->has_vlan) { ++ mlx4_en_lro_flush_single(priv, ring, lro); ++ goto sync_device; ++ } ++ } else if (lro->has_vlan) { ++ mlx4_en_lro_flush_single(priv, ring, lro); ++ goto sync_device; ++ } ++ ++ /* Check sequence number */ ++ if (unlikely(seq != lro->next_seq)) { ++ mlx4_en_lro_flush_single(priv, ring, lro); ++ goto sync_device; ++ } ++ ++ /* If the cummulative IP length is over 64K, flush and start ++ * a new session */ ++ if (lro->tot_len + tcp_data_len > 0xffff) { ++ mlx4_en_lro_flush_single(priv, ring, lro); ++ goto new_session; ++ } ++ ++ /* Check timestamps */ ++ if (tcp_hlen != sizeof(*th)) { ++ if (unlikely(lro->tsval > tsval || !tsecr)) ++ goto sync_device; ++ } ++ ++ window = th->window; ++ ack_seq = th->ack_seq; ++ if (likely(tcp_data_len)) { ++ /* Append the data! */ ++ hlen = ETH_HLEN + sizeof(struct iphdr) + tcp_hlen; ++ if (mlx4_en_lro_append(priv, lro, rx_desc, skb_frags, ++ ring->page_alloc, ++ tcp_data_len, hlen)) { ++ mlx4_en_lro_flush_single(priv, ring, lro); ++ goto sync_device; ++ } ++ } else { ++ /* No data */ ++ dma_sync_single_range_for_device(&mdev->dev->pdev->dev, dma, ++ 0, MAX_LRO_HEADER, ++ DMA_FROM_DEVICE); ++ } ++ ++ /* Update session */ ++ lro->psh |= th->psh; ++ lro->next_seq += tcp_data_len; ++ lro->data_csum = csum_block_add(lro->data_csum, ++ mlx4_en_lro_tcp_data_csum(iph, th, ++ tcp_data_len), ++ lro->tot_len); ++ lro->tot_len += tcp_data_len; ++ lro->tsval = tsval; ++ lro->tsecr = tsecr; ++ lro->ack_seq = ack_seq; ++ lro->window = window; ++ if (tcp_data_len > lro->mss) ++ lro->mss = tcp_data_len; ++ priv->port_stats.lro_aggregated++; ++ if (th->psh) ++ mlx4_en_lro_flush_single(priv, ring, lro); ++ return 0; ++ } ++ ++new_session: ++ if (th->psh) ++ goto sync_device; ++ lro = mlx4_en_lro_alloc_session(priv, ring); ++ if (lro) { ++ skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags, ring->page_alloc, ++ ETH_HLEN + ip_len); ++ if (skb) { ++ int index; ++ ++ /* Add in the skb */ ++ lro->skb = skb; ++ lro->skb_last = skb; ++ skb->protocol = eth_type_trans(skb, priv->dev); ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ ++ /* Initialize session */ ++ lro->saddr = iph->saddr; ++ lro->daddr = iph->daddr; ++ lro->sport_dport = *((u32*) &th->source); ++ ++ lro->next_seq = seq + tcp_data_len; ++ lro->tot_len = ip_len; ++ lro->psh = th->psh; ++ lro->ack_seq = th->ack_seq; ++ lro->window = th->window; ++ lro->mss = tcp_data_len; ++ lro->data_csum = mlx4_en_lro_tcp_data_csum(iph, th, ++ tcp_data_len); ++ ++ /* Handle vlans */ ++ if (cqe->vlan_my_qpn & MLX4_CQE_VLAN_PRESENT_MASK) { ++ lro->vlan_prio = cqe->sl_vid; ++ lro->has_vlan = 1; ++ } else ++ lro->has_vlan = 0; ++ ++ /* Handle timestamps */ ++ if (tcp_hlen != sizeof(*th)) { ++ lro->tsval = tsval; ++ lro->tsecr = tsecr; ++ lro->has_timestamp = 1; ++ } else { ++ lro->tsval = (u32) ~0UL; ++ lro->has_timestamp = 0; ++ } ++ ++ /* Activate this session */ ++ lro->expires = jiffies + HZ / 25; ++ hlist_del(&lro->node); ++ index = LRO_INDEX(th, mdev->profile.num_lro); ++ ++ hlist_add_head(&lro->node, &ring->lro_hash[index]); ++ hlist_add_head(&lro->flush_node, &ring->lro_flush); ++ priv->port_stats.lro_aggregated++; ++ return 0; ++ } else { ++ /* Packet is dropped because we were not able to allocate new ++ * page for fragments */ ++ dma_sync_single_range_for_device(&mdev->pdev->dev, dma, ++ 0, MAX_LRO_HEADER, ++ DMA_FROM_DEVICE); ++ return 0; ++ } ++ } else { ++ priv->port_stats.lro_no_desc++; ++ } ++ ++flush_session: ++ if (lro) ++ mlx4_en_lro_flush_single(priv, ring, lro); ++sync_device: ++ dma_sync_single_range_for_device(&mdev->pdev->dev, dma, 0, ++ MAX_LRO_HEADER, DMA_FROM_DEVICE); ++ return -1; ++} ++ ++void mlx4_en_lro_destroy(struct mlx4_en_rx_ring *ring) ++{ ++ struct mlx4_en_lro *lro; ++ struct hlist_node *node, *tmp; ++ ++ hlist_for_each_entry_safe(lro, node, tmp, &ring->lro_free, node) { ++ hlist_del(&lro->node); ++ kfree(lro); ++ } ++ kfree(ring->lro_hash); ++} ++ ++int mlx4_en_lro_init(struct mlx4_en_rx_ring *ring, int num_lro) ++{ ++ struct mlx4_en_lro *lro; ++ int i; ++ ++ INIT_HLIST_HEAD(&ring->lro_free); ++ INIT_HLIST_HEAD(&ring->lro_flush); ++ ring->lro_hash = kmalloc(sizeof(struct hlist_head) * num_lro, ++ GFP_KERNEL); ++ if (!ring->lro_hash) ++ return -ENOMEM; ++ ++ for (i = 0; i < num_lro; i++) { ++ INIT_HLIST_HEAD(&ring->lro_hash[i]); ++ lro = kzalloc(sizeof(struct mlx4_en_lro), GFP_KERNEL); ++ if (!lro) { ++ mlx4_en_lro_destroy(ring); ++ return -ENOMEM; ++ } ++ INIT_HLIST_NODE(&lro->node); ++ INIT_HLIST_NODE(&lro->flush_node); ++ hlist_add_head(&lro->node, &ring->lro_free); ++ } ++ return 0; ++} ++ ++ +diff -r 4e706462aff6 drivers/net/mlx4/en_main.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/en_main.c Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,265 @@ ++/* ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "mlx4_en.h" ++ ++MODULE_AUTHOR("Liran Liss, Yevgeny Petrilin"); ++MODULE_DESCRIPTION("Mellanox ConnectX HCA Ethernet driver"); ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_VERSION(DRV_VERSION " ("DRV_RELDATE")"); ++ ++static const char mlx4_en_version[] __devinitdata = ++ DRV_NAME ": Mellanox ConnectX HCA Ethernet driver v" ++ DRV_VERSION " (" DRV_RELDATE ")\n"; ++ ++static void mlx4_en_event(struct mlx4_dev *dev, void *endev_ptr, ++ enum mlx4_dev_event event, int port) ++{ ++ struct mlx4_en_dev *mdev = (struct mlx4_en_dev *) endev_ptr; ++ struct mlx4_en_priv *priv; ++ ++ if (!mdev->pndev[port]) ++ return; ++ ++ priv = netdev_priv(mdev->pndev[port]); ++ switch (event) { ++ case MLX4_DEV_EVENT_PORT_UP: ++ case MLX4_DEV_EVENT_PORT_DOWN: ++ /* To prevent races, we poll the link state in a separate ++ task rather than changing it here */ ++ priv->link_state = event; ++ queue_work(mdev->workqueue, &priv->linkstate_task); ++ break; ++ ++ case MLX4_DEV_EVENT_CATASTROPHIC_ERROR: ++ mlx4_err(mdev, "Internal error detected, restarting device\n"); ++ break; ++ ++ default: ++ mlx4_warn(mdev, "Unhandled event: %d\n", event); ++ } ++} ++ ++static void mlx4_en_remove(struct mlx4_dev *dev, void *endev_ptr) ++{ ++ struct mlx4_en_dev *mdev = endev_ptr; ++ int i; ++ ++ mutex_lock(&mdev->state_lock); ++ mdev->device_up = false; ++ mutex_unlock(&mdev->state_lock); ++ ++ mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) ++ if (mdev->pndev[i]) ++ mlx4_en_destroy_netdev(mdev->pndev[i]); ++ ++ flush_workqueue(mdev->workqueue); ++ destroy_workqueue(mdev->workqueue); ++ mlx4_mr_free(dev, &mdev->mr); ++ mlx4_uar_free(dev, &mdev->priv_uar); ++ mlx4_pd_free(dev, mdev->priv_pdn); ++ kfree(mdev); ++} ++ ++static void *mlx4_en_add(struct mlx4_dev *dev) ++{ ++ static int mlx4_en_version_printed; ++ struct mlx4_en_dev *mdev; ++ int i; ++ int err; ++ ++ if (!mlx4_en_version_printed) { ++ printk(KERN_INFO "%s", mlx4_en_version); ++ mlx4_en_version_printed++; ++ } ++ ++ mdev = kzalloc(sizeof *mdev, GFP_KERNEL); ++ if (!mdev) { ++ dev_err(&dev->pdev->dev, "Device struct alloc failed, " ++ "aborting.\n"); ++ err = -ENOMEM; ++ goto err_free_res; ++ } ++ ++ if (mlx4_pd_alloc(dev, &mdev->priv_pdn)) ++ goto err_free_dev; ++ ++ if (mlx4_uar_alloc(dev, &mdev->priv_uar)) ++ goto err_pd; ++ ++ mdev->uar_map = ioremap(mdev->priv_uar.pfn << PAGE_SHIFT, PAGE_SIZE); ++ if (!mdev->uar_map) ++ goto err_uar; ++ spin_lock_init(&mdev->uar_lock); ++ ++ mdev->dev = dev; ++ mdev->dma_device = &(dev->pdev->dev); ++ mdev->pdev = dev->pdev; ++ mdev->device_up = false; ++ ++ mdev->LSO_support = !!(dev->caps.flags & (1 << 15)); ++ if (!mdev->LSO_support) ++ mlx4_warn(mdev, "LSO not supported, please upgrade to later " ++ "FW version to enable LSO\n"); ++ ++ if(mlx4_mr_alloc(mdev->dev, mdev->priv_pdn, 0, ~0ull, ++ MLX4_PERM_LOCAL_WRITE | MLX4_PERM_LOCAL_READ, ++ 0, 0, &mdev->mr)){ ++ mlx4_err(mdev, "Failed allocating memory region\n"); ++ goto err_uar; ++ } ++ if(mlx4_mr_enable(mdev->dev, &mdev->mr)){ ++ mlx4_err(mdev, "Failed enabling memory region\n"); ++ goto err_mr; ++ } ++ ++ /* Build device profile according to supplied module parameters */ ++ err = mlx4_en_get_profile(mdev); ++ if (err) { ++ mlx4_err(mdev, "Bad module parameters, aborting.\n"); ++ goto err_mr; ++ } ++ ++ /* Configure wich ports to start according to module parameters */ ++ mdev->port_cnt = 0; ++ mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) ++ mdev->port_cnt++; ++ ++ /* Number of RX rings is the minimum between: ++ * number of completion vextors + 1 (for default ring) ++ * and MAX_RX_RINGS */ ++ mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { ++ mlx4_info(mdev, "Using %d tx rings for port:%d\n", ++ mdev->profile.prof[i].tx_ring_num, i); ++ mdev->profile.prof[i].rx_ring_num = ++ min_t(int, dev->caps.num_comp_vectors + 1, MAX_RX_RINGS); ++ mlx4_info(mdev, "Defaulting to %d rx rings for port:%d\n", ++ mdev->profile.prof[i].rx_ring_num, i); ++ } ++ ++ /* Create our own workqueue for reset/multicast tasks ++ * Note: we cannot use the shared workqueue because of deadlocks caused ++ * by the rtnl lock */ ++ mdev->workqueue = create_singlethread_workqueue("mlx4_en"); ++ if (!mdev->workqueue) { ++ err = -ENOMEM; ++ goto err_mr; ++ } ++ ++ /* At this stage all non-port specific tasks are complete: ++ * mark the card state as up */ ++ mutex_init(&mdev->state_lock); ++ mdev->device_up = true; ++ ++ /* Setup ports */ ++ ++ /* Create a netdev for each port */ ++ mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { ++ mlx4_info(mdev, "Activating port:%d\n", i); ++ if (mlx4_en_init_netdev(mdev, i, &mdev->profile.prof[i])) { ++ mdev->pndev[i] = NULL; ++ goto err_free_netdev; ++ } ++ } ++ return mdev; ++ ++ ++err_free_netdev: ++ mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { ++ if (mdev->pndev[i]) ++ mlx4_en_destroy_netdev(mdev->pndev[i]); ++ } ++ ++ mutex_lock(&mdev->state_lock); ++ mdev->device_up = false; ++ mutex_unlock(&mdev->state_lock); ++ flush_workqueue(mdev->workqueue); ++ ++ /* Stop event queue before we drop down to release shared SW state */ ++ destroy_workqueue(mdev->workqueue); ++ ++err_mr: ++ mlx4_mr_free(dev, &mdev->mr); ++err_uar: ++ mlx4_uar_free(dev, &mdev->priv_uar); ++err_pd: ++ mlx4_pd_free(dev, mdev->priv_pdn); ++err_free_dev: ++ kfree(mdev); ++err_free_res: ++ return NULL; ++} ++ ++enum mlx4_query_reply mlx4_en_query(void *endev_ptr, void *int_dev) ++{ ++ struct mlx4_en_dev *mdev = endev_ptr; ++ struct net_device *netdev = int_dev; ++ int p; ++ ++ for (p = 1; p <= MLX4_MAX_PORTS; ++p) ++ if (mdev->pndev[p] == netdev) ++ return p; ++ ++ return MLX4_QUERY_NOT_MINE; ++} ++ ++static struct mlx4_interface mlx4_en_interface = { ++ .add = mlx4_en_add, ++ .remove = mlx4_en_remove, ++ .event = mlx4_en_event, ++ .query = mlx4_en_query ++}; ++ ++static int __init mlx4_en_init(void) ++{ ++ return mlx4_register_interface(&mlx4_en_interface); ++} ++ ++static void __exit mlx4_en_cleanup(void) ++{ ++ mlx4_unregister_interface(&mlx4_en_interface); ++} ++ ++module_init(mlx4_en_init); ++module_exit(mlx4_en_cleanup); ++ +diff -r 4e706462aff6 drivers/net/mlx4/en_netdev.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/en_netdev.c Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,1098 @@ ++/* ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "mlx4_en.h" ++#include "en_port.h" ++ ++ ++static void mlx4_en_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int err; ++ ++ mlx4_dbg(HW, priv, "Regsitering VLAN group:%p\n", grp); ++ priv->vlgrp = grp; ++ ++ mutex_lock(&mdev->state_lock); ++ if (mdev->device_up && priv->port_up) { ++ err = mlx4_SET_VLAN_FLTR(mdev->dev, priv->port, grp); ++ if (err) ++ mlx4_err(mdev, "Failed configuring VLAN filter\n"); ++ } ++ mutex_unlock(&mdev->state_lock); ++} ++ ++static void mlx4_en_vlan_rx_add_vid(struct net_device *dev, unsigned short vid) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int err; ++ ++ if (!priv->vlgrp) ++ return; ++ ++ mlx4_dbg(HW, priv, "adding VLAN:%d (vlgrp entry:%p)\n", ++ vid, vlan_group_get_device(priv->vlgrp, vid)); ++ ++ /* Add VID to port VLAN filter */ ++ mutex_lock(&mdev->state_lock); ++ if (mdev->device_up && priv->port_up) { ++ err = mlx4_SET_VLAN_FLTR(mdev->dev, priv->port, priv->vlgrp); ++ if (err) ++ mlx4_err(mdev, "Failed configuring VLAN filter\n"); ++ } ++ mutex_unlock(&mdev->state_lock); ++} ++ ++static void mlx4_en_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int err; ++ ++ if (!priv->vlgrp) ++ return; ++ ++ mlx4_dbg(HW, priv, "Killing VID:%d (vlgrp:%p vlgrp " ++ "entry:%p)\n", vid, priv->vlgrp, ++ vlan_group_get_device(priv->vlgrp, vid)); ++ vlan_group_set_device(priv->vlgrp, vid, NULL); ++ ++ /* Remove VID from port VLAN filter */ ++ mutex_lock(&mdev->state_lock); ++ if (mdev->device_up && priv->port_up) { ++ err = mlx4_SET_VLAN_FLTR(mdev->dev, priv->port, priv->vlgrp); ++ if (err) ++ mlx4_err(mdev, "Failed configuring VLAN filter\n"); ++ } ++ mutex_unlock(&mdev->state_lock); ++} ++ ++static u64 mlx4_en_mac_to_u64(u8 *addr) ++{ ++ u64 mac = 0; ++ int i; ++ ++ for (i = 0; i < ETH_ALEN; i++) { ++ mac <<= 8; ++ mac |= addr[i]; ++ } ++ return mac; ++} ++ ++static int mlx4_en_set_mac(struct net_device *dev, void *addr) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct sockaddr *saddr = addr; ++ ++ if (!is_valid_ether_addr(saddr->sa_data)) ++ return -EADDRNOTAVAIL; ++ ++ memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN); ++ priv->mac = mlx4_en_mac_to_u64(dev->dev_addr); ++ queue_work(mdev->workqueue, &priv->mac_task); ++ return 0; ++} ++ ++static void mlx4_en_do_set_mac(struct work_struct *work) ++{ ++ struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, ++ mac_task); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int err = 0; ++ ++ mutex_lock(&mdev->state_lock); ++ if (priv->port_up) { ++ /* Remove old MAC and insert the new one */ ++ mlx4_unregister_mac(mdev->dev, priv->port, priv->mac_index); ++ err = mlx4_register_mac(mdev->dev, priv->port, ++ priv->mac, &priv->mac_index); ++ if (err) ++ mlx4_err(mdev, "Failed changing HW MAC address\n"); ++ } else ++ mlx4_dbg(HW, priv, "Port is down, exiting...\n"); ++ ++ mutex_unlock(&mdev->state_lock); ++} ++ ++static void mlx4_en_clear_list(struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct dev_mc_list *plist = priv->mc_list; ++ struct dev_mc_list *next; ++ ++ while (plist) { ++ next = plist->next; ++ kfree(plist); ++ plist = next; ++ } ++ priv->mc_list = NULL; ++} ++ ++static void mlx4_en_cache_mclist(struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct dev_mc_list *mclist; ++ struct dev_mc_list *tmp; ++ struct dev_mc_list *plist = NULL; ++ ++ for (mclist = dev->mc_list; mclist; mclist = mclist->next) { ++ tmp = kmalloc(sizeof(struct dev_mc_list), GFP_ATOMIC); ++ if (!tmp) { ++ mlx4_err(mdev, "failed to allocate multicast list\n"); ++ mlx4_en_clear_list(dev); ++ return; ++ } ++ memcpy(tmp, mclist, sizeof(struct dev_mc_list)); ++ tmp->next = NULL; ++ if (plist) ++ plist->next = tmp; ++ else ++ priv->mc_list = tmp; ++ plist = tmp; ++ } ++} ++ ++ ++static void mlx4_en_set_multicast(struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ ++ if (!priv->port_up) ++ return; ++ ++ queue_work(priv->mdev->workqueue, &priv->mcast_task); ++} ++ ++static void mlx4_en_do_set_multicast(struct work_struct *work) ++{ ++ struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, ++ mcast_task); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct net_device *dev = priv->dev; ++ struct dev_mc_list *mclist; ++ u64 mcast_addr = 0; ++ int err; ++ ++ mutex_lock(&mdev->state_lock); ++ if (!mdev->device_up) { ++ mlx4_dbg(HW, priv, "Card is not up, ignoring " ++ "multicast change.\n"); ++ goto out; ++ } ++ if (!priv->port_up) { ++ mlx4_dbg(HW, priv, "Port is down, ignoring " ++ "multicast change.\n"); ++ goto out; ++ } ++ ++ /* ++ * Promsicuous mode: disable all filters ++ */ ++ ++ if (dev->flags & IFF_PROMISC) { ++ if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) { ++ if (netif_msg_rx_status(priv)) ++ mlx4_warn(mdev, "Port:%d entering promiscuous mode\n", ++ priv->port); ++ priv->flags |= MLX4_EN_FLAG_PROMISC; ++ ++ /* Enable promiscouos mode */ ++ err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, ++ priv->base_qpn, 1); ++ if (err) ++ mlx4_err(mdev, "Failed enabling " ++ "promiscous mode\n"); ++ ++ /* Disable port multicast filter (unconditionally) */ ++ err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, ++ 0, MLX4_MCAST_DISABLE); ++ if (err) ++ mlx4_err(mdev, "Failed disabling " ++ "multicast filter\n"); ++ ++ /* Disable port VLAN filter */ ++ err = mlx4_SET_VLAN_FLTR(mdev->dev, priv->port, NULL); ++ if (err) ++ mlx4_err(mdev, "Failed disabling " ++ "VLAN filter\n"); ++ } ++ goto out; ++ } ++ ++ /* ++ * Not in promiscous mode ++ */ ++ ++ if (priv->flags & MLX4_EN_FLAG_PROMISC) { ++ if (netif_msg_rx_status(priv)) ++ mlx4_warn(mdev, "Port:%d leaving promiscuous mode\n", ++ priv->port); ++ priv->flags &= ~MLX4_EN_FLAG_PROMISC; ++ ++ /* Disable promiscouos mode */ ++ err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, ++ priv->base_qpn, 0); ++ if (err) ++ mlx4_err(mdev, "Failed disabling promiscous mode\n"); ++ ++ /* Enable port VLAN filter */ ++ err = mlx4_SET_VLAN_FLTR(mdev->dev, priv->port, priv->vlgrp); ++ if (err) ++ mlx4_err(mdev, "Failed enabling VLAN filter\n"); ++ } ++ ++ /* Enable/disable the multicast filter according to IFF_ALLMULTI */ ++ if (dev->flags & IFF_ALLMULTI) { ++ err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, ++ 0, MLX4_MCAST_DISABLE); ++ if (err) ++ mlx4_err(mdev, "Failed disabling multicast filter\n"); ++ } else { ++ err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, ++ 0, MLX4_MCAST_DISABLE); ++ if (err) ++ mlx4_err(mdev, "Failed disabling multicast filter\n"); ++ ++ /* Flush mcast filter and init it with broadcast address */ ++ mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST, ++ 1, MLX4_MCAST_CONFIG); ++ ++ /* Update multicast list - we cache all addresses so they won't ++ * change while HW is updated holding the command semaphor */ ++ netif_tx_lock_bh(dev); ++ mlx4_en_cache_mclist(dev); ++ netif_tx_unlock_bh(dev); ++ for (mclist = priv->mc_list; mclist; mclist = mclist->next) { ++ mcast_addr = mlx4_en_mac_to_u64(mclist->dmi_addr); ++ mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ++ mcast_addr, 0, MLX4_MCAST_CONFIG); ++ } ++ err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, ++ 0, MLX4_MCAST_ENABLE); ++ if (err) ++ mlx4_err(mdev, "Failed enabling multicast filter\n"); ++ ++ mlx4_en_clear_list(dev); ++ } ++out: ++ mutex_unlock(&mdev->state_lock); ++} ++ ++void mlx4_en_netpoll(struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_cq *cq; ++ unsigned long flags; ++ int i; ++ ++ ++ for (i = 0; i < priv->rx_ring_num; i++) { ++ cq = &priv->rx_cq[i]; ++ spin_lock_irqsave(&cq->lock, flags); ++ napi_synchronize(&cq->napi); ++ if (priv->rx_ring[i].use_frags) ++ mlx4_en_process_rx_cq(dev, cq, 0); ++ else ++ mlx4_en_process_rx_cq_skb(dev, cq, 0); ++ spin_unlock_irqrestore(&cq->lock, flags); ++ } ++} ++ ++ ++static void mlx4_en_tx_timeout(struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ ++ if (netif_msg_timer(priv)) ++ mlx4_warn(mdev, "Tx timeout called on port:%d\n", priv->port); ++ ++ priv->port_stats.tx_timeout++; ++ mlx4_dbg(DRV, priv, "Scheduling watchdog\n"); ++ queue_work(mdev->workqueue, &priv->watchdog_task); ++} ++ ++ ++static struct net_device_stats *mlx4_en_get_stats(struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ ++ spin_lock_bh(&priv->stats_lock); ++ memcpy(&priv->ret_stats, &priv->stats, sizeof(priv->stats)); ++ spin_unlock_bh(&priv->stats_lock); ++ ++ return &priv->ret_stats; ++} ++ ++void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv) ++{ ++ struct mlx4_en_cq *cq; ++ int i; ++ ++ /* If we haven't received a specific coalescing setting ++ * (module param), we set the moderation paramters as follows: ++ * - moder_cnt is set to the number of mtu sized packets to ++ * satisfy our coelsing target. ++ * - moder_time is set to a fixed value. ++ */ ++ priv->rx_frames = MLX4_EN_RX_COAL_TARGET / priv->dev->mtu + 1; ++ priv->rx_usecs = MLX4_EN_RX_COAL_TIME; ++ mlx4_dbg(INTR, priv, "Default coalesing params for mtu:%d - " ++ "rx_frames:%d rx_usecs:%d\n", ++ priv->dev->mtu, priv->rx_frames, priv->rx_usecs); ++ ++ /* Setup cq moderation params */ ++ for (i = 0; i < priv->rx_ring_num; i++) { ++ cq = &priv->rx_cq[i]; ++ cq->moder_cnt = priv->rx_frames; ++ cq->moder_time = priv->rx_usecs; ++ } ++ ++ for (i = 0; i < priv->tx_ring_num; i++) { ++ cq = &priv->tx_cq[i]; ++ cq->moder_cnt = MLX4_EN_TX_COAL_PKTS; ++ cq->moder_time = MLX4_EN_TX_COAL_TIME; ++ } ++ ++ /* Reset auto-moderation params */ ++ priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW; ++ priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW; ++ priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH; ++ priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH; ++ priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL; ++ priv->adaptive_rx_coal = 1; ++ priv->last_moder_time = MLX4_EN_AUTO_CONF; ++ priv->last_moder_jiffies = 0; ++ priv->last_moder_packets = 0; ++ priv->last_moder_tx_packets = 0; ++ priv->last_moder_bytes = 0; ++} ++ ++static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv) ++{ ++ unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_en_cq *cq; ++ unsigned long packets; ++ unsigned long rate; ++ unsigned long avg_pkt_size; ++ unsigned long rx_packets; ++ unsigned long rx_bytes; ++ unsigned long tx_packets; ++ unsigned long tx_pkt_diff; ++ unsigned long rx_pkt_diff; ++ int moder_time; ++ int i, err; ++ ++ if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ) ++ return; ++ ++ spin_lock_bh(&priv->stats_lock); ++ rx_packets = priv->stats.rx_packets; ++ rx_bytes = priv->stats.rx_bytes; ++ tx_packets = priv->stats.tx_packets; ++ spin_unlock_bh(&priv->stats_lock); ++ ++ if (!priv->last_moder_jiffies || !period) ++ goto out; ++ ++ tx_pkt_diff = ((unsigned long) (tx_packets - ++ priv->last_moder_tx_packets)); ++ rx_pkt_diff = ((unsigned long) (rx_packets - ++ priv->last_moder_packets)); ++ packets = max(tx_pkt_diff, rx_pkt_diff); ++ rate = packets * HZ / period; ++ avg_pkt_size = packets ? ((unsigned long) (rx_bytes - ++ priv->last_moder_bytes)) / packets : 0; ++ ++ /* Apply auto-moderation only when packet rate exceeds a rate that ++ * it matters */ ++ if (rate > MLX4_EN_RX_RATE_THRESH) { ++ /* If tx and rx packet rates are not balanced, assume that ++ * traffic is mainly BW bound and apply maximum moderation. ++ * Otherwise, moderate according to packet rate */ ++ if (2 * tx_pkt_diff > 3 * rx_pkt_diff || ++ 2 * rx_pkt_diff > 3 * tx_pkt_diff) { ++ moder_time = priv->rx_usecs_high; ++ } else { ++ if (rate < priv->pkt_rate_low) ++ moder_time = priv->rx_usecs_low; ++ else if (rate > priv->pkt_rate_high) ++ moder_time = priv->rx_usecs_high; ++ else ++ moder_time = (rate - priv->pkt_rate_low) * ++ (priv->rx_usecs_high - priv->rx_usecs_low) / ++ (priv->pkt_rate_high - priv->pkt_rate_low) + ++ priv->rx_usecs_low; ++ } ++ } else { ++ /* When packet rate is low, use default moderation rather than ++ * 0 to prevent interrupt storms if traffic suddenly increases */ ++ moder_time = priv->rx_usecs; ++ } ++ ++ mlx4_dbg(INTR, priv, "tx rate:%lu rx_rate:%lu\n", ++ tx_pkt_diff * HZ / period, rx_pkt_diff * HZ / period); ++ ++ mlx4_dbg(INTR, priv, "Rx moder_time changed from:%d to %d period:%lu " ++ "[jiff] packets:%lu avg_pkt_size:%lu rate:%lu [p/s])\n", ++ priv->last_moder_time, moder_time, period, packets, ++ avg_pkt_size, rate); ++ ++ if (moder_time != priv->last_moder_time) { ++ priv->last_moder_time = moder_time; ++ for (i = 0; i < priv->rx_ring_num; i++) { ++ cq = &priv->rx_cq[i]; ++ cq->moder_time = moder_time; ++ err = mlx4_en_set_cq_moder(priv, cq); ++ if (err) { ++ mlx4_err(mdev, "Failed modifying moderation for cq:%d " ++ "on port:%d\n", i, priv->port); ++ break; ++ } ++ } ++ } ++ ++out: ++ priv->last_moder_packets = rx_packets; ++ priv->last_moder_tx_packets = tx_packets; ++ priv->last_moder_bytes = rx_bytes; ++ priv->last_moder_jiffies = jiffies; ++} ++ ++static void mlx4_en_do_get_stats(struct work_struct *work) ++{ ++ struct delayed_work *delay = container_of(work, struct delayed_work, work); ++ struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv, ++ stats_task); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int err; ++ ++ err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0); ++ if (err) ++ mlx4_dbg(HW, priv, "Could not update stats for " ++ "port:%d\n", priv->port); ++ ++ mutex_lock(&mdev->state_lock); ++ if (mdev->device_up) { ++ if (priv->port_up) ++ mlx4_en_auto_moderation(priv); ++ ++ queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY); ++ } ++ mutex_unlock(&mdev->state_lock); ++} ++ ++static void mlx4_en_linkstate(struct work_struct *work) ++{ ++ struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, ++ linkstate_task); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int linkstate = priv->link_state; ++ ++ mutex_lock(&mdev->state_lock); ++ /* If observable port state changed set carrier state and ++ * report to system log */ ++ if (priv->last_link_state != linkstate) { ++ if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) { ++ if (netif_msg_link(priv)) ++ mlx4_info(mdev, "Port %d - link down\n", priv->port); ++ netif_carrier_off(priv->dev); ++ } else { ++ if (netif_msg_link(priv)) ++ mlx4_info(mdev, "Port %d - link up\n", priv->port); ++ netif_carrier_on(priv->dev); ++ } ++ } ++ priv->last_link_state = linkstate; ++ mutex_unlock(&mdev->state_lock); ++} ++ ++ ++int mlx4_en_start_port(struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_en_cq *cq; ++ struct mlx4_en_tx_ring *tx_ring; ++ struct mlx4_en_rx_ring *rx_ring; ++ int rx_index = 0; ++ int tx_index = 0; ++ int err = 0; ++ int i; ++ int j; ++ ++ if (priv->port_up) { ++ mlx4_dbg(DRV, priv, "start port called while port already up\n"); ++ return 0; ++ } ++ ++ /* Calculate Rx buf size */ ++ dev->mtu = min(dev->mtu, priv->max_mtu); ++ mlx4_en_calc_rx_buf(dev); ++ mlx4_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size); ++ /* Configure rx cq's and rings */ ++ for (i = 0; i < priv->rx_ring_num; i++) { ++ cq = &priv->rx_cq[i]; ++ rx_ring = &priv->rx_ring[i]; ++ ++ err = mlx4_en_activate_cq(priv, cq); ++ if (err) { ++ mlx4_err(mdev, "Failed activating Rx CQ\n"); ++ goto cq_err; ++ } ++ for (j = 0; j < cq->size; j++) ++ cq->buf[j].owner_sr_opcode = MLX4_CQE_OWNER_MASK; ++ err = mlx4_en_set_cq_moder(priv, cq); ++ if (err) { ++ mlx4_err(mdev, "Failed setting cq moderation parameters"); ++ mlx4_en_deactivate_cq(priv, cq); ++ goto cq_err; ++ } ++ mlx4_en_arm_cq(priv, cq); ++ ++ ++rx_index; ++ } ++ ++ err = mlx4_en_activate_rx_rings(priv); ++ if (err){ ++ mlx4_err(mdev, "Failed to activate RX rings\n"); ++ goto cq_err; ++ } ++ ++ err = mlx4_en_config_rss_steer(priv); ++ if (err) { ++ mlx4_err(mdev, "Failed configuring rss steering\n"); ++ goto rx_err; ++ } ++ ++ /* Configure tx cq's and rings */ ++ for (i = 0; i < priv->tx_ring_num; i++) { ++ /* Configure cq */ ++ cq = &priv->tx_cq[i]; ++ err = mlx4_en_activate_cq(priv, cq); ++ if (err) { ++ mlx4_err(mdev, "Failed allocating Tx CQ\n"); ++ goto tx_err; ++ } ++ err = mlx4_en_set_cq_moder(priv, cq); ++ if (err) { ++ mlx4_err(mdev, "Failed setting cq moderation parameters"); ++ mlx4_en_deactivate_cq(priv, cq); ++ goto tx_err; ++ } ++ mlx4_dbg(DRV, priv, "Resetting index of collapsed CQ:%d " ++ "to -1\n", i); ++ cq->buf->wqe_index = 0xffff; ++ ++ /* Configure ring */ ++ tx_ring = &priv->tx_ring[i]; ++ err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn, ++ priv->rx_ring[0].srq.srqn); ++ if (err) { ++ mlx4_err(mdev, "Failed allocating Tx ring\n"); ++ mlx4_en_deactivate_cq(priv, cq); ++ goto tx_err; ++ } ++ /* Set initial ownership of all Tx TXBBs to SW (1) */ ++ for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE) ++ *((u32 *) (tx_ring->buf + j)) = 0xffffffff; ++ ++tx_index; ++ } ++ ++ for (i = 0; i < MLX4_EN_TX_HASH_SIZE; i++) { ++ memset(&priv->tx_hash[i], 0, sizeof(struct mlx4_en_tx_hash_entry)); ++ /* ++ * Initially, all streams are assigned to the rings ++ * that should handle the small packages streams, (the lower ring ++ * indixes) then moved according the stream charasteristics. ++ */ ++ priv->tx_hash[i].ring = i & (MLX4_EN_NUM_HASH_RINGS / 2 - 1); ++ } ++ ++ /* Configure port */ ++ err = mlx4_SET_PORT_general(mdev->dev, priv->port, ++ priv->rx_skb_size + ETH_FCS_LEN, ++ priv->prof->tx_pause, ++ priv->prof->tx_ppp, ++ priv->prof->rx_pause, ++ priv->prof->rx_ppp); ++ if (err) { ++ mlx4_err(mdev, "Failed setting port general configurations" ++ " for port %d, with error %d\n", priv->port, err); ++ goto tx_err; ++ } ++ /* Set default qp number */ ++ err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0); ++ if (err) { ++ mlx4_err(mdev, "Failed setting default qp numbers\n"); ++ goto tx_err; ++ } ++ /* Set port mac number */ ++ err = mlx4_register_mac(mdev->dev, priv->port, ++ priv->mac, &priv->mac_index); ++ if (err) { ++ mlx4_err(mdev, "Failed setting port mac\n"); ++ goto tx_err; ++ } ++ ++ /* Init port */ ++ mlx4_dbg(HW, priv, "Initializing port\n"); ++ err = mlx4_INIT_PORT(mdev->dev, priv->port); ++ if (err) { ++ mlx4_err(mdev, "Failed Initializing port\n"); ++ goto mac_err; ++ } ++ ++ /* Schedule multicast task to populate multicast list */ ++ queue_work(mdev->workqueue, &priv->mcast_task); ++ ++ priv->port_up = true; ++ netif_start_queue(dev); ++ return 0; ++ ++mac_err: ++ mlx4_unregister_mac(mdev->dev, priv->port, priv->mac_index); ++tx_err: ++ while (tx_index--) { ++ mlx4_en_deactivate_tx_ring(priv, &priv->tx_ring[tx_index]); ++ mlx4_en_deactivate_cq(priv, &priv->tx_cq[tx_index]); ++ } ++ ++ mlx4_en_release_rss_steer(priv); ++rx_err: ++ for (i = 0; i < priv->rx_ring_num; i++) ++ mlx4_en_deactivate_rx_ring(priv, &priv->rx_ring[i]); ++cq_err: ++ while (rx_index--) ++ mlx4_en_deactivate_cq(priv, &priv->rx_cq[rx_index]); ++ ++ return err; /* need to close devices */ ++} ++ ++ ++void mlx4_en_stop_port(struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int i; ++ ++ if (!priv->port_up) { ++ mlx4_dbg(DRV, priv, "stop port (%d) called while port already down\n", ++ priv->port); ++ return; ++ } ++ netif_stop_queue(dev); ++ ++ /* Synchronize with tx routine */ ++ netif_tx_lock_bh(dev); ++ priv->port_up = false; ++ netif_tx_unlock_bh(dev); ++ ++ /* close port*/ ++ mlx4_CLOSE_PORT(mdev->dev, priv->port); ++ ++ /* Unregister Mac address for the port */ ++ mlx4_unregister_mac(mdev->dev, priv->port, priv->mac_index); ++ ++ /* Free TX Rings */ ++ for (i = 0; i < priv->tx_ring_num; i++) { ++ mlx4_en_deactivate_tx_ring(priv, &priv->tx_ring[i]); ++ mlx4_en_deactivate_cq(priv, &priv->tx_cq[i]); ++ } ++ msleep(10); ++ ++ for (i = 0; i < priv->tx_ring_num; i++) ++ mlx4_en_free_tx_buf(dev, &priv->tx_ring[i]); ++ ++ /* Free RSS qps */ ++ mlx4_en_release_rss_steer(priv); ++ ++ /* Free RX Rings */ ++ for (i = 0; i < priv->rx_ring_num; i++) { ++ mlx4_en_deactivate_rx_ring(priv, &priv->rx_ring[i]); ++ while (test_bit(NAPI_STATE_SCHED, &priv->rx_cq[i].napi.state)) ++ msleep(1); ++ mlx4_en_deactivate_cq(priv, &priv->rx_cq[i]); ++ } ++} ++ ++static void mlx4_en_restart(struct work_struct *work) ++{ ++ struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, ++ watchdog_task); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct net_device *dev = priv->dev; ++ ++ mlx4_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port); ++ ++ mutex_lock(&mdev->state_lock); ++ if (priv->port_up) { ++ mlx4_en_stop_port(dev); ++ if (mlx4_en_start_port(dev)) ++ mlx4_err(mdev, "Failed restarting port %d\n", priv->port); ++ } ++ mutex_unlock(&mdev->state_lock); ++} ++ ++ ++int mlx4_en_open(struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int i; ++ int err = 0; ++ ++ mutex_lock(&mdev->state_lock); ++ ++ if (!mdev->device_up) { ++ mlx4_err(mdev, "Cannot open - device down/disabled\n"); ++ err = -EBUSY; ++ goto out; ++ } ++ ++ /* Reset HW statistics and performance counters */ ++ if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1)) ++ mlx4_dbg(HW, priv, "Failed dumping statistics\n"); ++ ++ memset(&priv->stats, 0, sizeof(priv->stats)); ++ memset(&priv->pstats, 0, sizeof(priv->pstats)); ++ ++ for (i = 0; i < priv->tx_ring_num; i++) { ++ priv->tx_ring[i].bytes = 0; ++ priv->tx_ring[i].packets = 0; ++ } ++ for (i = 0; i < priv->rx_ring_num; i++) { ++ priv->rx_ring[i].bytes = 0; ++ priv->rx_ring[i].packets = 0; ++ } ++ ++ mlx4_en_set_default_moderation(priv); ++ err = mlx4_en_start_port(dev); ++ if (err) ++ mlx4_err(mdev, "Failed starting port:%d\n", priv->port); ++ ++out: ++ mutex_unlock(&mdev->state_lock); ++ return err; ++} ++ ++ ++int mlx4_en_close(struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ ++ if (netif_msg_ifdown(priv)) ++ mlx4_info(mdev, "Close called for port:%d\n", priv->port); ++ ++ mutex_lock(&mdev->state_lock); ++ ++ mlx4_en_stop_port(dev); ++ netif_carrier_off(dev); ++ ++ mutex_unlock(&mdev->state_lock); ++ return 0; ++} ++ ++void mlx4_en_free_resources(struct mlx4_en_priv *priv) ++{ ++ int i; ++ ++ for (i = 0; i < priv->tx_ring_num; i++) { ++ if (priv->tx_ring[i].tx_info) ++ mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]); ++ if (priv->tx_cq[i].buf) ++ mlx4_en_destroy_cq(priv, &priv->tx_cq[i]); ++ } ++ ++ for (i = 0; i < priv->rx_ring_num; i++) { ++ if (priv->rx_ring[i].rx_info) ++ mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i]); ++ if (priv->rx_cq[i].buf) ++ mlx4_en_destroy_cq(priv, &priv->rx_cq[i]); ++ } ++} ++ ++int mlx4_en_alloc_resources(struct mlx4_en_priv *priv) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_en_port_profile *prof = priv->prof; ++ int i; ++ ++ /* Create tx Rings */ ++ for (i = 0; i < priv->tx_ring_num; i++) { ++ if (mlx4_en_create_cq(priv, &priv->tx_cq[i], ++ prof->tx_ring_size, i, TX)) ++ goto err; ++ ++ if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i], ++ prof->tx_ring_size, TXBB_SIZE)) ++ goto err; ++ } ++ ++ /* Create rx Rings */ ++ for (i = 0; i < priv->rx_ring_num; i++) { ++ if (i > 0) ++ priv->rx_ring[i].use_frags = 1; ++ else ++ priv->rx_ring[i].use_frags = 0; ++ ++ if (mlx4_en_create_cq(priv, &priv->rx_cq[i], ++ prof->rx_ring_size, i, RX)) ++ goto err; ++ ++ if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i], ++ prof->rx_ring_size)) ++ goto err; ++ } ++ ++ return 0; ++ ++err: ++ mlx4_err(mdev, "Failed to allocate NIC resources\n"); ++ return -ENOMEM; ++} ++ ++ ++void mlx4_en_destroy_netdev(struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ ++ mlx4_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port); ++ ++ /* Unregsiter device - this will close the port if it was up */ ++ if (priv->registered) ++ unregister_netdev(dev); ++ ++ if (priv->allocated) ++ mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE); ++ ++ cancel_delayed_work(&priv->stats_task); ++ cancel_delayed_work(&priv->refill_task); ++ /* flush any pending task for this netdev */ ++ flush_workqueue(mdev->workqueue); ++ ++ /* Detach the netdev so tasks would not attempt to access it */ ++ mutex_lock(&mdev->state_lock); ++ mdev->pndev[priv->port] = NULL; ++ mutex_unlock(&mdev->state_lock); ++ ++ mlx4_en_free_resources(priv); ++ free_netdev(dev); ++} ++ ++static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int err = 0; ++ ++ mlx4_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n", ++ dev->mtu, new_mtu); ++ ++ if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) { ++ mlx4_err(mdev, "Bad MTU size:%d.\n", new_mtu); ++ return -EPERM; ++ } ++ dev->mtu = new_mtu; ++ ++ if (netif_running(dev)) { ++ mutex_lock(&mdev->state_lock); ++ if (!mdev->device_up) { ++ /* NIC is probably restarting - let watchdog task reset ++ * the port */ ++ mlx4_dbg(DRV, priv, "Change MTU called with card down!?\n"); ++ } else { ++ mlx4_en_stop_port(dev); ++ mlx4_en_set_default_moderation(priv); ++ err = mlx4_en_start_port(dev); ++ if (err) { ++ mlx4_err(mdev, "Failed restarting port:%d\n", ++ priv->port); ++ queue_work(mdev->workqueue, &priv->watchdog_task); ++ } ++ } ++ mutex_unlock(&mdev->state_lock); ++ } ++ return 0; ++} ++ ++int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, ++ struct mlx4_en_port_profile *prof) ++{ ++ struct net_device *dev; ++ struct mlx4_en_priv *priv; ++ int i; ++ int err; ++ ++ dev = alloc_etherdev_mq(sizeof(struct mlx4_en_priv), prof->tx_ring_num); ++ if (dev == NULL) { ++ mlx4_err(mdev, "Net device allocation failed\n"); ++ return -ENOMEM; ++ } ++ ++ SET_NETDEV_DEV(dev, &mdev->dev->pdev->dev); ++ ++ /* ++ * Initialize driver private data ++ */ ++ ++ priv = netdev_priv(dev); ++ memset(priv, 0, sizeof(struct mlx4_en_priv)); ++ priv->dev = dev; ++ priv->mdev = mdev; ++ priv->prof = prof; ++ priv->port = port; ++ priv->port_up = false; ++ priv->rx_csum = 1; ++ priv->flags = prof->flags; ++ priv->tx_ring_num = prof->tx_ring_num; ++ priv->rx_ring_num = prof->rx_ring_num; ++ priv->mc_list = NULL; ++ priv->mac_index = -1; ++ priv->msg_enable = MLX4_EN_MSG_LEVEL; ++ spin_lock_init(&priv->stats_lock); ++ INIT_WORK(&priv->mcast_task, mlx4_en_do_set_multicast); ++ INIT_WORK(&priv->mac_task, mlx4_en_do_set_mac); ++ INIT_DELAYED_WORK(&priv->refill_task, mlx4_en_rx_refill); ++ INIT_WORK(&priv->watchdog_task, mlx4_en_restart); ++ INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate); ++ INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats); ++ ++ /* Query for default mac and max mtu */ ++ priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port]; ++ priv->mac = mdev->dev->caps.def_mac[priv->port]; ++ if (ILLEGAL_MAC(priv->mac)) { ++ mlx4_err(mdev, "Port: %d, invalid mac burned: 0x%llx, quiting\n", ++ priv->port, priv->mac); ++ err = -EINVAL; ++ goto out; ++ } ++ ++ err = mlx4_en_alloc_resources(priv); ++ if (err) ++ goto out; ++ ++ /* Populate Rx default RSS mappings */ ++ mlx4_en_set_default_rss_map(priv, &priv->rss_map, priv->rx_ring_num * ++ RSS_FACTOR, priv->rx_ring_num); ++ /* Allocate page for receive rings */ ++ err = mlx4_alloc_hwq_res(mdev->dev, &priv->res, ++ MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE); ++ if (err) { ++ mlx4_err(mdev, "Failed to allocate page for rx qps\n"); ++ goto out; ++ } ++ priv->allocated = 1; ++ ++ /* Populate Tx priority mappings */ ++ mlx4_en_set_prio_map(priv, priv->tx_prio_map, ++ prof->tx_ring_num - MLX4_EN_NUM_HASH_RINGS); ++ ++ /* ++ * Initialize netdev entry points ++ */ ++ ++ dev->open = &mlx4_en_open; ++ dev->stop = &mlx4_en_close; ++ dev->hard_start_xmit = &mlx4_en_xmit; ++ dev->select_queue = &mlx4_en_select_queue; ++ dev->get_stats = &mlx4_en_get_stats; ++ dev->set_multicast_list = &mlx4_en_set_multicast; ++ dev->set_mac_address = &mlx4_en_set_mac; ++ dev->change_mtu = &mlx4_en_change_mtu; ++ dev->tx_timeout = &mlx4_en_tx_timeout; ++ dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT; ++ dev->vlan_rx_register = mlx4_en_vlan_rx_register; ++ dev->vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid; ++ dev->vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid; ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ dev->poll_controller = mlx4_en_netpoll; ++#endif ++ SET_ETHTOOL_OPS(dev, &mlx4_en_ethtool_ops); ++ ++ /* Set defualt MAC */ ++ dev->addr_len = ETH_ALEN; ++ for (i = 0; i < ETH_ALEN; i++) ++ dev->dev_addr[ETH_ALEN - 1 - i] = ++ (u8) (priv->mac >> (8 * i)); ++ ++ /* ++ * Set driver features ++ */ ++ dev->features |= NETIF_F_SG; ++ dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; ++ dev->features |= NETIF_F_HIGHDMA; ++ dev->features |= NETIF_F_HW_VLAN_TX | ++ NETIF_F_HW_VLAN_RX | ++ NETIF_F_HW_VLAN_FILTER; ++ if (mdev->profile.num_lro) ++ dev->features |= NETIF_F_LRO; ++ if (mdev->LSO_support) { ++ dev->features |= NETIF_F_TSO; ++ dev->features |= NETIF_F_TSO6; ++ } ++ ++ mdev->pndev[port] = dev; ++ ++ netif_carrier_off(dev); ++ err = register_netdev(dev); ++ if (err) { ++ mlx4_err(mdev, "Netdev registration failed\n"); ++ goto out; ++ } ++ priv->registered = 1; ++ queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY); ++ return 0; ++ ++out: ++ mlx4_en_destroy_netdev(dev); ++ return err; ++} ++ +diff -r 4e706462aff6 drivers/net/mlx4/en_params.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/en_params.c Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,484 @@ ++/* ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++#include ++#include ++#include ++ ++#include "mlx4_en.h" ++#include "en_port.h" ++ ++#define MLX4_EN_PARM_INT(X, def_val, desc) \ ++ static unsigned int X = def_val;\ ++ module_param(X , uint, 0444); \ ++ MODULE_PARM_DESC(X, desc); ++ ++ ++/* ++ * Device scope module parameters ++ */ ++ ++ ++/* Use a XOR rathern than Toeplitz hash function for RSS */ ++MLX4_EN_PARM_INT(rss_xor, 0, "Use XOR hash function for RSS"); ++ ++/* RSS hash type mask - default to */ ++MLX4_EN_PARM_INT(rss_mask, 0x5, "RSS hash type bitmask"); ++ ++/* Number of LRO sessions per Rx ring (rounded up to a power of two) */ ++MLX4_EN_PARM_INT(num_lro, MLX4_EN_MAX_LRO_DESCRIPTORS, ++ "Number of LRO sessions per ring or disabled (0)"); ++ ++/* Allow reassembly of fragmented IP packets */ ++MLX4_EN_PARM_INT(ip_reasm, 1, "Allow reassembly of fragmented IP packets (!0)"); ++ ++/* Priority pausing */ ++MLX4_EN_PARM_INT(pfctx, 0, "Priority based Flow Control policy on TX[7:0]." ++ " Per priority bit mask"); ++MLX4_EN_PARM_INT(pfcrx, 0, "Priority based Flow Control policy on RX[7:0]." ++ " Per priority bit mask"); ++ ++int mlx4_en_get_profile(struct mlx4_en_dev *mdev) ++{ ++ struct mlx4_en_profile *params = &mdev->profile; ++ int i; ++ ++ params->rss_xor = (rss_xor != 0); ++ params->rss_mask = rss_mask & 0x1f; ++ params->num_lro = min_t(int, num_lro , MLX4_EN_MAX_LRO_DESCRIPTORS); ++ params->ip_reasm = ip_reasm; ++ for (i = 1; i <= MLX4_MAX_PORTS; i++) { ++ params->prof[i].rx_pause = 1; ++ params->prof[i].rx_ppp = pfcrx; ++ params->prof[i].tx_pause = 1; ++ params->prof[i].tx_ppp = pfctx; ++ params->prof[i].tx_ring_size = MLX4_EN_DEF_TX_RING_SIZE; ++ params->prof[i].rx_ring_size = MLX4_EN_DEF_RX_RING_SIZE; ++ params->prof[i].tx_ring_num = MLX4_EN_NUM_HASH_RINGS + 1 + ++ (!!pfcrx) * MLX4_EN_NUM_PPP_RINGS; ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * Ethtool support ++ */ ++ ++static void ++mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ ++ sprintf(drvinfo->driver, DRV_NAME " (%s)", mdev->dev->board_id); ++ strncpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")", 32); ++ sprintf(drvinfo->fw_version, "%d.%d.%d", ++ (u16) (mdev->dev->caps.fw_ver >> 32), ++ (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff), ++ (u16) (mdev->dev->caps.fw_ver & 0xffff)); ++ strncpy(drvinfo->bus_info, pci_name(mdev->dev->pdev), 32); ++ drvinfo->n_stats = 0; ++ drvinfo->regdump_len = 0; ++ drvinfo->eedump_len = 0; ++} ++ ++static u32 mlx4_en_get_tso(struct net_device *dev) ++{ ++ return (dev->features & NETIF_F_TSO) != 0; ++} ++ ++static int mlx4_en_set_tso(struct net_device *dev, u32 data) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ ++ if (data) { ++ if (!priv->mdev->LSO_support) ++ return -EPERM; ++ dev->features |= (NETIF_F_TSO | NETIF_F_TSO6); ++ } else ++ dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6); ++ return 0; ++} ++ ++static u32 mlx4_en_get_rx_csum(struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ return priv->rx_csum; ++} ++ ++static int mlx4_en_set_rx_csum(struct net_device *dev, u32 data) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ priv->rx_csum = (data != 0); ++ return 0; ++} ++ ++static const char main_strings[][ETH_GSTRING_LEN] = { ++ "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", ++ "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", ++ "rx_length_errors", "rx_over_errors", "rx_crc_errors", ++ "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", ++ "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", ++ "tx_heartbeat_errors", "tx_window_errors", ++ ++ /* port statistics */ ++ "lro_aggregated", "lro_flushed", "lro_no_desc", "tso_packets", ++ "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed", ++ "rx_csum_good", "rx_csum_none", "tx_chksum_offload", ++ ++ /* packet statistics */ ++ "broadcast", "rx_prio_0", "rx_prio_1", "rx_prio_2", "rx_prio_3", ++ "rx_prio_4", "rx_prio_5", "rx_prio_6", "rx_prio_7", "tx_prio_0", ++ "tx_prio_1", "tx_prio_2", "tx_prio_3", "tx_prio_4", "tx_prio_5", ++ "tx_prio_6", "tx_prio_7", ++}; ++#define NUM_MAIN_STATS 21 ++#define NUM_ALL_STATS (NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PKT_STATS + NUM_PERF_STATS) ++ ++static u32 mlx4_en_get_msglevel(struct net_device *dev) ++{ ++ return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable; ++} ++ ++static void mlx4_en_set_msglevel(struct net_device *dev, u32 val) ++{ ++ ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val; ++} ++ ++static void mlx4_en_get_wol(struct net_device *netdev, ++ struct ethtool_wolinfo *wol) ++{ ++ wol->supported = 0; ++ wol->wolopts = 0; ++ ++ return; ++} ++ ++static int mlx4_en_get_sset_count(struct net_device *dev, int sset) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ ++ if (sset != ETH_SS_STATS) ++ return -EOPNOTSUPP; ++ ++ return NUM_ALL_STATS + (priv->tx_ring_num + priv->rx_ring_num) * 2; ++} ++ ++static void mlx4_en_get_ethtool_stats(struct net_device *dev, ++ struct ethtool_stats *stats, uint64_t *data) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ int index = 0; ++ int i; ++ ++ spin_lock_bh(&priv->stats_lock); ++ ++ for (i = 0; i < NUM_MAIN_STATS; i++) ++ data[index++] = ((unsigned long *) &priv->stats)[i]; ++ for (i = 0; i < NUM_PORT_STATS; i++) ++ data[index++] = ((unsigned long *) &priv->port_stats)[i]; ++ for (i = 0; i < priv->tx_ring_num; i++) { ++ data[index++] = priv->tx_ring[i].packets; ++ data[index++] = priv->tx_ring[i].bytes; ++ } ++ for (i = 0; i < priv->rx_ring_num; i++) { ++ data[index++] = priv->rx_ring[i].packets; ++ data[index++] = priv->rx_ring[i].bytes; ++ } ++ for (i = 0; i < NUM_PKT_STATS; i++) ++ data[index++] = ((unsigned long *) &priv->pkstats)[i]; ++ spin_unlock_bh(&priv->stats_lock); ++ ++} ++ ++static void mlx4_en_get_strings(struct net_device *dev, ++ uint32_t stringset, uint8_t *data) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ int index = 0; ++ int i; ++ ++ if (stringset != ETH_SS_STATS) ++ return; ++ ++ /* Add main counters */ ++ for (i = 0; i < NUM_MAIN_STATS; i++) ++ strcpy(data + (index++) * ETH_GSTRING_LEN, main_strings[i]); ++ for (i = 0; i< NUM_PORT_STATS; i++) ++ strcpy(data + (index++) * ETH_GSTRING_LEN, ++ main_strings[i + NUM_MAIN_STATS]); ++ for (i = 0; i < priv->tx_ring_num; i++) { ++ sprintf(data + (index++) * ETH_GSTRING_LEN, ++ "tx%d_packets", i); ++ sprintf(data + (index++) * ETH_GSTRING_LEN, ++ "tx%d_bytes", i); ++ } ++ for (i = 0; i < priv->rx_ring_num; i++) { ++ sprintf(data + (index++) * ETH_GSTRING_LEN, ++ "rx%d_packets", i); ++ sprintf(data + (index++) * ETH_GSTRING_LEN, ++ "rx%d_bytes", i); ++ } ++ for (i = 0; i< NUM_PKT_STATS; i++) ++ strcpy(data + (index++) * ETH_GSTRING_LEN, ++ main_strings[i + NUM_MAIN_STATS + NUM_PORT_STATS]); ++} ++ ++static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ int trans_type = priv->mdev->dev->caps.trans_type[priv->port]; ++ ++ cmd->autoneg = AUTONEG_DISABLE; ++ cmd->supported = SUPPORTED_10000baseT_Full; ++ cmd->advertising = ADVERTISED_10000baseT_Full; ++ if (netif_carrier_ok(dev)) { ++ cmd->speed = SPEED_10000; ++ cmd->duplex = DUPLEX_FULL; ++ } else { ++ cmd->speed = -1; ++ cmd->duplex = -1; ++ } ++ ++ if (trans_type > 0 && trans_type <= 0xC) { ++ cmd->port = PORT_FIBRE; ++ cmd->transceiver = XCVR_EXTERNAL; ++ cmd->supported |= SUPPORTED_FIBRE; ++ cmd->advertising |= ADVERTISED_FIBRE; ++ } else if (trans_type == 0x80 || trans_type == 0) { ++ cmd->port = PORT_TP; ++ cmd->transceiver = XCVR_INTERNAL; ++ cmd->supported |= SUPPORTED_TP; ++ cmd->advertising |= ADVERTISED_TP; ++ } else { ++ cmd->port = -1; ++ cmd->transceiver = -1; ++ } ++ return 0; ++} ++ ++static int mlx4_en_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ if ((cmd->autoneg == AUTONEG_ENABLE) || ++ (cmd->speed != SPEED_10000) || (cmd->duplex != DUPLEX_FULL)) ++ return -EINVAL; ++ ++ /* Nothing to change */ ++ return 0; ++} ++ ++static int mlx4_en_get_coalesce(struct net_device *dev, ++ struct ethtool_coalesce *coal) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ ++ coal->tx_coalesce_usecs = 0; ++ coal->tx_max_coalesced_frames = 0; ++ coal->rx_coalesce_usecs = priv->rx_usecs; ++ coal->rx_max_coalesced_frames = priv->rx_frames; ++ ++ coal->pkt_rate_low = priv->pkt_rate_low; ++ coal->rx_coalesce_usecs_low = priv->rx_usecs_low; ++ coal->pkt_rate_high = priv->pkt_rate_high; ++ coal->rx_coalesce_usecs_high = priv->rx_usecs_high; ++ coal->rate_sample_interval = priv->sample_interval; ++ coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal; ++ return 0; ++} ++ ++static int mlx4_en_set_coalesce(struct net_device *dev, ++ struct ethtool_coalesce *coal) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ int err, i; ++ ++ priv->rx_frames = (coal->rx_max_coalesced_frames == ++ MLX4_EN_AUTO_CONF) ? ++ MLX4_EN_RX_COAL_TARGET / ++ priv->dev->mtu + 1 : ++ coal->rx_max_coalesced_frames; ++ priv->rx_usecs = (coal->rx_coalesce_usecs == ++ MLX4_EN_AUTO_CONF) ? ++ MLX4_EN_RX_COAL_TIME : ++ coal->rx_coalesce_usecs; ++ ++ /* Set adaptive coalescing params */ ++ priv->pkt_rate_low = coal->pkt_rate_low; ++ priv->rx_usecs_low = coal->rx_coalesce_usecs_low; ++ priv->pkt_rate_high = coal->pkt_rate_high; ++ priv->rx_usecs_high = coal->rx_coalesce_usecs_high; ++ priv->sample_interval = coal->rate_sample_interval; ++ priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce; ++ priv->last_moder_time = MLX4_EN_AUTO_CONF; ++ if (priv->adaptive_rx_coal) ++ return 0; ++ ++ for (i = 0; i < priv->rx_ring_num; i++) { ++ priv->rx_cq[i].moder_cnt = priv->rx_frames; ++ priv->rx_cq[i].moder_time = priv->rx_usecs; ++ err = mlx4_en_set_cq_moder(priv, &priv->rx_cq[i]); ++ if (err) ++ return err; ++ } ++ return 0; ++} ++ ++static int mlx4_en_set_pauseparam(struct net_device *dev, ++ struct ethtool_pauseparam *pause) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int err; ++ ++ priv->prof->tx_pause = pause->tx_pause != 0; ++ priv->prof->rx_pause = pause->rx_pause != 0; ++ err = mlx4_SET_PORT_general(mdev->dev, priv->port, ++ priv->rx_skb_size + ETH_FCS_LEN, ++ priv->prof->tx_pause, ++ priv->prof->tx_ppp, ++ priv->prof->rx_pause, ++ priv->prof->rx_ppp); ++ if (err) ++ mlx4_err(mdev, "Failed setting pause params to\n"); ++ ++ return err; ++} ++ ++static void mlx4_en_get_pauseparam(struct net_device *dev, ++ struct ethtool_pauseparam *pause) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ ++ pause->tx_pause = priv->prof->tx_pause; ++ pause->rx_pause = priv->prof->rx_pause; ++} ++ ++static int mlx4_en_set_ringparam(struct net_device *dev, ++ struct ethtool_ringparam *param) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ u32 rx_size, tx_size; ++ int port_up = 0; ++ int err = 0; ++ ++ if (param->rx_jumbo_pending || param->rx_mini_pending) ++ return -EINVAL; ++ ++ rx_size = roundup_pow_of_two(param->rx_pending); ++ rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE); ++ rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE); ++ tx_size = roundup_pow_of_two(param->tx_pending); ++ tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE); ++ tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE); ++ ++ if (rx_size == priv->prof->rx_ring_size && ++ tx_size == priv->prof->tx_ring_size) ++ return 0; ++ ++ mutex_lock(&mdev->state_lock); ++ if (priv->port_up) { ++ port_up = 1; ++ mlx4_en_stop_port(dev); ++ } ++ ++ mlx4_en_free_resources(priv); ++ ++ priv->prof->tx_ring_size = tx_size; ++ priv->prof->rx_ring_size = rx_size; ++ ++ err = mlx4_en_alloc_resources(priv); ++ if (err) { ++ mlx4_err(mdev, "Failed reallocating port resources\n"); ++ goto out; ++ } ++ if (port_up) { ++ err = mlx4_en_start_port(dev); ++ if (err) ++ mlx4_err(mdev, "Failed starting port\n"); ++ } ++ ++out: ++ mutex_unlock(&mdev->state_lock); ++ return err; ++} ++ ++void mlx4_en_get_ringparam(struct net_device *dev, struct ethtool_ringparam *param) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ ++ memset(param, 0, sizeof(*param)); ++ param->rx_max_pending = MLX4_EN_MAX_RX_SIZE; ++ param->tx_max_pending = MLX4_EN_MAX_TX_SIZE; ++ param->rx_pending = mdev->profile.prof[priv->port].rx_ring_size; ++ param->tx_pending = mdev->profile.prof[priv->port].tx_ring_size; ++} ++ ++const struct ethtool_ops mlx4_en_ethtool_ops = { ++ .get_drvinfo = mlx4_en_get_drvinfo, ++ .get_settings = mlx4_en_get_settings, ++ .set_settings = mlx4_en_set_settings, ++#ifdef NETIF_F_TSO ++ .get_tso = mlx4_en_get_tso, ++ .set_tso = mlx4_en_set_tso, ++#endif ++ .get_sg = ethtool_op_get_sg, ++ .set_sg = ethtool_op_set_sg, ++ .get_link = ethtool_op_get_link, ++ .get_rx_csum = mlx4_en_get_rx_csum, ++ .set_rx_csum = mlx4_en_set_rx_csum, ++ .get_tx_csum = ethtool_op_get_tx_csum, ++ .set_tx_csum = ethtool_op_set_tx_csum, ++ .get_strings = mlx4_en_get_strings, ++ .get_sset_count = mlx4_en_get_sset_count, ++ .get_ethtool_stats = mlx4_en_get_ethtool_stats, ++ .get_wol = mlx4_en_get_wol, ++ .get_msglevel = mlx4_en_get_msglevel, ++ .set_msglevel = mlx4_en_set_msglevel, ++ .get_coalesce = mlx4_en_get_coalesce, ++ .set_coalesce = mlx4_en_set_coalesce, ++ .get_pauseparam = mlx4_en_get_pauseparam, ++ .set_pauseparam = mlx4_en_set_pauseparam, ++ .get_ringparam = mlx4_en_get_ringparam, ++ .set_ringparam = mlx4_en_set_ringparam, ++ .get_flags = ethtool_op_get_flags, ++ .set_flags = ethtool_op_set_flags, ++}; ++ ++ ++ ++ ++ +diff -r 4e706462aff6 drivers/net/mlx4/en_port.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/en_port.c Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,242 @@ ++/* ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++ ++#include ++ ++#include ++#include ++ ++#include "en_port.h" ++#include "mlx4_en.h" ++ ++ ++int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, ++ u64 mac, u64 clear, u8 mode) ++{ ++ return mlx4_cmd(dev, (mac | (clear << 63)), port, mode, ++ MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B); ++} ++ ++int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp) ++{ ++ struct mlx4_cmd_mailbox *mailbox; ++ struct mlx4_set_vlan_fltr_mbox *filter; ++ int i; ++ int j; ++ int index = 0; ++ u32 entry; ++ int err = 0; ++ ++ mailbox = mlx4_alloc_cmd_mailbox(dev); ++ if (IS_ERR(mailbox)) ++ return PTR_ERR(mailbox); ++ ++ filter = mailbox->buf; ++ if (grp) { ++ memset(filter, 0, sizeof *filter); ++ for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) { ++ entry = 0; ++ for (j = 0; j < 32; j++) ++ if (vlan_group_get_device(grp, index++)) ++ entry |= 1 << j; ++ filter->entry[i] = cpu_to_be32(entry); ++ } ++ } else { ++ /* When no vlans are configured we block all vlans */ ++ memset(filter, 0, sizeof(*filter)); ++ } ++ err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_VLAN_FLTR, ++ MLX4_CMD_TIME_CLASS_B); ++ mlx4_free_cmd_mailbox(dev, mailbox); ++ return err; ++} ++ ++ ++int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, ++ u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx) ++{ ++ struct mlx4_cmd_mailbox *mailbox; ++ struct mlx4_set_port_general_context *context; ++ int err; ++ u32 in_mod; ++ ++ mailbox = mlx4_alloc_cmd_mailbox(dev); ++ if (IS_ERR(mailbox)) ++ return PTR_ERR(mailbox); ++ context = mailbox->buf; ++ memset(context, 0, sizeof *context); ++ ++ context->flags = SET_PORT_GEN_ALL_VALID; ++ context->mtu = cpu_to_be16(mtu); ++ context->pptx = (pptx * (!pfctx)) << 7; ++ context->pfctx = pfctx; ++ context->pprx = (pprx * (!pfcrx)) << 7; ++ context->pfcrx = pfcrx; ++ ++ in_mod = MLX4_SET_PORT_GENERAL << 8 | port; ++ err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, ++ MLX4_CMD_TIME_CLASS_B); ++ ++ mlx4_free_cmd_mailbox(dev, mailbox); ++ return err; ++} ++ ++int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, ++ u8 promisc) ++{ ++ struct mlx4_cmd_mailbox *mailbox; ++ struct mlx4_set_port_rqp_calc_context *context; ++ int err; ++ u32 in_mod; ++ ++ mailbox = mlx4_alloc_cmd_mailbox(dev); ++ if (IS_ERR(mailbox)) ++ return PTR_ERR(mailbox); ++ context = mailbox->buf; ++ memset(context, 0, sizeof *context); ++ ++ context->base_qpn = cpu_to_be32(base_qpn); ++ context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT | base_qpn); ++ context->mcast = cpu_to_be32(1 << SET_PORT_PROMISC_SHIFT | base_qpn); ++ context->intra_no_vlan = 0; ++ context->no_vlan = MLX4_NO_VLAN_IDX; ++ context->intra_vlan_miss = 0; ++ context->vlan_miss = MLX4_VLAN_MISS_IDX; ++ ++ in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port; ++ err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, ++ MLX4_CMD_TIME_CLASS_B); ++ ++ mlx4_free_cmd_mailbox(dev, mailbox); ++ return err; ++} ++ ++ ++int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset) ++{ ++ struct mlx4_en_stat_out_mbox *mlx4_en_stats; ++ struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]); ++ struct net_device_stats *stats = &priv->stats; ++ struct mlx4_cmd_mailbox *mailbox; ++ u64 in_mod = reset << 8 | port; ++ int err; ++ int i; ++ ++ mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); ++ if (IS_ERR(mailbox)) ++ return PTR_ERR(mailbox); ++ memset(mailbox->buf, 0, sizeof(*mlx4_en_stats)); ++ err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0, ++ MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B); ++ if (err) ++ goto out; ++ ++ mlx4_en_stats = mailbox->buf; ++ ++ spin_lock_bh(&priv->stats_lock); ++ ++ stats->rx_packets = 0; ++ stats->rx_bytes = 0; ++ for (i = 0; i < priv->rx_ring_num; i++) { ++ stats->rx_packets += priv->rx_ring[i].packets; ++ stats->rx_bytes += priv->rx_ring[i].bytes; ++ } ++ stats->tx_packets = 0; ++ stats->tx_bytes = 0; ++ for (i = 0; i <= priv->tx_ring_num; i++) { ++ stats->tx_packets += priv->tx_ring[i].packets; ++ stats->tx_bytes += priv->tx_ring[i].bytes; ++ } ++ ++ stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) + ++ be32_to_cpu(mlx4_en_stats->RdropLength) + ++ be32_to_cpu(mlx4_en_stats->RJBBR) + ++ be32_to_cpu(mlx4_en_stats->RCRC) + ++ be32_to_cpu(mlx4_en_stats->RRUNT); ++ stats->tx_errors = be32_to_cpu(mlx4_en_stats->TDROP); ++ stats->multicast = be64_to_cpu(mlx4_en_stats->MCAST_prio_0) + ++ be64_to_cpu(mlx4_en_stats->MCAST_prio_1) + ++ be64_to_cpu(mlx4_en_stats->MCAST_prio_2) + ++ be64_to_cpu(mlx4_en_stats->MCAST_prio_3) + ++ be64_to_cpu(mlx4_en_stats->MCAST_prio_4) + ++ be64_to_cpu(mlx4_en_stats->MCAST_prio_5) + ++ be64_to_cpu(mlx4_en_stats->MCAST_prio_6) + ++ be64_to_cpu(mlx4_en_stats->MCAST_prio_7) + ++ be64_to_cpu(mlx4_en_stats->MCAST_novlan); ++ stats->collisions = 0; ++ stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength); ++ stats->rx_over_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw); ++ stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC); ++ stats->rx_frame_errors = 0; ++ stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw); ++ stats->rx_missed_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw); ++ stats->tx_aborted_errors = 0; ++ stats->tx_carrier_errors = 0; ++ stats->tx_fifo_errors = 0; ++ stats->tx_heartbeat_errors = 0; ++ stats->tx_window_errors = 0; ++ ++ priv->pkstats.broadcast = ++ be64_to_cpu(mlx4_en_stats->RBCAST_prio_0) + ++ be64_to_cpu(mlx4_en_stats->RBCAST_prio_1) + ++ be64_to_cpu(mlx4_en_stats->RBCAST_prio_2) + ++ be64_to_cpu(mlx4_en_stats->RBCAST_prio_3) + ++ be64_to_cpu(mlx4_en_stats->RBCAST_prio_4) + ++ be64_to_cpu(mlx4_en_stats->RBCAST_prio_5) + ++ be64_to_cpu(mlx4_en_stats->RBCAST_prio_6) + ++ be64_to_cpu(mlx4_en_stats->RBCAST_prio_7) + ++ be64_to_cpu(mlx4_en_stats->RBCAST_novlan); ++ priv->pkstats.rx_prio[0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0); ++ priv->pkstats.rx_prio[1] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1); ++ priv->pkstats.rx_prio[2] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2); ++ priv->pkstats.rx_prio[3] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3); ++ priv->pkstats.rx_prio[4] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4); ++ priv->pkstats.rx_prio[5] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5); ++ priv->pkstats.rx_prio[6] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6); ++ priv->pkstats.rx_prio[7] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7); ++ priv->pkstats.tx_prio[0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0); ++ priv->pkstats.tx_prio[1] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1); ++ priv->pkstats.tx_prio[2] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2); ++ priv->pkstats.tx_prio[3] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3); ++ priv->pkstats.tx_prio[4] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4); ++ priv->pkstats.tx_prio[5] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5); ++ priv->pkstats.tx_prio[6] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6); ++ priv->pkstats.tx_prio[7] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7); ++ spin_unlock_bh(&priv->stats_lock); ++ ++out: ++ mlx4_free_cmd_mailbox(mdev->dev, mailbox); ++ return err; ++} ++ +diff -r 4e706462aff6 drivers/net/mlx4/en_port.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/en_port.h Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,570 @@ ++/* ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++#ifndef _MLX4_EN_PORT_H_ ++#define _MLX4_EN_PORT_H_ ++ ++ ++#define SET_PORT_GEN_ALL_VALID 0x7 ++#define SET_PORT_PROMISC_SHIFT 31 ++ ++enum { ++ MLX4_CMD_SET_VLAN_FLTR = 0x47, ++ MLX4_CMD_SET_MCAST_FLTR = 0x48, ++ MLX4_CMD_DUMP_ETH_STATS = 0x49, ++}; ++ ++struct mlx4_set_port_general_context { ++ u8 reserved[3]; ++ u8 flags; ++ u16 reserved2; ++ __be16 mtu; ++ u8 pptx; ++ u8 pfctx; ++ u16 reserved3; ++ u8 pprx; ++ u8 pfcrx; ++ u16 reserved4; ++}; ++ ++struct mlx4_set_port_rqp_calc_context { ++ __be32 base_qpn; ++ __be32 flags; ++ u8 reserved[3]; ++ u8 mac_miss; ++ u8 intra_no_vlan; ++ u8 no_vlan; ++ u8 intra_vlan_miss; ++ u8 vlan_miss; ++ u8 reserved4[3]; ++ u8 no_vlan_prio; ++ __be32 promisc; ++ __be32 mcast; ++}; ++ ++#define VLAN_FLTR_SIZE 128 ++struct mlx4_set_vlan_fltr_mbox { ++ __be32 entry[VLAN_FLTR_SIZE]; ++}; ++ ++ ++enum { ++ MLX4_MCAST_CONFIG = 0, ++ MLX4_MCAST_DISABLE = 1, ++ MLX4_MCAST_ENABLE = 2, ++}; ++ ++ ++struct mlx4_en_stat_out_mbox { ++ /* Received frames with a length of 64 octets */ ++ __be64 R64_prio_0; ++ __be64 R64_prio_1; ++ __be64 R64_prio_2; ++ __be64 R64_prio_3; ++ __be64 R64_prio_4; ++ __be64 R64_prio_5; ++ __be64 R64_prio_6; ++ __be64 R64_prio_7; ++ __be64 R64_novlan; ++ /* Received frames with a length of 127 octets */ ++ __be64 R127_prio_0; ++ __be64 R127_prio_1; ++ __be64 R127_prio_2; ++ __be64 R127_prio_3; ++ __be64 R127_prio_4; ++ __be64 R127_prio_5; ++ __be64 R127_prio_6; ++ __be64 R127_prio_7; ++ __be64 R127_novlan; ++ /* Received frames with a length of 255 octets */ ++ __be64 R255_prio_0; ++ __be64 R255_prio_1; ++ __be64 R255_prio_2; ++ __be64 R255_prio_3; ++ __be64 R255_prio_4; ++ __be64 R255_prio_5; ++ __be64 R255_prio_6; ++ __be64 R255_prio_7; ++ __be64 R255_novlan; ++ /* Received frames with a length of 511 octets */ ++ __be64 R511_prio_0; ++ __be64 R511_prio_1; ++ __be64 R511_prio_2; ++ __be64 R511_prio_3; ++ __be64 R511_prio_4; ++ __be64 R511_prio_5; ++ __be64 R511_prio_6; ++ __be64 R511_prio_7; ++ __be64 R511_novlan; ++ /* Received frames with a length of 1023 octets */ ++ __be64 R1023_prio_0; ++ __be64 R1023_prio_1; ++ __be64 R1023_prio_2; ++ __be64 R1023_prio_3; ++ __be64 R1023_prio_4; ++ __be64 R1023_prio_5; ++ __be64 R1023_prio_6; ++ __be64 R1023_prio_7; ++ __be64 R1023_novlan; ++ /* Received frames with a length of 1518 octets */ ++ __be64 R1518_prio_0; ++ __be64 R1518_prio_1; ++ __be64 R1518_prio_2; ++ __be64 R1518_prio_3; ++ __be64 R1518_prio_4; ++ __be64 R1518_prio_5; ++ __be64 R1518_prio_6; ++ __be64 R1518_prio_7; ++ __be64 R1518_novlan; ++ /* Received frames with a length of 1522 octets */ ++ __be64 R1522_prio_0; ++ __be64 R1522_prio_1; ++ __be64 R1522_prio_2; ++ __be64 R1522_prio_3; ++ __be64 R1522_prio_4; ++ __be64 R1522_prio_5; ++ __be64 R1522_prio_6; ++ __be64 R1522_prio_7; ++ __be64 R1522_novlan; ++ /* Received frames with a length of 1548 octets */ ++ __be64 R1548_prio_0; ++ __be64 R1548_prio_1; ++ __be64 R1548_prio_2; ++ __be64 R1548_prio_3; ++ __be64 R1548_prio_4; ++ __be64 R1548_prio_5; ++ __be64 R1548_prio_6; ++ __be64 R1548_prio_7; ++ __be64 R1548_novlan; ++ /* Received frames with a length of 1548 < octets < MTU */ ++ __be64 R2MTU_prio_0; ++ __be64 R2MTU_prio_1; ++ __be64 R2MTU_prio_2; ++ __be64 R2MTU_prio_3; ++ __be64 R2MTU_prio_4; ++ __be64 R2MTU_prio_5; ++ __be64 R2MTU_prio_6; ++ __be64 R2MTU_prio_7; ++ __be64 R2MTU_novlan; ++ /* Received frames with a length of MTU< octets and good CRC */ ++ __be64 RGIANT_prio_0; ++ __be64 RGIANT_prio_1; ++ __be64 RGIANT_prio_2; ++ __be64 RGIANT_prio_3; ++ __be64 RGIANT_prio_4; ++ __be64 RGIANT_prio_5; ++ __be64 RGIANT_prio_6; ++ __be64 RGIANT_prio_7; ++ __be64 RGIANT_novlan; ++ /* Received broadcast frames with good CRC */ ++ __be64 RBCAST_prio_0; ++ __be64 RBCAST_prio_1; ++ __be64 RBCAST_prio_2; ++ __be64 RBCAST_prio_3; ++ __be64 RBCAST_prio_4; ++ __be64 RBCAST_prio_5; ++ __be64 RBCAST_prio_6; ++ __be64 RBCAST_prio_7; ++ __be64 RBCAST_novlan; ++ /* Received multicast frames with good CRC */ ++ __be64 MCAST_prio_0; ++ __be64 MCAST_prio_1; ++ __be64 MCAST_prio_2; ++ __be64 MCAST_prio_3; ++ __be64 MCAST_prio_4; ++ __be64 MCAST_prio_5; ++ __be64 MCAST_prio_6; ++ __be64 MCAST_prio_7; ++ __be64 MCAST_novlan; ++ /* Received unicast not short or GIANT frames with good CRC */ ++ __be64 RTOTG_prio_0; ++ __be64 RTOTG_prio_1; ++ __be64 RTOTG_prio_2; ++ __be64 RTOTG_prio_3; ++ __be64 RTOTG_prio_4; ++ __be64 RTOTG_prio_5; ++ __be64 RTOTG_prio_6; ++ __be64 RTOTG_prio_7; ++ __be64 RTOTG_novlan; ++ ++ /* Count of total octets of received frames, includes framing characters */ ++ __be64 RTTLOCT_prio_0; ++ /* Count of total octets of received frames, not including framing ++ characters */ ++ __be64 RTTLOCT_NOFRM_prio_0; ++ /* Count of Total number of octets received ++ (only for frames without errors) */ ++ __be64 ROCT_prio_0; ++ ++ __be64 RTTLOCT_prio_1; ++ __be64 RTTLOCT_NOFRM_prio_1; ++ __be64 ROCT_prio_1; ++ ++ __be64 RTTLOCT_prio_2; ++ __be64 RTTLOCT_NOFRM_prio_2; ++ __be64 ROCT_prio_2; ++ ++ __be64 RTTLOCT_prio_3; ++ __be64 RTTLOCT_NOFRM_prio_3; ++ __be64 ROCT_prio_3; ++ ++ __be64 RTTLOCT_prio_4; ++ __be64 RTTLOCT_NOFRM_prio_4; ++ __be64 ROCT_prio_4; ++ ++ __be64 RTTLOCT_prio_5; ++ __be64 RTTLOCT_NOFRM_prio_5; ++ __be64 ROCT_prio_5; ++ ++ __be64 RTTLOCT_prio_6; ++ __be64 RTTLOCT_NOFRM_prio_6; ++ __be64 ROCT_prio_6; ++ ++ __be64 RTTLOCT_prio_7; ++ __be64 RTTLOCT_NOFRM_prio_7; ++ __be64 ROCT_prio_7; ++ ++ __be64 RTTLOCT_novlan; ++ __be64 RTTLOCT_NOFRM_novlan; ++ __be64 ROCT_novlan; ++ ++ /* Count of Total received frames including bad frames */ ++ __be64 RTOT_prio_0; ++ /* Count of Total number of received frames with 802.1Q encapsulation */ ++ __be64 R1Q_prio_0; ++ __be64 reserved1; ++ ++ __be64 RTOT_prio_1; ++ __be64 R1Q_prio_1; ++ __be64 reserved2; ++ ++ __be64 RTOT_prio_2; ++ __be64 R1Q_prio_2; ++ __be64 reserved3; ++ ++ __be64 RTOT_prio_3; ++ __be64 R1Q_prio_3; ++ __be64 reserved4; ++ ++ __be64 RTOT_prio_4; ++ __be64 R1Q_prio_4; ++ __be64 reserved5; ++ ++ __be64 RTOT_prio_5; ++ __be64 R1Q_prio_5; ++ __be64 reserved6; ++ ++ __be64 RTOT_prio_6; ++ __be64 R1Q_prio_6; ++ __be64 reserved7; ++ ++ __be64 RTOT_prio_7; ++ __be64 R1Q_prio_7; ++ __be64 reserved8; ++ ++ __be64 RTOT_novlan; ++ __be64 R1Q_novlan; ++ __be64 reserved9; ++ ++ /* Total number of Successfully Received Control Frames */ ++ __be64 RCNTL; ++ __be64 reserved10; ++ __be64 reserved11; ++ __be64 reserved12; ++ /* Count of received frames with a length/type field value between 46 ++ (42 for VLANtagged frames) and 1500 (also 1500 for VLAN-tagged frames), ++ inclusive */ ++ __be64 RInRangeLengthErr; ++ /* Count of received frames with length/type field between 1501 and 1535 ++ decimal, inclusive */ ++ __be64 ROutRangeLengthErr; ++ /* Count of received frames that are longer than max allowed size for ++ 802.3 frames (1518/1522) */ ++ __be64 RFrmTooLong; ++ /* Count frames received with PCS error */ ++ __be64 PCS; ++ ++ /* Transmit frames with a length of 64 octets */ ++ __be64 T64_prio_0; ++ __be64 T64_prio_1; ++ __be64 T64_prio_2; ++ __be64 T64_prio_3; ++ __be64 T64_prio_4; ++ __be64 T64_prio_5; ++ __be64 T64_prio_6; ++ __be64 T64_prio_7; ++ __be64 T64_novlan; ++ __be64 T64_loopbk; ++ /* Transmit frames with a length of 65 to 127 octets. */ ++ __be64 T127_prio_0; ++ __be64 T127_prio_1; ++ __be64 T127_prio_2; ++ __be64 T127_prio_3; ++ __be64 T127_prio_4; ++ __be64 T127_prio_5; ++ __be64 T127_prio_6; ++ __be64 T127_prio_7; ++ __be64 T127_novlan; ++ __be64 T127_loopbk; ++ /* Transmit frames with a length of 128 to 255 octets */ ++ __be64 T255_prio_0; ++ __be64 T255_prio_1; ++ __be64 T255_prio_2; ++ __be64 T255_prio_3; ++ __be64 T255_prio_4; ++ __be64 T255_prio_5; ++ __be64 T255_prio_6; ++ __be64 T255_prio_7; ++ __be64 T255_novlan; ++ __be64 T255_loopbk; ++ /* Transmit frames with a length of 256 to 511 octets */ ++ __be64 T511_prio_0; ++ __be64 T511_prio_1; ++ __be64 T511_prio_2; ++ __be64 T511_prio_3; ++ __be64 T511_prio_4; ++ __be64 T511_prio_5; ++ __be64 T511_prio_6; ++ __be64 T511_prio_7; ++ __be64 T511_novlan; ++ __be64 T511_loopbk; ++ /* Transmit frames with a length of 512 to 1023 octets */ ++ __be64 T1023_prio_0; ++ __be64 T1023_prio_1; ++ __be64 T1023_prio_2; ++ __be64 T1023_prio_3; ++ __be64 T1023_prio_4; ++ __be64 T1023_prio_5; ++ __be64 T1023_prio_6; ++ __be64 T1023_prio_7; ++ __be64 T1023_novlan; ++ __be64 T1023_loopbk; ++ /* Transmit frames with a length of 1024 to 1518 octets */ ++ __be64 T1518_prio_0; ++ __be64 T1518_prio_1; ++ __be64 T1518_prio_2; ++ __be64 T1518_prio_3; ++ __be64 T1518_prio_4; ++ __be64 T1518_prio_5; ++ __be64 T1518_prio_6; ++ __be64 T1518_prio_7; ++ __be64 T1518_novlan; ++ __be64 T1518_loopbk; ++ /* Counts transmit frames with a length of 1519 to 1522 bytes */ ++ __be64 T1522_prio_0; ++ __be64 T1522_prio_1; ++ __be64 T1522_prio_2; ++ __be64 T1522_prio_3; ++ __be64 T1522_prio_4; ++ __be64 T1522_prio_5; ++ __be64 T1522_prio_6; ++ __be64 T1522_prio_7; ++ __be64 T1522_novlan; ++ __be64 T1522_loopbk; ++ /* Transmit frames with a length of 1523 to 1548 octets */ ++ __be64 T1548_prio_0; ++ __be64 T1548_prio_1; ++ __be64 T1548_prio_2; ++ __be64 T1548_prio_3; ++ __be64 T1548_prio_4; ++ __be64 T1548_prio_5; ++ __be64 T1548_prio_6; ++ __be64 T1548_prio_7; ++ __be64 T1548_novlan; ++ __be64 T1548_loopbk; ++ /* Counts transmit frames with a length of 1549 to MTU bytes */ ++ __be64 T2MTU_prio_0; ++ __be64 T2MTU_prio_1; ++ __be64 T2MTU_prio_2; ++ __be64 T2MTU_prio_3; ++ __be64 T2MTU_prio_4; ++ __be64 T2MTU_prio_5; ++ __be64 T2MTU_prio_6; ++ __be64 T2MTU_prio_7; ++ __be64 T2MTU_novlan; ++ __be64 T2MTU_loopbk; ++ /* Transmit frames with a length greater than MTU octets and a good CRC. */ ++ __be64 TGIANT_prio_0; ++ __be64 TGIANT_prio_1; ++ __be64 TGIANT_prio_2; ++ __be64 TGIANT_prio_3; ++ __be64 TGIANT_prio_4; ++ __be64 TGIANT_prio_5; ++ __be64 TGIANT_prio_6; ++ __be64 TGIANT_prio_7; ++ __be64 TGIANT_novlan; ++ __be64 TGIANT_loopbk; ++ /* Transmit broadcast frames with a good CRC */ ++ __be64 TBCAST_prio_0; ++ __be64 TBCAST_prio_1; ++ __be64 TBCAST_prio_2; ++ __be64 TBCAST_prio_3; ++ __be64 TBCAST_prio_4; ++ __be64 TBCAST_prio_5; ++ __be64 TBCAST_prio_6; ++ __be64 TBCAST_prio_7; ++ __be64 TBCAST_novlan; ++ __be64 TBCAST_loopbk; ++ /* Transmit multicast frames with a good CRC */ ++ __be64 TMCAST_prio_0; ++ __be64 TMCAST_prio_1; ++ __be64 TMCAST_prio_2; ++ __be64 TMCAST_prio_3; ++ __be64 TMCAST_prio_4; ++ __be64 TMCAST_prio_5; ++ __be64 TMCAST_prio_6; ++ __be64 TMCAST_prio_7; ++ __be64 TMCAST_novlan; ++ __be64 TMCAST_loopbk; ++ /* Transmit good frames that are neither broadcast nor multicast */ ++ __be64 TTOTG_prio_0; ++ __be64 TTOTG_prio_1; ++ __be64 TTOTG_prio_2; ++ __be64 TTOTG_prio_3; ++ __be64 TTOTG_prio_4; ++ __be64 TTOTG_prio_5; ++ __be64 TTOTG_prio_6; ++ __be64 TTOTG_prio_7; ++ __be64 TTOTG_novlan; ++ __be64 TTOTG_loopbk; ++ ++ /* total octets of transmitted frames, including framing characters */ ++ __be64 TTTLOCT_prio_0; ++ /* total octets of transmitted frames, not including framing characters */ ++ __be64 TTTLOCT_NOFRM_prio_0; ++ /* ifOutOctets */ ++ __be64 TOCT_prio_0; ++ ++ __be64 TTTLOCT_prio_1; ++ __be64 TTTLOCT_NOFRM_prio_1; ++ __be64 TOCT_prio_1; ++ ++ __be64 TTTLOCT_prio_2; ++ __be64 TTTLOCT_NOFRM_prio_2; ++ __be64 TOCT_prio_2; ++ ++ __be64 TTTLOCT_prio_3; ++ __be64 TTTLOCT_NOFRM_prio_3; ++ __be64 TOCT_prio_3; ++ ++ __be64 TTTLOCT_prio_4; ++ __be64 TTTLOCT_NOFRM_prio_4; ++ __be64 TOCT_prio_4; ++ ++ __be64 TTTLOCT_prio_5; ++ __be64 TTTLOCT_NOFRM_prio_5; ++ __be64 TOCT_prio_5; ++ ++ __be64 TTTLOCT_prio_6; ++ __be64 TTTLOCT_NOFRM_prio_6; ++ __be64 TOCT_prio_6; ++ ++ __be64 TTTLOCT_prio_7; ++ __be64 TTTLOCT_NOFRM_prio_7; ++ __be64 TOCT_prio_7; ++ ++ __be64 TTTLOCT_novlan; ++ __be64 TTTLOCT_NOFRM_novlan; ++ __be64 TOCT_novlan; ++ ++ __be64 TTTLOCT_loopbk; ++ __be64 TTTLOCT_NOFRM_loopbk; ++ __be64 TOCT_loopbk; ++ ++ /* Total frames transmitted with a good CRC that are not aborted */ ++ __be64 TTOT_prio_0; ++ /* Total number of frames transmitted with 802.1Q encapsulation */ ++ __be64 T1Q_prio_0; ++ __be64 reserved13; ++ ++ __be64 TTOT_prio_1; ++ __be64 T1Q_prio_1; ++ __be64 reserved14; ++ ++ __be64 TTOT_prio_2; ++ __be64 T1Q_prio_2; ++ __be64 reserved15; ++ ++ __be64 TTOT_prio_3; ++ __be64 T1Q_prio_3; ++ __be64 reserved16; ++ ++ __be64 TTOT_prio_4; ++ __be64 T1Q_prio_4; ++ __be64 reserved17; ++ ++ __be64 TTOT_prio_5; ++ __be64 T1Q_prio_5; ++ __be64 reserved18; ++ ++ __be64 TTOT_prio_6; ++ __be64 T1Q_prio_6; ++ __be64 reserved19; ++ ++ __be64 TTOT_prio_7; ++ __be64 T1Q_prio_7; ++ __be64 reserved20; ++ ++ __be64 TTOT_novlan; ++ __be64 T1Q_novlan; ++ __be64 reserved21; ++ ++ __be64 TTOT_loopbk; ++ __be64 T1Q_loopbk; ++ __be64 reserved22; ++ ++ /* Received frames with a length greater than MTU octets and a bad CRC */ ++ __be32 RJBBR; ++ /* Received frames with a bad CRC that are not runts, jabbers, ++ or alignment errors */ ++ __be32 RCRC; ++ /* Received frames with SFD with a length of less than 64 octets and a ++ bad CRC */ ++ __be32 RRUNT; ++ /* Received frames with a length less than 64 octets and a good CRC */ ++ __be32 RSHORT; ++ /* Total Number of Received Packets Dropped */ ++ __be32 RDROP; ++ /* Drop due to overflow */ ++ __be32 RdropOvflw; ++ /* Drop due to overflow */ ++ __be32 RdropLength; ++ /* Total of good frames. Does not include frames received with ++ frame-too-long, FCS, or length errors */ ++ __be32 RTOTFRMS; ++ /* Total dropped Xmited packets */ ++ __be32 TDROP; ++}; ++ ++ ++#endif +diff -r 4e706462aff6 drivers/net/mlx4/en_resources.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/en_resources.c Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,102 @@ ++/* ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++#include ++#include ++ ++#include "mlx4_en.h" ++ ++void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, ++ int is_tx, int rss, int qpn, int cqn, int srqn, ++ struct mlx4_qp_context *context) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ ++ memset(context, 0, sizeof *context); ++ context->flags = cpu_to_be32(7 << 16 | rss << 13); ++ context->pd = cpu_to_be32(mdev->priv_pdn); ++ context->mtu_msgmax = 0xff; ++ context->rq_size_stride = 0; ++ if (is_tx) ++ context->sq_size_stride = ilog2(size) << 3 | (ilog2(stride) - 4); ++ else ++ context->sq_size_stride = 1; ++ context->usr_page = cpu_to_be32(mdev->priv_uar.index); ++ context->local_qpn = cpu_to_be32(qpn); ++ context->pri_path.ackto = 1 & 0x07; ++ context->pri_path.sched_queue = 0x83 | (priv->port - 1) << 6; ++ context->pri_path.counter_index = 0xff; ++ context->cqn_send = cpu_to_be32(cqn); ++ context->cqn_recv = cpu_to_be32(cqn); ++ context->db_rec_addr = cpu_to_be64(priv->res.db.dma << 2); ++ if (!rss) ++ context->srqn = cpu_to_be32(MLX4_EN_USE_SRQ | srqn); ++} ++ ++ ++int mlx4_en_map_buffer(struct mlx4_buf *buf) ++{ ++ struct page **pages; ++ int i; ++ ++ if (BITS_PER_LONG == 64 || buf->nbufs == 1) ++ return 0; ++ ++ pages = kmalloc(sizeof *pages * buf->nbufs, GFP_KERNEL); ++ if (!pages) ++ return -ENOMEM; ++ ++ for (i = 0; i < buf->nbufs; ++i) ++ pages[i] = virt_to_page(buf->page_list[i].buf); ++ ++ buf->direct.buf = vmap(pages, buf->nbufs, VM_MAP, PAGE_KERNEL); ++ kfree(pages); ++ if (!buf->direct.buf) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++void mlx4_en_unmap_buffer(struct mlx4_buf *buf) ++{ ++ if (BITS_PER_LONG == 64 || buf->nbufs == 1) ++ return; ++ ++ vunmap(buf->direct.buf); ++} ++ ++void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event) ++{ ++ return; ++} ++ +diff -r 4e706462aff6 drivers/net/mlx4/en_rx.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/en_rx.c Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,1246 @@ ++/* ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mlx4_en.h" ++ ++static void *get_wqe(struct mlx4_en_rx_ring *ring, int n) ++{ ++ int offset = n << ring->srq.wqe_shift; ++ return ring->buf + offset; ++} ++ ++static void mlx4_en_srq_event(struct mlx4_srq *srq, enum mlx4_event type) ++{ ++ return; ++} ++ ++static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_desc *rx_desc, ++ struct skb_frag_struct *skb_frags, ++ struct mlx4_en_rx_alloc *ring_alloc, ++ int i) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; ++ struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i]; ++ struct page *page; ++ dma_addr_t dma; ++ ++ if (page_alloc->offset == frag_info->last_offset) { ++ /* Allocate new page */ ++ page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER); ++ if (!page) ++ return -ENOMEM; ++ ++ skb_frags[i].page = page_alloc->page; ++ skb_frags[i].page_offset = page_alloc->offset; ++ page_alloc->page = page; ++ page_alloc->offset = frag_info->frag_align; ++ } else { ++ page = page_alloc->page; ++ get_page(page); ++ ++ skb_frags[i].page = page; ++ skb_frags[i].page_offset = page_alloc->offset; ++ page_alloc->offset += frag_info->frag_stride; ++ } ++ dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) + ++ skb_frags[i].page_offset, frag_info->frag_size, ++ PCI_DMA_FROMDEVICE); ++ rx_desc->data[i].addr = cpu_to_be64(dma); ++ return 0; ++} ++ ++static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring) ++{ ++ struct mlx4_en_rx_alloc *page_alloc; ++ int i; ++ ++ for (i = 0; i < priv->num_frags; i++) { ++ page_alloc = &ring->page_alloc[i]; ++ page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP, ++ MLX4_EN_ALLOC_ORDER); ++ if (!page_alloc->page) ++ goto out; ++ ++ page_alloc->offset = priv->frag_info[i].frag_align; ++ mlx4_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n", ++ i, page_alloc->page); ++ } ++ return 0; ++ ++out: ++ while (i--) { ++ page_alloc = &ring->page_alloc[i]; ++ put_page(page_alloc->page); ++ page_alloc->page = NULL; ++ } ++ return -ENOMEM; ++} ++ ++static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring) ++{ ++ struct mlx4_en_rx_alloc *page_alloc; ++ int i; ++ ++ for (i = 0; i < priv->num_frags; i++) { ++ page_alloc = &ring->page_alloc[i]; ++ mlx4_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", ++ i, page_count(page_alloc->page)); ++ ++ put_page(page_alloc->page); ++ page_alloc->page = NULL; ++ } ++} ++ ++static void ++mlx4_en_init_rx_desc_skb(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring, int index) ++{ ++ struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; ++ ++ /* Pre-link descriptor */ ++ rx_desc->next.next_wqe_index = cpu_to_be16((index + 1) & ring->size_mask); ++ rx_desc->data->byte_count = cpu_to_be32(priv->rx_skb_size); ++ rx_desc->data->lkey = cpu_to_be32(priv->mdev->mr.key); ++} ++ ++static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring, int index) ++{ ++ struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; ++ struct skb_frag_struct *skb_frags = ring->rx_info + ++ (index << priv->log_rx_info); ++ int possible_frags; ++ int i; ++ ++ /* Pre-link descriptor */ ++ rx_desc->next.next_wqe_index = cpu_to_be16((index + 1) & ring->size_mask); ++ ++ /* Set size and memtype fields */ ++ for (i = 0; i < priv->num_frags; i++) { ++ skb_frags[i].size = priv->frag_info[i].frag_size; ++ rx_desc->data[i].byte_count = ++ cpu_to_be32(priv->frag_info[i].frag_size); ++ rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); ++ } ++ ++ /* If the number of used fragments does not fill up the ring stride, ++ * remaining (unused) fragments must be padded with null address/size ++ * and a special memory key */ ++ possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; ++ for (i = priv->num_frags; i < possible_frags; i++) { ++ rx_desc->data[i].byte_count = 0; ++ rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); ++ rx_desc->data[i].addr = 0; ++ } ++} ++ ++static int ++mlx4_en_alloc_rx_skb(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_desc *rx_desc, ++ struct sk_buff **pskb) ++{ ++ dma_addr_t dma; ++ int size = priv->rx_skb_size + NET_IP_ALIGN; ++ struct sk_buff *new_skb = alloc_skb(size, GFP_ATOMIC); ++ ++ if (unlikely(new_skb == NULL)) ++ return -ENOMEM; ++ ++ new_skb->dev = priv->dev; ++ skb_reserve(new_skb, NET_IP_ALIGN); ++ dma = pci_map_single(priv->mdev->pdev, new_skb->data, size, DMA_FROM_DEVICE); ++ *pskb = new_skb; ++ rx_desc->data->addr = cpu_to_be64(dma); ++ return 0; ++} ++ ++static int ++mlx4_en_prepare_rx_desc_skb(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring, int index) ++{ ++ struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); ++ struct sk_buff **pskb = (struct sk_buff **) ring->rx_info + index; ++ ++ return mlx4_en_alloc_rx_skb(priv, rx_desc, pskb); ++} ++ ++static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring, int index) ++{ ++ struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); ++ struct skb_frag_struct *skb_frags = ring->rx_info + ++ (index << priv->log_rx_info); ++ int i; ++ ++ for (i = 0; i < priv->num_frags; i++) ++ if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i)) ++ goto err; ++ ++ return 0; ++ ++err: ++ while (i--) ++ put_page(skb_frags[i].page); ++ return -ENOMEM; ++} ++ ++static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) ++{ ++ *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); ++} ++ ++static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_en_rx_ring *ring; ++ int ring_ind; ++ int buf_ind; ++ int err; ++ ++ for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { ++ for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { ++ ring = &priv->rx_ring[ring_ind]; ++ ++ if (ring->use_frags) ++ err = mlx4_en_prepare_rx_desc(priv, ring, ++ ring->actual_size); ++ else ++ err = mlx4_en_prepare_rx_desc_skb(priv, ring, ++ ring->actual_size); ++ if (err) { ++ mlx4_err(mdev, "Failed to allocate " ++ "enough rx buffers\n"); ++ return -ENOMEM; ++ } ++ ring->actual_size++; ++ ring->prod++; ++ } ++ } ++out: ++ return 0; ++} ++ ++static int mlx4_en_fill_rx_buf(struct net_device *dev, ++ struct mlx4_en_rx_ring *ring) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ int num = 0; ++ int err; ++ ++ while ((u32) (ring->prod - ring->cons) < ring->actual_size) { ++ if (ring->use_frags) ++ err = mlx4_en_prepare_rx_desc(priv, ring, ring->prod & ++ ring->size_mask); ++ else ++ err = mlx4_en_prepare_rx_desc_skb(priv, ring, ring->prod & ++ ring->size_mask); ++ if (err) { ++ if (netif_msg_rx_err(priv)) ++ mlx4_warn(priv->mdev, ++ "Failed preparing rx descriptor\n"); ++ priv->port_stats.rx_alloc_failed++; ++ break; ++ } ++ ++num; ++ ++ring->prod; ++ } ++ if ((u32) (ring->prod - ring->cons) == ring->size) ++ ring->full = 1; ++ ++ return num; ++} ++ ++static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct skb_frag_struct *skb_frags; ++ struct sk_buff *skb; ++ struct mlx4_en_rx_desc *rx_desc; ++ dma_addr_t dma; ++ int index; ++ int nr; ++ ++ mlx4_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", ++ ring->cons, ring->prod); ++ ++ /* Unmap and free Rx buffers */ ++ BUG_ON((u32) (ring->prod - ring->cons) > ring->size); ++ while (ring->cons != ring->prod) { ++ index = ring->cons & ring->size_mask; ++ rx_desc = ring->buf + (index << ring->log_stride); ++ mlx4_dbg(DRV, priv, "Processing descriptor:%d\n", index); ++ ++ if (ring->use_frags) { ++ skb_frags = ring->rx_info + (index << priv->log_rx_info); ++ for (nr = 0; nr < priv->num_frags; nr++) { ++ mlx4_dbg(DRV, priv, "Freeing fragment:%d\n", nr); ++ dma = be64_to_cpu(rx_desc->data[nr].addr); ++ ++ mlx4_dbg(DRV, priv, "Unmaping buffer at dma:0x%llx\n", (u64) dma); ++ pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size, ++ PCI_DMA_FROMDEVICE); ++ put_page(skb_frags[nr].page); ++ } ++ } else { ++ skb = *((struct sk_buff **) ring->rx_info + index); ++ dma = be64_to_cpu(rx_desc->data->addr); ++ pci_unmap_single(mdev->pdev, dma, ++ priv->rx_skb_size + NET_IP_ALIGN, ++ PCI_DMA_FROMDEVICE); ++ kfree_skb(skb); ++ } ++ ++ring->cons; ++ } ++} ++ ++ ++void mlx4_en_rx_refill(struct work_struct *work) ++{ ++ struct delayed_work *delay = container_of(work, struct delayed_work, work); ++ struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv, ++ refill_task); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct net_device *dev = priv->dev; ++ struct mlx4_en_rx_ring *ring; ++ int need_refill = 0; ++ int i; ++ ++ mutex_lock(&mdev->state_lock); ++ if (!mdev->device_up || !priv->port_up) ++ goto out; ++ ++ /* We only get here if there are no receive buffers, so we can't race ++ * with Rx interrupts while filling buffers */ ++ for (i = 0; i < priv->rx_ring_num; i++) { ++ ring = &priv->rx_ring[i]; ++ if (ring->need_refill) { ++ if (mlx4_en_fill_rx_buf(dev, ring)) { ++ ring->need_refill = 0; ++ mlx4_en_update_rx_prod_db(ring); ++ } else ++ need_refill = 1; ++ } ++ } ++ if (need_refill) ++ queue_delayed_work(mdev->workqueue, &priv->refill_task, HZ); ++ ++out: ++ mutex_unlock(&mdev->state_lock); ++} ++ ++ ++int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring, u32 size) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int err; ++ int tmp; ++ ++ /* Sanity check SRQ size before proceeding */ ++ if (size >= mdev->dev->caps.max_srq_wqes) ++ return -EINVAL; ++ ++ ring->prod = 0; ++ ring->cons = 0; ++ ring->size = size; ++ ring->size_mask = size - 1; ++ ring->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + ++ DS_SIZE * (ring->use_frags ? ++ MLX4_EN_MAX_RX_FRAGS : 1)); ++ ring->log_stride = ffs(ring->stride) - 1; ++ ring->buf_size = ring->size * ring->stride; ++ ++ if (ring->use_frags) ++ tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * ++ sizeof(struct skb_frag_struct)); ++ else ++ tmp = size * sizeof(struct sk_buff *); ++ ++ ring->rx_info = vmalloc(tmp); ++ if (!ring->rx_info) { ++ mlx4_err(mdev, "Failed allocating rx_info ring\n"); ++ return -ENOMEM; ++ } ++ mlx4_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", ++ ring->rx_info, tmp); ++ ++ err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ++ ring->buf_size, 2 * PAGE_SIZE); ++ if (err) ++ goto err_ring; ++ ++ err = mlx4_en_map_buffer(&ring->wqres.buf); ++ if (err) { ++ mlx4_err(mdev, "Failed to map RX buffer\n"); ++ goto err_hwq; ++ } ++ ring->buf = ring->wqres.buf.direct.buf; ++ ++ /* Allocate LRO sessions */ ++ if (mdev->profile.num_lro && mlx4_en_lro_init(ring, mdev->profile.num_lro)) { ++ mlx4_err(mdev, "Failed allocating lro sessions\n"); ++ goto err_map; ++ } ++ ++ return 0; ++ ++err_map: ++ mlx4_en_unmap_buffer(&ring->wqres.buf); ++err_hwq: ++ mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); ++err_ring: ++ vfree(ring->rx_info); ++ ring->rx_info = NULL; ++ return err; ++} ++ ++int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_wqe_srq_next_seg *next; ++ struct mlx4_en_rx_ring *ring; ++ int i; ++ int ring_ind; ++ int err; ++ int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + ++ DS_SIZE * priv->num_frags); ++ int max_gs = (stride - sizeof(struct mlx4_wqe_srq_next_seg)) / DS_SIZE; ++ ++ for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { ++ ring = &priv->rx_ring[ring_ind]; ++ ++ ring->prod = 0; ++ ring->cons = 0; ++ ring->actual_size = 0; ++ ring->cqn = priv->rx_cq[ring_ind].mcq.cqn; ++ ++ if (ring->use_frags) ++ ring->stride = stride; ++ ring->log_stride = ffs(ring->stride) - 1; ++ ring->buf_size = ring->size * ring->stride; ++ ++ memset(ring->rx_info, 0, sizeof(*(ring->rx_info))); ++ memset(ring->buf, 0, ring->buf_size); ++ mlx4_en_update_rx_prod_db(ring); ++ ++ if (ring->use_frags) { ++ /* Initailize all descriptors */ ++ for (i = 0; i < ring->size; i++) ++ mlx4_en_init_rx_desc(priv, ring, i); ++ ++ /* Initialize page allocators */ ++ err = mlx4_en_init_allocator(priv, ring); ++ if (err) { ++ mlx4_err(mdev, "Failed initializing ring allocator\n"); ++ ring_ind--; ++ goto err_allocator; ++ } ++ } else { ++ for (i = 0; i < ring->size; i++) ++ mlx4_en_init_rx_desc_skb(priv, ring, i); ++ } ++ ++ /* Fill Rx buffers */ ++ ring->full = 0; ++ } ++ err = mlx4_en_fill_rx_buffers(priv); ++ if (err) ++ goto err_buffers; ++ ++ for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { ++ ring = &priv->rx_ring[ring_ind]; ++ ++ mlx4_en_update_rx_prod_db(ring); ++ ++ /* Configure SRQ representing the ring */ ++ ring->srq.max = ring->size; ++ ring->srq.max_gs = max_gs; ++ ring->srq.wqe_shift = ilog2(ring->stride); ++ ++ for (i = 0; i < ring->srq.max; ++i) { ++ next = get_wqe(ring, i); ++ next->next_wqe_index = ++ cpu_to_be16((i + 1) & (ring->srq.max - 1)); ++ } ++ ++ err = mlx4_srq_alloc(mdev->dev, mdev->priv_pdn, ring->cqn, 0, ++ &ring->wqres.mtt, ring->wqres.db.dma, &ring->srq); ++ if (err){ ++ mlx4_err(mdev, "Failed to allocate srq\n"); ++ ring_ind--; ++ goto err_srq; ++ } ++ ring->srq.event = mlx4_en_srq_event; ++ } ++ ++ return 0; ++ ++err_srq: ++ while (ring_ind >= 0) { ++ ring = &priv->rx_ring[ring_ind]; ++ mlx4_srq_invalidate(mdev->dev, &ring->srq); ++ mlx4_srq_remove(mdev->dev, &ring->srq); ++ mlx4_srq_free(mdev->dev, &ring->srq); ++ ring_ind--; ++ } ++ ++err_buffers: ++ for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) ++ mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]); ++ ++ ring_ind = priv->rx_ring_num - 1; ++err_allocator: ++ while (ring_ind >= 0) { ++ if (priv->rx_ring[ring_ind].use_frags) ++ mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]); ++ ring_ind--; ++ } ++ return err; ++} ++ ++void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ ++ if (mdev->profile.num_lro) ++ mlx4_en_lro_destroy(ring); ++ mlx4_en_unmap_buffer(&ring->wqres.buf); ++ mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); ++ vfree(ring->rx_info); ++ ring->rx_info = NULL; ++} ++ ++void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ ++ mlx4_srq_invalidate(mdev->dev, &ring->srq); ++ mlx4_srq_remove(mdev->dev, &ring->srq); ++ mlx4_srq_free(mdev->dev, &ring->srq); ++ mlx4_en_free_rx_buf(priv, ring); ++ if (ring->use_frags) ++ mlx4_en_destroy_allocator(priv, ring); ++} ++ ++ ++/* Unmap a completed descriptor and free unused pages */ ++int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_desc *rx_desc, ++ struct skb_frag_struct *skb_frags, ++ struct skb_frag_struct *skb_frags_rx, ++ struct mlx4_en_rx_alloc *page_alloc, ++ int length) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_en_frag_info *frag_info; ++ int nr; ++ dma_addr_t dma; ++ ++ /* Collect used fragments while replacing them in the HW descirptors */ ++ for (nr = 0; nr < priv->num_frags; nr++) { ++ frag_info = &priv->frag_info[nr]; ++ if (length <= frag_info->frag_prefix_size) ++ break; ++ ++ /* Save page reference in skb */ ++ skb_frags_rx[nr].page = skb_frags[nr].page; ++ skb_frags_rx[nr].size = skb_frags[nr].size; ++ skb_frags_rx[nr].page_offset = skb_frags[nr].page_offset; ++ dma = be64_to_cpu(rx_desc->data[nr].addr); ++ ++ /* Allocate a replacement page */ ++ if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr)) ++ goto fail; ++ ++ /* Unmap buffer */ ++ pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size, ++ PCI_DMA_FROMDEVICE); ++ } ++ /* Adjust size of last fragment to match actual length */ ++ skb_frags_rx[nr - 1].size = length - ++ priv->frag_info[nr - 1].frag_prefix_size; ++ return nr; ++ ++fail: ++ /* Drop all accumulated fragments (which have already been replaced in ++ * the descriptor) of this packet; remaining fragments are reused... */ ++ while (nr > 0) { ++ nr--; ++ put_page(skb_frags_rx[nr].page); ++ } ++ return 0; ++} ++ ++ ++struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_desc *rx_desc, ++ struct skb_frag_struct *skb_frags, ++ struct mlx4_en_rx_alloc *page_alloc, ++ unsigned int length) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct sk_buff *skb; ++ void *va; ++ int used_frags; ++ dma_addr_t dma; ++ ++ skb = dev_alloc_skb(SMALL_PACKET_SIZE + NET_IP_ALIGN); ++ if (!skb) { ++ mlx4_dbg(RX_ERR, priv, "Failed allocating skb\n"); ++ return NULL; ++ } ++ skb->dev = priv->dev; ++ skb_reserve(skb, NET_IP_ALIGN); ++ skb->len = length; ++ skb->truesize = length + sizeof(struct sk_buff); ++ ++ /* Get pointer to first fragment so we could copy the headers into the ++ * (linear part of the) skb */ ++ va = page_address(skb_frags[0].page) + skb_frags[0].page_offset; ++ ++ if (length <= SMALL_PACKET_SIZE) { ++ /* We are copying all relevant data to the skb - temporarily ++ * synch buffers for the copy */ ++ dma = be64_to_cpu(rx_desc->data[0].addr); ++ dma_sync_single_range_for_cpu(&mdev->pdev->dev, dma, 0, ++ length, DMA_FROM_DEVICE); ++ skb_copy_to_linear_data(skb, va, length); ++ dma_sync_single_range_for_device(&mdev->pdev->dev, dma, 0, ++ length, DMA_FROM_DEVICE); ++ skb->tail += length; ++ } else { ++ ++ /* Move relevant fragments to skb */ ++ used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags, ++ skb_shinfo(skb)->frags, ++ page_alloc, length); ++ if (unlikely(!used_frags)) { ++ kfree_skb(skb); ++ return NULL; ++ } ++ skb_shinfo(skb)->nr_frags = used_frags; ++ ++ /* Copy headers into the skb linear buffer */ ++ memcpy(skb->data, va, HEADER_COPY_SIZE); ++ skb->tail += HEADER_COPY_SIZE; ++ ++ /* Skip headers in first fragment */ ++ skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE; ++ ++ /* Adjust size of first fragment */ ++ skb_shinfo(skb)->frags[0].size -= HEADER_COPY_SIZE; ++ skb->data_len = length - HEADER_COPY_SIZE; ++ } ++ return skb; ++} ++ ++static void mlx4_en_copy_desc(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring, ++ int from, int to, int num) ++{ ++ struct skb_frag_struct *skb_frags_from; ++ struct skb_frag_struct *skb_frags_to; ++ struct mlx4_en_rx_desc *rx_desc_from; ++ struct mlx4_en_rx_desc *rx_desc_to; ++ int from_index, to_index; ++ int nr, i; ++ ++ for (i = 0; i < num; i++) { ++ from_index = (from + i) & ring->size_mask; ++ to_index = (to + i) & ring->size_mask; ++ skb_frags_from = ring->rx_info + (from_index << priv->log_rx_info); ++ skb_frags_to = ring->rx_info + (to_index << priv->log_rx_info); ++ rx_desc_from = ring->buf + (from_index << ring->log_stride); ++ rx_desc_to = ring->buf + (to_index << ring->log_stride); ++ ++ for (nr = 0; nr < priv->num_frags; nr++) { ++ skb_frags_to[nr].page = skb_frags_from[nr].page; ++ skb_frags_to[nr].page_offset = skb_frags_from[nr].page_offset; ++ rx_desc_to->data[nr].addr = rx_desc_from->data[nr].addr; ++ } ++ } ++} ++ ++static inline int invalid_cqe(struct mlx4_en_priv *priv, ++ struct mlx4_cqe *cqe) ++{ ++ /* Drop packet on bad receive or bad checksum */ ++ if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == ++ MLX4_CQE_OPCODE_ERROR)) { ++ mlx4_err(priv->mdev, "CQE completed in error - vendor " ++ "syndrom:%d syndrom:%d\n", ++ ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome, ++ ((struct mlx4_err_cqe *) cqe)->syndrome); ++ return 1; ++ } ++ if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { ++ mlx4_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); ++ return 1;; ++ } ++ ++ return 0; ++} ++ ++static struct sk_buff * ++mlx4_en_get_rx_skb(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_desc *rx_desc, ++ struct sk_buff **pskb, ++ unsigned int length) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct sk_buff *skb; ++ dma_addr_t dma; ++ ++ if (length <= MLX4_EN_SMALL_PKT_SIZE) { ++ skb = dev_alloc_skb(length + NET_IP_ALIGN); ++ if (unlikely(!skb)) ++ return NULL; ++ ++ skb_reserve(skb, NET_IP_ALIGN); ++ /* We are copying all relevant data to the skb - temporarily ++ * synch buffers for the copy */ ++ dma = be64_to_cpu(rx_desc->data->addr); ++ dma_sync_single_range_for_cpu(&mdev->pdev->dev, dma, 0, ++ length, DMA_FROM_DEVICE); ++ skb_copy_to_linear_data(skb, (*pskb)->data, length); ++ dma_sync_single_range_for_device(&mdev->pdev->dev, dma, 0, ++ length, DMA_FROM_DEVICE); ++ ++ } else { ++ skb = *pskb; ++ if (unlikely(mlx4_en_alloc_rx_skb(priv, rx_desc, pskb))) ++ return NULL; ++ ++ pci_unmap_single(mdev->pdev, be64_to_cpu(rx_desc->data->addr), ++ be32_to_cpu(rx_desc->data->byte_count), ++ PCI_DMA_FROMDEVICE); ++ } ++ ++ skb->tail += length; ++ skb->len = length; ++ skb->truesize = length + sizeof(struct sk_buff); ++ return skb; ++} ++ ++int mlx4_en_process_rx_cq_skb(struct net_device *dev, ++ struct mlx4_en_cq *cq, int budget) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_cqe *cqe; ++ struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring]; ++ struct mlx4_en_rx_desc *rx_desc; ++ struct sk_buff **pskb; ++ struct sk_buff *skb; ++ int index; ++ unsigned int length; ++ int polled = 0; ++ ++ if (!priv->port_up) ++ return 0; ++ ++ /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx ++ * descriptor offset can be deduced from the CQE index instead of ++ * reading 'cqe->index' */ ++ index = cq->mcq.cons_index & ring->size_mask; ++ cqe = &cq->buf[index]; ++ ++ /* Process all completed CQEs */ ++ while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, ++ cq->mcq.cons_index & cq->size)) { ++ ++ pskb = (struct sk_buff **) ring->rx_info + index; ++ rx_desc = ring->buf + (index << ring->log_stride); ++ ++ /* ++ * make sure we read the CQE after we read the ownership bit ++ */ ++ rmb(); ++ ++ if (invalid_cqe(priv, cqe)) ++ goto next; ++ ++ /* ++ * Packet is OK - process it. ++ */ ++ length = be32_to_cpu(cqe->byte_cnt); ++ ring->bytes += length; ++ ring->packets++; ++ ++ skb = mlx4_en_get_rx_skb(priv, rx_desc, pskb, length); ++ if (unlikely(!skb)) ++ goto next; ++ skb->protocol = eth_type_trans(skb, dev); ++ ++ if (likely(priv->rx_csum && cqe->checksum == 0xffff)) { ++ priv->port_stats.rx_chksum_good++; ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } else { ++ priv->port_stats.rx_chksum_none++; ++ skb->ip_summed = CHECKSUM_NONE; ++ if (mdev->profile.ip_reasm && ++ cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4) && ++ !mlx4_en_rx_frags(priv, ring, skb, cqe)) ++ goto next; ++ } ++ ++ /* Push it up the stack */ ++ if (priv->vlgrp && (be32_to_cpu(cqe->vlan_my_qpn) & ++ MLX4_CQE_VLAN_PRESENT_MASK)) { ++ vlan_hwaccel_receive_skb(skb, priv->vlgrp, ++ be16_to_cpu(cqe->sl_vid)); ++ } else ++ netif_receive_skb(skb); ++ ++ dev->last_rx = jiffies; ++ ++next: ++ ++cq->mcq.cons_index; ++ index = (cq->mcq.cons_index) & ring->size_mask; ++ cqe = &cq->buf[index]; ++ if (++polled == budget) ++ goto out; ++ } ++ ++ /* If CQ is empty, flush all pending IP reassembly sessions */ ++ mlx4_en_flush_frags(priv, ring); ++ ++out: ++ AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); ++ mlx4_cq_set_ci(&cq->mcq); ++ wmb(); /* ensure HW sees CQ consumer before we post new buffers */ ++ ring->cons = cq->mcq.cons_index; ++ ring->prod += polled; /* Polled descriptors were realocated in place */ ++ if (unlikely(!ring->full)) ++ mlx4_en_fill_rx_buf(dev, ring); ++ mlx4_en_update_rx_prod_db(ring); ++ return polled; ++} ++ ++int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_cqe *cqe; ++ struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring]; ++ struct skb_frag_struct *skb_frags; ++ struct mlx4_en_rx_desc *rx_desc; ++ struct sk_buff *skb; ++ int index; ++ unsigned int length; ++ int polled = 0; ++ int ip_summed; ++ ++ if (!priv->port_up) ++ return 0; ++ ++ /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx ++ * descriptor offset can be deduced from the CQE index instead of ++ * reading 'cqe->index' */ ++ index = cq->mcq.cons_index & ring->size_mask; ++ cqe = &cq->buf[index]; ++ ++ /* Process all completed CQEs */ ++ while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, ++ cq->mcq.cons_index & cq->size)) { ++ ++ skb_frags = ring->rx_info + (index << priv->log_rx_info); ++ rx_desc = ring->buf + (index << ring->log_stride); ++ ++ /* ++ * make sure we read the CQE after we read the ownership bit ++ */ ++ rmb(); ++ ++ if (invalid_cqe(priv, cqe)) ++ goto next; ++ ++ /* ++ * Packet is OK - process it. ++ */ ++ length = be32_to_cpu(cqe->byte_cnt); ++ ring->bytes += length; ++ ring->packets++; ++ ++ if (likely(priv->rx_csum)) { ++ if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && ++ (cqe->checksum == 0xffff)) { ++ priv->port_stats.rx_chksum_good++; ++ if (mdev->profile.num_lro && ++ !mlx4_en_lro_rx(priv, ring, rx_desc, ++ skb_frags, length, cqe)) ++ goto next; ++ ++ /* LRO not possible, complete processing here */ ++ ip_summed = CHECKSUM_UNNECESSARY; ++ INC_PERF_COUNTER(priv->pstats.lro_misses); ++ } else { ++ ip_summed = CHECKSUM_NONE; ++ priv->port_stats.rx_chksum_none++; ++ } ++ } else { ++ ip_summed = CHECKSUM_NONE; ++ priv->port_stats.rx_chksum_none++; ++ } ++ ++ skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags, ++ ring->page_alloc, length); ++ if (!skb) { ++ priv->stats.rx_dropped++; ++ goto next; ++ } ++ ++ skb->ip_summed = ip_summed; ++ skb->protocol = eth_type_trans(skb, dev); ++ ++ /* Push it up the stack */ ++ if (priv->vlgrp && (be32_to_cpu(cqe->vlan_my_qpn) & ++ MLX4_CQE_VLAN_PRESENT_MASK)) { ++ vlan_hwaccel_receive_skb(skb, priv->vlgrp, ++ be16_to_cpu(cqe->sl_vid)); ++ } else ++ netif_receive_skb(skb); ++ ++ dev->last_rx = jiffies; ++ ++next: ++ ++cq->mcq.cons_index; ++ index = (cq->mcq.cons_index) & ring->size_mask; ++ cqe = &cq->buf[index]; ++ if (++polled == budget) { ++ /* We are here because we reached the NAPI budget - ++ * flush only pending LRO sessions */ ++ if (mdev->profile.num_lro) ++ mlx4_en_lro_flush(priv, ring, 0); ++ goto out; ++ } ++ } ++ ++ /* If CQ is empty flush all LRO sessions unconditionally */ ++ if (mdev->profile.num_lro) ++ mlx4_en_lro_flush(priv, ring, 1); ++ ++out: ++ AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); ++ mlx4_cq_set_ci(&cq->mcq); ++ wmb(); /* ensure HW sees CQ consumer before we post new buffers */ ++ ring->cons = cq->mcq.cons_index; ++ ring->prod += polled; /* Polled descriptors were realocated in place */ ++ if (unlikely(!ring->full)) { ++ mlx4_en_copy_desc(priv, ring, ring->cons - polled, ++ ring->prod - polled, polled); ++ mlx4_en_fill_rx_buf(dev, ring); ++ } ++ mlx4_en_update_rx_prod_db(ring); ++ return polled; ++} ++ ++ ++void mlx4_en_rx_irq(struct mlx4_cq *mcq) ++{ ++ struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); ++ struct mlx4_en_priv *priv = netdev_priv(cq->dev); ++ ++ if (priv->port_up) ++ netif_rx_schedule(cq->dev, &cq->napi); ++ else ++ mlx4_en_arm_cq(priv, cq); ++} ++ ++/* Rx CQ polling - called by NAPI */ ++int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) ++{ ++ struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); ++ struct net_device *dev = cq->dev; ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ int done; ++ ++ done = cq->process_cq(dev, cq, budget); ++ ++ /* If we used up all the quota - we're probably not done yet... */ ++ if (done == budget) ++ INC_PERF_COUNTER(priv->pstats.napi_quota); ++ else { ++ /* Done for now */ ++ netif_rx_complete(dev, napi); ++ mlx4_en_arm_cq(priv, cq); ++ } ++ return done; ++} ++ ++ ++/* Calculate the last offset position that accomodates a full fragment ++ * (assuming fagment size = stride-align) */ ++static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align) ++{ ++ u16 res = MLX4_EN_ALLOC_SIZE % stride; ++ u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align; ++ ++ mlx4_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d " ++ "res:%d offset:%d\n", stride, align, res, offset); ++ return offset; ++} ++ ++ ++static int frag_sizes[] = { ++ FRAG_SZ0, ++ FRAG_SZ1, ++ FRAG_SZ2, ++ FRAG_SZ3 ++}; ++ ++void mlx4_en_calc_rx_buf(struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE; ++ int buf_size = 0; ++ int i = 0; ++ ++ while (buf_size < eff_mtu) { ++ priv->frag_info[i].frag_size = ++ (eff_mtu > buf_size + frag_sizes[i]) ? ++ frag_sizes[i] : eff_mtu - buf_size; ++ priv->frag_info[i].frag_prefix_size = buf_size; ++ if (!i) { ++ priv->frag_info[i].frag_align = NET_IP_ALIGN; ++ priv->frag_info[i].frag_stride = ++ ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES); ++ } else { ++ priv->frag_info[i].frag_align = 0; ++ priv->frag_info[i].frag_stride = ++ ALIGN(frag_sizes[i], SMP_CACHE_BYTES); ++ } ++ priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset( ++ priv, priv->frag_info[i].frag_stride, ++ priv->frag_info[i].frag_align); ++ buf_size += priv->frag_info[i].frag_size; ++ i++; ++ } ++ ++ priv->num_frags = i; ++ priv->rx_skb_size = eff_mtu; ++ priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct)); ++ ++ mlx4_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d " ++ "num_frags:%d):\n", eff_mtu, priv->num_frags); ++ for (i = 0; i < priv->num_frags; i++) { ++ mlx4_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d " ++ "stride:%d last_offset:%d\n", i, ++ priv->frag_info[i].frag_size, ++ priv->frag_info[i].frag_prefix_size, ++ priv->frag_info[i].frag_align, ++ priv->frag_info[i].frag_stride, ++ priv->frag_info[i].last_offset); ++ } ++} ++ ++/* RSS related functions */ ++ ++/* Calculate rss size and map each entry in rss table to rx ring */ ++void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv, ++ struct mlx4_en_rss_map *rss_map, ++ int num_entries, int num_rings) ++{ ++ int i; ++ ++ rss_map->size = roundup_pow_of_two(num_entries); ++ mlx4_dbg(DRV, priv, "Setting default RSS map of %d entires\n", ++ rss_map->size); ++ ++ for (i = 0; i < rss_map->size; i++) { ++ rss_map->map[i] = i % num_rings; ++ mlx4_dbg(DRV, priv, "Entry %d ---> ring %d\n", i, rss_map->map[i]); ++ } ++} ++ ++static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, ++ int qpn, int srqn, int cqn, ++ enum mlx4_qp_state *state, ++ struct mlx4_qp *qp) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_qp_context *context; ++ int err = 0; ++ ++ context = kmalloc(sizeof *context , GFP_KERNEL); ++ if (!context) { ++ mlx4_err(mdev, "Failed to allocate qp context\n"); ++ return -ENOMEM; ++ } ++ ++ err = mlx4_qp_alloc(mdev->dev, qpn, qp); ++ if (err) { ++ mlx4_err(mdev, "Failed to allocate qp #%d\n", qpn); ++ goto out; ++ return err; ++ } ++ qp->event = mlx4_en_sqp_event; ++ ++ memset(context, 0, sizeof *context); ++ mlx4_en_fill_qp_context(priv, 0, 0, 0, 0, qpn, cqn, srqn, context); ++ ++ err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, context, qp, state); ++ if (err) { ++ mlx4_qp_remove(mdev->dev, qp); ++ mlx4_qp_free(mdev->dev, qp); ++ } ++out: ++ kfree(context); ++ return err; ++} ++ ++/* Allocate rx qp's and configure them according to rss map */ ++int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_en_rss_map *rss_map = &priv->rss_map; ++ struct mlx4_qp_context context; ++ struct mlx4_en_rss_context *rss_context; ++ void *ptr; ++ int rss_xor = mdev->profile.rss_xor; ++ u8 rss_mask = mdev->profile.rss_mask; ++ int i, srqn, qpn, cqn; ++ int err = 0; ++ int good_qps = 0; ++ ++ mlx4_dbg(DRV, priv, "Configuring rss steering for port %u\n", priv->port); ++ err = mlx4_qp_reserve_range(mdev->dev, rss_map->size, ++ rss_map->size, &rss_map->base_qpn); ++ if (err) { ++ mlx4_err(mdev, "Failed reserving %d qps for port %u\n", ++ rss_map->size, priv->port); ++ return err; ++ } ++ ++ for (i = 0; i < rss_map->size; i++) { ++ cqn = priv->rx_ring[rss_map->map[i]].cqn; ++ srqn = priv->rx_ring[rss_map->map[i]].srq.srqn; ++ qpn = rss_map->base_qpn + i; ++ err = mlx4_en_config_rss_qp(priv, qpn, srqn, cqn, ++ &rss_map->state[i], ++ &rss_map->qps[i]); ++ if (err) ++ goto rss_err; ++ ++ ++good_qps; ++ } ++ ++ /* Configure RSS indirection qp */ ++ err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &priv->base_qpn); ++ if (err) { ++ mlx4_err(mdev, "Failed to reserve range for RSS " ++ "indirection qp\n"); ++ goto rss_err; ++ } ++ err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp); ++ if (err) { ++ mlx4_err(mdev, "Failed to allocate RSS indirection QP\n"); ++ goto reserve_err; ++ } ++ rss_map->indir_qp.event = mlx4_en_sqp_event; ++ mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, ++ priv->rx_ring[0].cqn, 0, &context); ++ ++ ptr = ((void *) &context) + 0x3c; ++ rss_context = (struct mlx4_en_rss_context *) ptr; ++ rss_context->base_qpn = cpu_to_be32(ilog2(rss_map->size - 1) << 24 | ++ (rss_map->base_qpn + 1)); ++ rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); ++ rss_context->hash_fn = rss_xor & 0x3; ++ rss_context->flags = rss_mask << 2; ++ ++ err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, ++ &rss_map->indir_qp, &rss_map->indir_state); ++ if (err) ++ goto indir_err; ++ ++ return 0; ++ ++indir_err: ++ mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, ++ MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); ++ mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); ++ mlx4_qp_free(mdev->dev, &rss_map->indir_qp); ++reserve_err: ++ mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1); ++rss_err: ++ for (i = 0; i < good_qps; i++) { ++ mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], ++ MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); ++ mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); ++ mlx4_qp_free(mdev->dev, &rss_map->qps[i]); ++ } ++ mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size); ++ return err; ++} ++ ++void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_en_rss_map *rss_map = &priv->rss_map; ++ int i; ++ ++ mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, ++ MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); ++ mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); ++ mlx4_qp_free(mdev->dev, &rss_map->indir_qp); ++ mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1); ++ ++ for (i = 0; i < rss_map->size; i++) { ++ mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], ++ MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); ++ mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); ++ mlx4_qp_free(mdev->dev, &rss_map->qps[i]); ++ } ++ mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size); ++} ++ ++ ++ ++ ++ +diff -r 4e706462aff6 drivers/net/mlx4/en_tx.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/en_tx.c Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,868 @@ ++/* ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mlx4_en.h" ++ ++enum { ++ MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ ++}; ++ ++static int inline_thold __read_mostly = MAX_INLINE; ++ ++module_param_named(inline_thold, inline_thold, int, 0444); ++MODULE_PARM_DESC(inline_thold, "treshold for using inline data"); ++ ++int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, ++ struct mlx4_en_tx_ring *ring, u32 size, ++ u16 stride) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int tmp; ++ int err; ++ ++ ring->size = size; ++ ring->size_mask = size - 1; ++ ring->stride = stride; ++ ++ inline_thold = min(inline_thold, MAX_INLINE); ++ ++ spin_lock_init(&ring->comp_lock); ++ ++ tmp = size * sizeof(struct mlx4_en_tx_info); ++ ring->tx_info = vmalloc(tmp); ++ if (!ring->tx_info) { ++ mlx4_err(mdev, "Failed allocating tx_info ring\n"); ++ return -ENOMEM; ++ } ++ mlx4_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", ++ ring->tx_info, tmp); ++ ++ ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); ++ if (!ring->bounce_buf) { ++ mlx4_err(mdev, "Failed allocating bounce buffer\n"); ++ err = -ENOMEM; ++ goto err_tx; ++ } ++ ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); ++ ++ err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, ++ 2 * PAGE_SIZE); ++ if (err) { ++ mlx4_err(mdev, "Failed allocating hwq resources\n"); ++ goto err_bounce; ++ } ++ ++ err = mlx4_en_map_buffer(&ring->wqres.buf); ++ if (err) { ++ mlx4_err(mdev, "Failed to map TX buffer\n"); ++ goto err_hwq_res; ++ } ++ ++ ring->buf = ring->wqres.buf.direct.buf; ++ ++ mlx4_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d " ++ "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size, ++ ring->buf_size, ring->wqres.buf.direct.map); ++ ++ err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn); ++ if (err) { ++ mlx4_err(mdev, "Failed reserving qp for tx ring.\n"); ++ goto err_map; ++ } ++ ++ err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp); ++ if (err) { ++ mlx4_err(mdev, "Failed allocating qp %d\n", ring->qpn); ++ goto err_reserve; ++ } ++ ring->qp.event = mlx4_en_sqp_event; ++ ++ return 0; ++ ++err_reserve: ++ mlx4_qp_release_range(mdev->dev, ring->qpn, 1); ++err_map: ++ mlx4_en_unmap_buffer(&ring->wqres.buf); ++err_hwq_res: ++ mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); ++err_bounce: ++ kfree(ring->bounce_buf); ++ ring->bounce_buf = NULL; ++err_tx: ++ vfree(ring->tx_info); ++ ring->tx_info = NULL; ++ return err; ++} ++ ++void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, ++ struct mlx4_en_tx_ring *ring) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ mlx4_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); ++ ++ mlx4_qp_remove(mdev->dev, &ring->qp); ++ mlx4_qp_free(mdev->dev, &ring->qp); ++ mlx4_qp_release_range(mdev->dev, ring->qpn, 1); ++ mlx4_en_unmap_buffer(&ring->wqres.buf); ++ mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); ++ kfree(ring->bounce_buf); ++ ring->bounce_buf = NULL; ++ vfree(ring->tx_info); ++ ring->tx_info = NULL; ++} ++ ++int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, ++ struct mlx4_en_tx_ring *ring, ++ int cq, int srqn) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int err; ++ ++ ring->cqn = cq; ++ ring->prod = 0; ++ ring->cons = 0xffffffff; ++ ring->last_nr_txbb = 1; ++ ring->poll_cnt = 0; ++ ring->blocked = 0; ++ memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); ++ memset(ring->buf, 0, ring->buf_size); ++ ++ ring->qp_state = MLX4_QP_STATE_RST; ++ ring->doorbell_qpn = swab32(ring->qp.qpn << 8); ++ ++ mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, ++ ring->cqn, srqn, &ring->context); ++ ++ err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, ++ &ring->qp, &ring->qp_state); ++ ++ return err; ++} ++ ++void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, ++ struct mlx4_en_tx_ring *ring) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ ++ mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, ++ MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); ++} ++ ++ ++static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, ++ struct mlx4_en_tx_ring *ring, ++ int index, u8 owner) ++{ ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; ++ struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; ++ struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; ++ struct sk_buff *skb = tx_info->skb; ++ struct skb_frag_struct *frag; ++ void *end = ring->buf + ring->buf_size; ++ int frags = skb_shinfo(skb)->nr_frags; ++ int i; ++ __be32 *ptr = (__be32 *)tx_desc; ++ __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); ++ ++ /* Optimize the common case when there are no wraparounds */ ++ if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { ++ if (!tx_info->inl) { ++ if (tx_info->linear) { ++ pci_unmap_single(mdev->pdev, ++ (dma_addr_t) be64_to_cpu(data->addr), ++ be32_to_cpu(data->byte_count), ++ PCI_DMA_TODEVICE); ++ ++data; ++ } ++ ++ for (i = 0; i < frags; i++) { ++ frag = &skb_shinfo(skb)->frags[i]; ++ pci_unmap_page(mdev->pdev, ++ (dma_addr_t) be64_to_cpu(data[i].addr), ++ frag->size, PCI_DMA_TODEVICE); ++ } ++ } ++ /* Stamp the freed descriptor */ ++ for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) { ++ *ptr = stamp; ++ ptr += STAMP_DWORDS; ++ } ++ ++ } else { ++ if (!tx_info->inl) { ++ if ((void *) data >= end) { ++ data = (struct mlx4_wqe_data_seg *) ++ (ring->buf + ((void *) data - end)); ++ } ++ ++ if (tx_info->linear) { ++ pci_unmap_single(mdev->pdev, ++ (dma_addr_t) be64_to_cpu(data->addr), ++ be32_to_cpu(data->byte_count), ++ PCI_DMA_TODEVICE); ++ ++data; ++ } ++ ++ for (i = 0; i < frags; i++) { ++ /* Check for wraparound before unmapping */ ++ if ((void *) data >= end) ++ data = (struct mlx4_wqe_data_seg *) ring->buf; ++ frag = &skb_shinfo(skb)->frags[i]; ++ pci_unmap_page(mdev->pdev, ++ (dma_addr_t) be64_to_cpu(data->addr), ++ frag->size, PCI_DMA_TODEVICE); ++ } ++ } ++ /* Stamp the freed descriptor */ ++ for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) { ++ *ptr = stamp; ++ ptr += STAMP_DWORDS; ++ if ((void *) ptr >= end) { ++ ptr = ring->buf; ++ stamp ^= cpu_to_be32(0x80000000); ++ } ++ } ++ ++ } ++ dev_kfree_skb_any(skb); ++ return tx_info->nr_txbb; ++} ++ ++ ++int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ int cnt = 0; ++ ++ /* Skip last polled descriptor */ ++ ring->cons += ring->last_nr_txbb; ++ mlx4_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", ++ ring->cons, ring->prod); ++ ++ if ((u32) (ring->prod - ring->cons) > ring->size) { ++ if (netif_msg_tx_err(priv)) ++ mlx4_warn(priv->mdev, "Tx consumer passed producer!\n"); ++ return 0; ++ } ++ ++ while (ring->cons != ring->prod) { ++ ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, ++ ring->cons & ring->size_mask, ++ !!(ring->cons & ring->size)); ++ ring->cons += ring->last_nr_txbb; ++ cnt++; ++ } ++ ++ if (cnt) ++ mlx4_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); ++ ++ return cnt; ++} ++ ++void mlx4_en_set_prio_map(struct mlx4_en_priv *priv, u16 *prio_map, u32 ring_num) ++{ ++ int block = 8 / ring_num; ++ int extra = 8 - (block * ring_num); ++ int num = 0; ++ u16 ring = MLX4_EN_NUM_HASH_RINGS + 1; ++ int prio; ++ ++ if (ring_num == 1) { ++ for (prio = 0; prio < 8; prio++) ++ prio_map[prio] = 0; ++ return; ++ } ++ ++ for (prio = 0; prio < 8; prio++) { ++ if (extra && (num == block + 1)) { ++ ring++; ++ num = 0; ++ extra--; ++ } else if (!extra && (num == block)) { ++ ring++; ++ num = 0; ++ } ++ prio_map[prio] = ring; ++ mlx4_dbg(DRV, priv, " prio:%d --> ring:%d\n", prio, ring); ++ num++; ++ } ++} ++ ++void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_cq *mcq = &cq->mcq; ++ struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; ++ struct mlx4_cqe *cqe = cq->buf; ++ u16 index; ++ u16 new_index; ++ u32 txbbs_skipped = 0; ++ u32 cq_last_sav; ++ ++ /* index always points to the first TXBB of the last polled descriptor */ ++ index = ring->cons & ring->size_mask; ++ new_index = be16_to_cpu(cqe->wqe_index) & ring->size_mask; ++ if (index == new_index) ++ return; ++ ++ if (!priv->port_up) ++ return; ++ ++ /* ++ * We use a two-stage loop: ++ * - the first samples the HW-updated CQE ++ * - the second frees TXBBs until the last sample ++ * This lets us amortize CQE cache misses, while still polling the CQ ++ * until is quiescent. ++ */ ++ cq_last_sav = mcq->cons_index; ++ do { ++ do { ++ /* Skip over last polled CQE */ ++ index = (index + ring->last_nr_txbb) & ring->size_mask; ++ txbbs_skipped += ring->last_nr_txbb; ++ ++ /* Poll next CQE */ ++ ring->last_nr_txbb = mlx4_en_free_tx_desc( ++ priv, ring, index, ++ !!((ring->cons + txbbs_skipped) & ++ ring->size)); ++ ++mcq->cons_index; ++ ++ } while (index != new_index); ++ ++ new_index = be16_to_cpu(cqe->wqe_index) & ring->size_mask; ++ } while (index != new_index); ++ AVG_PERF_COUNTER(priv->pstats.tx_coal_avg, ++ (u32) (mcq->cons_index - cq_last_sav)); ++ ++ /* ++ * To prevent CQ overflow we first update CQ consumer and only then ++ * the ring consumer. ++ */ ++ mlx4_cq_set_ci(mcq); ++ wmb(); ++ ring->cons += txbbs_skipped; ++ ++ /* Wakeup Tx queue if this ring stopped it */ ++ if (unlikely(ring->blocked)) { ++ if ((u32) (ring->prod - ring->cons) <= ++ ring->size - HEADROOM - MAX_DESC_TXBBS) { ++ ++ /* TODO: support multiqueue netdevs. Currently, we block ++ * when *any* ring is full. Note that: ++ * - 2 Tx rings can unblock at the same time and call ++ * netif_wake_queue(), which is OK since this ++ * operation is idempotent. ++ * - We might wake the queue just after another ring ++ * stopped it. This is no big deal because the next ++ * transmission on that ring would stop the queue. ++ */ ++ ring->blocked = 0; ++ netif_tx_wake_queue(netdev_get_tx_queue(dev, cq->ring)); ++ priv->port_stats.wake_queue++; ++ } ++ } ++} ++ ++void mlx4_en_tx_irq(struct mlx4_cq *mcq) ++{ ++ struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); ++ struct mlx4_en_priv *priv = netdev_priv(cq->dev); ++ struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; ++ ++ if (!spin_trylock(&ring->comp_lock)) ++ return; ++ mlx4_en_process_tx_cq(cq->dev, cq); ++ mod_timer(&cq->timer, jiffies + 1); ++ spin_unlock(&ring->comp_lock); ++} ++ ++ ++void mlx4_en_poll_tx_cq(unsigned long data) ++{ ++ struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data; ++ struct mlx4_en_priv *priv = netdev_priv(cq->dev); ++ struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; ++ u32 inflight; ++ ++ INC_PERF_COUNTER(priv->pstats.tx_poll); ++ ++ if (!spin_trylock(&ring->comp_lock)){ ++ mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); ++ return; ++ } ++ mlx4_en_process_tx_cq(cq->dev, cq); ++ inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb); ++ ++ /* If there are still packets in flight and the timer has not already ++ * been scheduled by the Tx routine then schedule it here to guarantee ++ * completion processing of these packets */ ++ if (inflight && priv->port_up) ++ mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); ++ ++ spin_unlock(&ring->comp_lock); ++} ++ ++static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, ++ struct mlx4_en_tx_ring *ring, ++ u32 index, ++ unsigned int desc_size) ++{ ++ u32 copy = (ring->size - index) * TXBB_SIZE; ++ int i; ++ ++ for (i = desc_size - copy - 4; i >= 0; i -= 4) { ++ if ((i & (TXBB_SIZE - 1)) == 0) ++ wmb(); ++ ++ *((u32 *) (ring->buf + i)) = ++ *((u32 *) (ring->bounce_buf + copy + i)); ++ } ++ ++ for (i = copy - 4; i >= 4 ; i -= 4) { ++ if ((i & (TXBB_SIZE - 1)) == 0) ++ wmb(); ++ ++ *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = ++ *((u32 *) (ring->bounce_buf + i)); ++ } ++ ++ /* Return real descriptor location */ ++ return ring->buf + index * TXBB_SIZE; ++} ++ ++static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind) ++{ ++ struct mlx4_en_cq *cq = &priv->tx_cq[tx_ind]; ++ struct mlx4_en_tx_ring *ring = &priv->tx_ring[tx_ind]; ++ ++ /* If we don't have a pending timer, set one up to catch our recent ++ post in case the interface becomes idle */ ++ if (!timer_pending(&cq->timer)) ++ mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); ++ ++ /* Poll the CQ every mlx4_en_TX_MODER_POLL packets */ ++ if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0) ++ if (spin_trylock(&ring->comp_lock)) { ++ mlx4_en_process_tx_cq(priv->dev, cq); ++ spin_unlock(&ring->comp_lock); ++ } ++} ++ ++static void *get_frag_ptr(struct sk_buff *skb) ++{ ++ struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; ++ struct page *page = frag->page; ++ void *ptr; ++ ++ ptr = page_address(page); ++ if (unlikely(!ptr)) ++ return NULL; ++ ++ return ptr + frag->page_offset; ++} ++ ++static int is_inline(struct sk_buff *skb, void **pfrag) ++{ ++ void *ptr; ++ ++ if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) { ++ if (skb_shinfo(skb)->nr_frags == 1) { ++ ptr = get_frag_ptr(skb); ++ if (unlikely(!ptr)) ++ return 0; ++ ++ if (pfrag) ++ *pfrag = ptr; ++ ++ return 1; ++ } else if (unlikely(skb_shinfo(skb)->nr_frags)) ++ return 0; ++ else ++ return 1; ++ } ++ ++ return 0; ++} ++ ++int inline_size(struct sk_buff *skb) ++{ ++ if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) ++ <= MLX4_INLINE_ALIGN) ++ return ALIGN(skb->len + CTRL_SIZE + ++ sizeof(struct mlx4_wqe_inline_seg), 16); ++ else ++ return ALIGN(skb->len + CTRL_SIZE + 2 * ++ sizeof(struct mlx4_wqe_inline_seg), 16); ++} ++ ++static int get_real_size(struct sk_buff *skb, struct net_device *dev, ++ int *lso_header_size) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ int real_size; ++ ++ if (skb_is_gso(skb)) { ++ *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); ++ real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE + ++ ALIGN(*lso_header_size + 4, DS_SIZE); ++ if (unlikely(*lso_header_size != skb_headlen(skb))) { ++ /* We add a segment for the skb linear buffer only if ++ * it contains data */ ++ if (*lso_header_size < skb_headlen(skb)) ++ real_size += DS_SIZE; ++ else { ++ if (netif_msg_tx_err(priv)) ++ mlx4_warn(mdev, "Non-linear headers\n"); ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ } ++ if (unlikely(*lso_header_size > MAX_LSO_HDR_SIZE)) { ++ if (netif_msg_tx_err(priv)) ++ mlx4_warn(mdev, "LSO header size too big\n"); ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ } else { ++ *lso_header_size = 0; ++ if (!is_inline(skb, NULL)) ++ real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE; ++ else ++ real_size = inline_size(skb); ++ } ++ ++ return real_size; ++} ++ ++static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb, ++ int real_size, u16 *vlan_tag, int tx_ind, void *fragptr) ++{ ++ struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; ++ int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; ++ ++ if (skb->len <= spc) { ++ inl->byte_count = cpu_to_be32(1 << 31 | skb->len); ++ skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); ++ if (skb_shinfo(skb)->nr_frags) ++ memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr, ++ skb_shinfo(skb)->frags[0].size); ++ ++ } else { ++ inl->byte_count = cpu_to_be32(1 << 31 | spc); ++ if (skb_headlen(skb) <= spc) { ++ skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); ++ if (skb_headlen(skb) < spc) { ++ memcpy(((void *)(inl + 1)) + skb_headlen(skb), ++ fragptr, spc - skb_headlen(skb)); ++ fragptr += spc - skb_headlen(skb); ++ } ++ inl = (void *) (inl + 1) + spc; ++ memcpy(((void *)(inl + 1)), fragptr, skb->len -spc); ++ } else { ++ skb_copy_from_linear_data(skb, inl + 1, spc); ++ inl = (void *) (inl + 1) + spc; ++ skb_copy_from_linear_data_offset(skb, spc, inl + 1, ++ skb_headlen(skb) - spc); ++ if (skb_shinfo(skb)->nr_frags) ++ memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc, ++ fragptr, skb_shinfo(skb)->frags[0].size); ++ } ++ ++ wmb(); ++ inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); ++ } ++ tx_desc->ctrl.vlan_tag = cpu_to_be16(*vlan_tag); ++ tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * !!(*vlan_tag); ++ tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; ++} ++ ++int mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ u16 vlan_tag = 0; ++ int tx_ind = 0; ++ struct tcphdr *th = tcp_hdr(skb); ++ struct iphdr *iph = ip_hdr(skb); ++ struct mlx4_en_tx_hash_entry *entry; ++ u32 hash_index; ++ ++ /* Obtain VLAN information if present */ ++ if (priv->vlgrp && vlan_tx_tag_present(skb)) { ++ vlan_tag = vlan_tx_tag_get(skb); ++ /* Set the Tx ring to use according to vlan priority */ ++ tx_ind = priv->tx_prio_map[vlan_tag >> 13]; ++ if (tx_ind) ++ return tx_ind; ++ } ++ ++ /* Hashing is only done for TCP/IP or UDP/IP packets */ ++ if (be16_to_cpu(skb->protocol) != ETH_P_IP) ++ return MLX4_EN_NUM_HASH_RINGS; ++ ++ hash_index = be32_to_cpu(iph->daddr) & MLX4_EN_TX_HASH_MASK; ++ switch(iph->protocol) { ++ case IPPROTO_UDP: ++ break; ++ case IPPROTO_TCP: ++ hash_index = (hash_index ^ be16_to_cpu(th->dest ^ th->source)) & ++ MLX4_EN_TX_HASH_MASK; ++ break; ++ default: ++ return MLX4_EN_NUM_HASH_RINGS; ++ } ++ ++ entry = &priv->tx_hash[hash_index]; ++ if (skb->len > MLX4_EN_SMALL_PKT_SIZE) ++ entry->big_pkts++; ++ else ++ entry->small_pkts++; ++ ++ if(unlikely(!(++entry->cnt))) { ++ tx_ind = hash_index & (MLX4_EN_NUM_HASH_RINGS / 2 - 1); ++ if (2 * entry->big_pkts > entry->small_pkts) ++ tx_ind += MLX4_EN_NUM_HASH_RINGS / 2; ++ entry->small_pkts = entry->big_pkts = 0; ++ entry->ring = tx_ind; ++ } ++ return entry->ring; ++} ++ ++int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct mlx4_en_priv *priv = netdev_priv(dev); ++ struct mlx4_en_dev *mdev = priv->mdev; ++ struct mlx4_en_tx_ring *ring; ++ struct mlx4_en_cq *cq; ++ struct mlx4_en_tx_desc *tx_desc; ++ struct mlx4_wqe_data_seg *data; ++ struct skb_frag_struct *frag; ++ struct mlx4_en_tx_info *tx_info; ++ int tx_ind = 0; ++ int nr_txbb; ++ int desc_size; ++ int real_size; ++ dma_addr_t dma; ++ u32 index; ++ __be32 op_own; ++ u16 vlan_tag = 0; ++ int i; ++ int lso_header_size; ++ void *fragptr; ++ ++ if (unlikely(!skb->len)) { ++ dev_kfree_skb_any(skb); ++ return NETDEV_TX_OK; ++ } ++ real_size = get_real_size(skb, dev, &lso_header_size); ++ if (unlikely(!real_size)) ++ return NETDEV_TX_OK; ++ ++ /* Allign descriptor to TXBB size */ ++ desc_size = ALIGN(real_size, TXBB_SIZE); ++ nr_txbb = desc_size / TXBB_SIZE; ++ if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { ++ if (netif_msg_tx_err(priv)) ++ mlx4_warn(mdev, "Oversized header or SG list\n"); ++ dev_kfree_skb_any(skb); ++ return NETDEV_TX_OK; ++ } ++ ++ tx_ind = skb->queue_mapping; ++ ring = &priv->tx_ring[tx_ind]; ++ if (priv->vlgrp && vlan_tx_tag_present(skb)) ++ vlan_tag = vlan_tx_tag_get(skb); ++ ++ /* Check available TXBBs And 2K spare for prefetch */ ++ if (unlikely(((int)(ring->prod - ring->cons)) > ++ ring->size - HEADROOM - MAX_DESC_TXBBS)) { ++ /* every full Tx ring stops queue. ++ * TODO: implement multi-queue support (per-queue stop) */ ++ netif_tx_stop_queue(netdev_get_tx_queue(dev, tx_ind)); ++ ring->blocked = 1; ++ priv->port_stats.queue_stopped++; ++ ++ /* Use interrupts to find out when queue opened */ ++ cq = &priv->tx_cq[tx_ind]; ++ mlx4_en_arm_cq(priv, cq); ++ return NETDEV_TX_BUSY; ++ } ++ ++ /* Now that we know what Tx ring to use */ ++ if (unlikely(!priv->port_up)) { ++ if (netif_msg_tx_err(priv)) ++ mlx4_warn(mdev, "xmit: port down!\n"); ++ dev_kfree_skb_any(skb); ++ return NETDEV_TX_OK; ++ } ++ ++ /* Track current inflight packets for performance analysis */ ++ AVG_PERF_COUNTER(priv->pstats.inflight_avg, ++ (u32) (ring->prod - ring->cons - 1)); ++ ++ /* Packet is good - grab an index and transmit it */ ++ index = ring->prod & ring->size_mask; ++ ++ /* See if we have enough space for whole descriptor TXBB for setting ++ * SW ownership on next descriptor; if not, use a bounce buffer. */ ++ if (likely(index + nr_txbb <= ring->size)) ++ tx_desc = ring->buf + index * TXBB_SIZE; ++ else ++ tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; ++ ++ /* Save skb in tx_info ring */ ++ tx_info = &ring->tx_info[index]; ++ tx_info->skb = skb; ++ tx_info->nr_txbb = nr_txbb; ++ ++ /* Prepare ctrl segement apart opcode+ownership, which depends on ++ * whether LSO is used */ ++ tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); ++ tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * !!vlan_tag; ++ tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; ++ tx_desc->ctrl.srcrb_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE | ++ MLX4_WQE_CTRL_SOLICITED); ++ if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { ++ tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | ++ MLX4_WQE_CTRL_TCP_UDP_CSUM); ++ priv->port_stats.tx_chksum_offload++; ++ } ++ ++ /* Handle LSO (TSO) packets */ ++ if (lso_header_size) { ++ /* Mark opcode as LSO */ ++ op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | ++ ((ring->prod & ring->size) ? ++ cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); ++ ++ /* Fill in the LSO prefix */ ++ tx_desc->lso.mss_hdr_size = cpu_to_be32( ++ skb_shinfo(skb)->gso_size << 16 | lso_header_size); ++ ++ /* Copy headers; ++ * note that we already verified that it is linear */ ++ memcpy(tx_desc->lso.header, skb->data, lso_header_size); ++ data = ((void *) &tx_desc->lso + ++ ALIGN(lso_header_size + 4, DS_SIZE)); ++ ++ priv->port_stats.tso_packets++; ++ i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) + ++ !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size); ++ ring->bytes += skb->len + (i - 1) * lso_header_size; ++ ring->packets += i; ++ } else { ++ /* Normal (Non LSO) packet */ ++ op_own = cpu_to_be32(MLX4_OPCODE_SEND) | ++ ((ring->prod & ring->size) ? ++ cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); ++ data = &tx_desc->data; ++ ring->bytes += max_t(int, skb->len, ETH_ZLEN); ++ ring->packets++; ++ ++ } ++ AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); ++ ++ ++ /* valid only for none inline segments */ ++ tx_info->data_offset = (void *) data - (void *) tx_desc; ++ ++ tx_info->linear = (lso_header_size < skb_headlen(skb) && !is_inline(skb, NULL)) ? 1 : 0; ++ data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1; ++ ++ if (!is_inline(skb, &fragptr)) { ++ /* Map fragments */ ++ for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) { ++ frag = &skb_shinfo(skb)->frags[i]; ++ dma = pci_map_page(mdev->dev->pdev, frag->page, frag->page_offset, ++ frag->size, PCI_DMA_TODEVICE); ++ data->addr = cpu_to_be64(dma); ++ data->lkey = cpu_to_be32(mdev->mr.key); ++ wmb(); ++ data->byte_count = cpu_to_be32(frag->size); ++ --data; ++ } ++ ++ /* Map linear part */ ++ if (tx_info->linear) { ++ dma = pci_map_single(mdev->dev->pdev, skb->data + lso_header_size, ++ skb_headlen(skb) - lso_header_size, PCI_DMA_TODEVICE); ++ data->addr = cpu_to_be64(dma); ++ data->lkey = cpu_to_be32(mdev->mr.key); ++ wmb(); ++ data->byte_count = cpu_to_be32(skb_headlen(skb) - lso_header_size); ++ } ++ tx_info->inl = 0; ++ } else { ++ build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr); ++ tx_info->inl = 1; ++ } ++ ++ ring->prod += nr_txbb; ++ ++ /* If we used a bounce buffer then copy descriptor back into place */ ++ if (tx_desc == (struct mlx4_en_tx_desc *) ring->bounce_buf) ++ tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); ++ ++ /* Run destructor before passing skb to HW */ ++ if (likely(!skb_shared(skb))) ++ skb_orphan(skb); ++ ++ /* Ensure new descirptor hits memory ++ * before setting ownership of this descriptor to HW */ ++ wmb(); ++ tx_desc->ctrl.owner_opcode = op_own; ++ ++ /* Ring doorbell! */ ++ wmb(); ++ writel(ring->doorbell_qpn, mdev->uar_map + MLX4_SEND_DOORBELL); ++ dev->trans_start = jiffies; ++ ++ /* Poll CQ here */ ++ mlx4_en_xmit_poll(priv, tx_ind); ++ ++ return 0; ++} ++ +diff -r 4e706462aff6 drivers/net/mlx4/eq.c +--- a/drivers/net/mlx4/eq.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/eq.c Tue Oct 06 11:20:51 2009 +0100 +@@ -163,6 +163,7 @@ + int cqn; + int eqes_found = 0; + int set_ci = 0; ++ int port; + + while ((eqe = next_eqe_sw(eq))) { + /* +@@ -203,11 +204,13 @@ + break; + + case MLX4_EVENT_TYPE_PORT_CHANGE: +- mlx4_dispatch_event(dev, +- eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_ACTIVE ? +- MLX4_DEV_EVENT_PORT_UP : +- MLX4_DEV_EVENT_PORT_DOWN, +- be32_to_cpu(eqe->event.port_change.port) >> 28); ++ port = be32_to_cpu(eqe->event.port_change.port) >> 28; ++ if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) ++ mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN, ++ port); ++ else ++ mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, ++ port); + break; + + case MLX4_EVENT_TYPE_CQ_ERROR: +@@ -266,7 +269,7 @@ + + writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); + +- for (i = 0; i < MLX4_NUM_EQ; ++i) ++ for (i = 0; i < MLX4_EQ_COMP_CPU0 + dev->caps.num_comp_vectors; ++i) + work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]); + + return IRQ_RETVAL(work); +@@ -483,7 +486,7 @@ + + if (eq_table->have_irq) + free_irq(dev->pdev->irq, dev); +- for (i = 0; i < MLX4_NUM_EQ; ++i) ++ for (i = 0; i < MLX4_EQ_COMP_CPU0 + dev->caps.num_comp_vectors; ++i) + if (eq_table->eq[i].have_irq) + free_irq(eq_table->eq[i].irq, eq_table->eq + i); + } +@@ -554,11 +557,12 @@ + int mlx4_init_eq_table(struct mlx4_dev *dev) + { + struct mlx4_priv *priv = mlx4_priv(dev); ++ int req_eqs; + int err; + int i; + + err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs, +- dev->caps.num_eqs - 1, dev->caps.reserved_eqs); ++ dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0); + if (err) + return err; + +@@ -574,11 +578,21 @@ + priv->eq_table.clr_int = priv->clr_base + + (priv->eq_table.inta_pin < 32 ? 4 : 0); + +- err = mlx4_create_eq(dev, dev->caps.num_cqs + MLX4_NUM_SPARE_EQE, +- (dev->flags & MLX4_FLAG_MSI_X) ? MLX4_EQ_COMP : 0, +- &priv->eq_table.eq[MLX4_EQ_COMP]); +- if (err) +- goto err_out_unmap; ++ dev->caps.num_comp_vectors = 0; ++ req_eqs = (dev->flags & MLX4_FLAG_MSI_X) ? num_online_cpus() : 1; ++ while (req_eqs) { ++ err = mlx4_create_eq( ++ dev, dev->caps.num_cqs + MLX4_NUM_SPARE_EQE, ++ (dev->flags & MLX4_FLAG_MSI_X) ? ++ (MLX4_EQ_COMP_CPU0 + dev->caps.num_comp_vectors) : 0, ++ &priv->eq_table.eq[MLX4_EQ_COMP_CPU0 + ++ dev->caps.num_comp_vectors]); ++ if (err) ++ goto err_out_comp; ++ ++ dev->caps.num_comp_vectors++; ++ req_eqs--; ++ } + + err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE, + (dev->flags & MLX4_FLAG_MSI_X) ? MLX4_EQ_ASYNC : 0, +@@ -587,12 +601,16 @@ + goto err_out_comp; + + if (dev->flags & MLX4_FLAG_MSI_X) { +- static const char *eq_name[] = { +- [MLX4_EQ_COMP] = DRV_NAME " (comp)", +- [MLX4_EQ_ASYNC] = DRV_NAME " (async)" +- }; ++ static char eq_name[MLX4_NUM_EQ][20]; + +- for (i = 0; i < MLX4_NUM_EQ; ++i) { ++ for (i = 0; i < MLX4_EQ_COMP_CPU0 + ++ dev->caps.num_comp_vectors; ++i) { ++ if (i == 0) ++ snprintf(eq_name[0], 20, DRV_NAME "(async)"); ++ else ++ snprintf(eq_name[i], 20, "eth-mlx4-%d", ++ i - 1); ++ + err = request_irq(priv->eq_table.eq[i].irq, + mlx4_msi_x_interrupt, + 0, eq_name[i], priv->eq_table.eq + i); +@@ -617,7 +635,7 @@ + mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", + priv->eq_table.eq[MLX4_EQ_ASYNC].eqn, err); + +- for (i = 0; i < MLX4_NUM_EQ; ++i) ++ for (i = 0; i < MLX4_EQ_COMP_CPU0 + dev->caps.num_comp_vectors; ++i) + eq_set_ci(&priv->eq_table.eq[i], 1); + + return 0; +@@ -626,9 +644,9 @@ + mlx4_free_eq(dev, &priv->eq_table.eq[MLX4_EQ_ASYNC]); + + err_out_comp: +- mlx4_free_eq(dev, &priv->eq_table.eq[MLX4_EQ_COMP]); ++ for (i = 0; i < dev->caps.num_comp_vectors; ++i) ++ mlx4_free_eq(dev, &priv->eq_table.eq[MLX4_EQ_COMP_CPU0 + i]); + +-err_out_unmap: + mlx4_unmap_clr_int(dev); + mlx4_free_irqs(dev); + +@@ -647,7 +665,7 @@ + + mlx4_free_irqs(dev); + +- for (i = 0; i < MLX4_NUM_EQ; ++i) ++ for (i = 0; i < MLX4_EQ_COMP_CPU0 + dev->caps.num_comp_vectors; ++i) + mlx4_free_eq(dev, &priv->eq_table.eq[i]); + + mlx4_unmap_clr_int(dev); +diff -r 4e706462aff6 drivers/net/mlx4/fw.c +--- a/drivers/net/mlx4/fw.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/fw.c Tue Oct 06 11:20:51 2009 +0100 +@@ -138,6 +138,9 @@ + struct mlx4_cmd_mailbox *mailbox; + u32 *outbox; + u8 field; ++ u16 field16; ++ u32 field32; ++ u64 field64; + u16 size; + u16 stat_rate; + int err; +@@ -192,6 +195,8 @@ + #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 + #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 + #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 ++#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 ++#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 + #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 + #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 + #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 +@@ -302,6 +307,11 @@ + MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); + dev_cap->max_pds = 1 << (field & 0x3f); + ++ MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); ++ dev_cap->reserved_xrcds = field >> 4; ++ MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); ++ dev_cap->max_xrcds = 1 << (field & 0x1f); ++ + MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); + dev_cap->rdmarc_entry_sz = size; + MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); +@@ -346,7 +356,7 @@ + MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); + dev_cap->max_vl[i] = field >> 4; + MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); +- dev_cap->max_mtu[i] = field >> 4; ++ dev_cap->ib_mtu[i] = field >> 4; + dev_cap->max_port_width[i] = field & 0xf; + MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); + dev_cap->max_gids[i] = 1 << (field & 0xf); +@@ -354,10 +364,15 @@ + dev_cap->max_pkeys[i] = 1 << (field & 0xf); + } + } else { ++#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 + #define QUERY_PORT_MTU_OFFSET 0x01 + #define QUERY_PORT_WIDTH_OFFSET 0x06 + #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 ++#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a + #define QUERY_PORT_MAX_VL_OFFSET 0x0b ++#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 ++#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c ++#define QUERY_PORT_TRANS_CODE_OFFSET 0x20 + + for (i = 1; i <= dev_cap->num_ports; ++i) { + err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, +@@ -365,8 +380,11 @@ + if (err) + goto out; + ++ MLX4_GET(field, outbox, ++ QUERY_PORT_SUPPORTED_TYPE_OFFSET); ++ dev_cap->supported_port_types[i] = field & 3; + MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); +- dev_cap->max_mtu[i] = field & 0xf; ++ dev_cap->ib_mtu[i] = field & 0xf; + MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); + dev_cap->max_port_width[i] = field & 0xf; + MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); +@@ -374,6 +392,18 @@ + dev_cap->max_pkeys[i] = 1 << (field & 0xf); + MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); + dev_cap->max_vl[i] = field & 0xf; ++ MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); ++ dev_cap->log_max_macs[i] = field & 0xf; ++ dev_cap->log_max_vlans[i] = field >> 4; ++ dev_cap->eth_mtu[i] = be16_to_cpu(((u16 *) outbox)[1]); ++ dev_cap->def_mac[i] = be64_to_cpu(((u64 *) outbox)[2]); ++ MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); ++ dev_cap->trans_type[i] = field32 >> 24; ++ dev_cap->vendor_oui[i] = field32 & 0xffffff; ++ MLX4_GET(field16, outbox, QUERY_PORT_WAVELENGTH_OFFSET); ++ dev_cap->wavelength[i] = field16; ++ MLX4_GET(field64, outbox, QUERY_PORT_TRANS_CODE_OFFSET); ++ dev_cap->trans_code[i] = field64; + } + } + +@@ -407,7 +437,7 @@ + mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", + dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); + mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", +- dev_cap->local_ca_ack_delay, 128 << dev_cap->max_mtu[1], ++ dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], + dev_cap->max_port_width[1]); + mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", + dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); +@@ -686,6 +716,8 @@ + #define INIT_HCA_IN_SIZE 0x200 + #define INIT_HCA_VERSION_OFFSET 0x000 + #define INIT_HCA_VERSION 2 ++#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e ++#define INIT_HCA_X86_64_BYTE_CACHELINE_SZ 0x40 + #define INIT_HCA_FLAGS_OFFSET 0x014 + #define INIT_HCA_QPC_OFFSET 0x020 + #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) +@@ -722,6 +754,9 @@ + memset(inbox, 0, INIT_HCA_IN_SIZE); + + *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; ++#if defined(__x86_64__) || defined(__PPC64__) ++ *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = INIT_HCA_X86_64_BYTE_CACHELINE_SZ; ++#endif + + #if defined(__LITTLE_ENDIAN) + *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); +@@ -819,7 +854,7 @@ + flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; + MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); + +- field = 128 << dev->caps.mtu_cap[port]; ++ field = 128 << dev->caps.ib_mtu_cap[port]; + MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); + field = dev->caps.gid_table_len[port]; + MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); +@@ -872,3 +907,37 @@ + /* Input modifier of 0x1f means "finish as soon as possible." */ + return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100); + } ++ ++int mlx4_query_diag_counters(struct mlx4_dev *dev, int array_length, ++ u8 op_modifier, u32 in_offset[], u32 counter_out[]) ++{ ++ struct mlx4_cmd_mailbox *mailbox; ++ u32 *outbox; ++ int ret; ++ int i; ++ ++ mailbox = mlx4_alloc_cmd_mailbox(dev); ++ if (IS_ERR(mailbox)) ++ return PTR_ERR(mailbox); ++ outbox = mailbox->buf; ++ ++ ret = mlx4_cmd_box(dev, 0, mailbox->dma, 0, op_modifier, ++ MLX4_CMD_DIAG_RPRT, MLX4_CMD_TIME_CLASS_A); ++ if (ret) ++ goto out; ++ ++ for (i=0; i < array_length; i++) { ++ if (in_offset[i] > MLX4_MAILBOX_SIZE) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ MLX4_GET(counter_out[i], outbox, in_offset[i]); ++ } ++ ++out: ++ mlx4_free_cmd_mailbox(dev, mailbox); ++ return ret; ++} ++EXPORT_SYMBOL_GPL(mlx4_query_diag_counters); ++ +diff -r 4e706462aff6 drivers/net/mlx4/fw.h +--- a/drivers/net/mlx4/fw.h Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/fw.h Tue Oct 06 11:20:51 2009 +0100 +@@ -66,11 +66,17 @@ + int local_ca_ack_delay; + int num_ports; + u32 max_msg_sz; +- int max_mtu[MLX4_MAX_PORTS + 1]; ++ int ib_mtu[MLX4_MAX_PORTS + 1]; + int max_port_width[MLX4_MAX_PORTS + 1]; + int max_vl[MLX4_MAX_PORTS + 1]; + int max_gids[MLX4_MAX_PORTS + 1]; + int max_pkeys[MLX4_MAX_PORTS + 1]; ++ u64 def_mac[MLX4_MAX_PORTS + 1]; ++ int eth_mtu[MLX4_MAX_PORTS + 1]; ++ int trans_type[MLX4_MAX_PORTS + 1]; ++ int vendor_oui[MLX4_MAX_PORTS + 1]; ++ int wavelength[MLX4_MAX_PORTS + 1]; ++ u64 trans_code[MLX4_MAX_PORTS + 1]; + u16 stat_rate_support; + u32 flags; + int reserved_uars; +@@ -87,6 +93,8 @@ + int max_mcgs; + int reserved_pds; + int max_pds; ++ int reserved_xrcds; ++ int max_xrcds; + int qpc_entry_sz; + int rdmarc_entry_sz; + int altc_entry_sz; +@@ -102,6 +110,9 @@ + u32 reserved_lkey; + u64 max_icm_sz; + int max_gso_sz; ++ u8 supported_port_types[MLX4_MAX_PORTS + 1]; ++ u8 log_max_macs[MLX4_MAX_PORTS + 1]; ++ u8 log_max_vlans[MLX4_MAX_PORTS + 1]; + }; + + struct mlx4_adapter { +diff -r 4e706462aff6 drivers/net/mlx4/intf.c +--- a/drivers/net/mlx4/intf.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/intf.c Tue Oct 06 11:20:51 2009 +0100 +@@ -112,6 +112,36 @@ + } + EXPORT_SYMBOL_GPL(mlx4_unregister_interface); + ++struct mlx4_dev *mlx4_query_interface(void *int_dev, int *port) ++{ ++ struct mlx4_priv *priv; ++ struct mlx4_device_context *dev_ctx; ++ enum mlx4_query_reply r; ++ unsigned long flags; ++ ++ mutex_lock(&intf_mutex); ++ ++ list_for_each_entry(priv, &dev_list, dev_list) { ++ spin_lock_irqsave(&priv->ctx_lock, flags); ++ list_for_each_entry(dev_ctx, &priv->ctx_list, list) { ++ if (!dev_ctx->intf->query) ++ continue; ++ r = dev_ctx->intf->query(dev_ctx->context, int_dev); ++ if (r != MLX4_QUERY_NOT_MINE) { ++ *port = r; ++ spin_unlock_irqrestore(&priv->ctx_lock, flags); ++ mutex_unlock(&intf_mutex); ++ return &priv->dev; ++ } ++ } ++ spin_unlock_irqrestore(&priv->ctx_lock, flags); ++ } ++ ++ mutex_unlock(&intf_mutex); ++ return NULL; ++} ++EXPORT_SYMBOL_GPL(mlx4_query_interface); ++ + void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port) + { + struct mlx4_priv *priv = mlx4_priv(dev); +diff -r 4e706462aff6 drivers/net/mlx4/main.c +--- a/drivers/net/mlx4/main.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/main.c Tue Oct 06 11:20:51 2009 +0100 +@@ -59,6 +59,10 @@ + + #endif /* CONFIG_MLX4_DEBUG */ + ++int mlx4_blck_lb=1; ++module_param_named(block_loopback, mlx4_blck_lb, int, 0644); ++MODULE_PARM_DESC(block_loopback, "Block multicast loopback packets if > 0"); ++ + #ifdef CONFIG_PCI_MSI + + static int msi_x = 1; +@@ -76,14 +80,109 @@ + DRV_VERSION " (" DRV_RELDATE ")\n"; + + static struct mlx4_profile default_profile = { +- .num_qp = 1 << 17, ++ .num_qp = 1 << 18, + .num_srq = 1 << 16, + .rdmarc_per_qp = 1 << 4, + .num_cq = 1 << 16, + .num_mcg = 1 << 13, +- .num_mpt = 1 << 17, ++ .num_mpt = 1 << 19, + .num_mtt = 1 << 20, + }; ++ ++static struct mlx4_profile mod_param_profile = { 0 }; ++ ++module_param_named(log_num_qp, mod_param_profile.num_qp, int, 0444); ++MODULE_PARM_DESC(log_num_qp, "log maximum number of QPs per HCA"); ++ ++module_param_named(log_num_srq, mod_param_profile.num_srq, int, 0444); ++MODULE_PARM_DESC(log_num_srq, "log maximum number of SRQs per HCA"); ++ ++module_param_named(log_rdmarc_per_qp, mod_param_profile.rdmarc_per_qp, int, 0444); ++MODULE_PARM_DESC(log_rdmarc_per_qp, "log number of RDMARC buffers per QP"); ++ ++module_param_named(log_num_cq, mod_param_profile.num_cq, int, 0444); ++MODULE_PARM_DESC(log_num_cq, "log maximum number of CQs per HCA"); ++ ++module_param_named(log_num_mcg, mod_param_profile.num_mcg, int, 0444); ++MODULE_PARM_DESC(log_num_mcg, "log maximum number of multicast groups per HCA"); ++ ++module_param_named(log_num_mpt, mod_param_profile.num_mpt, int, 0444); ++MODULE_PARM_DESC(log_num_mpt, ++ "log maximum number of memory protection table entries per HCA"); ++ ++module_param_named(log_num_mtt, mod_param_profile.num_mtt, int, 0444); ++MODULE_PARM_DESC(log_num_mtt, ++ "log maximum number of memory translation table segments per HCA"); ++ ++static int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); ++module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); ++MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)"); ++ ++static void process_mod_param_profile(void) ++{ ++ default_profile.num_qp = (mod_param_profile.num_qp ? ++ 1 << mod_param_profile.num_qp : ++ default_profile.num_qp); ++ default_profile.num_srq = (mod_param_profile.num_srq ? ++ 1 << mod_param_profile.num_srq : ++ default_profile.num_srq); ++ default_profile.rdmarc_per_qp = (mod_param_profile.rdmarc_per_qp ? ++ 1 << mod_param_profile.rdmarc_per_qp : ++ default_profile.rdmarc_per_qp); ++ default_profile.num_cq = (mod_param_profile.num_cq ? ++ 1 << mod_param_profile.num_cq : ++ default_profile.num_cq); ++ default_profile.num_mcg = (mod_param_profile.num_mcg ? ++ 1 << mod_param_profile.num_mcg : ++ default_profile.num_mcg); ++ default_profile.num_mpt = (mod_param_profile.num_mpt ? ++ 1 << mod_param_profile.num_mpt : ++ default_profile.num_mpt); ++ default_profile.num_mtt = (mod_param_profile.num_mtt ? ++ 1 << mod_param_profile.num_mtt : ++ default_profile.num_mtt); ++} ++ ++static int log_num_mac = 2; ++module_param_named(log_num_mac, log_num_mac, int, 0444); ++MODULE_PARM_DESC(log_num_mac, "Log 2 Max number of MACs per ETH port (1-7)"); ++ ++static int log_num_vlan; ++module_param_named(log_num_vlan, log_num_vlan, int, 0444); ++MODULE_PARM_DESC(log_num_vlan, "Log 2 Max number of VLANs per ETH port (0-7)"); ++ ++static int use_prio; ++module_param_named(use_prio, use_prio, bool, 0444); ++MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports " ++ "(0/1, default 0)"); ++ ++struct mlx4_port_config ++{ ++ struct list_head list; ++ enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; ++ struct pci_dev *pdev; ++}; ++static LIST_HEAD(config_list); ++ ++static void mlx4_config_cleanup(void) ++{ ++ struct mlx4_port_config *config, *tmp; ++ ++ list_for_each_entry_safe(config, tmp, &config_list, list) { ++ list_del(&config->list); ++ kfree(config); ++ } ++} ++ ++static void mlx4_set_port_mask(struct mlx4_dev *dev) ++{ ++ int i; ++ ++ dev->caps.port_mask = 0; ++ for (i = 1; i <= dev->caps.num_ports; ++i) ++ if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB) ++ dev->caps.port_mask |= 1 << (i - 1); ++} + + static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) + { +@@ -120,10 +219,17 @@ + dev->caps.num_ports = dev_cap->num_ports; + for (i = 1; i <= dev->caps.num_ports; ++i) { + dev->caps.vl_cap[i] = dev_cap->max_vl[i]; +- dev->caps.mtu_cap[i] = dev_cap->max_mtu[i]; ++ dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; + dev->caps.gid_table_len[i] = dev_cap->max_gids[i]; + dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i]; + dev->caps.port_width_cap[i] = dev_cap->max_port_width[i]; ++ dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i]; ++ dev->caps.def_mac[i] = dev_cap->def_mac[i]; ++ dev->caps.supported_type[i] = dev_cap->supported_port_types[i]; ++ dev->caps.trans_type[i] = dev_cap->trans_type[i]; ++ dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i]; ++ dev->caps.wavelength[i] = dev_cap->wavelength[i]; ++ dev->caps.trans_code[i] = dev_cap->trans_code[i]; + } + + dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; +@@ -134,7 +240,6 @@ + dev->caps.max_rq_sg = dev_cap->max_rq_sg; + dev->caps.max_wqes = dev_cap->max_qp_sz; + dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; +- dev->caps.reserved_qps = dev_cap->reserved_qps; + dev->caps.max_srq_wqes = dev_cap->max_srq_sz; + dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; + dev->caps.reserved_srqs = dev_cap->reserved_srqs; +@@ -149,12 +254,13 @@ + dev->caps.max_cqes = dev_cap->max_cq_sz - 1; + dev->caps.reserved_cqs = dev_cap->reserved_cqs; + dev->caps.reserved_eqs = dev_cap->reserved_eqs; ++ dev->caps.mtts_per_seg = 1 << log_mtts_per_seg; + dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts, +- MLX4_MTT_ENTRY_PER_SEG); ++ dev->caps.mtts_per_seg); + dev->caps.reserved_mrws = dev_cap->reserved_mrws; + dev->caps.reserved_uars = dev_cap->reserved_uars; + dev->caps.reserved_pds = dev_cap->reserved_pds; +- dev->caps.mtt_entry_sz = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz; ++ dev->caps.mtt_entry_sz = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz; + dev->caps.max_msg_sz = dev_cap->max_msg_sz; + dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); + dev->caps.flags = dev_cap->flags; +@@ -162,6 +268,47 @@ + dev->caps.reserved_lkey = dev_cap->reserved_lkey; + dev->caps.stat_rate_support = dev_cap->stat_rate_support; + dev->caps.max_gso_sz = dev_cap->max_gso_sz; ++ dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? ++ dev_cap->reserved_xrcds : 0; ++ dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? ++ dev_cap->max_xrcds : 0; ++ ++ dev->caps.log_num_macs = log_num_mac; ++ dev->caps.log_num_vlans = log_num_vlan; ++ dev->caps.log_num_prios = use_prio ? 3 : 0; ++ ++ for (i = 1; i <= dev->caps.num_ports; ++i) { ++ if (!(dev->caps.supported_type[i] & MLX4_PORT_TYPE_ETH)) ++ dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; ++ else ++ dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; ++ dev->caps.possible_type[i] = MLX4_PORT_TYPE_ETH; ++ ++ if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { ++ dev->caps.log_num_macs = dev_cap->log_max_macs[i]; ++ mlx4_warn(dev, "Requested number of MACs is too much " ++ "for port %d, reducing to %d.\n", ++ i, 1 << dev->caps.log_num_macs); ++ } ++ if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { ++ dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; ++ mlx4_warn(dev, "Requested number of VLANs is too much " ++ "for port %d, reducing to %d.\n", ++ i, 1 << dev->caps.log_num_vlans); ++ } ++ } ++ ++ dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; ++ dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = ++ dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = ++ (1 << dev->caps.log_num_macs)* ++ (1 << dev->caps.log_num_vlans)* ++ (1 << dev->caps.log_num_prios)* ++ dev->caps.num_ports; ++ ++ dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + ++ dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + ++ dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR]; + + return 0; + } +@@ -211,7 +358,8 @@ + ((u64) (MLX4_CMPT_TYPE_QP * + cmpt_entry_sz) << MLX4_CMPT_SHIFT), + cmpt_entry_sz, dev->caps.num_qps, +- dev->caps.reserved_qps, 0, 0); ++ dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], ++ 0, 0); + if (err) + goto err; + +@@ -336,7 +484,8 @@ + init_hca->qpc_base, + dev_cap->qpc_entry_sz, + dev->caps.num_qps, +- dev->caps.reserved_qps, 0, 0); ++ dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], ++ 0, 0); + if (err) { + mlx4_err(dev, "Failed to map QP context memory, aborting.\n"); + goto err_unmap_dmpt; +@@ -346,7 +495,8 @@ + init_hca->auxc_base, + dev_cap->aux_entry_sz, + dev->caps.num_qps, +- dev->caps.reserved_qps, 0, 0); ++ dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], ++ 0, 0); + if (err) { + mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n"); + goto err_unmap_qp; +@@ -356,7 +506,8 @@ + init_hca->altc_base, + dev_cap->altc_entry_sz, + dev->caps.num_qps, +- dev->caps.reserved_qps, 0, 0); ++ dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], ++ 0, 0); + if (err) { + mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n"); + goto err_unmap_auxc; +@@ -366,7 +517,8 @@ + init_hca->rdmarc_base, + dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, + dev->caps.num_qps, +- dev->caps.reserved_qps, 0, 0); ++ dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], ++ 0, 0); + if (err) { + mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); + goto err_unmap_altc; +@@ -490,8 +642,10 @@ + struct mlx4_mod_stat_cfg mlx4_cfg; + struct mlx4_profile profile; + struct mlx4_init_hca_param init_hca; ++ struct mlx4_port_config *config; + u64 icm_size; + int err; ++ int i; + + err = mlx4_QUERY_FW(dev); + if (err) { +@@ -517,7 +671,20 @@ + goto err_stop_fw; + } + ++ process_mod_param_profile(); + profile = default_profile; ++ ++ list_for_each_entry(config, &config_list, list) { ++ if (config->pdev == dev->pdev) { ++ for (i = 1; i <= dev->caps.num_ports; i++) { ++ dev->caps.possible_type[i] = config->port_type[i]; ++ if (config->port_type[i] != MLX4_PORT_TYPE_AUTO) ++ dev->caps.port_type[i] = config->port_type[i]; ++ } ++ } ++ } ++ ++ mlx4_set_port_mask(dev); + + icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca); + if ((long long) icm_size < 0) { +@@ -565,6 +732,8 @@ + { + struct mlx4_priv *priv = mlx4_priv(dev); + int err; ++ int port; ++ __be32 ib_port_default_caps; + + err = mlx4_init_uar_table(dev); + if (err) { +@@ -595,11 +764,18 @@ + goto err_kar_unmap; + } + ++ err = mlx4_init_xrcd_table(dev); ++ if (err) { ++ mlx4_err(dev, "Failed to initialize extended " ++ "reliably connected domain table, aborting.\n"); ++ goto err_pd_table_free; ++ } ++ + err = mlx4_init_mr_table(dev); + if (err) { + mlx4_err(dev, "Failed to initialize " + "memory region table, aborting.\n"); +- goto err_pd_table_free; ++ goto err_xrcd_table_free; + } + + err = mlx4_init_eq_table(dev); +@@ -663,7 +839,26 @@ + goto err_qp_table_free; + } + ++ for (port = 1; port <= dev->caps.num_ports; port++) { ++ ib_port_default_caps = 0; ++ err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps); ++ if (err) ++ mlx4_warn(dev, "failed to get port %d default " ++ "ib capabilities (%d). Continuing with " ++ "caps = 0\n", port, err); ++ dev->caps.ib_port_def_cap[port] = ib_port_default_caps; ++ err = mlx4_SET_PORT(dev, port); ++ if (err) { ++ mlx4_err(dev, "Failed to set port %d, aborting\n", ++ port); ++ goto err_mcg_table_free; ++ } ++ } ++ + return 0; ++ ++err_mcg_table_free: ++ mlx4_cleanup_mcg_table(dev); + + err_qp_table_free: + mlx4_cleanup_qp_table(dev); +@@ -683,6 +878,9 @@ + err_mr_table_free: + mlx4_cleanup_mr_table(dev); + ++err_xrcd_table_free: ++ mlx4_cleanup_xrcd_table(dev); ++ + err_pd_table_free: + mlx4_cleanup_pd_table(dev); + +@@ -701,22 +899,24 @@ + { + struct mlx4_priv *priv = mlx4_priv(dev); + struct msix_entry entries[MLX4_NUM_EQ]; ++ int needed_vectors = MLX4_EQ_COMP_CPU0 + num_online_cpus(); + int err; + int i; + + if (msi_x) { +- for (i = 0; i < MLX4_NUM_EQ; ++i) ++ for (i = 0; i < needed_vectors; ++i) + entries[i].entry = i; + +- err = pci_enable_msix(dev->pdev, entries, ARRAY_SIZE(entries)); ++ err = pci_enable_msix(dev->pdev, entries, needed_vectors); + if (err) { + if (err > 0) +- mlx4_info(dev, "Only %d MSI-X vectors available, " +- "not using MSI-X\n", err); ++ mlx4_info(dev, "Only %d MSI-X vectors " ++ "available, need %d. Not using MSI-X\n", ++ err, needed_vectors); + goto no_msi; + } + +- for (i = 0; i < MLX4_NUM_EQ; ++i) ++ for (i = 0; i < needed_vectors; ++i) + priv->eq_table.eq[i].irq = entries[i].vector; + + dev->flags |= MLX4_FLAG_MSI_X; +@@ -724,8 +924,21 @@ + } + + no_msi: +- for (i = 0; i < MLX4_NUM_EQ; ++i) ++ for (i = 0; i < needed_vectors; ++i) + priv->eq_table.eq[i].irq = dev->pdev->irq; ++} ++ ++static int mlx4_init_port_info(struct mlx4_dev *dev, int port) ++{ ++ struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; ++ int err = 0; ++ ++ info->dev = dev; ++ info->port = port; ++ mlx4_init_mac_table(dev, &info->mac_table); ++ mlx4_init_vlan_table(dev, &info->vlan_table); ++ ++ return err; + } + + static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) +@@ -733,6 +946,7 @@ + struct mlx4_priv *priv; + struct mlx4_dev *dev; + int err; ++ int port; + + printk(KERN_INFO PFX "Initializing %s\n", + pci_name(pdev)); +@@ -807,6 +1021,8 @@ + INIT_LIST_HEAD(&priv->ctx_list); + spin_lock_init(&priv->ctx_lock); + ++ mutex_init(&priv->port_mutex); ++ + INIT_LIST_HEAD(&priv->pgdir_list); + mutex_init(&priv->pgdir_mutex); + +@@ -842,6 +1058,12 @@ + if (err) + goto err_close; + ++ for (port = 1; port <= dev->caps.num_ports; port++) { ++ err = mlx4_init_port_info(dev, port); ++ if (err) ++ goto err_cleanup; ++ } ++ + err = mlx4_register_device(dev); + if (err) + goto err_cleanup; +@@ -858,6 +1080,7 @@ + mlx4_cmd_use_polling(dev); + mlx4_cleanup_eq_table(dev); + mlx4_cleanup_mr_table(dev); ++ mlx4_cleanup_xrcd_table(dev); + mlx4_cleanup_pd_table(dev); + mlx4_cleanup_uar_table(dev); + +@@ -906,10 +1129,8 @@ + + if (dev) { + mlx4_unregister_device(dev); +- +- for (p = 1; p <= dev->caps.num_ports; ++p) ++ for (p = 1; p <= dev->caps.num_ports; p++) + mlx4_CLOSE_PORT(dev, p); +- + mlx4_cleanup_mcg_table(dev); + mlx4_cleanup_qp_table(dev); + mlx4_cleanup_srq_table(dev); +@@ -917,6 +1138,7 @@ + mlx4_cmd_use_polling(dev); + mlx4_cleanup_eq_table(dev); + mlx4_cleanup_mr_table(dev); ++ mlx4_cleanup_xrcd_table(dev); + mlx4_cleanup_pd_table(dev); + + iounmap(priv->kar); +@@ -948,6 +1170,10 @@ + { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */ + { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */ + { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */ ++ { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon"EN 10GigE */ ++ { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon"EN 10GigE + Gen2 */ ++ { PCI_VDEVICE(MELLANOX, 0x6372) }, /* MT25408 "YATIR" EN 10GigE */ ++ { PCI_VDEVICE(MELLANOX, 0x675a) }, /* MT25408 "YATIR" EN 10GigE + Gen2 */ + { 0, } + }; + +@@ -960,9 +1186,32 @@ + .remove = __devexit_p(mlx4_remove_one) + }; + ++static int __init mlx4_verify_params(void) ++{ ++ if ((log_num_mac < 0) || (log_num_mac > 7)) { ++ printk(KERN_WARNING "mlx4_core: bad num_mac: %d\n", log_num_mac); ++ return -1; ++ } ++ ++ if ((log_num_vlan < 0) || (log_num_vlan > 7)) { ++ printk(KERN_WARNING "mlx4_core: bad num_vlan: %d\n", log_num_vlan); ++ return -1; ++ } ++ ++ if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) { ++ printk(KERN_WARNING "mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg); ++ return -1; ++ } ++ ++ return 0; ++} ++ + static int __init mlx4_init(void) + { + int ret; ++ ++ if (mlx4_verify_params()) ++ return -EINVAL; + + ret = mlx4_catas_init(); + if (ret) +@@ -976,6 +1225,7 @@ + { + pci_unregister_driver(&mlx4_driver); + mlx4_catas_cleanup(); ++ mlx4_config_cleanup(); + } + + module_init(mlx4_init); +diff -r 4e706462aff6 drivers/net/mlx4/mcg.c +--- a/drivers/net/mlx4/mcg.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/mcg.c Tue Oct 06 11:20:51 2009 +0100 +@@ -213,11 +213,8 @@ + goto out; + } + +- if (block_mcast_loopback) +- mgm->qp[members_count++] = cpu_to_be32((qp->qpn & MGM_QPN_MASK) | +- (1 << MGM_BLCK_LB_BIT)); +- else +- mgm->qp[members_count++] = cpu_to_be32(qp->qpn & MGM_QPN_MASK); ++ mgm->qp[members_count++] = cpu_to_be32((qp->qpn & MGM_QPN_MASK) | ++ (!!mlx4_blck_lb << MGM_BLCK_LB_BIT)); + + mgm->members_count = cpu_to_be32(members_count); + +@@ -368,8 +365,8 @@ + struct mlx4_priv *priv = mlx4_priv(dev); + int err; + +- err = mlx4_bitmap_init(&priv->mcg_table.bitmap, +- dev->caps.num_amgms, dev->caps.num_amgms - 1, 0); ++ err = mlx4_bitmap_init(&priv->mcg_table.bitmap, dev->caps.num_amgms, ++ dev->caps.num_amgms - 1, 0, 0); + if (err) + return err; + +diff -r 4e706462aff6 drivers/net/mlx4/mlx4.h +--- a/drivers/net/mlx4/mlx4.h Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/mlx4.h Tue Oct 06 11:20:51 2009 +0100 +@@ -40,6 +40,8 @@ + #include + #include + #include ++#include ++#include + + #include + #include +@@ -47,8 +49,8 @@ + + #define DRV_NAME "mlx4_core" + #define PFX DRV_NAME ": " +-#define DRV_VERSION "0.01" +-#define DRV_RELDATE "May 1, 2007" ++#define DRV_VERSION "1.0" ++#define DRV_RELDATE "April 4, 2008" + + enum { + MLX4_HCR_BASE = 0x80680, +@@ -64,8 +66,8 @@ + + enum { + MLX4_EQ_ASYNC, +- MLX4_EQ_COMP, +- MLX4_NUM_EQ ++ MLX4_EQ_COMP_CPU0, ++ MLX4_NUM_EQ = MLX4_EQ_COMP_CPU0 + NR_CPUS + }; + + enum { +@@ -107,10 +109,13 @@ + #define mlx4_warn(mdev, format, arg...) \ + dev_warn(&mdev->pdev->dev, format, ## arg) + ++extern int mlx4_blck_lb; ++ + struct mlx4_bitmap { + u32 last; + u32 top; + u32 max; ++ u32 reserved_top; + u32 mask; + spinlock_t lock; + unsigned long *table; +@@ -144,6 +149,7 @@ + u16 irq; + u16 have_irq; + int nent; ++ int load; + struct mlx4_buf_list *page_list; + struct mlx4_mtt mtt; + }; +@@ -222,7 +228,6 @@ + struct mlx4_srq_table { + struct mlx4_bitmap bitmap; + spinlock_t lock; +- struct radix_tree_root tree; + struct mlx4_icm_table table; + struct mlx4_icm_table cmpt_table; + }; +@@ -251,6 +256,39 @@ + struct list_head list; + }; + ++struct mlx4_mac_table { ++#define MLX4_MAX_MAC_NUM 128 ++#define MLX4_MAC_MASK 0xffffffffffff ++#define MLX4_MAC_VALID_SHIFT 63 ++#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) ++ __be64 entries[MLX4_MAX_MAC_NUM]; ++ int refs[MLX4_MAX_MAC_NUM]; ++ struct semaphore mac_sem; ++ int total; ++ int max; ++}; ++ ++struct mlx4_vlan_table { ++#define MLX4_MAX_VLAN_NUM 128 ++#define MLX4_VLAN_MASK 0xfff ++#define MLX4_VLAN_VALID (1 << 31) ++#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) ++ __be32 entries[MLX4_MAX_VLAN_NUM]; ++ int refs[MLX4_MAX_VLAN_NUM]; ++ struct semaphore vlan_sem; ++ int total; ++ int max; ++}; ++ ++struct mlx4_port_info { ++ struct mlx4_dev *dev; ++ int port; ++ enum mlx4_port_type tmp_type; ++ struct mlx4_mac_table mac_table; ++ struct mlx4_vlan_table vlan_table; ++}; ++ ++ + struct mlx4_priv { + struct mlx4_dev dev; + +@@ -265,6 +303,7 @@ + struct mlx4_cmd cmd; + + struct mlx4_bitmap pd_bitmap; ++ struct mlx4_bitmap xrcd_bitmap; + struct mlx4_uar_table uar_table; + struct mlx4_mr_table mr_table; + struct mlx4_cq_table cq_table; +@@ -279,6 +318,8 @@ + + struct mlx4_uar driver_uar; + void __iomem *kar; ++ struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; ++ struct mutex port_mutex; + }; + + static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) +@@ -288,12 +329,16 @@ + + u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); + void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj); +-int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, u32 reserved); ++u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align); ++void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt); ++int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, ++ u32 reserved_bot, u32 resetrved_top); + void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); + + int mlx4_reset(struct mlx4_dev *dev); + + int mlx4_init_pd_table(struct mlx4_dev *dev); ++int mlx4_init_xrcd_table(struct mlx4_dev *dev); + int mlx4_init_uar_table(struct mlx4_dev *dev); + int mlx4_init_mr_table(struct mlx4_dev *dev); + int mlx4_init_eq_table(struct mlx4_dev *dev); +@@ -310,6 +355,7 @@ + void mlx4_cleanup_qp_table(struct mlx4_dev *dev); + void mlx4_cleanup_srq_table(struct mlx4_dev *dev); + void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); ++void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); + + void mlx4_start_catas_poll(struct mlx4_dev *dev); + void mlx4_stop_catas_poll(struct mlx4_dev *dev); +@@ -346,4 +392,10 @@ + + void mlx4_handle_catas_err(struct mlx4_dev *dev); + ++void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); ++void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); ++ ++int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port); ++int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); ++ + #endif /* MLX4_H */ +diff -r 4e706462aff6 drivers/net/mlx4/mlx4_en.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/mlx4_en.h Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,658 @@ ++/* ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++#ifndef _MLX4_EN_H_ ++#define _MLX4_EN_H_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "en_port.h" ++ ++#define DRV_NAME "mlx4_en" ++#define DRV_VERSION "1.4.1" ++#define DRV_RELDATE "April 2009" ++ ++ ++#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) ++ ++#define mlx4_dbg(mlevel, priv, format, arg...) \ ++ if (NETIF_MSG_##mlevel & priv->msg_enable) \ ++ printk(KERN_DEBUG "%s %s: " format , DRV_NAME ,\ ++ (&priv->mdev->pdev->dev)->bus_id , ## arg) ++ ++#define mlx4_err(mdev, format, arg...) \ ++ printk(KERN_ERR "%s %s: " format , DRV_NAME ,\ ++ (&mdev->pdev->dev)->bus_id , ## arg) ++#define mlx4_info(mdev, format, arg...) \ ++ printk(KERN_INFO "%s %s: " format , DRV_NAME ,\ ++ (&mdev->pdev->dev)->bus_id , ## arg) ++#define mlx4_warn(mdev, format, arg...) \ ++ printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\ ++ (&mdev->pdev->dev)->bus_id , ## arg) ++ ++/* ++ * Device constants ++ */ ++ ++ ++#define MLX4_EN_PAGE_SHIFT 12 ++#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) ++#define MAX_TX_RINGS (MLX4_EN_NUM_HASH_RINGS + MLX4_EN_NUM_PPP_RINGS + 1) ++#define MAX_RX_RINGS 17 ++#define MAX_RSS_MAP_SIZE 64 ++#define RSS_FACTOR 1 ++#define TXBB_SIZE 64 ++#define HEADROOM (2048 / TXBB_SIZE + 1) ++#define MAX_LSO_HDR_SIZE 92 ++#define STAMP_STRIDE 64 ++#define STAMP_DWORDS (STAMP_STRIDE / 4) ++#define STAMP_SHIFT 31 ++#define STAMP_VAL 0x7fffffff ++#define STATS_DELAY (HZ / 4) ++ ++/* Typical TSO descriptor with 16 gather entries is 352 bytes... */ ++#define MAX_DESC_SIZE 512 ++#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) ++ ++/* ++ * OS related constants and tunables ++ */ ++ ++#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) ++ ++#define MLX4_EN_ALLOC_ORDER 2 ++#define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER) ++ ++#define MLX4_EN_MAX_LRO_DESCRIPTORS 32 ++#define MLX4_EN_NUM_IPFRAG_SESSIONS 16 ++ ++/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU ++ * and 4K allocations) */ ++enum { ++ FRAG_SZ0 = 512 - NET_IP_ALIGN, ++ FRAG_SZ1 = 1024, ++ FRAG_SZ2 = 4096, ++ FRAG_SZ3 = MLX4_EN_ALLOC_SIZE ++}; ++#define MLX4_EN_MAX_RX_FRAGS 4 ++ ++/* Maximum ring sizes */ ++#define MLX4_EN_MAX_TX_SIZE 8192 ++#define MLX4_EN_MAX_RX_SIZE 8192 ++ ++/* Minimum ring size for our page-allocation sceme to work */ ++#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) ++#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) ++ ++#define MLX4_EN_SMALL_PKT_SIZE 64 ++#define MLX4_EN_TX_HASH_SIZE 256 ++#define MLX4_EN_TX_HASH_MASK (MLX4_EN_TX_HASH_SIZE - 1) ++#define MLX4_EN_NUM_HASH_RINGS 8 ++#define MLX4_EN_NUM_PPP_RINGS 8 ++#define MLX4_EN_DEF_TX_RING_SIZE 512 ++#define MLX4_EN_DEF_RX_RING_SIZE 1024 ++ ++/* Target number of bytes to coalesce with interrupt moderation */ ++#define MLX4_EN_RX_COAL_TARGET 0x20000 ++#define MLX4_EN_RX_COAL_TIME 0x10 ++ ++#define MLX4_EN_TX_COAL_PKTS 5 ++#define MLX4_EN_TX_COAL_TIME 0x80 ++ ++#define MLX4_EN_RX_RATE_LOW 400000 ++#define MLX4_EN_RX_COAL_TIME_LOW 0 ++#define MLX4_EN_RX_RATE_HIGH 450000 ++#define MLX4_EN_RX_COAL_TIME_HIGH 128 ++#define MLX4_EN_RX_SIZE_THRESH 1024 ++#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) ++#define MLX4_EN_SAMPLE_INTERVAL 0 ++ ++#define MLX4_EN_AUTO_CONF 0xffff ++ ++#define MLX4_EN_DEF_RX_PAUSE 1 ++#define MLX4_EN_DEF_TX_PAUSE 1 ++ ++/* Interval between sucessive polls in the Tx routine when polling is used ++ instead of interrupts (in per-core Tx rings) - should be power of 2 */ ++#define MLX4_EN_TX_POLL_MODER 16 ++#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) ++ ++#define ETH_LLC_SNAP_SIZE 8 ++ ++#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) ++#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) ++ ++#define MLX4_EN_MIN_MTU 46 ++#define ETH_BCAST 0xffffffffffff ++ ++#ifdef MLX4_EN_PERF_STAT ++/* Number of samples to 'average' */ ++#define AVG_SIZE 128 ++#define AVG_FACTOR 1024 ++#define NUM_PERF_STATS NUM_PERF_COUNTERS ++ ++#define INC_PERF_COUNTER(cnt) (++(cnt)) ++#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) ++#define AVG_PERF_COUNTER(cnt, sample) \ ++ ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) ++#define GET_PERF_COUNTER(cnt) (cnt) ++#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) ++ ++#else ++ ++#define NUM_PERF_STATS 0 ++#define INC_PERF_COUNTER(cnt) do {} while (0) ++#define ADD_PERF_COUNTER(cnt, add) do {} while (0) ++#define AVG_PERF_COUNTER(cnt, sample) do {} while (0) ++#define GET_PERF_COUNTER(cnt) (0) ++#define GET_AVG_PERF_COUNTER(cnt) (0) ++#endif /* MLX4_EN_PERF_STAT */ ++ ++/* ++ * Configurables ++ */ ++ ++enum cq_type { ++ RX = 0, ++ TX = 1, ++}; ++ ++ ++/* ++ * Useful macros ++ */ ++#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) ++#define XNOR(x, y) (!(x) == !(y)) ++#define ILLEGAL_MAC(addr) (addr == 0xffffffffffff || addr == 0x0) ++ ++ ++struct mlx4_en_tx_info { ++ struct sk_buff *skb; ++ u32 nr_txbb; ++ u8 linear; ++ u8 data_offset; ++ u8 inl; ++}; ++ ++ ++#define MLX4_EN_BIT_DESC_OWN 0x80000000 ++#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) ++#define MLX4_EN_MEMTYPE_PAD 0x100 ++#define DS_SIZE sizeof(struct mlx4_wqe_data_seg) ++ ++ ++struct mlx4_en_tx_desc { ++ struct mlx4_wqe_ctrl_seg ctrl; ++ union { ++ struct mlx4_wqe_data_seg data; /* at least one data segment */ ++ struct mlx4_wqe_lso_seg lso; ++ struct mlx4_wqe_inline_seg inl; ++ }; ++}; ++ ++#define MLX4_EN_USE_SRQ 0x01000000 ++ ++struct mlx4_en_rx_alloc { ++ struct page *page; ++ u16 offset; ++}; ++ ++struct mlx4_en_tx_ring { ++ struct mlx4_hwq_resources wqres; ++ u32 size ; /* number of TXBBs */ ++ u32 size_mask; ++ u16 stride; ++ u16 cqn; /* index of port CQ associated with this ring */ ++ u32 prod; ++ u32 cons; ++ u32 buf_size; ++ u32 doorbell_qpn; ++ void *buf; ++ u16 poll_cnt; ++ int blocked; ++ struct mlx4_en_tx_info *tx_info; ++ u8 *bounce_buf; ++ u32 last_nr_txbb; ++ struct mlx4_qp qp; ++ struct mlx4_qp_context context; ++ u32 qpn; ++ enum mlx4_qp_state qp_state; ++ struct mlx4_srq dummy; ++ unsigned long bytes; ++ unsigned long packets; ++ spinlock_t comp_lock; ++}; ++ ++ ++struct mlx4_en_ipfrag { ++ struct sk_buff *fragments; ++ struct sk_buff *last; ++ __be32 saddr; ++ __be32 daddr; ++ __be16 id; ++ u8 protocol; ++ int total_len; ++ u16 offset; ++ unsigned int vlan; ++ __be16 sl_vid; ++}; ++ ++struct mlx4_en_rx_desc { ++ struct mlx4_wqe_srq_next_seg next; ++ /* actual number of entries depends on rx ring stride */ ++ struct mlx4_wqe_data_seg data[0]; ++}; ++ ++struct mlx4_en_lro { ++ struct hlist_node node; ++ struct hlist_node flush_node; ++ ++ /* Id fields come first: */ ++ u32 saddr; ++ u32 daddr; ++ u32 sport_dport; ++ u32 next_seq; ++ u16 tot_len; ++ u8 psh; ++ ++ u32 tsval; ++ u32 tsecr; ++ u32 ack_seq; ++ u16 window; ++ __be16 vlan_prio; ++ u16 has_vlan; ++ u16 has_timestamp; ++ u16 mss; ++ __wsum data_csum; ++ ++ unsigned long expires; ++ struct sk_buff *skb; ++ struct sk_buff *skb_last; ++}; ++ ++ ++struct mlx4_en_rx_ring { ++ struct mlx4_srq srq; ++ struct mlx4_hwq_resources wqres; ++ struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; ++ struct mlx4_en_lro lro; ++ struct hlist_head *lro_hash; ++ struct hlist_head lro_free; ++ struct hlist_head lro_flush; ++ u32 size ; /* number of Rx descs*/ ++ u32 actual_size; ++ u32 size_mask; ++ u16 stride; ++ u16 log_stride; ++ u16 cqn; /* index of port CQ associated with this ring */ ++ u32 prod; ++ u32 cons; ++ u32 buf_size; ++ int need_refill; ++ int full; ++ void *buf; ++ void *rx_info; ++ unsigned long bytes; ++ unsigned long packets; ++ struct mlx4_en_ipfrag ipfrag[MLX4_EN_NUM_IPFRAG_SESSIONS]; ++ unsigned int use_frags; ++}; ++ ++ ++static inline int mlx4_en_can_lro(__be16 status) ++{ ++ return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | ++ MLX4_CQE_STATUS_IPV4F | ++ MLX4_CQE_STATUS_IPV6 | ++ MLX4_CQE_STATUS_IPV4OPT | ++ MLX4_CQE_STATUS_TCP | ++ MLX4_CQE_STATUS_UDP | ++ MLX4_CQE_STATUS_IPOK)) == ++ cpu_to_be16(MLX4_CQE_STATUS_IPV4 | ++ MLX4_CQE_STATUS_IPOK | ++ MLX4_CQE_STATUS_TCP); ++} ++ ++struct mlx4_en_cq { ++ struct mlx4_cq mcq; ++ struct mlx4_hwq_resources wqres; ++ int ring; ++ spinlock_t lock; ++ struct net_device *dev; ++ struct napi_struct napi; ++ /* Per-core Tx cq processing support */ ++ struct timer_list timer; ++ int size; ++ int buf_size; ++ unsigned vector; ++ enum cq_type is_tx; ++ u16 moder_time; ++ u16 moder_cnt; ++ int (*process_cq)(struct net_device *, struct mlx4_en_cq *, int); ++ struct mlx4_cqe *buf; ++#define MLX4_EN_OPCODE_ERROR 0x1e ++}; ++ ++struct mlx4_en_port_profile { ++ u32 flags; ++ u32 tx_ring_num; ++ u32 rx_ring_num; ++ u32 tx_ring_size; ++ u32 rx_ring_size; ++ u8 rx_pause; ++ u8 rx_ppp; ++ u8 tx_pause; ++ u8 tx_ppp; ++}; ++ ++struct mlx4_en_profile { ++ int rss_xor; ++ int num_lro; ++ int ip_reasm; ++ u8 rss_mask; ++ u32 active_ports; ++ u32 small_pkt_int; ++ u8 no_reset; ++ struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; ++}; ++ ++struct mlx4_en_dev { ++ struct mlx4_dev *dev; ++ struct pci_dev *pdev; ++ struct mutex state_lock; ++ struct net_device *pndev[MLX4_MAX_PORTS + 1]; ++ u32 port_cnt; ++ bool device_up; ++ struct mlx4_en_profile profile; ++ u32 LSO_support; ++ struct workqueue_struct *workqueue; ++ struct device *dma_device; ++ void __iomem *uar_map; ++ struct mlx4_uar priv_uar; ++ struct mlx4_mr mr; ++ u32 priv_pdn; ++ spinlock_t uar_lock; ++}; ++ ++ ++struct mlx4_en_rss_map { ++ int size; ++ int base_qpn; ++ u16 map[MAX_RSS_MAP_SIZE]; ++ struct mlx4_qp qps[MAX_RSS_MAP_SIZE]; ++ enum mlx4_qp_state state[MAX_RSS_MAP_SIZE]; ++ struct mlx4_qp indir_qp; ++ enum mlx4_qp_state indir_state; ++}; ++ ++struct mlx4_en_rss_context { ++ __be32 base_qpn; ++ __be32 default_qpn; ++ u16 reserved; ++ u8 hash_fn; ++ u8 flags; ++ __be32 rss_key[10]; ++}; ++ ++struct mlx4_en_pkt_stats { ++ unsigned long broadcast; ++ unsigned long rx_prio[8]; ++ unsigned long tx_prio[8]; ++#define NUM_PKT_STATS 17 ++}; ++ ++struct mlx4_en_port_stats { ++ unsigned long lro_aggregated; ++ unsigned long lro_flushed; ++ unsigned long lro_no_desc; ++ unsigned long tso_packets; ++ unsigned long queue_stopped; ++ unsigned long wake_queue; ++ unsigned long tx_timeout; ++ unsigned long rx_alloc_failed; ++ unsigned long rx_chksum_good; ++ unsigned long rx_chksum_none; ++ unsigned long tx_chksum_offload; ++#define NUM_PORT_STATS 11 ++}; ++ ++struct mlx4_en_perf_stats { ++ u32 tx_poll; ++ u64 tx_pktsz_avg; ++ u32 inflight_avg; ++ u16 tx_coal_avg; ++ u16 rx_coal_avg; ++ u32 napi_quota; ++#define NUM_PERF_COUNTERS 6 ++}; ++ ++struct mlx4_en_frag_info { ++ u16 frag_size; ++ u16 frag_prefix_size; ++ u16 frag_stride; ++ u16 frag_align; ++ u16 last_offset; ++ ++}; ++ ++struct mlx4_en_tx_hash_entry { ++ u8 cnt; ++ unsigned int small_pkts; ++ unsigned int big_pkts; ++ unsigned int ring; ++}; ++ ++struct mlx4_en_priv { ++ struct mlx4_en_dev *mdev; ++ struct mlx4_en_port_profile *prof; ++ struct net_device *dev; ++ struct vlan_group *vlgrp; ++ struct net_device_stats stats; ++ struct net_device_stats ret_stats; ++ spinlock_t stats_lock; ++ ++ unsigned long last_moder_packets; ++ unsigned long last_moder_tx_packets; ++ unsigned long last_moder_bytes; ++ unsigned long last_moder_jiffies; ++ int last_moder_time; ++ u16 rx_usecs; ++ u16 rx_frames; ++ u16 tx_usecs; ++ u16 tx_frames; ++ u32 pkt_rate_low; ++ u16 rx_usecs_low; ++ u32 pkt_rate_high; ++ u16 rx_usecs_high; ++ u16 sample_interval; ++ u16 adaptive_rx_coal; ++ u32 msg_enable; ++ ++ struct mlx4_hwq_resources res; ++ int link_state; ++ int last_link_state; ++ bool port_up; ++ int port; ++ int registered; ++ int allocated; ++ int rx_csum; ++ u64 mac; ++ int mac_index; ++ unsigned max_mtu; ++ int base_qpn; ++ ++ struct mlx4_en_rss_map rss_map; ++ u16 tx_prio_map[8]; ++ u32 flags; ++#define MLX4_EN_FLAG_PROMISC 0x1 ++ u32 tx_ring_num; ++ u32 rx_ring_num; ++ u32 rx_skb_size; ++ struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; ++ u16 num_frags; ++ u16 log_rx_info; ++ ++ struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS]; ++ struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS]; ++ struct mlx4_en_cq tx_cq[MAX_TX_RINGS]; ++ struct mlx4_en_cq rx_cq[MAX_RX_RINGS]; ++ struct mlx4_en_tx_hash_entry tx_hash[MLX4_EN_TX_HASH_SIZE]; ++ struct work_struct mcast_task; ++ struct work_struct mac_task; ++ struct delayed_work refill_task; ++ struct work_struct watchdog_task; ++ struct work_struct linkstate_task; ++ struct delayed_work stats_task; ++ struct mlx4_en_perf_stats pstats; ++ struct mlx4_en_pkt_stats pkstats; ++ struct mlx4_en_port_stats port_stats; ++ struct dev_mc_list *mc_list; ++ struct mlx4_en_stat_out_mbox hw_stats; ++}; ++ ++int mlx4_en_rx_frags(struct mlx4_en_priv *priv, struct mlx4_en_rx_ring *ring, ++ struct sk_buff *skb, struct mlx4_cqe *cqe); ++void mlx4_en_flush_frags(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring); ++void mlx4_en_destroy_netdev(struct net_device *dev); ++int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, ++ struct mlx4_en_port_profile *prof); ++ ++int mlx4_en_start_port(struct net_device *dev); ++void mlx4_en_stop_port(struct net_device *dev); ++ ++void mlx4_en_free_resources(struct mlx4_en_priv *priv); ++int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); ++ ++int mlx4_en_get_profile(struct mlx4_en_dev *mdev); ++ ++int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, ++ int entries, int ring, enum cq_type mode); ++void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); ++int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); ++void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); ++int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); ++int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); ++ ++void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq); ++void mlx4_en_poll_tx_cq(unsigned long data); ++void mlx4_en_tx_irq(struct mlx4_cq *mcq); ++int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); ++int mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb); ++ ++int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring, ++ u32 size, u16 stride); ++void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring); ++int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, ++ struct mlx4_en_tx_ring *ring, ++ int cq, int srqn); ++void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, ++ struct mlx4_en_tx_ring *ring); ++ ++int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring, u32 size); ++void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring); ++int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); ++void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_ring *ring); ++int mlx4_en_process_rx_cq(struct net_device *dev, ++ struct mlx4_en_cq *cq, ++ int budget); ++int mlx4_en_process_rx_cq_skb(struct net_device *dev, ++ struct mlx4_en_cq *cq, ++ int budget); ++int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); ++void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, ++ int is_tx, int rss, int qpn, int cqn, int srqn, ++ struct mlx4_qp_context *context); ++void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); ++int mlx4_en_map_buffer(struct mlx4_buf *buf); ++void mlx4_en_unmap_buffer(struct mlx4_buf *buf); ++ ++void mlx4_en_calc_rx_buf(struct net_device *dev); ++int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_desc *rx_desc, ++ struct skb_frag_struct *skb_frags, ++ struct skb_frag_struct *skb_frags_rx, ++ struct mlx4_en_rx_alloc *page_alloc, ++ int length); ++struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, ++ struct mlx4_en_rx_desc *rx_desc, ++ struct skb_frag_struct *skb_frags, ++ struct mlx4_en_rx_alloc *page_alloc, ++ unsigned int length); ++ ++void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv, ++ struct mlx4_en_rss_map *rss_map, ++ int num_entries, int num_rings); ++ ++void mlx4_en_lro_flush(struct mlx4_en_priv* priv, struct mlx4_en_rx_ring *ring, u8 all); ++int mlx4_en_lro_rx(struct mlx4_en_priv *priv, struct mlx4_en_rx_ring *ring, ++ struct mlx4_en_rx_desc *rx_desc, ++ struct skb_frag_struct *skb_frags, ++ unsigned int length, struct mlx4_cqe *cqe); ++void mlx4_en_lro_destroy(struct mlx4_en_rx_ring *ring); ++int mlx4_en_lro_init(struct mlx4_en_rx_ring *ring, int num_lro); ++ ++void mlx4_en_set_prio_map(struct mlx4_en_priv *priv, u16 *prio_map, u32 ring_num); ++int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); ++void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); ++int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); ++void mlx4_en_rx_refill(struct work_struct *work); ++void mlx4_en_rx_irq(struct mlx4_cq *mcq); ++ ++int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); ++int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp); ++int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, ++ u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); ++int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, ++ u8 promisc); ++ ++int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); ++ ++/* ++ * Globals ++ */ ++extern const struct ethtool_ops mlx4_en_ethtool_ops; ++#endif +diff -r 4e706462aff6 drivers/net/mlx4/mr.c +--- a/drivers/net/mlx4/mr.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/mr.c Tue Oct 06 11:20:51 2009 +0100 +@@ -52,7 +52,9 @@ + __be64 length; + __be32 lkey; + __be32 win_cnt; +- u8 reserved1[3]; ++ u8 reserved1; ++ u8 flags2; ++ u8 reserved2; + u8 mtt_rep; + __be64 mtt_seg; + __be32 mtt_sz; +@@ -70,6 +72,8 @@ + #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) + #define MLX4_MPT_PD_FLAG_RAE (1 << 28) + #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) ++ ++#define MLX4_MPT_FLAG2_FBO_EN (1 << 7) + + #define MLX4_MPT_STATUS_SW 0xF0 + #define MLX4_MPT_STATUS_HW 0x00 +@@ -209,7 +213,7 @@ + } else + mtt->page_shift = page_shift; + +- for (mtt->order = 0, i = MLX4_MTT_ENTRY_PER_SEG; i < npages; i <<= 1) ++ for (mtt->order = 0, i = dev->caps.mtts_per_seg; i < npages; i <<= 1) + ++mtt->order; + + mtt->first_seg = mlx4_alloc_mtt_range(dev, mtt->order); +@@ -263,6 +267,43 @@ + !mailbox, MLX4_CMD_HW2SW_MPT, MLX4_CMD_TIME_CLASS_B); + } + ++int mlx4_mr_reserve_range(struct mlx4_dev *dev, int cnt, int align, u32 *base_mridx) ++{ ++ struct mlx4_priv *priv = mlx4_priv(dev); ++ u32 mridx; ++ ++ mridx = mlx4_bitmap_alloc_range(&priv->mr_table.mpt_bitmap, cnt, align); ++ if (mridx == -1) ++ return -ENOMEM; ++ ++ *base_mridx = mridx; ++ return 0; ++ ++} ++EXPORT_SYMBOL_GPL(mlx4_mr_reserve_range); ++ ++void mlx4_mr_release_range(struct mlx4_dev *dev, u32 base_mridx, int cnt) ++{ ++ struct mlx4_priv *priv = mlx4_priv(dev); ++ mlx4_bitmap_free_range(&priv->mr_table.mpt_bitmap, base_mridx, cnt); ++} ++EXPORT_SYMBOL_GPL(mlx4_mr_release_range); ++ ++int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd, ++ u64 iova, u64 size, u32 access, int npages, ++ int page_shift, struct mlx4_mr *mr) ++{ ++ mr->iova = iova; ++ mr->size = size; ++ mr->pd = pd; ++ mr->access = access; ++ mr->enabled = 0; ++ mr->key = hw_index_to_key(mridx); ++ ++ return mlx4_mtt_init(dev, npages, page_shift, &mr->mtt); ++} ++EXPORT_SYMBOL_GPL(mlx4_mr_alloc_reserved); ++ + int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, + int npages, int page_shift, struct mlx4_mr *mr) + { +@@ -274,14 +315,8 @@ + if (index == -1) + return -ENOMEM; + +- mr->iova = iova; +- mr->size = size; +- mr->pd = pd; +- mr->access = access; +- mr->enabled = 0; +- mr->key = hw_index_to_key(index); +- +- err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt); ++ err = mlx4_mr_alloc_reserved(dev, index, pd, iova, size, ++ access, npages, page_shift, mr); + if (err) + mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index); + +@@ -289,9 +324,8 @@ + } + EXPORT_SYMBOL_GPL(mlx4_mr_alloc); + +-void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr) ++void mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr) + { +- struct mlx4_priv *priv = mlx4_priv(dev); + int err; + + if (mr->enabled) { +@@ -303,6 +337,13 @@ + } + + mlx4_mtt_cleanup(dev, &mr->mtt); ++} ++EXPORT_SYMBOL_GPL(mlx4_mr_free_reserved); ++ ++void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr) ++{ ++ struct mlx4_priv *priv = mlx4_priv(dev); ++ mlx4_mr_free_reserved(dev, mr); + mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, key_to_hw_index(mr->key)); + } + EXPORT_SYMBOL_GPL(mlx4_mr_free); +@@ -350,7 +391,7 @@ + mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG | + MLX4_MPT_PD_FLAG_RAE); + mpt_entry->mtt_sz = cpu_to_be32((1 << mr->mtt.order) * +- MLX4_MTT_ENTRY_PER_SEG); ++ dev->caps.mtts_per_seg); + } else { + mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS); + } +@@ -391,7 +432,7 @@ + (start_index + npages - 1) / (PAGE_SIZE / sizeof (u64))) + return -EINVAL; + +- if (start_index & (MLX4_MTT_ENTRY_PER_SEG - 1)) ++ if (start_index & (dev->caps.mtts_per_seg - 1)) + return -EINVAL; + + mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->first_seg + +@@ -460,8 +501,11 @@ + struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table; + int err; + ++ if (!is_power_of_2(dev->caps.num_mpts)) ++ return -EINVAL; ++ + err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts, +- ~0, dev->caps.reserved_mrws); ++ ~0, dev->caps.reserved_mrws, 0); + if (err) + return err; + +@@ -525,8 +569,9 @@ + return 0; + } + +-int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, +- int npages, u64 iova, u32 *lkey, u32 *rkey) ++int mlx4_map_phys_fmr_fbo(struct mlx4_dev *dev, struct mlx4_fmr *fmr, ++ u64 *page_list, int npages, u64 iova, u32 fbo, ++ u32 len, u32 *lkey, u32 *rkey, int same_key) + { + u32 key; + int i, err; +@@ -538,7 +583,8 @@ + ++fmr->maps; + + key = key_to_hw_index(fmr->mr.key); +- key += dev->caps.num_mpts; ++ if (!same_key) ++ key += dev->caps.num_mpts; + *lkey = *rkey = fmr->mr.key = hw_index_to_key(key); + + *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW; +@@ -554,8 +600,10 @@ + + fmr->mpt->key = cpu_to_be32(key); + fmr->mpt->lkey = cpu_to_be32(key); +- fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift)); ++ fmr->mpt->length = cpu_to_be64(len); + fmr->mpt->start = cpu_to_be64(iova); ++ fmr->mpt->first_byte_offset = cpu_to_be32(fbo & 0x001fffff); ++ fmr->mpt->flags2 = (fbo ? MLX4_MPT_FLAG2_FBO_EN : 0); + + /* Make MTT entries are visible before setting MPT status */ + wmb(); +@@ -566,6 +614,16 @@ + wmb(); + + return 0; ++} ++EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr_fbo); ++ ++int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, ++ int npages, u64 iova, u32 *lkey, u32 *rkey) ++{ ++ u32 len = npages * (1ull << fmr->page_shift); ++ ++ return mlx4_map_phys_fmr_fbo(dev, fmr, page_list, npages, iova, 0, ++ len, lkey, rkey, 0); + } + EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr); + +@@ -611,6 +669,49 @@ + } + EXPORT_SYMBOL_GPL(mlx4_fmr_alloc); + ++int mlx4_fmr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, ++ u32 pd, u32 access, int max_pages, ++ int max_maps, u8 page_shift, struct mlx4_fmr *fmr) ++{ ++ struct mlx4_priv *priv = mlx4_priv(dev); ++ u64 mtt_seg; ++ int err = -ENOMEM; ++ ++ if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32) ++ return -EINVAL; ++ ++ /* All MTTs must fit in the same page */ ++ if (max_pages * sizeof *fmr->mtts > PAGE_SIZE) ++ return -EINVAL; ++ ++ fmr->page_shift = page_shift; ++ fmr->max_pages = max_pages; ++ fmr->max_maps = max_maps; ++ fmr->maps = 0; ++ ++ err = mlx4_mr_alloc_reserved(dev, mridx, pd, 0, 0, access, max_pages, ++ page_shift, &fmr->mr); ++ if (err) ++ return err; ++ ++ mtt_seg = fmr->mr.mtt.first_seg * dev->caps.mtt_entry_sz; ++ ++ fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table, ++ fmr->mr.mtt.first_seg, ++ &fmr->dma_handle); ++ if (!fmr->mtts) { ++ err = -ENOMEM; ++ goto err_free; ++ } ++ ++ return 0; ++ ++err_free: ++ mlx4_mr_free_reserved(dev, &fmr->mr); ++ return err; ++} ++EXPORT_SYMBOL_GPL(mlx4_fmr_alloc_reserved); ++ + int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr) + { + struct mlx4_priv *priv = mlx4_priv(dev); +@@ -653,6 +754,18 @@ + } + EXPORT_SYMBOL_GPL(mlx4_fmr_free); + ++int mlx4_fmr_free_reserved(struct mlx4_dev *dev, struct mlx4_fmr *fmr) ++{ ++ if (fmr->maps) ++ return -EBUSY; ++ ++ fmr->mr.enabled = 0; ++ mlx4_mr_free_reserved(dev, &fmr->mr); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(mlx4_fmr_free_reserved); ++ + int mlx4_SYNC_TPT(struct mlx4_dev *dev) + { + return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, 1000); +diff -r 4e706462aff6 drivers/net/mlx4/pd.c +--- a/drivers/net/mlx4/pd.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/pd.c Tue Oct 06 11:20:51 2009 +0100 +@@ -62,7 +62,7 @@ + struct mlx4_priv *priv = mlx4_priv(dev); + + return mlx4_bitmap_init(&priv->pd_bitmap, dev->caps.num_pds, +- (1 << 24) - 1, dev->caps.reserved_pds); ++ (1 << 24) - 1, dev->caps.reserved_pds, 0); + } + + void mlx4_cleanup_pd_table(struct mlx4_dev *dev) +@@ -100,7 +100,7 @@ + + return mlx4_bitmap_init(&mlx4_priv(dev)->uar_table.bitmap, + dev->caps.num_uars, dev->caps.num_uars - 1, +- max(128, dev->caps.reserved_uars)); ++ max(128, dev->caps.reserved_uars), 0); + } + + void mlx4_cleanup_uar_table(struct mlx4_dev *dev) +diff -r 4e706462aff6 drivers/net/mlx4/port.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/port.c Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,320 @@ ++/* ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "mlx4.h" ++ ++int mlx4_ib_set_4k_mtu = 0; ++module_param_named(set_4k_mtu, mlx4_ib_set_4k_mtu, int, 0444); ++MODULE_PARM_DESC(set_4k_mtu, "attempt to set 4K MTU to all ConnectX ports"); ++ ++void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table) ++{ ++ int i; ++ ++ sema_init(&table->mac_sem, 1); ++ for (i = 0; i < MLX4_MAX_MAC_NUM; i++) { ++ table->entries[i] = 0; ++ table->refs[i] = 0; ++ } ++ table->max = 1 << dev->caps.log_num_macs; ++ table->total = 0; ++} ++ ++void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table) ++{ ++ int i; ++ ++ sema_init(&table->vlan_sem, 1); ++ for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) { ++ table->entries[i] = 0; ++ table->refs[i] = 0; ++ } ++ table->max = 1 << dev->caps.log_num_vlans; ++ table->total = 0; ++} ++ ++static int mlx4_SET_PORT_mac_table(struct mlx4_dev *dev, u8 port, ++ __be64 *entries) ++{ ++ struct mlx4_cmd_mailbox *mailbox; ++ u32 in_mod; ++ int err; ++ ++ mailbox = mlx4_alloc_cmd_mailbox(dev); ++ if (IS_ERR(mailbox)) ++ return PTR_ERR(mailbox); ++ ++ memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE); ++ ++ in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port; ++ err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, ++ MLX4_CMD_TIME_CLASS_B); ++ ++ mlx4_free_cmd_mailbox(dev, mailbox); ++ return err; ++} ++ ++int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index) ++{ ++ struct mlx4_mac_table *table = &mlx4_priv(dev)->port[port].mac_table; ++ int i, err = 0; ++ int free = -1; ++ u64 valid = 1; ++ ++ mlx4_dbg(dev, "Registering mac : 0x%llx\n", mac); ++ down(&table->mac_sem); ++ for (i = 0; i < MLX4_MAX_MAC_NUM - 1; i++) { ++ if (free < 0 && !table->refs[i]) { ++ free = i; ++ continue; ++ } ++ ++ if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) { ++ /* Mac already registered, increase refernce count */ ++ *index = i; ++ ++table->refs[i]; ++ goto out; ++ } ++ } ++ mlx4_dbg(dev, "Free mac index is %d\n", free); ++ ++ if (table->total == table->max) { ++ /* No free mac entries */ ++ err = -ENOSPC; ++ goto out; ++ } ++ ++ /* Register new MAC */ ++ table->refs[free] = 1; ++ table->entries[free] = cpu_to_be64(mac | valid << MLX4_MAC_VALID_SHIFT); ++ ++ err = mlx4_SET_PORT_mac_table(dev, port, table->entries); ++ if (unlikely(err)) { ++ mlx4_err(dev, "Failed adding mac: 0x%llx\n", mac); ++ table->refs[free] = 0; ++ table->entries[free] = 0; ++ goto out; ++ } ++ ++ *index = free; ++ ++table->total; ++out: ++ up(&table->mac_sem); ++ return err; ++} ++EXPORT_SYMBOL_GPL(mlx4_register_mac); ++ ++void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index) ++{ ++ struct mlx4_mac_table *table = &mlx4_priv(dev)->port[port].mac_table; ++ ++ down(&table->mac_sem); ++ if (!table->refs[index]) { ++ mlx4_warn(dev, "No mac entry for index %d\n", index); ++ goto out; ++ } ++ if (--table->refs[index]) { ++ mlx4_warn(dev, "Have more references for index %d," ++ "no need to modify mac table\n", index); ++ goto out; ++ } ++ table->entries[index] = 0; ++ mlx4_SET_PORT_mac_table(dev, port, table->entries); ++ --table->total; ++out: ++ up(&table->mac_sem); ++} ++EXPORT_SYMBOL_GPL(mlx4_unregister_mac); ++ ++static int mlx4_SET_PORT_vlan_table(struct mlx4_dev *dev, u8 port, ++ __be32 *entries) ++{ ++ struct mlx4_cmd_mailbox *mailbox; ++ u32 in_mod; ++ int err; ++ ++ mailbox = mlx4_alloc_cmd_mailbox(dev); ++ if (IS_ERR(mailbox)) ++ return PTR_ERR(mailbox); ++ ++ memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE); ++ in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port; ++ err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, ++ MLX4_CMD_TIME_CLASS_B); ++ ++ mlx4_free_cmd_mailbox(dev, mailbox); ++ ++ return err; ++} ++ ++int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index) ++{ ++ struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table; ++ int i, err = 0; ++ int free = -1; ++ ++ down(&table->vlan_sem); ++ for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) { ++ if (free < 0 && (table->refs[i] == 0)) { ++ free = i; ++ continue; ++ } ++ ++ if (table->refs[i] && ++ (vlan == (MLX4_VLAN_MASK & ++ be32_to_cpu(table->entries[i])))) { ++ /* Vlan already registered, increase refernce count */ ++ *index = i; ++ ++table->refs[i]; ++ goto out; ++ } ++ } ++ ++ if (table->total == table->max) { ++ /* No free vlan entries */ ++ err = -ENOSPC; ++ goto out; ++ } ++ ++ /* Register new MAC */ ++ table->refs[free] = 1; ++ table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID); ++ ++ err = mlx4_SET_PORT_vlan_table(dev, port, table->entries); ++ if (unlikely(err)) { ++ mlx4_warn(dev, "Failed adding vlan: %u\n", vlan); ++ table->refs[free] = 0; ++ table->entries[free] = 0; ++ goto out; ++ } ++ ++ *index = free; ++ ++table->total; ++out: ++ up(&table->vlan_sem); ++ return err; ++} ++EXPORT_SYMBOL_GPL(mlx4_register_vlan); ++ ++void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index) ++{ ++ struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table; ++ ++ if (index < MLX4_VLAN_REGULAR) { ++ mlx4_warn(dev, "Trying to free special vlan index %d\n", index); ++ return; ++ } ++ ++ down(&table->vlan_sem); ++ if (!table->refs[index]) { ++ mlx4_warn(dev, "No vlan entry for index %d\n", index); ++ goto out; ++ } ++ if (--table->refs[index]) { ++ mlx4_dbg(dev, "Have more references for index %d," ++ "no need to modify vlan table\n", index); ++ goto out; ++ } ++ table->entries[index] = 0; ++ mlx4_SET_PORT_vlan_table(dev, port, table->entries); ++ --table->total; ++out: ++ up(&table->vlan_sem); ++} ++EXPORT_SYMBOL_GPL(mlx4_unregister_vlan); ++ ++int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps) ++{ ++ struct mlx4_cmd_mailbox *inmailbox, *outmailbox; ++ u8 *inbuf, *outbuf; ++ int err; ++ ++ inmailbox = mlx4_alloc_cmd_mailbox(dev); ++ if (IS_ERR(inmailbox)) ++ return PTR_ERR(inmailbox); ++ ++ outmailbox = mlx4_alloc_cmd_mailbox(dev); ++ if (IS_ERR(outmailbox)) { ++ mlx4_free_cmd_mailbox(dev, inmailbox); ++ return PTR_ERR(outmailbox); ++ } ++ ++ inbuf = inmailbox->buf; ++ outbuf = outmailbox->buf; ++ memset(inbuf, 0, 256); ++ memset(outbuf, 0, 256); ++ inbuf[0] = 1; ++ inbuf[1] = 1; ++ inbuf[2] = 1; ++ inbuf[3] = 1; ++ *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015); ++ *(__be32 *) (&inbuf[20]) = cpu_to_be32(port); ++ ++ err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3, ++ MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C); ++ if (!err) ++ *caps = *(__be32 *) (outbuf + 84); ++ mlx4_free_cmd_mailbox(dev, inmailbox); ++ mlx4_free_cmd_mailbox(dev, outmailbox); ++ return err; ++} ++ ++int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port) ++{ ++ struct mlx4_cmd_mailbox *mailbox; ++ int err = 0; ++ ++ mailbox = mlx4_alloc_cmd_mailbox(dev); ++ if (IS_ERR(mailbox)) ++ return PTR_ERR(mailbox); ++ ++ memset(mailbox->buf, 0, 256); ++ if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) ++ goto out; ++ ++ if (mlx4_ib_set_4k_mtu) ++ ((__be32 *) mailbox->buf)[0] |= cpu_to_be32((1 << 22) | (1 << 21) | (5 << 12) | (2 << 4)); ++ ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port]; ++ ++ err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT, ++ MLX4_CMD_TIME_CLASS_B); ++ ++out: ++ mlx4_free_cmd_mailbox(dev, mailbox); ++ return err; ++} +diff -r 4e706462aff6 drivers/net/mlx4/profile.c +--- a/drivers/net/mlx4/profile.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/profile.c Tue Oct 06 11:20:51 2009 +0100 +@@ -98,7 +98,7 @@ + profile[MLX4_RES_EQ].size = dev_cap->eqc_entry_sz; + profile[MLX4_RES_DMPT].size = dev_cap->dmpt_entry_sz; + profile[MLX4_RES_CMPT].size = dev_cap->cmpt_entry_sz; +- profile[MLX4_RES_MTT].size = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz; ++ profile[MLX4_RES_MTT].size = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz; + profile[MLX4_RES_MCG].size = MLX4_MGM_ENTRY_SIZE; + + profile[MLX4_RES_QP].num = request->num_qp; +diff -r 4e706462aff6 drivers/net/mlx4/qp.c +--- a/drivers/net/mlx4/qp.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/qp.c Tue Oct 06 11:20:51 2009 +0100 +@@ -147,19 +147,42 @@ + } + EXPORT_SYMBOL_GPL(mlx4_qp_modify); + +-int mlx4_qp_alloc(struct mlx4_dev *dev, int sqpn, struct mlx4_qp *qp) ++int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base) ++{ ++ struct mlx4_priv *priv = mlx4_priv(dev); ++ struct mlx4_qp_table *qp_table = &priv->qp_table; ++ int qpn; ++ ++ qpn = mlx4_bitmap_alloc_range(&qp_table->bitmap, cnt, align); ++ if (qpn == -1) ++ return -ENOMEM; ++ ++ *base = qpn; ++ return 0; ++} ++EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range); ++ ++void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt) ++{ ++ struct mlx4_priv *priv = mlx4_priv(dev); ++ struct mlx4_qp_table *qp_table = &priv->qp_table; ++ if (base_qpn < dev->caps.sqp_start + 8) ++ return; ++ ++ mlx4_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt); ++} ++EXPORT_SYMBOL_GPL(mlx4_qp_release_range); ++ ++int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp) + { + struct mlx4_priv *priv = mlx4_priv(dev); + struct mlx4_qp_table *qp_table = &priv->qp_table; + int err; + +- if (sqpn) +- qp->qpn = sqpn; +- else { +- qp->qpn = mlx4_bitmap_alloc(&qp_table->bitmap); +- if (qp->qpn == -1) +- return -ENOMEM; +- } ++ if (!qpn) ++ return -EINVAL; ++ ++ qp->qpn = qpn; + + err = mlx4_table_get(dev, &qp_table->qp_table, qp->qpn); + if (err) +@@ -208,9 +231,6 @@ + mlx4_table_put(dev, &qp_table->qp_table, qp->qpn); + + err_out: +- if (!sqpn) +- mlx4_bitmap_free(&qp_table->bitmap, qp->qpn); +- + return err; + } + EXPORT_SYMBOL_GPL(mlx4_qp_alloc); +@@ -240,21 +260,21 @@ + mlx4_table_put(dev, &qp_table->auxc_table, qp->qpn); + mlx4_table_put(dev, &qp_table->qp_table, qp->qpn); + +- if (qp->qpn >= dev->caps.sqp_start + 8) +- mlx4_bitmap_free(&qp_table->bitmap, qp->qpn); + } + EXPORT_SYMBOL_GPL(mlx4_qp_free); + + static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn) + { +- return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP, +- MLX4_CMD_TIME_CLASS_B); ++ return mlx4_cmd(dev, 0, base_qpn, ++ (dev->caps.flags & MLX4_DEV_CAP_FLAG_RAW_ETY) ? 4 : 0, ++ MLX4_CMD_CONF_SPECIAL_QP, MLX4_CMD_TIME_CLASS_B); + } + + int mlx4_init_qp_table(struct mlx4_dev *dev) + { + struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table; + int err; ++ int reserved_from_top = 0; + + spin_lock_init(&qp_table->lock); + INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC); +@@ -263,10 +283,43 @@ + * We reserve 2 extra QPs per port for the special QPs. The + * block of special QPs must be aligned to a multiple of 8, so + * round up. ++ * We also reserve the MSB of the 24-bit QP number to indicate ++ * an XRC qp. + */ +- dev->caps.sqp_start = ALIGN(dev->caps.reserved_qps, 8); ++ dev->caps.sqp_start = ++ ALIGN(dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 8); ++ ++ { ++ int sort[MLX4_QP_REGION_COUNT]; ++ int i, j, tmp; ++ int last_base = dev->caps.num_qps; ++ ++ for (i = 1; i < MLX4_QP_REGION_COUNT; ++i) ++ sort[i] = i; ++ ++ for (i = MLX4_QP_REGION_COUNT; i > 0; --i) { ++ for (j = 2; j < i; ++j) { ++ if (dev->caps.reserved_qps_cnt[sort[j]] > ++ dev->caps.reserved_qps_cnt[sort[j - 1]]) { ++ tmp = sort[j]; ++ sort[j] = sort[j - 1]; ++ sort[j - 1] = tmp; ++ } ++ } ++ } ++ ++ for (i = 1; i < MLX4_QP_REGION_COUNT; ++i) { ++ last_base -= dev->caps.reserved_qps_cnt[sort[i]]; ++ dev->caps.reserved_qps_base[sort[i]] = last_base; ++ reserved_from_top += ++ dev->caps.reserved_qps_cnt[sort[i]]; ++ } ++ ++ } ++ + err = mlx4_bitmap_init(&qp_table->bitmap, dev->caps.num_qps, +- (1 << 24) - 1, dev->caps.sqp_start + 8); ++ (1 << 23) - 1, dev->caps.sqp_start + 8, ++ reserved_from_top); + if (err) + return err; + +@@ -278,6 +331,20 @@ + mlx4_CONF_SPECIAL_QP(dev, 0); + mlx4_bitmap_cleanup(&mlx4_priv(dev)->qp_table.bitmap); + } ++ ++int mlx4_qp_get_region(struct mlx4_dev *dev, ++ enum qp_region region, ++ int *base_qpn, int *cnt) ++{ ++ if ((region < 0) || (region >= MLX4_QP_REGION_COUNT)) ++ return -EINVAL; ++ ++ *base_qpn = dev->caps.reserved_qps_base[region]; ++ *cnt = dev->caps.reserved_qps_cnt[region]; ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(mlx4_qp_get_region); + + int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, + struct mlx4_qp_context *context) +diff -r 4e706462aff6 drivers/net/mlx4/srq.c +--- a/drivers/net/mlx4/srq.c Tue Oct 06 11:18:32 2009 +0100 ++++ b/drivers/net/mlx4/srq.c Tue Oct 06 11:20:51 2009 +0100 +@@ -41,20 +41,20 @@ + struct mlx4_srq_context { + __be32 state_logsize_srqn; + u8 logstride; +- u8 reserved1[3]; +- u8 pg_offset; +- u8 reserved2[3]; +- u32 reserved3; ++ u8 reserved1; ++ __be16 xrc_domain; ++ __be32 pg_offset_cqn; ++ u32 reserved2; + u8 log_page_size; +- u8 reserved4[2]; ++ u8 reserved3[2]; + u8 mtt_base_addr_h; + __be32 mtt_base_addr_l; + __be32 pd; + __be16 limit_watermark; + __be16 wqe_cnt; +- u16 reserved5; ++ u16 reserved4; + __be16 wqe_counter; +- u32 reserved6; ++ u32 reserved5; + __be64 db_rec_addr; + }; + +@@ -65,7 +65,8 @@ + + spin_lock(&srq_table->lock); + +- srq = radix_tree_lookup(&srq_table->tree, srqn & (dev->caps.num_srqs - 1)); ++ srq = radix_tree_lookup(&dev->srq_table_tree, ++ srqn & (dev->caps.num_srqs - 1)); + if (srq) + atomic_inc(&srq->refcount); + +@@ -110,8 +111,8 @@ + MLX4_CMD_TIME_CLASS_A); + } + +-int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt, +- u64 db_rec, struct mlx4_srq *srq) ++int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcd, ++ struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq) + { + struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; + struct mlx4_cmd_mailbox *mailbox; +@@ -132,7 +133,7 @@ + goto err_put; + + spin_lock_irq(&srq_table->lock); +- err = radix_tree_insert(&srq_table->tree, srq->srqn, srq); ++ err = radix_tree_insert(&dev->srq_table_tree, srq->srqn, srq); + spin_unlock_irq(&srq_table->lock); + if (err) + goto err_cmpt_put; +@@ -149,6 +150,8 @@ + srq_context->state_logsize_srqn = cpu_to_be32((ilog2(srq->max) << 24) | + srq->srqn); + srq_context->logstride = srq->wqe_shift - 4; ++ srq_context->xrc_domain = cpu_to_be16(xrcd); ++ srq_context->pg_offset_cqn = cpu_to_be32(cqn & 0xffffff); + srq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT; + + mtt_addr = mlx4_mtt_addr(dev, mtt); +@@ -169,7 +172,7 @@ + + err_radix: + spin_lock_irq(&srq_table->lock); +- radix_tree_delete(&srq_table->tree, srq->srqn); ++ radix_tree_delete(&dev->srq_table_tree, srq->srqn); + spin_unlock_irq(&srq_table->lock); + + err_cmpt_put: +@@ -185,18 +188,29 @@ + } + EXPORT_SYMBOL_GPL(mlx4_srq_alloc); + +-void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq) ++void mlx4_srq_invalidate(struct mlx4_dev *dev, struct mlx4_srq *srq) + { +- struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; + int err; + + err = mlx4_HW2SW_SRQ(dev, NULL, srq->srqn); + if (err) + mlx4_warn(dev, "HW2SW_SRQ failed (%d) for SRQN %06x\n", err, srq->srqn); ++} ++EXPORT_SYMBOL_GPL(mlx4_srq_invalidate); ++ ++void mlx4_srq_remove(struct mlx4_dev *dev, struct mlx4_srq *srq) ++{ ++ struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; + + spin_lock_irq(&srq_table->lock); +- radix_tree_delete(&srq_table->tree, srq->srqn); ++ radix_tree_delete(&dev->srq_table_tree, srq->srqn); + spin_unlock_irq(&srq_table->lock); ++} ++EXPORT_SYMBOL_GPL(mlx4_srq_remove); ++ ++void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq) ++{ ++ struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; + + if (atomic_dec_and_test(&srq->refcount)) + complete(&srq->free); +@@ -242,10 +256,10 @@ + int err; + + spin_lock_init(&srq_table->lock); +- INIT_RADIX_TREE(&srq_table->tree, GFP_ATOMIC); ++ INIT_RADIX_TREE(&dev->srq_table_tree, GFP_ATOMIC); + + err = mlx4_bitmap_init(&srq_table->bitmap, dev->caps.num_srqs, +- dev->caps.num_srqs - 1, dev->caps.reserved_srqs); ++ dev->caps.num_srqs - 1, dev->caps.reserved_srqs, 0); + if (err) + return err; + +diff -r 4e706462aff6 drivers/net/mlx4/xrcd.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/mlx4/xrcd.c Tue Oct 06 11:20:51 2009 +0100 +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. ++ * Copyright (c) 2007 Mellanox Technologies. All rights reserved. ++ * ++ * This software is available to you under a choice of one of two ++ * licenses. You may choose to be licensed under the terms of the GNU ++ * General Public License (GPL) Version 2, available from the file ++ * COPYING in the main directory of this source tree, or the ++ * OpenIB.org BSD license below: ++ * ++ * Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * - Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS ++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ */ ++ ++#include ++#include ++ ++#include "mlx4.h" ++ ++int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn) ++{ ++ struct mlx4_priv *priv = mlx4_priv(dev); ++ ++ *xrcdn = mlx4_bitmap_alloc(&priv->xrcd_bitmap); ++ if (*xrcdn == -1) ++ return -ENOMEM; ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(mlx4_xrcd_alloc); ++ ++void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn) ++{ ++ mlx4_bitmap_free(&mlx4_priv(dev)->xrcd_bitmap, xrcdn); ++} ++EXPORT_SYMBOL_GPL(mlx4_xrcd_free); ++ ++int __devinit mlx4_init_xrcd_table(struct mlx4_dev *dev) ++{ ++ struct mlx4_priv *priv = mlx4_priv(dev); ++ ++ return mlx4_bitmap_init(&priv->xrcd_bitmap, (1 << 16), ++ (1 << 16) - 1, dev->caps.reserved_xrcds + 1, 0); ++} ++ ++void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev) ++{ ++ mlx4_bitmap_cleanup(&mlx4_priv(dev)->xrcd_bitmap); ++} ++ ++ +diff -r 4e706462aff6 include/linux/mlx4/cmd.h +--- a/include/linux/mlx4/cmd.h Tue Oct 06 11:18:32 2009 +0100 ++++ b/include/linux/mlx4/cmd.h Tue Oct 06 11:20:51 2009 +0100 +@@ -55,6 +55,7 @@ + MLX4_CMD_CLOSE_PORT = 0xa, + MLX4_CMD_QUERY_HCA = 0xb, + MLX4_CMD_QUERY_PORT = 0x43, ++ MLX4_CMD_SENSE_PORT = 0x4d, + MLX4_CMD_SET_PORT = 0xc, + MLX4_CMD_ACCESS_DDR = 0x2e, + MLX4_CMD_MAP_ICM = 0xffa, +@@ -132,6 +133,15 @@ + MLX4_MAILBOX_SIZE = 4096 + }; + ++enum { ++ /* set port opcode modifiers */ ++ MLX4_SET_PORT_GENERAL = 0x0, ++ MLX4_SET_PORT_RQP_CALC = 0x1, ++ MLX4_SET_PORT_MAC_TABLE = 0x2, ++ MLX4_SET_PORT_VLAN_TABLE = 0x3, ++ MLX4_SET_PORT_PRIO_MAP = 0x4, ++}; ++ + struct mlx4_dev; + + struct mlx4_cmd_mailbox { +diff -r 4e706462aff6 include/linux/mlx4/device.h +--- a/include/linux/mlx4/device.h Tue Oct 06 11:18:32 2009 +0100 ++++ b/include/linux/mlx4/device.h Tue Oct 06 11:20:51 2009 +0100 +@@ -56,10 +56,13 @@ + MLX4_DEV_CAP_FLAG_RC = 1 << 0, + MLX4_DEV_CAP_FLAG_UC = 1 << 1, + MLX4_DEV_CAP_FLAG_UD = 1 << 2, ++ MLX4_DEV_CAP_FLAG_XRC = 1 << 3, + MLX4_DEV_CAP_FLAG_SRQ = 1 << 6, + MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7, + MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8, + MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9, ++ MLX4_DEV_CAP_FLAG_DPDP = 1 << 12, ++ MLX4_DEV_CAP_FLAG_RAW_ETY = 1 << 13, + MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16, + MLX4_DEV_CAP_FLAG_APM = 1 << 17, + MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18, +@@ -145,6 +148,27 @@ + MLX4_MTT_FLAG_PRESENT = 1 + }; + ++enum qp_region { ++ MLX4_QP_REGION_FW = 0, ++ MLX4_QP_REGION_ETH_ADDR, ++ MLX4_QP_REGION_FC_ADDR, ++ MLX4_QP_REGION_COUNT ++}; ++ ++enum mlx4_port_type { ++ MLX4_PORT_TYPE_IB = 1, ++ MLX4_PORT_TYPE_ETH = 2, ++ MLX4_PORT_TYPE_AUTO = 3 ++}; ++ ++enum mlx4_special_vlan_idx { ++ MLX4_NO_VLAN_IDX = 0, ++ MLX4_VLAN_MISS_IDX, ++ MLX4_VLAN_REGULAR ++}; ++ ++#define MLX4_LEAST_ATTACHED_VECTOR 0xffffffff ++ + static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) + { + return (major << 32) | (minor << 16) | subminor; +@@ -154,9 +178,16 @@ + u64 fw_ver; + int num_ports; + int vl_cap[MLX4_MAX_PORTS + 1]; +- int mtu_cap[MLX4_MAX_PORTS + 1]; ++ int ib_mtu_cap[MLX4_MAX_PORTS + 1]; ++ __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; ++ u64 def_mac[MLX4_MAX_PORTS + 1]; ++ int eth_mtu_cap[MLX4_MAX_PORTS + 1]; + int gid_table_len[MLX4_MAX_PORTS + 1]; + int pkey_table_len[MLX4_MAX_PORTS + 1]; ++ int trans_type[MLX4_MAX_PORTS + 1]; ++ int vendor_oui[MLX4_MAX_PORTS + 1]; ++ int wavelength[MLX4_MAX_PORTS + 1]; ++ u64 trans_code[MLX4_MAX_PORTS + 1]; + int local_ca_ack_delay; + int num_uars; + int bf_reg_size; +@@ -169,7 +200,6 @@ + int max_rq_desc_sz; + int max_qp_init_rdma; + int max_qp_dest_rdma; +- int reserved_qps; + int sqp_start; + int num_srqs; + int max_srq_wqes; +@@ -180,8 +210,10 @@ + int reserved_cqs; + int num_eqs; + int reserved_eqs; ++ int num_comp_vectors; + int num_mpts; + int num_mtt_segs; ++ int mtts_per_seg; + int fmr_reserved_mtts; + int reserved_mtts; + int reserved_mrws; +@@ -193,6 +225,8 @@ + int num_pds; + int reserved_pds; + int mtt_entry_sz; ++ int reserved_xrcds; ++ int max_xrcds; + u32 max_msg_sz; + u32 page_size_cap; + u32 flags; +@@ -201,6 +235,16 @@ + u16 stat_rate_support; + u8 port_width_cap[MLX4_MAX_PORTS + 1]; + int max_gso_sz; ++ int reserved_qps_cnt[MLX4_QP_REGION_COUNT]; ++ int reserved_qps; ++ int reserved_qps_base[MLX4_QP_REGION_COUNT]; ++ int log_num_macs; ++ int log_num_vlans; ++ int log_num_prios; ++ enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; ++ u8 supported_type[MLX4_MAX_PORTS + 1]; ++ u32 port_mask; ++ enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; + }; + + struct mlx4_buf_list { +@@ -293,6 +337,7 @@ + int arm_sn; + + int cqn; ++ int comp_eq_idx; + + atomic_t refcount; + struct completion free; +@@ -337,6 +382,7 @@ + unsigned long flags; + struct mlx4_caps caps; + struct radix_tree_root qp_table_tree; ++ struct radix_tree_root srq_table_tree; + u32 rev_id; + char board_id[MLX4_BOARD_ID_LEN]; + }; +@@ -355,6 +401,19 @@ + u64 si_guid; + }; + ++static inline void mlx4_query_steer_cap(struct mlx4_dev *dev, int *log_mac, ++ int *log_vlan, int *log_prio) ++{ ++ *log_mac = dev->caps.log_num_macs; ++ *log_vlan = dev->caps.log_num_vlans; ++ *log_prio = dev->caps.log_num_prios; ++} ++ ++#define mlx4_foreach_port(port, dev, type) \ ++ for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ ++ if ((type == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \ ++ ~(dev)->caps.port_mask) & 1 << ((port)-1)) ++ + int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, + struct mlx4_buf *buf); + void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); +@@ -370,6 +429,9 @@ + int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); + void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); + ++int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); ++void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); ++ + int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); + void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); + +@@ -378,8 +440,14 @@ + void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); + u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); + ++int mlx4_mr_reserve_range(struct mlx4_dev *dev, int cnt, int align, u32 *base_mridx); ++void mlx4_mr_release_range(struct mlx4_dev *dev, u32 base_mridx, int cnt); ++int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd, ++ u64 iova, u64 size, u32 access, int npages, ++ int page_shift, struct mlx4_mr *mr); + int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, + int npages, int page_shift, struct mlx4_mr *mr); ++void mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr); + void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); + int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); + int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, +@@ -397,14 +465,17 @@ + + int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, + struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, +- int collapsed); ++ unsigned vector, int collapsed); + void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); + +-int mlx4_qp_alloc(struct mlx4_dev *dev, int sqpn, struct mlx4_qp *qp); ++int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); ++void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); ++ ++int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); + void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); + +-int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt, +- u64 db_rec, struct mlx4_srq *srq); ++int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcd, ++ struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); + void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); + int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); + int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); +@@ -416,14 +487,29 @@ + int block_mcast_loopback); + int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]); + ++int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index); ++void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index); ++ ++int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); ++void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); ++ ++int mlx4_map_phys_fmr_fbo(struct mlx4_dev *dev, struct mlx4_fmr *fmr, ++ u64 *page_list, int npages, u64 iova, u32 fbo, ++ u32 len, u32 *lkey, u32 *rkey, int same_key); + int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, + int npages, u64 iova, u32 *lkey, u32 *rkey); ++int mlx4_fmr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd, ++ u32 access, int max_pages, int max_maps, ++ u8 page_shift, struct mlx4_fmr *fmr); + int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, + int max_maps, u8 page_shift, struct mlx4_fmr *fmr); + int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); + void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, + u32 *lkey, u32 *rkey); ++int mlx4_fmr_free_reserved(struct mlx4_dev *dev, struct mlx4_fmr *fmr); + int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); + int mlx4_SYNC_TPT(struct mlx4_dev *dev); ++int mlx4_query_diag_counters(struct mlx4_dev *mlx4_dev, int array_length, ++ u8 op_modifier, u32 in_offset[], u32 counter_out[]); + + #endif /* MLX4_DEVICE_H */ +diff -r 4e706462aff6 include/linux/mlx4/driver.h +--- a/include/linux/mlx4/driver.h Tue Oct 06 11:18:32 2009 +0100 ++++ b/include/linux/mlx4/driver.h Tue Oct 06 11:20:51 2009 +0100 +@@ -44,15 +44,22 @@ + MLX4_DEV_EVENT_PORT_REINIT, + }; + ++enum mlx4_query_reply { ++ MLX4_QUERY_NOT_MINE = -1, ++ MLX4_QUERY_MINE_NOPORT = 0 ++}; ++ + struct mlx4_interface { + void * (*add) (struct mlx4_dev *dev); + void (*remove)(struct mlx4_dev *dev, void *context); + void (*event) (struct mlx4_dev *dev, void *context, + enum mlx4_dev_event event, int port); ++ enum mlx4_query_reply (*query) (void *context, void *); + struct list_head list; + }; + + int mlx4_register_interface(struct mlx4_interface *intf); + void mlx4_unregister_interface(struct mlx4_interface *intf); ++struct mlx4_dev *mlx4_query_interface(void *, int *port); + + #endif /* MLX4_DRIVER_H */ +diff -r 4e706462aff6 include/linux/mlx4/qp.h +--- a/include/linux/mlx4/qp.h Tue Oct 06 11:18:32 2009 +0100 ++++ b/include/linux/mlx4/qp.h Tue Oct 06 11:20:51 2009 +0100 +@@ -74,6 +74,7 @@ + MLX4_QP_ST_UC = 0x1, + MLX4_QP_ST_RD = 0x2, + MLX4_QP_ST_UD = 0x3, ++ MLX4_QP_ST_XRC = 0x6, + MLX4_QP_ST_MLX = 0x7 + }; + +@@ -136,7 +137,7 @@ + __be32 ssn; + __be32 params2; + __be32 rnr_nextrecvpsn; +- __be32 srcd; ++ __be32 xrcd; + __be32 cqn_recv; + __be64 db_rec_addr; + __be32 qkey; +@@ -151,7 +152,16 @@ + u8 reserved4[2]; + u8 mtt_base_addr_h; + __be32 mtt_base_addr_l; +- u32 reserved5[10]; ++ u8 VE; ++ u8 reserved5; ++ __be16 VFT_id_prio; ++ u8 reserved6; ++ u8 exch_size; ++ __be16 exch_base; ++ u8 VFT_hop_cnt; ++ u8 my_fc_id_idx; ++ __be16 reserved7; ++ u32 reserved8[7]; + }; + + /* Which firmware version adds support for NEC (NoErrorCompletion) bit */ +@@ -165,7 +175,6 @@ + MLX4_WQE_CTRL_IP_CSUM = 1 << 4, + MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, + MLX4_WQE_CTRL_INS_VLAN = 1 << 6, +- MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, + }; + + struct mlx4_wqe_ctrl_seg { +@@ -192,7 +201,8 @@ + + enum { + MLX4_WQE_MLX_VL15 = 1 << 17, +- MLX4_WQE_MLX_SLR = 1 << 16 ++ MLX4_WQE_MLX_SLR = 1 << 16, ++ MLX4_WQE_MLX_ICRC = 1 << 4 + }; + + struct mlx4_wqe_mlx_seg { +@@ -318,4 +328,8 @@ + + void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp); + ++int mlx4_qp_get_region(struct mlx4_dev *dev, ++ enum qp_region region, ++ int *base_qpn, int *cnt); ++ + #endif /* MLX4_QP_H */ +diff -r 4e706462aff6 include/linux/mlx4/srq.h +--- a/include/linux/mlx4/srq.h Tue Oct 06 11:18:32 2009 +0100 ++++ b/include/linux/mlx4/srq.h Tue Oct 06 11:20:51 2009 +0100 +@@ -33,10 +33,22 @@ + #ifndef MLX4_SRQ_H + #define MLX4_SRQ_H + ++#include ++#include ++ + struct mlx4_wqe_srq_next_seg { + u16 reserved1; + __be16 next_wqe_index; + u32 reserved2[3]; + }; + ++void mlx4_srq_invalidate(struct mlx4_dev *dev, struct mlx4_srq *srq); ++void mlx4_srq_remove(struct mlx4_dev *dev, struct mlx4_srq *srq); ++ ++static inline struct mlx4_srq *__mlx4_srq_lookup(struct mlx4_dev *dev, u32 srqn) ++{ ++ return radix_tree_lookup(&dev->srq_table_tree, ++ srqn & (dev->caps.num_srqs - 1)); ++} ++ + #endif /* MLX4_SRQ_H */ diff --git a/master/mlnx_en-fix-warnings.patch b/master/mlnx_en-fix-warnings.patch new file mode 100644 index 0000000..994e338 --- /dev/null +++ b/master/mlnx_en-fix-warnings.patch @@ -0,0 +1,65 @@ +diff -r 5f6ac197b2f4 drivers/net/mlx4/en_rx.c +--- a/drivers/net/mlx4/en_rx.c Tue Oct 06 11:21:21 2009 +0100 ++++ b/drivers/net/mlx4/en_rx.c Tue Oct 06 11:26:07 2009 +0100 +@@ -258,7 +258,6 @@ + ring->prod++; + } + } +-out: + return 0; + } + +diff -r 5f6ac197b2f4 drivers/net/mlx4/en_tx.c +--- a/drivers/net/mlx4/en_tx.c Tue Oct 06 11:21:21 2009 +0100 ++++ b/drivers/net/mlx4/en_tx.c Tue Oct 06 11:26:07 2009 +0100 +@@ -620,7 +620,7 @@ + tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; + } + +-int mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb) ++u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb) + { + struct mlx4_en_priv *priv = netdev_priv(dev); + u16 vlan_tag = 0; +diff -r 5f6ac197b2f4 drivers/net/mlx4/mlx4.h +--- a/drivers/net/mlx4/mlx4.h Tue Oct 06 11:21:21 2009 +0100 ++++ b/drivers/net/mlx4/mlx4.h Tue Oct 06 11:26:07 2009 +0100 +@@ -258,7 +258,7 @@ + + struct mlx4_mac_table { + #define MLX4_MAX_MAC_NUM 128 +-#define MLX4_MAC_MASK 0xffffffffffff ++#define MLX4_MAC_MASK 0xffffffffffffULL + #define MLX4_MAC_VALID_SHIFT 63 + #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) + __be64 entries[MLX4_MAX_MAC_NUM]; +diff -r 5f6ac197b2f4 drivers/net/mlx4/mlx4_en.h +--- a/drivers/net/mlx4/mlx4_en.h Tue Oct 06 11:21:21 2009 +0100 ++++ b/drivers/net/mlx4/mlx4_en.h Tue Oct 06 11:26:07 2009 +0100 +@@ -163,7 +163,7 @@ + #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) + + #define MLX4_EN_MIN_MTU 46 +-#define ETH_BCAST 0xffffffffffff ++#define ETH_BCAST 0xffffffffffffULL + + #ifdef MLX4_EN_PERF_STAT + /* Number of samples to 'average' */ +@@ -203,7 +203,7 @@ + */ + #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) + #define XNOR(x, y) (!(x) == !(y)) +-#define ILLEGAL_MAC(addr) (addr == 0xffffffffffff || addr == 0x0) ++#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0) + + + struct mlx4_en_tx_info { +@@ -578,7 +578,7 @@ + void mlx4_en_poll_tx_cq(unsigned long data); + void mlx4_en_tx_irq(struct mlx4_cq *mcq); + int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); +-int mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb); ++u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb); + + int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring, + u32 size, u16 stride); diff --git a/master/mpt2sas-02.00.00.00.patch b/master/mpt2sas-02.00.00.00.patch new file mode 100644 index 0000000..96bdd75 --- /dev/null +++ b/master/mpt2sas-02.00.00.00.patch @@ -0,0 +1,25277 @@ +diff -r 2c3db38968de drivers/scsi/mpt2sas/Kconfig +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/Kconfig Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,66 @@ ++# ++# Kernel configuration file for the MPT2SAS ++# ++# This code is based on drivers/scsi/mpt2sas/Kconfig ++# Copyright (C) 2007-2008 LSI Corporation ++# (mailto:DL-MPTFusionLinux@lsi.com) ++ ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License ++# as published by the Free Software Foundation; either version 2 ++# of the License, or (at your option) any later version. ++ ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++ ++# NO WARRANTY ++# THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR ++# CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT ++# LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, ++# MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is ++# solely responsible for determining the appropriateness of using and ++# distributing the Program and assumes all risks associated with its ++# exercise of rights under this Agreement, including but not limited to ++# the risks and costs of program errors, damage to or loss of data, ++# programs or equipment, and unavailability or interruption of operations. ++ ++# DISCLAIMER OF LIABILITY ++# NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY ++# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++# DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND ++# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR ++# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++# USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED ++# HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ++ ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, ++# USA. ++ ++config SCSI_MPT2SAS ++ tristate "LSI MPT Fusion SAS 2.0 Device Driver" ++ depends on PCI && SCSI ++ select SCSI_SAS_ATTRS ++ ---help--- ++ This driver supports PCI-Express SAS 6Gb/s Host Adapters. ++ ++config SCSI_MPT2SAS_MAX_SGE ++ int "LSI MPT Fusion Max number of SG Entries (16 - 128)" ++ depends on PCI && SCSI && SCSI_MPT2SAS ++ default "128" ++ range 16 128 ++ ---help--- ++ This option allows you to specify the maximum number of scatter- ++ gather entries per I/O. The driver default is 128, which matches ++ SAFE_PHYS_SEGMENTS. However, it may decreased down to 16. ++ Decreasing this parameter will reduce memory requirements ++ on a per controller instance. ++ ++config SCSI_MPT2SAS_LOGGING ++ bool "LSI MPT Fusion logging facility" ++ depends on PCI && SCSI && SCSI_MPT2SAS ++ ---help--- ++ This turns on a logging facility. +diff -r 2c3db38968de drivers/scsi/mpt2sas/Makefile +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/Makefile Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,14 @@ ++# mpt2sas makefile ++ ++# event logging support ++EXTRA_CFLAGS += -DCONFIG_SCSI_MPT2SAS_LOGGING ++ ++# utilizing chain pool instead of dedicated chains ++#EXTRA_CFLAGS += -DCHAIN_POOL ++ ++obj-$(CONFIG_SCSI_MPT2SAS) += mpt2sas.o ++mpt2sas-y += mpt2sas_base.o \ ++ mpt2sas_config.o \ ++ mpt2sas_scsih.o \ ++ mpt2sas_transport.o \ ++ mpt2sas_ctl.o +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpi/.copyarea.db +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpi/.copyarea.db Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,14 @@ ++ClearCase CopyAreaDB|4 ++sas2_drv/mpt2sas/mpi ++2 ++a ++a:mpi2_sas.h|1|12025dcce68|334b|ca3600e0|a2b1036283134f29a0c114c045461ae1|0 ++10:mpi2_history.txt|1|12025dcce68|450e|99167003|4d701d3de14f46298b9695bf74267553|0 ++6:mpi2.h|1|12025dcce68|ac4c|a0dc971f|89e12deadaab4182948f74c3605ecea2|0 ++b:mpi2_raid.h|1|12025dcce68|3537|79494b61|49c45f50e8424b419d17f67da30aacf6|0 ++b:mpi2_targ.h|1|12025dcce68|5800|790c6272|be471f5dd75344c6aec626eb1440aa79|0 ++b:mpi2_tool.h|1|12025dcce68|302b|356b00fc|956d748c22024a72b5d0359a51518fc5|0 ++b:mpi2_type.h|1|1200fc4fbc8|664|6c63907c|d607d9eee2b842cbaae65f99c3b103fa|0 ++b:mpi2_init.h|1|12025dcce68|4f6a|99956bd|5e83d076242e4f289ff04f1b1d2ae824|0 ++b:mpi2_cnfg.h|1|12025dcce68|19fb3|483dd4d6|37e8cf7e03104e269f932cb5132bc05d|0 ++a:mpi2_ioc.h|1|12025dcce68|fece|86693d79|7d23222fe3e344f982bd80b433dcdc12|0 +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpi/mpi2.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpi/mpi2.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,1067 @@ ++/* ++ * Copyright (c) 2000-2009 LSI Corporation. ++ * ++ * ++ * Name: mpi2.h ++ * Title: MPI Message independent structures and definitions ++ * including System Interface Register Set and ++ * scatter/gather formats. ++ * Creation Date: June 21, 2006 ++ * ++ * mpi2.h Version: 02.00.11 ++ * ++ * Version History ++ * --------------- ++ * ++ * Date Version Description ++ * -------- -------- ------------------------------------------------------ ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. ++ * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. ++ * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. ++ * Moved ReplyPostHostIndex register to offset 0x6C of the ++ * MPI2_SYSTEM_INTERFACE_REGS and modified the define for ++ * MPI2_REPLY_POST_HOST_INDEX_OFFSET. ++ * Added union of request descriptors. ++ * Added union of reply descriptors. ++ * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. ++ * Added define for MPI2_VERSION_02_00. ++ * Fixed the size of the FunctionDependent5 field in the ++ * MPI2_DEFAULT_REPLY structure. ++ * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. ++ * Removed the MPI-defined Fault Codes and extended the ++ * product specific codes up to 0xEFFF. ++ * Added a sixth key value for the WriteSequence register ++ * and changed the flush value to 0x0. ++ * Added message function codes for Diagnostic Buffer Post ++ * and Diagnsotic Release. ++ * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED ++ * Moved MPI2_VERSION_UNION from mpi2_ioc.h. ++ * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. ++ * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. ++ * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. ++ * Added #defines for marking a reply descriptor as unused. ++ * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. ++ * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. ++ * Moved LUN field defines from mpi2_init.h. ++ * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. ++ * -------------------------------------------------------------------------- ++ */ ++ ++#ifndef MPI2_H ++#define MPI2_H ++ ++ ++/***************************************************************************** ++* ++* MPI Version Definitions ++* ++*****************************************************************************/ ++ ++#define MPI2_VERSION_MAJOR (0x02) ++#define MPI2_VERSION_MINOR (0x00) ++#define MPI2_VERSION_MAJOR_MASK (0xFF00) ++#define MPI2_VERSION_MAJOR_SHIFT (8) ++#define MPI2_VERSION_MINOR_MASK (0x00FF) ++#define MPI2_VERSION_MINOR_SHIFT (0) ++#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ ++ MPI2_VERSION_MINOR) ++ ++#define MPI2_VERSION_02_00 (0x0200) ++ ++/* versioning for this MPI header set */ ++#define MPI2_HEADER_VERSION_UNIT (0x0B) ++#define MPI2_HEADER_VERSION_DEV (0x00) ++#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) ++#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) ++#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) ++#define MPI2_HEADER_VERSION_DEV_SHIFT (0) ++#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) ++ ++ ++/***************************************************************************** ++* ++* IOC State Definitions ++* ++*****************************************************************************/ ++ ++#define MPI2_IOC_STATE_RESET (0x00000000) ++#define MPI2_IOC_STATE_READY (0x10000000) ++#define MPI2_IOC_STATE_OPERATIONAL (0x20000000) ++#define MPI2_IOC_STATE_FAULT (0x40000000) ++ ++#define MPI2_IOC_STATE_MASK (0xF0000000) ++#define MPI2_IOC_STATE_SHIFT (28) ++ ++/* Fault state range for prodcut specific codes */ ++#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) ++#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) ++ ++ ++/***************************************************************************** ++* ++* System Interface Register Definitions ++* ++*****************************************************************************/ ++ ++typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS ++{ ++ U32 Doorbell; /* 0x00 */ ++ U32 WriteSequence; /* 0x04 */ ++ U32 HostDiagnostic; /* 0x08 */ ++ U32 Reserved1; /* 0x0C */ ++ U32 DiagRWData; /* 0x10 */ ++ U32 DiagRWAddressLow; /* 0x14 */ ++ U32 DiagRWAddressHigh; /* 0x18 */ ++ U32 Reserved2[5]; /* 0x1C */ ++ U32 HostInterruptStatus; /* 0x30 */ ++ U32 HostInterruptMask; /* 0x34 */ ++ U32 DCRData; /* 0x38 */ ++ U32 DCRAddress; /* 0x3C */ ++ U32 Reserved3[2]; /* 0x40 */ ++ U32 ReplyFreeHostIndex; /* 0x48 */ ++ U32 Reserved4[8]; /* 0x4C */ ++ U32 ReplyPostHostIndex; /* 0x6C */ ++ U32 Reserved5; /* 0x70 */ ++ U32 HCBSize; /* 0x74 */ ++ U32 HCBAddressLow; /* 0x78 */ ++ U32 HCBAddressHigh; /* 0x7C */ ++ U32 Reserved6[16]; /* 0x80 */ ++ U32 RequestDescriptorPostLow; /* 0xC0 */ ++ U32 RequestDescriptorPostHigh; /* 0xC4 */ ++ U32 Reserved7[14]; /* 0xC8 */ ++} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, ++ Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; ++ ++/* ++ * Defines for working with the Doorbell register. ++ */ ++#define MPI2_DOORBELL_OFFSET (0x00000000) ++ ++/* IOC --> System values */ ++#define MPI2_DOORBELL_USED (0x08000000) ++#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) ++#define MPI2_DOORBELL_WHO_INIT_SHIFT (24) ++#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) ++#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) ++ ++/* System --> IOC values */ ++#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) ++#define MPI2_DOORBELL_FUNCTION_SHIFT (24) ++#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) ++#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) ++ ++ ++/* ++ * Defines for the WriteSequence register ++ */ ++#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) ++#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) ++#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) ++#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) ++#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) ++#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) ++#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) ++#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) ++#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) ++ ++/* ++ * Defines for the HostDiagnostic register ++ */ ++#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) ++ ++#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) ++#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) ++#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) ++ ++#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) ++#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) ++#define MPI2_DIAG_HCB_MODE (0x00000100) ++#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) ++#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) ++#define MPI2_DIAG_RESET_HISTORY (0x00000020) ++#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) ++#define MPI2_DIAG_RESET_ADAPTER (0x00000004) ++#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) ++ ++/* ++ * Offsets for DiagRWData and address ++ */ ++#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) ++#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) ++#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) ++ ++/* ++ * Defines for the HostInterruptStatus register ++ */ ++#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) ++#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) ++#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS ++#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) ++#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) ++#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) ++#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS ++ ++/* ++ * Defines for the HostInterruptMask register ++ */ ++#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) ++#define MPI2_HIM_RESET_IRQ_MASK (0x40000000) ++#define MPI2_HIM_REPLY_INT_MASK (0x00000008) ++#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK ++#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) ++#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK ++ ++/* ++ * Offsets for DCRData and address ++ */ ++#define MPI2_DCR_DATA_OFFSET (0x00000038) ++#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) ++ ++/* ++ * Offset for the Reply Free Queue ++ */ ++#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) ++ ++/* ++ * Offset for the Reply Descriptor Post Queue ++ */ ++#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) ++ ++/* ++ * Defines for the HCBSize and address ++ */ ++#define MPI2_HCB_SIZE_OFFSET (0x00000074) ++#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) ++#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) ++ ++#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) ++#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) ++ ++/* ++ * Offsets for the Request Queue ++ */ ++#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) ++#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) ++ ++ ++/***************************************************************************** ++* ++* Message Descriptors ++* ++*****************************************************************************/ ++ ++/* Request Descriptors */ ++ ++/* Default Request Descriptor */ ++typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR ++{ ++ U8 RequestFlags; /* 0x00 */ ++ U8 VF_ID; /* 0x01 */ ++ U16 SMID; /* 0x02 */ ++ U16 LMID; /* 0x04 */ ++ U16 DescriptorTypeDependent; /* 0x06 */ ++} MPI2_DEFAULT_REQUEST_DESCRIPTOR, ++ MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, ++ Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; ++ ++/* defines for the RequestFlags field */ ++#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) ++#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) ++#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) ++#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) ++#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) ++ ++#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) ++ ++ ++/* High Priority Request Descriptor */ ++typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR ++{ ++ U8 RequestFlags; /* 0x00 */ ++ U8 VF_ID; /* 0x01 */ ++ U16 SMID; /* 0x02 */ ++ U16 LMID; /* 0x04 */ ++ U16 Reserved1; /* 0x06 */ ++} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, ++ MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, ++ Mpi2HighPriorityRequestDescriptor_t, ++ MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; ++ ++ ++/* SCSI IO Request Descriptor */ ++typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR ++{ ++ U8 RequestFlags; /* 0x00 */ ++ U8 VF_ID; /* 0x01 */ ++ U16 SMID; /* 0x02 */ ++ U16 LMID; /* 0x04 */ ++ U16 DevHandle; /* 0x06 */ ++} MPI2_SCSI_IO_REQUEST_DESCRIPTOR, ++ MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, ++ Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; ++ ++ ++/* SCSI Target Request Descriptor */ ++typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR ++{ ++ U8 RequestFlags; /* 0x00 */ ++ U8 VF_ID; /* 0x01 */ ++ U16 SMID; /* 0x02 */ ++ U16 LMID; /* 0x04 */ ++ U16 IoIndex; /* 0x06 */ ++} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, ++ MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, ++ Mpi2SCSITargetRequestDescriptor_t, ++ MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; ++ ++/* union of Request Descriptors */ ++typedef union _MPI2_REQUEST_DESCRIPTOR_UNION ++{ ++ MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; ++ MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; ++ MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; ++ MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; ++ U64 Words; ++} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, ++ Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; ++ ++ ++/* Reply Descriptors */ ++ ++/* Default Reply Descriptor */ ++typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR ++{ ++ U8 ReplyFlags; /* 0x00 */ ++ U8 VF_ID; /* 0x01 */ ++ U16 DescriptorTypeDependent1; /* 0x02 */ ++ U32 DescriptorTypeDependent2; /* 0x04 */ ++} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, ++ Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; ++ ++/* defines for the ReplyFlags field */ ++#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) ++#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) ++#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) ++#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) ++#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) ++#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) ++ ++/* values for marking a reply descriptor as unused */ ++#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) ++#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) ++ ++/* Address Reply Descriptor */ ++typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR ++{ ++ U8 ReplyFlags; /* 0x00 */ ++ U8 VF_ID; /* 0x01 */ ++ U16 SMID; /* 0x02 */ ++ U32 ReplyFrameAddress; /* 0x04 */ ++} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, ++ Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; ++ ++#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) ++ ++ ++/* SCSI IO Success Reply Descriptor */ ++typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR ++{ ++ U8 ReplyFlags; /* 0x00 */ ++ U8 VF_ID; /* 0x01 */ ++ U16 SMID; /* 0x02 */ ++ U16 TaskTag; /* 0x04 */ ++ U16 DevHandle; /* 0x06 */ ++} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, ++ MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, ++ Mpi2SCSIIOSuccessReplyDescriptor_t, ++ MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; ++ ++ ++/* TargetAssist Success Reply Descriptor */ ++typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR ++{ ++ U8 ReplyFlags; /* 0x00 */ ++ U8 VF_ID; /* 0x01 */ ++ U16 SMID; /* 0x02 */ ++ U8 SequenceNumber; /* 0x04 */ ++ U8 Reserved1; /* 0x05 */ ++ U16 IoIndex; /* 0x06 */ ++} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, ++ MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, ++ Mpi2TargetAssistSuccessReplyDescriptor_t, ++ MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; ++ ++ ++/* Target Command Buffer Reply Descriptor */ ++typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR ++{ ++ U8 ReplyFlags; /* 0x00 */ ++ U8 VF_ID; /* 0x01 */ ++ U8 VP_ID; /* 0x02 */ ++ U8 Flags; /* 0x03 */ ++ U16 InitiatorDevHandle; /* 0x04 */ ++ U16 IoIndex; /* 0x06 */ ++} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, ++ MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, ++ Mpi2TargetCommandBufferReplyDescriptor_t, ++ MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; ++ ++/* defines for Flags field */ ++#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) ++ ++ ++/* union of Reply Descriptors */ ++typedef union _MPI2_REPLY_DESCRIPTORS_UNION ++{ ++ MPI2_DEFAULT_REPLY_DESCRIPTOR Default; ++ MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; ++ MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; ++ MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; ++ MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; ++ U64 Words; ++} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, ++ Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; ++ ++ ++ ++/***************************************************************************** ++* ++* Message Functions ++* 0x80 -> 0x8F reserved for private message use per product ++* ++* ++*****************************************************************************/ ++ ++#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ ++#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ ++#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ ++#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ ++#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ ++#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ ++#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ ++#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ ++#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ ++#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ ++#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ ++#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ ++#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ ++#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ ++#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ ++#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ ++#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ ++#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ ++#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ ++#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ ++#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ ++#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ ++#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ ++#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ ++#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ ++ ++ ++ ++/* Doorbell functions */ ++#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) ++/* #define MPI2_FUNCTION_IO_UNIT_RESET (0x41) */ ++#define MPI2_FUNCTION_HANDSHAKE (0x42) ++ ++ ++/***************************************************************************** ++* ++* IOC Status Values ++* ++*****************************************************************************/ ++ ++/* mask for IOCStatus status value */ ++#define MPI2_IOCSTATUS_MASK (0x7FFF) ++ ++/**************************************************************************** ++* Common IOCStatus values for all replies ++****************************************************************************/ ++ ++#define MPI2_IOCSTATUS_SUCCESS (0x0000) ++#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) ++#define MPI2_IOCSTATUS_BUSY (0x0002) ++#define MPI2_IOCSTATUS_INVALID_SGL (0x0003) ++#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) ++#define MPI2_IOCSTATUS_INVALID_VPID (0x0005) ++#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) ++#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) ++#define MPI2_IOCSTATUS_INVALID_STATE (0x0008) ++#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) ++ ++/**************************************************************************** ++* Config IOCStatus values ++****************************************************************************/ ++ ++#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) ++#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) ++#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) ++#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) ++#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) ++#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) ++ ++/**************************************************************************** ++* SCSI IO Reply ++****************************************************************************/ ++ ++#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) ++#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) ++#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) ++#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) ++#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) ++#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) ++#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) ++#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) ++#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) ++#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) ++#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) ++#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) ++ ++/**************************************************************************** ++* For use by SCSI Initiator and SCSI Target end-to-end data protection ++****************************************************************************/ ++ ++#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) ++#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) ++#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) ++ ++/**************************************************************************** ++* SCSI Target values ++****************************************************************************/ ++ ++#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) ++#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) ++#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) ++#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) ++#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) ++#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) ++#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) ++#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) ++#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) ++#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) ++ ++/**************************************************************************** ++* Serial Attached SCSI values ++****************************************************************************/ ++ ++#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) ++#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) ++ ++/**************************************************************************** ++* Diagnostic Buffer Post / Diagnostic Release values ++****************************************************************************/ ++ ++#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) ++ ++ ++/**************************************************************************** ++* IOCStatus flag to indicate that log info is available ++****************************************************************************/ ++ ++#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) ++ ++/**************************************************************************** ++* IOCLogInfo Types ++****************************************************************************/ ++ ++#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) ++#define MPI2_IOCLOGINFO_TYPE_SHIFT (28) ++#define MPI2_IOCLOGINFO_TYPE_NONE (0x0) ++#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) ++#define MPI2_IOCLOGINFO_TYPE_FC (0x2) ++#define MPI2_IOCLOGINFO_TYPE_SAS (0x3) ++#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) ++#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) ++ ++ ++/***************************************************************************** ++* ++* Standard Message Structures ++* ++*****************************************************************************/ ++ ++/**************************************************************************** ++* Request Message Header for all request messages ++****************************************************************************/ ++ ++typedef struct _MPI2_REQUEST_HEADER ++{ ++ U16 FunctionDependent1; /* 0x00 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 FunctionDependent2; /* 0x04 */ ++ U8 FunctionDependent3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved1; /* 0x0A */ ++} MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, ++ MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; ++ ++ ++/**************************************************************************** ++* Default Reply ++****************************************************************************/ ++ ++typedef struct _MPI2_DEFAULT_REPLY ++{ ++ U16 FunctionDependent1; /* 0x00 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 FunctionDependent2; /* 0x04 */ ++ U8 FunctionDependent3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved1; /* 0x0A */ ++ U16 FunctionDependent5; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++} MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, ++ MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; ++ ++ ++/* common version structure/union used in messages and configuration pages */ ++ ++typedef struct _MPI2_VERSION_STRUCT ++{ ++ U8 Dev; /* 0x00 */ ++ U8 Unit; /* 0x01 */ ++ U8 Minor; /* 0x02 */ ++ U8 Major; /* 0x03 */ ++} MPI2_VERSION_STRUCT; ++ ++typedef union _MPI2_VERSION_UNION ++{ ++ MPI2_VERSION_STRUCT Struct; ++ U32 Word; ++} MPI2_VERSION_UNION; ++ ++ ++/* LUN field defines, common to many structures */ ++#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) ++#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) ++#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) ++#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) ++#define MPI2_LUN_LEVEL_1_WORD (0xFF00) ++#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) ++ ++ ++/***************************************************************************** ++* ++* Fusion-MPT MPI Scatter Gather Elements ++* ++*****************************************************************************/ ++ ++/**************************************************************************** ++* MPI Simple Element structures ++****************************************************************************/ ++ ++typedef struct _MPI2_SGE_SIMPLE32 ++{ ++ U32 FlagsLength; ++ U32 Address; ++} MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, ++ Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; ++ ++typedef struct _MPI2_SGE_SIMPLE64 ++{ ++ U32 FlagsLength; ++ U64 Address; ++} MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, ++ Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; ++ ++typedef struct _MPI2_SGE_SIMPLE_UNION ++{ ++ U32 FlagsLength; ++ union ++ { ++ U32 Address32; ++ U64 Address64; ++ } u; ++} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, ++ Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; ++ ++ ++/**************************************************************************** ++* MPI Chain Element structures ++****************************************************************************/ ++ ++typedef struct _MPI2_SGE_CHAIN32 ++{ ++ U16 Length; ++ U8 NextChainOffset; ++ U8 Flags; ++ U32 Address; ++} MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, ++ Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; ++ ++typedef struct _MPI2_SGE_CHAIN64 ++{ ++ U16 Length; ++ U8 NextChainOffset; ++ U8 Flags; ++ U64 Address; ++} MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, ++ Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; ++ ++typedef struct _MPI2_SGE_CHAIN_UNION ++{ ++ U16 Length; ++ U8 NextChainOffset; ++ U8 Flags; ++ union ++ { ++ U32 Address32; ++ U64 Address64; ++ } u; ++} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, ++ Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; ++ ++ ++/**************************************************************************** ++* MPI Transaction Context Element structures ++****************************************************************************/ ++ ++typedef struct _MPI2_SGE_TRANSACTION32 ++{ ++ U8 Reserved; ++ U8 ContextSize; ++ U8 DetailsLength; ++ U8 Flags; ++ U32 TransactionContext[1]; ++ U32 TransactionDetails[1]; ++} MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, ++ Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; ++ ++typedef struct _MPI2_SGE_TRANSACTION64 ++{ ++ U8 Reserved; ++ U8 ContextSize; ++ U8 DetailsLength; ++ U8 Flags; ++ U32 TransactionContext[2]; ++ U32 TransactionDetails[1]; ++} MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, ++ Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; ++ ++typedef struct _MPI2_SGE_TRANSACTION96 ++{ ++ U8 Reserved; ++ U8 ContextSize; ++ U8 DetailsLength; ++ U8 Flags; ++ U32 TransactionContext[3]; ++ U32 TransactionDetails[1]; ++} MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, ++ Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; ++ ++typedef struct _MPI2_SGE_TRANSACTION128 ++{ ++ U8 Reserved; ++ U8 ContextSize; ++ U8 DetailsLength; ++ U8 Flags; ++ U32 TransactionContext[4]; ++ U32 TransactionDetails[1]; ++} MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, ++ Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; ++ ++typedef struct _MPI2_SGE_TRANSACTION_UNION ++{ ++ U8 Reserved; ++ U8 ContextSize; ++ U8 DetailsLength; ++ U8 Flags; ++ union ++ { ++ U32 TransactionContext32[1]; ++ U32 TransactionContext64[2]; ++ U32 TransactionContext96[3]; ++ U32 TransactionContext128[4]; ++ } u; ++ U32 TransactionDetails[1]; ++} MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, ++ Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; ++ ++ ++/**************************************************************************** ++* MPI SGE union for IO SGL's ++****************************************************************************/ ++ ++typedef struct _MPI2_MPI_SGE_IO_UNION ++{ ++ union ++ { ++ MPI2_SGE_SIMPLE_UNION Simple; ++ MPI2_SGE_CHAIN_UNION Chain; ++ } u; ++} MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, ++ Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; ++ ++ ++/**************************************************************************** ++* MPI SGE union for SGL's with Simple and Transaction elements ++****************************************************************************/ ++ ++typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION ++{ ++ union ++ { ++ MPI2_SGE_SIMPLE_UNION Simple; ++ MPI2_SGE_TRANSACTION_UNION Transaction; ++ } u; ++} MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, ++ Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; ++ ++ ++/**************************************************************************** ++* All MPI SGE types union ++****************************************************************************/ ++ ++typedef struct _MPI2_MPI_SGE_UNION ++{ ++ union ++ { ++ MPI2_SGE_SIMPLE_UNION Simple; ++ MPI2_SGE_CHAIN_UNION Chain; ++ MPI2_SGE_TRANSACTION_UNION Transaction; ++ } u; ++} MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, ++ Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; ++ ++ ++/**************************************************************************** ++* MPI SGE field definition and masks ++****************************************************************************/ ++ ++/* Flags field bit definitions */ ++ ++#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) ++#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) ++#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) ++#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) ++#define MPI2_SGE_FLAGS_DIRECTION (0x04) ++#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) ++#define MPI2_SGE_FLAGS_END_OF_LIST (0x01) ++ ++#define MPI2_SGE_FLAGS_SHIFT (24) ++ ++#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) ++#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) ++ ++/* Element Type */ ++ ++#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) ++#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) ++#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) ++#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) ++ ++/* Address location */ ++ ++#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) ++ ++/* Direction */ ++ ++#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) ++#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) ++ ++/* Address Size */ ++ ++#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) ++#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) ++ ++/* Context Size */ ++ ++#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) ++#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) ++#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) ++#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) ++ ++#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) ++#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) ++ ++/**************************************************************************** ++* MPI SGE operation Macros ++****************************************************************************/ ++ ++/* SIMPLE FlagsLength manipulations... */ ++#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) ++#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) ++#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) ++#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) ++ ++#define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) ++ ++#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) ++#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) ++#define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) ++ ++/* CAUTION - The following are READ-MODIFY-WRITE! */ ++#define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) ++#define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) ++ ++#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) ++ ++ ++/***************************************************************************** ++* ++* Fusion-MPT IEEE Scatter Gather Elements ++* ++*****************************************************************************/ ++ ++/**************************************************************************** ++* IEEE Simple Element structures ++****************************************************************************/ ++ ++typedef struct _MPI2_IEEE_SGE_SIMPLE32 ++{ ++ U32 Address; ++ U32 FlagsLength; ++} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, ++ Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; ++ ++typedef struct _MPI2_IEEE_SGE_SIMPLE64 ++{ ++ U64 Address; ++ U32 Length; ++ U16 Reserved1; ++ U8 Reserved2; ++ U8 Flags; ++} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, ++ Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; ++ ++typedef union _MPI2_IEEE_SGE_SIMPLE_UNION ++{ ++ MPI2_IEEE_SGE_SIMPLE32 Simple32; ++ MPI2_IEEE_SGE_SIMPLE64 Simple64; ++} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, ++ Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; ++ ++ ++/**************************************************************************** ++* IEEE Chain Element structures ++****************************************************************************/ ++ ++typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; ++ ++typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; ++ ++typedef union _MPI2_IEEE_SGE_CHAIN_UNION ++{ ++ MPI2_IEEE_SGE_CHAIN32 Chain32; ++ MPI2_IEEE_SGE_CHAIN64 Chain64; ++} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, ++ Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; ++ ++ ++/**************************************************************************** ++* All IEEE SGE types union ++****************************************************************************/ ++ ++typedef struct _MPI2_IEEE_SGE_UNION ++{ ++ union ++ { ++ MPI2_IEEE_SGE_SIMPLE_UNION Simple; ++ MPI2_IEEE_SGE_CHAIN_UNION Chain; ++ } u; ++} MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, ++ Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; ++ ++ ++/**************************************************************************** ++* IEEE SGE field definitions and masks ++****************************************************************************/ ++ ++/* Flags field bit definitions */ ++ ++#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) ++ ++#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) ++ ++#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) ++ ++/* Element Type */ ++ ++#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) ++#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) ++ ++/* Data Location Address Space */ ++ ++#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) ++#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) ++#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) ++#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) ++#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) ++ ++ ++/**************************************************************************** ++* IEEE SGE operation Macros ++****************************************************************************/ ++ ++/* SIMPLE FlagsLength manipulations... */ ++#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) ++#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) ++#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) ++ ++#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) ++ ++#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) ++#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) ++#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) ++ ++/* CAUTION - The following are READ-MODIFY-WRITE! */ ++#define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) ++#define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) ++ ++ ++ ++ ++/***************************************************************************** ++* ++* Fusion-MPT MPI/IEEE Scatter Gather Unions ++* ++*****************************************************************************/ ++ ++typedef union _MPI2_SIMPLE_SGE_UNION ++{ ++ MPI2_SGE_SIMPLE_UNION MpiSimple; ++ MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; ++} MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, ++ Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; ++ ++ ++typedef union _MPI2_SGE_IO_UNION ++{ ++ MPI2_SGE_SIMPLE_UNION MpiSimple; ++ MPI2_SGE_CHAIN_UNION MpiChain; ++ MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; ++ MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; ++} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, ++ Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; ++ ++ ++/**************************************************************************** ++* ++* Values for SGLFlags field, used in many request messages with an SGL ++* ++****************************************************************************/ ++ ++/* values for MPI SGL Data Location Address Space subfield */ ++#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) ++#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) ++#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) ++#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) ++#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) ++/* values for SGL Type subfield */ ++#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) ++#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) ++#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) ++#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) ++ ++ ++#endif ++ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpi/mpi2_cnfg.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpi/mpi2_cnfg.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,2151 @@ ++/* ++ * Copyright (c) 2000-2009 LSI Corporation. ++ * ++ * ++ * Name: mpi2_cnfg.h ++ * Title: MPI Configuration messages and pages ++ * Creation Date: November 10, 2006 ++ * ++ * mpi2_cnfg.h Version: 02.00.10 ++ * ++ * Version History ++ * --------------- ++ * ++ * Date Version Description ++ * -------- -------- ------------------------------------------------------ ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. ++ * Added Manufacturing Page 11. ++ * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE ++ * define. ++ * 06-26-07 02.00.02 Adding generic structure for product-specific ++ * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. ++ * Rework of BIOS Page 2 configuration page. ++ * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the ++ * forms. ++ * Added configuration pages IOC Page 8 and Driver ++ * Persistent Mapping Page 0. ++ * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated ++ * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, ++ * RAID Physical Disk Pages 0 and 1, RAID Configuration ++ * Page 0). ++ * Added new value for AccessStatus field of SAS Device ++ * Page 0 (_SATA_NEEDS_INITIALIZATION). ++ * 10-31-07 02.00.04 Added missing SEPDevHandle field to ++ * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. ++ * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for ++ * NVDATA. ++ * Modified IOC Page 7 to use masks and added field for ++ * SASBroadcastPrimitiveMasks. ++ * Added MPI2_CONFIG_PAGE_BIOS_4. ++ * Added MPI2_CONFIG_PAGE_LOG_0. ++ * 02-29-08 02.00.06 Modified various names to make them 32-character unique. ++ * Added SAS Device IDs. ++ * Updated Integrated RAID configuration pages including ++ * Manufacturing Page 4, IOC Page 6, and RAID Configuration ++ * Page 0. ++ * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. ++ * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. ++ * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. ++ * Added missing MaxNumRoutedSasAddresses field to ++ * MPI2_CONFIG_PAGE_EXPANDER_0. ++ * Added SAS Port Page 0. ++ * Modified structure layout for ++ * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. ++ * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use ++ * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. ++ * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF ++ * to 0x000000FF. ++ * Added two new values for the Physical Disk Coercion Size ++ * bits in the Flags field of Manufacturing Page 4. ++ * Added product-specific Manufacturing pages 16 to 31. ++ * Modified Flags bits for controlling write cache on SATA ++ * drives in IO Unit Page 1. ++ * Added new bit to AdditionalControlFlags of SAS IO Unit ++ * Page 1 to control Invalid Topology Correction. ++ * Added additional defines for RAID Volume Page 0 ++ * VolumeStatusFlags field. ++ * Modified meaning of RAID Volume Page 0 VolumeSettings ++ * define for auto-configure of hot-swap drives. ++ * Added SupportedPhysDisks field to RAID Volume Page 1 and ++ * added related defines. ++ * Added PhysDiskAttributes field (and related defines) to ++ * RAID Physical Disk Page 0. ++ * Added MPI2_SAS_PHYINFO_PHY_VACANT define. ++ * Added three new DiscoveryStatus bits for SAS IO Unit ++ * Page 0 and SAS Expander Page 0. ++ * Removed multiplexing information from SAS IO Unit pages. ++ * Added BootDeviceWaitTime field to SAS IO Unit Page 4. ++ * Removed Zone Address Resolved bit from PhyInfo and from ++ * Expander Page 0 Flags field. ++ * Added two new AccessStatus values to SAS Device Page 0 ++ * for indicating routing problems. Added 3 reserved words ++ * to this page. ++ * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. ++ * Inserted missing reserved field into structure for IOC ++ * Page 6. ++ * Added more pending task bits to RAID Volume Page 0 ++ * VolumeStatusFlags defines. ++ * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. ++ * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 ++ * and SAS Expander Page 0 to flag a downstream initiator ++ * when in simplified routing mode. ++ * Removed SATA Init Failure defines for DiscoveryStatus ++ * fields of SAS IO Unit Page 0 and SAS Expander Page 0. ++ * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. ++ * Added PortGroups, DmaGroup, and ControlGroup fields to ++ * SAS Device Page 0. ++ * -------------------------------------------------------------------------- ++ */ ++ ++#ifndef MPI2_CNFG_H ++#define MPI2_CNFG_H ++ ++/***************************************************************************** ++* Configuration Page Header and defines ++*****************************************************************************/ ++ ++/* Config Page Header */ ++typedef struct _MPI2_CONFIG_PAGE_HEADER ++{ ++ U8 PageVersion; /* 0x00 */ ++ U8 PageLength; /* 0x01 */ ++ U8 PageNumber; /* 0x02 */ ++ U8 PageType; /* 0x03 */ ++} MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, ++ Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; ++ ++typedef union _MPI2_CONFIG_PAGE_HEADER_UNION ++{ ++ MPI2_CONFIG_PAGE_HEADER Struct; ++ U8 Bytes[4]; ++ U16 Word16[2]; ++ U32 Word32; ++} MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, ++ Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; ++ ++/* Extended Config Page Header */ ++typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER ++{ ++ U8 PageVersion; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 PageNumber; /* 0x02 */ ++ U8 PageType; /* 0x03 */ ++ U16 ExtPageLength; /* 0x04 */ ++ U8 ExtPageType; /* 0x06 */ ++ U8 Reserved2; /* 0x07 */ ++} MPI2_CONFIG_EXTENDED_PAGE_HEADER, ++ MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, ++ Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; ++ ++typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION ++{ ++ MPI2_CONFIG_PAGE_HEADER Struct; ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; ++ U8 Bytes[8]; ++ U16 Word16[4]; ++ U32 Word32[2]; ++} MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, ++ Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; ++ ++ ++/* PageType field values */ ++#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) ++#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) ++#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) ++#define MPI2_CONFIG_PAGEATTR_MASK (0xF0) ++ ++#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) ++#define MPI2_CONFIG_PAGETYPE_IOC (0x01) ++#define MPI2_CONFIG_PAGETYPE_BIOS (0x02) ++#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) ++#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) ++#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) ++#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) ++#define MPI2_CONFIG_PAGETYPE_MASK (0x0F) ++ ++#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) ++ ++ ++/* ExtPageType field values */ ++#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) ++#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) ++#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) ++#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) ++#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) ++#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) ++#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) ++#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) ++#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) ++ ++ ++/***************************************************************************** ++* PageAddress defines ++*****************************************************************************/ ++ ++/* RAID Volume PageAddress format */ ++#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) ++#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) ++#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) ++ ++#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) ++ ++ ++/* RAID Physical Disk PageAddress format */ ++#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) ++#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) ++#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) ++#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) ++ ++#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) ++#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) ++ ++ ++/* SAS Expander PageAddress format */ ++#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) ++#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) ++#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) ++#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) ++ ++#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) ++#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) ++#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) ++ ++ ++/* SAS Device PageAddress format */ ++#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) ++#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) ++#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) ++ ++#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) ++ ++ ++/* SAS PHY PageAddress format */ ++#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) ++#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) ++#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) ++ ++#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) ++#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) ++ ++ ++/* SAS Port PageAddress format */ ++#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) ++#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) ++#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) ++ ++#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) ++ ++ ++/* SAS Enclosure PageAddress format */ ++#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) ++#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) ++#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) ++ ++#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) ++ ++ ++/* RAID Configuration PageAddress format */ ++#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) ++#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) ++#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) ++#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) ++ ++#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) ++ ++ ++/* Driver Persistent Mapping PageAddress format */ ++#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) ++#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) ++ ++#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) ++#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) ++#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) ++ ++ ++/**************************************************************************** ++* Configuration messages ++****************************************************************************/ ++ ++/* Configuration Request Message */ ++typedef struct _MPI2_CONFIG_REQUEST ++{ ++ U8 Action; /* 0x00 */ ++ U8 SGLFlags; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 ExtPageLength; /* 0x04 */ ++ U8 ExtPageType; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved1; /* 0x0A */ ++ U32 Reserved2; /* 0x0C */ ++ U32 Reserved3; /* 0x10 */ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ ++ U32 PageAddress; /* 0x18 */ ++ MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ ++} MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, ++ Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; ++ ++/* values for the Action field */ ++#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) ++#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) ++#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) ++#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) ++#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) ++#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) ++#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) ++#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) ++ ++/* values for SGLFlags field are in the SGL section of mpi2.h */ ++ ++ ++/* Config Reply Message */ ++typedef struct _MPI2_CONFIG_REPLY ++{ ++ U8 Action; /* 0x00 */ ++ U8 SGLFlags; /* 0x01 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 ExtPageLength; /* 0x04 */ ++ U8 ExtPageType; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved1; /* 0x0A */ ++ U16 Reserved2; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ ++} MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, ++ Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; ++ ++ ++ ++/***************************************************************************** ++* ++* C o n f i g u r a t i o n P a g e s ++* ++*****************************************************************************/ ++ ++/**************************************************************************** ++* Manufacturing Config pages ++****************************************************************************/ ++ ++#define MPI2_MFGPAGE_VENDORID_LSI (0x1000) ++ ++/* SAS */ ++#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) ++#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) ++#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) ++#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) ++#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) ++#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) ++#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) ++ ++ ++/* Manufacturing Page 0 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_MAN_0 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U8 ChipName[16]; /* 0x04 */ ++ U8 ChipRevision[8]; /* 0x14 */ ++ U8 BoardName[16]; /* 0x1C */ ++ U8 BoardAssembly[16]; /* 0x2C */ ++ U8 BoardTracerNumber[16]; /* 0x3C */ ++} MPI2_CONFIG_PAGE_MAN_0, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, ++ Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; ++ ++#define MPI2_MANUFACTURING0_PAGEVERSION (0x00) ++ ++ ++/* Manufacturing Page 1 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_MAN_1 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U8 VPD[256]; /* 0x04 */ ++} MPI2_CONFIG_PAGE_MAN_1, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, ++ Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; ++ ++#define MPI2_MANUFACTURING1_PAGEVERSION (0x00) ++ ++ ++typedef struct _MPI2_CHIP_REVISION_ID ++{ ++ U16 DeviceID; /* 0x00 */ ++ U8 PCIRevisionID; /* 0x02 */ ++ U8 Reserved; /* 0x03 */ ++} MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, ++ Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; ++ ++ ++/* Manufacturing Page 2 */ ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check Header.PageLength at runtime. ++ */ ++#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS ++#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) ++#endif ++ ++typedef struct _MPI2_CONFIG_PAGE_MAN_2 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ ++ U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ ++} MPI2_CONFIG_PAGE_MAN_2, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, ++ Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; ++ ++#define MPI2_MANUFACTURING2_PAGEVERSION (0x00) ++ ++ ++/* Manufacturing Page 3 */ ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check Header.PageLength at runtime. ++ */ ++#ifndef MPI2_MAN_PAGE_3_INFO_WORDS ++#define MPI2_MAN_PAGE_3_INFO_WORDS (1) ++#endif ++ ++typedef struct _MPI2_CONFIG_PAGE_MAN_3 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ ++ U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ ++} MPI2_CONFIG_PAGE_MAN_3, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, ++ Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; ++ ++#define MPI2_MANUFACTURING3_PAGEVERSION (0x00) ++ ++ ++/* Manufacturing Page 4 */ ++ ++typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS ++{ ++ U8 PowerSaveFlags; /* 0x00 */ ++ U8 InternalOperationsSleepTime; /* 0x01 */ ++ U8 InternalOperationsRunTime; /* 0x02 */ ++ U8 HostIdleTime; /* 0x03 */ ++} MPI2_MANPAGE4_PWR_SAVE_SETTINGS, ++ MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, ++ Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; ++ ++/* defines for the PowerSaveFlags field */ ++#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) ++#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) ++#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) ++#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) ++ ++typedef struct _MPI2_CONFIG_PAGE_MAN_4 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U32 Reserved1; /* 0x04 */ ++ U32 Flags; /* 0x08 */ ++ U8 InquirySize; /* 0x0C */ ++ U8 Reserved2; /* 0x0D */ ++ U16 Reserved3; /* 0x0E */ ++ U8 InquiryData[56]; /* 0x10 */ ++ U32 RAID0VolumeSettings; /* 0x48 */ ++ U32 RAID1EVolumeSettings; /* 0x4C */ ++ U32 RAID1VolumeSettings; /* 0x50 */ ++ U32 RAID10VolumeSettings; /* 0x54 */ ++ U32 Reserved4; /* 0x58 */ ++ U32 Reserved5; /* 0x5C */ ++ MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ ++ U8 MaxOCEDisks; /* 0x64 */ ++ U8 ResyncRate; /* 0x65 */ ++ U16 DataScrubDuration; /* 0x66 */ ++ U8 MaxHotSpares; /* 0x68 */ ++ U8 MaxPhysDisksPerVol; /* 0x69 */ ++ U8 MaxPhysDisks; /* 0x6A */ ++ U8 MaxVolumes; /* 0x6B */ ++} MPI2_CONFIG_PAGE_MAN_4, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, ++ Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; ++ ++#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) ++ ++/* Manufacturing Page 4 Flags field */ ++#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) ++#define MPI2_MANPAGE4_METADATA_512MB (0x00000000) ++ ++#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) ++#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) ++#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) ++ ++#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) ++#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) ++#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) ++#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) ++#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) ++ ++#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) ++#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) ++#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) ++#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) ++ ++#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) ++#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) ++#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) ++#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) ++#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) ++#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) ++#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) ++#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) ++ ++ ++/* Manufacturing Page 5 */ ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check Header.PageLength or NumPhys at runtime. ++ */ ++#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES ++#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) ++#endif ++ ++typedef struct _MPI2_MANUFACTURING5_ENTRY ++{ ++ U64 WWID; /* 0x00 */ ++ U64 DeviceName; /* 0x08 */ ++} MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, ++ Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; ++ ++typedef struct _MPI2_CONFIG_PAGE_MAN_5 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U8 NumPhys; /* 0x04 */ ++ U8 Reserved1; /* 0x05 */ ++ U16 Reserved2; /* 0x06 */ ++ U32 Reserved3; /* 0x08 */ ++ U32 Reserved4; /* 0x0C */ ++ MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ ++} MPI2_CONFIG_PAGE_MAN_5, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, ++ Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; ++ ++#define MPI2_MANUFACTURING5_PAGEVERSION (0x03) ++ ++ ++/* Manufacturing Page 6 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_MAN_6 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U32 ProductSpecificInfo;/* 0x04 */ ++} MPI2_CONFIG_PAGE_MAN_6, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, ++ Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; ++ ++#define MPI2_MANUFACTURING6_PAGEVERSION (0x00) ++ ++ ++/* Manufacturing Page 7 */ ++ ++typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO ++{ ++ U32 Pinout; /* 0x00 */ ++ U8 Connector[16]; /* 0x04 */ ++ U8 Location; /* 0x14 */ ++ U8 Reserved1; /* 0x15 */ ++ U16 Slot; /* 0x16 */ ++ U32 Reserved2; /* 0x18 */ ++} MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, ++ Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; ++ ++/* defines for the Pinout field */ ++#define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000) ++#define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000) ++#define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000) ++#define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000) ++#define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800) ++#define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400) ++#define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200) ++#define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100) ++#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002) ++#define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001) ++ ++/* defines for the Location field */ ++#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) ++#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) ++#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) ++#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) ++#define MPI2_MANPAGE7_LOCATION_AUTO (0x10) ++#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) ++#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check NumPhys at runtime. ++ */ ++#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX ++#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) ++#endif ++ ++typedef struct _MPI2_CONFIG_PAGE_MAN_7 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U32 Reserved1; /* 0x04 */ ++ U32 Reserved2; /* 0x08 */ ++ U32 Flags; /* 0x0C */ ++ U8 EnclosureName[16]; /* 0x10 */ ++ U8 NumPhys; /* 0x20 */ ++ U8 Reserved3; /* 0x21 */ ++ U16 Reserved4; /* 0x22 */ ++ MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ ++} MPI2_CONFIG_PAGE_MAN_7, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, ++ Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; ++ ++#define MPI2_MANUFACTURING7_PAGEVERSION (0x00) ++ ++/* defines for the Flags field */ ++#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) ++ ++ ++/* ++ * Generic structure to use for product-specific manufacturing pages ++ * (currently Manufacturing Page 8 through Manufacturing Page 31). ++ */ ++ ++typedef struct _MPI2_CONFIG_PAGE_MAN_PS ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U32 ProductSpecificInfo;/* 0x04 */ ++} MPI2_CONFIG_PAGE_MAN_PS, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, ++ Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; ++ ++#define MPI2_MANUFACTURING8_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING9_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING10_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING11_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING12_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING13_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING14_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING15_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING16_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING17_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING18_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING19_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING20_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING21_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING22_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING23_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING24_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING25_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING26_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING27_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING28_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING29_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING30_PAGEVERSION (0x00) ++#define MPI2_MANUFACTURING31_PAGEVERSION (0x00) ++ ++ ++/**************************************************************************** ++* IO Unit Config Pages ++****************************************************************************/ ++ ++/* IO Unit Page 0 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U64 UniqueValue; /* 0x04 */ ++ MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ ++ MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ ++} MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, ++ Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; ++ ++#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) ++ ++ ++/* IO Unit Page 1 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U32 Flags; /* 0x04 */ ++} MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, ++ Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; ++ ++#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) ++ ++/* IO Unit Page 1 Flags defines */ ++#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) ++#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) ++#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) ++#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) ++#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) ++#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) ++#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) ++#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) ++#define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002) ++#define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000) ++ ++ ++/* IO Unit Page 3 */ ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check Header.PageLength at runtime. ++ */ ++#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX ++#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) ++#endif ++ ++typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U8 GPIOCount; /* 0x04 */ ++ U8 Reserved1; /* 0x05 */ ++ U16 Reserved2; /* 0x06 */ ++ U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ ++} MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, ++ Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; ++ ++#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) ++ ++/* defines for IO Unit Page 3 GPIOVal field */ ++#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) ++#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) ++#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) ++#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) ++ ++ ++/**************************************************************************** ++* IOC Config Pages ++****************************************************************************/ ++ ++/* IOC Page 0 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_IOC_0 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U32 Reserved1; /* 0x04 */ ++ U32 Reserved2; /* 0x08 */ ++ U16 VendorID; /* 0x0C */ ++ U16 DeviceID; /* 0x0E */ ++ U8 RevisionID; /* 0x10 */ ++ U8 Reserved3; /* 0x11 */ ++ U16 Reserved4; /* 0x12 */ ++ U32 ClassCode; /* 0x14 */ ++ U16 SubsystemVendorID; /* 0x18 */ ++ U16 SubsystemID; /* 0x1A */ ++} MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, ++ Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; ++ ++#define MPI2_IOCPAGE0_PAGEVERSION (0x02) ++ ++ ++/* IOC Page 1 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_IOC_1 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U32 Flags; /* 0x04 */ ++ U32 CoalescingTimeout; /* 0x08 */ ++ U8 CoalescingDepth; /* 0x0C */ ++ U8 PCISlotNum; /* 0x0D */ ++ U8 PCIBusNum; /* 0x0E */ ++ U8 PCIDomainSegment; /* 0x0F */ ++ U32 Reserved1; /* 0x10 */ ++ U32 Reserved2; /* 0x14 */ ++} MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, ++ Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; ++ ++#define MPI2_IOCPAGE1_PAGEVERSION (0x05) ++ ++/* defines for IOC Page 1 Flags field */ ++#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) ++ ++#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) ++#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) ++#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) ++ ++/* IOC Page 6 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_IOC_6 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U32 CapabilitiesFlags; /* 0x04 */ ++ U8 MaxDrivesRAID0; /* 0x08 */ ++ U8 MaxDrivesRAID1; /* 0x09 */ ++ U8 MaxDrivesRAID1E; /* 0x0A */ ++ U8 MaxDrivesRAID10; /* 0x0B */ ++ U8 MinDrivesRAID0; /* 0x0C */ ++ U8 MinDrivesRAID1; /* 0x0D */ ++ U8 MinDrivesRAID1E; /* 0x0E */ ++ U8 MinDrivesRAID10; /* 0x0F */ ++ U32 Reserved1; /* 0x10 */ ++ U8 MaxGlobalHotSpares; /* 0x14 */ ++ U8 MaxPhysDisks; /* 0x15 */ ++ U8 MaxVolumes; /* 0x16 */ ++ U8 MaxConfigs; /* 0x17 */ ++ U8 MaxOCEDisks; /* 0x18 */ ++ U8 Reserved2; /* 0x19 */ ++ U16 Reserved3; /* 0x1A */ ++ U32 SupportedStripeSizeMapRAID0; /* 0x1C */ ++ U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ ++ U32 SupportedStripeSizeMapRAID10; /* 0x24 */ ++ U32 Reserved4; /* 0x28 */ ++ U32 Reserved5; /* 0x2C */ ++ U16 DefaultMetadataSize; /* 0x30 */ ++ U16 Reserved6; /* 0x32 */ ++ U16 MaxBadBlockTableEntries; /* 0x34 */ ++ U16 Reserved7; /* 0x36 */ ++ U32 IRNvsramVersion; /* 0x38 */ ++} MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, ++ Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; ++ ++#define MPI2_IOCPAGE6_PAGEVERSION (0x04) ++ ++/* defines for IOC Page 6 CapabilitiesFlags */ ++#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) ++#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) ++#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) ++#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) ++#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) ++ ++ ++/* IOC Page 7 */ ++ ++#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) ++ ++typedef struct _MPI2_CONFIG_PAGE_IOC_7 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U32 Reserved1; /* 0x04 */ ++ U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ ++ U16 SASBroadcastPrimitiveMasks; /* 0x18 */ ++ U16 Reserved2; /* 0x1A */ ++ U32 Reserved3; /* 0x1C */ ++} MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, ++ Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; ++ ++#define MPI2_IOCPAGE7_PAGEVERSION (0x01) ++ ++ ++/* IOC Page 8 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_IOC_8 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U8 NumDevsPerEnclosure; /* 0x04 */ ++ U8 Reserved1; /* 0x05 */ ++ U16 Reserved2; /* 0x06 */ ++ U16 MaxPersistentEntries; /* 0x08 */ ++ U16 MaxNumPhysicalMappedIDs; /* 0x0A */ ++ U16 Flags; /* 0x0C */ ++ U16 Reserved3; /* 0x0E */ ++ U16 IRVolumeMappingFlags; /* 0x10 */ ++ U16 Reserved4; /* 0x12 */ ++ U32 Reserved5; /* 0x14 */ ++} MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, ++ Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; ++ ++#define MPI2_IOCPAGE8_PAGEVERSION (0x00) ++ ++/* defines for IOC Page 8 Flags field */ ++#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) ++#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) ++ ++#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) ++#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) ++#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) ++ ++#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) ++#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) ++ ++/* defines for IOC Page 8 IRVolumeMappingFlags */ ++#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) ++#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) ++#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) ++ ++ ++/**************************************************************************** ++* BIOS Config Pages ++****************************************************************************/ ++ ++/* BIOS Page 1 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_BIOS_1 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U32 BiosOptions; /* 0x04 */ ++ U32 IOCSettings; /* 0x08 */ ++ U32 Reserved1; /* 0x0C */ ++ U32 DeviceSettings; /* 0x10 */ ++ U16 NumberOfDevices; /* 0x14 */ ++ U16 Reserved2; /* 0x16 */ ++ U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ ++ U16 IOTimeoutSequential; /* 0x1A */ ++ U16 IOTimeoutOther; /* 0x1C */ ++ U16 IOTimeoutBlockDevicesRM; /* 0x1E */ ++} MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, ++ Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; ++ ++#define MPI2_BIOSPAGE1_PAGEVERSION (0x04) ++ ++/* values for BIOS Page 1 BiosOptions field */ ++#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) ++ ++/* values for BIOS Page 1 IOCSettings field */ ++#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) ++#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) ++#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) ++ ++#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) ++#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) ++#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) ++#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) ++ ++#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) ++#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) ++#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) ++#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) ++#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) ++ ++#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) ++ ++/* values for BIOS Page 1 DeviceSettings field */ ++#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) ++#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) ++#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) ++#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) ++#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) ++ ++ ++/* BIOS Page 2 */ ++ ++typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER ++{ ++ U32 Reserved1; /* 0x00 */ ++ U32 Reserved2; /* 0x04 */ ++ U32 Reserved3; /* 0x08 */ ++ U32 Reserved4; /* 0x0C */ ++ U32 Reserved5; /* 0x10 */ ++ U32 Reserved6; /* 0x14 */ ++} MPI2_BOOT_DEVICE_ADAPTER_ORDER, ++ MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, ++ Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; ++ ++typedef struct _MPI2_BOOT_DEVICE_SAS_WWID ++{ ++ U64 SASAddress; /* 0x00 */ ++ U8 LUN[8]; /* 0x08 */ ++ U32 Reserved1; /* 0x10 */ ++ U32 Reserved2; /* 0x14 */ ++} MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, ++ Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; ++ ++typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT ++{ ++ U64 EnclosureLogicalID; /* 0x00 */ ++ U32 Reserved1; /* 0x08 */ ++ U32 Reserved2; /* 0x0C */ ++ U16 SlotNumber; /* 0x10 */ ++ U16 Reserved3; /* 0x12 */ ++ U32 Reserved4; /* 0x14 */ ++} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, ++ MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, ++ Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; ++ ++typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME ++{ ++ U64 DeviceName; /* 0x00 */ ++ U8 LUN[8]; /* 0x08 */ ++ U32 Reserved1; /* 0x10 */ ++ U32 Reserved2; /* 0x14 */ ++} MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, ++ Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; ++ ++typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE ++{ ++ MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; ++ MPI2_BOOT_DEVICE_SAS_WWID SasWwid; ++ MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; ++ MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; ++} MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, ++ Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; ++ ++typedef struct _MPI2_CONFIG_PAGE_BIOS_2 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U32 Reserved1; /* 0x04 */ ++ U32 Reserved2; /* 0x08 */ ++ U32 Reserved3; /* 0x0C */ ++ U32 Reserved4; /* 0x10 */ ++ U32 Reserved5; /* 0x14 */ ++ U32 Reserved6; /* 0x18 */ ++ U8 ReqBootDeviceForm; /* 0x1C */ ++ U8 Reserved7; /* 0x1D */ ++ U16 Reserved8; /* 0x1E */ ++ MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ ++ U8 ReqAltBootDeviceForm; /* 0x38 */ ++ U8 Reserved9; /* 0x39 */ ++ U16 Reserved10; /* 0x3A */ ++ MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ ++ U8 CurrentBootDeviceForm; /* 0x58 */ ++ U8 Reserved11; /* 0x59 */ ++ U16 Reserved12; /* 0x5A */ ++ MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ ++} MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, ++ Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; ++ ++#define MPI2_BIOSPAGE2_PAGEVERSION (0x04) ++ ++/* values for BIOS Page 2 BootDeviceForm fields */ ++#define MPI2_BIOSPAGE2_FORM_MASK (0x0F) ++#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) ++#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) ++#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) ++#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) ++ ++ ++/* BIOS Page 3 */ ++ ++typedef struct _MPI2_ADAPTER_INFO ++{ ++ U8 PciBusNumber; /* 0x00 */ ++ U8 PciDeviceAndFunctionNumber; /* 0x01 */ ++ U16 AdapterFlags; /* 0x02 */ ++} MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, ++ Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; ++ ++#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) ++#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) ++ ++typedef struct _MPI2_CONFIG_PAGE_BIOS_3 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U32 GlobalFlags; /* 0x04 */ ++ U32 BiosVersion; /* 0x08 */ ++ MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */ ++ U32 Reserved1; /* 0x1C */ ++} MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, ++ Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; ++ ++#define MPI2_BIOSPAGE3_PAGEVERSION (0x00) ++ ++/* values for BIOS Page 3 GlobalFlags */ ++#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) ++#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) ++#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) ++ ++#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) ++#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) ++#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) ++#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) ++ ++ ++/* BIOS Page 4 */ ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check Header.PageLength or NumPhys at runtime. ++ */ ++#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES ++#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) ++#endif ++ ++typedef struct _MPI2_BIOS4_ENTRY ++{ ++ U64 ReassignmentWWID; /* 0x00 */ ++ U64 ReassignmentDeviceName; /* 0x08 */ ++} MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, ++ Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; ++ ++typedef struct _MPI2_CONFIG_PAGE_BIOS_4 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U8 NumPhys; /* 0x04 */ ++ U8 Reserved1; /* 0x05 */ ++ U16 Reserved2; /* 0x06 */ ++ MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ ++} MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, ++ Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; ++ ++#define MPI2_BIOSPAGE4_PAGEVERSION (0x01) ++ ++ ++/**************************************************************************** ++* RAID Volume Config Pages ++****************************************************************************/ ++ ++/* RAID Volume Page 0 */ ++ ++typedef struct _MPI2_RAIDVOL0_PHYS_DISK ++{ ++ U8 RAIDSetNum; /* 0x00 */ ++ U8 PhysDiskMap; /* 0x01 */ ++ U8 PhysDiskNum; /* 0x02 */ ++ U8 Reserved; /* 0x03 */ ++} MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, ++ Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; ++ ++/* defines for the PhysDiskMap field */ ++#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) ++#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) ++ ++typedef struct _MPI2_RAIDVOL0_SETTINGS ++{ ++ U16 Settings; /* 0x00 */ ++ U8 HotSparePool; /* 0x01 */ ++ U8 Reserved; /* 0x02 */ ++} MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, ++ Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; ++ ++/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ ++#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) ++#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) ++#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) ++#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) ++#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) ++#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) ++#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) ++#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) ++ ++/* RAID Volume Page 0 VolumeSettings defines */ ++#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) ++#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) ++ ++#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) ++#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) ++#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) ++#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check Header.PageLength at runtime. ++ */ ++#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX ++#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) ++#endif ++ ++typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U16 DevHandle; /* 0x04 */ ++ U8 VolumeState; /* 0x06 */ ++ U8 VolumeType; /* 0x07 */ ++ U32 VolumeStatusFlags; /* 0x08 */ ++ MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ ++ U64 MaxLBA; /* 0x10 */ ++ U32 StripeSize; /* 0x18 */ ++ U16 BlockSize; /* 0x1C */ ++ U16 Reserved1; /* 0x1E */ ++ U8 SupportedPhysDisks; /* 0x20 */ ++ U8 ResyncRate; /* 0x21 */ ++ U16 DataScrubDuration; /* 0x22 */ ++ U8 NumPhysDisks; /* 0x24 */ ++ U8 Reserved2; /* 0x25 */ ++ U8 Reserved3; /* 0x26 */ ++ U8 InactiveStatus; /* 0x27 */ ++ MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ ++} MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, ++ Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; ++ ++#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) ++ ++/* values for RAID VolumeState */ ++#define MPI2_RAID_VOL_STATE_MISSING (0x00) ++#define MPI2_RAID_VOL_STATE_FAILED (0x01) ++#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) ++#define MPI2_RAID_VOL_STATE_ONLINE (0x03) ++#define MPI2_RAID_VOL_STATE_DEGRADED (0x04) ++#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) ++ ++/* values for RAID VolumeType */ ++#define MPI2_RAID_VOL_TYPE_RAID0 (0x00) ++#define MPI2_RAID_VOL_TYPE_RAID1E (0x01) ++#define MPI2_RAID_VOL_TYPE_RAID1 (0x02) ++#define MPI2_RAID_VOL_TYPE_RAID10 (0x05) ++#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) ++ ++/* values for RAID Volume Page 0 VolumeStatusFlags field */ ++#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) ++#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) ++#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) ++#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) ++#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) ++#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) ++#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) ++#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) ++#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) ++#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) ++#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) ++#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) ++#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) ++#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) ++#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) ++#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) ++#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) ++#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) ++ ++/* values for RAID Volume Page 0 SupportedPhysDisks field */ ++#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) ++#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) ++#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) ++#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) ++ ++/* values for RAID Volume Page 0 InactiveStatus field */ ++#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) ++#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) ++#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) ++#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) ++#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) ++#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) ++#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) ++ ++ ++/* RAID Volume Page 1 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U16 DevHandle; /* 0x04 */ ++ U16 Reserved0; /* 0x06 */ ++ U8 GUID[24]; /* 0x08 */ ++ U8 Name[16]; /* 0x20 */ ++ U64 WWID; /* 0x30 */ ++ U32 Reserved1; /* 0x38 */ ++ U32 Reserved2; /* 0x3C */ ++} MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, ++ Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; ++ ++#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) ++ ++ ++/**************************************************************************** ++* RAID Physical Disk Config Pages ++****************************************************************************/ ++ ++/* RAID Physical Disk Page 0 */ ++ ++typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS ++{ ++ U16 Reserved1; /* 0x00 */ ++ U8 HotSparePool; /* 0x02 */ ++ U8 Reserved2; /* 0x03 */ ++} MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, ++ Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; ++ ++/* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ ++ ++typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA ++{ ++ U8 VendorID[8]; /* 0x00 */ ++ U8 ProductID[16]; /* 0x08 */ ++ U8 ProductRevLevel[4]; /* 0x18 */ ++ U8 SerialNum[32]; /* 0x1C */ ++} MPI2_RAIDPHYSDISK0_INQUIRY_DATA, ++ MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, ++ Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; ++ ++typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U16 DevHandle; /* 0x04 */ ++ U8 Reserved1; /* 0x06 */ ++ U8 PhysDiskNum; /* 0x07 */ ++ MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ ++ U32 Reserved2; /* 0x0C */ ++ MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ ++ U32 Reserved3; /* 0x4C */ ++ U8 PhysDiskState; /* 0x50 */ ++ U8 OfflineReason; /* 0x51 */ ++ U8 IncompatibleReason; /* 0x52 */ ++ U8 PhysDiskAttributes; /* 0x53 */ ++ U32 PhysDiskStatusFlags; /* 0x54 */ ++ U64 DeviceMaxLBA; /* 0x58 */ ++ U64 HostMaxLBA; /* 0x60 */ ++ U64 CoercedMaxLBA; /* 0x68 */ ++ U16 BlockSize; /* 0x70 */ ++ U16 Reserved5; /* 0x72 */ ++ U32 Reserved6; /* 0x74 */ ++} MPI2_CONFIG_PAGE_RD_PDISK_0, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, ++ Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; ++ ++#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) ++ ++/* PhysDiskState defines */ ++#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) ++#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) ++#define MPI2_RAID_PD_STATE_OFFLINE (0x02) ++#define MPI2_RAID_PD_STATE_ONLINE (0x03) ++#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) ++#define MPI2_RAID_PD_STATE_DEGRADED (0x05) ++#define MPI2_RAID_PD_STATE_REBUILDING (0x06) ++#define MPI2_RAID_PD_STATE_OPTIMAL (0x07) ++ ++/* OfflineReason defines */ ++#define MPI2_PHYSDISK0_ONLINE (0x00) ++#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) ++#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) ++#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) ++#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) ++#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) ++#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) ++ ++/* IncompatibleReason defines */ ++#define MPI2_PHYSDISK0_COMPATIBLE (0x00) ++#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) ++#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) ++#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) ++#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) ++#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) ++#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) ++ ++/* PhysDiskAttributes defines */ ++#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) ++#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) ++#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) ++#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) ++ ++/* PhysDiskStatusFlags defines */ ++#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) ++#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) ++#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) ++#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) ++#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) ++#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) ++#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) ++#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) ++ ++ ++/* RAID Physical Disk Page 1 */ ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check Header.PageLength or NumPhysDiskPaths at runtime. ++ */ ++#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX ++#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) ++#endif ++ ++typedef struct _MPI2_RAIDPHYSDISK1_PATH ++{ ++ U16 DevHandle; /* 0x00 */ ++ U16 Reserved1; /* 0x02 */ ++ U64 WWID; /* 0x04 */ ++ U64 OwnerWWID; /* 0x0C */ ++ U8 OwnerIdentifier; /* 0x14 */ ++ U8 Reserved2; /* 0x15 */ ++ U16 Flags; /* 0x16 */ ++} MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, ++ Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; ++ ++/* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ ++#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) ++#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) ++#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) ++ ++typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 ++{ ++ MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ ++ U8 NumPhysDiskPaths; /* 0x04 */ ++ U8 PhysDiskNum; /* 0x05 */ ++ U16 Reserved1; /* 0x06 */ ++ U32 Reserved2; /* 0x08 */ ++ MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ ++} MPI2_CONFIG_PAGE_RD_PDISK_1, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, ++ Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; ++ ++#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) ++ ++ ++/**************************************************************************** ++* values for fields used by several types of SAS Config Pages ++****************************************************************************/ ++ ++/* values for NegotiatedLinkRates fields */ ++#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) ++#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) ++#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) ++/* link rates used for Negotiated Physical and Logical Link Rate */ ++#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) ++#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) ++#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) ++#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) ++#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) ++#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) ++#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) ++#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) ++#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) ++ ++ ++/* values for AttachedPhyInfo fields */ ++#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) ++#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) ++#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) ++ ++#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) ++#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) ++#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) ++#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) ++#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) ++#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) ++#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) ++#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) ++#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) ++#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) ++ ++ ++/* values for PhyInfo fields */ ++#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) ++#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) ++#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) ++#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) ++#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) ++#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) ++#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) ++ ++#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) ++#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) ++#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) ++#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) ++#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) ++#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) ++#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) ++#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) ++#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) ++#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) ++ ++#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) ++#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) ++#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) ++#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) ++ ++#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) ++#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) ++ ++#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) ++#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) ++#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) ++#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) ++ ++ ++/* values for SAS ProgrammedLinkRate fields */ ++#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) ++#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) ++#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) ++#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) ++#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) ++#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) ++#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) ++#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) ++#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) ++#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) ++ ++ ++/* values for SAS HwLinkRate fields */ ++#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) ++#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) ++#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) ++#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) ++#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) ++#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) ++#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) ++#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) ++ ++ ++ ++/**************************************************************************** ++* SAS IO Unit Config Pages ++****************************************************************************/ ++ ++/* SAS IO Unit Page 0 */ ++ ++typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA ++{ ++ U8 Port; /* 0x00 */ ++ U8 PortFlags; /* 0x01 */ ++ U8 PhyFlags; /* 0x02 */ ++ U8 NegotiatedLinkRate; /* 0x03 */ ++ U32 ControllerPhyDeviceInfo;/* 0x04 */ ++ U16 AttachedDevHandle; /* 0x08 */ ++ U16 ControllerDevHandle; /* 0x0A */ ++ U32 DiscoveryStatus; /* 0x0C */ ++ U32 Reserved; /* 0x10 */ ++} MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, ++ Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check Header.ExtPageLength or NumPhys at runtime. ++ */ ++#ifndef MPI2_SAS_IOUNIT0_PHY_MAX ++#define MPI2_SAS_IOUNIT0_PHY_MAX (1) ++#endif ++ ++typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ U32 Reserved1; /* 0x08 */ ++ U8 NumPhys; /* 0x0C */ ++ U8 Reserved2; /* 0x0D */ ++ U16 Reserved3; /* 0x0E */ ++ MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ ++} MPI2_CONFIG_PAGE_SASIOUNIT_0, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, ++ Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; ++ ++#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) ++ ++/* values for SAS IO Unit Page 0 PortFlags */ ++#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) ++#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) ++ ++/* values for SAS IO Unit Page 0 PhyFlags */ ++#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) ++#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) ++ ++/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ ++ ++/* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ ++ ++/* values for SAS IO Unit Page 0 DiscoveryStatus */ ++#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) ++#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) ++#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) ++#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) ++#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) ++#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) ++#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) ++#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) ++#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) ++#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) ++#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) ++#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) ++#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) ++#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) ++#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) ++#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) ++#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) ++#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) ++#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) ++#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) ++ ++ ++/* SAS IO Unit Page 1 */ ++ ++typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA ++{ ++ U8 Port; /* 0x00 */ ++ U8 PortFlags; /* 0x01 */ ++ U8 PhyFlags; /* 0x02 */ ++ U8 MaxMinLinkRate; /* 0x03 */ ++ U32 ControllerPhyDeviceInfo; /* 0x04 */ ++ U16 MaxTargetPortConnectTime; /* 0x08 */ ++ U16 Reserved1; /* 0x0A */ ++} MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, ++ Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check Header.ExtPageLength or NumPhys at runtime. ++ */ ++#ifndef MPI2_SAS_IOUNIT1_PHY_MAX ++#define MPI2_SAS_IOUNIT1_PHY_MAX (1) ++#endif ++ ++typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ U16 ControlFlags; /* 0x08 */ ++ U16 SASNarrowMaxQueueDepth; /* 0x0A */ ++ U16 AdditionalControlFlags; /* 0x0C */ ++ U16 SASWideMaxQueueDepth; /* 0x0E */ ++ U8 NumPhys; /* 0x10 */ ++ U8 SATAMaxQDepth; /* 0x11 */ ++ U8 ReportDeviceMissingDelay; /* 0x12 */ ++ U8 IODeviceMissingDelay; /* 0x13 */ ++ MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ ++} MPI2_CONFIG_PAGE_SASIOUNIT_1, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, ++ Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; ++ ++#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) ++ ++/* values for SAS IO Unit Page 1 ControlFlags */ ++#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) ++#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) ++#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) ++#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) ++ ++#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) ++#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) ++#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) ++#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) ++#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) ++ ++#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) ++#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) ++#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) ++#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) ++#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) ++#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) ++#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) ++#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) ++ ++/* values for SAS IO Unit Page 1 AdditionalControlFlags */ ++#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) ++#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) ++#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) ++#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) ++#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) ++#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) ++#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) ++#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) ++ ++/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ ++#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) ++#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) ++ ++/* values for SAS IO Unit Page 1 PortFlags */ ++#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) ++ ++/* values for SAS IO Unit Page 2 PhyFlags */ ++#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) ++#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) ++ ++/* values for SAS IO Unit Page 0 MaxMinLinkRate */ ++#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) ++#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) ++#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) ++#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) ++#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) ++#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) ++#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) ++#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) ++ ++/* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ ++ ++ ++/* SAS IO Unit Page 4 */ ++ ++typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP ++{ ++ U8 MaxTargetSpinup; /* 0x00 */ ++ U8 SpinupDelay; /* 0x01 */ ++ U16 Reserved1; /* 0x02 */ ++} MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, ++ Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * four and check Header.ExtPageLength or NumPhys at runtime. ++ */ ++#ifndef MPI2_SAS_IOUNIT4_PHY_MAX ++#define MPI2_SAS_IOUNIT4_PHY_MAX (4) ++#endif ++ ++typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ ++ U32 Reserved1; /* 0x18 */ ++ U32 Reserved2; /* 0x1C */ ++ U32 Reserved3; /* 0x20 */ ++ U8 BootDeviceWaitTime; /* 0x24 */ ++ U8 Reserved4; /* 0x25 */ ++ U16 Reserved5; /* 0x26 */ ++ U8 NumPhys; /* 0x28 */ ++ U8 PEInitialSpinupDelay; /* 0x29 */ ++ U8 PEReplyDelay; /* 0x2A */ ++ U8 Flags; /* 0x2B */ ++ U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ ++} MPI2_CONFIG_PAGE_SASIOUNIT_4, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, ++ Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; ++ ++#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) ++ ++/* defines for Flags field */ ++#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) ++ ++/* defines for PHY field */ ++#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) ++ ++ ++/**************************************************************************** ++* SAS Expander Config Pages ++****************************************************************************/ ++ ++/* SAS Expander Page 0 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ U8 PhysicalPort; /* 0x08 */ ++ U8 ReportGenLength; /* 0x09 */ ++ U16 EnclosureHandle; /* 0x0A */ ++ U64 SASAddress; /* 0x0C */ ++ U32 DiscoveryStatus; /* 0x14 */ ++ U16 DevHandle; /* 0x18 */ ++ U16 ParentDevHandle; /* 0x1A */ ++ U16 ExpanderChangeCount; /* 0x1C */ ++ U16 ExpanderRouteIndexes; /* 0x1E */ ++ U8 NumPhys; /* 0x20 */ ++ U8 SASLevel; /* 0x21 */ ++ U16 Flags; /* 0x22 */ ++ U16 STPBusInactivityTimeLimit; /* 0x24 */ ++ U16 STPMaxConnectTimeLimit; /* 0x26 */ ++ U16 STP_SMP_NexusLossTime; /* 0x28 */ ++ U16 MaxNumRoutedSasAddresses; /* 0x2A */ ++ U64 ActiveZoneManagerSASAddress;/* 0x2C */ ++ U16 ZoneLockInactivityLimit; /* 0x34 */ ++ U16 Reserved1; /* 0x36 */ ++} MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, ++ Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; ++ ++#define MPI2_SASEXPANDER0_PAGEVERSION (0x05) ++ ++/* values for SAS Expander Page 0 DiscoveryStatus field */ ++#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) ++#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) ++#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) ++#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) ++#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) ++#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) ++#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) ++#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) ++#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) ++#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) ++#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) ++#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) ++#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) ++#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) ++#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) ++#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) ++#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) ++#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) ++#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) ++#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) ++ ++/* values for SAS Expander Page 0 Flags field */ ++#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) ++#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) ++#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) ++#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) ++#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) ++#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) ++#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) ++#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) ++#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) ++#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) ++ ++ ++/* SAS Expander Page 1 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ U8 PhysicalPort; /* 0x08 */ ++ U8 Reserved1; /* 0x09 */ ++ U16 Reserved2; /* 0x0A */ ++ U8 NumPhys; /* 0x0C */ ++ U8 Phy; /* 0x0D */ ++ U16 NumTableEntriesProgrammed; /* 0x0E */ ++ U8 ProgrammedLinkRate; /* 0x10 */ ++ U8 HwLinkRate; /* 0x11 */ ++ U16 AttachedDevHandle; /* 0x12 */ ++ U32 PhyInfo; /* 0x14 */ ++ U32 AttachedDeviceInfo; /* 0x18 */ ++ U16 ExpanderDevHandle; /* 0x1C */ ++ U8 ChangeCount; /* 0x1E */ ++ U8 NegotiatedLinkRate; /* 0x1F */ ++ U8 PhyIdentifier; /* 0x20 */ ++ U8 AttachedPhyIdentifier; /* 0x21 */ ++ U8 Reserved3; /* 0x22 */ ++ U8 DiscoveryInfo; /* 0x23 */ ++ U32 AttachedPhyInfo; /* 0x24 */ ++ U8 ZoneGroup; /* 0x28 */ ++ U8 SelfConfigStatus; /* 0x29 */ ++ U16 Reserved4; /* 0x2A */ ++} MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, ++ Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; ++ ++#define MPI2_SASEXPANDER1_PAGEVERSION (0x02) ++ ++/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ ++ ++/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ ++ ++/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ ++ ++/* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ ++ ++/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ ++ ++/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ ++ ++/* values for SAS Expander Page 1 DiscoveryInfo field */ ++#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) ++#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) ++#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) ++ ++ ++/**************************************************************************** ++* SAS Device Config Pages ++****************************************************************************/ ++ ++/* SAS Device Page 0 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ U16 Slot; /* 0x08 */ ++ U16 EnclosureHandle; /* 0x0A */ ++ U64 SASAddress; /* 0x0C */ ++ U16 ParentDevHandle; /* 0x14 */ ++ U8 PhyNum; /* 0x16 */ ++ U8 AccessStatus; /* 0x17 */ ++ U16 DevHandle; /* 0x18 */ ++ U8 AttachedPhyIdentifier; /* 0x1A */ ++ U8 ZoneGroup; /* 0x1B */ ++ U32 DeviceInfo; /* 0x1C */ ++ U16 Flags; /* 0x20 */ ++ U8 PhysicalPort; /* 0x22 */ ++ U8 MaxPortConnections; /* 0x23 */ ++ U64 DeviceName; /* 0x24 */ ++ U8 PortGroups; /* 0x2C */ ++ U8 DmaGroup; /* 0x2D */ ++ U8 ControlGroup; /* 0x2E */ ++ U8 Reserved1; /* 0x2F */ ++ U32 Reserved2; /* 0x30 */ ++ U32 Reserved3; /* 0x34 */ ++} MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, ++ Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; ++ ++#define MPI2_SASDEVICE0_PAGEVERSION (0x08) ++ ++/* values for SAS Device Page 0 AccessStatus field */ ++#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) ++#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) ++#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) ++#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) ++#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) ++#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) ++#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) ++#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) ++/* specific values for SATA Init failures */ ++#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) ++#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) ++#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) ++#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) ++#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) ++#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) ++#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) ++#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) ++#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) ++#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) ++#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) ++ ++/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ ++ ++/* values for SAS Device Page 0 Flags field */ ++#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) ++#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) ++#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) ++#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) ++#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) ++#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) ++#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) ++#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) ++#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) ++ ++ ++/* SAS Device Page 1 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ U32 Reserved1; /* 0x08 */ ++ U64 SASAddress; /* 0x0C */ ++ U32 Reserved2; /* 0x14 */ ++ U16 DevHandle; /* 0x18 */ ++ U16 Reserved3; /* 0x1A */ ++ U8 InitialRegDeviceFIS[20];/* 0x1C */ ++} MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, ++ Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; ++ ++#define MPI2_SASDEVICE1_PAGEVERSION (0x01) ++ ++ ++/**************************************************************************** ++* SAS PHY Config Pages ++****************************************************************************/ ++ ++/* SAS PHY Page 0 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ U16 OwnerDevHandle; /* 0x08 */ ++ U16 Reserved1; /* 0x0A */ ++ U16 AttachedDevHandle; /* 0x0C */ ++ U8 AttachedPhyIdentifier; /* 0x0E */ ++ U8 Reserved2; /* 0x0F */ ++ U32 AttachedPhyInfo; /* 0x10 */ ++ U8 ProgrammedLinkRate; /* 0x14 */ ++ U8 HwLinkRate; /* 0x15 */ ++ U8 ChangeCount; /* 0x16 */ ++ U8 Flags; /* 0x17 */ ++ U32 PhyInfo; /* 0x18 */ ++ U8 NegotiatedLinkRate; /* 0x1C */ ++ U8 Reserved3; /* 0x1D */ ++ U16 Reserved4; /* 0x1E */ ++} MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, ++ Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; ++ ++#define MPI2_SASPHY0_PAGEVERSION (0x03) ++ ++/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ ++ ++/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ ++ ++/* values for SAS PHY Page 0 Flags field */ ++#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) ++ ++/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ ++ ++/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ ++ ++/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ ++ ++ ++/* SAS PHY Page 1 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ U32 Reserved1; /* 0x08 */ ++ U32 InvalidDwordCount; /* 0x0C */ ++ U32 RunningDisparityErrorCount; /* 0x10 */ ++ U32 LossDwordSynchCount; /* 0x14 */ ++ U32 PhyResetProblemCount; /* 0x18 */ ++} MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, ++ Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; ++ ++#define MPI2_SASPHY1_PAGEVERSION (0x01) ++ ++ ++/**************************************************************************** ++* SAS Port Config Pages ++****************************************************************************/ ++ ++/* SAS Port Page 0 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ U8 PortNumber; /* 0x08 */ ++ U8 PhysicalPort; /* 0x09 */ ++ U8 PortWidth; /* 0x0A */ ++ U8 PhysicalPortWidth; /* 0x0B */ ++ U8 ZoneGroup; /* 0x0C */ ++ U8 Reserved1; /* 0x0D */ ++ U16 Reserved2; /* 0x0E */ ++ U64 SASAddress; /* 0x10 */ ++ U32 DeviceInfo; /* 0x18 */ ++ U32 Reserved3; /* 0x1C */ ++ U32 Reserved4; /* 0x20 */ ++} MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, ++ Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; ++ ++#define MPI2_SASPORT0_PAGEVERSION (0x00) ++ ++/* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ ++ ++ ++/**************************************************************************** ++* SAS Enclosure Config Pages ++****************************************************************************/ ++ ++/* SAS Enclosure Page 0 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ U32 Reserved1; /* 0x08 */ ++ U64 EnclosureLogicalID; /* 0x0C */ ++ U16 Flags; /* 0x14 */ ++ U16 EnclosureHandle; /* 0x16 */ ++ U16 NumSlots; /* 0x18 */ ++ U16 StartSlot; /* 0x1A */ ++ U16 Reserved2; /* 0x1C */ ++ U16 SEPDevHandle; /* 0x1E */ ++ U32 Reserved3; /* 0x20 */ ++ U32 Reserved4; /* 0x24 */ ++} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, ++ Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t; ++ ++#define MPI2_SASENCLOSURE0_PAGEVERSION (0x03) ++ ++/* values for SAS Enclosure Page 0 Flags field */ ++#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) ++#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) ++#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) ++#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) ++#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) ++#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) ++#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) ++ ++ ++/**************************************************************************** ++* Log Config Page ++****************************************************************************/ ++ ++/* Log Page 0 */ ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check Header.ExtPageLength or NumPhys at runtime. ++ */ ++#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES ++#define MPI2_LOG_0_NUM_LOG_ENTRIES (1) ++#endif ++ ++#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) ++ ++typedef struct _MPI2_LOG_0_ENTRY ++{ ++ U64 TimeStamp; /* 0x00 */ ++ U32 Reserved1; /* 0x08 */ ++ U16 LogSequence; /* 0x0C */ ++ U16 LogEntryQualifier; /* 0x0E */ ++ U8 VP_ID; /* 0x10 */ ++ U8 VF_ID; /* 0x11 */ ++ U16 Reserved2; /* 0x12 */ ++ U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ ++} MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, ++ Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; ++ ++/* values for Log Page 0 LogEntry LogEntryQualifier field */ ++#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) ++#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) ++#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) ++#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) ++#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) ++ ++typedef struct _MPI2_CONFIG_PAGE_LOG_0 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ U32 Reserved1; /* 0x08 */ ++ U32 Reserved2; /* 0x0C */ ++ U16 NumLogEntries; /* 0x10 */ ++ U16 Reserved3; /* 0x12 */ ++ MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ ++} MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, ++ Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; ++ ++#define MPI2_LOG_0_PAGEVERSION (0x02) ++ ++ ++/**************************************************************************** ++* RAID Config Page ++****************************************************************************/ ++ ++/* RAID Page 0 */ ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check Header.ExtPageLength or NumPhys at runtime. ++ */ ++#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS ++#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) ++#endif ++ ++typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT ++{ ++ U16 ElementFlags; /* 0x00 */ ++ U16 VolDevHandle; /* 0x02 */ ++ U8 HotSparePool; /* 0x04 */ ++ U8 PhysDiskNum; /* 0x05 */ ++ U16 PhysDiskDevHandle; /* 0x06 */ ++} MPI2_RAIDCONFIG0_CONFIG_ELEMENT, ++ MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, ++ Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; ++ ++/* values for the ElementFlags field */ ++#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) ++#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) ++#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) ++#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) ++#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) ++ ++ ++typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ U8 NumHotSpares; /* 0x08 */ ++ U8 NumPhysDisks; /* 0x09 */ ++ U8 NumVolumes; /* 0x0A */ ++ U8 ConfigNum; /* 0x0B */ ++ U32 Flags; /* 0x0C */ ++ U8 ConfigGUID[24]; /* 0x10 */ ++ U32 Reserved1; /* 0x28 */ ++ U8 NumElements; /* 0x2C */ ++ U8 Reserved2; /* 0x2D */ ++ U16 Reserved3; /* 0x2E */ ++ MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ ++} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, ++ Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; ++ ++#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) ++ ++/* values for RAID Configuration Page 0 Flags field */ ++#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) ++ ++ ++/**************************************************************************** ++* Driver Persistent Mapping Config Pages ++****************************************************************************/ ++ ++/* Driver Persistent Mapping Page 0 */ ++ ++typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY ++{ ++ U64 PhysicalIdentifier; /* 0x00 */ ++ U16 MappingInformation; /* 0x08 */ ++ U16 DeviceIndex; /* 0x0A */ ++ U32 PhysicalBitsMapping; /* 0x0C */ ++ U32 Reserved1; /* 0x10 */ ++} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, ++ Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; ++ ++typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 ++{ ++ MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ ++ MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ ++} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, ++ Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; ++ ++#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) ++ ++/* values for Driver Persistent Mapping Page 0 MappingInformation field */ ++#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) ++#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) ++#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) ++ ++ ++#endif ++ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpi/mpi2_history.txt +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpi/mpi2_history.txt Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,294 @@ ++ ============================== ++ Fusion-MPT MPI 2.0 Header File Change History ++ ============================== ++ ++ Copyright (c) 2000-2009 LSI Corporation. ++ ++ --------------------------------------- ++ Header Set Release Version: 02.00.11 ++ Header Set Release Date: 01-19-09 ++ --------------------------------------- ++ ++ Filename Current version Prior version ++ ---------- --------------- ------------- ++ mpi2.h 02.00.11 02.00.10 ++ mpi2_cnfg.h 02.00.10 02.00.09 ++ mpi2_init.h 02.00.06 02.00.06 ++ mpi2_ioc.h 02.00.10 02.00.09 ++ mpi2_raid.h 02.00.03 02.00.03 ++ mpi2_sas.h 02.00.02 02.00.02 ++ mpi2_targ.h 02.00.03 02.00.03 ++ mpi2_tool.h 02.00.02 02.00.02 ++ mpi2_type.h 02.00.00 02.00.00 ++ mpi2_history.txt 02.00.11 02.00.10 ++ ++ ++ * Date Version Description ++ * -------- -------- ------------------------------------------------------ ++ ++mpi2.h ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. ++ * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. ++ * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. ++ * Moved ReplyPostHostIndex register to offset 0x6C of the ++ * MPI2_SYSTEM_INTERFACE_REGS and modified the define for ++ * MPI2_REPLY_POST_HOST_INDEX_OFFSET. ++ * Added union of request descriptors. ++ * Added union of reply descriptors. ++ * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. ++ * Added define for MPI2_VERSION_02_00. ++ * Fixed the size of the FunctionDependent5 field in the ++ * MPI2_DEFAULT_REPLY structure. ++ * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. ++ * Removed the MPI-defined Fault Codes and extended the ++ * product specific codes up to 0xEFFF. ++ * Added a sixth key value for the WriteSequence register ++ * and changed the flush value to 0x0. ++ * Added message function codes for Diagnostic Buffer Post ++ * and Diagnsotic Release. ++ * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED ++ * Moved MPI2_VERSION_UNION from mpi2_ioc.h. ++ * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. ++ * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. ++ * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. ++ * Added #defines for marking a reply descriptor as unused. ++ * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. ++ * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. ++ * Moved LUN field defines from mpi2_init.h. ++ * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. ++ * -------------------------------------------------------------------------- ++ ++mpi2_cnfg.h ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. ++ * Added Manufacturing Page 11. ++ * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE ++ * define. ++ * 06-26-07 02.00.02 Adding generic structure for product-specific ++ * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. ++ * Rework of BIOS Page 2 configuration page. ++ * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the ++ * forms. ++ * Added configuration pages IOC Page 8 and Driver ++ * Persistent Mapping Page 0. ++ * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated ++ * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, ++ * RAID Physical Disk Pages 0 and 1, RAID Configuration ++ * Page 0). ++ * Added new value for AccessStatus field of SAS Device ++ * Page 0 (_SATA_NEEDS_INITIALIZATION). ++ * 10-31-07 02.00.04 Added missing SEPDevHandle field to ++ * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. ++ * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for ++ * NVDATA. ++ * Modified IOC Page 7 to use masks and added field for ++ * SASBroadcastPrimitiveMasks. ++ * Added MPI2_CONFIG_PAGE_BIOS_4. ++ * Added MPI2_CONFIG_PAGE_LOG_0. ++ * 02-29-08 02.00.06 Modified various names to make them 32-character unique. ++ * Added SAS Device IDs. ++ * Updated Integrated RAID configuration pages including ++ * Manufacturing Page 4, IOC Page 6, and RAID Configuration ++ * Page 0. ++ * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. ++ * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. ++ * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. ++ * Added missing MaxNumRoutedSasAddresses field to ++ * MPI2_CONFIG_PAGE_EXPANDER_0. ++ * Added SAS Port Page 0. ++ * Modified structure layout for ++ * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. ++ * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use ++ * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. ++ * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF ++ * to 0x000000FF. ++ * Added two new values for the Physical Disk Coercion Size ++ * bits in the Flags field of Manufacturing Page 4. ++ * Added product-specific Manufacturing pages 16 to 31. ++ * Modified Flags bits for controlling write cache on SATA ++ * drives in IO Unit Page 1. ++ * Added new bit to AdditionalControlFlags of SAS IO Unit ++ * Page 1 to control Invalid Topology Correction. ++ * Added SupportedPhysDisks field to RAID Volume Page 1 and ++ * added related defines. ++ * Added additional defines for RAID Volume Page 0 ++ * VolumeStatusFlags field. ++ * Modified meaning of RAID Volume Page 0 VolumeSettings ++ * define for auto-configure of hot-swap drives. ++ * Added PhysDiskAttributes field (and related defines) to ++ * RAID Physical Disk Page 0. ++ * Added MPI2_SAS_PHYINFO_PHY_VACANT define. ++ * Added three new DiscoveryStatus bits for SAS IO Unit ++ * Page 0 and SAS Expander Page 0. ++ * Removed multiplexing information from SAS IO Unit pages. ++ * Added BootDeviceWaitTime field to SAS IO Unit Page 4. ++ * Removed Zone Address Resolved bit from PhyInfo and from ++ * Expander Page 0 Flags field. ++ * Added two new AccessStatus values to SAS Device Page 0 ++ * for indicating routing problems. Added 3 reserved words ++ * to this page. ++ * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. ++ * Inserted missing reserved field into structure for IOC ++ * Page 6. ++ * Added more pending task bits to RAID Volume Page 0 ++ * VolumeStatusFlags defines. ++ * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. ++ * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 ++ * and SAS Expander Page 0 to flag a downstream initiator ++ * when in simplified routing mode. ++ * Removed SATA Init Failure defines for DiscoveryStatus ++ * fields of SAS IO Unit Page 0 and SAS Expander Page 0. ++ * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. ++ * Added PortGroups, DmaGroup, and ControlGroup fields to ++ * SAS Device Page 0. ++ * -------------------------------------------------------------------------- ++ ++mpi2_init.h ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 10-31-07 02.00.01 Fixed name for pMpi2SCSITaskManagementRequest_t. ++ * 12-18-07 02.00.02 Modified Task Management Target Reset Method defines. ++ * 02-29-08 02.00.03 Added Query Task Set and Query Unit Attention. ++ * 03-03-08 02.00.04 Fixed name of struct _MPI2_SCSI_TASK_MANAGE_REPLY. ++ * 05-21-08 02.00.05 Fixed typo in name of Mpi2SepRequest_t. ++ * 10-02-08 02.00.06 Removed Untagged and No Disconnect values from SCSI IO ++ * Control field Task Attribute flags. ++ * Moved LUN field defines to mpi2.h becasue they are ++ * common to many structures. ++ * -------------------------------------------------------------------------- ++ ++mpi2_ioc.h ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to ++ * MaxTargets. ++ * Added TotalImageSize field to FWDownload Request. ++ * Added reserved words to FWUpload Request. ++ * 06-26-07 02.00.02 Added IR Configuration Change List Event. ++ * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit ++ * request and replaced it with ++ * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. ++ * Replaced the MinReplyQueueDepth field of the IOCFacts ++ * reply with MaxReplyDescriptorPostQueueDepth. ++ * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum ++ * depth for the Reply Descriptor Post Queue. ++ * Added SASAddress field to Initiator Device Table ++ * Overflow Event data. ++ * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING ++ * for SAS Initiator Device Status Change Event data. ++ * Modified Reason Code defines for SAS Topology Change ++ * List Event data, including adding a bit for PHY Vacant ++ * status, and adding a mask for the Reason Code. ++ * Added define for ++ * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. ++ * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. ++ * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of ++ * the IOCFacts Reply. ++ * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. ++ * Moved MPI2_VERSION_UNION to mpi2.h. ++ * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks ++ * instead of enables, and added SASBroadcastPrimitiveMasks ++ * field. ++ * Added Log Entry Added Event and related structure. ++ * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. ++ * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. ++ * Added MaxVolumes and MaxPersistentEntries fields to ++ * IOCFacts reply. ++ * Added ProtocalFlags and IOCCapabilities fields to ++ * MPI2_FW_IMAGE_HEADER. ++ * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. ++ * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to ++ * a U16 (from a U32). ++ * Removed extra 's' from EventMasks name. ++ * 06-27-08 02.00.08 Fixed an offset in a comment. ++ * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. ++ * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and ++ * renamed MinReplyFrameSize to ReplyFrameSize. ++ * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. ++ * Added two new RAIDOperation values for Integrated RAID ++ * Operations Status Event data. ++ * Added four new IR Configuration Change List Event data ++ * ReasonCode values. ++ * Added two new ReasonCode defines for SAS Device Status ++ * Change Event data. ++ * Added three new DiscoveryStatus bits for the SAS ++ * Discovery event data. ++ * Added Multiplexing Status Change bit to the PhyStatus ++ * field of the SAS Topology Change List event data. ++ * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. ++ * BootFlags are now product-specific. ++ * Added defines for the indivdual signature bytes ++ * for MPI2_INIT_IMAGE_FOOTER. ++ * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. ++ * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR ++ * define. ++ * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE ++ * define. ++ * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. ++ * -------------------------------------------------------------------------- ++ ++mpi2_raid.h ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 08-31-07 02.00.01 Modifications to RAID Action request and reply, ++ * including the Actions and ActionData. ++ * 02-29-08 02.00.02 Added MPI2_RAID_ACTION_ADATA_DISABL_FULL_REBUILD. ++ * 05-21-08 02.00.03 Added MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS so that ++ * the PhysDisk array in MPI2_RAID_VOLUME_CREATION_STRUCT ++ * can be sized by the build environment. ++ * -------------------------------------------------------------------------- ++ ++mpi2_sas.h ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 06-26-07 02.00.01 Added Clear All Persistent Operation to SAS IO Unit ++ * Control Request. ++ * 10-02-08 02.00.02 Added Set IOC Parameter Operation to SAS IO Unit Control ++ * Request. ++ * -------------------------------------------------------------------------- ++ ++mpi2_targ.h ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 08-31-07 02.00.01 Added Command Buffer Data Location Address Space bits to ++ * BufferPostFlags field of CommandBufferPostBase Request. ++ * 02-29-08 02.00.02 Modified various names to make them 32-character unique. ++ * 10-02-08 02.00.03 Removed NextCmdBufferOffset from ++ * MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST. ++ * Target Status Send Request only takes a single SGE for ++ * response data. ++ * -------------------------------------------------------------------------- ++ ++mpi2_tool.h ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 12-18-07 02.00.01 Added Diagnostic Buffer Post and Diagnostic Release ++ * structures and defines. ++ * 02-29-08 02.00.02 Modified various names to make them 32-character unique. ++ * -------------------------------------------------------------------------- ++ ++mpi2_type.h ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * -------------------------------------------------------------------------- ++ ++mpi2_history.txt Parts list history ++ ++Filename 02.00.11 02.00.10 02.00.09 02.00.08 02.00.07 02.00.06 ++---------- -------- -------- -------- -------- -------- -------- ++mpi2.h 02.00.11 02.00.10 02.00.09 02.00.08 02.00.07 02.00.06 ++mpi2_cnfg.h 02.00.10 02.00.09 02.00.08 02.00.07 02.00.06 02.00.06 ++mpi2_init.h 02.00.06 02.00.06 02.00.05 02.00.05 02.00.04 02.00.03 ++mpi2_ioc.h 02.00.10 02.00.09 02.00.08 02.00.07 02.00.07 02.00.06 ++mpi2_raid.h 02.00.03 02.00.03 02.00.03 02.00.03 02.00.02 02.00.02 ++mpi2_sas.h 02.00.02 02.00.02 02.00.01 02.00.01 02.00.01 02.00.01 ++mpi2_targ.h 02.00.03 02.00.03 02.00.02 02.00.02 02.00.02 02.00.02 ++mpi2_tool.h 02.00.02 02.00.02 02.00.02 02.00.02 02.00.02 02.00.02 ++mpi2_type.h 02.00.00 02.00.00 02.00.00 02.00.00 02.00.00 02.00.00 ++ ++Filename 02.00.05 02.00.04 02.00.03 02.00.02 02.00.01 02.00.00 ++---------- -------- -------- -------- -------- -------- -------- ++mpi2.h 02.00.05 02.00.04 02.00.03 02.00.02 02.00.01 02.00.00 ++mpi2_cnfg.h 02.00.05 02.00.04 02.00.03 02.00.02 02.00.01 02.00.00 ++mpi2_init.h 02.00.02 02.00.01 02.00.00 02.00.00 02.00.00 02.00.00 ++mpi2_ioc.h 02.00.05 02.00.04 02.00.03 02.00.02 02.00.01 02.00.00 ++mpi2_raid.h 02.00.01 02.00.01 02.00.01 02.00.00 02.00.00 02.00.00 ++mpi2_sas.h 02.00.01 02.00.01 02.00.01 02.00.01 02.00.00 02.00.00 ++mpi2_targ.h 02.00.01 02.00.01 02.00.01 02.00.00 02.00.00 02.00.00 ++mpi2_tool.h 02.00.01 02.00.00 02.00.00 02.00.00 02.00.00 02.00.00 ++mpi2_type.h 02.00.00 02.00.00 02.00.00 02.00.00 02.00.00 02.00.00 ++ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpi/mpi2_init.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpi/mpi2_init.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,420 @@ ++/* ++ * Copyright (c) 2000-2008 LSI Corporation. ++ * ++ * ++ * Name: mpi2_init.h ++ * Title: MPI SCSI initiator mode messages and structures ++ * Creation Date: June 23, 2006 ++ * ++ * mpi2_init.h Version: 02.00.06 ++ * ++ * Version History ++ * --------------- ++ * ++ * Date Version Description ++ * -------- -------- ------------------------------------------------------ ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 10-31-07 02.00.01 Fixed name for pMpi2SCSITaskManagementRequest_t. ++ * 12-18-07 02.00.02 Modified Task Management Target Reset Method defines. ++ * 02-29-08 02.00.03 Added Query Task Set and Query Unit Attention. ++ * 03-03-08 02.00.04 Fixed name of struct _MPI2_SCSI_TASK_MANAGE_REPLY. ++ * 05-21-08 02.00.05 Fixed typo in name of Mpi2SepRequest_t. ++ * 10-02-08 02.00.06 Removed Untagged and No Disconnect values from SCSI IO ++ * Control field Task Attribute flags. ++ * Moved LUN field defines to mpi2.h becasue they are ++ * common to many structures. ++ * -------------------------------------------------------------------------- ++ */ ++ ++#ifndef MPI2_INIT_H ++#define MPI2_INIT_H ++ ++/***************************************************************************** ++* ++* SCSI Initiator Messages ++* ++*****************************************************************************/ ++ ++/**************************************************************************** ++* SCSI IO messages and associated structures ++****************************************************************************/ ++ ++typedef struct ++{ ++ U8 CDB[20]; /* 0x00 */ ++ U32 PrimaryReferenceTag; /* 0x14 */ ++ U16 PrimaryApplicationTag; /* 0x18 */ ++ U16 PrimaryApplicationTagMask; /* 0x1A */ ++ U32 TransferLength; /* 0x1C */ ++} MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, ++ Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; ++ ++/* TBD: I don't think this is needed for MPI2/Gen2 */ ++#if 0 ++typedef struct ++{ ++ U8 CDB[16]; /* 0x00 */ ++ U32 DataLength; /* 0x10 */ ++ U32 PrimaryReferenceTag; /* 0x14 */ ++ U16 PrimaryApplicationTag; /* 0x18 */ ++ U16 PrimaryApplicationTagMask; /* 0x1A */ ++ U32 TransferLength; /* 0x1C */ ++} MPI2_SCSI_IO32_CDB_EEDP16, MPI2_POINTER PTR_MPI2_SCSI_IO32_CDB_EEDP16, ++ Mpi2ScsiIo32CdbEedp16_t, MPI2_POINTER pMpi2ScsiIo32CdbEedp16_t; ++#endif ++ ++typedef union ++{ ++ U8 CDB32[32]; ++ MPI2_SCSI_IO_CDB_EEDP32 EEDP32; ++ MPI2_SGE_SIMPLE_UNION SGE; ++} MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, ++ Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; ++ ++/* SCSI IO Request Message */ ++typedef struct _MPI2_SCSI_IO_REQUEST ++{ ++ U16 DevHandle; /* 0x00 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved1; /* 0x04 */ ++ U8 Reserved2; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++ U32 SenseBufferLowAddress; /* 0x0C */ ++ U16 SGLFlags; /* 0x10 */ ++ U8 SenseBufferLength; /* 0x12 */ ++ U8 Reserved4; /* 0x13 */ ++ U8 SGLOffset0; /* 0x14 */ ++ U8 SGLOffset1; /* 0x15 */ ++ U8 SGLOffset2; /* 0x16 */ ++ U8 SGLOffset3; /* 0x17 */ ++ U32 SkipCount; /* 0x18 */ ++ U32 DataLength; /* 0x1C */ ++ U32 BidirectionalDataLength; /* 0x20 */ ++ U16 IoFlags; /* 0x24 */ ++ U16 EEDPFlags; /* 0x26 */ ++ U32 EEDPBlockSize; /* 0x28 */ ++ U32 SecondaryReferenceTag; /* 0x2C */ ++ U16 SecondaryApplicationTag; /* 0x30 */ ++ U16 ApplicationTagTranslationMask; /* 0x32 */ ++ U8 LUN[8]; /* 0x34 */ ++ U32 Control; /* 0x3C */ ++ MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ ++ MPI2_SGE_IO_UNION SGL; /* 0x60 */ ++} MPI2_SCSI_IO_REQUEST, MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST, ++ Mpi2SCSIIORequest_t, MPI2_POINTER pMpi2SCSIIORequest_t; ++ ++/* SCSI IO MsgFlags bits */ ++ ++/* MsgFlags for SenseBufferAddressSpace */ ++#define MPI2_SCSIIO_MSGFLAGS_MASK_SENSE_ADDR (0x0C) ++#define MPI2_SCSIIO_MSGFLAGS_SYSTEM_SENSE_ADDR (0x00) ++#define MPI2_SCSIIO_MSGFLAGS_IOCDDR_SENSE_ADDR (0x04) ++#define MPI2_SCSIIO_MSGFLAGS_IOCPLB_SENSE_ADDR (0x08) ++#define MPI2_SCSIIO_MSGFLAGS_IOCPLBNTA_SENSE_ADDR (0x0C) ++ ++/* SCSI IO SGLFlags bits */ ++ ++/* base values for Data Location Address Space */ ++#define MPI2_SCSIIO_SGLFLAGS_ADDR_MASK (0x0C) ++#define MPI2_SCSIIO_SGLFLAGS_SYSTEM_ADDR (0x00) ++#define MPI2_SCSIIO_SGLFLAGS_IOCDDR_ADDR (0x04) ++#define MPI2_SCSIIO_SGLFLAGS_IOCPLB_ADDR (0x08) ++#define MPI2_SCSIIO_SGLFLAGS_IOCPLBNTA_ADDR (0x0C) ++ ++/* base values for Type */ ++#define MPI2_SCSIIO_SGLFLAGS_TYPE_MASK (0x03) ++#define MPI2_SCSIIO_SGLFLAGS_TYPE_MPI (0x00) ++#define MPI2_SCSIIO_SGLFLAGS_TYPE_IEEE32 (0x01) ++#define MPI2_SCSIIO_SGLFLAGS_TYPE_IEEE64 (0x02) ++ ++/* shift values for each sub-field */ ++#define MPI2_SCSIIO_SGLFLAGS_SGL3_SHIFT (12) ++#define MPI2_SCSIIO_SGLFLAGS_SGL2_SHIFT (8) ++#define MPI2_SCSIIO_SGLFLAGS_SGL1_SHIFT (4) ++#define MPI2_SCSIIO_SGLFLAGS_SGL0_SHIFT (0) ++ ++/* SCSI IO IoFlags bits */ ++ ++/* Large CDB Address Space */ ++#define MPI2_SCSIIO_CDB_ADDR_MASK (0x6000) ++#define MPI2_SCSIIO_CDB_ADDR_SYSTEM (0x0000) ++#define MPI2_SCSIIO_CDB_ADDR_IOCDDR (0x2000) ++#define MPI2_SCSIIO_CDB_ADDR_IOCPLB (0x4000) ++#define MPI2_SCSIIO_CDB_ADDR_IOCPLBNTA (0x6000) ++ ++#define MPI2_SCSIIO_IOFLAGS_LARGE_CDB (0x1000) ++#define MPI2_SCSIIO_IOFLAGS_BIDIRECTIONAL (0x0800) ++#define MPI2_SCSIIO_IOFLAGS_MULTICAST (0x0400) ++#define MPI2_SCSIIO_IOFLAGS_CMD_DETERMINES_DATA_DIR (0x0200) ++#define MPI2_SCSIIO_IOFLAGS_CDBLENGTH_MASK (0x01FF) ++ ++/* SCSI IO EEDPFlags bits */ ++ ++#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) ++#define MPI2_SCSIIO_EEDPFLAGS_INC_SEC_REFTAG (0x4000) ++#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_APPTAG (0x2000) ++#define MPI2_SCSIIO_EEDPFLAGS_INC_SEC_APPTAG (0x1000) ++ ++#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) ++#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) ++#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) ++ ++#define MPI2_SCSIIO_EEDPFLAGS_PASSTHRU_REFTAG (0x0008) ++ ++#define MPI2_SCSIIO_EEDPFLAGS_MASK_OP (0x0007) ++#define MPI2_SCSIIO_EEDPFLAGS_NOOP_OP (0x0000) ++#define MPI2_SCSIIO_EEDPFLAGS_CHECK_OP (0x0001) ++#define MPI2_SCSIIO_EEDPFLAGS_STRIP_OP (0x0002) ++#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) ++#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) ++#define MPI2_SCSIIO_EEDPFLAGS_REPLACE_OP (0x0006) ++#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REGEN_OP (0x0007) ++ ++/* SCSI IO LUN fields: use MPI2_LUN_ from mpi2.h */ ++ ++/* SCSI IO Control bits */ ++#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) ++#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) ++ ++#define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) ++#define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) ++#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) ++#define MPI2_SCSIIO_CONTROL_READ (0x02000000) ++#define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) ++ ++#define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) ++#define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) ++ ++#define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) ++#define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) ++#define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) ++#define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) ++#define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) ++ ++#define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) ++#define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) ++#define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) ++#define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) ++ ++ ++/* SCSI IO Error Reply Message */ ++typedef struct _MPI2_SCSI_IO_REPLY ++{ ++ U16 DevHandle; /* 0x00 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved1; /* 0x04 */ ++ U8 Reserved2; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++ U8 SCSIStatus; /* 0x0C */ ++ U8 SCSIState; /* 0x0D */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U32 TransferCount; /* 0x14 */ ++ U32 SenseCount; /* 0x18 */ ++ U32 ResponseInfo; /* 0x1C */ ++ U16 TaskTag; /* 0x20 */ ++ U16 Reserved4; /* 0x22 */ ++ U32 BidirectionalTransferCount; /* 0x24 */ ++ U32 Reserved5; /* 0x28 */ ++ U32 Reserved6; /* 0x2C */ ++} MPI2_SCSI_IO_REPLY, MPI2_POINTER PTR_MPI2_SCSI_IO_REPLY, ++ Mpi2SCSIIOReply_t, MPI2_POINTER pMpi2SCSIIOReply_t; ++ ++/* SCSI IO Reply SCSIStatus values (SAM-4 status codes) */ ++ ++#define MPI2_SCSI_STATUS_GOOD (0x00) ++#define MPI2_SCSI_STATUS_CHECK_CONDITION (0x02) ++#define MPI2_SCSI_STATUS_CONDITION_MET (0x04) ++#define MPI2_SCSI_STATUS_BUSY (0x08) ++#define MPI2_SCSI_STATUS_INTERMEDIATE (0x10) ++#define MPI2_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14) ++#define MPI2_SCSI_STATUS_RESERVATION_CONFLICT (0x18) ++#define MPI2_SCSI_STATUS_COMMAND_TERMINATED (0x22) /* obsolete */ ++#define MPI2_SCSI_STATUS_TASK_SET_FULL (0x28) ++#define MPI2_SCSI_STATUS_ACA_ACTIVE (0x30) ++#define MPI2_SCSI_STATUS_TASK_ABORTED (0x40) ++ ++/* SCSI IO Reply SCSIState flags */ ++ ++#define MPI2_SCSI_STATE_RESPONSE_INFO_VALID (0x10) ++#define MPI2_SCSI_STATE_TERMINATED (0x08) ++#define MPI2_SCSI_STATE_NO_SCSI_STATUS (0x04) ++#define MPI2_SCSI_STATE_AUTOSENSE_FAILED (0x02) ++#define MPI2_SCSI_STATE_AUTOSENSE_VALID (0x01) ++ ++#define MPI2_SCSI_TASKTAG_UNKNOWN (0xFFFF) ++ ++ ++/**************************************************************************** ++* SCSI Task Management messages ++****************************************************************************/ ++ ++/* SCSI Task Management Request Message */ ++typedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST ++{ ++ U16 DevHandle; /* 0x00 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U8 Reserved1; /* 0x04 */ ++ U8 TaskType; /* 0x05 */ ++ U8 Reserved2; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++ U8 LUN[8]; /* 0x0C */ ++ U32 Reserved4[7]; /* 0x14 */ ++ U16 TaskMID; /* 0x30 */ ++ U16 Reserved5; /* 0x32 */ ++} MPI2_SCSI_TASK_MANAGE_REQUEST, ++ MPI2_POINTER PTR_MPI2_SCSI_TASK_MANAGE_REQUEST, ++ Mpi2SCSITaskManagementRequest_t, ++ MPI2_POINTER pMpi2SCSITaskManagementRequest_t; ++ ++/* TaskType values */ ++ ++#define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) ++#define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) ++#define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) ++#define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) ++#define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06) ++#define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07) ++#define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08) ++#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09) ++#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION (0x0A) ++ ++/* MsgFlags bits */ ++ ++#define MPI2_SCSITASKMGMT_MSGFLAGS_MASK_TARGET_RESET (0x18) ++#define MPI2_SCSITASKMGMT_MSGFLAGS_LINK_RESET (0x00) ++#define MPI2_SCSITASKMGMT_MSGFLAGS_NEXUS_RESET_SRST (0x08) ++#define MPI2_SCSITASKMGMT_MSGFLAGS_SAS_HARD_LINK_RESET (0x10) ++ ++#define MPI2_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x01) ++ ++ ++ ++/* SCSI Task Management Reply Message */ ++typedef struct _MPI2_SCSI_TASK_MANAGE_REPLY ++{ ++ U16 DevHandle; /* 0x00 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U8 ResponseCode; /* 0x04 */ ++ U8 TaskType; /* 0x05 */ ++ U8 Reserved1; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved2; /* 0x0A */ ++ U16 Reserved3; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U32 TerminationCount; /* 0x14 */ ++} MPI2_SCSI_TASK_MANAGE_REPLY, ++ MPI2_POINTER PTR_MPI2_SCSI_TASK_MANAGE_REPLY, ++ Mpi2SCSITaskManagementReply_t, MPI2_POINTER pMpi2SCSIManagementReply_t; ++ ++/* ResponseCode values */ ++ ++#define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00) ++#define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02) ++#define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04) ++#define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05) ++#define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08) ++#define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09) ++#define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80) ++ ++ ++/**************************************************************************** ++* SCSI Enclosure Processor messages ++****************************************************************************/ ++ ++/* SCSI Enclosure Processor Request Message */ ++typedef struct _MPI2_SEP_REQUEST ++{ ++ U16 DevHandle; /* 0x00 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U8 Action; /* 0x04 */ ++ U8 Flags; /* 0x05 */ ++ U8 Reserved1; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved2; /* 0x0A */ ++ U32 SlotStatus; /* 0x0C */ ++ U32 Reserved3; /* 0x10 */ ++ U32 Reserved4; /* 0x14 */ ++ U32 Reserved5; /* 0x18 */ ++ U16 Slot; /* 0x1C */ ++ U16 EnclosureHandle; /* 0x1E */ ++} MPI2_SEP_REQUEST, MPI2_POINTER PTR_MPI2_SEP_REQUEST, ++ Mpi2SepRequest_t, MPI2_POINTER pMpi2SepRequest_t; ++ ++/* Action defines */ ++#define MPI2_SEP_REQ_ACTION_WRITE_STATUS (0x00) ++#define MPI2_SEP_REQ_ACTION_READ_STATUS (0x01) ++ ++/* Flags defines */ ++#define MPI2_SEP_REQ_FLAGS_DEVHANDLE_ADDRESS (0x00) ++#define MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS (0x01) ++ ++/* SlotStatus defines */ ++#define MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000) ++#define MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) ++#define MPI2_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200) ++#define MPI2_SEP_REQ_SLOTSTATUS_HOT_SPARE (0x00000100) ++#define MPI2_SEP_REQ_SLOTSTATUS_UNCONFIGURED (0x00000080) ++#define MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT (0x00000040) ++#define MPI2_SEP_REQ_SLOTSTATUS_DEV_REBUILDING (0x00000004) ++#define MPI2_SEP_REQ_SLOTSTATUS_DEV_FAULTY (0x00000002) ++#define MPI2_SEP_REQ_SLOTSTATUS_NO_ERROR (0x00000001) ++ ++ ++/* SCSI Enclosure Processor Reply Message */ ++typedef struct _MPI2_SEP_REPLY ++{ ++ U16 DevHandle; /* 0x00 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U8 Action; /* 0x04 */ ++ U8 Flags; /* 0x05 */ ++ U8 Reserved1; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved2; /* 0x0A */ ++ U16 Reserved3; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U32 SlotStatus; /* 0x14 */ ++ U32 Reserved4; /* 0x18 */ ++ U16 Slot; /* 0x1C */ ++ U16 EnclosureHandle; /* 0x1E */ ++} MPI2_SEP_REPLY, MPI2_POINTER PTR_MPI2_SEP_REPLY, ++ Mpi2SepReply_t, MPI2_POINTER pMpi2SepReply_t; ++ ++/* SlotStatus defines */ ++#define MPI2_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000) ++#define MPI2_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) ++#define MPI2_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200) ++#define MPI2_SEP_REPLY_SLOTSTATUS_HOT_SPARE (0x00000100) ++#define MPI2_SEP_REPLY_SLOTSTATUS_UNCONFIGURED (0x00000080) ++#define MPI2_SEP_REPLY_SLOTSTATUS_PREDICTED_FAULT (0x00000040) ++#define MPI2_SEP_REPLY_SLOTSTATUS_DEV_REBUILDING (0x00000004) ++#define MPI2_SEP_REPLY_SLOTSTATUS_DEV_FAULTY (0x00000002) ++#define MPI2_SEP_REPLY_SLOTSTATUS_NO_ERROR (0x00000001) ++ ++ ++#endif ++ ++ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpi/mpi2_ioc.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpi/mpi2_ioc.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,1295 @@ ++/* ++ * Copyright (c) 2000-2009 LSI Corporation. ++ * ++ * ++ * Name: mpi2_ioc.h ++ * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages ++ * Creation Date: October 11, 2006 ++ * ++ * mpi2_ioc.h Version: 02.00.10 ++ * ++ * Version History ++ * --------------- ++ * ++ * Date Version Description ++ * -------- -------- ------------------------------------------------------ ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to ++ * MaxTargets. ++ * Added TotalImageSize field to FWDownload Request. ++ * Added reserved words to FWUpload Request. ++ * 06-26-07 02.00.02 Added IR Configuration Change List Event. ++ * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit ++ * request and replaced it with ++ * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. ++ * Replaced the MinReplyQueueDepth field of the IOCFacts ++ * reply with MaxReplyDescriptorPostQueueDepth. ++ * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum ++ * depth for the Reply Descriptor Post Queue. ++ * Added SASAddress field to Initiator Device Table ++ * Overflow Event data. ++ * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING ++ * for SAS Initiator Device Status Change Event data. ++ * Modified Reason Code defines for SAS Topology Change ++ * List Event data, including adding a bit for PHY Vacant ++ * status, and adding a mask for the Reason Code. ++ * Added define for ++ * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. ++ * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. ++ * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of ++ * the IOCFacts Reply. ++ * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. ++ * Moved MPI2_VERSION_UNION to mpi2.h. ++ * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks ++ * instead of enables, and added SASBroadcastPrimitiveMasks ++ * field. ++ * Added Log Entry Added Event and related structure. ++ * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. ++ * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. ++ * Added MaxVolumes and MaxPersistentEntries fields to ++ * IOCFacts reply. ++ * Added ProtocalFlags and IOCCapabilities fields to ++ * MPI2_FW_IMAGE_HEADER. ++ * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. ++ * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to ++ * a U16 (from a U32). ++ * Removed extra 's' from EventMasks name. ++ * 06-27-08 02.00.08 Fixed an offset in a comment. ++ * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. ++ * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and ++ * renamed MinReplyFrameSize to ReplyFrameSize. ++ * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. ++ * Added two new RAIDOperation values for Integrated RAID ++ * Operations Status Event data. ++ * Added four new IR Configuration Change List Event data ++ * ReasonCode values. ++ * Added two new ReasonCode defines for SAS Device Status ++ * Change Event data. ++ * Added three new DiscoveryStatus bits for the SAS ++ * Discovery event data. ++ * Added Multiplexing Status Change bit to the PhyStatus ++ * field of the SAS Topology Change List event data. ++ * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. ++ * BootFlags are now product-specific. ++ * Added defines for the indivdual signature bytes ++ * for MPI2_INIT_IMAGE_FOOTER. ++ * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. ++ * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR ++ * define. ++ * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE ++ * define. ++ * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. ++ * -------------------------------------------------------------------------- ++ */ ++ ++#ifndef MPI2_IOC_H ++#define MPI2_IOC_H ++ ++/***************************************************************************** ++* ++* IOC Messages ++* ++*****************************************************************************/ ++ ++/**************************************************************************** ++* IOCInit message ++****************************************************************************/ ++ ++/* IOCInit Request message */ ++typedef struct _MPI2_IOC_INIT_REQUEST ++{ ++ U8 WhoInit; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U16 MsgVersion; /* 0x0C */ ++ U16 HeaderVersion; /* 0x0E */ ++ U32 Reserved5; /* 0x10 */ ++ U32 Reserved6; /* 0x14 */ ++ U16 Reserved7; /* 0x18 */ ++ U16 SystemRequestFrameSize; /* 0x1A */ ++ U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ ++ U16 ReplyFreeQueueDepth; /* 0x1E */ ++ U32 SenseBufferAddressHigh; /* 0x20 */ ++ U32 SystemReplyAddressHigh; /* 0x24 */ ++ U64 SystemRequestFrameBaseAddress; /* 0x28 */ ++ U64 ReplyDescriptorPostQueueAddress;/* 0x30 */ ++ U64 ReplyFreeQueueAddress; /* 0x38 */ ++ U64 TimeStamp; /* 0x40 */ ++} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, ++ Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; ++ ++/* WhoInit values */ ++#define MPI2_WHOINIT_NOT_INITIALIZED (0x00) ++#define MPI2_WHOINIT_SYSTEM_BIOS (0x01) ++#define MPI2_WHOINIT_ROM_BIOS (0x02) ++#define MPI2_WHOINIT_PCI_PEER (0x03) ++#define MPI2_WHOINIT_HOST_DRIVER (0x04) ++#define MPI2_WHOINIT_MANUFACTURER (0x05) ++ ++/* MsgVersion */ ++#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) ++#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) ++#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) ++#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) ++ ++/* HeaderVersion */ ++#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) ++#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) ++#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) ++#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) ++ ++/* minimum depth for the Reply Descriptor Post Queue */ ++#define MPI2_RDPQ_DEPTH_MIN (16) ++ ++ ++/* IOCInit Reply message */ ++typedef struct _MPI2_IOC_INIT_REPLY ++{ ++ U8 WhoInit; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U16 Reserved5; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++} MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY, ++ Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t; ++ ++ ++/**************************************************************************** ++* IOCFacts message ++****************************************************************************/ ++ ++/* IOCFacts Request message */ ++typedef struct _MPI2_IOC_FACTS_REQUEST ++{ ++ U16 Reserved1; /* 0x00 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++} MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST, ++ Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t; ++ ++ ++/* IOCFacts Reply message */ ++typedef struct _MPI2_IOC_FACTS_REPLY ++{ ++ U16 MsgVersion; /* 0x00 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 HeaderVersion; /* 0x04 */ ++ U8 IOCNumber; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved1; /* 0x0A */ ++ U16 IOCExceptions; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U8 MaxChainDepth; /* 0x14 */ ++ U8 WhoInit; /* 0x15 */ ++ U8 NumberOfPorts; /* 0x16 */ ++ U8 Reserved2; /* 0x17 */ ++ U16 RequestCredit; /* 0x18 */ ++ U16 ProductID; /* 0x1A */ ++ U32 IOCCapabilities; /* 0x1C */ ++ MPI2_VERSION_UNION FWVersion; /* 0x20 */ ++ U16 IOCRequestFrameSize; /* 0x24 */ ++ U16 Reserved3; /* 0x26 */ ++ U16 MaxInitiators; /* 0x28 */ ++ U16 MaxTargets; /* 0x2A */ ++ U16 MaxSasExpanders; /* 0x2C */ ++ U16 MaxEnclosures; /* 0x2E */ ++ U16 ProtocolFlags; /* 0x30 */ ++ U16 HighPriorityCredit; /* 0x32 */ ++ U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */ ++ U8 ReplyFrameSize; /* 0x36 */ ++ U8 MaxVolumes; /* 0x37 */ ++ U16 MaxDevHandle; /* 0x38 */ ++ U16 MaxPersistentEntries; /* 0x3A */ ++ U32 Reserved4; /* 0x3C */ ++} MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, ++ Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; ++ ++/* MsgVersion */ ++#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) ++#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) ++#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) ++#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) ++ ++/* HeaderVersion */ ++#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) ++#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) ++#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) ++#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) ++ ++/* IOCExceptions */ ++#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) ++ ++#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) ++#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) ++#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) ++#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) ++#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) ++ ++#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) ++#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) ++#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) ++#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) ++#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) ++ ++/* defines for WhoInit field are after the IOCInit Request */ ++ ++/* ProductID field uses MPI2_FW_HEADER_PID_ */ ++ ++/* IOCCapabilities */ ++#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) ++#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) ++#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) ++#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) ++#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) ++#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) ++#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) ++#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) ++#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) ++ ++/* ProtocolFlags */ ++#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) ++#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) ++ ++ ++/**************************************************************************** ++* PortFacts message ++****************************************************************************/ ++ ++/* PortFacts Request message */ ++typedef struct _MPI2_PORT_FACTS_REQUEST ++{ ++ U16 Reserved1; /* 0x00 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 PortNumber; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++} MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST, ++ Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t; ++ ++/* PortFacts Reply message */ ++typedef struct _MPI2_PORT_FACTS_REPLY ++{ ++ U16 Reserved1; /* 0x00 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 PortNumber; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++ U16 Reserved4; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U8 Reserved5; /* 0x14 */ ++ U8 PortType; /* 0x15 */ ++ U16 Reserved6; /* 0x16 */ ++ U16 MaxPostedCmdBuffers; /* 0x18 */ ++ U16 Reserved7; /* 0x1A */ ++} MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY, ++ Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t; ++ ++/* PortType values */ ++#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) ++#define MPI2_PORTFACTS_PORTTYPE_FC (0x10) ++#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) ++#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) ++#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) ++ ++ ++/**************************************************************************** ++* PortEnable message ++****************************************************************************/ ++ ++/* PortEnable Request message */ ++typedef struct _MPI2_PORT_ENABLE_REQUEST ++{ ++ U16 Reserved1; /* 0x00 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U8 Reserved2; /* 0x04 */ ++ U8 PortFlags; /* 0x05 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++} MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST, ++ Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t; ++ ++ ++/* PortEnable Reply message */ ++typedef struct _MPI2_PORT_ENABLE_REPLY ++{ ++ U16 Reserved1; /* 0x00 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U8 Reserved2; /* 0x04 */ ++ U8 PortFlags; /* 0x05 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U16 Reserved5; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++} MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY, ++ Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t; ++ ++ ++/**************************************************************************** ++* EventNotification message ++****************************************************************************/ ++ ++/* EventNotification Request message */ ++#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) ++ ++typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST ++{ ++ U16 Reserved1; /* 0x00 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U32 Reserved5; /* 0x0C */ ++ U32 Reserved6; /* 0x10 */ ++ U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */ ++ U16 SASBroadcastPrimitiveMasks; /* 0x24 */ ++ U16 Reserved7; /* 0x26 */ ++ U32 Reserved8; /* 0x28 */ ++} MPI2_EVENT_NOTIFICATION_REQUEST, ++ MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST, ++ Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t; ++ ++ ++/* EventNotification Reply message */ ++typedef struct _MPI2_EVENT_NOTIFICATION_REPLY ++{ ++ U16 EventDataLength; /* 0x00 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved1; /* 0x04 */ ++ U8 AckRequired; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved2; /* 0x0A */ ++ U16 Reserved3; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U16 Event; /* 0x14 */ ++ U16 Reserved4; /* 0x16 */ ++ U32 EventContext; /* 0x18 */ ++ U32 EventData[1]; /* 0x1C */ ++} MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY, ++ Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t; ++ ++/* AckRequired */ ++#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) ++#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) ++ ++/* Event */ ++#define MPI2_EVENT_LOG_DATA (0x0001) ++#define MPI2_EVENT_STATE_CHANGE (0x0002) ++#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) ++#define MPI2_EVENT_EVENT_CHANGE (0x000A) ++#define MPI2_EVENT_TASK_SET_FULL (0x000E) ++#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) ++#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) ++#define MPI2_EVENT_SAS_DISCOVERY (0x0016) ++#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) ++#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) ++#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) ++#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) ++#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) ++#define MPI2_EVENT_IR_VOLUME (0x001E) ++#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) ++#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) ++#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) ++ ++ ++/* Log Entry Added Event data */ ++ ++/* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ ++#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) ++ ++typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED ++{ ++ U64 TimeStamp; /* 0x00 */ ++ U32 Reserved1; /* 0x08 */ ++ U16 LogSequence; /* 0x0C */ ++ U16 LogEntryQualifier; /* 0x0E */ ++ U8 VP_ID; /* 0x10 */ ++ U8 VF_ID; /* 0x11 */ ++ U16 Reserved2; /* 0x12 */ ++ U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */ ++} MPI2_EVENT_DATA_LOG_ENTRY_ADDED, ++ MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, ++ Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; ++ ++/* Hard Reset Received Event data */ ++ ++typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED ++{ ++ U8 Reserved1; /* 0x00 */ ++ U8 Port; /* 0x01 */ ++ U16 Reserved2; /* 0x02 */ ++} MPI2_EVENT_DATA_HARD_RESET_RECEIVED, ++ MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, ++ Mpi2EventDataHardResetReceived_t, ++ MPI2_POINTER pMpi2EventDataHardResetReceived_t; ++ ++/* Task Set Full Event data */ ++ ++typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL ++{ ++ U16 DevHandle; /* 0x00 */ ++ U16 CurrentDepth; /* 0x02 */ ++} MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL, ++ Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t; ++ ++ ++/* SAS Device Status Change Event data */ ++ ++typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE ++{ ++ U16 TaskTag; /* 0x00 */ ++ U8 ReasonCode; /* 0x02 */ ++ U8 Reserved1; /* 0x03 */ ++ U8 ASC; /* 0x04 */ ++ U8 ASCQ; /* 0x05 */ ++ U16 DevHandle; /* 0x06 */ ++ U32 Reserved2; /* 0x08 */ ++ U64 SASAddress; /* 0x0C */ ++ U8 LUN[8]; /* 0x14 */ ++} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, ++ MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, ++ Mpi2EventDataSasDeviceStatusChange_t, ++ MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t; ++ ++/* SAS Device Status Change Event data ReasonCode values */ ++#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) ++#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) ++#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) ++#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) ++#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) ++#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) ++#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) ++#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) ++#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) ++#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) ++#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) ++ ++ ++/* Integrated RAID Operation Status Event data */ ++ ++typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS ++{ ++ U16 VolDevHandle; /* 0x00 */ ++ U16 Reserved1; /* 0x02 */ ++ U8 RAIDOperation; /* 0x04 */ ++ U8 PercentComplete; /* 0x05 */ ++ U16 Reserved2; /* 0x06 */ ++ U32 Resereved3; /* 0x08 */ ++} MPI2_EVENT_DATA_IR_OPERATION_STATUS, ++ MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, ++ Mpi2EventDataIrOperationStatus_t, ++ MPI2_POINTER pMpi2EventDataIrOperationStatus_t; ++ ++/* Integrated RAID Operation Status Event data RAIDOperation values */ ++#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) ++#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) ++#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) ++#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) ++#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) ++ ++ ++/* Integrated RAID Volume Event data */ ++ ++typedef struct _MPI2_EVENT_DATA_IR_VOLUME ++{ ++ U16 VolDevHandle; /* 0x00 */ ++ U8 ReasonCode; /* 0x02 */ ++ U8 Reserved1; /* 0x03 */ ++ U32 NewValue; /* 0x04 */ ++ U32 PreviousValue; /* 0x08 */ ++} MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME, ++ Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t; ++ ++/* Integrated RAID Volume Event data ReasonCode values */ ++#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) ++#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) ++#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) ++ ++ ++/* Integrated RAID Physical Disk Event data */ ++ ++typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK ++{ ++ U16 Reserved1; /* 0x00 */ ++ U8 ReasonCode; /* 0x02 */ ++ U8 PhysDiskNum; /* 0x03 */ ++ U16 PhysDiskDevHandle; /* 0x04 */ ++ U16 Reserved2; /* 0x06 */ ++ U16 Slot; /* 0x08 */ ++ U16 EnclosureHandle; /* 0x0A */ ++ U32 NewValue; /* 0x0C */ ++ U32 PreviousValue; /* 0x10 */ ++} MPI2_EVENT_DATA_IR_PHYSICAL_DISK, ++ MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, ++ Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t; ++ ++/* Integrated RAID Physical Disk Event data ReasonCode values */ ++#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) ++#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) ++#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) ++ ++ ++/* Integrated RAID Configuration Change List Event data */ ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check NumElements at runtime. ++ */ ++#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT ++#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) ++#endif ++ ++typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT ++{ ++ U16 ElementFlags; /* 0x00 */ ++ U16 VolDevHandle; /* 0x02 */ ++ U8 ReasonCode; /* 0x04 */ ++ U8 PhysDiskNum; /* 0x05 */ ++ U16 PhysDiskDevHandle; /* 0x06 */ ++} MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, ++ Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t; ++ ++/* IR Configuration Change List Event data ElementFlags values */ ++#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) ++#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) ++#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) ++#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) ++ ++/* IR Configuration Change List Event data ReasonCode values */ ++#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) ++#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) ++#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) ++#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) ++#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) ++#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) ++#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) ++#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) ++#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) ++ ++typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST ++{ ++ U8 NumElements; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 Reserved2; /* 0x02 */ ++ U8 ConfigNum; /* 0x03 */ ++ U32 Flags; /* 0x04 */ ++ MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */ ++} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, ++ MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, ++ Mpi2EventDataIrConfigChangeList_t, ++ MPI2_POINTER pMpi2EventDataIrConfigChangeList_t; ++ ++/* IR Configuration Change List Event data Flags values */ ++#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) ++ ++ ++/* SAS Discovery Event data */ ++ ++typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY ++{ ++ U8 Flags; /* 0x00 */ ++ U8 ReasonCode; /* 0x01 */ ++ U8 PhysicalPort; /* 0x02 */ ++ U8 Reserved1; /* 0x03 */ ++ U32 DiscoveryStatus; /* 0x04 */ ++} MPI2_EVENT_DATA_SAS_DISCOVERY, ++ MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, ++ Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t; ++ ++/* SAS Discovery Event data Flags values */ ++#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) ++#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) ++ ++/* SAS Discovery Event data ReasonCode values */ ++#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) ++#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) ++ ++/* SAS Discovery Event data DiscoveryStatus values */ ++#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) ++#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) ++#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) ++#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) ++#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) ++#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) ++#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) ++#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) ++#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) ++#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) ++#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) ++#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) ++#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) ++#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) ++#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) ++#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) ++#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) ++#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) ++#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) ++#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) ++ ++ ++/* SAS Broadcast Primitive Event data */ ++ ++typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE ++{ ++ U8 PhyNum; /* 0x00 */ ++ U8 Port; /* 0x01 */ ++ U8 PortWidth; /* 0x02 */ ++ U8 Primitive; /* 0x03 */ ++} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, ++ MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, ++ Mpi2EventDataSasBroadcastPrimitive_t, ++ MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t; ++ ++/* defines for the Primitive field */ ++#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) ++#define MPI2_EVENT_PRIMITIVE_SES (0x02) ++#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) ++#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) ++#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) ++#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) ++#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) ++#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) ++ ++ ++/* SAS Initiator Device Status Change Event data */ ++ ++typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE ++{ ++ U8 ReasonCode; /* 0x00 */ ++ U8 PhysicalPort; /* 0x01 */ ++ U16 DevHandle; /* 0x02 */ ++ U64 SASAddress; /* 0x04 */ ++} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, ++ MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, ++ Mpi2EventDataSasInitDevStatusChange_t, ++ MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t; ++ ++/* SAS Initiator Device Status Change event ReasonCode values */ ++#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) ++#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) ++ ++ ++/* SAS Initiator Device Table Overflow Event data */ ++ ++typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW ++{ ++ U16 MaxInit; /* 0x00 */ ++ U16 CurrentInit; /* 0x02 */ ++ U64 SASAddress; /* 0x04 */ ++} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, ++ MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, ++ Mpi2EventDataSasInitTableOverflow_t, ++ MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t; ++ ++ ++/* SAS Topology Change List Event data */ ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check NumEntries at runtime. ++ */ ++#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT ++#define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) ++#endif ++ ++typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY ++{ ++ U16 AttachedDevHandle; /* 0x00 */ ++ U8 LinkRate; /* 0x02 */ ++ U8 PhyStatus; /* 0x03 */ ++} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, ++ Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t; ++ ++typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST ++{ ++ U16 EnclosureHandle; /* 0x00 */ ++ U16 ExpanderDevHandle; /* 0x02 */ ++ U8 NumPhys; /* 0x04 */ ++ U8 Reserved1; /* 0x05 */ ++ U16 Reserved2; /* 0x06 */ ++ U8 NumEntries; /* 0x08 */ ++ U8 StartPhyNum; /* 0x09 */ ++ U8 ExpStatus; /* 0x0A */ ++ U8 PhysicalPort; /* 0x0B */ ++ MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ ++} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, ++ MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, ++ Mpi2EventDataSasTopologyChangeList_t, ++ MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t; ++ ++/* values for the ExpStatus field */ ++#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) ++#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) ++#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) ++#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) ++ ++/* defines for the LinkRate field */ ++#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) ++#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) ++#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) ++#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) ++ ++#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) ++#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) ++#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) ++#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) ++#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) ++#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) ++#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) ++#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) ++#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) ++ ++/* values for the PhyStatus field */ ++#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) ++#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) ++/* values for the PhyStatus ReasonCode sub-field */ ++#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) ++#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) ++#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) ++#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) ++#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) ++#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) ++ ++ ++/* SAS Enclosure Device Status Change Event data */ ++ ++typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE ++{ ++ U16 EnclosureHandle; /* 0x00 */ ++ U8 ReasonCode; /* 0x02 */ ++ U8 PhysicalPort; /* 0x03 */ ++ U64 EnclosureLogicalID; /* 0x04 */ ++ U16 NumSlots; /* 0x0C */ ++ U16 StartSlot; /* 0x0E */ ++ U32 PhyBits; /* 0x10 */ ++} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, ++ MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, ++ Mpi2EventDataSasEnclDevStatusChange_t, ++ MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t; ++ ++/* SAS Enclosure Device Status Change event ReasonCode values */ ++#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) ++#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) ++ ++ ++/**************************************************************************** ++* EventAck message ++****************************************************************************/ ++ ++/* EventAck Request message */ ++typedef struct _MPI2_EVENT_ACK_REQUEST ++{ ++ U16 Reserved1; /* 0x00 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U16 Event; /* 0x0C */ ++ U16 Reserved5; /* 0x0E */ ++ U32 EventContext; /* 0x10 */ ++} MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST, ++ Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t; ++ ++ ++/* EventAck Reply message */ ++typedef struct _MPI2_EVENT_ACK_REPLY ++{ ++ U16 Reserved1; /* 0x00 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U16 Reserved5; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++} MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY, ++ Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t; ++ ++ ++/**************************************************************************** ++* FWDownload message ++****************************************************************************/ ++ ++/* FWDownload Request message */ ++typedef struct _MPI2_FW_DOWNLOAD_REQUEST ++{ ++ U8 ImageType; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U32 TotalImageSize; /* 0x0C */ ++ U32 Reserved5; /* 0x10 */ ++ MPI2_MPI_SGE_UNION SGL; /* 0x14 */ ++} MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST, ++ Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest; ++ ++#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) ++ ++#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) ++#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) ++#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) ++#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) ++#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) ++#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) ++#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) ++ ++/* FWDownload TransactionContext Element */ ++typedef struct _MPI2_FW_DOWNLOAD_TCSGE ++{ ++ U8 Reserved1; /* 0x00 */ ++ U8 ContextSize; /* 0x01 */ ++ U8 DetailsLength; /* 0x02 */ ++ U8 Flags; /* 0x03 */ ++ U32 Reserved2; /* 0x04 */ ++ U32 ImageOffset; /* 0x08 */ ++ U32 ImageSize; /* 0x0C */ ++} MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE, ++ Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t; ++ ++/* FWDownload Reply message */ ++typedef struct _MPI2_FW_DOWNLOAD_REPLY ++{ ++ U8 ImageType; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U16 Reserved5; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++} MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY, ++ Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t; ++ ++ ++/**************************************************************************** ++* FWUpload message ++****************************************************************************/ ++ ++/* FWUpload Request message */ ++typedef struct _MPI2_FW_UPLOAD_REQUEST ++{ ++ U8 ImageType; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U32 Reserved5; /* 0x0C */ ++ U32 Reserved6; /* 0x10 */ ++ MPI2_MPI_SGE_UNION SGL; /* 0x14 */ ++} MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST, ++ Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t; ++ ++#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) ++#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) ++#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) ++#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) ++#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) ++#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) ++#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) ++#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) ++#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) ++#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) ++ ++typedef struct _MPI2_FW_UPLOAD_TCSGE ++{ ++ U8 Reserved1; /* 0x00 */ ++ U8 ContextSize; /* 0x01 */ ++ U8 DetailsLength; /* 0x02 */ ++ U8 Flags; /* 0x03 */ ++ U32 Reserved2; /* 0x04 */ ++ U32 ImageOffset; /* 0x08 */ ++ U32 ImageSize; /* 0x0C */ ++} MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE, ++ Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t; ++ ++/* FWUpload Reply message */ ++typedef struct _MPI2_FW_UPLOAD_REPLY ++{ ++ U8 ImageType; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U16 Reserved5; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U32 ActualImageSize; /* 0x14 */ ++} MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, ++ Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; ++ ++ ++/* FW Image Header */ ++typedef struct _MPI2_FW_IMAGE_HEADER ++{ ++ U32 Signature; /* 0x00 */ ++ U32 Signature0; /* 0x04 */ ++ U32 Signature1; /* 0x08 */ ++ U32 Signature2; /* 0x0C */ ++ MPI2_VERSION_UNION MPIVersion; /* 0x10 */ ++ MPI2_VERSION_UNION FWVersion; /* 0x14 */ ++ MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */ ++ MPI2_VERSION_UNION PackageVersion; /* 0x1C */ ++ U16 VendorID; /* 0x20 */ ++ U16 ProductID; /* 0x22 */ ++ U16 ProtocolFlags; /* 0x24 */ ++ U16 Reserved26; /* 0x26 */ ++ U32 IOCCapabilities; /* 0x28 */ ++ U32 ImageSize; /* 0x2C */ ++ U32 NextImageHeaderOffset; /* 0x30 */ ++ U32 Checksum; /* 0x34 */ ++ U32 Reserved38; /* 0x38 */ ++ U32 Reserved3C; /* 0x3C */ ++ U32 Reserved40; /* 0x40 */ ++ U32 Reserved44; /* 0x44 */ ++ U32 Reserved48; /* 0x48 */ ++ U32 Reserved4C; /* 0x4C */ ++ U32 Reserved50; /* 0x50 */ ++ U32 Reserved54; /* 0x54 */ ++ U32 Reserved58; /* 0x58 */ ++ U32 Reserved5C; /* 0x5C */ ++ U32 Reserved60; /* 0x60 */ ++ U32 FirmwareVersionNameWhat; /* 0x64 */ ++ U8 FirmwareVersionName[32]; /* 0x68 */ ++ U32 VendorNameWhat; /* 0x88 */ ++ U8 VendorName[32]; /* 0x8C */ ++ U32 PackageNameWhat; /* 0x88 */ ++ U8 PackageName[32]; /* 0x8C */ ++ U32 ReservedD0; /* 0xD0 */ ++ U32 ReservedD4; /* 0xD4 */ ++ U32 ReservedD8; /* 0xD8 */ ++ U32 ReservedDC; /* 0xDC */ ++ U32 ReservedE0; /* 0xE0 */ ++ U32 ReservedE4; /* 0xE4 */ ++ U32 ReservedE8; /* 0xE8 */ ++ U32 ReservedEC; /* 0xEC */ ++ U32 ReservedF0; /* 0xF0 */ ++ U32 ReservedF4; /* 0xF4 */ ++ U32 ReservedF8; /* 0xF8 */ ++ U32 ReservedFC; /* 0xFC */ ++} MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER, ++ Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t; ++ ++/* Signature field */ ++#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) ++#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) ++#define MPI2_FW_HEADER_SIGNATURE (0xEA000000) ++ ++/* Signature0 field */ ++#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) ++#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) ++ ++/* Signature1 field */ ++#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) ++#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) ++ ++/* Signature2 field */ ++#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) ++#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) ++ ++ ++/* defines for using the ProductID field */ ++#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) ++#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) ++ ++#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) ++#define MPI2_FW_HEADER_PID_PROD_A (0x0000) ++ ++#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) ++/* SAS */ ++#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0010) ++ ++/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ ++ ++/* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ ++ ++ ++#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) ++#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) ++#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) ++ ++#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) ++ ++#define MPI2_FW_HEADER_SIZE (0x100) ++ ++ ++/* Extended Image Header */ ++typedef struct _MPI2_EXT_IMAGE_HEADER ++ ++{ ++ U8 ImageType; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U16 Reserved2; /* 0x02 */ ++ U32 Checksum; /* 0x04 */ ++ U32 ImageSize; /* 0x08 */ ++ U32 NextImageHeaderOffset; /* 0x0C */ ++ U32 PackageVersion; /* 0x10 */ ++ U32 Reserved3; /* 0x14 */ ++ U32 Reserved4; /* 0x18 */ ++ U32 Reserved5; /* 0x1C */ ++ U8 IdentifyString[32]; /* 0x20 */ ++} MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER, ++ Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t; ++ ++/* useful offsets */ ++#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) ++#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) ++#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) ++ ++#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) ++ ++/* defines for the ImageType field */ ++#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) ++#define MPI2_EXT_IMAGE_TYPE_FW (0x01) ++#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) ++#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) ++#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) ++#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) ++#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) ++#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) ++ ++#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID) ++ ++ ++ ++/* FLASH Layout Extended Image Data */ ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check RegionsPerLayout at runtime. ++ */ ++#ifndef MPI2_FLASH_NUMBER_OF_REGIONS ++#define MPI2_FLASH_NUMBER_OF_REGIONS (1) ++#endif ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check NumberOfLayouts at runtime. ++ */ ++#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS ++#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) ++#endif ++ ++typedef struct _MPI2_FLASH_REGION ++{ ++ U8 RegionType; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U16 Reserved2; /* 0x02 */ ++ U32 RegionOffset; /* 0x04 */ ++ U32 RegionSize; /* 0x08 */ ++ U32 Reserved3; /* 0x0C */ ++} MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION, ++ Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t; ++ ++typedef struct _MPI2_FLASH_LAYOUT ++{ ++ U32 FlashSize; /* 0x00 */ ++ U32 Reserved1; /* 0x04 */ ++ U32 Reserved2; /* 0x08 */ ++ U32 Reserved3; /* 0x0C */ ++ MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */ ++} MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT, ++ Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t; ++ ++typedef struct _MPI2_FLASH_LAYOUT_DATA ++{ ++ U8 ImageRevision; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 SizeOfRegion; /* 0x02 */ ++ U8 Reserved2; /* 0x03 */ ++ U16 NumberOfLayouts; /* 0x04 */ ++ U16 RegionsPerLayout; /* 0x06 */ ++ U16 MinimumSectorAlignment; /* 0x08 */ ++ U16 Reserved3; /* 0x0A */ ++ U32 Reserved4; /* 0x0C */ ++ MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */ ++} MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA, ++ Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t; ++ ++/* defines for the RegionType field */ ++#define MPI2_FLASH_REGION_UNUSED (0x00) ++#define MPI2_FLASH_REGION_FIRMWARE (0x01) ++#define MPI2_FLASH_REGION_BIOS (0x02) ++#define MPI2_FLASH_REGION_NVDATA (0x03) ++#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) ++#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) ++#define MPI2_FLASH_REGION_CONFIG_1 (0x07) ++#define MPI2_FLASH_REGION_CONFIG_2 (0x08) ++#define MPI2_FLASH_REGION_MEGARAID (0x09) ++#define MPI2_FLASH_REGION_INIT (0x0A) ++ ++/* ImageRevision */ ++#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) ++ ++ ++ ++/* Supported Devices Extended Image Data */ ++ ++/* ++ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to ++ * one and check NumberOfDevices at runtime. ++ */ ++#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES ++#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) ++#endif ++ ++typedef struct _MPI2_SUPPORTED_DEVICE ++{ ++ U16 DeviceID; /* 0x00 */ ++ U16 VendorID; /* 0x02 */ ++ U16 DeviceIDMask; /* 0x04 */ ++ U16 Reserved1; /* 0x06 */ ++ U8 LowPCIRev; /* 0x08 */ ++ U8 HighPCIRev; /* 0x09 */ ++ U16 Reserved2; /* 0x0A */ ++ U32 Reserved3; /* 0x0C */ ++} MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE, ++ Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t; ++ ++typedef struct _MPI2_SUPPORTED_DEVICES_DATA ++{ ++ U8 ImageRevision; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 NumberOfDevices; /* 0x02 */ ++ U8 Reserved2; /* 0x03 */ ++ U32 Reserved3; /* 0x04 */ ++ MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */ ++} MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA, ++ Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t; ++ ++/* ImageRevision */ ++#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) ++ ++ ++/* Init Extended Image Data */ ++ ++typedef struct _MPI2_INIT_IMAGE_FOOTER ++ ++{ ++ U32 BootFlags; /* 0x00 */ ++ U32 ImageSize; /* 0x04 */ ++ U32 Signature0; /* 0x08 */ ++ U32 Signature1; /* 0x0C */ ++ U32 Signature2; /* 0x10 */ ++ U32 ResetVector; /* 0x14 */ ++} MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER, ++ Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t; ++ ++/* defines for the BootFlags field */ ++#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) ++ ++/* defines for the ImageSize field */ ++#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) ++ ++/* defines for the Signature0 field */ ++#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) ++#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) ++ ++/* defines for the Signature1 field */ ++#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) ++#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) ++ ++/* defines for the Signature2 field */ ++#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) ++#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) ++ ++/* Signature fields as individual bytes */ ++#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) ++#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) ++#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) ++#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) ++ ++#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) ++#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) ++#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) ++#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) ++ ++#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) ++#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) ++#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) ++#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) ++ ++/* defines for the ResetVector field */ ++#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) ++ ++ ++#endif ++ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpi/mpi2_ra.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpi/mpi2_ra.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,85 @@ ++/* ++ * Copyright (c) 2009 LSI Corporation. ++ * ++ * ++ * Name: mpi2_ra.h ++ * Title: MPI RAID Accelerator messages and structures ++ * Creation Date: April 13, 2009 ++ * ++ * mpi2_ra.h Version: 02.00.00 ++ * ++ * Version History ++ * --------------- ++ * ++ * Date Version Description ++ * -------- -------- ------------------------------------------------------ ++ * 05-06-09 02.00.00 Initial version. ++ * -------------------------------------------------------------------------- ++ */ ++ ++#ifndef MPI2_RA_H ++#define MPI2_RA_H ++ ++/* generic structure for RAID Accelerator Control Block */ ++typedef struct _MPI2_RAID_ACCELERATOR_CONTROL_BLOCK ++{ ++ U32 Reserved[8]; /* 0x00 */ ++ U32 RaidAcceleratorCDB[1]; /* 0x20 */ ++} MPI2_RAID_ACCELERATOR_CONTROL_BLOCK, ++ MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_CONTROL_BLOCK, ++ Mpi2RAIDAcceleratorControlBlock_t, ++ MPI2_POINTER pMpi2RAIDAcceleratorControlBlock_t; ++ ++ ++/****************************************************************************** ++* ++* RAID Accelerator Messages ++* ++*******************************************************************************/ ++ ++/* RAID Accelerator Request Message */ ++typedef struct _MPI2_RAID_ACCELERATOR_REQUEST ++{ ++ U16 Reserved0; /* 0x00 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved1; /* 0x04 */ ++ U8 Reserved2; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++ U64 RaidAcceleratorControlBlockAddress; /* 0x0C */ ++ U8 DmaEngineNumber; /* 0x14 */ ++ U8 Reserved4; /* 0x15 */ ++ U16 Reserved5; /* 0x16 */ ++ U32 Reserved6; /* 0x18 */ ++ U32 Reserved7; /* 0x1C */ ++ U32 Reserved8; /* 0x20 */ ++} MPI2_RAID_ACCELERATOR_REQUEST, MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_REQUEST, ++ Mpi2RAIDAcceleratorRequest_t, MPI2_POINTER pMpi2RAIDAcceleratorRequest_t; ++ ++ ++/* RAID Accelerator Error Reply Message */ ++typedef struct _MPI2_RAID_ACCELERATOR_REPLY ++{ ++ U16 Reserved0; /* 0x00 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved1; /* 0x04 */ ++ U8 Reserved2; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++ U16 Reserved4; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U32 ProductSpecificData[3]; /* 0x14 */ ++} MPI2_RAID_ACCELERATOR_REPLY, MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_REPLY, ++ Mpi2RAIDAcceleratorReply_t, MPI2_POINTER pMpi2RAIDAcceleratorReply_t; ++ ++ ++#endif ++ ++ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpi/mpi2_raid.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpi/mpi2_raid.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,295 @@ ++/* ++ * Copyright (c) 2000-2008 LSI Corporation. ++ * ++ * ++ * Name: mpi2_raid.h ++ * Title: MPI Integrated RAID messages and structures ++ * Creation Date: April 26, 2007 ++ * ++ * mpi2_raid.h Version: 02.00.03 ++ * ++ * Version History ++ * --------------- ++ * ++ * Date Version Description ++ * -------- -------- ------------------------------------------------------ ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 08-31-07 02.00.01 Modifications to RAID Action request and reply, ++ * including the Actions and ActionData. ++ * 02-29-08 02.00.02 Added MPI2_RAID_ACTION_ADATA_DISABL_FULL_REBUILD. ++ * 05-21-08 02.00.03 Added MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS so that ++ * the PhysDisk array in MPI2_RAID_VOLUME_CREATION_STRUCT ++ * can be sized by the build environment. ++ * -------------------------------------------------------------------------- ++ */ ++ ++#ifndef MPI2_RAID_H ++#define MPI2_RAID_H ++ ++/***************************************************************************** ++* ++* Integrated RAID Messages ++* ++*****************************************************************************/ ++ ++/**************************************************************************** ++* RAID Action messages ++****************************************************************************/ ++ ++/* ActionDataWord defines for use with MPI2_RAID_ACTION_DELETE_VOLUME action */ ++#define MPI2_RAID_ACTION_ADATA_KEEP_LBA0 (0x00000000) ++#define MPI2_RAID_ACTION_ADATA_ZERO_LBA0 (0x00000001) ++ ++/* use MPI2_RAIDVOL0_SETTING_ defines from mpi2_cnfg.h for MPI2_RAID_ACTION_CHANGE_VOL_WRITE_CACHE action */ ++ ++/* ActionDataWord defines for use with MPI2_RAID_ACTION_DISABLE_ALL_VOLUMES action */ ++#define MPI2_RAID_ACTION_ADATA_DISABL_FULL_REBUILD (0x00000001) ++ ++/* ActionDataWord for MPI2_RAID_ACTION_SET_RAID_FUNCTION_RATE Action */ ++typedef struct _MPI2_RAID_ACTION_RATE_DATA ++{ ++ U8 RateToChange; /* 0x00 */ ++ U8 RateOrMode; /* 0x01 */ ++ U16 DataScrubDuration; /* 0x02 */ ++} MPI2_RAID_ACTION_RATE_DATA, MPI2_POINTER PTR_MPI2_RAID_ACTION_RATE_DATA, ++ Mpi2RaidActionRateData_t, MPI2_POINTER pMpi2RaidActionRateData_t; ++ ++#define MPI2_RAID_ACTION_SET_RATE_RESYNC (0x00) ++#define MPI2_RAID_ACTION_SET_RATE_DATA_SCRUB (0x01) ++#define MPI2_RAID_ACTION_SET_RATE_POWERSAVE_MODE (0x02) ++ ++/* ActionDataWord for MPI2_RAID_ACTION_START_RAID_FUNCTION Action */ ++typedef struct _MPI2_RAID_ACTION_START_RAID_FUNCTION ++{ ++ U8 RAIDFunction; /* 0x00 */ ++ U8 Flags; /* 0x01 */ ++ U16 Reserved1; /* 0x02 */ ++} MPI2_RAID_ACTION_START_RAID_FUNCTION, ++ MPI2_POINTER PTR_MPI2_RAID_ACTION_START_RAID_FUNCTION, ++ Mpi2RaidActionStartRaidFunction_t, ++ MPI2_POINTER pMpi2RaidActionStartRaidFunction_t; ++ ++/* defines for the RAIDFunction field */ ++#define MPI2_RAID_ACTION_START_BACKGROUND_INIT (0x00) ++#define MPI2_RAID_ACTION_START_ONLINE_CAP_EXPANSION (0x01) ++#define MPI2_RAID_ACTION_START_CONSISTENCY_CHECK (0x02) ++ ++/* defines for the Flags field */ ++#define MPI2_RAID_ACTION_START_NEW (0x00) ++#define MPI2_RAID_ACTION_START_RESUME (0x01) ++ ++/* ActionDataWord for MPI2_RAID_ACTION_STOP_RAID_FUNCTION Action */ ++typedef struct _MPI2_RAID_ACTION_STOP_RAID_FUNCTION ++{ ++ U8 RAIDFunction; /* 0x00 */ ++ U8 Flags; /* 0x01 */ ++ U16 Reserved1; /* 0x02 */ ++} MPI2_RAID_ACTION_STOP_RAID_FUNCTION, ++ MPI2_POINTER PTR_MPI2_RAID_ACTION_STOP_RAID_FUNCTION, ++ Mpi2RaidActionStopRaidFunction_t, ++ MPI2_POINTER pMpi2RaidActionStopRaidFunction_t; ++ ++/* defines for the RAIDFunction field */ ++#define MPI2_RAID_ACTION_STOP_BACKGROUND_INIT (0x00) ++#define MPI2_RAID_ACTION_STOP_ONLINE_CAP_EXPANSION (0x01) ++#define MPI2_RAID_ACTION_STOP_CONSISTENCY_CHECK (0x02) ++ ++/* defines for the Flags field */ ++#define MPI2_RAID_ACTION_STOP_ABORT (0x00) ++#define MPI2_RAID_ACTION_STOP_PAUSE (0x01) ++ ++/* ActionDataWord for MPI2_RAID_ACTION_CREATE_HOT_SPARE Action */ ++typedef struct _MPI2_RAID_ACTION_HOT_SPARE ++{ ++ U8 HotSparePool; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U16 DevHandle; /* 0x02 */ ++} MPI2_RAID_ACTION_HOT_SPARE, MPI2_POINTER PTR_MPI2_RAID_ACTION_HOT_SPARE, ++ Mpi2RaidActionHotSpare_t, MPI2_POINTER pMpi2RaidActionHotSpare_t; ++ ++/* ActionDataWord for MPI2_RAID_ACTION_DEVICE_FW_UPDATE_MODE Action */ ++typedef struct _MPI2_RAID_ACTION_FW_UPDATE_MODE ++{ ++ U8 Flags; /* 0x00 */ ++ U8 DeviceFirmwareUpdateModeTimeout; /* 0x01 */ ++ U16 Reserved1; /* 0x02 */ ++} MPI2_RAID_ACTION_FW_UPDATE_MODE, ++ MPI2_POINTER PTR_MPI2_RAID_ACTION_FW_UPDATE_MODE, ++ Mpi2RaidActionFwUpdateMode_t, MPI2_POINTER pMpi2RaidActionFwUpdateMode_t; ++ ++/* ActionDataWord defines for use with MPI2_RAID_ACTION_DEVICE_FW_UPDATE_MODE action */ ++#define MPI2_RAID_ACTION_ADATA_DISABLE_FW_UPDATE (0x00) ++#define MPI2_RAID_ACTION_ADATA_ENABLE_FW_UPDATE (0x01) ++ ++typedef union _MPI2_RAID_ACTION_DATA ++{ ++ U32 Word; ++ MPI2_RAID_ACTION_RATE_DATA Rates; ++ MPI2_RAID_ACTION_START_RAID_FUNCTION StartRaidFunction; ++ MPI2_RAID_ACTION_STOP_RAID_FUNCTION StopRaidFunction; ++ MPI2_RAID_ACTION_HOT_SPARE HotSpare; ++ MPI2_RAID_ACTION_FW_UPDATE_MODE FwUpdateMode; ++} MPI2_RAID_ACTION_DATA, MPI2_POINTER PTR_MPI2_RAID_ACTION_DATA, ++ Mpi2RaidActionData_t, MPI2_POINTER pMpi2RaidActionData_t; ++ ++ ++/* RAID Action Request Message */ ++typedef struct _MPI2_RAID_ACTION_REQUEST ++{ ++ U8 Action; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 VolDevHandle; /* 0x04 */ ++ U8 PhysDiskNum; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved2; /* 0x0A */ ++ U32 Reserved3; /* 0x0C */ ++ MPI2_RAID_ACTION_DATA ActionDataWord; /* 0x10 */ ++ MPI2_SGE_SIMPLE_UNION ActionDataSGE; /* 0x14 */ ++} MPI2_RAID_ACTION_REQUEST, MPI2_POINTER PTR_MPI2_RAID_ACTION_REQUEST, ++ Mpi2RaidActionRequest_t, MPI2_POINTER pMpi2RaidActionRequest_t; ++ ++/* RAID Action request Action values */ ++ ++#define MPI2_RAID_ACTION_INDICATOR_STRUCT (0x01) ++#define MPI2_RAID_ACTION_CREATE_VOLUME (0x02) ++#define MPI2_RAID_ACTION_DELETE_VOLUME (0x03) ++#define MPI2_RAID_ACTION_DISABLE_ALL_VOLUMES (0x04) ++#define MPI2_RAID_ACTION_ENABLE_ALL_VOLUMES (0x05) ++#define MPI2_RAID_ACTION_PHYSDISK_OFFLINE (0x0A) ++#define MPI2_RAID_ACTION_PHYSDISK_ONLINE (0x0B) ++#define MPI2_RAID_ACTION_FAIL_PHYSDISK (0x0F) ++#define MPI2_RAID_ACTION_ACTIVATE_VOLUME (0x11) ++#define MPI2_RAID_ACTION_DEVICE_FW_UPDATE_MODE (0x15) ++#define MPI2_RAID_ACTION_CHANGE_VOL_WRITE_CACHE (0x17) ++#define MPI2_RAID_ACTION_SET_VOLUME_NAME (0x18) ++#define MPI2_RAID_ACTION_SET_RAID_FUNCTION_RATE (0x19) ++#define MPI2_RAID_ACTION_ENABLE_FAILED_VOLUME (0x1C) ++#define MPI2_RAID_ACTION_CREATE_HOT_SPARE (0x1D) ++#define MPI2_RAID_ACTION_DELETE_HOT_SPARE (0x1E) ++#define MPI2_RAID_ACTION_SYSTEM_SHUTDOWN_INITIATED (0x20) ++#define MPI2_RAID_ACTION_START_RAID_FUNCTION (0x21) ++#define MPI2_RAID_ACTION_STOP_RAID_FUNCTION (0x22) ++ ++ ++/* RAID Volume Creation Structure */ ++ ++/* ++ * The following define can be customized for the targeted product. ++ */ ++#ifndef MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS ++#define MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS (1) ++#endif ++ ++typedef struct _MPI2_RAID_VOLUME_PHYSDISK ++{ ++ U8 RAIDSetNum; /* 0x00 */ ++ U8 PhysDiskMap; /* 0x01 */ ++ U16 PhysDiskDevHandle; /* 0x02 */ ++} MPI2_RAID_VOLUME_PHYSDISK, MPI2_POINTER PTR_MPI2_RAID_VOLUME_PHYSDISK, ++ Mpi2RaidVolumePhysDisk_t, MPI2_POINTER pMpi2RaidVolumePhysDisk_t; ++ ++/* defines for the PhysDiskMap field */ ++#define MPI2_RAIDACTION_PHYSDISK_PRIMARY (0x01) ++#define MPI2_RAIDACTION_PHYSDISK_SECONDARY (0x02) ++ ++typedef struct _MPI2_RAID_VOLUME_CREATION_STRUCT ++{ ++ U8 NumPhysDisks; /* 0x00 */ ++ U8 VolumeType; /* 0x01 */ ++ U16 Reserved1; /* 0x02 */ ++ U32 VolumeCreationFlags; /* 0x04 */ ++ U32 VolumeSettings; /* 0x08 */ ++ U8 Reserved2; /* 0x0C */ ++ U8 ResyncRate; /* 0x0D */ ++ U16 DataScrubDuration; /* 0x0E */ ++ U64 VolumeMaxLBA; /* 0x10 */ ++ U32 StripeSize; /* 0x18 */ ++ U8 Name[16]; /* 0x1C */ ++ MPI2_RAID_VOLUME_PHYSDISK PhysDisk[MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS];/* 0x2C */ ++} MPI2_RAID_VOLUME_CREATION_STRUCT, ++ MPI2_POINTER PTR_MPI2_RAID_VOLUME_CREATION_STRUCT, ++ Mpi2RaidVolumeCreationStruct_t, MPI2_POINTER pMpi2RaidVolumeCreationStruct_t; ++ ++/* use MPI2_RAID_VOL_TYPE_ defines from mpi2_cnfg.h for VolumeType */ ++ ++/* defines for the VolumeCreationFlags field */ ++#define MPI2_RAID_VOL_CREATION_USE_DEFAULT_SETTINGS (0x80) ++#define MPI2_RAID_VOL_CREATION_BACKGROUND_INIT (0x04) ++#define MPI2_RAID_VOL_CREATION_LOW_LEVEL_INIT (0x02) ++#define MPI2_RAID_VOL_CREATION_MIGRATE_DATA (0x01) ++ ++ ++/* RAID Online Capacity Expansion Structure */ ++ ++typedef struct _MPI2_RAID_ONLINE_CAPACITY_EXPANSION ++{ ++ U32 Flags; /* 0x00 */ ++ U16 DevHandle0; /* 0x04 */ ++ U16 Reserved1; /* 0x06 */ ++ U16 DevHandle1; /* 0x08 */ ++ U16 Reserved2; /* 0x0A */ ++} MPI2_RAID_ONLINE_CAPACITY_EXPANSION, ++ MPI2_POINTER PTR_MPI2_RAID_ONLINE_CAPACITY_EXPANSION, ++ Mpi2RaidOnlineCapacityExpansion_t, ++ MPI2_POINTER pMpi2RaidOnlineCapacityExpansion_t; ++ ++ ++/* RAID Volume Indicator Structure */ ++ ++typedef struct _MPI2_RAID_VOL_INDICATOR ++{ ++ U64 TotalBlocks; /* 0x00 */ ++ U64 BlocksRemaining; /* 0x08 */ ++ U32 Flags; /* 0x10 */ ++} MPI2_RAID_VOL_INDICATOR, MPI2_POINTER PTR_MPI2_RAID_VOL_INDICATOR, ++ Mpi2RaidVolIndicator_t, MPI2_POINTER pMpi2RaidVolIndicator_t; ++ ++/* defines for RAID Volume Indicator Flags field */ ++#define MPI2_RAID_VOL_FLAGS_OP_MASK (0x0000000F) ++#define MPI2_RAID_VOL_FLAGS_OP_BACKGROUND_INIT (0x00000000) ++#define MPI2_RAID_VOL_FLAGS_OP_ONLINE_CAP_EXPANSION (0x00000001) ++#define MPI2_RAID_VOL_FLAGS_OP_CONSISTENCY_CHECK (0x00000002) ++#define MPI2_RAID_VOL_FLAGS_OP_RESYNC (0x00000003) ++ ++ ++/* RAID Action Reply ActionData union */ ++typedef union _MPI2_RAID_ACTION_REPLY_DATA ++{ ++ U32 Word[5]; ++ MPI2_RAID_VOL_INDICATOR RaidVolumeIndicator; ++ U16 VolDevHandle; ++ U8 VolumeState; ++ U8 PhysDiskNum; ++} MPI2_RAID_ACTION_REPLY_DATA, MPI2_POINTER PTR_MPI2_RAID_ACTION_REPLY_DATA, ++ Mpi2RaidActionReplyData_t, MPI2_POINTER pMpi2RaidActionReplyData_t; ++ ++/* use MPI2_RAIDVOL0_SETTING_ defines from mpi2_cnfg.h for MPI2_RAID_ACTION_CHANGE_VOL_WRITE_CACHE action */ ++ ++ ++/* RAID Action Reply Message */ ++typedef struct _MPI2_RAID_ACTION_REPLY ++{ ++ U8 Action; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 VolDevHandle; /* 0x04 */ ++ U8 PhysDiskNum; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved2; /* 0x0A */ ++ U16 Reserved3; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ MPI2_RAID_ACTION_REPLY_DATA ActionData; /* 0x14 */ ++} MPI2_RAID_ACTION_REPLY, MPI2_POINTER PTR_MPI2_RAID_ACTION_REPLY, ++ Mpi2RaidActionReply_t, MPI2_POINTER pMpi2RaidActionReply_t; ++ ++ ++#endif ++ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpi/mpi2_sas.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpi/mpi2_sas.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,282 @@ ++/* ++ * Copyright (c) 2000-2007 LSI Corporation. ++ * ++ * ++ * Name: mpi2_sas.h ++ * Title: MPI Serial Attached SCSI structures and definitions ++ * Creation Date: February 9, 2007 ++ * ++ * mpi2.h Version: 02.00.02 ++ * ++ * Version History ++ * --------------- ++ * ++ * Date Version Description ++ * -------- -------- ------------------------------------------------------ ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 06-26-07 02.00.01 Added Clear All Persistent Operation to SAS IO Unit ++ * Control Request. ++ * 10-02-08 02.00.02 Added Set IOC Parameter Operation to SAS IO Unit Control ++ * Request. ++ * -------------------------------------------------------------------------- ++ */ ++ ++#ifndef MPI2_SAS_H ++#define MPI2_SAS_H ++ ++/* ++ * Values for SASStatus. ++ */ ++#define MPI2_SASSTATUS_SUCCESS (0x00) ++#define MPI2_SASSTATUS_UNKNOWN_ERROR (0x01) ++#define MPI2_SASSTATUS_INVALID_FRAME (0x02) ++#define MPI2_SASSTATUS_UTC_BAD_DEST (0x03) ++#define MPI2_SASSTATUS_UTC_BREAK_RECEIVED (0x04) ++#define MPI2_SASSTATUS_UTC_CONNECT_RATE_NOT_SUPPORTED (0x05) ++#define MPI2_SASSTATUS_UTC_PORT_LAYER_REQUEST (0x06) ++#define MPI2_SASSTATUS_UTC_PROTOCOL_NOT_SUPPORTED (0x07) ++#define MPI2_SASSTATUS_UTC_STP_RESOURCES_BUSY (0x08) ++#define MPI2_SASSTATUS_UTC_WRONG_DESTINATION (0x09) ++#define MPI2_SASSTATUS_SHORT_INFORMATION_UNIT (0x0A) ++#define MPI2_SASSTATUS_LONG_INFORMATION_UNIT (0x0B) ++#define MPI2_SASSTATUS_XFER_RDY_INCORRECT_WRITE_DATA (0x0C) ++#define MPI2_SASSTATUS_XFER_RDY_REQUEST_OFFSET_ERROR (0x0D) ++#define MPI2_SASSTATUS_XFER_RDY_NOT_EXPECTED (0x0E) ++#define MPI2_SASSTATUS_DATA_INCORRECT_DATA_LENGTH (0x0F) ++#define MPI2_SASSTATUS_DATA_TOO_MUCH_READ_DATA (0x10) ++#define MPI2_SASSTATUS_DATA_OFFSET_ERROR (0x11) ++#define MPI2_SASSTATUS_SDSF_NAK_RECEIVED (0x12) ++#define MPI2_SASSTATUS_SDSF_CONNECTION_FAILED (0x13) ++#define MPI2_SASSTATUS_INITIATOR_RESPONSE_TIMEOUT (0x14) ++ ++ ++/* ++ * Values for the SAS DeviceInfo field used in SAS Device Status Change Event ++ * data and SAS Configuration pages. ++ */ ++#define MPI2_SAS_DEVICE_INFO_SEP (0x00004000) ++#define MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE (0x00002000) ++#define MPI2_SAS_DEVICE_INFO_LSI_DEVICE (0x00001000) ++#define MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH (0x00000800) ++#define MPI2_SAS_DEVICE_INFO_SSP_TARGET (0x00000400) ++#define MPI2_SAS_DEVICE_INFO_STP_TARGET (0x00000200) ++#define MPI2_SAS_DEVICE_INFO_SMP_TARGET (0x00000100) ++#define MPI2_SAS_DEVICE_INFO_SATA_DEVICE (0x00000080) ++#define MPI2_SAS_DEVICE_INFO_SSP_INITIATOR (0x00000040) ++#define MPI2_SAS_DEVICE_INFO_STP_INITIATOR (0x00000020) ++#define MPI2_SAS_DEVICE_INFO_SMP_INITIATOR (0x00000010) ++#define MPI2_SAS_DEVICE_INFO_SATA_HOST (0x00000008) ++ ++#define MPI2_SAS_DEVICE_INFO_MASK_DEVICE_TYPE (0x00000007) ++#define MPI2_SAS_DEVICE_INFO_NO_DEVICE (0x00000000) ++#define MPI2_SAS_DEVICE_INFO_END_DEVICE (0x00000001) ++#define MPI2_SAS_DEVICE_INFO_EDGE_EXPANDER (0x00000002) ++#define MPI2_SAS_DEVICE_INFO_FANOUT_EXPANDER (0x00000003) ++ ++ ++/***************************************************************************** ++* ++* SAS Messages ++* ++*****************************************************************************/ ++ ++/**************************************************************************** ++* SMP Passthrough messages ++****************************************************************************/ ++ ++/* SMP Passthrough Request Message */ ++typedef struct _MPI2_SMP_PASSTHROUGH_REQUEST ++{ ++ U8 PassthroughFlags; /* 0x00 */ ++ U8 PhysicalPort; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 RequestDataLength; /* 0x04 */ ++ U8 SGLFlags; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved1; /* 0x0A */ ++ U32 Reserved2; /* 0x0C */ ++ U64 SASAddress; /* 0x10 */ ++ U32 Reserved3; /* 0x18 */ ++ U32 Reserved4; /* 0x1C */ ++ MPI2_SIMPLE_SGE_UNION SGL; /* 0x20 */ ++} MPI2_SMP_PASSTHROUGH_REQUEST, MPI2_POINTER PTR_MPI2_SMP_PASSTHROUGH_REQUEST, ++ Mpi2SmpPassthroughRequest_t, MPI2_POINTER pMpi2SmpPassthroughRequest_t; ++ ++/* values for PassthroughFlags field */ ++#define MPI2_SMP_PT_REQ_PT_FLAGS_IMMEDIATE (0x80) ++ ++/* values for SGLFlags field are in the SGL section of mpi2.h */ ++ ++ ++/* SMP Passthrough Reply Message */ ++typedef struct _MPI2_SMP_PASSTHROUGH_REPLY ++{ ++ U8 PassthroughFlags; /* 0x00 */ ++ U8 PhysicalPort; /* 0x01 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 ResponseDataLength; /* 0x04 */ ++ U8 SGLFlags; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved1; /* 0x0A */ ++ U8 Reserved2; /* 0x0C */ ++ U8 SASStatus; /* 0x0D */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U32 Reserved3; /* 0x14 */ ++ U8 ResponseData[4]; /* 0x18 */ ++} MPI2_SMP_PASSTHROUGH_REPLY, MPI2_POINTER PTR_MPI2_SMP_PASSTHROUGH_REPLY, ++ Mpi2SmpPassthroughReply_t, MPI2_POINTER pMpi2SmpPassthroughReply_t; ++ ++/* values for PassthroughFlags field */ ++#define MPI2_SMP_PT_REPLY_PT_FLAGS_IMMEDIATE (0x80) ++ ++/* values for SASStatus field are at the top of this file */ ++ ++ ++/**************************************************************************** ++* SATA Passthrough messages ++****************************************************************************/ ++ ++/* SATA Passthrough Request Message */ ++typedef struct _MPI2_SATA_PASSTHROUGH_REQUEST ++{ ++ U16 DevHandle; /* 0x00 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 PassthroughFlags; /* 0x04 */ ++ U8 SGLFlags; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved1; /* 0x0A */ ++ U32 Reserved2; /* 0x0C */ ++ U32 Reserved3; /* 0x10 */ ++ U32 Reserved4; /* 0x14 */ ++ U32 DataLength; /* 0x18 */ ++ U8 CommandFIS[20]; /* 0x1C */ ++ MPI2_SIMPLE_SGE_UNION SGL; /* 0x20 */ ++} MPI2_SATA_PASSTHROUGH_REQUEST, MPI2_POINTER PTR_MPI2_SATA_PASSTHROUGH_REQUEST, ++ Mpi2SataPassthroughRequest_t, MPI2_POINTER pMpi2SataPassthroughRequest_t; ++ ++/* values for PassthroughFlags field */ ++#define MPI2_SATA_PT_REQ_PT_FLAGS_EXECUTE_DIAG (0x0100) ++#define MPI2_SATA_PT_REQ_PT_FLAGS_DMA (0x0020) ++#define MPI2_SATA_PT_REQ_PT_FLAGS_PIO (0x0010) ++#define MPI2_SATA_PT_REQ_PT_FLAGS_UNSPECIFIED_VU (0x0004) ++#define MPI2_SATA_PT_REQ_PT_FLAGS_WRITE (0x0002) ++#define MPI2_SATA_PT_REQ_PT_FLAGS_READ (0x0001) ++ ++/* values for SGLFlags field are in the SGL section of mpi2.h */ ++ ++ ++/* SATA Passthrough Reply Message */ ++typedef struct _MPI2_SATA_PASSTHROUGH_REPLY ++{ ++ U16 DevHandle; /* 0x00 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 PassthroughFlags; /* 0x04 */ ++ U8 SGLFlags; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved1; /* 0x0A */ ++ U8 Reserved2; /* 0x0C */ ++ U8 SASStatus; /* 0x0D */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U8 StatusFIS[20]; /* 0x14 */ ++ U32 StatusControlRegisters; /* 0x28 */ ++ U32 TransferCount; /* 0x2C */ ++} MPI2_SATA_PASSTHROUGH_REPLY, MPI2_POINTER PTR_MPI2_SATA_PASSTHROUGH_REPLY, ++ Mpi2SataPassthroughReply_t, MPI2_POINTER pMpi2SataPassthroughReply_t; ++ ++/* values for SASStatus field are at the top of this file */ ++ ++ ++/**************************************************************************** ++* SAS IO Unit Control messages ++****************************************************************************/ ++ ++/* SAS IO Unit Control Request Message */ ++typedef struct _MPI2_SAS_IOUNIT_CONTROL_REQUEST ++{ ++ U8 Operation; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 DevHandle; /* 0x04 */ ++ U8 IOCParameter; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++ U16 Reserved4; /* 0x0C */ ++ U8 PhyNum; /* 0x0E */ ++ U8 PrimFlags; /* 0x0F */ ++ U32 Primitive; /* 0x10 */ ++ U8 LookupMethod; /* 0x14 */ ++ U8 Reserved5; /* 0x15 */ ++ U16 SlotNumber; /* 0x16 */ ++ U64 LookupAddress; /* 0x18 */ ++ U32 IOCParameterValue; /* 0x20 */ ++ U32 Reserved7; /* 0x24 */ ++ U32 Reserved8; /* 0x28 */ ++} MPI2_SAS_IOUNIT_CONTROL_REQUEST, ++ MPI2_POINTER PTR_MPI2_SAS_IOUNIT_CONTROL_REQUEST, ++ Mpi2SasIoUnitControlRequest_t, MPI2_POINTER pMpi2SasIoUnitControlRequest_t; ++ ++/* values for the Operation field */ ++#define MPI2_SAS_OP_CLEAR_ALL_PERSISTENT (0x02) ++#define MPI2_SAS_OP_PHY_LINK_RESET (0x06) ++#define MPI2_SAS_OP_PHY_HARD_RESET (0x07) ++#define MPI2_SAS_OP_PHY_CLEAR_ERROR_LOG (0x08) ++#define MPI2_SAS_OP_SEND_PRIMITIVE (0x0A) ++#define MPI2_SAS_OP_FORCE_FULL_DISCOVERY (0x0B) ++#define MPI2_SAS_OP_TRANSMIT_PORT_SELECT_SIGNAL (0x0C) ++#define MPI2_SAS_OP_REMOVE_DEVICE (0x0D) ++#define MPI2_SAS_OP_LOOKUP_MAPPING (0x0E) ++#define MPI2_SAS_OP_SET_IOC_PARAMETER (0x0F) ++#define MPI2_SAS_OP_PRODUCT_SPECIFIC_MIN (0x80) ++ ++/* values for the PrimFlags field */ ++#define MPI2_SAS_PRIMFLAGS_SINGLE (0x08) ++#define MPI2_SAS_PRIMFLAGS_TRIPLE (0x02) ++#define MPI2_SAS_PRIMFLAGS_REDUNDANT (0x01) ++ ++/* values for the LookupMethod field */ ++#define MPI2_SAS_LOOKUP_METHOD_SAS_ADDRESS (0x01) ++#define MPI2_SAS_LOOKUP_METHOD_SAS_ENCLOSURE_SLOT (0x02) ++#define MPI2_SAS_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) ++ ++ ++/* SAS IO Unit Control Reply Message */ ++typedef struct _MPI2_SAS_IOUNIT_CONTROL_REPLY ++{ ++ U8 Operation; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 DevHandle; /* 0x04 */ ++ U8 IOCParameter; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++ U16 Reserved4; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++} MPI2_SAS_IOUNIT_CONTROL_REPLY, ++ MPI2_POINTER PTR_MPI2_SAS_IOUNIT_CONTROL_REPLY, ++ Mpi2SasIoUnitControlReply_t, MPI2_POINTER pMpi2SasIoUnitControlReply_t; ++ ++ ++#endif ++ ++ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpi/mpi2_targ.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpi/mpi2_targ.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,440 @@ ++/* ++ * Copyright (c) 2000-2008 LSI Corporation. ++ * ++ * ++ * Name: mpi2_targ.h ++ * Title: MPI Target mode messages and structures ++ * Creation Date: September 8, 2006 ++ * ++ * mpi2_targ.h Version: 02.00.03 ++ * ++ * Version History ++ * --------------- ++ * ++ * Date Version Description ++ * -------- -------- ------------------------------------------------------ ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 08-31-07 02.00.01 Added Command Buffer Data Location Address Space bits to ++ * BufferPostFlags field of CommandBufferPostBase Request. ++ * 02-29-08 02.00.02 Modified various names to make them 32-character unique. ++ * 10-02-08 02.00.03 Removed NextCmdBufferOffset from ++ * MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST. ++ * Target Status Send Request only takes a single SGE for ++ * response data. ++ * -------------------------------------------------------------------------- ++ */ ++ ++#ifndef MPI2_TARG_H ++#define MPI2_TARG_H ++ ++ ++/****************************************************************************** ++* ++* SCSI Target Messages ++* ++*******************************************************************************/ ++ ++/**************************************************************************** ++* Target Command Buffer Post Base Request ++****************************************************************************/ ++ ++typedef struct _MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST ++{ ++ U8 BufferPostFlags; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 TotalCmdBuffers; /* 0x04 */ ++ U8 Reserved; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved2; /* 0x0A */ ++ U32 Reserved3; /* 0x0C */ ++ U16 CmdBufferLength; /* 0x10 */ ++ U16 Reserved4; /* 0x12 */ ++ U32 BaseAddressLow; /* 0x14 */ ++ U32 BaseAddressHigh; /* 0x18 */ ++} MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST, ++ MPI2_POINTER PTR_MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST, ++ Mpi2TargetCmdBufferPostBaseRequest_t, ++ MPI2_POINTER pMpi2TargetCmdBufferPostBaseRequest_t; ++ ++/* values for the BufferPostflags field */ ++#define MPI2_CMD_BUF_POST_BASE_ADDRESS_SPACE_MASK (0x0C) ++#define MPI2_CMD_BUF_POST_BASE_SYSTEM_ADDRESS_SPACE (0x00) ++#define MPI2_CMD_BUF_POST_BASE_IOCDDR_ADDRESS_SPACE (0x04) ++#define MPI2_CMD_BUF_POST_BASE_IOCPLB_ADDRESS_SPACE (0x08) ++#define MPI2_CMD_BUF_POST_BASE_IOCPLBNTA_ADDRESS_SPACE (0x0C) ++ ++#define MPI2_CMD_BUF_POST_BASE_FLAGS_AUTO_POST_ALL (0x01) ++ ++ ++/**************************************************************************** ++* Target Command Buffer Post List Request ++****************************************************************************/ ++ ++typedef struct _MPI2_TARGET_CMD_BUF_POST_LIST_REQUEST ++{ ++ U16 Reserved; /* 0x00 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 CmdBufferCount; /* 0x04 */ ++ U8 Reserved1; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved2; /* 0x0A */ ++ U32 Reserved3; /* 0x0C */ ++ U16 IoIndex[2]; /* 0x10 */ ++} MPI2_TARGET_CMD_BUF_POST_LIST_REQUEST, ++ MPI2_POINTER PTR_MPI2_TARGET_CMD_BUF_POST_LIST_REQUEST, ++ Mpi2TargetCmdBufferPostListRequest_t, ++ MPI2_POINTER pMpi2TargetCmdBufferPostListRequest_t; ++ ++/**************************************************************************** ++* Target Command Buffer Post Base List Reply ++****************************************************************************/ ++ ++typedef struct _MPI2_TARGET_BUF_POST_BASE_LIST_REPLY ++{ ++ U8 Flags; /* 0x00 */ ++ U8 Reserved; /* 0x01 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved1; /* 0x04 */ ++ U8 Reserved2; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++ U16 Reserved4; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U16 IoIndex; /* 0x14 */ ++ U16 Reserved5; /* 0x16 */ ++ U32 Reserved6; /* 0x18 */ ++} MPI2_TARGET_BUF_POST_BASE_LIST_REPLY, ++ MPI2_POINTER PTR_MPI2_TARGET_BUF_POST_BASE_LIST_REPLY, ++ Mpi2TargetCmdBufferPostBaseListReply_t, ++ MPI2_POINTER pMpi2TargetCmdBufferPostBaseListReply_t; ++ ++/* Flags defines */ ++#define MPI2_CMD_BUF_POST_REPLY_IOINDEX_VALID (0x01) ++ ++ ++/**************************************************************************** ++* Command Buffer Formats (with 16 byte CDB) ++****************************************************************************/ ++ ++typedef struct _MPI2_TARGET_SSP_CMD_BUFFER ++{ ++ U8 FrameType; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U16 InitiatorConnectionTag; /* 0x02 */ ++ U32 HashedSourceSASAddress; /* 0x04 */ ++ U16 Reserved2; /* 0x08 */ ++ U16 Flags; /* 0x0A */ ++ U32 Reserved3; /* 0x0C */ ++ U16 Tag; /* 0x10 */ ++ U16 TargetPortTransferTag; /* 0x12 */ ++ U32 DataOffset; /* 0x14 */ ++ /* COMMAND information unit starts here */ ++ U8 LogicalUnitNumber[8]; /* 0x18 */ ++ U8 Reserved4; /* 0x20 */ ++ U8 TaskAttribute; /* lower 3 bits */ /* 0x21 */ ++ U8 Reserved5; /* 0x22 */ ++ U8 AdditionalCDBLength; /* upper 5 bits */ /* 0x23 */ ++ U8 CDB[16]; /* 0x24 */ ++ /* Additional CDB bytes extend past the CDB field */ ++} MPI2_TARGET_SSP_CMD_BUFFER, MPI2_POINTER PTR_MPI2_TARGET_SSP_CMD_BUFFER, ++ Mpi2TargetSspCmdBuffer, MPI2_POINTER pMp2iTargetSspCmdBuffer; ++ ++typedef struct _MPI2_TARGET_SSP_TASK_BUFFER ++{ ++ U8 FrameType; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U16 InitiatorConnectionTag; /* 0x02 */ ++ U32 HashedSourceSASAddress; /* 0x04 */ ++ U16 Reserved2; /* 0x08 */ ++ U16 Flags; /* 0x0A */ ++ U32 Reserved3; /* 0x0C */ ++ U16 Tag; /* 0x10 */ ++ U16 TargetPortTransferTag; /* 0x12 */ ++ U32 DataOffset; /* 0x14 */ ++ /* TASK information unit starts here */ ++ U8 LogicalUnitNumber[8]; /* 0x18 */ ++ U16 Reserved4; /* 0x20 */ ++ U8 TaskManagementFunction; /* 0x22 */ ++ U8 Reserved5; /* 0x23 */ ++ U16 ManagedTaskTag; /* 0x24 */ ++ U16 Reserved6; /* 0x26 */ ++ U32 Reserved7; /* 0x28 */ ++ U32 Reserved8; /* 0x2C */ ++ U32 Reserved9; /* 0x30 */ ++} MPI2_TARGET_SSP_TASK_BUFFER, MPI2_POINTER PTR_MPI2_TARGET_SSP_TASK_BUFFER, ++ Mpi2TargetSspTaskBuffer, MPI2_POINTER pMpi2TargetSspTaskBuffer; ++ ++/* mask and shift for HashedSourceSASAddress field */ ++#define MPI2_TARGET_HASHED_SAS_ADDRESS_MASK (0xFFFFFF00) ++#define MPI2_TARGET_HASHED_SAS_ADDRESS_SHIFT (8) ++ ++ ++/**************************************************************************** ++* Target Assist Request ++****************************************************************************/ ++ ++typedef struct _MPI2_TARGET_ASSIST_REQUEST ++{ ++ U8 Reserved1; /* 0x00 */ ++ U8 TargetAssistFlags; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 QueueTag; /* 0x04 */ ++ U8 Reserved2; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++ U16 IoIndex; /* 0x0C */ ++ U16 InitiatorConnectionTag; /* 0x0E */ ++ U16 SGLFlags; /* 0x10 */ ++ U8 SequenceNumber; /* 0x12 */ ++ U8 Reserved4; /* 0x13 */ ++ U8 SGLOffset0; /* 0x14 */ ++ U8 SGLOffset1; /* 0x15 */ ++ U8 SGLOffset2; /* 0x16 */ ++ U8 SGLOffset3; /* 0x17 */ ++ U32 SkipCount; /* 0x18 */ ++ U32 DataLength; /* 0x1C */ ++ U32 BidirectionalDataLength; /* 0x20 */ ++ U16 IoFlags; /* 0x24 */ ++ U16 EEDPFlags; /* 0x26 */ ++ U32 EEDPBlockSize; /* 0x28 */ ++ U32 SecondaryReferenceTag; /* 0x2C */ ++ U16 SecondaryApplicationTag; /* 0x30 */ ++ U16 ApplicationTagTranslationMask; /* 0x32 */ ++ U32 PrimaryReferenceTag; /* 0x34 */ ++ U16 PrimaryApplicationTag; /* 0x38 */ ++ U16 PrimaryApplicationTagMask; /* 0x3A */ ++ U32 RelativeOffset; /* 0x3C */ ++ U32 Reserved5; /* 0x40 */ ++ U32 Reserved6; /* 0x44 */ ++ U32 Reserved7; /* 0x48 */ ++ U32 Reserved8; /* 0x4C */ ++ MPI2_SGE_IO_UNION SGL[1]; /* 0x50 */ ++} MPI2_TARGET_ASSIST_REQUEST, MPI2_POINTER PTR_MPI2_TARGET_ASSIST_REQUEST, ++ Mpi2TargetAssistRequest_t, MPI2_POINTER pMpi2TargetAssistRequest_t; ++ ++/* Target Assist TargetAssistFlags bits */ ++ ++#define MPI2_TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER (0x80) ++#define MPI2_TARGET_ASSIST_FLAGS_TLR (0x10) ++#define MPI2_TARGET_ASSIST_FLAGS_RETRANSMIT (0x04) ++#define MPI2_TARGET_ASSIST_FLAGS_AUTO_STATUS (0x02) ++#define MPI2_TARGET_ASSIST_FLAGS_DATA_DIRECTION (0x01) ++ ++/* Target Assist SGLFlags bits */ ++ ++/* base values for Data Location Address Space */ ++#define MPI2_TARGET_ASSIST_SGLFLAGS_ADDR_MASK (0x0C) ++#define MPI2_TARGET_ASSIST_SGLFLAGS_SYSTEM_ADDR (0x00) ++#define MPI2_TARGET_ASSIST_SGLFLAGS_IOCDDR_ADDR (0x04) ++#define MPI2_TARGET_ASSIST_SGLFLAGS_IOCPLB_ADDR (0x08) ++#define MPI2_TARGET_ASSIST_SGLFLAGS_PLBNTA_ADDR (0x0C) ++ ++/* base values for Type */ ++#define MPI2_TARGET_ASSIST_SGLFLAGS_TYPE_MASK (0x03) ++#define MPI2_TARGET_ASSIST_SGLFLAGS_MPI_TYPE (0x00) ++#define MPI2_TARGET_ASSIST_SGLFLAGS_32IEEE_TYPE (0x01) ++#define MPI2_TARGET_ASSIST_SGLFLAGS_64IEEE_TYPE (0x02) ++ ++/* shift values for each sub-field */ ++#define MPI2_TARGET_ASSIST_SGLFLAGS_SGL3_SHIFT (12) ++#define MPI2_TARGET_ASSIST_SGLFLAGS_SGL2_SHIFT (8) ++#define MPI2_TARGET_ASSIST_SGLFLAGS_SGL1_SHIFT (4) ++#define MPI2_TARGET_ASSIST_SGLFLAGS_SGL0_SHIFT (0) ++ ++/* Target Assist IoFlags bits */ ++ ++#define MPI2_TARGET_ASSIST_IOFLAGS_BIDIRECTIONAL (0x0800) ++#define MPI2_TARGET_ASSIST_IOFLAGS_MULTICAST (0x0400) ++#define MPI2_TARGET_ASSIST_IOFLAGS_RECEIVE_FIRST (0x0200) ++ ++/* Target Assist EEDPFlags bits */ ++ ++#define MPI2_TA_EEDPFLAGS_INC_PRI_REFTAG (0x8000) ++#define MPI2_TA_EEDPFLAGS_INC_SEC_REFTAG (0x4000) ++#define MPI2_TA_EEDPFLAGS_INC_PRI_APPTAG (0x2000) ++#define MPI2_TA_EEDPFLAGS_INC_SEC_APPTAG (0x1000) ++ ++#define MPI2_TA_EEDPFLAGS_CHECK_REFTAG (0x0400) ++#define MPI2_TA_EEDPFLAGS_CHECK_APPTAG (0x0200) ++#define MPI2_TA_EEDPFLAGS_CHECK_GUARD (0x0100) ++ ++#define MPI2_TA_EEDPFLAGS_PASSTHRU_REFTAG (0x0008) ++ ++#define MPI2_TA_EEDPFLAGS_MASK_OP (0x0007) ++#define MPI2_TA_EEDPFLAGS_NOOP_OP (0x0000) ++#define MPI2_TA_EEDPFLAGS_CHECK_OP (0x0001) ++#define MPI2_TA_EEDPFLAGS_STRIP_OP (0x0002) ++#define MPI2_TA_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) ++#define MPI2_TA_EEDPFLAGS_INSERT_OP (0x0004) ++#define MPI2_TA_EEDPFLAGS_REPLACE_OP (0x0006) ++#define MPI2_TA_EEDPFLAGS_CHECK_REGEN_OP (0x0007) ++ ++ ++/**************************************************************************** ++* Target Status Send Request ++****************************************************************************/ ++ ++typedef struct _MPI2_TARGET_STATUS_SEND_REQUEST ++{ ++ U8 Reserved1; /* 0x00 */ ++ U8 StatusFlags; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 QueueTag; /* 0x04 */ ++ U8 Reserved2; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++ U16 IoIndex; /* 0x0C */ ++ U16 InitiatorConnectionTag; /* 0x0E */ ++ U16 SGLFlags; /* 0x10 */ ++ U16 Reserved4; /* 0x12 */ ++ U8 SGLOffset0; /* 0x14 */ ++ U8 Reserved5; /* 0x15 */ ++ U16 Reserved6; /* 0x16 */ ++ U32 Reserved7; /* 0x18 */ ++ U32 Reserved8; /* 0x1C */ ++ MPI2_SIMPLE_SGE_UNION StatusDataSGE; /* 0x20 */ ++} MPI2_TARGET_STATUS_SEND_REQUEST, ++ MPI2_POINTER PTR_MPI2_TARGET_STATUS_SEND_REQUEST, ++ Mpi2TargetStatusSendRequest_t, MPI2_POINTER pMpi2TargetStatusSendRequest_t; ++ ++/* Target Status Send StatusFlags bits */ ++ ++#define MPI2_TSS_FLAGS_REPOST_CMD_BUFFER (0x80) ++#define MPI2_TSS_FLAGS_RETRANSMIT (0x04) ++#define MPI2_TSS_FLAGS_AUTO_GOOD_STATUS (0x01) ++ ++/* Target Status Send SGLFlags bits */ ++/* Data Location Address Space */ ++#define MPI2_TSS_SGLFLAGS_ADDR_MASK (0x0C) ++#define MPI2_TSS_SGLFLAGS_SYSTEM_ADDR (0x00) ++#define MPI2_TSS_SGLFLAGS_IOCDDR_ADDR (0x04) ++#define MPI2_TSS_SGLFLAGS_IOCPLB_ADDR (0x08) ++#define MPI2_TSS_SGLFLAGS_IOCPLBNTA_ADDR (0x0C) ++/* Type */ ++#define MPI2_TSS_SGLFLAGS_TYPE_MASK (0x03) ++#define MPI2_TSS_SGLFLAGS_MPI_TYPE (0x00) ++#define MPI2_TSS_SGLFLAGS_IEEE32_TYPE (0x01) ++#define MPI2_TSS_SGLFLAGS_IEEE64_TYPE (0x02) ++ ++ ++ ++/* ++ * NOTE: The SSP status IU is big-endian. When used on a little-endian system, ++ * this structure properly orders the bytes. ++ */ ++typedef struct _MPI2_TARGET_SSP_RSP_IU ++{ ++ U32 Reserved0[6]; /* reserved for SSP header */ /* 0x00 */ ++ /* start of RESPONSE information unit */ ++ U32 Reserved1; /* 0x18 */ ++ U32 Reserved2; /* 0x1C */ ++ U16 Reserved3; /* 0x20 */ ++ U8 DataPres; /* lower 2 bits */ /* 0x22 */ ++ U8 Status; /* 0x23 */ ++ U32 Reserved4; /* 0x24 */ ++ U32 SenseDataLength; /* 0x28 */ ++ U32 ResponseDataLength; /* 0x2C */ ++ U8 ResponseSenseData[4]; /* 0x30 */ ++} MPI2_TARGET_SSP_RSP_IU, MPI2_POINTER PTR_MPI2_TARGET_SSP_RSP_IU, ++ Mpi2TargetSspRspIu_t, MPI2_POINTER pMpi2TargetSspRspIu_t; ++ ++ ++/**************************************************************************** ++* Target Standard Reply - used with Target Assist or Target Status Send ++****************************************************************************/ ++ ++typedef struct _MPI2_TARGET_STANDARD_REPLY ++{ ++ U16 Reserved; /* 0x00 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved1; /* 0x04 */ ++ U8 Reserved2; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++ U16 Reserved4; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U16 IoIndex; /* 0x14 */ ++ U16 Reserved5; /* 0x16 */ ++ U32 TransferCount; /* 0x18 */ ++ U32 BidirectionalTransferCount; /* 0x1C */ ++} MPI2_TARGET_STANDARD_REPLY, MPI2_POINTER PTR_MPI2_TARGET_STANDARD_REPLY, ++ Mpi2TargetErrorReply_t, MPI2_POINTER pMpi2TargetErrorReply_t; ++ ++ ++/**************************************************************************** ++* Target Mode Abort Request ++****************************************************************************/ ++ ++typedef struct _MPI2_TARGET_MODE_ABORT_REQUEST ++{ ++ U8 AbortType; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U16 IoIndexToAbort; /* 0x0C */ ++ U16 Reserved6; /* 0x0E */ ++ U32 MidToAbort; /* 0x10 */ ++} MPI2_TARGET_MODE_ABORT, MPI2_POINTER PTR_MPI2_TARGET_MODE_ABORT, ++ Mpi2TargetModeAbort_t, MPI2_POINTER pMpi2TargetModeAbort_t; ++ ++/* Target Mode Abort AbortType values */ ++ ++#define MPI2_TARGET_MODE_ABORT_ALL_CMD_BUFFERS (0x00) ++#define MPI2_TARGET_MODE_ABORT_ALL_IO (0x01) ++#define MPI2_TARGET_MODE_ABORT_EXACT_IO (0x02) ++#define MPI2_TARGET_MODE_ABORT_EXACT_IO_REQUEST (0x03) ++#define MPI2_TARGET_MODE_ABORT_IO_REQUEST_AND_IO (0x04) ++ ++ ++/**************************************************************************** ++* Target Mode Abort Reply ++****************************************************************************/ ++ ++typedef struct _MPI2_TARGET_MODE_ABORT_REPLY ++{ ++ U16 Reserved; /* 0x00 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved1; /* 0x04 */ ++ U8 Reserved2; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved3; /* 0x0A */ ++ U16 Reserved4; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U32 AbortCount; /* 0x14 */ ++} MPI2_TARGET_MODE_ABORT_REPLY, MPI2_POINTER PTR_MPI2_TARGET_MODE_ABORT_REPLY, ++ Mpi2TargetModeAbortReply_t, MPI2_POINTER pMpi2TargetModeAbortReply_t; ++ ++ ++#endif ++ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpi/mpi2_tool.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpi/mpi2_tool.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,249 @@ ++/* ++ * Copyright (c) 2000-2008 LSI Corporation. ++ * ++ * ++ * Name: mpi2_tool.h ++ * Title: MPI diagnostic tool structures and definitions ++ * Creation Date: March 26, 2007 ++ * ++ * mpi2_tool.h Version: 02.00.02 ++ * ++ * Version History ++ * --------------- ++ * ++ * Date Version Description ++ * -------- -------- ------------------------------------------------------ ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * 12-18-07 02.00.01 Added Diagnostic Buffer Post and Diagnostic Release ++ * structures and defines. ++ * 02-29-08 02.00.02 Modified various names to make them 32-character unique. ++ * -------------------------------------------------------------------------- ++ */ ++ ++#ifndef MPI2_TOOL_H ++#define MPI2_TOOL_H ++ ++/***************************************************************************** ++* ++* Toolbox Messages ++* ++*****************************************************************************/ ++ ++/* defines for the Tools */ ++#define MPI2_TOOLBOX_CLEAN_TOOL (0x00) ++#define MPI2_TOOLBOX_MEMORY_MOVE_TOOL (0x01) ++#define MPI2_TOOLBOX_BEACON_TOOL (0x05) ++ ++/**************************************************************************** ++* Toolbox reply ++****************************************************************************/ ++ ++typedef struct _MPI2_TOOLBOX_REPLY ++{ ++ U8 Tool; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U16 Reserved5; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++} MPI2_TOOLBOX_REPLY, MPI2_POINTER PTR_MPI2_TOOLBOX_REPLY, ++ Mpi2ToolboxReply_t, MPI2_POINTER pMpi2ToolboxReply_t; ++ ++ ++/**************************************************************************** ++* Toolbox Clean Tool request ++****************************************************************************/ ++ ++typedef struct _MPI2_TOOLBOX_CLEAN_REQUEST ++{ ++ U8 Tool; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U32 Flags; /* 0x0C */ ++ } MPI2_TOOLBOX_CLEAN_REQUEST, MPI2_POINTER PTR_MPI2_TOOLBOX_CLEAN_REQUEST, ++ Mpi2ToolboxCleanRequest_t, MPI2_POINTER pMpi2ToolboxCleanRequest_t; ++ ++/* values for the Flags field */ ++#define MPI2_TOOLBOX_CLEAN_BOOT_SERVICES (0x80000000) ++#define MPI2_TOOLBOX_CLEAN_PERSIST_MANUFACT_PAGES (0x40000000) ++#define MPI2_TOOLBOX_CLEAN_OTHER_PERSIST_PAGES (0x20000000) ++#define MPI2_TOOLBOX_CLEAN_FW_CURRENT (0x10000000) ++#define MPI2_TOOLBOX_CLEAN_FW_BACKUP (0x08000000) ++#define MPI2_TOOLBOX_CLEAN_MEGARAID (0x02000000) ++#define MPI2_TOOLBOX_CLEAN_INITIALIZATION (0x01000000) ++#define MPI2_TOOLBOX_CLEAN_FLASH (0x00000004) ++#define MPI2_TOOLBOX_CLEAN_SEEPROM (0x00000002) ++#define MPI2_TOOLBOX_CLEAN_NVSRAM (0x00000001) ++ ++ ++/**************************************************************************** ++* Toolbox Memory Move request ++****************************************************************************/ ++ ++typedef struct _MPI2_TOOLBOX_MEM_MOVE_REQUEST ++{ ++ U8 Tool; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ MPI2_SGE_SIMPLE_UNION SGL; /* 0x0C */ ++} MPI2_TOOLBOX_MEM_MOVE_REQUEST, MPI2_POINTER PTR_MPI2_TOOLBOX_MEM_MOVE_REQUEST, ++ Mpi2ToolboxMemMoveRequest_t, MPI2_POINTER pMpi2ToolboxMemMoveRequest_t; ++ ++ ++/**************************************************************************** ++* Toolbox Beacon Tool request ++****************************************************************************/ ++ ++typedef struct _MPI2_TOOLBOX_BEACON_REQUEST ++{ ++ U8 Tool; /* 0x00 */ ++ U8 Reserved1; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U8 Reserved5; /* 0x0C */ ++ U8 PhysicalPort; /* 0x0D */ ++ U8 Reserved6; /* 0x0E */ ++ U8 Flags; /* 0x0F */ ++} MPI2_TOOLBOX_BEACON_REQUEST, MPI2_POINTER PTR_MPI2_TOOLBOX_BEACON_REQUEST, ++ Mpi2ToolboxBeaconRequest_t, MPI2_POINTER pMpi2ToolboxBeaconRequest_t; ++ ++/* values for the Flags field */ ++#define MPI2_TOOLBOX_FLAGS_BEACONMODE_OFF (0x00) ++#define MPI2_TOOLBOX_FLAGS_BEACONMODE_ON (0x01) ++ ++ ++/***************************************************************************** ++* ++* Diagnostic Buffer Messages ++* ++*****************************************************************************/ ++ ++ ++/**************************************************************************** ++* Diagnostic Buffer Post request ++****************************************************************************/ ++ ++typedef struct _MPI2_DIAG_BUFFER_POST_REQUEST ++{ ++ U8 Reserved1; /* 0x00 */ ++ U8 BufferType; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U64 BufferAddress; /* 0x0C */ ++ U32 BufferLength; /* 0x14 */ ++ U32 Reserved5; /* 0x18 */ ++ U32 Reserved6; /* 0x1C */ ++ U32 Flags; /* 0x20 */ ++ U32 ProductSpecific[23]; /* 0x24 */ ++} MPI2_DIAG_BUFFER_POST_REQUEST, MPI2_POINTER PTR_MPI2_DIAG_BUFFER_POST_REQUEST, ++ Mpi2DiagBufferPostRequest_t, MPI2_POINTER pMpi2DiagBufferPostRequest_t; ++ ++/* values for the BufferType field */ ++#define MPI2_DIAG_BUF_TYPE_TRACE (0x00) ++#define MPI2_DIAG_BUF_TYPE_SNAPSHOT (0x01) ++/* count of the number of buffer types */ ++#define MPI2_DIAG_BUF_TYPE_COUNT (0x02) ++ ++ ++/**************************************************************************** ++* Diagnostic Buffer Post reply ++****************************************************************************/ ++ ++typedef struct _MPI2_DIAG_BUFFER_POST_REPLY ++{ ++ U8 Reserved1; /* 0x00 */ ++ U8 BufferType; /* 0x01 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U16 Reserved5; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++ U32 TransferLength; /* 0x14 */ ++} MPI2_DIAG_BUFFER_POST_REPLY, MPI2_POINTER PTR_MPI2_DIAG_BUFFER_POST_REPLY, ++ Mpi2DiagBufferPostReply_t, MPI2_POINTER pMpi2DiagBufferPostReply_t; ++ ++ ++/**************************************************************************** ++* Diagnostic Release request ++****************************************************************************/ ++ ++typedef struct _MPI2_DIAG_RELEASE_REQUEST ++{ ++ U8 Reserved1; /* 0x00 */ ++ U8 BufferType; /* 0x01 */ ++ U8 ChainOffset; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++} MPI2_DIAG_RELEASE_REQUEST, MPI2_POINTER PTR_MPI2_DIAG_RELEASE_REQUEST, ++ Mpi2DiagReleaseRequest_t, MPI2_POINTER pMpi2DiagReleaseRequest_t; ++ ++ ++/**************************************************************************** ++* Diagnostic Buffer Post reply ++****************************************************************************/ ++ ++typedef struct _MPI2_DIAG_RELEASE_REPLY ++{ ++ U8 Reserved1; /* 0x00 */ ++ U8 BufferType; /* 0x01 */ ++ U8 MsgLength; /* 0x02 */ ++ U8 Function; /* 0x03 */ ++ U16 Reserved2; /* 0x04 */ ++ U8 Reserved3; /* 0x06 */ ++ U8 MsgFlags; /* 0x07 */ ++ U8 VP_ID; /* 0x08 */ ++ U8 VF_ID; /* 0x09 */ ++ U16 Reserved4; /* 0x0A */ ++ U16 Reserved5; /* 0x0C */ ++ U16 IOCStatus; /* 0x0E */ ++ U32 IOCLogInfo; /* 0x10 */ ++} MPI2_DIAG_RELEASE_REPLY, MPI2_POINTER PTR_MPI2_DIAG_RELEASE_REPLY, ++ Mpi2DiagReleaseReply_t, MPI2_POINTER pMpi2DiagReleaseReply_t; ++ ++ ++#endif ++ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpi/mpi2_type.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpi/mpi2_type.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,61 @@ ++/* ++ * Copyright (c) 2000-2007 LSI Corporation. ++ * ++ * ++ * Name: mpi2_type.h ++ * Title: MPI basic type definitions ++ * Creation Date: August 16, 2006 ++ * ++ * mpi2_type.h Version: 02.00.00 ++ * ++ * Version History ++ * --------------- ++ * ++ * Date Version Description ++ * -------- -------- ------------------------------------------------------ ++ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. ++ * -------------------------------------------------------------------------- ++ */ ++ ++#ifndef MPI2_TYPE_H ++#define MPI2_TYPE_H ++ ++ ++/******************************************************************************* ++ * Define MPI2_POINTER if it hasn't already been defined. By default ++ * MPI2_POINTER is defined to be a near pointer. MPI2_POINTER can be defined as ++ * a far pointer by defining MPI2_POINTER as "far *" before this header file is ++ * included. ++ */ ++#ifndef MPI2_POINTER ++#define MPI2_POINTER * ++#endif ++ ++/* the basic types may have already been included by mpi_type.h */ ++#ifndef MPI_TYPE_H ++/***************************************************************************** ++* ++* Basic Types ++* ++*****************************************************************************/ ++ ++typedef u8 U8; ++typedef __le16 U16; ++typedef __le32 U32; ++typedef __le64 U64 __attribute__((aligned(4))); ++ ++/***************************************************************************** ++* ++* Pointer Types ++* ++*****************************************************************************/ ++ ++typedef U8 *PU8; ++typedef U16 *PU16; ++typedef U32 *PU32; ++typedef U64 *PU64; ++ ++#endif ++ ++#endif ++ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpt2sas_base.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpt2sas_base.c Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,3692 @@ ++/* ++ * This is the Fusion MPT base driver providing common API layer interface ++ * for access to MPT (Message Passing Technology) firmware. ++ * ++ * This code is based on drivers/scsi/mpt2sas/mpt2_base.c ++ * Copyright (C) 2007-2008 LSI Corporation ++ * (mailto:DL-MPTFusionLinux@lsi.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * NO WARRANTY ++ * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR ++ * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT ++ * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is ++ * solely responsible for determining the appropriateness of using and ++ * distributing the Program and assumes all risks associated with its ++ * exercise of rights under this Agreement, including but not limited to ++ * the risks and costs of program errors, damage to or loss of data, ++ * programs or equipment, and unavailability or interruption of operations. ++ ++ * DISCLAIMER OF LIABILITY ++ * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR ++ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED ++ * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ++ ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, ++ * USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mpt2sas_base.h" ++ ++static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS]; ++ ++#define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */ ++#define MPT2SAS_MAX_REQUEST_QUEUE 500 /* maximum controller queue depth */ ++ ++static int max_queue_depth = -1; ++module_param(max_queue_depth, int, 0); ++MODULE_PARM_DESC(max_queue_depth, " max controller queue depth "); ++ ++static int max_sgl_entries = -1; ++module_param(max_sgl_entries, int, 0); ++MODULE_PARM_DESC(max_sgl_entries, " max sg entries "); ++ ++static int msix_disable = -1; ++module_param(msix_disable, int, 0); ++MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)"); ++ ++/** ++ * _base_fault_reset_work - workq handling ioc fault conditions ++ * @work: input argument, used to derive ioc ++ * Context: sleep. ++ * ++ * Return nothing. ++ */ ++static void ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) ++_base_fault_reset_work(struct work_struct *work) ++{ ++ struct MPT2SAS_ADAPTER *ioc = ++ container_of(work, struct MPT2SAS_ADAPTER, fault_reset_work.work); ++#else ++_base_fault_reset_work(void *arg) ++{ ++ struct MPT2SAS_ADAPTER *ioc = (struct MPT2SAS_ADAPTER *)arg; ++#endif ++ unsigned long flags; ++ u32 doorbell; ++ int rc; ++ ++ spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); ++ if (ioc->shost_recovery) ++ goto rearm_timer; ++ spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); ++ ++ doorbell = mpt2sas_base_get_iocstate(ioc, 0); ++ if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { ++ rc = mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, ++ FORCE_BIG_HAMMER); ++ printk(MPT2SAS_WARN_FMT "%s: hard reset: %s\n", ioc->name, ++ __func__, (rc == 0) ? "success" : "failed"); ++ doorbell = mpt2sas_base_get_iocstate(ioc, 0); ++ if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) ++ mpt2sas_base_fault_info(ioc, doorbell & ++ MPI2_DOORBELL_DATA_MASK); ++ } ++ ++ spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); ++ rearm_timer: ++ if (ioc->fault_reset_work_q) ++ queue_delayed_work(ioc->fault_reset_work_q, ++ &ioc->fault_reset_work, ++ msecs_to_jiffies(FAULT_POLLING_INTERVAL)); ++ spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); ++} ++ ++/** ++ * mpt2sas_base_start_watchdog - start the fault_reset_work_q ++ * @ioc: pointer to scsi command object ++ * Context: sleep. ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_start_watchdog(struct MPT2SAS_ADAPTER *ioc) ++{ ++ unsigned long flags; ++ ++ if (ioc->fault_reset_work_q) ++ return; ++ ++ /* initialize fault polling */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) ++ INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work); ++#else ++ INIT_WORK(&ioc->fault_reset_work, _base_fault_reset_work, (void *)ioc); ++#endif ++ snprintf(ioc->fault_reset_work_q_name, ++ sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id); ++ ioc->fault_reset_work_q = ++ create_singlethread_workqueue(ioc->fault_reset_work_q_name); ++ if (!ioc->fault_reset_work_q) { ++ printk(MPT2SAS_ERR_FMT "%s: failed (line=%d)\n", ++ ioc->name, __func__, __LINE__); ++ return; ++ } ++ spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); ++ if (ioc->fault_reset_work_q) ++ queue_delayed_work(ioc->fault_reset_work_q, ++ &ioc->fault_reset_work, ++ msecs_to_jiffies(FAULT_POLLING_INTERVAL)); ++ spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); ++} ++ ++/** ++ * mpt2sas_base_stop_watchdog - stop the fault_reset_work_q ++ * @ioc: pointer to scsi command object ++ * Context: sleep. ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_stop_watchdog(struct MPT2SAS_ADAPTER *ioc) ++{ ++ unsigned long flags; ++ struct workqueue_struct *wq; ++ ++ spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); ++ wq = ioc->fault_reset_work_q; ++ ioc->fault_reset_work_q = NULL; ++ spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); ++ if (wq) { ++ if (!cancel_delayed_work(&ioc->fault_reset_work)) ++ flush_workqueue(wq); ++ destroy_workqueue(wq); ++ } ++} ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++/** ++ * _base_sas_ioc_info - verbose translation of the ioc status ++ * @ioc: pointer to scsi command object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @request_hdr: request mf ++ * ++ * Return nothing. ++ */ ++static void ++_base_sas_ioc_info(struct MPT2SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply, ++ MPI2RequestHeader_t *request_hdr) ++{ ++ u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ char *desc = NULL; ++ u16 frame_sz; ++ char *func_str = NULL; ++ ++ /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */ ++ if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || ++ request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH || ++ request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION) ++ return; ++ ++ switch (ioc_status) { ++ ++/**************************************************************************** ++* Common IOCStatus values for all replies ++****************************************************************************/ ++ ++ case MPI2_IOCSTATUS_INVALID_FUNCTION: ++ desc = "invalid function"; ++ break; ++ case MPI2_IOCSTATUS_BUSY: ++ desc = "busy"; ++ break; ++ case MPI2_IOCSTATUS_INVALID_SGL: ++ desc = "invalid sgl"; ++ break; ++ case MPI2_IOCSTATUS_INTERNAL_ERROR: ++ desc = "internal error"; ++ break; ++ case MPI2_IOCSTATUS_INVALID_VPID: ++ desc = "invalid vpid"; ++ break; ++ case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: ++ desc = "insufficient resources"; ++ break; ++ case MPI2_IOCSTATUS_INVALID_FIELD: ++ desc = "invalid field"; ++ break; ++ case MPI2_IOCSTATUS_INVALID_STATE: ++ desc = "invalid state"; ++ break; ++ case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: ++ desc = "op state not supported"; ++ break; ++ ++/**************************************************************************** ++* Config IOCStatus values ++****************************************************************************/ ++ ++ case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: ++ desc = "config invalid action"; ++ break; ++ case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: ++ desc = "config invalid type"; ++ break; ++ case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: ++ desc = "config invalid page"; ++ break; ++ case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: ++ desc = "config invalid data"; ++ break; ++ case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: ++ desc = "config no defaults"; ++ break; ++ case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: ++ desc = "config cant commit"; ++ break; ++ ++/**************************************************************************** ++* SCSI IO Reply ++****************************************************************************/ ++ ++ case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: ++ case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE: ++ case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: ++ case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: ++ case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: ++ case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: ++ case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: ++ case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: ++ case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: ++ case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED: ++ case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: ++ case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: ++ break; ++ ++/**************************************************************************** ++* For use by SCSI Initiator and SCSI Target end-to-end data protection ++****************************************************************************/ ++ ++#if defined(EEDP_SUPPORT) ++ case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: ++ desc = "eedp guard error"; ++ break; ++ case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: ++ desc = "eedp ref tag error"; ++ break; ++ case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: ++ desc = "eedp app tag error"; ++ break; ++#endif /* EEDP Support */ ++ ++/**************************************************************************** ++* SCSI Target values ++****************************************************************************/ ++ ++ case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX: ++ desc = "target invalid io index"; ++ break; ++ case MPI2_IOCSTATUS_TARGET_ABORTED: ++ desc = "target aborted"; ++ break; ++ case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: ++ desc = "target no conn retryable"; ++ break; ++ case MPI2_IOCSTATUS_TARGET_NO_CONNECTION: ++ desc = "target no connection"; ++ break; ++ case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: ++ desc = "target xfer count mismatch"; ++ break; ++ case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: ++ desc = "target data offset error"; ++ break; ++ case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: ++ desc = "target too much write data"; ++ break; ++ case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT: ++ desc = "target iu too short"; ++ break; ++ case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: ++ desc = "target ack nak timeout"; ++ break; ++ case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED: ++ desc = "target nak received"; ++ break; ++ ++/**************************************************************************** ++* Serial Attached SCSI values ++****************************************************************************/ ++ ++ case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: ++ desc = "smp request failed"; ++ break; ++ case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: ++ desc = "smp data overrun"; ++ break; ++ ++/**************************************************************************** ++* Diagnostic Buffer Post / Diagnostic Release values ++****************************************************************************/ ++ ++ case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED: ++ desc = "diagnostic released"; ++ break; ++ default: ++ break; ++ } ++ ++ if (!desc) ++ return; ++ ++ switch (request_hdr->Function) { ++ case MPI2_FUNCTION_CONFIG: ++ frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size; ++ func_str = "config_page"; ++ break; ++ case MPI2_FUNCTION_SCSI_TASK_MGMT: ++ frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t); ++ func_str = "task_mgmt"; ++ break; ++ case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL: ++ frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t); ++ func_str = "sas_iounit_ctl"; ++ break; ++ case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR: ++ frame_sz = sizeof(Mpi2SepRequest_t); ++ func_str = "enclosure"; ++ break; ++ case MPI2_FUNCTION_IOC_INIT: ++ frame_sz = sizeof(Mpi2IOCInitRequest_t); ++ func_str = "ioc_init"; ++ break; ++ case MPI2_FUNCTION_PORT_ENABLE: ++ frame_sz = sizeof(Mpi2PortEnableRequest_t); ++ func_str = "port_enable"; ++ break; ++ case MPI2_FUNCTION_SMP_PASSTHROUGH: ++ frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size; ++ func_str = "smp_passthru"; ++ break; ++ default: ++ frame_sz = 32; ++ func_str = "unknown"; ++ break; ++ } ++ ++ printk(MPT2SAS_WARN_FMT "ioc_status: %s(0x%04x), request(0x%p)," ++ " (%s)\n", ioc->name, desc, ioc_status, request_hdr, func_str); ++ ++ _debug_dump_mf(request_hdr, frame_sz/4); ++} ++ ++/** ++ * _base_display_event_data - verbose translation of firmware asyn events ++ * @ioc: pointer to scsi command object ++ * @mpi_reply: reply mf payload returned from firmware ++ * ++ * Return nothing. ++ */ ++static void ++_base_display_event_data(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventNotificationReply_t *mpi_reply) ++{ ++ char *desc = NULL; ++ u16 event; ++ ++ if (!(ioc->logging_level & MPT_DEBUG_EVENTS)) ++ return; ++ ++ event = le16_to_cpu(mpi_reply->Event); ++ ++ switch (event) { ++ case MPI2_EVENT_LOG_DATA: ++ desc = "Log Data"; ++ break; ++ case MPI2_EVENT_STATE_CHANGE: ++ desc = "Status Change"; ++ break; ++ case MPI2_EVENT_HARD_RESET_RECEIVED: ++ desc = "Hard Reset Received"; ++ break; ++ case MPI2_EVENT_EVENT_CHANGE: ++ desc = "Event Change"; ++ break; ++ case MPI2_EVENT_TASK_SET_FULL: ++ desc = "Task Set Full"; ++ break; ++ case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: ++ desc = "Device Status Change"; ++ break; ++ case MPI2_EVENT_IR_OPERATION_STATUS: ++ desc = "IR Operation Status"; ++ break; ++ case MPI2_EVENT_SAS_DISCOVERY: ++ desc = "Discovery"; ++ break; ++ case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: ++ desc = "SAS Broadcast Primitive"; ++ break; ++ case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: ++ desc = "SAS Init Device Status Change"; ++ break; ++ case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW: ++ desc = "SAS Init Table Overflow"; ++ break; ++ case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: ++ desc = "SAS Topology Change List"; ++ break; ++ case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: ++ desc = "SAS Enclosure Device Status Change"; ++ break; ++ case MPI2_EVENT_IR_VOLUME: ++ desc = "IR Volume"; ++ break; ++ case MPI2_EVENT_IR_PHYSICAL_DISK: ++ desc = "IR Physical Disk"; ++ break; ++ case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: ++ desc = "IR Configuration Change List"; ++ break; ++ case MPI2_EVENT_LOG_ENTRY_ADDED: ++ desc = "Log Entry Added"; ++ break; ++ } ++ ++ if (!desc) ++ return; ++ ++ printk(MPT2SAS_INFO_FMT "%s\n", ioc->name, desc); ++} ++#endif ++ ++/** ++ * _base_sas_log_info - verbose translation of firmware log info ++ * @ioc: pointer to scsi command object ++ * @log_info: log info ++ * ++ * Return nothing. ++ */ ++static void ++_base_sas_log_info(struct MPT2SAS_ADAPTER *ioc , u32 log_info) ++{ ++ union loginfo_type { ++ u32 loginfo; ++ struct { ++ u32 subcode:16; ++ u32 code:8; ++ u32 originator:4; ++ u32 bus_type:4; ++ } dw; ++ }; ++ union loginfo_type sas_loginfo; ++ char *originator_str = NULL; ++ ++ sas_loginfo.loginfo = log_info; ++ if (sas_loginfo.dw.bus_type != 3 /*SAS*/) ++ return; ++ ++ /* each nexus loss loginfo */ ++ if (log_info == 0x31170000) ++ return; ++ ++ /* eat the loginfos associated with task aborts */ ++ if (ioc->ignore_loginfos && (log_info == 30050000 || log_info == ++ 0x31140000 || log_info == 0x31130000)) ++ return; ++ ++ switch (sas_loginfo.dw.originator) { ++ case 0: ++ originator_str = "IOP"; ++ break; ++ case 1: ++ originator_str = "PL"; ++ break; ++ case 2: ++ originator_str = "IR"; ++ break; ++ } ++ ++ printk(MPT2SAS_WARN_FMT "log_info(0x%08x): originator(%s), " ++ "code(0x%02x), sub_code(0x%04x)\n", ioc->name, log_info, ++ originator_str, sas_loginfo.dw.code, ++ sas_loginfo.dw.subcode); ++} ++ ++/** ++ * mpt2sas_base_fault_info - verbose translation of firmware FAULT code ++ * @ioc: pointer to scsi command object ++ * @fault_code: fault code ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_fault_info(struct MPT2SAS_ADAPTER *ioc , u16 fault_code) ++{ ++ printk(MPT2SAS_ERR_FMT "fault_state(0x%04x)!\n", ++ ioc->name, fault_code); ++} ++ ++/** ++ * _base_display_reply_info - ++ * @ioc: pointer to scsi command object ++ * @smid: system request message index ++ * @VF_ID: virtual function id ++ * @reply: reply message frame(lower 32bit addr) ++ * ++ * Return nothing. ++ */ ++static void ++_base_display_reply_info(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, ++ u32 reply) ++{ ++ MPI2DefaultReply_t *mpi_reply; ++ u16 ioc_status; ++ ++ mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply); ++ ioc_status = le16_to_cpu(mpi_reply->IOCStatus); ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ if ((ioc_status & MPI2_IOCSTATUS_MASK) && ++ (ioc->logging_level & MPT_DEBUG_REPLY)) { ++ _base_sas_ioc_info(ioc , mpi_reply, ++ mpt2sas_base_get_msg_frame(ioc, smid)); ++ } ++#endif ++ if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) ++ _base_sas_log_info(ioc, le32_to_cpu(mpi_reply->IOCLogInfo)); ++} ++ ++/** ++ * mpt2sas_base_done - base internal command completion routine ++ * @ioc: pointer to scsi command object ++ * @smid: system request message index ++ * @VF_ID: virtual function id ++ * @reply: reply message frame(lower 32bit addr) ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, u32 reply) ++{ ++ MPI2DefaultReply_t *mpi_reply; ++ ++ mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply); ++ if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK) ++ return; ++ ++ if (ioc->base_cmds.status == MPT2_CMD_NOT_USED) ++ return; ++ ++ ioc->base_cmds.status |= MPT2_CMD_COMPLETE; ++ if (mpi_reply) { ++ ioc->base_cmds.status |= MPT2_CMD_REPLY_VALID; ++ memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); ++ } ++ ioc->base_cmds.status &= ~MPT2_CMD_PENDING; ++ complete(&ioc->base_cmds.done); ++} ++ ++/** ++ * _base_async_event - main callback handler for firmware asyn events ++ * @ioc: pointer to scsi command object ++ * @VF_ID: virtual function id ++ * @reply: reply message frame(lower 32bit addr) ++ * ++ * Return nothing. ++ */ ++static void ++_base_async_event(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, u32 reply) ++{ ++ Mpi2EventNotificationReply_t *mpi_reply; ++ Mpi2EventAckRequest_t *ack_request; ++ u16 smid; ++ ++ mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply); ++ if (!mpi_reply) ++ return; ++ if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION) ++ return; ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ _base_display_event_data(ioc, mpi_reply); ++#endif ++ if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED)) ++ goto out; ++ smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ goto out; ++ } ++ ++ ack_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t)); ++ ack_request->Function = MPI2_FUNCTION_EVENT_ACK; ++ ack_request->Event = mpi_reply->Event; ++ ack_request->EventContext = mpi_reply->EventContext; ++ ack_request->VF_ID = VF_ID; ++ mpt2sas_base_put_smid_default(ioc, smid, VF_ID); ++ ++ out: ++ ++ /* scsih callback handler */ ++ mpt2sas_scsih_event_callback(ioc, VF_ID, reply); ++ ++ /* ctl callback handler */ ++ mpt2sas_ctl_event_callback(ioc, VF_ID, reply); ++} ++ ++/** ++ * _base_mask_interrupts - disable interrupts ++ * @ioc: pointer to scsi command object ++ * ++ * Disabling ResetIRQ, Reply and Doorbell Interrupts ++ * ++ * Return nothing. ++ */ ++static void ++_base_mask_interrupts(struct MPT2SAS_ADAPTER *ioc) ++{ ++ u32 him_register; ++ ++ ioc->mask_interrupts = 1; ++ him_register = readl(&ioc->chip->HostInterruptMask); ++ him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK; ++ writel(him_register, &ioc->chip->HostInterruptMask); ++ readl(&ioc->chip->HostInterruptMask); ++} ++ ++/** ++ * _base_unmask_interrupts - enable interrupts ++ * @ioc: pointer to scsi command object ++ * ++ * Enabling only Reply Interrupts ++ * ++ * Return nothing. ++ */ ++static void ++_base_unmask_interrupts(struct MPT2SAS_ADAPTER *ioc) ++{ ++ u32 him_register; ++ ++ writel(0, &ioc->chip->HostInterruptStatus); ++ him_register = readl(&ioc->chip->HostInterruptMask); ++ him_register &= ~MPI2_HIM_RIM; ++ writel(him_register, &ioc->chip->HostInterruptMask); ++ ioc->mask_interrupts = 0; ++} ++ ++union reply_descriptor { ++ u64 word; ++ struct { ++ u32 low; ++ u32 high; ++ } u; ++}; ++ ++/** ++ * _base_interrupt - MPT adapter (IOC) specific interrupt handler. ++ * @irq: irq number (not used) ++ * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure ++ * @r: pt_regs pointer (not used) ++ * ++ * Return IRQ_HANDLE if processed, else IRQ_NONE. ++ */ ++static irqreturn_t ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++_base_interrupt(int irq, void *bus_id) ++#else ++_base_interrupt(int irq, void *bus_id, struct pt_regs *r) ++#endif ++{ ++ union reply_descriptor rd; ++ u32 completed_cmds; ++ u8 request_desript_type; ++ u16 smid; ++ u8 cb_idx; ++ u32 reply; ++ u8 VF_ID; ++ struct MPT2SAS_ADAPTER *ioc = bus_id; ++ Mpi2ReplyDescriptorsUnion_t *rpf; ++ ++ if (ioc->mask_interrupts) ++ return IRQ_NONE; ++ ++ rpf = &ioc->reply_post_free[ioc->reply_post_host_index]; ++ request_desript_type = rpf->Default.ReplyFlags ++ & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; ++ if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) ++ return IRQ_NONE; ++ ++ completed_cmds = 0; ++ do { ++ rd.word = rpf->Words; ++ if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX) ++ goto out; ++ reply = 0; ++ cb_idx = 0xFF; ++ smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1); ++ VF_ID = rpf->Default.VF_ID; ++ if (request_desript_type == ++ MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { ++ reply = le32_to_cpu( ++ rpf->AddressReply.ReplyFrameAddress); ++ } else if (request_desript_type == ++ MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER) { ++#if defined(TARGET_MODE) ++ mpt2sas_stmapp_target_command(ioc, ++ le16_to_cpu(rpf->TargetCommandBuffer.IoIndex), ++ le16_to_cpu( ++ rpf->TargetCommandBuffer.InitiatorDevHandle), ++ rpf->TargetCommandBuffer.VP_ID, ++ rpf->TargetCommandBuffer.VF_ID, ++ rpf->TargetCommandBuffer.Flags & ++ MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK); ++#endif ++ goto next; ++ } else if (request_desript_type == ++ MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS) { ++#if defined(TARGET_MODE) ++ mpt2sas_stm_target_assist_success_reply(ioc, ++ le16_to_cpu(rpf->TargetAssistSuccess.SMID), ++ rpf->TargetAssistSuccess.VF_ID, ++ le16_to_cpu(rpf->TargetAssistSuccess.IoIndex), ++ rpf->TargetAssistSuccess.SequenceNumber); ++ mpt2sas_base_free_smid(ioc, smid); ++#endif ++ goto next; ++ } ++ if (smid) ++ cb_idx = ioc->scsi_lookup[smid - 1].cb_idx; ++ if (smid && cb_idx != 0xFF) { ++ mpt_callbacks[cb_idx](ioc, smid, VF_ID, reply); ++ if (reply) ++ _base_display_reply_info(ioc, smid, VF_ID, ++ reply); ++ mpt2sas_base_free_smid(ioc, smid); ++ } ++ if (!smid) { ++#if defined(TARGET_MODE) ++ mpt2sas_stm_zero_smid_handler(ioc, VF_ID, reply); ++#endif ++ _base_async_event(ioc, VF_ID, reply); ++ } ++ ++ /* reply free queue handling */ ++ if (reply) { ++ ioc->reply_free_host_index = ++ (ioc->reply_free_host_index == ++ (ioc->reply_free_queue_depth - 1)) ? ++ 0 : ioc->reply_free_host_index + 1; ++ ioc->reply_free[ioc->reply_free_host_index] = ++ cpu_to_le32(reply); ++ wmb(); ++ writel(ioc->reply_free_host_index, ++ &ioc->chip->ReplyFreeHostIndex); ++ } ++ ++ next: ++ ++ rpf->Words = ULLONG_MAX; ++ ioc->reply_post_host_index = (ioc->reply_post_host_index == ++ (ioc->reply_post_queue_depth - 1)) ? 0 : ++ ioc->reply_post_host_index + 1; ++ request_desript_type = ++ ioc->reply_post_free[ioc->reply_post_host_index].Default. ++ ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; ++ completed_cmds++; ++ if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) ++ goto out; ++ if (!ioc->reply_post_host_index) ++ rpf = ioc->reply_post_free; ++ else ++ rpf++; ++ } while (1); ++ ++ out: ++ ++ if (!completed_cmds) ++ return IRQ_NONE; ++ ++ wmb(); ++ writel(ioc->reply_post_host_index, &ioc->chip->ReplyPostHostIndex); ++ return IRQ_HANDLED; ++} ++ ++/** ++ * mpt2sas_base_release_callback_handler - clear interupt callback handler ++ * @cb_idx: callback index ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_release_callback_handler(u8 cb_idx) ++{ ++ mpt_callbacks[cb_idx] = NULL; ++} ++ ++/** ++ * mpt2sas_base_register_callback_handler - obtain index for the ISR handler ++ * @cb_func: callback function ++ * ++ * Returns cb_func. ++ */ ++u8 ++mpt2sas_base_register_callback_handler(MPT_CALLBACK cb_func) ++{ ++ u8 cb_idx; ++ ++ for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--) ++ if (mpt_callbacks[cb_idx] == NULL) ++ break; ++ ++ mpt_callbacks[cb_idx] = cb_func; ++ return cb_idx; ++} ++ ++/** ++ * mpt2sas_base_initialize_callback_handler - initialize the ISR handler ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_initialize_callback_handler(void) ++{ ++ u8 cb_idx; ++ ++ for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++) ++ mpt2sas_base_release_callback_handler(cb_idx); ++} ++ ++/** ++ * mpt2sas_base_build_zero_len_sge - build zero length sg entry ++ * @ioc: per adapter object ++ * @paddr: virtual address for SGE ++ * ++ * Create a zero length scatter gather entry to insure the IOCs hardware has ++ * something to use if the target device goes brain dead and tries ++ * to send data even when none is asked for. ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_build_zero_len_sge(struct MPT2SAS_ADAPTER *ioc, void *paddr) ++{ ++ u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT | ++ MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST | ++ MPI2_SGE_FLAGS_SIMPLE_ELEMENT) << ++ MPI2_SGE_FLAGS_SHIFT); ++ ioc->base_add_sg_single(paddr, flags_length, -1); ++} ++ ++/** ++ * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr. ++ * @paddr: virtual address for SGE ++ * @flags_length: SGE flags and data transfer length ++ * @dma_addr: Physical address ++ * ++ * Return nothing. ++ */ ++static void ++_base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr) ++{ ++ Mpi2SGESimple32_t *sgel = paddr; ++ ++ flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING | ++ MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; ++ sgel->FlagsLength = cpu_to_le32(flags_length); ++ sgel->Address = cpu_to_le32(dma_addr); ++} ++ ++ ++/** ++ * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr. ++ * @paddr: virtual address for SGE ++ * @flags_length: SGE flags and data transfer length ++ * @dma_addr: Physical address ++ * ++ * Return nothing. ++ */ ++static void ++_base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr) ++{ ++ Mpi2SGESimple64_t *sgel = paddr; ++ ++ flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING | ++ MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; ++ sgel->FlagsLength = cpu_to_le32(flags_length); ++ sgel->Address = cpu_to_le64(dma_addr); ++} ++ ++#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10)) ++ ++/** ++ * _base_config_dma_addressing - set dma addressing ++ * @ioc: per adapter object ++ * @pdev: PCI device struct ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_base_config_dma_addressing(struct MPT2SAS_ADAPTER *ioc, struct pci_dev *pdev) ++{ ++ struct sysinfo s; ++ char *desc = NULL; ++ ++ if (sizeof(dma_addr_t) > 4) { ++ uint64_t required_mask; ++ ++ /* have to first set mask to 64 to find max mask required */ ++ if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) != 0) ++ goto try_32bit; ++ ++ required_mask = dma_get_required_mask(&pdev->dev); ++ ++ if (required_mask > DMA_32BIT_MASK && ++ !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) { ++ ioc->base_add_sg_single = &_base_add_sg_single_64; ++ ioc->sge_size = sizeof(Mpi2SGESimple64_t); ++ desc = "64"; ++ goto out; ++ } ++ } ++ ++ try_32bit: ++ ++ if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK) && ++ !pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { ++ ioc->base_add_sg_single = &_base_add_sg_single_32; ++ ioc->sge_size = sizeof(Mpi2SGESimple32_t); ++ desc = "32"; ++ } else ++ return -ENODEV; ++ ++ out: ++ si_meminfo(&s); ++ printk(MPT2SAS_INFO_FMT "%s BIT PCI BUS DMA ADDRESSING SUPPORTED, " ++ "total mem (%ld kB)\n", ioc->name, desc, convert_to_kb(s.totalram)); ++ ++ return 0; ++} ++ ++/** ++ * mpt2sas_base_save_msix_table - backup msix vector table ++ * @ioc: per adapter object ++ * ++ * This address an errata where diag reset clears out the table ++ */ ++void ++mpt2sas_base_save_msix_table(struct MPT2SAS_ADAPTER *ioc) ++{ ++ int i; ++ ++ if (!ioc->msix_enable || ioc->msix_table_backup == NULL) ++ return; ++ ++ for (i = 0; i < ioc->msix_vector_count; i++) ++ ioc->msix_table_backup[i] = ioc->msix_table[i]; ++} ++ ++/** ++ * mpt2sas_base_restore_msix_table - this restores the msix vector table ++ * @ioc: per adapter object ++ * ++ */ ++void ++mpt2sas_base_restore_msix_table(struct MPT2SAS_ADAPTER *ioc) ++{ ++ int i; ++ ++ if (!ioc->msix_enable || ioc->msix_table_backup == NULL) ++ return; ++ ++ for (i = 0; i < ioc->msix_vector_count; i++) ++ ioc->msix_table[i] = ioc->msix_table_backup[i]; ++} ++ ++/** ++ * _base_check_enable_msix - checks MSIX capabable. ++ * @ioc: per adapter object ++ * ++ * Check to see if card is capable of MSIX, and set number ++ * of avaliable msix vectors ++ */ ++static int ++_base_check_enable_msix(struct MPT2SAS_ADAPTER *ioc) ++{ ++ int base; ++ u16 message_control; ++ u32 msix_table_offset; ++ ++ base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX); ++ if (!base) { ++ dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "msix not " ++ "supported\n", ioc->name)); ++ return -EINVAL; ++ } ++ ++ /* get msix vector count */ ++ pci_read_config_word(ioc->pdev, base + 2, &message_control); ++ ioc->msix_vector_count = (message_control & 0x3FF) + 1; ++ ++ /* get msix table */ ++ pci_read_config_dword(ioc->pdev, base + 4, &msix_table_offset); ++ msix_table_offset &= 0xFFFFFFF8; ++ ioc->msix_table = (u32 *)((void *)ioc->chip + msix_table_offset); ++ ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "msix is supported, " ++ "vector_count(%d), table_offset(0x%08x), table(%p)\n", ioc->name, ++ ioc->msix_vector_count, msix_table_offset, ioc->msix_table)); ++ return 0; ++} ++ ++/** ++ * _base_disable_msix - disables msix ++ * @ioc: per adapter object ++ * ++ */ ++static void ++_base_disable_msix(struct MPT2SAS_ADAPTER *ioc) ++{ ++ if (!ioc->msix_enable) ++ return; ++ pci_disable_msix(ioc->pdev); ++ ioc->msix_enable = 0; ++} ++ ++/** ++ * _base_enable_msix - enables msix, failback to io_apic ++ * @ioc: per adapter object ++ * ++ */ ++static int ++_base_enable_msix(struct MPT2SAS_ADAPTER *ioc) ++{ ++ struct msix_entry entries; ++ int r; ++ u8 try_msix = 0; ++ ++ if (msix_disable == -1 || msix_disable == 0) ++ try_msix = 1; ++ ++ if (!try_msix) ++ goto try_ioapic; ++ ++ if (_base_check_enable_msix(ioc) != 0) ++ goto try_ioapic; ++ ++ memset(&entries, 0, sizeof(struct msix_entry)); ++ r = pci_enable_msix(ioc->pdev, &entries, 1); ++ if (r) { ++ dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "pci_enable_msix " ++ "failed (r=%d) !!!\n", ioc->name, r)); ++ goto try_ioapic; ++ } ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++ r = request_irq(entries.vector, _base_interrupt, IRQF_SHARED, ++ ioc->name, ioc); ++#else ++ r = request_irq(entries.vector, _base_interrupt, SA_SHIRQ, ++ ioc->name, ioc); ++#endif ++ if (r) { ++ dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "unable to allocate " ++ "interrupt %d !!!\n", ioc->name, entries.vector)); ++ pci_disable_msix(ioc->pdev); ++ goto try_ioapic; ++ } ++ ++ ioc->pci_irq = entries.vector; ++ ioc->msix_enable = 1; ++ return 0; ++ ++/* failback to io_apic interrupt routing */ ++ try_ioapic: ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++ r = request_irq(ioc->pdev->irq, _base_interrupt, IRQF_SHARED, ++ ioc->name, ioc); ++#else ++ r = request_irq(ioc->pdev->irq, _base_interrupt, SA_SHIRQ, ioc->name, ++ ioc); ++#endif ++ if (r) { ++ printk(MPT2SAS_ERR_FMT "unable to allocate interrupt %d!\n", ++ ioc->name, ioc->pdev->irq); ++ r = -EBUSY; ++ goto out_fail; ++ } ++ ++ ioc->pci_irq = ioc->pdev->irq; ++ return 0; ++ ++ out_fail: ++ return r; ++} ++ ++/** ++ * mpt2sas_base_map_resources - map in controller resources (io/irq/memap) ++ * @ioc: per adapter object ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_base_map_resources(struct MPT2SAS_ADAPTER *ioc) ++{ ++ struct pci_dev *pdev = ioc->pdev; ++ u32 memap_sz; ++ u32 pio_sz; ++ int i, r = 0; ++ ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ++ ioc->name, __func__)); ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) ++ if (pci_enable_device(pdev)) { ++ printk(MPT2SAS_WARN_FMT "pci_enable_device: failed\n", ++ ioc->name); ++ return -ENODEV; ++ } ++ ++ if (pci_request_regions(pdev, MPT2SAS_DRIVER_NAME)) { ++ printk(MPT2SAS_WARN_FMT "pci_request_regions: failed\n", ++ ioc->name); ++ r = -ENODEV; ++ goto out_fail; ++ } ++#else ++ ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); ++ if (pci_enable_device_mem(pdev)) { ++ printk(MPT2SAS_WARN_FMT "pci_enable_device_mem: " ++ "failed\n", ioc->name); ++ return -ENODEV; ++ } ++ ++ ++ if (pci_request_selected_regions(pdev, ioc->bars, ++ MPT2SAS_DRIVER_NAME)) { ++ printk(MPT2SAS_WARN_FMT "pci_request_selected_regions: " ++ "failed\n", ioc->name); ++ r = -ENODEV; ++ goto out_fail; ++ } ++#endif ++ ++ pci_set_master(pdev); ++ ++ if (_base_config_dma_addressing(ioc, pdev) != 0) { ++ printk(MPT2SAS_WARN_FMT "no suitable DMA mask for %s\n", ++ ioc->name, pci_name(pdev)); ++ r = -ENODEV; ++ goto out_fail; ++ } ++ ++ for (i = 0, memap_sz = 0, pio_sz = 0 ; i < DEVICE_COUNT_RESOURCE; i++) { ++ if (pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE_IO) { ++ if (pio_sz) ++ continue; ++ ioc->pio_chip = pci_resource_start(pdev, i); ++ pio_sz = pci_resource_len(pdev, i); ++ } else { ++ if (memap_sz) ++ continue; ++ ioc->chip_phys = pci_resource_start(pdev, i); ++ memap_sz = pci_resource_len(pdev, i); ++ ioc->chip = ioremap(ioc->chip_phys, memap_sz); ++ if (ioc->chip == NULL) { ++ printk(MPT2SAS_ERR_FMT "unable to map adapter " ++ "memory!\n", ioc->name); ++ r = -EINVAL; ++ goto out_fail; ++ } ++ } ++ } ++ ++ _base_mask_interrupts(ioc); ++ r = _base_enable_msix(ioc); ++ if (r) ++ goto out_fail; ++ ++ printk(MPT2SAS_INFO_FMT "%s: IRQ %d\n", ++ ioc->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" : ++ "IO-APIC enabled"), ioc->pci_irq); ++ printk(MPT2SAS_INFO_FMT "iomem(0x%lx), mapped(0x%p), size(%d)\n", ++ ioc->name, ioc->chip_phys, ioc->chip, memap_sz); ++ printk(MPT2SAS_INFO_FMT "ioport(0x%lx), size(%d)\n", ++ ioc->name, ioc->pio_chip, pio_sz); ++ ++ return 0; ++ ++ out_fail: ++ if (ioc->chip_phys) ++ iounmap(ioc->chip); ++ ioc->chip_phys = 0; ++ ioc->pci_irq = -1; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) ++ pci_release_regions(pdev); ++#else ++ pci_release_selected_regions(ioc->pdev, ioc->bars); ++#endif ++ pci_disable_device(pdev); ++ return r; ++} ++ ++/** ++ * mpt2sas_base_get_msg_frame_dma - obtain request mf pointer phys addr ++ * @ioc: per adapter object ++ * @smid: system request message index(smid zero is invalid) ++ * ++ * Returns phys pointer to message frame. ++ */ ++dma_addr_t ++mpt2sas_base_get_msg_frame_dma(struct MPT2SAS_ADAPTER *ioc, u16 smid) ++{ ++ return ioc->request_dma + (smid * ioc->request_sz); ++} ++ ++/** ++ * mpt2sas_base_get_msg_frame - obtain request mf pointer ++ * @ioc: per adapter object ++ * @smid: system request message index(smid zero is invalid) ++ * ++ * Returns virt pointer to message frame. ++ */ ++void * ++mpt2sas_base_get_msg_frame(struct MPT2SAS_ADAPTER *ioc, u16 smid) ++{ ++ return (void *)(ioc->request + (smid * ioc->request_sz)); ++} ++ ++/** ++ * mpt2sas_base_get_sense_buffer - obtain a sense buffer virt addr ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * ++ * Returns virt pointer to sense buffer. ++ */ ++void * ++mpt2sas_base_get_sense_buffer(struct MPT2SAS_ADAPTER *ioc, u16 smid) ++{ ++ return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE)); ++} ++ ++/** ++ * mpt2sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * ++ * Returns phys pointer to sense buffer. ++ */ ++dma_addr_t ++mpt2sas_base_get_sense_buffer_dma(struct MPT2SAS_ADAPTER *ioc, u16 smid) ++{ ++ return ioc->sense_dma + ((smid - 1) * SCSI_SENSE_BUFFERSIZE); ++} ++ ++/** ++ * mpt2sas_base_get_reply_virt_addr - obtain reply frames virt address ++ * @ioc: per adapter object ++ * @phys_addr: lower 32 physical addr of the reply ++ * ++ * Converts 32bit lower physical addr into a virt address. ++ */ ++void * ++mpt2sas_base_get_reply_virt_addr(struct MPT2SAS_ADAPTER *ioc, u32 phys_addr) ++{ ++ if (!phys_addr) ++ return NULL; ++ return ioc->reply + (phys_addr - (u32)ioc->reply_dma); ++} ++ ++/** ++ * mpt2sas_base_get_smid - obtain a free smid ++ * @ioc: per adapter object ++ * @cb_idx: callback index ++ * ++ * Returns smid (zero is invalid) ++ */ ++u16 ++mpt2sas_base_get_smid(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx) ++{ ++ unsigned long flags; ++ struct request_tracker *request; ++ u16 smid; ++ ++ spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); ++ if (list_empty(&ioc->free_list)) { ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++ printk(MPT2SAS_ERR_FMT "%s: smid not available\n", ++ ioc->name, __func__); ++ return 0; ++ } ++ ++ request = list_entry(ioc->free_list.next, ++ struct request_tracker, tracker_list); ++ request->cb_idx = cb_idx; ++ smid = request->smid; ++ list_del(&request->tracker_list); ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++ return smid; ++} ++ ++ ++/** ++ * mpt2sas_base_free_smid - put smid back on free_list ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_free_smid(struct MPT2SAS_ADAPTER *ioc, u16 smid) ++{ ++ unsigned long flags; ++#if defined(CHAIN_POOL) ++ struct chain_tracker *chain_req, *next; ++#endif ++ ++ spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); ++#if defined(CHAIN_POOL) ++ if (!list_empty(&ioc->scsi_lookup[smid - 1].chain_list)) { ++ list_for_each_entry_safe(chain_req, next, ++ &ioc->scsi_lookup[smid - 1].chain_list, tracker_list) { ++ list_del_init(&chain_req->tracker_list); ++ list_add_tail(&chain_req->tracker_list, ++ &ioc->free_chain_list); ++ } ++ } ++#endif ++ ioc->scsi_lookup[smid - 1].cb_idx = 0xFF; ++ list_add_tail(&ioc->scsi_lookup[smid - 1].tracker_list, ++ &ioc->free_list); ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++ ++ /* ++ * See _wait_for_commands_to_complete() call with regards to this code. ++ */ ++ if (ioc->shost_recovery && ioc->pending_io_count) { ++ if (ioc->pending_io_count == 1) ++ wake_up(&ioc->reset_wq); ++ ioc->pending_io_count--; ++ } ++} ++ ++/** ++ * _base_writeq - 64 bit write to MMIO ++ * @ioc: per adapter object ++ * @b: data payload ++ * @addr: address in MMIO space ++ * @writeq_lock: spin lock ++ * ++ * Glue for handling an atomic 64 bit word to MMIO. This special handling takes ++ * care of 32 bit environment where its not quarenteed to send the entire word ++ * in one transfer. ++ */ ++#ifndef writeq ++static inline void ++_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) ++{ ++ unsigned long flags; ++ __u64 data_out = cpu_to_le64(b); ++ ++ spin_lock_irqsave(writeq_lock, flags); ++ writel((u32)(data_out), addr); ++ writel((u32)(data_out >> 32), (addr + 4)); ++ spin_unlock_irqrestore(writeq_lock, flags); ++} ++#else ++static inline void ++_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) ++{ ++ writeq(cpu_to_le64(b), addr); ++} ++#endif ++ ++/** ++ * mpt2sas_base_put_smid_scsi_io - send SCSI_IO request to firmware ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @vf_id: virtual function id ++ * @handle: device handle ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_put_smid_scsi_io(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 vf_id, ++ u16 handle) ++{ ++ Mpi2RequestDescriptorUnion_t descriptor; ++ u64 *request = (u64 *)&descriptor; ++ ++ ++ descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; ++ descriptor.SCSIIO.VF_ID = vf_id; ++ descriptor.SCSIIO.SMID = cpu_to_le16(smid); ++ descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); ++ descriptor.SCSIIO.LMID = 0; ++ _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, ++ &ioc->scsi_lookup_lock); ++} ++ ++ ++/** ++ * mpt2sas_base_put_smid_hi_priority - send Task Managment request to firmware ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @vf_id: virtual function id ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_put_smid_hi_priority(struct MPT2SAS_ADAPTER *ioc, u16 smid, ++ u8 vf_id) ++{ ++ Mpi2RequestDescriptorUnion_t descriptor; ++ u64 *request = (u64 *)&descriptor; ++ ++ descriptor.HighPriority.RequestFlags = ++ MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; ++ descriptor.HighPriority.VF_ID = vf_id; ++ descriptor.HighPriority.SMID = cpu_to_le16(smid); ++ descriptor.HighPriority.LMID = 0; ++ descriptor.HighPriority.Reserved1 = 0; ++ _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, ++ &ioc->scsi_lookup_lock); ++} ++ ++/** ++ * mpt2sas_base_put_smid_default - Default, primarily used for config pages ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @vf_id: virtual function id ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_put_smid_default(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 vf_id) ++{ ++ Mpi2RequestDescriptorUnion_t descriptor; ++ u64 *request = (u64 *)&descriptor; ++ ++ descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; ++ descriptor.Default.VF_ID = vf_id; ++ descriptor.Default.SMID = cpu_to_le16(smid); ++ descriptor.Default.LMID = 0; ++ descriptor.Default.DescriptorTypeDependent = 0; ++ _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, ++ &ioc->scsi_lookup_lock); ++} ++ ++/** ++ * mpt2sas_base_put_smid_target_assist - send Target Assist/Status to firmware ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @vf_id: virtual function id ++ * @io_index: value used to track the IO ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_put_smid_target_assist(struct MPT2SAS_ADAPTER *ioc, u16 smid, ++ u8 vf_id, u16 io_index) ++{ ++ Mpi2RequestDescriptorUnion_t descriptor; ++ u64 *request = (u64 *)&descriptor; ++ ++ descriptor.SCSITarget.RequestFlags = ++ MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET; ++ descriptor.SCSITarget.VF_ID = vf_id; ++ descriptor.SCSITarget.SMID = cpu_to_le16(smid); ++ descriptor.SCSITarget.LMID = 0; ++ descriptor.SCSITarget.IoIndex = cpu_to_le16(io_index); ++ _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, ++ &ioc->scsi_lookup_lock); ++} ++ ++/** ++ * _base_display_dell_branding - Disply branding string ++ * @ioc: per adapter object ++ * ++ * Return nothing. ++ */ ++static void ++_base_display_dell_branding(struct MPT2SAS_ADAPTER *ioc) ++{ ++ char dell_branding[MPT2SAS_DELL_BRANDING_SIZE]; ++ ++ if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_DELL) ++ return; ++ ++ memset(dell_branding, 0, MPT2SAS_DELL_BRANDING_SIZE); ++ switch (ioc->pdev->subsystem_device) { ++ case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID: ++ strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING, ++ MPT2SAS_DELL_BRANDING_SIZE - 1); ++ break; ++ case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID: ++ strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING, ++ MPT2SAS_DELL_BRANDING_SIZE - 1); ++ break; ++ case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID: ++ strncpy(dell_branding, ++ MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING, ++ MPT2SAS_DELL_BRANDING_SIZE - 1); ++ break; ++ case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID: ++ strncpy(dell_branding, ++ MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING, ++ MPT2SAS_DELL_BRANDING_SIZE - 1); ++ break; ++ case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID: ++ strncpy(dell_branding, ++ MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING, ++ MPT2SAS_DELL_BRANDING_SIZE - 1); ++ break; ++ case MPT2SAS_DELL_PERC_H200_SSDID: ++ strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_BRANDING, ++ MPT2SAS_DELL_BRANDING_SIZE - 1); ++ break; ++ case MPT2SAS_DELL_6GBPS_SAS_SSDID: ++ strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_BRANDING, ++ MPT2SAS_DELL_BRANDING_SIZE - 1); ++ break; ++ default: ++ sprintf(dell_branding, "0x%4X", ioc->pdev->subsystem_device); ++ break; ++ } ++ ++ printk(MPT2SAS_INFO_FMT "%s: Vendor(0x%04X), Device(0x%04X)," ++ " SSVID(0x%04X), SSDID(0x%04X)\n", ioc->name, dell_branding, ++ ioc->pdev->vendor, ioc->pdev->device, ioc->pdev->subsystem_vendor, ++ ioc->pdev->subsystem_device); ++} ++ ++/** ++ * _base_display_ioc_capabilities - Disply IOC's capabilities. ++ * @ioc: per adapter object ++ * ++ * Return nothing. ++ */ ++static void ++_base_display_ioc_capabilities(struct MPT2SAS_ADAPTER *ioc) ++{ ++ int i = 0; ++ char desc[16]; ++ u8 revision; ++ u32 iounit_pg1_flags; ++ ++ pci_read_config_byte(ioc->pdev, PCI_CLASS_REVISION, &revision); ++ strncpy(desc, ioc->manu_pg0.ChipName, 16); ++ printk(MPT2SAS_INFO_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), " ++ "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n", ++ ioc->name, desc, ++ (ioc->facts.FWVersion.Word & 0xFF000000) >> 24, ++ (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16, ++ (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, ++ ioc->facts.FWVersion.Word & 0x000000FF, ++ revision, ++ (ioc->bios_pg3.BiosVersion & 0xFF000000) >> 24, ++ (ioc->bios_pg3.BiosVersion & 0x00FF0000) >> 16, ++ (ioc->bios_pg3.BiosVersion & 0x0000FF00) >> 8, ++ ioc->bios_pg3.BiosVersion & 0x000000FF); ++ ++ _base_display_dell_branding(ioc); ++ ++ printk(MPT2SAS_INFO_FMT "Protocol=(", ioc->name); ++ ++ if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) { ++ printk("Initiator"); ++ i++; ++ } ++ ++ if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) { ++ printk("%sTarget", i ? "," : ""); ++ i++; ++ } ++ ++ i = 0; ++ printk("), "); ++ printk("Capabilities=("); ++ ++ if (ioc->facts.IOCCapabilities & ++ MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) { ++ printk("Raid"); ++ i++; ++ } ++ ++ if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) { ++ printk("%sTLR", i ? "," : ""); ++ i++; ++ } ++ ++ if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) { ++ printk("%sMulticast", i ? "," : ""); ++ i++; ++ } ++ ++ if (ioc->facts.IOCCapabilities & ++ MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) { ++ printk("%sBIDI Target", i ? "," : ""); ++ i++; ++ } ++ ++ if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) { ++ printk("%sEEDP", i ? "," : ""); ++ i++; ++ } ++ ++ if (ioc->facts.IOCCapabilities & ++ MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) { ++ printk("%sSnapshot Buffer", i ? "," : ""); ++ i++; ++ } ++ ++ if (ioc->facts.IOCCapabilities & ++ MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) { ++ printk("%sDiag Trace Buffer", i ? "," : ""); ++ i++; ++ } ++ ++ if (ioc->facts.IOCCapabilities & ++ MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) { ++ printk("%sTask Set Full", i ? "," : ""); ++ i++; ++ } ++ ++ iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); ++ if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) { ++ printk("%sNCQ", i ? "," : ""); ++ i++; ++ } ++ ++ printk(")\n"); ++} ++ ++/** ++ * _base_static_config_pages - static start of day config pages ++ * @ioc: per adapter object ++ * ++ * Return nothing. ++ */ ++static void ++_base_static_config_pages(struct MPT2SAS_ADAPTER *ioc) ++{ ++ Mpi2ConfigReply_t mpi_reply; ++ u32 iounit_pg1_flags; ++ ++ mpt2sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0); ++ if (ioc->ir_firmware) ++ mpt2sas_config_get_manufacturing_pg10(ioc, &mpi_reply, ++ &ioc->manu_pg10); ++ mpt2sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2); ++ mpt2sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3); ++ mpt2sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8); ++ mpt2sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0); ++ mpt2sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); ++ _base_display_ioc_capabilities(ioc); ++ ++ /* ++ * Enable task_set_full handling in iounit_pg1 when the ++ * facts capabilities indicate that its supported. ++ */ ++ iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); ++ if ((ioc->facts.IOCCapabilities & ++ MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING)) ++ iounit_pg1_flags &= ++ ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; ++ else ++ iounit_pg1_flags |= ++ MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; ++ ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags); ++ mpt2sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); ++} ++ ++/** ++ * _base_release_memory_pools - release memory ++ * @ioc: per adapter object ++ * ++ * Free memory allocated from _base_allocate_memory_pools. ++ * ++ * Return nothing. ++ */ ++static void ++_base_release_memory_pools(struct MPT2SAS_ADAPTER *ioc) ++{ ++ dexitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ if (ioc->request) { ++ pci_free_consistent(ioc->pdev, ioc->request_dma_sz, ++ ioc->request, ioc->request_dma); ++ dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "request_pool(0x%p)" ++ ": free\n", ioc->name, ioc->request)); ++ ioc->request = NULL; ++ } ++ ++ if (ioc->sense) { ++ pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); ++ if (ioc->sense_dma_pool) ++ pci_pool_destroy(ioc->sense_dma_pool); ++ dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_pool(0x%p)" ++ ": free\n", ioc->name, ioc->sense)); ++ ioc->sense = NULL; ++ } ++ ++ if (ioc->reply) { ++ pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma); ++ if (ioc->reply_dma_pool) ++ pci_pool_destroy(ioc->reply_dma_pool); ++ dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_pool(0x%p)" ++ ": free\n", ioc->name, ioc->reply)); ++ ioc->reply = NULL; ++ } ++ ++ if (ioc->reply_free) { ++ pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free, ++ ioc->reply_free_dma); ++ if (ioc->reply_free_dma_pool) ++ pci_pool_destroy(ioc->reply_free_dma_pool); ++ dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_pool" ++ "(0x%p): free\n", ioc->name, ioc->reply_free)); ++ ioc->reply_free = NULL; ++ } ++ ++ if (ioc->reply_post_free) { ++ pci_pool_free(ioc->reply_post_free_dma_pool, ++ ioc->reply_post_free, ioc->reply_post_free_dma); ++ if (ioc->reply_post_free_dma_pool) ++ pci_pool_destroy(ioc->reply_post_free_dma_pool); ++ dexitprintk(ioc, printk(MPT2SAS_INFO_FMT ++ "reply_post_free_pool(0x%p): free\n", ioc->name, ++ ioc->reply_post_free)); ++ ioc->reply_post_free = NULL; ++ } ++ ++ if (ioc->config_page) { ++ dexitprintk(ioc, printk(MPT2SAS_INFO_FMT ++ "config_page(0x%p): free\n", ioc->name, ++ ioc->config_page)); ++ pci_free_consistent(ioc->pdev, ioc->config_page_sz, ++ ioc->config_page, ioc->config_page_dma); ++ } ++ ++ kfree(ioc->scsi_lookup); ++#if defined(CHAIN_POOL) ++ kfree(ioc->chain_lookup); ++#endif ++} ++ ++/** ++ * _base_allocate_memory_pools - allocate start of day memory pools ++ * @ioc: per adapter object ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 success, anything else error ++ */ ++static int ++_base_allocate_memory_pools(struct MPT2SAS_ADAPTER *ioc, int sleep_flag) ++{ ++ Mpi2IOCFactsReply_t *facts; ++ u32 queue_size, queue_diff; ++ u16 max_sge_elements; ++ u16 num_of_reply_frames; ++ u16 chains_needed_per_io; ++ u32 sz, total_sz; ++ u16 i; ++ u32 retry_sz; ++ u16 max_request_credit; ++ ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ retry_sz = 0; ++ facts = &ioc->facts; ++ ++ /* command line tunables for max sgl entries */ ++ if (max_sgl_entries != -1) { ++ ioc->shost->sg_tablesize = (max_sgl_entries < ++ MPT2SAS_SG_DEPTH) ? max_sgl_entries : ++ MPT2SAS_SG_DEPTH; ++ } else { ++ ioc->shost->sg_tablesize = MPT2SAS_SG_DEPTH; ++ } ++ ++ /* command line tunables for max controller queue depth */ ++ if (max_queue_depth != -1) { ++ max_request_credit = (max_queue_depth < facts->RequestCredit) ++ ? max_queue_depth : facts->RequestCredit; ++ } else { ++ max_request_credit = (facts->RequestCredit > ++ MPT2SAS_MAX_REQUEST_QUEUE) ? MPT2SAS_MAX_REQUEST_QUEUE : ++ facts->RequestCredit; ++ } ++ ioc->request_depth = max_request_credit; ++ ++#if defined(TARGET_MODE) ++ if ((INTERNAL_CMDS_COUNT + NUM_CMD_BUFFERS) > ioc->request_depth) { ++ printk(MPT2SAS_ERR_FMT "request_depth too small!!!!\n", ++ ioc->name); ++ goto out; ++ } ++#endif ++ ++ /* request frame size */ ++ ioc->request_sz = facts->IOCRequestFrameSize * 4; ++ ++ /* reply frame size */ ++ ioc->reply_sz = facts->ReplyFrameSize * 4; ++ ++ retry_allocation: ++ total_sz = 0; ++ /* calculate number of sg elements left over in the 1st frame */ ++ max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) - ++ sizeof(Mpi2SGEIOUnion_t)) + ioc->sge_size); ++ ioc->max_sges_in_main_message = max_sge_elements/ioc->sge_size; ++ ++ /* now do the same for a chain buffer */ ++ max_sge_elements = ioc->request_sz - ioc->sge_size; ++ ioc->max_sges_in_chain_message = max_sge_elements/ioc->sge_size; ++ ++ ioc->chain_offset_value_for_main_message = ++ ((sizeof(Mpi2SCSIIORequest_t) - sizeof(Mpi2SGEIOUnion_t)) + ++ (ioc->max_sges_in_chain_message * ioc->sge_size)) / 4; ++ ++ /* ++ * MPT2SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE ++ */ ++ chains_needed_per_io = ((ioc->shost->sg_tablesize - ++ ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message) ++ + 1; ++ if (chains_needed_per_io > facts->MaxChainDepth) { ++ chains_needed_per_io = facts->MaxChainDepth; ++ ioc->shost->sg_tablesize = min_t(u16, ++ ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message ++ * chains_needed_per_io), ioc->shost->sg_tablesize); ++ } ++ ioc->chains_needed_per_io = chains_needed_per_io; ++ ++ /* reply free queue sizing - taking into account for events */ ++ num_of_reply_frames = ioc->request_depth + 32; ++ ++ /* number of replies frames can't be a multiple of 16 */ ++ /* decrease number of reply frames by 1 */ ++ if (!(num_of_reply_frames % 16)) ++ num_of_reply_frames--; ++ ++ /* calculate number of reply free queue entries ++ * (must be multiple of 16) ++ */ ++ ++ /* (we know reply_free_queue_depth is not a multiple of 16) */ ++ queue_size = num_of_reply_frames; ++ queue_size += 16 - (queue_size % 16); ++ ioc->reply_free_queue_depth = queue_size; ++ ++ /* reply descriptor post queue sizing */ ++ /* this size should be the number of request frames + number of reply ++ * frames ++ */ ++ ++ queue_size = ioc->request_depth + num_of_reply_frames + 1; ++ /* round up to 16 byte boundary */ ++ if (queue_size % 16) ++ queue_size += 16 - (queue_size % 16); ++ ++ /* check against IOC maximum reply post queue depth */ ++ if (queue_size > facts->MaxReplyDescriptorPostQueueDepth) { ++ queue_diff = queue_size - ++ facts->MaxReplyDescriptorPostQueueDepth; ++ ++ /* round queue_diff up to multiple of 16 */ ++ if (queue_diff % 16) ++ queue_diff += 16 - (queue_diff % 16); ++ ++ /* adjust request_depth, reply_free_queue_depth, ++ * and queue_size ++ */ ++ ioc->request_depth -= queue_diff; ++ ioc->reply_free_queue_depth -= queue_diff; ++ queue_size -= queue_diff; ++ } ++ ioc->reply_post_queue_depth = queue_size; ++ ++ /* max scsi host queue depth */ ++#if defined(TARGET_MODE) ++ ioc->shost->can_queue = ioc->request_depth - INTERNAL_CMDS_COUNT - ++ NUM_CMD_BUFFERS; ++#else ++ ioc->shost->can_queue = ioc->request_depth - INTERNAL_CMDS_COUNT; ++#endif ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsi host queue: depth" ++ "(%d)\n", ioc->name, ioc->shost->can_queue)); ++ ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scatter gather: " ++ "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), " ++ "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message, ++ ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize, ++ ioc->chains_needed_per_io)); ++ ++ /* contiguous pool for request and chains, 16 byte align, one extra " ++ * "frame for smid=0 ++ */ ++#if defined(CHAIN_POOL) ++ ioc->chain_depth = ioc->chains_needed_per_io * ioc->shost->can_queue; ++#else ++ ioc->chain_depth = ioc->chains_needed_per_io * ioc->request_depth; ++#endif ++ sz = ((ioc->request_depth + 1 + ioc->chain_depth) * ioc->request_sz); ++ ++ ioc->request_dma_sz = sz; ++ ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma); ++ if (!ioc->request) { ++ printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent " ++ "failed: req_depth(%d), chains_per_io(%d), frame_sz(%d), " ++ "total(%d kB)\n", ioc->name, ioc->request_depth, ++ ioc->chains_needed_per_io, ioc->request_sz, sz/1024); ++ if (ioc->request_depth < MPT2SAS_SAS_QUEUE_DEPTH) ++ goto out; ++ retry_sz += 64; ++ ioc->request_depth = max_request_credit - retry_sz; ++ goto retry_allocation; ++ } ++ ++ if (retry_sz) ++ printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent " ++ "succeed: req_depth(%d), chains_per_io(%d), frame_sz(%d), " ++ "total(%d kb)\n", ioc->name, ioc->request_depth, ++ ioc->chains_needed_per_io, ioc->request_sz, sz/1024); ++ ++ ioc->chain = ioc->request + ((ioc->request_depth + 1) * ++ ioc->request_sz); ++ ioc->chain_dma = ioc->request_dma + ((ioc->request_depth + 1) * ++ ioc->request_sz); ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool(0x%p): " ++ "depth(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ++ ioc->request, ioc->request_depth, ioc->request_sz, ++ ((ioc->request_depth + 1) * ioc->request_sz)/1024)); ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "chain pool(0x%p): depth" ++ "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ioc->chain, ++ ioc->chain_depth, ioc->request_sz, ((ioc->chain_depth * ++ ioc->request_sz))/1024)); ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool: dma(0x%llx)\n", ++ ioc->name, (unsigned long long) ioc->request_dma)); ++ total_sz += sz; ++ ++ ioc->scsi_lookup = kcalloc(ioc->request_depth, ++ sizeof(struct request_tracker), GFP_KERNEL); ++ if (!ioc->scsi_lookup) { ++ printk(MPT2SAS_ERR_FMT "scsi_lookup: kcalloc failed\n", ++ ioc->name); ++ goto out; ++ } ++ ++ /* initialize some bits */ ++ for (i = 0; i < ioc->request_depth; i++) ++ ioc->scsi_lookup[i].smid = i + 1; ++ ++#if defined(CHAIN_POOL) ++ ioc->chain_lookup = kcalloc(ioc->chain_depth, ++ sizeof(struct chain_tracker), GFP_KERNEL); ++ if (!ioc->chain_lookup) { ++ printk(MPT2SAS_ERR_FMT "chain_lookup: kcalloc failed\n", ++ ioc->name); ++ goto out; ++ } ++ for (i = 0; i < ioc->chain_depth; i++) ++ ioc->chain_lookup[i].index = i; ++#endif ++ ++ /* sense buffers, 4 byte align */ ++ sz = ioc->request_depth * SCSI_SENSE_BUFFERSIZE; ++ ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4, ++ 0); ++ if (!ioc->sense_dma_pool) { ++ printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_create failed\n", ++ ioc->name); ++ goto out; ++ } ++ ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL, ++ &ioc->sense_dma); ++ if (!ioc->sense) { ++ printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_alloc failed\n", ++ ioc->name); ++ goto out; ++ } ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT ++ "sense pool(0x%p): depth(%d), element_size(%d), pool_size" ++ "(%d kB)\n", ioc->name, ioc->sense, ioc->request_depth, ++ SCSI_SENSE_BUFFERSIZE, sz/1024)); ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_dma(0x%llx)\n", ++ ioc->name, (unsigned long long)ioc->sense_dma)); ++ total_sz += sz; ++ ++ /* reply pool, 4 byte align */ ++ sz = ioc->reply_free_queue_depth * ioc->reply_sz; ++ ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4, ++ 0); ++ if (!ioc->reply_dma_pool) { ++ printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_create failed\n", ++ ioc->name); ++ goto out; ++ } ++ ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL, ++ &ioc->reply_dma); ++ if (!ioc->reply) { ++ printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_alloc failed\n", ++ ioc->name); ++ goto out; ++ } ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply pool(0x%p): depth" ++ "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ioc->reply, ++ ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024)); ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_dma(0x%llx)\n", ++ ioc->name, (unsigned long long)ioc->reply_dma)); ++ total_sz += sz; ++ ++ /* reply free queue, 16 byte align */ ++ sz = ioc->reply_free_queue_depth * 4; ++ ioc->reply_free_dma_pool = pci_pool_create("reply_free pool", ++ ioc->pdev, sz, 16, 0); ++ if (!ioc->reply_free_dma_pool) { ++ printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_create " ++ "failed\n", ioc->name); ++ goto out; ++ } ++ ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL, ++ &ioc->reply_free_dma); ++ if (!ioc->reply_free) { ++ printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_alloc " ++ "failed\n", ioc->name); ++ goto out; ++ } ++ memset(ioc->reply_free, 0, sz); ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free pool(0x%p): " ++ "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name, ++ ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024)); ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_dma" ++ "(0x%llx)\n", ioc->name, (unsigned long long)ioc->reply_free_dma)); ++ total_sz += sz; ++ ++ /* reply post queue, 16 byte align */ ++ sz = ioc->reply_post_queue_depth * sizeof(Mpi2DefaultReplyDescriptor_t); ++ ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool", ++ ioc->pdev, sz, 16, 0); ++ if (!ioc->reply_post_free_dma_pool) { ++ printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_create " ++ "failed\n", ioc->name); ++ goto out; ++ } ++ ioc->reply_post_free = pci_pool_alloc(ioc->reply_post_free_dma_pool , ++ GFP_KERNEL, &ioc->reply_post_free_dma); ++ if (!ioc->reply_post_free) { ++ printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_alloc " ++ "failed\n", ioc->name); ++ goto out; ++ } ++ memset(ioc->reply_post_free, 0, sz); ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply post free pool" ++ "(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n", ++ ioc->name, ioc->reply_post_free, ioc->reply_post_queue_depth, 8, ++ sz/1024)); ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_post_free_dma = " ++ "(0x%llx)\n", ioc->name, (unsigned long long) ++ ioc->reply_post_free_dma)); ++ total_sz += sz; ++ ++ ioc->config_page_sz = 512; ++ ioc->config_page = pci_alloc_consistent(ioc->pdev, ++ ioc->config_page_sz, &ioc->config_page_dma); ++ if (!ioc->config_page) { ++ printk(MPT2SAS_ERR_FMT "config page: pci_pool_alloc " ++ "failed\n", ioc->name); ++ goto out; ++ } ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config page(0x%p): size" ++ "(%d)\n", ioc->name, ioc->config_page, ioc->config_page_sz)); ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config_page_dma" ++ "(0x%llx)\n", ioc->name, (unsigned long long)ioc->config_page_dma)); ++ total_sz += ioc->config_page_sz; ++ ++ printk(MPT2SAS_INFO_FMT "Allocated physical memory: size(%d kB)\n", ++ ioc->name, total_sz/1024); ++ printk(MPT2SAS_INFO_FMT "Current Controller Queue Depth(%d), " ++ "Max Controller Queue Depth(%d)\n", ++ ioc->name, ioc->shost->can_queue, facts->RequestCredit); ++ printk(MPT2SAS_INFO_FMT "Scatter Gather Elements per IO(%d)\n", ++ ioc->name, ioc->shost->sg_tablesize); ++ return 0; ++ ++ out: ++ _base_release_memory_pools(ioc); ++ return -ENOMEM; ++} ++ ++ ++/** ++ * mpt2sas_base_get_iocstate - Get the current state of a MPT adapter. ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * @cooked: Request raw or cooked IOC state ++ * ++ * Returns all IOC Doorbell register bits if cooked==0, else just the ++ * Doorbell bits in MPI_IOC_STATE_MASK. ++ */ ++u32 ++mpt2sas_base_get_iocstate(struct MPT2SAS_ADAPTER *ioc, int cooked) ++{ ++ u32 s, sc; ++ ++ s = readl(&ioc->chip->Doorbell); ++ sc = s & MPI2_IOC_STATE_MASK; ++ return cooked ? sc : s; ++} ++ ++/** ++ * _base_wait_on_iocstate - waiting on a particular ioc state ++ * @ioc_state: controller state { READY, OPERATIONAL, or RESET } ++ * @timeout: timeout in second ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_base_wait_on_iocstate(struct MPT2SAS_ADAPTER *ioc, u32 ioc_state, int timeout, ++ int sleep_flag) ++{ ++ u32 count, cntdn; ++ u32 current_state; ++ ++ count = 0; ++ cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; ++ do { ++ current_state = mpt2sas_base_get_iocstate(ioc, 1); ++ if (current_state == ioc_state) ++ return 0; ++ if (count && current_state == MPI2_IOC_STATE_FAULT) ++ break; ++ if (sleep_flag == CAN_SLEEP) ++ msleep(1); ++ else ++ udelay(500); ++ count++; ++ } while (--cntdn); ++ ++ return current_state; ++} ++ ++/** ++ * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by ++ * a write to the doorbell) ++ * @ioc: per adapter object ++ * @timeout: timeout in second ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 for success, non-zero for failure. ++ * ++ * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell. ++ */ ++static int ++_base_wait_for_doorbell_int(struct MPT2SAS_ADAPTER *ioc, int timeout, ++ int sleep_flag) ++{ ++ u32 cntdn, count; ++ u32 int_status; ++ ++ count = 0; ++ cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; ++ do { ++ int_status = readl(&ioc->chip->HostInterruptStatus); ++ if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { ++ dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "successfull count(%d), timeout(%d)\n", ioc->name, ++ __func__, count, timeout)); ++ return 0; ++ } ++ if (sleep_flag == CAN_SLEEP) ++ msleep(1); ++ else ++ udelay(500); ++ count++; ++ } while (--cntdn); ++ ++ printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), " ++ "int_status(%x)!\n", ioc->name, __func__, count, int_status); ++ return -EFAULT; ++} ++ ++/** ++ * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell. ++ * @ioc: per adapter object ++ * @timeout: timeout in second ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 for success, non-zero for failure. ++ * ++ * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to ++ * doorbell. ++ */ ++static int ++_base_wait_for_doorbell_ack(struct MPT2SAS_ADAPTER *ioc, int timeout, ++ int sleep_flag) ++{ ++ u32 cntdn, count; ++ u32 int_status; ++ u32 doorbell; ++ ++ count = 0; ++ cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; ++ do { ++ int_status = readl(&ioc->chip->HostInterruptStatus); ++ if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { ++ dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "successfull count(%d), timeout(%d)\n", ioc->name, ++ __func__, count, timeout)); ++ return 0; ++ } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { ++ doorbell = readl(&ioc->chip->Doorbell); ++ if ((doorbell & MPI2_IOC_STATE_MASK) == ++ MPI2_IOC_STATE_FAULT) { ++ mpt2sas_base_fault_info(ioc , doorbell); ++ return -EFAULT; ++ } ++ } else if (int_status == 0xFFFFFFFF) ++ goto out; ++ ++ if (sleep_flag == CAN_SLEEP) ++ msleep(1); ++ else ++ udelay(500); ++ count++; ++ } while (--cntdn); ++ ++ out: ++ printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), " ++ "int_status(%x)!\n", ioc->name, __func__, count, int_status); ++ return -EFAULT; ++} ++ ++/** ++ * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use ++ * @ioc: per adapter object ++ * @timeout: timeout in second ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 for success, non-zero for failure. ++ * ++ */ ++static int ++_base_wait_for_doorbell_not_used(struct MPT2SAS_ADAPTER *ioc, int timeout, ++ int sleep_flag) ++{ ++ u32 cntdn, count; ++ u32 doorbell_reg; ++ ++ count = 0; ++ cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; ++ do { ++ doorbell_reg = readl(&ioc->chip->Doorbell); ++ if (!(doorbell_reg & MPI2_DOORBELL_USED)) { ++ dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "successfull count(%d), timeout(%d)\n", ioc->name, ++ __func__, count, timeout)); ++ return 0; ++ } ++ if (sleep_flag == CAN_SLEEP) ++ msleep(1); ++ else ++ udelay(500); ++ count++; ++ } while (--cntdn); ++ ++ printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), " ++ "doorbell_reg(%x)!\n", ioc->name, __func__, count, doorbell_reg); ++ return -EFAULT; ++} ++ ++/** ++ * _base_send_ioc_reset - send doorbell reset ++ * @ioc: per adapter object ++ * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET ++ * @timeout: timeout in second ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_base_send_ioc_reset(struct MPT2SAS_ADAPTER *ioc, u8 reset_type, int timeout, ++ int sleep_flag) ++{ ++ u32 ioc_state; ++ int r = 0; ++ ++ if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) { ++ printk(MPT2SAS_ERR_FMT "%s: unknown reset_type\n", ++ ioc->name, __func__); ++ return -EFAULT; ++ } ++ ++ if (!(ioc->facts.IOCCapabilities & ++ MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY)) ++ return -EFAULT; ++ ++ printk(MPT2SAS_INFO_FMT "sending message unit reset !!\n", ioc->name); ++ ++ writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT, ++ &ioc->chip->Doorbell); ++ if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) { ++ r = -EFAULT; ++ goto out; ++ } ++ ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, ++ timeout, sleep_flag); ++ if (ioc_state) { ++ printk(MPT2SAS_ERR_FMT "%s: failed going to ready state " ++ " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state); ++ r = -EFAULT; ++ goto out; ++ } ++ out: ++ printk(MPT2SAS_INFO_FMT "message unit reset: %s\n", ++ ioc->name, ((r == 0) ? "SUCCESS" : "FAILED")); ++ return r; ++} ++ ++/** ++ * _base_handshake_req_reply_wait - send request thru doorbell interface ++ * @ioc: per adapter object ++ * @request_bytes: request length ++ * @request: pointer having request payload ++ * @reply_bytes: reply length ++ * @reply: pointer to reply payload ++ * @timeout: timeout in second ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_base_handshake_req_reply_wait(struct MPT2SAS_ADAPTER *ioc, int request_bytes, ++ u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag) ++{ ++ MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply; ++ int i; ++ u8 failed; ++ u16 dummy; ++ u32 *mfp; ++ ++ /* make sure doorbell is not in use */ ++ if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) { ++ printk(MPT2SAS_ERR_FMT "doorbell is in use " ++ " (line=%d)\n", ioc->name, __LINE__); ++ return -EFAULT; ++ } ++ ++ /* clear pending doorbell interrupts from previous state changes */ ++ if (readl(&ioc->chip->HostInterruptStatus) & ++ MPI2_HIS_IOC2SYS_DB_STATUS) ++ writel(0, &ioc->chip->HostInterruptStatus); ++ ++ /* send message to ioc */ ++ writel(((MPI2_FUNCTION_HANDSHAKE<chip->Doorbell); ++ ++ if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) { ++ printk(MPT2SAS_ERR_FMT "doorbell handshake " ++ "int failed (line=%d)\n", ioc->name, __LINE__); ++ return -EFAULT; ++ } ++ writel(0, &ioc->chip->HostInterruptStatus); ++ ++ if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) { ++ printk(MPT2SAS_ERR_FMT "doorbell handshake " ++ "ack failed (line=%d)\n", ioc->name, __LINE__); ++ return -EFAULT; ++ } ++ ++ /* send message 32-bits at a time */ ++ for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) { ++ writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell); ++ if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) ++ failed = 1; ++ } ++ ++ if (failed) { ++ printk(MPT2SAS_ERR_FMT "doorbell handshake " ++ "sending request failed (line=%d)\n", ioc->name, __LINE__); ++ return -EFAULT; ++ } ++ ++ /* now wait for the reply */ ++ if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) { ++ printk(MPT2SAS_ERR_FMT "doorbell handshake " ++ "int failed (line=%d)\n", ioc->name, __LINE__); ++ return -EFAULT; ++ } ++ ++ /* read the first two 16-bits, it gives the total length of the reply */ ++ reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell) ++ & MPI2_DOORBELL_DATA_MASK); ++ writel(0, &ioc->chip->HostInterruptStatus); ++ if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) { ++ printk(MPT2SAS_ERR_FMT "doorbell handshake " ++ "int failed (line=%d)\n", ioc->name, __LINE__); ++ return -EFAULT; ++ } ++ reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell) ++ & MPI2_DOORBELL_DATA_MASK); ++ writel(0, &ioc->chip->HostInterruptStatus); ++ ++ for (i = 2; i < default_reply->MsgLength * 2; i++) { ++ if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) { ++ printk(MPT2SAS_ERR_FMT "doorbell " ++ "handshake int failed (line=%d)\n", ioc->name, ++ __LINE__); ++ return -EFAULT; ++ } ++ if (i >= reply_bytes/2) /* overflow case */ ++ dummy = readl(&ioc->chip->Doorbell); ++ else ++ reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell) ++ & MPI2_DOORBELL_DATA_MASK); ++ writel(0, &ioc->chip->HostInterruptStatus); ++ } ++ ++ _base_wait_for_doorbell_int(ioc, 5, sleep_flag); ++ if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) { ++ dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "doorbell is in use " ++ " (line=%d)\n", ioc->name, __LINE__)); ++ } ++ writel(0, &ioc->chip->HostInterruptStatus); ++ ++ if (ioc->logging_level & MPT_DEBUG_INIT) { ++ mfp = (u32 *)reply; ++ printk(KERN_DEBUG "\toffset:data\n"); ++ for (i = 0; i < reply_bytes/4; i++) ++ printk(KERN_DEBUG "\t[0x%02x]:%08x\n", i*4, ++ le32_to_cpu(mfp[i])); ++ } ++ return 0; ++} ++ ++/** ++ * mpt2sas_base_sas_iounit_control - send sas iounit control to FW ++ * @ioc: per adapter object ++ * @mpi_reply: the reply payload from FW ++ * @mpi_request: the request payload sent to FW ++ * ++ * The SAS IO Unit Control Request message allows the host to perform low-level ++ * operations, such as resets on the PHYs of the IO Unit, also allows the host ++ * to obtain the IOC assigned device handles for a device if it has other ++ * identifying information about the device, in addition allows the host to ++ * remove IOC resources associated with the device. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_base_sas_iounit_control(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2SasIoUnitControlReply_t *mpi_reply, ++ Mpi2SasIoUnitControlRequest_t *mpi_request) ++{ ++ u16 smid; ++ u32 ioc_state; ++ unsigned long timeleft; ++ u8 issue_reset; ++ int rc; ++ void *request; ++ u16 wait_state_count; ++ ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ mutex_lock(&ioc->base_cmds.mutex); ++ ++ if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) { ++ printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ wait_state_count = 0; ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { ++ if (wait_state_count++ == 10) { ++ printk(MPT2SAS_ERR_FMT ++ "%s: failed due to ioc not operational\n", ++ ioc->name, __func__); ++ rc = -EFAULT; ++ goto out; ++ } ++ ssleep(1); ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ printk(MPT2SAS_INFO_FMT "%s: waiting for " ++ "operational state(count=%d)\n", ioc->name, ++ __func__, wait_state_count); ++ } ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ rc = 0; ++ ioc->base_cmds.status = MPT2_CMD_PENDING; ++ request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ioc->base_cmds.smid = smid; ++ memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)); ++ if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || ++ mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) ++ ioc->ioc_link_reset_in_progress = 1; ++ mpt2sas_base_put_smid_default(ioc, smid, mpi_request->VF_ID); ++ timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, ++ msecs_to_jiffies(10000)); ++ if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || ++ mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) && ++ ioc->ioc_link_reset_in_progress) ++ ioc->ioc_link_reset_in_progress = 0; ++ if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) { ++ printk(MPT2SAS_ERR_FMT "%s: timeout\n", ++ ioc->name, __func__); ++ _debug_dump_mf(mpi_request, ++ sizeof(Mpi2SasIoUnitControlRequest_t)/4); ++ if (!(ioc->base_cmds.status & MPT2_CMD_RESET)) ++ issue_reset = 1; ++ goto issue_host_reset; ++ } ++ if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID) ++ memcpy(mpi_reply, ioc->base_cmds.reply, ++ sizeof(Mpi2SasIoUnitControlReply_t)); ++ else ++ memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t)); ++ ioc->base_cmds.status = MPT2_CMD_NOT_USED; ++ goto out; ++ ++ issue_host_reset: ++ if (issue_reset) ++ mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, ++ FORCE_BIG_HAMMER); ++ ioc->base_cmds.status = MPT2_CMD_NOT_USED; ++ rc = -EFAULT; ++ out: ++ mutex_unlock(&ioc->base_cmds.mutex); ++ return rc; ++} ++ ++ ++/** ++ * mpt2sas_base_scsi_enclosure_processor - sending request to sep device ++ * @ioc: per adapter object ++ * @mpi_reply: the reply payload from FW ++ * @mpi_request: the request payload sent to FW ++ * ++ * The SCSI Enclosure Processor request message causes the IOC to ++ * communicate with SES devices to control LED status signals. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_base_scsi_enclosure_processor(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request) ++{ ++ u16 smid; ++ u32 ioc_state; ++ unsigned long timeleft; ++ u8 issue_reset; ++ int rc; ++ void *request; ++ u16 wait_state_count; ++ ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ mutex_lock(&ioc->base_cmds.mutex); ++ ++ if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) { ++ printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ wait_state_count = 0; ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { ++ if (wait_state_count++ == 10) { ++ printk(MPT2SAS_ERR_FMT ++ "%s: failed due to ioc not operational\n", ++ ioc->name, __func__); ++ rc = -EFAULT; ++ goto out; ++ } ++ ssleep(1); ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ printk(MPT2SAS_INFO_FMT "%s: waiting for " ++ "operational state(count=%d)\n", ioc->name, ++ __func__, wait_state_count); ++ } ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ rc = 0; ++ ioc->base_cmds.status = MPT2_CMD_PENDING; ++ request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ioc->base_cmds.smid = smid; ++ memcpy(request, mpi_request, sizeof(Mpi2SepReply_t)); ++ mpt2sas_base_put_smid_default(ioc, smid, mpi_request->VF_ID); ++ timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, ++ msecs_to_jiffies(10000)); ++ if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) { ++ printk(MPT2SAS_ERR_FMT "%s: timeout\n", ++ ioc->name, __func__); ++ _debug_dump_mf(mpi_request, ++ sizeof(Mpi2SepRequest_t)/4); ++ if (!(ioc->base_cmds.status & MPT2_CMD_RESET)) ++ issue_reset = 1; ++ goto issue_host_reset; ++ } ++ if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID) ++ memcpy(mpi_reply, ioc->base_cmds.reply, ++ sizeof(Mpi2SepReply_t)); ++ else ++ memset(mpi_reply, 0, sizeof(Mpi2SepReply_t)); ++ ioc->base_cmds.status = MPT2_CMD_NOT_USED; ++ goto out; ++ ++ issue_host_reset: ++ if (issue_reset) ++ mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, ++ FORCE_BIG_HAMMER); ++ ioc->base_cmds.status = MPT2_CMD_NOT_USED; ++ rc = -EFAULT; ++ out: ++ mutex_unlock(&ioc->base_cmds.mutex); ++ return rc; ++} ++ ++/** ++ * _base_get_port_facts - obtain port facts reply and save in ioc ++ * @ioc: per adapter object ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_base_get_port_facts(struct MPT2SAS_ADAPTER *ioc, int port, int sleep_flag) ++{ ++ Mpi2PortFactsRequest_t mpi_request; ++ Mpi2PortFactsReply_t mpi_reply, *pfacts; ++ int mpi_reply_sz, mpi_request_sz, r; ++ ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ mpi_reply_sz = sizeof(Mpi2PortFactsReply_t); ++ mpi_request_sz = sizeof(Mpi2PortFactsRequest_t); ++ memset(&mpi_request, 0, mpi_request_sz); ++ mpi_request.Function = MPI2_FUNCTION_PORT_FACTS; ++ mpi_request.PortNumber = port; ++ r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, ++ (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP); ++ ++ if (r != 0) { ++ printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n", ++ ioc->name, __func__, r); ++ return r; ++ } ++ ++ pfacts = &ioc->pfacts[port]; ++ memset(pfacts, 0, sizeof(Mpi2PortFactsReply_t)); ++ pfacts->PortNumber = mpi_reply.PortNumber; ++ pfacts->VP_ID = mpi_reply.VP_ID; ++ pfacts->VF_ID = mpi_reply.VF_ID; ++ pfacts->MaxPostedCmdBuffers = ++ le16_to_cpu(mpi_reply.MaxPostedCmdBuffers); ++ ++ return 0; ++} ++ ++/** ++ * _base_get_ioc_facts - obtain ioc facts reply and save in ioc ++ * @ioc: per adapter object ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_base_get_ioc_facts(struct MPT2SAS_ADAPTER *ioc, int sleep_flag) ++{ ++ Mpi2IOCFactsRequest_t mpi_request; ++ Mpi2IOCFactsReply_t mpi_reply, *facts; ++ int mpi_reply_sz, mpi_request_sz, r; ++ ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t); ++ mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t); ++ memset(&mpi_request, 0, mpi_request_sz); ++ mpi_request.Function = MPI2_FUNCTION_IOC_FACTS; ++ r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, ++ (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP); ++ ++ if (r != 0) { ++ printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n", ++ ioc->name, __func__, r); ++ return r; ++ } ++ ++ facts = &ioc->facts; ++ memset(facts, 0, sizeof(Mpi2IOCFactsReply_t)); ++ facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion); ++ facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion); ++ facts->VP_ID = mpi_reply.VP_ID; ++ facts->VF_ID = mpi_reply.VF_ID; ++ facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions); ++ facts->MaxChainDepth = mpi_reply.MaxChainDepth; ++ facts->WhoInit = mpi_reply.WhoInit; ++ facts->NumberOfPorts = mpi_reply.NumberOfPorts; ++ facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit); ++ facts->MaxReplyDescriptorPostQueueDepth = ++ le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth); ++ facts->ProductID = le16_to_cpu(mpi_reply.ProductID); ++ facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities); ++ if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)) ++ ioc->ir_firmware = 1; ++ facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word); ++ facts->IOCRequestFrameSize = ++ le16_to_cpu(mpi_reply.IOCRequestFrameSize); ++ facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators); ++ facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets); ++ ioc->shost->max_id = -1; ++ facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders); ++ facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures); ++ facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags); ++ facts->HighPriorityCredit = ++ le16_to_cpu(mpi_reply.HighPriorityCredit); ++ facts->ReplyFrameSize = mpi_reply.ReplyFrameSize; ++ facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle); ++ ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hba queue depth(%d), " ++ "max chains per io(%d)\n", ioc->name, facts->RequestCredit, ++ facts->MaxChainDepth)); ++ dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request frame size(%d), " ++ "reply frame size(%d)\n", ioc->name, ++ facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4)); ++ return 0; ++} ++ ++/** ++ * _base_send_ioc_init - send ioc_init to firmware ++ * @ioc: per adapter object ++ * @VF_ID: virtual function id ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_base_send_ioc_init(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, int sleep_flag) ++{ ++ Mpi2IOCInitRequest_t mpi_request; ++ Mpi2IOCInitReply_t mpi_reply; ++ int r; ++ ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_IOC_INIT; ++ mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER; ++ mpi_request.VF_ID = VF_ID; ++ mpi_request.MsgVersion = cpu_to_le16(MPI2_VERSION); ++ mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION); ++ ++ /* In MPI Revision I (0xA), the SystemReplyFrameSize(offset 0x18) was ++ * removed and made reserved. For those with older firmware will need ++ * this fix. It was decided that the Reply and Request frame sizes are ++ * the same. ++ */ ++ if ((ioc->facts.HeaderVersion >> 8) < 0xA) ++ mpi_request.Reserved7 = cpu_to_le16(ioc->reply_sz); ++ ++ mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4); ++ mpi_request.ReplyDescriptorPostQueueDepth = ++ cpu_to_le16(ioc->reply_post_queue_depth); ++ mpi_request.ReplyFreeQueueDepth = ++ cpu_to_le16(ioc->reply_free_queue_depth); ++ ++#if BITS_PER_LONG > 32 ++ mpi_request.SenseBufferAddressHigh = ++ cpu_to_le32(ioc->sense_dma >> 32); ++ mpi_request.SystemReplyAddressHigh = ++ cpu_to_le32(ioc->reply_dma >> 32); ++ mpi_request.SystemRequestFrameBaseAddress = ++ cpu_to_le64(ioc->request_dma); ++ mpi_request.ReplyFreeQueueAddress = ++ cpu_to_le64(ioc->reply_free_dma); ++ mpi_request.ReplyDescriptorPostQueueAddress = ++ cpu_to_le64(ioc->reply_post_free_dma); ++#else ++ mpi_request.SystemRequestFrameBaseAddress = ++ cpu_to_le32(ioc->request_dma); ++ mpi_request.ReplyFreeQueueAddress = ++ cpu_to_le32(ioc->reply_free_dma); ++ mpi_request.ReplyDescriptorPostQueueAddress = ++ cpu_to_le32(ioc->reply_post_free_dma); ++#endif ++ ++ if (ioc->logging_level & MPT_DEBUG_INIT) { ++ u32 *mfp; ++ int i; ++ ++ mfp = (u32 *)&mpi_request; ++ printk(KERN_DEBUG "\toffset:data\n"); ++ for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++) ++ printk(KERN_DEBUG "\t[0x%02x]:%08x\n", i*4, ++ le32_to_cpu(mfp[i])); ++ } ++ ++ r = _base_handshake_req_reply_wait(ioc, ++ sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request, ++ sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10, ++ sleep_flag); ++ ++ if (r != 0) { ++ printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n", ++ ioc->name, __func__, r); ++ return r; ++ } ++ ++ if (mpi_reply.IOCStatus != MPI2_IOCSTATUS_SUCCESS || ++ mpi_reply.IOCLogInfo) { ++ printk(MPT2SAS_ERR_FMT "%s: failed\n", ioc->name, __func__); ++ r = -EIO; ++ } ++ ++ return 0; ++} ++ ++/** ++ * _base_send_port_enable - send port_enable(discovery stuff) to firmware ++ * @ioc: per adapter object ++ * @VF_ID: virtual function id ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_base_send_port_enable(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, int sleep_flag) ++{ ++ Mpi2PortEnableRequest_t *mpi_request; ++ u32 ioc_state; ++ unsigned long timeleft; ++ int r = 0; ++ u16 smid; ++ ++ printk(MPT2SAS_INFO_FMT "sending port enable !!\n", ioc->name); ++ ++ if (ioc->base_cmds.status & MPT2_CMD_PENDING) { ++ printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n", ++ ioc->name, __func__); ++ return -EAGAIN; ++ } ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ return -EAGAIN; ++ } ++ ++ ioc->base_cmds.status = MPT2_CMD_PENDING; ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ioc->base_cmds.smid = smid; ++ memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); ++ mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; ++ mpi_request->VF_ID = VF_ID; ++ ++ mpt2sas_base_put_smid_default(ioc, smid, VF_ID); ++ timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, ++ 300*HZ); ++ if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) { ++ printk(MPT2SAS_ERR_FMT "%s: timeout\n", ++ ioc->name, __func__); ++ _debug_dump_mf(mpi_request, ++ sizeof(Mpi2PortEnableRequest_t)/4); ++ if (ioc->base_cmds.status & MPT2_CMD_RESET) ++ r = -EFAULT; ++ else ++ r = -ETIME; ++ goto out; ++ } else ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: complete\n", ++ ioc->name, __func__)); ++ ++ ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_OPERATIONAL, ++ 60, sleep_flag); ++ if (ioc_state) { ++ printk(MPT2SAS_ERR_FMT "%s: failed going to operational state " ++ " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state); ++ r = -EFAULT; ++ } ++ out: ++ ioc->base_cmds.status = MPT2_CMD_NOT_USED; ++ printk(MPT2SAS_INFO_FMT "port enable: %s\n", ++ ioc->name, ((r == 0) ? "SUCCESS" : "FAILED")); ++ return r; ++} ++ ++/** ++ * _base_unmask_events - turn on notification for this event ++ * @ioc: per adapter object ++ * @event: firmware event ++ * ++ * The mask is stored in ioc->event_masks. ++ */ ++static void ++_base_unmask_events(struct MPT2SAS_ADAPTER *ioc, u16 event) ++{ ++ u32 desired_event; ++ ++ if (event >= 128) ++ return; ++ ++ desired_event = (1 << (event % 32)); ++ ++ if (event < 32) ++ ioc->event_masks[0] &= ~desired_event; ++ else if (event < 64) ++ ioc->event_masks[1] &= ~desired_event; ++ else if (event < 96) ++ ioc->event_masks[2] &= ~desired_event; ++ else if (event < 128) ++ ioc->event_masks[3] &= ~desired_event; ++} ++ ++/** ++ * _base_event_notification - send event notification ++ * @ioc: per adapter object ++ * @VF_ID: virtual function id ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_base_event_notification(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, int sleep_flag) ++{ ++ Mpi2EventNotificationRequest_t *mpi_request; ++ unsigned long timeleft; ++ u16 smid; ++ int r = 0; ++ int i; ++ ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ if (ioc->base_cmds.status & MPT2_CMD_PENDING) { ++ printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n", ++ ioc->name, __func__); ++ return -EAGAIN; ++ } ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ return -EAGAIN; ++ } ++ ioc->base_cmds.status = MPT2_CMD_PENDING; ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ioc->base_cmds.smid = smid; ++ memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t)); ++ mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; ++ mpi_request->VF_ID = VF_ID; ++ for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) ++ mpi_request->EventMasks[i] = ++ le32_to_cpu(ioc->event_masks[i]); ++ mpt2sas_base_put_smid_default(ioc, smid, VF_ID); ++ timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ); ++ if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) { ++ printk(MPT2SAS_ERR_FMT "%s: timeout\n", ++ ioc->name, __func__); ++ _debug_dump_mf(mpi_request, ++ sizeof(Mpi2EventNotificationRequest_t)/4); ++ if (ioc->base_cmds.status & MPT2_CMD_RESET) ++ r = -EFAULT; ++ else ++ r = -ETIME; ++ } else ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: complete\n", ++ ioc->name, __func__)); ++ ioc->base_cmds.status = MPT2_CMD_NOT_USED; ++ return r; ++} ++ ++/** ++ * mpt2sas_base_validate_event_type - validating event types ++ * @ioc: per adapter object ++ * @event: firmware event ++ * ++ * This will turn on firmware event notification when application ++ * ask for that event. We don't mask events that are already enabled. ++ */ ++void ++mpt2sas_base_validate_event_type(struct MPT2SAS_ADAPTER *ioc, u32 *event_type) ++{ ++ int i, j; ++ u32 event_mask, desired_event; ++ u8 send_update_to_fw; ++ ++ for (i = 0, send_update_to_fw = 0; i < ++ MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) { ++ event_mask = ~event_type[i]; ++ desired_event = 1; ++ for (j = 0; j < 32; j++) { ++ if (!(event_mask & desired_event) && ++ (ioc->event_masks[i] & desired_event)) { ++ ioc->event_masks[i] &= ~desired_event; ++ send_update_to_fw = 1; ++ } ++ desired_event = (desired_event << 1); ++ } ++ } ++ ++ if (!send_update_to_fw) ++ return; ++ ++ mutex_lock(&ioc->base_cmds.mutex); ++ _base_event_notification(ioc, 0, CAN_SLEEP); ++ mutex_unlock(&ioc->base_cmds.mutex); ++} ++ ++/** ++ * _base_diag_reset - the "big hammer" start of day reset ++ * @ioc: per adapter object ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_base_diag_reset(struct MPT2SAS_ADAPTER *ioc, int sleep_flag) ++{ ++ u32 host_diagnostic; ++ u32 ioc_state; ++ u32 count; ++ u32 hcb_size; ++ ++ printk(MPT2SAS_INFO_FMT "sending diag reset !!\n", ioc->name); ++ ++ mpt2sas_base_save_msix_table(ioc); ++ ++ drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "clear interrupts\n", ++ ioc->name)); ++ writel(0, &ioc->chip->HostInterruptStatus); ++ ++ count = 0; ++ do { ++ /* Write magic sequence to WriteSequence register ++ * Loop until in diagnostic mode ++ */ ++ drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "write magic " ++ "sequence\n", ioc->name)); ++ writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); ++ writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence); ++ writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence); ++ writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence); ++ writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence); ++ writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence); ++ writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence); ++ ++ /* wait 100 msec */ ++ if (sleep_flag == CAN_SLEEP) ++ msleep(100); ++ else ++ mdelay(100); ++ ++ if (count++ > 20) ++ goto out; ++ ++ host_diagnostic = readl(&ioc->chip->HostDiagnostic); ++ drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "wrote magic " ++ "sequence: count(%d), host_diagnostic(0x%08x)\n", ++ ioc->name, count, host_diagnostic)); ++ ++ } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0); ++ ++ hcb_size = readl(&ioc->chip->HCBSize); ++ ++ drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "diag reset: issued\n", ++ ioc->name)); ++ writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER, ++ &ioc->chip->HostDiagnostic); ++ ++ /* don't access any registers for 50 milliseconds */ ++ msleep(50); ++ ++ /* 300 second max wait */ ++ for (count = 0; count < 3000000 ; count++) { ++ ++ host_diagnostic = readl(&ioc->chip->HostDiagnostic); ++ ++ if (host_diagnostic == 0xFFFFFFFF) ++ goto out; ++ if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER)) ++ break; ++ ++ /* wait 100 msec */ ++ if (sleep_flag == CAN_SLEEP) ++ msleep(1); ++ else ++ mdelay(1); ++ } ++ ++ if (host_diagnostic & MPI2_DIAG_HCB_MODE) { ++ ++ drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "restart the adapter " ++ "assuming the HCB Address points to good F/W\n", ++ ioc->name)); ++ host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK; ++ host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW; ++ writel(host_diagnostic, &ioc->chip->HostDiagnostic); ++ ++ drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT ++ "re-enable the HCDW\n", ioc->name)); ++ writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE, ++ &ioc->chip->HCBSize); ++ } ++ ++ drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "restart the adapter\n", ++ ioc->name)); ++ writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET, ++ &ioc->chip->HostDiagnostic); ++ ++ drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "disable writes to the " ++ "diagnostic register\n", ioc->name)); ++ writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); ++ ++ drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "Wait for FW to go to the " ++ "READY state\n", ioc->name)); ++ ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20, ++ sleep_flag); ++ if (ioc_state) { ++ printk(MPT2SAS_ERR_FMT "%s: failed going to ready state " ++ " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state); ++ goto out; ++ } ++ ++ mpt2sas_base_restore_msix_table(ioc); ++ printk(MPT2SAS_INFO_FMT "diag reset: SUCCESS\n", ioc->name); ++ return 0; ++ ++ out: ++ printk(MPT2SAS_ERR_FMT "diag reset: FAILED\n", ioc->name); ++ return -EFAULT; ++} ++ ++/** ++ * _base_make_ioc_ready - put controller in READY state ++ * @ioc: per adapter object ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * @type: FORCE_BIG_HAMMER or SOFT_RESET ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_base_make_ioc_ready(struct MPT2SAS_ADAPTER *ioc, int sleep_flag, ++ enum reset_type type) ++{ ++ u32 ioc_state; ++ ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 0); ++ dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: ioc_state(0x%08x)\n", ++ ioc->name, __func__, ioc_state)); ++ ++ if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ++ return 0; ++ ++ if (ioc_state & MPI2_DOORBELL_USED) { ++ dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "unexpected doorbell " ++ "active!\n", ioc->name)); ++ goto issue_diag_reset; ++ } ++ ++ if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { ++ mpt2sas_base_fault_info(ioc, ioc_state & ++ MPI2_DOORBELL_DATA_MASK); ++ goto issue_diag_reset; ++ } ++ ++ if (type == FORCE_BIG_HAMMER) ++ goto issue_diag_reset; ++ ++ if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) ++ if (!(_base_send_ioc_reset(ioc, ++ MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) ++ return 0; ++ ++ issue_diag_reset: ++ return _base_diag_reset(ioc, CAN_SLEEP); ++} ++ ++/** ++ * _base_make_ioc_operational - put controller in OPERATIONAL state ++ * @ioc: per adapter object ++ * @VF_ID: virtual function id ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_base_make_ioc_operational(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ int sleep_flag) ++{ ++ int r, i; ++ unsigned long flags; ++ u32 reply_address; ++ ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ /* initialize the scsi lookup free list */ ++ spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); ++ INIT_LIST_HEAD(&ioc->free_list); ++ for (i = 0; i < ioc->request_depth; i++) { ++#if defined(CHAIN_POOL) ++ INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list); ++#endif ++ ioc->scsi_lookup[i].cb_idx = 0xFF; ++ list_add_tail(&ioc->scsi_lookup[i].tracker_list, ++ &ioc->free_list); ++ } ++#if defined(CHAIN_POOL) ++ INIT_LIST_HEAD(&ioc->free_chain_list); ++ for (i = 0; i < ioc->chain_depth; i++) ++ list_add_tail(&ioc->chain_lookup[i].tracker_list, ++ &ioc->free_chain_list); ++#endif ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++ ++ /* initialize Reply Free Queue */ ++ for (i = 0, reply_address = (u32)ioc->reply_dma ; ++ i < ioc->reply_free_queue_depth ; i++, reply_address += ++ ioc->reply_sz) ++ ioc->reply_free[i] = cpu_to_le32(reply_address); ++ ++ /* initialize Reply Post Free Queue */ ++ for (i = 0; i < ioc->reply_post_queue_depth; i++) ++ ioc->reply_post_free[i].Words = ULLONG_MAX; ++ ++ r = _base_send_ioc_init(ioc, VF_ID, sleep_flag); ++ if (r) ++ return r; ++ ++ /* initialize the index's */ ++ ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1; ++ ioc->reply_post_host_index = 0; ++ writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex); ++ writel(0, &ioc->chip->ReplyPostHostIndex); ++ ++ _base_unmask_interrupts(ioc); ++ r = _base_event_notification(ioc, VF_ID, sleep_flag); ++ if (r) ++ return r; ++ ++ if (sleep_flag == CAN_SLEEP) ++ _base_static_config_pages(ioc); ++ ++#if defined(TARGET_MODE) ++ if (ioc->wait_for_port_enable_to_complete) ++ mpt2sas_stm_adapter_install(ioc); ++#endif ++ ++ r = _base_send_port_enable(ioc, VF_ID, sleep_flag); ++ if (r) ++ return r; ++ ++ return r; ++} ++ ++/** ++ * mpt2sas_base_free_resources - free resources controller resources ++ * @ioc: per adapter object ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_free_resources(struct MPT2SAS_ADAPTER *ioc) ++{ ++ struct pci_dev *pdev = ioc->pdev; ++ ++ dexitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ _base_mask_interrupts(ioc); ++ _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET); ++ if (ioc->pci_irq) { ++ synchronize_irq(pdev->irq); ++ free_irq(ioc->pci_irq, ioc); ++ } ++ _base_disable_msix(ioc); ++ if (ioc->chip_phys) ++ iounmap(ioc->chip); ++ ioc->pci_irq = -1; ++ ioc->chip_phys = 0; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) ++ pci_release_regions(pdev); ++#else ++ pci_release_selected_regions(ioc->pdev, ioc->bars); ++#endif ++ pci_disable_device(pdev); ++ return; ++} ++ ++/** ++ * mpt2sas_base_attach - attach controller instance ++ * @ioc: per adapter object ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_base_attach(struct MPT2SAS_ADAPTER *ioc) ++{ ++ int r, i; ++ ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ r = mpt2sas_base_map_resources(ioc); ++ if (r) ++ return r; ++ ++ if (ioc->msix_enable) { ++ ioc->msix_table_backup = kcalloc(ioc->msix_vector_count, ++ sizeof(u32), GFP_KERNEL); ++ if (!ioc->msix_table_backup) { ++ dfailprintk(ioc, printk(MPT2SAS_INFO_FMT ++ "allocation for msix_table_backup failed!!!\n", ++ ioc->name)); ++ goto out_free_resources; ++ } ++ } ++ ++ pci_set_drvdata(ioc->pdev, ioc->shost); ++ r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET); ++ if (r) ++ goto out_free_resources; ++ ++ r = _base_get_ioc_facts(ioc, CAN_SLEEP); ++ if (r) ++ goto out_free_resources; ++ ++ r = _base_allocate_memory_pools(ioc, CAN_SLEEP); ++ if (r) ++ goto out_free_resources; ++ ++ init_waitqueue_head(&ioc->reset_wq); ++ ++ /* base internal command bits */ ++ mutex_init(&ioc->base_cmds.mutex); ++ init_completion(&ioc->base_cmds.done); ++ ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); ++ ioc->base_cmds.status = MPT2_CMD_NOT_USED; ++ ++ /* transport internal command bits */ ++ ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); ++ ioc->transport_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_init(&ioc->transport_cmds.mutex); ++ init_completion(&ioc->transport_cmds.done); ++ ++ /* scsih internal command bits */ ++ ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); ++ ioc->scsih_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_init(&ioc->scsih_cmds.mutex); ++ ++ /* task management internal command bits */ ++ ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); ++ ioc->tm_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_init(&ioc->tm_cmds.mutex); ++ ++ /* config page internal command bits */ ++ ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); ++ ioc->config_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_init(&ioc->config_cmds.mutex); ++ ++ /* ctl module internal command bits */ ++ ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); ++ ioc->ctl_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_init(&ioc->ctl_cmds.mutex); ++ init_completion(&ioc->ctl_cmds.done); ++ ++ for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) ++ ioc->event_masks[i] = -1; ++ ++ /* here we enable the events we care about */ ++ _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY); ++ _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE); ++ _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST); ++ _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE); ++ _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE); ++ _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST); ++ _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME); ++ _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK); ++ _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS); ++ _base_unmask_events(ioc, MPI2_EVENT_TASK_SET_FULL); ++ _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED); ++#if defined(TARGET_MODE) ++ _base_unmask_events(ioc, MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE); ++ _base_unmask_events(ioc, MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW); ++ _base_unmask_events(ioc, MPI2_EVENT_HARD_RESET_RECEIVED); ++#endif ++ ++ ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts, ++ sizeof(Mpi2PortFactsReply_t), GFP_KERNEL); ++ if (!ioc->pfacts) ++ goto out_free_resources; ++ ++ for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) { ++ r = _base_get_port_facts(ioc, i, CAN_SLEEP); ++ if (r) ++ goto out_free_resources; ++ } ++ r = _base_make_ioc_operational(ioc, 0, CAN_SLEEP); ++ if (r) ++ goto out_free_resources; ++ ++ mpt2sas_base_start_watchdog(ioc); ++ return 0; ++ ++ out_free_resources: ++ ++ ioc->remove_host = 1; ++#if defined(TARGET_MODE) ++ mpt2sas_stm_adapter_dispose(ioc); ++#endif ++ ++ mpt2sas_base_free_resources(ioc); ++ _base_release_memory_pools(ioc); ++ pci_set_drvdata(ioc->pdev, NULL); ++ kfree(ioc->msix_table_backup); ++ kfree(ioc->tm_cmds.reply); ++ kfree(ioc->transport_cmds.reply); ++ kfree(ioc->scsih_cmds.reply); ++ kfree(ioc->config_cmds.reply); ++ kfree(ioc->base_cmds.reply); ++ kfree(ioc->ctl_cmds.reply); ++ kfree(ioc->pfacts); ++ ioc->ctl_cmds.reply = NULL; ++ ioc->base_cmds.reply = NULL; ++ ioc->tm_cmds.reply = NULL; ++ ioc->scsih_cmds.reply = NULL; ++ ioc->transport_cmds.reply = NULL; ++ ioc->config_cmds.reply = NULL; ++ ioc->pfacts = NULL; ++ return r; ++} ++ ++ ++/** ++ * mpt2sas_base_detach - remove controller instance ++ * @ioc: per adapter object ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_base_detach(struct MPT2SAS_ADAPTER *ioc) ++{ ++ ++ dexitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++#if defined(TARGET_MODE) ++ mpt2sas_stm_adapter_dispose(ioc); ++#endif ++ ++ mpt2sas_base_stop_watchdog(ioc); ++ mpt2sas_base_free_resources(ioc); ++ _base_release_memory_pools(ioc); ++ pci_set_drvdata(ioc->pdev, NULL); ++ kfree(ioc->msix_table_backup); ++ kfree(ioc->pfacts); ++ kfree(ioc->ctl_cmds.reply); ++ kfree(ioc->base_cmds.reply); ++ kfree(ioc->tm_cmds.reply); ++ kfree(ioc->transport_cmds.reply); ++ kfree(ioc->scsih_cmds.reply); ++ kfree(ioc->config_cmds.reply); ++} ++ ++/** ++ * _base_reset_handler - reset callback handler (for base) ++ * @ioc: per adapter object ++ * @reset_phase: phase ++ * ++ * The handler for doing any required cleanup or initialization. ++ * ++ * The reset phase can be MPT2_IOC_PRE_RESET, MPT2_IOC_AFTER_RESET, ++ * MPT2_IOC_DONE_RESET ++ * ++ * Return nothing. ++ */ ++static void ++_base_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase) ++{ ++ switch (reset_phase) { ++ case MPT2_IOC_PRE_RESET: ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "MPT2_IOC_PRE_RESET\n", ioc->name, __func__)); ++ break; ++ case MPT2_IOC_AFTER_RESET: ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "MPT2_IOC_AFTER_RESET\n", ioc->name, __func__)); ++ if (ioc->transport_cmds.status & MPT2_CMD_PENDING) { ++ ioc->transport_cmds.status |= MPT2_CMD_RESET; ++ mpt2sas_base_free_smid(ioc, ioc->transport_cmds.smid); ++ complete(&ioc->transport_cmds.done); ++ } ++ if (ioc->base_cmds.status & MPT2_CMD_PENDING) { ++ ioc->base_cmds.status |= MPT2_CMD_RESET; ++ mpt2sas_base_free_smid(ioc, ioc->base_cmds.smid); ++ complete(&ioc->base_cmds.done); ++ } ++ if (ioc->config_cmds.status & MPT2_CMD_PENDING) { ++ ioc->config_cmds.status |= MPT2_CMD_RESET; ++ mpt2sas_base_free_smid(ioc, ioc->config_cmds.smid); ++ ioc->config_cmds.smid = USHORT_MAX; ++ complete(&ioc->config_cmds.done); ++ } ++ break; ++ case MPT2_IOC_DONE_RESET: ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "MPT2_IOC_DONE_RESET\n", ioc->name, __func__)); ++ break; ++ } ++ mpt2sas_scsih_reset_handler(ioc, reset_phase); ++ mpt2sas_ctl_reset_handler(ioc, reset_phase); ++#if defined(TARGET_MODE) ++ mpt2sas_stm_reset_handler(ioc, reset_phase); ++#endif ++} ++ ++/** ++ * _wait_for_commands_to_complete - reset controller ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * ++ * This function waiting(3s) for all pending commands to complete ++ * prior to putting controller in reset. ++ */ ++static void ++_wait_for_commands_to_complete(struct MPT2SAS_ADAPTER *ioc, int sleep_flag) ++{ ++ u32 ioc_state; ++ unsigned long flags; ++ u16 i; ++ ++ ioc->pending_io_count = 0; ++ if (sleep_flag != CAN_SLEEP) ++ return; ++ ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 0); ++ if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) ++ return; ++ ++ /* pending command count */ ++ spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); ++ for (i = 0; i < ioc->request_depth; i++) ++ if (ioc->scsi_lookup[i].cb_idx != 0xFF) ++ ioc->pending_io_count++; ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++ ++ if (!ioc->pending_io_count) ++ return; ++ ++ /* wait for pending commands to complete */ ++ wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 3 * HZ); ++} ++ ++/** ++ * mpt2sas_base_hard_reset_handler - reset controller ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * @sleep_flag: CAN_SLEEP or NO_SLEEP ++ * @type: FORCE_BIG_HAMMER or SOFT_RESET ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_base_hard_reset_handler(struct MPT2SAS_ADAPTER *ioc, int sleep_flag, ++ enum reset_type type) ++{ ++ int r, i; ++ unsigned long flags; ++ ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: enter\n", ioc->name, ++ __func__)); ++ ++ spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); ++ if (ioc->shost_recovery) { ++ spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); ++ printk(MPT2SAS_ERR_FMT "%s: busy\n", ++ ioc->name, __func__); ++ return -EBUSY; ++ } ++ ioc->shost_recovery = 1; ++ spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); ++ ++ _base_reset_handler(ioc, MPT2_IOC_PRE_RESET); ++ _wait_for_commands_to_complete(ioc, sleep_flag); ++ _base_mask_interrupts(ioc); ++ r = _base_make_ioc_ready(ioc, sleep_flag, type); ++ if (r) ++ goto out; ++ _base_reset_handler(ioc, MPT2_IOC_AFTER_RESET); ++ for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) ++ r = _base_make_ioc_operational(ioc, ioc->pfacts[i].VF_ID, ++ sleep_flag); ++ if (!r) ++ _base_reset_handler(ioc, MPT2_IOC_DONE_RESET); ++ ++ out: ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: %s\n", ++ ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED"))); ++ ++ spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); ++ ioc->shost_recovery = 0; ++ spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); ++ ++ if (!r) ++ _base_reset_handler(ioc, MPT2_IOC_RUNNING); ++ return r; ++} +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpt2sas_base.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpt2sas_base.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,981 @@ ++/* ++ * This is the Fusion MPT base driver providing common API layer interface ++ * for access to MPT (Message Passing Technology) firmware. ++ * ++ * This code is based on drivers/scsi/mpt2sas/mpt2_base.h ++ * Copyright (C) 2007-2008 LSI Corporation ++ * (mailto:DL-MPTFusionLinux@lsi.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * NO WARRANTY ++ * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR ++ * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT ++ * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is ++ * solely responsible for determining the appropriateness of using and ++ * distributing the Program and assumes all risks associated with its ++ * exercise of rights under this Agreement, including but not limited to ++ * the risks and costs of program errors, damage to or loss of data, ++ * programs or equipment, and unavailability or interruption of operations. ++ ++ * DISCLAIMER OF LIABILITY ++ * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR ++ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED ++ * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ++ ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, ++ * USA. ++ */ ++ ++#ifndef MPT2SAS_BASE_H_INCLUDED ++#define MPT2SAS_BASE_H_INCLUDED ++ ++#include "mpi/mpi2_type.h" ++#include "mpi/mpi2.h" ++#include "mpi/mpi2_ioc.h" ++#include "mpi/mpi2_cnfg.h" ++#include "mpi/mpi2_init.h" ++#include "mpi/mpi2_raid.h" ++#include "mpi/mpi2_targ.h" ++#include "mpi/mpi2_tool.h" ++#include "mpi/mpi2_sas.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mpt2sas_compatibility.h" ++#include "mpt2sas_debug.h" ++ ++/* driver versioning info */ ++#define MPT2SAS_DRIVER_NAME "mpt2sas" ++#define MPT2SAS_AUTHOR "LSI Corporation " ++#define MPT2SAS_DESCRIPTION "LSI MPT Fusion SAS 2.0 Device Driver" ++#define MPT2SAS_DRIVER_VERSION "02.00.00.00" ++#define MPT2SAS_MAJOR_VERSION 02 ++#define MPT2SAS_MINOR_VERSION 00 ++#define MPT2SAS_BUILD_VERSION 00 ++#define MPT2SAS_RELEASE_VERSION 00 ++ ++/* ++ * Set MPT2SAS_SG_DEPTH value based on user input. ++ */ ++#ifdef CONFIG_SCSI_MPT2SAS_MAX_SGE ++#if CONFIG_SCSI_MPT2SAS_MAX_SGE < 16 ++#define MPT2SAS_SG_DEPTH 16 ++#elif CONFIG_SCSI_MPT2SAS_MAX_SGE > 128 ++#define MPT2SAS_SG_DEPTH 128 ++#else ++#define MPT2SAS_SG_DEPTH CONFIG_SCSI_MPT2SAS_MAX_SGE ++#endif ++#else ++#define MPT2SAS_SG_DEPTH 128 /* MAX_HW_SEGMENTS */ ++#endif ++ ++#if defined(TARGET_MODE) ++#include "mpt2sas_stm.h" ++#endif ++ ++/* ++ * Generic Defines ++ */ ++#define MPT2SAS_SATA_QUEUE_DEPTH 32 ++#define MPT2SAS_SAS_QUEUE_DEPTH 254 ++#define MPT2SAS_RAID_QUEUE_DEPTH 128 ++ ++#define MPT_NAME_LENGTH 32 /* generic length of strings */ ++#define MPT_STRING_LENGTH 64 ++ ++#define MPT_MAX_CALLBACKS 16 ++ ++#define CAN_SLEEP 1 ++#define NO_SLEEP 0 ++ ++#define INTERNAL_CMDS_COUNT 10 /* reserved cmds */ ++ ++#define MPI2_HIM_MASK 0xFFFFFFFF /* mask every bit*/ ++ ++#define MPT2SAS_INVALID_DEVICE_HANDLE 0xFFFF ++ ++/* ++ * reset phases ++ */ ++#define MPT2_IOC_PRE_RESET 1 /* prior to host reset */ ++#define MPT2_IOC_AFTER_RESET 2 /* just after host reset */ ++#define MPT2_IOC_DONE_RESET 3 /* links re-initialized */ ++#define MPT2_IOC_RUNNING 4 /* shost running */ ++ ++/* ++ * logging format ++ */ ++#define MPT2SAS_FMT "%s: " ++#define MPT2SAS_DEBUG_FMT KERN_DEBUG MPT2SAS_FMT ++#define MPT2SAS_INFO_FMT KERN_INFO MPT2SAS_FMT ++#define MPT2SAS_NOTE_FMT KERN_NOTICE MPT2SAS_FMT ++#define MPT2SAS_WARN_FMT KERN_WARNING MPT2SAS_FMT ++#define MPT2SAS_ERR_FMT KERN_ERR MPT2SAS_FMT ++ ++/* ++ * per target private data ++ */ ++#define MPT_TARGET_FLAGS_RAID_COMPONENT 0x01 ++#define MPT_TARGET_FLAGS_VOLUME 0x02 ++#define MPT_TARGET_FLAGS_DELETED 0x04 ++ ++/* Enable Multipath suport */ ++#define MPT2SAS_MULTIPATH ++ ++/* ++ * Dell HBA branding ++ */ ++#define MPT2SAS_DELL_BRANDING_SIZE 32 ++ ++#define MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING "Dell 6Gbps SAS HBA" ++#define MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING "Dell PERC H200 Adapter" ++#define MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING "Dell PERC H200 Integrated" ++#define MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING "Dell PERC H200 Modular" ++#define MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING "Dell PERC H200 Embedded" ++#define MPT2SAS_DELL_PERC_H200_BRANDING "Dell PERC H200" ++#define MPT2SAS_DELL_6GBPS_SAS_BRANDING "Dell 6Gbps SAS" ++ ++/* ++ * Dell HBA SSDIDs ++ */ ++#define MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID 0x1F1C ++#define MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID 0x1F1D ++#define MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID 0x1F1E ++#define MPT2SAS_DELL_PERC_H200_MODULAR_SSDID 0x1F1F ++#define MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID 0x1F20 ++#define MPT2SAS_DELL_PERC_H200_SSDID 0x1F21 ++#define MPT2SAS_DELL_6GBPS_SAS_SSDID 0x1F22 ++ ++/* ++ * End to End Data Protection Support ++ */ ++#define EEDP_SUPPORT ++#ifdef EEDP_SUPPORT ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) ++ ++#define PRO_R MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP ++#define PRO_W MPI2_SCSIIO_EEDPFLAGS_INSERT_OP ++#define PRO_V MPI2_SCSIIO_EEDPFLAGS_INSERT_OP ++ ++/* the read capacity 16 byte parameter block - defined in SBC-3 */ ++struct read_cap_parameter{ ++ u64 logical_block_addr; ++ u32 logical_block_length; ++ u8 prot_en:1; ++ u8 p_type:3; ++ u8 reserved0:4; ++ u8 logical_blocks_per_phyical_block:4; ++ u8 reserved1:4; ++ u16 lowest_aligned_log_block_address:14; ++ u16 reserved2:2; ++ u8 reserved3[16]; ++}; ++#endif ++#endif ++ ++/* OEM Identifiers */ ++#define MFG10_OEM_ID_INVALID (0x00000000) ++#define MFG10_OEM_ID_DELL (0x00000001) ++#define MFG10_OEM_ID_FSC (0x00000002) ++#define MFG10_OEM_ID_SUN (0x00000003) ++#define MFG10_OEM_ID_IBM (0x00000004) ++ ++/* GENERIC Flags 0*/ ++#define MFG10_GF0_OCE_DISABLED (0x00000001) ++#define MFG10_GF0_R1E_DRIVE_COUNT (0x00000002) ++#define MFG10_GF0_R10_DISPLAY (0x00000004) ++#define MFG10_GF0_SSD_DATA_SCRUB_DISABLE (0x00000008) ++#define MFG10_GF0_SINGLE_DRIVE_R0 (0x00000010) ++ ++/* OEM Specific Flags will come from OEM specific header files */ ++typedef struct _MPI2_CONFIG_PAGE_MAN_10 { ++ MPI2_CONFIG_PAGE_HEADER Header; /* 00h */ ++ U8 OEMIdentifier; /* 04h */ ++ U8 Reserved1; /* 05h */ ++ U16 Reserved2; /* 08h */ ++ U32 Reserved3; /* 0Ch */ ++ U32 GenericFlags0; /* 10h */ ++ U32 GenericFlags1; /* 14h */ ++ U32 Reserved4; /* 18h */ ++ U32 OEMSpecificFlags0; /* 1Ch */ ++ U32 OEMSpecificFlags1; /* 20h */ ++ U32 Reserved5[18]; /* 24h - 60h*/ ++} MPI2_CONFIG_PAGE_MAN_10, ++ MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_10, ++ Mpi2ManufacturingPage10_t, MPI2_POINTER pMpi2ManufacturingPage10_t; ++ ++/** ++ * struct MPT2SAS_TARGET - starget private hostdata ++ * @starget: starget object ++ * @sas_address: target sas address ++ * @handle: device handle ++ * @num_luns: number luns ++ * @flags: MPT_TARGET_FLAGS_XXX flags ++ * @deleted: target flaged for deletion ++ * @tm_busy: target is busy with TM request. ++ */ ++struct MPT2SAS_TARGET { ++ struct scsi_target *starget; ++ u64 sas_address; ++ u16 handle; ++ int num_luns; ++ u32 flags; ++ u8 deleted; ++ u8 tm_busy; ++}; ++ ++/* ++ * per device private data ++ */ ++#define MPT_DEVICE_FLAGS_INIT 0x01 ++#define MPT_DEVICE_TLR_ON 0x02 ++ ++/** ++ * struct MPT2SAS_DEVICE - sdev private hostdata ++ * @sas_target: starget private hostdata ++ * @lun: lun number ++ * @flags: MPT_DEVICE_XXX flags ++ * @configured_lun: lun is configured ++ * @block: device is in SDEV_BLOCK state ++ * @tlr_snoop_check: flag used in determining whether to disable TLR ++ * @eedp_enable: eedp support enable bit ++ * @eedp_type: 0(type_1), 1(type_2), 2(type_3) ++ * @eedp_block_length: block size ++ */ ++struct MPT2SAS_DEVICE { ++ struct MPT2SAS_TARGET *sas_target; ++ unsigned int lun; ++ u32 flags; ++ u8 configured_lun; ++ u8 block; ++ u8 tlr_snoop_check; ++#ifdef EEDP_SUPPORT ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) ++ u8 eedp_enable; ++ u8 eedp_type; ++#endif ++#endif ++}; ++ ++#define MPT2_CMD_NOT_USED 0x8000 /* free */ ++#define MPT2_CMD_COMPLETE 0x0001 /* completed */ ++#define MPT2_CMD_PENDING 0x0002 /* pending */ ++#define MPT2_CMD_REPLY_VALID 0x0004 /* reply is valid */ ++#define MPT2_CMD_RESET 0x0008 /* host reset dropped the command */ ++ ++/** ++ * struct _internal_cmd - internal commands struct ++ * @mutex: mutex ++ * @done: completion ++ * @reply: reply message pointer ++ * @status: MPT2_CMD_XXX status ++ * @smid: system message id ++ */ ++struct _internal_cmd { ++ struct mutex mutex; ++ struct completion done; ++ void *reply; ++ u16 status; ++ u16 smid; ++}; ++ ++#if (defined(CONFIG_SUSE_KERNEL) && defined(scsi_is_sas_phy_local)) || LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) ++#define MPT_WIDE_PORT_API 1 ++#define MPT_WIDE_PORT_API_PLUS 1 ++#endif ++ ++/* ++ * SAS Topology Structures ++ */ ++ ++/** ++ * struct _sas_device - attached device information ++ * @list: sas device list ++ * @starget: starget object ++ * @sas_address: device sas address ++ * @device_name: retrieved from the SAS IDENTIFY frame. ++ * @handle: device handle ++ * @parent_handle: handle to parent device ++ * @enclosure_handle: enclosure handle ++ * @enclosure_logical_id: enclosure logical identifier ++ * @volume_handle: volume handle (valid when hidden raid member) ++ * @volume_wwid: volume unique identifier ++ * @device_info: bitfield provides detailed info about the device ++ * @id: target id ++ * @channel: target channel ++ * @slot: number number ++ * @hidden_raid_component: set to 1 when this is a raid member ++ * @responding: used in _scsih_sas_device_mark_responding ++ */ ++struct _sas_device { ++ struct list_head list; ++ struct scsi_target *starget; ++ u64 sas_address; ++ u64 device_name; ++ u16 handle; ++ u16 parent_handle; ++ u16 enclosure_handle; ++ u64 enclosure_logical_id; ++ u16 volume_handle; ++ u64 volume_wwid; ++ u32 device_info; ++ int id; ++ int channel; ++ u16 slot; ++ u8 hidden_raid_component; ++ u8 responding; ++#ifdef MPT2SAS_MULTIPATH ++ u8 *serial_number; ++ struct MPT2SAS_ADAPTER *ioc; ++ struct _sas_device *sas_device_alt; ++#endif ++}; ++ ++/** ++ * struct _raid_device - raid volume link list ++ * @list: sas device list ++ * @starget: starget object ++ * @sdev: scsi device struct (volumes are single lun) ++ * @wwid: unique identifier for the volume ++ * @handle: device handle ++ * @id: target id ++ * @channel: target channel ++ * @volume_type: the raid level ++ * @device_info: bitfield provides detailed info about the hidden components ++ * @num_pds: number of hidden raid components ++ * @responding: used in _scsih_raid_device_mark_responding ++ */ ++struct _raid_device { ++ struct list_head list; ++ struct scsi_target *starget; ++ struct scsi_device *sdev; ++ u64 wwid; ++ u16 handle; ++ int id; ++ int channel; ++ u8 volume_type; ++ u32 device_info; ++ u8 num_pds; ++ u8 responding; ++}; ++ ++/** ++ * struct _boot_device - boot device info ++ * @is_raid: flag to indicate whether this is volume ++ * @device: holds pointer for either struct _sas_device or ++ * struct _raid_device ++ */ ++struct _boot_device { ++ u8 is_raid; ++ void *device; ++}; ++ ++/** ++ * struct _sas_port - wide/narrow sas port information ++ * @port_list: list of ports belonging to expander ++ * @handle: device handle for this port ++ * @sas_address: sas address of this port ++ * @num_phys: number of phys belonging to this port ++ * @remote_identify: attached device identification ++ * @rphy: sas transport rphy object ++ * @port: sas transport wide/narrow port object ++ * @phy_list: _sas_phy list objects belonging to this port ++ */ ++struct _sas_port { ++ struct list_head port_list; ++ u16 handle; ++ u64 sas_address; ++ u8 num_phys; ++ struct sas_identify remote_identify; ++ struct sas_rphy *rphy; ++#if defined(MPT_WIDE_PORT_API) ++ struct sas_port *port; ++#endif ++ struct list_head phy_list; ++}; ++ ++/** ++ * struct _sas_phy - phy information ++ * @port_siblings: list of phys belonging to a port ++ * @identify: phy identification ++ * @remote_identify: attached device identification ++ * @phy: sas transport phy object ++ * @phy_id: unique phy id ++ * @handle: device handle for this phy ++ * @attached_handle: device handle for attached device ++ */ ++struct _sas_phy { ++ struct list_head port_siblings; ++ struct sas_identify identify; ++ struct sas_identify remote_identify; ++ struct sas_phy *phy; ++ u8 phy_id; ++ u16 handle; ++ u16 attached_handle; ++}; ++ ++/** ++ * struct _sas_node - sas_host/expander information ++ * @list: list of expanders ++ * @parent_dev: parent device class ++ * @num_phys: number phys belonging to this sas_host/expander ++ * @sas_address: sas address of this sas_host/expander ++ * @handle: handle for this sas_host/expander ++ * @parent_handle: parent handle ++ * @enclosure_handle: handle for this a member of an enclosure ++ * @device_info: bitwise defining capabilities of this sas_host/expander ++ * @responding: used in _scsih_expander_device_mark_responding ++ * @phy: a list of phys that make up this sas_host/expander ++ * @sas_port_list: list of ports attached to this sas_host/expander ++ */ ++struct _sas_node { ++ struct list_head list; ++ struct device *parent_dev; ++ u8 num_phys; ++ u64 sas_address; ++ u16 handle; ++ u16 parent_handle; ++ u16 enclosure_handle; ++ u64 enclosure_logical_id; ++ u8 responding; ++ struct _sas_phy *phy; ++ struct list_head sas_port_list; ++}; ++ ++/** ++ * enum reset_type - reset state ++ * @FORCE_BIG_HAMMER: issue diagnostic reset ++ * @SOFT_RESET: issue message_unit_reset, if fails to to big hammer ++ */ ++enum reset_type { ++ FORCE_BIG_HAMMER, ++ SOFT_RESET, ++}; ++ ++#if defined(CHAIN_POOL) ++/** ++ * struct chain_tracker - firmware chain tracker ++ * @index: index from zero (ioc->chain) ++ * @tracker_list: list of free request (ioc->free_chain_list) ++ */ ++struct chain_tracker { ++ u16 index; ++ struct list_head tracker_list; ++}; ++#endif ++ ++/** ++ * struct request_tracker - firmware request tracker ++ * @smid: system message id ++ * @scmd: scsi request pointer ++ * @cb_idx: callback index ++ * @chain_list: list of chains associated to this IO ++ * @tracker_list: list of free request (ioc->free_list) ++ */ ++struct request_tracker { ++ u16 smid; ++ struct scsi_cmnd *scmd; ++ u8 cb_idx; ++#if defined(CHAIN_POOL) ++ struct list_head chain_list; ++#endif ++ struct list_head tracker_list; ++}; ++ ++typedef void (*MPT_ADD_SGE)(void *paddr, u32 flags_length, dma_addr_t dma_addr); ++ ++/** ++ * struct MPT2SAS_ADAPTER - per adapter struct ++ * @list: ioc_list ++ * @shost: shost object ++ * @id: unique adapter id ++ * @pci_irq: irq number ++ * @name: generic ioc string ++ * @tmp_string: tmp string used for logging ++ * @pdev: pci pdev object ++ * @chip: memory mapped register space ++ * @chip_phys: physical addrss prior to mapping ++ * @pio_chip: I/O mapped register space ++ * @logging_level: see mpt2sas_debug.h ++ * @ir_firmware: IR firmware present ++ * @bars: bitmask of BAR's that must be configured ++ * @mask_interrupts: ignore interrupt ++ * @fault_reset_work_q_name: fw fault work queue ++ * @fault_reset_work_q: "" ++ * @fault_reset_work: "" ++ * @firmware_event_name: fw event work queue ++ * @firmware_event_thread: "" ++ * @fw_events_off: flag to turn off fw event handling ++ * @fw_event_lock: ++ * @fw_event_list: list of fw events ++ * @aen_event_read_flag: event log was read ++ * @broadcast_aen_busy: broadcast aen waiting to be serviced ++ * @shost_recovery: host reset in progress ++ * @ioc_reset_in_progress_lock: ++ * @ioc_link_reset_in_progress: phy/hard reset in progress ++ * @ignore_loginfos: ignore loginfos during task managment ++ * @remove_host: flag for when driver unloads, to avoid sending dev resets ++ * @wait_for_port_enable_to_complete: ++ * @msix_enable: flag indicating msix is enabled ++ * @msix_vector_count: number msix vectors ++ * @msix_table: virt address to the msix table ++ * @msix_table_backup: backup msix table ++ * @scsi_io_cb_idx: shost generated commands ++ * @tm_cb_idx: task management commands ++ * @scsih_cb_idx: scsih internal commands ++ * @ctl_cb_idx: clt internal commands ++ * @base_cb_idx: base internal commands ++ * @config_cb_idx: base internal commands ++ * @base_cmds: ++ * @transport_cmds: ++ * @scsih_cmds: ++ * @tm_cmds: ++ * @ctl_cmds: ++ * @config_cmds: ++ * @base_add_sg_single: handler for either 32/64 bit sgl's ++ * @event_type: bits indicating which events to log ++ * @event_context: unique id for each logged event ++ * @event_log: event log pointer ++ * @event_masks: events that are masked ++ * @facts: static facts data ++ * @pfacts: static port facts data ++ * @manu_pg0: static manufacturing page 0 ++ * @manu_pg10: static manufacturing page 10 ++ * @bios_pg2: static bios page 2 ++ * @bios_pg3: static bios page 3 ++ * @ioc_pg8: static ioc page 8 ++ * @iounit_pg0: static iounit page 0 ++ * @iounit_pg1: static iounit page 1 ++ * @sas_hba: sas host object ++ * @sas_expander_list: expander object list ++ * @sas_node_lock: ++ * @sas_device_list: sas device object list ++ * @sas_device_init_list: sas device object list (used only at init time) ++ * @sas_device_lock: ++ * @io_missing_delay: time for IO completed by fw when PDR enabled ++ * @device_missing_delay: time for device missing by fw when PDR enabled ++ * @config_page_sz: config page size ++ * @config_page: reserve memory for config page payload ++ * @config_page_dma: ++ * @sge_size: sg element size for either 32/64 bit ++ * @request_depth: hba request queue depth ++ * @request_sz: per request frame size ++ * @request: pool of request frames ++ * @request_dma: ++ * @request_dma_sz: ++ * @scsi_lookup: firmware request tracker list ++ * @scsi_lookup_lock: ++ * @free_list: free list of request ++ * @pending_io_count: ++ * @reset_wq: ++ * @chain: pool of chains ++ * @chain_dma: ++ * @max_sges_in_main_message: number sg elements in main message ++ * @max_sges_in_chain_message: number sg elements per chain ++ * @chains_needed_per_io: max chains per io ++ * @chain_offset_value_for_main_message: location 1st sg in main ++ * @chain_depth: total chains allocated ++ * @chain_lookup: chain lookup table ++ * @free_chain_list: pool of free chains buffers ++ * @sense: pool of sense ++ * @sense_dma: ++ * @sense_dma_pool: ++ * @reply_depth: hba reply queue depth: ++ * @reply_sz: per reply frame size: ++ * @reply: pool of replys: ++ * @reply_dma: ++ * @reply_dma_pool: ++ * @reply_free_queue_depth: reply free depth ++ * @reply_free: pool for reply free queue (32 bit addr) ++ * @reply_free_dma: ++ * @reply_free_dma_pool: ++ * @reply_free_host_index: tail index in pool to insert free replys ++ * @reply_post_queue_depth: reply post queue depth ++ * @reply_post_free: pool for reply post (64bit descriptor) ++ * @reply_post_free_dma: ++ * @reply_post_free_dma_pool: ++ * @reply_post_host_index: head index in the pool where FW completes IO ++ */ ++struct MPT2SAS_ADAPTER { ++ struct list_head list; ++ struct Scsi_Host *shost; ++ u8 id; ++ u32 pci_irq; ++ char name[MPT_NAME_LENGTH]; ++ char tmp_string[MPT_STRING_LENGTH]; ++ struct pci_dev *pdev; ++ Mpi2SystemInterfaceRegs_t __iomem *chip; ++ unsigned long chip_phys; ++ unsigned long pio_chip; ++ int logging_level; ++ u8 ir_firmware; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) ++ int bars; ++#endif ++ u8 mask_interrupts; ++ ++ /* fw fault handler */ ++ char fault_reset_work_q_name[20]; ++ struct workqueue_struct *fault_reset_work_q; ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) ++ struct delayed_work fault_reset_work; ++#else ++ struct work_struct fault_reset_work; ++#endif ++ ++ /* fw event handler */ ++ char firmware_event_name[20]; ++ struct workqueue_struct *firmware_event_thread; ++ u8 fw_events_off; ++ spinlock_t fw_event_lock; ++ struct list_head fw_event_list; ++ ++ /* misc flags */ ++ int aen_event_read_flag; ++ u8 broadcast_aen_busy; ++ u8 shost_recovery; ++ spinlock_t ioc_reset_in_progress_lock; ++ u8 ioc_link_reset_in_progress; ++ u8 ignore_loginfos; ++ u8 remove_host; ++ u8 wait_for_port_enable_to_complete; ++ ++ u8 msix_enable; ++ u16 msix_vector_count; ++ u32 *msix_table; ++ u32 *msix_table_backup; ++ ++ /* internal commands, callback index */ ++ u8 scsi_io_cb_idx; ++ u8 tm_cb_idx; ++ u8 transport_cb_idx; ++ u8 scsih_cb_idx; ++ u8 ctl_cb_idx; ++ u8 base_cb_idx; ++ u8 config_cb_idx; ++ struct _internal_cmd base_cmds; ++ struct _internal_cmd transport_cmds; ++ struct _internal_cmd scsih_cmds; ++ struct _internal_cmd tm_cmds; ++ struct _internal_cmd ctl_cmds; ++ struct _internal_cmd config_cmds; ++ ++ MPT_ADD_SGE base_add_sg_single; ++ ++ /* event log */ ++ u32 event_type[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; ++ u32 event_context; ++ void *event_log; ++ u32 event_masks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; ++ ++ /* static config pages */ ++ Mpi2IOCFactsReply_t facts; ++ Mpi2PortFactsReply_t *pfacts; ++ Mpi2ManufacturingPage0_t manu_pg0; ++ Mpi2ManufacturingPage10_t manu_pg10; ++ Mpi2BiosPage2_t bios_pg2; ++ Mpi2BiosPage3_t bios_pg3; ++ Mpi2IOCPage8_t ioc_pg8; ++ Mpi2IOUnitPage0_t iounit_pg0; ++ Mpi2IOUnitPage1_t iounit_pg1; ++ ++ struct _boot_device req_boot_device; ++ struct _boot_device req_alt_boot_device; ++ struct _boot_device current_boot_device; ++ ++ /* sas hba, expander, and device list */ ++ struct _sas_node sas_hba; ++ struct list_head sas_expander_list; ++ spinlock_t sas_node_lock; ++ struct list_head sas_device_list; ++ struct list_head sas_device_init_list; ++ spinlock_t sas_device_lock; ++ struct list_head raid_device_list; ++ spinlock_t raid_device_lock; ++ u8 io_missing_delay; ++ u16 device_missing_delay; ++ int sas_id; ++ ++ /* config page */ ++ u16 config_page_sz; ++ void *config_page; ++ dma_addr_t config_page_dma; ++ ++ /* request */ ++ u16 sge_size; ++ u16 request_depth; ++ u16 request_sz; ++ u8 *request; ++ dma_addr_t request_dma; ++ u32 request_dma_sz; ++ struct request_tracker *scsi_lookup; ++ spinlock_t scsi_lookup_lock; ++ struct list_head free_list; ++ int pending_io_count; ++ wait_queue_head_t reset_wq; ++ ++ /* chain */ ++ u8 *chain; ++ dma_addr_t chain_dma; ++ u16 max_sges_in_main_message; ++ u16 max_sges_in_chain_message; ++ u16 chains_needed_per_io; ++ u16 chain_offset_value_for_main_message; ++ u16 chain_depth; ++#if defined(CHAIN_POOL) ++ struct chain_tracker *chain_lookup; ++ struct list_head free_chain_list; ++#endif ++ ++ /* sense */ ++ u8 *sense; ++ dma_addr_t sense_dma; ++ struct dma_pool *sense_dma_pool; ++ ++ /* reply */ ++ u16 reply_sz; ++ u8 *reply; ++ dma_addr_t reply_dma; ++ struct dma_pool *reply_dma_pool; ++ ++ /* reply free queue */ ++ u16 reply_free_queue_depth; ++ u32 *reply_free; ++ dma_addr_t reply_free_dma; ++ struct dma_pool *reply_free_dma_pool; ++ u32 reply_free_host_index; ++ ++ /* reply post queue */ ++ u16 reply_post_queue_depth; ++ Mpi2ReplyDescriptorsUnion_t *reply_post_free; ++ dma_addr_t reply_post_free_dma; ++ struct dma_pool *reply_post_free_dma_pool; ++ u32 reply_post_host_index; ++ ++ /* diag buffer support */ ++ u8 *diag_buffer[MPI2_DIAG_BUF_TYPE_COUNT]; ++ u32 diag_buffer_sz[MPI2_DIAG_BUF_TYPE_COUNT]; ++ dma_addr_t diag_buffer_dma[MPI2_DIAG_BUF_TYPE_COUNT]; ++ u8 diag_buffer_status[MPI2_DIAG_BUF_TYPE_COUNT]; ++ u32 unique_id[MPI2_DIAG_BUF_TYPE_COUNT]; ++ u32 product_specific[MPI2_DIAG_BUF_TYPE_COUNT][23]; ++ u32 diagnostic_flags[MPI2_DIAG_BUF_TYPE_COUNT]; ++#if defined(TARGET_MODE) ++ char stm_name[MPT_NAME_LENGTH]; ++ u8 stm_io_cb_idx; /* normal io */ ++ u8 stm_tm_cb_idx; /* task managment */ ++ u8 stm_tm_imm_cb_idx; ++ struct _internal_cmd stm_tm_cmds; ++ void *priv; ++#endif ++}; ++ ++typedef void (*MPT_CALLBACK)(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, ++ u32 reply); ++ ++/* base shared API */ ++extern struct list_head mpt2sas_ioc_list; ++void mpt2sas_base_start_watchdog(struct MPT2SAS_ADAPTER *ioc); ++void mpt2sas_base_stop_watchdog(struct MPT2SAS_ADAPTER *ioc); ++void mpt2sas_base_save_msix_table(struct MPT2SAS_ADAPTER *ioc); ++void mpt2sas_base_restore_msix_table(struct MPT2SAS_ADAPTER *ioc); ++ ++int mpt2sas_base_attach(struct MPT2SAS_ADAPTER *ioc); ++void mpt2sas_base_detach(struct MPT2SAS_ADAPTER *ioc); ++int mpt2sas_base_map_resources(struct MPT2SAS_ADAPTER *ioc); ++void mpt2sas_base_free_resources(struct MPT2SAS_ADAPTER *ioc); ++int mpt2sas_base_hard_reset_handler(struct MPT2SAS_ADAPTER *ioc, int sleep_flag, ++ enum reset_type type); ++ ++void *mpt2sas_base_get_msg_frame(struct MPT2SAS_ADAPTER *ioc, u16 smid); ++void *mpt2sas_base_get_sense_buffer(struct MPT2SAS_ADAPTER *ioc, u16 smid); ++void mpt2sas_base_build_zero_len_sge(struct MPT2SAS_ADAPTER *ioc, void *paddr); ++dma_addr_t mpt2sas_base_get_msg_frame_dma(struct MPT2SAS_ADAPTER *ioc, ++ u16 smid); ++dma_addr_t mpt2sas_base_get_sense_buffer_dma(struct MPT2SAS_ADAPTER *ioc, ++ u16 smid); ++ ++u16 mpt2sas_base_get_smid(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx); ++void mpt2sas_base_free_smid(struct MPT2SAS_ADAPTER *ioc, u16 smid); ++void mpt2sas_base_put_smid_scsi_io(struct MPT2SAS_ADAPTER *ioc, u16 smid, ++ u8 vf_id, u16 handle); ++void mpt2sas_base_put_smid_hi_priority(struct MPT2SAS_ADAPTER *ioc, u16 smid, ++ u8 vf_id); ++void mpt2sas_base_put_smid_target_assist(struct MPT2SAS_ADAPTER *ioc, u16 smid, ++ u8 vf_id, u16 io_index); ++void mpt2sas_base_put_smid_default(struct MPT2SAS_ADAPTER *ioc, u16 smid, ++ u8 vf_id); ++void mpt2sas_base_initialize_callback_handler(void); ++u8 mpt2sas_base_register_callback_handler(MPT_CALLBACK cb_func); ++void mpt2sas_base_release_callback_handler(u8 cb_idx); ++ ++void mpt2sas_base_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, ++ u32 reply); ++void *mpt2sas_base_get_reply_virt_addr(struct MPT2SAS_ADAPTER *ioc, ++ u32 phys_addr); ++ ++u32 mpt2sas_base_get_iocstate(struct MPT2SAS_ADAPTER *ioc, int cooked); ++ ++void mpt2sas_base_fault_info(struct MPT2SAS_ADAPTER *ioc , u16 fault_code); ++int mpt2sas_base_sas_iounit_control(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2SasIoUnitControlReply_t *mpi_reply, Mpi2SasIoUnitControlRequest_t ++ *mpi_request); ++int mpt2sas_base_scsi_enclosure_processor(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request); ++ ++void mpt2sas_base_validate_event_type(struct MPT2SAS_ADAPTER *ioc, ++ u32 *event_type); ++ ++/* scsih shared API */ ++void mpt2sas_scsih_event_callback(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ u32 reply); ++void mpt2sas_scsih_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase); ++#ifdef MPT2SAS_MULTIPATH ++void mpt2sas_scsih_check_tm_for_multipath(struct MPT2SAS_ADAPTER *ioc, ++ u16 handle, u8 task_type); ++#endif ++void mpt2sas_scsih_issue_tm(struct MPT2SAS_ADAPTER *ioc, u16 handle, uint lun, ++ u8 type, u16 smid_task, ulong timeout); ++void mpt2sas_scsih_set_tm_flag(struct MPT2SAS_ADAPTER *ioc, u16 handle); ++void mpt2sas_scsih_clear_tm_flag(struct MPT2SAS_ADAPTER *ioc, u16 handle); ++ ++struct _sas_node *mpt2sas_scsih_expander_find_by_handle( ++ struct MPT2SAS_ADAPTER *ioc, u16 handle); ++struct _sas_node *mpt2sas_scsih_expander_find_by_sas_address( ++ struct MPT2SAS_ADAPTER *ioc, u64 sas_address); ++struct _sas_device *mpt2sas_scsih_sas_device_find_by_sas_address( ++ struct MPT2SAS_ADAPTER *ioc, u64 sas_address); ++ ++/* config shared API */ ++void mpt2sas_config_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, ++ u32 reply); ++int mpt2sas_config_get_number_hba_phys(struct MPT2SAS_ADAPTER *ioc, ++ u8 *num_phys); ++int mpt2sas_config_get_manufacturing_pg0(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2ManufacturingPage0_t *config_page); ++int mpt2sas_config_get_manufacturing_pg10(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2ManufacturingPage10_t *config_page); ++int mpt2sas_config_get_bios_pg2(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2BiosPage2_t *config_page); ++int mpt2sas_config_get_bios_pg3(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2BiosPage3_t *config_page); ++int mpt2sas_config_get_iounit_pg0(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2IOUnitPage0_t *config_page); ++int mpt2sas_config_get_sas_device_pg0(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2SasDevicePage0_t *config_page, u32 form, ++ u32 handle); ++int mpt2sas_config_get_sas_device_pg1(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2SasDevicePage1_t *config_page, u32 form, ++ u32 handle); ++int mpt2sas_config_get_sas_iounit_pg0(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2SasIOUnitPage0_t *config_page, u16 sz); ++int mpt2sas_config_get_iounit_pg1(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2IOUnitPage1_t *config_page); ++int mpt2sas_config_set_iounit_pg1(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2IOUnitPage1_t *config_page); ++int mpt2sas_config_get_sas_iounit_pg1(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2SasIOUnitPage1_t *config_page, u16 sz); ++int mpt2sas_config_get_ioc_pg8(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2IOCPage8_t *config_page); ++int mpt2sas_config_get_expander_pg0(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2ExpanderPage0_t *config_page, u32 form, ++ u32 handle); ++int mpt2sas_config_get_expander_pg1(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2ExpanderPage1_t *config_page, ++ u32 phy_number, u16 handle); ++int mpt2sas_config_get_enclosure_pg0(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2SasEnclosurePage0_t *config_page, ++ u32 form, u32 handle); ++int mpt2sas_config_get_phy_pg0(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2SasPhyPage0_t *config_page, u32 phy_number); ++int mpt2sas_config_get_phy_pg1(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2SasPhyPage1_t *config_page, u32 phy_number); ++int mpt2sas_config_get_raid_volume_pg1(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form, ++ u32 handle); ++int mpt2sas_config_get_number_pds(struct MPT2SAS_ADAPTER *ioc, u16 handle, ++ u8 *num_pds); ++int mpt2sas_config_get_raid_volume_pg0(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 form, ++ u32 handle, u16 sz); ++int mpt2sas_config_get_phys_disk_pg0(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2RaidPhysDiskPage0_t *config_page, ++ u32 form, u32 form_specific); ++int mpt2sas_config_get_volume_handle(struct MPT2SAS_ADAPTER *ioc, u16 pd_handle, ++ u16 *volume_handle); ++int mpt2sas_config_get_volume_wwid(struct MPT2SAS_ADAPTER *ioc, ++ u16 volume_handle, u64 *wwid); ++ ++/* ctl shared API */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++extern struct device_attribute *mpt2sas_host_attrs[]; ++#else ++extern struct class_device_attribute *mpt2sas_host_attrs[]; ++#endif ++extern struct device_attribute *mpt2sas_dev_attrs[]; ++void mpt2sas_ctl_init(void); ++void mpt2sas_ctl_exit(void); ++void mpt2sas_ctl_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, ++ u32 reply); ++void mpt2sas_ctl_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase); ++void mpt2sas_ctl_event_callback(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ u32 reply); ++void mpt2sas_ctl_add_to_event_log(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventNotificationReply_t *mpi_reply); ++ ++/* transport shared API */ ++void mpt2sas_transport_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, ++ u32 reply); ++struct _sas_port *mpt2sas_transport_port_add(struct MPT2SAS_ADAPTER *ioc, ++ u16 handle, u16 parent_handle); ++void mpt2sas_transport_port_remove(struct MPT2SAS_ADAPTER *ioc, u64 sas_address, ++ u16 parent_handle); ++int mpt2sas_transport_add_host_phy(struct MPT2SAS_ADAPTER *ioc, struct _sas_phy ++ *mpt2sas_phy, Mpi2SasPhyPage0_t phy_pg0, struct device *parent_dev); ++int mpt2sas_transport_add_expander_phy(struct MPT2SAS_ADAPTER *ioc, ++ struct _sas_phy *mpt2sas_phy, Mpi2ExpanderPage1_t expander_pg1, ++ struct device *parent_dev); ++void mpt2sas_transport_update_links(struct MPT2SAS_ADAPTER *ioc, ++ u16 handle, u16 attached_handle, u8 phy_number, u8 link_rate); ++extern struct sas_function_template mpt2sas_transport_functions; ++extern struct scsi_transport_template *mpt2sas_transport_template; ++ ++#if defined(TARGET_MODE) ++extern void mpt2sas_stmapp_target_command(struct MPT2SAS_ADAPTER *ioc, ++ u16 io_index, u16 initiator_handle, u8 VP_ID, u8 VF_ID, u8 phy_number); ++extern void mpt2sas_stm_target_assist_success_reply(struct MPT2SAS_ADAPTER *ioc, ++ u16 smid, u8 VF_ID, u16 io_index, u8 sequence_number); ++extern void mpt2sas_stm_init(void); ++extern void mpt2sas_stm_exit(void); ++extern void mpt2sas_stm_adapter_install(struct MPT2SAS_ADAPTER *ioc); ++extern void mpt2sas_stm_adapter_dispose(struct MPT2SAS_ADAPTER *ioc); ++extern void mpt2sas_stm_zero_smid_handler(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ u32 reply); ++extern void mpt2sas_stm_reset_handler(struct MPT2SAS_ADAPTER *ioc, ++ int reset_phase); ++#endif ++ ++#endif /* MPT2SAS_BASE_H_INCLUDED */ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpt2sas_compatibility.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpt2sas_compatibility.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,142 @@ ++/* ++ * Compatiblity Header for compilation working across multiple kernels ++ * ++ * This code is based on drivers/scsi/mpt2sas/mpt2_base.c ++ * Copyright (C) 2007-2008 LSI Corporation ++ * (mailto:DL-MPTFusionLinux@lsi.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * NO WARRANTY ++ * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR ++ * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT ++ * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is ++ * solely responsible for determining the appropriateness of using and ++ * distributing the Program and assumes all risks associated with its ++ * exercise of rights under this Agreement, including but not limited to ++ * the risks and costs of program errors, damage to or loss of data, ++ * programs or equipment, and unavailability or interruption of operations. ++ ++ * DISCLAIMER OF LIABILITY ++ * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR ++ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED ++ * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ++ ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, ++ * USA. ++ */ ++ ++#ifndef FUSION_LINUX_COMPAT_H ++#define FUSION_LINUX_COMPAT_H ++ ++#include ++ ++#ifndef ULLONG_MAX ++#define ULLONG_MAX (~0ULL) ++#endif ++ ++#ifndef USHORT_MAX ++#define USHORT_MAX ((u16)(~0U)) ++#endif ++ ++/* ++ * TODO Need to change 'shost_private' back to 'shost_priv' when suppying patchs ++ * upstream. Since Red Hat decided to backport this to rhel5.2 (2.6.18-92.el5) ++ * from the 2.6.23 kernel, it will make it difficult for us to add the proper ++ * glue in our driver. ++ */ ++static inline void *shost_private(struct Scsi_Host *shost) ++{ ++ return (void *)shost->hostdata; ++} ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) ++static inline sector_t scsi_get_lba(struct scsi_cmnd *scmd) ++{ ++ return scmd->request->sector; ++} ++#endif ++ ++/** ++ * mpt_scsi_build_sense_buffer - build sense data in a buffer ++ * @desc: Sense format (non zero == descriptor format, ++ * 0 == fixed format) ++ * @buf: Where to build sense data ++ * @key: Sense key ++ * @asc: Additional sense code ++ * @ascq: Additional sense code qualifier ++ * ++ * Note: scsi_build_sense_buffer was added in the 2.6.26 kernel ++ * It was backported in RHEL5.3 2.6.18-128.el5 ++ **/ ++static inline void mpt_scsi_build_sense_buffer(int desc, u8 *buf, u8 key, ++ u8 asc, u8 ascq) ++{ ++ if (desc) { ++ buf[0] = 0x72; /* descriptor, current */ ++ buf[1] = key; ++ buf[2] = asc; ++ buf[3] = ascq; ++ buf[7] = 0; ++ } else { ++ buf[0] = 0x70; /* fixed, current */ ++ buf[2] = key; ++ buf[7] = 0xa; ++ buf[12] = asc; ++ buf[13] = ascq; ++ } ++} ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++/** ++ * mpt_scsilun_to_int: convert a scsi_lun to an int ++ * @scsilun: struct scsi_lun to be converted. ++ * ++ * Description: ++ * Convert @scsilun from a struct scsi_lun to a four byte host byte-ordered ++ * integer, and return the result. The caller must check for ++ * truncation before using this function. ++ * ++ * Notes: ++ * The struct scsi_lun is assumed to be four levels, with each level ++ * effectively containing a SCSI byte-ordered (big endian) short; the ++ * addressing bits of each level are ignored (the highest two bits). ++ * For a description of the LUN format, post SCSI-3 see the SCSI ++ * Architecture Model, for SCSI-3 see the SCSI Controller Commands. ++ * ++ * Given a struct scsi_lun of: 0a 04 0b 03 00 00 00 00, this function ++ * returns the integer: 0x0b030a04 ++ **/ ++static inline int mpt_scsilun_to_int(struct scsi_lun *scsilun) ++{ ++ int i; ++ unsigned int lun; ++ ++ lun = 0; ++ for (i = 0; i < sizeof(lun); i += 2) ++ lun = lun | (((scsilun->scsi_lun[i] << 8) | ++ scsilun->scsi_lun[i + 1]) << (i * 8)); ++ return lun; ++} ++#else ++static inline int mpt_scsilun_to_int(struct scsi_lun *scsilun) ++{ ++ return scsilun_to_int(scsilun); ++} ++#endif ++#endif /* FUSION_LINUX_COMPAT_H */ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpt2sas_config.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpt2sas_config.c Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,1382 @@ ++/* ++ * This module provides common API for accessing firmware configuration pages ++ * ++ * This code is based on drivers/scsi/mpt2sas/mpt2_base.c ++ * Copyright (C) 2007-2008 LSI Corporation ++ * (mailto:DL-MPTFusionLinux@lsi.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * NO WARRANTY ++ * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR ++ * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT ++ * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is ++ * solely responsible for determining the appropriateness of using and ++ * distributing the Program and assumes all risks associated with its ++ * exercise of rights under this Agreement, including but not limited to ++ * the risks and costs of program errors, damage to or loss of data, ++ * programs or equipment, and unavailability or interruption of operations. ++ ++ * DISCLAIMER OF LIABILITY ++ * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR ++ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED ++ * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ++ ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, ++ * USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mpt2sas_base.h" ++ ++/* local definitions */ ++ ++/* Timeout for config page request (in seconds) */ ++#define MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT 15 ++ ++/* Common sgl flags for READING a config page. */ ++#define MPT2_CONFIG_COMMON_SGLFLAGS ((MPI2_SGE_FLAGS_SIMPLE_ELEMENT | \ ++ MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER \ ++ | MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT) ++ ++/* Common sgl flags for WRITING a config page. */ ++#define MPT2_CONFIG_COMMON_WRITE_SGLFLAGS ((MPI2_SGE_FLAGS_SIMPLE_ELEMENT | \ ++ MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER \ ++ | MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC) \ ++ << MPI2_SGE_FLAGS_SHIFT) ++ ++/** ++ * struct config_request - obtain dma memory via routine ++ * @sz: size ++ * @page: virt pointer ++ * @page_dma: phys pointer ++ * ++ */ ++struct config_request{ ++ u16 sz; ++ void *page; ++ dma_addr_t page_dma; ++}; ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++/** ++ * _config_display_some_debug - debug routine ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @calling_function_name: string pass from calling function ++ * @mpi_reply: reply message frame ++ * Context: none. ++ * ++ * Function for displaying debug info helpfull when debugging issues ++ * in this module. ++ */ ++static void ++_config_display_some_debug(struct MPT2SAS_ADAPTER *ioc, u16 smid, ++ char *calling_function_name, MPI2DefaultReply_t *mpi_reply) ++{ ++ Mpi2ConfigRequest_t *mpi_request; ++ char *desc = NULL; ++ ++ if (!(ioc->logging_level & MPT_DEBUG_CONFIG)) ++ return; ++ ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ switch (mpi_request->Header.PageType & MPI2_CONFIG_PAGETYPE_MASK) { ++ case MPI2_CONFIG_PAGETYPE_IO_UNIT: ++ desc = "io_unit"; ++ break; ++ case MPI2_CONFIG_PAGETYPE_IOC: ++ desc = "ioc"; ++ break; ++ case MPI2_CONFIG_PAGETYPE_BIOS: ++ desc = "bios"; ++ break; ++ case MPI2_CONFIG_PAGETYPE_RAID_VOLUME: ++ desc = "raid_volume"; ++ break; ++ case MPI2_CONFIG_PAGETYPE_MANUFACTURING: ++ desc = "manufaucturing"; ++ break; ++ case MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK: ++ desc = "physdisk"; ++ break; ++ case MPI2_CONFIG_PAGETYPE_EXTENDED: ++ switch (mpi_request->ExtPageType) { ++ case MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT: ++ desc = "sas_io_unit"; ++ break; ++ case MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER: ++ desc = "sas_expander"; ++ break; ++ case MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE: ++ desc = "sas_device"; ++ break; ++ case MPI2_CONFIG_EXTPAGETYPE_SAS_PHY: ++ desc = "sas_phy"; ++ break; ++ case MPI2_CONFIG_EXTPAGETYPE_LOG: ++ desc = "log"; ++ break; ++ case MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE: ++ desc = "enclosure"; ++ break; ++ case MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG: ++ desc = "raid_config"; ++ break; ++ case MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING: ++ desc = "driver_mappping"; ++ break; ++ } ++ break; ++ } ++ ++ if (!desc) ++ return; ++ ++ printk(MPT2SAS_DEBUG_FMT "%s: %s(%d), action(%d), form(0x%08x), " ++ "smid(%d)\n", ioc->name, calling_function_name, desc, ++ mpi_request->Header.PageNumber, mpi_request->Action, ++ le32_to_cpu(mpi_request->PageAddress), smid); ++ ++ if (!mpi_reply) ++ return; ++ ++ if (mpi_reply->IOCStatus || mpi_reply->IOCLogInfo) ++ printk(MPT2SAS_DEBUG_FMT ++ "\tiocstatus(0x%04x), loginfo(0x%08x)\n", ++ ioc->name, le16_to_cpu(mpi_reply->IOCStatus), ++ le32_to_cpu(mpi_reply->IOCLogInfo)); ++} ++#endif ++ ++/** ++ * _config_alloc_config_dma_memory - obtain physical memory ++ * @ioc: per adapter object ++ * @mem: struct config_request ++ * ++ * A wrapper for obtaining dma-able memory for config page request. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_config_alloc_config_dma_memory(struct MPT2SAS_ADAPTER *ioc, ++ struct config_request *mem) ++{ ++ int r = 0; ++ ++ if (mem->sz > ioc->config_page_sz) { ++ mem->page = dma_alloc_coherent(&ioc->pdev->dev, mem->sz, ++ &mem->page_dma, GFP_KERNEL); ++ if (!mem->page) { ++ printk(MPT2SAS_ERR_FMT "%s: dma_alloc_coherent" ++ " failed asking for (%d) bytes!!\n", ++ ioc->name, __func__, mem->sz); ++ r = -ENOMEM; ++ } ++ } else { /* use tmp buffer if less than 512 bytes */ ++ mem->page = ioc->config_page; ++ mem->page_dma = ioc->config_page_dma; ++ } ++ return r; ++} ++ ++/** ++ * _config_free_config_dma_memory - wrapper to free the memory ++ * @ioc: per adapter object ++ * @mem: struct config_request ++ * ++ * A wrapper to free dma-able memory when using _config_alloc_config_dma_memory. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static void ++_config_free_config_dma_memory(struct MPT2SAS_ADAPTER *ioc, ++ struct config_request *mem) ++{ ++ if (mem->sz > ioc->config_page_sz) ++ dma_free_coherent(&ioc->pdev->dev, mem->sz, mem->page, ++ mem->page_dma); ++} ++ ++/** ++ * mpt2sas_config_done - config page completion routine ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @VF_ID: virtual function id ++ * @reply: reply message frame(lower 32bit addr) ++ * Context: none. ++ * ++ * The callback handler when using _config_request. ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_config_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, u32 reply) ++{ ++ MPI2DefaultReply_t *mpi_reply; ++ ++ if (ioc->config_cmds.status == MPT2_CMD_NOT_USED) ++ return; ++ if (ioc->config_cmds.smid != smid) ++ return; ++ ioc->config_cmds.status |= MPT2_CMD_COMPLETE; ++ mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply); ++ if (mpi_reply) { ++ ioc->config_cmds.status |= MPT2_CMD_REPLY_VALID; ++ memcpy(ioc->config_cmds.reply, mpi_reply, ++ mpi_reply->MsgLength*4); ++ } ++ ioc->config_cmds.status &= ~MPT2_CMD_PENDING; ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ _config_display_some_debug(ioc, smid, "config_done", mpi_reply); ++#endif ++ ioc->config_cmds.smid = USHORT_MAX; ++ complete(&ioc->config_cmds.done); ++} ++ ++/** ++ * _config_request - main routine for sending config page requests ++ * @ioc: per adapter object ++ * @mpi_request: request message frame ++ * @mpi_reply: reply mf payload returned from firmware ++ * @timeout: timeout in seconds ++ * @config_page: contents of the config page ++ * @config_page_sz: size of config page ++ * Context: sleep ++ * ++ * A generic API for config page requests to firmware. ++ * ++ * The ioc->config_cmds.status flag should be MPT2_CMD_NOT_USED before calling ++ * this API. ++ * ++ * The callback index is set inside `ioc->config_cb_idx. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_config_request(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigRequest_t ++ *mpi_request, Mpi2ConfigReply_t *mpi_reply, int timeout, ++ void *config_page, u16 config_page_sz) ++{ ++ u16 smid; ++ u32 ioc_state; ++ unsigned long timeleft; ++ Mpi2ConfigRequest_t *config_request; ++ int r; ++ u8 retry_count, issue_host_reset = 0; ++ u16 wait_state_count; ++ struct config_request mem; ++ ++ mutex_lock(&ioc->config_cmds.mutex); ++ if (ioc->config_cmds.status != MPT2_CMD_NOT_USED) { ++ printk(MPT2SAS_ERR_FMT "%s: config_cmd in use\n", ++ ioc->name, __func__); ++ mutex_unlock(&ioc->config_cmds.mutex); ++ return -EAGAIN; ++ } ++ ++ retry_count = 0; ++ memset(&mem, 0, sizeof(struct config_request)); ++ ++ if (config_page) { ++ mpi_request->Header.PageVersion = mpi_reply->Header.PageVersion; ++ mpi_request->Header.PageNumber = mpi_reply->Header.PageNumber; ++ mpi_request->Header.PageType = mpi_reply->Header.PageType; ++ mpi_request->Header.PageLength = mpi_reply->Header.PageLength; ++ mpi_request->ExtPageLength = mpi_reply->ExtPageLength; ++ mpi_request->ExtPageType = mpi_reply->ExtPageType; ++ if (mpi_request->Header.PageLength) ++ mem.sz = mpi_request->Header.PageLength * 4; ++ else ++ mem.sz = le16_to_cpu(mpi_reply->ExtPageLength) * 4; ++ r = _config_alloc_config_dma_memory(ioc, &mem); ++ if (r != 0) ++ goto out; ++ if (mpi_request->Action == ++ MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT) { ++ ioc->base_add_sg_single(&mpi_request->PageBufferSGE, ++ MPT2_CONFIG_COMMON_WRITE_SGLFLAGS | mem.sz, ++ mem.page_dma); ++ memcpy(mem.page, config_page, min_t(u16, mem.sz, ++ config_page_sz)); ++ } else { ++ memset(config_page, 0, config_page_sz); ++ ioc->base_add_sg_single(&mpi_request->PageBufferSGE, ++ MPT2_CONFIG_COMMON_SGLFLAGS | mem.sz, mem.page_dma); ++ } ++ } ++ ++ retry_config: ++ if (retry_count) { ++ if (retry_count > 2) { /* attempt only 2 retries */ ++ r = -EFAULT; ++ goto free_mem; ++ } ++ printk(MPT2SAS_INFO_FMT "%s: attempting retry (%d)\n", ++ ioc->name, __func__, retry_count); ++ } ++ wait_state_count = 0; ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { ++ if (wait_state_count++ == MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT) { ++ printk(MPT2SAS_ERR_FMT ++ "%s: failed due to ioc not operational\n", ++ ioc->name, __func__); ++ ioc->config_cmds.status = MPT2_CMD_NOT_USED; ++ r = -EFAULT; ++ goto free_mem; ++ } ++ ssleep(1); ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ printk(MPT2SAS_INFO_FMT "%s: waiting for " ++ "operational state(count=%d)\n", ioc->name, ++ __func__, wait_state_count); ++ } ++ if (wait_state_count) ++ printk(MPT2SAS_INFO_FMT "%s: ioc is operational\n", ++ ioc->name, __func__); ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->config_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ ioc->config_cmds.status = MPT2_CMD_NOT_USED; ++ r = -EAGAIN; ++ goto free_mem; ++ } ++ ++ r = 0; ++ memset(mpi_reply, 0, sizeof(Mpi2ConfigReply_t)); ++ ioc->config_cmds.status = MPT2_CMD_PENDING; ++ config_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ioc->config_cmds.smid = smid; ++ memcpy(config_request, mpi_request, sizeof(Mpi2ConfigRequest_t)); ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ _config_display_some_debug(ioc, smid, "config_request", NULL); ++#endif ++ init_completion(&ioc->config_cmds.done); ++ mpt2sas_base_put_smid_default(ioc, smid, config_request->VF_ID); ++ timeleft = wait_for_completion_timeout(&ioc->config_cmds.done, ++ timeout*HZ); ++ if (!(ioc->config_cmds.status & MPT2_CMD_COMPLETE)) { ++ printk(MPT2SAS_ERR_FMT "%s: timeout\n", ++ ioc->name, __func__); ++ _debug_dump_mf(mpi_request, ++ sizeof(Mpi2ConfigRequest_t)/4); ++ retry_count++; ++ if (ioc->config_cmds.smid == smid) ++ mpt2sas_base_free_smid(ioc, smid); ++ if ((ioc->shost_recovery) || (ioc->config_cmds.status & ++ MPT2_CMD_RESET)) ++ goto retry_config; ++ issue_host_reset = 1; ++ r = -EFAULT; ++ goto free_mem; ++ } ++ ++ if (ioc->config_cmds.status & MPT2_CMD_REPLY_VALID) ++ memcpy(mpi_reply, ioc->config_cmds.reply, ++ sizeof(Mpi2ConfigReply_t)); ++ if (retry_count) ++ printk(MPT2SAS_INFO_FMT "%s: retry (%d) completed!!\n", ++ ioc->name, __func__, retry_count); ++ if (config_page && mpi_request->Action == ++ MPI2_CONFIG_ACTION_PAGE_READ_CURRENT) ++ memcpy(config_page, mem.page, min_t(u16, mem.sz, ++ config_page_sz)); ++ free_mem: ++ if (config_page) ++ _config_free_config_dma_memory(ioc, &mem); ++ out: ++ ioc->config_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->config_cmds.mutex); ++ ++ if (issue_host_reset) ++ mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, ++ FORCE_BIG_HAMMER); ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_manufacturing_pg0 - obtain manufacturing page 0 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_manufacturing_pg0(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2ManufacturingPage0_t *config_page) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_MANUFACTURING; ++ mpi_request.Header.PageNumber = 0; ++ mpi_request.Header.PageVersion = MPI2_MANUFACTURING0_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_manufacturing_pg10 - obtain manufacturing page 10 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_manufacturing_pg10(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2ManufacturingPage10_t *config_page) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_MANUFACTURING; ++ mpi_request.Header.PageNumber = 10; ++ mpi_request.Header.PageVersion = MPI2_MANUFACTURING0_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_bios_pg2 - obtain bios page 2 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_bios_pg2(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2BiosPage2_t *config_page) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_BIOS; ++ mpi_request.Header.PageNumber = 2; ++ mpi_request.Header.PageVersion = MPI2_BIOSPAGE2_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_bios_pg3 - obtain bios page 3 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_bios_pg3(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2BiosPage3_t *config_page) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_BIOS; ++ mpi_request.Header.PageNumber = 3; ++ mpi_request.Header.PageVersion = MPI2_BIOSPAGE3_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_iounit_pg0 - obtain iounit page 0 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_iounit_pg0(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2IOUnitPage0_t *config_page) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_IO_UNIT; ++ mpi_request.Header.PageNumber = 0; ++ mpi_request.Header.PageVersion = MPI2_IOUNITPAGE0_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_iounit_pg1 - obtain iounit page 1 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_iounit_pg1(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2IOUnitPage1_t *config_page) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_IO_UNIT; ++ mpi_request.Header.PageNumber = 1; ++ mpi_request.Header.PageVersion = MPI2_IOUNITPAGE1_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_set_iounit_pg1 - set iounit page 1 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_set_iounit_pg1(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2IOUnitPage1_t *config_page) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_IO_UNIT; ++ mpi_request.Header.PageNumber = 1; ++ mpi_request.Header.PageVersion = MPI2_IOUNITPAGE1_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_ioc_pg8 - obtain ioc page 8 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_ioc_pg8(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2IOCPage8_t *config_page) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_IOC; ++ mpi_request.Header.PageNumber = 8; ++ mpi_request.Header.PageVersion = MPI2_IOCPAGE8_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_sas_device_pg0 - obtain sas device page 0 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * @form: GET_NEXT_HANDLE or HANDLE ++ * @handle: device handle ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_sas_device_pg0(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2SasDevicePage0_t *config_page, u32 form, u32 handle) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; ++ mpi_request.ExtPageType = MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE; ++ mpi_request.Header.PageVersion = MPI2_SASDEVICE0_PAGEVERSION; ++ mpi_request.Header.PageNumber = 0; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.PageAddress = cpu_to_le32(form | handle); ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_sas_device_pg1 - obtain sas device page 1 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * @form: GET_NEXT_HANDLE or HANDLE ++ * @handle: device handle ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_sas_device_pg1(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2SasDevicePage1_t *config_page, u32 form, u32 handle) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; ++ mpi_request.ExtPageType = MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE; ++ mpi_request.Header.PageVersion = MPI2_SASDEVICE1_PAGEVERSION; ++ mpi_request.Header.PageNumber = 1; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.PageAddress = cpu_to_le32(form | handle); ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_number_hba_phys - obtain number of phys on the host ++ * @ioc: per adapter object ++ * @num_phys: pointer returned with the number of phys ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_number_hba_phys(struct MPT2SAS_ADAPTER *ioc, u8 *num_phys) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ u16 ioc_status; ++ Mpi2ConfigReply_t mpi_reply; ++ Mpi2SasIOUnitPage0_t config_page; ++ ++ *num_phys = 0; ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; ++ mpi_request.ExtPageType = MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT; ++ mpi_request.Header.PageNumber = 0; ++ mpi_request.Header.PageVersion = MPI2_SASIOUNITPAGE0_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, &mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, &mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, &config_page, ++ sizeof(Mpi2SasIOUnitPage0_t)); ++ if (!r) { ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status == MPI2_IOCSTATUS_SUCCESS) ++ *num_phys = config_page.NumPhys; ++ } ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_sas_iounit_pg0 - obtain sas iounit page 0 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * @sz: size of buffer passed in config_page ++ * Context: sleep. ++ * ++ * Calling function should call config_get_number_hba_phys prior to ++ * this function, so enough memory is allocated for config_page. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_sas_iounit_pg0(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2SasIOUnitPage0_t *config_page, u16 sz) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; ++ mpi_request.ExtPageType = MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT; ++ mpi_request.Header.PageNumber = 0; ++ mpi_request.Header.PageVersion = MPI2_SASIOUNITPAGE0_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, sz); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_sas_iounit_pg1 - obtain sas iounit page 0 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * @sz: size of buffer passed in config_page ++ * Context: sleep. ++ * ++ * Calling function should call config_get_number_hba_phys prior to ++ * this function, so enough memory is allocated for config_page. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_sas_iounit_pg1(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2SasIOUnitPage1_t *config_page, u16 sz) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; ++ mpi_request.ExtPageType = MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT; ++ mpi_request.Header.PageNumber = 1; ++ mpi_request.Header.PageVersion = MPI2_SASIOUNITPAGE0_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, sz); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_expander_pg0 - obtain expander page 0 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * @form: GET_NEXT_HANDLE or HANDLE ++ * @handle: expander handle ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_expander_pg0(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2ExpanderPage0_t *config_page, u32 form, u32 handle) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; ++ mpi_request.ExtPageType = MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER; ++ mpi_request.Header.PageNumber = 0; ++ mpi_request.Header.PageVersion = MPI2_SASEXPANDER0_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.PageAddress = cpu_to_le32(form | handle); ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_expander_pg1 - obtain expander page 1 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * @phy_number: phy number ++ * @handle: expander handle ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_expander_pg1(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2ExpanderPage1_t *config_page, u32 phy_number, ++ u16 handle) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; ++ mpi_request.ExtPageType = MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER; ++ mpi_request.Header.PageNumber = 1; ++ mpi_request.Header.PageVersion = MPI2_SASEXPANDER1_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.PageAddress = ++ cpu_to_le32(MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM | ++ (phy_number << MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT) | handle); ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_enclosure_pg0 - obtain enclosure page 0 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * @form: GET_NEXT_HANDLE or HANDLE ++ * @handle: expander handle ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_enclosure_pg0(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2SasEnclosurePage0_t *config_page, u32 form, u32 handle) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; ++ mpi_request.ExtPageType = MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE; ++ mpi_request.Header.PageNumber = 0; ++ mpi_request.Header.PageVersion = MPI2_SASENCLOSURE0_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.PageAddress = cpu_to_le32(form | handle); ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_phy_pg0 - obtain phy page 0 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * @phy_number: phy number ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_phy_pg0(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2SasPhyPage0_t *config_page, u32 phy_number) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; ++ mpi_request.ExtPageType = MPI2_CONFIG_EXTPAGETYPE_SAS_PHY; ++ mpi_request.Header.PageNumber = 0; ++ mpi_request.Header.PageVersion = MPI2_SASPHY0_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.PageAddress = ++ cpu_to_le32(MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER | phy_number); ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_phy_pg1 - obtain phy page 1 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * @phy_number: phy number ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_phy_pg1(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2SasPhyPage1_t *config_page, u32 phy_number) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; ++ mpi_request.ExtPageType = MPI2_CONFIG_EXTPAGETYPE_SAS_PHY; ++ mpi_request.Header.PageNumber = 1; ++ mpi_request.Header.PageVersion = MPI2_SASPHY1_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.PageAddress = ++ cpu_to_le32(MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER | phy_number); ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_raid_volume_pg1 - obtain raid volume page 1 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * @form: GET_NEXT_HANDLE or HANDLE ++ * @handle: volume handle ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_raid_volume_pg1(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form, ++ u32 handle) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_RAID_VOLUME; ++ mpi_request.Header.PageNumber = 1; ++ mpi_request.Header.PageVersion = MPI2_RAIDVOLPAGE1_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.PageAddress = cpu_to_le32(form | handle); ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_number_pds - obtain number of phys disk assigned to volume ++ * @ioc: per adapter object ++ * @handle: volume handle ++ * @num_pds: returns pds count ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_number_pds(struct MPT2SAS_ADAPTER *ioc, u16 handle, ++ u8 *num_pds) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ Mpi2RaidVolPage0_t config_page; ++ Mpi2ConfigReply_t mpi_reply; ++ int r; ++ u16 ioc_status; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ *num_pds = 0; ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_RAID_VOLUME; ++ mpi_request.Header.PageNumber = 0; ++ mpi_request.Header.PageVersion = MPI2_RAIDVOLPAGE0_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, &mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.PageAddress = ++ cpu_to_le32(MPI2_RAID_VOLUME_PGAD_FORM_HANDLE | handle); ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, &mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, &config_page, ++ sizeof(Mpi2RaidVolPage0_t)); ++ if (!r) { ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status == MPI2_IOCSTATUS_SUCCESS) ++ *num_pds = config_page.NumPhysDisks; ++ } ++ ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_raid_volume_pg0 - obtain raid volume page 0 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * @form: GET_NEXT_HANDLE or HANDLE ++ * @handle: volume handle ++ * @sz: size of buffer passed in config_page ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_raid_volume_pg0(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 form, ++ u32 handle, u16 sz) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_RAID_VOLUME; ++ mpi_request.Header.PageNumber = 0; ++ mpi_request.Header.PageVersion = MPI2_RAIDVOLPAGE0_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.PageAddress = cpu_to_le32(form | handle); ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, sz); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_phys_disk_pg0 - obtain phys disk page 0 ++ * @ioc: per adapter object ++ * @mpi_reply: reply mf payload returned from firmware ++ * @config_page: contents of the config page ++ * @form: GET_NEXT_PHYSDISKNUM, PHYSDISKNUM, DEVHANDLE ++ * @form_specific: specific to the form ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_phys_disk_pg0(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t ++ *mpi_reply, Mpi2RaidPhysDiskPage0_t *config_page, u32 form, ++ u32 form_specific) ++{ ++ Mpi2ConfigRequest_t mpi_request; ++ int r; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK; ++ mpi_request.Header.PageNumber = 0; ++ mpi_request.Header.PageVersion = MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.PageAddress = cpu_to_le32(form | form_specific); ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ r = _config_request(ioc, &mpi_request, mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ sizeof(*config_page)); ++ out: ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_volume_handle - returns volume handle for give hidden raid components ++ * @ioc: per adapter object ++ * @pd_handle: phys disk handle ++ * @volume_handle: volume handle ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_volume_handle(struct MPT2SAS_ADAPTER *ioc, u16 pd_handle, ++ u16 *volume_handle) ++{ ++ Mpi2RaidConfigurationPage0_t *config_page = NULL; ++ Mpi2ConfigRequest_t mpi_request; ++ Mpi2ConfigReply_t mpi_reply; ++ int r, i, config_page_sz; ++ u16 ioc_status; ++ ++ *volume_handle = 0; ++ memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_CONFIG; ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER; ++ mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; ++ mpi_request.ExtPageType = MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG; ++ mpi_request.Header.PageVersion = MPI2_RAIDCONFIG0_PAGEVERSION; ++ mpi_request.Header.PageNumber = 0; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE); ++ r = _config_request(ioc, &mpi_request, &mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, NULL, 0); ++ if (r) ++ goto out; ++ ++ mpi_request.PageAddress = ++ cpu_to_le32(MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG); ++ mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT; ++ config_page_sz = (le16_to_cpu(mpi_reply.ExtPageLength) * 4); ++ config_page = kmalloc(config_page_sz, GFP_KERNEL); ++ if (!config_page) ++ goto out; ++ r = _config_request(ioc, &mpi_request, &mpi_reply, ++ MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT, config_page, ++ config_page_sz); ++ if (r) ++ goto out; ++ ++ r = -1; ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK; ++ if (ioc_status != MPI2_IOCSTATUS_SUCCESS) ++ goto out; ++ for (i = 0; i < config_page->NumElements; i++) { ++ if ((config_page->ConfigElement[i].ElementFlags & ++ MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE) != ++ MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT) ++ continue; ++ if (config_page->ConfigElement[i].PhysDiskDevHandle == ++ pd_handle) { ++ *volume_handle = le16_to_cpu(config_page-> ++ ConfigElement[i].VolDevHandle); ++ r = 0; ++ goto out; ++ } ++ } ++ out: ++ kfree(config_page); ++ return r; ++} ++ ++/** ++ * mpt2sas_config_get_volume_wwid - returns wwid given the volume handle ++ * @ioc: per adapter object ++ * @volume_handle: volume handle ++ * @wwid: volume wwid ++ * Context: sleep. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_config_get_volume_wwid(struct MPT2SAS_ADAPTER *ioc, u16 volume_handle, ++ u64 *wwid) ++{ ++ Mpi2ConfigReply_t mpi_reply; ++ Mpi2RaidVolPage1_t raid_vol_pg1; ++ ++ *wwid = 0; ++ if (!(mpt2sas_config_get_raid_volume_pg1(ioc, &mpi_reply, ++ &raid_vol_pg1, MPI2_RAID_VOLUME_PGAD_FORM_HANDLE, ++ volume_handle))) { ++ *wwid = le64_to_cpu(raid_vol_pg1.WWID); ++ return 0; ++ } else ++ return -1; ++} +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpt2sas_ctl.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpt2sas_ctl.c Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,2753 @@ ++/* ++ * Management Module Support for MPT (Message Passing Technology) based ++ * controllers ++ * ++ * This code is based on drivers/scsi/mpt2sas/mpt2_ctl.c ++ * Copyright (C) 2007-2008 LSI Corporation ++ * (mailto:DL-MPTFusionLinux@lsi.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * NO WARRANTY ++ * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR ++ * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT ++ * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is ++ * solely responsible for determining the appropriateness of using and ++ * distributing the Program and assumes all risks associated with its ++ * exercise of rights under this Agreement, including but not limited to ++ * the risks and costs of program errors, damage to or loss of data, ++ * programs or equipment, and unavailability or interruption of operations. ++ ++ * DISCLAIMER OF LIABILITY ++ * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR ++ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED ++ * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ++ ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, ++ * USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "mpt2sas_base.h" ++#include "mpt2sas_ctl.h" ++ ++static struct fasync_struct *async_queue; ++static DECLARE_WAIT_QUEUE_HEAD(ctl_poll_wait); ++ ++static int _ctl_send_release(struct MPT2SAS_ADAPTER *ioc, u8 buffer_type, ++ u8 *issue_reset); ++ ++/** ++ * enum block_state - blocking state ++ * @NON_BLOCKING: non blocking ++ * @BLOCKING: blocking ++ * ++ * These states are for ioctls that need to wait for a response ++ * from firmware, so they probably require sleep. ++ */ ++enum block_state { ++ NON_BLOCKING, ++ BLOCKING, ++}; ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++/** ++ * _ctl_display_some_debug - debug routine ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @calling_function_name: string pass from calling function ++ * @mpi_reply: reply message frame ++ * Context: none. ++ * ++ * Function for displaying debug info helpfull when debugging issues ++ * in this module. ++ */ ++static void ++_ctl_display_some_debug(struct MPT2SAS_ADAPTER *ioc, u16 smid, ++ char *calling_function_name, MPI2DefaultReply_t *mpi_reply) ++{ ++ Mpi2ConfigRequest_t *mpi_request; ++ char *desc = NULL; ++ ++ if (!(ioc->logging_level & MPT_DEBUG_IOCTL)) ++ return; ++ ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ switch (mpi_request->Function) { ++ case MPI2_FUNCTION_SCSI_IO_REQUEST: ++ { ++ Mpi2SCSIIORequest_t *scsi_request = ++ (Mpi2SCSIIORequest_t *)mpi_request; ++ ++ snprintf(ioc->tmp_string, MPT_STRING_LENGTH, ++ "scsi_io, cmd(0x%02x), cdb_len(%d)", ++ scsi_request->CDB.CDB32[0], ++ le16_to_cpu(scsi_request->IoFlags) & 0xF); ++ desc = ioc->tmp_string; ++ break; ++ } ++ case MPI2_FUNCTION_SCSI_TASK_MGMT: ++ desc = "task_mgmt"; ++ break; ++ case MPI2_FUNCTION_IOC_INIT: ++ desc = "ioc_init"; ++ break; ++ case MPI2_FUNCTION_IOC_FACTS: ++ desc = "ioc_facts"; ++ break; ++ case MPI2_FUNCTION_CONFIG: ++ { ++ Mpi2ConfigRequest_t *config_request = ++ (Mpi2ConfigRequest_t *)mpi_request; ++ ++ snprintf(ioc->tmp_string, MPT_STRING_LENGTH, ++ "config, type(0x%02x), ext_type(0x%02x), number(%d)", ++ (config_request->Header.PageType & ++ MPI2_CONFIG_PAGETYPE_MASK), config_request->ExtPageType, ++ config_request->Header.PageNumber); ++ desc = ioc->tmp_string; ++ break; ++ } ++ case MPI2_FUNCTION_PORT_FACTS: ++ desc = "port_facts"; ++ break; ++ case MPI2_FUNCTION_PORT_ENABLE: ++ desc = "port_enable"; ++ break; ++ case MPI2_FUNCTION_EVENT_NOTIFICATION: ++ desc = "event_notification"; ++ break; ++ case MPI2_FUNCTION_FW_DOWNLOAD: ++ desc = "fw_download"; ++ break; ++ case MPI2_FUNCTION_FW_UPLOAD: ++ desc = "fw_upload"; ++ break; ++ case MPI2_FUNCTION_RAID_ACTION: ++ desc = "raid_action"; ++ break; ++ case MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH: ++ { ++ Mpi2SCSIIORequest_t *scsi_request = ++ (Mpi2SCSIIORequest_t *)mpi_request; ++ ++ snprintf(ioc->tmp_string, MPT_STRING_LENGTH, ++ "raid_pass, cmd(0x%02x), cdb_len(%d)", ++ scsi_request->CDB.CDB32[0], ++ le16_to_cpu(scsi_request->IoFlags) & 0xF); ++ desc = ioc->tmp_string; ++ break; ++ } ++ case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL: ++ desc = "sas_iounit_cntl"; ++ break; ++ case MPI2_FUNCTION_SATA_PASSTHROUGH: ++ desc = "sata_pass"; ++ break; ++ case MPI2_FUNCTION_DIAG_BUFFER_POST: ++ desc = "diag_buffer_post"; ++ break; ++ case MPI2_FUNCTION_DIAG_RELEASE: ++ desc = "diag_release"; ++ break; ++ case MPI2_FUNCTION_SMP_PASSTHROUGH: ++ desc = "smp_passthrough"; ++ break; ++ } ++ ++ if (!desc) ++ return; ++ ++ printk(MPT2SAS_DEBUG_FMT "%s: %s, smid(%d)\n", ++ ioc->name, calling_function_name, desc, smid); ++ ++ if (!mpi_reply) ++ return; ++ ++ if (mpi_reply->IOCStatus || mpi_reply->IOCLogInfo) ++ printk(MPT2SAS_DEBUG_FMT ++ "\tiocstatus(0x%04x), loginfo(0x%08x)\n", ++ ioc->name, le16_to_cpu(mpi_reply->IOCStatus), ++ le32_to_cpu(mpi_reply->IOCLogInfo)); ++ ++ if (mpi_request->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || ++ mpi_request->Function == ++ MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH) { ++ Mpi2SCSIIOReply_t *scsi_reply = ++ (Mpi2SCSIIOReply_t *)mpi_reply; ++ if (scsi_reply->SCSIState || scsi_reply->SCSIStatus) ++ printk(MPT2SAS_DEBUG_FMT ++ "\tscsi_state(0x%02x), scsi_status" ++ "(0x%02x)\n", ioc->name, ++ scsi_reply->SCSIState, ++ scsi_reply->SCSIStatus); ++ } ++} ++#endif ++ ++/** ++ * mpt2sas_ctl_done - ctl module completion routine ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @VF_ID: virtual function id ++ * @reply: reply message frame(lower 32bit addr) ++ * Context: none. ++ * ++ * The callback handler when using ioc->ctl_cb_idx. ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_ctl_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, u32 reply) ++{ ++ MPI2DefaultReply_t *mpi_reply; ++ ++ if (ioc->ctl_cmds.status == MPT2_CMD_NOT_USED) ++ return; ++ if (ioc->ctl_cmds.smid != smid) ++ return; ++ ioc->ctl_cmds.status |= MPT2_CMD_COMPLETE; ++ mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply); ++ if (mpi_reply) { ++ memcpy(ioc->ctl_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); ++ ioc->ctl_cmds.status |= MPT2_CMD_REPLY_VALID; ++ } ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ _ctl_display_some_debug(ioc, smid, "ctl_done", mpi_reply); ++#endif ++ ioc->ctl_cmds.status &= ~MPT2_CMD_PENDING; ++ complete(&ioc->ctl_cmds.done); ++} ++ ++/** ++ * _ctl_check_event_type - determines when an event needs logging ++ * @ioc: per adapter object ++ * @event: firmware event ++ * ++ * The bitmask in ioc->event_type[] indicates which events should be ++ * be saved in the driver event_log. This bitmask is set by application. ++ * ++ * Returns 1 when event should be captured, or zero means no match. ++ */ ++static int ++_ctl_check_event_type(struct MPT2SAS_ADAPTER *ioc, u16 event) ++{ ++ u16 i; ++ u32 desired_event; ++ ++ if (event >= 128 || !event || !ioc->event_log) ++ return 0; ++ ++ desired_event = (1 << (event % 32)); ++ if (!desired_event) ++ desired_event = 1; ++ i = event / 32; ++ return desired_event & ioc->event_type[i]; ++} ++ ++/** ++ * mpt2sas_ctl_add_to_event_log - add event ++ * @ioc: per adapter object ++ * @mpi_reply: reply message frame ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_ctl_add_to_event_log(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventNotificationReply_t *mpi_reply) ++{ ++ struct MPT2_IOCTL_EVENTS *event_log; ++ u16 event; ++ int i; ++ u32 sz, event_data_sz; ++ u8 send_aen = 0; ++ ++ if (!ioc->event_log) ++ return; ++ ++ event = le16_to_cpu(mpi_reply->Event); ++ ++ if (_ctl_check_event_type(ioc, event)) { ++ ++ /* insert entry into circular event_log */ ++ i = ioc->event_context % MPT2SAS_CTL_EVENT_LOG_SIZE; ++ event_log = ioc->event_log; ++ event_log[i].event = event; ++ event_log[i].context = ioc->event_context++; ++ ++ event_data_sz = le16_to_cpu(mpi_reply->EventDataLength)*4; ++ sz = min_t(u32, event_data_sz, MPT2_EVENT_DATA_SIZE); ++ memset(event_log[i].data, 0, MPT2_EVENT_DATA_SIZE); ++ memcpy(event_log[i].data, mpi_reply->EventData, sz); ++ send_aen = 1; ++ } ++ ++ /* This aen_event_read_flag flag is set until the ++ * application has read the event log. ++ * For MPI2_EVENT_LOG_ENTRY_ADDED, we always notify. ++ */ ++ if (event == MPI2_EVENT_LOG_ENTRY_ADDED || ++ (send_aen && !ioc->aen_event_read_flag)) { ++ ioc->aen_event_read_flag = 1; ++ wake_up_interruptible(&ctl_poll_wait); ++ if (async_queue) ++ kill_fasync(&async_queue, SIGIO, POLL_IN); ++ } ++} ++ ++/** ++ * mpt2sas_ctl_event_callback - firmware event handler (called at ISR time) ++ * @ioc: per adapter object ++ * @VF_ID: virtual function id ++ * @reply: reply message frame(lower 32bit addr) ++ * Context: interrupt. ++ * ++ * This function merely adds a new work task into ioc->firmware_event_thread. ++ * The tasks are worked from _firmware_event_work in user context. ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_ctl_event_callback(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, u32 reply) ++{ ++ Mpi2EventNotificationReply_t *mpi_reply; ++ ++ mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply); ++ mpt2sas_ctl_add_to_event_log(ioc, mpi_reply); ++} ++ ++/** ++ * _ctl_verify_adapter - validates ioc_number passed from application ++ * @ioc: per adapter object ++ * @iocpp: The ioc pointer is returned in this. ++ * ++ * Return (-1) means error, else ioc_number. ++ */ ++static int ++_ctl_verify_adapter(int ioc_number, struct MPT2SAS_ADAPTER **iocpp) ++{ ++ struct MPT2SAS_ADAPTER *ioc; ++ ++ list_for_each_entry(ioc, &mpt2sas_ioc_list, list) { ++ if (ioc->id != ioc_number) ++ continue; ++ *iocpp = ioc; ++ return ioc_number; ++ } ++ *iocpp = NULL; ++ return -1; ++} ++ ++/** ++ * mpt2sas_ctl_reset_handler - reset callback handler (for ctl) ++ * @ioc: per adapter object ++ * @reset_phase: phase ++ * ++ * The handler for doing any required cleanup or initialization. ++ * ++ * The reset phase can be MPT2_IOC_PRE_RESET, MPT2_IOC_AFTER_RESET, ++ * MPT2_IOC_DONE_RESET ++ */ ++void ++mpt2sas_ctl_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase) ++{ ++ int i; ++ u8 issue_reset; ++ ++ switch (reset_phase) { ++ case MPT2_IOC_PRE_RESET: ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "MPT2_IOC_PRE_RESET\n", ioc->name, __func__)); ++ for (i = 0; i < MPI2_DIAG_BUF_TYPE_COUNT; i++) { ++ if (!(ioc->diag_buffer_status[i] & ++ MPT2_DIAG_BUFFER_IS_REGISTERED)) ++ continue; ++ if ((ioc->diag_buffer_status[i] & ++ MPT2_DIAG_BUFFER_IS_RELEASED)) ++ continue; ++ _ctl_send_release(ioc, i, &issue_reset); ++ } ++ break; ++ case MPT2_IOC_AFTER_RESET: ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "MPT2_IOC_AFTER_RESET\n", ioc->name, __func__)); ++ if (ioc->ctl_cmds.status & MPT2_CMD_PENDING) { ++ ioc->ctl_cmds.status |= MPT2_CMD_RESET; ++ mpt2sas_base_free_smid(ioc, ioc->ctl_cmds.smid); ++ complete(&ioc->ctl_cmds.done); ++ } ++ break; ++ case MPT2_IOC_DONE_RESET: ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "MPT2_IOC_DONE_RESET\n", ioc->name, __func__)); ++ ++ for (i = 0; i < MPI2_DIAG_BUF_TYPE_COUNT; i++) { ++ if (!(ioc->diag_buffer_status[i] & ++ MPT2_DIAG_BUFFER_IS_REGISTERED)) ++ continue; ++ if ((ioc->diag_buffer_status[i] & ++ MPT2_DIAG_BUFFER_IS_RELEASED)) ++ continue; ++ ioc->diag_buffer_status[i] |= ++ MPT2_DIAG_BUFFER_IS_DIAG_RESET; ++ } ++ break; ++ } ++} ++ ++/** ++ * _ctl_fasync - ++ * @fd - ++ * @filep - ++ * @mode - ++ * ++ * Called when application request fasyn callback handler. ++ */ ++static int ++_ctl_fasync(int fd, struct file *filep, int mode) ++{ ++ return fasync_helper(fd, filep, mode, &async_queue); ++} ++ ++/** ++ * _ctl_release - ++ * @inode - ++ * @filep - ++ * ++ * Called when application releases the fasyn callback handler. ++ */ ++static int ++_ctl_release(struct inode *inode, struct file *filep) ++{ ++ return fasync_helper(-1, filep, 0, &async_queue); ++} ++ ++/** ++ * _ctl_poll - ++ * @file - ++ * @wait - ++ * ++ */ ++static unsigned int ++_ctl_poll(struct file *filep, poll_table *wait) ++{ ++ struct MPT2SAS_ADAPTER *ioc; ++ ++ poll_wait(filep, &ctl_poll_wait, wait); ++ ++ list_for_each_entry(ioc, &mpt2sas_ioc_list, list) { ++ if (ioc->aen_event_read_flag) ++ return POLLIN | POLLRDNORM; ++ } ++ return 0; ++} ++ ++/** ++ * _ctl_set_task_mid - assign an active smid to tm request ++ * @ioc: per adapter object ++ * @karg - (struct mpt2_ioctl_command) ++ * @tm_request - pointer to mf from user space ++ * ++ * Returns 0 when an smid if found, else fail. ++ * during failure, the reply frame is filled. ++ */ ++static int ++_ctl_set_task_mid(struct MPT2SAS_ADAPTER *ioc, struct mpt2_ioctl_command *karg, ++ Mpi2SCSITaskManagementRequest_t *tm_request) ++{ ++ u8 found = 0; ++ u16 i; ++ u16 handle; ++ struct scsi_cmnd *scmd; ++ struct MPT2SAS_DEVICE *priv_data; ++ unsigned long flags; ++ Mpi2SCSITaskManagementReply_t *tm_reply; ++ u32 sz; ++ u32 lun; ++ char *desc = NULL; ++ ++ if (tm_request->TaskType == MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK) ++ desc = "abort_task"; ++ else if (tm_request->TaskType == MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK) ++ desc = "query_task"; ++ else ++ return 0; ++ ++ lun = mpt_scsilun_to_int((struct scsi_lun *)tm_request->LUN); ++ ++ handle = le16_to_cpu(tm_request->DevHandle); ++ spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); ++ for (i = ioc->request_depth; i && !found; i--) { ++ scmd = ioc->scsi_lookup[i - 1].scmd; ++ if (scmd == NULL || scmd->device == NULL || ++ scmd->device->hostdata == NULL) ++ continue; ++ if (lun != scmd->device->lun) ++ continue; ++ priv_data = scmd->device->hostdata; ++ if (priv_data->sas_target == NULL) ++ continue; ++ if (priv_data->sas_target->handle != handle) ++ continue; ++ tm_request->TaskMID = cpu_to_le16(ioc->scsi_lookup[i - 1].smid); ++ found = 1; ++ } ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++ ++ if (!found) { ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "handle(0x%04x), lun(%d), no active mid!!\n", ioc->name, ++ desc, tm_request->DevHandle, lun)); ++ tm_reply = ioc->ctl_cmds.reply; ++ tm_reply->DevHandle = tm_request->DevHandle; ++ tm_reply->Function = MPI2_FUNCTION_SCSI_TASK_MGMT; ++ tm_reply->TaskType = tm_request->TaskType; ++ tm_reply->MsgLength = sizeof(Mpi2SCSITaskManagementReply_t)/4; ++ tm_reply->VP_ID = tm_request->VP_ID; ++ tm_reply->VF_ID = tm_request->VF_ID; ++ sz = min_t(u32, karg->max_reply_bytes, ioc->reply_sz); ++ if (copy_to_user(karg->reply_frame_buf_ptr, ioc->ctl_cmds.reply, ++ sz)) ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", __FILE__, ++ __LINE__, __func__); ++ return 1; ++ } ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "handle(0x%04x), lun(%d), task_mid(%d)\n", ioc->name, ++ desc, tm_request->DevHandle, lun, tm_request->TaskMID)); ++ return 0; ++} ++ ++/** ++ * _ctl_do_mpt_command - main handler for MPT2COMMAND opcode ++ * @ioc: per adapter object ++ * @karg - (struct mpt2_ioctl_command) ++ * @mf - pointer to mf in user space ++ * @state - NON_BLOCKING or BLOCKING ++ */ ++static long ++_ctl_do_mpt_command(struct MPT2SAS_ADAPTER *ioc, ++ struct mpt2_ioctl_command karg, void __user *mf, enum block_state state) ++{ ++ MPI2RequestHeader_t *mpi_request; ++ MPI2DefaultReply_t *mpi_reply; ++ u32 ioc_state; ++ u16 ioc_status; ++ u16 smid; ++ unsigned long timeout, timeleft; ++ u8 issue_reset; ++ u32 sz; ++ void *psge; ++ void *priv_sense = NULL; ++ void *data_out = NULL; ++ dma_addr_t data_out_dma; ++ size_t data_out_sz = 0; ++ void *data_in = NULL; ++ dma_addr_t data_in_dma; ++ size_t data_in_sz = 0; ++ u32 sgl_flags; ++ long ret; ++ u16 wait_state_count; ++ ++ issue_reset = 0; ++ ++ if (state == NON_BLOCKING && !mutex_trylock(&ioc->ctl_cmds.mutex)) ++ return -EAGAIN; ++ else if (mutex_lock_interruptible(&ioc->ctl_cmds.mutex)) ++ return -ERESTARTSYS; ++ ++ if (ioc->ctl_cmds.status != MPT2_CMD_NOT_USED) { ++ printk(MPT2SAS_ERR_FMT "%s: ctl_cmd in use\n", ++ ioc->name, __func__); ++ ret = -EAGAIN; ++ goto out; ++ } ++ ++ wait_state_count = 0; ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { ++ if (wait_state_count++ == 10) { ++ printk(MPT2SAS_ERR_FMT ++ "%s: failed due to ioc not operational\n", ++ ioc->name, __func__); ++ ret = -EFAULT; ++ goto out; ++ } ++ ssleep(1); ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ printk(MPT2SAS_INFO_FMT "%s: waiting for " ++ "operational state(count=%d)\n", ioc->name, ++ __func__, wait_state_count); ++ } ++ if (wait_state_count) ++ printk(MPT2SAS_INFO_FMT "%s: ioc is operational\n", ++ ioc->name, __func__); ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->ctl_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ ret = -EAGAIN; ++ goto out; ++ } ++ ++ ret = 0; ++ ioc->ctl_cmds.status = MPT2_CMD_PENDING; ++ memset(ioc->ctl_cmds.reply, 0, ioc->reply_sz); ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ioc->ctl_cmds.smid = smid; ++ data_out_sz = karg.data_out_size; ++ data_in_sz = karg.data_in_size; ++ ++ /* copy in request message frame from user */ ++ if (copy_from_user(mpi_request, mf, karg.data_sge_offset*4)) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", __FILE__, __LINE__, ++ __func__); ++ ret = -EFAULT; ++ mpt2sas_base_free_smid(ioc, smid); ++ goto out; ++ } ++ ++ if (mpi_request->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || ++ mpi_request->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH) { ++ if (!mpi_request->FunctionDependent1 || ++ mpi_request->FunctionDependent1 > ++ cpu_to_le16(ioc->facts.MaxDevHandle)) { ++ ret = -EINVAL; ++ mpt2sas_base_free_smid(ioc, smid); ++ goto out; ++ } ++ } ++ ++ /* obtain dma-able memory for data transfer */ ++ if (data_out_sz) /* WRITE */ { ++ data_out = pci_alloc_consistent(ioc->pdev, data_out_sz, ++ &data_out_dma); ++ if (!data_out) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", __FILE__, ++ __LINE__, __func__); ++ ret = -ENOMEM; ++ mpt2sas_base_free_smid(ioc, smid); ++ goto out; ++ } ++ if (copy_from_user(data_out, karg.data_out_buf_ptr, ++ data_out_sz)) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", __FILE__, ++ __LINE__, __func__); ++ ret = -EFAULT; ++ mpt2sas_base_free_smid(ioc, smid); ++ goto out; ++ } ++ } ++ ++ if (data_in_sz) /* READ */ { ++ data_in = pci_alloc_consistent(ioc->pdev, data_in_sz, ++ &data_in_dma); ++ if (!data_in) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", __FILE__, ++ __LINE__, __func__); ++ ret = -ENOMEM; ++ mpt2sas_base_free_smid(ioc, smid); ++ goto out; ++ } ++ } ++ ++ /* add scatter gather elements */ ++ psge = (void *)mpi_request + (karg.data_sge_offset*4); ++ ++ if (!data_out_sz && !data_in_sz) { ++ mpt2sas_base_build_zero_len_sge(ioc, psge); ++ } else if (data_out_sz && data_in_sz) { ++ /* WRITE sgel first */ ++ sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | ++ MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC); ++ sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; ++ ioc->base_add_sg_single(psge, sgl_flags | ++ data_out_sz, data_out_dma); ++ ++ /* incr sgel */ ++ psge += ioc->sge_size; ++ ++ /* READ sgel last */ ++ sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | ++ MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | ++ MPI2_SGE_FLAGS_END_OF_LIST); ++ sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; ++ ioc->base_add_sg_single(psge, sgl_flags | ++ data_in_sz, data_in_dma); ++ } else if (data_out_sz) /* WRITE */ { ++ sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | ++ MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | ++ MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC); ++ sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; ++ ioc->base_add_sg_single(psge, sgl_flags | ++ data_out_sz, data_out_dma); ++ } else if (data_in_sz) /* READ */ { ++ sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | ++ MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | ++ MPI2_SGE_FLAGS_END_OF_LIST); ++ sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; ++ ioc->base_add_sg_single(psge, sgl_flags | ++ data_in_sz, data_in_dma); ++ } ++ ++ /* send command to firmware */ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ _ctl_display_some_debug(ioc, smid, "ctl_request", NULL); ++#endif ++ ++ switch (mpi_request->Function) { ++ case MPI2_FUNCTION_SCSI_IO_REQUEST: ++ case MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH: ++ { ++ Mpi2SCSIIORequest_t *scsiio_request = ++ (Mpi2SCSIIORequest_t *)mpi_request; ++ scsiio_request->SenseBufferLowAddress = ++ (u32)mpt2sas_base_get_sense_buffer_dma(ioc, smid); ++ priv_sense = mpt2sas_base_get_sense_buffer(ioc, smid); ++ memset(priv_sense, 0, SCSI_SENSE_BUFFERSIZE); ++ mpt2sas_base_put_smid_scsi_io(ioc, smid, 0, ++ le16_to_cpu(mpi_request->FunctionDependent1)); ++ break; ++ } ++ case MPI2_FUNCTION_SCSI_TASK_MGMT: ++ { ++ Mpi2SCSITaskManagementRequest_t *tm_request = ++ (Mpi2SCSITaskManagementRequest_t *)mpi_request; ++ ++ if (tm_request->TaskType == ++ MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK || ++ tm_request->TaskType == ++ MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK) { ++ if (_ctl_set_task_mid(ioc, &karg, tm_request)) { ++ mpt2sas_base_free_smid(ioc, smid); ++ goto out; ++ } ++ } ++ ++#ifdef MPT2SAS_MULTIPATH ++ mpt2sas_scsih_check_tm_for_multipath(ioc, ++ le16_to_cpu(tm_request->DevHandle), tm_request->TaskType); ++#endif ++ ++ mutex_lock(&ioc->tm_cmds.mutex); ++ mpt2sas_scsih_set_tm_flag(ioc, le16_to_cpu( ++ tm_request->DevHandle)); ++ mpt2sas_base_put_smid_hi_priority(ioc, smid, ++ mpi_request->VF_ID); ++ break; ++ } ++ case MPI2_FUNCTION_SMP_PASSTHROUGH: ++ { ++ Mpi2SmpPassthroughRequest_t *smp_request = ++ (Mpi2SmpPassthroughRequest_t *)mpi_request; ++ u8 *data; ++ ++ /* ioc determines which port to use */ ++ smp_request->PhysicalPort = 0xFF; ++ if (smp_request->PassthroughFlags & ++ MPI2_SMP_PT_REQ_PT_FLAGS_IMMEDIATE) ++ data = (u8 *)&smp_request->SGL; ++ else ++ data = data_out; ++ ++ if (data[1] == 0x91 && (data[10] == 1 || data[10] == 2)) { ++ ioc->ioc_link_reset_in_progress = 1; ++ ioc->ignore_loginfos = 1; ++ } ++ mpt2sas_base_put_smid_default(ioc, smid, mpi_request->VF_ID); ++ break; ++ } ++ case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL: ++ { ++ Mpi2SasIoUnitControlRequest_t *sasiounit_request = ++ (Mpi2SasIoUnitControlRequest_t *)mpi_request; ++ ++ if (sasiounit_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ++ || sasiounit_request->Operation == ++ MPI2_SAS_OP_PHY_LINK_RESET) { ++ ioc->ioc_link_reset_in_progress = 1; ++ ioc->ignore_loginfos = 1; ++ } ++ mpt2sas_base_put_smid_default(ioc, smid, mpi_request->VF_ID); ++ break; ++ } ++ default: ++ mpt2sas_base_put_smid_default(ioc, smid, mpi_request->VF_ID); ++ break; ++ } ++ ++ if (karg.timeout < MPT2_IOCTL_DEFAULT_TIMEOUT) ++ timeout = MPT2_IOCTL_DEFAULT_TIMEOUT; ++ else ++ timeout = karg.timeout; ++ timeleft = wait_for_completion_timeout(&ioc->ctl_cmds.done, ++ timeout*HZ); ++ if (mpi_request->Function == MPI2_FUNCTION_SCSI_TASK_MGMT) { ++ Mpi2SCSITaskManagementRequest_t *tm_request = ++ (Mpi2SCSITaskManagementRequest_t *)mpi_request; ++ mutex_unlock(&ioc->tm_cmds.mutex); ++ mpt2sas_scsih_clear_tm_flag(ioc, le16_to_cpu( ++ tm_request->DevHandle)); ++ } else if ((mpi_request->Function == MPI2_FUNCTION_SMP_PASSTHROUGH || ++ mpi_request->Function == MPI2_FUNCTION_SAS_IO_UNIT_CONTROL) && ++ ioc->ioc_link_reset_in_progress) { ++ ioc->ioc_link_reset_in_progress = 0; ++ ioc->ignore_loginfos = 0; ++ } ++ if (!(ioc->ctl_cmds.status & MPT2_CMD_COMPLETE)) { ++ printk(MPT2SAS_ERR_FMT "%s: timeout\n", ioc->name, ++ __func__); ++ _debug_dump_mf(mpi_request, karg.data_sge_offset); ++ if (!(ioc->ctl_cmds.status & MPT2_CMD_RESET)) ++ issue_reset = 1; ++ goto issue_host_reset; ++ } ++ ++ mpi_reply = ioc->ctl_cmds.reply; ++ ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ if (mpi_reply->Function == MPI2_FUNCTION_SCSI_TASK_MGMT && ++ (ioc->logging_level & MPT_DEBUG_TM)) { ++ Mpi2SCSITaskManagementReply_t *tm_reply = ++ (Mpi2SCSITaskManagementReply_t *)mpi_reply; ++ ++ printk(MPT2SAS_DEBUG_FMT "TASK_MGMT: " ++ "IOCStatus(0x%04x), IOCLogInfo(0x%08x), " ++ "TerminationCount(0x%08x)\n", ioc->name, ++ tm_reply->IOCStatus, tm_reply->IOCLogInfo, ++ tm_reply->TerminationCount); ++ } ++#endif ++ /* copy out xdata to user */ ++ if (data_in_sz) { ++ if (copy_to_user(karg.data_in_buf_ptr, data_in, ++ data_in_sz)) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", __FILE__, ++ __LINE__, __func__); ++ ret = -ENODATA; ++ goto out; ++ } ++ } ++ ++ /* copy out reply message frame to user */ ++ if (karg.max_reply_bytes) { ++ sz = min_t(u32, karg.max_reply_bytes, ioc->reply_sz); ++ if (copy_to_user(karg.reply_frame_buf_ptr, ioc->ctl_cmds.reply, ++ sz)) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", __FILE__, ++ __LINE__, __func__); ++ ret = -ENODATA; ++ goto out; ++ } ++ } ++ ++ /* copy out sense to user */ ++ if (karg.max_sense_bytes && (mpi_request->Function == ++ MPI2_FUNCTION_SCSI_IO_REQUEST || mpi_request->Function == ++ MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { ++ sz = min_t(u32, karg.max_sense_bytes, SCSI_SENSE_BUFFERSIZE); ++ if (copy_to_user(karg.sense_data_ptr, priv_sense, sz)) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", __FILE__, ++ __LINE__, __func__); ++ ret = -ENODATA; ++ goto out; ++ } ++ } ++ ++ issue_host_reset: ++ if (issue_reset) { ++ if ((mpi_request->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || ++ mpi_request->Function == ++ MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { ++ printk(MPT2SAS_INFO_FMT "issue target reset: handle " ++ "= (0x%04x)\n", ioc->name, ++ mpi_request->FunctionDependent1); ++ mutex_lock(&ioc->tm_cmds.mutex); ++ mpt2sas_scsih_issue_tm(ioc, ++ mpi_request->FunctionDependent1, 0, ++ MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, 0, 10); ++ ioc->tm_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->tm_cmds.mutex); ++ } else ++ mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, ++ FORCE_BIG_HAMMER); ++ } ++ ++ out: ++ ++ /* free memory associated with sg buffers */ ++ if (data_in) ++ pci_free_consistent(ioc->pdev, data_in_sz, data_in, ++ data_in_dma); ++ ++ if (data_out) ++ pci_free_consistent(ioc->pdev, data_out_sz, data_out, ++ data_out_dma); ++ ++ ioc->ctl_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->ctl_cmds.mutex); ++ return ret; ++} ++ ++/** ++ * _ctl_getiocinfo - main handler for MPT2IOCINFO opcode ++ * @arg - user space buffer containing ioctl content ++ */ ++static long ++_ctl_getiocinfo(void __user *arg) ++{ ++ struct mpt2_ioctl_iocinfo karg; ++ struct MPT2SAS_ADAPTER *ioc; ++ u8 revision; ++ ++ if (copy_from_user(&karg, arg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ if (_ctl_verify_adapter(karg.hdr.ioc_number, &ioc) == -1 || !ioc) ++ return -ENODEV; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: enter\n", ioc->name, ++ __func__)); ++ ++ memset(&karg, 0 , sizeof(karg)); ++ karg.adapter_type = MPT2_IOCTL_INTERFACE_SAS2; ++ if (ioc->pfacts) ++ karg.port_number = ioc->pfacts[0].PortNumber; ++ pci_read_config_byte(ioc->pdev, PCI_CLASS_REVISION, &revision); ++ karg.hw_rev = revision; ++ karg.pci_id = ioc->pdev->device; ++ karg.subsystem_device = ioc->pdev->subsystem_device; ++ karg.subsystem_vendor = ioc->pdev->subsystem_vendor; ++ karg.pci_information.u.bits.bus = ioc->pdev->bus->number; ++ karg.pci_information.u.bits.device = PCI_SLOT(ioc->pdev->devfn); ++ karg.pci_information.u.bits.function = PCI_FUNC(ioc->pdev->devfn); ++ karg.pci_information.segment_id = pci_domain_nr(ioc->pdev->bus); ++ karg.firmware_version = ioc->facts.FWVersion.Word; ++ strcpy(karg.driver_version, MPT2SAS_DRIVER_NAME); ++ strcat(karg.driver_version, "-"); ++ strcat(karg.driver_version, MPT2SAS_DRIVER_VERSION); ++ karg.bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion); ++ ++ if (copy_to_user(arg, &karg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++/** ++ * _ctl_eventquery - main handler for MPT2EVENTQUERY opcode ++ * @arg - user space buffer containing ioctl content ++ */ ++static long ++_ctl_eventquery(void __user *arg) ++{ ++ struct mpt2_ioctl_eventquery karg; ++ struct MPT2SAS_ADAPTER *ioc; ++ ++ if (copy_from_user(&karg, arg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ if (_ctl_verify_adapter(karg.hdr.ioc_number, &ioc) == -1 || !ioc) ++ return -ENODEV; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: enter\n", ioc->name, ++ __func__)); ++ ++ karg.event_entries = MPT2SAS_CTL_EVENT_LOG_SIZE; ++ memcpy(karg.event_types, ioc->event_type, ++ MPI2_EVENT_NOTIFY_EVENTMASK_WORDS * sizeof(u32)); ++ ++ if (copy_to_user(arg, &karg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++/** ++ * _ctl_eventenable - main handler for MPT2EVENTENABLE opcode ++ * @arg - user space buffer containing ioctl content ++ */ ++static long ++_ctl_eventenable(void __user *arg) ++{ ++ struct mpt2_ioctl_eventenable karg; ++ struct MPT2SAS_ADAPTER *ioc; ++ ++ if (copy_from_user(&karg, arg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ if (_ctl_verify_adapter(karg.hdr.ioc_number, &ioc) == -1 || !ioc) ++ return -ENODEV; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: enter\n", ioc->name, ++ __func__)); ++ ++ if (ioc->event_log) ++ return 0; ++ memcpy(ioc->event_type, karg.event_types, ++ MPI2_EVENT_NOTIFY_EVENTMASK_WORDS * sizeof(u32)); ++ mpt2sas_base_validate_event_type(ioc, ioc->event_type); ++ ++ /* initialize event_log */ ++ ioc->event_context = 0; ++ ioc->aen_event_read_flag = 0; ++ ioc->event_log = kcalloc(MPT2SAS_CTL_EVENT_LOG_SIZE, ++ sizeof(struct MPT2_IOCTL_EVENTS), GFP_KERNEL); ++ if (!ioc->event_log) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -ENOMEM; ++ } ++ return 0; ++} ++ ++/** ++ * _ctl_eventreport - main handler for MPT2EVENTREPORT opcode ++ * @arg - user space buffer containing ioctl content ++ */ ++static long ++_ctl_eventreport(void __user *arg) ++{ ++ struct mpt2_ioctl_eventreport karg; ++ struct MPT2SAS_ADAPTER *ioc; ++ u32 number_bytes, max_events, max; ++ struct mpt2_ioctl_eventreport __user *uarg = arg; ++ ++ if (copy_from_user(&karg, arg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ if (_ctl_verify_adapter(karg.hdr.ioc_number, &ioc) == -1 || !ioc) ++ return -ENODEV; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: enter\n", ioc->name, ++ __func__)); ++ ++ number_bytes = karg.hdr.max_data_size - ++ sizeof(struct mpt2_ioctl_header); ++ max_events = number_bytes/sizeof(struct MPT2_IOCTL_EVENTS); ++ max = min_t(u32, MPT2SAS_CTL_EVENT_LOG_SIZE, max_events); ++ ++ /* If fewer than 1 event is requested, there must have ++ * been some type of error. ++ */ ++ if (!max || !ioc->event_log) ++ return -ENODATA; ++ ++ number_bytes = max * sizeof(struct MPT2_IOCTL_EVENTS); ++ if (copy_to_user(uarg->event_data, ioc->event_log, number_bytes)) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ ++ /* reset flag so SIGIO can restart */ ++ ioc->aen_event_read_flag = 0; ++ return 0; ++} ++ ++/** ++ * _ctl_do_reset - main handler for MPT2HARDRESET opcode ++ * @arg - user space buffer containing ioctl content ++ */ ++static long ++_ctl_do_reset(void __user *arg) ++{ ++ struct mpt2_ioctl_diag_reset karg; ++ struct MPT2SAS_ADAPTER *ioc; ++ int retval; ++ ++ if (copy_from_user(&karg, arg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ if (_ctl_verify_adapter(karg.hdr.ioc_number, &ioc) == -1 || !ioc) ++ return -ENODEV; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: enter\n", ioc->name, ++ __func__)); ++ ++ retval = mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, ++ FORCE_BIG_HAMMER); ++ printk(MPT2SAS_INFO_FMT "host reset: %s\n", ++ ioc->name, ((!retval) ? "SUCCESS" : "FAILED")); ++ return 0; ++} ++ ++/** ++ * _ctl_btdh_search_sas_device - searching for sas device ++ * @ioc: per adapter object ++ * @btdh: btdh ioctl payload ++ */ ++static int ++_ctl_btdh_search_sas_device(struct MPT2SAS_ADAPTER *ioc, ++ struct mpt2_ioctl_btdh_mapping *btdh) ++{ ++ struct _sas_device *sas_device; ++ unsigned long flags; ++ int rc = 0; ++ ++ if (list_empty(&ioc->sas_device_list)) ++ return rc; ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ list_for_each_entry(sas_device, &ioc->sas_device_list, list) { ++ if (btdh->bus == 0xFFFFFFFF && btdh->id == 0xFFFFFFFF && ++ btdh->handle == sas_device->handle) { ++ btdh->bus = sas_device->channel; ++ btdh->id = sas_device->id; ++ rc = 1; ++ goto out; ++ } else if (btdh->bus == sas_device->channel && btdh->id == ++ sas_device->id && btdh->handle == 0xFFFF) { ++ btdh->handle = sas_device->handle; ++ rc = 1; ++ goto out; ++ } ++ } ++ out: ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ return rc; ++} ++ ++/** ++ * _ctl_btdh_search_raid_device - searching for raid device ++ * @ioc: per adapter object ++ * @btdh: btdh ioctl payload ++ */ ++static int ++_ctl_btdh_search_raid_device(struct MPT2SAS_ADAPTER *ioc, ++ struct mpt2_ioctl_btdh_mapping *btdh) ++{ ++ struct _raid_device *raid_device; ++ unsigned long flags; ++ int rc = 0; ++ ++ if (list_empty(&ioc->raid_device_list)) ++ return rc; ++ ++ spin_lock_irqsave(&ioc->raid_device_lock, flags); ++ list_for_each_entry(raid_device, &ioc->raid_device_list, list) { ++ if (btdh->bus == 0xFFFFFFFF && btdh->id == 0xFFFFFFFF && ++ btdh->handle == raid_device->handle) { ++ btdh->bus = raid_device->channel; ++ btdh->id = raid_device->id; ++ rc = 1; ++ goto out; ++ } else if (btdh->bus == raid_device->channel && btdh->id == ++ raid_device->id && btdh->handle == 0xFFFF) { ++ btdh->handle = raid_device->handle; ++ rc = 1; ++ goto out; ++ } ++ } ++ out: ++ spin_unlock_irqrestore(&ioc->raid_device_lock, flags); ++ return rc; ++} ++ ++/** ++ * _ctl_btdh_mapping - main handler for MPT2BTDHMAPPING opcode ++ * @arg - user space buffer containing ioctl content ++ */ ++static long ++_ctl_btdh_mapping(void __user *arg) ++{ ++ struct mpt2_ioctl_btdh_mapping karg; ++ struct MPT2SAS_ADAPTER *ioc; ++ int rc; ++ ++ if (copy_from_user(&karg, arg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ if (_ctl_verify_adapter(karg.hdr.ioc_number, &ioc) == -1 || !ioc) ++ return -ENODEV; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ rc = _ctl_btdh_search_sas_device(ioc, &karg); ++ if (!rc) ++ _ctl_btdh_search_raid_device(ioc, &karg); ++ ++ if (copy_to_user(arg, &karg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++/** ++ * _ctl_diag_capability - return diag buffer capability ++ * @ioc: per adapter object ++ * @buffer_type: specifies either TRACE or SNAPSHOT ++ * ++ * returns 1 when diag buffer support is enabled in firmware ++ */ ++static u8 ++_ctl_diag_capability(struct MPT2SAS_ADAPTER *ioc, u8 buffer_type) ++{ ++ u8 rc = 0; ++ ++ switch (buffer_type) { ++ case MPI2_DIAG_BUF_TYPE_TRACE: ++ if (ioc->facts.IOCCapabilities & ++ MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) ++ rc = 1; ++ break; ++ case MPI2_DIAG_BUF_TYPE_SNAPSHOT: ++ if (ioc->facts.IOCCapabilities & ++ MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) ++ rc = 1; ++ break; ++ } ++ ++ return rc; ++} ++ ++/** ++ * _ctl_diag_register - application register with driver ++ * @arg - user space buffer containing ioctl content ++ * @state - NON_BLOCKING or BLOCKING ++ * ++ * This will allow the driver to setup any required buffers that will be ++ * needed by firmware to communicate with the driver. ++ */ ++static long ++_ctl_diag_register(void __user *arg, enum block_state state) ++{ ++ struct mpt2_diag_register karg; ++ struct MPT2SAS_ADAPTER *ioc; ++ int rc, i; ++ void *request_data = NULL; ++ dma_addr_t request_data_dma; ++ u32 request_data_sz = 0; ++ Mpi2DiagBufferPostRequest_t *mpi_request; ++ Mpi2DiagBufferPostReply_t *mpi_reply; ++ u8 buffer_type; ++ unsigned long timeleft; ++ u16 smid; ++ u16 ioc_status; ++ u8 issue_reset = 0; ++ ++ if (copy_from_user(&karg, arg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ if (_ctl_verify_adapter(karg.hdr.ioc_number, &ioc) == -1 || !ioc) ++ return -ENODEV; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ buffer_type = karg.buffer_type; ++ if (!_ctl_diag_capability(ioc, buffer_type)) { ++ printk(MPT2SAS_ERR_FMT "%s: doesn't have capability for " ++ "buffer_type(0x%02x)\n", ioc->name, __func__, buffer_type); ++ return -EPERM; ++ } ++ ++ if (ioc->diag_buffer_status[buffer_type] & ++ MPT2_DIAG_BUFFER_IS_REGISTERED) { ++ printk(MPT2SAS_ERR_FMT "%s: already has a registered " ++ "buffer for buffer_type(0x%02x)\n", ioc->name, __func__, ++ buffer_type); ++ return -EINVAL; ++ } ++ ++ if (karg.requested_buffer_size % 4) { ++ printk(MPT2SAS_ERR_FMT "%s: the requested_buffer_size " ++ "is not 4 byte aligned\n", ioc->name, __func__); ++ return -EINVAL; ++ } ++ ++ if (state == NON_BLOCKING && !mutex_trylock(&ioc->ctl_cmds.mutex)) ++ return -EAGAIN; ++ else if (mutex_lock_interruptible(&ioc->ctl_cmds.mutex)) ++ return -ERESTARTSYS; ++ ++ if (ioc->ctl_cmds.status != MPT2_CMD_NOT_USED) { ++ printk(MPT2SAS_ERR_FMT "%s: ctl_cmd in use\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->ctl_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ rc = 0; ++ ioc->ctl_cmds.status = MPT2_CMD_PENDING; ++ memset(ioc->ctl_cmds.reply, 0, ioc->reply_sz); ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ioc->ctl_cmds.smid = smid; ++ ++ request_data = ioc->diag_buffer[buffer_type]; ++ request_data_sz = karg.requested_buffer_size; ++ ioc->unique_id[buffer_type] = karg.unique_id; ++ ioc->diag_buffer_status[buffer_type] = 0; ++ memcpy(ioc->product_specific[buffer_type], karg.product_specific, ++ MPT2_PRODUCT_SPECIFIC_DWORDS); ++ ioc->diagnostic_flags[buffer_type] = karg.diagnostic_flags; ++ ++ if (request_data) { ++ request_data_dma = ioc->diag_buffer_dma[buffer_type]; ++ if (request_data_sz != ioc->diag_buffer_sz[buffer_type]) { ++ pci_free_consistent(ioc->pdev, ++ ioc->diag_buffer_sz[buffer_type], ++ request_data, request_data_dma); ++ request_data = NULL; ++ } ++ } ++ ++ if (request_data == NULL) { ++ ioc->diag_buffer_sz[buffer_type] = 0; ++ ioc->diag_buffer_dma[buffer_type] = 0; ++ request_data = pci_alloc_consistent( ++ ioc->pdev, request_data_sz, &request_data_dma); ++ if (request_data == NULL) { ++ printk(MPT2SAS_ERR_FMT "%s: failed allocating memory" ++ " for diag buffers, requested size(%d)\n", ++ ioc->name, __func__, request_data_sz); ++ mpt2sas_base_free_smid(ioc, smid); ++ return -ENOMEM; ++ } ++ ioc->diag_buffer[buffer_type] = request_data; ++ ioc->diag_buffer_sz[buffer_type] = request_data_sz; ++ ioc->diag_buffer_dma[buffer_type] = request_data_dma; ++ } ++ ++ mpi_request->Function = MPI2_FUNCTION_DIAG_BUFFER_POST; ++ mpi_request->BufferType = karg.buffer_type; ++ mpi_request->Flags = cpu_to_le32(karg.diagnostic_flags); ++ mpi_request->BufferAddress = cpu_to_le64(request_data_dma); ++ mpi_request->BufferLength = cpu_to_le32(request_data_sz); ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: diag_buffer(0x%p), " ++ "dma(0x%llx), sz(%d)\n", ioc->name, __func__, request_data, ++ (unsigned long long)request_data_dma, mpi_request->BufferLength)); ++ ++ for (i = 0; i < MPT2_PRODUCT_SPECIFIC_DWORDS; i++) ++ mpi_request->ProductSpecific[i] = ++ cpu_to_le32(ioc->product_specific[buffer_type][i]); ++ ++ mpt2sas_base_put_smid_default(ioc, smid, mpi_request->VF_ID); ++ timeleft = wait_for_completion_timeout(&ioc->ctl_cmds.done, ++ MPT2_IOCTL_DEFAULT_TIMEOUT*HZ); ++ ++ if (!(ioc->ctl_cmds.status & MPT2_CMD_COMPLETE)) { ++ printk(MPT2SAS_ERR_FMT "%s: timeout\n", ioc->name, ++ __func__); ++ _debug_dump_mf(mpi_request, ++ sizeof(Mpi2DiagBufferPostRequest_t)/4); ++ if (!(ioc->ctl_cmds.status & MPT2_CMD_RESET)) ++ issue_reset = 1; ++ goto issue_host_reset; ++ } ++ ++ /* process the completed Reply Message Frame */ ++ if ((ioc->ctl_cmds.status & MPT2_CMD_REPLY_VALID) == 0) { ++ printk(MPT2SAS_ERR_FMT "%s: no reply message\n", ++ ioc->name, __func__); ++ rc = -EFAULT; ++ goto out; ++ } ++ ++ mpi_reply = ioc->ctl_cmds.reply; ++ ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; ++ ++ if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { ++ ioc->diag_buffer_status[buffer_type] |= ++ MPT2_DIAG_BUFFER_IS_REGISTERED; ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: success\n", ++ ioc->name, __func__)); ++ } else { ++ printk(MPT2SAS_DEBUG_FMT "%s: ioc_status(0x%04x) " ++ "log_info(0x%08x)\n", ioc->name, __func__, ++ ioc_status, mpi_reply->IOCLogInfo); ++ rc = -EFAULT; ++ } ++ ++ issue_host_reset: ++ if (issue_reset) ++ mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, ++ FORCE_BIG_HAMMER); ++ ++ out: ++ ++ if (rc && request_data) ++ pci_free_consistent(ioc->pdev, request_data_sz, ++ request_data, request_data_dma); ++ ++ ioc->ctl_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->ctl_cmds.mutex); ++ return rc; ++} ++ ++/** ++ * _ctl_diag_unregister - application unregister with driver ++ * @arg - user space buffer containing ioctl content ++ * ++ * This will allow the driver to cleanup any memory allocated for diag ++ * messages and to free up any resources. ++ */ ++static long ++_ctl_diag_unregister(void __user *arg) ++{ ++ struct mpt2_diag_unregister karg; ++ struct MPT2SAS_ADAPTER *ioc; ++ void *request_data; ++ dma_addr_t request_data_dma; ++ u32 request_data_sz; ++ u8 buffer_type; ++ ++ if (copy_from_user(&karg, arg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ if (_ctl_verify_adapter(karg.hdr.ioc_number, &ioc) == -1 || !ioc) ++ return -ENODEV; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ buffer_type = karg.unique_id & 0x000000ff; ++ if (!_ctl_diag_capability(ioc, buffer_type)) { ++ printk(MPT2SAS_ERR_FMT "%s: doesn't have capability for " ++ "buffer_type(0x%02x)\n", ioc->name, __func__, buffer_type); ++ return -EPERM; ++ } ++ ++ if ((ioc->diag_buffer_status[buffer_type] & ++ MPT2_DIAG_BUFFER_IS_REGISTERED) == 0) { ++ printk(MPT2SAS_ERR_FMT "%s: buffer_type(0x%02x) is not " ++ "registered\n", ioc->name, __func__, buffer_type); ++ return -EINVAL; ++ } ++ if ((ioc->diag_buffer_status[buffer_type] & ++ MPT2_DIAG_BUFFER_IS_RELEASED) == 0) { ++ printk(MPT2SAS_ERR_FMT "%s: buffer_type(0x%02x) has not been " ++ "released\n", ioc->name, __func__, buffer_type); ++ return -EINVAL; ++ } ++ ++ if (karg.unique_id != ioc->unique_id[buffer_type]) { ++ printk(MPT2SAS_ERR_FMT "%s: unique_id(0x%08x) is not " ++ "registered\n", ioc->name, __func__, karg.unique_id); ++ return -EINVAL; ++ } ++ ++ request_data = ioc->diag_buffer[buffer_type]; ++ if (!request_data) { ++ printk(MPT2SAS_ERR_FMT "%s: doesn't have memory allocated for " ++ "buffer_type(0x%02x)\n", ioc->name, __func__, buffer_type); ++ return -ENOMEM; ++ } ++ ++ request_data_sz = ioc->diag_buffer_sz[buffer_type]; ++ request_data_dma = ioc->diag_buffer_dma[buffer_type]; ++ pci_free_consistent(ioc->pdev, request_data_sz, ++ request_data, request_data_dma); ++ ioc->diag_buffer[buffer_type] = NULL; ++ ioc->diag_buffer_status[buffer_type] = 0; ++ return 0; ++} ++ ++/** ++ * _ctl_diag_query - query relevant info associated with diag buffers ++ * @arg - user space buffer containing ioctl content ++ * ++ * The application will send only buffer_type and unique_id. Driver will ++ * inspect unique_id first, if valid, fill in all the info. If unique_id is ++ * 0x00, the driver will return info specified by Buffer Type. ++ */ ++static long ++_ctl_diag_query(void __user *arg) ++{ ++ struct mpt2_diag_query karg; ++ struct MPT2SAS_ADAPTER *ioc; ++ void *request_data; ++ int i; ++ u8 buffer_type; ++ ++ if (copy_from_user(&karg, arg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ if (_ctl_verify_adapter(karg.hdr.ioc_number, &ioc) == -1 || !ioc) ++ return -ENODEV; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ karg.application_flags = 0; ++ buffer_type = karg.buffer_type; ++ ++ if (!_ctl_diag_capability(ioc, buffer_type)) { ++ printk(MPT2SAS_ERR_FMT "%s: doesn't have capability for " ++ "buffer_type(0x%02x)\n", ioc->name, __func__, buffer_type); ++ return -EPERM; ++ } ++ ++ if ((ioc->diag_buffer_status[buffer_type] & ++ MPT2_DIAG_BUFFER_IS_REGISTERED) == 0) { ++ printk(MPT2SAS_ERR_FMT "%s: buffer_type(0x%02x) is not " ++ "registered\n", ioc->name, __func__, buffer_type); ++ return -EINVAL; ++ } ++ ++ if (karg.unique_id & 0xffffff00) { ++ if (karg.unique_id != ioc->unique_id[buffer_type]) { ++ printk(MPT2SAS_ERR_FMT "%s: unique_id(0x%08x) is not " ++ "registered\n", ioc->name, __func__, ++ karg.unique_id); ++ return -EINVAL; ++ } ++ } ++ ++ request_data = ioc->diag_buffer[buffer_type]; ++ if (!request_data) { ++ printk(MPT2SAS_ERR_FMT "%s: doesn't have buffer for " ++ "buffer_type(0x%02x)\n", ioc->name, __func__, buffer_type); ++ return -ENOMEM; ++ } ++ ++ if (ioc->diag_buffer_status[buffer_type] & MPT2_DIAG_BUFFER_IS_RELEASED) ++ karg.application_flags = (MPT2_APP_FLAGS_APP_OWNED | ++ MPT2_APP_FLAGS_BUFFER_VALID); ++ else ++ karg.application_flags = (MPT2_APP_FLAGS_APP_OWNED | ++ MPT2_APP_FLAGS_BUFFER_VALID | ++ MPT2_APP_FLAGS_FW_BUFFER_ACCESS); ++ ++ for (i = 0; i < MPT2_PRODUCT_SPECIFIC_DWORDS; i++) ++ karg.product_specific[i] = ++ ioc->product_specific[buffer_type][i]; ++ ++ karg.total_buffer_size = ioc->diag_buffer_sz[buffer_type]; ++ karg.driver_added_buffer_size = 0; ++ karg.unique_id = ioc->unique_id[buffer_type]; ++ karg.diagnostic_flags = ioc->diagnostic_flags[buffer_type]; ++ ++ if (copy_to_user(arg, &karg, sizeof(struct mpt2_diag_query))) { ++ printk(MPT2SAS_ERR_FMT "%s: unable to write mpt2_diag_query " ++ "data @ %p\n", ioc->name, __func__, arg); ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++/** ++ * _ctl_send_release - Diag Release Message ++ * @ioc: per adapter object ++ * @buffer_type - specifies either TRACE or SNAPSHOT ++ * @issue_reset - specifies whether host reset is required. ++ * ++ */ ++static int ++_ctl_send_release(struct MPT2SAS_ADAPTER *ioc, u8 buffer_type, u8 *issue_reset) ++{ ++ Mpi2DiagReleaseRequest_t *mpi_request; ++ Mpi2DiagReleaseReply_t *mpi_reply; ++ u16 smid; ++ u16 ioc_status; ++ u32 ioc_state; ++ int rc; ++ unsigned long timeleft; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ rc = 0; ++ *issue_reset = 0; ++ ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ if (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "skipping due to FAULT state\n", ioc->name, ++ __func__)); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ if (ioc->ctl_cmds.status != MPT2_CMD_NOT_USED) { ++ printk(MPT2SAS_ERR_FMT "%s: ctl_cmd in use\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->ctl_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ ioc->ctl_cmds.status = MPT2_CMD_PENDING; ++ memset(ioc->ctl_cmds.reply, 0, ioc->reply_sz); ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ioc->ctl_cmds.smid = smid; ++ ++ mpi_request->Function = MPI2_FUNCTION_DIAG_RELEASE; ++ mpi_request->BufferType = buffer_type; ++ ++ mpt2sas_base_put_smid_default(ioc, smid, mpi_request->VF_ID); ++ timeleft = wait_for_completion_timeout(&ioc->ctl_cmds.done, ++ MPT2_IOCTL_DEFAULT_TIMEOUT*HZ); ++ ++ if (!(ioc->ctl_cmds.status & MPT2_CMD_COMPLETE)) { ++ printk(MPT2SAS_ERR_FMT "%s: timeout\n", ioc->name, ++ __func__); ++ _debug_dump_mf(mpi_request, ++ sizeof(Mpi2DiagReleaseRequest_t)/4); ++ if (!(ioc->ctl_cmds.status & MPT2_CMD_RESET)) ++ *issue_reset = 1; ++ rc = -EFAULT; ++ goto out; ++ } ++ ++ /* process the completed Reply Message Frame */ ++ if ((ioc->ctl_cmds.status & MPT2_CMD_REPLY_VALID) == 0) { ++ printk(MPT2SAS_ERR_FMT "%s: no reply message\n", ++ ioc->name, __func__); ++ rc = -EFAULT; ++ goto out; ++ } ++ ++ mpi_reply = ioc->ctl_cmds.reply; ++ ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; ++ ++ if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { ++ ioc->diag_buffer_status[buffer_type] |= ++ MPT2_DIAG_BUFFER_IS_RELEASED; ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: success\n", ++ ioc->name, __func__)); ++ } else { ++ printk(MPT2SAS_DEBUG_FMT "%s: ioc_status(0x%04x) " ++ "log_info(0x%08x)\n", ioc->name, __func__, ++ ioc_status, mpi_reply->IOCLogInfo); ++ rc = -EFAULT; ++ } ++ ++ out: ++ ioc->ctl_cmds.status = MPT2_CMD_NOT_USED; ++ return rc; ++} ++ ++/** ++ * _ctl_diag_release - request to send Diag Release Message to firmware ++ * @arg - user space buffer containing ioctl content ++ * @state - NON_BLOCKING or BLOCKING ++ * ++ * This allows ownership of the specified buffer to returned to the driver, ++ * allowing an application to read the buffer without fear that firmware is ++ * overwritting information in the buffer. ++ */ ++static long ++_ctl_diag_release(void __user *arg, enum block_state state) ++{ ++ struct mpt2_diag_release karg; ++ struct MPT2SAS_ADAPTER *ioc; ++ void *request_data; ++ int rc; ++ u8 buffer_type; ++ u8 issue_reset = 0; ++ ++ if (copy_from_user(&karg, arg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ if (_ctl_verify_adapter(karg.hdr.ioc_number, &ioc) == -1 || !ioc) ++ return -ENODEV; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ buffer_type = karg.unique_id & 0x000000ff; ++ if (!_ctl_diag_capability(ioc, buffer_type)) { ++ printk(MPT2SAS_ERR_FMT "%s: doesn't have capability for " ++ "buffer_type(0x%02x)\n", ioc->name, __func__, buffer_type); ++ return -EPERM; ++ } ++ ++ if ((ioc->diag_buffer_status[buffer_type] & ++ MPT2_DIAG_BUFFER_IS_REGISTERED) == 0) { ++ printk(MPT2SAS_ERR_FMT "%s: buffer_type(0x%02x) is not " ++ "registered\n", ioc->name, __func__, buffer_type); ++ return -EINVAL; ++ } ++ ++ if (karg.unique_id != ioc->unique_id[buffer_type]) { ++ printk(MPT2SAS_ERR_FMT "%s: unique_id(0x%08x) is not " ++ "registered\n", ioc->name, __func__, karg.unique_id); ++ return -EINVAL; ++ } ++ ++ if (ioc->diag_buffer_status[buffer_type] & ++ MPT2_DIAG_BUFFER_IS_RELEASED) { ++ printk(MPT2SAS_ERR_FMT "%s: buffer_type(0x%02x) " ++ "is already released\n", ioc->name, __func__, ++ buffer_type); ++ return 0; ++ } ++ ++ request_data = ioc->diag_buffer[buffer_type]; ++ ++ if (!request_data) { ++ printk(MPT2SAS_ERR_FMT "%s: doesn't have memory allocated for " ++ "buffer_type(0x%02x)\n", ioc->name, __func__, buffer_type); ++ return -ENOMEM; ++ } ++ ++ /* buffers were released by due to host reset */ ++ if ((ioc->diag_buffer_status[buffer_type] & ++ MPT2_DIAG_BUFFER_IS_DIAG_RESET)) { ++ ioc->diag_buffer_status[buffer_type] |= ++ MPT2_DIAG_BUFFER_IS_RELEASED; ++ ioc->diag_buffer_status[buffer_type] &= ++ ~MPT2_DIAG_BUFFER_IS_DIAG_RESET; ++ printk(MPT2SAS_ERR_FMT "%s: buffer_type(0x%02x) " ++ "was released due to host reset\n", ioc->name, __func__, ++ buffer_type); ++ return 0; ++ } ++ ++ if (state == NON_BLOCKING && !mutex_trylock(&ioc->ctl_cmds.mutex)) ++ return -EAGAIN; ++ else if (mutex_lock_interruptible(&ioc->ctl_cmds.mutex)) ++ return -ERESTARTSYS; ++ ++ rc = _ctl_send_release(ioc, buffer_type, &issue_reset); ++ ++ if (issue_reset) ++ mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, ++ FORCE_BIG_HAMMER); ++ ++ mutex_unlock(&ioc->ctl_cmds.mutex); ++ return rc; ++} ++ ++/** ++ * _ctl_diag_read_buffer - request for copy of the diag buffer ++ * @arg - user space buffer containing ioctl content ++ * @state - NON_BLOCKING or BLOCKING ++ */ ++static long ++_ctl_diag_read_buffer(void __user *arg, enum block_state state) ++{ ++ struct mpt2_diag_read_buffer karg; ++ struct mpt2_diag_read_buffer __user *uarg = arg; ++ struct MPT2SAS_ADAPTER *ioc; ++ void *request_data, *diag_data; ++ Mpi2DiagBufferPostRequest_t *mpi_request; ++ Mpi2DiagBufferPostReply_t *mpi_reply; ++ int rc, i; ++ u8 buffer_type; ++ unsigned long timeleft; ++ u16 smid; ++ u16 ioc_status; ++ u8 issue_reset = 0; ++ ++ if (copy_from_user(&karg, arg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ if (_ctl_verify_adapter(karg.hdr.ioc_number, &ioc) == -1 || !ioc) ++ return -ENODEV; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name, ++ __func__)); ++ ++ buffer_type = karg.unique_id & 0x000000ff; ++ if (!_ctl_diag_capability(ioc, buffer_type)) { ++ printk(MPT2SAS_ERR_FMT "%s: doesn't have capability for " ++ "buffer_type(0x%02x)\n", ioc->name, __func__, buffer_type); ++ return -EPERM; ++ } ++ ++ if (karg.unique_id != ioc->unique_id[buffer_type]) { ++ printk(MPT2SAS_ERR_FMT "%s: unique_id(0x%08x) is not " ++ "registered\n", ioc->name, __func__, karg.unique_id); ++ return -EINVAL; ++ } ++ ++ request_data = ioc->diag_buffer[buffer_type]; ++ if (!request_data) { ++ printk(MPT2SAS_ERR_FMT "%s: doesn't have buffer for " ++ "buffer_type(0x%02x)\n", ioc->name, __func__, buffer_type); ++ return -ENOMEM; ++ } ++ ++ if ((karg.starting_offset % 4) || (karg.bytes_to_read % 4)) { ++ printk(MPT2SAS_ERR_FMT "%s: either the starting_offset " ++ "or bytes_to_read are not 4 byte aligned\n", ioc->name, ++ __func__); ++ return -EINVAL; ++ } ++ ++ diag_data = (void *)(request_data + karg.starting_offset); ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: diag_buffer(%p), " ++ "offset(%d), sz(%d)\n", ioc->name, __func__, ++ diag_data, karg.starting_offset, karg.bytes_to_read)); ++ ++ if (copy_to_user((void __user *)uarg->diagnostic_data, ++ diag_data, karg.bytes_to_read)) { ++ printk(MPT2SAS_ERR_FMT "%s: Unable to write " ++ "mpt_diag_read_buffer_t data @ %p\n", ioc->name, ++ __func__, diag_data); ++ return -EFAULT; ++ } ++ ++ if ((karg.flags & MPT2_FLAGS_REREGISTER) == 0) ++ return 0; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: Reregister " ++ "buffer_type(0x%02x)\n", ioc->name, __func__, buffer_type)); ++ if ((ioc->diag_buffer_status[buffer_type] & ++ MPT2_DIAG_BUFFER_IS_RELEASED) == 0) { ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "buffer_type(0x%02x) is still registered\n", ioc->name, ++ __func__, buffer_type)); ++ return 0; ++ } ++ /* Get a free request frame and save the message context. ++ */ ++ if (state == NON_BLOCKING && !mutex_trylock(&ioc->ctl_cmds.mutex)) ++ return -EAGAIN; ++ else if (mutex_lock_interruptible(&ioc->ctl_cmds.mutex)) ++ return -ERESTARTSYS; ++ ++ if (ioc->ctl_cmds.status != MPT2_CMD_NOT_USED) { ++ printk(MPT2SAS_ERR_FMT "%s: ctl_cmd in use\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->ctl_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ rc = 0; ++ ioc->ctl_cmds.status = MPT2_CMD_PENDING; ++ memset(ioc->ctl_cmds.reply, 0, ioc->reply_sz); ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ioc->ctl_cmds.smid = smid; ++ ++ mpi_request->Function = MPI2_FUNCTION_DIAG_BUFFER_POST; ++ mpi_request->BufferType = buffer_type; ++ mpi_request->BufferLength = ++ cpu_to_le32(ioc->diag_buffer_sz[buffer_type]); ++ mpi_request->BufferAddress = ++ cpu_to_le64(ioc->diag_buffer_dma[buffer_type]); ++ for (i = 0; i < MPT2_PRODUCT_SPECIFIC_DWORDS; i++) ++ mpi_request->ProductSpecific[i] = ++ cpu_to_le32(ioc->product_specific[buffer_type][i]); ++ ++ mpt2sas_base_put_smid_default(ioc, smid, mpi_request->VF_ID); ++ timeleft = wait_for_completion_timeout(&ioc->ctl_cmds.done, ++ MPT2_IOCTL_DEFAULT_TIMEOUT*HZ); ++ ++ if (!(ioc->ctl_cmds.status & MPT2_CMD_COMPLETE)) { ++ printk(MPT2SAS_ERR_FMT "%s: timeout\n", ioc->name, ++ __func__); ++ _debug_dump_mf(mpi_request, ++ sizeof(Mpi2DiagBufferPostRequest_t)/4); ++ if (!(ioc->ctl_cmds.status & MPT2_CMD_RESET)) ++ issue_reset = 1; ++ goto issue_host_reset; ++ } ++ ++ /* process the completed Reply Message Frame */ ++ if ((ioc->ctl_cmds.status & MPT2_CMD_REPLY_VALID) == 0) { ++ printk(MPT2SAS_ERR_FMT "%s: no reply message\n", ++ ioc->name, __func__); ++ rc = -EFAULT; ++ goto out; ++ } ++ ++ mpi_reply = ioc->ctl_cmds.reply; ++ ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; ++ ++ if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { ++ ioc->diag_buffer_status[buffer_type] |= ++ MPT2_DIAG_BUFFER_IS_REGISTERED; ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: success\n", ++ ioc->name, __func__)); ++ } else { ++ printk(MPT2SAS_DEBUG_FMT "%s: ioc_status(0x%04x) " ++ "log_info(0x%08x)\n", ioc->name, __func__, ++ ioc_status, mpi_reply->IOCLogInfo); ++ rc = -EFAULT; ++ } ++ ++ issue_host_reset: ++ if (issue_reset) ++ mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, ++ FORCE_BIG_HAMMER); ++ ++ out: ++ ++ ioc->ctl_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->ctl_cmds.mutex); ++ return rc; ++} ++ ++/** ++ * _ctl_ioctl_main - main ioctl entry point ++ * @file - (struct file) ++ * @cmd - ioctl opcode ++ * @arg - ++ */ ++static long ++_ctl_ioctl_main(struct file *file, unsigned int cmd, void __user *arg) ++{ ++ enum block_state state; ++ long ret = -EINVAL; ++ ++ state = (file->f_flags & O_NONBLOCK) ? NON_BLOCKING : ++ BLOCKING; ++ ++ switch (cmd) { ++ case MPT2IOCINFO: ++ if (_IOC_SIZE(cmd) == sizeof(struct mpt2_ioctl_iocinfo)) ++ ret = _ctl_getiocinfo(arg); ++ break; ++ case MPT2COMMAND: ++ { ++ struct mpt2_ioctl_command karg; ++ struct mpt2_ioctl_command __user *uarg; ++ struct MPT2SAS_ADAPTER *ioc; ++ ++ if (copy_from_user(&karg, arg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ ++ if (_ctl_verify_adapter(karg.hdr.ioc_number, &ioc) == -1 || ++ !ioc) ++ return -ENODEV; ++ ++ if (ioc->shost_recovery) ++ return -EAGAIN; ++ ++ if (_IOC_SIZE(cmd) == sizeof(struct mpt2_ioctl_command)) { ++ uarg = arg; ++ ret = _ctl_do_mpt_command(ioc, karg, &uarg->mf, state); ++ } ++ break; ++ } ++ case MPT2EVENTQUERY: ++ if (_IOC_SIZE(cmd) == sizeof(struct mpt2_ioctl_eventquery)) ++ ret = _ctl_eventquery(arg); ++ break; ++ case MPT2EVENTENABLE: ++ if (_IOC_SIZE(cmd) == sizeof(struct mpt2_ioctl_eventenable)) ++ ret = _ctl_eventenable(arg); ++ break; ++ case MPT2EVENTREPORT: ++ ret = _ctl_eventreport(arg); ++ break; ++ case MPT2HARDRESET: ++ if (_IOC_SIZE(cmd) == sizeof(struct mpt2_ioctl_diag_reset)) ++ ret = _ctl_do_reset(arg); ++ break; ++ case MPT2BTDHMAPPING: ++ if (_IOC_SIZE(cmd) == sizeof(struct mpt2_ioctl_btdh_mapping)) ++ ret = _ctl_btdh_mapping(arg); ++ break; ++ case MPT2DIAGREGISTER: ++ if (_IOC_SIZE(cmd) == sizeof(struct mpt2_diag_register)) ++ ret = _ctl_diag_register(arg, state); ++ break; ++ case MPT2DIAGUNREGISTER: ++ if (_IOC_SIZE(cmd) == sizeof(struct mpt2_diag_unregister)) ++ ret = _ctl_diag_unregister(arg); ++ break; ++ case MPT2DIAGQUERY: ++ if (_IOC_SIZE(cmd) == sizeof(struct mpt2_diag_query)) ++ ret = _ctl_diag_query(arg); ++ break; ++ case MPT2DIAGRELEASE: ++ if (_IOC_SIZE(cmd) == sizeof(struct mpt2_diag_release)) ++ ret = _ctl_diag_release(arg, state); ++ break; ++ case MPT2DIAGREADBUFFER: ++ if (_IOC_SIZE(cmd) == sizeof(struct mpt2_diag_read_buffer)) ++ ret = _ctl_diag_read_buffer(arg, state); ++ break; ++ default: ++ { ++ struct mpt2_ioctl_command karg; ++ struct MPT2SAS_ADAPTER *ioc; ++ ++ if (copy_from_user(&karg, arg, sizeof(karg))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ ++ if (_ctl_verify_adapter(karg.hdr.ioc_number, &ioc) == -1 || ++ !ioc) ++ return -ENODEV; ++ ++ dctlprintk(ioc, printk(MPT2SAS_DEBUG_FMT ++ "unsupported ioctl opcode(0x%08x)\n", ioc->name, cmd)); ++ break; ++ } ++ } ++ return ret; ++} ++ ++/** ++ * _ctl_ioctl - main ioctl entry point (unlocked) ++ * @file - (struct file) ++ * @cmd - ioctl opcode ++ * @arg - ++ */ ++static long ++_ctl_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ long ret; ++ lock_kernel(); ++ ret = _ctl_ioctl_main(file, cmd, (void __user *)arg); ++ unlock_kernel(); ++ return ret; ++} ++ ++#ifdef CONFIG_COMPAT ++/** ++ * _ctl_compat_mpt_command - convert 32bit pointers to 64bit. ++ * @file - (struct file) ++ * @cmd - ioctl opcode ++ * @arg - (struct mpt2_ioctl_command32) ++ * ++ * MPT2COMMAND32 - Handle 32bit applications running on 64bit os. ++ */ ++static long ++_ctl_compat_mpt_command(struct file *file, unsigned cmd, unsigned long arg) ++{ ++ struct mpt2_ioctl_command32 karg32; ++ struct mpt2_ioctl_command32 __user *uarg; ++ struct mpt2_ioctl_command karg; ++ struct MPT2SAS_ADAPTER *ioc; ++ enum block_state state; ++ ++ if (_IOC_SIZE(cmd) != sizeof(struct mpt2_ioctl_command32)) ++ return -EINVAL; ++ ++ uarg = (struct mpt2_ioctl_command32 __user *) arg; ++ ++ if (copy_from_user(&karg32, (char __user *)arg, sizeof(karg32))) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ return -EFAULT; ++ } ++ if (_ctl_verify_adapter(karg32.hdr.ioc_number, &ioc) == -1 || !ioc) ++ return -ENODEV; ++ ++ if (ioc->shost_recovery) ++ return -EAGAIN; ++ ++ memset(&karg, 0, sizeof(struct mpt2_ioctl_command)); ++ karg.hdr.ioc_number = karg32.hdr.ioc_number; ++ karg.hdr.port_number = karg32.hdr.port_number; ++ karg.hdr.max_data_size = karg32.hdr.max_data_size; ++ karg.timeout = karg32.timeout; ++ karg.max_reply_bytes = karg32.max_reply_bytes; ++ karg.data_in_size = karg32.data_in_size; ++ karg.data_out_size = karg32.data_out_size; ++ karg.max_sense_bytes = karg32.max_sense_bytes; ++ karg.data_sge_offset = karg32.data_sge_offset; ++ memcpy(&karg.reply_frame_buf_ptr, &karg32.reply_frame_buf_ptr, ++ sizeof(uint32_t)); ++ memcpy(&karg.data_in_buf_ptr, &karg32.data_in_buf_ptr, ++ sizeof(uint32_t)); ++ memcpy(&karg.data_out_buf_ptr, &karg32.data_out_buf_ptr, ++ sizeof(uint32_t)); ++ memcpy(&karg.sense_data_ptr, &karg32.sense_data_ptr, ++ sizeof(uint32_t)); ++ state = (file->f_flags & O_NONBLOCK) ? NON_BLOCKING : BLOCKING; ++ return _ctl_do_mpt_command(ioc, karg, &uarg->mf, state); ++} ++ ++/** ++ * _ctl_ioctl_compat - main ioctl entry point (compat) ++ * @file - ++ * @cmd - ++ * @arg - ++ * ++ * This routine handles 32 bit applications in 64bit os. ++ */ ++static long ++_ctl_ioctl_compat(struct file *file, unsigned cmd, unsigned long arg) ++{ ++ long ret; ++ lock_kernel(); ++ if (cmd == MPT2COMMAND32) ++ ret = _ctl_compat_mpt_command(file, cmd, arg); ++ else ++ ret = _ctl_ioctl_main(file, cmd, (void __user *)arg); ++ unlock_kernel(); ++ return ret; ++} ++#endif ++ ++/* scsi host attributes */ ++ ++/** ++ * _ctl_version_fw_show - firmware version ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_version_fw_show(struct device *cdev, struct device_attribute *attr, ++ char *buf) ++#else ++static ssize_t ++_ctl_version_fw_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ return snprintf(buf, PAGE_SIZE, "%02d.%02d.%02d.%02d\n", ++ (ioc->facts.FWVersion.Word & 0xFF000000) >> 24, ++ (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16, ++ (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, ++ ioc->facts.FWVersion.Word & 0x000000FF); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(version_fw, S_IRUGO, _ctl_version_fw_show, NULL); ++#else ++static CLASS_DEVICE_ATTR(version_fw, S_IRUGO, _ctl_version_fw_show, NULL); ++#endif ++ ++/** ++ * _ctl_version_bios_show - bios version ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_version_bios_show(struct device *cdev, struct device_attribute *attr, ++ char *buf) ++#else ++static ssize_t ++_ctl_version_bios_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ u32 version = le32_to_cpu(ioc->bios_pg3.BiosVersion); ++ ++ return snprintf(buf, PAGE_SIZE, "%02d.%02d.%02d.%02d\n", ++ (version & 0xFF000000) >> 24, ++ (version & 0x00FF0000) >> 16, ++ (version & 0x0000FF00) >> 8, ++ version & 0x000000FF); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(version_bios, S_IRUGO, _ctl_version_bios_show, NULL); ++#else ++static CLASS_DEVICE_ATTR(version_bios, S_IRUGO, _ctl_version_bios_show, NULL); ++#endif ++ ++/** ++ * _ctl_version_mpi_show - MPI (message passing interface) version ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_version_mpi_show(struct device *cdev, struct device_attribute *attr, ++ char *buf) ++#else ++static ssize_t ++_ctl_version_mpi_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ return snprintf(buf, PAGE_SIZE, "%03x.%02x\n", ++ ioc->facts.MsgVersion, ioc->facts.HeaderVersion >> 8); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(version_mpi, S_IRUGO, _ctl_version_mpi_show, NULL); ++#else ++static CLASS_DEVICE_ATTR(version_mpi, S_IRUGO, _ctl_version_mpi_show, NULL); ++#endif ++ ++/** ++ * _ctl_version_product_show - product name ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_version_product_show(struct device *cdev, struct device_attribute *attr, ++ char *buf) ++#else ++static ssize_t ++_ctl_version_product_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ return snprintf(buf, 16, "%s\n", ioc->manu_pg0.ChipName); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(version_product, S_IRUGO, ++ _ctl_version_product_show, NULL); ++#else ++static CLASS_DEVICE_ATTR(version_product, S_IRUGO, ++ _ctl_version_product_show, NULL); ++#endif ++ ++/** ++ * _ctl_version_nvdata_persistent_show - ndvata persistent version ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_version_nvdata_persistent_show(struct device *cdev, ++ struct device_attribute *attr, char *buf) ++#else ++static ssize_t ++_ctl_version_nvdata_persistent_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ return snprintf(buf, PAGE_SIZE, "%02xh\n", ++ le16_to_cpu(ioc->iounit_pg0.NvdataVersionPersistent.Word)); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(version_nvdata_persistent, S_IRUGO, ++ _ctl_version_nvdata_persistent_show, NULL); ++#else ++static CLASS_DEVICE_ATTR(version_nvdata_persistent, S_IRUGO, ++ _ctl_version_nvdata_persistent_show, NULL); ++#endif ++ ++/** ++ * _ctl_version_nvdata_default_show - nvdata default version ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_version_nvdata_default_show(struct device *cdev, struct device_attribute ++ *attr, char *buf) ++#else ++static ssize_t ++_ctl_version_nvdata_default_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ return snprintf(buf, PAGE_SIZE, "%02xh\n", ++ le16_to_cpu(ioc->iounit_pg0.NvdataVersionDefault.Word)); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(version_nvdata_default, S_IRUGO, ++ _ctl_version_nvdata_default_show, NULL); ++#else ++static CLASS_DEVICE_ATTR(version_nvdata_default, S_IRUGO, ++ _ctl_version_nvdata_default_show, NULL); ++#endif ++ ++/** ++ * _ctl_board_name_show - board name ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_board_name_show(struct device *cdev, struct device_attribute *attr, ++ char *buf) ++#else ++static ssize_t ++_ctl_board_name_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ return snprintf(buf, 16, "%s\n", ioc->manu_pg0.BoardName); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(board_name, S_IRUGO, _ctl_board_name_show, NULL); ++#else ++static CLASS_DEVICE_ATTR(board_name, S_IRUGO, _ctl_board_name_show, NULL); ++#endif ++ ++/** ++ * _ctl_board_assembly_show - board assembly name ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_board_assembly_show(struct device *cdev, struct device_attribute *attr, ++ char *buf) ++#else ++static ssize_t ++_ctl_board_assembly_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ return snprintf(buf, 16, "%s\n", ioc->manu_pg0.BoardAssembly); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(board_assembly, S_IRUGO, ++ _ctl_board_assembly_show, NULL); ++#else ++static CLASS_DEVICE_ATTR(board_assembly, S_IRUGO, ++ _ctl_board_assembly_show, NULL); ++#endif ++ ++/** ++ * _ctl_board_tracer_show - board tracer number ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_board_tracer_show(struct device *cdev, struct device_attribute *attr, ++ char *buf) ++#else ++static ssize_t ++_ctl_board_tracer_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ return snprintf(buf, 16, "%s\n", ioc->manu_pg0.BoardTracerNumber); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(board_tracer, S_IRUGO, ++ _ctl_board_tracer_show, NULL); ++#else ++static CLASS_DEVICE_ATTR(board_tracer, S_IRUGO, ++ _ctl_board_tracer_show, NULL); ++#endif ++ ++/** ++ * _ctl_io_delay_show - io missing delay ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * This is for firmware implemention for deboucing device ++ * removal events. ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_io_delay_show(struct device *cdev, struct device_attribute *attr, ++ char *buf) ++#else ++static ssize_t ++_ctl_io_delay_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ return snprintf(buf, PAGE_SIZE, "%02d\n", ioc->io_missing_delay); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(io_delay, S_IRUGO, ++ _ctl_io_delay_show, NULL); ++#else ++static CLASS_DEVICE_ATTR(io_delay, S_IRUGO, ++ _ctl_io_delay_show, NULL); ++#endif ++ ++/** ++ * _ctl_device_delay_show - device missing delay ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * This is for firmware implemention for deboucing device ++ * removal events. ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_device_delay_show(struct device *cdev, struct device_attribute *attr, ++ char *buf) ++#else ++static ssize_t ++_ctl_device_delay_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ return snprintf(buf, PAGE_SIZE, "%02d\n", ioc->device_missing_delay); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(device_delay, S_IRUGO, ++ _ctl_device_delay_show, NULL); ++#else ++static CLASS_DEVICE_ATTR(device_delay, S_IRUGO, ++ _ctl_device_delay_show, NULL); ++#endif ++ ++/** ++ * _ctl_fw_queue_depth_show - global credits ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * This is firmware queue depth limit ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_fw_queue_depth_show(struct device *cdev, struct device_attribute *attr, ++ char *buf) ++#else ++static ssize_t ++_ctl_fw_queue_depth_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ return snprintf(buf, PAGE_SIZE, "%02d\n", ioc->facts.RequestCredit); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(fw_queue_depth, S_IRUGO, ++ _ctl_fw_queue_depth_show, NULL); ++#else ++static CLASS_DEVICE_ATTR(fw_queue_depth, S_IRUGO, ++ _ctl_fw_queue_depth_show, NULL); ++#endif ++ ++/** ++ * _ctl_sas_address_show - sas address ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * This is the controller sas address ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_host_sas_address_show(struct device *cdev, struct device_attribute *attr, ++ char *buf) ++#else ++static ssize_t ++_ctl_host_sas_address_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ return snprintf(buf, PAGE_SIZE, "0x%016llx\n", ++ (unsigned long long)ioc->sas_hba.sas_address); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(host_sas_address, S_IRUGO, ++ _ctl_host_sas_address_show, NULL); ++#else ++static CLASS_DEVICE_ATTR(host_sas_address, S_IRUGO, ++ _ctl_host_sas_address_show, NULL); ++#endif ++ ++/** ++ * _ctl_logging_level_show - logging level ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * A sysfs 'read/write' shost attribute. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_logging_level_show(struct device *cdev, struct device_attribute *attr, ++ char *buf) ++#else ++static ssize_t ++_ctl_logging_level_show(struct class_device *cdev, char *buf) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ ++ return snprintf(buf, PAGE_SIZE, "%08xh\n", ioc->logging_level); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static ssize_t ++_ctl_logging_level_store(struct device *cdev, struct device_attribute *attr, ++ const char *buf, size_t count) ++#else ++static ssize_t ++_ctl_logging_level_store(struct class_device *cdev, const char *buf, ++ size_t count) ++#endif ++{ ++ struct Scsi_Host *shost = class_to_shost(cdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ int val = 0; ++ ++ if (sscanf(buf, "%x", &val) != 1) ++ return -EINVAL; ++ ++ ioc->logging_level = val; ++ printk(MPT2SAS_INFO_FMT "logging_level=%08xh\n", ioc->name, ++ ioc->logging_level); ++ return strlen(buf); ++} ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++static DEVICE_ATTR(logging_level, S_IRUGO | S_IWUSR, ++ _ctl_logging_level_show, _ctl_logging_level_store); ++#else ++static CLASS_DEVICE_ATTR(logging_level, S_IRUGO | S_IWUSR, ++ _ctl_logging_level_show, _ctl_logging_level_store); ++#endif ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)) ++struct device_attribute *mpt2sas_host_attrs[] = { ++ &dev_attr_version_fw, ++ &dev_attr_version_bios, ++ &dev_attr_version_mpi, ++ &dev_attr_version_product, ++ &dev_attr_version_nvdata_persistent, ++ &dev_attr_version_nvdata_default, ++ &dev_attr_board_name, ++ &dev_attr_board_assembly, ++ &dev_attr_board_tracer, ++ &dev_attr_io_delay, ++ &dev_attr_device_delay, ++ &dev_attr_logging_level, ++ &dev_attr_fw_queue_depth, ++ &dev_attr_host_sas_address, ++ NULL, ++}; ++#else ++struct class_device_attribute *mpt2sas_host_attrs[] = { ++ &class_device_attr_version_fw, ++ &class_device_attr_version_bios, ++ &class_device_attr_version_mpi, ++ &class_device_attr_version_product, ++ &class_device_attr_version_nvdata_persistent, ++ &class_device_attr_version_nvdata_default, ++ &class_device_attr_board_name, ++ &class_device_attr_board_assembly, ++ &class_device_attr_board_tracer, ++ &class_device_attr_io_delay, ++ &class_device_attr_device_delay, ++ &class_device_attr_logging_level, ++ &class_device_attr_fw_queue_depth, ++ &class_device_attr_host_sas_address, ++ NULL, ++}; ++#endif ++ ++/* device attributes */ ++ ++/** ++ * _ctl_device_sas_address_show - sas address ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * This is the sas address for the target ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++static ssize_t ++_ctl_device_sas_address_show(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ struct scsi_device *sdev = to_scsi_device(dev); ++ struct MPT2SAS_DEVICE *sas_device_priv_data = sdev->hostdata; ++ ++ return snprintf(buf, PAGE_SIZE, "0x%016llx\n", ++ (unsigned long long)sas_device_priv_data->sas_target->sas_address); ++} ++static DEVICE_ATTR(sas_address, S_IRUGO, _ctl_device_sas_address_show, NULL); ++ ++/** ++ * _ctl_device_handle_show - device handle ++ * @cdev - pointer to embedded class device ++ * @buf - the buffer returned ++ * ++ * This is the firmware assigned device handle ++ * ++ * A sysfs 'read-only' shost attribute. ++ */ ++static ssize_t ++_ctl_device_handle_show(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ struct scsi_device *sdev = to_scsi_device(dev); ++ struct MPT2SAS_DEVICE *sas_device_priv_data = sdev->hostdata; ++ ++ return snprintf(buf, PAGE_SIZE, "0x%04x\n", ++ sas_device_priv_data->sas_target->handle); ++} ++static DEVICE_ATTR(sas_device_handle, S_IRUGO, _ctl_device_handle_show, NULL); ++ ++struct device_attribute *mpt2sas_dev_attrs[] = { ++ &dev_attr_sas_address, ++ &dev_attr_sas_device_handle, ++ NULL, ++}; ++ ++static struct file_operations ctl_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = _ctl_ioctl, ++ .release = _ctl_release, ++ .poll = _ctl_poll, ++ .fasync = _ctl_fasync, ++#ifdef CONFIG_COMPAT ++ .compat_ioctl = _ctl_ioctl_compat, ++#endif ++}; ++ ++static struct miscdevice ctl_dev = { ++ .minor = MPT2SAS_MINOR, ++ .name = MPT2SAS_DEV_NAME, ++ .fops = &ctl_fops, ++}; ++ ++/** ++ * mpt2sas_ctl_init - main entry point for ctl. ++ * ++ */ ++void ++mpt2sas_ctl_init(void) ++{ ++ async_queue = NULL; ++ if (misc_register(&ctl_dev) < 0) ++ printk(KERN_ERR "%s can't register misc device [minor=%d]\n", ++ MPT2SAS_DRIVER_NAME, MPT2SAS_MINOR); ++ ++ init_waitqueue_head(&ctl_poll_wait); ++} ++ ++/** ++ * mpt2sas_ctl_exit - exit point for ctl ++ * ++ */ ++void ++mpt2sas_ctl_exit(void) ++{ ++ struct MPT2SAS_ADAPTER *ioc; ++ int i; ++ ++ list_for_each_entry(ioc, &mpt2sas_ioc_list, list) { ++ ++ /* free memory associated to diag buffers */ ++ for (i = 0; i < MPI2_DIAG_BUF_TYPE_COUNT; i++) { ++ if (!ioc->diag_buffer[i]) ++ continue; ++ pci_free_consistent(ioc->pdev, ioc->diag_buffer_sz[i], ++ ioc->diag_buffer[i], ioc->diag_buffer_dma[i]); ++ ioc->diag_buffer[i] = NULL; ++ ioc->diag_buffer_status[i] = 0; ++ } ++ ++ kfree(ioc->event_log); ++ } ++ misc_deregister(&ctl_dev); ++} ++ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpt2sas_ctl.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpt2sas_ctl.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,429 @@ ++/* ++ * Management Module Support for MPT (Message Passing Technology) based ++ * controllers ++ * ++ * This code is based on drivers/scsi/mpt2sas/mpt2_ctl.h ++ * Copyright (C) 2007-2008 LSI Corporation ++ * (mailto:DL-MPTFusionLinux@lsi.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * NO WARRANTY ++ * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR ++ * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT ++ * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is ++ * solely responsible for determining the appropriateness of using and ++ * distributing the Program and assumes all risks associated with its ++ * exercise of rights under this Agreement, including but not limited to ++ * the risks and costs of program errors, damage to or loss of data, ++ * programs or equipment, and unavailability or interruption of operations. ++ ++ * DISCLAIMER OF LIABILITY ++ * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR ++ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED ++ * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ++ ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, ++ * USA. ++ */ ++ ++#ifndef MPT2SAS_CTL_H_INCLUDED ++#define MPT2SAS_CTL_H_INCLUDED ++ ++#ifdef __KERNEL__ ++#include ++#endif ++ ++/** ++ * NOTE ++ * FWDOWNLOAD - PR is let me know if we need to implement this ++ * DIAGBUFFER - PR said hold off ++ */ ++ ++/** ++ * HACK - changeme (MPT_MINOR = 220 ) ++ */ ++#ifndef MPT2SAS_MINOR ++#define MPT2SAS_MINOR (MPT_MINOR + 1) ++#endif ++#define MPT2SAS_DEV_NAME "mpt2ctl" ++#define MPT2_MAGIC_NUMBER 'L' ++#define MPT2_IOCTL_DEFAULT_TIMEOUT (10) /* in seconds */ ++ ++/** ++ * IOCTL opcodes ++ */ ++#define MPT2IOCINFO _IOWR(MPT2_MAGIC_NUMBER, 17, \ ++ struct mpt2_ioctl_iocinfo) ++#define MPT2COMMAND _IOWR(MPT2_MAGIC_NUMBER, 20, \ ++ struct mpt2_ioctl_command) ++#ifdef CONFIG_COMPAT ++#define MPT2COMMAND32 _IOWR(MPT2_MAGIC_NUMBER, 20, \ ++ struct mpt2_ioctl_command32) ++#endif ++#define MPT2EVENTQUERY _IOWR(MPT2_MAGIC_NUMBER, 21, \ ++ struct mpt2_ioctl_eventquery) ++#define MPT2EVENTENABLE _IOWR(MPT2_MAGIC_NUMBER, 22, \ ++ struct mpt2_ioctl_eventenable) ++#define MPT2EVENTREPORT _IOWR(MPT2_MAGIC_NUMBER, 23, \ ++ struct mpt2_ioctl_eventreport) ++#define MPT2HARDRESET _IOWR(MPT2_MAGIC_NUMBER, 24, \ ++ struct mpt2_ioctl_diag_reset) ++#define MPT2BTDHMAPPING _IOWR(MPT2_MAGIC_NUMBER, 31, \ ++ struct mpt2_ioctl_btdh_mapping) ++ ++/* diag buffer support */ ++#define MPT2DIAGREGISTER _IOWR(MPT2_MAGIC_NUMBER, 26, \ ++ struct mpt2_diag_register) ++#define MPT2DIAGRELEASE _IOWR(MPT2_MAGIC_NUMBER, 27, \ ++ struct mpt2_diag_release) ++#define MPT2DIAGUNREGISTER _IOWR(MPT2_MAGIC_NUMBER, 28, \ ++ struct mpt2_diag_unregister) ++#define MPT2DIAGQUERY _IOWR(MPT2_MAGIC_NUMBER, 29, \ ++ struct mpt2_diag_query) ++#define MPT2DIAGREADBUFFER _IOWR(MPT2_MAGIC_NUMBER, 30, \ ++ struct mpt2_diag_read_buffer) ++ ++/** ++ * struct mpt2_ioctl_header - main header structure ++ * @ioc_number - IOC unit number ++ * @port_number - IOC port number ++ * @max_data_size - maximum number bytes to transfer on read ++ */ ++struct mpt2_ioctl_header { ++ uint32_t ioc_number; ++ uint32_t port_number; ++ uint32_t max_data_size; ++}; ++ ++/** ++ * struct mpt2_ioctl_diag_reset - diagnostic reset ++ * @hdr - generic header ++ */ ++struct mpt2_ioctl_diag_reset { ++ struct mpt2_ioctl_header hdr; ++}; ++ ++ ++/** ++ * struct mpt2_ioctl_pci_info - pci device info ++ * @device - pci device id ++ * @function - pci function id ++ * @bus - pci bus id ++ * @segment_id - pci segment id ++ */ ++struct mpt2_ioctl_pci_info { ++ union { ++ struct { ++ uint32_t device:5; ++ uint32_t function:3; ++ uint32_t bus:24; ++ } bits; ++ uint32_t word; ++ } u; ++ uint32_t segment_id; ++}; ++ ++ ++#define MPT2_IOCTL_INTERFACE_SCSI (0x00) ++#define MPT2_IOCTL_INTERFACE_FC (0x01) ++#define MPT2_IOCTL_INTERFACE_FC_IP (0x02) ++#define MPT2_IOCTL_INTERFACE_SAS (0x03) ++#define MPT2_IOCTL_INTERFACE_SAS2 (0x04) ++#define MPT2_IOCTL_VERSION_LENGTH (32) ++ ++/** ++ * struct mpt2_ioctl_iocinfo - generic controller info ++ * @hdr - generic header ++ * @adapter_type - type of adapter (spi, fc, sas) ++ * @port_number - port number ++ * @pci_id - PCI Id ++ * @hw_rev - hardware revision ++ * @sub_system_device - PCI subsystem Device ID ++ * @sub_system_vendor - PCI subsystem Vendor ID ++ * @rsvd0 - reserved ++ * @firmware_version - firmware version ++ * @bios_version - BIOS version ++ * @driver_version - driver version - 32 ASCII characters ++ * @rsvd1 - reserved ++ * @scsi_id - scsi id of adapter 0 ++ * @rsvd2 - reserved ++ * @pci_information - pci info (2nd revision) ++ */ ++struct mpt2_ioctl_iocinfo { ++ struct mpt2_ioctl_header hdr; ++ uint32_t adapter_type; ++ uint32_t port_number; ++ uint32_t pci_id; ++ uint32_t hw_rev; ++ uint32_t subsystem_device; ++ uint32_t subsystem_vendor; ++ uint32_t rsvd0; ++ uint32_t firmware_version; ++ uint32_t bios_version; ++ uint8_t driver_version[MPT2_IOCTL_VERSION_LENGTH]; ++ uint8_t rsvd1; ++ uint8_t scsi_id; ++ uint16_t rsvd2; ++ struct mpt2_ioctl_pci_info pci_information; ++}; ++ ++ ++/* number of event log entries */ ++#define MPT2SAS_CTL_EVENT_LOG_SIZE (50) ++ ++/** ++ * struct mpt2_ioctl_eventquery - query event count and type ++ * @hdr - generic header ++ * @event_entries - number of events returned by get_event_report ++ * @rsvd - reserved ++ * @event_types - type of events currently being captured ++ */ ++struct mpt2_ioctl_eventquery { ++ struct mpt2_ioctl_header hdr; ++ uint16_t event_entries; ++ uint16_t rsvd; ++ uint32_t event_types[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; ++}; ++ ++/** ++ * struct mpt2_ioctl_eventenable - enable/disable event capturing ++ * @hdr - generic header ++ * @event_types - toggle off/on type of events to be captured ++ */ ++struct mpt2_ioctl_eventenable { ++ struct mpt2_ioctl_header hdr; ++ uint32_t event_types[4]; ++}; ++ ++#define MPT2_EVENT_DATA_SIZE (192) ++/** ++ * struct MPT2_IOCTL_EVENTS - ++ * @event - the event that was reported ++ * @context - unique value for each event assigned by driver ++ * @data - event data returned in fw reply message ++ */ ++struct MPT2_IOCTL_EVENTS { ++ uint32_t event; ++ uint32_t context; ++ uint8_t data[MPT2_EVENT_DATA_SIZE]; ++}; ++ ++/** ++ * struct mpt2_ioctl_eventreport - returing event log ++ * @hdr - generic header ++ * @event_data - (see struct MPT2_IOCTL_EVENTS) ++ */ ++struct mpt2_ioctl_eventreport { ++ struct mpt2_ioctl_header hdr; ++ struct MPT2_IOCTL_EVENTS event_data[1]; ++}; ++ ++/** ++ * struct mpt2_ioctl_command - generic mpt firmware passthru ioclt ++ * @hdr - generic header ++ * @timeout - command timeout in seconds. (if zero then use driver default ++ * value). ++ * @reply_frame_buf_ptr - reply location ++ * @data_in_buf_ptr - destination for read ++ * @data_out_buf_ptr - data source for write ++ * @sense_data_ptr - sense data location ++ * @max_reply_bytes - maximum number of reply bytes to be sent to app. ++ * @data_in_size - number bytes for data transfer in (read) ++ * @data_out_size - number bytes for data transfer out (write) ++ * @max_sense_bytes - maximum number of bytes for auto sense buffers ++ * @data_sge_offset - offset in words from the start of the request message to ++ * the first SGL ++ * @mf[1]; ++ */ ++struct mpt2_ioctl_command { ++ struct mpt2_ioctl_header hdr; ++ uint32_t timeout; ++ void __user *reply_frame_buf_ptr; ++ void __user *data_in_buf_ptr; ++ void __user *data_out_buf_ptr; ++ void __user *sense_data_ptr; ++ uint32_t max_reply_bytes; ++ uint32_t data_in_size; ++ uint32_t data_out_size; ++ uint32_t max_sense_bytes; ++ uint32_t data_sge_offset; ++ uint8_t mf[1]; ++}; ++ ++#ifdef CONFIG_COMPAT ++struct mpt2_ioctl_command32 { ++ struct mpt2_ioctl_header hdr; ++ uint32_t timeout; ++ uint32_t reply_frame_buf_ptr; ++ uint32_t data_in_buf_ptr; ++ uint32_t data_out_buf_ptr; ++ uint32_t sense_data_ptr; ++ uint32_t max_reply_bytes; ++ uint32_t data_in_size; ++ uint32_t data_out_size; ++ uint32_t max_sense_bytes; ++ uint32_t data_sge_offset; ++ uint8_t mf[1]; ++}; ++#endif ++ ++/** ++ * struct mpt2_ioctl_btdh_mapping - mapping info ++ * @hdr - generic header ++ * @id - target device identification number ++ * @bus - SCSI bus number that the target device exists on ++ * @handle - device handle for the target device ++ * @rsvd - reserved ++ * ++ * To obtain a bus/id the application sets ++ * handle to valid handle, and bus/id to 0xFFFF. ++ * ++ * To obtain the device handle the application sets ++ * bus/id valid value, and the handle to 0xFFFF. ++ */ ++struct mpt2_ioctl_btdh_mapping { ++ struct mpt2_ioctl_header hdr; ++ uint32_t id; ++ uint32_t bus; ++ uint16_t handle; ++ uint16_t rsvd; ++}; ++ ++ ++/* status bits for ioc->diag_buffer_status */ ++#define MPT2_DIAG_BUFFER_IS_REGISTERED (0x01) ++#define MPT2_DIAG_BUFFER_IS_RELEASED (0x02) ++#define MPT2_DIAG_BUFFER_IS_DIAG_RESET (0x04) ++ ++/* application flags for mpt2_diag_register, mpt2_diag_query */ ++#define MPT2_APP_FLAGS_APP_OWNED (0x0001) ++#define MPT2_APP_FLAGS_BUFFER_VALID (0x0002) ++#define MPT2_APP_FLAGS_FW_BUFFER_ACCESS (0x0004) ++ ++/* flags for mpt2_diag_read_buffer */ ++#define MPT2_FLAGS_REREGISTER (0x0001) ++ ++#define MPT2_PRODUCT_SPECIFIC_DWORDS 23 ++ ++/** ++ * struct mpt2_diag_register - application register with driver ++ * @hdr - generic header ++ * @reserved - ++ * @buffer_type - specifies either TRACE or SNAPSHOT ++ * @application_flags - misc flags ++ * @diagnostic_flags - specifies flags affecting command processing ++ * @product_specific - product specific information ++ * @requested_buffer_size - buffers size in bytes ++ * @unique_id - tag specified by application that is used to signal ownership ++ * of the buffer. ++ * ++ * This will allow the driver to setup any required buffers that will be ++ * needed by firmware to communicate with the driver. ++ */ ++struct mpt2_diag_register { ++ struct mpt2_ioctl_header hdr; ++ uint8_t reserved; ++ uint8_t buffer_type; ++ uint16_t application_flags; ++ uint32_t diagnostic_flags; ++ uint32_t product_specific[MPT2_PRODUCT_SPECIFIC_DWORDS]; ++ uint32_t requested_buffer_size; ++ uint32_t unique_id; ++}; ++ ++/** ++ * struct mpt2_diag_unregister - application unregister with driver ++ * @hdr - generic header ++ * @unique_id - tag uniquely identifies the buffer to be unregistered ++ * ++ * This will allow the driver to cleanup any memory allocated for diag ++ * messages and to free up any resources. ++ */ ++struct mpt2_diag_unregister { ++ struct mpt2_ioctl_header hdr; ++ uint32_t unique_id; ++}; ++ ++/** ++ * struct mpt2_diag_query - query relevant info associated with diag buffers ++ * @hdr - generic header ++ * @reserved - ++ * @buffer_type - specifies either TRACE or SNAPSHOT ++ * @application_flags - misc flags ++ * @diagnostic_flags - specifies flags affecting command processing ++ * @product_specific - product specific information ++ * @total_buffer_size - diag buffer size in bytes ++ * @driver_added_buffer_size - size of extra space appended to end of buffer ++ * @unique_id - unique id associated with this buffer. ++ * ++ * The application will send only buffer_type and unique_id. Driver will ++ * inspect unique_id first, if valid, fill in all the info. If unique_id is ++ * 0x00, the driver will return info specified by Buffer Type. ++ */ ++struct mpt2_diag_query { ++ struct mpt2_ioctl_header hdr; ++ uint8_t reserved; ++ uint8_t buffer_type; ++ uint16_t application_flags; ++ uint32_t diagnostic_flags; ++ uint32_t product_specific[MPT2_PRODUCT_SPECIFIC_DWORDS]; ++ uint32_t total_buffer_size; ++ uint32_t driver_added_buffer_size; ++ uint32_t unique_id; ++}; ++ ++/** ++ * struct mpt2_diag_release - request to send Diag Release Message to firmware ++ * @hdr - generic header ++ * @unique_id - tag uniquely identifies the buffer to be released ++ * ++ * This allows ownership of the specified buffer to returned to the driver, ++ * allowing an application to read the buffer without fear that firmware is ++ * overwritting information in the buffer. ++ */ ++struct mpt2_diag_release { ++ struct mpt2_ioctl_header hdr; ++ uint32_t unique_id; ++}; ++ ++/** ++ * struct mpt2_diag_read_buffer - request for copy of the diag buffer ++ * @hdr - generic header ++ * @status - ++ * @reserved - ++ * @flags - misc flags ++ * @starting_offset - starting offset within drivers buffer where to start ++ * reading data at into the specified application buffer ++ * @bytes_to_read - number of bytes to copy from the drivers buffer into the ++ * application buffer starting at starting_offset. ++ * @unique_id - unique id associated with this buffer. ++ * @diagnostic_data - data payload ++ */ ++struct mpt2_diag_read_buffer { ++ struct mpt2_ioctl_header hdr; ++ uint8_t status; ++ uint8_t reserved; ++ uint16_t flags; ++ uint32_t starting_offset; ++ uint32_t bytes_to_read; ++ uint32_t unique_id; ++ uint32_t diagnostic_data[1]; ++}; ++ ++#endif /* MPT2SAS_CTL_H_INCLUDED */ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpt2sas_debug.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpt2sas_debug.h Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,181 @@ ++/* ++ * Logging Support for MPT (Message Passing Technology) based controllers ++ * ++ * This code is based on drivers/scsi/mpt2sas/mpt2_debug.c ++ * Copyright (C) 2007-2008 LSI Corporation ++ * (mailto:DL-MPTFusionLinux@lsi.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * NO WARRANTY ++ * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR ++ * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT ++ * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is ++ * solely responsible for determining the appropriateness of using and ++ * distributing the Program and assumes all risks associated with its ++ * exercise of rights under this Agreement, including but not limited to ++ * the risks and costs of program errors, damage to or loss of data, ++ * programs or equipment, and unavailability or interruption of operations. ++ ++ * DISCLAIMER OF LIABILITY ++ * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR ++ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED ++ * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ++ ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, ++ * USA. ++ */ ++ ++#ifndef MPT2SAS_DEBUG_H_INCLUDED ++#define MPT2SAS_DEBUG_H_INCLUDED ++ ++#define MPT_DEBUG 0x00000001 ++#define MPT_DEBUG_MSG_FRAME 0x00000002 ++#define MPT_DEBUG_SG 0x00000004 ++#define MPT_DEBUG_EVENTS 0x00000008 ++#define MPT_DEBUG_EVENT_WORK_TASK 0x00000010 ++#define MPT_DEBUG_INIT 0x00000020 ++#define MPT_DEBUG_EXIT 0x00000040 ++#define MPT_DEBUG_FAIL 0x00000080 ++#define MPT_DEBUG_TM 0x00000100 ++#define MPT_DEBUG_REPLY 0x00000200 ++#define MPT_DEBUG_HANDSHAKE 0x00000400 ++#define MPT_DEBUG_CONFIG 0x00000800 ++#define MPT_DEBUG_DL 0x00001000 ++#define MPT_DEBUG_RESET 0x00002000 ++#define MPT_DEBUG_SCSI 0x00004000 ++#define MPT_DEBUG_IOCTL 0x00008000 ++#define MPT_DEBUG_CSMISAS 0x00010000 ++#define MPT_DEBUG_SAS 0x00020000 ++#define MPT_DEBUG_TRANSPORT 0x00040000 ++#define MPT_DEBUG_TASK_SET_FULL 0x00080000 ++ ++#define MPT_DEBUG_TARGET_MODE 0x00100000 ++ ++ ++/* ++ * CONFIG_SCSI_MPT2SAS_LOGGING - enabled in Kconfig ++ */ ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++#define MPT_CHECK_LOGGING(IOC, CMD, BITS) \ ++{ \ ++ if (IOC->logging_level & BITS) \ ++ CMD; \ ++} ++#else ++#define MPT_CHECK_LOGGING(IOC, CMD, BITS) ++#endif /* CONFIG_SCSI_MPT2SAS_LOGGING */ ++ ++ ++/* ++ * debug macros ++ */ ++ ++#define dprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG) ++ ++#define dsgprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_SG) ++ ++#define devtprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_EVENTS) ++ ++#define dewtprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_EVENT_WORK_TASK) ++ ++#define dinitprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_INIT) ++ ++#define dexitprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_EXIT) ++ ++#define dfailprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_FAIL) ++ ++#define dtmprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_TM) ++ ++#define dreplyprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_REPLY) ++ ++#define dhsprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_HANDSHAKE) ++ ++#define dcprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_CONFIG) ++ ++#define ddlprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_DL) ++ ++#define drsprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_RESET) ++ ++#define dsprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_SCSI) ++ ++#define dctlprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_IOCTL) ++ ++#define dcsmisasprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_CSMISAS) ++ ++#define dsasprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_SAS) ++ ++#define dsastransport(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_SAS_WIDE) ++ ++#define dmfprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_MSG_FRAME) ++ ++#define dtsfprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_TASK_SET_FULL) ++ ++#define dtransportprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_TRANSPORT) ++ ++#define dTMprintk(IOC, CMD) \ ++ MPT_CHECK_LOGGING(IOC, CMD, MPT_DEBUG_TARGET_MODE) ++ ++/* inline functions for dumping debug data*/ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++/** ++ * _debug_dump_mf - print message frame contents ++ * @mpi_request: pointer to message frame ++ * @sz: number of dwords ++ */ ++static inline void ++_debug_dump_mf(void *mpi_request, int sz) ++{ ++ int i; ++ u32 *mfp = (u32 *)mpi_request; ++ ++ printk(KERN_INFO "mf:\n\t"); ++ for (i = 0; i < sz; i++) { ++ if (i && ((i % 8) == 0)) ++ printk("\n\t"); ++ printk("%08x ", le32_to_cpu(mfp[i])); ++ } ++ printk("\n"); ++} ++#else ++#define _debug_dump_mf(mpi_request, sz) ++#endif /* CONFIG_SCSI_MPT2SAS_LOGGING */ ++ ++#endif /* MPT2SAS_DEBUG_H_INCLUDED */ +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpt2sas_scsih.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpt2sas_scsih.c Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,7634 @@ ++/* ++ * Scsi Host Layer for MPT (Message Passing Technology) based controllers ++ * ++ * This code is based on drivers/scsi/mpt2sas/mpt2_scsih.c ++ * Copyright (C) 2007-2008 LSI Corporation ++ * (mailto:DL-MPTFusionLinux@lsi.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * NO WARRANTY ++ * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR ++ * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT ++ * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is ++ * solely responsible for determining the appropriateness of using and ++ * distributing the Program and assumes all risks associated with its ++ * exercise of rights under this Agreement, including but not limited to ++ * the risks and costs of program errors, damage to or loss of data, ++ * programs or equipment, and unavailability or interruption of operations. ++ ++ * DISCLAIMER OF LIABILITY ++ * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR ++ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED ++ * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ++ ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, ++ * USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mpt2sas_base.h" ++ ++MODULE_AUTHOR(MPT2SAS_AUTHOR); ++MODULE_DESCRIPTION(MPT2SAS_DESCRIPTION); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(MPT2SAS_DRIVER_VERSION); ++ ++#define RAID_CHANNEL 1 ++ ++/* forward proto's */ ++static void _scsih_expander_node_remove(struct MPT2SAS_ADAPTER *ioc, ++ struct _sas_node *sas_expander); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) ++static void _firmware_event_work(struct work_struct *work); ++static void _firmware_event_work_delayed(struct work_struct *work); ++#else ++static void _firmware_event_work(void *arg); ++#endif ++ ++#if defined(EEDP_SUPPORT) ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) ++static enum device_responsive_state ++_scsih_read_capacity_16(struct MPT2SAS_ADAPTER *ioc, u16 handle, u32 lun, ++ void *data, u32 data_length); ++#endif ++#endif ++ ++#ifdef MPT2SAS_MULTIPATH ++static enum device_responsive_state ++_scsih_inquiry_vpd_sn(struct MPT2SAS_ADAPTER *ioc, u16 handle, void *data, ++ u32 data_length); ++#endif ++ ++static enum device_responsive_state ++_scsih_inquiry_vpd_supported_pages(struct MPT2SAS_ADAPTER *ioc, u16 handle, u32 lun, ++ void *data, u32 data_length); ++ ++/* global parameters */ ++LIST_HEAD(mpt2sas_ioc_list); ++ ++/* local parameters */ ++static u8 scsi_io_cb_idx = -1; ++static u8 tm_cb_idx = -1; ++static u8 ctl_cb_idx = -1; ++static u8 base_cb_idx = -1; ++static u8 transport_cb_idx = -1; ++static u8 scsih_cb_idx = -1; ++static u8 config_cb_idx = -1; ++static int mpt_ids; ++ ++/* command line options */ ++static u32 logging_level; ++MODULE_PARM_DESC(logging_level, " bits for enabling additional logging info " ++ "(default=0)"); ++ ++static int command_retry_count = 144; ++module_param(command_retry_count, int, 0); ++MODULE_PARM_DESC(command_retry_count, " Device discovery TUR command retry " ++ "count: (default=144)"); ++ ++/* scsi-mid layer global parmeter is max_report_luns, which is 511 */ ++#define MPT2SAS_MAX_LUN (16895) ++static int max_lun = MPT2SAS_MAX_LUN; ++module_param(max_lun, int, 0); ++MODULE_PARM_DESC(max_lun, " max lun, default=16895 "); ++ ++#ifdef MPT2SAS_MULTIPATH ++static int mpt2sas_multipath = -1; ++module_param(mpt2sas_multipath, int, 0); ++MODULE_PARM_DESC(mpt2sas_multipath, " enabling mulipath support for target " ++ "resets (default=0)"); ++#endif ++ ++#if (defined(CONFIG_SUSE_KERNEL) && defined(scsi_is_sas_phy_local)) || LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) ++#define MPT_WIDE_PORT_API 1 ++#define MPT_WIDE_PORT_API_PLUS 1 ++#endif ++ ++/** ++ * enum device_responsive_state - responsive state ++ * @DEVICE_READY: device is ready to be added ++ * @DEVICE_RETRY: device can be retried later ++ * @DEVICE_RETRY_UA: retry unit attentions ++ * @DEVICE_START_UNIT: requires start unit ++ * @DEVICE_ERROR: device reported some fatal error ++ * ++ * Look at _scsih_wait_for_device_to_become_ready() ++ * ++ */ ++enum device_responsive_state { ++ DEVICE_READY, ++ DEVICE_RETRY, ++ DEVICE_RETRY_UA, ++ DEVICE_START_UNIT, ++ DEVICE_ERROR, ++}; ++ ++/** ++ * struct sense_info - common structure for obtaining sense keys ++ * @skey: sense key ++ * @asc: additional sense code ++ * @ascq: additional sense code qualifier ++ */ ++struct sense_info { ++ u8 skey; ++ u8 asc; ++ u8 ascq; ++}; ++ ++#ifdef MPT2SAS_MULTIPATH ++/** ++ * struct mpt2sas_abort_task_set - abort task set ++ * @handle: device handle ++ * @lun: lun ++ */ ++struct mpt2sas_abort_task_set { ++ u16 handle; ++ u32 lun; ++}; ++#endif ++ ++#define MPT2SAS_ABRT_TASK_SET (0xFFFE) ++ ++/** ++ * struct fw_event_work - firmware event struct ++ * @list: link list framework ++ * @work: work object (ioc->fault_reset_work_q) ++ * @ioc: per adapter object ++ * @VF_ID: virtual function id ++ * @host_reset_handling: handling events during host reset ++ * @ignore: flag meaning this event has been marked to ignore ++ * @event: firmware event MPI2_EVENT_XXX defined in mpt2_ioc.h ++ * @event_data: reply event data payload follows ++ * @retries: number of times this event has been retried(for each device) ++ * ++ * This object stored on ioc->fw_event_list. ++ */ ++struct fw_event_work { ++ struct list_head list; ++ struct work_struct work; ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) ++ struct delayed_work delayed_work; ++ u8 delayed_work_active; ++#endif ++ struct MPT2SAS_ADAPTER *ioc; ++ u8 VF_ID; ++ u8 host_reset_handling; ++ u8 ignore; ++ u16 event; ++ void *event_data; ++ u8 *retries; ++}; ++ ++/** ++ * struct _scsi_io_transfer - scsi io transfer ++ * @handle: sas device handle (assigned by firmware) ++ * @is_raid: flag set for hidden raid components ++ * @dir: DMA_TO_DEVICE, DMA_FROM_DEVICE, ++ * @data_length: data transfer length ++ * @data_dma: dma pointer to data ++ * @sense: sense data ++ * @lun: lun number ++ * @cdb_length: cdb length ++ * @cdb: cdb contents ++ * @valid_reply: flag set for reply message ++ * @timeout: timeout for this command ++ * @sense_length: sense length ++ * @ioc_status: ioc status ++ * @scsi_state: scsi state ++ * @scsi_status: scsi staus ++ * @log_info: log information ++ * @transfer_length: data length transfer when there is a reply message ++ * ++ * Used for sending internal scsi commands to devices within this module. ++ * Refer to _scsi_send_scsi_io(). ++ */ ++struct _scsi_io_transfer { ++ u16 handle; ++ u8 is_raid; ++ enum dma_data_direction dir; ++ u32 data_length; ++ dma_addr_t data_dma; ++ u8 sense[SCSI_SENSE_BUFFERSIZE]; ++ u32 lun; ++ u8 cdb_length; ++ u8 cdb[32]; ++ u8 timeout; ++ u8 valid_reply; ++ /* the following bits are only valid when 'valid_reply = 1' */ ++ u32 sense_length; ++ u16 ioc_status; ++ u8 scsi_state; ++ u8 scsi_status; ++ u32 log_info; ++ u32 transfer_length; ++}; ++ ++/* ++ * The pci device ids are defined in mpi/mpi2_cnfg.h. ++ */ ++static struct pci_device_id scsih_pci_table[] = { ++ { MPI2_MFGPAGE_VENDORID_LSI, MPI2_MFGPAGE_DEVID_SAS2004, ++ PCI_ANY_ID, PCI_ANY_ID }, ++ /* Falcon ~ 2008*/ ++ { MPI2_MFGPAGE_VENDORID_LSI, MPI2_MFGPAGE_DEVID_SAS2008, ++ PCI_ANY_ID, PCI_ANY_ID }, ++ /* Liberator ~ 2108 */ ++ { MPI2_MFGPAGE_VENDORID_LSI, MPI2_MFGPAGE_DEVID_SAS2108_1, ++ PCI_ANY_ID, PCI_ANY_ID }, ++ { MPI2_MFGPAGE_VENDORID_LSI, MPI2_MFGPAGE_DEVID_SAS2108_2, ++ PCI_ANY_ID, PCI_ANY_ID }, ++ { MPI2_MFGPAGE_VENDORID_LSI, MPI2_MFGPAGE_DEVID_SAS2108_3, ++ PCI_ANY_ID, PCI_ANY_ID }, ++ { MPI2_MFGPAGE_VENDORID_LSI, MPI2_MFGPAGE_DEVID_SAS2116_1, ++ PCI_ANY_ID, PCI_ANY_ID }, ++ { MPI2_MFGPAGE_VENDORID_LSI, MPI2_MFGPAGE_DEVID_SAS2116_2, ++ PCI_ANY_ID, PCI_ANY_ID }, ++ {0} /* Terminating entry */ ++}; ++MODULE_DEVICE_TABLE(pci, scsih_pci_table); ++ ++/** ++ * _scsih_set_debug_level - global setting of ioc->logging_level. ++ * ++ * Note: The logging levels are defined in mpt2sas_debug.h. ++ */ ++static int ++_scsih_set_debug_level(const char *val, struct kernel_param *kp) ++{ ++ int ret = param_set_int(val, kp); ++ struct MPT2SAS_ADAPTER *ioc; ++ ++ if (ret) ++ return ret; ++ ++ printk(KERN_INFO "setting logging_level(0x%08x)\n", logging_level); ++ list_for_each_entry(ioc, &mpt2sas_ioc_list, list) ++ ioc->logging_level = logging_level; ++ return 0; ++} ++module_param_call(logging_level, _scsih_set_debug_level, param_get_int, ++ &logging_level, 0644); ++ ++/** ++ * _scsih_srch_boot_sas_address - search based on sas_address ++ * @sas_address: sas address ++ * @boot_device: boot device object from bios page 2 ++ * ++ * Returns 1 when there's a match, 0 means no match. ++ */ ++static inline int ++_scsih_srch_boot_sas_address(u64 sas_address, ++ Mpi2BootDeviceSasWwid_t *boot_device) ++{ ++ return (sas_address == le64_to_cpu(boot_device->SASAddress)) ? 1 : 0; ++} ++ ++/** ++ * _scsih_srch_boot_device_name - search based on device name ++ * @device_name: device name specified in INDENTIFY fram ++ * @boot_device: boot device object from bios page 2 ++ * ++ * Returns 1 when there's a match, 0 means no match. ++ */ ++static inline int ++_scsih_srch_boot_device_name(u64 device_name, ++ Mpi2BootDeviceDeviceName_t *boot_device) ++{ ++ return (device_name == le64_to_cpu(boot_device->DeviceName)) ? 1 : 0; ++} ++ ++/** ++ * _scsih_srch_boot_encl_slot - search based on enclosure_logical_id/slot ++ * @enclosure_logical_id: enclosure logical id ++ * @slot_number: slot number ++ * @boot_device: boot device object from bios page 2 ++ * ++ * Returns 1 when there's a match, 0 means no match. ++ */ ++static inline int ++_scsih_srch_boot_encl_slot(u64 enclosure_logical_id, u16 slot_number, ++ Mpi2BootDeviceEnclosureSlot_t *boot_device) ++{ ++ return (enclosure_logical_id == le64_to_cpu(boot_device-> ++ EnclosureLogicalID) && slot_number == le16_to_cpu(boot_device-> ++ SlotNumber)) ? 1 : 0; ++} ++ ++/** ++ * _scsih_is_boot_device - search for matching boot device. ++ * @sas_address: sas address ++ * @device_name: device name specified in INDENTIFY fram ++ * @enclosure_logical_id: enclosure logical id ++ * @slot_number: slot number ++ * @form: specifies boot device form ++ * @boot_device: boot device object from bios page 2 ++ * ++ * Returns 1 when there's a match, 0 means no match. ++ */ ++static int ++_scsih_is_boot_device(u64 sas_address, u64 device_name, ++ u64 enclosure_logical_id, u16 slot, u8 form, ++ Mpi2BiosPage2BootDevice_t *boot_device) ++{ ++ int rc = 0; ++ ++ switch (form) { ++ case MPI2_BIOSPAGE2_FORM_SAS_WWID: ++ if (!sas_address) ++ break; ++ rc = _scsih_srch_boot_sas_address( ++ sas_address, &boot_device->SasWwid); ++ break; ++ case MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT: ++ if (!enclosure_logical_id) ++ break; ++ rc = _scsih_srch_boot_encl_slot( ++ enclosure_logical_id, ++ slot, &boot_device->EnclosureSlot); ++ break; ++ case MPI2_BIOSPAGE2_FORM_DEVICE_NAME: ++ if (!device_name) ++ break; ++ rc = _scsih_srch_boot_device_name( ++ device_name, &boot_device->DeviceName); ++ break; ++ case MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED: ++ break; ++ } ++ ++ return rc; ++} ++ ++/** ++ * _scsih_determine_boot_device - determine boot device. ++ * @ioc: per adapter object ++ * @device: either sas_device or raid_device object ++ * @is_raid: [flag] 1 = raid object, 0 = sas object ++ * ++ * Determines whether this device should be first reported device to ++ * to scsi-ml or sas transport, this purpose is for persistant boot device. ++ * There are primary, alternate, and current entries in bios page 2. The order ++ * priority is primary, alternate, then current. This routine saves ++ * the corresponding device object and is_raid flag in the ioc object. ++ * The saved data to be used later in _scsih_probe_boot_devices(). ++ */ ++static void ++_scsih_determine_boot_device(struct MPT2SAS_ADAPTER *ioc, ++ void *device, u8 is_raid) ++{ ++ struct _sas_device *sas_device; ++ struct _raid_device *raid_device; ++ u64 sas_address; ++ u64 device_name; ++ u64 enclosure_logical_id; ++ u16 slot; ++ ++ /* only process this function when driver loads */ ++ if (!ioc->wait_for_port_enable_to_complete) ++ return; ++ ++ if (!is_raid) { ++ sas_device = device; ++ sas_address = sas_device->sas_address; ++ device_name = sas_device->device_name; ++ enclosure_logical_id = sas_device->enclosure_logical_id; ++ slot = sas_device->slot; ++ } else { ++ raid_device = device; ++ sas_address = raid_device->wwid; ++ device_name = 0; ++ enclosure_logical_id = 0; ++ slot = 0; ++ } ++ ++ if (!ioc->req_boot_device.device) { ++ if (_scsih_is_boot_device(sas_address, device_name, ++ enclosure_logical_id, slot, ++ (ioc->bios_pg2.ReqBootDeviceForm & ++ MPI2_BIOSPAGE2_FORM_MASK), ++ &ioc->bios_pg2.RequestedBootDevice)) { ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT ++ "%s: req_boot_device(0x%016llx)\n", ++ ioc->name, __func__, ++ (unsigned long long)sas_address)); ++ ioc->req_boot_device.device = device; ++ ioc->req_boot_device.is_raid = is_raid; ++ } ++ } ++ ++ if (!ioc->req_alt_boot_device.device) { ++ if (_scsih_is_boot_device(sas_address, device_name, ++ enclosure_logical_id, slot, ++ (ioc->bios_pg2.ReqAltBootDeviceForm & ++ MPI2_BIOSPAGE2_FORM_MASK), ++ &ioc->bios_pg2.RequestedAltBootDevice)) { ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT ++ "%s: req_alt_boot_device(0x%016llx)\n", ++ ioc->name, __func__, ++ (unsigned long long)sas_address)); ++ ioc->req_alt_boot_device.device = device; ++ ioc->req_alt_boot_device.is_raid = is_raid; ++ } ++ } ++ ++ if (!ioc->current_boot_device.device) { ++ if (_scsih_is_boot_device(sas_address, device_name, ++ enclosure_logical_id, slot, ++ (ioc->bios_pg2.CurrentBootDeviceForm & ++ MPI2_BIOSPAGE2_FORM_MASK), ++ &ioc->bios_pg2.CurrentBootDevice)) { ++ dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT ++ "%s: current_boot_device(0x%016llx)\n", ++ ioc->name, __func__, ++ (unsigned long long)sas_address)); ++ ioc->current_boot_device.device = device; ++ ioc->current_boot_device.is_raid = is_raid; ++ } ++ } ++} ++ ++/** ++ * mpt2sas_scsih_sas_device_find_by_sas_address - sas device search ++ * @ioc: per adapter object ++ * @sas_address: sas address ++ * Context: Calling function should acquire ioc->sas_device_lock ++ * ++ * This searches for sas_device based on sas_address, then return sas_device ++ * object. ++ */ ++struct _sas_device * ++mpt2sas_scsih_sas_device_find_by_sas_address(struct MPT2SAS_ADAPTER *ioc, ++ u64 sas_address) ++{ ++ struct _sas_device *sas_device, *r; ++ ++ r = NULL; ++ /* check the sas_device_init_list */ ++ list_for_each_entry(sas_device, &ioc->sas_device_init_list, ++ list) { ++ if (sas_device->sas_address != sas_address) ++ continue; ++ r = sas_device; ++ goto out; ++ } ++ ++ /* then check the sas_device_list */ ++ list_for_each_entry(sas_device, &ioc->sas_device_list, list) { ++ if (sas_device->sas_address != sas_address) ++ continue; ++ r = sas_device; ++ goto out; ++ } ++ out: ++ return r; ++} ++ ++/** ++ * _scsih_sas_device_find_by_handle - sas device search ++ * @ioc: per adapter object ++ * @handle: sas device handle (assigned by firmware) ++ * Context: Calling function should acquire ioc->sas_device_lock ++ * ++ * This searches for sas_device based on sas_address, then return sas_device ++ * object. ++ */ ++static struct _sas_device * ++_scsih_sas_device_find_by_handle(struct MPT2SAS_ADAPTER *ioc, u16 handle) ++{ ++ struct _sas_device *sas_device, *r; ++ ++ r = NULL; ++ if (ioc->wait_for_port_enable_to_complete) { ++ list_for_each_entry(sas_device, &ioc->sas_device_init_list, ++ list) { ++ if (sas_device->handle != handle) ++ continue; ++ r = sas_device; ++ goto out; ++ } ++ } else { ++ list_for_each_entry(sas_device, &ioc->sas_device_list, list) { ++ if (sas_device->handle != handle) ++ continue; ++ r = sas_device; ++ goto out; ++ } ++ } ++ ++ out: ++ return r; ++} ++ ++/** ++ * _scsih_sas_device_remove - remove sas_device from list. ++ * @ioc: per adapter object ++ * @sas_device: the sas_device object ++ * Context: This function will acquire ioc->sas_device_lock. ++ * ++ * Removing object and freeing associated memory from the ioc->sas_device_list. ++ */ ++static void ++_scsih_sas_device_remove(struct MPT2SAS_ADAPTER *ioc, ++ struct _sas_device *sas_device) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ list_del(&sas_device->list); ++#ifdef MPT2SAS_MULTIPATH ++ kfree(sas_device->serial_number); ++#endif ++ memset(sas_device, 0, sizeof(struct _sas_device)); ++ kfree(sas_device); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++} ++ ++/** ++ * _scsih_sas_device_add - insert sas_device to the list. ++ * @ioc: per adapter object ++ * @sas_device: the sas_device object ++ * Context: This function will acquire ioc->sas_device_lock. ++ * ++ * Adding new object to the ioc->sas_device_list. ++ */ ++static void ++_scsih_sas_device_add(struct MPT2SAS_ADAPTER *ioc, ++ struct _sas_device *sas_device) ++{ ++ unsigned long flags; ++ u16 handle, parent_handle; ++ u64 sas_address; ++ ++ dewtprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: handle" ++ "(0x%04x), sas_addr(0x%016llx)\n", ioc->name, __func__, ++ sas_device->handle, (unsigned long long)sas_device->sas_address)); ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ list_add_tail(&sas_device->list, &ioc->sas_device_list); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ ++ handle = sas_device->handle; ++ parent_handle = sas_device->parent_handle; ++ sas_address = sas_device->sas_address; ++ if (!mpt2sas_transport_port_add(ioc, handle, parent_handle)) ++ _scsih_sas_device_remove(ioc, sas_device); ++} ++ ++/** ++ * _scsih_sas_device_init_add - insert sas_device to the list. ++ * @ioc: per adapter object ++ * @sas_device: the sas_device object ++ * Context: This function will acquire ioc->sas_device_lock. ++ * ++ * Adding new object at driver load time to the ioc->sas_device_init_list. ++ */ ++static void ++_scsih_sas_device_init_add(struct MPT2SAS_ADAPTER *ioc, ++ struct _sas_device *sas_device) ++{ ++ unsigned long flags; ++ ++ dewtprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: handle" ++ "(0x%04x), sas_addr(0x%016llx)\n", ioc->name, __func__, ++ sas_device->handle, (unsigned long long)sas_device->sas_address)); ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ list_add_tail(&sas_device->list, &ioc->sas_device_init_list); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ _scsih_determine_boot_device(ioc, sas_device, 0); ++} ++ ++/** ++ * mpt2sas_scsih_expander_find_by_handle - expander device search ++ * @ioc: per adapter object ++ * @handle: expander handle (assigned by firmware) ++ * Context: Calling function should acquire ioc->sas_device_lock ++ * ++ * This searches for expander device based on handle, then returns the ++ * sas_node object. ++ */ ++struct _sas_node * ++mpt2sas_scsih_expander_find_by_handle(struct MPT2SAS_ADAPTER *ioc, u16 handle) ++{ ++ struct _sas_node *sas_expander, *r; ++ ++ r = NULL; ++ list_for_each_entry(sas_expander, &ioc->sas_expander_list, list) { ++ if (sas_expander->handle != handle) ++ continue; ++ r = sas_expander; ++ goto out; ++ } ++ out: ++ return r; ++} ++ ++/** ++ * _scsih_raid_device_find_by_id - raid device search ++ * @ioc: per adapter object ++ * @id: sas device target id ++ * @channel: sas device channel ++ * Context: Calling function should acquire ioc->raid_device_lock ++ * ++ * This searches for raid_device based on target id, then return raid_device ++ * object. ++ */ ++static struct _raid_device * ++_scsih_raid_device_find_by_id(struct MPT2SAS_ADAPTER *ioc, int id, int channel) ++{ ++ struct _raid_device *raid_device, *r; ++ ++ r = NULL; ++ list_for_each_entry(raid_device, &ioc->raid_device_list, list) { ++ if (raid_device->id == id && raid_device->channel == channel) { ++ r = raid_device; ++ goto out; ++ } ++ } ++ ++ out: ++ return r; ++} ++ ++/** ++ * _scsih_raid_device_find_by_handle - raid device search ++ * @ioc: per adapter object ++ * @handle: sas device handle (assigned by firmware) ++ * Context: Calling function should acquire ioc->raid_device_lock ++ * ++ * This searches for raid_device based on handle, then return raid_device ++ * object. ++ */ ++static struct _raid_device * ++_scsih_raid_device_find_by_handle(struct MPT2SAS_ADAPTER *ioc, u16 handle) ++{ ++ struct _raid_device *raid_device, *r; ++ ++ r = NULL; ++ list_for_each_entry(raid_device, &ioc->raid_device_list, list) { ++ if (raid_device->handle != handle) ++ continue; ++ r = raid_device; ++ goto out; ++ } ++ ++ out: ++ return r; ++} ++ ++/** ++ * _scsih_raid_device_find_by_wwid - raid device search ++ * @ioc: per adapter object ++ * @handle: sas device handle (assigned by firmware) ++ * Context: Calling function should acquire ioc->raid_device_lock ++ * ++ * This searches for raid_device based on wwid, then return raid_device ++ * object. ++ */ ++static struct _raid_device * ++_scsih_raid_device_find_by_wwid(struct MPT2SAS_ADAPTER *ioc, u64 wwid) ++{ ++ struct _raid_device *raid_device, *r; ++ ++ r = NULL; ++ list_for_each_entry(raid_device, &ioc->raid_device_list, list) { ++ if (raid_device->wwid != wwid) ++ continue; ++ r = raid_device; ++ goto out; ++ } ++ ++ out: ++ return r; ++} ++ ++/** ++ * _scsih_raid_device_add - add raid_device object ++ * @ioc: per adapter object ++ * @raid_device: raid_device object ++ * ++ * This is added to the raid_device_list link list. ++ */ ++static void ++_scsih_raid_device_add(struct MPT2SAS_ADAPTER *ioc, ++ struct _raid_device *raid_device) ++{ ++ unsigned long flags; ++ ++ dewtprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: handle" ++ "(0x%04x), wwid(0x%016llx)\n", ioc->name, __func__, ++ raid_device->handle, (unsigned long long)raid_device->wwid)); ++ ++ spin_lock_irqsave(&ioc->raid_device_lock, flags); ++ list_add_tail(&raid_device->list, &ioc->raid_device_list); ++ spin_unlock_irqrestore(&ioc->raid_device_lock, flags); ++} ++ ++/** ++ * _scsih_raid_device_remove - delete raid_device object ++ * @ioc: per adapter object ++ * @raid_device: raid_device object ++ * ++ * This is removed from the raid_device_list link list. ++ */ ++static void ++_scsih_raid_device_remove(struct MPT2SAS_ADAPTER *ioc, ++ struct _raid_device *raid_device) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ioc->raid_device_lock, flags); ++ list_del(&raid_device->list); ++ memset(raid_device, 0, sizeof(struct _raid_device)); ++ kfree(raid_device); ++ spin_unlock_irqrestore(&ioc->raid_device_lock, flags); ++} ++ ++/** ++ * mpt2sas_scsih_expander_find_by_sas_address - expander device search ++ * @ioc: per adapter object ++ * @sas_address: sas address ++ * Context: Calling function should acquire ioc->sas_node_lock. ++ * ++ * This searches for expander device based on sas_address, then returns the ++ * sas_node object. ++ */ ++struct _sas_node * ++mpt2sas_scsih_expander_find_by_sas_address(struct MPT2SAS_ADAPTER *ioc, ++ u64 sas_address) ++{ ++ struct _sas_node *sas_expander, *r; ++ ++ r = NULL; ++ list_for_each_entry(sas_expander, &ioc->sas_expander_list, list) { ++ if (sas_expander->sas_address != sas_address) ++ continue; ++ r = sas_expander; ++ goto out; ++ } ++ out: ++ return r; ++} ++ ++/** ++ * _scsih_expander_node_add - insert expander device to the list. ++ * @ioc: per adapter object ++ * @sas_expander: the sas_device object ++ * Context: This function will acquire ioc->sas_node_lock. ++ * ++ * Adding new object to the ioc->sas_expander_list. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_expander_node_add(struct MPT2SAS_ADAPTER *ioc, ++ struct _sas_node *sas_expander) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ list_add_tail(&sas_expander->list, &ioc->sas_expander_list); ++ spin_unlock_irqrestore(&ioc->sas_node_lock, flags); ++} ++ ++/** ++ * _scsih_is_end_device - determines if device is an end device ++ * @device_info: bitfield providing information about the device. ++ * Context: none ++ * ++ * Returns 1 if end device. ++ */ ++static int ++_scsih_is_end_device(u32 device_info) ++{ ++ if (device_info & MPI2_SAS_DEVICE_INFO_END_DEVICE && ++ ((device_info & MPI2_SAS_DEVICE_INFO_SSP_TARGET) | ++ (device_info & MPI2_SAS_DEVICE_INFO_STP_TARGET) | ++ (device_info & MPI2_SAS_DEVICE_INFO_SATA_DEVICE))) ++ return 1; ++ else ++ return 0; ++} ++ ++/** ++ * _scsih_scsi_lookup_get - returns scmd entry ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * Context: This function will acquire ioc->scsi_lookup_lock. ++ * ++ * Returns the smid stored scmd pointer. ++ */ ++static struct scsi_cmnd * ++_scsih_scsi_lookup_get(struct MPT2SAS_ADAPTER *ioc, u16 smid) ++{ ++ unsigned long flags; ++ struct scsi_cmnd *scmd; ++ ++ spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); ++ scmd = ioc->scsi_lookup[smid - 1].scmd; ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++ return scmd; ++} ++ ++/** ++ * mptscsih_getclear_scsi_lookup - returns scmd entry ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * Context: This function will acquire ioc->scsi_lookup_lock. ++ * ++ * Returns the smid stored scmd pointer, as well as clearing the scmd pointer. ++ */ ++static struct scsi_cmnd * ++_scsih_scsi_lookup_getclear(struct MPT2SAS_ADAPTER *ioc, u16 smid) ++{ ++ unsigned long flags; ++ struct scsi_cmnd *scmd; ++ ++ spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); ++ scmd = ioc->scsi_lookup[smid - 1].scmd; ++ ioc->scsi_lookup[smid - 1].scmd = NULL; ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++ return scmd; ++} ++ ++/** ++ * _scsih_scsi_lookup_set - updates scmd entry in lookup ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @scmd: pointer to scsi command object ++ * Context: This function will acquire ioc->scsi_lookup_lock. ++ * ++ * This will save scmd pointer in the scsi_lookup array. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_scsi_lookup_set(struct MPT2SAS_ADAPTER *ioc, u16 smid, ++ struct scsi_cmnd *scmd) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); ++ ioc->scsi_lookup[smid - 1].scmd = scmd; ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++} ++ ++/** ++ * _scsih_scsi_lookup_find_by_scmd - scmd lookup ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @scmd: pointer to scsi command object ++ * Context: This function will acquire ioc->scsi_lookup_lock. ++ * ++ * This will search for a scmd pointer in the scsi_lookup array, ++ * returning the revelent smid. A returned value of zero means invalid. ++ */ ++static u16 ++_scsih_scsi_lookup_find_by_scmd(struct MPT2SAS_ADAPTER *ioc, struct scsi_cmnd ++ *scmd) ++{ ++ u16 smid; ++ unsigned long flags; ++ int i; ++ ++ spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); ++ smid = 0; ++ for (i = 0; i < ioc->request_depth; i++) { ++ if (ioc->scsi_lookup[i].scmd == scmd) { ++ smid = i + 1; ++ goto out; ++ } ++ } ++ out: ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++ return smid; ++} ++ ++/** ++ * _scsih_scsi_lookup_find_by_target - search for matching channel:id ++ * @ioc: per adapter object ++ * @id: target id ++ * @channel: channel ++ * Context: This function will acquire ioc->scsi_lookup_lock. ++ * ++ * This will search for a matching channel:id in the scsi_lookup array, ++ * returning 1 if found. ++ */ ++static u8 ++_scsih_scsi_lookup_find_by_target(struct MPT2SAS_ADAPTER *ioc, int id, ++ int channel) ++{ ++ u8 found; ++ unsigned long flags; ++ int i; ++ ++ spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); ++ found = 0; ++ for (i = 0 ; i < ioc->request_depth; i++) { ++ if (ioc->scsi_lookup[i].scmd && ++ (ioc->scsi_lookup[i].scmd->device->id == id && ++ ioc->scsi_lookup[i].scmd->device->channel == channel)) { ++ found = 1; ++ goto out; ++ } ++ } ++ out: ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++ return found; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) ++/** ++ * _scsih_scsi_lookup_find_by_lun - search for matching channel:id:lun ++ * @ioc: per adapter object ++ * @id: target id ++ * @lun: lun number ++ * @channel: channel ++ * Context: This function will acquire ioc->scsi_lookup_lock. ++ * ++ * This will search for a matching channel:id:lun in the scsi_lookup array, ++ * returning 1 if found. ++ */ ++static u8 ++_scsih_scsi_lookup_find_by_lun(struct MPT2SAS_ADAPTER *ioc, int id, ++ unsigned int lun, int channel) ++{ ++ u8 found; ++ unsigned long flags; ++ int i; ++ ++ spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); ++ found = 0; ++ for (i = 0 ; i < ioc->request_depth; i++) { ++ if (ioc->scsi_lookup[i].scmd && ++ (ioc->scsi_lookup[i].scmd->device->id == id && ++ ioc->scsi_lookup[i].scmd->device->channel == channel && ++ ioc->scsi_lookup[i].scmd->device->lun == lun)) { ++ found = 1; ++ goto out; ++ } ++ } ++ out: ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++ return found; ++} ++#endif ++ ++#if defined(CHAIN_POOL) ++/** ++ * _scsih_get_chain_buffer_tracker - obtain chain tracker ++ * @ioc: per adapter object ++ * @smid: smid associated to an IO request ++ * ++ * Returns chain tracker(from ioc->free_chain_list) ++ */ ++static struct chain_tracker * ++_scsih_get_chain_buffer_tracker(struct MPT2SAS_ADAPTER *ioc, u16 smid) ++{ ++ struct chain_tracker *chain_req; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); ++ if (list_empty(&ioc->free_chain_list)) { ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++ printk(MPT2SAS_WARN_FMT "chain buffers not available\n", ++ ioc->name); ++ return NULL; ++ } ++ chain_req = list_entry(ioc->free_chain_list.next, ++ struct chain_tracker, tracker_list); ++ list_del_init(&chain_req->tracker_list); ++ list_add_tail(&chain_req->tracker_list, ++ &ioc->scsi_lookup[smid - 1].chain_list); ++ spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); ++ return chain_req; ++} ++ ++/** ++ * _scsih_get_chain_buffer_dma - obtain chain dma address ++ * @ioc: per adapter object ++ * @index: index from zero (ioc->chain) ++ * ++ * Returns phys pointer to chain buffer. ++ */ ++static dma_addr_t ++_scsih_get_chain_buffer_dma(struct MPT2SAS_ADAPTER *ioc, u16 index) ++{ ++ return ioc->chain_dma + (ioc->request_sz * index); ++} ++ ++/** ++ * _scsih_get_chain_buffer - obtain chains virtual addr ++ * @ioc: per adapter object ++ * @index: index from zero (ioc->chain) ++ * ++ * Returns virt pointer to chain buffer. ++ */ ++static void * ++_scsih_get_chain_buffer(struct MPT2SAS_ADAPTER *ioc, u16 index) ++{ ++ return (void *)(ioc->chain + (ioc->request_sz * index)); ++} ++#else ++/** ++ * _scsih_get_chain_buffer_dma - obtain block of chains (dma address) ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * ++ * Returns phys pointer to chain buffer. ++ */ ++static dma_addr_t ++_scsih_get_chain_buffer_dma(struct MPT2SAS_ADAPTER *ioc, u16 smid) ++{ ++ return ioc->chain_dma + ((smid - 1) * (ioc->request_sz * ++ ioc->chains_needed_per_io)); ++} ++ ++/** ++ * _scsih_get_chain_buffer - obtain block of chains assigned to a mf request ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * ++ * Returns virt pointer to chain buffer. ++ */ ++static void * ++_scsih_get_chain_buffer(struct MPT2SAS_ADAPTER *ioc, u16 smid) ++{ ++ return (void *)(ioc->chain + ((smid - 1) * (ioc->request_sz * ++ ioc->chains_needed_per_io))); ++} ++#endif ++ ++/** ++ * _scsih_build_scatter_gather - main sg creation routine ++ * @ioc: per adapter object ++ * @scmd: scsi command ++ * @smid: system request message index ++ * Context: none. ++ * ++ * The main routine that builds scatter gather table from a given ++ * scsi request sent via the .queuecommand main handler. ++ * ++ * Returns 0 success, anything else error ++ */ ++static int ++_scsih_build_scatter_gather(struct MPT2SAS_ADAPTER *ioc, ++ struct scsi_cmnd *scmd, u16 smid) ++{ ++ Mpi2SCSIIORequest_t *mpi_request; ++ dma_addr_t chain_dma; ++ struct scatterlist *sg_scmd; ++ void *sg_local, *chain; ++ u32 chain_offset; ++ u32 chain_length; ++ u32 chain_flags; ++ u32 sges_left; ++ u32 sges_in_segment; ++ u32 sgl_flags; ++ u32 sgl_flags_last_element; ++ u32 sgl_flags_end_buffer; ++#if defined(CHAIN_POOL) ++ struct chain_tracker *chain_req; ++#endif ++ ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ++ /* init scatter gather flags */ ++ sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT; ++ if (scmd->sc_data_direction == DMA_TO_DEVICE) ++ sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC; ++ sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT) ++ << MPI2_SGE_FLAGS_SHIFT; ++ sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT | ++ MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST) ++ << MPI2_SGE_FLAGS_SHIFT; ++ sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ /* single buffer sge */ ++ if (!scmd->use_sg) { ++ scmd->SCp.dma_handle = pci_map_single(ioc->pdev, ++ scmd->request_buffer, scmd->request_bufflen, ++ scmd->sc_data_direction); ++ if (pci_dma_mapping_error(scmd->SCp.dma_handle)) { ++ sdev_printk(KERN_ERR, scmd->device, "pci_map_single" ++ " failed: request for %d bytes!\n", ++ scmd->request_bufflen); ++ return -ENOMEM; ++ } ++ ioc->base_add_sg_single(&mpi_request->SGL, ++ sgl_flags_end_buffer | scmd->request_bufflen, ++ scmd->SCp.dma_handle); ++ return 0; ++ } ++ ++ /* sg list provided */ ++ sg_scmd = (struct scatterlist *) scmd->request_buffer; ++ sges_left = pci_map_sg(ioc->pdev, sg_scmd, scmd->use_sg, ++ scmd->sc_data_direction); ++ ++#if defined(CRACK_MONKEY_EEDP) && defined(EEDP_SUPPORT) ++ if (scmd->cmnd[0] == INQUIRY) { ++ scmd->host_scribble = ++ page_address(((struct scatterlist *) ++ scmd->request_buffer)[0].page)+ ++ ((struct scatterlist *) ++ scmd->request_buffer)[0].offset; ++ } ++#endif /* CRACK_MONKEY_EEDP */ ++ if (!sges_left) { ++ sdev_printk(KERN_ERR, scmd->device, "pci_map_sg" ++ " failed: request for %d bytes!\n", scmd->request_bufflen); ++ return -ENOMEM; ++ } ++#else ++ sg_scmd = scsi_sglist(scmd); ++ sges_left = scsi_dma_map(scmd); ++ if (!sges_left) { ++ sdev_printk(KERN_ERR, scmd->device, "pci_map_sg" ++ " failed: request for %d bytes!\n", scsi_bufflen(scmd)); ++ return -ENOMEM; ++ } ++ ++#if defined(CRACK_MONKEY_EEDP) && defined(EEDP_SUPPORT) ++ if (scmd->cmnd[0] == INQUIRY) ++ scmd->host_scribble = page_address(sg_page(sg_scmd)) + ++ sg_scmd[0].offset; ++#endif /* CRACK_MONKEY_EEDP */ ++#endif ++ ++ ++ sg_local = &mpi_request->SGL; ++ sges_in_segment = ioc->max_sges_in_main_message; ++ if (sges_left <= sges_in_segment) ++ goto fill_in_last_segment; ++ ++ mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) + ++ (sges_in_segment * ioc->sge_size))/4; ++ ++ /* fill in main message segment when there is a chain following */ ++ while (sges_in_segment) { ++ if (sges_in_segment == 1) ++ ioc->base_add_sg_single(sg_local, ++ sgl_flags_last_element | sg_dma_len(sg_scmd), ++ sg_dma_address(sg_scmd)); ++ else ++ ioc->base_add_sg_single(sg_local, sgl_flags | ++ sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ sg_scmd++; ++#else ++ sg_scmd = sg_next(sg_scmd); ++#endif ++ sg_local += ioc->sge_size; ++ sges_left--; ++ sges_in_segment--; ++ } ++ ++ /* initializing the chain flags and pointers */ ++ chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT; ++#if defined(CHAIN_POOL) ++ chain_req = _scsih_get_chain_buffer_tracker(ioc, smid); ++ if (!chain_req) ++ return -1; ++ chain = _scsih_get_chain_buffer(ioc, chain_req->index); ++ chain_dma = _scsih_get_chain_buffer_dma(ioc, chain_req->index); ++#else ++ chain = _scsih_get_chain_buffer(ioc, smid); ++ chain_dma = _scsih_get_chain_buffer_dma(ioc, smid); ++#endif ++ do { ++ sges_in_segment = (sges_left <= ++ ioc->max_sges_in_chain_message) ? sges_left : ++ ioc->max_sges_in_chain_message; ++ chain_offset = (sges_left == sges_in_segment) ? ++ 0 : (sges_in_segment * ioc->sge_size)/4; ++ chain_length = sges_in_segment * ioc->sge_size; ++ if (chain_offset) { ++ chain_offset = chain_offset << ++ MPI2_SGE_CHAIN_OFFSET_SHIFT; ++ chain_length += ioc->sge_size; ++ } ++ ioc->base_add_sg_single(sg_local, chain_flags | chain_offset | ++ chain_length, chain_dma); ++ sg_local = chain; ++ if (!chain_offset) ++ goto fill_in_last_segment; ++ ++ /* fill in chain segments */ ++ while (sges_in_segment) { ++ if (sges_in_segment == 1) ++ ioc->base_add_sg_single(sg_local, ++ sgl_flags_last_element | ++ sg_dma_len(sg_scmd), ++ sg_dma_address(sg_scmd)); ++ else ++ ioc->base_add_sg_single(sg_local, sgl_flags | ++ sg_dma_len(sg_scmd), ++ sg_dma_address(sg_scmd)); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ sg_scmd++; ++#else ++ sg_scmd = sg_next(sg_scmd); ++#endif ++ sg_local += ioc->sge_size; ++ sges_left--; ++ sges_in_segment--; ++ } ++ ++#if defined(CHAIN_POOL) ++ chain_req = _scsih_get_chain_buffer_tracker(ioc, smid); ++ if (!chain_req) ++ return -1; ++ chain = _scsih_get_chain_buffer(ioc, chain_req->index); ++ chain_dma = _scsih_get_chain_buffer_dma(ioc, chain_req->index); ++#else ++ chain_dma += ioc->request_sz; ++ chain += ioc->request_sz; ++#endif ++ } while (1); ++ ++ ++ fill_in_last_segment: ++ ++ /* fill the last segment */ ++ while (sges_left) { ++ if (sges_left == 1) ++ ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer | ++ sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); ++ else ++ ioc->base_add_sg_single(sg_local, sgl_flags | ++ sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ sg_scmd++; ++#else ++ sg_scmd = sg_next(sg_scmd); ++#endif ++ sg_local += ioc->sge_size; ++ sges_left--; ++ } ++ ++ return 0; ++} ++ ++/** ++ * _scsih_change_queue_depth - setting device queue depth ++ * @sdev: scsi device struct ++ * @qdepth: requested queue depth ++ * ++ * Returns queue depth. ++ */ ++static int ++_scsih_change_queue_depth(struct scsi_device *sdev, int qdepth) ++{ ++ struct Scsi_Host *shost = sdev->host; ++ int max_depth; ++ int tag_type; ++ ++ max_depth = shost->can_queue; ++ if (!sdev->tagged_supported) ++ max_depth = 1; ++ if (qdepth > max_depth) ++ qdepth = max_depth; ++ tag_type = (qdepth == 1) ? 0 : MSG_SIMPLE_TAG; ++ scsi_adjust_queue_depth(sdev, tag_type, qdepth); ++ ++ if (sdev->inquiry_len > 7) ++ sdev_printk(KERN_INFO, sdev, "qdepth(%d), tagged(%d), " ++ "simple(%d), ordered(%d), scsi_level(%d), cmd_que(%d)\n", ++ sdev->queue_depth, sdev->tagged_supported, sdev->simple_tags, ++ sdev->ordered_tags, sdev->scsi_level, ++ (sdev->inquiry[7] & 2) >> 1); ++ ++ return sdev->queue_depth; ++} ++ ++/** ++ * _scsih_change_queue_type - changing device queue tag type ++ * @sdev: scsi device struct ++ * @tag_type: requested tag type ++ * ++ * Returns queue tag type. ++ */ ++static int ++_scsih_change_queue_type(struct scsi_device *sdev, int tag_type) ++{ ++ if (sdev->tagged_supported) { ++ scsi_set_tag_type(sdev, tag_type); ++ if (tag_type) ++ scsi_activate_tcq(sdev, sdev->queue_depth); ++ else ++ scsi_deactivate_tcq(sdev, sdev->queue_depth); ++ } else ++ tag_type = 0; ++ ++ return tag_type; ++} ++ ++/** ++ * _scsih_target_alloc - target add routine ++ * @starget: scsi target struct ++ * ++ * Returns 0 if ok. Any other return is assumed to be an error and ++ * the device is ignored. ++ */ ++static int ++_scsih_target_alloc(struct scsi_target *starget) ++{ ++ struct Scsi_Host *shost = dev_to_shost(&starget->dev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ struct MPT2SAS_TARGET *sas_target_priv_data; ++ struct _sas_device *sas_device; ++ struct _raid_device *raid_device; ++ unsigned long flags; ++ struct sas_rphy *rphy; ++ ++ sas_target_priv_data = kzalloc(sizeof(struct scsi_target), GFP_KERNEL); ++ if (!sas_target_priv_data) ++ return -ENOMEM; ++ ++ starget->hostdata = sas_target_priv_data; ++ sas_target_priv_data->starget = starget; ++ sas_target_priv_data->handle = MPT2SAS_INVALID_DEVICE_HANDLE; ++ ++ /* RAID volumes */ ++ if (starget->channel == RAID_CHANNEL) { ++ spin_lock_irqsave(&ioc->raid_device_lock, flags); ++ raid_device = _scsih_raid_device_find_by_id(ioc, starget->id, ++ starget->channel); ++ if (raid_device) { ++ sas_target_priv_data->handle = raid_device->handle; ++ sas_target_priv_data->sas_address = raid_device->wwid; ++ sas_target_priv_data->flags |= MPT_TARGET_FLAGS_VOLUME; ++ raid_device->starget = starget; ++ } ++ spin_unlock_irqrestore(&ioc->raid_device_lock, flags); ++ return 0; ++ } ++ ++ /* sas/sata devices */ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ rphy = dev_to_rphy(starget->dev.parent); ++ sas_device = mpt2sas_scsih_sas_device_find_by_sas_address(ioc, ++ rphy->identify.sas_address); ++ ++ if (sas_device) { ++ sas_target_priv_data->handle = sas_device->handle; ++ sas_target_priv_data->sas_address = sas_device->sas_address; ++ sas_device->starget = starget; ++ sas_device->id = starget->id; ++ sas_device->channel = starget->channel; ++ if (sas_device->hidden_raid_component) ++ sas_target_priv_data->flags |= ++ MPT_TARGET_FLAGS_RAID_COMPONENT; ++ } ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ ++ return 0; ++} ++ ++/** ++ * _scsih_target_destroy - target destroy routine ++ * @starget: scsi target struct ++ * ++ * Returns nothing. ++ */ ++static void ++_scsih_target_destroy(struct scsi_target *starget) ++{ ++ struct Scsi_Host *shost = dev_to_shost(&starget->dev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ struct MPT2SAS_TARGET *sas_target_priv_data; ++ struct _sas_device *sas_device; ++ struct _raid_device *raid_device; ++ unsigned long flags; ++ struct sas_rphy *rphy; ++ ++ sas_target_priv_data = starget->hostdata; ++ if (!sas_target_priv_data) ++ return; ++ ++ if (starget->channel == RAID_CHANNEL) { ++ spin_lock_irqsave(&ioc->raid_device_lock, flags); ++ raid_device = _scsih_raid_device_find_by_id(ioc, starget->id, ++ starget->channel); ++ if (raid_device) { ++ raid_device->starget = NULL; ++ raid_device->sdev = NULL; ++ } ++ spin_unlock_irqrestore(&ioc->raid_device_lock, flags); ++ goto out; ++ } ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ rphy = dev_to_rphy(starget->dev.parent); ++ sas_device = mpt2sas_scsih_sas_device_find_by_sas_address(ioc, ++ rphy->identify.sas_address); ++ if (sas_device && (sas_device->starget == starget) && ++ (sas_device->id == starget->id) && ++ (sas_device->channel == starget->channel)) ++ sas_device->starget = NULL; ++ ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ ++ out: ++ kfree(sas_target_priv_data); ++ starget->hostdata = NULL; ++} ++ ++/** ++ * _scsih_slave_alloc - device add routine ++ * @sdev: scsi device struct ++ * ++ * Returns 0 if ok. Any other return is assumed to be an error and ++ * the device is ignored. ++ */ ++static int ++_scsih_slave_alloc(struct scsi_device *sdev) ++{ ++ struct Scsi_Host *shost; ++ struct MPT2SAS_ADAPTER *ioc; ++ struct MPT2SAS_TARGET *sas_target_priv_data; ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ struct scsi_target *starget; ++ struct _raid_device *raid_device; ++ unsigned long flags; ++ ++ sas_device_priv_data = kzalloc(sizeof(struct scsi_device), GFP_KERNEL); ++ if (!sas_device_priv_data) ++ return -ENOMEM; ++ ++ sas_device_priv_data->lun = sdev->lun; ++ sas_device_priv_data->flags = MPT_DEVICE_FLAGS_INIT; ++ ++ starget = scsi_target(sdev); ++ sas_target_priv_data = starget->hostdata; ++ sas_target_priv_data->num_luns++; ++ sas_device_priv_data->sas_target = sas_target_priv_data; ++ sdev->hostdata = sas_device_priv_data; ++ if ((sas_target_priv_data->flags & MPT_TARGET_FLAGS_RAID_COMPONENT)) ++ sdev->no_uld_attach = 1; ++ ++ shost = dev_to_shost(&starget->dev); ++ ioc = shost_private(shost); ++ if (starget->channel == RAID_CHANNEL) { ++ spin_lock_irqsave(&ioc->raid_device_lock, flags); ++ raid_device = _scsih_raid_device_find_by_id(ioc, ++ starget->id, starget->channel); ++ if (raid_device) ++ raid_device->sdev = sdev; /* raid is single lun */ ++ spin_unlock_irqrestore(&ioc->raid_device_lock, flags); ++ } ++ ++ return 0; ++} ++ ++/** ++ * _scsih_slave_destroy - device destroy routine ++ * @sdev: scsi device struct ++ * ++ * Returns nothing. ++ */ ++static void ++_scsih_slave_destroy(struct scsi_device *sdev) ++{ ++ struct MPT2SAS_TARGET *sas_target_priv_data; ++ struct scsi_target *starget; ++ ++ if (!sdev->hostdata) ++ return; ++ ++ starget = scsi_target(sdev); ++ sas_target_priv_data = starget->hostdata; ++ sas_target_priv_data->num_luns--; ++ kfree(sdev->hostdata); ++ sdev->hostdata = NULL; ++} ++ ++/** ++ * _scsih_display_sata_capabilities - sata capabilities ++ * @ioc: per adapter object ++ * @sas_device: the sas_device object ++ * @sdev: scsi device struct ++ */ ++static void ++_scsih_display_sata_capabilities(struct MPT2SAS_ADAPTER *ioc, ++ struct _sas_device *sas_device, struct scsi_device *sdev) ++{ ++ Mpi2ConfigReply_t mpi_reply; ++ Mpi2SasDevicePage0_t sas_device_pg0; ++ u32 ioc_status; ++ u16 flags; ++ u32 device_info; ++ ++ if ((mpt2sas_config_get_sas_device_pg0(ioc, &mpi_reply, &sas_device_pg0, ++ MPI2_SAS_DEVICE_PGAD_FORM_HANDLE, sas_device->handle))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ flags = le16_to_cpu(sas_device_pg0.Flags); ++ device_info = le16_to_cpu(sas_device_pg0.DeviceInfo); ++ ++ sdev_printk(KERN_INFO, sdev, ++ "atapi(%s), ncq(%s), asyn_notify(%s), smart(%s), fua(%s), " ++ "sw_preserve(%s)\n", ++ (device_info & MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE) ? "y" : "n", ++ (flags & MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED) ? "y" : "n", ++ (flags & MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY) ? "y" : ++ "n", ++ (flags & MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED) ? "y" : "n", ++ (flags & MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED) ? "y" : "n", ++ (flags & MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE) ? "y" : "n"); ++} ++ ++/** ++ * _scsih_get_volume_capabilities - volume capabilities ++ * @ioc: per adapter object ++ * @sas_device: the raid_device object ++ */ ++static void ++_scsih_get_volume_capabilities(struct MPT2SAS_ADAPTER *ioc, ++ struct _raid_device *raid_device) ++{ ++ Mpi2RaidVolPage0_t *vol_pg0; ++ Mpi2RaidPhysDiskPage0_t pd_pg0; ++ Mpi2SasDevicePage0_t sas_device_pg0; ++ Mpi2ConfigReply_t mpi_reply; ++ u16 sz; ++ u8 num_pds; ++ ++ if ((mpt2sas_config_get_number_pds(ioc, raid_device->handle, ++ &num_pds)) || !num_pds) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ raid_device->num_pds = num_pds; ++ sz = offsetof(Mpi2RaidVolPage0_t, PhysDisk) + (num_pds * ++ sizeof(Mpi2RaidVol0PhysDisk_t)); ++ vol_pg0 = kzalloc(sz, GFP_KERNEL); ++ if (!vol_pg0) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ if ((mpt2sas_config_get_raid_volume_pg0(ioc, &mpi_reply, vol_pg0, ++ MPI2_RAID_VOLUME_PGAD_FORM_HANDLE, raid_device->handle, sz))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ kfree(vol_pg0); ++ return; ++ } ++ ++ raid_device->volume_type = vol_pg0->VolumeType; ++ ++ /* figure out what the underlying devices are by ++ * obtaining the device_info bits for the 1st device ++ */ ++ if (!(mpt2sas_config_get_phys_disk_pg0(ioc, &mpi_reply, ++ &pd_pg0, MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM, ++ vol_pg0->PhysDisk[0].PhysDiskNum))) { ++ if (!(mpt2sas_config_get_sas_device_pg0(ioc, &mpi_reply, ++ &sas_device_pg0, MPI2_SAS_DEVICE_PGAD_FORM_HANDLE, ++ le16_to_cpu(pd_pg0.DevHandle)))) { ++ raid_device->device_info = ++ le32_to_cpu(sas_device_pg0.DeviceInfo); ++ } ++ } ++ ++ kfree(vol_pg0); ++} ++ ++#ifdef MPT2SAS_MULTIPATH ++/** ++ * _scsih_detect_multipath - find vpd-sn, and dual path ++ * @ioc: ++ * @sdev: scsi device struct ++ * @sas_device: ++ * ++ */ ++static void ++_scsih_detect_multipath(struct MPT2SAS_ADAPTER *ioc, struct scsi_device *sdev, ++ struct _sas_device *sas_device) ++{ ++ struct _sas_device *sas_device_alt; ++ u8 data[252], len; ++ struct MPT2SAS_ADAPTER *ioc_alt; ++ ++ if (mpt2sas_multipath == -1 || mpt2sas_multipath == 0) ++ return; ++ ++ if (sdev->type != TYPE_DISK) ++ return; ++ ++ if (sas_device->serial_number != NULL) ++ return; ++ ++ if (_scsih_inquiry_vpd_sn(ioc, sas_device->handle, data, 252) ++ != DEVICE_READY) ++ return; ++ ++ len = strlen(&data[4]) + 1; ++ sas_device->serial_number = kmalloc(len, GFP_KERNEL); ++ if (!sas_device->serial_number) ++ return; ++ ++ strncpy(sas_device->serial_number, &data[4], len); ++ sdev_printk(KERN_INFO, sdev, "serial_number(%s)\n", ++ sas_device->serial_number); ++ list_for_each_entry(ioc_alt, &mpt2sas_ioc_list, list) { ++ list_for_each_entry(sas_device_alt, &ioc_alt->sas_device_list, ++ list) { ++ if (sas_device_alt == sas_device) ++ continue; ++ if (sas_device_alt->serial_number == NULL) ++ continue; ++ if (strcmp(sas_device_alt->serial_number, ++ sas_device->serial_number) != 0) ++ continue; ++ sas_device->ioc = ioc; ++ sas_device->sas_device_alt = sas_device_alt; ++ sas_device_alt->sas_device_alt = sas_device; ++ sas_device_alt->ioc = ioc_alt; ++ } ++ } ++} ++#endif ++ ++/** ++ * _scsih_enable_tlr - setting TLR flags ++ * @ioc: per adapter object ++ * @sdev: scsi device struct ++ * ++ * Enabling Transaction Layer Retries for tape devices when ++ * vpd page 0x90 is present ++ * ++ */ ++static void ++_scsih_enable_tlr(struct MPT2SAS_ADAPTER *ioc, struct scsi_device *sdev) ++{ ++ u8 data[30]; ++ u8 page_len, ii; ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ struct MPT2SAS_TARGET *sas_target_priv_data; ++ ++ /* only for TAPE */ ++ if (sdev->type != TYPE_TAPE) ++ return; ++ ++ if (!(ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR)) ++ return; ++ ++ sas_device_priv_data = sdev->hostdata; ++ if (!sas_device_priv_data) ++ return; ++ sas_target_priv_data = sas_device_priv_data->sas_target; ++ if (!sas_target_priv_data) ++ return; ++ ++ /* is Protocol-specific logical unit information (0x90) present ?? */ ++ if (_scsih_inquiry_vpd_supported_pages(ioc, ++ sas_target_priv_data->handle, sdev->lun, data, ++ sizeof(data)) != DEVICE_READY) ++ return; ++ ++ page_len = data[3]; ++ for (ii = 4; ii < page_len + 4; ii++) { ++ if (data[ii] == 0x90) { ++ sas_device_priv_data->flags |= MPT_DEVICE_TLR_ON; ++ return; ++ } ++ } ++} ++ ++/** ++ * _scsih_slave_configure - device configure routine. ++ * @sdev: scsi device struct ++ * ++ * Returns 0 if ok. Any other return is assumed to be an error and ++ * the device is ignored. ++ */ ++static int ++_scsih_slave_configure(struct scsi_device *sdev) ++{ ++ struct Scsi_Host *shost = sdev->host; ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ struct MPT2SAS_TARGET *sas_target_priv_data; ++ struct _sas_device *sas_device; ++ struct _raid_device *raid_device; ++ unsigned long flags; ++ int qdepth; ++ u8 ssp_target = 0; ++ char *ds = ""; ++ char *r_level = ""; ++ ++ qdepth = 1; ++ sas_device_priv_data = sdev->hostdata; ++ sas_device_priv_data->configured_lun = 1; ++ sas_device_priv_data->flags &= ~MPT_DEVICE_FLAGS_INIT; ++ sas_target_priv_data = sas_device_priv_data->sas_target; ++ ++ /* raid volume handling */ ++ if (sas_target_priv_data->flags & MPT_TARGET_FLAGS_VOLUME) { ++ ++ spin_lock_irqsave(&ioc->raid_device_lock, flags); ++ raid_device = _scsih_raid_device_find_by_handle(ioc, ++ sas_target_priv_data->handle); ++ spin_unlock_irqrestore(&ioc->raid_device_lock, flags); ++ if (!raid_device) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return 0; ++ } ++ ++ _scsih_get_volume_capabilities(ioc, raid_device); ++ ++ /* RAID Queue Depth Support ++ * IS volume = underlying qdepth of drive type, either ++ * MPT2SAS_SAS_QUEUE_DEPTH or MPT2SAS_SATA_QUEUE_DEPTH ++ * IM/IME/R10 = 128 (MPT2SAS_RAID_QUEUE_DEPTH) ++ */ ++ if (raid_device->device_info & ++ MPI2_SAS_DEVICE_INFO_SSP_TARGET) { ++ qdepth = MPT2SAS_SAS_QUEUE_DEPTH; ++ ds = "SSP"; ++ } else { ++ qdepth = MPT2SAS_SATA_QUEUE_DEPTH; ++ if (raid_device->device_info & ++ MPI2_SAS_DEVICE_INFO_SATA_DEVICE) ++ ds = "SATA"; ++ else ++ ds = "STP"; ++ } ++ ++ switch (raid_device->volume_type) { ++ case MPI2_RAID_VOL_TYPE_RAID0: ++ r_level = "RAID0"; ++ break; ++ case MPI2_RAID_VOL_TYPE_RAID1E: ++ qdepth = MPT2SAS_RAID_QUEUE_DEPTH; ++ if (ioc->manu_pg10.OEMIdentifier && ++ (ioc->manu_pg10.GenericFlags0 & ++ MFG10_GF0_R10_DISPLAY) && ++ !(raid_device->num_pds % 2)) ++ r_level = "RAID10"; ++ else ++ r_level = "RAID1E"; ++ break; ++ case MPI2_RAID_VOL_TYPE_RAID1: ++ qdepth = MPT2SAS_RAID_QUEUE_DEPTH; ++ r_level = "RAID1"; ++ break; ++ case MPI2_RAID_VOL_TYPE_RAID10: ++ qdepth = MPT2SAS_RAID_QUEUE_DEPTH; ++ r_level = "RAID10"; ++ break; ++ case MPI2_RAID_VOL_TYPE_UNKNOWN: ++ default: ++ qdepth = MPT2SAS_RAID_QUEUE_DEPTH; ++ r_level = "RAIDX"; ++ break; ++ } ++ ++ sdev_printk(KERN_INFO, sdev, "%s: " ++ "handle(0x%04x), wwid(0x%016llx), pd_count(%d), type(%s)\n", ++ r_level, raid_device->handle, ++ (unsigned long long)raid_device->wwid, ++ raid_device->num_pds, ds); ++ _scsih_change_queue_depth(sdev, qdepth); ++ return 0; ++ } ++ ++ /* non-raid handling */ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = mpt2sas_scsih_sas_device_find_by_sas_address(ioc, ++ sas_device_priv_data->sas_target->sas_address); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ if (sas_device) { ++ if (sas_target_priv_data->flags & ++ MPT_TARGET_FLAGS_RAID_COMPONENT) { ++ mpt2sas_config_get_volume_handle(ioc, ++ sas_device->handle, &sas_device->volume_handle); ++ mpt2sas_config_get_volume_wwid(ioc, ++ sas_device->volume_handle, ++ &sas_device->volume_wwid); ++ } ++ if (sas_device->device_info & MPI2_SAS_DEVICE_INFO_SSP_TARGET) { ++ qdepth = MPT2SAS_SAS_QUEUE_DEPTH; ++ ssp_target = 1; ++ ds = "SSP"; ++ } else { ++ qdepth = MPT2SAS_SATA_QUEUE_DEPTH; ++ if (sas_device->device_info & ++ MPI2_SAS_DEVICE_INFO_STP_TARGET) ++ ds = "STP"; ++ else if (sas_device->device_info & ++ MPI2_SAS_DEVICE_INFO_SATA_DEVICE) ++ ds = "SATA"; ++ } ++ ++ sdev_printk(KERN_INFO, sdev, "%s: handle(0x%04x), " ++ "sas_addr(0x%016llx), device_name(0x%016llx)\n", ++ ds, sas_device->handle, ++ (unsigned long long)sas_device->sas_address, ++ (unsigned long long)sas_device->device_name); ++ sdev_printk(KERN_INFO, sdev, "%s: " ++ "enclosure_logical_id(0x%016llx), slot(%d)\n", ds, ++ (unsigned long long)sas_device->enclosure_logical_id, ++ sas_device->slot); ++ ++ if (!ssp_target) ++ _scsih_display_sata_capabilities(ioc, sas_device, sdev); ++ ++#ifdef MPT2SAS_MULTIPATH ++ _scsih_detect_multipath(ioc, sdev, sas_device); ++#endif ++ } ++ ++ _scsih_change_queue_depth(sdev, qdepth); ++ ++ if (ssp_target) { ++ sas_read_port_mode_page(sdev); ++ _scsih_enable_tlr(ioc, sdev); ++ } ++ ++#if defined(EEDP_SUPPORT) ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) ++ if (ssp_target && (!(sas_target_priv_data->flags & ++ MPT_TARGET_FLAGS_RAID_COMPONENT))) { ++ struct read_cap_parameter data; ++ enum device_responsive_state retcode; ++ u8 retry_count = 0; ++ ++ if (!(sdev->inquiry[5] & 1)) ++ goto out; ++ retry: ++ /* issue one retry to handle UA's */ ++ memset(&data, 0, sizeof(struct read_cap_parameter)); ++ retcode = _scsih_read_capacity_16(ioc, ++ sas_target_priv_data->handle, sdev->lun, &data, ++ sizeof(struct read_cap_parameter)); ++ ++ if ((retcode == DEVICE_RETRY || retcode == DEVICE_RETRY_UA) ++ && (!retry_count++)) ++ goto retry; ++ if (retcode != DEVICE_READY) ++ goto out; ++ if (!data.prot_en) ++ goto out; ++ sas_device_priv_data->eedp_type = data.p_type + 1; ++ ++ if (sas_device_priv_data->eedp_type == 2) { ++ sdev_printk(KERN_INFO, sdev, "formatted with " ++ "DIF Type 2 protection which is currently " ++ "unsupported. \n"); ++ goto out; ++ } ++ ++ sas_device_priv_data->eedp_enable = 1; ++ sdev_printk(KERN_INFO, sdev, "Enabling DIF Type %d " ++ "protection\n", sas_device_priv_data->eedp_type); ++ } ++ out: ++#endif ++#endif /* EEDP Support */ ++ return 0; ++} ++ ++/** ++ * _scsih_bios_param - fetch head, sector, cylinder info for a disk ++ * @sdev: scsi device struct ++ * @bdev: pointer to block device context ++ * @capacity: device size (in 512 byte sectors) ++ * @params: three element array to place output: ++ * params[0] number of heads (max 255) ++ * params[1] number of sectors (max 63) ++ * params[2] number of cylinders ++ * ++ * Return nothing. ++ */ ++static int ++_scsih_bios_param(struct scsi_device *sdev, struct block_device *bdev, ++ sector_t capacity, int params[]) ++{ ++ int heads; ++ int sectors; ++ sector_t cylinders; ++ ulong dummy; ++ ++ heads = 64; ++ sectors = 32; ++ ++ dummy = heads * sectors; ++ cylinders = capacity; ++ sector_div(cylinders, dummy); ++ ++ /* ++ * Handle extended translation size for logical drives ++ * > 1Gb ++ */ ++ if ((ulong)capacity >= 0x200000) { ++ heads = 255; ++ sectors = 63; ++ dummy = heads * sectors; ++ cylinders = capacity; ++ sector_div(cylinders, dummy); ++ } ++ ++ /* return result */ ++ params[0] = heads; ++ params[1] = sectors; ++ params[2] = cylinders; ++ ++ return 0; ++} ++ ++/** ++ * _scsih_response_code - translation of device response code ++ * @ioc: per adapter object ++ * @response_code: response code returned by the device ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_response_code(struct MPT2SAS_ADAPTER *ioc, u8 response_code) ++{ ++ char *desc; ++ ++ switch (response_code) { ++ case MPI2_SCSITASKMGMT_RSP_TM_COMPLETE: ++ desc = "task management request completed"; ++ break; ++ case MPI2_SCSITASKMGMT_RSP_INVALID_FRAME: ++ desc = "invalid frame"; ++ break; ++ case MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED: ++ desc = "task management request not supported"; ++ break; ++ case MPI2_SCSITASKMGMT_RSP_TM_FAILED: ++ desc = "task management request failed"; ++ break; ++ case MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED: ++ desc = "task management request succeeded"; ++ break; ++ case MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN: ++ desc = "invalid lun"; ++ break; ++ case 0xA: ++ desc = "overlapped tag attempted"; ++ break; ++ case MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC: ++ desc = "task queued, however not sent to target"; ++ break; ++ default: ++ desc = "unknown"; ++ break; ++ } ++ printk(MPT2SAS_WARN_FMT "response_code(0x%01x): %s\n", ++ ioc->name, response_code, desc); ++} ++ ++/** ++ * _scsih_tm_done - tm completion routine ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @VF_ID: virtual function id ++ * @reply: reply message frame(lower 32bit addr) ++ * Context: none. ++ * ++ * The callback handler when using scsih_issue_tm. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_tm_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, u32 reply) ++{ ++ MPI2DefaultReply_t *mpi_reply; ++ ++ if (ioc->tm_cmds.status == MPT2_CMD_NOT_USED) ++ return; ++ if (ioc->tm_cmds.smid != smid) ++ return; ++ ioc->tm_cmds.status |= MPT2_CMD_COMPLETE; ++ mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply); ++ if (mpi_reply) { ++ memcpy(ioc->tm_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); ++ ioc->tm_cmds.status |= MPT2_CMD_REPLY_VALID; ++ } ++ ioc->tm_cmds.status &= ~MPT2_CMD_PENDING; ++ complete(&ioc->tm_cmds.done); ++} ++ ++/** ++ * mpt2sas_scsih_set_tm_flag - set per target tm_busy ++ * @ioc: per adapter object ++ * @handle: device handle ++ * ++ * During taskmangement request, we need to freeze the device queue. ++ */ ++void ++mpt2sas_scsih_set_tm_flag(struct MPT2SAS_ADAPTER *ioc, u16 handle) ++{ ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ struct scsi_device *sdev; ++ u8 skip = 0; ++ ++ shost_for_each_device(sdev, ioc->shost) { ++ if (skip) ++ continue; ++ sas_device_priv_data = sdev->hostdata; ++ if (!sas_device_priv_data) ++ continue; ++ if (sas_device_priv_data->sas_target->handle == handle) { ++ sas_device_priv_data->sas_target->tm_busy = 1; ++ skip = 1; ++ ioc->ignore_loginfos = 1; ++ } ++ } ++} ++ ++/** ++ * mpt2sas_scsih_clear_tm_flag - clear per target tm_busy ++ * @ioc: per adapter object ++ * @handle: device handle ++ * ++ * During taskmangement request, we need to freeze the device queue. ++ */ ++void ++mpt2sas_scsih_clear_tm_flag(struct MPT2SAS_ADAPTER *ioc, u16 handle) ++{ ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ struct scsi_device *sdev; ++ u8 skip = 0; ++ ++ shost_for_each_device(sdev, ioc->shost) { ++ if (skip) ++ continue; ++ sas_device_priv_data = sdev->hostdata; ++ if (!sas_device_priv_data) ++ continue; ++ if (sas_device_priv_data->sas_target->handle == handle) { ++ sas_device_priv_data->sas_target->tm_busy = 0; ++ skip = 1; ++ ioc->ignore_loginfos = 0; ++ } ++ } ++} ++ ++/** ++ * mpt2sas_scsih_issue_tm - main routine for sending tm requests ++ * @ioc: per adapter struct ++ * @device_handle: device handle ++ * @lun: lun number ++ * @type: MPI2_SCSITASKMGMT_TASKTYPE__XXX (defined in mpi2_init.h) ++ * @smid_task: smid assigned to the task ++ * @timeout: timeout in seconds ++ * Context: The calling function needs to acquire the tm_cmds.mutex ++ * ++ * A generic API for sending task management requests to firmware. ++ * ++ * The ioc->tm_cmds.status flag should be MPT2_CMD_NOT_USED before calling ++ * this API. ++ * ++ * The callback index is set inside `ioc->tm_cb_idx`. ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_scsih_issue_tm(struct MPT2SAS_ADAPTER *ioc, u16 handle, uint lun, ++ u8 type, u16 smid_task, ulong timeout) ++{ ++ Mpi2SCSITaskManagementRequest_t *mpi_request; ++ Mpi2SCSITaskManagementReply_t *mpi_reply; ++ u16 smid = 0; ++ u32 ioc_state; ++ unsigned long timeleft; ++ u8 VF_ID = 0; ++ ++ if (ioc->tm_cmds.status != MPT2_CMD_NOT_USED) { ++ printk(MPT2SAS_INFO_FMT "%s: tm_cmd busy!!!\n", ++ __func__, ioc->name); ++ return; ++ } ++ ++ if (ioc->shost_recovery) { ++ printk(MPT2SAS_INFO_FMT "%s: host reset in progress!\n", ++ __func__, ioc->name); ++ return; ++ } ++ ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 0); ++ if (ioc_state & MPI2_DOORBELL_USED) { ++ dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "unexpected doorbell " ++ "active!\n", ioc->name)); ++ goto issue_host_reset; ++ } ++ ++ if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { ++ mpt2sas_base_fault_info(ioc, ioc_state & ++ MPI2_DOORBELL_DATA_MASK); ++ goto issue_host_reset; ++ } ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->tm_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ return; ++ } ++ ++ dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "sending tm: handle(0x%04x)," ++ " task_type(0x%02x), smid(%d)\n", ioc->name, handle, type, ++ smid_task)); ++ ioc->tm_cmds.status = MPT2_CMD_PENDING; ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ioc->tm_cmds.smid = smid; ++ memset(mpi_request, 0, sizeof(Mpi2SCSITaskManagementRequest_t)); ++ mpi_request->Function = MPI2_FUNCTION_SCSI_TASK_MGMT; ++ mpi_request->DevHandle = cpu_to_le16(handle); ++ mpi_request->TaskType = type; ++ mpi_request->TaskMID = cpu_to_le16(smid_task); ++ int_to_scsilun(lun, (struct scsi_lun *)mpi_request->LUN); ++ mpt2sas_scsih_set_tm_flag(ioc, handle); ++ init_completion(&ioc->tm_cmds.done); ++ mpt2sas_base_put_smid_hi_priority(ioc, smid, VF_ID); ++ timeleft = wait_for_completion_timeout(&ioc->tm_cmds.done, timeout*HZ); ++ mpt2sas_scsih_clear_tm_flag(ioc, handle); ++ if (!(ioc->tm_cmds.status & MPT2_CMD_COMPLETE)) { ++ printk(MPT2SAS_ERR_FMT "%s: timeout\n", ++ ioc->name, __func__); ++ _debug_dump_mf(mpi_request, ++ sizeof(Mpi2SCSITaskManagementRequest_t)/4); ++ if (!(ioc->tm_cmds.status & MPT2_CMD_RESET)) ++ goto issue_host_reset; ++ } ++ ++ if (ioc->tm_cmds.status & MPT2_CMD_REPLY_VALID) { ++ mpi_reply = ioc->tm_cmds.reply; ++ dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "complete tm: " ++ "ioc_status(0x%04x), loginfo(0x%08x), term_count(0x%08x)\n", ++ ioc->name, le16_to_cpu(mpi_reply->IOCStatus), ++ le32_to_cpu(mpi_reply->IOCLogInfo), ++ le32_to_cpu(mpi_reply->TerminationCount))); ++ if (ioc->logging_level & MPT_DEBUG_TM) { ++ _scsih_response_code(ioc, mpi_reply->ResponseCode); ++ if (mpi_reply->IOCStatus) ++ _debug_dump_mf(mpi_request, ++ sizeof(Mpi2SCSITaskManagementRequest_t)/4); ++ } ++ } ++ ++#ifdef MPT2SAS_MULTIPATH ++ mpt2sas_scsih_check_tm_for_multipath(ioc, handle, type); ++#endif ++ ++ return; ++ issue_host_reset: ++ mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, FORCE_BIG_HAMMER); ++} ++ ++/** ++ * _scsih_abort - eh threads main abort routine ++ * @sdev: scsi device struct ++ * ++ * Returns SUCCESS if command aborted else FAILED ++ */ ++static int ++_scsih_abort(struct scsi_cmnd *scmd) ++{ ++ struct MPT2SAS_ADAPTER *ioc = shost_private(scmd->device->host); ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ u16 smid; ++ u16 handle; ++ int r; ++ struct scsi_cmnd *scmd_lookup; ++ ++ printk(MPT2SAS_INFO_FMT "attempting task abort! scmd(%p)\n", ++ ioc->name, scmd); ++ scsi_print_command(scmd); ++ ++ sas_device_priv_data = scmd->device->hostdata; ++ if (!sas_device_priv_data || !sas_device_priv_data->sas_target) { ++ printk(MPT2SAS_INFO_FMT "device been deleted! scmd(%p)\n", ++ ioc->name, scmd); ++ scmd->result = DID_NO_CONNECT << 16; ++ scmd->scsi_done(scmd); ++ r = SUCCESS; ++ goto out; ++ } ++ ++ /* search for the command */ ++ smid = _scsih_scsi_lookup_find_by_scmd(ioc, scmd); ++ if (!smid) { ++ scmd->result = DID_RESET << 16; ++ r = SUCCESS; ++ goto out; ++ } ++ ++ /* for hidden raid components and volumes this is not supported */ ++ if (sas_device_priv_data->sas_target->flags & ++ MPT_TARGET_FLAGS_RAID_COMPONENT || ++ sas_device_priv_data->sas_target->flags & MPT_TARGET_FLAGS_VOLUME) { ++ scmd->result = DID_RESET << 16; ++ r = FAILED; ++ goto out; ++ } ++ ++ mutex_lock(&ioc->tm_cmds.mutex); ++ handle = sas_device_priv_data->sas_target->handle; ++ mpt2sas_scsih_issue_tm(ioc, handle, sas_device_priv_data->lun, ++ MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, smid, 30); ++ ++ /* sanity check - see whether command actually completed */ ++ scmd_lookup = _scsih_scsi_lookup_get(ioc, smid); ++ if (scmd_lookup && (scmd_lookup->serial_number == scmd->serial_number)) ++ r = FAILED; ++ else ++ r = SUCCESS; ++ ioc->tm_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->tm_cmds.mutex); ++ ++ out: ++ printk(MPT2SAS_INFO_FMT "task abort: %s scmd(%p)\n", ++ ioc->name, ((r == SUCCESS) ? "SUCCESS" : "FAILED"), scmd); ++ return r; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) ++/** ++ * _scsih_dev_reset - eh threads main device reset routine ++ * @sdev: scsi device struct ++ * ++ * Returns SUCCESS if command aborted else FAILED ++ */ ++static int ++_scsih_dev_reset(struct scsi_cmnd *scmd) ++{ ++ struct MPT2SAS_ADAPTER *ioc = shost_private(scmd->device->host); ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ struct _sas_device *sas_device; ++ unsigned long flags; ++ u16 handle; ++ int r; ++ ++ printk(MPT2SAS_INFO_FMT "attempting device reset! scmd(%p)\n", ++ ioc->name, scmd); ++ scsi_print_command(scmd); ++ ++ sas_device_priv_data = scmd->device->hostdata; ++ if (!sas_device_priv_data || !sas_device_priv_data->sas_target) { ++ printk(MPT2SAS_INFO_FMT "device been deleted! scmd(%p)\n", ++ ioc->name, scmd); ++ scmd->result = DID_NO_CONNECT << 16; ++ scmd->scsi_done(scmd); ++ r = SUCCESS; ++ goto out; ++ } ++ ++ /* for hidden raid components obtain the volume_handle */ ++ handle = 0; ++ if (sas_device_priv_data->sas_target->flags & ++ MPT_TARGET_FLAGS_RAID_COMPONENT) { ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = _scsih_sas_device_find_by_handle(ioc, ++ sas_device_priv_data->sas_target->handle); ++ if (sas_device) ++ handle = sas_device->volume_handle; ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ } else ++ handle = sas_device_priv_data->sas_target->handle; ++ ++ if (!handle) { ++ scmd->result = DID_RESET << 16; ++ r = FAILED; ++ goto out; ++ } ++ ++ mutex_lock(&ioc->tm_cmds.mutex); ++ mpt2sas_scsih_issue_tm(ioc, handle, 0, ++ MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET, scmd->device->lun, ++ 30); ++ ++ /* ++ * sanity check see whether all commands to this device been ++ * completed ++ */ ++ if (_scsih_scsi_lookup_find_by_lun(ioc, scmd->device->id, ++ scmd->device->lun, scmd->device->channel)) ++ r = FAILED; ++ else ++ r = SUCCESS; ++ ioc->tm_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->tm_cmds.mutex); ++ ++ out: ++ printk(MPT2SAS_INFO_FMT "device reset: %s scmd(%p)\n", ++ ioc->name, ((r == SUCCESS) ? "SUCCESS" : "FAILED"), scmd); ++ return r; ++} ++ ++/** ++ * _scsih_target_reset - eh threads main target reset routine ++ * @sdev: scsi device struct ++ * ++ * Returns SUCCESS if command aborted else FAILED ++ */ ++static int ++_scsih_target_reset(struct scsi_cmnd *scmd) ++{ ++ struct MPT2SAS_ADAPTER *ioc = shost_private(scmd->device->host); ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ struct _sas_device *sas_device; ++ unsigned long flags; ++ u16 handle; ++ int r; ++ ++ printk(MPT2SAS_INFO_FMT "attempting target reset! scmd(%p)\n", ++ ioc->name, scmd); ++ scsi_print_command(scmd); ++ ++ sas_device_priv_data = scmd->device->hostdata; ++ if (!sas_device_priv_data || !sas_device_priv_data->sas_target) { ++ printk(MPT2SAS_INFO_FMT "target been deleted! scmd(%p)\n", ++ ioc->name, scmd); ++ scmd->result = DID_NO_CONNECT << 16; ++ scmd->scsi_done(scmd); ++ r = SUCCESS; ++ goto out; ++ } ++ ++ /* for hidden raid components obtain the volume_handle */ ++ handle = 0; ++ if (sas_device_priv_data->sas_target->flags & ++ MPT_TARGET_FLAGS_RAID_COMPONENT) { ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = _scsih_sas_device_find_by_handle(ioc, ++ sas_device_priv_data->sas_target->handle); ++ if (sas_device) ++ handle = sas_device->volume_handle; ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ } else ++ handle = sas_device_priv_data->sas_target->handle; ++ ++ if (!handle) { ++ scmd->result = DID_RESET << 16; ++ r = FAILED; ++ goto out; ++ } ++ ++ mutex_lock(&ioc->tm_cmds.mutex); ++ mpt2sas_scsih_issue_tm(ioc, handle, 0, ++ MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, 0, 30); ++ ++ /* ++ * sanity check see whether all commands to this target been ++ * completed ++ */ ++ if (_scsih_scsi_lookup_find_by_target(ioc, scmd->device->id, ++ scmd->device->channel)) ++ r = FAILED; ++ else ++ r = SUCCESS; ++ ioc->tm_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->tm_cmds.mutex); ++ ++ out: ++ printk(MPT2SAS_INFO_FMT "target reset: %s scmd(%p)\n", ++ ioc->name, ((r == SUCCESS) ? "SUCCESS" : "FAILED"), scmd); ++ return r; ++} ++ ++#else /* prior to 2.6.26 kernel */ ++ ++/** ++ * _scsih_dev_reset - eh threads main device reset routine ++ * @sdev: scsi device struct ++ * ++ * Returns SUCCESS if command aborted else FAILED ++ */ ++static int ++_scsih_dev_reset(struct scsi_cmnd *scmd) ++{ ++ struct MPT2SAS_ADAPTER *ioc = shost_private(scmd->device->host); ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ struct _sas_device *sas_device; ++ unsigned long flags; ++ u16 handle; ++ int r; ++ ++ printk(MPT2SAS_INFO_FMT "attempting target reset! scmd(%p)\n", ++ ioc->name, scmd); ++ scsi_print_command(scmd); ++ ++ sas_device_priv_data = scmd->device->hostdata; ++ if (!sas_device_priv_data || !sas_device_priv_data->sas_target) { ++ printk(MPT2SAS_INFO_FMT "target been deleted! scmd(%p)\n", ++ ioc->name, scmd); ++ scmd->result = DID_NO_CONNECT << 16; ++ scmd->scsi_done(scmd); ++ r = SUCCESS; ++ goto out; ++ } ++ ++ /* for hidden raid components obtain the volume_handle */ ++ handle = 0; ++ if (sas_device_priv_data->sas_target->flags & ++ MPT_TARGET_FLAGS_RAID_COMPONENT) { ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = _scsih_sas_device_find_by_handle(ioc, ++ sas_device_priv_data->sas_target->handle); ++ if (sas_device) ++ handle = sas_device->volume_handle; ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ } else ++ handle = sas_device_priv_data->sas_target->handle; ++ ++ if (!handle) { ++ scmd->result = DID_RESET << 16; ++ r = FAILED; ++ goto out; ++ } ++ ++ mutex_lock(&ioc->tm_cmds.mutex); ++ mpt2sas_scsih_issue_tm(ioc, handle, 0, ++ MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, 0, 30); ++ ++ /* ++ * sanity check see whether all commands to this target been ++ * completed ++ */ ++ if (_scsih_scsi_lookup_find_by_target(ioc, scmd->device->id, ++ scmd->device->channel)) ++ r = FAILED; ++ else ++ r = SUCCESS; ++ ioc->tm_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->tm_cmds.mutex); ++ ++ out: ++ printk(MPT2SAS_INFO_FMT "target reset: %s scmd(%p)\n", ++ ioc->name, ((r == SUCCESS) ? "SUCCESS" : "FAILED"), scmd); ++ return r; ++} ++#endif ++ ++/** ++ * _scsih_host_reset - eh threads main host reset routine ++ * @sdev: scsi device struct ++ * ++ * Returns SUCCESS if command aborted else FAILED ++ */ ++static int ++_scsih_host_reset(struct scsi_cmnd *scmd) ++{ ++ struct MPT2SAS_ADAPTER *ioc = shost_private(scmd->device->host); ++ int r, retval; ++ ++ printk(MPT2SAS_INFO_FMT "attempting host reset! scmd(%p)\n", ++ ioc->name, scmd); ++ scsi_print_command(scmd); ++ ++ retval = mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, ++ FORCE_BIG_HAMMER); ++ r = (retval < 0) ? FAILED : SUCCESS; ++ printk(MPT2SAS_INFO_FMT "host reset: %s scmd(%p)\n", ++ ioc->name, ((r == SUCCESS) ? "SUCCESS" : "FAILED"), scmd); ++ ++ return r; ++} ++ ++/** ++ * _scsih_fw_event_add - insert and queue up fw_event ++ * @ioc: per adapter object ++ * @fw_event: object describing the event ++ * Context: This function will acquire ioc->fw_event_lock. ++ * ++ * This adds the firmware event object into link list, then queues it up to ++ * be processed from user context. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_fw_event_add(struct MPT2SAS_ADAPTER *ioc, struct fw_event_work *fw_event) ++{ ++ unsigned long flags; ++ ++ if (ioc->firmware_event_thread == NULL) ++ return; ++ ++ spin_lock_irqsave(&ioc->fw_event_lock, flags); ++ list_add_tail(&fw_event->list, &ioc->fw_event_list); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) ++ INIT_WORK(&fw_event->work, _firmware_event_work); ++#else ++ INIT_WORK(&fw_event->work, _firmware_event_work, (void *)fw_event); ++#endif ++ queue_work(ioc->firmware_event_thread, &fw_event->work); ++ spin_unlock_irqrestore(&ioc->fw_event_lock, flags); ++} ++ ++/** ++ * _scsih_fw_event_free - delete fw_event ++ * @ioc: per adapter object ++ * @fw_event: object describing the event ++ * Context: This function will acquire ioc->fw_event_lock. ++ * ++ * This removes firmware event object from link list, frees associated memory. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_fw_event_free(struct MPT2SAS_ADAPTER *ioc, struct fw_event_work ++ *fw_event) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ioc->fw_event_lock, flags); ++ list_del(&fw_event->list); ++ kfree(fw_event->retries); ++ kfree(fw_event->event_data); ++ kfree(fw_event); ++ spin_unlock_irqrestore(&ioc->fw_event_lock, flags); ++} ++ ++/** ++ * _scsih_fw_event_add - requeue an event ++ * @ioc: per adapter object ++ * @fw_event: object describing the event ++ * Context: This function will acquire ioc->fw_event_lock. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_fw_event_requeue(struct MPT2SAS_ADAPTER *ioc, struct fw_event_work ++ *fw_event, unsigned long delay) ++{ ++ unsigned long flags; ++ ++ if (ioc->firmware_event_thread == NULL) ++ return; ++ ++ spin_lock_irqsave(&ioc->fw_event_lock, flags); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) ++ if (!fw_event->delayed_work_active) { ++ fw_event->delayed_work_active = 1; ++ INIT_DELAYED_WORK(&fw_event->delayed_work, ++ _firmware_event_work_delayed); ++ } ++ queue_delayed_work(ioc->firmware_event_thread, &fw_event->delayed_work, ++ msecs_to_jiffies(delay)); ++#else ++ queue_delayed_work(ioc->firmware_event_thread, &fw_event->work, ++ msecs_to_jiffies(delay)); ++#endif ++ spin_unlock_irqrestore(&ioc->fw_event_lock, flags); ++} ++ ++/** ++ * _scsih_fw_event_off - turn flag off preventing event handling ++ * @ioc: per adapter object ++ * ++ * Used to prevent handling of firmware events during adapter reset ++ * driver unload. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_fw_event_off(struct MPT2SAS_ADAPTER *ioc) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ioc->fw_event_lock, flags); ++ ioc->fw_events_off = 1; ++ spin_unlock_irqrestore(&ioc->fw_event_lock, flags); ++ ++} ++ ++/** ++ * _scsih_fw_event_on - turn flag on allowing firmware event handling ++ * @ioc: per adapter object ++ * ++ * Returns nothing. ++ */ ++static void ++_scsih_fw_event_on(struct MPT2SAS_ADAPTER *ioc) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ioc->fw_event_lock, flags); ++ ioc->fw_events_off = 0; ++ spin_unlock_irqrestore(&ioc->fw_event_lock, flags); ++} ++ ++/** ++ * _scsih_fw_event_cleanup_queue - cleanup event queue ++ * @ioc: per adapter object ++ * ++ * Walk the firmware event queue, either killing timers, or waiting ++ * for outstanding events to complete ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_fw_event_cleanup_queue(struct MPT2SAS_ADAPTER *ioc) ++{ ++ struct fw_event_work *fw_event, *next; ++ ++ if (list_empty(&ioc->fw_event_list) || ++ !ioc->firmware_event_thread || in_interrupt()) ++ return; ++ ++ list_for_each_entry_safe(fw_event, next, &ioc->fw_event_list, list) ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) ++ if (fw_event->delayed_work_active && ++ cancel_delayed_work(&fw_event->delayed_work)) ++ _scsih_fw_event_free(ioc, fw_event); ++#else ++ if (cancel_delayed_work(&fw_event->work)) ++ _scsih_fw_event_free(ioc, fw_event); ++#endif ++} ++ ++/** ++ * _scsih_ublock_io_device - set the device state to SDEV_RUNNING ++ * @ioc: per adapter object ++ * @handle: device handle ++ * ++ * During device pull we need to appropiately set the sdev state. ++ */ ++static void ++_scsih_ublock_io_device(struct MPT2SAS_ADAPTER *ioc, u16 handle) ++{ ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ struct scsi_device *sdev; ++ ++ shost_for_each_device(sdev, ioc->shost) { ++ sas_device_priv_data = sdev->hostdata; ++ if (!sas_device_priv_data) ++ continue; ++ if (!sas_device_priv_data->block) ++ continue; ++ if (sas_device_priv_data->sas_target->handle == handle) { ++ dewtprintk(ioc, sdev_printk(KERN_INFO, sdev, ++ MPT2SAS_INFO_FMT "SDEV_RUNNING: " ++ "handle(0x%04x)\n", ioc->name, handle)); ++ sas_device_priv_data->block = 0; ++ scsi_device_set_state(sdev, SDEV_RUNNING); ++ } ++ } ++} ++ ++/** ++ * _scsih_block_io_device - set the device state to SDEV_BLOCK ++ * @ioc: per adapter object ++ * @handle: device handle ++ * ++ * During device pull we need to appropiately set the sdev state. ++ */ ++static void ++_scsih_block_io_device(struct MPT2SAS_ADAPTER *ioc, u16 handle) ++{ ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ struct scsi_device *sdev; ++ ++ shost_for_each_device(sdev, ioc->shost) { ++ sas_device_priv_data = sdev->hostdata; ++ if (!sas_device_priv_data) ++ continue; ++ if (sas_device_priv_data->block) ++ continue; ++ if (sas_device_priv_data->sas_target->handle == handle) { ++ dewtprintk(ioc, sdev_printk(KERN_INFO, sdev, ++ MPT2SAS_INFO_FMT "SDEV_BLOCK: " ++ "handle(0x%04x)\n", ioc->name, handle)); ++ sas_device_priv_data->block = 1; ++ scsi_device_set_state(sdev, SDEV_BLOCK); ++ } ++ } ++} ++ ++/** ++ * _scsih_block_io_to_children_attached_to_ex ++ * @ioc: per adapter object ++ * @sas_expander: the sas_device object ++ * ++ * This routine set sdev state to SDEV_BLOCK for all devices ++ * attached to this expander. This function called when expander is ++ * pulled. ++ */ ++static void ++_scsih_block_io_to_children_attached_to_ex(struct MPT2SAS_ADAPTER *ioc, ++ struct _sas_node *sas_expander) ++{ ++ struct _sas_port *mpt2sas_port; ++ struct _sas_device *sas_device; ++ struct _sas_node *expander_sibling; ++ unsigned long flags; ++ ++ if (!sas_expander) ++ return; ++ ++ list_for_each_entry(mpt2sas_port, ++ &sas_expander->sas_port_list, port_list) { ++ if (mpt2sas_port->remote_identify.device_type == ++ SAS_END_DEVICE) { ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = ++ mpt2sas_scsih_sas_device_find_by_sas_address(ioc, ++ mpt2sas_port->remote_identify.sas_address); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ if (!sas_device) ++ continue; ++ _scsih_block_io_device(ioc, sas_device->handle); ++ } ++ } ++ ++ list_for_each_entry(mpt2sas_port, ++ &sas_expander->sas_port_list, port_list) { ++ ++ if (mpt2sas_port->remote_identify.device_type == ++ MPI2_SAS_DEVICE_INFO_EDGE_EXPANDER || ++ mpt2sas_port->remote_identify.device_type == ++ MPI2_SAS_DEVICE_INFO_FANOUT_EXPANDER) { ++ ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ expander_sibling = ++ mpt2sas_scsih_expander_find_by_sas_address( ++ ioc, mpt2sas_port->remote_identify.sas_address); ++ spin_unlock_irqrestore(&ioc->sas_node_lock, flags); ++ _scsih_block_io_to_children_attached_to_ex(ioc, ++ expander_sibling); ++ } ++ } ++} ++ ++/** ++ * _scsih_block_io_to_children_attached_directly ++ * @ioc: per adapter object ++ * @event_data: topology change event data ++ * ++ * This routine set sdev state to SDEV_BLOCK for all devices ++ * direct attached during device pull. ++ */ ++static void ++_scsih_block_io_to_children_attached_directly(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventDataSasTopologyChangeList_t *event_data) ++{ ++ int i; ++ u16 handle; ++ u16 reason_code; ++ u8 phy_number; ++ u8 link_rate; ++ ++ for (i = 0; i < event_data->NumEntries; i++) { ++ handle = le16_to_cpu(event_data->PHY[i].AttachedDevHandle); ++ if (!handle) ++ continue; ++ phy_number = event_data->StartPhyNum + i; ++ reason_code = event_data->PHY[i].PhyStatus & ++ MPI2_EVENT_SAS_TOPO_RC_MASK; ++ if (reason_code == MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING) ++ _scsih_block_io_device(ioc, handle); ++ if (reason_code == MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED) { ++ link_rate = event_data->PHY[i].LinkRate >> 4; ++ if (link_rate >= MPI2_SAS_NEG_LINK_RATE_1_5) ++ _scsih_ublock_io_device(ioc, handle); ++ } ++ } ++} ++ ++/** ++ * _scsih_check_topo_delete_events - sanity check on topo events ++ * @ioc: per adapter object ++ * @event_data: the event data payload ++ * ++ * This routine added to better handle cable breaker. ++ * ++ * This handles the case where driver recieves multiple expander ++ * add and delete events in a single shot. When there is a delete event ++ * the routine will void any pending add events waiting in the event queue. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_check_topo_delete_events(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventDataSasTopologyChangeList_t *event_data) ++{ ++ struct fw_event_work *fw_event; ++ Mpi2EventDataSasTopologyChangeList_t *local_event_data; ++ u16 expander_handle; ++ struct _sas_node *sas_expander; ++ unsigned long flags; ++ ++ expander_handle = le16_to_cpu(event_data->ExpanderDevHandle); ++ if (expander_handle < ioc->sas_hba.num_phys) { ++ _scsih_block_io_to_children_attached_directly(ioc, event_data); ++ return; ++ } ++ ++ if (event_data->ExpStatus == MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING ++ || event_data->ExpStatus == MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING) { ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ sas_expander = mpt2sas_scsih_expander_find_by_handle(ioc, ++ expander_handle); ++ spin_unlock_irqrestore(&ioc->sas_node_lock, flags); ++ _scsih_block_io_to_children_attached_to_ex(ioc, sas_expander); ++ } else if (event_data->ExpStatus == MPI2_EVENT_SAS_TOPO_ES_RESPONDING) ++ _scsih_block_io_to_children_attached_directly(ioc, event_data); ++ ++ if (event_data->ExpStatus != MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING) ++ return; ++ ++ /* mark ignore flag for pending events */ ++ spin_lock_irqsave(&ioc->fw_event_lock, flags); ++ list_for_each_entry(fw_event, &ioc->fw_event_list, list) { ++ if (fw_event->event != MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST || ++ fw_event->ignore) ++ continue; ++ local_event_data = fw_event->event_data; ++ if (local_event_data->ExpStatus == ++ MPI2_EVENT_SAS_TOPO_ES_ADDED || ++ local_event_data->ExpStatus == ++ MPI2_EVENT_SAS_TOPO_ES_RESPONDING) { ++ if (le16_to_cpu(local_event_data->ExpanderDevHandle) == ++ expander_handle) { ++ dewtprintk(ioc, printk(MPT2SAS_DEBUG_FMT ++ "setting ignoring flag\n", ioc->name)); ++ fw_event->ignore = 1; ++ } ++ } ++ } ++ spin_unlock_irqrestore(&ioc->fw_event_lock, flags); ++} ++ ++/** ++ * _scsih_flush_running_cmds - completing outstanding commands. ++ * @ioc: per adapter object ++ * ++ * The flushing out of all pending scmd commands following host reset, ++ * where all IO is dropped to the floor. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_flush_running_cmds(struct MPT2SAS_ADAPTER *ioc) ++{ ++ struct scsi_cmnd *scmd; ++ u16 smid; ++ u16 count = 0; ++ ++ for (smid = 1; smid <= ioc->request_depth; smid++) { ++ scmd = _scsih_scsi_lookup_getclear(ioc, smid); ++ if (!scmd) ++ continue; ++ count++; ++ mpt2sas_base_free_smid(ioc, smid); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ if (scmd->use_sg) { ++ pci_unmap_sg(ioc->pdev, ++ (struct scatterlist *) scmd->request_buffer, ++ scmd->use_sg, scmd->sc_data_direction); ++ } else if (scmd->request_bufflen) { ++ pci_unmap_single(ioc->pdev, ++ scmd->SCp.dma_handle, scmd->request_bufflen, ++ scmd->sc_data_direction); ++ } ++#else ++ scsi_dma_unmap(scmd); ++#endif ++ scmd->result = DID_RESET << 16; ++ scmd->scsi_done(scmd); ++ } ++ dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "completing %d cmds\n", ++ ioc->name, count)); ++} ++ ++#if defined(EEDP_SUPPORT) ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) ++static u8 opcode_protection[256] = { ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, PRO_R, 0, PRO_W, 0, 0, 0, PRO_W, PRO_V, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, PRO_W, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, PRO_R, 0, PRO_W, 0, 0, 0, PRO_W, PRO_V, ++ 0, 0, 0, PRO_W, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, PRO_R, 0, PRO_W, 0, 0, 0, PRO_W, PRO_V, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; ++#endif ++/** ++ * _scsih_setup_eedp - setup MPI request for EEDP transfer ++ * @scmd: pointer to scsi command object ++ * @mpi_request: pointer to the SCSI_IO reqest message frame ++ * ++ * Supporting protection 1 and 3. ++ * ++ * Returns nothing ++ */ ++static void ++_scsih_setup_eedp(struct scsi_cmnd *scmd, Mpi2SCSIIORequest_t *mpi_request) ++{ ++ u16 eedp_flags; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ u8 scsi_opcode; ++ ++ sas_device_priv_data = scmd->device->hostdata; ++ ++ if (!sas_device_priv_data->eedp_enable) ++ return; ++ ++ /* check whether scsi opcode supports eedp transfer */ ++ scsi_opcode = scmd->cmnd[0]; ++ eedp_flags = opcode_protection[scsi_opcode]; ++ if (!eedp_flags) ++ return; ++ ++ /* set RDPROTECT, WRPROTECT, VRPROTECT bits to (001b) */ ++ scmd->cmnd[1] = (scmd->cmnd[1] & 0x1F) | 0x20; ++ ++ mpi_request->EEDPBlockSize = scmd->device->sector_size; ++ ++ switch (sas_device_priv_data->eedp_type) { ++ case 1: /* type 1 */ ++ ++ /* ++ * enable ref/guard checking ++ * auto increment ref tag ++ */ ++ mpi_request->EEDPFlags = eedp_flags | ++ MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG | ++ MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG | ++ MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD; ++ mpi_request->CDB.EEDP32.PrimaryReferenceTag = ++ cpu_to_be32(scsi_get_lba(scmd)); ++ ++ break; ++ ++ case 3: /* type 3 */ ++ ++ /* ++ * enable guard checking ++ */ ++ mpi_request->EEDPFlags = eedp_flags | ++ MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD; ++ ++ break; ++ } ++ ++#else /* sles11 and newer */ ++ ++ unsigned char prot_op = scsi_get_prot_op(scmd); ++ unsigned char prot_type = scsi_get_prot_type(scmd); ++ ++ if (prot_type == SCSI_PROT_DIF_TYPE0 || ++ prot_type == SCSI_PROT_DIF_TYPE2 || ++ prot_op == SCSI_PROT_NORMAL) ++ return; ++ ++ if (prot_op == SCSI_PROT_READ_STRIP) ++ eedp_flags = MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP; ++ else if (prot_op == SCSI_PROT_WRITE_INSERT) ++ eedp_flags = MPI2_SCSIIO_EEDPFLAGS_INSERT_OP; ++ else ++ return; ++ ++ mpi_request->EEDPBlockSize = scmd->device->sector_size; ++ ++ switch (prot_type) { ++ case SCSI_PROT_DIF_TYPE1: ++ ++ /* ++ * enable ref/guard checking ++ * auto increment ref tag ++ */ ++ mpi_request->EEDPFlags = eedp_flags | ++ MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG | ++ MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG | ++ MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD; ++ mpi_request->CDB.EEDP32.PrimaryReferenceTag = ++ cpu_to_be32(scsi_get_lba(scmd)); ++ ++ break; ++ ++ case SCSI_PROT_DIF_TYPE3: ++ ++ /* ++ * enable guard checking ++ */ ++ mpi_request->EEDPFlags = eedp_flags | ++ MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD; ++ ++ break; ++ } ++#endif ++} ++ ++/** ++ * _scsih_eedp_error_handling - return sense code for EEDP errors ++ * @scmd: pointer to scsi command object ++ * @ioc_status: ioc status ++ * ++ * Returns nothing ++ */ ++static void ++_scsih_eedp_error_handling(struct scsi_cmnd *scmd, u16 ioc_status) ++{ ++ u8 ascq; ++ u8 sk; ++ u8 host_byte; ++ ++ switch (ioc_status) { ++ case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: ++ ascq = 0x01; ++ break; ++ case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: ++ ascq = 0x02; ++ break; ++ case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: ++ ascq = 0x03; ++ break; ++ default: ++ ascq = 0x00; ++ break; ++ } ++ ++ if (scmd->sc_data_direction == DMA_TO_DEVICE) { ++ sk = ILLEGAL_REQUEST; ++ host_byte = DID_ABORT; ++ } else { ++ sk = ABORTED_COMMAND; ++ host_byte = DID_OK; ++ } ++ ++ mpt_scsi_build_sense_buffer(0, scmd->sense_buffer, sk, 0x10, ascq); ++ scmd->result = DRIVER_SENSE << 24 | (host_byte << 16) | ++ SAM_STAT_CHECK_CONDITION; ++} ++#endif /* EEDP_SUPPORT Support */ ++ ++/** ++ * _scsih_qcmd - main scsi request entry point ++ * @scmd: pointer to scsi command object ++ * @done: function pointer to be invoked on completion ++ * ++ * The callback index is set inside `ioc->scsi_io_cb_idx`. ++ * ++ * Returns 0 on success. If there's a failure, return either: ++ * SCSI_MLQUEUE_DEVICE_BUSY if the device queue is full, or ++ * SCSI_MLQUEUE_HOST_BUSY if the entire host queue is full ++ */ ++static int ++_scsih_qcmd(struct scsi_cmnd *scmd, void (*done)(struct scsi_cmnd *)) ++{ ++ struct MPT2SAS_ADAPTER *ioc = shost_private(scmd->device->host); ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ struct MPT2SAS_TARGET *sas_target_priv_data; ++ Mpi2SCSIIORequest_t *mpi_request; ++ u32 mpi_control; ++ u16 smid; ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ if (ioc->logging_level & MPT_DEBUG_SCSI) ++ scsi_print_command(scmd); ++#endif ++ ++ scmd->scsi_done = done; ++ sas_device_priv_data = scmd->device->hostdata; ++ if (!sas_device_priv_data) { ++ scmd->result = DID_NO_CONNECT << 16; ++ scmd->scsi_done(scmd); ++ return 0; ++ } ++ ++ sas_target_priv_data = sas_device_priv_data->sas_target; ++ if (!sas_target_priv_data || sas_target_priv_data->handle == ++ MPT2SAS_INVALID_DEVICE_HANDLE || sas_target_priv_data->deleted) { ++ scmd->result = DID_NO_CONNECT << 16; ++ scmd->scsi_done(scmd); ++ return 0; ++ } ++ ++ /* see if we are busy with task managment stuff */ ++ if (sas_target_priv_data->tm_busy) ++ return SCSI_MLQUEUE_DEVICE_BUSY; ++ else if (ioc->shost_recovery || ioc->ioc_link_reset_in_progress) ++ return SCSI_MLQUEUE_HOST_BUSY; ++ ++ if (scmd->sc_data_direction == DMA_FROM_DEVICE) ++ mpi_control = MPI2_SCSIIO_CONTROL_READ; ++ else if (scmd->sc_data_direction == DMA_TO_DEVICE) ++ mpi_control = MPI2_SCSIIO_CONTROL_WRITE; ++ else ++ mpi_control = MPI2_SCSIIO_CONTROL_NODATATRANSFER; ++ ++ /* set tags */ ++ if (!(sas_device_priv_data->flags & MPT_DEVICE_FLAGS_INIT)) { ++ if (scmd->device->tagged_supported) { ++ if (scmd->device->ordered_tags) ++ mpi_control |= MPI2_SCSIIO_CONTROL_ORDEREDQ; ++ else ++ mpi_control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; ++ } else ++/* MPI Revision I (UNIT = 0xA) - removed MPI2_SCSIIO_CONTROL_UNTAGGED */ ++/* mpi_control |= MPI2_SCSIIO_CONTROL_UNTAGGED; ++ */ ++ mpi_control |= (0x500); ++ } else ++ mpi_control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; ++ ++ if ((sas_device_priv_data->flags & MPT_DEVICE_TLR_ON)) ++ mpi_control |= MPI2_SCSIIO_CONTROL_TLR_ON; ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->scsi_io_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ goto out; ++ } ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ memset(mpi_request, 0, sizeof(Mpi2SCSIIORequest_t)); ++#if defined(EEDP_SUPPORT) ++ _scsih_setup_eedp(scmd, mpi_request); ++#endif ++ mpi_request->Function = MPI2_FUNCTION_SCSI_IO_REQUEST; ++ if (sas_device_priv_data->sas_target->flags & ++ MPT_TARGET_FLAGS_RAID_COMPONENT) ++ mpi_request->Function = MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH; ++ else ++ mpi_request->Function = MPI2_FUNCTION_SCSI_IO_REQUEST; ++ mpi_request->DevHandle = ++ cpu_to_le16(sas_device_priv_data->sas_target->handle); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ mpi_request->DataLength = cpu_to_le32(scmd->request_bufflen); ++#else ++ mpi_request->DataLength = cpu_to_le32(scsi_bufflen(scmd)); ++#endif ++ mpi_request->Control = cpu_to_le32(mpi_control); ++ mpi_request->IoFlags = cpu_to_le16(scmd->cmd_len); ++ mpi_request->MsgFlags = MPI2_SCSIIO_MSGFLAGS_SYSTEM_SENSE_ADDR; ++ mpi_request->SenseBufferLength = SCSI_SENSE_BUFFERSIZE; ++ mpi_request->SenseBufferLowAddress = ++ (u32)mpt2sas_base_get_sense_buffer_dma(ioc, smid); ++ mpi_request->SGLOffset0 = offsetof(Mpi2SCSIIORequest_t, SGL) / 4; ++ mpi_request->SGLFlags = cpu_to_le16(MPI2_SCSIIO_SGLFLAGS_TYPE_MPI + ++ MPI2_SCSIIO_SGLFLAGS_SYSTEM_ADDR); ++ ++ int_to_scsilun(sas_device_priv_data->lun, (struct scsi_lun *) ++ mpi_request->LUN); ++ memcpy(mpi_request->CDB.CDB32, scmd->cmnd, scmd->cmd_len); ++ ++ if (!mpi_request->DataLength) { ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request->SGL); ++ } else { ++ if (_scsih_build_scatter_gather(ioc, scmd, smid)) { ++ mpt2sas_base_free_smid(ioc, smid); ++ goto out; ++ } ++ } ++ ++ _scsih_scsi_lookup_set(ioc, smid, scmd); ++ mpt2sas_base_put_smid_scsi_io(ioc, smid, 0, ++ sas_device_priv_data->sas_target->handle); ++ return 0; ++ ++ out: ++ return SCSI_MLQUEUE_HOST_BUSY; ++} ++ ++/** ++ * _scsih_normalize_sense - normalize descriptor and fixed format sense data ++ * @sense_buffer: sense data returned by target ++ * @data: normalized skey/asc/ascq ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_normalize_sense(char *sense_buffer, struct sense_info *data) ++{ ++ if ((sense_buffer[0] & 0x7F) >= 0x72) { ++ /* descriptor format */ ++ data->skey = sense_buffer[1] & 0x0F; ++ data->asc = sense_buffer[2]; ++ data->ascq = sense_buffer[3]; ++ } else { ++ /* fixed format */ ++ data->skey = sense_buffer[2] & 0x0F; ++ data->asc = sense_buffer[12]; ++ data->ascq = sense_buffer[13]; ++ } ++} ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++/** ++ * _scsih_scsi_ioc_info - translated non-succesfull SCSI_IO request ++ * @ioc: per adapter object ++ * @scmd: pointer to scsi command object ++ * @mpi_reply: reply mf payload returned from firmware ++ * ++ * scsi_status - SCSI Status code returned from target device ++ * scsi_state - state info associated with SCSI_IO determined by ioc ++ * ioc_status - ioc supplied status info ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_scsi_ioc_info(struct MPT2SAS_ADAPTER *ioc, struct scsi_cmnd *scmd, ++ Mpi2SCSIIOReply_t *mpi_reply, u16 smid) ++{ ++ u32 response_info; ++ u8 *response_bytes; ++ u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ u8 scsi_state = mpi_reply->SCSIState; ++ u8 scsi_status = mpi_reply->SCSIStatus; ++ char *desc_ioc_state = NULL; ++ char *desc_scsi_status = NULL; ++ char *desc_scsi_state = ioc->tmp_string; ++ u32 log_info = le32_to_cpu(mpi_reply->IOCLogInfo); ++ ++ if (log_info == 0x31170000) ++ return; ++ ++ switch (ioc_status) { ++ case MPI2_IOCSTATUS_SUCCESS: ++ desc_ioc_state = "success"; ++ break; ++ case MPI2_IOCSTATUS_INVALID_FUNCTION: ++ desc_ioc_state = "invalid function"; ++ break; ++ case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: ++ desc_ioc_state = "scsi recovered error"; ++ break; ++ case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE: ++ desc_ioc_state = "scsi invalid dev handle"; ++ break; ++ case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: ++ desc_ioc_state = "scsi device not there"; ++ break; ++ case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: ++ desc_ioc_state = "scsi data overrun"; ++ break; ++ case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: ++ desc_ioc_state = "scsi data underrun"; ++ break; ++ case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: ++ desc_ioc_state = "scsi io data error"; ++ break; ++ case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: ++ desc_ioc_state = "scsi protocol error"; ++ break; ++ case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: ++ desc_ioc_state = "scsi task terminated"; ++ break; ++ case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: ++ desc_ioc_state = "scsi residual mismatch"; ++ break; ++ case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED: ++ desc_ioc_state = "scsi task mgmt failed"; ++ break; ++ case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: ++ desc_ioc_state = "scsi ioc terminated"; ++ break; ++ case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: ++ desc_ioc_state = "scsi ext terminated"; ++ break; ++#if defined(EEDP_SUPPORT) ++ case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: ++ desc_ioc_state = "eedp guard error"; ++ break; ++ case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: ++ desc_ioc_state = "eedp ref tag error"; ++ break; ++ case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: ++ desc_ioc_state = "eedp app tag error"; ++ break; ++#endif /* EEDP Support */ ++ default: ++ desc_ioc_state = "unknown"; ++ break; ++ } ++ ++ switch (scsi_status) { ++ case MPI2_SCSI_STATUS_GOOD: ++ desc_scsi_status = "good"; ++ break; ++ case MPI2_SCSI_STATUS_CHECK_CONDITION: ++ desc_scsi_status = "check condition"; ++ break; ++ case MPI2_SCSI_STATUS_CONDITION_MET: ++ desc_scsi_status = "condition met"; ++ break; ++ case MPI2_SCSI_STATUS_BUSY: ++ desc_scsi_status = "busy"; ++ break; ++ case MPI2_SCSI_STATUS_INTERMEDIATE: ++ desc_scsi_status = "intermediate"; ++ break; ++ case MPI2_SCSI_STATUS_INTERMEDIATE_CONDMET: ++ desc_scsi_status = "intermediate condmet"; ++ break; ++ case MPI2_SCSI_STATUS_RESERVATION_CONFLICT: ++ desc_scsi_status = "reservation conflict"; ++ break; ++ case MPI2_SCSI_STATUS_COMMAND_TERMINATED: ++ desc_scsi_status = "command terminated"; ++ break; ++ case MPI2_SCSI_STATUS_TASK_SET_FULL: ++ desc_scsi_status = "task set full"; ++ break; ++ case MPI2_SCSI_STATUS_ACA_ACTIVE: ++ desc_scsi_status = "aca active"; ++ break; ++ case MPI2_SCSI_STATUS_TASK_ABORTED: ++ desc_scsi_status = "task aborted"; ++ break; ++ default: ++ desc_scsi_status = "unknown"; ++ break; ++ } ++ ++ desc_scsi_state[0] = '\0'; ++ if (!scsi_state) ++ desc_scsi_state = " "; ++ if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) ++ strcat(desc_scsi_state, "response info "); ++ if (scsi_state & MPI2_SCSI_STATE_TERMINATED) ++ strcat(desc_scsi_state, "state terminated "); ++ if (scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) ++ strcat(desc_scsi_state, "no status "); ++ if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_FAILED) ++ strcat(desc_scsi_state, "autosense failed "); ++ if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) ++ strcat(desc_scsi_state, "autosense valid "); ++ ++ scsi_print_command(scmd); ++ printk(MPT2SAS_WARN_FMT "\tdev handle(0x%04x), " ++ "ioc_status(%s)(0x%04x), smid(%d)\n", ioc->name, ++ le16_to_cpu(mpi_reply->DevHandle), desc_ioc_state, ++ ioc_status, smid); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ printk(MPT2SAS_WARN_FMT "\trequest_len(%d), underflow(%d), " ++ "resid(%d)\n", ioc->name, scmd->request_bufflen, scmd->underflow, ++ scmd->resid); ++#else ++ printk(MPT2SAS_WARN_FMT "\trequest_len(%d), underflow(%d), " ++ "resid(%d)\n", ioc->name, scsi_bufflen(scmd), scmd->underflow, ++ scsi_get_resid(scmd)); ++#endif ++ printk(MPT2SAS_WARN_FMT "\ttag(%d), transfer_count(%d), " ++ "sc->result(0x%08x)\n", ioc->name, le16_to_cpu(mpi_reply->TaskTag), ++ le32_to_cpu(mpi_reply->TransferCount), scmd->result); ++ printk(MPT2SAS_WARN_FMT "\tscsi_status(%s)(0x%02x), " ++ "scsi_state(%s)(0x%02x)\n", ioc->name, desc_scsi_status, ++ scsi_status, desc_scsi_state, scsi_state); ++ ++ if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) { ++ struct sense_info data; ++ _scsih_normalize_sense(scmd->sense_buffer, &data); ++ printk(MPT2SAS_WARN_FMT "\t[sense_key,asc,ascq]: " ++ "[0x%02x,0x%02x,0x%02x], count(%d)\n", ioc->name, data.skey, ++ data.asc, data.ascq, le32_to_cpu(mpi_reply->SenseCount)); ++ } ++ ++ if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) { ++ response_info = le32_to_cpu(mpi_reply->ResponseInfo); ++ response_bytes = (u8 *)&response_info; ++ _scsih_response_code(ioc, response_bytes[3]); ++ } ++} ++#endif ++ ++#ifdef MPT2SAS_MULTIPATH ++/** ++ * _scsih_abort_task_set - issue a delayed ABRT_TASK_SET ++ * @ioc: per adapter object ++ * @VF_ID: virtual function id ++ * @tm_data: contains handle/lun ++ * ++ * issue TM following bus reset using custom event MPT2SAS_ABRT_TASK_SET ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_abort_task_set(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ struct mpt2sas_abort_task_set *tm_data) ++{ ++ mutex_lock(&ioc->tm_cmds.mutex); ++ mpt2sas_scsih_issue_tm(ioc, tm_data->handle, tm_data->lun, ++ MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, 0, 5); ++ ioc->tm_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->tm_cmds.mutex); ++} ++ ++/** ++ * _scsih_abort_task_set_schedule - schedule a ABRT_TASK_SET ++ * @ioc: per adapter object ++ * @handle: device handle ++ * @lun: lun ++ * @VF_ID: virtual function id ++ * ++ * schedule a ABRT_TASK_SET following UA bus reset ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_abort_task_set_schedule(struct MPT2SAS_ADAPTER *ioc, u16 handle, ++ u32 lun, u8 VF_ID, ulong delay) ++{ ++ struct fw_event_work *fw_event; ++ struct mpt2sas_abort_task_set *tm_data; ++ unsigned long flags; ++ ++ if (ioc->remove_host) ++ return; ++ ++ fw_event = kzalloc(sizeof(struct fw_event_work), GFP_ATOMIC); ++ if (!fw_event) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ tm_data = kzalloc(sizeof(struct mpt2sas_abort_task_set), GFP_ATOMIC); ++ if (!tm_data) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ kfree(fw_event); ++ return; ++ } ++ ++ fw_event->event_data = tm_data; ++ tm_data->handle = handle; ++ tm_data->lun = lun; ++ fw_event->ioc = ioc; ++ fw_event->VF_ID = VF_ID; ++ fw_event->event = MPT2SAS_ABRT_TASK_SET; ++ ++ spin_lock_irqsave(&ioc->fw_event_lock, flags); ++ list_add_tail(&fw_event->list, &ioc->fw_event_list); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) ++ INIT_WORK(&fw_event->work, _firmware_event_work); ++ queue_work(ioc->firmware_event_thread, &fw_event->work); ++#else ++ INIT_WORK(&fw_event->work, _firmware_event_work, (void *)fw_event); ++ queue_delayed_work(ioc->firmware_event_thread, &fw_event->work, ++ msecs_to_jiffies(delay)); ++#endif ++ spin_unlock_irqrestore(&ioc->fw_event_lock, flags); ++} ++ ++/** ++ * mpt2sas_scsih_check_tm_for_multipath - ++ * @ioc: per adapter object ++ * @handle: device handle ++ * @task_type: ++ * ++ * For multipath, a target reset to one path will kill all the IO to the ++ * other. This code issues an abrt_task_set to the other path, so as ++ * to prevent timeouts. ++ */ ++void ++mpt2sas_scsih_check_tm_for_multipath(struct MPT2SAS_ADAPTER *ioc, u16 handle, ++ u8 task_type) ++{ ++ struct MPT2SAS_ADAPTER *ioc_alt; ++ struct _sas_device *sas_device, *sas_device_alt; ++ unsigned long flags; ++ struct scsi_device *sdev; ++ ++ if (mpt2sas_multipath == -1 || mpt2sas_multipath == 0) ++ return; ++ ++ if (task_type != MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET) ++ return; ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = _scsih_sas_device_find_by_handle(ioc, handle); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ ++ if (!sas_device || !sas_device->sas_device_alt) ++ return; ++ ++ sas_device_alt = sas_device->sas_device_alt; ++ ioc_alt = sas_device_alt->ioc; ++ ++ /* sending abort task 5 seconds later on alternate path */ ++ shost_for_each_device(sdev, ioc_alt->shost) { ++ if (sdev->id != sas_device_alt->id || ++ sdev->channel != sas_device_alt->channel) ++ continue; ++ _scsih_abort_task_set_schedule(ioc_alt, ++ sas_device_alt->handle, sdev->lun, 0, 5000); ++ } ++} ++#endif ++ ++/** ++ * _scsih_smart_predicted_fault - illuminate Fault LED ++ * @ioc: per adapter object ++ * @handle: device handle ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_smart_predicted_fault(struct MPT2SAS_ADAPTER *ioc, u16 handle) ++{ ++ Mpi2SepReply_t mpi_reply; ++ Mpi2SepRequest_t mpi_request; ++ struct scsi_target *starget; ++ struct MPT2SAS_TARGET *sas_target_priv_data; ++ Mpi2EventNotificationReply_t *event_reply; ++ Mpi2EventDataSasDeviceStatusChange_t *event_data; ++ struct _sas_device *sas_device; ++ ssize_t sz; ++ unsigned long flags; ++ ++ /* only handle non-raid devices */ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = _scsih_sas_device_find_by_handle(ioc, handle); ++ if (!sas_device) { ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ return; ++ } ++ starget = sas_device->starget; ++ sas_target_priv_data = starget->hostdata; ++ ++ if ((sas_target_priv_data->flags & MPT_TARGET_FLAGS_RAID_COMPONENT) || ++ ((sas_target_priv_data->flags & MPT_TARGET_FLAGS_VOLUME))) { ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ return; ++ } ++ starget_printk(KERN_WARNING, starget, "predicted fault\n"); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ ++ if (ioc->pdev->subsystem_vendor == PCI_VENDOR_ID_IBM) { ++ memset(&mpi_request, 0, sizeof(Mpi2SepRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR; ++ mpi_request.Action = MPI2_SEP_REQ_ACTION_WRITE_STATUS; ++ mpi_request.SlotStatus = ++ MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT; ++ mpi_request.DevHandle = cpu_to_le16(handle); ++ mpi_request.Flags = MPI2_SEP_REQ_FLAGS_DEVHANDLE_ADDRESS; ++ if ((mpt2sas_base_scsi_enclosure_processor(ioc, &mpi_reply, ++ &mpi_request)) != 0) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ if (mpi_reply.IOCStatus || mpi_reply.IOCLogInfo) { ++ dewtprintk(ioc, printk(MPT2SAS_INFO_FMT ++ "enclosure_processor: ioc_status (0x%04x), " ++ "loginfo(0x%08x)\n", ioc->name, ++ le16_to_cpu(mpi_reply.IOCStatus), ++ le32_to_cpu(mpi_reply.IOCLogInfo))); ++ return; ++ } ++ } ++ ++ /* insert into event log */ ++ sz = offsetof(Mpi2EventNotificationReply_t, EventData) + ++ sizeof(Mpi2EventDataSasDeviceStatusChange_t); ++ event_reply = kzalloc(sz, GFP_KERNEL); ++ if (!event_reply) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ event_reply->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; ++ event_reply->Event = ++ cpu_to_le16(MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE); ++ event_reply->MsgLength = sz/4; ++ event_reply->EventDataLength = ++ cpu_to_le16(sizeof(Mpi2EventDataSasDeviceStatusChange_t)/4); ++ event_data = (Mpi2EventDataSasDeviceStatusChange_t *) ++ event_reply->EventData; ++ event_data->ReasonCode = MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA; ++ event_data->ASC = 0x5D; ++ event_data->DevHandle = cpu_to_le16(handle); ++ event_data->SASAddress = cpu_to_le64(sas_target_priv_data->sas_address); ++ mpt2sas_ctl_add_to_event_log(ioc, event_reply); ++ kfree(event_reply); ++} ++ ++/** ++ * _scsih_io_done - scsi request callback ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @VF_ID: virtual function id ++ * @reply: reply message frame(lower 32bit addr) ++ * ++ * Callback handler when using _scsih_qcmd. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_io_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, u32 reply) ++{ ++ Mpi2SCSIIORequest_t *mpi_request; ++ Mpi2SCSIIOReply_t *mpi_reply; ++ struct scsi_cmnd *scmd; ++ u16 ioc_status; ++ u32 xfer_cnt; ++ u8 scsi_state; ++ u8 scsi_status; ++ u32 log_info; ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ u32 response_code; ++ ++ mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply); ++ scmd = _scsih_scsi_lookup_getclear(ioc, smid); ++ if (scmd == NULL) ++ return; ++ ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ++ if (mpi_reply == NULL) { ++ scmd->result = DID_OK << 16; ++ goto out; ++ } ++ ++ sas_device_priv_data = scmd->device->hostdata; ++ if (!sas_device_priv_data || !sas_device_priv_data->sas_target || ++ sas_device_priv_data->sas_target->deleted) { ++ scmd->result = DID_NO_CONNECT << 16; ++ goto out; ++ } ++ ++ /* turning off TLR */ ++ if (!sas_device_priv_data->tlr_snoop_check) { ++ sas_device_priv_data->tlr_snoop_check++; ++ if (sas_device_priv_data->flags & MPT_DEVICE_TLR_ON) { ++ response_code = (le32_to_cpu(mpi_reply->ResponseInfo) ++ >> 24); ++ if (response_code == ++ MPI2_SCSITASKMGMT_RSP_INVALID_FRAME) ++ sas_device_priv_data->flags &= ++ ~MPT_DEVICE_TLR_ON; ++ } ++ } ++ ++ xfer_cnt = le32_to_cpu(mpi_reply->TransferCount); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ scmd->resid = scmd->request_bufflen - xfer_cnt; ++#else ++ scsi_set_resid(scmd, scsi_bufflen(scmd) - xfer_cnt); ++#endif ++ ioc_status = le16_to_cpu(mpi_reply->IOCStatus); ++ if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) ++ log_info = le32_to_cpu(mpi_reply->IOCLogInfo); ++ else ++ log_info = 0; ++ ioc_status &= MPI2_IOCSTATUS_MASK; ++ scsi_state = mpi_reply->SCSIState; ++ scsi_status = mpi_reply->SCSIStatus; ++ ++ if (ioc_status == MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN && xfer_cnt == 0 && ++ (scsi_status == MPI2_SCSI_STATUS_BUSY || ++ scsi_status == MPI2_SCSI_STATUS_RESERVATION_CONFLICT || ++ scsi_status == MPI2_SCSI_STATUS_TASK_SET_FULL)) { ++ ioc_status = MPI2_IOCSTATUS_SUCCESS; ++ } ++ ++ if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) { ++ struct sense_info data; ++ const void *sense_data = mpt2sas_base_get_sense_buffer(ioc, ++ smid); ++ u32 sz = min_t(u32, SCSI_SENSE_BUFFERSIZE, ++ le32_to_cpu(mpi_reply->SenseCount)); ++ memcpy(scmd->sense_buffer, sense_data, sz); ++ _scsih_normalize_sense(scmd->sense_buffer, &data); ++ /* failure prediction threshold exceeded */ ++ if (data.asc == 0x5D) ++ _scsih_smart_predicted_fault(ioc, ++ le16_to_cpu(mpi_reply->DevHandle)); ++ } ++ ++ switch (ioc_status) { ++ case MPI2_IOCSTATUS_BUSY: ++ case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: ++ scmd->result = SAM_STAT_BUSY; ++ break; ++ ++ case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: ++ scmd->result = DID_NO_CONNECT << 16; ++ break; ++ ++ case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: ++ if (sas_device_priv_data->block) { ++ scmd->result = (DID_BUS_BUSY << 16); ++ break; ++ } ++ ++ case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: ++ case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: ++ scmd->result = DID_RESET << 16; ++ break; ++ ++ case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: ++ if ((xfer_cnt == 0) || (scmd->underflow > xfer_cnt)) ++ scmd->result = DID_SOFT_ERROR << 16; ++ else ++ scmd->result = (DID_OK << 16) | scsi_status; ++ break; ++ ++ case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: ++ scmd->result = (DID_OK << 16) | scsi_status; ++ ++ if ((scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID)) ++ break; ++ ++ if (xfer_cnt < scmd->underflow) { ++ if (scsi_status == SAM_STAT_BUSY) ++ scmd->result = SAM_STAT_BUSY; ++ else ++ scmd->result = DID_SOFT_ERROR << 16; ++ } else if (scsi_state & (MPI2_SCSI_STATE_AUTOSENSE_FAILED | ++ MPI2_SCSI_STATE_NO_SCSI_STATUS)) ++ scmd->result = DID_SOFT_ERROR << 16; ++ else if (scsi_state & MPI2_SCSI_STATE_TERMINATED) ++ scmd->result = DID_RESET << 16; ++ else if (!xfer_cnt && scmd->cmnd[0] == REPORT_LUNS) { ++ mpi_reply->SCSIState = MPI2_SCSI_STATE_AUTOSENSE_VALID; ++ mpi_reply->SCSIStatus = SAM_STAT_CHECK_CONDITION; ++ scmd->result = (DRIVER_SENSE << 24) | ++ SAM_STAT_CHECK_CONDITION; ++ scmd->sense_buffer[0] = 0x70; ++ scmd->sense_buffer[2] = ILLEGAL_REQUEST; ++ scmd->sense_buffer[12] = 0x20; ++ scmd->sense_buffer[13] = 0; ++ } ++ break; ++ ++ case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ scmd->resid = 0; ++#else ++ scsi_set_resid(scmd, 0); ++#endif ++ case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: ++ case MPI2_IOCSTATUS_SUCCESS: ++ scmd->result = (DID_OK << 16) | scsi_status; ++ if (scsi_state & (MPI2_SCSI_STATE_AUTOSENSE_FAILED | ++ MPI2_SCSI_STATE_NO_SCSI_STATUS)) ++ scmd->result = DID_SOFT_ERROR << 16; ++ else if (scsi_state & MPI2_SCSI_STATE_TERMINATED) ++ scmd->result = DID_RESET << 16; ++ break; ++ ++#if defined(EEDP_SUPPORT) ++ case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: ++ case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: ++ case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: ++ _scsih_eedp_error_handling(scmd, ioc_status); ++ break; ++#endif /* EEDP Support */ ++ ++ case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: ++ case MPI2_IOCSTATUS_INVALID_FUNCTION: ++ case MPI2_IOCSTATUS_INVALID_SGL: ++ case MPI2_IOCSTATUS_INTERNAL_ERROR: ++ case MPI2_IOCSTATUS_INVALID_FIELD: ++ case MPI2_IOCSTATUS_INVALID_STATE: ++ case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: ++ case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED: ++ default: ++ scmd->result = DID_SOFT_ERROR << 16; ++ break; ++ ++ } ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ if (scmd->result && (ioc->logging_level & MPT_DEBUG_REPLY)) ++ _scsih_scsi_ioc_info(ioc , scmd, mpi_reply, smid); ++#endif ++ ++ out: ++ ++#if defined(CRACK_MONKEY_EEDP) && defined(EEDP_SUPPORT) ++ if (scmd->cmnd[0] == INQUIRY && scmd->host_scribble) { ++ char *some_data = scmd->host_scribble; ++ char inq_str[16]; ++ ++ memset(inq_str, 0, 16); ++ strncpy(inq_str, &some_data[16], 10); ++ if (!strcmp(inq_str, "Harpy Disk")) ++ some_data[5] |= 1; ++ scmd->host_scribble = NULL; ++ } ++#endif /* CRACK_MONKEY_EEDP */ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ if (scmd->use_sg) ++ pci_unmap_sg(ioc->pdev, (struct scatterlist *) ++ scmd->request_buffer, scmd->use_sg, ++ scmd->sc_data_direction); ++ else if (scmd->request_bufflen) ++ pci_unmap_single(ioc->pdev, scmd->SCp.dma_handle, ++ scmd->request_bufflen, scmd->sc_data_direction); ++#else ++ scsi_dma_unmap(scmd); ++#endif ++ ++ scmd->scsi_done(scmd); ++} ++ ++/** ++ * _scsih_sas_host_refresh - refreshing sas host object contents ++ * @ioc: per adapter object ++ * @update: update link information ++ * Context: user ++ * ++ * During port enable, fw will send topology events for every device. Its ++ * possible that the handles may change from the previous setting, so this ++ * code keeping handles updating if changed. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_host_refresh(struct MPT2SAS_ADAPTER *ioc, u8 update) ++{ ++ u16 sz; ++ u16 ioc_status; ++ int i; ++ Mpi2ConfigReply_t mpi_reply; ++ Mpi2SasIOUnitPage0_t *sas_iounit_pg0 = NULL; ++ ++ dtmprintk(ioc, printk(MPT2SAS_INFO_FMT ++ "updating handles for sas_host(0x%016llx)\n", ++ ioc->name, (unsigned long long)ioc->sas_hba.sas_address)); ++ ++ sz = offsetof(Mpi2SasIOUnitPage0_t, PhyData) + (ioc->sas_hba.num_phys ++ * sizeof(Mpi2SasIOUnit0PhyData_t)); ++ sas_iounit_pg0 = kzalloc(sz, GFP_KERNEL); ++ if (!sas_iounit_pg0) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ if (!(mpt2sas_config_get_sas_iounit_pg0(ioc, &mpi_reply, ++ sas_iounit_pg0, sz))) { ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status != MPI2_IOCSTATUS_SUCCESS) ++ goto out; ++ for (i = 0; i < ioc->sas_hba.num_phys ; i++) { ++ ioc->sas_hba.phy[i].handle = ++ le16_to_cpu(sas_iounit_pg0->PhyData[i]. ++ ControllerDevHandle); ++ if (update) ++ mpt2sas_transport_update_links( ++ ioc, ++ ioc->sas_hba.phy[i].handle, ++ le16_to_cpu(sas_iounit_pg0->PhyData[i]. ++ AttachedDevHandle), i, ++ sas_iounit_pg0->PhyData[i]. ++ NegotiatedLinkRate >> 4); ++ } ++ } ++ ++ out: ++ kfree(sas_iounit_pg0); ++} ++ ++/** ++ * _scsih_sas_host_add - create sas host object ++ * @ioc: per adapter object ++ * ++ * Creating host side data object, stored in ioc->sas_hba ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_host_add(struct MPT2SAS_ADAPTER *ioc) ++{ ++ int i; ++ Mpi2ConfigReply_t mpi_reply; ++ Mpi2SasIOUnitPage0_t *sas_iounit_pg0 = NULL; ++ Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL; ++ Mpi2SasPhyPage0_t phy_pg0; ++ Mpi2SasDevicePage0_t sas_device_pg0; ++ Mpi2SasEnclosurePage0_t enclosure_pg0; ++ u16 ioc_status; ++ u16 sz; ++ u16 device_missing_delay; ++ ++ mpt2sas_config_get_number_hba_phys(ioc, &ioc->sas_hba.num_phys); ++ if (!ioc->sas_hba.num_phys) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ /* sas_iounit page 0 */ ++ sz = offsetof(Mpi2SasIOUnitPage0_t, PhyData) + (ioc->sas_hba.num_phys * ++ sizeof(Mpi2SasIOUnit0PhyData_t)); ++ sas_iounit_pg0 = kzalloc(sz, GFP_KERNEL); ++ if (!sas_iounit_pg0) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ if ((mpt2sas_config_get_sas_iounit_pg0(ioc, &mpi_reply, ++ sas_iounit_pg0, sz))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out; ++ } ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out; ++ } ++ ++ /* sas_iounit page 1 */ ++ sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (ioc->sas_hba.num_phys * ++ sizeof(Mpi2SasIOUnit1PhyData_t)); ++ sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL); ++ if (!sas_iounit_pg1) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out; ++ } ++ if ((mpt2sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, ++ sas_iounit_pg1, sz))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out; ++ } ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out; ++ } ++ ++ ioc->io_missing_delay = ++ le16_to_cpu(sas_iounit_pg1->IODeviceMissingDelay); ++ device_missing_delay = ++ le16_to_cpu(sas_iounit_pg1->ReportDeviceMissingDelay); ++ if (device_missing_delay & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) ++ ioc->device_missing_delay = (device_missing_delay & ++ MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; ++ else ++ ioc->device_missing_delay = device_missing_delay & ++ MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; ++ ++ ioc->sas_hba.parent_dev = &ioc->shost->shost_gendev; ++ ioc->sas_hba.phy = kcalloc(ioc->sas_hba.num_phys, ++ sizeof(struct _sas_phy), GFP_KERNEL); ++ if (!ioc->sas_hba.phy) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out; ++ } ++ for (i = 0; i < ioc->sas_hba.num_phys ; i++) { ++ if ((mpt2sas_config_get_phy_pg0(ioc, &mpi_reply, &phy_pg0, ++ i))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out; ++ } ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out; ++ } ++ ioc->sas_hba.phy[i].handle = ++ le16_to_cpu(sas_iounit_pg0->PhyData[i].ControllerDevHandle); ++ ioc->sas_hba.phy[i].phy_id = i; ++ mpt2sas_transport_add_host_phy(ioc, &ioc->sas_hba.phy[i], ++ phy_pg0, ioc->sas_hba.parent_dev); ++ } ++ if ((mpt2sas_config_get_sas_device_pg0(ioc, &mpi_reply, &sas_device_pg0, ++ MPI2_SAS_DEVICE_PGAD_FORM_HANDLE, ioc->sas_hba.phy[0].handle))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out; ++ } ++ ioc->sas_hba.handle = le16_to_cpu(sas_device_pg0.DevHandle); ++ ioc->sas_hba.enclosure_handle = ++ le16_to_cpu(sas_device_pg0.EnclosureHandle); ++ ioc->sas_hba.sas_address = le64_to_cpu(sas_device_pg0.SASAddress); ++ printk(MPT2SAS_INFO_FMT "host_add: handle(0x%04x), " ++ "sas_addr(0x%016llx), phys(%d)\n", ioc->name, ioc->sas_hba.handle, ++ (unsigned long long) ioc->sas_hba.sas_address, ++ ioc->sas_hba.num_phys) ; ++ ++ if (ioc->sas_hba.enclosure_handle) { ++ if (!(mpt2sas_config_get_enclosure_pg0(ioc, &mpi_reply, ++ &enclosure_pg0, MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE, ++ ioc->sas_hba.enclosure_handle))) ++ ioc->sas_hba.enclosure_logical_id = ++ le64_to_cpu(enclosure_pg0.EnclosureLogicalID); ++ } ++ ++ out: ++ kfree(sas_iounit_pg1); ++ kfree(sas_iounit_pg0); ++} ++ ++/** ++ * _scsih_expander_add - creating expander object ++ * @ioc: per adapter object ++ * @handle: expander handle ++ * ++ * Creating expander object, stored in ioc->sas_expander_list. ++ * ++ * Return 0 for success, else error. ++ */ ++static int ++_scsih_expander_add(struct MPT2SAS_ADAPTER *ioc, u16 handle) ++{ ++ struct _sas_node *sas_expander; ++ Mpi2ConfigReply_t mpi_reply; ++ Mpi2ExpanderPage0_t expander_pg0; ++ Mpi2ExpanderPage1_t expander_pg1; ++ Mpi2SasEnclosurePage0_t enclosure_pg0; ++ u32 ioc_status; ++ u16 parent_handle; ++ __le64 sas_address; ++ int i; ++ unsigned long flags; ++ struct _sas_port *mpt2sas_port = NULL; ++ ++ int rc = 0; ++ ++ if (!handle) ++ return -1; ++ ++ if (ioc->shost_recovery) ++ return -1; ++ ++ if ((mpt2sas_config_get_expander_pg0(ioc, &mpi_reply, &expander_pg0, ++ MPI2_SAS_EXPAND_PGAD_FORM_HNDL, handle))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return -1; ++ } ++ ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return -1; ++ } ++ ++ /* handle out of order topology events */ ++ parent_handle = le16_to_cpu(expander_pg0.ParentDevHandle); ++ if (parent_handle >= ioc->sas_hba.num_phys) { ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ sas_expander = mpt2sas_scsih_expander_find_by_handle(ioc, ++ parent_handle); ++ spin_unlock_irqrestore(&ioc->sas_node_lock, flags); ++ if (!sas_expander) { ++ rc = _scsih_expander_add(ioc, parent_handle); ++ if (rc != 0) ++ return rc; ++ } ++ } ++ ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ sas_address = le64_to_cpu(expander_pg0.SASAddress); ++ sas_expander = mpt2sas_scsih_expander_find_by_sas_address(ioc, ++ sas_address); ++ spin_unlock_irqrestore(&ioc->sas_node_lock, flags); ++ ++ if (sas_expander) ++ return 0; ++ ++ sas_expander = kzalloc(sizeof(struct _sas_node), ++ GFP_KERNEL); ++ if (!sas_expander) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return -1; ++ } ++ ++ sas_expander->handle = handle; ++ sas_expander->num_phys = expander_pg0.NumPhys; ++ sas_expander->parent_handle = parent_handle; ++ sas_expander->enclosure_handle = ++ le16_to_cpu(expander_pg0.EnclosureHandle); ++ sas_expander->sas_address = sas_address; ++ ++ printk(MPT2SAS_INFO_FMT "expander_add: handle(0x%04x)," ++ " parent(0x%04x), sas_addr(0x%016llx), phys(%d)\n", ioc->name, ++ handle, sas_expander->parent_handle, (unsigned long long) ++ sas_expander->sas_address, sas_expander->num_phys); ++ ++ if (!sas_expander->num_phys) ++ goto out_fail; ++ sas_expander->phy = kcalloc(sas_expander->num_phys, ++ sizeof(struct _sas_phy), GFP_KERNEL); ++ if (!sas_expander->phy) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = -1; ++ goto out_fail; ++ } ++ ++ INIT_LIST_HEAD(&sas_expander->sas_port_list); ++ mpt2sas_port = mpt2sas_transport_port_add(ioc, handle, ++ sas_expander->parent_handle); ++ if (!mpt2sas_port) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = -1; ++ goto out_fail; ++ } ++ sas_expander->parent_dev = &mpt2sas_port->rphy->dev; ++ ++ for (i = 0 ; i < sas_expander->num_phys ; i++) { ++ if ((mpt2sas_config_get_expander_pg1(ioc, &mpi_reply, ++ &expander_pg1, i, handle))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = -1; ++ goto out_fail; ++ } ++ sas_expander->phy[i].handle = handle; ++ sas_expander->phy[i].phy_id = i; ++ ++ if ((mpt2sas_transport_add_expander_phy(ioc, ++ &sas_expander->phy[i], expander_pg1, ++ sas_expander->parent_dev))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = -1; ++ goto out_fail; ++ } ++ } ++ ++ if (sas_expander->enclosure_handle) { ++ if (!(mpt2sas_config_get_enclosure_pg0(ioc, &mpi_reply, ++ &enclosure_pg0, MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE, ++ sas_expander->enclosure_handle))) ++ sas_expander->enclosure_logical_id = ++ le64_to_cpu(enclosure_pg0.EnclosureLogicalID); ++ } ++ ++ _scsih_expander_node_add(ioc, sas_expander); ++ return 0; ++ ++ out_fail: ++ ++ if (mpt2sas_port) ++ mpt2sas_transport_port_remove(ioc, sas_expander->sas_address, ++ sas_expander->parent_handle); ++ kfree(sas_expander); ++ return rc; ++} ++ ++/** ++ * _scsih_expander_remove - removing expander object ++ * @ioc: per adapter object ++ * @handle: expander handle ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_expander_remove(struct MPT2SAS_ADAPTER *ioc, u16 handle) ++{ ++ struct _sas_node *sas_expander; ++ unsigned long flags; ++ ++ if (ioc->shost_recovery) ++ return; ++ ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ sas_expander = mpt2sas_scsih_expander_find_by_handle(ioc, handle); ++ spin_unlock_irqrestore(&ioc->sas_node_lock, flags); ++ _scsih_expander_node_remove(ioc, sas_expander); ++} ++ ++/** ++ * _scsih_done - internal SCSI_IO callback handler. ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @VF_ID: virtual function id ++ * @reply: reply message frame(lower 32bit addr) ++ * ++ * Callback handler when sending internal generated SCSI_IO. ++ * The callback index passed is `ioc->scsih_cb_idx` ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, u32 reply) ++{ ++ MPI2DefaultReply_t *mpi_reply; ++ ++ mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply); ++ if (ioc->scsih_cmds.status == MPT2_CMD_NOT_USED) ++ return; ++ if (ioc->scsih_cmds.smid != smid) ++ return; ++ ioc->scsih_cmds.status |= MPT2_CMD_COMPLETE; ++ if (mpi_reply) { ++ memcpy(ioc->scsih_cmds.reply, mpi_reply, ++ mpi_reply->MsgLength*4); ++ ioc->scsih_cmds.status |= MPT2_CMD_REPLY_VALID; ++ } ++ ioc->scsih_cmds.status &= ~MPT2_CMD_PENDING; ++ complete(&ioc->scsih_cmds.done); ++} ++ ++/** ++ * _scsi_send_scsi_io - send internal SCSI_IO to target ++ * @ioc: per adapter object ++ * @transfer_packet: packet describing the transfer ++ * Context: user ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_scsi_send_scsi_io(struct MPT2SAS_ADAPTER *ioc, struct _scsi_io_transfer ++ *transfer_packet) ++{ ++ Mpi2SCSIIOReply_t *mpi_reply; ++ Mpi2SCSIIORequest_t *mpi_request; ++ u16 smid; ++ u32 ioc_state; ++ unsigned long timeleft; ++ u8 issue_reset; ++ int rc; ++ void *priv_sense; ++ u32 mpi_control; ++ u32 sgl_flags; ++ u16 wait_state_count; ++ ++ if (ioc->shost_recovery) { ++ printk(MPT2SAS_INFO_FMT "%s: host reset in progress!\n", ++ __func__, ioc->name); ++ return -EFAULT; ++ } ++ ++ mutex_lock(&ioc->scsih_cmds.mutex); ++ ++ if (ioc->scsih_cmds.status != MPT2_CMD_NOT_USED) { ++ printk(MPT2SAS_ERR_FMT "%s: scsih_cmd in use\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ioc->scsih_cmds.status = MPT2_CMD_PENDING; ++ ++ wait_state_count = 0; ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { ++ if (wait_state_count++ == 10) { ++ printk(MPT2SAS_ERR_FMT ++ "%s: failed due to ioc not operational\n", ++ ioc->name, __func__); ++ rc = -EFAULT; ++ goto out; ++ } ++ ssleep(1); ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ printk(MPT2SAS_INFO_FMT "%s: waiting for " ++ "operational state(count=%d)\n", ioc->name, ++ __func__, wait_state_count); ++ } ++ if (wait_state_count) ++ printk(MPT2SAS_INFO_FMT "%s: ioc is operational\n", ++ ioc->name, __func__); ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->scsih_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ rc = 0; ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ioc->scsih_cmds.smid = smid; ++ memset(mpi_request, 0, sizeof(Mpi2SCSIIORequest_t)); ++ if (transfer_packet->is_raid) ++ mpi_request->Function = MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH; ++ else ++ mpi_request->Function = MPI2_FUNCTION_SCSI_IO_REQUEST; ++ mpi_request->DevHandle = cpu_to_le16(transfer_packet->handle); ++ ++ /* set scatter gather flags */ ++ sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | ++ MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | ++ MPI2_SGE_FLAGS_END_OF_LIST); ++ if (transfer_packet->dir == DMA_TO_DEVICE) ++ sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC; ++ sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; ++ ++ switch (transfer_packet->dir) { ++ case DMA_TO_DEVICE: ++ ioc->base_add_sg_single(&mpi_request->SGL, sgl_flags | ++ transfer_packet->data_length, transfer_packet->data_dma); ++ mpi_control = MPI2_SCSIIO_CONTROL_WRITE; ++ break; ++ case DMA_FROM_DEVICE: ++ ioc->base_add_sg_single(&mpi_request->SGL, sgl_flags | ++ transfer_packet->data_length, transfer_packet->data_dma); ++ mpi_control = MPI2_SCSIIO_CONTROL_READ; ++ break; ++ case DMA_BIDIRECTIONAL: ++ mpi_control = MPI2_SCSIIO_CONTROL_BIDIRECTIONAL; ++ /* TODO - is BIDI support needed ?? */ ++ BUG(); ++ break; ++ default: ++ case DMA_NONE: ++ mpi_control = MPI2_SCSIIO_CONTROL_NODATATRANSFER; ++ mpt2sas_base_build_zero_len_sge(ioc, &mpi_request->SGL); ++ break; ++ } ++ mpi_request->Control = cpu_to_le32(mpi_control | ++ MPI2_SCSIIO_CONTROL_SIMPLEQ); ++ mpi_request->DataLength = cpu_to_le32(transfer_packet->data_length); ++ mpi_request->MsgFlags = MPI2_SCSIIO_MSGFLAGS_SYSTEM_SENSE_ADDR; ++ mpi_request->SenseBufferLength = SCSI_SENSE_BUFFERSIZE; ++ mpi_request->SenseBufferLowAddress = ++ (u32)mpt2sas_base_get_sense_buffer_dma(ioc, smid); ++ priv_sense = mpt2sas_base_get_sense_buffer(ioc, smid); ++ mpi_request->SGLOffset0 = offsetof(Mpi2SCSIIORequest_t, SGL) / 4; ++ mpi_request->SGLFlags = cpu_to_le16(MPI2_SCSIIO_SGLFLAGS_TYPE_MPI + ++ MPI2_SCSIIO_SGLFLAGS_SYSTEM_ADDR); ++ mpi_request->IoFlags = cpu_to_le16(transfer_packet->cdb_length); ++ int_to_scsilun(transfer_packet->lun, (struct scsi_lun *) ++ mpi_request->LUN); ++ memcpy(mpi_request->CDB.CDB32, transfer_packet->cdb, ++ transfer_packet->cdb_length); ++ init_completion(&ioc->scsih_cmds.done); ++ mpt2sas_base_put_smid_scsi_io(ioc, smid, 0, transfer_packet->handle); ++ timeleft = wait_for_completion_timeout(&ioc->scsih_cmds.done, ++ transfer_packet->timeout*HZ); ++ if (!(ioc->scsih_cmds.status & MPT2_CMD_COMPLETE)) { ++ printk(MPT2SAS_ERR_FMT "%s: timeout\n", ++ ioc->name, __func__); ++ ++ _debug_dump_mf(mpi_request, sizeof(Mpi2SCSIIORequest_t)/4); ++ ++ if (!(ioc->scsih_cmds.status & MPT2_CMD_RESET)) ++ issue_reset = 1; ++ goto issue_target_reset; ++ } ++ if (ioc->scsih_cmds.status & MPT2_CMD_REPLY_VALID) { ++ transfer_packet->valid_reply = 1; ++ mpi_reply = ioc->scsih_cmds.reply; ++ transfer_packet->sense_length = ++ le32_to_cpu(mpi_reply->SenseCount); ++ if (transfer_packet->sense_length) ++ memcpy(transfer_packet->sense, priv_sense, ++ transfer_packet->sense_length); ++ transfer_packet->transfer_length = ++ le32_to_cpu(mpi_reply->TransferCount); ++ transfer_packet->ioc_status = ++ le16_to_cpu(mpi_reply->IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ transfer_packet->scsi_state = mpi_reply->SCSIState; ++ transfer_packet->scsi_status = mpi_reply->SCSIStatus; ++ transfer_packet->log_info = ++ le32_to_cpu(mpi_reply->IOCLogInfo); ++ } ++ goto out; ++ ++ issue_target_reset: ++ if (issue_reset) { ++ printk(MPT2SAS_INFO_FMT "issue target reset: handle" ++ "(0x%04x)\n", ioc->name, transfer_packet->handle); ++ mutex_lock(&ioc->tm_cmds.mutex); ++ mpt2sas_scsih_issue_tm(ioc, transfer_packet->handle, 0, ++ MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, 0, 10); ++ ioc->tm_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->tm_cmds.mutex); ++ /* TODO validate whether command was terminated ++ * so we know whether to call mpt2sas_base_free_smid() ++ */ ++ } ++/* TODO ~ don't allow retries for commands that timeout */ ++#if 0 ++ rc = -EAGAIN; ++#endif ++ rc = -EFAULT; ++ ++ out: ++ ioc->scsih_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->scsih_cmds.mutex); ++ return rc; ++} ++ ++/** ++ * _scsih_determine_disposition - ++ * @ioc: per adapter object ++ * @transfer_packet: packet describing the transfer ++ * Context: user ++ * ++ * Determines if an internal generated scsi_io is good data, or ++ * whether it needs to be retried or treated as an error. ++ * ++ * Returns device_responsive_state ++ */ ++static enum device_responsive_state ++_scsih_determine_disposition(struct MPT2SAS_ADAPTER *ioc, ++ struct _scsi_io_transfer *transfer_packet) ++{ ++ static enum device_responsive_state rc; ++ struct sense_info sense_info = {0, 0, 0}; ++ u8 check_sense = 0; ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ char *desc = NULL; ++#endif ++ ++ if (!transfer_packet->valid_reply) ++ return DEVICE_READY; ++ ++ switch (transfer_packet->ioc_status) { ++ case MPI2_IOCSTATUS_BUSY: ++ case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: ++ case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: ++ case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: ++ case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: ++ rc = DEVICE_RETRY; ++ break; ++ case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: ++ if (transfer_packet->cdb[0] == REPORT_LUNS) ++ rc = DEVICE_READY; ++ else ++ rc = DEVICE_RETRY; ++ case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: ++ case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: ++ case MPI2_IOCSTATUS_SUCCESS: ++ if (!transfer_packet->scsi_state || ++ !transfer_packet->scsi_status) { ++ rc = DEVICE_READY; ++ break; ++ } ++ if (transfer_packet->scsi_state & ++ MPI2_SCSI_STATE_AUTOSENSE_VALID) { ++ rc = DEVICE_ERROR; ++ check_sense = 1; ++ break; ++ } ++ if (transfer_packet->scsi_state & ++ (MPI2_SCSI_STATE_AUTOSENSE_FAILED | ++ MPI2_SCSI_STATE_NO_SCSI_STATUS | ++ MPI2_SCSI_STATE_TERMINATED)) { ++ rc = DEVICE_RETRY; ++ break; ++ } ++ if (transfer_packet->scsi_status >= ++ MPI2_SCSI_STATUS_BUSY) { ++ rc = DEVICE_RETRY; ++ break; ++ } ++ rc = DEVICE_READY; ++ break; ++ case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: ++ if (transfer_packet->scsi_state & ++ MPI2_SCSI_STATE_TERMINATED) ++ rc = DEVICE_RETRY; ++ else ++ rc = DEVICE_ERROR; ++ break; ++ default: ++ rc = DEVICE_ERROR; ++ break; ++ } ++ ++ if (check_sense) { ++ _scsih_normalize_sense(transfer_packet->sense, &sense_info); ++ if (sense_info.skey == UNIT_ATTENTION) ++ rc = DEVICE_RETRY_UA; ++ else if (sense_info.skey == NOT_READY) { ++ /* medium isn't present */ ++ if (sense_info.asc == 0x3a) ++ rc = DEVICE_READY; ++ /* send START_UNIT */ ++ if (sense_info.asc == 0x04 && sense_info.ascq == 0x11) ++ rc = DEVICE_START_UNIT; ++ /* LU becoming ready, or hasn't self-configured yet */ ++ else if ((sense_info.asc == 0x04 && ++ sense_info.ascq == 0x01) || sense_info.asc == 0x3e) ++ rc = DEVICE_RETRY; ++ } else if (sense_info.skey == ILLEGAL_REQUEST && ++ transfer_packet->cdb[0] == REPORT_LUNS) { ++ rc = DEVICE_READY; ++ } ++ } ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ if (ioc->logging_level & MPT_DEBUG_EVENT_WORK_TASK) { ++ switch (rc) { ++ case DEVICE_READY: ++ desc = "ready"; ++ break; ++ case DEVICE_RETRY: ++ desc = "retry"; ++ break; ++ case DEVICE_RETRY_UA: ++ desc = "retry_ua"; ++ break; ++ case DEVICE_START_UNIT: ++ desc = "start_unit"; ++ break; ++ case DEVICE_ERROR: ++ desc = "error"; ++ break; ++ } ++ ++ printk(MPT2SAS_INFO_FMT "\tioc_status(0x%04x), " ++ "loginfo(0x%08x), rc(%s)\n", ++ ioc->name, transfer_packet->ioc_status, ++ transfer_packet->log_info, desc); ++ ++ if (check_sense) ++ printk(MPT2SAS_INFO_FMT "\t[sense_key,asc,ascq]: " ++ "[0x%02x,0x%02x,0x%02x]\n", ioc->name, ++ sense_info.skey, sense_info.asc, sense_info.ascq); ++ } ++#endif ++ return rc; ++} ++ ++#if defined(EEDP_SUPPORT) ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) ++/** ++ * _scsih_read_capacity_16 - send READ_CAPACITY_16 to target ++ * @ioc: per adapter object ++ * @handle: expander handle ++ * @data: report luns data payload ++ * @data_length: length of data in bytes ++ * Context: user ++ * ++ * Returns device_responsive_state ++ */ ++static enum device_responsive_state ++_scsih_read_capacity_16(struct MPT2SAS_ADAPTER *ioc, u16 handle, u32 lun, ++ void *data, u32 data_length) ++{ ++ struct _scsi_io_transfer *transfer_packet; ++ enum device_responsive_state rc; ++ void *parameter_data; ++ int return_code; ++ ++ parameter_data = NULL; ++ transfer_packet = kzalloc(sizeof(struct _scsi_io_transfer), GFP_KERNEL); ++ if (!transfer_packet) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ parameter_data = pci_alloc_consistent(ioc->pdev, data_length, ++ &transfer_packet->data_dma); ++ if (!parameter_data) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ rc = DEVICE_READY; ++ memset(parameter_data, 0, data_length); ++ transfer_packet->handle = handle; ++ transfer_packet->lun = lun; ++ transfer_packet->dir = DMA_FROM_DEVICE; ++ transfer_packet->data_length = data_length; ++ transfer_packet->cdb_length = 16; ++ transfer_packet->cdb[0] = SERVICE_ACTION_IN; ++ transfer_packet->cdb[1] = 0x10; ++ transfer_packet->cdb[13] = data_length; ++ transfer_packet->timeout = 10; ++ ++ return_code = _scsi_send_scsi_io(ioc, transfer_packet); ++ if (return_code == -EFAULT) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_ERROR; ++ goto out; ++ } else if (return_code == -EAGAIN) { ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ rc = _scsih_determine_disposition(ioc, transfer_packet); ++ if (rc == DEVICE_READY) ++ memcpy(data, parameter_data, data_length); ++ ++ out: ++ if (parameter_data) ++ pci_free_consistent(ioc->pdev, data_length, parameter_data, ++ transfer_packet->data_dma); ++ kfree(transfer_packet); ++ return rc; ++} ++#endif ++#endif /* EEDP Support */ ++ ++#ifdef MPT2SAS_MULTIPATH ++/** ++ * _scsih_inquiry_vpd_sn - obtain device serial number ++ * @ioc: per adapter object ++ * @handle: device handle ++ * @data: report luns data payload ++ * @data_length: length of data in bytes ++ * Context: user ++ * ++ * Returns device_responsive_state ++ */ ++static enum device_responsive_state ++_scsih_inquiry_vpd_sn(struct MPT2SAS_ADAPTER *ioc, u16 handle, void *data, ++ u32 data_length) ++{ ++ struct _scsi_io_transfer *transfer_packet; ++ enum device_responsive_state rc; ++ void *inq_data; ++ int return_code; ++ ++ inq_data = NULL; ++ transfer_packet = kzalloc(sizeof(struct _scsi_io_transfer), GFP_KERNEL); ++ if (!transfer_packet) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ inq_data = pci_alloc_consistent(ioc->pdev, data_length, ++ &transfer_packet->data_dma); ++ if (!inq_data) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ rc = DEVICE_READY; ++ memset(inq_data, 0, data_length); ++ transfer_packet->handle = handle; ++ transfer_packet->dir = DMA_FROM_DEVICE; ++ transfer_packet->data_length = data_length; ++ transfer_packet->cdb_length = 6; ++ transfer_packet->cdb[0] = INQUIRY; ++ transfer_packet->cdb[1] = 1; ++ transfer_packet->cdb[2] = 0x80; ++ transfer_packet->cdb[4] = data_length; ++ transfer_packet->timeout = 5; ++ ++ return_code = _scsi_send_scsi_io(ioc, transfer_packet); ++ if (return_code == -EFAULT) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_ERROR; ++ goto out; ++ } else if (return_code == -EAGAIN) { ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ rc = _scsih_determine_disposition(ioc, transfer_packet); ++ if (rc == DEVICE_READY) ++ memcpy(data, inq_data, data_length); ++ ++ out: ++ if (inq_data) ++ pci_free_consistent(ioc->pdev, data_length, inq_data, ++ transfer_packet->data_dma); ++ kfree(transfer_packet); ++ return rc; ++} ++#endif ++ ++/** ++ * _scsih_inquiry_vpd_supported_pages - get supported pages ++ * @ioc: per adapter object ++ * @handle: device handle ++ * @data: report luns data payload ++ * @data_length: length of data in bytes ++ * Context: user ++ * ++ * Returns device_responsive_state ++ */ ++static enum device_responsive_state ++_scsih_inquiry_vpd_supported_pages(struct MPT2SAS_ADAPTER *ioc, u16 handle, u32 lun, ++ void *data, u32 data_length) ++{ ++ struct _scsi_io_transfer *transfer_packet; ++ enum device_responsive_state rc; ++ void *inq_data; ++ int return_code; ++ ++ inq_data = NULL; ++ transfer_packet = kzalloc(sizeof(struct _scsi_io_transfer), GFP_KERNEL); ++ if (!transfer_packet) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ inq_data = pci_alloc_consistent(ioc->pdev, data_length, ++ &transfer_packet->data_dma); ++ if (!inq_data) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ rc = DEVICE_READY; ++ memset(inq_data, 0, data_length); ++ transfer_packet->handle = handle; ++ transfer_packet->dir = DMA_FROM_DEVICE; ++ transfer_packet->data_length = data_length; ++ transfer_packet->cdb_length = 6; ++ transfer_packet->lun = lun; ++ transfer_packet->cdb[0] = INQUIRY; ++ transfer_packet->cdb[1] = 1; ++ transfer_packet->cdb[4] = data_length; ++ transfer_packet->timeout = 5; ++ ++ return_code = _scsi_send_scsi_io(ioc, transfer_packet); ++ if (return_code == -EFAULT) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_ERROR; ++ goto out; ++ } else if (return_code == -EAGAIN) { ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ rc = _scsih_determine_disposition(ioc, transfer_packet); ++ if (rc == DEVICE_READY) ++ memcpy(data, inq_data, data_length); ++ ++ out: ++ if (inq_data) ++ pci_free_consistent(ioc->pdev, data_length, inq_data, ++ transfer_packet->data_dma); ++ kfree(transfer_packet); ++ return rc; ++} ++ ++/** ++ * _scsih_report_luns - send REPORT_LUNS to target ++ * @ioc: per adapter object ++ * @handle: expander handle ++ * @data: report luns data payload ++ * @data_length: length of data in bytes ++ * @is_pd: is this hidden raid component ++ * Context: user ++ * ++ * Returns device_responsive_state ++ */ ++static enum device_responsive_state ++_scsih_report_luns(struct MPT2SAS_ADAPTER *ioc, u16 handle, void *data, ++ u32 data_length, u8 is_pd) ++{ ++ struct _scsi_io_transfer *transfer_packet; ++ enum device_responsive_state rc; ++ void *lun_data; ++ int return_code; ++ ++ lun_data = NULL; ++ transfer_packet = kzalloc(sizeof(struct _scsi_io_transfer), GFP_KERNEL); ++ if (!transfer_packet) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ lun_data = pci_alloc_consistent(ioc->pdev, data_length, ++ &transfer_packet->data_dma); ++ if (!lun_data) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ rc = DEVICE_READY; ++ memset(lun_data, 0, data_length); ++ transfer_packet->handle = handle; ++ transfer_packet->dir = DMA_FROM_DEVICE; ++ transfer_packet->data_length = data_length; ++ transfer_packet->cdb_length = 12; ++ transfer_packet->cdb[0] = REPORT_LUNS; ++ transfer_packet->cdb[6] = (data_length >> 24) & 0xFF; ++ transfer_packet->cdb[7] = (data_length >> 16) & 0xFF; ++ transfer_packet->cdb[8] = (data_length >> 8) & 0xFF; ++ transfer_packet->cdb[9] = data_length & 0xFF; ++ transfer_packet->timeout = 30; ++ transfer_packet->is_raid = is_pd; ++ ++ return_code = _scsi_send_scsi_io(ioc, transfer_packet); ++ if (return_code == -EFAULT) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_ERROR; ++ goto out; ++ } else if (return_code == -EAGAIN) { ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ rc = _scsih_determine_disposition(ioc, transfer_packet); ++ if (rc == DEVICE_READY) ++ memcpy(data, lun_data, data_length); ++ ++ out: ++ if (lun_data) ++ pci_free_consistent(ioc->pdev, data_length, lun_data, ++ transfer_packet->data_dma); ++ kfree(transfer_packet); ++ return rc; ++} ++ ++/** ++ * _scsih_start_unit - send START_UNIT to target ++ * @ioc: per adapter object ++ * @handle: expander handle ++ * @lun: lun number ++ * @is_pd: is this hidden raid component ++ * Context: user ++ * ++ * Returns device_responsive_state ++ */ ++static enum device_responsive_state ++_scsih_start_unit(struct MPT2SAS_ADAPTER *ioc, u16 handle, u32 lun, u8 is_pd) ++{ ++ struct _scsi_io_transfer *transfer_packet; ++ enum device_responsive_state rc; ++ ++ transfer_packet = kzalloc(sizeof(struct _scsi_io_transfer), GFP_KERNEL); ++ if (!transfer_packet) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ rc = DEVICE_READY; ++ transfer_packet->handle = handle; ++ transfer_packet->dir = DMA_NONE; ++ transfer_packet->lun = lun; ++ transfer_packet->cdb_length = 6; ++ transfer_packet->cdb[0] = START_STOP; ++ transfer_packet->cdb[4] = 1; ++ transfer_packet->timeout = 30; ++ transfer_packet->is_raid = is_pd; ++ ++ if ((_scsi_send_scsi_io(ioc, transfer_packet))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ rc = _scsih_determine_disposition(ioc, transfer_packet); ++ ++ out: ++ kfree(transfer_packet); ++ return rc; ++} ++ ++/** ++ * _scsih_test_unit_ready - send TUR to target ++ * @ioc: per adapter object ++ * @handle: expander handle ++ * @lun: lun number ++ * @is_pd: is this hidden raid component ++ * Context: user ++ * ++ * Returns device_responsive_state ++ */ ++static enum device_responsive_state ++_scsih_test_unit_ready(struct MPT2SAS_ADAPTER *ioc, u16 handle, u32 lun, ++ u8 is_pd) ++{ ++ struct _scsi_io_transfer *transfer_packet; ++ enum device_responsive_state rc; ++ ++ transfer_packet = kzalloc(sizeof(struct _scsi_io_transfer), GFP_KERNEL); ++ if (!transfer_packet) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ rc = DEVICE_READY; ++ transfer_packet->handle = handle; ++ transfer_packet->dir = DMA_NONE; ++ transfer_packet->lun = lun; ++ transfer_packet->cdb_length = 6; ++ transfer_packet->cdb[0] = TEST_UNIT_READY; ++ transfer_packet->timeout = 10; ++ transfer_packet->is_raid = is_pd; ++ ++ if ((_scsi_send_scsi_io(ioc, transfer_packet))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ rc = DEVICE_RETRY; ++ goto out; ++ } ++ ++ rc = _scsih_determine_disposition(ioc, transfer_packet); ++ ++ out: ++ kfree(transfer_packet); ++ return rc; ++} ++ ++#define MPT2_MAX_LUNS (255) ++ ++/** ++ * _scsih_wait_for_device_to_become_ready - handle busy devices ++ * @ioc: per adapter object ++ * @handle: expander handle ++ * @retry_count: number of times this event has been retried ++ * @is_pd: is this hidden raid component ++ * ++ * Some devices spend too much time in busy state, queue event later ++ * ++ * Return the device_responsive_state. ++ */ ++static enum device_responsive_state ++_scsih_wait_for_device_to_become_ready(struct MPT2SAS_ADAPTER *ioc, u16 handle, ++ u8 retry_count, u8 is_pd) ++{ ++ enum device_responsive_state rc; ++ struct scsi_lun *lun_data; ++ u32 length, num_luns; ++ u8 *data; ++ int lun; ++ ++ lun_data = kcalloc(MPT2_MAX_LUNS, sizeof(struct scsi_lun), GFP_KERNEL); ++ if (!lun_data) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return DEVICE_RETRY; ++ } ++ ++ retry_rlun: ++ ++ dewtprintk(ioc, printk(MPT2SAS_INFO_FMT "RLUN: handle(0x%04x), " ++ "retry_count(%d)\n", ioc->name, handle, retry_count)); ++ ++ rc = _scsih_report_luns(ioc, handle, lun_data, ++ MPT2_MAX_LUNS * sizeof(struct scsi_lun), is_pd); ++ ++ if (rc == DEVICE_RETRY_UA) ++ goto retry_rlun; ++ else if (rc != DEVICE_READY) ++ goto out; ++ ++ /* some debug bits*/ ++ data = (u8 *)lun_data; ++ length = ((data[0] << 24) | (data[1] << 16) | ++ (data[2] << 8) | (data[3] << 0)); ++ ++ num_luns = (length / sizeof(struct scsi_lun)); ++#if 0 /* debug */ ++ if (num_luns) { ++ struct scsi_lun *lunp; ++ for (lunp = &lun_data[1]; lunp <= &lun_data[num_luns]; ++ lunp++) ++ printk("%x\n", mpt_scsilun_to_int(lunp)); ++ } ++#endif ++ lun = (num_luns) ? mpt_scsilun_to_int(&lun_data[1]) : 0; ++ ++ retry_tur: ++ dewtprintk(ioc, printk(MPT2SAS_INFO_FMT "TUR: handle" ++ "(0x%04x), lun(%d), retry_count(%d)\n", ioc->name, ++ handle, lun, retry_count)); ++ rc = _scsih_test_unit_ready(ioc, handle, lun, is_pd); ++ if (rc == DEVICE_RETRY_UA) ++ goto retry_tur; ++ else if (rc != DEVICE_START_UNIT) ++ goto out; ++ ++ dewtprintk(ioc, printk(MPT2SAS_INFO_FMT "START: handle" ++ "(0x%04x), lun(%d), retry_count(%d)\n", ioc->name, ++ handle, lun, retry_count)); ++ _scsih_start_unit(ioc, handle, lun, is_pd); ++ goto retry_tur; ++ ++ out: ++ kfree(lun_data); ++ ++ if (rc == DEVICE_RETRY && retry_count >= command_retry_count) ++ rc = DEVICE_ERROR; ++ ++ return rc; ++} ++ ++/** ++ * _scsih_add_device - creating sas device object ++ * @ioc: per adapter object ++ * @handle: sas device handle ++ * @retry_count: number of times this event has been retried ++ * @phy_num: phy number end device attached to ++ * @is_pd: is this hidden raid component ++ * ++ * Creating end device object, stored in ioc->sas_device_list. ++ * ++ * Return 1 means queue the event later, 0 means complete the event ++ */ ++static int ++_scsih_add_device(struct MPT2SAS_ADAPTER *ioc, u16 handle, u8 retry_count, ++ u8 phy_num, u8 is_pd) ++{ ++ Mpi2ConfigReply_t mpi_reply; ++ Mpi2SasDevicePage0_t sas_device_pg0; ++ Mpi2SasEnclosurePage0_t enclosure_pg0; ++ struct _sas_device *sas_device; ++ u32 ioc_status; ++ __le64 sas_address; ++ u32 device_info; ++ unsigned long flags; ++ enum device_responsive_state rc; ++ ++ if ((mpt2sas_config_get_sas_device_pg0(ioc, &mpi_reply, &sas_device_pg0, ++ MPI2_SAS_DEVICE_PGAD_FORM_HANDLE, handle))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return 0; ++ } ++ ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return 0; ++ } ++ ++ sas_address = le64_to_cpu(sas_device_pg0.SASAddress); ++ ++ /* check if device is present */ ++ if (!(le16_to_cpu(sas_device_pg0.Flags) & ++ MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT)) { ++ printk(MPT2SAS_INFO_FMT "not present: handle(0x%04x)" ++ ", sas_addr(0x%016llx), retry_count(%d)\n", ioc->name, ++ handle, (unsigned long long)sas_address, retry_count); ++ if (retry_count && !is_pd) { ++ sas_device = kzalloc(sizeof(struct _sas_device), ++ GFP_KERNEL); ++ if (!sas_device) ++ return 0; ++ sas_device->handle = handle; ++ sas_device->sas_address = sas_address; ++ list_add_tail(&sas_device->list, &ioc->sas_device_list); ++ } ++ return 0; ++ } ++ ++ /* check if there were any issus with discovery */ ++ if (sas_device_pg0.AccessStatus == ++ MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ printk(MPT2SAS_ERR_FMT "AccessStatus = 0x%02x\n", ++ ioc->name, sas_device_pg0.AccessStatus); ++ return 0; ++ } ++ ++ /* check if this is end device */ ++ device_info = le32_to_cpu(sas_device_pg0.DeviceInfo); ++ if (!(_scsih_is_end_device(device_info))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return 0; ++ } ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = mpt2sas_scsih_sas_device_find_by_sas_address(ioc, ++ sas_address); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ ++ if (sas_device) { ++ _scsih_ublock_io_device(ioc, handle); ++ return 0; ++ } ++ ++ /* ++ * Wait for device that is becoming ready ++ * queue request later if device is busy. ++ */ ++ if (!ioc->wait_for_port_enable_to_complete) { ++ rc = _scsih_wait_for_device_to_become_ready(ioc, handle, ++ retry_count, is_pd); ++ if (rc == DEVICE_RETRY) ++ return 1; ++ else if (rc == DEVICE_ERROR) ++ return 0; ++ } ++ ++ sas_device = kzalloc(sizeof(struct _sas_device), ++ GFP_KERNEL); ++ if (!sas_device) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return 0; ++ } ++ ++ sas_device->handle = handle; ++ sas_device->parent_handle = ++ le16_to_cpu(sas_device_pg0.ParentDevHandle); ++ sas_device->enclosure_handle = ++ le16_to_cpu(sas_device_pg0.EnclosureHandle); ++ sas_device->slot = ++ le16_to_cpu(sas_device_pg0.Slot); ++ sas_device->device_info = device_info; ++ sas_device->sas_address = sas_address; ++ sas_device->hidden_raid_component = is_pd; ++ ++ ++ /* get enclosure_logical_id */ ++ if (sas_device->enclosure_handle && !(mpt2sas_config_get_enclosure_pg0( ++ ioc, &mpi_reply, &enclosure_pg0, MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE, ++ sas_device->enclosure_handle))) ++ sas_device->enclosure_logical_id = ++ le64_to_cpu(enclosure_pg0.EnclosureLogicalID); ++ ++ /* get device name */ ++ sas_device->device_name = le64_to_cpu(sas_device_pg0.DeviceName); ++ ++ if (ioc->wait_for_port_enable_to_complete) ++ _scsih_sas_device_init_add(ioc, sas_device); ++ else ++ _scsih_sas_device_add(ioc, sas_device); ++ ++ return 0; ++} ++ ++/** ++ * _scsih_remove_device - removing sas device object ++ * @ioc: per adapter object ++ * @handle: sas device handle ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_remove_device(struct MPT2SAS_ADAPTER *ioc, u16 handle) ++{ ++ struct MPT2SAS_TARGET *sas_target_priv_data; ++ struct _sas_device *sas_device; ++ unsigned long flags; ++ Mpi2SasIoUnitControlReply_t mpi_reply; ++ Mpi2SasIoUnitControlRequest_t mpi_request; ++ u16 device_handle; ++ ++ /* lookup sas_device */ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = _scsih_sas_device_find_by_handle(ioc, handle); ++ if (!sas_device) { ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ return; ++ } ++ ++ dewtprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: enter: handle" ++ "(0x%04x)\n", ioc->name, __func__, handle)); ++ ++ if (sas_device->starget && sas_device->starget->hostdata) { ++ sas_target_priv_data = sas_device->starget->hostdata; ++ sas_target_priv_data->deleted = 1; ++ } ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ ++ if (ioc->remove_host) ++ goto out; ++ ++ /* Target Reset to flush out all the outstanding IO */ ++ device_handle = (sas_device->hidden_raid_component) ? ++ sas_device->volume_handle : handle; ++ if (device_handle) { ++ dewtprintk(ioc, printk(MPT2SAS_INFO_FMT "issue target reset: " ++ "handle(0x%04x)\n", ioc->name, device_handle)); ++ mutex_lock(&ioc->tm_cmds.mutex); ++ mpt2sas_scsih_issue_tm(ioc, device_handle, 0, ++ MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, 0, 10); ++ ioc->tm_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->tm_cmds.mutex); ++ dewtprintk(ioc, printk(MPT2SAS_INFO_FMT "issue target reset " ++ "done: handle(0x%04x)\n", ioc->name, device_handle)); ++ if (ioc->shost_recovery) ++ goto out; ++ } ++ ++ /* SAS_IO_UNIT_CNTR - send REMOVE_DEVICE */ ++ dewtprintk(ioc, printk(MPT2SAS_INFO_FMT "sas_iounit: handle" ++ "(0x%04x)\n", ioc->name, handle)); ++ memset(&mpi_request, 0, sizeof(Mpi2SasIoUnitControlRequest_t)); ++ mpi_request.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL; ++ mpi_request.Operation = MPI2_SAS_OP_REMOVE_DEVICE; ++ mpi_request.DevHandle = handle; ++ mpi_request.VF_ID = 0; ++ if ((mpt2sas_base_sas_iounit_control(ioc, &mpi_reply, ++ &mpi_request)) != 0) ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ ++ dewtprintk(ioc, printk(MPT2SAS_INFO_FMT "sas_iounit: ioc_status" ++ "(0x%04x), loginfo(0x%08x)\n", ioc->name, ++ le16_to_cpu(mpi_reply.IOCStatus), ++ le32_to_cpu(mpi_reply.IOCLogInfo))); ++ ++ out: ++ mpt2sas_transport_port_remove(ioc, sas_device->sas_address, ++ sas_device->parent_handle); ++ ++#ifdef MPT2SAS_MULTIPATH ++ if (sas_device->sas_device_alt != NULL) { ++ sas_device->sas_device_alt->sas_device_alt = NULL; ++ sas_device->sas_device_alt->ioc = NULL; ++ } ++#endif ++ ++ printk(MPT2SAS_INFO_FMT "removing handle(0x%04x), sas_addr" ++ "(0x%016llx)\n", ioc->name, sas_device->handle, ++ (unsigned long long) sas_device->sas_address); ++ _scsih_sas_device_remove(ioc, sas_device); ++ ++ dewtprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: exit: handle" ++ "(0x%04x)\n", ioc->name, __func__, handle)); ++} ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++/** ++ * _scsih_sas_topology_change_event_debug - debug for topology event ++ * @ioc: per adapter object ++ * @event_data: event data payload ++ * Context: user. ++ */ ++static void ++_scsih_sas_topology_change_event_debug(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventDataSasTopologyChangeList_t *event_data) ++{ ++ int i; ++ u16 handle; ++ u16 reason_code; ++ u8 phy_number; ++ char *status_str = NULL; ++ char link_rate[25]; ++ ++ switch (event_data->ExpStatus) { ++ case MPI2_EVENT_SAS_TOPO_ES_ADDED: ++ status_str = "add"; ++ break; ++ case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING: ++ status_str = "remove"; ++ break; ++ case MPI2_EVENT_SAS_TOPO_ES_RESPONDING: ++ status_str = "responding"; ++ break; ++ case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING: ++ status_str = "remove delay"; ++ break; ++ default: ++ status_str = "unknown status"; ++ break; ++ } ++ printk(MPT2SAS_DEBUG_FMT "sas topology change: (%s)\n", ++ ioc->name, status_str); ++ printk(KERN_DEBUG "\thandle(0x%04x), enclosure_handle(0x%04x) " ++ "start_phy(%02d), count(%d)\n", ++ le16_to_cpu(event_data->ExpanderDevHandle), ++ le16_to_cpu(event_data->EnclosureHandle), ++ event_data->StartPhyNum, event_data->NumEntries); ++ for (i = 0; i < event_data->NumEntries; i++) { ++ handle = le16_to_cpu(event_data->PHY[i].AttachedDevHandle); ++ if (!handle) ++ continue; ++ phy_number = event_data->StartPhyNum + i; ++ reason_code = event_data->PHY[i].PhyStatus & ++ MPI2_EVENT_SAS_TOPO_RC_MASK; ++ switch (reason_code) { ++ case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED: ++ snprintf(link_rate, 25, ": add, link(0x%02x)", ++ (event_data->PHY[i].LinkRate >> 4)); ++ status_str = link_rate; ++ break; ++ case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING: ++ status_str = ": remove"; ++ break; ++ case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING: ++ status_str = ": remove_delay"; ++ break; ++ case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED: ++ snprintf(link_rate, 25, ": link(0x%02x)", ++ (event_data->PHY[i].LinkRate >> 4)); ++ status_str = link_rate; ++ break; ++ case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE: ++ status_str = ": responding"; ++ break; ++ default: ++ status_str = ": unknown"; ++ break; ++ } ++ printk(KERN_DEBUG "\tphy(%02d), attached_handle(0x%04x)%s\n", ++ phy_number, handle, status_str); ++ } ++} ++#endif ++ ++/** ++ * _scsih_sas_topology_change_event - handle topology changes ++ * @ioc: per adapter object ++ * @VF_ID: ++ * @event_data: event data payload ++ * fw_event: ++ * Context: user. ++ * ++ */ ++static int ++_scsih_sas_topology_change_event(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ Mpi2EventDataSasTopologyChangeList_t *event_data, ++ struct fw_event_work *fw_event) ++{ ++ int i; ++ u16 parent_handle, handle; ++ u16 reason_code; ++ u8 phy_number; ++ struct _sas_node *sas_expander; ++ unsigned long flags; ++ u8 link_rate_; ++ int rc; ++ int requeue_event; ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ if (ioc->logging_level & MPT_DEBUG_EVENT_WORK_TASK) ++ _scsih_sas_topology_change_event_debug(ioc, event_data); ++#endif ++ ++ if (!ioc->sas_hba.num_phys) ++ _scsih_sas_host_add(ioc); ++ else ++ _scsih_sas_host_refresh(ioc, 0); ++ ++ if (fw_event->ignore) { ++ dewtprintk(ioc, printk(MPT2SAS_DEBUG_FMT "ignoring expander " ++ "event\n", ioc->name)); ++ return 0; ++ } ++ ++ parent_handle = le16_to_cpu(event_data->ExpanderDevHandle); ++ ++ /* handle expander add */ ++ if (event_data->ExpStatus == MPI2_EVENT_SAS_TOPO_ES_ADDED) ++ if (_scsih_expander_add(ioc, parent_handle) != 0) ++ return 0; ++ ++ /* handle siblings events */ ++ for (i = 0, requeue_event = 0; i < event_data->NumEntries; i++) { ++ if (fw_event->ignore) { ++ dewtprintk(ioc, printk(MPT2SAS_DEBUG_FMT "ignoring " ++ "expander event\n", ioc->name)); ++ return 0; ++ } ++ if (ioc->shost_recovery) ++ return 0; ++ if (event_data->PHY[i].PhyStatus & ++ MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) ++ continue; ++ handle = le16_to_cpu(event_data->PHY[i].AttachedDevHandle); ++ if (!handle) ++ continue; ++ phy_number = event_data->StartPhyNum + i; ++ reason_code = event_data->PHY[i].PhyStatus & ++ MPI2_EVENT_SAS_TOPO_RC_MASK; ++ link_rate_ = event_data->PHY[i].LinkRate >> 4; ++ switch (reason_code) { ++ case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED: ++ case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED: ++ if (!parent_handle) { ++ if (phy_number < ioc->sas_hba.num_phys) ++ mpt2sas_transport_update_links( ++ ioc, ++ ioc->sas_hba.phy[phy_number].handle, ++ handle, phy_number, link_rate_); ++ } else { ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ sas_expander = ++ mpt2sas_scsih_expander_find_by_handle(ioc, ++ parent_handle); ++ spin_unlock_irqrestore(&ioc->sas_node_lock, ++ flags); ++ if (sas_expander) { ++ if (phy_number < sas_expander->num_phys) ++ mpt2sas_transport_update_links( ++ ioc, ++ sas_expander-> ++ phy[phy_number].handle, ++ handle, phy_number, ++ link_rate_); ++ } ++ } ++ if (reason_code == MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED) { ++ if (link_rate_ < MPI2_SAS_NEG_LINK_RATE_1_5) ++ break; ++ rc = _scsih_add_device(ioc, handle, ++ fw_event->retries[i], phy_number, 0); ++ if (rc) {/* retry due to busy device */ ++ fw_event->retries[i]++; ++ requeue_event = 1; ++ } else {/* mark entry vacant */ ++ event_data->PHY[i].PhyStatus |= ++ MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT; ++ } ++ } ++ break; ++ case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING: ++ _scsih_remove_device(ioc, handle); ++ break; ++ } ++ } ++ ++ /* handle expander removal */ ++ if (event_data->ExpStatus == MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING) ++ _scsih_expander_remove(ioc, parent_handle); ++ ++ return requeue_event; ++} ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++/** ++ * _scsih_sas_device_status_change_event_debug - debug for device event ++ * @event_data: event data payload ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_device_status_change_event_debug(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventDataSasDeviceStatusChange_t *event_data) ++{ ++ char *reason_str = NULL; ++ ++ switch (event_data->ReasonCode) { ++ case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA: ++ reason_str = "smart data"; ++ break; ++ case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED: ++ reason_str = "unsupported device discovered"; ++ break; ++ case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: ++ reason_str = "internal device reset"; ++ break; ++ case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL: ++ reason_str = "internal task abort"; ++ break; ++ case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL: ++ reason_str = "internal task abort set"; ++ break; ++ case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL: ++ reason_str = "internal clear task set"; ++ break; ++ case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL: ++ reason_str = "internal query task"; ++ break; ++ case MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE: ++ reason_str = "sata init failure"; ++ break; ++ case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET: ++ reason_str = "internal device reset complete"; ++ break; ++ case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL: ++ reason_str = "internal task abort complete"; ++ break; ++ case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION: ++ reason_str = "internal async notification"; ++ break; ++ default: ++ reason_str = "unknown reason"; ++ break; ++ } ++ printk(MPT2SAS_DEBUG_FMT "device status change: (%s)\n" ++ "\thandle(0x%04x), sas address(0x%016llx)", ioc->name, ++ reason_str, le16_to_cpu(event_data->DevHandle), ++ (unsigned long long)le64_to_cpu(event_data->SASAddress)); ++ if (event_data->ReasonCode == MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA) ++ printk(MPT2SAS_DEBUG_FMT ", ASC(0x%x), ASCQ(0x%x)\n", ioc->name, ++ event_data->ASC, event_data->ASCQ); ++ printk(KERN_INFO "\n"); ++} ++#endif ++ ++/** ++ * _scsih_sas_device_status_change_event - handle device status change ++ * @ioc: per adapter object ++ * @VF_ID: ++ * @event_data: event data payload ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_device_status_change_event(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ Mpi2EventDataSasDeviceStatusChange_t *event_data) ++{ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ if (ioc->logging_level & MPT_DEBUG_EVENT_WORK_TASK) ++ _scsih_sas_device_status_change_event_debug(ioc, event_data); ++#endif ++} ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++/** ++ * _scsih_sas_enclosure_dev_status_change_event_debug - debug for enclosure event ++ * @ioc: per adapter object ++ * @event_data: event data payload ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_enclosure_dev_status_change_event_debug(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventDataSasEnclDevStatusChange_t *event_data) ++{ ++ char *reason_str = NULL; ++ ++ switch (event_data->ReasonCode) { ++ case MPI2_EVENT_SAS_ENCL_RC_ADDED: ++ reason_str = "enclosure add"; ++ break; ++ case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING: ++ reason_str = "enclosure remove"; ++ break; ++ default: ++ reason_str = "unknown reason"; ++ break; ++ } ++ ++ printk(MPT2SAS_DEBUG_FMT "enclosure status change: (%s)\n" ++ "\thandle(0x%04x), enclosure logical id(0x%016llx)" ++ " number slots(%d)\n", ioc->name, reason_str, ++ le16_to_cpu(event_data->EnclosureHandle), ++ (unsigned long long)le64_to_cpu(event_data->EnclosureLogicalID), ++ le16_to_cpu(event_data->StartSlot)); ++} ++#endif ++ ++/** ++ * _scsih_sas_enclosure_dev_status_change_event - handle enclosure events ++ * @ioc: per adapter object ++ * @VF_ID: ++ * @event_data: event data payload ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_enclosure_dev_status_change_event(struct MPT2SAS_ADAPTER *ioc, ++ u8 VF_ID, Mpi2EventDataSasEnclDevStatusChange_t *event_data) ++{ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ if (ioc->logging_level & MPT_DEBUG_EVENT_WORK_TASK) ++ _scsih_sas_enclosure_dev_status_change_event_debug(ioc, ++ event_data); ++#endif ++} ++ ++/** ++ * _scsih_sas_broadcast_primative_event - handle broadcast events ++ * @ioc: per adapter object ++ * @event_data: event data payload ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_broadcast_primative_event(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ Mpi2EventDataSasBroadcastPrimitive_t *event_data) ++{ ++ struct scsi_cmnd *scmd; ++ u16 smid, handle; ++ u32 lun; ++ struct MPT2SAS_DEVICE *sas_device_priv_data; ++ u32 termination_count; ++ u32 query_count; ++ Mpi2SCSITaskManagementReply_t *mpi_reply; ++ ++ dewtprintk(ioc, printk(MPT2SAS_DEBUG_FMT "broadcast primative: " ++ "phy number(%d), width(%d)\n", ioc->name, event_data->PhyNum, ++ event_data->PortWidth)); ++ ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: enter\n", ioc->name, ++ __func__)); ++ ++ mutex_lock(&ioc->tm_cmds.mutex); ++ termination_count = 0; ++ query_count = 0; ++ mpi_reply = ioc->tm_cmds.reply; ++ for (smid = 1; smid <= ioc->request_depth; smid++) { ++ scmd = _scsih_scsi_lookup_get(ioc, smid); ++ if (!scmd) ++ continue; ++ sas_device_priv_data = scmd->device->hostdata; ++ if (!sas_device_priv_data || !sas_device_priv_data->sas_target) ++ continue; ++ /* skip hidden raid components */ ++ if (sas_device_priv_data->sas_target->flags & ++ MPT_TARGET_FLAGS_RAID_COMPONENT) ++ continue; ++ /* skip volumes */ ++ if (sas_device_priv_data->sas_target->flags & ++ MPT_TARGET_FLAGS_VOLUME) ++ continue; ++ ++ handle = sas_device_priv_data->sas_target->handle; ++ lun = sas_device_priv_data->lun; ++ query_count++; ++ ++ mpt2sas_scsih_issue_tm(ioc, handle, lun, ++ MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK, smid, 30); ++ ioc->tm_cmds.status = MPT2_CMD_NOT_USED; ++ ++ if ((mpi_reply->IOCStatus == MPI2_IOCSTATUS_SUCCESS) && ++ (mpi_reply->ResponseCode == ++ MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED || ++ mpi_reply->ResponseCode == ++ MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC)) ++ continue; ++ ++ mpt2sas_scsih_issue_tm(ioc, handle, lun, ++ MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, 0, 30); ++ ioc->tm_cmds.status = MPT2_CMD_NOT_USED; ++ termination_count += le32_to_cpu(mpi_reply->TerminationCount); ++ } ++ ioc->broadcast_aen_busy = 0; ++ mutex_unlock(&ioc->tm_cmds.mutex); ++ ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT ++ "%s - exit, query_count = %d termination_count = %d\n", ++ ioc->name, __func__, query_count, termination_count)); ++} ++ ++/** ++ * _scsih_sas_discovery_event - handle discovery events ++ * @ioc: per adapter object ++ * @event_data: event data payload ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_discovery_event(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ Mpi2EventDataSasDiscovery_t *event_data) ++{ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ if (ioc->logging_level & MPT_DEBUG_EVENT_WORK_TASK) { ++ printk(MPT2SAS_DEBUG_FMT "discovery event: (%s)", ioc->name, ++ (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ? ++ "start" : "stop"); ++ if (event_data->DiscoveryStatus) ++ printk(MPT2SAS_DEBUG_FMT ", discovery_status(0x%08x)", ++ ioc->name, le32_to_cpu(event_data->DiscoveryStatus)); ++ printk("\n"); ++ } ++#endif ++ ++ if (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED && ++ !ioc->sas_hba.num_phys) ++ _scsih_sas_host_add(ioc); ++} ++ ++/** ++ * _scsih_reprobe_lun - reprobing lun ++ * @sdev: scsi device struct ++ * @no_uld_attach: sdev->no_uld_attach flag setting ++ * ++ **/ ++static void ++_scsih_reprobe_lun(struct scsi_device *sdev, void *no_uld_attach) ++{ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++ int rc; ++#endif ++ sdev->no_uld_attach = no_uld_attach ? 1 : 0; ++ sdev_printk(KERN_INFO, sdev, "%s raid component\n", ++ sdev->no_uld_attach ? "hidding" : "exposing"); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++ rc = scsi_device_reprobe(sdev); ++#else ++ scsi_device_reprobe(sdev); ++#endif ++} ++ ++/** ++ * _scsih_reprobe_target - reprobing target ++ * @starget: scsi target struct ++ * @no_uld_attach: sdev->no_uld_attach flag setting ++ * ++ * Note: no_uld_attach flag determines whether the disk device is attached ++ * to block layer. A value of `1` means to not attach. ++ **/ ++static void ++_scsih_reprobe_target(struct scsi_target *starget, int no_uld_attach) ++{ ++ struct MPT2SAS_TARGET *sas_target_priv_data = starget->hostdata; ++ ++ if (no_uld_attach) ++ sas_target_priv_data->flags |= MPT_TARGET_FLAGS_RAID_COMPONENT; ++ else ++ sas_target_priv_data->flags &= ~MPT_TARGET_FLAGS_RAID_COMPONENT; ++ ++ starget_for_each_device(starget, no_uld_attach ? (void *)1 : NULL, ++ _scsih_reprobe_lun); ++} ++ ++/** ++ * _scsih_sas_volume_add - add new volume ++ * @ioc: per adapter object ++ * @element: IR config element data ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_volume_add(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventIrConfigElement_t *element) ++{ ++ struct _raid_device *raid_device; ++ unsigned long flags; ++ u64 wwid; ++ u16 handle = le16_to_cpu(element->VolDevHandle); ++ int rc; ++ ++ mpt2sas_config_get_volume_wwid(ioc, handle, &wwid); ++ if (!wwid) { ++ printk(MPT2SAS_ERR_FMT ++ "failure at %s:%d/%s()!\n", ioc->name, ++ __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ spin_lock_irqsave(&ioc->raid_device_lock, flags); ++ raid_device = _scsih_raid_device_find_by_wwid(ioc, wwid); ++ spin_unlock_irqrestore(&ioc->raid_device_lock, flags); ++ ++ if (raid_device) ++ return; ++ ++ raid_device = kzalloc(sizeof(struct _raid_device), GFP_KERNEL); ++ if (!raid_device) { ++ printk(MPT2SAS_ERR_FMT ++ "failure at %s:%d/%s()!\n", ioc->name, ++ __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ raid_device->id = ioc->sas_id++; ++ raid_device->channel = RAID_CHANNEL; ++ raid_device->handle = handle; ++ raid_device->wwid = wwid; ++ _scsih_raid_device_add(ioc, raid_device); ++ if (!ioc->wait_for_port_enable_to_complete) { ++ rc = scsi_add_device(ioc->shost, RAID_CHANNEL, ++ raid_device->id, 0); ++ if (rc) ++ _scsih_raid_device_remove(ioc, raid_device); ++ } else ++ _scsih_determine_boot_device(ioc, raid_device, 1); ++} ++ ++/** ++ * _scsih_sas_volume_delete - delete volume ++ * @ioc: per adapter object ++ * @element: IR config element data ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_volume_delete(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventIrConfigElement_t *element) ++{ ++ struct _raid_device *raid_device; ++ u16 handle = le16_to_cpu(element->VolDevHandle); ++ unsigned long flags; ++ struct MPT2SAS_TARGET *sas_target_priv_data; ++ ++ spin_lock_irqsave(&ioc->raid_device_lock, flags); ++ raid_device = _scsih_raid_device_find_by_handle(ioc, handle); ++ spin_unlock_irqrestore(&ioc->raid_device_lock, flags); ++ if (!raid_device) ++ return; ++ if (raid_device->starget) { ++ sas_target_priv_data = raid_device->starget->hostdata; ++ sas_target_priv_data->deleted = 1; ++ scsi_remove_target(&raid_device->starget->dev); ++ } ++ _scsih_raid_device_remove(ioc, raid_device); ++} ++ ++/** ++ * _scsih_sas_pd_expose - expose pd component to /dev/sdX ++ * @ioc: per adapter object ++ * @element: IR config element data ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_pd_expose(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventIrConfigElement_t *element) ++{ ++ struct _sas_device *sas_device; ++ unsigned long flags; ++ u16 handle = le16_to_cpu(element->PhysDiskDevHandle); ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = _scsih_sas_device_find_by_handle(ioc, handle); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ if (!sas_device) ++ return; ++ ++ /* exposing raid component */ ++ sas_device->volume_handle = 0; ++ sas_device->volume_wwid = 0; ++ sas_device->hidden_raid_component = 0; ++ _scsih_reprobe_target(sas_device->starget, 0); ++} ++ ++/** ++ * _scsih_sas_pd_hide - hide pd component from /dev/sdX ++ * @ioc: per adapter object ++ * @element: IR config element data ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_pd_hide(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventIrConfigElement_t *element) ++{ ++ struct _sas_device *sas_device; ++ unsigned long flags; ++ u16 handle = le16_to_cpu(element->PhysDiskDevHandle); ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = _scsih_sas_device_find_by_handle(ioc, handle); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ if (!sas_device) ++ return; ++ ++ /* hiding raid component */ ++ mpt2sas_config_get_volume_handle(ioc, handle, ++ &sas_device->volume_handle); ++ mpt2sas_config_get_volume_wwid(ioc, sas_device->volume_handle, ++ &sas_device->volume_wwid); ++ sas_device->hidden_raid_component = 1; ++ _scsih_reprobe_target(sas_device->starget, 1); ++} ++ ++/** ++ * _scsih_sas_pd_delete - delete pd component ++ * @ioc: per adapter object ++ * @element: IR config element data ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_pd_delete(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventIrConfigElement_t *element) ++{ ++ struct _sas_device *sas_device; ++ unsigned long flags; ++ u16 handle = le16_to_cpu(element->PhysDiskDevHandle); ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = _scsih_sas_device_find_by_handle(ioc, handle); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ if (!sas_device) ++ return; ++ _scsih_remove_device(ioc, handle); ++} ++ ++/** ++ * _scsih_sas_pd_add - remove pd component ++ * @ioc: per adapter object ++ * @element: IR config element data ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_pd_add(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventIrConfigElement_t *element) ++{ ++ struct _sas_device *sas_device; ++ unsigned long flags; ++ u16 handle = le16_to_cpu(element->PhysDiskDevHandle); ++ Mpi2ConfigReply_t mpi_reply; ++ Mpi2SasDevicePage0_t sas_device_pg0; ++ u32 ioc_status; ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = _scsih_sas_device_find_by_handle(ioc, handle); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ if (sas_device) { ++ sas_device->hidden_raid_component = 1; ++ return; ++ } ++ ++ if ((mpt2sas_config_get_sas_device_pg0(ioc, &mpi_reply, &sas_device_pg0, ++ MPI2_SAS_DEVICE_PGAD_FORM_HANDLE, handle))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ mpt2sas_transport_update_links(ioc, ++ le16_to_cpu(sas_device_pg0.ParentDevHandle), ++ handle, sas_device_pg0.PhyNum, MPI2_SAS_NEG_LINK_RATE_1_5); ++ ++ _scsih_add_device(ioc, handle, 0, 0, 1); ++} ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++/** ++ * _scsih_sas_ir_config_change_event_debug - debug for IR Config Change events ++ * @ioc: per adapter object ++ * @event_data: event data payload ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_ir_config_change_event_debug(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventDataIrConfigChangeList_t *event_data) ++{ ++ Mpi2EventIrConfigElement_t *element; ++ u8 element_type; ++ int i; ++ char *reason_str = NULL, *element_str = NULL; ++ ++ element = (Mpi2EventIrConfigElement_t *)&event_data->ConfigElement[0]; ++ ++ printk(MPT2SAS_DEBUG_FMT "raid config change: (%s), elements(%d)\n", ++ ioc->name, (le32_to_cpu(event_data->Flags) & ++ MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG) ? ++ "foreign" : "native", event_data->NumElements); ++ for (i = 0; i < event_data->NumElements; i++, element++) { ++ switch (element->ReasonCode) { ++ case MPI2_EVENT_IR_CHANGE_RC_ADDED: ++ reason_str = "add"; ++ break; ++ case MPI2_EVENT_IR_CHANGE_RC_REMOVED: ++ reason_str = "remove"; ++ break; ++ case MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE: ++ reason_str = "no change"; ++ break; ++ case MPI2_EVENT_IR_CHANGE_RC_HIDE: ++ reason_str = "hide"; ++ break; ++ case MPI2_EVENT_IR_CHANGE_RC_UNHIDE: ++ reason_str = "unhide"; ++ break; ++ case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED: ++ reason_str = "volume_created"; ++ break; ++ case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED: ++ reason_str = "volume_deleted"; ++ break; ++ case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED: ++ reason_str = "pd_created"; ++ break; ++ case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED: ++ reason_str = "pd_deleted"; ++ break; ++ default: ++ reason_str = "unknown reason"; ++ break; ++ } ++ element_type = le16_to_cpu(element->ElementFlags) & ++ MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK; ++ switch (element_type) { ++ case MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT: ++ element_str = "volume"; ++ break; ++ case MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT: ++ element_str = "phys disk"; ++ break; ++ case MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT: ++ element_str = "hot spare"; ++ break; ++ default: ++ element_str = "unknown element"; ++ break; ++ } ++ printk(KERN_DEBUG "\t(%s:%s), vol handle(0x%04x), " ++ "pd handle(0x%04x), pd num(0x%02x)\n", element_str, ++ reason_str, le16_to_cpu(element->VolDevHandle), ++ le16_to_cpu(element->PhysDiskDevHandle), ++ element->PhysDiskNum); ++ } ++} ++#endif ++ ++/** ++ * _scsih_sas_ir_config_change_event - handle ir configuration change events ++ * @ioc: per adapter object ++ * @VF_ID: ++ * @event_data: event data payload ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_ir_config_change_event(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ Mpi2EventDataIrConfigChangeList_t *event_data) ++{ ++ Mpi2EventIrConfigElement_t *element; ++ int i; ++ u8 foreign_config; ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ if (ioc->logging_level & MPT_DEBUG_EVENT_WORK_TASK) ++ _scsih_sas_ir_config_change_event_debug(ioc, event_data); ++ ++#endif ++ ++ foreign_config = (le32_to_cpu(event_data->Flags) & ++ MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG) ? 1 : 0; ++ ++ element = (Mpi2EventIrConfigElement_t *)&event_data->ConfigElement[0]; ++ for (i = 0; i < event_data->NumElements; i++, element++) { ++ ++ switch (element->ReasonCode) { ++ case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED: ++ case MPI2_EVENT_IR_CHANGE_RC_ADDED: ++ if (!foreign_config) ++ _scsih_sas_volume_add(ioc, element); ++ break; ++ case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED: ++ case MPI2_EVENT_IR_CHANGE_RC_REMOVED: ++ if (!foreign_config) ++ _scsih_sas_volume_delete(ioc, element); ++ break; ++ case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED: ++ _scsih_sas_pd_hide(ioc, element); ++ break; ++ case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED: ++ _scsih_sas_pd_expose(ioc, element); ++ break; ++ case MPI2_EVENT_IR_CHANGE_RC_HIDE: ++ _scsih_sas_pd_add(ioc, element); ++ break; ++ case MPI2_EVENT_IR_CHANGE_RC_UNHIDE: ++ _scsih_sas_pd_delete(ioc, element); ++ break; ++ } ++ } ++} ++ ++/** ++ * _scsih_sas_ir_volume_event - IR volume event ++ * @ioc: per adapter object ++ * @event_data: event data payload ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_ir_volume_event(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ Mpi2EventDataIrVolume_t *event_data) ++{ ++ u64 wwid; ++ unsigned long flags; ++ struct _raid_device *raid_device; ++ u16 handle; ++ u32 state; ++ int rc; ++ struct MPT2SAS_TARGET *sas_target_priv_data; ++ ++ if (event_data->ReasonCode != MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED) ++ return; ++ ++ handle = le16_to_cpu(event_data->VolDevHandle); ++ state = le32_to_cpu(event_data->NewValue); ++ dewtprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: handle(0x%04x), " ++ "old(0x%08x), new(0x%08x)\n", ioc->name, __func__, handle, ++ le32_to_cpu(event_data->PreviousValue), state)); ++ ++ spin_lock_irqsave(&ioc->raid_device_lock, flags); ++ raid_device = _scsih_raid_device_find_by_handle(ioc, handle); ++ spin_unlock_irqrestore(&ioc->raid_device_lock, flags); ++ ++ switch (state) { ++ case MPI2_RAID_VOL_STATE_MISSING: ++ case MPI2_RAID_VOL_STATE_FAILED: ++ if (!raid_device) ++ break; ++ if (raid_device->starget) { ++ sas_target_priv_data = raid_device->starget->hostdata; ++ sas_target_priv_data->deleted = 1; ++ scsi_remove_target(&raid_device->starget->dev); ++ } ++ _scsih_raid_device_remove(ioc, raid_device); ++ break; ++ ++ case MPI2_RAID_VOL_STATE_ONLINE: ++ case MPI2_RAID_VOL_STATE_DEGRADED: ++ case MPI2_RAID_VOL_STATE_OPTIMAL: ++ if (raid_device) ++ break; ++ ++ mpt2sas_config_get_volume_wwid(ioc, handle, &wwid); ++ if (!wwid) { ++ printk(MPT2SAS_ERR_FMT ++ "failure at %s:%d/%s()!\n", ioc->name, ++ __FILE__, __LINE__, __func__); ++ break; ++ } ++ ++ raid_device = kzalloc(sizeof(struct _raid_device), GFP_KERNEL); ++ if (!raid_device) { ++ printk(MPT2SAS_ERR_FMT ++ "failure at %s:%d/%s()!\n", ioc->name, ++ __FILE__, __LINE__, __func__); ++ break; ++ } ++ ++ raid_device->id = ioc->sas_id++; ++ raid_device->channel = RAID_CHANNEL; ++ raid_device->handle = handle; ++ raid_device->wwid = wwid; ++ _scsih_raid_device_add(ioc, raid_device); ++ rc = scsi_add_device(ioc->shost, RAID_CHANNEL, ++ raid_device->id, 0); ++ if (rc) ++ _scsih_raid_device_remove(ioc, raid_device); ++ break; ++ ++ case MPI2_RAID_VOL_STATE_INITIALIZING: ++ default: ++ break; ++ } ++} ++ ++/** ++ * _scsih_sas_ir_physical_disk_event - PD event ++ * @ioc: per adapter object ++ * @event_data: event data payload ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_ir_physical_disk_event(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ Mpi2EventDataIrPhysicalDisk_t *event_data) ++{ ++ u16 handle; ++ u32 state; ++ struct _sas_device *sas_device; ++ unsigned long flags; ++ Mpi2ConfigReply_t mpi_reply; ++ Mpi2SasDevicePage0_t sas_device_pg0; ++ u32 ioc_status; ++ ++ if (event_data->ReasonCode != MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED) ++ return; ++ ++ handle = le16_to_cpu(event_data->PhysDiskDevHandle); ++ state = le32_to_cpu(event_data->NewValue); ++ ++ dewtprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: handle(0x%04x), " ++ "old(0x%08x), new(0x%08x)\n", ioc->name, __func__, handle, ++ le32_to_cpu(event_data->PreviousValue), state)); ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = _scsih_sas_device_find_by_handle(ioc, handle); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ ++ switch (state) { ++ case MPI2_RAID_PD_STATE_ONLINE: ++ case MPI2_RAID_PD_STATE_DEGRADED: ++ case MPI2_RAID_PD_STATE_REBUILDING: ++ case MPI2_RAID_PD_STATE_OPTIMAL: ++ if (sas_device) { ++ sas_device->hidden_raid_component = 1; ++ return; ++ } ++ ++ if ((mpt2sas_config_get_sas_device_pg0(ioc, &mpi_reply, ++ &sas_device_pg0, MPI2_SAS_DEVICE_PGAD_FORM_HANDLE, ++ handle))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ ++ mpt2sas_transport_update_links(ioc, ++ le16_to_cpu(sas_device_pg0.ParentDevHandle), ++ handle, sas_device_pg0.PhyNum, MPI2_SAS_NEG_LINK_RATE_1_5); ++ ++ _scsih_add_device(ioc, handle, 0, 0, 1); ++ ++ break; ++ ++ case MPI2_RAID_PD_STATE_OFFLINE: ++ case MPI2_RAID_PD_STATE_NOT_CONFIGURED: ++ case MPI2_RAID_PD_STATE_NOT_COMPATIBLE: ++ case MPI2_RAID_PD_STATE_HOT_SPARE: ++ default: ++ break; ++ } ++} ++ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++/** ++ * _scsih_sas_ir_operation_status_event_debug - debug for IR op event ++ * @ioc: per adapter object ++ * @event_data: event data payload ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_ir_operation_status_event_debug(struct MPT2SAS_ADAPTER *ioc, ++ Mpi2EventDataIrOperationStatus_t *event_data) ++{ ++ char *reason_str = NULL; ++ ++ switch (event_data->RAIDOperation) { ++ case MPI2_EVENT_IR_RAIDOP_RESYNC: ++ reason_str = "resync"; ++ break; ++ case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION: ++ reason_str = "online capacity expansion"; ++ break; ++ case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK: ++ reason_str = "consistency check"; ++ break; ++ default: ++ reason_str = "unknown reason"; ++ break; ++ } ++ ++ printk(MPT2SAS_INFO_FMT "raid operational status: (%s)" ++ "\thandle(0x%04x), percent complete(%d)\n", ++ ioc->name, reason_str, ++ le16_to_cpu(event_data->VolDevHandle), ++ event_data->PercentComplete); ++} ++#endif ++ ++/** ++ * _scsih_sas_ir_operation_status_event - handle RAID operation events ++ * @ioc: per adapter object ++ * @VF_ID: ++ * @event_data: event data payload ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_sas_ir_operation_status_event(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ Mpi2EventDataIrOperationStatus_t *event_data) ++{ ++#ifdef CONFIG_SCSI_MPT2SAS_LOGGING ++ if (ioc->logging_level & MPT_DEBUG_EVENT_WORK_TASK) ++ _scsih_sas_ir_operation_status_event_debug(ioc, event_data); ++#endif ++} ++ ++/** ++ * _scsih_task_set_full - handle task set full ++ * @ioc: per adapter object ++ * @event_data: event data payload ++ * Context: user. ++ * ++ * Throttle back qdepth. ++ */ ++static void ++_scsih_task_set_full(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, ++ Mpi2EventDataTaskSetFull_t *event_data) ++{ ++ unsigned long flags; ++ struct _sas_device *sas_device; ++ static struct _raid_device *raid_device; ++ struct scsi_device *sdev; ++ int depth; ++ u16 current_depth; ++ u16 handle; ++ int id, channel; ++ u64 sas_address; ++ ++ current_depth = le16_to_cpu(event_data->CurrentDepth); ++ handle = le16_to_cpu(event_data->DevHandle); ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = _scsih_sas_device_find_by_handle(ioc, handle); ++ if (!sas_device) { ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ return; ++ } ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ id = sas_device->id; ++ channel = sas_device->channel; ++ sas_address = sas_device->sas_address; ++ ++ /* if hidden raid component, then change to volume characteristics */ ++ if (sas_device->hidden_raid_component && sas_device->volume_handle) { ++ spin_lock_irqsave(&ioc->raid_device_lock, flags); ++ raid_device = _scsih_raid_device_find_by_handle( ++ ioc, sas_device->volume_handle); ++ spin_unlock_irqrestore(&ioc->raid_device_lock, flags); ++ if (raid_device) { ++ id = raid_device->id; ++ channel = raid_device->channel; ++ handle = raid_device->handle; ++ sas_address = raid_device->wwid; ++ } ++ } ++ ++ if (ioc->logging_level & MPT_DEBUG_TASK_SET_FULL) ++ starget_printk(KERN_DEBUG, sas_device->starget, "task set " ++ "full: handle(0x%04x), sas_addr(0x%016llx), depth(%d)\n", ++ handle, (unsigned long long)sas_address, current_depth); ++ ++ shost_for_each_device(sdev, ioc->shost) { ++ if (sdev->id == id && sdev->channel == channel) { ++ if (current_depth > sdev->queue_depth) { ++ if (ioc->logging_level & ++ MPT_DEBUG_TASK_SET_FULL) ++ sdev_printk(KERN_INFO, sdev, "strange " ++ "observation, the queue depth is" ++ " (%d) meanwhile fw queue depth " ++ "is (%d)\n", sdev->queue_depth, ++ current_depth); ++ continue; ++ } ++ depth = scsi_track_queue_full(sdev, ++ current_depth - 1); ++ if (depth > 0) ++ sdev_printk(KERN_INFO, sdev, "Queue depth " ++ "reduced to (%d)\n", depth); ++ else if (depth < 0) ++ sdev_printk(KERN_INFO, sdev, "Tagged Command " ++ "Queueing is being disabled\n"); ++ else if (depth == 0) ++ if (ioc->logging_level & ++ MPT_DEBUG_TASK_SET_FULL) ++ sdev_printk(KERN_INFO, sdev, ++ "Queue depth not changed yet\n"); ++ } ++ } ++} ++ ++/** ++ * _scsih_mark_responding_sas_device - mark a sas_devices as responding ++ * @ioc: per adapter object ++ * @sas_address: sas address ++ * @slot: enclosure slot id ++ * @handle: device handle ++ * ++ * After host reset, find out whether devices are still responding. ++ * Used in _scsi_remove_unresponsive_sas_devices. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_mark_responding_sas_device(struct MPT2SAS_ADAPTER *ioc, u64 sas_address, ++ u16 slot, u16 handle) ++{ ++ struct MPT2SAS_TARGET *sas_target_priv_data; ++ struct scsi_target *starget; ++ struct _sas_device *sas_device; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ list_for_each_entry(sas_device, &ioc->sas_device_list, list) { ++ if (sas_device->sas_address == sas_address && ++ sas_device->slot == slot && sas_device->starget) { ++ sas_device->responding = 1; ++ starget_printk(KERN_INFO, sas_device->starget, ++ "handle(0x%04x), sas_addr(0x%016llx), enclosure " ++ "logical id(0x%016llx), slot(%d)\n", handle, ++ (unsigned long long)sas_device->sas_address, ++ (unsigned long long) ++ sas_device->enclosure_logical_id, ++ sas_device->slot); ++ if (sas_device->handle == handle) ++ goto out; ++ printk(KERN_INFO "\thandle changed from(0x%04x)!!!\n", ++ sas_device->handle); ++ sas_device->handle = handle; ++ starget = sas_device->starget; ++ sas_target_priv_data = starget->hostdata; ++ sas_target_priv_data->handle = handle; ++ goto out; ++ } ++ } ++ out: ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++} ++ ++/** ++ * _scsih_search_responding_sas_devices - ++ * @ioc: per adapter object ++ * ++ * After host reset, find out whether devices are still responding. ++ * If not remove. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_search_responding_sas_devices(struct MPT2SAS_ADAPTER *ioc) ++{ ++ Mpi2SasDevicePage0_t sas_device_pg0; ++ Mpi2ConfigReply_t mpi_reply; ++ u16 ioc_status; ++ u16 handle; ++ u32 device_info; ++ ++ printk(MPT2SAS_INFO_FMT "%s\n", ioc->name, __func__); ++ ++ if (list_empty(&ioc->sas_device_list)) ++ return; ++ ++ handle = 0xFFFF; ++ while (!(mpt2sas_config_get_sas_device_pg0(ioc, &mpi_reply, ++ &sas_device_pg0, MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE, ++ handle))) { ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE) ++ break; ++ handle = le16_to_cpu(sas_device_pg0.DevHandle); ++ device_info = le32_to_cpu(sas_device_pg0.DeviceInfo); ++ if (!(_scsih_is_end_device(device_info))) ++ continue; ++ _scsih_mark_responding_sas_device(ioc, ++ le64_to_cpu(sas_device_pg0.SASAddress), ++ le16_to_cpu(sas_device_pg0.Slot), handle); ++ } ++} ++ ++/** ++ * _scsih_mark_responding_raid_device - mark a raid_device as responding ++ * @ioc: per adapter object ++ * @wwid: world wide identifier for raid volume ++ * @handle: device handle ++ * ++ * After host reset, find out whether devices are still responding. ++ * Used in _scsi_remove_unresponsive_raid_devices. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_mark_responding_raid_device(struct MPT2SAS_ADAPTER *ioc, u64 wwid, ++ u16 handle) ++{ ++ struct MPT2SAS_TARGET *sas_target_priv_data; ++ struct scsi_target *starget; ++ struct _raid_device *raid_device; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ioc->raid_device_lock, flags); ++ list_for_each_entry(raid_device, &ioc->raid_device_list, list) { ++ if (raid_device->wwid == wwid && raid_device->starget) { ++ raid_device->responding = 1; ++ starget_printk(KERN_INFO, raid_device->starget, ++ "handle(0x%04x), wwid(0x%016llx)\n", handle, ++ (unsigned long long)raid_device->wwid); ++ if (raid_device->handle == handle) ++ goto out; ++ printk(KERN_INFO "\thandle changed from(0x%04x)!!!\n", ++ raid_device->handle); ++ raid_device->handle = handle; ++ starget = raid_device->starget; ++ sas_target_priv_data = starget->hostdata; ++ sas_target_priv_data->handle = handle; ++ goto out; ++ } ++ } ++ out: ++ spin_unlock_irqrestore(&ioc->raid_device_lock, flags); ++} ++ ++/** ++ * _scsih_search_responding_raid_devices - ++ * @ioc: per adapter object ++ * ++ * After host reset, find out whether devices are still responding. ++ * If not remove. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_search_responding_raid_devices(struct MPT2SAS_ADAPTER *ioc) ++{ ++ Mpi2RaidVolPage1_t volume_pg1; ++ Mpi2ConfigReply_t mpi_reply; ++ u16 ioc_status; ++ u16 handle; ++ ++ printk(MPT2SAS_INFO_FMT "%s\n", ioc->name, __func__); ++ ++ if (list_empty(&ioc->raid_device_list)) ++ return; ++ ++ handle = 0xFFFF; ++ while (!(mpt2sas_config_get_raid_volume_pg1(ioc, &mpi_reply, ++ &volume_pg1, MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE, handle))) { ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE) ++ break; ++ handle = le16_to_cpu(volume_pg1.DevHandle); ++ _scsih_mark_responding_raid_device(ioc, ++ le64_to_cpu(volume_pg1.WWID), handle); ++ } ++} ++ ++/** ++ * _scsih_mark_responding_expander - mark a expander as responding ++ * @ioc: per adapter object ++ * @sas_address: sas address ++ * @handle: ++ * ++ * After host reset, find out whether devices are still responding. ++ * Used in _scsi_remove_unresponsive_expanders. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_mark_responding_expander(struct MPT2SAS_ADAPTER *ioc, u64 sas_address, ++ u16 handle) ++{ ++ struct _sas_node *sas_expander; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ list_for_each_entry(sas_expander, &ioc->sas_expander_list, list) { ++ if (sas_expander->sas_address == sas_address) { ++ sas_expander->responding = 1; ++ if (sas_expander->handle != handle) { ++ printk(KERN_INFO "old handle(0x%04x)\n", ++ sas_expander->handle); ++ sas_expander->handle = handle; ++ } ++ goto out; ++ } ++ } ++ out: ++ spin_unlock_irqrestore(&ioc->sas_node_lock, flags); ++} ++ ++/** ++ * _scsih_search_responding_expanders - ++ * @ioc: per adapter object ++ * ++ * After host reset, find out whether devices are still responding. ++ * If not remove. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_search_responding_expanders(struct MPT2SAS_ADAPTER *ioc) ++{ ++ Mpi2ExpanderPage0_t expander_pg0; ++ Mpi2ConfigReply_t mpi_reply; ++ u16 ioc_status; ++ __le64 sas_address; ++ u16 handle; ++ ++ printk(MPT2SAS_INFO_FMT "%s\n", ioc->name, __func__); ++ ++ if (list_empty(&ioc->sas_expander_list)) ++ return; ++ ++ handle = 0xFFFF; ++ while (!(mpt2sas_config_get_expander_pg0(ioc, &mpi_reply, &expander_pg0, ++ MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL, handle))) { ++ ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE) ++ break; ++ ++ handle = le16_to_cpu(expander_pg0.DevHandle); ++ sas_address = le64_to_cpu(expander_pg0.SASAddress); ++ printk(KERN_INFO "\texpander present: handle(0x%04x), " ++ "sas_addr(0x%016llx)\n", handle, ++ (unsigned long long)sas_address); ++ _scsih_mark_responding_expander(ioc, sas_address, handle); ++ } ++ ++} ++ ++/** ++ * _scsih_remove_unresponding_devices - removing unresponding devices ++ * @ioc: per adapter object ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_remove_unresponding_devices(struct MPT2SAS_ADAPTER *ioc) ++{ ++ struct _sas_device *sas_device, *sas_device_next; ++ struct _sas_node *sas_expander; ++ struct _raid_device *raid_device, *raid_device_next; ++ ++ list_for_each_entry_safe(sas_device, sas_device_next, ++ &ioc->sas_device_list, list) { ++ if (sas_device->responding) { ++ sas_device->responding = 0; ++ continue; ++ } ++ if (sas_device->starget) ++ starget_printk(KERN_INFO, sas_device->starget, ++ "removing: handle(0x%04x), sas_addr(0x%016llx), " ++ "enclosure logical id(0x%016llx), slot(%d)\n", ++ sas_device->handle, ++ (unsigned long long)sas_device->sas_address, ++ (unsigned long long) ++ sas_device->enclosure_logical_id, ++ sas_device->slot); ++ _scsih_remove_device(ioc, sas_device->handle); ++ } ++ ++ list_for_each_entry_safe(raid_device, raid_device_next, ++ &ioc->raid_device_list, list) { ++ if (raid_device->responding) { ++ raid_device->responding = 0; ++ continue; ++ } ++ if (raid_device->starget) { ++ starget_printk(KERN_INFO, raid_device->starget, ++ "removing: handle(0x%04x), wwid(0x%016llx)\n", ++ raid_device->handle, ++ (unsigned long long)raid_device->wwid); ++ scsi_remove_target(&raid_device->starget->dev); ++ } ++ _scsih_raid_device_remove(ioc, raid_device); ++ } ++ ++ retry_expander_search: ++ sas_expander = NULL; ++ list_for_each_entry(sas_expander, &ioc->sas_expander_list, list) { ++ if (sas_expander->responding) { ++ sas_expander->responding = 0; ++ continue; ++ } ++ _scsih_expander_remove(ioc, sas_expander->handle); ++ goto retry_expander_search; ++ } ++} ++ ++/** ++ * mpt2sas_scsih_reset_handler - reset callback handler (for scsih) ++ * @ioc: per adapter object ++ * @reset_phase: phase ++ * ++ * The handler for doing any required cleanup or initialization. ++ * ++ * The reset phase can be MPT2_IOC_PRE_RESET, MPT2_IOC_AFTER_RESET, ++ * MPT2_IOC_DONE_RESET ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_scsih_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase) ++{ ++ switch (reset_phase) { ++ case MPT2_IOC_PRE_RESET: ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "MPT2_IOC_PRE_RESET\n", ioc->name, __func__)); ++ _scsih_fw_event_off(ioc); ++ break; ++ case MPT2_IOC_AFTER_RESET: ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "MPT2_IOC_AFTER_RESET\n", ioc->name, __func__)); ++ if (ioc->scsih_cmds.status & MPT2_CMD_PENDING) { ++ ioc->scsih_cmds.status |= MPT2_CMD_RESET; ++ mpt2sas_base_free_smid(ioc, ioc->scsih_cmds.smid); ++ complete(&ioc->scsih_cmds.done); ++ } ++ if (ioc->tm_cmds.status & MPT2_CMD_PENDING) { ++ ioc->tm_cmds.status |= MPT2_CMD_RESET; ++ mpt2sas_base_free_smid(ioc, ioc->tm_cmds.smid); ++ complete(&ioc->tm_cmds.done); ++ } ++ _scsih_fw_event_cleanup_queue(ioc); ++ _scsih_fw_event_on(ioc); ++ _scsih_flush_running_cmds(ioc); ++ break; ++ case MPT2_IOC_DONE_RESET: ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "MPT2_IOC_DONE_RESET\n", ioc->name, __func__)); ++ _scsih_sas_host_refresh(ioc, 0); ++ _scsih_search_responding_sas_devices(ioc); ++ _scsih_search_responding_raid_devices(ioc); ++ _scsih_search_responding_expanders(ioc); ++ break; ++ case MPT2_IOC_RUNNING: ++ dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: " ++ "MPT2_IOC_RUNNING\n", ioc->name, __func__)); ++ _scsih_remove_unresponding_devices(ioc); ++ break; ++ } ++} ++ ++/** ++ * _mpt2sas_fw_work - delayed task for processing firmware events ++ * @ioc: per adapter object ++ * @fw_event: The fw_event_work object ++ * Context: user. ++ * ++ * Return nothing. ++ */ ++static void ++_mpt2sas_fw_work(struct MPT2SAS_ADAPTER *ioc, struct fw_event_work *fw_event) ++{ ++ unsigned long flags; ++ ++ /* the queue is being flushed so ignore this event */ ++ spin_lock_irqsave(&ioc->fw_event_lock, flags); ++ if (ioc->fw_events_off || ioc->remove_host) { ++ spin_unlock_irqrestore(&ioc->fw_event_lock, flags); ++ _scsih_fw_event_free(ioc, fw_event); ++ return; ++ } ++ spin_unlock_irqrestore(&ioc->fw_event_lock, flags); ++ ++ if (ioc->shost_recovery) { ++ _scsih_fw_event_requeue(ioc, fw_event, 1000); ++ return; ++ } ++ ++ switch (fw_event->event) { ++#ifdef MPT2SAS_MULTIPATH ++ case MPT2SAS_ABRT_TASK_SET: ++ _scsih_abort_task_set(ioc, fw_event->VF_ID, ++ fw_event->event_data); ++ break; ++#endif ++ case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: ++ if (_scsih_sas_topology_change_event(ioc, fw_event->VF_ID, ++ fw_event->event_data, fw_event)) { ++ _scsih_fw_event_requeue(ioc, fw_event, 1000); ++ return; ++ } ++ break; ++ case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: ++ _scsih_sas_device_status_change_event(ioc, fw_event->VF_ID, ++ fw_event->event_data); ++ break; ++ case MPI2_EVENT_SAS_DISCOVERY: ++ _scsih_sas_discovery_event(ioc, fw_event->VF_ID, ++ fw_event->event_data); ++ break; ++ case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: ++ _scsih_sas_broadcast_primative_event(ioc, fw_event->VF_ID, ++ fw_event->event_data); ++ break; ++ case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: ++ _scsih_sas_enclosure_dev_status_change_event(ioc, ++ fw_event->VF_ID, fw_event->event_data); ++ break; ++ case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: ++ _scsih_sas_ir_config_change_event(ioc, fw_event->VF_ID, ++ fw_event->event_data); ++ break; ++ case MPI2_EVENT_IR_VOLUME: ++ _scsih_sas_ir_volume_event(ioc, fw_event->VF_ID, ++ fw_event->event_data); ++ break; ++ case MPI2_EVENT_IR_PHYSICAL_DISK: ++ _scsih_sas_ir_physical_disk_event(ioc, fw_event->VF_ID, ++ fw_event->event_data); ++ break; ++ case MPI2_EVENT_IR_OPERATION_STATUS: ++ _scsih_sas_ir_operation_status_event(ioc, fw_event->VF_ID, ++ fw_event->event_data); ++ break; ++ case MPI2_EVENT_TASK_SET_FULL: ++ _scsih_task_set_full(ioc, fw_event->VF_ID, ++ fw_event->event_data); ++ break; ++ } ++ _scsih_fw_event_free(ioc, fw_event); ++} ++ ++/** ++ * _firmware_event_work and _firmware_event_work_delayed ++ * @ioc: per adapter object ++ * @work: The fw_event_work object ++ * Context: user. ++ * ++ * wrappers for the work thread handling firmware events ++ * ++ * Return nothing. ++ */ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) ++static void ++_firmware_event_work(struct work_struct *work) ++{ ++ struct fw_event_work *fw_event = container_of(work, ++ struct fw_event_work, work); ++ ++ _mpt2sas_fw_work(fw_event->ioc, fw_event); ++} ++static void ++_firmware_event_work_delayed(struct work_struct *work) ++{ ++ struct fw_event_work *fw_event = container_of(work, ++ struct fw_event_work, delayed_work.work); ++ ++ _mpt2sas_fw_work(fw_event->ioc, fw_event); ++} ++#else ++static void ++_firmware_event_work(void *arg) ++{ ++ struct fw_event_work *fw_event = (struct fw_event_work *)arg; ++ ++ _mpt2sas_fw_work(fw_event->ioc, fw_event); ++} ++#endif ++ ++/** ++ * mpt2sas_scsih_event_callback - firmware event handler (called at ISR time) ++ * @ioc: per adapter object ++ * @VF_ID: virtual function id ++ * @reply: reply message frame(lower 32bit addr) ++ * Context: interrupt. ++ * ++ * This function merely adds a new work task into ioc->firmware_event_thread. ++ * The tasks are worked from _firmware_event_work in user context. ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_scsih_event_callback(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID, u32 reply) ++{ ++ struct fw_event_work *fw_event; ++ Mpi2EventNotificationReply_t *mpi_reply; ++ unsigned long flags; ++ u16 event; ++ ++ /* events turned off due to host reset or driver unloading */ ++ spin_lock_irqsave(&ioc->fw_event_lock, flags); ++ if (ioc->fw_events_off || ioc->remove_host) { ++ spin_unlock_irqrestore(&ioc->fw_event_lock, flags); ++ return; ++ } ++ spin_unlock_irqrestore(&ioc->fw_event_lock, flags); ++ ++ mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply); ++ event = le16_to_cpu(mpi_reply->Event); ++ ++ switch (event) { ++ /* handle these */ ++ case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: ++ { ++ Mpi2EventDataSasBroadcastPrimitive_t *baen_data = ++ (Mpi2EventDataSasBroadcastPrimitive_t *) ++ mpi_reply->EventData; ++ ++ if (baen_data->Primitive != ++ MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT || ++ ioc->broadcast_aen_busy) ++ return; ++ ioc->broadcast_aen_busy = 1; ++ break; ++ } ++ ++ case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: ++ _scsih_check_topo_delete_events(ioc, ++ (Mpi2EventDataSasTopologyChangeList_t *) ++ mpi_reply->EventData); ++ break; ++ ++ case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: ++ case MPI2_EVENT_IR_OPERATION_STATUS: ++ case MPI2_EVENT_SAS_DISCOVERY: ++ case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: ++ case MPI2_EVENT_IR_VOLUME: ++ case MPI2_EVENT_IR_PHYSICAL_DISK: ++ case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: ++ case MPI2_EVENT_TASK_SET_FULL: ++ break; ++ ++ default: /* ignore the rest */ ++ return; ++ } ++ ++ fw_event = kzalloc(sizeof(struct fw_event_work), GFP_ATOMIC); ++ if (!fw_event) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return; ++ } ++ fw_event->event_data = ++ kzalloc(mpi_reply->EventDataLength*4, GFP_ATOMIC); ++ if (!fw_event->event_data) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ kfree(fw_event); ++ return; ++ } ++ ++ if (event == MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST) { ++ Mpi2EventDataSasTopologyChangeList_t *topo_event_data = ++ (Mpi2EventDataSasTopologyChangeList_t *) ++ mpi_reply->EventData; ++ fw_event->retries = kzalloc(topo_event_data->NumEntries, ++ GFP_ATOMIC); ++ if (!fw_event->retries) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ kfree(fw_event->event_data); ++ kfree(fw_event); ++ return; ++ } ++ } ++ ++ memcpy(fw_event->event_data, mpi_reply->EventData, ++ mpi_reply->EventDataLength*4); ++ fw_event->ioc = ioc; ++ fw_event->VF_ID = VF_ID; ++ fw_event->event = event; ++ _scsih_fw_event_add(ioc, fw_event); ++} ++ ++/* shost template */ ++static struct scsi_host_template scsih_driver_template = { ++ .module = THIS_MODULE, ++ .name = "Fusion MPT SAS Host", ++ .proc_name = MPT2SAS_DRIVER_NAME, ++ .queuecommand = _scsih_qcmd, ++ .target_alloc = _scsih_target_alloc, ++ .slave_alloc = _scsih_slave_alloc, ++ .slave_configure = _scsih_slave_configure, ++ .target_destroy = _scsih_target_destroy, ++ .slave_destroy = _scsih_slave_destroy, ++ .change_queue_depth = _scsih_change_queue_depth, ++ .change_queue_type = _scsih_change_queue_type, ++ .eh_abort_handler = _scsih_abort, ++ .eh_device_reset_handler = _scsih_dev_reset, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) ++ .eh_target_reset_handler = _scsih_target_reset, ++#endif ++ .eh_host_reset_handler = _scsih_host_reset, ++ .bios_param = _scsih_bios_param, ++ .can_queue = 1, ++ .this_id = -1, ++ .sg_tablesize = MPT2SAS_SG_DEPTH, ++ .max_sectors = 8192, ++ .cmd_per_lun = 7, ++ .use_clustering = ENABLE_CLUSTERING, ++ .shost_attrs = mpt2sas_host_attrs, ++ .sdev_attrs = mpt2sas_dev_attrs, ++}; ++ ++/** ++ * _scsih_expander_node_remove - removing expander device from list. ++ * @ioc: per adapter object ++ * @sas_expander: the sas_device object ++ * Context: Calling function should acquire ioc->sas_node_lock. ++ * ++ * Removing object and freeing associated memory from the ++ * ioc->sas_expander_list. ++ * ++ * Return nothing. ++ */ ++static void ++_scsih_expander_node_remove(struct MPT2SAS_ADAPTER *ioc, ++ struct _sas_node *sas_expander) ++{ ++ struct _sas_port *mpt2sas_port; ++ struct _sas_device *sas_device; ++ struct _sas_node *expander_sibling; ++ unsigned long flags; ++ ++ if (!sas_expander) ++ return; ++ ++ /* remove sibling ports attached to this expander */ ++ retry_device_search: ++ list_for_each_entry(mpt2sas_port, ++ &sas_expander->sas_port_list, port_list) { ++ if (mpt2sas_port->remote_identify.device_type == ++ SAS_END_DEVICE) { ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = ++ mpt2sas_scsih_sas_device_find_by_sas_address(ioc, ++ mpt2sas_port->remote_identify.sas_address); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ if (!sas_device) ++ continue; ++ _scsih_remove_device(ioc, sas_device->handle); ++ if (ioc->shost_recovery) ++ return; ++ goto retry_device_search; ++ } ++ } ++ ++ retry_expander_search: ++ list_for_each_entry(mpt2sas_port, ++ &sas_expander->sas_port_list, port_list) { ++ ++ if (mpt2sas_port->remote_identify.device_type == ++ MPI2_SAS_DEVICE_INFO_EDGE_EXPANDER || ++ mpt2sas_port->remote_identify.device_type == ++ MPI2_SAS_DEVICE_INFO_FANOUT_EXPANDER) { ++ ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ expander_sibling = ++ mpt2sas_scsih_expander_find_by_sas_address( ++ ioc, mpt2sas_port->remote_identify.sas_address); ++ spin_unlock_irqrestore(&ioc->sas_node_lock, flags); ++ if (!expander_sibling) ++ continue; ++ _scsih_expander_remove(ioc, expander_sibling->handle); ++ if (ioc->shost_recovery) ++ return; ++ goto retry_expander_search; ++ } ++ } ++ ++ mpt2sas_transport_port_remove(ioc, sas_expander->sas_address, ++ sas_expander->parent_handle); ++ ++ printk(MPT2SAS_INFO_FMT "expander_remove: handle" ++ "(0x%04x), sas_addr(0x%016llx)\n", ioc->name, ++ sas_expander->handle, (unsigned long long) ++ sas_expander->sas_address); ++ ++ list_del(&sas_expander->list); ++ kfree(sas_expander->phy); ++ kfree(sas_expander); ++} ++ ++/** ++ * _scsih_remove - detach and remove add host ++ * @pdev: PCI device struct ++ * ++ * Return nothing. ++ */ ++static void __devexit ++_scsih_remove(struct pci_dev *pdev) ++{ ++ struct Scsi_Host *shost = pci_get_drvdata(pdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ struct _sas_port *mpt2sas_port; ++ struct _sas_device *sas_device; ++ struct _sas_node *expander_sibling; ++ struct workqueue_struct *wq; ++ unsigned long flags; ++ ++ ioc->remove_host = 1; ++ _scsih_fw_event_off(ioc); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)) ++ _scsih_fw_event_cleanup_queue(ioc); ++#endif ++ ++ spin_lock_irqsave(&ioc->fw_event_lock, flags); ++ wq = ioc->firmware_event_thread; ++ ioc->firmware_event_thread = NULL; ++ spin_unlock_irqrestore(&ioc->fw_event_lock, flags); ++ if (wq) ++ destroy_workqueue(wq); ++ ++ /* free ports attached to the sas_host */ ++ retry_again: ++ list_for_each_entry(mpt2sas_port, ++ &ioc->sas_hba.sas_port_list, port_list) { ++ if (mpt2sas_port->remote_identify.device_type == ++ SAS_END_DEVICE) { ++ sas_device = ++ mpt2sas_scsih_sas_device_find_by_sas_address(ioc, ++ mpt2sas_port->remote_identify.sas_address); ++ if (sas_device) { ++ _scsih_remove_device(ioc, sas_device->handle); ++ goto retry_again; ++ } ++ } else { ++ expander_sibling = ++ mpt2sas_scsih_expander_find_by_sas_address(ioc, ++ mpt2sas_port->remote_identify.sas_address); ++ if (expander_sibling) { ++ _scsih_expander_remove(ioc, ++ expander_sibling->handle); ++ goto retry_again; ++ } ++ } ++ } ++ ++ /* free phys attached to the sas_host */ ++ if (ioc->sas_hba.num_phys) { ++ kfree(ioc->sas_hba.phy); ++ ioc->sas_hba.phy = NULL; ++ ioc->sas_hba.num_phys = 0; ++ } ++ ++ sas_remove_host(shost); ++ mpt2sas_base_detach(ioc); ++ list_del(&ioc->list); ++ scsi_remove_host(shost); ++ scsi_host_put(shost); ++} ++ ++/** ++ * _scsih_probe_boot_devices - reports 1st device ++ * @ioc: per adapter object ++ * ++ * If specified in bios page 2, this routine reports the 1st ++ * device scsi-ml or sas transport for persistent boot device ++ * purposes. Please refer to function _scsih_determine_boot_device() ++ */ ++static void ++_scsih_probe_boot_devices(struct MPT2SAS_ADAPTER *ioc) ++{ ++ u8 is_raid; ++ void *device; ++ struct _sas_device *sas_device; ++ struct _raid_device *raid_device; ++ u16 handle, parent_handle; ++ u64 sas_address; ++ unsigned long flags; ++ int rc; ++ ++ device = NULL; ++ if (ioc->req_boot_device.device) { ++ device = ioc->req_boot_device.device; ++ is_raid = ioc->req_boot_device.is_raid; ++ } else if (ioc->req_alt_boot_device.device) { ++ device = ioc->req_alt_boot_device.device; ++ is_raid = ioc->req_alt_boot_device.is_raid; ++ } else if (ioc->current_boot_device.device) { ++ device = ioc->current_boot_device.device; ++ is_raid = ioc->current_boot_device.is_raid; ++ } ++ ++ if (!device) ++ return; ++ ++ if (is_raid) { ++ raid_device = device; ++ rc = scsi_add_device(ioc->shost, RAID_CHANNEL, ++ raid_device->id, 0); ++ if (rc) ++ _scsih_raid_device_remove(ioc, raid_device); ++ } else { ++ sas_device = device; ++ handle = sas_device->handle; ++ parent_handle = sas_device->parent_handle; ++ sas_address = sas_device->sas_address; ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ list_move_tail(&sas_device->list, &ioc->sas_device_list); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ if (!mpt2sas_transport_port_add(ioc, handle, parent_handle)) { ++ _scsih_sas_device_remove(ioc, sas_device); ++ } else if (!sas_device->starget) { ++ mpt2sas_transport_port_remove(ioc, sas_address, ++ parent_handle); ++ _scsih_sas_device_remove(ioc, sas_device); ++ } ++ } ++} ++ ++/** ++ * _scsih_probe_raid - reporting raid volumes to scsi-ml ++ * @ioc: per adapter object ++ * ++ * Called during initial loading of the driver. ++ */ ++static void ++_scsih_probe_raid(struct MPT2SAS_ADAPTER *ioc) ++{ ++ struct _raid_device *raid_device, *raid_next; ++ int rc; ++ ++ list_for_each_entry_safe(raid_device, raid_next, ++ &ioc->raid_device_list, list) { ++ if (raid_device->starget) ++ continue; ++ rc = scsi_add_device(ioc->shost, RAID_CHANNEL, ++ raid_device->id, 0); ++ if (rc) ++ _scsih_raid_device_remove(ioc, raid_device); ++ } ++} ++ ++/** ++ * _scsih_probe_sas - reporting sas devices to sas transport ++ * @ioc: per adapter object ++ * ++ * Called during initial loading of the driver. ++ */ ++static void ++_scsih_probe_sas(struct MPT2SAS_ADAPTER *ioc) ++{ ++ struct _sas_device *sas_device, *next; ++ unsigned long flags; ++ u16 handle, parent_handle; ++ u64 sas_address; ++ ++ /* SAS Device List */ ++ list_for_each_entry_safe(sas_device, next, &ioc->sas_device_init_list, ++ list) { ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ list_move_tail(&sas_device->list, &ioc->sas_device_list); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ ++ handle = sas_device->handle; ++ parent_handle = sas_device->parent_handle; ++ sas_address = sas_device->sas_address; ++ if (!mpt2sas_transport_port_add(ioc, handle, parent_handle)) { ++ _scsih_sas_device_remove(ioc, sas_device); ++ } else if (!sas_device->starget) { ++ mpt2sas_transport_port_remove(ioc, sas_address, ++ parent_handle); ++ _scsih_sas_device_remove(ioc, sas_device); ++ } ++ } ++} ++ ++/** ++ * _scsih_probe_devices - probing for devices ++ * @ioc: per adapter object ++ * ++ * Called during initial loading of the driver. ++ */ ++static void ++_scsih_probe_devices(struct MPT2SAS_ADAPTER *ioc) ++{ ++ u16 volume_mapping_flags = ++ le16_to_cpu(ioc->ioc_pg8.IRVolumeMappingFlags) & ++ MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE; ++ ++ if (!(ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR)) ++ return; /* return when IOC doesn't support initiator mode */ ++ ++ _scsih_probe_boot_devices(ioc); ++ ++ if (ioc->ir_firmware) { ++ if ((volume_mapping_flags & ++ MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING)) { ++ _scsih_probe_sas(ioc); ++ _scsih_probe_raid(ioc); ++ } else { ++ _scsih_probe_raid(ioc); ++ _scsih_probe_sas(ioc); ++ } ++ } else ++ _scsih_probe_sas(ioc); ++} ++ ++/** ++ * _scsih_probe - attach and add scsi host ++ * @pdev: PCI device struct ++ * @id: pci device id ++ * ++ * Returns 0 success, anything else error. ++ */ ++static int ++_scsih_probe(struct pci_dev *pdev, const struct pci_device_id *id) ++{ ++ struct MPT2SAS_ADAPTER *ioc; ++ struct Scsi_Host *shost; ++ ++ shost = scsi_host_alloc(&scsih_driver_template, ++ sizeof(struct MPT2SAS_ADAPTER)); ++ if (!shost) ++ return -ENODEV; ++ ++ /* init local params */ ++ ioc = shost_private(shost); ++ memset(ioc, 0, sizeof(struct MPT2SAS_ADAPTER)); ++ INIT_LIST_HEAD(&ioc->list); ++ list_add_tail(&ioc->list, &mpt2sas_ioc_list); ++ ioc->shost = shost; ++ ioc->id = mpt_ids++; ++ sprintf(ioc->name, "%s%d", MPT2SAS_DRIVER_NAME, ioc->id); ++ ioc->pdev = pdev; ++ ioc->scsi_io_cb_idx = scsi_io_cb_idx; ++ ioc->tm_cb_idx = tm_cb_idx; ++ ioc->ctl_cb_idx = ctl_cb_idx; ++ ioc->base_cb_idx = base_cb_idx; ++ ioc->transport_cb_idx = transport_cb_idx; ++ ioc->scsih_cb_idx = scsih_cb_idx; ++ ioc->config_cb_idx = config_cb_idx; ++ ioc->logging_level = logging_level; ++ /* misc semaphores and spin locks */ ++ spin_lock_init(&ioc->ioc_reset_in_progress_lock); ++ spin_lock_init(&ioc->scsi_lookup_lock); ++ spin_lock_init(&ioc->sas_device_lock); ++ spin_lock_init(&ioc->sas_node_lock); ++ spin_lock_init(&ioc->fw_event_lock); ++ spin_lock_init(&ioc->raid_device_lock); ++ ++ INIT_LIST_HEAD(&ioc->sas_device_list); ++ INIT_LIST_HEAD(&ioc->sas_device_init_list); ++ INIT_LIST_HEAD(&ioc->sas_expander_list); ++ INIT_LIST_HEAD(&ioc->fw_event_list); ++ INIT_LIST_HEAD(&ioc->raid_device_list); ++ INIT_LIST_HEAD(&ioc->sas_hba.sas_port_list); ++ ++ /* init shost parameters */ ++ shost->max_cmd_len = 16; ++ shost->max_lun = max_lun; ++ shost->transportt = mpt2sas_transport_template; ++ shost->unique_id = ioc->id; ++ ++ if ((scsi_add_host(shost, &pdev->dev))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ list_del(&ioc->list); ++ goto out_add_shost_fail; ++ } ++ ++#if defined(EEDP_SUPPORT) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) ++ scsi_host_set_prot(shost, SHOST_DIF_TYPE1_PROTECTION ++ | SHOST_DIF_TYPE3_PROTECTION); ++ scsi_host_set_guard(shost, SHOST_DIX_GUARD_CRC); ++#endif ++#endif ++ ++ /* event thread */ ++ snprintf(ioc->firmware_event_name, sizeof(ioc->firmware_event_name), ++ "fw_event%d", ioc->id); ++ ioc->firmware_event_thread = create_singlethread_workqueue( ++ ioc->firmware_event_name); ++ if (!ioc->firmware_event_thread) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out_thread_fail; ++ } ++ ++ ioc->wait_for_port_enable_to_complete = 1; ++ if ((mpt2sas_base_attach(ioc))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out_attach_fail; ++ } ++ ++ ioc->wait_for_port_enable_to_complete = 0; ++ _scsih_probe_devices(ioc); ++ return 0; ++ ++ out_attach_fail: ++ destroy_workqueue(ioc->firmware_event_thread); ++ out_thread_fail: ++ list_del(&ioc->list); ++ scsi_remove_host(shost); ++ out_add_shost_fail: ++ return -ENODEV; ++} ++ ++#ifdef CONFIG_PM ++/** ++ * _scsih_suspend - power management suspend main entry point ++ * @pdev: PCI device struct ++ * @state: PM state change to (usually PCI_D3) ++ * ++ * Returns 0 success, anything else error. ++ */ ++static int ++_scsih_suspend(struct pci_dev *pdev, pm_message_t state) ++{ ++ struct Scsi_Host *shost = pci_get_drvdata(pdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ u32 device_state; ++ ++ mpt2sas_base_stop_watchdog(ioc); ++ flush_scheduled_work(); ++ scsi_block_requests(shost); ++ device_state = pci_choose_state(pdev, state); ++ printk(MPT2SAS_INFO_FMT "pdev=0x%p, slot=%s, entering " ++ "operating state [D%d]\n", ioc->name, pdev, ++ pci_name(pdev), device_state); ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) ++ mpt2sas_base_save_msix_table(ioc); ++#endif ++ mpt2sas_base_free_resources(ioc); ++ pci_save_state(pdev); ++ pci_disable_device(pdev); ++ pci_set_power_state(pdev, device_state); ++ return 0; ++} ++ ++/** ++ * _scsih_resume - power management resume main entry point ++ * @pdev: PCI device struct ++ * ++ * Returns 0 success, anything else error. ++ */ ++static int ++_scsih_resume(struct pci_dev *pdev) ++{ ++ struct Scsi_Host *shost = pci_get_drvdata(pdev); ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ u32 device_state = pdev->current_state; ++ int r; ++ ++ printk(MPT2SAS_INFO_FMT "pdev=0x%p, slot=%s, previous " ++ "operating state [D%d]\n", ioc->name, pdev, ++ pci_name(pdev), device_state); ++ ++ pci_set_power_state(pdev, PCI_D0); ++ pci_enable_wake(pdev, PCI_D0, 0); ++ pci_restore_state(pdev); ++ ioc->pdev = pdev; ++ r = mpt2sas_base_map_resources(ioc); ++ if (r) ++ return r; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) ++ mpt2sas_base_restore_msix_table(ioc); ++#endif ++ mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, SOFT_RESET); ++ scsi_unblock_requests(shost); ++ mpt2sas_base_start_watchdog(ioc); ++ return 0; ++} ++#endif /* CONFIG_PM */ ++ ++ ++static struct pci_driver scsih_driver = { ++ .name = MPT2SAS_DRIVER_NAME, ++ .id_table = scsih_pci_table, ++ .probe = _scsih_probe, ++ .remove = __devexit_p(_scsih_remove), ++#ifdef CONFIG_PM ++ .suspend = _scsih_suspend, ++ .resume = _scsih_resume, ++#endif ++}; ++ ++ ++/** ++ * _scsih_init - main entry point for this driver. ++ * ++ * Returns 0 success, anything else error. ++ */ ++static int __init ++_scsih_init(void) ++{ ++ int error; ++ ++ mpt_ids = 0; ++ ++ printk(KERN_INFO "%s version %s loaded\n", MPT2SAS_DRIVER_NAME, ++ MPT2SAS_DRIVER_VERSION); ++ ++ mpt2sas_transport_template = ++ sas_attach_transport(&mpt2sas_transport_functions); ++ if (!mpt2sas_transport_template) ++ return -ENODEV; ++ ++ mpt2sas_base_initialize_callback_handler(); ++ ++ /* queuecommand callback hander */ ++ scsi_io_cb_idx = mpt2sas_base_register_callback_handler(_scsih_io_done); ++ ++ /* task managment callback handler */ ++ tm_cb_idx = mpt2sas_base_register_callback_handler(_scsih_tm_done); ++ ++ /* base internal commands callback handler */ ++ base_cb_idx = mpt2sas_base_register_callback_handler(mpt2sas_base_done); ++ ++ /* transport internal commands callback handler */ ++ transport_cb_idx = mpt2sas_base_register_callback_handler( ++ mpt2sas_transport_done); ++ ++ /* scsih internal commands callback handler */ ++ scsih_cb_idx = mpt2sas_base_register_callback_handler(_scsih_done); ++ ++ /* configuration page API internal commands callback handler */ ++ config_cb_idx = mpt2sas_base_register_callback_handler( ++ mpt2sas_config_done); ++ ++ /* ctl module callback handler */ ++ ctl_cb_idx = mpt2sas_base_register_callback_handler(mpt2sas_ctl_done); ++ ++ mpt2sas_ctl_init(); ++ ++#if defined(TARGET_MODE) ++ mpt2sas_stm_init(); ++#endif ++ ++ error = pci_register_driver(&scsih_driver); ++ if (error) ++ sas_release_transport(mpt2sas_transport_template); ++ ++ return error; ++} ++ ++/** ++ * _scsih_exit - exit point for this driver (when it is a module). ++ * ++ * Returns 0 success, anything else error. ++ */ ++static void __exit ++_scsih_exit(void) ++{ ++ printk(KERN_INFO "mpt2sas version %s unloading\n", ++ MPT2SAS_DRIVER_VERSION); ++ ++ pci_unregister_driver(&scsih_driver); ++ ++ sas_release_transport(mpt2sas_transport_template); ++ mpt2sas_base_release_callback_handler(scsi_io_cb_idx); ++ mpt2sas_base_release_callback_handler(tm_cb_idx); ++ mpt2sas_base_release_callback_handler(base_cb_idx); ++ mpt2sas_base_release_callback_handler(transport_cb_idx); ++ mpt2sas_base_release_callback_handler(scsih_cb_idx); ++ mpt2sas_base_release_callback_handler(config_cb_idx); ++ mpt2sas_base_release_callback_handler(ctl_cb_idx); ++ ++#if defined(TARGET_MODE) ++ mpt2sas_stm_exit(); ++#endif ++ mpt2sas_ctl_exit(); ++} ++ ++module_init(_scsih_init); ++module_exit(_scsih_exit); +diff -r 2c3db38968de drivers/scsi/mpt2sas/mpt2sas_transport.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/scsi/mpt2sas/mpt2sas_transport.c Tue Sep 01 16:14:41 2009 +0100 +@@ -0,0 +1,1258 @@ ++/* ++ * SAS Transport Layer for MPT (Message Passing Technology) based controllers ++ * ++ * This code is based on drivers/scsi/mpt2sas/mpt2_transport.c ++ * Copyright (C) 2007-2008 LSI Corporation ++ * (mailto:DL-MPTFusionLinux@lsi.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * NO WARRANTY ++ * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR ++ * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT ++ * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is ++ * solely responsible for determining the appropriateness of using and ++ * distributing the Program and assumes all risks associated with its ++ * exercise of rights under this Agreement, including but not limited to ++ * the risks and costs of program errors, damage to or loss of data, ++ * programs or equipment, and unavailability or interruption of operations. ++ ++ * DISCLAIMER OF LIABILITY ++ * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR ++ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED ++ * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ++ ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, ++ * USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mpt2sas_base.h" ++ ++/** ++ * _transport_sas_node_find_by_handle - sas node search ++ * @ioc: per adapter object ++ * @handle: expander or hba handle (assigned by firmware) ++ * Context: Calling function should acquire ioc->sas_node_lock. ++ * ++ * Search for either hba phys or expander device based on handle, then returns ++ * the sas_node object. ++ */ ++static struct _sas_node * ++_transport_sas_node_find_by_handle(struct MPT2SAS_ADAPTER *ioc, u16 handle) ++{ ++ int i; ++ ++ for (i = 0; i < ioc->sas_hba.num_phys; i++) ++ if (ioc->sas_hba.phy[i].handle == handle) ++ return &ioc->sas_hba; ++ ++ return mpt2sas_scsih_expander_find_by_handle(ioc, handle); ++} ++ ++/** ++ * _transport_convert_phy_link_rate - ++ * @link_rate: link rate returned from mpt firmware ++ * ++ * Convert link_rate from mpi fusion into sas_transport form. ++ */ ++static enum sas_linkrate ++_transport_convert_phy_link_rate(u8 link_rate) ++{ ++ enum sas_linkrate rc; ++ ++ switch (link_rate) { ++ case MPI2_SAS_NEG_LINK_RATE_1_5: ++ rc = SAS_LINK_RATE_1_5_GBPS; ++ break; ++ case MPI2_SAS_NEG_LINK_RATE_3_0: ++ rc = SAS_LINK_RATE_3_0_GBPS; ++ break; ++ case MPI2_SAS_NEG_LINK_RATE_6_0: ++ rc = SAS_LINK_RATE_6_0_GBPS; ++ break; ++ case MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED: ++ rc = SAS_PHY_DISABLED; ++ break; ++ case MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED: ++ rc = SAS_LINK_RATE_FAILED; ++ break; ++ case MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR: ++ rc = SAS_SATA_PORT_SELECTOR; ++ break; ++ case MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS: ++ /* only supported in SLES10 SP1 kernels, not RHEL5 */ ++/* rc = SAS_PHY_RESET_IN_PROGRESS; ++ * break; ++ */ ++ default: ++ case MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE: ++ case MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE: ++ rc = SAS_LINK_RATE_UNKNOWN; ++ break; ++ } ++ return rc; ++} ++ ++/** ++ * _transport_set_identify - set identify for phys and end devices ++ * @ioc: per adapter object ++ * @handle: device handle ++ * @identify: sas identify info ++ * ++ * Populates sas identify info. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_transport_set_identify(struct MPT2SAS_ADAPTER *ioc, u16 handle, ++ struct sas_identify *identify) ++{ ++ Mpi2SasDevicePage0_t sas_device_pg0; ++ Mpi2ConfigReply_t mpi_reply; ++ u32 device_info; ++ u32 ioc_status; ++ ++ if (ioc->shost_recovery) { ++ printk(MPT2SAS_INFO_FMT "%s: host reset in progress!\n", ++ __func__, ioc->name); ++ return -EFAULT; ++ } ++ ++ if ((mpt2sas_config_get_sas_device_pg0(ioc, &mpi_reply, &sas_device_pg0, ++ MPI2_SAS_DEVICE_PGAD_FORM_HANDLE, handle))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return -ENXIO; ++ } ++ ++ ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & ++ MPI2_IOCSTATUS_MASK; ++ if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { ++ printk(MPT2SAS_ERR_FMT "handle(0x%04x), ioc_status(0x%04x)" ++ "\nfailure at %s:%d/%s()!\n", ioc->name, handle, ioc_status, ++ __FILE__, __LINE__, __func__); ++ return -EIO; ++ } ++ ++ memset(identify, 0, sizeof(identify)); ++ device_info = le32_to_cpu(sas_device_pg0.DeviceInfo); ++ ++ /* sas_address */ ++ identify->sas_address = le64_to_cpu(sas_device_pg0.SASAddress); ++ ++ /* device_type */ ++ switch (device_info & MPI2_SAS_DEVICE_INFO_MASK_DEVICE_TYPE) { ++ case MPI2_SAS_DEVICE_INFO_NO_DEVICE: ++ identify->device_type = SAS_PHY_UNUSED; ++ break; ++ case MPI2_SAS_DEVICE_INFO_END_DEVICE: ++ identify->device_type = SAS_END_DEVICE; ++ break; ++ case MPI2_SAS_DEVICE_INFO_EDGE_EXPANDER: ++ identify->device_type = SAS_EDGE_EXPANDER_DEVICE; ++ break; ++ case MPI2_SAS_DEVICE_INFO_FANOUT_EXPANDER: ++ identify->device_type = SAS_FANOUT_EXPANDER_DEVICE; ++ break; ++ } ++ ++ /* initiator_port_protocols */ ++ if (device_info & MPI2_SAS_DEVICE_INFO_SSP_INITIATOR) ++ identify->initiator_port_protocols |= SAS_PROTOCOL_SSP; ++ if (device_info & MPI2_SAS_DEVICE_INFO_STP_INITIATOR) ++ identify->initiator_port_protocols |= SAS_PROTOCOL_STP; ++ if (device_info & MPI2_SAS_DEVICE_INFO_SMP_INITIATOR) ++ identify->initiator_port_protocols |= SAS_PROTOCOL_SMP; ++ if (device_info & MPI2_SAS_DEVICE_INFO_SATA_HOST) ++ identify->initiator_port_protocols |= SAS_PROTOCOL_SATA; ++ ++ /* target_port_protocols */ ++ if (device_info & MPI2_SAS_DEVICE_INFO_SSP_TARGET) ++ identify->target_port_protocols |= SAS_PROTOCOL_SSP; ++ if (device_info & MPI2_SAS_DEVICE_INFO_STP_TARGET) ++ identify->target_port_protocols |= SAS_PROTOCOL_STP; ++ if (device_info & MPI2_SAS_DEVICE_INFO_SMP_TARGET) ++ identify->target_port_protocols |= SAS_PROTOCOL_SMP; ++ if (device_info & MPI2_SAS_DEVICE_INFO_SATA_DEVICE) ++ identify->target_port_protocols |= SAS_PROTOCOL_SATA; ++ ++ return 0; ++} ++ ++/** ++ * mpt2sas_transport_done - internal transport layer callback handler. ++ * @ioc: per adapter object ++ * @smid: system request message index ++ * @VF_ID: virtual function id ++ * @reply: reply message frame(lower 32bit addr) ++ * ++ * Callback handler when sending internal generated transport cmds. ++ * The callback index passed is `ioc->transport_cb_idx` ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_transport_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, ++ u32 reply) ++{ ++ MPI2DefaultReply_t *mpi_reply; ++ ++ mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply); ++ if (ioc->transport_cmds.status == MPT2_CMD_NOT_USED) ++ return; ++ if (ioc->transport_cmds.smid != smid) ++ return; ++ ioc->transport_cmds.status |= MPT2_CMD_COMPLETE; ++ if (mpi_reply) { ++ memcpy(ioc->transport_cmds.reply, mpi_reply, ++ mpi_reply->MsgLength*4); ++ ioc->transport_cmds.status |= MPT2_CMD_REPLY_VALID; ++ } ++ ioc->transport_cmds.status &= ~MPT2_CMD_PENDING; ++ complete(&ioc->transport_cmds.done); ++} ++ ++#if defined(MPT_WIDE_PORT_API) ++/* report manufacture request structure */ ++struct rep_manu_request{ ++ u8 smp_frame_type; ++ u8 function; ++ u8 reserved; ++ u8 request_length; ++}; ++ ++/* report manufacture reply structure */ ++struct rep_manu_reply{ ++ u8 smp_frame_type; /* 0x41 */ ++ u8 function; /* 0x01 */ ++ u8 function_result; ++ u8 response_length; ++ u16 expander_change_count; ++ u8 reserved0[2]; ++ u8 sas_format:1; ++ u8 reserved1:7; ++ u8 reserved2[3]; ++ u8 vendor_id[SAS_EXPANDER_VENDOR_ID_LEN]; ++ u8 product_id[SAS_EXPANDER_PRODUCT_ID_LEN]; ++ u8 product_rev[SAS_EXPANDER_PRODUCT_REV_LEN]; ++ u8 component_vendor_id[SAS_EXPANDER_COMPONENT_VENDOR_ID_LEN]; ++ u16 component_id; ++ u8 component_revision_id; ++ u8 reserved3; ++ u8 vendor_specific[8]; ++}; ++ ++/** ++ * transport_expander_report_manufacture - obtain SMP report_manufacture ++ * @ioc: per adapter object ++ * @sas_address: expander sas address ++ * @edev: the sas_expander_device object ++ * ++ * Fills in the sas_expander_device object when SMP port is created. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_transport_expander_report_manufacture(struct MPT2SAS_ADAPTER *ioc, ++ u64 sas_address, struct sas_expander_device *edev) ++{ ++ Mpi2SmpPassthroughRequest_t *mpi_request; ++ Mpi2SmpPassthroughReply_t *mpi_reply; ++ struct rep_manu_reply *manufacture_reply; ++ struct rep_manu_request *manufacture_request; ++ int rc; ++ u16 smid; ++ u32 ioc_state; ++ unsigned long timeleft; ++ void *psge; ++ u32 sgl_flags; ++ u8 issue_reset = 0; ++ void *data_out = NULL; ++ dma_addr_t data_out_dma; ++ u32 sz; ++ u64 *sas_address_le; ++ u16 wait_state_count; ++ ++ if (ioc->shost_recovery) { ++ printk(MPT2SAS_INFO_FMT "%s: host reset in progress!\n", ++ __func__, ioc->name); ++ return -EFAULT; ++ } ++ ++ mutex_lock(&ioc->transport_cmds.mutex); ++ ++ if (ioc->transport_cmds.status != MPT2_CMD_NOT_USED) { ++ printk(MPT2SAS_ERR_FMT "%s: transport_cmds in use\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ioc->transport_cmds.status = MPT2_CMD_PENDING; ++ ++ wait_state_count = 0; ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { ++ if (wait_state_count++ == 10) { ++ printk(MPT2SAS_ERR_FMT ++ "%s: failed due to ioc not operational\n", ++ ioc->name, __func__); ++ rc = -EFAULT; ++ goto out; ++ } ++ ssleep(1); ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ printk(MPT2SAS_INFO_FMT "%s: waiting for " ++ "operational state(count=%d)\n", ioc->name, ++ __func__, wait_state_count); ++ } ++ if (wait_state_count) ++ printk(MPT2SAS_INFO_FMT "%s: ioc is operational\n", ++ ioc->name, __func__); ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->transport_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ rc = 0; ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ioc->transport_cmds.smid = smid; ++ ++ sz = sizeof(struct rep_manu_request) + sizeof(struct rep_manu_reply); ++ data_out = pci_alloc_consistent(ioc->pdev, sz, &data_out_dma); ++ ++ if (!data_out) { ++ printk(KERN_ERR "failure at %s:%d/%s()!\n", __FILE__, ++ __LINE__, __func__); ++ rc = -ENOMEM; ++ mpt2sas_base_free_smid(ioc, smid); ++ goto out; ++ } ++ ++ manufacture_request = data_out; ++ manufacture_request->smp_frame_type = 0x40; ++ manufacture_request->function = 1; ++ manufacture_request->reserved = 0; ++ manufacture_request->request_length = 0; ++ ++ memset(mpi_request, 0, sizeof(Mpi2SmpPassthroughRequest_t)); ++ mpi_request->Function = MPI2_FUNCTION_SMP_PASSTHROUGH; ++ mpi_request->PhysicalPort = 0xFF; ++ sas_address_le = (u64 *)&mpi_request->SASAddress; ++ *sas_address_le = cpu_to_le64(sas_address); ++ mpi_request->RequestDataLength = sizeof(struct rep_manu_request); ++ psge = &mpi_request->SGL; ++ ++ /* WRITE sgel first */ ++ sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | ++ MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC); ++ sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; ++ ioc->base_add_sg_single(psge, sgl_flags | ++ sizeof(struct rep_manu_request), data_out_dma); ++ ++ /* incr sgel */ ++ psge += ioc->sge_size; ++ ++ /* READ sgel last */ ++ sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | ++ MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | ++ MPI2_SGE_FLAGS_END_OF_LIST); ++ sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; ++ ioc->base_add_sg_single(psge, sgl_flags | ++ sizeof(struct rep_manu_reply), data_out_dma + ++ sizeof(struct rep_manu_request)); ++ ++ dtransportprintk(ioc, printk(MPT2SAS_DEBUG_FMT "report_manufacture - " ++ "send to sas_addr(0x%016llx)\n", ioc->name, ++ (unsigned long long)sas_address)); ++ mpt2sas_base_put_smid_default(ioc, smid, 0 /* VF_ID */); ++ timeleft = wait_for_completion_timeout(&ioc->transport_cmds.done, ++ 10*HZ); ++ ++ if (!(ioc->transport_cmds.status & MPT2_CMD_COMPLETE)) { ++ printk(MPT2SAS_ERR_FMT "%s: timeout\n", ++ ioc->name, __func__); ++ _debug_dump_mf(mpi_request, ++ sizeof(Mpi2SmpPassthroughRequest_t)/4); ++ if (!(ioc->transport_cmds.status & MPT2_CMD_RESET)) ++ issue_reset = 1; ++ goto issue_host_reset; ++ } ++ ++ dtransportprintk(ioc, printk(MPT2SAS_DEBUG_FMT "report_manufacture - " ++ "complete\n", ioc->name)); ++ ++ if (ioc->transport_cmds.status & MPT2_CMD_REPLY_VALID) { ++ u8 *tmp; ++ ++ mpi_reply = ioc->transport_cmds.reply; ++ ++ dtransportprintk(ioc, printk(MPT2SAS_DEBUG_FMT ++ "report_manufacture - reply data transfer size(%d)\n", ++ ioc->name, le16_to_cpu(mpi_reply->ResponseDataLength))); ++ ++ if (le16_to_cpu(mpi_reply->ResponseDataLength) != ++ sizeof(struct rep_manu_reply)) ++ goto out; ++ ++ manufacture_reply = data_out + sizeof(struct rep_manu_request); ++ strncpy(edev->vendor_id, manufacture_reply->vendor_id, ++ SAS_EXPANDER_VENDOR_ID_LEN); ++ strncpy(edev->product_id, manufacture_reply->product_id, ++ SAS_EXPANDER_PRODUCT_ID_LEN); ++ strncpy(edev->product_rev, manufacture_reply->product_rev, ++ SAS_EXPANDER_PRODUCT_REV_LEN); ++ edev->level = manufacture_reply->sas_format; ++ if (manufacture_reply->sas_format) { ++ strncpy(edev->component_vendor_id, ++ manufacture_reply->component_vendor_id, ++ SAS_EXPANDER_COMPONENT_VENDOR_ID_LEN); ++ tmp = (u8 *)&manufacture_reply->component_id; ++ edev->component_id = tmp[0] << 8 | tmp[1]; ++ edev->component_revision_id = ++ manufacture_reply->component_revision_id; ++ } ++ } else ++ dtransportprintk(ioc, printk(MPT2SAS_DEBUG_FMT ++ "report_manufacture - no reply\n", ioc->name)); ++ ++ issue_host_reset: ++ if (issue_reset) ++ mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, ++ FORCE_BIG_HAMMER); ++ out: ++ ioc->transport_cmds.status = MPT2_CMD_NOT_USED; ++ if (data_out) ++ pci_free_consistent(ioc->pdev, sz, data_out, data_out_dma); ++ ++ mutex_unlock(&ioc->transport_cmds.mutex); ++ return rc; ++} ++#endif ++ ++/** ++ * mpt2sas_transport_port_add - insert port to the list ++ * @ioc: per adapter object ++ * @handle: handle of attached device ++ * @parent_handle: parent handle(either hba or expander) ++ * Context: This function will acquire ioc->sas_node_lock. ++ * ++ * Adding new port object to the sas_node->sas_port_list. ++ * ++ * Returns mpt2sas_port. ++ */ ++struct _sas_port * ++mpt2sas_transport_port_add(struct MPT2SAS_ADAPTER *ioc, u16 handle, ++ u16 parent_handle) ++{ ++ struct _sas_phy *mpt2sas_phy, *next; ++ struct _sas_port *mpt2sas_port; ++ unsigned long flags; ++ struct _sas_node *sas_node; ++ struct sas_rphy *rphy; ++ int i; ++#if defined(MPT_WIDE_PORT_API) ++ struct sas_port *port; ++#endif ++ ++ if (!parent_handle) ++ return NULL; ++ ++ mpt2sas_port = kzalloc(sizeof(struct _sas_port), ++ GFP_KERNEL); ++ if (!mpt2sas_port) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return NULL; ++ } ++ ++ INIT_LIST_HEAD(&mpt2sas_port->port_list); ++ INIT_LIST_HEAD(&mpt2sas_port->phy_list); ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ sas_node = _transport_sas_node_find_by_handle(ioc, parent_handle); ++ spin_unlock_irqrestore(&ioc->sas_node_lock, flags); ++ ++ if (!sas_node) { ++ printk(MPT2SAS_ERR_FMT "%s: Could not find parent(0x%04x)!\n", ++ ioc->name, __func__, parent_handle); ++ goto out_fail; ++ } ++ ++ mpt2sas_port->handle = parent_handle; ++ mpt2sas_port->sas_address = sas_node->sas_address; ++ if ((_transport_set_identify(ioc, handle, ++ &mpt2sas_port->remote_identify))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out_fail; ++ } ++ ++ if (mpt2sas_port->remote_identify.device_type == SAS_PHY_UNUSED) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out_fail; ++ } ++ ++ for (i = 0; i < sas_node->num_phys; i++) { ++ if (sas_node->phy[i].remote_identify.sas_address != ++ mpt2sas_port->remote_identify.sas_address) ++ continue; ++ list_add_tail(&sas_node->phy[i].port_siblings, ++ &mpt2sas_port->phy_list); ++ mpt2sas_port->num_phys++; ++ } ++ ++ if (!mpt2sas_port->num_phys) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out_fail; ++ } ++ ++#if defined(MPT_WIDE_PORT_API) ++ port = sas_port_alloc_num(sas_node->parent_dev); ++ if ((sas_port_add(port))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ goto out_fail; ++ } ++ ++ list_for_each_entry(mpt2sas_phy, &mpt2sas_port->phy_list, ++ port_siblings) { ++ if ((ioc->logging_level & MPT_DEBUG_TRANSPORT)) ++ dev_printk(KERN_INFO, &port->dev, "add: handle(0x%04x)" ++ ", sas_addr(0x%016llx), phy(%d)\n", handle, ++ (unsigned long long) ++ mpt2sas_port->remote_identify.sas_address, ++ mpt2sas_phy->phy_id); ++ sas_port_add_phy(port, mpt2sas_phy->phy); ++ } ++ ++ mpt2sas_port->port = port; ++ if (mpt2sas_port->remote_identify.device_type == SAS_END_DEVICE) ++ rphy = sas_end_device_alloc(port); ++ else ++ rphy = sas_expander_alloc(port, ++ mpt2sas_port->remote_identify.device_type); ++#else ++ mpt2sas_phy = list_entry(mpt2sas_port->phy_list.next, struct _sas_phy, ++ port_siblings); ++ if (mpt2sas_port->remote_identify.device_type == SAS_END_DEVICE) ++ rphy = sas_end_device_alloc(mpt2sas_phy->phy); ++ else ++ rphy = sas_expander_alloc(mpt2sas_phy->phy, ++ mpt2sas_port->remote_identify.device_type); ++#endif ++ rphy->identify = mpt2sas_port->remote_identify; ++ if ((sas_rphy_add(rphy))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ } ++ if ((ioc->logging_level & MPT_DEBUG_TRANSPORT)) ++ dev_printk(KERN_INFO, &rphy->dev, "add: handle(0x%04x), " ++ "sas_addr(0x%016llx)\n", handle, ++ (unsigned long long) ++ mpt2sas_port->remote_identify.sas_address); ++ mpt2sas_port->rphy = rphy; ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ list_add_tail(&mpt2sas_port->port_list, &sas_node->sas_port_list); ++ spin_unlock_irqrestore(&ioc->sas_node_lock, flags); ++ ++#if defined(MPT_WIDE_PORT_API) ++ /* fill in report manufacture */ ++ if (mpt2sas_port->remote_identify.device_type == ++ MPI2_SAS_DEVICE_INFO_EDGE_EXPANDER || ++ mpt2sas_port->remote_identify.device_type == ++ MPI2_SAS_DEVICE_INFO_FANOUT_EXPANDER) ++ _transport_expander_report_manufacture(ioc, ++ mpt2sas_port->remote_identify.sas_address, ++ rphy_to_expander_device(rphy)); ++#endif ++ return mpt2sas_port; ++ ++ out_fail: ++ list_for_each_entry_safe(mpt2sas_phy, next, &mpt2sas_port->phy_list, ++ port_siblings) ++ list_del(&mpt2sas_phy->port_siblings); ++ kfree(mpt2sas_port); ++ return NULL; ++} ++ ++/** ++ * mpt2sas_transport_port_remove - remove port from the list ++ * @ioc: per adapter object ++ * @sas_address: sas address of attached device ++ * @parent_handle: handle to the upstream parent(either hba or expander) ++ * Context: This function will acquire ioc->sas_node_lock. ++ * ++ * Removing object and freeing associated memory from the ++ * ioc->sas_port_list. ++ * ++ * Return nothing. ++ */ ++void ++mpt2sas_transport_port_remove(struct MPT2SAS_ADAPTER *ioc, u64 sas_address, ++ u16 parent_handle) ++{ ++ int i; ++ unsigned long flags; ++ struct _sas_port *mpt2sas_port, *next; ++ struct _sas_node *sas_node; ++ u8 found = 0; ++#if defined(MPT_WIDE_PORT_API) ++ struct _sas_phy *mpt2sas_phy, *next_phy; ++#endif ++ ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ sas_node = _transport_sas_node_find_by_handle(ioc, parent_handle); ++ spin_unlock_irqrestore(&ioc->sas_node_lock, flags); ++ if (!sas_node) ++ return; ++ list_for_each_entry_safe(mpt2sas_port, next, &sas_node->sas_port_list, ++ port_list) { ++ if (mpt2sas_port->remote_identify.sas_address != sas_address) ++ continue; ++ found = 1; ++ list_del(&mpt2sas_port->port_list); ++ goto out; ++ } ++ out: ++ if (!found) ++ return; ++ ++ for (i = 0; i < sas_node->num_phys; i++) { ++ if (sas_node->phy[i].remote_identify.sas_address == sas_address) ++ memset(&sas_node->phy[i].remote_identify, 0 , ++ sizeof(struct sas_identify)); ++ } ++ ++#if defined(MPT_WIDE_PORT_API) ++ list_for_each_entry_safe(mpt2sas_phy, next_phy, ++ &mpt2sas_port->phy_list, port_siblings) { ++ if ((ioc->logging_level & MPT_DEBUG_TRANSPORT)) ++ dev_printk(KERN_INFO, &mpt2sas_port->port->dev, ++ "remove: parent_handle(0x%04x), " ++ "sas_addr(0x%016llx), phy(%d)\n", parent_handle, ++ (unsigned long long) ++ mpt2sas_port->remote_identify.sas_address, ++ mpt2sas_phy->phy_id); ++ sas_port_delete_phy(mpt2sas_port->port, mpt2sas_phy->phy); ++ list_del(&mpt2sas_phy->port_siblings); ++ } ++ sas_port_delete(mpt2sas_port->port); ++#else ++ if ((ioc->logging_level & MPT_DEBUG_TRANSPORT)) ++ dev_printk(KERN_INFO, &mpt2sas_port->rphy->dev, ++ "remove: parent_handle(0x%04x), sas_addr(0x%016llx)\n", ++ parent_handle, ++ (unsigned long long)sas_address); ++ sas_rphy_delete(mpt2sas_port->rphy); ++#endif ++ kfree(mpt2sas_port); ++} ++ ++/** ++ * mpt2sas_transport_add_host_phy - report sas_host phy to transport ++ * @ioc: per adapter object ++ * @mpt2sas_phy: mpt2sas per phy object ++ * @phy_pg0: sas phy page 0 ++ * @parent_dev: parent device class object ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_transport_add_host_phy(struct MPT2SAS_ADAPTER *ioc, struct _sas_phy ++ *mpt2sas_phy, Mpi2SasPhyPage0_t phy_pg0, struct device *parent_dev) ++{ ++ struct sas_phy *phy; ++ int phy_index = mpt2sas_phy->phy_id; ++ ++ ++ INIT_LIST_HEAD(&mpt2sas_phy->port_siblings); ++ phy = sas_phy_alloc(parent_dev, phy_index); ++ if (!phy) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return -1; ++ } ++ if ((_transport_set_identify(ioc, mpt2sas_phy->handle, ++ &mpt2sas_phy->identify))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return -1; ++ } ++ phy->identify = mpt2sas_phy->identify; ++ mpt2sas_phy->attached_handle = le16_to_cpu(phy_pg0.AttachedDevHandle); ++ if (mpt2sas_phy->attached_handle) ++ _transport_set_identify(ioc, mpt2sas_phy->attached_handle, ++ &mpt2sas_phy->remote_identify); ++ phy->identify.phy_identifier = mpt2sas_phy->phy_id; ++ phy->negotiated_linkrate = _transport_convert_phy_link_rate( ++ phy_pg0.NegotiatedLinkRate & MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL); ++ phy->minimum_linkrate_hw = _transport_convert_phy_link_rate( ++ phy_pg0.HwLinkRate & MPI2_SAS_HWRATE_MIN_RATE_MASK); ++ phy->maximum_linkrate_hw = _transport_convert_phy_link_rate( ++ phy_pg0.HwLinkRate >> 4); ++ phy->minimum_linkrate = _transport_convert_phy_link_rate( ++ phy_pg0.ProgrammedLinkRate & MPI2_SAS_PRATE_MIN_RATE_MASK); ++ phy->maximum_linkrate = _transport_convert_phy_link_rate( ++ phy_pg0.ProgrammedLinkRate >> 4); ++ ++#if !defined(MPT_WIDE_PORT_API_PLUS) ++ phy->local_attached = 1; ++#endif ++#if !defined(MPT_WIDE_PORT_API) ++ phy->port_identifier = phy_index; ++#endif ++ ++ if ((sas_phy_add(phy))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ sas_phy_free(phy); ++ return -1; ++ } ++ if ((ioc->logging_level & MPT_DEBUG_TRANSPORT)) ++ dev_printk(KERN_INFO, &phy->dev, ++ "add: handle(0x%04x), sas_addr(0x%016llx)\n" ++ "\tattached_handle(0x%04x), sas_addr(0x%016llx)\n", ++ mpt2sas_phy->handle, (unsigned long long) ++ mpt2sas_phy->identify.sas_address, ++ mpt2sas_phy->attached_handle, ++ (unsigned long long) ++ mpt2sas_phy->remote_identify.sas_address); ++ mpt2sas_phy->phy = phy; ++ return 0; ++} ++ ++ ++/** ++ * mpt2sas_transport_add_expander_phy - report expander phy to transport ++ * @ioc: per adapter object ++ * @mpt2sas_phy: mpt2sas per phy object ++ * @expander_pg1: expander page 1 ++ * @parent_dev: parent device class object ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++int ++mpt2sas_transport_add_expander_phy(struct MPT2SAS_ADAPTER *ioc, struct _sas_phy ++ *mpt2sas_phy, Mpi2ExpanderPage1_t expander_pg1, struct device *parent_dev) ++{ ++ struct sas_phy *phy; ++ int phy_index = mpt2sas_phy->phy_id; ++ ++ INIT_LIST_HEAD(&mpt2sas_phy->port_siblings); ++ phy = sas_phy_alloc(parent_dev, phy_index); ++ if (!phy) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return -1; ++ } ++ if ((_transport_set_identify(ioc, mpt2sas_phy->handle, ++ &mpt2sas_phy->identify))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return -1; ++ } ++ phy->identify = mpt2sas_phy->identify; ++ mpt2sas_phy->attached_handle = ++ le16_to_cpu(expander_pg1.AttachedDevHandle); ++ if (mpt2sas_phy->attached_handle) ++ _transport_set_identify(ioc, mpt2sas_phy->attached_handle, ++ &mpt2sas_phy->remote_identify); ++ phy->identify.phy_identifier = mpt2sas_phy->phy_id; ++ phy->negotiated_linkrate = _transport_convert_phy_link_rate( ++ expander_pg1.NegotiatedLinkRate & ++ MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL); ++ phy->minimum_linkrate_hw = _transport_convert_phy_link_rate( ++ expander_pg1.HwLinkRate & MPI2_SAS_HWRATE_MIN_RATE_MASK); ++ phy->maximum_linkrate_hw = _transport_convert_phy_link_rate( ++ expander_pg1.HwLinkRate >> 4); ++ phy->minimum_linkrate = _transport_convert_phy_link_rate( ++ expander_pg1.ProgrammedLinkRate & MPI2_SAS_PRATE_MIN_RATE_MASK); ++ phy->maximum_linkrate = _transport_convert_phy_link_rate( ++ expander_pg1.ProgrammedLinkRate >> 4); ++ ++#if !defined(MPT_WIDE_PORT_API) ++ phy->port_identifier = phy_index; ++#endif ++ ++ if ((sas_phy_add(phy))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ sas_phy_free(phy); ++ return -1; ++ } ++ if ((ioc->logging_level & MPT_DEBUG_TRANSPORT)) ++ dev_printk(KERN_INFO, &phy->dev, ++ "add: handle(0x%04x), sas_addr(0x%016llx)\n" ++ "\tattached_handle(0x%04x), sas_addr(0x%016llx)\n", ++ mpt2sas_phy->handle, (unsigned long long) ++ mpt2sas_phy->identify.sas_address, ++ mpt2sas_phy->attached_handle, ++ (unsigned long long) ++ mpt2sas_phy->remote_identify.sas_address); ++ mpt2sas_phy->phy = phy; ++ return 0; ++} ++ ++/** ++ * mpt2sas_transport_update_links - refreshing phy link changes ++ * @ioc: per adapter object ++ * @handle: handle to sas_host or expander ++ * @attached_handle: attached device handle ++ * @phy_numberv: phy number ++ * @link_rate: new link rate ++ * ++ * Returns nothing. ++ */ ++void ++mpt2sas_transport_update_links(struct MPT2SAS_ADAPTER *ioc, ++ u16 handle, u16 attached_handle, u8 phy_number, u8 link_rate) ++{ ++ unsigned long flags; ++ struct _sas_node *sas_node; ++ struct _sas_phy *mpt2sas_phy; ++ ++ if (ioc->shost_recovery) { ++ printk(MPT2SAS_INFO_FMT "%s: host reset in progress!\n", ++ __func__, ioc->name); ++ return; ++ } ++ ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ sas_node = _transport_sas_node_find_by_handle(ioc, handle); ++ spin_unlock_irqrestore(&ioc->sas_node_lock, flags); ++ if (!sas_node) ++ return; ++ ++ mpt2sas_phy = &sas_node->phy[phy_number]; ++ mpt2sas_phy->attached_handle = attached_handle; ++ if (attached_handle && (link_rate >= MPI2_SAS_NEG_LINK_RATE_1_5)) ++ _transport_set_identify(ioc, mpt2sas_phy->attached_handle, ++ &mpt2sas_phy->remote_identify); ++ else ++ memset(&mpt2sas_phy->remote_identify, 0 , sizeof(struct ++ sas_identify)); ++ ++ if (mpt2sas_phy->phy) ++ mpt2sas_phy->phy->negotiated_linkrate = ++ _transport_convert_phy_link_rate(link_rate); ++ ++ if ((ioc->logging_level & MPT_DEBUG_TRANSPORT)) ++ dev_printk(KERN_INFO, &mpt2sas_phy->phy->dev, ++ "refresh: handle(0x%04x), sas_addr(0x%016llx),\n" ++ "\tlink_rate(0x%02x), phy(%d)\n" ++ "\tattached_handle(0x%04x), sas_addr(0x%016llx)\n", ++ handle, (unsigned long long) ++ mpt2sas_phy->identify.sas_address, link_rate, ++ phy_number, attached_handle, ++ (unsigned long long) ++ mpt2sas_phy->remote_identify.sas_address); ++} ++ ++static inline void * ++phy_to_ioc(struct sas_phy *phy) ++{ ++ struct Scsi_Host *shost = dev_to_shost(phy->dev.parent); ++ return shost_private(shost); ++} ++ ++static inline void * ++rphy_to_ioc(struct sas_rphy *rphy) ++{ ++ struct Scsi_Host *shost = dev_to_shost(rphy->dev.parent->parent); ++ return shost_private(shost); ++} ++ ++/** ++ * _transport_get_linkerrors - ++ * @phy: The sas phy object ++ * ++ * Only support sas_host direct attached phys. ++ * Returns 0 for success, non-zero for failure. ++ * ++ */ ++static int ++_transport_get_linkerrors(struct sas_phy *phy) ++{ ++ struct MPT2SAS_ADAPTER *ioc = phy_to_ioc(phy); ++ struct _sas_phy *mpt2sas_phy; ++ Mpi2ConfigReply_t mpi_reply; ++ Mpi2SasPhyPage1_t phy_pg1; ++ int i; ++ ++ for (i = 0, mpt2sas_phy = NULL; i < ioc->sas_hba.num_phys && ++ !mpt2sas_phy; i++) { ++ if (ioc->sas_hba.phy[i].phy != phy) ++ continue; ++ mpt2sas_phy = &ioc->sas_hba.phy[i]; ++ } ++ ++ if (!mpt2sas_phy) /* this phy not on sas_host */ ++ return -EINVAL; ++ ++ if ((mpt2sas_config_get_phy_pg1(ioc, &mpi_reply, &phy_pg1, ++ mpt2sas_phy->phy_id))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return -ENXIO; ++ } ++ ++ if (mpi_reply.IOCStatus || mpi_reply.IOCLogInfo) ++ printk(MPT2SAS_INFO_FMT "phy(%d), ioc_status" ++ "(0x%04x), loginfo(0x%08x)\n", ioc->name, ++ mpt2sas_phy->phy_id, ++ le16_to_cpu(mpi_reply.IOCStatus), ++ le32_to_cpu(mpi_reply.IOCLogInfo)); ++ ++ phy->invalid_dword_count = le32_to_cpu(phy_pg1.InvalidDwordCount); ++ phy->running_disparity_error_count = ++ le32_to_cpu(phy_pg1.RunningDisparityErrorCount); ++ phy->loss_of_dword_sync_count = ++ le32_to_cpu(phy_pg1.LossDwordSynchCount); ++ phy->phy_reset_problem_count = ++ le32_to_cpu(phy_pg1.PhyResetProblemCount); ++ return 0; ++} ++ ++/** ++ * _transport_get_enclosure_identifier - ++ * @phy: The sas phy object ++ * ++ * Obtain the enclosure logical id for an expander. ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_transport_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier) ++{ ++ struct MPT2SAS_ADAPTER *ioc = rphy_to_ioc(rphy); ++ struct _sas_node *sas_expander; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ioc->sas_node_lock, flags); ++ sas_expander = mpt2sas_scsih_expander_find_by_sas_address(ioc, ++ rphy->identify.sas_address); ++ spin_unlock_irqrestore(&ioc->sas_node_lock, flags); ++ ++ if (!sas_expander) ++ return -ENXIO; ++ ++ *identifier = sas_expander->enclosure_logical_id; ++ return 0; ++} ++ ++/** ++ * _transport_get_bay_identifier - ++ * @phy: The sas phy object ++ * ++ * Returns the slot id for a device that resides inside an enclosure. ++ */ ++static int ++_transport_get_bay_identifier(struct sas_rphy *rphy) ++{ ++ struct MPT2SAS_ADAPTER *ioc = rphy_to_ioc(rphy); ++ struct _sas_device *sas_device; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ioc->sas_device_lock, flags); ++ sas_device = mpt2sas_scsih_sas_device_find_by_sas_address(ioc, ++ rphy->identify.sas_address); ++ spin_unlock_irqrestore(&ioc->sas_device_lock, flags); ++ ++ if (!sas_device) ++ return -ENXIO; ++ ++ return sas_device->slot; ++} ++ ++/** ++ * _transport_phy_reset - ++ * @phy: The sas phy object ++ * @hard_reset: ++ * ++ * Only support sas_host direct attached phys. ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++_transport_phy_reset(struct sas_phy *phy, int hard_reset) ++{ ++ struct MPT2SAS_ADAPTER *ioc = phy_to_ioc(phy); ++ struct _sas_phy *mpt2sas_phy; ++ Mpi2SasIoUnitControlReply_t mpi_reply; ++ Mpi2SasIoUnitControlRequest_t mpi_request; ++ int i; ++ ++ for (i = 0, mpt2sas_phy = NULL; i < ioc->sas_hba.num_phys && ++ !mpt2sas_phy; i++) { ++ if (ioc->sas_hba.phy[i].phy != phy) ++ continue; ++ mpt2sas_phy = &ioc->sas_hba.phy[i]; ++ } ++ ++ if (!mpt2sas_phy) /* this phy not on sas_host */ ++ return -EINVAL; ++ ++ memset(&mpi_request, 0, sizeof(Mpi2SasIoUnitControlReply_t)); ++ mpi_request.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL; ++ mpi_request.Operation = hard_reset ? ++ MPI2_SAS_OP_PHY_HARD_RESET : MPI2_SAS_OP_PHY_LINK_RESET; ++ mpi_request.PhyNum = mpt2sas_phy->phy_id; ++ ++ if ((mpt2sas_base_sas_iounit_control(ioc, &mpi_reply, &mpi_request))) { ++ printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return -ENXIO; ++ } ++ ++ if (mpi_reply.IOCStatus || mpi_reply.IOCLogInfo) ++ printk(MPT2SAS_INFO_FMT "phy(%d), ioc_status" ++ "(0x%04x), loginfo(0x%08x)\n", ioc->name, ++ mpt2sas_phy->phy_id, ++ le16_to_cpu(mpi_reply.IOCStatus), ++ le32_to_cpu(mpi_reply.IOCLogInfo)); ++ ++ return 0; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) ++/** ++ * _transport_smp_handler - transport portal for smp passthru ++ * @shost: shost object ++ * @rphy: sas transport rphy object ++ * @req: ++ * ++ * This used primarily for smp_utils. ++ * Example: ++ * smp_rep_general /sys/class/bsg/expander-5:0 ++ */ ++static int ++_transport_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy, ++ struct request *req) ++{ ++ struct MPT2SAS_ADAPTER *ioc = shost_private(shost); ++ Mpi2SmpPassthroughRequest_t *mpi_request; ++ Mpi2SmpPassthroughReply_t *mpi_reply; ++ int rc; ++ u16 smid; ++ u32 ioc_state; ++ unsigned long timeleft; ++ void *psge; ++ u32 sgl_flags; ++ u8 issue_reset = 0; ++ dma_addr_t dma_addr_in = 0; ++ dma_addr_t dma_addr_out = 0; ++ u16 wait_state_count; ++ struct request *rsp = req->next_rq; ++ ++ if (!rsp) { ++ printk(MPT2SAS_ERR_FMT "%s: the smp response space is " ++ "missing\n", ioc->name, __func__); ++ return -EINVAL; ++ } ++ ++ /* do we need to support multiple segments? */ ++ if (req->bio->bi_vcnt > 1 || rsp->bio->bi_vcnt > 1) { ++ printk(MPT2SAS_ERR_FMT "%s: multiple segments req %u %u, " ++ "rsp %u %u\n", ioc->name, __func__, req->bio->bi_vcnt, ++ req->data_len, rsp->bio->bi_vcnt, rsp->data_len); ++ return -EINVAL; ++ } ++ ++ if (ioc->shost_recovery) { ++ printk(MPT2SAS_INFO_FMT "%s: host reset in progress!\n", ++ __func__, ioc->name); ++ return -EFAULT; ++ } ++ ++ rc = mutex_lock_interruptible(&ioc->transport_cmds.mutex); ++ if (rc) ++ return rc; ++ ++ if (ioc->transport_cmds.status != MPT2_CMD_NOT_USED) { ++ printk(MPT2SAS_ERR_FMT "%s: transport_cmds in use\n", ioc->name, ++ __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ioc->transport_cmds.status = MPT2_CMD_PENDING; ++ ++ wait_state_count = 0; ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { ++ if (wait_state_count++ == 10) { ++ printk(MPT2SAS_ERR_FMT ++ "%s: failed due to ioc not operational\n", ++ ioc->name, __func__); ++ rc = -EFAULT; ++ goto out; ++ } ++ ssleep(1); ++ ioc_state = mpt2sas_base_get_iocstate(ioc, 1); ++ printk(MPT2SAS_INFO_FMT "%s: waiting for " ++ "operational state(count=%d)\n", ioc->name, ++ __func__, wait_state_count); ++ } ++ if (wait_state_count) ++ printk(MPT2SAS_INFO_FMT "%s: ioc is operational\n", ++ ioc->name, __func__); ++ ++ smid = mpt2sas_base_get_smid(ioc, ioc->transport_cb_idx); ++ if (!smid) { ++ printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n", ++ ioc->name, __func__); ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ rc = 0; ++ mpi_request = mpt2sas_base_get_msg_frame(ioc, smid); ++ ioc->transport_cmds.smid = smid; ++ ++ memset(mpi_request, 0, sizeof(Mpi2SmpPassthroughRequest_t)); ++ mpi_request->Function = MPI2_FUNCTION_SMP_PASSTHROUGH; ++ mpi_request->PhysicalPort = 0xFF; ++ *((u64 *)&mpi_request->SASAddress) = (rphy) ? ++ cpu_to_le64(rphy->identify.sas_address) : ++ cpu_to_le64(ioc->sas_hba.sas_address); ++ mpi_request->RequestDataLength = cpu_to_le16(req->data_len - 4); ++ psge = &mpi_request->SGL; ++ ++ /* WRITE sgel first */ ++ sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | ++ MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC); ++ sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; ++ dma_addr_out = pci_map_single(ioc->pdev, bio_data(req->bio), ++ req->data_len, PCI_DMA_BIDIRECTIONAL); ++ if (!dma_addr_out) { ++ mpt2sas_base_free_smid(ioc, le16_to_cpu(smid)); ++ goto unmap; ++ } ++ ++ ioc->base_add_sg_single(psge, sgl_flags | (req->data_len - 4), ++ dma_addr_out); ++ ++ /* incr sgel */ ++ psge += ioc->sge_size; ++ ++ /* READ sgel last */ ++ sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | ++ MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | ++ MPI2_SGE_FLAGS_END_OF_LIST); ++ sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; ++ dma_addr_in = pci_map_single(ioc->pdev, bio_data(rsp->bio), ++ rsp->data_len, PCI_DMA_BIDIRECTIONAL); ++ if (!dma_addr_in) { ++ mpt2sas_base_free_smid(ioc, le16_to_cpu(smid)); ++ goto unmap; ++ } ++ ++ ioc->base_add_sg_single(psge, sgl_flags | (rsp->data_len + 4), ++ dma_addr_in); ++ ++ dtransportprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s - " ++ "sending smp request\n", ioc->name, __func__)); ++ ++ mpt2sas_base_put_smid_default(ioc, smid, 0 /* VF_ID */); ++ timeleft = wait_for_completion_timeout(&ioc->transport_cmds.done, ++ 10*HZ); ++ ++ if (!(ioc->transport_cmds.status & MPT2_CMD_COMPLETE)) { ++ printk(MPT2SAS_ERR_FMT "%s : timeout\n", ++ __func__, ioc->name); ++ _debug_dump_mf(mpi_request, ++ sizeof(Mpi2SmpPassthroughRequest_t)/4); ++ if (!(ioc->transport_cmds.status & MPT2_CMD_RESET)) ++ issue_reset = 1; ++ goto issue_host_reset; ++ } ++ ++ dtransportprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s - " ++ "complete\n", ioc->name, __func__)); ++ ++ if (ioc->transport_cmds.status & MPT2_CMD_REPLY_VALID) { ++ ++ mpi_reply = ioc->transport_cmds.reply; ++ ++ dtransportprintk(ioc, printk(MPT2SAS_DEBUG_FMT ++ "%s - reply data transfer size(%d)\n", ++ ioc->name, __func__, ++ le16_to_cpu(mpi_reply->ResponseDataLength))); ++ ++ memcpy(req->sense, mpi_reply, sizeof(*mpi_reply)); ++ req->sense_len = sizeof(*mpi_reply); ++ req->data_len = 0; ++ rsp->data_len -= mpi_reply->ResponseDataLength; ++ ++ } else { ++ dtransportprintk(ioc, printk(MPT2SAS_DEBUG_FMT ++ "%s - no reply\n", ioc->name, __func__)); ++ rc = -ENXIO; ++ } ++ ++ issue_host_reset: ++ if (issue_reset) { ++ mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP, ++ FORCE_BIG_HAMMER); ++ rc = -ETIMEDOUT; ++ } ++ ++ unmap: ++ if (dma_addr_out) ++ pci_unmap_single(ioc->pdev, dma_addr_out, req->data_len, ++ PCI_DMA_BIDIRECTIONAL); ++ if (dma_addr_in) ++ pci_unmap_single(ioc->pdev, dma_addr_in, rsp->data_len, ++ PCI_DMA_BIDIRECTIONAL); ++ ++ out: ++ ioc->transport_cmds.status = MPT2_CMD_NOT_USED; ++ mutex_unlock(&ioc->transport_cmds.mutex); ++ return rc; ++} ++#endif ++ ++struct sas_function_template mpt2sas_transport_functions = { ++ .get_linkerrors = _transport_get_linkerrors, ++ .get_enclosure_identifier = _transport_get_enclosure_identifier, ++ .get_bay_identifier = _transport_get_bay_identifier, ++ .phy_reset = _transport_phy_reset, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) ++ .smp_handler = _transport_smp_handler, ++#endif ++}; ++ ++struct scsi_transport_template *mpt2sas_transport_template; diff --git a/master/mptlinux-4.20.00.01.patch b/master/mptlinux-4.20.00.01.patch new file mode 100644 index 0000000..722e9af --- /dev/null +++ b/master/mptlinux-4.20.00.01.patch @@ -0,0 +1,18891 @@ +MPT Fusion driver 4.00.07.00 from +http://scale.ad.xensource.com/confluence/download/attachments/1409154/DellDrivers.zip?version=1 +-> DellDrivers.zip/mptlinux_4.00.07.00_2.tgz -> mptlinux-4.00.07.00-src.tar + +diff -r 8807687e8e9c drivers/message/fusion/csmi/csmisas.c +--- a/drivers/message/fusion/csmi/csmisas.c Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/csmi/csmisas.c Tue Sep 01 16:11:22 2009 +0100 +@@ -43,13 +43,16 @@ + */ + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + +-#define MPT_CSMI_DESCRIPTION \ +- "LSI Corporation: Fusion MPT Driver "MPT_LINUX_VERSION_COMMON ++#define MPT_CSMI_DESCRIPTION "LSI Corporation: Fusion MPT Driver "MPT_LINUX_VERSION_COMMON + #define csmisas_is_this_sas_cntr(ioc) (ioc->bus_type == SAS) ? 1 : 0 + +- +-static int csmisas_do_raid(MPT_ADAPTER *ioc, u8 action, u8 PhysDiskNum, +- u8 VolumeBus, u8 VolumeId, pMpiRaidActionReply_t reply); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) ++#define __user ++#include ++#endif ++ ++static int csmisas_do_raid(MPT_ADAPTER *ioc, u8 action, u8 PhysDiskNum, u8 VolumeBus, ++ u8 VolumeId, pMpiRaidActionReply_t reply); + static u8 map_sas_status_to_csmi(u8 mpi_sas_status); + + /** +@@ -63,7 +66,7 @@ + { + int i; + u64 rc; +- u8 *inWord = (u8 *)&data64, *outWord = (u8 *)&rc; ++ u8 *inWord = (u8*)&data64, *outWord = (u8*)&rc; + + for (i = 0 ; i < 8 ; i++) + outWord[i] = inWord[7-i]; +@@ -95,7 +98,7 @@ + * + **/ + static inline int +-csmisas_is_end_device(struct mptsas_devinfo *attached) ++csmisas_is_end_device(struct mptsas_devinfo * attached) + { + if ((attached->sas_address) && + (attached->device_info & +@@ -127,8 +130,7 @@ + goto out; + for (i = 0; i < ioc->raid_data.pIocPg3->NumPhysDisks; i++) { + if ((id == ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskID) && +- (channel == +- ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskBus)) { ++ (channel == ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskBus)) { + rc = 1; + goto out; + } +@@ -140,14 +142,14 @@ + if (list_empty(&ioc->raid_data.inactive_list)) + goto out; + +- mutex_lock(&ioc->raid_data.inactive_list_mutex); ++ down(&ioc->raid_data.inactive_list_mutex); + list_for_each_entry(component_info, &ioc->raid_data.inactive_list, + list) { + if ((component_info->d.PhysDiskID == id) && + (component_info->d.PhysDiskBus == channel)) + rc = 1; + } +- mutex_unlock(&ioc->raid_data.inactive_list_mutex); ++ up(&ioc->raid_data.inactive_list_mutex); + + out: + return rc; +@@ -159,8 +161,7 @@ + * Obtains the phys disk num for given H:C:T nexus + * + * input (channel/id) +- * output (phys disk number - used by SCSI_IO_PASSTHRU to access hidden +- * component) ++ * output (phys disk number - used by SCSI_IO_PASSTHRU to access hidden component) + * + * returns - signed return means failure + **/ +@@ -175,8 +176,7 @@ + goto out; + for (i = 0; i < ioc->raid_data.pIocPg3->NumPhysDisks; i++) { + if ((id == ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskID) && +- (channel == +- ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskBus)) { ++ (channel == ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskBus)) { + rc = ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskNum; + goto out; + } +@@ -188,14 +188,14 @@ + if (list_empty(&ioc->raid_data.inactive_list)) + goto out; + +- mutex_lock(&ioc->raid_data.inactive_list_mutex); ++ down(&ioc->raid_data.inactive_list_mutex); + list_for_each_entry(component_info, &ioc->raid_data.inactive_list, + list) { + if ((component_info->d.PhysDiskID == id) && + (component_info->d.PhysDiskBus == channel)) + rc = component_info->d.PhysDiskNum; + } +- mutex_unlock(&ioc->raid_data.inactive_list_mutex); ++ up(&ioc->raid_data.inactive_list_mutex); + + out: + return rc; +@@ -218,7 +218,7 @@ + + sas_info = NULL; + +- mutex_lock(&ioc->sas_device_info_mutex); ++ down(&ioc->sas_device_info_mutex); + list_for_each_entry(p, &ioc->sas_device_info_list, list) { + if (p->os.channel == channel && p->os.id == id) { + sas_info = p; +@@ -227,7 +227,7 @@ + } + + out: +- mutex_unlock(&ioc->sas_device_info_mutex); ++ up(&ioc->sas_device_info_mutex); + return sas_info; + } + +@@ -248,7 +248,7 @@ + + sas_info = NULL; + +- mutex_lock(&ioc->sas_device_info_mutex); ++ down(&ioc->sas_device_info_mutex); + list_for_each_entry(p, &ioc->sas_device_info_list, list) { + if (p->fw.channel == channel && p->fw.id == id) { + sas_info = p; +@@ -257,7 +257,7 @@ + } + + out: +- mutex_unlock(&ioc->sas_device_info_mutex); ++ up(&ioc->sas_device_info_mutex); + return sas_info; + } + +@@ -279,7 +279,7 @@ + + sas_info = NULL; + +- mutex_lock(&ioc->sas_device_info_mutex); ++ down(&ioc->sas_device_info_mutex); + list_for_each_entry(p, &ioc->sas_device_info_list, list) { + if (p->sas_address == sas_address) { + sas_info = p; +@@ -288,7 +288,7 @@ + } + + out: +- mutex_unlock(&ioc->sas_device_info_mutex); ++ up(&ioc->sas_device_info_mutex); + return sas_info; + } + +@@ -305,8 +305,7 @@ + * non-zero, failure + **/ + static int +-csmisas_send_command_wait(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf, +- unsigned long timeout) ++csmisas_send_command_wait(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf, unsigned long timeout) + { + int rc; + unsigned long timeleft; +@@ -314,16 +313,41 @@ + timeout = max_t(unsigned long, MPT_IOCTL_DEFAULT_TIMEOUT, timeout); + rc = 0; + timeleft = 0; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) ++ ++ INITIALIZE_IOCTL_STATUS(ioc->ioctl_cmds.status) ++ ioc->ioctl_cmds.wait_done = 0; ++ ioc->ioctl_cmds.timer.expires = jiffies + (MPT_JIFFY * timeout); ++ ioc->ioctl_cmds.status |= MPT_MGMT_STATUS_TIMER_ACTIVE; ++ ADD_TIMER(&ioc->ioctl_cmds.timer); ++ mpt_put_msg_frame(mptctl_id, ioc, mf); ++ WAIT_EVENT(mptctl_wait, ioc->ioctl_cmds.wait_done); ++ ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) ++ ++ INITIALIZE_IOCTL_STATUS(ioc->ioctl_cmds.status) ++ ioc->ioctl_cmds.wait_done = 0; ++ mpt_put_msg_frame(mptctl_id, ioc, mf); ++ ++ if ((wait_event_timeout(mptctl_wait, ++ ioc->ioctl_cmds.wait_done == 1, HZ * timeout) <=0) && ++ ioc->ioctl_cmds.wait_done != 1 ) { ++ mptctl_timeout_expired(ioc,mf); ++ mpt_free_msg_frame(ioc, mf); ++ rc = -1; ++ } ++ ++#else + + SET_MGMT_MSG_CONTEXT(ioc->ioctl_cmds.msg_context, + mf->u.hdr.MsgContext); + INITIALIZE_MGMT_STATUS(ioc->ioctl_cmds.status) + mpt_put_msg_frame(mptctl_id, ioc, mf); +- timeleft = wait_for_completion_timeout(&ioc->ioctl_cmds.done, +- timeout*HZ); ++ timeleft = wait_for_completion_timeout(&ioc->ioctl_cmds.done, timeout*HZ); + if (!(ioc->ioctl_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { + rc = -1; +- printk(KERN_WARNING "%s: failed\n", __func__); ++ printk("%s: failed\n", __FUNCTION__); + if (ioc->ioctl_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) { + mpt_free_msg_frame(ioc, mf); + CLEAR_MGMT_STATUS(ioc->ioctl_cmds.status) +@@ -333,6 +357,7 @@ + mptctl_timeout_expired(ioc, mf); + } + SET_MGMT_MSG_CONTEXT(ioc->ioctl_cmds.msg_context, 0); ++#endif + return rc; + } + +@@ -350,8 +375,7 @@ + * non-zero, failure + **/ + static int +-csmisas_send_handshake_wait(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf, +- unsigned long timeout) ++csmisas_send_handshake_wait(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf, unsigned long timeout) + { + int rc; + unsigned long timeleft; +@@ -360,13 +384,42 @@ + rc = 0; + timeleft = 0; + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) ++ ++ INITIALIZE_IOCTL_STATUS(ioc->taskmgmt_cmds.status) ++ ioc->taskmgmt_cmds.timer.expires = jiffies + (MPT_JIFFY*timeout); ++ ioc->taskmgmt_cmds.status |= MPT_MGMT_STATUS_TIMER_ACTIVE; ++ ioc->taskmgmt_cmds.wait_done = 0; ++ ADD_TIMER(&ioc->taskmgmt_cmds.timer); ++ rc = mpt_send_special_message(mptctl_taskmgmt_id, ioc, ++ sizeof(SCSITaskMgmt_t), (u32*)mf, timeout, CAN_SLEEP); ++ if (rc != 0) ++ return rc; ++ WAIT_EVENT(mptctl_taskmgmt_wait, ioc->taskmgmt_cmds.wait_done); ++ ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) ++ ++ INITIALIZE_IOCTL_STATUS(ioc->taskmgmt_cmds.status) ++ ioc->taskmgmt_cmds.wait_done = 0; ++ rc = mpt_send_special_message(mptctl_taskmgmt_id, ioc, ++ sizeof(SCSITaskMgmt_t), (u32*)mf, timeout, CAN_SLEEP); ++ if (rc != 0) ++ return rc; ++ if ((wait_event_timeout(mptctl_taskmgmt_wait, ++ ioc->taskmgmt_cmds.wait_done == 1, HZ * timeout) <=0) && ++ ioc->taskmgmt_cmds.wait_done != 1 ) { ++ mptctl_timeout_expired(ioc, mf); ++ mpt_free_msg_frame(ioc, mf); ++ rc = -1; ++ } ++ ++#else + INITIALIZE_MGMT_STATUS(ioc->taskmgmt_cmds.status) + mpt_put_msg_frame_hi_pri(mptctl_taskmgmt_id, ioc, mf); +- timeleft = wait_for_completion_timeout(&ioc->taskmgmt_cmds.done, +- timeout*HZ); ++ timeleft = wait_for_completion_timeout(&ioc->taskmgmt_cmds.done, timeout*HZ); + if (!(ioc->ioctl_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { + rc = -1; +- printk(KERN_WARNING "%s: failed\n", __func__); ++ printk("%s: failed\n", __FUNCTION__); + mpt_clear_taskmgmt_in_progress_flag(ioc); + if (ioc->ioctl_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) { + mpt_free_msg_frame(ioc, mf); +@@ -376,6 +429,7 @@ + if (!timeleft) + mptctl_timeout_expired(ioc, mf); + } ++#endif + return rc; + } + +@@ -473,8 +527,7 @@ + cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; + cfg.timeout = MPT_IOCTL_DEFAULT_TIMEOUT; + +- rc = mpt_config(ioc, &cfg); +- if (rc != 0) ++ if ((rc = mpt_config(ioc, &cfg)) != 0) + goto get_ioc_pg5; + + if (hdr.PageLength == 0) { +@@ -494,8 +547,7 @@ + cfg.physAddr = dma_handle; + cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; + +- rc = mpt_config(ioc, &cfg); +- if (rc != 0) ++ if ((rc = mpt_config(ioc, &cfg)) != 0) + goto get_ioc_pg5; + + memcpy(iocPage5, buffer, data_size); +@@ -513,8 +565,7 @@ + * csmisas_sas_device_pg0 - sas device page 0 + * @ioc: Pointer to MPT_ADAPTER structure + * @mptsas_devinfo: structure found in mptsas.h +- * @form, @form_specific - defines the Page Address field in +- * the config page ++ * @form, @form_specific - defines the Page Address field in the config page + * (pls refer to chapter 5.1 in the mpi spec) + * + * Return: 0 for success +@@ -551,8 +602,7 @@ + cfg.timeout = 10; + + memset(device_info, 0, sizeof(struct mptsas_devinfo)); +- rc = mpt_config(ioc, &cfg); +- if (rc != 0) ++ if ((rc = mpt_config(ioc, &cfg)) != 0) + goto out; + + if (!hdr.ExtPageLength) { +@@ -570,8 +620,7 @@ + cfg.physAddr = dma_handle; + cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; + +- rc = mpt_config(ioc, &cfg); +- if (rc != 0) ++ if ((rc = mpt_config(ioc, &cfg)) != 0) + goto out_free_consistent; + + device_info->handle = le16_to_cpu(buffer->DevHandle); +@@ -615,31 +664,31 @@ + if (copy_from_user(&karg, uarg, sizeof(CSMI_SAS_DRIVER_INFO_BUFFER))) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to read in csmi_sas_get_driver_info_buffer struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + /* Fill in the data and return the structure to the calling + * program + */ +- memcpy(karg.Information.szName, MPT_MISCDEV_BASENAME, ++ memcpy( karg.Information.szName, MPT_MISCDEV_BASENAME, + sizeof(MPT_MISCDEV_BASENAME)); +- memcpy(karg.Information.szDescription, MPT_CSMI_DESCRIPTION, ++ memcpy( karg.Information.szDescription, MPT_CSMI_DESCRIPTION, + sizeof(MPT_CSMI_DESCRIPTION)); + + karg.Information.usMajorRevision = MPT_LINUX_MAJOR_VERSION; +@@ -658,11 +707,11 @@ + sizeof(CSMI_SAS_DRIVER_INFO_BUFFER))) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to write out csmi_sas_get_driver_info_buffer @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + } + +@@ -687,28 +736,28 @@ + if (copy_from_user(&karg, uarg, sizeof(CSMI_SAS_CNTLR_CONFIG_BUFFER))) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to read in csmi_sas_get_cntlr_config_buffer struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_INVALID_PARAMETER; + return -ENODEV; + } + + if (!csmisas_is_this_sas_cntr(ioc)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + /* Clear the struct before filling in data. */ +- memset(&karg.Configuration, 0, sizeof(CSMI_SAS_CNTLR_CONFIG)); ++ memset( &karg.Configuration, 0, sizeof(CSMI_SAS_CNTLR_CONFIG)); + + /* Fill in the data and return the structure to the calling + * program +@@ -737,7 +786,7 @@ + karg.Configuration.BusAddress.PciAddress.bFunctionNumber = + PCI_FUNC(ioc->pcidev->devfn); + karg.Configuration.BusAddress.PciAddress.bReserved = 0; +- memcpy(&karg.Configuration.szSerialNumber, ioc->board_tracer, 16); ++ memcpy( &karg.Configuration.szSerialNumber, ioc->board_tracer, 16 ); + karg.Configuration.usMajorRevision = ioc->facts.FWVersion.Struct.Major; + karg.Configuration.usMinorRevision = ioc->facts.FWVersion.Struct.Minor; + karg.Configuration.usBuildRevision = ioc->facts.FWVersion.Struct.Unit; +@@ -770,11 +819,11 @@ + sizeof(CSMI_SAS_DRIVER_INFO_BUFFER))) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to write out csmi_sas_get_driver_info_buffer @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + } + +@@ -799,24 +848,24 @@ + if (copy_from_user(&karg, uarg, sizeof(CSMI_SAS_CNTLR_STATUS_BUFFER))) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to read in csmi_sas_get_cntlr_status_buffer struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + /* Fill in the data and return the structure to the calling + * program +@@ -853,11 +902,11 @@ + sizeof(CSMI_SAS_CNTLR_STATUS_BUFFER))) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to write out csmi_sas_get_cntlr_status @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + } + +@@ -891,19 +940,19 @@ + struct mptsas_devinfo device_info; + int memory_pages; + +- sasIoUnitPg0 = NULL; +- sasPhyPg0 = NULL; +- sasIoUnitPg0_data_sz = 0; +- sasPhyPg0_data_sz = 0; ++ sasIoUnitPg0=NULL; ++ sasPhyPg0=NULL; ++ sasIoUnitPg0_data_sz=0; ++ sasPhyPg0_data_sz=0; + + memory_pages = get_order(sizeof(CSMI_SAS_PHY_INFO_BUFFER)); + karg = (CSMI_SAS_PHY_INFO_BUFFER *)__get_free_pages( + GFP_KERNEL, memory_pages); +- if (!karg) { ++ if (!karg){ + printk(KERN_ERR "%s@%d::%s() - " + "Unable to malloc CSMI_SAS_PHY_INFO_BUFFER " + "malloc_data_sz=%d memory_pages=%d\n", +- __FILE__, __LINE__, __func__, ++ __FILE__, __LINE__, __FUNCTION__, + (int)sizeof(CSMI_SAS_PHY_INFO_BUFFER), memory_pages); + return -ENOMEM; + } +@@ -913,7 +962,7 @@ + if (copy_from_user(karg, uarg, sizeof(CSMI_SAS_PHY_INFO_BUFFER))) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to read in csmisas_get_phy_info_buffer struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + free_pages((unsigned long)karg, memory_pages); + return -EFAULT; + } +@@ -921,19 +970,19 @@ + if (((iocnum = mpt_verify_adapter(karg->IoctlHeader.IOControllerNumber, + &ioc)) < 0) || (ioc == NULL)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)karg, memory_pages); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)karg, memory_pages); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)karg, memory_pages); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)karg, memory_pages); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + /* Fill in the data and return the structure to the calling + * program +@@ -962,7 +1011,7 @@ + */ + dcsmisasprintk(ioc, printk(KERN_ERR + ": FAILED: MPI_SASIOUNITPAGE0_PAGEVERSION: HEADER\n")); +- dcsmisasprintk(ioc, printk(": rc=%x\n", rc)); ++ dcsmisasprintk(ioc, printk(": rc=%x\n",rc)); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto sas_get_phy_info_exit; + } +@@ -971,8 +1020,7 @@ + /* Don't check if this failed. Already in a + * failure case. + */ +- dcsmisasprintk(ioc, printk(KERN_ERR +- ": hdr.ExtPageLength == 0\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": hdr.ExtPageLength == 0\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto sas_get_phy_info_exit; + } +@@ -984,8 +1032,7 @@ + sasIoUnitPg0_data_sz, &sasIoUnitPg0_dma); + + if (!sasIoUnitPg0) { +- dcsmisasprintk(ioc, printk(KERN_ERR +- ": pci_alloc_consistent: FAILED\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto sas_get_phy_info_exit; + } +@@ -1001,7 +1048,7 @@ + */ + dcsmisasprintk(ioc, printk(KERN_ERR + ": FAILED: MPI_SASIOUNITPAGE0_PAGEVERSION: PAGE\n")); +- dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n", rc)); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n",rc)); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto sas_get_phy_info_exit; + } +@@ -1011,30 +1058,27 @@ + + /* Fill in information for each phy. */ + for (ii = 0; ii < karg->Information.bNumberOfPhys; ii++) { +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "---- IO UNIT PAGE 0 ------------\n")); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "Handle=0x%X\n", ++ ++/* EDM : dump IO Unit Page 0 data*/ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "---- IO UNIT PAGE 0 ------------\n")); ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "Handle=0x%X\n", + le16_to_cpu(sasIoUnitPg0->PhyData[ii].AttachedDeviceHandle))); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "Controller Handle=0x%X\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "Controller Handle=0x%X\n", + le16_to_cpu(sasIoUnitPg0->PhyData[ii].ControllerDevHandle))); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "Port=0x%X\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "Port=0x%X\n", + sasIoUnitPg0->PhyData[ii].Port)); + dcsmisasprintk(ioc, printk(KERN_DEBUG "Port Flags=0x%X\n", + sasIoUnitPg0->PhyData[ii].PortFlags)); + dcsmisasprintk(ioc, printk(KERN_DEBUG "PHY Flags=0x%X\n", + sasIoUnitPg0->PhyData[ii].PhyFlags)); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "Negotiated Link Rate=0x%X\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "Negotiated Link Rate=0x%X\n", + sasIoUnitPg0->PhyData[ii].NegotiatedLinkRate)); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "Controller PHY Device Info=0x%X\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "Controller PHY Device Info=0x%X\n", + le32_to_cpu(sasIoUnitPg0->PhyData[ii].ControllerPhyDeviceInfo))); + dcsmisasprintk(ioc, printk(KERN_DEBUG "DiscoveryStatus=0x%X\n", + le32_to_cpu(sasIoUnitPg0->PhyData[ii].DiscoveryStatus))); + dcsmisasprintk(ioc, printk(KERN_DEBUG "\n")); ++/* EDM : debug data */ + + /* PHY stuff. */ + karg->Information.Phy[ii].bPortIdentifier = +@@ -1103,14 +1147,13 @@ + if ((rc = mpt_config(ioc, &cfg)) != 0) { + dcsmisasprintk(ioc, printk(KERN_ERR + ": FAILED: MPI_SASPHY0_PAGEVERSION: HEADER\n")); +- dcsmisasprintk(ioc, printk(": rc=%x\n", rc)); ++ dcsmisasprintk(ioc, printk(": rc=%x\n",rc)); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto sas_get_phy_info_exit; + } + + if (hdr.ExtPageLength == 0) { +- dcsmisasprintk(ioc, printk(KERN_ERR +- ": pci_alloc_consistent: FAILED\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto sas_get_phy_info_exit; + } +@@ -1121,9 +1164,8 @@ + sasPhyPg0 = (SasPhyPage0_t *) pci_alloc_consistent( + ioc->pcidev, sasPhyPg0_data_sz, &sasPhyPg0_dma); + +- if (!sasPhyPg0) { +- dcsmisasprintk(ioc, printk(KERN_ERR +- ": pci_alloc_consistent: FAILED\n")); ++ if (! sasPhyPg0) { ++ dcsmisasprintk(ioc, printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto sas_get_phy_info_exit; + } +@@ -1135,37 +1177,34 @@ + if ((rc = mpt_config(ioc, &cfg)) != 0) { + dcsmisasprintk(ioc, printk(KERN_ERR + ": FAILED: MPI_SASPHY0_PAGEVERSION: PAGE\n")); +- dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n", rc)); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n",rc)); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + pci_free_consistent(ioc->pcidev, sasPhyPg0_data_sz, + (u8 *) sasPhyPg0, sasPhyPg0_dma); + goto sas_get_phy_info_exit; + } + ++/* EDM : dump PHY Page 0 data*/ + memcpy(&sas_address, &sasPhyPg0->SASAddress, sizeof(u64)); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "---- SAS PHY PAGE 0 ------------\n")); ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "---- SAS PHY PAGE 0 ------------\n")); + dcsmisasprintk(ioc, printk(KERN_DEBUG "Handle=0x%X\n", + le16_to_cpu(sasPhyPg0->AttachedDevHandle))); + dcsmisasprintk(ioc, printk(KERN_DEBUG "SAS Address=0x%llX\n", + (unsigned long long)sas_address)); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "Attached PHY Identifier=0x%X\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "Attached PHY Identifier=0x%X\n", + sasPhyPg0->AttachedPhyIdentifier)); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "Attached Device Info=0x%X\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "Attached Device Info=0x%X\n", + le32_to_cpu(sasPhyPg0->AttachedDeviceInfo))); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "Programmed Link Rate=0x%X\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "Programmed Link Rate=0x%X\n", + sasPhyPg0->ProgrammedLinkRate)); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "Hardware Link Rate=0x%X\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "Hardware Link Rate=0x%X\n", + sasPhyPg0->HwLinkRate)); + dcsmisasprintk(ioc, printk(KERN_DEBUG "Change Count=0x%X\n", + sasPhyPg0->ChangeCount)); + dcsmisasprintk(ioc, printk(KERN_DEBUG "PHY Info=0x%X\n", + le32_to_cpu(sasPhyPg0->PhyInfo))); + dcsmisasprintk(ioc, printk(KERN_DEBUG "\n")); ++/* EDM : debug data */ + + /* save the data */ + +@@ -1245,9 +1284,8 @@ + } + + karg->Information.Phy[ii].bPhyChangeCount = sasPhyPg0->ChangeCount; +- if (sasPhyPg0->PhyInfo & MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY) +- karg->Information.Phy[ii].bPhyFeatures +- = CSMI_SAS_PHY_VIRTUAL_SMP; ++ if( sasPhyPg0->PhyInfo & MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY ) ++ karg->Information.Phy[ii].bPhyFeatures = CSMI_SAS_PHY_VIRTUAL_SMP; + + /* Fill in Attached Device + * Initiator Port Protocol. +@@ -1257,17 +1295,17 @@ + protocol = le32_to_cpu(sasPhyPg0->AttachedDeviceInfo) & 0x78; + karg->Information.Phy[ii].Attached.bInitiatorPortProtocol = 0; + if (protocol & MPI_SAS_DEVICE_INFO_SSP_INITIATOR) +- karg->Information.Phy[ii].Attached.bInitiatorPortProtocol +- = CSMI_SAS_PROTOCOL_SSP; ++ karg->Information.Phy[ii].Attached.bInitiatorPortProtocol = ++ CSMI_SAS_PROTOCOL_SSP; + if (protocol & MPI_SAS_DEVICE_INFO_STP_INITIATOR) +- karg->Information.Phy[ii].Attached.bInitiatorPortProtocol +- |= CSMI_SAS_PROTOCOL_STP; ++ karg->Information.Phy[ii].Attached.bInitiatorPortProtocol |= ++ CSMI_SAS_PROTOCOL_STP; + if (protocol & MPI_SAS_DEVICE_INFO_SMP_INITIATOR) +- karg->Information.Phy[ii].Attached.bInitiatorPortProtocol +- |= CSMI_SAS_PROTOCOL_SMP; ++ karg->Information.Phy[ii].Attached.bInitiatorPortProtocol |= ++ CSMI_SAS_PROTOCOL_SMP; + if (protocol & MPI_SAS_DEVICE_INFO_SATA_HOST) +- karg->Information.Phy[ii].Attached.bInitiatorPortProtocol +- |= CSMI_SAS_PROTOCOL_SATA; ++ karg->Information.Phy[ii].Attached.bInitiatorPortProtocol |= ++ CSMI_SAS_PROTOCOL_SATA; + + /* Fill in Phy Target Port + * Protocol. Bits 10:7 +@@ -1276,17 +1314,17 @@ + protocol = le32_to_cpu(sasPhyPg0->AttachedDeviceInfo) & 0x780; + karg->Information.Phy[ii].Attached.bTargetPortProtocol = 0; + if (protocol & MPI_SAS_DEVICE_INFO_SSP_TARGET) +- karg->Information.Phy[ii].Attached.bTargetPortProtocol +- |= CSMI_SAS_PROTOCOL_SSP; ++ karg->Information.Phy[ii].Attached.bTargetPortProtocol |= ++ CSMI_SAS_PROTOCOL_SSP; + if (protocol & MPI_SAS_DEVICE_INFO_STP_TARGET) +- karg->Information.Phy[ii].Attached.bTargetPortProtocol +- |= CSMI_SAS_PROTOCOL_STP; ++ karg->Information.Phy[ii].Attached.bTargetPortProtocol |= ++ CSMI_SAS_PROTOCOL_STP; + if (protocol & MPI_SAS_DEVICE_INFO_SMP_TARGET) +- karg->Information.Phy[ii].Attached.bTargetPortProtocol +- |= CSMI_SAS_PROTOCOL_SMP; ++ karg->Information.Phy[ii].Attached.bTargetPortProtocol |= ++ CSMI_SAS_PROTOCOL_SMP; + if (protocol & MPI_SAS_DEVICE_INFO_SATA_DEVICE) +- karg->Information.Phy[ii].Attached.bTargetPortProtocol +- |= CSMI_SAS_PROTOCOL_SATA; ++ karg->Information.Phy[ii].Attached.bTargetPortProtocol |= ++ CSMI_SAS_PROTOCOL_SATA; + + + /* Fill in Attached device type */ +@@ -1315,8 +1353,7 @@ + } + + /* Identify Info. */ +- switch (le32_to_cpu +- (sasIoUnitPg0->PhyData[ii].ControllerPhyDeviceInfo) & ++ switch (le32_to_cpu(sasIoUnitPg0->PhyData[ii].ControllerPhyDeviceInfo) & + MPI_SAS_DEVICE_INFO_MASK_DEVICE_TYPE) { + + case MPI_SAS_DEVICE_INFO_NO_DEVICE: +@@ -1346,18 +1383,18 @@ + protocol = le32_to_cpu( + sasIoUnitPg0->PhyData[ii].ControllerPhyDeviceInfo) & 0x78; + karg->Information.Phy[ii].Identify.bInitiatorPortProtocol = 0; +- if (protocol & MPI_SAS_DEVICE_INFO_SSP_INITIATOR) +- karg->Information.Phy[ii].Identify.bInitiatorPortProtocol +- |= CSMI_SAS_PROTOCOL_SSP; +- if (protocol & MPI_SAS_DEVICE_INFO_STP_INITIATOR) +- karg->Information.Phy[ii].Identify.bInitiatorPortProtocol +- |= CSMI_SAS_PROTOCOL_STP; +- if (protocol & MPI_SAS_DEVICE_INFO_SMP_INITIATOR) +- karg->Information.Phy[ii].Identify.bInitiatorPortProtocol +- |= CSMI_SAS_PROTOCOL_SMP; +- if (protocol & MPI_SAS_DEVICE_INFO_SATA_HOST) +- karg->Information.Phy[ii].Identify.bInitiatorPortProtocol +- |= CSMI_SAS_PROTOCOL_SATA; ++ if( protocol & MPI_SAS_DEVICE_INFO_SSP_INITIATOR ) ++ karg->Information.Phy[ii].Identify.bInitiatorPortProtocol |= ++ CSMI_SAS_PROTOCOL_SSP; ++ if( protocol & MPI_SAS_DEVICE_INFO_STP_INITIATOR ) ++ karg->Information.Phy[ii].Identify.bInitiatorPortProtocol |= ++ CSMI_SAS_PROTOCOL_STP; ++ if( protocol & MPI_SAS_DEVICE_INFO_SMP_INITIATOR ) ++ karg->Information.Phy[ii].Identify.bInitiatorPortProtocol |= ++ CSMI_SAS_PROTOCOL_SMP; ++ if( protocol & MPI_SAS_DEVICE_INFO_SATA_HOST ) ++ karg->Information.Phy[ii].Identify.bInitiatorPortProtocol |= ++ CSMI_SAS_PROTOCOL_SATA; + + /* Fill in Phy Target Port Protocol. Bits 10:7 + * More than one bit can be set, fall through cases. +@@ -1365,18 +1402,18 @@ + protocol = le32_to_cpu( + sasIoUnitPg0->PhyData[ii].ControllerPhyDeviceInfo) & 0x780; + karg->Information.Phy[ii].Identify.bTargetPortProtocol = 0; +- if (protocol & MPI_SAS_DEVICE_INFO_SSP_TARGET) +- karg->Information.Phy[ii].Identify.bTargetPortProtocol +- |= CSMI_SAS_PROTOCOL_SSP; +- if (protocol & MPI_SAS_DEVICE_INFO_STP_TARGET) +- karg->Information.Phy[ii].Identify.bTargetPortProtocol +- |= CSMI_SAS_PROTOCOL_STP; +- if (protocol & MPI_SAS_DEVICE_INFO_SMP_TARGET) +- karg->Information.Phy[ii].Identify.bTargetPortProtocol +- |= CSMI_SAS_PROTOCOL_SMP; +- if (protocol & MPI_SAS_DEVICE_INFO_SATA_DEVICE) +- karg->Information.Phy[ii].Identify.bTargetPortProtocol +- |= CSMI_SAS_PROTOCOL_SATA; ++ if( protocol & MPI_SAS_DEVICE_INFO_SSP_TARGET ) ++ karg->Information.Phy[ii].Identify.bTargetPortProtocol |= ++ CSMI_SAS_PROTOCOL_SSP; ++ if( protocol & MPI_SAS_DEVICE_INFO_STP_TARGET ) ++ karg->Information.Phy[ii].Identify.bTargetPortProtocol |= ++ CSMI_SAS_PROTOCOL_STP; ++ if( protocol & MPI_SAS_DEVICE_INFO_SMP_TARGET ) ++ karg->Information.Phy[ii].Identify.bTargetPortProtocol |= ++ CSMI_SAS_PROTOCOL_SMP; ++ if( protocol & MPI_SAS_DEVICE_INFO_SATA_DEVICE ) ++ karg->Information.Phy[ii].Identify.bTargetPortProtocol |= ++ CSMI_SAS_PROTOCOL_SATA; + + /* Setup SAS Address for the attached device */ + if (sasPhyPg0->AttachedDevHandle) { +@@ -1413,13 +1450,13 @@ + sizeof(CSMI_SAS_PHY_INFO_BUFFER))) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to write out csmisas_get_phy_info_buffer @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- free_pages((unsigned long)karg, memory_pages); +- return -EFAULT; +- } +- +- free_pages((unsigned long)karg, memory_pages); +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ free_pages((unsigned long)karg, memory_pages); ++ return -EFAULT; ++ } ++ ++ free_pages((unsigned long)karg, memory_pages); ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + } + +@@ -1442,28 +1479,30 @@ + if (copy_from_user(&karg, uarg, sizeof(CSMI_SAS_SET_PHY_INFO_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_set_phy_info struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); +- ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); ++ ++/* TODO - implement IOCTL here */ + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_BAD_CNTL_CODE; + dcsmisasprintk(ioc, printk(KERN_DEBUG ": not implemented\n")); + ++// cim_set_phy_info_exit: + + /* Copy the data from kernel memory to user memory + */ +@@ -1471,11 +1510,11 @@ + sizeof(CSMI_SAS_SET_PHY_INFO_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_set_phy_info @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + + } +@@ -1502,24 +1541,24 @@ + sizeof(CSMI_SAS_GET_SCSI_ADDRESS_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_get_scsi_address struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + /* reverse byte order the sas address */ + memcpy(&sas_address, karg.bSASAddress, sizeof(u64)); +@@ -1547,11 +1586,11 @@ + sizeof(CSMI_SAS_GET_SCSI_ADDRESS_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_get_scsi_address @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + } + +@@ -1582,38 +1621,37 @@ + u8 phyId; + u64 sas_address; + +- sasPhyPg0 = NULL; +- sasPhyPg0_data_sz = 0; +- sasDevicePg1 = NULL; +- sasDevicePg1_data_sz = 0; ++ sasPhyPg0=NULL; ++ sasPhyPg0_data_sz=0; ++ sasDevicePg1=NULL; ++ sasDevicePg1_data_sz=0; + + if (copy_from_user(&karg, uarg, + sizeof(CSMI_SAS_SATA_SIGNATURE_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_sata_signature struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + phyId = karg.Signature.bPhyIdentifier; + if (phyId >= ioc->num_ports) { + karg.IoctlHeader.ReturnCode = CSMI_SAS_PHY_DOES_NOT_EXIST; +- dcsmisasprintk(ioc, +- printk(KERN_WARNING ": phyId >= ioc->num_ports\n")); ++ dcsmisasprintk(ioc, printk(KERN_WARNING ": phyId >= ioc->num_ports\n")); + goto cim_sata_signature_exit; + } + +@@ -1645,17 +1683,16 @@ + */ + dcsmisasprintk(ioc, printk(KERN_ERR + ": FAILED: MPI_SASPHY0_PAGEVERSION: HEADER\n")); +- dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n", rc)); +- karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; +- goto cim_sata_signature_exit; +- } +- +- if (hdr.ExtPageLength == 0) { +- /* Don't check if this failed. Already in a +- * failure case. +- */ +- dcsmisasprintk(ioc, +- printk(KERN_ERR ": hdr.ExtPageLength == 0\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n",rc)); ++ karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; ++ goto cim_sata_signature_exit; ++ } ++ ++ if (hdr.ExtPageLength == 0) { ++ /* Don't check if this failed. Already in a ++ * failure case. ++ */ ++ dcsmisasprintk(ioc, printk(KERN_ERR ": hdr.ExtPageLength == 0\n")); + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_sata_signature_exit; + } +@@ -1667,9 +1704,8 @@ + sasPhyPg0 = (SasPhyPage0_t *) pci_alloc_consistent(ioc->pcidev, + sasPhyPg0_data_sz, &sasPhyPg0_dma); + +- if (!sasPhyPg0) { +- dcsmisasprintk(ioc, +- printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); ++ if (! sasPhyPg0) { ++ dcsmisasprintk(ioc, printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_sata_signature_exit; + } +@@ -1684,7 +1720,7 @@ + */ + dcsmisasprintk(ioc, printk(KERN_ERR + ": FAILED: MPI_SASPHY0_PAGEVERSION: PAGE\n")); +- dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n", rc)); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n",rc)); + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_sata_signature_exit; + } +@@ -1692,8 +1728,7 @@ + /* Make sure a SATA device is attached. */ + if ((le32_to_cpu(sasPhyPg0->AttachedDeviceInfo) & + MPI_SAS_DEVICE_INFO_SATA_DEVICE) == 0) { +- dcsmisasprintk(ioc, +- printk(KERN_WARNING ": NOT A SATA DEVICE\n")); ++ dcsmisasprintk(ioc, printk(KERN_WARNING ": NOT A SATA DEVICE\n")); + karg.IoctlHeader.ReturnCode = CSMI_SAS_NO_SATA_DEVICE; + goto cim_sata_signature_exit; + } +@@ -1720,14 +1755,13 @@ + if ((rc = mpt_config(ioc, &cfg)) != 0) { + dcsmisasprintk(ioc, printk(KERN_ERR + ": FAILED: MPI_SASDEVICE1_PAGEVERSION: HEADER\n")); +- dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n", rc)); +- karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; +- goto cim_sata_signature_exit; +- } +- +- if (hdr.ExtPageLength == 0) { +- dcsmisasprintk(ioc, printk(KERN_ERR +- ": hdr.ExtPageLength == 0\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n",rc)); ++ karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; ++ goto cim_sata_signature_exit; ++ } ++ ++ if (hdr.ExtPageLength == 0) { ++ dcsmisasprintk(ioc, printk(KERN_ERR ": hdr.ExtPageLength == 0\n")); + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_sata_signature_exit; + } +@@ -1738,9 +1772,8 @@ + sasDevicePg1 = (SasDevicePage1_t *) pci_alloc_consistent + (ioc->pcidev, sasDevicePg1_data_sz, &sasDevicePg1_dma); + +- if (!sasDevicePg1) { +- dcsmisasprintk(ioc, printk(KERN_ERR +- ": pci_alloc_consistent: FAILED\n")); ++ if (! sasDevicePg1) { ++ dcsmisasprintk(ioc, printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_sata_signature_exit; + } +@@ -1752,31 +1785,29 @@ + if ((rc = mpt_config(ioc, &cfg)) != 0) { + dcsmisasprintk(ioc, printk(KERN_ERR + ": FAILED: MPI_SASDEVICE1_PAGEVERSION: PAGE\n")); +- dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n", rc)); +- karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; +- goto cim_sata_signature_exit; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "---- SAS DEVICE PAGE 1 ---------\n")); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "Handle=0x%x\n", sasDevicePg1->DevHandle)); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n",rc)); ++ karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; ++ goto cim_sata_signature_exit; ++ } ++ ++/* EDM : dump Device Page 1 data*/ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "---- SAS DEVICE PAGE 1 ---------\n")); ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "Handle=0x%x\n",sasDevicePg1->DevHandle)); + memcpy(&sas_address, &sasDevicePg1->SASAddress, sizeof(u64)); + dcsmisasprintk(ioc, printk(KERN_DEBUG "SAS Address=0x%llX\n", + (unsigned long long)sas_address)); + dcsmisasprintk(ioc, printk(KERN_DEBUG "\n")); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "Target ID=0x%x\n", sasDevicePg1->TargetID)); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "Bus=0x%x\n", sasDevicePg1->Bus)); ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "Target ID=0x%x\n",sasDevicePg1->TargetID)); ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "Bus=0x%x\n",sasDevicePg1->Bus)); + dcsmisasprintk(ioc, printk(KERN_DEBUG "Initial Reg Device FIS=")); +- for (jj = 0; jj < 20; jj++) ++ for(jj=0;jj<20;jj++) + dcsmisasprintk(ioc, printk("%02x ", + ((u8 *)&sasDevicePg1->InitialRegDeviceFIS)[jj])); + dcsmisasprintk(ioc, printk(KERN_DEBUG "\n\n")); ++/* EDM : debug data */ + + memcpy(karg.Signature.bSignatureFIS, +- sasDevicePg1->InitialRegDeviceFIS, 20); ++ sasDevicePg1->InitialRegDeviceFIS,20); + + cim_sata_signature_exit: + +@@ -1794,11 +1825,11 @@ + sizeof(CSMI_SAS_SATA_SIGNATURE_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_sata_signature @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + } + +@@ -1824,24 +1855,24 @@ + sizeof(CSMI_SAS_GET_DEVICE_ADDRESS_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_get_device_address_buffer struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + karg.IoctlHeader.ReturnCode = CSMI_SAS_NO_DEVICE_ADDRESS; + memset(karg.bSASAddress, 0, sizeof(u64)); +@@ -1865,11 +1896,11 @@ + sizeof(CSMI_SAS_GET_DEVICE_ADDRESS_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_get_device_address_buffer @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + } + +@@ -1902,36 +1933,35 @@ + u16 ioc_status; + u32 MsgContext; + +- sasPhyPage1 = NULL; +- sasPhyPage1_data_sz = 0; ++ sasPhyPage1=NULL; ++ sasPhyPage1_data_sz=0; + + if (copy_from_user(&karg, uarg, + sizeof(CSMI_SAS_LINK_ERRORS_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmisas_get_link_errors struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + phyId = karg.Information.bPhyIdentifier; + if (phyId >= ioc->num_ports) { + karg.IoctlHeader.ReturnCode = CSMI_SAS_PHY_DOES_NOT_EXIST; +- dcsmisasprintk(ioc, printk(KERN_WARNING +- ": phyId >= ioc->num_ports\n")); ++ dcsmisasprintk(ioc, printk(KERN_WARNING ": phyId >= ioc->num_ports\n")); + goto cim_get_link_errors_exit; + } + +@@ -1963,17 +1993,16 @@ + */ + dcsmisasprintk(ioc, printk(KERN_ERR + ": FAILED: MPI_SASPHY1_PAGEVERSION: HEADER\n")); +- dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n", rc)); +- karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; +- goto cim_get_link_errors_exit; +- } +- +- if (hdr.ExtPageLength == 0) { +- /* Don't check if this failed. Already in a +- * failure case. +- */ +- dcsmisasprintk(ioc, printk(KERN_ERR +- ": hdr.ExtPageLength == 0\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n",rc)); ++ karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; ++ goto cim_get_link_errors_exit; ++ } ++ ++ if (hdr.ExtPageLength == 0) { ++ /* Don't check if this failed. Already in a ++ * failure case. ++ */ ++ dcsmisasprintk(ioc, printk(KERN_ERR ": hdr.ExtPageLength == 0\n")); + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_get_link_errors_exit; + } +@@ -1985,9 +2014,8 @@ + sasPhyPage1 = (SasPhyPage1_t *) pci_alloc_consistent(ioc->pcidev, + sasPhyPage1_data_sz, &sasPhyPage1_dma); + +- if (!sasPhyPage1) { +- dcsmisasprintk(ioc, printk(KERN_ERR +- ": pci_alloc_consistent: FAILED\n")); ++ if (! sasPhyPage1) { ++ dcsmisasprintk(ioc, printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_get_link_errors_exit; + } +@@ -2000,25 +2028,24 @@ + /* Don't check if this failed. Already in a + * failure case. + */ +- dcsmisasprintk(ioc, printk(KERN_ERR +- ": FAILED: MPI_SASPHY1_PAGEVERSION: PAGE\n")); +- dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n", rc)); +- karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; +- goto cim_get_link_errors_exit; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "---- SAS PHY PAGE 1 ------------\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": FAILED: MPI_SASPHY1_PAGEVERSION: PAGE\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": rc=%x\n",rc)); ++ karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; ++ goto cim_get_link_errors_exit; ++ } ++ ++/* EDM : dump PHY Page 1 data*/ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "---- SAS PHY PAGE 1 ------------\n")); + dcsmisasprintk(ioc, printk(KERN_DEBUG "Invalid Dword Count=0x%x\n", + sasPhyPage1->InvalidDwordCount)); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "Running Disparity Error Count=0x%x\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "Running Disparity Error Count=0x%x\n", + sasPhyPage1->RunningDisparityErrorCount)); + dcsmisasprintk(ioc, printk(KERN_DEBUG "Loss Dword Synch Count=0x%x\n", + sasPhyPage1->LossDwordSynchCount)); + dcsmisasprintk(ioc, printk(KERN_DEBUG "PHY Reset Problem Count=0x%x\n", + sasPhyPage1->PhyResetProblemCount)); + dcsmisasprintk(ioc, printk(KERN_DEBUG "\n\n")); ++/* EDM : debug data */ + + karg.Information.uInvalidDwordCount = + le32_to_cpu(sasPhyPage1->InvalidDwordCount); +@@ -2030,7 +2057,7 @@ + le32_to_cpu(sasPhyPage1->PhyResetProblemCount); + + if (karg.Information.bResetCounts == +- CSMI_SAS_LINK_ERROR_DONT_RESET_COUNTS) { ++ CSMI_SAS_LINK_ERROR_DONT_RESET_COUNTS ) { + goto cim_get_link_errors_exit; + } + +@@ -2045,12 +2072,12 @@ + dcsmisasprintk(ioc, printk(KERN_ERR ": no msg frames!\n")); + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_get_link_errors_exit; +- } ++ } + + mpi_hdr = (MPIHeader_t *) mf; + MsgContext = mpi_hdr->MsgContext; + sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf; +- memset(sasIoUnitCntrReq, 0, sizeof(SasIoUnitControlRequest_t)); ++ memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t)); + sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL; + sasIoUnitCntrReq->MsgContext = MsgContext; + sasIoUnitCntrReq->PhyNum = phyId; +@@ -2070,10 +2097,8 @@ + & MPI_IOCSTATUS_MASK; + + if (ioc_status != MPI_IOCSTATUS_SUCCESS) { +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- ": SAS IO Unit Control: ")); +- dcsmisasprintk(ioc, printk( +- "IOCStatus=0x%X IOCLogInfo=0x%X\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG ": SAS IO Unit Control: ")); ++ dcsmisasprintk(ioc, printk("IOCStatus=0x%X IOCLogInfo=0x%X\n", + sasIoUnitCntrReply->IOCStatus, + sasIoUnitCntrReply->IOCLogInfo)); + } +@@ -2091,11 +2116,11 @@ + sizeof(CSMI_SAS_LINK_ERRORS_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmisas_get_link_errors @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + + } +@@ -2120,10 +2145,10 @@ + MPIHeader_t *mpi_hdr; + char *psge; + int iocnum, flagsLength; +- void *request_data; ++ void * request_data; + dma_addr_t request_data_dma; + u32 request_data_sz; +- void *response_data; ++ void * response_data; + dma_addr_t response_data_dma; + u32 response_data_sz; + u16 ioc_status; +@@ -2136,11 +2161,11 @@ + memory_pages = get_order(malloc_data_sz); + karg = (CSMI_SAS_SMP_PASSTHRU_BUFFER *)__get_free_pages( + GFP_KERNEL, memory_pages); +- if (!karg) { ++ if (!karg){ + printk(KERN_ERR "%s@%d::%s() - " + "Unable to malloc CSMI_SAS_SMP_PASSTHRU_BUFFER " + "malloc_data_sz=%d memory_pages=%d\n", +- __FILE__, __LINE__, __func__, ++ __FILE__, __LINE__, __FUNCTION__, + malloc_data_sz, memory_pages); + return -ENOMEM; + } +@@ -2148,7 +2173,7 @@ + if (copy_from_user(karg, uarg, sizeof(CSMI_SAS_SMP_PASSTHRU_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_smp_passthru struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + free_pages((unsigned long)karg, memory_pages); + return -EFAULT; + } +@@ -2161,7 +2186,7 @@ + if (((iocnum = mpt_verify_adapter(karg->IoctlHeader.IOControllerNumber, + &ioc)) < 0) || (ioc == NULL)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); + free_pages((unsigned long)karg, memory_pages); + return -ENODEV; + } +@@ -2169,19 +2194,19 @@ + if (ioc->ioc_reset_in_progress) { + printk(KERN_ERR "%s@%d::%s - " + "Busy with IOC Reset \n", +- __FILE__, __LINE__, __func__); ++ __FILE__, __LINE__,__FUNCTION__); + free_pages((unsigned long)karg, memory_pages); + return -EBUSY; + } + + if (!csmisas_is_this_sas_cntr(ioc)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)karg, memory_pages); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)karg, memory_pages); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + /* Default to success.*/ + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_SUCCESS; +@@ -2203,13 +2228,13 @@ + dcsmisasprintk(ioc, printk(KERN_ERR ": no msg frames!\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_smp_passthru_exit; +- } ++ } + + mpi_hdr = (MPIHeader_t *) mf; + MsgContext = mpi_hdr->MsgContext; +- smpReq = (pSmpPassthroughRequest_t) mf; +- +- memset(smpReq, 0, ioc->req_sz); ++ smpReq = (pSmpPassthroughRequest_t ) mf; ++ ++ memset(smpReq,0,ioc->req_sz); + + memcpy(&sas_address, karg->Parameters.bDestinationSASAddress, + sizeof(u64)); +@@ -2245,8 +2270,7 @@ + ioc->pcidev, request_data_sz, &request_data_dma); + + if (!request_data) { +- dcsmisasprintk(ioc, printk(KERN_ERR +- ": pci_alloc_consistent: FAILED\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + mpt_free_msg_frame(ioc, mf); + goto cim_smp_passthru_exit; +@@ -2262,8 +2286,7 @@ + ioc->pcidev, response_data_sz, &response_data_dma); + + if (!response_data) { +- dcsmisasprintk(ioc, printk(KERN_ERR +- ": pci_alloc_consistent: FAILED\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + mpt_free_msg_frame(ioc, mf); + goto cim_smp_passthru_exit; +@@ -2279,29 +2302,26 @@ + + ioc->add_sge(psge, flagsLength, response_data_dma); + +- if (csmisas_send_command_wait(ioc, mf, karg->IoctlHeader.Timeout) +- != 0) { ++ if (csmisas_send_command_wait(ioc, mf, karg->IoctlHeader.Timeout) != 0) { + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_smp_passthru_exit; + } + + if ((ioc->ioctl_cmds.status & MPT_MGMT_STATUS_RF_VALID) == 0) { +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- ": SMP Passthru: oh no, there is no reply!!")); ++ dcsmisasprintk(ioc, printk(KERN_DEBUG ": SMP Passthru: oh no, there is no reply!!")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_smp_passthru_exit; + } + + /* process the completed Reply Message Frame */ +- smpReply = (pSmpPassthroughReply_t)ioc->ioctl_cmds.reply; ++ smpReply = (pSmpPassthroughReply_t )ioc->ioctl_cmds.reply; + ioc_status = le16_to_cpu(smpReply->IOCStatus) & MPI_IOCSTATUS_MASK; + + if ((ioc_status != MPI_IOCSTATUS_SUCCESS) && + (ioc_status != MPI_IOCSTATUS_SCSI_DATA_UNDERRUN)) { + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + dcsmisasprintk(ioc, printk(KERN_DEBUG ": SMP Passthru: ")); +- dcsmisasprintk(ioc, printk( +- "IOCStatus=0x%X IOCLogInfo=0x%X SASStatus=0x%X\n", ++ dcsmisasprintk(ioc, printk("IOCStatus=0x%X IOCLogInfo=0x%X SASStatus=0x%X\n", + le16_to_cpu(smpReply->IOCStatus), + le32_to_cpu(smpReply->IOCLogInfo), + smpReply->SASStatus)); +@@ -2313,8 +2333,7 @@ + + + if (le16_to_cpu(smpReply->ResponseDataLength)) { +- karg->Parameters.uResponseBytes +- = le16_to_cpu(smpReply->ResponseDataLength); ++ karg->Parameters.uResponseBytes = le16_to_cpu(smpReply->ResponseDataLength); + memcpy(&karg->Parameters.Response, + response_data, le16_to_cpu(smpReply->ResponseDataLength)); + } +@@ -2336,13 +2355,13 @@ + sizeof(CSMI_SAS_SMP_PASSTHRU_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_smp_passthru @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- free_pages((unsigned long)karg, memory_pages); +- return -EFAULT; +- } +- +- free_pages((unsigned long)karg, memory_pages); +- dcsmisasprintk(ioc, printk(KERN_DEBUG ": %s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ free_pages((unsigned long)karg, memory_pages); ++ return -EFAULT; ++ } ++ ++ free_pages((unsigned long)karg, memory_pages); ++ dcsmisasprintk(ioc, printk(KERN_DEBUG ": %s exit.\n",__FUNCTION__)); + return 0; + } + +@@ -2357,18 +2376,18 @@ + static int csmisas_ssp_passthru(unsigned long arg) + { + CSMI_SAS_SSP_PASSTHRU_BUFFER __user *uarg = (void __user *) arg; +- CSMI_SAS_SSP_PASSTHRU_BUFFER karg_hdr, *karg; ++ CSMI_SAS_SSP_PASSTHRU_BUFFER karg_hdr, * karg; + MPT_ADAPTER *ioc = NULL; + pSCSIIORequest_t pScsiRequest; + pSCSIIOReply_t pScsiReply; + MPT_FRAME_HDR *mf = NULL; + MPIHeader_t *mpi_hdr; +- int iocnum, ii; ++ int iocnum,ii; + u64 sas_address; + u16 req_idx; + char *psge; + int flagsLength; +- void *request_data; ++ void * request_data; + dma_addr_t request_data_dma; + u32 request_data_sz; + int malloc_data_sz; +@@ -2383,11 +2402,10 @@ + u8 skey, asc, ascq; + u32 MsgContext; + +- if (copy_from_user(&karg_hdr, uarg, +- sizeof(CSMI_SAS_SSP_PASSTHRU_BUFFER))) { ++ if (copy_from_user(&karg_hdr, uarg, sizeof(CSMI_SAS_SSP_PASSTHRU_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_ssp_passthru struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + return -EFAULT; + } + +@@ -2404,11 +2422,11 @@ + memory_pages = get_order(malloc_data_sz); + karg = (CSMI_SAS_SSP_PASSTHRU_BUFFER *)__get_free_pages( + GFP_KERNEL, memory_pages); +- if (!karg) { ++ if (!karg){ + printk(KERN_ERR "%s@%d::%s() - " + "Unable to malloc SAS_SSP_PASSTHRU_BUFFER " + "malloc_data_sz=%d memory_pages=%d\n", +- __FILE__, __LINE__, __func__, ++ __FILE__, __LINE__, __FUNCTION__, + malloc_data_sz, memory_pages); + return -ENOMEM; + } +@@ -2416,10 +2434,10 @@ + memset(karg, 0, sizeof(*karg)); + + if (copy_from_user(karg, uarg, request_data_sz + +- offsetof(CSMI_SAS_SSP_PASSTHRU_BUFFER, bDataBuffer))) { ++ offsetof(CSMI_SAS_SSP_PASSTHRU_BUFFER,bDataBuffer))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_ssp_passthru struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + free_pages((unsigned long)karg, memory_pages); + return -EFAULT; + } +@@ -2427,43 +2445,40 @@ + /* + * some checks of the incoming frame + */ +- if (offsetof(CSMI_SAS_SSP_PASSTHRU_BUFFER, bDataBuffer) + ++ if ( offsetof(CSMI_SAS_SSP_PASSTHRU_BUFFER,bDataBuffer) + + request_data_sz - sizeof(IOCTL_HEADER) > +- karg->IoctlHeader.Length) { +- karg->IoctlHeader.ReturnCode +- = CSMI_SAS_STATUS_INVALID_PARAMETER; ++ karg->IoctlHeader.Length ) { ++ karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_INVALID_PARAMETER; + dcsmisasprintk(ioc, printk(KERN_ERR + "%s::%s()" + " @%d - expected datalen incorrect!\n", +- __FILE__, __func__, __LINE__)); ++ __FILE__, __FUNCTION__, __LINE__)); + goto cim_ssp_passthru_exit; + } + + if (((iocnum = mpt_verify_adapter(karg->IoctlHeader.IOControllerNumber, + &ioc)) < 0) || (ioc == NULL)) { +- karg->IoctlHeader.ReturnCode +- = CSMI_SAS_STATUS_INVALID_PARAMETER; +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_INVALID_PARAMETER; ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); + goto cim_ssp_passthru_exit; + } + + if (ioc->ioc_reset_in_progress) { + printk(KERN_ERR "%s@%d::%s - " + "Busy with IOC Reset \n", +- __FILE__, __LINE__, __func__); ++ __FILE__, __LINE__,__FUNCTION__); + return -EBUSY; + } + + if (!csmisas_is_this_sas_cntr(ioc)) { +- karg->IoctlHeader.ReturnCode +- = CSMI_SAS_STATUS_INVALID_PARAMETER; ++ karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_INVALID_PARAMETER; + printk(KERN_ERR "%s::%s()@%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- goto cim_ssp_passthru_exit; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ goto cim_ssp_passthru_exit; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + /* Default to success. + */ +@@ -2477,7 +2492,7 @@ + dcsmisasprintk(ioc, printk(KERN_ERR + "%s::%s()" + " @%d - incorrect bPhyIdentifier and bPortIdentifier!\n", +- __FILE__, __func__, __LINE__)); ++ __FILE__, __FUNCTION__, __LINE__)); + goto cim_ssp_passthru_exit; + } + +@@ -2487,8 +2502,7 @@ + + /* Is the phy in range? */ + if (karg->Parameters.bPhyIdentifier >= ioc->num_ports) { +- dcsmisasprintk(ioc, printk(KERN_WARNING +- ": phyId >= ioc->num_ports (%d %d)\n", ++ dcsmisasprintk(ioc, printk(KERN_WARNING ": phyId >= ioc->num_ports (%d %d)\n", + karg->Parameters.bPhyIdentifier, + ioc->num_ports)); + karg->IoctlHeader.ReturnCode = +@@ -2497,9 +2511,10 @@ + } + } + +- if (karg->Parameters.bAdditionalCDBLength) { +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- ": greater than 16-byte cdb " ++ if(karg->Parameters.bAdditionalCDBLength) { ++ /* TODO - SCSI IO (32) Request Message support ++ */ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG ": greater than 16-byte cdb " + "is not supported!\n")); + karg->IoctlHeader.ReturnCode = + CSMI_SAS_STATUS_INVALID_PARAMETER; +@@ -2523,7 +2538,7 @@ + CSMI_SAS_STATUS_INVALID_PARAMETER; + dcsmisasprintk(ioc, printk(KERN_ERR + "%s::%s() @%d - couldn't find associated " +- "SASAddress=%llX!\n", __FILE__, __func__, __LINE__, ++ "SASAddress=%llX!\n", __FILE__, __FUNCTION__, __LINE__, + (unsigned long long)sas_address)); + goto cim_ssp_passthru_exit; + } +@@ -2543,21 +2558,20 @@ + dcsmisasprintk(ioc, printk(KERN_ERR ": no msg frames!\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_ssp_passthru_exit; +- } ++ } + + mpi_hdr = (MPIHeader_t *) mf; + MsgContext = mpi_hdr->MsgContext; + pScsiRequest = (pSCSIIORequest_t) mf; + req_idx = le16_to_cpu(mf->u.frame.hwhdr.msgctxu.fld.req_idx); + +- memset(pScsiRequest, 0, sizeof(SCSIIORequest_t)); ++ memset(pScsiRequest,0,sizeof(SCSIIORequest_t)); + + /* Fill in SCSI IO (16) request. + */ + + pScsiRequest->Function = (is_hidden_raid_component == 1) ? +- MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH +- : MPI_FUNCTION_SCSI_IO_REQUEST; ++ MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH : MPI_FUNCTION_SCSI_IO_REQUEST; + pScsiRequest->TargetID = id; + pScsiRequest->Bus = channel; + memcpy(pScsiRequest->LUN, &karg->Parameters.bLun, 8); +@@ -2569,11 +2583,10 @@ + + dcsmisasprintk(ioc, printk(KERN_DEBUG "\tchannel = %d id = %d ", + sas_info->fw.channel, sas_info->fw.id)); +- dcsmisasprintk(ioc, if (is_hidden_raid_component) ++ dcsmisasprintk(ioc, if(is_hidden_raid_component) + printk(KERN_DEBUG "num_id = %d ", id)); + dcsmisasprintk(ioc, printk(KERN_DEBUG "\n")); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "\tcdb_len = %d request_len = %d\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "\tcdb_len = %d request_len = %d\n", + pScsiRequest->CDBLength, request_data_sz)); + dcsmisasprintk(ioc, printk(KERN_DEBUG "\t")); + dcsmisasprintk(ioc, for (ii = 0; ii < pScsiRequest->CDBLength; ++ii) +@@ -2590,8 +2603,7 @@ + (!karg->Parameters.uDataLength)) { + /* no data transfer + */ +- pScsiRequest->Control +- = cpu_to_le32(MPI_SCSIIO_CONTROL_NODATATRANSFER); ++ pScsiRequest->Control = cpu_to_le32(MPI_SCSIIO_CONTROL_NODATATRANSFER); + } else { + /* no direction specified + */ +@@ -2606,23 +2618,19 @@ + + /* task attributes + */ +- if ((karg->Parameters.uFlags && 0xFF) == 0) { +- pScsiRequest->Control +- |= cpu_to_le32(MPI_SCSIIO_CONTROL_SIMPLEQ); ++ if((karg->Parameters.uFlags && 0xFF) == 0) { ++ pScsiRequest->Control |= cpu_to_le32(MPI_SCSIIO_CONTROL_SIMPLEQ); + } else if (karg->Parameters.uFlags & + CSMI_SAS_SSP_TASK_ATTRIBUTE_HEAD_OF_QUEUE) { +- pScsiRequest->Control +- |= cpu_to_le32(MPI_SCSIIO_CONTROL_HEADOFQ); ++ pScsiRequest->Control |= cpu_to_le32(MPI_SCSIIO_CONTROL_HEADOFQ); + } else if (karg->Parameters.uFlags & + CSMI_SAS_SSP_TASK_ATTRIBUTE_ORDERED) { +- pScsiRequest->Control +- |= cpu_to_le32(MPI_SCSIIO_CONTROL_ORDEREDQ); ++ pScsiRequest->Control |= cpu_to_le32(MPI_SCSIIO_CONTROL_ORDEREDQ); + } else if (karg->Parameters.uFlags & + CSMI_SAS_SSP_TASK_ATTRIBUTE_ACA) { + pScsiRequest->Control |= cpu_to_le32(MPI_SCSIIO_CONTROL_ACAQ); + } else { +- pScsiRequest->Control +- |= cpu_to_le32(MPI_SCSIIO_CONTROL_UNTAGGED); ++ pScsiRequest->Control |= cpu_to_le32(MPI_SCSIIO_CONTROL_UNTAGGED); + } + + /* setup sense +@@ -2639,20 +2647,19 @@ + flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE; + } else if (karg->Parameters.uFlags & CSMI_SAS_SSP_READ) { + flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ; +- } else { +- flagsLength = (MPI_SGE_FLAGS_SIMPLE_ELEMENT | +- MPI_SGE_FLAGS_DIRECTION) ++ }else { ++ flagsLength = ( MPI_SGE_FLAGS_SIMPLE_ELEMENT | ++ MPI_SGE_FLAGS_DIRECTION ) + << MPI_SGE_FLAGS_SHIFT; + } + flagsLength |= request_data_sz; + +- if (request_data_sz > 0) { ++ if ( request_data_sz > 0) { + request_data = pci_alloc_consistent( + ioc->pcidev, request_data_sz, &request_data_dma); + + if (request_data == NULL) { +- dcsmisasprintk(ioc, printk(KERN_ERR +- ": pci_alloc_consistent: FAILED " ++ dcsmisasprintk(ioc, printk(KERN_ERR ": pci_alloc_consistent: FAILED " + "request_data_sz=%d\n", request_data_sz)); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + mpt_free_msg_frame(ioc, mf); +@@ -2661,19 +2668,17 @@ + + ioc->add_sge(psge, flagsLength, request_data_dma); + if (karg->Parameters.uFlags & CSMI_SAS_SSP_WRITE) +- memcpy(request_data, karg->bDataBuffer, +- request_data_sz); ++ memcpy(request_data, karg->bDataBuffer, request_data_sz); + } else { + ioc->add_sge(psge, flagsLength, (dma_addr_t) -1); + } + +- if (csmisas_send_command_wait(ioc, mf, karg->IoctlHeader.Timeout) +- != 0) { +- karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; +- goto cim_ssp_passthru_exit; +- } +- +- memset(&karg->Status, 0, sizeof(CSMI_SAS_SSP_PASSTHRU_STATUS)); ++ if (csmisas_send_command_wait(ioc, mf, karg->IoctlHeader.Timeout) != 0) { ++ karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; ++ goto cim_ssp_passthru_exit; ++ } ++ ++ memset(&karg->Status,0,sizeof(CSMI_SAS_SSP_PASSTHRU_STATUS)); + karg->Status.bConnectionStatus = CSMI_SAS_OPEN_ACCEPT; + karg->Status.bDataPresent = CSMI_SAS_SSP_NO_DATA_PRESENT; + karg->Status.bStatus = GOOD; +@@ -2684,13 +2689,11 @@ + /* process the completed Reply Message Frame */ + if (ioc->ioctl_cmds.status & MPT_MGMT_STATUS_RF_VALID) { + +- pScsiReply = (pSCSIIOReply_t) ioc->ioctl_cmds.reply; ++ pScsiReply = (pSCSIIOReply_t ) ioc->ioctl_cmds.reply; + karg->Status.bStatus = pScsiReply->SCSIStatus; +- karg->Status.uDataBytes +- = min(le32_to_cpu(pScsiReply->TransferCount), ++ karg->Status.uDataBytes = min(le32_to_cpu(pScsiReply->TransferCount), + request_data_sz); +- ioc_status +- = le16_to_cpu(pScsiReply->IOCStatus) & MPI_IOCSTATUS_MASK; ++ ioc_status = le16_to_cpu(pScsiReply->IOCStatus) & MPI_IOCSTATUS_MASK; + + if (pScsiReply->SCSIState == + MPI_SCSI_STATE_AUTOSENSE_VALID) { +@@ -2698,28 +2701,26 @@ + CSMI_SAS_SSP_SENSE_DATA_PRESENT; + karg->Status.bResponseLength[0] = + (u8)le32_to_cpu(pScsiReply->SenseCount) & 0xFF; +- memcpy(karg->Status.bResponse, ioc->ioctl_cmds.sense, +- le32_to_cpu(pScsiReply->SenseCount)); ++ memcpy(karg->Status.bResponse, ++ ioc->ioctl_cmds.sense, le32_to_cpu(pScsiReply->SenseCount)); + + skey = ioc->ioctl_cmds.sense[2] & 0x0F; + asc = ioc->ioctl_cmds.sense[12]; + ascq = ioc->ioctl_cmds.sense[13]; + +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "\t [sense_key,asc,ascq]: " +- "[0x%02x,0x%02x,0x%02x]\n", +- skey, asc, ascq)); +- +- } else if (pScsiReply->SCSIState == ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "\t [sense_key,asc,ascq]: " ++ "[0x%02x,0x%02x,0x%02x]\n", ++ skey, asc, ascq)); ++ ++ } else if(pScsiReply->SCSIState == + MPI_SCSI_STATE_RESPONSE_INFO_VALID) { + karg->Status.bDataPresent = + CSMI_SAS_SSP_RESPONSE_DATA_PRESENT; + karg->Status.bResponseLength[0] = + sizeof(pScsiReply->ResponseInfo); +- for (ii = 0; ii < sizeof(pScsiReply->ResponseInfo); +- ii++) { ++ for (ii=0;iiResponseInfo);ii++) { + karg->Status.bResponse[ii] = +- ((u8 *)&pScsiReply->ResponseInfo)[ ++ ((u8*)&pScsiReply->ResponseInfo)[ + (sizeof(pScsiReply->ResponseInfo)-1)-ii]; + } + } else if ((ioc_status != MPI_IOCSTATUS_SUCCESS) && +@@ -2727,8 +2728,7 @@ + (ioc_status != MPI_IOCSTATUS_SCSI_DATA_UNDERRUN)) { + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + dcsmisasprintk(ioc, printk(KERN_DEBUG ": SCSI IO : ")); +- dcsmisasprintk(ioc, +- printk("IOCStatus=0x%X IOCLogInfo=0x%X\n", ++ dcsmisasprintk(ioc, printk("IOCStatus=0x%X IOCLogInfo=0x%X\n", + pScsiReply->IOCStatus, + pScsiReply->IOCLogInfo)); + } +@@ -2740,8 +2740,8 @@ + request_data, karg->Status.uDataBytes)) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to write data to user %p\n", +- __FILE__, __LINE__, __func__, +- (void *)karg->bDataBuffer); ++ __FILE__, __LINE__,__FUNCTION__, ++ (void*)karg->bDataBuffer); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + } + } +@@ -2759,12 +2759,12 @@ + offsetof(CSMI_SAS_SSP_PASSTHRU_BUFFER, bDataBuffer))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_ssp_passthru @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- free_pages((unsigned long)karg, memory_pages); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ free_pages((unsigned long)karg, memory_pages); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + free_pages((unsigned long)karg, memory_pages); + return 0; + } +@@ -2793,7 +2793,7 @@ + u16 req_idx; + char *psge; + int flagsLength; +- void *request_data; ++ void * request_data; + dma_addr_t request_data_dma; + u32 request_data_sz; + int malloc_data_sz; +@@ -2806,15 +2806,14 @@ + u16 ioc_status; + u32 MsgContext; + +- if (copy_from_user(&karg_hdr, uarg, +- sizeof(CSMI_SAS_STP_PASSTHRU_BUFFER))) { ++ if (copy_from_user(&karg_hdr, uarg, sizeof(CSMI_SAS_STP_PASSTHRU_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- request_data = NULL; ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ request_data=NULL; + request_data_sz = karg_hdr.Parameters.uDataLength; + volume_id = 0; + volume_bus = 0; +@@ -2826,11 +2825,11 @@ + memory_pages = get_order(malloc_data_sz); + karg = (CSMI_SAS_STP_PASSTHRU_BUFFER *)__get_free_pages( + GFP_KERNEL, memory_pages); +- if (!karg) { ++ if (!karg){ + printk(KERN_ERR "%s@%d::%s() - " + "Unable to malloc CSMI_SAS_STP_PASSTHRU_BUFFER " + "malloc_data_sz=%d memory_pages=%d\n", +- __FILE__, __LINE__, __func__, ++ __FILE__, __LINE__, __FUNCTION__, + malloc_data_sz, memory_pages); + return -ENOMEM; + } +@@ -2840,7 +2839,7 @@ + if (copy_from_user(karg, uarg, malloc_data_sz)) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_ssp_passthru struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + free_pages((unsigned long)karg, memory_pages); + return -EFAULT; + } +@@ -2848,7 +2847,7 @@ + if (((iocnum = mpt_verify_adapter(karg->IoctlHeader.IOControllerNumber, + &ioc)) < 0) || (ioc == NULL)) { + printk(KERN_ERR "%s::%s @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); + free_pages((unsigned long)karg, memory_pages); + return -ENODEV; + } +@@ -2856,19 +2855,19 @@ + if (ioc->ioc_reset_in_progress) { + printk(KERN_ERR "%s@%d::%s - " + "Busy with IOC Reset \n", +- __FILE__, __LINE__, __func__); ++ __FILE__, __LINE__,__FUNCTION__); + free_pages((unsigned long)karg, memory_pages); + return -EBUSY; + } + + if (!csmisas_is_this_sas_cntr(ioc)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)karg, memory_pages); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)karg, memory_pages); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + /* Default to success. + */ +@@ -2880,9 +2879,8 @@ + (karg->Parameters.bPortIdentifier == CSMI_SAS_IGNORE_PORT)) { + karg->IoctlHeader.ReturnCode = CSMI_SAS_SELECT_PHY_OR_PORT; + dcsmisasprintk(ioc, printk(KERN_ERR +- "%s::%s() @%d -incorrect bPhyIdentifier" +- " and bPortIdentifier!\n", +- __FILE__, __func__, __LINE__)); ++ "%s::%s() @%d - incorrect bPhyIdentifier and bPortIdentifier!\n", ++ __FILE__,__FUNCTION__, __LINE__)); + goto cim_stp_passthru_exit; + } + +@@ -2899,15 +2897,15 @@ + } + + data_sz = sizeof(CSMI_SAS_STP_PASSTHRU_BUFFER) - +- sizeof(IOCTL_HEADER) - sizeof(u8 *) + ++ sizeof(IOCTL_HEADER) - sizeof(u8*) + + request_data_sz; + +- if (data_sz > karg->IoctlHeader.Length) { ++ if ( data_sz > karg->IoctlHeader.Length ) { + karg->IoctlHeader.ReturnCode = + CSMI_SAS_STATUS_INVALID_PARAMETER; + dcsmisasprintk(ioc, printk(KERN_ERR + "%s::%s() @%d - expected datalen incorrect!\n", +- __FILE__, __func__, __LINE__)); ++ __FILE__, __FUNCTION__,__LINE__)); + goto cim_stp_passthru_exit; + } + +@@ -2929,7 +2927,7 @@ + CSMI_SAS_STATUS_INVALID_PARAMETER; + dcsmisasprintk(ioc, printk(KERN_ERR + "%s::%s() @%d - couldn't find associated " +- "SASAddress=%llX!\n", __FILE__, __func__, __LINE__, ++ "SASAddress=%llX!\n", __FILE__, __FUNCTION__, __LINE__, + (unsigned long long)sas_address)); + goto cim_stp_passthru_exit; + } +@@ -2939,8 +2937,8 @@ + + /* check that this is an STP or SATA target device + */ +- if (!(sas_info->device_info & MPI_SAS_DEVICE_INFO_STP_TARGET) && +- !(sas_info->device_info & MPI_SAS_DEVICE_INFO_SATA_DEVICE)) { ++ if ( !(sas_info->device_info & MPI_SAS_DEVICE_INFO_STP_TARGET ) && ++ !(sas_info->device_info & MPI_SAS_DEVICE_INFO_SATA_DEVICE )) { + karg->IoctlHeader.ReturnCode = + CSMI_SAS_STATUS_INVALID_PARAMETER; + goto cim_stp_passthru_exit; +@@ -2952,14 +2950,14 @@ + dcsmisasprintk(ioc, printk(KERN_ERR ": no msg frames!\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_stp_passthru_exit; +- } ++ } + + mpi_hdr = (MPIHeader_t *) mf; + MsgContext = mpi_hdr->MsgContext; + pSataRequest = (pSataPassthroughRequest_t) mf; + req_idx = le16_to_cpu(mf->u.frame.hwhdr.msgctxu.fld.req_idx); + +- memset(pSataRequest, 0, sizeof(pSataPassthroughRequest_t)); ++ memset(pSataRequest,0,sizeof(pSataPassthroughRequest_t)); + + pSataRequest->TargetID = id; + pSataRequest->Bus = channel; +@@ -2969,16 +2967,16 @@ + pSataRequest->MsgContext = MsgContext; + pSataRequest->DataLength = cpu_to_le32(request_data_sz); + pSataRequest->MsgFlags = 0; +- memcpy(pSataRequest->CommandFIS, karg->Parameters.bCommandFIS, 20); ++ memcpy( pSataRequest->CommandFIS,karg->Parameters.bCommandFIS, 20); + + psge = (char *)&pSataRequest->SGL; + if (karg->Parameters.uFlags & CSMI_SAS_STP_WRITE) { + flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE; + } else if (karg->Parameters.uFlags & CSMI_SAS_STP_READ) { + flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ; +- } else { +- flagsLength = (MPI_SGE_FLAGS_SIMPLE_ELEMENT | +- MPI_SGE_FLAGS_DIRECTION) ++ }else { ++ flagsLength = ( MPI_SGE_FLAGS_SIMPLE_ELEMENT | ++ MPI_SGE_FLAGS_DIRECTION ) + << MPI_SGE_FLAGS_SHIFT; + } + +@@ -2988,8 +2986,7 @@ + ioc->pcidev, request_data_sz, &request_data_dma); + + if (request_data == NULL) { +- dcsmisasprintk(ioc, printk(KERN_ERR +- ": pci_alloc_consistent: FAILED\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + mpt_free_msg_frame(ioc, mf); + goto cim_stp_passthru_exit; +@@ -2997,37 +2994,33 @@ + + ioc->add_sge(psge, flagsLength, request_data_dma); + if (karg->Parameters.uFlags & CSMI_SAS_SSP_WRITE) +- memcpy(request_data, karg->bDataBuffer, +- request_data_sz); ++ memcpy(request_data, karg->bDataBuffer, request_data_sz); + } else { + ioc->add_sge(psge, flagsLength, (dma_addr_t) -1); + } + +- if (csmisas_send_command_wait(ioc, mf, karg->IoctlHeader.Timeout) +- != 0) { +- karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; +- goto cim_stp_passthru_exit; +- } +- +- memset(&karg->Status, 0, sizeof(CSMI_SAS_STP_PASSTHRU_STATUS)); ++ if (csmisas_send_command_wait(ioc, mf, karg->IoctlHeader.Timeout) != 0) { ++ karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; ++ goto cim_stp_passthru_exit; ++ } ++ ++ memset(&karg->Status,0,sizeof(CSMI_SAS_STP_PASSTHRU_STATUS)); + + if ((ioc->ioctl_cmds.status & MPT_MGMT_STATUS_RF_VALID) == 0) { +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- ": STP Passthru: oh no, there is no reply!!")); ++ dcsmisasprintk(ioc, printk(KERN_DEBUG ": STP Passthru: oh no, there is no reply!!")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_stp_passthru_exit; + } + + /* process the completed Reply Message Frame */ +- pSataReply = (pSataPassthroughReply_t) ioc->ioctl_cmds.reply; ++ pSataReply = (pSataPassthroughReply_t ) ioc->ioctl_cmds.reply; + ioc_status = le16_to_cpu(pSataReply->IOCStatus) & MPI_IOCSTATUS_MASK; + + if (ioc_status != MPI_IOCSTATUS_SUCCESS && + ioc_status != MPI_IOCSTATUS_SCSI_DATA_UNDERRUN) { + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + dcsmisasprintk(ioc, printk(KERN_DEBUG ": STP Passthru: ")); +- dcsmisasprintk(ioc, +- printk("IOCStatus=0x%X IOCLogInfo=0x%X SASStatus=0x%X\n", ++ dcsmisasprintk(ioc, printk("IOCStatus=0x%X IOCLogInfo=0x%X SASStatus=0x%X\n", + le16_to_cpu(pSataReply->IOCStatus), + le32_to_cpu(pSataReply->IOCLogInfo), + pSataReply->SASStatus)); +@@ -3036,27 +3029,26 @@ + karg->Status.bConnectionStatus = + map_sas_status_to_csmi(pSataReply->SASStatus); + +- memcpy(karg->Status.bStatusFIS, pSataReply->StatusFIS, 20); ++ memcpy(karg->Status.bStatusFIS,pSataReply->StatusFIS, 20); + + /* + * for now, just zero out uSCR array, + * then copy the one dword returned + * in the reply frame into uSCR[0] + */ +- memset(karg->Status.uSCR, 0, 64); ++ memset( karg->Status.uSCR, 0, 64); + karg->Status.uSCR[0] = le32_to_cpu(pSataReply->StatusControlRegisters); + +- if ((le32_to_cpu(pSataReply->TransferCount)) && (request_data) && ++ if((le32_to_cpu(pSataReply->TransferCount)) && (request_data) && + (karg->Parameters.uFlags & CSMI_SAS_STP_READ)) { + karg->Status.uDataBytes = +- min(le32_to_cpu(pSataReply->TransferCount), +- request_data_sz); ++ min(le32_to_cpu(pSataReply->TransferCount),request_data_sz); + if (copy_to_user((void __user *)uarg->bDataBuffer, + request_data, karg->Status.uDataBytes)) { + printk(KERN_ERR "%s::%s() @%d - " + "Unable to write data to user %p\n", +- __FILE__, __func__, __LINE__, +- (void *)karg->bDataBuffer); ++ __FILE__, __FUNCTION__, __LINE__, ++ (void*)karg->bDataBuffer); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + } + } +@@ -3073,13 +3065,13 @@ + offsetof(CSMI_SAS_STP_PASSTHRU_BUFFER, bDataBuffer))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_ssp_passthru @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- free_pages((unsigned long)karg, memory_pages); +- return -EFAULT; +- } +- +- free_pages((unsigned long)karg, memory_pages); +- dcsmisasprintk(ioc, printk(KERN_DEBUG ": %s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ free_pages((unsigned long)karg, memory_pages); ++ return -EFAULT; ++ } ++ ++ free_pages((unsigned long)karg, memory_pages); ++ dcsmisasprintk(ioc, printk(KERN_DEBUG ": %s exit.\n",__FUNCTION__)); + return 0; + } + +@@ -3098,30 +3090,30 @@ + CSMI_SAS_FIRMWARE_DOWNLOAD_BUFFER karg; + MPT_ADAPTER *ioc = NULL; + int iocnum; +- pMpiFwHeader_t pFwHeader = NULL; ++ pMpiFwHeader_t pFwHeader=NULL; + + if (copy_from_user(&karg, uarg, + sizeof(CSMI_SAS_FIRMWARE_DOWNLOAD_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " +- "Unable to read in csmi_sas_firmware_download struct@ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ "Unable to read in csmi_sas_firmware_download struct @ %p\n", ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + /* Default to success.*/ + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_SUCCESS; +@@ -3138,7 +3130,7 @@ + goto cim_firmware_download_exit; + } + +- if (karg.Information.uDownloadFlags & ++ if ( karg.Information.uDownloadFlags & + (CSMI_SAS_FWD_SOFT_RESET | CSMI_SAS_FWD_VALIDATE)) { + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + karg.Information.usStatus = CSMI_SAS_FWD_REJECT; +@@ -3150,7 +3142,7 @@ + * fw image attached to end of incoming packet. + */ + pFwHeader = kmalloc(karg.Information.uBufferLength, GFP_KERNEL); +- if (!pFwHeader) { ++ if (!pFwHeader){ + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + karg.Information.usStatus = CSMI_SAS_FWD_REJECT; + karg.Information.usSeverity = CSMI_SAS_FWD_ERROR; +@@ -3162,21 +3154,21 @@ + karg.Information.uBufferLength)) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in pFwHeader @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (!((pFwHeader->Signature0 == MPI_FW_HEADER_SIGNATURE_0) && ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if ( !((pFwHeader->Signature0 == MPI_FW_HEADER_SIGNATURE_0) && + (pFwHeader->Signature1 == MPI_FW_HEADER_SIGNATURE_1) && + (pFwHeader->Signature2 == MPI_FW_HEADER_SIGNATURE_2))) { +- /* the signature check failed */ ++ // the signature check failed + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + karg.Information.usStatus = CSMI_SAS_FWD_REJECT; + karg.Information.usSeverity = CSMI_SAS_FWD_ERROR; + goto cim_firmware_download_exit; + } + +- if (mptctl_do_fw_download(karg.IoctlHeader.IOControllerNumber, ++ if ( mptctl_do_fw_download(karg.IoctlHeader.IOControllerNumber, + uarg->bDataBuffer, karg.Information.uBufferLength) + != 0) { + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; +@@ -3185,7 +3177,7 @@ + goto cim_firmware_download_exit; + } + +- if ((karg.Information.uDownloadFlags & CSMI_SAS_FWD_SOFT_RESET) || ++ if((karg.Information.uDownloadFlags & CSMI_SAS_FWD_SOFT_RESET) || + (karg.Information.uDownloadFlags & CSMI_SAS_FWD_HARD_RESET)) { + if (mpt_HardResetHandler(ioc, CAN_SLEEP) != 0) { + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; +@@ -3196,7 +3188,7 @@ + + cim_firmware_download_exit: + +- if (pFwHeader) ++ if(pFwHeader) + kfree(pFwHeader); + + /* Copy the data from kernel memory to user memory +@@ -3205,11 +3197,11 @@ + sizeof(CSMI_SAS_FIRMWARE_DOWNLOAD_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_firmware_download @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + } + +@@ -3235,24 +3227,24 @@ + if (copy_from_user(&karg, uarg, sizeof(CSMI_SAS_RAID_INFO_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_get_raid_info struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + if (!ioc->raid_data.pIocPg2) +@@ -3260,8 +3252,8 @@ + karg.Information.uNumRaidSets = + ioc->raid_data.pIocPg2->NumActiveVolumes; + karg.Information.uMaxRaidSets = ioc->raid_data.pIocPg2->MaxVolumes; +- if (ioc->raid_data.pIocPg6) { +- /* get absolute maximum for all RAID sets */ ++ if( ioc->raid_data.pIocPg6 ) { ++ // get absolute maximum for all RAID sets + maxDrivesPerSet = ioc->raid_data.pIocPg6->MaxDrivesIS; + maxDrivesPerSet = max(ioc->raid_data.pIocPg6->MaxDrivesIM, + maxDrivesPerSet); +@@ -3271,19 +3263,17 @@ + } + else + karg.Information.uMaxDrivesPerSet = 8; +- /* For bMaxRaidSets, count bits set in bits 0-6 of CapabilitiesFlags */ ++ // For bMaxRaidSets, count bits set in bits 0-6 of CapabilitiesFlags + raidFlags = ioc->raid_data.pIocPg2->CapabilitiesFlags & 0x0000007F; +- for (maxRaidTypes = 0; raidFlags; maxRaidTypes++) ++ for( maxRaidTypes=0; raidFlags; maxRaidTypes++ ) + raidFlags &= raidFlags - 1; + karg.Information.bMaxRaidTypes = maxRaidTypes; +- /* ulMinRaidSetBlocks hard coded to 1MB until available +- * from config page +- */ ++ // ulMinRaidSetBlocks hard coded to 1MB until available from config page + karg.Information.ulMinRaidSetBlocks.uLowPart = 2048; + karg.Information.ulMinRaidSetBlocks.uHighPart = 0; + karg.Information.ulMaxRaidSetBlocks.uLowPart = 0xffffffff; +- if (ioc->raid_data.pIocPg2->CapabilitiesFlags & +- MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING) ++ if( ioc->raid_data.pIocPg2->CapabilitiesFlags & ++ MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING ) + karg.Information.ulMaxRaidSetBlocks.uHighPart = 0xffffffff; + else + karg.Information.ulMaxRaidSetBlocks.uHighPart = 0; +@@ -3303,11 +3293,11 @@ + sizeof(CSMI_SAS_RAID_INFO_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_get_raid_info @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + } + +@@ -3325,8 +3315,7 @@ + * Remark: Wait to return until reply processed by the ISR. + **/ + static int +-csmisas_do_raid(MPT_ADAPTER *ioc, u8 action, u8 PhysDiskNum, u8 VolumeBus, +- u8 VolumeId, pMpiRaidActionReply_t reply) ++csmisas_do_raid(MPT_ADAPTER *ioc, u8 action, u8 PhysDiskNum, u8 VolumeBus, u8 VolumeId, pMpiRaidActionReply_t reply) + { + MpiRaidActionRequest_t *pReq; + MpiRaidActionReply_t *pReply; +@@ -3349,6 +3338,7 @@ + pReq->MsgFlags = 0; + pReq->Reserved2 = 0; + pReq->ActionDataWord = 0; /* Reserved for this action */ ++ //pReq->ActionDataSGE = 0; + + ioc->add_sge((char *)&pReq->ActionDataSGE, + MPT_SGE_FLAGS_SSIMPLE_READ | 0, (dma_addr_t) -1); +@@ -3357,7 +3347,7 @@ + return -ENODATA; + + if ((ioc->ioctl_cmds.status & MPT_MGMT_STATUS_RF_VALID) && +- (reply != NULL)) { ++ (reply != NULL)){ + pReply = (MpiRaidActionReply_t *)&(ioc->ioctl_cmds.reply); + memcpy(reply, pReply, + min(ioc->reply_sz, +@@ -3381,7 +3371,7 @@ + **/ + static int + csmisas_raid_inq(MPT_ADAPTER *ioc, u8 opcode, u8 bus, u8 id, u8 inq_vpd_page, +- u8 *inq_vpd, u32 inq_vpd_sz) ++ u8 * inq_vpd, u32 inq_vpd_sz) + { + MPT_FRAME_HDR *mf = NULL; + MPIHeader_t *mpi_hdr; +@@ -3389,7 +3379,7 @@ + u16 req_idx; + char *psge; + u8 inq_vpd_cdb[6]; +- u8 *request_data = NULL; ++ u8 *request_data=NULL; + dma_addr_t request_data_dma; + u32 request_data_sz; + int rc = 0; +@@ -3419,14 +3409,14 @@ + pScsiRequest = (pSCSIIORequest_t) mf; + req_idx = le16_to_cpu(mf->u.frame.hwhdr.msgctxu.fld.req_idx); + +- memset(pScsiRequest, 0, sizeof(SCSIIORequest_t)); ++ memset(pScsiRequest,0,sizeof(SCSIIORequest_t)); + pScsiRequest->Function = opcode; + pScsiRequest->TargetID = id; + pScsiRequest->Bus = bus; + pScsiRequest->CDBLength = 6; + pScsiRequest->DataLength = cpu_to_le32(request_data_sz); + pScsiRequest->MsgContext = MsgContext; +- memcpy(pScsiRequest->CDB, inq_vpd_cdb, pScsiRequest->CDBLength); ++ memcpy(pScsiRequest->CDB,inq_vpd_cdb,pScsiRequest->CDBLength); + pScsiRequest->Control = cpu_to_le32(MPI_SCSIIO_CONTROL_READ); + pScsiRequest->Control |= cpu_to_le32(MPI_SCSIIO_CONTROL_SIMPLEQ); + pScsiRequest->MsgFlags &= ~MPI_SCSIIO_MSGFLGS_SENSE_WIDTH; +@@ -3444,18 +3434,17 @@ + + if (request_data == NULL) { + mpt_free_msg_frame(ioc, mf); +- rc = -1; ++ rc=-1; + goto csmisas_raid_inq_exit; + } + +- memset(request_data, 0, request_data_sz); ++ memset(request_data,0,request_data_sz); + psge = (char *)&pScsiRequest->SGL; + ioc->add_sge(psge, (MPT_SGE_FLAGS_SSIMPLE_READ | 0xFC) , + request_data_dma); + +- if (csmisas_send_command_wait(ioc, mf, MPT_IOCTL_DEFAULT_TIMEOUT) +- != 0) { +- rc = -1; ++ if (csmisas_send_command_wait(ioc, mf, MPT_IOCTL_DEFAULT_TIMEOUT) != 0) { ++ rc=-1; + goto csmisas_raid_inq_exit; + } + +@@ -3483,7 +3472,7 @@ + csmisas_get_raid_config(unsigned long arg) + { + CSMI_SAS_RAID_CONFIG_BUFFER __user *uarg = (void __user *) arg; +- CSMI_SAS_RAID_CONFIG_BUFFER karg, *pKarg = NULL; ++ CSMI_SAS_RAID_CONFIG_BUFFER karg,*pKarg=NULL; + CONFIGPARMS cfg; + ConfigPageHeader_t header; + MPT_ADAPTER *ioc = NULL; +@@ -3509,7 +3498,7 @@ + if (copy_from_user(&karg, uarg, sizeof(IOCTL_HEADER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmisas_get_raid_config struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + return -EFAULT; + } + +@@ -3517,11 +3506,11 @@ + memory_pages = get_order(csmi_sas_raid_config_buffer_sz); + pKarg = (CSMI_SAS_RAID_CONFIG_BUFFER *)__get_free_pages( + GFP_KERNEL, memory_pages); +- if (!pKarg) { ++ if (!pKarg){ + printk(KERN_ERR "%s@%d::%s() - " + "Unable to malloc RAID_CONFIG_BUFFER " + "csmi_sas_raid_config_buffer_sz=%d memory_pages=%d\n", +- __FILE__, __LINE__, __func__, ++ __FILE__, __LINE__, __FUNCTION__, + csmi_sas_raid_config_buffer_sz, memory_pages); + return -ENOMEM; + } +@@ -3530,7 +3519,7 @@ + if (copy_from_user(pKarg, uarg, csmi_sas_raid_config_buffer_sz)) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmisas_get_raid_config struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + free_pages((unsigned long)pKarg, memory_pages); + return -EFAULT; + } +@@ -3538,22 +3527,22 @@ + if (((iocnum = mpt_verify_adapter(pKarg->IoctlHeader.IOControllerNumber, + &ioc)) < 0) || (ioc == NULL)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)pKarg, memory_pages); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)pKarg, memory_pages); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)pKarg, memory_pages); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)pKarg, memory_pages); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + if (pKarg->Configuration.uChangeCount != 0 && +- pKarg->Configuration.uChangeCount != ioc->csmi_change_count) { ++ pKarg->Configuration.uChangeCount != ioc->csmi_change_count ) { + pKarg->IoctlHeader.ReturnCode = + CSMI_SAS_STATUS_INVALID_PARAMETER; + pKarg->Configuration.uFailureCode = +@@ -3626,7 +3615,7 @@ + pKarg->Configuration.uStripeSize = + le32_to_cpu(pVolume0->StripeSize)/2; + +- switch (pVolume0->VolumeType) { ++ switch(pVolume0->VolumeType) { + case MPI_RAID_VOL_TYPE_IS: + pKarg->Configuration.bRaidType = CSMI_SAS_RAID_TYPE_0; + break; +@@ -3647,8 +3636,7 @@ + break; + case MPI_RAIDVOL0_STATUS_STATE_DEGRADED: + /* Volume is degraded, check if Resyncing or Inactive */ +- pKarg->Configuration.bStatus +- = CSMI_SAS_RAID_SET_STATUS_DEGRADED; ++ pKarg->Configuration.bStatus = CSMI_SAS_RAID_SET_STATUS_DEGRADED; + break; + case MPI_RAIDVOL0_STATUS_STATE_FAILED: + pKarg->Configuration.bStatus = CSMI_SAS_RAID_SET_STATUS_FAILED; +@@ -3661,26 +3649,25 @@ + pKarg->Configuration.bStatus = CSMI_SAS_RAID_SET_STATUS_OFFLINE; + else if (pVolume0->VolumeStatus.Flags & + MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS) +- pKarg->Configuration.bStatus +- = CSMI_SAS_RAID_SET_STATUS_REBUILDING; ++ pKarg->Configuration.bStatus = CSMI_SAS_RAID_SET_STATUS_REBUILDING; + + pKarg->Configuration.bInformation = 0; /* default */ +- if (pVolume0->VolumeStatus.Flags & +- MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS) { +- +- uint64_t *ptrUint64; ++ if(pVolume0->VolumeStatus.Flags & ++ MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS ) { ++ ++ uint64_t * ptrUint64; + uint64_t totalBlocks64, blocksRemaining64; + uint32_t totalBlocks32, blocksRemaining32; + + /* get percentage complete */ +- pRaidActionReply = kmalloc(sizeof(MPI_RAID_VOL_INDICATOR) + +- offsetof(MSG_RAID_ACTION_REPLY, ActionData), ++ pRaidActionReply = kmalloc( sizeof(MPI_RAID_VOL_INDICATOR) + ++ offsetof(MSG_RAID_ACTION_REPLY,ActionData), + GFP_KERNEL); + +- if (!pRaidActionReply) { ++ if (!pRaidActionReply){ + printk(KERN_ERR "%s@%d::%s() - " + "Unable to malloc @ %p\n", +- __FILE__, __LINE__, __func__, pKarg); ++ __FILE__, __LINE__, __FUNCTION__,pKarg); + goto cim_get_raid_config_exit; + } + memset(pRaidActionReply, 0, sizeof(*pRaidActionReply)); +@@ -3693,14 +3680,14 @@ + totalBlocks64 = *ptrUint64; + ptrUint64++; + blocksRemaining64 = *ptrUint64; +- while (totalBlocks64 > 0xFFFFFFFFUL) { ++ while(totalBlocks64 > 0xFFFFFFFFUL){ + totalBlocks64 = totalBlocks64 >> 1; + blocksRemaining64 = blocksRemaining64 >> 1; + } + totalBlocks32 = (uint32_t)totalBlocks64; + blocksRemaining32 = (uint32_t)blocksRemaining64; + +- if (totalBlocks32) ++ if(totalBlocks32) + pKarg->Configuration.bInformation = + (totalBlocks32 - blocksRemaining32) / + (totalBlocks32 / 100); +@@ -3726,14 +3713,15 @@ + pKarg->Configuration.Data->ulRaidSetBlocks.uHighPart = + le32_to_cpu(pVolume0->MaxLBAHigh); + if (pVolume0->VolumeType == MPI_RAID_VOL_TYPE_IS || +- pVolume0->VolumeType == MPI_RAID_VOL_TYPE_IME) { ++ pVolume0->VolumeType == MPI_RAID_VOL_TYPE_IME ) { + pKarg->Configuration.Data->uStripeSizeInBlocks = + le32_to_cpu(pVolume0->StripeSize); + } else { + pKarg->Configuration.Data->uStripeSizeInBlocks = 0; + } + pKarg->Configuration.Data->uSectorsPerTrack = 128; +- for (i = 0; i < 16; i++) { ++ for (i=0; i<16; i++) { ++ // unsupported + pKarg->Configuration.Data->bApplicationScratchPad[i] = + 0xFF; + } +@@ -3744,15 +3732,15 @@ + (pKarg->Configuration.Data->uNumberOfHeads * + pKarg->Configuration.Data->uSectorsPerTrack)); + pKarg->Configuration.Data->uNumberOfTracks = tmpTotalMaxLBA; +- } else if (pKarg->Configuration.bDataType == +- CSMI_SAS_RAID_DATA_DEVICE_ID) { ++ } else if ( pKarg->Configuration.bDataType == ++ CSMI_SAS_RAID_DATA_DEVICE_ID ) { + /* Send inquiry to get VPD Page 0x83 */ + u32 vpd_page_sz; + vpd_page_sz = csmi_sas_raid_config_buffer_sz - +- offsetof(CSMI_SAS_RAID_CONFIG, DeviceId); ++ offsetof(CSMI_SAS_RAID_CONFIG,DeviceId); + if (csmisas_raid_inq(ioc, MPI_FUNCTION_SCSI_IO_REQUEST, + VolumeBus, volumeID, 0x83, +- (u8 *)&pKarg->Configuration.DeviceId->bDeviceIdentificationVPDPage, ++ (u8*)&pKarg->Configuration.DeviceId->bDeviceIdentificationVPDPage, + vpd_page_sz) != 0) { + pKarg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_get_raid_config_exit; +@@ -3785,7 +3773,7 @@ + pIocPage5 = pci_alloc_consistent(ioc->pcidev, + ioc_page5_sz, + &ioc_page5_dma); +- memset(pIocPage5, 0, ioc_page5_sz); ++ memset(pIocPage5,0,ioc_page5_sz); + if (ioc_page5_dma) { + cfg.physAddr = ioc_page5_dma; + cfg.action = +@@ -3828,55 +3816,52 @@ + cfg.physAddr = physdisk0_dma; + + physDiskNumMax = (csmi_sas_raid_config_buffer_sz - +- offsetof(CSMI_SAS_RAID_CONFIG, Drives)) ++ offsetof(CSMI_SAS_RAID_CONFIG,Drives)) + / sizeof(CSMI_SAS_RAID_DRIVES); + + tmpTotalMaxLBA = totalMaxLBA; + if (pVolume0->VolumeType == MPI_RAID_VOL_TYPE_IS) { + do_div(tmpTotalMaxLBA, pVolume0->NumPhysDisks); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "IS Volume tmpTotalMaxLBA=%llX\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "IS Volume tmpTotalMaxLBA=%llX\n", + (unsigned long long)tmpTotalMaxLBA)); +- } else if (pVolume0->VolumeType == MPI_RAID_VOL_TYPE_IME) { ++ } ++ else if (pVolume0->VolumeType == MPI_RAID_VOL_TYPE_IME) { + do_div(tmpTotalMaxLBA, pVolume0->NumPhysDisks * 2); +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "IME Volume tmpTotalMaxLBA=%llX\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "IME Volume tmpTotalMaxLBA=%llX\n", + (unsigned long long)tmpTotalMaxLBA)); + } else { +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "IM Volume tmpTotalMaxLBA=%llX\n", ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "IM Volume tmpTotalMaxLBA=%llX\n", + (unsigned long long)tmpTotalMaxLBA)); + } + +- for (i = 0; i < min(pVolume0->NumPhysDisks, physDiskNumMax); i++) { ++ for (i=0; i< min(pVolume0->NumPhysDisks, physDiskNumMax); i++) { + + physDiskNum = pVolume0->PhysDisk[i].PhysDiskNum; + cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; + cfg.pageAddr = physDiskNum; +- if (mpt_config(ioc, &cfg) != 0) { ++ if (mpt_config(ioc, &cfg) != 0){ + pKarg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_get_raid_config_exit; + } + +- pKarg->Configuration.bDriveCount++; ++ pKarg->Configuration.bDriveCount++; + if (pKarg->Configuration.bDataType != CSMI_SAS_RAID_DATA_DRIVES) + continue; + + /* Search the list for the matching SAS address. */ +- sas_info = csmisas_get_device_component_by_fw(ioc, +- pPhysDisk0->PhysDiskBus, pPhysDisk0->PhysDiskID); ++ sas_info = csmisas_get_device_component_by_fw(ioc, pPhysDisk0->PhysDiskBus, ++ pPhysDisk0->PhysDiskID); + if (sas_info) { +- sas_address +- = reverse_byte_order64(sas_info->sas_address); ++ sas_address = reverse_byte_order64(sas_info->sas_address); + memcpy(pKarg->Configuration.Drives[i].bSASAddress, +- &sas_address, sizeof(u64)); ++ &sas_address,sizeof(u64)); + if (!device_info) + device_info = sas_info->device_info; + } + + memcpy(pKarg->Configuration.Drives[i].bModel, + pPhysDisk0->InquiryData.VendorID, +- offsetof(RAID_PHYS_DISK0_INQUIRY_DATA, ProductRevLevel)); ++ offsetof(RAID_PHYS_DISK0_INQUIRY_DATA,ProductRevLevel)); + memcpy(pKarg->Configuration.Drives[i].bFirmware, + pPhysDisk0->InquiryData.ProductRevLevel, + sizeof(pPhysDisk0->InquiryData.ProductRevLevel)); +@@ -3905,19 +3890,19 @@ + MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED) { + pKarg->Configuration.Drives[i].bDriveStatus = + CSMI_SAS_DRIVE_STATUS_OFFLINE; +- } else if (pPhysDisk0->PhysDiskStatus.State) { ++ } else if(pPhysDisk0->PhysDiskStatus.State) { + pKarg->Configuration.Drives[i].bDriveStatus = + CSMI_SAS_DRIVE_STATUS_FAILED; +- if (pKarg->Configuration.bStatus == ++ if(pKarg->Configuration.bStatus == + CSMI_SAS_RAID_SET_STATUS_DEGRADED) + pKarg->Configuration.bInformation = i; +- } else if ((pVolume0->VolumeStatus.Flags & ++ } else if((pVolume0->VolumeStatus.Flags & + MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS) && + (pPhysDisk0->PhysDiskStatus.Flags & + MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC)) + pKarg->Configuration.Drives[i].bDriveStatus = + CSMI_SAS_DRIVE_STATUS_REBUILDING; +- else if (pPhysDisk0->ErrorData.SmartCount || ++ else if(pPhysDisk0->ErrorData.SmartCount || + (pPhysDisk0->PhysDiskStatus.Flags & + MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC)) + pKarg->Configuration.Drives[i].bDriveStatus = +@@ -3933,7 +3918,7 @@ + CSMI_SAS_DRIVE_TYPE_SINGLE_PORT_SAS; + if (mpt_raid_phys_disk_get_num_paths(ioc, + pVolume0->PhysDisk[i].PhysDiskNum) > 1) +- pKarg->Configuration.Drives[i].bDriveType = ++ pKarg->Configuration.Drives[i].bDriveType = + CSMI_SAS_DRIVE_TYPE_DUAL_PORT_SAS; + } + +@@ -3956,9 +3941,9 @@ + if ((pVolume0->VolumeSettings.HotSparePool & + pIocPage5->HotSpare[idx].HotSparePool) == 0) + continue; +- if (pIocPage5->HotSpare[idx].Flags != ++ if(pIocPage5->HotSpare[idx].Flags != + MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE) +- continue; ++ continue; + physDiskNum = pIocPage5->HotSpare[idx].PhysDiskNum; + cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; + cfg.pageAddr = physDiskNum; +@@ -3996,11 +3981,11 @@ + MPI_RAID_VOL_TYPE_IME) && + (((totalMaxLBA + + pVolume0->NumPhysDisks) * 2) + +- (64*2*1024) /*metadata = 64MB*/ > ++ (64*2*1024 ) /*metadata = 64MB*/ > + le32_to_cpu(pPhysDisk0->MaxLBA))) + continue; + +- pKarg->Configuration.bDriveCount++; ++ pKarg->Configuration.bDriveCount++; + if (pKarg->Configuration.bDataType != + CSMI_SAS_RAID_DATA_DRIVES) { + i++; +@@ -4011,16 +3996,14 @@ + sas_info = csmisas_get_device_component_by_fw(ioc, + pPhysDisk0->PhysDiskBus, pPhysDisk0->PhysDiskID); + if (sas_info) { +- sas_address = +- reverse_byte_order64(sas_info->sas_address); ++ sas_address = reverse_byte_order64(sas_info->sas_address); + memcpy(pKarg->Configuration.Drives[i].bSASAddress, +- &sas_address, sizeof(u64)); ++ &sas_address,sizeof(u64)); + } + + memcpy(pKarg->Configuration.Drives[i].bModel, + pPhysDisk0->InquiryData.VendorID, +- offsetof(RAID_PHYS_DISK0_INQUIRY_DATA, +- ProductRevLevel)); ++ offsetof(RAID_PHYS_DISK0_INQUIRY_DATA,ProductRevLevel)); + memcpy(pKarg->Configuration.Drives[i].bFirmware, + pPhysDisk0->InquiryData.ProductRevLevel, + sizeof(pPhysDisk0->InquiryData.ProductRevLevel)); +@@ -4038,10 +4021,10 @@ + } + pKarg->Configuration.Drives[i].bDriveStatus = + CSMI_SAS_DRIVE_STATUS_OK; +- if (pPhysDisk0->PhysDiskStatus.State) ++ if(pPhysDisk0->PhysDiskStatus.State) + pKarg->Configuration.Drives[i].bDriveStatus = + CSMI_SAS_DRIVE_STATUS_FAILED; +- else if (pPhysDisk0->ErrorData.SmartCount) ++ else if(pPhysDisk0->ErrorData.SmartCount) + pKarg->Configuration.Drives[i].bDriveStatus = + CSMI_SAS_DRIVE_STATUS_DEGRADED; + pKarg->Configuration.Drives[i].bDriveUsage = +@@ -4064,8 +4047,8 @@ + } + } + +- /* Only return data on the first 240 drives */ +- if (pKarg->Configuration.bDriveCount > 0xF0) ++ // Only return data on the first 240 drives ++ if( pKarg->Configuration.bDriveCount > 0xF0 ) + pKarg->Configuration.bDriveCount = + CSMI_SAS_RAID_DRIVE_COUNT_TOO_BIG; + +@@ -4077,11 +4060,11 @@ + pci_free_consistent(ioc->pcidev, volumepage0sz, pVolume0, + volume0_dma); + +- if (pPhysDisk0 != NULL) ++ if(pPhysDisk0 != NULL) + pci_free_consistent(ioc->pcidev, physdiskpage0sz, pPhysDisk0, + physdisk0_dma); + +- if (pIocPage5 != NULL) ++ if(pIocPage5 != NULL) + pci_free_consistent(ioc->pcidev, ioc_page5_sz, pIocPage5, + ioc_page5_dma); + +@@ -4092,17 +4075,17 @@ + switch (pKarg->Configuration.bDataType) { + case CSMI_SAS_RAID_DATA_ADDITIONAL_DATA: + copy_buffer_sz = sizeof(IOCTL_HEADER) + +- offsetof(CSMI_SAS_RAID_CONFIG, Data) + ++ offsetof(CSMI_SAS_RAID_CONFIG,Data) + + sizeof(CSMI_SAS_RAID_SET_ADDITIONAL_DATA); + break; + case CSMI_SAS_RAID_DATA_DRIVES: + if (pKarg->Configuration.bDriveCount == + CSMI_SAS_RAID_DRIVE_COUNT_SUPRESSED) + copy_buffer_sz = sizeof(IOCTL_HEADER) + +- offsetof(CSMI_SAS_RAID_CONFIG, Drives); +- else ++ offsetof(CSMI_SAS_RAID_CONFIG,Drives); ++ else + copy_buffer_sz = sizeof(IOCTL_HEADER) + +- offsetof(CSMI_SAS_RAID_CONFIG, Drives) + ++ offsetof(CSMI_SAS_RAID_CONFIG,Drives) + + (pKarg->Configuration.bDriveCount * + sizeof(CSMI_SAS_RAID_DRIVES)); + break; +@@ -4114,12 +4097,12 @@ + if (copy_to_user(uarg, pKarg, copy_buffer_sz)) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_get_raid_config @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- free_pages((unsigned long)pKarg, memory_pages); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ free_pages((unsigned long)pKarg, memory_pages); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + free_pages((unsigned long)pKarg, memory_pages); + return 0; + } +@@ -4136,15 +4119,15 @@ + csmisas_get_raid_features(unsigned long arg) + { + CSMI_SAS_RAID_FEATURES_BUFFER __user *uarg = (void __user *) arg; +- CSMI_SAS_RAID_FEATURES_BUFFER karg, *pKarg = NULL; ++ CSMI_SAS_RAID_FEATURES_BUFFER karg, *pKarg=NULL; + int csmi_sas_raid_features_buffer_sz, iocnum; + int memory_pages; + MPT_ADAPTER *ioc = NULL; + + if (copy_from_user(&karg, uarg, sizeof(IOCTL_HEADER))) { +- printk(KERN_ERR "%s@%d::%s() - Unable to " +- "read in csmi_sas_get_raid_features struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ printk(KERN_ERR "%s@%d::%s() - " ++ "Unable to read in csmi_sas_get_raid_features struct @ %p\n", ++ __FILE__, __LINE__, __FUNCTION__, uarg); + return -EFAULT; + } + +@@ -4152,20 +4135,20 @@ + memory_pages = get_order(csmi_sas_raid_features_buffer_sz); + pKarg = (CSMI_SAS_RAID_FEATURES_BUFFER *)__get_free_pages( + GFP_KERNEL, memory_pages); +- if (!pKarg) { ++ if (!pKarg){ + printk(KERN_ERR "%s@%d::%s() - " + "Unable to malloc RAID_FEATURES_BUFFER " + "csmi_sas_raid_features_buffer_sz=%d memory_pages=%d\n", +- __FILE__, __LINE__, __func__, ++ __FILE__, __LINE__, __FUNCTION__, + csmi_sas_raid_features_buffer_sz, memory_pages); + return -ENOMEM; + } + memset(pKarg, 0, sizeof(*pKarg)); + + if (copy_from_user(pKarg, uarg, csmi_sas_raid_features_buffer_sz)) { +- printk(KERN_ERR "%s@%d::%s() - Unable to " +- "read in csmi_sas_get_raid_features struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ printk(KERN_ERR "%s@%d::%s() - " ++ "Unable to read in csmi_sas_get_raid_features struct @ %p\n", ++ __FILE__, __LINE__, __FUNCTION__, uarg); + free_pages((unsigned long)pKarg, memory_pages); + return -EFAULT; + } +@@ -4173,22 +4156,22 @@ + if (((iocnum = mpt_verify_adapter(pKarg->IoctlHeader.IOControllerNumber, + &ioc)) < 0) || (ioc == NULL)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)pKarg, memory_pages); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)pKarg, memory_pages); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)pKarg, memory_pages); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)pKarg, memory_pages); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + if (pKarg->Information.uChangeCount != 0 && +- pKarg->Information.uChangeCount != ioc->csmi_change_count) { ++ pKarg->Information.uChangeCount != ioc->csmi_change_count ) { + pKarg->IoctlHeader.ReturnCode = + CSMI_SAS_STATUS_INVALID_PARAMETER; + pKarg->Information.uFailureCode = +@@ -4235,12 +4218,12 @@ + sizeof(CSMI_SAS_RAID_FEATURES_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_get_raid_features @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- free_pages((unsigned long)pKarg, memory_pages); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ free_pages((unsigned long)pKarg, memory_pages); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + free_pages((unsigned long)pKarg, memory_pages); + return 0; + } +@@ -4257,7 +4240,7 @@ + csmisas_set_raid_control(unsigned long arg) + { + CSMI_SAS_RAID_CONTROL_BUFFER __user *uarg = (void __user *) arg; +- CSMI_SAS_RAID_CONTROL_BUFFER karg, *pKarg = NULL; ++ CSMI_SAS_RAID_CONTROL_BUFFER karg, *pKarg=NULL; + int csmi_sas_raid_control_buffer_sz, iocnum; + int memory_pages; + MPT_ADAPTER *ioc = NULL; +@@ -4265,7 +4248,7 @@ + if (copy_from_user(&karg, uarg, sizeof(IOCTL_HEADER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_set_raid_control struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + return -EFAULT; + } + +@@ -4273,11 +4256,11 @@ + memory_pages = get_order(csmi_sas_raid_control_buffer_sz); + pKarg = (CSMI_SAS_RAID_CONTROL_BUFFER *)__get_free_pages( + GFP_KERNEL, memory_pages); +- if (!pKarg) { ++ if (!pKarg){ + printk(KERN_ERR "%s@%d::%s() - " + "Unable to malloc RAID_CONTROL_BUFFER " + "csmi_sas_raid_control_buffer_sz=%d memory_pages=%d\n", +- __FILE__, __LINE__, __func__, ++ __FILE__, __LINE__, __FUNCTION__, + csmi_sas_raid_control_buffer_sz, memory_pages); + return -ENOMEM; + } +@@ -4286,7 +4269,7 @@ + if (copy_from_user(pKarg, uarg, csmi_sas_raid_control_buffer_sz)) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_set_raid_control struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + free_pages((unsigned long)pKarg, memory_pages); + return -EFAULT; + } +@@ -4294,22 +4277,22 @@ + if (((iocnum = mpt_verify_adapter(pKarg->IoctlHeader.IOControllerNumber, + &ioc)) < 0) || (ioc == NULL)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)pKarg, memory_pages); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)pKarg, memory_pages); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)pKarg, memory_pages); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)pKarg, memory_pages); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + if (pKarg->Information.uChangeCount != 0 && +- pKarg->Information.uChangeCount != ioc->csmi_change_count) { ++ pKarg->Information.uChangeCount != ioc->csmi_change_count ) { + pKarg->IoctlHeader.ReturnCode = + CSMI_SAS_STATUS_INVALID_PARAMETER; + pKarg->Information.uFailureCode = +@@ -4346,8 +4329,8 @@ + goto cim_set_raid_control_exit; + } + +- if (!strcmp(pKarg->Information.bClearConfiguration, +- CSMI_SAS_RAID_CLEAR_CONFIGURATION_SIGNATURE)) { ++ if( !strcmp(pKarg->Information.bClearConfiguration, ++ CSMI_SAS_RAID_CLEAR_CONFIGURATION_SIGNATURE) ) { + pKarg->IoctlHeader.ReturnCode = + CSMI_SAS_STATUS_INVALID_PARAMETER; + pKarg->Information.uFailureCode = +@@ -4366,12 +4349,12 @@ + sizeof(CSMI_SAS_RAID_CONTROL_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_set_raid_control @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- free_pages((unsigned long)pKarg, memory_pages); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ free_pages((unsigned long)pKarg, memory_pages); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + free_pages((unsigned long)pKarg, memory_pages); + return 0; + } +@@ -4395,39 +4378,42 @@ + if (copy_from_user(&karg, uarg, sizeof(CSMI_SAS_RAID_ELEMENT_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmisas_get_raid_element struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); +- ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); ++ ++/* TODO - implement IOCTL here */ + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_BAD_CNTL_CODE; + dcsmisasprintk(ioc, printk(KERN_DEBUG ": not implemented\n")); + ++// csmisas_get_raid_element_exit: ++ + /* Copy the data from kernel memory to user memory + */ + if (copy_to_user(uarg, &karg, + sizeof(CSMI_SAS_RAID_ELEMENT_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmisas_get_raid_element @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + + } +@@ -4448,43 +4434,45 @@ + MPT_ADAPTER *ioc = NULL; + int iocnum; + +- if (copy_from_user(&karg, uarg, +- sizeof(CSMI_SAS_RAID_SET_OPERATION_BUFFER))) { ++ if (copy_from_user(&karg, uarg, sizeof(CSMI_SAS_RAID_SET_OPERATION_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_set_raid_operation struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); +- ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); ++ ++/* TODO - implement IOCTL here */ + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_BAD_CNTL_CODE; + dcsmisasprintk(ioc, printk(KERN_DEBUG ": not implemented\n")); + ++// cim_set_raid_operation: ++ + /* Copy the data from kernel memory to user memory + */ + if (copy_to_user(uarg, &karg, + sizeof(CSMI_SAS_RAID_SET_OPERATION_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_set_raid_operation @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + + } +@@ -4524,24 +4512,24 @@ + if (copy_from_user(&karg, uarg, sizeof(CSMI_SAS_SSP_TASK_IU_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_task_managment struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_INVALID_PARAMETER; + +@@ -4587,22 +4575,18 @@ + goto cim_get_task_managment_exit; + + switch (karg.Parameters.uInformation) { +- case CSMI_SAS_SSP_TEST: +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "TM request for test purposes\n")); +- break; +- case CSMI_SAS_SSP_EXCEEDED: +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "TM request due to timeout\n")); +- break; +- case CSMI_SAS_SSP_DEMAND: +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "TM request demanded by app\n")); +- break; +- case CSMI_SAS_SSP_TRIGGER: +- dcsmisasprintk(ioc, printk(KERN_DEBUG +- "TM request sent to trigger event\n")); +- break; ++ case CSMI_SAS_SSP_TEST: ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "TM request for test purposes\n")); ++ break; ++ case CSMI_SAS_SSP_EXCEEDED: ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "TM request due to timeout\n")); ++ break; ++ case CSMI_SAS_SSP_DEMAND: ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "TM request demanded by app\n")); ++ break; ++ case CSMI_SAS_SSP_TRIGGER: ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "TM request sent to trigger event\n")); ++ break; + } + + switch (taskType) { +@@ -4617,12 +4601,12 @@ + mf = MPT_INDEX_2_MFPTR(hd->ioc, i); + TaskMsgContext = + mf->u.frame.hwhdr.msgctxu.MsgContext; +- found_qtag = 1; ++ found_qtag=1; + break; + } + } + +- if (!found_qtag) ++ if(!found_qtag) + goto cim_get_task_managment_exit; + + case MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: +@@ -4634,6 +4618,7 @@ + + /* Single threading .... + */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,15)) + mutex_lock(&ioc->taskmgmt_cmds.mutex); + if (mpt_set_taskmgmt_in_progress_flag(ioc) != 0) { + mutex_unlock(&ioc->taskmgmt_cmds.mutex); +@@ -4641,34 +4626,50 @@ + CSMI_SAS_STATUS_FAILED; + goto cim_get_task_managment_exit; + } ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)) ++ if (mptctl_set_tm_flags(hd) != 0) { ++ karg.IoctlHeader.ReturnCode = ++ CSMI_SAS_STATUS_FAILED; ++ goto cim_get_task_managment_exit; ++ } ++#endif + /* Send request + */ + if ((mf = mpt_get_msg_frame(mptctl_taskmgmt_id, ioc)) == NULL) { +- dcsmisasprintk(ioc, +- printk(KERN_ERR ": no msg frames!\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": no msg frames!\n")); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,15)) + mutex_unlock(&ioc->taskmgmt_cmds.mutex); + mpt_clear_taskmgmt_in_progress_flag(ioc); ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)) ++ mptctl_free_tm_flags(ioc); ++#endif + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_get_task_managment_exit; + } + + mpi_hdr = (MPIHeader_t *) mf; + MsgContext = mpi_hdr->MsgContext; +- pScsiTm = (pSCSITaskMgmt_t) mf; +- +- memset(pScsiTm, 0, sizeof(SCSITaskMgmt_t)); ++ pScsiTm = (pSCSITaskMgmt_t ) mf; ++ ++ memset(pScsiTm,0,sizeof(SCSITaskMgmt_t)); + pScsiTm->TaskType = taskType; + pScsiTm->Bus = channel; + pScsiTm->TargetID = id; ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,15)) + int_to_scsilun(karg.Parameters.bLun, + (struct scsi_lun *)pScsiTm->LUN); ++#else ++ pScsiTm->LUN[1] = karg.Parameters.bLun; ++#endif + pScsiTm->MsgContext = MsgContext; + pScsiTm->TaskMsgContext = TaskMsgContext; + pScsiTm->Function = MPI_FUNCTION_SCSI_TASK_MGMT; + + if (csmisas_send_handshake_wait(ioc, mf, + karg.IoctlHeader.Timeout) != 0) { ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,15)) + mutex_unlock(&ioc->taskmgmt_cmds.mutex); ++#endif + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_get_task_managment_exit; + } +@@ -4676,26 +4677,25 @@ + if (ioc->ioctl_cmds.status & MPT_MGMT_STATUS_RF_VALID) { + + pScsiTmReply = +- (pSCSITaskMgmtReply_t) ioc->ioctl_cmds.reply; ++ (pSCSITaskMgmtReply_t ) ioc->ioctl_cmds.reply; + + ioc_status = le16_to_cpu(pScsiTmReply->IOCStatus) + & MPI_IOCSTATUS_MASK; + +- memset(&karg.Status, 0, ++ memset(&karg.Status,0, + sizeof(CSMI_SAS_SSP_PASSTHRU_STATUS)); + +- if (ioc_status == MPI_IOCSTATUS_SUCCESS) { ++ if(ioc_status == MPI_IOCSTATUS_SUCCESS) { + karg.IoctlHeader.ReturnCode = + CSMI_SAS_STATUS_SUCCESS; + karg.Status.bSSPStatus = + CSMI_SAS_SSP_STATUS_COMPLETED; +- } else if (ioc_status +- == MPI_IOCSTATUS_INSUFFICIENT_RESOURCES) { ++ }else if(ioc_status == MPI_IOCSTATUS_INSUFFICIENT_RESOURCES) { + karg.IoctlHeader.ReturnCode = + CSMI_SAS_STATUS_SUCCESS; + karg.Status.bSSPStatus = + CSMI_SAS_SSP_STATUS_RETRY; +- } else { ++ }else { + karg.IoctlHeader.ReturnCode = + CSMI_SAS_STATUS_FAILED; + karg.Status.bSSPStatus = +@@ -4711,7 +4711,9 @@ + break; + } + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,15)) + mutex_unlock(&ioc->taskmgmt_cmds.mutex); ++#endif + + cim_get_task_managment_exit: + +@@ -4721,11 +4723,11 @@ + sizeof(CSMI_SAS_SSP_TASK_IU_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_task_managment @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + } + +@@ -4825,19 +4827,19 @@ + + if ((opcode != MPI_SAS_OP_PHY_LINK_RESET) && + (opcode != MPI_SAS_OP_PHY_HARD_RESET)) ++ return -1; ++ ++ /* Get a MF for this command. ++ */ ++ if ((mf = mpt_get_msg_frame(mptctl_id, ioc)) == NULL) { ++ dcsmisasprintk(ioc, printk(KERN_ERR ": no msg frames!\n")); + return -1; +- +- /* Get a MF for this command. +- */ +- if ((mf = mpt_get_msg_frame(mptctl_id, ioc)) == NULL) { +- dcsmisasprintk(ioc, printk(KERN_ERR ": no msg frames!\n")); +- return -1; +- } ++ } + + mpi_hdr = (MPIHeader_t *) mf; + MsgContext = mpi_hdr->MsgContext; + sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf; +- memset(sasIoUnitCntrReq, 0, sizeof(SasIoUnitControlRequest_t)); ++ memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t)); + sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL; + sasIoUnitCntrReq->MsgContext = MsgContext; + sasIoUnitCntrReq->Operation = opcode; +@@ -4855,7 +4857,7 @@ + & MPI_IOCSTATUS_MASK; + if (ioc_status != MPI_IOCSTATUS_SUCCESS) { + printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n", +- __func__, ++ __FUNCTION__, + sasIoUnitCntrReply->IOCStatus, + sasIoUnitCntrReply->IOCLogInfo); + return -1; +@@ -4876,12 +4878,12 @@ + CSMI_SAS_PHY_CONTROL_BUFFER __user *uarg = (void __user *) arg; + IOCTL_HEADER ioctl_header; + PCSMI_SAS_PHY_CONTROL_BUFFER karg; +- SasIOUnitPage0_t *sasIoUnitPg0 = NULL; ++ SasIOUnitPage0_t *sasIoUnitPg0=NULL; + dma_addr_t sasIoUnitPg0_dma; +- int sasIoUnitPg0_data_sz = 0; +- SasIOUnitPage1_t *sasIoUnitPg1 = NULL; ++ int sasIoUnitPg0_data_sz=0; ++ SasIOUnitPage1_t *sasIoUnitPg1=NULL; + dma_addr_t sasIoUnitPg1_dma; +- int sasIoUnitPg1_data_sz = 0; ++ int sasIoUnitPg1_data_sz=0; + ConfigExtendedPageHeader_t hdr; + CONFIGPARMS cfg; + MPT_ADAPTER *ioc = NULL; +@@ -4892,7 +4894,7 @@ + if (copy_from_user(&ioctl_header, uarg, sizeof(IOCTL_HEADER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in IOCTL_HEADER" +- "struct @ %p\n", __FILE__, __LINE__, __func__, uarg); ++ "struct @ %p\n", __FILE__, __LINE__, __FUNCTION__, uarg); + return -EFAULT; + } + +@@ -4900,11 +4902,11 @@ + memory_pages = get_order(csmi_sas_phy_control_buffer_sz); + karg = (PCSMI_SAS_PHY_CONTROL_BUFFER)__get_free_pages( + GFP_KERNEL, memory_pages); +- if (!karg) { ++ if (!karg){ + printk(KERN_ERR "%s@%d::%s() - " + "Unable to malloc SAS_PHY_CONTROL_BUFFER " + "csmi_sas_phy_control_buffer_sz=%d memory_pages=%d\n", +- __FILE__, __LINE__, __func__, ++ __FILE__, __LINE__, __FUNCTION__, + csmi_sas_phy_control_buffer_sz, memory_pages); + return -ENOMEM; + } +@@ -4913,7 +4915,7 @@ + if (copy_from_user(karg, uarg, csmi_sas_phy_control_buffer_sz)) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_phy_control_buffer " +- "struct @ %p\n", __FILE__, __LINE__, __func__, uarg); ++ "struct @ %p\n", __FILE__, __LINE__, __FUNCTION__, uarg); + free_pages((unsigned long)karg, memory_pages); + return -EFAULT; + } +@@ -4921,19 +4923,19 @@ + if (((iocnum = mpt_verify_adapter(ioctl_header.IOControllerNumber, + &ioc)) < 0) || (ioc == NULL)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)karg, memory_pages); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)karg, memory_pages); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)karg, memory_pages); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)karg, memory_pages); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + if (karg->bPhyIdentifier >= ioc->num_ports) { + karg->IoctlHeader.ReturnCode = +@@ -4968,8 +4970,7 @@ + } + + if (hdr.ExtPageLength == 0) { +- dcsmisasprintk(ioc, +- printk(KERN_ERR ": hdr.ExtPageLength == 0\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": hdr.ExtPageLength == 0\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_sas_phy_control_exit; + } +@@ -4979,8 +4980,7 @@ + sasIoUnitPg0_data_sz, &sasIoUnitPg0_dma); + + if (!sasIoUnitPg0) { +- dcsmisasprintk(ioc, +- printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_sas_phy_control_exit; + } +@@ -5023,8 +5023,7 @@ + } + + if (hdr.ExtPageLength == 0) { +- dcsmisasprintk(ioc, +- printk(KERN_ERR ": hdr.ExtPageLength == 0\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": hdr.ExtPageLength == 0\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_sas_phy_control_exit; + } +@@ -5034,8 +5033,7 @@ + sasIoUnitPg1_data_sz, &sasIoUnitPg1_dma); + + if (!sasIoUnitPg1) { +- dcsmisasprintk(ioc, +- printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); ++ dcsmisasprintk(ioc, printk(KERN_ERR ": pci_alloc_consistent: FAILED\n")); + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_FAILED; + goto cim_sas_phy_control_exit; + } +@@ -5056,18 +5054,19 @@ + case CSMI_SAS_PC_LINK_RESET: + case CSMI_SAS_PC_HARD_RESET: + { +- u8 opcode = (karg->uFunction == CSMI_SAS_PC_LINK_RESET) ? ++ u8 opcode = (karg->uFunction==CSMI_SAS_PC_LINK_RESET) ? + MPI_SAS_OP_PHY_LINK_RESET : MPI_SAS_OP_PHY_HARD_RESET; + +- if ((karg->uLinkFlags & CSMI_SAS_PHY_ACTIVATE_CONTROL) && ++ if((karg->uLinkFlags & CSMI_SAS_PHY_ACTIVATE_CONTROL) && + (karg->usLengthOfControl >= sizeof(CSMI_SAS_PHY_CONTROL)) && +- (karg->bNumberOfControls > 0)) { +- if (karg->Control[0].bRate == ++ (karg->bNumberOfControls > 0)){ ++ if(karg->Control[0].bRate == + CSMI_SAS_LINK_RATE_1_5_GBPS) { + sasIoUnitPg1->PhyData[karg->bPhyIdentifier].MaxMinLinkRate = + MPI_SAS_IOUNIT1_MAX_RATE_1_5 | + MPI_SAS_IOUNIT1_MIN_RATE_1_5; +- } else if (karg->Control[0].bRate == ++ } ++ else if(karg->Control[0].bRate == + CSMI_SAS_LINK_RATE_3_0_GBPS) { + sasIoUnitPg1->PhyData[karg->bPhyIdentifier].MaxMinLinkRate = + MPI_SAS_IOUNIT1_MAX_RATE_3_0 | +@@ -5104,7 +5103,7 @@ + + } + case CSMI_SAS_PC_PHY_DISABLE: +- if (karg->usLengthOfControl || karg->bNumberOfControls) { ++ if(karg->usLengthOfControl || karg->bNumberOfControls) { + karg->IoctlHeader.ReturnCode = + CSMI_SAS_STATUS_INVALID_PARAMETER; + break; +@@ -5136,14 +5135,14 @@ + break; + + case CSMI_SAS_PC_GET_PHY_SETTINGS: +- if (karg->usLengthOfControl || karg->bNumberOfControls) { ++ if(karg->usLengthOfControl || karg->bNumberOfControls) { + karg->IoctlHeader.ReturnCode = + CSMI_SAS_STATUS_INVALID_PARAMETER; + break; + } +- if (csmi_sas_phy_control_buffer_sz < +- offsetof(CSMI_SAS_PHY_CONTROL_BUFFER, Control) + +- (4 * sizeof(CSMI_SAS_PHY_CONTROL))) { ++ if(csmi_sas_phy_control_buffer_sz < ++ offsetof(CSMI_SAS_PHY_CONTROL_BUFFER,Control) + ++ (4* sizeof(CSMI_SAS_PHY_CONTROL))) { + karg->IoctlHeader.ReturnCode = + CSMI_SAS_STATUS_INVALID_PARAMETER; + break; +@@ -5176,15 +5175,15 @@ + + /* Copy the data from kernel memory to user memory + */ +- if (copy_to_user(uarg, karg, csmi_sas_phy_control_buffer_sz)) { ++ if (copy_to_user(uarg, karg,csmi_sas_phy_control_buffer_sz)) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_phy_control_buffer @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- free_pages((unsigned long)karg, memory_pages); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ free_pages((unsigned long)karg, memory_pages); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + free_pages((unsigned long)karg, memory_pages); + return 0; + } +@@ -5203,8 +5202,7 @@ + * -EFAULT for non-successful reply or no reply (timeout) + **/ + static int +-csmisas_get_manuf_pg_7(MPT_ADAPTER *ioc, ManufacturingPage7_t *mfgpage7_buffer, +- int mfg_size) ++csmisas_get_manuf_pg_7(MPT_ADAPTER *ioc, ManufacturingPage7_t *mfgpage7_buffer, int mfg_size) + { + ConfigPageHeader_t hdr; + CONFIGPARMS cfg; +@@ -5283,41 +5281,41 @@ + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_connector_info_buffer" + " struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, +- &ioc)) < 0) || (ioc == NULL)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ if (((iocnum = mpt_verify_adapter(karg.IoctlHeader.IOControllerNumber, ++ &ioc)) < 0) || (ioc == NULL)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + karg.IoctlHeader.ReturnCode = CSMI_SAS_STATUS_SUCCESS; + + /* `32` is the sizeof MPI_MANPAGE7_CONNECTOR_INFO */ + for (i = 0; i < 32; i++) { + karg.Reference[i].uPinout = CSMI_SAS_CON_UNKNOWN; +- strcpy(karg.Reference[i].bConnector, ""); ++ strcpy(karg.Reference[i].bConnector,""); + karg.Reference[i].bLocation = CSMI_SAS_CON_UNKNOWN; + } + +- mfgPg7_sz = offsetof(CONFIG_PAGE_MANUFACTURING_7, ConnectorInfo) + ++ mfgPg7_sz = offsetof(CONFIG_PAGE_MANUFACTURING_7,ConnectorInfo) + + (ioc->num_ports * sizeof(MPI_MANPAGE7_CONNECTOR_INFO)); + mfgPg7 = kmalloc(mfgPg7_sz, GFP_KERNEL); +- if (!mfgPg7) { ++ if (!mfgPg7){ + printk(KERN_ERR "%s@%d::%s() - " + "Unable to malloc @ %p\n", +- __FILE__, __LINE__, __func__, mfgPg7); ++ __FILE__, __LINE__, __FUNCTION__, mfgPg7); + return -EFAULT; + } + memset(mfgPg7, 0, mfgPg7_sz); +@@ -5341,12 +5339,13 @@ + if (copy_to_user(uarg, &karg, + sizeof(CSMI_SAS_CONNECTOR_INFO_BUFFER))) { + printk(KERN_ERR "%s@%d::%s() - " +- "Unable to write out csmi_sas_connector_info_buffer @%p\n", +- __FILE__, __LINE__, __func__, uarg); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); ++ "Unable to write out csmi_sas_connector_info_buffer @" ++ "%p\n", ++ __FILE__, __LINE__, __FUNCTION__, uarg); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); + return 0; + } + +@@ -5358,21 +5357,21 @@ + **/ + static int + csmisas_fill_location_data(MPT_ADAPTER *ioc, u8 bus, u8 id, u8 opcode, +- CSMI_SAS_LOCATION_IDENTIFIER *location_ident) ++ CSMI_SAS_LOCATION_IDENTIFIER * location_ident) + { + + ConfigExtendedPageHeader_t hdr; + CONFIGPARMS cfg; + int rc; +- SasDevicePage0_t *sasDevicePg0 = NULL; +- SasEnclosurePage0_t *sasEnclosurePg0 = NULL; +- dma_addr_t sasDevicePg0_dma, sasEnclosurePg0_dma; +- int sasDevicePg0_data_sz = 0; +- int sasEnclosurePg0_data_sz = 0; +- u64 sas_address; +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); +- memset(location_ident, 0, sizeof(*location_ident)); ++ SasDevicePage0_t *sasDevicePg0=NULL; ++ SasEnclosurePage0_t *sasEnclosurePg0=NULL; ++ dma_addr_t sasDevicePg0_dma,sasEnclosurePg0_dma; ++ int sasDevicePg0_data_sz=0; ++ int sasEnclosurePg0_data_sz=0; ++ u64 sas_address; ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); ++ memset (location_ident, 0, sizeof(*location_ident)); + + /* SAS Device Page 0 */ + hdr.PageVersion = MPI_SASDEVICE0_PAGEVERSION; +@@ -5390,12 +5389,12 @@ + cfg.timeout = MPT_IOCTL_DEFAULT_TIMEOUT; + + if ((rc = mpt_config(ioc, &cfg)) != 0) { +- rc = -1; +- goto fill_location_data_exit; +- } +- +- if (hdr.ExtPageLength == 0) { +- rc = -1; ++ rc=-1; ++ goto fill_location_data_exit; ++ } ++ ++ if (hdr.ExtPageLength == 0) { ++ rc=-1; + goto fill_location_data_exit; + } + +@@ -5403,7 +5402,7 @@ + sasDevicePg0 = (SasDevicePage0_t *) pci_alloc_consistent( + ioc->pcidev, sasDevicePg0_data_sz, &sasDevicePg0_dma); + if (!sasDevicePg0) { +- rc = -1; ++ rc=-1; + goto fill_location_data_exit; + } + +@@ -5412,10 +5411,10 @@ + cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; + cfg.pageAddr = (bus << 8) + id + + (MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID << +- MPI_SAS_DEVICE_PGAD_FORM_SHIFT); +- +- if ((rc = mpt_config(ioc, &cfg)) != 0) { +- rc = -1; ++ MPI_SAS_DEVICE_PGAD_FORM_SHIFT); ++ ++ if ((rc = mpt_config(ioc, &cfg)) != 0) { ++ rc=-1; + goto fill_location_data_exit; + } + +@@ -5443,12 +5442,12 @@ + cfg.timeout = MPT_IOCTL_DEFAULT_TIMEOUT; + + if ((rc = mpt_config(ioc, &cfg)) != 0) { +- rc = 0; +- goto fill_location_data_exit; +- } +- +- if (hdr.ExtPageLength == 0) { +- rc = 0; ++ rc=0; ++ goto fill_location_data_exit; ++ } ++ ++ if (hdr.ExtPageLength == 0) { ++ rc=0; + goto fill_location_data_exit; + } + +@@ -5456,34 +5455,36 @@ + sasEnclosurePg0 = (SasEnclosurePage0_t *) pci_alloc_consistent( + ioc->pcidev, sasEnclosurePg0_data_sz, &sasEnclosurePg0_dma); + if (!sasEnclosurePg0) { +- rc = 0; ++ rc=0; + goto fill_location_data_exit; + } + cfg.physAddr = sasEnclosurePg0_dma; + cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; + cfg.pageAddr = sasDevicePg0->EnclosureHandle +- + (MPI_SAS_ENCLOS_PGAD_FORM_HANDLE << +- MPI_SAS_ENCLOS_PGAD_FORM_SHIFT); +- +- if ((rc = mpt_config(ioc, &cfg)) != 0) { +- rc = 0; +- goto fill_location_data_exit; +- } +- +- location_ident->bLocationFlags |= +- CSMI_SAS_LOCATE_ENCLOSURE_IDENTIFIER_VALID; ++ + (MPI_SAS_ENCLOS_PGAD_FORM_HANDLE << MPI_SAS_ENCLOS_PGAD_FORM_SHIFT); ++ ++ if ((rc = mpt_config(ioc, &cfg)) != 0) { ++ rc=0; ++ goto fill_location_data_exit; ++ } ++ ++ location_ident->bLocationFlags |= CSMI_SAS_LOCATE_ENCLOSURE_IDENTIFIER_VALID; + memcpy(&sas_address, &sasEnclosurePg0->EnclosureLogicalID, sizeof(u64)); + sas_address = reverse_byte_order64(sas_address); + if (sas_address) +- memcpy(location_ident->bEnclosureIdentifier, &sas_address, +- sizeof(u64)); +- else +- strcpy(location_ident->bEnclosureIdentifier, "Internal"); +- +-/* bBayPrefix - not supported */ +- ++ memcpy(location_ident->bEnclosureIdentifier, &sas_address, sizeof(u64)); ++ else ++ strcpy(location_ident->bEnclosureIdentifier,"Internal"); ++ ++// bBayPrefix - not supported ++ ++// TODO - We need to look at sasEnclosurePg0-.Flags , to determine ++// whether SEP BUS/TargetID is valid. Ifs its a SES device, then ++// issue internal inquiry to (bus/id) to gather the Enclosure name. ++// If the device is SMP, then issue SMP_MANUFACTURING to get enclosure name ++// If its direct attached, there is no enclosure name + location_ident->bLocationFlags |= CSMI_SAS_LOCATE_ENCLOSURE_NAME_VALID; +- strcpy(location_ident->bEnclosureName, "Not Supported"); ++ strcpy(location_ident->bEnclosureName,"Not Supported"); + + location_ident->bLocationFlags |= CSMI_SAS_LOCATE_LOCATION_STATE_VALID; + location_ident->bLocationState = CSMI_SAS_LOCATE_UNKNOWN; +@@ -5491,6 +5492,11 @@ + location_ident->bLocationFlags |= CSMI_SAS_LOCATE_BAY_IDENTIFIER_VALID; + location_ident->bBayIdentifier = le16_to_cpu(sasDevicePg0->Slot); + ++ ++// TODO - illuminating LEDs, ++// karg->bIdentify = CSMI_SAS_LOCATE_FORCE_OFF, CSMI_SAS_LOCATE_FORCE_ON ++// We can enable/disable LEDs by SCSI Enclosure Processor MPI request message ++// printk("Flags=0x%x\n",sasEnclosurePg0->Flags); + + /* check sasEnclosurePg0->Flags - + * to validate whether we need to send the SEPRequest +@@ -5521,13 +5527,13 @@ + pci_free_consistent(ioc->pcidev, sasEnclosurePg0_data_sz, + sasEnclosurePg0, sasEnclosurePg0_dma); + +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); +- return rc; +-} +- +-static int +-csmisas_fill_location_data_raid(MPT_ADAPTER *ioc, +- PCSMI_SAS_GET_LOCATION_BUFFER karg, u8 VolumeBus, u8 volumeID) ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); ++ return rc; ++} ++ ++static int ++csmisas_fill_location_data_raid(MPT_ADAPTER *ioc, PCSMI_SAS_GET_LOCATION_BUFFER karg, u8 VolumeBus, ++ u8 volumeID) + { + pRaidVolumePage0_t pVolume0 = NULL; + pRaidPhysDiskPage0_t pPhysDisk0 = NULL; +@@ -5548,9 +5554,9 @@ + + csmi_sas_get_location_sz = karg->IoctlHeader.Length; + physDiskNumMax = (csmi_sas_get_location_sz - +- offsetof(CSMI_SAS_GET_LOCATION_BUFFER, Location)) ++ offsetof(CSMI_SAS_GET_LOCATION_BUFFER,Location)) + / sizeof(CSMI_SAS_LOCATION_IDENTIFIER); +- karg->bNumberOfLocationIdentifiers = 0; ++ karg->bNumberOfLocationIdentifiers=0; + + /* + * get RAID Volume Page 0 +@@ -5586,7 +5592,7 @@ + + cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; + cfg.physAddr = volume0_dma; +- if (mpt_config(ioc, &cfg) != 0) { ++ if (mpt_config(ioc, &cfg) != 0){ + rc = -1; + goto sas_fill_location_data_raid_exit; + } +@@ -5626,17 +5632,17 @@ + } + cfg.physAddr = physdisk0_dma; + +- for (i = 0; i < min(pVolume0->NumPhysDisks, physDiskNumMax); i++) { ++ for (i=0; i < min(pVolume0->NumPhysDisks, physDiskNumMax); i++) { + + /* obtain a refresh of pPhysDisk0 */ + cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; + cfg.pageAddr = pVolume0->PhysDisk[i].PhysDiskNum; +- if (mpt_config(ioc, &cfg) != 0) { ++ if (mpt_config(ioc, &cfg) != 0){ + rc = -1; + goto sas_fill_location_data_raid_exit; + } + +- if ((csmisas_fill_location_data(ioc, pPhysDisk0->PhysDiskBus, ++ if((csmisas_fill_location_data(ioc, pPhysDisk0->PhysDiskBus, + pPhysDisk0->PhysDiskID, karg->bIdentify, + &karg->Location[karg->bNumberOfLocationIdentifiers])) == 0) + karg->bNumberOfLocationIdentifiers++; +@@ -5673,7 +5679,7 @@ + if (csmisas_get_ioc_pg5(ioc, iocPage5, sz) != 0) + goto sas_fill_location_data_raid_exit; + +- for (i = 0, idx = pVolume0->NumPhysDisks ; i < num_hotpares; ++ for(i = 0, idx = pVolume0->NumPhysDisks ; i < num_hotpares; + i++, idx++) { + + if (idx >= physDiskNumMax) +@@ -5722,11 +5728,11 @@ + if ((pVolume0->VolumeType == + MPI_RAID_VOL_TYPE_IME) && + ((tmpTotalMaxLBA * 2) + +- (64*2*1024) /*metadata = 64MB*/ > ++ (64*2*1024 ) /*metadata = 64MB*/ > + le32_to_cpu(pPhysDisk0->MaxLBA))) + continue; + +- if ((csmisas_fill_location_data(ioc, ++ if((csmisas_fill_location_data(ioc, + pPhysDisk0->PhysDiskBus, pPhysDisk0->PhysDiskID, + karg->bIdentify, + &karg->Location[karg->bNumberOfLocationIdentifiers])) == 0) +@@ -5743,7 +5749,7 @@ + pci_free_consistent(ioc->pcidev, volumepage0sz, pVolume0, + volume0_dma); + +- if (pPhysDisk0) ++ if(pPhysDisk0) + pci_free_consistent(ioc->pcidev, physdiskpage0sz, pPhysDisk0, + physdisk0_dma); + +@@ -5765,7 +5771,7 @@ + PCSMI_SAS_GET_LOCATION_BUFFER karg; + IOCTL_HEADER ioctl_header; + MPT_ADAPTER *ioc = NULL; +- int iocnum, i; ++ int iocnum,i; + int csmi_sas_get_location_sz; + int memory_pages; + struct sas_device_info *sas_info; +@@ -5773,7 +5779,7 @@ + if (copy_from_user(&ioctl_header, uarg, sizeof(IOCTL_HEADER))) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in IOCTL_HEADER" +- "struct @ %p\n", __FILE__, __LINE__, __func__, uarg); ++ "struct @ %p\n", __FILE__, __LINE__, __FUNCTION__, uarg); + return -EFAULT; + } + +@@ -5781,11 +5787,11 @@ + memory_pages = get_order(csmi_sas_get_location_sz); + karg = (PCSMI_SAS_GET_LOCATION_BUFFER)__get_free_pages( + GFP_KERNEL, memory_pages); +- if (!karg) { ++ if (!karg){ + printk(KERN_ERR "%s@%d::%s() - " + "Unable to malloc GET_LOCATION_BUFFER " + "csmi_sas_get_location_sz=%d memory_pages=%d\n", +- __FILE__, __LINE__, __func__, ++ __FILE__, __LINE__, __FUNCTION__, + csmi_sas_get_location_sz, memory_pages); + return -ENOMEM; + } +@@ -5794,7 +5800,7 @@ + if (copy_from_user(karg, uarg, csmi_sas_get_location_sz)) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to read in csmi_sas_phy_control_buffer " +- "struct @ %p\n", __FILE__, __LINE__, __func__, uarg); ++ "struct @ %p\n", __FILE__, __LINE__, __FUNCTION__, uarg); + free_pages((unsigned long)karg, memory_pages); + return -EFAULT; + } +@@ -5802,22 +5808,22 @@ + if (((iocnum = mpt_verify_adapter(karg->IoctlHeader.IOControllerNumber, + &ioc)) < 0) || (ioc == NULL)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)karg, memory_pages); +- return -ENODEV; +- } +- +- if (!csmisas_is_this_sas_cntr(ioc)) { +- printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", +- __FILE__, __func__, __LINE__, iocnum); +- free_pages((unsigned long)karg, memory_pages); +- return -ENODEV; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n", __func__)); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)karg, memory_pages); ++ return -ENODEV; ++ } ++ ++ if (!csmisas_is_this_sas_cntr(ioc)) { ++ printk(KERN_ERR "%s::%s() @%d - ioc%d not SAS controller!\n", ++ __FILE__, __FUNCTION__, __LINE__, iocnum); ++ free_pages((unsigned long)karg, memory_pages); ++ return -ENODEV; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s enter.\n",__FUNCTION__)); + + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_INVALID_PARAMETER; +- if (karg->bLengthOfLocationIdentifier != ++ if(karg->bLengthOfLocationIdentifier != + sizeof(CSMI_SAS_LOCATION_IDENTIFIER)) + goto cim_sas_get_location_exit; + +@@ -5828,12 +5834,12 @@ + + /* RAID SUPPORT */ + if (ioc->raid_data.pIocPg2 && sas_info->is_logical_volume) { +- for (i = 0; i < ioc->raid_data.pIocPg2->NumActiveVolumes; i++) { ++ for (i=0; iraid_data.pIocPg2->NumActiveVolumes; i++){ + if (sas_info->fw.id == + ioc->raid_data.pIocPg2->RaidVolume[i].VolumeID && + sas_info->fw.channel == + ioc->raid_data.pIocPg2->RaidVolume[i].VolumeBus) { +- if (csmisas_fill_location_data_raid(ioc, karg, ++ if(csmisas_fill_location_data_raid(ioc, karg, + ioc->raid_data.pIocPg2->RaidVolume[i].VolumeBus, + ioc->raid_data.pIocPg2->RaidVolume[i].VolumeID) == 0) + karg->IoctlHeader.ReturnCode = +@@ -5852,13 +5858,13 @@ + + /* make sure there's enough room to populate the Location[] struct */ + if ((csmi_sas_get_location_sz - +- offsetof(CSMI_SAS_GET_LOCATION_BUFFER, Location)) < ++ offsetof(CSMI_SAS_GET_LOCATION_BUFFER,Location)) < + sizeof(CSMI_SAS_LOCATION_IDENTIFIER)) + goto cim_sas_get_location_exit; + +- karg->bNumberOfLocationIdentifiers = 1; +- karg->Location[0].bLocationFlags = 0; +- if ((csmisas_fill_location_data(ioc, sas_info->fw.channel, ++ karg->bNumberOfLocationIdentifiers=1; ++ karg->Location[0].bLocationFlags=0; ++ if((csmisas_fill_location_data(ioc, sas_info->fw.channel, + sas_info->fw.id, karg->bIdentify, &karg->Location[0])) == 0) + karg->IoctlHeader.ReturnCode = CSMI_SAS_STATUS_SUCCESS; + else +@@ -5871,12 +5877,12 @@ + if (copy_to_user(uarg, karg, csmi_sas_get_location_sz)) { + printk(KERN_ERR "%s@%d::%s() - " + "Unable to write out csmi_sas_get_location_buffer " +- "@ %p\n", __FILE__, __LINE__, __func__, uarg); +- free_pages((unsigned long)karg, memory_pages); +- return -EFAULT; +- } +- +- dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n", __func__)); +- free_pages((unsigned long)karg, memory_pages); +- return 0; +-} ++ "@ %p\n",__FILE__, __LINE__, __FUNCTION__, uarg); ++ free_pages((unsigned long)karg, memory_pages); ++ return -EFAULT; ++ } ++ ++ dcsmisasprintk(ioc, printk(KERN_DEBUG "%s exit.\n",__FUNCTION__)); ++ free_pages((unsigned long)karg, memory_pages); ++ return 0; ++} +diff -r 8807687e8e9c drivers/message/fusion/csmi/csmisas.h +--- a/drivers/message/fusion/csmi/csmisas.h Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/csmi/csmisas.h Tue Sep 01 16:11:22 2009 +0100 +@@ -87,10 +87,10 @@ + #ifndef _CSMI_SAS_H_ + #define _CSMI_SAS_H_ + +-/* CSMI Specification Revision, the intent is that all versions of the +- specification will be backward compatible after the 1.00 release. +- Major revision number, corresponds to xxxx. of CSMI specification +- Minor revision number, corresponds to .xxxx of CSMI specification */ ++// CSMI Specification Revision, the intent is that all versions of the ++// specification will be backward compatible after the 1.00 release. ++// Major revision number, corresponds to xxxx. of CSMI specification ++// Minor revision number, corresponds to .xxxx of CSMI specification + #define CSMI_MAJOR_REVISION 0 + #define CSMI_MINOR_REVISION 90 + +@@ -104,60 +104,60 @@ + /* TARGET OS LINUX SPECIFIC CODE */ + /*************************************************************************/ + ++// EDM #ifdef _linux + #ifdef __KERNEL__ + +-/* Linux base types */ ++// Linux base types + + #include + + #define __i8 char + +-/* pack definition */ ++// pack definition + +-#if 0 +- #define CSMI_SAS_BEGIN_PACK(x) pack(x) +- #define CSMI_SAS_END_PACK pack() ++// EDM #define CSMI_SAS_BEGIN_PACK(x) pack(x) ++// EDM #define CSMI_SAS_END_PACK pack() + +- /* IOCTL Control Codes */ +- /* (IoctlHeader.ControlCode) */ ++// IOCTL Control Codes ++// (IoctlHeader.ControlCode) + +- /* Control Codes prior to 0.77 */ ++// Control Codes prior to 0.77 + +- /* Control Codes requiring CSMI_ALL_SIGNATURE */ ++// Control Codes requiring CSMI_ALL_SIGNATURE + +- #define CC_CSMI_SAS_GET_DRIVER_INFO 0x12345678 +- #define CC_CSMI_SAS_GET_CNTLR_CONFIG 0x23456781 +- #define CC_CSMI_SAS_GET_CNTLR_STATUS 0x34567812 +- #define CC_CSMI_SAS_FIRMWARE_DOWNLOAD 0x92345678 ++// #define CC_CSMI_SAS_GET_DRIVER_INFO 0x12345678 ++// #define CC_CSMI_SAS_GET_CNTLR_CONFIG 0x23456781 ++// #define CC_CSMI_SAS_GET_CNTLR_STATUS 0x34567812 ++// #define CC_CSMI_SAS_FIRMWARE_DOWNLOAD 0x92345678 + +- /* Control Codes requiring CSMI_RAID_SIGNATURE */ ++// Control Codes requiring CSMI_RAID_SIGNATURE + +- #define CC_CSMI_SAS_GET_RAID_INFO 0x45678123 +- #define CC_CSMI_SAS_GET_RAID_CONFIG 0x56781234 ++// #define CC_CSMI_SAS_GET_RAID_INFO 0x45678123 ++// #define CC_CSMI_SAS_GET_RAID_CONFIG 0x56781234 + +- /* Control Codes requiring CSMI_SAS_SIGNATURE */ ++// Control Codes requiring CSMI_SAS_SIGNATURE + +- #define CC_CSMI_SAS_GET_PHY_INFO 0x67812345 +- #define CC_CSMI_SAS_SET_PHY_INFO 0x78123456 +- #define CC_CSMI_SAS_GET_LINK_ERRORS 0x81234567 +- #define CC_CSMI_SAS_SMP_PASSTHRU 0xA1234567 +- #define CC_CSMI_SAS_SSP_PASSTHRU 0xB1234567 +- #define CC_CSMI_SAS_STP_PASSTHRU 0xC1234567 +- #define CC_CSMI_SAS_GET_SATA_SIGNATURE 0xD1234567 +- #define CC_CSMI_SAS_GET_SCSI_ADDRESS 0xE1234567 +- #define CC_CSMI_SAS_GET_DEVICE_ADDRESS 0xF1234567 +- #define CC_CSMI_SAS_TASK_MANAGEMENT 0xA2345678 +-#endif +- /* Control Codes for 0.77 and later */ ++// #define CC_CSMI_SAS_GET_PHY_INFO 0x67812345 ++// #define CC_CSMI_SAS_SET_PHY_INFO 0x78123456 ++// #define CC_CSMI_SAS_GET_LINK_ERRORS 0x81234567 ++// #define CC_CSMI_SAS_SMP_PASSTHRU 0xA1234567 ++// #define CC_CSMI_SAS_SSP_PASSTHRU 0xB1234567 ++// #define CC_CSMI_SAS_STP_PASSTHRU 0xC1234567 ++// #define CC_CSMI_SAS_GET_SATA_SIGNATURE 0xD1234567 ++// #define CC_CSMI_SAS_GET_SCSI_ADDRESS 0xE1234567 ++// #define CC_CSMI_SAS_GET_DEVICE_ADDRESS 0xF1234567 ++// #define CC_CSMI_SAS_TASK_MANAGEMENT 0xA2345678 + +- /* Control Codes requiring CSMI_ALL_SIGNATURE */ ++// Control Codes for 0.77 and later ++ ++// Control Codes requiring CSMI_ALL_SIGNATURE + + #define CC_CSMI_SAS_GET_DRIVER_INFO 0xCC770001 + #define CC_CSMI_SAS_GET_CNTLR_CONFIG 0xCC770002 + #define CC_CSMI_SAS_GET_CNTLR_STATUS 0xCC770003 + #define CC_CSMI_SAS_FIRMWARE_DOWNLOAD 0xCC770004 + +-/* Control Codes requiring CSMI_RAID_SIGNATURE */ ++// Control Codes requiring CSMI_RAID_SIGNATURE + + #define CC_CSMI_SAS_GET_RAID_INFO 0xCC77000A + #define CC_CSMI_SAS_GET_RAID_CONFIG 0xCC77000B +@@ -166,7 +166,7 @@ + #define CC_CSMI_SAS_GET_RAID_ELEMENT 0xCC77000E + #define CC_CSMI_SAS_SET_RAID_OPERATION 0xCC77000F + +-/* Control Codes requiring CSMI_SAS_SIGNATURE */ ++// Control Codes requiring CSMI_SAS_SIGNATURE + + #define CC_CSMI_SAS_GET_PHY_INFO 0xCC770014 + #define CC_CSMI_SAS_SET_PHY_INFO 0xCC770015 +@@ -182,14 +182,14 @@ + #define CC_CSMI_SAS_GET_LOCATION 0xCC770025 + + +-/* Control Codes requiring CSMI_PHY_SIGNATURE */ ++// Control Codes requiring CSMI_PHY_SIGNATURE + + #define CC_CSMI_SAS_PHY_CONTROL 0xCC77003C + +-/* #pragma CSMI_SAS_BEGIN_PACK(8) */ ++// EDM #pragma CSMI_SAS_BEGIN_PACK(8) + #pragma pack(8) + +-/* IOCTL_HEADER */ ++// IOCTL_HEADER + typedef struct _IOCTL_HEADER { + __u32 IOControllerNumber; + __u32 Length; +@@ -199,9 +199,180 @@ + } IOCTL_HEADER, + *PIOCTL_HEADER; + ++// EDM #pragma CSMI_SAS_END_PACK + #pragma pack() + + #endif ++ ++/*************************************************************************/ ++/* TARGET OS WINDOWS SPECIFIC CODE */ ++/*************************************************************************/ ++ ++#ifdef _WIN32 ++ ++// windows IOCTL definitions ++ ++#ifndef _NTDDSCSIH_ ++#include ++#endif ++ ++// pack definition ++ ++#if defined _MSC_VER ++ #define CSMI_SAS_BEGIN_PACK(x) pack(push,x) ++ #define CSMI_SAS_END_PACK pack(pop) ++#elif defined __BORLANDC__ ++ #define CSMI_SAS_BEGIN_PACK(x) option -a##x ++ #define CSMI_SAS_END_PACK option -a. ++#else ++ #error "CSMISAS.H - Must externally define a pack compiler designator." ++#endif ++ ++// base types ++ ++#define __u8 unsigned char ++#define __u16 unsigned short ++#define __u32 unsigned long ++#define __u64 unsigned __int64 ++ ++#define __i8 char ++ ++// IOCTL Control Codes ++// (IoctlHeader.ControlCode) ++ ++// Control Codes requiring CSMI_ALL_SIGNATURE ++ ++#define CC_CSMI_SAS_GET_DRIVER_INFO 1 ++#define CC_CSMI_SAS_GET_CNTLR_CONFIG 2 ++#define CC_CSMI_SAS_GET_CNTLR_STATUS 3 ++#define CC_CSMI_SAS_FIRMWARE_DOWNLOAD 4 ++ ++// Control Codes requiring CSMI_RAID_SIGNATURE ++ ++#define CC_CSMI_SAS_GET_RAID_INFO 10 ++#define CC_CSMI_SAS_GET_RAID_CONFIG 11 ++#define CC_CSMI_SAS_GET_RAID_FEATURES 12 ++#define CC_CSMI_SAS_SET_RAID_CONTROL 13 ++#define CC_CSMI_SAS_GET_RAID_ELEMENT 14 ++#define CC_CSMI_SAS_SET_RAID_OPERATION 15 ++ ++// Control Codes requiring CSMI_SAS_SIGNATURE ++ ++#define CC_CSMI_SAS_GET_PHY_INFO 20 ++#define CC_CSMI_SAS_SET_PHY_INFO 21 ++#define CC_CSMI_SAS_GET_LINK_ERRORS 22 ++#define CC_CSMI_SAS_SMP_PASSTHRU 23 ++#define CC_CSMI_SAS_SSP_PASSTHRU 24 ++#define CC_CSMI_SAS_STP_PASSTHRU 25 ++#define CC_CSMI_SAS_GET_SATA_SIGNATURE 26 ++#define CC_CSMI_SAS_GET_SCSI_ADDRESS 27 ++#define CC_CSMI_SAS_GET_DEVICE_ADDRESS 28 ++#define CC_CSMI_SAS_TASK_MANAGEMENT 29 ++#define CC_CSMI_SAS_GET_CONNECTOR_INFO 30 ++#define CC_CSMI_SAS_GET_LOCATION 31 ++ ++// Control Codes requiring CSMI_PHY_SIGNATURE ++ ++#define CC_CSMI_SAS_PHY_CONTROL 60 ++ ++#define IOCTL_HEADER SRB_IO_CONTROL ++#define PIOCTL_HEADER PSRB_IO_CONTROL ++ ++#endif ++ ++/*************************************************************************/ ++/* TARGET OS NETWARE SPECIFIC CODE */ ++/*************************************************************************/ ++ ++#ifdef _NETWARE ++ ++// NetWare IOCTL definitions ++ ++#define CSMI_SAS_BEGIN_PACK(x) pack(x) ++#define CSMI_SAS_END_PACK pack() ++ ++#ifndef LONG ++typedef unsigned long LONG; ++#endif ++ ++#ifndef WORD ++typedef unsigned short WORD; ++#endif ++ ++#ifndef BYTE ++typedef unsigned char BYTE; ++#endif ++ ++/* Need to have these definitions for Netware */ ++#define __u8 unsigned char ++#define __u16 unsigned short ++#define __u32 unsigned long ++#define __u64 unsigned __int64 ++ ++#define __i8 char ++ ++ ++// EDM #pragma CSMI_SAS_BEGIN_PACK(8) ++#pragma pack(8) ++ ++// IOCTL_HEADER ++typedef struct _IOCTL_HEADER { ++ __u32 Length; ++ __u32 ReturnCode; ++} IOCTL_HEADER, ++ *PIOCTL_HEADER; ++ ++// EDM #pragma CSMI_SAS_END_PACK ++#pragma pack() ++ ++// IOCTL Control Codes ++// (IoctlHeader.ControlCode) ++ ++// Control Codes requiring CSMI_ALL_SIGNATURE ++ ++#define CC_CSMI_SAS_GET_DRIVER_INFO 0x01FF0001 ++#define CC_CSMI_SAS_GET_CNTLR_CONFIG 0x01FF0002 ++#define CC_CSMI_SAS_GET_CNTLR_STATUS 0x01FF0003 ++#define CC_CSMI_SAS_FIRMWARE_DOWNLOAD 0x01FF0004 ++ ++// Control Codes requiring CSMI_RAID_SIGNATURE ++ ++#define CC_CSMI_SAS_GET_RAID_INFO 0x01FF000A ++#define CC_CSMI_SAS_GET_RAID_CONFIG 0x01FF000B ++#define CC_CSMI_SAS_GET_RAID_FEATURES 0x01FF000C ++#define CC_CSMI_SAS_SET_RAID_CONTROL 0x01FF000D ++#define CC_CSMI_SAS_GET_RAID_ELEMENT 0x01FF000E ++#define CC_CSMI_SAS_SET_RAID_OPERATION 0x01FF000F ++ ++// Control Codes requiring CSMI_SAS_SIGNATURE ++ ++#define CC_CSMI_SAS_GET_PHY_INFO 0x01FF0014 ++#define CC_CSMI_SAS_SET_PHY_INFO 0x01FF0015 ++#define CC_CSMI_SAS_GET_LINK_ERRORS 0x01FF0016 ++#define CC_CSMI_SAS_SMP_PASSTHRU 0x01FF0017 ++#define CC_CSMI_SAS_SSP_PASSTHRU 0x01FF0018 ++#define CC_CSMI_SAS_STP_PASSTHRU 0x01FF0019 ++#define CC_CSMI_SAS_GET_SATA_SIGNATURE 0x01FF001A ++#define CC_CSMI_SAS_GET_SCSI_ADDRESS 0x01FF001B ++#define CC_CSMI_SAS_GET_DEVICE_ADDRESS 0x01FF001C ++#define CC_CSMI_SAS_TASK_MANAGEMENT 0x01FF001D ++#define CC_CSMI_SAS_GET_CONNECTOR_INFO 0x01FF001E ++#define CC_CSMI_SAS_GET_LOCATION 0x01FF001F ++ ++// Control Codes requiring CSMI_PHY_SIGNATURE ++ ++#define CC_CSMI_SAS_PHY_CONTROL 60 ++ ++#endif ++ ++/*************************************************************************/ ++/* TARGET OS NOT DEFINED ERROR */ ++/*************************************************************************/ ++ ++// EDM ++//#if (!_WIN32 && !_linux && !_NETWARE) ++// #error "Unknown target OS." ++//#endif + + /*************************************************************************/ + /* OS INDEPENDENT CODE */ +@@ -209,8 +380,8 @@ + + /* * * * * * * * * * Class Independent IOCTL Constants * * * * * * * * * */ + +-/* Return codes for all IOCTL's regardless of class*/ +-/* (IoctlHeader.ReturnCode) */ ++// Return codes for all IOCTL's regardless of class ++// (IoctlHeader.ReturnCode) + + #define CSMI_SAS_STATUS_SUCCESS 0 + #define CSMI_SAS_STATUS_FAILED 1 +@@ -218,51 +389,51 @@ + #define CSMI_SAS_STATUS_INVALID_PARAMETER 3 + #define CSMI_SAS_STATUS_WRITE_ATTEMPTED 4 + +-/* Signature value +- (IoctlHeader.Signature) */ ++// Signature value ++// (IoctlHeader.Signature) + + #define CSMI_ALL_SIGNATURE "CSMIALL" + +-/* Timeout value default of 60 seconds +- (IoctlHeader.Timeout) */ ++// Timeout value default of 60 seconds ++// (IoctlHeader.Timeout) + + #define CSMI_ALL_TIMEOUT 60 + +-/* Direction values for data flow on this IOCTL +- (IoctlHeader.Direction, Linux only) */ ++// Direction values for data flow on this IOCTL ++// (IoctlHeader.Direction, Linux only) + #define CSMI_SAS_DATA_READ 0 + #define CSMI_SAS_DATA_WRITE 1 + +-/* I/O Bus Types +- ISA and EISA bus types are not supported +- (bIoBusType) */ ++// I/O Bus Types ++// ISA and EISA bus types are not supported ++// (bIoBusType) + + #define CSMI_SAS_BUS_TYPE_PCI 3 + #define CSMI_SAS_BUS_TYPE_PCMCIA 4 + +-/* Controller Status +- (uStatus) */ ++// Controller Status ++// (uStatus) + + #define CSMI_SAS_CNTLR_STATUS_GOOD 1 + #define CSMI_SAS_CNTLR_STATUS_FAILED 2 + #define CSMI_SAS_CNTLR_STATUS_OFFLINE 3 + #define CSMI_SAS_CNTLR_STATUS_POWEROFF 4 + +-/* Offline Status Reason +- (uOfflineReason) */ ++// Offline Status Reason ++// (uOfflineReason) + + #define CSMI_SAS_OFFLINE_REASON_NO_REASON 0 + #define CSMI_SAS_OFFLINE_REASON_INITIALIZING 1 + #define CSMI_SAS_OFFLINE_REASON_BACKSIDE_BUS_DEGRADED 2 + #define CSMI_SAS_OFFLINE_REASON_BACKSIDE_BUS_FAILURE 3 + +-/* Controller Class +- (bControllerClass) */ ++// Controller Class ++// (bControllerClass) + + #define CSMI_SAS_CNTLR_CLASS_HBA 5 + +-/* Controller Flag bits +- (uControllerFlags) */ ++// Controller Flag bits ++// (uControllerFlags) + + #define CSMI_SAS_CNTLR_SAS_HBA 0x00000001 + #define CSMI_SAS_CNTLR_SAS_RAID 0x00000002 +@@ -270,29 +441,32 @@ + #define CSMI_SAS_CNTLR_SATA_RAID 0x00000008 + #define CSMI_SAS_CNTLR_SMART_ARRAY 0x00000010 + +-/* for firmware download */ ++// for firmware download + #define CSMI_SAS_CNTLR_FWD_SUPPORT 0x00010000 + #define CSMI_SAS_CNTLR_FWD_ONLINE 0x00020000 + #define CSMI_SAS_CNTLR_FWD_SRESET 0x00040000 + #define CSMI_SAS_CNTLR_FWD_HRESET 0x00080000 + #define CSMI_SAS_CNTLR_FWD_RROM 0x00100000 + +-/* for RAID configuration supported */ ++// for RAID configuration supported + #define CSMI_SAS_CNTLR_RAID_CFG_SUPPORT 0x01000000 + +-/* Download Flag bits (uDownloadFlags) */ ++// Download Flag bits ++// (uDownloadFlags) + #define CSMI_SAS_FWD_VALIDATE 0x00000001 + #define CSMI_SAS_FWD_SOFT_RESET 0x00000002 + #define CSMI_SAS_FWD_HARD_RESET 0x00000004 + +-/* Firmware Download Status (usStatus) */ ++// Firmware Download Status ++// (usStatus) + #define CSMI_SAS_FWD_SUCCESS 0 + #define CSMI_SAS_FWD_FAILED 1 + #define CSMI_SAS_FWD_USING_RROM 2 + #define CSMI_SAS_FWD_REJECT 3 + #define CSMI_SAS_FWD_DOWNREV 4 + +-/* Firmware Download Severity (usSeverity) */ ++// Firmware Download Severity ++// (usSeverity> + #define CSMI_SAS_FWD_INFORMATION 0 + #define CSMI_SAS_FWD_WARNING 1 + #define CSMI_SAS_FWD_ERROR 2 +@@ -300,22 +474,25 @@ + + /* * * * * * * * * * SAS RAID Class IOCTL Constants * * * * * * * * */ + +-/* Return codes for the RAID IOCTL's regardless of class */ +-/* (IoctlHeader.ReturnCode) */ ++// Return codes for the RAID IOCTL's regardless of class ++// (IoctlHeader.ReturnCode) + + #define CSMI_SAS_RAID_SET_OUT_OF_RANGE 1000 + #define CSMI_SAS_RAID_SET_BUFFER_TOO_SMALL 1001 + #define CSMI_SAS_RAID_SET_DATA_CHANGED 1002 + +-/* Signature value (IoctlHeader.Signature) */ ++// Signature value ++// (IoctlHeader.Signature) + + #define CSMI_RAID_SIGNATURE "CSMIARY" + +-/* Timeout value default of 60 seconds (IoctlHeader.Timeout) */ ++// Timeout value default of 60 seconds ++// (IoctlHeader.Timeout) + + #define CSMI_RAID_TIMEOUT 60 + +-/* RAID Types (bRaidType) */ ++// RAID Types ++// (bRaidType) + #define CSMI_SAS_RAID_TYPE_NONE 0 + #define CSMI_SAS_RAID_TYPE_0 1 + #define CSMI_SAS_RAID_TYPE_1 2 +@@ -327,11 +504,12 @@ + #define CSMI_SAS_RAID_TYPE_VOLUME 8 + #define CSMI_SAS_RAID_TYPE_1E 9 + #define CSMI_SAS_RAID_TYPE_OTHER 255 +-/* the last value 255 was already defined for other so end is defined as 254 */ ++// the last value 255 was already defined for other ++// so end is defined as 254 + #define CSMI_SAS_RAID_TYPE_END 254 + +-/* RAID Status (bStatus) */ +- ++// RAID Status ++// (bStatus) + #define CSMI_SAS_RAID_SET_STATUS_OK 0 + #define CSMI_SAS_RAID_SET_STATUS_DEGRADED 1 + #define CSMI_SAS_RAID_SET_STATUS_REBUILDING 2 +@@ -341,16 +519,19 @@ + #define CSMI_SAS_RAID_SET_STATUS_QUEUED_FOR_REBUILD 6 + #define CSMI_SAS_RAID_SET_STATUS_QUEUED_FOR_TRANSFORMATION 7 + +-/* RAID Drive Count (bDriveCount, 0xF1 to 0xFF are reserved) */ ++// RAID Drive Count ++// (bDriveCount, 0xF1 to 0xFF are reserved) + #define CSMI_SAS_RAID_DRIVE_COUNT_TOO_BIG 0xF1 + #define CSMI_SAS_RAID_DRIVE_COUNT_SUPRESSED 0xF2 + +-/* RAID Data Type (bDataType) */ ++// RAID Data Type ++// (bDataType) + #define CSMI_SAS_RAID_DATA_DRIVES 0 + #define CSMI_SAS_RAID_DATA_DEVICE_ID 1 + #define CSMI_SAS_RAID_DATA_ADDITIONAL_DATA 2 + +-/* RAID Drive Status (bDriveStatus) */ ++// RAID Drive Status ++// (bDriveStatus) + #define CSMI_SAS_DRIVE_STATUS_OK 0 + #define CSMI_SAS_DRIVE_STATUS_REBUILDING 1 + #define CSMI_SAS_DRIVE_STATUS_FAILED 2 +@@ -358,13 +539,15 @@ + #define CSMI_SAS_DRIVE_STATUS_OFFLINE 4 + #define CSMI_SAS_DRIVE_STATUS_QUEUED_FOR_REBUILD 5 + +-/* RAID Drive Usage (bDriveUsage) */ ++// RAID Drive Usage ++// (bDriveUsage) + #define CSMI_SAS_DRIVE_CONFIG_NOT_USED 0 + #define CSMI_SAS_DRIVE_CONFIG_MEMBER 1 + #define CSMI_SAS_DRIVE_CONFIG_SPARE 2 + #define CSMI_SAS_DRIVE_CONFIG_SPARE_ACTIVE 3 + +-/* RAID Drive Type (bDriveType) */ ++// RAID Drive Type ++// (bDriveType) + #define CSMI_SAS_DRIVE_TYPE_UNKNOWN 0 + #define CSMI_SAS_DRIVE_TYPE_SINGLE_PORT_SAS 1 + #define CSMI_SAS_DRIVE_TYPE_DUAL_PORT_SAS 2 +@@ -372,20 +555,23 @@ + #define CSMI_SAS_DRIVE_TYPE_SATA_PS 4 + #define CSMI_SAS_DRIVE_TYPE_OTHER 255 + +-/* RAID Write Protect (bWriteProtect) */ ++// RAID Write Protect ++// (bWriteProtect) + #define CSMI_SAS_RAID_SET_WRITE_PROTECT_UNKNOWN 0 + #define CSMI_SAS_RAID_SET_WRITE_PROTECT_UNCHANGED 0 + #define CSMI_SAS_RAID_SET_WRITE_PROTECT_ENABLED 1 + #define CSMI_SAS_RAID_SET_WRITE_PROTECT_DISABLED 2 + +-/* RAID Cache Setting (bCacheSetting) */ ++// RAID Cache Setting ++// (bCacheSetting) + #define CSMI_SAS_RAID_SET_CACHE_UNKNOWN 0 + #define CSMI_SAS_RAID_SET_CACHE_UNCHANGED 0 + #define CSMI_SAS_RAID_SET_CACHE_ENABLED 1 + #define CSMI_SAS_RAID_SET_CACHE_DISABLED 2 + #define CSMI_SAS_RAID_SET_CACHE_CORRUPT 3 + +-/* RAID Features (uFeatures) */ ++// RAID Features ++// (uFeatures) + #define CSMI_SAS_RAID_FEATURE_TRANSFORMATION 0x00000001 + #define CSMI_SAS_RAID_FEATURE_REBUILD 0x00000002 + #define CSMI_SAS_RAID_FEATURE_SPLIT_MIRROR 0x00000004 +@@ -394,7 +580,8 @@ + #define CSMI_SAS_RAID_FEATURE_SURFACE_SCAN 0x00000020 + #define CSMI_SAS_RAID_FEATURE_SPARES_SHARED 0x00000040 + +-/* RAID Priority (bDefaultTransformPriority, etc.) */ ++// RAID Priority ++// (bDefaultTransformPriority, etc.) + #define CSMI_SAS_PRIORITY_UNKNOWN 0 + #define CSMI_SAS_PRIORITY_UNCHANGED 0 + #define CSMI_SAS_PRIORITY_AUTO 1 +@@ -403,25 +590,30 @@ + #define CSMI_SAS_PRIORITY_MEDIUM 4 + #define CSMI_SAS_PRIORITY_HIGH 5 + +-/* RAID Transformation Rules (uRaidSetTransformationRules) */ ++// RAID Transformation Rules ++// (uRaidSetTransformationRules) + #define CSMI_SAS_RAID_RULE_AVAILABLE_MEMORY 0x00000001 + #define CSMI_SAS_RAID_RULE_OVERLAPPED_EXTENTS 0x00000002 + +-/* RAID Cache Ratios Supported (bCacheRatiosSupported) */ +-/* from 0 to 100 defines the write to read ratio, 0 is 100% write */ ++// RAID Cache Ratios Supported ++// (bCacheRatiosSupported) ++// from 0 to 100 defines the write to read ratio, 0 is 100% write + #define CSMI_SAS_RAID_CACHE_RATIO_RANGE 101 + #define CSMI_SAS_RAID_CACHE_RATIO_FIXED 102 + #define CSMI_SAS_RAID_CACHE_RATIO_AUTO 103 + #define CSMI_SAS_RAID_CACHE_RATIO_END 255 + +-/* RAID Cache Ratio Flag (bCacheRatioFlag) */ ++// RAID Cache Ratio Flag ++// (bCacheRatioFlag) + #define CSMI_SAS_RAID_CACHE_RATIO_DISABLE 0 + #define CSMI_SAS_RAID_CACHE_RATIO_ENABLE 1 + +-/* RAID Clear Configuration Signature (bClearConfiguration) */ ++// RAID Clear Configuration Signature ++// (bClearConfiguration) + #define CSMI_SAS_RAID_CLEAR_CONFIGURATION_SIGNATURE "RAIDCLR" + +-/* RAID Failure Codes (uFailureCode) */ ++// RAID Failure Codes ++// (uFailureCode) + #define CSMI_SAS_FAIL_CODE_OK 0 + #define CSMI_SAS_FAIL_CODE_PARAMETER_INVALID 1000 + #define CSMI_SAS_FAIL_CODE_TRANSFORM_PRIORITY_INVALID 1001 +@@ -446,19 +638,22 @@ + + #define CSMI_SAS_FAIL_CODE_WAIT_FOR_OPERATION 3000 + +-/* RAID Enumeration Types (uEnumerationType) */ ++// RAID Enumeration Types ++// (uEnumerationType) + #define CSMI_SAS_RAID_ELEMENT_TYPE_DRIVE 0 + #define CSMI_SAS_RAID_ELEMENT_TYPE_MODULE 1 + #define CSMI_SAS_RAID_ELEMENT_TYPE_DRIVE_RAID_SET 2 + #define CSMI_SAS_RAID_ELEMENT_TYPE_EXTENT_DRIVE 3 + +-/* RAID Extent Types (bExtentType) */ ++// RAID Extent Types ++// (bExtentType) + #define CSMI_SAS_RAID_EXTENT_RESERVED 0 + #define CSMI_SAS_RAID_EXTENT_METADATA 1 + #define CSMI_SAS_RAID_EXTENT_ALLOCATED 2 + #define CSMI_SAS_RAID_EXTENT_UNALLOCATED 3 + +-/* RAID Operation Types (uOperationType) */ ++// RAID Operation Types ++// (uOperationType) + #define CSMI_SAS_RAID_SET_CREATE 0 + #define CSMI_SAS_RAID_SET_LABEL 1 + #define CSMI_SAS_RAID_SET_TRANSFORM 2 +@@ -468,20 +663,23 @@ + #define CSMI_SAS_RAID_SET_ONLINE_STATE 6 + #define CSMI_SAS_RAID_SET_SPARE 7 + +-/* RAID Transform Types (bTransformType) */ ++// RAID Transform Types ++// (bTransformType) + #define CSMI_SAS_RAID_SET_TRANSFORM_SPLIT_MIRROR 0 + #define CSMI_SAS_RAID_SET_TRANSFORM_MERGE_RAID_0 1 + #define CSMI_SAS_RAID_SET_TRANSFORM_LUN_RENUMBER 2 + #define CSMI_SAS_RAID_SET_TRANSFORM_RAID_SET 3 + +-/* RAID Online State (bOnlineState) */ ++// RAID Online State ++// (bOnlineState) + #define CSMI_SAS_RAID_SET_STATE_UNKNOWN 0 + #define CSMI_SAS_RAID_SET_STATE_ONLINE 1 + #define CSMI_SAS_RAID_SET_STATE_OFFLINE 2 + + /* * * * * * * * * * SAS HBA Class IOCTL Constants * * * * * * * * * */ + +-/* Return codes for SAS IOCTL's (IoctlHeader.ReturnCode) */ ++// Return codes for SAS IOCTL's ++// (IoctlHeader.ReturnCode) + + #define CSMI_SAS_PHY_INFO_CHANGED CSMI_SAS_STATUS_SUCCESS + #define CSMI_SAS_PHY_INFO_NOT_CHANGEABLE 2000 +@@ -502,15 +700,18 @@ + #define CSMI_SAS_NO_SCSI_ADDRESS 2013 + #define CSMI_SAS_NO_DEVICE_ADDRESS 2014 + +-/* Signature value (IoctlHeader.Signature) */ ++// Signature value ++// (IoctlHeader.Signature) + + #define CSMI_SAS_SIGNATURE "CSMISAS" + +-/* Timeout value default of 60 seconds (IoctlHeader.Timeout) */ ++// Timeout value default of 60 seconds ++// (IoctlHeader.Timeout) + + #define CSMI_SAS_TIMEOUT 60 + +-/* Device types (bDeviceType) */ ++// Device types ++// (bDeviceType) + + #define CSMI_SAS_PHY_UNUSED 0x00 + #define CSMI_SAS_NO_DEVICE_ATTACHED 0x00 +@@ -518,15 +719,16 @@ + #define CSMI_SAS_EDGE_EXPANDER_DEVICE 0x20 + #define CSMI_SAS_FANOUT_EXPANDER_DEVICE 0x30 + +-/* Protocol options (bInitiatorPortProtocol, bTargetPortProtocol) */ ++// Protocol options ++// (bInitiatorPortProtocol, bTargetPortProtocol) + + #define CSMI_SAS_PROTOCOL_SATA 0x01 + #define CSMI_SAS_PROTOCOL_SMP 0x02 + #define CSMI_SAS_PROTOCOL_STP 0x04 + #define CSMI_SAS_PROTOCOL_SSP 0x08 + +-/* Negotiated and hardware link rates */ +-/* (bNegotiatedLinkRate, bMinimumLinkRate, bMaximumLinkRate) */ ++// Negotiated and hardware link rates ++// (bNegotiatedLinkRate, bMinimumLinkRate, bMaximumLinkRate) + + #define CSMI_SAS_LINK_RATE_UNKNOWN 0x00 + #define CSMI_SAS_PHY_DISABLED 0x01 +@@ -537,7 +739,8 @@ + #define CSMI_SAS_LINK_RATE_3_0_GBPS 0x09 + #define CSMI_SAS_LINK_VIRTUAL 0x10 + +-/* Discover state (bAutoDiscover) */ ++// Discover state ++// (bAutoDiscover) + + #define CSMI_SAS_DISCOVER_NOT_SUPPORTED 0x00 + #define CSMI_SAS_DISCOVER_NOT_STARTED 0x01 +@@ -545,49 +748,57 @@ + #define CSMI_SAS_DISCOVER_COMPLETE 0x03 + #define CSMI_SAS_DISCOVER_ERROR 0x04 + +-/* Phy features */ ++// Phy features + + #define CSMI_SAS_PHY_VIRTUAL_SMP 0x01 + +-/* Programmed link rates (bMinimumLinkRate, bMaximumLinkRate) */ +-/* (bProgrammedMinimumLinkRate, bProgrammedMaximumLinkRate) */ ++// Programmed link rates ++// (bMinimumLinkRate, bMaximumLinkRate) ++// (bProgrammedMinimumLinkRate, bProgrammedMaximumLinkRate) + + #define CSMI_SAS_PROGRAMMED_LINK_RATE_UNCHANGED 0x00 + #define CSMI_SAS_PROGRAMMED_LINK_RATE_1_5_GBPS 0x08 + #define CSMI_SAS_PROGRAMMED_LINK_RATE_3_0_GBPS 0x09 + +-/* Link rate (bNegotiatedLinkRate in CSMI_SAS_SET_PHY_INFO) */ ++// Link rate ++// (bNegotiatedLinkRate in CSMI_SAS_SET_PHY_INFO) + + #define CSMI_SAS_LINK_RATE_NEGOTIATE 0x00 + #define CSMI_SAS_LINK_RATE_PHY_DISABLED 0x01 + +-/* Signal class (bSignalClass in CSMI_SAS_SET_PHY_INFO) */ ++// Signal class ++// (bSignalClass in CSMI_SAS_SET_PHY_INFO) + + #define CSMI_SAS_SIGNAL_CLASS_UNKNOWN 0x00 + #define CSMI_SAS_SIGNAL_CLASS_DIRECT 0x01 + #define CSMI_SAS_SIGNAL_CLASS_SERVER 0x02 + #define CSMI_SAS_SIGNAL_CLASS_ENCLOSURE 0x03 + +-/* Link error reset (bResetCounts) */ ++// Link error reset ++// (bResetCounts) + + #define CSMI_SAS_LINK_ERROR_DONT_RESET_COUNTS 0x00 + #define CSMI_SAS_LINK_ERROR_RESET_COUNTS 0x01 + +-/* Phy identifier (bPhyIdentifier) */ ++// Phy identifier ++// (bPhyIdentifier) + + #define CSMI_SAS_USE_PORT_IDENTIFIER 0xFF + +-/* Port identifier (bPortIdentifier) */ ++// Port identifier ++// (bPortIdentifier) + + #define CSMI_SAS_IGNORE_PORT 0xFF + +-/* Programmed link rates (bConnectionRate) */ ++// Programmed link rates ++// (bConnectionRate) + + #define CSMI_SAS_LINK_RATE_NEGOTIATED 0x00 + #define CSMI_SAS_LINK_RATE_1_5_GBPS 0x08 + #define CSMI_SAS_LINK_RATE_3_0_GBPS 0x09 + +-/* Connection status (bConnectionStatus) */ ++// Connection status ++// (bConnectionStatus) + + #define CSMI_SAS_OPEN_ACCEPT 0 + #define CSMI_SAS_OPEN_REJECT_BAD_DESTINATION 1 +@@ -603,7 +814,8 @@ + #define CSMI_SAS_OPEN_REJECT_STP_RESOURCES_BUSY 11 + #define CSMI_SAS_OPEN_REJECT_WRONG_DESTINATION 12 + +-/* SSP Status (bSSPStatus)*/ ++// SSP Status ++// (bSSPStatus) + + #define CSMI_SAS_SSP_STATUS_UNKNOWN 0x00 + #define CSMI_SAS_SSP_STATUS_WAITING 0x01 +@@ -612,7 +824,8 @@ + #define CSMI_SAS_SSP_STATUS_RETRY 0x04 + #define CSMI_SAS_SSP_STATUS_NO_TAG 0x05 + +-/* SSP Flags (uFlags) */ ++// SSP Flags ++// (uFlags) + + #define CSMI_SAS_SSP_READ 0x00000001 + #define CSMI_SAS_SSP_WRITE 0x00000002 +@@ -623,13 +836,15 @@ + #define CSMI_SAS_SSP_TASK_ATTRIBUTE_ORDERED 0x00000020 + #define CSMI_SAS_SSP_TASK_ATTRIBUTE_ACA 0x00000040 + +-/* SSP Data present (bDataPresent) */ ++// SSP Data present ++// (bDataPresent) + + #define CSMI_SAS_SSP_NO_DATA_PRESENT 0x00 + #define CSMI_SAS_SSP_RESPONSE_DATA_PRESENT 0x01 + #define CSMI_SAS_SSP_SENSE_DATA_PRESENT 0x02 + +-/* STP Flags (uFlags) */ ++// STP Flags ++// (uFlags) + + #define CSMI_SAS_STP_READ 0x00000001 + #define CSMI_SAS_STP_WRITE 0x00000002 +@@ -641,13 +856,15 @@ + #define CSMI_SAS_STP_EXECUTE_DIAG 0x00000100 + #define CSMI_SAS_STP_RESET_DEVICE 0x00000200 + +-/* Task Management Flags (uFlags) */ ++// Task Management Flags ++// (uFlags) + + #define CSMI_SAS_TASK_IU 0x00000001 + #define CSMI_SAS_HARD_RESET_SEQUENCE 0x00000002 + #define CSMI_SAS_SUPPRESS_RESULT 0x00000004 + +-/* Task Management Functions (bTaskManagement) */ ++// Task Management Functions ++// (bTaskManagement) + + #define CSMI_SAS_SSP_ABORT_TASK 0x01 + #define CSMI_SAS_SSP_ABORT_TASK_SET 0x02 +@@ -656,14 +873,16 @@ + #define CSMI_SAS_SSP_CLEAR_ACA 0x40 + #define CSMI_SAS_SSP_QUERY_TASK 0x80 + +-/* Task Management Information (uInformation) */ ++// Task Management Information ++// (uInformation) + + #define CSMI_SAS_SSP_TEST 1 + #define CSMI_SAS_SSP_EXCEEDED 2 + #define CSMI_SAS_SSP_DEMAND 3 + #define CSMI_SAS_SSP_TRIGGER 4 + +-/* Connector Pinout Information (uPinout) */ ++// Connector Pinout Information ++// (uPinout) + + #define CSMI_SAS_CON_UNKNOWN 0x00000001 + #define CSMI_SAS_CON_SFF_8482 0x00000002 +@@ -676,9 +895,10 @@ + #define CSMI_SAS_CON_SFF_8484_LANE_3 0x00040000 + #define CSMI_SAS_CON_SFF_8484_LANE_4 0x00080000 + +-/* Connector Location Information (bLocation) */ ++// Connector Location Information ++// (bLocation) + +-/* same as uPinout above... */ ++// same as uPinout above... + // #define CSMI_SAS_CON_UNKNOWN 0x01 + #define CSMI_SAS_CON_INTERNAL 0x02 + #define CSMI_SAS_CON_EXTERNAL 0x04 +@@ -687,13 +907,15 @@ + #define CSMI_SAS_CON_NOT_PRESENT 0x20 + #define CSMI_SAS_CON_NOT_CONNECTED 0x80 + +-/* Device location identification (bIdentify) */ ++// Device location identification ++// (bIdentify) + + #define CSMI_SAS_LOCATE_UNKNOWN 0x00 + #define CSMI_SAS_LOCATE_FORCE_OFF 0x01 + #define CSMI_SAS_LOCATE_FORCE_ON 0x02 + +-/* Location Valid flags (uLocationFlags) */ ++// Location Valid flags ++// (uLocationFlags) + + #define CSMI_SAS_LOCATE_SAS_ADDRESS_VALID 0x00000001 + #define CSMI_SAS_LOCATE_SAS_LUN_VALID 0x00000002 +@@ -705,41 +927,48 @@ + + /* * * * * * * * SAS Phy Control Class IOCTL Constants * * * * * * * * */ + +-/* Return codes for SAS Phy Control IOCTL's (IoctlHeader.ReturnCode) */ ++// Return codes for SAS Phy Control IOCTL's ++// (IoctlHeader.ReturnCode) + +-/* Signature value (IoctlHeader.Signature) */ ++// Signature value ++// (IoctlHeader.Signature) + + #define CSMI_PHY_SIGNATURE "CSMIPHY" + +-/* Phy Control Functions (bFunction) */ ++// Phy Control Functions ++// (bFunction) + +-/* values 0x00 to 0xFF are consistent in definition with the SMP PHY CONTROL +- function defined in the SAS spec */ ++// values 0x00 to 0xFF are consistent in definition with the SMP PHY CONTROL ++// function defined in the SAS spec + #define CSMI_SAS_PC_NOP 0x00000000 + #define CSMI_SAS_PC_LINK_RESET 0x00000001 + #define CSMI_SAS_PC_HARD_RESET 0x00000002 + #define CSMI_SAS_PC_PHY_DISABLE 0x00000003 +-/* 0x04 to 0xFF reserved... */ ++// 0x04 to 0xFF reserved... + #define CSMI_SAS_PC_GET_PHY_SETTINGS 0x00000100 + +-/* Link Flags */ ++// Link Flags + #define CSMI_SAS_PHY_ACTIVATE_CONTROL 0x00000001 + #define CSMI_SAS_PHY_UPDATE_SPINUP_RATE 0x00000002 + #define CSMI_SAS_PHY_AUTO_COMWAKE 0x00000004 + +-/* Device Types for Phy Settings (bType) */ ++// Device Types for Phy Settings ++// (bType) + #define CSMI_SAS_UNDEFINED 0x00 + #define CSMI_SAS_SATA 0x01 + #define CSMI_SAS_SAS 0x02 + +-/* Transmitter Flags (uTransmitterFlags) */ ++// Transmitter Flags ++// (uTransmitterFlags) + #define CSMI_SAS_PHY_PREEMPHASIS_DISABLED 0x00000001 + +-/* Receiver Flags (uReceiverFlags) */ ++// Receiver Flags ++// (uReceiverFlags) + #define CSMI_SAS_PHY_EQUALIZATION_DISABLED 0x00000001 + +-/* Pattern Flags (uPatternFlags) */ +-#define CSMI_SAS_PHY_ACTIVATE_CONTROL 0x00000001 ++// Pattern Flags ++// (uPatternFlags) ++// #define CSMI_SAS_PHY_ACTIVATE_CONTROL 0x00000001 + #define CSMI_SAS_PHY_DISABLE_SCRAMBLING 0x00000002 + #define CSMI_SAS_PHY_DISABLE_ALIGN 0x00000004 + #define CSMI_SAS_PHY_DISABLE_SSC 0x00000008 +@@ -747,16 +976,18 @@ + #define CSMI_SAS_PHY_FIXED_PATTERN 0x00000010 + #define CSMI_SAS_PHY_USER_PATTERN 0x00000020 + +-/* Fixed Patterns (bFixedPattern) */ ++// Fixed Patterns ++// (bFixedPattern) + #define CSMI_SAS_PHY_CJPAT 0x00000001 + #define CSMI_SAS_PHY_ALIGN 0x00000002 + +-/* Type Flags (bTypeFlags) */ ++// Type Flags ++// (bTypeFlags) + #define CSMI_SAS_PHY_POSITIVE_DISPARITY 0x01 + #define CSMI_SAS_PHY_NEGATIVE_DISPARITY 0x02 + #define CSMI_SAS_PHY_CONTROL_CHARACTER 0x04 + +-/* Miscellaneous */ ++// Miscellaneous + #define SLOT_NUMBER_UNKNOWN 0xFFFF + + /*************************************************************************/ +@@ -765,9 +996,10 @@ + + /* * * * * * * * * * Class Independent Structures * * * * * * * * * */ + ++// EDM #pragma CSMI_SAS_BEGIN_PACK(8) + #pragma pack(8) + +-/* CC_CSMI_SAS_DRIVER_INFO */ ++// CC_CSMI_SAS_DRIVER_INFO + + typedef struct _CSMI_SAS_DRIVER_INFO { + __u8 szName[81]; +@@ -787,7 +1019,7 @@ + } CSMI_SAS_DRIVER_INFO_BUFFER, + *PCSMI_SAS_DRIVER_INFO_BUFFER; + +-/* CC_CSMI_SAS_CNTLR_CONFIGURATION */ ++// CC_CSMI_SAS_CNTLR_CONFIGURATION + + typedef struct _CSMI_SAS_PCI_BUS_ADDRESS { + __u8 bBusNumber; +@@ -842,7 +1074,7 @@ + } CSMI_SAS_CNTLR_CONFIG_BUFFER, + *PCSMI_SAS_CNTLR_CONFIG_BUFFER; + +-/* CC_CSMI_SAS_CNTLR_STATUS */ ++// CC_CSMI_SAS_CNTLR_STATUS + + typedef struct _CSMI_SAS_CNTLR_STATUS { + __u32 uStatus; +@@ -857,7 +1089,7 @@ + } CSMI_SAS_CNTLR_STATUS_BUFFER, + *PCSMI_SAS_CNTLR_STATUS_BUFFER; + +-/* CC_CSMI_SAS_FIRMWARE_DOWNLOAD */ ++// CC_CSMI_SAS_FIRMWARE_DOWNLOAD + + typedef struct _CSMI_SAS_FIRMWARE_DOWNLOAD { + __u32 uBufferLength; +@@ -875,7 +1107,7 @@ + } CSMI_SAS_FIRMWARE_DOWNLOAD_BUFFER, + *PCSMI_SAS_FIRMWARE_DOWNLOAD_BUFFER; + +-/* CC_CSMI_SAS_RAID_INFO */ ++// CC_CSMI_SAS_RAID_INFO + + typedef struct _CSMI_SAS_RAID_INFO { + __u32 uNumRaidSets; +@@ -908,7 +1140,7 @@ + } CSMI_SAS_RAID_INFO_BUFFER, + *PCSMI_SAS_RAID_INFO_BUFFER; + +-/* CC_CSMI_SAS_GET_RAID_CONFIG */ ++// CC_CSMI_SAS_GET_RAID_CONFIG + + typedef struct _CSMI_SAS_RAID_DRIVES { + __u8 bModel[40]; +@@ -988,7 +1220,7 @@ + } CSMI_SAS_RAID_CONFIG_BUFFER, + *PCSMI_SAS_RAID_CONFIG_BUFFER; + +-/* CC_CSMI_SAS_GET_RAID_FEATURES */ ++// CC_CSMI_SAS_GET_RAID_FEATURES + + typedef struct _CSMI_SAS_RAID_TYPE_DESCRIPTION { + __u8 bRaidType; +@@ -1024,7 +1256,7 @@ + } CSMI_SAS_RAID_FEATURES_BUFFER, + *PCSMI_SAS_RAID_FEATURES_BUFFER; + +-/* CC_CSMI_SAS_SET_RAID_CONTROL */ ++// CC_CSMI_SAS_SET_RAID_CONTROL + + typedef struct _CSMI_SAS_RAID_CONTROL { + __u8 bTransformPriority; +@@ -1047,7 +1279,7 @@ + } CSMI_SAS_RAID_CONTROL_BUFFER, + *PCSMI_SAS_RAID_CONTROL_BUFFER; + +-/* CC_CSMI_SAS_GET_RAID_ELEMENT */ ++// CC_CSMI_SAS_GET_RAID_ELEMENT + + typedef struct _CSMI_SAS_DRIVE_EXTENT_INFO { + __u32 uDriveIndex; +@@ -1121,7 +1353,7 @@ + } CSMI_SAS_RAID_ELEMENT_BUFFER, + *PCSMI_SAS_RAID_ELEMENT_BUFFER; + +-/* CC_CSMI_SAS_SET_RAID_OPERATION */ ++// CC_CSMI_SAS_SET_RAID_OPERATION + + typedef struct _CSMI_SAS_RAID_SET_LIST { + __u32 uRaidSetIndex; +@@ -1271,7 +1503,7 @@ + + /* * * * * * * * * * SAS HBA Class Structures * * * * * * * * * */ + +-/* CC_CSMI_SAS_GET_PHY_INFO */ ++// CC_CSMI_SAS_GET_PHY_INFO + + typedef struct _CSMI_SAS_IDENTIFY { + __u8 bDeviceType; +@@ -1313,7 +1545,7 @@ + } CSMI_SAS_PHY_INFO_BUFFER, + *PCSMI_SAS_PHY_INFO_BUFFER; + +-/* CC_CSMI_SAS_SET_PHY_INFO */ ++// CC_CSMI_SAS_SET_PHY_INFO + + typedef struct _CSMI_SAS_SET_PHY_INFO { + __u8 bPhyIdentifier; +@@ -1331,7 +1563,7 @@ + } CSMI_SAS_SET_PHY_INFO_BUFFER, + *PCSMI_SAS_SET_PHY_INFO_BUFFER; + +-/* CC_CSMI_SAS_GET_LINK_ERRORS */ ++// CC_CSMI_SAS_GET_LINK_ERRORS + + typedef struct _CSMI_SAS_LINK_ERRORS { + __u8 bPhyIdentifier; +@@ -1350,7 +1582,7 @@ + } CSMI_SAS_LINK_ERRORS_BUFFER, + *PCSMI_SAS_LINK_ERRORS_BUFFER; + +-/* CC_CSMI_SAS_SMP_PASSTHRU */ ++// CC_CSMI_SAS_SMP_PASSTHRU + + typedef struct _CSMI_SAS_SMP_REQUEST { + __u8 bFrameType; +@@ -1390,7 +1622,7 @@ + } CSMI_SAS_SMP_PASSTHRU_BUFFER, + *PCSMI_SAS_SMP_PASSTHRU_BUFFER; + +-/* CC_CSMI_SAS_SSP_PASSTHRU */ ++// CC_CSMI_SAS_SSP_PASSTHRU + + typedef struct _CSMI_SAS_SSP_PASSTHRU { + __u8 bPhyIdentifier; +@@ -1429,7 +1661,7 @@ + } CSMI_SAS_SSP_PASSTHRU_BUFFER, + *PCSMI_SAS_SSP_PASSTHRU_BUFFER; + +-/* CC_CSMI_SAS_STP_PASSTHRU */ ++// CC_CSMI_SAS_STP_PASSTHRU + + typedef struct _CSMI_SAS_STP_PASSTHRU { + __u8 bPhyIdentifier; +@@ -1461,7 +1693,7 @@ + } CSMI_SAS_STP_PASSTHRU_BUFFER, + *PCSMI_SAS_STP_PASSTHRU_BUFFER; + +-/* CC_CSMI_SAS_GET_SATA_SIGNATURE */ ++// CC_CSMI_SAS_GET_SATA_SIGNATURE + + typedef struct _CSMI_SAS_SATA_SIGNATURE { + __u8 bPhyIdentifier; +@@ -1476,7 +1708,7 @@ + } CSMI_SAS_SATA_SIGNATURE_BUFFER, + *PCSMI_SAS_SATA_SIGNATURE_BUFFER; + +-/* CC_CSMI_SAS_GET_SCSI_ADDRESS */ ++// CC_CSMI_SAS_GET_SCSI_ADDRESS + + typedef struct _CSMI_SAS_GET_SCSI_ADDRESS_BUFFER { + IOCTL_HEADER IoctlHeader; +@@ -1489,7 +1721,7 @@ + } CSMI_SAS_GET_SCSI_ADDRESS_BUFFER, + *PCSMI_SAS_GET_SCSI_ADDRESS_BUFFER; + +-/* CC_CSMI_SAS_GET_DEVICE_ADDRESS */ ++// CC_CSMI_SAS_GET_DEVICE_ADDRESS + + typedef struct _CSMI_SAS_GET_DEVICE_ADDRESS_BUFFER { + IOCTL_HEADER IoctlHeader; +@@ -1502,7 +1734,7 @@ + } CSMI_SAS_GET_DEVICE_ADDRESS_BUFFER, + *PCSMI_SAS_GET_DEVICE_ADDRESS_BUFFER; + +-/* CC_CSMI_SAS_TASK_MANAGEMENT */ ++// CC_CSMI_SAS_TASK_MANAGEMENT + + typedef struct _CSMI_SAS_SSP_TASK_IU { + __u8 bHostIndex; +@@ -1525,7 +1757,7 @@ + } CSMI_SAS_SSP_TASK_IU_BUFFER, + *PCSMI_SAS_SSP_TASK_IU_BUFFER; + +-/* CC_CSMI_SAS_GET_CONNECTOR_INFO */ ++// CC_CSMI_SAS_GET_CONNECTOR_INFO + + typedef struct _CSMI_SAS_GET_CONNECTOR_INFO { + __u32 uPinout; +@@ -1541,7 +1773,7 @@ + } CSMI_SAS_CONNECTOR_INFO_BUFFER, + *PCSMI_SAS_CONNECTOR_INFO_BUFFER; + +-/* CC_CSMI_SAS_GET_LOCATION */ ++// CC_CSMI_SAS_GET_LOCATION + + typedef struct _CSMI_SAS_LOCATION_IDENTIFIER { + __u32 bLocationFlags; +@@ -1569,7 +1801,7 @@ + } CSMI_SAS_GET_LOCATION_BUFFER, + *PCSMI_SAS_GET_LOCATION_BUFFER; + +-/* CC_CSMI_SAS_PHY_CONTROL */ ++// CC_CSMI_SAS_PHY_CONTROL + + typedef struct _CSMI_SAS_CHARACTER { + __u8 bTypeFlags; +@@ -1616,6 +1848,7 @@ + } CSMI_SAS_PHY_CONTROL_BUFFER, + *PCSMI_SAS_PHY_CONTROL_BUFFER; + ++//EDM #pragma CSMI_SAS_END_PACK + #pragma pack() + + #endif // _CSMI_SAS_H_ +diff -r 8807687e8e9c drivers/message/fusion/linux_compat.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/message/fusion/linux_compat.h Tue Sep 01 16:11:22 2009 +0100 +@@ -0,0 +1,73 @@ ++/* drivers/message/fusion/linux_compat.h */ ++#ifndef FUSION_LINUX_COMPAT_H ++#define FUSION_LINUX_COMPAT_H ++ ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef PCI_VENDOR_ID_ATTO ++#define PCI_VENDOR_ID_ATTO 0x117c ++#endif ++ ++#ifndef PCI_VENDOR_ID_BROCADE ++#define PCI_VENDOR_ID_BROCADE 0x1657 ++#endif ++ ++/* ++ * TODO Need to change 'shost_private' back to 'shost_priv' when suppying patchs ++ * upstream. Since Red Hat decided to backport this to rhel5.2 (2.6.18-92.el5) ++ * from the 2.6.23 kernel, it will make it difficult for us to add the proper ++ * glue in our driver. ++ */ ++static inline void *shost_private(struct Scsi_Host *shost) ++{ ++ return (void *)shost->hostdata; ++} ++ ++#ifndef spi_dv_pending ++#define spi_dv_pending(x) (((struct spi_transport_attrs *)&(x)->starget_data)->dv_pending) ++#endif ++#ifndef upper_32_bits ++#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) ++#endif ++#ifndef lower_32_bits ++#define lower_32_bits(n) ((u32)(n)) ++#endif ++/** ++ * mpt_scsilun_to_int: convert a scsi_lun to an int ++ * @scsilun: struct scsi_lun to be converted. ++ * ++ * Description: ++ * Convert @scsilun from a struct scsi_lun to a four byte host byte-ordered ++ * integer, and return the result. The caller must check for ++ * truncation before using this function. ++ * ++ * Notes: ++ * The struct scsi_lun is assumed to be four levels, with each level ++ * effectively containing a SCSI byte-ordered (big endian) short; the ++ * addressing bits of each level are ignored (the highest two bits). ++ * For a description of the LUN format, post SCSI-3 see the SCSI ++ * Architecture Model, for SCSI-3 see the SCSI Controller Commands. ++ * ++ * Given a struct scsi_lun of: 0a 04 0b 03 00 00 00 00, this function returns ++ * the integer: 0x0b030a04 ++ **/ ++static inline int mpt_scsilun_to_int(struct scsi_lun *scsilun) ++{ ++ int i; ++ unsigned int lun; ++ ++ lun = 0; ++ for (i = 0; i < sizeof(lun); i += 2) ++ lun = lun | (((scsilun->scsi_lun[i] << 8) | ++ scsilun->scsi_lun[i + 1]) << (i * 8)); ++ return lun; ++} ++#if (defined(CONFIG_SUSE_KERNEL) && !defined(scsi_is_sas_phy_local)) ++#define SUSE_KERNEL_BASE 1 ++#endif ++/*}-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ ++#endif /* _LINUX_COMPAT_H */ +diff -r 8807687e8e9c drivers/message/fusion/lsi/mpi.h +--- a/drivers/message/fusion/lsi/mpi.h Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/lsi/mpi.h Tue Sep 01 16:11:22 2009 +0100 +@@ -6,7 +6,7 @@ + * Title: MPI Message independent structures and definitions + * Creation Date: July 27, 2000 + * +- * mpi.h Version: 01.05.16 ++ * mpi.h Version: 01.05.17 + * + * Version History + * --------------- +@@ -82,6 +82,7 @@ + * 08-07-07 01.05.14 Bumped MPI_HEADER_VERSION_UNIT. + * 01-15-08 01.05.15 Bumped MPI_HEADER_VERSION_UNIT. + * 03-28-08 01.05.16 Bumped MPI_HEADER_VERSION_UNIT. ++ * 07-11-08 01.05.17 Bumped MPI_HEADER_VERSION_UNIT. + * -------------------------------------------------------------------------- + */ + +@@ -112,7 +113,7 @@ + /* Note: The major versions of 0xe0 through 0xff are reserved */ + + /* versioning for this MPI header set */ +-#define MPI_HEADER_VERSION_UNIT (0x13) ++#define MPI_HEADER_VERSION_UNIT (0x14) + #define MPI_HEADER_VERSION_DEV (0x00) + #define MPI_HEADER_VERSION_UNIT_MASK (0xFF00) + #define MPI_HEADER_VERSION_UNIT_SHIFT (8) +diff -r 8807687e8e9c drivers/message/fusion/lsi/mpi_cnfg.h +--- a/drivers/message/fusion/lsi/mpi_cnfg.h Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/lsi/mpi_cnfg.h Tue Sep 01 16:11:22 2009 +0100 +@@ -6,7 +6,7 @@ + * Title: MPI Config message, structures, and Pages + * Creation Date: July 27, 2000 + * +- * mpi_cnfg.h Version: 01.05.18 ++ * mpi_cnfg.h Version: 01.05.19 + * + * Version History + * --------------- +@@ -322,6 +322,14 @@ + * 03-28-08 01.05.18 Defined new bits in Manufacturing Page 4 ExtFlags field + * to control coercion size and the mixing of SAS and SATA + * SSD drives. ++ * 07-11-08 01.05.19 Added defines MPI_MANPAGE4_EXTFLAGS_RAID0_SINGLE_DRIVE ++ * and MPI_MANPAGE4_EXTFLAGS_SSD_SCRUB_DISABLE for ExtFlags ++ * field of Manufacturing Page 4. ++ * Added defines for a new bit in BIOS Page 1 BiosOptions ++ * field to control adapter scan order. ++ * Added BootDeviceWaitTime field to SAS IO Unit Page 2. ++ * Added MPI_SAS_PHY0_PHYINFO_PHY_VACANT for use in PhyInfo ++ * field of SAS Expander Page 1. + * -------------------------------------------------------------------------- + */ + +@@ -700,6 +708,8 @@ + #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01) + + /* defines for the ExtFlags field */ ++#define MPI_MANPAGE4_EXTFLAGS_RAID0_SINGLE_DRIVE (0x0400) ++#define MPI_MANPAGE4_EXTFLAGS_SSD_SCRUB_DISABLE (0x0200) + #define MPI_MANPAGE4_EXTFLAGS_MASK_COERCION_SIZE (0x0180) + #define MPI_MANPAGE4_EXTFLAGS_SHIFT_COERCION_SIZE (7) + #define MPI_MANPAGE4_EXTFLAGS_1GB_COERCION_SIZE (0) +@@ -1219,6 +1229,10 @@ + #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400) + #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200) + #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100) ++ ++#define MPI_BIOSPAGE1_OPTIONS_SCAN_HIGH_TO_LOW (0x00000002) ++#define MPI_BIOSPAGE1_OPTIONS_SCAN_LOW_TO_HIGH (0x00000000) ++ + #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) + + /* values for the IOCSettings field */ +@@ -1452,7 +1466,8 @@ + #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05) + #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) + +-typedef struct _CONFIG_PAGE_BIOS_4 { ++typedef struct _CONFIG_PAGE_BIOS_4 ++{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U64 ReassignmentBaseWWID; /* 04h */ + } CONFIG_PAGE_BIOS_4, MPI_POINTER PTR_CONFIG_PAGE_BIOS_4, +@@ -2711,7 +2726,7 @@ + { + CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ + U8 NumDevsPerEnclosure; /* 08h */ +- U8 Reserved1; /* 09h */ ++ U8 BootDeviceWaitTime; /* 09h */ + U16 Reserved2; /* 0Ah */ + U16 MaxPersistentIDs; /* 0Ch */ + U16 NumPersistentIDsUsed; /* 0Eh */ +@@ -2721,7 +2736,7 @@ + } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2, + SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t; + +-#define MPI_SASIOUNITPAGE2_PAGEVERSION (0x06) ++#define MPI_SASIOUNITPAGE2_PAGEVERSION (0x07) + + /* values for SAS IO Unit Page 2 Status field */ + #define MPI_SAS_IOUNIT2_STATUS_DEVICE_LIMIT_EXCEEDED (0x08) +@@ -2996,6 +3011,7 @@ + #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) + + /* values for SAS PHY Page 0 PhyInfo field */ ++#define MPI_SAS_PHY0_PHYINFO_PHY_VACANT (0x80000000) + #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000) + #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000) + #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000) +diff -r 8807687e8e9c drivers/message/fusion/lsi/mpi_history.txt +--- a/drivers/message/fusion/lsi/mpi_history.txt Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/lsi/mpi_history.txt Tue Sep 01 16:11:22 2009 +0100 +@@ -6,15 +6,15 @@ + Copyright (c) 2000-2008 LSI Corporation. + + --------------------------------------- +- Header Set Release Version: 01.05.19 +- Header Set Release Date: 03-28-08 ++ Header Set Release Version: 01.05.20 ++ Header Set Release Date: 07-11-08 + --------------------------------------- + + Filename Current version Prior version + ---------- --------------- ------------- +- mpi.h 01.05.16 01.05.15 +- mpi_ioc.h 01.05.16 01.05.15 +- mpi_cnfg.h 01.05.18 01.05.17 ++ mpi.h 01.05.17 01.05.16 ++ mpi_ioc.h 01.05.16 01.05.16 ++ mpi_cnfg.h 01.05.19 01.05.18 + mpi_init.h 01.05.09 01.05.09 + mpi_targ.h 01.05.06 01.05.06 + mpi_fc.h 01.05.01 01.05.01 +@@ -24,7 +24,7 @@ + mpi_inb.h 01.05.01 01.05.01 + mpi_sas.h 01.05.05 01.05.05 + mpi_type.h 01.05.02 01.05.02 +- mpi_history.txt 01.05.19 01.05.18 ++ mpi_history.txt 01.05.20 01.05.19 + + + * Date Version Description +@@ -99,6 +99,7 @@ + * 08-07-07 01.05.14 Bumped MPI_HEADER_VERSION_UNIT. + * 01-15-08 01.05.15 Bumped MPI_HEADER_VERSION_UNIT. + * 03-28-08 01.05.16 Bumped MPI_HEADER_VERSION_UNIT. ++ * 07-11-08 01.05.17 Bumped MPI_HEADER_VERSION_UNIT. + * -------------------------------------------------------------------------- + + mpi_ioc.h +@@ -523,6 +524,14 @@ + * 03-28-08 01.05.18 Defined new bits in Manufacturing Page 4 ExtFlags field + * to control coercion size and the mixing of SAS and SATA + * SSD drives. ++ * 07-11-08 01.05.19 Added defines MPI_MANPAGE4_EXTFLAGS_RAID0_SINGLE_DRIVE ++ * and MPI_MANPAGE4_EXTFLAGS_SSD_SCRUB_DISABLE for ExtFlags ++ * field of Manufacturing Page 4. ++ * Added defines for a new bit in BIOS Page 1 BiosOptions ++ * field to control adapter scan order. ++ * Added BootDeviceWaitTime field to SAS IO Unit Page 2. ++ * Added MPI_SAS_PHY0_PHYINFO_PHY_VACANT for use in PhyInfo ++ * field of SAS Expander Page 1. + * -------------------------------------------------------------------------- + + mpi_init.h +@@ -743,20 +752,20 @@ + + mpi_history.txt Parts list history + +-Filename 01.05.19 01.05.18 01.05.17 01.05.16 01.05.15 +----------- -------- -------- -------- -------- -------- +-mpi.h 01.05.16 01.05.15 01.05.14 01.05.13 01.05.12 +-mpi_ioc.h 01.05.16 01.05.15 01.05.15 01.05.14 01.05.13 +-mpi_cnfg.h 01.05.18 01.05.17 01.05.16 01.05.15 01.05.14 +-mpi_init.h 01.05.09 01.05.09 01.05.09 01.05.09 01.05.09 +-mpi_targ.h 01.05.06 01.05.06 01.05.06 01.05.06 01.05.06 +-mpi_fc.h 01.05.01 01.05.01 01.05.01 01.05.01 01.05.01 +-mpi_lan.h 01.05.01 01.05.01 01.05.01 01.05.01 01.05.01 +-mpi_raid.h 01.05.05 01.05.05 01.05.04 01.05.03 01.05.03 +-mpi_tool.h 01.05.03 01.05.03 01.05.03 01.05.03 01.05.03 +-mpi_inb.h 01.05.01 01.05.01 01.05.01 01.05.01 01.05.01 +-mpi_sas.h 01.05.05 01.05.05 01.05.04 01.05.04 01.05.04 +-mpi_type.h 01.05.02 01.05.02 01.05.02 01.05.02 01.05.02 ++Filename 01.05.20 01.05.19 01.05.18 01.05.17 01.05.16 01.05.15 ++---------- -------- -------- -------- -------- -------- -------- ++mpi.h 01.05.17 01.05.16 01.05.15 01.05.14 01.05.13 01.05.12 ++mpi_ioc.h 01.05.16 01.05.16 01.05.15 01.05.15 01.05.14 01.05.13 ++mpi_cnfg.h 01.05.19 01.05.18 01.05.17 01.05.16 01.05.15 01.05.14 ++mpi_init.h 01.05.09 01.05.09 01.05.09 01.05.09 01.05.09 01.05.09 ++mpi_targ.h 01.05.06 01.05.06 01.05.06 01.05.06 01.05.06 01.05.06 ++mpi_fc.h 01.05.01 01.05.01 01.05.01 01.05.01 01.05.01 01.05.01 ++mpi_lan.h 01.05.01 01.05.01 01.05.01 01.05.01 01.05.01 01.05.01 ++mpi_raid.h 01.05.05 01.05.05 01.05.05 01.05.04 01.05.03 01.05.03 ++mpi_tool.h 01.05.03 01.05.03 01.05.03 01.05.03 01.05.03 01.05.03 ++mpi_inb.h 01.05.01 01.05.01 01.05.01 01.05.01 01.05.01 01.05.01 ++mpi_sas.h 01.05.05 01.05.05 01.05.05 01.05.04 01.05.04 01.05.04 ++mpi_type.h 01.05.02 01.05.02 01.05.02 01.05.02 01.05.02 01.05.02 + + Filename 01.05.14 01.05.13 01.05.12 01.05.11 01.05.10 01.05.09 + ---------- -------- -------- -------- -------- -------- -------- +diff -r 8807687e8e9c drivers/message/fusion/lsi/mpi_log_sas.h +--- a/drivers/message/fusion/lsi/mpi_log_sas.h Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/lsi/mpi_log_sas.h Tue Sep 01 16:11:22 2009 +0100 +@@ -160,12 +160,11 @@ + + + #define PL_LOGINFO_SUB_CODE_INVALID_SGL (0x00000200) +- + #define PL_LOGINFO_SUB_CODE_WRONG_REL_OFF_OR_FRAME_LENGTH (0x00000300) +-/* Bits 0-3 encode Transport Status Register (offset 0x08) */ +-/* Bit 0 is Status Bit 0: FrameXferErr */ +-/* Bit 1 & 2 are Status Bits 16 and 17: FrameXmitErrStatus */ +-/* Bit 3 is Status Bit 18 WriteDataLenghtGTDataLengthErr */ ++#define PL_LOGINFO_SUB_CODE_FRAME_XFER_ERROR (0x00000400) /* Bits 0-3 encode Transport Status Register (offset 0x08) */ ++ /* Bit 0 is Status Bit 0: FrameXferErr */ ++ /* Bit 1 & 2 are Status Bits 16 and 17: FrameXmitErrStatus */ ++ /* Bit 3 is Status Bit 18 WriteDataLenghtGTDataLengthErr */ + + #define PL_LOGINFO_SUB_CODE_TX_FM_CONNECTED_LOW (0x00000500) + #define PL_LOGINFO_SUB_CODE_SATA_NON_NCQ_RW_ERR_BIT_SET (0x00000600) +@@ -180,7 +179,7 @@ + #define PL_LOGINFO_SUB_CODE_DISCOVERY_REMOTE_SEP_RESET (0x00000E01) + #define PL_LOGINFO_SUB_CODE_SECOND_OPEN (0x00000F00) + #define PL_LOGINFO_SUB_CODE_DSCVRY_SATA_INIT_TIMEOUT (0x00001000) +-#define PL_LOGINFO_SUB_CODE_BREAK_ON_SATA_CONNECTION (0x00002000) ++#define PL_LOGINFO_SUB_CODE_BREAK_ON_SATA_CONNECTION (0x00002000) /* not currently used in mainline */ + #define PL_LOGINFO_SUB_CODE_BREAK_ON_STUCK_LINK (0x00003000) + #define PL_LOGINFO_SUB_CODE_BREAK_ON_STUCK_LINK_AIP (0x00004000) + #define PL_LOGINFO_SUB_CODE_BREAK_ON_INCOMPLETE_BREAK_RCVD (0x00005000) +@@ -309,6 +308,7 @@ + /* Device Firmware Update: Unable to allocate memory for page */ + #define IR_LOGINFO_DEV_FW_UPDATE_ERR_ALLOC_CFG_PAGE (0x00010056) + /* Device Firmware Update: */ ++//#define IR_LOGINFO_DEV_FW_UPDATE_ERR_ (0x00010054) + + + /****************************************************************************/ +diff -r 8807687e8e9c drivers/message/fusion/lsi/mpi_type.h +--- a/drivers/message/fusion/lsi/mpi_type.h Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/lsi/mpi_type.h Tue Sep 01 16:11:22 2009 +0100 +@@ -50,8 +50,18 @@ + typedef unsigned short U16; + + +-typedef int32_t S32; +-typedef u_int32_t U32; ++#if defined(unix) || defined(__arm) || defined(ALPHA) || defined(__PPC__) || defined(__ppc) ++ ++ typedef signed int S32; ++ typedef unsigned int U32; ++ ++#else ++ ++ typedef signed long S32; ++ typedef unsigned long U32; ++ ++#endif ++ + + typedef struct _S64 + { +diff -r 8807687e8e9c drivers/message/fusion/mptbase.c +--- a/drivers/message/fusion/mptbase.c Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/mptbase.c Tue Sep 01 16:11:22 2009 +0100 +@@ -45,7 +45,7 @@ + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +- ++#include + #include + #include + #include +@@ -65,6 +65,7 @@ + #endif + + #include "mptbase.h" ++#include "linux_compat.h" /* linux-2.6 tweaks */ + #include "lsi/mpi_log_fc.h" + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +@@ -83,18 +84,18 @@ + + static int mpt_msi_enable_spi; + module_param(mpt_msi_enable_spi, int, 0); +-MODULE_PARM_DESC(mpt_msi_enable_spi, +- " Enable MSI Support for SPI controllers (default=0)"); ++MODULE_PARM_DESC(mpt_msi_enable_spi, " Enable MSI Support for SPI \ ++ controllers (default=0)"); + + static int mpt_msi_enable_fc; + module_param(mpt_msi_enable_fc, int, 0); +-MODULE_PARM_DESC(mpt_msi_enable_fc, +- " Enable MSI Support for FC controllers (default=0)"); +- +-static int mpt_msi_enable_sas = 1; ++MODULE_PARM_DESC(mpt_msi_enable_fc, " Enable MSI Support for FC \ ++ controllers (default=0)"); ++ ++static int mpt_msi_enable_sas; + module_param(mpt_msi_enable_sas, int, 0); +-MODULE_PARM_DESC(mpt_msi_enable_sas, +- " Enable MSI Support for SAS controllers (default=1)"); ++MODULE_PARM_DESC(mpt_msi_enable_sas, " Enable MSI Support for SAS \ ++ controllers (default=0)"); + + + static int mpt_channel_mapping; +@@ -102,20 +103,20 @@ + MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)"); + + int mpt_debug_level; +-EXPORT_SYMBOL(mpt_debug_level); +- + static int mpt_set_debug_level(const char *val, struct kernel_param *kp); + module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int, + &mpt_debug_level, 0600); +-MODULE_PARM_DESC(mpt_debug_level, +- " debug level - refer to mptdebug.h - (default=0)"); ++MODULE_PARM_DESC(mpt_debug_level, " debug level - refer to mptdebug.h \ ++ - (default=0)"); ++EXPORT_SYMBOL(mpt_debug_level); + + int mpt_fwfault_debug; + EXPORT_SYMBOL(mpt_fwfault_debug); + module_param_call(mpt_fwfault_debug, param_set_int, param_get_int, +- &mpt_fwfault_debug, 0600); ++ &mpt_fwfault_debug, 0600); + MODULE_PARM_DESC(mpt_fwfault_debug, "Enable detection of Firmware fault" +- " and halt Firmware on fault - (default=0)"); ++ " and halt Firmware on fault - (default=0)"); ++ + + + #ifdef MFCNT +@@ -127,7 +128,8 @@ + /* + * Public data... + */ +-static struct proc_dir_entry *mpt_proc_root_dir; ++ ++struct proc_dir_entry *mpt_proc_root_dir; + + #define WHOINIT_UNKNOWN 0xAA + +@@ -147,9 +149,6 @@ + static MPT_RESETHANDLER MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS]; + static struct mpt_pci_driver *MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS]; + +-static DECLARE_WAIT_QUEUE_HEAD(mpt_waitq); +- +-/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + + /* + * Driver Callback Index's +@@ -162,7 +161,7 @@ + * Forward protos... + */ + static int mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, +- MPT_FRAME_HDR *reply); ++ MPT_FRAME_HDR *reply); + static int mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, + u32 *req, int replyBytes, u16 *u16reply, int maxwait, + int sleepFlag); +@@ -195,7 +194,7 @@ + static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc); + static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc); + static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, +- int sleepFlag); ++ int sleepFlag); + static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp); + static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag); + static int mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init); +@@ -210,7 +209,8 @@ + #endif + static void mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc); + +-static int ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *evReply, int *evHandlers); ++static int ProcessEventNotification(MPT_ADAPTER *ioc, ++ EventNotificationReply_t *evReply, int *evHandlers); + static void mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf); + static void mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info); + static void mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info); +@@ -218,7 +218,6 @@ + static int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc); + static void mpt_inactive_raid_list_free(MPT_ADAPTER *ioc); + +- + /* module entry point */ + static int __init fusion_init (void); + static void __exit fusion_exit (void); +@@ -257,8 +256,8 @@ + * + * Returns + **/ +-static int +-mpt_set_debug_level(const char *val, struct kernel_param *kp) ++ ++static int mpt_set_debug_level(const char *val, struct kernel_param *kp) + { + int ret = param_set_int(val, kp); + MPT_ADAPTER *ioc; +@@ -344,10 +343,16 @@ + * + **/ + static void ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + mpt_fault_reset_work(struct work_struct *work) + { + MPT_ADAPTER *ioc = + container_of(work, MPT_ADAPTER, fault_reset_work.work); ++#else ++mpt_fault_reset_work(void *arg) ++{ ++ MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg; ++#endif + u32 ioc_raw_state; + int rc; + unsigned long flags; +@@ -358,12 +363,12 @@ + ioc_raw_state = mpt_GetIocState(ioc, 0); + if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) { + printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n", +- ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK); ++ ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK); + printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n", +- ioc->name, __func__); ++ ioc->name, __func__); + rc = mpt_HardResetHandler(ioc, CAN_SLEEP); + printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name, +- __func__, (rc == 0) ? "success" : "failed"); ++ __func__, (rc == 0) ? "success" : "failed"); + ioc_raw_state = mpt_GetIocState(ioc, 0); + if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) + printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after " +@@ -385,12 +390,13 @@ + ioc = ioc->alt_ioc; + + /* rearm the timer */ +- spin_lock_irqsave(&ioc->fault_reset_work_lock, flags); ++ spin_lock_irqsave(&ioc->taskmgmt_lock, flags); + if (ioc->reset_work_q) + queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work, + msecs_to_jiffies(MPT_POLLING_INTERVAL)); +- spin_unlock_irqrestore(&ioc->fault_reset_work_lock, flags); +-} ++ spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); ++} ++ + + /* + * Process turbo (context) reply... +@@ -444,7 +450,7 @@ + + /* Check for (valid) IO callback! */ + if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS || +- MptCallbacks[cb_idx] == NULL) { ++ MptCallbacks[cb_idx] == NULL) { + printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n", + __func__, ioc->name, cb_idx); + goto out; +@@ -488,7 +494,6 @@ + + dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n", + ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function)); +- + DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr); + + /* Check/log IOC log info +@@ -504,12 +509,15 @@ + mpt_sas_log_info(ioc, log_info); + } + ++ /* TODO - add shost_attrs, or command line option, and ++ * extend this to SAS/FC ++ */ + if (ioc_stat & MPI_IOCSTATUS_MASK) + mpt_iocstatus_info(ioc, (u32)ioc_stat, mf); + + /* Check for (valid) IO callback! */ + if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS || +- MptCallbacks[cb_idx] == NULL) { ++ MptCallbacks[cb_idx] == NULL) { + printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n", + __func__, ioc->name, cb_idx); + freeme = 0; +@@ -545,7 +553,11 @@ + * the protocol-specific details of the MPT request completion. + */ + static irqreturn_t ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) + mpt_interrupt(int irq, void *bus_id) ++#else ++mpt_interrupt(int irq, void *bus_id, struct pt_regs *r) ++#endif + { + MPT_ADAPTER *ioc = bus_id; + u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo); +@@ -720,7 +732,7 @@ + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** +- * mpt_event_deregister - Deregister protocol-specific event callback handler. ++ * mpt_event_deregister - Deregister protocol-specific event callback handler + * @cb_idx: previously registered callback handle + * + * Each protocol-specific driver should call this routine +@@ -794,11 +806,13 @@ + + /* call per pci device probe entry point */ + list_for_each_entry(ioc, &ioc_list, list) { ++ if (!pci_get_drvdata(ioc->pcidev)) ++ continue; + id = ioc->pcidev->driver ? + ioc->pcidev->driver->id_table : NULL; + if (dd_cbfunc->probe) + dd_cbfunc->probe(ioc->pcidev, id); +- } ++ } + + return 0; + } +@@ -826,6 +840,7 @@ + + MptDeviceDriverHandlers[cb_idx] = NULL; + } ++ + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** +@@ -868,6 +883,7 @@ + mf->u.frame.linkage.arg1 = 0; + mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */ + req_offset = (u8 *)mf - (u8 *)ioc->req_frames; ++ /* u16! */ + req_idx = req_offset / ioc->req_sz; + mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); + mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; +@@ -917,6 +933,7 @@ + /* ensure values are reset properly! */ + mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */ + req_offset = (u8 *)mf - (u8 *)ioc->req_frames; ++ /* u16! */ + req_idx = req_offset / ioc->req_sz; + mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); + mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; +@@ -968,7 +985,6 @@ + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** + * mpt_free_msg_frame - Place MPT request frame back on FreeQ. +- * @handle: Handle of registered MPT protocol driver + * @ioc: Pointer to MPT adapter structure + * @mf: Pointer to MPT request frame + * +@@ -994,6 +1010,7 @@ + spin_unlock_irqrestore(&ioc->FreeQlock, flags); + } + ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** + * mpt_add_sge - Place a simple 32 bit SGE at address pAddr. + * @pAddr: virtual address for SGE +@@ -1002,15 +1019,14 @@ + * + * This routine places a MPT request frame back on the MPT adapter's + * FreeQ. +- **/ +-static void +-mpt_add_sge(char *pAddr, u32 flagslength, dma_addr_t dma_addr) ++ */ ++static void ++mpt_add_sge(void *pAddr, u32 flagslength, dma_addr_t dma_addr) + { + SGESimple32_t *pSge = (SGESimple32_t *) pAddr; + pSge->FlagsLength = cpu_to_le32(flagslength); + pSge->Address = cpu_to_le32(dma_addr); + } +- + + /** + * mpt_add_sge_64bit - Place a simple 64 bit SGE at address pAddr. +@@ -1022,19 +1038,16 @@ + * FreeQ. + **/ + static void +-mpt_add_sge_64bit(char *pAddr, u32 flagslength, dma_addr_t dma_addr) ++mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr) + { + SGESimple64_t *pSge = (SGESimple64_t *) pAddr; +- u32 tmp; +- +- tmp = dma_addr & 0xFFFFFFFF; +- pSge->Address.Low = cpu_to_le32(tmp); +- tmp = (u32) ((u64)dma_addr >> 32); +- pSge->Address.High = cpu_to_le32(tmp); +- pSge->FlagsLength = cpu_to_le32( +- (flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING)); +-} +- ++ pSge->Address.Low = cpu_to_le32 ++ (lower_32_bits(dma_addr)); ++ pSge->Address.High = cpu_to_le32 ++ (upper_32_bits(dma_addr)); ++ pSge->FlagsLength = cpu_to_le32 ++ ((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING)); ++} + + /** + * mpt_add_sge_64bit_1078 - Place a simple 64 bit SGE at address pAddr +@@ -1047,14 +1060,14 @@ + * FreeQ. + **/ + static void +-mpt_add_sge_64bit_1078(char *pAddr, u32 flagslength, dma_addr_t dma_addr) ++mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr) + { + SGESimple64_t *pSge = (SGESimple64_t *) pAddr; + u32 tmp; + +- tmp = dma_addr & 0xFFFFFFFF; +- pSge->Address.Low = cpu_to_le32(tmp); +- tmp = (u32) ((u64)dma_addr >> 32); ++ pSge->Address.Low = cpu_to_le32 ++ (lower_32_bits(dma_addr)); ++ tmp = (u32)(upper_32_bits(dma_addr)); + + /* + * 1078 errata workaround for the 36GB limitation +@@ -1085,7 +1098,7 @@ + * + */ + static void +-mpt_add_chain(char *pAddr, u8 next, u16 length, dma_addr_t dma_addr) ++mpt_add_chain(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr) + { + SGEChain32_t *pChain = (SGEChain32_t *) pAddr; + pChain->Length = cpu_to_le16(length); +@@ -1104,7 +1117,7 @@ + * + */ + static void +-mpt_add_chain_64bit(char *pAddr, u8 next, u16 length, dma_addr_t dma_addr) ++mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr) + { + SGEChain64_t *pChain = (SGEChain64_t *) pAddr; + u32 tmp = dma_addr & 0xFFFFFFFF; +@@ -1116,10 +1129,9 @@ + pChain->NextChainOffset = next; + + pChain->Address.Low = cpu_to_le32(tmp); +- tmp = (u32) ((u64)dma_addr >> 32); ++ tmp = (u32)(upper_32_bits(dma_addr)); + pChain->Address.High = cpu_to_le32(tmp); + } +- + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** +@@ -1141,7 +1153,7 @@ + int + mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag) + { +- int r = 0; ++ int r = 0; + u8 *req_as_bytes; + int ii; + +@@ -1232,6 +1244,7 @@ + * + * Returns 0 for success, non-zero for failure. + */ ++ + static int + mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag) + { +@@ -1288,7 +1301,7 @@ + host_page_buffer_sz, + &ioc->HostPageBuffer_dma)) != NULL) { + +- dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ++ dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT + "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n", + ioc->name, ioc->HostPageBuffer, + (u32)ioc->HostPageBuffer_dma, +@@ -1597,6 +1610,7 @@ + * @ioc: Pointer to pointer to IOC adapter + * + **/ ++#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10)) + static int + mpt_mapresources(MPT_ADAPTER *ioc) + { +@@ -1608,48 +1622,82 @@ + u32 psize; + int r = -ENODEV; + struct pci_dev *pdev; ++ struct sysinfo s; + + pdev = ioc->pcidev; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) ++ if (pci_enable_device(pdev)) { ++ printk(MYIOC_s_WARN_FMT "pci_enable_device: failed\n", ++ ioc->name); ++ return r; ++ } ++#else + ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)) ++ if (pci_enable_device_bars(pdev, ioc->bars)) { ++ printk(MYIOC_s_ERR_FMT "pci_enable_device_bars() with MEM " ++ "failed\n",ioc->name); ++ return r; ++ } ++#else + if (pci_enable_device_mem(pdev)) { + printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() " + "failed\n", ioc->name); + return r; + } ++#endif + if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) { + printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with " + "MEM failed\n", ioc->name); + return r; + } ++#endif + if (sizeof(dma_addr_t) > 4) { + uint64_t required_mask; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) ++ /*have to first set mask to 64 bits to find max mask required */ ++ if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) != 0) { ++ printk(MYIOC_s_WARN_FMT ++ "unable to set dma mask to 64BIT for %s\n", ++ ioc->name, pci_name(pdev)); ++ if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) { ++ printk(MYIOC_s_WARN_FMT ++ "unable to set dma mask to 32BIT for %s\n", ++ ioc->name, pci_name(pdev)); ++ return r; ++ } ++ } ++#endif ++ + required_mask = dma_get_required_mask(&pdev->dev); ++ + if (required_mask > DMA_32BIT_MASK +- && !pci_set_dma_mask(pdev, DMA_64BIT_MASK) +- && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) { ++ && !pci_set_dma_mask(pdev, DMA_64BIT_MASK) ++ && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) { + ioc->dma_mask = DMA_64BIT_MASK; + dinitprintk(ioc, printk(MYIOC_s_INFO_FMT +- ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", +- ioc->name)); ++ ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", ++ ioc->name)); + } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK) +- && !pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { ++ && !pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { + ioc->dma_mask = DMA_32BIT_MASK; + dinitprintk(ioc, printk(MYIOC_s_INFO_FMT +- ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", +- ioc->name)); ++ ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", ++ ioc->name)); + } else { + printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n", + ioc->name, pci_name(pdev)); + return r; + } +- + } else { + if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK) +- && !pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { ++ && !pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { + ioc->dma_mask = DMA_32BIT_MASK; + dinitprintk(ioc, printk(MYIOC_s_INFO_FMT +- ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", +- ioc->name)); ++ ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", ++ ioc->name)); + } else { + printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n", + ioc->name, pci_name(pdev)); +@@ -1657,6 +1705,11 @@ + } + } + ++ si_meminfo(&s); ++ printk(MYIOC_s_INFO_FMT "%s BIT PCI BUS DMA ADDRESSING SUPPORTED, " ++ "total memory = %ld kB\n", ++ ioc->name, ioc->dma_mask == DMA_64BIT_MASK ? "64" : "32", ++ convert_to_kb(s.totalram)); + mem_phys = msize = 0; + port = psize = 0; + for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) { +@@ -1682,7 +1735,7 @@ + mem = ioremap(mem_phys, msize); + if (mem == NULL) { + printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter" +- "memory!\n", ioc->name); ++ " memory!\n", ioc->name); + return -EINVAL; + } + ioc->memmap = mem; +@@ -1715,6 +1768,7 @@ + * + * Returns 0 for success, non-zero for failure. + * ++ * TODO: Add support for polled controllers + */ + int + mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id) +@@ -1748,6 +1802,7 @@ + if (mpt_debug_level) + printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level); + ++ dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name)); + + ioc->pcidev = pdev; + if (mpt_mapresources(ioc)) { +@@ -1775,6 +1830,9 @@ + ioc->alloc_total = sizeof(MPT_ADAPTER); + ioc->req_sz = MPT_DEFAULT_FRAME_SIZE; /* avoid div by zero! */ + ioc->reply_sz = MPT_REPLY_FRAME_SIZE; ++ ++ ioc->pcidev = pdev; ++ + + spin_lock_init(&ioc->taskmgmt_lock); + mutex_init(&ioc->internal_cmds.mutex); +@@ -1810,25 +1868,30 @@ + INIT_LIST_HEAD(&ioc->list); + + /* Initialize work */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work); +- spin_lock_init(&ioc->fault_reset_work_lock); ++#else ++ INIT_WORK(&ioc->fault_reset_work, mpt_fault_reset_work, (void *)ioc); ++#endif + + /* Initialize workqueue */ +- snprintf(ioc->reset_work_q_name, sizeof(ioc->reset_work_q_name), ++ ++ snprintf(ioc->reset_work_q_name, MPT_KOBJ_NAME_LEN, + "mpt_poll_%d", ioc->id); + ioc->reset_work_q = + create_singlethread_workqueue(ioc->reset_work_q_name); + if (!ioc->reset_work_q) { + printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n", + ioc->name); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) + pci_release_selected_regions(pdev, ioc->bars); ++#endif + kfree(ioc); + return -ENOMEM; + } + +- dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts @ %p," +- " pfacts[0] @ %p\n", +- ioc->name, &ioc->facts, &ioc->pfacts[0])); ++ dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n", ++ ioc->name, &ioc->facts, &ioc->pfacts[0])); + + pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision); + mpt_get_product_name(pdev->vendor, pdev->device, revision, ioc->prod_name); +@@ -1848,14 +1911,14 @@ + case MPI_MANUFACTPAGE_DEVICEID_FC929X: + if (revision < XL_929) { + /* 929X Chip Fix. Set Split transactions level +- * for PCIX. Set MOST bits to zero. +- */ ++ * for PCIX. Set MOST bits to zero. ++ */ + pci_read_config_byte(pdev, 0x6a, &pcixcmd); + pcixcmd &= 0x8F; + pci_write_config_byte(pdev, 0x6a, pcixcmd); + } else { + /* 929XL Chip Fix. Set MMRBC to 0x08. +- */ ++ */ + pci_read_config_byte(pdev, 0x6a, &pcixcmd); + pcixcmd |= 0x08; + pci_write_config_byte(pdev, 0x6a, pcixcmd); +@@ -1873,7 +1936,6 @@ + ioc->bus_type = FC; + break; + +- + case MPI_MANUFACTPAGE_DEVID_53C1030: + /* 1030 Chip Fix. Disable Split transactions + * for PCIX. Set MOST bits to zero if Rev < C0( = 8). +@@ -1901,7 +1963,9 @@ + break; + } + ++ + switch (ioc->bus_type) { ++ + case SAS: + ioc->msi_enable = mpt_msi_enable_sas; + break; +@@ -1918,7 +1982,6 @@ + ioc->msi_enable = 0; + break; + } +- + if (ioc->errata_flag_1064) + pci_disable_io_access(pdev); + +@@ -1939,29 +2002,27 @@ + */ + mpt_detect_bound_ports(ioc, pdev); + +- + INIT_LIST_HEAD(&ioc->fw_event_list); + spin_lock_init(&ioc->fw_event_lock); +- snprintf(ioc->fw_event_q_name, sizeof(ioc->fw_event_q_name), +- "mpt/%d", ioc->id); ++ snprintf(ioc->fw_event_q_name, MPT_KOBJ_NAME_LEN, "mpt/%d", ioc->id); + ioc->fw_event_q = create_singlethread_workqueue(ioc->fw_event_q_name); + + if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP, + CAN_SLEEP)) != 0){ + printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n", +- ioc->name, r); ++ ioc->name, r); + + list_del(&ioc->list); + if (ioc->alt_ioc) + ioc->alt_ioc->alt_ioc = NULL; + iounmap(ioc->memmap); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) + if (r != -5) + pci_release_selected_regions(pdev, ioc->bars); +- ++#endif + destroy_workqueue(ioc->reset_work_q); + ioc->reset_work_q = NULL; +- destroy_workqueue(ioc->fw_event_q); +- ioc->fw_event_q = NULL; ++ + kfree(ioc); + pci_set_drvdata(pdev, NULL); + return r; +@@ -1997,6 +2058,7 @@ + if (!ioc->alt_ioc) + queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work, + msecs_to_jiffies(MPT_POLLING_INTERVAL)); ++ + return 0; + } + +@@ -2005,22 +2067,23 @@ + * mpt_detach - Remove a PCI intelligent MPT adapter. + * @pdev: Pointer to pci_dev structure + */ ++ + void + mpt_detach(struct pci_dev *pdev) + { + MPT_ADAPTER *ioc = pci_get_drvdata(pdev); + char pname[32]; + u8 cb_idx; +- unsigned long flags; ++ unsigned long flags; + struct workqueue_struct *wq; + + /* + * Stop polling ioc for fault condition + */ +- spin_lock_irqsave(&ioc->fault_reset_work_lock, flags); ++ spin_lock_irqsave(&ioc->taskmgmt_lock, flags); + wq = ioc->reset_work_q; + ioc->reset_work_q = NULL; +- spin_unlock_irqrestore(&ioc->fault_reset_work_lock, flags); ++ spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); + cancel_delayed_work(&ioc->fault_reset_work); + destroy_workqueue(wq); + +@@ -2045,7 +2108,20 @@ + } + } + ++ /* Disable interrupts! */ ++ CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); ++ ++ ioc->active = 0; ++ synchronize_irq(pdev->irq); ++ ++ /* Clear any lingering interrupt */ ++ CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); ++ ++ CHIPREG_READ32(&ioc->chip->IntStatus); ++ + mpt_adapter_dispose(ioc); ++ ++ pci_set_drvdata(pdev, NULL); + } + + /************************************************************************** +@@ -2078,6 +2154,7 @@ + /* disable interrupts */ + CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); + ioc->active = 0; ++ + /* Clear any lingering interrupt */ + CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); + +@@ -2087,7 +2164,9 @@ + ioc->pci_irq = -1; + pci_save_state(pdev); + pci_disable_device(pdev); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) + pci_release_selected_regions(pdev, ioc->bars); ++#endif + pci_set_power_state(pdev, device_state); + return 0; + } +@@ -2132,7 +2211,6 @@ + } + ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size; + +- + printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n", + ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT), + CHIPREG_READ32(&ioc->chip->Doorbell)); +@@ -2157,7 +2235,7 @@ + /* bring ioc to operational state */ + printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name); + recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP, +- CAN_SLEEP); ++ CAN_SLEEP); + if (recovery_state != 0) + printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, " + "error:[%x]\n", ioc->name, recovery_state); +@@ -2166,6 +2244,7 @@ + "pci-resume: success\n", ioc->name); + out: + return 0; ++ + } + #endif + +@@ -2219,7 +2298,7 @@ + int irq_allocated = 0; + u8 *a; + +- printk(MYIOC_s_DEBUG_FMT "Initiating %s\n", ioc->name, ++ printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name, + reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery"); + + /* Disable reply interrupts (also blocks FreeQ) */ +@@ -2227,12 +2306,16 @@ + ioc->active = 0; + + if (ioc->alt_ioc) { +- if (ioc->alt_ioc->active || reason == MPT_HOSTEVENT_IOC_RECOVER) ++ if (ioc->alt_ioc->active || ++ reason == MPT_HOSTEVENT_IOC_RECOVER) { + reset_alt_ioc_active = 1; +- +- /* Disable alt-IOC's reply interrupts (and FreeQ) for a bit ... */ +- CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, 0xFFFFFFFF); +- ioc->alt_ioc->active = 0; ++ /* Disable alt-IOC's reply interrupts ++ * (and FreeQ) for a bit ++ **/ ++ CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, ++ 0xFFFFFFFF); ++ ioc->alt_ioc->active = 0; ++ } + } + + hard = 1; +@@ -2246,16 +2329,15 @@ + + if (reset_alt_ioc_active && ioc->alt_ioc) { + /* (re)Enable alt-IOC! (reply interrupt, FreeQ) */ +- dprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- ": alt-ioc reply irq re-enabled\n", +- ioc->alt_ioc->name)); ++ dprintk(ioc, printk(MYIOC_s_INFO_FMT ++ "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name)); + CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM); + ioc->alt_ioc->active = 1; + } + + } else { +- printk(MYIOC_s_WARN_FMT "NOT READY WARNING!\n", +- ioc->name); ++ printk(MYIOC_s_WARN_FMT ++ "NOT READY WARNING!\n", ioc->name); + } + ret = -1; + goto out; +@@ -2264,6 +2346,15 @@ + /* hard_reset_done = 0 if a soft reset was performed + * and 1 if a hard reset was performed. + */ ++ if (!hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) { ++ /* (re)Enable alt-IOC! (reply interrupt, FreeQ) */ ++ dprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": alt-ioc reply irq re-enabled\n", ++ ioc->alt_ioc->name)); ++ CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM); ++ ioc->alt_ioc->active = 1; ++ reset_alt_ioc_active = 0; ++ } ++ + if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) { + if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0) + alt_ioc_ready = 1; +@@ -2291,7 +2382,8 @@ + if (alt_ioc_ready) { + if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) { + dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "Initial Alt IocFacts failed rc=%x\n", ioc->name, rc)); ++ "Initial Alt IocFacts failed rc=%x\n", ++ ioc->name, rc)); + /* Retry - alt IOC was initialized once + */ + rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason); +@@ -2306,17 +2398,24 @@ + } + } + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) + if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) && + (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) { + pci_release_selected_regions(ioc->pcidev, ioc->bars); + ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM | + IORESOURCE_IO); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)) ++ if (pci_enable_device_bars(ioc->pcidev, ioc->bars)) ++ return -5; ++#else + if (pci_enable_device(ioc->pcidev)) + return -5; ++#endif + if (pci_request_selected_regions(ioc->pcidev, ioc->bars, + "mpt")) + return -5; + } ++#endif + + /* + * Device is reset now. It must have de-asserted the interrupt line +@@ -2328,16 +2427,21 @@ + if (ioc->pcidev->irq) { + if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev)) + printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n", +- ioc->name); ++ ioc->name); + else + ioc->msi_enable = 0; + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) + rc = request_irq(ioc->pcidev->irq, mpt_interrupt, + IRQF_SHARED, ioc->name, ioc); ++#else ++ rc = request_irq(ioc->pcidev->irq, mpt_interrupt, ++ SA_SHIRQ, ioc->name, ioc); ++#endif + if (rc < 0) { + printk(MYIOC_s_ERR_FMT "Unable to allocate " +- "interrupt %d!\n", ioc->name, +- ioc->pcidev->irq); ++ "interrupt %d!\n", ++ ioc->name, ioc->pcidev->irq); + if (ioc->msi_enable) + pci_disable_msi(ioc->pcidev); + ret = -EBUSY; +@@ -2392,7 +2496,7 @@ + if (reason == MPT_HOSTEVENT_IOC_BRINGUP){ + if (ioc->upload_fw) { + ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "firmware upload required!\n", ioc->name)); ++ "firmware upload required!\n", ioc->name)); + + /* Controller is not operational, cannot do upload + */ +@@ -2426,7 +2530,8 @@ + */ + if ((ret == 0) && (!ioc->facts.EventState)) { + dinitprintk(ioc, printk(MYIOC_s_INFO_FMT +- "SendEventNotification\n", ioc->name)); ++ "SendEventNotification\n", ++ ioc->name)); + ret = SendEventNotification(ioc, 1, sleepFlag); /* 1=Enable */ + } + +@@ -2441,11 +2546,11 @@ + if (rc == 0) { /* alt ioc */ + if (reset_alt_ioc_active && ioc->alt_ioc) { + /* (re)Enable alt-IOC! (reply interrupt) */ +- dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "alt-ioc reply irq re-enabled\n", ++ dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "alt-ioc" ++ "reply irq re-enabled\n", + ioc->alt_ioc->name)); + CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, +- MPI_HIM_DIM); ++ MPI_HIM_DIM); + ioc->alt_ioc->active = 1; + } + } +@@ -2462,7 +2567,7 @@ + /* + * Initalize link list for inactive raid volumes. + */ +- mutex_init(&ioc->raid_data.inactive_list_mutex); ++ init_MUTEX(&ioc->raid_data.inactive_list_mutex); + INIT_LIST_HEAD(&ioc->raid_data.inactive_list); + + switch (ioc->bus_type) { +@@ -2496,8 +2601,7 @@ + * (LANPage1_t stuff) + */ + (void) GetLanConfigPages(ioc); +- a = (u8 *) +- &ioc->lan_cnfg_page1.HardwareAddressLow; ++ a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; + dprintk(ioc, printk(MYIOC_s_DEBUG_FMT + "LanAddr = %02X:%02X:%02X" + ":%02X:%02X:%02X\n", +@@ -2534,7 +2638,6 @@ + } + + out: +- + if ((ret != 0) && irq_allocated) { + free_irq(ioc->pci_irq, ioc); + if (ioc->msi_enable) +@@ -2566,8 +2669,8 @@ + + dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x," + " searching for devfn match on %x or %x\n", +- ioc->name, pci_name(pdev), pdev->bus->number, +- pdev->devfn, func-1, func+1)); ++ ioc->name, pci_name(pdev), pdev->bus->number, ++ pdev->devfn, func-1, func+1)); + + peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1)); + if (!peer) { +@@ -2614,8 +2717,8 @@ + int ret; + + if (ioc->cached_fw != NULL) { +- ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_adapter_disable: " +- "Pushing FW onto adapter\n", ioc->name)); ++ ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "%s: Pushing FW onto adapter\n", __func__, ioc->name)); + if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *) + ioc->cached_fw, CAN_SLEEP)) < 0) { + printk(MYIOC_s_WARN_FMT +@@ -2628,15 +2731,15 @@ + * Put the controller into ready state (if its not already) + */ + if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) { +- if (!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, ++ if(!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, + CAN_SLEEP)) { + if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) + printk(MYIOC_s_ERR_FMT "%s: IOC msg unit " + "reset failed to put ioc in ready state!\n", +- ioc->name, __func__); ++ ioc->name, __FUNCTION__); + } else + printk(MYIOC_s_ERR_FMT "%s: IOC msg unit reset " +- "failed!\n", ioc->name, __func__); ++ "failed!\n", ioc->name, __FUNCTION__); + } + + /* Disable adapter interrupts! */ +@@ -2650,9 +2753,8 @@ + + if (ioc->alloc != NULL) { + sz = ioc->alloc_sz; +- dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "free @ %p, sz=%d bytes\n", ioc->name, +- ioc->alloc, ioc->alloc_sz)); ++ dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free @ %p, sz=%d bytes\n", ++ ioc->name, ioc->alloc, ioc->alloc_sz)); + pci_free_consistent(ioc->pcidev, sz, + ioc->alloc, ioc->alloc_dma); + ioc->reply_frames = NULL; +@@ -2713,11 +2815,11 @@ + ioc->name, __func__, ret); + } + dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "HostPageBuffer free @ %p, sz=%d bytes\n", ioc->name, +- ioc->HostPageBuffer, ioc->HostPageBuffer_sz)); ++ "HostPageBuffer free @ %p, sz=%d bytes\n", ++ ioc->name, ioc->HostPageBuffer, ++ ioc->HostPageBuffer_sz)); + pci_free_consistent(ioc->pcidev, ioc->HostPageBuffer_sz, +- ioc->HostPageBuffer, +- ioc->HostPageBuffer_dma); ++ ioc->HostPageBuffer, ioc->HostPageBuffer_dma); + ioc->HostPageBuffer = NULL; + ioc->HostPageBuffer_sz = 0; + ioc->alloc_total -= ioc->HostPageBuffer_sz; +@@ -2725,7 +2827,6 @@ + + pci_set_drvdata(ioc->pcidev, NULL); + } +- + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** + * mpt_adapter_dispose - Free all resources associated with an MPT adapter +@@ -2759,13 +2860,14 @@ + } + + pci_disable_device(ioc->pcidev); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) + pci_release_selected_regions(ioc->pcidev, ioc->bars); ++#endif + + #if defined(CONFIG_MTRR) && 0 + if (ioc->mtrr_reg > 0) { + mtrr_del(ioc->mtrr_reg, 0, 0); +- dprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "MTRR region de-registered\n", ioc->name)); ++ dprintk(ioc, printk(MYIOC_s_INFO_FMT "MTRR region de-registered\n", ioc->name)); + } + #endif + +@@ -2773,9 +2875,8 @@ + list_del(&ioc->list); + + sz_last = ioc->alloc_total; +- dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free'd %d of %d bytes\n", +- ioc->name, sz_first-sz_last+(int)sizeof(*ioc), +- sz_first)); ++ dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n", ++ ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first)); + + if (ioc->alt_ioc) + ioc->alt_ioc->alt_ioc = NULL; +@@ -2854,8 +2955,7 @@ + + /* Get current [raw] IOC state */ + ioc_state = mpt_GetIocState(ioc, 0); +- dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "MakeIocReady, [raw] state=%08x\n", ioc->name, ioc_state)); ++ dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state)); + + /* + * Check to see if IOC got left/stuck in doorbell handshake +@@ -2869,10 +2969,9 @@ + + /* Is it already READY? */ + if (!statefault && +- (ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY) { ++ ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)) { + dinitprintk(ioc, printk(MYIOC_s_INFO_FMT +- "IOC is in READY state\n", +- ioc->name)); ++ "IOC is in READY state\n", ioc->name)); + return 0; + } + +@@ -2881,10 +2980,11 @@ + */ + if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) { + statefault = 2; ++ ioc->is_fault = 1; + printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n", +- ioc->name); +- printk(KERN_WARNING " FAULT code = %04xh\n", +- ioc_state & MPI_DOORBELL_DATA_MASK); ++ ioc->name); ++ printk(MYIOC_s_WARN_FMT " FAULT code = %04xh\n", ++ ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK); + } + + /* +@@ -2900,7 +3000,7 @@ + * Else, fall through to KickStart case + */ + whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT; +- dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ dinitprintk(ioc, printk(MYIOC_s_INFO_FMT + "whoinit 0x%x statefault %d force %d\n", + ioc->name, whoinit, statefault, force)); + if (whoinit == MPI_WHOINIT_PCI_PEER) +@@ -2948,23 +3048,22 @@ + ii++; cntdn--; + if (!cntdn) { + printk(MYIOC_s_ERR_FMT +- "Wait IOC_READY state (0x%x) timeout(%d)!\n", +- ioc->name, ioc_state, (int)((ii+5)/HZ)); ++ "Wait IOC_READY state (0x%x) timeout(%d)!\n", ++ ioc->name, ioc_state, (int)((ii+5)/HZ)); + return -ETIME; + } + + if (sleepFlag == CAN_SLEEP) { + msleep(1); + } else { +- mdelay(1); /* 1 msec delay */ ++ mdelay (1); /* 1 msec delay */ + } + + } + + if (statefault < 3) { +- printk(MYIOC_s_INFO_FMT "Recovered from %s\n", +- ioc->name, +- statefault==1 ? "stuck handshake" : "IOC FAULT"); ++ printk(MYIOC_s_INFO_FMT "Recovered from %s\n", ioc->name, ++ statefault == 1 ? "stuck handshake" : "IOC FAULT"); + } + + return hard_reset_done; +@@ -3036,7 +3135,7 @@ + get_facts.Function = MPI_FUNCTION_IOC_FACTS; + /* Assert: All other get_facts fields are zero! */ + +- dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ++ dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT + "Sending get IocFacts request req_sz=%d reply_sz=%d\n", + ioc->name, req_sz, reply_sz)); + +@@ -3067,8 +3166,7 @@ + + facts->MsgVersion = le16_to_cpu(facts->MsgVersion); + if (facts->MsgVersion == MPI_VERSION_01_05) +- facts->HeaderVersion = +- le16_to_cpu(facts->HeaderVersion); ++ facts->HeaderVersion = le16_to_cpu(facts->HeaderVersion); + facts->MsgContext = le32_to_cpu(facts->MsgContext); + facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions); + facts->IOCStatus = le16_to_cpu(facts->IOCStatus); +@@ -3198,8 +3296,8 @@ + + /* IOC *must* NOT be in RESET state! */ + if (ioc->last_state == MPI_IOC_STATE_RESET) { +- printk(MYIOC_s_ERR_FMT "Can't get PortFacts, " +- " NOT READY! (%08x)\n", ioc->name, ioc->last_state); ++ printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n", ++ ioc->name, ioc->last_state ); + return -4; + } + +@@ -3217,14 +3315,14 @@ + get_pfacts.PortNumber = portnum; + /* Assert: All other get_pfacts fields are zero! */ + +- dinitprintk(ioc, printk(MYIOC_s_INFO_FMT +- "Sending get PortFacts(%d) request\n", ioc->name, portnum)); ++ dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n", ++ ioc->name, portnum)); + + /* No non-zero fields in the get_pfacts request are greater than + * 1 byte in size, so we can just fire it off as is. + */ + ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts, +- reply_sz, (u16 *)pfacts, 5 /*seconds*/, sleepFlag); ++ reply_sz, (u16*)pfacts, 5 /*seconds*/, sleepFlag); + if (ii != 0) + return ii; + +@@ -3299,7 +3397,7 @@ + ioc_init.MaxDevices = (U8)ioc->devices_per_bus; + ioc_init.MaxBuses = (U8)ioc->number_of_buses; + +- dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts.MsgVersion=%x\n", ++ dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n", + ioc->name, ioc->facts.MsgVersion)); + if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) { + // set MsgVersion and HeaderVersion host driver was built with +@@ -3415,19 +3513,18 @@ + /* port_enable.MsgFlags = 0; */ + /* port_enable.MsgContext = 0; */ + +- dinitprintk(ioc, printk(MYIOC_s_INFO_FMT +- "Sending Port(%d)Enable (req @ %p)\n", ioc->name, +- portnum, &port_enable)); ++ dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n", ++ ioc->name, portnum, &port_enable)); + + /* RAID FW may take a long time to enable + */ + if (ioc->ir_firmware || ioc->bus_type == SAS) { + rc = mpt_handshake_req_reply_wait(ioc, req_sz, +- (u32 *)&port_enable, reply_sz, (u16 *)&reply_buf, ++ (u32*)&port_enable, reply_sz, (u16*)&reply_buf, + 300 /*seconds*/, sleepFlag); + } else { + rc = mpt_handshake_req_reply_wait(ioc, req_sz, +- (u32 *)&port_enable, reply_sz, (u16 *)&reply_buf, ++ (u32*)&port_enable, reply_sz, (u16*)&reply_buf, + 30 /*seconds*/, sleepFlag); + } + return rc; +@@ -3518,17 +3615,21 @@ + FWUploadReply_t *preply; + FWUploadTCSGE_t *ptcsge; + u32 flagsLength; +- int ii, reply_sz; ++ int ii, sz, reply_sz; + int cmdStatus; + int request_size; + + /* If the image size is 0, we are done. + */ +- if (!ioc->facts.FWImageSize) +- return 0; +- +- if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0) ++ sz = ioc->facts.FWImageSize; ++ if (!sz) ++ return 0; ++ ++ if (mpt_alloc_fw_memory(ioc, sz) != 0) + return -ENOMEM; ++ ++ dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image @ %p[%p], sz=%d[%x] bytes\n", ++ ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz)); + + prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) : + kzalloc(ioc->req_sz, GFP_KERNEL); +@@ -3546,19 +3647,20 @@ + + prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM; + prequest->Function = MPI_FUNCTION_FW_UPLOAD; ++ + ptcsge = (FWUploadTCSGE_t *) &prequest->SGL; + ptcsge->DetailsLength = 12; + ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT; +- ptcsge->ImageSize = cpu_to_le32(ioc->facts.FWImageSize); ++ ptcsge->ImageSize = cpu_to_le32(sz); + ptcsge++; + +- flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | ioc->facts.FWImageSize; ++ flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz; + ioc->add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma); + request_size = offsetof(FWUpload_t, SGL) + sizeof(FWUploadTCSGE_t) + + ioc->SGE_size; + dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending FW Upload " + " (req @ %p) fw_size=%d mf_request_size=%d\n", ioc->name, prequest, +- ioc->facts.FWImageSize, request_size)); ++ sz, request_size)); + DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest); + + ii = mpt_handshake_req_reply_wait(ioc, request_size, (u32 *)prequest, +@@ -3574,14 +3676,14 @@ + */ + int status; + status = le16_to_cpu(preply->IOCStatus) & +- MPI_IOCSTATUS_MASK; +- if (status == MPI_IOCSTATUS_SUCCESS && +- ioc->facts.FWImageSize == +- le32_to_cpu(preply->ActualImageSize)) +- cmdStatus = 0; +- } +- dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "do_upload cmdStatus=%d \n", +- ioc->name, cmdStatus)); ++ MPI_IOCSTATUS_MASK; ++ if ((status == MPI_IOCSTATUS_SUCCESS) && ++ (ioc->facts.FWImageSize == ++ le32_to_cpu(preply->ActualImageSize))) ++ cmdStatus = 0; ++ } ++ dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n", ++ ioc->name, cmdStatus)); + + + if (cmdStatus) { +@@ -3622,7 +3724,7 @@ + u32 doorbell; + + ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n", +- ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader)); ++ ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader)); + + CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); + CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); +@@ -3634,10 +3736,11 @@ + CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM)); + + /* wait 1 msec */ +- if (sleepFlag == CAN_SLEEP) ++ if (sleepFlag == CAN_SLEEP) { + msleep(1); +- else +- mdelay(1); ++ } else { ++ mdelay (1); ++ } + + diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); + CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER); +@@ -3650,10 +3753,11 @@ + break; + } + /* wait .1 sec */ +- if (sleepFlag == CAN_SLEEP) ++ if (sleepFlag == CAN_SLEEP) { + msleep (100); +- else ++ } else { + mdelay (100); ++ } + } + + if ( count == 30 ) { +@@ -3685,12 +3789,13 @@ + + CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress); + ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n", +- ioc->name, pFwHeader->LoadStartAddress)); ++ ioc->name, pFwHeader->LoadStartAddress)); + + ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n", +- ioc->name, fwSize*4, ptrFw)); +- while (fwSize--) ++ ioc->name, fwSize*4, ptrFw)); ++ while (fwSize--) { + CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++); ++ } + + nextImage = pFwHeader->NextImageHeaderOffset; + while (nextImage) { +@@ -3702,24 +3807,23 @@ + ptrFw = (u32 *)pExtImage; + + ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n", +- ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr)); ++ ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr)); + CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr); + +- while (fwSize--) ++ while (fwSize--) { + CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++); ++ } + nextImage = pExtImage->NextImageHeaderOffset; + } + + /* Write the IopResetVectorRegAddr */ +- ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "Write IopResetVector Addr=%x!\n", ioc->name, +- pFwHeader->IopResetRegAddr)); ++ ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ++ ioc->name, pFwHeader->IopResetRegAddr)); + CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr); + + /* Write the IopResetVectorValue */ +- ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "Write IopResetVector Value=%x!\n", ioc->name, +- pFwHeader->IopResetVectorValue)); ++ ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ++ ioc->name, pFwHeader->IopResetVectorValue)); + CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue); + + /* Clear the internal flash bad bit - autoincrementing register, +@@ -3742,14 +3846,15 @@ + pci_disable_io_access(ioc->pcidev); + + diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); +- ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "diag0val=%x, turning off" +- " PREVENT_IOC_BOOT and DISABLE_ARM\n", ioc->name, diag0val)); ++ ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, " ++ "turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n", ++ ioc->name, diag0val)); + diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM); +- ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "diag0val=%x\n", +- ioc->name, diag0val)); ++ ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n", ++ ioc->name, diag0val)); + CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val); + +- if (ioc->bus_type == SAS) { ++ if (ioc->bus_type == SAS ) { + /* wait 1 sec */ + if (sleepFlag == CAN_SLEEP) + msleep(1000); +@@ -3757,7 +3862,7 @@ + mdelay(1000); + + diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); +- ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ ddlprintk(ioc, printk (MYIOC_s_DEBUG_FMT + "diag0val=%x, turning off RW_ENABLE\n", ioc->name, + diag0val)); + diag0val &= ~(MPI_DIAG_RW_ENABLE); +@@ -3780,9 +3885,8 @@ + /* Write 0xFF to reset the sequencer */ + CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); + +- for (count = 0; count < 30; count++) { +- doorbell = CHIPREG_READ32(&ioc->chip->Doorbell) +- & MPI_IOC_STATE_MASK; ++ for (count = 0; count < 30; count ++) { ++ doorbell = CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_IOC_STATE_MASK; + if (doorbell == MPI_IOC_STATE_READY) { + if (ioc->bus_type == SAS) + return 0; +@@ -3795,16 +3899,14 @@ + "SendIocInit successful\n", ioc->name)); + return 0; + } +- ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "looking for READY STATE: doorbell=%x count=%d\n", +- ioc->name, doorbell, count)); ++ ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "looking for READY STATE:" ++ " doorbell=%x count=%d\n", ioc->name, doorbell, count)); + if (sleepFlag == CAN_SLEEP) + msleep(1000); + else + mdelay(1000); + } +- ddlprintk(ioc, printk(MYIOC_s_WARN_FMT +- "downloadboot failed! count=%d\n", ioc->name, count)); ++ ddlprintk(ioc, printk(MYIOC_s_WARN_FMT "downloadboot failed! count=%d\n", ioc->name, count)); + return -EFAULT; + } + +@@ -3841,7 +3943,7 @@ + u32 ioc_state=0; + int cnt,cntdn; + +- dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": KickStart\n", ioc->name)); ++ dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name)); + if (ioc->bus_type == SPI) { + /* Always issue a Msg Unit Reset first. This will clear some + * SCSI bus hang conditions. +@@ -3859,20 +3961,16 @@ + if (hard_reset_done < 0) + return hard_reset_done; + +- /* may not have worked but hard_reset_done +- * doesn't always signal failure +- */ +- dinitprintk(ioc, printk(MYIOC_s_INFO_FMT +- "Diagnostic reset completed!\n", ioc->name)); ++ /* may not have worked but hard_reset_done doesn't always signal failure */ ++ dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n", ++ ioc->name)); + + cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2; /* 2 seconds */ + for (cnt=0; cntname, +- cnt)); ++ if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) { ++ dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n", ++ ioc->name, cnt)); + return hard_reset_done; + } + if (sleepFlag == CAN_SLEEP) { +@@ -3883,7 +3981,7 @@ + } + + dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n", +- ioc->name, mpt_GetIocState(ioc, 0))); ++ ioc->name, mpt_GetIocState(ioc, 0))); + return -1; + } + +@@ -3926,8 +4024,8 @@ + return 0; + + drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset " +- "address=%p\n", ioc->name, __func__, &ioc->chip->Doorbell, +- &ioc->chip->Reset_1078)); ++ "address=%p\n", ioc->name, __func__, ++ &ioc->chip->Doorbell, &ioc->chip->Reset_1078)); + CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07); + if (sleepFlag == CAN_SLEEP) + msleep(1); +@@ -3942,8 +4040,7 @@ + */ + for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { + if (MptResetHandlers[cb_idx]) +- (*(MptResetHandlers[cb_idx])) +- (ioc, MPT_IOC_PRE_RESET); ++ (*(MptResetHandlers[cb_idx]))(ioc, MPT_IOC_PRE_RESET); + } + + for (count = 0; count < 60; count ++) { +@@ -3955,8 +4052,9 @@ + " count=%d\n", + ioc->name, doorbell, count)); + +- if (doorbell == MPI_IOC_STATE_READY) ++ if (doorbell == MPI_IOC_STATE_READY) { + return 1; ++ } + + /* + * Early out for hard fault +@@ -3982,10 +4080,8 @@ + + if (ioc->debug_level & MPT_DEBUG_RESET) { + if (ioc->alt_ioc) +- diag1val = +- CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); +- drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "DbG1: diag0=%08x, diag1=%08x\n", ++ diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); ++ drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n", + ioc->name, diag0val, diag1val)); + } + +@@ -4005,10 +4101,11 @@ + CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); + + /* wait 100 msec */ +- if (sleepFlag == CAN_SLEEP) ++ if (sleepFlag == CAN_SLEEP) { + msleep (100); +- else ++ } else { + mdelay (100); ++ } + + count++; + if (count > 20) { +@@ -4020,16 +4117,14 @@ + + diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); + +- drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "Wrote magic DiagWriteEn sequence (%x)\n", +- ioc->name, diag0val)); ++ drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n", ++ ioc->name, diag0val)); + } + + if (ioc->debug_level & MPT_DEBUG_RESET) { + if (ioc->alt_ioc) + diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); +- drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "DbG2: diag0=%08x, diag1=%08x\n", ++ drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n", + ioc->name, diag0val, diag1val)); + } + /* +@@ -4045,8 +4140,8 @@ + */ + CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER); + hard_reset_done = 1; +- drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "Diagnostic reset performed\n", ioc->name)); ++ drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n", ++ ioc->name)); + + /* + * Call each currently registered protocol IOC reset handler +@@ -4056,11 +4151,10 @@ + */ + for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { + if (MptResetHandlers[cb_idx]) { +- mpt_signal_reset(cb_idx, ioc, +- MPT_IOC_PRE_RESET); +- if (ioc->alt_ioc) +- mpt_signal_reset(cb_idx, +- ioc->alt_ioc, MPT_IOC_PRE_RESET); ++ mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET); ++ if (ioc->alt_ioc) { ++ mpt_signal_reset(cb_idx, ioc->alt_ioc, MPT_IOC_PRE_RESET); ++ } + } + } + +@@ -4081,19 +4175,20 @@ + break; + } + +- drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "cached_fw: diag0val=%x count=%d\n", ++ drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n", + ioc->name, diag0val, count)); + /* wait 1 sec */ +- if (sleepFlag == CAN_SLEEP) ++ if (sleepFlag == CAN_SLEEP) { + msleep (1000); +- else ++ } else { + mdelay (1000); ++ } + } + if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) { + printk(MYIOC_s_WARN_FMT + "firmware downloadboot failure (%d)!\n", ioc->name, count); + } ++ + } else { + /* Wait for FW to reload and for board + * to go to the READY state. +@@ -4109,8 +4204,9 @@ + "looking for READY STATE: doorbell=%x" + " count=%d\n", ioc->name, doorbell, count)); + +- if (doorbell == MPI_IOC_STATE_READY) ++ if (doorbell == MPI_IOC_STATE_READY) { + break; ++ } + + /* + * Early out for hard fault +@@ -4119,10 +4215,11 @@ + break; + + /* wait 1 sec */ +- if (sleepFlag == CAN_SLEEP) ++ if (sleepFlag == CAN_SLEEP) { + msleep (1000); +- else ++ } else { + mdelay (1000); ++ } + } + + if (doorbell != MPI_IOC_STATE_READY) +@@ -4136,8 +4233,7 @@ + if (ioc->debug_level & MPT_DEBUG_RESET) { + if (ioc->alt_ioc) + diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); +- drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "DbG3: diag0=%08x, diag1=%08x\n", ++ drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n", + ioc->name, diag0val, diag1val)); + } + +@@ -4158,10 +4254,11 @@ + CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); + + /* wait 100 msec */ +- if (sleepFlag == CAN_SLEEP) ++ if (sleepFlag == CAN_SLEEP) { + msleep (100); +- else ++ } else { + mdelay (100); ++ } + + count++; + if (count > 20) { +@@ -4195,9 +4292,8 @@ + if (ioc->debug_level & MPT_DEBUG_RESET) { + if (ioc->alt_ioc) + diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); +- drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "DbG4: diag0=%08x, diag1=%08x\n", +- ioc->name, diag0val, diag1val)); ++ drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n", ++ ioc->name, diag0val, diag1val)); + } + + /* +@@ -4257,10 +4353,14 @@ + if (sleepFlag == CAN_SLEEP) { + msleep(1); + } else { +- mdelay(1); /* 1 msec delay */ +- } +- } +- ++ mdelay (1); /* 1 msec delay */ ++ } ++ } ++ ++ /* TODO! ++ * Cleanup all event stuff for this IOC; re-issue EventNotification ++ * request if needed. ++ */ + if (ioc->facts.Function) + ioc->facts.EventState = 0; + +@@ -4326,8 +4426,8 @@ + numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale + + (ioc->req_sz - 60) / ioc->SGE_size; + } else { +- numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale + +- (ioc->req_sz - 64) / ioc->SGE_size; ++ numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) + ++ scale + (ioc->req_sz - 64) / ioc->SGE_size; + } + dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n", + ioc->name, num_sge, numSGE)); +@@ -4335,7 +4435,8 @@ + if (ioc->bus_type == FC) { + if (numSGE > MPT_SCSI_FC_SG_DEPTH) + numSGE = MPT_SCSI_FC_SG_DEPTH; +- } else { ++ } ++ else { + if (numSGE > MPT_SCSI_SG_DEPTH) + numSGE = MPT_SCSI_SG_DEPTH; + } +@@ -4397,10 +4498,10 @@ + dma_mask = 0; + + /* Prime reply FIFO... */ ++ + if (ioc->reply_frames == NULL) { + if ( (num_chain = initChainBuffers(ioc)) < 0) + return -1; +- + /* + * 1078 errata workaround for the 36GB limitation + */ +@@ -4415,10 +4516,17 @@ + "Request/Reply/Chain and Sense Buffers\n", + ioc->name)); + } else { +- d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ /*Reseting DMA mask to 64 bit*/ ++ pci_set_dma_mask(ioc->pcidev, ++ DMA_64BIT_MASK); ++ pci_set_consistent_dma_mask(ioc->pcidev, ++ DMA_64BIT_MASK); ++ ++ printk(MYIOC_s_ERR_FMT + "failed setting 35 bit addressing for " + "Request/Reply/Chain and Sense Buffers\n", +- ioc->name)); ++ ioc->name); ++ return -1; + } + } + +@@ -4788,7 +4896,7 @@ + } + } else { + while (--cntdn) { +- udelay(1000); ++ udelay (1000); + intstat = CHIPREG_READ32(&ioc->chip->IntStatus); + if (intstat & MPI_HIS_DOORBELL_INTERRUPT) + break; +@@ -4862,7 +4970,7 @@ + failcnt++; + hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF); + /* don't overflow our IOC hs_reply[] buffer! */ +- if (u16cnt < sizeof(ioc->hs_reply) / sizeof(ioc->hs_reply[0])) ++ if (u16cnt < ARRAY_SIZE(ioc->hs_reply)) + hs_reply[u16cnt] = hword; + CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); + } +@@ -4950,6 +5058,10 @@ + + pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage0_alloc, page0_dma); + ++ /* FIXME! ++ * Normalize endianness of structure data, ++ * by byte-swapping all > 1 byte fields! ++ */ + + } + +@@ -4990,6 +5102,11 @@ + + pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage1_alloc, page1_dma); + ++ /* FIXME! ++ * Normalize endianness of structure data, ++ * by byte-swapping all > 1 byte fields! ++ */ ++ + } + + return rc; +@@ -5009,6 +5126,8 @@ + * + * Returns 0 for success, non-zero error + */ ++ ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + int + mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode) + { +@@ -5037,12 +5156,13 @@ + goto out; + } + +- printk("%s: persist_opcode=%x\n",__func__, persist_opcode); ++ printk(KERN_DEBUG "%s: persist_opcode=%x\n", ++ __func__, persist_opcode); + + /* Get a MF for this command. + */ + if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { +- printk("%s: no msg frames!\n",__func__); ++ printk(KERN_DEBUG "%s: no msg frames!\n", __func__); + ret = -1; + goto out; + } +@@ -5058,11 +5178,11 @@ + timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 10*HZ); + if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { + ret = -ETIME; +- printk(KERN_WARNING "%s: failed\n", __func__); ++ printk(KERN_DEBUG "%s: failed\n", __func__); + if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) + goto out; + if (!timeleft) { +- printk(MYIOC_s_WARN_FMT "Issuing Reset from %s!!\n", ++ printk(KERN_DEBUG "%s: Issuing Reset from %s!!\n", + ioc->name, __func__); + if (mpt_SoftResetHandler(ioc, CAN_SLEEP) != 0) + mpt_HardResetHandler(ioc, CAN_SLEEP); +@@ -5079,13 +5199,13 @@ + sasIoUnitCntrReply = + (SasIoUnitControlReply_t *)ioc->mptbase_cmds.reply; + if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) { +- printk(KERN_WARNING "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n", ++ printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n", + __func__, sasIoUnitCntrReply->IOCStatus, + sasIoUnitCntrReply->IOCLogInfo); +- printk(KERN_WARNING "%s: failed\n", __func__); ++ printk(KERN_DEBUG "%s: failed\n", __func__); + ret = -1; + } else +- printk(KERN_INFO "%s: success\n", __func__); ++ printk(KERN_DEBUG "%s: success\n", __func__); + out: + + CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status) +@@ -5363,8 +5483,8 @@ + ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN; + rc = 1; + ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "Unable to read PortPage0 minSyncFactor=%x\n", +- ioc->name, ioc->spi_data.minSyncFactor)); ++ "Unable to read PortPage0 minSyncFactor=%x\n", ++ ioc->name, ioc->spi_data.minSyncFactor)); + } else { + /* Save the Port Page 0 data + */ +@@ -5563,7 +5683,7 @@ + { + CONFIGPARMS cfg; + ConfigPageHeader_t header; +- IOCPage6_t *pIoc6 = NULL; ++ IOCPage6_t *pIoc6=NULL; + dma_addr_t ioc6_dma; + int iocpage6sz; + void *mem; +@@ -5622,9 +5742,8 @@ + } + + /** +- * mpt_inactive_raid_list_free - This clears this link list. +- * @ioc : pointer to per adapter structure +- * ++ * mpt_inactive_raid_list_free - This clears this link list. ++ * @ioc : pointer to per adapter structure + **/ + static void + mpt_inactive_raid_list_free(MPT_ADAPTER *ioc) +@@ -5634,23 +5753,21 @@ + if (list_empty(&ioc->raid_data.inactive_list)) + return; + +- mutex_lock(&ioc->raid_data.inactive_list_mutex); ++ down(&ioc->raid_data.inactive_list_mutex); + list_for_each_entry_safe(component_info, pNext, + &ioc->raid_data.inactive_list, list) { + list_del(&component_info->list); + kfree(component_info); + } +- mutex_unlock(&ioc->raid_data.inactive_list_mutex); +-} +- +-/** +- * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums +- * for devices belonging in an inactive volume +- * +- * @ioc : pointer to per adapter structure +- * @channel : volume channel +- * @id : volume target id +- * ++ up(&ioc->raid_data.inactive_list_mutex); ++} ++ ++/** ++ * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums for devices belonging in an inactive volume ++ * ++ * @ioc : pointer to per adapter structure ++ * @channel : volume channel ++ * @id : volume target id + **/ + static void + mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id) +@@ -5703,7 +5820,7 @@ + if (!handle_inactive_volumes) + goto out; + +- mutex_lock(&ioc->raid_data.inactive_list_mutex); ++ down(&ioc->raid_data.inactive_list_mutex); + for (i = 0; i < buffer->NumPhysDisks; i++) { + if(mpt_raid_phys_disk_pg0(ioc, + buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0) +@@ -5719,7 +5836,7 @@ + buffer->PhysDisk[i].PhysDiskNum); + if (num_paths < 2) + continue; +- phys_disk_1 = kzalloc(offsetof(RaidPhysDiskPage1_t, Path) + ++ phys_disk_1 = kzalloc(offsetof(RaidPhysDiskPage1_t,Path) + + (num_paths * sizeof(RAID_PHYS_DISK1_PATH)), GFP_KERNEL); + if (!phys_disk_1) + continue; +@@ -5733,7 +5850,7 @@ + continue; + + if ((component_info = kmalloc(sizeof (*component_info), +- GFP_KERNEL)) == NULL) ++ GFP_KERNEL)) == NULL) + continue; + + component_info->volumeID = id; +@@ -5746,7 +5863,7 @@ + list_add_tail(&component_info->list, + &ioc->raid_data.inactive_list); + } +- mutex_unlock(&ioc->raid_data.inactive_list_mutex); ++ up(&ioc->raid_data.inactive_list_mutex); + + out: + if (buffer) +@@ -5767,10 +5884,10 @@ + **/ + int + mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num, +- RaidPhysDiskPage0_t *phys_disk) +-{ +- CONFIGPARMS cfg; +- ConfigPageHeader_t hdr; ++ RaidPhysDiskPage0_t *phys_disk) ++{ ++ CONFIGPARMS cfg; ++ ConfigPageHeader_t hdr; + dma_addr_t dma_handle; + pRaidPhysDiskPage0_t buffer = NULL; + int rc; +@@ -5901,8 +6018,7 @@ + * -ENOMEM if pci_alloc failed + **/ + int +-mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num, +- RaidPhysDiskPage1_t *phys_disk) ++mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num, RaidPhysDiskPage1_t *phys_disk) + { + CONFIGPARMS cfg; + ConfigPageHeader_t hdr; +@@ -5955,20 +6071,14 @@ + for (i = 0; i < phys_disk->NumPhysDiskPaths; i++) { + phys_disk->Path[i].PhysDiskID = buffer->Path[i].PhysDiskID; + phys_disk->Path[i].PhysDiskBus = buffer->Path[i].PhysDiskBus; +- phys_disk->Path[i].OwnerIdentifier = +- buffer->Path[i].OwnerIdentifier; +- phys_disk->Path[i].Flags = +- le16_to_cpu(buffer->Path[i].Flags); +- memcpy(&sas_address, &buffer->Path[i].WWID, +- sizeof(__le64)); ++ phys_disk->Path[i].OwnerIdentifier = buffer->Path[i].OwnerIdentifier; ++ phys_disk->Path[i].Flags = le16_to_cpu(buffer->Path[i].Flags); ++ memcpy(&sas_address, &buffer->Path[i].WWID, sizeof(__le64)); + sas_address = le64_to_cpu(sas_address); +- memcpy(&phys_disk->Path[i].WWID, &sas_address, +- sizeof(__le64)); +- memcpy(&sas_address, &buffer->Path[i].OwnerWWID, +- sizeof(__le64)); ++ memcpy(&phys_disk->Path[i].WWID, &sas_address, sizeof(__le64)); ++ memcpy(&sas_address, &buffer->Path[i].OwnerWWID, sizeof(__le64)); + sas_address = le64_to_cpu(sas_address); +- memcpy(&phys_disk->Path[i].OwnerWWID, &sas_address, +- sizeof(__le64)); ++ memcpy(&phys_disk->Path[i].OwnerWWID, &sas_address, sizeof(__le64)); + } + + out: +@@ -5992,8 +6102,8 @@ + static int + mpt_sort_ioc_pg2(const void *a, const void *b) + { +- ConfigPageIoc2RaidVol_t *volume_a = (ConfigPageIoc2RaidVol_t *)a; +- ConfigPageIoc2RaidVol_t *volume_b = (ConfigPageIoc2RaidVol_t *)b; ++ ConfigPageIoc2RaidVol_t * volume_a = (ConfigPageIoc2RaidVol_t *)a; ++ ConfigPageIoc2RaidVol_t * volume_b = (ConfigPageIoc2RaidVol_t *)b; + + if (volume_a->VolumeBus == volume_b->VolumeBus) { + if (volume_a->VolumeID == volume_b->VolumeID) +@@ -6010,7 +6120,6 @@ + /** + * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes + * @ioc: Pointer to a Adapter Strucutre +- * @portnum: IOC port number + * + * Return: + * 0 on success +@@ -6268,22 +6377,24 @@ + + cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM; + if (mpt_config(ioc, &cfg) == 0) { +- dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset NVRAM Coalescing Timeout to = %d\n", ++ dprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "Reset NVRAM Coalescing Timeout to = %d\n", + ioc->name, MPT_COALESCING_TIMEOUT)); + } else { +- dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset NVRAM Coalescing Timeout Failed\n", +- ioc->name)); ++ dprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "Reset NVRAM Coalescing Timeout Failed\n", ++ ioc->name)); + } + + } else { +- dprintk(ioc, printk(MYIOC_s_WARN_FMT "Reset of Current Coalescing Timeout Failed!\n", +- ioc->name)); +- } +- } +- +- } else { +- dprintk(ioc, printk(MYIOC_s_WARN_FMT +- "Coalescing Disabled\n", ioc->name)); ++ dprintk(ioc, printk(MYIOC_s_WARN_FMT ++ "Reset of Current Coalescing Timeout Failed!\n", ++ ioc->name)); ++ } ++ } ++ ++ } else { ++ dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name)); + } + } + +@@ -6377,7 +6488,7 @@ + + if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { + dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n", +- ioc->name,__func__)); ++ ioc->name, __func__)); + return -1; + } + +@@ -6424,11 +6535,19 @@ + u8 page_type = 0, extend_page; + unsigned long timeleft; + unsigned long flags; ++ int in_isr; + u8 issue_hard_reset = 0; + u8 retry_count = 0; + +- if (in_interrupt()) ++ /* Prevent calling wait_event() (below), if caller happens ++ * to be in ISR context, because that is fatal! ++ */ ++ in_isr = in_interrupt(); ++ if (in_isr) { ++ dcprintk(ioc, printk(MYIOC_s_WARN_FMT "Config request not allowed in ISR context!\n", ++ ioc->name)); + return -EPERM; ++ } + + /* don't send a config page during diag reset */ + spin_lock_irqsave(&ioc->taskmgmt_lock, flags); +@@ -6523,8 +6642,8 @@ + ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr); + timeout = (pCfg->timeout < 15) ? HZ*15 : HZ*pCfg->timeout; + mpt_put_msg_frame(mpt_base_index, ioc, mf); +- timeleft = +- wait_for_completion_timeout(&ioc->mptbase_cmds.done, timeout); ++ timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, ++ timeout); + if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { + ret = -ETIME; + dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT +@@ -6560,8 +6679,8 @@ + } + + if (retry_count) +- printk(MYIOC_s_INFO_FMT +- "Retry completed ret=0x%x timeleft=%ld\n", ++ printk(MYIOC_s_INFO_FMT "Retry completed " ++ "ret=0x%x timeleft=%ld\n", + ioc->name, ret, timeleft); + + dcprintk(ioc, printk(KERN_DEBUG "IOCStatus=%04xh, IOCLogInfo=%08xh\n", +@@ -6581,8 +6700,9 @@ + /* attempt one retry for a timed out command */ + if (!retry_count) { + printk(MYIOC_s_INFO_FMT +- "Attempting Retry Config request type 0x%x," +- " page 0x%x, action %d\n", ioc->name, page_type, ++ "Attempting Retry Config request" ++ " type 0x%x, page 0x%x," ++ " action %d\n", ioc->name, page_type, + pCfg->cfghdr.hdr->PageNumber, pCfg->action); + retry_count++; + goto retry_config; +@@ -6604,9 +6724,9 @@ + { + switch (reset_phase) { + case MPT_IOC_SETUP_RESET: ++ ioc->taskmgmt_quiesce_io = 1; + dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT + "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__)); +- ioc->taskmgmt_quiesce_io = 1; + break; + case MPT_IOC_PRE_RESET: + dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +@@ -6617,14 +6737,14 @@ + "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__)); + /* wake up mptbase_cmds */ + if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) { +- ioc->mptbase_cmds.status +- |= MPT_MGMT_STATUS_DID_IOCRESET; ++ ioc->mptbase_cmds.status |= ++ MPT_MGMT_STATUS_DID_IOCRESET; + complete(&ioc->mptbase_cmds.done); + } + /* wake up taskmgmt_cmds */ + if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) { +- ioc->taskmgmt_cmds.status +- |= MPT_MGMT_STATUS_DID_IOCRESET; ++ ioc->taskmgmt_cmds.status |= ++ MPT_MGMT_STATUS_DID_IOCRESET; + complete(&ioc->taskmgmt_cmds.done); + } + break; +@@ -6637,6 +6757,10 @@ + + + #ifdef CONFIG_PROC_FS /* { */ ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ ++/* ++ * procfs (%MPT_PROCFS_MPTBASEDIR/...) support stuff... ++ */ + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** + * procmpt_create - Create %MPT_PROCFS_MPTBASEDIR entries. +@@ -6874,6 +6998,7 @@ + + #endif /* CONFIG_PROC_FS } */ + ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + static void + mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc) + { +@@ -6936,12 +7061,6 @@ + + *size = y; + } +- +-/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/* +- * Reset Handling +- */ +- + /** + * mpt_set_taskmgmt_in_progress_flag - set flags associated with task managment + * @ioc: Pointer to MPT_ADAPTER structure +@@ -7012,19 +7131,19 @@ + if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) { + printk(MYIOC_s_ERR_FMT "IOC is in FAULT state (%04xh)!!!\n", + ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK); +- if (mpt_fwfault_debug == 2) +- for (;;); +- else +- panic("%s: IOC Fault (%04xh)!!!\n", ioc->name, +- ioc_raw_state & MPI_DOORBELL_DATA_MASK); ++ if(mpt_fwfault_debug == 2) ++ for(;;); ++ else ++ panic("%s: IOC Fault (%04xh)!!!\n", ioc->name, ++ ioc_raw_state & MPI_DOORBELL_DATA_MASK); + } else { + CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00); +- if (mpt_fwfault_debug == 2) { +- printk(KERN_ERR +- "%s: Firmware is halted due to command timeout\n", +- ioc->name); +- for (;;); +- } else ++ if(mpt_fwfault_debug == 2) { ++ printk("%s: Firmware is halted due to command timeout\n" ++ ,ioc->name); ++ for(;;); ++ } ++ else + panic("%s: Firmware is halted due to command timeout\n", + ioc->name); + } +@@ -7054,18 +7173,22 @@ + u32 ioc_state; + unsigned long time_count; + +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "SoftResetHandler Entered!\n", ioc->name)); ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SoftResetHandler Entered!\n", ioc->name)); + + ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK; + +- if (mpt_fwfault_debug) ++ if(mpt_fwfault_debug) + mpt_halt_firmware(ioc); + +- if (ioc_state == MPI_IOC_STATE_FAULT +- || ioc_state == MPI_IOC_STATE_RESET) { ++ if (ioc_state == MPI_IOC_STATE_FAULT || ioc_state == MPI_IOC_STATE_RESET) { + dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT + "skipping, either in FAULT or RESET state!\n", ioc->name)); ++ return -1; ++ } ++ ++ if (ioc->bus_type == FC) { ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "skipping, because the bus type is FC!\n", ioc->name)); + return -1; + } + +@@ -7084,6 +7207,12 @@ + mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET); + } + ++ spin_lock_irqsave(&ioc->taskmgmt_lock, flags); ++ if (ioc->taskmgmt_in_progress) { ++ spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); ++ return -1; ++ } ++ spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); + /* Disable reply interrupts (also blocks FreeQ) */ + CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); + ioc->active = 0; +@@ -7095,7 +7224,7 @@ + if (MptResetHandlers[cb_idx]) + mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET); + } +- ++ + if (rc) + goto out; + +@@ -7108,10 +7237,11 @@ + if ((rc = GetIocFacts(ioc, sleepFlag, + MPT_HOSTEVENT_IOC_RECOVER)) == 0) + break; +- if (sleepFlag == CAN_SLEEP) ++ if (sleepFlag == CAN_SLEEP) { + msleep(100); +- else ++ } else { + mdelay(100); ++ } + } + if (ii == 5) + goto out; +@@ -7145,15 +7275,13 @@ + if (ioc->active) { /* otherwise, hard reset coming */ + for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { + if (MptResetHandlers[cb_idx]) +- mpt_signal_reset(cb_idx, +- ioc, MPT_IOC_POST_RESET); +- } +- } +- +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "SoftResetHandler: completed (%d seconds): %s\n", +- ioc->name, jiffies_to_msecs(jiffies - time_count)/1000, +- ((rc == 0) ? "SUCCESS" : "FAILED"))); ++ mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET); ++ } ++ } ++ ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SoftResetHandler: completed (%d seconds): %s\n", ++ ioc->name, jiffies_to_msecs(jiffies - time_count)/1000, ++ ((rc == 0) ? "SUCCESS" : "FAILED"))); + + return rc; + } +@@ -7188,7 +7316,6 @@ + printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name); + printk("MF count 0x%x !\n", ioc->mfcnt); + #endif +- + if (mpt_fwfault_debug) + mpt_halt_firmware(ioc); + +@@ -7215,27 +7342,29 @@ + if (MptResetHandlers[cb_idx]) { + mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET); + if (ioc->alt_ioc) +- mpt_signal_reset(cb_idx, +- ioc->alt_ioc, MPT_IOC_SETUP_RESET); ++ mpt_signal_reset(cb_idx, ioc->alt_ioc, ++ MPT_IOC_SETUP_RESET); + } + } + + time_count = jiffies; + if ((rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag)) != 0) { +- printk(KERN_WARNING MYNAM +- ": WARNING - (%d) Cannot recover %s\n", rc, ioc->name); ++ printk(KERN_WARNING MYNAM ": WARNING - (%d) Cannot recover %s\n", ++ rc, ioc->name); + } else { + if (ioc->hard_resets < -1) + ioc->hard_resets++; + } + + spin_lock_irqsave(&ioc->taskmgmt_lock, flags); ++ if (ioc->is_fault == 1) ++ ioc->is_fault = 2; ++ ioc->taskmgmt_quiesce_io = 0; + ioc->ioc_reset_in_progress = 0; +- ioc->taskmgmt_quiesce_io = 0; + ioc->taskmgmt_in_progress = 0; + if (ioc->alt_ioc) { ++ ioc->alt_ioc->taskmgmt_quiesce_io = 0; + ioc->alt_ioc->ioc_reset_in_progress = 0; +- ioc->alt_ioc->taskmgmt_quiesce_io = 0; + ioc->alt_ioc->taskmgmt_in_progress = 0; + } + spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); +@@ -7244,15 +7373,16 @@ + if (MptResetHandlers[cb_idx]) { + mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET); + if (ioc->alt_ioc) +- mpt_signal_reset(cb_idx, +- ioc->alt_ioc, MPT_IOC_POST_RESET); +- } +- } +- +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "HardResetHandler: completed (%d seconds): %s\n", +- ioc->name, jiffies_to_msecs(jiffies - time_count)/1000, +- ((rc == 0) ? "SUCCESS" : "FAILED"))); ++ mpt_signal_reset(cb_idx, ioc->alt_ioc, MPT_IOC_POST_RESET); ++ } ++ } ++ ++ dtmprintk(ioc, ++ printk(MYIOC_s_DEBUG_FMT ++ "HardResetHandler: completed (%d seconds): %s\n", ioc->name, ++ jiffies_to_msecs(jiffies - time_count)/1000, ((rc == 0) ? ++ "SUCCESS" : "FAILED"))); ++ + return rc; + } + +@@ -7723,7 +7853,6 @@ + devtverboseprintk(ioc, printk(KERN_DEBUG "\n")); + } + #endif +- + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** + * ProcessEventNotification - Route EventNotificationReply to all event handlers +@@ -7746,14 +7875,14 @@ + int handlers = 0; + u8 event; + +- + /* + * Do platform normalization of values + */ + event = le32_to_cpu(pEventReply->Event) & 0xFF; + evDataLen = le16_to_cpu(pEventReply->EventDataLength); +- if (evDataLen) ++ if (evDataLen) { + evData0 = le32_to_cpu(pEventReply->Data[0]); ++ } + + #ifdef CONFIG_FUSION_LOGGING + if (evDataLen) +@@ -7819,6 +7948,7 @@ + handlers++; + } + } ++ /* FIXME? Examine results here? */ + + /* + * If needed, send (a single) EventAck. +@@ -7884,7 +8014,6 @@ + /** + * mpt_spi_log_info - Log information returned from SCSI Parallel IOC. + * @ioc: Pointer to MPT_ADAPTER structure +- * @mr: Pointer to MPT reply frame + * @log_info: U32 LogInfo word from the IOC + * + * Refer to lsi/sp_log.h. +@@ -8092,6 +8221,7 @@ + "Compatibility Error: IME Size Limited to < 2TB", /* 3Dh */ + }; + ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** + * mpt_sas_log_info - Log information returned from SAS IOC. + * @ioc: Pointer to MPT_ADAPTER structure +@@ -8118,7 +8248,7 @@ + + sas_loginfo.loginfo = log_info; + if ((sas_loginfo.dw.bus_type != 3 /*SAS*/) && +- (sas_loginfo.dw.originator < sizeof(originator_str)/sizeof(char*))) ++ (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str))) + return; + + originator_desc = originator_str[sas_loginfo.dw.originator]; +@@ -8127,21 +8257,21 @@ + + case 0: /* IOP */ + if (sas_loginfo.dw.code < +- sizeof(iop_code_str)/sizeof(char*)) ++ ARRAY_SIZE(iop_code_str)) + code_desc = iop_code_str[sas_loginfo.dw.code]; + break; + case 1: /* PL */ + if (sas_loginfo.dw.code < +- sizeof(pl_code_str)/sizeof(char*)) ++ ARRAY_SIZE(pl_code_str)) + code_desc = pl_code_str[sas_loginfo.dw.code]; + break; + case 2: /* IR */ + if (sas_loginfo.dw.code >= +- sizeof(ir_code_str)/sizeof(char*)) ++ ARRAY_SIZE(ir_code_str)) + break; + code_desc = ir_code_str[sas_loginfo.dw.code]; + if (sas_loginfo.dw.subcode >= +- sizeof(raid_sub_code_str)/sizeof(char*)) ++ ARRAY_SIZE(raid_sub_code_str)) + break; + if (sas_loginfo.dw.code == 0) + sub_code_desc = +@@ -8171,6 +8301,7 @@ + sas_loginfo.dw.code, sas_loginfo.dw.subcode); + } + ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** + * mpt_iocstatus_info_config - IOCSTATUS information for config pages + * @ioc: Pointer to MPT_ADAPTER structure +@@ -8472,8 +8603,8 @@ + if (!desc) + return; + +- dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "IOCStatus(0x%04X): %s\n", ioc->name, status, desc)); ++ dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n", ++ ioc->name, status, desc)); + } + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +@@ -8484,6 +8615,7 @@ + EXPORT_SYMBOL(mpt_suspend); + #endif + EXPORT_SYMBOL(ioc_list); ++EXPORT_SYMBOL(mpt_proc_root_dir); + EXPORT_SYMBOL(mpt_register); + EXPORT_SYMBOL(mpt_deregister); + EXPORT_SYMBOL(mpt_event_register); +@@ -8513,7 +8645,6 @@ + EXPORT_SYMBOL(mpt_set_taskmgmt_in_progress_flag); + EXPORT_SYMBOL(mpt_clear_taskmgmt_in_progress_flag); + EXPORT_SYMBOL(mpt_halt_firmware); +- + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** + * fusion_init - Fusion MPT base driver initialization routine. +@@ -8560,6 +8691,7 @@ + static void __exit + fusion_exit(void) + { ++ + mpt_reset_deregister(mpt_base_index); + + #ifdef CONFIG_PROC_FS +diff -r 8807687e8e9c drivers/message/fusion/mptbase.h +--- a/drivers/message/fusion/mptbase.h Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/mptbase.h Tue Sep 01 16:11:22 2009 +0100 +@@ -72,13 +72,13 @@ + #define COPYRIGHT "Copyright (c) 1999-2008 " MODULEAUTHOR + #endif + +-#define MPT_LINUX_VERSION_COMMON "4.00.43.00suse" +-#define MPT_LINUX_PACKAGE_NAME "@(#)mptlinux-4.00.43.00suse" ++#define MPT_LINUX_VERSION_COMMON "4.20.00.01" ++#define MPT_LINUX_PACKAGE_NAME "@(#)mptlinux-4.20.00.01" + #define WHAT_MAGIC_STRING "@" "(" "#" ")" + #define MPT_LINUX_MAJOR_VERSION 4 +-#define MPT_LINUX_MINOR_VERSION 00 +-#define MPT_LINUX_BUILD_VERSION 43 +-#define MPT_LINUX_RELEASE_VERSION 00 ++#define MPT_LINUX_MINOR_VERSION 20 ++#define MPT_LINUX_BUILD_VERSION 00 ++#define MPT_LINUX_RELEASE_VERSION 01 + + #define show_mptmod_ver(s,ver) \ + printk(KERN_INFO "%s %s\n", s, ver); +@@ -106,6 +106,11 @@ + #endif + + #define MPT_NAME_LENGTH 32 ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22)) ++#define MPT_KOBJ_NAME_LEN 20 ++#else ++#define MPT_KOBJ_NAME_LEN KOBJ_NAME_LEN ++#endif + + #define MPT_PROCFS_MPTBASEDIR "mpt" + /* chg it to "driver/fusion" ? */ +@@ -159,8 +164,9 @@ + /* + * Try to keep these at 2^N-1 + */ +-#define MPT_FC_CAN_QUEUE 127 ++#define MPT_FC_CAN_QUEUE 1024 + #define MPT_SCSI_CAN_QUEUE 127 ++#define MPT_SAS_CAN_QUEUE 127 + + /* + * Set the MAX_SGE value based on user input. +@@ -177,10 +183,10 @@ + #define MPT_SCSI_SG_DEPTH 40 + #endif + +-#ifdef CONFIG_FUSION_MAX_FC_SGE +-#if CONFIG_FUSION_MAX_FC_SGE < 16 ++#ifdef CONFIG_FUSION_MAX_FC_SGE ++#if CONFIG_FUSION_MAX_FC_SGE < 16 + #define MPT_SCSI_FC_SG_DEPTH 16 +-#elif CONFIG_FUSION_MAX_FC_SGE > 256 ++#elif CONFIG_FUSION_MAX_FC_SGE > 256 + #define MPT_SCSI_FC_SG_DEPTH 256 + #else + #define MPT_SCSI_FC_SG_DEPTH CONFIG_FUSION_MAX_FC_SGE +@@ -368,6 +374,31 @@ + * in conjunction with SYSIF_REGS accesses! + */ + ++/* ++ * End to End Data Protection Support ++ */ ++#define EEDP_SUPPORT ++#ifdef EEDP_SUPPORT ++ ++#define PRO_R MPI_SCSIIO32_EEDPFLAGS_CHKRM_OP ++#define PRO_W MPI_SCSIIO32_EEDPFLAGS_INSERT_OP ++#define PRO_V MPI_SCSIIO32_EEDPFLAGS_INSERT_OP ++ ++/* the read capacity 16 byte parameter block - defined in SBC-3 */ ++struct read_cap_parameter{ ++ u64 logical_block_addr; ++ u32 logical_block_length; ++ u8 prot_en:1; ++ u8 p_type:3; ++ u8 reserved0:4; ++ u8 logical_blocks_per_phyical_block:4; ++ u8 reserved1:4; ++ u16 lowest_aligned_log_block_address:14; ++ u16 reserved2:2; ++ u8 reserved3[16]; ++}; ++#endif ++ + + /* + * Dynamic Multi-Pathing specific stuff... +@@ -402,6 +433,11 @@ + VirtTarget *vtarget; + u8 configured_lun; + int lun; ++#ifdef EEDP_SUPPORT ++ u8 eedp_enable; ++ u8 eedp_type; ++ u32 eedp_block_length; ++#endif + } VirtDevice; + + /* +@@ -444,10 +480,10 @@ + #define MPT_MGMT_STATUS_RF_VALID 0x01 /* The Reply Frame is VALID */ + #define MPT_MGMT_STATUS_COMMAND_GOOD 0x02 /* Command Status GOOD */ + #define MPT_MGMT_STATUS_PENDING 0x04 /* command is pending */ +-#define MPT_MGMT_STATUS_DID_IOCRESET 0x08 /* IOC Reset occurred */ ++#define MPT_MGMT_STATUS_DID_IOCRESET 0x08 /* IOC Reset occurred on the current*/ + #define MPT_MGMT_STATUS_SENSE_VALID 0x10 /* valid sense info */ + #define MPT_MGMT_STATUS_TIMER_ACTIVE 0x20 /* obsolete */ +-#define MPT_MGMT_STATUS_FREE_MF 0x40 /* free the mf */ ++#define MPT_MGMT_STATUS_FREE_MF 0x40 /* free the mf from complete routine */ + + + #define INITIALIZE_MGMT_STATUS(status) \ +@@ -467,7 +503,7 @@ + u8 status; /* current command status */ + int completion_code; + u32 msg_context; +-} MPT_MGMT; ++}MPT_MGMT; + + /* + * Event Structure and define +@@ -540,7 +576,7 @@ + IOCPage2_t *pIocPg2; /* table of Raid Volumes */ + IOCPage3_t *pIocPg3; /* table of physical disks */ + IOCPage6_t *pIocPg6; /* table of IR static data */ +- struct mutex inactive_list_mutex; ++ struct semaphore inactive_list_mutex; + struct list_head inactive_list; /* link list for physical + disk that belong in + inactive volumes */ +@@ -570,9 +606,8 @@ + u8 flags; + }; + +-typedef void (*MPT_ADD_SGE)(char *pAddr, u32 flagslength, dma_addr_t dma_addr); +-typedef void (*MPT_ADD_CHAIN) +- (char *pAddr, u8 next, u16 length, dma_addr_t dma_addr); ++typedef void (*MPT_ADD_SGE)(void *pAddr, u32 flagslength, dma_addr_t dma_addr); ++typedef void (*MPT_ADD_CHAIN)(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr); + + /* + * Adapter Structure - pci_dev specific. Maximum: MPT_MAX_ADAPTERS +@@ -584,8 +619,7 @@ + char name[MPT_NAME_LENGTH]; /* "iocN" */ + char prod_name[MPT_NAME_LENGTH]; /* "LSIFC9x9" */ + #ifdef CONFIG_FUSION_LOGGING +- /* used in mpt_display_event_info */ +- char evStr[EVENT_DESCR_STR_SZ]; ++ char evStr[EVENT_DESCR_STR_SZ]; /* used in mpt_display_event_info */ + #endif + char board_name[16]; + char board_assembly[16]; +@@ -599,8 +633,7 @@ + SYSIF_REGS __iomem *pio_chip; /* Programmed IO (downloadboot) */ + u8 bus_type; + unsigned long mem_phys; /* == f4020000 (mmap) */ +- /* Programmed IO (downloadboot) */ +- unsigned long pio_mem_phys; ++ unsigned long pio_mem_phys; /* Programmed IO (downloadboot) */ + int mem_size; /* mmap memory size */ + int number_of_buses; + int devices_per_bus; +@@ -615,10 +648,8 @@ + int reply_depth; /* Num Allocated reply frames */ + int reply_sz; /* Reply frame size */ + int num_chain; /* Number of chain buffers */ +- /* Pointer to add_sge function */ +- MPT_ADD_SGE add_sge; +- /* Pointer to add_chain function */ +- MPT_ADD_CHAIN add_chain; ++ MPT_ADD_SGE add_sge; /* Pointer to add_sge function */ ++ MPT_ADD_CHAIN add_chain; /* Pointer to add_chain function */ + /* Pool of buffers for chaining. ReqToChain + * and ChainToChain track index of chain buffers. + * ChainBuffer (DMA) virt/phys addresses. +@@ -651,8 +682,9 @@ + dma_addr_t HostPageBuffer_dma; + int mtrr_reg; + struct pci_dev *pcidev; /* struct pci_dev pointer */ +- /* bitmask of BAR's that must be configured */ +- int bars; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) ++ int bars; /* bitmask of BAR's that must be configured */ ++#endif + int msi_enable; + u8 __iomem *memmap; /* mmap address */ + struct Scsi_Host *sh; /* Scsi Host pointer */ +@@ -686,8 +718,7 @@ + #if defined(CPQ_CIM) + u32 csmi_change_count; /* count to track all IR + events for CSMI */ +- /* ioc page 1 - pci slot number */ +- u8 pci_slot_number; ++ u8 pci_slot_number; /* ioc page 1 - pci slot number */ + #endif + + u8 ir_firmware; /* =1 if IR firmware detected */ +@@ -716,14 +747,13 @@ + struct list_head fw_event_list; + spinlock_t fw_event_lock; + u8 fw_events_off; /* if '1', then ignore events */ +- char fw_event_q_name[20]; ++ char fw_event_q_name[MPT_KOBJ_NAME_LEN]; + +- /* port_info object for the host */ +- struct mptsas_portinfo *hba_port_info; ++ struct mptsas_portinfo *hba_port_info; /* port_info object for the host */ + u64 hba_port_sas_addr; + u16 hba_port_num_phy; + struct list_head sas_device_info_list; +- struct mutex sas_device_info_mutex; ++ struct semaphore sas_device_info_mutex; + u8 old_sas_discovery_protocal; + u8 sas_discovery_quiesce_io; + int sas_index; /* index refrencing */ +@@ -740,24 +770,24 @@ + u8 num_ports; + #endif + +- char reset_work_q_name[20]; ++ char reset_work_q_name[MPT_KOBJ_NAME_LEN]; + struct workqueue_struct *reset_work_q; ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + struct delayed_work fault_reset_work; +- spinlock_t fault_reset_work_lock; ++#else ++ struct work_struct fault_reset_work; ++#endif + struct work_struct fc_setup_reset_work; + struct list_head fc_rports; + struct work_struct fc_lsc_work; + u8 fc_link_speed[2]; + spinlock_t fc_rescan_work_lock; + struct work_struct fc_rescan_work; +- char fc_rescan_work_q_name[20]; ++ char fc_rescan_work_q_name[MPT_KOBJ_NAME_LEN]; + struct workqueue_struct *fc_rescan_work_q; +- /* driver forced bus resets count */ +- unsigned long hard_resets; +- /* fw/external bus resets count */ +- unsigned long soft_resets; +- /* cmd timeouts */ +- unsigned long timeouts; ++ unsigned long hard_resets; /* driver forced bus resets count */ ++ unsigned long soft_resets; /* fw/external bus resets count */ ++ unsigned long timeouts; /* cmd timeouts */ + struct scsi_cmnd **ScsiLookup; + spinlock_t scsi_lookup_lock; + int sdev_queue_depth; /* sdev queue depth */ +@@ -776,6 +806,11 @@ + #endif + u8 sg_addr_size; + u8 SGE_size; ++ u8 in_rescan; ++ /* diag buffer bits for sysfs */ ++ u8 is_fault; ++ u32 ring_buffer_offset; ++ u32 ring_buffer_sz; + } MPT_ADAPTER; + + /* +@@ -919,14 +954,10 @@ + extern int mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size); + extern void mpt_free_fw_memory(MPT_ADAPTER *ioc); + extern int mpt_findImVolumes(MPT_ADAPTER *ioc); +-extern int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, +- u8 persist_opcode); +-extern int mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num, +- pRaidPhysDiskPage0_t phys_disk); +-extern int mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num, +- pRaidPhysDiskPage1_t phys_disk); +-extern int mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, +- u8 phys_disk_num); ++extern int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode); ++extern int mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num, pRaidPhysDiskPage0_t phys_disk); ++extern int mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num, pRaidPhysDiskPage1_t phys_disk); ++extern int mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, u8 phys_disk_num); + + extern int mpt_set_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc); + extern void mpt_clear_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc); +@@ -936,6 +967,7 @@ + * Public data decl's... + */ + extern struct list_head ioc_list; ++extern struct proc_dir_entry *mpt_proc_root_dir; + extern int mpt_debug_level; + extern int mpt_fwfault_debug; + +diff -r 8807687e8e9c drivers/message/fusion/mptctl.c +--- a/drivers/message/fusion/mptctl.c Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/mptctl.c Tue Sep 01 16:11:22 2009 +0100 +@@ -75,7 +75,7 @@ + #if defined(CPQ_CIM) + #include "mptsas.h" + #include "csmi/csmisas.h" +-#endif ++#endif // CPQ_CIM + + #if defined(DIAG_BUFFER_SUPPORT) + #include "rejected_ioctls/diag_buffer.h" +@@ -148,7 +148,7 @@ + static int csmisas_phy_control(unsigned long arg); + static int csmisas_get_connector_info(unsigned long arg); + static int csmisas_get_location(unsigned long arg); +-#endif ++#endif // CPQ_CIM + + #if defined(DIAG_BUFFER_SUPPORT) + /* diag_buffer proto's */ +@@ -157,7 +157,7 @@ + static int mptctl_unregister_diag_buffer(unsigned long arg); + static int mptctl_query_diag_buffer(unsigned long arg); + static int mptctl_read_diag_buffer(unsigned long arg); +-#endif ++#endif // DIAG_BUFFER_SUPPORT + + static int mptctl_probe(struct pci_dev *, const struct pci_device_id *); + static void mptctl_remove(struct pci_dev *); +@@ -279,8 +279,7 @@ + le32_to_cpu(reply->u.reply.IOCLogInfo))); + + if ((req->u.hdr.Function == MPI_FUNCTION_SCSI_IO_REQUEST) || +- (req->u.hdr.Function +- == MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { ++ (req->u.hdr.Function == MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { + + if (reply->u.sreply.SCSIStatus || reply->u.sreply.SCSIState) + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT +@@ -291,8 +290,7 @@ + le16_to_cpu(reply->u.sreply.TaskTag), + le32_to_cpu(reply->u.sreply.TransferCount))); + +- if (reply->u.sreply.SCSIState +- & MPI_SCSI_STATE_AUTOSENSE_VALID) { ++ if (reply->u.sreply.SCSIState & MPI_SCSI_STATE_AUTOSENSE_VALID) { + sz = req->u.scsireq.SenseBufferLength; + req_index = + le16_to_cpu(req->u.frame.hwhdr.msgctxu.fld.req_idx); +@@ -326,8 +324,7 @@ + if (!mf) + return 0; + +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "TaskMgmt completed (mf=%p, mr=%p)\n", ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "TaskMgmt completed (mf=%p, mr=%p)\n", + ioc->name, mf, mr)); + + ioc->taskmgmt_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD; +@@ -366,10 +363,10 @@ + u16 iocstatus; + + /* bus reset is only good for SCSI IO, RAID PASSTHRU */ +- if (!(function == MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH) || +- (function == MPI_FUNCTION_SCSI_IO_REQUEST)) { +- dtmprintk(ioc, printk(MYIOC_s_WARN_FMT +- "TaskMgmt, not SCSI_IO!!\n", ioc->name)); ++ if (!(function == MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH || ++ function == MPI_FUNCTION_SCSI_IO_REQUEST)) { ++ dtmprintk(ioc, printk(MYIOC_s_WARN_FMT "TaskMgmt, not SCSI_IO!!\n", ++ ioc->name)); + return -EPERM; + } + +@@ -384,8 +381,8 @@ + /* Send request + */ + if ((mf = mpt_get_msg_frame(mptctl_taskmgmt_id, ioc)) == NULL) { +- dtmprintk(ioc, printk(MYIOC_s_WARN_FMT +- "TaskMgmt, no msg frames!!\n", ioc->name)); ++ dtmprintk(ioc, printk(MYIOC_s_WARN_FMT "TaskMgmt, no msg frames!!\n", ++ ioc->name)); + mpt_clear_taskmgmt_in_progress_flag(ioc); + retval = -ENOMEM; + goto mptctl_bus_reset_done; +@@ -411,34 +408,31 @@ + pScsiTm->Reserved2[ii] = 0; + + switch (ioc->bus_type) { +- case FC: +- timeout = 40; +- break; +- case SAS: +- timeout = 30; +- break; +- case SPI: +- default: +- timeout = 10; +- break; ++ case FC: ++ timeout = 40; ++ break; ++ case SAS: ++ timeout = 30; ++ break; ++ case SPI: ++ default: ++ timeout = 2; ++ break; + } + +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "TaskMgmt type=%d timeout=%ld\n", ioc->name, +- MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS, timeout)); ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "TaskMgmt type=%d timeout=%ld\n", ++ ioc->name, MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS, timeout)); + + INITIALIZE_MGMT_STATUS(ioc->taskmgmt_cmds.status) +- CLEAR_MGMT_STATUS(ioc->taskmgmt_cmds.status) + time_count = jiffies; + if ((ioc->facts.IOCCapabilities & MPI_IOCFACTS_CAPABILITY_HIGH_PRI_Q) && + (ioc->facts.MsgVersion >= MPI_VERSION_01_05)) + mpt_put_msg_frame_hi_pri(mptctl_taskmgmt_id, ioc, mf); + else { + retval = mpt_send_handshake_request(mptctl_taskmgmt_id, ioc, +- sizeof(SCSITaskMgmt_t), (u32 *)pScsiTm, CAN_SLEEP); ++ sizeof(SCSITaskMgmt_t), (u32*)pScsiTm, CAN_SLEEP); + if (retval != 0) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "TaskMgmt send_handshake FAILED!" ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT "TaskMgmt send_handshake FAILED!" + " (ioc %p, mf %p, rc=%d) \n", ioc->name, + ioc, mf, retval)); + mpt_clear_taskmgmt_in_progress_flag(ioc); +@@ -503,10 +497,11 @@ + unsigned long flags; + + dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": %s\n", +- ioc->name, __func__)); ++ ioc->name, __FUNCTION__)); + +- if (mpt_fwfault_debug) ++ if(mpt_fwfault_debug) + mpt_halt_firmware(ioc); ++ + spin_lock_irqsave(&ioc->taskmgmt_lock, flags); + if (ioc->ioc_reset_in_progress) { + spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); +@@ -517,6 +512,7 @@ + spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); + + ++ CLEAR_MGMT_PENDING_STATUS(ioc->ioctl_cmds.status) + if (!mptctl_bus_reset(ioc, mf->u.hdr.Function)) + return; + +@@ -525,7 +521,6 @@ + */ + dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Calling HardReset! \n", + ioc->name)); +- CLEAR_MGMT_PENDING_STATUS(ioc->ioctl_cmds.status) + if (mpt_SoftResetHandler(ioc, CAN_SLEEP) != 0) + mpt_HardResetHandler(ioc, CAN_SLEEP); + mpt_free_msg_frame(ioc, mf); +@@ -580,6 +575,8 @@ + return 1; + + /* Raise SIGIO for persistent events. ++ * TODO - this define is not in MPI spec yet, ++ * but they plan to set it to 0x21 + */ + if (event == 0x21 ) { + ioc->aen_event_read_flag=1; +@@ -662,9 +659,8 @@ + if (((iocnum = mpt_verify_adapter(iocnumX, &iocp)) < 0) || + (iocp == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "%s::%s @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnumX); ++ printk(KERN_DEBUG MYNAM "%s::mptctl_ioctl() @%d - ioc%d not found!\n", ++ __FILE__, __LINE__, iocnumX); + return -ENODEV; + } + +@@ -703,9 +699,9 @@ + return csmisas_get_cntlr_status(arg); + } else if (cmd == CC_CSMI_SAS_GET_SCSI_ADDRESS) { + return csmisas_get_scsi_address(arg); +- } else if (cmd == CC_CSMI_SAS_GET_DEVICE_ADDRESS) { ++ } else if (cmd == CC_CSMI_SAS_GET_DEVICE_ADDRESS){ + return csmisas_get_device_address(arg); +-#endif ++#endif // CPQ_CIM + } + + /* All of these commands require an interrupt or +@@ -713,6 +709,8 @@ + */ + if ((ret = mptctl_syscall_down(iocp, nonblock)) != 0) + return ret; ++ ++// dctlprintk(iocp, printk(MYIOC_s_DEBUG_FMT ": mptctl_ioctl()\n", iocp->name)); + + if (cmd == MPTFWDOWNLOAD) + ret = mptctl_fw_download(arg); +@@ -764,7 +762,7 @@ + ret = csmisas_get_connector_info(arg); + else if (cmd == CC_CSMI_SAS_GET_LOCATION) + ret = csmisas_get_location(arg); +-#endif ++#endif // CPQ_CIM + + #if defined(DIAG_BUFFER_SUPPORT) + /* diag_buffer requiring fw calls*/ +@@ -774,7 +772,7 @@ + ret = mptctl_release_diag_buffer(arg); + else if (cmd == MPTDIAGREADBUFFER) + ret = mptctl_read_diag_buffer(arg); +-#endif ++#endif // DIAG_BUFFER_SUPPORT + else + ret = -EINVAL; + +@@ -808,9 +806,8 @@ + + if (mpt_verify_adapter(krinfo.hdr.iocnum, &iocp) < 0) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "%s@%d::%s - ioc%d not found!\n", +- __FILE__, __LINE__, __func__, krinfo.hdr.iocnum); ++ printk(KERN_DEBUG MYNAM "%s@%d::mptctl_do_reset - ioc%d not found!\n", ++ __FILE__, __LINE__, krinfo.hdr.iocnum); + return -ENODEV; /* (-6) No such device or address */ + } + +@@ -900,8 +897,7 @@ + + if (mpt_verify_adapter(ioc, &iocp) < 0) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "ioctl_fwdl - ioc%d not found!\n", ioc); ++ printk(KERN_DEBUG MYNAM "ioctl_fwdl - ioc%d not found!\n", ioc); + return -ENODEV; /* (-6) No such device or address */ + } else { + +@@ -985,7 +981,7 @@ + / iocp->SGE_size; + if (numfrags > maxfrags) { + ret = -EMLINK; +- goto fwdl_out; ++ goto fwdl_out; + } + + dctlprintk(iocp, printk(MYIOC_s_DEBUG_FMT "DbG: sgl buffer = %p, sgfrags = %d\n", +@@ -1036,21 +1032,24 @@ + mpt_put_msg_frame(mptctl_id, iocp, mf); + + /* Now wait for the command to complete */ ++retry_wait: + timeleft = wait_for_completion_timeout(&iocp->ioctl_cmds.done, HZ*60); + if (!(iocp->ioctl_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { + ret = -ETIME; +- printk(MYIOC_s_WARN_FMT "%s: failed\n", iocp->name, __func__); ++ printk(MYIOC_s_WARN_FMT "%s: failed\n", iocp->name, __FUNCTION__); + if (iocp->ioctl_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) { + mpt_free_msg_frame(iocp, mf); + goto fwdl_out; + } + if (!timeleft) + mptctl_timeout_expired(iocp, mf); ++ else ++ goto retry_wait; + goto fwdl_out; + } + + if (!(iocp->ioctl_cmds.status & MPT_MGMT_STATUS_RF_VALID)) { +- printk(MYIOC_s_WARN_FMT "%s: failed\n", iocp->name, __func__); ++ printk(MYIOC_s_WARN_FMT "%s: failed\n", iocp->name, __FUNCTION__); + mpt_free_msg_frame(iocp, mf); + ret = -ENODATA; + goto fwdl_out; +@@ -1062,12 +1061,10 @@ + ReplyMsg = (pFWDownloadReply_t)iocp->ioctl_cmds.reply; + iocstat = le16_to_cpu(ReplyMsg->IOCStatus) & MPI_IOCSTATUS_MASK; + if (iocstat == MPI_IOCSTATUS_SUCCESS) { +- printk(MYIOC_s_INFO_FMT +- ": F/W update successfully sent!\n", iocp->name); ++ printk(MYIOC_s_INFO_FMT ": F/W update successfully sent!\n", iocp->name); + return 0; + } else if (iocstat == MPI_IOCSTATUS_INVALID_FUNCTION) { +- printk(MYIOC_s_WARN_FMT +- "Hmmm... doesn't support F/W download?\n", ++ printk(MYIOC_s_WARN_FMT "Hmmm... doesn't support F/W download?\n", + iocp->name); + printk(MYIOC_s_WARN_FMT "(time to go bang on somebodies door)\n", + iocp->name); +@@ -1182,8 +1179,7 @@ + bytes_allocd += this_alloc; + sgl->FlagsLength = (0x10000000|sgdir|this_alloc); + if (ioc->sg_addr_size == sizeof(u64)) +- sgl->FlagsLength +- |= MPT_SGE_FLAGS_64_BIT_ADDRESSING; ++ sgl->FlagsLength |= MPT_SGE_FLAGS_64_BIT_ADDRESSING; + dma_addr = pci_map_single(ioc->pcidev, buflist[buflist_ent].kptr, this_alloc, dir); + sgl->Address = dma_addr; + +@@ -1368,9 +1364,8 @@ + if (((iocnum = mpt_verify_adapter(karg->hdr.iocnum, &ioc)) < 0) || + (ioc == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "%s::%s @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ printk(KERN_DEBUG MYNAM "%s::mptctl_getiocinfo() @%d - ioc%d not found!\n", ++ __FILE__, __LINE__, iocnum); + kfree(karg); + return -ENODEV; + } +@@ -1505,9 +1500,8 @@ + if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || + (ioc == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "%s::%s @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ printk(KERN_DEBUG MYNAM "%s::mptctl_gettargetinfo() @%d - ioc%d not found!\n", ++ __FILE__, __LINE__, iocnum); + return -ENODEV; + } + +@@ -1522,8 +1516,7 @@ + port = karg.hdr.port; + + if (maxWordsLeft <= 0) { +- printk(MYIOC_s_ERR_FMT +- "%s::mptctl_gettargetinfo() @%d - no memory available!\n", ++ printk(MYIOC_s_ERR_FMT "%s::mptctl_gettargetinfo() @%d - no memory available!\n", + ioc->name, __FILE__, __LINE__); + return -ENOMEM; + } +@@ -1544,8 +1537,7 @@ + */ + pmem = kzalloc(numBytes, GFP_KERNEL); + if (!pmem) { +- printk(MYIOC_s_ERR_FMT +- "%s::mptctl_gettargetinfo() @%d - no memory available!\n", ++ printk(MYIOC_s_ERR_FMT "%s::mptctl_gettargetinfo() @%d - no memory available!\n", + ioc->name, __FILE__, __LINE__); + return -ENOMEM; + } +@@ -1625,9 +1617,8 @@ + if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || + (ioc == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "%s::%s @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ printk(KERN_DEBUG MYNAM "%s::mptctl_readtest() @%d - ioc%d not found!\n", ++ __FILE__, __LINE__, iocnum); + return -ENODEV; + } + +@@ -1688,9 +1679,8 @@ + if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || + (ioc == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "%s::%s @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ printk(KERN_DEBUG MYNAM "%s::mptctl_eventquery() @%d - ioc%d not found!\n", ++ __FILE__, __LINE__, iocnum); + return -ENODEV; + } + +@@ -1729,9 +1719,8 @@ + if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || + (ioc == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "%s::%s @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ printk(KERN_DEBUG MYNAM "%s::mptctl_eventenable() @%d - ioc%d not found!\n", ++ __FILE__, __LINE__, iocnum); + return -ENODEV; + } + +@@ -1743,8 +1732,7 @@ + int sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS); + ioc->events = kzalloc(sz, GFP_KERNEL); + if (!ioc->events) { +- printk(MYIOC_s_ERR_FMT +- "Insufficient memory to add adapter!\n", ++ printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n", + ioc->name); + return -ENOMEM; + } +@@ -1780,9 +1768,8 @@ + if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || + (ioc == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "%s::%s @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ printk(KERN_DEBUG MYNAM "%s::mptctl_eventreport() @%d - ioc%d not found!\n", ++ __FILE__, __LINE__, iocnum); + return -ENODEV; + } + +@@ -1836,9 +1823,8 @@ + if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || + (ioc == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "%s::%s @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ printk(KERN_DEBUG MYNAM "%s::mptctl_replace_fw() @%d - ioc%d not found!\n", ++ __FILE__, __LINE__, iocnum); + return -ENODEV; + } + +@@ -1886,8 +1872,7 @@ + * + * Outputs: None. + * Return: 0 if successful +- * -EBUSY if previous command timout and IOC reset is +- * not complete. ++ * -EBUSY if previous command timout and IOC reset is not complete. + * -EFAULT if data unavailable + * -ENODEV if no such device/adapter + * -ETIME if timer expires +@@ -1913,9 +1898,8 @@ + if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || + (ioc == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "%s::%s @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ printk(KERN_DEBUG MYNAM "%s::mptctl_mpt_command() @%d - ioc%d not found!\n", ++ __FILE__, __LINE__, iocnum); + return -ENODEV; + } + +@@ -1929,8 +1913,7 @@ + * + * Outputs: None. + * Return: 0 if successful +- * -EBUSY if previous command timout and IOC reset is +- * not complete. ++ * -EBUSY if previous command timout and IOC reset is not complete. + * -EFAULT if data unavailable + * -ENODEV if no such device/adapter + * -ETIME if timer expires +@@ -1967,9 +1950,8 @@ + if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || + (ioc == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "%s::%s @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ printk(KERN_DEBUG MYNAM "%s::mptctl_do_mpt_command() @%d - ioc%d not found!\n", ++ __FILE__, __LINE__, iocnum); + return -ENODEV; + } + +@@ -2214,12 +2196,10 @@ + { + SCSITaskMgmt_t *pScsiTm; + pScsiTm = (SCSITaskMgmt_t *)mf; +- dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "\tTaskType=0x%x MsgFlags=0x%x " +- "TaskMsgContext=0x%x id=%d channel=%d\n", +- ioc->name, pScsiTm->TaskType, +- le32_to_cpu(pScsiTm->TaskMsgContext), +- pScsiTm->MsgFlags, pScsiTm->TargetID, pScsiTm->Bus)); ++ dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "\tTaskType=0x%x MsgFlags=0x%x " ++ "TaskMsgContext=0x%x id=%d channel=%d\n", ioc->name, pScsiTm->TaskType, ++ le32_to_cpu(pScsiTm->TaskMsgContext), pScsiTm->MsgFlags, ++ pScsiTm->TargetID, pScsiTm->Bus)); + break; + } + +@@ -2308,9 +2288,9 @@ + /* Set up the dataOut memory allocation */ + if (karg.dataOutSize > 0) { + if (karg.dataInSize > 0) { +- flagsLength = (MPI_SGE_FLAGS_SIMPLE_ELEMENT | ++ flagsLength = ( MPI_SGE_FLAGS_SIMPLE_ELEMENT | + MPI_SGE_FLAGS_END_OF_BUFFER | +- MPI_SGE_FLAGS_DIRECTION) ++ MPI_SGE_FLAGS_DIRECTION ) + << MPI_SGE_FLAGS_SHIFT; + } else { + flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE; +@@ -2387,7 +2367,7 @@ + mpt_put_msg_frame_hi_pri(mptctl_id, ioc, mf); + else { + rc = mpt_send_handshake_request(mptctl_id, ioc, +- sizeof(SCSITaskMgmt_t), (u32 *)mf, CAN_SLEEP); ++ sizeof(SCSITaskMgmt_t), (u32*)mf, CAN_SLEEP); + if (rc != 0) { + dfailprintk(ioc, printk(MYIOC_s_ERR_FMT + "send_handshake FAILED! (ioc %p, mf %p)\n", +@@ -2403,20 +2383,25 @@ + + /* Now wait for the command to complete */ + timeout = (karg.timeout > 0) ? karg.timeout : MPT_IOCTL_DEFAULT_TIMEOUT; +- timeleft = +- wait_for_completion_timeout(&ioc->ioctl_cmds.done, HZ*timeout); ++retry_wait: ++ timeleft = wait_for_completion_timeout(&ioc->ioctl_cmds.done, HZ*timeout); + if (!(ioc->ioctl_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { + rc = -ETIME; + dfailprintk(ioc, printk(MYIOC_s_ERR_FMT "%s: TIMED OUT!\n", +- ioc->name, __func__)); +- if (function == MPI_FUNCTION_SCSI_TASK_MGMT) +- mutex_unlock(&ioc->taskmgmt_cmds.mutex); +- if (ioc->ioctl_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) ++ ioc->name, __FUNCTION__)); ++ if (ioc->ioctl_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) { ++ if (function == MPI_FUNCTION_SCSI_TASK_MGMT) ++ mutex_unlock(&ioc->taskmgmt_cmds.mutex); + goto done_free_mem; ++ } + if (!timeleft) { ++ if (function == MPI_FUNCTION_SCSI_TASK_MGMT) ++ mutex_unlock(&ioc->taskmgmt_cmds.mutex); + mptctl_timeout_expired(ioc, mf); + mf = NULL; + } ++ else ++ goto retry_wait; + goto done_free_mem; + } + +@@ -2430,8 +2415,7 @@ + */ + if (ioc->ioctl_cmds.status & MPT_MGMT_STATUS_RF_VALID) { + if (karg.maxReplyBytes < ioc->reply_sz) { +- sz = min(karg.maxReplyBytes, +- 4*ioc->ioctl_cmds.reply[2]); ++ sz = min(karg.maxReplyBytes, 4*ioc->ioctl_cmds.reply[2]); + } else { + sz = min(ioc->reply_sz, 4*ioc->ioctl_cmds.reply[2]); + } +@@ -2453,8 +2437,7 @@ + if (ioc->ioctl_cmds.status & MPT_MGMT_STATUS_SENSE_VALID) { + sz = min(karg.maxSenseBytes, MPT_SENSE_BUFFER_SIZE); + if (sz > 0) { +- if (copy_to_user(karg.senseDataPtr, +- ioc->ioctl_cmds.sense, sz)) { ++ if (copy_to_user(karg.senseDataPtr, ioc->ioctl_cmds.sense, sz)) { + printk(MYIOC_s_ERR_FMT "%s@%d::mptctl_do_mpt_command - " + "Unable to write sense data to user %p\n", + ioc->name, __FILE__, __LINE__, +@@ -2512,8 +2495,7 @@ + * Outputs: None. + * Return: 0 if successful + * -EFAULT if data unavailable +- * -EBUSY if previous command timout and IOC reset is +- * not complete. ++ * -EBUSY if previous command timout and IOC reset is not complete. + * -ENODEV if no such device/adapter + * -ETIME if timer expires + * -ENOMEM if memory allocation error +@@ -2524,7 +2506,7 @@ + hp_host_info_t __user *uarg = (void __user *) arg; + MPT_ADAPTER *ioc; + struct pci_dev *pdev; +- char *pbuf = NULL; ++ char *pbuf=NULL; + dma_addr_t buf_dma; + hp_host_info_t karg; + int iocnum; +@@ -2555,9 +2537,8 @@ + if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || + (ioc == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "%s::%s @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ printk(KERN_DEBUG MYNAM "%s::mptctl_hp_hostinfo() @%d - ioc%d not found!\n", ++ __FILE__, __LINE__, iocnum); + return -ENODEV; + } + +@@ -2645,7 +2626,7 @@ + */ + if ((mf = mpt_get_msg_frame(mptctl_id, ioc)) == NULL) { + dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n", +- ioc->name,__func__)); ++ ioc->name,__FUNCTION__)); + retval = -ENOMEM; + goto out; + } +@@ -2670,29 +2651,29 @@ + retval = -ENOMEM; + goto out; + } +- ioc->add_sge((char *)&IstwiRWRequest->SGL, +- (MPT_SGE_FLAGS_SSIMPLE_READ|4), buf_dma); ++ ioc->add_sge((char *)&IstwiRWRequest->SGL, (MPT_SGE_FLAGS_SSIMPLE_READ|4),buf_dma); + + retval = 0; +- SET_MGMT_MSG_CONTEXT(ioc->ioctl_cmds.msg_context, +- IstwiRWRequest->MsgContext); ++ SET_MGMT_MSG_CONTEXT(ioc->ioctl_cmds.msg_context, IstwiRWRequest->MsgContext); + INITIALIZE_MGMT_STATUS(ioc->ioctl_cmds.status) + mpt_put_msg_frame(mptctl_id, ioc, mf); +- timeleft = wait_for_completion_timeout(&ioc->ioctl_cmds.done, +- HZ*MPT_IOCTL_DEFAULT_TIMEOUT); ++retry_wait: ++ timeleft = wait_for_completion_timeout(&ioc->ioctl_cmds.done, HZ*MPT_IOCTL_DEFAULT_TIMEOUT); + if (!(ioc->ioctl_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { + retval = -ETIME; +- printk(MYIOC_s_WARN_FMT "%s: failed\n", ioc->name, __func__); ++ printk(MYIOC_s_WARN_FMT "%s: failed\n", ioc->name, __FUNCTION__); + if (ioc->ioctl_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) { + mpt_free_msg_frame(ioc, mf); + goto out; + } + if (!timeleft) + mptctl_timeout_expired(ioc, mf); ++ else ++ goto retry_wait; + goto out; + } + +- /* ++ /* + *ISTWI Data Definition + * pbuf[0] = FW_VERSION = 0x4 + * pbuf[1] = Bay Count = 6 or 4 or 2, depending on +@@ -2730,8 +2711,7 @@ + * Outputs: None. + * Return: 0 if successful + * -EFAULT if data unavailable +- * -EBUSY if previous command timout and IOC reset is +- * not complete. ++ * -EBUSY if previous command timout and IOC reset is not complete. + * -ENODEV if no such device/adapter + * -ETIME if timer expires + * -ENOMEM if memory allocation error +@@ -2762,14 +2742,12 @@ + if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || + (ioc == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "%s::%s @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ printk(KERN_DEBUG MYNAM "%s::mptctl_hp_targetinfo() @%d - ioc%d not found!\n", ++ __FILE__, __LINE__, iocnum); + return -ENODEV; + } + +- dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- ": mptctl_hp_targetinfo called.\n", ++ dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": mptctl_hp_targetinfo called.\n", + ioc->name)); + /* There is nothing to do for FCP parts. + */ +@@ -2921,9 +2899,8 @@ + if (((iocnum = mpt_verify_adapter(iocnumX, &iocp)) < 0) || + (iocp == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "::%s @%d - ioc%d not found!\n", __func__, +- __LINE__, iocnumX); ++ printk(KERN_DEBUG MYNAM "::compat_mptfwxfer_ioctl @%d - ioc%d not found!\n", ++ __LINE__, iocnumX); + return -ENODEV; + } + +@@ -2963,9 +2940,8 @@ + if (((iocnum = mpt_verify_adapter(iocnumX, &iocp)) < 0) || + (iocp == NULL)) { + if (mpt_debug_level & MPT_DEBUG_IOCTL) +- printk(KERN_DEBUG MYNAM +- "::%s @%d - ioc%d not found!\n", +- __func__, __LINE__, iocnumX); ++ printk(KERN_DEBUG MYNAM "::compat_mpt_command @%d - ioc%d not found!\n", ++ __LINE__, iocnumX); + return -ENODEV; + } + +@@ -3178,7 +3154,7 @@ + + #if defined(CPQ_CIM) + #include "csmi/csmisas.c" +-#endif ++#endif // CPQ_CIM + + #if defined(DIAG_BUFFER_SUPPORT) + #include "rejected_ioctls/diag_buffer.c" +diff -r 8807687e8e9c drivers/message/fusion/mptfc.c +--- a/drivers/message/fusion/mptfc.c Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/mptfc.c Tue Sep 01 16:11:23 2009 +0100 +@@ -43,7 +43,7 @@ + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +- ++#include + #include + #include + #include +@@ -65,6 +65,7 @@ + #include + #include + ++#include "linux_compat.h" /* linux-2.6 tweaks */ + #include "mptbase.h" + #include "mptscsih.h" + +@@ -235,7 +236,7 @@ + int ready; + MPT_ADAPTER *ioc; + +- hd = shost_priv(SCpnt->device->host); ++ hd = shost_private(SCpnt->device->host); + ioc = hd->ioc; + spin_lock_irqsave(shost->host_lock, flags); + while ((ready = fc_remote_port_chkready(rport) >> 16) == DID_IMM_RETRY) { +@@ -270,28 +271,28 @@ + mptfc_abort(struct scsi_cmnd *SCpnt) + { + return +- mptfc_block_error_handler(SCpnt, mptscsih_abort, __func__); ++ mptfc_block_error_handler(SCpnt, mptscsih_abort, __FUNCTION__); + } + + static int + mptfc_dev_reset(struct scsi_cmnd *SCpnt) + { + return +- mptfc_block_error_handler(SCpnt, mptscsih_dev_reset, __func__); ++ mptfc_block_error_handler(SCpnt, mptscsih_dev_reset, __FUNCTION__); + } + + static int + mptfc_bus_reset(struct scsi_cmnd *SCpnt) + { + return +- mptfc_block_error_handler(SCpnt, mptscsih_bus_reset, __func__); ++ mptfc_block_error_handler(SCpnt, mptscsih_bus_reset, __FUNCTION__); + } + + static int + mptfc_host_reset(struct scsi_cmnd *SCpnt) + { + return +- mptfc_block_error_handler(SCpnt, mptscsih_host_reset, __func__); ++ mptfc_block_error_handler(SCpnt, mptscsih_host_reset, __FUNCTION__); + } + + static void +@@ -553,6 +554,7 @@ + struct fc_rport *rport; + struct mptfc_rport_info *ri; + ++ printk("%s - starget=%p\n", __FUNCTION__, starget); + rport = starget_to_rport(starget); + if (rport) { + ri = *((struct mptfc_rport_info **)rport->dd_data); +@@ -652,7 +654,7 @@ + if (!rport || fc_remote_port_chkready(rport)) + return -ENXIO; + +- hd = shost_priv(sdev->host); ++ hd = shost_private(sdev->host); + ioc = hd->ioc; + vdevice = kzalloc(sizeof(VirtDevice), GFP_KERNEL); + if (!vdevice) { +@@ -993,8 +995,7 @@ + #define OFF_FLAGS (MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS) + + for (ii=0; iifacts.NumberOfPorts; ii++) { +- rc = mptfc_GetFcPortPage1(ioc, ii); +- if (rc < 0) ++ if ((rc = mptfc_GetFcPortPage1(ioc, ii)) < 0) + return rc; + pp1 = ioc->fc_data.fc_port_page1[ii].data; + if ((pp1->InitiatorDeviceTimeout == MPTFC_FW_DEVICE_TIMEOUT) +@@ -1006,8 +1007,7 @@ + pp1->InitiatorIoPendTimeout = MPTFC_FW_IO_PEND_TIMEOUT; + pp1->Flags &= ~OFF_FLAGS; + pp1->Flags |= ON_FLAGS; +- rc = mptfc_WriteFcPortPage1(ioc, ii); +- if (rc < 0) ++ if ((rc = mptfc_WriteFcPortPage1(ioc, ii)) < 0) + return rc; + } + return 0; +@@ -1109,10 +1109,16 @@ + } + + static void ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + mptfc_link_status_change(struct work_struct *work) + { + MPT_ADAPTER *ioc = + container_of(work, MPT_ADAPTER, fc_rescan_work); ++#else ++mptfc_link_status_change(void *arg) ++{ ++ MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg; ++#endif + int ii; + + for (ii=0; ii < ioc->facts.NumberOfPorts; ii++) +@@ -1121,10 +1127,16 @@ + } + + static void ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + mptfc_setup_reset(struct work_struct *work) + { + MPT_ADAPTER *ioc = + container_of(work, MPT_ADAPTER, fc_setup_reset_work); ++#else ++mptfc_setup_reset(void *arg) ++{ ++ MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg; ++#endif + u64 pn; + struct mptfc_rport_info *ri; + struct scsi_target *starget; +@@ -1156,10 +1168,16 @@ + } + + static void ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + mptfc_rescan_devices(struct work_struct *work) + { + MPT_ADAPTER *ioc = + container_of(work, MPT_ADAPTER, fc_rescan_work); ++#else ++mptfc_rescan_devices(void *arg) ++{ ++ MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg; ++#endif + int ii; + int rc; + u64 pn; +@@ -1171,9 +1189,8 @@ + * if cannot set defaults, something's really wrong, bail out + */ + +- rc = mptfc_SetFcPortPage1_defaults(ioc); +- if (rc < 0) { +- dfcprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ if ((rc = mptfc_SetFcPortPage1_defaults(ioc)) < 0) { ++ dfcprintk (ioc, printk(MYIOC_s_DEBUG_FMT + "mptfc_rescan.%d: unable to set PP1 defaults, rc %d.\n", + ioc->name, ioc->sh->host_no, rc)); + return; +@@ -1289,9 +1306,15 @@ + } + + spin_lock_init(&ioc->fc_rescan_work_lock); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + INIT_WORK(&ioc->fc_rescan_work, mptfc_rescan_devices); + INIT_WORK(&ioc->fc_setup_reset_work, mptfc_setup_reset); + INIT_WORK(&ioc->fc_lsc_work, mptfc_link_status_change); ++#else ++ INIT_WORK(&ioc->fc_rescan_work, mptfc_rescan_devices,(void *)ioc); ++ INIT_WORK(&ioc->fc_setup_reset_work, mptfc_setup_reset, (void *)ioc); ++ INIT_WORK(&ioc->fc_lsc_work, mptfc_link_status_change, (void *)ioc); ++#endif + + spin_lock_irqsave(&ioc->FreeQlock, flags); + +@@ -1347,7 +1370,7 @@ + + spin_unlock_irqrestore(&ioc->FreeQlock, flags); + +- hd = shost_priv(sh); ++ hd = shost_private(sh); + hd->ioc = ioc; + + /* SCSI needs scsi_cmnd lookup table! +@@ -1375,9 +1398,8 @@ + + /* initialize workqueue */ + +- snprintf(ioc->fc_rescan_work_q_name, +- sizeof(ioc->fc_rescan_work_q_name), "mptfc_wq_%d", +- sh->host_no); ++ snprintf(ioc->fc_rescan_work_q_name, MPT_KOBJ_NAME_LEN, "mptfc_wq_%d", ++ sh->host_no); + ioc->fc_rescan_work_q = + create_singlethread_workqueue(ioc->fc_rescan_work_q_name); + if (!ioc->fc_rescan_work_q) +@@ -1428,7 +1450,7 @@ + int rc=1; + + if (ioc->sh == NULL || +- ((hd = shost_priv(ioc->sh)) == NULL)) ++ ((hd = shost_private(ioc->sh)) == NULL)) + return 1; + + switch (event) { +@@ -1465,10 +1487,10 @@ + if ((ioc->bus_type != FC) || (!rc)) + return rc; + +- switch (reset_phase) { ++ switch(reset_phase) { + case MPT_IOC_SETUP_RESET: + dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__)); ++ "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __FUNCTION__)); + spin_lock_irqsave(&ioc->fc_rescan_work_lock, flags); + if (ioc->fc_rescan_work_q) { + queue_work(ioc->fc_rescan_work_q, +@@ -1478,11 +1500,11 @@ + break; + case MPT_IOC_PRE_RESET: + dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__)); ++ "%s: MPT_IOC_PRE_RESET\n", ioc->name, __FUNCTION__)); + break; + case MPT_IOC_POST_RESET: + dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__)); ++ "%s: MPT_IOC_POST_RESET\n", ioc->name, __FUNCTION__)); + spin_lock_irqsave(&ioc->fc_rescan_work_lock, flags); + if (ioc->fc_rescan_work_q) { + queue_work(ioc->fc_rescan_work_q, +@@ -1496,12 +1518,11 @@ + return 1; + } + +-/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** + * mptfc_init - Register MPT adapter(s) as SCSI host(s) with SCSI mid-layer. + * + * Returns 0 for success, non-zero for failure. +- */ ++ **/ + static int __init + mptfc_init(void) + { +@@ -1533,12 +1554,11 @@ + return error; + } + +-/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** + * mptfc_remove - Remove fc infrastructure for devices + * @pdev: Pointer to pci_dev structure + * +- */ ++ **/ + static void __devexit + mptfc_remove(struct pci_dev *pdev) + { +@@ -1547,6 +1567,8 @@ + struct workqueue_struct *work_q; + unsigned long flags; + int ii; ++ ++ printk("%s -pdev=%p\n", __FUNCTION__, pdev); + + /* destroy workqueue */ + if ((work_q=ioc->fc_rescan_work_q)) { +diff -r 8807687e8e9c drivers/message/fusion/mptlan.c +--- a/drivers/message/fusion/mptlan.c Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/mptlan.c Tue Sep 01 16:11:23 2009 +0100 +@@ -52,6 +52,7 @@ + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + + #include "mptlan.h" ++#include + #include + #include + #include +@@ -113,8 +114,12 @@ + u32 total_received; + struct net_device_stats stats; /* Per device statistics */ + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + struct delayed_work post_buckets_task; + struct net_device *dev; ++#else ++ struct work_struct post_buckets_task; ++#endif + unsigned long post_buckets_active; + }; + +@@ -135,7 +140,11 @@ + static int mpt_lan_open(struct net_device *dev); + static int mpt_lan_reset(struct net_device *dev); + static int mpt_lan_close(struct net_device *dev); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + static void mpt_lan_post_receive_buckets(struct mpt_lan_priv *priv); ++#else ++static void mpt_lan_post_receive_buckets(void *dev_id); ++#endif + static void mpt_lan_wake_post_buckets_task(struct net_device *dev, + int priority); + static int mpt_lan_receive_post_turbo(struct net_device *dev, u32 tmsg); +@@ -346,7 +355,11 @@ + priv->mpt_rxfidx[++priv->mpt_rxfidx_tail] = i; + spin_unlock_irqrestore(&priv->rxfidx_lock, flags); + } else { ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + mpt_lan_post_receive_buckets(priv); ++#else ++ mpt_lan_post_receive_buckets(dev); ++#endif + netif_wake_queue(dev); + } + +@@ -442,7 +455,11 @@ + + dlprintk((KERN_INFO MYNAM "/lo: Finished initializing RcvCtl\n")); + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + mpt_lan_post_receive_buckets(priv); ++#else ++ mpt_lan_post_receive_buckets(dev); ++#endif + + printk(KERN_INFO MYNAM ": %s/%s: interface up & active\n", + IOC_AND_NETDEV_NAMES_s_s(dev)); +@@ -614,7 +631,7 @@ + + dioprintk((KERN_INFO MYNAM ": %s/%s: @%s, skb %p sent.\n", + IOC_AND_NETDEV_NAMES_s_s(dev), +- __func__, sent)); ++ __FUNCTION__, sent)); + + priv->SendCtl[ctx].skb = NULL; + pci_unmap_single(mpt_dev->pcidev, priv->SendCtl[ctx].dma, +@@ -680,7 +697,7 @@ + + dioprintk((KERN_INFO MYNAM ": %s/%s: @%s, skb %p sent.\n", + IOC_AND_NETDEV_NAMES_s_s(dev), +- __func__, sent)); ++ __FUNCTION__, sent)); + + priv->SendCtl[ctx].skb = NULL; + pci_unmap_single(mpt_dev->pcidev, priv->SendCtl[ctx].dma, +@@ -712,14 +729,16 @@ + LANSendRequest_t *pSendReq; + SGETransaction32_t *pTrans; + SGESimple64_t *pSimple; ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)) + const unsigned char *mac; ++#endif + dma_addr_t dma; + unsigned long flags; + int ctx; + u16 cur_naa = 0x1000; + + dioprintk((KERN_INFO MYNAM ": %s called, skb_addr = %p\n", +- __func__, skb)); ++ __FUNCTION__, skb)); + + spin_lock_irqsave(&priv->txfidx_lock, flags); + if (priv->mpt_txfidx_tail < 0) { +@@ -727,7 +746,7 @@ + spin_unlock_irqrestore(&priv->txfidx_lock, flags); + + printk (KERN_ERR "%s: no tx context available: %u\n", +- __func__, priv->mpt_txfidx_tail); ++ __FUNCTION__, priv->mpt_txfidx_tail); + return 1; + } + +@@ -737,7 +756,7 @@ + spin_unlock_irqrestore(&priv->txfidx_lock, flags); + + printk (KERN_ERR "%s: Unable to alloc request frame\n", +- __func__); ++ __FUNCTION__); + return 1; + } + +@@ -752,7 +771,11 @@ + /* Set the mac.raw pointer, since this apparently isn't getting + * done before we get the skb. Pull the data pointer past the mac data. + */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)) + skb_reset_mac_header(skb); ++#else ++ skb->mac.raw = skb->data; ++#endif + skb_pull(skb, 12); + + dma = pci_map_single(mpt_dev->pcidev, skb->data, skb->len, +@@ -783,7 +806,9 @@ + // IOC_AND_NETDEV_NAMES_s_s(dev), + // ctx, skb, skb->data)); + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)) + mac = skb_mac_header(skb); ++#endif + + #ifdef QLOGIC_NAA_WORKAROUND + { +@@ -794,12 +819,21 @@ + drops. */ + read_lock_irq(&bad_naa_lock); + for (nh = mpt_bad_naa; nh != NULL; nh=nh->next) { ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)) + if ((nh->ieee[0] == mac[0]) && + (nh->ieee[1] == mac[1]) && + (nh->ieee[2] == mac[2]) && + (nh->ieee[3] == mac[3]) && + (nh->ieee[4] == mac[4]) && + (nh->ieee[5] == mac[5])) { ++#else ++ if ((nh->ieee[0] == skb->mac.raw[0]) && ++ (nh->ieee[1] == skb->mac.raw[1]) && ++ (nh->ieee[2] == skb->mac.raw[2]) && ++ (nh->ieee[3] == skb->mac.raw[3]) && ++ (nh->ieee[4] == skb->mac.raw[4]) && ++ (nh->ieee[5] == skb->mac.raw[5])) { ++#endif + cur_naa = nh->NAA; + dlprintk ((KERN_INFO "mptlan/sdu_send: using NAA value " + "= %04x.\n", cur_naa)); +@@ -811,6 +845,7 @@ + #endif + + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)) + pTrans->TransactionDetails[0] = cpu_to_le32((cur_naa << 16) | + (mac[0] << 8) | + (mac[1] << 0)); +@@ -818,6 +853,15 @@ + (mac[3] << 16) | + (mac[4] << 8) | + (mac[5] << 0)); ++#else ++ pTrans->TransactionDetails[0] = cpu_to_le32((cur_naa << 16) | ++ (skb->mac.raw[0] << 8) | ++ (skb->mac.raw[1] << 0)); ++ pTrans->TransactionDetails[1] = cpu_to_le32((skb->mac.raw[2] << 24) | ++ (skb->mac.raw[3] << 16) | ++ (skb->mac.raw[4] << 8) | ++ (skb->mac.raw[5] << 0)); ++#endif + + pSimple = (SGESimple64_t *) &pTrans->TransactionDetails[2]; + +@@ -856,7 +900,8 @@ + * @priority: 0 = put it on the timer queue, 1 = put it on the immediate queue + */ + { +- struct mpt_lan_priv *priv = dev->priv; ++ //struct mpt_lan_priv *priv = dev->priv; ++ struct mpt_lan_priv *priv = netdev_priv(dev); + + if (test_and_set_bit(0, &priv->post_buckets_active) == 0) { + if (priority) { +@@ -875,7 +920,8 @@ + static int + mpt_lan_receive_skb(struct net_device *dev, struct sk_buff *skb) + { +- struct mpt_lan_priv *priv = dev->priv; ++ //struct mpt_lan_priv *priv = dev->priv; ++ struct mpt_lan_priv *priv = netdev_priv(dev); + + skb->protocol = mpt_lan_type_trans(skb, dev); + +@@ -907,7 +953,8 @@ + static int + mpt_lan_receive_post_turbo(struct net_device *dev, u32 tmsg) + { +- struct mpt_lan_priv *priv = dev->priv; ++ //struct mpt_lan_priv *priv = dev->priv; ++ struct mpt_lan_priv *priv = netdev_priv(dev); + MPT_ADAPTER *mpt_dev = priv->mpt_dev; + struct sk_buff *skb, *old_skb; + unsigned long flags; +@@ -932,7 +979,11 @@ + pci_dma_sync_single_for_cpu(mpt_dev->pcidev, priv->RcvCtl[ctx].dma, + priv->RcvCtl[ctx].len, PCI_DMA_FROMDEVICE); + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)) + skb_copy_from_linear_data(old_skb, skb_put(skb, len), len); ++#else ++ memcpy(skb_put(skb, len), old_skb->data, len); ++#endif + + pci_dma_sync_single_for_device(mpt_dev->pcidev, priv->RcvCtl[ctx].dma, + priv->RcvCtl[ctx].len, PCI_DMA_FROMDEVICE); +@@ -962,7 +1013,8 @@ + mpt_lan_receive_post_free(struct net_device *dev, + LANReceivePostReply_t *pRecvRep) + { +- struct mpt_lan_priv *priv = dev->priv; ++ //struct mpt_lan_priv *priv = dev->priv; ++ struct mpt_lan_priv *priv = netdev_priv(dev); + MPT_ADAPTER *mpt_dev = priv->mpt_dev; + unsigned long flags; + struct sk_buff *skb; +@@ -1017,7 +1069,8 @@ + mpt_lan_receive_post_reply(struct net_device *dev, + LANReceivePostReply_t *pRecvRep) + { +- struct mpt_lan_priv *priv = dev->priv; ++ //struct mpt_lan_priv *priv = dev->priv; ++ struct mpt_lan_priv *priv = netdev_priv(dev); + MPT_ADAPTER *mpt_dev = priv->mpt_dev; + struct sk_buff *skb, *old_skb; + unsigned long flags; +@@ -1093,7 +1146,11 @@ + priv->RcvCtl[ctx].dma, + priv->RcvCtl[ctx].len, + PCI_DMA_FROMDEVICE); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)) + skb_copy_from_linear_data(old_skb, skb_put(skb, l), l); ++#else ++ memcpy(skb_put(skb, l), old_skb->data, l); ++#endif + + pci_dma_sync_single_for_device(mpt_dev->pcidev, + priv->RcvCtl[ctx].dma, +@@ -1122,7 +1179,11 @@ + priv->RcvCtl[ctx].len, + PCI_DMA_FROMDEVICE); + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)) + skb_copy_from_linear_data(old_skb, skb_put(skb, len), len); ++#else ++ memcpy(skb_put(skb, len), old_skb->data, len); ++#endif + pci_dma_sync_single_for_device(mpt_dev->pcidev, + priv->RcvCtl[ctx].dma, + priv->RcvCtl[ctx].len, +@@ -1193,9 +1254,17 @@ + /* Simple SGE's only at the moment */ + + static void ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + mpt_lan_post_receive_buckets(struct mpt_lan_priv *priv) + { + struct net_device *dev = priv->dev; ++#else ++mpt_lan_post_receive_buckets(void *dev_id) ++{ ++ struct net_device *dev = dev_id; ++ //struct mpt_lan_priv *priv = dev->priv; ++ struct mpt_lan_priv *priv = netdev_priv(dev); ++#endif + MPT_ADAPTER *mpt_dev = priv->mpt_dev; + MPT_FRAME_HDR *mf; + LANReceivePostRequest_t *pRecvReq; +@@ -1213,7 +1282,7 @@ + + dioprintk((KERN_INFO MYNAM ": %s/%s: @%s, Start_buckets = %u, buckets_out = %u\n", + IOC_AND_NETDEV_NAMES_s_s(dev), +- __func__, buckets, curr)); ++ __FUNCTION__, buckets, curr)); + + max = (mpt_dev->req_sz - MPT_LAN_RECEIVE_POST_REQUEST_SIZE) / + (MPT_LAN_TRANSACTION32_SIZE + sizeof(SGESimple64_t)); +@@ -1222,9 +1291,9 @@ + mf = mpt_get_msg_frame(LanCtx, mpt_dev); + if (mf == NULL) { + printk (KERN_ERR "%s: Unable to alloc request frame\n", +- __func__); ++ __FUNCTION__); + dioprintk((KERN_ERR "%s: %u buckets remaining\n", +- __func__, buckets)); ++ __FUNCTION__, buckets)); + goto out; + } + pRecvReq = (LANReceivePostRequest_t *) mf; +@@ -1249,7 +1318,7 @@ + spin_lock_irqsave(&priv->rxfidx_lock, flags); + if (priv->mpt_rxfidx_tail < 0) { + printk (KERN_ERR "%s: Can't alloc context\n", +- __func__); ++ __FUNCTION__); + spin_unlock_irqrestore(&priv->rxfidx_lock, + flags); + break; +@@ -1272,7 +1341,7 @@ + if (skb == NULL) { + printk (KERN_WARNING + MYNAM "/%s: Can't alloc skb\n", +- __func__); ++ __FUNCTION__); + priv->mpt_rxfidx[++priv->mpt_rxfidx_tail] = ctx; + spin_unlock_irqrestore(&priv->rxfidx_lock, flags); + break; +@@ -1310,7 +1379,7 @@ + + if (pSimple == NULL) { + /**/ printk (KERN_WARNING MYNAM "/%s: No buckets posted\n", +-/**/ __func__); ++/**/ __FUNCTION__); + mpt_free_msg_frame(mpt_dev, mf); + goto out; + } +@@ -1334,19 +1403,21 @@ + + out: + dioprintk((KERN_INFO MYNAM "/%s: End_buckets = %u, priv->buckets_out = %u\n", +- __func__, buckets, atomic_read(&priv->buckets_out))); ++ __FUNCTION__, buckets, atomic_read(&priv->buckets_out))); + dioprintk((KERN_INFO MYNAM "/%s: Posted %u buckets and received %u back\n", +- __func__, priv->total_posted, priv->total_received)); ++ __FUNCTION__, priv->total_posted, priv->total_received)); + + clear_bit(0, &priv->post_buckets_active); + } + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + static void + mpt_lan_post_receive_buckets_work(struct work_struct *work) + { + mpt_lan_post_receive_buckets(container_of(work, struct mpt_lan_priv, + post_buckets_task.work)); + } ++#endif + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + static struct net_device * +@@ -1363,13 +1434,20 @@ + + priv = netdev_priv(dev); + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + priv->dev = dev; ++#endif + priv->mpt_dev = mpt_dev; + priv->pnum = pnum; + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + memset(&priv->post_buckets_task, 0, sizeof(priv->post_buckets_task)); + INIT_DELAYED_WORK(&priv->post_buckets_task, + mpt_lan_post_receive_buckets_work); ++#else ++ memset(&priv->post_buckets_task, 0, sizeof(struct work_struct)); ++ INIT_WORK(&priv->post_buckets_task, mpt_lan_post_receive_buckets, dev); ++#endif + priv->post_buckets_active = 0; + + dlprintk((KERN_INFO MYNAM "@%d: bucketlen = %d\n", +@@ -1428,6 +1506,9 @@ + dlprintk((KERN_INFO MYNAM ": Finished registering dev " + "and setting initial values\n")); + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ SET_MODULE_OWNER(dev); ++#endif + + if (register_netdev(dev) != 0) { + free_netdev(dev); +@@ -1546,7 +1627,11 @@ + struct mpt_lan_ohdr *fch = (struct mpt_lan_ohdr *)skb->data; + struct fcllc *fcllc; + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)) + skb_reset_mac_header(skb); ++#else ++ skb->mac.raw = skb->data; ++#endif + skb_pull(skb, sizeof(struct mpt_lan_ohdr)); + + if (fch->dtype == htons(0xffff)) { +diff -r 8807687e8e9c drivers/message/fusion/mptlan.h +--- a/drivers/message/fusion/mptlan.h Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/mptlan.h Tue Sep 01 16:11:23 2009 +0100 +@@ -123,7 +123,7 @@ + #define dlprintk(x) + #endif + +-#define NETDEV_TO_LANPRIV_PTR(d) ((struct mpt_lan_priv *)(d)->priv) ++#define NETDEV_TO_LANPRIV_PTR(d) ((struct mpt_lan_priv *)netdev_priv(d)) + #define NETDEV_PTR_TO_IOC_NAME_s(d) (NETDEV_TO_LANPRIV_PTR(d)->mpt_dev->name) + #define IOC_AND_NETDEV_NAMES_s_s(d) NETDEV_PTR_TO_IOC_NAME_s(d), (d)->name + +diff -r 8807687e8e9c drivers/message/fusion/mptsas.c +--- a/drivers/message/fusion/mptsas.c Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/mptsas.c Tue Sep 01 16:11:23 2009 +0100 +@@ -42,7 +42,8 @@ + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +- ++#include "linux_compat.h" /* linux-2.6 tweaks */ ++#include + #include + #include + #include +@@ -60,8 +61,18 @@ + #include + #include + ++#include "linux_compat.h" /* linux-2.6 tweaks */ + #include "mptbase.h" + #include "mptscsih.h" ++ ++/* The glue to get a single driver working in both ++ * SLES10 and RHEL5 environments ++ */ ++#if (defined(CONFIG_SUSE_KERNEL) && defined(scsi_is_sas_phy_local)) || LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) ++#define MPT_WIDE_PORT_API 1 ++#define MPT_WIDE_PORT_API_PLUS 1 ++#endif ++ + #include "mptsas.h" + + #define my_NAME "Fusion MPT SAS Host driver" +@@ -71,7 +82,11 @@ + /* + * Reserved channel for integrated raid + */ ++#if defined(MPT_WIDE_PORT_API) + #define MPTSAS_RAID_CHANNEL 1 ++#else ++#define MPTSAS_RAID_CHANNEL 8 ++#endif + + #define SAS_CONFIG_PAGE_TIMEOUT 30 + +@@ -86,10 +101,10 @@ + " Clear persistency table: enable=1 " + "(default=MPTSCSIH_PT_CLEAR=0)"); + +-static int mpt_cmd_retry_count = 144; ++static int mpt_cmd_retry_count = 300; + module_param(mpt_cmd_retry_count, int, 0); + MODULE_PARM_DESC(mpt_cmd_retry_count, +- " Device discovery TUR command retry count: default=144"); ++ " Device discovery TUR command retry count: default=300"); + + static int mpt_disable_hotplug_remove = 0; + module_param(mpt_disable_hotplug_remove, int, 0); +@@ -117,27 +132,41 @@ + static u8 mptsasMgmtCtx = MPT_MAX_PROTOCOL_DRIVERS; + static u8 mptsasDeviceResetCtx = MPT_MAX_PROTOCOL_DRIVERS; + ++static void mptsas_send_sas_event(struct fw_event_work *fw_event); ++static void mptsas_send_raid_event(struct fw_event_work *fw_event); ++static void mptsas_send_ir2_event(struct fw_event_work *fw_event); ++static void mptsas_parse_device_info(struct sas_identify *identify, ++ struct mptsas_devinfo *device_info); + static inline void mptsas_set_rphy(MPT_ADAPTER *ioc, +- struct mptsas_phyinfo *phy_info, struct sas_rphy *rphy); +-static struct mptsas_phyinfo *mptsas_find_phyinfo_by_sas_address( +- MPT_ADAPTER *ioc, u64 sas_address); ++ struct mptsas_phyinfo *phy_info, struct sas_rphy *rphy); ++static struct mptsas_phyinfo *mptsas_find_phyinfo_by_sas_address ++ (MPT_ADAPTER *ioc, u64 sas_address); + static int mptsas_sas_device_pg0(MPT_ADAPTER *ioc, +- struct mptsas_devinfo *device_info, u32 form, u32 form_specific); ++ struct mptsas_devinfo *device_info, u32 form, u32 form_specific); + static int mptsas_sas_enclosure_pg0(MPT_ADAPTER *ioc, +- struct mptsas_enclosure *enclosure, u32 form, u32 form_specific); +- ++ struct mptsas_enclosure *enclosure, u32 form, u32 form_specific); + static int mptsas_add_end_device(MPT_ADAPTER *ioc, +- struct mptsas_phyinfo *phy_info); ++ struct mptsas_phyinfo *phy_info); + static void mptsas_del_end_device(MPT_ADAPTER *ioc, +- struct mptsas_phyinfo *phy_info); ++ struct mptsas_phyinfo *phy_info); ++static void mptsas_send_link_status_event(struct fw_event_work *fw_event); ++static struct mptsas_portinfo *mptsas_find_portinfo_by_sas_address ++ (MPT_ADAPTER *ioc, u64 sas_address); + static void mptsas_expander_delete(MPT_ADAPTER *ioc, +- struct mptsas_portinfo *port_info); +-static int mptsas_sas_expander_pg0(MPT_ADAPTER *ioc, +- struct mptsas_portinfo *port_info, u32 form, u32 form_specific); ++ struct mptsas_portinfo *port_info, u8 force); ++static void mptsas_send_expander_event(struct fw_event_work *fw_event); ++static void mptsas_not_responding_devices(MPT_ADAPTER *ioc); + static void mptsas_scan_sas_topology(MPT_ADAPTER *ioc); +-static void mptsas_not_responding_devices(MPT_ADAPTER *ioc); +- ++static void mptsas_broadcast_primative_work(struct fw_event_work *fw_event); ++static void mptsas_handle_queue_full_event(struct fw_event_work *fw_event); ++static void mptsas_volume_delete(MPT_ADAPTER *ioc, u8 id); ++ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + static void mptsas_firmware_event_work(struct work_struct *work); ++#else ++static void mptsas_firmware_event_work(void *arg); ++#endif + + /** + * mptsas_set_sdev_queue_depth - global setting of the mpt_sdev_queue_depth +@@ -152,7 +181,7 @@ + { + int ret = param_set_int(val, kp); + MPT_ADAPTER *ioc; +- struct scsi_device *sdev; ++ struct scsi_device *sdev; + + if (ret) + return ret; +@@ -297,6 +326,7 @@ + + spin_lock_irqsave(&ioc->fw_event_lock, flags); + ioc->fw_events_off = 1; ++ ioc->sas_discovery_quiesce_io = 0; + spin_unlock_irqrestore(&ioc->fw_event_lock, flags); + + } +@@ -325,11 +355,15 @@ + + spin_lock_irqsave(&ioc->fw_event_lock, flags); + list_add_tail(&fw_event->list, &ioc->fw_event_list); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + INIT_DELAYED_WORK(&fw_event->work, mptsas_firmware_event_work); +- devtprintk(ioc, printk(MYIOC_s_INFO_FMT "%s: add (fw_event=0x%p)\n", ++#else ++ INIT_WORK(&fw_event->work, mptsas_firmware_event_work, (void *)fw_event); ++#endif ++ devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: add (fw_event=0x%p)\n", + ioc->name, __func__, fw_event)); + queue_delayed_work(ioc->fw_event_q, &fw_event->work, +- msecs_to_jiffies(delay)); ++ delay); + spin_unlock_irqrestore(&ioc->fw_event_lock, flags); + } + +@@ -340,8 +374,8 @@ + { + unsigned long flags; + spin_lock_irqsave(&ioc->fw_event_lock, flags); +- devtprintk(ioc, printk(MYIOC_s_INFO_FMT "%s: reschedule task " +- "(fw_event=0x%p)\n", ioc->name, __func__, fw_event)); ++ devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: reschedule task " ++ "(fw_event=0x%p)\n", ioc->name,__FUNCTION__, fw_event)); + fw_event->retries++; + queue_delayed_work(ioc->fw_event_q, &fw_event->work, + msecs_to_jiffies(delay)); +@@ -355,7 +389,7 @@ + unsigned long flags; + + spin_lock_irqsave(&ioc->fw_event_lock, flags); +- devtprintk(ioc, printk(MYIOC_s_INFO_FMT "%s: kfree (fw_event=0x%p)\n", ++ devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: kfree (fw_event=0x%p)\n", + ioc->name, __func__, fw_event)); + list_del(&fw_event->list); + kfree(fw_event); +@@ -370,7 +404,7 @@ + struct fw_event_work *fw_event, *next; + struct mptsas_target_reset_event *target_reset_list, *n; + u8 flush_q; +- MPT_SCSI_HOST *hd = shost_priv(ioc->sh); ++ MPT_SCSI_HOST *hd = shost_private(ioc->sh); + + /* flush the target_reset_list */ + if (!list_empty(&hd->target_reset_list)) { +@@ -401,30 +435,37 @@ + } + + +-/** +- * phy_to_ioc - +- * @phy: +- * +- * +- **/ +-static inline MPT_ADAPTER * +-phy_to_ioc(struct sas_phy *phy) ++static inline MPT_ADAPTER *phy_to_ioc(struct sas_phy *phy) + { + struct Scsi_Host *shost = dev_to_shost(phy->dev.parent); + return ((MPT_SCSI_HOST *)shost->hostdata)->ioc; + } + +-/** +- * rphy_to_ioc - +- * @rphy: +- * +- * +- **/ +-static inline MPT_ADAPTER * +-rphy_to_ioc(struct sas_rphy *rphy) ++static inline MPT_ADAPTER *rphy_to_ioc(struct sas_rphy *rphy) + { + struct Scsi_Host *shost = dev_to_shost(rphy->dev.parent->parent); + return ((MPT_SCSI_HOST *)shost->hostdata)->ioc; ++} ++ ++/* ++ * mptsas_find_portinfo_by_handle ++ * ++ * This function should be called with the sas_topology_mutex already held ++ */ ++static struct mptsas_portinfo * ++mptsas_find_portinfo_by_handle(MPT_ADAPTER *ioc, u16 handle) ++{ ++ struct mptsas_portinfo *port_info, *rc=NULL; ++ int i; ++ ++ list_for_each_entry(port_info, &ioc->sas_topology, list) ++ for (i = 0; i < port_info->num_phys; i++) ++ if (port_info->phy_info[i].identify.handle == handle) { ++ rc = port_info; ++ goto out; ++ } ++ out: ++ return rc; + } + + /** +@@ -459,36 +500,9 @@ + return rc; + } + +-/** +- * mptsas_find_portinfo_by_handle - +- * @ioc: Pointer to MPT_ADAPTER structure +- * @handle: +- * +- * This function should be called with the sas_topology_mutex already held +- * +- **/ +-static struct mptsas_portinfo * +-mptsas_find_portinfo_by_handle(MPT_ADAPTER *ioc, u16 handle) +-{ +- struct mptsas_portinfo *port_info, *rc=NULL; +- int i; +- +- list_for_each_entry(port_info, &ioc->sas_topology, list) +- for (i = 0; i < port_info->num_phys; i++) +- if (port_info->phy_info[i].identify.handle == handle) { +- rc = port_info; +- goto out; +- } +- out: +- return rc; +-} +- +-/** +- * mptsas_is_end_device - +- * @attached: +- * +- * Returns true if there is a scsi end device +- **/ ++/* ++ * Returns true if there is a scsi end device ++ */ + static inline int + mptsas_is_end_device(struct mptsas_devinfo * attached) + { +@@ -527,10 +541,18 @@ + port_info = port_details->port_info; + phy_info = port_info->phy_info; + ++#if defined(MPT_WIDE_PORT_API) + dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: [%p]: num_phys=%02d " + "bitmask=0x%016llX\n", ioc->name, __func__, port_details, + port_details->num_phys, (unsigned long long) + port_details->phy_bitmask)); ++#else ++ dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: [%p]: port=%02d num_phys=%02d " ++ "rphy=%02d bitmask=0x%016llX\n", ioc->name, __FUNCTION__, port_details, ++ port_details->port_id, port_details->num_phys, ++ port_details->rphy_id, (unsigned long long) ++ port_details->phy_bitmask)); ++#endif + + for (i = 0; i < port_info->num_phys; i++, phy_info++) { + if(phy_info->port_details != port_details) +@@ -568,8 +590,8 @@ + { + if (phy_info->port_details) { + phy_info->port_details->rphy = rphy; +- dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "sas_rphy_add: rphy=%p\n", ioc->name, rphy)); ++ dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT "sas_rphy_add: rphy=%p\n", ++ ioc->name, rphy)); + } + + if (rphy) { +@@ -580,6 +602,23 @@ + } + } + ++#if !defined(MPT_WIDE_PORT_API) ++/** ++ * mptsas_get_rphy_id - ++ * @phy_info: ++ * ++ **/ ++static inline u8 ++mptsas_get_rphy_id(struct mptsas_phyinfo *phy_info) ++{ ++ if (phy_info->port_details) ++ return phy_info->port_details->rphy_id; ++ else ++ return 0xFF; ++} ++#endif ++ ++#if defined(MPT_WIDE_PORT_API) + /** + * mptsas_get_port - + * @phy_info: +@@ -614,6 +653,7 @@ + ioc->name, port, port->dev.release)); + } + } ++#endif + + /** + * mptsas_get_starget - +@@ -657,14 +697,14 @@ + u64 sas_address, u32 device_info, u16 slot, u64 enclosure_logical_id) + { + struct sas_device_info *sas_info, *next; +- struct scsi_device *sdev; ++ struct scsi_device *sdev; + struct scsi_target *starget; + struct sas_rphy *rphy; + + /* + * Delete all matching devices out of the list + */ +- mutex_lock(&ioc->sas_device_info_mutex); ++ down(&ioc->sas_device_info_mutex); + list_for_each_entry_safe(sas_info, next, &ioc->sas_device_info_list, + list) { + if (!sas_info->is_logical_volume && +@@ -676,7 +716,8 @@ + } + } + +- if (!(sas_info = kzalloc(sizeof(struct sas_device_info), GFP_KERNEL))) ++ sas_info = kzalloc(sizeof(struct sas_device_info), GFP_KERNEL); ++ if (!sas_info) + goto out; + + /* +@@ -705,7 +746,7 @@ + } + + out: +- mutex_unlock(&ioc->sas_device_info_mutex); ++ up(&ioc->sas_device_info_mutex); + return; + } + +@@ -750,8 +791,7 @@ + * + **/ + static void +-mptsas_add_device_component_starget_ir(MPT_ADAPTER *ioc, +- struct scsi_target *starget) ++mptsas_add_device_component_starget_ir(MPT_ADAPTER *ioc, struct scsi_target *starget) + { + CONFIGPARMS cfg; + ConfigPageHeader_t hdr; +@@ -765,7 +805,7 @@ + memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); + hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME; + /* assumption that all volumes on channel = 0 */ +- cfg.pageAddr = starget->id; ++ cfg.pageAddr = starget->id; + cfg.cfghdr.hdr = &hdr; + cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; + cfg.timeout = SAS_CONFIG_PAGE_TIMEOUT; +@@ -796,14 +836,14 @@ + */ + for (i = 0; i < buffer->NumPhysDisks; i++) { + +- if (mpt_raid_phys_disk_pg0(ioc, ++ if(mpt_raid_phys_disk_pg0(ioc, + buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0) + continue; + + mptsas_add_device_component_by_fw(ioc, phys_disk.PhysDiskBus, + phys_disk.PhysDiskID); + +- mutex_lock(&ioc->sas_device_info_mutex); ++ down(&ioc->sas_device_info_mutex); + list_for_each_entry(sas_info, &ioc->sas_device_info_list, + list) { + if (!sas_info->is_logical_volume && +@@ -813,13 +853,13 @@ + sas_info->volume_id = starget->id; + } + } +- mutex_unlock(&ioc->sas_device_info_mutex); ++ up(&ioc->sas_device_info_mutex); + } + + /* + * Delete all matching devices out of the list + */ +- mutex_lock(&ioc->sas_device_info_mutex); ++ down(&ioc->sas_device_info_mutex); + list_for_each_entry_safe(sas_info, next, &ioc->sas_device_info_list, + list) { + if (sas_info->is_logical_volume && sas_info->fw.id == +@@ -838,7 +878,7 @@ + INIT_LIST_HEAD(&sas_info->list); + list_add_tail(&sas_info->list, &ioc->sas_device_info_list); + } +- mutex_unlock(&ioc->sas_device_info_mutex); ++ up(&ioc->sas_device_info_mutex); + + out: + if (buffer) +@@ -854,30 +894,30 @@ + **/ + static void + mptsas_add_device_component_starget(MPT_ADAPTER *ioc, +- struct scsi_target *starget) +-{ +- VirtTarget *vtarget; +- struct sas_rphy *rphy; +- struct mptsas_phyinfo *phy_info = NULL; +- struct mptsas_enclosure enclosure_info; ++ struct scsi_target *starget) ++{ ++ VirtTarget *vtarget; ++ struct sas_rphy *rphy; ++ struct mptsas_phyinfo *phy_info = NULL; ++ struct mptsas_enclosure enclosure_info; + + rphy = dev_to_rphy(starget->dev.parent); + vtarget = starget->hostdata; + phy_info = mptsas_find_phyinfo_by_sas_address(ioc, +- rphy->identify.sas_address); ++ rphy->identify.sas_address); + if (!phy_info) + return; + + memset(&enclosure_info, 0, sizeof(struct mptsas_enclosure)); + mptsas_sas_enclosure_pg0(ioc, &enclosure_info, +- (MPI_SAS_ENCLOS_PGAD_FORM_HANDLE << +- MPI_SAS_ENCLOS_PGAD_FORM_SHIFT), +- phy_info->attached.handle_enclosure); ++ (MPI_SAS_ENCLOS_PGAD_FORM_HANDLE << ++ MPI_SAS_ENCLOS_PGAD_FORM_SHIFT), ++ phy_info->attached.handle_enclosure); + + mptsas_add_device_component(ioc, phy_info->attached.channel, +- phy_info->attached.id, phy_info->attached.sas_address, +- phy_info->attached.device_info, +- phy_info->attached.slot, enclosure_info.enclosure_logical_id); ++ phy_info->attached.id, phy_info->attached.sas_address, ++ phy_info->attached.device_info, ++ phy_info->attached.slot, enclosure_info.enclosure_logical_id); + } + + /** +@@ -913,29 +953,35 @@ + { + struct sas_device_info *sas_info, *next; + +- mutex_lock(&ioc->sas_device_info_mutex); ++ down(&ioc->sas_device_info_mutex); + list_for_each_entry_safe(sas_info, next, &ioc->sas_device_info_list, + list) { + list_del(&sas_info->list); + kfree(sas_info); + } +- mutex_unlock(&ioc->sas_device_info_mutex); +-} +- +-/** +- * mptsas_setup_wide_ports - Updates for new and existing narrow/wide port ++ up(&ioc->sas_device_info_mutex); ++} ++ ++ ++/* ++ * mptsas_setup_wide_ports + * configuration + * in the sas_topology + * @ioc: Pointer to MPT_ADAPTER structure + * @port_info: + * ++ * Updates for new and existing narrow/wide port configuration ++ * in the sas_topology + */ + static void + mptsas_setup_wide_ports(MPT_ADAPTER *ioc, struct mptsas_portinfo *port_info) + { +- struct mptsas_portinfo_details *port_details; ++ struct mptsas_portinfo_details * port_details; + struct mptsas_phyinfo *phy_info, *phy_info_cmp; + u64 sas_address; ++#if !defined(MPT_WIDE_PORT_API) ++ u8 found_wide_port; ++#endif + int i, j; + + mutex_lock(&ioc->sas_topology_mutex); +@@ -954,16 +1000,27 @@ + * Removing a phy from a port, letting the last + * phy be removed by firmware events. + */ ++#if defined(MPT_WIDE_PORT_API) + dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT + "%s: [%p]: deleting phy = %d\n", +- ioc->name, __func__, port_details, i)); ++ ioc->name, __FUNCTION__, port_details, i)); ++#else ++ dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "%s: [%p]: deleting phy = %d\n", ++ ioc->name, __func__, port_details, i)); ++#endif + port_details->num_phys--; +- port_details->phy_bitmask &= ~(1 << phy_info->phy_id); ++ port_details->phy_bitmask &= ~ (1 << phy_info->phy_id); + memset(&phy_info->attached, 0, sizeof(struct mptsas_devinfo)); +- devtprintk(ioc, dev_printk(KERN_DEBUG, &phy_info->phy->dev, +- MYIOC_s_FMT "delete phy %d, phy-obj (0x%p)\n", ioc->name, +- phy_info->phy_id, phy_info->phy)); ++#if defined(MPT_WIDE_PORT_API) ++ if (phy_info->phy) { ++ devtprintk(ioc, dev_printk(KERN_DEBUG, ++ &phy_info->phy->dev, MYIOC_s_FMT ++ "delete phy %d, phy-obj (0x%p)\n", ioc->name, ++ phy_info->phy_id, phy_info->phy)); + sas_port_delete_phy(port_details->port, phy_info->phy); ++ } ++#endif + phy_info->port_details = NULL; + } + +@@ -973,9 +1030,8 @@ + phy_info = port_info->phy_info; + for (i = 0 ; i < port_info->num_phys ; i++, phy_info++) { + sas_address = phy_info->attached.sas_address; +- dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "phy_id=%d sas_address=0x%018llX\n", +- ioc->name, i, (unsigned long long)sas_address)); ++ dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT "phy_id=%d sas_address=0x%018llX\n", ++ ioc->name, i, (unsigned long long)sas_address)); + if (!sas_address) + continue; + port_details = phy_info->port_details; +@@ -983,33 +1039,45 @@ + * Forming a port + */ + if (!port_details) { +- port_details = kzalloc(sizeof(struct mptsas_portinfo_details), +- GFP_KERNEL); ++ port_details = kzalloc(sizeof(struct ++ mptsas_portinfo_details), GFP_KERNEL); + if (!port_details) + goto out; + port_details->num_phys = 1; + port_details->port_info = port_info; +- if (phy_info->phy_id < 64) ++#if !defined(MPT_WIDE_PORT_API) ++ port_details->port_id = phy_info->port_id; ++ port_details->rphy_id = i; ++ port_details->device_info = phy_info->attached.device_info; ++#endif ++ if (phy_info->phy_id < 64 ) + port_details->phy_bitmask |= + (1 << phy_info->phy_id); +- phy_info->sas_port_add_phy = 1; +- dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "\t\tForming port\n\t\t" +- "phy_id=%d sas_address=0x%018llX\n", ioc->name, +- i, (unsigned long long) sas_address)); ++#if defined(MPT_WIDE_PORT_API) ++ phy_info->sas_port_add_phy=1; ++#endif ++ dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT "\t\tForming port\n\t\t" ++ "phy_id=%d sas_address=0x%018llX\n", ++ ioc->name, i, (unsigned long long)sas_address)); + phy_info->port_details = port_details; + } + + if (i == port_info->num_phys - 1) + continue; + phy_info_cmp = &port_info->phy_info[i + 1]; ++#if !defined(MPT_WIDE_PORT_API) ++ found_wide_port = 0; ++#endif + for (j = i + 1 ; j < port_info->num_phys ; j++, + phy_info_cmp++) { + if (!phy_info_cmp->attached.sas_address) + continue; + if (sas_address != phy_info_cmp->attached.sas_address) + continue; +- if (phy_info_cmp->port_details == port_details) ++#if !defined(MPT_WIDE_PORT_API) ++ found_wide_port = 1; ++#endif ++ if (phy_info_cmp->port_details == port_details ) + continue; + dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT + "\t\tphy_id=%d sas_address=0x%018llX\n", +@@ -1018,25 +1086,43 @@ + if (phy_info_cmp->port_details) { + port_details->rphy = + mptsas_get_rphy(phy_info_cmp); ++#if defined(MPT_WIDE_PORT_API) + port_details->port = + mptsas_get_port(phy_info_cmp); ++#endif + port_details->starget = + mptsas_get_starget(phy_info_cmp); ++#if !defined(MPT_WIDE_PORT_API) ++ port_details->port_id = ++ phy_info_cmp->port_details->port_id; ++ port_details->rphy_id = ++ phy_info_cmp->port_details->rphy_id; ++#endif + port_details->num_phys = + phy_info_cmp->port_details->num_phys; + if (!phy_info_cmp->port_details->num_phys) + kfree(phy_info_cmp->port_details); ++#if defined(MPT_WIDE_PORT_API) + } else +- phy_info_cmp->sas_port_add_phy = 1; ++ phy_info_cmp->sas_port_add_phy=1; ++#else ++ } ++#endif + /* + * Adding a phy to a port + */ + phy_info_cmp->port_details = port_details; +- if (phy_info_cmp->phy_id < 64) ++ if (phy_info_cmp->phy_id < 64 ) + port_details->phy_bitmask |= + (1 << phy_info_cmp->phy_id); + port_details->num_phys++; +- } ++#if !defined(MPT_WIDE_PORT_API) ++ phy_info_cmp->attached.wide_port_enable = 1; ++#endif ++ } ++#if !defined(MPT_WIDE_PORT_API) ++ phy_info->attached.wide_port_enable = (found_wide_port) ? 1:0; ++#endif + } + + out: +@@ -1045,14 +1131,25 @@ + port_details = port_info->phy_info[i].port_details; + if (!port_details) + continue; ++#if defined(MPT_WIDE_PORT_API) + dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT + "%s: [%p]: phy_id=%02d num_phys=%02d " + "bitmask=0x%016llX\n", ioc->name, __func__, + port_details, i, port_details->num_phys, + (unsigned long long)port_details->phy_bitmask)); ++ dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT "\t\tport = %p rphy=%p\n", ++ ioc->name, port_details->port, port_details->rphy)); ++#else + dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "\t\tport = %p rphy=%p\n", +- ioc->name, port_details->port, port_details->rphy)); ++ "%s: [%p]: phy=%02d port=%02d num_phys=%02d " ++ "rphy=%02d bitmask=0x%016llX\n", ++ ioc->name, __FUNCTION__, ++ port_details, i, port_details->port_id, ++ port_details->num_phys, port_details->rphy_id, ++ (unsigned long long)port_details->phy_bitmask)); ++ dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "\t\trphy=%p\n", ioc->name, port_details->rphy)); ++#endif + } + dsaswideprintk(ioc, printk("\n")); + mutex_unlock(&ioc->sas_topology_mutex); +@@ -1073,7 +1170,8 @@ + VirtTarget *vtarget = NULL; + + shost_for_each_device(sdev, ioc->sh) { +- if ((vdevice = sdev->hostdata) == NULL || ++ vdevice = sdev->hostdata; ++ if ((vdevice == NULL) || + (vdevice->vtarget == NULL)) + continue; + if ((vdevice->vtarget->tflags & +@@ -1081,7 +1179,7 @@ + vdevice->vtarget->raidVolume)) + continue; + if (vdevice->vtarget->id == id && +- vdevice->vtarget->channel == channel) ++ vdevice->vtarget->channel == channel) + vtarget = vdevice->vtarget; + } + return vtarget; +@@ -1089,7 +1187,7 @@ + + static void + mptsas_queue_device_delete(MPT_ADAPTER *ioc, +- MpiEventDataSasDeviceStatusChange_t *sas_event_data) ++ MpiEventDataSasDeviceStatusChange_t *sas_event_data) + { + struct fw_event_work *fw_event; + int sz; +@@ -1148,10 +1246,12 @@ + if (mpt_set_taskmgmt_in_progress_flag(ioc) != 0) + return 0; + +- if ((mf = mpt_get_msg_frame(mptsasDeviceResetCtx, ioc)) == NULL) { ++ ++ mf = mpt_get_msg_frame(mptsasDeviceResetCtx, ioc); ++ if (mf == NULL) { + dfailprintk(ioc, printk(MYIOC_s_WARN_FMT +- "%s, no msg frames @%d!!\n", +- ioc->name, __func__, __LINE__)); ++ "%s, no msg frames @%d!!\n", ioc->name, ++ __func__, __LINE__)); + goto out_fail; + } + +@@ -1161,7 +1261,7 @@ + /* Format the Request + */ + pScsiTm = (SCSITaskMgmt_t *) mf; +- memset(pScsiTm, 0, sizeof(SCSITaskMgmt_t)); ++ memset (pScsiTm, 0, sizeof(SCSITaskMgmt_t)); + pScsiTm->TargetID = id; + pScsiTm->Bus = channel; + pScsiTm->Function = MPI_FUNCTION_SCSI_TASK_MGMT; +@@ -1183,6 +1283,20 @@ + mpt_clear_taskmgmt_in_progress_flag(ioc); + return 0; + } ++ ++static void ++mptsas_block_io_sdev(struct scsi_device *sdev, void *data) ++{ ++ scsi_device_set_state(sdev, SDEV_BLOCK); ++} ++ ++static void ++mptsas_block_io_starget(struct scsi_target *starget) ++{ ++ if (starget) ++ starget_for_each_device(starget, NULL, mptsas_block_io_sdev); ++} ++ + /** + * mptsas_target_reset_queue - + * @ioc: Pointer to MPT_ADAPTER structure +@@ -1196,17 +1310,19 @@ + mptsas_target_reset_queue(MPT_ADAPTER *ioc, + EVENT_DATA_SAS_DEVICE_STATUS_CHANGE *sas_event_data) + { +- MPT_SCSI_HOST *hd = shost_priv(ioc->sh); ++ MPT_SCSI_HOST *hd = shost_private(ioc->sh); + VirtTarget *vtarget = NULL; +- struct mptsas_target_reset_event *target_reset_list; ++ struct mptsas_target_reset_event *target_reset_list; + u8 id, channel; + + id = sas_event_data->TargetID; + channel = sas_event_data->Bus; + + if ((vtarget = mptsas_find_vtarget(ioc, channel, id))) { +- if (!ioc->disable_hotplug_remove) ++ if (!ioc->disable_hotplug_remove) { ++ mptsas_block_io_starget(vtarget->starget); + vtarget->deleted = 1; /* block IO */ ++ } + } + + target_reset_list = kzalloc(sizeof(struct mptsas_target_reset_event), +@@ -1224,8 +1340,9 @@ + + target_reset_list->time_count = jiffies; + +- if (mptsas_target_reset(ioc, channel, id)) ++ if (mptsas_target_reset(ioc, channel, id)) { + target_reset_list->target_reset_issued = 1; ++ } + } + + /** +@@ -1238,8 +1355,8 @@ + static int + mptsas_taskmgmt_complete(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf, MPT_FRAME_HDR *mr) + { +- MPT_SCSI_HOST *hd = shost_priv(ioc->sh); +- struct list_head *head = &hd->target_reset_list; ++ MPT_SCSI_HOST *hd = shost_private(ioc->sh); ++ struct list_head *head = &hd->target_reset_list; + struct mptsas_target_reset_event *target_reset_list; + u8 id, channel; + SCSITaskMgmtReply_t *pScsiTmReply; +@@ -1313,7 +1430,7 @@ + list_del(&target_reset_list->list); + if ((mptsas_find_vtarget(ioc, channel, id)) && !ioc->fw_events_off) + mptsas_queue_device_delete(ioc, +- &target_reset_list->sas_event_data); ++ &target_reset_list->sas_event_data); + + + /* +@@ -1324,8 +1441,8 @@ + if (list_empty(head)) + return 1; + +- target_reset_list = list_entry(head->next, +- struct mptsas_target_reset_event, list); ++ target_reset_list = list_entry(head->next, struct mptsas_target_reset_event, ++ list); + + id = target_reset_list->sas_event_data.TargetID; + channel = target_reset_list->sas_event_data.Bus; +@@ -1346,14 +1463,14 @@ + static int + mptsas_ioc_reset(MPT_ADAPTER *ioc, int reset_phase) + { +- MPT_SCSI_HOST *hd; ++ MPT_SCSI_HOST *hd; + int rc; + + rc = mptscsih_ioc_reset(ioc, reset_phase); + if ((ioc->bus_type != SAS) || (!rc)) + return rc; + +- hd = shost_priv(ioc->sh); ++ hd = shost_private(ioc->sh); + if (!hd->ioc) + goto out; + +@@ -1385,6 +1502,20 @@ + out: + return rc; + } ++ ++/** ++ * enum device_state - ++ * @DEVICE_RETRY: need to retry the TUR ++ * @DEVICE_ERROR: TUR return error, don't add device ++ * @DEVICE_READY: device can be added ++ * ++ */ ++enum device_state{ ++ DEVICE_RETRY, ++ DEVICE_ERROR, ++ DEVICE_READY, ++}; ++ + + /** + * mptsas_sas_enclosure_pg0 - +@@ -1460,6 +1591,304 @@ + } + + /** ++ * mptsas_add_end_device - report a new end device to sas transport layer ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * @phy_info: decribes attached device ++ * ++ * return (0) success (1) failure ++ * ++ **/ ++static int ++mptsas_add_end_device(MPT_ADAPTER *ioc, struct mptsas_phyinfo *phy_info) ++{ ++ struct sas_rphy *rphy; ++#if defined(MPT_WIDE_PORT_API) ++ struct sas_port *port; ++#endif ++ struct sas_identify identify; ++ char *ds = NULL; ++ u8 fw_id; ++ ++ if (!phy_info) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: exit at line=%d\n", ioc->name, ++ __func__, __LINE__)); ++ return 1; ++ } ++ ++ fw_id = phy_info->attached.id; ++ ++ if (mptsas_get_rphy(phy_info)) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, fw_id, __LINE__)); ++ return 2; ++ } ++ ++#if defined(MPT_WIDE_PORT_API) ++ port = mptsas_get_port(phy_info); ++ if (!port) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, fw_id, __LINE__)); ++ return 3; ++ } ++#endif ++ ++ if (phy_info->attached.device_info & ++ MPI_SAS_DEVICE_INFO_SSP_TARGET) ++ ds = "ssp"; ++ if (phy_info->attached.device_info & ++ MPI_SAS_DEVICE_INFO_STP_TARGET) ++ ds = "stp"; ++ if (phy_info->attached.device_info & ++ MPI_SAS_DEVICE_INFO_SATA_DEVICE) ++ ds = "sata"; ++ ++ printk(MYIOC_s_INFO_FMT "attaching %s device: fw_channel %d, fw_id %d," ++ " phy %d, sas_addr 0x%llx\n", ioc->name, ds, ++ phy_info->attached.channel, phy_info->attached.id, ++ phy_info->attached.phy_id, (unsigned long long) ++ phy_info->attached.sas_address); ++ ++ mptsas_parse_device_info(&identify, &phy_info->attached); ++#if defined(MPT_WIDE_PORT_API) ++ rphy = sas_end_device_alloc(port); ++#else ++ rphy = sas_end_device_alloc(phy_info->phy); ++#endif ++ if (!rphy) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, fw_id, __LINE__)); ++ return 5; /* non-fatal: an rphy can be added later */ ++ } ++ ++ rphy->identify = identify; ++ if (sas_rphy_add(rphy)) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, fw_id, __LINE__)); ++ sas_rphy_free(rphy); ++ return 6; ++ } ++ mptsas_set_rphy(ioc, phy_info, rphy); ++ return 0; ++} ++ ++/** ++ * mptsas_del_end_device - report a deleted end device to sas transport ++ * layer ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * @phy_info: decribes attached device ++ * ++ **/ ++static void ++mptsas_del_end_device(MPT_ADAPTER *ioc, struct mptsas_phyinfo *phy_info) ++{ ++ struct sas_rphy *rphy; ++#if defined(MPT_WIDE_PORT_API) ++ struct sas_port *port; ++ struct mptsas_portinfo *port_info; ++ struct mptsas_phyinfo *phy_info_parent; ++ int i; ++#endif ++ char *ds = NULL; ++ u8 fw_id; ++ u64 sas_address; ++ ++ if (!phy_info) ++ return; ++ ++ fw_id = phy_info->attached.id; ++ sas_address = phy_info->attached.sas_address; ++ ++ if (!phy_info->port_details) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, fw_id, __LINE__)); ++ return; ++ } ++ rphy = mptsas_get_rphy(phy_info); ++ if (!rphy) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, fw_id, __LINE__)); ++ return; ++ } ++ ++ if (phy_info->attached.device_info & MPI_SAS_DEVICE_INFO_SSP_INITIATOR ++ || phy_info->attached.device_info ++ & MPI_SAS_DEVICE_INFO_SMP_INITIATOR ++ || phy_info->attached.device_info ++ & MPI_SAS_DEVICE_INFO_STP_INITIATOR) ++ ds = "initiator"; ++ if (phy_info->attached.device_info & ++ MPI_SAS_DEVICE_INFO_SSP_TARGET) ++ ds = "ssp"; ++ if (phy_info->attached.device_info & ++ MPI_SAS_DEVICE_INFO_STP_TARGET) ++ ds = "stp"; ++ if (phy_info->attached.device_info & ++ MPI_SAS_DEVICE_INFO_SATA_DEVICE) ++ ds = "sata"; ++ ++ dev_printk(KERN_DEBUG, &rphy->dev, MYIOC_s_FMT ++ "removing %s device: fw_channel %d, fw_id %d, phy %d," ++ "sas_addr 0x%llx\n", ioc->name, ds, phy_info->attached.channel, ++ phy_info->attached.id, phy_info->attached.phy_id, ++ (unsigned long long) sas_address); ++ ++#if defined(MPT_WIDE_PORT_API) ++ port = mptsas_get_port(phy_info); ++ if (!port) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, fw_id, __LINE__)); ++ return; ++ } ++ port_info = phy_info->portinfo; ++ phy_info_parent = port_info->phy_info; ++ for (i = 0; i < port_info->num_phys; i++, phy_info_parent++) { ++ if (!phy_info_parent->phy) ++ continue; ++ if (phy_info_parent->attached.sas_address != ++ sas_address) ++ continue; ++ dev_printk(KERN_DEBUG, &phy_info_parent->phy->dev, ++ MYIOC_s_FMT "delete phy %d, phy-obj (0x%p)\n", ++ ioc->name, phy_info_parent->phy_id, ++ phy_info_parent->phy); ++ sas_port_delete_phy(port, phy_info_parent->phy); ++ } ++ ++ dev_printk(KERN_DEBUG, &port->dev, MYIOC_s_FMT ++ "delete port %d, sas_addr (0x%llx)\n", ioc->name, ++ port->port_identifier, (unsigned long long)sas_address); ++ sas_port_delete(port); ++ mptsas_set_port(ioc, phy_info, NULL); ++#else ++ sas_rphy_delete(rphy); ++ mptsas_set_rphy(ioc, phy_info, NULL); ++#endif ++ mptsas_port_delete(ioc, phy_info->port_details); ++} ++ ++struct mptsas_phyinfo * ++mptsas_refreshing_device_handles(MPT_ADAPTER *ioc, ++ struct mptsas_devinfo *sas_device) ++{ ++ struct mptsas_phyinfo *phy_info; ++ struct mptsas_portinfo *port_info; ++ int i; ++ ++ phy_info = mptsas_find_phyinfo_by_sas_address(ioc, ++ sas_device->sas_address); ++ if (!phy_info) ++ goto out; ++ port_info = phy_info->portinfo; ++ if (!port_info) ++ goto out; ++ mutex_lock(&ioc->sas_topology_mutex); ++ for (i = 0; i < port_info->num_phys; i++) { ++ if (port_info->phy_info[i].attached.sas_address != ++ sas_device->sas_address) ++ continue; ++ port_info->phy_info[i].attached.channel = sas_device->channel; ++ port_info->phy_info[i].attached.id = sas_device->id; ++ port_info->phy_info[i].attached.sas_address = ++ sas_device->sas_address; ++ port_info->phy_info[i].attached.handle = sas_device->handle; ++ port_info->phy_info[i].attached.handle_parent = ++ sas_device->handle_parent; ++ port_info->phy_info[i].attached.handle_enclosure = ++ sas_device->handle_enclosure; ++ } ++ mutex_unlock(&ioc->sas_topology_mutex); ++ out: ++ return phy_info; ++} ++ ++/** ++ * mptsas_firmware_event_work - work thread for processing fw events ++ * @work: work queue payload containing info describing the event ++ * Context: user ++ * ++ */ ++static void ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) ++mptsas_firmware_event_work(struct work_struct *work) ++{ ++ struct fw_event_work *fw_event = ++ container_of(work, struct fw_event_work, work.work); ++#else ++mptsas_firmware_event_work(void *arg) ++{ ++ struct fw_event_work *fw_event = (struct fw_event_work *)arg; ++#endif ++ MPT_ADAPTER *ioc = fw_event->ioc; ++ ++ /* special rescan topology handling */ ++ if (fw_event->event == -1) { ++ if (ioc->in_rescan) { ++ devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "%s: rescan ignored as it is in progress\n", ++ ioc->name, __func__)); ++ return; ++ } ++ devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: rescan after " ++ "reset\n", ioc->name, __func__)); ++ ioc->in_rescan = 1; ++ mptsas_not_responding_devices(ioc); ++ mptsas_scan_sas_topology(ioc); ++ ioc->in_rescan = 0; ++ mptsas_free_fw_event(ioc, fw_event); ++ return; ++ } ++ ++ /* events handling turned off during host reset */ ++ if (ioc->fw_events_off) { ++ mptsas_free_fw_event(ioc, fw_event); ++ return; ++ } ++ ++ devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: fw_event=(0x%p), " ++ "event = (0x%02x)\n", ioc->name, __func__, fw_event, ++ (fw_event->event & 0xFF))); ++ ++ switch (fw_event->event) { ++ case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE: ++ mptsas_send_sas_event(fw_event); ++ break; ++ case MPI_EVENT_INTEGRATED_RAID: ++ mptsas_send_raid_event(fw_event); ++ break; ++ case MPI_EVENT_IR2: ++ mptsas_send_ir2_event(fw_event); ++ break; ++ case MPI_EVENT_PERSISTENT_TABLE_FULL: ++ mptbase_sas_persist_operation(ioc, ++ MPI_SAS_OP_CLEAR_NOT_PRESENT); ++ mptsas_free_fw_event(ioc, fw_event); ++ break; ++ case MPI_EVENT_SAS_BROADCAST_PRIMITIVE: ++ mptsas_broadcast_primative_work(fw_event); ++ break; ++ case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE: ++ mptsas_send_expander_event(fw_event); ++ break; ++ case MPI_EVENT_SAS_PHY_LINK_STATUS: ++ mptsas_send_link_status_event(fw_event); ++ break; ++ case MPI_EVENT_QUEUE_FULL: ++ mptsas_handle_queue_full_event(fw_event); ++ break; ++ } ++} ++ ++ ++ ++/** + * mptsas_get_lun_number - returns the first entry in report_luns table + * @ioc: Pointer to MPT_ADAPTER structure + * @channel: +@@ -1480,13 +1909,13 @@ + u32 length, num_luns; + + iocmd = NULL; +- hd = shost_priv(ioc->sh); ++ hd = shost_private(ioc->sh); + lun_data_len = (255 * sizeof(struct scsi_lun)); + lun_data = pci_alloc_consistent(ioc->pcidev, lun_data_len, + &lun_data_dma); + if (!lun_data) { + printk(MYIOC_s_ERR_FMT "%s: pci_alloc_consistent(%d) FAILED!\n", +- ioc->name, __func__, lun_data_len); ++ ioc->name, __FUNCTION__, lun_data_len); + rc = -ENOMEM; + goto out; + } +@@ -1494,7 +1923,7 @@ + iocmd = kzalloc(sizeof(INTERNAL_CMD), GFP_KERNEL); + if (!iocmd) { + printk(MYIOC_s_ERR_FMT "%s: kzalloc(%zd) FAILED!\n", +- ioc->name, __func__, sizeof(INTERNAL_CMD)); ++ ioc->name, __FUNCTION__, sizeof(INTERNAL_CMD)); + rc = -ENOMEM; + goto out; + } +@@ -1512,14 +1941,14 @@ + if ((rc = mptscsih_do_cmd(hd, iocmd)) < 0) { + printk(MYIOC_s_ERR_FMT "%s: fw_channel=%d fw_id=%d: " + "report_luns failed due to rc=0x%x\n", ioc->name, +- __func__, channel, id, rc); ++ __FUNCTION__, channel, id, rc); + goto out; + } + + if (rc != MPT_SCANDV_GOOD) { + printk(MYIOC_s_ERR_FMT "%s: fw_channel=%d fw_id=%d: " + "report_luns failed due to rc=0x%x\n", ioc->name, +- __func__, channel, id, rc); ++ __FUNCTION__, channel, id, rc); + rc = -rc; + goto out; + } +@@ -1532,7 +1961,7 @@ + if (!num_luns) + goto out; + /* return 1st lun in the list */ +- *lun = scsilun_to_int(&lun_data[1]); ++ *lun = mpt_scsilun_to_int(&lun_data[1]); + + #if 0 + /* some debugging, left commented out */ +@@ -1552,19 +1981,6 @@ + } + + /** +- * enum device_state - +- * @DEVICE_RETRY: need to retry the TUR +- * @DEVICE_ERROR: TUR return error, don't add device +- * @DEVICE_READY: device can be added +- * +- */ +-enum device_state{ +- DEVICE_RETRY, +- DEVICE_ERROR, +- DEVICE_READY, +-}; +- +-/** + * mptsas_test_unit_ready - + * @ioc: Pointer to MPT_ADAPTER structure + * @channel: +@@ -1576,18 +1992,20 @@ + mptsas_test_unit_ready(MPT_ADAPTER *ioc, u8 channel, u8 id, u16 count) + { + INTERNAL_CMD *iocmd; +- MPT_SCSI_HOST *hd = shost_priv(ioc->sh); ++ MPT_SCSI_HOST *hd = shost_private(ioc->sh); + enum device_state state; + int rc; + u8 skey, asc, ascq; ++ u8 retry_ua; + + if (count >= mpt_cmd_retry_count) + return DEVICE_ERROR; + ++ retry_ua = 0; + iocmd = kzalloc(sizeof(INTERNAL_CMD), GFP_KERNEL); + if (!iocmd) { + printk(MYIOC_s_ERR_FMT "%s: kzalloc(%zd) FAILED!\n", +- __func__, ioc->name, sizeof(INTERNAL_CMD)); ++ __FUNCTION__, ioc->name, sizeof(INTERNAL_CMD)); + return DEVICE_ERROR; + } + +@@ -1606,31 +2024,31 @@ + + retry: + devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: fw_channel=%d " +- "fw_id=%d retry=%d\n", ioc->name, __func__, channel, id, count)); ++ "fw_id=%d retry=%d\n", ioc->name, __FUNCTION__, channel, id, count)); + rc = mptscsih_do_cmd(hd, iocmd); + devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: rc=0x%02x\n", +- ioc->name, __func__, rc)); ++ ioc->name, __FUNCTION__, rc)); + if (rc < 0) { + printk(MYIOC_s_ERR_FMT "%s: fw_channel=%d fw_id=%d: " + "tur failed due to timeout\n", ioc->name, +- __func__, channel, id); +- goto tur_done; +- } +- +- switch (rc) { ++ __FUNCTION__, channel, id); ++ goto tur_done; ++ } ++ ++ switch(rc) { + case MPT_SCANDV_GOOD: + state = DEVICE_READY; + goto tur_done; + case MPT_SCANDV_BUSY: + devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: " + "fw_channel=%d fw_id=%d : device busy\n", +- ioc->name, __func__, channel, id)); ++ ioc->name, __FUNCTION__, channel, id)); + state = DEVICE_RETRY; + break; + case MPT_SCANDV_DID_RESET: + devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: " + "fw_channel=%d fw_id=%d : did reset\n", +- ioc->name, __func__, channel, id)); ++ ioc->name, __FUNCTION__, channel, id)); + state = DEVICE_RETRY; + break; + case MPT_SCANDV_SENSE: +@@ -1641,7 +2059,7 @@ + devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: " + "fw_channel=%d fw_id=%d : [sense_key,asc," + "ascq]: [0x%02x,0x%02x,0x%02x]\n", ioc->name, +- __func__, channel, id, skey, asc, ascq)); ++ __FUNCTION__, channel, id, skey, asc, ascq)); + + if (skey == UNIT_ATTENTION) { + state = DEVICE_RETRY; +@@ -1665,7 +2083,7 @@ + break; + } + } else if (skey == ILLEGAL_REQUEST) { +- /* try sending a tur to a non-zero lun number */ ++ /* try sending a tur to a non-zero lun number */ + if (!iocmd->lun && !mptsas_get_lun_number(ioc, + channel, id, &iocmd->lun) && iocmd->lun) + goto retry; +@@ -1673,25 +2091,25 @@ + printk(MYIOC_s_ERR_FMT "%s: fw_channel=%d fw_id=%d : " + "tur failed due to [sense_key,asc,ascq]: " + "[0x%02x,0x%02x,0x%02x]\n", ioc->name, +- __func__, channel, id, skey, asc, ascq); ++ __FUNCTION__, channel, id, skey, asc, ascq); + goto tur_done; + case MPT_SCANDV_SELECTION_TIMEOUT: + printk(MYIOC_s_ERR_FMT "%s: fw_channel=%d fw_id=%d: " + "tur failed due to no device\n", ioc->name, +- __func__, channel, ++ __FUNCTION__, channel, + id); + goto tur_done; + case MPT_SCANDV_SOME_ERROR: + printk(MYIOC_s_ERR_FMT "%s: fw_channel=%d fw_id=%d: " + "tur failed due to some error\n", ioc->name, +- __func__, ++ __FUNCTION__, + channel, id); + goto tur_done; + default: + printk(MYIOC_s_ERR_FMT + "%s: fw_channel=%d fw_id=%d: tur failed due to " +- "unknown rc=0x%02x\n", ioc->name, __func__, +- channel, id, rc); ++ "unknown rc=0x%02x\n", ioc->name, __FUNCTION__, ++ channel, id, rc ); + goto tur_done; + } + tur_done: +@@ -1714,19 +2132,19 @@ + u8 rc; + MPT_ADAPTER *ioc = hd->ioc; + +- if (sdev->inquiry[8] == 'H' && ++ if ( sdev->inquiry[8] == 'H' && + sdev->inquiry[9] == 'P' && + sdev->inquiry[10] == ' ' && + sdev->inquiry[11] == ' ' && + sdev->inquiry[12] == ' ' && + sdev->inquiry[13] == ' ' && + sdev->inquiry[14] == ' ' && +- sdev->inquiry[15] == ' ') { ++ sdev->inquiry[15] == ' ' ) { + + iocmd = kzalloc(sizeof(INTERNAL_CMD), GFP_KERNEL); + if (!iocmd) { + printk(MYIOC_s_ERR_FMT "%s: kzalloc(%zd) FAILED!\n", +- __func__, ioc->name, sizeof(INTERNAL_CMD)); ++ __FUNCTION__, ioc->name, sizeof(INTERNAL_CMD)); + return; + } + iocmd->id = vdevice->vtarget->id; +@@ -1758,10 +2176,11 @@ + mptsas_slave_configure(struct scsi_device *sdev) + { + struct Scsi_Host *host = sdev->host; +- MPT_SCSI_HOST *hd = shost_priv(host); +- MPT_ADAPTER *ioc = hd->ioc; ++ MPT_SCSI_HOST *hd = shost_private(host); ++ MPT_ADAPTER *ioc = hd->ioc; ++ + VirtDevice *vdevice = sdev->hostdata; +- ++ + + if (vdevice->vtarget->deleted) { + sdev_printk(KERN_INFO, sdev, "clearing deleted flag\n"); +@@ -1782,7 +2201,7 @@ + mptsas_add_device_component_starget(ioc, scsi_target(sdev)); + + if (sdev->type == TYPE_TAPE && +- (ioc->facts.IOCCapabilities & MPI_IOCFACTS_CAPABILITY_TLR)) ++ (ioc->facts.IOCCapabilities & MPI_IOCFACTS_CAPABILITY_TLR )) + mptsas_issue_tlr(hd, sdev); + out: + +@@ -1798,7 +2217,7 @@ + mptsas_target_alloc(struct scsi_target *starget) + { + struct Scsi_Host *host = dev_to_shost(&starget->dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++ MPT_SCSI_HOST *hd = shost_private(host); + VirtTarget *vtarget; + u8 id, channel; + struct sas_rphy *rphy; +@@ -1824,7 +2243,7 @@ + kfree(vtarget); + return -ENXIO; + } +- for (i = 0; i < ioc->raid_data.pIocPg2->NumActiveVolumes; i++) ++ for (i=0; i < ioc->raid_data.pIocPg2->NumActiveVolumes; i++) + if (id == ioc->raid_data.pIocPg2->RaidVolume[i].VolumeID) + channel = ioc->raid_data.pIocPg2->RaidVolume[i].VolumeBus; + vtarget->raidVolume = 1; +@@ -1836,18 +2255,16 @@ + list_for_each_entry(p, &ioc->sas_topology, list) { + for (i = 0; i < p->num_phys; i++) { + if (p->phy_info[i].attached.sas_address != +- rphy->identify.sas_address) ++ rphy->identify.sas_address) + continue; + id = p->phy_info[i].attached.id; + channel = p->phy_info[i].attached.channel; + mptsas_set_starget(&p->phy_info[i], starget); + + starget_printk(KERN_INFO, starget, MYIOC_s_FMT +- "add device: fw_channel %d, fw_id %d, phy %d," +- " sas_addr 0x%llx\n", ++ "add device: fw_channel %d, fw_id %d, phy %d, sas_addr 0x%llx\n", + ioc->name, p->phy_info[i].attached.channel, +- p->phy_info[i].attached.id, +- p->phy_info[i].attached.phy_id, ++ p->phy_info[i].attached.id, p->phy_info[i].attached.phy_id, + (unsigned long long)p->phy_info[i].attached.sas_address); + + /* +@@ -1855,7 +2272,7 @@ + */ + if (mptscsih_is_phys_disk(ioc, channel, id)) { + id = mptscsih_raid_id_to_num(ioc, +- channel, id); ++ channel, id); + vtarget->tflags |= + MPT_TARGET_FLAGS_RAID_COMPONENT; + p->phy_info[i].attached.phys_disk_num = id; +@@ -1885,14 +2302,17 @@ + mptsas_target_destroy(struct scsi_target *starget) + { + struct Scsi_Host *host = dev_to_shost(&starget->dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++ MPT_SCSI_HOST *hd = shost_private(host); + struct sas_rphy *rphy; + struct mptsas_portinfo *p; + int i; +- MPT_ADAPTER *ioc = hd->ioc; ++ MPT_ADAPTER *ioc = hd->ioc; ++ VirtTarget *vtarget; + + if (!starget->hostdata) + return; ++ ++ vtarget = starget->hostdata; + + mptsas_del_device_component_by_os(ioc, starget->channel, + starget->id); +@@ -1915,11 +2335,12 @@ + p->phy_info[i].attached.phy_id, (unsigned long long) + p->phy_info[i].attached.sas_address); + +- mptsas_port_delete(ioc, p->phy_info[i].port_details); +- } +- } +- +- out: ++ mptsas_set_starget(&p->phy_info[i], NULL); ++ } ++ } ++ ++ out: ++ vtarget->starget = NULL; + kfree(starget->hostdata); + starget->hostdata = NULL; + } +@@ -1933,18 +2354,18 @@ + mptsas_slave_alloc(struct scsi_device *sdev) + { + struct Scsi_Host *host = sdev->host; +- MPT_SCSI_HOST *hd = shost_priv(host); ++ MPT_SCSI_HOST *hd = shost_private(host); + struct sas_rphy *rphy; + struct mptsas_portinfo *p; + VirtDevice *vdevice; + struct scsi_target *starget; + int i; +- MPT_ADAPTER *ioc = hd->ioc; ++ MPT_ADAPTER *ioc = hd->ioc; + + vdevice = kzalloc(sizeof(VirtDevice), GFP_KERNEL); + if (!vdevice) { + printk(MYIOC_s_ERR_FMT "slave_alloc kzalloc(%zd) FAILED!\n", +- ioc->name, sizeof(VirtDevice)); ++ ioc->name, sizeof(VirtDevice)); + return -ENOMEM; + } + starget = scsi_target(sdev); +@@ -2005,13 +2426,16 @@ + return 0; + } + +- hd = shost_priv(SCpnt->device->host); ++ hd = shost_private(SCpnt->device->host); + ioc = hd->ioc; + + if (ioc->sas_discovery_quiesce_io) + return SCSI_MLQUEUE_HOST_BUSY; + +- return mptscsih_qcmd(SCpnt, done); ++ if (ioc->debug_level & MPT_DEBUG_SCSI) ++ scsi_print_command(SCpnt); ++ ++ return mptscsih_qcmd(SCpnt,done); + } + + +@@ -2033,7 +2457,7 @@ + .eh_bus_reset_handler = mptscsih_bus_reset, + .eh_host_reset_handler = mptscsih_host_reset, + .bios_param = mptscsih_bios_param, +- .can_queue = MPT_FC_CAN_QUEUE, ++ .can_queue = MPT_SAS_CAN_QUEUE, + .this_id = -1, + .sg_tablesize = MPT_SCSI_SG_DEPTH, + .max_sectors = 8192, +@@ -2056,8 +2480,11 @@ + dma_addr_t dma_handle; + int error; + ++#if defined(MPT_WIDE_PORT_API_PLUS) ++ /* FIXME: only have link errors on local phys */ + if (!scsi_is_sas_phy_local(phy)) + return -EINVAL; ++#endif + + hdr.PageVersion = MPI_SASPHY1_PAGEVERSION; + hdr.ExtPageLength = 0; +@@ -2149,8 +2576,11 @@ + unsigned long timeleft; + int error = -ERESTARTSYS; + ++#if defined(MPT_WIDE_PORT_API_PLUS) ++ /* FIXME: fusion doesn't allow non-local phy reset */ + if (!scsi_is_sas_phy_local(phy)) + return -EINVAL; ++#endif + + /* not implemented for expanders */ + if (phy->identify.target_port_protocols & SAS_PROTOCOL_SMP) +@@ -2181,7 +2611,7 @@ + error = -ETIME; + mpt_free_msg_frame(ioc, mf); + if (ioc->sas_mgmt.status & MPT_MGMT_STATUS_DID_IOCRESET) +- goto out; ++ goto out_unlock; + if (!timeleft) { + if (mpt_SoftResetHandler(ioc, CAN_SLEEP) != 0) + mpt_HardResetHandler(ioc, CAN_SLEEP); +@@ -2248,8 +2678,7 @@ + memset(&enclosure_info, 0, sizeof(struct mptsas_enclosure)); + error = mptsas_sas_enclosure_pg0(ioc, &enclosure_info, + (MPI_SAS_ENCLOS_PGAD_FORM_HANDLE << +- MPI_SAS_ENCLOS_PGAD_FORM_SHIFT), +- enclosure_handle); ++ MPI_SAS_ENCLOS_PGAD_FORM_SHIFT), enclosure_handle); + if (!error) + *identifier = enclosure_info.enclosure_logical_id; + return error; +@@ -2283,6 +2712,7 @@ + return rc; + } + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,26)) + static int mptsas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy, + struct request *req) + { +@@ -2299,16 +2729,14 @@ + u64 sas_address = 0; + + if (!rsp) { +- printk(MYIOC_s_ERR_FMT +- "%s: the smp response space is missing\n", ++ printk(MYIOC_s_ERR_FMT "%s: the smp response space is missing\n", + ioc->name, __func__); + return -EINVAL; + } + + /* do we need to support multiple segments? */ + if (req->bio->bi_vcnt > 1 || rsp->bio->bi_vcnt > 1) { +- printk(MYIOC_s_ERR_FMT +- "%s: multiple segments req %u %u, rsp %u %u\n", ++ printk(MYIOC_s_ERR_FMT "%s: multiple segments req %u %u, rsp %u %u\n", + ioc->name, __func__, req->bio->bi_vcnt, req->data_len, + rsp->bio->bi_vcnt, rsp->data_len); + return -EINVAL; +@@ -2430,13 +2858,17 @@ + out: + return ret; + } ++#endif ++ + + static struct sas_function_template mptsas_transport_functions = { + .get_linkerrors = mptsas_get_linkerrors, + .get_enclosure_identifier = mptsas_get_enclosure_identifier, + .get_bay_identifier = mptsas_get_bay_identifier, + .phy_reset = mptsas_phy_reset, ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,26)) + .smp_handler = mptsas_smp_handler, ++#endif + }; + + static struct scsi_transport_template *mptsas_transport_template; +@@ -2495,7 +2927,7 @@ + + port_info->num_phys = buffer->NumPhys; + port_info->phy_info = kcalloc(port_info->num_phys, +- sizeof(struct mptsas_phyinfo), GFP_KERNEL); ++ sizeof(struct mptsas_phyinfo),GFP_KERNEL); + if (!port_info->phy_info) { + error = -ENOMEM; + goto out_free_consistent; +@@ -2516,8 +2948,6 @@ + port_info->phy_info[i].portinfo = port_info; + port_info->phy_info[i].handle = + le16_to_cpu(buffer->PhyData[i].ControllerDevHandle); +- port_info->phy_info[i].port_flags = +- buffer->PhyData[i].PortFlags; + } + + out_free_consistent: +@@ -2653,8 +3083,6 @@ + phy_info->programmed_link_rate = buffer->ProgrammedLinkRate; + phy_info->identify.handle = le16_to_cpu(buffer->OwnerDevHandle); + phy_info->attached.handle = le16_to_cpu(buffer->AttachedDevHandle); +- phy_info->change_count = buffer->ChangeCount; +- phy_info->phy_info = le32_to_cpu(buffer->PhyInfo); + + out_free_consistent: + pci_free_consistent(ioc->pcidev, hdr.ExtPageLength * 4, +@@ -2816,7 +3244,7 @@ + /* save config data */ + port_info->num_phys = (buffer->NumPhys) ? buffer->NumPhys : 1; + port_info->phy_info = kcalloc(port_info->num_phys, +- sizeof(struct mptsas_phyinfo), GFP_KERNEL); ++ sizeof(struct mptsas_phyinfo),GFP_KERNEL); + if (!port_info->phy_info) { + error = -ENOMEM; + goto out_free_consistent; +@@ -2897,7 +3325,7 @@ + error = -ENODEV; + goto out; + } +- ++ + if (error) + goto out_free_consistent; + +@@ -2912,15 +3340,200 @@ + phy_info->hw_link_rate = buffer->HwLinkRate; + phy_info->identify.handle = le16_to_cpu(buffer->OwnerDevHandle); + phy_info->attached.handle = le16_to_cpu(buffer->AttachedDevHandle); +- phy_info->change_count = buffer->ChangeCount; +- phy_info->phy_info = le32_to_cpu(buffer->PhyInfo); +- +- out_free_consistent: +- pci_free_consistent(ioc->pcidev, hdr.ExtPageLength * 4, +- buffer, dma_handle); +- out: +- return error; +-} ++ ++ out_free_consistent: ++ pci_free_consistent(ioc->pcidev, hdr.ExtPageLength * 4, ++ buffer, dma_handle); ++ out: ++ return error; ++} ++ ++struct rep_manu_request{ ++ u8 smp_frame_type; ++ u8 function; ++ u8 reserved; ++ u8 request_length; ++}; ++ ++struct rep_manu_reply{ ++ u8 smp_frame_type; /* 0x41 */ ++ u8 function; /* 0x01 */ ++ u8 function_result; ++ u8 response_length; ++ u16 expander_change_count; ++ u8 reserved0[2]; ++ u8 sas_format:1; ++ u8 reserved1:7; ++ u8 reserved2[3]; ++ u8 vendor_id[SAS_EXPANDER_VENDOR_ID_LEN]; ++ u8 product_id[SAS_EXPANDER_PRODUCT_ID_LEN]; ++ u8 product_rev[SAS_EXPANDER_PRODUCT_REV_LEN]; ++ u8 component_vendor_id[SAS_EXPANDER_COMPONENT_VENDOR_ID_LEN]; ++ u16 component_id; ++ u8 component_revision_id; ++ u8 reserved3; ++ u8 vendor_specific[8]; ++}; ++ ++/** ++ * mptsas_exp_repmanufacture_info - ++ * @ioc: per adapter object ++ * @sas_address: expander sas address ++ * @edev: the sas_expander_device object ++ * ++ * Fills in the sas_expander_device object when SMP port is created. ++ * ++ * Returns 0 for success, non-zero for failure. ++ */ ++static int ++mptsas_exp_repmanufacture_info(MPT_ADAPTER *ioc, ++ u64 sas_address, struct sas_expander_device *edev) ++{ ++ MPT_FRAME_HDR *mf; ++ SmpPassthroughRequest_t *smpreq; ++ SmpPassthroughReply_t *smprep; ++ struct rep_manu_reply *manufacture_reply; ++ struct rep_manu_request *manufacture_request; ++ int ret; ++ int flagsLength; ++ unsigned long timeleft; ++ char *psge; ++ unsigned long flags; ++ void *data_out = NULL; ++ dma_addr_t data_out_dma = 0; ++ u32 sz; ++ ++ spin_lock_irqsave(&ioc->taskmgmt_lock, flags); ++ if (ioc->ioc_reset_in_progress) { ++ spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); ++ printk(MYIOC_s_INFO_FMT "%s: host reset in progress!\n", ++ __func__, ioc->name); ++ return -EFAULT; ++ } ++ spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); ++ ++ ret = mutex_lock_interruptible(&ioc->sas_mgmt.mutex); ++ if (ret) ++ goto out; ++ ++ mf = mpt_get_msg_frame(mptsasMgmtCtx, ioc); ++ if (!mf) { ++ ret = -ENOMEM; ++ goto out_unlock; ++ } ++ ++ smpreq = (SmpPassthroughRequest_t *)mf; ++ memset(smpreq, 0, sizeof(*smpreq)); ++ ++ sz = sizeof(struct rep_manu_request) + sizeof(struct rep_manu_reply); ++ ++ data_out = pci_alloc_consistent(ioc->pcidev, sz, &data_out_dma); ++ if (!data_out) { ++ printk(KERN_ERR "Memory allocation failure at %s:%d/%s()!\n", ++ __FILE__, __LINE__, __func__); ++ ret = -ENOMEM; ++ goto put_mf; ++ } ++ ++ manufacture_request = data_out; ++ manufacture_request->smp_frame_type = 0x40; ++ manufacture_request->function = 1; ++ manufacture_request->reserved = 0; ++ manufacture_request->request_length = 0; ++ ++ smpreq->Function = MPI_FUNCTION_SMP_PASSTHROUGH; ++ smpreq->PhysicalPort = 0xFF; ++ *((u64 *)&smpreq->SASAddress) = cpu_to_le64(sas_address); ++ smpreq->RequestDataLength = sizeof(struct rep_manu_request); ++ ++ psge = (char *) ++ (((int *) mf) + (offsetof(SmpPassthroughRequest_t, SGL) / 4)); ++ ++ flagsLength = MPI_SGE_FLAGS_SIMPLE_ELEMENT | ++ MPI_SGE_FLAGS_SYSTEM_ADDRESS | ++ MPI_SGE_FLAGS_HOST_TO_IOC | ++ MPI_SGE_FLAGS_END_OF_BUFFER; ++ flagsLength = flagsLength << MPI_SGE_FLAGS_SHIFT; ++ flagsLength |= sizeof(struct rep_manu_request); ++ ++ ioc->add_sge(psge, flagsLength, data_out_dma); ++ psge += ioc->SGE_size; ++ ++ flagsLength = MPI_SGE_FLAGS_SIMPLE_ELEMENT | ++ MPI_SGE_FLAGS_SYSTEM_ADDRESS | ++ MPI_SGE_FLAGS_IOC_TO_HOST | ++ MPI_SGE_FLAGS_END_OF_BUFFER; ++ flagsLength = flagsLength << MPI_SGE_FLAGS_SHIFT; ++ flagsLength |= sizeof(struct rep_manu_reply); ++ ioc->add_sge(psge, flagsLength, data_out_dma + ++ sizeof(struct rep_manu_request)); ++ ++ INITIALIZE_MGMT_STATUS(ioc->sas_mgmt.status) ++ mpt_put_msg_frame(mptsasMgmtCtx, ioc, mf); ++ ++ timeleft = wait_for_completion_timeout(&ioc->sas_mgmt.done, 10 * HZ); ++ if (!(ioc->sas_mgmt.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { ++ ret = -ETIME; ++ mpt_free_msg_frame(ioc, mf); ++ mf = NULL; ++ if (ioc->sas_mgmt.status & MPT_MGMT_STATUS_DID_IOCRESET) ++ goto out_free; ++ if (!timeleft) { ++ if (mpt_SoftResetHandler(ioc, CAN_SLEEP) != 0) ++ mpt_HardResetHandler(ioc, CAN_SLEEP); ++ } ++ goto out_free; ++ } ++ ++ mf = NULL; ++ ++ if (ioc->sas_mgmt.status & MPT_MGMT_STATUS_RF_VALID) { ++ u8 *tmp; ++ ++ smprep = (SmpPassthroughReply_t *)ioc->sas_mgmt.reply; ++ if (le16_to_cpu(smprep->ResponseDataLength) != ++ sizeof(struct rep_manu_reply)) ++ goto out_free; ++ ++ manufacture_reply = data_out + sizeof(struct rep_manu_request); ++ strncpy(edev->vendor_id, manufacture_reply->vendor_id, ++ SAS_EXPANDER_VENDOR_ID_LEN); ++ strncpy(edev->product_id, manufacture_reply->product_id, ++ SAS_EXPANDER_PRODUCT_ID_LEN); ++ strncpy(edev->product_rev, manufacture_reply->product_rev, ++ SAS_EXPANDER_PRODUCT_REV_LEN); ++ edev->level = manufacture_reply->sas_format; ++ if (manufacture_reply->sas_format) { ++ strncpy(edev->component_vendor_id, ++ manufacture_reply->component_vendor_id, ++ SAS_EXPANDER_COMPONENT_VENDOR_ID_LEN); ++ tmp = (u8 *)&manufacture_reply->component_id; ++ edev->component_id = tmp[0] << 8 | tmp[1]; ++ edev->component_revision_id = ++ manufacture_reply->component_revision_id; ++ } ++ ++ } else { ++ printk(MYIOC_s_ERR_FMT ++ "%s: smp passthru reply failed to be returned\n", ++ ioc->name, __func__); ++ ret = -ENXIO; ++ } ++ ++out_free: ++ if (data_out_dma) ++ pci_free_consistent(ioc->pcidev, sz, data_out, data_out_dma); ++put_mf: ++ if (mf) ++ mpt_free_msg_frame(ioc, mf); ++out_unlock: ++ CLEAR_MGMT_STATUS(ioc->sas_mgmt.status) ++ mutex_unlock(&ioc->sas_mgmt.mutex); ++out: ++ return ret; ++ ++} ++ + + /** + * mptsas_parse_device_info - +@@ -2999,7 +3612,9 @@ + { + MPT_ADAPTER *ioc; + struct sas_phy *phy; ++#if defined(MPT_WIDE_PORT_API) + struct sas_port *port; ++#endif + int error = 0; + + if (!dev) { +@@ -3016,6 +3631,9 @@ + } else + phy = phy_info->phy; + ++#if !defined(MPT_WIDE_PORT_API) ++ phy->port_identifier = phy_info->port_id; ++#endif + mptsas_parse_device_info(&phy->identify, &phy_info->identify); + + /* +@@ -3101,6 +3719,10 @@ + + if (!phy_info->phy) { + ++#if !defined(MPT_WIDE_PORT_API_PLUS) ++ if (local) ++ phy->local_attached = 1; ++#endif + error = sas_phy_add(phy); + if (error) { + sas_phy_free(phy); +@@ -3113,9 +3735,12 @@ + !phy_info->port_details) + goto out; + ++#if defined(MPT_WIDE_PORT_API) + port = mptsas_get_port(phy_info); ++#endif + ioc = phy_to_ioc(phy_info->phy); + ++#if defined(MPT_WIDE_PORT_API) + if (phy_info->sas_port_add_phy) { + if (!port) { + port = sas_port_alloc_num(dev); +@@ -3136,21 +3761,41 @@ + ioc->name, port->port_identifier, + (unsigned long long)phy_info->attached.sas_address)); + } ++ dsaswideprintk(ioc, printk(MYIOC_s_DEBUG_FMT "sas_port_add_phy: phy_id=%d\n", ++ ioc->name, phy_info->phy_id)); + sas_port_add_phy(port, phy_info->phy); + phy_info->sas_port_add_phy = 0; + devtprintk(ioc, dev_printk(KERN_DEBUG, &phy_info->phy->dev, + MYIOC_s_FMT "add phy %d, phy-obj (0x%p)\n", ioc->name, + phy_info->phy_id, phy_info->phy)); + } +- ++#else ++ /* ++ * wide port suport ++ * only report the expander or end device once ++ */ ++ if (phy_info->attached.wide_port_enable && ++ (phy_info->phy_id != mptsas_get_rphy_id(phy_info))) ++ goto out; ++ ++#endif ++ ++#if defined(MPT_WIDE_PORT_API) + if (!mptsas_get_rphy(phy_info) && port && !port->rphy) { ++#else ++ if (!mptsas_get_rphy(phy_info)) { ++#endif + + struct sas_rphy *rphy; + struct device *parent; + struct sas_identify identify; + + parent = dev->parent->parent; +- ++ /* ++ * Let the hotplug_work thread handle processing ++ * the adding/removing of devices that occur ++ * after start of day. ++ */ + if (mptsas_is_end_device(&phy_info->attached) && + phy_info->attached.handle_parent) { + goto out; +@@ -3162,29 +3807,42 @@ + int i; + + port_info = ioc->hba_port_info; ++ + for (i = 0; i < port_info->num_phys; i++) + if (port_info->phy_info[i].identify.sas_address == + identify.sas_address) { ++#if defined(MPT_WIDE_PORT_API_PLUS) + sas_port_mark_backlink(port); ++#endif + goto out; +- } ++ } + + } else if (scsi_is_sas_rphy(parent)) { + struct sas_rphy *parent_rphy = dev_to_rphy(parent); + if (identify.sas_address == + parent_rphy->identify.sas_address) { ++#if defined(MPT_WIDE_PORT_API_PLUS) + sas_port_mark_backlink(port); ++#endif + goto out; + } + } + + switch (identify.device_type) { + case SAS_END_DEVICE: ++#if defined(MPT_WIDE_PORT_API) + rphy = sas_end_device_alloc(port); ++#else ++ rphy = sas_end_device_alloc(phy); ++#endif + break; + case SAS_EDGE_EXPANDER_DEVICE: + case SAS_FANOUT_EXPANDER_DEVICE: ++#if defined(MPT_WIDE_PORT_API) + rphy = sas_expander_alloc(port, identify.device_type); ++#else ++ rphy = sas_expander_alloc(phy, identify.device_type); ++#endif + break; + default: + rphy = NULL; +@@ -3207,6 +3865,11 @@ + goto out; + } + mptsas_set_rphy(ioc, phy_info, rphy); ++ if (identify.device_type == SAS_EDGE_EXPANDER_DEVICE || ++ identify.device_type == SAS_FANOUT_EXPANDER_DEVICE) ++ mptsas_exp_repmanufacture_info(ioc, ++ identify.sas_address, ++ rphy_to_expander_device(rphy)); + } + + out: +@@ -3226,7 +3889,7 @@ + int error = -ENOMEM, i; + + hba = kzalloc(sizeof(struct mptsas_portinfo), GFP_KERNEL); +- if (!hba) ++ if (! hba) + goto out; + + error = mptsas_sas_io_unit_pg0(ioc, hba); +@@ -3248,8 +3911,6 @@ + hba->phy_info[i].handle; + port_info->phy_info[i].port_id = + hba->phy_info[i].port_id; +- port_info->phy_info[i].port_flags = +- hba->phy_info[i].port_flags; + } + kfree(hba->phy_info); + kfree(hba); +@@ -3296,1062 +3957,6 @@ + return error; + } + +-/** +- * mptsas_find_phyinfo_by_sas_address - +- * @ioc: Pointer to MPT_ADAPTER structure +- * @sas_address: +- * +- **/ +-static struct mptsas_phyinfo * +-mptsas_find_phyinfo_by_sas_address(MPT_ADAPTER *ioc, u64 sas_address) +-{ +- struct mptsas_portinfo *port_info; +- struct mptsas_phyinfo *phy_info = NULL; +- int i; +- +- mutex_lock(&ioc->sas_topology_mutex); +- list_for_each_entry(port_info, &ioc->sas_topology, list) { +- for (i = 0; i < port_info->num_phys; i++) { +- if (!mptsas_is_end_device( +- &port_info->phy_info[i].attached)) +- continue; +- if (port_info->phy_info[i].attached.sas_address +- != sas_address) +- continue; +- phy_info = &port_info->phy_info[i]; +- break; +- } +- } +- mutex_unlock(&ioc->sas_topology_mutex); +- return phy_info; +-} +- +-/** +- * mptsas_find_phyinfo_by_phys_disk_num - +- * @ioc: Pointer to MPT_ADAPTER structure +- * @phys_disk_num: +- * @channel: +- * @id: +- * +- **/ +-static struct mptsas_phyinfo * +-mptsas_find_phyinfo_by_phys_disk_num(MPT_ADAPTER *ioc, u8 phys_disk_num, +- u8 channel, u8 id) +-{ +- struct mptsas_phyinfo *phy_info; +- struct mptsas_portinfo *port_info; +- RaidPhysDiskPage1_t *phys_disk = NULL; +- int num_paths; +- u64 sas_address = 0; +- int i; +- +- phy_info = NULL; +- if (!ioc->raid_data.pIocPg3) +- return NULL; +- /* dual port support */ +- num_paths = mpt_raid_phys_disk_get_num_paths(ioc, phys_disk_num); +- if (!num_paths) +- goto out; +- phys_disk = kzalloc(offsetof(RaidPhysDiskPage1_t, Path) + +- (num_paths * sizeof(RAID_PHYS_DISK1_PATH)), GFP_KERNEL); +- if (!phys_disk) +- goto out; +- mpt_raid_phys_disk_pg1(ioc, phys_disk_num, phys_disk); +- for (i = 0; i < num_paths; i++) { +- if ((phys_disk->Path[i].Flags & 1) != 0) +- /* entry no longer valid */ +- continue; +- if ((id == phys_disk->Path[i].PhysDiskID) && +- (channel == phys_disk->Path[i].PhysDiskBus)) { +- memcpy(&sas_address, &phys_disk->Path[i].WWID, +- sizeof(u64)); +- phy_info = mptsas_find_phyinfo_by_sas_address(ioc, +- sas_address); +- goto out; +- } +- } +- +- out: +- kfree(phys_disk); +- if (phy_info) +- return phy_info; +- +- /* +- * Extra code to handle RAID0 case, where the sas_address is not updated +- * in phys_disk_page_1 when hotswapped +- */ +- mutex_lock(&ioc->sas_topology_mutex); +- list_for_each_entry(port_info, &ioc->sas_topology, list) { +- for (i = 0; i < port_info->num_phys && !phy_info; i++) { +- if (!mptsas_is_end_device( +- &port_info->phy_info[i].attached)) +- continue; +- if (port_info->phy_info[i].attached.phys_disk_num == ~0) +- continue; +- if (port_info->phy_info[i].attached.phys_disk_num == +- phys_disk_num && +- port_info->phy_info[i].attached.id == id && +- port_info->phy_info[i].attached.channel == channel) +- phy_info = &port_info->phy_info[i]; +- } +- } +- mutex_unlock(&ioc->sas_topology_mutex); +- return phy_info; +-} +- +-/** +- * mptsas_reprobe_lun - +- * @sdev: +- * @data: +- * +- **/ +-static void +-mptsas_reprobe_lun(struct scsi_device *sdev, void *data) +-{ +- int rc; +- +- sdev->no_uld_attach = data ? 1 : 0; +- rc = scsi_device_reprobe(sdev); +-} +- +-/** +- * mptsas_reprobe_target - +- * @starget: +- * @uld_attach: +- * +- **/ +-static void +-mptsas_reprobe_target(struct scsi_target *starget, int uld_attach) +-{ +- starget_for_each_device(starget, uld_attach ? (void *)1 : NULL, +- mptsas_reprobe_lun); +-} +- +-/** +- * mptsas_adding_inactive_raid_components - +- * @ioc: Pointer to MPT_ADAPTER structure +- * @channel: +- * @id: +- * +- * +- **/ +-static void +-mptsas_adding_inactive_raid_components(MPT_ADAPTER *ioc, u8 channel, u8 id) +-{ +- CONFIGPARMS cfg; +- ConfigPageHeader_t hdr; +- dma_addr_t dma_handle; +- pRaidVolumePage0_t buffer = NULL; +- RaidPhysDiskPage0_t phys_disk; +- int i; +- struct mptsas_phyinfo *phy_info; +- struct mptsas_devinfo sas_device; +- +- memset(&cfg, 0 , sizeof(CONFIGPARMS)); +- memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); +- hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME; +- cfg.pageAddr = (channel << 8) + id; +- cfg.cfghdr.hdr = &hdr; +- cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; +- cfg.timeout = SAS_CONFIG_PAGE_TIMEOUT; +- +- if (mpt_config(ioc, &cfg) != 0) +- goto out; +- +- if (!hdr.PageLength) +- goto out; +- +- buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, +- &dma_handle); +- +- if (!buffer) +- goto out; +- +- cfg.physAddr = dma_handle; +- cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; +- +- if (mpt_config(ioc, &cfg) != 0) +- goto out; +- +- if (!(buffer->VolumeStatus.Flags & +- MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE)) +- goto out; +- +- if (!buffer->NumPhysDisks) +- goto out; +- +- for (i = 0; i < buffer->NumPhysDisks; i++) { +- +- if (mpt_raid_phys_disk_pg0(ioc, +- buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0) +- continue; +- +- if (mptsas_sas_device_pg0(ioc, &sas_device, +- (MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID << +- MPI_SAS_DEVICE_PGAD_FORM_SHIFT), +- (phys_disk.PhysDiskBus << 8) + +- phys_disk.PhysDiskID)) +- continue; +- +- phy_info = mptsas_find_phyinfo_by_sas_address(ioc, +- sas_device.sas_address); +- mptsas_add_end_device(ioc, phy_info); +- } +- +- out: +- if (buffer) +- pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer, +- dma_handle); +-} +- +-/** +- * mptsas_add_end_device - report a new end device to sas transport layer +- * @ioc: Pointer to MPT_ADAPTER structure +- * @phy_info: decribes attached device +- * +- * return (0) success (1) failure +- * +- **/ +-static int +-mptsas_add_end_device(MPT_ADAPTER *ioc, struct mptsas_phyinfo *phy_info) +-{ +- struct sas_rphy *rphy; +- struct sas_port *port; +- struct sas_identify identify; +- char *ds = NULL; +- u8 fw_id; +- +- if (!phy_info) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: exit at line=%d\n", ioc->name, +- __func__, __LINE__)); +- return 1; +- } +- +- fw_id = phy_info->attached.id; +- +- if (mptsas_get_rphy(phy_info)) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, fw_id, __LINE__)); +- return 2; +- } +- +- port = mptsas_get_port(phy_info); +- if (!port) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, fw_id, __LINE__)); +- return 3; +- } +- +- if (phy_info->attached.device_info & +- MPI_SAS_DEVICE_INFO_SSP_TARGET) +- ds = "ssp"; +- if (phy_info->attached.device_info & +- MPI_SAS_DEVICE_INFO_STP_TARGET) +- ds = "stp"; +- if (phy_info->attached.device_info & +- MPI_SAS_DEVICE_INFO_SATA_DEVICE) +- ds = "sata"; +- +- printk(MYIOC_s_INFO_FMT "attaching %s device: fw_channel %d, fw_id %d," +- " phy %d, sas_addr 0x%llx\n", ioc->name, ds, +- phy_info->attached.channel, phy_info->attached.id, +- phy_info->attached.phy_id, (unsigned long long) +- phy_info->attached.sas_address); +- +- mptsas_parse_device_info(&identify, &phy_info->attached); +- rphy = sas_end_device_alloc(port); +- if (!rphy) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, fw_id, __LINE__)); +- return 5; /* non-fatal: an rphy can be added later */ +- } +- +- rphy->identify = identify; +- if (sas_rphy_add(rphy)) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, fw_id, __LINE__)); +- sas_rphy_free(rphy); +- return 6; +- } +- mptsas_set_rphy(ioc, phy_info, rphy); +- return 0; +-} +- +-/** +- * mptsas_del_end_device - report a deleted end device to sas transport +- * layer +- * @ioc: Pointer to MPT_ADAPTER structure +- * @phy_info: decribes attached device +- * +- **/ +-static void +-mptsas_del_end_device(MPT_ADAPTER *ioc, struct mptsas_phyinfo *phy_info) +-{ +- struct sas_rphy *rphy; +- struct sas_port *port; +- struct mptsas_portinfo *port_info; +- struct mptsas_phyinfo *phy_info_parent; +- int i; +- struct scsi_target *starget; +- char *ds = NULL; +- u8 fw_id; +- u64 sas_address; +- +- if (!phy_info) +- return; +- +- fw_id = phy_info->attached.id; +- sas_address = phy_info->attached.sas_address; +- +- if (!phy_info->port_details) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, fw_id, __LINE__)); +- return; +- } +- rphy = mptsas_get_rphy(phy_info); +- if (!rphy) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, fw_id, __LINE__)); +- return; +- } +- if (phy_info->attached.device_info & +- MPI_SAS_DEVICE_INFO_SSP_TARGET) +- ds = "ssp"; +- if (phy_info->attached.device_info & +- MPI_SAS_DEVICE_INFO_STP_TARGET) +- ds = "stp"; +- if (phy_info->attached.device_info & +- MPI_SAS_DEVICE_INFO_SATA_DEVICE) +- ds = "sata"; +- +- starget = mptsas_get_starget(phy_info); +- +- printk(MYIOC_s_INFO_FMT "removing %s device: fw_channel %d," +- " fw_id %d, phy %d, sas_addr 0x%llx\n", ioc->name, ds, +- phy_info->attached.channel, phy_info->attached.id, +- phy_info->attached.phy_id, (unsigned long long) +- sas_address); +- +- port = mptsas_get_port(phy_info); +- if (!port) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, fw_id, __LINE__)); +- return; +- } +- port_info = phy_info->portinfo; +- phy_info_parent = port_info->phy_info; +- for (i = 0; i < port_info->num_phys; i++, phy_info_parent++) { +- if (!phy_info_parent->phy) +- continue; +- if (phy_info_parent->attached.sas_address != +- sas_address) +- continue; +- dev_printk(KERN_DEBUG, &phy_info_parent->phy->dev, +- MYIOC_s_FMT "delete phy %d, phy-obj (0x%p)\n", +- ioc->name, phy_info_parent->phy_id, +- phy_info_parent->phy); +- sas_port_delete_phy(port, phy_info_parent->phy); +- } +- +- dev_printk(KERN_DEBUG, &port->dev, MYIOC_s_FMT +- "delete port %d, sas_addr (0x%llx)\n", ioc->name, +- port->port_identifier, (unsigned long long)sas_address); +- sas_port_delete(port); +-} +- +-struct mptsas_phyinfo * +-mptsas_refreshing_device_handles(MPT_ADAPTER *ioc, +- struct mptsas_devinfo *sas_device) +-{ +- struct mptsas_phyinfo *phy_info; +- struct mptsas_portinfo *port_info; +- int i; +- +- phy_info = mptsas_find_phyinfo_by_sas_address(ioc, +- sas_device->sas_address); +- if (!phy_info) +- goto out; +- port_info = phy_info->portinfo; +- if (!port_info) +- goto out; +- mutex_lock(&ioc->sas_topology_mutex); +- for (i = 0; i < port_info->num_phys; i++) { +- if (port_info->phy_info[i].attached.sas_address != +- sas_device->sas_address) +- continue; +- port_info->phy_info[i].attached.channel = sas_device->channel; +- port_info->phy_info[i].attached.id = sas_device->id; +- port_info->phy_info[i].attached.sas_address = +- sas_device->sas_address; +- port_info->phy_info[i].attached.handle = sas_device->handle; +- port_info->phy_info[i].attached.handle_parent = +- sas_device->handle_parent; +- port_info->phy_info[i].attached.handle_enclosure = +- sas_device->handle_enclosure; +- } +- mutex_unlock(&ioc->sas_topology_mutex); +- out: +- return phy_info; +-} +- +- +-/** +- * mptsas_hotplug_work - Work queue thread to handle SAS hotplug events +- * +- * +- **/ +-static void +-mptsas_hotplug_work(MPT_ADAPTER *ioc, struct fw_event_work *fw_event, +- struct mptsas_hotplug_event *hot_plug_info) +-{ +- struct mptsas_phyinfo *phy_info; +- struct scsi_target *starget; +- struct mptsas_devinfo sas_device; +- VirtTarget *vtarget; +- enum device_state state; +- int i; +- +- switch (hot_plug_info->event_type) { +- +- case MPTSAS_ADD_PHYSDISK: +- +- if (!ioc->raid_data.pIocPg2) +- break; +- +- for (i = 0; i < ioc->raid_data.pIocPg2->NumActiveVolumes; i++) { +- if (ioc->raid_data.pIocPg2->RaidVolume[i].VolumeID == +- hot_plug_info->id) { +- printk(MYIOC_s_WARN_FMT "firmware bug: unable " +- "to add hidden disk - target_id matchs " +- "volume_id\n", ioc->name); +- mptsas_free_fw_event(ioc, fw_event); +- return; +- } +- } +- mpt_findImVolumes(ioc); +- +- case MPTSAS_ADD_DEVICE: +- memset(&sas_device, 0, sizeof(struct mptsas_devinfo)); +- mptsas_sas_device_pg0(ioc, &sas_device, +- (MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID << +- MPI_SAS_DEVICE_PGAD_FORM_SHIFT), +- (hot_plug_info->channel << 8) + +- hot_plug_info->id); +- +- if (!sas_device.handle) +- return; +- +- phy_info = mptsas_refreshing_device_handles(ioc, &sas_device); +- if (!phy_info) +- break; +- +- if (mptsas_get_rphy(phy_info)) +- break; +- +- state = mptsas_test_unit_ready(ioc, phy_info->attached.channel, +- phy_info->attached.id, fw_event->retries); +- +- if (state == DEVICE_RETRY && !ioc->fw_events_off) { +- mptsas_requeue_fw_event(ioc, fw_event, 1000); +- return; +- } +- +- if (state == DEVICE_READY) +- mptsas_add_end_device(ioc, phy_info); +- break; +- +- case MPTSAS_DEL_DEVICE: +- +- if (!ioc->disable_hotplug_remove) { +- phy_info = mptsas_find_phyinfo_by_sas_address(ioc, +- hot_plug_info->sas_address); +- mptsas_del_end_device(ioc, phy_info); +- } +- break; +- +- case MPTSAS_DEL_PHYSDISK: +- +- mpt_findImVolumes(ioc); +- +- phy_info = mptsas_find_phyinfo_by_phys_disk_num( +- ioc, hot_plug_info->phys_disk_num, hot_plug_info->channel, +- hot_plug_info->id); +- mptsas_del_end_device(ioc, phy_info); +- break; +- +- case MPTSAS_ADD_PHYSDISK_REPROBE: +- +- if (mptsas_sas_device_pg0(ioc, &sas_device, +- (MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID << +- MPI_SAS_DEVICE_PGAD_FORM_SHIFT), +- (hot_plug_info->channel << 8) + hot_plug_info->id)) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, hot_plug_info->id, __LINE__)); +- break; +- } +- +- phy_info = mptsas_find_phyinfo_by_sas_address( +- ioc, sas_device.sas_address); +- +- if (!phy_info) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, hot_plug_info->id, __LINE__)); +- break; +- } +- +- starget = mptsas_get_starget(phy_info); +- if (!starget) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, hot_plug_info->id, __LINE__)); +- break; +- } +- +- vtarget = starget->hostdata; +- if (!vtarget) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, hot_plug_info->id, __LINE__)); +- break; +- } +- +- mpt_findImVolumes(ioc); +- +- starget_printk(KERN_INFO, starget, MYIOC_s_FMT "RAID Hidding: " +- "fw_channel=%d, fw_id=%d, physdsk %d, sas_addr 0x%llx\n", +- ioc->name, hot_plug_info->channel, hot_plug_info->id, +- hot_plug_info->phys_disk_num, (unsigned long long) +- sas_device.sas_address); +- +- vtarget->id = hot_plug_info->phys_disk_num; +- vtarget->tflags |= MPT_TARGET_FLAGS_RAID_COMPONENT; +- phy_info->attached.phys_disk_num = hot_plug_info->phys_disk_num; +- mptsas_reprobe_target(starget, 1); +- break; +- +- case MPTSAS_DEL_PHYSDISK_REPROBE: +- +- if (mptsas_sas_device_pg0(ioc, &sas_device, +- (MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID << +- MPI_SAS_DEVICE_PGAD_FORM_SHIFT), +- (hot_plug_info->channel << 8) + hot_plug_info->id)) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", +- ioc->name, __func__, +- hot_plug_info->id, __LINE__)); +- break; +- } +- +- phy_info = mptsas_find_phyinfo_by_sas_address(ioc, +- sas_device.sas_address); +- if (!phy_info) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, hot_plug_info->id, __LINE__)); +- break; +- } +- +- starget = mptsas_get_starget(phy_info); +- if (!starget) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, hot_plug_info->id, __LINE__)); +- break; +- } +- +- vtarget = starget->hostdata; +- if (!vtarget) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, hot_plug_info->id, __LINE__)); +- break; +- } +- +- if (!(vtarget->tflags & MPT_TARGET_FLAGS_RAID_COMPONENT)) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: fw_id=%d exit at line=%d\n", ioc->name, +- __func__, hot_plug_info->id, __LINE__)); +- break; +- } +- +- mpt_findImVolumes(ioc); +- +- starget_printk(KERN_INFO, starget, MYIOC_s_FMT "RAID Exposing:" +- " fw_channel=%d, fw_id=%d, physdsk %d, sas_addr 0x%llx\n", +- ioc->name, hot_plug_info->channel, hot_plug_info->id, +- hot_plug_info->phys_disk_num, (unsigned long long) +- sas_device.sas_address); +- +- vtarget->tflags &= ~MPT_TARGET_FLAGS_RAID_COMPONENT; +- vtarget->id = hot_plug_info->id; +- phy_info->attached.phys_disk_num = ~0; +- mptsas_reprobe_target(starget, 0); +- mptsas_add_device_component_by_fw(ioc, +- hot_plug_info->channel, hot_plug_info->id); +- break; +- +- case MPTSAS_ADD_RAID: +- +- mpt_findImVolumes(ioc); +- printk(MYIOC_s_INFO_FMT "attaching raid volume, channel %d, " +- "id %d\n", ioc->name, MPTSAS_RAID_CHANNEL, +- hot_plug_info->id); +- scsi_add_device(ioc->sh, MPTSAS_RAID_CHANNEL, +- hot_plug_info->id, 0); +- break; +- +- case MPTSAS_DEL_RAID: +- +- mpt_findImVolumes(ioc); +- printk(MYIOC_s_INFO_FMT "removing raid volume, channel %d, " +- "id %d\n", ioc->name, MPTSAS_RAID_CHANNEL, +- hot_plug_info->id); +- scsi_remove_device(hot_plug_info->sdev); +- scsi_device_put(hot_plug_info->sdev); +- break; +- +- case MPTSAS_ADD_INACTIVE_VOLUME: +- +- mpt_findImVolumes(ioc); +- mptsas_adding_inactive_raid_components(ioc, +- hot_plug_info->channel, hot_plug_info->id); +- break; +- +- default: +- break; +- } +- +- mptsas_free_fw_event(ioc, fw_event); +-} +- +-/** +- * mptsas_send_sas_event +- * +- * +- * @ioc +- * @sas_event_data +- * +- **/ +-static void +-mptsas_send_sas_event(struct fw_event_work *fw_event) +-{ +- MPT_ADAPTER *ioc; +- struct mptsas_hotplug_event hot_plug_info; +- EVENT_DATA_SAS_DEVICE_STATUS_CHANGE *sas_event_data; +- u32 device_info; +- u64 sas_address; +- +- ioc = fw_event->ioc; +- sas_event_data = (EVENT_DATA_SAS_DEVICE_STATUS_CHANGE *) +- fw_event->event_data; +- device_info = le32_to_cpu(sas_event_data->DeviceInfo); +- +- if ((device_info & +- (MPI_SAS_DEVICE_INFO_SSP_TARGET | +- MPI_SAS_DEVICE_INFO_STP_TARGET | +- MPI_SAS_DEVICE_INFO_SATA_DEVICE)) == 0) { +- mptsas_free_fw_event(ioc, fw_event); +- return; +- } +- +- if (sas_event_data->ReasonCode == +- MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED) { +- mptbase_sas_persist_operation(ioc, +- MPI_SAS_OP_CLEAR_NOT_PRESENT); +- mptsas_free_fw_event(ioc, fw_event); +- return; +- } +- +- switch (sas_event_data->ReasonCode) { +- case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING: +- case MPI_EVENT_SAS_DEV_STAT_RC_ADDED: +- memset(&hot_plug_info, 0, sizeof(struct mptsas_hotplug_event)); +- hot_plug_info.handle = le16_to_cpu(sas_event_data->DevHandle); +- hot_plug_info.channel = sas_event_data->Bus; +- hot_plug_info.id = sas_event_data->TargetID; +- hot_plug_info.phy_id = sas_event_data->PhyNum; +- memcpy(&sas_address, &sas_event_data->SASAddress, +- sizeof(u64)); +- hot_plug_info.sas_address = le64_to_cpu(sas_address); +- hot_plug_info.device_info = device_info; +- if (sas_event_data->ReasonCode & +- MPI_EVENT_SAS_DEV_STAT_RC_ADDED) +- hot_plug_info.event_type = MPTSAS_ADD_DEVICE; +- else +- hot_plug_info.event_type = MPTSAS_DEL_DEVICE; +- mptsas_hotplug_work(ioc, fw_event, &hot_plug_info); +- break; +- +- case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED: +- mptbase_sas_persist_operation(ioc, +- MPI_SAS_OP_CLEAR_NOT_PRESENT); +- mptsas_free_fw_event(ioc, fw_event); +- break; +- +- case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA: +- case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: +- default: +- mptsas_free_fw_event(ioc, fw_event); +- break; +- } +-} +- +- +-/** +- * mptsas_send_raid_event +- * +- * +- * @ioc +- * @raid_event_data +- * +- **/ +-static void +-mptsas_send_raid_event(struct fw_event_work *fw_event) +-{ +- MPT_ADAPTER *ioc; +- EVENT_DATA_RAID *raid_event_data; +- struct mptsas_hotplug_event hot_plug_info; +- int status; +- int state; +- struct scsi_device *sdev = NULL; +- VirtDevice *vdevice = NULL; +- RaidPhysDiskPage0_t phys_disk; +- +- ioc = fw_event->ioc; +- raid_event_data = (EVENT_DATA_RAID *)fw_event->event_data; +- status = le32_to_cpu(raid_event_data->SettingsStatus); +- state = (status >> 8) & 0xff; +- +- memset(&hot_plug_info, 0, sizeof(struct mptsas_hotplug_event)); +- hot_plug_info.id = raid_event_data->VolumeID; +- hot_plug_info.channel = raid_event_data->VolumeBus; +- hot_plug_info.phys_disk_num = raid_event_data->PhysDiskNum; +- +- if (raid_event_data->ReasonCode == MPI_EVENT_RAID_RC_VOLUME_DELETED || +- raid_event_data->ReasonCode == MPI_EVENT_RAID_RC_VOLUME_CREATED || +- raid_event_data->ReasonCode == +- MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED) { +- sdev = scsi_device_lookup(ioc->sh, MPTSAS_RAID_CHANNEL, +- hot_plug_info.id, 0); +- hot_plug_info.sdev = sdev; +- if (sdev) +- vdevice = sdev->hostdata; +- } +- +- devtprintk(ioc, printk(MYIOC_s_INFO_FMT "Entering %s: " +- "ReasonCode=%02x\n", ioc->name, __func__, +- raid_event_data->ReasonCode)); +- +- switch (raid_event_data->ReasonCode) { +- case MPI_EVENT_RAID_RC_PHYSDISK_DELETED: +- hot_plug_info.event_type = MPTSAS_DEL_PHYSDISK_REPROBE; +- break; +- case MPI_EVENT_RAID_RC_PHYSDISK_CREATED: +- hot_plug_info.event_type = MPTSAS_ADD_PHYSDISK_REPROBE; +- break; +- case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED: +- switch (state) { +- case MPI_PD_STATE_ONLINE: +- case MPI_PD_STATE_NOT_COMPATIBLE: +- mpt_raid_phys_disk_pg0(ioc, +- raid_event_data->PhysDiskNum, &phys_disk); +- hot_plug_info.id = phys_disk.PhysDiskID; +- hot_plug_info.channel = phys_disk.PhysDiskBus; +- hot_plug_info.event_type = MPTSAS_ADD_PHYSDISK; +- break; +- case MPI_PD_STATE_FAILED: +- case MPI_PD_STATE_MISSING: +- case MPI_PD_STATE_OFFLINE_AT_HOST_REQUEST: +- case MPI_PD_STATE_FAILED_AT_HOST_REQUEST: +- case MPI_PD_STATE_OFFLINE_FOR_ANOTHER_REASON: +- hot_plug_info.event_type = MPTSAS_DEL_PHYSDISK; +- break; +- default: +- break; +- } +- break; +- case MPI_EVENT_RAID_RC_VOLUME_DELETED: +- if (!sdev) +- break; +- vdevice->vtarget->deleted = 1; /* block IO */ +- hot_plug_info.event_type = MPTSAS_DEL_RAID; +- break; +- case MPI_EVENT_RAID_RC_VOLUME_CREATED: +- if (sdev) { +- scsi_device_put(sdev); +- break; +- } +- hot_plug_info.event_type = MPTSAS_ADD_RAID; +- break; +- case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED: +- if (!(status & MPI_RAIDVOL0_STATUS_FLAG_ENABLED)) { +- if (!sdev) +- break; +- vdevice->vtarget->deleted = 1; /* block IO */ +- hot_plug_info.event_type = MPTSAS_DEL_RAID; +- break; +- } +- switch (state) { +- case MPI_RAIDVOL0_STATUS_STATE_FAILED: +- case MPI_RAIDVOL0_STATUS_STATE_MISSING: +- if (!sdev) +- break; +- vdevice->vtarget->deleted = 1; /* block IO */ +- hot_plug_info.event_type = MPTSAS_DEL_RAID; +- break; +- case MPI_RAIDVOL0_STATUS_STATE_OPTIMAL: +- case MPI_RAIDVOL0_STATUS_STATE_DEGRADED: +- if (sdev) { +- scsi_device_put(sdev); +- break; +- } +- hot_plug_info.event_type = MPTSAS_ADD_RAID; +- break; +- default: +- break; +- } +- break; +- default: +- break; +- } +- +- if (hot_plug_info.event_type != MPTSAS_IGNORE_EVENT) +- mptsas_hotplug_work(ioc, fw_event, &hot_plug_info); +- else +- mptsas_free_fw_event(ioc, fw_event); +-} +- +-/** +- * mptsas_issue_tm - send mptsas internal tm request +- * @ioc: Pointer to MPT_ADAPTER structure +- * @type +- * @channel +- * @id +- * @lun +- * @task_context +- * @timeout +- * +- * return: +- * +- **/ +-static int +-mptsas_issue_tm(MPT_ADAPTER *ioc, u8 type, u8 channel, u8 id, u64 lun, +- int task_context, ulong timeout, u8 *issue_reset) +-{ +- MPT_FRAME_HDR *mf; +- SCSITaskMgmt_t *pScsiTm; +- int retval; +- unsigned long timeleft; +- +- *issue_reset = 0; +- if ((mf = mpt_get_msg_frame(mptsasDeviceResetCtx, ioc)) == NULL) { +- retval = -1; /* return failure */ +- dtmprintk(ioc, printk(MYIOC_s_WARN_FMT "TaskMgmt request: no " +- "msg frames!!\n", ioc->name)); +- goto out; +- } +- +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "TaskMgmt request: mr = %p, " +- "task_type = 0x%02X,\n\t timeout = %ld, fw_channel = %d, " +- "fw_id = %d, lun = %lld,\n\t task_context = 0x%x\n", ioc->name, mf, +- type, timeout, channel, id, (unsigned long long)lun, +- task_context)); +- +- pScsiTm = (SCSITaskMgmt_t *) mf; +- memset(pScsiTm, 0, sizeof(SCSITaskMgmt_t)); +- pScsiTm->Function = MPI_FUNCTION_SCSI_TASK_MGMT; +- pScsiTm->TaskType = type; +- pScsiTm->MsgFlags = 0; +- pScsiTm->TargetID = id; +- pScsiTm->Bus = channel; +- pScsiTm->ChainOffset = 0; +- pScsiTm->Reserved = 0; +- pScsiTm->Reserved1 = 0; +- pScsiTm->TaskMsgContext = task_context; +- int_to_scsilun(lun, (struct scsi_lun *)pScsiTm->LUN); +- +- INITIALIZE_MGMT_STATUS(ioc->taskmgmt_cmds.status) +- CLEAR_MGMT_STATUS(ioc->internal_cmds.status) +- retval = 0; +- mpt_put_msg_frame_hi_pri(mptsasDeviceResetCtx, ioc, mf); +- +- /* Now wait for the command to complete */ +- timeleft = wait_for_completion_timeout(&ioc->taskmgmt_cmds.done, +- timeout*HZ); +- if (!(ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { +- retval = -1; /* return failure */ +- dtmprintk(ioc, printk(MYIOC_s_ERR_FMT +- "TaskMgmt request: TIMED OUT!(mr=%p)\n", ioc->name, mf)); +- mpt_free_msg_frame(ioc, mf); +- if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) +- goto out; +- *issue_reset = 1; +- goto out; +- } +- +- if (!(ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_RF_VALID)) { +- retval = -1; /* return failure */ +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "TaskMgmt request: failed with no reply\n", ioc->name)); +- goto out; +- } +- +- out: +- CLEAR_MGMT_STATUS(ioc->taskmgmt_cmds.status) +- return retval; +-} +- +-/** +- * mptsas_broadcast_primative_work - Work queue thread to handle +- * broadcast primitive events +- * @work: work queue payload containing info describing the event +- * +- **/ +-static void +-mptsas_broadcast_primative_work(struct fw_event_work *fw_event) +-{ +- MPT_ADAPTER *ioc = fw_event->ioc; +- MPT_FRAME_HDR *mf; +- VirtDevice *vdevice; +- int ii; +- struct scsi_cmnd *sc; +- SCSITaskMgmtReply_t *pScsiTmReply; +- u8 issue_reset; +- int task_context; +- u8 channel, id; +- int lun; +- u32 termination_count; +- u32 query_count; +- +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "%s - enter\n", ioc->name, __func__)); +- +- mutex_lock(&ioc->taskmgmt_cmds.mutex); +- if (mpt_set_taskmgmt_in_progress_flag(ioc) != 0) { +- mutex_unlock(&ioc->taskmgmt_cmds.mutex); +- mptsas_requeue_fw_event(ioc, fw_event, 1000); +- return; +- } +- +- issue_reset = 0; +- termination_count = 0; +- query_count = 0; +- mpt_findImVolumes(ioc); +- pScsiTmReply = (SCSITaskMgmtReply_t *) ioc->taskmgmt_cmds.reply; +- +- for (ii = 0; ii < ioc->req_depth; ii++) { +- sc = mptscsih_get_scsi_lookup(ioc, ii); +- if (!sc) +- continue; +- mf = MPT_INDEX_2_MFPTR(ioc, ii); +- if (!mf) +- continue; +- task_context = mf->u.frame.hwhdr.msgctxu.MsgContext; +- vdevice = sc->device->hostdata; +- if (!vdevice || !vdevice->vtarget) +- continue; +- if (vdevice->vtarget->tflags & MPT_TARGET_FLAGS_RAID_COMPONENT) +- continue; /* skip hidden raid components */ +- if (vdevice->vtarget->raidVolume) +- continue; /* skip hidden raid components */ +- channel = vdevice->vtarget->channel; +- id = vdevice->vtarget->id; +- lun = vdevice->lun; +- if (mptsas_issue_tm(ioc, MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK, +- channel, id, (u64)lun, task_context, 30, &issue_reset)) +- goto out; +- query_count++; +- termination_count += +- le32_to_cpu(pScsiTmReply->TerminationCount); +- if ((pScsiTmReply->IOCStatus == MPI_IOCSTATUS_SUCCESS) && +- (pScsiTmReply->ResponseCode == +- MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED || +- pScsiTmReply->ResponseCode == +- MPI_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC)) +- continue; +- if (mptsas_issue_tm(ioc, +- MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, +- channel, id, (u64)lun, 0, 30, &issue_reset)) +- goto out; +- termination_count += +- le32_to_cpu(pScsiTmReply->TerminationCount); +- } +- +- out: +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "%s - exit, query_count = %d termination_count = %d\n", +- ioc->name, __func__, query_count, termination_count)); +- +- ioc->broadcast_aen_busy = 0; +- mpt_clear_taskmgmt_in_progress_flag(ioc); +- mutex_unlock(&ioc->taskmgmt_cmds.mutex); +- +- if (issue_reset) { +- printk(MYIOC_s_WARN_FMT "Issuing Reset from %s!!\n", +- ioc->name, __func__); +- if (mpt_SoftResetHandler(ioc, CAN_SLEEP)) +- mpt_HardResetHandler(ioc, CAN_SLEEP); +- } +- mptsas_free_fw_event(ioc, fw_event); +-} +- +-/** +- * mptsas_send_ir2_event - handle exposing hidden disk when an inactive raid volume is added +- * @ioc: Pointer to MPT_ADAPTER structure +- * @ir2_data: +- * +- **/ +-static void +-mptsas_send_ir2_event(struct fw_event_work *fw_event) +-{ +- MPT_ADAPTER *ioc; +- struct mptsas_hotplug_event hot_plug_info; +- MPI_EVENT_DATA_IR2 *ir2_data; +- u8 reasonCode; +- RaidPhysDiskPage0_t phys_disk; +- +- ioc = fw_event->ioc; +- ir2_data = (MPI_EVENT_DATA_IR2 *)fw_event->event_data; +- reasonCode = ir2_data->ReasonCode; +- +- devtprintk(ioc, printk(MYIOC_s_INFO_FMT "Entering %s: " +- "ReasonCode=%02x\n", ioc->name, __func__, reasonCode)); +- +- memset(&hot_plug_info, 0, sizeof(struct mptsas_hotplug_event)); +- hot_plug_info.id = ir2_data->TargetID; +- hot_plug_info.channel = ir2_data->Bus; +- switch (reasonCode) { +- case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED: +- hot_plug_info.event_type = MPTSAS_ADD_INACTIVE_VOLUME; +- break; +- case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED: +- hot_plug_info.phys_disk_num = ir2_data->PhysDiskNum; +- hot_plug_info.event_type = MPTSAS_DEL_PHYSDISK; +- break; +- case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED: +- hot_plug_info.phys_disk_num = ir2_data->PhysDiskNum; +- mpt_raid_phys_disk_pg0(ioc, +- ir2_data->PhysDiskNum, &phys_disk); +- hot_plug_info.id = phys_disk.PhysDiskID; +- hot_plug_info.event_type = MPTSAS_ADD_PHYSDISK; +- break; +- default: +- mptsas_free_fw_event(ioc, fw_event); +- return; +- } +- mptsas_hotplug_work(ioc, fw_event, &hot_plug_info); +-} +- + static void + mptsas_expander_refresh(MPT_ADAPTER *ioc, struct mptsas_portinfo *port_info) + { +@@ -4466,7 +4071,8 @@ + + phy_info = expander->phy_info; + for (i = 0; i < expander->num_phys; i++, phy_info++) { +- if (!(rphy = mptsas_get_rphy(phy_info))) ++ rphy = mptsas_get_rphy(phy_info); ++ if (!rphy) + continue; + if (rphy->identify.device_type == SAS_END_DEVICE) + mptsas_del_end_device(ioc, phy_info); +@@ -4474,7 +4080,8 @@ + + phy_info = expander->phy_info; + for (i = 0; i < expander->num_phys; i++, phy_info++) { +- if (!(rphy = mptsas_get_rphy(phy_info))) ++ rphy = mptsas_get_rphy(phy_info); ++ if (!rphy) + continue; + if (rphy->identify.device_type == + MPI_SAS_DEVICE_INFO_EDGE_EXPANDER || +@@ -4486,7 +4093,11 @@ + continue; + if (port_info == parent) /* backlink rphy */ + continue; +- mptsas_expander_delete(ioc, port_info); ++ /* ++ Delete this expander even if the expdevpage is exists ++ because the parent expander is already deleted ++ */ ++ mptsas_expander_delete(ioc, port_info, 1); + } + } + } +@@ -4496,11 +4107,12 @@ + * mptsas_expander_delete - remove this expander + * @ioc: Pointer to MPT_ADAPTER structure + * @port_info: expander port_info struct +- * +- **/ +- +-static void +-mptsas_expander_delete(MPT_ADAPTER *ioc, struct mptsas_portinfo *port_info) ++ * @force: Flag to forcefully delete the expander ++ * ++ **/ ++ ++static void mptsas_expander_delete(MPT_ADAPTER *ioc, ++ struct mptsas_portinfo *port_info, u8 force) + { + + struct mptsas_portinfo *parent; +@@ -4509,7 +4121,11 @@ + struct mptsas_phyinfo *phy_info; + struct mptsas_portinfo buffer; + struct mptsas_portinfo_details *port_details; ++#if defined(MPT_WIDE_PORT_API) + struct sas_port *port; ++#else ++ struct sas_rphy * rphy; ++#endif + + if (!port_info) + return; +@@ -4522,7 +4138,8 @@ + + if (buffer.num_phys) { + kfree(buffer.phy_info); +- return; ++ if (!force) ++ return; + } + + +@@ -4542,6 +4159,7 @@ + * Delete rphys in the parent that point + * to this expander. + */ ++#if defined(MPT_WIDE_PORT_API) + phy_info = parent->phy_info; + port = NULL; + for (i = 0; i < parent->num_phys; i++, phy_info++) { +@@ -4567,6 +4185,22 @@ + sas_port_delete(port); + mptsas_port_delete(ioc, port_details); + } ++#else ++ phy_info = parent->phy_info; ++ for (i = 0; i < parent->num_phys; i++, phy_info++) { ++ rphy = mptsas_get_rphy(phy_info); ++ if (!rphy) ++ continue; ++ if (phy_info->attached.sas_address != ++ expander_sas_address) ++ continue; ++ dev_printk(KERN_DEBUG, &rphy->dev, ++ MYIOC_s_FMT "delete: sas_addr (0x%llx)\n", ++ ioc->name, (unsigned long long) expander_sas_address); ++ sas_rphy_delete(rphy); ++ mptsas_port_delete(ioc, port_details); ++ } ++#endif + out: + + printk(MYIOC_s_INFO_FMT "delete expander: num_phys %d, " +@@ -4604,6 +4238,7 @@ + expander_data = (MpiEventDataSasExpanderStatusChange_t *) + fw_event->event_data; + memcpy(&sas_address, &expander_data->SASAddress, sizeof(__le64)); ++ sas_address = le64_to_cpu(sas_address); + port_info = mptsas_find_portinfo_by_sas_address(ioc, sas_address); + + if (expander_data->ReasonCode == MPI_EVENT_SAS_EXP_RC_ADDED) { +@@ -4622,7 +4257,7 @@ + mptsas_expander_event_add(ioc, expander_data); + } else if (expander_data->ReasonCode == + MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING) +- mptsas_expander_delete(ioc, port_info); ++ mptsas_expander_delete(ioc, port_info, 0); + + mptsas_free_fw_event(ioc, fw_event); + } +@@ -4724,6 +4359,258 @@ + mptsas_free_fw_event(ioc, fw_event); + } + ++static void ++mptsas_not_responding_devices(MPT_ADAPTER *ioc) ++{ ++ struct mptsas_portinfo buffer, *port_info; ++ struct sas_device_info *sas_info; ++ struct mptsas_devinfo sas_device; ++ u32 handle; ++ VirtTarget *vtarget = NULL; ++ struct mptsas_phyinfo *phy_info; ++ u8 found_expander; ++ int retval, retry_count; ++ unsigned long flags; ++ ++ if (ioc->disable_hotplug_remove) ++ return; ++ ++ mpt_findImVolumes(ioc); ++ ++ spin_lock_irqsave(&ioc->taskmgmt_lock, flags); ++ if (ioc->ioc_reset_in_progress) { ++ dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "%s: exiting due to a parallel reset \n", ioc->name, ++ __func__)); ++ spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); ++ return; ++ } ++ spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); ++ ++ /* devices, logical volumes */ ++ redo_device_scan: ++ list_for_each_entry(sas_info, &ioc->sas_device_info_list, list) { ++ if (sas_info->is_cached) ++ continue; ++ if (!sas_info->is_logical_volume) { ++ sas_device.handle = 0; ++ retry_count = 0; ++retry_page: ++ retval = mptsas_sas_device_pg0(ioc, &sas_device, ++ (MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID ++ << MPI_SAS_DEVICE_PGAD_FORM_SHIFT), ++ (sas_info->fw.channel << 8) + ++ sas_info->fw.id); ++ ++ if (sas_device.handle) ++ continue; ++ if (retval == -EBUSY) { ++ spin_lock_irqsave(&ioc->taskmgmt_lock, flags); ++ if (ioc->ioc_reset_in_progress) { ++ dfailprintk(ioc, ++ printk(MYIOC_s_DEBUG_FMT ++ "%s: exiting due to reset\n", ++ ioc->name, __func__)); ++ spin_unlock_irqrestore ++ (&ioc->taskmgmt_lock, flags); ++ return; ++ } ++ spin_unlock_irqrestore(&ioc->taskmgmt_lock, ++ flags); ++ } ++ ++ if (retval && (retval != -ENODEV)) { ++ if (retry_count < 10) { ++ retry_count++; ++ goto retry_page; ++ } else { ++ devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "%s: Config page retry exceeded retry " ++ "count deleting device 0x%llx\n", ++ ioc->name, __func__, ++ sas_info->sas_address)); ++ } ++ } ++ ++ /* delete device */ ++ vtarget = mptsas_find_vtarget(ioc, ++ sas_info->fw.channel, sas_info->fw.id); ++ if (vtarget) ++ vtarget->deleted = 1; ++ phy_info = mptsas_find_phyinfo_by_sas_address(ioc, ++ sas_info->sas_address); ++ if (phy_info) { ++ mptsas_del_end_device(ioc, phy_info); ++ goto redo_device_scan; ++ } ++ } else ++ mptsas_volume_delete(ioc, sas_info->fw.id); ++ } ++ ++ /* expanders */ ++ redo_expander_scan: ++ list_for_each_entry(port_info, &ioc->sas_topology, list) { ++ ++ if (port_info->phy_info && ++ (!(port_info->phy_info[0].identify.device_info & ++ MPI_SAS_DEVICE_INFO_SMP_TARGET))) ++ continue; ++ found_expander = 0; ++ handle = 0xFFFF; ++ while (!mptsas_sas_expander_pg0(ioc, &buffer, ++ (MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE << ++ MPI_SAS_EXPAND_PGAD_FORM_SHIFT), handle) && ++ !found_expander) { ++ ++ handle = buffer.phy_info[0].handle; ++ if (buffer.phy_info[0].identify.sas_address == ++ port_info->phy_info[0].identify.sas_address) { ++ found_expander = 1; ++ } ++ kfree(buffer.phy_info); ++ } ++ ++ if (!found_expander) { ++ mptsas_expander_delete(ioc, port_info, 0); ++ goto redo_expander_scan; ++ } ++ } ++} ++ ++/** ++ * mptsas_probe_expanders - adding expanders ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * ++ **/ ++static void ++mptsas_probe_expanders(MPT_ADAPTER *ioc) ++{ ++ struct mptsas_portinfo buffer, *port_info; ++ u32 handle; ++ int i; ++ ++ handle = 0xFFFF; ++ while (!mptsas_sas_expander_pg0(ioc, &buffer, ++ (MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE << ++ MPI_SAS_EXPAND_PGAD_FORM_SHIFT), handle)) { ++ ++ handle = buffer.phy_info[0].handle; ++ port_info = mptsas_find_portinfo_by_sas_address(ioc, ++ buffer.phy_info[0].identify.sas_address); ++ ++ if (port_info) { ++ /* refreshing handles */ ++ for (i = 0; i < buffer.num_phys; i++) { ++ port_info->phy_info[i].handle = handle; ++ port_info->phy_info[i].identify.handle_parent = ++ buffer.phy_info[0].identify.handle_parent; ++ } ++ mptsas_expander_refresh(ioc, port_info); ++ kfree(buffer.phy_info); ++ continue; ++ } ++ ++ port_info = kzalloc(sizeof(struct mptsas_portinfo), GFP_KERNEL); ++ if (!port_info) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: exit at line=%d\n", ioc->name, ++ __func__, __LINE__)); ++ return; ++ } ++ port_info->num_phys = buffer.num_phys; ++ port_info->phy_info = buffer.phy_info; ++ for (i = 0; i < port_info->num_phys; i++) ++ port_info->phy_info[i].portinfo = port_info; ++ mutex_lock(&ioc->sas_topology_mutex); ++ list_add_tail(&port_info->list, &ioc->sas_topology); ++ mutex_unlock(&ioc->sas_topology_mutex); ++ printk(MYIOC_s_INFO_FMT "add expander: num_phys %d, " ++ "sas_addr (0x%llx)\n", ioc->name, port_info->num_phys, ++ (unsigned long long)buffer.phy_info[0].identify.sas_address); ++ mptsas_expander_refresh(ioc, port_info); ++ } ++} ++ ++static void ++mptsas_probe_devices(MPT_ADAPTER *ioc) ++{ ++ u16 retry_count; ++ u16 handle; ++ struct mptsas_devinfo sas_device; ++ struct mptsas_phyinfo *phy_info; ++ enum device_state state; ++ ++ handle = 0xFFFF; ++ while (!(mptsas_sas_device_pg0(ioc, &sas_device, ++ MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE, handle))) { ++ ++ handle = sas_device.handle; ++ ++ if ((sas_device.device_info & ++ (MPI_SAS_DEVICE_INFO_SSP_TARGET | ++ MPI_SAS_DEVICE_INFO_STP_TARGET | ++ MPI_SAS_DEVICE_INFO_SATA_DEVICE)) == 0) ++ continue; ++ ++ phy_info = mptsas_refreshing_device_handles(ioc, &sas_device); ++ if (!phy_info) ++ continue; ++ ++ if (mptsas_get_rphy(phy_info)) ++ continue; ++ ++ state = DEVICE_RETRY; ++ retry_count = 0; ++ while(state == DEVICE_RETRY) { ++ state = mptsas_test_unit_ready(ioc, sas_device.channel, ++ sas_device.id, retry_count++); ++ ssleep(1); ++ } ++ if (state == DEVICE_READY) ++ mptsas_add_end_device(ioc, phy_info); ++ else ++ memset(&phy_info->attached, 0, sizeof(struct mptsas_devinfo)); ++ } ++} ++ ++/** ++ * mptsas_scan_sas_topology - ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * @sas_address: ++ * ++ **/ ++static void ++mptsas_scan_sas_topology(MPT_ADAPTER *ioc) ++{ ++ struct scsi_device *sdev; ++ int i; ++ ++ mptsas_probe_hba_phys(ioc); ++ mptsas_probe_expanders(ioc); ++ mptsas_probe_devices(ioc); ++ ++ /* ++ Reporting RAID volumes. ++ */ ++ if (!ioc->ir_firmware || !ioc->raid_data.pIocPg2 || ++ !ioc->raid_data.pIocPg2->NumActiveVolumes) ++ return; ++ for (i = 0; i < ioc->raid_data.pIocPg2->NumActiveVolumes; i++) { ++ sdev = scsi_device_lookup(ioc->sh, MPTSAS_RAID_CHANNEL, ++ ioc->raid_data.pIocPg2->RaidVolume[i].VolumeID, 0); ++ if (sdev) { ++ scsi_device_put(sdev); ++ continue; ++ } ++ printk(MYIOC_s_INFO_FMT "attaching raid volume, channel %d, " ++ "id %d\n", ioc->name, MPTSAS_RAID_CHANNEL, ++ ioc->raid_data.pIocPg2->RaidVolume[i].VolumeID); ++ scsi_add_device(ioc->sh, MPTSAS_RAID_CHANNEL, ++ ioc->raid_data.pIocPg2->RaidVolume[i].VolumeID, 0); ++ } ++} ++ ++ + + static void + mptsas_handle_queue_full_event(struct fw_event_work *fw_event) +@@ -4744,9 +4631,9 @@ + fw_id = qfull_data->TargetID; + fw_channel = qfull_data->Bus; + current_depth = le16_to_cpu(qfull_data->CurrentDepth); +- ++ + /* if hidden raid component, look for the volume id */ +- mutex_lock(&ioc->sas_device_info_mutex); ++ down(&ioc->sas_device_info_mutex); + if (mptscsih_is_phys_disk(ioc, fw_channel, fw_id)) { + list_for_each_entry(sas_info, &ioc->sas_device_info_list, + list) { +@@ -4779,8 +4666,8 @@ + } + + out: +- mutex_unlock(&ioc->sas_device_info_mutex); +- ++ up(&ioc->sas_device_info_mutex); ++ + if (id != -1) { + shost_for_each_device(sdev, ioc->sh) { + if (sdev->id == id && sdev->channel == channel) { +@@ -4800,8 +4687,8 @@ + depth); + else if (depth < 0) + sdev_printk(KERN_INFO, sdev, +- "Tagged Command Queueing is being " +- "disabled\n"); ++ "Tagged Command Queueing is being " ++ "disabled\n"); + else if (depth == 0) + sdev_printk(KERN_INFO, sdev, + "Queue depth not changed yet\n"); +@@ -4812,67 +4699,870 @@ + mptsas_free_fw_event(ioc, fw_event); + } + +-/** +- * mptsas_firmware_event_work - work thread for processing fw events +- * @work: work queue payload containing info describing the event +- * Context: user +- * +- */ +-static void +-mptsas_firmware_event_work(struct work_struct *work) +-{ +- struct fw_event_work *fw_event = +- container_of(work, struct fw_event_work, work.work); +- MPT_ADAPTER *ioc = fw_event->ioc; +- +- /* special rescan topology handling */ +- if (fw_event->event == -1) { +- devtprintk(ioc, printk(MYIOC_s_INFO_FMT "%s: rescan after " +- "reset\n", ioc->name, __func__)); +- mptsas_not_responding_devices(ioc); +- mptsas_scan_sas_topology(ioc); +- mptsas_free_fw_event(ioc, fw_event); +- return; +- } +- +- /* events handling turned off during host reset */ +- if (ioc->fw_events_off) { +- mptsas_free_fw_event(ioc, fw_event); +- return; +- } +- +- devtprintk(ioc, printk(MYIOC_s_INFO_FMT "%s: fw_event=(0x%p), " +- "event = (0x%02x)\n", ioc->name, __func__, fw_event, +- (fw_event->event & 0xFF))); +- +- switch (fw_event->event) { +- case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE: +- mptsas_send_sas_event(fw_event); +- break; +- case MPI_EVENT_INTEGRATED_RAID: +- mptsas_send_raid_event(fw_event); +- break; +- case MPI_EVENT_IR2: +- mptsas_send_ir2_event(fw_event); +- break; +- case MPI_EVENT_PERSISTENT_TABLE_FULL: ++ ++/** ++ * mptsas_find_phyinfo_by_sas_address - ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * @sas_address: ++ * ++ **/ ++static struct mptsas_phyinfo * ++mptsas_find_phyinfo_by_sas_address(MPT_ADAPTER *ioc, u64 sas_address) ++{ ++ struct mptsas_portinfo *port_info; ++ struct mptsas_phyinfo *phy_info = NULL; ++ int i; ++ ++ mutex_lock(&ioc->sas_topology_mutex); ++ list_for_each_entry(port_info, &ioc->sas_topology, list) { ++ for (i = 0; i < port_info->num_phys; i++) { ++ if (!mptsas_is_end_device( ++ &port_info->phy_info[i].attached)) ++ continue; ++ if (port_info->phy_info[i].attached.sas_address ++ != sas_address) ++ continue; ++ phy_info = &port_info->phy_info[i]; ++ break; ++ } ++ } ++ mutex_unlock(&ioc->sas_topology_mutex); ++ return phy_info; ++} ++ ++ ++/** ++ * mptsas_find_phyinfo_by_phys_disk_num - ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * @phys_disk_num: ++ * @channel: ++ * @id: ++ * ++ **/ ++static struct mptsas_phyinfo * ++mptsas_find_phyinfo_by_phys_disk_num(MPT_ADAPTER *ioc, u8 phys_disk_num, ++ u8 channel, u8 id) ++{ ++ struct mptsas_phyinfo *phy_info = NULL; ++ struct mptsas_portinfo *port_info; ++ RaidPhysDiskPage1_t *phys_disk = NULL; ++ int num_paths; ++ u64 sas_address = 0; ++ int i; ++ ++ phy_info = NULL; ++ if (!ioc->raid_data.pIocPg3) ++ return NULL; ++ /* dual port support */ ++ num_paths = mpt_raid_phys_disk_get_num_paths(ioc, phys_disk_num); ++ if (!num_paths) ++ goto out; ++ phys_disk = kzalloc(offsetof(RaidPhysDiskPage1_t,Path) + ++ (num_paths * sizeof(RAID_PHYS_DISK1_PATH)), GFP_KERNEL); ++ if (!phys_disk) ++ goto out; ++ mpt_raid_phys_disk_pg1(ioc, phys_disk_num, phys_disk); ++ for (i = 0; i < num_paths; i++) { ++ if ((phys_disk->Path[i].Flags & 1) != 0) ++ /* entry no longer valid */ ++ continue; ++ if ((id == phys_disk->Path[i].PhysDiskID) && ++ (channel == phys_disk->Path[i].PhysDiskBus)) { ++ memcpy(&sas_address, &phys_disk->Path[i].WWID, ++ sizeof(u64)); ++ phy_info = mptsas_find_phyinfo_by_sas_address(ioc, sas_address); ++ goto out; ++ } ++ } ++ ++ out: ++ kfree(phys_disk); ++ if (phy_info) ++ return phy_info; ++ ++ /* ++ * Extra code to handle RAID0 case, where the sas_address is not updated ++ * in phys_disk_page_1 when hotswapped ++ */ ++ mutex_lock(&ioc->sas_topology_mutex); ++ list_for_each_entry(port_info, &ioc->sas_topology, list) { ++ for (i = 0; i < port_info->num_phys && !phy_info; i++) { ++ if (!mptsas_is_end_device( ++ &port_info->phy_info[i].attached)) ++ continue; ++ if (port_info->phy_info[i].attached.phys_disk_num == ~0) ++ continue; ++ if (port_info->phy_info[i].attached.phys_disk_num == phys_disk_num && ++ port_info->phy_info[i].attached.id == id && ++ port_info->phy_info[i].attached.channel == channel) ++ phy_info = &port_info->phy_info[i]; ++ } ++ } ++ mutex_unlock(&ioc->sas_topology_mutex); ++ return phy_info; ++} ++ ++/** ++ * mptsas_reprobe_lun - ++ * @sdev: ++ * @data: ++ * ++ **/ ++static void ++mptsas_reprobe_lun(struct scsi_device *sdev, void *data) ++{ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++ int rc; ++#endif ++ sdev->no_uld_attach = data ? 1 : 0; ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++ rc = scsi_device_reprobe(sdev); ++#else ++ scsi_device_reprobe(sdev); ++#endif ++} ++ ++/** ++ * mptsas_reprobe_target - ++ * @starget: ++ * @uld_attach: ++ * ++ **/ ++static void ++mptsas_reprobe_target(struct scsi_target *starget, int uld_attach) ++{ ++ starget_for_each_device(starget, uld_attach ? (void *)1 : NULL, ++ mptsas_reprobe_lun); ++} ++ ++/** ++ * mptsas_adding_inactive_raid_components - ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * @channel: ++ * @id: ++ * ++ * ++ * TODO: check for hotspares ++ **/ ++static void ++mptsas_adding_inactive_raid_components(MPT_ADAPTER *ioc, u8 channel, u8 id) ++{ ++ CONFIGPARMS cfg; ++ ConfigPageHeader_t hdr; ++ dma_addr_t dma_handle; ++ pRaidVolumePage0_t buffer = NULL; ++ RaidPhysDiskPage0_t phys_disk; ++ int i; ++ struct mptsas_phyinfo *phy_info; ++ struct mptsas_devinfo sas_device; ++ ++ memset(&cfg, 0 , sizeof(CONFIGPARMS)); ++ memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); ++ hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME; ++ cfg.pageAddr = (channel << 8) + id; ++ cfg.cfghdr.hdr = &hdr; ++ cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; ++ cfg.timeout = SAS_CONFIG_PAGE_TIMEOUT; ++ ++ if (mpt_config(ioc, &cfg) != 0) ++ goto out; ++ ++ if (!hdr.PageLength) ++ goto out; ++ ++ buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, ++ &dma_handle); ++ ++ if (!buffer) ++ goto out; ++ ++ cfg.physAddr = dma_handle; ++ cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; ++ ++ if (mpt_config(ioc, &cfg) != 0) ++ goto out; ++ ++ if (!(buffer->VolumeStatus.Flags & ++ MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE)) ++ goto out; ++ ++ if (!buffer->NumPhysDisks) ++ goto out; ++ ++ for (i = 0; i < buffer->NumPhysDisks; i++) { ++ ++ if (mpt_raid_phys_disk_pg0(ioc, ++ buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0) ++ continue; ++ ++ if (mptsas_sas_device_pg0(ioc, &sas_device, ++ (MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID << ++ MPI_SAS_DEVICE_PGAD_FORM_SHIFT), ++ (phys_disk.PhysDiskBus << 8) + ++ phys_disk.PhysDiskID)) ++ continue; ++ ++ phy_info = mptsas_find_phyinfo_by_sas_address(ioc, ++ sas_device.sas_address); ++ mptsas_add_end_device(ioc, phy_info); ++ } ++ ++ out: ++ if (buffer) ++ pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer, ++ dma_handle); ++} ++/* ++ * Work queue thread to handle SAS hotplug events ++ */ ++static void ++mptsas_hotplug_work(MPT_ADAPTER *ioc, struct fw_event_work *fw_event, ++ struct mptsas_hotplug_event *hot_plug_info) ++{ ++ struct mptsas_phyinfo *phy_info; ++ struct scsi_target * starget; ++ struct mptsas_devinfo sas_device; ++ VirtTarget *vtarget; ++ enum device_state state; ++ int i; ++ ++ switch (hot_plug_info->event_type) { ++ ++ case MPTSAS_ADD_PHYSDISK: ++ ++ if (!ioc->raid_data.pIocPg2) ++ break; ++ ++ for (i = 0; i < ioc->raid_data.pIocPg2->NumActiveVolumes; i++) { ++ if (ioc->raid_data.pIocPg2->RaidVolume[i].VolumeID == ++ hot_plug_info->id) { ++ printk(MYIOC_s_WARN_FMT "firmware bug: unable " ++ "to add hidden disk - target_id matchs " ++ "volume_id\n", ioc->name); ++ mptsas_free_fw_event(ioc, fw_event); ++ return; ++ } ++ } ++ mpt_findImVolumes(ioc); ++ ++ case MPTSAS_ADD_DEVICE: ++ memset(&sas_device, 0, sizeof(struct mptsas_devinfo)); ++ mptsas_sas_device_pg0(ioc, &sas_device, ++ (MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID << ++ MPI_SAS_DEVICE_PGAD_FORM_SHIFT), ++ (hot_plug_info->channel << 8) + ++ hot_plug_info->id); ++ ++ if (!sas_device.handle) ++ return; ++ ++ phy_info = mptsas_refreshing_device_handles(ioc, &sas_device); ++ if (!phy_info) ++ break; ++ ++ if (mptsas_get_rphy(phy_info)) ++ break; ++ ++ state = mptsas_test_unit_ready(ioc, phy_info->attached.channel, ++ phy_info->attached.id, fw_event->retries); ++ ++ if (state == DEVICE_RETRY && !ioc->fw_events_off) { ++ mptsas_requeue_fw_event(ioc, fw_event, 1000); ++ return; ++ } ++ ++ if (state == DEVICE_READY) ++ mptsas_add_end_device(ioc, phy_info); ++ else ++ memset(&phy_info->attached, 0, sizeof(struct mptsas_devinfo)); ++ break; ++ ++ case MPTSAS_DEL_DEVICE: ++ ++ if (!ioc->disable_hotplug_remove) { ++ phy_info = mptsas_find_phyinfo_by_sas_address(ioc, ++ hot_plug_info->sas_address); ++ mptsas_del_end_device(ioc, phy_info); ++ } ++ break; ++ ++ case MPTSAS_DEL_PHYSDISK: ++ ++ mpt_findImVolumes(ioc); ++ ++ phy_info = mptsas_find_phyinfo_by_phys_disk_num( ++ ioc, hot_plug_info->phys_disk_num, hot_plug_info->channel, ++ hot_plug_info->id); ++ mptsas_del_end_device(ioc, phy_info); ++ break; ++ ++ case MPTSAS_ADD_PHYSDISK_REPROBE: ++ ++ if (mptsas_sas_device_pg0(ioc, &sas_device, ++ (MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID << ++ MPI_SAS_DEVICE_PGAD_FORM_SHIFT), ++ (hot_plug_info->channel << 8) + hot_plug_info->id)) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, hot_plug_info->id, __LINE__)); ++ break; ++ } ++ ++ phy_info = mptsas_find_phyinfo_by_sas_address( ++ ioc, sas_device.sas_address); ++ ++ if (!phy_info) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, hot_plug_info->id, __LINE__)); ++ break; ++ } ++ ++ starget = mptsas_get_starget(phy_info); ++ if (!starget) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, hot_plug_info->id, __LINE__)); ++ break; ++ } ++ ++ vtarget = starget->hostdata; ++ if (!vtarget) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, hot_plug_info->id, __LINE__)); ++ break; ++ } ++ ++ mpt_findImVolumes(ioc); ++ ++ starget_printk(KERN_INFO, starget, MYIOC_s_FMT "RAID Hidding: " ++ "fw_channel=%d, fw_id=%d, physdsk %d, sas_addr 0x%llx\n", ++ ioc->name, hot_plug_info->channel, hot_plug_info->id, ++ hot_plug_info->phys_disk_num, (unsigned long long) ++ sas_device.sas_address); ++ ++ vtarget->id = hot_plug_info->phys_disk_num; ++ vtarget->tflags |= MPT_TARGET_FLAGS_RAID_COMPONENT; ++ phy_info->attached.phys_disk_num = hot_plug_info->phys_disk_num; ++ mptsas_reprobe_target(starget, 1); ++ break; ++ ++ case MPTSAS_DEL_PHYSDISK_REPROBE: ++ ++ if (mptsas_sas_device_pg0(ioc, &sas_device, ++ (MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID << ++ MPI_SAS_DEVICE_PGAD_FORM_SHIFT), ++ (hot_plug_info->channel << 8) + hot_plug_info->id)) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ++ ioc->name, __func__, ++ hot_plug_info->id, __LINE__)); ++ break; ++ } ++ ++ phy_info = mptsas_find_phyinfo_by_sas_address(ioc, ++ sas_device.sas_address); ++ if (!phy_info) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, hot_plug_info->id, __LINE__)); ++ break; ++ } ++ ++ starget = mptsas_get_starget(phy_info); ++ if (!starget) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, hot_plug_info->id, __LINE__)); ++ break; ++ } ++ ++ vtarget = starget->hostdata; ++ if (!vtarget) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, hot_plug_info->id, __LINE__)); ++ break; ++ } ++ ++ if (!(vtarget->tflags & MPT_TARGET_FLAGS_RAID_COMPONENT)) { ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "%s: fw_id=%d exit at line=%d\n", ioc->name, ++ __func__, hot_plug_info->id, __LINE__)); ++ break; ++ } ++ ++ mpt_findImVolumes(ioc); ++ ++ starget_printk(KERN_INFO, starget, MYIOC_s_FMT "RAID Exposing:" ++ " fw_channel=%d, fw_id=%d, physdsk %d, sas_addr 0x%llx\n", ++ ioc->name, hot_plug_info->channel, hot_plug_info->id, ++ hot_plug_info->phys_disk_num, (unsigned long long) ++ sas_device.sas_address); ++ ++ vtarget->tflags &= ~MPT_TARGET_FLAGS_RAID_COMPONENT; ++ vtarget->id = hot_plug_info->id; ++ phy_info->attached.phys_disk_num = ~0; ++ mptsas_reprobe_target(starget, 0); ++ mptsas_add_device_component_by_fw(ioc, ++ hot_plug_info->channel, hot_plug_info->id); ++ break; ++ ++ case MPTSAS_ADD_RAID: ++ ++ mpt_findImVolumes(ioc); ++ printk(MYIOC_s_INFO_FMT "attaching raid volume, channel %d, " ++ "id %d\n", ioc->name, MPTSAS_RAID_CHANNEL, ++ hot_plug_info->id); ++ scsi_add_device(ioc->sh, MPTSAS_RAID_CHANNEL, ++ hot_plug_info->id, 0); ++ break; ++ ++ case MPTSAS_DEL_RAID: ++ ++ mpt_findImVolumes(ioc); ++ printk(MYIOC_s_INFO_FMT "removing raid volume, channel %d, " ++ "id %d\n", ioc->name, MPTSAS_RAID_CHANNEL, ++ hot_plug_info->id); ++ scsi_remove_device(hot_plug_info->sdev); ++ scsi_device_put(hot_plug_info->sdev); ++ break; ++ ++ case MPTSAS_ADD_INACTIVE_VOLUME: ++ ++ mpt_findImVolumes(ioc); ++ mptsas_adding_inactive_raid_components(ioc, ++ hot_plug_info->channel, hot_plug_info->id); ++ break; ++ ++ default: ++ break; ++ } ++ ++ mptsas_free_fw_event(ioc, fw_event); ++} ++ ++/** ++ * mptsas_send_sas_event ++ * ++ * ++ * @ioc ++ * @sas_event_data ++ * ++ **/ ++static void ++mptsas_send_sas_event(struct fw_event_work *fw_event) ++{ ++ MPT_ADAPTER *ioc; ++ struct mptsas_hotplug_event hot_plug_info; ++ EVENT_DATA_SAS_DEVICE_STATUS_CHANGE *sas_event_data; ++ u32 device_info; ++ u64 sas_address; ++ ++ ioc = fw_event->ioc; ++ sas_event_data = (EVENT_DATA_SAS_DEVICE_STATUS_CHANGE *) ++ fw_event->event_data; ++ device_info = le32_to_cpu(sas_event_data->DeviceInfo); ++ ++ if ((device_info & ++ (MPI_SAS_DEVICE_INFO_SSP_TARGET | ++ MPI_SAS_DEVICE_INFO_STP_TARGET | ++ MPI_SAS_DEVICE_INFO_SATA_DEVICE)) == 0) { ++ mptsas_free_fw_event(ioc, fw_event); ++ return; ++ } ++ ++ if (sas_event_data->ReasonCode == ++ MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED) { ++ mptbase_sas_persist_operation(ioc, ++ MPI_SAS_OP_CLEAR_NOT_PRESENT); ++ mptsas_free_fw_event(ioc, fw_event); ++ return; ++ } ++ ++ switch (sas_event_data->ReasonCode) { ++ case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING: ++ case MPI_EVENT_SAS_DEV_STAT_RC_ADDED: ++ memset(&hot_plug_info, 0, sizeof(struct mptsas_hotplug_event)); ++ hot_plug_info.handle = le16_to_cpu(sas_event_data->DevHandle); ++ hot_plug_info.channel = sas_event_data->Bus; ++ hot_plug_info.id = sas_event_data->TargetID; ++ hot_plug_info.phy_id = sas_event_data->PhyNum; ++ memcpy(&sas_address, &sas_event_data->SASAddress, ++ sizeof(u64)); ++ hot_plug_info.sas_address = le64_to_cpu(sas_address); ++ hot_plug_info.device_info = device_info; ++ if (sas_event_data->ReasonCode & ++ MPI_EVENT_SAS_DEV_STAT_RC_ADDED) ++ hot_plug_info.event_type = MPTSAS_ADD_DEVICE; ++ else ++ hot_plug_info.event_type = MPTSAS_DEL_DEVICE; ++ mptsas_hotplug_work(ioc, fw_event, &hot_plug_info); ++ break; ++ ++ case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED: + mptbase_sas_persist_operation(ioc, + MPI_SAS_OP_CLEAR_NOT_PRESENT); + mptsas_free_fw_event(ioc, fw_event); + break; +- case MPI_EVENT_SAS_BROADCAST_PRIMITIVE: +- mptsas_broadcast_primative_work(fw_event); +- break; +- case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE: +- mptsas_send_expander_event(fw_event); +- break; +- case MPI_EVENT_SAS_PHY_LINK_STATUS: +- mptsas_send_link_status_event(fw_event); +- break; +- case MPI_EVENT_QUEUE_FULL: +- mptsas_handle_queue_full_event(fw_event); +- break; +- } ++ ++ case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA: ++ /* TODO */ ++ case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: ++ /* TODO */ ++ default: ++ mptsas_free_fw_event(ioc, fw_event); ++ break; ++ } ++} ++ ++ ++/** ++ * mptsas_send_raid_event ++ * ++ * ++ * @ioc ++ * @raid_event_data ++ * ++ **/ ++static void ++mptsas_send_raid_event(struct fw_event_work *fw_event) ++{ ++ MPT_ADAPTER *ioc; ++ EVENT_DATA_RAID *raid_event_data; ++ struct mptsas_hotplug_event hot_plug_info; ++ int status; ++ int state; ++ struct scsi_device *sdev = NULL; ++ VirtDevice *vdevice = NULL; ++ RaidPhysDiskPage0_t phys_disk; ++ ++ ioc = fw_event->ioc; ++ raid_event_data = (EVENT_DATA_RAID *)fw_event->event_data; ++ status = le32_to_cpu(raid_event_data->SettingsStatus); ++ state = (status >> 8) & 0xff; ++ ++ memset(&hot_plug_info, 0, sizeof(struct mptsas_hotplug_event)); ++ hot_plug_info.id = raid_event_data->VolumeID; ++ hot_plug_info.channel = raid_event_data->VolumeBus; ++ hot_plug_info.phys_disk_num = raid_event_data->PhysDiskNum; ++ ++ if (raid_event_data->ReasonCode == MPI_EVENT_RAID_RC_VOLUME_DELETED || ++ raid_event_data->ReasonCode == MPI_EVENT_RAID_RC_VOLUME_CREATED || ++ raid_event_data->ReasonCode == ++ MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED) { ++ sdev = scsi_device_lookup(ioc->sh, MPTSAS_RAID_CHANNEL, ++ hot_plug_info.id, 0); ++ hot_plug_info.sdev = sdev; ++ if (sdev) ++ vdevice = sdev->hostdata; ++ } ++ ++ devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Entering %s: " ++ "ReasonCode=%02x\n", ioc->name, __func__, ++ raid_event_data->ReasonCode)); ++ ++ switch (raid_event_data->ReasonCode) { ++ case MPI_EVENT_RAID_RC_PHYSDISK_DELETED: ++ hot_plug_info.event_type = MPTSAS_DEL_PHYSDISK_REPROBE; ++ break; ++ case MPI_EVENT_RAID_RC_PHYSDISK_CREATED: ++ hot_plug_info.event_type = MPTSAS_ADD_PHYSDISK_REPROBE; ++ break; ++ case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED: ++ switch (state) { ++ case MPI_PD_STATE_ONLINE: ++ case MPI_PD_STATE_NOT_COMPATIBLE: ++ mpt_raid_phys_disk_pg0(ioc, ++ raid_event_data->PhysDiskNum, &phys_disk); ++ hot_plug_info.id = phys_disk.PhysDiskID; ++ hot_plug_info.channel = phys_disk.PhysDiskBus; ++ hot_plug_info.event_type = MPTSAS_ADD_PHYSDISK; ++ break; ++ case MPI_PD_STATE_FAILED: ++ case MPI_PD_STATE_MISSING: ++ case MPI_PD_STATE_OFFLINE_AT_HOST_REQUEST: ++ case MPI_PD_STATE_FAILED_AT_HOST_REQUEST: ++ case MPI_PD_STATE_OFFLINE_FOR_ANOTHER_REASON: ++ hot_plug_info.event_type = MPTSAS_DEL_PHYSDISK; ++ break; ++ default: ++ break; ++ } ++ break; ++ case MPI_EVENT_RAID_RC_VOLUME_DELETED: ++ if (!sdev) ++ break; ++ vdevice->vtarget->deleted = 1; /* block IO */ ++ hot_plug_info.event_type = MPTSAS_DEL_RAID; ++ break; ++ case MPI_EVENT_RAID_RC_VOLUME_CREATED: ++ if (sdev) { ++ scsi_device_put(sdev); ++ break; ++ } ++ hot_plug_info.event_type = MPTSAS_ADD_RAID; ++ break; ++ case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED: ++ if (!(status & MPI_RAIDVOL0_STATUS_FLAG_ENABLED)) { ++ if (!sdev) ++ break; ++ vdevice->vtarget->deleted = 1; /* block IO */ ++ hot_plug_info.event_type = MPTSAS_DEL_RAID; ++ break; ++ } ++ switch (state) { ++ case MPI_RAIDVOL0_STATUS_STATE_FAILED: ++ case MPI_RAIDVOL0_STATUS_STATE_MISSING: ++ if (!sdev) ++ break; ++ vdevice->vtarget->deleted = 1; /* block IO */ ++ hot_plug_info.event_type = MPTSAS_DEL_RAID; ++ break; ++ case MPI_RAIDVOL0_STATUS_STATE_OPTIMAL: ++ case MPI_RAIDVOL0_STATUS_STATE_DEGRADED: ++ if (sdev) { ++ scsi_device_put(sdev); ++ break; ++ } ++ hot_plug_info.event_type = MPTSAS_ADD_RAID; ++ break; ++ default: ++ break; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ if (hot_plug_info.event_type != MPTSAS_IGNORE_EVENT) ++ mptsas_hotplug_work(ioc, fw_event, &hot_plug_info); ++ else ++ mptsas_free_fw_event(ioc, fw_event); ++} ++ ++/** ++ * mptsas_issue_tm - send mptsas internal tm request ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * @type ++ * @channel ++ * @id ++ * @lun ++ * @task_context ++ * @timeout ++ * ++ * return: ++ * ++ **/ ++static int ++mptsas_issue_tm(MPT_ADAPTER *ioc, u8 type, u8 channel, u8 id, u64 lun, int task_context, ulong timeout, ++ u8 *issue_reset) ++{ ++ MPT_FRAME_HDR *mf; ++ SCSITaskMgmt_t *pScsiTm; ++ int retval; ++ unsigned long timeleft; ++ ++ *issue_reset = 0; ++ if ((mf = mpt_get_msg_frame(mptsasDeviceResetCtx, ioc)) == NULL) { ++ retval = -1; /* return failure */ ++ dtmprintk(ioc, printk(MYIOC_s_WARN_FMT "TaskMgmt request: no " ++ "msg frames!!\n", ioc->name)); ++ goto out; ++ } ++ ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "TaskMgmt request: mr = %p, " ++ "task_type = 0x%02X,\n\t timeout = %ld, fw_channel = %d, " ++ "fw_id = %d, lun = %lld,\n\t task_context = 0x%x\n", ioc->name, mf, ++ type, timeout, channel, id, (unsigned long long)lun, ++ task_context)); ++ ++ pScsiTm = (SCSITaskMgmt_t *) mf; ++ memset(pScsiTm, 0, sizeof(SCSITaskMgmt_t)); ++ pScsiTm->Function = MPI_FUNCTION_SCSI_TASK_MGMT; ++ pScsiTm->TaskType = type; ++ pScsiTm->MsgFlags = 0; ++ pScsiTm->TargetID = id; ++ pScsiTm->Bus = channel; ++ pScsiTm->ChainOffset = 0; ++ pScsiTm->Reserved = 0; ++ pScsiTm->Reserved1 = 0; ++ pScsiTm->TaskMsgContext = task_context; ++ int_to_scsilun(lun, (struct scsi_lun *)pScsiTm->LUN); ++ ++ INITIALIZE_MGMT_STATUS(ioc->taskmgmt_cmds.status) ++ CLEAR_MGMT_STATUS(ioc->internal_cmds.status) ++ retval = 0; ++ mpt_put_msg_frame_hi_pri(mptsasDeviceResetCtx, ioc, mf); ++ ++ /* Now wait for the command to complete */ ++ timeleft = wait_for_completion_timeout(&ioc->taskmgmt_cmds.done, ++ timeout*HZ); ++ if (!(ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { ++ retval = -1; /* return failure */ ++ dtmprintk(ioc, printk(MYIOC_s_ERR_FMT ++ "TaskMgmt request: TIMED OUT!(mr=%p)\n", ioc->name, mf)); ++ mpt_free_msg_frame(ioc, mf); ++ if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) ++ goto out; ++ *issue_reset = 1; ++ goto out; ++ } ++ ++ if (!(ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_RF_VALID)) { ++ retval = -1; /* return failure */ ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "TaskMgmt request: failed with no reply\n", ioc->name)); ++ goto out; ++ } ++ ++ out: ++ CLEAR_MGMT_STATUS(ioc->taskmgmt_cmds.status) ++ return retval; ++} ++ ++/** ++ * mptsas_broadcast_primative_work - Work queue thread to handle ++ * broadcast primitive events ++ * @work: work queue payload containing info describing the event ++ * ++ **/ ++static void ++mptsas_broadcast_primative_work(struct fw_event_work *fw_event) ++{ ++ MPT_ADAPTER *ioc = fw_event->ioc; ++ MPT_FRAME_HDR *mf; ++ VirtDevice *vdevice; ++ int ii; ++ struct scsi_cmnd *sc; ++ SCSITaskMgmtReply_t * pScsiTmReply; ++ u8 issue_reset; ++ int task_context; ++ u8 channel, id; ++ int lun; ++ u32 termination_count; ++ u32 query_count; ++ ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "%s - enter\n", ioc->name, __FUNCTION__)); ++ ++ mutex_lock(&ioc->taskmgmt_cmds.mutex); ++ if (mpt_set_taskmgmt_in_progress_flag(ioc) != 0) { ++ mutex_unlock(&ioc->taskmgmt_cmds.mutex); ++ mptsas_requeue_fw_event(ioc, fw_event, 1000); ++ return; ++ } ++ ++ issue_reset = 0; ++ termination_count = 0; ++ query_count = 0; ++ mpt_findImVolumes(ioc); ++ pScsiTmReply = (SCSITaskMgmtReply_t *) ioc->taskmgmt_cmds.reply; ++ ++ for (ii = 0; ii < ioc->req_depth; ii++) { ++ if (ioc->fw_events_off) ++ goto out; ++ sc = mptscsih_get_scsi_lookup(ioc, ii); ++ if (!sc) ++ continue; ++ mf = MPT_INDEX_2_MFPTR(ioc, ii); ++ if (!mf) ++ continue; ++ task_context = mf->u.frame.hwhdr.msgctxu.MsgContext; ++ vdevice = sc->device->hostdata; ++ if (!vdevice || !vdevice->vtarget) ++ continue; ++ if (vdevice->vtarget->tflags & MPT_TARGET_FLAGS_RAID_COMPONENT) ++ continue; /* skip hidden raid components */ ++ if (vdevice->vtarget->raidVolume) ++ continue; /* skip hidden raid components */ ++ channel = vdevice->vtarget->channel; ++ id = vdevice->vtarget->id; ++ lun = vdevice->lun; ++ if (mptsas_issue_tm(ioc, MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK, ++ channel, id, (u64)lun, task_context, 30, &issue_reset)) ++ goto out; ++ query_count++; ++ termination_count += ++ le32_to_cpu(pScsiTmReply->TerminationCount); ++ if ((pScsiTmReply->IOCStatus == MPI_IOCSTATUS_SUCCESS) && ++ (pScsiTmReply->ResponseCode == ++ MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED || ++ pScsiTmReply->ResponseCode == ++ MPI_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC)) ++ continue; ++ if (mptsas_issue_tm(ioc, ++ MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, ++ channel, id, (u64)lun, 0, 30, &issue_reset)) ++ goto out; ++ termination_count += ++ le32_to_cpu(pScsiTmReply->TerminationCount); ++ } ++ ++ out: ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "%s - exit, query_count = %d termination_count = %d\n", ++ ioc->name, __FUNCTION__, query_count, termination_count)); ++ ++ ioc->broadcast_aen_busy = 0; ++ mpt_clear_taskmgmt_in_progress_flag(ioc); ++ mutex_unlock(&ioc->taskmgmt_cmds.mutex); ++ ++ if (issue_reset) { ++ printk(MYIOC_s_WARN_FMT "Issuing Reset from %s!!\n", ++ ioc->name, __FUNCTION__); ++ if (mpt_SoftResetHandler(ioc, CAN_SLEEP)) ++ mpt_HardResetHandler(ioc, CAN_SLEEP); ++ } ++ mptsas_free_fw_event(ioc, fw_event); ++} ++ ++/** ++ * mptsas_send_ir2_event - handle exposing hidden disk when an inactive raid volume is added ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * @ir2_data: ++ * ++ **/ ++static void ++mptsas_send_ir2_event(struct fw_event_work *fw_event) ++{ ++ MPT_ADAPTER *ioc; ++ struct mptsas_hotplug_event hot_plug_info; ++ MPI_EVENT_DATA_IR2 *ir2_data; ++ u8 reasonCode; ++ RaidPhysDiskPage0_t phys_disk; ++ ++ ioc = fw_event->ioc; ++ ir2_data = (MPI_EVENT_DATA_IR2 *)fw_event->event_data; ++ reasonCode = ir2_data->ReasonCode; ++ ++ devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Entering %s: " ++ "ReasonCode=%02x\n", ioc->name, __func__, reasonCode)); ++ ++ memset(&hot_plug_info, 0, sizeof(struct mptsas_hotplug_event)); ++ hot_plug_info.id = ir2_data->TargetID; ++ hot_plug_info.channel = ir2_data->Bus; ++ switch (reasonCode) { ++ case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED: ++ hot_plug_info.event_type = MPTSAS_ADD_INACTIVE_VOLUME; ++ break; ++ case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED: ++ hot_plug_info.phys_disk_num = ir2_data->PhysDiskNum; ++ hot_plug_info.event_type = MPTSAS_DEL_PHYSDISK; ++ break; ++ case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED: ++ hot_plug_info.phys_disk_num = ir2_data->PhysDiskNum; ++ mpt_raid_phys_disk_pg0(ioc, ++ ir2_data->PhysDiskNum, &phys_disk); ++ hot_plug_info.id = phys_disk.PhysDiskID; ++ hot_plug_info.event_type = MPTSAS_ADD_PHYSDISK; ++ break; ++ default: ++ mptsas_free_fw_event(ioc, fw_event); ++ return; ++ } ++ mptsas_hotplug_work(ioc, fw_event, &hot_plug_info); + } + + +@@ -4962,7 +5652,7 @@ + fw_event = kzalloc(sz, GFP_ATOMIC); + if (!fw_event) { + printk(MYIOC_s_WARN_FMT "%s: failed at (line=%d)\n", ioc->name, +- __func__, __LINE__); ++ __func__, __LINE__); + return 0; + } + memcpy(fw_event->event_data, reply->Data, event_data_sz); +@@ -4992,215 +5682,10 @@ + goto release_sdev; + out: + printk(MYIOC_s_INFO_FMT "removing raid volume, channel %d, " +- "id %d\n", ioc->name, MPTSAS_RAID_CHANNEL, id); ++ "id %d\n", ioc->name, MPTSAS_RAID_CHANNEL,id); + scsi_remove_device(sdev); + release_sdev: + scsi_device_put(sdev); +-} +- +-static void +-mptsas_not_responding_devices(MPT_ADAPTER *ioc) +-{ +- struct mptsas_portinfo buffer, *port_info; +- struct sas_device_info *sas_info; +- struct mptsas_devinfo sas_device; +- u32 handle; +- VirtTarget *vtarget = NULL; +- struct mptsas_phyinfo *phy_info; +- u8 found_expander; +- +- if (ioc->disable_hotplug_remove) +- return; +- +- mpt_findImVolumes(ioc); +- +- /* devices, logical volumes */ +- redo_device_scan: +- list_for_each_entry(sas_info, &ioc->sas_device_info_list, list) { +- if (sas_info->is_cached) +- continue; +- if (!sas_info->is_logical_volume) { +- sas_device.handle = 0; +- mptsas_sas_device_pg0(ioc, &sas_device, +- (MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID << +- MPI_SAS_DEVICE_PGAD_FORM_SHIFT), +- (sas_info->fw.channel << 8) + +- sas_info->fw.id); +- if (sas_device.handle) +- continue; +- /* delete device */ +- if ((vtarget = mptsas_find_vtarget(ioc, +- sas_info->fw.channel, +- sas_info->fw.id))) +- vtarget->deleted = 1; +- phy_info = mptsas_find_phyinfo_by_sas_address(ioc, +- sas_info->sas_address); +- if (phy_info) { +- mptsas_del_end_device(ioc, phy_info); +- goto redo_device_scan; +- } +- } else +- mptsas_volume_delete(ioc, sas_info->fw.id); +- } +- +- /* expanders */ +- redo_expander_scan: +- list_for_each_entry(port_info, &ioc->sas_topology, list) { +- +- if (port_info->phy_info && +- (!(port_info->phy_info[0].identify.device_info & +- MPI_SAS_DEVICE_INFO_SMP_TARGET))) +- continue; +- found_expander = 0; +- handle = 0xFFFF; +- while (!mptsas_sas_expander_pg0(ioc, &buffer, +- (MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE << +- MPI_SAS_EXPAND_PGAD_FORM_SHIFT), handle) && +- !found_expander) { +- +- handle = buffer.phy_info[0].handle; +- if (buffer.phy_info[0].identify.sas_address == +- port_info->phy_info[0].identify.sas_address) { +- found_expander = 1; +- } +- kfree(buffer.phy_info); +- } +- +- if (!found_expander) { +- mptsas_expander_delete(ioc, port_info); +- goto redo_expander_scan; +- } +- } +-} +- +-/** +- * mptsas_probe_expanders - adding expanders +- * @ioc: Pointer to MPT_ADAPTER structure +- * +- **/ +-static void +-mptsas_probe_expanders(MPT_ADAPTER *ioc) +-{ +- struct mptsas_portinfo buffer, *port_info; +- u32 handle; +- int i; +- +- handle = 0xFFFF; +- while (!mptsas_sas_expander_pg0(ioc, &buffer, +- (MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE << +- MPI_SAS_EXPAND_PGAD_FORM_SHIFT), handle)) { +- +- handle = buffer.phy_info[0].handle; +- port_info = mptsas_find_portinfo_by_sas_address(ioc, +- buffer.phy_info[0].identify.sas_address); +- +- if (port_info) { +- /* refreshing handles */ +- for (i = 0; i < buffer.num_phys; i++) { +- port_info->phy_info[i].handle = handle; +- port_info->phy_info[i].identify.handle_parent = +- buffer.phy_info[0].identify.handle_parent; +- } +- mptsas_expander_refresh(ioc, port_info); +- kfree(buffer.phy_info); +- continue; +- } +- +- port_info = kzalloc(sizeof(struct mptsas_portinfo), GFP_KERNEL); +- if (!port_info) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "%s: exit at line=%d\n", ioc->name, +- __func__, __LINE__)); +- return; +- } +- port_info->num_phys = buffer.num_phys; +- port_info->phy_info = buffer.phy_info; +- for (i = 0; i < port_info->num_phys; i++) +- port_info->phy_info[i].portinfo = port_info; +- mutex_lock(&ioc->sas_topology_mutex); +- list_add_tail(&port_info->list, &ioc->sas_topology); +- mutex_unlock(&ioc->sas_topology_mutex); +- printk(MYIOC_s_INFO_FMT "add expander: num_phys %d, " +- "sas_addr (0x%llx)\n", ioc->name, port_info->num_phys, +- (unsigned long long)buffer.phy_info[0].identify.sas_address); +- mptsas_expander_refresh(ioc, port_info); +- } +-} +- +-static void +-mptsas_probe_devices(MPT_ADAPTER *ioc) +-{ +- u16 retry_count; +- u16 handle; +- struct mptsas_devinfo sas_device; +- struct mptsas_phyinfo *phy_info; +- enum device_state state; +- +- handle = 0xFFFF; +- while (!(mptsas_sas_device_pg0(ioc, &sas_device, +- MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE, handle))) { +- +- handle = sas_device.handle; +- +- if ((sas_device.device_info & +- (MPI_SAS_DEVICE_INFO_SSP_TARGET | +- MPI_SAS_DEVICE_INFO_STP_TARGET | +- MPI_SAS_DEVICE_INFO_SATA_DEVICE)) == 0) +- continue; +- +- phy_info = mptsas_refreshing_device_handles(ioc, &sas_device); +- if (!phy_info) +- continue; +- +- if (mptsas_get_rphy(phy_info)) +- continue; +- +- state = DEVICE_RETRY; +- retry_count = 0; +- while (state == DEVICE_RETRY) { +- state = mptsas_test_unit_ready(ioc, sas_device.channel, +- sas_device.id, retry_count++); +- ssleep(1); +- } +- if (state == DEVICE_READY) +- mptsas_add_end_device(ioc, phy_info); +- } +-} +- +-/** +- * mptsas_scan_sas_topology - +- * @ioc: Pointer to MPT_ADAPTER structure +- * @sas_address: +- * +- **/ +-static void +-mptsas_scan_sas_topology(MPT_ADAPTER *ioc) +-{ +- struct scsi_device *sdev; +- int i; +- +- mptsas_probe_hba_phys(ioc); +- mptsas_probe_expanders(ioc); +- mptsas_probe_devices(ioc); +- +- /* +- Reporting RAID volumes. +- */ +- if (!ioc->ir_firmware || !ioc->raid_data.pIocPg2 || +- !ioc->raid_data.pIocPg2->NumActiveVolumes) +- return; +- for (i = 0; i < ioc->raid_data.pIocPg2->NumActiveVolumes; i++) { +- if ((sdev = scsi_device_lookup(ioc->sh, MPTSAS_RAID_CHANNEL, +- ioc->raid_data.pIocPg2->RaidVolume[i].VolumeID, 0))) { +- scsi_device_put(sdev); +- continue; +- } +- printk(MYIOC_s_INFO_FMT "attaching raid volume, channel %d, " +- "id %d\n", ioc->name, MPTSAS_RAID_CHANNEL, +- ioc->raid_data.pIocPg2->RaidVolume[i].VolumeID); +- scsi_add_device(ioc->sh, MPTSAS_RAID_CHANNEL, +- ioc->raid_data.pIocPg2->RaidVolume[i].VolumeID, 0); +- } + } + + /** +@@ -5273,7 +5758,7 @@ + ioc->name); + error = -1; + goto out_mptsas_probe; +- } ++ } + + spin_lock_irqsave(&ioc->FreeQlock, flags); + +@@ -5331,7 +5816,7 @@ + sh->sg_tablesize = numSGE; + } + +- hd = shost_priv(sh); ++ hd = shost_private(sh); + hd->ioc = ioc; + + /* SCSI needs scsi_cmnd lookup table! +@@ -5353,12 +5838,11 @@ + hd->last_queue_full = 0; + ioc->disable_hotplug_remove = mpt_disable_hotplug_remove; + if (ioc->disable_hotplug_remove) +- printk(MYIOC_s_INFO_FMT +- "disabling hotplug remove\n", ioc->name); ++ printk(MYIOC_s_INFO_FMT "disabling hotplug remove\n", ioc->name); + + INIT_LIST_HEAD(&hd->target_reset_list); + INIT_LIST_HEAD(&ioc->sas_device_info_list); +- mutex_init(&ioc->sas_device_info_mutex); ++ init_MUTEX(&ioc->sas_device_info_mutex); + + spin_unlock_irqrestore(&ioc->FreeQlock, flags); + +@@ -5387,6 +5871,16 @@ + return error; + } + ++void ++mptsas_shutdown(struct pci_dev *pdev) ++{ ++ MPT_ADAPTER *ioc = pci_get_drvdata(pdev); ++ ++ mptsas_fw_event_off(ioc); ++ mptsas_cleanup_fw_event_q(ioc); ++} ++ ++ + /** + * mptsas_remove - + * @pdev: +@@ -5399,8 +5893,7 @@ + struct mptsas_portinfo *p, *n; + int i; + +- mptsas_fw_event_off(ioc); +- mptsas_cleanup_fw_event_q(ioc); ++ mptsas_shutdown(pdev); + + mptsas_del_device_components(ioc); + +@@ -5441,7 +5934,7 @@ + .id_table = mptsas_pci_table, + .probe = mptsas_probe, + .remove = __devexit_p(mptsas_remove), +- .shutdown = mptscsih_shutdown, ++ .shutdown = mptsas_shutdown, + #ifdef CONFIG_PM + .suspend = mptscsih_suspend, + .resume = mptscsih_resume, +diff -r 8807687e8e9c drivers/message/fusion/mptsas.h +--- a/drivers/message/fusion/mptsas.h Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/mptsas.h Tue Sep 01 16:11:23 2009 +0100 +@@ -50,7 +50,7 @@ + /*{-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + + struct mptsas_target_reset_event { +- struct list_head list; ++ struct list_head list; + MpiEventDataSasDeviceStatusChange_t sas_event_data; + u8 target_reset_issued; + unsigned long time_count; +@@ -76,20 +76,17 @@ + }; + + struct sas_device_info { +- struct list_head list; ++ struct list_head list; + struct sas_mapping os; /* operating system mapping*/ + struct sas_mapping fw; /* firmware mapping */ +- u64 sas_address; ++ u64 sas_address; + u32 device_info; /* specific bits for devices */ + u16 slot; /* enclosure slot id */ + u64 enclosure_logical_id; /*enclosure address */ + u8 is_logical_volume; /* is this logical volume */ +- /* this belongs to volume */ +- u8 is_hidden_raid_component; +- /* this valid when is_hidden_raid_component set */ +- u8 volume_id; +- /* cached data for a removed device */ +- u8 is_cached; ++ u8 is_hidden_raid_component; /* this belongs to volume */ ++ u8 volume_id; /* this valid when is_hidden_raid_component set */ ++ u8 is_cached; /* cached data for a removed device */ + }; + + struct mptsas_hotplug_event { +@@ -107,8 +104,12 @@ + + + struct fw_event_work { +- struct list_head list; ++ struct list_head list; ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + struct delayed_work work; ++#else ++ struct work_struct work; ++#endif + MPT_ADAPTER *ioc; + u32 event; + u8 retries; +@@ -145,31 +146,40 @@ + u64 sas_address; /* WWN of this device, + SATA is assigned by HBA,expander */ + u32 device_info; /* bitfield detailed info about this device */ ++#if !defined(MPT_WIDE_PORT_API) ++ u8 wide_port_enable; /* when set, this is part of wide port*/ ++#endif + }; + + /* + * Specific details on ports, wide/narrow + */ + struct mptsas_portinfo_details{ ++#if !defined(MPT_WIDE_PORT_API) ++ u8 port_id; /* port number provided to transport */ ++ u8 rphy_id; /* phy index used for reporting end device*/ ++ u32 device_info; /* bitfield detailed info about this device */ ++#endif + u16 num_phys; /* number of phys beloing to this port */ +- u64 phy_bitmask; /* this needs extending to support 128 phys */ ++ u64 phy_bitmask; /* this needs extending to support 128 phys */ + struct sas_rphy *rphy; /* rphy for end devices */ ++#if defined(MPT_WIDE_PORT_API) + struct sas_port *port; /* transport layer port object */ ++#endif + struct scsi_target *starget; + struct mptsas_portinfo *port_info; + }; + + struct mptsas_phyinfo { + u16 handle; /* handle for this phy */ +- u8 phy_id; /* phy index */ +- u8 port_id; /* port number this phy is part of */ ++ u8 phy_id; /* phy index */ ++ u8 port_id; /* port number this phy is part of */ + u8 negotiated_link_rate; /* nego'd link rate for this phy */ +- u8 hw_link_rate; /* hardware max/min phys link rate */ ++ u8 hw_link_rate; /* hardware max/min phys link rate */ + u8 programmed_link_rate; /* programmed max/min phy link rate */ ++#if defined(MPT_WIDE_PORT_API) + u8 sas_port_add_phy; /* flag to request sas_port_add_phy*/ +- u8 change_count; /* change count of the phy */ +- u8 port_flags; /* info wrt host sas ports */ +- u32 phy_info; /* various info wrt the phy */ ++#endif + struct mptsas_devinfo identify; /* point to phy device info */ + struct mptsas_devinfo attached; /* point to attached device info */ + struct sas_phy *phy; +@@ -194,7 +204,16 @@ + u8 sep_id; /* SEP device logical target id */ + u8 sep_channel; /* SEP channel logical channel id */ + }; +- ++#if 0 ++struct mptsas_broadcast_primative_event { ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) ++ struct delayed_work aen_work; ++#else ++ struct work_struct aen_work; ++#endif ++ MPT_ADAPTER *ioc; ++}; ++#endif + /*}-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + #endif + +diff -r 8807687e8e9c drivers/message/fusion/mptscsih.c +--- a/drivers/message/fusion/mptscsih.c Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/mptscsih.c Tue Sep 01 16:11:23 2009 +0100 +@@ -43,7 +43,7 @@ + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +- ++#include + #include + #include + #include +@@ -64,6 +64,7 @@ + #include + #include + ++#include "linux_compat.h" /* linux-2.6 tweaks */ + #include "mptbase.h" + #include "mptscsih.h" + #include "lsi/mpi_log_sas.h" +@@ -102,8 +103,7 @@ + + int mptscsih_ioc_reset(MPT_ADAPTER *ioc, int post_reset); + int mptscsih_event_process(MPT_ADAPTER *ioc, EventNotificationReply_t *pEvReply); +-static void mptscsih_synchronize_cache(struct scsi_device *sdev, +- MPT_SCSI_HOST *hd, VirtDevice *vdevice); ++static void mptscsih_synchronize_cache(struct scsi_device *sdev, MPT_SCSI_HOST *hd, VirtDevice *vdevice); + + void mptscsih_remove(struct pci_dev *); + void mptscsih_shutdown(struct pci_dev *); +@@ -111,16 +111,23 @@ + int mptscsih_suspend(struct pci_dev *pdev, pm_message_t state); + int mptscsih_resume(struct pci_dev *pdev); + #endif +- +-/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** ++static int mptscsih_taskmgmt_reply(MPT_ADAPTER *ioc, u8 type, ++ SCSITaskMgmtReply_t *pScsiTmReply); ++static int mptscsih_get_completion_code(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, ++ MPT_FRAME_HDR *reply); ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)) ++#define SNS_LEN(scp) sizeof((scp)->sense_buffer) ++#endif ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ ++/* + * mptscsih_getFreeChainBuffer - Function to get a free chain + * from the MPT_SCSI_HOST FreeChainQ. + * @ioc: Pointer to MPT_ADAPTER structure + * @req_idx: Index of the SCSI IO request frame. (output) + * + * return SUCCESS or FAILED +- **/ ++ */ + static inline int + mptscsih_getFreeChainBuffer(MPT_ADAPTER *ioc, int *retIndex) + { +@@ -130,7 +137,7 @@ + int chain_idx; + + dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "getFreeChainBuffer called\n", +- ioc->name)); ++ ioc->name)); + spin_lock_irqsave(&ioc->FreeQlock, flags); + if (!list_empty(&ioc->FreeChainQ)) { + int offset; +@@ -142,16 +149,13 @@ + chain_idx = offset / ioc->req_sz; + rc = SUCCESS; + dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "getFreeChainBuffer chainBuf=%p ChainBuffer=%p" +- " offset=%d chain_idx=%d\n", +- ioc->name, chainBuf, ioc->ChainBuffer, offset, +- chain_idx)); ++ "getFreeChainBuffer chainBuf=%p ChainBuffer=%p offset=%d chain_idx=%d\n", ++ ioc->name, chainBuf, ioc->ChainBuffer, offset, chain_idx)); + } else { + rc = FAILED; + chain_idx = MPT_HOST_NO_CHAIN; +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "getFreeChainBuffer failed\n", +- ioc->name)); ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT "getFreeChainBuffer failed\n", ++ ioc->name)); + } + spin_unlock_irqrestore(&ioc->FreeQlock, flags); + +@@ -160,7 +164,7 @@ + } /* mptscsih_getFreeChainBuffer() */ + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** ++/* + * mptscsih_AddSGE - Add a SGE (plus chain buffers) to the + * SCSIIORequest_t Message Frame. + * @ioc: Pointer to MPT_ADAPTER structure +@@ -168,7 +172,7 @@ + * @pReq: Pointer to SCSIIORequest_t structure + * + * Returns ... +- **/ ++ */ + static int + mptscsih_AddSGE(MPT_ADAPTER *ioc, struct scsi_cmnd *SCpnt, + SCSIIORequest_t *pReq, int req_idx) +@@ -188,19 +192,59 @@ + dma_addr_t v2; + u32 RequestNB; + +- sgdir = le32_to_cpu(pReq->Control) & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK; ++#ifdef EEDP_SUPPORT ++ if (pReq->Function == MPI_FUNCTION_SCSI_IO_32) { ++ SCSIIO32Request_t *mpi_request = (SCSIIO32Request_t *)pReq; ++ ++ sgdir = le32_to_cpu(mpi_request->Control) ++ & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK; ++ psge = (char *) &mpi_request->SGL; ++ } else { ++#endif ++ sgdir = le32_to_cpu(pReq->Control) & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK; ++ psge = (char *) &pReq->SGL; ++#ifdef EEDP_SUPPORT ++ } ++#endif + if (sgdir == MPI_SCSIIO_CONTROL_WRITE) { + sgdir = MPT_TRANSFER_HOST_TO_IOC; + } else { + sgdir = MPT_TRANSFER_IOC_TO_HOST; + } + +- psge = (char *) &pReq->SGL; + frm_sz = ioc->req_sz; ++ + + /* Map the data portion, if any. + * sges_left = 0 if no data transfer. + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ if ( (sges_left = SCpnt->use_sg) ) { ++ sges_left = pci_map_sg(ioc->pcidev, ++ (struct scatterlist *) SCpnt->request_buffer, ++ SCpnt->use_sg, ++ SCpnt->sc_data_direction); ++ if (sges_left == 0) ++ return FAILED; ++ } else if (SCpnt->request_bufflen) { ++ SCpnt->SCp.dma_handle = pci_map_single(ioc->pcidev, ++ SCpnt->request_buffer, ++ SCpnt->request_bufflen, ++ SCpnt->sc_data_direction); ++ dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SG: non-SG for %p, len=%d\n", ++ ioc->name, SCpnt, SCpnt->request_bufflen)); ++ ioc->add_sge((char *) &pReq->SGL, ++ 0xD1000000|sgdir|SCpnt->request_bufflen, ++ SCpnt->SCp.dma_handle); ++ ++ return SUCCESS; ++ } ++ ++ /* Handle the SG case. ++ */ ++ sg = (struct scatterlist *) SCpnt->request_buffer; ++#else ++ + sges_left = scsi_dma_map(SCpnt); + if (sges_left < 0) + return FAILED; +@@ -208,8 +252,9 @@ + /* Handle the SG case. + */ + sg = scsi_sglist(SCpnt); ++#endif + sg_done = 0; +- sgeOffset = sizeof(SCSIIORequest_t) - sizeof(SGE_IO_UNION); ++ sgeOffset = psge - (char *) pReq; + chainSge = NULL; + + /* Prior to entering this loop - the following must be set +@@ -231,7 +276,8 @@ + for (ii=0; ii < (numSgeThisFrame-1); ii++) { + thisxfer = sg_dma_len(sg); + if (thisxfer == 0) { +- sg = sg_next(sg); /* Get next SG element from the OS */ ++ /* Get next SG element from the OS */ ++ sg = mpt_sg_next(sg); + sg_done++; + continue; + } +@@ -239,7 +285,8 @@ + v2 = sg_dma_address(sg); + ioc->add_sge(psge, sgflags | thisxfer, v2); + +- sg = sg_next(sg); /* Get next SG element from the OS */ ++ /* Get next SG element from the OS */ ++ sg = mpt_sg_next(sg); + psge += ioc->SGE_size; + sgeOffset += ioc->SGE_size; + sg_done++; +@@ -269,7 +316,7 @@ + * Offset and Length fields. + */ + ioc->add_chain((char *)chainSge, 0, sgeOffset, +- ioc->ChainBufferDMA + chain_dma_off); ++ ioc->ChainBufferDMA + chain_dma_off); + } else { + /* The current buffer is the original MF + * and there is no Chain buffer. +@@ -318,7 +365,7 @@ + u8 nextChain = (u8) (sgeOffset >> 2); + sgeOffset += ioc->SGE_size; + ioc->add_chain((char *)chainSge, nextChain, sgeOffset, +- ioc->ChainBufferDMA + chain_dma_off); ++ ioc->ChainBufferDMA + chain_dma_off); + } else { + /* The original MF buffer requires a chain buffer - + * set the offset. +@@ -530,12 +577,16 @@ + scsi_print_command(sc); + printk(MYIOC_s_DEBUG_FMT "\tfw_channel = %d, fw_id = %d, lun = %d\n", + ioc->name, pScsiReply->Bus, pScsiReply->TargetID, sc->device->lun); +- printk(MYIOC_s_DEBUG_FMT +- "\trequest_len = %d, underflow = %d, resid = %d\n", +- ioc->name, scsi_bufflen(sc), sc->underflow, scsi_get_resid(sc)); +- printk(MYIOC_s_DEBUG_FMT +- "\ttag = %d, transfer_count = %d, sc->result = %08X\n", +- ioc->name, le16_to_cpu(pScsiReply->TaskTag), ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ printk(MYIOC_s_DEBUG_FMT "\trequest_len = %d, underflow = %d, resid = %d\n", ++ ioc->name, sc->request_bufflen, sc->underflow, sc->resid); ++#else ++ printk(MYIOC_s_DEBUG_FMT "\trequest_len = %d, underflow = %d, " ++ "resid = %d\n", ioc->name, scsi_bufflen(sc), sc->underflow, ++ scsi_get_resid(sc)); ++#endif ++ printk(MYIOC_s_DEBUG_FMT "\ttag = %d, transfer_count = %d, " ++ "sc->result = %08X\n", ioc->name, le16_to_cpu(pScsiReply->TaskTag), + le32_to_cpu(pScsiReply->TransferCount), sc->result); + + printk(MYIOC_s_DEBUG_FMT "\tiocstatus = %s (0x%04x), " +@@ -563,7 +614,7 @@ + #endif + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** ++/* + * mptscsih_io_done - Main SCSI IO callback routine registered to + * Fusion MPT (base) driver + * @ioc: Pointer to MPT_ADAPTER structure +@@ -576,7 +627,7 @@ + * load/init time via the mpt_register() API call. + * + * Returns 1 indicating alloc'd request frame ptr should be freed. +- **/ ++ */ + int + mptscsih_io_done(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf, MPT_FRAME_HDR *mr) + { +@@ -588,16 +639,15 @@ + VirtDevice *vdevice; + VirtTarget *vtarget; + +- hd = shost_priv(ioc->sh); +- ++ hd = shost_private(ioc->sh); + req_idx = le16_to_cpu(mf->u.frame.hwhdr.msgctxu.fld.req_idx); + req_idx_MR = (mr != NULL) ? + le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx) : req_idx; + if ((req_idx != req_idx_MR) || + (le32_to_cpu(mf->u.frame.linkage.arg1) == 0xdeadbeaf)) { +- printk(MYIOC_s_WARN_FMT +- "Received a mf that was already freed\n", ioc->name); +- printk(MYIOC_s_WARN_FMT ++ printk(MYIOC_s_ERR_FMT "Received a mf that was already freed\n", ++ ioc->name); ++ printk (MYIOC_s_ERR_FMT + "req_idx=%x req_idx_MR=%x mf=%p mr=%p sc=%p\n", + ioc->name, req_idx, req_idx_MR, mf, mr, + mptscsih_get_scsi_lookup(ioc, req_idx_MR)); +@@ -623,6 +673,16 @@ + if ((unsigned char *)mf != sc->host_scribble) { + mptscsih_freeChainBuffers(ioc, req_idx); + return 1; ++ } ++ ++ if (ioc->bus_type == SAS) { ++ VirtDevice *vdevice = sc->device->hostdata; ++ ++ if (!vdevice || !vdevice->vtarget || ++ vdevice->vtarget->deleted) { ++ sc->result = DID_NO_CONNECT << 16; ++ goto out; ++ } + } + + sc->host_scribble = NULL; +@@ -632,7 +692,7 @@ + + if((ioc->facts.MsgVersion >= MPI_VERSION_01_05) && pScsiReply){ + dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "ScsiDone (mf=%p,mr=%p,sc=%p,idx=%d,task_tag=%d)\n", ++ "ScsiDone (mf=%p,mr=%p,sc=%p,idx=%d,task-tag=%d)\n", + ioc->name, mf, mr, sc, req_idx, pScsiReply->TaskTag)); + }else{ + dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT +@@ -654,7 +714,11 @@ + scsi_state = pScsiReply->SCSIState; + scsi_status = pScsiReply->SCSIStatus; + xfer_cnt = le32_to_cpu(pScsiReply->TransferCount); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ sc->resid = sc->request_bufflen - xfer_cnt; ++#else + scsi_set_resid(sc, scsi_bufflen(sc) - xfer_cnt); ++#endif + log_info = le32_to_cpu(pScsiReply->IOCLogInfo); + vdevice = sc->device->hostdata; + +@@ -722,12 +786,14 @@ + } + } + } else if (ioc->bus_type == FC) { +- /* The FC IOC may kill a request for variety +- * of reasons, some of which may be recovered +- * by a retry, some which are unlikely to be +- * recovered. Return DID_ERROR instead of +- * DID_RESET to permit retry of the command, +- * just not an infinite number of them */ ++ /* ++ * The FC IOC may kill a request for variety of ++ * reasons, some of which may be recovered by a ++ * retry, some which are unlikely to be ++ * recovered. Return DID_ERROR instead of ++ * DID_RESET to permit retry of the command, ++ * just not an infinite number of them ++ */ + sc->result = DID_ERROR << 16; + break; + } +@@ -743,18 +809,25 @@ + sc->result = DID_RESET << 16; + + case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: /* 0x004C */ +- if (ioc->bus_type == FC) ++ if ( ioc->bus_type == FC ) + sc->result = DID_ERROR << 16; + else + sc->result = DID_RESET << 16; + break; + + case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: /* 0x0049 */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ sc->resid = sc->request_bufflen - xfer_cnt; ++#else + scsi_set_resid(sc, scsi_bufflen(sc) - xfer_cnt); ++#endif + if((xfer_cnt==0)||(sc->underflow > xfer_cnt)) + sc->result=DID_SOFT_ERROR << 16; + else /* Sufficient data transfer occurred */ + sc->result = (DID_OK << 16) | scsi_status; ++ dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "RESIDUAL_MISMATCH: result=%x on channel=%d id=%d\n", ++ ioc->name, sc->result, sc->device->channel, sc->device->id)); + break; + + case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: /* 0x0045 */ +@@ -781,12 +854,17 @@ + pScsiReq->CDB[0] == READ_16 || + pScsiReq->CDB[0] == VERIFY || + pScsiReq->CDB[0] == VERIFY_16) { +- if (scsi_bufflen(sc) != +- xfer_cnt) { +- sc->result = DID_SOFT_ERROR << 16; +- printk(MYIOC_s_WARN_FMT "Errata" +- "on LSI53C1030 occurred. sc->request_bufflen=0x%02x, " +- "xfer_cnt=0x%02x\n", ioc->name, scsi_bufflen(sc), xfer_cnt); ++ unsigned int bufflen; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ bufflen = sc->request_bufflen; ++#else ++ bufflen = scsi_bufflen(sc); ++#endif ++ if (bufflen != xfer_cnt) { ++ sc->result = DID_SOFT_ERROR << 16; ++ printk(MYIOC_s_WARN_FMT "Errata" ++ "on LSI53C1030 occurred. sc->request_bufflen=0x%02x, " ++ "xfer_cnt=0x%02x\n", ioc->name, bufflen, xfer_cnt); + } + } + } +@@ -799,7 +877,7 @@ + } + if (scsi_state & (MPI_SCSI_STATE_AUTOSENSE_FAILED | MPI_SCSI_STATE_NO_SCSI_STATUS)) { + /* What to do? +- */ ++ */ + sc->result = DID_SOFT_ERROR << 16; + } + else if (scsi_state & MPI_SCSI_STATE_TERMINATED) { +@@ -808,6 +886,13 @@ + } + } + ++ ++ dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ " sc->underflow={report ERR if < %02xh bytes xfer'd}\n", ++ ioc->name, sc->underflow)); ++ dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ " ActBytesXferd=%02xh\n", ioc->name, xfer_cnt)); ++ + /* Report Queue Full + */ + if (scsi_status == MPI_SCSI_STATUS_TASK_SET_FULL) +@@ -816,14 +901,24 @@ + break; + + case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: /* 0x0044 */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ sc->resid=0; ++#else + scsi_set_resid(sc, 0); ++#endif + case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: /* 0x0040 */ + case MPI_IOCSTATUS_SUCCESS: /* 0x0000 */ + sc->result = (DID_OK << 16) | scsi_status; + if (scsi_state == 0) { + ; + } else if (scsi_state & MPI_SCSI_STATE_AUTOSENSE_VALID) { +- ++ unsigned int bufflen; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ bufflen = sc->request_bufflen; ++#else ++ bufflen = scsi_bufflen(sc); ++#endif + /* + * For potential trouble on LSI53C1030. (date:2007.xx.) + * It is checked whether the length of request data is equal to +@@ -833,30 +928,30 @@ + if (ioc->bus_type == SPI && vdevice && + vdevice->vtarget->type == TYPE_DISK) { + if (sc->sense_buffer[2] & 0x20) { +- difftransfer = +- sc->sense_buffer[3] << 24 | +- sc->sense_buffer[4] << 16 | +- sc->sense_buffer[5] << 8 | +- sc->sense_buffer[6]; +- if ((sc->sense_buffer[3] & 0x80) == 0x80) { +- if (scsi_bufflen(sc) != xfer_cnt) { +- sc->sense_buffer[2] = MEDIUM_ERROR; +- sc->sense_buffer[12] = 0xff; +- sc->sense_buffer[13] = 0xff; +- printk(MYIOC_s_WARN_FMT "Errata on " +- "LSI53C1030 occurred. sc->request_bufflen=0x%02x," +- "xfer_cnt=0x%02x\n", ioc->name, scsi_bufflen(sc), xfer_cnt); +- } +- } else { +- if (scsi_bufflen(sc) != xfer_cnt + difftransfer) { +- sc->sense_buffer[2] = MEDIUM_ERROR; +- sc->sense_buffer[12] = 0xff; +- sc->sense_buffer[13] = 0xff; +- printk(MYIOC_s_WARN_FMT "Errata on " +- "LSI53C1030 occurred. sc->request_bufflen=0x%02x," +- " xfer_cnt=0x%02x, difftransfer=0x%02x\n", +- ioc->name, scsi_bufflen(sc) , xfer_cnt, difftransfer); +- } ++ difftransfer = ++ sc->sense_buffer[3] << 24 | ++ sc->sense_buffer[4] << 16 | ++ sc->sense_buffer[5] << 8 | ++ sc->sense_buffer[6]; ++ if ((sc->sense_buffer[3] & 0x80) == 0x80) { ++ if (bufflen != xfer_cnt) { ++ sc->sense_buffer[2] = MEDIUM_ERROR; ++ sc->sense_buffer[12] = 0xff; ++ sc->sense_buffer[13] = 0xff; ++ printk(MYIOC_s_WARN_FMT "Errata on " ++ "LSI53C1030 occurred. sc->request_bufflen=0x%02x," ++ "xfer_cnt=0x%02x\n", ioc->name, bufflen, xfer_cnt); ++ } ++ } else { ++ if (bufflen != xfer_cnt + difftransfer) { ++ sc->sense_buffer[2] = MEDIUM_ERROR; ++ sc->sense_buffer[12] = 0xff; ++ sc->sense_buffer[13] = 0xff; ++ printk(MYIOC_s_WARN_FMT "Errata on " ++ "LSI53C1030 occurred. sc->request_bufflen=0x%02x," ++ " xfer_cnt=0x%02x, difftransfer=0x%02x\n", ++ ioc->name, bufflen , xfer_cnt, difftransfer); ++ } + } + } + } +@@ -872,7 +967,7 @@ + + } + else if (scsi_state & +- (MPI_SCSI_STATE_AUTOSENSE_FAILED | MPI_SCSI_STATE_NO_SCSI_STATUS) ++ (MPI_SCSI_STATE_AUTOSENSE_FAILED | MPI_SCSI_STATE_NO_SCSI_STATUS) + ) { + /* + * What to do? +@@ -903,6 +998,13 @@ + case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: /* 0x0047 */ + sc->result = DID_SOFT_ERROR << 16; + break; ++#ifdef EEDP_SUPPORT ++ case MPI_IOCSTATUS_EEDP_GUARD_ERROR: ++ case MPI_IOCSTATUS_EEDP_REF_TAG_ERROR: ++ case MPI_IOCSTATUS_EEDP_APP_TAG_ERROR: ++ sc->result = DID_PARITY << 16; ++ break; ++#endif /* EEDP Support */ + + case MPI_IOCSTATUS_INVALID_FUNCTION: /* 0x0001 */ + case MPI_IOCSTATUS_INVALID_SGL: /* 0x0003 */ +@@ -928,8 +1030,19 @@ + + } /* end of address reply case */ + ++ out: + /* Unmap the DMA buffers, if any. */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ if (sc->use_sg) { ++ pci_unmap_sg(ioc->pcidev, (struct scatterlist *) sc->request_buffer, ++ sc->use_sg, sc->sc_data_direction); ++ } else if (sc->request_bufflen) { ++ pci_unmap_single(ioc->pcidev, sc->SCp.dma_handle, ++ sc->request_bufflen, sc->sc_data_direction); ++ } ++#else + scsi_dma_unmap(sc); ++#endif + + sc->scsi_done(sc); /* Issue the command callback */ + +@@ -938,7 +1051,7 @@ + return 1; + } + +-/** ++/* + * mptscsih_flush_running_cmds - For each command found, search + * Scsi_Host instance taskQ and reply to OS. + * Called only if recovering from a FW reload. +@@ -947,7 +1060,7 @@ + * Returns: None. + * + * Must be called while new I/Os are being queued. +- **/ ++ */ + static void + mptscsih_flush_running_cmds(MPT_SCSI_HOST *hd) + { +@@ -970,7 +1083,19 @@ + mpt_free_msg_frame(ioc, (MPT_FRAME_HDR *)mf); + if ((unsigned char *)mf != sc->host_scribble) + continue; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ if (sc->use_sg) { ++ pci_unmap_sg(ioc->pcidev, ++ (struct scatterlist *) sc->request_buffer, ++ sc->use_sg, sc->sc_data_direction); ++ } else if (sc->request_bufflen) { ++ pci_unmap_single(ioc->pcidev, ++ sc->SCp.dma_handle, sc->request_bufflen, ++ sc->sc_data_direction); ++ } ++#else + scsi_dma_unmap(sc); ++#endif + sc->result = DID_RESET << 16; + sc->host_scribble = NULL; + dtmprintk(ioc, sdev_printk(KERN_INFO, sc->device, MYIOC_s_FMT +@@ -980,7 +1105,7 @@ + } + } + +-/** ++/* + * mptscsih_search_running_cmds - Delete any commands associated + * with the specified target and lun. Function called only + * when a lun is disable by mid-layer. +@@ -993,15 +1118,15 @@ + * Returns: None. + * + * Called from slave_destroy. +- **/ ++ */ + static void + mptscsih_search_running_cmds(MPT_SCSI_HOST *hd, VirtDevice *vdevice) + { + SCSIIORequest_t *mf = NULL; + int ii; + struct scsi_cmnd *sc; +- struct scsi_lun lun; +- MPT_ADAPTER *ioc = hd->ioc; ++ struct scsi_lun lun; ++ MPT_ADAPTER *ioc = hd->ioc; + unsigned long flags; + + spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); +@@ -1011,11 +1136,8 @@ + mf = (SCSIIORequest_t *)MPT_INDEX_2_MFPTR(ioc, ii); + if (mf == NULL) + continue; +- +- /* +- * If the device is a hidden raid component, +- * then its expected that +- * the function would be raid scsi io ++ /* If the device is a hidden raid component, then its ++ * expected that the mf->function will be RAID_SCSI_IO + */ + if (vdevice->vtarget->tflags & + MPT_TARGET_FLAGS_RAID_COMPONENT && mf->Function != +@@ -1034,7 +1156,21 @@ + spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); + mptscsih_freeChainBuffers(ioc, ii); + mpt_free_msg_frame(ioc, (MPT_FRAME_HDR *)mf); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ if (sc->use_sg) { ++ pci_unmap_sg(ioc->pcidev, ++ (struct scatterlist *) sc->request_buffer, ++ sc->use_sg, ++ sc->sc_data_direction); ++ } else if (sc->request_bufflen) { ++ pci_unmap_single(ioc->pcidev, ++ sc->SCp.dma_handle, ++ sc->request_bufflen, ++ sc->sc_data_direction); ++ } ++#else + scsi_dma_unmap(sc); ++#endif + sc->host_scribble = NULL; + sc->result = DID_NO_CONNECT << 16; + dtmprintk(ioc, sdev_printk(KERN_INFO, sc->device, +@@ -1053,7 +1189,7 @@ + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** ++/* + * mptscsih_report_queue_full - Report QUEUE_FULL status returned + * from a SCSI target device. + * @sc: Pointer to scsi_cmnd structure +@@ -1063,19 +1199,19 @@ + * This routine periodically reports QUEUE_FULL status returned from a + * SCSI target device. It reports this to the console via kernel + * printk() API call, not more than once every 10 seconds. +- **/ ++ */ + static void + mptscsih_report_queue_full(struct scsi_cmnd *sc, SCSIIOReply_t *pScsiReply, SCSIIORequest_t *pScsiReq) + { + long time = jiffies; +- MPT_SCSI_HOST *hd; ++ MPT_SCSI_HOST *hd; + MPT_ADAPTER *ioc; + + if (sc->device == NULL) + return; + if (sc->device->host == NULL) + return; +- if ((hd = shost_priv(sc->device->host)) == NULL) ++ if ((hd = shost_private(sc->device->host)) == NULL) + return; + ioc = hd->ioc; + if (time - hd->last_queue_full > 10 * HZ) { +@@ -1086,12 +1222,12 @@ + } + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** ++/* + * mptscsih_remove - Removed scsi devices + * @pdev: Pointer to pci_dev structure + * + * +- **/ ++ */ + void + mptscsih_remove(struct pci_dev *pdev) + { +@@ -1107,7 +1243,7 @@ + + scsi_remove_host(host); + +- if((hd = shost_priv(host)) == NULL) ++ if((hd = shost_private(host)) == NULL) + return; + + mptscsih_shutdown(pdev); +@@ -1137,10 +1273,10 @@ + } + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** ++/* + * mptscsih_shutdown - reboot notifier + * +- **/ ++ */ + void + mptscsih_shutdown(struct pci_dev *pdev) + { +@@ -1148,11 +1284,11 @@ + + #ifdef CONFIG_PM + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** ++/* + * mptscsih_suspend - Fusion MPT scsi driver suspend routine. + * + * +- **/ ++ */ + int + mptscsih_suspend(struct pci_dev *pdev, pm_message_t state) + { +@@ -1165,11 +1301,11 @@ + } + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** ++/* + * mptscsih_resume - Fusion MPT scsi driver resume routine. + * + * +- **/ ++ */ + int + mptscsih_resume(struct pci_dev *pdev) + { +@@ -1191,14 +1327,14 @@ + * (linux scsi_host_template.info routine) + * + * Returns pointer to buffer where information was written. +- **/ ++ */ + const char * + mptscsih_info(struct Scsi_Host *SChost) + { + MPT_SCSI_HOST *h; + int size = 0; + +- h = shost_priv(SChost); ++ h = shost_private(SChost); + + if (h) { + if (h->info_kbuf == NULL) +@@ -1292,7 +1428,7 @@ + mptscsih_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset, + int length, int func) + { +- MPT_SCSI_HOST *hd = shost_priv(host); ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + int size = 0; + +@@ -1310,6 +1446,103 @@ + return size; + } + ++#ifdef EEDP_SUPPORT ++u8 opcode_protection[256] = { ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, PRO_R, 0, PRO_W, 0, 0, 0, PRO_W, PRO_V, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, PRO_W, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, PRO_R, 0, PRO_W, 0, 0, 0, PRO_W, PRO_V, ++ 0, 0, 0, PRO_W, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, PRO_R, 0, PRO_W, 0, 0, 0, PRO_W, PRO_V, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; ++ ++/** ++ * _scsih_setup_eedp - setup MPI request for EEDP transfer ++ * @ioc: ++ * @scmd: pointer to scsi command object ++ * @mpi_request: pointer to the SCSI_IO reqest message frame ++ * ++ * Supporting protection 1 only. ++ * ++ * Returns nothing ++ */ ++static int ++_scsih_setup_eedp(MPT_ADAPTER *ioc, struct scsi_cmnd *scmd, SCSIIO32Request_t *mpi_request) ++{ ++ VirtDevice *vdevice = scmd->device->hostdata; ++ u16 eedp_flags; ++ u8 scsi_opcode; ++ int lba_byte; ++ u32 *lba32; ++ ++ vdevice = scmd->device->hostdata; ++ if (!vdevice->eedp_enable) ++ return -1; ++ ++ /* protection type 1 support only */ ++ if (vdevice->eedp_type != 0) ++ return -1; ++ ++ /* check whether scsi opcode supports eedp transfer */ ++ scsi_opcode = scmd->cmnd[0]; ++ eedp_flags = opcode_protection[scsi_opcode]; ++ if (!eedp_flags) ++ return -1; ++ ++ /* ++ * enable ref/app/guard checking ++ * auto increment ref and app tag ++ */ ++ mpi_request->EEDPFlags = eedp_flags | ++ MPI_SCSIIO32_EEDPFLAGS_INC_PRI_REFTAG | ++ MPI_SCSIIO32_EEDPFLAGS_T10_CHK_REFTAG | ++ MPI_SCSIIO32_EEDPFLAGS_T10_CHK_LBATAG | ++ MPI_SCSIIO32_EEDPFLAGS_T10_CHK_GUARD; ++ ++ /* set block size */ ++ mpi_request->EEDPBlockSize = vdevice->eedp_block_length; ++ mpi_request->EEDPBlockSize += 8; ++ memset(mpi_request->CDB.CDB32, 0, 32); ++ ++ mpi_request->CDB.EEDP32.PrimaryApplicationTagMask = 0xFFFF; ++ ++ /* set reference tag to low 32bit lba */ ++ lba_byte = (scmd->cmd_len == 16) ? 6 : 2; ++ lba32 = (u32 *)&scmd->cmnd[lba_byte]; ++ mpi_request->CDB.EEDP32.PrimaryReferenceTag = *lba32; ++ ++ /* set RDPROTECT, WRPROTECT, VRPROTECT bits to (001b) */ ++ scmd->cmnd[1] = (scmd->cmnd[1] & 0x1F) | 0x20; ++ ++ /* add the rest of the bits */ ++ mpi_request->Port = 0; ++ mpi_request->Flags = MPI_SCSIIO32_FLAGS_FORM_SCSIID; ++ mpi_request->DeviceAddress.SCSIID.TargetID = vdevice->vtarget->id; ++ mpi_request->DeviceAddress.SCSIID.Bus = vdevice->vtarget->channel; ++ mpi_request->ChainOffset = 0; ++ mpi_request->Function = MPI_FUNCTION_SCSI_IO_32; ++ mpi_request->CDBLength = scmd->cmd_len; ++ mpi_request->SenseBufferLength = MPT_SENSE_BUFFER_SIZE; ++ mpi_request->MsgFlags = mpt_msg_flags(ioc); ++ int_to_scsilun(scmd->device->lun, (struct scsi_lun *)mpi_request->LUN); ++ memcpy(mpi_request->CDB.CDB32, scmd->cmnd, scmd->cmd_len); ++ mpi_request->SGLOffset0 = offsetof(SCSIIO32Request_t, SGL) / 4; ++ mpi_request->SGLOffset1 = 0; ++ mpi_request->SGLOffset2 = 0; ++ mpi_request->SGLOffset3 = 0; ++ return 0; ++} ++#endif /* EEDP Support */ ++ + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + #define ADD_INDEX_LOG(req_ent) do { } while(0) + +@@ -1324,7 +1557,7 @@ + * from a linux scsi_cmnd request and send it to the IOC. + * + * Returns 0. (rtn value discarded by linux scsi mid-layer) +- **/ ++ */ + int + mptscsih_qcmd(struct scsi_cmnd *SCpnt, void (*done)(struct scsi_cmnd *)) + { +@@ -1340,22 +1573,25 @@ + int ii; + MPT_ADAPTER *ioc; + +- hd = shost_priv(SCpnt->device->host); ++ hd = shost_private(SCpnt->device->host); + ioc = hd->ioc; + SCpnt->scsi_done = done; + + dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "qcmd: SCpnt=%p, done()=%p\n", + ioc->name, SCpnt, done)); + +- if (ioc->taskmgmt_quiesce_io) ++ if (ioc->taskmgmt_quiesce_io) { ++ dtmprintk(ioc, printk(MYIOC_s_WARN_FMT "qcmd: SCpnt=%p timeout + 60HZ\n", ++ ioc->name, SCpnt)); + return SCSI_MLQUEUE_HOST_BUSY; ++ } + + /* + * Put together a MPT SCSI request... + */ + if ((mf = mpt_get_msg_frame(ioc->DoneCtx, ioc)) == NULL) { + dprintk(ioc, printk(MYIOC_s_WARN_FMT "QueueCmd, no msg frames!!\n", +- ioc->name)); ++ ioc->name)); + return SCSI_MLQUEUE_HOST_BUSY; + } + +@@ -1370,10 +1606,18 @@ + * will be no data transfer! GRRRRR... + */ + if (SCpnt->sc_data_direction == DMA_FROM_DEVICE) { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ datalen = SCpnt->request_bufflen; ++#else + datalen = scsi_bufflen(SCpnt); ++#endif + scsidir = MPI_SCSIIO_CONTROL_READ; /* DATA IN (host<--ioc<--dev) */ + } else if (SCpnt->sc_data_direction == DMA_TO_DEVICE) { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ datalen = SCpnt->request_bufflen; ++#else + datalen = scsi_bufflen(SCpnt); ++#endif + scsidir = MPI_SCSIIO_CONTROL_WRITE; /* DATA OUT (host-->ioc-->dev) */ + } else { + datalen = 0; +@@ -1393,6 +1637,36 @@ + + /* Use the above information to set up the message frame + */ ++#ifdef EEDP_SUPPORT ++ if (_scsih_setup_eedp(ioc, SCpnt, (SCSIIO32Request_t *)mf) == 0) { ++ SCSIIO32Request_t *mpi_request = (SCSIIO32Request_t *)mf; ++ ++ /* finish off setting the rest of the SCSIIO32 */ ++ mpi_request->Control = cpu_to_le32(scsictl); ++ mpi_request->DataLength = cpu_to_le32(datalen); ++ ++ /* SenseBuffer low address */ ++ mpi_request->SenseBufferLowAddr = ++ cpu_to_le32(ioc->sense_buf_low_dma ++ + (my_idx * MPT_SENSE_BUFFER_ALLOC)); ++ ++ /* Now add the SG list ++ * Always have a SGE even if null length. ++ */ ++ if (datalen == 0) { ++ /* Add a NULL SGE */ ++ ioc->add_sge((char *)&mpi_request->SGL, ++ MPT_SGE_FLAGS_SSIMPLE_READ | 0, ++ (dma_addr_t) -1); ++ } else { ++ /* Add a 32 or 64 bit SGE */ ++ if (mptscsih_AddSGE(ioc, SCpnt, ++ pScsiReq, my_idx) != SUCCESS) ++ goto fail; ++ } ++ goto send_mf; ++ } ++#endif + pScsiReq->TargetID = (u8) vdevice->vtarget->id; + pScsiReq->Bus = vdevice->vtarget->channel; + pScsiReq->ChainOffset = 0; +@@ -1430,13 +1704,17 @@ + if (datalen == 0) { + /* Add a NULL SGE */ + ioc->add_sge((char *)&pScsiReq->SGL, +- MPT_SGE_FLAGS_SSIMPLE_READ | 0, (dma_addr_t) -1); ++ MPT_SGE_FLAGS_SSIMPLE_READ | 0, ++ (dma_addr_t) -1); + } else { + /* Add a 32 or 64 bit SGE */ + if (mptscsih_AddSGE(ioc, SCpnt, pScsiReq, my_idx) != SUCCESS) + goto fail; + } + ++#ifdef EEDP_SUPPORT ++ send_mf: ++#endif + SCpnt->host_scribble = (unsigned char *)mf; + mptscsih_set_scsi_lookup(ioc, my_idx, SCpnt); + +@@ -1453,7 +1731,7 @@ + } + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** ++/* + * mptscsih_freeChainBuffers - Function to free chain buffers associated + * with a SCSI IO request + * @hd: Pointer to the MPT_SCSI_HOST instance +@@ -1461,7 +1739,7 @@ + * + * Called if SG chain buffer allocation fails and mptscsih callbacks. + * No return. +- **/ ++ */ + static void + mptscsih_freeChainBuffers(MPT_ADAPTER *ioc, int req_idx) + { +@@ -1508,7 +1786,6 @@ + */ + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + + static int + mptscsih_scandv_bus_reset(MPT_ADAPTER *ioc) +@@ -1531,8 +1808,8 @@ + /* Send request + */ + if ((mf = mpt_get_msg_frame(ioc->TaskCtx, ioc)) == NULL) { +- dtmprintk(ioc, printk(MYIOC_s_WARN_FMT +- "TaskMgmt, no msg frames!!\n", ioc->name)); ++ dtmprintk(ioc, printk(MYIOC_s_WARN_FMT "TaskMgmt, no msg frames!!\n", ++ ioc->name)); + mpt_clear_taskmgmt_in_progress_flag(ioc); + retval = -ENOMEM; + goto out; +@@ -1552,27 +1829,26 @@ + pScsiTm->Reserved = 0; + pScsiTm->Reserved1 = 0; + pScsiTm->TaskMsgContext = 0; +- for (ii = 0; ii < 8; ii++) ++ for (ii= 0; ii < 8; ii++) + pScsiTm->LUN[ii] = 0; +- for (ii = 0; ii < 7; ii++) ++ for (ii=0; ii < 7; ii++) + pScsiTm->Reserved2[ii] = 0; + + switch (ioc->bus_type) { +- case FC: +- timeout = 40; +- break; +- case SAS: +- timeout = 30; +- break; +- case SPI: +- default: +- timeout = 10; +- break; +- } +- +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "TaskMgmt type=%d timeout=%ld\n", ioc->name, +- MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS, timeout)); ++ case FC: ++ timeout = 40; ++ break; ++ case SAS: ++ timeout = 30; ++ break; ++ case SPI: ++ default: ++ timeout = 2; ++ break; ++ } ++ ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "TaskMgmt type=%d timeout=%ld\n", ++ ioc->name, MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS, timeout)); + + INITIALIZE_MGMT_STATUS(ioc->taskmgmt_cmds.status) + CLEAR_MGMT_STATUS(ioc->internal_cmds.status) +@@ -1585,8 +1861,7 @@ + retval = mpt_send_handshake_request(ioc->TaskCtx, ioc, + sizeof(SCSITaskMgmt_t), (u32*)pScsiTm, CAN_SLEEP); + if (retval != 0) { +- dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "TaskMgmt send_handshake FAILED!" ++ dfailprintk(ioc, printk(MYIOC_s_ERR_FMT "TaskMgmt send_handshake FAILED!" + " (ioc %p, mf %p, rc=%d) \n", ioc->name, + ioc, mf, retval)); + mpt_clear_taskmgmt_in_progress_flag(ioc); +@@ -1641,165 +1916,6 @@ + return retval; + } + +-int +-mptscsih_ioc_reset(MPT_ADAPTER *ioc, int reset_phase) +-{ +- MPT_SCSI_HOST *hd; +- +- if ((ioc->sh == NULL) || (ioc->sh->hostdata == NULL)) +- return 0; +- +- switch (reset_phase) { +- case MPT_IOC_SETUP_RESET: +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__)); +- break; +- case MPT_IOC_PRE_RESET: +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__)); +- hd = shost_priv(ioc->sh); +- mptscsih_flush_running_cmds(hd); +- break; +- case MPT_IOC_POST_RESET: +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__)); +- if (ioc->internal_cmds.status & MPT_MGMT_STATUS_PENDING) { +- ioc->internal_cmds.status +- |= MPT_MGMT_STATUS_DID_IOCRESET; +- complete(&ioc->internal_cmds.done); +- } +- break; +- default: +- break; +- } +- return 1; /* currently means nothing really */ +-} +- +-void +-mptscsih_taskmgmt_response_code(MPT_ADAPTER *ioc, u8 response_code) +-{ +- char *desc; +- +- switch (response_code) { +- case MPI_SCSITASKMGMT_RSP_TM_COMPLETE: +- desc = "The task completed."; +- break; +- case MPI_SCSITASKMGMT_RSP_INVALID_FRAME: +- desc = "The IOC received an invalid frame status."; +- break; +- case MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED: +- desc = "The task type is not supported."; +- break; +- case MPI_SCSITASKMGMT_RSP_TM_FAILED: +- desc = "The requested task failed."; +- break; +- case MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED: +- desc = "The task completed successfully."; +- break; +- case MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN: +- desc = "The LUN request is invalid."; +- break; +- case MPI_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC: +- desc = "The task is in the IOC queue and has not been sent to target."; +- break; +- default: +- desc = "unknown"; +- break; +- } +- printk(MYIOC_s_DEBUG_FMT "Response Code(0x%08x): F/W: %s\n", +- ioc->name, response_code, desc); +-} +- +-static int +-mptscsih_taskmgmt_reply(MPT_ADAPTER *ioc, u8 type, +- SCSITaskMgmtReply_t *pScsiTmReply) +-{ +- u16 iocstatus; +- u32 termination_count; +- int retval; +- +- if (!(ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_RF_VALID)) { +- retval = FAILED; +- goto out; +- } +- +- DBG_DUMP_TM_REPLY_FRAME(ioc, (u32 *)pScsiTmReply); +- +- iocstatus = le16_to_cpu(pScsiTmReply->IOCStatus) & MPI_IOCSTATUS_MASK; +- termination_count = le32_to_cpu(pScsiTmReply->TerminationCount); +- +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "TaskMgmt fw_channel = %d, fw_id = %d, task_type = 0x%02X,\n" +- "\tiocstatus = 0x%04X, loginfo = 0x%08X, response_code = 0x%02X,\n" +- "\tterm_cmnds = %d\n", ioc->name, pScsiTmReply->Bus, +- pScsiTmReply->TargetID, type, le16_to_cpu(pScsiTmReply->IOCStatus), +- le32_to_cpu(pScsiTmReply->IOCLogInfo), pScsiTmReply->ResponseCode, +- termination_count)); +- +- if (ioc->facts.MsgVersion >= MPI_VERSION_01_05 && +- pScsiTmReply->ResponseCode) +- mptscsih_taskmgmt_response_code(ioc, +- pScsiTmReply->ResponseCode); +- +- if (iocstatus == MPI_IOCSTATUS_SUCCESS) { +- retval = 0; +- goto out; +- } +- +- retval = FAILED; +- if (type == MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK) { +- if (termination_count == 1) +- retval = 0; +- goto out; +- } +- +- if (iocstatus == MPI_IOCSTATUS_SCSI_TASK_TERMINATED || +- iocstatus == MPI_IOCSTATUS_SCSI_IOC_TERMINATED) +- retval = 0; +- +- out: +- return retval; +-} +- +-/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** +- * mptscsih_taskmgmt_complete - Registered with Fusion MPT base driver +- * @ioc: Pointer to MPT_ADAPTER structure +- * @mf: Pointer to SCSI task mgmt request frame +- * @mr: Pointer to SCSI task mgmt reply frame +- * +- * This routine is called from mptbase.c::mpt_interrupt() at the completion +- * of any SCSI task management request. +- * This routine is registered with the MPT (base) driver at driver +- * load/init time via the mpt_register() API call. +- * +- * Returns 1 indicating alloc'd request frame ptr should be freed. +- **/ +-int +-mptscsih_taskmgmt_complete(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf, +- MPT_FRAME_HDR *mr) +-{ +- dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "TaskMgmt completed (mf=%p, mr=%p)\n", +- ioc->name, mf, mr)); +- +- ioc->taskmgmt_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD; +- +- if (!mr) +- goto out; +- +- ioc->taskmgmt_cmds.status |= MPT_MGMT_STATUS_RF_VALID; +- memcpy(ioc->taskmgmt_cmds.reply, mr, +- min(MPT_DEFAULT_FRAME_SIZE, 4 * mr->u.reply.MsgLength)); +- out: +- if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) { +- mpt_clear_taskmgmt_in_progress_flag(ioc); +- ioc->taskmgmt_cmds.status &= ~MPT_MGMT_STATUS_PENDING; +- complete(&ioc->taskmgmt_cmds.done); +- return 1; +- } +- return 0; +-} +- + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** + * mptscsih_IssueTaskMgmt - Generic send Task Management function. +@@ -1820,14 +1936,13 @@ + * + **/ + int +-mptscsih_IssueTaskMgmt(MPT_SCSI_HOST *hd, u8 type, u8 channel, u8 id, int lun, +- int ctx2abort, ulong timeout) +-{ +- MPT_FRAME_HDR *mf = NULL; ++mptscsih_IssueTaskMgmt(MPT_SCSI_HOST *hd, u8 type, u8 channel, u8 id, int lun, int ctx2abort, ulong timeout) ++{ ++ MPT_FRAME_HDR *mf; + SCSITaskMgmt_t *pScsiTm; + int ii; + int retval; +- MPT_ADAPTER *ioc = hd->ioc; ++ MPT_ADAPTER *ioc = hd->ioc; + unsigned long timeleft; + u8 issue_hard_reset; + u32 ioc_raw_state; +@@ -1858,7 +1973,7 @@ + + mutex_lock(&ioc->taskmgmt_cmds.mutex); + if (mpt_set_taskmgmt_in_progress_flag(ioc) != 0) { +- mutex_unlock(&ioc->taskmgmt_cmds.mutex); ++ mf = NULL; + retval = FAILED; + goto out; + } +@@ -1867,8 +1982,7 @@ + */ + if ((mf = mpt_get_msg_frame(ioc->TaskCtx, ioc)) == NULL) { + dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "TaskMgmt no msg frames!!\n", +- ioc->name)); ++ "TaskMgmt no msg frames!!\n", ioc->name)); + retval = FAILED; + mpt_clear_taskmgmt_in_progress_flag(ioc); + goto out; +@@ -1888,18 +2002,18 @@ + pScsiTm->TaskType = type; + pScsiTm->Reserved1 = 0; + pScsiTm->MsgFlags = (type == MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS) +- ? MPI_SCSITASKMGMT_MSGFLAGS_LIPRESET_RESET_OPTION : 0; ++ ? MPI_SCSITASKMGMT_MSGFLAGS_LIPRESET_RESET_OPTION : 0; + + int_to_scsilun(lun, (struct scsi_lun *)pScsiTm->LUN); + +- for (ii = 0; ii < 7; ii++) ++ for (ii=0; ii < 7; ii++) + pScsiTm->Reserved2[ii] = 0; + + pScsiTm->TaskMsgContext = ctx2abort; + + dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "TaskMgmt: ctx2abort (0x%08x) " +- "task_type = 0x%02X, timeout = %ld\n", ioc->name, ctx2abort, +- type, timeout)); ++ "task_type = 0x%02X, timeout = %ld\n", ioc->name, ctx2abort, ++ type, timeout)); + + DBG_DUMP_TM_REQUEST_FRAME(ioc, (u32 *)pScsiTm); + +@@ -1910,11 +2024,11 @@ + mpt_put_msg_frame_hi_pri(ioc->TaskCtx, ioc, mf); + else { + retval = mpt_send_handshake_request(ioc->TaskCtx, ioc, +- sizeof(SCSITaskMgmt_t), (u32 *)pScsiTm, CAN_SLEEP); ++ sizeof(SCSITaskMgmt_t), (u32*)pScsiTm, CAN_SLEEP); + if (retval) { + dfailprintk(ioc, printk(MYIOC_s_ERR_FMT +- "TaskMgmt handshake FAILED!" +- " (mf=%p, rc=%d) \n", ioc->name, mf, retval)); ++ "TaskMgmt handshake FAILED!(mf=%p, rc=%d) \n", ++ ioc->name, mf, retval)); + mpt_free_msg_frame(ioc, mf); + mpt_clear_taskmgmt_in_progress_flag(ioc); + goto out; +@@ -1922,7 +2036,7 @@ + } + + timeleft = wait_for_completion_timeout(&ioc->taskmgmt_cmds.done, +- timeout*HZ); ++ timeout*HZ); + if (!(ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { + retval = FAILED; + dtmprintk(ioc, printk(MYIOC_s_ERR_FMT +@@ -1946,7 +2060,7 @@ + CLEAR_MGMT_STATUS(ioc->taskmgmt_cmds.status) + if (issue_hard_reset) { + printk(MYIOC_s_WARN_FMT "Issuing Reset from %s!!\n", +- ioc->name, __func__); ++ ioc->name, __func__); + if ((retval = mpt_SoftResetHandler(ioc, CAN_SLEEP)) != 0) + retval = mpt_HardResetHandler(ioc, CAN_SLEEP); + mpt_free_msg_frame(ioc, mf); +@@ -1990,11 +2104,11 @@ + int retval; + VirtDevice *vdevice; + ulong sn = SCpnt->serial_number; +- MPT_ADAPTER *ioc; ++ MPT_ADAPTER *ioc; + + /* If we can't locate our host adapter structure, return FAILED status. + */ +- if ((hd = shost_priv(SCpnt->device->host)) == NULL) { ++ if ((hd = shost_private(SCpnt->device->host)) == NULL) { + SCpnt->result = DID_RESET << 16; + SCpnt->scsi_done(SCpnt); + printk(KERN_ERR MYNAM ": task abort: " +@@ -2070,9 +2184,12 @@ + */ + mf = MPT_INDEX_2_MFPTR(ioc, scpnt_idx); + ctx2abort = mf->u.frame.hwhdr.msgctxu.MsgContext; +- mptscsih_IssueTaskMgmt(hd, MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK, +- vdevice->vtarget->channel, vdevice->vtarget->id, vdevice->lun, +- ctx2abort, mptscsih_get_tm_timeout(ioc)); ++ retval = mptscsih_IssueTaskMgmt(hd, ++ MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK, ++ vdevice->vtarget->channel, ++ vdevice->vtarget->id, vdevice->lun, ++ ctx2abort, mptscsih_get_tm_timeout(ioc)); ++ + + /* check to see whether command actually completed and/or + * terminated +@@ -2092,7 +2209,7 @@ + + out: + printk(MYIOC_s_INFO_FMT "task abort: %s (sc=%p)\n", +- ioc->name, ((retval == SUCCESS) ? "SUCCESS" : "FAILED"), SCpnt); ++ ioc->name, ((retval == SUCCESS) ? "SUCCESS" : "FAILED" ), SCpnt); + + return retval; + } +@@ -2116,7 +2233,7 @@ + + /* If we can't locate our host adapter structure, return FAILED status. + */ +- if ((hd = shost_priv(SCpnt->device->host)) == NULL){ ++ if ((hd = shost_private(SCpnt->device->host)) == NULL){ + printk(KERN_ERR MYNAM ": target reset: " + "Can't locate host! (sc=%p)\n", SCpnt); + return FAILED; +@@ -2141,11 +2258,13 @@ + } + + retval = mptscsih_IssueTaskMgmt(hd, +- MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET, vdevice->vtarget->channel, +- vdevice->vtarget->id, 0, 0, mptscsih_get_tm_timeout(ioc)); +- +- out: +- printk(MYIOC_s_INFO_FMT "target reset: %s (sc=%p)\n", ++ MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET, ++ vdevice->vtarget->channel, ++ vdevice->vtarget->id, 0, 0, ++ mptscsih_get_tm_timeout(ioc)); ++ ++ out: ++ printk (MYIOC_s_INFO_FMT "target reset: %s (sc=%p)\n", + ioc->name, ((retval == 0) ? "SUCCESS" : "FAILED" ), SCpnt); + + if (retval == 0) +@@ -2170,12 +2289,12 @@ + MPT_SCSI_HOST *hd; + int retval; + VirtDevice *vdevice; +- MPT_ADAPTER *ioc; ++ MPT_ADAPTER *ioc; + + /* If we can't locate our host adapter structure, return FAILED status. + */ +- if ((hd = shost_priv(SCpnt->device->host)) == NULL){ +- printk(KERN_ERR MYNAM ": bus_reset: " ++ if ((hd = shost_private(SCpnt->device->host)) == NULL){ ++ printk(KERN_ERR MYNAM ": bus reset: " + "Can't locate host! (sc=%p)\n", SCpnt); + return FAILED; + } +@@ -2191,8 +2310,10 @@ + vdevice = SCpnt->device->hostdata; + if (!vdevice || !vdevice->vtarget) + return SUCCESS; +- retval = mptscsih_IssueTaskMgmt(hd, MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS, +- vdevice->vtarget->channel, 0, 0, 0, mptscsih_get_tm_timeout(ioc)); ++ retval = mptscsih_IssueTaskMgmt(hd, ++ MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS, ++ vdevice->vtarget->channel, 0, 0, 0, ++ mptscsih_get_tm_timeout(ioc)); + + printk(MYIOC_s_INFO_FMT "bus reset: %s (sc=%p)\n", + ioc->name, ((retval == 0) ? "SUCCESS" : "FAILED" ), SCpnt); +@@ -2217,11 +2338,11 @@ + { + MPT_SCSI_HOST * hd; + int status = SUCCESS; +- MPT_ADAPTER *ioc; ++ MPT_ADAPTER *ioc; + int retval; + + /* If we can't locate the host to reset, then we failed. */ +- if ((hd = shost_priv(SCpnt->device->host)) == NULL){ ++ if ((hd = shost_private(SCpnt->device->host)) == NULL){ + printk(KERN_ERR MYNAM ": host reset: " + "Can't locate host! (sc=%p)\n", SCpnt); + return FAILED; +@@ -2229,7 +2350,7 @@ + + ioc = hd->ioc; + printk(MYIOC_s_INFO_FMT "attempting host reset! (sc=%p)\n", +- ioc->name, SCpnt); ++ ioc->name, SCpnt); + + /* If our attempts to reset the host failed, then return a failed + * status. The host will be taken off line by the SCSI mid-layer. +@@ -2248,10 +2369,137 @@ + return status; + } + +-/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** ++ ++static int ++mptscsih_taskmgmt_reply(MPT_ADAPTER *ioc, u8 type, ++ SCSITaskMgmtReply_t *pScsiTmReply) ++{ ++ u16 iocstatus; ++ u32 termination_count; ++ int retval; ++ ++ if (!(ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_RF_VALID)) { ++ retval = FAILED; ++ goto out; ++ } ++ ++ DBG_DUMP_TM_REPLY_FRAME(ioc, (u32 *)pScsiTmReply); ++ ++ iocstatus = le16_to_cpu(pScsiTmReply->IOCStatus) & MPI_IOCSTATUS_MASK; ++ termination_count = le32_to_cpu(pScsiTmReply->TerminationCount); ++ ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "TaskMgmt fw_channel = %d, fw_id = %d, task_type = 0x%02X,\n" ++ "\tiocstatus = 0x%04X, loginfo = 0x%08X, response_code = 0x%02X,\n" ++ "\tterm_cmnds = %d\n", ioc->name, pScsiTmReply->Bus, ++ pScsiTmReply->TargetID, type, le16_to_cpu(pScsiTmReply->IOCStatus), ++ le32_to_cpu(pScsiTmReply->IOCLogInfo), pScsiTmReply->ResponseCode, ++ termination_count)); ++ ++ if (ioc->facts.MsgVersion >= MPI_VERSION_01_05 && ++ pScsiTmReply->ResponseCode) ++ mptscsih_taskmgmt_response_code(ioc, ++ pScsiTmReply->ResponseCode); ++ ++ if (iocstatus == MPI_IOCSTATUS_SUCCESS) { ++ retval = 0; ++ goto out; ++ } ++ ++ retval = FAILED; ++ if (type == MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK) { ++ if (termination_count == 1) ++ retval = 0; ++ goto out; ++ } ++ ++ if (iocstatus == MPI_IOCSTATUS_SCSI_TASK_TERMINATED || ++ iocstatus == MPI_IOCSTATUS_SCSI_IOC_TERMINATED) ++ retval = 0; ++ ++ out: ++ return retval; ++} ++ ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ ++void ++mptscsih_taskmgmt_response_code(MPT_ADAPTER *ioc, u8 response_code) ++{ ++ char *desc; ++ ++ switch (response_code) { ++ case MPI_SCSITASKMGMT_RSP_TM_COMPLETE: ++ desc = "The task completed."; ++ break; ++ case MPI_SCSITASKMGMT_RSP_INVALID_FRAME: ++ desc = "The IOC received an invalid frame status."; ++ break; ++ case MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED: ++ desc = "The task type is not supported."; ++ break; ++ case MPI_SCSITASKMGMT_RSP_TM_FAILED: ++ desc = "The requested task failed."; ++ break; ++ case MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED: ++ desc = "The task completed successfully."; ++ break; ++ case MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN: ++ desc = "The LUN request is invalid."; ++ break; ++ case MPI_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC: ++ desc = "The task is in the IOC queue and has not been sent to target."; ++ break; ++ default: ++ desc = "unknown"; ++ break; ++ } ++ printk(MYIOC_s_INFO_FMT "Response Code(0x%08x): F/W: %s\n", ++ ioc->name, response_code, desc); ++} ++ ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ ++/** ++ * mptscsih_taskmgmt_complete - Registered with Fusion MPT base driver ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * @mf: Pointer to SCSI task mgmt request frame ++ * @mr: Pointer to SCSI task mgmt reply frame ++ * ++ * This routine is called from mptbase.c::mpt_interrupt() at the completion ++ * of any SCSI task management request. ++ * This routine is registered with the MPT (base) driver at driver ++ * load/init time via the mpt_register() API call. ++ * ++ * Returns 1 indicating alloc'd request frame ptr should be freed. ++ **/ ++int ++mptscsih_taskmgmt_complete(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf, ++ MPT_FRAME_HDR *mr) ++{ ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "TaskMgmt completed (mf=%p, mr=%p)\n", ioc->name, mf, mr)); ++ ++ ioc->taskmgmt_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD; ++ ++ if (!mr) ++ goto out; ++ ++ ioc->taskmgmt_cmds.status |= MPT_MGMT_STATUS_RF_VALID; ++ memcpy(ioc->taskmgmt_cmds.reply, mr, ++ min(MPT_DEFAULT_FRAME_SIZE, 4 * mr->u.reply.MsgLength)); ++ out: ++ if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) { ++ mpt_clear_taskmgmt_in_progress_flag(ioc); ++ ioc->taskmgmt_cmds.status &= ~MPT_MGMT_STATUS_PENDING; ++ complete(&ioc->taskmgmt_cmds.done); ++ return 1; ++ } ++ return 0; ++} ++ ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ ++/* + * This is anyones guess quite frankly. +- **/ ++ */ + int + mptscsih_bios_param(struct scsi_device * sdev, struct block_device *bdev, + sector_t capacity, int geom[]) +@@ -2291,7 +2539,7 @@ + /** + * Search IOC page 3 to determine if this is hidden physical disk + * +- **/ ++ */ + int + mptscsih_is_phys_disk(MPT_ADAPTER *ioc, u8 channel, u8 id) + { +@@ -2305,8 +2553,7 @@ + goto out; + for (i = 0; i < ioc->raid_data.pIocPg3->NumPhysDisks; i++) { + if ((id == ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskID) && +- (channel == +- ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskBus)) { ++ (channel == ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskBus)) { + rc = 1; + goto out; + } +@@ -2323,7 +2570,7 @@ + ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskNum); + if (num_paths < 2) + continue; +- phys_disk = kzalloc(offsetof(RaidPhysDiskPage1_t, Path) + ++ phys_disk = kzalloc(offsetof(RaidPhysDiskPage1_t,Path) + + (num_paths * sizeof(RAID_PHYS_DISK1_PATH)), GFP_KERNEL); + if (!phys_disk) + continue; +@@ -2356,14 +2603,14 @@ + if (list_empty(&ioc->raid_data.inactive_list)) + goto out; + +- mutex_lock(&ioc->raid_data.inactive_list_mutex); ++ down(&ioc->raid_data.inactive_list_mutex); + list_for_each_entry(component_info, &ioc->raid_data.inactive_list, + list) { + if ((component_info->d.PhysDiskID == id) && + (component_info->d.PhysDiskBus == channel)) + rc = 1; + } +- mutex_lock(&ioc->raid_data.inactive_list_mutex); ++ up(&ioc->raid_data.inactive_list_mutex); + + out: + return rc; +@@ -2374,7 +2621,7 @@ + mptscsih_raid_id_to_num(MPT_ADAPTER *ioc, u8 channel, u8 id) + { + struct inactive_raid_component_info *component_info; +- int i, j; ++ int i,j; + RaidPhysDiskPage1_t *phys_disk; + int rc = -ENXIO; + u8 num_paths; +@@ -2383,8 +2630,7 @@ + goto out; + for (i = 0; i < ioc->raid_data.pIocPg3->NumPhysDisks; i++) { + if ((id == ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskID) && +- (channel == +- ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskBus)) { ++ (channel == ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskBus)) { + rc = ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskNum; + goto out; + } +@@ -2401,7 +2647,7 @@ + ioc->raid_data.pIocPg3->PhysDisk[i].PhysDiskNum); + if (num_paths < 2) + continue; +- phys_disk = kzalloc(offsetof(RaidPhysDiskPage1_t, Path) + ++ phys_disk = kzalloc(offsetof(RaidPhysDiskPage1_t,Path) + + (num_paths * sizeof(RAID_PHYS_DISK1_PATH)), GFP_KERNEL); + if (!phys_disk) + continue; +@@ -2434,29 +2680,29 @@ + if (list_empty(&ioc->raid_data.inactive_list)) + goto out; + +- mutex_lock(&ioc->raid_data.inactive_list_mutex); ++ down(&ioc->raid_data.inactive_list_mutex); + list_for_each_entry(component_info, &ioc->raid_data.inactive_list, + list) { + if ((component_info->d.PhysDiskID == id) && + (component_info->d.PhysDiskBus == channel)) + rc = component_info->d.PhysDiskNum; + } +- mutex_unlock(&ioc->raid_data.inactive_list_mutex); ++ up(&ioc->raid_data.inactive_list_mutex); + + out: + return rc; + } + EXPORT_SYMBOL(mptscsih_raid_id_to_num); + +-/** ++/* + * OS entry point to allow for host driver to free allocated memory + * Called if no device present or device being unloaded +- **/ ++ */ + void + mptscsih_slave_destroy(struct scsi_device *sdev) + { + struct Scsi_Host *host = sdev->host; +- MPT_SCSI_HOST *hd = shost_priv(host); ++ MPT_SCSI_HOST *hd = shost_private(host); + VirtTarget *vtarget; + VirtDevice *vdevice; + struct scsi_target *starget; +@@ -2475,17 +2721,17 @@ + } + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** ++/* + * mptscsih_change_queue_depth - This function will set a devices queue depth + * @sdev: per scsi_device pointer + * @qdepth: requested queue depth + * + * Adding support for new 'change_queue_depth' api. +- **/ ++*/ + int + mptscsih_change_queue_depth(struct scsi_device *sdev, int qdepth) + { +- MPT_SCSI_HOST *hd = shost_priv(sdev->host); ++ MPT_SCSI_HOST *hd = shost_private(sdev->host); + VirtTarget *vtarget; + struct scsi_target *starget; + int max_depth; +@@ -2527,12 +2773,115 @@ + return sdev->queue_depth; + } + +-/** ++#ifdef EEDP_SUPPORT ++/** ++ * _scsih_read_capacity_16 - send READ_CAPACITY_16 to target ++ * ++ */ ++static int ++_scsih_read_capacity_16(MPT_SCSI_HOST *hd, int id, int channel, u32 lun, ++ void *data, u32 length) ++{ ++ INTERNAL_CMD iocmd; ++ dma_addr_t data_dma; ++ struct read_cap_parameter *parameter_data; ++ u32 data_length; ++ MPT_ADAPTER *ioc = hd->ioc; ++ int rc; ++ int count; ++ u8 skey; ++ u8 asc; ++ u8 ascq; ++ ++ data_length = sizeof(struct read_cap_parameter); ++ parameter_data = pci_alloc_consistent(ioc->pcidev, ++ data_length, &data_dma); ++ if (!parameter_data) { ++ printk(MYIOC_s_ERR_FMT "failure at %s:%d/%s()!\n", ++ ioc->name, __FILE__, __LINE__, __func__); ++ return -1; ++ } ++ ++ iocmd.cmd = SERVICE_ACTION_IN; ++ iocmd.data_dma = data_dma; ++ iocmd.data = (u8 *)parameter_data; ++ iocmd.size = data_length; ++ iocmd.channel = channel; ++ iocmd.id = id; ++ iocmd.lun = lun; ++ ++ for (count=0; count < 4; count++) { ++ rc = mptscsih_do_cmd(hd, &iocmd); ++ ++ if(rc == MPT_SCANDV_GOOD) { ++ memcpy(data, parameter_data, ++ min_t(u32, data_length, length)); ++ break; ++ } else if(rc == MPT_SCANDV_BUSY) { ++ devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: " ++ "fw_channel=%d fw_id=%d : device busy\n", ++ ioc->name, __FUNCTION__, channel, id)); ++ continue; ++ } else if(rc == MPT_SCANDV_DID_RESET) { ++ devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: " ++ "fw_channel=%d fw_id=%d : did reset\n", ++ ioc->name, __FUNCTION__, channel, id)); ++ continue; ++ } else if(rc == MPT_SCANDV_SENSE) { ++ skey = ioc->internal_cmds.sense[2] & 0x0F; ++ asc = ioc->internal_cmds.sense[12]; ++ ascq = ioc->internal_cmds.sense[13]; ++ devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: " ++ "fw_channel=%d fw_id=%d : [sense_key,arc,ascq]: " ++ "[0x%02x,0x%02x,0x%02x]\n", ioc->name, ++ __FUNCTION__, channel, id, skey, asc, ascq)); ++ if( skey == UNIT_ATTENTION || ++ skey == NOT_READY || ++ skey == ILLEGAL_REQUEST ) { ++ continue; ++ } else { ++ printk(MYIOC_s_ERR_FMT "%s: fw_channel=%d fw_id=%d : " ++ "tur failed due to [sense_key,asc,ascq]: " ++ "[0x%02x,0x%02x,0x%02x]\n", ioc->name, ++ __FUNCTION__, channel, id, skey, asc, ascq); ++ break; ++ } ++ } else if(rc == MPT_SCANDV_SELECTION_TIMEOUT) { ++ printk(MYIOC_s_ERR_FMT "%s: fw_channel=%d fw_id=%d: " ++ "read capacity failed due to no device\n", ioc->name, ++ __FUNCTION__, channel, id); ++ break; ++ } else if(rc == MPT_SCANDV_SOME_ERROR) { ++ printk(MYIOC_s_ERR_FMT "%s: fw_channel=%d fw_id=%d: " ++ "read capacity failed due to some error\n", ioc->name, ++ __FUNCTION__, channel, id); ++ break; ++ } else { ++ printk(MYIOC_s_ERR_FMT "%s: fw_channel=%d fw_id=%d: " ++ "read capacity failed due to some error\n", ioc->name, ++ __FUNCTION__, channel, id); ++ break; ++ } ++ ++ } ++ ++ if(count > 4 && rc != 0) { ++ printk(MYIOC_s_ERR_FMT "%s: fw_channel=%d fw_id=%d: " ++ "read capacity failed to many times\n", ioc->name, ++ __FUNCTION__, channel, id); ++ } ++ ++ pci_free_consistent(ioc->pcidev, data_length, parameter_data, data_dma); ++ return rc; ++} ++#endif ++ ++/* + * OS entry point to adjust the queue_depths on a per-device basis. + * Called once per device the bus scan. Use it to force the queue_depth + * member to 1 if a device does not support Q tags. + * Return non-zero if fails. +- **/ ++ */ + int + mptscsih_slave_configure(struct scsi_device *sdev) + { +@@ -2540,12 +2889,61 @@ + VirtTarget *vtarget; + VirtDevice *vdevice; + struct scsi_target *starget; +- MPT_SCSI_HOST *hd = shost_priv(sh); +- MPT_ADAPTER *ioc = hd->ioc; ++ MPT_SCSI_HOST *hd = shost_private(sh); ++ MPT_ADAPTER *ioc = hd->ioc; + + starget = scsi_target(sdev); + vtarget = starget->hostdata; + vdevice = sdev->hostdata; ++ ++#ifdef EEDP_SUPPORT ++ if ((!(vdevice->vtarget->tflags & MPT_TARGET_FLAGS_RAID_COMPONENT)) && ++ (!(vdevice->vtarget->raidVolume))) { ++ ++ struct read_cap_parameter data; ++ memset(&data, 0, sizeof(struct read_cap_parameter)); ++ ++ /* ++ * check PROTECT bit ++ * ++ * NOTE: The crack monkey target mode driver doesn't ++ * set this bit(bug has been reported). ++ * The cm_target command line option is a work around. ++ */ ++ if (!(sdev->inquiry[5] & 1)) ++ goto out; ++ ++ if ((ioc->bus_type == FC) && ++ (_scsih_read_capacity_16(hd, vtarget->id, ++ vtarget->channel, sdev->lun, &data, ++ sizeof(struct read_cap_parameter)) == 0)) { ++ vdevice->eedp_enable = data.prot_en; ++ vdevice->eedp_type = data.p_type; ++ vdevice->eedp_block_length = ++ be32_to_cpu(data.logical_block_length); ++ ++ if (!vdevice->eedp_enable) ++ goto out; ++ ++ sdev_printk(KERN_INFO, sdev, "EEDP enabled: " ++ "protection_type(%d), block_length(%d)\n", ++ vdevice->eedp_type+1, ++ vdevice->eedp_block_length); ++ } ++ } ++ out: ++#endif /* EEDP Support */ ++ ++ ++ dsprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "device @ %p, channel=%d, id=%d, lun=%d\n", ++ ioc->name, sdev, sdev->channel, sdev->id, sdev->lun)); ++ if (ioc->bus_type == SPI) ++ dsprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "sdtr %d wdtr %d ppr %d inq length=%d\n", ++ ioc->name, sdev->sdtr, sdev->wdtr, ++ sdev->ppr, sdev->inquiry_len)); ++ + vdevice->configured_lun = 1; + + if ((ioc->bus_type != SAS) && (sdev->id > sh->max_id)) { +@@ -2553,25 +2951,37 @@ + scsi_adjust_queue_depth(sdev, 0, 1); + goto slave_configure_exit; + } ++ dsprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "Queue depth=%d, tflags=%x\n", ++ ioc->name, sdev->queue_depth, vtarget->tflags)); ++ ++ if (ioc->bus_type == SPI) ++ dsprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "negoFlags=%x, maxOffset=%x, SyncFactor=%x\n", ++ ioc->name, vtarget->negoFlags, vtarget->maxOffset, ++ vtarget->minSyncFactor)); + + mptscsih_change_queue_depth(sdev, ioc->sdev_queue_depth); + + slave_configure_exit: +- +- return 0; +-} +- +-/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** ++ dsprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "tagged %d, simple %d, ordered %d\n", ++ ioc->name,sdev->tagged_supported, sdev->simple_tags, ++ sdev->ordered_tags)); ++ ++ return 0; ++} ++ ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ ++/* + * Private routines... + */ + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +-/** +- * Utility function to copy sense data from the scsi_cmnd buffer ++/* Utility function to copy sense data from the scsi_cmnd buffer + * to the FC and SCSI target structures. + * +- **/ ++ */ + static void + mptscsih_copy_sense_data(struct scsi_cmnd *sc, MPT_SCSI_HOST *hd, MPT_FRAME_HDR *mf, SCSIIOReply_t *pScsiReply) + { +@@ -2593,11 +3003,14 @@ + req_index = le16_to_cpu(mf->u.frame.hwhdr.msgctxu.fld.req_idx); + sense_data = ((u8 *)ioc->sense_buf_pool + (req_index * MPT_SENSE_BUFFER_ALLOC)); + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,24)) + if (sense_count > SCSI_SENSE_BUFFERSIZE) +- sense_count = SCSI_SENSE_BUFFERSIZE; ++ sense_count = SCSI_SENSE_BUFFERSIZE; + + memcpy(sc->sense_buffer, sense_data, sense_count); +- ++#else ++ memcpy(sc->sense_buffer, sense_data, SNS_LEN(sc)); ++#endif + /* Log SMART data (asc = 0x5D, non-IM case only) if required. + */ + if ((ioc->events) && (ioc->eventTypes & (1 << MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE))) { +@@ -2616,17 +3029,15 @@ + + ioc->eventContext++; + if (ioc->pcidev->vendor == PCI_VENDOR_ID_IBM) { +- mptscsih_issue_sep_command(ioc, +- vdevice->vtarget, ++ mptscsih_issue_sep_command(ioc, vdevice->vtarget, + MPI_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT); +- vdevice->vtarget->tflags |= +- MPT_TARGET_FLAGS_LED_ON; ++ vdevice->vtarget->tflags |= MPT_TARGET_FLAGS_LED_ON; + } + } + } + } else { + dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Hmmm... SenseData len=0! (?)\n", +- ioc->name)); ++ ioc->name)); + } + } + +@@ -2700,14 +3111,10 @@ + } + + /** +- * SCPNT_TO_LOOKUP_IDX +- * +- * search's for a given scmd in the ScsiLookup[] array list +- * ++ * SCPNT_TO_LOOKUP_IDX - searches for a given scmd in the ScsiLookup[] array list + * @ioc: Pointer to MPT_ADAPTER structure +- * @scmd: scsi_cmnd pointer +- * +- **/ ++ * @sc: scsi_cmnd pointer ++ */ + static int + SCPNT_TO_LOOKUP_IDX(MPT_ADAPTER *ioc, struct scsi_cmnd *sc) + { +@@ -2729,13 +3136,48 @@ + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + int ++mptscsih_ioc_reset(MPT_ADAPTER *ioc, int reset_phase) ++{ ++ MPT_SCSI_HOST *hd; ++ ++ if ((ioc->sh == NULL) || (ioc->sh->hostdata == NULL)) ++ return 0; ++ ++ hd = shost_private(ioc->sh); ++ switch (reset_phase) { ++ case MPT_IOC_SETUP_RESET: ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__)); ++ break; ++ case MPT_IOC_PRE_RESET: ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__)); ++ mptscsih_flush_running_cmds(hd); ++ break; ++ case MPT_IOC_POST_RESET: ++ dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT ++ "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__)); ++ if (ioc->internal_cmds.status & MPT_MGMT_STATUS_PENDING) { ++ ioc->internal_cmds.status |= ++ MPT_MGMT_STATUS_DID_IOCRESET; ++ complete(&ioc->internal_cmds.done); ++ } ++ break; ++ default: ++ break; ++ } ++ return 1; /* currently means nothing really */ ++} ++ ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ ++int + mptscsih_event_process(MPT_ADAPTER *ioc, EventNotificationReply_t *pEvReply) + { + u8 event = le32_to_cpu(pEvReply->Event) & 0xFF; + + devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "MPT event (=%02Xh) routed to SCSI host driver!\n", +- ioc->name, event)); ++ "MPT event (=%02Xh) routed to SCSI host driver!\n", ++ ioc->name, event)); + + if ((event == MPI_EVENT_IOC_BUS_RESET || + event == MPI_EVENT_EXT_BUS_RESET) && +@@ -2745,74 +3187,73 @@ + return 1; /* currently means nothing really */ + } + +-int +-mptscsih_quiesce_raid(MPT_SCSI_HOST *hd, int quiesce, u8 channel, u8 id) +-{ +- MPT_ADAPTER *ioc = hd->ioc; +- MpiRaidActionRequest_t *pReq; +- MPT_FRAME_HDR *mf; +- int ret; +- unsigned long timeleft; +- +- mutex_lock(&ioc->internal_cmds.mutex); +- +- /* Get and Populate a free Frame +- */ +- if ((mf = mpt_get_msg_frame(ioc->InternalCtx, ioc)) == NULL) { +- dfailprintk(hd->ioc, printk(MYIOC_s_WARN_FMT +- "%s: no msg frames!\n", +- ioc->name, __func__)); +- ret = -EAGAIN; +- goto out; +- } +- pReq = (MpiRaidActionRequest_t *)mf; +- if (quiesce) +- pReq->Action = MPI_RAID_ACTION_QUIESCE_PHYS_IO; +- else +- pReq->Action = MPI_RAID_ACTION_ENABLE_PHYS_IO; +- pReq->Reserved1 = 0; +- pReq->ChainOffset = 0; +- pReq->Function = MPI_FUNCTION_RAID_ACTION; +- pReq->VolumeID = id; +- pReq->VolumeBus = channel; +- pReq->PhysDiskNum = 0; +- pReq->MsgFlags = 0; +- pReq->Reserved2 = 0; +- pReq->ActionDataWord = 0; /* Reserved for this action */ +- +- ioc->add_sge((char *)&pReq->ActionDataSGE, +- MPT_SGE_FLAGS_SSIMPLE_READ | 0, (dma_addr_t) -1); +- +- ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "RAID Volume action=%x channel=%d id=%d\n", +- ioc->name, pReq->Action, channel, id)); +- +- INITIALIZE_MGMT_STATUS(ioc->internal_cmds.status) +- mpt_put_msg_frame(ioc->InternalCtx, ioc, mf); +- timeleft = wait_for_completion_timeout(&ioc->internal_cmds.done, 10*HZ); +- if (!(ioc->internal_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { +- ret = -ETIME; +- dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: TIMED OUT!\n", +- ioc->name, __func__)); +- if (ioc->internal_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) +- goto out; +- if (!timeleft) { +- printk(MYIOC_s_WARN_FMT "Issuing Reset from %s!!\n", +- ioc->name, __func__); +- if (mpt_SoftResetHandler(ioc, CAN_SLEEP) != 0) +- mpt_HardResetHandler(ioc, CAN_SLEEP); +- mpt_free_msg_frame(ioc, mf); +- } +- goto out; +- } +- +- ret = ioc->internal_cmds.completion_code; +- +- out: +- CLEAR_MGMT_STATUS(ioc->internal_cmds.status) +- mutex_unlock(&ioc->internal_cmds.mutex); +- return ret; +-} ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ ++/* ++ * Bus Scan and Domain Validation functionality ... ++ */ ++ ++/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ ++/* ++ * mptscsih_scandv_complete - Scan and DV callback routine registered ++ * to Fustion MPT (base) driver. ++ * ++ * @ioc: Pointer to MPT_ADAPTER structure ++ * @mf: Pointer to original MPT request frame ++ * @mr: Pointer to MPT reply frame (NULL if TurboReply) ++ * ++ * This routine is called from mpt.c::mpt_interrupt() at the completion ++ * of any SCSI IO request. ++ * This routine is registered with the Fusion MPT (base) driver at driver ++ * load/init time via the mpt_register() API call. ++ * ++ * Returns 1 indicating alloc'd request frame ptr should be freed. ++ * ++ * Remark: Sets a completion code and (possibly) saves sense data ++ * in the IOC member localReply structure. ++ * Used ONLY for DV and other internal commands. ++ */ ++int ++mptscsih_scandv_complete(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, ++ MPT_FRAME_HDR *reply) ++{ ++ SCSIIORequest_t *pReq; ++ SCSIIOReply_t *pReply; ++ u8 cmd; ++ u16 req_idx; ++ u8 *sense_data; ++ int sz; ++ ++ ioc->internal_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD; ++ ioc->internal_cmds.completion_code = MPT_SCANDV_GOOD; ++ if (!reply) ++ goto out; ++ ++ pReply = (SCSIIOReply_t *) reply; ++ pReq = (SCSIIORequest_t *) req; ++ ioc->internal_cmds.completion_code = ++ mptscsih_get_completion_code(ioc, req, reply); ++ ioc->internal_cmds.status |= MPT_MGMT_STATUS_RF_VALID; ++ memcpy(ioc->internal_cmds.reply, reply, ++ min(MPT_DEFAULT_FRAME_SIZE, 4 * reply->u.reply.MsgLength)); ++ cmd = reply->u.hdr.Function; ++ if (((cmd == MPI_FUNCTION_SCSI_IO_REQUEST) || ++ (cmd == MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) && ++ (pReply->SCSIState & MPI_SCSI_STATE_AUTOSENSE_VALID)) { ++ req_idx = le16_to_cpu(req->u.frame.hwhdr.msgctxu.fld.req_idx); ++ sense_data = ((u8 *)ioc->sense_buf_pool + ++ (req_idx * MPT_SENSE_BUFFER_ALLOC)); ++ sz = min_t(int, pReq->SenseBufferLength, ++ MPT_SENSE_BUFFER_ALLOC); ++ memcpy(ioc->internal_cmds.sense, sense_data, sz); ++ } ++ out: ++ if (!(ioc->internal_cmds.status & MPT_MGMT_STATUS_PENDING)) ++ return 0; ++ ioc->internal_cmds.status &= ~MPT_MGMT_STATUS_PENDING; ++ complete(&ioc->internal_cmds.done); ++ return 1; ++} ++ + + /** + * mptscsih_get_completion_code - +@@ -2823,7 +3264,7 @@ + **/ + static int + mptscsih_get_completion_code(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, +- MPT_FRAME_HDR *reply) ++ MPT_FRAME_HDR *reply) + { + SCSIIOReply_t *pReply; + MpiRaidActionReply_t *pr; +@@ -2837,9 +3278,8 @@ + + devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT + "IOCStatus=%04xh, SCSIState=%02xh, SCSIStatus=%02xh," +- " IOCLogInfo=%08xh\n", +- ioc->name, status, pReply->SCSIState, scsi_status, +- le32_to_cpu(pReply->IOCLogInfo))); ++ "IOCLogInfo=%08xh\n", ioc->name, status, pReply->SCSIState, ++ scsi_status, le32_to_cpu(pReply->IOCLogInfo))); + + switch (status) { + +@@ -2864,11 +3304,10 @@ + case MPI_IOCSTATUS_SUCCESS: /* 0x0000 */ + if (pReply->Function == MPI_FUNCTION_CONFIG) { + completion_code = MPT_SCANDV_GOOD; +- } else if (pReply->Function == +- MPI_FUNCTION_RAID_ACTION) { ++ } else if (pReply->Function == MPI_FUNCTION_RAID_ACTION) { + pr = (MpiRaidActionReply_t *)reply; + if (le16_to_cpu(pr->ActionStatus) == +- MPI_RAID_ACTION_ASTATUS_SUCCESS) ++ MPI_RAID_ACTION_ASTATUS_SUCCESS) + completion_code = MPT_SCANDV_GOOD; + else + completion_code = MPT_SCANDV_SOME_ERROR; +@@ -2906,55 +3345,6 @@ + return completion_code; + } + +-/** +- * mptscsih_scandv_complete - +- * @ioc: Pointer to MPT_ADAPTER structure +- * @req: +- * @reply: +- * +- **/ +-int +-mptscsih_scandv_complete(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, +- MPT_FRAME_HDR *reply) +-{ +- SCSIIORequest_t *pReq; +- SCSIIOReply_t *pReply; +- u8 cmd; +- u16 req_idx; +- u8 *sense_data; +- int sz; +- +- ioc->internal_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD; +- ioc->internal_cmds.completion_code = MPT_SCANDV_GOOD; +- if (!reply) +- goto out; +- +- pReply = (SCSIIOReply_t *) reply; +- pReq = (SCSIIORequest_t *) req; +- ioc->internal_cmds.completion_code = +- mptscsih_get_completion_code(ioc, req, reply); +- ioc->internal_cmds.status |= MPT_MGMT_STATUS_RF_VALID; +- memcpy(ioc->internal_cmds.reply, reply, +- min(MPT_DEFAULT_FRAME_SIZE, 4 * reply->u.reply.MsgLength)); +- cmd = reply->u.hdr.Function; +- if (((cmd == MPI_FUNCTION_SCSI_IO_REQUEST) || +- (cmd == MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) && +- (pReply->SCSIState & MPI_SCSI_STATE_AUTOSENSE_VALID)) { +- req_idx = le16_to_cpu(req->u.frame.hwhdr.msgctxu.fld.req_idx); +- sense_data = ((u8 *)ioc->sense_buf_pool + +- (req_idx * MPT_SENSE_BUFFER_ALLOC)); +- sz = min_t(int, pReq->SenseBufferLength, +- MPT_SENSE_BUFFER_ALLOC); +- memcpy(ioc->internal_cmds.sense, sense_data, sz); +- } +- out: +- if (!(ioc->internal_cmds.status & MPT_MGMT_STATUS_PENDING)) +- return 0; +- ioc->internal_cmds.status &= ~MPT_MGMT_STATUS_PENDING; +- complete(&ioc->internal_cmds.done); +- return 1; +-} +- + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** + * mptscsih_do_cmd - Do internal command. +@@ -2974,7 +3364,7 @@ + * 0 if good + * + * > 0 if command complete but some type of completion error. +- **/ ++ */ + int + mptscsih_do_cmd(MPT_SCSI_HOST *hd, INTERNAL_CMD *io) + { +@@ -2989,13 +3379,13 @@ + int ret = 0; + unsigned long timeleft; + unsigned long flags; +- ++ + /* don't send internal command during diag reset */ + spin_lock_irqsave(&ioc->taskmgmt_lock, flags); + if (ioc->ioc_reset_in_progress) { + spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); + dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "%s: busy with host reset\n", ioc->name, __func__)); ++ "%s: busy with host reset\n", ioc->name, __FUNCTION__)); + return MPT_SCANDV_BUSY; + } + spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); +@@ -3109,6 +3499,16 @@ + dir = MPI_SCSIIO_CONTROL_READ; + timeout = 10; + break; ++#ifdef EEDP_SUPPORT ++ case SERVICE_ACTION_IN: ++ CDB[0] = cmd; ++ CDB[1] = 0x10; ++ CDB[13] = io->size & 0xFF; ++ dir = MPI_SCSIIO_CONTROL_READ; ++ timeout = 10; ++ cmdLen = 16; ++ break; ++#endif + + default: + /* Error Case */ +@@ -3146,10 +3546,14 @@ + + pScsiReq->CDBLength = cmdLen; + pScsiReq->SenseBufferLength = MPT_SENSE_BUFFER_SIZE; ++ + pScsiReq->Reserved = 0; ++ + pScsiReq->MsgFlags = mpt_msg_flags(ioc); ++ /* MsgContext set in mpt_get_msg_fram call */ + + int_to_scsilun(io->lun, (struct scsi_lun *)pScsiReq->LUN); ++ + if (io->flags & MPT_ICFLAG_TAGGED_CMD) + pScsiReq->Control = cpu_to_le32(dir | MPI_SCSIIO_CONTROL_SIMPLEQ); + else +@@ -3214,6 +3618,73 @@ + return ret; + } + ++int ++mptscsih_quiesce_raid(MPT_SCSI_HOST *hd, int quiesce, u8 channel, u8 id) ++{ ++ MPT_ADAPTER *ioc = hd->ioc; ++ MpiRaidActionRequest_t *pReq; ++ MPT_FRAME_HDR *mf; ++ int ret; ++ unsigned long timeleft; ++ ++ mutex_lock(&ioc->internal_cmds.mutex); ++ ++ /* Get and Populate a free Frame ++ */ ++ if ((mf = mpt_get_msg_frame(ioc->InternalCtx, ioc)) == NULL) { ++ dfailprintk(hd->ioc, printk(MYIOC_s_WARN_FMT "%s: no msg frames!\n", ++ ioc->name, __FUNCTION__)); ++ ret = -EAGAIN; ++ goto out; ++ } ++ pReq = (MpiRaidActionRequest_t *)mf; ++ if (quiesce) ++ pReq->Action = MPI_RAID_ACTION_QUIESCE_PHYS_IO; ++ else ++ pReq->Action = MPI_RAID_ACTION_ENABLE_PHYS_IO; ++ pReq->Reserved1 = 0; ++ pReq->ChainOffset = 0; ++ pReq->Function = MPI_FUNCTION_RAID_ACTION; ++ pReq->VolumeID = id; ++ pReq->VolumeBus = channel; ++ pReq->PhysDiskNum = 0; ++ pReq->MsgFlags = 0; ++ pReq->Reserved2 = 0; ++ pReq->ActionDataWord = 0; /* Reserved for this action */ ++ ++ ioc->add_sge((char *)&pReq->ActionDataSGE, ++ MPT_SGE_FLAGS_SSIMPLE_READ | 0, (dma_addr_t) -1); ++ ++ ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RAID Volume action=%x channel=%d id=%d\n", ++ ioc->name, pReq->Action, channel, id)); ++ ++ INITIALIZE_MGMT_STATUS(ioc->internal_cmds.status) ++ mpt_put_msg_frame(ioc->InternalCtx, ioc, mf); ++ timeleft = wait_for_completion_timeout(&ioc->internal_cmds.done, 10*HZ); ++ if (!(ioc->internal_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { ++ ret = -ETIME; ++ dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: TIMED OUT!\n", ++ ioc->name, __FUNCTION__)); ++ if (ioc->internal_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) ++ goto out; ++ if (!timeleft) { ++ printk(MYIOC_s_WARN_FMT "Issuing Reset from %s!!\n", ++ ioc->name, __FUNCTION__); ++ if (mpt_SoftResetHandler(ioc, CAN_SLEEP) != 0) ++ mpt_HardResetHandler(ioc, CAN_SLEEP); ++ mpt_free_msg_frame(ioc, mf); ++ } ++ goto out; ++ } ++ ++ ret = ioc->internal_cmds.completion_code; ++ ++ out: ++ CLEAR_MGMT_STATUS(ioc->internal_cmds.status) ++ mutex_unlock(&ioc->internal_cmds.mutex); ++ return ret; ++} ++ + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ + /** + * mptscsih_synchronize_cache - Send SYNCHRONIZE_CACHE to all disks. +@@ -3225,8 +3696,7 @@ + * + */ + static void +-mptscsih_synchronize_cache(struct scsi_device *sdev, MPT_SCSI_HOST *hd, +- VirtDevice *vdevice) ++mptscsih_synchronize_cache(struct scsi_device *sdev, MPT_SCSI_HOST *hd, VirtDevice *vdevice) + { + INTERNAL_CMD iocmd; + MPT_ADAPTER *ioc = hd->ioc; +@@ -3250,21 +3720,164 @@ + iocmd.id = vdevice->vtarget->id; + iocmd.lun = vdevice->lun; + +- sdev_printk(KERN_INFO, sdev, MYIOC_s_FMT +- "SYNCHRONIZE_CACHE: fw_channel %d, fw_id %d\n", +- ioc->name, vdevice->vtarget->channel, vdevice->vtarget->id); ++ sdev_printk(KERN_INFO, sdev, MYIOC_s_FMT "SYNCHRONIZE_CACHE: fw_channel %d," ++ " fw_id %d\n", ioc->name, vdevice->vtarget->channel, vdevice->vtarget->id); + mptscsih_do_cmd(hd, &iocmd); + } + + /* + * shost attributes + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_fault_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else ++static ssize_t ++mptscsih_fault_show(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(dev); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); ++ MPT_ADAPTER *ioc = hd->ioc; ++ ++ return snprintf(buf, PAGE_SIZE, "%d\n", ioc->is_fault); ++} ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_fault_store(struct class_device *cdev, const char *buf, size_t count) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else ++static ssize_t ++mptscsih_fault_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct Scsi_Host *host = class_to_shost(dev); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); ++ MPT_ADAPTER *ioc = hd->ioc; ++ int val = 0; ++ ++ if (sscanf(buf, "%d", &val) != 1) ++ return -EINVAL; ++ ++ ioc->is_fault = val; ++ return strlen(buf); ++ ++} ++ ++struct DIAG_BUFFER_START { ++ u32 Size; ++ u32 DiagVersion; ++ u8 BufferType; ++ u8 Reserved[3]; ++ u32 Reserved1; ++ u32 Reserved2; ++ u32 Reserved3; ++}; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_ring_buffer_size_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else ++static ssize_t ++mptscsih_ring_buffer_size_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(dev); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); ++ MPT_ADAPTER *ioc = hd->ioc; ++ u32 size = 0; ++ struct DIAG_BUFFER_START *request_data; ++ ++ ioc->ring_buffer_sz = 0; ++ if (!ioc->DiagBuffer[0]) ++ return 0; ++ ++ request_data = (struct DIAG_BUFFER_START *)ioc->DiagBuffer[0]; ++ if ((le32_to_cpu(request_data->DiagVersion) == 0x00000000 || ++ le32_to_cpu(request_data->DiagVersion) == 0x01000000) && ++ le32_to_cpu(request_data->Reserved3) == 0x4742444c) { ++ size = le32_to_cpu(request_data->Size); ++ ioc->ring_buffer_sz = size; ++ } ++ ++ return snprintf(buf, PAGE_SIZE, "%d\n", size); ++} ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_ring_buffer_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else ++static ssize_t ++mptscsih_ring_buffer_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(dev); ++#endif ++ ++ MPT_SCSI_HOST *hd = shost_private(host); ++ MPT_ADAPTER *ioc = hd->ioc; ++ void *request_data; ++ u32 size; ++ ++ if (!ioc->DiagBuffer[0]) ++ return 0; ++ ++ if (ioc->ring_buffer_offset > ioc->ring_buffer_sz) ++ return 0; ++ ++ size = ioc->ring_buffer_sz - ioc->ring_buffer_offset; ++ size = (size > PAGE_SIZE) ? PAGE_SIZE : size; ++ request_data = ioc->DiagBuffer[0] + ioc->ring_buffer_offset; ++ memcpy(buf, request_data, size); ++ return size; ++} ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_ring_buffer_store(struct class_device *cdev, const char *buf, ++ size_t count) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else ++static ssize_t ++mptscsih_ring_buffer_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct Scsi_Host *host = class_to_shost(dev); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); ++ MPT_ADAPTER *ioc = hd->ioc; ++ int val = 0; ++ ++ if (sscanf(buf, "%d", &val) != 1) ++ return -EINVAL; ++ ++ ioc->ring_buffer_offset = val; ++ return strlen(buf); ++} ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_version_fw_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_version_fw_show(struct device *dev, struct device_attribute *attr, + char *buf) + { + struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + + return snprintf(buf, PAGE_SIZE, "%02d.%02d.%02d.%02d\n", +@@ -3273,158 +3886,229 @@ + (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, + ioc->facts.FWVersion.Word & 0x000000FF); + } +-static DEVICE_ATTR(version_fw, S_IRUGO, mptscsih_version_fw_show, NULL); +- ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_version_bios_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_version_bios_show(struct device *dev, struct device_attribute *attr, + char *buf) + { + struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); +- MPT_ADAPTER *ioc = hd->ioc; +- +- return snprintf(buf, PAGE_SIZE, "%02x.%02x.%02x.%02x\n", ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); ++ MPT_ADAPTER *ioc = hd->ioc; ++ ++ return snprintf(buf, PAGE_SIZE, "%02d.%02d.%02d.%02d\n", + (ioc->biosVersion & 0xFF000000) >> 24, + (ioc->biosVersion & 0x00FF0000) >> 16, + (ioc->biosVersion & 0x0000FF00) >> 8, + ioc->biosVersion & 0x000000FF); + } +-static DEVICE_ATTR(version_bios, S_IRUGO, mptscsih_version_bios_show, NULL); +- ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_version_mpi_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_version_mpi_show(struct device *dev, struct device_attribute *attr, + char *buf) + { + struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); +- MPT_ADAPTER *ioc = hd->ioc; +- +- return snprintf(buf, PAGE_SIZE, "%03x\n", ioc->facts.MsgVersion); +-} +-static DEVICE_ATTR(version_mpi, S_IRUGO, mptscsih_version_mpi_show, NULL); +- ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); ++ MPT_ADAPTER *ioc = hd->ioc; ++ ++ if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) ++ return snprintf(buf, PAGE_SIZE, "%03x.%02x\n", ++ ioc->facts.MsgVersion, ioc->facts.HeaderVersion >> 8); ++ else ++ return snprintf(buf, PAGE_SIZE, "%03x\n", ++ ioc->facts.MsgVersion); ++} ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_version_product_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_version_product_show(struct device *dev, +- struct device_attribute *attr, +-char *buf) +-{ +- struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++ struct device_attribute *attr, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(dev); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + + return snprintf(buf, PAGE_SIZE, "%s\n", ioc->prod_name); + } +-static DEVICE_ATTR(version_product, S_IRUGO, +- mptscsih_version_product_show, NULL); +- ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_version_nvdata_persistent_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_version_nvdata_persistent_show(struct device *dev, + struct device_attribute *attr, + char *buf) + { + struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + + return snprintf(buf, PAGE_SIZE, "%02xh\n", + ioc->nvdata_version_persistent); + } +-static DEVICE_ATTR(version_nvdata_persistent, S_IRUGO, +- mptscsih_version_nvdata_persistent_show, NULL); +- ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_version_nvdata_default_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_version_nvdata_default_show(struct device *dev, + struct device_attribute *attr, char *buf) + { + struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + + return snprintf(buf, PAGE_SIZE, "%02xh\n",ioc->nvdata_version_default); + } +-static DEVICE_ATTR(version_nvdata_default, S_IRUGO, +- mptscsih_version_nvdata_default_show, NULL); +- ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_board_name_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_board_name_show(struct device *dev, struct device_attribute *attr, + char *buf) + { + struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + + return snprintf(buf, PAGE_SIZE, "%s\n", ioc->board_name); + } +-static DEVICE_ATTR(board_name, S_IRUGO, mptscsih_board_name_show, NULL); +- +-static ssize_t +-mptscsih_board_assembly_show(struct device *dev, +- struct device_attribute *attr, char *buf) +-{ +- struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_board_assembly_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else ++static ssize_t ++mptscsih_board_assembly_show(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(dev); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + + return snprintf(buf, PAGE_SIZE, "%s\n", ioc->board_assembly); + } +-static DEVICE_ATTR(board_assembly, S_IRUGO, +- mptscsih_board_assembly_show, NULL); +- ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_board_tracer_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_board_tracer_show(struct device *dev, struct device_attribute *attr, + char *buf) + { + struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + + return snprintf(buf, PAGE_SIZE, "%s\n", ioc->board_tracer); + } +-static DEVICE_ATTR(board_tracer, S_IRUGO, +- mptscsih_board_tracer_show, NULL); +- ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_io_delay_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_io_delay_show(struct device *dev, struct device_attribute *attr, + char *buf) + { + struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + + return snprintf(buf, PAGE_SIZE, "%02d\n", ioc->io_missing_delay); + } +-static DEVICE_ATTR(io_delay, S_IRUGO, +- mptscsih_io_delay_show, NULL); +- ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_device_delay_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_device_delay_show(struct device *dev, struct device_attribute *attr, + char *buf) + { + struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + + return snprintf(buf, PAGE_SIZE, "%02d\n", ioc->device_missing_delay); + } +-static DEVICE_ATTR(device_delay, S_IRUGO, +- mptscsih_device_delay_show, NULL); +- ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_debug_level_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_debug_level_show(struct device *dev, struct device_attribute *attr, + char *buf) + { + struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + + return snprintf(buf, PAGE_SIZE, "%08xh\n", ioc->debug_level); + } ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_debug_level_store(struct class_device *cdev, const char *buf, size_t count) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_debug_level_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) + { + struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + int val = 0; + +@@ -3436,25 +4120,39 @@ + ioc->debug_level); + return strlen(buf); + } +-static DEVICE_ATTR(debug_level, S_IRUGO | S_IWUSR, +- mptscsih_debug_level_show, mptscsih_debug_level_store); +- ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_disable_hotplug_remove_show(struct class_device *cdev, char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_disable_hotplug_remove_show(struct device *dev, +- struct device_attribute *attr, char *buf) +-{ +- struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct Scsi_Host *host = class_to_shost(dev); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + + return snprintf(buf, PAGE_SIZE, "%02xh\n", ioc->disable_hotplug_remove); + } ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static ssize_t ++mptscsih_disable_hotplug_remove_store(struct class_device *cdev, const char *buf, size_t count) ++{ ++ struct Scsi_Host *host = class_to_shost(cdev); ++#else + static ssize_t + mptscsih_disable_hotplug_remove_store(struct device *dev, +- struct device_attribute *attr, const char *buf, size_t count) +-{ +- struct Scsi_Host *host = class_to_shost(dev); +- MPT_SCSI_HOST *hd = shost_priv(host); ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct Scsi_Host *host = class_to_shost(dev); ++#endif ++ MPT_SCSI_HOST *hd = shost_private(host); + MPT_ADAPTER *ioc = hd->ioc; + int val = 0; + +@@ -3469,11 +4167,94 @@ + printk(MYIOC_s_INFO_FMT "eanbling hotplug remove\n", ioc->name); + return strlen(buf); + } ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++static CLASS_DEVICE_ATTR(fault, S_IRUGO | S_IWUSR, ++ mptscsih_fault_show, mptscsih_fault_store); ++static CLASS_DEVICE_ATTR(ring_buffer_size, S_IRUGO, ++ mptscsih_ring_buffer_size_show, NULL); ++static CLASS_DEVICE_ATTR(ring_buffer, S_IRUGO | S_IWUSR, ++ mptscsih_ring_buffer_show, mptscsih_ring_buffer_store); ++static CLASS_DEVICE_ATTR(version_fw, S_IRUGO, mptscsih_version_fw_show, NULL); ++static CLASS_DEVICE_ATTR(version_bios, S_IRUGO, ++ mptscsih_version_bios_show, NULL); ++static CLASS_DEVICE_ATTR(version_mpi, S_IRUGO, mptscsih_version_mpi_show, NULL); ++static CLASS_DEVICE_ATTR(version_product, S_IRUGO, ++ mptscsih_version_product_show, NULL); ++static CLASS_DEVICE_ATTR(version_nvdata_persistent, S_IRUGO, ++ mptscsih_version_nvdata_persistent_show, NULL); ++static CLASS_DEVICE_ATTR(version_nvdata_default, S_IRUGO, ++ mptscsih_version_nvdata_default_show, NULL); ++static CLASS_DEVICE_ATTR(board_name, S_IRUGO, mptscsih_board_name_show, NULL); ++static CLASS_DEVICE_ATTR(board_assembly, S_IRUGO, ++ mptscsih_board_assembly_show, NULL); ++static CLASS_DEVICE_ATTR(board_tracer, S_IRUGO, ++ mptscsih_board_tracer_show, NULL); ++static CLASS_DEVICE_ATTR(io_delay, S_IRUGO, ++ mptscsih_io_delay_show, NULL); ++static CLASS_DEVICE_ATTR(device_delay, S_IRUGO, ++ mptscsih_device_delay_show, NULL); ++static CLASS_DEVICE_ATTR(debug_level, S_IRUGO | S_IWUSR, ++ mptscsih_debug_level_show, mptscsih_debug_level_store); ++static CLASS_DEVICE_ATTR(disable_hotplug_remove, S_IRUGO | S_IWUSR, ++ mptscsih_disable_hotplug_remove_show, mptscsih_disable_hotplug_remove_store); ++ ++struct class_device_attribute *mptscsih_host_attrs[] = { ++ &class_device_attr_fault, ++ &class_device_attr_ring_buffer_size, ++ &class_device_attr_ring_buffer, ++ &class_device_attr_version_fw, ++ &class_device_attr_version_bios, ++ &class_device_attr_version_mpi, ++ &class_device_attr_version_product, ++ &class_device_attr_version_nvdata_persistent, ++ &class_device_attr_version_nvdata_default, ++ &class_device_attr_board_name, ++ &class_device_attr_board_assembly, ++ &class_device_attr_board_tracer, ++ &class_device_attr_io_delay, ++ &class_device_attr_device_delay, ++ &class_device_attr_debug_level, ++ &class_device_attr_disable_hotplug_remove, ++ NULL, ++}; ++#else ++ ++static DEVICE_ATTR(fault, S_IRUGO | S_IWUSR, ++ mptscsih_fault_show, mptscsih_fault_store); ++static DEVICE_ATTR(ring_buffer_size, S_IRUGO, ++ mptscsih_ring_buffer_size_show, NULL); ++static DEVICE_ATTR(ring_buffer, S_IRUGO | S_IWUSR, ++ mptscsih_ring_buffer_show, mptscsih_ring_buffer_store); ++static DEVICE_ATTR(version_fw, S_IRUGO, mptscsih_version_fw_show, NULL); ++static DEVICE_ATTR(version_bios, S_IRUGO, ++ mptscsih_version_bios_show, NULL); ++static DEVICE_ATTR(version_mpi, S_IRUGO, mptscsih_version_mpi_show, NULL); ++static DEVICE_ATTR(version_product, S_IRUGO, ++ mptscsih_version_product_show, NULL); ++static DEVICE_ATTR(version_nvdata_persistent, S_IRUGO, ++ mptscsih_version_nvdata_persistent_show, NULL); ++static DEVICE_ATTR(version_nvdata_default, S_IRUGO, ++ mptscsih_version_nvdata_default_show, NULL); ++static DEVICE_ATTR(board_name, S_IRUGO, mptscsih_board_name_show, NULL); ++static DEVICE_ATTR(board_assembly, S_IRUGO, ++ mptscsih_board_assembly_show, NULL); ++static DEVICE_ATTR(board_tracer, S_IRUGO, ++ mptscsih_board_tracer_show, NULL); ++static DEVICE_ATTR(io_delay, S_IRUGO, ++ mptscsih_io_delay_show, NULL); ++static DEVICE_ATTR(device_delay, S_IRUGO, ++ mptscsih_device_delay_show, NULL); ++static DEVICE_ATTR(debug_level, S_IRUGO | S_IWUSR, ++ mptscsih_debug_level_show, mptscsih_debug_level_store); + static DEVICE_ATTR(disable_hotplug_remove, S_IRUGO | S_IWUSR, +- mptscsih_disable_hotplug_remove_show, +- mptscsih_disable_hotplug_remove_store); ++ mptscsih_disable_hotplug_remove_show, mptscsih_disable_hotplug_remove_store); + + struct device_attribute *mptscsih_host_attrs[] = { ++ &dev_attr_fault, ++ &dev_attr_ring_buffer_size, ++ &dev_attr_ring_buffer, + &dev_attr_version_fw, + &dev_attr_version_bios, + &dev_attr_version_mpi, +@@ -3489,6 +4270,9 @@ + &dev_attr_disable_hotplug_remove, + NULL, + }; ++ ++#endif ++ + EXPORT_SYMBOL(mptscsih_host_attrs); + + EXPORT_SYMBOL(mptscsih_remove); +diff -r 8807687e8e9c drivers/message/fusion/mptscsih.h +--- a/drivers/message/fusion/mptscsih.h Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/mptscsih.h Tue Sep 01 16:11:23 2009 +0100 +@@ -93,6 +93,11 @@ + #define TRANSPORT_LAYER_RETRIES 0xC2 + #endif + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++#define mpt_sg_next(sg) sg + 1 ++#else ++#define mpt_sg_next(sg) sg_next(sg) ++#endif + typedef struct _internal_cmd { + char *data; /* data pointer */ + dma_addr_t data_dma; /* data dma address */ +@@ -129,13 +134,15 @@ + extern int mptscsih_event_process(MPT_ADAPTER *ioc, EventNotificationReply_t *pEvReply); + extern int mptscsih_ioc_reset(MPT_ADAPTER *ioc, int post_reset); + extern int mptscsih_change_queue_depth(struct scsi_device *sdev, int qdepth); +-extern int mptscsih_IssueTaskMgmt(MPT_SCSI_HOST *hd, u8 type, u8 channel, +- u8 id, int lun, int ctx2abort, ulong timeout); ++extern int mptscsih_IssueTaskMgmt(MPT_SCSI_HOST *hd, u8 type, u8 channel, u8 id, int lun, int ctx2abort, ulong timeout); + extern u8 mptscsih_raid_id_to_num(MPT_ADAPTER *ioc, u8 channel, u8 id); + extern int mptscsih_is_phys_disk(MPT_ADAPTER *ioc, u8 channel, u8 id); + extern int mptscsih_do_cmd(MPT_SCSI_HOST *hd, INTERNAL_CMD *iocmd); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++extern struct class_device_attribute *mptscsih_host_attrs[]; ++#else + extern struct device_attribute *mptscsih_host_attrs[]; +-extern int mptscsih_quiesce_raid(MPT_SCSI_HOST *hd, int quiesce, u8 channel, +- u8 id); ++#endif ++extern int mptscsih_quiesce_raid(MPT_SCSI_HOST *hd, int quiesce, u8 channel, u8 id); + extern struct scsi_cmnd * mptscsih_get_scsi_lookup(MPT_ADAPTER *ioc, int i); + extern void mptscsih_taskmgmt_response_code(MPT_ADAPTER *ioc, u8 response_code); +diff -r 8807687e8e9c drivers/message/fusion/mptspi.c +--- a/drivers/message/fusion/mptspi.c Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/mptspi.c Tue Sep 01 16:11:23 2009 +0100 +@@ -43,7 +43,7 @@ + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +- ++#include + #include + #include + #include +@@ -67,6 +67,7 @@ + #include + #include + ++#include "linux_compat.h" /* linux-2.6 tweaks */ + #include "mptbase.h" + #include "mptscsih.h" + +@@ -87,8 +88,7 @@ + + static int mpt_qas = MPTSCSIH_QAS; + module_param(mpt_qas, int, 1); +-MODULE_PARM_DESC(mpt_qas, " Quick Arbitration and Selection (QAS) enabled=1," +- " disabled= (default=MPTSCSIH_QAS=1)"); ++MODULE_PARM_DESC(mpt_qas, " Quick Arbitration and Selection (QAS) enabled=1, disabled=0 (default=MPTSCSIH_QAS=1)"); + + static void mptspi_write_offset(struct scsi_target *, int); + static void mptspi_write_width(struct scsi_target *, int); +@@ -241,7 +241,7 @@ + */ + + ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT +- "Disabling QAS due to noQas=%02x on id=%d!\n", ioc->name, noQas, id)); ++ "Disabling QAS due to noQas=%02x on id=%d!\n", ioc->name, noQas, id)); + } + } + +@@ -315,7 +315,7 @@ + + ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT + "writeIOCPage4: MaxSEP=%d ActiveSEP=%d id=%d bus=%d\n", +- ioc->name, IOCPage4Ptr->MaxSEP, IOCPage4Ptr->ActiveSEP, id, channel)); ++ ioc->name, IOCPage4Ptr->MaxSEP, IOCPage4Ptr->ActiveSEP, id, channel)); + + mpt_put_msg_frame(ioc->DoneCtx, ioc, mf); + +@@ -408,7 +408,7 @@ + static int mptspi_target_alloc(struct scsi_target *starget) + { + struct Scsi_Host *shost = dev_to_shost(&starget->dev); +- struct _MPT_SCSI_HOST *hd = shost_priv(shost); ++ struct _MPT_SCSI_HOST *hd = shost_private(shost); + VirtTarget *vtarget; + MPT_ADAPTER *ioc = hd->ioc; + +@@ -496,7 +496,7 @@ + ii & MPI_SCSIDEVPAGE0_NP_WR_FLOW ? "WRFLOW ": "", + ii & MPI_SCSIDEVPAGE0_NP_RD_STRM ? "RDSTRM ": "", + ii & MPI_SCSIDEVPAGE0_NP_RTI ? "RTI ": "", +- ii & MPI_SCSIDEVPAGE0_NP_PCOMP_EN ? "PCOMP " : ""); ++ ii & MPI_SCSIDEVPAGE0_NP_PCOMP_EN ? "PCOMP ": ""); + } + + /** +@@ -524,14 +524,14 @@ + ii & MPI_SCSIDEVPAGE0_NP_WR_FLOW ? "WRFLOW ": "", + ii & MPI_SCSIDEVPAGE0_NP_RD_STRM ? "RDSTRM ": "", + ii & MPI_SCSIDEVPAGE0_NP_RTI ? "RTI ": "", +- ii & MPI_SCSIDEVPAGE0_NP_PCOMP_EN ? "PCOMP " : ""); ++ ii & MPI_SCSIDEVPAGE0_NP_PCOMP_EN ? "PCOMP ": ""); + } + + static int mptspi_read_spi_device_pg0(struct scsi_target *starget, + struct _CONFIG_PAGE_SCSI_DEVICE_0 *pass_pg0) + { + struct Scsi_Host *shost = dev_to_shost(&starget->dev); +- struct _MPT_SCSI_HOST *hd = shost_priv(shost); ++ struct _MPT_SCSI_HOST *hd = shost_private(shost); + struct _MPT_ADAPTER *ioc = hd->ioc; + struct _CONFIG_PAGE_SCSI_DEVICE_0 *spi_dev_pg0; + dma_addr_t spi_dev_pg0_dma; +@@ -677,7 +677,7 @@ + + static int mptspi_slave_alloc(struct scsi_device *sdev) + { +- MPT_SCSI_HOST *hd = shost_priv(sdev->host); ++ MPT_SCSI_HOST *hd = shost_private(sdev->host); + VirtTarget *vtarget; + VirtDevice *vdevice; + struct scsi_target *starget; +@@ -710,7 +710,7 @@ + + static int mptspi_slave_configure(struct scsi_device *sdev) + { +- struct _MPT_SCSI_HOST *hd = shost_priv(sdev->host); ++ struct _MPT_SCSI_HOST *hd = shost_private(sdev->host); + VirtTarget *vtarget = scsi_target(sdev)->hostdata; + int ret; + +@@ -730,7 +730,7 @@ + static int + mptspi_qcmd(struct scsi_cmnd *SCpnt, void (*done)(struct scsi_cmnd *)) + { +- struct _MPT_SCSI_HOST *hd = shost_priv(SCpnt->device->host); ++ struct _MPT_SCSI_HOST *hd = shost_private(SCpnt->device->host); + VirtDevice *vdevice = SCpnt->device->hostdata; + MPT_ADAPTER *ioc = hd->ioc; + +@@ -805,7 +805,7 @@ + struct _CONFIG_PAGE_SCSI_DEVICE_1 *pass_pg1) + { + struct Scsi_Host *shost = dev_to_shost(&starget->dev); +- struct _MPT_SCSI_HOST *hd = shost_priv(shost); ++ struct _MPT_SCSI_HOST *hd = shost_private(shost); + struct _MPT_ADAPTER *ioc = hd->ioc; + struct _CONFIG_PAGE_SCSI_DEVICE_1 *pg1; + dma_addr_t pg1_dma; +@@ -823,8 +823,8 @@ + + pg1 = dma_alloc_coherent(&ioc->pcidev->dev, size, &pg1_dma, GFP_KERNEL); + if (pg1 == NULL) { +- starget_printk(KERN_ERR, starget, MYIOC_s_FMT +- "dma_alloc_coherent for parameters failed\n", ioc->name); ++ starget_printk(KERN_ERR, starget, ++ MYIOC_s_FMT "dma_alloc_coherent for parameters failed\n", ioc->name); + return -EINVAL; + } + +@@ -991,7 +991,7 @@ + { + struct _CONFIG_PAGE_SCSI_DEVICE_1 pg1; + struct Scsi_Host *shost = dev_to_shost(&starget->dev); +- struct _MPT_SCSI_HOST *hd = shost_priv(shost); ++ struct _MPT_SCSI_HOST *hd = shost_private(shost); + VirtTarget *vtarget = starget->hostdata; + u32 nego; + MPT_ADAPTER *ioc = hd->ioc; +@@ -1041,10 +1041,16 @@ + }; + + static void ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + mpt_work_wrapper(struct work_struct *work) + { + struct work_queue_wrapper *wqw = + container_of(work, struct work_queue_wrapper, work); ++#else ++mpt_work_wrapper(void *data) ++{ ++ struct work_queue_wrapper *wqw = (struct work_queue_wrapper *)data; ++#endif + struct _MPT_SCSI_HOST *hd = wqw->hd; + MPT_ADAPTER *ioc = hd->ioc; + struct Scsi_Host *shost = ioc->sh; +@@ -1072,12 +1078,12 @@ + if(vtarget->id != disk) + continue; + +- starget_printk(KERN_INFO, vtarget->starget, MYIOC_s_FMT +- "Integrated RAID requests DV of new device\n", ioc->name); ++ starget_printk(KERN_INFO, vtarget->starget, ++ MYIOC_s_FMT "Integrated RAID requests DV of new device\n", ioc->name); + mptspi_dv_device(hd, sdev); + } +- shost_printk(KERN_INFO, shost, MYIOC_s_FMT +- "Integrated RAID detects new device %d\n", ioc->name, disk); ++ shost_printk(KERN_INFO, shost, ++ MYIOC_s_FMT "Integrated RAID detects new device %d\n", ioc->name, disk); + scsi_scan_target(&ioc->sh->shost_gendev, 1, disk, 0, 1); + } + +@@ -1088,12 +1094,16 @@ + MPT_ADAPTER *ioc = hd->ioc; + + if (!wqw) { +- shost_printk(KERN_ERR, ioc->sh, MYIOC_s_FMT +- "Failed to act on RAID event for physical disk %d\n", ++ shost_printk(KERN_ERR, ioc->sh, ++ MYIOC_s_FMT "Failed to act on RAID event for physical disk %d\n", + ioc->name, disk); + return; + } ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + INIT_WORK(&wqw->work, mpt_work_wrapper); ++#else ++ INIT_WORK(&wqw->work, mpt_work_wrapper, wqw); ++#endif + wqw->hd = hd; + wqw->disk = disk; + +@@ -1104,7 +1114,7 @@ + mptspi_event_process(MPT_ADAPTER *ioc, EventNotificationReply_t *pEvReply) + { + u8 event = le32_to_cpu(pEvReply->Event) & 0xFF; +- struct _MPT_SCSI_HOST *hd = shost_priv(ioc->sh); ++ struct _MPT_SCSI_HOST *hd = shost_private(ioc->sh); + + if (hd && event == MPI_EVENT_INTEGRATED_RAID) { + int reason +@@ -1184,10 +1194,16 @@ + * renegotiate for a given target + **/ + static void ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + mptspi_dv_renegotiate_work(struct work_struct *work) + { + struct work_queue_wrapper *wqw = + container_of(work, struct work_queue_wrapper, work); ++#else ++mptspi_dv_renegotiate_work(void *data) ++{ ++ struct work_queue_wrapper *wqw = (struct work_queue_wrapper *)data; ++#endif + struct _MPT_SCSI_HOST *hd = wqw->hd; + struct scsi_device *sdev; + struct scsi_target *starget; +@@ -1222,7 +1238,11 @@ + if (!wqw) + return; + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)) + INIT_WORK(&wqw->work, mptspi_dv_renegotiate_work); ++#else ++ INIT_WORK(&wqw->work, mptspi_dv_renegotiate_work, wqw); ++#endif + wqw->hd = hd; + + schedule_work(&wqw->work); +@@ -1241,7 +1261,7 @@ + if ((ioc->bus_type != SPI) || (!rc)) + goto out; + +- hd = shost_priv(ioc->sh); ++ hd = shost_private(ioc->sh); + if (!hd->ioc) + goto out; + +@@ -1259,7 +1279,7 @@ + mptspi_resume(struct pci_dev *pdev) + { + MPT_ADAPTER *ioc = pci_get_drvdata(pdev); +- struct _MPT_SCSI_HOST *hd = shost_priv(ioc->sh); ++ struct _MPT_SCSI_HOST *hd = shost_private(ioc->sh); + int rc; + + rc = mptscsih_resume(pdev); +@@ -1411,7 +1431,7 @@ + sh->sg_tablesize = numSGE; + } + +- hd = shost_priv(sh); ++ hd = shost_private(sh); + hd->ioc = ioc; + + spin_unlock_irqrestore(&ioc->FreeQlock, flags); +diff -r 8807687e8e9c drivers/message/fusion/rejected_ioctls/diag_buffer.c +--- a/drivers/message/fusion/rejected_ioctls/diag_buffer.c Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/rejected_ioctls/diag_buffer.c Tue Sep 01 16:11:23 2009 +0100 +@@ -4,20 +4,19 @@ + * Outputs: None. + * Return: 0 if successful + * -EFAULT if data unavailable +- * -EBUSY if previous command timout and IOC reset is not +- * complete. ++ * -EBUSY if previous command timout and IOC reset is not complete. + * -ENODEV if no such device/adapter + * -ETIME if timer expires + * -ENOMEM if memory allocation error + */ + static int +-mptctl_register_diag_buffer(unsigned long arg) ++mptctl_register_diag_buffer (unsigned long arg) + { + mpt_diag_register_t __user *uarg = (void __user *) arg; + mpt_diag_register_t karg; + MPT_ADAPTER *ioc; + int iocnum, rc, ii; +- void *request_data; ++ void * request_data; + dma_addr_t request_data_dma; + u32 request_data_sz; + MPT_FRAME_HDR *mf; +@@ -31,39 +30,37 @@ + if (copy_from_user(&karg, uarg, sizeof(mpt_diag_register_t))) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to read in mpt_diag_register_t struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + return -EFAULT; + } + +- iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc); +- +- if ((iocnum < 0) || (ioc == NULL)) { ++ if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || ++ (ioc == NULL)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); + return -ENODEV; + } + + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s enter.\n", ioc->name, +- __func__)); ++ __FUNCTION__)); + buffer_type = karg.data.BufferType; + if (!(ioc->facts.IOCCapabilities & MPT_DIAG_CAPABILITY(buffer_type))) { + printk(MYIOC_s_DEBUG_FMT "%s: doesn't have Capability for " +- "buffer_type=%x\n", ioc->name, __func__, buffer_type); ++ "buffer_type=%x\n", ioc->name, __FUNCTION__, buffer_type); + return -ENODEV; + } + + if (ioc->DiagBuffer_Status[buffer_type] & + MPT_DIAG_BUFFER_IS_REGISTERED) { + printk(MYIOC_s_DEBUG_FMT "%s: already has a Registered " +- "buffer for buffer_type=%x\n", ioc->name, __func__, ++ "buffer for buffer_type=%x\n", ioc->name, __FUNCTION__, + buffer_type); + return -EFAULT; + } + + /* Get a free request frame and save the message context. + */ +- mf = mpt_get_msg_frame(mptctl_id, ioc); +- if (mf == NULL) ++ if ((mf = mpt_get_msg_frame(mptctl_id, ioc)) == NULL) + return -EAGAIN; + + request_data = ioc->DiagBuffer[buffer_type]; +@@ -88,9 +85,9 @@ + if (request_data == NULL) { + printk(MYIOC_s_DEBUG_FMT "%s: pci_alloc_consistent" + " FAILED, (request_sz=%d)\n", ioc->name, +- __func__, request_data_sz); ++ __FUNCTION__, request_data_sz); + mpt_free_msg_frame(ioc, mf); +- return -EAGAIN; ++ return -EAGAIN; + } + ioc->DiagBuffer[buffer_type] = request_data; + ioc->DiagBuffer_sz[buffer_type] = request_data_sz; +@@ -98,7 +95,7 @@ + } + + ioc->DiagBuffer_Status[buffer_type] = 0; +- diag_buffer_post_request = (DiagBufferPostRequest_t *)mf; ++ diag_buffer_post_request = (DiagBufferPostRequest_t *)mf; + diag_buffer_post_request->Function = MPI_FUNCTION_DIAG_BUFFER_POST; + diag_buffer_post_request->ChainOffset = 0; + diag_buffer_post_request->BufferType = karg.data.BufferType; +@@ -140,7 +137,7 @@ + if (!(ioc->ioctl_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { + rc = -ETIME; + printk(MYIOC_s_WARN_FMT "%s: failed\n", ioc->name, +- __func__); ++ __FUNCTION__); + if (ioc->ioctl_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) { + mpt_free_msg_frame(ioc, mf); + goto out; +@@ -153,7 +150,7 @@ + /* process the completed Reply Message Frame */ + if ((ioc->ioctl_cmds.status & MPT_MGMT_STATUS_RF_VALID) == 0) { + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: status=%x\n", +- ioc->name, __func__, ioc->ioctl_cmds.status)); ++ ioc->name, __FUNCTION__, ioc->ioctl_cmds.status)); + rc = -EFAULT; + goto out; + } +@@ -163,13 +160,12 @@ + MPI_IOCSTATUS_SUCCESS) { + if (diag_buffer_post_reply->MsgLength > 5) + ioc->DataSize[buffer_type] = +- le32_to_cpu +- (diag_buffer_post_reply->TransferLength); ++ le32_to_cpu(diag_buffer_post_reply->TransferLength); + ioc->DiagBuffer_Status[buffer_type] |= + MPT_DIAG_BUFFER_IS_REGISTERED; + } else { + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: IOCStatus=%x " +- "IOCLogInfo=%x\n", ioc->name, __func__, ++ "IOCLogInfo=%x\n", ioc->name, __FUNCTION__, + diag_buffer_post_reply->IOCStatus, + diag_buffer_post_reply->IOCLogInfo)); + rc = -EFAULT; +@@ -191,19 +187,18 @@ + * Outputs: None. + * Return: 0 if successful + * -EFAULT if data unavailable +- * -EBUSY if previous command timout and IOC reset is +- * not complete. ++ * -EBUSY if previous command timout and IOC reset is not complete. + * -ENODEV if no such device/adapter + * -ETIME if timer expires + * -ENOMEM if memory allocation error + */ + static int +-mptctl_release_diag_buffer(unsigned long arg) ++mptctl_release_diag_buffer (unsigned long arg) + { + mpt_diag_release_t __user *uarg = (void __user *) arg; + mpt_diag_release_t karg; + MPT_ADAPTER *ioc; +- void *request_data; ++ void * request_data; + int iocnum, rc; + MPT_FRAME_HDR *mf; + DiagReleaseRequest_t *diag_release; +@@ -215,42 +210,42 @@ + if (copy_from_user(&karg, uarg, sizeof(mpt_diag_release_t))) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to read in mpt_diag_release_t struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + return -EFAULT; + } + +- iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc); +- if ((iocnum < 0) || (ioc == NULL)) { ++ if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || ++ (ioc == NULL)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); + return -ENODEV; + } + + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s enter.\n", ioc->name, +- __func__)); ++ __FUNCTION__)); + buffer_type = karg.data.UniqueId & 0x000000ff; + if (!(ioc->facts.IOCCapabilities & MPT_DIAG_CAPABILITY(buffer_type))) { + printk(MYIOC_s_DEBUG_FMT "%s: doesn't have Capability for " +- "buffer_type=%x\n", ioc->name, __func__, buffer_type); ++ "buffer_type=%x\n", ioc->name, __FUNCTION__, buffer_type); + return -ENODEV; + } + + if ((ioc->DiagBuffer_Status[buffer_type] & +- MPT_DIAG_BUFFER_IS_REGISTERED) == 0) { ++ MPT_DIAG_BUFFER_IS_REGISTERED) == 0 ) { + printk(MYIOC_s_DEBUG_FMT "%s: buffer_type=%x is not " +- "registered\n", ioc->name, __func__, buffer_type); ++ "registered\n", ioc->name, __FUNCTION__, buffer_type); + return -EFAULT; + } + + if (karg.data.UniqueId != ioc->UniqueId[buffer_type]) { + printk(MYIOC_s_DEBUG_FMT "%s: unique_id=%x is not registered\n", +- ioc->name, __func__, karg.data.UniqueId); ++ ioc->name, __FUNCTION__, karg.data.UniqueId); + return -EFAULT; + } + + if (ioc->DiagBuffer_Status[buffer_type] & MPT_DIAG_BUFFER_IS_RELEASED) { + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: buffer_type=%x " +- "is already released\n", ioc->name, __func__, ++ "is already released\n", ioc->name, __FUNCTION__, + buffer_type)); + return rc; + } +@@ -259,14 +254,13 @@ + + if (request_data == NULL) { + printk(MYIOC_s_DEBUG_FMT "%s: doesn't have buffer for " +- "buffer_type=%x\n", ioc->name, __func__, buffer_type); ++ "buffer_type=%x\n", ioc->name, __FUNCTION__, buffer_type); + return -ENODEV; + } + + /* Get a free request frame and save the message context. + */ +- mf = mpt_get_msg_frame(mptctl_id, ioc); +- if (mf == NULL) ++ if ((mf = mpt_get_msg_frame(mptctl_id, ioc)) == NULL) + return -EAGAIN; + + diag_release = (DiagReleaseRequest_t *)mf; +@@ -287,7 +281,7 @@ + if (!(ioc->ioctl_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { + rc = -ETIME; + printk(MYIOC_s_WARN_FMT "%s: failed\n", ioc->name, +- __func__); ++ __FUNCTION__); + if (ioc->ioctl_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) { + mpt_free_msg_frame(ioc, mf); + goto out; +@@ -300,7 +294,7 @@ + /* process the completed Reply Message Frame */ + if ((ioc->ioctl_cmds.status & MPT_MGMT_STATUS_RF_VALID) == 0) { + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: status=%x\n", +- ioc->name, __func__, ioc->ioctl_cmds.status)); ++ ioc->name, __FUNCTION__, ioc->ioctl_cmds.status)); + rc = -EFAULT; + goto out; + } +@@ -310,7 +304,7 @@ + MPI_IOCSTATUS_SUCCESS) { + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: IOCStatus=%x " + "IOCLogInfo=%x\n", +- ioc->name, __func__, diag_release_reply->IOCStatus, ++ ioc->name, __FUNCTION__, diag_release_reply->IOCStatus, + diag_release_reply->IOCLogInfo)); + rc = -EFAULT; + } else +@@ -330,20 +324,19 @@ + * Outputs: None. + * Return: 0 if successful + * -EFAULT if data unavailable +- * -EBUSY if previous command timout and IOC reset is +- * not complete. ++ * -EBUSY if previous command timout and IOC reset is not complete. + * -ENODEV if no such device/adapter + * -ETIME if timer expires + * -ENOMEM if memory allocation error + */ + static int +-mptctl_unregister_diag_buffer(unsigned long arg) ++mptctl_unregister_diag_buffer (unsigned long arg) + { + mpt_diag_unregister_t __user *uarg = (void __user *) arg; + mpt_diag_unregister_t karg; + MPT_ADAPTER *ioc; + int iocnum; +- void *request_data; ++ void * request_data; + dma_addr_t request_data_dma; + u32 request_data_sz; + u8 buffer_type; +@@ -351,48 +344,49 @@ + if (copy_from_user(&karg, uarg, sizeof(mpt_diag_unregister_t))) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to read in mpt_diag_unregister_t struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + return -EFAULT; + } +- iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc); +- if ((iocnum < 0) || (ioc == NULL)) { ++ ++ if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || ++ (ioc == NULL)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); + return -ENODEV; + } + + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s enter.\n", ioc->name, +- __func__)); ++ __FUNCTION__)); + buffer_type = karg.data.UniqueId & 0x000000ff; + if (!(ioc->facts.IOCCapabilities & MPT_DIAG_CAPABILITY(buffer_type))) { + printk(MYIOC_s_DEBUG_FMT "%s: doesn't have Capability for " +- "buffer_type=%x\n", ioc->name, __func__, buffer_type); ++ "buffer_type=%x\n", ioc->name, __FUNCTION__, buffer_type); + return -ENODEV; + } + + if ((ioc->DiagBuffer_Status[buffer_type] & + MPT_DIAG_BUFFER_IS_REGISTERED) == 0) { + printk(MYIOC_s_DEBUG_FMT "%s: buffer_type=%x is not " +- "registered\n", ioc->name, __func__, buffer_type); ++ "registered\n", ioc->name, __FUNCTION__, buffer_type); + return -EFAULT; + } + if ((ioc->DiagBuffer_Status[buffer_type] & + MPT_DIAG_BUFFER_IS_RELEASED) == 0) { + printk(MYIOC_s_DEBUG_FMT "%s: buffer_type=%x has not been " +- "released\n", ioc->name, __func__, buffer_type); ++ "released\n", ioc->name, __FUNCTION__, buffer_type); + return -EFAULT; + } + + if (karg.data.UniqueId != ioc->UniqueId[buffer_type]) { + printk(MYIOC_s_DEBUG_FMT "%s: unique_id=%x is not registered\n", +- ioc->name, __func__, karg.data.UniqueId); ++ ioc->name, __FUNCTION__, karg.data.UniqueId); + return -EFAULT; + } + + request_data = ioc->DiagBuffer[buffer_type]; + if (!request_data) { + printk(MYIOC_s_DEBUG_FMT "%s: doesn't have buffer for " +- "buffer_type=%x\n", ioc->name, __func__, buffer_type); ++ "buffer_type=%x\n", ioc->name, __FUNCTION__, buffer_type); + return -ENODEV; + } + +@@ -411,19 +405,18 @@ + * Outputs: None. + * Return: 0 if successful + * -EFAULT if data unavailable +- * -EBUSY if previous command timout and IOC reset +- * is not complete. ++ * -EBUSY if previous command timout and IOC reset is not complete. + * -ENODEV if no such device/adapter + * -ETIME if timer expires + * -ENOMEM if memory allocation error + */ + static int +-mptctl_query_diag_buffer(unsigned long arg) ++mptctl_query_diag_buffer (unsigned long arg) + { + mpt_diag_query_t __user *uarg = (void __user *)arg; + mpt_diag_query_t karg; + MPT_ADAPTER *ioc; +- void *request_data; ++ void * request_data; + int iocnum, ii, rc; + u8 buffer_type; + +@@ -431,38 +424,38 @@ + if (copy_from_user(&karg, uarg, sizeof(mpt_diag_query_t))) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to read in mpt_diag_query_t struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + return -EFAULT; + } + + karg.data.Flags = 0; +- iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc); +- if ((iocnum < 0) || (ioc == NULL)) { ++ if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || ++ (ioc == NULL)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); + goto out; + } + + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s enter.\n", ioc->name, +- __func__)); ++ __FUNCTION__)); + buffer_type = karg.data.BufferType; + if (!(ioc->facts.IOCCapabilities & MPT_DIAG_CAPABILITY(buffer_type))) { + printk(MYIOC_s_DEBUG_FMT "%s: doesn't have Capability for " +- "buffer_type=%x\n", ioc->name, __func__, buffer_type); ++ "buffer_type=%x\n", ioc->name, __FUNCTION__, buffer_type); + goto out; + } + + if ((ioc->DiagBuffer_Status[buffer_type] & +- MPT_DIAG_BUFFER_IS_REGISTERED) == 0) { ++ MPT_DIAG_BUFFER_IS_REGISTERED) == 0) { + printk(MYIOC_s_DEBUG_FMT "%s: buffer_type=%x is not " +- "registered\n", ioc->name, __func__, buffer_type); ++ "registered\n", ioc->name, __FUNCTION__, buffer_type); + goto out; + } + + if (karg.data.UniqueId & 0xffffff00) { + if (karg.data.UniqueId != ioc->UniqueId[buffer_type]) { + printk(MYIOC_s_DEBUG_FMT "%s: unique_id=%x is not " +- "registered\n", ioc->name, __func__, ++ "registered\n", ioc->name, __FUNCTION__, + karg.data.UniqueId); + goto out; + } +@@ -471,10 +464,10 @@ + request_data = ioc->DiagBuffer[buffer_type]; + if (!request_data) { + printk(MYIOC_s_DEBUG_FMT "%s: doesn't have buffer for " +- "buffer_type=%x\n", ioc->name, __func__, buffer_type); ++ "buffer_type=%x\n", ioc->name, __FUNCTION__, buffer_type); + goto out; + } +- ++ + rc = 0; + if (buffer_type == MPI_DIAG_BUF_TYPE_EXTENDED) { + if (karg.data.ExtendedType != ioc->ExtendedType[buffer_type]) +@@ -497,7 +490,7 @@ + out: + if (copy_to_user(uarg, &karg, sizeof(mpt_diag_query_t))) { + printk(MYIOC_s_ERR_FMT "%s Unable to write mpt_diag_query_t " +- "data @ %p\n", ioc->name, __func__, uarg); ++ "data @ %p\n", ioc->name, __FUNCTION__, uarg); + return -EFAULT; + } + return rc; +@@ -509,14 +502,13 @@ + * Outputs: None. + * Return: 0 if successful + * -EFAULT if data unavailable +- * -EBUSY if previous command timout and IOC reset +- * is not complete. ++ * -EBUSY if previous command timout and IOC reset is not complete. + * -ENODEV if no such device/adapter + * -ETIME if timer expires + * -ENOMEM if memory allocation error + */ + static int +-mptctl_read_diag_buffer(unsigned long arg) ++mptctl_read_diag_buffer (unsigned long arg) + { + mpt_diag_read_buffer_t __user *uarg = (void __user *) arg; + mpt_diag_read_buffer_t karg; +@@ -535,49 +527,50 @@ + if (copy_from_user(&karg, uarg, sizeof(mpt_diag_read_buffer_t))) { + printk(KERN_ERR "%s@%d::%s - " + "Unable to read in mpt_diag_read_buffer_t struct @ %p\n", +- __FILE__, __LINE__, __func__, uarg); ++ __FILE__, __LINE__, __FUNCTION__, uarg); + return -EFAULT; + } +- iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc); +- if ((iocnum < 0) || (ioc == NULL)) { ++ ++ if (((iocnum = mpt_verify_adapter(karg.hdr.iocnum, &ioc)) < 0) || ++ (ioc == NULL)) { + printk(KERN_ERR "%s::%s() @%d - ioc%d not found!\n", +- __FILE__, __func__, __LINE__, iocnum); ++ __FILE__, __FUNCTION__, __LINE__, iocnum); + return -ENODEV; + } + + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s enter.\n", ioc->name, +- __func__)); ++ __FUNCTION__)); + buffer_type = karg.data.UniqueId & 0x000000ff; + if (!(ioc->facts.IOCCapabilities & MPT_DIAG_CAPABILITY(buffer_type))) { + printk(MYIOC_s_DEBUG_FMT "%s: doesn't have Capability " +- "for buffer_type=%x\n", ioc->name, __func__, ++ "for buffer_type=%x\n", ioc->name, __FUNCTION__, + buffer_type); + return -EFAULT; + } + + if (karg.data.UniqueId != ioc->UniqueId[buffer_type]) { + printk(MYIOC_s_DEBUG_FMT "%s: unique_id=%x is not registered\n", +- ioc->name, __func__, karg.data.UniqueId); ++ ioc->name, __FUNCTION__, karg.data.UniqueId); + return -EFAULT; + } + + request_data = ioc->DiagBuffer[buffer_type]; + if (!request_data) { + printk(MYIOC_s_DEBUG_FMT "%s: doesn't have buffer for " +- "buffer_type=%x\n", ioc->name, __func__, buffer_type); ++ "buffer_type=%x\n", ioc->name, __FUNCTION__, buffer_type); + return -EFAULT; + } + + diagData = (void *)(request_data + karg.data.StartingOffset); + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: diagData=%p " +- "request_data=%p StartingOffset=%x\n", ioc->name, __func__, ++ "request_data=%p StartingOffset=%x\n", ioc->name, __FUNCTION__, + diagData, request_data, karg.data.StartingOffset)); + + if (copy_to_user((void __user *)&uarg->data.DiagnosticData[0], + diagData, karg.data.BytesToRead)) { + printk(MYIOC_s_ERR_FMT "%s: Unable to write " + "mpt_diag_read_buffer_t data @ %p\n", ioc->name, +- __func__, diagData); ++ __FUNCTION__, diagData); + return -EFAULT; + } + +@@ -585,18 +578,17 @@ + goto out; + + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: Reregister " +- "buffer_type=%x\n", ioc->name, __func__, buffer_type)); ++ "buffer_type=%x\n", ioc->name, __FUNCTION__, buffer_type)); + if ((ioc->DiagBuffer_Status[buffer_type] & +- MPT_DIAG_BUFFER_IS_RELEASED) == 0) { ++ MPT_DIAG_BUFFER_IS_RELEASED) == 0) { + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: buffer_type=%x " +- "is still registered\n", ioc->name, __func__, ++ "is still registered\n", ioc->name, __FUNCTION__, + buffer_type)); + return rc; + } + /* Get a free request frame and save the message context. + */ +- mf = mpt_get_msg_frame(mptctl_id, ioc); +- if (mf == NULL) ++ if ((mf = mpt_get_msg_frame(mptctl_id, ioc)) == NULL) + return -EAGAIN; + + diag_buffer_post_request = (DiagBufferPostRequest_t *)mf; +@@ -610,7 +602,7 @@ + diag_buffer_post_request->Reserved2 = 0; + diag_buffer_post_request->Reserved3 = 0; + diag_buffer_post_request->BufferAddress.High = 0; +- if (buffer_type == MPI_DIAG_BUF_TYPE_EXTENDED) ++ if ( buffer_type == MPI_DIAG_BUF_TYPE_EXTENDED ) + diag_buffer_post_request->ExtendedType = + cpu_to_le32(ioc->ExtendedType[buffer_type]); + diag_buffer_post_request->BufferLength = +@@ -635,7 +627,7 @@ + if (!(ioc->ioctl_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { + rc = -ETIME; + printk(MYIOC_s_WARN_FMT "%s: failed\n", ioc->name, +- __func__); ++ __FUNCTION__); + if (ioc->ioctl_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) { + mpt_free_msg_frame(ioc, mf); + goto out; +@@ -648,7 +640,7 @@ + /* process the completed Reply Message Frame */ + if ((ioc->ioctl_cmds.status & MPT_MGMT_STATUS_RF_VALID) == 0) { + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: status=%x\n", +- ioc->name, __func__, ioc->ioctl_cmds.status)); ++ ioc->name, __FUNCTION__, ioc->ioctl_cmds.status)); + rc = -EFAULT; + } + +@@ -662,7 +654,7 @@ + MPT_DIAG_BUFFER_IS_REGISTERED; + } else { + dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: IOCStatus=%x " +- "IOCLogInfo=%x\n", ioc->name, __func__, ++ "IOCLogInfo=%x\n", ioc->name, __FUNCTION__, + diag_buffer_post_reply->IOCStatus, + diag_buffer_post_reply->IOCLogInfo)); + rc = -EFAULT; +diff -r 8807687e8e9c drivers/message/fusion/rejected_ioctls/diag_buffer.h +--- a/drivers/message/fusion/rejected_ioctls/diag_buffer.h Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/message/fusion/rejected_ioctls/diag_buffer.h Tue Sep 01 16:11:23 2009 +0100 +@@ -1,13 +1,8 @@ +-#define MPTDIAGREGISTER \ +- _IOWR(MPT_MAGIC_NUMBER, 26, mpt_diag_register_t) +-#define MPTDIAGRELEASE \ +- _IOWR(MPT_MAGIC_NUMBER, 27, mpt_diag_release_t) +-#define MPTDIAGUNREGISTER \ +- _IOWR(MPT_MAGIC_NUMBER, 28, mpt_diag_unregister_t) +-#define MPTDIAGQUERY \ +- _IOWR(MPT_MAGIC_NUMBER, 29, mpt_diag_query_t) +-#define MPTDIAGREADBUFFER \ +- _IOWR(MPT_MAGIC_NUMBER, 30, mpt_diag_read_buffer_t) ++#define MPTDIAGREGISTER _IOWR(MPT_MAGIC_NUMBER,26,mpt_diag_register_t) ++#define MPTDIAGRELEASE _IOWR(MPT_MAGIC_NUMBER,27,mpt_diag_release_t) ++#define MPTDIAGUNREGISTER _IOWR(MPT_MAGIC_NUMBER,28,mpt_diag_unregister_t) ++#define MPTDIAGQUERY _IOWR(MPT_MAGIC_NUMBER,29,mpt_diag_query_t) ++#define MPTDIAGREADBUFFER _IOWR(MPT_MAGIC_NUMBER,30,mpt_diag_read_buffer_t) + + #define MPI_FW_DIAG_IOCTL (0x80646961) + #define MPI_FW_DIAG_TYPE_REGISTER (0x00000001) +@@ -30,8 +25,7 @@ + #define MPI_FW_DIAG_ERROR_NO_BUFFER (0x00000013) + #define MPI_FW_DIAG_ERROR_ALREADY_RELEASED (0x00000014) + +-#define MPT_DIAG_CAPABILITY(bufftype) \ +- (MPI_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER << bufftype) ++#define MPT_DIAG_CAPABILITY(bufftype) (MPI_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER << bufftype) + + #define MPT_DIAG_BUFFER_IS_REGISTERED 1 + #define MPT_DIAG_BUFFER_IS_RELEASED 2 diff --git a/master/netback-call-skb_checksum_setup-at-receive.patch b/master/netback-call-skb_checksum_setup-at-receive.patch new file mode 100644 index 0000000..b53edd2 --- /dev/null +++ b/master/netback-call-skb_checksum_setup-at-receive.patch @@ -0,0 +1,109 @@ +diff -r 8a57936f5555 drivers/xen/netback/netback.c +--- a/drivers/xen/netback/netback.c Fri Aug 07 11:43:25 2009 +0100 ++++ b/drivers/xen/netback/netback.c Fri Aug 07 11:44:50 2009 +0100 +@@ -1421,6 +1421,18 @@ + netif->stats.rx_bytes += skb->len; + netif->stats.rx_packets++; + ++ if (skb->ip_summed == CHECKSUM_PARTIAL) { ++ if (skb_checksum_setup(skb)) { ++ DPRINTK("Can't setup checksum in net_tx_action\n"); ++ kfree_skb(skb); ++ continue; ++ } ++ } else if (skb_is_gso(skb)) { ++ DPRINTK("Dropping GSO but not CHECKSUM_PARTIAL skb\n"); ++ kfree_skb(skb); ++ continue; ++ } ++ + if (unlikely(netbk_copy_skb_mode == NETBK_ALWAYS_COPY_SKB) && + unlikely(skb_linearize(skb))) { + DPRINTK("Can't linearize skb in net_tx_action.\n"); +diff -r 8a57936f5555 drivers/xen/netfront/netfront.c +--- a/drivers/xen/netfront/netfront.c Fri Aug 07 11:43:25 2009 +0100 ++++ b/drivers/xen/netfront/netfront.c Fri Aug 07 11:44:50 2009 +0100 +@@ -1479,6 +1479,18 @@ + /* Ethernet work: Delayed to here as it peeks the header. */ + skb->protocol = eth_type_trans(skb, dev); + ++ if (skb->ip_summed == CHECKSUM_PARTIAL) { ++ if (skb_checksum_setup(skb)) { ++ kfree_skb(skb); ++ dev->stats.rx_errors++; ++ continue; ++ } ++ } else if (skb_is_gso(skb)) { ++ kfree_skb(skb); ++ dev->stats.rx_errors++; ++ continue; ++ } ++ + /* Pass it up. */ + netif_receive_skb(skb); + dev->last_rx = jiffies; +diff -r 8a57936f5555 net/core/dev.c +--- a/net/core/dev.c Fri Aug 07 11:43:25 2009 +0100 ++++ b/net/core/dev.c Fri Aug 07 11:44:50 2009 +0100 +@@ -1762,8 +1762,8 @@ + if (skb->protocol != htons(ETH_P_IP)) + goto out; + +- iph = ip_hdr(skb); +- th = skb_network_header(skb) + 4 * iph->ihl; ++ iph = (void *)skb->data; ++ th = skb->data + 4 * iph->ihl; + if (th >= skb_tail_pointer(skb)) + goto out; + +@@ -1829,12 +1829,6 @@ + struct netdev_queue *txq; + struct Qdisc *q; + int rc = -ENOMEM; +- +- /* If a checksum-deferred packet is forwarded to a device that needs a +- * checksum, correct the pointers and force checksumming. +- */ +- if (skb_checksum_setup(skb)) +- goto out_kfree_skb; + + /* GSO will handle the following emulations directly. */ + if (netif_needs_gso(dev, skb)) +diff -r 8a57936f5555 net/ipv4/netfilter/nf_nat_proto_tcp.c +--- a/net/ipv4/netfilter/nf_nat_proto_tcp.c Fri Aug 07 11:43:25 2009 +0100 ++++ b/net/ipv4/netfilter/nf_nat_proto_tcp.c Fri Aug 07 11:44:50 2009 +0100 +@@ -75,9 +75,6 @@ + if (hdrsize < sizeof(*hdr)) + return true; + +- if (skb_checksum_setup(skb)) +- return false; +- + inet_proto_csum_replace4(&hdr->check, skb, oldip, newip, 1); + inet_proto_csum_replace2(&hdr->check, skb, oldport, newport, 0); + return true; +diff -r 8a57936f5555 net/ipv4/netfilter/nf_nat_proto_udp.c +--- a/net/ipv4/netfilter/nf_nat_proto_udp.c Fri Aug 07 11:43:25 2009 +0100 ++++ b/net/ipv4/netfilter/nf_nat_proto_udp.c Fri Aug 07 11:44:50 2009 +0100 +@@ -61,9 +61,6 @@ + portptr = &hdr->dest; + } + +- if (skb_checksum_setup(skb)) +- return false; +- + if (hdr->check || skb->ip_summed == CHECKSUM_PARTIAL) { + inet_proto_csum_replace4(&hdr->check, skb, oldip, newip, 1); + inet_proto_csum_replace2(&hdr->check, skb, *portptr, newport, +diff -r 8a57936f5555 net/ipv4/xfrm4_output.c +--- a/net/ipv4/xfrm4_output.c Fri Aug 07 11:43:25 2009 +0100 ++++ b/net/ipv4/xfrm4_output.c Fri Aug 07 11:44:50 2009 +0100 +@@ -81,7 +81,7 @@ + #endif + + skb->protocol = htons(ETH_P_IP); +- return skb_checksum_setup(skb) ?: xfrm_output(skb); ++ return xfrm_output(skb); + } + + int xfrm4_output(struct sk_buff *skb) diff --git a/master/netback-drop-xen-skb-members.patch b/master/netback-drop-xen-skb-members.patch new file mode 100644 index 0000000..d818978 --- /dev/null +++ b/master/netback-drop-xen-skb-members.patch @@ -0,0 +1,171 @@ +diff -r 56747c4f30e5 drivers/xen/netback/loopback.c +--- a/drivers/xen/netback/loopback.c Fri Aug 07 11:33:03 2009 +0100 ++++ b/drivers/xen/netback/loopback.c Fri Aug 07 12:00:36 2009 +0100 +@@ -151,16 +151,6 @@ + + np->stats.rx_bytes += skb->len; + np->stats.rx_packets++; +- +- if (skb->ip_summed == CHECKSUM_PARTIAL) { +- /* Defer checksum calculation. */ +- skb->proto_csum_blank = 1; +- /* Must be a local packet: assert its integrity. */ +- skb->proto_data_valid = 1; +- } +- +- skb->ip_summed = skb->proto_data_valid ? +- CHECKSUM_UNNECESSARY : CHECKSUM_NONE; + + skb->pkt_type = PACKET_HOST; /* overridden by eth_type_trans() */ + skb->protocol = eth_type_trans(skb, dev); +diff -r 56747c4f30e5 drivers/xen/netback/netback.c +--- a/drivers/xen/netback/netback.c Fri Aug 07 11:33:03 2009 +0100 ++++ b/drivers/xen/netback/netback.c Fri Aug 07 12:00:36 2009 +0100 +@@ -306,7 +306,6 @@ + /* Copy only the header fields we use in this driver. */ + nskb->dev = skb->dev; + nskb->ip_summed = skb->ip_summed; +- nskb->proto_data_valid = skb->proto_data_valid; + dev_kfree_skb(skb); + skb = nskb; + } +@@ -698,7 +697,7 @@ + + if (skb->ip_summed == CHECKSUM_PARTIAL) /* local packet? */ + flags |= NETRXF_csum_blank | NETRXF_data_validated; +- else if (skb->proto_data_valid) /* remote but checksummed? */ ++ else if (skb->ip_summed == CHECKSUM_UNNECESSARY) /* remote but checksummed? */ + flags |= NETRXF_data_validated; + + if (meta[npo.meta_cons].copy) +@@ -1407,18 +1406,10 @@ + netif_idx_release(pending_idx); + } + +- /* +- * Old frontends do not assert data_validated but we +- * can infer it from csum_blank so test both flags. +- */ +- if (txp->flags & (NETTXF_data_validated|NETTXF_csum_blank)) { ++ if (txp->flags & NETTXF_csum_blank) ++ skb->ip_summed = CHECKSUM_PARTIAL; ++ else if (txp->flags & NETTXF_data_validated) + skb->ip_summed = CHECKSUM_UNNECESSARY; +- skb->proto_data_valid = 1; +- } else { +- skb->ip_summed = CHECKSUM_NONE; +- skb->proto_data_valid = 0; +- } +- skb->proto_csum_blank = !!(txp->flags & NETTXF_csum_blank); + + netbk_fill_frags(skb); + +diff -r 56747c4f30e5 drivers/xen/netfront/netfront.c +--- a/drivers/xen/netfront/netfront.c Fri Aug 07 11:33:03 2009 +0100 ++++ b/drivers/xen/netfront/netfront.c Fri Aug 07 12:00:36 2009 +0100 +@@ -995,10 +995,8 @@ + + if (skb->ip_summed == CHECKSUM_PARTIAL) /* local packet? */ + tx->flags |= NETTXF_csum_blank | NETTXF_data_validated; +-#ifdef CONFIG_XEN +- if (skb->proto_data_valid) /* remote but checksummed? */ ++ else if (skb->ip_summed == CHECKSUM_UNNECESSARY) /* remote but checksummed? */ + tx->flags |= NETTXF_data_validated; +-#endif + + #if HAVE_TSO + if (skb_shinfo(skb)->gso_size) { +@@ -1424,18 +1422,11 @@ + skb->truesize += skb->data_len - (RX_COPY_THRESHOLD - len); + skb->len += skb->data_len; + +- /* +- * Old backends do not assert data_validated but we +- * can infer it from csum_blank so test both flags. +- */ +- if (rx->flags & (NETRXF_data_validated|NETRXF_csum_blank)) ++ if (rx->flags & NETRXF_csum_blank) ++ skb->ip_summed = CHECKSUM_PARTIAL; ++ else if (rx->flags & NETRXF_data_validated) + skb->ip_summed = CHECKSUM_UNNECESSARY; +- else +- skb->ip_summed = CHECKSUM_NONE; +-#ifdef CONFIG_XEN +- skb->proto_data_valid = (skb->ip_summed != CHECKSUM_NONE); +- skb->proto_csum_blank = !!(rx->flags & NETRXF_csum_blank); +-#endif ++ + np->stats.rx_packets++; + np->stats.rx_bytes += skb->len; + +diff -r 56747c4f30e5 include/linux/skbuff.h +--- a/include/linux/skbuff.h Fri Aug 07 11:33:03 2009 +0100 ++++ b/include/linux/skbuff.h Fri Aug 07 12:00:36 2009 +0100 +@@ -324,10 +324,6 @@ + #endif + #ifdef CONFIG_NETVM + __u8 emergency:1; +-#endif +-#ifdef CONFIG_XEN +- __u8 proto_data_valid:1, +- proto_csum_blank:1; + #endif + /* 10-16 bit hole */ + +diff -r 56747c4f30e5 net/core/dev.c +--- a/net/core/dev.c Fri Aug 07 11:33:03 2009 +0100 ++++ b/net/core/dev.c Fri Aug 07 12:00:36 2009 +0100 +@@ -1759,11 +1759,6 @@ + unsigned char *th; + int err = -EPROTO; + +-#ifdef CONFIG_XEN +- if (!skb->proto_csum_blank) +- return 0; +-#endif +- + if (skb->protocol != htons(ETH_P_IP)) + goto out; + +@@ -1793,7 +1788,6 @@ + + #ifdef CONFIG_XEN + skb->ip_summed = CHECKSUM_PARTIAL; +- skb->proto_csum_blank = 0; + #endif + + err = 0; +@@ -2347,19 +2341,6 @@ + if (skb->tc_verd & TC_NCLS) { + skb->tc_verd = CLR_TC_NCLS(skb->tc_verd); + goto ncls; +- } +-#endif +- +-#ifdef CONFIG_XEN +- switch (skb->ip_summed) { +- case CHECKSUM_UNNECESSARY: +- skb->proto_data_valid = 1; +- break; +- case CHECKSUM_PARTIAL: +- /* XXX Implement me. */ +- default: +- skb->proto_data_valid = 0; +- break; + } + #endif + +diff -r 56747c4f30e5 net/core/skbuff.c +--- a/net/core/skbuff.c Fri Aug 07 11:33:03 2009 +0100 ++++ b/net/core/skbuff.c Fri Aug 07 12:00:36 2009 +0100 +@@ -555,10 +555,6 @@ + n->hdr_len = skb->nohdr ? skb_headroom(skb) : skb->hdr_len; + n->cloned = 1; + n->nohdr = 0; +-#ifdef CONFIG_XEN +- C(proto_data_valid); +- C(proto_csum_blank); +-#endif + n->destructor = NULL; + C(iif); + C(tail); diff --git a/master/netback-force-CHECKSUM_PARTIAL-for-GSO.patch b/master/netback-force-CHECKSUM_PARTIAL-for-GSO.patch new file mode 100644 index 0000000..4d4b41e --- /dev/null +++ b/master/netback-force-CHECKSUM_PARTIAL-for-GSO.patch @@ -0,0 +1,34 @@ +diff -r 52e594b04f24 drivers/xen/netback/netback.c +--- a/drivers/xen/netback/netback.c Fri Aug 07 11:44:54 2009 +0100 ++++ b/drivers/xen/netback/netback.c Fri Aug 07 11:46:57 2009 +0100 +@@ -1413,6 +1413,13 @@ + else + skb->ip_summed = CHECKSUM_NONE; + ++ /* ++ * Workaround Windows frontends which do not set ++ * NETTXF_csum_blank for GSO packets. (CA-31049) ++ */ ++ if (skb_shinfo(skb)->gso_type) ++ skb->ip_summed = CHECKSUM_PARTIAL; ++ + netbk_fill_frags(skb); + + skb->dev = netif->dev; +diff -r 52e594b04f24 drivers/xen/netfront/netfront.c +--- a/drivers/xen/netfront/netfront.c Fri Aug 07 11:44:54 2009 +0100 ++++ b/drivers/xen/netfront/netfront.c Fri Aug 07 11:46:57 2009 +0100 +@@ -1436,6 +1436,13 @@ + else if (rx->flags & NETRXF_data_validated) + skb->ip_summed = CHECKSUM_UNNECESSARY; + ++ /* ++ * Workaround Windows frontends which do not set ++ * NETTXF_csum_blank for GSO packets. (CA-31049) ++ */ ++ if (skb_shinfo(skb)->gso_type) ++ skb->ip_summed = CHECKSUM_PARTIAL; ++ + np->stats.rx_packets++; + np->stats.rx_bytes += skb->len; + diff --git a/master/netback-tcp-and-ip-in-different-fragments b/master/netback-tcp-and-ip-in-different-fragments index 5442b7d..91e2771 100644 --- a/master/netback-tcp-and-ip-in-different-fragments +++ b/master/netback-tcp-and-ip-in-different-fragments @@ -47,11 +47,11 @@ diff -r 9889d3f55a9c net/core/dev.c @@ -1756,10 +1768,10 @@ goto out; - iph = ip_hdr(skb); + iph = (void *)skb->data; + if (!skb_pull_up_to(skb, iph + 1)) + goto out; + - th = skb_network_header(skb) + 4 * iph->ihl; + th = skb->data + 4 * iph->ihl; - if (th >= skb_tail_pointer(skb)) - goto out; - diff --git a/master/netxen_nic-4.0.50.patch b/master/netxen_nic-4.0.50.patch new file mode 100644 index 0000000..b7a3c5a --- /dev/null +++ b/master/netxen_nic-4.0.50.patch @@ -0,0 +1,12431 @@ +diff -r 6335373db0ec drivers/net/netxen/Makefile +--- a/drivers/net/netxen/Makefile Thu Oct 01 10:10:06 2009 +0100 ++++ b/drivers/net/netxen/Makefile Mon Oct 05 17:00:12 2009 +0100 +@@ -1,4 +1,5 @@ +-# Copyright (C) 2003 - 2006 NetXen, Inc. ++# Copyright (C) 2003 - 2009 NetXen, Inc. ++# Copyright (C) 2009 - QLogic Corporation. + # All rights reserved. + # + # This program is free software; you can redistribute it and/or +@@ -19,17 +20,10 @@ + # The full GNU General Public License is included in this distribution + # in the file called LICENSE. + # +-# Contact Information: +-# info@netxen.com +-# NetXen, +-# 3965 Freedom Circle, Fourth floor, +-# Santa Clara, CA 95054 +-# +-# Makefile for the NetXen NIC Driver + # + + + obj-$(CONFIG_NETXEN_NIC) := netxen_nic.o + + netxen_nic-y := netxen_nic_hw.o netxen_nic_main.o netxen_nic_init.o \ +- netxen_nic_ethtool.o netxen_nic_niu.o netxen_nic_ctx.o ++ netxen_nic_ethtool.o netxen_nic_ctx.o +diff -r 6335373db0ec drivers/net/netxen/netxen_nic.h +--- a/drivers/net/netxen/netxen_nic.h Thu Oct 01 10:10:06 2009 +0100 ++++ b/drivers/net/netxen/netxen_nic.h Mon Oct 05 17:00:12 2009 +0100 +@@ -1,5 +1,6 @@ + /* +- * Copyright (C) 2003 - 2006 NetXen, Inc. ++ * Copyright (C) 2003 - 2009 NetXen, Inc. ++ * Copyright (C) 2009 - QLogic Corporation. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or +@@ -20,11 +21,6 @@ + * The full GNU General Public License is included in this distribution + * in the file called LICENSE. + * +- * Contact Information: +- * info@netxen.com +- * NetXen, +- * 3965 Freedom Circle, Fourth floor, +- * Santa Clara, CA 95054 + */ + + #ifndef _NETXEN_NIC_H_ +@@ -33,10 +29,6 @@ + #include + #include + #include +-#include +-#include +-#include +-#include + #include + #include + #include +@@ -45,30 +37,37 @@ + #include + #include + #include ++#include + + #include + #include +-#include + #include + +-#include +-#include + #include + +-#include + #include + #include +-#include +-#include + ++#include "netxen_nic_hdr.h" + #include "netxen_nic_hw.h" + + #define _NETXEN_NIC_LINUX_MAJOR 4 + #define _NETXEN_NIC_LINUX_MINOR 0 +-#define _NETXEN_NIC_LINUX_SUBVERSION 11 +-#define NETXEN_NIC_LINUX_VERSIONID "4.0.11" ++#define _NETXEN_NIC_LINUX_SUBVERSION 50 ++#define NETXEN_NIC_LINUX_VERSIONID "4.0.50" + +-#define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c)) ++#define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) ++#define _major(v) (((v) >> 24) & 0xff) ++#define _minor(v) (((v) >> 16) & 0xff) ++#define _build(v) ((v) & 0xffff) ++ ++/* version in image has weird encoding: ++ * 7:0 - major ++ * 15:8 - minor ++ * 31:16 - build (little endian) ++ */ ++#define NETXEN_DECODE_VERSION(v) \ ++ NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) + + #define NETXEN_NUM_FLASH_SECTORS (64) + #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024) +@@ -77,19 +76,19 @@ + + #define PHAN_VENDOR_ID 0x4040 + +-#define RCV_DESC_RINGSIZE \ +- (sizeof(struct rcv_desc) * adapter->max_rx_desc_count) +-#define STATUS_DESC_RINGSIZE \ +- (sizeof(struct status_desc)* adapter->max_rx_desc_count) +-#define LRO_DESC_RINGSIZE \ +- (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count) +-#define TX_RINGSIZE \ +- (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count) +-#define RCV_BUFFSIZE \ +- (sizeof(struct netxen_rx_buffer) * rds_ring->max_rx_desc_count) ++#define RCV_DESC_RINGSIZE(rds_ring) \ ++ (sizeof(struct rcv_desc) * (rds_ring)->num_desc) ++#define RCV_BUFF_RINGSIZE(rds_ring) \ ++ (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc) ++#define STATUS_DESC_RINGSIZE(sds_ring) \ ++ (sizeof(struct status_desc) * (sds_ring)->num_desc) ++#define TX_BUFF_RINGSIZE(tx_ring) \ ++ (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc) ++#define TX_DESC_RINGSIZE(tx_ring) \ ++ (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) ++ + #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a))) + +-#define NETXEN_NETDEV_STATUS 0x1 + #define NETXEN_RCV_PRODUCER_OFFSET 0 + #define NETXEN_RCV_PEG_DB_ID 2 + #define NETXEN_HOST_DUMMY_DMA_SIZE 1024 +@@ -117,6 +116,7 @@ + #define NX_P3_A2 0x30 + #define NX_P3_B0 0x40 + #define NX_P3_B1 0x41 ++#define NX_P3_B2 0x42 + + #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1) + #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0) +@@ -139,18 +139,14 @@ + #define NX_ETHERMTU 1500 + #define NX_MAX_ETHERHDR 32 /* This contains some padding */ + +-#define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU) ++#define NX_P2_RX_BUF_MAX_LEN 1760 ++#define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU) + #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU) + #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU) + #define NX_CT_DEFAULT_RX_BUF_LEN 2048 ++#define NX_LRO_BUFFER_EXTRA 2048 + +-#define MAX_RX_BUFFER_LENGTH 1760 +-#define MAX_RX_JUMBO_BUFFER_LENGTH 8062 +-#define MAX_RX_LRO_BUFFER_LENGTH (8062) +-#define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2) +-#define RX_JUMBO_DMA_MAP_LEN \ +- (MAX_RX_JUMBO_BUFFER_LENGTH - 2) +-#define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2) ++#define NX_RX_LRO_BUFFER_LENGTH (8060) + + /* + * Maximum number of ring contexts +@@ -176,6 +172,8 @@ + #define MAX_NUM_CARDS 4 + + #define MAX_BUFFERS_PER_CMD 32 ++#define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4) ++#define NX_MAX_TX_TIMEOUTS 2 + + /* + * Following are the states of the Phantom. Phantom will set them and +@@ -188,42 +186,32 @@ + /* Host writes the following to notify that it has done the init-handshake */ + #define PHAN_INITIALIZE_ACK 0xf00f + +-#define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */ ++#define NUM_RCV_DESC_RINGS 3 ++#define NUM_STS_DESC_RINGS 4 + +-/* descriptor types */ +-#define RCV_DESC_NORMAL 0x01 +-#define RCV_DESC_JUMBO 0x02 +-#define RCV_DESC_LRO 0x04 +-#define RCV_DESC_NORMAL_CTXID 0 +-#define RCV_DESC_JUMBO_CTXID 1 +-#define RCV_DESC_LRO_CTXID 2 ++#define RCV_RING_NORMAL 0 ++#define RCV_RING_JUMBO 1 ++#define RCV_RING_LRO 2 + +-#define RCV_DESC_TYPE(ID) \ +- ((ID == RCV_DESC_JUMBO_CTXID) \ +- ? RCV_DESC_JUMBO \ +- : ((ID == RCV_DESC_LRO_CTXID) \ +- ? RCV_DESC_LRO : \ +- (RCV_DESC_NORMAL))) ++#define MIN_CMD_DESCRIPTORS 64 ++#define MIN_RCV_DESCRIPTORS 64 ++#define MIN_JUMBO_DESCRIPTORS 32 + +-#define MAX_CMD_DESCRIPTORS 4096 +-#define MAX_RCV_DESCRIPTORS 16384 +-#define MAX_CMD_DESCRIPTORS_HOST 1024 +-#define MAX_RCV_DESCRIPTORS_1G 2048 +-#define MAX_RCV_DESCRIPTORS_10G 4096 +-#define MAX_JUMBO_RCV_DESCRIPTORS 1024 ++#define MAX_CMD_DESCRIPTORS 1024 ++#define MAX_RCV_DESCRIPTORS_1G 4096 ++#define MAX_RCV_DESCRIPTORS_10G 8192 ++#define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 ++#define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 + #define MAX_LRO_RCV_DESCRIPTORS 8 +-#define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS +-#define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS +-#define MAX_RCV_DESC MAX_RCV_DESCRIPTORS +-#define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS +-#define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8) +-#define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \ +- MAX_LRO_RCV_DESCRIPTORS) +-#define MIN_TX_COUNT 4096 +-#define MIN_RX_COUNT 4096 ++ ++#define DEFAULT_RCV_DESCRIPTORS_1G 2048 ++#define DEFAULT_RCV_DESCRIPTORS_10G 4096 ++ + #define NETXEN_CTX_SIGNATURE 0xdee0 ++#define NETXEN_CTX_SIGNATURE_V2 0x0002dee0 ++#define NETXEN_CTX_RESET 0xbad0 ++#define NETXEN_CTX_D3_RESET 0xacc0 + #define NETXEN_RCV_PRODUCER(ringid) (ringid) +-#define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */ + + #define PHAN_PEG_RCV_INITIALIZED 0xff01 + #define PHAN_PEG_RCV_START_INITIALIZE 0xff00 +@@ -237,7 +225,7 @@ + #define MPORT_SINGLE_FUNCTION_MODE 0x1111 + #define MPORT_MULTI_FUNCTION_MODE 0x2222 + +-#include "netxen_nic_phan_reg.h" ++#define NX_MAX_PCI_FUNC 8 + + /* + * NetXen host-peg signal message structure +@@ -262,11 +250,18 @@ + #define netxen_set_msg_opcode(config_word, val) \ + ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28) + +-struct netxen_rcv_context { +- __le64 rcv_ring_addr; +- __le32 rcv_ring_size; ++struct netxen_rcv_ring { ++ __le64 addr; ++ __le32 size; + __le32 rsrvd; + }; ++ ++struct netxen_sts_ring { ++ __le64 addr; ++ __le32 size; ++ __le16 msi_index; ++ __le16 rsvd; ++} ; + + struct netxen_ring_ctx { + +@@ -277,13 +272,18 @@ + __le32 rsrvd; + + /* three receive rings */ +- struct netxen_rcv_context rcv_ctx[3]; ++ struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS]; + +- /* one status ring */ + __le64 sts_ring_addr; + __le32 sts_ring_size; + + __le32 ctx_id; ++ ++ __le64 rsrvd_2[3]; ++ __le32 sts_ring_count; ++ __le32 rsrvd_3; ++ struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS]; ++ + } __attribute__ ((aligned(64))); + + /* +@@ -302,6 +302,10 @@ + #define FLAGS_IPSEC_SA_ADD 0x04 + #define FLAGS_IPSEC_SA_DELETE 0x08 + #define FLAGS_VLAN_TAGGED 0x10 ++#define FLAGS_VLAN_OOB 0x40 ++ ++#define netxen_set_tx_vlan_tci(cmd_desc, v) \ ++ (cmd_desc)->vlan_TCI = cpu_to_le16(v); + + #define netxen_set_cmd_desc_port(cmd_desc, var) \ + ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) +@@ -316,61 +320,33 @@ + cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)) + + #define netxen_set_tx_frags_len(_desc, _frags, _len) \ +- (_desc)->num_of_buffers_total_length = \ ++ (_desc)->nfrags__length = \ + cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)) + + struct cmd_desc_type0 { + u8 tcp_hdr_offset; /* For LSO only */ + u8 ip_hdr_offset; /* For LSO only */ +- /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */ +- __le16 flags_opcode; +- /* Bit pattern: 0-7 total number of segments, +- 8-31 Total size of the packet */ +- __le32 num_of_buffers_total_length; +- union { +- struct { +- __le32 addr_low_part2; +- __le32 addr_high_part2; +- }; +- __le64 addr_buffer2; +- }; ++ __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ ++ __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ + +- __le16 reference_handle; /* changed to u16 to add mss */ +- __le16 mss; /* passed by NDIS_PACKET for LSO */ +- /* Bit pattern 0-3 port, 0-3 ctx id */ +- u8 port_ctxid; ++ __le64 addr_buffer2; ++ ++ __le16 reference_handle; ++ __le16 mss; ++ u8 port_ctxid; /* 7:4 ctxid 3:0 port */ + u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ + __le16 conn_id; /* IPSec offoad only */ + +- union { +- struct { +- __le32 addr_low_part3; +- __le32 addr_high_part3; +- }; +- __le64 addr_buffer3; +- }; +- union { +- struct { +- __le32 addr_low_part1; +- __le32 addr_high_part1; +- }; +- __le64 addr_buffer1; +- }; ++ __le64 addr_buffer3; ++ __le64 addr_buffer1; + +- __le16 buffer1_length; +- __le16 buffer2_length; +- __le16 buffer3_length; +- __le16 buffer4_length; ++ __le16 buffer_length[4]; + +- union { +- struct { +- __le32 addr_low_part4; +- __le32 addr_high_part4; +- }; +- __le64 addr_buffer4; +- }; ++ __le64 addr_buffer4; + +- __le64 unused; ++ __le32 reserved2; ++ __le16 reserved; ++ __le16 vlan_TCI; + + } __attribute__ ((aligned(64))); + +@@ -383,27 +359,25 @@ + }; + + /* opcode field in status_desc */ ++#define NETXEN_NIC_SYN_OFFLOAD 0x03 + #define NETXEN_NIC_RXPKT_DESC 0x04 + #define NETXEN_OLD_RXPKT_DESC 0x3f ++#define NETXEN_NIC_RESPONSE_DESC 0x05 ++#define NETXEN_NIC_LRO_DESC 0x12 + + /* for status field in status_desc */ + #define STATUS_NEED_CKSUM (1) + #define STATUS_CKSUM_OK (2) + + /* owner bits of status_desc */ +-#define STATUS_OWNER_HOST (0x1) +-#define STATUS_OWNER_PHANTOM (0x2) ++#define STATUS_OWNER_HOST (0x1ULL << 56) ++#define STATUS_OWNER_PHANTOM (0x2ULL << 56) + +-#define NETXEN_PROT_IP (1) +-#define NETXEN_PROT_UNKNOWN (0) +- +-/* Note: sizeof(status_desc) should always be a mutliple of 2 */ +- +-#define netxen_get_sts_desc_lro_cnt(status_desc) \ +- ((status_desc)->lro & 0x7F) +-#define netxen_get_sts_desc_lro_last_frag(status_desc) \ +- (((status_desc)->lro & 0x80) >> 7) +- ++/* Status descriptor: ++ 0-3 port, 4-7 status, 8-11 type, 12-27 total_length ++ 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset ++ 53-55 desc_cnt, 56-57 owner, 58-63 opcode ++ */ + #define netxen_get_sts_port(sts_data) \ + ((sts_data) & 0x0F) + #define netxen_get_sts_status(sts_data) \ +@@ -418,50 +392,33 @@ + (((sts_data) >> 44) & 0x0F) + #define netxen_get_sts_pkt_offset(sts_data) \ + (((sts_data) >> 48) & 0x1F) ++#define netxen_get_sts_desc_cnt(sts_data) \ ++ (((sts_data) >> 53) & 0x7) + #define netxen_get_sts_opcode(sts_data) \ + (((sts_data) >> 58) & 0x03F) + +-#define netxen_get_sts_owner(status_desc) \ +- ((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03) +-#define netxen_set_sts_owner(status_desc, val) { \ +- (status_desc)->status_desc_data = \ +- ((status_desc)->status_desc_data & \ +- ~cpu_to_le64(0x3ULL << 56)) | \ +- cpu_to_le64((u64)((val) & 0x3) << 56); \ +-} ++#define netxen_get_lro_sts_refhandle(sts_data) \ ++ ((sts_data) & 0x0FFFF) ++#define netxen_get_lro_sts_length(sts_data) \ ++ (((sts_data) >> 16) & 0x0FFFF) ++#define netxen_get_lro_sts_l2_hdr_offset(sts_data) \ ++ (((sts_data) >> 32) & 0x0FF) ++#define netxen_get_lro_sts_l4_hdr_offset(sts_data) \ ++ (((sts_data) >> 40) & 0x0FF) ++#define netxen_get_lro_sts_timestamp(sts_data) \ ++ (((sts_data) >> 48) & 0x1) ++#define netxen_get_lro_sts_type(sts_data) \ ++ (((sts_data) >> 49) & 0x7) ++#define netxen_get_lro_sts_push_flag(sts_data) \ ++ (((sts_data) >> 52) & 0x1) ++#define netxen_get_lro_sts_seq_number(sts_data) \ ++ ((sts_data) & 0x0FFFFFFFF) ++ + + struct status_desc { +- /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length +- 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset +- 53-55 desc_cnt, 56-57 owner, 58-63 opcode +- */ +- __le64 status_desc_data; +- union { +- struct { +- __le32 hash_value; +- u8 hash_type; +- u8 msg_type; +- u8 unused; +- union { +- /* Bit pattern: 0-6 lro_count indicates frag +- * sequence, 7 last_frag indicates last frag +- */ +- u8 lro; +- +- /* chained buffers */ +- u8 nr_frags; +- }; +- }; +- struct { +- __le16 frag_handles[4]; +- }; +- }; ++ __le64 status_desc_data[2]; + } __attribute__ ((aligned(16))); + +-enum { +- NETXEN_RCV_PEG_0 = 0, +- NETXEN_RCV_PEG_1 +-}; + /* The version of the main data structure */ + #define NETXEN_BDINFO_VERSION 1 + +@@ -471,275 +428,69 @@ + /* Max number of Gig ports on a Phantom board */ + #define NETXEN_MAX_PORTS 4 + +-typedef enum { +- NETXEN_BRDTYPE_P1_BD = 0x0000, +- NETXEN_BRDTYPE_P1_SB = 0x0001, +- NETXEN_BRDTYPE_P1_SMAX = 0x0002, +- NETXEN_BRDTYPE_P1_SOCK = 0x0003, ++#define NETXEN_BRDTYPE_P1_BD 0x0000 ++#define NETXEN_BRDTYPE_P1_SB 0x0001 ++#define NETXEN_BRDTYPE_P1_SMAX 0x0002 ++#define NETXEN_BRDTYPE_P1_SOCK 0x0003 + +- NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008, +- NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009, +- NETXEN_BRDTYPE_P2_SB35_4G = 0x000a, +- NETXEN_BRDTYPE_P2_SB31_10G = 0x000b, +- NETXEN_BRDTYPE_P2_SB31_2G = 0x000c, ++#define NETXEN_BRDTYPE_P2_SOCK_31 0x0008 ++#define NETXEN_BRDTYPE_P2_SOCK_35 0x0009 ++#define NETXEN_BRDTYPE_P2_SB35_4G 0x000a ++#define NETXEN_BRDTYPE_P2_SB31_10G 0x000b ++#define NETXEN_BRDTYPE_P2_SB31_2G 0x000c + +- NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d, +- NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e, +- NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f, ++#define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d ++#define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e ++#define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f + +- NETXEN_BRDTYPE_P3_REF_QG = 0x0021, +- NETXEN_BRDTYPE_P3_HMEZ = 0x0022, +- NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023, +- NETXEN_BRDTYPE_P3_4_GB = 0x0024, +- NETXEN_BRDTYPE_P3_IMEZ = 0x0025, +- NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026, +- NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027, +- NETXEN_BRDTYPE_P3_XG_LOM = 0x0028, +- NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029, +- NETXEN_BRDTYPE_P3_10G_SFP_CT = 0x002a, +- NETXEN_BRDTYPE_P3_10G_SFP_QT = 0x002b, +- NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031, +- NETXEN_BRDTYPE_P3_10G_XFP = 0x0032, +- NETXEN_BRDTYPE_P3_10G_TP = 0x0080 +- +-} netxen_brdtype_t; +- +-typedef enum { +- NETXEN_BRDMFG_INVENTEC = 1 +-} netxen_brdmfg; +- +-typedef enum { +- MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */ +- MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */ +- MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */ +- MEM_ORG_256Mbx4 = 0x3, +- MEM_ORG_256Mbx8 = 0x4, +- MEM_ORG_256Mbx16 = 0x5, +- MEM_ORG_512Mbx4 = 0x6, +- MEM_ORG_512Mbx8 = 0x7, +- MEM_ORG_512Mbx16 = 0x8, +- MEM_ORG_1Gbx4 = 0x9, +- MEM_ORG_1Gbx8 = 0xa, +- MEM_ORG_1Gbx16 = 0xb, +- MEM_ORG_2Gbx4 = 0xc, +- MEM_ORG_2Gbx8 = 0xd, +- MEM_ORG_2Gbx16 = 0xe, +- MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */ +- MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */ +-} netxen_mn_mem_org_t; +- +-typedef enum { +- MEM_ORG_512Kx36 = 0x0, +- MEM_ORG_1Mx36 = 0x1, +- MEM_ORG_2Mx36 = 0x2 +-} netxen_sn_mem_org_t; +- +-typedef enum { +- MEM_DEPTH_4MB = 0x1, +- MEM_DEPTH_8MB = 0x2, +- MEM_DEPTH_16MB = 0x3, +- MEM_DEPTH_32MB = 0x4, +- MEM_DEPTH_64MB = 0x5, +- MEM_DEPTH_128MB = 0x6, +- MEM_DEPTH_256MB = 0x7, +- MEM_DEPTH_512MB = 0x8, +- MEM_DEPTH_1GB = 0x9, +- MEM_DEPTH_2GB = 0xa, +- MEM_DEPTH_4GB = 0xb, +- MEM_DEPTH_8GB = 0xc, +- MEM_DEPTH_16GB = 0xd, +- MEM_DEPTH_32GB = 0xe +-} netxen_mem_depth_t; +- +-struct netxen_board_info { +- u32 header_version; +- +- u32 board_mfg; +- u32 board_type; +- u32 board_num; +- u32 chip_id; +- u32 chip_minor; +- u32 chip_major; +- u32 chip_pkg; +- u32 chip_lot; +- +- u32 port_mask; /* available niu ports */ +- u32 peg_mask; /* available pegs */ +- u32 icache_ok; /* can we run with icache? */ +- u32 dcache_ok; /* can we run with dcache? */ +- u32 casper_ok; +- +- u32 mac_addr_lo_0; +- u32 mac_addr_lo_1; +- u32 mac_addr_lo_2; +- u32 mac_addr_lo_3; +- +- /* MN-related config */ +- u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */ +- u32 mn_sync_shift_cclk; +- u32 mn_sync_shift_mclk; +- u32 mn_wb_en; +- u32 mn_crystal_freq; /* in MHz */ +- u32 mn_speed; /* in MHz */ +- u32 mn_org; +- u32 mn_depth; +- u32 mn_ranks_0; /* ranks per slot */ +- u32 mn_ranks_1; /* ranks per slot */ +- u32 mn_rd_latency_0; +- u32 mn_rd_latency_1; +- u32 mn_rd_latency_2; +- u32 mn_rd_latency_3; +- u32 mn_rd_latency_4; +- u32 mn_rd_latency_5; +- u32 mn_rd_latency_6; +- u32 mn_rd_latency_7; +- u32 mn_rd_latency_8; +- u32 mn_dll_val[18]; +- u32 mn_mode_reg; /* MIU DDR Mode Register */ +- u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */ +- u32 mn_timing_0; /* MIU Memory Control Timing Rgister */ +- u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */ +- u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */ +- +- /* SN-related config */ +- u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */ +- u32 sn_pt_mode; /* pass through mode */ +- u32 sn_ecc_en; +- u32 sn_wb_en; +- u32 sn_crystal_freq; +- u32 sn_speed; +- u32 sn_org; +- u32 sn_depth; +- u32 sn_dll_tap; +- u32 sn_rd_latency; +- +- u32 mac_addr_hi_0; +- u32 mac_addr_hi_1; +- u32 mac_addr_hi_2; +- u32 mac_addr_hi_3; +- +- u32 magic; /* indicates flash has been initialized */ +- +- u32 mn_rdimm; +- u32 mn_dll_override; +- +-}; +- +-#define FLASH_NUM_PORTS (4) +- +-struct netxen_flash_mac_addr { +- u32 flash_addr[32]; +-}; +- +-struct netxen_user_old_info { +- u8 flash_md5[16]; +- u8 crbinit_md5[16]; +- u8 brdcfg_md5[16]; +- /* bootloader */ +- u32 bootld_version; +- u32 bootld_size; +- u8 bootld_md5[16]; +- /* image */ +- u32 image_version; +- u32 image_size; +- u8 image_md5[16]; +- /* primary image status */ +- u32 primary_status; +- u32 secondary_present; +- +- /* MAC address , 4 ports */ +- struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS]; +-}; +-#define FLASH_NUM_MAC_PER_PORT 32 +-struct netxen_user_info { +- u8 flash_md5[16 * 64]; +- /* bootloader */ +- u32 bootld_version; +- u32 bootld_size; +- /* image */ +- u32 image_version; +- u32 image_size; +- /* primary image status */ +- u32 primary_status; +- u32 secondary_present; +- +- /* MAC address , 4 ports, 32 address per port */ +- u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; +- u32 sub_sys_id; +- u8 serial_num[32]; +- +- /* Any user defined data */ +-}; +- +-/* +- * Flash Layout - new format. +- */ +-struct netxen_new_user_info { +- u8 flash_md5[16 * 64]; +- /* bootloader */ +- u32 bootld_version; +- u32 bootld_size; +- /* image */ +- u32 image_version; +- u32 image_size; +- /* primary image status */ +- u32 primary_status; +- u32 secondary_present; +- +- /* MAC address , 4 ports, 32 address per port */ +- u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; +- u32 sub_sys_id; +- u8 serial_num[32]; +- +- /* Any user defined data */ +-}; +- +-#define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6 +-#define SECONDARY_IMAGE_ABSENT 0xffffffff +-#define PRIMARY_IMAGE_GOOD 0x5a5a5a5a +-#define PRIMARY_IMAGE_BAD 0xffffffff ++#define NETXEN_BRDTYPE_P3_REF_QG 0x0021 ++#define NETXEN_BRDTYPE_P3_HMEZ 0x0022 ++#define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023 ++#define NETXEN_BRDTYPE_P3_4_GB 0x0024 ++#define NETXEN_BRDTYPE_P3_IMEZ 0x0025 ++#define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026 ++#define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027 ++#define NETXEN_BRDTYPE_P3_XG_LOM 0x0028 ++#define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029 ++#define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a ++#define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b ++#define NETXEN_BRDTYPE_P3_10G_CX4 0x0031 ++#define NETXEN_BRDTYPE_P3_10G_XFP 0x0032 ++#define NETXEN_BRDTYPE_P3_10G_TP 0x0080 + + /* Flash memory map */ +-typedef enum { +- NETXEN_CRBINIT_START = 0, /* Crbinit section */ +- NETXEN_BRDCFG_START = 0x4000, /* board config */ +- NETXEN_INITCODE_START = 0x6000, /* pegtune code */ +- NETXEN_BOOTLD_START = 0x10000, /* bootld */ +- NETXEN_IMAGE_START = 0x43000, /* compressed image */ +- NETXEN_SECONDARY_START = 0x200000, /* backup images */ +- NETXEN_PXE_START = 0x3E0000, /* user defined region */ +- NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */ +- NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */ +-} netxen_flash_map_t; ++#define NETXEN_CRBINIT_START 0 /* crbinit section */ ++#define NETXEN_BRDCFG_START 0x4000 /* board config */ ++#define NETXEN_INITCODE_START 0x6000 /* pegtune code */ ++#define NETXEN_BOOTLD_START 0x10000 /* bootld */ ++#define NETXEN_IMAGE_START 0x43000 /* compressed image */ ++#define NETXEN_SECONDARY_START 0x200000 /* backup images */ ++#define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */ ++#define NETXEN_USER_START 0x3E8000 /* Firmare info */ ++#define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */ ++#define NETXEN_USER_START_OLD NETXEN_PXE_START /* very old flash */ + +-#define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */ ++#define NX_OLD_MAC_ADDR_OFFSET (NETXEN_USER_START) ++#define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408) ++#define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c) ++#define NX_FW_MAC_ADDR_OFFSET (NETXEN_USER_START+0x418) ++#define NX_FW_SERIAL_NUM_OFFSET (NETXEN_USER_START+0x81c) ++#define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c) + +-#define NETXEN_FLASH_START (NETXEN_CRBINIT_START) +-#define NETXEN_INIT_SECTOR (0) +-#define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START) +-#define NETXEN_FLASH_CRBINIT_SIZE (0x4000) +-#define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info)) +-#define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32)) +-#define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START) +-#define NETXEN_NUM_PRIMARY_SECTORS (0x20) +-#define NETXEN_NUM_CONFIG_SECTORS (1) +-#define PFX "NetXen: " ++#define NX_HDR_VERSION_OFFSET (NETXEN_BRDCFG_START) ++#define NX_BRDTYPE_OFFSET (NETXEN_BRDCFG_START+0x8) ++#define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128) ++ ++#define NX_FW_MIN_SIZE (0x3fffff) ++#define NX_P2_MN_ROMIMAGE 0 ++#define NX_P3_CT_ROMIMAGE 1 ++#define NX_P3_MN_ROMIMAGE 2 ++#define NX_FLASH_ROMIMAGE 3 ++ + extern char netxen_nic_driver_name[]; + +-/* Note: Make sure to not call this before adapter->port is valid */ +-#if !defined(NETXEN_DEBUG) +-#define DPRINTK(klevel, fmt, args...) do { \ +- } while (0) +-#else +-#define DPRINTK(klevel, fmt, args...) do { \ +- printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\ +- (adapter != NULL && adapter->netdev != NULL) ? \ +- adapter->netdev->name : NULL, \ +- ## args); } while(0) +-#endif +- + /* Number of status descriptors to handle per interrupt */ +-#define MAX_STATUS_HANDLE (128) ++#define MAX_STATUS_HANDLE (64) + + /* + * netxen_skb_frag{} is to contain mapping info for each SG list. This +@@ -747,20 +498,14 @@ + */ + struct netxen_skb_frag { + u64 dma; +- ulong length; ++ u64 length; + }; + +-#define _netxen_set_bits(config_word, start, bits, val) {\ +- unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\ +- unsigned long long __tvalue = (val); \ +- (config_word) &= ~__tmask; \ +- (config_word) |= (((__tvalue) << (start)) & __tmask); \ +-} +- +-#define _netxen_clear_bits(config_word, start, bits) {\ +- unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \ +- (config_word) &= ~__tmask; \ +-} ++struct netxen_recv_crb { ++ u32 crb_rcv_producer[NUM_RCV_DESC_RINGS]; ++ u32 crb_sts_consumer[NUM_STS_DESC_RINGS]; ++ u32 sw_int_mask[NUM_STS_DESC_RINGS]; ++}; + + /* Following defines are for the state of the buffers */ + #define NETXEN_BUFFER_FREE 0 +@@ -783,9 +528,6 @@ + u64 dma; + u16 ref_handle; + u16 state; +- u32 lro_expected_frags; +- u32 lro_current_frags; +- u32 lro_length; + }; + + /* Board types */ +@@ -800,49 +542,36 @@ + void __iomem *pci_base0; + void __iomem *pci_base1; + void __iomem *pci_base2; +- unsigned long first_page_group_end; +- unsigned long first_page_group_start; + void __iomem *db_base; + unsigned long db_len; + unsigned long pci_len0; + +- u8 cut_through; + int qdr_sn_window; + int ddr_mn_window; +- unsigned long mn_win_crb; +- unsigned long ms_win_crb; ++ u32 mn_win_crb; ++ u32 ms_win_crb; + ++ u8 cut_through; + u8 revision_id; ++ u8 pci_func; ++ u8 linkup; ++ u16 port_type; + u16 board_type; +- struct netxen_board_info boardcfg; +- u32 linkup; +- /* Address of cmd ring in Phantom */ +- struct cmd_desc_type0 *cmd_desc_head; +- dma_addr_t cmd_desc_phys_addr; +- struct netxen_adapter *adapter; +- int pci_func; + }; +- +-#define RCV_RING_LRO RCV_DESC_LRO + + #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ + #define ETHERNET_FCS_SIZE 4 + + struct netxen_adapter_stats { +- u64 rcvdbadskb; + u64 xmitcalled; +- u64 xmitedframes; + u64 xmitfinished; +- u64 badskblen; +- u64 nocmddescriptor; +- u64 polled; + u64 rxdropped; + u64 txdropped; + u64 csummed; +- u64 no_rcv; ++ u64 rx_pkts; ++ u64 lro_pkts; + u64 rxbytes; + u64 txbytes; +- u64 ints; + }; + + /* +@@ -850,16 +579,49 @@ + * be one Rcv Descriptor for normal packets, one for jumbo and may be others. + */ + struct nx_host_rds_ring { +- u32 flags; + u32 producer; +- dma_addr_t phys_addr; +- u32 crb_rcv_producer; /* reg offset */ +- struct rcv_desc *desc_head; /* address of rx ring in Phantom */ +- u32 max_rx_desc_count; ++ u32 num_desc; + u32 dma_size; + u32 skb_size; +- struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */ ++ u32 flags; ++ void __iomem *crb_rcv_producer; ++ struct rcv_desc *desc_head; ++ struct netxen_rx_buffer *rx_buf_arr; + struct list_head free_list; ++ spinlock_t lock; ++ dma_addr_t phys_addr; ++}; ++ ++struct nx_host_sds_ring { ++ u32 consumer; ++ u32 num_desc; ++ void __iomem *crb_sts_consumer; ++ void __iomem *crb_intr_mask; ++ ++ struct status_desc *desc_head; ++ struct netxen_adapter *adapter; ++ struct napi_struct napi; ++ struct list_head free_list[NUM_RCV_DESC_RINGS]; ++ ++ int irq; ++ ++ dma_addr_t phys_addr; ++ char name[IFNAMSIZ+4]; ++}; ++ ++struct nx_host_tx_ring { ++ u32 producer; ++ __le32 *hw_consumer; ++ u32 sw_consumer; ++ void __iomem *crb_cmd_producer; ++ void __iomem *crb_cmd_consumer; ++ u32 num_desc; ++ ++ struct netdev_queue *txq; ++ ++ struct netxen_cmd_buffer *cmd_buf_arr; ++ struct cmd_desc_type0 *desc_head; ++ dma_addr_t phys_addr; + }; + + /* +@@ -873,11 +635,11 @@ + u16 context_id; + u16 virt_port; + +- struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS]; +- u32 status_rx_consumer; +- u32 crb_sts_consumer; /* reg offset */ +- dma_addr_t rcv_status_desc_phys_addr; +- struct status_desc *rcv_status_desc_head; ++ struct nx_host_rds_ring *rds_rings; ++ struct nx_host_sds_ring *sds_rings; ++ ++ struct netxen_ring_ctx *hwctx; ++ dma_addr_t phys_addr; + }; + + /* New HW context creation */ +@@ -921,7 +683,19 @@ + #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f + #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010 + #define NX_CDRP_CMD_SET_MTU 0x00000012 +-#define NX_CDRP_CMD_MAX 0x00000013 ++#define NX_CDRP_CMD_READ_PHY 0x00000013 ++#define NX_CDRP_CMD_WRITE_PHY 0x00000014 ++#define NX_CDRP_CMD_READ_HW_REG 0x00000015 ++#define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016 ++#define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017 ++#define NX_CDRP_CMD_READ_MAX_MTU 0x00000018 ++#define NX_CDRP_CMD_READ_MAX_LRO 0x00000019 ++#define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a ++#define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b ++#define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c ++#define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d ++#define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e ++#define NX_CDRP_CMD_MAX 0x0000001f + + #define NX_RCODE_SUCCESS 0 + #define NX_RCODE_NO_HOST_MEM 1 +@@ -962,6 +736,7 @@ + #define NX_CAP0_LSO NX_CAP_BIT(0, 6) + #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7) + #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8) ++#define NX_CAP0_HW_LRO NX_CAP_BIT(0, 10) + + /* + * Context state +@@ -1116,8 +891,8 @@ + #define NETXEN_MAC_DEL 2 + + typedef struct nx_mac_list_s { +- struct nx_mac_list_s *next; +- uint8_t mac_addr[MAX_ADDR_LEN]; ++ struct list_head list; ++ uint8_t mac_addr[ETH_ALEN+2]; + } nx_mac_list_t; + + /* +@@ -1159,30 +934,139 @@ + + #define NX_MAC_EVENT 0x1 + +-enum { +- NX_NIC_H2C_OPCODE_START = 0, +- NX_NIC_H2C_OPCODE_CONFIG_RSS, +- NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL, +- NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE, +- NX_NIC_H2C_OPCODE_CONFIG_LED, +- NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS, +- NX_NIC_H2C_OPCODE_CONFIG_L2_MAC, +- NX_NIC_H2C_OPCODE_LRO_REQUEST, +- NX_NIC_H2C_OPCODE_GET_SNMP_STATS, +- NX_NIC_H2C_OPCODE_PROXY_START_REQUEST, +- NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST, +- NX_NIC_H2C_OPCODE_PROXY_SET_MTU, +- NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE, +- NX_H2P_OPCODE_GET_FINGER_PRINT_REQUEST, +- NX_H2P_OPCODE_INSTALL_LICENSE_REQUEST, +- NX_H2P_OPCODE_GET_LICENSE_CAPABILITY_REQUEST, +- NX_NIC_H2C_OPCODE_GET_NET_STATS, +- NX_NIC_H2C_OPCODE_LAST +-}; ++#define NX_IP_UP 2 ++#define NX_IP_DOWN 3 ++ ++/* ++ * Driver --> Firmware ++ */ ++#define NX_NIC_H2C_OPCODE_START 0 ++#define NX_NIC_H2C_OPCODE_CONFIG_RSS 1 ++#define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2 ++#define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3 ++#define NX_NIC_H2C_OPCODE_CONFIG_LED 4 ++#define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5 ++#define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6 ++#define NX_NIC_H2C_OPCODE_LRO_REQUEST 7 ++#define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8 ++#define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9 ++#define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10 ++#define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11 ++#define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12 ++#define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13 ++#define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14 ++#define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15 ++#define NX_NIC_H2C_OPCODE_GET_NET_STATS 16 ++#define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17 ++#define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18 ++#define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19 ++#define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20 ++#define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21 ++#define NX_NIC_C2C_OPCODE 22 ++#define NX_NIC_H2C_OPCODE_CONFIG_BRIDGING 23 ++#define NX_NIC_H2C_OPCODE_CONFIG_HW_LRO 24 ++#define NX_NIC_H2C_OPCODE_LAST 25 ++ ++/* ++ * Firmware --> Driver ++ */ ++ ++#define NX_NIC_C2H_OPCODE_START 128 ++#define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129 ++#define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130 ++#define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131 ++#define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132 ++#define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133 ++#define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134 ++#define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135 ++#define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136 ++#define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137 ++#define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138 ++#define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139 ++#define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140 ++#define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 ++#define NX_NIC_C2H_OPCODE_LAST 142 + + #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ + #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ + #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ ++ ++#define NX_NIC_LRO_REQUEST_FIRST 0 ++#define NX_NIC_LRO_REQUEST_ADD_FLOW 1 ++#define NX_NIC_LRO_REQUEST_DELETE_FLOW 2 ++#define NX_NIC_LRO_REQUEST_TIMER 3 ++#define NX_NIC_LRO_REQUEST_CLEANUP 4 ++#define NX_NIC_LRO_REQUEST_ADD_FLOW_SCHEDULED 5 ++#define NX_TOE_LRO_REQUEST_ADD_FLOW 6 ++#define NX_TOE_LRO_REQUEST_ADD_FLOW_RESPONSE 7 ++#define NX_TOE_LRO_REQUEST_DELETE_FLOW 8 ++#define NX_TOE_LRO_REQUEST_DELETE_FLOW_RESPONSE 9 ++#define NX_TOE_LRO_REQUEST_TIMER 10 ++#define NX_NIC_LRO_REQUEST_LAST 11 ++ ++#define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5) ++#define NX_FW_CAPABILITY_SWITCHING (1 << 6) ++#define NX_FW_CAPABILITY_PEXQ (1 << 7) ++#define NX_FW_CAPABILITY_BDG (1 << 8) ++#define NX_FW_CAPABILITY_FVLANTX (1 << 9) ++#define NX_FW_CAPABILITY_HW_LRO (1 << 10) ++ ++/* module types */ ++#define LINKEVENT_MODULE_NOT_PRESENT 1 ++#define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 ++#define LINKEVENT_MODULE_OPTICAL_SRLR 3 ++#define LINKEVENT_MODULE_OPTICAL_LRM 4 ++#define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 ++#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 ++#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 ++#define LINKEVENT_MODULE_TWINAX 8 ++ ++#define LINKSPEED_10GBPS 10000 ++#define LINKSPEED_1GBPS 1000 ++#define LINKSPEED_100MBPS 100 ++#define LINKSPEED_10MBPS 10 ++ ++#define LINKSPEED_ENCODED_10MBPS 0 ++#define LINKSPEED_ENCODED_100MBPS 1 ++#define LINKSPEED_ENCODED_1GBPS 2 ++ ++#define LINKEVENT_AUTONEG_DISABLED 0 ++#define LINKEVENT_AUTONEG_ENABLED 1 ++ ++#define LINKEVENT_HALF_DUPLEX 0 ++#define LINKEVENT_FULL_DUPLEX 1 ++ ++#define LINKEVENT_LINKSPEED_MBPS 0 ++#define LINKEVENT_LINKSPEED_ENCODED 1 ++ ++/* firmware response header: ++ * 63:58 - message type ++ * 57:56 - owner ++ * 55:53 - desc count ++ * 52:48 - reserved ++ * 47:40 - completion id ++ * 39:32 - opcode ++ * 31:16 - error code ++ * 15:00 - reserved ++ */ ++#define netxen_get_nic_msgtype(msg_hdr) \ ++ ((msg_hdr >> 58) & 0x3F) ++#define netxen_get_nic_msg_compid(msg_hdr) \ ++ ((msg_hdr >> 40) & 0xFF) ++#define netxen_get_nic_msg_opcode(msg_hdr) \ ++ ((msg_hdr >> 32) & 0xFF) ++#define netxen_get_nic_msg_errcode(msg_hdr) \ ++ ((msg_hdr >> 16) & 0xFFFF) ++ ++typedef struct { ++ union { ++ struct { ++ u64 hdr; ++ u64 body[7]; ++ }; ++ u64 words[8]; ++ }; ++} nx_fw_msg_t; + + typedef struct { + __le64 qhdr; +@@ -1200,18 +1084,24 @@ + + #define NETXEN_NIC_MSI_ENABLED 0x02 + #define NETXEN_NIC_MSIX_ENABLED 0x04 ++#define NETXEN_NIC_LRO_ENABLED 0x08 ++#define NETXEN_NIC_BRIDGE_ENABLED 0X10 + #define NETXEN_IS_MSI_FAMILY(adapter) \ + ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED)) + +-#define MSIX_ENTRIES_PER_ADAPTER 8 ++#define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS + #define NETXEN_MSIX_TBL_SPACE 8192 + #define NETXEN_PCI_REG_MSIX_TBL 0x44 + + #define NETXEN_DB_MAPSIZE_BYTES 0x1000 + +-#define NETXEN_NETDEV_WEIGHT 120 ++#define NETXEN_NETDEV_WEIGHT 128 + #define NETXEN_ADAPTER_UP_MAGIC 777 + #define NETXEN_NIC_PEG_TUNE 0 ++ ++#define __NX_FW_ATTACHED 0 ++#define __NX_DEV_UP 1 ++#define __NX_RESETTING 2 + + struct netxen_dummy_dma { + void *addr; +@@ -1223,226 +1113,164 @@ + + struct net_device *netdev; + struct pci_dev *pdev; +- int pci_using_dac; +- struct napi_struct napi; +- struct net_device_stats net_stats; +- int mtu; +- int portnum; +- u8 physical_port; +- u16 tx_context_id; +- +- uint8_t mc_enabled; +- uint8_t max_mc_count; +- nx_mac_list_t *mac_list; +- +- struct netxen_legacy_intr_set legacy_intr; +- u32 crb_intr_mask; +- +- struct work_struct watchdog_task; +- struct timer_list watchdog_timer; +- struct work_struct tx_timeout_task; ++ struct list_head mac_list; + + u32 curr_window; + u32 crb_win; + rwlock_t adapter_lock; + +- uint64_t dma_mask; ++ spinlock_t tx_clean_lock; + +- u32 cmd_producer; +- __le32 *cmd_consumer; +- u32 last_cmd_consumer; +- u32 crb_addr_cmd_producer; +- u32 crb_addr_cmd_consumer; ++ u16 num_txd; ++ u16 num_rxd; ++ u16 num_jumbo_rxd; ++ u16 num_lro_rxd; + +- u32 max_tx_desc_count; +- u32 max_rx_desc_count; +- u32 max_jumbo_rx_desc_count; +- u32 max_lro_rx_desc_count; ++ u8 max_rds_rings; ++ u8 max_sds_rings; ++ u8 driver_mismatch; ++ u8 msix_supported; ++ u8 rx_csum; ++ u8 pci_using_dac; ++ u8 portnum; ++ u8 physical_port; + +- int max_rds_rings; ++ u8 mc_enabled; ++ u8 max_mc_count; ++ u8 rss_supported; ++ u8 link_changed; ++ u8 fw_wait_cnt; ++ u8 fw_fail_cnt; ++ u8 tx_timeo_cnt; ++ u8 need_fw_reset; + ++ u8 has_link_events; ++ u8 fw_type; ++ u16 tx_context_id; ++ u16 mtu; ++ u16 is_up; ++ ++ u16 link_speed; ++ u16 link_duplex; ++ u16 link_autoneg; ++ u16 module_type; ++ ++ u32 capabilities; + u32 flags; + u32 irq; +- int driver_mismatch; + u32 temp; + +- u32 fw_major; +- +- u8 msix_supported; +- u8 max_possible_rss_rings; +- struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER]; ++ u32 int_vec_bit; ++ u32 heartbit; + + struct netxen_adapter_stats stats; + +- u16 link_speed; +- u16 link_duplex; +- u16 state; +- u16 link_autoneg; +- int rx_csum; +- int status; ++ struct netxen_recv_context recv_ctx; ++ struct nx_host_tx_ring *tx_ring; + +- struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */ +- +- /* +- * Receive instances. These can be either one per port, +- * or one per peg, etc. +- */ +- struct netxen_recv_context recv_ctx[MAX_RCV_CTX]; +- +- int is_up; +- struct netxen_dummy_dma dummy_dma; +- nx_nic_intr_coalesce_t coal; +- +- /* Context interface shared between card and host */ +- struct netxen_ring_ctx *ctx_desc; +- dma_addr_t ctx_desc_phys_addr; +- int intr_scheme; +- int msi_mode; +- int (*enable_phy_interrupts) (struct netxen_adapter *); +- int (*disable_phy_interrupts) (struct netxen_adapter *); +- int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t); ++ int (*macaddr_set) (struct netxen_adapter *, u8 *); + int (*set_mtu) (struct netxen_adapter *, int); + int (*set_promisc) (struct netxen_adapter *, u32); +- int (*phy_read) (struct netxen_adapter *, long reg, u32 *); +- int (*phy_write) (struct netxen_adapter *, long reg, u32 val); ++ void (*set_multi) (struct net_device *); ++ int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *); ++ int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val); + int (*init_port) (struct netxen_adapter *, int); + int (*stop_port) (struct netxen_adapter *); + +- int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int); +- int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int); ++ u32 (*crb_read)(struct netxen_adapter *, ulong); ++ int (*crb_write)(struct netxen_adapter *, ulong, u32); ++ + int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int); + int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int); +- int (*pci_write_immediate)(struct netxen_adapter *, u64, u32); +- u32 (*pci_read_immediate)(struct netxen_adapter *, u64); +- void (*pci_write_normalize)(struct netxen_adapter *, u64, u32); +- u32 (*pci_read_normalize)(struct netxen_adapter *, u64); ++ + unsigned long (*pci_set_window)(struct netxen_adapter *, + unsigned long long); +-}; /* netxen_adapter structure */ + +-/* +- * NetXen dma watchdog control structure +- * +- * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive +- * Bit 1 : disable_request => 1 req disable dma watchdog +- * Bit 2 : enable_request => 1 req enable dma watchdog +- * Bit 3-31 : unused +- */ ++ u32 (*io_read)(struct netxen_adapter *, void __iomem *); ++ void (*io_write)(struct netxen_adapter *, void __iomem *, u32); + +-#define netxen_set_dma_watchdog_disable_req(config_word) \ +- _netxen_set_bits(config_word, 1, 1, 1) +-#define netxen_set_dma_watchdog_enable_req(config_word) \ +- _netxen_set_bits(config_word, 2, 1, 1) +-#define netxen_get_dma_watchdog_enabled(config_word) \ +- ((config_word) & 0x1) +-#define netxen_get_dma_watchdog_disabled(config_word) \ +- (((config_word) >> 1) & 0x1) ++ void __iomem *tgt_mask_reg; ++ void __iomem *pci_int_reg; ++ void __iomem *tgt_status_reg; ++ void __iomem *crb_int_state_reg; ++ void __iomem *isr_int_vec; + +-/* Max number of xmit producer threads that can run simultaneously */ +-#define MAX_XMIT_PRODUCERS 16 ++ struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER]; + +-#define PCI_OFFSET_FIRST_RANGE(adapter, off) \ +- ((adapter)->ahw.pci_base0 + (off)) +-#define PCI_OFFSET_SECOND_RANGE(adapter, off) \ +- ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) +-#define PCI_OFFSET_THIRD_RANGE(adapter, off) \ +- ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) ++ struct netxen_dummy_dma dummy_dma; + +-static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter, +- unsigned long off) +-{ +- if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { +- return (adapter->ahw.pci_base0 + off); +- } else if ((off < SECOND_PAGE_GROUP_END) && +- (off >= SECOND_PAGE_GROUP_START)) { +- return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START); +- } else if ((off < THIRD_PAGE_GROUP_END) && +- (off >= THIRD_PAGE_GROUP_START)) { +- return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START); +- } +- return NULL; +-} ++ struct delayed_work fw_work; + +-static inline void __iomem *pci_base(struct netxen_adapter *adapter, +- unsigned long off) +-{ +- if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { +- return adapter->ahw.pci_base0; +- } else if ((off < SECOND_PAGE_GROUP_END) && +- (off >= SECOND_PAGE_GROUP_START)) { +- return adapter->ahw.pci_base1; +- } else if ((off < THIRD_PAGE_GROUP_END) && +- (off >= THIRD_PAGE_GROUP_START)) { +- return adapter->ahw.pci_base2; +- } +- return NULL; +-} ++ struct work_struct tx_timeout_task; + +-int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter); +-int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter); +-int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter); +-int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter); +-int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg, +- __u32 * readval); +-int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, +- long reg, __u32 val); ++ struct net_device_stats net_stats; ++ ++ nx_nic_intr_coalesce_t coal; ++ ++ unsigned long state; ++ u32 resv5; ++ u32 fw_version; ++ const struct firmware *fw; ++}; ++ ++int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port); ++int netxen_niu_disable_xg_port(struct netxen_adapter *adapter); ++ ++int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val); ++int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val); + + /* Functions available from netxen_nic_hw.c */ + int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu); + int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu); +-void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val); +-int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off); +-void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value); +-void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value); +-void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value); +-void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value); ++ ++int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr); ++int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr); ++ ++#define NXRD32(adapter, off) \ ++ (adapter->crb_read(adapter, off)) ++#define NXWR32(adapter, off, val) \ ++ (adapter->crb_write(adapter, off, val)) ++#define NXRDIO(adapter, addr) \ ++ (adapter->io_read(adapter, addr)) ++#define NXWRIO(adapter, addr, val) \ ++ (adapter->io_write(adapter, addr, val)) ++ ++int netxen_pcie_sem_lock(struct netxen_adapter *, int, u32); ++void netxen_pcie_sem_unlock(struct netxen_adapter *, int); ++ ++#define netxen_rom_lock(a) \ ++ netxen_pcie_sem_lock((a), 2, NETXEN_ROM_LOCK_ID) ++#define netxen_rom_unlock(a) \ ++ netxen_pcie_sem_unlock((a), 2) ++#define netxen_phy_lock(a) \ ++ netxen_pcie_sem_lock((a), 3, NETXEN_PHY_LOCK_ID) ++#define netxen_phy_unlock(a) \ ++ netxen_pcie_sem_unlock((a), 3) ++#define netxen_api_lock(a) \ ++ netxen_pcie_sem_lock((a), 5, 0) ++#define netxen_api_unlock(a) \ ++ netxen_pcie_sem_unlock((a), 5) ++#define netxen_sw_lock(a) \ ++ netxen_pcie_sem_lock((a), 6, 0) ++#define netxen_sw_unlock(a) \ ++ netxen_pcie_sem_unlock((a), 6) ++#define crb_win_lock(a) \ ++ netxen_pcie_sem_lock((a), 7, NETXEN_CRB_WIN_LOCK_ID) ++#define crb_win_unlock(a) \ ++ netxen_pcie_sem_unlock((a), 7) + + int netxen_nic_get_board_info(struct netxen_adapter *adapter); +- +-int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, +- ulong off, void *data, int len); +-int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, +- ulong off, void *data, int len); +-int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, +- u64 off, void *data, int size); +-int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, +- u64 off, void *data, int size); +-int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter, +- u64 off, u32 data); +-u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off); +-void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter, +- u64 off, u32 data); +-u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off); +-unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, +- unsigned long long addr); +-void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, +- u32 wndw); +- +-int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, +- ulong off, void *data, int len); +-int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, +- ulong off, void *data, int len); +-int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, +- u64 off, void *data, int size); +-int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, +- u64 off, void *data, int size); +-void netxen_crb_writelit_adapter(struct netxen_adapter *adapter, +- unsigned long off, int data); +-int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, +- u64 off, u32 data); +-u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off); +-void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter, +- u64 off, u32 data); +-u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off); +-unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, +- unsigned long long addr); ++int netxen_nic_wol_supported(struct netxen_adapter *adapter); + + /* Functions from netxen_nic_init.c */ +-void netxen_free_adapter_offload(struct netxen_adapter *adapter); +-int netxen_initialize_adapter_offload(struct netxen_adapter *adapter); ++int netxen_init_dummy_dma(struct netxen_adapter *adapter); ++void netxen_free_dummy_dma(struct netxen_adapter *adapter); ++ + int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val); +-int netxen_receive_peg_ready(struct netxen_adapter *adapter); + int netxen_load_firmware(struct netxen_adapter *adapter); ++int netxen_need_fw_reset(struct netxen_adapter *adapter); ++void netxen_request_firmware(struct netxen_adapter *adapter); ++void netxen_release_firmware(struct netxen_adapter *adapter); + int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose); + + int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp); +@@ -1461,34 +1289,47 @@ + int netxen_alloc_sw_resources(struct netxen_adapter *adapter); + void netxen_free_sw_resources(struct netxen_adapter *adapter); + ++void netxen_setup_hwops(struct netxen_adapter *adapter); ++void __iomem *netxen_get_ioaddr(struct netxen_adapter *, u32); ++ + int netxen_alloc_hw_resources(struct netxen_adapter *adapter); + void netxen_free_hw_resources(struct netxen_adapter *adapter); + + void netxen_release_rx_buffers(struct netxen_adapter *adapter); + void netxen_release_tx_buffers(struct netxen_adapter *adapter); + +-void netxen_initialize_adapter_ops(struct netxen_adapter *adapter); + int netxen_init_firmware(struct netxen_adapter *adapter); + void netxen_nic_clear_stats(struct netxen_adapter *adapter); + void netxen_watchdog_task(struct work_struct *work); +-void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, +- u32 ringid); ++void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid, ++ struct nx_host_rds_ring *rds_ring); + int netxen_process_cmd_ring(struct netxen_adapter *adapter); +-u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max); ++int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max); + void netxen_p2_nic_set_multi(struct net_device *netdev); + void netxen_p3_nic_set_multi(struct net_device *netdev); + void netxen_p3_free_mac_list(struct netxen_adapter *adapter); ++int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode); + int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32); + int netxen_config_intr_coalesce(struct netxen_adapter *adapter); ++int netxen_config_rss(struct netxen_adapter *adapter, int enable); ++int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd); ++int netxen_linkevent_request(struct netxen_adapter *adapter, int enable); ++void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup); + + int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu); + int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); ++int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable); ++int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable); ++int netxen_send_lro_cleanup(struct netxen_adapter *adapter); + + int netxen_nic_set_mac(struct net_device *netdev, void *p); + struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev); + + void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter, +- uint32_t crb_producer); ++ struct nx_host_tx_ring *tx_ring); ++ ++/* Functions from netxen_nic_main.c */ ++int netxen_nic_reset_context(struct netxen_adapter *); + + /* + * NetXen Board information +@@ -1496,7 +1337,7 @@ + + #define NETXEN_MAX_SHORT_NAME 32 + struct netxen_brdinfo { +- netxen_brdtype_t brdtype; /* type of board */ ++ int brdtype; /* type of board */ + long ports; /* max no of physical ports */ + char short_name[NETXEN_MAX_SHORT_NAME]; + }; +@@ -1540,68 +1381,20 @@ + name = "Unknown"; + } + +-static inline int +-dma_watchdog_shutdown_request(struct netxen_adapter *adapter) ++static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring) + { +- u32 ctrl; ++ smp_mb(); ++ return find_diff_among(tx_ring->producer, ++ tx_ring->sw_consumer, tx_ring->num_desc); + +- /* check if already inactive */ +- if (adapter->hw_read_wx(adapter, +- NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) +- printk(KERN_ERR "failed to read dma watchdog status\n"); +- +- if (netxen_get_dma_watchdog_enabled(ctrl) == 0) +- return 1; +- +- /* Send the disable request */ +- netxen_set_dma_watchdog_disable_req(ctrl); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl); +- +- return 0; + } + +-static inline int +-dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter) +-{ +- u32 ctrl; +- +- if (adapter->hw_read_wx(adapter, +- NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) +- printk(KERN_ERR "failed to read dma watchdog status\n"); +- +- return (netxen_get_dma_watchdog_enabled(ctrl) == 0); +-} +- +-static inline int +-dma_watchdog_wakeup(struct netxen_adapter *adapter) +-{ +- u32 ctrl; +- +- if (adapter->hw_read_wx(adapter, +- NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) +- printk(KERN_ERR "failed to read dma watchdog status\n"); +- +- if (netxen_get_dma_watchdog_enabled(ctrl)) +- return 1; +- +- /* send the wakeup request */ +- netxen_set_dma_watchdog_enable_req(ctrl); +- +- netxen_crb_writelit_adapter(adapter, +- NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl); +- +- return 0; +-} +- +- +-int netxen_is_flash_supported(struct netxen_adapter *adapter); + int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac); + int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac); + extern void netxen_change_ringparam(struct netxen_adapter *adapter); + extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, + int *valp); + +-extern struct ethtool_ops netxen_nic_ethtool_ops; ++extern const struct ethtool_ops netxen_nic_ethtool_ops; + + #endif /* __NETXEN_NIC_H_ */ +diff -r 6335373db0ec drivers/net/netxen/netxen_nic_ctx.c +--- a/drivers/net/netxen/netxen_nic_ctx.c Thu Oct 01 10:10:06 2009 +0100 ++++ b/drivers/net/netxen/netxen_nic_ctx.c Mon Oct 05 17:00:12 2009 +0100 +@@ -1,5 +1,6 @@ + /* +- * Copyright (C) 2003 - 2008 NetXen, Inc. ++ * Copyright (C) 2003 - 2009 NetXen, Inc. ++ * Copyright (C) 2009 - QLogic Corporation. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or +@@ -20,58 +21,12 @@ + * The full GNU General Public License is included in this distribution + * in the file called LICENSE. + * +- * Contact Information: +- * info@netxen.com +- * NetXen, +- * 3965 Freedom Circle, Fourth floor, +- * Santa Clara, CA 95054 +- * + */ + + #include "netxen_nic_hw.h" + #include "netxen_nic.h" +-#include "netxen_nic_phan_reg.h" + + #define NXHAL_VERSION 1 +- +-static int +-netxen_api_lock(struct netxen_adapter *adapter) +-{ +- u32 done = 0, timeout = 0; +- +- for (;;) { +- /* Acquire PCIE HW semaphore5 */ +- netxen_nic_read_w0(adapter, +- NETXEN_PCIE_REG(PCIE_SEM5_LOCK), &done); +- +- if (done == 1) +- break; +- +- if (++timeout >= NX_OS_CRB_RETRY_COUNT) { +- printk(KERN_ERR "%s: lock timeout.\n", __func__); +- return -1; +- } +- +- msleep(1); +- } +- +-#if 0 +- netxen_nic_write_w1(adapter, +- NETXEN_API_LOCK_ID, NX_OS_API_LOCK_DRIVER); +-#endif +- return 0; +-} +- +-static int +-netxen_api_unlock(struct netxen_adapter *adapter) +-{ +- u32 val; +- +- /* Release PCIE HW semaphore5 */ +- netxen_nic_read_w0(adapter, +- NETXEN_PCIE_REG(PCIE_SEM5_UNLOCK), &val); +- return 0; +-} + + static u32 + netxen_poll_rsp(struct netxen_adapter *adapter) +@@ -86,7 +41,7 @@ + if (++timeout > NX_OS_CRB_RETRY_COUNT) + return NX_CDRP_RSP_TIMEOUT; + +- netxen_nic_read_w1(adapter, NX_CDRP_CRB_OFFSET, &rsp); ++ rsp = NXRD32(adapter, NX_CDRP_CRB_OFFSET); + } while (!NX_CDRP_IS_RSP(rsp)); + + return rsp; +@@ -106,16 +61,15 @@ + if (netxen_api_lock(adapter)) + return NX_RCODE_TIMEOUT; + +- netxen_nic_write_w1(adapter, NX_SIGN_CRB_OFFSET, signature); ++ NXWR32(adapter, NX_SIGN_CRB_OFFSET, signature); + +- netxen_nic_write_w1(adapter, NX_ARG1_CRB_OFFSET, arg1); ++ NXWR32(adapter, NX_ARG1_CRB_OFFSET, arg1); + +- netxen_nic_write_w1(adapter, NX_ARG2_CRB_OFFSET, arg2); ++ NXWR32(adapter, NX_ARG2_CRB_OFFSET, arg2); + +- netxen_nic_write_w1(adapter, NX_ARG3_CRB_OFFSET, arg3); ++ NXWR32(adapter, NX_ARG3_CRB_OFFSET, arg3); + +- netxen_nic_write_w1(adapter, NX_CDRP_CRB_OFFSET, +- NX_CDRP_FORM_CMD(cmd)); ++ NXWR32(adapter, NX_CDRP_CRB_OFFSET, NX_CDRP_FORM_CMD(cmd)); + + rsp = netxen_poll_rsp(adapter); + +@@ -125,7 +79,7 @@ + + rcode = NX_RCODE_TIMEOUT; + } else if (rsp == NX_CDRP_RSP_FAIL) { +- netxen_nic_read_w1(adapter, NX_ARG1_CRB_OFFSET, &rcode); ++ rcode = NXRD32(adapter, NX_ARG1_CRB_OFFSET); + + printk(KERN_ERR "%s: failed card response code:0x%x\n", + netxen_nic_driver_name, rcode); +@@ -141,7 +95,7 @@ + nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu) + { + u32 rcode = NX_RCODE_SUCCESS; +- struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0]; ++ struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; + + if (recv_ctx->state == NX_HOST_CTX_STATE_ACTIVE) + rcode = netxen_issue_cmd(adapter, +@@ -169,6 +123,7 @@ + nx_cardrsp_rds_ring_t *prsp_rds; + nx_cardrsp_sds_ring_t *prsp_sds; + struct nx_host_rds_ring *rds_ring; ++ struct nx_host_sds_ring *sds_ring; + + dma_addr_t hostrq_phys_addr, cardrsp_phys_addr; + u64 phys_addr; +@@ -179,11 +134,10 @@ + + int err; + +- struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0]; ++ struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; + +- /* only one sds ring for now */ + nrds_rings = adapter->max_rds_rings; +- nsds_rings = 1; ++ nsds_rings = adapter->max_sds_rings; + + rq_size = + SIZEOF_HOSTRQ_RX(nx_hostrq_rx_ctx_t, nrds_rings, nsds_rings); +@@ -231,7 +185,7 @@ + rds_ring = &recv_ctx->rds_rings[i]; + + prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr); +- prq_rds[i].ring_size = cpu_to_le32(rds_ring->max_rx_desc_count); ++ prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc); + prq_rds[i].ring_kind = cpu_to_le32(i); + prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size); + } +@@ -239,11 +193,14 @@ + prq_sds = (nx_hostrq_sds_ring_t *)(prq->data + + le32_to_cpu(prq->sds_ring_offset)); + +- prq_sds[0].host_phys_addr = +- cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr); +- prq_sds[0].ring_size = cpu_to_le32(adapter->max_rx_desc_count); +- /* only one msix vector for now */ +- prq_sds[0].msi_index = cpu_to_le16(0); ++ for (i = 0; i < nsds_rings; i++) { ++ ++ sds_ring = &recv_ctx->sds_rings[i]; ++ ++ prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr); ++ prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc); ++ prq_sds[i].msi_index = cpu_to_le16(i); ++ } + + phys_addr = hostrq_phys_addr; + err = netxen_issue_cmd(adapter, +@@ -267,16 +224,24 @@ + rds_ring = &recv_ctx->rds_rings[i]; + + reg = le32_to_cpu(prsp_rds[i].host_producer_crb); +- rds_ring->crb_rcv_producer = NETXEN_NIC_REG(reg - 0x200); ++ rds_ring->crb_rcv_producer = netxen_get_ioaddr(adapter, ++ NETXEN_NIC_REG(reg - 0x200)); + } + + prsp_sds = ((nx_cardrsp_sds_ring_t *) + &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]); +- reg = le32_to_cpu(prsp_sds[0].host_consumer_crb); +- recv_ctx->crb_sts_consumer = NETXEN_NIC_REG(reg - 0x200); + +- reg = le32_to_cpu(prsp_sds[0].interrupt_crb); +- adapter->crb_intr_mask = NETXEN_NIC_REG(reg - 0x200); ++ for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) { ++ sds_ring = &recv_ctx->sds_rings[i]; ++ ++ reg = le32_to_cpu(prsp_sds[i].host_consumer_crb); ++ sds_ring->crb_sts_consumer = netxen_get_ioaddr(adapter, ++ NETXEN_NIC_REG(reg - 0x200)); ++ ++ reg = le32_to_cpu(prsp_sds[i].interrupt_crb); ++ sds_ring->crb_intr_mask = netxen_get_ioaddr(adapter, ++ NETXEN_NIC_REG(reg - 0x200)); ++ } + + recv_ctx->state = le32_to_cpu(prsp->host_ctx_state); + recv_ctx->context_id = le16_to_cpu(prsp->context_id); +@@ -292,7 +257,7 @@ + static void + nx_fw_cmd_destroy_rx_ctx(struct netxen_adapter *adapter) + { +- struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0]; ++ struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; + + if (netxen_issue_cmd(adapter, + adapter->ahw.pci_func, +@@ -320,6 +285,8 @@ + int err = 0; + u64 offset, phys_addr; + dma_addr_t rq_phys_addr, rsp_phys_addr; ++ struct nx_host_tx_ring *tx_ring = adapter->tx_ring; ++ struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; + + rq_size = SIZEOF_HOSTRQ_TX(nx_hostrq_tx_ctx_t); + rq_addr = pci_alloc_consistent(adapter->pdev, +@@ -354,15 +321,13 @@ + + prq->dummy_dma_addr = cpu_to_le64(adapter->dummy_dma.phys_addr); + +- offset = adapter->ctx_desc_phys_addr+sizeof(struct netxen_ring_ctx); ++ offset = recv_ctx->phys_addr + sizeof(struct netxen_ring_ctx); + prq->cmd_cons_dma_addr = cpu_to_le64(offset); + + prq_cds = &prq->cds_ring; + +- prq_cds->host_phys_addr = +- cpu_to_le64(adapter->ahw.cmd_desc_phys_addr); +- +- prq_cds->ring_size = cpu_to_le32(adapter->max_tx_desc_count); ++ prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr); ++ prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc); + + phys_addr = rq_phys_addr; + err = netxen_issue_cmd(adapter, +@@ -375,8 +340,8 @@ + + if (err == NX_RCODE_SUCCESS) { + temp = le32_to_cpu(prsp->cds_ring.host_producer_crb); +- adapter->crb_addr_cmd_producer = +- NETXEN_NIC_REG(temp - 0x200); ++ tx_ring->crb_cmd_producer = netxen_get_ioaddr(adapter, ++ NETXEN_NIC_REG(temp - 0x200)); + #if 0 + adapter->tx_state = + le32_to_cpu(prsp->host_ctx_state); +@@ -414,6 +379,44 @@ + } + } + ++int ++nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val) ++{ ++ u32 rcode; ++ ++ rcode = netxen_issue_cmd(adapter, ++ adapter->ahw.pci_func, ++ NXHAL_VERSION, ++ reg, ++ 0, ++ 0, ++ NX_CDRP_CMD_READ_PHY); ++ ++ if (rcode != NX_RCODE_SUCCESS) ++ return -EIO; ++ ++ return NXRD32(adapter, NX_ARG1_CRB_OFFSET); ++} ++ ++int ++nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val) ++{ ++ u32 rcode; ++ ++ rcode = netxen_issue_cmd(adapter, ++ adapter->ahw.pci_func, ++ NXHAL_VERSION, ++ reg, ++ val, ++ 0, ++ NX_CDRP_CMD_WRITE_PHY); ++ ++ if (rcode != NX_RCODE_SUCCESS) ++ return -EIO; ++ ++ return 0; ++} ++ + static u64 ctx_addr_sig_regs[][3] = { + {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)}, + {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)}, +@@ -440,7 +443,19 @@ + NETXEN_NIC_REG(0x120) + }, + /* crb_sts_consumer: */ +- NETXEN_NIC_REG(0x138), ++ { ++ NETXEN_NIC_REG(0x138), ++ NETXEN_NIC_REG_2(0x000), ++ NETXEN_NIC_REG_2(0x004), ++ NETXEN_NIC_REG_2(0x008), ++ }, ++ /* sw_int_mask */ ++ { ++ CRB_SW_INT_MASK_0, ++ NETXEN_NIC_REG_2(0x044), ++ NETXEN_NIC_REG_2(0x048), ++ NETXEN_NIC_REG_2(0x04c), ++ }, + }, + /* Instance 1 */ + { +@@ -453,7 +468,19 @@ + NETXEN_NIC_REG(0x164) + }, + /* crb_sts_consumer: */ +- NETXEN_NIC_REG(0x17c), ++ { ++ NETXEN_NIC_REG(0x17c), ++ NETXEN_NIC_REG_2(0x020), ++ NETXEN_NIC_REG_2(0x024), ++ NETXEN_NIC_REG_2(0x028), ++ }, ++ /* sw_int_mask */ ++ { ++ CRB_SW_INT_MASK_1, ++ NETXEN_NIC_REG_2(0x064), ++ NETXEN_NIC_REG_2(0x068), ++ NETXEN_NIC_REG_2(0x06c), ++ }, + }, + /* Instance 2 */ + { +@@ -466,7 +493,19 @@ + NETXEN_NIC_REG(0x208) + }, + /* crb_sts_consumer: */ +- NETXEN_NIC_REG(0x220), ++ { ++ NETXEN_NIC_REG(0x220), ++ NETXEN_NIC_REG_2(0x03c), ++ NETXEN_NIC_REG_2(0x03c), ++ NETXEN_NIC_REG_2(0x03c), ++ }, ++ /* sw_int_mask */ ++ { ++ CRB_SW_INT_MASK_2, ++ NETXEN_NIC_REG_2(0x03c), ++ NETXEN_NIC_REG_2(0x03c), ++ NETXEN_NIC_REG_2(0x03c), ++ }, + }, + /* Instance 3 */ + { +@@ -479,7 +518,19 @@ + NETXEN_NIC_REG(0x24c) + }, + /* crb_sts_consumer: */ +- NETXEN_NIC_REG(0x264), ++ { ++ NETXEN_NIC_REG(0x264), ++ NETXEN_NIC_REG_2(0x03c), ++ NETXEN_NIC_REG_2(0x03c), ++ NETXEN_NIC_REG_2(0x03c), ++ }, ++ /* sw_int_mask */ ++ { ++ CRB_SW_INT_MASK_3, ++ NETXEN_NIC_REG_2(0x03c), ++ NETXEN_NIC_REG_2(0x03c), ++ NETXEN_NIC_REG_2(0x03c), ++ }, + }, + }; + +@@ -488,138 +539,149 @@ + { + struct netxen_recv_context *recv_ctx; + struct nx_host_rds_ring *rds_ring; +- int ctx, ring; +- int func_id = adapter->portnum; ++ struct nx_host_sds_ring *sds_ring; ++ struct nx_host_tx_ring *tx_ring; ++ int ring; ++ int port = adapter->portnum; ++ struct netxen_ring_ctx *hwctx; ++ u32 signature; + +- adapter->ctx_desc->cmd_ring_addr = +- cpu_to_le64(adapter->ahw.cmd_desc_phys_addr); +- adapter->ctx_desc->cmd_ring_size = +- cpu_to_le32(adapter->max_tx_desc_count); ++ tx_ring = adapter->tx_ring; ++ recv_ctx = &adapter->recv_ctx; ++ hwctx = recv_ctx->hwctx; + +- for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { +- recv_ctx = &adapter->recv_ctx[ctx]; ++ hwctx->cmd_ring_addr = cpu_to_le64(tx_ring->phys_addr); ++ hwctx->cmd_ring_size = cpu_to_le32(tx_ring->num_desc); + +- for (ring = 0; ring < adapter->max_rds_rings; ring++) { +- rds_ring = &recv_ctx->rds_rings[ring]; + +- adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr = +- cpu_to_le64(rds_ring->phys_addr); +- adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size = +- cpu_to_le32(rds_ring->max_rx_desc_count); +- } +- adapter->ctx_desc->sts_ring_addr = +- cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr); +- adapter->ctx_desc->sts_ring_size = +- cpu_to_le32(adapter->max_rx_desc_count); ++ for (ring = 0; ring < adapter->max_rds_rings; ring++) { ++ rds_ring = &recv_ctx->rds_rings[ring]; ++ ++ hwctx->rcv_rings[ring].addr = ++ cpu_to_le64(rds_ring->phys_addr); ++ hwctx->rcv_rings[ring].size = ++ cpu_to_le32(rds_ring->num_desc); + } + +- adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_LO(func_id), +- lower32(adapter->ctx_desc_phys_addr)); +- adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_HI(func_id), +- upper32(adapter->ctx_desc_phys_addr)); +- adapter->pci_write_normalize(adapter, CRB_CTX_SIGNATURE_REG(func_id), +- NETXEN_CTX_SIGNATURE | func_id); ++ for (ring = 0; ring < adapter->max_sds_rings; ring++) { ++ sds_ring = &recv_ctx->sds_rings[ring]; ++ ++ if (ring == 0) { ++ hwctx->sts_ring_addr = cpu_to_le64(sds_ring->phys_addr); ++ hwctx->sts_ring_size = cpu_to_le32(sds_ring->num_desc); ++ } ++ hwctx->sts_rings[ring].addr = cpu_to_le64(sds_ring->phys_addr); ++ hwctx->sts_rings[ring].size = cpu_to_le32(sds_ring->num_desc); ++ hwctx->sts_rings[ring].msi_index = cpu_to_le16(ring); ++ } ++ hwctx->sts_ring_count = cpu_to_le32(adapter->max_sds_rings); ++ ++ signature = (adapter->max_sds_rings > 1) ? ++ NETXEN_CTX_SIGNATURE_V2 : NETXEN_CTX_SIGNATURE; ++ ++ NXWR32(adapter, CRB_CTX_ADDR_REG_LO(port), ++ lower32(recv_ctx->phys_addr)); ++ NXWR32(adapter, CRB_CTX_ADDR_REG_HI(port), ++ upper32(recv_ctx->phys_addr)); ++ NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port), ++ signature | port); + return 0; + } + +-static uint32_t sw_int_mask[4] = { +- CRB_SW_INT_MASK_0, CRB_SW_INT_MASK_1, +- CRB_SW_INT_MASK_2, CRB_SW_INT_MASK_3 +-}; +- + int netxen_alloc_hw_resources(struct netxen_adapter *adapter) + { +- struct netxen_hardware_context *hw = &adapter->ahw; +- u32 state = 0; + void *addr; + int err = 0; +- int ctx, ring; ++ int ring; + struct netxen_recv_context *recv_ctx; + struct nx_host_rds_ring *rds_ring; ++ struct nx_host_sds_ring *sds_ring; ++ struct nx_host_tx_ring *tx_ring; + +- err = netxen_receive_peg_ready(adapter); +- if (err) { +- printk(KERN_ERR "Rcv Peg initialization not complete:%x.\n", +- state); +- return err; ++ struct pci_dev *pdev = adapter->pdev; ++ struct net_device *netdev = adapter->netdev; ++ int port = adapter->portnum; ++ ++ recv_ctx = &adapter->recv_ctx; ++ tx_ring = adapter->tx_ring; ++ ++ addr = pci_alloc_consistent(pdev, ++ sizeof(struct netxen_ring_ctx) + sizeof(uint32_t), ++ &recv_ctx->phys_addr); ++ if (addr == NULL) { ++ dev_err(&pdev->dev, "failed to allocate hw context\n"); ++ return -ENOMEM; + } + +- addr = pci_alloc_consistent(adapter->pdev, +- sizeof(struct netxen_ring_ctx) + sizeof(uint32_t), +- &adapter->ctx_desc_phys_addr); +- +- if (addr == NULL) { +- DPRINTK(ERR, "failed to allocate hw context\n"); +- return -ENOMEM; +- } + memset(addr, 0, sizeof(struct netxen_ring_ctx)); +- adapter->ctx_desc = (struct netxen_ring_ctx *)addr; +- adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum); +- adapter->ctx_desc->cmd_consumer_offset = +- cpu_to_le64(adapter->ctx_desc_phys_addr + ++ recv_ctx->hwctx = (struct netxen_ring_ctx *)addr; ++ recv_ctx->hwctx->ctx_id = cpu_to_le32(port); ++ recv_ctx->hwctx->cmd_consumer_offset = ++ cpu_to_le64(recv_ctx->phys_addr + + sizeof(struct netxen_ring_ctx)); +- adapter->cmd_consumer = ++ tx_ring->hw_consumer = + (__le32 *)(((char *)addr) + sizeof(struct netxen_ring_ctx)); + + /* cmd desc ring */ +- addr = pci_alloc_consistent(adapter->pdev, +- sizeof(struct cmd_desc_type0) * +- adapter->max_tx_desc_count, +- &hw->cmd_desc_phys_addr); ++ addr = pci_alloc_consistent(pdev, TX_DESC_RINGSIZE(tx_ring), ++ &tx_ring->phys_addr); + + if (addr == NULL) { +- printk(KERN_ERR "%s failed to allocate tx desc ring\n", +- netxen_nic_driver_name); ++ dev_err(&pdev->dev, "%s: failed to allocate tx desc ring\n", ++ netdev->name); + return -ENOMEM; + } + +- hw->cmd_desc_head = (struct cmd_desc_type0 *)addr; ++ tx_ring->desc_head = (struct cmd_desc_type0 *)addr; + +- for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { +- recv_ctx = &adapter->recv_ctx[ctx]; +- +- for (ring = 0; ring < adapter->max_rds_rings; ring++) { +- /* rx desc ring */ +- rds_ring = &recv_ctx->rds_rings[ring]; +- addr = pci_alloc_consistent(adapter->pdev, +- RCV_DESC_RINGSIZE, +- &rds_ring->phys_addr); +- if (addr == NULL) { +- printk(KERN_ERR "%s failed to allocate rx " +- "desc ring[%d]\n", +- netxen_nic_driver_name, ring); +- err = -ENOMEM; +- goto err_out_free; +- } +- rds_ring->desc_head = (struct rcv_desc *)addr; +- +- if (adapter->fw_major < 4) +- rds_ring->crb_rcv_producer = +- recv_crb_registers[adapter->portnum]. +- crb_rcv_producer[ring]; +- } +- +- /* status desc ring */ ++ for (ring = 0; ring < adapter->max_rds_rings; ring++) { ++ rds_ring = &recv_ctx->rds_rings[ring]; + addr = pci_alloc_consistent(adapter->pdev, +- STATUS_DESC_RINGSIZE, +- &recv_ctx->rcv_status_desc_phys_addr); ++ RCV_DESC_RINGSIZE(rds_ring), ++ &rds_ring->phys_addr); + if (addr == NULL) { +- printk(KERN_ERR "%s failed to allocate sts desc ring\n", +- netxen_nic_driver_name); ++ dev_err(&pdev->dev, ++ "%s: failed to allocate rds ring [%d]\n", ++ netdev->name, ring); + err = -ENOMEM; + goto err_out_free; + } +- recv_ctx->rcv_status_desc_head = (struct status_desc *)addr; ++ rds_ring->desc_head = (struct rcv_desc *)addr; + +- if (adapter->fw_major < 4) +- recv_ctx->crb_sts_consumer = +- recv_crb_registers[adapter->portnum]. +- crb_sts_consumer; ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ++ rds_ring->crb_rcv_producer = ++ netxen_get_ioaddr(adapter, ++ recv_crb_registers[port].crb_rcv_producer[ring]); + } + +- if (adapter->fw_major >= 4) { +- adapter->intr_scheme = INTR_SCHEME_PERPORT; +- adapter->msi_mode = MSI_MODE_MULTIFUNC; ++ for (ring = 0; ring < adapter->max_sds_rings; ring++) { ++ sds_ring = &recv_ctx->sds_rings[ring]; ++ ++ addr = pci_alloc_consistent(adapter->pdev, ++ STATUS_DESC_RINGSIZE(sds_ring), ++ &sds_ring->phys_addr); ++ if (addr == NULL) { ++ dev_err(&pdev->dev, ++ "%s: failed to allocate sds ring [%d]\n", ++ netdev->name, ring); ++ err = -ENOMEM; ++ goto err_out_free; ++ } ++ sds_ring->desc_head = (struct status_desc *)addr; ++ ++ sds_ring->crb_sts_consumer = ++ netxen_get_ioaddr(adapter, ++ recv_crb_registers[port].crb_sts_consumer[ring]); ++ ++ sds_ring->crb_intr_mask = ++ netxen_get_ioaddr(adapter, ++ recv_crb_registers[port].sw_int_mask[ring]); ++ } ++ ++ ++ if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) { ++ if (test_and_set_bit(__NX_FW_ATTACHED, &adapter->state)) ++ goto done; + + err = nx_fw_cmd_create_rx_ctx(adapter); + if (err) +@@ -628,21 +690,12 @@ + if (err) + goto err_out_free; + } else { +- +- adapter->intr_scheme = adapter->pci_read_normalize(adapter, +- CRB_NIC_CAPABILITIES_FW); +- adapter->msi_mode = adapter->pci_read_normalize(adapter, +- CRB_NIC_MSI_MODE_FW); +- adapter->crb_intr_mask = sw_int_mask[adapter->portnum]; +- + err = netxen_init_old_ctx(adapter); +- if (err) { +- netxen_free_hw_resources(adapter); +- return err; +- } +- ++ if (err) ++ goto err_out_free; + } + ++done: + return 0; + + err_out_free: +@@ -654,51 +707,69 @@ + { + struct netxen_recv_context *recv_ctx; + struct nx_host_rds_ring *rds_ring; +- int ctx, ring; ++ struct nx_host_sds_ring *sds_ring; ++ struct nx_host_tx_ring *tx_ring; ++ int ring; + +- if (adapter->fw_major >= 4) { ++ int port = adapter->portnum; ++ ++ if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) { ++ if (!test_and_clear_bit(__NX_FW_ATTACHED, &adapter->state)) ++ goto done; ++ ++ nx_fw_cmd_destroy_rx_ctx(adapter); + nx_fw_cmd_destroy_tx_ctx(adapter); +- nx_fw_cmd_destroy_rx_ctx(adapter); ++ } else { ++ netxen_api_lock(adapter); ++ NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port), ++ NETXEN_CTX_D3_RESET | port); ++ netxen_api_unlock(adapter); + } + +- if (adapter->ctx_desc != NULL) { ++ /* Allow dma queues to drain after context reset */ ++ msleep(20); ++ ++done: ++ recv_ctx = &adapter->recv_ctx; ++ ++ if (recv_ctx->hwctx != NULL) { + pci_free_consistent(adapter->pdev, + sizeof(struct netxen_ring_ctx) + + sizeof(uint32_t), +- adapter->ctx_desc, +- adapter->ctx_desc_phys_addr); +- adapter->ctx_desc = NULL; ++ recv_ctx->hwctx, ++ recv_ctx->phys_addr); ++ recv_ctx->hwctx = NULL; + } + +- if (adapter->ahw.cmd_desc_head != NULL) { ++ tx_ring = adapter->tx_ring; ++ if (tx_ring->desc_head != NULL) { + pci_free_consistent(adapter->pdev, +- sizeof(struct cmd_desc_type0) * +- adapter->max_tx_desc_count, +- adapter->ahw.cmd_desc_head, +- adapter->ahw.cmd_desc_phys_addr); +- adapter->ahw.cmd_desc_head = NULL; ++ TX_DESC_RINGSIZE(tx_ring), ++ tx_ring->desc_head, tx_ring->phys_addr); ++ tx_ring->desc_head = NULL; + } + +- for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { +- recv_ctx = &adapter->recv_ctx[ctx]; +- for (ring = 0; ring < adapter->max_rds_rings; ring++) { +- rds_ring = &recv_ctx->rds_rings[ring]; ++ for (ring = 0; ring < adapter->max_rds_rings; ring++) { ++ rds_ring = &recv_ctx->rds_rings[ring]; + +- if (rds_ring->desc_head != NULL) { +- pci_free_consistent(adapter->pdev, +- RCV_DESC_RINGSIZE, +- rds_ring->desc_head, +- rds_ring->phys_addr); +- rds_ring->desc_head = NULL; +- } ++ if (rds_ring->desc_head != NULL) { ++ pci_free_consistent(adapter->pdev, ++ RCV_DESC_RINGSIZE(rds_ring), ++ rds_ring->desc_head, ++ rds_ring->phys_addr); ++ rds_ring->desc_head = NULL; + } ++ } + +- if (recv_ctx->rcv_status_desc_head != NULL) { ++ for (ring = 0; ring < adapter->max_sds_rings; ring++) { ++ sds_ring = &recv_ctx->sds_rings[ring]; ++ ++ if (sds_ring->desc_head != NULL) { + pci_free_consistent(adapter->pdev, +- STATUS_DESC_RINGSIZE, +- recv_ctx->rcv_status_desc_head, +- recv_ctx->rcv_status_desc_phys_addr); +- recv_ctx->rcv_status_desc_head = NULL; ++ STATUS_DESC_RINGSIZE(sds_ring), ++ sds_ring->desc_head, ++ sds_ring->phys_addr); ++ sds_ring->desc_head = NULL; + } + } + } +diff -r 6335373db0ec drivers/net/netxen/netxen_nic_ethtool.c +--- a/drivers/net/netxen/netxen_nic_ethtool.c Thu Oct 01 10:10:06 2009 +0100 ++++ b/drivers/net/netxen/netxen_nic_ethtool.c Mon Oct 05 17:00:12 2009 +0100 +@@ -1,5 +1,6 @@ + /* +- * Copyright (C) 2003 - 2006 NetXen, Inc. ++ * Copyright (C) 2003 - 2009 NetXen, Inc. ++ * Copyright (C) 2009 - QLogic Corporation. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or +@@ -20,20 +21,10 @@ + * The full GNU General Public License is included in this distribution + * in the file called LICENSE. + * +- * Contact Information: +- * info@netxen.com +- * NetXen, +- * 3965 Freedom Circle, Fourth floor, +- * Santa Clara, CA 95054 +- * +- * +- * ethtool support for netxen nic +- * + */ + + #include + #include +-#include + #include + #include + #include +@@ -41,7 +32,6 @@ + + #include "netxen_nic.h" + #include "netxen_nic_hw.h" +-#include "netxen_nic_phan_reg.h" + + struct netxen_nic_stats { + char stat_string[ETH_GSTRING_LEN]; +@@ -56,16 +46,13 @@ + #define NETXEN_NIC_INVALID_DATA 0xDEADBEEF + + static const struct netxen_nic_stats netxen_nic_gstrings_stats[] = { +- {"rcvd_bad_skb", NETXEN_NIC_STAT(stats.rcvdbadskb)}, + {"xmit_called", NETXEN_NIC_STAT(stats.xmitcalled)}, +- {"xmited_frames", NETXEN_NIC_STAT(stats.xmitedframes)}, + {"xmit_finished", NETXEN_NIC_STAT(stats.xmitfinished)}, +- {"bad_skb_len", NETXEN_NIC_STAT(stats.badskblen)}, +- {"no_cmd_desc", NETXEN_NIC_STAT(stats.nocmddescriptor)}, +- {"polled", NETXEN_NIC_STAT(stats.polled)}, ++ {"rx_dropped", NETXEN_NIC_STAT(stats.rxdropped)}, + {"tx_dropped", NETXEN_NIC_STAT(stats.txdropped)}, + {"csummed", NETXEN_NIC_STAT(stats.csummed)}, +- {"no_rcv", NETXEN_NIC_STAT(stats.no_rcv)}, ++ {"rx_pkts", NETXEN_NIC_STAT(stats.rx_pkts)}, ++ {"lro_pkts", NETXEN_NIC_STAT(stats.lro_pkts)}, + {"rx_bytes", NETXEN_NIC_STAT(stats.rxbytes)}, + {"tx_bytes", NETXEN_NIC_STAT(stats.txbytes)}, + }; +@@ -92,21 +79,17 @@ + netxen_nic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) + { + struct netxen_adapter *adapter = netdev_priv(dev); +- unsigned long flags; + u32 fw_major = 0; + u32 fw_minor = 0; + u32 fw_build = 0; + + strncpy(drvinfo->driver, netxen_nic_driver_name, 32); + strncpy(drvinfo->version, NETXEN_NIC_LINUX_VERSIONID, 32); +- write_lock_irqsave(&adapter->adapter_lock, flags); +- fw_major = adapter->pci_read_normalize(adapter, +- NETXEN_FW_VERSION_MAJOR); +- fw_minor = adapter->pci_read_normalize(adapter, +- NETXEN_FW_VERSION_MINOR); +- fw_build = adapter->pci_read_normalize(adapter, +- NETXEN_FW_VERSION_SUB); +- write_unlock_irqrestore(&adapter->adapter_lock, flags); ++ read_lock(&adapter->adapter_lock); ++ fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR); ++ fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR); ++ fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB); ++ read_unlock(&adapter->adapter_lock); + sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build); + + strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); +@@ -118,10 +101,10 @@ + netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) + { + struct netxen_adapter *adapter = netdev_priv(dev); +- struct netxen_board_info *boardinfo = &adapter->ahw.boardcfg; ++ int check_sfp_module = 0; + + /* read which mode */ +- if (adapter->ahw.board_type == NETXEN_NIC_GBE) { ++ if (adapter->ahw.port_type == NETXEN_NIC_GBE) { + ecmd->supported = (SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | +@@ -140,10 +123,10 @@ + ecmd->duplex = adapter->link_duplex; + ecmd->autoneg = adapter->link_autoneg; + +- } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) { ++ } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) { + u32 val; + +- adapter->hw_read_wx(adapter, NETXEN_PORT_MODE_ADDR, &val, 4); ++ val = NXRD32(adapter, NETXEN_PORT_MODE_ADDR); + if (val == NETXEN_PORT_MODE_802_3_AP) { + ecmd->supported = SUPPORTED_1000baseT_Full; + ecmd->advertising = ADVERTISED_1000baseT_Full; +@@ -152,13 +135,19 @@ + ecmd->advertising = ADVERTISED_10000baseT_Full; + } + ++ if (netif_running(dev) && adapter->has_link_events) { ++ ecmd->speed = adapter->link_speed; ++ ecmd->autoneg = adapter->link_autoneg; ++ ecmd->duplex = adapter->link_duplex; ++ goto skip; ++ } ++ + ecmd->port = PORT_TP; + + if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { + u16 pcifn = adapter->ahw.pci_func; + +- adapter->hw_read_wx(adapter, +- P3_LINK_SPEED_REG(pcifn), &val, 4); ++ val = NXRD32(adapter, P3_LINK_SPEED_REG(pcifn)); + ecmd->speed = P3_LINK_SPEED_MHZ * + P3_LINK_SPEED_VAL(pcifn, val); + } else +@@ -169,10 +158,11 @@ + } else + return -EIO; + ++skip: + ecmd->phy_address = adapter->physical_port; + ecmd->transceiver = XCVR_EXTERNAL; + +- switch ((netxen_brdtype_t) boardinfo->board_type) { ++ switch (adapter->ahw.board_type) { + case NETXEN_BRDTYPE_P2_SB35_4G: + case NETXEN_BRDTYPE_P2_SB31_2G: + case NETXEN_BRDTYPE_P3_REF_QG: +@@ -188,7 +178,7 @@ + ecmd->supported |= SUPPORTED_TP; + ecmd->advertising |= ADVERTISED_TP; + ecmd->port = PORT_TP; +- ecmd->autoneg = (boardinfo->board_type == ++ ecmd->autoneg = (adapter->ahw.board_type == + NETXEN_BRDTYPE_P2_SB31_10G_CX4) ? + (AUTONEG_DISABLE) : (adapter->link_autoneg); + break; +@@ -199,7 +189,7 @@ + case NETXEN_BRDTYPE_P3_HMEZ: + ecmd->supported |= SUPPORTED_MII; + ecmd->advertising |= ADVERTISED_MII; +- ecmd->port = PORT_FIBRE; ++ ecmd->port = PORT_MII; + ecmd->autoneg = AUTONEG_DISABLE; + break; + case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: +@@ -207,6 +197,8 @@ + case NETXEN_BRDTYPE_P3_10G_SFP_QT: + ecmd->advertising |= ADVERTISED_TP; + ecmd->supported |= SUPPORTED_TP; ++ check_sfp_module = netif_running(dev) && ++ adapter->has_link_events; + case NETXEN_BRDTYPE_P2_SB31_10G: + case NETXEN_BRDTYPE_P3_10G_XFP: + ecmd->supported |= SUPPORTED_FIBRE; +@@ -215,12 +207,14 @@ + ecmd->autoneg = AUTONEG_DISABLE; + break; + case NETXEN_BRDTYPE_P3_10G_TP: +- if (adapter->ahw.board_type == NETXEN_NIC_XGBE) { ++ if (adapter->ahw.port_type == NETXEN_NIC_XGBE) { + ecmd->autoneg = AUTONEG_DISABLE; + ecmd->supported |= (SUPPORTED_FIBRE | SUPPORTED_TP); + ecmd->advertising |= + (ADVERTISED_FIBRE | ADVERTISED_TP); + ecmd->port = PORT_FIBRE; ++ check_sfp_module = netif_running(dev) && ++ adapter->has_link_events; + } else { + ecmd->autoneg = AUTONEG_ENABLE; + ecmd->supported |= (SUPPORTED_TP |SUPPORTED_Autoneg); +@@ -231,8 +225,26 @@ + break; + default: + printk(KERN_ERR "netxen-nic: Unsupported board model %d\n", +- (netxen_brdtype_t) boardinfo->board_type); ++ adapter->ahw.board_type); + return -EIO; ++ } ++ ++ if (check_sfp_module) { ++ switch (adapter->module_type) { ++ case LINKEVENT_MODULE_OPTICAL_UNKNOWN: ++ case LINKEVENT_MODULE_OPTICAL_SRLR: ++ case LINKEVENT_MODULE_OPTICAL_LRM: ++ case LINKEVENT_MODULE_OPTICAL_SFP_1G: ++ ecmd->port = PORT_FIBRE; ++ break; ++ case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE: ++ case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN: ++ case LINKEVENT_MODULE_TWINAX: ++ ecmd->port = PORT_TP; ++ break; ++ default: ++ ecmd->port = -1; ++ } + } + + return 0; +@@ -245,7 +257,7 @@ + __u32 status; + + /* read which mode */ +- if (adapter->ahw.board_type == NETXEN_NIC_GBE) { ++ if (adapter->ahw.port_type == NETXEN_NIC_GBE) { + /* autonegotiation */ + if (adapter->phy_write + && adapter->phy_write(adapter, +@@ -402,12 +414,11 @@ + regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) | + (adapter->pdev)->device; + /* which mode */ +- adapter->hw_read_wx(adapter, NETXEN_NIU_MODE, ®s_buff[0], 4); ++ regs_buff[0] = NXRD32(adapter, NETXEN_NIU_MODE); + mode = regs_buff[0]; + + /* Common registers to all the modes */ +- adapter->hw_read_wx(adapter, +- NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER, ®s_buff[2], 4); ++ regs_buff[2] = NXRD32(adapter, NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER); + /* GB/XGB Mode */ + mode = (mode / 2) - 1; + window = 0; +@@ -418,9 +429,8 @@ + window = adapter->physical_port * + NETXEN_NIC_PORT_WINDOW; + +- adapter->hw_read_wx(adapter, +- niu_registers[mode].reg[i - 3] + window, +- ®s_buff[i], 4); ++ regs_buff[i] = NXRD32(adapter, ++ niu_registers[mode].reg[i - 3] + window); + } + + } +@@ -433,7 +443,7 @@ + int val; + + /* read which mode */ +- if (adapter->ahw.board_type == NETXEN_NIC_GBE) { ++ if (adapter->ahw.port_type == NETXEN_NIC_GBE) { + if (adapter->phy_read + && adapter->phy_read(adapter, + NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, +@@ -443,8 +453,8 @@ + val = netxen_get_phy_link(status); + return !val; + } +- } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) { +- val = adapter->pci_read_normalize(adapter, CRB_XG_STATE); ++ } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) { ++ val = NXRD32(adapter, CRB_XG_STATE); + return (val == XG_LINK_UP) ? 0 : 1; + } + return -EIO; +@@ -473,102 +483,85 @@ + return 0; + } + +-#if 0 +-static int +-netxen_nic_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, +- u8 * bytes) ++static void ++netxen_nic_get_ringparam(struct net_device *dev, ++ struct ethtool_ringparam *ring) + { + struct netxen_adapter *adapter = netdev_priv(dev); +- int offset = eeprom->offset; +- static int flash_start; +- static int ready_to_flash; +- int ret; + +- if (flash_start == 0) { +- netxen_halt_pegs(adapter); +- ret = netxen_flash_unlock(adapter); +- if (ret < 0) { +- printk(KERN_ERR "%s: Flash unlock failed.\n", +- netxen_nic_driver_name); +- return ret; +- } +- printk(KERN_INFO "%s: flash unlocked. \n", +- netxen_nic_driver_name); +- ret = netxen_flash_erase_secondary(adapter); +- if (ret != FLASH_SUCCESS) { +- printk(KERN_ERR "%s: Flash erase failed.\n", +- netxen_nic_driver_name); +- return ret; +- } +- printk(KERN_INFO "%s: secondary flash erased successfully.\n", +- netxen_nic_driver_name); +- flash_start = 1; +- return 0; ++ ring->rx_pending = adapter->num_rxd; ++ ring->rx_jumbo_pending = adapter->num_jumbo_rxd; ++ ring->rx_jumbo_pending += adapter->num_lro_rxd; ++ ring->tx_pending = adapter->num_txd; ++ ++ if (adapter->ahw.port_type == NETXEN_NIC_GBE) { ++ ring->rx_max_pending = MAX_RCV_DESCRIPTORS_1G; ++ ring->rx_jumbo_max_pending = MAX_JUMBO_RCV_DESCRIPTORS_1G; ++ } else { ++ ring->rx_max_pending = MAX_RCV_DESCRIPTORS_10G; ++ ring->rx_jumbo_max_pending = MAX_JUMBO_RCV_DESCRIPTORS_10G; + } + +- if (offset == NETXEN_BOOTLD_START) { +- ret = netxen_flash_erase_primary(adapter); +- if (ret != FLASH_SUCCESS) { +- printk(KERN_ERR "%s: Flash erase failed.\n", +- netxen_nic_driver_name); +- return ret; +- } ++ ring->tx_max_pending = MAX_CMD_DESCRIPTORS; + +- ret = netxen_rom_se(adapter, NETXEN_USER_START); +- if (ret != FLASH_SUCCESS) +- return ret; +- ret = netxen_rom_se(adapter, NETXEN_FIXED_START); +- if (ret != FLASH_SUCCESS) +- return ret; ++ ring->rx_mini_max_pending = 0; ++ ring->rx_mini_pending = 0; ++} + +- printk(KERN_INFO "%s: primary flash erased successfully\n", +- netxen_nic_driver_name); ++static u32 ++netxen_validate_ringparam(u32 val, u32 min, u32 max, char *r_name) ++{ ++ u32 num_desc; ++ num_desc = max(val, min); ++ num_desc = min(num_desc, max); ++ num_desc = roundup_pow_of_two(num_desc); + +- ret = netxen_backup_crbinit(adapter); +- if (ret != FLASH_SUCCESS) { +- printk(KERN_ERR "%s: CRBinit backup failed.\n", +- netxen_nic_driver_name); +- return ret; +- } +- printk(KERN_INFO "%s: CRBinit backup done.\n", +- netxen_nic_driver_name); +- ready_to_flash = 1; ++ if (val != num_desc) { ++ printk(KERN_INFO "%s: setting %s ring size %d instead of %d\n", ++ netxen_nic_driver_name, r_name, num_desc, val); + } + +- if (!ready_to_flash) { +- printk(KERN_ERR "%s: Invalid write sequence, returning...\n", +- netxen_nic_driver_name); +- return -EINVAL; ++ return num_desc; ++} ++ ++static int ++netxen_nic_set_ringparam(struct net_device *dev, ++ struct ethtool_ringparam *ring) ++{ ++ struct netxen_adapter *adapter = netdev_priv(dev); ++ u16 max_rcv_desc = MAX_RCV_DESCRIPTORS_10G; ++ u16 max_jumbo_desc = MAX_JUMBO_RCV_DESCRIPTORS_10G; ++ u16 num_rxd, num_jumbo_rxd, num_txd; ++ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ++ return -EOPNOTSUPP; ++ ++ if (ring->rx_mini_pending) ++ return -EOPNOTSUPP; ++ ++ if (adapter->ahw.port_type == NETXEN_NIC_GBE) { ++ max_rcv_desc = MAX_RCV_DESCRIPTORS_1G; ++ max_jumbo_desc = MAX_JUMBO_RCV_DESCRIPTORS_10G; + } + +- return netxen_rom_fast_write_words(adapter, offset, bytes, eeprom->len); +-} +-#endif /* 0 */ ++ num_rxd = netxen_validate_ringparam(ring->rx_pending, ++ MIN_RCV_DESCRIPTORS, max_rcv_desc, "rx"); + +-static void +-netxen_nic_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ring) +-{ +- struct netxen_adapter *adapter = netdev_priv(dev); +- int i; ++ num_jumbo_rxd = netxen_validate_ringparam(ring->rx_jumbo_pending, ++ MIN_JUMBO_DESCRIPTORS, max_jumbo_desc, "rx jumbo"); + +- ring->rx_pending = 0; +- ring->rx_jumbo_pending = 0; +- for (i = 0; i < MAX_RCV_CTX; ++i) { +- ring->rx_pending += adapter->recv_ctx[i]. +- rds_rings[RCV_DESC_NORMAL_CTXID].max_rx_desc_count; +- ring->rx_jumbo_pending += adapter->recv_ctx[i]. +- rds_rings[RCV_DESC_JUMBO_CTXID].max_rx_desc_count; +- } +- ring->tx_pending = adapter->max_tx_desc_count; ++ num_txd = netxen_validate_ringparam(ring->tx_pending, ++ MIN_CMD_DESCRIPTORS, MAX_CMD_DESCRIPTORS, "tx"); + +- if (adapter->ahw.board_type == NETXEN_NIC_GBE) +- ring->rx_max_pending = MAX_RCV_DESCRIPTORS_1G; +- else +- ring->rx_max_pending = MAX_RCV_DESCRIPTORS_10G; +- ring->tx_max_pending = MAX_CMD_DESCRIPTORS_HOST; +- ring->rx_jumbo_max_pending = MAX_JUMBO_RCV_DESCRIPTORS; +- ring->rx_mini_max_pending = 0; +- ring->rx_mini_pending = 0; ++ if (num_rxd == adapter->num_rxd && num_txd == adapter->num_txd && ++ num_jumbo_rxd == adapter->num_jumbo_rxd) ++ return 0; ++ ++ adapter->num_rxd = num_rxd; ++ adapter->num_jumbo_rxd = num_jumbo_rxd; ++ adapter->num_txd = num_txd; ++ ++ return netxen_nic_reset_context(adapter); + } + + static void +@@ -579,14 +572,13 @@ + __u32 val; + int port = adapter->physical_port; + +- if (adapter->ahw.board_type == NETXEN_NIC_GBE) { ++ if (adapter->ahw.port_type == NETXEN_NIC_GBE) { + if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS)) + return; + /* get flow control settings */ +- netxen_nic_read_w0(adapter,NETXEN_NIU_GB_MAC_CONFIG_0(port), +- &val); ++ val = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port)); + pause->rx_pause = netxen_gb_get_rx_flowctl(val); +- netxen_nic_read_w0(adapter, NETXEN_NIU_GB_PAUSE_CTL, &val); ++ val = NXRD32(adapter, NETXEN_NIU_GB_PAUSE_CTL); + switch (port) { + case 0: + pause->tx_pause = !(netxen_gb_get_gb0_mask(val)); +@@ -602,18 +594,18 @@ + pause->tx_pause = !(netxen_gb_get_gb3_mask(val)); + break; + } +- } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) { ++ } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) { + if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS)) + return; + pause->rx_pause = 1; +- netxen_nic_read_w0(adapter, NETXEN_NIU_XG_PAUSE_CTL, &val); ++ val = NXRD32(adapter, NETXEN_NIU_XG_PAUSE_CTL); + if (port == 0) + pause->tx_pause = !(netxen_xg_get_xg0_mask(val)); + else + pause->tx_pause = !(netxen_xg_get_xg1_mask(val)); + } else { + printk(KERN_ERR"%s: Unknown board type: %x\n", +- netxen_nic_driver_name, adapter->ahw.board_type); ++ netxen_nic_driver_name, adapter->ahw.port_type); + } + } + +@@ -625,22 +617,21 @@ + __u32 val; + int port = adapter->physical_port; + /* read mode */ +- if (adapter->ahw.board_type == NETXEN_NIC_GBE) { ++ if (adapter->ahw.port_type == NETXEN_NIC_GBE) { + if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS)) + return -EIO; + /* set flow control */ +- netxen_nic_read_w0(adapter, +- NETXEN_NIU_GB_MAC_CONFIG_0(port), &val); ++ val = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port)); + + if (pause->rx_pause) + netxen_gb_rx_flowctl(val); + else + netxen_gb_unset_rx_flowctl(val); + +- netxen_nic_write_w0(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), ++ NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), + val); + /* set autoneg */ +- netxen_nic_read_w0(adapter, NETXEN_NIU_GB_PAUSE_CTL, &val); ++ val = NXRD32(adapter, NETXEN_NIU_GB_PAUSE_CTL); + switch (port) { + case 0: + if (pause->tx_pause) +@@ -668,11 +659,11 @@ + netxen_gb_set_gb3_mask(val); + break; + } +- netxen_nic_write_w0(adapter, NETXEN_NIU_GB_PAUSE_CTL, val); +- } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) { ++ NXWR32(adapter, NETXEN_NIU_GB_PAUSE_CTL, val); ++ } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) { + if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS)) + return -EIO; +- netxen_nic_read_w0(adapter, NETXEN_NIU_XG_PAUSE_CTL, &val); ++ val = NXRD32(adapter, NETXEN_NIU_XG_PAUSE_CTL); + if (port == 0) { + if (pause->tx_pause) + netxen_xg_unset_xg0_mask(val); +@@ -684,11 +675,11 @@ + else + netxen_xg_set_xg1_mask(val); + } +- netxen_nic_write_w0(adapter, NETXEN_NIU_XG_PAUSE_CTL, val); ++ NXWR32(adapter, NETXEN_NIU_XG_PAUSE_CTL, val); + } else { + printk(KERN_ERR "%s: Unknown board type: %x\n", + netxen_nic_driver_name, +- adapter->ahw.board_type); ++ adapter->ahw.port_type); + } + return 0; + } +@@ -698,14 +689,14 @@ + struct netxen_adapter *adapter = netdev_priv(dev); + u32 data_read, data_written; + +- netxen_nic_read_w0(adapter, NETXEN_PCIX_PH_REG(0), &data_read); ++ data_read = NXRD32(adapter, NETXEN_PCIX_PH_REG(0)); + if ((data_read & 0xffff) != PHAN_VENDOR_ID) + return 1; + + data_written = (u32)0xa5a5a5a5; + +- netxen_nic_reg_write(adapter, CRB_SCRATCHPAD_TEST, data_written); +- data_read = adapter->pci_read_normalize(adapter, CRB_SCRATCHPAD_TEST); ++ NXWR32(adapter, CRB_SCRATCHPAD_TEST, data_written); ++ data_read = NXRD32(adapter, CRB_SCRATCHPAD_TEST); + if (data_written != data_read) + return 1; + +@@ -810,6 +801,53 @@ + return 0; + } + ++static void ++netxen_nic_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) ++{ ++ struct netxen_adapter *adapter = netdev_priv(dev); ++ u32 wol_cfg = 0; ++ ++ wol->supported = 0; ++ wol->wolopts = 0; ++ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ++ return; ++ ++ wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV); ++ if (wol_cfg & (1UL << adapter->portnum)) ++ wol->supported |= WAKE_MAGIC; ++ ++ wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG); ++ if (wol_cfg & (1UL << adapter->portnum)) ++ wol->wolopts |= WAKE_MAGIC; ++} ++ ++static int ++netxen_nic_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) ++{ ++ struct netxen_adapter *adapter = netdev_priv(dev); ++ u32 wol_cfg = 0; ++ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ++ return -EOPNOTSUPP; ++ ++ if (wol->wolopts & ~WAKE_MAGIC) ++ return -EOPNOTSUPP; ++ ++ wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV); ++ if (!(wol_cfg & (1 << adapter->portnum))) ++ return -EOPNOTSUPP; ++ ++ wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG); ++ if (wol->wolopts & WAKE_MAGIC) ++ wol_cfg |= 1UL << adapter->portnum; ++ else ++ wol_cfg &= ~(1UL << adapter->portnum); ++ NXWR32(adapter, NETXEN_WOL_CONFIG, wol_cfg); ++ ++ return 0; ++} ++ + /* + * Set the coalescing parameters. Currently only normal is supported. + * If rx_coalesce_usecs == 0 or rx_max_coalesced_frames == 0 then set the +@@ -897,7 +935,29 @@ + return 0; + } + +-struct ethtool_ops netxen_nic_ethtool_ops = { ++static int netxen_nic_set_flags(struct net_device *netdev, u32 data) ++{ ++ struct netxen_adapter *adapter = netdev_priv(netdev); ++ int hw_lro; ++ ++ if (!(adapter->capabilities & NX_FW_CAPABILITY_HW_LRO)) ++ return -EINVAL; ++ ++ ethtool_op_set_flags(netdev, data); ++ ++ hw_lro = (data & ETH_FLAG_LRO) ? NETXEN_NIC_LRO_ENABLED : 0; ++ ++ if (netxen_config_hw_lro(adapter, hw_lro)) ++ return -EIO; ++ ++ if ((hw_lro == 0) && netxen_send_lro_cleanup(adapter)) ++ return -EIO; ++ ++ ++ return 0; ++} ++ ++const struct ethtool_ops netxen_nic_ethtool_ops = { + .get_settings = netxen_nic_get_settings, + .set_settings = netxen_nic_set_settings, + .get_drvinfo = netxen_nic_get_drvinfo, +@@ -906,16 +966,16 @@ + .get_link = ethtool_op_get_link, + .get_eeprom_len = netxen_nic_get_eeprom_len, + .get_eeprom = netxen_nic_get_eeprom, +-#if 0 +- .set_eeprom = netxen_nic_set_eeprom, +-#endif + .get_ringparam = netxen_nic_get_ringparam, ++ .set_ringparam = netxen_nic_set_ringparam, + .get_pauseparam = netxen_nic_get_pauseparam, + .set_pauseparam = netxen_nic_set_pauseparam, + .set_tx_csum = ethtool_op_set_tx_csum, + .set_sg = ethtool_op_set_sg, + .get_tso = netxen_nic_get_tso, + .set_tso = netxen_nic_set_tso, ++ .get_wol = netxen_nic_get_wol, ++ .set_wol = netxen_nic_set_wol, + .self_test = netxen_nic_diag_test, + .get_strings = netxen_nic_get_strings, + .get_ethtool_stats = netxen_nic_get_ethtool_stats, +@@ -924,4 +984,6 @@ + .set_rx_csum = netxen_nic_set_rx_csum, + .get_coalesce = netxen_get_intr_coalesce, + .set_coalesce = netxen_set_intr_coalesce, ++ .get_flags = ethtool_op_get_flags, ++ .set_flags = netxen_nic_set_flags, + }; +diff -r 6335373db0ec drivers/net/netxen/netxen_nic_hdr.h +--- a/drivers/net/netxen/netxen_nic_hdr.h Thu Oct 01 10:10:06 2009 +0100 ++++ b/drivers/net/netxen/netxen_nic_hdr.h Mon Oct 05 17:00:12 2009 +0100 +@@ -1,5 +1,6 @@ + /* +- * Copyright (C) 2003 - 2006 NetXen, Inc. ++ * Copyright (C) 2003 - 2009 NetXen, Inc. ++ * Copyright (C) 2009 - QLogic Corporation. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or +@@ -20,26 +21,13 @@ + * The full GNU General Public License is included in this distribution + * in the file called LICENSE. + * +- * Contact Information: +- * info@netxen.com +- * NetXen, +- * 3965 Freedom Circle, Fourth floor, +- * Santa Clara, CA 95054 + */ + + #ifndef __NETXEN_NIC_HDR_H_ + #define __NETXEN_NIC_HDR_H_ + +-#include + #include +-#include +-#include +-#include +-#include +-#include + #include +-#include +-#include /* for memset */ + + /* + * The basic unit of access when reading/writing control registers. +@@ -362,12 +350,7 @@ + #define NETXEN_HW_CRB_HUB_AGT_ADR_LPC \ + ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_LPC_CRB_AGT_ADR) + +-/* +- * MAX_RCV_CTX : The number of receive contexts that are available on +- * the phantom. +- */ +-#define MAX_RCV_CTX 1 +- ++#define NETXEN_SRE_MISC (NETXEN_CRB_SRE + 0x0002c) + #define NETXEN_SRE_INT_STATUS (NETXEN_CRB_SRE + 0x00034) + #define NETXEN_SRE_PBI_ACTIVE_STATUS (NETXEN_CRB_SRE + 0x01014) + #define NETXEN_SRE_L1RE_CTL (NETXEN_CRB_SRE + 0x03000) +@@ -445,6 +428,7 @@ + #define NETXEN_CRB_PEG_NET_1 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN1) + #define NETXEN_CRB_PEG_NET_2 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN2) + #define NETXEN_CRB_PEG_NET_3 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN3) ++#define NETXEN_CRB_PEG_NET_4 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SQS2) + #define NETXEN_CRB_PEG_NET_D NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGND) + #define NETXEN_CRB_PEG_NET_I NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGNI) + #define NETXEN_CRB_DDR_NET NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_MN) +@@ -735,9 +719,92 @@ + #define NETXEN_FW_VERSION_MINOR (NETXEN_CAM_RAM(0x154)) + #define NETXEN_FW_VERSION_SUB (NETXEN_CAM_RAM(0x158)) + #define NETXEN_ROM_LOCK_ID (NETXEN_CAM_RAM(0x100)) ++#define NETXEN_PHY_LOCK_ID (NETXEN_CAM_RAM(0x120)) + #define NETXEN_CRB_WIN_LOCK_ID (NETXEN_CAM_RAM(0x124)) + +-#define NETXEN_PHY_LOCK_ID (NETXEN_CAM_RAM(0x120)) ++#define NIC_CRB_BASE (NETXEN_CAM_RAM(0x200)) ++#define NIC_CRB_BASE_2 (NETXEN_CAM_RAM(0x700)) ++#define NETXEN_NIC_REG(X) (NIC_CRB_BASE+(X)) ++#define NETXEN_NIC_REG_2(X) (NIC_CRB_BASE_2+(X)) ++ ++#define NX_CDRP_CRB_OFFSET (NETXEN_NIC_REG(0x18)) ++#define NX_ARG1_CRB_OFFSET (NETXEN_NIC_REG(0x1c)) ++#define NX_ARG2_CRB_OFFSET (NETXEN_NIC_REG(0x20)) ++#define NX_ARG3_CRB_OFFSET (NETXEN_NIC_REG(0x24)) ++#define NX_SIGN_CRB_OFFSET (NETXEN_NIC_REG(0x28)) ++ ++#define CRB_HOST_DUMMY_BUF_ADDR_HI (NETXEN_NIC_REG(0x3c)) ++#define CRB_HOST_DUMMY_BUF_ADDR_LO (NETXEN_NIC_REG(0x40)) ++ ++#define CRB_CMDPEG_STATE (NETXEN_NIC_REG(0x50)) ++#define CRB_RCVPEG_STATE (NETXEN_NIC_REG(0x13c)) ++ ++#define CRB_XG_STATE (NETXEN_NIC_REG(0x94)) ++#define CRB_XG_STATE_P3 (NETXEN_NIC_REG(0x98)) ++#define CRB_PF_LINK_SPEED_1 (NETXEN_NIC_REG(0xe8)) ++#define CRB_PF_LINK_SPEED_2 (NETXEN_NIC_REG(0xec)) ++ ++#define CRB_MPORT_MODE (NETXEN_NIC_REG(0xc4)) ++#define CRB_DMA_SHIFT (NETXEN_NIC_REG(0xcc)) ++#define CRB_INT_VECTOR (NETXEN_NIC_REG(0xd4)) ++ ++#define CRB_CMD_PRODUCER_OFFSET (NETXEN_NIC_REG(0x08)) ++#define CRB_CMD_CONSUMER_OFFSET (NETXEN_NIC_REG(0x0c)) ++#define CRB_CMD_PRODUCER_OFFSET_1 (NETXEN_NIC_REG(0x1ac)) ++#define CRB_CMD_CONSUMER_OFFSET_1 (NETXEN_NIC_REG(0x1b0)) ++#define CRB_CMD_PRODUCER_OFFSET_2 (NETXEN_NIC_REG(0x1b8)) ++#define CRB_CMD_CONSUMER_OFFSET_2 (NETXEN_NIC_REG(0x1bc)) ++#define CRB_CMD_PRODUCER_OFFSET_3 (NETXEN_NIC_REG(0x1d0)) ++#define CRB_CMD_CONSUMER_OFFSET_3 (NETXEN_NIC_REG(0x1d4)) ++#define CRB_TEMP_STATE (NETXEN_NIC_REG(0x1b4)) ++ ++#define CRB_V2P_0 (NETXEN_NIC_REG(0x290)) ++#define CRB_V2P(port) (CRB_V2P_0+((port)*4)) ++#define CRB_DRIVER_VERSION (NETXEN_NIC_REG(0x2a0)) ++ ++#define CRB_SW_INT_MASK_0 (NETXEN_NIC_REG(0x1d8)) ++#define CRB_SW_INT_MASK_1 (NETXEN_NIC_REG(0x1e0)) ++#define CRB_SW_INT_MASK_2 (NETXEN_NIC_REG(0x1e4)) ++#define CRB_SW_INT_MASK_3 (NETXEN_NIC_REG(0x1e8)) ++ ++#define CRB_FW_CAPABILITIES_1 (NETXEN_CAM_RAM(0x128)) ++#define CRB_MAC_BLOCK_START (NETXEN_CAM_RAM(0x1c0)) ++ ++/* ++ * capabilities register, can be used to selectively enable/disable features ++ * for backward compability ++ */ ++#define CRB_NIC_CAPABILITIES_HOST NETXEN_NIC_REG(0x1a8) ++#define CRB_NIC_CAPABILITIES_FW NETXEN_NIC_REG(0x1dc) ++#define CRB_NIC_MSI_MODE_HOST NETXEN_NIC_REG(0x270) ++#define CRB_NIC_MSI_MODE_FW NETXEN_NIC_REG(0x274) ++ ++#define INTR_SCHEME_PERPORT 0x1 ++#define MSI_MODE_MULTIFUNC 0x1 ++ ++/* used for ethtool tests */ ++#define CRB_SCRATCHPAD_TEST NETXEN_NIC_REG(0x280) ++ ++/* ++ * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address ++ * which can be read by the Phantom host to get producer/consumer indexes from ++ * Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following ++ * registers will be used for the addresses of the ring's shared memory ++ * on the Phantom. ++ */ ++ ++#define nx_get_temp_val(x) ((x) >> 16) ++#define nx_get_temp_state(x) ((x) & 0xffff) ++#define nx_encode_temp(val, state) (((val) << 16) | (state)) ++ ++/* ++ * Temperature control. ++ */ ++enum { ++ NX_TEMP_NORMAL = 0x1, /* Normal operating range */ ++ NX_TEMP_WARN, /* Sound alert, temperature getting high */ ++ NX_TEMP_PANIC /* Fatal error, hardware has shut down. */ ++}; + + /* Lock IDs for PHY lock */ + #define PHY_LOCK_DRIVER 0x44524956 +@@ -828,16 +895,24 @@ + + #define PCIE_DCR 0x00d8 + ++#define PCIE_SEM0_LOCK (0x1c000) ++#define PCIE_SEM0_UNLOCK (0x1c004) ++#define PCIE_SEM1_LOCK (0x1c008) ++#define PCIE_SEM1_UNLOCK (0x1c00c) + #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */ + #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */ + #define PCIE_SEM3_LOCK (0x1c018) /* Phy lock */ + #define PCIE_SEM3_UNLOCK (0x1c01c) /* Phy unlock */ ++#define PCIE_SEM4_LOCK (0x1c020) ++#define PCIE_SEM4_UNLOCK (0x1c024) + #define PCIE_SEM5_LOCK (0x1c028) /* API lock */ + #define PCIE_SEM5_UNLOCK (0x1c02c) /* API unlock */ + #define PCIE_SEM6_LOCK (0x1c030) /* sw lock */ + #define PCIE_SEM6_UNLOCK (0x1c034) /* sw unlock */ + #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */ + #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/ ++#define PCIE_SEM_LOCK(N) (PCIE_SEM0_LOCK + 8*(N)) ++#define PCIE_SEM_UNLOCK(N) (PCIE_SEM0_UNLOCK + 8*(N)) + + #define PCIE_SETUP_FUNCTION (0x12040) + #define PCIE_SETUP_FUNCTION2 (0x12048) +@@ -858,7 +933,36 @@ + #define NETXEN_PORT_MODE_ADDR (NETXEN_CAM_RAM(0x24)) + #define NETXEN_WOL_PORT_MODE (NETXEN_CAM_RAM(0x198)) + +-#define NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL (0x14) ++#define NETXEN_WOL_CONFIG_NV (NETXEN_CAM_RAM(0x184)) ++#define NETXEN_WOL_CONFIG (NETXEN_CAM_RAM(0x188)) ++ ++#define NX_PEG_TUNE_MN_PRESENT 0x1 ++#define NX_PEG_TUNE_CAPABILITY (NETXEN_CAM_RAM(0x02c)) ++ ++#define NETXEN_DMA_WATCHDOG_CTRL (NETXEN_CAM_RAM(0x14)) ++#define NETXEN_PEG_ALIVE_COUNTER (NETXEN_CAM_RAM(0xb0)) ++#define NETXEN_PEG_HALT_STATUS1 (NETXEN_CAM_RAM(0xa8)) ++#define NETXEN_PEG_HALT_STATUS2 (NETXEN_CAM_RAM(0xac)) ++#define NX_CRB_DEV_REF_COUNT (NETXEN_CAM_RAM(0x138)) ++#define NX_CRB_DEV_STATE (NETXEN_CAM_RAM(0x140)) ++ ++/* Device State */ ++#define NX_DEV_COLD 1 ++#define NX_DEV_INITALIZING 2 ++#define NX_DEV_READY 3 ++#define NX_DEV_NEED_RESET 4 ++#define NX_DEV_NEED_QUISCENT 5 ++#define NX_DEV_FAILED 6 ++ ++#define NX_RCODE_DRIVER_INFO 0x20000000 ++#define NX_RCODE_DRIVER_CAN_RELOAD 0x40000000 ++#define NX_RCODE_FATAL_ERROR 0x80000000 ++#define NX_FWERROR_PEGNUM(code) ((code) & 0xff) ++#define NX_FWERROR_CODE(code) ((code >> 8) & 0xfffff) ++ ++#define FW_POLL_DELAY (2 * HZ) ++#define FW_FAIL_THRESH 3 ++#define FW_POLL_THRESH 10 + + #define ISR_MSI_INT_TRIGGER(FUNC) (NETXEN_PCIX_PS_REG(PCIX_MSI_F(FUNC))) + #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) +diff -r 6335373db0ec drivers/net/netxen/netxen_nic_hw.c +--- a/drivers/net/netxen/netxen_nic_hw.c Thu Oct 01 10:10:06 2009 +0100 ++++ b/drivers/net/netxen/netxen_nic_hw.c Mon Oct 05 17:00:12 2009 +0100 +@@ -1,5 +1,6 @@ + /* +- * Copyright (C) 2003 - 2006 NetXen, Inc. ++ * Copyright (C) 2003 - 2009 NetXen, Inc. ++ * Copyright (C) 2009 - QLogic Corporation. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or +@@ -20,21 +21,10 @@ + * The full GNU General Public License is included in this distribution + * in the file called LICENSE. + * +- * Contact Information: +- * info@netxen.com +- * NetXen, +- * 3965 Freedom Circle, Fourth floor, +- * Santa Clara, CA 95054 +- * +- * +- * Source file for NIC routines to access the Phantom hardware +- * + */ + + #include "netxen_nic.h" + #include "netxen_nic_hw.h" +-#include "netxen_nic_phan_reg.h" +- + + #include + +@@ -51,8 +41,48 @@ + #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000)) + #define CRB_INDIRECT_2M (0x1e0000UL) + +-#define CRB_WIN_LOCK_TIMEOUT 100000000 +-static crb_128M_2M_block_map_t crb_128M_2M_map[64] = { ++#ifndef readq ++static inline u64 readq(void __iomem *addr) ++{ ++ return readl(addr) | (((u64) readl(addr + 4)) << 32LL); ++} ++#endif ++ ++#ifndef writeq ++static inline void writeq(u64 val, void __iomem *addr) ++{ ++ writel(((u32) (val)), (addr)); ++ writel(((u32) (val >> 32)), (addr + 4)); ++} ++#endif ++ ++#define ADDR_IN_RANGE(addr, low, high) \ ++ (((addr) < (high)) && ((addr) >= (low))) ++ ++#define PCI_OFFSET_FIRST_RANGE(adapter, off) \ ++ ((adapter)->ahw.pci_base0 + (off)) ++#define PCI_OFFSET_SECOND_RANGE(adapter, off) \ ++ ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) ++#define PCI_OFFSET_THIRD_RANGE(adapter, off) \ ++ ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) ++ ++static void __iomem *pci_base_offset(struct netxen_adapter *adapter, ++ unsigned long off) ++{ ++ if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END)) ++ return PCI_OFFSET_FIRST_RANGE(adapter, off); ++ ++ if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END)) ++ return PCI_OFFSET_SECOND_RANGE(adapter, off); ++ ++ if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END)) ++ return PCI_OFFSET_THIRD_RANGE(adapter, off); ++ ++ return NULL; ++} ++ ++static crb_128M_2M_block_map_t ++crb_128M_2M_map[64] __cacheline_aligned_in_smp = { + {{{0, 0, 0, 0} } }, /* 0: PCI */ + {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ + {1, 0x0110000, 0x0120000, 0x130000}, +@@ -282,36 +312,63 @@ + + /* PCI Windowing for DDR regions. */ + +-#define ADDR_IN_RANGE(addr, low, high) \ +- (((addr) <= (high)) && ((addr) >= (low))) +- + #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ + +-#define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL +-#define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL +-#define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL +-#define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL ++#define NETXEN_PCIE_SEM_TIMEOUT 10000 + +-#define NETXEN_NIC_WINDOW_MARGIN 0x100000 ++int ++netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg) ++{ ++ int done = 0, timeout = 0; + +-int netxen_nic_set_mac(struct net_device *netdev, void *p) ++ while (!done) { ++ done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem))); ++ if (done == 1) ++ break; ++ if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT) ++ return -1; ++ msleep(1); ++ } ++ ++ if (id_reg) ++ NXWR32(adapter, id_reg, adapter->portnum); ++ ++ return 0; ++} ++ ++void ++netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem) + { +- struct netxen_adapter *adapter = netdev_priv(netdev); +- struct sockaddr *addr = p; ++ int val; ++ val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem))); ++} + +- if (netif_running(netdev)) +- return -EBUSY; ++int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port) ++{ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { ++ NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447); ++ NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5); ++ } + +- if (!is_valid_ether_addr(addr->sa_data)) +- return -EADDRNOTAVAIL; ++ return 0; ++} + +- memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); ++/* Disable an XG interface */ ++int netxen_niu_disable_xg_port(struct netxen_adapter *adapter) ++{ ++ __u32 mac_cfg; ++ u32 port = adapter->physical_port; + +- /* For P3, MAC addr is not set in NIU */ +- if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) +- if (adapter->macaddr_set) +- adapter->macaddr_set(adapter, addr->sa_data); ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) ++ return 0; + ++ if (port > NETXEN_NIU_MAX_XG_PORTS) ++ return -EINVAL; ++ ++ mac_cfg = 0; ++ if (NXWR32(adapter, ++ NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg)) ++ return -EIO; + return 0; + } + +@@ -324,6 +381,56 @@ + #define MAC_LO(addr) \ + ((addr[5] << 16) | (addr[4] << 8) | (addr[3])) + ++int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode) ++{ ++ __u32 reg; ++ u32 port = adapter->physical_port; ++ ++ if (port > NETXEN_NIU_MAX_XG_PORTS) ++ return -EINVAL; ++ ++ reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port)); ++ if (mode == NETXEN_NIU_PROMISC_MODE) ++ reg = (reg | 0x2000UL); ++ else ++ reg = (reg & ~0x2000UL); ++ ++ if (mode == NETXEN_NIU_ALLMULTI_MODE) ++ reg = (reg | 0x1000UL); ++ else ++ reg = (reg & ~0x1000UL); ++ ++ NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg); ++ ++ return 0; ++} ++ ++int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr) ++{ ++ u32 mac_hi, mac_lo; ++ u32 reg_hi, reg_lo; ++ ++ u8 phy = adapter->physical_port; ++ ++ if (phy >= NETXEN_NIU_MAX_XG_PORTS) ++ return -EINVAL; ++ ++ mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24); ++ mac_hi = addr[2] | ((u32)addr[3] << 8) | ++ ((u32)addr[4] << 16) | ((u32)addr[5] << 24); ++ ++ reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy); ++ reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy); ++ ++ /* write twice to flush */ ++ if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi)) ++ return -EIO; ++ if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi)) ++ return -EIO; ++ ++ return 0; ++} ++ + static int + netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter) + { +@@ -334,22 +441,20 @@ + if (adapter->mc_enabled) + return 0; + +- adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); ++ val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); + val |= (1UL << (28+port)); +- adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); ++ NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); + + /* add broadcast addr to filter */ + val = 0xffffff; +- netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_UNICAST_ADDR(port, 0)+4, val); ++ NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); ++ NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); + + /* add station addr to filter */ + val = MAC_HI(addr); +- netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val); ++ NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val); + val = MAC_LO(addr); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_UNICAST_ADDR(port, 1)+4, val); ++ NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val); + + adapter->mc_enabled = 1; + return 0; +@@ -365,18 +470,17 @@ + if (!adapter->mc_enabled) + return 0; + +- adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); ++ val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); + val &= ~(1UL << (28+port)); +- adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); ++ NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); + + val = MAC_HI(addr); +- netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); ++ NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); + val = MAC_LO(addr); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_UNICAST_ADDR(port, 0)+4, val); ++ NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); + +- netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); +- netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); ++ NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); ++ NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); + + adapter->mc_enabled = 0; + return 0; +@@ -392,10 +496,8 @@ + lo = MAC_LO(addr); + hi = MAC_HI(addr); + +- netxen_crb_writelit_adapter(adapter, +- NETXEN_MCAST_ADDR(port, index), hi); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_MCAST_ADDR(port, index)+4, lo); ++ NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi); ++ NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo); + + return 0; + } +@@ -448,100 +550,62 @@ + netxen_nic_set_mcast_addr(adapter, index, null_addr); + } + +-static int nx_p3_nic_add_mac(struct netxen_adapter *adapter, +- u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list) ++static int ++netxen_send_cmd_descs(struct netxen_adapter *adapter, ++ struct cmd_desc_type0 *cmd_desc_arr, int nr_desc) + { +- nx_mac_list_t *cur, *prev; ++ u32 i, producer, consumer; ++ struct netxen_cmd_buffer *pbuf; ++ struct cmd_desc_type0 *cmd_desc; ++ struct nx_host_tx_ring *tx_ring; + +- /* if in del_list, move it to adapter->mac_list */ +- for (cur = *del_list, prev = NULL; cur;) { +- if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) { +- if (prev == NULL) +- *del_list = cur->next; +- else +- prev->next = cur->next; +- cur->next = adapter->mac_list; +- adapter->mac_list = cur; +- return 0; +- } +- prev = cur; +- cur = cur->next; ++ i = 0; ++ ++ if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) ++ return -EIO; ++ ++ tx_ring = adapter->tx_ring; ++ __netif_tx_lock_bh(tx_ring->txq); ++ ++ producer = tx_ring->producer; ++ consumer = tx_ring->sw_consumer; ++ ++ if (nr_desc >= netxen_tx_avail(tx_ring)) { ++ netif_tx_stop_queue(tx_ring->txq); ++ __netif_tx_unlock_bh(tx_ring->txq); ++ return -EBUSY; + } + +- /* make sure to add each mac address only once */ +- for (cur = adapter->mac_list; cur; cur = cur->next) { +- if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) +- return 0; +- } +- /* not in del_list, create new entry and add to add_list */ +- cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL); +- if (cur == NULL) { +- printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may" +- "not work properly from now.\n", __func__); +- return -1; +- } ++ do { ++ cmd_desc = &cmd_desc_arr[i]; + +- memcpy(cur->mac_addr, addr, ETH_ALEN); +- cur->next = *add_list; +- *add_list = cur; ++ pbuf = &tx_ring->cmd_buf_arr[producer]; ++ pbuf->skb = NULL; ++ pbuf->frag_count = 0; ++ ++ memcpy(&tx_ring->desc_head[producer], ++ &cmd_desc_arr[i], sizeof(struct cmd_desc_type0)); ++ ++ producer = get_next_index(producer, tx_ring->num_desc); ++ i++; ++ ++ } while (i != nr_desc); ++ ++ tx_ring->producer = producer; ++ ++ netxen_nic_update_cmd_producer(adapter, tx_ring); ++ ++ __netif_tx_unlock_bh(tx_ring->txq); ++ + return 0; + } + + static int +-netxen_send_cmd_descs(struct netxen_adapter *adapter, +- struct cmd_desc_type0 *cmd_desc_arr, int nr_elements) ++nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op) + { +- uint32_t i, producer; +- struct netxen_cmd_buffer *pbuf; +- struct cmd_desc_type0 *cmd_desc; +- +- if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) { +- printk(KERN_WARNING "%s: Too many command descriptors in a " +- "request\n", __func__); +- return -EINVAL; +- } +- +- i = 0; +- +- netif_tx_lock_bh(adapter->netdev); +- +- producer = adapter->cmd_producer; +- do { +- cmd_desc = &cmd_desc_arr[i]; +- +- pbuf = &adapter->cmd_buf_arr[producer]; +- pbuf->skb = NULL; +- pbuf->frag_count = 0; +- +- /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */ +- memcpy(&adapter->ahw.cmd_desc_head[producer], +- &cmd_desc_arr[i], sizeof(struct cmd_desc_type0)); +- +- producer = get_next_index(producer, +- adapter->max_tx_desc_count); +- i++; +- +- } while (i != nr_elements); +- +- adapter->cmd_producer = producer; +- +- /* write producer index to start the xmit */ +- +- netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer); +- +- netif_tx_unlock_bh(adapter->netdev); +- +- return 0; +-} +- +-static int nx_p3_sre_macaddr_change(struct net_device *dev, +- u8 *addr, unsigned op) +-{ +- struct netxen_adapter *adapter = (struct netxen_adapter *)dev->priv; + nx_nic_req_t req; + nx_mac_req_t *mac_req; + u64 word; +- int rv; + + memset(&req, 0, sizeof(nx_nic_req_t)); + req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23); +@@ -553,28 +617,51 @@ + mac_req->op = op; + memcpy(mac_req->mac_addr, addr, 6); + +- rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); +- if (rv != 0) { +- printk(KERN_ERR "ERROR. Could not send mac update\n"); +- return rv; ++ return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); ++} ++ ++static int nx_p3_nic_add_mac(struct netxen_adapter *adapter, ++ u8 *addr, struct list_head *del_list) ++{ ++ struct list_head *head; ++ nx_mac_list_t *cur; ++ ++ /* look up if already exists */ ++ list_for_each(head, del_list) { ++ cur = list_entry(head, nx_mac_list_t, list); ++ ++ if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) { ++ list_move_tail(head, &adapter->mac_list); ++ return 0; ++ } + } + +- return 0; ++ cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC); ++ if (cur == NULL) { ++ printk(KERN_ERR "%s: failed to add mac address filter\n", ++ adapter->netdev->name); ++ return -ENOMEM; ++ } ++ memcpy(cur->mac_addr, addr, ETH_ALEN); ++ list_add_tail(&cur->list, &adapter->mac_list); ++ return nx_p3_sre_macaddr_change(adapter, ++ cur->mac_addr, NETXEN_MAC_ADD); + } + + void netxen_p3_nic_set_multi(struct net_device *netdev) + { + struct netxen_adapter *adapter = netdev_priv(netdev); +- nx_mac_list_t *cur, *next, *del_list, *add_list = NULL; + struct dev_mc_list *mc_ptr; + u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + u32 mode = VPORT_MISS_MODE_DROP; ++ LIST_HEAD(del_list); ++ struct list_head *head; ++ nx_mac_list_t *cur; + +- del_list = adapter->mac_list; +- adapter->mac_list = NULL; ++ list_splice_tail_init(&adapter->mac_list, &del_list); + +- nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list); +- nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list); ++ nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list); ++ nx_p3_nic_add_mac(adapter, bcast_addr, &del_list); + + if (netdev->flags & IFF_PROMISC) { + mode = VPORT_MISS_MODE_ACCEPT_ALL; +@@ -590,25 +677,20 @@ + if (netdev->mc_count > 0) { + for (mc_ptr = netdev->mc_list; mc_ptr; + mc_ptr = mc_ptr->next) { +- nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, +- &add_list, &del_list); ++ nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list); + } + } + + send_fw_cmd: + adapter->set_promisc(adapter, mode); +- for (cur = del_list; cur;) { +- nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL); +- next = cur->next; ++ head = &del_list; ++ while (!list_empty(head)) { ++ cur = list_entry(head->next, nx_mac_list_t, list); ++ ++ nx_p3_sre_macaddr_change(adapter, ++ cur->mac_addr, NETXEN_MAC_DEL); ++ list_del(&cur->list); + kfree(cur); +- cur = next; +- } +- for (cur = add_list; cur;) { +- nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD); +- next = cur->next; +- cur->next = adapter->mac_list; +- adapter->mac_list = cur; +- cur = next; + } + } + +@@ -633,15 +715,23 @@ + + void netxen_p3_free_mac_list(struct netxen_adapter *adapter) + { +- nx_mac_list_t *cur, *next; ++ nx_mac_list_t *cur; ++ struct list_head *head = &adapter->mac_list; + +- cur = adapter->mac_list; ++ while (!list_empty(head)) { ++ cur = list_entry(head->next, nx_mac_list_t, list); ++ nx_p3_sre_macaddr_change(adapter, ++ cur->mac_addr, NETXEN_MAC_DEL); ++ list_del(&cur->list); ++ kfree(cur); ++ } ++} + +- while (cur) { +- next = cur->next; +- kfree(cur); +- cur = next; +- } ++int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr) ++{ ++ /* assuming caller has already copied new addr to netdev */ ++ netxen_p3_nic_set_multi(adapter->netdev); ++ return 0; + } + + #define NETXEN_CONFIG_INTR_COALESCE 3 +@@ -657,7 +747,7 @@ + + memset(&req, 0, sizeof(nx_nic_req_t)); + +- req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23); ++ req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); + + word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16); + req.req_hdr = cpu_to_le64(word); +@@ -670,6 +760,182 @@ + "interrupt coalescing parameters\n"); + } + ++ return rv; ++} ++ ++int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable) ++{ ++ nx_nic_req_t req; ++ u64 word; ++ int rv = 0; ++ ++ if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable) ++ return 0; ++ ++ memset(&req, 0, sizeof(nx_nic_req_t)); ++ ++ req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); ++ ++ word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16); ++ req.req_hdr = cpu_to_le64(word); ++ ++ req.words[0] = cpu_to_le64(enable); ++ ++ rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); ++ if (rv != 0) { ++ printk(KERN_ERR "ERROR. Could not send " ++ "configure hw lro request\n"); ++ } ++ ++ adapter->flags ^= NETXEN_NIC_LRO_ENABLED; ++ ++ return rv; ++} ++ ++int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable) ++{ ++ nx_nic_req_t req; ++ u64 word; ++ int rv = 0; ++ ++ if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable) ++ return rv; ++ ++ memset(&req, 0, sizeof(nx_nic_req_t)); ++ ++ req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); ++ ++ word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING | ++ ((u64)adapter->portnum << 16); ++ req.req_hdr = cpu_to_le64(word); ++ ++ req.words[0] = cpu_to_le64(enable); ++ ++ rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); ++ if (rv != 0) { ++ printk(KERN_ERR "ERROR. Could not send " ++ "configure bridge mode request\n"); ++ } ++ ++ adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED; ++ ++ return rv; ++} ++ ++ ++#define RSS_HASHTYPE_IP_TCP 0x3 ++ ++int netxen_config_rss(struct netxen_adapter *adapter, int enable) ++{ ++ nx_nic_req_t req; ++ u64 word; ++ int i, rv; ++ ++ u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, ++ 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, ++ 0x255b0ec26d5a56daULL }; ++ ++ ++ memset(&req, 0, sizeof(nx_nic_req_t)); ++ req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); ++ ++ word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16); ++ req.req_hdr = cpu_to_le64(word); ++ ++ /* ++ * RSS request: ++ * bits 3-0: hash_method ++ * 5-4: hash_type_ipv4 ++ * 7-6: hash_type_ipv6 ++ * 8: enable ++ * 9: use indirection table ++ * 47-10: reserved ++ * 63-48: indirection table mask ++ */ ++ word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) | ++ ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) | ++ ((u64)(enable & 0x1) << 8) | ++ ((0x7ULL) << 48); ++ req.words[0] = cpu_to_le64(word); ++ for (i = 0; i < 5; i++) ++ req.words[i+1] = cpu_to_le64(key[i]); ++ ++ ++ rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); ++ if (rv != 0) { ++ printk(KERN_ERR "%s: could not configure RSS\n", ++ adapter->netdev->name); ++ } ++ ++ return rv; ++} ++ ++int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd) ++{ ++ nx_nic_req_t req; ++ u64 word; ++ int rv; ++ ++ memset(&req, 0, sizeof(nx_nic_req_t)); ++ req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); ++ ++ word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16); ++ req.req_hdr = cpu_to_le64(word); ++ ++ req.words[0] = cpu_to_le64(cmd); ++ req.words[1] = cpu_to_le64(ip); ++ ++ rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); ++ if (rv != 0) { ++ printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n", ++ adapter->netdev->name, ++ (cmd == NX_IP_UP) ? "Add" : "Remove", ip); ++ } ++ return rv; ++} ++ ++int netxen_linkevent_request(struct netxen_adapter *adapter, int enable) ++{ ++ nx_nic_req_t req; ++ u64 word; ++ int rv; ++ ++ memset(&req, 0, sizeof(nx_nic_req_t)); ++ req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); ++ ++ word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16); ++ req.req_hdr = cpu_to_le64(word); ++ req.words[0] = cpu_to_le64(enable | (enable << 8)); ++ ++ rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); ++ if (rv != 0) { ++ printk(KERN_ERR "%s: could not configure link notification\n", ++ adapter->netdev->name); ++ } ++ ++ return rv; ++} ++ ++int netxen_send_lro_cleanup(struct netxen_adapter *adapter) ++{ ++ nx_nic_req_t req; ++ u64 word; ++ int rv; ++ ++ memset(&req, 0, sizeof(nx_nic_req_t)); ++ req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); ++ ++ word = NX_NIC_H2C_OPCODE_LRO_REQUEST | ++ ((u64)adapter->portnum << 16) | ++ ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ; ++ ++ req.req_hdr = cpu_to_le64(word); ++ ++ rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); ++ if (rv != 0) { ++ printk(KERN_ERR "%s: could not cleanup lro flows\n", ++ adapter->netdev->name); ++ } + return rv; + } + +@@ -706,34 +972,11 @@ + return rc; + } + +-int netxen_is_flash_supported(struct netxen_adapter *adapter) +-{ +- const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 }; +- int addr, val01, val02, i, j; +- +- /* if the flash size less than 4Mb, make huge war cry and die */ +- for (j = 1; j < 4; j++) { +- addr = j * NETXEN_NIC_WINDOW_MARGIN; +- for (i = 0; i < ARRAY_SIZE(locs); i++) { +- if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0 +- && netxen_rom_fast_read(adapter, (addr + locs[i]), +- &val02) == 0) { +- if (val01 == val02) +- return -1; +- } else +- return -1; +- } +- } +- +- return 0; +-} +- + static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, + int size, __le32 * buf) + { +- int i, addr; ++ int i, v, addr; + __le32 *ptr32; +- u32 v; + + addr = base; + ptr32 = buf; +@@ -760,18 +1003,15 @@ + __le32 *pmac = (__le32 *) mac; + u32 offset; + +- offset = NETXEN_USER_START + +- offsetof(struct netxen_new_user_info, mac_addr) + +- adapter->portnum * sizeof(u64); ++ offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64)); + + if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1) + return -1; + + if (*mac == cpu_to_le64(~0ULL)) { + +- offset = NETXEN_USER_START_OLD + +- offsetof(struct netxen_user_old_info, mac_addr) + +- adapter->portnum * sizeof(u64); ++ offset = NX_OLD_MAC_ADDR_OFFSET + ++ (adapter->portnum * sizeof(u64)); + + if (netxen_get_flash_block(adapter, + offset, sizeof(u64), pmac) == -1) +@@ -791,8 +1031,8 @@ + crbaddr = CRB_MAC_BLOCK_START + + (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1)); + +- adapter->hw_read_wx(adapter, crbaddr, &mac_lo, 4); +- adapter->hw_read_wx(adapter, crbaddr+4, &mac_hi, 4); ++ mac_lo = NXRD32(adapter, crbaddr); ++ mac_hi = NXRD32(adapter, crbaddr+4); + + if (pci_func & 1) + *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16)); +@@ -802,40 +1042,10 @@ + return 0; + } + +-#define CRB_WIN_LOCK_TIMEOUT 100000000 +- +-static int crb_win_lock(struct netxen_adapter *adapter) +-{ +- int done = 0, timeout = 0; +- +- while (!done) { +- /* acquire semaphore3 from PCI HW block */ +- adapter->hw_read_wx(adapter, +- NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4); +- if (done == 1) +- break; +- if (timeout >= CRB_WIN_LOCK_TIMEOUT) +- return -1; +- timeout++; +- udelay(1); +- } +- netxen_crb_writelit_adapter(adapter, +- NETXEN_CRB_WIN_LOCK_ID, adapter->portnum); +- return 0; +-} +- +-static void crb_win_unlock(struct netxen_adapter *adapter) +-{ +- int val; +- +- adapter->hw_read_wx(adapter, +- NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4); +-} +- + /* + * Changes the CRB window to the specified window. + */ +-void ++static void + netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw) + { + void __iomem *offset; +@@ -886,17 +1096,15 @@ + * In: 'off' is offset from base in 128M pci map + */ + static int +-netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, +- ulong *off, int len) ++netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off) + { +- unsigned long end = *off + len; + crb_128M_2M_sub_block_map_t *m; + + + if (*off >= NETXEN_CRB_MAX) + return -1; + +- if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) { ++ if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) { + *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE + + (ulong)adapter->ahw.pci_base0; + return 0; +@@ -906,14 +1114,13 @@ + return -1; + + *off -= NETXEN_PCI_CRBSPACE; +- end = *off + len; + + /* + * Try direct map + */ + m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; + +- if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) { ++ if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { + *off = *off + m->start_2M - m->start_128M + + (ulong)adapter->ahw.pci_base0; + return 0; +@@ -936,13 +1143,12 @@ + u32 win_read; + + adapter->crb_win = CRB_HI(*off); +- writel(adapter->crb_win, (void *)(CRB_WINDOW_2M + +- adapter->ahw.pci_base0)); ++ writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M)); + /* + * Read back value to make sure write has gone through before trying + * to use it. + */ +- win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0)); ++ win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M); + if (win_read != adapter->crb_win) { + printk(KERN_ERR "%s: Written crbwin (0x%x) != " + "Read crbwin (0x%x), off=0x%lx\n", +@@ -952,143 +1158,71 @@ + (ulong)adapter->ahw.pci_base0; + } + +-int netxen_load_firmware(struct netxen_adapter *adapter) ++static int ++netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data) + { +- int i; +- u32 data, size = 0; +- u32 flashaddr = NETXEN_BOOTLD_START; ++ unsigned long flags; ++ void __iomem *addr; + +- size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START)/4; ++ if (ADDR_IN_WINDOW1(off)) ++ addr = NETXEN_CRB_NORMALIZE(adapter, off); ++ else ++ addr = pci_base_offset(adapter, off); + +- if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) +- adapter->pci_write_normalize(adapter, +- NETXEN_ROMUSB_GLB_CAS_RST, 1); ++ BUG_ON(!addr); + +- for (i = 0; i < size; i++) { +- if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) +- return -EIO; +- +- adapter->pci_mem_write(adapter, flashaddr, &data, 4); +- flashaddr += 4; +- } +- msleep(1); +- +- if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) +- adapter->pci_write_normalize(adapter, +- NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d); +- else { +- adapter->pci_write_normalize(adapter, +- NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff); +- adapter->pci_write_normalize(adapter, +- NETXEN_ROMUSB_GLB_CAS_RST, 0); ++ if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ ++ read_lock(&adapter->adapter_lock); ++ writel(data, addr); ++ read_unlock(&adapter->adapter_lock); ++ } else { /* Window 0 */ ++ write_lock_irqsave(&adapter->adapter_lock, flags); ++ addr = pci_base_offset(adapter, off); ++ netxen_nic_pci_change_crbwindow_128M(adapter, 0); ++ writel(data, addr); ++ netxen_nic_pci_change_crbwindow_128M(adapter, 1); ++ write_unlock_irqrestore(&adapter->adapter_lock, flags); + } + + return 0; + } + +-int +-netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, +- ulong off, void *data, int len) ++static u32 ++netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off) + { ++ unsigned long flags; + void __iomem *addr; ++ u32 data; + +- if (ADDR_IN_WINDOW1(off)) { ++ if (ADDR_IN_WINDOW1(off)) + addr = NETXEN_CRB_NORMALIZE(adapter, off); ++ else ++ addr = pci_base_offset(adapter, off); ++ ++ BUG_ON(!addr); ++ ++ if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ ++ read_lock(&adapter->adapter_lock); ++ data = readl(addr); ++ read_unlock(&adapter->adapter_lock); + } else { /* Window 0 */ +- addr = pci_base_offset(adapter, off); ++ write_lock_irqsave(&adapter->adapter_lock, flags); + netxen_nic_pci_change_crbwindow_128M(adapter, 0); ++ data = readl(addr); ++ netxen_nic_pci_change_crbwindow_128M(adapter, 1); ++ write_unlock_irqrestore(&adapter->adapter_lock, flags); + } + +- DPRINTK(INFO, "writing to base %lx offset %llx addr %p" +- " data %llx len %d\n", +- pci_base(adapter, off), off, addr, +- *(unsigned long long *)data, len); +- if (!addr) { +- netxen_nic_pci_change_crbwindow_128M(adapter, 1); +- return 1; +- } +- +- switch (len) { +- case 1: +- writeb(*(u8 *) data, addr); +- break; +- case 2: +- writew(*(u16 *) data, addr); +- break; +- case 4: +- writel(*(u32 *) data, addr); +- break; +- case 8: +- writeq(*(u64 *) data, addr); +- break; +- default: +- DPRINTK(INFO, +- "writing data %lx to offset %llx, num words=%d\n", +- *(unsigned long *)data, off, (len >> 3)); +- +- netxen_nic_hw_block_write64((u64 __iomem *) data, addr, +- (len >> 3)); +- break; +- } +- if (!ADDR_IN_WINDOW1(off)) +- netxen_nic_pci_change_crbwindow_128M(adapter, 1); +- +- return 0; ++ return data; + } + +-int +-netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, +- ulong off, void *data, int len) ++static int ++netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data) + { +- void __iomem *addr; +- +- if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ +- addr = NETXEN_CRB_NORMALIZE(adapter, off); +- } else { /* Window 0 */ +- addr = pci_base_offset(adapter, off); +- netxen_nic_pci_change_crbwindow_128M(adapter, 0); +- } +- +- DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n", +- pci_base(adapter, off), off, addr); +- if (!addr) { +- netxen_nic_pci_change_crbwindow_128M(adapter, 1); +- return 1; +- } +- switch (len) { +- case 1: +- *(u8 *) data = readb(addr); +- break; +- case 2: +- *(u16 *) data = readw(addr); +- break; +- case 4: +- *(u32 *) data = readl(addr); +- break; +- case 8: +- *(u64 *) data = readq(addr); +- break; +- default: +- netxen_nic_hw_block_read64((u64 __iomem *) data, addr, +- (len >> 3)); +- break; +- } +- DPRINTK(INFO, "read %lx\n", *(unsigned long *)data); +- +- if (!ADDR_IN_WINDOW1(off)) +- netxen_nic_pci_change_crbwindow_128M(adapter, 1); +- +- return 0; +-} +- +-int +-netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, +- ulong off, void *data, int len) +-{ +- unsigned long flags = 0; ++ unsigned long flags; + int rv; + +- rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len); ++ rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off); + + if (rv == -1) { + printk(KERN_ERR "%s: invalid offset: 0x%016lx\n", +@@ -1101,46 +1235,24 @@ + write_lock_irqsave(&adapter->adapter_lock, flags); + crb_win_lock(adapter); + netxen_nic_pci_set_crbwindow_2M(adapter, &off); +- } +- +- DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n", +- *(unsigned long *)data, off, len); +- +- switch (len) { +- case 1: +- writeb(*(uint8_t *)data, (void *)off); +- break; +- case 2: +- writew(*(uint16_t *)data, (void *)off); +- break; +- case 4: +- writel(*(uint32_t *)data, (void *)off); +- break; +- case 8: +- writeq(*(uint64_t *)data, (void *)off); +- break; +- default: +- DPRINTK(1, INFO, +- "writing data %lx to offset %llx, num words=%d\n", +- *(unsigned long *)data, off, (len>>3)); +- break; +- } +- if (rv == 1) { ++ writel(data, (void __iomem *)off); + crb_win_unlock(adapter); + write_unlock_irqrestore(&adapter->adapter_lock, flags); +- } ++ } else ++ writel(data, (void __iomem *)off); ++ + + return 0; + } + +-int +-netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, +- ulong off, void *data, int len) ++static u32 ++netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off) + { +- unsigned long flags = 0; ++ unsigned long flags; + int rv; ++ u32 data; + +- rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len); ++ rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off); + + if (rv == -1) { + printk(KERN_ERR "%s: invalid offset: 0x%016lx\n", +@@ -1153,93 +1265,18 @@ + write_lock_irqsave(&adapter->adapter_lock, flags); + crb_win_lock(adapter); + netxen_nic_pci_set_crbwindow_2M(adapter, &off); +- } +- +- DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len); +- +- switch (len) { +- case 1: +- *(uint8_t *)data = readb((void *)off); +- break; +- case 2: +- *(uint16_t *)data = readw((void *)off); +- break; +- case 4: +- *(uint32_t *)data = readl((void *)off); +- break; +- case 8: +- *(uint64_t *)data = readq((void *)off); +- break; +- default: +- break; +- } +- +- DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data); +- +- if (rv == 1) { ++ data = readl((void __iomem *)off); + crb_win_unlock(adapter); + write_unlock_irqrestore(&adapter->adapter_lock, flags); +- } ++ } else ++ data = readl((void __iomem *)off); + +- return 0; +-} +- +-void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val) +-{ +- adapter->hw_write_wx(adapter, off, &val, 4); +-} +- +-int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off) +-{ +- int val; +- adapter->hw_read_wx(adapter, off, &val, 4); +- return val; +-} +- +-/* Change the window to 0, write and change back to window 1. */ +-void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value) +-{ +- adapter->hw_write_wx(adapter, index, &value, 4); +-} +- +-/* Change the window to 0, read and change back to window 1. */ +-void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value) +-{ +- adapter->hw_read_wx(adapter, index, value, 4); +-} +- +-void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value) +-{ +- adapter->hw_write_wx(adapter, index, &value, 4); +-} +- +-void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value) +-{ +- adapter->hw_read_wx(adapter, index, value, 4); +-} +- +-/* +- * check memory access boundary. +- * used by test agent. support ddr access only for now +- */ +-static unsigned long +-netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter, +- unsigned long long addr, int size) +-{ +- if (!ADDR_IN_RANGE(addr, +- NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) || +- !ADDR_IN_RANGE(addr+size-1, +- NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) || +- ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { +- return 0; +- } +- +- return 1; ++ return data; + } + + static int netxen_pci_set_window_warning_count; + +-unsigned long ++static unsigned long + netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, + unsigned long long addr) + { +@@ -1303,33 +1340,56 @@ + return addr; + } + +-/* +- * Note : only 32-bit writes! +- */ +-int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter, +- u64 off, u32 data) ++/* window 1 registers only */ ++static void netxen_nic_io_write_128M(struct netxen_adapter *adapter, ++ void __iomem *addr, u32 data) + { +- writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off))); +- return 0; ++ read_lock(&adapter->adapter_lock); ++ writel(data, addr); ++ read_unlock(&adapter->adapter_lock); + } + +-u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off) ++static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter, ++ void __iomem *addr) + { +- return readl((void __iomem *)(pci_base_offset(adapter, off))); ++ u32 val; ++ ++ read_lock(&adapter->adapter_lock); ++ val = readl(addr); ++ read_unlock(&adapter->adapter_lock); ++ ++ return val; + } + +-void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter, +- u64 off, u32 data) ++static void netxen_nic_io_write_2M(struct netxen_adapter *adapter, ++ void __iomem *addr, u32 data) + { +- writel(data, NETXEN_CRB_NORMALIZE(adapter, off)); ++ writel(data, addr); + } + +-u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off) ++static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter, ++ void __iomem *addr) + { +- return readl(NETXEN_CRB_NORMALIZE(adapter, off)); ++ return readl(addr); + } + +-unsigned long ++void __iomem * ++netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset) ++{ ++ ulong off = offset; ++ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { ++ if (offset < NETXEN_CRB_PCIX_HOST2 && ++ offset > NETXEN_CRB_PCIX_HOST) ++ return PCI_OFFSET_SECOND_RANGE(adapter, offset); ++ return NETXEN_CRB_NORMALIZE(adapter, offset); ++ } ++ ++ BUG_ON(netxen_nic_pci_get_crb_addr_2M(adapter, &off)); ++ return (void __iomem *)off; ++} ++ ++static unsigned long + netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, + unsigned long long addr) + { +@@ -1340,12 +1400,8 @@ + /* DDR network side */ + window = MN_WIN(addr); + adapter->ahw.ddr_mn_window = window; +- adapter->hw_write_wx(adapter, +- adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, +- &window, 4); +- adapter->hw_read_wx(adapter, +- adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, +- &win_read, 4); ++ NXWR32(adapter, adapter->ahw.mn_win_crb, window); ++ win_read = NXRD32(adapter, adapter->ahw.mn_win_crb); + if ((win_read << 17) != window) { + printk(KERN_INFO "Written MNwin (0x%x) != " + "Read MNwin (0x%x)\n", window, win_read); +@@ -1360,12 +1416,8 @@ + + window = OCM_WIN(addr); + adapter->ahw.ddr_mn_window = window; +- adapter->hw_write_wx(adapter, +- adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, +- &window, 4); +- adapter->hw_read_wx(adapter, +- adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, +- &win_read, 4); ++ NXWR32(adapter, adapter->ahw.mn_win_crb, window); ++ win_read = NXRD32(adapter, adapter->ahw.mn_win_crb); + if ((win_read >> 7) != window) { + printk(KERN_INFO "%s: Written OCMwin (0x%x) != " + "Read OCMwin (0x%x)\n", +@@ -1378,12 +1430,8 @@ + /* QDR network side */ + window = MS_WIN(addr); + adapter->ahw.qdr_sn_window = window; +- adapter->hw_write_wx(adapter, +- adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE, +- &window, 4); +- adapter->hw_read_wx(adapter, +- adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE, +- &win_read, 4); ++ NXWR32(adapter, adapter->ahw.ms_win_crb, window); ++ win_read = NXRD32(adapter, adapter->ahw.ms_win_crb); + if (win_read != window) { + printk(KERN_INFO "%s: Written MSwin (0x%x) != " + "Read MSwin (0x%x)\n", +@@ -1406,206 +1454,40 @@ + return addr; + } + +-static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter, +- unsigned long long addr) +-{ +- int window; +- unsigned long long qdr_max; +- +- if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) +- qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2; +- else +- qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3; +- +- if (ADDR_IN_RANGE(addr, +- NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { +- /* DDR network side */ +- BUG(); /* MN access can not come here */ +- } else if (ADDR_IN_RANGE(addr, +- NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { +- return 1; +- } else if (ADDR_IN_RANGE(addr, +- NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { +- return 1; +- } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) { +- /* QDR network side */ +- window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f; +- if (adapter->ahw.qdr_sn_window == window) +- return 1; +- } +- +- return 0; +-} +- +-static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter, +- u64 off, void *data, int size) +-{ +- unsigned long flags; +- void *addr; +- int ret = 0; +- u64 start; +- uint8_t *mem_ptr = NULL; +- unsigned long mem_base; +- unsigned long mem_page; +- +- write_lock_irqsave(&adapter->adapter_lock, flags); +- +- /* +- * If attempting to access unknown address or straddle hw windows, +- * do not access. +- */ +- start = adapter->pci_set_window(adapter, off); +- if ((start == -1UL) || +- (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { +- write_unlock_irqrestore(&adapter->adapter_lock, flags); +- printk(KERN_ERR "%s out of bound pci memory access. " +- "offset is 0x%llx\n", netxen_nic_driver_name, +- (unsigned long long)off); +- return -1; +- } +- +- addr = (void *)(pci_base_offset(adapter, start)); +- if (!addr) { +- write_unlock_irqrestore(&adapter->adapter_lock, flags); +- mem_base = pci_resource_start(adapter->pdev, 0); +- mem_page = start & PAGE_MASK; +- /* Map two pages whenever user tries to access addresses in two +- consecutive pages. +- */ +- if (mem_page != ((start + size - 1) & PAGE_MASK)) +- mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); +- else +- mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); +- if (mem_ptr == 0UL) { +- *(uint8_t *)data = 0; +- return -1; +- } +- addr = mem_ptr; +- addr += start & (PAGE_SIZE - 1); +- write_lock_irqsave(&adapter->adapter_lock, flags); +- } +- +- switch (size) { +- case 1: +- *(uint8_t *)data = readb(addr); +- break; +- case 2: +- *(uint16_t *)data = readw(addr); +- break; +- case 4: +- *(uint32_t *)data = readl(addr); +- break; +- case 8: +- *(uint64_t *)data = readq(addr); +- break; +- default: +- ret = -1; +- break; +- } +- write_unlock_irqrestore(&adapter->adapter_lock, flags); +- DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data); +- +- if (mem_ptr) +- iounmap(mem_ptr); +- return ret; +-} ++#define MAX_CTL_CHECK 1000 + + static int +-netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off, +- void *data, int size) +-{ +- unsigned long flags; +- void *addr; +- int ret = 0; +- u64 start; +- uint8_t *mem_ptr = NULL; +- unsigned long mem_base; +- unsigned long mem_page; +- +- write_lock_irqsave(&adapter->adapter_lock, flags); +- +- /* +- * If attempting to access unknown address or straddle hw windows, +- * do not access. +- */ +- start = adapter->pci_set_window(adapter, off); +- if ((start == -1UL) || +- (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { +- write_unlock_irqrestore(&adapter->adapter_lock, flags); +- printk(KERN_ERR "%s out of bound pci memory access. " +- "offset is 0x%llx\n", netxen_nic_driver_name, +- (unsigned long long)off); +- return -1; +- } +- +- addr = (void *)(pci_base_offset(adapter, start)); +- if (!addr) { +- write_unlock_irqrestore(&adapter->adapter_lock, flags); +- mem_base = pci_resource_start(adapter->pdev, 0); +- mem_page = start & PAGE_MASK; +- /* Map two pages whenever user tries to access addresses in two +- * consecutive pages. +- */ +- if (mem_page != ((start + size - 1) & PAGE_MASK)) +- mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); +- else +- mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); +- if (mem_ptr == 0UL) +- return -1; +- addr = mem_ptr; +- addr += start & (PAGE_SIZE - 1); +- write_lock_irqsave(&adapter->adapter_lock, flags); +- } +- +- switch (size) { +- case 1: +- writeb(*(uint8_t *)data, addr); +- break; +- case 2: +- writew(*(uint16_t *)data, addr); +- break; +- case 4: +- writel(*(uint32_t *)data, addr); +- break; +- case 8: +- writeq(*(uint64_t *)data, addr); +- break; +- default: +- ret = -1; +- break; +- } +- write_unlock_irqrestore(&adapter->adapter_lock, flags); +- DPRINTK(1, INFO, "writing data %llx to offset %llx\n", +- *(unsigned long long *)data, start); +- if (mem_ptr) +- iounmap(mem_ptr); +- return ret; +-} +- +-#define MAX_CTL_CHECK 1000 +- +-int + netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, + u64 off, void *data, int size) + { +- unsigned long flags, mem_crb; ++ unsigned long flags; + int i, j, ret = 0, loop, sz[2], off0; + uint32_t temp; + uint64_t off8, tmpw, word[2] = {0, 0}; ++ void __iomem *mem_crb; + +- /* +- * If not MN, go check for MS or invalid. +- */ +- if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) +- return netxen_nic_pci_mem_write_direct(adapter, +- off, data, size); ++ if (size != 8) ++ return -EIO; + ++ if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, ++ NETXEN_ADDR_QDR_NET_MAX_P2)) { ++ mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET); ++ goto correct; ++ } ++ ++ if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { ++ mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET); ++ goto correct; ++ } ++ ++ return -EIO; ++ ++correct: + off8 = off & 0xfffffff8; + off0 = off & 0x7; + sz[0] = (size < (8 - off0)) ? size : (8 - off0); + sz[1] = size - sz[0]; + loop = ((off0 + size - 1) >> 3) + 1; +- mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET); + + if ((size != 8) || (off0 != 0)) { + for (i = 0; i < loop; i++) { +@@ -1643,28 +1525,29 @@ + + for (i = 0; i < loop; i++) { + writel((uint32_t)(off8 + (i << 3)), +- (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO)); ++ (mem_crb+MIU_TEST_AGT_ADDR_LO)); + writel(0, +- (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI)); ++ (mem_crb+MIU_TEST_AGT_ADDR_HI)); + writel(word[i] & 0xffffffff, +- (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO)); ++ (mem_crb+MIU_TEST_AGT_WRDATA_LO)); + writel((word[i] >> 32) & 0xffffffff, +- (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI)); ++ (mem_crb+MIU_TEST_AGT_WRDATA_HI)); + writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE, +- (void *)(mem_crb+MIU_TEST_AGT_CTRL)); ++ (mem_crb+MIU_TEST_AGT_CTRL)); + writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE, +- (void *)(mem_crb+MIU_TEST_AGT_CTRL)); ++ (mem_crb+MIU_TEST_AGT_CTRL)); + + for (j = 0; j < MAX_CTL_CHECK; j++) { + temp = readl( +- (void *)(mem_crb+MIU_TEST_AGT_CTRL)); ++ (mem_crb+MIU_TEST_AGT_CTRL)); + if ((temp & MIU_TA_CTL_BUSY) == 0) + break; + } + + if (j >= MAX_CTL_CHECK) { +- printk("%s: %s Fail to write through agent\n", +- __func__, netxen_nic_driver_name); ++ if (printk_ratelimit()) ++ dev_err(&adapter->pdev->dev, ++ "failed to write through agent\n"); + ret = -1; + break; + } +@@ -1675,53 +1558,64 @@ + return ret; + } + +-int ++static int + netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, + u64 off, void *data, int size) + { +- unsigned long flags, mem_crb; ++ unsigned long flags; + int i, j = 0, k, start, end, loop, sz[2], off0[2]; + uint32_t temp; + uint64_t off8, val, word[2] = {0, 0}; ++ void __iomem *mem_crb; + ++ if (size != 8) ++ return -EIO; + +- /* +- * If not MN, go check for MS or invalid. +- */ +- if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) +- return netxen_nic_pci_mem_read_direct(adapter, off, data, size); ++ if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, ++ NETXEN_ADDR_QDR_NET_MAX_P2)) { ++ mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET); ++ goto correct; ++ } + ++ if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { ++ mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET); ++ goto correct; ++ } ++ ++ return -EIO; ++ ++correct: + off8 = off & 0xfffffff8; + off0[0] = off & 0x7; + off0[1] = 0; + sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); + sz[1] = size - sz[0]; + loop = ((off0[0] + size - 1) >> 3) + 1; +- mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET); + + write_lock_irqsave(&adapter->adapter_lock, flags); + netxen_nic_pci_change_crbwindow_128M(adapter, 0); + + for (i = 0; i < loop; i++) { + writel((uint32_t)(off8 + (i << 3)), +- (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO)); ++ (mem_crb+MIU_TEST_AGT_ADDR_LO)); + writel(0, +- (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI)); ++ (mem_crb+MIU_TEST_AGT_ADDR_HI)); + writel(MIU_TA_CTL_ENABLE, +- (void *)(mem_crb+MIU_TEST_AGT_CTRL)); ++ (mem_crb+MIU_TEST_AGT_CTRL)); + writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE, +- (void *)(mem_crb+MIU_TEST_AGT_CTRL)); ++ (mem_crb+MIU_TEST_AGT_CTRL)); + + for (j = 0; j < MAX_CTL_CHECK; j++) { + temp = readl( +- (void *)(mem_crb+MIU_TEST_AGT_CTRL)); ++ (mem_crb+MIU_TEST_AGT_CTRL)); + if ((temp & MIU_TA_CTL_BUSY) == 0) + break; + } + + if (j >= MAX_CTL_CHECK) { +- printk(KERN_ERR "%s: %s Fail to read through agent\n", +- __func__, netxen_nic_driver_name); ++ if (printk_ratelimit()) ++ dev_err(&adapter->pdev->dev, ++ "failed to read through agent\n"); + break; + } + +@@ -1729,7 +1623,7 @@ + end = (off0[i] + sz[i] - 1) >> 2; + for (k = start; k <= end; k++) { + word[i] |= ((uint64_t) readl( +- (void *)(mem_crb + ++ (mem_crb + + MIU_TEST_AGT_RDDATA(k))) << (32*k)); + } + } +@@ -1761,30 +1655,35 @@ + *(uint64_t *)data = val; + break; + } +- DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data); + return 0; + } + +-int ++static int + netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, + u64 off, void *data, int size) + { + int i, j, ret = 0, loop, sz[2], off0; + uint32_t temp; +- uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; ++ uint64_t off8, tmpw, word[2] = {0, 0}; ++ void __iomem *mem_crb; + +- /* +- * If not MN, go check for MS or invalid. +- */ +- if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3) +- mem_crb = NETXEN_CRB_QDR_NET; +- else { +- mem_crb = NETXEN_CRB_DDR_NET; +- if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) +- return netxen_nic_pci_mem_write_direct(adapter, +- off, data, size); ++ if (size != 8) ++ return -EIO; ++ ++ if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, ++ NETXEN_ADDR_QDR_NET_MAX_P3)) { ++ mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET); ++ goto correct; + } + ++ if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { ++ mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET); ++ goto correct; ++ } ++ ++ return -EIO; ++ ++correct: + off8 = off & 0xfffffff8; + off0 = off & 0x7; + sz[0] = (size < (8 - off0)) ? size : (8 - off0); +@@ -1793,8 +1692,8 @@ + + if ((size != 8) || (off0 != 0)) { + for (i = 0; i < loop; i++) { +- if (adapter->pci_mem_read(adapter, off8 + (i << 3), +- &word[i], 8)) ++ if (adapter->pci_mem_read(adapter, ++ off8 + (i << 3), &word[i], 8)) + return -1; + } + } +@@ -1830,35 +1729,26 @@ + */ + + for (i = 0; i < loop; i++) { +- temp = off8 + (i << 3); +- adapter->hw_write_wx(adapter, +- mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4); +- temp = 0; +- adapter->hw_write_wx(adapter, +- mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4); +- temp = word[i] & 0xffffffff; +- adapter->hw_write_wx(adapter, +- mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4); +- temp = (word[i] >> 32) & 0xffffffff; +- adapter->hw_write_wx(adapter, +- mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4); +- temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; +- adapter->hw_write_wx(adapter, +- mem_crb+MIU_TEST_AGT_CTRL, &temp, 4); +- temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; +- adapter->hw_write_wx(adapter, +- mem_crb+MIU_TEST_AGT_CTRL, &temp, 4); ++ writel(off8 + (i << 3), mem_crb+MIU_TEST_AGT_ADDR_LO); ++ writel(0, mem_crb+MIU_TEST_AGT_ADDR_HI); ++ writel(word[i] & 0xffffffff, mem_crb+MIU_TEST_AGT_WRDATA_LO); ++ writel((word[i] >> 32) & 0xffffffff, ++ mem_crb+MIU_TEST_AGT_WRDATA_HI); ++ writel((MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE), ++ mem_crb+MIU_TEST_AGT_CTRL); ++ writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE, ++ mem_crb+MIU_TEST_AGT_CTRL); + + for (j = 0; j < MAX_CTL_CHECK; j++) { +- adapter->hw_read_wx(adapter, +- mem_crb + MIU_TEST_AGT_CTRL, &temp, 4); ++ temp = readl(mem_crb + MIU_TEST_AGT_CTRL); + if ((temp & MIU_TA_CTL_BUSY) == 0) + break; + } + + if (j >= MAX_CTL_CHECK) { +- printk(KERN_ERR "%s: Fail to write through agent\n", +- netxen_nic_driver_name); ++ if (printk_ratelimit()) ++ dev_err(&adapter->pdev->dev, ++ "failed to write through agent\n"); + ret = -1; + break; + } +@@ -1871,27 +1761,32 @@ + return ret; + } + +-int ++static int + netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, + u64 off, void *data, int size) + { + int i, j = 0, k, start, end, loop, sz[2], off0[2]; + uint32_t temp; +- uint64_t off8, val, mem_crb, word[2] = {0, 0}; ++ uint64_t off8, val, word[2] = {0, 0}; ++ void __iomem *mem_crb; + +- /* +- * If not MN, go check for MS or invalid. +- */ ++ if (size != 8) ++ return -EIO; + +- if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3) +- mem_crb = NETXEN_CRB_QDR_NET; +- else { +- mem_crb = NETXEN_CRB_DDR_NET; +- if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) +- return netxen_nic_pci_mem_read_direct(adapter, +- off, data, size); ++ if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, ++ NETXEN_ADDR_QDR_NET_MAX_P3)) { ++ mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET); ++ goto correct; + } + ++ if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { ++ mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET); ++ goto correct; ++ } ++ ++ return -EIO; ++ ++correct: + off8 = off & 0xfffffff8; + off0[0] = off & 0x7; + off0[1] = 0; +@@ -1906,37 +1801,29 @@ + */ + + for (i = 0; i < loop; i++) { +- temp = off8 + (i << 3); +- adapter->hw_write_wx(adapter, +- mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4); +- temp = 0; +- adapter->hw_write_wx(adapter, +- mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4); +- temp = MIU_TA_CTL_ENABLE; +- adapter->hw_write_wx(adapter, +- mem_crb + MIU_TEST_AGT_CTRL, &temp, 4); +- temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; +- adapter->hw_write_wx(adapter, +- mem_crb + MIU_TEST_AGT_CTRL, &temp, 4); ++ writel(off8 + (i << 3), mem_crb + MIU_TEST_AGT_ADDR_LO); ++ writel(0, mem_crb + MIU_TEST_AGT_ADDR_HI); ++ writel(MIU_TA_CTL_ENABLE, mem_crb + MIU_TEST_AGT_CTRL); ++ writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE, ++ mem_crb + MIU_TEST_AGT_CTRL); + + for (j = 0; j < MAX_CTL_CHECK; j++) { +- adapter->hw_read_wx(adapter, +- mem_crb + MIU_TEST_AGT_CTRL, &temp, 4); ++ temp = readl(mem_crb + MIU_TEST_AGT_CTRL); + if ((temp & MIU_TA_CTL_BUSY) == 0) + break; + } + + if (j >= MAX_CTL_CHECK) { +- printk(KERN_ERR "%s: Fail to read through agent\n", +- netxen_nic_driver_name); ++ if (printk_ratelimit()) ++ dev_err(&adapter->pdev->dev, ++ "failed to read through agent\n"); + break; + } + + start = off0[i] >> 2; + end = (off0[i] + sz[i] - 1) >> 2; + for (k = start; k <= end; k++) { +- adapter->hw_read_wx(adapter, +- mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4); ++ temp = readl(mem_crb + MIU_TEST_AGT_RDDATA(k)); + word[i] |= ((uint64_t)temp << (32 * k)); + } + } +@@ -1970,97 +1857,84 @@ + *(uint64_t *)data = val; + break; + } +- DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data); + return 0; + } + +-/* +- * Note : only 32-bit writes! +- */ +-int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, +- u64 off, u32 data) ++void ++netxen_setup_hwops(struct netxen_adapter *adapter) + { +- adapter->hw_write_wx(adapter, off, &data, 4); ++ adapter->init_port = netxen_niu_xg_init_port; ++ adapter->stop_port = netxen_niu_disable_xg_port; + +- return 0; ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { ++ adapter->crb_read = netxen_nic_hw_read_wx_128M, ++ adapter->crb_write = netxen_nic_hw_write_wx_128M, ++ adapter->pci_set_window = netxen_nic_pci_set_window_128M, ++ adapter->pci_mem_read = netxen_nic_pci_mem_read_128M, ++ adapter->pci_mem_write = netxen_nic_pci_mem_write_128M, ++ adapter->io_read = netxen_nic_io_read_128M, ++ adapter->io_write = netxen_nic_io_write_128M, ++ ++ adapter->macaddr_set = netxen_p2_nic_set_mac_addr; ++ adapter->set_multi = netxen_p2_nic_set_multi; ++ adapter->set_mtu = netxen_nic_set_mtu_xgb; ++ adapter->set_promisc = netxen_p2_nic_set_promisc; ++ ++ } else { ++ adapter->crb_read = netxen_nic_hw_read_wx_2M, ++ adapter->crb_write = netxen_nic_hw_write_wx_2M, ++ adapter->pci_set_window = netxen_nic_pci_set_window_2M, ++ adapter->pci_mem_read = netxen_nic_pci_mem_read_2M, ++ adapter->pci_mem_write = netxen_nic_pci_mem_write_2M, ++ adapter->io_read = netxen_nic_io_read_2M, ++ adapter->io_write = netxen_nic_io_write_2M, ++ ++ adapter->set_mtu = nx_fw_cmd_set_mtu; ++ adapter->set_promisc = netxen_p3_nic_set_promisc; ++ adapter->macaddr_set = netxen_p3_nic_set_mac_addr; ++ adapter->set_multi = netxen_p3_nic_set_multi; ++ ++ adapter->phy_read = nx_fw_cmd_query_phy; ++ adapter->phy_write = nx_fw_cmd_set_phy; ++ } + } +- +-u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off) +-{ +- u32 temp; +- adapter->hw_read_wx(adapter, off, &temp, 4); +- return temp; +-} +- +-void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter, +- u64 off, u32 data) +-{ +- adapter->hw_write_wx(adapter, off, &data, 4); +-} +- +-u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off) +-{ +- u32 temp; +- adapter->hw_read_wx(adapter, off, &temp, 4); +- return temp; +-} +- +-#if 0 +-int +-netxen_nic_erase_pxe(struct netxen_adapter *adapter) +-{ +- if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) { +- printk(KERN_ERR "%s: erase pxe failed\n", +- netxen_nic_driver_name); +- return -1; +- } +- return 0; +-} +-#endif /* 0 */ + + int netxen_nic_get_board_info(struct netxen_adapter *adapter) + { +- int rv = 0; +- int addr = NETXEN_BRDCFG_START; +- struct netxen_board_info *boardinfo; +- int index; +- u32 *ptr32; ++ int offset, board_type, magic, header_version; ++ struct pci_dev *pdev = adapter->pdev; + +- boardinfo = &adapter->ahw.boardcfg; +- ptr32 = (u32 *) boardinfo; ++ offset = NX_FW_MAGIC_OFFSET; ++ if (netxen_rom_fast_read(adapter, offset, &magic)) ++ return -EIO; + +- for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32); +- index++) { +- if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) { +- return -EIO; +- } +- ptr32++; +- addr += sizeof(u32); +- } +- if (boardinfo->magic != NETXEN_BDINFO_MAGIC) { +- printk("%s: ERROR reading %s board config." +- " Read %x, expected %x\n", netxen_nic_driver_name, +- netxen_nic_driver_name, +- boardinfo->magic, NETXEN_BDINFO_MAGIC); +- rv = -1; +- } +- if (boardinfo->header_version != NETXEN_BDINFO_VERSION) { +- printk("%s: Unknown board config version." +- " Read %x, expected %x\n", netxen_nic_driver_name, +- boardinfo->header_version, NETXEN_BDINFO_VERSION); +- rv = -1; ++ offset = NX_HDR_VERSION_OFFSET; ++ if (netxen_rom_fast_read(adapter, offset, &header_version)) ++ return -EIO; ++ ++ if (magic != NETXEN_BDINFO_MAGIC || ++ header_version != NETXEN_BDINFO_VERSION) { ++ dev_err(&pdev->dev, ++ "invalid board config, magic=%08x, version=%08x\n", ++ magic, header_version); ++ return -EIO; + } + +- if (boardinfo->board_type == NETXEN_BRDTYPE_P3_4_GB_MM) { +- u32 gpio = netxen_nic_reg_read(adapter, +- NETXEN_ROMUSB_GLB_PAD_GPIO_I); ++ offset = NX_BRDTYPE_OFFSET; ++ if (netxen_rom_fast_read(adapter, offset, &board_type)) ++ return -EIO; ++ ++ adapter->ahw.board_type = board_type; ++ ++ if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) { ++ u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I); + if ((gpio & 0x8000) == 0) +- boardinfo->board_type = NETXEN_BRDTYPE_P3_10G_TP; ++ board_type = NETXEN_BRDTYPE_P3_10G_TP; + } + +- switch ((netxen_brdtype_t) boardinfo->board_type) { ++ switch (board_type) { + case NETXEN_BRDTYPE_P2_SB35_4G: +- adapter->ahw.board_type = NETXEN_NIC_GBE; ++ adapter->ahw.port_type = NETXEN_NIC_GBE; + break; + case NETXEN_BRDTYPE_P2_SB31_10G: + case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: +@@ -2076,7 +1950,7 @@ + case NETXEN_BRDTYPE_P3_10G_SFP_QT: + case NETXEN_BRDTYPE_P3_10G_XFP: + case NETXEN_BRDTYPE_P3_10000_BASE_T: +- adapter->ahw.board_type = NETXEN_NIC_XGBE; ++ adapter->ahw.port_type = NETXEN_NIC_XGBE; + break; + case NETXEN_BRDTYPE_P1_BD: + case NETXEN_BRDTYPE_P1_SB: +@@ -2085,20 +1959,19 @@ + case NETXEN_BRDTYPE_P3_REF_QG: + case NETXEN_BRDTYPE_P3_4_GB: + case NETXEN_BRDTYPE_P3_4_GB_MM: +- adapter->ahw.board_type = NETXEN_NIC_GBE; ++ adapter->ahw.port_type = NETXEN_NIC_GBE; + break; + case NETXEN_BRDTYPE_P3_10G_TP: +- adapter->ahw.board_type = (adapter->portnum < 2) ? ++ adapter->ahw.port_type = (adapter->portnum < 2) ? + NETXEN_NIC_XGBE : NETXEN_NIC_GBE; + break; + default: +- printk("%s: Unknown(%x)\n", netxen_nic_driver_name, +- boardinfo->board_type); +- rv = -ENODEV; ++ dev_err(&pdev->dev, "unknown board type %x\n", board_type); ++ adapter->ahw.port_type = NETXEN_NIC_XGBE; + break; + } + +- return rv; ++ return 0; + } + + /* NIU access sections */ +@@ -2106,8 +1979,7 @@ + int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) + { + new_mtu += MTU_FUDGE_FACTOR; +- netxen_nic_write_w0(adapter, +- NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port), ++ NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port), + new_mtu); + return 0; + } +@@ -2116,19 +1988,10 @@ + { + new_mtu += MTU_FUDGE_FACTOR; + if (adapter->physical_port == 0) +- netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, +- new_mtu); ++ NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu); + else +- netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, +- new_mtu); ++ NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu); + return 0; +-} +- +-void +-netxen_crb_writelit_adapter(struct netxen_adapter *adapter, +- unsigned long off, int data) +-{ +- adapter->hw_write_wx(adapter, off, &data, 4); + } + + void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) +@@ -2144,9 +2007,8 @@ + return; + } + +- if (adapter->ahw.board_type == NETXEN_NIC_GBE) { +- adapter->hw_read_wx(adapter, +- NETXEN_PORT_MODE_ADDR, &port_mode, 4); ++ if (adapter->ahw.port_type == NETXEN_NIC_GBE) { ++ port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR); + if (port_mode == NETXEN_PORT_MODE_802_3_AP) { + adapter->link_speed = SPEED_1000; + adapter->link_duplex = DUPLEX_FULL; +@@ -2199,57 +2061,20 @@ + } + } + +-void netxen_nic_flash_print(struct netxen_adapter *adapter) ++int ++netxen_nic_wol_supported(struct netxen_adapter *adapter) + { +- u32 fw_major = 0; +- u32 fw_minor = 0; +- u32 fw_build = 0; +- char brd_name[NETXEN_MAX_SHORT_NAME]; +- char serial_num[32]; +- int i, addr; +- __le32 *ptr32; ++ u32 wol_cfg; + +- struct netxen_board_info *board_info = &(adapter->ahw.boardcfg); ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ++ return 0; + +- adapter->driver_mismatch = 0; +- +- ptr32 = (u32 *)&serial_num; +- addr = NETXEN_USER_START + +- offsetof(struct netxen_new_user_info, serial_num); +- for (i = 0; i < 8; i++) { +- if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) { +- printk("%s: ERROR reading %s board userarea.\n", +- netxen_nic_driver_name, +- netxen_nic_driver_name); +- adapter->driver_mismatch = 1; +- return; +- } +- ptr32++; +- addr += sizeof(u32); ++ wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV); ++ if (wol_cfg & (1UL << adapter->portnum)) { ++ wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG); ++ if (wol_cfg & (1 << adapter->portnum)) ++ return 1; + } + +- adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4); +- adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4); +- adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4); +- +- adapter->fw_major = fw_major; +- +- if (adapter->portnum == 0) { +- get_brd_name_by_type(board_info->board_type, brd_name); +- +- printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n", +- brd_name, serial_num, adapter->ahw.revision_id); +- printk(KERN_INFO "NetXen Firmware version %d.%d.%d\n", +- fw_major, fw_minor, fw_build); +- } +- +- if (NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build) < +- NETXEN_VERSION_CODE(3, 4, 216)) { +- adapter->driver_mismatch = 1; +- printk(KERN_ERR "%s: firmware version %d.%d.%d unsupported\n", +- netxen_nic_driver_name, +- fw_major, fw_minor, fw_build); +- return; +- } ++ return 0; + } +- +diff -r 6335373db0ec drivers/net/netxen/netxen_nic_hw.h +--- a/drivers/net/netxen/netxen_nic_hw.h Thu Oct 01 10:10:06 2009 +0100 ++++ b/drivers/net/netxen/netxen_nic_hw.h Mon Oct 05 17:00:12 2009 +0100 +@@ -1,5 +1,6 @@ + /* +- * Copyright (C) 2003 - 2006 NetXen, Inc. ++ * Copyright (C) 2003 - 2009 NetXen, Inc. ++ * Copyright (C) 2009 - QLogic Corporation. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or +@@ -20,79 +21,21 @@ + * The full GNU General Public License is included in this distribution + * in the file called LICENSE. + * +- * Contact Information: +- * info@netxen.com +- * NetXen, +- * 3965 Freedom Circle, Fourth floor, +- * Santa Clara, CA 95054 +- * +- * +- * Structures, enums, and macros for the MAC +- * + */ + + #ifndef __NETXEN_NIC_HW_H_ + #define __NETXEN_NIC_HW_H_ + +-#include "netxen_nic_hdr.h" +- + /* Hardware memory size of 128 meg */ + #define NETXEN_MEMADDR_MAX (128 * 1024 * 1024) +- +-#ifndef readq +-static inline u64 readq(void __iomem * addr) +-{ +- return readl(addr) | (((u64) readl(addr + 4)) << 32LL); +-} +-#endif +- +-#ifndef writeq +-static inline void writeq(u64 val, void __iomem * addr) +-{ +- writel(((u32) (val)), (addr)); +- writel(((u32) (val >> 32)), (addr + 4)); +-} +-#endif +- +-static inline void netxen_nic_hw_block_write64(u64 __iomem * data_ptr, +- u64 __iomem * addr, +- int num_words) +-{ +- int num; +- for (num = 0; num < num_words; num++) { +- writeq(readq((void __iomem *)data_ptr), addr); +- addr++; +- data_ptr++; +- } +-} +- +-static inline void netxen_nic_hw_block_read64(u64 __iomem * data_ptr, +- u64 __iomem * addr, int num_words) +-{ +- int num; +- for (num = 0; num < num_words; num++) { +- writeq(readq((void __iomem *)addr), data_ptr); +- addr++; +- data_ptr++; +- } +- +-} + + struct netxen_adapter; + + #define NETXEN_PCI_MAPSIZE_BYTES (NETXEN_PCI_MAPSIZE << 20) + +-struct netxen_port; + void netxen_nic_set_link_parameters(struct netxen_adapter *adapter); +-void netxen_nic_flash_print(struct netxen_adapter *adapter); +- +-typedef u8 netxen_ethernet_macaddr_t[6]; + + /* Nibble or Byte mode for phy interface (GbE mode only) */ +-typedef enum { +- NETXEN_NIU_10_100_MB = 0, +- NETXEN_NIU_1000_MB +-} netxen_niu_gbe_ifmode_t; + + #define _netxen_crb_get_bit(var, bit) ((var >> bit) & 0x1) + +@@ -113,10 +56,6 @@ + * Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op + */ + +-#define netxen_gb_enable_tx(config_word) \ +- ((config_word) |= 1 << 0) +-#define netxen_gb_enable_rx(config_word) \ +- ((config_word) |= 1 << 2) + #define netxen_gb_tx_flowctl(config_word) \ + ((config_word) |= 1 << 4) + #define netxen_gb_rx_flowctl(config_word) \ +@@ -129,8 +68,6 @@ + ((config_word) |= 1 << 18) + #define netxen_gb_rx_reset_mac(config_word) \ + ((config_word) |= 1 << 19) +-#define netxen_gb_soft_reset(config_word) \ +- ((config_word) |= 1 << 31) + + #define netxen_gb_unset_tx_flowctl(config_word) \ + ((config_word) &= ~(1 << 4)) +@@ -147,33 +84,6 @@ + _netxen_crb_get_bit((config_word), 5) + #define netxen_gb_get_soft_reset(config_word) \ + _netxen_crb_get_bit((config_word), 31) +- +-/* +- * NIU GB MAC Config Register 1 (applies to GB0, GB1, GB2, GB3) +- * +- * Bit 0 : duplex => 1:full duplex mode, 0:half duplex +- * Bit 1 : crc_enable => 1:append CRC to xmit frames, 0:dont append +- * Bit 2 : padshort => 1:pad short frames and add CRC, 0:dont pad +- * Bit 4 : checklength => 1:check framelen with actual,0:dont check +- * Bit 5 : hugeframes => 1:allow oversize xmit frames, 0:dont allow +- * Bits 8-9 : intfmode => 01:nibble (10/100), 10:byte (1000) +- * Bits 12-15 : preamblelen => preamble field length in bytes, default 7 +- */ +- +-#define netxen_gb_set_duplex(config_word) \ +- ((config_word) |= 1 << 0) +-#define netxen_gb_set_crc_enable(config_word) \ +- ((config_word) |= 1 << 1) +-#define netxen_gb_set_padshort(config_word) \ +- ((config_word) |= 1 << 2) +-#define netxen_gb_set_checklength(config_word) \ +- ((config_word) |= 1 << 4) +-#define netxen_gb_set_hugeframes(config_word) \ +- ((config_word) |= 1 << 5) +-#define netxen_gb_set_preamblelen(config_word, val) \ +- ((config_word) |= ((val) << 12) & 0xF000) +-#define netxen_gb_set_intfmode(config_word, val) \ +- ((config_word) |= ((val) << 8) & 0x300) + + #define netxen_gb_get_stationaddress_low(config_word) ((config_word) >> 16) + +@@ -277,30 +187,28 @@ + /* + * PHY-Specific MII control/status registers. + */ +-typedef enum { +- NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL = 0, +- NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS = 1, +- NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 = 2, +- NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 = 3, +- NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG = 4, +- NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART = 5, +- NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE = 6, +- NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT = 7, +- NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE = 8, +- NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL = 9, +- NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS = 10, +- NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS = 15, +- NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL = 16, +- NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS = 17, +- NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE = 18, +- NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS = 19, +- NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE = 20, +- NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT = 21, +- NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL = 24, +- NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE = 25, +- NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET = 26, +- NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE = 27 +-} netxen_niu_phy_register_t; ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL 0 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS 1 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 2 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 3 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG 4 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART 5 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE 6 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT 7 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE 8 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL 9 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS 10 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS 15 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL 16 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS 17 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE 18 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS 19 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE 20 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT 21 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL 24 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE 25 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET 26 ++#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE 27 + + /* + * PHY-Specific Status Register (reg 17). +@@ -321,7 +229,6 @@ + * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd + */ + +-#define netxen_get_phy_cablelen(config_word) (((config_word) >> 7) & 0x07) + #define netxen_get_phy_speed(config_word) (((config_word) >> 14) & 0x03) + + #define netxen_set_phy_speed(config_word, val) \ +@@ -331,83 +238,10 @@ + #define netxen_clear_phy_duplex(config_word) \ + ((config_word) &= ~(1 << 13)) + +-#define netxen_get_phy_jabber(config_word) \ +- _netxen_crb_get_bit(config_word, 0) +-#define netxen_get_phy_polarity(config_word) \ +- _netxen_crb_get_bit(config_word, 1) +-#define netxen_get_phy_recvpause(config_word) \ +- _netxen_crb_get_bit(config_word, 2) +-#define netxen_get_phy_xmitpause(config_word) \ +- _netxen_crb_get_bit(config_word, 3) +-#define netxen_get_phy_energydetect(config_word) \ +- _netxen_crb_get_bit(config_word, 4) +-#define netxen_get_phy_downshift(config_word) \ +- _netxen_crb_get_bit(config_word, 5) +-#define netxen_get_phy_crossover(config_word) \ +- _netxen_crb_get_bit(config_word, 6) + #define netxen_get_phy_link(config_word) \ + _netxen_crb_get_bit(config_word, 10) +-#define netxen_get_phy_resolved(config_word) \ +- _netxen_crb_get_bit(config_word, 11) +-#define netxen_get_phy_pagercvd(config_word) \ +- _netxen_crb_get_bit(config_word, 12) + #define netxen_get_phy_duplex(config_word) \ + _netxen_crb_get_bit(config_word, 13) +- +-/* +- * Interrupt Register definition +- * This definition applies to registers 18 and 19 (int enable and int status). +- * Bit 0 : jabber +- * Bit 1 : polarity_changed +- * Bit 4 : energy_detect +- * Bit 5 : downshift +- * Bit 6 : mdi_xover_changed +- * Bit 7 : fifo_over_underflow +- * Bit 8 : false_carrier +- * Bit 9 : symbol_error +- * Bit 10: link_status_changed +- * Bit 11: autoneg_completed +- * Bit 12: page_received +- * Bit 13: duplex_changed +- * Bit 14: speed_changed +- * Bit 15: autoneg_error +- */ +- +-#define netxen_get_phy_int_jabber(config_word) \ +- _netxen_crb_get_bit(config_word, 0) +-#define netxen_get_phy_int_polarity_changed(config_word) \ +- _netxen_crb_get_bit(config_word, 1) +-#define netxen_get_phy_int_energy_detect(config_word) \ +- _netxen_crb_get_bit(config_word, 4) +-#define netxen_get_phy_int_downshift(config_word) \ +- _netxen_crb_get_bit(config_word, 5) +-#define netxen_get_phy_int_mdi_xover_changed(config_word) \ +- _netxen_crb_get_bit(config_word, 6) +-#define netxen_get_phy_int_fifo_over_underflow(config_word) \ +- _netxen_crb_get_bit(config_word, 7) +-#define netxen_get_phy_int_false_carrier(config_word) \ +- _netxen_crb_get_bit(config_word, 8) +-#define netxen_get_phy_int_symbol_error(config_word) \ +- _netxen_crb_get_bit(config_word, 9) +-#define netxen_get_phy_int_link_status_changed(config_word) \ +- _netxen_crb_get_bit(config_word, 10) +-#define netxen_get_phy_int_autoneg_completed(config_word) \ +- _netxen_crb_get_bit(config_word, 11) +-#define netxen_get_phy_int_page_received(config_word) \ +- _netxen_crb_get_bit(config_word, 12) +-#define netxen_get_phy_int_duplex_changed(config_word) \ +- _netxen_crb_get_bit(config_word, 13) +-#define netxen_get_phy_int_speed_changed(config_word) \ +- _netxen_crb_get_bit(config_word, 14) +-#define netxen_get_phy_int_autoneg_error(config_word) \ +- _netxen_crb_get_bit(config_word, 15) +- +-#define netxen_set_phy_int_link_status_changed(config_word) \ +- ((config_word) |= 1 << 10) +-#define netxen_set_phy_int_autoneg_completed(config_word) \ +- ((config_word) |= 1 << 11) +-#define netxen_set_phy_int_speed_changed(config_word) \ +- ((config_word) |= 1 << 14) + + /* + * NIU Mode Register. +@@ -422,33 +256,6 @@ + #define NETXEN_NIU_NON_PROMISC_MODE 0 + #define NETXEN_NIU_PROMISC_MODE 1 + #define NETXEN_NIU_ALLMULTI_MODE 2 +- +-/* +- * NIU GB Drop CRC Register +- * +- * Bit 0 : drop_gb0 => 1:drop pkts with bad CRCs, 0:pass them on +- * Bit 1 : drop_gb1 => 1:drop pkts with bad CRCs, 0:pass them on +- * Bit 2 : drop_gb2 => 1:drop pkts with bad CRCs, 0:pass them on +- * Bit 3 : drop_gb3 => 1:drop pkts with bad CRCs, 0:pass them on +- */ +- +-#define netxen_set_gb_drop_gb0(config_word) \ +- ((config_word) |= 1 << 0) +-#define netxen_set_gb_drop_gb1(config_word) \ +- ((config_word) |= 1 << 1) +-#define netxen_set_gb_drop_gb2(config_word) \ +- ((config_word) |= 1 << 2) +-#define netxen_set_gb_drop_gb3(config_word) \ +- ((config_word) |= 1 << 3) +- +-#define netxen_clear_gb_drop_gb0(config_word) \ +- ((config_word) &= ~(1 << 0)) +-#define netxen_clear_gb_drop_gb1(config_word) \ +- ((config_word) &= ~(1 << 1)) +-#define netxen_clear_gb_drop_gb2(config_word) \ +- ((config_word) &= ~(1 << 2)) +-#define netxen_clear_gb_drop_gb3(config_word) \ +- ((config_word) &= ~(1 << 3)) + + /* + * NIU XG MAC Config Register +@@ -466,30 +273,6 @@ + #define netxen_xg_soft_reset(config_word) \ + ((config_word) |= 1 << 4) + +-/* Set promiscuous mode for a GbE interface */ +-int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter, +- u32 mode); +-int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter, +- u32 mode); +- +-/* set the MAC address for a given MAC */ +-int netxen_niu_macaddr_set(struct netxen_adapter *adapter, +- netxen_ethernet_macaddr_t addr); +- +-/* XG version */ +-int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter, +- netxen_ethernet_macaddr_t addr); +- +-/* Generic enable for GbE ports. Will detect the speed of the link. */ +-int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port); +- +-int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port); +- +-/* Disable a GbE interface */ +-int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter); +- +-int netxen_niu_disable_xg_port(struct netxen_adapter *adapter); +- + typedef struct { + unsigned valid; + unsigned start_128M; +diff -r 6335373db0ec drivers/net/netxen/netxen_nic_init.c +--- a/drivers/net/netxen/netxen_nic_init.c Thu Oct 01 10:10:06 2009 +0100 ++++ b/drivers/net/netxen/netxen_nic_init.c Mon Oct 05 17:00:12 2009 +0100 +@@ -1,5 +1,6 @@ + /* +- * Copyright (C) 2003 - 2006 NetXen, Inc. ++ * Copyright (C) 2003 - 2009 NetXen, Inc. ++ * Copyright (C) 2009 - QLogic Corporation. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or +@@ -20,22 +21,12 @@ + * The full GNU General Public License is included in this distribution + * in the file called LICENSE. + * +- * Contact Information: +- * info@netxen.com +- * NetXen, +- * 3965 Freedom Circle, Fourth floor, +- * Santa Clara, CA 95054 +- * +- * +- * Source file for NIC routines to initialize the Phantom Hardware +- * + */ + + #include + #include + #include "netxen_nic.h" + #include "netxen_nic_hw.h" +-#include "netxen_nic_phan_reg.h" + + struct crb_addr_pair { + u32 addr; +@@ -52,17 +43,9 @@ + + #define NETXEN_NIC_XDMA_RESET 0x8000ff + +-static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, +- uint32_t ctx, uint32_t ringid); +- +-#if 0 +-static void netxen_nic_locked_write_reg(struct netxen_adapter *adapter, +- unsigned long off, int *data) +-{ +- void __iomem *addr = pci_base_offset(adapter, off); +- writel(*data, addr); +-} +-#endif /* 0 */ ++static void ++netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, ++ struct nx_host_rds_ring *rds_ring); + + static void crb_addr_transform_setup(void) + { +@@ -119,64 +102,26 @@ + crb_addr_transform(I2C0); + } + +-int netxen_init_firmware(struct netxen_adapter *adapter) +-{ +- u32 state = 0, loops = 0, err = 0; +- +- /* Window 1 call */ +- state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE); +- +- if (state == PHAN_INITIALIZE_ACK) +- return 0; +- +- while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) { +- msleep(1); +- /* Window 1 call */ +- state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE); +- +- loops++; +- } +- if (loops >= 2000) { +- printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n", +- state); +- err = -EIO; +- return err; +- } +- /* Window 1 call */ +- adapter->pci_write_normalize(adapter, +- CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT); +- adapter->pci_write_normalize(adapter, +- CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC); +- adapter->pci_write_normalize(adapter, +- CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE); +- adapter->pci_write_normalize(adapter, +- CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK); +- +- return err; +-} +- + void netxen_release_rx_buffers(struct netxen_adapter *adapter) + { + struct netxen_recv_context *recv_ctx; + struct nx_host_rds_ring *rds_ring; + struct netxen_rx_buffer *rx_buf; +- int i, ctxid, ring; ++ int i, ring; + +- for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) { +- recv_ctx = &adapter->recv_ctx[ctxid]; +- for (ring = 0; ring < adapter->max_rds_rings; ring++) { +- rds_ring = &recv_ctx->rds_rings[ring]; +- for (i = 0; i < rds_ring->max_rx_desc_count; ++i) { +- rx_buf = &(rds_ring->rx_buf_arr[i]); +- if (rx_buf->state == NETXEN_BUFFER_FREE) +- continue; +- pci_unmap_single(adapter->pdev, +- rx_buf->dma, +- rds_ring->dma_size, +- PCI_DMA_FROMDEVICE); +- if (rx_buf->skb != NULL) +- dev_kfree_skb_any(rx_buf->skb); +- } ++ recv_ctx = &adapter->recv_ctx; ++ for (ring = 0; ring < adapter->max_rds_rings; ring++) { ++ rds_ring = &recv_ctx->rds_rings[ring]; ++ for (i = 0; i < rds_ring->num_desc; ++i) { ++ rx_buf = &(rds_ring->rx_buf_arr[i]); ++ if (rx_buf->state == NETXEN_BUFFER_FREE) ++ continue; ++ pci_unmap_single(adapter->pdev, ++ rx_buf->dma, ++ rds_ring->dma_size, ++ PCI_DMA_FROMDEVICE); ++ if (rx_buf->skb != NULL) ++ dev_kfree_skb_any(rx_buf->skb); + } + } + } +@@ -186,9 +131,10 @@ + struct netxen_cmd_buffer *cmd_buf; + struct netxen_skb_frag *buffrag; + int i, j; ++ struct nx_host_tx_ring *tx_ring = adapter->tx_ring; + +- cmd_buf = adapter->cmd_buf_arr; +- for (i = 0; i < adapter->max_tx_desc_count; i++) { ++ cmd_buf = tx_ring->cmd_buf_arr; ++ for (i = 0; i < tx_ring->num_desc; i++) { + buffrag = cmd_buf->frag_array; + if (buffrag->dma) { + pci_unmap_single(adapter->pdev, buffrag->dma, +@@ -204,7 +150,6 @@ + buffrag->dma = 0ULL; + } + } +- /* Free the skb we received in netxen_nic_xmit_frame */ + if (cmd_buf->skb) { + dev_kfree_skb_any(cmd_buf->skb); + cmd_buf->skb = NULL; +@@ -217,111 +162,153 @@ + { + struct netxen_recv_context *recv_ctx; + struct nx_host_rds_ring *rds_ring; +- int ctx, ring; ++ struct nx_host_tx_ring *tx_ring; ++ int ring; + +- for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) { +- recv_ctx = &adapter->recv_ctx[ctx]; +- for (ring = 0; ring < adapter->max_rds_rings; ring++) { +- rds_ring = &recv_ctx->rds_rings[ring]; +- if (rds_ring->rx_buf_arr) { +- vfree(rds_ring->rx_buf_arr); +- rds_ring->rx_buf_arr = NULL; +- } +- } ++ recv_ctx = &adapter->recv_ctx; ++ ++ if (recv_ctx->rds_rings == NULL) ++ goto skip_rds; ++ ++ for (ring = 0; ring < adapter->max_rds_rings; ring++) { ++ rds_ring = &recv_ctx->rds_rings[ring]; ++ vfree(rds_ring->rx_buf_arr); ++ rds_ring->rx_buf_arr = NULL; + } +- if (adapter->cmd_buf_arr) +- vfree(adapter->cmd_buf_arr); +- return; ++ kfree(recv_ctx->rds_rings); ++ ++skip_rds: ++ if (adapter->tx_ring == NULL) ++ return; ++ ++ tx_ring = adapter->tx_ring; ++ vfree(tx_ring->cmd_buf_arr); + } + + int netxen_alloc_sw_resources(struct netxen_adapter *adapter) + { + struct netxen_recv_context *recv_ctx; + struct nx_host_rds_ring *rds_ring; ++ struct nx_host_sds_ring *sds_ring; ++ struct nx_host_tx_ring *tx_ring; + struct netxen_rx_buffer *rx_buf; +- int ctx, ring, i, num_rx_bufs; ++ int ring, i, size; + + struct netxen_cmd_buffer *cmd_buf_arr; + struct net_device *netdev = adapter->netdev; ++ struct pci_dev *pdev = adapter->pdev; + +- cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE); +- if (cmd_buf_arr == NULL) { +- printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n", ++ size = sizeof(struct nx_host_tx_ring); ++ tx_ring = kzalloc(size, GFP_KERNEL); ++ if (tx_ring == NULL) { ++ dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n", + netdev->name); + return -ENOMEM; + } +- memset(cmd_buf_arr, 0, TX_RINGSIZE); +- adapter->cmd_buf_arr = cmd_buf_arr; ++ adapter->tx_ring = tx_ring; + +- for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) { +- recv_ctx = &adapter->recv_ctx[ctx]; +- for (ring = 0; ring < adapter->max_rds_rings; ring++) { +- rds_ring = &recv_ctx->rds_rings[ring]; +- switch (RCV_DESC_TYPE(ring)) { +- case RCV_DESC_NORMAL: +- rds_ring->max_rx_desc_count = +- adapter->max_rx_desc_count; +- rds_ring->flags = RCV_DESC_NORMAL; +- if (adapter->ahw.cut_through) { +- rds_ring->dma_size = +- NX_CT_DEFAULT_RX_BUF_LEN; +- rds_ring->skb_size = +- NX_CT_DEFAULT_RX_BUF_LEN; +- } else { +- rds_ring->dma_size = RX_DMA_MAP_LEN; +- rds_ring->skb_size = +- MAX_RX_BUFFER_LENGTH; +- } +- break; ++ tx_ring->num_desc = adapter->num_txd; ++ tx_ring->txq = netdev_get_tx_queue(netdev, 0); + +- case RCV_DESC_JUMBO: +- rds_ring->max_rx_desc_count = +- adapter->max_jumbo_rx_desc_count; +- rds_ring->flags = RCV_DESC_JUMBO; ++ cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring)); ++ if (cmd_buf_arr == NULL) { ++ dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n", ++ netdev->name); ++ return -ENOMEM; ++ } ++ memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring)); ++ tx_ring->cmd_buf_arr = cmd_buf_arr; ++ ++ recv_ctx = &adapter->recv_ctx; ++ ++ size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring); ++ rds_ring = kzalloc(size, GFP_KERNEL); ++ if (rds_ring == NULL) { ++ dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n", ++ netdev->name); ++ return -ENOMEM; ++ } ++ recv_ctx->rds_rings = rds_ring; ++ ++ for (ring = 0; ring < adapter->max_rds_rings; ring++) { ++ rds_ring = &recv_ctx->rds_rings[ring]; ++ switch (ring) { ++ case RCV_RING_NORMAL: ++ rds_ring->num_desc = adapter->num_rxd; ++ if (adapter->ahw.cut_through) { ++ rds_ring->dma_size = ++ NX_CT_DEFAULT_RX_BUF_LEN; ++ rds_ring->skb_size = ++ NX_CT_DEFAULT_RX_BUF_LEN; ++ } else { + if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) + rds_ring->dma_size = +- NX_P3_RX_JUMBO_BUF_MAX_LEN; ++ NX_P3_RX_BUF_MAX_LEN; + else + rds_ring->dma_size = +- NX_P2_RX_JUMBO_BUF_MAX_LEN; ++ NX_P2_RX_BUF_MAX_LEN; + rds_ring->skb_size = + rds_ring->dma_size + NET_IP_ALIGN; +- break; ++ } ++ break; + +- case RCV_RING_LRO: +- rds_ring->max_rx_desc_count = +- adapter->max_lro_rx_desc_count; +- rds_ring->flags = RCV_DESC_LRO; +- rds_ring->dma_size = RX_LRO_DMA_MAP_LEN; +- rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH; +- break; ++ case RCV_RING_JUMBO: ++ rds_ring->num_desc = adapter->num_jumbo_rxd; ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) ++ rds_ring->dma_size = ++ NX_P3_RX_JUMBO_BUF_MAX_LEN; ++ else ++ rds_ring->dma_size = ++ NX_P2_RX_JUMBO_BUF_MAX_LEN; + +- } +- rds_ring->rx_buf_arr = (struct netxen_rx_buffer *) +- vmalloc(RCV_BUFFSIZE); +- if (rds_ring->rx_buf_arr == NULL) { +- printk(KERN_ERR "%s: Failed to allocate " +- "rx buffer ring %d\n", +- netdev->name, ring); +- /* free whatever was already allocated */ +- goto err_out; +- } +- memset(rds_ring->rx_buf_arr, 0, RCV_BUFFSIZE); +- INIT_LIST_HEAD(&rds_ring->free_list); +- /* +- * Now go through all of them, set reference handles +- * and put them in the queues. +- */ +- num_rx_bufs = rds_ring->max_rx_desc_count; +- rx_buf = rds_ring->rx_buf_arr; +- for (i = 0; i < num_rx_bufs; i++) { +- list_add_tail(&rx_buf->list, +- &rds_ring->free_list); +- rx_buf->ref_handle = i; +- rx_buf->state = NETXEN_BUFFER_FREE; +- rx_buf++; +- } ++ if (adapter->capabilities & NX_CAP0_HW_LRO) ++ rds_ring->dma_size += NX_LRO_BUFFER_EXTRA; ++ ++ rds_ring->skb_size = ++ rds_ring->dma_size + NET_IP_ALIGN; ++ break; ++ ++ case RCV_RING_LRO: ++ rds_ring->num_desc = adapter->num_lro_rxd; ++ rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH; ++ rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN; ++ break; ++ + } ++ rds_ring->rx_buf_arr = (struct netxen_rx_buffer *) ++ vmalloc(RCV_BUFF_RINGSIZE(rds_ring)); ++ if (rds_ring->rx_buf_arr == NULL) { ++ printk(KERN_ERR "%s: Failed to allocate " ++ "rx buffer ring %d\n", ++ netdev->name, ring); ++ /* free whatever was already allocated */ ++ goto err_out; ++ } ++ memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring)); ++ INIT_LIST_HEAD(&rds_ring->free_list); ++ /* ++ * Now go through all of them, set reference handles ++ * and put them in the queues. ++ */ ++ rx_buf = rds_ring->rx_buf_arr; ++ for (i = 0; i < rds_ring->num_desc; i++) { ++ list_add_tail(&rx_buf->list, ++ &rds_ring->free_list); ++ rx_buf->ref_handle = i; ++ rx_buf->state = NETXEN_BUFFER_FREE; ++ rx_buf++; ++ } ++ spin_lock_init(&rds_ring->lock); ++ } ++ ++ for (ring = 0; ring < adapter->max_sds_rings; ring++) { ++ sds_ring = &recv_ctx->sds_rings[ring]; ++ sds_ring->irq = adapter->msix_entries[ring].vector; ++ sds_ring->adapter = adapter; ++ sds_ring->num_desc = adapter->num_rxd; ++ ++ for (i = 0; i < NUM_RCV_DESC_RINGS; i++) ++ INIT_LIST_HEAD(&sds_ring->free_list[i]); + } + + return 0; +@@ -329,45 +316,6 @@ + err_out: + netxen_free_sw_resources(adapter); + return -ENOMEM; +-} +- +-void netxen_initialize_adapter_ops(struct netxen_adapter *adapter) +-{ +- switch (adapter->ahw.board_type) { +- case NETXEN_NIC_GBE: +- adapter->enable_phy_interrupts = +- netxen_niu_gbe_enable_phy_interrupts; +- adapter->disable_phy_interrupts = +- netxen_niu_gbe_disable_phy_interrupts; +- adapter->macaddr_set = netxen_niu_macaddr_set; +- adapter->set_mtu = netxen_nic_set_mtu_gb; +- adapter->set_promisc = netxen_niu_set_promiscuous_mode; +- adapter->phy_read = netxen_niu_gbe_phy_read; +- adapter->phy_write = netxen_niu_gbe_phy_write; +- adapter->init_port = netxen_niu_gbe_init_port; +- adapter->stop_port = netxen_niu_disable_gbe_port; +- break; +- +- case NETXEN_NIC_XGBE: +- adapter->enable_phy_interrupts = +- netxen_niu_xgbe_enable_phy_interrupts; +- adapter->disable_phy_interrupts = +- netxen_niu_xgbe_disable_phy_interrupts; +- adapter->macaddr_set = netxen_niu_xg_macaddr_set; +- adapter->set_mtu = netxen_nic_set_mtu_xgb; +- adapter->init_port = netxen_niu_xg_init_port; +- adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode; +- adapter->stop_port = netxen_niu_disable_xg_port; +- break; +- +- default: +- break; +- } +- +- if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { +- adapter->set_mtu = nx_fw_cmd_set_mtu; +- adapter->set_promisc = netxen_p3_nic_set_promisc; +- } + } + + /* +@@ -397,41 +345,7 @@ + return (pci_base + offset); + } + +-static long rom_max_timeout = 100; +-static long rom_lock_timeout = 10000; +-#if 0 +-static long rom_write_timeout = 700; +-#endif +- +-static int rom_lock(struct netxen_adapter *adapter) +-{ +- int iter; +- u32 done = 0; +- int timeout = 0; +- +- while (!done) { +- /* acquire semaphore2 from PCI HW block */ +- netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK), +- &done); +- if (done == 1) +- break; +- if (timeout >= rom_lock_timeout) +- return -EIO; +- +- timeout++; +- /* +- * Yield CPU +- */ +- if (!in_atomic()) +- schedule(); +- else { +- for (iter = 0; iter < 20; iter++) +- cpu_relax(); /*This a nop instr on i386 */ +- } +- } +- netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER); +- return 0; +-} ++#define NETXEN_MAX_ROM_WAIT_USEC 100 + + static int netxen_wait_rom_done(struct netxen_adapter *adapter) + { +@@ -441,113 +355,35 @@ + cond_resched(); + + while (done == 0) { +- done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS); ++ done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS); + done &= 2; +- timeout++; +- if (timeout >= rom_max_timeout) { +- printk("Timeout reached waiting for rom done"); ++ if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) { ++ dev_err(&adapter->pdev->dev, ++ "Timeout reached waiting for rom done"); + return -EIO; + } ++ udelay(1); + } + return 0; + } + +-#if 0 +-static int netxen_rom_wren(struct netxen_adapter *adapter) +-{ +- /* Set write enable latch in ROM status register */ +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, +- M25P_INSTR_WREN); +- if (netxen_wait_rom_done(adapter)) { +- return -1; +- } +- return 0; +-} +- +-static unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter, +- unsigned int addr) +-{ +- unsigned int data = 0xdeaddead; +- data = netxen_nic_reg_read(adapter, addr); +- return data; +-} +- +-static int netxen_do_rom_rdsr(struct netxen_adapter *adapter) +-{ +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, +- M25P_INSTR_RDSR); +- if (netxen_wait_rom_done(adapter)) { +- return -1; +- } +- return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA); +-} +-#endif +- +-static void netxen_rom_unlock(struct netxen_adapter *adapter) +-{ +- u32 val; +- +- /* release semaphore2 */ +- netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val); +- +-} +- +-#if 0 +-static int netxen_rom_wip_poll(struct netxen_adapter *adapter) +-{ +- long timeout = 0; +- long wip = 1; +- int val; +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); +- while (wip != 0) { +- val = netxen_do_rom_rdsr(adapter); +- wip = val & 1; +- timeout++; +- if (timeout > rom_max_timeout) { +- return -1; +- } +- } +- return 0; +-} +- +-static int do_rom_fast_write(struct netxen_adapter *adapter, int addr, +- int data) +-{ +- if (netxen_rom_wren(adapter)) { +- return -1; +- } +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data); +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, +- M25P_INSTR_PP); +- if (netxen_wait_rom_done(adapter)) { +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); +- return -1; +- } +- +- return netxen_rom_wip_poll(adapter); +-} +-#endif +- + static int do_rom_fast_read(struct netxen_adapter *adapter, + int addr, int *valp) + { +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb); ++ NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); ++ NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); ++ NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); ++ NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb); + if (netxen_wait_rom_done(adapter)) { + printk("Error waiting for rom done\n"); + return -EIO; + } + /* reset abyte_cnt and dummy_byte_cnt */ +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); ++ NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); + udelay(10); +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); ++ NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); + +- *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA); ++ *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA); + return 0; + } + +@@ -575,7 +411,7 @@ + { + int ret; + +- ret = rom_lock(adapter); ++ ret = netxen_rom_lock(adapter); + if (ret < 0) + return ret; + +@@ -589,291 +425,13 @@ + { + int ret; + +- if (rom_lock(adapter) != 0) ++ if (netxen_rom_lock(adapter) != 0) + return -EIO; + + ret = do_rom_fast_read(adapter, addr, valp); + netxen_rom_unlock(adapter); + return ret; + } +- +-#if 0 +-int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data) +-{ +- int ret = 0; +- +- if (rom_lock(adapter) != 0) { +- return -1; +- } +- ret = do_rom_fast_write(adapter, addr, data); +- netxen_rom_unlock(adapter); +- return ret; +-} +- +-static int do_rom_fast_write_words(struct netxen_adapter *adapter, +- int addr, u8 *bytes, size_t size) +-{ +- int addridx = addr; +- int ret = 0; +- +- while (addridx < (addr + size)) { +- int last_attempt = 0; +- int timeout = 0; +- int data; +- +- data = le32_to_cpu((*(__le32*)bytes)); +- ret = do_rom_fast_write(adapter, addridx, data); +- if (ret < 0) +- return ret; +- +- while(1) { +- int data1; +- +- ret = do_rom_fast_read(adapter, addridx, &data1); +- if (ret < 0) +- return ret; +- +- if (data1 == data) +- break; +- +- if (timeout++ >= rom_write_timeout) { +- if (last_attempt++ < 4) { +- ret = do_rom_fast_write(adapter, +- addridx, data); +- if (ret < 0) +- return ret; +- } +- else { +- printk(KERN_INFO "Data write did not " +- "succeed at address 0x%x\n", addridx); +- break; +- } +- } +- } +- +- bytes += 4; +- addridx += 4; +- } +- +- return ret; +-} +- +-int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr, +- u8 *bytes, size_t size) +-{ +- int ret = 0; +- +- ret = rom_lock(adapter); +- if (ret < 0) +- return ret; +- +- ret = do_rom_fast_write_words(adapter, addr, bytes, size); +- netxen_rom_unlock(adapter); +- +- return ret; +-} +- +-static int netxen_rom_wrsr(struct netxen_adapter *adapter, int data) +-{ +- int ret; +- +- ret = netxen_rom_wren(adapter); +- if (ret < 0) +- return ret; +- +- netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1); +- +- ret = netxen_wait_rom_done(adapter); +- if (ret < 0) +- return ret; +- +- return netxen_rom_wip_poll(adapter); +-} +- +-static int netxen_rom_rdsr(struct netxen_adapter *adapter) +-{ +- int ret; +- +- ret = rom_lock(adapter); +- if (ret < 0) +- return ret; +- +- ret = netxen_do_rom_rdsr(adapter); +- netxen_rom_unlock(adapter); +- return ret; +-} +- +-int netxen_backup_crbinit(struct netxen_adapter *adapter) +-{ +- int ret = FLASH_SUCCESS; +- int val; +- char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL); +- +- if (!buffer) +- return -ENOMEM; +- /* unlock sector 63 */ +- val = netxen_rom_rdsr(adapter); +- val = val & 0xe3; +- ret = netxen_rom_wrsr(adapter, val); +- if (ret != FLASH_SUCCESS) +- goto out_kfree; +- +- ret = netxen_rom_wip_poll(adapter); +- if (ret != FLASH_SUCCESS) +- goto out_kfree; +- +- /* copy sector 0 to sector 63 */ +- ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START, +- buffer, NETXEN_FLASH_SECTOR_SIZE); +- if (ret != FLASH_SUCCESS) +- goto out_kfree; +- +- ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START, +- buffer, NETXEN_FLASH_SECTOR_SIZE); +- if (ret != FLASH_SUCCESS) +- goto out_kfree; +- +- /* lock sector 63 */ +- val = netxen_rom_rdsr(adapter); +- if (!(val & 0x8)) { +- val |= (0x1 << 2); +- /* lock sector 63 */ +- if (netxen_rom_wrsr(adapter, val) == 0) { +- ret = netxen_rom_wip_poll(adapter); +- if (ret != FLASH_SUCCESS) +- goto out_kfree; +- +- /* lock SR writes */ +- ret = netxen_rom_wip_poll(adapter); +- if (ret != FLASH_SUCCESS) +- goto out_kfree; +- } +- } +- +-out_kfree: +- kfree(buffer); +- return ret; +-} +- +-static int netxen_do_rom_se(struct netxen_adapter *adapter, int addr) +-{ +- netxen_rom_wren(adapter); +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, +- M25P_INSTR_SE); +- if (netxen_wait_rom_done(adapter)) { +- netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); +- return -1; +- } +- return netxen_rom_wip_poll(adapter); +-} +- +-static void check_erased_flash(struct netxen_adapter *adapter, int addr) +-{ +- int i; +- int val; +- int count = 0, erased_errors = 0; +- int range; +- +- range = (addr == NETXEN_USER_START) ? +- NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE; +- +- for (i = addr; i < range; i += 4) { +- netxen_rom_fast_read(adapter, i, &val); +- if (val != 0xffffffff) +- erased_errors++; +- count++; +- } +- +- if (erased_errors) +- printk(KERN_INFO "0x%x out of 0x%x words fail to be erased " +- "for sector address: %x\n", erased_errors, count, addr); +-} +- +-int netxen_rom_se(struct netxen_adapter *adapter, int addr) +-{ +- int ret = 0; +- if (rom_lock(adapter) != 0) { +- return -1; +- } +- ret = netxen_do_rom_se(adapter, addr); +- netxen_rom_unlock(adapter); +- msleep(30); +- check_erased_flash(adapter, addr); +- +- return ret; +-} +- +-static int netxen_flash_erase_sections(struct netxen_adapter *adapter, +- int start, int end) +-{ +- int ret = FLASH_SUCCESS; +- int i; +- +- for (i = start; i < end; i++) { +- ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE); +- if (ret) +- break; +- ret = netxen_rom_wip_poll(adapter); +- if (ret < 0) +- return ret; +- } +- +- return ret; +-} +- +-int +-netxen_flash_erase_secondary(struct netxen_adapter *adapter) +-{ +- int ret = FLASH_SUCCESS; +- int start, end; +- +- start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE; +- end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE; +- ret = netxen_flash_erase_sections(adapter, start, end); +- +- return ret; +-} +- +-int +-netxen_flash_erase_primary(struct netxen_adapter *adapter) +-{ +- int ret = FLASH_SUCCESS; +- int start, end; +- +- start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE; +- end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE; +- ret = netxen_flash_erase_sections(adapter, start, end); +- +- return ret; +-} +- +-void netxen_halt_pegs(struct netxen_adapter *adapter) +-{ +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1); +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1); +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1); +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1); +-} +- +-int netxen_flash_unlock(struct netxen_adapter *adapter) +-{ +- int ret = 0; +- +- ret = netxen_rom_wrsr(adapter, 0); +- if (ret < 0) +- return ret; +- +- ret = netxen_rom_wren(adapter); +- if (ret < 0) +- return ret; +- +- return ret; +-} +-#endif /* 0 */ + + #define NETXEN_BOARDTYPE 0x4008 + #define NETXEN_BOARDNUM 0x400c +@@ -888,9 +446,8 @@ + u32 off; + + /* resetall */ +- rom_lock(adapter); +- netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET, +- 0xffffffff); ++ netxen_rom_lock(adapter); ++ NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff); + netxen_rom_unlock(adapter); + + if (verbose) { +@@ -1014,7 +571,7 @@ + } + } + +- adapter->hw_write_wx(adapter, off, &buf[i].data, 4); ++ NXWR32(adapter, off, buf[i].data); + + msleep(init_delay); + } +@@ -1024,49 +581,326 @@ + + /* unreset_net_cache */ + if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { +- adapter->hw_read_wx(adapter, +- NETXEN_ROMUSB_GLB_SW_RESET, &val, 4); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f)); ++ val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET); ++ NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f)); + } + + /* p2dn replyCount */ +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e); ++ NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e); + /* disable_peg_cache 0 */ +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8); ++ NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8); + /* disable_peg_cache 1 */ +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8); ++ NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8); + + /* peg_clr_all */ + + /* peg_clr 0 */ +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0); +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0); ++ NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0); ++ NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0); + /* peg_clr 1 */ +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0); +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0); ++ NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0); ++ NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0); + /* peg_clr 2 */ +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0); +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0); ++ NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0); ++ NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0); + /* peg_clr 3 */ +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0); +- netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0); ++ NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0); ++ NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0); + return 0; + } + +-int netxen_initialize_adapter_offload(struct netxen_adapter *adapter) ++int ++netxen_need_fw_reset(struct netxen_adapter *adapter) + { +- uint64_t addr; +- uint32_t hi; +- uint32_t lo; ++ u32 count, old_count; ++ u32 val, version, major, minor, build; ++ int i, timeout; ++ u8 fw_type; + +- adapter->dummy_dma.addr = +- pci_alloc_consistent(adapter->pdev, ++ /* NX2031 firmware doesn't support heartbit */ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ++ return 1; ++ ++ /* last attempt had failed */ ++ if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED) ++ return 1; ++ ++ old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER); ++ ++ for (i = 0; i < 10; i++) { ++ ++ timeout = msleep_interruptible(200); ++ if (timeout) { ++ NXWR32(adapter, CRB_CMDPEG_STATE, ++ PHAN_INITIALIZE_FAILED); ++ return -EINTR; ++ } ++ ++ count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER); ++ if (count != old_count) ++ break; ++ } ++ ++ /* firmware is dead */ ++ if (count == old_count) ++ return 1; ++ ++ /* check if we have got newer or different file firmware */ ++ if (adapter->fw) { ++ ++ const struct firmware *fw = adapter->fw; ++ ++ val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]); ++ version = NETXEN_DECODE_VERSION(val); ++ ++ major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR); ++ minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR); ++ build = NXRD32(adapter, NETXEN_FW_VERSION_SUB); ++ ++ if (version > NETXEN_VERSION_CODE(major, minor, build)) ++ return 1; ++ ++ if (version == NETXEN_VERSION_CODE(major, minor, build)) { ++ ++ val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL); ++ fw_type = (val & 0x4) ? ++ NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE; ++ ++ if (adapter->fw_type != fw_type) ++ return 1; ++ } ++ } ++ ++ return 0; ++} ++ ++static char *fw_name[] = { ++ "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash", ++}; ++ ++int ++netxen_load_firmware(struct netxen_adapter *adapter) ++{ ++ u64 *ptr64; ++ u32 i, flashaddr, size; ++ const struct firmware *fw = adapter->fw; ++ struct pci_dev *pdev = adapter->pdev; ++ ++ dev_info(&pdev->dev, "loading firmware from %s\n", ++ fw_name[adapter->fw_type]); ++ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ++ NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1); ++ ++ if (fw) { ++ __le64 data; ++ ++ size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8; ++ ++ ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START]; ++ flashaddr = NETXEN_BOOTLD_START; ++ ++ for (i = 0; i < size; i++) { ++ data = cpu_to_le64(ptr64[i]); ++ adapter->pci_mem_write(adapter, flashaddr, &data, 8); ++ flashaddr += 8; ++ } ++ ++ size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET]; ++ size = (__force u32)cpu_to_le32(size) / 8; ++ ++ ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START]; ++ flashaddr = NETXEN_IMAGE_START; ++ ++ for (i = 0; i < size; i++) { ++ data = cpu_to_le64(ptr64[i]); ++ ++ if (adapter->pci_mem_write(adapter, ++ flashaddr, &data, 8)) ++ return -EIO; ++ ++ flashaddr += 8; ++ } ++ } else { ++ u64 data; ++ u32 hi, lo; ++ ++ size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8; ++ flashaddr = NETXEN_BOOTLD_START; ++ ++ for (i = 0; i < size; i++) { ++ if (netxen_rom_fast_read(adapter, ++ flashaddr, &lo) != 0) ++ return -EIO; ++ if (netxen_rom_fast_read(adapter, ++ flashaddr + 4, &hi) != 0) ++ return -EIO; ++ ++ /* hi, lo are already in host endian byteorder */ ++ data = (((u64)hi << 32) | lo); ++ ++ if (adapter->pci_mem_write(adapter, ++ flashaddr, &data, 8)) ++ return -EIO; ++ ++ flashaddr += 8; ++ } ++ } ++ msleep(1); ++ ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) ++ NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d); ++ else { ++ NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff); ++ NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0); ++ } ++ ++ return 0; ++} ++ ++static int ++netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname) ++{ ++ __le32 val; ++ u32 ver, min_ver, bios; ++ struct pci_dev *pdev = adapter->pdev; ++ const struct firmware *fw = adapter->fw; ++ ++ if (fw->size < NX_FW_MIN_SIZE) ++ return -EINVAL; ++ ++ val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]); ++ if ((__force u32)val != NETXEN_BDINFO_MAGIC) ++ return -EINVAL; ++ ++ val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]); ++ ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) ++ min_ver = NETXEN_VERSION_CODE(4, 0, 216); ++ else ++ min_ver = NETXEN_VERSION_CODE(3, 4, 216); ++ ++ ver = NETXEN_DECODE_VERSION(val); ++ ++ if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) { ++ dev_err(&pdev->dev, ++ "%s: firmware version %d.%d.%d unsupported\n", ++ fwname, _major(ver), _minor(ver), _build(ver)); ++ return -EINVAL; ++ } ++ ++ val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]); ++ netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios); ++ if ((__force u32)val != bios) { ++ dev_err(&pdev->dev, "%s: firmware bios is incompatible\n", ++ fwname); ++ return -EINVAL; ++ } ++ ++ /* check if flashed firmware is newer */ ++ if (netxen_rom_fast_read(adapter, ++ NX_FW_VERSION_OFFSET, (int *)&val)) ++ return -EIO; ++ val = NETXEN_DECODE_VERSION(val); ++ if (val > ver) { ++ dev_info(&pdev->dev, "%s: firmware is older than flash\n", ++ fwname); ++ return -EINVAL; ++ } ++ ++ NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC); ++ return 0; ++} ++ ++static int ++netxen_p3_has_mn(struct netxen_adapter *adapter) ++{ ++ u32 capability, flashed_ver; ++ capability = 0; ++ ++ netxen_rom_fast_read(adapter, ++ NX_FW_VERSION_OFFSET, (int *)&flashed_ver); ++ flashed_ver = NETXEN_DECODE_VERSION(flashed_ver); ++ ++ if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) { ++ ++ capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY); ++ if (capability & NX_PEG_TUNE_MN_PRESENT) ++ return 1; ++ } ++ return 0; ++} ++ ++void netxen_request_firmware(struct netxen_adapter *adapter) ++{ ++ u8 fw_type; ++ struct pci_dev *pdev = adapter->pdev; ++ int rc = 0; ++ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { ++ fw_type = NX_P2_MN_ROMIMAGE; ++ goto request_fw; ++ } ++ ++ fw_type = netxen_p3_has_mn(adapter) ? ++ NX_P3_MN_ROMIMAGE : NX_P3_CT_ROMIMAGE; ++ ++request_fw: ++ rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev); ++ if (rc != 0) { ++ if (fw_type == NX_P3_MN_ROMIMAGE) { ++ msleep(1); ++ fw_type = NX_P3_CT_ROMIMAGE; ++ goto request_fw; ++ } ++ ++ fw_type = NX_FLASH_ROMIMAGE; ++ adapter->fw = NULL; ++ goto done; ++ } ++ ++ rc = netxen_validate_firmware(adapter, fw_name[fw_type]); ++ if (rc != 0) { ++ release_firmware(adapter->fw); ++ ++ if (fw_type == NX_P3_MN_ROMIMAGE) { ++ msleep(1); ++ fw_type = NX_P3_CT_ROMIMAGE; ++ goto request_fw; ++ } ++ ++ fw_type = NX_FLASH_ROMIMAGE; ++ adapter->fw = NULL; ++ goto done; ++ } ++ ++done: ++ adapter->fw_type = fw_type; ++} ++ ++ ++void ++netxen_release_firmware(struct netxen_adapter *adapter) ++{ ++ if (adapter->fw) ++ release_firmware(adapter->fw); ++ adapter->fw = NULL; ++} ++ ++int netxen_init_dummy_dma(struct netxen_adapter *adapter) ++{ ++ u64 addr; ++ u32 hi, lo; ++ ++ if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) ++ return 0; ++ ++ adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev, + NETXEN_HOST_DUMMY_DMA_SIZE, + &adapter->dummy_dma.phys_addr); + if (adapter->dummy_dma.addr == NULL) { +- printk("%s: ERROR: Could not allocate dummy DMA memory\n", +- __func__); ++ dev_err(&adapter->pdev->dev, ++ "ERROR: Could not allocate dummy DMA memory\n"); + return -ENOMEM; + } + +@@ -1074,32 +908,44 @@ + hi = (addr >> 32) & 0xffffffff; + lo = addr & 0xffffffff; + +- adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi); +- adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo); +- +- if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { +- uint32_t temp = 0; +- adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4); +- } ++ NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi); ++ NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo); + + return 0; + } + +-void netxen_free_adapter_offload(struct netxen_adapter *adapter) ++/* ++ * NetXen DMA watchdog control: ++ * ++ * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive ++ * Bit 1 : disable_request => 1 req disable dma watchdog ++ * Bit 2 : enable_request => 1 req enable dma watchdog ++ * Bit 3-31 : unused ++ */ ++void netxen_free_dummy_dma(struct netxen_adapter *adapter) + { + int i = 100; ++ u32 ctrl; ++ ++ if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) ++ return; + + if (!adapter->dummy_dma.addr) + return; + +- if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { +- do { +- if (dma_watchdog_shutdown_request(adapter) == 1) ++ ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL); ++ if ((ctrl & 0x1) != 0) { ++ NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2)); ++ ++ while ((ctrl & 0x1) != 0) { ++ ++ msleep(50); ++ ++ ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL); ++ ++ if (--i == 0) + break; +- msleep(50); +- if (dma_watchdog_shutdown_poll_result(adapter) == 1) +- break; +- } while (--i); ++ }; + } + + if (i) { +@@ -1108,10 +954,8 @@ + adapter->dummy_dma.addr, + adapter->dummy_dma.phys_addr); + adapter->dummy_dma.addr = NULL; +- } else { +- printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n", +- adapter->netdev->name); +- } ++ } else ++ dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n"); + } + + int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val) +@@ -1119,38 +963,41 @@ + u32 val = 0; + int retries = 60; + +- if (!pegtune_val) { +- do { +- val = adapter->pci_read_normalize(adapter, +- CRB_CMDPEG_STATE); ++ if (pegtune_val) ++ return 0; + +- if (val == PHAN_INITIALIZE_COMPLETE || +- val == PHAN_INITIALIZE_ACK) +- return 0; ++ do { ++ val = NXRD32(adapter, CRB_CMDPEG_STATE); + +- msleep(500); ++ switch (val) { ++ case PHAN_INITIALIZE_COMPLETE: ++ case PHAN_INITIALIZE_ACK: ++ return 0; ++ case PHAN_INITIALIZE_FAILED: ++ goto out_err; ++ default: ++ break; ++ } + +- } while (--retries); ++ msleep(500); + +- if (!retries) { +- pegtune_val = adapter->pci_read_normalize(adapter, +- NETXEN_ROMUSB_GLB_PEGTUNE_DONE); +- printk(KERN_WARNING "netxen_phantom_init: init failed, " +- "pegtune_val=%x\n", pegtune_val); +- return -1; +- } +- } ++ } while (--retries); + +- return 0; ++ NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); ++ ++out_err: ++ dev_warn(&adapter->pdev->dev, "firmware init failed\n"); ++ return -EIO; + } + +-int netxen_receive_peg_ready(struct netxen_adapter *adapter) ++static int ++netxen_receive_peg_ready(struct netxen_adapter *adapter) + { + u32 val = 0; + int retries = 2000; + + do { +- val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE); ++ val = NXRD32(adapter, CRB_RCVPEG_STATE); + + if (val == PHAN_PEG_RCV_INITIALIZED) + return 0; +@@ -1164,6 +1011,123 @@ + "complete, state: 0x%x.\n", val); + return -EIO; + } ++ ++ return 0; ++} ++ ++int netxen_init_firmware(struct netxen_adapter *adapter) ++{ ++ int err; ++ ++ err = netxen_receive_peg_ready(adapter); ++ if (err) ++ return err; ++ ++ NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT); ++ NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC); ++ NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE); ++ NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK); ++ ++ return err; ++} ++ ++static void ++netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg) ++{ ++ u32 cable_OUI; ++ u16 cable_len; ++ u16 link_speed; ++ u8 link_status, module, duplex, autoneg; ++ struct net_device *netdev = adapter->netdev; ++ ++ adapter->has_link_events = 1; ++ ++ cable_OUI = msg->body[1] & 0xffffffff; ++ cable_len = (msg->body[1] >> 32) & 0xffff; ++ link_speed = (msg->body[1] >> 48) & 0xffff; ++ ++ link_status = msg->body[2] & 0xff; ++ duplex = (msg->body[2] >> 16) & 0xff; ++ autoneg = (msg->body[2] >> 24) & 0xff; ++ ++ module = (msg->body[2] >> 8) & 0xff; ++ if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) { ++ printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n", ++ netdev->name, cable_OUI, cable_len); ++ } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) { ++ printk(KERN_INFO "%s: unsupported cable length %d\n", ++ netdev->name, cable_len); ++ } ++ ++ netxen_advert_link_change(adapter, link_status); ++ ++ /* update link parameters */ ++ if (duplex == LINKEVENT_FULL_DUPLEX) ++ adapter->link_duplex = DUPLEX_FULL; ++ else ++ adapter->link_duplex = DUPLEX_HALF; ++ adapter->module_type = module; ++ adapter->link_autoneg = autoneg; ++ adapter->link_speed = link_speed; ++} ++ ++static void ++netxen_handle_fw_message(int desc_cnt, int index, ++ struct nx_host_sds_ring *sds_ring) ++{ ++ nx_fw_msg_t msg; ++ struct status_desc *desc; ++ int i = 0, opcode; ++ ++ while (desc_cnt > 0 && i < 8) { ++ desc = &sds_ring->desc_head[index]; ++ msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]); ++ msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]); ++ ++ index = get_next_index(index, sds_ring->num_desc); ++ desc_cnt--; ++ } ++ ++ opcode = netxen_get_nic_msg_opcode(msg.body[0]); ++ switch (opcode) { ++ case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE: ++ netxen_handle_linkevent(sds_ring->adapter, &msg); ++ break; ++ default: ++ break; ++ } ++} ++ ++static int ++netxen_alloc_rx_skb(struct netxen_adapter *adapter, ++ struct nx_host_rds_ring *rds_ring, ++ struct netxen_rx_buffer *buffer) ++{ ++ struct sk_buff *skb; ++ dma_addr_t dma; ++ struct pci_dev *pdev = adapter->pdev; ++ ++ buffer->skb = dev_alloc_skb(rds_ring->skb_size); ++ if (!buffer->skb) ++ return 1; ++ ++ skb = buffer->skb; ++ ++ if (!adapter->ahw.cut_through) ++ skb_reserve(skb, 2); ++ ++ dma = pci_map_single(pdev, skb->data, ++ rds_ring->dma_size, PCI_DMA_FROMDEVICE); ++ ++ if (pci_dma_mapping_error(pdev, dma)) { ++ dev_kfree_skb_any(skb); ++ buffer->skb = NULL; ++ return 1; ++ } ++ ++ buffer->skb = skb; ++ buffer->dma = dma; ++ buffer->state = NETXEN_BUFFER_BUSY; + + return 0; + } +@@ -1192,166 +1156,226 @@ + skb->dev = adapter->netdev; + + buffer->skb = NULL; +- + no_skb: + buffer->state = NETXEN_BUFFER_FREE; +- buffer->lro_current_frags = 0; +- buffer->lro_expected_frags = 0; +- list_add_tail(&buffer->list, &rds_ring->free_list); + return skb; + } + +-/* +- * netxen_process_rcv() send the received packet to the protocol stack. +- * and if the number of receives exceeds RX_BUFFERS_REFILL, then we +- * invoke the routine to send more rx buffers to the Phantom... +- */ +-static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid, +- struct status_desc *desc, struct status_desc *frag_desc) ++static struct netxen_rx_buffer * ++netxen_process_rcv(struct netxen_adapter *adapter, ++ struct nx_host_sds_ring *sds_ring, ++ int ring, u64 sts_data0) + { + struct net_device *netdev = adapter->netdev; +- u64 sts_data = le64_to_cpu(desc->status_desc_data); +- int index = netxen_get_sts_refhandle(sts_data); +- struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]); ++ struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; + struct netxen_rx_buffer *buffer; + struct sk_buff *skb; +- u32 length = netxen_get_sts_totallength(sts_data); +- u32 desc_ctx; +- u16 pkt_offset = 0, cksum; + struct nx_host_rds_ring *rds_ring; ++ int index, length, cksum, pkt_offset; + +- desc_ctx = netxen_get_sts_type(sts_data); +- if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) { +- printk("%s: %s Bad Rcv descriptor ring\n", +- netxen_nic_driver_name, netdev->name); +- return; +- } ++ if (unlikely(ring >= adapter->max_rds_rings)) ++ return NULL; + +- rds_ring = &recv_ctx->rds_rings[desc_ctx]; +- if (unlikely(index > rds_ring->max_rx_desc_count)) { +- DPRINTK(ERR, "Got a buffer index:%x Max is %x\n", +- index, rds_ring->max_rx_desc_count); +- return; +- } ++ rds_ring = &recv_ctx->rds_rings[ring]; ++ ++ index = netxen_get_sts_refhandle(sts_data0); ++ if (unlikely(index >= rds_ring->num_desc)) ++ return NULL; ++ + buffer = &rds_ring->rx_buf_arr[index]; +- if (desc_ctx == RCV_DESC_LRO_CTXID) { +- buffer->lro_current_frags++; +- if (netxen_get_sts_desc_lro_last_frag(desc)) { +- buffer->lro_expected_frags = +- netxen_get_sts_desc_lro_cnt(desc); +- buffer->lro_length = length; +- } +- if (buffer->lro_current_frags != buffer->lro_expected_frags) { +- if (buffer->lro_expected_frags != 0) { +- printk("LRO: (refhandle:%x) recv frag. " +- "wait for last. flags: %x expected:%d " +- "have:%d\n", index, +- netxen_get_sts_desc_lro_last_frag(desc), +- buffer->lro_expected_frags, +- buffer->lro_current_frags); +- } +- return; +- } +- } + +- cksum = netxen_get_sts_status(sts_data); ++ length = netxen_get_sts_totallength(sts_data0); ++ cksum = netxen_get_sts_status(sts_data0); ++ pkt_offset = netxen_get_sts_pkt_offset(sts_data0); + + skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum); + if (!skb) +- return; ++ return buffer; + +- if (desc_ctx == RCV_DESC_LRO_CTXID) { +- /* True length was only available on the last pkt */ +- skb_put(skb, buffer->lro_length); +- } else { +- if (length > rds_ring->skb_size) +- skb_put(skb, rds_ring->skb_size); +- else +- skb_put(skb, length); ++ if (length > rds_ring->skb_size) ++ skb_put(skb, rds_ring->skb_size); ++ else ++ skb_put(skb, length); + +- pkt_offset = netxen_get_sts_pkt_offset(sts_data); +- if (pkt_offset) +- skb_pull(skb, pkt_offset); ++ ++ if (pkt_offset) ++ skb_pull(skb, pkt_offset); ++ ++ skb->truesize = skb->len + sizeof(struct sk_buff); ++ skb->protocol = eth_type_trans(skb, netdev); ++ ++ netif_receive_skb(skb); ++ netdev->last_rx = jiffies; ++ ++ adapter->stats.rx_pkts++; ++ adapter->stats.rxbytes += length; ++ ++ return buffer; ++} ++ ++#define TCP_HDR_SIZE 20 ++#define TCP_TS_OPTION_SIZE 12 ++#define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE) ++ ++static struct netxen_rx_buffer * ++netxen_process_lro(struct netxen_adapter *adapter, ++ struct nx_host_sds_ring *sds_ring, ++ int ring, u64 sts_data0, u64 sts_data1) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; ++ struct netxen_rx_buffer *buffer; ++ struct sk_buff *skb; ++ struct nx_host_rds_ring *rds_ring; ++ struct iphdr *iph; ++ struct tcphdr *th; ++ bool push, timestamp; ++ int l2_hdr_offset, l4_hdr_offset; ++ int index; ++ u16 lro_length, length, data_offset; ++ u32 seq_number; ++ ++ if (unlikely(ring > adapter->max_rds_rings)) ++ return NULL; ++ ++ rds_ring = &recv_ctx->rds_rings[ring]; ++ ++ index = netxen_get_lro_sts_refhandle(sts_data0); ++ if (unlikely(index > rds_ring->num_desc)) ++ return NULL; ++ ++ buffer = &rds_ring->rx_buf_arr[index]; ++ ++ timestamp = netxen_get_lro_sts_timestamp(sts_data0); ++ lro_length = netxen_get_lro_sts_length(sts_data0); ++ l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0); ++ l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0); ++ push = netxen_get_lro_sts_push_flag(sts_data0); ++ seq_number = netxen_get_lro_sts_seq_number(sts_data1); ++ ++ skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK); ++ if (!skb) ++ return buffer; ++ ++ if (timestamp) ++ data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE; ++ else ++ data_offset = l4_hdr_offset + TCP_HDR_SIZE; ++ ++ skb_put(skb, lro_length + data_offset); ++ ++ skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb); ++ ++ skb_pull(skb, l2_hdr_offset); ++ skb->protocol = eth_type_trans(skb, netdev); ++ ++ iph = (struct iphdr *)skb->data; ++ th = (struct tcphdr *)(skb->data + (iph->ihl << 2)); ++ ++ length = (iph->ihl << 2) + (th->doff << 2) + lro_length; ++ iph->tot_len = htons(length); ++ iph->check = 0; ++ iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl); ++ th->psh = push; ++ th->seq = htonl(seq_number); ++ ++ length = skb->len; ++ ++ netif_receive_skb(skb); ++ ++ adapter->stats.lro_pkts++; ++ adapter->stats.rxbytes += length; ++ ++ return buffer; ++} ++ ++#define netxen_merge_rx_buffers(list, head) \ ++ do { list_splice_tail_init(list, head); } while (0); ++ ++int ++netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max) ++{ ++ struct netxen_adapter *adapter = sds_ring->adapter; ++ ++ struct list_head *cur; ++ ++ struct status_desc *desc; ++ struct netxen_rx_buffer *rxbuf; ++ ++ u32 consumer = sds_ring->consumer; ++ ++ int count = 0; ++ u64 sts_data0, sts_data1; ++ int opcode, ring = 0, desc_cnt; ++ ++ while (count < max) { ++ desc = &sds_ring->desc_head[consumer]; ++ sts_data0 = le64_to_cpu(desc->status_desc_data[0]); ++ ++ if (!(sts_data0 & STATUS_OWNER_HOST)) ++ break; ++ ++ desc_cnt = netxen_get_sts_desc_cnt(sts_data0); ++ ++ opcode = netxen_get_sts_opcode(sts_data0); ++ ++ switch (opcode) { ++ case NETXEN_NIC_RXPKT_DESC: ++ case NETXEN_OLD_RXPKT_DESC: ++ case NETXEN_NIC_SYN_OFFLOAD: ++ ring = netxen_get_sts_type(sts_data0); ++ rxbuf = netxen_process_rcv(adapter, sds_ring, ++ ring, sts_data0); ++ break; ++ case NETXEN_NIC_LRO_DESC: ++ ring = netxen_get_lro_sts_type(sts_data0); ++ sts_data1 = le64_to_cpu(desc->status_desc_data[1]); ++ rxbuf = netxen_process_lro(adapter, sds_ring, ++ ring, sts_data0, sts_data1); ++ break; ++ case NETXEN_NIC_RESPONSE_DESC: ++ netxen_handle_fw_message(desc_cnt, consumer, sds_ring); ++ default: ++ goto skip; ++ } ++ ++ WARN_ON(desc_cnt > 1); ++ ++ if (rxbuf) ++ list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]); ++ ++skip: ++ for (; desc_cnt > 0; desc_cnt--) { ++ desc = &sds_ring->desc_head[consumer]; ++ desc->status_desc_data[0] = ++ cpu_to_le64(STATUS_OWNER_PHANTOM); ++ consumer = get_next_index(consumer, sds_ring->num_desc); ++ } ++ count++; + } + +- skb->protocol = eth_type_trans(skb, netdev); ++ for (ring = 0; ring < adapter->max_rds_rings; ring++) { ++ struct nx_host_rds_ring *rds_ring = ++ &adapter->recv_ctx.rds_rings[ring]; + +- /* +- * rx buffer chaining is disabled, walk and free +- * any spurious rx buffer chain. +- */ +- if (frag_desc) { +- u16 i, nr_frags = desc->nr_frags; +- +- dev_kfree_skb_any(skb); +- for (i = 0; i < nr_frags; i++) { +- index = le16_to_cpu(frag_desc->frag_handles[i]); +- skb = netxen_process_rxbuf(adapter, +- rds_ring, index, cksum); +- if (skb) +- dev_kfree_skb_any(skb); +- } +- adapter->stats.rxdropped++; +- } else { +- +- netif_receive_skb(skb); +- netdev->last_rx = jiffies; +- +- adapter->stats.no_rcv++; +- adapter->stats.rxbytes += length; +- } +-} +- +-/* Process Receive status ring */ +-u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max) +-{ +- struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]); +- struct status_desc *desc_head = recv_ctx->rcv_status_desc_head; +- struct status_desc *desc, *frag_desc; +- u32 consumer = recv_ctx->status_rx_consumer; +- int count = 0, ring; +- u64 sts_data; +- u16 opcode; +- +- while (count < max) { +- desc = &desc_head[consumer]; +- if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) { +- DPRINTK(ERR, "desc %p ownedby %x\n", desc, +- netxen_get_sts_owner(desc)); +- break; ++ if (!list_empty(&sds_ring->free_list[ring])) { ++ list_for_each(cur, &sds_ring->free_list[ring]) { ++ rxbuf = list_entry(cur, ++ struct netxen_rx_buffer, list); ++ netxen_alloc_rx_skb(adapter, rds_ring, rxbuf); ++ } ++ spin_lock(&rds_ring->lock); ++ netxen_merge_rx_buffers(&sds_ring->free_list[ring], ++ &rds_ring->free_list); ++ spin_unlock(&rds_ring->lock); + } + +- sts_data = le64_to_cpu(desc->status_desc_data); +- opcode = netxen_get_sts_opcode(sts_data); +- frag_desc = NULL; +- if (opcode == NETXEN_NIC_RXPKT_DESC) { +- if (desc->nr_frags) { +- consumer = get_next_index(consumer, +- adapter->max_rx_desc_count); +- frag_desc = &desc_head[consumer]; +- netxen_set_sts_owner(frag_desc, +- STATUS_OWNER_PHANTOM); +- } +- } ++ netxen_post_rx_buffers_nodb(adapter, rds_ring); ++ } + +- netxen_process_rcv(adapter, ctxid, desc, frag_desc); +- +- netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM); +- +- consumer = get_next_index(consumer, +- adapter->max_rx_desc_count); +- count++; +- } +- for (ring = 0; ring < adapter->max_rds_rings; ring++) +- netxen_post_rx_buffers_nodb(adapter, ctxid, ring); +- +- /* update the consumer index in phantom */ + if (count) { +- recv_ctx->status_rx_consumer = consumer; +- +- /* Window = 1 */ +- adapter->pci_write_normalize(adapter, +- recv_ctx->crb_sts_consumer, consumer); ++ sds_ring->consumer = consumer; ++ NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer); + } + + return count; +@@ -1360,19 +1384,23 @@ + /* Process Command status ring */ + int netxen_process_cmd_ring(struct netxen_adapter *adapter) + { +- u32 last_consumer, consumer; ++ u32 sw_consumer, hw_consumer; + int count = 0, i; + struct netxen_cmd_buffer *buffer; + struct pci_dev *pdev = adapter->pdev; + struct net_device *netdev = adapter->netdev; + struct netxen_skb_frag *frag; + int done = 0; ++ struct nx_host_tx_ring *tx_ring = adapter->tx_ring; + +- last_consumer = adapter->last_cmd_consumer; +- consumer = le32_to_cpu(*(adapter->cmd_consumer)); ++ if (!spin_trylock(&adapter->tx_clean_lock)) ++ return 1; + +- while (last_consumer != consumer) { +- buffer = &adapter->cmd_buf_arr[last_consumer]; ++ sw_consumer = tx_ring->sw_consumer; ++ hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer)); ++ ++ while (sw_consumer != hw_consumer) { ++ buffer = &tx_ring->cmd_buf_arr[sw_consumer]; + if (buffer->skb) { + frag = &buffer->frag_array[0]; + pci_unmap_single(pdev, frag->dma, frag->length, +@@ -1390,20 +1418,23 @@ + buffer->skb = NULL; + } + +- last_consumer = get_next_index(last_consumer, +- adapter->max_tx_desc_count); ++ sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc); + if (++count >= MAX_STATUS_HANDLE) + break; + } + +- if (count) { +- adapter->last_cmd_consumer = last_consumer; ++ if (count && netif_running(netdev)) { ++ tx_ring->sw_consumer = sw_consumer; ++ + smp_mb(); +- if (netif_queue_stopped(netdev) && netif_running(netdev)) { +- netif_tx_lock(netdev); +- netif_wake_queue(netdev); +- smp_mb(); +- netif_tx_unlock(netdev); ++ ++ if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) { ++ __netif_tx_lock(tx_ring->txq, smp_processor_id()); ++ if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) { ++ netif_wake_queue(netdev); ++ adapter->tx_timeo_cnt = 0; ++ } ++ __netif_tx_unlock(tx_ring->txq); + } + } + /* +@@ -1419,77 +1450,55 @@ + * There is still a possible race condition and the host could miss an + * interrupt. The card has to take care of this. + */ +- consumer = le32_to_cpu(*(adapter->cmd_consumer)); +- done = (last_consumer == consumer); ++ hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer)); ++ done = (sw_consumer == hw_consumer); ++ spin_unlock(&adapter->tx_clean_lock); + + return (done); + } + +-/* +- * netxen_post_rx_buffers puts buffer in the Phantom memory +- */ +-void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid) ++void ++netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid, ++ struct nx_host_rds_ring *rds_ring) + { +- struct pci_dev *pdev = adapter->pdev; +- struct sk_buff *skb; +- struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]); +- struct nx_host_rds_ring *rds_ring = NULL; +- uint producer; + struct rcv_desc *pdesc; + struct netxen_rx_buffer *buffer; +- int count = 0; ++ int producer, count = 0; + netxen_ctx_msg msg = 0; +- dma_addr_t dma; + struct list_head *head; + +- rds_ring = &recv_ctx->rds_rings[ringid]; ++ producer = rds_ring->producer; + +- producer = rds_ring->producer; ++ spin_lock(&rds_ring->lock); + head = &rds_ring->free_list; +- +- /* We can start writing rx descriptors into the phantom memory. */ + while (!list_empty(head)) { + +- skb = dev_alloc_skb(rds_ring->skb_size); +- if (unlikely(!skb)) { +- break; +- } ++ buffer = list_entry(head->next, struct netxen_rx_buffer, list); + +- if (!adapter->ahw.cut_through) +- skb_reserve(skb, 2); +- +- dma = pci_map_single(pdev, skb->data, +- rds_ring->dma_size, PCI_DMA_FROMDEVICE); +- if (pci_dma_mapping_error(pdev, dma)) { +- dev_kfree_skb_any(skb); +- break; ++ if (!buffer->skb) { ++ if (netxen_alloc_rx_skb(adapter, rds_ring, buffer)) ++ break; + } + + count++; +- buffer = list_entry(head->next, struct netxen_rx_buffer, list); + list_del(&buffer->list); +- +- buffer->skb = skb; +- buffer->state = NETXEN_BUFFER_BUSY; +- buffer->dma = dma; + + /* make a rcv descriptor */ + pdesc = &rds_ring->desc_head[producer]; +- pdesc->addr_buffer = cpu_to_le64(dma); ++ pdesc->addr_buffer = cpu_to_le64(buffer->dma); + pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); + pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size); + +- producer = get_next_index(producer, rds_ring->max_rx_desc_count); ++ producer = get_next_index(producer, rds_ring->num_desc); + } +- /* if we did allocate buffers, then write the count to Phantom */ ++ spin_unlock(&rds_ring->lock); ++ + if (count) { + rds_ring->producer = producer; +- /* Window = 1 */ +- adapter->pci_write_normalize(adapter, +- rds_ring->crb_rcv_producer, +- (producer-1) & (rds_ring->max_rx_desc_count-1)); ++ NXWRIO(adapter, rds_ring->crb_rcv_producer, ++ (producer-1) & (rds_ring->num_desc-1)); + +- if (adapter->fw_major < 4) { ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { + /* + * Write a doorbell msg to tell phanmon of change in + * receive ring producer +@@ -1498,61 +1507,43 @@ + netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID); + netxen_set_msg_privid(msg); + netxen_set_msg_count(msg, +- ((producer - +- 1) & (rds_ring-> +- max_rx_desc_count - 1))); ++ ((producer - 1) & ++ (rds_ring->num_desc - 1))); + netxen_set_msg_ctxid(msg, adapter->portnum); + netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid)); +- writel(msg, +- DB_NORMALIZE(adapter, ++ read_lock(&adapter->adapter_lock); ++ writel(msg, DB_NORMALIZE(adapter, + NETXEN_RCV_PRODUCER_OFFSET)); ++ read_unlock(&adapter->adapter_lock); + } + } + } + +-static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, +- uint32_t ctx, uint32_t ringid) ++static void ++netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, ++ struct nx_host_rds_ring *rds_ring) + { +- struct pci_dev *pdev = adapter->pdev; +- struct sk_buff *skb; +- struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]); +- struct nx_host_rds_ring *rds_ring = NULL; +- u32 producer; + struct rcv_desc *pdesc; + struct netxen_rx_buffer *buffer; +- int count = 0; ++ int producer, count = 0; + struct list_head *head; +- dma_addr_t dma; +- +- rds_ring = &recv_ctx->rds_rings[ringid]; + + producer = rds_ring->producer; ++ if (!spin_trylock(&rds_ring->lock)) ++ return; ++ + head = &rds_ring->free_list; +- /* We can start writing rx descriptors into the phantom memory. */ + while (!list_empty(head)) { + +- skb = dev_alloc_skb(rds_ring->skb_size); +- if (unlikely(!skb)) { +- break; +- } ++ buffer = list_entry(head->next, struct netxen_rx_buffer, list); + +- if (!adapter->ahw.cut_through) +- skb_reserve(skb, 2); +- +- dma = pci_map_single(pdev, skb->data, +- rds_ring->dma_size, PCI_DMA_FROMDEVICE); +- if (pci_dma_mapping_error(pdev, dma)) { +- dev_kfree_skb_any(skb); +- break; ++ if (!buffer->skb) { ++ if (netxen_alloc_rx_skb(adapter, rds_ring, buffer)) ++ break; + } + + count++; +- buffer = list_entry(head->next, struct netxen_rx_buffer, list); + list_del(&buffer->list); +- +- buffer->skb = skb; +- buffer->state = NETXEN_BUFFER_BUSY; +- buffer->dma = dma; + + /* make a rcv descriptor */ + pdesc = &rds_ring->desc_head[producer]; +@@ -1560,18 +1551,15 @@ + pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size); + pdesc->addr_buffer = cpu_to_le64(buffer->dma); + +- producer = get_next_index(producer, rds_ring->max_rx_desc_count); ++ producer = get_next_index(producer, rds_ring->num_desc); + } + +- /* if we did allocate buffers, then write the count to Phantom */ + if (count) { + rds_ring->producer = producer; +- /* Window = 1 */ +- adapter->pci_write_normalize(adapter, +- rds_ring->crb_rcv_producer, +- (producer-1) & (rds_ring->max_rx_desc_count-1)); +- wmb(); ++ NXWRIO(adapter, rds_ring->crb_rcv_producer, ++ (producer - 1) & (rds_ring->num_desc - 1)); + } ++ spin_unlock(&rds_ring->lock); + } + + void netxen_nic_clear_stats(struct netxen_adapter *adapter) +diff -r 6335373db0ec drivers/net/netxen/netxen_nic_main.c +--- a/drivers/net/netxen/netxen_nic_main.c Thu Oct 01 10:10:06 2009 +0100 ++++ b/drivers/net/netxen/netxen_nic_main.c Mon Oct 05 17:00:12 2009 +0100 +@@ -1,5 +1,6 @@ + /* +- * Copyright (C) 2003 - 2006 NetXen, Inc. ++ * Copyright (C) 2003 - 2009 NetXen, Inc. ++ * Copyright (C) 2009 - QLogic Corporation. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or +@@ -20,28 +21,19 @@ + * The full GNU General Public License is included in this distribution + * in the file called LICENSE. + * +- * Contact Information: +- * info@netxen.com +- * NetXen, +- * 3965 Freedom Circle, Fourth floor, +- * Santa Clara, CA 95054 +- * +- * +- * Main source file for NetXen NIC Driver on Linux +- * + */ + + #include +-#include ++#include + #include "netxen_nic_hw.h" + + #include "netxen_nic.h" +-#include "netxen_nic_phan_reg.h" + + #include + #include + #include + #include ++#include + + MODULE_DESCRIPTION("NetXen Multi port (1/10) Gigabit Network Driver"); + MODULE_LICENSE("GPL"); +@@ -69,13 +61,26 @@ + static int netxen_nic_xmit_frame(struct sk_buff *, struct net_device *); + static void netxen_tx_timeout(struct net_device *netdev); + static void netxen_tx_timeout_task(struct work_struct *work); +-static void netxen_watchdog(unsigned long); ++static void netxen_fw_poll_work(struct work_struct *work); ++static void netxen_schedule_work(struct netxen_adapter *adapter, ++ work_func_t func, int delay); ++static void netxen_cancel_fw_work(struct netxen_adapter *adapter); + static int netxen_nic_poll(struct napi_struct *napi, int budget); + #ifdef CONFIG_NET_POLL_CONTROLLER + static void netxen_nic_poll_controller(struct net_device *netdev); + #endif ++ ++static void netxen_create_sysfs_entries(struct netxen_adapter *adapter); ++static void netxen_remove_sysfs_entries(struct netxen_adapter *adapter); ++ ++static int nx_decr_dev_ref_cnt(struct netxen_adapter *adapter); ++static int netxen_can_start_firmware(struct netxen_adapter *adapter); ++ + static irqreturn_t netxen_intr(int irq, void *data); + static irqreturn_t netxen_msi_intr(int irq, void *data); ++static irqreturn_t netxen_msix_intr(int irq, void *data); ++ ++static void netxen_config_indev_addr(struct net_device *dev, unsigned long); + + /* PCI Device ID Table */ + #define ENTRY(device) \ +@@ -96,26 +101,6 @@ + + MODULE_DEVICE_TABLE(pci, netxen_pci_tbl); + +-/* +- * In netxen_nic_down(), we must wait for any pending callback requests into +- * netxen_watchdog_task() to complete; eg otherwise the watchdog_timer could be +- * reenabled right after it is deleted in netxen_nic_down(). +- * FLUSH_SCHEDULED_WORK() does this synchronization. +- * +- * Normally, schedule_work()/flush_scheduled_work() could have worked, but +- * netxen_nic_close() is invoked with kernel rtnl lock held. netif_carrier_off() +- * call in netxen_nic_close() triggers a schedule_work(&linkwatch_work), and a +- * subsequent call to flush_scheduled_work() in netxen_nic_down() would cause +- * linkwatch_event() to be executed which also attempts to acquire the rtnl +- * lock thus causing a deadlock. +- */ +- +-static struct workqueue_struct *netxen_workq; +-#define SCHEDULE_WORK(tp) queue_work(netxen_workq, tp) +-#define FLUSH_SCHEDULED_WORK() flush_workqueue(netxen_workq) +- +-static void netxen_watchdog(unsigned long); +- + static uint32_t crb_cmd_producer[4] = { + CRB_CMD_PRODUCER_OFFSET, CRB_CMD_PRODUCER_OFFSET_1, + CRB_CMD_PRODUCER_OFFSET_2, CRB_CMD_PRODUCER_OFFSET_3 +@@ -123,10 +108,14 @@ + + void + netxen_nic_update_cmd_producer(struct netxen_adapter *adapter, +- uint32_t crb_producer) ++ struct nx_host_tx_ring *tx_ring) + { +- adapter->pci_write_normalize(adapter, +- adapter->crb_addr_cmd_producer, crb_producer); ++ NXWRIO(adapter, tx_ring->crb_cmd_producer, tx_ring->producer); ++ ++ if (netxen_tx_avail(tx_ring) <= TX_STOP_THRESH) { ++ netif_stop_queue(adapter->netdev); ++ smp_mb(); ++ } + } + + static uint32_t crb_cmd_consumer[4] = { +@@ -136,10 +125,9 @@ + + static inline void + netxen_nic_update_cmd_consumer(struct netxen_adapter *adapter, +- u32 crb_consumer) ++ struct nx_host_tx_ring *tx_ring) + { +- adapter->pci_write_normalize(adapter, +- adapter->crb_addr_cmd_consumer, crb_consumer); ++ NXWRIO(adapter, tx_ring->crb_cmd_consumer, tx_ring->sw_consumer); + } + + static uint32_t msi_tgt_status[8] = { +@@ -151,131 +139,177 @@ + + static struct netxen_legacy_intr_set legacy_intr[] = NX_LEGACY_INTR_CONFIG; + +-static inline void netxen_nic_disable_int(struct netxen_adapter *adapter) ++static inline void netxen_nic_disable_int(struct nx_host_sds_ring *sds_ring) + { +- adapter->pci_write_normalize(adapter, adapter->crb_intr_mask, 0); ++ struct netxen_adapter *adapter = sds_ring->adapter; ++ ++ NXWRIO(adapter, sds_ring->crb_intr_mask, 0); + } + +-static inline void netxen_nic_enable_int(struct netxen_adapter *adapter) ++static inline void netxen_nic_enable_int(struct nx_host_sds_ring *sds_ring) + { +- adapter->pci_write_normalize(adapter, adapter->crb_intr_mask, 0x1); ++ struct netxen_adapter *adapter = sds_ring->adapter; ++ ++ NXWRIO(adapter, sds_ring->crb_intr_mask, 0x1); + + if (!NETXEN_IS_MSI_FAMILY(adapter)) +- adapter->pci_write_immediate(adapter, +- adapter->legacy_intr.tgt_mask_reg, 0xfbff); ++ NXWRIO(adapter, adapter->tgt_mask_reg, 0xfbff); + } + +-static int nx_set_dma_mask(struct netxen_adapter *adapter, uint8_t revision_id) ++static int ++netxen_alloc_sds_rings(struct netxen_recv_context *recv_ctx, int count) ++{ ++ int size = sizeof(struct nx_host_sds_ring) * count; ++ ++ recv_ctx->sds_rings = kzalloc(size, GFP_KERNEL); ++ ++ return (recv_ctx->sds_rings == NULL); ++} ++ ++static void ++netxen_free_sds_rings(struct netxen_recv_context *recv_ctx) ++{ ++ if (recv_ctx->sds_rings != NULL) ++ kfree(recv_ctx->sds_rings); ++ ++ recv_ctx->sds_rings = NULL; ++} ++ ++static int ++netxen_napi_add(struct netxen_adapter *adapter, struct net_device *netdev) ++{ ++ int ring; ++ struct nx_host_sds_ring *sds_ring; ++ struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; ++ ++ if (netxen_alloc_sds_rings(recv_ctx, adapter->max_sds_rings)) ++ return -ENOMEM; ++ ++ for (ring = 0; ring < adapter->max_sds_rings; ring++) { ++ sds_ring = &recv_ctx->sds_rings[ring]; ++ netif_napi_add(netdev, &sds_ring->napi, ++ netxen_nic_poll, NETXEN_NETDEV_WEIGHT); ++ } ++ ++ return 0; ++} ++ ++static void ++netxen_napi_del(struct netxen_adapter *adapter) ++{ ++ int ring; ++ struct nx_host_sds_ring *sds_ring; ++ struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; ++ ++ for (ring = 0; ring < adapter->max_sds_rings; ring++) { ++ sds_ring = &recv_ctx->sds_rings[ring]; ++ netif_napi_del(&sds_ring->napi); ++ } ++ ++ netxen_free_sds_rings(&adapter->recv_ctx); ++} ++ ++static void ++netxen_napi_enable(struct netxen_adapter *adapter) ++{ ++ int ring; ++ struct nx_host_sds_ring *sds_ring; ++ struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; ++ ++ for (ring = 0; ring < adapter->max_sds_rings; ring++) { ++ sds_ring = &recv_ctx->sds_rings[ring]; ++ napi_enable(&sds_ring->napi); ++ netxen_nic_enable_int(sds_ring); ++ } ++} ++ ++static void ++netxen_napi_disable(struct netxen_adapter *adapter) ++{ ++ int ring; ++ struct nx_host_sds_ring *sds_ring; ++ struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; ++ ++ for (ring = 0; ring < adapter->max_sds_rings; ring++) { ++ sds_ring = &recv_ctx->sds_rings[ring]; ++ netxen_nic_disable_int(sds_ring); ++ napi_synchronize(&sds_ring->napi); ++ napi_disable(&sds_ring->napi); ++ } ++} ++ ++static int nx_set_dma_mask(struct netxen_adapter *adapter) + { + struct pci_dev *pdev = adapter->pdev; +- int err; +- uint64_t mask; ++ uint64_t mask, cmask; + +-#ifdef CONFIG_IA64 +- adapter->dma_mask = DMA_32BIT_MASK; +-#else +- if (revision_id >= NX_P3_B0) { +- /* should go to DMA_64BIT_MASK */ +- adapter->dma_mask = DMA_39BIT_MASK; +- mask = DMA_39BIT_MASK; +- } else if (revision_id == NX_P3_A2) { +- adapter->dma_mask = DMA_39BIT_MASK; +- mask = DMA_39BIT_MASK; +- } else if (revision_id == NX_P2_C1) { +- adapter->dma_mask = DMA_35BIT_MASK; +- mask = DMA_35BIT_MASK; ++ adapter->pci_using_dac = 0; ++ ++ mask = DMA_BIT_MASK(32); ++ cmask = DMA_BIT_MASK(32); ++ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { ++#ifndef CONFIG_IA64 ++ mask = DMA_BIT_MASK(35); ++#endif + } else { +- adapter->dma_mask = DMA_32BIT_MASK; +- mask = DMA_32BIT_MASK; +- goto set_32_bit_mask; ++ mask = DMA_BIT_MASK(39); ++ cmask = mask; + } + +- /* +- * Consistent DMA mask is set to 32 bit because it cannot be set to +- * 35 bits. For P3 also leave it at 32 bits for now. Only the rings +- * come off this pool. +- */ + if (pci_set_dma_mask(pdev, mask) == 0 && +- pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK) == 0) { ++ pci_set_consistent_dma_mask(pdev, cmask) == 0) { + adapter->pci_using_dac = 1; + return 0; + } +-#endif /* CONFIG_IA64 */ + +-set_32_bit_mask: +- err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); +- if (!err) +- err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); +- if (err) { +- DPRINTK(ERR, "No usable DMA configuration, aborting:%d\n", err); +- return err; ++ return -EIO; ++} ++ ++/* Update addressable range if firmware supports it */ ++static int ++nx_update_dma_mask(struct netxen_adapter *adapter) ++{ ++ int change, shift, err; ++ uint64_t mask, old_mask, old_cmask; ++ struct pci_dev *pdev = adapter->pdev; ++ ++ change = 0; ++ ++ shift = NXRD32(adapter, CRB_DMA_SHIFT); ++ if (shift > 32) ++ return 0; ++ ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id) && (shift > 9)) ++ change = 1; ++ else if ((adapter->ahw.revision_id == NX_P2_C1) && (shift <= 4)) ++ change = 1; ++ ++ if (change) { ++ old_mask = pdev->dma_mask; ++ old_cmask = pdev->dev.coherent_dma_mask; ++ ++ mask = DMA_BIT_MASK(32+shift); ++ ++ err = pci_set_dma_mask(pdev, mask); ++ if (err) ++ goto err_out; ++ ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { ++ ++ err = pci_set_consistent_dma_mask(pdev, mask); ++ if (err) ++ goto err_out; ++ } ++ dev_info(&pdev->dev, "using %d-bit dma mask\n", 32+shift); + } + +- adapter->pci_using_dac = 0; + return 0; +-} + +-static void netxen_check_options(struct netxen_adapter *adapter) +-{ +- switch (adapter->ahw.boardcfg.board_type) { +- case NETXEN_BRDTYPE_P3_HMEZ: +- case NETXEN_BRDTYPE_P3_XG_LOM: +- case NETXEN_BRDTYPE_P3_10G_CX4: +- case NETXEN_BRDTYPE_P3_10G_CX4_LP: +- case NETXEN_BRDTYPE_P3_IMEZ: +- case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: +- case NETXEN_BRDTYPE_P3_10G_SFP_QT: +- case NETXEN_BRDTYPE_P3_10G_SFP_CT: +- case NETXEN_BRDTYPE_P3_10G_XFP: +- case NETXEN_BRDTYPE_P3_10000_BASE_T: +- adapter->msix_supported = !!use_msi_x; +- adapter->max_rx_desc_count = MAX_RCV_DESCRIPTORS_10G; +- break; +- +- case NETXEN_BRDTYPE_P2_SB31_10G: +- case NETXEN_BRDTYPE_P2_SB31_10G_CX4: +- case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: +- case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: +- adapter->msix_supported = 0; +- adapter->max_rx_desc_count = MAX_RCV_DESCRIPTORS_10G; +- break; +- +- case NETXEN_BRDTYPE_P3_REF_QG: +- case NETXEN_BRDTYPE_P3_4_GB: +- case NETXEN_BRDTYPE_P3_4_GB_MM: +- adapter->msix_supported = !!use_msi_x; +- adapter->max_rx_desc_count = MAX_RCV_DESCRIPTORS_1G; +- break; +- +- case NETXEN_BRDTYPE_P2_SB35_4G: +- case NETXEN_BRDTYPE_P2_SB31_2G: +- adapter->msix_supported = 0; +- adapter->max_rx_desc_count = MAX_RCV_DESCRIPTORS_1G; +- break; +- +- case NETXEN_BRDTYPE_P3_10G_TP: +- adapter->msix_supported = !!use_msi_x; +- if (adapter->ahw.board_type == NETXEN_NIC_XGBE) +- adapter->max_rx_desc_count = MAX_RCV_DESCRIPTORS_10G; +- else +- adapter->max_rx_desc_count = MAX_RCV_DESCRIPTORS_1G; +- break; +- +- default: +- adapter->msix_supported = 0; +- adapter->max_rx_desc_count = MAX_RCV_DESCRIPTORS_1G; +- +- printk(KERN_WARNING "Unknown board type(0x%x)\n", +- adapter->ahw.boardcfg.board_type); +- break; +- } +- +- adapter->max_tx_desc_count = MAX_CMD_DESCRIPTORS_HOST; +- adapter->max_jumbo_rx_desc_count = MAX_JUMBO_RCV_DESCRIPTORS; +- adapter->max_lro_rx_desc_count = MAX_LRO_RCV_DESCRIPTORS; +- +- adapter->max_possible_rss_rings = 1; +- return; ++err_out: ++ pci_set_dma_mask(pdev, old_mask); ++ pci_set_consistent_dma_mask(pdev, old_cmask); ++ return err; + } + + static int +@@ -285,43 +319,34 @@ + + if (first_boot == 0x55555555) { + /* This is the first boot after power up */ +- adapter->pci_write_normalize(adapter, +- NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC); ++ NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC); + + if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) + return 0; + + /* PCI bus master workaround */ +- adapter->hw_read_wx(adapter, +- NETXEN_PCIE_REG(0x4), &first_boot, 4); ++ first_boot = NXRD32(adapter, NETXEN_PCIE_REG(0x4)); + if (!(first_boot & 0x4)) { + first_boot |= 0x4; +- adapter->hw_write_wx(adapter, +- NETXEN_PCIE_REG(0x4), &first_boot, 4); +- adapter->hw_read_wx(adapter, +- NETXEN_PCIE_REG(0x4), &first_boot, 4); ++ NXWR32(adapter, NETXEN_PCIE_REG(0x4), first_boot); ++ first_boot = NXRD32(adapter, NETXEN_PCIE_REG(0x4)); + } + + /* This is the first boot after power up */ +- adapter->hw_read_wx(adapter, +- NETXEN_ROMUSB_GLB_SW_RESET, &first_boot, 4); ++ first_boot = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET); + if (first_boot != 0x80000f) { + /* clear the register for future unloads/loads */ +- adapter->pci_write_normalize(adapter, +- NETXEN_CAM_RAM(0x1fc), 0); ++ NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), 0); + return -EIO; + } + + /* Start P2 boot loader */ +- val = adapter->pci_read_normalize(adapter, +- NETXEN_ROMUSB_GLB_PEGTUNE_DONE); +- adapter->pci_write_normalize(adapter, +- NETXEN_ROMUSB_GLB_PEGTUNE_DONE, val | 0x1); ++ val = NXRD32(adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE); ++ NXWR32(adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE, val | 0x1); + timeout = 0; + do { + msleep(1); +- val = adapter->pci_read_normalize(adapter, +- NETXEN_CAM_RAM(0x1fc)); ++ val = NXRD32(adapter, NETXEN_CAM_RAM(0x1fc)); + + if (++timeout > 5000) + return -EIO; +@@ -335,29 +360,24 @@ + { + u32 val, data; + +- val = adapter->ahw.boardcfg.board_type; ++ val = adapter->ahw.board_type; + if ((val == NETXEN_BRDTYPE_P3_HMEZ) || + (val == NETXEN_BRDTYPE_P3_XG_LOM)) { + if (port_mode == NETXEN_PORT_MODE_802_3_AP) { + data = NETXEN_PORT_MODE_802_3_AP; +- adapter->hw_write_wx(adapter, +- NETXEN_PORT_MODE_ADDR, &data, 4); ++ NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data); + } else if (port_mode == NETXEN_PORT_MODE_XG) { + data = NETXEN_PORT_MODE_XG; +- adapter->hw_write_wx(adapter, +- NETXEN_PORT_MODE_ADDR, &data, 4); ++ NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data); + } else if (port_mode == NETXEN_PORT_MODE_AUTO_NEG_1G) { + data = NETXEN_PORT_MODE_AUTO_NEG_1G; +- adapter->hw_write_wx(adapter, +- NETXEN_PORT_MODE_ADDR, &data, 4); ++ NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data); + } else if (port_mode == NETXEN_PORT_MODE_AUTO_NEG_XG) { + data = NETXEN_PORT_MODE_AUTO_NEG_XG; +- adapter->hw_write_wx(adapter, +- NETXEN_PORT_MODE_ADDR, &data, 4); ++ NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data); + } else { + data = NETXEN_PORT_MODE_AUTO_NEG; +- adapter->hw_write_wx(adapter, +- NETXEN_PORT_MODE_ADDR, &data, 4); ++ NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data); + } + + if ((wol_port_mode != NETXEN_PORT_MODE_802_3_AP) && +@@ -366,70 +386,8 @@ + (wol_port_mode != NETXEN_PORT_MODE_AUTO_NEG_XG)) { + wol_port_mode = NETXEN_PORT_MODE_AUTO_NEG; + } +- adapter->hw_write_wx(adapter, NETXEN_WOL_PORT_MODE, +- &wol_port_mode, 4); ++ NXWR32(adapter, NETXEN_WOL_PORT_MODE, wol_port_mode); + } +-} +- +-#define PCI_CAP_ID_GEN 0x10 +- +-static void netxen_pcie_strap_init(struct netxen_adapter *adapter) +-{ +- u32 pdevfuncsave; +- u32 c8c9value = 0; +- u32 chicken = 0; +- u32 control = 0; +- int i, pos; +- struct pci_dev *pdev; +- +- pdev = adapter->pdev; +- +- adapter->hw_read_wx(adapter, +- NETXEN_PCIE_REG(PCIE_CHICKEN3), &chicken, 4); +- /* clear chicken3.25:24 */ +- chicken &= 0xFCFFFFFF; +- /* +- * if gen1 and B0, set F1020 - if gen 2, do nothing +- * if gen2 set to F1000 +- */ +- pos = pci_find_capability(pdev, PCI_CAP_ID_GEN); +- if (pos == 0xC0) { +- pci_read_config_dword(pdev, pos + 0x10, &control); +- if ((control & 0x000F0000) != 0x00020000) { +- /* set chicken3.24 if gen1 */ +- chicken |= 0x01000000; +- } +- printk(KERN_INFO "%s Gen2 strapping detected\n", +- netxen_nic_driver_name); +- c8c9value = 0xF1000; +- } else { +- /* set chicken3.24 if gen1 */ +- chicken |= 0x01000000; +- printk(KERN_INFO "%s Gen1 strapping detected\n", +- netxen_nic_driver_name); +- if (adapter->ahw.revision_id == NX_P3_B0) +- c8c9value = 0xF1020; +- else +- c8c9value = 0; +- +- } +- adapter->hw_write_wx(adapter, +- NETXEN_PCIE_REG(PCIE_CHICKEN3), &chicken, 4); +- +- if (!c8c9value) +- return; +- +- pdevfuncsave = pdev->devfn; +- if (pdevfuncsave & 0x07) +- return; +- +- for (i = 0; i < 8; i++) { +- pci_read_config_dword(pdev, pos + 8, &control); +- pci_read_config_dword(pdev, pos + 8, &control); +- pci_write_config_dword(pdev, pos + 8, c8c9value); +- pdev->devfn++; +- } +- pdev->devfn = pdevfuncsave; + } + + static void netxen_set_msix_bit(struct pci_dev *pdev, int enable) +@@ -448,11 +406,11 @@ + } + } + +-static void netxen_init_msix_entries(struct netxen_adapter *adapter) ++static void netxen_init_msix_entries(struct netxen_adapter *adapter, int count) + { + int i; + +- for (i = 0; i < MSIX_ENTRIES_PER_ADAPTER; i++) ++ for (i = 0; i < count; i++) + adapter->msix_entries[i].entry = i; + } + +@@ -465,9 +423,6 @@ + DECLARE_MAC_BUF(mac); + struct net_device *netdev = adapter->netdev; + struct pci_dev *pdev = adapter->pdev; +- +- if (netxen_is_flash_supported(adapter) != 0) +- return -EIO; + + if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { + if (netxen_p3_get_mac_addr(adapter, &mac_addr) != 0) +@@ -485,50 +440,776 @@ + + /* set station address */ + +- if (!is_valid_ether_addr(netdev->perm_addr)) { ++ if (!is_valid_ether_addr(netdev->perm_addr)) + dev_warn(&pdev->dev, "Bad MAC address %s.\n", + print_mac(mac, netdev->dev_addr)); +- } else +- adapter->macaddr_set(adapter, netdev->dev_addr); + + return 0; + } + +-/* +- * netxen_nic_probe() +- * +- * The Linux system will invoke this after identifying the vendor ID and +- * device Id in the pci_tbl supported by this module. +- * +- * A quad port card has one operational PCI config space, (function 0), +- * which is used to access all four ports. +- * +- * This routine will initialize the adapter, and setup the global parameters +- * along with the port's specific structure. +- */ ++int netxen_nic_set_mac(struct net_device *netdev, void *p) ++{ ++ struct netxen_adapter *adapter = netdev_priv(netdev); ++ struct sockaddr *addr = p; ++ ++ if (!is_valid_ether_addr(addr->sa_data)) ++ return -EINVAL; ++ ++ if (netif_running(netdev)) { ++ netif_device_detach(netdev); ++ netxen_napi_disable(adapter); ++ } ++ ++ memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); ++ adapter->macaddr_set(adapter, addr->sa_data); ++ ++ if (netif_running(netdev)) { ++ netif_device_attach(netdev); ++ netxen_napi_enable(adapter); ++ } ++ return 0; ++} ++ ++static void netxen_set_multicast_list(struct net_device *dev) ++{ ++ struct netxen_adapter *adapter = netdev_priv(dev); ++ ++ adapter->set_multi(dev); ++} ++ ++static void ++netxen_setup_intr(struct netxen_adapter *adapter) ++{ ++ struct netxen_legacy_intr_set *legacy_intrp; ++ struct pci_dev *pdev = adapter->pdev; ++ int err, num_msix; ++ ++ if (adapter->rss_supported) { ++ num_msix = (num_online_cpus() >= MSIX_ENTRIES_PER_ADAPTER) ? ++ MSIX_ENTRIES_PER_ADAPTER : 2; ++ } else ++ num_msix = 1; ++ ++ adapter->max_sds_rings = 1; ++ ++ adapter->flags &= ~(NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED); ++ ++ if (adapter->ahw.revision_id >= NX_P3_B0) ++ legacy_intrp = &legacy_intr[adapter->ahw.pci_func]; ++ else ++ legacy_intrp = &legacy_intr[0]; ++ ++ adapter->int_vec_bit = legacy_intrp->int_vec_bit; ++ adapter->tgt_status_reg = netxen_get_ioaddr(adapter, ++ legacy_intrp->tgt_status_reg); ++ adapter->tgt_mask_reg = netxen_get_ioaddr(adapter, ++ legacy_intrp->tgt_mask_reg); ++ adapter->pci_int_reg = netxen_get_ioaddr(adapter, ++ legacy_intrp->pci_int_reg); ++ adapter->isr_int_vec = netxen_get_ioaddr(adapter, ISR_INT_VECTOR); ++ ++ if (adapter->ahw.revision_id >= NX_P3_B1) ++ adapter->crb_int_state_reg = netxen_get_ioaddr(adapter, ++ ISR_INT_STATE_REG); ++ else ++ adapter->crb_int_state_reg = netxen_get_ioaddr(adapter, ++ CRB_INT_VECTOR); ++ ++ netxen_set_msix_bit(pdev, 0); ++ ++ if (adapter->msix_supported) { ++ ++ netxen_init_msix_entries(adapter, num_msix); ++ err = pci_enable_msix(pdev, adapter->msix_entries, num_msix); ++ if (err == 0) { ++ adapter->flags |= NETXEN_NIC_MSIX_ENABLED; ++ netxen_set_msix_bit(pdev, 1); ++ ++ if (adapter->rss_supported) ++ adapter->max_sds_rings = num_msix; ++ ++ dev_info(&pdev->dev, "using msi-x interrupts\n"); ++ return; ++ } ++ ++ if (err > 0) ++ pci_disable_msix(pdev); ++ ++ /* fall through for msi */ ++ } ++ ++ if (use_msi && !pci_enable_msi(pdev)) { ++ adapter->flags |= NETXEN_NIC_MSI_ENABLED; ++ adapter->tgt_status_reg = netxen_get_ioaddr(adapter, ++ msi_tgt_status[adapter->ahw.pci_func]); ++ dev_info(&pdev->dev, "using msi interrupts\n"); ++ adapter->msix_entries[0].vector = pdev->irq; ++ return; ++ } ++ ++ dev_info(&pdev->dev, "using legacy interrupts\n"); ++ adapter->msix_entries[0].vector = pdev->irq; ++} ++ ++static void ++netxen_teardown_intr(struct netxen_adapter *adapter) ++{ ++ if (adapter->flags & NETXEN_NIC_MSIX_ENABLED) ++ pci_disable_msix(adapter->pdev); ++ if (adapter->flags & NETXEN_NIC_MSI_ENABLED) ++ pci_disable_msi(adapter->pdev); ++} ++ ++static void ++netxen_cleanup_pci_map(struct netxen_adapter *adapter) ++{ ++ if (adapter->ahw.db_base != NULL) ++ iounmap(adapter->ahw.db_base); ++ if (adapter->ahw.pci_base0 != NULL) ++ iounmap(adapter->ahw.pci_base0); ++ if (adapter->ahw.pci_base1 != NULL) ++ iounmap(adapter->ahw.pci_base1); ++ if (adapter->ahw.pci_base2 != NULL) ++ iounmap(adapter->ahw.pci_base2); ++} ++ ++static int ++netxen_setup_pci_map(struct netxen_adapter *adapter) ++{ ++ void __iomem *mem_ptr0 = NULL; ++ void __iomem *mem_ptr1 = NULL; ++ void __iomem *mem_ptr2 = NULL; ++ void __iomem *db_ptr = NULL; ++ ++ unsigned long mem_base, mem_len, db_base, db_len = 0, pci_len0 = 0; ++ ++ struct pci_dev *pdev = adapter->pdev; ++ int pci_func = adapter->ahw.pci_func; ++ ++ int err = 0; ++ ++ /* ++ * Set the CRB window to invalid. If any register in window 0 is ++ * accessed it should set the window to 0 and then reset it to 1. ++ */ ++ adapter->curr_window = 255; ++ adapter->ahw.qdr_sn_window = -1; ++ adapter->ahw.ddr_mn_window = -1; ++ ++ /* remap phys address */ ++ mem_base = pci_resource_start(pdev, 0); /* 0 is for BAR 0 */ ++ mem_len = pci_resource_len(pdev, 0); ++ pci_len0 = 0; ++ ++ /* 128 Meg of memory */ ++ if (mem_len == NETXEN_PCI_128MB_SIZE) { ++ mem_ptr0 = ioremap(mem_base, FIRST_PAGE_GROUP_SIZE); ++ mem_ptr1 = ioremap(mem_base + SECOND_PAGE_GROUP_START, ++ SECOND_PAGE_GROUP_SIZE); ++ mem_ptr2 = ioremap(mem_base + THIRD_PAGE_GROUP_START, ++ THIRD_PAGE_GROUP_SIZE); ++ } else if (mem_len == NETXEN_PCI_32MB_SIZE) { ++ mem_ptr1 = ioremap(mem_base, SECOND_PAGE_GROUP_SIZE); ++ mem_ptr2 = ioremap(mem_base + THIRD_PAGE_GROUP_START - ++ SECOND_PAGE_GROUP_START, THIRD_PAGE_GROUP_SIZE); ++ } else if (mem_len == NETXEN_PCI_2MB_SIZE) { ++ ++ mem_ptr0 = ioremap(mem_base, mem_len); ++ if (mem_ptr0 == NULL) { ++ dev_err(&pdev->dev, "failed to map PCI bar 0\n"); ++ return -EIO; ++ } ++ pci_len0 = mem_len; ++ ++ adapter->ahw.ddr_mn_window = 0; ++ adapter->ahw.qdr_sn_window = 0; ++ ++ adapter->ahw.mn_win_crb = NETXEN_PCI_CRBSPACE + ++ 0x100000 + PCIX_MN_WINDOW + (pci_func * 0x20); ++ adapter->ahw.ms_win_crb = NETXEN_PCI_CRBSPACE + ++ 0x100000 + PCIX_SN_WINDOW; ++ if (pci_func < 4) ++ adapter->ahw.ms_win_crb += (pci_func * 0x20); ++ else ++ adapter->ahw.ms_win_crb += ++ 0xA0 + ((pci_func - 4) * 0x10); ++ } else { ++ return -EIO; ++ } ++ ++ netxen_setup_hwops(adapter); ++ ++ dev_info(&pdev->dev, "%dMB memory map\n", (int)(mem_len>>20)); ++ ++ adapter->ahw.pci_base0 = mem_ptr0; ++ adapter->ahw.pci_len0 = pci_len0; ++ adapter->ahw.pci_base1 = mem_ptr1; ++ adapter->ahw.pci_base2 = mem_ptr2; ++ ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) ++ goto skip_doorbell; ++ ++ db_base = pci_resource_start(pdev, 4); /* doorbell is on bar 4 */ ++ db_len = pci_resource_len(pdev, 4); ++ ++ if (db_len == 0) { ++ printk(KERN_ERR "%s: doorbell is disabled\n", ++ netxen_nic_driver_name); ++ err = -EIO; ++ goto err_out; ++ } ++ ++ db_ptr = ioremap(db_base, NETXEN_DB_MAPSIZE_BYTES); ++ if (!db_ptr) { ++ printk(KERN_ERR "%s: Failed to allocate doorbell map.", ++ netxen_nic_driver_name); ++ err = -EIO; ++ goto err_out; ++ } ++ ++skip_doorbell: ++ adapter->ahw.db_base = db_ptr; ++ adapter->ahw.db_len = db_len; ++ return 0; ++ ++err_out: ++ netxen_cleanup_pci_map(adapter); ++ return err; ++} ++ ++static void ++netxen_check_options(struct netxen_adapter *adapter) ++{ ++ u32 fw_major, fw_minor, fw_build; ++ char brd_name[NETXEN_MAX_SHORT_NAME]; ++ char serial_num[32]; ++ int i, offset, val; ++ int *ptr32; ++ struct pci_dev *pdev = adapter->pdev; ++ ++ adapter->driver_mismatch = 0; ++ ++ ptr32 = (int *)&serial_num; ++ offset = NX_FW_SERIAL_NUM_OFFSET; ++ for (i = 0; i < 8; i++) { ++ if (netxen_rom_fast_read(adapter, offset, &val) == -1) { ++ dev_err(&pdev->dev, "error reading board info\n"); ++ adapter->driver_mismatch = 1; ++ return; ++ } ++ ptr32[i] = cpu_to_le32(val); ++ offset += sizeof(u32); ++ } ++ ++ fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR); ++ fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR); ++ fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB); ++ ++ adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build); ++ ++ if (adapter->portnum == 0) { ++ get_brd_name_by_type(adapter->ahw.board_type, brd_name); ++ ++ printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n", ++ brd_name, serial_num, adapter->ahw.revision_id); ++ } ++ ++ if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) { ++ adapter->driver_mismatch = 1; ++ dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n", ++ fw_major, fw_minor, fw_build); ++ return; ++ } ++ ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { ++ i = NXRD32(adapter, NETXEN_SRE_MISC); ++ adapter->ahw.cut_through = (i & 0x8000) ? 1 : 0; ++ } ++ ++ dev_info(&pdev->dev, "firmware v%d.%d.%d [%s]\n", ++ fw_major, fw_minor, fw_build, ++ adapter->ahw.cut_through ? "cut-through" : "legacy"); ++ ++ if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222)) ++ adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1); ++ ++ adapter->flags &= ~NETXEN_NIC_LRO_ENABLED; ++ ++ if (adapter->ahw.port_type == NETXEN_NIC_XGBE) { ++ adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G; ++ adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; ++ } else if (adapter->ahw.port_type == NETXEN_NIC_GBE) { ++ adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G; ++ adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; ++ } ++ ++ adapter->msix_supported = 0; ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { ++ adapter->msix_supported = !!use_msi_x; ++ adapter->rss_supported = !!use_msi_x; ++ } else if (adapter->fw_version >= NETXEN_VERSION_CODE(3, 4, 336)) { ++ switch (adapter->ahw.board_type) { ++ case NETXEN_BRDTYPE_P2_SB31_10G: ++ case NETXEN_BRDTYPE_P2_SB31_10G_CX4: ++ adapter->msix_supported = !!use_msi_x; ++ adapter->rss_supported = !!use_msi_x; ++ break; ++ default: ++ break; ++ } ++ } ++ ++ adapter->num_txd = MAX_CMD_DESCRIPTORS; ++ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { ++ adapter->num_lro_rxd = MAX_LRO_RCV_DESCRIPTORS; ++ adapter->max_rds_rings = 3; ++ } else { ++ adapter->num_lro_rxd = 0; ++ adapter->max_rds_rings = 2; ++ } ++} ++ ++static int ++netxen_start_firmware(struct netxen_adapter *adapter) ++{ ++ int val, err, first_boot; ++ struct pci_dev *pdev = adapter->pdev; ++ ++ /* required for NX2031 dummy dma */ ++ err = nx_set_dma_mask(adapter); ++ if (err) ++ return err; ++ ++ if (!netxen_can_start_firmware(adapter)) ++ goto wait_init; ++ ++ first_boot = NXRD32(adapter, NETXEN_CAM_RAM(0x1fc)); ++ ++ err = netxen_check_hw_init(adapter, first_boot); ++ if (err) { ++ dev_err(&pdev->dev, "error in init HW init sequence\n"); ++ return err; ++ } ++ ++ netxen_request_firmware(adapter); ++ ++ err = netxen_need_fw_reset(adapter); ++ if (err < 0) ++ goto err_out; ++ if (err == 0) ++ goto ready; ++ ++ if (first_boot != 0x55555555) { ++ NXWR32(adapter, CRB_CMDPEG_STATE, 0); ++ netxen_pinit_from_rom(adapter, 0); ++ msleep(1); ++ } ++ ++ NXWR32(adapter, CRB_DMA_SHIFT, 0x55555555); ++ NXWR32(adapter, NETXEN_PEG_HALT_STATUS1, 0); ++ NXWR32(adapter, NETXEN_PEG_HALT_STATUS2, 0); ++ ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) ++ netxen_set_port_mode(adapter); ++ ++ err = netxen_load_firmware(adapter); ++ if (err) ++ goto err_out; ++ ++ netxen_release_firmware(adapter); ++ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { ++ ++ /* Initialize multicast addr pool owners */ ++ val = 0x7654; ++ if (adapter->ahw.port_type == NETXEN_NIC_XGBE) ++ val |= 0x0f000000; ++ NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); ++ ++ } ++ ++ err = netxen_init_dummy_dma(adapter); ++ if (err) ++ goto err_out; ++ ++ /* ++ * Tell the hardware our version number. ++ */ ++ val = (_NETXEN_NIC_LINUX_MAJOR << 16) ++ | ((_NETXEN_NIC_LINUX_MINOR << 8)) ++ | (_NETXEN_NIC_LINUX_SUBVERSION); ++ NXWR32(adapter, CRB_DRIVER_VERSION, val); ++ ++ready: ++ NXWR32(adapter, NX_CRB_DEV_STATE, NX_DEV_READY); ++ ++wait_init: ++ /* Handshake with the card before we register the devices. */ ++ err = netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE); ++ if (err) { ++ netxen_free_dummy_dma(adapter); ++ goto err_out; ++ } ++ ++ nx_update_dma_mask(adapter); ++ ++ netxen_check_options(adapter); ++ ++ adapter->need_fw_reset = 0; ++ ++ /* fall through and release firmware */ ++ ++err_out: ++ netxen_release_firmware(adapter); ++ return err; ++} ++ ++static int ++netxen_nic_request_irq(struct netxen_adapter *adapter) ++{ ++ irq_handler_t handler; ++ struct nx_host_sds_ring *sds_ring; ++ int err, ring; ++ ++ unsigned long flags = IRQF_SAMPLE_RANDOM; ++ struct net_device *netdev = adapter->netdev; ++ struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; ++ ++ if (adapter->flags & NETXEN_NIC_MSIX_ENABLED) ++ handler = netxen_msix_intr; ++ else if (adapter->flags & NETXEN_NIC_MSI_ENABLED) ++ handler = netxen_msi_intr; ++ else { ++ flags |= IRQF_SHARED; ++ handler = netxen_intr; ++ } ++ adapter->irq = netdev->irq; ++ ++ for (ring = 0; ring < adapter->max_sds_rings; ring++) { ++ sds_ring = &recv_ctx->sds_rings[ring]; ++ sprintf(sds_ring->name, "%s[%d]", netdev->name, ring); ++ err = request_irq(sds_ring->irq, handler, ++ flags, sds_ring->name, sds_ring); ++ if (err) ++ return err; ++ } ++ ++ return 0; ++} ++ ++static void ++netxen_nic_free_irq(struct netxen_adapter *adapter) ++{ ++ int ring; ++ struct nx_host_sds_ring *sds_ring; ++ ++ struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; ++ ++ for (ring = 0; ring < adapter->max_sds_rings; ring++) { ++ sds_ring = &recv_ctx->sds_rings[ring]; ++ free_irq(sds_ring->irq, sds_ring); ++ } ++} ++ ++static void ++netxen_nic_init_coalesce_defaults(struct netxen_adapter *adapter) ++{ ++ adapter->coal.flags = NETXEN_NIC_INTR_DEFAULT; ++ adapter->coal.normal.data.rx_time_us = ++ NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US; ++ adapter->coal.normal.data.rx_packets = ++ NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS; ++ adapter->coal.normal.data.tx_time_us = ++ NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US; ++ adapter->coal.normal.data.tx_packets = ++ NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS; ++} ++ ++static int ++netxen_nic_up(struct netxen_adapter *adapter, struct net_device *netdev) ++{ ++ int err; ++ ++ if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) ++ return -EIO; ++ ++ err = adapter->init_port(adapter, adapter->physical_port); ++ if (err) { ++ printk(KERN_ERR "%s: Failed to initialize port %d\n", ++ netxen_nic_driver_name, adapter->portnum); ++ return err; ++ } ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ++ adapter->macaddr_set(adapter, netdev->dev_addr); ++ ++ adapter->set_multi(netdev); ++ adapter->set_mtu(adapter, netdev->mtu); ++ ++ adapter->ahw.linkup = 0; ++ ++ if (adapter->max_sds_rings > 1) ++ netxen_config_rss(adapter, 1); ++ ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) ++ netxen_config_intr_coalesce(adapter); ++ ++ if (adapter->capabilities & NX_FW_CAPABILITY_HW_LRO) ++ netxen_config_hw_lro(adapter, NETXEN_NIC_LRO_ENABLED); ++ ++ netxen_napi_enable(adapter); ++ ++#ifdef CONFIG_XEN ++ if (adapter->capabilities & NX_FW_CAPABILITY_BDG) ++ netxen_config_bridged_mode(adapter, 1); ++#endif ++ ++ if (adapter->capabilities & NX_FW_CAPABILITY_LINK_NOTIFICATION) ++ netxen_linkevent_request(adapter, 1); ++ else ++ netxen_nic_set_link_parameters(adapter); ++ ++ set_bit(__NX_DEV_UP, &adapter->state); ++ return 0; ++} ++ ++static void ++netxen_nic_down(struct netxen_adapter *adapter, struct net_device *netdev) ++{ ++ if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) ++ return; ++ ++ clear_bit(__NX_DEV_UP, &adapter->state); ++ ++ spin_lock(&adapter->tx_clean_lock); ++ netif_carrier_off(netdev); ++ netif_tx_disable(netdev); ++ ++ if (adapter->stop_port) ++ adapter->stop_port(adapter); ++ ++#ifdef CONFIG_XEN ++ if (adapter->capabilities & NX_FW_CAPABILITY_BDG) ++ netxen_config_bridged_mode(adapter, 0); ++#endif ++ ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) ++ netxen_p3_free_mac_list(adapter); ++ ++ adapter->set_promisc(adapter, NETXEN_NIU_NON_PROMISC_MODE); ++ ++ netxen_napi_disable(adapter); ++ ++ netxen_release_tx_buffers(adapter); ++ spin_unlock(&adapter->tx_clean_lock); ++} ++ ++ ++static int ++netxen_nic_attach(struct netxen_adapter *adapter) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct pci_dev *pdev = adapter->pdev; ++ int err, ring; ++ struct nx_host_rds_ring *rds_ring; ++ struct nx_host_tx_ring *tx_ring; ++ ++ if (adapter->is_up == NETXEN_ADAPTER_UP_MAGIC) ++ return 0; ++ ++ err = netxen_init_firmware(adapter); ++ if (err) ++ return err; ++ ++ err = netxen_napi_add(adapter, netdev); ++ if (err) ++ return err; ++ ++ err = netxen_alloc_sw_resources(adapter); ++ if (err) { ++ printk(KERN_ERR "%s: Error in setting sw resources\n", ++ netdev->name); ++ return err; ++ } ++ ++ err = netxen_alloc_hw_resources(adapter); ++ if (err) { ++ printk(KERN_ERR "%s: Error in setting hw resources\n", ++ netdev->name); ++ goto err_out_free_sw; ++ } ++ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { ++ tx_ring = adapter->tx_ring; ++ tx_ring->crb_cmd_producer = netxen_get_ioaddr(adapter, ++ crb_cmd_producer[adapter->portnum]); ++ tx_ring->crb_cmd_consumer = netxen_get_ioaddr(adapter, ++ crb_cmd_consumer[adapter->portnum]); ++ ++ tx_ring->producer = 0; ++ tx_ring->sw_consumer = 0; ++ ++ netxen_nic_update_cmd_producer(adapter, tx_ring); ++ netxen_nic_update_cmd_consumer(adapter, tx_ring); ++ } ++ ++ for (ring = 0; ring < adapter->max_rds_rings; ring++) { ++ rds_ring = &adapter->recv_ctx.rds_rings[ring]; ++ netxen_post_rx_buffers(adapter, ring, rds_ring); ++ } ++ ++ err = netxen_nic_request_irq(adapter); ++ if (err) { ++ dev_err(&pdev->dev, "%s: failed to setup interrupt\n", ++ netdev->name); ++ goto err_out_free_rxbuf; ++ } ++ ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) ++ netxen_nic_init_coalesce_defaults(adapter); ++ ++ netxen_create_sysfs_entries(adapter); ++ ++ adapter->is_up = NETXEN_ADAPTER_UP_MAGIC; ++ return 0; ++ ++err_out_free_rxbuf: ++ netxen_release_rx_buffers(adapter); ++ netxen_free_hw_resources(adapter); ++err_out_free_sw: ++ netxen_free_sw_resources(adapter); ++ return err; ++} ++ ++static void ++netxen_nic_detach(struct netxen_adapter *adapter) ++{ ++ if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) ++ return; ++ ++ netxen_remove_sysfs_entries(adapter); ++ ++ netxen_free_hw_resources(adapter); ++ netxen_release_rx_buffers(adapter); ++ netxen_nic_free_irq(adapter); ++ netxen_napi_del(adapter); ++ netxen_free_sw_resources(adapter); ++ ++ adapter->is_up = 0; ++} ++ ++int ++netxen_nic_reset_context(struct netxen_adapter *adapter) ++{ ++ int err = 0; ++ struct net_device *netdev = adapter->netdev; ++ ++ if (test_and_set_bit(__NX_RESETTING, &adapter->state)) ++ return -EBUSY; ++ ++ if (adapter->is_up == NETXEN_ADAPTER_UP_MAGIC) { ++ ++ netif_device_detach(netdev); ++ ++ if (netif_running(netdev)) ++ netxen_nic_down(adapter, netdev); ++ ++ netxen_nic_detach(adapter); ++ ++ if (netif_running(netdev)) { ++ err = netxen_nic_attach(adapter); ++ if (!err) ++ err = netxen_nic_up(adapter, netdev); ++ ++ if (err) ++ goto done; ++ } ++ ++ netif_device_attach(netdev); ++ } ++ ++done: ++ clear_bit(__NX_RESETTING, &adapter->state); ++ return err; ++} ++ ++static int ++netxen_setup_netdev(struct netxen_adapter *adapter, ++ struct net_device *netdev) ++{ ++ int err = 0; ++ struct pci_dev *pdev = adapter->pdev; ++ ++ adapter->rx_csum = 1; ++ adapter->mc_enabled = 0; ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) ++ adapter->max_mc_count = 38; ++ else ++ adapter->max_mc_count = 16; ++ ++ netdev->open = netxen_nic_open; ++ netdev->stop = netxen_nic_close; ++ netdev->hard_start_xmit = netxen_nic_xmit_frame; ++ netdev->get_stats = netxen_nic_get_stats; ++ netdev->set_multicast_list = netxen_set_multicast_list; ++ netdev->set_mac_address = netxen_nic_set_mac; ++ netdev->change_mtu = netxen_nic_change_mtu; ++ netdev->tx_timeout = netxen_tx_timeout; ++ netdev->watchdog_timeo = 2*HZ; ++ ++ netxen_nic_change_mtu(netdev, netdev->mtu); ++ ++ SET_ETHTOOL_OPS(netdev, &netxen_nic_ethtool_ops); ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ netdev->poll_controller = netxen_nic_poll_controller; ++#endif ++ ++ netdev->features |= (NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO); ++ netdev->vlan_features |= (NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO); ++ ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { ++ netdev->features |= (NETIF_F_IPV6_CSUM | NETIF_F_TSO6); ++ netdev->vlan_features |= (NETIF_F_IPV6_CSUM | NETIF_F_TSO6); ++ } ++ ++ if (adapter->pci_using_dac) { ++ netdev->features |= NETIF_F_HIGHDMA; ++ netdev->vlan_features |= NETIF_F_HIGHDMA; ++ } ++ ++ if (adapter->capabilities & NX_FW_CAPABILITY_FVLANTX) ++ netdev->features |= (NETIF_F_HW_VLAN_TX); ++ ++ if (adapter->capabilities & NX_FW_CAPABILITY_HW_LRO) ++ netdev->features |= NETIF_F_LRO; ++ ++ netdev->irq = adapter->msix_entries[0].vector; ++ ++ INIT_WORK(&adapter->tx_timeout_task, netxen_tx_timeout_task); ++ ++ if (netxen_read_mac_addr(adapter)) ++ dev_warn(&pdev->dev, "failed to read mac addr\n"); ++ ++ netif_carrier_off(netdev); ++ netif_stop_queue(netdev); ++ ++ err = register_netdev(netdev); ++ if (err) { ++ dev_err(&pdev->dev, "failed to register net device\n"); ++ return err; ++ } ++ ++ return 0; ++} ++ + static int __devinit + netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + { + struct net_device *netdev = NULL; + struct netxen_adapter *adapter = NULL; +- void __iomem *mem_ptr0 = NULL; +- void __iomem *mem_ptr1 = NULL; +- void __iomem *mem_ptr2 = NULL; +- unsigned long first_page_group_end; +- unsigned long first_page_group_start; +- +- +- u8 __iomem *db_ptr = NULL; +- unsigned long mem_base, mem_len, db_base, db_len, pci_len0 = 0; + int i = 0, err; +- int first_driver, first_boot; +- u32 val; + int pci_func_id = PCI_FUNC(pdev->devfn); +- struct netxen_legacy_intr_set *legacy_intrp; + uint8_t revision_id; +- +- if (pci_func_id == 0) +- printk(KERN_INFO "%s\n", netxen_nic_driver_string); + + if (pdev->class != 0x020000) { + printk(KERN_DEBUG "NetXen function %d, class %x will not " +@@ -558,15 +1239,14 @@ + + netdev = alloc_etherdev(sizeof(struct netxen_adapter)); + if(!netdev) { +- printk(KERN_ERR"%s: Failed to allocate memory for the " +- "device block.Check system memory resource" +- " usage.\n", netxen_nic_driver_name); ++ dev_err(&pdev->dev, "failed to allocate net_device\n"); ++ err = -ENOMEM; + goto err_out_free_res; + } + + SET_NETDEV_DEV(netdev, &pdev->dev); + +- adapter = netdev->priv; ++ adapter = netdev_priv(netdev); + adapter->netdev = netdev; + adapter->pdev = pdev; + adapter->ahw.pci_func = pci_func_id; +@@ -574,185 +1254,25 @@ + revision_id = pdev->revision; + adapter->ahw.revision_id = revision_id; + +- err = nx_set_dma_mask(adapter, revision_id); ++ rwlock_init(&adapter->adapter_lock); ++ spin_lock_init(&adapter->tx_clean_lock); ++ INIT_LIST_HEAD(&adapter->mac_list); ++ ++ err = netxen_setup_pci_map(adapter); + if (err) + goto err_out_free_netdev; + +- rwlock_init(&adapter->adapter_lock); +- adapter->ahw.qdr_sn_window = -1; +- adapter->ahw.ddr_mn_window = -1; +- +- /* remap phys address */ +- mem_base = pci_resource_start(pdev, 0); /* 0 is for BAR 0 */ +- mem_len = pci_resource_len(pdev, 0); +- pci_len0 = 0; +- +- adapter->hw_write_wx = netxen_nic_hw_write_wx_128M; +- adapter->hw_read_wx = netxen_nic_hw_read_wx_128M; +- adapter->pci_read_immediate = netxen_nic_pci_read_immediate_128M; +- adapter->pci_write_immediate = netxen_nic_pci_write_immediate_128M; +- adapter->pci_read_normalize = netxen_nic_pci_read_normalize_128M; +- adapter->pci_write_normalize = netxen_nic_pci_write_normalize_128M; +- adapter->pci_set_window = netxen_nic_pci_set_window_128M; +- adapter->pci_mem_read = netxen_nic_pci_mem_read_128M; +- adapter->pci_mem_write = netxen_nic_pci_mem_write_128M; +- +- /* 128 Meg of memory */ +- if (mem_len == NETXEN_PCI_128MB_SIZE) { +- mem_ptr0 = ioremap(mem_base, FIRST_PAGE_GROUP_SIZE); +- mem_ptr1 = ioremap(mem_base + SECOND_PAGE_GROUP_START, +- SECOND_PAGE_GROUP_SIZE); +- mem_ptr2 = ioremap(mem_base + THIRD_PAGE_GROUP_START, +- THIRD_PAGE_GROUP_SIZE); +- first_page_group_start = FIRST_PAGE_GROUP_START; +- first_page_group_end = FIRST_PAGE_GROUP_END; +- } else if (mem_len == NETXEN_PCI_32MB_SIZE) { +- mem_ptr1 = ioremap(mem_base, SECOND_PAGE_GROUP_SIZE); +- mem_ptr2 = ioremap(mem_base + THIRD_PAGE_GROUP_START - +- SECOND_PAGE_GROUP_START, THIRD_PAGE_GROUP_SIZE); +- first_page_group_start = 0; +- first_page_group_end = 0; +- } else if (mem_len == NETXEN_PCI_2MB_SIZE) { +- adapter->hw_write_wx = netxen_nic_hw_write_wx_2M; +- adapter->hw_read_wx = netxen_nic_hw_read_wx_2M; +- adapter->pci_read_immediate = netxen_nic_pci_read_immediate_2M; +- adapter->pci_write_immediate = +- netxen_nic_pci_write_immediate_2M; +- adapter->pci_read_normalize = netxen_nic_pci_read_normalize_2M; +- adapter->pci_write_normalize = +- netxen_nic_pci_write_normalize_2M; +- adapter->pci_set_window = netxen_nic_pci_set_window_2M; +- adapter->pci_mem_read = netxen_nic_pci_mem_read_2M; +- adapter->pci_mem_write = netxen_nic_pci_mem_write_2M; +- +- mem_ptr0 = ioremap(mem_base, mem_len); +- pci_len0 = mem_len; +- first_page_group_start = 0; +- first_page_group_end = 0; +- +- adapter->ahw.ddr_mn_window = 0; +- adapter->ahw.qdr_sn_window = 0; +- +- adapter->ahw.mn_win_crb = 0x100000 + PCIX_MN_WINDOW + +- (pci_func_id * 0x20); +- adapter->ahw.ms_win_crb = 0x100000 + PCIX_SN_WINDOW; +- if (pci_func_id < 4) +- adapter->ahw.ms_win_crb += (pci_func_id * 0x20); +- else +- adapter->ahw.ms_win_crb += +- 0xA0 + ((pci_func_id - 4) * 0x10); +- } else { +- err = -EIO; +- goto err_out_free_netdev; +- } +- +- dev_info(&pdev->dev, "%dMB memory map\n", (int)(mem_len>>20)); +- +- db_base = pci_resource_start(pdev, 4); /* doorbell is on bar 4 */ +- db_len = pci_resource_len(pdev, 4); +- +- if (db_len == 0) { +- printk(KERN_ERR "%s: doorbell is disabled\n", +- netxen_nic_driver_name); +- err = -EIO; +- goto err_out_iounmap; +- } +- DPRINTK(INFO, "doorbell ioremap from %lx a size of %lx\n", db_base, +- db_len); +- +- db_ptr = ioremap(db_base, NETXEN_DB_MAPSIZE_BYTES); +- if (!db_ptr) { +- printk(KERN_ERR "%s: Failed to allocate doorbell map.", +- netxen_nic_driver_name); +- err = -EIO; +- goto err_out_iounmap; +- } +- DPRINTK(INFO, "doorbell ioremaped at %p\n", db_ptr); +- +- adapter->ahw.pci_base0 = mem_ptr0; +- adapter->ahw.pci_len0 = pci_len0; +- adapter->ahw.first_page_group_start = first_page_group_start; +- adapter->ahw.first_page_group_end = first_page_group_end; +- adapter->ahw.pci_base1 = mem_ptr1; +- adapter->ahw.pci_base2 = mem_ptr2; +- adapter->ahw.db_base = db_ptr; +- adapter->ahw.db_len = db_len; +- +- netif_napi_add(netdev, &adapter->napi, +- netxen_nic_poll, NETXEN_NETDEV_WEIGHT); +- +- if (revision_id >= NX_P3_B0) +- legacy_intrp = &legacy_intr[pci_func_id]; +- else +- legacy_intrp = &legacy_intr[0]; +- +- adapter->legacy_intr.int_vec_bit = legacy_intrp->int_vec_bit; +- adapter->legacy_intr.tgt_status_reg = legacy_intrp->tgt_status_reg; +- adapter->legacy_intr.tgt_mask_reg = legacy_intrp->tgt_mask_reg; +- adapter->legacy_intr.pci_int_reg = legacy_intrp->pci_int_reg; +- +- /* this will be read from FW later */ +- adapter->intr_scheme = -1; +- adapter->msi_mode = -1; +- + /* This will be reset for mezz cards */ + adapter->portnum = pci_func_id; +- adapter->status &= ~NETXEN_NETDEV_STATUS; +- adapter->rx_csum = 1; +- adapter->mc_enabled = 0; +- if (NX_IS_REVISION_P3(revision_id)) +- adapter->max_mc_count = 38; +- else +- adapter->max_mc_count = 16; + +- netdev->open = netxen_nic_open; +- netdev->stop = netxen_nic_close; +- netdev->hard_start_xmit = netxen_nic_xmit_frame; +- netdev->get_stats = netxen_nic_get_stats; +- if (NX_IS_REVISION_P3(revision_id)) +- netdev->set_multicast_list = netxen_p3_nic_set_multi; +- else +- netdev->set_multicast_list = netxen_p2_nic_set_multi; +- netdev->set_mac_address = netxen_nic_set_mac; +- netdev->change_mtu = netxen_nic_change_mtu; +- netdev->tx_timeout = netxen_tx_timeout; +- netdev->watchdog_timeo = 2*HZ; +- +- netxen_nic_change_mtu(netdev, netdev->mtu); +- +- SET_ETHTOOL_OPS(netdev, &netxen_nic_ethtool_ops); +-#ifdef CONFIG_NET_POLL_CONTROLLER +- netdev->poll_controller = netxen_nic_poll_controller; +-#endif +- /* ScatterGather support */ +- netdev->features = NETIF_F_SG; +- netdev->features |= NETIF_F_IP_CSUM; +- netdev->features |= NETIF_F_TSO; +- if (NX_IS_REVISION_P3(revision_id)) { +- netdev->features |= NETIF_F_IPV6_CSUM; +- netdev->features |= NETIF_F_TSO6; +- } +- +- if (adapter->pci_using_dac) +- netdev->features |= NETIF_F_HIGHDMA; +- +- /* +- * Set the CRB window to invalid. If any register in window 0 is +- * accessed it should set the window to 0 and then reset it to 1. +- */ +- adapter->curr_window = 255; +- +- if (netxen_nic_get_board_info(adapter) != 0) { +- printk("%s: Error getting board config info.\n", +- netxen_nic_driver_name); +- err = -EIO; ++ err = netxen_nic_get_board_info(adapter); ++ if (err) { ++ dev_err(&pdev->dev, "Error getting board config info.\n"); + goto err_out_iounmap; + } + +- netxen_initialize_adapter_ops(adapter); +- + /* Mezz cards have PCI function 0,2,3 enabled */ +- switch (adapter->ahw.boardcfg.board_type) { ++ switch (adapter->ahw.board_type) { + case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: + case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: + if (pci_func_id >= 2) +@@ -762,158 +1282,33 @@ + break; + } + +- /* +- * This call will setup various max rx/tx counts. +- * It must be done before any buffer/ring allocations. +- */ +- netxen_check_options(adapter); +- +- first_driver = 0; +- if (NX_IS_REVISION_P3(revision_id)) { +- if (adapter->ahw.pci_func == 0) +- first_driver = 1; +- } else { +- if (adapter->portnum == 0) +- first_driver = 1; +- } +- +- if (first_driver) { +- first_boot = adapter->pci_read_normalize(adapter, +- NETXEN_CAM_RAM(0x1fc)); +- +- err = netxen_check_hw_init(adapter, first_boot); +- if (err) { +- printk(KERN_ERR "%s: error in init HW init sequence\n", +- netxen_nic_driver_name); +- goto err_out_iounmap; +- } +- +- if (NX_IS_REVISION_P3(revision_id)) +- netxen_set_port_mode(adapter); +- +- if (first_boot != 0x55555555) { +- adapter->pci_write_normalize(adapter, +- CRB_CMDPEG_STATE, 0); +- netxen_pinit_from_rom(adapter, 0); +- msleep(1); +- } +- netxen_load_firmware(adapter); +- +- if (NX_IS_REVISION_P3(revision_id)) +- netxen_pcie_strap_init(adapter); +- +- if (NX_IS_REVISION_P2(revision_id)) { +- +- /* Initialize multicast addr pool owners */ +- val = 0x7654; +- if (adapter->ahw.board_type == NETXEN_NIC_XGBE) +- val |= 0x0f000000; +- netxen_crb_writelit_adapter(adapter, +- NETXEN_MAC_ADDR_CNTL_REG, val); +- +- } +- +- err = netxen_initialize_adapter_offload(adapter); +- if (err) +- goto err_out_iounmap; +- +- /* +- * Tell the hardware our version number. +- */ +- i = (_NETXEN_NIC_LINUX_MAJOR << 16) +- | ((_NETXEN_NIC_LINUX_MINOR << 8)) +- | (_NETXEN_NIC_LINUX_SUBVERSION); +- adapter->pci_write_normalize(adapter, CRB_DRIVER_VERSION, i); +- +- /* Handshake with the card before we register the devices. */ +- err = netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE); +- if (err) +- goto err_out_free_offload; +- +- } /* first_driver */ +- +- netxen_nic_flash_print(adapter); +- +- if (NX_IS_REVISION_P3(revision_id)) { +- adapter->hw_read_wx(adapter, +- NETXEN_MIU_MN_CONTROL, &val, 4); +- adapter->ahw.cut_through = (val & 0x4) ? 1 : 0; +- dev_info(&pdev->dev, "firmware running in %s mode\n", +- adapter->ahw.cut_through ? "cut through" : "legacy"); +- } ++ err = netxen_start_firmware(adapter); ++ if (err) ++ goto err_out_iounmap; + + /* + * See if the firmware gave us a virtual-physical port mapping. + */ + adapter->physical_port = adapter->portnum; +- i = adapter->pci_read_normalize(adapter, CRB_V2P(adapter->portnum)); +- if (i != 0x55555555) +- adapter->physical_port = i; +- +- adapter->flags &= ~(NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED); +- +- netxen_set_msix_bit(pdev, 0); +- +- if (NX_IS_REVISION_P3(revision_id)) { +- if ((mem_len != NETXEN_PCI_128MB_SIZE) && +- mem_len != NETXEN_PCI_2MB_SIZE) +- adapter->msix_supported = 0; ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { ++ i = NXRD32(adapter, CRB_V2P(adapter->portnum)); ++ if (i != 0x55555555) ++ adapter->physical_port = i; + } + +- if (adapter->msix_supported) { ++ netxen_nic_clear_stats(adapter); + +- netxen_init_msix_entries(adapter); ++ netxen_setup_intr(adapter); + +- if (pci_enable_msix(pdev, adapter->msix_entries, +- MSIX_ENTRIES_PER_ADAPTER)) +- goto request_msi; +- +- adapter->flags |= NETXEN_NIC_MSIX_ENABLED; +- netxen_set_msix_bit(pdev, 1); +- dev_info(&pdev->dev, "using msi-x interrupts\n"); +- +- } else { +-request_msi: +- if (use_msi && !pci_enable_msi(pdev)) { +- adapter->flags |= NETXEN_NIC_MSI_ENABLED; +- dev_info(&pdev->dev, "using msi interrupts\n"); +- } else +- dev_info(&pdev->dev, "using legacy interrupts\n"); +- } +- +- if (adapter->flags & NETXEN_NIC_MSIX_ENABLED) +- netdev->irq = adapter->msix_entries[0].vector; +- else +- netdev->irq = pdev->irq; +- +- err = netxen_receive_peg_ready(adapter); ++ err = netxen_setup_netdev(adapter, netdev); + if (err) + goto err_out_disable_msi; + +- init_timer(&adapter->watchdog_timer); +- adapter->watchdog_timer.function = &netxen_watchdog; +- adapter->watchdog_timer.data = (unsigned long)adapter; +- INIT_WORK(&adapter->watchdog_task, netxen_watchdog_task); +- INIT_WORK(&adapter->tx_timeout_task, netxen_tx_timeout_task); +- +- err = netxen_read_mac_addr(adapter); +- if (err) +- dev_warn(&pdev->dev, "failed to read mac addr\n"); +- +- netif_carrier_off(netdev); +- netif_stop_queue(netdev); +- +- if ((err = register_netdev(netdev))) { +- printk(KERN_ERR "%s: register_netdev failed port #%d" +- " aborting\n", netxen_nic_driver_name, +- adapter->portnum); +- err = -EIO; +- goto err_out_disable_msi; +- } +- + pci_set_drvdata(pdev, adapter); + +- switch (adapter->ahw.board_type) { ++ netxen_schedule_work(adapter, netxen_fw_poll_work, FW_POLL_DELAY); ++ ++ switch (adapter->ahw.port_type) { + case NETXEN_NIC_GBE: + dev_info(&adapter->pdev->dev, "%s: GbE port initialized\n", + adapter->netdev->name); +@@ -927,25 +1322,14 @@ + return 0; + + err_out_disable_msi: +- if (adapter->flags & NETXEN_NIC_MSIX_ENABLED) +- pci_disable_msix(pdev); +- if (adapter->flags & NETXEN_NIC_MSI_ENABLED) +- pci_disable_msi(pdev); ++ netxen_teardown_intr(adapter); + +-err_out_free_offload: +- if (first_driver) +- netxen_free_adapter_offload(adapter); ++ netxen_free_dummy_dma(adapter); ++ ++ nx_decr_dev_ref_cnt(adapter); + + err_out_iounmap: +- if (db_ptr) +- iounmap(db_ptr); +- +- if (mem_ptr0) +- iounmap(mem_ptr0); +- if (mem_ptr1) +- iounmap(mem_ptr1); +- if (mem_ptr2) +- iounmap(mem_ptr2); ++ netxen_cleanup_pci_map(adapter); + + err_out_free_netdev: + free_netdev(netdev); +@@ -970,34 +1354,26 @@ + + netdev = adapter->netdev; + ++ netxen_cancel_fw_work(adapter); ++ + unregister_netdev(netdev); + +- if (adapter->is_up == NETXEN_ADAPTER_UP_MAGIC) { +- netxen_free_hw_resources(adapter); +- netxen_release_rx_buffers(adapter); +- netxen_free_sw_resources(adapter); ++ cancel_work_sync(&adapter->tx_timeout_task); + +- if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) +- netxen_p3_free_mac_list(adapter); +- } ++ netxen_nic_detach(adapter); ++ ++ nx_decr_dev_ref_cnt(adapter); + + if (adapter->portnum == 0) +- netxen_free_adapter_offload(adapter); ++ netxen_free_dummy_dma(adapter); + +- if (adapter->irq) +- free_irq(adapter->irq, adapter); ++ clear_bit(__NX_RESETTING, &adapter->state); + +- if (adapter->flags & NETXEN_NIC_MSIX_ENABLED) +- pci_disable_msix(pdev); +- if (adapter->flags & NETXEN_NIC_MSI_ENABLED) +- pci_disable_msi(pdev); ++ netxen_teardown_intr(adapter); + +- iounmap(adapter->ahw.db_base); +- iounmap(adapter->ahw.pci_base0); +- if (adapter->ahw.pci_base1 != NULL) +- iounmap(adapter->ahw.pci_base1); +- if (adapter->ahw.pci_base2 != NULL) +- iounmap(adapter->ahw.pci_base2); ++ netxen_cleanup_pci_map(adapter); ++ ++ netxen_release_firmware(adapter); + + pci_release_regions(pdev); + pci_disable_device(pdev); +@@ -1005,124 +1381,130 @@ + + free_netdev(netdev); + } ++static int __netxen_nic_shutdown(struct pci_dev *pdev) ++{ ++ struct netxen_adapter *adapter = pci_get_drvdata(pdev); ++ struct net_device *netdev = adapter->netdev; ++ int retval; + +-/* +- * Called when a network interface is made active +- * @returns 0 on success, negative value on failure +- */ ++ netif_device_detach(netdev); ++ ++ netxen_cancel_fw_work(adapter); ++ ++ if (netif_running(netdev)) ++ netxen_nic_down(adapter, netdev); ++ ++ cancel_work_sync(&adapter->tx_timeout_task); ++ ++ netxen_nic_detach(adapter); ++ ++ if (adapter->portnum == 0) ++ netxen_free_dummy_dma(adapter); ++ ++ nx_decr_dev_ref_cnt(adapter); ++ ++ clear_bit(__NX_RESETTING, &adapter->state); ++ ++ retval = pci_save_state(pdev); ++ if (retval) ++ return retval; ++ ++ if (netxen_nic_wol_supported(adapter)) { ++ pci_enable_wake(pdev, PCI_D3cold, 1); ++ pci_enable_wake(pdev, PCI_D3hot, 1); ++ } ++ ++ pci_disable_device(pdev); ++ ++ return 0; ++} ++static void netxen_nic_shutdown(struct pci_dev *pdev) ++{ ++ if (__netxen_nic_shutdown(pdev)) ++ return; ++} ++#ifdef CONFIG_PM ++static int ++netxen_nic_suspend(struct pci_dev *pdev, pm_message_t state) ++{ ++ int retval; ++ ++ retval = __netxen_nic_shutdown(pdev); ++ if (retval) ++ return retval; ++ ++ pci_set_power_state(pdev, pci_choose_state(pdev, state)); ++ return 0; ++} ++ ++static int ++netxen_nic_resume(struct pci_dev *pdev) ++{ ++ struct netxen_adapter *adapter = pci_get_drvdata(pdev); ++ struct net_device *netdev = adapter->netdev; ++ int err; ++ ++ pci_set_power_state(pdev, PCI_D0); ++ pci_restore_state(pdev); ++ ++ err = pci_enable_device(pdev); ++ if (err) ++ return err; ++ ++ adapter->curr_window = 255; ++ ++ err = netxen_start_firmware(adapter); ++ if (err) { ++ dev_err(&pdev->dev, "failed to start firmware\n"); ++ return err; ++ } ++ ++ if (netif_running(netdev)) { ++ err = netxen_nic_attach(adapter); ++ if (err) ++ goto err_out; ++ ++ err = netxen_nic_up(adapter, netdev); ++ if (err) ++ goto err_out_detach; ++ ++ netif_device_attach(netdev); ++ ++ netxen_config_indev_addr(netdev, NETDEV_UP); ++ } ++ ++ netxen_schedule_work(adapter, netxen_fw_poll_work, FW_POLL_DELAY); ++ ++err_out_detach: ++ netxen_nic_detach(adapter); ++err_out: ++ nx_decr_dev_ref_cnt(adapter); ++ return err; ++} ++#endif ++ + static int netxen_nic_open(struct net_device *netdev) + { +- struct netxen_adapter *adapter = (struct netxen_adapter *)netdev->priv; ++ struct netxen_adapter *adapter = netdev_priv(netdev); + int err = 0; +- int ctx, ring; +- irq_handler_t handler; +- unsigned long flags = IRQF_SAMPLE_RANDOM; + + if (adapter->driver_mismatch) + return -EIO; + +- if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) { +- err = netxen_init_firmware(adapter); +- if (err != 0) { +- printk(KERN_ERR "Failed to init firmware\n"); +- return -EIO; +- } ++ err = netxen_nic_attach(adapter); ++ if (err) ++ return err; + +- if (adapter->fw_major < 4) +- adapter->max_rds_rings = 3; +- else +- adapter->max_rds_rings = 2; +- +- err = netxen_alloc_sw_resources(adapter); +- if (err) { +- printk(KERN_ERR "%s: Error in setting sw resources\n", +- netdev->name); +- return err; +- } +- +- netxen_nic_clear_stats(adapter); +- +- err = netxen_alloc_hw_resources(adapter); +- if (err) { +- printk(KERN_ERR "%s: Error in setting hw resources\n", +- netdev->name); +- goto err_out_free_sw; +- } +- +- if ((adapter->msi_mode != MSI_MODE_MULTIFUNC) || +- (adapter->intr_scheme != INTR_SCHEME_PERPORT)) { +- printk(KERN_ERR "%s: Firmware interrupt scheme is " +- "incompatible with driver\n", +- netdev->name); +- adapter->driver_mismatch = 1; +- goto err_out_free_hw; +- } +- +- if (adapter->fw_major < 4) { +- adapter->crb_addr_cmd_producer = +- crb_cmd_producer[adapter->portnum]; +- adapter->crb_addr_cmd_consumer = +- crb_cmd_consumer[adapter->portnum]; +- +- netxen_nic_update_cmd_producer(adapter, 0); +- netxen_nic_update_cmd_consumer(adapter, 0); +- } +- +- for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { +- for (ring = 0; ring < adapter->max_rds_rings; ring++) +- netxen_post_rx_buffers(adapter, ctx, ring); +- } +- if (NETXEN_IS_MSI_FAMILY(adapter)) +- handler = netxen_msi_intr; +- else { +- flags |= IRQF_SHARED; +- handler = netxen_intr; +- } +- adapter->irq = netdev->irq; +- err = request_irq(adapter->irq, handler, +- flags, netdev->name, adapter); +- if (err) { +- printk(KERN_ERR "request_irq failed with: %d\n", err); +- goto err_out_free_rxbuf; +- } +- +- adapter->is_up = NETXEN_ADAPTER_UP_MAGIC; +- } +- +- /* Done here again so that even if phantom sw overwrote it, +- * we set it */ +- err = adapter->init_port(adapter, adapter->physical_port); +- if (err) { +- printk(KERN_ERR "%s: Failed to initialize port %d\n", +- netxen_nic_driver_name, adapter->portnum); +- goto err_out_free_irq; +- } +- adapter->macaddr_set(adapter, netdev->dev_addr); +- +- netxen_nic_set_link_parameters(adapter); +- +- netdev->set_multicast_list(netdev); +- if (adapter->set_mtu) +- adapter->set_mtu(adapter, netdev->mtu); +- +- adapter->ahw.linkup = 0; +- mod_timer(&adapter->watchdog_timer, jiffies); +- +- napi_enable(&adapter->napi); +- netxen_nic_enable_int(adapter); ++ err = netxen_nic_up(adapter, netdev); ++ if (err) ++ goto err_out; + + netif_start_queue(netdev); + + return 0; + +-err_out_free_irq: +- free_irq(adapter->irq, adapter); +-err_out_free_rxbuf: +- netxen_release_rx_buffers(adapter); +-err_out_free_hw: +- netxen_free_hw_resources(adapter); +-err_out_free_sw: +- netxen_free_sw_resources(adapter); ++err_out: ++ netxen_nic_detach(adapter); + return err; + } + +@@ -1133,59 +1515,68 @@ + { + struct netxen_adapter *adapter = netdev_priv(netdev); + +- netif_carrier_off(netdev); +- netif_stop_queue(netdev); +- napi_disable(&adapter->napi); +- +- if (adapter->stop_port) +- adapter->stop_port(adapter); +- +- netxen_nic_disable_int(adapter); +- +- netxen_release_tx_buffers(adapter); +- +- FLUSH_SCHEDULED_WORK(); +- del_timer_sync(&adapter->watchdog_timer); +- ++ netxen_nic_down(adapter, netdev); + return 0; + } + +-static bool netxen_tso_check(struct net_device *netdev, +- struct cmd_desc_type0 *desc, struct sk_buff *skb) ++static void ++netxen_tso_check(struct net_device *netdev, ++ struct nx_host_tx_ring *tx_ring, ++ struct cmd_desc_type0 *first_desc, ++ struct sk_buff *skb) + { +- bool tso = false; + u8 opcode = TX_ETHER_PKT; + __be16 protocol = skb->protocol; +- u16 flags = 0; ++ u16 flags = 0, vid = 0; ++ u32 producer; ++ int copied, offset, copy_len, hdr_len = 0, tso = 0, vlan_oob = 0; ++ struct cmd_desc_type0 *hwdesc; ++ struct vlan_ethhdr *vh; + +- if (protocol == __constant_htons(ETH_P_8021Q)) { +- struct vlan_ethhdr *vh = (struct vlan_ethhdr *)skb->data; ++ if (protocol == cpu_to_be16(ETH_P_8021Q)) { ++ ++ vh = (struct vlan_ethhdr *)skb->data; + protocol = vh->h_vlan_encapsulated_proto; + flags = FLAGS_VLAN_TAGGED; ++ ++ } else if (vlan_tx_tag_present(skb)) { ++ ++ flags = FLAGS_VLAN_OOB; ++ vid = vlan_tx_tag_get(skb); ++ netxen_set_tx_vlan_tci(first_desc, vid); ++ vlan_oob = 1; + } + + if ((netdev->features & (NETIF_F_TSO | NETIF_F_TSO6)) && + skb_shinfo(skb)->gso_size > 0) { + +- desc->mss = cpu_to_le16(skb_shinfo(skb)->gso_size); +- desc->total_hdr_length = +- skb_transport_offset(skb) + tcp_hdrlen(skb); ++ hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); + +- opcode = (protocol == __constant_htons(ETH_P_IPV6)) ? ++ first_desc->mss = cpu_to_le16(skb_shinfo(skb)->gso_size); ++ first_desc->total_hdr_length = hdr_len; ++ if (vlan_oob) { ++ first_desc->total_hdr_length += VLAN_HLEN; ++ first_desc->tcp_hdr_offset = VLAN_HLEN; ++ first_desc->ip_hdr_offset = VLAN_HLEN; ++ /* Only in case of TSO on vlan device */ ++ flags |= FLAGS_VLAN_TAGGED; ++ } ++ ++ opcode = (protocol == cpu_to_be16(ETH_P_IPV6)) ? + TX_TCP_LSO6 : TX_TCP_LSO; +- tso = true; ++ tso = 1; + + } else if (skb->ip_summed == CHECKSUM_PARTIAL) { + u8 l4proto; + +- if (protocol == __constant_htons(ETH_P_IP)) { ++ if (protocol == cpu_to_be16(ETH_P_IP)) { + l4proto = ip_hdr(skb)->protocol; + + if (l4proto == IPPROTO_TCP) + opcode = TX_TCP_PKT; + else if(l4proto == IPPROTO_UDP) + opcode = TX_UDP_PKT; +- } else if (protocol == __constant_htons(ETH_P_IPV6)) { ++ } else if (protocol == cpu_to_be16(ETH_P_IPV6)) { + l4proto = ipv6_hdr(skb)->nexthdr; + + if (l4proto == IPPROTO_TCP) +@@ -1194,180 +1585,199 @@ + opcode = TX_UDPV6_PKT; + } + } +- desc->tcp_hdr_offset = skb_transport_offset(skb); +- desc->ip_hdr_offset = skb_network_offset(skb); +- netxen_set_tx_flags_opcode(desc, flags, opcode); +- return tso; +-} + +-static void +-netxen_clean_tx_dma_mapping(struct pci_dev *pdev, +- struct netxen_cmd_buffer *pbuf, int last) +-{ +- int k; +- struct netxen_skb_frag *buffrag; ++ first_desc->tcp_hdr_offset += skb_transport_offset(skb); ++ first_desc->ip_hdr_offset += skb_network_offset(skb); ++ netxen_set_tx_flags_opcode(first_desc, flags, opcode); + +- buffrag = &pbuf->frag_array[0]; +- pci_unmap_single(pdev, buffrag->dma, +- buffrag->length, PCI_DMA_TODEVICE); +- +- for (k = 1; k < last; k++) { +- buffrag = &pbuf->frag_array[k]; +- pci_unmap_page(pdev, buffrag->dma, +- buffrag->length, PCI_DMA_TODEVICE); +- } +-} +- +-static int netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev) +-{ +- struct netxen_adapter *adapter = netdev_priv(netdev); +- struct netxen_hardware_context *hw = &adapter->ahw; +- unsigned int first_seg_len = skb->len - skb->data_len; +- struct netxen_cmd_buffer *pbuf; +- struct netxen_skb_frag *buffrag; +- struct cmd_desc_type0 *hwdesc; +- struct pci_dev *pdev = adapter->pdev; +- dma_addr_t temp_dma; +- int i, k; +- +- u32 producer, consumer; +- int frag_count, no_of_desc; +- u32 num_txd = adapter->max_tx_desc_count; +- bool is_tso = false; +- +- frag_count = skb_shinfo(skb)->nr_frags + 1; +- +- /* There 4 fragments per descriptor */ +- no_of_desc = (frag_count + 3) >> 2; +- +- producer = adapter->cmd_producer; +- smp_mb(); +- consumer = adapter->last_cmd_consumer; +- if ((no_of_desc+2) > find_diff_among(producer, consumer, num_txd)) { +- netif_stop_queue(netdev); +- smp_mb(); +- return NETDEV_TX_BUSY; +- } +- +- /* Copy the descriptors into the hardware */ +- hwdesc = &hw->cmd_desc_head[producer]; +- memset(hwdesc, 0, sizeof(struct cmd_desc_type0)); +- /* Take skb->data itself */ +- pbuf = &adapter->cmd_buf_arr[producer]; +- +- is_tso = netxen_tso_check(netdev, hwdesc, skb); +- +- pbuf->skb = skb; +- pbuf->frag_count = frag_count; +- buffrag = &pbuf->frag_array[0]; +- temp_dma = pci_map_single(pdev, skb->data, first_seg_len, +- PCI_DMA_TODEVICE); +- if (pci_dma_mapping_error(pdev, temp_dma)) +- goto drop_packet; +- +- buffrag->dma = temp_dma; +- buffrag->length = first_seg_len; +- netxen_set_tx_frags_len(hwdesc, frag_count, skb->len); +- netxen_set_tx_port(hwdesc, adapter->portnum); +- +- hwdesc->buffer1_length = cpu_to_le16(first_seg_len); +- hwdesc->addr_buffer1 = cpu_to_le64(buffrag->dma); +- +- for (i = 1, k = 1; i < frag_count; i++, k++) { +- struct skb_frag_struct *frag; +- int len, temp_len; +- unsigned long offset; +- +- /* move to next desc. if there is a need */ +- if ((i & 0x3) == 0) { +- k = 0; +- producer = get_next_index(producer, num_txd); +- hwdesc = &hw->cmd_desc_head[producer]; +- memset(hwdesc, 0, sizeof(struct cmd_desc_type0)); +- pbuf = &adapter->cmd_buf_arr[producer]; +- pbuf->skb = NULL; +- } +- frag = &skb_shinfo(skb)->frags[i - 1]; +- len = frag->size; +- offset = frag->page_offset; +- +- temp_len = len; +- temp_dma = pci_map_page(pdev, frag->page, offset, +- len, PCI_DMA_TODEVICE); +- if (pci_dma_mapping_error(pdev, temp_dma)) { +- netxen_clean_tx_dma_mapping(pdev, pbuf, i); +- goto drop_packet; +- } +- +- buffrag++; +- buffrag->dma = temp_dma; +- buffrag->length = temp_len; +- +- switch (k) { +- case 0: +- hwdesc->buffer1_length = cpu_to_le16(temp_len); +- hwdesc->addr_buffer1 = cpu_to_le64(temp_dma); +- break; +- case 1: +- hwdesc->buffer2_length = cpu_to_le16(temp_len); +- hwdesc->addr_buffer2 = cpu_to_le64(temp_dma); +- break; +- case 2: +- hwdesc->buffer3_length = cpu_to_le16(temp_len); +- hwdesc->addr_buffer3 = cpu_to_le64(temp_dma); +- break; +- case 3: +- hwdesc->buffer4_length = cpu_to_le16(temp_len); +- hwdesc->addr_buffer4 = cpu_to_le64(temp_dma); +- break; +- } +- frag++; +- } +- producer = get_next_index(producer, num_txd); ++ if (!tso) ++ return; + + /* For LSO, we need to copy the MAC/IP/TCP headers into + * the descriptor ring + */ +- if (is_tso) { +- int hdr_len, first_hdr_len, more_hdr; +- hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); +- if (hdr_len > (sizeof(struct cmd_desc_type0) - 2)) { +- first_hdr_len = sizeof(struct cmd_desc_type0) - 2; +- more_hdr = 1; +- } else { +- first_hdr_len = hdr_len; +- more_hdr = 0; ++ producer = tx_ring->producer; ++ copied = 0; ++ offset = 2; ++ ++ if (vlan_oob) { ++ /* Create a TSO vlan header template for firmware */ ++ ++ hwdesc = &tx_ring->desc_head[producer]; ++ tx_ring->cmd_buf_arr[producer].skb = NULL; ++ ++ copy_len = min((int)sizeof(struct cmd_desc_type0) - offset, ++ hdr_len + VLAN_HLEN); ++ ++ vh = (struct vlan_ethhdr *)((char *)hwdesc + 2); ++ skb_copy_from_linear_data(skb, vh, 12); ++ vh->h_vlan_proto = htons(ETH_P_8021Q); ++ vh->h_vlan_TCI = htons(vid); ++ skb_copy_from_linear_data_offset(skb, 12, ++ (char *)vh + 16, copy_len - 16); ++ ++ copied = copy_len - VLAN_HLEN; ++ offset = 0; ++ ++ producer = get_next_index(producer, tx_ring->num_desc); ++ } ++ ++ while (copied < hdr_len) { ++ ++ copy_len = min((int)sizeof(struct cmd_desc_type0) - offset, ++ (hdr_len - copied)); ++ ++ hwdesc = &tx_ring->desc_head[producer]; ++ tx_ring->cmd_buf_arr[producer].skb = NULL; ++ ++ skb_copy_from_linear_data_offset(skb, copied, ++ (char *)hwdesc + offset, copy_len); ++ ++ copied += copy_len; ++ offset = 0; ++ ++ producer = get_next_index(producer, tx_ring->num_desc); ++ } ++ ++ tx_ring->producer = producer; ++ barrier(); ++} ++ ++static int ++netxen_map_tx_skb(struct pci_dev *pdev, ++ struct sk_buff *skb, struct netxen_cmd_buffer *pbuf) ++{ ++ struct netxen_skb_frag *nf; ++ struct skb_frag_struct *frag; ++ int i, nr_frags; ++ dma_addr_t map; ++ ++ nr_frags = skb_shinfo(skb)->nr_frags; ++ nf = &pbuf->frag_array[0]; ++ ++ map = pci_map_single(pdev, skb->data, ++ skb_headlen(skb), PCI_DMA_TODEVICE); ++ if (pci_dma_mapping_error(pdev, map)) ++ goto out_err; ++ ++ nf->dma = map; ++ nf->length = skb_headlen(skb); ++ ++ for (i = 0; i < nr_frags; i++) { ++ frag = &skb_shinfo(skb)->frags[i]; ++ nf = &pbuf->frag_array[i+1]; ++ ++ map = pci_map_page(pdev, frag->page, frag->page_offset, ++ frag->size, PCI_DMA_TODEVICE); ++ if (pci_dma_mapping_error(pdev, map)) ++ goto unwind; ++ ++ nf->dma = map; ++ nf->length = frag->size; ++ } ++ ++ return 0; ++ ++unwind: ++ while (--i >= 0) { ++ nf = &pbuf->frag_array[i+1]; ++ pci_unmap_page(pdev, nf->dma, nf->length, PCI_DMA_TODEVICE); ++ } ++ ++ nf = &pbuf->frag_array[0]; ++ pci_unmap_single(pdev, nf->dma, skb_headlen(skb), PCI_DMA_TODEVICE); ++ ++out_err: ++ return -ENOMEM; ++} ++ ++static inline void ++netxen_clear_cmddesc(u64 *desc) ++{ ++ desc[0] = 0ULL; ++ desc[2] = 0ULL; ++} ++ ++static int ++netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev) ++{ ++ struct netxen_adapter *adapter = netdev_priv(netdev); ++ struct nx_host_tx_ring *tx_ring = adapter->tx_ring; ++ struct netxen_cmd_buffer *pbuf; ++ struct netxen_skb_frag *buffrag; ++ struct cmd_desc_type0 *hwdesc, *first_desc; ++ struct pci_dev *pdev; ++ int i, k; ++ ++ u32 producer; ++ int frag_count, no_of_desc; ++ u32 num_txd = tx_ring->num_desc; ++ ++ frag_count = skb_shinfo(skb)->nr_frags + 1; ++ ++ /* 4 fragments per cmd des */ ++ no_of_desc = (frag_count + 3) >> 2; ++ ++ if (unlikely(no_of_desc + 2) > netxen_tx_avail(tx_ring)) { ++ netif_stop_queue(netdev); ++ return NETDEV_TX_BUSY; ++ } ++ ++ producer = tx_ring->producer; ++ pbuf = &tx_ring->cmd_buf_arr[producer]; ++ ++ pdev = adapter->pdev; ++ ++ if (netxen_map_tx_skb(pdev, skb, pbuf)) ++ goto drop_packet; ++ ++ pbuf->skb = skb; ++ pbuf->frag_count = frag_count; ++ ++ first_desc = hwdesc = &tx_ring->desc_head[producer]; ++ netxen_clear_cmddesc((u64 *)hwdesc); ++ ++ netxen_set_tx_frags_len(first_desc, frag_count, skb->len); ++ netxen_set_tx_port(first_desc, adapter->portnum); ++ ++ for (i = 0; i < frag_count; i++) { ++ ++ k = i % 4; ++ ++ if ((k == 0) && (i > 0)) { ++ /* move to next desc.*/ ++ producer = get_next_index(producer, num_txd); ++ hwdesc = &tx_ring->desc_head[producer]; ++ netxen_clear_cmddesc((u64 *)hwdesc); ++ tx_ring->cmd_buf_arr[producer].skb = NULL; + } +- /* copy the MAC/IP/TCP headers to the cmd descriptor list */ +- hwdesc = &hw->cmd_desc_head[producer]; +- pbuf = &adapter->cmd_buf_arr[producer]; +- pbuf->skb = NULL; + +- /* copy the first 64 bytes */ +- memcpy(((void *)hwdesc) + 2, +- (void *)(skb->data), first_hdr_len); +- producer = get_next_index(producer, num_txd); ++ buffrag = &pbuf->frag_array[i]; + +- if (more_hdr) { +- hwdesc = &hw->cmd_desc_head[producer]; +- pbuf = &adapter->cmd_buf_arr[producer]; +- pbuf->skb = NULL; +- /* copy the next 64 bytes - should be enough except +- * for pathological case +- */ +- skb_copy_from_linear_data_offset(skb, first_hdr_len, +- hwdesc, +- (hdr_len - +- first_hdr_len)); +- producer = get_next_index(producer, num_txd); ++ hwdesc->buffer_length[k] = cpu_to_le16(buffrag->length); ++ switch (k) { ++ case 0: ++ hwdesc->addr_buffer1 = cpu_to_le64(buffrag->dma); ++ break; ++ case 1: ++ hwdesc->addr_buffer2 = cpu_to_le64(buffrag->dma); ++ break; ++ case 2: ++ hwdesc->addr_buffer3 = cpu_to_le64(buffrag->dma); ++ break; ++ case 3: ++ hwdesc->addr_buffer4 = cpu_to_le64(buffrag->dma); ++ break; + } + } + +- adapter->cmd_producer = producer; ++ tx_ring->producer = get_next_index(producer, num_txd); ++ ++ netxen_tso_check(netdev, tx_ring, first_desc, skb); ++ ++ netxen_nic_update_cmd_producer(adapter, tx_ring); ++ + adapter->stats.txbytes += skb->len; +- +- netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer); +- + adapter->stats.xmitcalled++; + netdev->trans_start = jiffies; + +@@ -1385,7 +1795,7 @@ + uint32_t temp, temp_state, temp_val; + int rv = 0; + +- temp = adapter->pci_read_normalize(adapter, CRB_TEMP_STATE); ++ temp = NXRD32(adapter, CRB_TEMP_STATE); + + temp_state = nx_get_temp_state(temp); + temp_val = nx_get_temp_val(temp); +@@ -1394,10 +1804,7 @@ + printk(KERN_ALERT + "%s: Device temperature %d degrees C exceeds" + " maximum allowed. Hardware has been shut down.\n", +- netxen_nic_driver_name, temp_val); +- +- netif_carrier_off(netdev); +- netif_stop_queue(netdev); ++ netdev->name, temp_val); + rv = 1; + } else if (temp_state == NX_TEMP_WARN) { + if (adapter->temp == NX_TEMP_NORMAL) { +@@ -1405,13 +1812,13 @@ + "%s: Device temperature %d degrees C " + "exceeds operating range." + " Immediate action needed.\n", +- netxen_nic_driver_name, temp_val); ++ netdev->name, temp_val); + } + } else { + if (adapter->temp == NX_TEMP_WARN) { + printk(KERN_INFO + "%s: Device temperature is now %d degrees C" +- " in normal range.\n", netxen_nic_driver_name, ++ " in normal range.\n", netdev->name, + temp_val); + } + } +@@ -1419,26 +1826,9 @@ + return rv; + } + +-static void netxen_nic_handle_phy_intr(struct netxen_adapter *adapter) ++void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup) + { + struct net_device *netdev = adapter->netdev; +- u32 val, port, linkup; +- +- port = adapter->physical_port; +- +- if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { +- val = adapter->pci_read_normalize(adapter, CRB_XG_STATE_P3); +- val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val); +- linkup = (val == XG_LINK_UP_P3); +- } else { +- val = adapter->pci_read_normalize(adapter, CRB_XG_STATE); +- if (adapter->ahw.board_type == NETXEN_NIC_GBE) +- linkup = (val >> port) & 1; +- else { +- val = (val >> port*8) & 0xff; +- linkup = (val == XG_LINK_UP); +- } +- } + + if (adapter->ahw.linkup && !linkup) { + printk(KERN_INFO "%s: %s NIC Link is down\n", +@@ -1448,8 +1838,7 @@ + netif_carrier_off(netdev); + netif_stop_queue(netdev); + } +- +- netxen_nic_set_link_parameters(adapter); ++ adapter->link_changed = !adapter->has_link_events; + } else if (!adapter->ahw.linkup && linkup) { + printk(KERN_INFO "%s: %s NIC Link is up\n", + netxen_nic_driver_name, netdev->name); +@@ -1458,37 +1847,42 @@ + netif_carrier_on(netdev); + netif_wake_queue(netdev); + } +- +- netxen_nic_set_link_parameters(adapter); ++ adapter->link_changed = !adapter->has_link_events; + } + } + +-static void netxen_watchdog(unsigned long v) ++static void netxen_nic_handle_phy_intr(struct netxen_adapter *adapter) + { +- struct netxen_adapter *adapter = (struct netxen_adapter *)v; ++ u32 val, port, linkup; + +- SCHEDULE_WORK(&adapter->watchdog_task); +-} ++ port = adapter->physical_port; + +-void netxen_watchdog_task(struct work_struct *work) +-{ +- struct netxen_adapter *adapter = +- container_of(work, struct netxen_adapter, watchdog_task); ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { ++ val = NXRD32(adapter, CRB_XG_STATE_P3); ++ val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val); ++ linkup = (val == XG_LINK_UP_P3); ++ } else { ++ val = NXRD32(adapter, CRB_XG_STATE); ++ if (adapter->ahw.port_type == NETXEN_NIC_GBE) ++ linkup = (val >> port) & 1; ++ else { ++ val = (val >> port*8) & 0xff; ++ linkup = (val == XG_LINK_UP); ++ } ++ } + +- if ((adapter->portnum == 0) && netxen_nic_check_temp(adapter)) +- return; +- +- netxen_nic_handle_phy_intr(adapter); +- +- if (netif_running(adapter->netdev)) +- mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ); ++ netxen_advert_link_change(adapter, linkup); + } + + static void netxen_tx_timeout(struct net_device *netdev) + { +- struct netxen_adapter *adapter = (struct netxen_adapter *) +- netdev_priv(netdev); +- SCHEDULE_WORK(&adapter->tx_timeout_task); ++ struct netxen_adapter *adapter = netdev_priv(netdev); ++ ++ if (test_bit(__NX_RESETTING, &adapter->state)) ++ return; ++ ++ dev_err(&netdev->dev, "transmit timeout, resetting.\n"); ++ schedule_work(&adapter->tx_timeout_task); + } + + static void netxen_tx_timeout_task(struct work_struct *work) +@@ -1496,23 +1890,41 @@ + struct netxen_adapter *adapter = + container_of(work, struct netxen_adapter, tx_timeout_task); + +- printk(KERN_ERR "%s %s: transmit timeout, resetting.\n", +- netxen_nic_driver_name, adapter->netdev->name); ++ if (!netif_running(adapter->netdev)) ++ return; + +- netxen_nic_disable_int(adapter); +- napi_disable(&adapter->napi); ++ if (test_and_set_bit(__NX_RESETTING, &adapter->state)) ++ return; + +- adapter->netdev->trans_start = jiffies; ++ if (++adapter->tx_timeo_cnt >= NX_MAX_TX_TIMEOUTS) ++ goto request_reset; + +- napi_enable(&adapter->napi); +- netxen_nic_enable_int(adapter); +- netif_wake_queue(adapter->netdev); ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { ++ /* try to scrub interrupt */ ++ netxen_napi_disable(adapter); ++ ++ adapter->netdev->trans_start = jiffies; ++ ++ netxen_napi_enable(adapter); ++ ++ netif_wake_queue(adapter->netdev); ++ ++ clear_bit(__NX_RESETTING, &adapter->state); ++ ++ } else { ++ clear_bit(__NX_RESETTING, &adapter->state); ++ if (!netxen_nic_reset_context(adapter)) { ++ adapter->netdev->trans_start = jiffies; ++ return; ++ } ++ ++ /* context reset failed, fall through for fw reset */ ++ } ++ ++request_reset: ++ adapter->need_fw_reset = 1; + } + +-/* +- * netxen_nic_get_stats - Get System Network Statistics +- * @netdev: network interface device structure +- */ + struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev) + { + struct netxen_adapter *adapter = netdev_priv(netdev); +@@ -1520,22 +1932,11 @@ + + memset(stats, 0, sizeof(*stats)); + +- /* total packets received */ +- stats->rx_packets = adapter->stats.no_rcv; +- /* total packets transmitted */ +- stats->tx_packets = adapter->stats.xmitedframes + +- adapter->stats.xmitfinished; +- /* total bytes received */ ++ stats->rx_packets = adapter->stats.rx_pkts + adapter->stats.lro_pkts; ++ stats->tx_packets = adapter->stats.xmitfinished; + stats->rx_bytes = adapter->stats.rxbytes; +- /* total bytes transmitted */ + stats->tx_bytes = adapter->stats.txbytes; +- /* bad packets received */ +- stats->rx_errors = adapter->stats.rcvdbadskb; +- /* packet transmit problems */ +- stats->tx_errors = adapter->stats.nocmddescriptor; +- /* no space in linux buffers */ + stats->rx_dropped = adapter->stats.rxdropped; +- /* no space available in linux */ + stats->tx_dropped = adapter->stats.txdropped; + + return stats; +@@ -1543,93 +1944,85 @@ + + static irqreturn_t netxen_intr(int irq, void *data) + { +- struct netxen_adapter *adapter = data; ++ struct nx_host_sds_ring *sds_ring = data; ++ struct netxen_adapter *adapter = sds_ring->adapter; + u32 status = 0; + +- status = adapter->pci_read_immediate(adapter, ISR_INT_VECTOR); ++ status = readl(adapter->isr_int_vec); + +- if (!(status & adapter->legacy_intr.int_vec_bit)) ++ if (!(status & adapter->int_vec_bit)) + return IRQ_NONE; + +- if (adapter->ahw.revision_id >= NX_P3_B1) { ++ if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { + /* check interrupt state machine, to be sure */ +- status = adapter->pci_read_immediate(adapter, +- ISR_INT_STATE_REG); ++ status = readl(adapter->crb_int_state_reg); + if (!ISR_LEGACY_INT_TRIGGERED(status)) + return IRQ_NONE; + + } else { + unsigned long our_int = 0; + +- our_int = adapter->pci_read_normalize(adapter, CRB_INT_VECTOR); ++ our_int = readl(adapter->crb_int_state_reg); + + /* not our interrupt */ + if (!test_and_clear_bit((7 + adapter->portnum), &our_int)) + return IRQ_NONE; + + /* claim interrupt */ +- adapter->pci_write_normalize(adapter, +- CRB_INT_VECTOR, (our_int & 0xffffffff)); ++ writel((our_int & 0xffffffff), adapter->crb_int_state_reg); ++ ++ /* clear interrupt */ ++ netxen_nic_disable_int(sds_ring); + } + +- /* clear interrupt */ +- if (adapter->fw_major < 4) +- netxen_nic_disable_int(adapter); ++ writel(0xffffffff, adapter->tgt_status_reg); ++ /* read twice to ensure write is flushed */ ++ readl(adapter->isr_int_vec); ++ readl(adapter->isr_int_vec); + +- adapter->pci_write_immediate(adapter, +- adapter->legacy_intr.tgt_status_reg, +- 0xffffffff); +- /* read twice to ensure write is flushed */ +- adapter->pci_read_immediate(adapter, ISR_INT_VECTOR); +- adapter->pci_read_immediate(adapter, ISR_INT_VECTOR); +- +- napi_schedule(&adapter->napi); ++ napi_schedule(&sds_ring->napi); + + return IRQ_HANDLED; + } + + static irqreturn_t netxen_msi_intr(int irq, void *data) + { +- struct netxen_adapter *adapter = data; ++ struct nx_host_sds_ring *sds_ring = data; ++ struct netxen_adapter *adapter = sds_ring->adapter; + + /* clear interrupt */ +- adapter->pci_write_immediate(adapter, +- msi_tgt_status[adapter->ahw.pci_func], 0xffffffff); ++ writel(0xffffffff, adapter->tgt_status_reg); + +- napi_schedule(&adapter->napi); ++ napi_schedule(&sds_ring->napi); ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t netxen_msix_intr(int irq, void *data) ++{ ++ struct nx_host_sds_ring *sds_ring = data; ++ ++ napi_schedule(&sds_ring->napi); + return IRQ_HANDLED; + } + + static int netxen_nic_poll(struct napi_struct *napi, int budget) + { +- struct netxen_adapter *adapter = container_of(napi, struct netxen_adapter, napi); ++ struct nx_host_sds_ring *sds_ring = ++ container_of(napi, struct nx_host_sds_ring, napi); ++ ++ struct netxen_adapter *adapter = sds_ring->adapter; ++ + int tx_complete; +- int ctx; + int work_done; + + tx_complete = netxen_process_cmd_ring(adapter); + +- work_done = 0; +- for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { +- /* +- * Fairness issue. This will give undue weight to the +- * receive context 0. +- */ +- +- /* +- * To avoid starvation, we give each of our receivers, +- * a fraction of the quota. Sometimes, it might happen that we +- * have enough quota to process every packet, but since all the +- * packets are on one context, it gets only half of the quota, +- * and ends up not processing it. +- */ +- work_done += netxen_process_rcv_ring(adapter, ctx, +- budget / MAX_RCV_CTX); +- } ++ work_done = netxen_process_rcv_ring(sds_ring, budget); + + if ((work_done < budget) && tx_complete) { +- netif_rx_complete(adapter->netdev, &adapter->napi); +- netxen_nic_enable_int(adapter); ++ napi_complete(&sds_ring->napi); ++ if (netif_running(adapter->netdev)) ++ netxen_nic_enable_int(sds_ring); + } + + return work_done; +@@ -1645,19 +2038,493 @@ + } + #endif + ++static int ++nx_incr_dev_ref_cnt(struct netxen_adapter *adapter) ++{ ++ int count; ++ if (netxen_api_lock(adapter)) ++ return -EIO; ++ ++ count = NXRD32(adapter, NX_CRB_DEV_REF_COUNT); ++ ++ NXWR32(adapter, NX_CRB_DEV_REF_COUNT, ++count); ++ ++ netxen_api_unlock(adapter); ++ return count; ++} ++ ++static int ++nx_decr_dev_ref_cnt(struct netxen_adapter *adapter) ++{ ++ int count; ++ if (netxen_api_lock(adapter)) ++ return -EIO; ++ ++ count = NXRD32(adapter, NX_CRB_DEV_REF_COUNT); ++ WARN_ON(count == 0); ++ ++ NXWR32(adapter, NX_CRB_DEV_REF_COUNT, --count); ++ ++ if (count == 0) ++ NXWR32(adapter, NX_CRB_DEV_STATE, NX_DEV_COLD); ++ ++ netxen_api_unlock(adapter); ++ return count; ++} ++ ++static void ++nx_dev_request_reset(struct netxen_adapter *adapter) ++{ ++ u32 state; ++ ++ if (netxen_api_lock(adapter)) ++ return; ++ ++ state = NXRD32(adapter, NX_CRB_DEV_STATE); ++ ++ if (state != NX_DEV_INITALIZING) ++ NXWR32(adapter, NX_CRB_DEV_STATE, NX_DEV_NEED_RESET); ++ ++ netxen_api_unlock(adapter); ++} ++ ++static int ++netxen_can_start_firmware(struct netxen_adapter *adapter) ++{ ++ int count; ++ int can_start = 0; ++ ++ if (netxen_api_lock(adapter)) ++ return 0; ++ ++ count = NXRD32(adapter, NX_CRB_DEV_REF_COUNT); ++ ++ if ((count < 0) || (count >= NX_MAX_PCI_FUNC)) ++ count = 0; ++ ++ if (count == 0) { ++ can_start = 1; ++ NXWR32(adapter, NX_CRB_DEV_STATE, NX_DEV_INITALIZING); ++ } ++ ++ NXWR32(adapter, NX_CRB_DEV_REF_COUNT, ++count); ++ ++ netxen_api_unlock(adapter); ++ ++ return can_start; ++} ++ ++static void ++netxen_schedule_work(struct netxen_adapter *adapter, ++ work_func_t func, int delay) ++{ ++ INIT_DELAYED_WORK(&adapter->fw_work, func); ++ schedule_delayed_work(&adapter->fw_work, delay); ++} ++ ++static void ++netxen_cancel_fw_work(struct netxen_adapter *adapter) ++{ ++ while (test_and_set_bit(__NX_RESETTING, &adapter->state)) ++ msleep(10); ++ ++ cancel_delayed_work_sync(&adapter->fw_work); ++} ++ ++static void ++netxen_attach_work(struct work_struct *work) ++{ ++ struct netxen_adapter *adapter = container_of(work, ++ struct netxen_adapter, fw_work.work); ++ struct net_device *netdev = adapter->netdev; ++ int err = 0; ++ ++ if (netif_running(netdev)) { ++ err = netxen_nic_attach(adapter); ++ if (err) ++ goto done; ++ ++ err = netxen_nic_up(adapter, netdev); ++ if (err) { ++ netxen_nic_detach(adapter); ++ goto done; ++ } ++ ++ netxen_config_indev_addr(netdev, NETDEV_UP); ++ } ++ ++ netif_device_attach(netdev); ++ ++done: ++ adapter->fw_fail_cnt = 0; ++ clear_bit(__NX_RESETTING, &adapter->state); ++ netxen_schedule_work(adapter, netxen_fw_poll_work, FW_POLL_DELAY); ++} ++ ++static void ++netxen_fwinit_work(struct work_struct *work) ++{ ++ struct netxen_adapter *adapter = container_of(work, ++ struct netxen_adapter, fw_work.work); ++ int dev_state; ++ ++ dev_state = NXRD32(adapter, NX_CRB_DEV_STATE); ++ ++ switch (dev_state) { ++ case NX_DEV_COLD: ++ case NX_DEV_READY: ++ if (!netxen_start_firmware(adapter)) { ++ netxen_schedule_work(adapter, netxen_attach_work, 0); ++ return; ++ } ++ break; ++ ++ case NX_DEV_INITALIZING: ++ if (++adapter->fw_wait_cnt < FW_POLL_THRESH) { ++ netxen_schedule_work(adapter, ++ netxen_fwinit_work, 2 * FW_POLL_DELAY); ++ return; ++ } ++ break; ++ ++ case NX_DEV_FAILED: ++ default: ++ break; ++ } ++ ++ nx_incr_dev_ref_cnt(adapter); ++ clear_bit(__NX_RESETTING, &adapter->state); ++} ++ ++static void ++netxen_detach_work(struct work_struct *work) ++{ ++ struct netxen_adapter *adapter = container_of(work, ++ struct netxen_adapter, fw_work.work); ++ struct net_device *netdev = adapter->netdev; ++ int ref_cnt, delay; ++ u32 status; ++ ++ netif_device_detach(netdev); ++ ++ if (netif_running(netdev)) ++ netxen_nic_down(adapter, netdev); ++ ++ netxen_nic_detach(adapter); ++ ++ status = NXRD32(adapter, NETXEN_PEG_HALT_STATUS1); ++ ++ ref_cnt = nx_decr_dev_ref_cnt(adapter); ++ ++ if (status & NX_RCODE_FATAL_ERROR) ++ return; ++ ++ if (adapter->temp == NX_TEMP_PANIC) ++ return; ++ ++ delay = (ref_cnt == 0) ? 0 : (2 * FW_POLL_DELAY); ++ ++ adapter->fw_wait_cnt = 0; ++ netxen_schedule_work(adapter, netxen_fwinit_work, delay); ++} ++ ++static int ++netxen_check_health(struct netxen_adapter *adapter) ++{ ++ u32 state, heartbit; ++ struct net_device *netdev = adapter->netdev; ++ ++ if (netxen_nic_check_temp(adapter)) ++ goto detach; ++ ++ if (adapter->need_fw_reset) { ++ nx_dev_request_reset(adapter); ++ goto detach; ++ } ++ ++ state = NXRD32(adapter, NX_CRB_DEV_STATE); ++ if (state == NX_DEV_NEED_RESET) ++ goto detach; ++ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ++ return 0; ++ ++ heartbit = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER); ++ if (heartbit != adapter->heartbit) { ++ adapter->heartbit = heartbit; ++ adapter->fw_fail_cnt = 0; ++ return 0; ++ } ++ ++ if (++adapter->fw_fail_cnt < FW_FAIL_THRESH) ++ return 0; ++ ++ clear_bit(__NX_FW_ATTACHED, &adapter->state); ++ ++ dev_info(&netdev->dev, "firmware hang detected\n"); ++ ++detach: ++ if (!test_and_set_bit(__NX_RESETTING, &adapter->state)) ++ netxen_schedule_work(adapter, netxen_detach_work, 0); ++ return 1; ++} ++ ++static void ++netxen_fw_poll_work(struct work_struct *work) ++{ ++ struct netxen_adapter *adapter = container_of(work, ++ struct netxen_adapter, fw_work.work); ++ ++ if (test_bit(__NX_RESETTING, &adapter->state)) ++ goto reschedule; ++ ++ if (test_bit(__NX_DEV_UP, &adapter->state)) { ++ if (!adapter->has_link_events) { ++ ++ netxen_nic_handle_phy_intr(adapter); ++ ++ if (adapter->link_changed) ++ netxen_nic_set_link_parameters(adapter); ++ } ++ } ++ ++ if (netxen_check_health(adapter)) ++ return; ++ ++reschedule: ++ netxen_schedule_work(adapter, netxen_fw_poll_work, FW_POLL_DELAY); ++} ++ ++static ssize_t ++netxen_store_bridged_mode(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t len) ++{ ++ struct net_device *net = to_net_dev(dev); ++ struct netxen_adapter *adapter = netdev_priv(net); ++ unsigned long new; ++ int ret = -EINVAL; ++ ++ if (!(adapter->capabilities & NX_FW_CAPABILITY_BDG)) ++ goto err_out; ++ ++ if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) ++ goto err_out; ++ ++ if (strict_strtoul(buf, 2, &new)) ++ goto err_out; ++ ++ if (!netxen_config_bridged_mode(adapter, !!new)) ++ ret = len; ++ ++err_out: ++ return ret; ++} ++ ++static ssize_t ++netxen_show_bridged_mode(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct net_device *net = to_net_dev(dev); ++ struct netxen_adapter *adapter; ++ int bridged_mode = 0; ++ ++ adapter = netdev_priv(net); ++ ++ if (adapter->capabilities & NX_FW_CAPABILITY_BDG) ++ bridged_mode = !!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED); ++ ++ return sprintf(buf, "%d\n", bridged_mode); ++} ++ ++static struct device_attribute dev_attr_bridged_mode = { ++ .attr = {.name = "bridged_mode", .mode = (S_IRUGO | S_IWUSR)}, ++ .show = netxen_show_bridged_mode, ++ .store = netxen_store_bridged_mode, ++}; ++ ++static void ++netxen_create_sysfs_entries(struct netxen_adapter *adapter) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct device *dev = &netdev->dev; ++ ++ if (adapter->capabilities & NX_FW_CAPABILITY_BDG) { ++ /* bridged_mode control */ ++ if (device_create_file(dev, &dev_attr_bridged_mode)) { ++ dev_warn(&netdev->dev, ++ "failed to create bridged_mode sysfs entry\n"); ++ } ++ } ++} ++ ++static void ++netxen_remove_sysfs_entries(struct netxen_adapter *adapter) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct device *dev = &netdev->dev; ++ ++ if (adapter->capabilities & NX_FW_CAPABILITY_BDG) ++ device_remove_file(dev, &dev_attr_bridged_mode); ++} ++ ++#ifdef CONFIG_INET ++ ++#define is_netxen_netdev(dev) (dev->open == netxen_nic_open) ++ ++static int ++netxen_destip_supported(struct netxen_adapter *adapter) ++{ ++ if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ++ return 0; ++ ++ if (adapter->ahw.cut_through) ++ return 0; ++ ++ return 1; ++} ++ ++static void ++netxen_config_indev_addr(struct net_device *dev, unsigned long event) ++{ ++ struct in_device *indev; ++ struct netxen_adapter *adapter = netdev_priv(dev); ++ ++ if (!netxen_destip_supported(adapter)) ++ return; ++ ++ indev = in_dev_get(dev); ++ if (!indev) ++ return; ++ ++ for_ifa(indev) { ++ switch (event) { ++ case NETDEV_UP: ++ netxen_config_ipaddr(adapter, ++ ifa->ifa_address, NX_IP_UP); ++ break; ++ case NETDEV_DOWN: ++ netxen_config_ipaddr(adapter, ++ ifa->ifa_address, NX_IP_DOWN); ++ break; ++ default: ++ break; ++ } ++ } endfor_ifa(indev); ++ ++ in_dev_put(indev); ++ return; ++} ++ ++static int netxen_netdev_event(struct notifier_block *this, ++ unsigned long event, void *ptr) ++{ ++ struct netxen_adapter *adapter; ++ struct net_device *dev = (struct net_device *)ptr; ++ ++recheck: ++ if (dev == NULL) ++ goto done; ++ ++ if (dev->priv_flags & IFF_802_1Q_VLAN) { ++ dev = vlan_dev_real_dev(dev); ++ goto recheck; ++ } ++ ++ if (!is_netxen_netdev(dev)) ++ goto done; ++ ++ adapter = netdev_priv(dev); ++ ++ if (!adapter) ++ goto done; ++ ++ if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) ++ goto done; ++ ++ netxen_config_indev_addr(dev, event); ++done: ++ return NOTIFY_DONE; ++} ++ ++static int ++netxen_inetaddr_event(struct notifier_block *this, ++ unsigned long event, void *ptr) ++{ ++ struct netxen_adapter *adapter; ++ struct net_device *dev; ++ ++ struct in_ifaddr *ifa = (struct in_ifaddr *)ptr; ++ ++ dev = ifa->ifa_dev ? ifa->ifa_dev->dev : NULL; ++ ++recheck: ++ if (dev == NULL || !netif_running(dev)) ++ goto done; ++ ++ if (dev->priv_flags & IFF_802_1Q_VLAN) { ++ dev = vlan_dev_real_dev(dev); ++ goto recheck; ++ } ++ ++ if (!is_netxen_netdev(dev)) ++ goto done; ++ ++ adapter = netdev_priv(dev); ++ ++ if (!adapter || !netxen_destip_supported(adapter)) ++ goto done; ++ ++ if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) ++ goto done; ++ ++ switch (event) { ++ case NETDEV_UP: ++ netxen_config_ipaddr(adapter, ifa->ifa_address, NX_IP_UP); ++ break; ++ case NETDEV_DOWN: ++ netxen_config_ipaddr(adapter, ifa->ifa_address, NX_IP_DOWN); ++ break; ++ default: ++ break; ++ } ++ ++done: ++ return NOTIFY_DONE; ++} ++ ++static struct notifier_block netxen_netdev_cb = { ++ .notifier_call = netxen_netdev_event, ++}; ++ ++static struct notifier_block netxen_inetaddr_cb = { ++ .notifier_call = netxen_inetaddr_event, ++}; ++#else ++static void ++netxen_config_indev_addr(struct net_device *dev, unsigned long event) ++{ } ++#endif ++ + static struct pci_driver netxen_driver = { + .name = netxen_nic_driver_name, + .id_table = netxen_pci_tbl, + .probe = netxen_nic_probe, +- .remove = __devexit_p(netxen_nic_remove) ++ .remove = __devexit_p(netxen_nic_remove), ++#ifdef CONFIG_PM ++ .suspend = netxen_nic_suspend, ++ .resume = netxen_nic_resume, ++#endif ++ .shutdown = netxen_nic_shutdown + }; +- +-/* Driver Registration on NetXen card */ + + static int __init netxen_init_module(void) + { +- if ((netxen_workq = create_singlethread_workqueue("netxen")) == NULL) +- return -ENOMEM; ++ printk(KERN_INFO "%s\n", netxen_nic_driver_string); ++ ++#ifdef CONFIG_INET ++ register_netdevice_notifier(&netxen_netdev_cb); ++ register_inetaddr_notifier(&netxen_inetaddr_cb); ++#endif + + return pci_register_driver(&netxen_driver); + } +@@ -1667,7 +2534,11 @@ + static void __exit netxen_exit_module(void) + { + pci_unregister_driver(&netxen_driver); +- destroy_workqueue(netxen_workq); ++ ++#ifdef CONFIG_INET ++ unregister_inetaddr_notifier(&netxen_inetaddr_cb); ++ unregister_netdevice_notifier(&netxen_netdev_cb); ++#endif + } + + module_exit(netxen_exit_module); +diff -r 6335373db0ec drivers/net/netxen/netxen_nic_niu.c +--- a/drivers/net/netxen/netxen_nic_niu.c Thu Oct 01 10:10:06 2009 +0100 ++++ /dev/null Thu Jan 01 00:00:00 1970 +0000 +@@ -1,934 +0,0 @@ +-/* +- * Copyright (C) 2003 - 2006 NetXen, Inc. +- * All rights reserved. +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * as published by the Free Software Foundation; either version 2 +- * of the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, but +- * WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, +- * MA 02111-1307, USA. +- * +- * The full GNU General Public License is included in this distribution +- * in the file called LICENSE. +- * +- * Contact Information: +- * info@netxen.com +- * NetXen, +- * 3965 Freedom Circle, Fourth floor, +- * Santa Clara, CA 95054 +- * +- * +- * Provides access to the Network Interface Unit h/w block. +- * +- */ +- +-#include "netxen_nic.h" +- +-#define NETXEN_GB_MAC_SOFT_RESET 0x80000000 +-#define NETXEN_GB_MAC_RESET_PROT_BLK 0x000F0000 +-#define NETXEN_GB_MAC_ENABLE_TX_RX 0x00000005 +-#define NETXEN_GB_MAC_PAUSED_FRMS 0x00000020 +- +-static long phy_lock_timeout = 100000000; +- +-static int phy_lock(struct netxen_adapter *adapter) +-{ +- int i; +- int done = 0, timeout = 0; +- +- while (!done) { +- done = netxen_nic_reg_read(adapter, +- NETXEN_PCIE_REG(PCIE_SEM3_LOCK)); +- if (done == 1) +- break; +- if (timeout >= phy_lock_timeout) { +- return -1; +- } +- timeout++; +- if (!in_atomic()) +- schedule(); +- else { +- for (i = 0; i < 20; i++) +- cpu_relax(); +- } +- } +- +- netxen_crb_writelit_adapter(adapter, +- NETXEN_PHY_LOCK_ID, PHY_LOCK_DRIVER); +- return 0; +-} +- +-static int phy_unlock(struct netxen_adapter *adapter) +-{ +- adapter->pci_read_immediate(adapter, NETXEN_PCIE_REG(PCIE_SEM3_UNLOCK)); +- +- return 0; +-} +- +-/* +- * netxen_niu_gbe_phy_read - read a register from the GbE PHY via +- * mii management interface. +- * +- * Note: The MII management interface goes through port 0. +- * Individual phys are addressed as follows: +- * @param phy [15:8] phy id +- * @param reg [7:0] register number +- * +- * @returns 0 on success +- * -1 on error +- * +- */ +-int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg, +- __u32 * readval) +-{ +- long timeout = 0; +- long result = 0; +- long restore = 0; +- long phy = adapter->physical_port; +- __u32 address; +- __u32 command; +- __u32 status; +- __u32 mac_cfg0; +- +- if (phy_lock(adapter) != 0) { +- return -1; +- } +- +- /* +- * MII mgmt all goes through port 0 MAC interface, +- * so it cannot be in reset +- */ +- +- if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), +- &mac_cfg0, 4)) +- return -EIO; +- if (netxen_gb_get_soft_reset(mac_cfg0)) { +- __u32 temp; +- temp = 0; +- netxen_gb_tx_reset_pb(temp); +- netxen_gb_rx_reset_pb(temp); +- netxen_gb_tx_reset_mac(temp); +- netxen_gb_rx_reset_mac(temp); +- if (adapter->hw_write_wx(adapter, +- NETXEN_NIU_GB_MAC_CONFIG_0(0), +- &temp, 4)) +- return -EIO; +- restore = 1; +- } +- +- address = 0; +- netxen_gb_mii_mgmt_reg_addr(address, reg); +- netxen_gb_mii_mgmt_phy_addr(address, phy); +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), +- &address, 4)) +- return -EIO; +- command = 0; /* turn off any prior activity */ +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), +- &command, 4)) +- return -EIO; +- /* send read command */ +- netxen_gb_mii_mgmt_set_read_cycle(command); +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), +- &command, 4)) +- return -EIO; +- +- status = 0; +- do { +- if (adapter->hw_read_wx(adapter, +- NETXEN_NIU_GB_MII_MGMT_INDICATE(0), +- &status, 4)) +- return -EIO; +- timeout++; +- } while ((netxen_get_gb_mii_mgmt_busy(status) +- || netxen_get_gb_mii_mgmt_notvalid(status)) +- && (timeout++ < NETXEN_NIU_PHY_WAITMAX)); +- +- if (timeout < NETXEN_NIU_PHY_WAITMAX) { +- if (adapter->hw_read_wx(adapter, +- NETXEN_NIU_GB_MII_MGMT_STATUS(0), +- readval, 4)) +- return -EIO; +- result = 0; +- } else +- result = -1; +- +- if (restore) +- if (adapter->hw_write_wx(adapter, +- NETXEN_NIU_GB_MAC_CONFIG_0(0), +- &mac_cfg0, 4)) +- return -EIO; +- phy_unlock(adapter); +- return result; +-} +- +-/* +- * netxen_niu_gbe_phy_write - write a register to the GbE PHY via +- * mii management interface. +- * +- * Note: The MII management interface goes through port 0. +- * Individual phys are addressed as follows: +- * @param phy [15:8] phy id +- * @param reg [7:0] register number +- * +- * @returns 0 on success +- * -1 on error +- * +- */ +-int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg, +- __u32 val) +-{ +- long timeout = 0; +- long result = 0; +- long restore = 0; +- long phy = adapter->physical_port; +- __u32 address; +- __u32 command; +- __u32 status; +- __u32 mac_cfg0; +- +- /* +- * MII mgmt all goes through port 0 MAC interface, so it +- * cannot be in reset +- */ +- +- if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), +- &mac_cfg0, 4)) +- return -EIO; +- if (netxen_gb_get_soft_reset(mac_cfg0)) { +- __u32 temp; +- temp = 0; +- netxen_gb_tx_reset_pb(temp); +- netxen_gb_rx_reset_pb(temp); +- netxen_gb_tx_reset_mac(temp); +- netxen_gb_rx_reset_mac(temp); +- +- if (adapter->hw_write_wx(adapter, +- NETXEN_NIU_GB_MAC_CONFIG_0(0), +- &temp, 4)) +- return -EIO; +- restore = 1; +- } +- +- command = 0; /* turn off any prior activity */ +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), +- &command, 4)) +- return -EIO; +- +- address = 0; +- netxen_gb_mii_mgmt_reg_addr(address, reg); +- netxen_gb_mii_mgmt_phy_addr(address, phy); +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), +- &address, 4)) +- return -EIO; +- +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0), +- &val, 4)) +- return -EIO; +- +- status = 0; +- do { +- if (adapter->hw_read_wx(adapter, +- NETXEN_NIU_GB_MII_MGMT_INDICATE(0), +- &status, 4)) +- return -EIO; +- timeout++; +- } while ((netxen_get_gb_mii_mgmt_busy(status)) +- && (timeout++ < NETXEN_NIU_PHY_WAITMAX)); +- +- if (timeout < NETXEN_NIU_PHY_WAITMAX) +- result = 0; +- else +- result = -EIO; +- +- /* restore the state of port 0 MAC in case we tampered with it */ +- if (restore) +- if (adapter->hw_write_wx(adapter, +- NETXEN_NIU_GB_MAC_CONFIG_0(0), +- &mac_cfg0, 4)) +- return -EIO; +- +- return result; +-} +- +-int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter) +-{ +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x3f); +- return 0; +-} +- +-int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter) +-{ +- int result = 0; +- __u32 enable = 0; +- netxen_set_phy_int_link_status_changed(enable); +- netxen_set_phy_int_autoneg_completed(enable); +- netxen_set_phy_int_speed_changed(enable); +- +- if (0 != +- netxen_niu_gbe_phy_write(adapter, +- NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE, +- enable)) +- result = -EIO; +- +- return result; +-} +- +-int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter) +-{ +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x7f); +- return 0; +-} +- +-int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter) +-{ +- int result = 0; +- if (0 != +- netxen_niu_gbe_phy_write(adapter, +- NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE, 0)) +- result = -EIO; +- +- return result; +-} +- +-#if 0 +-int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter) +-{ +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_ACTIVE_INT, -1); +- return 0; +-} +-#endif /* 0 */ +- +-static int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter) +-{ +- int result = 0; +- if (0 != +- netxen_niu_gbe_phy_write(adapter, +- NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS, +- -EIO)) +- result = -EIO; +- +- return result; +-} +- +-/* +- * netxen_niu_gbe_set_mii_mode- Set 10/100 Mbit Mode for GbE MAC +- * +- */ +-static void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter, +- int port, long enable) +-{ +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2); +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), +- 0x80000000); +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), +- 0x0000f0025); +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), +- 0xf1ff); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_NIU_GB0_MII_MODE + (port << 3), 1); +- netxen_crb_writelit_adapter(adapter, +- (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7); +- +- if (enable) { +- /* +- * Do NOT enable flow control until a suitable solution for +- * shutting down pause frames is found. +- */ +- netxen_crb_writelit_adapter(adapter, +- NETXEN_NIU_GB_MAC_CONFIG_0(port), +- 0x5); +- } +- +- if (netxen_niu_gbe_enable_phy_interrupts(adapter)) +- printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n"); +- if (netxen_niu_gbe_clear_phy_interrupts(adapter)) +- printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n"); +-} +- +-/* +- * netxen_niu_gbe_set_gmii_mode- Set GbE Mode for GbE MAC +- */ +-static void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter, +- int port, long enable) +-{ +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2); +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), +- 0x80000000); +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), +- 0x0000f0025); +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), +- 0xf2ff); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_NIU_GB0_MII_MODE + (port << 3), 0); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1); +- netxen_crb_writelit_adapter(adapter, +- (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7); +- +- if (enable) { +- /* +- * Do NOT enable flow control until a suitable solution for +- * shutting down pause frames is found. +- */ +- netxen_crb_writelit_adapter(adapter, +- NETXEN_NIU_GB_MAC_CONFIG_0(port), +- 0x5); +- } +- +- if (netxen_niu_gbe_enable_phy_interrupts(adapter)) +- printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n"); +- if (netxen_niu_gbe_clear_phy_interrupts(adapter)) +- printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n"); +-} +- +-int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port) +-{ +- int result = 0; +- __u32 status; +- +- if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) +- return 0; +- +- if (adapter->disable_phy_interrupts) +- adapter->disable_phy_interrupts(adapter); +- mdelay(2); +- +- if (0 == netxen_niu_gbe_phy_read(adapter, +- NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, &status)) { +- if (netxen_get_phy_link(status)) { +- if (netxen_get_phy_speed(status) == 2) { +- netxen_niu_gbe_set_gmii_mode(adapter, port, 1); +- } else if ((netxen_get_phy_speed(status) == 1) +- || (netxen_get_phy_speed(status) == 0)) { +- netxen_niu_gbe_set_mii_mode(adapter, port, 1); +- } else { +- result = -1; +- } +- +- } else { +- /* +- * We don't have link. Cable must be unconnected. +- * Enable phy interrupts so we take action when +- * plugged in. +- */ +- +- netxen_crb_writelit_adapter(adapter, +- NETXEN_NIU_GB_MAC_CONFIG_0 +- (port), +- NETXEN_GB_MAC_SOFT_RESET); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_NIU_GB_MAC_CONFIG_0 +- (port), +- NETXEN_GB_MAC_RESET_PROT_BLK +- | NETXEN_GB_MAC_ENABLE_TX_RX +- | +- NETXEN_GB_MAC_PAUSED_FRMS); +- if (netxen_niu_gbe_clear_phy_interrupts(adapter)) +- printk(KERN_ERR PFX +- "ERROR clearing PHY interrupts\n"); +- if (netxen_niu_gbe_enable_phy_interrupts(adapter)) +- printk(KERN_ERR PFX +- "ERROR enabling PHY interrupts\n"); +- if (netxen_niu_gbe_clear_phy_interrupts(adapter)) +- printk(KERN_ERR PFX +- "ERROR clearing PHY interrupts\n"); +- result = -1; +- } +- } else { +- result = -EIO; +- } +- return result; +-} +- +-int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port) +-{ +- if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { +- netxen_crb_writelit_adapter(adapter, +- NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447); +- netxen_crb_writelit_adapter(adapter, +- NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5); +- } +- +- return 0; +-} +- +-#if 0 +-/* +- * netxen_niu_gbe_handle_phy_interrupt - Handles GbE PHY interrupts +- * @param enable 0 means don't enable the port +- * 1 means enable (or re-enable) the port +- */ +-int netxen_niu_gbe_handle_phy_interrupt(struct netxen_adapter *adapter, +- int port, long enable) +-{ +- int result = 0; +- __u32 int_src; +- +- printk(KERN_INFO PFX "NETXEN: Handling PHY interrupt on port %d" +- " (device enable = %d)\n", (int)port, (int)enable); +- +- /* +- * The read of the PHY INT status will clear the pending +- * interrupt status +- */ +- if (netxen_niu_gbe_phy_read(adapter, +- NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS, +- &int_src) != 0) +- result = -EINVAL; +- else { +- printk(KERN_INFO PFX "PHY Interrupt source = 0x%x \n", int_src); +- if (netxen_get_phy_int_jabber(int_src)) +- printk(KERN_INFO PFX "jabber Interrupt "); +- if (netxen_get_phy_int_polarity_changed(int_src)) +- printk(KERN_INFO PFX "polarity changed "); +- if (netxen_get_phy_int_energy_detect(int_src)) +- printk(KERN_INFO PFX "energy detect \n"); +- if (netxen_get_phy_int_downshift(int_src)) +- printk(KERN_INFO PFX "downshift \n"); +- if (netxen_get_phy_int_mdi_xover_changed(int_src)) +- printk(KERN_INFO PFX "mdi_xover_changed "); +- if (netxen_get_phy_int_fifo_over_underflow(int_src)) +- printk(KERN_INFO PFX "fifo_over_underflow "); +- if (netxen_get_phy_int_false_carrier(int_src)) +- printk(KERN_INFO PFX "false_carrier "); +- if (netxen_get_phy_int_symbol_error(int_src)) +- printk(KERN_INFO PFX "symbol_error "); +- if (netxen_get_phy_int_autoneg_completed(int_src)) +- printk(KERN_INFO PFX "autoneg_completed "); +- if (netxen_get_phy_int_page_received(int_src)) +- printk(KERN_INFO PFX "page_received "); +- if (netxen_get_phy_int_duplex_changed(int_src)) +- printk(KERN_INFO PFX "duplex_changed "); +- if (netxen_get_phy_int_autoneg_error(int_src)) +- printk(KERN_INFO PFX "autoneg_error "); +- if ((netxen_get_phy_int_speed_changed(int_src)) +- || (netxen_get_phy_int_link_status_changed(int_src))) { +- __u32 status; +- +- printk(KERN_INFO PFX +- "speed_changed or link status changed"); +- if (netxen_niu_gbe_phy_read +- (adapter, +- NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, +- &status) == 0) { +- if (netxen_get_phy_speed(status) == 2) { +- printk +- (KERN_INFO PFX "Link speed changed" +- " to 1000 Mbps\n"); +- netxen_niu_gbe_set_gmii_mode(adapter, +- port, +- enable); +- } else if (netxen_get_phy_speed(status) == 1) { +- printk +- (KERN_INFO PFX "Link speed changed" +- " to 100 Mbps\n"); +- netxen_niu_gbe_set_mii_mode(adapter, +- port, +- enable); +- } else if (netxen_get_phy_speed(status) == 0) { +- printk +- (KERN_INFO PFX "Link speed changed" +- " to 10 Mbps\n"); +- netxen_niu_gbe_set_mii_mode(adapter, +- port, +- enable); +- } else { +- printk(KERN_ERR PFX "ERROR reading " +- "PHY status. Invalid speed.\n"); +- result = -1; +- } +- } else { +- printk(KERN_ERR PFX +- "ERROR reading PHY status.\n"); +- result = -1; +- } +- +- } +- printk(KERN_INFO "\n"); +- } +- return result; +-} +-#endif /* 0 */ +- +-/* +- * Return the current station MAC address. +- * Note that the passed-in value must already be in network byte order. +- */ +-static int netxen_niu_macaddr_get(struct netxen_adapter *adapter, +- netxen_ethernet_macaddr_t * addr) +-{ +- u32 stationhigh; +- u32 stationlow; +- int phy = adapter->physical_port; +- u8 val[8]; +- +- if (addr == NULL) +- return -EINVAL; +- if ((phy < 0) || (phy > 3)) +- return -EINVAL; +- +- if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy), +- &stationhigh, 4)) +- return -EIO; +- if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy), +- &stationlow, 4)) +- return -EIO; +- ((__le32 *)val)[1] = cpu_to_le32(stationhigh); +- ((__le32 *)val)[0] = cpu_to_le32(stationlow); +- +- memcpy(addr, val + 2, 6); +- +- return 0; +-} +- +-/* +- * Set the station MAC address. +- * Note that the passed-in value must already be in network byte order. +- */ +-int netxen_niu_macaddr_set(struct netxen_adapter *adapter, +- netxen_ethernet_macaddr_t addr) +-{ +- u8 temp[4]; +- u32 val; +- int phy = adapter->physical_port; +- unsigned char mac_addr[6]; +- int i; +- DECLARE_MAC_BUF(mac); +- +- if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) +- return 0; +- +- for (i = 0; i < 10; i++) { +- temp[0] = temp[1] = 0; +- memcpy(temp + 2, addr, 2); +- val = le32_to_cpu(*(__le32 *)temp); +- if (adapter->hw_write_wx(adapter, +- NETXEN_NIU_GB_STATION_ADDR_1(phy), &val, 4)) +- return -EIO; +- +- memcpy(temp, ((u8 *) addr) + 2, sizeof(__le32)); +- val = le32_to_cpu(*(__le32 *)temp); +- if (adapter->hw_write_wx(adapter, +- NETXEN_NIU_GB_STATION_ADDR_0(phy), &val, 4)) +- return -2; +- +- netxen_niu_macaddr_get(adapter, +- (netxen_ethernet_macaddr_t *) mac_addr); +- if (memcmp(mac_addr, addr, 6) == 0) +- break; +- } +- +- if (i == 10) { +- printk(KERN_ERR "%s: cannot set Mac addr for %s\n", +- netxen_nic_driver_name, adapter->netdev->name); +- printk(KERN_ERR "MAC address set: %s.\n", +- print_mac(mac, addr)); +- printk(KERN_ERR "MAC address get: %s.\n", +- print_mac(mac, mac_addr)); +- } +- return 0; +-} +- +-#if 0 +-/* Enable a GbE interface */ +-int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter, +- int port, netxen_niu_gbe_ifmode_t mode) +-{ +- __u32 mac_cfg0; +- __u32 mac_cfg1; +- __u32 mii_cfg; +- +- if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS)) +- return -EINVAL; +- +- mac_cfg0 = 0; +- netxen_gb_soft_reset(mac_cfg0); +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), +- &mac_cfg0, 4)) +- return -EIO; +- mac_cfg0 = 0; +- netxen_gb_enable_tx(mac_cfg0); +- netxen_gb_enable_rx(mac_cfg0); +- netxen_gb_unset_rx_flowctl(mac_cfg0); +- netxen_gb_tx_reset_pb(mac_cfg0); +- netxen_gb_rx_reset_pb(mac_cfg0); +- netxen_gb_tx_reset_mac(mac_cfg0); +- netxen_gb_rx_reset_mac(mac_cfg0); +- +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), +- &mac_cfg0, 4)) +- return -EIO; +- mac_cfg1 = 0; +- netxen_gb_set_preamblelen(mac_cfg1, 0xf); +- netxen_gb_set_duplex(mac_cfg1); +- netxen_gb_set_crc_enable(mac_cfg1); +- netxen_gb_set_padshort(mac_cfg1); +- netxen_gb_set_checklength(mac_cfg1); +- netxen_gb_set_hugeframes(mac_cfg1); +- +- if (mode == NETXEN_NIU_10_100_MB) { +- netxen_gb_set_intfmode(mac_cfg1, 1); +- if (adapter->hw_write_wx(adapter, +- NETXEN_NIU_GB_MAC_CONFIG_1(port), +- &mac_cfg1, 4)) +- return -EIO; +- +- /* set mii mode */ +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE + +- (port << 3), 0); +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE + +- (port << 3), 1); +- +- } else if (mode == NETXEN_NIU_1000_MB) { +- netxen_gb_set_intfmode(mac_cfg1, 2); +- if (adapter->hw_write_wx(adapter, +- NETXEN_NIU_GB_MAC_CONFIG_1(port), +- &mac_cfg1, 4)) +- return -EIO; +- /* set gmii mode */ +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE + +- (port << 3), 0); +- netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE + +- (port << 3), 1); +- } +- mii_cfg = 0; +- netxen_gb_set_mii_mgmt_clockselect(mii_cfg, 7); +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port), +- &mii_cfg, 4)) +- return -EIO; +- mac_cfg0 = 0; +- netxen_gb_enable_tx(mac_cfg0); +- netxen_gb_enable_rx(mac_cfg0); +- netxen_gb_unset_rx_flowctl(mac_cfg0); +- netxen_gb_unset_tx_flowctl(mac_cfg0); +- +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), +- &mac_cfg0, 4)) +- return -EIO; +- return 0; +-} +-#endif /* 0 */ +- +-/* Disable a GbE interface */ +-int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter) +-{ +- __u32 mac_cfg0; +- u32 port = adapter->physical_port; +- +- if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) +- return 0; +- +- if (port > NETXEN_NIU_MAX_GBE_PORTS) +- return -EINVAL; +- mac_cfg0 = 0; +- netxen_gb_soft_reset(mac_cfg0); +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), +- &mac_cfg0, 4)) +- return -EIO; +- return 0; +-} +- +-/* Disable an XG interface */ +-int netxen_niu_disable_xg_port(struct netxen_adapter *adapter) +-{ +- __u32 mac_cfg; +- u32 port = adapter->physical_port; +- +- if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) +- return 0; +- +- if (port > NETXEN_NIU_MAX_XG_PORTS) +- return -EINVAL; +- +- mac_cfg = 0; +- if (adapter->hw_write_wx(adapter, +- NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), &mac_cfg, 4)) +- return -EIO; +- return 0; +-} +- +-/* Set promiscuous mode for a GbE interface */ +-int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter, +- u32 mode) +-{ +- __u32 reg; +- u32 port = adapter->physical_port; +- +- if (port > NETXEN_NIU_MAX_GBE_PORTS) +- return -EINVAL; +- +- /* save previous contents */ +- if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR, +- ®, 4)) +- return -EIO; +- if (mode == NETXEN_NIU_PROMISC_MODE) { +- switch (port) { +- case 0: +- netxen_clear_gb_drop_gb0(reg); +- break; +- case 1: +- netxen_clear_gb_drop_gb1(reg); +- break; +- case 2: +- netxen_clear_gb_drop_gb2(reg); +- break; +- case 3: +- netxen_clear_gb_drop_gb3(reg); +- break; +- default: +- return -EIO; +- } +- } else { +- switch (port) { +- case 0: +- netxen_set_gb_drop_gb0(reg); +- break; +- case 1: +- netxen_set_gb_drop_gb1(reg); +- break; +- case 2: +- netxen_set_gb_drop_gb2(reg); +- break; +- case 3: +- netxen_set_gb_drop_gb3(reg); +- break; +- default: +- return -EIO; +- } +- } +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR, +- ®, 4)) +- return -EIO; +- return 0; +-} +- +-/* +- * Set the MAC address for an XG port +- * Note that the passed-in value must already be in network byte order. +- */ +-int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter, +- netxen_ethernet_macaddr_t addr) +-{ +- int phy = adapter->physical_port; +- u8 temp[4]; +- u32 val; +- +- if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) +- return 0; +- +- if ((phy < 0) || (phy > NETXEN_NIU_MAX_XG_PORTS)) +- return -EIO; +- +- temp[0] = temp[1] = 0; +- switch (phy) { +- case 0: +- memcpy(temp + 2, addr, 2); +- val = le32_to_cpu(*(__le32 *)temp); +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1, +- &val, 4)) +- return -EIO; +- +- memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32)); +- val = le32_to_cpu(*(__le32 *)temp); +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI, +- &val, 4)) +- return -EIO; +- break; +- +- case 1: +- memcpy(temp + 2, addr, 2); +- val = le32_to_cpu(*(__le32 *)temp); +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_1, +- &val, 4)) +- return -EIO; +- +- memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32)); +- val = le32_to_cpu(*(__le32 *)temp); +- if (adapter->hw_write_wx(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_HI, +- &val, 4)) +- return -EIO; +- break; +- +- default: +- printk(KERN_ERR "Unknown port %d\n", phy); +- break; +- } +- +- return 0; +-} +- +-#if 0 +-/* +- * Return the current station MAC address. +- * Note that the passed-in value must already be in network byte order. +- */ +-int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter, +- netxen_ethernet_macaddr_t * addr) +-{ +- int phy = adapter->physical_port; +- u32 stationhigh; +- u32 stationlow; +- u8 val[8]; +- +- if (addr == NULL) +- return -EINVAL; +- if (phy != 0) +- return -EINVAL; +- +- if (adapter->hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI, +- &stationhigh, 4)) +- return -EIO; +- if (adapter->hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1, +- &stationlow, 4)) +- return -EIO; +- ((__le32 *)val)[1] = cpu_to_le32(stationhigh); +- ((__le32 *)val)[0] = cpu_to_le32(stationlow); +- +- memcpy(addr, val + 2, 6); +- +- return 0; +-} +-#endif /* 0 */ +- +-int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter, +- u32 mode) +-{ +- __u32 reg; +- u32 port = adapter->physical_port; +- +- if (port > NETXEN_NIU_MAX_XG_PORTS) +- return -EINVAL; +- +- if (adapter->hw_read_wx(adapter, +- NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), ®, 4)) +- return -EIO; +- if (mode == NETXEN_NIU_PROMISC_MODE) +- reg = (reg | 0x2000UL); +- else +- reg = (reg & ~0x2000UL); +- +- if (mode == NETXEN_NIU_ALLMULTI_MODE) +- reg = (reg | 0x1000UL); +- else +- reg = (reg & ~0x1000UL); +- +- netxen_crb_writelit_adapter(adapter, +- NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg); +- +- return 0; +-} diff --git a/master/open-iscsi-gfpkernel.patch b/master/open-iscsi-gfpkernel.patch index b7b4610..bf4c237 100644 --- a/master/open-iscsi-gfpkernel.patch +++ b/master/open-iscsi-gfpkernel.patch @@ -1,12 +1,12 @@ -diff -r cf52cd97d524 drivers/scsi/scsi_transport_iscsi.c ---- a/drivers/scsi/scsi_transport_iscsi.c Fri Jun 05 15:56:34 2009 +0100 -+++ b/drivers/scsi/scsi_transport_iscsi.c Mon Jun 15 11:28:15 2009 +0100 -@@ -1044,7 +1044,7 @@ - if (!priv) - return; +diff -r 346396209a00 drivers/scsi/scsi_transport_iscsi.c +--- a/drivers/scsi/scsi_transport_iscsi.c Thu Jul 30 13:49:24 2009 +0100 ++++ b/drivers/scsi/scsi_transport_iscsi.c Fri Jul 31 11:07:27 2009 +0100 +@@ -1076,7 +1076,7 @@ + int flags = multi ? NLM_F_MULTI : 0; + int t = done ? NLMSG_DONE : type; - skb = alloc_skb(len, GFP_ATOMIC); + skb = alloc_skb(len, GFP_KERNEL); /* not called from interrupt ctxt */ if (!skb) { - iscsi_cls_conn_printk(KERN_ERR, conn, "gracefully ignored " - "conn error (%d)\n", error); + printk(KERN_ERR "Could not allocate skb to send reply.\n"); + return -ENOMEM; diff --git a/master/pciback-flr-82599 b/master/pciback-flr-82599 new file mode 100644 index 0000000..4e8e585 --- /dev/null +++ b/master/pciback-flr-82599 @@ -0,0 +1,29 @@ +diff -r d0bf5b4297d0 drivers/xen/pciback/pciback_ops.c +--- a/drivers/xen/pciback/pciback_ops.c Thu Aug 20 11:46:16 2009 +0100 ++++ b/drivers/xen/pciback/pciback_ops.c Mon Aug 24 15:22:09 2009 +0100 +@@ -472,7 +472,13 @@ + pciback_do_pci_flr(dev, dev_data->af_flr_offset, 1); + break; + } +- ++ /* Quirk for the VF of Intel 82599 10GbE Controller */ ++ if (dev->vendor == PCIBACK_VENDOR_INTEL && ++ dev->device == PCI_DEVICE_ID_INTEL_82599) { ++ pciback_do_pcie_flr(dev, dev_data->exp_flr_offset); ++ break; ++ } ++ + /* Next for integrated devices on the host bus 0, try some other methods */ + if (dev->bus->number == 0) { + err = pciback_do_vendor_specific_reset(dev); +diff -r d0bf5b4297d0 include/linux/pci_ids.h +--- a/include/linux/pci_ids.h Thu Aug 20 11:46:16 2009 +0100 ++++ b/include/linux/pci_ids.h Mon Aug 24 15:22:09 2009 +0100 +@@ -2506,6 +2506,7 @@ + #define PCI_DEVICE_ID_INTEL_MCHP45 0x2e20 + #define PCI_DEVICE_ID_INTEL_GMCHG41 0x2e30 + #define PCI_DEVICE_ID_INTEL_GMCHGM45 0x2a40 ++#define PCI_DEVICE_ID_INTEL_82599 0x10ed + + #define PCI_DEVICE_ID_INTEL_GMCHG41 0x2e30 + diff --git a/master/s2io-2-0-27-1.patch b/master/s2io-2-0-27-1.patch new file mode 100644 index 0000000..dd7da9e --- /dev/null +++ b/master/s2io-2-0-27-1.patch @@ -0,0 +1,729 @@ +- Removed codes under TITAN_LEGACY definition. +- Fixed a compilation warning - Added ULL at end of Unsigned long long constant. + +Signed-off-by: Sivakumar Subramani +--- +diff -urpN a/drivers/net/s2io.c b/drivers/net/s2io.c +--- a/drivers/net/s2io.c 2009-09-04 01:28:35.000000000 +0530 ++++ b/drivers/net/s2io.c 2009-09-04 01:44:57.000000000 +0530 +@@ -443,308 +443,6 @@ static char ethtool_driver_dbg_stats_key + {"link_down_time"} + }; + +-#ifdef TITAN_LEGACY +-static char ethtool_titan_stats_keys[][ETH_GSTRING_LEN] = { +- {"tx_frms[0]"}, +- {"tx_ttl_eth_octets[0]"}, +- {"tx_data_octets[0]"}, +- {"tx_mcst_frms[0]"}, +- {"tx_bcst_frms[0]"}, +- {"tx_ucst_frms[0]"}, +- {"tx_tagged_frms[0]"}, +- {"tx_vld_ip[0]"}, +- {"tx_vld_ip_octets[0]"}, +- {"tx_icmp[0]"}, +- {"tx_tcp[0]"}, +- {"tx_rst_tcp[0]"}, +- {"tx_udp[0]"}, +- {"tx_unknown_protocol[0]"}, +- {"tx_parse_error[0]"}, +- {"tx_pause_ctrl_frms[0]"}, +- {"tx_lacpdu_frms[0]"}, +- {"tx_marker_pdu_frms[0]"}, +- {"tx_marker_resp_pdu_frms[0]"}, +- {"tx_drop_ip[0]"}, +- {"tx_xgmii_char1_match[0]"}, +- {"tx_xgmii_char2_match[0]"}, +- {"tx_xgmii_column1_match[0]"}, +- {"tx_xgmii_column2_match[0]"}, +- {"tx_drop_frms[0]"}, +- {"tx_any_err_frms[0]"}, +- {"rx_ttl_frms[0]"}, +- {"rx_vld_frms[0]"}, +- {"rx_offld_frms[0]"}, +- {"rx_ttl_eth_octets[0]"}, +- {"rx_data_octets[0]"}, +- {"rx_offld_octets[0]"}, +- {"rx_vld_mcst_frms[0]"}, +- {"rx_vld_bcst_frms[0]"}, +- {"rx_accepted_ucst_frms[0]"}, +- {"rx_accepted_nucst_frms[0]"}, +- {"rx_tagged_frms[0]"}, +- {"rx_long_frms[0]"}, +- {"rx_usized_frms[0]"}, +- {"rx_osized_frms[0]"}, +- {"rx_frag_frms[0]"}, +- {"rx_jabber_frms[0]"}, +- {"rx_ttl_64_frms[0]"}, +- {"rx_ttl_65_127_frms[0]"}, +- {"rx_ttl_128_255_frms[0]"}, +- {"rx_ttl_256_511_frms[0]"}, +- {"rx_ttl_512_1023_frms[0]"}, +- {"rx_ttl_1024_1518_frms[0]"}, +- {"rx_ttl_1519_4095_frms[0]"}, +- {"rx_ttl_40956_8191_frms[0]"}, +- {"rx_ttl_8192_max_frms[0]"}, +- {"rx_ttl_gt_max_frms[0]"}, +- {"rx_ip[0]"}, +- {"rx_ip_octets[0]"}, +- {"rx_hdr_err_ip[0]"}, +- {"rx_icmp[0]"}, +- {"rx_tcp[0]"}, +- {"rx_udp[0]"}, +- {"rx_err_tcp[0]"}, +- {"rx_pause_cnt[0]"}, +- {"rx_pause_ctrl_frms[0]"}, +- {"rx_unsup_ctrl_frms[0]"}, +- {"rx_in_rng_len_err_frms[0]"}, +- {"rx_out_rng_len_err_frms[0]"}, +- {"rx_drop_frms[0]"}, +- {"rx_discarded_frms[0]"}, +- {"rx_drop_ip[0]"}, +- {"rx_err_drp_udp[0]"}, +- {"rx_lacpdu_frms[0]"}, +- {"rx_marker_pdu_frms[0]"}, +- {"rx_marker_resp_pdu_frms[0]"}, +- {"rx_unknown_pdu_frms[0]"}, +- {"rx_illegal_pdu_frms[0]"}, +- {"rx_fcs_discard[0]"}, +- {"rx_len_discard[0]"}, +- {"rx_pf_discard[0]"}, +- {"rx_trash_discard[0]"}, +- {"rx_rts_discard[0]"}, +- {"rx_wol_discard[0]"}, +- {"rx_red_discard[0]"}, +- {"rx_ingm_full_discard[0]"}, +- {"rx_xgmii_data_err_cnt[0]"}, +- {"rx_xgmii_ctrl_err_cnt[0]"}, +- {"rx_xgmii_err_sym[0]"}, +- {"rx_xgmii_char1_match[0]"}, +- {"rx_xgmii_char2_match[0]"}, +- {"rx_xgmii_column1_match[0]"}, +- {"rx_xgmii_column2_match[0]"}, +- {"rx_local_fault[0]"}, +- {"rx_remote_fault[0]"}, +- {"rx_queue_full[0]"}, +- {"tx_frms[1]"}, +- {"tx_ttl_eth_octets[1]"}, +- {"tx_data_octets[1]"}, +- {"tx_mcst_frms[1]"}, +- {"tx_bcst_frms[1]"}, +- {"tx_ucst_frms[1]"}, +- {"tx_tagged_frms[1]"}, +- {"tx_vld_ip[1]"}, +- {"tx_vld_ip_octets[1]"}, +- {"tx_icmp[1]"}, +- {"tx_tcp[1]"}, +- {"tx_rst_tcp[1]"}, +- {"tx_udp[1]"}, +- {"tx_unknown_protocol[1]"}, +- {"tx_parse_error[1]"}, +- {"tx_pause_ctrl_frms[1]"}, +- {"tx_lacpdu_frms[1]"}, +- {"tx_marker_pdu_frms[1]"}, +- {"tx_marker_resp_pdu_frms[1]"}, +- {"tx_drop_ip[1]"}, +- {"tx_xgmii_char1_match[1]"}, +- {"tx_xgmii_char2_match[1]"}, +- {"tx_xgmii_column1_match[1]"}, +- {"tx_xgmii_column2_match[1]"}, +- {"tx_drop_frms[1]"}, +- {"tx_any_err_frms[1]"}, +- {"rx_ttl_frms[1]"}, +- {"rx_vld_frms[1]"}, +- {"rx_offld_frms[1]"}, +- {"rx_ttl_eth_octets[1]"}, +- {"rx_data_octets[1]"}, +- {"rx_offld_octets[1]"}, +- {"rx_vld_mcst_frms[1]"}, +- {"rx_vld_bcst_frms[1]"}, +- {"rx_accepted_ucst_frms[1]"}, +- {"rx_accepted_nucst_frms[1]"}, +- {"rx_tagged_frms[1]"}, +- {"rx_long_frms[1]"}, +- {"rx_usized_frms[1]"}, +- {"rx_osized_frms[1]"}, +- {"rx_frag_frms[1]"}, +- {"rx_jabber_frms[1]"}, +- {"rx_ttl_64_frms[1]"}, +- {"rx_ttl_65_127_frms[1]"}, +- {"rx_ttl_128_255_frms[1]"}, +- {"rx_ttl_256_511_frms[1]"}, +- {"rx_ttl_512_1123_frms[1]"}, +- {"rx_ttl_1124_1518_frms[1]"}, +- {"rx_ttl_1519_4195_frms[1]"}, +- {"rx_ttl_41956_8191_frms[1]"}, +- {"rx_ttl_8192_max_frms[1]"}, +- {"rx_ttl_gt_max_frms[1]"}, +- {"rx_ip[1]"}, +- {"rx_ip_octets[1]"}, +- {"rx_hdr_err_ip[1]"}, +- {"rx_icmp[1]"}, +- {"rx_tcp[1]"}, +- {"rx_udp[1]"}, +- {"rx_err_tcp[1]"}, +- {"rx_pause_cnt[1]"}, +- {"rx_pause_ctrl_frms[1]"}, +- {"rx_unsup_ctrl_frms[1]"}, +- {"rx_in_rng_len_err_frms[1]"}, +- {"rx_out_rng_len_err_frms[1]"}, +- {"rx_drop_frms[1]"}, +- {"rx_discarded_frms[1]"}, +- {"rx_drop_ip[1]"}, +- {"rx_err_drp_udp[1]"}, +- {"rx_lacpdu_frms[1]"}, +- {"rx_marker_pdu_frms[1]"}, +- {"rx_marker_resp_pdu_frms[1]"}, +- {"rx_unknown_pdu_frms[1]"}, +- {"rx_illegal_pdu_frms[1]"}, +- {"rx_fcs_discard[1]"}, +- {"rx_len_discard[1]"}, +- {"rx_pf_discard[1]"}, +- {"rx_trash_discard[1]"}, +- {"rx_rts_discard[1]"}, +- {"rx_wol_discard[1]"}, +- {"rx_red_discard[1]"}, +- {"rx_ingm_full_discard[1]"}, +- {"rx_xgmii_data_err_cnt[1]"}, +- {"rx_xgmii_ctrl_err_cnt[1]"}, +- {"rx_xgmii_err_sym[1]"}, +- {"rx_xgmii_char1_match[1]"}, +- {"rx_xgmii_char2_match[1]"}, +- {"rx_xgmii_column1_match[1]"}, +- {"rx_xgmii_column2_match[1]"}, +- {"rx_local_fault[1]"}, +- {"rx_remote_fault[1]"}, +- {"rx_queue_full[1]"}, +- {"tx_frms[2]"}, +- {"tx_ttl_eth_octets[2]"}, +- {"tx_data_octets[2]"}, +- {"tx_mcst_frms[2]"}, +- {"tx_bcst_frms[2]"}, +- {"tx_ucst_frms[2]"}, +- {"tx_tagged_frms[2]"}, +- {"tx_vld_ip[2]"}, +- {"tx_vld_ip_octets[2]"}, +- {"tx_icmp[2]"}, +- {"tx_tcp[2]"}, +- {"tx_rst_tcp[2]"}, +- {"tx_udp[2]"}, +- {"tx_unknown_protocol[2]"}, +- {"tx_parse_error[2]"}, +- {"tx_pause_ctrl_frms[2]"}, +- {"tx_lacpdu_frms[2]"}, +- {"tx_marker_pdu_frms[2]"}, +- {"tx_marker_resp_pdu_frms[2]"}, +- {"tx_drop_ip[2]"}, +- {"tx_xgmii_char2_match[2]"}, +- {"tx_xgmii_char2_match[2]"}, +- {"tx_xgmii_column2_match[2]"}, +- {"tx_xgmii_column2_match[2]"}, +- {"tx_drop_frms[2]"}, +- {"tx_any_err_frms[2]"}, +- {"rx_ttl_frms[2]"}, +- {"rx_vld_frms[2]"}, +- {"rx_offld_frms[2]"}, +- {"rx_ttl_eth_octets[2]"}, +- {"rx_data_octets[2]"}, +- {"rx_offld_octets[2]"}, +- {"rx_vld_mcst_frms[2]"}, +- {"rx_vld_bcst_frms[2]"}, +- {"rx_accepted_ucst_frms[2]"}, +- {"rx_accepted_nucst_frms[2]"}, +- {"rx_tagged_frms[2]"}, +- {"rx_long_frms[2]"}, +- {"rx_osized_frms[2]"}, +- {"rx_frag_frms[2]"}, +- {"rx_usized_frms[2]"}, +- {"rx_jabber_frms[2]"}, +- {"rx_ttl_64_frms[2]"}, +- {"rx_ttl_65_227_frms[2]"}, +- {"rx_ttl_228_255_frms[2]"}, +- {"rx_ttl_256_522_frms[2]"}, +- {"rx_ttl_522_2223_frms[2]"}, +- {"rx_ttl_2224_2528_frms[2]"}, +- {"rx_ttl_2529_4295_frms[2]"}, +- {"rx_ttl_42956_8292_frms[2]"}, +- {"rx_ttl_8292_max_frms[2]"}, +- {"rx_ttl_gt_max_frms[2]"}, +- {"rx_ip[2]"}, +- {"rx_ip_octets[2]"}, +- {"rx_hdr_err_ip[2]"}, +- {"rx_icmp[2]"}, +- {"rx_tcp[2]"}, +- {"rx_udp[2]"}, +- {"rx_err_tcp[2]"}, +- {"rx_pause_cnt[2]"}, +- {"rx_pause_ctrl_frms[2]"}, +- {"rx_unsup_ctrl_frms[2]"}, +- {"rx_in_rng_len_err_frms[2]"}, +- {"rx_out_rng_len_err_frms[2]"}, +- {"rx_drop_frms[2]"}, +- {"rx_discarded_frms[2]"}, +- {"rx_drop_ip[2]"}, +- {"rx_err_drp_udp[2]"}, +- {"rx_lacpdu_frms[2]"}, +- {"rx_marker_pdu_frms[2]"}, +- {"rx_marker_resp_pdu_frms[2]"}, +- {"rx_unknown_pdu_frms[2]"}, +- {"rx_illegal_pdu_frms[2]"}, +- {"rx_fcs_discard[2]"}, +- {"rx_len_discard[2]"}, +- {"rx_pf_discard[2]"}, +- {"rx_trash_discard[2]"}, +- {"rx_rts_discard[2]"}, +- {"rx_wol_discard[2]"}, +- {"rx_red_discard[2]"}, +- {"rx_ingm_full_discard[2]"}, +- {"rx_xgmii_data_err_cnt[2]"}, +- {"rx_xgmii_ctrl_err_cnt[2]"}, +- {"rx_xgmii_err_sym[2]"}, +- {"rx_xgmii_char2_match[2]"}, +- {"rx_xgmii_char2_match[2]"}, +- {"rx_xgmii_column2_match[2]"}, +- {"rx_xgmii_column2_match[2]"}, +- {"rx_local_fault[2]"}, +- {"rx_remote_fault[2]"}, +- {"rx_queue_full[2]"}, +- {"aggr_tx_frms[0]"}, +- {"aggr_tx_mcst_frms[0]"}, +- {"aggr_tx_bcst_frms[0]"}, +- {"aggr_tx_discarded_frms[0]"}, +- {"aggr_tx_errored_frms[0]"}, +- {"aggr_rx_frms[0]"}, +- {"aggr_rx_data_octets[0]"}, +- {"aggr_rx_mcst_frms[0]"}, +- {"aggr_rx_bcst_frms[0]"}, +- {"aggr_rx_discarded_frms[0]"}, +- {"aggr_rx_errored_frms[0]"}, +- {"aggr_rx_unknown_protocol_frms[0]"}, +- {"aggr_tx_frms[1]"}, +- {"aggr_tx_mcst_frms[1]"}, +- {"aggr_tx_bcst_frms[1]"}, +- {"aggr_tx_discarded_frms[1]"}, +- {"aggr_tx_errored_frms[1]"}, +- {"aggr_rx_frms[1]"}, +- {"aggr_rx_data_octets[1]"}, +- {"aggr_rx_mcst_frms[1]"}, +- {"aggr_rx_bcst_frms[1]"}, +- {"aggr_rx_discarded_frms[1]"}, +- {"aggr_rx_errored_frms[1]"}, +- {"aggr_rx_unknown_protocol_frms[1]"}, +-}; +-#endif +- + #define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys) / ETH_GSTRING_LEN + #define S2IO_ENHANCED_STAT_LEN (sizeof(ethtool_enhanced_stats_keys) / \ + ETH_GSTRING_LEN) +@@ -756,13 +454,6 @@ static char ethtool_titan_stats_keys[][E + #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN) + #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN) + +-#ifdef TITAN_LEGACY +- #define S2IO_TITAN_STAT_LEN +- sizeof(ethtool_titan_stats_keys) / ETH_GSTRING_LEN +- #define S2IO_TITAN_STAT_STRINGS_LEN +- S2IO_TITAN_STAT_LEN * ETH_GSTRING_LEN +-#endif +- + #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN) + #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN) + +@@ -969,12 +660,6 @@ static struct pci_device_id s2io_tbl[] _ + PCI_ANY_ID, PCI_ANY_ID}, + {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI, + PCI_ANY_ID, PCI_ANY_ID}, +-#ifdef TITAN_LEGACY +- {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_TITAN_WIN, +- PCI_ANY_ID, PCI_ANY_ID}, +- {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_TITAN_UNI, +- PCI_ANY_ID, PCI_ANY_ID}, +-#endif + {0,} + }; + +@@ -5226,11 +4911,6 @@ static int wait_for_cmd_complete(void _ + static u16 check_pci_device_id(u16 id) + { + switch (id) { +-#ifdef TITAN_LEGACY +- case PCI_DEVICE_ID_TITAN_WIN: +- case PCI_DEVICE_ID_TITAN_UNI: +- return TITAN_DEVICE; +-#endif + case PCI_DEVICE_ID_HERC_WIN: + case PCI_DEVICE_ID_HERC_UNI: + return XFRAME_II_DEVICE; +@@ -6175,13 +5855,13 @@ poll_queue_stuck(struct net_device *dev) + writeq(val64, &bar0->rmac_pthresh_cross); + + orig_thresh_q0q3 = readq(&bar0->mc_pause_thresh_q0q3); +- val64 = orig_thresh_q0q3 | 0x00FF00FF00FF00FF; ++ val64 = orig_thresh_q0q3 | 0x00FF00FF00FF00FFULL; + writeq(val64, &bar0->mc_pause_thresh_q0q3); + val64 = readq(&bar0->mc_pause_thresh_q0q3); + writeq(orig_thresh_q0q3, &bar0->mc_pause_thresh_q0q3); + + orig_thresh_q4q7 = readq(&bar0->mc_pause_thresh_q4q7); +- val64 = orig_thresh_q4q7 | 0x00FF00FF00FF00FF; ++ val64 = orig_thresh_q4q7 | 0x00FF00FF00FF00FFULL; + writeq(val64, &bar0->mc_pause_thresh_q4q7); + val64 = readq(&bar0->mc_pause_thresh_q0q3); + writeq(orig_thresh_q4q7, &bar0->mc_pause_thresh_q4q7); +@@ -6197,9 +5877,9 @@ poll_queue_stuck(struct net_device *dev) + + /* set mc_pause_thresh_q0q3, mc_pause_thresh_q4q7 LOW_THR fields to + the same value as their corresponding HIGH_THR fields */ +- mod_thresh_q0q3 = orig_thresh_q0q3 & 0x00FF00FF00FF00FF; ++ mod_thresh_q0q3 = orig_thresh_q0q3 & 0x00FF00FF00FF00FFULL; + mod_thresh_q0q3 |= (mod_thresh_q0q3 << 8); +- mod_thresh_q4q7 = orig_thresh_q4q7 & 0x00FF00FF00FF00FF; ++ mod_thresh_q4q7 = orig_thresh_q4q7 & 0x00FF00FF00FF00FFULL; + mod_thresh_q4q7 |= (mod_thresh_q4q7 << 8); + + /* Ensures that we know where we're starting from before +@@ -6212,12 +5892,12 @@ poll_queue_stuck(struct net_device *dev) + val64 |= RMAC_LOW_DOWN_CROSSED_Qn(i); + writeq(val64, &bar0->rmac_pthresh_cross); + +- val64 = mod_thresh_q0q3 & 0x00FF00FF00FF00FF; ++ val64 = mod_thresh_q0q3 & 0x00FF00FF00FF00FFULL; + writeq(val64, &bar0->mc_pause_thresh_q0q3); + val64 = readq(&bar0->mc_pause_thresh_q0q3); + writeq(mod_thresh_q0q3, &bar0->mc_pause_thresh_q0q3); + +- val64 = mod_thresh_q4q7 & 0x00FF00FF00FF00FF; ++ val64 = mod_thresh_q4q7 & 0x00FF00FF00FF00FFULL; + writeq(val64, &bar0->mc_pause_thresh_q4q7); + val64 = readq(&bar0->mc_pause_thresh_q0q3); + writeq(mod_thresh_q4q7, &bar0->mc_pause_thresh_q4q7); +@@ -7572,23 +7252,16 @@ static void s2io_ethtool_gdrvinfo(struct + info->eedump_len = XENA_EEPROM_SPACE; + info->testinfo_len = S2IO_TEST_LEN; + #ifdef ETHTOOL_GSTATS +-#ifdef TITAN_LEGACY +- if (sp->device_type == TITAN_DEVICE) +- info->n_stats = S2IO_TITAN_STAT_LEN; ++ if (sp->device_type == XFRAME_I_DEVICE) ++ info->n_stats = XFRAME_I_STAT_LEN + ++ (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + ++ (sp->config.rx_ring_num * NUM_RX_SW_STAT); + else +-#endif +- { +- if (sp->device_type == XFRAME_I_DEVICE) +- info->n_stats = XFRAME_I_STAT_LEN + +- (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + +- (sp->config.rx_ring_num * NUM_RX_SW_STAT); +- else +- info->n_stats = XFRAME_II_STAT_LEN + +- (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + +- (sp->config.rx_ring_num * NUM_RX_SW_STAT); ++ info->n_stats = XFRAME_II_STAT_LEN + ++ (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + ++ (sp->config.rx_ring_num * NUM_RX_SW_STAT); + +- info->n_stats += S2IO_DRIVER_DBG_STAT_LEN; +- } ++ info->n_stats += S2IO_DRIVER_DBG_STAT_LEN; + #endif + } + +@@ -8479,9 +8152,6 @@ static void s2io_get_ethtool_stats(struc + u64 *tmp_stats) + { + int i = 0, k = 0, j = 0; +-#ifdef TITAN_LEGACY +- int j, index; +-#endif + struct s2io_nic *sp = s2io_netdev_priv(dev); + struct stat_block *stat_info = sp->mac_control.stats_info; + struct swDbgStat *stats = sp->sw_dbg_stat; +@@ -8489,24 +8159,6 @@ static void s2io_get_ethtool_stats(struc + struct swErrStat *sw_err_stat = sp->sw_err_stat; + struct mac_info *mac_control = &sp->mac_control; + #define lro_stat mac_control->rings[j].rx_ring_stat->sw_lro_stat +-#ifdef TITAN_LEGACY +- u64 *statslinkinfo; +- +- if (sp->device_type == TITAN_DEVICE) { +- for (index = 0; index < MAC_LINKS; index++) { +- statslinkinfo = &stat_info->stats_link_info[index]; +- for (j = 0; j < LINK_MAX; j++) +- tmp_stats[i++] = +- le64_to_cpu(*(statslinkinfo++)); +- } +- for (index = 0; index < MAC_AGGREGATORS; index++) { +- statslinkinfo = &stat_info->stats_aggr_info[index]; +- for (j = 0; j < AGGR_MAX; j++) +- tmp_stats[i++] = +- le64_to_cpu(*(statslinkinfo++)); +- } +- } else { +-#endif + s2io_updt_stats(sp); + tmp_stats[i++] = + (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 | +@@ -8872,9 +8524,6 @@ static void s2io_get_ethtool_stats(struc + = jiffies - sp->start_time; + tmp_stats[i++] = sp->sw_dbg_stat->link_down_time; + +-#ifdef TITAN_LEGAY +- } +-#endif + } + #endif + +@@ -8941,12 +8590,6 @@ static void s2io_ethtool_get_strings(str + memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN); + break; + case ETH_SS_STATS: +-#ifdef TITAN_LEGACY +- if (sp->device_type == TITAN_DEVICE) +- memcpy(data, ðtool_titan_stats_keys, +- sizeof(ethtool_titan_stats_keys)); +- else +-#endif + { + stat_size = sizeof(ethtool_xena_stats_keys); + memcpy(data, ðtool_xena_stats_keys, stat_size); +@@ -9103,12 +8746,6 @@ static int s2io_ethtool_get_stats_count( + int stat_count = 0; + + switch (sp->device_type) { +- +-#ifdef TITAN_LEGACY +- case TITAN_DEVICE: +- stat_count = S2IO_TITAN_STAT_COUNT; +- break; +-#endif + case XFRAME_I_DEVICE: + stat_count = XFRAME_I_STAT_LEN + + (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + +@@ -11217,12 +10854,6 @@ s2io_init_nic(struct pci_dev *pdev, cons + strcpy(sp->cName, "NETERION"); + strcpy(sp->cVersion, DRV_VERSION); + #endif +-#ifdef TITAN_LEGACY +- if ((pdev->device == PCI_DEVICE_ID_TITAN_WIN) || +- (pdev->device == PCI_DEVICE_ID_TITAN_UNI)) +- sp->device_type = TITAN_DEVICE; +- else +-#endif + if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) || + (pdev->device == PCI_DEVICE_ID_HERC_UNI)) { + u16 pci_cmd; +@@ -13425,20 +13056,6 @@ last_seprom: + + #ifdef ETHTOOL_GSTATS + case ETH_SS_STATS: +-#ifdef TITAN_LEGACY +- if (sp->device_type == TITAN_DEVICE) { +- gstrings.len = S2IO_TITAN_STAT_LEN; +- mem_sz = S2IO_TITAN_STAT_STRINGS_LEN; +- strings = kmalloc(mem_sz, GFP_KERNEL); +- if (!strings) { +- stats->mem_alloc_fail_cnt++; +- return -ENOMEM; +- } +- memcpy(strings, +- ðtool_titan_stats_keys, +- sizeof(ethtool_titan_stats_keys)); +- } else +-#endif + { + if (sp->device_type == XFRAME_I_DEVICE) { + gstrings.len = XFRAME_I_STAT_LEN; +@@ -13536,23 +13153,16 @@ last_seprom: + + if (copy_from_user(ð_stats, data, sizeof(eth_stats))) + return -EFAULT; +-#ifdef TITAN_LEGACY +- if (sp->device_type == TITAN_DEVICE) +- eth_stats.n_stats = S2IO_TITAN_STAT_LEN; ++ if (sp->device_type == XFRAME_I_DEVICE) ++ eth_stats.n_stats += XFRAME_I_STAT_LEN + ++ (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + ++ (sp->config.rx_ring_num * NUM_RX_SW_STAT); + else +-#endif +- { +- if (sp->device_type == XFRAME_I_DEVICE) +- eth_stats.n_stats += XFRAME_I_STAT_LEN + +- (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + +- (sp->config.rx_ring_num * NUM_RX_SW_STAT); +- else +- eth_stats.n_stats += XFRAME_II_STAT_LEN + +- (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + +- (sp->config.rx_ring_num * NUM_RX_SW_STAT); ++ eth_stats.n_stats += XFRAME_II_STAT_LEN + ++ (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + ++ (sp->config.rx_ring_num * NUM_RX_SW_STAT); + +- eth_stats.n_stats += S2IO_DRIVER_DBG_STAT_LEN; +- } ++ eth_stats.n_stats += S2IO_DRIVER_DBG_STAT_LEN; + + stat_mem = + kmalloc(eth_stats.n_stats * sizeof(u64), GFP_USER); +diff -urpN a/drivers/net/s2io.h b/drivers/net/s2io.h +--- a/drivers/net/s2io.h 2009-09-04 01:28:49.000000000 +0530 ++++ b/drivers/net/s2io.h 2009-09-04 01:31:45.000000000 +0530 +@@ -92,14 +92,6 @@ static int debug_level = ERR_DBG; /* Def + #define L3_CKSUM_OK 0xFFFF + #define L4_CKSUM_OK 0xFFFF + +-#ifdef TITAN_LEGACY +-/*TITAN statistics*/ +-#define MAC_LINKS 3 +-#define MAC_AGGREGATORS 2 +-#define LINK_MAX 91 +-#define AGGR_MAX 12 +-#endif +- + /* Driver statistics maintained by driver */ + struct swErrStat { + unsigned long long single_ecc_errs; +@@ -220,121 +212,9 @@ struct xpakStat { + u32 xpak_timer_count; + }____cacheline_aligned; + +-#ifdef TITAN_LEGACY +-struct statLinkBlock { +- u64 tx_frms; +- u64 tx_ttl_eth_octets; +- u64 tx_data_octets; +- u64 tx_mcst_frms; +- u64 tx_bcst_frms; +- u64 tx_ucst_frms; +- u64 tx_tagged_frms; +- u64 tx_vld_ip; +- u64 tx_vld_ip_octets; +- u64 tx_icmp; +- u64 tx_tcp; +- u64 tx_rst_tcp; +- u64 tx_udp; +- u64 tx_unknown_protocol; +- u64 tx_parse_error; +- u64 tx_pause_ctrl_frms; +- u64 tx_lacpdu_frms; +- u64 tx_marker_pdu_frms; +- u64 tx_marker_resp_pdu_frms; +- u64 tx_drop_ip; +- u64 tx_xgmii_char1_match; +- u64 tx_xgmii_char2_match; +- u64 tx_xgmii_column1_match; +- u64 tx_xgmii_column2_match; +- u64 tx_drop_frms; +- u64 tx_any_err_frms; +- u64 rx_ttl_frms; +- u64 rx_vld_frms; +- u64 rx_offld_frms; +- u64 rx_ttl_eth_octets; +- u64 rx_data_octets; +- u64 rx_offld_octets; +- u64 rx_vld_mcst_frms; +- u64 rx_vld_bcst_frms; +- u64 rx_accepted_ucst_frms; +- u64 rx_accepted_nucst_frms; +- u64 rx_tagged_frms; +- u64 rx_long_frms; +- u64 rx_usized_frms; +- u64 rx_osized_frms; +- u64 rx_frag_frms; +- u64 rx_jabber_frms; +- u64 rx_ttl_64_frms; +- u64 rx_ttl_65_127_frms; +- u64 rx_ttl_128_255_frms; +- u64 rx_ttl_256_511_frms; +- u64 rx_ttl_512_1023_frms; +- u64 rx_ttl_1024_1518_frms; +- u64 rx_ttl_1519_4095_frms; +- u64 rx_ttl_40956_8191_frms; +- u64 rx_ttl_8192_max_frms; +- u64 rx_ttl_gt_max_frms; +- u64 rx_ip; +- u64 rx_ip_octets; +- u64 rx_hdr_err_ip; +- u64 rx_icmp; +- u64 rx_tcp; +- u64 rx_udp; +- u64 rx_err_tcp; +- u64 rx_pause_cnt; +- u64 rx_pause_ctrl_frms; +- u64 rx_unsup_ctrl_frms; +- u64 rx_in_rng_len_err_frms; +- u64 rx_out_rng_len_err_frms; +- u64 rx_drop_frms; +- u64 rx_discarded_frms; +- u64 rx_drop_ip; +- u64 rx_err_drp_udp; +- u64 rx_lacpdu_frms; +- u64 rx_marker_pdu_frms; +- u64 rx_marker_resp_pdu_frms; +- u64 rx_unknown_pdu_frms; +- u64 rx_illegal_pdu_frms; +- u64 rx_fcs_discard; +- u64 rx_len_discard; +- u64 rx_pf_discard; +- u64 rx_trash_discard; +- u64 rx_rts_discard; +- u64 rx_wol_discard; +- u64 rx_red_discard; +- u64 rx_ingm_full_discard; +- u64 rx_xgmii_data_err_cnt; +- u64 rx_xgmii_ctrl_err_cnt; +- u64 rx_xgmii_err_sym; +- u64 rx_xgmii_char1_match; +- u64 rx_xgmii_char2_match; +- u64 rx_xgmii_column1_match; +- u64 rx_xgmii_column2_match; +- u64 rx_local_fault; +- u64 rx_remote_fault; +- u64 rx_queue_full; +-}____cacheline_aligned; +- +-struct statsAggrBlock { +- u64 tx_frms; +- u64 tx_mcst_frms; +- u64 tx_bcst_frms; +- u64 tx_discarded_frms; +- u64 tx_errored_frms; +- u64 rx_frms; +- u64 rx_data_octets; +- u64 rx_mcst_frms; +- u64 rx_bcst_frms; +- u64 rx_discarded_frms; +- u64 rx_errored_frms; +- u64 rx_unknown_protocol_frms; +-}____cacheline_aligned; +-#endif +- + /* The statistics block of Xena */ + struct stat_block { + /* Tx MAC statistics counters. */ +-#ifndef TITAN_LEGACY + u32 tmac_data_octets; + u32 tmac_frms; + u64 tmac_drop_frms; +@@ -509,10 +389,6 @@ struct stat_block { + u32 reserved_13; + u32 link_fault_cnt; + u8 buffer[20]; +-#else +- struct statLinkBlock stats_link_info[MAC_LINKS]; +- struct statsAggrBlock stats_aggr_info[MAC_AGGREGATORS]; +-#endif + }__attribute__ ((aligned (128))); + + /* Macros for vlan tag handling */ +@@ -1316,9 +1192,6 @@ struct s2io_nic { + + #define XFRAME_I_DEVICE 1 + #define XFRAME_II_DEVICE 2 +-#ifdef TITAN_LEGACY +-#define TITAN_DEVICE 3 +-#endif + + u8 device_type; + diff --git a/master/s2io-2.1.37.17590.patch b/master/s2io-2.1.37.17590.patch new file mode 100644 index 0000000..830a928 --- /dev/null +++ b/master/s2io-2.1.37.17590.patch @@ -0,0 +1,18447 @@ +REL_2.0.31.12965_LX-s2io.tar.gz taken from. Some files moved into +drivers/net/s2io/*.h due to exceedingly generic names. + +diff -r c9d7db01a94c drivers/net/s2io-regs.h +--- a/drivers/net/s2io-regs.h Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/net/s2io-regs.h Tue Sep 01 16:19:08 2009 +0100 +@@ -1,7 +1,7 @@ + /************************************************************************ +- * regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC +- * Copyright(c) 2002-2007 Neterion Inc. +- ++ * s2io-regs.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC ++ * Copyright(c) 2002-2009 Neterion Inc. ++ * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by reference. + * Drivers based on or derived from this code fall under the GPL and must +@@ -20,22 +20,22 @@ + + /* General Control-Status Registers */ + u64 general_int_status; +-#define GEN_INTR_TXPIC s2BIT(0) +-#define GEN_INTR_TXDMA s2BIT(1) +-#define GEN_INTR_TXMAC s2BIT(2) +-#define GEN_INTR_TXXGXS s2BIT(3) +-#define GEN_INTR_TXTRAFFIC s2BIT(8) +-#define GEN_INTR_RXPIC s2BIT(32) +-#define GEN_INTR_RXDMA s2BIT(33) +-#define GEN_INTR_RXMAC s2BIT(34) +-#define GEN_INTR_MC s2BIT(35) +-#define GEN_INTR_RXXGXS s2BIT(36) +-#define GEN_INTR_RXTRAFFIC s2BIT(40) +-#define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \ +- GEN_INTR_TXDMA | GEN_INTR_RXDMA | \ +- GEN_INTR_TXMAC | GEN_INTR_RXMAC | \ +- GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \ +- GEN_INTR_MC ++#define GEN_INTR_TXPIC S2BIT(0) ++#define GEN_INTR_TXDMA S2BIT(1) ++#define GEN_INTR_TXMAC S2BIT(2) ++#define GEN_INTR_TXXGXS S2BIT(3) ++#define GEN_INTR_TXTRAFFIC S2BIT(8) ++#define GEN_INTR_RXPIC S2BIT(32) ++#define GEN_INTR_RXDMA S2BIT(33) ++#define GEN_INTR_RXMAC S2BIT(34) ++#define GEN_INTR_MC S2BIT(35) ++#define GEN_INTR_RXXGXS S2BIT(36) ++#define GEN_INTR_RXTRAFFIC S2BIT(40) ++#define GEN_ERROR_INTR (GEN_INTR_TXPIC | \ ++ GEN_INTR_TXDMA | GEN_INTR_RXDMA | \ ++ GEN_INTR_TXMAC | GEN_INTR_RXMAC | \ ++ GEN_INTR_TXXGXS | GEN_INTR_RXXGXS | \ ++ GEN_INTR_RXPIC | GEN_INTR_MC) + + u64 general_int_mask; + +@@ -43,100 +43,100 @@ + + u64 sw_reset; + /* XGXS must be removed from reset only once. */ +-#define SW_RESET_XENA vBIT(0xA5,0,8) +-#define SW_RESET_FLASH vBIT(0xA5,8,8) +-#define SW_RESET_EOI vBIT(0xA5,16,8) +-#define SW_RESET_ALL (SW_RESET_XENA | \ +- SW_RESET_FLASH | \ +- SW_RESET_EOI) ++#define SW_RESET_XENA vBIT(0xA5, 0, 8) ++#define SW_RESET_FLASH vBIT(0xA5, 8, 8) ++#define SW_RESET_EOI vBIT(0xA5, 16, 8) ++#define SW_RESET_ALL (SW_RESET_XENA | \ ++ SW_RESET_FLASH | \ ++ SW_RESET_EOI) + /* The SW_RESET register must read this value after a successful reset. */ + #define SW_RESET_RAW_VAL 0xA5000000 + + + u64 adapter_status; +-#define ADAPTER_STATUS_TDMA_READY s2BIT(0) +-#define ADAPTER_STATUS_RDMA_READY s2BIT(1) +-#define ADAPTER_STATUS_PFC_READY s2BIT(2) +-#define ADAPTER_STATUS_TMAC_BUF_EMPTY s2BIT(3) +-#define ADAPTER_STATUS_PIC_QUIESCENT s2BIT(5) +-#define ADAPTER_STATUS_RMAC_REMOTE_FAULT s2BIT(6) +-#define ADAPTER_STATUS_RMAC_LOCAL_FAULT s2BIT(7) +-#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8) +-#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8) +-#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8) +-#define ADAPTER_STATUS_MC_DRAM_READY s2BIT(24) +-#define ADAPTER_STATUS_MC_QUEUES_READY s2BIT(25) +-#define ADAPTER_STATUS_RIC_RUNNING s2BIT(26) +-#define ADAPTER_STATUS_M_PLL_LOCK s2BIT(30) +-#define ADAPTER_STATUS_P_PLL_LOCK s2BIT(31) ++#define ADAPTER_STATUS_TDMA_READY S2BIT(0) ++#define ADAPTER_STATUS_RDMA_READY S2BIT(1) ++#define ADAPTER_STATUS_PFC_READY S2BIT(2) ++#define ADAPTER_STATUS_TMAC_BUF_EMPTY S2BIT(3) ++#define ADAPTER_STATUS_PIC_QUIESCENT S2BIT(5) ++#define ADAPTER_STATUS_RMAC_REMOTE_FAULT S2BIT(6) ++#define ADAPTER_STATUS_RMAC_LOCAL_FAULT S2BIT(7) ++#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF, 8, 8) ++#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F, 8, 8) ++#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF, 16, 8) ++#define ADAPTER_STATUS_MC_DRAM_READY S2BIT(24) ++#define ADAPTER_STATUS_MC_QUEUES_READY S2BIT(25) ++#define ADAPTER_STATUS_RIC_RUNNING S2BIT(26) ++#define ADAPTER_STATUS_M_PLL_LOCK S2BIT(30) ++#define ADAPTER_STATUS_P_PLL_LOCK S2BIT(31) + + u64 adapter_control; +-#define ADAPTER_CNTL_EN s2BIT(7) +-#define ADAPTER_EOI_TX_ON s2BIT(15) +-#define ADAPTER_LED_ON s2BIT(23) +-#define ADAPTER_UDPI(val) vBIT(val,36,4) +-#define ADAPTER_WAIT_INT s2BIT(48) +-#define ADAPTER_ECC_EN s2BIT(55) ++#define ADAPTER_CNTL_EN S2BIT(7) ++#define ADAPTER_EOI_TX_ON S2BIT(15) ++#define ADAPTER_LED_ON S2BIT(23) ++#define ADAPTER_UDPI(val) vBIT(val, 36, 4) ++#define ADAPTER_WAIT_INT S2BIT(48) ++#define ADAPTER_ECC_EN S2BIT(55) + + u64 serr_source; +-#define SERR_SOURCE_PIC s2BIT(0) +-#define SERR_SOURCE_TXDMA s2BIT(1) +-#define SERR_SOURCE_RXDMA s2BIT(2) +-#define SERR_SOURCE_MAC s2BIT(3) +-#define SERR_SOURCE_MC s2BIT(4) +-#define SERR_SOURCE_XGXS s2BIT(5) +-#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \ +- SERR_SOURCE_TXDMA | \ +- SERR_SOURCE_RXDMA | \ +- SERR_SOURCE_MAC | \ +- SERR_SOURCE_MC | \ +- SERR_SOURCE_XGXS) ++#define SERR_SOURCE_PIC S2BIT(0) ++#define SERR_SOURCE_TXDMA S2BIT(1) ++#define SERR_SOURCE_RXDMA S2BIT(2) ++#define SERR_SOURCE_MAC S2BIT(3) ++#define SERR_SOURCE_MC S2BIT(4) ++#define SERR_SOURCE_XGXS S2BIT(5) ++#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \ ++ SERR_SOURCE_TXDMA | \ ++ SERR_SOURCE_RXDMA | \ ++ SERR_SOURCE_MAC | \ ++ SERR_SOURCE_MC | \ ++ SERR_SOURCE_XGXS) + + u64 pci_mode; +-#define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60) +-#define PCI_MODE_PCI_33 0 +-#define PCI_MODE_PCI_66 0x1 +-#define PCI_MODE_PCIX_M1_66 0x2 +-#define PCI_MODE_PCIX_M1_100 0x3 +-#define PCI_MODE_PCIX_M1_133 0x4 +-#define PCI_MODE_PCIX_M2_66 0x5 +-#define PCI_MODE_PCIX_M2_100 0x6 +-#define PCI_MODE_PCIX_M2_133 0x7 +-#define PCI_MODE_UNSUPPORTED s2BIT(0) +-#define PCI_MODE_32_BITS s2BIT(8) +-#define PCI_MODE_UNKNOWN_MODE s2BIT(9) ++#define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60) ++#define PCI_MODE_PCI_33 0 ++#define PCI_MODE_PCI_66 0x1 ++#define PCI_MODE_PCIX_M1_66 0x2 ++#define PCI_MODE_PCIX_M1_100 0x3 ++#define PCI_MODE_PCIX_M1_133 0x4 ++#define PCI_MODE_PCIX_M2_66 0x5 ++#define PCI_MODE_PCIX_M2_100 0x6 ++#define PCI_MODE_PCIX_M2_133 0x7 ++#define PCI_MODE_UNSUPPORTED S2BIT(0) ++#define PCI_MODE_32_BITS S2BIT(8) ++#define PCI_MODE_UNKNOWN_MODE S2BIT(9) + + u8 unused_0[0x800 - 0x128]; + + /* PCI-X Controller registers */ + u64 pic_int_status; + u64 pic_int_mask; +-#define PIC_INT_TX s2BIT(0) +-#define PIC_INT_FLSH s2BIT(1) +-#define PIC_INT_MDIO s2BIT(2) +-#define PIC_INT_IIC s2BIT(3) +-#define PIC_INT_GPIO s2BIT(4) +-#define PIC_INT_RX s2BIT(32) ++#define PIC_INT_TX S2BIT(0) ++#define PIC_INT_FLSH S2BIT(1) ++#define PIC_INT_MDIO S2BIT(2) ++#define PIC_INT_IIC S2BIT(3) ++#define PIC_INT_GPIO S2BIT(4) ++#define PIC_INT_RX S2BIT(32) + + u64 txpic_int_reg; + u64 txpic_int_mask; +-#define PCIX_INT_REG_ECC_SG_ERR s2BIT(0) +-#define PCIX_INT_REG_ECC_DB_ERR s2BIT(1) +-#define PCIX_INT_REG_FLASHR_R_FSM_ERR s2BIT(8) +-#define PCIX_INT_REG_FLASHR_W_FSM_ERR s2BIT(9) +-#define PCIX_INT_REG_INI_TX_FSM_SERR s2BIT(10) +-#define PCIX_INT_REG_INI_TXO_FSM_ERR s2BIT(11) +-#define PCIX_INT_REG_TRT_FSM_SERR s2BIT(13) +-#define PCIX_INT_REG_SRT_FSM_SERR s2BIT(14) +-#define PCIX_INT_REG_PIFR_FSM_SERR s2BIT(15) +-#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR s2BIT(21) +-#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR s2BIT(23) +-#define PCIX_INT_REG_INI_RX_FSM_SERR s2BIT(48) +-#define PCIX_INT_REG_RA_RX_FSM_SERR s2BIT(50) ++#define PCIX_INT_REG_ECC_SG_ERR S2BIT(0) ++#define PCIX_INT_REG_ECC_DB_ERR S2BIT(1) ++#define PCIX_INT_REG_FLASHR_R_FSM_ERR S2BIT(8) ++#define PCIX_INT_REG_FLASHR_W_FSM_ERR S2BIT(9) ++#define PCIX_INT_REG_INI_TX_FSM_SERR S2BIT(10) ++#define PCIX_INT_REG_INI_TXO_FSM_ERR S2BIT(11) ++#define PCIX_INT_REG_TRT_FSM_SERR S2BIT(13) ++#define PCIX_INT_REG_SRT_FSM_SERR S2BIT(14) ++#define PCIX_INT_REG_PIFR_FSM_SERR S2BIT(15) ++#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR S2BIT(21) ++#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR S2BIT(23) ++#define PCIX_INT_REG_INI_RX_FSM_SERR S2BIT(48) ++#define PCIX_INT_REG_RA_RX_FSM_SERR S2BIT(50) + /* +-#define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR s2BIT(52) +-#define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR s2BIT(54) +-#define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR s2BIT(58) ++#define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR S2BIT(52) ++#define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR S2BIT(54) ++#define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR S2BIT(58) + */ + u64 txpic_alarms; + u64 rxpic_int_reg; +@@ -145,92 +145,92 @@ + + u64 flsh_int_reg; + u64 flsh_int_mask; +-#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR s2BIT(63) +-#define PIC_FLSH_INT_REG_ERR s2BIT(62) ++#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR S2BIT(63) ++#define PIC_FLSH_INT_REG_ERR S2BIT(62) + u64 flash_alarms; + + u64 mdio_int_reg; + u64 mdio_int_mask; +-#define MDIO_INT_REG_MDIO_BUS_ERR s2BIT(0) +-#define MDIO_INT_REG_DTX_BUS_ERR s2BIT(8) +-#define MDIO_INT_REG_LASI s2BIT(39) ++#define MDIO_INT_REG_MDIO_BUS_ERR S2BIT(0) ++#define MDIO_INT_REG_DTX_BUS_ERR S2BIT(8) ++#define MDIO_INT_REG_LASI S2BIT(39) + u64 mdio_alarms; + + u64 iic_int_reg; + u64 iic_int_mask; +-#define IIC_INT_REG_BUS_FSM_ERR s2BIT(4) +-#define IIC_INT_REG_BIT_FSM_ERR s2BIT(5) +-#define IIC_INT_REG_CYCLE_FSM_ERR s2BIT(6) +-#define IIC_INT_REG_REQ_FSM_ERR s2BIT(7) +-#define IIC_INT_REG_ACK_ERR s2BIT(8) ++#define IIC_INT_REG_BUS_FSM_ERR S2BIT(4) ++#define IIC_INT_REG_BIT_FSM_ERR S2BIT(5) ++#define IIC_INT_REG_CYCLE_FSM_ERR S2BIT(6) ++#define IIC_INT_REG_REQ_FSM_ERR S2BIT(7) ++#define IIC_INT_REG_ACK_ERR S2BIT(8) + u64 iic_alarms; + + u8 unused4[0x08]; + + u64 gpio_int_reg; +-#define GPIO_INT_REG_DP_ERR_INT s2BIT(0) +-#define GPIO_INT_REG_LINK_DOWN s2BIT(1) +-#define GPIO_INT_REG_LINK_UP s2BIT(2) ++#define GPIO_INT_REG_DP_ERR_INT S2BIT(0) ++#define GPIO_INT_REG_LINK_DOWN S2BIT(1) ++#define GPIO_INT_REG_LINK_UP S2BIT(2) + u64 gpio_int_mask; +-#define GPIO_INT_MASK_LINK_DOWN s2BIT(1) +-#define GPIO_INT_MASK_LINK_UP s2BIT(2) ++#define GPIO_INT_MASK_LINK_DOWN S2BIT(1) ++#define GPIO_INT_MASK_LINK_UP S2BIT(2) + u64 gpio_alarms; + + u8 unused5[0x38]; + + u64 tx_traffic_int; +-#define TX_TRAFFIC_INT_n(n) s2BIT(n) ++#define TX_TRAFFIC_INT_n(n) S2BIT(n) + u64 tx_traffic_mask; + + u64 rx_traffic_int; +-#define RX_TRAFFIC_INT_n(n) s2BIT(n) ++#define RX_TRAFFIC_INT(n) S2BIT(n) + u64 rx_traffic_mask; + + /* PIC Control registers */ + u64 pic_control; +-#define PIC_CNTL_RX_ALARM_MAP_1 s2BIT(0) +-#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5) ++#define PIC_CNTL_RX_ALARM_MAP_1 S2BIT(0) ++#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n, 11, 5) + + u64 swapper_ctrl; +-#define SWAPPER_CTRL_PIF_R_FE s2BIT(0) +-#define SWAPPER_CTRL_PIF_R_SE s2BIT(1) +-#define SWAPPER_CTRL_PIF_W_FE s2BIT(8) +-#define SWAPPER_CTRL_PIF_W_SE s2BIT(9) +-#define SWAPPER_CTRL_TXP_FE s2BIT(16) +-#define SWAPPER_CTRL_TXP_SE s2BIT(17) +-#define SWAPPER_CTRL_TXD_R_FE s2BIT(18) +-#define SWAPPER_CTRL_TXD_R_SE s2BIT(19) +-#define SWAPPER_CTRL_TXD_W_FE s2BIT(20) +-#define SWAPPER_CTRL_TXD_W_SE s2BIT(21) +-#define SWAPPER_CTRL_TXF_R_FE s2BIT(22) +-#define SWAPPER_CTRL_TXF_R_SE s2BIT(23) +-#define SWAPPER_CTRL_RXD_R_FE s2BIT(32) +-#define SWAPPER_CTRL_RXD_R_SE s2BIT(33) +-#define SWAPPER_CTRL_RXD_W_FE s2BIT(34) +-#define SWAPPER_CTRL_RXD_W_SE s2BIT(35) +-#define SWAPPER_CTRL_RXF_W_FE s2BIT(36) +-#define SWAPPER_CTRL_RXF_W_SE s2BIT(37) +-#define SWAPPER_CTRL_XMSI_FE s2BIT(40) +-#define SWAPPER_CTRL_XMSI_SE s2BIT(41) +-#define SWAPPER_CTRL_STATS_FE s2BIT(48) +-#define SWAPPER_CTRL_STATS_SE s2BIT(49) ++#define SWAPPER_CTRL_PIF_R_FE S2BIT(0) ++#define SWAPPER_CTRL_PIF_R_SE S2BIT(1) ++#define SWAPPER_CTRL_PIF_W_FE S2BIT(8) ++#define SWAPPER_CTRL_PIF_W_SE S2BIT(9) ++#define SWAPPER_CTRL_TXP_FE S2BIT(16) ++#define SWAPPER_CTRL_TXP_SE S2BIT(17) ++#define SWAPPER_CTRL_TXD_R_FE S2BIT(18) ++#define SWAPPER_CTRL_TXD_R_SE S2BIT(19) ++#define SWAPPER_CTRL_TXD_W_FE S2BIT(20) ++#define SWAPPER_CTRL_TXD_W_SE S2BIT(21) ++#define SWAPPER_CTRL_TXF_R_FE S2BIT(22) ++#define SWAPPER_CTRL_TXF_R_SE S2BIT(23) ++#define SWAPPER_CTRL_RXD_R_FE S2BIT(32) ++#define SWAPPER_CTRL_RXD_R_SE S2BIT(33) ++#define SWAPPER_CTRL_RXD_W_FE S2BIT(34) ++#define SWAPPER_CTRL_RXD_W_SE S2BIT(35) ++#define SWAPPER_CTRL_RXF_W_FE S2BIT(36) ++#define SWAPPER_CTRL_RXF_W_SE S2BIT(37) ++#define SWAPPER_CTRL_XMSI_FE S2BIT(40) ++#define SWAPPER_CTRL_XMSI_SE S2BIT(41) ++#define SWAPPER_CTRL_STATS_FE S2BIT(48) ++#define SWAPPER_CTRL_STATS_SE S2BIT(49) + + u64 pif_rd_swapper_fb; +-#define IF_RD_SWAPPER_FB 0x0123456789ABCDEF ++#define IF_RD_SWAPPER_FB 0x0123456789ABCDEF + + u64 scheduled_int_ctrl; +-#define SCHED_INT_CTRL_TIMER_EN s2BIT(0) +-#define SCHED_INT_CTRL_ONE_SHOT s2BIT(1) +-#define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) +-#define SCHED_INT_PERIOD TBD ++#define SCHED_INT_CTRL_TIMER_EN S2BIT(0) ++#define SCHED_INT_CTRL_ONE_SHOT S2BIT(1) ++#define SCHED_INT_CTRL_INT2MSI(val) vBIT(val, 10, 6) ++#define SCHED_INT_PERIOD TBD + + u64 txreqtimeout; +-#define TXREQTO_VAL(val) vBIT(val,0,32) +-#define TXREQTO_EN s2BIT(63) ++#define TXREQTO_VAL(val) vBIT(val, 0, 32) ++#define TXREQTO_EN S2BIT(63) + + u64 statsreqtimeout; +-#define STATREQTO_VAL(n) TBD +-#define STATREQTO_EN s2BIT(63) ++#define STATREQTO_VAL(n) TBD ++#define STATREQTO_EN S2BIT(63) + + u64 read_retry_delay; + u64 read_retry_acceleration; +@@ -251,141 +251,148 @@ + #define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8) + + u64 xmsi_mask_reg; ++#define DISABLE_MSI_RX(val, ring) vBIT(val, (ring + 1), 1) ++#define ENABLE_MSI_RX(val, ring) vBIT(val, (ring + 1), 1) + u64 stat_byte_cnt; +-#define STAT_BC(n) vBIT(n,4,12) ++#define STAT_BC(n) vBIT(n, 4, 12) + + /* Automated statistics collection */ + u64 stat_cfg; +-#define STAT_CFG_STAT_EN s2BIT(0) +-#define STAT_CFG_ONE_SHOT_EN s2BIT(1) +-#define STAT_CFG_STAT_NS_EN s2BIT(8) +-#define STAT_CFG_STAT_RO s2BIT(9) +-#define STAT_TRSF_PER(n) TBD +-#define PER_SEC 0x208d5 +-#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32) +-#define SET_UPDT_CLICKS(val) vBIT(val, 32, 32) ++#define STAT_CFG_STAT_EN S2BIT(0) ++#define STAT_CFG_ONE_SHOT_EN S2BIT(1) ++#define STAT_CFG_STAT_NS_EN S2BIT(8) ++#define STAT_CFG_STAT_RO S2BIT(9) ++#define STAT_TRSF_PER(n) TBD ++#define PER_SEC 0x208d5 ++#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n), 32, 32) ++#define SET_UPDT_CLICKS(val) vBIT(val, 32, 32) + + u64 stat_addr; + + /* General Configuration */ + u64 mdio_control; +-#define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16) +-#define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5) +-#define MDIO_MMD_PMA_DEV_ADDR 0x1 +-#define MDIO_MMD_PMD_DEV_ADDR 0x1 +-#define MDIO_MMD_WIS_DEV_ADDR 0x2 +-#define MDIO_MMD_PCS_DEV_ADDR 0x3 +-#define MDIO_MMD_PHYXS_DEV_ADDR 0x4 +-#define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5) +-#define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4) +-#define MDIO_OP(val) vBIT(val, 60, 2) +-#define MDIO_OP_ADDR_TRANS 0x0 +-#define MDIO_OP_WRITE_TRANS 0x1 +-#define MDIO_OP_READ_POST_INC_TRANS 0x2 +-#define MDIO_OP_READ_TRANS 0x3 +-#define MDIO_MDIO_DATA(val) vBIT(val, 32, 16) ++#define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16) ++#define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5) ++#define MDIO_MMD_PMA_DEV_ADDR 0x1 ++#define MDIO_MMD_PMD_DEV_ADDR 0x1 ++#define MDIO_MMD_WIS_DEV_ADDR 0x2 ++#define MDIO_MMD_PCS_DEV_ADDR 0x3 ++#define MDIO_MMD_PHYXS_DEV_ADDR 0x4 ++#define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5) ++#define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4) ++#define MDIO_OP(val) vBIT(val, 60, 2) ++#define MDIO_OP_ADDR_TRANS 0x0 ++#define MDIO_OP_WRITE_TRANS 0x1 ++#define MDIO_OP_READ_POST_INC_TRANS 0x2 ++#define MDIO_OP_READ_TRANS 0x3 ++#define MDIO_MDIO_DATA(val) vBIT(val, 32, 16) + + u64 dtx_control; + + u64 i2c_control; +-#define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) +-#define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) +-#define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) +-#define I2C_CONTROL_READ s2BIT(24) +-#define I2C_CONTROL_NACK s2BIT(25) +-#define I2C_CONTROL_CNTL_START vBIT(0xE,28,4) +-#define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) +-#define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) +-#define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) ++#define I2C_CONTROL_DEV_ID(id) vBIT(id, 1, 3) ++#define I2C_CONTROL_ADDR(addr) vBIT(addr, 5, 11) ++#define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt, 22, 2) ++#define I2C_CONTROL_READ S2BIT(24) ++#define I2C_CONTROL_NACK S2BIT(25) ++#define I2C_CONTROL_CNTL_START vBIT(0xE, 28, 4) ++#define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1, 28, 4)) ++#define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) ++#define I2C_CONTROL_SET_DATA(val) vBIT(val, 32, 32) + + u64 gpio_control; +-#define GPIO_CTRL_GPIO_0 s2BIT(8) ++#define GPIO_CTRL_GPIO_0 S2BIT(8) + u64 misc_control; +-#define FAULT_BEHAVIOUR s2BIT(0) +-#define EXT_REQ_EN s2BIT(1) +-#define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3) +- ++#define FAULT_BEHAVIOUR S2BIT(0) ++#define EXT_REQ_EN S2BIT(1) ++#define MISC_LINK_STABILITY_PRD(val) vBIT(val, 29, 3) + u8 unused7_1[0x230 - 0x208]; + + u64 pic_control2; + u64 ini_dperr_ctrl; + + u64 wreq_split_mask; +-#define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12) ++#define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12) + +- u8 unused7_2[0x800 - 0x248]; ++ u8 unused7_2[0x318 - 0x248]; ++ ++ u64 spdm_bir_offset; ++ u64 spdm_overwrite; ++ ++ u8 unused7_3[0x368 - 0x328]; ++ u64 spdm_structure; ++ u8 unused7_4[0x800 - 0x370]; + + /* TxDMA registers */ + u64 txdma_int_status; + u64 txdma_int_mask; +-#define TXDMA_PFC_INT s2BIT(0) +-#define TXDMA_TDA_INT s2BIT(1) +-#define TXDMA_PCC_INT s2BIT(2) +-#define TXDMA_TTI_INT s2BIT(3) +-#define TXDMA_LSO_INT s2BIT(4) +-#define TXDMA_TPA_INT s2BIT(5) +-#define TXDMA_SM_INT s2BIT(6) ++#define TXDMA_PFC_INT S2BIT(0) ++#define TXDMA_TDA_INT S2BIT(1) ++#define TXDMA_PCC_INT S2BIT(2) ++#define TXDMA_TTI_INT S2BIT(3) ++#define TXDMA_LSO_INT S2BIT(4) ++#define TXDMA_TPA_INT S2BIT(5) ++#define TXDMA_SM_INT S2BIT(6) + u64 pfc_err_reg; +-#define PFC_ECC_SG_ERR s2BIT(7) +-#define PFC_ECC_DB_ERR s2BIT(15) +-#define PFC_SM_ERR_ALARM s2BIT(23) +-#define PFC_MISC_0_ERR s2BIT(31) +-#define PFC_MISC_1_ERR s2BIT(32) +-#define PFC_PCIX_ERR s2BIT(39) ++#define PFC_ECC_SG_ERR S2BIT(7) ++#define PFC_ECC_DB_ERR S2BIT(15) ++#define PFC_SM_ERR_ALARM S2BIT(23) ++#define PFC_MISC_0_ERR S2BIT(31) ++#define PFC_MISC_1_ERR S2BIT(32) ++#define PFC_PCIX_ERR S2BIT(39) + u64 pfc_err_mask; + u64 pfc_err_alarm; + + u64 tda_err_reg; +-#define TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8) +-#define TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8) +-#define TDA_SM0_ERR_ALARM s2BIT(22) +-#define TDA_SM1_ERR_ALARM s2BIT(23) +-#define TDA_PCIX_ERR s2BIT(39) ++#define TDA_Fn_ECC_SG_ERR vBIT(0xff, 0, 8) ++#define TDA_Fn_ECC_DB_ERR vBIT(0xff, 8, 8) ++#define TDA_SM0_ERR_ALARM S2BIT(22) ++#define TDA_SM1_ERR_ALARM S2BIT(23) ++#define TDA_PCIX_ERR S2BIT(39) + u64 tda_err_mask; + u64 tda_err_alarm; + + u64 pcc_err_reg; +-#define PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8) +-#define PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8) +-#define PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8) +-#define PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8) +-#define PCC_SM_ERR_ALARM vBIT(0xff,32,8) +-#define PCC_WR_ERR_ALARM vBIT(0xff,40,8) +-#define PCC_N_SERR vBIT(0xff,48,8) +-#define PCC_6_COF_OV_ERR s2BIT(56) +-#define PCC_7_COF_OV_ERR s2BIT(57) +-#define PCC_6_LSO_OV_ERR s2BIT(58) +-#define PCC_7_LSO_OV_ERR s2BIT(59) +-#define PCC_ENABLE_FOUR vBIT(0x0F,0,8) ++#define PCC_FB_ECC_SG_ERR vBIT(0xFF, 0, 8) ++#define PCC_TXB_ECC_SG_ERR vBIT(0xFF, 8, 8) ++#define PCC_FB_ECC_DB_ERR vBIT(0xFF, 16, 8) ++#define PCC_TXB_ECC_DB_ERR vBIT(0xff, 24, 8) ++#define PCC_SM_ERR_ALARM vBIT(0xff, 32, 8) ++#define PCC_WR_ERR_ALARM vBIT(0xff, 40, 8) ++#define PCC_N_SERR vBIT(0xff, 48, 8) ++#define PCC_6_COF_OV_ERR S2BIT(56) ++#define PCC_7_COF_OV_ERR S2BIT(57) ++#define PCC_6_LSO_OV_ERR S2BIT(58) ++#define PCC_7_LSO_OV_ERR S2BIT(59) ++#define PCC_ENABLE_FOUR vBIT(0x0F, 0, 8) + u64 pcc_err_mask; + u64 pcc_err_alarm; + + u64 tti_err_reg; +-#define TTI_ECC_SG_ERR s2BIT(7) +-#define TTI_ECC_DB_ERR s2BIT(15) +-#define TTI_SM_ERR_ALARM s2BIT(23) ++#define TTI_ECC_SG_ERR S2BIT(7) ++#define TTI_ECC_DB_ERR S2BIT(15) ++#define TTI_SM_ERR_ALARM S2BIT(23) + u64 tti_err_mask; + u64 tti_err_alarm; + + u64 lso_err_reg; +-#define LSO6_SEND_OFLOW s2BIT(12) +-#define LSO7_SEND_OFLOW s2BIT(13) +-#define LSO6_ABORT s2BIT(14) +-#define LSO7_ABORT s2BIT(15) +-#define LSO6_SM_ERR_ALARM s2BIT(22) +-#define LSO7_SM_ERR_ALARM s2BIT(23) ++#define LSO6_SEND_OFLOW S2BIT(12) ++#define LSO7_SEND_OFLOW S2BIT(13) ++#define LSO6_ABORT S2BIT(14) ++#define LSO7_ABORT S2BIT(15) ++#define LSO6_SM_ERR_ALARM S2BIT(22) ++#define LSO7_SM_ERR_ALARM S2BIT(23) + u64 lso_err_mask; + u64 lso_err_alarm; + + u64 tpa_err_reg; +-#define TPA_TX_FRM_DROP s2BIT(7) +-#define TPA_SM_ERR_ALARM s2BIT(23) +- ++#define TPA_TX_FRM_DROP S2BIT(7) ++#define TPA_SM_ERR_ALARM S2BIT(23) + u64 tpa_err_mask; + u64 tpa_err_alarm; + + u64 sm_err_reg; +-#define SM_SM_ERR_ALARM s2BIT(15) ++#define SM_SM_ERR_ALARM S2BIT(15) + u64 sm_err_mask; + u64 sm_err_alarm; + +@@ -395,41 +402,41 @@ + u64 tx_dma_wrap_stat; + + /* Tx FIFO controller */ +-#define X_MAX_FIFOS 8 +-#define X_FIFO_MAX_LEN 0x1FFF /*8191 */ ++#define X_MAX_FIFOS 8 ++#define X_FIFO_MAX_LEN 0x1FFF /*8191 */ + u64 tx_fifo_partition_0; +-#define TX_FIFO_PARTITION_EN s2BIT(0) +-#define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) +-#define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13) +-#define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3) +-#define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 ) ++#define TX_FIFO_PARTITION_EN S2BIT(0) ++#define TX_FIFO_PARTITION_0_PRI(val) vBIT(val, 5, 3) ++#define TX_FIFO_PARTITION_0_LEN(val) vBIT(val, 19, 13) ++#define TX_FIFO_PARTITION_1_PRI(val) vBIT(val, 37, 3) ++#define TX_FIFO_PARTITION_1_LEN(val) vBIT(val, 51, 13) + + u64 tx_fifo_partition_1; +-#define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3) +-#define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13) +-#define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3) +-#define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13) ++#define TX_FIFO_PARTITION_2_PRI(val) vBIT(val, 5, 3) ++#define TX_FIFO_PARTITION_2_LEN(val) vBIT(val, 19, 13) ++#define TX_FIFO_PARTITION_3_PRI(val) vBIT(val, 37, 3) ++#define TX_FIFO_PARTITION_3_LEN(val) vBIT(val, 51, 13) + + u64 tx_fifo_partition_2; +-#define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3) +-#define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13) +-#define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3) +-#define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13) ++#define TX_FIFO_PARTITION_4_PRI(val) vBIT(val, 5, 3) ++#define TX_FIFO_PARTITION_4_LEN(val) vBIT(val, 19, 13) ++#define TX_FIFO_PARTITION_5_PRI(val) vBIT(val, 37, 3) ++#define TX_FIFO_PARTITION_5_LEN(val) vBIT(val, 51, 13) + + u64 tx_fifo_partition_3; +-#define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3) +-#define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13) +-#define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3) +-#define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13) ++#define TX_FIFO_PARTITION_6_PRI(val) vBIT(val, 5, 3) ++#define TX_FIFO_PARTITION_6_LEN(val) vBIT(val, 19, 13) ++#define TX_FIFO_PARTITION_7_PRI(val) vBIT(val, 37, 3) ++#define TX_FIFO_PARTITION_7_LEN(val) vBIT(val, 51, 13) + +-#define TX_FIFO_PARTITION_PRI_0 0 /* highest */ +-#define TX_FIFO_PARTITION_PRI_1 1 +-#define TX_FIFO_PARTITION_PRI_2 2 +-#define TX_FIFO_PARTITION_PRI_3 3 +-#define TX_FIFO_PARTITION_PRI_4 4 +-#define TX_FIFO_PARTITION_PRI_5 5 +-#define TX_FIFO_PARTITION_PRI_6 6 +-#define TX_FIFO_PARTITION_PRI_7 7 /* lowest */ ++#define TX_FIFO_PARTITION_PRI_0 0 /* highest */ ++#define TX_FIFO_PARTITION_PRI_1 1 ++#define TX_FIFO_PARTITION_PRI_2 2 ++#define TX_FIFO_PARTITION_PRI_3 3 ++#define TX_FIFO_PARTITION_PRI_4 4 ++#define TX_FIFO_PARTITION_PRI_5 5 ++#define TX_FIFO_PARTITION_PRI_6 6 ++#define TX_FIFO_PARTITION_PRI_7 7 /* lowest */ + + u64 tx_w_round_robin_0; + u64 tx_w_round_robin_1; +@@ -438,33 +445,32 @@ + u64 tx_w_round_robin_4; + + u64 tti_command_mem; +-#define TTI_CMD_MEM_WE s2BIT(7) +-#define TTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15) +-#define TTI_CMD_MEM_STROBE_BEING_EXECUTED s2BIT(15) +-#define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) ++#define TTI_CMD_MEM_WE S2BIT(7) ++#define TTI_CMD_MEM_STROBE_NEW_CMD S2BIT(15) ++#define TTI_CMD_MEM_STROBE_BEING_EXECUTED S2BIT(15) ++#define TTI_CMD_MEM_OFFSET(n) vBIT(n, 26, 6) + + u64 tti_data1_mem; +-#define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26) +-#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2) +-#define TTI_DATA1_MEM_TX_TIMER_AC_EN s2BIT(38) +-#define TTI_DATA1_MEM_TX_TIMER_CI_EN s2BIT(39) +-#define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7) +-#define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7) +-#define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) ++#define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n, 6, 26) ++#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n, 38, 2) ++#define TTI_DATA1_MEM_TX_TIMER_AC_EN S2BIT(38) ++#define TTI_DATA1_MEM_TX_TIMER_CI_EN S2BIT(39) ++#define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n, 41, 7) ++#define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n, 49, 7) ++#define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n, 57, 7) + + u64 tti_data2_mem; +-#define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16) +-#define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16) +-#define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16) +-#define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16) ++#define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n, 0, 16) ++#define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n, 16, 16) ++#define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n, 32, 16) ++#define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n, 48, 16) + + /* Tx Protocol assist */ + u64 tx_pa_cfg; +-#define TX_PA_CFG_IGNORE_FRM_ERR s2BIT(1) +-#define TX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2) +-#define TX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3) +-#define TX_PA_CFG_IGNORE_L2_ERR s2BIT(6) +-#define RX_PA_CFG_STRIP_VLAN_TAG s2BIT(15) ++#define TX_PA_CFG_IGNORE_FRM_ERR S2BIT(1) ++#define TX_PA_CFG_IGNORE_SNAP_OUI S2BIT(2) ++#define TX_PA_CFG_IGNORE_LLC_CTRL S2BIT(3) ++#define TX_PA_CFG_IGNORE_L2_ERR S2BIT(6) + + /* Recent add, used only debug purposes. */ + u64 pcc_enable; +@@ -478,58 +484,58 @@ + /* RxDMA Registers */ + u64 rxdma_int_status; + u64 rxdma_int_mask; +-#define RXDMA_INT_RC_INT_M s2BIT(0) +-#define RXDMA_INT_RPA_INT_M s2BIT(1) +-#define RXDMA_INT_RDA_INT_M s2BIT(2) +-#define RXDMA_INT_RTI_INT_M s2BIT(3) ++#define RXDMA_INT_RC_INT_M S2BIT(0) ++#define RXDMA_INT_RPA_INT_M S2BIT(1) ++#define RXDMA_INT_RDA_INT_M S2BIT(2) ++#define RXDMA_INT_RTI_INT_M S2BIT(3) + + u64 rda_err_reg; +-#define RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8) +-#define RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8) +-#define RDA_FRM_ECC_SG_ERR s2BIT(23) +-#define RDA_FRM_ECC_DB_N_AERR s2BIT(31) +-#define RDA_SM1_ERR_ALARM s2BIT(38) +-#define RDA_SM0_ERR_ALARM s2BIT(39) +-#define RDA_MISC_ERR s2BIT(47) +-#define RDA_PCIX_ERR s2BIT(55) +-#define RDA_RXD_ECC_DB_SERR s2BIT(63) ++#define RDA_RXDn_ECC_SG_ERR vBIT(0xFF, 0, 8) ++#define RDA_RXDn_ECC_DB_ERR vBIT(0xFF, 8, 8) ++#define RDA_FRM_ECC_SG_ERR S2BIT(23) ++#define RDA_FRM_ECC_DB_N_AERR S2BIT(31) ++#define RDA_SM1_ERR_ALARM S2BIT(38) ++#define RDA_SM0_ERR_ALARM S2BIT(39) ++#define RDA_MISC_ERR S2BIT(47) ++#define RDA_PCIX_ERR S2BIT(55) ++#define RDA_RXD_ECC_DB_SERR S2BIT(63) + u64 rda_err_mask; + u64 rda_err_alarm; + + u64 rc_err_reg; +-#define RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8) +-#define RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8) +-#define RC_FTC_ECC_SG_ERR s2BIT(23) +-#define RC_FTC_ECC_DB_ERR s2BIT(31) +-#define RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8) +-#define RC_FTC_SM_ERR_ALARM s2BIT(47) +-#define RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8) ++#define RC_PRCn_ECC_SG_ERR vBIT(0xFF, 0, 8) ++#define RC_PRCn_ECC_DB_ERR vBIT(0xFF, 8, 8) ++#define RC_FTC_ECC_SG_ERR S2BIT(23) ++#define RC_FTC_ECC_DB_ERR S2BIT(31) ++#define RC_PRCn_SM_ERR_ALARM vBIT(0xFF, 32, 8) ++#define RC_FTC_SM_ERR_ALARM S2BIT(47) ++#define RC_RDA_FAIL_WR_Rn vBIT(0xFF, 48, 8) + u64 rc_err_mask; + u64 rc_err_alarm; + + u64 prc_pcix_err_reg; +-#define PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8) +-#define PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8) +-#define PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8) +-#define PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8) +-#define PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8) +-#define PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8) ++#define PRC_PCI_AB_RD_Rn vBIT(0xFF, 0, 8) ++#define PRC_PCI_DP_RD_Rn vBIT(0xFF, 8, 8) ++#define PRC_PCI_AB_WR_Rn vBIT(0xFF, 16, 8) ++#define PRC_PCI_DP_WR_Rn vBIT(0xFF, 24, 8) ++#define PRC_PCI_AB_F_WR_Rn vBIT(0xFF, 32, 8) ++#define PRC_PCI_DP_F_WR_Rn vBIT(0xFF, 40, 8) + u64 prc_pcix_err_mask; + u64 prc_pcix_err_alarm; + + u64 rpa_err_reg; +-#define RPA_ECC_SG_ERR s2BIT(7) +-#define RPA_ECC_DB_ERR s2BIT(15) +-#define RPA_FLUSH_REQUEST s2BIT(22) +-#define RPA_SM_ERR_ALARM s2BIT(23) +-#define RPA_CREDIT_ERR s2BIT(31) ++#define RPA_ECC_SG_ERR S2BIT(7) ++#define RPA_ECC_DB_ERR S2BIT(15) ++#define RPA_FLUSH_REQUEST S2BIT(22) ++#define RPA_SM_ERR_ALARM S2BIT(23) ++#define RPA_CREDIT_ERR S2BIT(31) + u64 rpa_err_mask; + u64 rpa_err_alarm; + + u64 rti_err_reg; +-#define RTI_ECC_SG_ERR s2BIT(7) +-#define RTI_ECC_DB_ERR s2BIT(15) +-#define RTI_SM_ERR_ALARM s2BIT(23) ++#define RTI_ECC_SG_ERR S2BIT(7) ++#define RTI_ECC_DB_ERR S2BIT(15) ++#define RTI_SM_ERR_ALARM S2BIT(23) + u64 rti_err_mask; + u64 rti_err_alarm; + +@@ -537,23 +543,23 @@ + + /* DMA arbiter */ + u64 rx_queue_priority; +-#define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3) +-#define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3) +-#define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3) +-#define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3) +-#define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3) +-#define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3) +-#define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3) +-#define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3) ++#define RX_QUEUE_0_PRIORITY(val) vBIT(val, 5, 3) ++#define RX_QUEUE_1_PRIORITY(val) vBIT(val, 13, 3) ++#define RX_QUEUE_2_PRIORITY(val) vBIT(val, 21, 3) ++#define RX_QUEUE_3_PRIORITY(val) vBIT(val, 29, 3) ++#define RX_QUEUE_4_PRIORITY(val) vBIT(val, 37, 3) ++#define RX_QUEUE_5_PRIORITY(val) vBIT(val, 45, 3) ++#define RX_QUEUE_6_PRIORITY(val) vBIT(val, 53, 3) ++#define RX_QUEUE_7_PRIORITY(val) vBIT(val, 61, 3) + +-#define RX_QUEUE_PRI_0 0 /* highest */ +-#define RX_QUEUE_PRI_1 1 +-#define RX_QUEUE_PRI_2 2 +-#define RX_QUEUE_PRI_3 3 +-#define RX_QUEUE_PRI_4 4 +-#define RX_QUEUE_PRI_5 5 +-#define RX_QUEUE_PRI_6 6 +-#define RX_QUEUE_PRI_7 7 /* lowest */ ++#define RX_QUEUE_PRI_0 0 /* highest */ ++#define RX_QUEUE_PRI_1 1 ++#define RX_QUEUE_PRI_2 2 ++#define RX_QUEUE_PRI_3 3 ++#define RX_QUEUE_PRI_4 4 ++#define RX_QUEUE_PRI_5 5 ++#define RX_QUEUE_PRI_6 6 ++#define RX_QUEUE_PRI_7 7 /* lowest */ + + u64 rx_w_round_robin_0; + u64 rx_w_round_robin_1; +@@ -562,71 +568,74 @@ + u64 rx_w_round_robin_4; + + /* Per-ring controller regs */ +-#define RX_MAX_RINGS 8 ++#define RX_MAX_RINGS 8 + #if 0 +-#define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */ +-#define RX_MIN_RINGS_SZ 0x3F /* 63 */ ++#define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */ ++#define RX_MIN_RINGS_SZ 0x3F /* 63 */ + #endif + u64 prc_rxd0_n[RX_MAX_RINGS]; + u64 prc_ctrl_n[RX_MAX_RINGS]; +-#define PRC_CTRL_RC_ENABLED s2BIT(7) +-#define PRC_CTRL_RING_MODE (s2BIT(14)|s2BIT(15)) +-#define PRC_CTRL_RING_MODE_1 vBIT(0,14,2) +-#define PRC_CTRL_RING_MODE_3 vBIT(1,14,2) +-#define PRC_CTRL_RING_MODE_5 vBIT(2,14,2) +-#define PRC_CTRL_RING_MODE_x vBIT(3,14,2) +-#define PRC_CTRL_NO_SNOOP (s2BIT(22)|s2BIT(23)) +-#define PRC_CTRL_NO_SNOOP_DESC s2BIT(22) +-#define PRC_CTRL_NO_SNOOP_BUFF s2BIT(23) +-#define PRC_CTRL_BIMODAL_INTERRUPT s2BIT(37) +-#define PRC_CTRL_GROUP_READS s2BIT(38) +-#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) ++#define PRC_CTRL_RC_ENABLED S2BIT(7) ++#define PRC_CTRL_RING_MODE (S2BIT(14)|S2BIT(15)) ++#define PRC_CTRL_RING_MODE_1 vBIT(0, 14, 2) ++#define PRC_CTRL_RING_MODE_3 vBIT(1, 14, 2) ++#define PRC_CTRL_RING_MODE_5 vBIT(2, 14, 2) ++#define PRC_CTRL_RING_MODE_x vBIT(3, 14, 2) ++#define PRC_CTRL_NO_SNOOP (S2BIT(22)|S2BIT(23)) ++#define PRC_CTRL_NO_SNOOP_DESC S2BIT(22) ++#define PRC_CTRL_NO_SNOOP_BUFF S2BIT(23) ++#define PRC_CTRL_RTH_DISABLE S2BIT(31) ++#define PRC_CTRL_BIMODAL_INTERRUPT S2BIT(37) ++#define PRC_CTRL_GROUP_READS S2BIT(38) ++#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val, 40, 24) + + u64 prc_alarm_action; +-#define PRC_ALARM_ACTION_RR_R0_STOP s2BIT(3) +-#define PRC_ALARM_ACTION_RW_R0_STOP s2BIT(7) +-#define PRC_ALARM_ACTION_RR_R1_STOP s2BIT(11) +-#define PRC_ALARM_ACTION_RW_R1_STOP s2BIT(15) +-#define PRC_ALARM_ACTION_RR_R2_STOP s2BIT(19) +-#define PRC_ALARM_ACTION_RW_R2_STOP s2BIT(23) +-#define PRC_ALARM_ACTION_RR_R3_STOP s2BIT(27) +-#define PRC_ALARM_ACTION_RW_R3_STOP s2BIT(31) +-#define PRC_ALARM_ACTION_RR_R4_STOP s2BIT(35) +-#define PRC_ALARM_ACTION_RW_R4_STOP s2BIT(39) +-#define PRC_ALARM_ACTION_RR_R5_STOP s2BIT(43) +-#define PRC_ALARM_ACTION_RW_R5_STOP s2BIT(47) +-#define PRC_ALARM_ACTION_RR_R6_STOP s2BIT(51) +-#define PRC_ALARM_ACTION_RW_R6_STOP s2BIT(55) +-#define PRC_ALARM_ACTION_RR_R7_STOP s2BIT(59) +-#define PRC_ALARM_ACTION_RW_R7_STOP s2BIT(63) ++#define PRC_ALARM_ACTION_RR_R0_STOP S2BIT(3) ++#define PRC_ALARM_ACTION_RW_R0_STOP S2BIT(7) ++#define PRC_ALARM_ACTION_RR_R1_STOP S2BIT(11) ++#define PRC_ALARM_ACTION_RW_R1_STOP S2BIT(15) ++#define PRC_ALARM_ACTION_RR_R2_STOP S2BIT(19) ++#define PRC_ALARM_ACTION_RW_R2_STOP S2BIT(23) ++#define PRC_ALARM_ACTION_RR_R3_STOP S2BIT(27) ++#define PRC_ALARM_ACTION_RW_R3_STOP S2BIT(31) ++#define PRC_ALARM_ACTION_RR_R4_STOP S2BIT(35) ++#define PRC_ALARM_ACTION_RW_R4_STOP S2BIT(39) ++#define PRC_ALARM_ACTION_RR_R5_STOP S2BIT(43) ++#define PRC_ALARM_ACTION_RW_R5_STOP S2BIT(47) ++#define PRC_ALARM_ACTION_RR_R6_STOP S2BIT(51) ++#define PRC_ALARM_ACTION_RW_R6_STOP S2BIT(55) ++#define PRC_ALARM_ACTION_RR_R7_STOP S2BIT(59) ++#define PRC_ALARM_ACTION_RW_R7_STOP S2BIT(63) + + /* Receive traffic interrupts */ + u64 rti_command_mem; +-#define RTI_CMD_MEM_WE s2BIT(7) +-#define RTI_CMD_MEM_STROBE s2BIT(15) +-#define RTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15) +-#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED s2BIT(15) +-#define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) ++#define RTI_CMD_MEM_WE S2BIT(7) ++#define RTI_CMD_MEM_STROBE S2BIT(15) ++#define RTI_CMD_MEM_STROBE_NEW_CMD S2BIT(15) ++#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED S2BIT(15) ++#define RTI_CMD_MEM_OFFSET(n) vBIT(n, 29, 3) + + u64 rti_data1_mem; +-#define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29) +-#define RTI_DATA1_MEM_RX_TIMER_AC_EN s2BIT(38) +-#define RTI_DATA1_MEM_RX_TIMER_CI_EN s2BIT(39) +-#define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7) +-#define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7) +-#define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) ++#define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n, 3, 29) ++#define RTI_DATA1_MEM_RX_TIMER_AC_EN S2BIT(38) ++#define RTI_DATA1_MEM_RX_TIMER_CI_EN S2BIT(39) ++#define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n, 41, 7) ++#define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n, 49, 7) ++#define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n, 57, 7) + + u64 rti_data2_mem; +-#define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16) +-#define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16) +-#define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16) +-#define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) ++#define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n, 0, 16) ++#define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n, 16, 16) ++#define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n, 32, 16) ++#define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n, 48, 16) + + u64 rx_pa_cfg; +-#define RX_PA_CFG_IGNORE_FRM_ERR s2BIT(1) +-#define RX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2) +-#define RX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3) +-#define RX_PA_CFG_IGNORE_L2_ERR s2BIT(6) ++#define RX_PA_CFG_IGNORE_FRM_ERR S2BIT(1) ++#define RX_PA_CFG_IGNORE_SNAP_OUI S2BIT(2) ++#define RX_PA_CFG_IGNORE_LLC_CTRL S2BIT(3) ++#define RX_PA_CFG_IGNORE_L2_ERR S2BIT(6) ++#define RX_PA_CFG_STRIP_VLAN_TAG S2BIT(15) ++#define RX_PA_CFG_UDP_ZERO_CS_EN S2BIT(31) + + u64 unused_11_1; + +@@ -642,130 +651,132 @@ + /* Media Access Controller Register */ + u64 mac_int_status; + u64 mac_int_mask; +-#define MAC_INT_STATUS_TMAC_INT s2BIT(0) +-#define MAC_INT_STATUS_RMAC_INT s2BIT(1) ++#define MAC_INT_STATUS_TMAC_INT S2BIT(0) ++#define MAC_INT_STATUS_RMAC_INT S2BIT(1) + + u64 mac_tmac_err_reg; +-#define TMAC_ECC_SG_ERR s2BIT(7) +-#define TMAC_ECC_DB_ERR s2BIT(15) +-#define TMAC_TX_BUF_OVRN s2BIT(23) +-#define TMAC_TX_CRI_ERR s2BIT(31) +-#define TMAC_TX_SM_ERR s2BIT(39) +-#define TMAC_DESC_ECC_SG_ERR s2BIT(47) +-#define TMAC_DESC_ECC_DB_ERR s2BIT(55) +- ++#define TMAC_ECC_SG_ERR S2BIT(7) ++#define TMAC_ECC_DB_ERR S2BIT(15) ++#define TMAC_TX_BUF_OVRN S2BIT(23) ++#define TMAC_TX_CRI_ERR S2BIT(31) ++#define TMAC_TX_SM_ERR S2BIT(39) ++#define TMAC_DESC_ECC_SG_ERR S2BIT(47) ++#define TMAC_DESC_ECC_DB_ERR S2BIT(55) + u64 mac_tmac_err_mask; + u64 mac_tmac_err_alarm; + + u64 mac_rmac_err_reg; +-#define RMAC_RX_BUFF_OVRN s2BIT(0) +-#define RMAC_FRM_RCVD_INT s2BIT(1) +-#define RMAC_UNUSED_INT s2BIT(2) +-#define RMAC_RTS_PNUM_ECC_SG_ERR s2BIT(5) +-#define RMAC_RTS_DS_ECC_SG_ERR s2BIT(6) +-#define RMAC_RD_BUF_ECC_SG_ERR s2BIT(7) +-#define RMAC_RTH_MAP_ECC_SG_ERR s2BIT(8) +-#define RMAC_RTH_SPDM_ECC_SG_ERR s2BIT(9) +-#define RMAC_RTS_VID_ECC_SG_ERR s2BIT(10) +-#define RMAC_DA_SHADOW_ECC_SG_ERR s2BIT(11) +-#define RMAC_RTS_PNUM_ECC_DB_ERR s2BIT(13) +-#define RMAC_RTS_DS_ECC_DB_ERR s2BIT(14) +-#define RMAC_RD_BUF_ECC_DB_ERR s2BIT(15) +-#define RMAC_RTH_MAP_ECC_DB_ERR s2BIT(16) +-#define RMAC_RTH_SPDM_ECC_DB_ERR s2BIT(17) +-#define RMAC_RTS_VID_ECC_DB_ERR s2BIT(18) +-#define RMAC_DA_SHADOW_ECC_DB_ERR s2BIT(19) +-#define RMAC_LINK_STATE_CHANGE_INT s2BIT(31) +-#define RMAC_RX_SM_ERR s2BIT(39) +-#define RMAC_SINGLE_ECC_ERR (s2BIT(5) | s2BIT(6) | s2BIT(7) |\ +- s2BIT(8) | s2BIT(9) | s2BIT(10)|\ +- s2BIT(11)) +-#define RMAC_DOUBLE_ECC_ERR (s2BIT(13) | s2BIT(14) | s2BIT(15) |\ +- s2BIT(16) | s2BIT(17) | s2BIT(18)|\ +- s2BIT(19)) ++#define RMAC_RX_BUFF_OVRN S2BIT(0) ++#define RMAC_FRM_RCVD_INT S2BIT(1) ++#define RMAC_UNUSED_INT S2BIT(2) ++#define RMAC_RTS_PNUM_ECC_SG_ERR S2BIT(5) ++#define RMAC_RTS_DS_ECC_SG_ERR S2BIT(6) ++#define RMAC_RD_BUF_ECC_SG_ERR S2BIT(7) ++#define RMAC_RTH_MAP_ECC_SG_ERR S2BIT(8) ++#define RMAC_RTH_SPDM_ECC_SG_ERR S2BIT(9) ++#define RMAC_RTS_VID_ECC_SG_ERR S2BIT(10) ++#define RMAC_DA_SHADOW_ECC_SG_ERR S2BIT(11) ++#define RMAC_RTS_PNUM_ECC_DB_ERR S2BIT(13) ++#define RMAC_RTS_DS_ECC_DB_ERR S2BIT(14) ++#define RMAC_RD_BUF_ECC_DB_ERR S2BIT(15) ++#define RMAC_RTH_MAP_ECC_DB_ERR S2BIT(16) ++#define RMAC_RTH_SPDM_ECC_DB_ERR S2BIT(17) ++#define RMAC_RTS_VID_ECC_DB_ERR S2BIT(18) ++#define RMAC_DA_SHADOW_ECC_DB_ERR S2BIT(19) ++#define RMAC_LINK_STATE_CHANGE_INT S2BIT(31) ++#define RMAC_RX_SM_ERR S2BIT(39) ++#define RMAC_SINGLE_ECC_ERR (S2BIT(5) | S2BIT(6) | \ ++ S2BIT(7) | S2BIT(8) | \ ++ S2BIT(9) | S2BIT(10) | \ ++ S2BIT(11)) ++#define RMAC_DOUBLE_ECC_ERR (S2BIT(13) | S2BIT(14) | \ ++ S2BIT(15) | S2BIT(16) | \ ++ S2BIT(17) | S2BIT(18) | \ ++ S2BIT(19)) ++ + u64 mac_rmac_err_mask; + u64 mac_rmac_err_alarm; + + u8 unused14[0x100 - 0x40]; + + u64 mac_cfg; +-#define MAC_CFG_TMAC_ENABLE s2BIT(0) +-#define MAC_CFG_RMAC_ENABLE s2BIT(1) +-#define MAC_CFG_LAN_NOT_WAN s2BIT(2) +-#define MAC_CFG_TMAC_LOOPBACK s2BIT(3) +-#define MAC_CFG_TMAC_APPEND_PAD s2BIT(4) +-#define MAC_CFG_RMAC_STRIP_FCS s2BIT(5) +-#define MAC_CFG_RMAC_STRIP_PAD s2BIT(6) +-#define MAC_CFG_RMAC_PROM_ENABLE s2BIT(7) +-#define MAC_RMAC_DISCARD_PFRM s2BIT(8) +-#define MAC_RMAC_BCAST_ENABLE s2BIT(9) +-#define MAC_RMAC_ALL_ADDR_ENABLE s2BIT(10) +-#define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) ++#define MAC_CFG_TMAC_ENABLE S2BIT(0) ++#define MAC_CFG_RMAC_ENABLE S2BIT(1) ++#define MAC_CFG_LAN_NOT_WAN S2BIT(2) ++#define MAC_CFG_TMAC_LOOPBACK S2BIT(3) ++#define MAC_CFG_TMAC_APPEND_PAD S2BIT(4) ++#define MAC_CFG_RMAC_STRIP_FCS S2BIT(5) ++#define MAC_CFG_RMAC_STRIP_PAD S2BIT(6) ++#define MAC_CFG_RMAC_PROM_ENABLE S2BIT(7) ++#define MAC_RMAC_DISCARD_PFRM S2BIT(8) ++#define MAC_RMAC_BCAST_ENABLE S2BIT(9) ++#define MAC_RMAC_ALL_ADDR_ENABLE S2BIT(10) ++#define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val, 16, 8) + + u64 tmac_avg_ipg; +-#define TMAC_AVG_IPG(val) vBIT(val,0,8) ++#define TMAC_AVG_IPG(val) vBIT(val, 0, 8) + + u64 rmac_max_pyld_len; +-#define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14) +-#define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14) +-#define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14) ++#define RMAC_MAX_PYLD_LEN(val) vBIT(val, 2, 14) ++#define RMAC_MAX_PYLD_LEN_DEF vBIT(1500, 2, 14) ++#define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600, 2, 14) + + u64 rmac_err_cfg; +-#define RMAC_ERR_FCS s2BIT(0) +-#define RMAC_ERR_FCS_ACCEPT s2BIT(1) +-#define RMAC_ERR_TOO_LONG s2BIT(1) +-#define RMAC_ERR_TOO_LONG_ACCEPT s2BIT(1) +-#define RMAC_ERR_RUNT s2BIT(2) +-#define RMAC_ERR_RUNT_ACCEPT s2BIT(2) +-#define RMAC_ERR_LEN_MISMATCH s2BIT(3) +-#define RMAC_ERR_LEN_MISMATCH_ACCEPT s2BIT(3) ++#define RMAC_ERR_FCS S2BIT(0) ++#define RMAC_ERR_FCS_ACCEPT S2BIT(1) ++#define RMAC_ERR_TOO_LONG S2BIT(1) ++#define RMAC_ERR_TOO_LONG_ACCEPT S2BIT(1) ++#define RMAC_ERR_RUNT S2BIT(2) ++#define RMAC_ERR_RUNT_ACCEPT S2BIT(2) ++#define RMAC_ERR_LEN_MISMATCH S2BIT(3) ++#define RMAC_ERR_LEN_MISMATCH_ACCEPT S2BIT(3) + + u64 rmac_cfg_key; +-#define RMAC_CFG_KEY(val) vBIT(val,0,16) ++#define RMAC_CFG_KEY(val) vBIT(val, 0, 16) + +-#define S2IO_MAC_ADDR_START_OFFSET 0 ++#define S2IO_MAC_ADDR_START_OFFSET 0 + +-#define S2IO_XENA_MAX_MC_ADDRESSES 64 /* multicast addresses */ +-#define S2IO_HERC_MAX_MC_ADDRESSES 256 ++#define S2IO_XENA_MAX_MC_ADDRESSES 64 /*multicast addresses*/ ++#define S2IO_HERC_MAX_MC_ADDRESSES 256 + +-#define S2IO_XENA_MAX_MAC_ADDRESSES 16 +-#define S2IO_HERC_MAX_MAC_ADDRESSES 64 ++#define S2IO_XENA_MAX_MAC_ADDRESSES 16 ++#define S2IO_HERC_MAX_MAC_ADDRESSES 64 + +-#define S2IO_XENA_MC_ADDR_START_OFFSET 16 +-#define S2IO_HERC_MC_ADDR_START_OFFSET 64 ++#define S2IO_XENA_MC_ADDR_START_OFFSET 16 ++#define S2IO_HERC_MC_ADDR_START_OFFSET 64 + + u64 rmac_addr_cmd_mem; +-#define RMAC_ADDR_CMD_MEM_WE s2BIT(7) +-#define RMAC_ADDR_CMD_MEM_RD 0 +-#define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD s2BIT(15) +-#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING s2BIT(15) +-#define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) ++#define RMAC_ADDR_CMD_MEM_WE S2BIT(7) ++#define RMAC_ADDR_CMD_MEM_RD 0 ++#define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD S2BIT(15) ++#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING S2BIT(15) ++#define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n, 26, 6) + + u64 rmac_addr_data0_mem; +-#define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48) +-#define RMAC_ADDR_DATA0_MEM_USER s2BIT(48) ++#define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n, 0, 48) ++#define RMAC_ADDR_DATA0_MEM_USER S2BIT(48) + + u64 rmac_addr_data1_mem; +-#define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) ++#define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n, 0, 48) + + u8 unused15[0x8]; + + /* +- u64 rmac_addr_cfg; +-#define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n) +-#define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n) +-#define RMAC_ADDR_BCAST_EN vBIT(0)_48 +-#define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49 ++ u64 rmac_addr_cfg; ++#define RMAC_ADDR_UCASTn_EN(n) mS2BIT(0)_n(n) ++#define RMAC_ADDR_MCASTn_EN(n) mS2BIT(0)_n(n) ++#define RMAC_ADDR_BCAST_EN vBIT(0)_48 ++#define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49 + */ + u64 tmac_ipg_cfg; + + u64 rmac_pause_cfg; +-#define RMAC_PAUSE_GEN s2BIT(0) +-#define RMAC_PAUSE_GEN_ENABLE s2BIT(0) +-#define RMAC_PAUSE_RX s2BIT(1) +-#define RMAC_PAUSE_RX_ENABLE s2BIT(1) +-#define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16) +-#define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) ++#define RMAC_PAUSE_GEN S2BIT(0) ++#define RMAC_PAUSE_GEN_ENABLE S2BIT(0) ++#define RMAC_PAUSE_RX S2BIT(1) ++#define RMAC_PAUSE_RX_ENABLE S2BIT(1) ++#define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF, 16, 16) ++#define RMAC_PAUSE_HG_PTIME(val) vBIT(val, 16, 16) + + u64 rmac_red_cfg; + +@@ -773,80 +784,152 @@ + u64 rmac_red_rate_q4q7; + + u64 mac_link_util; +-#define MAC_TX_LINK_UTIL vBIT(0xFE,1,7) +-#define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4) +-#define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4) +-#define MAC_RX_LINK_UTIL vBIT(0xFE,33,7) +-#define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4) +-#define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4) ++#define MAC_TX_LINK_UTIL vBIT(0xFE, 1, 7) ++#define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8, 4) ++#define MAC_TX_LINK_UTIL_VAL(n) vBIT(n, 8, 4) ++#define MAC_RX_LINK_UTIL vBIT(0xFE, 33, 7) ++#define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF, 40, 4) ++#define MAC_RX_LINK_UTIL_VAL(n) vBIT(n, 40, 4) + +-#define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \ +- MAC_RX_LINK_UTIL_DISABLE ++#define MAC_LINK_UTIL_DISABLE (MAC_TX_LINK_UTIL_DISABLE | \ ++ MAC_RX_LINK_UTIL_DISABLE) + + u64 rmac_invalid_ipg; + + /* rx traffic steering */ +-#define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14) ++#define MAC_RTS_FRM_LEN_SET(len) vBIT(len, 2, 14) + u64 rts_frm_len_n[8]; + + u64 rts_qos_steering; + +-#define MAX_DIX_MAP 4 ++#define MAX_DIX_MAP 4 + u64 rts_dix_map_n[MAX_DIX_MAP]; +-#define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) +-#define RTS_DIX_MAP_SCW(val) s2BIT(val,21) ++#define RTS_DIX_MAP_ETYPE(val) vBIT(val, 0, 16) ++#define RTS_DIX_MAP_SCW(val) S2BIT(val, 21) + + u64 rts_q_alternates; + u64 rts_default_q; + + u64 rts_ctrl; +-#define RTS_CTRL_IGNORE_SNAP_OUI s2BIT(2) +-#define RTS_CTRL_IGNORE_LLC_CTRL s2BIT(3) ++#define RTS_CTRL_IGNORE_SNAP_OUI S2BIT(2) ++#define RTS_CTRL_IGNORE_LLC_CTRL S2BIT(3) ++#define RTS_CTRL_ENHANCED S2BIT(7) + + u64 rts_pn_cam_ctrl; +-#define RTS_PN_CAM_CTRL_WE s2BIT(7) +-#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD s2BIT(15) +-#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED s2BIT(15) +-#define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) ++#define RTS_PN_CAM_CTRL_WE S2BIT(7) ++#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD S2BIT(15) ++#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED S2BIT(15) ++#define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n, 24, 8) + u64 rts_pn_cam_data; +-#define RTS_PN_CAM_DATA_TCP_SELECT s2BIT(7) +-#define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) +-#define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) ++#define RTS_PN_CAM_DATA_TCP_SELECT S2BIT(7) ++#define RTS_PN_CAM_DATA_PORT(val) vBIT(val, 8, 16) ++#define RTS_PN_CAM_DATA_SCW(val) vBIT(val, 24, 8) + + u64 rts_ds_mem_ctrl; +-#define RTS_DS_MEM_CTRL_WE s2BIT(7) +-#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD s2BIT(15) +-#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED s2BIT(15) +-#define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) ++#define RTS_DS_MEM_CTRL_WE S2BIT(7) ++#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD S2BIT(15) ++#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED S2BIT(15) ++#define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n, 26, 6) + u64 rts_ds_mem_data; +-#define RTS_DS_MEM_DATA(n) vBIT(n,0,8) ++#define RTS_DS_MEM_DATA(n) vBIT(n, 0, 8) + +- u8 unused16[0x700 - 0x220]; ++ u8 unused15_1[0x308 - 0x220]; ++ ++ u64 rts_vid_mem_ctrl; ++#define RTS_VID_MEM_CTRL_WE S2BIT(7) ++#define RTS_VID_MEM_CTRL_STROBE_NEW_CMD S2BIT(15) ++#define RTS_VID_MEM_CTRL_STROBE_CMD_BEING_EXECUTED S2BIT(15) ++#define RTS_VID_MEM_CTRL_OFFSET(n) vBIT(n, 20, 12) ++ u64 rts_vid_mem_data; ++#define RTS_VID_MEM_ENTRY_EN(n) vBIT(n, 3, 1) ++#define RTS_VID_MEM_DATA(n) vBIT(n, 5, 3) ++ ++ u64 rts_p0_p3_map; ++ u64 rts_p4_p7_map; ++ u8 unused15_2[0x380 - 0x328]; ++ u64 rts_rth_cfg; ++#define RTS_RTH_EN S2BIT(3) ++#define RTS_RTH_BUCKET_SIZE(n) vBIT(n, 4, 4) ++#define RTS_RTH_TCP_IPV4_EN S2BIT(15) ++#define RTS_RTH_UDP_IPV4_EN S2BIT(19) ++#define RTS_RTH_IPV4_EN S2BIT(23) ++#define RTS_RTH_TCP_IPV6_EN S2BIT(27) ++#define RTS_RTH_UDP_IPV6_EN S2BIT(31) ++#define RTS_RTH_IPV6_EN S2BIT(35) ++#define RTS_RTH_TCP_IPV6_EX_EN S2BIT(39) ++#define RTS_RTH_UDP_IPV6_EX_EN S2BIT(43) ++#define RTS_RTH_IPV6_EX_EN S2BIT(47) ++ ++ u64 rts_rth_map_mem_ctrl; ++#define RTS_RTH_MAP_MEM_CTRL_WE S2BIT(7) ++#define RTS_RTH_MAP_MEM_CTRL_STROBE S2BIT(15) ++#define RTS_RTH_MAP_MEM_CTRL_OFFSET(n) vBIT(n, 24, 8) ++ ++ u64 rts_rth_map_mem_data; ++#define RTS_RTH_MAP_MEM_DATA_ENTRY_EN S2BIT(3) ++#define RTS_RTH_MAP_MEM_DATA_(n) vBIT(n, 5, 3) ++ ++ u64 rts_rth_spdm_mem_ctrl; ++#define RTS_RTH_SPDM_MEM_CTRL_STROBE S2BIT(15) ++#define RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(n) vBIT(n, 21, 3) ++#define RTS_RTH_SPDM_MEM_CTRL_OFFSET(n) vBIT(n, 24, 8) ++ ++ u64 rts_rth_spdm_mem_data; ++ ++ u64 rts_rth_jhash_cfg; ++#define RTS_RTH_JHASH_GOLDEN(n) vBIT(n, 0, 32) ++#define RTS_RTH_JHASH_INIT_VAL(n) vBIT(n, 32, 32) ++ ++ u64 rts_rth_hash_mask_n[5]; ++#define RTS_RTH_HASH_MASK_IPV4_SA(mask) vBIT(mask, 0, 32) ++#define RTS_RTH_HASH_MASK_IPV4_DA(mask) vBIT(mask, 32, 32) ++ ++ u64 rts_rth_hash_mask_5; ++#define RTS_RTH_HASH_MASK_L4_SP(mask) vBIT(mask, 0, 16) ++#define RTS_RTH_HASH_MASK_L4_DP(mask) vBIT(mask, 16, 16) ++ ++/* 0x3E0 */ ++ u64 rts_rth_status; ++#define SPDM_USE_L4 S2BIT(3) ++ u8 unused15_3[0x400 - 0x3E8]; ++/* 0x400 */ ++ u64 rmac_red_fine_Q0Q3; ++ u64 rmac_red_fine_Q4Q7; ++ u64 rmac_pthresh_cross; ++ ++#define RMAC_LOW_DOWN_CROSSED_Qn(q) S2BIT(q + 8) ++#define RMAC_HIGH_UP_CROSSED_Qn(q) S2BIT(q + 16) ++ ++ u64 rmac_rthresh_cross; ++ ++ u8 unused16[0x700 - 0x420]; + + u64 mac_debug_ctrl; +-#define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL ++#define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL + + u8 unused17[0x2800 - 0x2708]; + + /* memory controller registers */ + u64 mc_int_status; +-#define MC_INT_STATUS_MC_INT s2BIT(0) ++#define MC_INT_STATUS_MC_INT S2BIT(0) + u64 mc_int_mask; +-#define MC_INT_MASK_MC_INT s2BIT(0) ++#define MC_INT_MASK_MC_INT S2BIT(0) + + u64 mc_err_reg; +-#define MC_ERR_REG_ECC_DB_ERR_L s2BIT(14) +-#define MC_ERR_REG_ECC_DB_ERR_U s2BIT(15) +-#define MC_ERR_REG_MIRI_ECC_DB_ERR_0 s2BIT(18) +-#define MC_ERR_REG_MIRI_ECC_DB_ERR_1 s2BIT(20) +-#define MC_ERR_REG_MIRI_CRI_ERR_0 s2BIT(22) +-#define MC_ERR_REG_MIRI_CRI_ERR_1 s2BIT(23) +-#define MC_ERR_REG_SM_ERR s2BIT(31) +-#define MC_ERR_REG_ECC_ALL_SNG (s2BIT(2) | s2BIT(3) | s2BIT(4) | s2BIT(5) |\ +- s2BIT(17) | s2BIT(19)) +-#define MC_ERR_REG_ECC_ALL_DBL (s2BIT(10) | s2BIT(11) | s2BIT(12) |\ +- s2BIT(13) | s2BIT(18) | s2BIT(20)) +-#define PLL_LOCK_N s2BIT(39) ++#define MC_ERR_REG_ECC_DB_ERR_L S2BIT(14) ++#define MC_ERR_REG_ECC_DB_ERR_U S2BIT(15) ++#define MC_ERR_REG_MIRI_ECC_DB_ERR_0 S2BIT(18) ++#define MC_ERR_REG_MIRI_ECC_DB_ERR_1 S2BIT(20) ++#define MC_ERR_REG_MIRI_CRI_ERR_0 S2BIT(22) ++#define MC_ERR_REG_MIRI_CRI_ERR_1 S2BIT(23) ++#define MC_ERR_REG_SM_ERR S2BIT(31) ++#define MC_ERR_REG_ECC_ALL_SNG (S2BIT(2) | S2BIT(3) | \ ++ S2BIT(4) | S2BIT(5) | \ ++ S2BIT(17) | S2BIT(19)) ++#define MC_ERR_REG_ECC_ALL_DBL (S2BIT(10) | S2BIT(11) | \ ++ S2BIT(12) | S2BIT(13) | \ ++ S2BIT(18) | S2BIT(20)) ++#define PLL_LOCK_N S2BIT(39) + u64 mc_err_mask; + u64 mc_err_alarm; + +@@ -854,18 +937,18 @@ + + /* MC configuration */ + u64 rx_queue_cfg; +-#define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8) +-#define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8) +-#define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8) +-#define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8) +-#define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8) +-#define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8) +-#define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8) +-#define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) ++#define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n, 0, 8) ++#define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n, 8, 8) ++#define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n, 16, 8) ++#define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n, 24, 8) ++#define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n, 32, 8) ++#define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n, 40, 8) ++#define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n, 48, 8) ++#define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n, 56, 8) + + u64 mc_rldram_mrs; +-#define MC_RLDRAM_QUEUE_SIZE_ENABLE s2BIT(39) +-#define MC_RLDRAM_MRS_ENABLE s2BIT(47) ++#define MC_RLDRAM_QUEUE_SIZE_ENABLE S2BIT(39) ++#define MC_RLDRAM_MRS_ENABLE S2BIT(47) + + u64 mc_rldram_interleave; + +@@ -878,11 +961,11 @@ + u64 mc_rldram_ref_per; + u8 unused20[0x220 - 0x208]; + u64 mc_rldram_test_ctrl; +-#define MC_RLDRAM_TEST_MODE s2BIT(47) +-#define MC_RLDRAM_TEST_WRITE s2BIT(7) +-#define MC_RLDRAM_TEST_GO s2BIT(15) +-#define MC_RLDRAM_TEST_DONE s2BIT(23) +-#define MC_RLDRAM_TEST_PASS s2BIT(31) ++#define MC_RLDRAM_TEST_MODE S2BIT(47) ++#define MC_RLDRAM_TEST_WRITE S2BIT(7) ++#define MC_RLDRAM_TEST_GO S2BIT(15) ++#define MC_RLDRAM_TEST_DONE S2BIT(23) ++#define MC_RLDRAM_TEST_PASS S2BIT(31) + + u8 unused21[0x240 - 0x228]; + u64 mc_rldram_test_add; +@@ -895,11 +978,17 @@ + + u8 unused24_1[0x360 - 0x308]; + u64 mc_rldram_ctrl; +-#define MC_RLDRAM_ENABLE_ODT s2BIT(7) ++#define MC_RLDRAM_ENABLE_ODT S2BIT(7) ++ u8 unused25_1[0x380 - 0x368]; ++ u64 mc_qdr_ctrl; ++ u8 unused30[0x460 - 0x388]; ++ u64 mc_rldram_test_add_bkg; ++ u8 unused28[0x620 - 0x468]; ++ u64 mc_driver; ++ u8 unused29[0x640 - 0x628]; + +- u8 unused24_2[0x640 - 0x368]; + u64 mc_rldram_ref_per_herc; +-#define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16) ++#define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16) + + u8 unused24_3[0x660 - 0x648]; + u64 mc_rldram_mrs_herc; +@@ -913,24 +1002,23 @@ + /* XGXS control registers */ + + u64 xgxs_int_status; +-#define XGXS_INT_STATUS_TXGXS s2BIT(0) +-#define XGXS_INT_STATUS_RXGXS s2BIT(1) ++#define XGXS_INT_STATUS_TXGXS S2BIT(0) ++#define XGXS_INT_STATUS_RXGXS S2BIT(1) ++#define SPI_ERR_INT S2BIT(2) + u64 xgxs_int_mask; +-#define XGXS_INT_MASK_TXGXS s2BIT(0) +-#define XGXS_INT_MASK_RXGXS s2BIT(1) +- ++#define XGXS_INT_MASK_TXGXS S2BIT(0) ++#define XGXS_INT_MASK_RXGXS S2BIT(1) + u64 xgxs_txgxs_err_reg; +-#define TXGXS_ECC_SG_ERR s2BIT(7) +-#define TXGXS_ECC_DB_ERR s2BIT(15) +-#define TXGXS_ESTORE_UFLOW s2BIT(31) +-#define TXGXS_TX_SM_ERR s2BIT(39) +- ++#define TXGXS_ECC_SG_ERR S2BIT(7) ++#define TXGXS_ECC_DB_ERR S2BIT(15) ++#define TXGXS_ESTORE_UFLOW S2BIT(31) ++#define TXGXS_TX_SM_ERR S2BIT(39) + u64 xgxs_txgxs_err_mask; + u64 xgxs_txgxs_err_alarm; + + u64 xgxs_rxgxs_err_reg; +-#define RXGXS_ESTORE_OFLOW s2BIT(7) +-#define RXGXS_RX_SM_ERR s2BIT(39) ++#define RXGXS_ESTORE_OFLOW S2BIT(7) ++#define RXGXS_RX_SM_ERR S2BIT(39) + u64 xgxs_rxgxs_err_mask; + u64 xgxs_rxgxs_err_alarm; + +@@ -943,21 +1031,20 @@ + u64 xgxs_efifo_cfg; /* CHANGED */ + u64 rxgxs_ber_0; /* CHANGED */ + u64 rxgxs_ber_1; /* CHANGED */ +- + u64 spi_control; +-#define SPI_CONTROL_KEY(key) vBIT(key,0,4) +-#define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3) +-#define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8) +-#define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24) +-#define SPI_CONTROL_SEL1 s2BIT(4) +-#define SPI_CONTROL_REQ s2BIT(7) +-#define SPI_CONTROL_NACK s2BIT(5) +-#define SPI_CONTROL_DONE s2BIT(6) ++#define SPI_CONTROL_KEY(key) vBIT(key, 0, 4) ++#define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt, 29, 3) ++#define SPI_CONTROL_CMD(cmd) vBIT(cmd, 32, 8) ++#define SPI_CONTROL_ADDR(addr) vBIT(addr, 40, 24) ++#define SPI_CONTROL_SEL1 S2BIT(4) ++#define SPI_CONTROL_REQ S2BIT(7) ++#define SPI_CONTROL_NACK S2BIT(5) ++#define SPI_CONTROL_DONE S2BIT(6) + u64 spi_data; +-#define SPI_DATA_WRITE(data,len) vBIT(data,0,len) ++#define SPI_DATA_WRITE(data, len) vBIT(data, 0, len) + }; + +-#define XENA_REG_SPACE sizeof(struct XENA_dev_config) ++#define XENA_REG_SPACE sizeof(struct XENA_dev_config) + #define XENA_EEPROM_SPACE (0x01 << 11) + + #endif /* _REGS_H */ +diff -r c9d7db01a94c drivers/net/s2io.c +--- a/drivers/net/s2io.c Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/net/s2io.c Tue Sep 01 16:19:08 2009 +0100 +@@ -1,99 +1,198 @@ +-/************************************************************************ +- * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC +- * Copyright(c) 2002-2007 Neterion Inc. +- +- * This software may be used and distributed according to the terms of +- * the GNU General Public License (GPL), incorporated herein by reference. +- * Drivers based on or derived from this code fall under the GPL and must +- * retain the authorship, copyright and license notice. This file is not +- * a complete program and may only be used when the entire operating +- * system is licensed under the GPL. +- * See the file COPYING in this distribution for more information. +- * +- * Credits: +- * Jeff Garzik : For pointing out the improper error condition +- * check in the s2io_xmit routine and also some +- * issues in the Tx watch dog function. Also for +- * patiently answering all those innumerable +- * questions regaring the 2.6 porting issues. +- * Stephen Hemminger : Providing proper 2.6 porting mechanism for some +- * macros available only in 2.6 Kernel. +- * Francois Romieu : For pointing out all code part that were +- * deprecated and also styling related comments. +- * Grant Grundler : For helping me get rid of some Architecture +- * dependent code. +- * Christopher Hellwig : Some more 2.6 specific issues in the driver. +- * +- * The module loadable parameters that are supported by the driver and a brief +- * explaination of all the variables. +- * +- * rx_ring_num : This can be used to program the number of receive rings used +- * in the driver. +- * rx_ring_sz: This defines the number of receive blocks each ring can have. +- * This is also an array of size 8. +- * rx_ring_mode: This defines the operation mode of all 8 rings. The valid +- * values are 1, 2. +- * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver. +- * tx_fifo_len: This too is an array of 8. Each element defines the number of +- * Tx descriptors that can be associated with each corresponding FIFO. +- * intr_type: This defines the type of interrupt. The values can be 0(INTA), +- * 2(MSI_X). Default value is '2(MSI_X)' +- * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not. +- * Possible values '1' for enable '0' for disable. Default is '0' +- * lro_max_pkts: This parameter defines maximum number of packets can be +- * aggregated as a single large packet +- * napi: This parameter used to enable/disable NAPI (polling Rx) +- * Possible values '1' for enable and '0' for disable. Default is '1' +- * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO) +- * Possible values '1' for enable and '0' for disable. Default is '0' +- * vlan_tag_strip: This can be used to enable or disable vlan stripping. +- * Possible values '1' for enable , '0' for disable. +- * Default is '2' - which means disable in promisc mode +- * and enable in non-promiscuous mode. +- * multiq: This parameter used to enable/disable MULTIQUEUE support. +- * Possible values '1' for enable and '0' for disable. Default is '0' +- ************************************************************************/ +- ++/****************************************************************************** ++ * * ++ * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC * ++ * Copyright(c) 2002-2009 Neterion Inc. * ++ * * ++ * This software may be used and distributed according to the terms of * ++ * the GNU General Public License (GPL), incorporated herein by reference. * ++ * Drivers based on or derived from this code fall under the GPL and must * ++ * retain the authorship, copyright and license notice. This file is not * ++ * a complete program and may only be used when the entire operating * ++ * system is licensed under the GPL. * ++ * See the file COPYING in this distribution for more information. * ++ * * ++ * Credits: * ++ * Jeff Garzik : For pointing out the improper error condition * ++ * check in the s2io_xmit routine and also some * ++ * issues in the Tx watch dog function. Also for * ++ * patiently answering all those innumerable * ++ * questions regaring the 2.6 porting issues. * ++ * Stephen Hemminger : Providing proper 2.6 porting mechanism for some * ++ * macros available only in 2.6 Kernel. * ++ * Francois Romieu : For pointing out all code part that were * ++ * deprecated and also styling related comments. * ++ * Grant Grundler : For helping me get rid of some Architecture * ++ * dependent code. * ++ * Christopher Hellwig : Some more 2.6 specific issues in the driver. * ++ * * ++ * The module loadable parameters that are supported by the driver and a brief* ++ * explanation of all the variables. * ++ * * ++ * rst_q_stuck: * ++ * This flag is used to decide whether to reset the device * ++ * when a receive queue is stuck * ++ * rx_ring_num: * ++ * This can be used to program the number of receive rings used * ++ * in the driver. * ++ * rx_ring_sz: * ++ * This defines the number of receive blocks each ring can have. * ++ * This is an array of size 8. * ++ * rx_ring_mode: * ++ * This defines the operation mode of all 8 rings. Possible * ++ * values are 1, 2 and 5, corresponds to 1-buffer, 2-buffer, * ++ * and 5-buffer respectively. Default value is '1'. * ++ * tx_fifo_num: * ++ * This defines the number of Tx FIFOs thats used int the driver. * ++ * tx_fifo_len: * ++ * This is an array of 8. Each element defines the number of * ++ * Tx descriptors that can be associated with each corresponding FIFO * ++ * bw_percentage: * ++ * This is an array of 8. Each element defines the percentage of * ++ * bandwidth associated with each corresponding FIFO/RING * ++ * intr_type: * ++ * This defines the type of interrupt. The values can be 0(INTA), * ++ * 2(MSI-X). Default is '0'(INTA) for Xframe I and '2'(MSI-X) for * ++ * others if system supports MSI-X and has 4 or more cpus, else default* ++ * is '0' * ++ * lro: Specifies whether to enable Large Receive Offload (LRO) or not. * ++ * Possible values: '2' for driver default, 1' for enable and * ++ * '0' for disable. * ++ * Default is '2' - LRO enabled for connections within subnet * ++ * lro_max_bytes: * ++ * This parameter defines maximum number of bytes that can be * ++ * aggregated as a single large packet * ++ * napi: This parameter used to enable/disable NAPI (polling Rx) * ++ * Possible values: '1' for enable and '0' for disable. Default is '1' * ++ * vlan_tag_strip: * ++ * This can be used to enable or disable vlan tag stripping. * ++ * Possible values: '2' for driver default, '1' for enable and * ++ * '0' for disable * ++ * Default is '2' - VLAN tag stripping enabled if vlan group present * ++ * ufo: This parameter is to enable/disable UDP Fragmentation Offload(UFO) * ++ * Possible values: '1' for enable and '0' for disable. Default is '1' * ++ * tx_steering_type: * ++ * This parameter is to configure the transmit distribution * ++ * Possible values: '0' is no steering, '1' is Priority, '2' is vlan * ++ * id, and '3' is Multiq steering and '4' is L3 & L4 tuples * ++ * Default is '3' transmit distribution based on L3 & L4 tuples * ++ * rx_steering_type: * ++ * This parameter is to configure the receive side steering * ++ * Possible values: '0' is no steering, '1' is L4 port, '2' is RTH, '3'* ++ * is Priority, '4' is Vlan id * ++ * Default is '2' RTH steering * ++ * * ++ * Parameters associated when RTH and Port steering are enabled * ++ * * ++ * rth_ports: The specific ports which will be routed to programmed rings. * ++ * Possible values: 0 to 65535 * ++ * Default is '0' * ++ * port_type: * ++ * This parameter can be used to specify if the ports being * ++ * scanned by the H/W is a Destination port or source port. Default is * ++ * destination port. * ++ * Possible values: '1' for destination port and '2' for source port * ++ * Default is '1' destination port * ++ * rth_protocol: * ++ * This parameter can be used to specify the protocol to be used * ++ * Possible values: * ++ * 1 is IPV4 Src and dst address and TCP src and Dst ports * ++ * 2 is IPV4 Src and dst address and UDP src and Dst ports * ++ * 3 is IPV4 Src and dst address * ++ * 4 is IPV6 Src and dst address and TCP src and Dst ports * ++ * 5 is IPV6 Src and dst address and UDP src and Dst ports * ++ * 6 is IPV6 Src and dst address * ++ * 8 is extended IPV6 Src and dst address and UDP src abd Dst ports * ++ * 9 is extended IPV6 Src and dst address * ++ * Default is '1' * ++ * rth_mask: * ++ * This parameter specifies which fields should be considered for the * ++ * RTH calculation. The bits 0 to 5 represent IPV4 SA, IPV4 DA, IPV6 * ++ * SA, IPV6 DA, L4 SP, L4 DP in that order. * ++ * Possible values: 0 to 255 * ++ * Default is '0' no mask * ++ ******************************************************************************/ + #include + #include + #include + #include + #include +-#include + #include + #include + #include ++#include + #include + #include + #include + #include + #include + #include ++#include + #include +-#include +-#include + #include + #include ++#include ++#include ++#include ++#include + #include ++#include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)) ++#include ++#endif + + #include + #include + #include +-#include +-#include ++#include + + /* local include */ ++#include "spdm_cfg.h" ++ ++#include "kcompat.h" + #include "s2io.h" + #include "s2io-regs.h" +- +-#define DRV_VERSION "2.0.26.25" +- ++#include "util.h" ++ ++#define DRV_VERSION "2.1.37.17590" + /* S2io Driver name & version. */ + static char s2io_driver_name[] = "Neterion"; + static char s2io_driver_version[] = DRV_VERSION; + +-static int rxd_size[2] = {32,48}; +-static int rxd_count[2] = {127,85}; ++static int rxd_size[3] = {32, 48, 64}; ++static int rxd_count[3] = {127, 85, 63}; ++ ++/* FIFO mappings for all possible number of fifos configured */ ++static int fifo_map[MAX_TX_FIFOS][8] = { ++ {0, 0, 0, 0, 0, 0, 0, 0}, ++ {0, 0, 0, 0, 1, 1, 1, 1}, ++ {0, 0, 0, 1, 1, 1, 2, 2}, ++ {0, 0, 1, 1, 2, 2, 3, 3}, ++ {0, 0, 1, 1, 2, 2, 3, 4}, ++ {0, 0, 1, 1, 2, 3, 4, 5}, ++ {0, 0, 1, 2, 3, 4, 5, 6}, ++ {0, 1, 2, 3, 4, 5, 6, 7}, ++}; ++ ++static u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7}; ++ ++/* the sub system ids used for xframe-E adapters */ ++static const u16 s2io_subsystem_id[] = { ++ 0x6022, 0x6422, 0x6C22, 0x6822, ++ 0x6023, 0x6423, 0x6C23, 0x6823 ++}; ++ ++/* Extern function prototype declaration. */ ++int spdm_extract_table(void *data, struct s2io_nic *nic); ++int spdm_configure(struct s2io_nic *nic, struct spdm_cfg *info); ++static int spdm_data_processor(struct spdm_cfg *usr_info, struct s2io_nic *sp); ++int s2io_rth_configure(struct s2io_nic *nic); ++int s2io_ioctl_util(struct s2io_nic *sp, struct ifreq *rq, int cmd); ++void general_info(struct s2io_nic *sp, struct ifreq *rq); ++int s2io_snmp_init(struct s2io_nic *nic); ++int s2io_snmp_exit(struct s2io_nic *nic); ++ ++static void fix_rldram(struct s2io_nic *sp); ++static void fix_rldram_qdr(struct s2io_nic *sp); + + static inline int RXD_IS_UP2DT(struct RxD_t *rxdp) + { +@@ -104,6 +203,43 @@ + + return ret; + } ++ ++#ifdef CONFIG_PCI_MSI ++static inline irqreturn_t S2IO_RING_IN_USE(struct ring_info *ring) ++{ ++ irqreturn_t ret = IRQ_NONE; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ if (test_and_set_bit(0, (unsigned long *)(&ring->isr_cnt))) ++ ret = IRQ_HANDLED; ++#endif ++ return ret; ++} ++ ++static inline void S2IO_RING_DONE(struct ring_info *ring) ++{ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ clear_bit(0, (unsigned long *)(&ring->isr_cnt)); ++#endif ++ return; ++} ++static inline irqreturn_t S2IO_FIFO_IN_USE(struct s2io_nic *sp) ++{ ++ irqreturn_t ret = IRQ_NONE; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ if (test_and_set_bit(0, (unsigned long *)(&sp->isr_cnt))) ++ ret = IRQ_HANDLED; ++#endif ++ return ret; ++} ++ ++static inline void S2IO_FIFO_DONE(struct s2io_nic *sp) ++{ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ clear_bit(0, (unsigned long *)(&sp->isr_cnt)); ++#endif ++ return; ++} ++#endif + + /* + * Cards with following subsystem_id have a link state indication +@@ -117,10 +253,11 @@ + + #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \ + ADAPTER_STATUS_RMAC_LOCAL_FAULT))) +- +-static inline int is_s2io_card_up(const struct s2io_nic * sp) +-{ +- return test_bit(__S2IO_STATE_CARD_UP, &sp->state); ++#define mac_stat_info sw_err_stat ++ ++static inline int is_s2io_card_up(const struct s2io_nic *sp) ++{ ++ return test_bit(__S2IO_STATE_CARD_UP, (void *) &sp->state); + } + + /* Ethtool related variables and Macros. */ +@@ -132,6 +269,7 @@ + "BIST Test\t(offline)" + }; + ++#ifdef ETHTOOL_GSTATS + static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = { + {"tmac_frms"}, + {"tmac_data_octets"}, +@@ -242,28 +380,15 @@ + {"rmac_fcs_discard"}, + {"rmac_pf_discard"}, + {"rmac_da_discard"}, +- {"rmac_red_discard"}, ++ {"rmac_wol_discard"}, + {"rmac_rts_discard"}, + {"rmac_ingm_full_discard"}, ++ {"rmac_red_discard"}, + {"link_fault_cnt"} + }; + + static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = { + {"\n DRIVER STATISTICS"}, +- {"single_bit_ecc_errs"}, +- {"double_bit_ecc_errs"}, +- {"parity_err_cnt"}, +- {"serious_err_cnt"}, +- {"soft_reset_cnt"}, +- {"fifo_full_cnt"}, +- {"ring_0_full_cnt"}, +- {"ring_1_full_cnt"}, +- {"ring_2_full_cnt"}, +- {"ring_3_full_cnt"}, +- {"ring_4_full_cnt"}, +- {"ring_5_full_cnt"}, +- {"ring_6_full_cnt"}, +- {"ring_7_full_cnt"}, + {"alarm_transceiver_temp_high"}, + {"alarm_transceiver_temp_low"}, + {"alarm_laser_bias_current_high"}, +@@ -276,34 +401,16 @@ + {"warn_laser_bias_current_low"}, + {"warn_laser_output_power_high"}, + {"warn_laser_output_power_low"}, +- {"lro_aggregated_pkts"}, +- {"lro_flush_both_count"}, +- {"lro_out_of_sequence_pkts"}, +- {"lro_flush_due_to_max_pkts"}, +- {"lro_avg_aggr_pkts"}, +- {"mem_alloc_fail_cnt"}, +- {"pci_map_fail_cnt"}, ++ {"single_bit_ecc_errs"}, ++ {"double_bit_ecc_errs"}, ++ {"parity_err_cnt"}, ++ {"serious_err_cnt"}, ++ {"rx_stuck_cnt"}, ++ {"soft_reset_cnt"}, + {"watchdog_timer_cnt"}, +- {"mem_allocated"}, +- {"mem_freed"}, +- {"link_up_cnt"}, +- {"link_down_cnt"}, +- {"link_up_time"}, +- {"link_down_time"}, +- {"tx_tcode_buf_abort_cnt"}, +- {"tx_tcode_desc_abort_cnt"}, +- {"tx_tcode_parity_err_cnt"}, +- {"tx_tcode_link_loss_cnt"}, +- {"tx_tcode_list_proc_err_cnt"}, +- {"rx_tcode_parity_err_cnt"}, +- {"rx_tcode_abort_cnt"}, +- {"rx_tcode_parity_abort_cnt"}, +- {"rx_tcode_rda_fail_cnt"}, +- {"rx_tcode_unkn_prot_cnt"}, +- {"rx_tcode_fcs_err_cnt"}, +- {"rx_tcode_buf_size_err_cnt"}, +- {"rx_tcode_rxd_corrupt_cnt"}, +- {"rx_tcode_unkn_err_cnt"}, ++ {"dte_reset_cnt"}, ++ {"skb_null_s2io_xmit_cnt"}, ++ {"skb_null_tx_intr_handler_cnt"}, + {"tda_err_cnt"}, + {"pfc_err_cnt"}, + {"pcc_err_cnt"}, +@@ -320,20 +427,348 @@ + {"rpa_err_cnt"}, + {"rda_err_cnt"}, + {"rti_err_cnt"}, +- {"mc_err_cnt"} +-}; +- +-#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys) +-#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys) +-#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys) +- +-#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN ) +-#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN ) +- +-#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN ) +-#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN ) +- +-#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings) ++ {"mc_err_cnt"}, ++ {"tx_intr_cnt"}, ++ {"rx_inta_cnt"}, ++}; ++ ++static char ethtool_driver_dbg_stats_keys[][ETH_GSTRING_LEN] = { ++ {"mem_alloc_fail_cnt"}, ++ {"pci_map_fail_cnt"}, ++ {"mem_allocated"}, ++ {"mem_freed"}, ++ {"link_up_cnt"}, ++ {"link_down_cnt"}, ++ {"link_up_time"}, ++ {"link_down_time"} ++}; ++ ++#ifdef TITAN_LEGACY ++static char ethtool_titan_stats_keys[][ETH_GSTRING_LEN] = { ++ {"tx_frms[0]"}, ++ {"tx_ttl_eth_octets[0]"}, ++ {"tx_data_octets[0]"}, ++ {"tx_mcst_frms[0]"}, ++ {"tx_bcst_frms[0]"}, ++ {"tx_ucst_frms[0]"}, ++ {"tx_tagged_frms[0]"}, ++ {"tx_vld_ip[0]"}, ++ {"tx_vld_ip_octets[0]"}, ++ {"tx_icmp[0]"}, ++ {"tx_tcp[0]"}, ++ {"tx_rst_tcp[0]"}, ++ {"tx_udp[0]"}, ++ {"tx_unknown_protocol[0]"}, ++ {"tx_parse_error[0]"}, ++ {"tx_pause_ctrl_frms[0]"}, ++ {"tx_lacpdu_frms[0]"}, ++ {"tx_marker_pdu_frms[0]"}, ++ {"tx_marker_resp_pdu_frms[0]"}, ++ {"tx_drop_ip[0]"}, ++ {"tx_xgmii_char1_match[0]"}, ++ {"tx_xgmii_char2_match[0]"}, ++ {"tx_xgmii_column1_match[0]"}, ++ {"tx_xgmii_column2_match[0]"}, ++ {"tx_drop_frms[0]"}, ++ {"tx_any_err_frms[0]"}, ++ {"rx_ttl_frms[0]"}, ++ {"rx_vld_frms[0]"}, ++ {"rx_offld_frms[0]"}, ++ {"rx_ttl_eth_octets[0]"}, ++ {"rx_data_octets[0]"}, ++ {"rx_offld_octets[0]"}, ++ {"rx_vld_mcst_frms[0]"}, ++ {"rx_vld_bcst_frms[0]"}, ++ {"rx_accepted_ucst_frms[0]"}, ++ {"rx_accepted_nucst_frms[0]"}, ++ {"rx_tagged_frms[0]"}, ++ {"rx_long_frms[0]"}, ++ {"rx_usized_frms[0]"}, ++ {"rx_osized_frms[0]"}, ++ {"rx_frag_frms[0]"}, ++ {"rx_jabber_frms[0]"}, ++ {"rx_ttl_64_frms[0]"}, ++ {"rx_ttl_65_127_frms[0]"}, ++ {"rx_ttl_128_255_frms[0]"}, ++ {"rx_ttl_256_511_frms[0]"}, ++ {"rx_ttl_512_1023_frms[0]"}, ++ {"rx_ttl_1024_1518_frms[0]"}, ++ {"rx_ttl_1519_4095_frms[0]"}, ++ {"rx_ttl_40956_8191_frms[0]"}, ++ {"rx_ttl_8192_max_frms[0]"}, ++ {"rx_ttl_gt_max_frms[0]"}, ++ {"rx_ip[0]"}, ++ {"rx_ip_octets[0]"}, ++ {"rx_hdr_err_ip[0]"}, ++ {"rx_icmp[0]"}, ++ {"rx_tcp[0]"}, ++ {"rx_udp[0]"}, ++ {"rx_err_tcp[0]"}, ++ {"rx_pause_cnt[0]"}, ++ {"rx_pause_ctrl_frms[0]"}, ++ {"rx_unsup_ctrl_frms[0]"}, ++ {"rx_in_rng_len_err_frms[0]"}, ++ {"rx_out_rng_len_err_frms[0]"}, ++ {"rx_drop_frms[0]"}, ++ {"rx_discarded_frms[0]"}, ++ {"rx_drop_ip[0]"}, ++ {"rx_err_drp_udp[0]"}, ++ {"rx_lacpdu_frms[0]"}, ++ {"rx_marker_pdu_frms[0]"}, ++ {"rx_marker_resp_pdu_frms[0]"}, ++ {"rx_unknown_pdu_frms[0]"}, ++ {"rx_illegal_pdu_frms[0]"}, ++ {"rx_fcs_discard[0]"}, ++ {"rx_len_discard[0]"}, ++ {"rx_pf_discard[0]"}, ++ {"rx_trash_discard[0]"}, ++ {"rx_rts_discard[0]"}, ++ {"rx_wol_discard[0]"}, ++ {"rx_red_discard[0]"}, ++ {"rx_ingm_full_discard[0]"}, ++ {"rx_xgmii_data_err_cnt[0]"}, ++ {"rx_xgmii_ctrl_err_cnt[0]"}, ++ {"rx_xgmii_err_sym[0]"}, ++ {"rx_xgmii_char1_match[0]"}, ++ {"rx_xgmii_char2_match[0]"}, ++ {"rx_xgmii_column1_match[0]"}, ++ {"rx_xgmii_column2_match[0]"}, ++ {"rx_local_fault[0]"}, ++ {"rx_remote_fault[0]"}, ++ {"rx_queue_full[0]"}, ++ {"tx_frms[1]"}, ++ {"tx_ttl_eth_octets[1]"}, ++ {"tx_data_octets[1]"}, ++ {"tx_mcst_frms[1]"}, ++ {"tx_bcst_frms[1]"}, ++ {"tx_ucst_frms[1]"}, ++ {"tx_tagged_frms[1]"}, ++ {"tx_vld_ip[1]"}, ++ {"tx_vld_ip_octets[1]"}, ++ {"tx_icmp[1]"}, ++ {"tx_tcp[1]"}, ++ {"tx_rst_tcp[1]"}, ++ {"tx_udp[1]"}, ++ {"tx_unknown_protocol[1]"}, ++ {"tx_parse_error[1]"}, ++ {"tx_pause_ctrl_frms[1]"}, ++ {"tx_lacpdu_frms[1]"}, ++ {"tx_marker_pdu_frms[1]"}, ++ {"tx_marker_resp_pdu_frms[1]"}, ++ {"tx_drop_ip[1]"}, ++ {"tx_xgmii_char1_match[1]"}, ++ {"tx_xgmii_char2_match[1]"}, ++ {"tx_xgmii_column1_match[1]"}, ++ {"tx_xgmii_column2_match[1]"}, ++ {"tx_drop_frms[1]"}, ++ {"tx_any_err_frms[1]"}, ++ {"rx_ttl_frms[1]"}, ++ {"rx_vld_frms[1]"}, ++ {"rx_offld_frms[1]"}, ++ {"rx_ttl_eth_octets[1]"}, ++ {"rx_data_octets[1]"}, ++ {"rx_offld_octets[1]"}, ++ {"rx_vld_mcst_frms[1]"}, ++ {"rx_vld_bcst_frms[1]"}, ++ {"rx_accepted_ucst_frms[1]"}, ++ {"rx_accepted_nucst_frms[1]"}, ++ {"rx_tagged_frms[1]"}, ++ {"rx_long_frms[1]"}, ++ {"rx_usized_frms[1]"}, ++ {"rx_osized_frms[1]"}, ++ {"rx_frag_frms[1]"}, ++ {"rx_jabber_frms[1]"}, ++ {"rx_ttl_64_frms[1]"}, ++ {"rx_ttl_65_127_frms[1]"}, ++ {"rx_ttl_128_255_frms[1]"}, ++ {"rx_ttl_256_511_frms[1]"}, ++ {"rx_ttl_512_1123_frms[1]"}, ++ {"rx_ttl_1124_1518_frms[1]"}, ++ {"rx_ttl_1519_4195_frms[1]"}, ++ {"rx_ttl_41956_8191_frms[1]"}, ++ {"rx_ttl_8192_max_frms[1]"}, ++ {"rx_ttl_gt_max_frms[1]"}, ++ {"rx_ip[1]"}, ++ {"rx_ip_octets[1]"}, ++ {"rx_hdr_err_ip[1]"}, ++ {"rx_icmp[1]"}, ++ {"rx_tcp[1]"}, ++ {"rx_udp[1]"}, ++ {"rx_err_tcp[1]"}, ++ {"rx_pause_cnt[1]"}, ++ {"rx_pause_ctrl_frms[1]"}, ++ {"rx_unsup_ctrl_frms[1]"}, ++ {"rx_in_rng_len_err_frms[1]"}, ++ {"rx_out_rng_len_err_frms[1]"}, ++ {"rx_drop_frms[1]"}, ++ {"rx_discarded_frms[1]"}, ++ {"rx_drop_ip[1]"}, ++ {"rx_err_drp_udp[1]"}, ++ {"rx_lacpdu_frms[1]"}, ++ {"rx_marker_pdu_frms[1]"}, ++ {"rx_marker_resp_pdu_frms[1]"}, ++ {"rx_unknown_pdu_frms[1]"}, ++ {"rx_illegal_pdu_frms[1]"}, ++ {"rx_fcs_discard[1]"}, ++ {"rx_len_discard[1]"}, ++ {"rx_pf_discard[1]"}, ++ {"rx_trash_discard[1]"}, ++ {"rx_rts_discard[1]"}, ++ {"rx_wol_discard[1]"}, ++ {"rx_red_discard[1]"}, ++ {"rx_ingm_full_discard[1]"}, ++ {"rx_xgmii_data_err_cnt[1]"}, ++ {"rx_xgmii_ctrl_err_cnt[1]"}, ++ {"rx_xgmii_err_sym[1]"}, ++ {"rx_xgmii_char1_match[1]"}, ++ {"rx_xgmii_char2_match[1]"}, ++ {"rx_xgmii_column1_match[1]"}, ++ {"rx_xgmii_column2_match[1]"}, ++ {"rx_local_fault[1]"}, ++ {"rx_remote_fault[1]"}, ++ {"rx_queue_full[1]"}, ++ {"tx_frms[2]"}, ++ {"tx_ttl_eth_octets[2]"}, ++ {"tx_data_octets[2]"}, ++ {"tx_mcst_frms[2]"}, ++ {"tx_bcst_frms[2]"}, ++ {"tx_ucst_frms[2]"}, ++ {"tx_tagged_frms[2]"}, ++ {"tx_vld_ip[2]"}, ++ {"tx_vld_ip_octets[2]"}, ++ {"tx_icmp[2]"}, ++ {"tx_tcp[2]"}, ++ {"tx_rst_tcp[2]"}, ++ {"tx_udp[2]"}, ++ {"tx_unknown_protocol[2]"}, ++ {"tx_parse_error[2]"}, ++ {"tx_pause_ctrl_frms[2]"}, ++ {"tx_lacpdu_frms[2]"}, ++ {"tx_marker_pdu_frms[2]"}, ++ {"tx_marker_resp_pdu_frms[2]"}, ++ {"tx_drop_ip[2]"}, ++ {"tx_xgmii_char2_match[2]"}, ++ {"tx_xgmii_char2_match[2]"}, ++ {"tx_xgmii_column2_match[2]"}, ++ {"tx_xgmii_column2_match[2]"}, ++ {"tx_drop_frms[2]"}, ++ {"tx_any_err_frms[2]"}, ++ {"rx_ttl_frms[2]"}, ++ {"rx_vld_frms[2]"}, ++ {"rx_offld_frms[2]"}, ++ {"rx_ttl_eth_octets[2]"}, ++ {"rx_data_octets[2]"}, ++ {"rx_offld_octets[2]"}, ++ {"rx_vld_mcst_frms[2]"}, ++ {"rx_vld_bcst_frms[2]"}, ++ {"rx_accepted_ucst_frms[2]"}, ++ {"rx_accepted_nucst_frms[2]"}, ++ {"rx_tagged_frms[2]"}, ++ {"rx_long_frms[2]"}, ++ {"rx_osized_frms[2]"}, ++ {"rx_frag_frms[2]"}, ++ {"rx_usized_frms[2]"}, ++ {"rx_jabber_frms[2]"}, ++ {"rx_ttl_64_frms[2]"}, ++ {"rx_ttl_65_227_frms[2]"}, ++ {"rx_ttl_228_255_frms[2]"}, ++ {"rx_ttl_256_522_frms[2]"}, ++ {"rx_ttl_522_2223_frms[2]"}, ++ {"rx_ttl_2224_2528_frms[2]"}, ++ {"rx_ttl_2529_4295_frms[2]"}, ++ {"rx_ttl_42956_8292_frms[2]"}, ++ {"rx_ttl_8292_max_frms[2]"}, ++ {"rx_ttl_gt_max_frms[2]"}, ++ {"rx_ip[2]"}, ++ {"rx_ip_octets[2]"}, ++ {"rx_hdr_err_ip[2]"}, ++ {"rx_icmp[2]"}, ++ {"rx_tcp[2]"}, ++ {"rx_udp[2]"}, ++ {"rx_err_tcp[2]"}, ++ {"rx_pause_cnt[2]"}, ++ {"rx_pause_ctrl_frms[2]"}, ++ {"rx_unsup_ctrl_frms[2]"}, ++ {"rx_in_rng_len_err_frms[2]"}, ++ {"rx_out_rng_len_err_frms[2]"}, ++ {"rx_drop_frms[2]"}, ++ {"rx_discarded_frms[2]"}, ++ {"rx_drop_ip[2]"}, ++ {"rx_err_drp_udp[2]"}, ++ {"rx_lacpdu_frms[2]"}, ++ {"rx_marker_pdu_frms[2]"}, ++ {"rx_marker_resp_pdu_frms[2]"}, ++ {"rx_unknown_pdu_frms[2]"}, ++ {"rx_illegal_pdu_frms[2]"}, ++ {"rx_fcs_discard[2]"}, ++ {"rx_len_discard[2]"}, ++ {"rx_pf_discard[2]"}, ++ {"rx_trash_discard[2]"}, ++ {"rx_rts_discard[2]"}, ++ {"rx_wol_discard[2]"}, ++ {"rx_red_discard[2]"}, ++ {"rx_ingm_full_discard[2]"}, ++ {"rx_xgmii_data_err_cnt[2]"}, ++ {"rx_xgmii_ctrl_err_cnt[2]"}, ++ {"rx_xgmii_err_sym[2]"}, ++ {"rx_xgmii_char2_match[2]"}, ++ {"rx_xgmii_char2_match[2]"}, ++ {"rx_xgmii_column2_match[2]"}, ++ {"rx_xgmii_column2_match[2]"}, ++ {"rx_local_fault[2]"}, ++ {"rx_remote_fault[2]"}, ++ {"rx_queue_full[2]"}, ++ {"aggr_tx_frms[0]"}, ++ {"aggr_tx_mcst_frms[0]"}, ++ {"aggr_tx_bcst_frms[0]"}, ++ {"aggr_tx_discarded_frms[0]"}, ++ {"aggr_tx_errored_frms[0]"}, ++ {"aggr_rx_frms[0]"}, ++ {"aggr_rx_data_octets[0]"}, ++ {"aggr_rx_mcst_frms[0]"}, ++ {"aggr_rx_bcst_frms[0]"}, ++ {"aggr_rx_discarded_frms[0]"}, ++ {"aggr_rx_errored_frms[0]"}, ++ {"aggr_rx_unknown_protocol_frms[0]"}, ++ {"aggr_tx_frms[1]"}, ++ {"aggr_tx_mcst_frms[1]"}, ++ {"aggr_tx_bcst_frms[1]"}, ++ {"aggr_tx_discarded_frms[1]"}, ++ {"aggr_tx_errored_frms[1]"}, ++ {"aggr_rx_frms[1]"}, ++ {"aggr_rx_data_octets[1]"}, ++ {"aggr_rx_mcst_frms[1]"}, ++ {"aggr_rx_bcst_frms[1]"}, ++ {"aggr_rx_discarded_frms[1]"}, ++ {"aggr_rx_errored_frms[1]"}, ++ {"aggr_rx_unknown_protocol_frms[1]"}, ++}; ++#endif ++ ++#define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys) / ETH_GSTRING_LEN ++#define S2IO_ENHANCED_STAT_LEN (sizeof(ethtool_enhanced_stats_keys) / \ ++ ETH_GSTRING_LEN) ++#define S2IO_DRIVER_STAT_LEN (sizeof(ethtool_driver_stats_keys) / \ ++ ETH_GSTRING_LEN) ++#define S2IO_DRIVER_DBG_STAT_LEN (sizeof(ethtool_driver_dbg_stats_keys) / \ ++ ETH_GSTRING_LEN) ++ ++#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN) ++#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN) ++ ++#ifdef TITAN_LEGACY ++ #define S2IO_TITAN_STAT_LEN ++ sizeof(ethtool_titan_stats_keys) / ETH_GSTRING_LEN ++ #define S2IO_TITAN_STAT_STRINGS_LEN ++ S2IO_TITAN_STAT_LEN * ETH_GSTRING_LEN ++#endif ++ ++#define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN) ++#define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN) ++ ++#endif ++ ++#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN + #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN + + #define S2IO_TIMER_CONF(timer, handle, arg, exp) \ +@@ -341,6 +776,13 @@ + timer.function = handle; \ + timer.data = (unsigned long) arg; \ + mod_timer(&timer, (jiffies + exp)) \ ++ ++#define FILL_RR_REG(states, reg) \ ++ writeq(states[0], reg); \ ++ writeq(states[1], reg + 1); \ ++ writeq(states[2], reg + 2); \ ++ writeq(states[3], reg + 3); \ ++ writeq(states[4], reg + 4) \ + + /* copy mac addr to def_mac_addr array */ + static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr) +@@ -352,47 +794,7 @@ + sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32); + sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40); + } +-/* Add the vlan */ +-static void s2io_vlan_rx_register(struct net_device *dev, +- struct vlan_group *grp) +-{ +- int i; +- struct s2io_nic *nic = dev->priv; +- unsigned long flags[MAX_TX_FIFOS]; +- struct mac_info *mac_control = &nic->mac_control; +- struct config_param *config = &nic->config; +- +- for (i = 0; i < config->tx_fifo_num; i++) +- spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]); +- +- nic->vlgrp = grp; +- for (i = config->tx_fifo_num - 1; i >= 0; i--) +- spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, +- flags[i]); +-} +- +-/* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */ +-static int vlan_strip_flag; +- +-/* Unregister the vlan */ +-static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid) +-{ +- int i; +- struct s2io_nic *nic = dev->priv; +- unsigned long flags[MAX_TX_FIFOS]; +- struct mac_info *mac_control = &nic->mac_control; +- struct config_param *config = &nic->config; +- +- for (i = 0; i < config->tx_fifo_num; i++) +- spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]); +- +- if (nic->vlgrp) +- vlan_group_set_device(nic->vlgrp, vid, NULL); +- +- for (i = config->tx_fifo_num - 1; i >= 0; i--) +- spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, +- flags[i]); +-} ++ + + /* + * Constants to be programmed into the Xena's registers, to configure +@@ -460,13 +862,15 @@ + }; + + MODULE_LICENSE("GPL"); ++#ifdef MODULE_VERSION + MODULE_VERSION(DRV_VERSION); ++#endif + + + /* Module Loadable parameters. */ +-S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM); +-S2IO_PARM_INT(rx_ring_num, 1); +-S2IO_PARM_INT(multiq, 0); ++S2IO_PARM_INT(rst_q_stuck, 1); ++S2IO_PARM_INT(tx_fifo_num, 0); ++S2IO_PARM_INT(rx_ring_num, 0); + S2IO_PARM_INT(rx_ring_mode, 1); + S2IO_PARM_INT(use_continuous_tx_intrs, 1); + S2IO_PARM_INT(rmac_pause_time, 0x100); +@@ -476,36 +880,81 @@ + S2IO_PARM_INT(tmac_util_period, 5); + S2IO_PARM_INT(rmac_util_period, 5); + S2IO_PARM_INT(l3l4hdr_size, 128); +-/* 0 is no steering, 1 is Priority steering, 2 is Default steering */ +-S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING); + /* Frequency of Rx desc syncs expressed as power of 2 */ + S2IO_PARM_INT(rxsync_frequency, 3); +-/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */ +-S2IO_PARM_INT(intr_type, 2); ++/* Interrupt type. Values can be 0(INTA), 2(MSI-X)*/ ++#ifdef CONFIG_PCI_MSI ++S2IO_PARM_INT(intr_type, DEF_MSI_X); ++#else ++S2IO_PARM_INT(intr_type, INTA); ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 9)) ++static unsigned int lro_enable = S2IO_DONOT_AGGREGATE; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) ++S2IO_PARM_INT(lro, S2IO_DONOT_AGGREGATE); ++#else + /* Large receive offload feature */ +-static unsigned int lro_enable; + module_param_named(lro, lro_enable, uint, 0); ++#endif ++#else ++static unsigned int lro_enable = S2IO_DONT_AGGR_FWD_PKTS; ++/* Large receive offload feature */ ++module_param_named(lro, lro_enable, uint, 0); ++#endif + + /* Max pkts to be aggregated by LRO at one time. If not specified, +- * aggregation happens until we hit max IP pkt size(64K) +- */ +-S2IO_PARM_INT(lro_max_pkts, 0xFFFF); ++ * aggregation happens until we hit max IP pkt size(16K) ++ */ ++S2IO_PARM_INT(lro_max_bytes, 0x4000); + S2IO_PARM_INT(indicate_max_pkts, 0); +- + S2IO_PARM_INT(napi, 1); +-S2IO_PARM_INT(ufo, 0); +-S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC); +- ++S2IO_PARM_INT(vlan_tag_strip, S2IO_DEFAULT_STRIP_MODE_VLAN_TAG); ++S2IO_PARM_INT(ufo, 1); ++S2IO_PARM_INT(rx_steering_type, RTH_STEERING_DEFAULT); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 26)) ++S2IO_PARM_INT(tx_steering_type, TX_MULTIQ_STEERING); ++#else ++S2IO_PARM_INT(tx_steering_type, TX_STEERING_DEFAULT); ++#endif ++S2IO_PARM_INT(rth_protocol, 0x1); ++S2IO_PARM_INT(rth_mask, 0); ++S2IO_PARM_INT(port_type, DP); ++ ++static int rth_ports[MAX_STEERABLE_PORTS] = ++ {[0 ...(MAX_STEERABLE_PORTS - 1)] = 0 }; ++static unsigned int bw_percentage[MAX_TX_FIFOS] = ++ {[0 ...(MAX_TX_FIFOS - 1)] = 0xFF}; + static unsigned int tx_fifo_len[MAX_TX_FIFOS] = +- {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN}; ++ {[0 ...(MAX_TX_FIFOS - 1)] = FIFO_DEFAULT_LEN}; + static unsigned int rx_ring_sz[MAX_RX_RINGS] = +- {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT}; ++ {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT}; + static unsigned int rts_frm_len[MAX_RX_RINGS] = +- {[0 ...(MAX_RX_RINGS - 1)] = 0 }; +- ++ {[0 ...(MAX_RX_RINGS - 1)] = 0 }; ++ ++#ifdef module_param_array ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 10)) + module_param_array(tx_fifo_len, uint, NULL, 0); + module_param_array(rx_ring_sz, uint, NULL, 0); + module_param_array(rts_frm_len, uint, NULL, 0); ++module_param_array(rth_ports, uint, NULL, 0); ++module_param_array(bw_percentage, uint, NULL, 0); ++#else ++module_param_array(tx_fifo_len, int, tx_fifo_num, 0); ++module_param_array(rx_ring_sz, int, rx_ring_num, 0); ++module_param_array(rts_frm_len, int, rx_ring_num, 0); ++int num_fifo_rings = MAX_RX_RINGS; ++module_param_array(bw_percentage, int, num_fifo_rings, 0); ++int num_rth_ports = MAX_STEERABLE_PORTS; ++module_param_array(rth_ports, int, num_rth_ports, 0); ++#endif ++#else ++MODULE_PARM(tx_fifo_len, "1-" __MODULE_STRING(8) "i"); ++MODULE_PARM(rx_ring_sz, "1-" __MODULE_STRING(8) "i"); ++MODULE_PARM(rts_frm_len, "1-" __MODULE_STRING(8) "i"); ++MODULE_PARM(rth_ports, "1-" __MODULE_STRING(MAX_STEERABLE_PORTS) "i"); ++MODULE_PARM(bw_percentage, "1-" __MODULE_STRING(8) "i"); ++#endif + + /* + * S2IO device table. +@@ -517,151 +966,466 @@ + {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI, + PCI_ANY_ID, PCI_ANY_ID}, + {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN, +- PCI_ANY_ID, PCI_ANY_ID}, +- {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI, +- PCI_ANY_ID, PCI_ANY_ID}, ++ PCI_ANY_ID, PCI_ANY_ID}, ++ {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI, ++ PCI_ANY_ID, PCI_ANY_ID}, ++#ifdef TITAN_LEGACY ++ {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_TITAN_WIN, ++ PCI_ANY_ID, PCI_ANY_ID}, ++ {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_TITAN_UNI, ++ PCI_ANY_ID, PCI_ANY_ID}, ++#endif + {0,} + }; + + MODULE_DEVICE_TABLE(pci, s2io_tbl); + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) + static struct pci_error_handlers s2io_err_handler = { +- .error_detected = s2io_io_error_detected, +- .slot_reset = s2io_io_slot_reset, +- .resume = s2io_io_resume, +-}; ++ .error_detected = s2io_io_error_detected, ++ .slot_reset = s2io_io_slot_reset, ++ .resume = s2io_io_resume, ++}; ++#endif + + static struct pci_driver s2io_driver = { +- .name = "S2IO", +- .id_table = s2io_tbl, +- .probe = s2io_init_nic, +- .remove = __devexit_p(s2io_rem_nic), +- .err_handler = &s2io_err_handler, +-}; +- +-/* A simplifier macro used both by init and free shared_mem Fns(). */ +-#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each) +- +-/* netqueue manipulation helper functions */ ++ .name = "S2IO", ++ .id_table = s2io_tbl, ++ .probe = s2io_init_nic, ++ .remove = __devexit_p(s2io_rem_nic), ++#ifdef CONFIG_PM ++ .suspend = s2io_pm_suspend, ++ .resume = s2io_pm_resume, ++#endif ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) ++ .err_handler = &s2io_err_handler, ++#endif ++}; ++ ++static void s2io_handle_vlan_tag_strip(struct s2io_nic *nic, int flag) ++{ ++ struct XENA_dev_config __iomem *bar0 = nic->bar0; ++ u64 val64; ++ ++ val64 = readq(&bar0->rx_pa_cfg); ++ if (flag == S2IO_DO_NOT_STRIP_VLAN_TAG) ++ val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG; ++ else ++ val64 |= RX_PA_CFG_STRIP_VLAN_TAG; ++ ++ writeq(val64, &bar0->rx_pa_cfg); ++} ++ ++/* Register or unregister the vlan group*/ ++static void s2io_vlan_rx_register(struct net_device *dev, ++ struct vlan_group *grp) ++{ ++ int i; ++ struct s2io_nic *nic = s2io_netdev_priv(dev); ++ unsigned long flags[MAX_TX_FIFOS]; ++ struct mac_info *mac_control = &nic->mac_control; ++ struct config_param *config = &nic->config; ++ ++ for (i = 0; i < config->tx_fifo_num; i++) ++ spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]); ++ ++ nic->vlgrp = grp; ++ ++ /* if vlgrp is NULL disable VLAN stripping */ ++ if (config->vlan_tag_strip == S2IO_DEFAULT_STRIP_MODE_VLAN_TAG) { ++ if (!grp) ++ nic->vlan_strip_flag = S2IO_DO_NOT_STRIP_VLAN_TAG; ++ else ++ nic->vlan_strip_flag = S2IO_STRIP_VLAN_TAG; ++ } ++ ++ s2io_handle_vlan_tag_strip(nic, nic->vlan_strip_flag); ++ ++ for (i = config->tx_fifo_num - 1; i >= 0; i--) ++ spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, ++ flags[i]); ++ ++ for (i = 0; i < config->rx_ring_num; i++) { ++ mac_control->rings[i].vlan_strip_flag = nic->vlan_strip_flag; ++ mac_control->rings[i].vlgrp = nic->vlgrp; ++ } ++} ++ ++/** ++ * rts_vid_steer - Receive traffic steering based on VID ++ * @nic: device private variable ++ * @vid: VLAN ID to map ++ * @ring: ring to steer the above VLAN ID ++ * @enable: 1 - Enable the steering, 0 - Disable the steering ++ * Description: The function configures the receive steering to ++ * steer the VLAN ID to the desired receive ring. ++ * Return Value: SUCCESS on success and ++ * '-1' on failure (endian settings incorrect). ++ */ ++static int rts_vid_steer(struct s2io_nic *nic, u16 vid, u8 ring, u8 enable) ++{ ++ struct XENA_dev_config __iomem *bar0 = nic->bar0; ++ register u64 val64 = 0; ++ ++ if (vid >= VLAN_VID_MASK) ++ return FAILURE; ++ ++ /* Enabled enhanced RTS steering */ ++ val64 = readq(&bar0->rts_ctrl); ++ val64 |= RTS_CTRL_ENHANCED; ++ writeq(val64, &bar0->rts_ctrl); ++ ++ val64 = RTS_VID_MEM_DATA(ring) | ++ RTS_VID_MEM_ENTRY_EN(enable); ++ ++ writeq(val64, &bar0->rts_vid_mem_data); ++ ++ val64 = RTS_VID_MEM_CTRL_WE | ++ RTS_VID_MEM_CTRL_STROBE_NEW_CMD | ++ RTS_VID_MEM_CTRL_OFFSET(vid); ++ ++ writeq(val64, &bar0->rts_vid_mem_ctrl); ++ ++ return wait_for_cmd_complete(&bar0->rts_vid_mem_ctrl, ++ RTS_VID_MEM_CTRL_STROBE_CMD_BEING_EXECUTED, ++ S2IO_BIT_RESET); ++} ++ ++/* Add the vlan */ ++static void s2io_vlan_rx_add_vid(struct net_device *dev, unsigned short vid) ++{ ++ int i; ++ struct s2io_nic *nic = s2io_netdev_priv(dev); ++ unsigned long flags[MAX_TX_FIFOS]; ++ struct mac_info *mac_control = &nic->mac_control; ++ struct config_param *config = &nic->config; ++ ++ if (vid >= VLAN_VID_MASK) ++ return; ++ ++ for (i = 0; i < config->tx_fifo_num; i++) ++ spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]); ++ ++ if (nic->vlgrp) { ++ if ((config->tx_steering_type == TX_VLAN_STEERING) || ++ (config->rx_steering_type == RX_VLAN_STEERING)) { ++ nic->vlan_array[vid] = nic->vlan_added; ++ ++ if (config->rx_steering_type == RX_VLAN_STEERING) { ++ rts_vid_steer(nic, vid, nic->vlan_added, 1); ++ ++nic->vlan_added; ++ nic->vlan_added %= config->rx_ring_num; ++ } else { ++ ++nic->vlan_added; ++ nic->vlan_added %= config->tx_fifo_num; ++ } ++ } ++ } ++ ++ for (i = config->tx_fifo_num - 1; i >= 0; i--) ++ spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, ++ flags[i]); ++} ++ ++/* Unregister the vlan */ ++static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid) ++{ ++ int i; ++ struct s2io_nic *nic = s2io_netdev_priv(dev); ++ unsigned long flags[MAX_TX_FIFOS]; ++ struct mac_info *mac_control = &nic->mac_control; ++ struct config_param *config = &nic->config; ++ ++ if (vid >= VLAN_VID_MASK) ++ return; ++ ++ for (i = 0; i < config->tx_fifo_num; i++) ++ spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]); ++ ++ if (nic->vlgrp) { ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) ++ vlan_group_set_device(nic->vlgrp, vid, NULL); ++#else ++ nic->vlgrp->vlan_devices[vid] = NULL; ++#endif ++ /* Remove vlan id receive steering here */ ++ if (config->rx_steering_type == RX_VLAN_STEERING) ++ rts_vid_steer(nic, vid, nic->vlan_array[vid], 0); ++ ++ if ((config->tx_steering_type == TX_VLAN_STEERING) || ++ (config->rx_steering_type == RX_VLAN_STEERING)) { ++ if (nic->vlan_added) ++ --nic->vlan_added; ++ nic->vlan_array[vid] = S2IO_INVALID_RING; ++ } ++ } ++ ++ for (i = config->tx_fifo_num - 1; i >= 0; i--) ++ spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, ++ flags[i]); ++} ++ ++/* multiqueue manipulation helper functions */ + static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp) + { +- if (!sp->config.multiq) { +- int i; +- ++ int i; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ if(sp->config.tx_steering_type == TX_MULTIQ_STEERING) { ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ netif_stop_subqueue(sp->dev, i); ++ } else ++#endif ++ { + for (i = 0; i < sp->config.tx_fifo_num; i++) + sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP; ++ netif_stop_queue(sp->dev); ++ } ++#else ++ /* If kernel version is >= 2.6.27 */ ++ if(!sp->config.tx_steering_type == TX_MULTIQ_STEERING) { ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP; + } + netif_tx_stop_all_queues(sp->dev); ++#endif + } + + static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no) + { +- if (!sp->config.multiq) ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ if (sp->config.tx_steering_type == TX_MULTIQ_STEERING) ++ netif_stop_subqueue(sp->dev, fifo_no); ++ else ++#endif ++ { + sp->mac_control.fifos[fifo_no].queue_state = + FIFO_QUEUE_STOP; +- +- netif_tx_stop_all_queues(sp->dev); ++ netif_stop_queue(sp->dev); ++ } ++#else ++ /* If kernel version is >= 2.6.27 */ ++ struct netdev_queue *txq = NULL; ++ if (sp->config.tx_steering_type == TX_MULTIQ_STEERING) ++ txq = netdev_get_tx_queue(sp->dev, fifo_no); ++ else { ++ txq = netdev_get_tx_queue(sp->dev, 0); ++ sp->mac_control.fifos[fifo_no].queue_state = ++ FIFO_QUEUE_STOP; ++ } ++ ++ netif_tx_stop_queue(txq); ++#endif + } + + static inline void s2io_start_all_tx_queue(struct s2io_nic *sp) + { +- if (!sp->config.multiq) { +- int i; +- ++ int i; ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ if (sp->config.tx_steering_type == TX_MULTIQ_STEERING) { ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ netif_start_subqueue(sp->dev, i); ++ } else ++#endif ++ { + for (i = 0; i < sp->config.tx_fifo_num; i++) + sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START; +- } +- netif_tx_start_all_queues(sp->dev); ++ netif_start_queue(sp->dev); ++ } ++#else ++ /* If kernel version is >= 2.6.27 */ ++ if (!sp->config.tx_steering_type == TX_MULTIQ_STEERING) { ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START; ++ } ++ netif_tx_start_all_queues(sp->dev); ++#endif + } + + static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no) + { +- if (!sp->config.multiq) ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ if (sp->config.tx_steering_type == TX_MULTIQ_STEERING) ++ netif_start_subqueue(sp->dev, fifo_no); ++ else ++#endif ++ { + sp->mac_control.fifos[fifo_no].queue_state = + FIFO_QUEUE_START; +- +- netif_tx_start_all_queues(sp->dev); ++ netif_start_queue(sp->dev); ++ } ++#else ++ /* If kernel version is >= 2.6.27 */ ++ struct netdev_queue *txq = NULL; ++ if (sp->config.tx_steering_type == TX_MULTIQ_STEERING) ++ txq = netdev_get_tx_queue(sp->dev, fifo_no); ++ else { ++ txq = netdev_get_tx_queue(sp->dev, 0); ++ sp->mac_control.fifos[fifo_no].queue_state = ++ FIFO_QUEUE_START; ++ } ++ ++ netif_tx_start_queue(txq); ++ ++#endif + } + + static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp) + { +- if (!sp->config.multiq) { +- int i; +- ++ int i; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ if (sp->config.tx_steering_type == TX_MULTIQ_STEERING) { ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ netif_wake_subqueue(sp->dev, i); ++ } else ++#endif ++ { + for (i = 0; i < sp->config.tx_fifo_num; i++) + sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START; ++ netif_wake_queue(sp->dev); ++ } ++#else ++ /* If kernel version is >= 2.6.27 */ ++ if (!sp->config.tx_steering_type == TX_MULTIQ_STEERING) { ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START; + } + netif_tx_wake_all_queues(sp->dev); ++ ++#endif + } + + static inline void s2io_wake_tx_queue( +- struct fifo_info *fifo, int cnt, u8 multiq) +-{ +- +- if (multiq) { +- if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no)) ++ struct fifo_info *fifo, int cnt, struct sk_buff *skb, u8 tx_steering) ++{ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ if (tx_steering) { ++ if (cnt && s2io_netif_subqueue_stopped(fifo->dev, skb, ++ fifo->fifo_no)) + netif_wake_subqueue(fifo->dev, fifo->fifo_no); +- } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) { ++ } ++ else ++#endif ++ if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) { + if (netif_queue_stopped(fifo->dev)) { + fifo->queue_state = FIFO_QUEUE_START; + netif_wake_queue(fifo->dev); + } + } +-} +- +-/** +- * init_shared_mem - Allocation and Initialization of Memory +- * @nic: Device private variable. +- * Description: The function allocates all the memory areas shared +- * between the NIC and the driver. This includes Tx descriptors, +- * Rx descriptors and the statistics block. +- */ +- +-static int init_shared_mem(struct s2io_nic *nic) +-{ +- u32 size; +- void *tmp_v_addr, *tmp_v_addr_next; +- dma_addr_t tmp_p_addr, tmp_p_addr_next; +- struct RxD_block *pre_rxd_blk = NULL; +- int i, j, blk_cnt; ++#else ++ /* If kernel version is > 2.6.26 */ ++ struct netdev_queue *txq = NULL; ++ ++ if (tx_steering){ ++ txq = netdev_get_tx_queue(fifo->dev, fifo->fifo_no); ++ if (cnt && netif_tx_queue_stopped(txq)) ++ netif_tx_wake_queue(txq); ++ } ++ else { ++ txq = netdev_get_tx_queue(fifo->dev, 0); ++ ++ if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) ++ if (netif_tx_queue_stopped(txq)) { ++ fifo->queue_state = FIFO_QUEUE_START; ++ netif_tx_wake_queue(txq); ++ } ++ } ++#endif ++} ++ ++/* A simplifier macro used both by init and free shared_mem Fns(). */ ++#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each) ++ ++static void *s2io_kzalloc(int size) ++{ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 14)) ++ void *ret = kmalloc(size, GFP_KERNEL); ++ if(ret) ++ return(memset(ret, 0, size)); ++ else ++ return NULL; ++#else ++ return(kzalloc(size, GFP_KERNEL)); ++#endif ++} ++ ++static int alloc_ethtool_sw_stat(struct s2io_nic *sp) ++{ ++ int i; ++ struct mac_info *mac_control = &sp->mac_control; ++ ++ sp->sw_dbg_stat = s2io_kzalloc(sizeof(struct swDbgStat)); ++ if (!sp->sw_dbg_stat) ++ return -ENOMEM; ++ sp->sw_dbg_stat->mem_allocated += sizeof(struct swDbgStat); ++ ++ sp->xpak_stat = s2io_kzalloc(sizeof(struct xpakStat)); ++ if (!sp->xpak_stat) ++ return -ENOMEM; ++ sp->sw_dbg_stat->mem_allocated += sizeof(struct xpakStat); ++ ++ sp->sw_err_stat = s2io_kzalloc(sizeof(struct swErrStat)); ++ if (!sp->sw_err_stat) ++ return -ENOMEM; ++ sp->sw_dbg_stat->mem_allocated += sizeof(struct swErrStat); ++ ++ for (i = 0; i < sp->config.tx_fifo_num; i++) { ++ mac_control->fifos[i].tx_fifo_stat = ++ s2io_kzalloc(sizeof(struct txFifoStat)); ++ if (!mac_control->fifos[i].tx_fifo_stat) ++ return -ENOMEM; ++ mac_control->fifos[i].tx_fifo_stat->tx_mem_allocated += ++ sizeof(struct txFifoStat); ++ } ++ for (i = 0; i < sp->config.rx_ring_num; i++) { ++ mac_control->rings[i].rx_ring_stat = ++ s2io_kzalloc(sizeof(struct rxRingStat)); ++ if (!mac_control->rings[i].rx_ring_stat) ++ return -ENOMEM; ++ mac_control->rings[i].rx_ring_stat->rx_mem_allocated += ++ sizeof(struct rxRingStat); ++ } ++ return SUCCESS; ++} ++ ++static void free_ethtool_sw_stat(struct s2io_nic *sp) ++{ ++ int i; ++ struct mac_info *mac_control = &sp->mac_control; ++ if (sp->xpak_stat) ++ kfree(sp->xpak_stat); ++ ++ if (sp->sw_err_stat) ++ kfree(sp->sw_err_stat); ++ ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ kfree(mac_control->fifos[i].tx_fifo_stat); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ kfree(mac_control->rings[i].rx_ring_stat); ++ ++ if (sp->sw_dbg_stat) ++ kfree(sp->sw_dbg_stat); ++} ++ ++ ++static int alloc_init_fifo_mem(struct s2io_nic *nic) ++{ ++ int i, j; + int lst_size, lst_per_page; +- struct net_device *dev = nic->dev; +- unsigned long tmp; +- struct buffAdd *ba; +- + struct mac_info *mac_control; + struct config_param *config; + unsigned long long mem_allocated = 0; ++ struct list_info_hold *list_info = NULL; + + mac_control = &nic->mac_control; + config = &nic->config; +- +- +- /* Allocation and initialization of TXDLs in FIOFs */ +- size = 0; +- for (i = 0; i < config->tx_fifo_num; i++) { +- size += config->tx_cfg[i].fifo_len; +- } +- if (size > MAX_AVAILABLE_TXDS) { +- DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, "); +- DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size); +- return -EINVAL; +- } +- +- size = 0; +- for (i = 0; i < config->tx_fifo_num; i++) { +- size = config->tx_cfg[i].fifo_len; +- /* +- * Legal values are from 2 to 8192 +- */ +- if (size < 2) { +- DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size); +- DBG_PRINT(ERR_DBG, "for fifo %d\n", i); +- DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len" +- "are 2 to 8192\n"); +- return -EINVAL; +- } +- } + + lst_size = (sizeof(struct TxD) * config->max_txds); + lst_per_page = PAGE_SIZE / lst_size; +@@ -669,15 +1433,16 @@ + for (i = 0; i < config->tx_fifo_num; i++) { + int fifo_len = config->tx_cfg[i].fifo_len; + int list_holder_size = fifo_len * sizeof(struct list_info_hold); +- mac_control->fifos[i].list_info = kzalloc(list_holder_size, ++ mac_control->fifos[i].list_info = kmalloc(list_holder_size, + GFP_KERNEL); + if (!mac_control->fifos[i].list_info) { +- DBG_PRINT(INFO_DBG, +- "Malloc failed for list_info\n"); ++ DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n"); + return -ENOMEM; + } + mem_allocated += list_holder_size; +- } ++ memset(mac_control->fifos[i].list_info, 0, list_holder_size); ++ } ++ + for (i = 0; i < config->tx_fifo_num; i++) { + int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len, + lst_per_page); +@@ -689,8 +1454,10 @@ + config->tx_cfg[i].fifo_len - 1; + mac_control->fifos[i].fifo_no = i; + mac_control->fifos[i].nic = nic; +- mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2; +- mac_control->fifos[i].dev = dev; ++ mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 1; ++ #ifdef NETIF_F_UFO ++ mac_control->fifos[i].max_txds++; ++ #endif + + for (j = 0; j < page_num; j++) { + int k = 0; +@@ -699,28 +1466,26 @@ + tmp_v = pci_alloc_consistent(nic->pdev, + PAGE_SIZE, &tmp_p); + if (!tmp_v) { +- DBG_PRINT(INFO_DBG, +- "pci_alloc_consistent "); ++ DBG_PRINT(INFO_DBG, "pci_alloc_consistent "); + DBG_PRINT(INFO_DBG, "failed for TxDL\n"); + return -ENOMEM; + } ++ mem_allocated += PAGE_SIZE; + /* If we got a zero DMA address(can happen on + * certain platforms like PPC), reallocate. +- * Store virtual address of page we don't want, +- * to be freed later. ++ * Free the virtual address of page we don't want. + */ + if (!tmp_p) { +- mac_control->zerodma_virt_addr = tmp_v; +- DBG_PRINT(INIT_DBG, +- "%s: Zero DMA address for TxDL. ", dev->name); +- DBG_PRINT(INIT_DBG, +- "Virtual address %p\n", tmp_v); ++ pci_free_consistent(nic->pdev, PAGE_SIZE, ++ tmp_v, (dma_addr_t)0); ++ + tmp_v = pci_alloc_consistent(nic->pdev, + PAGE_SIZE, &tmp_p); + if (!tmp_v) { + DBG_PRINT(INFO_DBG, +- "pci_alloc_consistent "); +- DBG_PRINT(INFO_DBG, "failed for TxDL\n"); ++ "pci_alloc_consistent "); ++ DBG_PRINT(INFO_DBG, ++ "failed for TxDL\n"); + return -ENOMEM; + } + mem_allocated += PAGE_SIZE; +@@ -729,62 +1494,119 @@ + int l = (j * lst_per_page) + k; + if (l == config->tx_cfg[i].fifo_len) + break; +- mac_control->fifos[i].list_info[l].list_virt_addr = +- tmp_v + (k * lst_size); +- mac_control->fifos[i].list_info[l].list_phy_addr = +- tmp_p + (k * lst_size); ++ list_info = ++ &mac_control->fifos[i].list_info[l]; ++ list_info->list_virt_addr = ++ tmp_v + (k * lst_size); ++ list_info->list_phy_addr = ++ tmp_p + (k * lst_size); + k++; + } + } + } +- ++ #ifdef NETIF_F_UFO + for (i = 0; i < config->tx_fifo_num; i++) { +- size = config->tx_cfg[i].fifo_len; ++ lst_size = config->tx_cfg[i].fifo_len; + mac_control->fifos[i].ufo_in_band_v +- = kcalloc(size, sizeof(u64), GFP_KERNEL); ++ = kcalloc(lst_size, sizeof(u64), GFP_KERNEL); + if (!mac_control->fifos[i].ufo_in_band_v) + return -ENOMEM; +- mem_allocated += (size * sizeof(u64)); +- } ++ mem_allocated += (lst_size * sizeof(u64)); ++ } ++ #endif ++ ++ return mem_allocated; ++} ++ ++static int alloc_init_ring_mem(struct s2io_nic *nic) ++{ ++ u32 size; ++ void *tmp_v_addr, *tmp_v_addr_next; ++ dma_addr_t tmp_p_addr, tmp_p_addr_next; ++ struct RxD_block *pre_rxd_blk = NULL; ++ int i, j, blk_cnt, rx_sz; ++ unsigned long tmp; ++ struct buffAdd *ba; ++ struct mac_info *mac_control; ++ struct config_param *config; ++ unsigned long long mem_allocated = 0; ++ int total_rxds = 0; ++ ++ mac_control = &nic->mac_control; ++ config = &nic->config; + + /* Allocation and initialization of RXDs in Rings */ + size = 0; + for (i = 0; i < config->rx_ring_num; i++) { +- if (config->rx_cfg[i].num_rxd % +- (rxd_count[nic->rxd_mode] + 1)) { +- DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name); +- DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ", +- i); +- DBG_PRINT(ERR_DBG, "RxDs per Block"); +- return FAILURE; +- } + size += config->rx_cfg[i].num_rxd; ++ mac_control->rings[i].rx_blocks = ++ kmalloc(rx_ring_sz[i] * sizeof(struct rx_block_info), ++ GFP_KERNEL); ++ if (!mac_control->rings[i].rx_blocks) ++ return -ENOMEM; ++ memset(mac_control->rings[i].rx_blocks, 0, ++ sizeof(struct rx_block_info) * rx_ring_sz[i]); ++ mem_allocated += (rx_ring_sz[i] * ++ sizeof(struct rx_block_info)); + mac_control->rings[i].block_count = + config->rx_cfg[i].num_rxd / + (rxd_count[nic->rxd_mode] + 1 ); + mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd - + mac_control->rings[i].block_count; + } ++ + if (nic->rxd_mode == RXD_MODE_1) + size = (size * (sizeof(struct RxD1))); ++ else if (nic->rxd_mode == RXD_MODE_5) ++ size = (size * (sizeof(struct RxD5))); + else + size = (size * (sizeof(struct RxD3))); ++ rx_sz = size; + + for (i = 0; i < config->rx_ring_num; i++) { + mac_control->rings[i].rx_curr_get_info.block_index = 0; + mac_control->rings[i].rx_curr_get_info.offset = 0; +- mac_control->rings[i].rx_curr_get_info.ring_len = +- config->rx_cfg[i].num_rxd - 1; + mac_control->rings[i].rx_curr_put_info.block_index = 0; + mac_control->rings[i].rx_curr_put_info.offset = 0; +- mac_control->rings[i].rx_curr_put_info.ring_len = +- config->rx_cfg[i].num_rxd - 1; + mac_control->rings[i].nic = nic; + mac_control->rings[i].ring_no = i; ++ mac_control->rings[i].jiffies = jiffies; ++ mac_control->rings[i].interrupt_count = 0; ++ mac_control->rings[i].ufc_a = MIN_RX_UFC_A; ++ mac_control->rings[i].aggr_ack = 0; ++ mac_control->rings[i].max_pkts_aggr = 0; + mac_control->rings[i].lro = lro_enable; +- +- blk_cnt = config->rx_cfg[i].num_rxd / +- (rxd_count[nic->rxd_mode] + 1); ++ for (j = 0; j < MAX_LRO_SESSIONS; j++) { ++ struct lro *l_lro = &mac_control->rings[i].lro0_n[j]; ++ l_lro->in_use = 0; ++ l_lro->saw_ts = 0; ++ l_lro->last_frag = NULL; ++ } ++ if ((config->rx_ring_num == 1) && ++ mac_control->rings[i].config_napi && ++ mac_control->rings[i].lro) ++ mac_control->rings[i].aggr_ack = 1; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) ++ else if ((config->intr_type == MSI_X) && ++ mac_control->rings[i].config_napi && ++ mac_control->rings[i].lro) ++ mac_control->rings[i].aggr_ack = 1; ++#endif ++ ++ total_rxds = config->rx_cfg[i].num_rxd; ++ /* Allocate memory to hold the skb addresses */ ++ if (nic->rxd_mode == RXD_MODE_5) { ++ mac_control->rings[i].skbs = ++ kmalloc(total_rxds * sizeof(u64), GFP_KERNEL); ++ if (!mac_control->rings[i].skbs) ++ return -ENOMEM; ++ memset(mac_control->rings[i].skbs, 0, ++ total_rxds * sizeof(u64)); ++ mem_allocated += (total_rxds * sizeof(u64)); ++ } ++ ++ blk_cnt = total_rxds/(rxd_count[nic->rxd_mode] + 1); ++ + /* Allocating all the Rx blocks */ + for (j = 0; j < blk_cnt; j++) { + struct rx_block_info *rx_blocks; +@@ -813,9 +1635,9 @@ + GFP_KERNEL); + if (!rx_blocks->rxds) + return -ENOMEM; +- mem_allocated += +- (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]); +- for (l=0; lrxd_mode];l++) { ++ mem_allocated += (sizeof(struct rxd_info) * ++ rxd_count[nic->rxd_mode]); ++ for (l=0; lrxd_mode]; l++) { + rx_blocks->rxds[l].virt_addr = + rx_blocks->block_virt_addr + + (rxd_size[nic->rxd_mode] * l); +@@ -826,38 +1648,42 @@ + } + /* Interlinking all Rx Blocks */ + for (j = 0; j < blk_cnt; j++) { +- tmp_v_addr = +- mac_control->rings[i].rx_blocks[j].block_virt_addr; ++ struct rx_block_info *rx_blocks; ++ rx_blocks = &mac_control->rings[i].rx_blocks[j]; ++ tmp_v_addr = rx_blocks->block_virt_addr; + tmp_v_addr_next = + mac_control->rings[i].rx_blocks[(j + 1) % +- blk_cnt].block_virt_addr; +- tmp_p_addr = +- mac_control->rings[i].rx_blocks[j].block_dma_addr; ++ blk_cnt].block_virt_addr; ++ tmp_p_addr = rx_blocks->block_dma_addr; + tmp_p_addr_next = + mac_control->rings[i].rx_blocks[(j + 1) % +- blk_cnt].block_dma_addr; ++ blk_cnt].block_dma_addr; + + pre_rxd_blk = (struct RxD_block *) tmp_v_addr; + pre_rxd_blk->reserved_2_pNext_RxD_block = +- (unsigned long) tmp_v_addr_next; ++ (unsigned long) tmp_v_addr_next; + pre_rxd_blk->pNext_RxD_Blk_physical = +- (u64) tmp_p_addr_next; +- } +- } +- if (nic->rxd_mode == RXD_MODE_3B) { ++ (u64) tmp_p_addr_next; ++ } ++ } ++ ++ if (nic->rxd_mode >= RXD_MODE_3B) { + /* + * Allocation of Storages for buffer addresses in 2BUFF mode + * and the buffers as well. + */ ++ int hdrs_per_cache = L1_CACHE_BYTES / BUF0_LEN; ++ int hdr_index = 0; ++ void *prev_ba_0 = NULL; + for (i = 0; i < config->rx_ring_num; i++) { + blk_cnt = config->rx_cfg[i].num_rxd / + (rxd_count[nic->rxd_mode]+ 1); + mac_control->rings[i].ba = + kmalloc((sizeof(struct buffAdd *) * blk_cnt), +- GFP_KERNEL); ++ GFP_KERNEL); + if (!mac_control->rings[i].ba) + return -ENOMEM; +- mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt); ++ mem_allocated += (sizeof(struct buffAdd *) * blk_cnt); + for (j = 0; j < blk_cnt; j++) { + int k = 0; + mac_control->rings[i].ba[j] = +@@ -866,28 +1692,58 @@ + GFP_KERNEL); + if (!mac_control->rings[i].ba[j]) + return -ENOMEM; +- mem_allocated += (sizeof(struct buffAdd) * \ +- (rxd_count[nic->rxd_mode] + 1)); ++ ++ mem_allocated += (sizeof(struct buffAdd) * ++ (rxd_count[nic->rxd_mode] + 1)); + while (k != rxd_count[nic->rxd_mode]) { + ba = &mac_control->rings[i].ba[j][k]; +- +- ba->ba_0_org = (void *) kmalloc +- (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL); +- if (!ba->ba_0_org) ++ if (L1_CACHE_BYTES > BUF0_LEN) { ++ if (hdr_index == ++ hdrs_per_cache) { ++ prev_ba_0 = NULL; ++ hdr_index = 0; ++ } ++ ba->ba_0_org = NULL; ++ if (hdr_index == 0) { ++ ba->ba_0_org = ++ (void *) kmalloc(2 * ++ L1_CACHE_BYTES, ++ GFP_KERNEL); ++ if (!ba->ba_0_org) ++ return -ENOMEM; ++ mem_allocated += (2 * ++ L1_CACHE_BYTES); ++ ba->ba_0 = (void *) ++ L1_CACHE_ALIGN( ++ (unsigned long) ++ ba->ba_0_org); ++ } else ++ ba->ba_0 = prev_ba_0 + ++ BUF0_LEN; ++ prev_ba_0 = ba->ba_0; ++ hdr_index++; ++ } else { ++ ba->ba_0_org = (void *) kmalloc ++ (BUF0_LEN + ALIGN_SIZE, ++ GFP_KERNEL); ++ if (!ba->ba_0_org) ++ return -ENOMEM; ++ mem_allocated += (BUF0_LEN + ++ ALIGN_SIZE); ++ tmp = ++ (unsigned long)ba->ba_0_org; ++ tmp += ALIGN_SIZE; ++ tmp &= ++ ~((unsigned long) ALIGN_SIZE); ++ ba->ba_0 = (void *) tmp; ++ } ++ ++ ba->ba_1_org = (void *) kmalloc ++ (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL); ++ if (!ba->ba_1_org) + return -ENOMEM; + mem_allocated += +- (BUF0_LEN + ALIGN_SIZE); +- tmp = (unsigned long)ba->ba_0_org; +- tmp += ALIGN_SIZE; +- tmp &= ~((unsigned long) ALIGN_SIZE); +- ba->ba_0 = (void *) tmp; +- +- ba->ba_1_org = (void *) kmalloc +- (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL); +- if (!ba->ba_1_org) +- return -ENOMEM; +- mem_allocated +- += (BUF1_LEN + ALIGN_SIZE); ++ (BUF1_LEN + ALIGN_SIZE); + tmp = (unsigned long) ba->ba_1_org; + tmp += ALIGN_SIZE; + tmp &= ~((unsigned long) ALIGN_SIZE); +@@ -897,6 +1753,79 @@ + } + } + } ++ return mem_allocated; ++} ++ ++ ++/** ++ * init_shared_mem - Allocation and Initialization of Memory ++ * @nic: Device private variable. ++ * Description: The function allocates all the memory areas shared ++ * between the NIC and the driver. This includes Tx descriptors, ++ * Rx descriptors and the statistics block. ++ */ ++ ++static int init_shared_mem(struct s2io_nic *nic) ++{ ++ int size; ++ void *tmp_v_addr = NULL; ++ int i; ++ struct net_device *dev = nic->dev; ++ struct mac_info *mac_control; ++ struct config_param *config; ++ unsigned long long mem_allocated = 0; ++ unsigned long long tx_mem_allocated = 0; ++ unsigned long long rx_mem_allocated = 0; ++ ++ mac_control = &nic->mac_control; ++ config = &nic->config; ++ ++ /* Allocation and initialization of TXDLs in FIOFs */ ++ size = 0; ++ for (i = 0; i < config->tx_fifo_num; i++) ++ size += config->tx_cfg[i].fifo_len; ++ ++ if (size > MAX_AVAILABLE_TXDS) { ++ DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, "); ++ DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", ++ size); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < config->tx_fifo_num; i++) { ++ size = config->tx_cfg[i].fifo_len; ++ /* ++ * Legal values are from 2 to 8192 ++ */ ++ if (size < 2) { ++ DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d) ", ++ size); ++ DBG_PRINT(ERR_DBG, "for fifo %d\n", i); ++ DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len " ++ "are 2 to 8192\n"); ++ return -EINVAL; ++ } ++ } ++ ++ for (i = 0; i < config->rx_ring_num; i++) { ++ if (config->rx_cfg[i].num_rxd % ++ (rxd_count[nic->rxd_mode] + 1)) { ++ DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name); ++ DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ", i); ++ DBG_PRINT(ERR_DBG, "RxDs per Block"); ++ return -EINVAL; ++ } ++ } ++ ++ size = alloc_init_fifo_mem(nic); ++ if (size == -ENOMEM) ++ return size; ++ tx_mem_allocated = size; ++ ++ size = alloc_init_ring_mem(nic); ++ if (size == -ENOMEM) ++ return size; ++ rx_mem_allocated = size; + + /* Allocation and initialization of Statistics block */ + size = sizeof(struct stat_block); +@@ -917,9 +1846,39 @@ + tmp_v_addr = mac_control->stats_mem; + mac_control->stats_info = (struct stat_block *) tmp_v_addr; + memset(tmp_v_addr, 0, size); +- DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name, +- (unsigned long long) tmp_p_addr); +- mac_control->stats_info->sw_stat.mem_allocated += mem_allocated; ++ if (alloc_ethtool_sw_stat(nic) != SUCCESS) ++ return -ENOMEM; ++ ++ if ((config->tx_steering_type == TX_VLAN_STEERING) || ++ (config->rx_steering_type == RX_VLAN_STEERING)) { ++ /* This memory should be allocated only if the steering option is set */ ++ nic->vlan_array = (u16 *) ++ kmalloc(VLAN_GROUP_ARRAY_LEN * ++ sizeof(u16), GFP_KERNEL); ++ if (nic->vlan_array) ++ for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) ++ nic->vlan_array[i] = S2IO_INVALID_RING; ++ else ++ return -ENOMEM; ++ ++ mem_allocated += (VLAN_GROUP_ARRAY_LEN * sizeof(u16)); ++ } ++ ++ nic->sw_dbg_stat->mem_allocated += mem_allocated; ++ ++ /* division result is stored result in tx_mem_allocated */ ++ do_div(tx_mem_allocated, config->tx_fifo_num); ++ for (i = 0; i < config->tx_fifo_num; i++) { ++ mac_control->fifos[i].tx_fifo_stat->tx_mem_allocated = ++ tx_mem_allocated; ++ } ++ ++ /* division result is stored result in rx_mem_allocated */ ++ do_div(rx_mem_allocated, config->rx_ring_num); ++ for (i = 0; i < config->rx_ring_num; i++) { ++ mac_control->rings[i].rx_ring_stat->rx_mem_allocated = ++ rx_mem_allocated; ++ } + return SUCCESS; + } + +@@ -938,13 +1897,10 @@ + struct mac_info *mac_control; + struct config_param *config; + int lst_size, lst_per_page; +- struct net_device *dev; + int page_num = 0; + + if (!nic) + return; +- +- dev = nic->dev; + + mac_control = &nic->mac_control; + config = &nic->config; +@@ -954,7 +1910,7 @@ + + for (i = 0; i < config->tx_fifo_num; i++) { + page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len, +- lst_per_page); ++ lst_per_page); + for (j = 0; j < page_num; j++) { + int mem_blks = (j * lst_per_page); + if (!mac_control->fifos[i].list_info) +@@ -969,31 +1925,19 @@ + mac_control->fifos[i]. + list_info[mem_blks]. + list_phy_addr); +- nic->mac_control.stats_info->sw_stat.mem_freed +- += PAGE_SIZE; +- } +- /* If we got a zero DMA address during allocation, +- * free the page now +- */ +- if (mac_control->zerodma_virt_addr) { +- pci_free_consistent(nic->pdev, PAGE_SIZE, +- mac_control->zerodma_virt_addr, +- (dma_addr_t)0); +- DBG_PRINT(INIT_DBG, +- "%s: Freeing TxDL with zero DMA addr. ", +- dev->name); +- DBG_PRINT(INIT_DBG, "Virtual address %p\n", +- mac_control->zerodma_virt_addr); +- nic->mac_control.stats_info->sw_stat.mem_freed +- += PAGE_SIZE; +- } ++ } ++ + kfree(mac_control->fifos[i].list_info); +- nic->mac_control.stats_info->sw_stat.mem_freed += +- (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold)); + } + + size = SIZE_OF_BLOCK; + for (i = 0; i < config->rx_ring_num; i++) { ++ if (nic->rxd_mode == RXD_MODE_5) { ++ if (mac_control->rings[i].skbs) ++ kfree(mac_control->rings[i].skbs); ++ } ++ if (!mac_control->rings[i].rx_blocks) ++ break; + blk_cnt = mac_control->rings[i].block_count; + for (j = 0; j < blk_cnt; j++) { + tmp_v_addr = mac_control->rings[i].rx_blocks[j]. +@@ -1004,61 +1948,123 @@ + break; + pci_free_consistent(nic->pdev, size, + tmp_v_addr, tmp_p_addr); +- nic->mac_control.stats_info->sw_stat.mem_freed += size; ++ if (NULL == mac_control->rings[i].rx_blocks[j].rxds) ++ break; + kfree(mac_control->rings[i].rx_blocks[j].rxds); +- nic->mac_control.stats_info->sw_stat.mem_freed += +- ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]); +- } +- } +- +- if (nic->rxd_mode == RXD_MODE_3B) { ++ } ++ kfree(mac_control->rings[i].rx_blocks); ++ } ++ ++ if (nic->rxd_mode >= RXD_MODE_3B) { + /* Freeing buffer storage addresses in 2BUFF mode. */ + for (i = 0; i < config->rx_ring_num; i++) { + blk_cnt = config->rx_cfg[i].num_rxd / + (rxd_count[nic->rxd_mode] + 1); ++ if (!mac_control->rings[i].ba) ++ break; + for (j = 0; j < blk_cnt; j++) { + int k = 0; + if (!mac_control->rings[i].ba[j]) + continue; + while (k != rxd_count[nic->rxd_mode]) { + struct buffAdd *ba = +- &mac_control->rings[i].ba[j][k]; +- kfree(ba->ba_0_org); +- nic->mac_control.stats_info->sw_stat.\ +- mem_freed += (BUF0_LEN + ALIGN_SIZE); +- kfree(ba->ba_1_org); +- nic->mac_control.stats_info->sw_stat.\ +- mem_freed += (BUF1_LEN + ALIGN_SIZE); ++ &mac_control->rings[i].ba[j][k]; ++ if (NULL == ba) ++ break; ++ if (ba->ba_0_org) ++ kfree(ba->ba_0_org); ++ if (ba->ba_1_org) ++ kfree(ba->ba_1_org); + k++; + } + kfree(mac_control->rings[i].ba[j]); +- nic->mac_control.stats_info->sw_stat.mem_freed += +- (sizeof(struct buffAdd) * +- (rxd_count[nic->rxd_mode] + 1)); + } + kfree(mac_control->rings[i].ba); +- nic->mac_control.stats_info->sw_stat.mem_freed += +- (sizeof(struct buffAdd *) * blk_cnt); +- } +- } +- +- for (i = 0; i < nic->config.tx_fifo_num; i++) { +- if (mac_control->fifos[i].ufo_in_band_v) { +- nic->mac_control.stats_info->sw_stat.mem_freed +- += (config->tx_cfg[i].fifo_len * sizeof(u64)); +- kfree(mac_control->fifos[i].ufo_in_band_v); + } + } + + if (mac_control->stats_mem) { +- nic->mac_control.stats_info->sw_stat.mem_freed += +- mac_control->stats_mem_sz; + pci_free_consistent(nic->pdev, + mac_control->stats_mem_sz, + mac_control->stats_mem, + mac_control->stats_mem_phy); + } +-} ++ ++#ifdef NETIF_F_UFO ++ for (i = 0; i < config->tx_fifo_num; i++) { ++ if (mac_control->fifos[i].ufo_in_band_v) ++ kfree(mac_control->fifos[i].ufo_in_band_v); ++ } ++#endif ++ free_ethtool_sw_stat(nic); ++ ++ if (nic->vlan_array) ++ kfree(nic->vlan_array); ++} ++ ++#ifdef CONFIG_PM ++/** ++ * s2io_pm_suspend - s2io power management suspend entry point ++ * ++ */ ++static int s2io_pm_suspend(struct pci_dev *pdev, pm_message_t state) ++{ ++ int ret = 0; ++ struct net_device *dev = pci_get_drvdata(pdev); ++ struct s2io_nic *nic = s2io_netdev_priv(dev); ++ ++ if (netif_running(dev)) { ++ s2io_card_down(nic); ++ netif_device_detach(dev); ++ } ++ if (nic->device_type == XFRAME_II_DEVICE) { ++ ret = pci_set_power_state(pdev, pci_choose_state(pdev, state)); ++ if (ret) ++ DBG_PRINT(ERR_DBG, "%s: Error %d setting power state\n", ++ nic->dev->name, ret); ++ } ++ pci_disable_device(pdev); ++ return ret; ++} ++/** ++ * s2io_pm_resume - s2io power management resume entry point ++ * ++ */ ++static int s2io_pm_resume(struct pci_dev *pdev) ++{ ++ int ret = 0; ++ struct net_device *dev = pci_get_drvdata(pdev); ++ struct s2io_nic *nic = s2io_netdev_priv(dev); ++ ++ if (nic->device_type == XFRAME_II_DEVICE) { ++ ret = pci_set_power_state(pdev, PCI_D0); ++ if (ret) { ++ DBG_PRINT(ERR_DBG, "%s: Error %d setting power state\n", ++ nic->dev->name, ret); ++ return ret; ++ } ++ } ++ ret = pci_enable_device(pdev); ++ pci_set_master(pdev); ++ pci_restore_state(pdev, nic->config_space); ++#ifdef CONFIG_PCI_MSI ++ /* Restore the MSIX table entries from local variables */ ++ restore_xmsi_data(nic); ++#endif ++ ++ if (netif_running(dev)) { ++ ret = s2io_card_up(nic); ++ if (ret) ++ DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n", ++ dev->name); ++ } ++ netif_device_attach(dev); ++ s2io_start_all_tx_queue(nic); ++ ++ return ret; ++} ++ ++#endif + + /** + * s2io_verify_pci_mode - +@@ -1083,10 +2089,12 @@ + static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev) + { + struct pci_dev *tdev = NULL; +- while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) { +- if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) { ++ while ((tdev = S2IO_PCI_FIND_DEVICE(PCI_ANY_ID, ++ PCI_ANY_ID, tdev)) != NULL) { ++ if ((tdev->vendor == NEC_VENID) && ++ (tdev->device == NEC_DEVID)) { + if (tdev->bus == s2io_pdev->bus->parent) { +- pci_dev_put(tdev); ++ S2IO_PCI_PUT_DEVICE(tdev); + return 1; + } + } +@@ -1094,7 +2102,7 @@ + return 0; + } + +-static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266}; ++static int bus_speed[8] = {33, 66, 66, 100, 133, 133, 200, 266}; + /** + * s2io_print_pci_mode - + */ +@@ -1108,7 +2116,7 @@ + val64 = readq(&bar0->pci_mode); + mode = (u8)GET_PCI_MODE(val64); + +- if ( val64 & PCI_MODE_UNKNOWN_MODE) ++ if (val64 & PCI_MODE_UNKNOWN_MODE) + return -1; /* Unknown PCI mode */ + + config->bus_speed = bus_speed[mode]; +@@ -1125,7 +2133,7 @@ + DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name); + } + +- switch(mode) { ++ switch (mode) { + case PCI_MODE_PCI_33: + DBG_PRINT(ERR_DBG, "33MHz PCI bus\n"); + break; +@@ -1155,6 +2163,149 @@ + } + + return mode; ++} ++ ++/** ++ * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS ++ * or Traffic class respectively. ++ * @nic: device private variable ++ * Description: The function configures the receive steering to ++ * desired receive ring. ++ * Return Value: SUCCESS on success and ++ * '-1' on failure (endian settings incorrect). ++ */ ++static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring) ++{ ++ struct XENA_dev_config __iomem *bar0 = nic->bar0; ++ register u64 val64 = 0; ++ ++ if (ds_codepoint > 63) ++ return FAILURE; ++ ++ val64 = S2BIT(ring); ++ ++ writeq(val64, &bar0->rts_ds_mem_data); ++ ++ val64 = RTS_DS_MEM_CTRL_WE | ++ RTS_DS_MEM_CTRL_STROBE_NEW_CMD| ++ RTS_DS_MEM_CTRL_OFFSET(ds_codepoint); ++ ++ writeq(val64, &bar0->rts_ds_mem_ctrl); ++ ++ return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl, ++ RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED, ++ S2IO_BIT_RESET); ++} ++ ++/** ++ * init_rti - Initialization receive traffic interrupt scheme ++ * @nic: device private variable ++ * Description: The function configures receive traffic interrupts ++ * Return Value: SUCCESS on success and ++ * '-1' on failure ++ */ ++ ++static int init_rti(struct s2io_nic *nic) ++{ ++ struct XENA_dev_config __iomem *bar0 = nic->bar0; ++ register u64 val64 = 0; ++ int i, timer_interval = 0; ++ struct config_param *config; ++ struct mac_info *mac_control; ++ int udp_ring = 0; ++ ++ config = &nic->config; ++ mac_control = &nic->mac_control; ++ ++ if (nic->device_type == XFRAME_II_DEVICE) { ++ /* ++ * Programmed to generate Apprx 250 Intrs per ++ * second ++ */ ++ timer_interval = (nic->config.bus_speed * 125)/4; ++ } else ++ timer_interval = 0xFFF; ++ ++ /* RTI Initialization */ ++ for (i = 0; i < config->rx_ring_num; i++) { ++ val64 = RTI_DATA1_MEM_RX_TIMER_VAL(timer_interval); ++ mac_control->rings[i].rx_timer_val = timer_interval; ++ mac_control->rings[i].rx_timer_val_saved = timer_interval; ++ ++ if (nic->device_type == XFRAME_I_DEVICE) ++ udp_ring = 0; /* Set TCP settings for XENA rings */ ++ else if (rx_steering_type == NO_STEERING) ++ udp_ring = 0; /* Set TCP settings as default */ ++ else if (rx_steering_type == RX_TOS_STEERING) ++ udp_ring = 0; /* Set TCP settings as default */ ++ else if (rth_protocol == 2) ++ udp_ring = 1; /* Set UDP settings all rings */ ++ else if ((rth_protocol == 1) && rx_ring_num) ++ udp_ring = 0; /* Set TCP settings all rings */ ++ else if ((config->rx_ring_num > 1) && (0 == i)) ++ udp_ring = 1; /* Set UDP settings for ring 0 */ ++ else ++ udp_ring = 0; /* Set TCP settings for other rings */ ++ ++ if (udp_ring) { ++ val64 |= RTI_DATA1_MEM_RX_URNG_A(1); ++ mac_control->rings[i].urange_a = 1; ++ } else { ++ val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA); ++ mac_control->rings[i].urange_a = 0xA; ++ } ++ ++ val64 |= RTI_DATA1_MEM_RX_URNG_B(0x10) | ++ RTI_DATA1_MEM_RX_URNG_C(0x30) | ++ RTI_DATA1_MEM_RX_TIMER_AC_EN; ++ ++ mac_control->rings[i].urange_b = 0x10; ++ mac_control->rings[i].urange_c = 0x30; ++ writeq(val64, &bar0->rti_data1_mem); ++ ++ if (udp_ring) { ++ val64 = RTI_DATA2_MEM_RX_UFC_A(1) | ++ RTI_DATA2_MEM_RX_UFC_B(0x40) ; ++ mac_control->rings[i].ufc_a = 1; ++ mac_control->rings[i].ufc_b = 0x40; ++ } else { ++ val64 = RTI_DATA2_MEM_RX_UFC_A(1) | ++ RTI_DATA2_MEM_RX_UFC_B(2) ; ++ mac_control->rings[i].ufc_a = 1; ++ mac_control->rings[i].ufc_b = 2; ++ } ++ ++ if (config->intr_type == MSI_X) { ++ if (udp_ring) { ++ val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x60) | \ ++ RTI_DATA2_MEM_RX_UFC_D(0x80)); ++ mac_control->rings[i].ufc_c = 0x60; ++ mac_control->rings[i].ufc_d = 0x80; ++ } else { ++ val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \ ++ RTI_DATA2_MEM_RX_UFC_D(0x40)); ++ mac_control->rings[i].ufc_c = 0x20; ++ mac_control->rings[i].ufc_d = 0x40; ++ } ++ } ++ else { ++ val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \ ++ RTI_DATA2_MEM_RX_UFC_D(0x80)); ++ mac_control->rings[i].ufc_c = 0x40; ++ mac_control->rings[i].ufc_d = 0x80; ++ } ++ writeq(val64, &bar0->rti_data2_mem); ++ ++ val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD ++ | RTI_CMD_MEM_OFFSET(i); ++ writeq(val64, &bar0->rti_command_mem); ++ ++ if (wait_for_cmd_complete(&bar0->rti_command_mem, ++ RTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS) ++ return FAILURE; ++ } ++ ++ return SUCCESS; + } + + /** +@@ -1166,7 +2317,6 @@ + * Return Value: SUCCESS on success and + * '-1' on failure + */ +- + static int init_tti(struct s2io_nic *nic, int link) + { + struct XENA_dev_config __iomem *bar0 = nic->bar0; +@@ -1188,27 +2338,33 @@ + } else + val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078); + ++ /* ++ * We will use different interrupt schemes when there are more ++ * than 5 fifos configured ++ */ + val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) | + TTI_DATA1_MEM_TX_URNG_B(0x10) | + TTI_DATA1_MEM_TX_URNG_C(0x30) | + TTI_DATA1_MEM_TX_TIMER_AC_EN; ++ + if (i == 0) +- if (use_continuous_tx_intrs && (link == LINK_UP)) ++ if ((use_continuous_tx_intrs) && (link == LINK_UP)) + val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN; ++ + writeq(val64, &bar0->tti_data1_mem); + +- if (nic->config.intr_type == MSI_X) { ++ if (nic->config.intr_type == MSI_X){ + val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | + TTI_DATA2_MEM_TX_UFC_B(0x100) | + TTI_DATA2_MEM_TX_UFC_C(0x200) | + TTI_DATA2_MEM_TX_UFC_D(0x300); +- } else { ++ } ++ else { + if ((nic->config.tx_steering_type == +- TX_DEFAULT_STEERING) && ++ TX_STEERING_DEFAULT) && + (config->tx_fifo_num > 1) && + (i >= nic->udp_fifo_idx) && +- (i < (nic->udp_fifo_idx + +- nic->total_udp_fifos))) ++ (i < (nic->udp_fifo_idx + nic->total_udp_fifos))) + val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) | + TTI_DATA2_MEM_TX_UFC_B(0x80) | + TTI_DATA2_MEM_TX_UFC_C(0x100) | +@@ -1219,7 +2375,6 @@ + TTI_DATA2_MEM_TX_UFC_C(0x40) | + TTI_DATA2_MEM_TX_UFC_D(0x80); + } +- + writeq(val64, &bar0->tti_data2_mem); + + val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD | +@@ -1234,9 +2389,127 @@ + return SUCCESS; + } + ++static void verify_bandwidth(int queue_num, unsigned int *queue_bw_percentage, ++ u8 queue_type) ++{ ++ int i, band_width, total = 0, equal_priority = 0; ++ ++ //1. If user enters 0 for some fifo, give equal priority to all ++ for(i = 0; i < queue_num; i++) { ++ if (queue_bw_percentage[i] == 0) { ++ equal_priority = 1; ++ break; ++ } ++ } ++ ++ if (!equal_priority) { ++ total = 0; ++ //2. If sum exceeds 100, give equal priority to all ++ for (i = 0; i < queue_num; i++) { ++ if (queue_bw_percentage[i] != 0xFF) ++ total += queue_bw_percentage[i]; ++ if (total > 100) { ++ equal_priority = 1; ++ break; ++ } ++ } ++ } ++ ++ if (!equal_priority) { ++ total = 0; ++ for (i = 0; i < queue_num; i++) { ++ if (queue_bw_percentage[i] == 0xFF) ++ break; ++ total += queue_bw_percentage[i]; ++ } ++ ++ if (total < 100) { ++ if (i < queue_num) { ++ band_width = (100 - total) / ++ (queue_num - i); ++ if (band_width < 2) ++ equal_priority = 1; ++ else { ++ for(; i < queue_num; i++) ++ queue_bw_percentage[i] = ++ band_width; ++ } ++ } ++ } else if (i < queue_num) ++ equal_priority = 1; ++ } ++ ++ if (equal_priority) { ++ if (queue_type == QUEUE_FIFO) { ++ DBG_PRINT(ERR_DBG, ++ "Assigning equal bandwidth to all the fifos\n"); ++ } else ++ DBG_PRINT(ERR_DBG, ++ "Assigning equal bandwidth to all the rings\n"); ++ for (i = 0; i < queue_num; i++) ++ queue_bw_percentage[i] = 100 / queue_num; ++ } ++} ++ ++static void do_calculate_calendar(u32 num, unsigned int *bw, u64 *rr_states, ++ int type) ++{ ++ int i, j, how_often = 1; ++ unsigned char queue_to_serve[40] = {[0 ...39] = 0xff}; ++ u64 *val64; ++ const char *str = (type == QUEUE_FIFO)?"Fifo":"Ring"; ++ ++ //Prepare the service states ++ for (i = 0; i < num; i++) { ++ how_often = 100 / bw[i]; ++ if (how_often) { ++ DBG_PRINT(INFO_DBG, ++ "%s%d is to be served %d times\n", str, i, how_often); ++ ++ for (j = 0; j < 36; ) { ++ if(queue_to_serve[j] == 0xFF) { ++ queue_to_serve[j] = i; ++ //Make sure each fifo/ring is serviced atleast once ++ if(i == j) ++ j += num; ++ else ++ j += how_often; ++ } else ++ j++; ++ } ++ } ++ } ++ ++ //Fill the unused slots with 0 ++ for (j = 0; j < 40; j++) ++ if (queue_to_serve[j] == 0xFF) ++ queue_to_serve[j] = 0; ++ ++ for (j = 0; j < 5; j++) { ++ val64 = (u64*)(queue_to_serve + j*8); ++ rr_states[j] = swab64(*val64); ++ DBG_PRINT(INFO_DBG, ++ "%s state%d %llx \n", str, j, (unsigned long long)rr_states[j]); ++ } ++} ++ ++static void calculate_calender(struct s2io_nic *nic) ++{ ++ struct config_param *config = &nic->config; ++ ++ verify_bandwidth(config->tx_fifo_num, config->tx_bw_percentage, QUEUE_FIFO); ++ verify_bandwidth(config->rx_ring_num, config->rx_bw_percentage, QUEUE_RING); ++ ++ do_calculate_calendar( config->tx_fifo_num, config->tx_bw_percentage, ++ nic->tx_round_robin_states, QUEUE_FIFO); ++ ++ do_calculate_calendar( config->rx_ring_num, config->rx_bw_percentage, ++ nic->rx_round_robin_states, QUEUE_RING); ++} ++ + /** + * init_nic - Initialization of hardware +- * @nic: device private variable ++ * @nic: device peivate variable + * Description: The function sequentially configures every block + * of the H/W from their reset values. + * Return Value: SUCCESS on success and +@@ -1249,7 +2522,6 @@ + struct net_device *dev = nic->dev; + register u64 val64 = 0; + void __iomem *add; +- u32 time; + int i, j; + struct mac_info *mac_control; + struct config_param *config; +@@ -1261,7 +2533,7 @@ + config = &nic->config; + + /* to set the swapper controle on the card */ +- if(s2io_set_swapper(nic)) { ++ if (s2io_set_swapper(nic)) { + DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n"); + return -EIO; + } +@@ -1269,7 +2541,7 @@ + /* + * Herc requires EOI to be removed from reset before XGXS, so.. + */ +- if (nic->device_type & XFRAME_II_DEVICE) { ++ if (nic->device_type == XFRAME_II_DEVICE) { + val64 = 0xA500000000ULL; + writeq(val64, &bar0->sw_reset); + msleep(500); +@@ -1286,7 +2558,7 @@ + * RIC_RUNNING bit is reset. Check is valid only for XframeII. + */ + if (nic->device_type == XFRAME_II_DEVICE) { +- for (i = 0; i < 50; i++) { ++ for (i=0; i < 50; i++) { + val64 = readq(&bar0->adapter_status); + if (!(val64 & ADAPTER_STATUS_RIC_RUNNING)) + break; +@@ -1314,10 +2586,10 @@ + val64 = dev->mtu; + writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); + +- if (nic->device_type & XFRAME_II_DEVICE) { ++ if (nic->device_type == XFRAME_II_DEVICE) { + while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) { + SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt], +- &bar0->dtx_control, UF); ++ &bar0->dtx_control, UF); + if (dtx_cnt & 0x1) + msleep(1); /* Necessary!! */ + dtx_cnt++; +@@ -1338,12 +2610,11 @@ + writeq(val64, &bar0->tx_fifo_partition_2); + writeq(val64, &bar0->tx_fifo_partition_3); + +- + for (i = 0, j = 0; i < config->tx_fifo_num; i++) { + val64 |= +- vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19), +- 13) | vBIT(config->tx_cfg[i].fifo_priority, +- ((j * 32) + 5), 3); ++ vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19), ++ 13) | vBIT(config->tx_cfg[i].fifo_priority, ++ ((j * 32) + 5), 3); + + if (i == (config->tx_fifo_num - 1)) { + if (i % 2 == 0) +@@ -1382,7 +2653,7 @@ + * SXE-008 TRANSMIT DMA ARBITRATION ISSUE. + */ + if ((nic->device_type == XFRAME_I_DEVICE) && +- (nic->pdev->revision < 4)) ++ (get_xena_rev_id(nic->pdev) < 4)) + writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable); + + val64 = readq(&bar0->tx_fifo_partition_0); +@@ -1395,16 +2666,16 @@ + */ + val64 = readq(&bar0->tx_pa_cfg); + val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI | +- TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR; ++ TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR; + writeq(val64, &bar0->tx_pa_cfg); + + /* Rx DMA intialization. */ + val64 = 0; +- for (i = 0; i < config->rx_ring_num; i++) { ++ for (i = 0; i < config->rx_ring_num; i++) + val64 |= +- vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)), +- 3); +- } ++ vBIT(config->rx_cfg[i].ring_priority, ++ (5 + (i * 8)), 3); ++ + writeq(val64, &bar0->rx_queue_priority); + + /* +@@ -1412,7 +2683,7 @@ + * configured Rings. + */ + val64 = 0; +- if (nic->device_type & XFRAME_II_DEVICE) ++ if (nic->device_type == XFRAME_II_DEVICE) + mem_size = 32; + else + mem_size = 64; +@@ -1421,7 +2692,7 @@ + switch (i) { + case 0: + mem_share = (mem_size / config->rx_ring_num + +- mem_size % config->rx_ring_num); ++ mem_size % config->rx_ring_num); + val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share); + continue; + case 1: +@@ -1456,95 +2727,13 @@ + } + writeq(val64, &bar0->rx_queue_cfg); + ++ calculate_calender(nic); ++ + /* + * Filling Tx round robin registers +- * as per the number of FIFOs for equal scheduling priority +- */ +- switch (config->tx_fifo_num) { +- case 1: +- val64 = 0x0; +- writeq(val64, &bar0->tx_w_round_robin_0); +- writeq(val64, &bar0->tx_w_round_robin_1); +- writeq(val64, &bar0->tx_w_round_robin_2); +- writeq(val64, &bar0->tx_w_round_robin_3); +- writeq(val64, &bar0->tx_w_round_robin_4); +- break; +- case 2: +- val64 = 0x0001000100010001ULL; +- writeq(val64, &bar0->tx_w_round_robin_0); +- writeq(val64, &bar0->tx_w_round_robin_1); +- writeq(val64, &bar0->tx_w_round_robin_2); +- writeq(val64, &bar0->tx_w_round_robin_3); +- val64 = 0x0001000100000000ULL; +- writeq(val64, &bar0->tx_w_round_robin_4); +- break; +- case 3: +- val64 = 0x0001020001020001ULL; +- writeq(val64, &bar0->tx_w_round_robin_0); +- val64 = 0x0200010200010200ULL; +- writeq(val64, &bar0->tx_w_round_robin_1); +- val64 = 0x0102000102000102ULL; +- writeq(val64, &bar0->tx_w_round_robin_2); +- val64 = 0x0001020001020001ULL; +- writeq(val64, &bar0->tx_w_round_robin_3); +- val64 = 0x0200010200000000ULL; +- writeq(val64, &bar0->tx_w_round_robin_4); +- break; +- case 4: +- val64 = 0x0001020300010203ULL; +- writeq(val64, &bar0->tx_w_round_robin_0); +- writeq(val64, &bar0->tx_w_round_robin_1); +- writeq(val64, &bar0->tx_w_round_robin_2); +- writeq(val64, &bar0->tx_w_round_robin_3); +- val64 = 0x0001020300000000ULL; +- writeq(val64, &bar0->tx_w_round_robin_4); +- break; +- case 5: +- val64 = 0x0001020304000102ULL; +- writeq(val64, &bar0->tx_w_round_robin_0); +- val64 = 0x0304000102030400ULL; +- writeq(val64, &bar0->tx_w_round_robin_1); +- val64 = 0x0102030400010203ULL; +- writeq(val64, &bar0->tx_w_round_robin_2); +- val64 = 0x0400010203040001ULL; +- writeq(val64, &bar0->tx_w_round_robin_3); +- val64 = 0x0203040000000000ULL; +- writeq(val64, &bar0->tx_w_round_robin_4); +- break; +- case 6: +- val64 = 0x0001020304050001ULL; +- writeq(val64, &bar0->tx_w_round_robin_0); +- val64 = 0x0203040500010203ULL; +- writeq(val64, &bar0->tx_w_round_robin_1); +- val64 = 0x0405000102030405ULL; +- writeq(val64, &bar0->tx_w_round_robin_2); +- val64 = 0x0001020304050001ULL; +- writeq(val64, &bar0->tx_w_round_robin_3); +- val64 = 0x0203040500000000ULL; +- writeq(val64, &bar0->tx_w_round_robin_4); +- break; +- case 7: +- val64 = 0x0001020304050600ULL; +- writeq(val64, &bar0->tx_w_round_robin_0); +- val64 = 0x0102030405060001ULL; +- writeq(val64, &bar0->tx_w_round_robin_1); +- val64 = 0x0203040506000102ULL; +- writeq(val64, &bar0->tx_w_round_robin_2); +- val64 = 0x0304050600010203ULL; +- writeq(val64, &bar0->tx_w_round_robin_3); +- val64 = 0x0405060000000000ULL; +- writeq(val64, &bar0->tx_w_round_robin_4); +- break; +- case 8: +- val64 = 0x0001020304050607ULL; +- writeq(val64, &bar0->tx_w_round_robin_0); +- writeq(val64, &bar0->tx_w_round_robin_1); +- writeq(val64, &bar0->tx_w_round_robin_2); +- writeq(val64, &bar0->tx_w_round_robin_3); +- val64 = 0x0001020300000000ULL; +- writeq(val64, &bar0->tx_w_round_robin_4); +- break; +- } ++ * as per the number of FIFOs ++ */ ++ FILL_RR_REG(nic->tx_round_robin_states, &bar0->tx_w_round_robin_0); + + /* Enable all configured Tx FIFO partitions */ + val64 = readq(&bar0->tx_fifo_partition_0); +@@ -1552,117 +2741,121 @@ + writeq(val64, &bar0->tx_fifo_partition_0); + + /* Filling the Rx round robin registers as per the +- * number of Rings and steering based on QoS with +- * equal priority. +- */ ++ * number of Rings and steering based on QoS. ++ */ ++ ++ /* ++ * Classic mode: Specify which queues a frame with a particular ++ * QoS value may be steered to ++ * Enhanced mode: Maps QoS to a priority level which is ++ * then mapped to a queue ++ */ ++ FILL_RR_REG(nic->rx_round_robin_states, &bar0->rx_w_round_robin_0); ++ + switch (config->rx_ring_num) { + case 1: +- val64 = 0x0; +- writeq(val64, &bar0->rx_w_round_robin_0); +- writeq(val64, &bar0->rx_w_round_robin_1); +- writeq(val64, &bar0->rx_w_round_robin_2); +- writeq(val64, &bar0->rx_w_round_robin_3); +- writeq(val64, &bar0->rx_w_round_robin_4); +- +- val64 = 0x8080808080808080ULL; +- writeq(val64, &bar0->rts_qos_steering); ++ if (config->rx_steering_type && ++ config->rx_steering_type != RX_TOS_STEERING) { ++ val64 = 0x0180018001800180ULL; ++ writeq(val64, &bar0->rts_p0_p3_map); ++ val64 = 0x0180018001800180ULL; ++ writeq(val64, &bar0->rts_p4_p7_map); ++ val64 = 0x00ULL; ++ } else ++ val64 = 0x8080808080808080ULL; ++ + break; + case 2: +- val64 = 0x0001000100010001ULL; +- writeq(val64, &bar0->rx_w_round_robin_0); +- writeq(val64, &bar0->rx_w_round_robin_1); +- writeq(val64, &bar0->rx_w_round_robin_2); +- writeq(val64, &bar0->rx_w_round_robin_3); +- val64 = 0x0001000100000000ULL; +- writeq(val64, &bar0->rx_w_round_robin_4); +- +- val64 = 0x8080808040404040ULL; +- writeq(val64, &bar0->rts_qos_steering); ++ if (config->rx_steering_type && ++ config->rx_steering_type != RX_TOS_STEERING) { ++ val64 = 0x0180018001800180ULL; ++ writeq(val64, &bar0->rts_p0_p3_map); ++ val64 = 0x0140014001400140ULL; ++ writeq(val64, &bar0->rts_p4_p7_map); ++ val64 = 0x0000000001010101ULL; ++ } else ++ val64 = 0x8080808040404040ULL; ++ + break; + case 3: +- val64 = 0x0001020001020001ULL; +- writeq(val64, &bar0->rx_w_round_robin_0); +- val64 = 0x0200010200010200ULL; +- writeq(val64, &bar0->rx_w_round_robin_1); +- val64 = 0x0102000102000102ULL; +- writeq(val64, &bar0->rx_w_round_robin_2); +- val64 = 0x0001020001020001ULL; +- writeq(val64, &bar0->rx_w_round_robin_3); +- val64 = 0x0200010200000000ULL; +- writeq(val64, &bar0->rx_w_round_robin_4); +- +- val64 = 0x8080804040402020ULL; +- writeq(val64, &bar0->rts_qos_steering); ++ if (config->rx_steering_type && ++ config->rx_steering_type != RX_TOS_STEERING) { ++ val64 = 0x0180018001800140ULL; ++ writeq(val64, &bar0->rts_p0_p3_map); ++ val64 = 0x0140014001200120ULL; ++ writeq(val64, &bar0->rts_p4_p7_map); ++ val64 = 0x0000000101010202ULL; ++ } else ++ val64 = 0x8080804040402020ULL; ++ + break; + case 4: +- val64 = 0x0001020300010203ULL; +- writeq(val64, &bar0->rx_w_round_robin_0); +- writeq(val64, &bar0->rx_w_round_robin_1); +- writeq(val64, &bar0->rx_w_round_robin_2); +- writeq(val64, &bar0->rx_w_round_robin_3); +- val64 = 0x0001020300000000ULL; +- writeq(val64, &bar0->rx_w_round_robin_4); +- +- val64 = 0x8080404020201010ULL; +- writeq(val64, &bar0->rts_qos_steering); ++ if (config->rx_steering_type && ++ config->rx_steering_type != RX_TOS_STEERING) { ++ val64 = 0x0180018001400140ULL; ++ writeq(val64, &bar0->rts_p0_p3_map); ++ val64 = 0x0120012001100110ULL; ++ writeq(val64, &bar0->rts_p4_p7_map); ++ val64 = 0x0000010102020303ULL; ++ } else ++ val64 = 0x8080404020201010ULL; ++ + break; + case 5: +- val64 = 0x0001020304000102ULL; +- writeq(val64, &bar0->rx_w_round_robin_0); +- val64 = 0x0304000102030400ULL; +- writeq(val64, &bar0->rx_w_round_robin_1); +- val64 = 0x0102030400010203ULL; +- writeq(val64, &bar0->rx_w_round_robin_2); +- val64 = 0x0400010203040001ULL; +- writeq(val64, &bar0->rx_w_round_robin_3); +- val64 = 0x0203040000000000ULL; +- writeq(val64, &bar0->rx_w_round_robin_4); +- +- val64 = 0x8080404020201008ULL; +- writeq(val64, &bar0->rts_qos_steering); ++ if (config->rx_steering_type && ++ config->rx_steering_type != RX_TOS_STEERING) { ++ val64 = 0x0180018001400140ULL; ++ writeq(val64, &bar0->rts_p0_p3_map); ++ val64 = 0x0120012001100108ULL; ++ writeq(val64, &bar0->rts_p4_p7_map); ++ val64 = 0x0000010102020304ULL; ++ } else ++ val64 = 0x8080404020201008ULL; ++ + break; + case 6: +- val64 = 0x0001020304050001ULL; +- writeq(val64, &bar0->rx_w_round_robin_0); +- val64 = 0x0203040500010203ULL; +- writeq(val64, &bar0->rx_w_round_robin_1); +- val64 = 0x0405000102030405ULL; +- writeq(val64, &bar0->rx_w_round_robin_2); +- val64 = 0x0001020304050001ULL; +- writeq(val64, &bar0->rx_w_round_robin_3); +- val64 = 0x0203040500000000ULL; +- writeq(val64, &bar0->rx_w_round_robin_4); +- +- val64 = 0x8080404020100804ULL; +- writeq(val64, &bar0->rts_qos_steering); ++ if (config->rx_steering_type && ++ config->rx_steering_type != RX_TOS_STEERING) { ++ val64 = 0x0180018001400140ULL; ++ writeq(val64, &bar0->rts_p0_p3_map); ++ val64 = 0x0120011001080104ULL; ++ writeq(val64, &bar0->rts_p4_p7_map); ++ val64 = 0x0000010102030405ULL; ++ } else ++ val64 = 0x8080404020100804ULL; ++ + break; + case 7: +- val64 = 0x0001020304050600ULL; +- writeq(val64, &bar0->rx_w_round_robin_0); +- val64 = 0x0102030405060001ULL; +- writeq(val64, &bar0->rx_w_round_robin_1); +- val64 = 0x0203040506000102ULL; +- writeq(val64, &bar0->rx_w_round_robin_2); +- val64 = 0x0304050600010203ULL; +- writeq(val64, &bar0->rx_w_round_robin_3); +- val64 = 0x0405060000000000ULL; +- writeq(val64, &bar0->rx_w_round_robin_4); +- +- val64 = 0x8080402010080402ULL; +- writeq(val64, &bar0->rts_qos_steering); ++ if (config->rx_steering_type && ++ config->rx_steering_type != RX_TOS_STEERING) { ++ val64 = 0x0180018001400120ULL; ++ writeq(val64, &bar0->rts_p0_p3_map); ++ val64 = 0x0110010801040102ULL; ++ writeq(val64, &bar0->rts_p4_p7_map); ++ val64 = 0x0000010203040506ULL; ++ } else ++ val64 = 0x8080402010080402ULL; ++ + break; + case 8: +- val64 = 0x0001020304050607ULL; +- writeq(val64, &bar0->rx_w_round_robin_0); +- writeq(val64, &bar0->rx_w_round_robin_1); +- writeq(val64, &bar0->rx_w_round_robin_2); +- writeq(val64, &bar0->rx_w_round_robin_3); +- val64 = 0x0001020300000000ULL; +- writeq(val64, &bar0->rx_w_round_robin_4); +- +- val64 = 0x8040201008040201ULL; +- writeq(val64, &bar0->rts_qos_steering); +- break; ++ if (config->rx_steering_type && ++ config->rx_steering_type != RX_TOS_STEERING) { ++ val64 = 0x0180014001200110ULL; ++ writeq(val64, &bar0->rts_p0_p3_map); ++ val64 = 0x0108010401020101ULL; ++ writeq(val64, &bar0->rts_p4_p7_map); ++ val64 = 0x0001020304050607ULL; ++ } else ++ val64 = 0x8040201008040201ULL; ++ ++ break; ++ } ++ writeq(val64, &bar0->rts_qos_steering); ++ ++ if (nic->device_type == XFRAME_II_DEVICE ++ && (nic->device_sub_type == XFRAME_E_DEVICE)) { ++ fix_rldram(nic); ++ fix_rldram_qdr(nic); + } + + /* UDP Fix */ +@@ -1672,7 +2865,7 @@ + + /* Set the default rts frame length for the rings configured */ + val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22); +- for (i = 0 ; i < config->rx_ring_num ; i++) ++ for (i = 0; i < config->rx_ring_num; i++) + writeq(val64, &bar0->rts_frm_len_n[i]); + + /* Set the frame length for the configured rings +@@ -1685,20 +2878,40 @@ + * the rts_frm_len register for those values or else + * leave it as it is. + */ +- if (rts_frm_len[i] != 0) { ++ if (rts_frm_len[i] != 0) + writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]), + &bar0->rts_frm_len_n[i]); +- } +- } +- +- /* Disable differentiated services steering logic */ +- for (i = 0; i < 64; i++) { ++ } ++ ++ /* ++ * Disable differentiated services steering logic ++ */ ++ for (i = 0; i < 64; i++) + if (rts_ds_steer(nic, i, 0) == FAILURE) { + DBG_PRINT(ERR_DBG, "%s: failed rts ds steering", + dev->name); + DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i); + return -ENODEV; + } ++ ++ /* ++ * Configuring DS steering ++ * MAP DS codepoints 0-7 to ring0-last ring, and codepoints 8-63 to last ring ++ */ ++ if (config->rx_steering_type == RX_TOS_STEERING) { ++ int ring_num = 0; ++ for (i = 0; i < 64; i++) { ++ ring_num = (i < 8) ? i : 7; ++ if (ring_num >= config->rx_ring_num) ++ ring_num = config->rx_ring_num - 1; ++ ++ if (rts_ds_steer(nic, i, ring_num) == FAILURE) { ++ DBG_PRINT(ERR_DBG, "%s: failed rts ds steering", ++ dev->name); ++ DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i); ++ return -ENODEV; ++ } ++ } + } + + /* Program statistics memory */ +@@ -1726,57 +2939,21 @@ + if (SUCCESS != init_tti(nic, nic->last_link_state)) + return -ENODEV; + +- /* RTI Initialization */ +- if (nic->device_type == XFRAME_II_DEVICE) { +- /* +- * Programmed to generate Apprx 500 Intrs per +- * second +- */ +- int count = (nic->config.bus_speed * 125)/4; +- val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count); +- } else +- val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF); +- val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) | +- RTI_DATA1_MEM_RX_URNG_B(0x10) | +- RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN; +- +- writeq(val64, &bar0->rti_data1_mem); +- +- val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) | +- RTI_DATA2_MEM_RX_UFC_B(0x2) ; +- if (nic->config.intr_type == MSI_X) +- val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \ +- RTI_DATA2_MEM_RX_UFC_D(0x40)); +- else +- val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \ +- RTI_DATA2_MEM_RX_UFC_D(0x80)); +- writeq(val64, &bar0->rti_data2_mem); +- +- for (i = 0; i < config->rx_ring_num; i++) { +- val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD +- | RTI_CMD_MEM_OFFSET(i); +- writeq(val64, &bar0->rti_command_mem); +- +- /* +- * Once the operation completes, the Strobe bit of the +- * command register will be reset. We poll for this +- * particular condition. We wait for a maximum of 500ms +- * for the operation to complete, if it's not complete +- * by then we return error. +- */ +- time = 0; +- while (TRUE) { +- val64 = readq(&bar0->rti_command_mem); +- if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) +- break; +- +- if (time > 10) { +- DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n", +- dev->name); +- return -ENODEV; +- } +- time++; +- msleep(50); ++ /* Initialize RTI */ ++ if (SUCCESS != init_rti(nic)) ++ return -ENODEV; ++ ++ /* Configure RTH */ ++ if ((config->rx_steering_type) && ++ (config->rx_steering_type != RX_TOS_STEERING) && ++ (config->rx_steering_type != RX_VLAN_STEERING)) ++ s2io_rth_configure(nic); ++ ++ /* Configure VLAN ID steering */ ++ if (config->rx_steering_type == RX_VLAN_STEERING) { ++ for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) { ++ if (S2IO_INVALID_RING != nic->vlan_array[i]) ++ rts_vid_steer(nic, i, nic->vlan_array[i], 1); + } + } + +@@ -1863,10 +3040,10 @@ + */ + if (nic->device_type == XFRAME_II_DEVICE) { + val64 = FAULT_BEHAVIOUR | EXT_REQ_EN | +- MISC_LINK_STABILITY_PRD(3); ++ MISC_LINK_STABILITY_PRD(3); + writeq(val64, &bar0->misc_control); + val64 = readq(&bar0->pic_control2); +- val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15)); ++ val64 &= ~(S2BIT(13)|S2BIT(14)|S2BIT(15)); + writeq(val64, &bar0->pic_control2); + } + if (strstr(nic->product_name, "CX4")) { +@@ -1874,6 +3051,7 @@ + writeq(val64, &bar0->tmac_avg_ipg); + } + ++ nic->spdm_entry = 0; + return SUCCESS; + } + #define LINK_UP_DOWN_INTERRUPT 1 +@@ -1902,7 +3080,7 @@ + + temp64 = readq(addr); + +- if(flag == ENABLE_INTRS) ++ if (flag == ENABLE_INTRS) + temp64 &= ~((u64) value); + else + temp64 |= ((u64) value); +@@ -1913,9 +3091,9 @@ + { + struct XENA_dev_config __iomem *bar0 = nic->bar0; + register u64 gen_int_mask = 0; +- u64 interruptible; +- +- writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask); ++ ++ writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); ++ + if (mask & TX_DMA_INTR) { + + gen_int_mask |= TXDMA_INT_M; +@@ -2002,20 +3180,18 @@ + } + + if (mask & RX_MAC_INTR) { +- gen_int_mask |= RXMAC_INT_M; +- do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag, +- &bar0->mac_int_mask); +- interruptible = RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR | ++ u64 interruptible = RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR | + RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR | + RMAC_DOUBLE_ECC_ERR; + if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) + interruptible |= RMAC_LINK_STATE_CHANGE_INT; +- do_s2io_write_bits(interruptible, +- flag, &bar0->mac_rmac_err_mask); +- } +- +- if (mask & RX_XGXS_INTR) +- { ++ gen_int_mask |= RXMAC_INT_M; ++ do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag, ++ &bar0->mac_int_mask); ++ do_s2io_write_bits(interruptible, flag, &bar0->mac_rmac_err_mask); ++ } ++ ++ if (mask & RX_XGXS_INTR) { + gen_int_mask |= RXXGXS_INT_M; + do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag, + &bar0->xgxs_int_mask); +@@ -2025,7 +3201,8 @@ + + if (mask & MC_INTR) { + gen_int_mask |= MC_INT_M; +- do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask); ++ do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, ++ &bar0->mc_int_mask); + do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG | + MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag, + &bar0->mc_err_mask); +@@ -2035,6 +3212,7 @@ + /* Remove this line when alarm interrupts are enabled */ + nic->general_int_mask = 0; + } ++ + /** + * en_dis_able_nic_intrs - Enable or Disable the interrupts + * @nic: device private variable, +@@ -2057,7 +3235,7 @@ + /* PIC Interrupts */ + if (mask & TX_PIC_INTR) { + /* Enable PIC Intrs in the general intr mask register */ +- intr_mask |= TXPIC_INT_M; ++ intr_mask |= TXPIC_INT_M ; + if (flag == ENABLE_INTRS) { + /* + * If Hercules adapter enable GPIO otherwise +@@ -2124,12 +3302,12 @@ + + nic->general_int_mask = readq(&bar0->general_int_mask); + } +- + /** + * verify_pcc_quiescent- Checks for PCC quiescent state + * Return: 1 If PCC is quiescence + * 0 If PCC is not quiescence + */ ++ + static int verify_pcc_quiescent(struct s2io_nic *sp, int flag) + { + int ret = 0, herc; +@@ -2139,7 +3317,7 @@ + herc = (sp->device_type == XFRAME_II_DEVICE); + + if (flag == FALSE) { +- if ((!herc && (sp->pdev->revision >= 4)) || herc) { ++ if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) { + if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE)) + ret = 1; + } else { +@@ -2147,7 +3325,7 @@ + ret = 1; + } + } else { +- if ((!herc && (sp->pdev->revision >= 4)) || herc) { ++ if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) { + if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == + ADAPTER_STATUS_RMAC_PCC_IDLE)) + ret = 1; +@@ -2160,6 +3338,7 @@ + + return ret; + } ++ + /** + * verify_xena_quiescence - Checks whether the H/W is ready + * Description: Returns whether the H/W is ready to go or not. Depending +@@ -2169,7 +3348,6 @@ + * Return: 1 If xena is quiescence + * 0 If Xena is not quiescence + */ +- + static int verify_xena_quiescence(struct s2io_nic *sp) + { + int mode; +@@ -2182,7 +3360,7 @@ + return 0; + } + if (!(val64 & ADAPTER_STATUS_RDMA_READY)) { +- DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!"); ++ DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!"); + return 0; + } + if (!(val64 & ADAPTER_STATUS_PFC_READY)) { +@@ -2209,35 +3387,37 @@ + DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!"); + return 0; + } +- +- /* +- * In PCI 33 mode, the P_PLL is not used, and therefore, +- * the the P_PLL_LOCK bit in the adapter_status register will +- * not be asserted. +- */ ++ /* ++ * In PCI 33 mode, the P_PLL is not used, and therefore, ++ * the the P_PLL_LOCK bit in the adapter_status register will ++ * not be asserted. ++ */ + if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) && +- sp->device_type == XFRAME_II_DEVICE && mode != +- PCI_MODE_PCI_33) { +- DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!"); +- return 0; +- } +- if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == +- ADAPTER_STATUS_RC_PRC_QUIESCENT)) { +- DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!"); +- return 0; +- } ++ (sp->device_type == XFRAME_II_DEVICE) && ++ (mode != PCI_MODE_PCI_33)) { ++ DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!"); ++ return 0; ++ } ++ /* RC_PRC bit is only valid when ADAPTER_EN is not asserted */ ++ if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) ++ if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ++ == ADAPTER_STATUS_RC_PRC_QUIESCENT)) { ++ DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!"); ++ return 0; ++ } ++ + return 1; + } + + /** +- * fix_mac_address - Fix for Mac addr problem on Alpha platforms +- * @sp: Pointer to device specifc structure +- * Description : +- * New procedure to clear mac address reading problems on Alpha platforms +- * +- */ +- +-static void fix_mac_address(struct s2io_nic * sp) ++* fix_mac_address - Fix for Mac addr problem on Alpha platforms ++* @sp: Pointer to device specifc structure ++* Description : ++* New procedure to clear mac address reading problems on Alpha platforms ++* ++*/ ++ ++static void fix_mac_address(struct s2io_nic *sp) + { + struct XENA_dev_config __iomem *bar0 = sp->bar0; + u64 val64; +@@ -2249,6 +3429,53 @@ + val64 = readq(&bar0->gpio_control); + } + } ++ ++/* ++* fix_rldram ++* Description: ++* For XFrame II devices, causes the MC test controller ++* to issue 4 reads to all rldram banks which cause the ++* memory to reset. This works around issues seen with ++* rldram ram. Once out of test mode, you can not return. ++* Assumes the following register are hardware defaults or ++* are set by flash ++* MC_RLDRAM_GENERATION 0000_0100_0000_0000 ++* MC_RLDRAM_MRS_HERC 0003_5700_0301_0300 ++* ++*/ ++static void fix_rldram(struct s2io_nic * sp) ++{ ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ ++ /* Put in test mode */ ++ writeq(0x0000000000010000ULL, &bar0->mc_rldram_test_ctrl); ++ /* Disable ODT to fix 0xFF failures */ ++ writeq(0x0003560003010300ULL, &bar0->mc_rldram_mrs_herc); ++ /* Remove out of test mode */ ++ writeq(0x0000000000000000ULL, &bar0->mc_rldram_test_ctrl); ++ ++ return; ++} ++ ++/* ++ * fix_rldram_qdr ++ * Description: ++ * MC_QDR_CTRL 0x0001_0101_0101_0100 instead change value to 0101_0101_0101_0100 ++ * ++ */ ++ static void fix_rldram_qdr(struct s2io_nic *sp) ++ { ++ u64 val64 = 0; ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ ++ val64 = readq(&bar0->mc_qdr_ctrl); ++ val64 |= S2BIT(7); ++ writeq(val64, &bar0->mc_qdr_ctrl); ++ ++ /* Read back to flush */ ++ val64 = readq(&bar0->mc_qdr_ctrl); ++ return; ++ } + + /** + * start_nic - Turns the device on +@@ -2281,10 +3508,16 @@ + &bar0->prc_rxd0_n[i]); + + val64 = readq(&bar0->prc_ctrl_n[i]); ++ + if (nic->rxd_mode == RXD_MODE_1) + val64 |= PRC_CTRL_RC_ENABLED; +- else +- val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3; ++ else if (nic->rxd_mode == RXD_MODE_5) ++ val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_5 | ++ PRC_CTRL_RTH_DISABLE; ++ else ++ val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3 | ++ PRC_CTRL_RTH_DISABLE; ++ + if (nic->device_type == XFRAME_II_DEVICE) + val64 |= PRC_CTRL_GROUP_READS; + val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF); +@@ -2299,11 +3532,12 @@ + writeq(val64, &bar0->rx_pa_cfg); + } + +- if (vlan_tag_strip == 0) { ++ s2io_handle_vlan_tag_strip(nic, nic->vlan_strip_flag); ++ ++ if (nic->device_type == XFRAME_II_DEVICE) { + val64 = readq(&bar0->rx_pa_cfg); +- val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG; ++ val64 |= RX_PA_CFG_UDP_ZERO_CS_EN; + writeq(val64, &bar0->rx_pa_cfg); +- vlan_strip_flag = 0; + } + + /* +@@ -2372,7 +3606,7 @@ + * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb + */ + static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \ +- TxD *txdlp, int get_off) ++TxD *txdlp, int get_off) + { + struct s2io_nic *nic = fifo_data->nic; + struct sk_buff *skb; +@@ -2380,12 +3614,14 @@ + u16 j, frg_cnt; + + txds = txdlp; ++#ifdef NETIF_F_UFO + if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) { + pci_unmap_single(nic->pdev, (dma_addr_t) + txds->Buffer_Pointer, sizeof(u64), + PCI_DMA_TODEVICE); + txds++; + } ++#endif + + skb = (struct sk_buff *) ((unsigned long) + txds->Host_Control); +@@ -2409,7 +3645,7 @@ + frag->size, PCI_DMA_TODEVICE); + } + } +- memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds)); ++ memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds)); + return(skb); + } + +@@ -2430,20 +3666,22 @@ + struct mac_info *mac_control; + struct config_param *config; + int cnt = 0; ++ struct txFifoStat *stats; + + mac_control = &nic->mac_control; + config = &nic->config; + + for (i = 0; i < config->tx_fifo_num; i++) { + unsigned long flags; ++ stats = nic->mac_control.fifos[i].tx_fifo_stat; ++ + spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags); + for (j = 0; j < config->tx_cfg[i].fifo_len; j++) { +- txdp = (struct TxD *) \ +- mac_control->fifos[i].list_info[j].list_virt_addr; ++ txdp = (struct TxD *) mac_control->fifos[i]. ++ list_info[j].list_virt_addr; + skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j); + if (skb) { +- nic->mac_control.stats_info->sw_stat.mem_freed +- += skb->truesize; ++ stats->tx_mem_freed += skb->truesize; + dev_kfree_skb(skb); + cnt++; + } +@@ -2472,11 +3710,6 @@ + struct XENA_dev_config __iomem *bar0 = nic->bar0; + register u64 val64 = 0; + u16 interruptible; +- struct mac_info *mac_control; +- struct config_param *config; +- +- mac_control = &nic->mac_control; +- config = &nic->config; + + /* Disable all interrupts */ + en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS); +@@ -2490,20 +3723,170 @@ + writeq(val64, &bar0->adapter_control); + } + ++static int fill_rxd_5buf(struct ring_info *ring, struct RxD5 *rxdp, ++struct sk_buff *skb, int ring_no, int rxd_index) ++{ ++ struct sk_buff *frag_list = NULL; ++ u64 tmp; ++ struct rxRingStat *stats = ring->rx_ring_stat; ++ dma_addr_t dma_handle; ++ ++ /* Buffer-1 receives L3/L4 headers */ ++ dma_handle = pci_map_single ++ (ring->pdev, skb->data, l3l4hdr_size + 4, ++ PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(dma_handle)) ++ return -ENOMEM; ++ ++ ((struct RxD5 *)rxdp)->Buffer1_ptr = dma_handle; ++ ++ /* skb_shinfo(skb)->frag_list will have L4 data payload */ ++ skb_shinfo(skb)->frag_list = ++ netdev_alloc_skb(ring->dev, MODE5_BUF_SIZE + ALIGN_SIZE); ++ if (skb_shinfo(skb)->frag_list == NULL) { ++ stats->rx_mem_alloc_fail_cnt++; ++ goto unmap_buf1; ++ } ++ frag_list = skb_shinfo(skb)->frag_list; ++ skb->truesize += frag_list->truesize; /* updating skb->truesize */ ++ stats->rx_mem_allocated += frag_list->truesize; ++ frag_list->next = NULL; ++ ++ /*Align the RxD on 128 byte boundary */ ++ tmp = (u64)(unsigned long) frag_list->data; ++ tmp += ALIGN_SIZE; ++ tmp &= ~ALIGN_SIZE; ++ frag_list->data = (void *) (unsigned long)tmp; ++ S2IO_SKB_INIT_TAIL(frag_list, tmp); ++ ++ dma_handle = pci_map_single(ring->pdev, ++ frag_list->data, MODE5_BUF_SIZE, ++ PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(dma_handle)) ++ goto unmap_buf1; ++ ++ rxdp->Buffer2_ptr = dma_handle; ++ ++ rxdp->Control_3 &= (~MASK_BUFFER3_SIZE_5); ++ if (ring->skbs_per_rxd > 2) { ++ /* Allocate and map buffer3 */ ++ frag_list->next = netdev_alloc_skb(ring->dev, ++ MODE5_BUF_SIZE + ALIGN_SIZE); ++ if (frag_list->next == NULL) { ++ stats->rx_mem_alloc_fail_cnt++; ++ goto unmap_buf2; ++ } ++ ++ frag_list = frag_list->next; ++ skb->truesize += frag_list->truesize; /*updating skb->truesize*/ ++ stats->rx_mem_allocated += frag_list->truesize; ++ frag_list->next = NULL; ++ ++ /*Align the RxD on 128 byte boundary */ ++ tmp = (u64)(unsigned long) frag_list->data; ++ tmp += ALIGN_SIZE; ++ tmp &= ~ALIGN_SIZE; ++ frag_list->data = (void *) (unsigned long)tmp; ++ S2IO_SKB_INIT_TAIL(frag_list, tmp); ++ ++ dma_handle = pci_map_single(ring->pdev, ++ frag_list->data, MODE5_BUF_SIZE, ++ PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(dma_handle)) { ++ frag_list = skb_shinfo(skb)->frag_list; ++ goto unmap_buf2; ++ } ++ ++ rxdp->Buffer3_ptr = dma_handle; ++ rxdp->Control_3 |= SET_BUFFER3_SIZE_5(MODE5_BUF_SIZE); ++ } else { ++ rxdp->Buffer3_ptr = rxdp->Buffer2_ptr; ++ rxdp->Control_3 |= SET_BUFFER3_SIZE_5(1); ++ } ++ ++ rxdp->Control_3 &= (~MASK_BUFFER4_SIZE_5); ++ if (ring->skbs_per_rxd > 3) { ++ /* Allocate and map buffer4 */ ++ frag_list->next = netdev_alloc_skb(ring->dev, ++ MODE5_BUF_SIZE + ALIGN_SIZE); ++ if (frag_list->next == NULL) { ++ stats->rx_mem_alloc_fail_cnt++; ++ frag_list = skb_shinfo(skb)->frag_list; ++ goto unmap_buf3; ++ } ++ ++ frag_list = frag_list->next; ++ skb->truesize += frag_list->truesize; /*updating skb->truesize*/ ++ stats->rx_mem_allocated += frag_list->truesize; ++ frag_list->next = NULL; ++ ++ /*Align the RxD on 128 byte boundary */ ++ tmp = (u64)(unsigned long) frag_list->data; ++ tmp += ALIGN_SIZE; ++ tmp &= ~ALIGN_SIZE; ++ frag_list->data = (void *) (unsigned long)tmp; ++ S2IO_SKB_INIT_TAIL(frag_list, tmp); ++ ++ dma_handle = pci_map_single(ring->pdev, ++ frag_list->data, MODE5_BUF_SIZE, ++ PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(dma_handle)) { ++ frag_list = skb_shinfo(skb)->frag_list; ++ goto unmap_buf3; ++ } ++ ++ rxdp->Buffer4_ptr = dma_handle; ++ rxdp->Control_3 |= SET_BUFFER4_SIZE_5(MODE5_BUF_SIZE); ++ } else { ++ rxdp->Buffer4_ptr = rxdp->Buffer3_ptr; ++ rxdp->Control_3 |= SET_BUFFER4_SIZE_5(1); ++ } ++ ++ /* Update the buffer sizes */ ++ rxdp->Control_2 &= (~MASK_BUFFER0_SIZE_5); ++ rxdp->Control_2 |= SET_BUFFER0_SIZE_5(BUF0_LEN); ++ rxdp->Control_2 &= (~MASK_BUFFER1_SIZE_5); ++ rxdp->Control_2 |= SET_BUFFER1_SIZE_5(l3l4hdr_size + 4); ++ rxdp->Control_2 &= (~MASK_BUFFER2_SIZE_5); ++ rxdp->Control_2 |= SET_BUFFER2_SIZE_5(MODE5_BUF_SIZE); ++ ++ rxdp->Host_Control = rxd_index; ++ ring->skbs[rxd_index] = (unsigned long) (skb); ++ return SUCCESS; ++ ++unmap_buf3: ++ stats->rx_pci_map_fail_cnt++; ++ pci_unmap_single(ring->pdev, ++ (dma_addr_t)(unsigned long)frag_list->next->data, ++ MODE5_BUF_SIZE, PCI_DMA_FROMDEVICE); ++unmap_buf2: ++ stats->rx_pci_map_fail_cnt++; ++ pci_unmap_single(ring->pdev, ++ (dma_addr_t)(unsigned long)frag_list->data, ++ MODE5_BUF_SIZE, PCI_DMA_FROMDEVICE); ++unmap_buf1: ++ stats->rx_pci_map_fail_cnt++; ++ pci_unmap_single(ring->pdev, ++ (dma_addr_t)(unsigned long)skb->data, l3l4hdr_size + 4, ++ PCI_DMA_FROMDEVICE); ++ return -ENOMEM ; ++} ++ ++ + /** + * fill_rx_buffers - Allocates the Rx side skbs +- * @ring_info: per ring structure ++ * @nic: device private variable ++ * @ring_no: ring number + * @from_card_up: If this is true, we will map the buffer to get + * the dma address for buf0 and buf1 to give it to the card. +- * Else we will sync the already mapped buffer to give it to the card. ++ * Else we will sync the already mapped buffer to give it to the card + * Description: + * The function allocates Rx side skbs and puts the physical + * address of these buffers into the RxD buffer pointers, so that the NIC + * can DMA the received frame into these locations. +- * The NIC supports 3 receive modes, viz ++ * The NIC supports 2 receive modes, viz + * 1. single buffer, +- * 2. three buffer and +- * 3. Five buffer modes. ++ * 2. Five buffer modes. + * Each mode defines how many fragments the received frame will be split + * up into by the NIC. The frame is split into L3 header, L4 Header, + * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself +@@ -2512,29 +3895,29 @@ + * Return Value: + * SUCCESS on success or an appropriate -ve value on failure. + */ +-static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring, +- int from_card_up) +-{ +- struct sk_buff *skb; +- struct RxD_t *rxdp; ++ ++static int fill_rx_buffers(struct ring_info *ring, int from_card_up) ++{ ++ struct sk_buff *skb = NULL; ++ struct RxD_t *rxdp = NULL; + int off, size, block_no, block_no1; + u32 alloc_tab = 0; + u32 alloc_cnt; + u64 tmp; +- struct buffAdd *ba; ++ struct buffAdd *ba = NULL; + struct RxD_t *first_rxdp = NULL; + u64 Buffer0_ptr = 0, Buffer1_ptr = 0; + int rxd_index = 0; + struct RxD1 *rxdp1; + struct RxD3 *rxdp3; +- struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat; ++ struct RxD5 *rxdp5; ++ struct rxRingStat *stats = ring->rx_ring_stat; + + alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left; + + block_no1 = ring->rx_curr_get_info.block_index; + while (alloc_tab < alloc_cnt) { + block_no = ring->rx_curr_put_info.block_index; +- + off = ring->rx_curr_put_info.offset; + + rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr; +@@ -2551,7 +3934,8 @@ + DBG_PRINT(INTR_DBG, " info equated\n"); + goto end; + } +- if (off && (off == ring->rxd_count)) { ++ ++ if (off == ring->rxd_count) { + ring->rx_curr_put_info.block_index++; + if (ring->rx_curr_put_info.block_index == + ring->block_count) +@@ -2562,25 +3946,27 @@ + rxdp = ring->rx_blocks[block_no].block_virt_addr; + DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n", + ring->dev->name, rxdp); +- + } + + if ((rxdp->Control_1 & RXD_OWN_XENA) && + ((ring->rxd_mode == RXD_MODE_3B) && +- (rxdp->Control_2 & s2BIT(0)))) { ++ (rxdp->Control_2 & S2BIT(0)))) { + ring->rx_curr_put_info.offset = off; + goto end; + } ++ + /* calculate size of skb based on ring mode */ + size = ring->mtu + HEADER_ETHERNET_II_802_3_SIZE + + HEADER_802_2_SIZE + HEADER_SNAP_SIZE; + if (ring->rxd_mode == RXD_MODE_1) + size += NET_IP_ALIGN; +- else ++ else if (ring->rxd_mode == RXD_MODE_3B) + size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4; ++ else ++ size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4; + + /* allocate skb */ +- skb = dev_alloc_skb(size); ++ skb = netdev_alloc_skb(ring->dev, size); + if(!skb) { + DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name); + DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n"); +@@ -2588,103 +3974,125 @@ + wmb(); + first_rxdp->Control_1 |= RXD_OWN_XENA; + } +- stats->mem_alloc_fail_cnt++; +- ++ stats->rx_mem_alloc_fail_cnt++; + return -ENOMEM ; + } +- stats->mem_allocated += skb->truesize; +- ++ stats->rx_mem_allocated += skb->truesize; + if (ring->rxd_mode == RXD_MODE_1) { + /* 1 buffer mode - normal operation mode */ +- rxdp1 = (struct RxD1*)rxdp; ++ rxdp1 = (struct RxD1 *)rxdp; + memset(rxdp, 0, sizeof(struct RxD1)); + skb_reserve(skb, NET_IP_ALIGN); ++ + rxdp1->Buffer0_ptr = pci_map_single +- (ring->pdev, skb->data, size - NET_IP_ALIGN, +- PCI_DMA_FROMDEVICE); +- if (pci_dma_mapping_error(nic->pdev, +- rxdp1->Buffer0_ptr)) ++ (ring->pdev, skb->data, size - NET_IP_ALIGN, ++ PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(rxdp1->Buffer0_ptr)) + goto pci_map_failed; + + rxdp->Control_2 = + SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN); + rxdp->Host_Control = (unsigned long) (skb); +- } else if (ring->rxd_mode == RXD_MODE_3B) { ++ } else if (ring->rxd_mode >= RXD_MODE_3B) { + /* + * 2 buffer mode - + * 2 buffer mode provides 128 + * byte aligned receive buffers. +- */ +- +- rxdp3 = (struct RxD3*)rxdp; +- /* save buffer pointers to avoid frequent dma mapping */ ++ * ++ */ ++ ba = &ring->ba[block_no][off]; ++ ++ rxdp3 = (struct RxD3 *)rxdp; ++ rxdp5 = (struct RxD5 *)rxdp; ++ /* save the buffer pointers to avoid frequent ++ * dma mapping ++ */ + Buffer0_ptr = rxdp3->Buffer0_ptr; + Buffer1_ptr = rxdp3->Buffer1_ptr; +- memset(rxdp, 0, sizeof(struct RxD3)); ++ if (ring->rxd_mode == RXD_MODE_5) ++ memset(rxdp, 0, sizeof(struct RxD5)); ++ else ++ memset(rxdp, 0, sizeof(struct RxD3)); + /* restore the buffer pointers for dma sync*/ + rxdp3->Buffer0_ptr = Buffer0_ptr; + rxdp3->Buffer1_ptr = Buffer1_ptr; +- +- ba = &ring->ba[block_no][off]; + skb_reserve(skb, BUF0_LEN); + tmp = (u64)(unsigned long) skb->data; + tmp += ALIGN_SIZE; + tmp &= ~ALIGN_SIZE; + skb->data = (void *) (unsigned long)tmp; +- skb_reset_tail_pointer(skb); ++ S2IO_SKB_INIT_TAIL(skb, tmp); + + if (from_card_up) { + rxdp3->Buffer0_ptr = +- pci_map_single(ring->pdev, ba->ba_0, ++ pci_map_single(ring->pdev, ba->ba_0, ++ BUF0_LEN, PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(rxdp3->Buffer0_ptr)) ++ goto pci_map_failed; ++ } else { ++ /* Sync the buffer to give it back to the card.*/ ++ pci_dma_sync_single_for_device(ring->pdev, ++ (dma_addr_t) rxdp3->Buffer0_ptr, + BUF0_LEN, PCI_DMA_FROMDEVICE); +- if (pci_dma_mapping_error(nic->pdev, +- rxdp3->Buffer0_ptr)) ++ } ++ ++ if (ring->rxd_mode == RXD_MODE_5) { ++ if (fill_rxd_5buf(ring, rxdp5, skb, ++ ring->ring_no, rxd_index) == -ENOMEM) { ++ stats->rx_mem_freed += skb->truesize; ++ dev_kfree_skb_irq(skb); ++ if (first_rxdp) { ++ wmb(); ++ first_rxdp->Control_1 |= ++ RXD_OWN_XENA; ++ } ++ return -ENOMEM ; ++ } ++ } else { ++ /* Two buffer mode */ ++ ++ rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN); ++ ++ /* ++ *Buffer2 will have L3/L4 header plus ++ * L4 payload ++ */ ++ ++ rxdp3->Buffer2_ptr = ++ pci_map_single(ring->pdev, ++ skb->data, ++ ring->mtu + 4, ++ PCI_DMA_FROMDEVICE); ++ ++ if (pci_dma_mapping_error(rxdp3->Buffer2_ptr)) + goto pci_map_failed; +- } else +- pci_dma_sync_single_for_device(ring->pdev, +- (dma_addr_t) rxdp3->Buffer0_ptr, +- BUF0_LEN, PCI_DMA_FROMDEVICE); +- +- rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN); +- if (ring->rxd_mode == RXD_MODE_3B) { +- /* Two buffer mode */ +- +- /* +- * Buffer2 will have L3/L4 header plus +- * L4 payload +- */ +- rxdp3->Buffer2_ptr = pci_map_single +- (ring->pdev, skb->data, ring->mtu + 4, +- PCI_DMA_FROMDEVICE); +- +- if (pci_dma_mapping_error(nic->pdev, +- rxdp3->Buffer2_ptr)) +- goto pci_map_failed; +- ++ ++ /* Buffer-1 will be dummy buffer */ + if (from_card_up) { + rxdp3->Buffer1_ptr = +- pci_map_single(ring->pdev, ++ pci_map_single(ring->pdev, + ba->ba_1, BUF1_LEN, + PCI_DMA_FROMDEVICE); + +- if (pci_dma_mapping_error(nic->pdev, +- rxdp3->Buffer1_ptr)) { +- pci_unmap_single +- (ring->pdev, ++ if (pci_dma_mapping_error(rxdp3->Buffer1_ptr)) { ++ pci_unmap_single(ring->pdev, + (dma_addr_t)(unsigned long) + skb->data, +- ring->mtu + 4, +- PCI_DMA_FROMDEVICE); ++ ring->mtu + 4, ++ PCI_DMA_FROMDEVICE); + goto pci_map_failed; + } + } +- rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1); +- rxdp->Control_2 |= SET_BUFFER2_SIZE_3 +- (ring->mtu + 4); +- } +- rxdp->Control_2 |= s2BIT(0); +- rxdp->Host_Control = (unsigned long) (skb); +- } ++ ++ rxdp->Control_2 |= ++ SET_BUFFER1_SIZE_3(1); ++ rxdp->Control_2 |= ++ SET_BUFFER2_SIZE_3(ring->mtu + 4); ++ ++ rxdp->Host_Control = (unsigned long) (skb); ++ } ++ } ++ + if (alloc_tab & ((1 << rxsync_frequency) - 1)) + rxdp->Control_1 |= RXD_OWN_XENA; + off++; +@@ -2704,7 +4112,7 @@ + alloc_tab++; + } + +- end: ++end: + /* Transfer ownership of first descriptor to adapter just before + * exiting. Before that, use memory barrier so that ownership + * and other fields are seen by adapter correctly. +@@ -2716,63 +4124,93 @@ + + return SUCCESS; + pci_map_failed: +- stats->pci_map_fail_cnt++; +- stats->mem_freed += skb->truesize; ++ stats->rx_pci_map_fail_cnt++; ++ stats->rx_mem_freed += skb->truesize; + dev_kfree_skb_irq(skb); + return -ENOMEM; + } + +-static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk) +-{ +- struct net_device *dev = sp->dev; ++static void free_rxd_blk(struct ring_info *ring, int blk) ++{ + int j; + struct sk_buff *skb; + struct RxD_t *rxdp; +- struct mac_info *mac_control; +- struct buffAdd *ba; + struct RxD1 *rxdp1; + struct RxD3 *rxdp3; +- +- mac_control = &sp->mac_control; +- for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) { +- rxdp = mac_control->rings[ring_no]. +- rx_blocks[blk].rxds[j].virt_addr; +- skb = (struct sk_buff *) +- ((unsigned long) rxdp->Host_Control); +- if (!skb) { ++ struct RxD5 *rxdp5; ++ struct rxRingStat *stats = ring->rx_ring_stat; ++ ++ for (j = 0 ; j < rxd_count[ring->rxd_mode]; j++) { ++ rxdp = ring->rx_blocks[blk].rxds[j].virt_addr; ++ if (ring->rxd_mode == RXD_MODE_5) { ++ rxdp5 = (struct RxD5 *)rxdp; ++ skb = (struct sk_buff *) ++ ((unsigned long)ring-> ++ skbs[((u64) rxdp5->Host_Control)]); ++ } else ++ skb = (struct sk_buff *) ++ ((unsigned long) rxdp->Host_Control); ++ ++ if (!skb) + continue; +- } +- if (sp->rxd_mode == RXD_MODE_1) { +- rxdp1 = (struct RxD1*)rxdp; +- pci_unmap_single(sp->pdev, (dma_addr_t) ++ ++ switch (ring->rxd_mode) { ++ case RXD_MODE_1: ++ rxdp1 = (struct RxD1 *)rxdp; ++ pci_unmap_single(ring->pdev, (dma_addr_t) + rxdp1->Buffer0_ptr, +- dev->mtu + +- HEADER_ETHERNET_II_802_3_SIZE +- + HEADER_802_2_SIZE + +- HEADER_SNAP_SIZE, +- PCI_DMA_FROMDEVICE); +- memset(rxdp, 0, sizeof(struct RxD1)); +- } else if(sp->rxd_mode == RXD_MODE_3B) { +- rxdp3 = (struct RxD3*)rxdp; +- ba = &mac_control->rings[ring_no]. +- ba[blk][j]; +- pci_unmap_single(sp->pdev, (dma_addr_t) ++ ring->mtu + HEADER_ETHERNET_II_802_3_SIZE + ++ HEADER_802_2_SIZE + HEADER_SNAP_SIZE, ++ PCI_DMA_FROMDEVICE); ++ memset(rxdp, 0, sizeof(struct RxD1)); ++ break; ++ ++ case RXD_MODE_5: ++ rxdp5 = (struct RxD5 *)rxdp; ++ pci_unmap_single(ring->pdev, (dma_addr_t) ++ rxdp5->Buffer0_ptr, ++ BUF0_LEN, ++ PCI_DMA_FROMDEVICE); ++ pci_unmap_single(ring->pdev, (dma_addr_t) ++ rxdp5->Buffer1_ptr, ++ l3l4hdr_size + 4, ++ PCI_DMA_FROMDEVICE); ++ pci_unmap_single(ring->pdev, (dma_addr_t) ++ rxdp5->Buffer2_ptr, ++ MODE5_BUF_SIZE, ++ PCI_DMA_FROMDEVICE); ++ if (ring->skbs_per_rxd > 2) ++ pci_unmap_single(ring->pdev, (dma_addr_t) ++ rxdp5->Buffer3_ptr, ++ MODE5_BUF_SIZE, ++ PCI_DMA_FROMDEVICE); ++ if (ring->skbs_per_rxd > 3) ++ pci_unmap_single(ring->pdev, (dma_addr_t) ++ rxdp5->Buffer4_ptr, ++ MODE5_BUF_SIZE, ++ PCI_DMA_FROMDEVICE); ++ memset(rxdp, 0, sizeof(struct RxD5)); ++ break; ++ ++ case RXD_MODE_3B: ++ rxdp3 = (struct RxD3 *)rxdp; ++ pci_unmap_single(ring->pdev, (dma_addr_t) + rxdp3->Buffer0_ptr, + BUF0_LEN, + PCI_DMA_FROMDEVICE); +- pci_unmap_single(sp->pdev, (dma_addr_t) ++ pci_unmap_single(ring->pdev, (dma_addr_t) + rxdp3->Buffer1_ptr, + BUF1_LEN, + PCI_DMA_FROMDEVICE); +- pci_unmap_single(sp->pdev, (dma_addr_t) ++ pci_unmap_single(ring->pdev, (dma_addr_t) + rxdp3->Buffer2_ptr, +- dev->mtu + 4, +- PCI_DMA_FROMDEVICE); ++ ring->mtu + 4, PCI_DMA_FROMDEVICE); + memset(rxdp, 0, sizeof(struct RxD3)); +- } +- sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize; ++ break; ++ } ++ stats->rx_mem_freed += skb->truesize; + dev_kfree_skb(skb); +- mac_control->rings[ring_no].rx_bufs_left -= 1; ++ ring->rx_bufs_left -= 1; + } + } + +@@ -2796,31 +4234,34 @@ + config = &sp->config; + + for (i = 0; i < config->rx_ring_num; i++) { ++ + for (blk = 0; blk < rx_ring_sz[i]; blk++) +- free_rxd_blk(sp,i,blk); ++ free_rxd_blk(&mac_control->rings[i], blk); + + mac_control->rings[i].rx_curr_put_info.block_index = 0; + mac_control->rings[i].rx_curr_get_info.block_index = 0; + mac_control->rings[i].rx_curr_put_info.offset = 0; + mac_control->rings[i].rx_curr_get_info.offset = 0; + mac_control->rings[i].rx_bufs_left = 0; ++ + DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n", + dev->name, buf_cnt, i); + } + } + +-static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring) +-{ +- if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) { +- DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name); ++static int s2io_chk_rx_buffers(struct ring_info *ring) ++{ ++ if (fill_rx_buffers(ring, 0) == -ENOMEM) { ++ DBG_PRINT(INFO_DBG, "%s - %s:Out of memory", __FUNCTION__, ++ ring->dev->name); + DBG_PRINT(INFO_DBG, " in Rx Intr!!\n"); + } + return 0; + } + + /** +- * s2io_poll - Rx interrupt handler for NAPI support +- * @napi : pointer to the napi structure. ++ * s2io_poll - Rx interrupt handler for New NAPI support ++ * @dev : pointer to the device structure. + * @budget : The number of packets that were budgeted to be processed + * during one pass through the 'Poll" function. + * Description: +@@ -2828,9 +4269,11 @@ + * the same thing that rx_intr_handler does, but not in a interrupt context + * also It will process only a given number of packets. + * Return value: +- * 0 on success and 1 if there are No Rx packets to be processed. +- */ +- ++ * No of Rx packets processed. ++ */ ++ ++#if defined(HAVE_NETDEV_POLL) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) + static int s2io_poll_msix(struct napi_struct *napi, int budget) + { + struct ring_info *ring = container_of(napi, struct ring_info, napi); +@@ -2838,9 +4281,8 @@ + struct config_param *config; + struct mac_info *mac_control; + int pkts_processed = 0; +- u8 __iomem *addr = NULL; +- u8 val8 = 0; +- struct s2io_nic *nic = dev->priv; ++ u8 __iomem *addr, val8; ++ struct s2io_nic *nic = s2io_netdev_priv(dev); + struct XENA_dev_config __iomem *bar0 = nic->bar0; + int budget_org = budget; + +@@ -2851,10 +4293,10 @@ + return 0; + + pkts_processed = rx_intr_handler(ring, budget); +- s2io_chk_rx_buffers(nic, ring); ++ s2io_chk_rx_buffers(ring); + + if (pkts_processed < budget_org) { +- netif_rx_complete(dev, napi); ++ s2io_netif_do_rx_complete(dev, napi); + /*Re Enable MSI-Rx Vector*/ + addr = (u8 __iomem *)&bar0->xmsi_mask_reg; + addr += 7 - ring->ring_no; +@@ -2868,7 +4310,7 @@ + { + struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi); + struct ring_info *ring; +- struct net_device *dev = nic->dev; ++ struct net_device *dev = nic->dev; + struct config_param *config; + struct mac_info *mac_control; + int pkts_processed = 0; +@@ -2885,20 +4327,100 @@ + for (i = 0; i < config->rx_ring_num; i++) { + ring = &mac_control->rings[i]; + ring_pkts_processed = rx_intr_handler(ring, budget); +- s2io_chk_rx_buffers(nic, ring); ++ s2io_chk_rx_buffers(ring); + pkts_processed += ring_pkts_processed; + budget -= ring_pkts_processed; + if (budget <= 0) + break; + } ++ + if (pkts_processed < budget_org) { +- netif_rx_complete(dev, napi); ++ s2io_netif_do_rx_complete(dev, napi); + /* Re enable the Rx interrupts for the ring */ + writeq(0, &bar0->rx_traffic_mask); + readl(&bar0->rx_traffic_mask); + } + return pkts_processed; + } ++#else ++/** ++ * s2io_poll - Rx interrupt handler for NAPI support ++ * @dev : pointer to the device structure. ++ * @budget : The number of packets that were budgeted to be processed ++ * during one pass through the 'Poll" function. ++ * Description: ++ * Comes into picture only if NAPI support has been incorporated. It does ++ * the same thing that rx_intr_handler does, but not in a interrupt context ++ * also It will process only a given number of packets. ++ * Return value: ++ * 0 on success and 1 if there are No Rx packets to be processed. ++ */ ++static int s2io_poll(struct net_device *dev, int *budget) ++{ ++ struct s2io_nic *nic = s2io_netdev_priv(dev); ++ int pkt_cnt = 0, org_pkts_to_process; ++ struct mac_info *mac_control; ++ struct config_param *config; ++ struct XENA_dev_config __iomem *bar0 = nic->bar0; ++ int i; ++ ++ if (unlikely(!is_s2io_card_up(nic))) ++ return 0; ++ ++ mac_control = &nic->mac_control; ++ config = &nic->config; ++ ++ nic->pkts_to_process = *budget; ++ if (nic->pkts_to_process > dev->quota) ++ nic->pkts_to_process = dev->quota; ++ org_pkts_to_process = nic->pkts_to_process; ++ ++ for (i = 0; i < config->rx_ring_num; i++) { ++ rx_intr_handler(&mac_control->rings[i], 0); ++ pkt_cnt = org_pkts_to_process - nic->pkts_to_process; ++ if (!nic->pkts_to_process) { ++ /* Quota for the current iteration has been met */ ++ goto no_rx; ++ } ++ } ++ ++ if (!pkt_cnt) ++ pkt_cnt = 1; ++ ++ dev->quota -= pkt_cnt; ++ *budget -= pkt_cnt; ++ s2io_netif_do_rx_complete(dev, NULL); ++ ++ for (i = 0; i < config->rx_ring_num; i++) ++ s2io_chk_rx_buffers(&mac_control->rings[i]); ++ ++ /* Re enable the Rx interrupts. */ ++ if (config->intr_type == MSI_X) { ++ u8 __iomem *addr; ++ u8 val8; ++ ++ addr = (u8 __iomem *)&bar0->xmsi_mask_reg; ++ addr += 7 - mac_control->rings[0].ring_no; ++ val8 = (mac_control->rings[0].ring_no == 0) ? 0x3f : 0xbf; ++ writeb(val8, addr); ++ val8 = readb(addr); ++ } ++ else { ++ writeq(0x0, &bar0->rx_traffic_mask); ++ readl(&bar0->rx_traffic_mask); ++ } ++ ++ return 0; ++no_rx: ++ dev->quota -= pkt_cnt; ++ *budget -= pkt_cnt; ++ ++ for (i = 0; i < config->rx_ring_num; i++) ++ s2io_chk_rx_buffers(&mac_control->rings[i]); ++ return 1; ++} ++#endif ++#endif + + #ifdef CONFIG_NET_POLL_CONTROLLER + /** +@@ -2912,15 +4434,16 @@ + */ + static void s2io_netpoll(struct net_device *dev) + { +- struct s2io_nic *nic = dev->priv; ++ struct s2io_nic *nic = s2io_netdev_priv(dev); + struct mac_info *mac_control; + struct config_param *config; + struct XENA_dev_config __iomem *bar0 = nic->bar0; + u64 val64 = 0xFFFFFFFFFFFFFFFFULL; + int i; +- ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) + if (pci_channel_offline(nic->pdev)) + return; ++#endif + + disable_irq(dev->irq); + +@@ -2942,9 +4465,9 @@ + rx_intr_handler(&mac_control->rings[i], 0); + + for (i = 0; i < config->rx_ring_num; i++) { +- if (fill_rx_buffers(nic, &mac_control->rings[i], 0) == +- -ENOMEM) { +- DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name); ++ if (fill_rx_buffers(&mac_control->rings[i], 0) == -ENOMEM) { ++ DBG_PRINT(INFO_DBG, "%s - %s:Out of memory", ++ __FUNCTION__, dev->name); + DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n"); + break; + } +@@ -2953,6 +4476,38 @@ + return; + } + #endif ++ ++static inline void clear_lro_session(struct lro *lro) ++{ ++ lro->in_use = 0; ++ lro->saw_ts = 0; ++ lro->last_frag = NULL; ++} ++ ++static inline void queue_rx_frame(struct sk_buff *skb, struct ring_info *ring, ++ u16 vlan_tag) ++{ ++ struct vlan_group *vlgrp = ring->vlgrp; ++ u8 vlan_strip_flag = ring->vlan_strip_flag; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)) ++ skb_record_rx_queue(skb, ring->ring_no); ++#endif ++ skb->protocol = eth_type_trans(skb, ring->dev); ++ if (vlgrp && vlan_tag ++ && (vlan_strip_flag == S2IO_STRIP_VLAN_TAG)) { ++ /* Queueing the vlan frame to the upper layer */ ++ if (ring->config_napi) ++ vlan_hwaccel_receive_skb(skb, vlgrp, vlan_tag); ++ else ++ vlan_hwaccel_rx(skb, vlgrp, vlan_tag); ++ } else { ++ if (ring->config_napi) ++ netif_receive_skb(skb); ++ else ++ netif_rx(skb); ++ } ++} + + /** + * rx_intr_handler - Rx interrupt handler +@@ -2967,7 +4522,7 @@ + * Return Value: + * No. of napi packets processed. + */ +-static int rx_intr_handler(struct ring_info *ring_data, int budget) ++static int rx_intr_handler(struct ring_info *ring, int budget) + { + int get_block, put_block; + struct rx_curr_get_info get_info, put_info; +@@ -2975,85 +4530,138 @@ + struct sk_buff *skb; + int pkt_cnt = 0, napi_pkts = 0; + int i; +- struct RxD1* rxdp1; +- struct RxD3* rxdp3; +- +- get_info = ring_data->rx_curr_get_info; ++ struct RxD1 *rxdp1; ++ struct RxD3 *rxdp3; ++ struct RxD5 *rxdp5; ++ ++ get_info = ring->rx_curr_get_info; + get_block = get_info.block_index; +- memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info)); ++ memcpy(&put_info, &ring->rx_curr_put_info, sizeof(put_info)); + put_block = put_info.block_index; +- rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr; +- ++ rxdp = ring->rx_blocks[get_block].rxds[get_info.offset].virt_addr; + while (RXD_IS_UP2DT(rxdp)) { +- /* +- * If your are next to put index then it's +- * FIFO full condition +- */ ++ /* If your are next to put index then it's FIFO ++ * full condition ++ */ + if ((get_block == put_block) && +- (get_info.offset + 1) == put_info.offset) { +- DBG_PRINT(INTR_DBG, "%s: Ring Full\n", +- ring_data->dev->name); +- break; +- } +- skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control); ++ ((get_info.offset + 1) == put_info.offset)) { ++ DBG_PRINT(INTR_DBG, "%s: Ring Full\n", ring->dev->name); ++ break; ++ } ++ if (ring->rxd_mode == RXD_MODE_5) ++ skb = (struct sk_buff *) ++ ((unsigned long)ring->skbs[((unsigned long) \ ++ ((struct RxD5 *)rxdp)->Host_Control)]); ++ else ++ skb = (struct sk_buff *) ((unsigned long) ++ rxdp->Host_Control); ++ + if (skb == NULL) { +- DBG_PRINT(ERR_DBG, "%s: The skb is ", +- ring_data->dev->name); +- DBG_PRINT(ERR_DBG, "Null in Rx Intr\n"); +- return 0; +- } +- if (ring_data->rxd_mode == RXD_MODE_1) { +- rxdp1 = (struct RxD1*)rxdp; +- pci_unmap_single(ring_data->pdev, (dma_addr_t) ++ DBG_PRINT(INTR_DBG, "%s: The skb is ", ++ ring->dev->name); ++ DBG_PRINT(INTR_DBG, "Null in Rx Intr\n"); ++ ring->rx_ring_stat->skb_null_rx_intr_handler_cnt++; ++ break; ++ } ++ ++ if (ring->rxd_mode == RXD_MODE_1) { ++ rxdp1 = (struct RxD1 *)rxdp; ++ pci_unmap_single(ring->pdev, (dma_addr_t) + rxdp1->Buffer0_ptr, +- ring_data->mtu + ++ ring->mtu + + HEADER_ETHERNET_II_802_3_SIZE + + HEADER_802_2_SIZE + + HEADER_SNAP_SIZE, + PCI_DMA_FROMDEVICE); +- } else if (ring_data->rxd_mode == RXD_MODE_3B) { +- rxdp3 = (struct RxD3*)rxdp; +- pci_dma_sync_single_for_cpu(ring_data->pdev, (dma_addr_t) ++ } ++ else if (ring->rxd_mode == RXD_MODE_3B) { ++ rxdp3 = (struct RxD3 *)rxdp; ++ ++ /* Synchronize the DMA transfer with the CPU first ++ * so that we see updated contents ++ */ ++ pci_dma_sync_single_for_cpu(ring->pdev, (dma_addr_t) + rxdp3->Buffer0_ptr, + BUF0_LEN, PCI_DMA_FROMDEVICE); +- pci_unmap_single(ring_data->pdev, (dma_addr_t) ++ pci_unmap_single(ring->pdev, (dma_addr_t) + rxdp3->Buffer2_ptr, +- ring_data->mtu + 4, +- PCI_DMA_FROMDEVICE); +- } +- prefetch(skb->data); +- rx_osm_handler(ring_data, rxdp); ++ ring->mtu + 4, ++ PCI_DMA_FROMDEVICE); ++ } ++ else if (ring->rxd_mode == RXD_MODE_5) { ++ rxdp5 = (struct RxD5 *)rxdp; ++ ++ /* Synchronize the DMA transfer with the CPU first ++ * so that we see updated contents ++ */ ++ pci_dma_sync_single_for_cpu(ring->pdev, (dma_addr_t) ++ rxdp5->Buffer0_ptr, BUF0_LEN, ++ PCI_DMA_FROMDEVICE); ++ pci_unmap_single(ring->pdev, (dma_addr_t) ++ rxdp5->Buffer1_ptr, ++ l3l4hdr_size + 4, ++ PCI_DMA_FROMDEVICE); ++ pci_unmap_single(ring->pdev, (dma_addr_t) ++ rxdp5->Buffer2_ptr, ++ MODE5_BUF_SIZE, PCI_DMA_FROMDEVICE); ++ if (ring->skbs_per_rxd > 2) ++ pci_unmap_single(ring->pdev, (dma_addr_t) ++ rxdp5->Buffer3_ptr, ++ MODE5_BUF_SIZE, PCI_DMA_FROMDEVICE); ++ if (ring->skbs_per_rxd > 3) ++ pci_unmap_single(ring->pdev, (dma_addr_t) ++ rxdp5->Buffer4_ptr, ++ MODE5_BUF_SIZE, PCI_DMA_FROMDEVICE); ++ } ++ else { ++ DBG_PRINT(ERR_DBG, "%s: ", ring->dev->name); ++ DBG_PRINT(ERR_DBG,"Unsupported receive mode\n"); ++ BUG(); ++ } ++ ++ (void) rx_osm_handler(ring, rxdp); + get_info.offset++; +- ring_data->rx_curr_get_info.offset = get_info.offset; +- rxdp = ring_data->rx_blocks[get_block]. ++ ring->rx_curr_get_info.offset = get_info.offset; ++ rxdp = ring->rx_blocks[get_block]. + rxds[get_info.offset].virt_addr; +- if (get_info.offset == rxd_count[ring_data->rxd_mode]) { ++ if (get_info.offset == ring->rxd_count) { + get_info.offset = 0; +- ring_data->rx_curr_get_info.offset = get_info.offset; ++ ring->rx_curr_get_info.offset = get_info.offset; + get_block++; +- if (get_block == ring_data->block_count) ++ if (get_block == ring->block_count) + get_block = 0; +- ring_data->rx_curr_get_info.block_index = get_block; +- rxdp = ring_data->rx_blocks[get_block].block_virt_addr; +- } +- +- if (ring_data->nic->config.napi) { ++ ring->rx_curr_get_info.block_index = get_block; ++ rxdp = ring->rx_blocks[get_block].block_virt_addr; ++ } ++ ++ pkt_cnt++; ++ if (ring->config_napi) { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) ++ ring->nic->pkts_to_process -= 1; ++ if (!ring->nic->pkts_to_process) ++ break; ++#else + budget--; + napi_pkts++; + if (!budget) + break; +- } +- pkt_cnt++; ++#endif ++ } ++ + if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts)) + break; +- } +- if (ring_data->lro) { ++ ++ } ++ ++ ring->rx_ring_stat->rx_pkt_cnt += pkt_cnt; ++ if (ring->lro) { + /* Clear all LRO sessions before exiting */ + for (i=0; ilro0_n[i]; ++ struct lro *lro = &ring->lro0_n[i]; + if (lro->in_use) { +- update_L3L4_header(ring_data->nic, lro); +- queue_rx_frame(lro->parent, lro->vlan_tag); ++ update_L3L4_header(ring, lro, ring->ring_no); ++ queue_rx_frame(lro->parent, ring, ++ lro->vlan_tag); + clear_lro_session(lro); + } + } +@@ -3075,90 +4683,99 @@ + + static void tx_intr_handler(struct fifo_info *fifo_data) + { ++ u8 err; + struct s2io_nic *nic = fifo_data->nic; + struct tx_curr_get_info get_info, put_info; + struct sk_buff *skb = NULL; + struct TxD *txdlp; ++ struct sk_buff *head = NULL; ++ struct sk_buff **temp; + int pkt_cnt = 0; + unsigned long flags = 0; +- u8 err_mask; + + if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags)) +- return; ++ return; + + get_info = fifo_data->tx_curr_get_info; +- memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info)); ++ put_info = fifo_data->tx_curr_put_info; + txdlp = (struct TxD *) fifo_data->list_info[get_info.offset]. +- list_virt_addr; ++ list_virt_addr; + while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) && +- (get_info.offset != put_info.offset) && +- (txdlp->Host_Control)) { ++ (get_info.offset != put_info.offset) && ++ (txdlp->Host_Control)) { + /* Check for TxD errors */ +- if (txdlp->Control_1 & TXD_T_CODE) { +- unsigned long long err; +- err = txdlp->Control_1 & TXD_T_CODE; +- if (err & 0x1) { +- nic->mac_control.stats_info->sw_stat. +- parity_err_cnt++; +- } ++ err = GET_TXD_T_CODE(txdlp->Control_1); ++ if (err) { + + /* update t_code statistics */ +- err_mask = err >> 48; +- switch(err_mask) { +- case 2: +- nic->mac_control.stats_info->sw_stat. +- tx_buf_abort_cnt++; +- break; +- +- case 3: +- nic->mac_control.stats_info->sw_stat. +- tx_desc_abort_cnt++; +- break; +- +- case 7: +- nic->mac_control.stats_info->sw_stat. +- tx_parity_err_cnt++; +- break; +- +- case 10: +- nic->mac_control.stats_info->sw_stat. +- tx_link_loss_cnt++; +- break; +- +- case 15: +- nic->mac_control.stats_info->sw_stat. +- tx_list_proc_err_cnt++; +- break; +- } ++ switch (err) { ++ case 2: ++ fifo_data->tx_fifo_stat->tx_buf_abort_cnt++; ++ break; ++ ++ case 3: ++ fifo_data->tx_fifo_stat->tx_desc_abort_cnt++; ++ break; ++ ++ case 7: ++ fifo_data->tx_fifo_stat->tx_parity_err_cnt++; ++ break; ++ ++ case 10: ++ fifo_data->tx_fifo_stat->tx_link_loss_cnt++; ++ break; ++ ++ case 15: ++ fifo_data->tx_fifo_stat->tx_list_proc_err_cnt++; ++ break; ++ } + } + + skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset); + if (skb == NULL) { + spin_unlock_irqrestore(&fifo_data->tx_lock, flags); +- DBG_PRINT(ERR_DBG, "%s: Null skb ", ++ DBG_PRINT(INTR_DBG, "%s: Null skb ", + __FUNCTION__); +- DBG_PRINT(ERR_DBG, "in Tx Free Intr\n"); ++ DBG_PRINT(INTR_DBG, "in Tx Free Intr\n"); ++ nic->sw_err_stat->skb_null_tx_intr_handler_cnt++; + return; + } ++ temp = (struct sk_buff **)&skb->cb; ++ *temp = head; ++ head = skb; + pkt_cnt++; + + /* Updating the statistics block */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22)) ++ nic->prev_stats.tx_bytes += skb->len; ++#else + nic->dev->stats.tx_bytes += skb->len; +- nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize; +- dev_kfree_skb_irq(skb); ++#endif ++ fifo_data->tx_fifo_stat->tx_mem_freed += skb->truesize; + + get_info.offset++; + if (get_info.offset == get_info.fifo_len + 1) + get_info.offset = 0; + txdlp = (struct TxD *) fifo_data->list_info +- [get_info.offset].list_virt_addr; ++ [get_info.offset].list_virt_addr; + fifo_data->tx_curr_get_info.offset = + get_info.offset; +- } +- +- s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq); ++ s2io_wake_tx_queue(fifo_data, pkt_cnt, skb, ++ nic->config.tx_steering_type); ++ } ++ ++ ++ fifo_data->tx_fifo_stat->tx_completion_cnt += pkt_cnt; + + spin_unlock_irqrestore(&fifo_data->tx_lock, flags); ++ ++ while (head) { ++ skb = head; ++ temp = (struct sk_buff **)&skb->cb; ++ head = *temp; ++ *temp = NULL; ++ dev_kfree_skb_irq(skb); ++ } + } + + /** +@@ -3174,10 +4791,10 @@ + static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev) + { + u64 val64 = 0x0; +- struct s2io_nic *sp = dev->priv; +- struct XENA_dev_config __iomem *bar0 = sp->bar0; +- +- //address transaction ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ ++ /* address transaction */ + val64 = val64 | MDIO_MMD_INDX_ADDR(addr) + | MDIO_MMD_DEV_ADDR(mmd_type) + | MDIO_MMS_PRT_ADDR(0x0); +@@ -3186,7 +4803,7 @@ + writeq(val64, &bar0->mdio_control); + udelay(100); + +- //Data transaction ++ /*Data transaction */ + val64 = 0x0; + val64 = val64 | MDIO_MMD_INDX_ADDR(addr) + | MDIO_MMD_DEV_ADDR(mmd_type) +@@ -3223,7 +4840,7 @@ + { + u64 val64 = 0x0; + u64 rval64 = 0x0; +- struct s2io_nic *sp = dev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + struct XENA_dev_config __iomem *bar0 = sp->bar0; + + /* address transaction */ +@@ -3253,6 +4870,150 @@ + return rval64; + } + /** ++ * s2io_dtx_write - Function to write in to DTX registers ++ * @mmd_type : always 5 ++ * @addr : address value ++ * @value : data value ++ * @dev : pointer to net_device structure ++ * Description: ++ * This function is used to write values to the DTE registers ++ * NONE ++ */ ++static void s2io_dtx_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev) ++{ ++ u64 val64 = 0x0; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ ++ /* address transaction */ ++ val64 = MDIO_MMD_INDX_ADDR(addr) ++ | MDIO_MMD_DEV_ADDR(mmd_type) ++ | MDIO_MMS_PRT_ADDR(0x15); ++ SPECIAL_REG_WRITE(val64, &bar0->dtx_control, UF); ++ val64 = val64 | MDIO_CTRL_START_TRANS(0xE); ++ SPECIAL_REG_WRITE(val64, &bar0->dtx_control, UF); ++ udelay(100); ++ ++ /*Data transaction */ ++ val64 = 0x0; ++ val64 = MDIO_MMD_INDX_ADDR(addr) ++ | MDIO_MMD_DEV_ADDR(mmd_type) ++ | MDIO_MMS_PRT_ADDR(0x15) ++ | MDIO_MDIO_DATA(value) ++ | MDIO_OP(MDIO_OP_WRITE_TRANS); ++ SPECIAL_REG_WRITE(val64, &bar0->dtx_control, UF); ++ val64 = val64 | MDIO_CTRL_START_TRANS(0xE); ++ SPECIAL_REG_WRITE(val64, &bar0->dtx_control, UF); ++ udelay(100); ++ ++ val64 = 0x0; ++ val64 = MDIO_MMD_INDX_ADDR(addr) ++ | MDIO_MMD_DEV_ADDR(mmd_type) ++ | MDIO_MMS_PRT_ADDR(0x15) ++ | MDIO_OP(MDIO_OP_READ_TRANS); ++ SPECIAL_REG_WRITE(val64, &bar0->dtx_control, UF); ++ val64 = val64 | MDIO_CTRL_START_TRANS(0xE); ++ SPECIAL_REG_WRITE(val64, &bar0->dtx_control, UF); ++ udelay(100); ++} ++ ++static u64 s2io_dtx_read(u32 mmd_type, u64 addr, struct net_device *dev) ++{ ++ u64 val64 = 0x0; ++ u64 rval64 = 0x0; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ ++ /* address transaction */ ++ val64 = val64 | MDIO_MMD_INDX_ADDR(addr) ++ | MDIO_MMD_DEV_ADDR(mmd_type) ++ | MDIO_MMS_PRT_ADDR(0x15); ++ ++ SPECIAL_REG_WRITE(val64,&bar0->dtx_control, UF); ++ val64 = val64 | MDIO_CTRL_START_TRANS(0xE); ++ SPECIAL_REG_WRITE(val64,&bar0->dtx_control, UF); ++ udelay(100); ++ ++ /* Data transaction */ ++ val64 = 0x0; ++ val64 = val64 | MDIO_MMD_INDX_ADDR(addr) ++ | MDIO_MMD_DEV_ADDR(mmd_type) ++ | MDIO_MMS_PRT_ADDR(0x15) ++ | MDIO_OP(MDIO_OP_READ_TRANS); ++ SPECIAL_REG_WRITE(val64,&bar0->dtx_control, UF); ++ val64 = val64 | MDIO_CTRL_START_TRANS(0xE); ++ SPECIAL_REG_WRITE(val64,&bar0->dtx_control, UF); ++ udelay(100); ++ ++ /* Read the value from regs */ ++ rval64 = readq(&bar0->dtx_control); ++ rval64 = rval64 & 0xFFFF0000; ++ rval64 = rval64 >> 16; ++ return rval64; ++} ++ ++/** ++ * s2io_chk_dte_rx_local_fault - Function to detect dte rx local fault ++ * @dev : n/w device instance ++ * Description: ++ * This function checks the occurrence of a dtx receive local fault ++ * in the absence of a rx local fault in the pcs (transponder) and will ++ * issue a dte reset if in this state. Since there is a remote ++ * possibility that the fault can persist after the dte reset, this ++ * function needs to be called from a periodic timer thread. If this function is ++ * invoked due to a link state change (link down) interrupt, and if the ++ * error persists after the dte reset, the link down interrupt will not ++ * fire again as the driver's link handling masks the link down ++ * interrupt expecting a link up (link change) interrupt, causing the adapter to ++ * remain in a persistant link down state. ++ */ ++#define MDIO_DTE_STATUS_RECEIVE_FAULT S2BIT(53) ++#define MDIO_PCS_STATUS_RECEIVE_FAULT S2BIT(53) ++#define MDIO_DTE_CONTROL1_RESET S2BIT(48) ++ ++static void s2io_chk_dte_rx_local_fault(struct net_device *dev) ++{ ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ u64 val64; ++ ++ /* ++ * Note: For mdio and dte reads, first read clears the history - the ++ * bit that was latched long ago. Second read checks if a new bit ++ * was latched and is persisting. ++ */ ++ ++ val64 = readq(&bar0->adapter_status); ++ if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT) { ++ u64 dte_val, pcs_val; ++ ++ /* dte fault condition on receive path*/ ++ dte_val = s2io_dtx_read(5, 8, dev); ++ dte_val = s2io_dtx_read(5, 8, dev); ++ ++ /* pcs no-fault condition on receive path*/ ++ ++ pcs_val = s2io_mdio_read(3, 8, dev); ++ pcs_val = s2io_mdio_read(3, 8, dev); ++ ++ if ((dte_val & MDIO_DTE_STATUS_RECEIVE_FAULT) && ++ !(pcs_val & MDIO_PCS_STATUS_RECEIVE_FAULT)) { ++ u16 val16; ++ /* dte control1 reset*/ ++ val64 = s2io_dtx_read(5, 0, dev); ++ val64 = s2io_dtx_read(5, 0, dev); ++ ++ val64 |= MDIO_DTE_CONTROL1_RESET; ++ val16 = *((u16 *)&val64); ++ s2io_dtx_write(5, 0, val16, dev); ++ ++ sp->mac_stat_info->dte_reset_cnt++; ++ } ++ } ++ return; ++} ++ ++/** + * s2io_chk_xpak_counter - Function to check the status of the xpak counters + * @counter : couter value to be updated + * @flag : flag to indicate the status +@@ -3262,42 +5023,42 @@ + * NONE + */ + +-static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type) ++static void s2io_chk_xpak_counter(u64 *counter, u64 *regs_stat, u32 index, ++ u16 flag, u16 type) + { + u64 mask = 0x3; + u64 val64; + int i; +- for(i = 0; i 0) +- { ++ if (flag > 0) { + *counter = *counter + 1; + val64 = *regs_stat & mask; + val64 = val64 >> (index * 0x2); + val64 = val64 + 1; +- if(val64 == 3) +- { ++ if (val64 == 3) { + switch(type) + { + case 1: + DBG_PRINT(ERR_DBG, "Take Xframe NIC out of " +- "service. Excessive temperatures may " +- "result in premature transceiver " +- "failure \n"); +- break; ++ "service. Excessive temperatures may " ++ "result in premature transceiver " ++ "failure \n"); ++ break; + case 2: + DBG_PRINT(ERR_DBG, "Take Xframe NIC out of " +- "service Excessive bias currents may " +- "indicate imminent laser diode " +- "failure \n"); +- break; ++ "service Excessive bias currents may " ++ "indicate imminent laser diode " ++ "failure \n"); ++ break; + case 3: + DBG_PRINT(ERR_DBG, "Take Xframe NIC out of " +- "service Excessive laser output " +- "power may saturate far-end " +- "receiver\n"); +- break; ++ "service Excessive laser output " ++ "power may saturate far-end " ++ "receiver\n"); ++ break; + default: + DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm " + "type \n"); +@@ -3307,9 +5068,8 @@ + val64 = val64 << (index * 0x2); + *regs_stat = (*regs_stat & (~mask)) | (val64); + +- } else { ++ } else + *regs_stat = *regs_stat & (~mask); +- } + } + + /** +@@ -3327,23 +5087,21 @@ + u64 val64 = 0x0; + u64 addr = 0x0; + +- struct s2io_nic *sp = dev->priv; +- struct stat_block *stat_info = sp->mac_control.stats_info; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ struct xpakStat *xpak_stat = sp->xpak_stat; + + /* Check the communication with the MDIO slave */ + addr = 0x0000; + val64 = 0x0; + val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev); +- if((val64 == 0xFFFF) || (val64 == 0x0000)) +- { ++ if ((val64 == 0xFFFF) || (val64 == 0x0000)) { + DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - " + "Returned %llx\n", (unsigned long long)val64); + return; + } + + /* Check for the expecte value of 2040 at PMA address 0x0000 */ +- if(val64 != 0x2040) +- { ++ if (val64 != 0x2040) { + DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "); + DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n", + (unsigned long long)val64); +@@ -3362,71 +5120,73 @@ + + flag = CHECKBIT(val64, 0x7); + type = 1; +- s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high, +- &stat_info->xpak_stat.xpak_regs_stat, ++ s2io_chk_xpak_counter(&xpak_stat->alarm_transceiver_temp_high, ++ &xpak_stat->xpak_regs_stat, + 0x0, flag, type); + +- if(CHECKBIT(val64, 0x6)) +- stat_info->xpak_stat.alarm_transceiver_temp_low++; ++ if (CHECKBIT(val64, 0x6)) ++ xpak_stat->alarm_transceiver_temp_low++; + + flag = CHECKBIT(val64, 0x3); + type = 2; +- s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high, +- &stat_info->xpak_stat.xpak_regs_stat, ++ s2io_chk_xpak_counter(&xpak_stat->alarm_laser_bias_current_high, ++ &xpak_stat->xpak_regs_stat, + 0x2, flag, type); + +- if(CHECKBIT(val64, 0x2)) +- stat_info->xpak_stat.alarm_laser_bias_current_low++; ++ if (CHECKBIT(val64, 0x2)) ++ xpak_stat->alarm_laser_bias_current_low++; + + flag = CHECKBIT(val64, 0x1); + type = 3; +- s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high, +- &stat_info->xpak_stat.xpak_regs_stat, ++ s2io_chk_xpak_counter(&xpak_stat->alarm_laser_output_power_high, ++ &xpak_stat->xpak_regs_stat, + 0x4, flag, type); + +- if(CHECKBIT(val64, 0x0)) +- stat_info->xpak_stat.alarm_laser_output_power_low++; ++ if (CHECKBIT(val64, 0x0)) ++ xpak_stat->alarm_laser_output_power_low++; + + /* Reading the Warning flags */ + addr = 0xA074; + val64 = 0x0; + val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev); + +- if(CHECKBIT(val64, 0x7)) +- stat_info->xpak_stat.warn_transceiver_temp_high++; +- +- if(CHECKBIT(val64, 0x6)) +- stat_info->xpak_stat.warn_transceiver_temp_low++; +- +- if(CHECKBIT(val64, 0x3)) +- stat_info->xpak_stat.warn_laser_bias_current_high++; +- +- if(CHECKBIT(val64, 0x2)) +- stat_info->xpak_stat.warn_laser_bias_current_low++; +- +- if(CHECKBIT(val64, 0x1)) +- stat_info->xpak_stat.warn_laser_output_power_high++; +- +- if(CHECKBIT(val64, 0x0)) +- stat_info->xpak_stat.warn_laser_output_power_low++; ++ if (CHECKBIT(val64, 0x7)) ++ xpak_stat->warn_transceiver_temp_high++; ++ ++ if (CHECKBIT(val64, 0x6)) ++ xpak_stat->warn_transceiver_temp_low++; ++ ++ if (CHECKBIT(val64, 0x3)) ++ xpak_stat->warn_laser_bias_current_high++; ++ ++ if (CHECKBIT(val64, 0x2)) ++ xpak_stat->warn_laser_bias_current_low++; ++ ++ if (CHECKBIT(val64, 0x1)) ++ xpak_stat->warn_laser_output_power_high++; ++ ++ if (CHECKBIT(val64, 0x0)) ++ xpak_stat->warn_laser_output_power_low++; + } + + /** + * wait_for_cmd_complete - waits for a command to complete. +- * @sp : private member of the device structure, which is a pointer to the +- * s2io_nic structure. +- * Description: Function that waits for a command to Write into RMAC +- * ADDR DATA registers to be completed and returns either success or +- * error depending on whether the command was complete or not. +- * Return value: +- * SUCCESS on success and FAILURE on failure. +- */ +- +-static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit, ++ * @addr: address value ++ * @busy_bit: bit in the register that needs to be checked ++ * @bit_state: flag to check if bit is set or reset ++ * Description: Function that waits for a command to be completed ++ * and returns either success or error depending on whether the ++ * command was complete or not. ++ * Return value: ++ * SUCCESS or FAILURE. ++ */ ++ ++static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit, + int bit_state) + { +- int ret = FAILURE, cnt = 0, delay = 1; +- u64 val64; ++ int ret = FAILURE, cnt = 0; ++ u64 val64; ++ int delay = 1; + + if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET)) + return FAILURE; +@@ -3439,31 +5199,38 @@ + break; + } + } else { +- if (!(val64 & busy_bit)) { ++ if (val64 & busy_bit) { + ret = SUCCESS; + break; + } + } + +- if(in_interrupt()) ++ if (in_interrupt()) + mdelay(delay); + else + msleep(delay); + + if (++cnt >= 10) + delay = 50; ++ + } while (cnt < 20); + return ret; + } ++ + /* + * check_pci_device_id - Checks if the device id is supported + * @id : device id +- * Description: Function to check if the pci device id is supported by driver. ++ * Description: Function to check if the pci device id is supported by the driver. + * Return value: Actual device id if supported else PCI_ANY_ID + */ + static u16 check_pci_device_id(u16 id) + { + switch (id) { ++#ifdef TITAN_LEGACY ++ case PCI_DEVICE_ID_TITAN_WIN: ++ case PCI_DEVICE_ID_TITAN_UNI: ++ return TITAN_DEVICE; ++#endif + case PCI_DEVICE_ID_HERC_WIN: + case PCI_DEVICE_ID_HERC_UNI: + return XFRAME_II_DEVICE; +@@ -3485,41 +5252,40 @@ + * void. + */ + +-static void s2io_reset(struct s2io_nic * sp) ++static void s2io_reset(struct s2io_nic *sp) + { + struct XENA_dev_config __iomem *bar0 = sp->bar0; + u64 val64; + u16 subid, pci_cmd; + int i; + u16 val16; +- unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt; +- unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt; +- +- DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n", +- __FUNCTION__, sp->dev->name); ++ struct swErrStat err_stat; ++ ++ DBG_PRINT(INIT_DBG, "%s - Resetting XFrame card %s\n", ++ __FUNCTION__, sp->dev->name); + + /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */ + pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd)); + + val64 = SW_RESET_ALL; + writeq(val64, &bar0->sw_reset); +- if (strstr(sp->product_name, "CX4")) { ++ ++ if (strstr(sp->product_name, "CX4")) + msleep(750); +- } + msleep(250); ++ + for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) { + + /* Restore the PCI state saved during initialization. */ +- pci_restore_state(sp->pdev); ++ pci_restore_state(sp->pdev, sp->config_space); + pci_read_config_word(sp->pdev, 0x2, &val16); + if (check_pci_device_id(val16) != (u16)PCI_ANY_ID) + break; + msleep(200); + } + +- if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) { +- DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__); +- } ++ if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) ++ DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __FUNCTION__); + + pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd); + +@@ -3531,8 +5297,10 @@ + /* restore mac_addr entries */ + do_s2io_restore_unicast_mc(sp); + ++#ifdef CONFIG_PCI_MSI + /* Restore the MSIX table entries from local variables */ + restore_xmsi_data(sp); ++#endif + + /* Clear certain PCI/PCI-X fields after reset */ + if (sp->device_type == XFRAME_II_DEVICE) { +@@ -3543,36 +5311,24 @@ + pci_write_config_dword(sp->pdev, 0x68, 0x7C); + + /* Clearing PCI_STATUS error reflected here */ +- writeq(s2BIT(62), &bar0->txpic_int_reg); ++ writeq(S2BIT(62), &bar0->txpic_int_reg); + } + + /* Reset device statistics maintained by OS */ + memset(&sp->stats, 0, sizeof (struct net_device_stats)); + +- up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt; +- down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt; +- up_time = sp->mac_control.stats_info->sw_stat.link_up_time; +- down_time = sp->mac_control.stats_info->sw_stat.link_down_time; +- reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt; +- mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated; +- mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed; +- watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt; +- /* save link up/down time/cnt, reset/memory/watchdog cnt */ ++ /* save all the software error statistics */ ++ memcpy(&err_stat, &sp->mac_stat_info, sizeof(struct swErrStat)); ++ + memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block)); +- /* restore link up/down time/cnt, reset/memory/watchdog cnt */ +- sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt; +- sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt; +- sp->mac_control.stats_info->sw_stat.link_up_time = up_time; +- sp->mac_control.stats_info->sw_stat.link_down_time = down_time; +- sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt; +- sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt; +- sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt; +- sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt; ++ ++ /* restore the software error statistics */ ++ memcpy(&sp->mac_stat_info, &err_stat, sizeof(struct swErrStat)); + + /* SXE-002: Configure link and activity LED to turn it off */ + subid = sp->pdev->subsystem_device; + if (((subid & 0xFF) >= 0x07) && +- (sp->device_type == XFRAME_I_DEVICE)) { ++ (sp->device_type == XFRAME_I_DEVICE)) { + val64 = readq(&bar0->gpio_control); + val64 |= 0x0000800000000000ULL; + writeq(val64, &bar0->gpio_control); +@@ -3602,11 +5358,11 @@ + * SUCCESS on success and FAILURE on failure. + */ + +-static int s2io_set_swapper(struct s2io_nic * sp) ++static int s2io_set_swapper(struct s2io_nic *sp) + { + struct net_device *dev = sp->dev; + struct XENA_dev_config __iomem *bar0 = sp->bar0; +- u64 val64, valt, valr; ++ u64 val64, valt, valr, sw_wr, rth_wr; + + /* + * Set proper endian settings and verify the same by reading +@@ -3616,12 +5372,12 @@ + val64 = readq(&bar0->pif_rd_swapper_fb); + if (val64 != 0x0123456789ABCDEFULL) { + int i = 0; +- u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */ +- 0x8100008181000081ULL, /* FE=1, SE=0 */ +- 0x4200004242000042ULL, /* FE=0, SE=1 */ +- 0}; /* FE=0, SE=0 */ +- +- while(i<4) { ++ u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */ ++ 0x8100008181000081ULL, /* FE=1, SE=0 */ ++ 0x4200004242000042ULL, /* FE=0, SE=1 */ ++ 0}; /* FE=0, SE=0 */ ++ ++ while (i < 4) { + writeq(value[i], &bar0->swapper_ctrl); + val64 = readq(&bar0->pif_rd_swapper_fb); + if (val64 == 0x0123456789ABCDEFULL) +@@ -3636,22 +5392,21 @@ + return FAILURE; + } + valr = value[i]; +- } else { ++ } else + valr = readq(&bar0->swapper_ctrl); +- } + + valt = 0x0123456789ABCDEFULL; + writeq(valt, &bar0->xmsi_address); + val64 = readq(&bar0->xmsi_address); + +- if(val64 != valt) { ++ if (val64 != valt) { + int i = 0; + u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */ + 0x0081810000818100ULL, /* FE=1, SE=0 */ + 0x0042420000424200ULL, /* FE=0, SE=1 */ + 0}; /* FE=0, SE=0 */ + +- while(i<4) { ++ while (i < 4) { + writeq((value[i] | valr), &bar0->swapper_ctrl); + writeq(valt, &bar0->xmsi_address); + val64 = readq(&bar0->xmsi_address); +@@ -3659,7 +5414,7 @@ + break; + i++; + } +- if(i == 4) { ++ if (i == 4) { + unsigned long long x = val64; + DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr "); + DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x); +@@ -3668,6 +5423,9 @@ + } + val64 = readq(&bar0->swapper_ctrl); + val64 &= 0xFFFF000000000000ULL; ++ sw_wr = (val64 & vBIT(3, 8, 2)); ++ rth_wr = (sw_wr >> 2); ++ val64 |= rth_wr; + + #ifdef __BIG_ENDIAN + /* +@@ -3730,6 +5488,7 @@ + return SUCCESS; + } + ++#ifdef CONFIG_PCI_MSI + static int wait_for_msix_trans(struct s2io_nic *nic, int i) + { + struct XENA_dev_config __iomem *bar0 = nic->bar0; +@@ -3738,7 +5497,7 @@ + + do { + val64 = readq(&bar0->xmsi_access); +- if (!(val64 & s2BIT(15))) ++ if (!(val64 & S2BIT(15))) + break; + mdelay(1); + cnt++; +@@ -3755,19 +5514,18 @@ + { + struct XENA_dev_config __iomem *bar0 = nic->bar0; + u64 val64; +- int i, msix_index; +- ++ int i, msix_indx; + + if (nic->device_type == XFRAME_I_DEVICE) + return; + +- for (i=0; i < MAX_REQUESTED_MSI_X; i++) { +- msix_index = (i) ? ((i-1) * 8 + 1): 0; ++ for (i = 0; i < MAX_REQUESTED_MSI_X; i++) { ++ msix_indx = (i) ? ((i-1) * 8 + 1): 0; + writeq(nic->msix_info[i].addr, &bar0->xmsi_address); + writeq(nic->msix_info[i].data, &bar0->xmsi_data); +- val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6)); ++ val64 = (S2BIT(7) | S2BIT(15) | vBIT(msix_indx, 26, 6)); + writeq(val64, &bar0->xmsi_access); +- if (wait_for_msix_trans(nic, msix_index)) { ++ if (wait_for_msix_trans(nic, msix_indx)) { + DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__); + continue; + } +@@ -3778,17 +5536,17 @@ + { + struct XENA_dev_config __iomem *bar0 = nic->bar0; + u64 val64, addr, data; +- int i, msix_index; ++ int i, msix_indx; + + if (nic->device_type == XFRAME_I_DEVICE) + return; + + /* Store and display */ +- for (i=0; i < MAX_REQUESTED_MSI_X; i++) { +- msix_index = (i) ? ((i-1) * 8 + 1): 0; +- val64 = (s2BIT(15) | vBIT(msix_index, 26, 6)); ++ for (i = 0; i < MAX_REQUESTED_MSI_X; i++) { ++ msix_indx = (i) ? ((i-1) * 8 + 1): 0; ++ val64 = (S2BIT(15) | vBIT(msix_indx, 26, 6)); + writeq(val64, &bar0->xmsi_access); +- if (wait_for_msix_trans(nic, msix_index)) { ++ if (wait_for_msix_trans(nic, msix_indx)) { + DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__); + continue; + } +@@ -3809,32 +5567,23 @@ + int ret, i, j, msix_indx = 1; + + nic->entries = kmalloc(nic->num_entries * sizeof(struct msix_entry), +- GFP_KERNEL); +- if (!nic->entries) { +- DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \ ++ GFP_KERNEL); ++ if (nic->entries == NULL) { ++ DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", + __FUNCTION__); +- nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++; + return -ENOMEM; + } +- nic->mac_control.stats_info->sw_stat.mem_allocated +- += (nic->num_entries * sizeof(struct msix_entry)); +- + memset(nic->entries, 0, nic->num_entries * sizeof(struct msix_entry)); + + nic->s2io_entries = + kmalloc(nic->num_entries * sizeof(struct s2io_msix_entry), + GFP_KERNEL); +- if (!nic->s2io_entries) { ++ if (nic->s2io_entries == NULL) { + DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", + __FUNCTION__); +- nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++; + kfree(nic->entries); +- nic->mac_control.stats_info->sw_stat.mem_freed +- += (nic->num_entries * sizeof(struct msix_entry)); + return -ENOMEM; + } +- nic->mac_control.stats_info->sw_stat.mem_allocated +- += (nic->num_entries * sizeof(struct s2io_msix_entry)); + memset(nic->s2io_entries, 0, + nic->num_entries * sizeof(struct s2io_msix_entry)); + +@@ -3863,15 +5612,17 @@ + readq(&bar0->rx_mat); + + ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries); ++ + /* We fail init if error or we get less vectors than min required */ + if (ret) { +- DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name); ++ DBG_PRINT(ERR_DBG, "s2io: Enabling MSIX failed\n"); ++ if (ret > 0) ++ DBG_PRINT(ERR_DBG, "s2io: Requested for %d, " \ ++ "but got only %d vector(s), try with " \ ++ "rx_ring_num = %d\n", ++ nic->num_entries, ret, (ret-1)); + kfree(nic->entries); +- nic->mac_control.stats_info->sw_stat.mem_freed +- += (nic->num_entries * sizeof(struct msix_entry)); + kfree(nic->s2io_entries); +- nic->mac_control.stats_info->sw_stat.mem_freed +- += (nic->num_entries * sizeof(struct s2io_msix_entry)); + nic->entries = NULL; + nic->s2io_entries = NULL; + return -ENOMEM; +@@ -3889,7 +5640,12 @@ + } + + /* Handle software interrupt used during MSI(X) test */ +-static irqreturn_t s2io_test_intr(int irq, void *dev_id) ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++static irqreturn_t __devinit s2io_test_intr(int irq, void *dev_id, ++ struct pt_regs *regs) ++#else ++static irqreturn_t __devinit s2io_test_intr(int irq, void *dev_id) ++#endif + { + struct s2io_nic *sp = dev_id; + +@@ -3900,7 +5656,7 @@ + } + + /* Test interrupt path by forcing a a software IRQ */ +-static int s2io_test_msi(struct s2io_nic *sp) ++static int __devinit s2io_test_msi(struct s2io_nic *sp) + { + struct pci_dev *pdev = sp->pdev; + struct XENA_dev_config __iomem *bar0 = sp->bar0; +@@ -3908,14 +5664,14 @@ + u64 val64, saved64; + + err = request_irq(sp->entries[1].vector, s2io_test_intr, 0, +- sp->name, sp); ++ sp->name, sp); + if (err) { +- DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n", +- sp->dev->name, pci_name(pdev), pdev->irq); ++ DBG_PRINT(ERR_DBG, "s2io: PCI %s: cannot assign irq %d\n", ++ pci_name(pdev), pdev->irq); + return err; + } + +- init_waitqueue_head (&sp->msi_wait); ++ init_waitqueue_head(&sp->msi_wait); + sp->msi_detected = 0; + + saved64 = val64 = readq(&bar0->scheduled_int_ctrl); +@@ -3928,9 +5684,8 @@ + + if (!sp->msi_detected) { + /* MSI(X) test failed, go back to INTx mode */ +- DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated " +- "using MSI(X) during test\n", sp->dev->name, +- pci_name(pdev)); ++ DBG_PRINT(ERR_DBG, "s2io: PCI %s: No interrupt was generated " ++ "using MSI(X) during test\n", pci_name(pdev)); + + err = -EOPNOTSUPP; + } +@@ -3941,8 +5696,10 @@ + + return err; + } +- +-static void remove_msix_isr(struct s2io_nic *sp) ++#endif ++ ++#ifdef CONFIG_PCI_MSI ++static void do_rem_msix_isr(struct s2io_nic *sp) + { + int i; + u16 msi_control; +@@ -3952,6 +5709,7 @@ + MSIX_REGISTERED_SUCCESS) { + int vector = sp->entries[i].vector; + void *arg = sp->s2io_entries[i].arg; ++ s2io_synchronize_irq(vector); + free_irq(vector, arg); + } + } +@@ -3967,11 +5725,13 @@ + + pci_disable_msix(sp->pdev); + } +- +-static void remove_inta_isr(struct s2io_nic *sp) ++#endif ++ ++static void do_rem_inta_isr(struct s2io_nic *sp) + { + struct net_device *dev = sp->dev; +- ++ /* Waiting till all Interrupt handlers are complete */ ++ s2io_synchronize_irq(sp->pdev->irq); + free_irq(sp->pdev->irq, dev); + } + +@@ -3993,8 +5753,12 @@ + + static int s2io_open(struct net_device *dev) + { +- struct s2io_nic *sp = dev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + int err = 0; ++ ++#ifdef CONFIG_PCI_MSI ++ struct swDbgStat *stats = sp->sw_dbg_stat; ++#endif + + /* + * Make sure you have link off by default every time +@@ -4017,22 +5781,27 @@ + err = -ENODEV; + goto hw_init_failed; + } ++ + s2io_start_all_tx_queue(sp); ++ + return 0; + + hw_init_failed: ++#ifdef CONFIG_PCI_MSI + if (sp->config.intr_type == MSI_X) { + if (sp->entries) { + kfree(sp->entries); +- sp->mac_control.stats_info->sw_stat.mem_freed +- += (sp->num_entries * sizeof(struct msix_entry)); ++ stats->mem_freed += ++ (sp->num_entries * sizeof(struct msix_entry)); + } + if (sp->s2io_entries) { + kfree(sp->s2io_entries); +- sp->mac_control.stats_info->sw_stat.mem_freed +- += (sp->num_entries * sizeof(struct s2io_msix_entry)); +- } +- } ++ stats->mem_freed += ++ (sp->num_entries * ++ sizeof(struct s2io_msix_entry)); ++ } ++ } ++#endif + return err; + } + +@@ -4051,30 +5820,63 @@ + + static int s2io_close(struct net_device *dev) + { +- struct s2io_nic *sp = dev->priv; +- struct config_param *config = &sp->config; +- u64 tmp64; +- int offset; +- +- /* Return if the device is already closed * +- * Can happen when s2io_card_up failed in change_mtu * ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ ++ /* Return if the device is already closed * ++ * Can happen when s2io_card_up failed in change_mtu * + */ + if (!is_s2io_card_up(sp)) + return 0; + + s2io_stop_all_tx_queue(sp); +- /* delete all populated mac entries */ +- for (offset = 1; offset < config->max_mc_addr; offset++) { +- tmp64 = do_s2io_read_unicast_mc(sp, offset); +- if (tmp64 != S2IO_DISABLE_MAC_ENTRY) +- do_s2io_delete_unicast_mc(sp, tmp64); +- } +- ++ ++ /* Reset card, free Tx and Rx buffers. */ + s2io_card_down(sp); + + return 0; + } + ++/* select a fifo to trasmit the packet */ ++static void get_fifo_no( struct s2io_nic *sp, struct sk_buff *skb, ++ int *enable_per_list_interrupt, u16 *queue_len, ++ u16 *counter, int *do_spin_lock) ++{ ++ if (skb->protocol == htons(ETH_P_IP)) { ++ struct iphdr *ip; ++ struct tcphdr *th; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)) ++ ip = ip_hdr(skb); ++#else ++ ip = skb->nh.iph; ++#endif ++ if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) { ++ th = (struct tcphdr *)(((unsigned char *)ip) + ++ ip->ihl*4); ++ ++ if (ip->protocol == IPPROTO_TCP) { ++ *queue_len = sp->total_tcp_fifos; ++ *counter = (ntohs(th->source) + ++ ntohs(th->dest)) & ++ sp->fifo_selector[*queue_len - 1]; ++ if (*counter >= *queue_len) ++ *counter = *queue_len - 1; ++ } else if (ip->protocol == IPPROTO_UDP) { ++ *queue_len = sp->total_udp_fifos; ++ *counter = (ntohs(th->source) + ++ ntohs(th->dest)) & ++ sp->fifo_selector[*queue_len - 1]; ++ if (*counter >= *queue_len) ++ *counter = *queue_len - 1; ++ *counter += sp->udp_fifo_idx; ++ if (skb->len > 1024) ++ *enable_per_list_interrupt = 1; ++#ifdef NETIF_F_LLTX ++ *do_spin_lock = 0; ++#endif ++ } ++ } ++ } ++} + /** + * s2io_xmit - Tx entry point of te driver + * @skb : the socket buffer containing the Tx data. +@@ -4087,81 +5889,81 @@ + * Return value: + * 0 on success & 1 on failure. + */ +- + static int s2io_xmit(struct sk_buff *skb, struct net_device *dev) + { +- struct s2io_nic *sp = dev->priv; +- u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off; +- register u64 val64; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ u16 frg_cnt, frg_len, queue_len, put_off, get_off; ++ u64 val64; ++ u32 val32; + struct TxD *txdp; + struct TxFIFO_element __iomem *tx_fifo; + unsigned long flags = 0; + u16 vlan_tag = 0; ++ struct mac_info *mac_control; + struct fifo_info *fifo = NULL; +- struct mac_info *mac_control; +- struct config_param *config; +- int do_spin_lock = 1; ++ int txd_cnt = 0; + int offload_type; + int enable_per_list_interrupt = 0; +- struct swStat *stats = &sp->mac_control.stats_info->sw_stat; ++ int do_spin_lock = 1; ++ struct txFifoStat *fifo_stats; ++ u16 counter = sp->other_fifo_idx; + + mac_control = &sp->mac_control; +- config = &sp->config; + + DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name); + ++ /* A buffer with no data will be dropped */ + if (unlikely(skb->len <= 0)) { + DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name); + dev_kfree_skb_any(skb); + return 0; + } + +- if (!is_s2io_card_up(sp)) { ++ /* In debug mode, return if a serious error had occured */ ++ if (unlikely(1 == sp->serious_err) && unlikely(0 == sp->exec_mode)) { ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ ++ if (unlikely(!is_s2io_card_up(sp))) { + DBG_PRINT(TX_DBG, "%s: Card going down for reset\n", + dev->name); +- dev_kfree_skb(skb); +- return 0; +- } +- +- queue = 0; ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ + if (sp->vlgrp && vlan_tx_tag_present(skb)) ++ /* Get Fifo number to Transmit based on vlan priority */ + vlan_tag = vlan_tx_tag_get(skb); +- if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) { +- if (skb->protocol == htons(ETH_P_IP)) { +- struct iphdr *ip; +- struct tcphdr *th; +- ip = ip_hdr(skb); +- +- if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) { +- th = (struct tcphdr *)(((unsigned char *)ip) + +- ip->ihl*4); +- +- if (ip->protocol == IPPROTO_TCP) { +- queue_len = sp->total_tcp_fifos; +- queue = (ntohs(th->source) + +- ntohs(th->dest)) & +- sp->fifo_selector[queue_len - 1]; +- if (queue >= queue_len) +- queue = queue_len - 1; +- } else if (ip->protocol == IPPROTO_UDP) { +- queue_len = sp->total_udp_fifos; +- queue = (ntohs(th->source) + +- ntohs(th->dest)) & +- sp->fifo_selector[queue_len - 1]; +- if (queue >= queue_len) +- queue = queue_len - 1; +- queue += sp->udp_fifo_idx; +- if (skb->len > 1024) +- enable_per_list_interrupt = 1; +- do_spin_lock = 0; +- } +- } +- } +- } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING) +- /* get fifo number based on skb->priority value */ +- queue = config->fifo_mapping +- [skb->priority & (MAX_TX_FIFOS - 1)]; +- fifo = &mac_control->fifos[queue]; ++ ++ if (sp->config.tx_steering_type == TX_MULTIQ_STEERING) { ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 26)) ++ counter = skb_get_queue_mapping(skb); ++#else ++ get_fifo_no(sp, skb, &enable_per_list_interrupt, ++ &queue_len, &counter, &do_spin_lock); ++#endif ++ } else if (sp->config.tx_steering_type == TX_STEERING_DEFAULT) { ++ get_fifo_no(sp, skb, &enable_per_list_interrupt, ++ &queue_len, &counter, &do_spin_lock); ++ } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING) { ++ counter = s2io_get_tx_priority(skb, vlan_tag); ++ counter = sp->fifo_mapping[counter]; ++ } else if (sp->config.tx_steering_type == TX_VLAN_STEERING) { ++ u16 vlan_id = vlan_tag & VLAN_VID_MASK; ++ ++ if (vlan_id < VLAN_VID_MASK) { ++ if (S2IO_INVALID_RING != sp->vlan_array[vlan_id]) ++ counter = sp->vlan_array[vlan_id]; ++ ++ if (counter > sp->config.tx_fifo_num) ++ counter = 0; ++ } ++ } ++ ++ fifo = &mac_control->fifos[counter]; ++ fifo_stats = fifo->tx_fifo_stat; + + if (do_spin_lock) + spin_lock_irqsave(&fifo->tx_lock, flags); +@@ -4170,8 +5972,8 @@ + return NETDEV_TX_LOCKED; + } + +- if (sp->config.multiq) { +- if (__netif_subqueue_stopped(dev, fifo->fifo_no)) { ++ if (sp->config.tx_steering_type == TX_MULTIQ_STEERING) { ++ if (s2io_netif_subqueue_stopped(dev, skb, fifo->fifo_no)) { + spin_unlock_irqrestore(&fifo->tx_lock, flags); + return NETDEV_TX_BUSY; + } +@@ -4181,7 +5983,6 @@ + return NETDEV_TX_BUSY; + } + } +- + put_off = (u16) fifo->tx_curr_put_info.offset; + get_off = (u16) fifo->tx_curr_get_info.offset; + txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr; +@@ -4192,21 +5993,31 @@ + ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) { + DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n"); + s2io_stop_tx_queue(sp, fifo->fifo_no); ++ ++ spin_unlock_irqrestore(&fifo->tx_lock, flags); + dev_kfree_skb(skb); +- spin_unlock_irqrestore(&fifo->tx_lock, flags); + return 0; + } + + offload_type = s2io_offload_type(skb); ++ ++ /* only txd0 Buffer pointer, Buffer length changes depending upon ++ * whether amd_fix is enabled, or UFO is enabled. Rest all bits of ++ * txd0 will remain same so lets set them in the beginning itself ++ * before we start processing the txds so that we can reduce number of ++ * if conditions ++ */ ++#ifdef NETIF_F_TSO + if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { + txdp->Control_1 |= TXD_TCP_LSO_EN; + txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb)); + } +- if (skb->ip_summed == CHECKSUM_PARTIAL) { ++#endif ++ if (skb->ip_summed == CHECKSUM_PARTIAL) + txdp->Control_2 |= +- (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN | +- TXD_TX_CKO_UDP_EN); +- } ++ (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN | ++ TXD_TX_CKO_UDP_EN); ++ + txdp->Control_1 |= TXD_GATHER_CODE_FIRST; + txdp->Control_1 |= TXD_LIST_OWN_XENA; + txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no); +@@ -4217,8 +6028,9 @@ + txdp->Control_2 |= TXD_VLAN_ENABLE; + txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag); + } +- + frg_len = skb->len - skb->data_len; ++ ++#ifdef NETIF_F_UFO + if (offload_type == SKB_GSO_UDP) { + int ufo_size; + +@@ -4228,25 +6040,27 @@ + txdp->Control_1 |= TXD_UFO_MSS(ufo_size); + txdp->Control_1 |= TXD_BUFFER0_SIZE(8); + #ifdef __BIG_ENDIAN +- /* both variants do cpu_to_be64(be32_to_cpu(...)) */ + fifo->ufo_in_band_v[put_off] = +- (__force u64)skb_shinfo(skb)->ip6_frag_id; ++ (u64)skb_shinfo(skb)->ip6_frag_id; + #else + fifo->ufo_in_band_v[put_off] = +- (__force u64)skb_shinfo(skb)->ip6_frag_id << 32; ++ (u64)skb_shinfo(skb)->ip6_frag_id << 32; + #endif + txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v; + txdp->Buffer_Pointer = pci_map_single(sp->pdev, + fifo->ufo_in_band_v, + sizeof(u64), PCI_DMA_TODEVICE); +- if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer)) ++ if (pci_dma_mapping_error(txdp->Buffer_Pointer)) + goto pci_map_failed; ++ + txdp++; + } ++#endif + + txdp->Buffer_Pointer = pci_map_single +- (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE); +- if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer)) ++ (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE); ++ ++ if (pci_dma_mapping_error(txdp->Buffer_Pointer)) + goto pci_map_failed; + + txdp->Host_Control = (unsigned long) skb; +@@ -4256,15 +6070,15 @@ + + frg_cnt = skb_shinfo(skb)->nr_frags; + /* For fragmented SKB. */ +- for (i = 0; i < frg_cnt; i++) { +- skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ for (counter = 0; counter < frg_cnt; counter++) { ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[counter]; + /* A '0' length fragment will be ignored */ + if (!frag->size) + continue; + txdp++; + txdp->Buffer_Pointer = (u64) pci_map_page +- (sp->pdev, frag->page, frag->page_offset, +- frag->size, PCI_DMA_TODEVICE); ++ (sp->pdev, frag->page, frag->page_offset, ++ frag->size, PCI_DMA_TODEVICE); + txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size); + if (offload_type == SKB_GSO_UDP) + txdp->Control_1 |= TXD_UFO_EN; +@@ -4274,18 +6088,38 @@ + if (offload_type == SKB_GSO_UDP) + frg_cnt++; /* as Txd0 was used for inband header */ + +- tx_fifo = mac_control->tx_FIFO_start[queue]; ++ tx_fifo = mac_control->tx_FIFO_start[fifo->fifo_no]; + val64 = fifo->list_info[put_off].list_phy_addr; + writeq(val64, &tx_fifo->TxDL_Pointer); + +- val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST | +- TX_FIFO_LAST_LIST); ++ wmb(); ++ ++ val64 = (TX_FIFO_LAST_TXD_NUM(txd_cnt + frg_cnt) | TX_FIFO_FIRST_LIST | ++ TX_FIFO_LAST_LIST); + if (offload_type) + val64 |= TX_FIFO_SPECIAL_FUNC; + + writeq(val64, &tx_fifo->List_Control); + +- mmiowb(); ++ val32 = readl(&bar0->general_int_status); ++ /* if the returned value is all F's free skb */ ++ if (unlikely(val32 == S2IO_32_BIT_MINUS_ONE)) { ++ s2io_stop_tx_queue(sp, fifo->fifo_no); ++ ++ txdp = fifo->list_info[put_off].list_virt_addr; ++ skb = s2io_txdl_getskb(fifo, txdp, put_off); ++ spin_unlock_irqrestore(&fifo->tx_lock, flags); ++ if (skb == NULL) { ++ DBG_PRINT(TX_DBG, "%s: Null skb ", ++ __FUNCTION__); ++ sp->mac_stat_info->skb_null_s2io_xmit_cnt++; ++ return 0; ++ } ++ dev_kfree_skb(skb); ++ return 0; ++ } ++ ++ fifo->tx_fifo_stat->tx_pkt_cnt ++; + + put_off++; + if (put_off == fifo->tx_curr_put_info.fifo_len + 1) +@@ -4294,27 +6128,133 @@ + + /* Avoid "put" pointer going beyond "get" pointer */ + if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) { +- sp->mac_control.stats_info->sw_stat.fifo_full_cnt++; ++ fifo_stats->fifo_full_cnt++; + DBG_PRINT(TX_DBG, +- "No free TxDs for xmit, Put: 0x%x Get:0x%x\n", +- put_off, get_off); ++ "No free TxDs for xmit, Put: 0x%x Get:0x%x\n", ++ put_off, get_off); + s2io_stop_tx_queue(sp, fifo->fifo_no); + } +- mac_control->stats_info->sw_stat.mem_allocated += skb->truesize; ++ ++ fifo_stats->tx_mem_allocated += skb->truesize; + dev->trans_start = jiffies; ++ + spin_unlock_irqrestore(&fifo->tx_lock, flags); + +- if (sp->config.intr_type == MSI_X) ++ if(sp->config.intr_type == MSI_X) + tx_intr_handler(fifo); + + return 0; + pci_map_failed: +- stats->pci_map_fail_cnt++; ++ fifo_stats->tx_pci_map_fail_cnt++; + s2io_stop_tx_queue(sp, fifo->fifo_no); +- stats->mem_freed += skb->truesize; ++ fifo_stats->tx_mem_freed += skb->truesize; ++ spin_unlock_irqrestore(&fifo->tx_lock, flags); + dev_kfree_skb(skb); +- spin_unlock_irqrestore(&fifo->tx_lock, flags); +- return 0; ++ return 0; ++} ++ ++static void ++poll_queue_stuck(struct net_device *dev) ++{ ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ struct ring_info *ring; ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ u64 val64 = 0, orig_thresh_q0q3, orig_thresh_q4q7, mod_thresh_q0q3, mod_thresh_q4q7; ++ int i; ++ ++ /* ++ Force the HIGH threshold UP_CROSSED event to be re-evaluated by ++ temporarily moving the threshold to a value that can't be up-crossed. ++ This fakes out the hardware such that it thinks the amount of queued ++ data is less than the threshold. When the threshold is restored to its ++ original value, if the amount of queued data is above the threshold then ++ the UP_CROSSED event will latch in the register. ++ */ ++ for (i=0; i < MAX_RX_RINGS; i++) ++ val64 |= RMAC_HIGH_UP_CROSSED_Qn(i); ++ writeq(val64, &bar0->rmac_pthresh_cross); ++ ++ orig_thresh_q0q3 = readq(&bar0->mc_pause_thresh_q0q3); ++ val64 = orig_thresh_q0q3 | 0x00FF00FF00FF00FF; ++ writeq(val64, &bar0->mc_pause_thresh_q0q3); ++ val64 = readq(&bar0->mc_pause_thresh_q0q3); ++ writeq(orig_thresh_q0q3, &bar0->mc_pause_thresh_q0q3); ++ ++ orig_thresh_q4q7 = readq(&bar0->mc_pause_thresh_q4q7); ++ val64 = orig_thresh_q4q7 | 0x00FF00FF00FF00FF; ++ writeq(val64, &bar0->mc_pause_thresh_q4q7); ++ val64 = readq(&bar0->mc_pause_thresh_q0q3); ++ writeq(orig_thresh_q4q7, &bar0->mc_pause_thresh_q4q7); ++ ++ /* ++ Force the LOW threshold DOWN_CROSSED event to be re-evaluated by ++ temporarily moving the threshold to a value that can't be down-crossed. ++ This fakes out the hardware such that it thinks the amount of queued ++ data is more than the threshold. When the threshold is restored to its ++ original value, if the amount of queued data is below the threshold then ++ the DOWN_CROSSED event will latch in the register. ++ */ ++ ++ /* set mc_pause_thresh_q0q3, mc_pause_thresh_q4q7 LOW_THR fields to ++ the same value as their corresponding HIGH_THR fields */ ++ mod_thresh_q0q3 = orig_thresh_q0q3 & 0x00FF00FF00FF00FF; ++ mod_thresh_q0q3 |= (mod_thresh_q0q3 << 8); ++ mod_thresh_q4q7 = orig_thresh_q4q7 & 0x00FF00FF00FF00FF; ++ mod_thresh_q4q7 |= (mod_thresh_q4q7 << 8); ++ ++ /* Ensures that we know where we're starting from before ++ we set the LOW_THR to 0x00 */ ++ writeq(mod_thresh_q0q3, &bar0->mc_pause_thresh_q0q3); ++ writeq(mod_thresh_q4q7, &bar0->mc_pause_thresh_q4q7); ++ ++ val64 = 0; ++ for (i=0, val64=0; i < MAX_RX_RINGS; i++) ++ val64 |= RMAC_LOW_DOWN_CROSSED_Qn(i); ++ writeq(val64, &bar0->rmac_pthresh_cross); ++ ++ val64 = mod_thresh_q0q3 & 0x00FF00FF00FF00FF; ++ writeq(val64, &bar0->mc_pause_thresh_q0q3); ++ val64 = readq(&bar0->mc_pause_thresh_q0q3); ++ writeq(mod_thresh_q0q3, &bar0->mc_pause_thresh_q0q3); ++ ++ val64 = mod_thresh_q4q7 & 0x00FF00FF00FF00FF; ++ writeq(val64, &bar0->mc_pause_thresh_q4q7); ++ val64 = readq(&bar0->mc_pause_thresh_q0q3); ++ writeq(mod_thresh_q4q7, &bar0->mc_pause_thresh_q4q7); ++ ++ /* Read the up_crossed/down_crossed registers */ ++ val64 = readq(&bar0->rmac_pthresh_cross); ++ ++ /* See if any of the queues are stuck */ ++ for (i = 0; i < sp->config.rx_ring_num; i++) { ++ ring = &sp->mac_control.rings[i]; ++ if ((val64 & RMAC_HIGH_UP_CROSSED_Qn(i)) && ++ !(val64 & RMAC_LOW_DOWN_CROSSED_Qn(i))) { ++ if (++ring->queue_pause_cnt >= ++ PAUSE_STUCK_THRESHOLD) ++ { ++ ring->queue_pause_cnt = 0; ++ /* No errors if packets received */ ++ if (ring->rx_packets == ++ ring->prev_rx_packets) ++ goto reset; ++ } ++ } else ++ ring->queue_pause_cnt = 0; ++ ++ ring->prev_rx_packets = ring->rx_packets; ++ } ++ ++ return; ++reset: ++ if (sp->exec_mode) { ++ sp->mac_stat_info->rx_stuck_cnt++; ++ if (sp->config.rst_q_stuck) { ++ s2io_stop_all_tx_queue(sp); ++ schedule_work(&sp->rst_timer_task); ++ } ++ } else ++ sp->serious_err = 1; + } + + static void +@@ -4323,39 +6263,169 @@ + struct s2io_nic *sp = (struct s2io_nic *)data; + struct net_device *dev = sp->dev; + +- s2io_handle_errors(dev); +- mod_timer(&sp->alarm_timer, jiffies + HZ / 2); +-} +- ++ if (is_s2io_card_up(sp)) { ++ if (++sp->chk_device_error_count >= MAX_DEVICE_CHECK_COUNT){ ++ s2io_handle_errors(dev); ++ sp->chk_device_error_count = 0; ++ } ++ ++ if ((sp->device_type == XFRAME_II_DEVICE) ++ && (sp->device_sub_type == XFRAME_E_DEVICE)) { ++ ++ if (++sp->chk_rx_queue_count >= ++ MAX_RX_QUEUE_CHECK_COUNT) { ++ poll_queue_stuck(dev); ++ sp->chk_rx_queue_count = 0; ++ } ++ } ++ ++ if (++sp->chk_dte_count >= MAX_DTE_CHECK_COUNT) { ++ s2io_chk_dte_rx_local_fault(dev); ++ sp->chk_dte_count = 0; ++ } ++ } ++ ++ mod_timer(&sp->alarm_timer, jiffies + HZ/10); ++} ++ ++/** ++ * dynamic_rti - Modifies receive traffic interrupt scheme during run time ++ * @ring: pointer to receive ring structure ++ * Description: The function configures receive traffic interrupts ++ * Return Value: Nothing ++ */ ++ ++static void dynamic_rti(struct ring_info *ring) ++{ ++ struct s2io_nic *nic = ring->nic; ++ struct XENA_dev_config __iomem *bar0 = nic->bar0; ++ u64 val64; ++ ++ val64 = RTI_DATA1_MEM_RX_TIMER_VAL(ring->rx_timer_val); ++ ++ val64 |= RTI_DATA1_MEM_RX_URNG_A(ring->urange_a) | ++ RTI_DATA1_MEM_RX_URNG_B(ring->urange_b) | ++ RTI_DATA1_MEM_RX_URNG_C(ring->urange_c) | ++ RTI_DATA1_MEM_RX_TIMER_AC_EN; ++ writeq(val64, &bar0->rti_data1_mem); ++ ++ val64 = RTI_DATA2_MEM_RX_UFC_A(ring->ufc_a) | ++ RTI_DATA2_MEM_RX_UFC_B(ring->ufc_b)| ++ RTI_DATA2_MEM_RX_UFC_C(ring->ufc_c)| ++ RTI_DATA2_MEM_RX_UFC_D(ring->ufc_d); ++ writeq(val64, &bar0->rti_data2_mem); ++ ++ val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD ++ | RTI_CMD_MEM_OFFSET(ring->ring_no); ++ writeq(val64, &bar0->rti_command_mem); ++ ++ return; ++} ++ ++/** ++ * adaptive_coalesce_rx_interrupts - Changes the interrupt coalescing ++ * if the interrupts are not within a range ++ * @ring: pointer to receive ring structure ++ * Description: The function increases of decreases the packet counts within ++ * the ranges of traffic utilization, if the interrupts due to this ring are ++ * not within a fixed range. ++ * Return Value: Nothing ++ */ ++static void adaptive_coalesce_rx_interrupts(struct ring_info *ring) ++{ ++ int cnt = 0; ++ ++ ring->interrupt_count++; ++ if (jiffies > ring->jiffies + HZ/100) { ++ ring->jiffies = jiffies; ++ if (ring->interrupt_count > MAX_INTERRUPT_COUNT) { ++ if (ring->ufc_a < MAX_RX_UFC_A) { ++ ring->ufc_a++; ++ ring->rx_timer_val >>= 5; ++ if (ring->rx_timer_val <= 0) ++ ring->rx_timer_val = MIN_RX_TIMER_VAL; ++ cnt++; ++ } ++ } else if (ring->interrupt_count < MAX_INTERRUPT_COUNT) { ++ if (ring->ufc_a > MIN_RX_UFC_A) { ++ ring->ufc_a--; ++ ring->rx_timer_val <<= 5; ++ if (ring->rx_timer_val > ++ ring->rx_timer_val_saved) ++ ring->rx_timer_val = ++ ring->rx_timer_val_saved; ++ cnt++; ++ } ++ } ++ ++ if (cnt) ++ dynamic_rti(ring); ++ ++ ring->interrupt_count = 0; ++ } ++} ++ ++#ifdef CONFIG_PCI_MSI ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++static irqreturn_t ++s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs) ++#else + static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id) ++#endif + { + struct ring_info *ring = (struct ring_info *)dev_id; + struct s2io_nic *sp = ring->nic; + struct XENA_dev_config __iomem *bar0 = sp->bar0; + struct net_device *dev = sp->dev; + +- if (unlikely(!is_s2io_card_up(sp))) ++ if (IRQ_HANDLED == S2IO_RING_IN_USE(ring)) + return IRQ_HANDLED; + +- if (sp->config.napi) { ++ /*Increment the per ring msix interrupt counter*/ ++ ring->rx_ring_stat->rx_msix_cnt++; ++ ++ /* In debug mode, return if a serious error has occured */ ++ if (sp->serious_err && (0 == sp->exec_mode)) { ++ S2IO_RING_DONE(ring); ++ return IRQ_NONE; ++ } ++ ++ if (unlikely(!is_s2io_card_up(sp))) { ++ S2IO_RING_DONE(ring); ++ return IRQ_NONE; ++ } ++ ++ if (ring->aggr_ack) ++ adaptive_coalesce_rx_interrupts(ring); ++ ++ if (ring->config_napi) { + u8 __iomem *addr = NULL; + u8 val8 = 0; +- + addr = (u8 __iomem *)&bar0->xmsi_mask_reg; + addr += (7 - ring->ring_no); + val8 = (ring->ring_no == 0) ? 0x7f : 0xff; + writeb(val8, addr); + val8 = readb(addr); +- netif_rx_schedule(dev, &ring->napi); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) ++ s2io_netif_do_rx_schedule(dev, &ring->napi); ++#else ++ s2io_netif_do_rx_schedule(dev, NULL); ++#endif + } else { + rx_intr_handler(ring, 0); +- s2io_chk_rx_buffers(sp, ring); +- } +- ++ s2io_chk_rx_buffers(ring); ++ } ++ ++ S2IO_RING_DONE(ring); + return IRQ_HANDLED; + } + ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)) ++static irqreturn_t ++s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs) ++#else + static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id) ++#endif + { + int i; + struct fifo_info *fifos = (struct fifo_info *)dev_id; +@@ -4364,34 +6434,54 @@ + struct config_param *config = &sp->config; + u64 reason; + +- if (unlikely(!is_s2io_card_up(sp))) ++ if (IRQ_HANDLED == S2IO_FIFO_IN_USE(sp)) ++ return IRQ_HANDLED; ++ ++ /*Increment the fifo interrupt counter*/ ++ sp->tx_intr_cnt++; ++ ++ /* In debug mode, return if a serious error has occured */ ++ if (sp->serious_err && (0 == sp->exec_mode)) { ++ S2IO_FIFO_DONE(sp); + return IRQ_NONE; ++ } ++ ++ if (unlikely(!is_s2io_card_up(sp))) { ++ S2IO_FIFO_DONE(sp); ++ return IRQ_NONE; ++ } + + reason = readq(&bar0->general_int_status); ++ + if (unlikely(reason == S2IO_MINUS_ONE)) + /* Nothing much can be done. Get out */ + return IRQ_HANDLED; + +- if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) { ++ if (reason & (GEN_INTR_TXTRAFFIC|GEN_INTR_TXPIC)) ++ { + writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); ++ ++ if (reason & GEN_INTR_TXTRAFFIC) ++ writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); ++ ++ for (i = 0; i < config->tx_fifo_num; i++) ++ tx_intr_handler(&fifos[i]); + + if (reason & GEN_INTR_TXPIC) + s2io_txpic_intr_handle(sp); + +- if (reason & GEN_INTR_TXTRAFFIC) +- writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); +- +- for (i = 0; i < config->tx_fifo_num; i++) +- tx_intr_handler(&fifos[i]); +- + writeq(sp->general_int_mask, &bar0->general_int_mask); + readl(&bar0->general_int_status); ++ ++ S2IO_FIFO_DONE(sp); + return IRQ_HANDLED; + } +- /* The interrupt was not raised by us */ ++ ++ S2IO_FIFO_DONE(sp); + return IRQ_NONE; + } + ++#endif + static void s2io_txpic_intr_handle(struct s2io_nic *sp) + { + struct XENA_dev_config __iomem *bar0 = sp->bar0; +@@ -4401,7 +6491,7 @@ + if (val64 & PIC_INT_GPIO) { + val64 = readq(&bar0->gpio_int_reg); + if ((val64 & GPIO_INT_REG_LINK_DOWN) && +- (val64 & GPIO_INT_REG_LINK_UP)) { ++ (val64 & GPIO_INT_REG_LINK_UP)) { + /* + * This is unstable state so clear both up/down + * interrupt and adapter to re-evaluate the link state. +@@ -4413,18 +6503,14 @@ + val64 &= ~(GPIO_INT_MASK_LINK_UP | + GPIO_INT_MASK_LINK_DOWN); + writeq(val64, &bar0->gpio_int_mask); +- } +- else if (val64 & GPIO_INT_REG_LINK_UP) { +- val64 = readq(&bar0->adapter_status); +- /* Enable Adapter */ ++ } else if (val64 & GPIO_INT_REG_LINK_UP) { ++ /* Enable Adapter */ + val64 = readq(&bar0->adapter_control); + val64 |= ADAPTER_CNTL_EN; + writeq(val64, &bar0->adapter_control); + val64 |= ADAPTER_LED_ON; + writeq(val64, &bar0->adapter_control); +- if (!sp->device_enabled_once) +- sp->device_enabled_once = 1; +- ++ sp->device_enabled_once = TRUE; + s2io_link(sp, LINK_UP); + /* + * unmask link down interrupt and mask link-up +@@ -4435,25 +6521,23 @@ + val64 |= GPIO_INT_MASK_LINK_UP; + writeq(val64, &bar0->gpio_int_mask); + +- }else if (val64 & GPIO_INT_REG_LINK_DOWN) { +- val64 = readq(&bar0->adapter_status); ++ } else if (val64 & GPIO_INT_REG_LINK_DOWN) { + s2io_link(sp, LINK_DOWN); +- /* Link is down so unmaks link up interrupt */ ++ /* Link is down so unmask link up interrupt */ + val64 = readq(&bar0->gpio_int_mask); + val64 &= ~GPIO_INT_MASK_LINK_UP; + val64 |= GPIO_INT_MASK_LINK_DOWN; + writeq(val64, &bar0->gpio_int_mask); +- + /* turn off LED */ + val64 = readq(&bar0->adapter_control); +- val64 = val64 &(~ADAPTER_LED_ON); ++ val64 = val64 & (~ADAPTER_LED_ON); + writeq(val64, &bar0->adapter_control); + } + } +- val64 = readq(&bar0->gpio_int_mask); +-} +- +-/** ++ readq(&bar0->gpio_int_mask); ++} ++ ++ /** + * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter + * @value: alarm bits + * @addr: address value +@@ -4463,50 +6547,47 @@ + * 1 - if alarm bit set + * 0 - if alarm bit is not set + */ +-static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr, +- unsigned long long *cnt) ++static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr, ++ unsigned long long *cnt) + { + u64 val64; + val64 = readq(addr); +- if ( val64 & value ) { ++ if (val64 & value) { + writeq(val64, addr); + (*cnt)++; + return 1; + } + return 0; +- +-} +- +-/** ++} ++ ++ /** + * s2io_handle_errors - Xframe error indication handler + * @nic: device private variable +- * Description: Handle alarms such as loss of link, single or +- * double ECC errors, critical and serious errors. +- * Return Value: +- * NONE +- */ +-static void s2io_handle_errors(void * dev_id) ++ * Description: Handle alarms such as loss of link, single or double ECC ++ * errors, critical and serious errors. ++ * Return Value: NONE ++ */ ++static void s2io_handle_errors(void *dev_id) + { + struct net_device *dev = (struct net_device *) dev_id; +- struct s2io_nic *sp = dev->priv; +- struct XENA_dev_config __iomem *bar0 = sp->bar0; +- u64 temp64 = 0,val64=0; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ u64 temp64 = 0, val64 = 0; + int i = 0; +- +- struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat; +- struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat; ++ struct xpakStat *stats = sp->xpak_stat; ++ struct mac_info *mac_control; ++ mac_control = &sp->mac_control; + + if (!is_s2io_card_up(sp)) + return; + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) + if (pci_channel_offline(sp->pdev)) + return; +- +- memset(&sw_stat->ring_full_cnt, 0, +- sizeof(sw_stat->ring_full_cnt)); ++#endif + + /* Handling the XPAK counters update */ +- if(stats->xpak_timer_count < 72000) { ++ if (stats->xpak_timer_count < 72000) { + /* waiting for an hour */ + stats->xpak_timer_count++; + } else { +@@ -4525,97 +6606,114 @@ + + /* In case of a serious error, the device will be Reset. */ + if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source, +- &sw_stat->serious_err_cnt)) ++ &sp->mac_stat_info->serious_err_cnt)) + goto reset; + + /* Check for data parity error */ + if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg, +- &sw_stat->parity_err_cnt)) ++ &sp->mac_stat_info->parity_err_cnt)) + goto reset; ++ ++ val64 = readq(&bar0->gpio_int_reg); ++ if (val64 & GPIO_INT_REG_DP_ERR_INT) { ++ sp->mac_stat_info->parity_err_cnt++; ++ goto reset; ++ } + + /* Check for ring full counter */ + if (sp->device_type == XFRAME_II_DEVICE) { +- val64 = readq(&bar0->ring_bump_counter1); +- for (i=0; i<4; i++) { +- temp64 = ( val64 & vBIT(0xFFFF,(i*16),16)); ++ for (i = 0; i < sp->config.rx_ring_num; i++) { ++ if (i < 4) ++ val64 = readq(&bar0->ring_bump_counter1); ++ else ++ val64 = readq(&bar0->ring_bump_counter2); ++ temp64 = (val64 & vBIT(0xFFFF, (i*16), 16)); + temp64 >>= 64 - ((i+1)*16); +- sw_stat->ring_full_cnt[i] += temp64; +- } +- +- val64 = readq(&bar0->ring_bump_counter2); +- for (i=0; i<4; i++) { +- temp64 = ( val64 & vBIT(0xFFFF,(i*16),16)); +- temp64 >>= 64 - ((i+1)*16); +- sw_stat->ring_full_cnt[i+4] += temp64; +- } +- } ++ mac_control->rings[i].rx_ring_stat->ring_full_cnt += ++ temp64; ++ } ++ } ++ + + val64 = readq(&bar0->txdma_int_status); + /*check for pfc_err*/ + if (val64 & TXDMA_PFC_INT) { +- if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM| +- PFC_MISC_0_ERR | PFC_MISC_1_ERR| ++ if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM | ++ PFC_MISC_0_ERR | PFC_MISC_1_ERR | + PFC_PCIX_ERR, &bar0->pfc_err_reg, +- &sw_stat->pfc_err_cnt)) ++ &sp->mac_stat_info->pfc_err_cnt)) + goto reset; + do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg, +- &sw_stat->pfc_err_cnt); ++ &sp->mac_stat_info->pfc_err_cnt); + } + + /*check for tda_err*/ + if (val64 & TXDMA_TDA_INT) { +- if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM | ++ if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | ++ TDA_SM0_ERR_ALARM | + TDA_SM1_ERR_ALARM, &bar0->tda_err_reg, +- &sw_stat->tda_err_cnt)) ++ &sp->mac_stat_info->tda_err_cnt)) + goto reset; + do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR, +- &bar0->tda_err_reg, &sw_stat->tda_err_cnt); ++ &bar0->tda_err_reg, ++ &sp->mac_stat_info->tda_err_cnt); + } + /*check for pcc_err*/ + if (val64 & TXDMA_PCC_INT) { +- if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM +- | PCC_N_SERR | PCC_6_COF_OV_ERR +- | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR +- | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR +- | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg, +- &sw_stat->pcc_err_cnt)) +- goto reset; ++ val64 = readq(&bar0->pcc_err_reg); ++ temp64 = PCC_TXB_ECC_DB_ERR ++ | PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM ++ | PCC_N_SERR | PCC_6_COF_OV_ERR ++ | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR ++ | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR ++ | PCC_TXB_ECC_DB_ERR; ++ if (val64 & temp64) { ++ writeq(val64, &bar0->pcc_err_reg); ++ sp->mac_stat_info->pcc_err_cnt++; ++ if (val64 & PCC_N_SERR) ++ sp->serious_err = 1; ++ goto reset; ++ } + do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR, +- &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt); ++ &bar0->pcc_err_reg, ++ &sp->mac_stat_info->pcc_err_cnt); + } + + /*check for tti_err*/ + if (val64 & TXDMA_TTI_INT) { + if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg, +- &sw_stat->tti_err_cnt)) +- goto reset; +- do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR, +- &bar0->tti_err_reg, &sw_stat->tti_err_cnt); ++ &sp->mac_stat_info->tti_err_cnt)) ++ goto reset; ++ do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW, ++ &bar0->lso_err_reg, ++ &sp->mac_stat_info->tti_err_cnt); + } + + /*check for lso_err*/ + if (val64 & TXDMA_LSO_INT) { + if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT + | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM, +- &bar0->lso_err_reg, &sw_stat->lso_err_cnt)) ++ &bar0->lso_err_reg, ++ &sp->mac_stat_info->lso_err_cnt)) + goto reset; + do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW, +- &bar0->lso_err_reg, &sw_stat->lso_err_cnt); ++ &bar0->lso_err_reg, ++ &sp->mac_stat_info->lso_err_cnt); + } + + /*check for tpa_err*/ + if (val64 & TXDMA_TPA_INT) { + if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg, +- &sw_stat->tpa_err_cnt)) ++ &sp->mac_stat_info->tpa_err_cnt)) + goto reset; + do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg, +- &sw_stat->tpa_err_cnt); ++ &sp->mac_stat_info->tpa_err_cnt); + } + + /*check for sm_err*/ + if (val64 & TXDMA_SM_INT) { + if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg, +- &sw_stat->sm_err_cnt)) ++ &sp->mac_stat_info->sm_err_cnt)) + goto reset; + } + +@@ -4623,119 +6721,135 @@ + if (val64 & MAC_INT_STATUS_TMAC_INT) { + if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR, + &bar0->mac_tmac_err_reg, +- &sw_stat->mac_tmac_err_cnt)) ++ &sp->mac_stat_info->mac_tmac_err_cnt)) + goto reset; + do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR + | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR, + &bar0->mac_tmac_err_reg, +- &sw_stat->mac_tmac_err_cnt); ++ &sp->mac_stat_info->mac_tmac_err_cnt); ++ + } + + val64 = readq(&bar0->xgxs_int_status); + if (val64 & XGXS_INT_STATUS_TXGXS) { + if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR, + &bar0->xgxs_txgxs_err_reg, +- &sw_stat->xgxs_txgxs_err_cnt)) ++ &sp->mac_stat_info->xgxs_txgxs_err_cnt)) + goto reset; + do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR, + &bar0->xgxs_txgxs_err_reg, +- &sw_stat->xgxs_txgxs_err_cnt); ++ &sp->mac_stat_info->xgxs_txgxs_err_cnt); + } + + val64 = readq(&bar0->rxdma_int_status); + if (val64 & RXDMA_INT_RC_INT_M) { +- if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR +- | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM, +- &bar0->rc_err_reg, &sw_stat->rc_err_cnt)) ++ if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | ++ RC_FTC_ECC_DB_ERR | RC_PRCn_SM_ERR_ALARM | ++ RC_FTC_SM_ERR_ALARM, &bar0->rc_err_reg, ++ &sp->mac_stat_info->rc_err_cnt)) + goto reset; + do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR + | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg, +- &sw_stat->rc_err_cnt); ++ &sp->mac_stat_info->rc_err_cnt); + if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn + | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg, +- &sw_stat->prc_pcix_err_cnt)) +- goto reset; ++ &sp->mac_stat_info->prc_pcix_err_cnt)) ++ goto reset; ++ + do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn + | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg, +- &sw_stat->prc_pcix_err_cnt); ++ &sp->mac_stat_info->prc_pcix_err_cnt); + } + + if (val64 & RXDMA_INT_RPA_INT_M) { + if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR, +- &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt)) ++ &bar0->rpa_err_reg, ++ &sp->mac_stat_info->rpa_err_cnt)) + goto reset; + do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, +- &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt); ++ &bar0->rpa_err_reg, ++ &sp->mac_stat_info->rpa_err_cnt); + } + + if (val64 & RXDMA_INT_RDA_INT_M) { + if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR + | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM + | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR, +- &bar0->rda_err_reg, &sw_stat->rda_err_cnt)) ++ &bar0->rda_err_reg, ++ &sp->mac_stat_info->rda_err_cnt)) + goto reset; + do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR + | RDA_MISC_ERR | RDA_PCIX_ERR, +- &bar0->rda_err_reg, &sw_stat->rda_err_cnt); ++ &bar0->rda_err_reg, ++ &sp->mac_stat_info->rda_err_cnt); + } + + if (val64 & RXDMA_INT_RTI_INT_M) { + if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg, +- &sw_stat->rti_err_cnt)) ++ &sp->mac_stat_info->rti_err_cnt)) + goto reset; + do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR, +- &bar0->rti_err_reg, &sw_stat->rti_err_cnt); ++ &bar0->rti_err_reg, ++ &sp->mac_stat_info->rti_err_cnt); + } + + val64 = readq(&bar0->mac_int_status); + if (val64 & MAC_INT_STATUS_RMAC_INT) { + if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR, + &bar0->mac_rmac_err_reg, +- &sw_stat->mac_rmac_err_cnt)) ++ &sp->mac_stat_info->mac_rmac_err_cnt)) + goto reset; + do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR| + RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg, +- &sw_stat->mac_rmac_err_cnt); ++ &sp->mac_stat_info->mac_rmac_err_cnt); + } + + val64 = readq(&bar0->xgxs_int_status); + if (val64 & XGXS_INT_STATUS_RXGXS) { + if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, + &bar0->xgxs_rxgxs_err_reg, +- &sw_stat->xgxs_rxgxs_err_cnt)) ++ &sp->mac_stat_info->xgxs_rxgxs_err_cnt)) + goto reset; + } + + val64 = readq(&bar0->mc_int_status); +- if(val64 & MC_INT_STATUS_MC_INT) { ++ if (val64 & MC_INT_STATUS_MC_INT) { + if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg, +- &sw_stat->mc_err_cnt)) ++ &sp->mac_stat_info->mc_err_cnt)) + goto reset; + + /* Handling Ecc errors */ +- if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) { ++ val64 = readq(&bar0->mc_err_reg); ++ if (val64 & (MC_ERR_REG_ECC_ALL_SNG | ++ MC_ERR_REG_ECC_ALL_DBL)) { + writeq(val64, &bar0->mc_err_reg); + if (val64 & MC_ERR_REG_ECC_ALL_DBL) { +- sw_stat->double_ecc_errs++; ++ sp->mac_stat_info->double_ecc_errs++; + if (sp->device_type != XFRAME_II_DEVICE) { +- /* +- * Reset XframeI only if critical error +- */ ++ /* Reset XframeI only if critical ++ * error occured ++ */ + if (val64 & + (MC_ERR_REG_MIRI_ECC_DB_ERR_0 | + MC_ERR_REG_MIRI_ECC_DB_ERR_1)) +- goto reset; ++ goto reset; + } + } else +- sw_stat->single_ecc_errs++; ++ sp->mac_stat_info->single_ecc_errs++; ++#ifdef RX_ERR_DBG ++ sp->ecc_flag = 1; ++#endif + } + } + return; + + reset: + s2io_stop_all_tx_queue(sp); +- schedule_work(&sp->rst_timer_task); +- sw_stat->soft_reset_cnt++; ++ ++ if (sp->exec_mode) ++ schedule_work(&sp->rst_timer_task); ++ else ++ sp->serious_err = 1; + return; + } + +@@ -4743,6 +6857,7 @@ + * s2io_isr - ISR handler of the device . + * @irq: the irq of the device. + * @dev_id: a void pointer to the dev structure of the NIC. ++ * @pt_regs: pointer to the registers pushed on the stack. + * Description: This function is the ISR handler of the device. It + * identifies the reason for the interrupt and calls the relevant + * service routines. As a contongency measure, this ISR allocates the +@@ -4752,21 +6867,31 @@ + * IRQ_HANDLED: will be returned if IRQ was handled by this routine + * IRQ_NONE: will be returned if interrupt is not from our device + */ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs) ++#else + static irqreturn_t s2io_isr(int irq, void *dev_id) ++#endif + { + struct net_device *dev = (struct net_device *) dev_id; +- struct s2io_nic *sp = dev->priv; +- struct XENA_dev_config __iomem *bar0 = sp->bar0; +- int i; +- u64 reason = 0; +- struct mac_info *mac_control; +- struct config_param *config; +- ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ int i; ++ u64 reason; ++ struct mac_info *mac_control; ++ struct config_param *config; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) + /* Pretend we handled any irq's from a disconnected card */ + if (pci_channel_offline(sp->pdev)) + return IRQ_NONE; +- +- if (!is_s2io_card_up(sp)) ++#endif ++ ++ /* In debug mode, return if a serious error has occured */ ++ if (sp->serious_err && (0 == sp->exec_mode)) ++ return IRQ_NONE; ++ ++ if (unlikely(!is_s2io_card_up(sp))) + return IRQ_NONE; + + mac_control = &sp->mac_control; +@@ -4778,34 +6903,48 @@ + * 1. Rx of packet. + * 2. Tx complete. + * 3. Link down. ++ * 4. Error in any functional blocks of the NIC. + */ + reason = readq(&bar0->general_int_status); + +- if (unlikely(reason == S2IO_MINUS_ONE) ) { ++ if (unlikely(reason == S2IO_MINUS_ONE)) { + /* Nothing much can be done. Get out */ + return IRQ_HANDLED; + } + + if (reason & (GEN_INTR_RXTRAFFIC | +- GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) +- { ++ GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) { + writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); + + if (config->napi) { + if (reason & GEN_INTR_RXTRAFFIC) { +- netif_rx_schedule(dev, &sp->napi); ++ sp->rx_inta_cnt++; ++ ++ for (i = 0; i < config->rx_ring_num; i++) { ++ struct ring_info *ring = &mac_control->rings[i]; ++ if (ring->aggr_ack) ++ adaptive_coalesce_rx_interrupts(ring); ++ } ++ + writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask); + writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); + readl(&bar0->rx_traffic_int); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) ++ s2io_netif_do_rx_schedule(dev, &sp->napi); ++#else ++ s2io_netif_do_rx_schedule(dev, NULL); ++#endif + } + } else { + /* + * rx_traffic_int reg is an R1 register, writing all 1's + * will ensure that the actual interrupt causing bit +- * get's cleared and hence a read can be avoided. +- */ +- if (reason & GEN_INTR_RXTRAFFIC) ++ * gets cleared and hence a read can be avoided. ++ */ ++ if (reason & GEN_INTR_RXTRAFFIC) { ++ sp->rx_inta_cnt++; + writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); ++ } + + for (i = 0; i < config->rx_ring_num; i++) + rx_intr_handler(&mac_control->rings[i], 0); +@@ -4816,8 +6955,10 @@ + * will ensure that the actual interrupt causing bit get's + * cleared and hence a read can be avoided. + */ +- if (reason & GEN_INTR_TXTRAFFIC) ++ if (reason & GEN_INTR_TXTRAFFIC) { ++ sp->tx_intr_cnt++; + writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); ++ } + + for (i = 0; i < config->tx_fifo_num; i++) + tx_intr_handler(&mac_control->fifos[i]); +@@ -4828,17 +6969,14 @@ + /* + * Reallocate the buffers from the interrupt handler itself. + */ +- if (!config->napi) { ++ if (!config->napi) + for (i = 0; i < config->rx_ring_num; i++) +- s2io_chk_rx_buffers(sp, &mac_control->rings[i]); +- } ++ s2io_chk_rx_buffers(&mac_control->rings[i]); ++ + writeq(sp->general_int_mask, &bar0->general_int_mask); + readl(&bar0->general_int_status); +- + return IRQ_HANDLED; +- +- } +- else if (!reason) { ++ } else if (unlikely(!reason)) { + /* The interrupt was not raised by us */ + return IRQ_NONE; + } +@@ -4854,6 +6992,11 @@ + struct XENA_dev_config __iomem *bar0 = sp->bar0; + u64 val64; + int cnt = 0; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) ++ if (pci_channel_offline(sp->pdev)) ++ return; ++#endif + + if (is_s2io_card_up(sp)) { + /* Apprx 30us on a 133 MHz bus */ +@@ -4863,7 +7006,7 @@ + do { + udelay(100); + val64 = readq(&bar0->stat_cfg); +- if (!(val64 & s2BIT(0))) ++ if (!(val64 & S2BIT(0))) + break; + cnt++; + if (cnt == 5) +@@ -4884,11 +7027,17 @@ + + static struct net_device_stats *s2io_get_stats(struct net_device *dev) + { +- struct s2io_nic *sp = dev->priv; +- struct mac_info *mac_control; +- struct config_param *config; +- int i; +- ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ struct mac_info *mac_control; ++ struct stat_block *stats_info = sp->mac_control.stats_info; ++ struct config_param *config; ++ int i; ++ struct net_device_stats *stats = NULL; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22)) ++ stats = &sp->prev_stats; ++#else ++ stats = &dev->stats; ++#endif + + mac_control = &sp->mac_control; + config = &sp->config; +@@ -4897,41 +7046,54 @@ + s2io_updt_stats(sp); + + /* Using sp->stats as a staging area, because reset (due to mtu +- change, for example) will clear some hardware counters */ +- dev->stats.tx_packets += +- le32_to_cpu(mac_control->stats_info->tmac_frms) - ++ change, for example) will clear some hardware counters */ ++ stats->tx_packets += ++ le32_to_cpu(mac_control->stats_info->tmac_frms) - + sp->stats.tx_packets; ++ + sp->stats.tx_packets = +- le32_to_cpu(mac_control->stats_info->tmac_frms); +- dev->stats.tx_errors += ++ (u64)le32_to_cpu(stats_info->tmac_frms_oflow) << 32 | ++ le32_to_cpu(stats_info->tmac_frms); ++ ++ stats->tx_errors += + le32_to_cpu(mac_control->stats_info->tmac_any_err_frms) - + sp->stats.tx_errors; ++ + sp->stats.tx_errors = +- le32_to_cpu(mac_control->stats_info->tmac_any_err_frms); +- dev->stats.rx_errors += ++ (u64)le32_to_cpu(stats_info->tmac_any_err_frms_oflow) << 32 | ++ le32_to_cpu(stats_info->tmac_any_err_frms); ++ ++ stats->rx_errors += + le64_to_cpu(mac_control->stats_info->rmac_drop_frms) - + sp->stats.rx_errors; ++ + sp->stats.rx_errors = +- le64_to_cpu(mac_control->stats_info->rmac_drop_frms); +- dev->stats.multicast = +- le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms) - ++ le64_to_cpu(stats_info->rmac_drop_frms); ++ ++ stats->multicast = ++ le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms) - + sp->stats.multicast; ++ + sp->stats.multicast = +- le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms); +- dev->stats.rx_length_errors = +- le64_to_cpu(mac_control->stats_info->rmac_long_frms) - ++ (u64)le32_to_cpu(stats_info->rmac_vld_mcst_frms_oflow) << 32 | ++ le32_to_cpu(stats_info->rmac_vld_mcst_frms); ++ ++ stats->rx_length_errors = ++ le64_to_cpu(mac_control->stats_info->rmac_long_frms) - + sp->stats.rx_length_errors; ++ + sp->stats.rx_length_errors = +- le64_to_cpu(mac_control->stats_info->rmac_long_frms); ++ le64_to_cpu(stats_info->rmac_long_frms); + + /* collect per-ring rx_packets and rx_bytes */ +- dev->stats.rx_packets = dev->stats.rx_bytes = 0; +- for (i = 0; i < config->rx_ring_num; i++) { +- dev->stats.rx_packets += mac_control->rings[i].rx_packets; +- dev->stats.rx_bytes += mac_control->rings[i].rx_bytes; +- } +- +- return (&dev->stats); ++ stats->rx_packets = stats->rx_bytes = 0; ++ ++ for (i = 0; i < config->rx_ring_num; i++) { ++ stats->rx_packets += mac_control->rings[i].rx_packets; ++ stats->rx_bytes += mac_control->rings[i].rx_bytes; ++ } ++ ++ return (stats); + } + + /** +@@ -4951,7 +7113,7 @@ + { + int i, j, prev_cnt; + struct dev_mc_list *mclist; +- struct s2io_nic *sp = dev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + struct XENA_dev_config __iomem *bar0 = sp->bar0; + u64 val64 = 0, multi_mac = 0x010203040506ULL, mask = + 0xfeffffffffffULL; +@@ -4971,25 +7133,25 @@ + writeq(val64, &bar0->rmac_addr_cmd_mem); + /* Wait till command completes */ + wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, +- RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, +- S2IO_BIT_RESET); ++ RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, ++ S2IO_BIT_RESET); + + sp->m_cast_flg = 1; + sp->all_multi_pos = config->max_mc_addr - 1; + } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) { + /* Disable all Multicast addresses */ + writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr), +- &bar0->rmac_addr_data0_mem); ++ &bar0->rmac_addr_data0_mem); + writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0), +- &bar0->rmac_addr_data1_mem); ++ &bar0->rmac_addr_data1_mem); + val64 = RMAC_ADDR_CMD_MEM_WE | +- RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | +- RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos); ++ RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | ++ RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos); + writeq(val64, &bar0->rmac_addr_cmd_mem); + /* Wait till command completes */ + wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, +- RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, +- S2IO_BIT_RESET); ++ RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, ++ S2IO_BIT_RESET); + + sp->m_cast_flg = 0; + sp->all_multi_pos = 0; +@@ -5006,20 +7168,13 @@ + writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); + writel((u32) (val64 >> 32), (add + 4)); + +- if (vlan_tag_strip != 1) { +- val64 = readq(&bar0->rx_pa_cfg); +- val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG; +- writeq(val64, &bar0->rx_pa_cfg); +- vlan_strip_flag = 0; +- } +- + val64 = readq(&bar0->mac_cfg); + sp->promisc_flg = 1; + DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n", +- dev->name); ++ dev->name); + } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) { + /* Remove the NIC from promiscuous mode */ +- add = &bar0->mac_cfg; ++ add = (void __iomem *) &bar0->mac_cfg; + val64 = readq(&bar0->mac_cfg); + val64 &= ~MAC_CFG_RMAC_PROM_ENABLE; + +@@ -5028,25 +7183,18 @@ + writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); + writel((u32) (val64 >> 32), (add + 4)); + +- if (vlan_tag_strip != 0) { +- val64 = readq(&bar0->rx_pa_cfg); +- val64 |= RX_PA_CFG_STRIP_VLAN_TAG; +- writeq(val64, &bar0->rx_pa_cfg); +- vlan_strip_flag = 1; +- } +- + val64 = readq(&bar0->mac_cfg); + sp->promisc_flg = 0; + DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", +- dev->name); ++ dev->name); + } + + /* Update individual M_CAST address list */ + if ((!sp->m_cast_flg) && dev->mc_count) { + if (dev->mc_count > +- (config->max_mc_addr - config->max_mac_addr)) { ++ (config->max_mc_addr - config->max_mac_addr)) { + DBG_PRINT(ERR_DBG, "%s: No more Rx filters ", +- dev->name); ++ dev->name); + DBG_PRINT(ERR_DBG, "can be added, please enable "); + DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n"); + return; +@@ -5058,21 +7206,20 @@ + /* Clear out the previous list of Mc in the H/W. */ + for (i = 0; i < prev_cnt; i++) { + writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr), +- &bar0->rmac_addr_data0_mem); ++ &bar0->rmac_addr_data0_mem); + writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL), + &bar0->rmac_addr_data1_mem); + val64 = RMAC_ADDR_CMD_MEM_WE | +- RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | +- RMAC_ADDR_CMD_MEM_OFFSET +- (config->mc_start_offset + i); ++ RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | ++ RMAC_ADDR_CMD_MEM_OFFSET ++ (config->mc_start_offset + i); + writeq(val64, &bar0->rmac_addr_cmd_mem); + + /* Wait for command completes */ + if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, +- RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, +- S2IO_BIT_RESET)) { +- DBG_PRINT(ERR_DBG, "%s: Adding ", +- dev->name); ++ RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, ++ S2IO_BIT_RESET)) { ++ DBG_PRINT(ERR_DBG, "%s: Adding ", dev->name); + DBG_PRINT(ERR_DBG, "Multicasts failed\n"); + return; + } +@@ -5080,9 +7227,7 @@ + + /* Create the new Rx filter list and update the same in H/W. */ + for (i = 0, mclist = dev->mc_list; i < dev->mc_count; +- i++, mclist = mclist->next) { +- memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr, +- ETH_ALEN); ++ i++, mclist = mclist->next) { + mac_addr = 0; + for (j = 0; j < ETH_ALEN; j++) { + mac_addr |= mclist->dmi_addr[j]; +@@ -5090,21 +7235,20 @@ + } + mac_addr >>= 8; + writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr), +- &bar0->rmac_addr_data0_mem); ++ &bar0->rmac_addr_data0_mem); + writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL), + &bar0->rmac_addr_data1_mem); + val64 = RMAC_ADDR_CMD_MEM_WE | +- RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | +- RMAC_ADDR_CMD_MEM_OFFSET +- (i + config->mc_start_offset); ++ RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | ++ RMAC_ADDR_CMD_MEM_OFFSET ++ (i + config->mc_start_offset); + writeq(val64, &bar0->rmac_addr_cmd_mem); + + /* Wait for command completes */ + if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, +- RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, +- S2IO_BIT_RESET)) { +- DBG_PRINT(ERR_DBG, "%s: Adding ", +- dev->name); ++ RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, ++ S2IO_BIT_RESET)) { ++ DBG_PRINT(ERR_DBG, "%s: Adding ", dev->name); + DBG_PRINT(ERR_DBG, "Multicasts failed\n"); + return; + } +@@ -5112,10 +7256,10 @@ + } + } + +-/* read from CAM unicast & multicast addresses and store it in +- * def_mac_addr structure +- */ +-void do_s2io_store_unicast_mc(struct s2io_nic *sp) ++/* read from CAM unicast & multicast addresses and store it in def_mac_addr ++* structure ++*/ ++static void do_s2io_store_unicast_mc(struct s2io_nic *sp) + { + int offset; + u64 mac_addr = 0x0; +@@ -5131,7 +7275,9 @@ + } + } + +-/* restore unicast & multicast MAC to CAM from def_mac_addr structure */ ++/* restore unicast MAC addresses(0-15 entries)& multicast(16-31) ++ * to CAM from def_mac_addr structure ++ **/ + static void do_s2io_restore_unicast_mc(struct s2io_nic *sp) + { + int offset; +@@ -5147,7 +7293,9 @@ + do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr); + } + +-/* add a multicast MAC address to CAM */ ++/* add a multicast MAC address to CAM. CAM entries 16-31 are used to ++ * store multicast MAC entries ++ **/ + static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr) + { + int i; +@@ -5171,10 +7319,10 @@ + if (tmp64 == mac_addr) + return SUCCESS; + } ++ + if (i == config->max_mc_addr) { +- DBG_PRINT(ERR_DBG, +- "CAM full no space left for multicast MAC\n"); +- return FAILURE; ++ DBG_PRINT(ERR_DBG, "CAM full no space left for multicast MAC\n"); ++ return FAILURE; + } + /* Update the internal structure with this new mac address */ + do_s2io_copy_mac_addr(sp, i, mac_addr); +@@ -5205,19 +7353,20 @@ + } + return SUCCESS; + } ++ + /* deletes a specified unicast/multicast mac entry from CAM */ + static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr) + { +- int offset; ++ int off; + u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64; + struct config_param *config = &sp->config; + +- for (offset = 1; +- offset < config->max_mc_addr; offset++) { +- tmp64 = do_s2io_read_unicast_mc(sp, offset); ++ for (off = 1; ++ off < config->max_mc_addr; off++) { ++ tmp64 = do_s2io_read_unicast_mc(sp, off); + if (tmp64 == addr) { + /* disable the entry by writing 0xffffffffffffULL */ +- if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE) ++ if (do_s2io_add_mac(sp, dis_addr, off) == FAILURE) + return FAILURE; + /* store the new mac list from CAM */ + do_s2io_store_unicast_mc(sp); +@@ -5268,6 +7417,7 @@ + /* store the MAC address in CAM */ + return (do_s2io_prog_unicast(dev, dev->dev_addr)); + } ++ + /** + * do_s2io_prog_unicast - Programs the Xframe mac address + * @dev : pointer to the device structure. +@@ -5280,7 +7430,7 @@ + + static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr) + { +- struct s2io_nic *sp = dev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + register u64 mac_addr = 0, perm_addr = 0; + int i; + u64 tmp64; +@@ -5297,6 +7447,9 @@ + perm_addr <<= 8; + perm_addr |= sp->def_mac_addr[0].mac_addr[i]; + } ++ /* is addr is 0 or broadcast fail open */ ++ if ((0 == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY)) ++ return FAILURE; + + /* check if the dev_addr is different than perm_addr */ + if (mac_addr == perm_addr) +@@ -5326,7 +7479,8 @@ + + /** + * s2io_ethtool_sset - Sets different link parameters. +- * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. ++ * @sp : private member of the device structure, which is a pointer to the ++ * s2io_nic structure. + * @info: pointer to the structure with parameters given by ethtool to set + * link information. + * Description: +@@ -5339,11 +7493,12 @@ + static int s2io_ethtool_sset(struct net_device *dev, + struct ethtool_cmd *info) + { +- struct s2io_nic *sp = dev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + if ((info->autoneg == AUTONEG_ENABLE) || +- (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL)) ++ (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL)) + return -EINVAL; +- else { ++ ++ if (netif_running(dev)) { + s2io_close(sp->dev); + s2io_open(sp->dev); + } +@@ -5365,16 +7520,23 @@ + + static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info) + { +- struct s2io_nic *sp = dev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); +- info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); ++#ifdef ADVERTISED_10000baseT_Full ++ info->advertising = ADVERTISED_10000baseT_Full; ++#else ++ info->advertising = SUPPORTED_10000baseT_Full; ++#endif ++#ifdef ADVERTISED_FIBRE ++ info->advertising |= ADVERTISED_FIBRE; ++#else ++ info->advertising |= SUPPORTED_FIBRE; ++#endif + info->port = PORT_FIBRE; +- +- /* info->transceiver */ + info->transceiver = XCVR_EXTERNAL; + + if (netif_carrier_ok(sp->dev)) { +- info->speed = 10000; ++ info->speed = SPEED_10000; + info->duplex = DUPLEX_FULL; + } else { + info->speed = -1; +@@ -5400,7 +7562,7 @@ + static void s2io_ethtool_gdrvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) + { +- struct s2io_nic *sp = dev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + + strncpy(info->driver, s2io_driver_name, sizeof(info->driver)); + strncpy(info->version, s2io_driver_version, sizeof(info->version)); +@@ -5408,6 +7570,26 @@ + strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info)); + info->regdump_len = XENA_REG_SPACE; + info->eedump_len = XENA_EEPROM_SPACE; ++ info->testinfo_len = S2IO_TEST_LEN; ++#ifdef ETHTOOL_GSTATS ++#ifdef TITAN_LEGACY ++ if (sp->device_type == TITAN_DEVICE) ++ info->n_stats = S2IO_TITAN_STAT_LEN; ++ else ++#endif ++ { ++ if (sp->device_type == XFRAME_I_DEVICE) ++ info->n_stats = XFRAME_I_STAT_LEN + ++ (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + ++ (sp->config.rx_ring_num * NUM_RX_SW_STAT); ++ else ++ info->n_stats = XFRAME_II_STAT_LEN + ++ (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + ++ (sp->config.rx_ring_num * NUM_RX_SW_STAT); ++ ++ info->n_stats += S2IO_DRIVER_DBG_STAT_LEN; ++ } ++#endif + } + + /** +@@ -5430,7 +7612,7 @@ + int i; + u64 reg; + u8 *reg_space = (u8 *) space; +- struct s2io_nic *sp = dev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + + regs->len = XENA_REG_SPACE; + regs->version = sp->pdev->subsystem_device; +@@ -5490,7 +7672,7 @@ + static int s2io_ethtool_idnic(struct net_device *dev, u32 data) + { + u64 val64 = 0, last_gpio_ctrl_val; +- struct s2io_nic *sp = dev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + struct XENA_dev_config __iomem *bar0 = sp->bar0; + u16 subid; + +@@ -5500,8 +7682,8 @@ + ((subid & 0xFF) < 0x07)) { + val64 = readq(&bar0->adapter_control); + if (!(val64 & ADAPTER_CNTL_EN)) { +- printk(KERN_ERR +- "Adapter Link down, cannot blink LED\n"); ++ DBG_PRINT(ERR_DBG, ++ "Adapter Link down, cannot blink LED\n"); + return -EFAULT; + } + } +@@ -5525,36 +7707,32 @@ + return 0; + } + ++ + static void s2io_ethtool_gringparam(struct net_device *dev, +- struct ethtool_ringparam *ering) +-{ +- struct s2io_nic *sp = dev->priv; +- int i,tx_desc_count=0,rx_desc_count=0; +- +- if (sp->rxd_mode == RXD_MODE_1) +- ering->rx_max_pending = MAX_RX_DESC_1; +- else if (sp->rxd_mode == RXD_MODE_3B) +- ering->rx_max_pending = MAX_RX_DESC_2; +- ++ struct ethtool_ringparam *ering) ++{ ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ int i, tx_desc_count = 0, rx_desc_count = 0; ++ ++ memset(ering, 0, sizeof(struct ethtool_ringparam)); + ering->tx_max_pending = MAX_TX_DESC; +- for (i = 0 ; i < sp->config.tx_fifo_num ; i++) ++ for (i = 0 ; i < sp->config.tx_fifo_num; i++) + tx_desc_count += sp->config.tx_cfg[i].fifo_len; + +- DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds); ++ DBG_PRINT(INFO_DBG, "\nmax txds : %d\n", sp->config.max_txds); + ering->tx_pending = tx_desc_count; ++ ++ for (i = 0; i < MAX_RX_RINGS; i++) ++ ering->rx_max_pending += rx_ring_sz[i] * rxd_count[sp->rxd_mode]; ++ ++ ering->rx_jumbo_max_pending = ering->rx_max_pending; + rx_desc_count = 0; + for (i = 0 ; i < sp->config.rx_ring_num ; i++) + rx_desc_count += sp->config.rx_cfg[i].num_rxd; +- + ering->rx_pending = rx_desc_count; +- ++ ering->rx_jumbo_pending = rx_desc_count; + ering->rx_mini_max_pending = 0; + ering->rx_mini_pending = 0; +- if(sp->rxd_mode == RXD_MODE_1) +- ering->rx_jumbo_max_pending = MAX_RX_DESC_1; +- else if (sp->rxd_mode == RXD_MODE_3B) +- ering->rx_jumbo_max_pending = MAX_RX_DESC_2; +- ering->rx_jumbo_pending = rx_desc_count; + } + + /** +@@ -5568,11 +7746,12 @@ + * void + */ + static void s2io_ethtool_getpause_data(struct net_device *dev, +- struct ethtool_pauseparam *ep) +-{ +- u64 val64; +- struct s2io_nic *sp = dev->priv; +- struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ struct ethtool_pauseparam *ep) ++{ ++ u64 val64; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ + + val64 = readq(&bar0->rmac_pause_cfg); + if (val64 & RMAC_PAUSE_GEN_ENABLE) +@@ -5595,10 +7774,10 @@ + */ + + static int s2io_ethtool_setpause_data(struct net_device *dev, +- struct ethtool_pauseparam *ep) +-{ +- u64 val64; +- struct s2io_nic *sp = dev->priv; ++ struct ethtool_pauseparam *ep) ++{ ++ u64 val64; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + struct XENA_dev_config __iomem *bar0 = sp->bar0; + + val64 = readq(&bar0->rmac_pause_cfg); +@@ -5631,7 +7810,7 @@ + */ + + #define S2IO_DEV_ID 5 +-static int read_eeprom(struct s2io_nic * sp, int off, u64 * data) ++static int read_eeprom(struct s2io_nic *sp, int off, u64 *data) + { + int ret = -1; + u32 exit_cnt = 0; +@@ -5639,9 +7818,9 @@ + struct XENA_dev_config __iomem *bar0 = sp->bar0; + + if (sp->device_type == XFRAME_I_DEVICE) { +- val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) | +- I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ | +- I2C_CONTROL_CNTL_START; ++ val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | ++ I2C_CONTROL_ADDR(off) | I2C_CONTROL_BYTE_CNT(0x3) | ++ I2C_CONTROL_READ | I2C_CONTROL_CNTL_START; + SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); + + while (exit_cnt < 5) { +@@ -5696,16 +7875,16 @@ + * 0 on success, -1 on failure. + */ + +-static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt) ++static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt) + { + int exit_cnt = 0, ret = -1; + u64 val64; + struct XENA_dev_config __iomem *bar0 = sp->bar0; + + if (sp->device_type == XFRAME_I_DEVICE) { +- val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) | +- I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) | +- I2C_CONTROL_CNTL_START; ++ val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | ++ I2C_CONTROL_ADDR(off) | I2C_CONTROL_BYTE_CNT(cnt) | ++ I2C_CONTROL_SET_DATA((u32)data) | I2C_CONTROL_CNTL_START; + SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); + + while (exit_cnt < 5) { +@@ -5745,18 +7924,19 @@ + } + return ret; + } ++ + static void s2io_vpd_read(struct s2io_nic *nic) + { + u8 *vpd_data; + u8 data; + int i=0, cnt, fail = 0; + int vpd_addr = 0x80; ++ struct swDbgStat *stats = nic->sw_dbg_stat; + + if (nic->device_type == XFRAME_II_DEVICE) { + strcpy(nic->product_name, "Xframe II 10GbE network adapter"); + vpd_addr = 0x80; +- } +- else { ++ } else { + strcpy(nic->product_name, "Xframe I 10GbE network adapter"); + vpd_addr = 0x50; + } +@@ -5764,10 +7944,10 @@ + + vpd_data = kmalloc(256, GFP_KERNEL); + if (!vpd_data) { +- nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++; +- return; +- } +- nic->mac_control.stats_info->sw_stat.mem_allocated += 256; ++ stats->mem_alloc_fail_cnt++; ++ return; ++ } ++ stats->mem_allocated += 256; + + for (i = 0; i < 256; i +=4 ) { + pci_write_config_byte(nic->pdev, (vpd_addr + 2), i); +@@ -5785,15 +7965,14 @@ + break; + } + pci_read_config_dword(nic->pdev, (vpd_addr + 4), +- (u32 *)&vpd_data[i]); +- } +- +- if(!fail) { ++ (u32 *)&vpd_data[i]); ++ } ++ if (!fail) { + /* read serial number of adapter */ + for (cnt = 0; cnt < 256; cnt++) { +- if ((vpd_data[cnt] == 'S') && +- (vpd_data[cnt+1] == 'N') && +- (vpd_data[cnt+2] < VPD_STRING_LEN)) { ++ if ((vpd_data[cnt] == 'S') && ++ (vpd_data[cnt+1] == 'N') && ++ (vpd_data[cnt+2] < VPD_STRING_LEN)) { + memset(nic->serial_num, 0, VPD_STRING_LEN); + memcpy(nic->serial_num, &vpd_data[cnt + 3], + vpd_data[cnt+2]); +@@ -5801,18 +7980,18 @@ + } + } + } +- + if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) { + memset(nic->product_name, 0, vpd_data[1]); + memcpy(nic->product_name, &vpd_data[3], vpd_data[1]); + } + kfree(vpd_data); +- nic->mac_control.stats_info->sw_stat.mem_freed += 256; ++ stats->mem_freed += 256; + } + + /** + * s2io_ethtool_geeprom - reads the value stored in the Eeprom. +- * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. ++ * @sp : private member of the device structure, which is a pointer to the ++ * s2io_nic structure. + * @eeprom : pointer to the user level structure provided by ethtool, + * containing all relevant information. + * @data_buf : user defined value to be written into Eeprom. +@@ -5824,11 +8003,11 @@ + */ + + static int s2io_ethtool_geeprom(struct net_device *dev, +- struct ethtool_eeprom *eeprom, u8 * data_buf) ++ struct ethtool_eeprom *eeprom, u8 *data_buf) + { + u32 i, valid; + u64 data; +- struct s2io_nic *sp = dev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + + eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16); + +@@ -5862,32 +8041,29 @@ + + static int s2io_ethtool_seeprom(struct net_device *dev, + struct ethtool_eeprom *eeprom, +- u8 * data_buf) ++ u8 *data_buf) + { + int len = eeprom->len, cnt = 0; + u64 valid = 0, data; +- struct s2io_nic *sp = dev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + + if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) { +- DBG_PRINT(ERR_DBG, +- "ETHTOOL_WRITE_EEPROM Err: Magic value "); +- DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n", +- eeprom->magic); ++ DBG_PRINT(ERR_DBG, "ETHTOOL_WRITE_EEPROM Err: Magic value "); ++ DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n", eeprom->magic); + return -EFAULT; + } + + while (len) { + data = (u32) data_buf[cnt] & 0x000000FF; +- if (data) { ++ if (data) + valid = (u32) (data << 24); +- } else ++ else + valid = data; + + if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) { +- DBG_PRINT(ERR_DBG, +- "ETHTOOL_WRITE_EEPROM Err: Cannot "); +- DBG_PRINT(ERR_DBG, +- "write into the specified offset\n"); ++ DBG_PRINT(ERR_DBG, "ETHTOOL_WRITE_EEPROM Err: "); ++ DBG_PRINT(ERR_DBG, ++ "Cannot write into the specified offset\n"); + return -EFAULT; + } + cnt++; +@@ -5910,7 +8086,7 @@ + * 0 on success. + */ + +-static int s2io_register_test(struct s2io_nic * sp, uint64_t * data) ++static int s2io_register_test(struct s2io_nic *sp, uint64_t *data) + { + struct XENA_dev_config __iomem *bar0 = sp->bar0; + u64 val64 = 0, exp_val; +@@ -5977,7 +8153,7 @@ + * 0 on success. + */ + +-static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data) ++static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data) + { + int fail = 0; + u64 ret_data, org_4F0, org_7F0; +@@ -6079,7 +8255,7 @@ + * 0 on success and -1 on failure. + */ + +-static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data) ++static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data) + { + u8 bist = 0; + int cnt = 0, ret = -1; +@@ -6115,13 +8291,13 @@ + * 0 on success. + */ + +-static int s2io_link_test(struct s2io_nic * sp, uint64_t * data) ++static int s2io_link_test(struct s2io_nic *sp, uint64_t *data) + { + struct XENA_dev_config __iomem *bar0 = sp->bar0; + u64 val64; + + val64 = readq(&bar0->adapter_status); +- if(!(LINK_IS_UP(val64))) ++ if (!(LINK_IS_UP(val64))) + *data = 1; + else + *data = 0; +@@ -6142,7 +8318,7 @@ + * 0 on success. + */ + +-static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data) ++static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data) + { + struct XENA_dev_config __iomem *bar0 = sp->bar0; + u64 val64; +@@ -6165,28 +8341,28 @@ + + while (iteration < 2) { + val64 = 0x55555555aaaa0000ULL; +- if (iteration == 1) { ++ if (iteration == 1) + val64 ^= 0xFFFFFFFFFFFF0000ULL; +- } ++ + writeq(val64, &bar0->mc_rldram_test_d0); + + val64 = 0xaaaa5a5555550000ULL; +- if (iteration == 1) { ++ if (iteration == 1) + val64 ^= 0xFFFFFFFFFFFF0000ULL; +- } ++ + writeq(val64, &bar0->mc_rldram_test_d1); + + val64 = 0x55aaaaaaaa5a0000ULL; +- if (iteration == 1) { ++ if (iteration == 1) + val64 ^= 0xFFFFFFFFFFFF0000ULL; +- } ++ + writeq(val64, &bar0->mc_rldram_test_d2); + + val64 = (u64) (0x0000003ffffe0100ULL); + writeq(val64, &bar0->mc_rldram_test_add); + + val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE | +- MC_RLDRAM_TEST_GO; ++ MC_RLDRAM_TEST_GO; + SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); + + for (cnt = 0; cnt < 5; cnt++) { +@@ -6243,10 +8419,10 @@ + */ + + static void s2io_ethtool_test(struct net_device *dev, +- struct ethtool_test *ethtest, +- uint64_t * data) +-{ +- struct s2io_nic *sp = dev->priv; ++ struct ethtool_test *ethtest, ++ uint64_t *data) ++{ ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + int orig_state = netif_running(sp->dev); + + if (ethtest->flags == ETH_TEST_FL_OFFLINE) { +@@ -6278,8 +8454,8 @@ + /* Online Tests. */ + if (!orig_state) { + DBG_PRINT(ERR_DBG, +- "%s: is not up, cannot run test\n", +- dev->name); ++ "%s: is not up, cannot run test\n", ++ dev->name); + data[0] = -1; + data[1] = -1; + data[2] = -1; +@@ -6297,14 +8473,40 @@ + } + } + ++#ifdef ETHTOOL_GSTATS + static void s2io_get_ethtool_stats(struct net_device *dev, +- struct ethtool_stats *estats, +- u64 * tmp_stats) +-{ +- int i = 0, k; +- struct s2io_nic *sp = dev->priv; ++ struct ethtool_stats *estats, ++ u64 *tmp_stats) ++{ ++ int i = 0, k = 0, j = 0; ++#ifdef TITAN_LEGACY ++ int j, index; ++#endif ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + struct stat_block *stat_info = sp->mac_control.stats_info; +- ++ struct swDbgStat *stats = sp->sw_dbg_stat; ++ struct xpakStat *xpak_stat = sp->xpak_stat; ++ struct swErrStat *sw_err_stat = sp->sw_err_stat; ++ struct mac_info *mac_control = &sp->mac_control; ++#define lro_stat mac_control->rings[j].rx_ring_stat->sw_lro_stat ++#ifdef TITAN_LEGACY ++ u64 *statslinkinfo; ++ ++ if (sp->device_type == TITAN_DEVICE) { ++ for (index = 0; index < MAC_LINKS; index++) { ++ statslinkinfo = &stat_info->stats_link_info[index]; ++ for (j = 0; j < LINK_MAX; j++) ++ tmp_stats[i++] = ++ le64_to_cpu(*(statslinkinfo++)); ++ } ++ for (index = 0; index < MAC_AGGREGATORS; index++) { ++ statslinkinfo = &stat_info->stats_aggr_info[index]; ++ for (j = 0; j < AGGR_MAX; j++) ++ tmp_stats[i++] = ++ le64_to_cpu(*(statslinkinfo++)); ++ } ++ } else { ++#endif + s2io_updt_stats(sp); + tmp_stats[i++] = + (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 | +@@ -6320,19 +8522,19 @@ + (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 | + le32_to_cpu(stat_info->tmac_bcst_frms); + tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms); +- tmp_stats[i++] = +- (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 | +- le32_to_cpu(stat_info->tmac_ttl_octets); +- tmp_stats[i++] = +- (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 | +- le32_to_cpu(stat_info->tmac_ucst_frms); +- tmp_stats[i++] = +- (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 | +- le32_to_cpu(stat_info->tmac_nucst_frms); ++ tmp_stats[i++] = ++ (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 | ++ le32_to_cpu(stat_info->tmac_ttl_octets); ++ tmp_stats[i++] = ++ (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 | ++ le32_to_cpu(stat_info->tmac_ucst_frms); ++ tmp_stats[i++] = ++ (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 | ++ le32_to_cpu(stat_info->tmac_nucst_frms); + tmp_stats[i++] = + (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 | + le32_to_cpu(stat_info->tmac_any_err_frms); +- tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets); ++ tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets); + tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets); + tmp_stats[i++] = + (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 | +@@ -6368,23 +8570,23 @@ + tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms); + tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms); + tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms); +- tmp_stats[i++] = +- (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 | ++ tmp_stats[i++] = ++ (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 | + le32_to_cpu(stat_info->rmac_ttl_octets); +- tmp_stats[i++] = +- (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow) ++ tmp_stats[i++] = ++ (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow) + << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms); + tmp_stats[i++] = +- (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow) +- << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms); ++ (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow) ++ << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms); + tmp_stats[i++] = + (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 | + le32_to_cpu(stat_info->rmac_discarded_frms); +- tmp_stats[i++] = +- (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow) +- << 32 | le32_to_cpu(stat_info->rmac_drop_events); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms); ++ tmp_stats[i++] = ++ (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow) ++ << 32 | le32_to_cpu(stat_info->rmac_drop_events); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms); + tmp_stats[i++] = + (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 | + le32_to_cpu(stat_info->rmac_usized_frms); +@@ -6398,11 +8600,11 @@ + (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 | + le32_to_cpu(stat_info->rmac_jabber_frms); + tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms); + tmp_stats[i++] = + (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 | + le32_to_cpu(stat_info->rmac_ip); +@@ -6422,27 +8624,27 @@ + (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 | + le32_to_cpu(stat_info->rmac_err_drp_udp); + tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7); +- tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0); +- tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1); +- tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2); +- tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3); +- tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4); +- tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5); +- tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6); +- tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7); ++ tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0); ++ tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1); ++ tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2); ++ tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3); ++ tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4); ++ tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5); ++ tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6); ++ tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7); + tmp_stats[i++] = + (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 | + le32_to_cpu(stat_info->rmac_pause_cnt); + tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt); + tmp_stats[i++] = + (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 | + le32_to_cpu(stat_info->rmac_accepted_ip); +@@ -6467,202 +8669,505 @@ + tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt); + + /* Enhanced statistics exist only for Hercules */ +- if(sp->device_type == XFRAME_II_DEVICE) { +- tmp_stats[i++] = +- le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms); +- tmp_stats[i++] = +- le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms); +- tmp_stats[i++] = +- le64_to_cpu(stat_info->rmac_ttl_8192_max_frms); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms); +- tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms); +- tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard); +- tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard); +- tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard); +- tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard); +- tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard); +- tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard); +- tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard); +- tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt); ++ if (sp->device_type == XFRAME_II_DEVICE) { ++ tmp_stats[i++] = ++ le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_8192_max_frms); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms); ++ tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms); ++ tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard); ++ tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard); ++ tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard); ++ tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard); ++ tmp_stats[i++] = le32_to_cpu(stat_info->rmac_wol_discard); ++ tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard); ++ tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard); ++ tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard); ++ tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt); + } + + tmp_stats[i++] = 0; +- tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs; +- tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs; +- tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt; +- tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt; +- for (k = 0; k < MAX_RX_RINGS; k++) +- tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k]; +- tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high; +- tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low; +- tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high; +- tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low; +- tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high; +- tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low; +- tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high; +- tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low; +- tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high; +- tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low; +- tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high; +- tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low; +- tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt; +- tmp_stats[i++] = stat_info->sw_stat.sending_both; +- tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts; +- tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts; +- if (stat_info->sw_stat.num_aggregations) { +- u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated; +- int count = 0; +- /* +- * Since 64-bit divide does not work on all platforms, +- * do repeated subtraction. +- */ +- while (tmp >= stat_info->sw_stat.num_aggregations) { +- tmp -= stat_info->sw_stat.num_aggregations; +- count++; +- } +- tmp_stats[i++] = count; +- } +- else +- tmp_stats[i++] = 0; +- tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt; +- tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt; +- tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt; +- tmp_stats[i++] = stat_info->sw_stat.mem_allocated; +- tmp_stats[i++] = stat_info->sw_stat.mem_freed; +- tmp_stats[i++] = stat_info->sw_stat.link_up_cnt; +- tmp_stats[i++] = stat_info->sw_stat.link_down_cnt; +- tmp_stats[i++] = stat_info->sw_stat.link_up_time; +- tmp_stats[i++] = stat_info->sw_stat.link_down_time; +- +- tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt; +- tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt; +- tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt; +- tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt; +- +- tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt; +- tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt; +- tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt; +- tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt; +- tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt; +- tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt; +- tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt; +-} +- ++ tmp_stats[i++] = xpak_stat->alarm_transceiver_temp_high; ++ tmp_stats[i++] = xpak_stat->alarm_transceiver_temp_low; ++ tmp_stats[i++] = xpak_stat->alarm_laser_bias_current_high; ++ tmp_stats[i++] = xpak_stat->alarm_laser_bias_current_low; ++ tmp_stats[i++] = xpak_stat->alarm_laser_output_power_high; ++ tmp_stats[i++] = xpak_stat->alarm_laser_output_power_low; ++ tmp_stats[i++] = xpak_stat->warn_transceiver_temp_high; ++ tmp_stats[i++] = xpak_stat->warn_transceiver_temp_low; ++ tmp_stats[i++] = xpak_stat->warn_laser_bias_current_high; ++ tmp_stats[i++] = xpak_stat->warn_laser_bias_current_low; ++ tmp_stats[i++] = xpak_stat->warn_laser_output_power_high; ++ tmp_stats[i++] = xpak_stat->warn_laser_output_power_low; ++ ++ tmp_stats[i++] = sw_err_stat->single_ecc_errs; ++ tmp_stats[i++] = sw_err_stat->double_ecc_errs; ++ tmp_stats[i++] = sw_err_stat->parity_err_cnt; ++ tmp_stats[i++] = sw_err_stat->serious_err_cnt; ++ tmp_stats[i++] = sw_err_stat->rx_stuck_cnt; ++ tmp_stats[i++] = sw_err_stat->soft_reset_cnt; ++ tmp_stats[i++] = sw_err_stat->watchdog_timer_cnt; ++ tmp_stats[i++] = sw_err_stat->dte_reset_cnt; ++ ++ tmp_stats[i++] = sw_err_stat->skb_null_s2io_xmit_cnt; ++ tmp_stats[i++] = sw_err_stat->skb_null_tx_intr_handler_cnt; ++ ++ tmp_stats[i++] = sw_err_stat->tda_err_cnt; ++ tmp_stats[i++] = sw_err_stat->pfc_err_cnt; ++ tmp_stats[i++] = sw_err_stat->pcc_err_cnt; ++ tmp_stats[i++] = sw_err_stat->tti_err_cnt; ++ tmp_stats[i++] = sw_err_stat->tpa_err_cnt; ++ tmp_stats[i++] = sw_err_stat->sm_err_cnt; ++ tmp_stats[i++] = sw_err_stat->lso_err_cnt; ++ tmp_stats[i++] = sw_err_stat->mac_tmac_err_cnt; ++ tmp_stats[i++] = sw_err_stat->mac_rmac_err_cnt; ++ tmp_stats[i++] = sw_err_stat->xgxs_txgxs_err_cnt; ++ tmp_stats[i++] = sw_err_stat->xgxs_rxgxs_err_cnt; ++ tmp_stats[i++] = sw_err_stat->rc_err_cnt; ++ tmp_stats[i++] = sw_err_stat->prc_pcix_err_cnt; ++ tmp_stats[i++] = sw_err_stat->rpa_err_cnt; ++ tmp_stats[i++] = sw_err_stat->rda_err_cnt; ++ tmp_stats[i++] = sw_err_stat->rti_err_cnt; ++ tmp_stats[i++] = sw_err_stat->mc_err_cnt; ++ ++ tmp_stats[i++] = sp->tx_intr_cnt; ++ tmp_stats[i++] = sp->rx_inta_cnt; ++ ++ for (k = 0; k < sp->config.tx_fifo_num; k++) ++ tmp_stats[i++] = ++ mac_control->fifos[k].tx_fifo_stat->tx_pkt_cnt; ++ for (k = 0; k < sp->config.tx_fifo_num; k++) ++ tmp_stats[i++] = ++ mac_control->fifos[k].tx_fifo_stat->tx_completion_cnt; ++ for (k = 0; k < sp->config.tx_fifo_num; k++) ++ tmp_stats[i++] = ++ mac_control->fifos[k].tx_fifo_stat->fifo_full_cnt; ++ for (k = 0; k < sp->config.tx_fifo_num; k++) ++ tmp_stats[i++] = ++ mac_control->fifos[k].tx_fifo_stat->tx_buf_abort_cnt; ++ for (k = 0; k < sp->config.tx_fifo_num; k++) ++ tmp_stats[i++] = ++ mac_control->fifos[k].tx_fifo_stat->tx_desc_abort_cnt; ++ for (k = 0; k < sp->config.tx_fifo_num; k++) ++ tmp_stats[i++] = ++ mac_control->fifos[k].tx_fifo_stat->tx_parity_err_cnt; ++ for (k = 0; k < sp->config.tx_fifo_num; k++) ++ tmp_stats[i++] = ++ mac_control->fifos[k].tx_fifo_stat->tx_link_loss_cnt; ++ for (k = 0; k < sp->config.tx_fifo_num; k++) ++ tmp_stats[i++] = ++ mac_control->fifos[k].tx_fifo_stat->tx_list_proc_err_cnt; ++ for (k = 0; k < sp->config.tx_fifo_num; k++) ++ tmp_stats[i++] = ++ mac_control->fifos[k].tx_fifo_stat->tx_pci_map_fail_cnt; ++ for (k = 0; k < sp->config.tx_fifo_num; k++) ++ tmp_stats[i++] = ++ mac_control->fifos[k].tx_fifo_stat->tx_mem_allocated; ++ for (k = 0; k < sp->config.tx_fifo_num; k++) ++ tmp_stats[i++] = ++ mac_control->fifos[k].tx_fifo_stat->tx_mem_freed; ++ ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_msix_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_pkt_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->ring_full_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_parity_err_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_abort_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_parity_abort_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_rda_fail_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_unkn_prot_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_fcs_err_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_buf_size_err_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_rxd_corrupt_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_unkn_err_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat-> ++ rx_mem_alloc_fail_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_pci_map_fail_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat-> ++ skb_null_rx_intr_handler_cnt; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_mem_allocated; ++ for (k = 0; k < sp->config.rx_ring_num; k++) ++ tmp_stats[i++] = ++ mac_control->rings[k].rx_ring_stat->rx_mem_freed; ++ ++ for (j = 0; j < sp->config.rx_ring_num; j++) { ++ tmp_stats[i++] = lro_stat.clubbed_frms_cnt; ++ tmp_stats[i++] = lro_stat.sending_both; ++ tmp_stats[i++] = lro_stat.outof_sequence_pkts; ++ tmp_stats[i++] = lro_stat.flush_max_pkts; ++ ++ if (lro_stat.num_aggregations) { ++ u64 tmp = lro_stat.sum_avg_pkts_aggregated; ++ int count = 0; ++ /* ++ * Since 64-bit divide does not work on all platforms, ++ * do repeated subtraction. ++ */ ++ while (tmp >= lro_stat.num_aggregations) { ++ tmp -= lro_stat.num_aggregations; ++ count++; ++ } ++ tmp_stats[i++] = count; ++ } ++ else ++ tmp_stats[i++] = 0; ++ ++ tmp_stats[i] = 0; ++ for (k = 0; k < MAX_RX_RINGS; k++) { ++ if (sp->mac_control.rings[k].max_pkts_aggr > ++ tmp_stats[i]) ++ tmp_stats[i] = ++ sp->mac_control.rings[k].max_pkts_aggr; ++ } ++ i++; ++ } ++ ++ tmp_stats[i++] = sp->sw_dbg_stat->mem_alloc_fail_cnt; ++ tmp_stats[i++] = sp->sw_dbg_stat->pci_map_fail_cnt; ++ tmp_stats[i++] = sp->sw_dbg_stat->mem_allocated; ++ tmp_stats[i++] = sp->sw_dbg_stat->mem_freed; ++ tmp_stats[i++] = sp->sw_dbg_stat->link_up_cnt; ++ tmp_stats[i++] = sp->sw_dbg_stat->link_down_cnt; ++ if (sp->last_link_state == LINK_UP) ++ stats->link_up_time ++ = jiffies - sp->start_time; ++ tmp_stats[i++] = sp->sw_dbg_stat->link_up_time; ++ if (sp->last_link_state == LINK_DOWN) ++ stats->link_down_time ++ = jiffies - sp->start_time; ++ tmp_stats[i++] = sp->sw_dbg_stat->link_down_time; ++ ++#ifdef TITAN_LEGAY ++ } ++#endif ++} ++#endif ++ ++#ifdef SET_ETHTOOL_OPS + static int s2io_ethtool_get_regs_len(struct net_device *dev) + { + return (XENA_REG_SPACE); + } + + +-static u32 s2io_ethtool_get_rx_csum(struct net_device * dev) +-{ +- struct s2io_nic *sp = dev->priv; ++static u32 s2io_ethtool_get_rx_csum(struct net_device *dev) ++{ ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + + return (sp->rx_csum); + } + + static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data) + { +- struct s2io_nic *sp = dev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ int i; + + if (data) + sp->rx_csum = 1; + else + sp->rx_csum = 0; + +- return 0; +-} +- ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ sp->mac_control.rings[i].rx_csum = sp->rx_csum; ++ ++ return 0; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 00)) || \ ++ (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 4, 23)) + static int s2io_get_eeprom_len(struct net_device *dev) + { + return (XENA_EEPROM_SPACE); + } +- +-static int s2io_get_sset_count(struct net_device *dev, int sset) +-{ +- struct s2io_nic *sp = dev->priv; +- +- switch (sset) { +- case ETH_SS_TEST: +- return S2IO_TEST_LEN; +- case ETH_SS_STATS: +- switch(sp->device_type) { +- case XFRAME_I_DEVICE: +- return XFRAME_I_STAT_LEN; +- case XFRAME_II_DEVICE: +- return XFRAME_II_STAT_LEN; +- default: +- return 0; +- } +- default: +- return -EOPNOTSUPP; +- } ++#endif ++ ++static int s2io_ethtool_self_test_count(struct net_device *dev) ++{ ++ return (S2IO_TEST_LEN); ++} ++ ++static void add_print_string(char *prnt_string, int j, int *stat_size, u8 *data, ++ struct s2io_nic *sp) ++{ ++ char data_string[ETH_GSTRING_LEN] = {}; ++ sprintf(data_string, prnt_string, j); ++ memcpy(data + *stat_size, data_string, ETH_GSTRING_LEN); ++ *stat_size += ETH_GSTRING_LEN; + } + + static void s2io_ethtool_get_strings(struct net_device *dev, +- u32 stringset, u8 * data) +-{ +- int stat_size = 0; +- struct s2io_nic *sp = dev->priv; ++ u32 stringset, u8 *data) ++{ ++ int stat_size = 0, i; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + + switch (stringset) { + case ETH_SS_TEST: + memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN); + break; + case ETH_SS_STATS: ++#ifdef TITAN_LEGACY ++ if (sp->device_type == TITAN_DEVICE) ++ memcpy(data, ðtool_titan_stats_keys, ++ sizeof(ethtool_titan_stats_keys)); ++ else ++#endif ++ { + stat_size = sizeof(ethtool_xena_stats_keys); +- memcpy(data, ðtool_xena_stats_keys,stat_size); +- if(sp->device_type == XFRAME_II_DEVICE) { ++ memcpy(data, ðtool_xena_stats_keys, stat_size); ++ ++ if (sp->device_type == XFRAME_II_DEVICE) { + memcpy(data + stat_size, + ðtool_enhanced_stats_keys, + sizeof(ethtool_enhanced_stats_keys)); + stat_size += sizeof(ethtool_enhanced_stats_keys); + } + +- memcpy(data + stat_size, ðtool_driver_stats_keys, ++ memcpy(data + stat_size, ++ ðtool_driver_stats_keys, + sizeof(ethtool_driver_stats_keys)); +- } ++ stat_size += sizeof(ethtool_driver_stats_keys); ++ ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ add_print_string("tx_pkt_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ add_print_string("tx_completion_cnt%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ add_print_string("fifo_full_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ add_print_string("tx_buf_abort_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ add_print_string("tx_desc_abort_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ add_print_string("tx_parity_err_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ add_print_string("tx_link_loss_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ add_print_string("tx_list_proc_err_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ add_print_string("tx_pci_map_fail_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ add_print_string("tx_mem_allocated_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ add_print_string("tx_mem_freed_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_msix_cnt%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_pkt_cnt%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("ring_full_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_parity_err_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_abort_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_parity_abort_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_rda_fail_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_unkn_prot_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_fcs_err_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_buf_size_err_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_rxd_corrupt_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_unkn_err_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_mem_alloc_fail_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_pci_map_fail_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("skb_null_rx_intr_handler_cnt_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_mem_allocated_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ add_print_string("rx_mem_freed_%d", ++ i, &stat_size, data, sp); ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) { ++ add_print_string("lro_aggregated_pkts_%d\t\t", ++ i, &stat_size, data, sp); ++ add_print_string("lro_flush_both_count_%d\t\t", ++ i, &stat_size, data, sp); ++ add_print_string("lro_out_of_sequence_pkts_%d\t\t", ++ i, &stat_size, data, sp); ++ add_print_string("lro_flush_due_to_max_pkts_%d\t", ++ i, &stat_size, data, sp); ++ add_print_string("lro_avg_aggr_pkts_%d\t\t", ++ i, &stat_size, data, sp); ++ add_print_string("lro_max_pkts_aggr_%d\t\t", ++ i, &stat_size, data, sp); ++ } ++ ++ memcpy(data + stat_size, ++ ðtool_driver_dbg_stats_keys, ++ sizeof(ethtool_driver_dbg_stats_keys)); ++ } ++ } ++} ++ ++static int s2io_ethtool_get_stats_count(struct net_device *dev) ++{ ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ int stat_count = 0; ++ ++ switch (sp->device_type) { ++ ++#ifdef TITAN_LEGACY ++ case TITAN_DEVICE: ++ stat_count = S2IO_TITAN_STAT_COUNT; ++ break; ++#endif ++ case XFRAME_I_DEVICE: ++ stat_count = XFRAME_I_STAT_LEN + ++ (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + ++ (sp->config.rx_ring_num * NUM_RX_SW_STAT) + ++ S2IO_DRIVER_DBG_STAT_LEN; ++ break; ++ ++ case XFRAME_II_DEVICE: ++ stat_count = XFRAME_II_STAT_LEN + ++ (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + ++ (sp->config.rx_ring_num * NUM_RX_SW_STAT) + ++ S2IO_DRIVER_DBG_STAT_LEN; ++ break; ++ } ++ ++ return stat_count; ++} ++ ++static u32 s2io_ethtool_get_link(struct net_device *dev) ++{ ++ u64 val64 = 0; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ ++ val64 = netif_carrier_ok(dev); ++ if (val64) { ++ /* Verify Adapter_Enable bit which automatically ++ * transitions to 0 in the event of a link fault ++ */ ++ val64 = readq(&bar0->adapter_control); ++ } ++ return (val64 & ADAPTER_CNTL_EN) ? 1 : 0; + } + + static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data) + { +- if (data) +- dev->features |= NETIF_F_IP_CSUM; +- else ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ ++ if (data) { ++ if (sp->device_type == XFRAME_II_DEVICE) ++ dev->features |= NETIF_F_HW_CSUM; ++ else ++ dev->features |= NETIF_F_IP_CSUM; ++ } else { + dev->features &= ~NETIF_F_IP_CSUM; +- +- return 0; +-} +- ++ if (sp->device_type == XFRAME_II_DEVICE) ++ dev->features &= ~NETIF_F_HW_CSUM; ++ } ++ ++ return 0; ++} ++ ++ ++#ifdef NETIF_F_TSO6 + static u32 s2io_ethtool_op_get_tso(struct net_device *dev) + { + return (dev->features & NETIF_F_TSO) != 0; + } ++ + static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data) + { + if (data) +@@ -6672,6 +9177,7 @@ + + return 0; + } ++#endif + + static const struct ethtool_ops netdev_ethtool_ops = { + .get_settings = s2io_ethtool_gset, +@@ -6679,8 +9185,11 @@ + .get_drvinfo = s2io_ethtool_gdrvinfo, + .get_regs_len = s2io_ethtool_get_regs_len, + .get_regs = s2io_ethtool_gregs, +- .get_link = ethtool_op_get_link, ++ .get_link = s2io_ethtool_get_link, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 00)) || \ ++ (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 4, 23)) + .get_eeprom_len = s2io_get_eeprom_len, ++#endif + .get_eeprom = s2io_ethtool_geeprom, + .set_eeprom = s2io_ethtool_seeprom, + .get_ringparam = s2io_ethtool_gringparam, +@@ -6688,17 +9197,26 @@ + .set_pauseparam = s2io_ethtool_setpause_data, + .get_rx_csum = s2io_ethtool_get_rx_csum, + .set_rx_csum = s2io_ethtool_set_rx_csum, ++ .get_tx_csum = ethtool_op_get_tx_csum, + .set_tx_csum = s2io_ethtool_op_set_tx_csum, ++ .get_sg = ethtool_op_get_sg, + .set_sg = ethtool_op_set_sg, ++#ifdef NETIF_F_TSO + .get_tso = s2io_ethtool_op_get_tso, + .set_tso = s2io_ethtool_op_set_tso, ++#endif ++#ifdef NETIF_F_UFO ++ .get_ufo = ethtool_op_get_ufo, + .set_ufo = ethtool_op_set_ufo, ++#endif ++ .self_test_count = s2io_ethtool_self_test_count, + .self_test = s2io_ethtool_test, + .get_strings = s2io_ethtool_get_strings, + .phys_id = s2io_ethtool_idnic, +- .get_ethtool_stats = s2io_get_ethtool_stats, +- .get_sset_count = s2io_get_sset_count, +-}; ++ .get_stats_count = s2io_ethtool_get_stats_count, ++ .get_ethtool_stats = s2io_get_ethtool_stats ++}; ++#endif + + /** + * s2io_ioctl - Entry point for the Ioctl +@@ -6708,13 +9226,43 @@ + * @cmd : This is used to distinguish between the different commands that + * can be passed to the IOCTL functions. + * Description: +- * Currently there are no special functionality supported in IOCTL, hence +- * function always return EOPNOTSUPPORTED ++ * This function has support for ethtool, adding multiple MAC addresses on ++ * the NIC and some DBG commands for the util tool. ++ * Return value: ++ * 0 on success and an appropriate (-)ve integer as defined in errno.h ++ * file on failure. + */ + + static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) + { +- return -EOPNOTSUPP; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ ++ switch (cmd) { ++#ifndef SET_ETHTOOL_OPS ++ case SIOCETHTOOL: ++ return s2io_ethtool(dev, rq); ++#endif ++ default: ++ if (s2io_ioctl_util(sp, rq, cmd) < 0) ++ return -EFAULT; ++ } ++ return SUCCESS; ++} ++ ++static int s2io_restart_card(struct s2io_nic *sp) ++{ ++ int ret = 0; ++ if (test_and_set_bit(__S2IO_STATE_RESET_CARD, &(sp->state))) ++ return -1; ++ s2io_card_down(sp); ++ ret = s2io_card_up(sp); ++ if (ret) { ++ DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", ++ __FUNCTION__); ++ return ret; ++ } ++ clear_bit(__S2IO_STATE_RESET_CARD, &(sp->state)); ++ return ret; + } + + /** +@@ -6730,25 +9278,23 @@ + + static int s2io_change_mtu(struct net_device *dev, int new_mtu) + { +- struct s2io_nic *sp = dev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); + int ret = 0; + +- if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) { ++ if ((new_mtu < MIN_MTU) || (new_mtu > MAX_PYLD_JUMBO)) { + DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", + dev->name); + return -EPERM; + } + + dev->mtu = new_mtu; ++ + if (netif_running(dev)) { + s2io_stop_all_tx_queue(sp); +- s2io_card_down(sp); +- ret = s2io_card_up(sp); +- if (ret) { +- DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", +- __FUNCTION__); ++ ++ ret = s2io_restart_card(sp); ++ if (ret) + return ret; +- } + s2io_wake_all_tx_queue(sp); + } else { /* Device is down */ + struct XENA_dev_config __iomem *bar0 = sp->bar0; +@@ -6757,6 +9303,8 @@ + writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); + } + ++ DBG_PRINT(ERR_DBG, "%s: MTU is changed to %d\n", dev->name, new_mtu); ++ + return ret; + } + +@@ -6766,22 +9314,28 @@ + * Description: Sets the link status for the adapter + */ + ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++static void s2io_set_link(unsigned long data) ++{ ++ struct s2io_nic *nic = (struct s2io_nic *) data; ++ struct net_device *dev = nic->dev; ++#else + static void s2io_set_link(struct work_struct *work) + { +- struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task); ++ struct s2io_nic *nic = container_of(work, struct s2io_nic, ++ set_link_task); + struct net_device *dev = nic->dev; ++#endif + struct XENA_dev_config __iomem *bar0 = nic->bar0; + register u64 val64; + u16 subid; + +- rtnl_lock(); +- + if (!netif_running(dev)) +- goto out_unlock; +- +- if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) { ++ return; ++ ++ if (test_and_set_bit(__S2IO_STATE_LINK_RESET_TASK, &(nic->state))) { + /* The card is being reset, no point doing anything */ +- goto out_unlock; ++ return; + } + + subid = nic->pdev->subsystem_device; +@@ -6792,14 +9346,14 @@ + */ + msleep(100); + } +- + val64 = readq(&bar0->adapter_status); + if (LINK_IS_UP(val64)) { +- if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) { ++ if (nic->device_type == XFRAME_I_DEVICE) { + if (verify_xena_quiescence(nic)) { + val64 = readq(&bar0->adapter_control); + val64 |= ADAPTER_CNTL_EN; + writeq(val64, &bar0->adapter_control); ++ + if (CARDS_WITH_FAULTY_LINK_INDICATORS( + nic->device_type, subid)) { + val64 = readq(&bar0->gpio_control); +@@ -6813,17 +9367,22 @@ + nic->device_enabled_once = TRUE; + } else { + DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name); +- DBG_PRINT(ERR_DBG, "device is not Quiescent\n"); ++ DBG_PRINT(ERR_DBG, ++ "device is not Quiescent\n"); + s2io_stop_all_tx_queue(nic); + } +- } +- val64 = readq(&bar0->adapter_control); +- val64 |= ADAPTER_LED_ON; +- writeq(val64, &bar0->adapter_control); ++ } else { ++ val64 = readq(&bar0->adapter_control); ++ val64 |= ADAPTER_CNTL_EN; ++ writeq(val64, &bar0->adapter_control); ++ val64 |= ADAPTER_LED_ON; ++ writeq(val64, &bar0->adapter_control); ++ nic->device_enabled_once = TRUE; ++ } + s2io_link(nic, LINK_UP); + } else { + if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type, +- subid)) { ++ subid)) { + val64 = readq(&bar0->gpio_control); + val64 &= ~GPIO_CTRL_GPIO_0; + writeq(val64, &bar0->gpio_control); +@@ -6831,143 +9390,348 @@ + } + /* turn off LED */ + val64 = readq(&bar0->adapter_control); +- val64 = val64 &(~ADAPTER_LED_ON); ++ val64 = val64 & (~ADAPTER_LED_ON); + writeq(val64, &bar0->adapter_control); + s2io_link(nic, LINK_DOWN); + } +- clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state)); +- +-out_unlock: +- rtnl_unlock(); +-} +- +-static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp, ++ clear_bit(__S2IO_STATE_LINK_RESET_TASK, &(nic->state)); ++} ++ ++static int set_rxd_buffer_pointer(struct ring_info *ring, struct RxD_t *rxdp, + struct buffAdd *ba, + struct sk_buff **skb, u64 *temp0, u64 *temp1, +- u64 *temp2, int size) +-{ +- struct net_device *dev = sp->dev; +- struct swStat *stats = &sp->mac_control.stats_info->sw_stat; +- +- if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) { +- struct RxD1 *rxdp1 = (struct RxD1 *)rxdp; ++ u64 *temp2, u64 *temp3, u64 *temp4, int size, ++ int rxd_index) ++{ ++ struct sk_buff *frag_list; ++ struct RxD1 *rxdp1; ++ struct RxD3 *rxdp3; ++ struct RxD5 *rxdp5; ++ struct rxRingStat *stats = ring->rx_ring_stat; ++ ++ if (ring->rxd_mode == RXD_MODE_5) { ++ if (((struct RxD5 *)rxdp)->Host_Control) ++ return 0; ++ } else ++ if (rxdp->Host_Control) ++ return 0; ++ ++ switch (ring->rxd_mode) { ++ case RXD_MODE_1: + /* allocate skb */ ++ rxdp1 = (struct RxD1 *)rxdp; + if (*skb) { + DBG_PRINT(INFO_DBG, "SKB is not NULL\n"); + /* +- * As Rx frame are not going to be processed, +- * using same mapped address for the Rxd +- * buffer pointer +- */ ++ * As Rx frame are not going to be processed, ++ * using same mapped address for the Rxd ++ * buffer pointer ++ */ + rxdp1->Buffer0_ptr = *temp0; + } else { +- *skb = dev_alloc_skb(size); ++ *skb = netdev_alloc_skb(ring->dev, size); + if (!(*skb)) { +- DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name); ++ DBG_PRINT(INFO_DBG, "%s: Out of ", ++ ring->dev->name); + DBG_PRINT(INFO_DBG, "memory to allocate "); + DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n"); +- sp->mac_control.stats_info->sw_stat. \ +- mem_alloc_fail_cnt++; ++ stats->rx_mem_alloc_fail_cnt++; + return -ENOMEM ; + } +- sp->mac_control.stats_info->sw_stat.mem_allocated +- += (*skb)->truesize; ++ stats->rx_mem_allocated += (*skb)->truesize; + /* storing the mapped addr in a temp variable + * such it will be used for next rxd whose + * Host Control is NULL + */ + rxdp1->Buffer0_ptr = *temp0 = +- pci_map_single( sp->pdev, (*skb)->data, +- size - NET_IP_ALIGN, +- PCI_DMA_FROMDEVICE); +- if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr)) +- goto memalloc_failed; ++ pci_map_single(ring->pdev, (*skb)->data, ++ size - NET_IP_ALIGN, ++ PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(rxdp1->Buffer0_ptr)) { ++ stats->rx_pci_map_fail_cnt++; ++ stats->rx_mem_freed += (*skb)->truesize; ++ dev_kfree_skb(*skb); ++ return -ENOMEM; ++ } + rxdp->Host_Control = (unsigned long) (*skb); + } +- } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) { +- struct RxD3 *rxdp3 = (struct RxD3 *)rxdp; +- /* Two buffer Mode */ ++ break; ++ ++ case RXD_MODE_5: ++ rxdp5 = (struct RxD5 *)rxdp; ++ if (*skb) { ++ rxdp5->Buffer0_ptr = *temp0; ++ rxdp5->Buffer1_ptr = *temp1; ++ rxdp5->Buffer2_ptr = *temp2; ++ rxdp5->Buffer3_ptr = *temp3; ++ rxdp5->Buffer4_ptr = *temp4; ++ } else { ++ /* Allocate Buffer 0 */ ++ *skb = netdev_alloc_skb(ring->dev, size); ++ if (!(*skb)) { ++ DBG_PRINT(INFO_DBG, "%s: Out of ", ++ ring->dev->name); ++ DBG_PRINT(INFO_DBG, "memory to allocate "); ++ DBG_PRINT(INFO_DBG, "5 buf mode SKBs\n"); ++ stats->rx_mem_alloc_fail_cnt++; ++ return -ENOMEM ; ++ } ++ ++ stats->rx_mem_allocated += (*skb)->truesize; ++ rxdp5->Buffer0_ptr = *temp0 = ++ pci_map_single(ring->pdev, ba->ba_0, BUF0_LEN, ++ PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(rxdp5->Buffer0_ptr)) ++ goto free_5b_0; ++ ++ /* Buffer-1 receives L3/L4 headers */ ++ rxdp5->Buffer1_ptr = *temp1 = ++ pci_map_single(ring->pdev, (*skb)->data, ++ l3l4hdr_size + 4, ++ PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(rxdp5->Buffer1_ptr)) ++ goto free_5b_1; ++ /* ++ * skb_shinfo(skb)->frag_list will have L4 ++ * data payload ++ */ ++ skb_shinfo(*skb)->frag_list = ++ netdev_alloc_skb(ring->dev, ++ MODE5_BUF_SIZE + ALIGN_SIZE); ++ if (skb_shinfo(*skb)->frag_list == NULL) { ++ DBG_PRINT(INFO_DBG, "%s: netdev_alloc_skb \ ++ failed\n ", ring->dev->name); ++ stats->rx_mem_alloc_fail_cnt++; ++ goto free_5b_2; ++ } ++ frag_list = skb_shinfo(*skb)->frag_list; ++ frag_list->next = NULL; ++ (*skb)->truesize += frag_list->truesize; ++ stats->rx_mem_allocated += frag_list->truesize; ++ /* ++ * Buffer-2 receives L4 data payload ++ */ ++ rxdp5->Buffer2_ptr = *temp2 = ++ pci_map_single(ring->pdev, frag_list->data, ++ MODE5_BUF_SIZE, PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(rxdp5->Buffer2_ptr)) ++ goto free_5b_2; ++ ++ if (ring->skbs_per_rxd > 2) { ++ /* ++ * frag_list->next will have L4 ++ * data payload ++ */ ++ frag_list->next = ++ netdev_alloc_skb(ring->dev, ++ MODE5_BUF_SIZE + ALIGN_SIZE); ++ if (frag_list->next == NULL) { ++ DBG_PRINT(ERR_DBG, "%s: \ ++ netdev_alloc_skb failed\n", ++ ring->dev->name); ++ stats->rx_mem_alloc_fail_cnt++; ++ goto free_5b_3; ++ } ++ ++ frag_list = frag_list->next; ++ frag_list->next = NULL; ++ (*skb)->truesize += frag_list->truesize; ++ stats->rx_mem_allocated += frag_list->truesize; ++ ++ /* ++ * Buffer-3 receives L4 data payload ++ */ ++ rxdp5->Buffer3_ptr = *temp3 = ++ pci_map_single(ring->pdev, ++ frag_list->data, MODE5_BUF_SIZE, ++ PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(rxdp5->Buffer3_ptr)) { ++ frag_list = ++ skb_shinfo(*skb)->frag_list; ++ goto free_5b_3; ++ } ++ } else ++ rxdp5->Buffer3_ptr = *temp3 = ++ rxdp5->Buffer2_ptr; ++ ++ if (ring->skbs_per_rxd > 3) { ++ frag_list->next = netdev_alloc_skb(ring->dev, ++ MODE5_BUF_SIZE + ALIGN_SIZE); ++ if (skb_shinfo(*skb)->frag_list == NULL) { ++ DBG_PRINT(INFO_DBG, "%s: \ ++ netdev_alloc_skb failed\n", ++ ring->dev->name); ++ stats->rx_mem_alloc_fail_cnt++; ++ frag_list = skb_shinfo(*skb)->frag_list; ++ goto free_5b_4; ++ } ++ frag_list->next = NULL; ++ (*skb)->truesize += frag_list->truesize; ++ stats->rx_mem_allocated += ++ frag_list->truesize; ++ ++ /* Get physical address for buffer 4 */ ++ rxdp5->Buffer4_ptr = *temp4 = ++ pci_map_single(ring->pdev, ++ frag_list->data, ++ MODE5_BUF_SIZE, ++ PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(rxdp5->Buffer4_ptr)) { ++ frag_list = ++ skb_shinfo(*skb)->frag_list; ++ goto free_5b_4; ++ } ++ } else ++ rxdp5->Buffer4_ptr = *temp4 = ++ rxdp5->Buffer3_ptr; ++ ++ rxdp5->Host_Control = rxd_index; ++ ring->skbs[rxd_index] = ++ (unsigned long) (*skb); ++ break; ++ ++free_5b_4: ++ stats->rx_pci_map_fail_cnt++; ++ pci_unmap_single(ring->pdev, ++ (dma_addr_t)(unsigned long)frag_list->next->data, ++ MODE5_BUF_SIZE, PCI_DMA_FROMDEVICE); ++free_5b_3: ++ stats->rx_pci_map_fail_cnt++; ++ pci_unmap_single(ring->pdev, ++ (dma_addr_t)(unsigned long)frag_list->data, ++ MODE5_BUF_SIZE, PCI_DMA_FROMDEVICE); ++free_5b_2: ++ stats->rx_pci_map_fail_cnt++; ++ pci_unmap_single(ring->pdev, ++ (dma_addr_t)(unsigned long)(*skb)->data, ++ l3l4hdr_size + 4, PCI_DMA_FROMDEVICE); ++free_5b_1: ++ stats->rx_pci_map_fail_cnt++; ++ pci_unmap_single(ring->pdev, ++ (dma_addr_t)(unsigned long)ba->ba_0, ++ BUF0_LEN, PCI_DMA_FROMDEVICE); ++free_5b_0: ++ stats->rx_pci_map_fail_cnt++; ++ stats->rx_mem_freed += (*skb)->truesize; ++ dev_kfree_skb(*skb); ++ return -ENOMEM; ++ } ++ break; ++ ++ case RXD_MODE_3B: /* Two buffer Mode */ ++ rxdp3 = (struct RxD3 *)rxdp; + if (*skb) { + rxdp3->Buffer2_ptr = *temp2; + rxdp3->Buffer0_ptr = *temp0; + rxdp3->Buffer1_ptr = *temp1; + } else { +- *skb = dev_alloc_skb(size); ++ *skb = netdev_alloc_skb(ring->dev, size); + if (!(*skb)) { +- DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name); ++ DBG_PRINT(INFO_DBG, "%s: Out of ", ++ ring->dev->name); + DBG_PRINT(INFO_DBG, "memory to allocate "); + DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n"); +- sp->mac_control.stats_info->sw_stat. \ +- mem_alloc_fail_cnt++; +- return -ENOMEM; +- } +- sp->mac_control.stats_info->sw_stat.mem_allocated +- += (*skb)->truesize; +- rxdp3->Buffer2_ptr = *temp2 = +- pci_map_single(sp->pdev, (*skb)->data, +- dev->mtu + 4, +- PCI_DMA_FROMDEVICE); +- if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr)) +- goto memalloc_failed; ++ stats->rx_mem_alloc_fail_cnt++; ++ return -ENOMEM ; ++ } ++ + rxdp3->Buffer0_ptr = *temp0 = +- pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN, +- PCI_DMA_FROMDEVICE); +- if (pci_dma_mapping_error(sp->pdev, +- rxdp3->Buffer0_ptr)) { +- pci_unmap_single (sp->pdev, +- (dma_addr_t)rxdp3->Buffer2_ptr, +- dev->mtu + 4, PCI_DMA_FROMDEVICE); +- goto memalloc_failed; +- } +- rxdp->Host_Control = (unsigned long) (*skb); ++ pci_map_single(ring->pdev, ba->ba_0, BUF0_LEN, ++ PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(rxdp3->Buffer0_ptr)) ++ goto free_3b_0; + + /* Buffer-1 will be dummy buffer not used */ + rxdp3->Buffer1_ptr = *temp1 = +- pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN, +- PCI_DMA_FROMDEVICE); +- if (pci_dma_mapping_error(sp->pdev, +- rxdp3->Buffer1_ptr)) { +- pci_unmap_single (sp->pdev, +- (dma_addr_t)rxdp3->Buffer0_ptr, +- BUF0_LEN, PCI_DMA_FROMDEVICE); +- pci_unmap_single (sp->pdev, +- (dma_addr_t)rxdp3->Buffer2_ptr, +- dev->mtu + 4, PCI_DMA_FROMDEVICE); +- goto memalloc_failed; +- } +- } +- } +- return 0; +- memalloc_failed: +- stats->pci_map_fail_cnt++; +- stats->mem_freed += (*skb)->truesize; ++ pci_map_single(ring->pdev, ba->ba_1, BUF1_LEN, ++ PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(rxdp3->Buffer1_ptr)) ++ goto free_3b_1; ++ ++ stats->rx_mem_allocated += (*skb)->truesize; ++ rxdp3->Buffer2_ptr = *temp2 = ++ pci_map_single(ring->pdev, (*skb)->data, ++ size - BUF0_LEN, ++ PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(rxdp3->Buffer2_ptr)) ++ goto free_3b_2; ++ ++ rxdp->Host_Control = (unsigned long) (*skb); ++ break; ++ ++free_3b_2: ++ stats->rx_pci_map_fail_cnt++; ++ pci_unmap_single(ring->pdev, ++ (dma_addr_t)(unsigned long)ba->ba_1, ++ BUF1_LEN, PCI_DMA_FROMDEVICE); ++free_3b_1: ++ stats->rx_pci_map_fail_cnt++; ++ pci_unmap_single(ring->pdev, ++ (dma_addr_t)(unsigned long)ba->ba_0, ++ BUF0_LEN, PCI_DMA_FROMDEVICE); ++free_3b_0: ++ stats->rx_pci_map_fail_cnt++; ++ stats->rx_mem_freed += (*skb)->truesize; + dev_kfree_skb(*skb); + return -ENOMEM; +-} +- +-static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp, +- int size) +-{ +- struct net_device *dev = sp->dev; +- if (sp->rxd_mode == RXD_MODE_1) { ++ } ++ break; ++ } ++ return 0; ++} ++ ++static void set_rxd_buffer_size(struct ring_info *ring, struct RxD_t *rxdp, ++ int size) ++{ ++ struct RxD5 *rxdp5; ++ ++ switch (ring->rxd_mode) { ++ case RXD_MODE_1: + rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN); +- } else if (sp->rxd_mode == RXD_MODE_3B) { ++ break; ++ ++ case RXD_MODE_5: ++ rxdp5 = (struct RxD5 *)rxdp; ++ rxdp->Control_2 &= (~MASK_BUFFER0_SIZE_5); ++ rxdp->Control_2 |= SET_BUFFER0_SIZE_5(BUF0_LEN); ++ rxdp->Control_2 &= (~MASK_BUFFER1_SIZE_5); ++ rxdp->Control_2 |= SET_BUFFER1_SIZE_5(l3l4hdr_size + 4); ++ rxdp->Control_2 &= (~MASK_BUFFER2_SIZE_5); ++ rxdp->Control_2 |= SET_BUFFER2_SIZE_5(MODE5_BUF_SIZE); ++ rxdp5->Control_3 &= (~MASK_BUFFER3_SIZE_5); ++ if (ring->skbs_per_rxd > 2) ++ rxdp5->Control_3 |= ++ SET_BUFFER3_SIZE_5(MODE5_BUF_SIZE); ++ else ++ rxdp5->Control_3 |= SET_BUFFER3_SIZE_5(1); ++ rxdp5->Control_3 &= (~MASK_BUFFER4_SIZE_5); ++ if (ring->skbs_per_rxd > 3) ++ rxdp5->Control_3 |= ++ SET_BUFFER4_SIZE_5(MODE5_BUF_SIZE); ++ else ++ rxdp5->Control_3 |= SET_BUFFER4_SIZE_5(1); ++ break; ++ ++ case RXD_MODE_3B: + rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN); + rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1); +- rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4); ++ rxdp->Control_2 |= SET_BUFFER2_SIZE_3(size - BUF0_LEN); ++ break; + } + } + + static int rxd_owner_bit_reset(struct s2io_nic *sp) + { + int i, j, k, blk_cnt = 0, size; +- struct mac_info * mac_control = &sp->mac_control; ++ struct mac_info *mac_control = &sp->mac_control; + struct config_param *config = &sp->config; + struct net_device *dev = sp->dev; + struct RxD_t *rxdp = NULL; + struct sk_buff *skb = NULL; + struct buffAdd *ba = NULL; + u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0; ++ u64 temp3_64 = 0, temp4_64 = 0; ++ int rxd_index = 0; + + /* Calculate the size based on ring mode */ + size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE + +@@ -6976,6 +9740,8 @@ + size += NET_IP_ALIGN; + else if (sp->rxd_mode == RXD_MODE_3B) + size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4; ++ else ++ size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4; + + for (i = 0; i < config->rx_ring_num; i++) { + blk_cnt = config->rx_cfg[i].num_rxd / +@@ -6985,17 +9751,26 @@ + for (k = 0; k < rxd_count[sp->rxd_mode]; k++) { + rxdp = mac_control->rings[i]. + rx_blocks[j].rxds[k].virt_addr; +- if(sp->rxd_mode == RXD_MODE_3B) ++ ++ rxd_index = k + 1; ++ if (j) ++ rxd_index += ++ (j * rxd_count[sp->rxd_mode]); ++ ++ if (sp->rxd_mode >= RXD_MODE_3B) + ba = &mac_control->rings[i].ba[j][k]; +- if (set_rxd_buffer_pointer(sp, rxdp, ba, +- &skb,(u64 *)&temp0_64, +- (u64 *)&temp1_64, +- (u64 *)&temp2_64, +- size) == -ENOMEM) { ++ if (set_rxd_buffer_pointer ++ (&mac_control->rings[i], rxdp, ++ ba, &skb, (u64 *)&temp0_64, ++ (u64 *)&temp1_64, ++ (u64 *)&temp2_64, ++ (u64 *)&temp3_64, ++ (u64 *)&temp4_64, ++ size, rxd_index) == -ENOMEM) + return 0; +- } +- +- set_rxd_buffer_size(sp, rxdp, size); ++ ++ set_rxd_buffer_size(&mac_control->rings[i], ++ rxdp, size); + wmb(); + /* flip the Ownership bit to Hardware */ + rxdp->Control_1 |= RXD_OWN_XENA; +@@ -7006,20 +9781,22 @@ + + } + +-static int s2io_add_isr(struct s2io_nic * sp) +-{ +- int ret = 0; ++static int s2io_add_isr(struct s2io_nic *sp) ++{ + struct net_device *dev = sp->dev; + int err = 0; + ++#ifdef CONFIG_PCI_MSI ++ int ret = 0; + if (sp->config.intr_type == MSI_X) + ret = s2io_enable_msi_x(sp); ++ + if (ret) { + DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name); + sp->config.intr_type = INTA; + } + +- /* Store the values of the MSIX table in the struct s2io_nic structure */ ++ /* Store the values of the MSIX table in the s2io_nic structure */ + store_xmsi_data(sp); + + /* After proper initialization of H/W, register ISR */ +@@ -7027,22 +9804,20 @@ + int i, msix_rx_cnt = 0; + + for (i = 0; i < sp->num_entries; i++) { +- if (sp->s2io_entries[i].in_use == MSIX_FLG) { ++ if(sp->s2io_entries[i].in_use == MSIX_FLG) { + if (sp->s2io_entries[i].type == + MSIX_RING_TYPE) { + sprintf(sp->desc[i], "%s:MSI-X-%d-RX", + dev->name, i); + err = request_irq(sp->entries[i].vector, +- s2io_msix_ring_handle, 0, +- sp->desc[i], ++ s2io_msix_ring_handle, 0, sp->desc[i], + sp->s2io_entries[i].arg); + } else if (sp->s2io_entries[i].type == + MSIX_ALARM_TYPE) { + sprintf(sp->desc[i], "%s:MSI-X-%d-TX", + dev->name, i); + err = request_irq(sp->entries[i].vector, +- s2io_msix_fifo_handle, 0, +- sp->desc[i], ++ s2io_msix_fifo_handle, 0, sp->desc[i], + sp->s2io_entries[i].arg); + + } +@@ -7050,16 +9825,16 @@ + if (!(sp->msix_info[i].addr && + sp->msix_info[i].data)) { + DBG_PRINT(ERR_DBG, +- "%s @Addr:0x%llx Data:0x%llx\n", +- sp->desc[i], +- (unsigned long long) ++ "%s @ Addr:0x%llx Data:0x%llx\n", ++ sp->desc[i], ++ (unsigned long long) + sp->msix_info[i].addr, +- (unsigned long long) ++ (unsigned long long) + ntohl(sp->msix_info[i].data)); + } else + msix_rx_cnt++; + if (err) { +- remove_msix_isr(sp); ++ do_rem_msix_isr(sp); + + DBG_PRINT(ERR_DBG, + "%s:MSI-X-%d registration " +@@ -7076,14 +9851,16 @@ + } + } + if (!err) { +- printk(KERN_INFO "MSI-X-RX %d entries enabled\n", +- --msix_rx_cnt); ++ DBG_PRINT(INFO_DBG, "MSI-X-RX %d entries enabled\n", ++ --msix_rx_cnt); + DBG_PRINT(INFO_DBG, "MSI-X-TX entries enabled" + " through alarm vector\n"); + } + } ++#endif + if (sp->config.intr_type == INTA) { +- err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED, ++ err = request_irq((int) sp->pdev->irq, ++ s2io_isr, IRQF_SHARED, + sp->name, dev); + if (err) { + DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n", +@@ -7093,41 +9870,44 @@ + } + return 0; + } +-static void s2io_rem_isr(struct s2io_nic * sp) +-{ ++ ++static void s2io_rem_isr(struct s2io_nic *sp) ++{ ++#ifdef CONFIG_PCI_MSI + if (sp->config.intr_type == MSI_X) +- remove_msix_isr(sp); +- else +- remove_inta_isr(sp); +-} +- +-static void do_s2io_card_down(struct s2io_nic * sp, int do_io) +-{ +- int cnt = 0; ++ do_rem_msix_isr(sp); ++ else ++#endif ++ do_rem_inta_isr(sp); ++} ++ ++static void do_s2io_card_down(struct s2io_nic *sp, int do_io) ++{ ++ int cnt; + struct XENA_dev_config __iomem *bar0 = sp->bar0; + register u64 val64 = 0; +- struct config_param *config; +- config = &sp->config; ++ struct config_param *config = &sp->config; + + if (!is_s2io_card_up(sp)) + return; + + del_timer_sync(&sp->alarm_timer); +- /* If s2io_set_link task is executing, wait till it completes. */ +- while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) { ++ ++ /* If s2io_set_link task/restart task is executing, ++ * wait till it completes. */ ++ while (test_and_set_bit(__S2IO_STATE_LINK_RESET_TASK, &(sp->state))) + msleep(50); +- } ++ + clear_bit(__S2IO_STATE_CARD_UP, &sp->state); + + /* Disable napi */ +- if (sp->config.napi) { +- int off = 0; ++ if (config->napi) { + if (config->intr_type == MSI_X) { +- for (; off < sp->config.rx_ring_num; off++) +- napi_disable(&sp->mac_control.rings[off].napi); +- } +- else +- napi_disable(&sp->napi); ++ for (cnt = 0; cnt < config->rx_ring_num; cnt++) ++ S2IO_NAPI_DISABLE(&sp->mac_control.rings[cnt].napi); ++ } ++ else ++ S2IO_NAPI_DISABLE(&sp->napi); + } + + /* disable Tx and Rx traffic on the NIC */ +@@ -7136,11 +9916,11 @@ + + s2io_rem_isr(sp); + +- /* stop the tx queue, indicate link down */ + s2io_link(sp, LINK_DOWN); + ++ cnt = 0; + /* Check if the device is Quiescent and then Reset the NIC */ +- while(do_io) { ++ while (do_io) { + /* As per the HW requirement we need to replenish the + * receive buffer to avoid the ring bump. Since there is + * no intention of processing the Rx frame at this pointwe are +@@ -7152,20 +9932,21 @@ + + val64 = readq(&bar0->adapter_status); + if (verify_xena_quiescence(sp)) { +- if(verify_pcc_quiescent(sp, sp->device_enabled_once)) +- break; ++ if (verify_pcc_quiescent(sp, sp->device_enabled_once)) ++ break; + } + + msleep(50); + cnt++; + if (cnt == 10) { + DBG_PRINT(ERR_DBG, +- "s2io_close:Device not Quiescent "); ++ "%s:%s:Device not Quiescent ", sp->dev->name, __FUNCTION__); + DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n", +- (unsigned long long) val64); +- break; +- } +- } ++ (unsigned long long) val64); ++ break; ++ } ++ } ++ + if (do_io) + s2io_reset(sp); + +@@ -7175,27 +9956,28 @@ + /* Free all Rx buffers */ + free_rx_buffers(sp); + +- clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state)); +-} +- +-static void s2io_card_down(struct s2io_nic * sp) ++ clear_bit(__S2IO_STATE_LINK_RESET_TASK, &(sp->state)); ++} ++ ++static void s2io_card_down(struct s2io_nic *sp) + { + do_s2io_card_down(sp, 1); + } + +-static int s2io_card_up(struct s2io_nic * sp) ++static int s2io_card_up(struct s2io_nic *sp) + { + int i, ret = 0; + struct mac_info *mac_control; + struct config_param *config; + struct net_device *dev = (struct net_device *) sp->dev; ++ struct ring_info *ring; + u16 interruptible; + + /* Initialize the H/W I/O registers */ + ret = init_nic(sp); + if (ret != 0) { + DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n", +- dev->name); ++ dev->name); + if (ret != -EIO) + s2io_reset(sp); + return ret; +@@ -7208,29 +9990,44 @@ + mac_control = &sp->mac_control; + config = &sp->config; + +- for (i = 0; i < config->rx_ring_num; i++) { +- mac_control->rings[i].mtu = dev->mtu; +- ret = fill_rx_buffers(sp, &mac_control->rings[i], 1); ++ ++ for (i = 0; i < config->rx_ring_num; i++) { ++ ring = &mac_control->rings[i]; ++ ring->skbs_per_rxd = 1; ++ if (ring->rxd_mode == RXD_MODE_5) { ++ if (dev->mtu <= MODE5_BUF_SIZE) ++ /* l3l4 Header + Payload */ ++ ring->skbs_per_rxd = 2; ++ else ++ if (dev->mtu <= (2 * MODE5_BUF_SIZE)) ++ /* Header+2*Payload */ ++ ring->skbs_per_rxd = 3; ++ else ++ /* Header+3*Payload */ ++ ring->skbs_per_rxd = 4; ++ } ++ ring->mtu = dev->mtu; ++ ret = fill_rx_buffers(ring, 1); + if (ret) { +- DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n", +- dev->name); ++ DBG_PRINT(ERR_DBG, "%s - %s: Out of memory in Open\n", ++ __FUNCTION__, dev->name); + s2io_reset(sp); + free_rx_buffers(sp); + return -ENOMEM; + } + DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i, +- mac_control->rings[i].rx_bufs_left); +- } +- +- /* Initialise napi */ ++ ring->rx_bufs_left); ++ } ++ ++ /* Initialize napi */ + if (config->napi) { +- int i; + if (config->intr_type == MSI_X) { + for (i = 0; i < sp->config.rx_ring_num; i++) +- napi_enable(&sp->mac_control.rings[i].napi); +- } else { +- napi_enable(&sp->napi); +- } ++ S2IO_NAPI_ENABLE( ++ &sp->mac_control.rings[i].napi); ++ } ++ else ++ S2IO_NAPI_ENABLE(&sp->napi); + } + + /* Maintain the state prior to the open */ +@@ -7238,7 +10035,7 @@ + sp->promisc_flg = 0; + if (sp->m_cast_flg) { + sp->m_cast_flg = 0; +- sp->all_multi_pos= 0; ++ sp->all_multi_pos = 0; + } + + /* Setting its receive mode */ +@@ -7246,10 +10043,18 @@ + + if (sp->lro) { + /* Initialize max aggregatable pkts per session based on MTU */ +- sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu; +- /* Check if we can use(if specified) user provided value */ +- if (lro_max_pkts < sp->lro_max_aggr_per_sess) +- sp->lro_max_aggr_per_sess = lro_max_pkts; ++ sp->lro_max_aggr_per_sess = (lro_max_bytes - 1) / dev->mtu; ++ ++ if (sp->lro_max_aggr_per_sess < MIN_LRO_PACKETS) ++ sp->lro_max_aggr_per_sess = MIN_LRO_PACKETS; ++ ++ if (sp->lro_max_aggr_per_sess > MAX_LRO_PACKETS) ++ sp->lro_max_aggr_per_sess = MAX_LRO_PACKETS; ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) { ++ ring = &mac_control->rings[i]; ++ ring->lro_max_aggr_per_sess = sp->lro_max_aggr_per_sess; ++ } + } + + /* Enable Rx Traffic and interrupts on the NIC */ +@@ -7262,12 +10067,14 @@ + + /* Add interrupt service routine */ + if (s2io_add_isr(sp) != 0) { +- if (sp->config.intr_type == MSI_X) +- s2io_rem_isr(sp); + s2io_reset(sp); + free_rx_buffers(sp); + return -ENODEV; + } ++ ++ sp->chk_dte_count = 0; ++ sp->chk_device_error_count = 0; ++ sp->chk_rx_queue_count = 0; + + S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2)); + +@@ -7297,26 +10104,29 @@ + * spin lock. + */ + ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++static void s2io_restart_nic(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *) data; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++#else + static void s2io_restart_nic(struct work_struct *work) + { +- struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task); ++ struct s2io_nic *sp = container_of(work, struct s2io_nic, ++ rst_timer_task); + struct net_device *dev = sp->dev; +- +- rtnl_lock(); ++#endif ++ int ret = 0; + + if (!netif_running(dev)) +- goto out_unlock; +- +- s2io_card_down(sp); +- if (s2io_card_up(sp)) { +- DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", +- dev->name); +- } ++ return; ++ ++ ret = s2io_restart_card(sp); ++ if(ret) ++ return; ++ + s2io_wake_all_tx_queue(sp); +- DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", +- dev->name); +-out_unlock: +- rtnl_unlock(); ++ sp->mac_stat_info->soft_reset_cnt++; + } + + /** +@@ -7334,14 +10144,85 @@ + + static void s2io_tx_watchdog(struct net_device *dev) + { +- struct s2io_nic *sp = dev->priv; +- ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ /* Donot reset in debug mode */ + if (netif_carrier_ok(dev)) { +- sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++; +- schedule_work(&sp->rst_timer_task); +- sp->mac_control.stats_info->sw_stat.soft_reset_cnt++; +- } +-} ++ sp->mac_stat_info->watchdog_timer_cnt++; ++ if (sp->exec_mode) { ++ DBG_PRINT(ERR_DBG, "%s: Tx watchdog timer reset\n", ++ dev->name); ++ schedule_work(&sp->rst_timer_task); ++ } ++ } ++} ++ ++#ifdef RX_ERR_DBG ++void dump_packet(struct ring_info *ring, struct sk_buff *skb, ++ struct RxD_t *rxdp) ++{ ++ int len = 0, buf0_len = 0, buf1_len = 0, frag_len = 0, i = 0, j; ++ struct sk_buff *frag_list = skb_shinfo(skb)->frag_list; ++ u8 *ptr = skb->data; ++ u8 *frag_ptr = frag_list->data; ++ struct RxD5 *rxdptr; ++ ++ if (!skb->len) { ++ if (ring->rxd_mode == RXD_MODE_1) { ++ len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2); ++ } else if (ring->rxd_mode == RXD_MODE_5) { ++ rxdptr = (struct RxD5 *)rxdp; ++ buf0_len = RXD_GET_BUFFER0_SIZE_5(rxdp->Control_2); ++ buf1_len = RXD_GET_BUFFER1_SIZE_5(rxdp->Control_2); ++ frag_len = RXD_GET_BUFFER2_SIZE_5(rxdp->Control_2); ++ if (ring->skbs_per_rxd > 2) ++ frag_len += RXD_GET_BUFFER3_SIZE_5 ++ (rxdptr->Control_3); ++ if (ring->skbs_per_rxd > 3) ++ frag_len += RXD_GET_BUFFER4_SIZE_5 ++ (rxdptr->Control_3); ++ len = buf0_len + buf1_len + frag_len; ++ } else if (ring->rxd_mode == RXD_MODE_3B) { ++ buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2); ++ len = buf0_len + ++ RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2); ++ } ++ ++ DBG_PRINT(ERR_DBG, "Packet contents : Length = %d\n", len); ++ ++ if (ring->rxd_mode >= RXD_MODE_3B) { ++ int get_block = ring->rx_curr_get_info.block_index; ++ int get_off = ring->rx_curr_get_info.offset; ++ struct buffAdd *ba = &ring->ba[get_block][get_off]; ++ for (i = 0; i < buf0_len; i += 2) { ++ DBG_PRINT(ERR_DBG, "%02x%02x ", ++ *(u8 *)(ba->ba_0 + i), ++ *(u8 *)(ba->ba_0 + i + 1)); ++ if (!((i + 2) % 16)) ++ DBG_PRINT(ERR_DBG, "\n"); ++ } ++ } ++ } else { ++ len = skb->len; ++ frag_len = frag_list->len; ++ DBG_PRINT(ERR_DBG, "Packet contents : Length = %d\n", len); ++ } ++ for (j = 0; j < (len - buf0_len - frag_len); j += 2, i += 2) { ++ DBG_PRINT(ERR_DBG, "%02x%02x ", *(ptr + j), *(ptr + j + 1)); ++ if (!((i + 2) % 16)) ++ DBG_PRINT(ERR_DBG, "\n"); ++ } ++ ++ if (ring->rxd_mode == RXD_MODE_5) { ++ for (j = 0; j < frag_len; j += 2, i += 2) { ++ DBG_PRINT(ERR_DBG, "%02x%02x ", *(frag_ptr + j), ++ *(frag_ptr + j + 1)); ++ if (!((i + 2) % 16)) ++ DBG_PRINT(ERR_DBG, "\n"); ++ } ++ } ++ DBG_PRINT(ERR_DBG, "\n\n"); ++} ++#endif + + /** + * rx_osm_handler - To perform some OS related operations on SKB. +@@ -7360,72 +10241,78 @@ + * Return value: + * SUCCESS on success and -1 on failure. + */ +-static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp) +-{ +- struct s2io_nic *sp = ring_data->nic; +- struct net_device *dev = (struct net_device *) ring_data->dev; +- struct sk_buff *skb = (struct sk_buff *) +- ((unsigned long) rxdp->Host_Control); +- int ring_no = ring_data->ring_no; +- u16 l3_csum, l4_csum; +- unsigned long long err = rxdp->Control_1 & RXD_T_CODE; +- struct lro *lro; +- u8 err_mask; +- ++static int rx_osm_handler(struct ring_info *ring, struct RxD_t *rxdp) ++{ ++ struct net_device *dev = (struct net_device *) ring->dev; ++ struct sk_buff *skb = NULL; ++ u16 vlan_tag; ++ u16 vlan_id = 0; ++ int verify_vlan_registered = 0; ++ u8 err = rxdp->Control_1 & RXD_T_CODE; ++ struct lro *lro = NULL; ++ struct rxRingStat *ring_stats = ring->rx_ring_stat; ++ struct swLROStat *lro_stats = &ring->rx_ring_stat->sw_lro_stat; ++ ++ if (ring->rxd_mode == RXD_MODE_5) ++ skb = (struct sk_buff *) \ ++ ((unsigned long)ring->skbs[((unsigned long) \ ++ ((struct RxD5 *)rxdp)->Host_Control)]); ++ else ++ skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control); ++ ++#ifdef virt_addr_valid ++ if (!virt_addr_valid(skb)) { ++ DBG_PRINT(INFO_DBG, "%s: not valid SKB: %p\n", ++ dev->name, skb); ++ return 0; ++ } ++#endif + skb->dev = dev; +- ++ err = GET_RXD_T_CODE(rxdp->Control_1); + if (err) { +- /* Check for parity error */ +- if (err & 0x1) { +- sp->mac_control.stats_info->sw_stat.parity_err_cnt++; +- } +- err_mask = err >> 48; +- switch(err_mask) { +- case 1: +- sp->mac_control.stats_info->sw_stat. +- rx_parity_err_cnt++; +- break; +- +- case 2: +- sp->mac_control.stats_info->sw_stat. +- rx_abort_cnt++; +- break; +- +- case 3: +- sp->mac_control.stats_info->sw_stat. +- rx_parity_abort_cnt++; +- break; +- +- case 4: +- sp->mac_control.stats_info->sw_stat. +- rx_rda_fail_cnt++; +- break; +- +- case 5: +- sp->mac_control.stats_info->sw_stat. +- rx_unkn_prot_cnt++; +- break; +- +- case 6: +- sp->mac_control.stats_info->sw_stat. +- rx_fcs_err_cnt++; +- break; +- +- case 7: +- sp->mac_control.stats_info->sw_stat. +- rx_buf_size_err_cnt++; +- break; +- +- case 8: +- sp->mac_control.stats_info->sw_stat. +- rx_rxd_corrupt_cnt++; +- break; +- +- case 15: +- sp->mac_control.stats_info->sw_stat. +- rx_unkn_err_cnt++; +- break; +- } ++ switch (err) { ++ case 1: ++ ring->rx_ring_stat->rx_parity_err_cnt++; ++ break; ++ ++ case 2: ++ ring->rx_ring_stat->rx_abort_cnt++; ++ break; ++ ++ case 3: ++ ring->rx_ring_stat->rx_parity_abort_cnt++; ++ break; ++ ++ case 4: ++ ring->rx_ring_stat->rx_rda_fail_cnt++; ++ break; ++ ++ case 5: ++ ring->rx_ring_stat->rx_unkn_prot_cnt++; ++ break; ++ ++ case 6: ++ ring->rx_ring_stat->rx_fcs_err_cnt++; ++ break; ++ ++ case 7: ++ ring->rx_ring_stat->rx_buf_size_err_cnt++; ++ break; ++ ++ case 8: ++ ring->rx_ring_stat->rx_rxd_corrupt_cnt++; ++ break; ++ ++ case 15: ++ ring->rx_ring_stat->rx_unkn_err_cnt++; ++ break; ++ } ++ ++#ifdef RX_ERR_DBG ++ DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n", ++ dev->name, err); ++ dump_packet(ring, skb, rxdp); ++#endif + /* + * Drop the packet if bad transfer code. Exception being + * 0x5, which could be due to unsupported IPv6 extension header. +@@ -7433,104 +10320,187 @@ + * Note that in this case, since checksum will be incorrect, + * stack will validate the same. + */ +- if (err_mask != 0x5) { +- DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n", +- dev->name, err_mask); ++ if (err != 0x5) { ++ DBG_PRINT(INFO_DBG, "%s: Rx error Value: 0x%x\n", ++ dev->name, err); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22)) ++ ring->nic->prev_stats.rx_crc_errors++; ++#else + dev->stats.rx_crc_errors++; +- sp->mac_control.stats_info->sw_stat.mem_freed +- += skb->truesize; ++#endif ++ ring_stats->rx_mem_freed += skb->truesize; + dev_kfree_skb(skb); +- ring_data->rx_bufs_left -= 1; ++ ring->rx_bufs_left -= 1; + rxdp->Host_Control = 0; + return 0; + } + } ++#ifdef RX_ERR_DBG ++ else if (ring->nic->ecc_flag) { ++ DBG_PRINT(ERR_DBG, "%s: ECC error encountered\n", ++ dev->name); ++ dump_packet(ring, skb, rxdp); ++ } ++#endif ++ ++ vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2); ++ ++ /* Check the packet for correct registered vlan id*/ ++ if ((ring->ring_no == 0) && ++ (ring->rx_steering_type == RX_VLAN_STEERING)) ++ verify_vlan_registered = 1; ++ ++ if (verify_vlan_registered || ring->lro){ ++ /* Is the frame VLAN tagged? */ ++ if (rxdp->Control_1 & RXD_FRAME_VLAN_TAG) ++ /* Get the vlan id */ ++ vlan_id = VLAN_VID_MASK & vlan_tag; ++ if (!vlan_id) ++ verify_vlan_registered = 0; ++ /* VLANs are not yet registered and is in promiscous mode */ ++ if (!ring->vlgrp && ring->nic->promisc_flg) ++ verify_vlan_registered = 0; ++ } ++ ++ if (verify_vlan_registered) { ++ /* Is it registered */ ++ if ((vlan_id >= VLAN_VID_MASK) || ++ (S2IO_INVALID_RING == ++ ring->nic->vlan_array[vlan_id])) { ++ DBG_PRINT(INFO_DBG, "%s: Drop the unregistered" ++ " vlan packet with VID = %d\n", ++ dev->name, vlan_id); ++ ring_stats->rx_mem_freed += skb->truesize; ++ dev_kfree_skb(skb); ++ ring->rx_bufs_left -= 1; ++ rxdp->Host_Control = 0; ++ return 0; ++ } ++ } + + /* Updating statistics */ +- ring_data->rx_packets++; +- rxdp->Host_Control = 0; +- if (sp->rxd_mode == RXD_MODE_1) { ++ if (ring->rxd_mode == RXD_MODE_5) ++ ((struct RxD5 *)rxdp)->Host_Control = 0; ++ else ++ rxdp->Host_Control = 0; ++ ++ ring->rx_packets++; ++ if (ring->rxd_mode == RXD_MODE_1) { + int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2); +- +- ring_data->rx_bytes += len; ++ ring->rx_bytes += len; + skb_put(skb, len); +- +- } else if (sp->rxd_mode == RXD_MODE_3B) { +- int get_block = ring_data->rx_curr_get_info.block_index; +- int get_off = ring_data->rx_curr_get_info.offset; ++ } else if (ring->rxd_mode == RXD_MODE_5) { ++ int get_block = ring->rx_curr_get_info.block_index; ++ int get_off = ring->rx_curr_get_info.offset; ++ int buf0_len = RXD_GET_BUFFER0_SIZE_5(rxdp->Control_2); ++ int buf1_len = RXD_GET_BUFFER1_SIZE_5(rxdp->Control_2); ++ int buf2_len = RXD_GET_BUFFER2_SIZE_5(rxdp->Control_2); ++ int buf3_len = ++ RXD_GET_BUFFER3_SIZE_5(((struct RxD5 *)rxdp)->Control_3); ++ int buf4_len = ++ RXD_GET_BUFFER4_SIZE_5(((struct RxD5 *)rxdp)->Control_3); ++ unsigned char *buff = skb_push(skb, buf0_len); ++ struct buffAdd *ba = &ring->ba[get_block][get_off]; ++ struct sk_buff *frag_list = NULL; ++ ++ memcpy(buff, ba->ba_0, buf0_len); ++ ++ ring->rx_bytes += buf0_len + buf1_len + buf2_len + ++ buf3_len + buf4_len; ++ ++ skb_put(skb, buf1_len); ++ skb->len += buf2_len; ++ skb->data_len += buf2_len; ++ frag_list = skb_shinfo(skb)->frag_list; ++ skb_put(frag_list, buf2_len); ++ if (ring->skbs_per_rxd > 2) { ++ skb->len += buf3_len; ++ skb->data_len += buf3_len; ++ skb_put(frag_list->next, buf3_len); ++ } ++ if (ring->skbs_per_rxd > 3) { ++ skb->len += buf4_len; ++ skb->data_len += buf4_len; ++ frag_list = frag_list->next; ++ skb_put(frag_list->next, buf4_len); ++ } ++ } else if (ring->rxd_mode >= RXD_MODE_3B) { ++ int get_block = ring->rx_curr_get_info.block_index; ++ int get_off = ring->rx_curr_get_info.offset; + int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2); + int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2); + unsigned char *buff = skb_push(skb, buf0_len); + +- struct buffAdd *ba = &ring_data->ba[get_block][get_off]; +- ring_data->rx_bytes += buf0_len + buf2_len; ++ struct buffAdd *ba = &ring->ba[get_block][get_off]; ++ ring->rx_bytes += buf0_len + buf2_len; ++ + memcpy(buff, ba->ba_0, buf0_len); ++ + skb_put(skb, buf2_len); + } + +- if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!ring_data->lro) || +- (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) && +- (sp->rx_csum)) { +- l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1); +- l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1); +- if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) { +- /* +- * NIC verifies if the Checksum of the received +- * frame is Ok or not and accordingly returns +- * a flag in the RxD. +- */ ++ if ((rxdp->Control_1 & RXD_TCP_OR_UDP_FRAME) && ((!ring->lro) || ++ (ring->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) && ++ (ring->rx_csum)) { ++ if ((RXD_GET_L3_CKSUM(rxdp->Control_1) == L3_CKSUM_OK) && ++ (RXD_GET_L4_CKSUM(rxdp->Control_1) == L4_CKSUM_OK)) { + skb->ip_summed = CHECKSUM_UNNECESSARY; +- if (ring_data->lro) { +- u32 tcp_len; ++ if (ring->lro && ((rxdp->Control_1 & ++ RXD_TCP_IPV4_FRAME) == RXD_TCP_IPV4_FRAME)) { ++ u32 tcp_len = 0; + u8 *tcp; + int ret = 0; + +- ret = s2io_club_tcp_session(ring_data, +- skb->data, &tcp, &tcp_len, &lro, +- rxdp, sp); +- switch (ret) { +- case 3: /* Begin anew */ +- lro->parent = skb; +- goto aggregate; +- case 1: /* Aggregate */ +- { +- lro_append_pkt(sp, lro, +- skb, tcp_len); +- goto aggregate; ++ ret = s2io_club_tcp_session(ring, skb->data, ++ &tcp, &tcp_len, &lro, rxdp, vlan_id); ++ ++ if (lro && (lro->sg_num > ring->max_pkts_aggr)){ ++ lro->vlan_tag = vlan_tag; ++ ring->max_pkts_aggr = lro->sg_num; ++ } ++ ++ if (LRO_AGGR_PACKET == ret) { ++ lro_append_pkt(ring, lro, skb, tcp_len, ++ ring->aggr_ack); ++ goto aggregate; ++ } else if (LRO_BEG_AGGR == ret) { ++ lro->parent = skb; ++ if (ring->rxd_mode == RXD_MODE_5) { ++ struct sk_buff *frag_list = ++ skb_shinfo(skb)->frag_list; ++ if (frag_list) { ++ /* Traverse to the end ++ * of the list*/ ++ while (frag_list->next) ++ frag_list = ++ frag_list->next; ++ lro->last_frag = ++ frag_list; ++ lro->frags_len = ++ skb->data_len; ++ } + } +- case 4: /* Flush session */ +- { +- lro_append_pkt(sp, lro, +- skb, tcp_len); +- queue_rx_frame(lro->parent, +- lro->vlan_tag); +- clear_lro_session(lro); +- sp->mac_control.stats_info-> +- sw_stat.flush_max_pkts++; +- goto aggregate; +- } +- case 2: /* Flush both */ +- lro->parent->data_len = +- lro->frags_len; +- sp->mac_control.stats_info-> +- sw_stat.sending_both++; +- queue_rx_frame(lro->parent, +- lro->vlan_tag); +- clear_lro_session(lro); +- goto send_up; +- case 0: /* sessions exceeded */ +- case -1: /* non-TCP or not +- * L2 aggregatable +- */ +- case 5: /* +- * First pkt in session not +- * L3/L4 aggregatable +- */ +- break; +- default: +- DBG_PRINT(ERR_DBG, +- "%s: Samadhana!!\n", +- __FUNCTION__); ++ goto aggregate; ++ } else if (LRO_FLUSH_SESSION == ret) { ++ lro_append_pkt(ring, lro, skb, tcp_len, ++ ring->aggr_ack); ++ queue_rx_frame(lro->parent, ++ ring, lro->vlan_tag); ++ clear_lro_session(lro); ++ lro_stats->flush_max_pkts++; ++ goto aggregate; ++ } else if (LRO_FLUSH_BOTH == ret) { ++ lro->parent->data_len = lro->frags_len; ++ lro_stats->sending_both++; ++ queue_rx_frame(lro->parent, ++ ring, lro->vlan_tag); ++ clear_lro_session(lro); ++ goto send_up; ++ } else if ((0 != ret) && (-1 != ret) && ++ (5 != ret)) { ++ DBG_PRINT(INFO_DBG, ++ "%s:Tcp Session Unhandled\n", ++ __FUNCTION__); + BUG(); + } + } +@@ -7540,16 +10510,23 @@ + * upper layers deal with it. + */ + skb->ip_summed = CHECKSUM_NONE; +- } +- } else ++#ifdef RX_ERR_DBG ++ DBG_PRINT(ERR_DBG, "%s: Checksum error\n", ++ dev->name); ++ dump_packet(ring, skb, rxdp); ++#endif ++ } ++ } else { + skb->ip_summed = CHECKSUM_NONE; +- +- sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize; ++ } ++ ++ ring_stats->rx_mem_freed += skb->truesize; ++ + send_up: +- queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2)); ++ queue_rx_frame(skb, ring, vlan_tag); + dev->last_rx = jiffies; + aggregate: +- sp->mac_control.rings[ring_no].rx_bufs_left -= 1; ++ ring->rx_bufs_left -= 1; + return SUCCESS; + } + +@@ -7566,32 +10543,93 @@ + * void. + */ + +-static void s2io_link(struct s2io_nic * sp, int link) ++static void s2io_link(struct s2io_nic *sp, int link) + { + struct net_device *dev = (struct net_device *) sp->dev; ++ struct swDbgStat *stats = sp->sw_dbg_stat; + + if (link != sp->last_link_state) { + init_tti(sp, link); + if (link == LINK_DOWN) { + DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name); + s2io_stop_all_tx_queue(sp); ++ + netif_carrier_off(dev); +- if(sp->mac_control.stats_info->sw_stat.link_up_cnt) +- sp->mac_control.stats_info->sw_stat.link_up_time = +- jiffies - sp->start_time; +- sp->mac_control.stats_info->sw_stat.link_down_cnt++; ++ if (stats->link_up_cnt) ++ stats->link_up_time = jiffies - sp->start_time; ++ stats->link_down_cnt++; + } else { + DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name); +- if (sp->mac_control.stats_info->sw_stat.link_down_cnt) +- sp->mac_control.stats_info->sw_stat.link_down_time = +- jiffies - sp->start_time; +- sp->mac_control.stats_info->sw_stat.link_up_cnt++; ++ ++ if (stats->link_down_cnt) ++ stats->link_down_time = ++ jiffies - sp->start_time; ++ stats->link_up_cnt++; + netif_carrier_on(dev); + s2io_wake_all_tx_queue(sp); + } + } + sp->last_link_state = link; + sp->start_time = jiffies; ++} ++ ++/** ++ * get_xena_rev_id - to identify revision ID of xena. ++ * @pdev : PCI Dev structure ++ * Description: ++ * Function to identify the Revision ID of xena. ++ * Return value: ++ * returns the revision ID of the device. ++ */ ++ ++static int get_xena_rev_id(struct pci_dev *pdev) ++{ ++ u8 id = 0; ++ pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) &id); ++ return id; ++} ++ ++/* Returns 1 if system has AMD 8131 or Broadcom HT 1000 chipset. ++* Returns 0 otherwise ++*/ ++static int check_for_pcix_safe_param(void) ++{ ++ struct pci_dev *tdev = NULL; ++ u8 set_param = 0; ++ ++ if ((tdev = S2IO_PCI_FIND_DEVICE(0x1022, 0x7450, NULL))!= NULL) { ++ S2IO_PCI_PUT_DEVICE(tdev); ++ DBG_PRINT(INIT_DBG, "Found AMD 8131a bridge\n"); ++ set_param = 1; ++ } ++ ++ if ((tdev = S2IO_PCI_FIND_DEVICE(0x1166, 0x0104, NULL)) != NULL) { ++ S2IO_PCI_PUT_DEVICE(tdev); ++ DBG_PRINT(INIT_DBG, "Found Broadcom HT 1000 bridge\n"); ++ set_param = 1; ++ } ++ return set_param; ++} ++ ++static u8 update_8132_hyper_transport; ++static void amd_8132_update_hyper_tx(u8 set_reset) ++{ ++ struct pci_dev *tdev = NULL; ++ u8 id = 0, ret; ++ ++ while ((tdev = S2IO_PCI_FIND_DEVICE(PCI_VENDOR_ID_AMD, ++ PCI_DEVICE_ID_AMD_8132_BRIDGE, tdev)) != NULL) { ++ ret = pci_read_config_byte(tdev, 0xf6, (u8 *) &id); ++ if (set_reset & S2IO_BIT_SET) { ++ if (id != 1) { ++ ret = pci_write_config_byte(tdev, 0xf6, 1); ++ update_8132_hyper_transport = 1; ++ } ++ } else { ++ if (update_8132_hyper_transport && (id == 1)) ++ ret = pci_write_config_byte(tdev, 0xf6, 0); ++ } ++ } + } + + /** +@@ -7599,19 +10637,19 @@ + * @sp : private member of the device structure, which is a pointer to the + * s2io_nic structure. + * Description: +- * This function initializes a few of the PCI and PCI-X configuration registers +- * with recommended values. ++ * This function initializes a few of the PCI and PCI-X configuration ++ * registers with recommended values. + * Return value: + * void + */ + +-static void s2io_init_pci(struct s2io_nic * sp) ++static void s2io_init_pci(struct s2io_nic *sp) + { + u16 pci_cmd = 0, pcix_cmd = 0; + + /* Enable Data Parity Error Recovery in PCI-X command register. */ + pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, +- &(pcix_cmd)); ++ &(pcix_cmd)); + pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, + (pcix_cmd | 1)); + pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, +@@ -7622,30 +10660,303 @@ + pci_write_config_word(sp->pdev, PCI_COMMAND, + (pci_cmd | PCI_COMMAND_PARITY)); + pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd); +-} +- +-static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type, +- u8 *dev_multiq) +-{ +- if ((tx_fifo_num > MAX_TX_FIFOS) || +- (tx_fifo_num < 1)) { ++ ++ /* ++ * If system has AMD 8131a(rev12 and below) OR ++ * Broadcom HT 1000 bridge, set safe PCI-X ++ * parameters(MMRBC=1K and max splits = 2) ++ */ ++ if (check_for_pcix_safe_param()) { ++ pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, ++ &(pcix_cmd)); ++ pcix_cmd &= ~(0x7c); ++ pcix_cmd |= 0x14; ++ pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, ++ pcix_cmd); ++ DBG_PRINT(INIT_DBG, "Found AMD 8131a bridge\n"); ++ } ++} ++ ++static void print_static_param_list(struct net_device *dev) ++{ ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ ++ DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name, ++ sp->config.tx_fifo_num); ++ ++ DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name, ++ sp->config.rx_ring_num); ++ ++ DBG_PRINT(ERR_DBG, "%s: %d-Buffer receive mode enabled\n", ++ dev->name, rx_ring_mode); ++ ++ if (lro_enable == S2IO_DONT_AGGR_FWD_PKTS) { ++ DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n", ++ dev->name); ++ } else if (lro_enable == S2IO_ALWAYS_AGGREGATE) { ++ DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled " ++ "for all packets\n", dev->name); ++ } else ++ DBG_PRINT(ERR_DBG, "%s: Large receive offload disabled\n", ++ dev->name); ++ ++ if (vlan_tag_strip == S2IO_STRIP_VLAN_TAG) { ++ DBG_PRINT(ERR_DBG, "%s: Vlan tag stripping enabled\n", ++ dev->name); ++ } else if (vlan_tag_strip == S2IO_DO_NOT_STRIP_VLAN_TAG) ++ DBG_PRINT(ERR_DBG, "%s: Vlan tag stripping disabled\n", ++ dev->name); ++ if (ufo) { ++ if (sp->device_type != XFRAME_II_DEVICE) { ++ DBG_PRINT(ERR_DBG, "%s: Xframe I does not support UDP " ++ "Fragmentation Offload(UFO)\n", dev->name); ++ } else ++ DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)" ++ " enabled\n", dev->name); ++ } else ++ DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO) " ++ "disabled\n", dev->name); ++ ++ if (sp->config.tx_steering_type == TX_MULTIQ_STEERING) { ++ DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n", ++ dev->name); ++ } else ++ DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n", ++ dev->name); ++ ++ if (dev->mtu == 1500) ++ DBG_PRINT(ERR_DBG, "%s: MTU size is %d\n", ++ dev->name, dev->mtu); ++ ++ switch (sp->config.intr_type) { ++ case INTA: ++ DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name); ++ break; ++ case MSI_X: ++ DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name); ++ break; ++ } ++ ++ switch (sp->config.tx_steering_type) { ++ case TX_PRIORITY_STEERING: ++ DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for " ++ "transmit\n", dev->name); ++ break; ++ case TX_VLAN_STEERING: ++ DBG_PRINT(ERR_DBG, "%s: VLAN steering enabled for " ++ "transmit\n", dev->name); ++ break; ++ } ++ ++ switch (sp->config.rx_steering_type) { ++ case RX_TOS_STEERING: ++ DBG_PRINT(ERR_DBG, "%s: TOS steering enabled " ++ "for receive\n", dev->name); ++ break; ++ case RX_VLAN_STEERING: ++ DBG_PRINT(ERR_DBG, "%s: VLAN steering enabled for " ++ "receive\n", dev->name); ++ break; ++ case PORT_STEERING: ++ DBG_PRINT(ERR_DBG, "%s: PORT steering enabled\n", ++ dev->name); ++ break; ++ } ++ ++ if (sp->config.rx_steering_type == RTH_STEERING) { ++ switch (rth_protocol) { ++ case 1: ++ case 2: ++ if (1 == rth_protocol) { ++ DBG_PRINT(ERR_DBG, "%s: " \ ++ "RTH steering enabled for TCP_IPV4\n", ++ dev->name); ++ } else { ++ DBG_PRINT(ERR_DBG, "%s: " \ ++ "RTH steering enabled for UDP_IPV4\n", ++ dev->name); ++ } ++ ++ if ((rth_mask & S2IO_RTS_RTH_MASK_IPV6_SRC) || ++ (rth_mask & S2IO_RTS_RTH_MASK_IPV6_DST)) { ++ DBG_PRINT(ERR_DBG, "RTH Mask is not correct. " ++ "Disabling mask.\n"); ++ rth_mask = 0; ++ } ++ ++ break; ++ ++ case 3: ++ DBG_PRINT(ERR_DBG, ++ "%s: RTH steering enabled for IPV4 \n", ++ dev->name); ++ if ((rth_mask & S2IO_RTS_RTH_MASK_IPV6_SRC) || ++ (rth_mask & S2IO_RTS_RTH_MASK_IPV6_DST) || ++ (rth_mask & S2IO_RTS_RTH_MASK_L4_SRC) || ++ (rth_mask & S2IO_RTS_RTH_MASK_L4_DST)) { ++ DBG_PRINT(ERR_DBG, "RTH Mask is not correct. " ++ "Disabling mask.\n"); ++ rth_mask = 0; ++ } ++ break; ++ ++ case 4: ++ case 5: ++ if (4 == rth_protocol) { ++ DBG_PRINT(ERR_DBG, ++ "%s: RTH steering enabled for " \ ++ "TCP_IPV6 \n", dev->name); ++ } else { ++ DBG_PRINT(ERR_DBG, ++ "%s: RTH steering enabled for " \ ++ "UDP_IPV6 \n", dev->name); ++ } ++ ++ if ((rth_mask & S2IO_RTS_RTH_MASK_IPV4_SRC) || ++ (rth_mask & S2IO_RTS_RTH_MASK_IPV4_DST)) { ++ DBG_PRINT(ERR_DBG, "RTH Mask is not correct. " ++ "Disabling mask.\n"); ++ rth_mask = 0; ++ } ++ break; ++ ++ case 6: ++ DBG_PRINT(ERR_DBG, ++ "%s: RTH steering enabled for IPV6 \n", ++ dev->name); ++ if ((rth_mask & S2IO_RTS_RTH_MASK_IPV4_SRC) || ++ (rth_mask & S2IO_RTS_RTH_MASK_IPV4_DST) || ++ (rth_mask & S2IO_RTS_RTH_MASK_L4_SRC) || ++ (rth_mask & S2IO_RTS_RTH_MASK_L4_DST)) { ++ DBG_PRINT(ERR_DBG, "RTH Mask is not correct. " ++ "Disabling mask.\n"); ++ rth_mask = 0; ++ } ++ break; ++ ++ case 7: ++ case 8: ++ case 9: ++ if (7 == rth_protocol) { ++ DBG_PRINT(ERR_DBG, ++ "%s: RTH steering enabled for " \ ++ "TCP_IPV6_EX \n", dev->name); ++ } else if (8 == rth_protocol) { ++ DBG_PRINT(ERR_DBG, ++ "%s: RTH steering enabled for " \ ++ "UDP_IPV6_EX \n", dev->name); ++ } else { ++ DBG_PRINT(ERR_DBG, ++ "%s: RTH steering enabled for " \ ++ "IPV6_EX \n", dev->name); ++ } ++ ++ if ((rth_mask & S2IO_RTS_RTH_MASK_IPV4_SRC) || ++ (rth_mask & S2IO_RTS_RTH_MASK_IPV4_DST)) { ++ DBG_PRINT(ERR_DBG, "RTH Mask is not correct. " ++ "Disabling mask.\n"); ++ rth_mask = 0; ++ } ++ break; ++ ++ default: ++ DBG_PRINT(ERR_DBG, "%s: RTH Function is not correct. " ++ "Defaulting to TCP_IPV4.\n", dev->name); ++ rth_protocol = 0x1; ++ if ((rth_mask & S2IO_RTS_RTH_MASK_IPV6_SRC) || ++ (rth_mask & S2IO_RTS_RTH_MASK_IPV6_DST)) { ++ DBG_PRINT(ERR_DBG, "RTH Mask is not correct. " ++ "Disabling mask.\n"); ++ rth_mask = 0; ++ } ++ ++ break; ++ } ++ ++ if ((rth_mask < 0) || (rth_mask > 255)) { ++ DBG_PRINT(ERR_DBG, "RTH Mask is not correct. " ++ "Disabling mask.\n"); ++ rth_mask = 0; ++ } ++ } ++ ++ if (sp->config.napi) { ++ DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name); ++ } ++ else { ++ DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name); ++ } ++ ++ return; ++} ++ ++static void s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type, ++ u8 *dev_steer_type, u8 *dev_tx_steer_type, int no_cpus) ++{ ++ if (lro_enable) { ++ if (lro_enable > S2IO_DONT_AGGR_FWD_PKTS) { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 9)) ++ DBG_PRINT(ERR_DBG, "s2io: Unsupported LRO option. " ++ "Disabling LRO\n"); ++ lro_enable = S2IO_DONOT_AGGREGATE; ++#else ++ DBG_PRINT(ERR_DBG, ++ "s2io: Unsupported LRO option. Enabling LRO " ++ "for local destination\n"); ++ lro_enable = S2IO_DONT_AGGR_FWD_PKTS; ++#endif ++ } ++ } ++ ++ if (vlan_tag_strip) { ++ if (vlan_tag_strip > S2IO_DEFAULT_STRIP_MODE_VLAN_TAG) { ++ DBG_PRINT(ERR_DBG, ++ "s2io: Unsupported vlan tag sripping option. " ++ "Enabling vlan tag stripping " ++ "if vlan group present\n"); ++ vlan_tag_strip = S2IO_DEFAULT_STRIP_MODE_VLAN_TAG; ++ } ++ } ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 23)) ++ if (tx_steering_type == TX_MULTIQ_STEERING) { ++ DBG_PRINT(ERR_DBG, "s2io: Multiqueue is not supported by this " ++ "driver on this kernel\n"); ++ tx_steering_type = NO_STEERING; ++ } ++#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26)) ++#ifndef CONFIG_NETDEVICES_MULTIQUEUE ++ if (tx_steering_type == TX_MULTIQ_STEERING) { ++ DBG_PRINT(ERR_DBG, "S2io: Multiqueue is not supported by this " ++ "driver on this kernel\n"); ++ tx_steering_type = NO_STEERING; ++#endif ++#endif ++ ++ /* user didn't specify the fifo numbers */ ++ if (tx_fifo_num == 0) { ++ if ( (tx_steering_type == TX_VLAN_STEERING) || ++ (tx_steering_type == TX_PRIORITY_STEERING)) ++ tx_fifo_num = MAX_TX_FIFOS; ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 26)) ++ else if (tx_steering_type == TX_MULTIQ_STEERING) ++ tx_fifo_num = no_cpus; ++#endif ++ else ++ tx_fifo_num = FIFO_DEFAULT_NUM; ++ } ++ ++ if (tx_fifo_num > MAX_TX_FIFOS) { + DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos " + "(%d) not supported\n", tx_fifo_num); +- +- if (tx_fifo_num < 1) +- tx_fifo_num = 1; +- else +- tx_fifo_num = MAX_TX_FIFOS; ++ tx_fifo_num = MAX_TX_FIFOS; + + DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num); + DBG_PRINT(ERR_DBG, "tx fifos\n"); + } + +- if (multiq) +- *dev_multiq = multiq; +- + if (tx_steering_type && (1 == tx_fifo_num)) { +- if (tx_steering_type != TX_DEFAULT_STEERING) ++ if (tx_steering_type != TX_STEERING_DEFAULT) + DBG_PRINT(ERR_DBG, + "s2io: Tx steering is not supported with " + "one fifo. Disabling Tx steering.\n"); +@@ -7653,11 +10964,38 @@ + } + + if ((tx_steering_type < NO_STEERING) || +- (tx_steering_type > TX_DEFAULT_STEERING)) { ++ (tx_steering_type > TX_STEERING_DEFAULT)) { + DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not " + "supported\n"); + DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n"); + tx_steering_type = NO_STEERING; ++ } ++ ++ if ((rx_steering_type < NO_STEERING) || ++ (rx_steering_type > RTH_STEERING_DEFAULT)) { ++ DBG_PRINT(ERR_DBG, "s2io: Requested receive steering not " ++ "supported\n"); ++ DBG_PRINT(ERR_DBG, "s2io: Disabling receive steering\n"); ++ rx_steering_type = NO_STEERING; ++ } ++ ++ if (rx_steering_type && (1 == rx_ring_num)) { ++ if (rx_steering_type != RTH_STEERING_DEFAULT) ++ DBG_PRINT(ERR_DBG, ++ "s2io: Receive steering is not supported with " ++ "one ring. Disabling receive steering.\n"); ++ *dev_steer_type = NO_STEERING; ++ } ++ ++ if (rx_steering_type) { ++ /* Check if it is a xena card */ ++ if ((pdev->device != PCI_DEVICE_ID_HERC_WIN) && ++ (pdev->device != PCI_DEVICE_ID_HERC_UNI)) { ++ if (rx_steering_type != RTH_STEERING_DEFAULT) ++ DBG_PRINT(ERR_DBG, ++ "s2io: Receive steering disabled on Xframe I\n"); ++ *dev_steer_type = NO_STEERING; ++ } + } + + if (rx_ring_num > MAX_RX_RINGS) { +@@ -7668,57 +11006,58 @@ + rx_ring_num = MAX_RX_RINGS; + } + +- if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) { ++#ifndef CONFIG_PCI_MSI ++ if (intr_type != INTA) { ++ DBG_PRINT(ERR_DBG, "s2io: This kernel does not support " ++ "MSI-X. Defaulting to INTA\n"); ++ *dev_intr_type = INTA; ++ intr_type = INTA; ++ } ++#else ++ if ((intr_type != INTA) && (intr_type != MSI_X)) { + DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. " + "Defaulting to INTA\n"); + *dev_intr_type = INTA; +- } +- +- if ((*dev_intr_type == MSI_X) && +- ((pdev->device != PCI_DEVICE_ID_HERC_WIN) && +- (pdev->device != PCI_DEVICE_ID_HERC_UNI))) { +- DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. " +- "Defaulting to INTA\n"); ++ intr_type = INTA; ++ } ++ ++ if ((pdev->device != PCI_DEVICE_ID_HERC_WIN) && ++ (pdev->device != PCI_DEVICE_ID_HERC_UNI)) { ++ if (intr_type == MSI_X) ++ DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support " ++ "MSI_X. Defaulting to INTA\n"); + *dev_intr_type = INTA; + } +- +- if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) { +- DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n"); ++#endif ++ ++#ifndef NETIF_F_UFO ++ if (ufo) { ++ DBG_PRINT(ERR_DBG, "s2io: This kernel does not support " ++ "UDP Fragmentation Offload(UFO)\n"); ++ DBG_PRINT(ERR_DBG, ++ "s2io: UDP Fragmentation Offload(UFO) disabled\n"); ++ ufo = 0; ++ } ++#endif ++ ++ *dev_tx_steer_type = tx_steering_type; ++ ++#if defined CONFIG_PPC64 ++ if (rx_ring_mode == 2) { ++ rx_ring_mode = 1; ++ DBG_PRINT(ERR_DBG, "s2io: 2 Buffer mode is not supported " ++ "on PPC64 Arch. Switching to 1-buffer mode \n"); ++ } ++#endif ++ ++ if ((rx_ring_mode != 1) && (rx_ring_mode != 2) && ++ (rx_ring_mode != 5)) { ++ DBG_PRINT(ERR_DBG, ++ "s2io: Requested ring mode not supported\n"); + DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n"); + rx_ring_mode = 1; + } +- return SUCCESS; +-} +- +-/** +- * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS +- * or Traffic class respectively. +- * @nic: device private variable +- * Description: The function configures the receive steering to +- * desired receive ring. +- * Return Value: SUCCESS on success and +- * '-1' on failure (endian settings incorrect). +- */ +-static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring) +-{ +- struct XENA_dev_config __iomem *bar0 = nic->bar0; +- register u64 val64 = 0; +- +- if (ds_codepoint > 63) +- return FAILURE; +- +- val64 = RTS_DS_MEM_DATA(ring); +- writeq(val64, &bar0->rts_ds_mem_data); +- +- val64 = RTS_DS_MEM_CTRL_WE | +- RTS_DS_MEM_CTRL_STROBE_NEW_CMD | +- RTS_DS_MEM_CTRL_OFFSET(ds_codepoint); +- +- writeq(val64, &bar0->rts_ds_mem_ctrl); +- +- return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl, +- RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED, +- S2IO_BIT_RESET); ++ return; + } + + /** +@@ -7739,7 +11078,7 @@ + s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) + { + struct s2io_nic *sp; +- struct net_device *dev; ++ struct net_device *dev = NULL; + int i, j, ret; + int dma_flag = FALSE; + u32 mac_up, mac_down; +@@ -7749,60 +11088,98 @@ + struct mac_info *mac_control; + struct config_param *config; + int mode; +- u8 dev_intr_type = intr_type; +- u8 dev_multiq = 0; +- DECLARE_MAC_BUF(mac); +- +- ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq); +- if (ret) +- return ret; +- +- if ((ret = pci_enable_device(pdev))) { ++ u8 dev_intr_type, dev_tx_steer_type = tx_steering_type; ++ u8 dev_steer_type = rx_steering_type; ++ int no_cpus = 1; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 67)) ++ int no_online_cpus = 0; ++#endif ++ DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2009 Neterion Inc.\n"); ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 67)) ++ for (i = 0; i < NR_CPUS; i++) { ++ if (cpu_online_map & (1<= KERNEL_VERSION(2, 6, 00)) || \ ++ defined CONFIG_IA64_SGI_SN2 ++ if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) { ++ DBG_PRINT(ERR_DBG, "%s: \ ++ Unable to obtain 64bit DMA for \ ++ consistent allocations\n", __FUNCTION__); ++ ret = -ENOMEM; ++ goto set_dma_mask_failed; ++ } ++#endif + } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { +- DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n"); +- } else { +- pci_disable_device(pdev); +- return -ENOMEM; +- } +- if ((ret = pci_request_regions(pdev, s2io_driver_name))) { +- DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret); +- pci_disable_device(pdev); +- return -ENODEV; +- } +- if (dev_multiq) +- dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num); +- else +- dev = alloc_etherdev(sizeof(struct s2io_nic)); ++ DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __FUNCTION__); ++ } else { ++ ret = -ENOMEM; ++ goto set_dma_mask_failed; ++ } ++ ++ ret = pci_request_regions(pdev, s2io_driver_name); ++ if (ret) { ++ DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", ++ __FUNCTION__, ret); ++ ret = -ENODEV; ++ goto pci_request_regions_failed; ++ } ++ ++ dev = s2io_alloc_etherdev(sizeof(struct s2io_nic), tx_fifo_num, ++ dev_tx_steer_type); ++ + if (dev == NULL) { +- DBG_PRINT(ERR_DBG, "Device allocation failed\n"); +- pci_disable_device(pdev); +- pci_release_regions(pdev); +- return -ENODEV; ++ DBG_PRINT(ERR_DBG, "%s: Device allocation failed\n", ++ __FUNCTION__); ++ ret = -ENODEV; ++ goto alloc_etherdev_failed; + } + + pci_set_master(pdev); + pci_set_drvdata(pdev, dev); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 23)) ++ SET_MODULE_OWNER(dev); ++#endif + SET_NETDEV_DEV(dev, &pdev->dev); + + /* Private member variable initialized to s2io NIC structure */ +- sp = dev->priv; ++ sp = s2io_netdev_priv(dev); + memset(sp, 0, sizeof(struct s2io_nic)); ++ /* Default execution mode is release mode*/ ++ sp->exec_mode = 1; ++ sp->serious_err = 0; ++#ifdef RX_ERR_DBG ++ sp->ecc_flag = 0; ++#endif + sp->dev = dev; + sp->pdev = pdev; + sp->high_dma_flag = dma_flag; +@@ -7811,19 +11188,8 @@ + sp->rxd_mode = RXD_MODE_1; + if (rx_ring_mode == 2) + sp->rxd_mode = RXD_MODE_3B; +- +- sp->config.intr_type = dev_intr_type; +- +- if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) || +- (pdev->device == PCI_DEVICE_ID_HERC_UNI)) +- sp->device_type = XFRAME_II_DEVICE; +- else +- sp->device_type = XFRAME_I_DEVICE; +- +- sp->lro = lro_enable; +- +- /* Initialize some PCI/PCI-X fields of the NIC. */ +- s2io_init_pci(sp); ++ if (rx_ring_mode == 5) ++ sp->rxd_mode = RXD_MODE_5; + + /* + * Setting the device configuration parameters. +@@ -7835,14 +11201,145 @@ + mac_control = &sp->mac_control; + config = &sp->config; + ++ config->rst_q_stuck = rst_q_stuck; + config->napi = napi; +- config->tx_steering_type = tx_steering_type; ++ config->intr_type = dev_intr_type; ++ config->rx_steering_type = dev_steer_type; ++ config->tx_steering_type = dev_tx_steer_type; ++ config->vlan_tag_strip = vlan_tag_strip; ++ config->tx_fifo_num = tx_fifo_num; ++ ++ sp->vlan_strip_flag = config->vlan_tag_strip; ++ if (sp->vlan_strip_flag == S2IO_DEFAULT_STRIP_MODE_VLAN_TAG) ++ sp->vlan_strip_flag = S2IO_DO_NOT_STRIP_VLAN_TAG; ++ ++#ifdef SNMP_SUPPORT ++ strcpy(sp->cName, "NETERION"); ++ strcpy(sp->cVersion, DRV_VERSION); ++#endif ++#ifdef TITAN_LEGACY ++ if ((pdev->device == PCI_DEVICE_ID_TITAN_WIN) || ++ (pdev->device == PCI_DEVICE_ID_TITAN_UNI)) ++ sp->device_type = TITAN_DEVICE; ++ else ++#endif ++ if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) || ++ (pdev->device == PCI_DEVICE_ID_HERC_UNI)) { ++ u16 pci_cmd; ++ sp->device_type = XFRAME_II_DEVICE; ++ pci_read_config_word(sp->pdev, PCI_SUBSYSTEM_ID, &pci_cmd); ++ for (i = 0; i < ARRAY_SIZE(s2io_subsystem_id); i++) ++ if (pci_cmd == s2io_subsystem_id[i]) { ++ sp->device_sub_type = XFRAME_E_DEVICE; ++ break; ++ } ++ } else ++ sp->device_type = XFRAME_I_DEVICE; ++ ++ sp->lro = lro_enable; ++ ++ /* Initialize some PCI/PCI-X fields of the NIC. */ ++ s2io_init_pci(sp); ++ ++ /* By default, the mapping from MSI/MSI-X to hyper transport interrupts ++ is disabled on AMD 8132 bridge. Enable this to support MSI-X interrupts ++ */ ++ if (MSI_X == intr_type) ++ amd_8132_update_hyper_tx(S2IO_BIT_SET); ++ ++ sp->bar0 = (void __iomem *) ioremap(pci_resource_start(pdev, 0), ++ pci_resource_len(pdev, 0)); ++ if (!sp->bar0) { ++ DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__); ++ DBG_PRINT(ERR_DBG, "cannot remap io mem1\n"); ++ ret = -ENOMEM; ++ goto bar0_remap_failed; ++ } ++ ++ sp->bar1 = (void __iomem *) ioremap(pci_resource_start(pdev, 2), ++ pci_resource_len(pdev, 2)); ++ if (!sp->bar1) { ++ DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__); ++ DBG_PRINT(ERR_DBG, "cannot remap io mem2\n"); ++ ret = -ENOMEM; ++ goto bar1_remap_failed; ++ } ++ ++ dev->irq = pdev->irq; ++ dev->base_addr = (unsigned long) sp->bar0; ++ ++ /* Setting swapper control on the NIC, for proper reset operation */ ++ if (s2io_set_swapper(sp)) { ++ DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__); ++ DBG_PRINT(ERR_DBG, "swapper settings are wrong\n"); ++ ret = -EAGAIN; ++ goto set_swap_failed; ++ } ++ ++ /* Verify if the Herc works on the slot its placed into */ ++ if (sp->device_type == XFRAME_II_DEVICE) { ++ mode = s2io_verify_pci_mode(sp); ++ if (mode < 0) { ++ DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__); ++ DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n"); ++ ret = -EBADSLT; ++ goto set_swap_failed; ++ } ++ } ++ ++ /* Decice on the number of rings */ ++ config->rx_ring_num = rx_ring_num; ++ ++ if (rx_ring_num == 0) { ++ if (config->intr_type == MSI_X) ++ config->rx_ring_num = ++ (no_cpus < S2IO_NUM_CPU_THRESHOLD) ? ++ RTH_MIN_RING_NUM : no_cpus; ++ else ++ config->rx_ring_num = RTH_MIN_RING_NUM; ++ } ++ ++ if (config->rx_ring_num > MAX_RX_RINGS) ++ config->rx_ring_num = MAX_RX_RINGS; ++ ++#ifdef CONFIG_PCI_MSI ++ if ((sp->device_type == XFRAME_II_DEVICE) && ++ (config->intr_type == MSI_X)) { ++ sp->num_entries = config->rx_ring_num + 1; ++ ret = s2io_enable_msi_x(sp); ++ if (!ret) { ++ ret = s2io_test_msi(sp); ++ /* rollback MSI-X, will re-enable during add_isr() */ ++ do_rem_msix_isr(sp); ++ } ++ ++ if (ret) { ++ DBG_PRINT(ERR_DBG, ++ "MSI-X requested but failed to enable\n"); ++ config->intr_type = INTA; ++ } ++ } ++#endif ++ ++ if ((config->intr_type == MSI_X) && ++ (config->rx_steering_type == RTH_STEERING_DEFAULT) && ++ (config->rx_ring_num > RTH_MIN_RING_NUM)) ++ config->rx_steering_type = RTH_STEERING; ++ ++ if (rx_ring_num == 0) { ++ if ( (config->rx_steering_type == RX_VLAN_STEERING) || ++ (config->rx_steering_type == RX_TOS_STEERING)) ++ config->rx_ring_num = MAX_RX_RINGS; ++ } ++ ++ if ((config->rx_steering_type == RX_VLAN_STEERING) && ++ (config->tx_steering_type == TX_VLAN_STEERING)) { ++ config->tx_fifo_num = config->rx_ring_num = ++ (config->tx_fifo_num < config->rx_ring_num ? ++ config->tx_fifo_num : config->rx_ring_num); ++ } + + /* Tx side parameters. */ +- if (config->tx_steering_type == TX_PRIORITY_STEERING) +- config->tx_fifo_num = MAX_TX_FIFOS; +- else +- config->tx_fifo_num = tx_fifo_num; + + /* Initialize the fifos used for tx steering */ + if (config->tx_fifo_num < 5) { +@@ -7861,50 +11358,58 @@ + sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM; + } + +- config->multiq = dev_multiq; + for (i = 0; i < config->tx_fifo_num; i++) { + config->tx_cfg[i].fifo_len = tx_fifo_len[i]; + config->tx_cfg[i].fifo_priority = i; ++ config->tx_bw_percentage[i] = bw_percentage[i]; + } + + /* mapping the QoS priority to the configured fifos */ + for (i = 0; i < MAX_TX_FIFOS; i++) +- config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i]; ++ sp->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i]; + + /* map the hashing selector table to the configured fifos */ + for (i = 0; i < config->tx_fifo_num; i++) + sp->fifo_selector[i] = fifo_selector[i]; + +- + config->tx_intr_type = TXD_INT_TYPE_UTILZ; + for (i = 0; i < config->tx_fifo_num; i++) { +- config->tx_cfg[i].f_no_snoop = +- (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER); + if (config->tx_cfg[i].fifo_len < 65) { + config->tx_intr_type = TXD_INT_TYPE_PER_LIST; + break; + } + } +- /* + 2 because one Txd for skb->data and one Txd for UFO */ +- config->max_txds = MAX_SKB_FRAGS + 2; +- +- /* Rx side parameters. */ +- config->rx_ring_num = rx_ring_num; ++ config->max_txds = MAX_SKB_FRAGS + 1; ++#ifdef NETIF_F_UFO ++ config->max_txds++; ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) ++ /* NAPI doesn't work well with MSI(X) & more than 1 ring*/ ++ if (config->intr_type == MSI_X) ++ if (config->napi) ++ if (config->rx_ring_num > 1) ++ config->napi = 0; ++#endif + for (i = 0; i < config->rx_ring_num; i++) { + config->rx_cfg[i].num_rxd = rx_ring_sz[i] * +- (rxd_count[sp->rxd_mode] + 1); ++ (rxd_count[sp->rxd_mode] + 1); + config->rx_cfg[i].ring_priority = i; ++ config->rx_bw_percentage[i] = bw_percentage[i]; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ atomic_set(&mac_control->rings[i].isr_cnt, 0); ++ atomic_set(&sp->isr_cnt, 0); ++#endif ++ mac_control->rings[i].vlan_strip_flag = sp->vlan_strip_flag; + mac_control->rings[i].rx_bufs_left = 0; ++ mac_control->rings[i].lro = sp->lro; + mac_control->rings[i].rxd_mode = sp->rxd_mode; + mac_control->rings[i].rxd_count = rxd_count[sp->rxd_mode]; + mac_control->rings[i].pdev = sp->pdev; + mac_control->rings[i].dev = sp->dev; +- } +- +- for (i = 0; i < rx_ring_num; i++) { +- config->rx_cfg[i].ring_org = RING_ORG_BUFF1; +- config->rx_cfg[i].f_no_snoop = +- (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER); ++ mac_control->rings[i].config_napi = config->napi; ++ mac_control->rings[i].rx_steering_type = ++ config->rx_steering_type; + } + + /* Setting Mac Control parameters */ +@@ -7912,41 +11417,25 @@ + mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3; + mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7; + +- + /* initialize the shared memory used by the NIC and the host */ +- if (init_shared_mem(sp)) { +- DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", +- dev->name); +- ret = -ENOMEM; +- goto mem_alloc_failed; +- } +- +- sp->bar0 = ioremap(pci_resource_start(pdev, 0), +- pci_resource_len(pdev, 0)); +- if (!sp->bar0) { +- DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n", +- dev->name); +- ret = -ENOMEM; +- goto bar0_remap_failed; +- } +- +- sp->bar1 = ioremap(pci_resource_start(pdev, 2), +- pci_resource_len(pdev, 2)); +- if (!sp->bar1) { +- DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n", +- dev->name); +- ret = -ENOMEM; +- goto bar1_remap_failed; +- } +- +- dev->irq = pdev->irq; +- dev->base_addr = (unsigned long) sp->bar0; ++ ret = init_shared_mem(sp); ++ if (ret != SUCCESS) { ++ DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__); ++ if (ret == -ENOMEM) { ++ DBG_PRINT(ERR_DBG, "Memory allocation failed\n"); ++ goto mem_alloc_failed; ++ } else { ++ DBG_PRINT(ERR_DBG, ++ "Memory allocation configuration invalid\n"); ++ goto configuration_failed; ++ } ++ } + + /* Initializing the BAR1 address as the start of the FIFO pointer. */ +- for (j = 0; j < MAX_TX_FIFOS; j++) { +- mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *) +- (sp->bar1 + (j * 0x00020000)); +- } ++ for (j = 0; j < config->tx_fifo_num; j++) ++ mac_control->tx_FIFO_start[j] = ++ (struct TxFIFO_element __iomem *) ++ (sp->bar1 + (j * 0x00020000)); + + /* Driver entry points */ + dev->open = &s2io_open; +@@ -7957,82 +11446,78 @@ + dev->do_ioctl = &s2io_ioctl; + dev->set_mac_address = &s2io_set_mac_addr; + dev->change_mtu = &s2io_change_mtu; +- SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops); ++#ifdef SET_ETHTOOL_OPS ++ SET_ETHTOOL_OPS(dev, (struct ethtool_ops *)&netdev_ethtool_ops); ++#endif + dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; ++ if ((rx_steering_type == RX_VLAN_STEERING) || ++ (tx_steering_type == TX_VLAN_STEERING)) ++ dev->features |= NETIF_F_HW_VLAN_FILTER; ++ ++#ifdef NETIF_F_LLTX ++ if (sp->device_type != XFRAME_I_DEVICE) ++ dev->features |= NETIF_F_LLTX; ++#endif + dev->vlan_rx_register = s2io_vlan_rx_register; + dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid; +- +- /* +- * will use eth_mac_addr() for dev->set_mac_address +- * mac address will be set every time dev->open() is called +- */ +-#ifdef CONFIG_NET_POLL_CONTROLLER +- dev->poll_controller = s2io_netpoll; +-#endif +- +- dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; +- if (sp->high_dma_flag == TRUE) +- dev->features |= NETIF_F_HIGHDMA; +- dev->features |= NETIF_F_TSO; +- dev->features |= NETIF_F_TSO6; +- if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) { +- dev->features |= NETIF_F_UFO; +- dev->features |= NETIF_F_HW_CSUM; +- } +- dev->tx_timeout = &s2io_tx_watchdog; +- dev->watchdog_timeo = WATCH_DOG_TIMEOUT; +- INIT_WORK(&sp->rst_timer_task, s2io_restart_nic); +- INIT_WORK(&sp->set_link_task, s2io_set_link); +- +- pci_save_state(sp->pdev); +- +- /* Setting swapper control on the NIC, for proper reset operation */ +- if (s2io_set_swapper(sp)) { +- DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n", +- dev->name); +- ret = -EAGAIN; +- goto set_swap_failed; +- } +- +- /* Verify if the Herc works on the slot its placed into */ +- if (sp->device_type & XFRAME_II_DEVICE) { +- mode = s2io_verify_pci_mode(sp); +- if (mode < 0) { +- DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__); +- DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n"); +- ret = -EBADSLT; +- goto set_swap_failed; +- } +- } +- +- if (sp->config.intr_type == MSI_X) { +- sp->num_entries = config->rx_ring_num + 1; +- ret = s2io_enable_msi_x(sp); +- +- if (!ret) { +- ret = s2io_test_msi(sp); +- /* rollback MSI-X, will re-enable during add_isr() */ +- remove_msix_isr(sp); +- } +- if (ret) { +- +- DBG_PRINT(ERR_DBG, +- "%s: MSI-X requested but failed to enable\n", +- dev->name); +- sp->config.intr_type = INTA; +- } +- } +- +- if (config->intr_type == MSI_X) { ++ dev->vlan_rx_add_vid = (void *)s2io_vlan_rx_add_vid; ++#if defined(HAVE_NETDEV_POLL) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) ++ if (config->intr_type == MSI_X) { + for (i = 0; i < config->rx_ring_num ; i++) + netif_napi_add(dev, &mac_control->rings[i].napi, + s2io_poll_msix, 64); +- } else { +- netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64); +- } ++ } else ++ netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64); ++#else ++ dev->poll = s2io_poll; ++ dev->weight = 32; ++#endif ++#endif ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ dev->poll_controller = s2io_netpoll; ++#endif ++ ++ dev->features |= NETIF_F_SG; ++ if (sp->high_dma_flag == TRUE) ++ dev->features |= NETIF_F_HIGHDMA; ++#ifdef NETIF_F_TSO ++ dev->features |= NETIF_F_TSO; ++#endif ++#ifdef NETIF_F_TSO6 ++ dev->features |= NETIF_F_TSO6; ++#endif ++#ifdef NETIF_F_UFO ++ if ((sp->device_type == XFRAME_II_DEVICE) && (ufo)) ++ dev->features |= NETIF_F_UFO; ++#endif ++ if (sp->device_type == XFRAME_II_DEVICE) ++ dev->features |= NETIF_F_HW_CSUM; ++ else ++ dev->features |= NETIF_F_IP_CSUM; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ if (config->tx_steering_type == TX_MULTIQ_STEERING) ++ dev->features |= NETIF_F_MULTI_QUEUE; ++#endif ++#endif ++ dev->tx_timeout = &s2io_tx_watchdog; ++ dev->watchdog_timeo = WATCH_DOG_TIMEOUT; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++ INIT_WORK(&sp->rst_timer_task, ++ (void (*)(void *)) s2io_restart_nic, dev); ++ INIT_WORK(&sp->set_link_task, ++ (void (*)(void *)) s2io_set_link, sp); ++#else ++ INIT_WORK(&sp->rst_timer_task, s2io_restart_nic); ++ INIT_WORK(&sp->set_link_task, s2io_set_link); ++#endif ++ ++ pci_save_state(sp->pdev, sp->config_space); + + /* Not needed for Herc */ +- if (sp->device_type & XFRAME_I_DEVICE) { ++ if (sp->device_type == XFRAME_I_DEVICE) { + /* + * Fix for all "FFs" MAC address problems observed on + * Alpha platforms +@@ -8050,7 +11535,8 @@ + RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET); + writeq(val64, &bar0->rmac_addr_cmd_mem); + wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, +- RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET); ++ RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, ++ S2IO_BIT_RESET); + tmp64 = readq(&bar0->rmac_addr_data0_mem); + mac_down = (u32) tmp64; + mac_up = (u32) (tmp64 >> 32); +@@ -8061,11 +11547,12 @@ + sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24); + sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16); + sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24); +- + /* Set the factory defined MAC address initially */ + dev->addr_len = ETH_ALEN; + memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 14)) + memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN); ++#endif + + /* initialize number of multicast & unicast MAC entries variables */ + if (sp->device_type == XFRAME_I_DEVICE) { +@@ -8081,25 +11568,30 @@ + /* store mac addresses from CAM to s2io_nic structure */ + do_s2io_store_unicast_mc(sp); + +- /* Configure MSIX vector for number of rings configured plus one */ ++#ifdef CONFIG_PCI_MSI + if ((sp->device_type == XFRAME_II_DEVICE) && + (config->intr_type == MSI_X)) + sp->num_entries = config->rx_ring_num + 1; +- +- /* Store the values of the MSIX table in the s2io_nic structure */ +- store_xmsi_data(sp); ++ /* Store the values of the MSIX table in the ++ * s2io_nic structure ++ */ ++ store_xmsi_data(sp); ++#endif ++ + /* reset Nic and bring it to known state */ + s2io_reset(sp); + + /* +- * Initialize link state flags ++ * Initialize the link state flags + * and the card state parameter + */ + sp->state = 0; +- + /* Initialize spinlocks */ +- for (i = 0; i < sp->config.tx_fifo_num; i++) ++ for (i = 0; i < config->tx_fifo_num; i++) { + spin_lock_init(&mac_control->fifos[i].tx_lock); ++ mac_control->fifos[i].intr_type = config->intr_type; ++ mac_control->fifos[i].dev = sp->dev; ++ } + + /* + * SXE-002: Configure link and activity LED to init state +@@ -8115,7 +11607,10 @@ + val64 = readq(&bar0->gpio_control); + } + +- sp->rx_csum = 1; /* Rx chksum verify enabled by default */ ++ sp->rx_csum = 1; /* Rx chksum verify enabled by default */ ++ ++ for (i = 0; i < config->rx_ring_num; i++) ++ mac_control->rings[i].rx_csum = sp->rx_csum; + + if (register_netdev(dev)) { + DBG_PRINT(ERR_DBG, "Device registration failed\n"); +@@ -8123,86 +11618,31 @@ + goto register_failed; + } + s2io_vpd_read(sp); +- DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n"); +- DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name, +- sp->product_name, pdev->revision); ++ DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name, ++ sp->product_name, get_xena_rev_id(sp->pdev)); + DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name, + s2io_driver_version); +- DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %s\n", +- dev->name, print_mac(mac, dev->dev_addr)); ++ DBG_PRINT(ERR_DBG, "%s: MAC ADDR: " ++ "%02x:%02x:%02x:%02x:%02x:%02x, ", dev->name, ++ sp->def_mac_addr[0].mac_addr[0], ++ sp->def_mac_addr[0].mac_addr[1], ++ sp->def_mac_addr[0].mac_addr[2], ++ sp->def_mac_addr[0].mac_addr[3], ++ sp->def_mac_addr[0].mac_addr[4], ++ sp->def_mac_addr[0].mac_addr[5]); + DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num); +- if (sp->device_type & XFRAME_II_DEVICE) { ++ if (sp->device_type == XFRAME_II_DEVICE) { + mode = s2io_print_pci_mode(sp); + if (mode < 0) { + DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n"); + ret = -EBADSLT; +- unregister_netdev(dev); +- goto set_swap_failed; +- } +- } +- switch(sp->rxd_mode) { +- case RXD_MODE_1: +- DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n", +- dev->name); +- break; +- case RXD_MODE_3B: +- DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n", +- dev->name); +- break; +- } +- +- switch (sp->config.napi) { +- case 0: +- DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name); +- break; +- case 1: +- DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name); +- break; +- } +- +- DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name, +- sp->config.tx_fifo_num); +- +- DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name, +- sp->config.rx_ring_num); +- +- switch(sp->config.intr_type) { +- case INTA: +- DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name); +- break; +- case MSI_X: +- DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name); +- break; +- } +- if (sp->config.multiq) { +- for (i = 0; i < sp->config.tx_fifo_num; i++) +- mac_control->fifos[i].multiq = config->multiq; +- DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n", +- dev->name); +- } else +- DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n", +- dev->name); +- +- switch (sp->config.tx_steering_type) { +- case NO_STEERING: +- DBG_PRINT(ERR_DBG, "%s: No steering enabled for" +- " transmit\n", dev->name); +- break; +- case TX_PRIORITY_STEERING: +- DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for" +- " transmit\n", dev->name); +- break; +- case TX_DEFAULT_STEERING: +- DBG_PRINT(ERR_DBG, "%s: Default steering enabled for" +- " transmit\n", dev->name); +- } +- +- if (sp->lro) +- DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n", +- dev->name); +- if (ufo) +- DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)" +- " enabled\n", dev->name); ++ goto check_pci_bus_mode_failed; ++ } ++ } ++ ++ ++ print_static_param_list(dev); ++ + /* Initialize device name */ + sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name); + +@@ -8213,21 +11653,38 @@ + */ + netif_carrier_off(dev); + +- return 0; +- +- register_failed: +- set_swap_failed: ++#ifdef SNMP_SUPPORT ++ s2io_snmp_init(sp); ++#endif ++ ++ return 0; ++ ++check_pci_bus_mode_failed: ++ unregister_netdev(dev); ++ ++register_failed: ++mem_alloc_failed: ++ free_shared_mem(sp); ++ ++configuration_failed: ++set_swap_failed: + iounmap(sp->bar1); +- bar1_remap_failed: ++ ++bar1_remap_failed: + iounmap(sp->bar0); +- bar0_remap_failed: +- mem_alloc_failed: +- free_shared_mem(sp); +- pci_disable_device(pdev); +- pci_release_regions(pdev); ++ ++bar0_remap_failed: + pci_set_drvdata(pdev, NULL); + free_netdev(dev); + ++alloc_etherdev_failed: ++ pci_release_regions(pdev); ++ ++pci_request_regions_failed: ++set_dma_mask_failed: ++ pci_disable_device(pdev); ++ ++enable_device_failed: + return ret; + } + +@@ -8245,23 +11702,38 @@ + struct net_device *dev = + (struct net_device *) pci_get_drvdata(pdev); + struct s2io_nic *sp; ++ int cnt; ++ u64 tmp64; + + if (dev == NULL) { + DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n"); + return; + } + ++ sp = s2io_netdev_priv(dev); ++ ++ /* delete all populated mac entries */ ++ for (cnt = 1; cnt < sp->config.max_mc_addr; cnt++) { ++ tmp64 = do_s2io_read_unicast_mc(sp, cnt); ++ if (tmp64 != S2IO_DISABLE_MAC_ENTRY) ++ do_s2io_delete_unicast_mc(sp, tmp64); ++ } ++ + flush_scheduled_work(); + +- sp = dev->priv; + unregister_netdev(dev); + + free_shared_mem(sp); + iounmap(sp->bar0); + iounmap(sp->bar1); + pci_release_regions(pdev); ++ + pci_set_drvdata(pdev, NULL); ++#ifdef SNMP_SUPPORT ++ s2io_snmp_exit(sp); ++#endif + free_netdev(dev); ++ + pci_disable_device(pdev); + } + +@@ -8273,46 +11745,57 @@ + + static int __init s2io_starter(void) + { ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) ++ lro_enable = lro; ++#endif ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 17)) ++ return pci_module_init(&s2io_driver); ++#else + return pci_register_driver(&s2io_driver); ++#endif + } + + /** + * s2io_closer - Cleanup routine for the driver +- * Description: This function is the cleanup routine for the driver. It unregist * ers the driver. ++ * Description: This function is the cleanup routine for the driver. ++ * It unregisters the driver. + */ + + static __exit void s2io_closer(void) + { + pci_unregister_driver(&s2io_driver); ++ ++ /* Reset the hyper transport interrupts if set on AMD 8132 bridge */ ++ if (intr_type == MSI_X) ++ amd_8132_update_hyper_tx(S2IO_BIT_RESET); ++ + DBG_PRINT(INIT_DBG, "cleanup done\n"); + } + + module_init(s2io_starter); + module_exit(s2io_closer); + ++ + static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip, + struct tcphdr **tcp, struct RxD_t *rxdp, +- struct s2io_nic *sp) ++ struct ring_info *ring, u16 vid) + { + int ip_off; ++ u32 daddr = 0; ++ + u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len; + +- if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) { +- DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n", +- __FUNCTION__); +- return -1; +- } +- +- /* Checking for DIX type or DIX type with VLAN */ +- if ((l2_type == 0) +- || (l2_type == 4)) { ++ if ((l2_type == 0) || /* DIX type */ ++ (l2_type == 4)) { /* DIX type with VLAN */ + ip_off = HEADER_ETHERNET_II_802_3_SIZE; + /* +- * If vlan stripping is disabled and the frame is VLAN tagged, +- * shift the offset by the VLAN header size bytes. +- */ +- if ((!vlan_strip_flag) && +- (rxdp->Control_1 & RXD_FRAME_VLAN_TAG)) ++ * If vlan stripping is disabled and the frame is VLAN tagged, ++ * shift the offset by the VLAN header size bytes. ++ */ ++ if ((ring->vlan_strip_flag == S2IO_DO_NOT_STRIP_VLAN_TAG) && ++ vid) + ip_off += HEADER_VLAN_SIZE; + } else { + /* LLC, SNAP etc are considered non-mergeable */ +@@ -8324,58 +11807,208 @@ + ip_len <<= 2; + *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len); + ++ if (lro_enable == S2IO_DONT_AGGR_FWD_PKTS) { ++ ++ daddr = (*ip)->daddr; ++ /* Check if it is a broadcast or multicast ip */ ++ if (!IN_MULTICAST(daddr) && (INADDR_BROADCAST != daddr)) { ++ struct in_device *in_dev = NULL; ++ struct in_ifaddr *ifa = NULL; ++ /* ++ * Does this packets destined for this interface? ++ */ ++ in_dev = ring->dev->ip_ptr; ++ if (in_dev != NULL) { ++ ifa = in_dev->ifa_list; ++ while (ifa != NULL) { ++ if (daddr == ifa->ifa_local) ++ return 0; ++ ifa = ifa->ifa_next; ++ } ++ } ++ ++ /* Check if it is a vlan packet */ ++ if (ring->vlgrp && vid) { ++ struct net_device *vlan_dev = NULL; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)) ++ struct vlan_dev_info *vlan_info = NULL; ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) ++ vlan_dev = ++ vlan_group_get_device(ring->vlgrp, vid); ++#else ++ vlan_dev = ring->vlgrp->vlan_devices[vid]; ++#endif ++ if (!vlan_dev) ++ goto donot_aggr; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)) ++ vlan_info = ++ (struct vlan_dev_info *) ++ s2io_netdev_priv(vlan_dev); ++ if (!vlan_info) ++ goto donot_aggr; ++ ++ /* Is this a registered vlan? */ ++ if (vlan_info->real_dev == ring->dev) ++#else ++ if (vlan_dev_real_dev(vlan_dev) == ring->dev) ++#endif ++ return 0; ++ } ++ ++donot_aggr: ++ /* Packet is to be forwarded. Don't aggregate */ ++ return -1; ++ } ++ } ++ + return 0; + } + + static int check_for_socket_match(struct lro *lro, struct iphdr *ip, + struct tcphdr *tcp) + { +- DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__); ++ DBG_PRINT(INFO_DBG, "%s: Been here...\n", __FUNCTION__); + if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) || +- (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest)) ++ (lro->tcph->source != tcp->source) || ++ (lro->tcph->dest != tcp->dest)) + return -1; + return 0; + } + ++#define S2IO_TS_SAVE 2 ++#define S2IO_TS_VERIFY 1 ++#define S2IO_TS_UPDATE 0 ++ ++static int update_tcp_timestamp_slow(struct tcphdr *th, struct lro *lro, int save) ++{ ++ unsigned char *ptr; ++ int opt_cnt = 0; ++ int length = (th->doff*4) - sizeof(struct tcphdr); ++ ++ ptr = (unsigned char *)(th + 1); ++ ++ while (length > 0) { ++ int opcode=*ptr++; ++ int opsize; ++ ++ switch (opcode) { ++ case TCPOPT_EOL: ++ return 1; ++ case TCPOPT_NOP: ++ length--; ++ continue; ++ default: ++ /* Not sure about this check, but not taking a chance ... */ ++ if ((opcode == TCPOPT_SACK_PERM) || (opcode == TCPOPT_SACK)) ++ return 1; ++ opsize=*ptr++; ++ if (opsize < 2) ++ return 1; ++ /* don't parse partial options */ ++ if (opsize > length) ++ return 1; ++ if (++opt_cnt > 3) ++ return 1; ++ if (opcode == TCPOPT_TIMESTAMP) { ++ if (opsize==TCPOLEN_TIMESTAMP) { ++ ++ if (save == S2IO_TS_SAVE){ ++ lro->cur_tsval = ntohl(* (__be32 *)ptr); ++ lro->cur_tsecr = *(__be32 *)(ptr + 4); ++ } ++ else if (save == S2IO_TS_VERIFY){ ++ /* Ensure timestamp value increases monotonically */ ++ if (lro->cur_tsval > ntohl(*((__be32 *)ptr))) ++ return -1; ++ /* timestamp echo reply should be non-zero */ ++ if (*((__be32 *)(ptr + 4)) == 0) ++ return -1; ++ } ++ else { ++ __be32 *tmp_ptr = (__be32 *)(ptr + 4); ++ *tmp_ptr = lro->cur_tsecr; ++ } ++ return 0; ++ } ++ } ++ ptr+=opsize-2; ++ length-=opsize; ++ } ++ } ++ return 1; ++} ++ ++static int update_tcp_timestamp(struct tcphdr *th, struct lro *lro, int save) ++{ ++ if (th->doff == sizeof(struct tcphdr)>>2) { ++ return 1; ++ } else if (th->doff == (sizeof(struct tcphdr)>>2) ++ +(TCPOLEN_TSTAMP_ALIGNED>>2)) { ++ __be32 *ptr = (__be32 *)(th + 1); ++ if (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) ++ | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) { ++ ++ ++ptr; ++ if (save == S2IO_TS_SAVE){ ++ lro->cur_tsval = ntohl(*(__be32 *)ptr); ++ lro->cur_tsecr = *(__be32 *)(ptr + 1); ++ } ++ else if (save == S2IO_TS_VERIFY){ ++ /* Ensure timestamp value increases monotonically */ ++ if (lro->cur_tsval > ntohl(*((__be32 *)ptr))) ++ return -1; ++ ++ /* timestamp echo reply should be non-zero */ ++ if (*((__be32 *)(ptr + 1)) == 0) ++ return -1; ++ } ++ else ++ *(ptr + 1) = lro->cur_tsecr; ++ ++ return 0; ++ } ++ } ++ return (update_tcp_timestamp_slow(th, lro, save)); ++} ++ + static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp) + { + return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2)); + } + +-static void initiate_new_session(struct lro *lro, u8 *l2h, +- struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag) +-{ +- DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__); +- lro->l2h = l2h; ++static void initiate_new_session(struct lro *lro, ++ struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len) ++{ ++ DBG_PRINT(INFO_DBG, "%s: Been here...\n", __FUNCTION__); + lro->iph = ip; + lro->tcph = tcp; + lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq); + lro->tcp_ack = tcp->ack_seq; ++ lro->window = tcp->window; + lro->sg_num = 1; + lro->total_len = ntohs(ip->tot_len); + lro->frags_len = 0; +- lro->vlan_tag = vlan_tag; ++ + /* + * check if we saw TCP timestamp. Other consistency checks have + * already been done. +- */ +- if (tcp->doff == 8) { +- __be32 *ptr; +- ptr = (__be32 *)(tcp+1); ++ */ ++ if (!update_tcp_timestamp(tcp, lro, S2IO_TS_SAVE)) + lro->saw_ts = 1; +- lro->cur_tsval = ntohl(*(ptr+1)); +- lro->cur_tsecr = *(ptr+2); +- } ++ + lro->in_use = 1; + } + +-static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro) ++static void update_L3L4_header(struct ring_info *ring, struct lro *lro, ++int ring_no) + { + struct iphdr *ip = lro->iph; + struct tcphdr *tcp = lro->tcph; +- __sum16 nchk; +- struct stat_block *statinfo = sp->mac_control.stats_info; +- DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__); ++ u16 nchk; ++ ++ DBG_PRINT(INFO_DBG, "%s: Been here...\n", __FUNCTION__); + + /* Update L3 header */ + ip->tot_len = htons(lro->total_len); +@@ -8388,22 +12021,20 @@ + tcp->window = lro->window; + + /* Update tsecr field if this session has timestamps enabled */ +- if (lro->saw_ts) { +- __be32 *ptr = (__be32 *)(tcp + 1); +- *(ptr+2) = lro->cur_tsecr; +- } ++ if (lro->saw_ts) ++ update_tcp_timestamp(tcp, lro, S2IO_TS_UPDATE); + + /* Update counters required for calculation of + * average no. of packets aggregated. + */ +- statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num; +- statinfo->sw_stat.num_aggregations++; ++ ring->rx_ring_stat->sw_lro_stat.sum_avg_pkts_aggregated += lro->sg_num; ++ ring->rx_ring_stat->sw_lro_stat.num_aggregations++; + } + + static void aggregate_new_rx(struct lro *lro, struct iphdr *ip, + struct tcphdr *tcp, u32 l4_pyld) + { +- DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__); ++ DBG_PRINT(INFO_DBG, "%s: Been here...\n", __FUNCTION__); + lro->total_len += l4_pyld; + lro->frags_len += l4_pyld; + lro->tcp_next_seq += l4_pyld; +@@ -8413,35 +12044,38 @@ + lro->tcp_ack = tcp->ack_seq; + lro->window = tcp->window; + +- if (lro->saw_ts) { +- __be32 *ptr; +- /* Update tsecr and tsval from this packet */ +- ptr = (__be32 *)(tcp+1); +- lro->cur_tsval = ntohl(*(ptr+1)); +- lro->cur_tsecr = *(ptr + 2); +- } ++ if (lro->saw_ts) ++ update_tcp_timestamp(tcp, lro, S2IO_TS_SAVE); + } + + static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip, +- struct tcphdr *tcp, u32 tcp_pyld_len) +-{ +- u8 *ptr; +- +- DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__); +- +- if (!tcp_pyld_len) { ++ struct tcphdr *tcp, u32 tcp_pyld_len, u8 agg_ack) ++{ ++ DBG_PRINT(INFO_DBG, "%s: Been here...\n", __FUNCTION__); ++ ++ if (!agg_ack && !tcp_pyld_len) { + /* Runt frame or a pure ack */ + return -1; + } + +- if (ip->ihl != 5) /* IP has options */ ++ /* Ensure there are no IP options */ ++ if ((ip->ihl << 2) != sizeof(*ip)) + return -1; + ++ /* IP packet is not fragmented */ ++ if (ip->frag_off & htons(IP_MF|IP_OFFSET)) ++ return -1; ++ ++ /* ++ * TODO: Currently works with normal ECN. No support for ++ * ECN with nonces(RFC3540). ++ */ + /* If we see CE codepoint in IP header, packet is not mergeable */ + if (INET_ECN_is_ce(ipv4_get_dsfield(ip))) + return -1; + + /* If we see ECE or CWR flags in TCP header, packet is not mergeable */ ++ + if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin || + tcp->ece || tcp->cwr || !tcp->ack) { + /* +@@ -8452,55 +12086,34 @@ + return -1; + } + +- /* +- * Allow only one TCP timestamp option. Don't aggregate if +- * any other options are detected. +- */ +- if (tcp->doff != 5 && tcp->doff != 8) +- return -1; +- +- if (tcp->doff == 8) { +- ptr = (u8 *)(tcp + 1); +- while (*ptr == TCPOPT_NOP) +- ptr++; +- if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP) ++ if (l_lro) ++ if (update_tcp_timestamp(tcp, l_lro, S2IO_TS_VERIFY) == -1) + return -1; + +- /* Ensure timestamp value increases monotonically */ +- if (l_lro) +- if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2)))) +- return -1; +- +- /* timestamp echo reply should be non-zero */ +- if (*((__be32 *)(ptr+6)) == 0) +- return -1; +- } +- + return 0; + } + + static int +-s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, u8 **tcp, +- u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp, +- struct s2io_nic *sp) ++s2io_club_tcp_session(struct ring_info *ring, u8 *buffer, u8 **tcp, ++ u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp, u16 vid) + { + struct iphdr *ip; + struct tcphdr *tcph; + int ret = 0, i; +- u16 vlan_tag = 0; ++ struct swLROStat *lro_stats = &ring->rx_ring_stat->sw_lro_stat; + + if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp, +- rxdp, sp))) { ++ rxdp, ring, vid))) { + DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n", + ip->saddr, ip->daddr); + } else + return ret; + +- vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2); + tcph = (struct tcphdr *)*tcp; + *tcp_len = get_l4_pyld_length(ip, tcph); ++ + for (i=0; ilro0_n[i]; ++ struct lro *l_lro = &ring->lro0_n[i]; + if (l_lro->in_use) { + if (check_for_socket_match(l_lro, ip, tcph)) + continue; +@@ -8508,21 +12121,23 @@ + *lro = l_lro; + + if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) { +- DBG_PRINT(INFO_DBG, "%s:Out of order. expected " +- "0x%x, actual 0x%x\n", __FUNCTION__, +- (*lro)->tcp_next_seq, +- ntohl(tcph->seq)); +- +- sp->mac_control.stats_info-> +- sw_stat.outof_sequence_pkts++; +- ret = 2; +- break; +- } +- +- if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len)) +- ret = 1; /* Aggregate */ ++ DBG_PRINT(INFO_DBG, ++ "%s:Out of order. expected " ++ "0x%x, actual 0x%x\n", __FUNCTION__, ++ (*lro)->tcp_next_seq, ++ ntohl(tcph->seq)); ++ ++ lro_stats->outof_sequence_pkts++; ++ ret = LRO_FLUSH_BOTH; ++ break; ++ } ++ ++ if (!verify_l3_l4_lro_capable(l_lro, ip, tcph, ++ *tcp_len, ring->aggr_ack)) ++ ret = LRO_AGGR_PACKET; /* Aggregate */ + else +- ret = 2; /* Flush both */ ++ ret = LRO_FLUSH_BOTH; /* Flush both */ ++ + break; + } + } +@@ -8533,15 +12148,15 @@ + * don't create new LRO session. Just send this + * packet up. + */ +- if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) { ++ if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len, ++ ring->aggr_ack)) + return 5; +- } + + for (i=0; ilro0_n[i]; ++ struct lro *l_lro = &ring->lro0_n[i]; + if (!(l_lro->in_use)) { + *lro = l_lro; +- ret = 3; /* Begin anew */ ++ ret = LRO_BEG_AGGR; /* Begin anew */ + break; + } + } +@@ -8554,90 +12169,98 @@ + return ret; + } + +- switch (ret) { +- case 3: +- initiate_new_session(*lro, buffer, ip, tcph, *tcp_len, +- vlan_tag); +- break; +- case 2: +- update_L3L4_header(sp, *lro); +- break; +- case 1: +- aggregate_new_rx(*lro, ip, tcph, *tcp_len); +- if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) { +- update_L3L4_header(sp, *lro); +- ret = 4; /* Flush the LRO */ +- } +- break; +- default: +- DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n", +- __FUNCTION__); +- break; +- } +- +- return ret; +-} +- +-static void clear_lro_session(struct lro *lro) +-{ +- static u16 lro_struct_size = sizeof(struct lro); +- +- memset(lro, 0, lro_struct_size); +-} +- +-static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag) +-{ +- struct net_device *dev = skb->dev; +- struct s2io_nic *sp = dev->priv; +- +- skb->protocol = eth_type_trans(skb, dev); +- if (sp->vlgrp && vlan_tag +- && (vlan_strip_flag)) { +- /* Queueing the vlan frame to the upper layer */ +- if (sp->config.napi) +- vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag); +- else +- vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag); +- } else { +- if (sp->config.napi) +- netif_receive_skb(skb); +- else +- netif_rx(skb); +- } +-} +- +-static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro, +- struct sk_buff *skb, +- u32 tcp_len) ++ if (LRO_AGGR_PACKET == ret) { ++ aggregate_new_rx(*lro, ip, tcph, *tcp_len); ++ if ((*lro)->sg_num == ring->lro_max_aggr_per_sess) { ++ update_L3L4_header(ring, *lro, ring->ring_no); ++ ret = LRO_FLUSH_SESSION; /* Flush the LRO */ ++ } ++ } else if (LRO_BEG_AGGR == ret) ++ initiate_new_session(*lro, ip, tcph, *tcp_len); ++ else if (LRO_FLUSH_BOTH == ret) ++ update_L3L4_header(ring, *lro, ring->ring_no); ++ else ++ DBG_PRINT(ERR_DBG, "%s:LRO Unhandled.\n", __FUNCTION__); ++ ++ return ret; ++} ++ ++static void lro_append_pkt(struct ring_info *ring, struct lro *lro, ++ struct sk_buff *skb, u32 tcp_len, u8 aggr_ack) + { + struct sk_buff *first = lro->parent; ++ struct sk_buff *frag_list = NULL; ++ struct sk_buff *data_skb = NULL; ++ int data_skb_true_size = 0; ++ struct swLROStat *lro_stats = &ring->rx_ring_stat->sw_lro_stat; + + first->len += tcp_len; + first->data_len = lro->frags_len; +- skb_pull(skb, (skb->len - tcp_len)); +- if (skb_shinfo(first)->frag_list) +- lro->last_frag->next = skb; +- else ++ lro_stats->clubbed_frms_cnt++; ++ ++ if (aggr_ack && (tcp_len == 0)) { ++ dev_kfree_skb_any(skb); ++ return; ++ } ++ ++ if (ring->rxd_mode == RXD_MODE_5) { ++ /* leave the Buf2 which contains l3l4 header */ ++ data_skb = skb_shinfo(skb)->frag_list; ++ data_skb_true_size = data_skb->truesize; ++ skb_shinfo(skb)->frag_list = NULL; ++ skb->data_len = 0; ++ skb->len = skb->len - tcp_len; ++ /* calcualate the size of the skbs containg only data*/ ++ for (frag_list = data_skb; frag_list->next; ++ frag_list = frag_list->next) ++ data_skb_true_size += frag_list->truesize; ++ ++ /* single header skb with truesize*/ ++ skb->truesize -= data_skb_true_size; ++ /* Free the SKB containing the l3l4 header*/ ++ dev_kfree_skb(skb); ++ /* skb will now point to the actual l3l4 data*/ ++ skb = data_skb; ++ skb->truesize = data_skb_true_size; ++ } else ++ skb_pull(skb, (skb->len - tcp_len)); ++ ++ frag_list = skb_shinfo(first)->frag_list; ++ if (frag_list) { ++ if (lro->last_frag) /* valid only in 5 buffer mode */ ++ lro->last_frag->next = skb; ++ } else + skb_shinfo(first)->frag_list = skb; +- first->truesize += skb->truesize; +- lro->last_frag = skb; +- sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++; ++ ++ first->truesize += skb->truesize; /*updating skb->truesize */ ++ ++ if (ring->rxd_mode == RXD_MODE_5) { ++ frag_list = data_skb; ++ if (frag_list) { ++ /* Traverse to the end of the list*/ ++ for (; frag_list->next; frag_list = frag_list->next); ++ } ++ lro->last_frag = frag_list; ++ } else ++ lro->last_frag = skb; ++ + return; + } + +-/** +- * s2io_io_error_detected - called when PCI error is detected +- * @pdev: Pointer to PCI device +- * @state: The current pci connection state +- * +- * This function is called after a PCI bus error affecting +- * this device has been detected. +- */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) ++/* ++* s2io_io_error_detected - called when PCI error is detected ++* @pdev: Pointer to PCI device ++* @state: The current pci connection state ++* ++* This function is called after a PCI bus error affecting ++* this device has been detected. ++*/ + static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev, +- pci_channel_state_t state) ++ pci_channel_state_t state) + { + struct net_device *netdev = pci_get_drvdata(pdev); +- struct s2io_nic *sp = netdev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(netdev); + + netif_device_detach(netdev); + +@@ -8650,23 +12273,23 @@ + return PCI_ERS_RESULT_NEED_RESET; + } + +-/** +- * s2io_io_slot_reset - called after the pci bus has been reset. +- * @pdev: Pointer to PCI device +- * +- * Restart the card from scratch, as if from a cold-boot. +- * At this point, the card has exprienced a hard reset, +- * followed by fixups by BIOS, and has its config space +- * set up identically to what it was at cold boot. +- */ ++/* ++* s2io_io_slot_reset - called after the pci bus has been reset. ++* @pdev: Pointer to PCI device ++* ++* Restart the card from scratch, as if from a cold-boot. ++* At this point, the card has exprienced a hard reset, ++* followed by fixups by BIOS, and has its config space ++* set up identically to what it was at cold boot. ++*/ + static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev) + { + struct net_device *netdev = pci_get_drvdata(pdev); +- struct s2io_nic *sp = netdev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(netdev); + + if (pci_enable_device(pdev)) { + printk(KERN_ERR "s2io: " +- "Cannot re-enable PCI device after reset.\n"); ++ "Cannot re-enable PCI device after reset.\n"); + return PCI_ERS_RESULT_DISCONNECT; + } + +@@ -8676,33 +12299,1906 @@ + return PCI_ERS_RESULT_RECOVERED; + } + +-/** +- * s2io_io_resume - called when traffic can start flowing again. +- * @pdev: Pointer to PCI device +- * +- * This callback is called when the error recovery driver tells +- * us that its OK to resume normal operation. +- */ ++/* ++* s2io_io_resume - called when traffic can start flowing again. ++* @pdev: Pointer to PCI device ++* ++* This callback is called when the error recovery driver tells ++* us that its OK to resume normal operation. ++*/ + static void s2io_io_resume(struct pci_dev *pdev) + { + struct net_device *netdev = pci_get_drvdata(pdev); +- struct s2io_nic *sp = netdev->priv; ++ struct s2io_nic *sp = s2io_netdev_priv(netdev); + + if (netif_running(netdev)) { + if (s2io_card_up(sp)) { + printk(KERN_ERR "s2io: " +- "Can't bring device back up after reset.\n"); ++ "Can't bring device back up after reset.\n"); + return; + } + + if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) { + s2io_card_down(sp); + printk(KERN_ERR "s2io: " +- "Can't resetore mac addr after reset.\n"); ++ "Can't resetore mac addr after reset.\n"); + return; + } + } + + netif_device_attach(netdev); +- netif_tx_wake_all_queues(netdev); +-} ++} ++#endif ++ ++/* Following code not present in kernel release */ ++ ++int s2io_ioctl_util(struct s2io_nic *sp, struct ifreq *rq, int cmd) ++{ ++ int ret; ++ u8 mac_addr[6]; ++ switch (cmd) { ++ /* Private IOCTLs used by the util tool. */ ++ case SIOCDEVPRIVATE + 4: ++ { ++ struct ioctlInfo *io = (struct ioctlInfo *) rq->ifr_data; ++ struct config_param *config = &sp->config; ++ int i, j; ++ int lst_size = config->max_txds * sizeof(struct TxD); ++ void *to_buf = io->buffer, *fr_buf; ++ io->size = 0; ++ ++ DBG_PRINT(INFO_DBG, "Tx get_offset %d, " ++ "put_offset %d \n", ++ sp->mac_control.fifos[0]. ++ tx_curr_get_info.offset, ++ sp->mac_control.fifos[0]. ++ tx_curr_put_info.offset); ++ ++ for (i = 0; i < config->tx_fifo_num; i++) { ++ int fifo_len = config->tx_cfg[i].fifo_len; ++ io->size += fifo_len; ++ for (j = 0; j < fifo_len; j++) { ++ fr_buf = sp->mac_control.fifos[i]. ++ list_info[j]. ++ list_virt_addr; ++ ret = copy_to_user(to_buf, ++ fr_buf, ++ lst_size); ++ if (ret) ++ return -EFAULT; ++ to_buf += lst_size; ++ } ++ } ++ io->size *= lst_size; ++ break; ++ } ++ ++ case SIOCDEVPRIVATE + 5: ++ { ++ struct ioctlInfo *io = (struct ioctlInfo *) rq->ifr_data; ++ int i, j, row_sz; ++ ++ io->size = sp->mac_control.stats_mem_sz; ++ s2io_updt_stats(sp); ++ ++ row_sz = (io->size + 15)/16; ++ DBG_PRINT(INFO_DBG, "Stats Dump:\n"); ++ for (i = 0; i < row_sz; i++) { ++ DBG_PRINT(INFO_DBG, "%03x: ", (i*16)); ++ for (j = 0; j < 16; j++) { ++ u8 *x = (u8 *) ++ (sp->mac_control.stats_mem + (i*16)+j); ++ if (j == 8) ++ DBG_PRINT(INFO_DBG, " "); ++ DBG_PRINT(INFO_DBG, "%02x ", *x); ++ if (((i*16)+j) == io->size-1) ++ goto end; ++ } ++ DBG_PRINT(INFO_DBG, "\n"); ++ } ++end: ++ DBG_PRINT(INFO_DBG, "\n"); ++ ++ ret = copy_to_user((void *)io->buffer, ++ (void *)sp->mac_control.stats_mem, ++ io->size); ++ if (ret) ++ return -EFAULT; ++ break; ++ } ++ ++ case SIOCDEVPRIVATE + 7: ++ { ++ unsigned int i = 0, j = 0; ++ struct ioctlInfo *io = (struct ioctlInfo *) rq->ifr_data; ++ ++ DBG_PRINT(INFO_DBG, "Rx get_offset %d, " ++ "put_offset %d \n", ++ sp->mac_control.rings[0]. ++ rx_curr_get_info.offset, ++ sp->mac_control.rings[0]. ++ rx_curr_put_info.offset); ++ ++ io->size = 4096 * rx_ring_sz[0]; ++ while (i < sp->config.rx_cfg[0].num_rxd) { ++ char *c = ++ (char *) sp->mac_control.rings[0]. ++ rx_blocks[j].block_virt_addr; ++ ret = copy_to_user( ++ (io->buffer + (j * 4096)), ++ c, 4096); ++ if (ret) ++ return -EFAULT; ++ i += (MAX_RXDS_PER_BLOCK_1 + 1); ++ j++; ++ } ++ break; ++ } ++ ++ case SIOCDEVPRIVATE + 8: ++ { ++ struct spdm_cfg *io = (struct spdm_cfg *)rq->ifr_data; ++ spdm_data_processor(io, sp); ++ break; ++ } ++ ++ case SIOCDEVPRIVATE + 9: ++ { ++ struct ioctlInfo *io = (struct ioctlInfo *) rq->ifr_data; ++ u64 val64; ++ if (!is_s2io_card_up(sp)) { ++ DBG_PRINT(ERR_DBG, ++ "%s: Device is down!!\n", __FUNCTION__); ++ break; ++ } ++ ++ val64 = readq((sp->bar0 + io->offset)); ++ io->value = val64; ++ break; ++ } ++ ++ case SIOCDEVPRIVATE + 10: ++ { ++ struct ioctlInfo *io = (struct ioctlInfo *) rq->ifr_data; ++ writeq(io->value, (sp->bar0 + io->offset)); ++ break; ++ } ++ ++ case SIOCDEVPRIVATE + 11: ++ { ++ struct ioctlInfo *io = (struct ioctlInfo *) rq->ifr_data; ++ sp->exec_mode = io->value; ++ break; ++ } ++ ++ case SIOCDEVPRIVATE + 12: ++ { ++ struct ioctlInfo *io = (struct ioctlInfo *) rq->ifr_data; ++ mac_addr[5] = (u8) (io->value); ++ mac_addr[4] = (u8) (io->value >> 8); ++ mac_addr[3] = (u8) (io->value >> 16); ++ mac_addr[2] = (u8) (io->value >> 24); ++ mac_addr[1] = (u8) (io->value >> 32); ++ mac_addr[0] = (u8) (io->value >> 40); ++ do_s2io_prog_unicast(sp->dev, mac_addr); ++ break; ++ } ++ ++ case SIOCDEVPRIVATE + 13: ++ { ++ struct ioctlInfo *io = (struct ioctlInfo *) rq->ifr_data; ++ mac_addr[5] = (u8) (io->value); ++ mac_addr[4] = (u8) (io->value >> 8); ++ mac_addr[3] = (u8) (io->value >> 16); ++ mac_addr[2] = (u8) (io->value >> 24); ++ mac_addr[1] = (u8) (io->value >> 32); ++ mac_addr[0] = (u8) (io->value >> 40); ++ do_s2io_add_mc(sp, mac_addr); ++ break; ++ } ++ ++ case SIOCDEVPRIVATE + 14: ++ { ++ struct ioctlInfo *io = (struct ioctlInfo *) rq->ifr_data; ++ do_s2io_delete_unicast_mc(sp, io->value); ++ break; ++ } ++ ++ case SIOCDEVPRIVATE + 15: ++ { ++ struct ioctlInfo *io = (struct ioctlInfo *) rq->ifr_data; ++ io->value = do_s2io_read_unicast_mc(sp, io->offset); ++ break; ++ } ++ ++ case SIOCDEVPRIVATE + 3: ++ { ++ general_info(sp, rq); ++ break; ++ } ++ ++ default: ++ return -EOPNOTSUPP; ++ } ++ return SUCCESS; ++} ++ ++/*General Info*/ ++void general_info(struct s2io_nic *sp, struct ifreq *rq) ++{ ++ struct net_device *dev = sp->dev; ++ struct ioctlInfo *io = (struct ioctlInfo *) rq->ifr_data; ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ register u64 val64 = 0; ++ int mode, i; ++ u16 pci_cmd; ++ u8 data; ++ ++ /*Get current values of per ring msix interrupt counter*/ ++ for (i = 0; i < 8; i++) { ++ if (i < sp->config.rx_ring_num) ++ io->ginfo.rx_msix_intr_cnt[i] = ++ sp->mac_control.rings[i].rx_ring_stat->rx_msix_cnt; ++ else ++ io->ginfo.rx_msix_intr_cnt[i] = 0; ++ } ++ io->ginfo.tx_intr_cnt = sp->tx_intr_cnt; ++ io->ginfo.rx_intr_cnt = sp->rx_inta_cnt; ++ io->ginfo.deviceid = sp->pdev->device; ++ io->ginfo.vendorid = PCI_VENDOR_ID_S2IO; ++ strcpy(io->ginfo.driver_version, s2io_driver_version); ++ io->ginfo.intr_type = sp->config.intr_type; ++ io->ginfo.tx_fifo_num = sp->config.tx_fifo_num; ++ io->ginfo.rx_ring_num = sp->config.rx_ring_num; ++ io->ginfo.rxd_mode = sp->rxd_mode; ++ io->ginfo.lro = sp->lro; ++ io->ginfo.lro_max_pkts = sp->lro_max_aggr_per_sess; ++ io->ginfo.napi = sp->config.napi; ++ io->ginfo.rx_steering_type = sp->config.rx_steering_type; ++ io->ginfo.rth_mask = rth_mask; ++ io->ginfo.vlan_tag_strip = sp->config.vlan_tag_strip; ++ io->ginfo.device_type = sp->device_type; ++ io->ginfo.mtu = dev->mtu; ++ pci_read_config_byte(sp->pdev, PCI_LATENCY_TIMER, &data); ++ io->ginfo.latency_timer = data; ++ io->ginfo.rx_csum = sp->rx_csum; ++ if (sp->device_type == XFRAME_II_DEVICE) ++ io->ginfo.tx_csum = ((dev->features & NETIF_F_HW_CSUM)? 1: 0); ++ else ++ io->ginfo.tx_csum = ((dev->features & NETIF_F_IP_CSUM)? 1: 0); ++ ++ io->ginfo.sg = ((dev->features & NETIF_F_SG)?1:0); ++ io->ginfo.perm_addr = do_s2io_read_unicast_mc(sp, 0); ++ ++ pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd)); ++ io->ginfo.pcix_cmd = pci_cmd; ++ io->ginfo.tx_urng = readq(&bar0->tti_data1_mem); ++ io->ginfo.rx_urng = readq(&bar0->rti_data1_mem); ++ io->ginfo.tx_ufc = readq(&bar0->tti_data2_mem); ++ io->ginfo.rx_ufc = readq(&bar0->rti_data2_mem); ++#ifndef NETIF_F_UFO ++ io->ginfo.ufo = 0; ++#else ++ io->ginfo.ufo = 0; ++ if ((sp->device_type == XFRAME_II_DEVICE) && ufo) ++ io->ginfo.ufo = 1; ++#endif ++#ifndef NETIF_F_TSO ++ io->ginfo.tso = 0; ++#else ++ io->ginfo.tso = 1; ++#endif ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ io->ginfo.fifo_len[i] = sp->config.tx_cfg[i].fifo_len; ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ io->ginfo.rx_ring_size[i] = rx_ring_sz[i]; ++ ++ io->ginfo.rth_bucket_size = ((sp->config.rx_ring_num + 1)/2); ++ val64 = readq(&bar0->pci_mode); ++ mode = (u8)GET_PCI_MODE(val64); ++ if (val64 & PCI_MODE_UNKNOWN_MODE) ++ strcpy(io->ginfo.pci_type, "Unknown PCI mode"); ++ if (s2io_on_nec_bridge(sp->pdev)) ++ strcpy(io->ginfo.pci_type, "PCI-E bus"); ++ ++ switch (mode) { ++ case PCI_MODE_PCI_33: ++ strcpy(io->ginfo.pci_type, "33MHz PCI bus"); ++ break; ++ case PCI_MODE_PCI_66: ++ strcpy(io->ginfo.pci_type, "66MHz PCI bus"); ++ break; ++ case PCI_MODE_PCIX_M1_66: ++ strcpy(io->ginfo.pci_type, "66MHz PCIX(M1) bus"); ++ break; ++ case PCI_MODE_PCIX_M1_100: ++ strcpy(io->ginfo.pci_type, "100MHz PCIX(M1) bus"); ++ break; ++ case PCI_MODE_PCIX_M1_133: ++ strcpy(io->ginfo.pci_type, "133MHz PCIX(M1) bus"); ++ break; ++ case PCI_MODE_PCIX_M2_66: ++ strcpy(io->ginfo.pci_type, "133MHz PCIX(M2) bus"); ++ break; ++ case PCI_MODE_PCIX_M2_100: ++ strcpy(io->ginfo.pci_type, "200MHz PCIX(M2) bus"); ++ break; ++ case PCI_MODE_PCIX_M2_133: ++ strcpy(io->ginfo.pci_type, "266MHz PCIX(M2) bus"); ++ break; ++ default: ++ strcpy(io->ginfo.pci_type, "Unsupported bus speed"); ++ } ++ ++ if (sp->config.rx_steering_type == RTH_STEERING ++ || sp->config.rx_steering_type == RTH_STEERING_DEFAULT) { ++ val64 = readq(&bar0->rts_rth_cfg); ++ ++ switch (rth_protocol) { ++ case 1: ++ if (val64 & RTS_RTH_TCP_IPV4_EN) ++ strcpy(io->ginfo.rth_steering_mask, ++ "RTS_RTH_TCP_IPV4_EN"); ++ break; ++ case 2: ++ if (val64 & RTS_RTH_UDP_IPV4_EN) ++ strcpy(io->ginfo.rth_steering_mask, ++ "RTS_RTH_UDP_IPV4_EN"); ++ break; ++ case 3: ++ if (val64 & RTS_RTH_IPV4_EN) ++ strcpy(io->ginfo.rth_steering_mask, ++ "RTS_RTH_IPV4_EN"); ++ break; ++ case 4: ++ if (val64 & RTS_RTH_TCP_IPV6_EN) ++ strcpy(io->ginfo.rth_steering_mask, ++ "RTS_RTH_TCP_IPV6_EN"); ++ break; ++ case 5: ++ if (val64 & RTS_RTH_UDP_IPV6_EN) ++ strcpy(io->ginfo.rth_steering_mask, ++ "RTS_RTH_UDP_IPV6_EN"); ++ break; ++ case 6: ++ if (val64 & RTS_RTH_IPV6_EN) ++ strcpy(io->ginfo.rth_steering_mask, ++ "RTS_RTH_IPV6_EN"); ++ break; ++ case 7: ++ if (val64 & RTS_RTH_TCP_IPV6_EX_EN) ++ strcpy(io->ginfo.rth_steering_mask, ++ "RTS_RTH_TCP_IPV6_EX_EN"); ++ break; ++ case 8: ++ if (val64 & RTS_RTH_UDP_IPV6_EX_EN) ++ strcpy(io->ginfo.rth_steering_mask, ++ "RTS_RTH_UDP_IPV6_EX_EN"); ++ break; ++ case 9: ++ if (val64 & RTS_RTH_IPV6_EX_EN) ++ strcpy(io->ginfo.rth_steering_mask, ++ "RTS_RTH_IPV6_EX_EN"); ++ break; ++ default: ++ if (val64 & RTS_RTH_TCP_IPV4_EN) ++ strcpy(io->ginfo.rth_steering_mask, ++ "RTS_RTH_TCP_IPV4_EN"); ++ } ++ } ++} ++ ++/* ++ * spdm_extract_table - ++ */ ++static int spdm_extract_table(void *data, struct s2io_nic *nic) ++{ ++ struct XENA_dev_config __iomem *bar0 = nic->bar0; ++ u64 val64, table_content; ++ int line, entry = 0; ++ ++ while (entry < nic->spdm_entry) { ++ u64 *tmp = (u64 *)((u8 *)data + (0x40 * entry)); ++ for (line = 0; line < 8; line++, tmp++) { ++ val64 = RTS_RTH_SPDM_MEM_CTRL_OFFSET(entry) | ++ RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(line) | ++ RTS_RTH_SPDM_MEM_CTRL_STROBE; ++ writeq(val64, &bar0->rts_rth_spdm_mem_ctrl); ++ if (wait_for_cmd_complete(&bar0->rts_rth_spdm_mem_ctrl, ++ RTS_RTH_SPDM_MEM_CTRL_STROBE, ++ S2IO_BIT_RESET) == FAILURE) ++ return FAILURE; ++ table_content = readq(&bar0->rts_rth_spdm_mem_data); ++ if (!line && !table_content) ++ goto end; ++ *tmp = table_content; ++ } ++ entry++; ++ } ++end: ++ return entry; ++} ++ ++static int spdm_clear_table(struct s2io_nic *nic) ++{ ++ struct XENA_dev_config __iomem *bar0 = nic->bar0; ++ u64 val64; ++ u32 start_tbl, entry_offset, i; ++ void __iomem *element_addr; ++ ++ val64 = readq(&bar0->spdm_bir_offset); ++ start_tbl = (u32)(val64 >> 32); ++ start_tbl *= 8; ++ ++ for (entry_offset = 0; entry_offset < nic->spdm_entry; entry_offset++) { ++ element_addr = (void __iomem *)((u8 __iomem*)bar0 + start_tbl + entry_offset); ++ for (i = 0; i < 8; i++) ++ writeq(0, element_addr + (i * 8)); ++ msleep(20); ++ } ++ nic->spdm_entry = 0; ++ return 0; ++} ++ ++/* ++ * s2io_program_spdm_table - ++ */ ++static int s2io_program_spdm_table(struct spdm_cfg *info, int entry, ++ struct s2io_nic *nic) ++{ ++ struct XENA_dev_config __iomem *bar0 = nic->bar0; ++ u64 val64; ++ unsigned long tmp; ++ int ring; ++ u32 start_tbl, entry_offset; ++ struct spdm_entry element; ++ void __iomem *element_addr; ++ u16 sprt, dprt; ++ u32 sip, dip, hash; ++ ++ ring = info->t_queue; ++ entry = nic->spdm_entry; ++ ++ val64 = readq(&bar0->spdm_bir_offset); ++ start_tbl = (u32)(val64 >> 32); ++ start_tbl *= 8; ++ entry_offset = entry * sizeof(struct spdm_entry); ++ ++ element_addr = (void __iomem *) ++ ((u8 __iomem*)bar0 + start_tbl + entry_offset); ++ tmp = (unsigned long)element_addr; ++ ++ sprt = info->sprt; ++ dprt = info->dprt; ++ sip = info->sip; ++ dip = info->dip; ++ element.port_n_entry_control_0 = SPDM_PGM_L4_SRC_PORT(sprt) | ++ SPDM_PGM_L4_DST_PORT(dprt) | ++ SPDM_PGM_TARGET_QUEUE(ring); ++ if (info->sprt) { ++ if (rth_protocol == 1) /* TCP */ ++ element.port_n_entry_control_0 |= SPDM_PGM_IS_TCP | ++ SPDM_PGM_IS_IPV4; ++ else if (rth_protocol == 2) /* UDP */ ++ element.port_n_entry_control_0 |= SPDM_PGM_IS_IPV4; ++ } ++ writeq(element.port_n_entry_control_0, element_addr); ++ tmp += 8; ++ element_addr = (void __iomem*)tmp; ++ ++ element.ip.ipv4_sa_da = sip; ++ element.ip.ipv4_sa_da <<= 32; ++ element.ip.ipv4_sa_da |= dip; ++ writeq(element.ip.ipv4_sa_da, element_addr); ++ ++ tmp += 8; ++ element_addr = (void __iomem*)tmp; ++ writeq(0, element_addr); ++ tmp += 8; ++ element_addr = (void __iomem*)tmp; ++ writeq(0, element_addr); ++ tmp += 8; ++ element_addr = (void __iomem*)tmp; ++ writeq(0, element_addr); ++ tmp += 8; ++ element_addr = (void __iomem*)tmp; ++ writeq(0, element_addr); ++ tmp += 8; ++ element_addr = (void __iomem*)tmp; ++ writeq(0, element_addr); ++ tmp += 8; ++ element_addr = (void __iomem*)tmp; ++ ++ hash = info->hash; ++ element.hash_n_entry_control_1 = SPDM_PGM_HASH(hash) | ++ SPDM_PGM_ENABLE_ENTRY; ++ writeq(element.hash_n_entry_control_1, element_addr); ++ msleep(20); ++ ++ return 0; ++} ++ ++/** ++ * spdm_configure - ++ */ ++static int spdm_configure(struct s2io_nic *nic, struct spdm_cfg *info) ++{ ++ struct XENA_dev_config __iomem *bar0 = nic->bar0; ++ struct net_device *dev = nic->dev; ++ u64 val64; ++ int ret; ++ ++ val64 = readq(&bar0->spdm_bir_offset); ++ if (!(val64 & (vBIT(3, 0, 2)))) { ++ s2io_program_spdm_table(info, nic->spdm_entry, nic); ++ nic->spdm_entry++; ++ if (nic->spdm_entry == MAX_SUPPORTED_SPDM_ENTRIES) ++ nic->spdm_entry = 0; ++ ret = SUCCESS; ++ } else { ++ DBG_PRINT(ERR_DBG, "SPDM table of %s is not in BAR0!!\n", ++ dev->name); ++ info->ret = SPDM_TABLE_UNKNOWN_BAR; ++ ret = FAILURE; ++ } ++ ++ return ret; ++} ++ ++static int spdm_data_processor(struct spdm_cfg *usr_info, struct s2io_nic *sp) ++{ ++ int ret; ++ struct swDbgStat *stats = sp->sw_dbg_stat; ++ ++ if (sp->device_type == XFRAME_I_DEVICE) { ++ usr_info->ret = SPDM_XENA_IF; ++ return FAILURE; ++ } ++ ++ if (!netif_running(sp->dev)) { ++ usr_info->ret = SPDM_HW_UNINITIALIZED; ++ return FAILURE; ++ } ++ if (usr_info->ret == SPDM_GET_CFG_DATA) {/* Retrieve info */ ++ u8 *data = kmalloc(MAX_SPDM_ENTRIES_SIZE, GFP_KERNEL); ++ if (!data) { ++ usr_info->ret = SPDM_TABLE_MALLOC_FAIL; ++ stats->mem_alloc_fail_cnt++; ++ return FAILURE; ++ } ++ ++ ret = spdm_extract_table(data, sp); ++ if (ret != FAILURE) { ++ memcpy(usr_info->data, data, ++ (sp->spdm_entry * 0x40)); ++ usr_info->data_len = ret; ++ usr_info->ret = SPDM_CONF_SUCCESS; ++ ret = SUCCESS; ++ } else { ++ usr_info->ret = SPDM_TABLE_ACCESS_FAILED; ++ ret = FAILURE; ++ } ++ ++ kfree(data); ++ return ret; ++ } else if (usr_info->ret == SPDM_GET_CLR_DATA) {/* Clear info */ ++ ret = spdm_clear_table(sp); ++ if (ret != FAILURE) { ++ usr_info->ret = SPDM_CLR_SUCCESS; ++ ret = SUCCESS; ++ } else { ++ usr_info->ret = SPDM_CLR_FAIL; ++ ret = FAILURE; ++ } ++ return ret; ++ } ++ ++ if (!usr_info->dip || !usr_info->sip || !usr_info->sprt || ++ !usr_info->dprt) { ++ usr_info->ret = SPDM_INCOMPLETE_SOCKET; ++ return FAILURE; ++ } ++ ++ ret = spdm_configure(sp, usr_info); ++ if (ret == SUCCESS) ++ usr_info->ret = SPDM_CONF_SUCCESS; ++ ++ return SUCCESS; ++} ++ ++/* ++ * s2io_rth_configure - ++ */ ++int s2io_rth_configure(struct s2io_nic *nic) ++{ ++ struct XENA_dev_config __iomem *bar0 = nic->bar0; ++ register u64 val64 = 0; ++ struct config_param *config; ++ int buckets, i, ring = 0, cnt = 0; ++ ++ config = &nic->config; ++ ++ /* Enabled enhanced RTS steering */ ++ val64 = readq(&bar0->rts_ctrl); ++ val64 |= RTS_CTRL_ENHANCED; ++ writeq(val64, &bar0->rts_ctrl); ++ ++ if (config->rx_steering_type == PORT_STEERING) { ++ for (i = 0, ring = 0; i < MAX_STEERABLE_PORTS; i++) { ++ int port = rth_ports[i]; ++ if (!port) ++ break; ++ ring = i % config->rx_ring_num; ++ val64 = S2BIT(7) | vBIT(port, 8, 16) | ++ vBIT(ring, 37, 3) | S2BIT(63); ++ if (port_type == SP) ++ val64 = S2BIT(47); ++ writeq(val64, &bar0->rts_pn_cam_data); ++ val64 = S2BIT(7) | S2BIT(15) | vBIT(i, 24, 8); ++ writeq(val64, &bar0->rts_pn_cam_ctrl); ++ mdelay(5); ++ } ++ } else { ++ int rth_sz = 0; ++ int start_ring = 0; ++ ++ if (config->rx_steering_type == RTH_STEERING_DEFAULT) { ++ rth_sz = config->rx_ring_num - 1; ++ start_ring = 1; ++ } else { ++ if (rx_ring_num == 0) { ++ start_ring = 1; ++ rth_sz = config->rx_ring_num - 1; ++ } else { ++ /* ++ * If the user overrides the driver ++ * configuration of number of rings then ++ * include ring zero in the steering criteria ++ */ ++ rth_sz = config->rx_ring_num; ++ start_ring = 0; ++ } ++ } ++ ++ ring = start_ring; ++ buckets = 1 << rth_sz; ++ ++ for (i = 0; i < buckets; i++) { ++ val64 = RTS_RTH_MAP_MEM_DATA_ENTRY_EN | ++ RTS_RTH_MAP_MEM_DATA_(ring); ++ writeq(val64, &bar0->rts_rth_map_mem_data); ++ ++ val64 = RTS_RTH_MAP_MEM_CTRL_WE | ++ RTS_RTH_MAP_MEM_CTRL_STROBE | ++ RTS_RTH_MAP_MEM_CTRL_OFFSET(i); ++ writeq(val64, &bar0->rts_rth_map_mem_ctrl); ++ ++ do { ++ val64 = readq(&bar0->rts_rth_map_mem_ctrl); ++ if (val64 & RTS_RTH_MAP_MEM_CTRL_STROBE) { ++ cnt++; ++ msleep(10); ++ continue; ++ } ++ break; ++ } while (cnt < 5); ++ if (cnt == 5) ++ return FAILURE; ++ ++ if (++ring > rth_sz) ++ ring = start_ring; ++ } ++ ++ /* ++ * Mask all parameters as per user's input. ++ */ ++ for (i = 0; i < 6; i++) { ++ if (!((rth_mask >> i) & 0x1)) ++ continue; ++ switch (i) { ++ case 0: ++ val64 = readq(&bar0->rts_rth_hash_mask_n[4]); ++ val64 |= RTS_RTH_HASH_MASK_IPV4_SA(0xFFFFFFFF); ++ writeq(val64, &bar0->rts_rth_hash_mask_n[4]); ++ break; ++ case 1: ++ val64 = readq(&bar0->rts_rth_hash_mask_n[4]); ++ val64 |= RTS_RTH_HASH_MASK_IPV4_DA(0xFFFFFFFF); ++ writeq(val64, &bar0->rts_rth_hash_mask_n[4]); ++ break; ++ case 2: ++ val64 = 0xFFFFFFFFFFFFFFFFULL; ++ writeq(val64, &bar0->rts_rth_hash_mask_n[0]); ++ val64 = 0xFFFFFFFFFFFFFFFFULL; ++ writeq(val64, &bar0->rts_rth_hash_mask_n[1]); ++ break; ++ case 3: ++ val64 = 0xFFFFFFFFFFFFFFFFULL; ++ writeq(val64, &bar0->rts_rth_hash_mask_n[2]); ++ val64 = 0xFFFFFFFFFFFFFFFFULL; ++ writeq(val64, &bar0->rts_rth_hash_mask_n[3]); ++ break; ++ case 4: ++ val64 = readq(&bar0->rts_rth_hash_mask_5); ++ val64 |= RTS_RTH_HASH_MASK_L4_SP(0xFFFF); ++ writeq(val64, &bar0->rts_rth_hash_mask_5); ++ break; ++ case 5: ++ val64 = readq(&bar0->rts_rth_hash_mask_5); ++ val64 |= RTS_RTH_HASH_MASK_L4_DP(0xFFFF); ++ writeq(val64, &bar0->rts_rth_hash_mask_5); ++ break; ++ } ++ } ++ ++ /* ++ * Set the RTH function type as per user's input and enable RTH. ++ */ ++ switch (rth_protocol) { ++ case 1: ++ val64 = RTS_RTH_TCP_IPV4_EN; ++ break; ++ case 2: ++ val64 = RTS_RTH_UDP_IPV4_EN; ++ break; ++ case 3: ++ val64 = RTS_RTH_IPV4_EN; ++ break; ++ case 4: ++ val64 = RTS_RTH_TCP_IPV6_EN; ++ break; ++ case 5: ++ val64 = RTS_RTH_UDP_IPV6_EN; ++ break; ++ case 6: ++ val64 = RTS_RTH_IPV6_EN; ++ break; ++ case 7: ++ val64 = RTS_RTH_TCP_IPV6_EX_EN; ++ break; ++ case 8: ++ val64 = RTS_RTH_UDP_IPV6_EX_EN; ++ break; ++ case 9: ++ val64 = RTS_RTH_IPV6_EX_EN; ++ break; ++ default: ++ val64 = RTS_RTH_TCP_IPV4_EN; ++ break; ++ } ++ val64 |= RTS_RTH_EN | RTS_RTH_BUCKET_SIZE(rth_sz); ++ writeq(val64, &bar0->rts_rth_cfg); ++ } ++ ++ return 0; ++} ++ ++#ifndef SET_ETHTOOL_OPS ++/** ++ * s2io_ethtool -to support all ethtool features . ++ * @dev : device pointer. ++ * @ifr : An IOCTL specefic structure, that can contain a pointer to ++ * a proprietary structure used to pass information to the driver. ++ * Description: ++ * Function used to support all ethtool fatures except dumping Device stats ++ * as it can be obtained from the util tool for now. ++ * Return value: ++ * 0 on success and an appropriate (-)ve integer as defined in errno.h ++ * file on failure. ++ */ ++ ++static int s2io_ethtool(struct net_device *dev, struct ifreq *rq) ++{ ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ void *data = rq->ifr_data; ++ u32 ecmd; ++ u64 val64 = 0; ++ int i; ++#ifdef ETHTOOL_GSTATS ++ int stat_size = 0; ++#endif ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ struct swDbgStat *stats = sp->sw_dbg_stat; ++ ++ if (get_user(ecmd, (u32 *) data)) ++ return -EFAULT; ++ ++ switch (ecmd) { ++ case ETHTOOL_GSET: ++ { ++ struct ethtool_cmd info = { ETHTOOL_GSET }; ++ s2io_ethtool_gset(dev, &info); ++ if (copy_to_user(data, &info, sizeof(info))) ++ return -EFAULT; ++ break; ++ } ++ case ETHTOOL_SSET: ++ { ++ struct ethtool_cmd info; ++ ++ if (copy_from_user(&info, data, sizeof(info))) ++ return -EFAULT; ++ if (s2io_ethtool_sset(dev, &info)) ++ return -EFAULT; ++ break; ++ } ++ case ETHTOOL_GDRVINFO: ++ { ++ struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO }; ++ ++ s2io_ethtool_gdrvinfo(dev, &info); ++ if (copy_to_user(data, &info, sizeof(info))) ++ return -EFAULT; ++ break; ++ } ++ case ETHTOOL_GREGS: ++ { ++ struct ethtool_regs regs = { ETHTOOL_GREGS }; ++ u8 *reg_space; ++ int ret = 0; ++ ++ regs.version = sp->pdev->subsystem_device; ++ ++ reg_space = kmalloc(XENA_REG_SPACE, GFP_KERNEL); ++ if (reg_space == NULL) { ++ DBG_PRINT(ERR_DBG, ++ "Memory allocation to dump "); ++ DBG_PRINT(ERR_DBG, "registers failed\n"); ++ stats->mem_alloc_fail_cnt++; ++ ret = -EFAULT; ++ } ++ stats->mem_allocated += XENA_REG_SPACE; ++ memset(reg_space, 0, XENA_REG_SPACE); ++ s2io_ethtool_gregs(dev, ®s, reg_space); ++ if (copy_to_user(data, ®s, sizeof(regs))) { ++ ret = -EFAULT; ++ goto last_gregs; ++ } ++ data += offsetof(struct ethtool_regs, data); ++ if (copy_to_user(data, reg_space, regs.len)) { ++ ret = -EFAULT; ++ goto last_gregs; ++ } ++last_gregs: ++ kfree(reg_space); ++ stats->mem_freed += XENA_REG_SPACE; ++ if (ret) ++ return ret; ++ break; ++ } ++ case ETHTOOL_GLINK: ++ { ++ struct ethtool_value link = { ETHTOOL_GLINK }; ++ link.data = netif_carrier_ok(dev); ++ if (link.data) { ++ val64 = readq(&bar0->adapter_control); ++ link.data = (val64 & ADAPTER_CNTL_EN); ++ } ++ if (copy_to_user(data, &link, sizeof(link))) ++ return -EFAULT; ++ break; ++ } ++ case ETHTOOL_PHYS_ID: ++ { ++ struct ethtool_value id; ++ ++ if (copy_from_user(&id, data, sizeof(id))) ++ return -EFAULT; ++ s2io_ethtool_idnic(dev, id.data); ++ break; ++ } ++ case ETHTOOL_GRINGPARAM: ++ { ++ struct ethtool_ringparam ep = { ETHTOOL_GRINGPARAM }; ++ s2io_ethtool_gringparam(dev, &ep); ++ if (copy_to_user(data, &ep, sizeof(ep))) ++ return -EFAULT; ++ break; ++ } ++ case ETHTOOL_GPAUSEPARAM: ++ { ++ struct ethtool_pauseparam ep = { ETHTOOL_GPAUSEPARAM }; ++ s2io_ethtool_getpause_data(dev, &ep); ++ if (copy_to_user(data, &ep, sizeof(ep))) ++ return -EFAULT; ++ break; ++ ++ } ++ case ETHTOOL_SPAUSEPARAM: ++ { ++ struct ethtool_pauseparam ep; ++ ++ if (copy_from_user(&ep, data, sizeof(ep))) ++ return -EFAULT; ++ s2io_ethtool_setpause_data(dev, &ep); ++ break; ++ } ++ case ETHTOOL_GRXCSUM: ++ { ++ struct ethtool_value ev = { ETHTOOL_GRXCSUM }; ++ ++ ev.data = sp->rx_csum; ++ if (copy_to_user(data, &ev, sizeof(ev))) ++ return -EFAULT; ++ break; ++ } ++ case ETHTOOL_GTXCSUM: ++ { ++ struct ethtool_value ev = { ETHTOOL_GTXCSUM }; ++ if (sp->device_type == XFRAME_II_DEVICE) ++ ev.data = (dev->features & NETIF_F_HW_CSUM); ++ else ++ ev.data = (dev->features & NETIF_F_IP_CSUM); ++ ++ if (copy_to_user(data, &ev, sizeof(ev))) ++ return -EFAULT; ++ break; ++ } ++ case ETHTOOL_GSG: ++ { ++ struct ethtool_value ev = { ETHTOOL_GSG }; ++ ev.data = (dev->features & NETIF_F_SG); ++ ++ if (copy_to_user(data, &ev, sizeof(ev))) ++ return -EFAULT; ++ break; ++ } ++#ifdef NETIF_F_TSO ++ case ETHTOOL_GTSO: ++ { ++ struct ethtool_value ev = { ETHTOOL_GTSO }; ++ ev.data = (dev->features & NETIF_F_TSO); ++ ++ if (copy_to_user(data, &ev, sizeof(ev))) ++ return -EFAULT; ++ break; ++ } ++#endif ++ case ETHTOOL_STXCSUM: ++ { ++ struct ethtool_value ev; ++ ++ if (copy_from_user(&ev, data, sizeof(ev))) ++ return -EFAULT; ++ ++ if (ev.data) { ++ if (sp->device_type == XFRAME_II_DEVICE) ++ dev->features |= NETIF_F_HW_CSUM; ++ else ++ dev->features |= NETIF_F_IP_CSUM; ++ } else { ++ dev->features &= ~NETIF_F_IP_CSUM; ++ if (sp->device_type == XFRAME_II_DEVICE) ++ dev->features &= ~NETIF_F_HW_CSUM; ++ } ++ break; ++ } ++ case ETHTOOL_SRXCSUM: ++ { ++ struct ethtool_value ev; ++ ++ if (copy_from_user(&ev, data, sizeof(ev))) ++ return -EFAULT; ++ ++ if (ev.data) ++ sp->rx_csum = 1; ++ else ++ sp->rx_csum = 0; ++ ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ sp->mac_control.rings[i].rx_csum = sp->rx_csum; ++ break; ++ } ++ case ETHTOOL_SSG: ++ { ++ struct ethtool_value ev; ++ ++ if (copy_from_user(&ev, data, sizeof(ev))) ++ return -EFAULT; ++ ++ if (ev.data) ++ dev->features |= NETIF_F_SG; ++ else ++ dev->features &= ~NETIF_F_SG; ++ break; ++ } ++#ifdef NETIF_F_TSO ++ case ETHTOOL_STSO: ++ { ++ struct ethtool_value ev; ++ ++ if (copy_from_user(&ev, data, sizeof(ev))) ++ return -EFAULT; ++ ++ if (ev.data) ++ dev->features |= NETIF_F_TSO; ++ else ++ dev->features &= ~NETIF_F_TSO; ++ break; ++ } ++#endif ++ case ETHTOOL_GEEPROM: ++ { ++ struct ethtool_eeprom eeprom = { ETHTOOL_GEEPROM }; ++ char *data_buf; ++ int ret = 0; ++ ++ if (copy_from_user(&eeprom, data, sizeof(eeprom))) ++ return -EFAULT; ++ ++ if (eeprom.len <= 0) ++ return -EINVAL; ++ data_buf = kmalloc(XENA_EEPROM_SPACE, GFP_KERNEL); ++ if (!data_buf) { ++ stats->mem_alloc_fail_cnt++; ++ return -ENOMEM; ++ } ++ stats->mem_allocated += ++ XENA_EEPROM_SPACE; ++ s2io_ethtool_geeprom(dev, &eeprom, data_buf); ++ ++ if (copy_to_user(data, &eeprom, sizeof(eeprom))) { ++ ret = -EFAULT; ++ goto last_geprom; ++ } ++ ++ data += offsetof(struct ethtool_eeprom, data); ++ ++ if (copy_to_user(data, (void *)data_buf, eeprom.len)) { ++ ret = -EFAULT; ++ goto last_geprom; ++ } ++ ++last_geprom: ++ kfree(data_buf); ++ stats->mem_freed += XENA_EEPROM_SPACE; ++ if (ret) ++ return ret; ++ break; ++ } ++ case ETHTOOL_SEEPROM: ++ { ++ struct ethtool_eeprom eeprom; ++ unsigned char *data_buf; ++ void *ptr; ++ int ret = 0; ++ ++ if (copy_from_user(&eeprom, data, sizeof(eeprom))) ++ return -EFAULT; ++ ++ data_buf = kmalloc(eeprom.len, GFP_KERNEL); ++ if (!data_buf) { ++ stats->mem_alloc_fail_cnt++; ++ return -ENOMEM; ++ } ++ ++ stats->mem_allocated += eeprom.len; ++ ptr = (void *) data_buf; ++ ++ data += offsetof(struct ethtool_eeprom, data); ++ if (copy_from_user(ptr, data, eeprom.len)) { ++ ret = -EFAULT; ++ goto last_seprom; ++ } ++ ++ if ((eeprom.offset + eeprom.len) > (XENA_EEPROM_SPACE)) { ++ DBG_PRINT(ERR_DBG, "%s Write ", dev->name); ++ DBG_PRINT(ERR_DBG, "request overshoots "); ++ DBG_PRINT(ERR_DBG, "the EEPROM area\n"); ++ ret = -EFAULT; ++ goto last_seprom; ++ } ++ if (s2io_ethtool_seeprom(dev, &eeprom, data_buf)) { ++ ret = -EFAULT; ++ goto last_seprom; ++ } ++ ++last_seprom: ++ kfree(data_buf); ++ stats->mem_freed += eeprom.len; ++ if (ret) ++ return ret; ++ break; ++ } ++ case ETHTOOL_GSTRINGS: ++ { ++ struct ethtool_gstrings gstrings = { ETHTOOL_GSTRINGS }; ++ char *strings = NULL; ++ int ret = 0, mem_sz; ++ ++ if (copy_from_user(&gstrings, data, sizeof(gstrings))) ++ return -EFAULT; ++ ++ switch (gstrings.string_set) { ++ case ETH_SS_TEST: ++ gstrings.len = S2IO_TEST_LEN; ++ mem_sz = S2IO_STRINGS_LEN; ++ strings = kmalloc(mem_sz, GFP_KERNEL); ++ if (!strings) { ++ stats->mem_alloc_fail_cnt++; ++ return -ENOMEM; ++ } ++ ++ memcpy(strings, s2io_gstrings, S2IO_STRINGS_LEN); ++ break; ++ ++#ifdef ETHTOOL_GSTATS ++ case ETH_SS_STATS: ++#ifdef TITAN_LEGACY ++ if (sp->device_type == TITAN_DEVICE) { ++ gstrings.len = S2IO_TITAN_STAT_LEN; ++ mem_sz = S2IO_TITAN_STAT_STRINGS_LEN; ++ strings = kmalloc(mem_sz, GFP_KERNEL); ++ if (!strings) { ++ stats->mem_alloc_fail_cnt++; ++ return -ENOMEM; ++ } ++ memcpy(strings, ++ ðtool_titan_stats_keys, ++ sizeof(ethtool_titan_stats_keys)); ++ } else ++#endif ++ { ++ if (sp->device_type == XFRAME_I_DEVICE) { ++ gstrings.len = XFRAME_I_STAT_LEN; ++ mem_sz = XFRAME_I_STAT_STRINGS_LEN; ++ } else { ++ gstrings.len = XFRAME_II_STAT_LEN; ++ mem_sz = XFRAME_II_STAT_STRINGS_LEN; ++ } ++ gstrings.len += (sp->config.tx_fifo_num ++ * NUM_TX_SW_STAT * ETH_GSTRING_LEN) + ++ (sp->config.rx_ring_num ++ * NUM_RX_SW_STAT * ETH_GSTRING_LEN); ++ mem_sz += (sp->config.tx_fifo_num ++ * NUM_TX_SW_STAT * ETH_GSTRING_LEN) + ++ (sp->config.rx_ring_num ++ * NUM_RX_SW_STAT * ETH_GSTRING_LEN); ++ ++ ++ gstrings.len += ++ S2IO_DRIVER_DBG_STAT_LEN; ++ mem_sz += S2IO_DRIVER_DBG_STAT_LEN * ++ ETH_GSTRING_LEN; ++ ++ strings = kmalloc(mem_sz, GFP_KERNEL); ++ if (!strings) { ++ stats->mem_alloc_fail_cnt++; ++ return -ENOMEM; ++ } ++ ++ stat_size = sizeof(ethtool_xena_stats_keys); ++ memcpy(strings, ++ ðtool_xena_stats_keys, stat_size); ++ ++ if (sp->device_type == XFRAME_II_DEVICE) { ++ memcpy(strings + stat_size, ++ ðtool_enhanced_stats_keys, ++ sizeof(ethtool_enhanced_stats_keys)); ++ ++ stat_size += ++ sizeof(ethtool_enhanced_stats_keys); ++ } ++ ++ memcpy(strings + stat_size, ++ ðtool_driver_stats_keys, ++ sizeof(ethtool_driver_stats_keys)); ++ ++ stat_size += sizeof(ethtool_driver_stats_keys); ++ memcpy(strings + stat_size, ++ ðtool_driver_dbg_stats_keys, ++ sizeof(ethtool_driver_dbg_stats_keys)); ++ ++ } ++ break; ++#endif ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ if (copy_to_user(data, &gstrings, sizeof(gstrings))) ++ ret = -EFAULT; ++ if (!ret) { ++ data += ++ offsetof(struct ethtool_gstrings, ++ data); ++ if (copy_to_user(data, strings, mem_sz)) ++ ret = -EFAULT; ++ } ++ kfree(strings); ++ if (ret) ++ return ret; ++ break; ++ } ++ case ETHTOOL_TEST: ++ { ++ struct { ++ struct ethtool_test ethtest; ++ uint64_t data[S2IO_TEST_LEN]; ++ } test = { {ETHTOOL_TEST} }; ++ ++ if (copy_from_user(&test.ethtest, data, sizeof(test.ethtest))) ++ return -EFAULT; ++ ++ s2io_ethtool_test(dev, &test.ethtest, test.data); ++ if (copy_to_user(data, &test, sizeof(test))) ++ return -EFAULT; ++ ++ break; ++ } ++#ifdef ETHTOOL_GSTATS ++ case ETHTOOL_GSTATS: ++ { ++ struct ethtool_stats eth_stats; ++ int ret; ++ u64 *stat_mem; ++ ++ if (copy_from_user(ð_stats, data, sizeof(eth_stats))) ++ return -EFAULT; ++#ifdef TITAN_LEGACY ++ if (sp->device_type == TITAN_DEVICE) ++ eth_stats.n_stats = S2IO_TITAN_STAT_LEN; ++ else ++#endif ++ { ++ if (sp->device_type == XFRAME_I_DEVICE) ++ eth_stats.n_stats += XFRAME_I_STAT_LEN + ++ (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + ++ (sp->config.rx_ring_num * NUM_RX_SW_STAT); ++ else ++ eth_stats.n_stats += XFRAME_II_STAT_LEN + ++ (sp->config.tx_fifo_num * NUM_TX_SW_STAT) + ++ (sp->config.rx_ring_num * NUM_RX_SW_STAT); ++ ++ eth_stats.n_stats += S2IO_DRIVER_DBG_STAT_LEN; ++ } ++ ++ stat_mem = ++ kmalloc(eth_stats.n_stats * sizeof(u64), GFP_USER); ++ if (!stat_mem) { ++ stats->mem_alloc_fail_cnt++; ++ return -ENOMEM; ++ } ++ stats->mem_allocated += ++ (eth_stats.n_stats * sizeof(u64)); ++ s2io_get_ethtool_stats(dev, ð_stats, stat_mem); ++ ret = 0; ++ if (copy_to_user(data, ð_stats, sizeof(eth_stats))) ++ ret = -EFAULT; ++ data += sizeof(eth_stats); ++ if (copy_to_user(data, stat_mem, ++ eth_stats.n_stats * sizeof(u64))) ++ ret = -EFAULT; ++ kfree(stat_mem); ++ stats->mem_freed += (eth_stats.n_stats * sizeof(u64)); ++ return ret; ++ } ++#endif ++ ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return 0; ++} ++#endif ++ ++#ifdef SNMP_SUPPORT ++int s2io_snmp_init(struct s2io_nic *nic) ++{ ++ struct net_device *dev = nic->dev; ++ struct timeval tm; ++ if (!s2io_bdsnmp_init(dev)) ++ DBG_PRINT(INIT_DBG, "Error Creating Proc directory for SNMP\n"); ++ ++ do_gettimeofday(&tm); ++ nic->lDate = tm.tv_sec; ++ return 0; ++} ++ ++int s2io_snmp_exit(struct s2io_nic *nic) ++{ ++ struct net_device *dev = nic->dev; ++ s2io_bdsnmp_rem(dev); ++ return 0; ++} ++ ++/** ++ * fnBaseDrv - Get the driver information ++ * @pBaseDrv -Pointer to Base driver structure which contains the offset ++ * and length of each of the field. ++ * Description ++ * This function copies the driver specific information from the dev structure ++ * to the pBaseDrv stucture. It calculates the number of physical adapters by ++ * parsing the dev_base global variable maintained by the kernel. This ++ * variable has to read locked before accesing.This function is called by ++ * fnBaseReadProc function. ++ * ++ */ ++ ++static void fnBaseDrv(struct stBaseDrv *pBaseDrv, struct net_device *dev) ++{ ++ ++ struct pci_dev *pdev = NULL; ++ struct net_device *ndev; ++ struct s2io_nic *sp = s2io_netdev_priv(dev); ++ struct XENA_dev_config __iomem *bar0 = sp->bar0; ++ int nCount = 0; ++ int i; ++ struct swDbgStat *stats = sp->sw_dbg_stat; ++ ++ strncpy(pBaseDrv->m_cName, sp->cName, 20); ++ strncpy(pBaseDrv->m_cVersion, sp->cVersion, 20); ++ pBaseDrv->m_nStatus = sp->last_link_state; ++ pBaseDrv->m_nMemorySize = stats->mem_allocated; ++ sprintf(pBaseDrv->m_cDate, "%ld", sp->lDate); ++ pBaseDrv->m_dev_id = sp->pdev->device; ++ pBaseDrv->m_ven_id = PCI_VENDOR_ID_S2IO; ++ pBaseDrv->m_tx_intr_cnt = sp->tx_intr_cnt; ++ pBaseDrv->m_rx_intr_cnt = 0; ++ ++ if (sp->config.intr_type == MSI_X) { ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ pBaseDrv->m_rx_intr_cnt += ++ sp->mac_control.rings[i].rx_ring_stat->rx_msix_cnt; ++ } else ++ pBaseDrv->m_rx_intr_cnt = sp->rx_inta_cnt; ++ ++ pBaseDrv->m_intr_type = sp->config.intr_type; ++ pBaseDrv->m_tx_fifo_num = sp->config.tx_fifo_num; ++ pBaseDrv->m_rx_ring_num = sp->config.rx_ring_num; ++ pBaseDrv->m_rxd_mode = sp->rxd_mode; ++ pBaseDrv->m_lro = sp->lro; ++ pBaseDrv->m_lro_max_pkts = sp->lro_max_aggr_per_sess; ++ pBaseDrv->m_napi = sp->config.napi; ++ pBaseDrv->m_rx_steering_type = sp->config.rx_steering_type; ++ pBaseDrv->m_vlan_tag_strip = sp->config.vlan_tag_strip; ++ pBaseDrv->m_rx_csum = sp->rx_csum; ++ if (sp->device_type == XFRAME_II_DEVICE) ++ pBaseDrv->m_tx_csum = ((dev->features & NETIF_F_HW_CSUM)? 1: 0); ++ else ++ pBaseDrv->m_tx_csum = ((dev->features & NETIF_F_IP_CSUM)? 1: 0); ++ pBaseDrv->m_sg = ((dev->features & NETIF_F_SG)?1:0); ++#ifndef NETIF_F_UFO ++ pBaseDrv->m_ufo = 0; ++#else ++ pBaseDrv->m_ufo = 0; ++ if ((sp->device_type == XFRAME_II_DEVICE) && ufo) ++ pBaseDrv->m_ufo = 1; ++#endif ++#ifndef NETIF_F_TSO ++ pBaseDrv->m_tso = 0; ++#else ++ pBaseDrv->m_tso = 1; ++#endif ++ pBaseDrv->m_nFeature = ((pBaseDrv->m_tx_csum && sp->rx_csum && ++ pBaseDrv->m_tso)?3:((pBaseDrv->m_tso)?1:0)); ++ pBaseDrv->m_fifo_len = 0; ++ for (i = 0; i < sp->config.tx_fifo_num; i++) ++ pBaseDrv->m_fifo_len += sp->config.tx_cfg[i].fifo_len; ++ pBaseDrv->m_rx_ring_size = 0; ++ for (i = 0; i < sp->config.rx_ring_num; i++) ++ pBaseDrv->m_rx_ring_size += rx_ring_sz[i]; ++ pBaseDrv->m_rth_bucket_size = ((sp->config.rx_ring_num + 1)/2); ++ pBaseDrv->m_tx_urng = readq(&bar0->tti_data1_mem); ++ pBaseDrv->m_rx_urng = readq(&bar0->rti_data1_mem); ++ pBaseDrv->m_tx_ufc = readq(&bar0->tti_data2_mem); ++ pBaseDrv->m_rx_ufc = readq(&bar0->rti_data2_mem); ++ /* ++ * Find all the ethernet devices on the system using ++ * pci_find_device. Get the private data which will be the ++ * net_device structure assigned by the driver. ++ */ ++ while ((pdev = ++ S2IO_PCI_FIND_DEVICE(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) { ++ if (pdev->vendor == PCI_VENDOR_ID_S2IO) { ++ ndev = (struct net_device *) pci_get_drvdata(pdev); ++ if (ndev == NULL) ++ continue; ++ memcpy(pBaseDrv->m_stPhyAdap[nCount].m_cName, ++ ndev->name, 20); ++ pBaseDrv->m_stPhyAdap[nCount].m_nIndex = ndev->ifindex; ++ nCount++; ++ } ++ } ++ pBaseDrv->m_nPhyCnt = nCount; ++} ++ ++/* ++* fnBaseReadProc - Read entry point for the proc file ++* @page - Buffer pointer where the data is written ++* @start- Pointer to buffer ptr . It is used if the data is more than a page ++* @off- the offset to the page where data is written ++* @count - number of bytes to write ++* @eof - to indicate end of file ++* @data - pointer to device structure. ++* ++* Description - ++* This function gets Base driver specific information from the fnBaseDrv ++* function and writes into the BDInfo file. This function is called whenever ++* the user reads the file. The length of data written cannot exceed 4kb. ++* If it exceeds then use the start pointer to write multiple pages ++* Return - the length of the string written to proc file ++*/ ++static int fnBaseReadProc(char *page, char **start, off_t off, int count, ++ int *eof, void *data) ++{ ++ struct stBaseDrv *pBaseDrv; ++ int nLength = 0; ++ int nCount = 0; ++ struct net_device *dev = (struct net_device *) data; ++ int nIndex = 0; ++ ++ pBaseDrv = kmalloc(sizeof(struct stBaseDrv), GFP_KERNEL); ++ if (pBaseDrv == NULL) { ++ DBG_PRINT(ERR_DBG, "Error allocating memory\n"); ++ return -ENOMEM; ++ } ++ fnBaseDrv(pBaseDrv, dev); ++ sprintf(page + nLength, "%-30s%-20s\n", "Base Driver Name", ++ pBaseDrv->m_cName); ++ nLength += 51; ++ if (pBaseDrv->m_nStatus == 2) ++ sprintf(page + nLength, "%-30s%-20s\n", "Load Status", ++ "Loaded"); ++ else ++ sprintf(page + nLength, "%-30s%-20s\n", "Load Status", ++ "UnLoaded"); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20s\n", "Base Driver Version", ++ pBaseDrv->m_cVersion); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20d\n", "Feature Supported", ++ pBaseDrv->m_nFeature); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20lld\n", ++ "Base Driver Memrory in Bytes", pBaseDrv->m_nMemorySize); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20s\n", "Base Driver Date", ++ pBaseDrv->m_cDate); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20d\n", "No of Phy Adapter", ++ pBaseDrv->m_nPhyCnt); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20x\n", "Device id", ++ pBaseDrv->m_dev_id); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20x\n", "Vendor id", ++ pBaseDrv->m_ven_id); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20u\n", "Tx Interrupt Count", ++ pBaseDrv->m_tx_intr_cnt); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20u\n", "Rx Interrupt Count", ++ pBaseDrv->m_rx_intr_cnt); ++ nLength += 51; ++ if (pBaseDrv->m_intr_type == 0) ++ sprintf(page + nLength, "%-30s%-20s\n", "Interrupt Type", ++ "INTA"); ++ else ++ sprintf(page + nLength, "%-30s%-20s\n", "Interrupt Type", ++ "MSI-X"); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20u\n", "FIFOs Configured", ++ pBaseDrv->m_tx_fifo_num); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20u\n", "Rings Configured", ++ pBaseDrv->m_rx_ring_num); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20d\n", "Fifo Length", ++ pBaseDrv->m_fifo_len); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20d\n", "Rx Ring Size", ++ pBaseDrv->m_rx_ring_size); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20d\n", "Rth Bucket Size", ++ pBaseDrv->m_rth_bucket_size); ++ nLength += 51; ++ if (pBaseDrv->m_rxd_mode == 0) ++ sprintf(page + nLength, "%-30s%-20s\n", "Rx Buffer Mode", ++ "1-buffer mode"); ++ else if (pBaseDrv->m_rxd_mode == 1) ++ sprintf(page + nLength, "%-30s%-20s\n", "Rx Buffer Mode", ++ "2-buffer mode"); ++ else ++ sprintf(page + nLength, "%-30s%-20s\n", "Rx Buffer Mode", ++ "5-buffer mode"); ++ nLength += 51; ++ if (pBaseDrv->m_lro == 1) ++ sprintf(page + nLength, "%-30s%-20s\n", "LRO", ++ "LRO ENABLED"); ++ else ++ sprintf(page + nLength, "%-30s%-20s\n", "LRO", ++ "LRO DISABLED"); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s%-20d\n", "LRO Max Packets", ++ pBaseDrv->m_lro_max_pkts); ++ nLength += 51; ++ if (pBaseDrv->m_napi == 1) ++ sprintf(page + nLength, "%-30s%-20s\n", "NAPI", ++ "NAPI ENABLED"); ++ else ++ sprintf(page + nLength, "%-30s%-20s\n", "NAPI", ++ "NAPI DISABLED"); ++ nLength += 51; ++ if (pBaseDrv->m_ufo == 1) ++ sprintf(page + nLength, "%-30s%-20s\n", "UFO", ++ "UFO ENABLED"); ++ else ++ sprintf(page + nLength, "%-30s%-20s\n", "UFO", ++ "UFO DISABLED"); ++ nLength += 51; ++ if (pBaseDrv->m_tso == 1) ++ sprintf(page + nLength, "%-30s%-20s\n", "TSO", ++ "TSO ENABLED"); ++ else ++ sprintf(page + nLength, "%-30s%-20s\n", "TSO", ++ "TSO DISABLED"); ++ nLength += 51; ++ if (pBaseDrv->m_rx_steering_type == 0) ++ sprintf(page + nLength, "%-30s%-20s\n", "Rx Steering Type", ++ "NO STEERING"); ++ else if (pBaseDrv->m_rx_steering_type == 1) ++ sprintf(page + nLength, "%-30s%-20s\n", "Rx Steering Type", ++ "PORT STEERING"); ++ else ++ sprintf(page + nLength, "%-30s%-20s\n", "Rx Steering Type", ++ "RTH ENABLED"); ++ nLength += 51; ++ if (pBaseDrv->m_vlan_tag_strip == 0) ++ sprintf(page + nLength, "%-30s%-20s\n", "VLAN Tag Stripping", ++ "DISABLED"); ++ else if (pBaseDrv->m_vlan_tag_strip == 1) ++ sprintf(page + nLength, "%-30s%-20s\n", "VLAN Tag Stripping", ++ "ENABLED"); ++ else ++ sprintf(page + nLength, "%-30s%-20s\n", "VLAN Tag Stripping", ++ "DEFAULT MODE"); ++ nLength += 51; ++ if (pBaseDrv->m_rx_csum == 1) ++ sprintf(page + nLength, "%-30s%-20s\n", "Rx Checksum", ++ "RX CSUM ENABLED"); ++ else ++ sprintf(page + nLength, "%-30s%-20s\n", "Rx Checksum", ++ "RX CSUM DISABLED"); ++ nLength += 51; ++ if (pBaseDrv->m_tx_csum == 1) ++ sprintf(page + nLength, "%-30s%-20s\n", "Tx Checksum", ++ "TX CSUM ENABLED"); ++ else ++ sprintf(page + nLength, "%-30s%-20s\n", "Tx Checksum", ++ "TX CSUM DISABLED"); ++ nLength += 51; ++ if (pBaseDrv->m_sg == 1) ++ sprintf(page + nLength, "%-30s%-20s\n", "Scatter Gather", ++ "SG ENABLED"); ++ else ++ sprintf(page + nLength, "%-30s%-20s\n", "Scatter Gather", ++ "SG DISABLED"); ++ nLength += 51; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "TX_URNG_A", ++ ((unsigned long long)(0x7F0000 & pBaseDrv->m_tx_urng) >> 16)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "TX_URNG_B", ++ ((unsigned long long)(0x7F00 & pBaseDrv->m_tx_urng) >> 8)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "TX_URNG_C", ++ (unsigned long long)(0x7F & pBaseDrv->m_tx_urng)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "RX_URNG_A", ++ ((unsigned long long)(0x7F0000 & pBaseDrv->m_rx_urng) >> 16)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "RX_URNG_B", ++ ((unsigned long long)(0x7F00 & pBaseDrv->m_rx_urng) >> 8)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "RX_URNG_C", ++ (unsigned long long)(0x7F & pBaseDrv->m_rx_urng)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "TX_UFC_A", ++ ((unsigned long long) ++ (0xFFFF000000000000ULL & pBaseDrv->m_tx_ufc) >> 48)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "TX_UFC_B", ++ ((unsigned long long) ++ (0xFFFF00000000ULL & pBaseDrv->m_tx_ufc) >> 32)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "TX_UFC_C", ++ ((unsigned long long)(0xFFFF0000 & pBaseDrv->m_tx_ufc) >> 16)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "TX_UFC_D", ++ (unsigned long long)(0xFFFF & pBaseDrv->m_tx_ufc)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "RX_UFC_A", ++ ((unsigned long long) ++ (0xFFFF000000000000ULL & pBaseDrv->m_rx_ufc) >> 48)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "RX_UFC_B", ++ ((unsigned long long) ++ (0xFFFF00000000ULL & pBaseDrv->m_rx_ufc) >> 32)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "RX_UFC_C", ++ ((unsigned long long)(0xFFFF0000 & pBaseDrv->m_rx_ufc) >> 16)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s0x%-20llx\n", "RX_UFC_D", ++ (unsigned long long)(0xFFFF & pBaseDrv->m_rx_ufc)); ++ nLength += 53; ++ sprintf(page + nLength, "%-30s%-20s\n\n", "Phy Adapter Index", ++ "Phy Adapter Name"); ++ nLength += 42; ++ for (nIndex = 0, nCount = pBaseDrv->m_nPhyCnt; nCount != 0; ++ nCount--, nIndex++) { ++ sprintf(page + nLength, "%-20d%-20s\n", ++ pBaseDrv->m_stPhyAdap[nIndex].m_nIndex, ++ pBaseDrv->m_stPhyAdap[nIndex].m_cName); ++ nLength += 41; ++ } ++ ++ *eof = 1; ++ kfree(pBaseDrv); ++ return nLength; ++} ++ ++/* ++ * fnPhyAdapReadProc - Read entry point for the proc file ++ * @page - Buffer pointer where the data is written ++ * @start- Pointer to buffer ptr . It is used if the data is more than a page ++ * @off- the offset to the page where data is written ++ * @count - number of bytes to write ++ * @eof - to indicate end of file ++ * @data - pointer to device structure. ++ * ++ * Description - ++ * This function gets physical adapter information. This function is called ++ * whenever the user reads the file. The length of data written cannot ++ * exceed 4kb. If it exceeds then use the start pointer to write multiple page ++ * ++ * Return - the length of the string written to proc file ++ */ ++static int fnPhyAdapReadProc(char *page, char **start, off_t off, ++ int count, int *eof, void *data) ++{ ++ ++ struct stPhyData *pPhyData; ++ struct net_device *pNetDev = (struct net_device *) data; ++ struct s2io_nic *sp = s2io_netdev_priv(pNetDev); ++ struct net_device_stats *pNetStat; ++ struct pci_dev *pdev = NULL; ++ int nLength = 0; ++ u64 pmaddr; ++ unsigned char cMAC[20]; ++ unsigned char pMAC[20]; ++ pPhyData = kmalloc(sizeof(struct stPhyData), GFP_KERNEL); ++ if (pPhyData == NULL) { ++ DBG_PRINT(ERR_DBG, "Error allocating memory\n"); ++ return -ENOMEM; ++ } ++ ++ /* Print the header in the PhyAdap proc file */ ++ sprintf(page + nLength, ++ "%-10s%-22s%-10s%-10s%-22s%-22s%-22s%-10s%-10s%-10s%-10s%-10s" ++ "%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s\n", ++ "Index", "Description", "Mode", "Type", "Speed", "PMAC", "CMAC", ++ "Status", "Slot", "Bus", "IRQ", "Colis", "Multi", ++ "RxBytes", "RxDrop", "RxError", "RxPacket", "TRxBytes", ++ "TRxDrop", "TxError", "TxPacket"); ++ ++ /* 259 is the lenght of the above string copied in the page */ ++ nLength += 259; ++ ++ while ((pdev = ++ S2IO_PCI_FIND_DEVICE(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) { ++ if (pdev->vendor == PCI_VENDOR_ID_S2IO) { ++ /* Private data will point to the netdevice structure */ ++ pNetDev = (struct net_device *) pci_get_drvdata(pdev); ++ if (pNetDev == NULL) ++ continue; ++ if (pNetDev->addr_len != 0) { ++ pNetStat = pNetDev->get_stats(pNetDev); ++ pPhyData->m_nIndex = pNetDev->ifindex; ++ memcpy(pPhyData->m_cDesc, pNetDev->name, 20); ++ pPhyData->m_nMode = 0; ++ pPhyData->m_nType = 0; ++ switch (pPhyData->m_nType) { ++ /* ++ case IFT_ETHER: ++ memcpy(pPhyData->m_cSpeed, ++ "10000000",20); ++ break; ++ ++ case 9: ++ memcpy(pPhyData->m_cSpeed, ++ "4000000",20); ++ break; ++ */ ++ default: ++ memcpy(pPhyData->m_cSpeed, ++ "10000000", 20); ++ break; ++ } ++ pmaddr = do_s2io_read_unicast_mc(sp, 0); ++ memcpy(pPhyData->m_cPMAC, &pmaddr, ++ ETH_ALEN); ++ memcpy(pPhyData->m_cCMAC, pNetDev->dev_addr, ++ ETH_ALEN); ++ pPhyData->m_nLinkStatus = ++ test_bit(__LINK_STATE_START, ++ &pNetDev->state); ++ pPhyData->m_nPCISlot = PCI_SLOT(pdev->devfn); ++ pPhyData->m_nPCIBus = pdev->bus->number; ++ pPhyData->m_nIRQ = pNetDev->irq; ++ pPhyData->m_nCollision = pNetStat->collisions; ++ pPhyData->m_nMulticast = pNetStat->multicast; ++ ++ pPhyData->m_nRxBytes = pNetStat->rx_bytes; ++ pPhyData->m_nRxDropped = pNetStat->rx_dropped; ++ pPhyData->m_nRxErrors = pNetStat->rx_errors; ++ pPhyData->m_nRxPackets = pNetStat->rx_packets; ++ ++ pPhyData->m_nTxBytes = pNetStat->tx_bytes; ++ pPhyData->m_nTxDropped = pNetStat->tx_dropped; ++ pPhyData->m_nTxErrors = pNetStat->tx_errors; ++ pPhyData->m_nTxPackets = pNetStat->tx_packets; ++ ++ sprintf(cMAC, "%02x:%02x:%02x:%02x:%02x:%02x", ++ pPhyData->m_cCMAC[0], ++ pPhyData->m_cCMAC[1], ++ pPhyData->m_cCMAC[2], ++ pPhyData->m_cCMAC[3], ++ pPhyData->m_cCMAC[4], ++ pPhyData->m_cCMAC[5]); ++ ++ sprintf(pMAC, "%02x:%02x:%02x:%02x:%02x:%02x", ++ pPhyData->m_cPMAC[5], ++ pPhyData->m_cPMAC[4], ++ pPhyData->m_cPMAC[3], ++ pPhyData->m_cPMAC[2], ++ pPhyData->m_cPMAC[1], ++ pPhyData->m_cPMAC[0]); ++ ++ sprintf(page + nLength, ++ "%-10d%-22s%-10d%-10d%-22s%-22s%-22s" ++ "%-10d%-10d%-10d%-10d%-10d%-10d%-10lld" ++ "%-10lld%-10lld%-10lld%-10lld%-10lld" ++ "%-10lld%-10lld\n", ++ pPhyData->m_nIndex, pPhyData->m_cDesc, ++ pPhyData->m_nMode, pPhyData->m_nType, ++ pPhyData->m_cSpeed, pMAC, cMAC, ++ pPhyData->m_nLinkStatus, ++ pPhyData->m_nPCISlot, pPhyData->m_nPCIBus, ++ pPhyData->m_nIRQ, pPhyData->m_nCollision, ++ pPhyData->m_nMulticast, ++ pPhyData->m_nRxBytes, ++ pPhyData->m_nRxDropped, ++ pPhyData->m_nRxErrors, ++ pPhyData->m_nRxPackets, ++ pPhyData->m_nTxBytes, ++ pPhyData->m_nTxDropped, ++ pPhyData->m_nTxErrors, ++ pPhyData->m_nTxPackets); ++ nLength += 259; ++ } ++ } ++ } ++ *eof = 1; ++ kfree(pPhyData); ++ return nLength; ++} ++ ++/* ++ * s2io_bdsnmp_init - Entry point to create proc file ++ * @dev- Pointer to net device structure passed by the driver. ++ * Return ++ * Success If creates all the files ++ * ERROR_PROC_ENTRY /ERROR_PROC_DIR Error If could not create all the files ++ * Description ++ * This functon is called when the driver is loaded. It creates the S2IO ++ * proc file system in the /proc/net/ directory. This directory is used to ++ * store the info about the base driver afm driver, lacp, vlan and nplus. ++ * It checks if S2IO directory already exists else creates it and creates ++ * the files BDInfo files and assiciates read function to each of the files. ++ */ ++ ++static int s2io_bdsnmp_init(struct net_device *dev) ++{ ++ struct proc_dir_entry *S2ioDir; ++ struct proc_dir_entry *BaseDrv; ++ struct proc_dir_entry *PhyAdap; ++ ++ /* IF the directory already exists then just return */ ++ for (S2ioDir = proc_net->subdir; S2ioDir != NULL; ++ S2ioDir = S2ioDir->next) { ++ if (!strcmp(S2ioDir->name, S2IODIRNAME)) ++ break; ++ } ++ ++ if (S2ioDir == NULL) { ++ /* Create the s2io directory */ ++ if (!(S2ioDir = ++ create_proc_entry(S2IODIRNAME, S_IFDIR, proc_net))) { ++ DBG_PRINT(INIT_DBG, ++ "Error Creating Proc directory for SNMP\n"); ++ return ERROR_PROC_DIR; ++ } ++ } ++ ++ /* IF the directory already exists then just return */ ++ for (BaseDrv = S2ioDir->subdir; BaseDrv != NULL; ++ BaseDrv = BaseDrv->next) { ++ if (!strcmp(BaseDrv->name, BDFILENAME)) ++ break; ++ } ++ ++ if (BaseDrv == NULL) { ++ ++ /* Create the BDInfo file to store driver info and associate ++ * read funtion ++ */ ++ if (!(BaseDrv = ++ create_proc_read_entry(BDFILENAME, S_IFREG | S_IRUSR, ++ S2ioDir, fnBaseReadProc, (void *) dev))) { ++ DBG_PRINT(INIT_DBG, "Error Creating Proc " ++ "File for Base Drvr\n"); ++ return ERROR_PROC_ENTRY; ++ } ++ } ++ ++ /* IF the directory already exists then just return */ ++ for (PhyAdap = S2ioDir->subdir; PhyAdap != NULL; ++ PhyAdap = PhyAdap->next) { ++ if (!strcmp(PhyAdap->name, PADAPFILENAME)) ++ break; ++ } ++ ++ if (PhyAdap == NULL) { ++ if (!(PhyAdap = ++ create_proc_read_entry(PADAPFILENAME, S_IFREG | S_IRUSR, ++ S2ioDir, fnPhyAdapReadProc, (void *) dev))) { ++ DBG_PRINT(INIT_DBG, "Error Creating Proc File " ++ "for Phys Adap\n"); ++ return ERROR_PROC_ENTRY; ++ } ++ } ++ ++ return SUCCESS; ++} ++ ++/** ++ * s2io_bdsnmp_rem : Removes the proc file entry ++ * @dev - pointer to netdevice structre ++ * Return - void ++ * Description ++ * This functon is called when the driver is Unloaded. It checks if the ++ * S2IO directoy exists and deletes the files in the reverse order of ++ * creation. ++ */ ++ ++static void s2io_bdsnmp_rem(struct net_device *dev) ++{ ++ int nLength = 0; ++ struct proc_dir_entry *S2ioDir; ++ nLength = strlen(S2IODIRNAME); ++ /* ++ * Check if the S2IO directory exists or not and then delete ++ * all the files in the S2IO Directory ++ */ ++ for (S2ioDir = proc_net->subdir; S2ioDir != NULL; ++ S2ioDir = S2ioDir->next) { ++ if ((S2ioDir->namelen == nLength) ++ && (!memcmp(S2ioDir->name, S2IODIRNAME, ++ nLength))) ++ break; ++ } ++ if (S2ioDir == NULL) ++ return; ++ remove_proc_entry(BDFILENAME, S2ioDir); ++ remove_proc_entry(PADAPFILENAME, S2ioDir); ++ if (S2ioDir->subdir == NULL) ++ remove_proc_entry(S2IODIRNAME, proc_net); ++} ++#endif ++/* ++ * To build the driver, ++ * gcc -D__KERNEL__ -DMODULE -I/usr/src/linux-2.4/include -Wall ++ * -Wstrict-prototypes -O2 -c s2io.c ++ */ +diff -r c9d7db01a94c drivers/net/s2io.h +--- a/drivers/net/s2io.h Tue Sep 01 13:50:23 2009 +0100 ++++ b/drivers/net/s2io.h Tue Sep 01 16:19:08 2009 +0100 +@@ -1,20 +1,19 @@ +-/************************************************************************ +- * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC +- * Copyright(c) 2002-2007 Neterion Inc. +- +- * This software may be used and distributed according to the terms of +- * the GNU General Public License (GPL), incorporated herein by reference. +- * Drivers based on or derived from this code fall under the GPL and must +- * retain the authorship, copyright and license notice. This file is not +- * a complete program and may only be used when the entire operating +- * system is licensed under the GPL. +- * See the file COPYING in this distribution for more information. +- ************************************************************************/ ++/*************************************************************************** ++ * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC * ++ * Copyright(c) 2002-2009 Neterion Inc. * ++ * This software may be used and distributed according to the terms of * ++ * the GNU General Public License (GPL), incorporated herein by reference. * ++ * Drivers based on or derived from this code fall under the GPL and must * ++ * retain the authorship, copyright and license notice. This file is not * ++ * a complete program and may only be used when the entire operating * ++ * system is licensed under the GPL. * ++ * See the file COPYING in this distribution for more information. * ++ ***************************************************************************/ + #ifndef _S2IO_H + #define _S2IO_H + + #define TBD 0 +-#define s2BIT(loc) (0x8000000000000000ULL >> (loc)) ++#define S2BIT(loc) (0x8000000000000000ULL >> (loc)) + #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz)) + #define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff) + +@@ -30,15 +29,26 @@ + #undef SUCCESS + #define SUCCESS 0 + #define FAILURE -1 +-#define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL +-#define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL +-#define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100 + #define S2IO_BIT_RESET 1 + #define S2IO_BIT_SET 2 ++ ++/* Macro to added SNMP support in Driver */ ++#define SNMP_SUPPORT ++ ++#define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL ++#define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL ++#define S2IO_32_BIT_MINUS_ONE 0xFFFFFFFFULL ++#define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100 ++#define S2IO_WAIT_FOR_RESET_MAX 25 ++ + #define CHECKBIT(value, nbit) (value & (1 << nbit)) + + /* Maximum time to flicker LED when asked to identify NIC using ethtool */ + #define MAX_FLICKER_TIME 60000 /* 60 Secs */ ++ ++/* Buffer size for 5 buffer mode */ ++#define MODE5_BUF_SIZE \ ++ (PAGE_SIZE - sizeof(struct skb_shared_info) - 64 - ALIGN_SIZE) + + /* Maximum outstanding splits to be configured into xena. */ + enum { +@@ -55,9 +65,12 @@ + + /* OS concerned variables and constants */ + #define WATCH_DOG_TIMEOUT 15*HZ +-#define EFILL 0x1234 +-#define ALIGN_SIZE 127 +-#define PCIX_COMMAND_REGISTER 0x62 ++#define ALIGN_SIZE 127 ++#define PCIX_COMMAND_REGISTER 0x62 ++ ++#ifndef SET_ETHTOOL_OPS ++#define SUPPORTED_10000baseT_Full (1 << 12) ++#endif + + /* + * Debug related variables. +@@ -70,7 +83,7 @@ + #define INTR_DBG 4 + + /* Global variable that defines the present debug level of the driver. */ +-static int debug_level = ERR_DBG; ++static int debug_level = ERR_DBG; /* Default level. */ + + /* DEBUG message print. */ + #define DBG_PRINT(dbg_level, args...) if(!(debug_level= KERNEL_VERSION(2, 6, 24)) ++#define FIFO_DEFAULT_NUM MAX_TX_FIFOS ++#else ++#define FIFO_DEFAULT_NUM 5 ++#endif ++#else ++#define FIFO_DEFAULT_NUM 5 ++#endif ++ + #define FIFO_UDP_MAX_NUM 2 /* 0 - even, 1 -odd ports */ + #define FIFO_OTHER_MAX_NUM 1 ++#define FIFO_DEFAULT_LEN 1024 + +- +-#define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 ) +-#define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 ) +-#define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 ) + #define MAX_TX_DESC (MAX_AVAILABLE_TXDS) +- +-/* FIFO mappings for all possible number of fifos configured */ +-static int fifo_map[][MAX_TX_FIFOS] = { +- {0, 0, 0, 0, 0, 0, 0, 0}, +- {0, 0, 0, 0, 1, 1, 1, 1}, +- {0, 0, 0, 1, 1, 1, 2, 2}, +- {0, 0, 1, 1, 2, 2, 3, 3}, +- {0, 0, 1, 1, 2, 2, 3, 4}, +- {0, 0, 1, 1, 2, 3, 4, 5}, +- {0, 0, 1, 2, 3, 4, 5, 6}, +- {0, 1, 2, 3, 4, 5, 6, 7}, +-}; +- +-static u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7}; + + /* Maintains Per FIFO related information. */ + struct tx_fifo_config { +-#define MAX_AVAILABLE_TXDS 8192 +- u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */ ++#define MAX_AVAILABLE_TXDS 8192 ++ u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */ + /* Priority definition */ +-#define TX_FIFO_PRI_0 0 /*Highest */ +-#define TX_FIFO_PRI_1 1 +-#define TX_FIFO_PRI_2 2 +-#define TX_FIFO_PRI_3 3 +-#define TX_FIFO_PRI_4 4 +-#define TX_FIFO_PRI_5 5 +-#define TX_FIFO_PRI_6 6 +-#define TX_FIFO_PRI_7 7 /*lowest */ ++#define TX_FIFO_PRI_0 0 /*Highest */ ++#define TX_FIFO_PRI_1 1 ++#define TX_FIFO_PRI_2 2 ++#define TX_FIFO_PRI_3 3 ++#define TX_FIFO_PRI_4 4 ++#define TX_FIFO_PRI_5 5 ++#define TX_FIFO_PRI_6 6 ++#define TX_FIFO_PRI_7 7 /*lowest */ + u8 fifo_priority; /* specifies pointer level for FIFO */ +- /* user should not set twos fifos with same pri */ +- u8 f_no_snoop; +-#define NO_SNOOP_TXD 0x01 +-#define NO_SNOOP_TXD_BUFFER 0x02 +-}; +- ++}____cacheline_aligned; + + /* Maintains per Ring related information */ + struct rx_ring_config { + u32 num_rxd; /*No of RxDs per Rx Ring */ +-#define RX_RING_PRI_0 0 /* highest */ +-#define RX_RING_PRI_1 1 +-#define RX_RING_PRI_2 2 +-#define RX_RING_PRI_3 3 +-#define RX_RING_PRI_4 4 +-#define RX_RING_PRI_5 5 +-#define RX_RING_PRI_6 6 +-#define RX_RING_PRI_7 7 /* lowest */ ++#define RX_RING_PRI_0 0 /* highest */ ++#define RX_RING_PRI_1 1 ++#define RX_RING_PRI_2 2 ++#define RX_RING_PRI_3 3 ++#define RX_RING_PRI_4 4 ++#define RX_RING_PRI_5 5 ++#define RX_RING_PRI_6 6 ++#define RX_RING_PRI_7 7 /* lowest */ + + u8 ring_priority; /*Specifies service priority of ring */ +- /* OSM should not set any two rings with same priority */ +- u8 ring_org; /*Organization of ring */ +-#define RING_ORG_BUFF1 0x01 +-#define RX_RING_ORG_BUFF3 0x03 +-#define RX_RING_ORG_BUFF5 0x05 +- +- u8 f_no_snoop; +-#define NO_SNOOP_RXD 0x01 +-#define NO_SNOOP_RXD_BUFFER 0x02 +-}; ++}____cacheline_aligned; + + /* This structure provides contains values of the tunable parameters + * of the H/W +@@ -431,48 +600,64 @@ + struct config_param { + /* Tx Side */ + u32 tx_fifo_num; /*Number of Tx FIFOs */ +- +- /* 0-No steering, 1-Priority steering, 2-Default fifo map */ +-#define NO_STEERING 0 +-#define TX_PRIORITY_STEERING 0x1 +-#define TX_DEFAULT_STEERING 0x2 + u8 tx_steering_type; + +- u8 fifo_mapping[MAX_TX_FIFOS]; +- struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */ ++ struct tx_fifo_config tx_cfg[MAX_TX_FIFOS];/*Per-Tx FIFO config */ ++ unsigned int tx_bw_percentage[MAX_TX_FIFOS]; ++ + u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */ ++ /* Specifies if Tx Intr is UTILZ or PER_LIST type. */ + u64 tx_intr_type; +-#define INTA 0 +-#define MSI_X 2 ++ ++#define INTA 0 ++#define MSI_X 2 ++#define DEF_MSI_X 99 + u8 intr_type; ++ + u8 napi; +- +- /* Specifies if Tx Intr is UTILZ or PER_LIST type. */ +- + /* Rx Side */ ++ u8 rst_q_stuck; /* flag to check for reset on queue stuck */ + u32 rx_ring_num; /*Number of receive rings */ +-#define MAX_RX_BLOCKS_PER_RING 150 + + struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */ ++ unsigned int rx_bw_percentage[MAX_RX_RINGS]; + +-#define HEADER_ETHERNET_II_802_3_SIZE 14 +-#define HEADER_802_2_SIZE 3 +-#define HEADER_SNAP_SIZE 5 +-#define HEADER_VLAN_SIZE 4 ++#define HEADER_ETHERNET_II_802_3_SIZE 14 ++#define HEADER_802_2_SIZE 3 ++#define HEADER_SNAP_SIZE 5 ++#define HEADER_VLAN_SIZE 4 + +-#define MIN_MTU 46 +-#define MAX_PYLD 1500 +-#define MAX_MTU (MAX_PYLD+18) +-#define MAX_MTU_VLAN (MAX_PYLD+22) +-#define MAX_PYLD_JUMBO 9600 +-#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18) +-#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22) ++#define MIN_MTU 68 ++#define MAX_PYLD 1500 ++#define MAX_MTU (MAX_PYLD+18) ++#define MAX_MTU_VLAN (MAX_PYLD+22) ++#define MAX_PYLD_JUMBO 9600 ++#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18) ++#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22) + u16 bus_speed; ++#define NO_STEERING 0 ++#define PORT_STEERING 0x1 ++#define RTH_STEERING 0x2 ++#define RX_TOS_STEERING 0x3 ++#define RX_VLAN_STEERING 0x4 ++/* The driver assumes a default setting of RTH_STEERING internally and ++ * will enable some rings based on it. ++ * If the user enables rth_steering on the driver load, then the number of ++ * rings enabled will be equal to the number of cpus (max of 8), which can ++ * be overridden by the user. ++ */ ++#define RTH_STEERING_DEFAULT 0x5 ++ u8 rx_steering_type; ++#define MAX_STEERABLE_PORTS 256 ++ int steer_ports[MAX_STEERABLE_PORTS]; ++ int port_type; ++#define SP 2 ++#define DP 1 + int max_mc_addr; /* xena=64 herc=256 */ + int max_mac_addr; /* xena=16 herc=64 */ + int mc_start_offset; /* xena=16 herc=64 */ +- u8 multiq; +-}; ++ u8 vlan_tag_strip; ++}____cacheline_aligned; + + /* Structure representing MAC Addrs */ + struct mac_addr { +@@ -486,44 +671,45 @@ + u64 TxDL_Pointer; + + u64 List_Control; +-#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8) +-#define TX_FIFO_FIRST_LIST s2BIT(14) +-#define TX_FIFO_LAST_LIST s2BIT(15) +-#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2) +-#define TX_FIFO_SPECIAL_FUNC s2BIT(23) +-#define TX_FIFO_DS_NO_SNOOP s2BIT(31) +-#define TX_FIFO_BUFF_NO_SNOOP s2BIT(30) ++#define TX_FIFO_LAST_TXD_NUM(val) vBIT(val, 0, 8) ++#define TX_FIFO_FIRST_LIST S2BIT(14) ++#define TX_FIFO_LAST_LIST S2BIT(15) ++#define TX_FIFO_FIRSTNLAST_LIST vBIT(3, 14, 2) ++#define TX_FIFO_SPECIAL_FUNC S2BIT(23) ++#define TX_FIFO_DS_NO_SNOOP S2BIT(31) ++#define TX_FIFO_BUFF_NO_SNOOP S2BIT(30) + }; + + /* Tx descriptor structure */ + struct TxD { + u64 Control_1; + /* bit mask */ +-#define TXD_LIST_OWN_XENA s2BIT(7) +-#define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15)) +-#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE)) +-#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12) +-#define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23)) +-#define TXD_GATHER_CODE_FIRST s2BIT(22) +-#define TXD_GATHER_CODE_LAST s2BIT(23) +-#define TXD_TCP_LSO_EN s2BIT(30) +-#define TXD_UDP_COF_EN s2BIT(31) +-#define TXD_UFO_EN s2BIT(31) | s2BIT(30) +-#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14) +-#define TXD_UFO_MSS(val) vBIT(val,34,14) +-#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16) ++#define TXD_LIST_OWN_XENA S2BIT(7) ++#define TXD_T_CODE (S2BIT(12)|S2BIT(13)|\ ++ S2BIT(14)|S2BIT(15)) ++#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE)) ++#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE) >> 48) ++#define TXD_GATHER_CODE (S2BIT(22) | S2BIT(23)) ++#define TXD_GATHER_CODE_FIRST S2BIT(22) ++#define TXD_GATHER_CODE_LAST S2BIT(23) ++#define TXD_TCP_LSO_EN S2BIT(30) ++#define TXD_UDP_COF_EN S2BIT(31) ++#define TXD_UFO_EN S2BIT(31) | S2BIT(30) ++#define TXD_TCP_LSO_MSS(val) vBIT(val, 34, 14) ++#define TXD_UFO_MSS(val) vBIT(val, 34, 14) ++#define TXD_BUFFER0_SIZE(val) vBIT(val, 48, 16) + + u64 Control_2; +-#define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7)) +-#define TXD_TX_CKO_IPV4_EN s2BIT(5) +-#define TXD_TX_CKO_TCP_EN s2BIT(6) +-#define TXD_TX_CKO_UDP_EN s2BIT(7) +-#define TXD_VLAN_ENABLE s2BIT(15) +-#define TXD_VLAN_TAG(val) vBIT(val,16,16) +-#define TXD_INT_NUMBER(val) vBIT(val,34,6) +-#define TXD_INT_TYPE_PER_LIST s2BIT(47) +-#define TXD_INT_TYPE_UTILZ s2BIT(46) +-#define TXD_SET_MARKER vBIT(0x6,0,4) ++#define TXD_TX_CKO_CONTROL (S2BIT(5)|S2BIT(6)|S2BIT(7)) ++#define TXD_TX_CKO_IPV4_EN S2BIT(5) ++#define TXD_TX_CKO_TCP_EN S2BIT(6) ++#define TXD_TX_CKO_UDP_EN S2BIT(7) ++#define TXD_VLAN_ENABLE S2BIT(15) ++#define TXD_VLAN_TAG(val) vBIT(val, 16, 16) ++#define TXD_INT_NUMBER(val) vBIT(val, 34, 6) ++#define TXD_INT_TYPE_PER_LIST S2BIT(47) ++#define TXD_INT_TYPE_UTILZ S2BIT(46) ++#define TXD_SET_MARKER vBIT(0x6, 0, 4) + + u64 Buffer_Pointer; + u64 Host_Control; /* reserved for host */ +@@ -539,65 +725,112 @@ + struct RxD_t { + u64 Host_Control; /* reserved for host */ + u64 Control_1; +-#define RXD_OWN_XENA s2BIT(7) +-#define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15)) +-#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8) +-#define RXD_FRAME_VLAN_TAG s2BIT(24) +-#define RXD_FRAME_PROTO_IPV4 s2BIT(27) +-#define RXD_FRAME_PROTO_IPV6 s2BIT(28) +-#define RXD_FRAME_IP_FRAG s2BIT(29) +-#define RXD_FRAME_PROTO_TCP s2BIT(30) +-#define RXD_FRAME_PROTO_UDP s2BIT(31) +-#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP) +-#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF) +-#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF) ++#define RXD_OWN_XENA S2BIT(7) ++#define RXD_T_CODE (S2BIT(12)|S2BIT(13)|\ ++ S2BIT(14)|S2BIT(15)) ++#define GET_RXD_T_CODE(val) ((val & RXD_T_CODE) >> 48) ++#define RXD_FRAME_PROTO vBIT(0xFFFF, 24, 8) ++#define RXD_FRAME_VLAN_TAG S2BIT(24) ++#define RXD_FRAME_PROTO_IPV4 S2BIT(27) ++#define RXD_FRAME_PROTO_IPV6 S2BIT(28) ++#define RXD_FRAME_IP_FRAG S2BIT(29) ++#define RXD_FRAME_PROTO_TCP S2BIT(30) ++#define RXD_FRAME_PROTO_UDP S2BIT(31) ++#define RXD_TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | \ ++ RXD_FRAME_PROTO_UDP) ++#define RXD_TCP_IPV4_FRAME (RXD_FRAME_PROTO_IPV4 | \ ++ RXD_FRAME_PROTO_TCP) ++#define RXD_GET_L3_CKSUM(val) ((u16)(val >> 16) & 0xFFFF) ++#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF) + + u64 Control_2; +-#define THE_RXD_MARK 0x3 +-#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2) +-#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62) ++#define THE_RXD_MARK 0x3 ++#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2) ++#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62) + +-#define MASK_VLAN_TAG vBIT(0xFFFF,48,16) +-#define SET_VLAN_TAG(val) vBIT(val,48,16) +-#define SET_NUM_TAG(val) vBIT(val,16,32) ++#define MASK_VLAN_TAG vBIT(0xFFFF, 48, 16) ++#define SET_VLAN_TAG(val) vBIT(val, 48, 16) ++#define SET_NUM_TAG(val) vBIT(val, 16, 32) ++}; + ++#define BUF0_LEN 26 ++#define BUF1_LEN 1 + +-}; + /* Rx descriptor structure for 1 buffer mode */ + struct RxD1 { + struct RxD_t h; + +-#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14) +-#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14) ++#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF, 2, 14) ++#define SET_BUFFER0_SIZE_1(val) vBIT(val, 2, 14) + #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \ + (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48) + u64 Buffer0_ptr; + }; ++ + /* Rx descriptor structure for 3 or 2 buffer mode */ +- + struct RxD3 { + struct RxD_t h; + +-#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14) +-#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16) +-#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16) +-#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8) +-#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16) +-#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16) ++#define MASK_BUFFER0_SIZE_3 vBIT(0xFF, 8, 8) ++#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF, 16, 16) ++#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF, 32, 16) ++#define SET_BUFFER0_SIZE_3(val) vBIT(val, 8, 8) ++#define SET_BUFFER1_SIZE_3(val) vBIT(val, 16, 16) ++#define SET_BUFFER2_SIZE_3(val) vBIT(val, 32, 16) ++ + #define RXD_GET_BUFFER0_SIZE_3(Control_2) \ + (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48) + #define RXD_GET_BUFFER1_SIZE_3(Control_2) \ + (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32) + #define RXD_GET_BUFFER2_SIZE_3(Control_2) \ + (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16) +-#define BUF0_LEN 40 +-#define BUF1_LEN 1 + + u64 Buffer0_ptr; + u64 Buffer1_ptr; + u64 Buffer2_ptr; + }; + ++/* Rx descriptor structure for 5 buffer mode */ ++struct RxD5 { ++#ifdef __BIG_ENDIAN ++ u32 Host_Control; ++ u32 Control_3; ++#else ++ u32 Control_3; ++ u32 Host_Control; ++#endif ++#define MASK_BUFFER3_SIZE_5 vBIT(0xFFFF, 32, 16) ++#define SET_BUFFER3_SIZE_5(val) vBIT(val, 32, 16) ++#define MASK_BUFFER4_SIZE_5 vBIT(0xFFFF, 48, 16) ++#define SET_BUFFER4_SIZE_5(val) vBIT(val, 48, 16) ++ ++#define RXD_GET_BUFFER3_SIZE_5(Control_3) \ ++ (u16)((Control_3 & MASK_BUFFER3_SIZE_5) >> 16) ++#define RXD_GET_BUFFER4_SIZE_5(Control_3) \ ++ (u16)(Control_3 & MASK_BUFFER4_SIZE_5) ++ ++ u64 Control_1; ++ u64 Control_2; ++#define MASK_BUFFER0_SIZE_5 vBIT(0xFFFF, 0, 16) ++#define MASK_BUFFER1_SIZE_5 vBIT(0xFFFF, 16, 16) ++#define MASK_BUFFER2_SIZE_5 vBIT(0xFFFF, 32, 16) ++#define SET_BUFFER0_SIZE_5(val) vBIT(val, 0, 16) ++#define SET_BUFFER1_SIZE_5(val) vBIT(val, 16, 16) ++#define SET_BUFFER2_SIZE_5(val) vBIT(val, 32, 16) ++ ++#define RXD_GET_BUFFER0_SIZE_5(Control_2) \ ++ (u16)((Control_2 & MASK_BUFFER0_SIZE_5) >> 48) ++#define RXD_GET_BUFFER1_SIZE_5(Control_2) \ ++ (u16)((Control_2 & MASK_BUFFER1_SIZE_5) >> 32) ++#define RXD_GET_BUFFER2_SIZE_5(Control_2) \ ++ (u16)((Control_2 & MASK_BUFFER2_SIZE_5) >> 16) ++ ++ u64 Buffer0_ptr; ++ u64 Buffer1_ptr; ++ u64 Buffer2_ptr; ++ u64 Buffer3_ptr; ++ u64 Buffer4_ptr; ++}; + + /* Structure that represents the Rx descriptor block which contains + * 128 Rx descriptors. +@@ -620,12 +853,13 @@ + + #define RXD_MODE_1 0 /* One Buffer mode */ + #define RXD_MODE_3B 1 /* Two Buffer mode */ ++#define RXD_MODE_5 2 /* Five Buffer mode */ + + /* Structure to hold virtual addresses of Buf0 and Buf1 in + * 2buf mode. */ + struct buffAdd { +- void *ba_0_org; +- void *ba_1_org; ++ void *ba_0_org ____cacheline_aligned; ++ void *ba_1_org ____cacheline_aligned; + void *ba_0; + void *ba_1; + }; +@@ -639,14 +873,12 @@ + struct rx_curr_get_info { + u32 block_index; + u32 offset; +- u32 ring_len; +-}; ++}____cacheline_aligned; + + struct rx_curr_put_info { + u32 block_index; + u32 offset; +- u32 ring_len; +-}; ++}____cacheline_aligned; + + /* This structure stores the offset of the TxDl in the FIFO + * from which the Tx Interrupt processor can start picking +@@ -655,17 +887,12 @@ + struct tx_curr_get_info { + u32 offset; + u32 fifo_len; +-}; +- +-struct tx_curr_put_info { +- u32 offset; +- u32 fifo_len; +-}; ++}____cacheline_aligned; + + struct rxd_info { + void *virt_addr; + dma_addr_t dma_addr; +-}; ++}____cacheline_aligned; + + /* Structure that holds the Phy and virt addresses of the Blocks */ + struct rx_block_info { +@@ -677,34 +904,86 @@ + /* Data structure to represent a LRO session */ + struct lro { + struct sk_buff *parent; +- struct sk_buff *last_frag; +- u8 *l2h; ++ struct sk_buff *last_frag; + struct iphdr *iph; + struct tcphdr *tcph; + u32 tcp_next_seq; +- __be32 tcp_ack; ++ u32 tcp_ack; ++ u32 cur_tsval; ++ __be32 cur_tsecr; + int total_len; + int frags_len; + int sg_num; + int in_use; +- __be16 window; +- u16 vlan_tag; +- u32 cur_tsval; +- __be32 cur_tsecr; ++ u16 window; ++ u16 vlan_tag; + u8 saw_ts; +-} ____cacheline_aligned; ++}____cacheline_aligned; ++ ++#define MIN_LRO_PACKETS 2 ++#define MAX_LRO_PACKETS 10 ++ ++#define LRO_AGGR_PACKET 1 ++#define LRO_BEG_AGGR 3 ++#define LRO_FLUSH_SESSION 4 ++#define LRO_FLUSH_BOTH 2 ++ ++/* ++ * Interrupt count per 10 milliseconds, ie.., 5000 ints/sec. ++ */ ++#define MAX_INTERRUPT_COUNT 50 + + /* Ring specific structure */ + struct ring_info { +- /* The ring number */ +- int ring_no; ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ /* per-ring atomic ISR counter (used for MSI-X only) */ ++ atomic_t isr_cnt; ++#endif ++ ++ unsigned long interrupt_count; ++ unsigned long jiffies; ++ ++#define MAX_RX_UFC_A 4 ++#define MIN_RX_UFC_A 1 ++ unsigned long ufc_a; ++ unsigned long ufc_b; ++ unsigned long ufc_c; ++ unsigned long ufc_d; ++ ++ unsigned long urange_a; ++ unsigned long urange_b; ++ unsigned long urange_c; ++ ++#define MIN_RX_TIMER_VAL 8 ++ int rx_timer_val; ++ int rx_timer_val_saved; + + /* per-ring buffer counter */ + u32 rx_bufs_left; + +-#define MAX_LRO_SESSIONS 32 +- struct lro lro0_n[MAX_LRO_SESSIONS]; ++ u8 skbs_per_rxd; ++ ++ struct vlan_group *vlgrp; ++ u8 vlan_strip_flag; ++ u8 rx_steering_type; ++ ++ /* per-ring napi flag*/ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) ++ struct napi_struct napi; ++#endif ++ ++ u8 config_napi; ++ /* The ring number */ ++ int ring_no; ++ ++ u16 lro_max_aggr_per_sess; ++ int rx_csum; ++#define MAX_LRO_SESSIONS 32 ++ struct lro lro0_n[MAX_LRO_SESSIONS]; + u8 lro; ++ u8 aggr_ack; ++ u8 max_pkts_aggr; + + /* copy of sp->rxd_mode flag */ + int rxd_mode; +@@ -721,16 +1000,11 @@ + /* copy of sp->pdev pointer */ + struct pci_dev *pdev; + +- /* Per ring napi struct */ +- struct napi_struct napi; +- +- unsigned long interrupt_count; +- + /* + * Place holders for the virtual and physical addresses of + * all the Rx Blocks + */ +- struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING]; ++ struct rx_block_info *rx_blocks ____cacheline_aligned; + int block_count; + int pkt_cnt; + +@@ -747,24 +1021,34 @@ + struct rx_curr_get_info rx_curr_get_info; + + /* interface MTU value */ +- unsigned mtu; ++ unsigned mtu; + +- /* Buffer Address store. */ ++ /* Buffer Address store. Used for 2 buffer mode. */ + struct buffAdd **ba; ++ ++ /* ++ * On 64 bit platforms for 5 buf mode we need to store the skb pointers, ++ * as we can't save them in RxD Host_Control field which is 32 bit. ++ */ ++ u64 *skbs; + + /* per-Ring statistics */ + unsigned long rx_packets; + unsigned long rx_bytes; +-} ____cacheline_aligned; ++ ++ /* This threshold needs to be greater than 1 */ ++#define PAUSE_STUCK_THRESHOLD 3 ++ /* number of times in a row the queue is stuck */ ++ u8 queue_pause_cnt; ++ u64 prev_rx_packets; ++ ++ /*per-ring ethtool stats*/ ++ struct rxRingStat *rx_ring_stat; ++ ++}____cacheline_aligned; + + /* Fifo specific structure */ + struct fifo_info { +- /* FIFO number */ +- int fifo_no; +- +- /* Maximum TxDs per TxDL */ +- int max_txds; +- + /* Place holder of all the TX List's Phy and Virt addresses. */ + struct list_info_hold *list_info; + +@@ -772,31 +1056,41 @@ + * Current offset within the tx FIFO where driver would write + * new Tx frame + */ +- struct tx_curr_put_info tx_curr_put_info; ++ struct tx_curr_get_info tx_curr_put_info; + + /* + * Current offset within tx FIFO from where the driver would start freeing + * the buffers + */ + struct tx_curr_get_info tx_curr_get_info; ++ ++ spinlock_t tx_lock; + #define FIFO_QUEUE_START 0 + #define FIFO_QUEUE_STOP 1 ++ /* flag used to maintain queue state when MULTIQ is not enabled */ + int queue_state; ++ ++ struct s2io_nic *nic; + + /* copy of sp->dev pointer */ + struct net_device *dev; + +- /* copy of multiq status */ +- u8 multiq; ++ /* FIFO number */ ++ int fifo_no; + +- /* Per fifo lock */ +- spinlock_t tx_lock; ++ /* Maximum TxDs per TxDL */ ++ int max_txds; + +- /* Per fifo UFO in band structure */ ++ /* copy of interrupt type */ ++ u8 intr_type; ++ ++#ifdef NETIF_F_UFO + u64 *ufo_in_band_v; ++#endif ++ /*per-fifo ethtool stats*/ ++ struct txFifoStat *tx_fifo_stat; + +- struct s2io_nic *nic; +-} ____cacheline_aligned; ++}____cacheline_aligned; + + /* Information related to the Tx and Rx FIFOs and Rings of Xena + * is maintained in this structure. +@@ -809,9 +1103,6 @@ + /* Fifo specific structure */ + struct fifo_info fifos[MAX_TX_FIFOS]; + +- /* Save virtual address of TxD page with zero DMA addr(if any) */ +- void *zerodma_virt_addr; +- + /* rx side stuff */ + /* Ring specific structure */ + struct ring_info rings[MAX_RX_RINGS]; +@@ -823,20 +1114,11 @@ + void *stats_mem; /* orignal pointer to allocated mem */ + dma_addr_t stats_mem_phy; /* Physical address of the stat block */ + u32 stats_mem_sz; +- struct stat_block *stats_info; /* Logical address of the stat block */ +-}; ++ struct stat_block *stats_info; /* Logical address of the stat block */ ++}____cacheline_aligned; + +-/* structure representing the user defined MAC addresses */ +-struct usr_addr { +- char addr[ETH_ALEN]; +- int usage_cnt; +-}; + +-/* Default Tunable parameters of the NIC. */ +-#define DEFAULT_FIFO_0_LEN 4096 +-#define DEFAULT_FIFO_1_7_LEN 512 +-#define SMALL_BLK_CNT 30 +-#define LARGE_BLK_CNT 100 ++#define SMALL_BLK_CNT 10 + + /* + * Structure to keep track of the MSI-X vectors and the corresponding +@@ -850,8 +1132,8 @@ + void *arg; + + u8 type; +-#define MSIX_ALARM_TYPE 1 +-#define MSIX_RING_TYPE 2 ++#define MSIX_ALARM_TYPE 1 /* This is used for handling MSI-TX */ ++#define MSIX_RING_TYPE 2 + + u8 in_use; + #define MSIX_REGISTERED_SUCCESS 0xAA +@@ -862,10 +1144,36 @@ + u64 data; + }; + ++/* SPDM related data */ ++#define MAX_SUPPORTED_SPDM_ENTRIES 256 ++struct spdm_entry{ ++ u64 port_n_entry_control_0; ++#define SPDM_PGM_L4_SRC_PORT(port) vBIT(port, 0, 16) ++#define SPDM_PGM_L4_DST_PORT(port) vBIT(port, 16, 16) ++#define SPDM_PGM_TARGET_QUEUE(queue) vBIT(queue, 53, 3) ++#define SPDM_PGM_IS_TCP S2BIT(59) ++#define SPDM_PGM_IS_IPV4 S2BIT(63) ++ ++ union { ++ u64 ipv4_sa_da; ++ u64 ipv6_sa_p0; ++ } ip; ++ u64 ipv6_sa_p1; ++ u64 ipv6_da_p0; ++ u64 ipv6_da_p1; ++ u64 rsvd_3; ++ u64 rsvd_4; ++ ++ u64 hash_n_entry_control_1; ++#define SPDM_PGM_HASH(hash) vBIT(hash, 0, 32) ++#define SPDM_PGM_ENABLE_ENTRY S2BIT(63) ++}; ++ + /* These flags represent the devices temporary state */ + enum s2io_device_state_t + { +- __S2IO_STATE_LINK_TASK=0, ++ __S2IO_STATE_LINK_RESET_TASK = 0, ++ __S2IO_STATE_RESET_CARD, + __S2IO_STATE_CARD_UP + }; + +@@ -873,9 +1181,10 @@ + struct s2io_nic { + int rxd_mode; + /* +- * Count of packets to be processed in a given iteration, it will be indicated +- * by the quota field of the device structure when NAPI is enabled. +- */ ++ * Count of packets to be processed in a given iteration, it will be ++ * indicated by the quota field of the device structure when ++ * NAPI is enabled. ++ */ + int pkts_to_process; + struct net_device *dev; + struct mac_info mac_control; +@@ -883,12 +1192,15 @@ + struct pci_dev *pdev; + void __iomem *bar0; + void __iomem *bar1; +-#define MAX_MAC_SUPPORTED 16 +-#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED + ++ /* Number of skbs allocated for each RxD. Valid only in case of ++ * 5 buffer mode ++ */ + struct mac_addr def_mac_addr[256]; +- + struct net_device_stats stats; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22)) ++ struct net_device_stats prev_stats; ++#endif + int high_dma_flag; + int device_enabled_once; + +@@ -903,14 +1215,20 @@ + #define PROMISC 1 + #define ALL_MULTI 2 + +-#define MAX_ADDRS_SUPPORTED 64 +- u16 usr_addr_count; + u16 mc_addr_count; +- struct usr_addr usr_addrs[256]; + + u16 m_cast_flg; + u16 all_multi_pos; + u16 promisc_flg; ++ ++#define MAX_DTE_CHECK_COUNT 40 ++ int chk_dte_count; ++ ++#define MAX_DEVICE_CHECK_COUNT 5 ++ int chk_device_error_count; ++ ++#define MAX_RX_QUEUE_CHECK_COUNT 10 ++ int chk_rx_queue_count; + + /* Id timer, used to blink NIC to physically identify NIC. */ + struct timer_list id_timer; +@@ -919,16 +1237,28 @@ + * a schedule task that will set the correct Link state once the + * NIC's PHY has stabilized after a state change. + */ ++#ifdef INIT_TQUEUE ++ struct tq_struct rst_timer_task; ++ struct tq_struct set_link_task; ++#else + struct work_struct rst_timer_task; + struct work_struct set_link_task; ++#endif + + /* Flag that can be used to turn on or turn off the Rx checksum + * offload feature. + */ + int rx_csum; + +- /* Below variables are used for fifo selection to transmit a packet */ ++ /* Below variables are used for fifo selection to transmit a packet */ ++ ++ u8 fifo_mapping[MAX_TX_FIFOS]; ++ + u16 fifo_selector[MAX_TX_FIFOS]; ++ ++ /* Calculate the round robin states dynamically */ ++ u64 tx_round_robin_states[5]; ++ u64 rx_round_robin_states[5]; + + /* Total fifos for tcp packets */ + u8 total_tcp_fifos; +@@ -948,50 +1278,79 @@ + */ + u8 other_fifo_idx; + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) + struct napi_struct napi; +- /* after blink, the adapter must be restored with original +- * values. +- */ +- u64 adapt_ctrl_org; ++#endif + + /* Last known link state. */ + u16 last_link_state; + #define LINK_DOWN 1 + #define LINK_UP 2 + +- int task_flag; ++ u8 exec_mode; ++ u8 serious_err; + unsigned long long start_time; ++#ifdef SNMP_SUPPORT ++ char cName[20]; ++ u64 nMemorySize; ++ int nLinkStatus; ++ int nFeature; ++ char cVersion[20]; ++ long lDate; ++#endif + struct vlan_group *vlgrp; +-#define MSIX_FLG 0xA5 ++#define S2IO_INVALID_RING 0xFFFF ++ u16 *vlan_array; ++ u8 vlan_added; ++#define MSIX_FLG 0xA5 ++#ifdef CONFIG_PCI_MSI + int num_entries; + struct msix_entry *entries; + int msi_detected; + wait_queue_head_t msi_wait; ++#endif + struct s2io_msix_entry *s2io_entries; + char desc[MAX_REQUESTED_MSI_X][25]; + +- int avail_msix_vectors; /* No. of MSI-X vectors granted by system */ +- +- struct msix_info_st msix_info[0x3f]; ++ struct msix_info_st msix_info[MAX_REQUESTED_MSI_X]; + + #define XFRAME_I_DEVICE 1 + #define XFRAME_II_DEVICE 2 ++#ifdef TITAN_LEGACY ++#define TITAN_DEVICE 3 ++#endif ++ + u8 device_type; + +- unsigned long clubbed_frms_cnt; +- unsigned long sending_both; +- u8 lro; +- u16 lro_max_aggr_per_sess; ++#define XFRAME_E_DEVICE 4 ++ u8 device_sub_type; ++ ++ u8 lro; ++ u16 lro_max_aggr_per_sess; + volatile unsigned long state; +- u64 general_int_mask; ++ unsigned long long tx_intr_cnt; ++ unsigned long long rx_inta_cnt; ++ u64 general_int_mask; ++ int spdm_entry; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ /* Tx fifo ISR counter (used for MSI-X only) */ ++ atomic_t isr_cnt; ++#endif ++ ++ struct xpakStat *xpak_stat; ++ struct swErrStat *sw_err_stat; ++ struct swDbgStat *sw_dbg_stat; + + #define VPD_STRING_LEN 80 + u8 product_name[VPD_STRING_LEN]; + u8 serial_num[VPD_STRING_LEN]; +-}; ++ u8 vlan_strip_flag; + +-#define RESET_ERROR 1; +-#define CMD_ERROR 2; ++#ifdef RX_ERR_DBG ++int ecc_flag; ++#endif ++ ++}____cacheline_aligned; + + /* OS related system calls */ + #ifndef readq +@@ -1030,10 +1389,10 @@ + writel((u32) (val), addr); + ret = readl(addr); + writel((u32) (val >> 32), (addr + 4)); +- ret = readl(addr + 4); ++ ret = readl((addr + 4)); + } else { + writel((u32) (val >> 32), (addr + 4)); +- ret = readl(addr + 4); ++ ret = readl((addr + 4)); + writel((u32) (val), addr); + ret = readl(addr); + } +@@ -1045,52 +1404,52 @@ + #define DISABLE_INTRS 2 + + /* Highest level interrupt blocks */ +-#define TX_PIC_INTR (0x0001<<0) +-#define TX_DMA_INTR (0x0001<<1) +-#define TX_MAC_INTR (0x0001<<2) +-#define TX_XGXS_INTR (0x0001<<3) +-#define TX_TRAFFIC_INTR (0x0001<<4) +-#define RX_PIC_INTR (0x0001<<5) +-#define RX_DMA_INTR (0x0001<<6) +-#define RX_MAC_INTR (0x0001<<7) +-#define RX_XGXS_INTR (0x0001<<8) +-#define RX_TRAFFIC_INTR (0x0001<<9) +-#define MC_INTR (0x0001<<10) +-#define ENA_ALL_INTRS ( TX_PIC_INTR | \ +- TX_DMA_INTR | \ +- TX_MAC_INTR | \ +- TX_XGXS_INTR | \ +- TX_TRAFFIC_INTR | \ +- RX_PIC_INTR | \ +- RX_DMA_INTR | \ +- RX_MAC_INTR | \ +- RX_XGXS_INTR | \ +- RX_TRAFFIC_INTR | \ +- MC_INTR ) ++#define TX_PIC_INTR (0x0001<<0) ++#define TX_DMA_INTR (0x0001<<1) ++#define TX_MAC_INTR (0x0001<<2) ++#define TX_XGXS_INTR (0x0001<<3) ++#define TX_TRAFFIC_INTR (0x0001<<4) ++#define RX_PIC_INTR (0x0001<<5) ++#define RX_DMA_INTR (0x0001<<6) ++#define RX_MAC_INTR (0x0001<<7) ++#define RX_XGXS_INTR (0x0001<<8) ++#define RX_TRAFFIC_INTR (0x0001<<9) ++#define MC_INTR (0x0001<<10) ++#define ENA_ALL_INTRS (TX_PIC_INTR | \ ++ TX_DMA_INTR | \ ++ TX_MAC_INTR | \ ++ TX_XGXS_INTR | \ ++ TX_TRAFFIC_INTR | \ ++ RX_PIC_INTR | \ ++ RX_DMA_INTR | \ ++ RX_MAC_INTR | \ ++ RX_XGXS_INTR | \ ++ RX_TRAFFIC_INTR | \ ++ MC_INTR) + + /* Interrupt masks for the general interrupt mask register */ + #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL + +-#define TXPIC_INT_M s2BIT(0) +-#define TXDMA_INT_M s2BIT(1) +-#define TXMAC_INT_M s2BIT(2) +-#define TXXGXS_INT_M s2BIT(3) +-#define TXTRAFFIC_INT_M s2BIT(8) +-#define PIC_RX_INT_M s2BIT(32) +-#define RXDMA_INT_M s2BIT(33) +-#define RXMAC_INT_M s2BIT(34) +-#define MC_INT_M s2BIT(35) +-#define RXXGXS_INT_M s2BIT(36) +-#define RXTRAFFIC_INT_M s2BIT(40) ++#define TXPIC_INT_M S2BIT(0) ++#define TXDMA_INT_M S2BIT(1) ++#define TXMAC_INT_M S2BIT(2) ++#define TXXGXS_INT_M S2BIT(3) ++#define TXTRAFFIC_INT_M S2BIT(8) ++#define PIC_RX_INT_M S2BIT(32) ++#define RXDMA_INT_M S2BIT(33) ++#define RXMAC_INT_M S2BIT(34) ++#define MC_INT_M S2BIT(35) ++#define RXXGXS_INT_M S2BIT(36) ++#define RXTRAFFIC_INT_M S2BIT(40) + + /* PIC level Interrupts TODO*/ + + /* DMA level Inressupts */ +-#define TXDMA_PFC_INT_M s2BIT(0) +-#define TXDMA_PCC_INT_M s2BIT(2) ++#define TXDMA_PFC_INT_M S2BIT(0) ++#define TXDMA_PCC_INT_M S2BIT(2) + + /* PFC block interrupts */ +-#define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */ ++#define PFC_MISC_ERR_1 S2BIT(0) /* FIFO full Interrupt */ + + /* PCC block interrupts. */ + #define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate +@@ -1107,67 +1466,192 @@ + static void free_shared_mem(struct s2io_nic *sp); + static int init_nic(struct s2io_nic *nic); + static int rx_intr_handler(struct ring_info *ring_data, int budget); ++static void tx_intr_handler(struct fifo_info *fifo_data); + static void s2io_txpic_intr_handle(struct s2io_nic *sp); +-static void tx_intr_handler(struct fifo_info *fifo_data); +-static void s2io_handle_errors(void * dev_id); +- ++static void s2io_handle_errors(void *dev_id); + static int s2io_starter(void); + static void s2io_closer(void); + static void s2io_tx_watchdog(struct net_device *dev); + static void s2io_set_multicast(struct net_device *dev); +-static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp); +-static void s2io_link(struct s2io_nic * sp, int link); +-static void s2io_reset(struct s2io_nic * sp); ++static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t *rxdp); ++static void s2io_link(struct s2io_nic *sp, int link); ++static void s2io_reset(struct s2io_nic *sp); ++#if defined(HAVE_NETDEV_POLL) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) + static int s2io_poll_msix(struct napi_struct *napi, int budget); + static int s2io_poll_inta(struct napi_struct *napi, int budget); +-static void s2io_init_pci(struct s2io_nic * sp); ++#else ++static int s2io_poll(struct net_device *dev, int *budget); ++#endif ++#endif ++static void s2io_init_pci(struct s2io_nic *sp); + static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr); + static void s2io_alarm_handle(unsigned long data); ++#ifndef SET_ETHTOOL_OPS ++static int s2io_ethtool(struct net_device *dev, struct ifreq *rq); ++#endif ++#ifdef CONFIG_PCI_MSI ++static void store_xmsi_data(struct s2io_nic *nic); ++static void restore_xmsi_data(struct s2io_nic *nic); ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) + static irqreturn_t +-s2io_msix_ring_handle(int irq, void *dev_id); ++s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs); + static irqreturn_t +-s2io_msix_fifo_handle(int irq, void *dev_id); ++s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs); ++#else ++static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id); ++static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id); ++#endif ++static int s2io_enable_msi_x(struct s2io_nic *nic); ++#endif ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs); ++#else + static irqreturn_t s2io_isr(int irq, void *dev_id); ++#endif + static int verify_xena_quiescence(struct s2io_nic *sp); ++#ifdef SET_ETHTOOL_OPS + static const struct ethtool_ops netdev_ethtool_ops; ++#endif ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++static void s2io_set_link(unsigned long data); ++#else + static void s2io_set_link(struct work_struct *work); +-static int s2io_set_swapper(struct s2io_nic * sp); ++#endif ++static int s2io_set_swapper(struct s2io_nic *sp); + static void s2io_card_down(struct s2io_nic *nic); + static int s2io_card_up(struct s2io_nic *nic); +-static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit, +- int bit_state); +-static int s2io_add_isr(struct s2io_nic * sp); +-static void s2io_rem_isr(struct s2io_nic * sp); ++static int get_xena_rev_id(struct pci_dev *pdev); ++static int spdm_extract_table(void *data, struct s2io_nic *nic); ++static int spdm_configure(struct s2io_nic *nic, struct spdm_cfg *info); ++static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit, ++ int bit_state); ++static int s2io_add_isr(struct s2io_nic *sp); ++static void s2io_rem_isr(struct s2io_nic *sp); ++#ifdef CONFIG_PM ++static int s2io_pm_suspend(struct pci_dev *pdev, pm_message_t state); ++static int s2io_pm_resume(struct pci_dev *pdev); ++#endif + ++#ifdef SNMP_SUPPORT ++ ++#define S2IODIRNAME "S2IO" ++#define BDFILENAME "BDInfo" ++#define PADAPFILENAME "PhyAdap" ++#define ERROR_PROC_DIR -20 ++#define ERROR_PROC_ENTRY -21 ++ ++struct stDrvData { ++ struct stBaseDrv *pBaseDrv; ++}; ++ ++struct stPhyAdap { ++ int m_nIndex; ++ char m_cName[20]; ++}; ++struct stBaseDrv { ++ char m_cName[21]; ++ int m_nStatus; ++ char m_cVersion[21]; ++ int m_nFeature; ++ unsigned long long m_nMemorySize; ++ char m_cDate[21]; ++ int m_nPhyCnt; ++ char m_cPhyIndex[21]; ++ int m_dev_id; ++ int m_ven_id; ++ u32 m_tx_intr_cnt; ++ u32 m_rx_intr_cnt; ++ u32 m_intr_type; ++ u32 m_tx_fifo_num; ++ u32 m_rx_ring_num; ++ int m_rxd_mode; ++ u8 m_lro; ++ u16 m_lro_max_pkts; ++ u8 m_napi; ++ u8 m_rx_steering_type; ++ int m_vlan_tag_strip; ++ int m_rx_csum; ++ int m_tx_csum; ++ int m_sg; ++ int m_ufo; ++ int m_tso; ++ int m_fifo_len; ++ int m_rx_ring_size; ++ int m_rth_bucket_size; ++ u64 m_tx_urng; ++ u64 m_rx_urng; ++ u64 m_tx_ufc; ++ u64 m_rx_ufc; ++ struct stPhyAdap m_stPhyAdap[5]; ++}; ++ ++struct stPhyData { ++ int m_nIndex; ++ unsigned char m_cDesc[20]; ++ int m_nMode; ++ int m_nType; ++ char m_cSpeed[20]; ++ unsigned char m_cPMAC[20]; ++ unsigned char m_cCMAC[20]; ++ int m_nLinkStatus; ++ int m_nPCISlot; ++ int m_nPCIBus; ++ int m_nIRQ; ++ int m_nCollision; ++ int m_nMulticast; ++ ++ unsigned long long m_nRxBytes; ++ unsigned long long m_nRxDropped; ++ unsigned long long m_nRxErrors; ++ unsigned long long m_nRxPackets; ++ unsigned long long m_nTxBytes; ++ unsigned long long m_nTxDropped; ++ unsigned long long m_nTxErrors; ++ unsigned long long m_nTxPackets; ++}; ++ ++static int s2io_bdsnmp_init(struct net_device *dev); ++static void s2io_bdsnmp_rem(struct net_device *dev); ++#endif ++ ++static int s2io_club_tcp_session(struct ring_info *ring, u8 *buffer, u8 **tcp, ++ u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp, u16 vid); ++static void clear_lro_session(struct lro *lro); ++static void queue_rx_frame(struct sk_buff *skb, struct ring_info *ring, ++ u16 vlan_tag); ++static void update_L3L4_header(struct ring_info *ring, struct lro *lro, ++int ring_no); ++static void lro_append_pkt(struct ring_info *ring, struct lro *lro, ++ struct sk_buff *skb, u32 tcp_len, u8 aggr_ack); ++static void amd_8132_update_hyper_tx(u8 set_reset); ++ ++#ifdef CONFIG_PCI_MSI + static void restore_xmsi_data(struct s2io_nic *nic); ++#endif + static void do_s2io_store_unicast_mc(struct s2io_nic *sp); + static void do_s2io_restore_unicast_mc(struct s2io_nic *sp); + static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset); + static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr); +-static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset); ++static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off); + static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr); +- +-static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, +- u8 **tcp, u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp, +- struct s2io_nic *sp); +-static void clear_lro_session(struct lro *lro); +-static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag); +-static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro); +-static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro, +- struct sk_buff *skb, u32 tcp_len); +-static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring); +- ++static void print_static_param_list(struct net_device *dev); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) + static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev, +- pci_channel_state_t state); ++ pci_channel_state_t state); + static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev); + static void s2io_io_resume(struct pci_dev *pdev); +- ++#endif ++#ifdef NETIF_F_GSO + #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size + #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size + #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type ++#endif + ++#ifdef module_param + #define S2IO_PARM_INT(X, def_val) \ + static unsigned int X = def_val;\ + module_param(X , uint, 0); ++#endif + + #endif /* _S2IO_H */ +diff -r c9d7db01a94c drivers/net/s2io/kcompat.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/s2io/kcompat.h Tue Sep 01 16:19:08 2009 +0100 +@@ -0,0 +1,429 @@ ++#ifndef _KCOMPAT_H_ ++#define _KCOMPAT_H_ ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,16)) ++#include ++#endif ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#include ++#else ++#include ++#include ++#endif ++ ++/* VENDOR and DEVICE ID of XENA. */ ++#ifndef PCI_VENDOR_ID_S2IO ++#define PCI_VENDOR_ID_S2IO 0x17D5 ++#define PCI_DEVICE_ID_S2IO_WIN 0x5731 ++#define PCI_DEVICE_ID_S2IO_UNI 0x5831 ++#endif ++ ++#ifndef PCI_DEVICE_ID_HERC_WIN ++#define PCI_DEVICE_ID_HERC_WIN 0x5732 ++#define PCI_DEVICE_ID_HERC_UNI 0x5832 ++#endif ++ ++#ifndef PCI_DEVICE_ID_TITAN ++#define PCI_DEVICE_ID_TITAN_WIN 0x5733 ++#define PCI_DEVICE_ID_TITAN_UNI 0x5833 ++#endif ++ ++#ifndef PCI_DEVICE_ID_AMD_8132_BRIDGE ++#define PCI_DEVICE_ID_AMD_8132_BRIDGE 0x7458 ++#endif ++ ++/* Ethtool related variables and Macros. */ ++#ifndef SET_ETHTOOL_OPS ++static int s2io_ethtool(struct net_device *dev, struct ifreq *rq); ++#define SPEED_10000 10000 ++#endif ++ ++/* ++ * Macros for msleep and msleep_interruptible for kernel versions in which ++ * they are not defined. ++ */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) ) ++#define msleep(x) do { set_current_state(TASK_UNINTERRUPTIBLE); \ ++ schedule_timeout((x * HZ)/1000 + 2); \ ++ } while(0) ++#endif ++ ++#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) ) ++#define proc_net init_net.proc_net ++#endif ++ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9) ) ++#define msleep_interruptible(x) do {set_current_state(TASK_INTERRUPTIBLE); \ ++ schedule_timeout((x * HZ)/1000); \ ++ } while(0) ++#endif ++ ++/* Use pci_name instead of slot_name for kernel versions > 2.4.22 */ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) ) ++#define pci_name(x) ((x)->slot_name) ++#endif ++ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) ++#define pci_dma_sync_single_for_cpu(pdev, dma_addr, len, dir) \ ++ pci_dma_sync_single((pdev), (dma_addr), (len), (dir)) ++ ++#define pci_dma_sync_single_for_device(pdev, dma_addr, len, dir) \ ++ pci_dma_sync_single((pdev), (dma_addr), (len), (dir)) ++#endif ++ ++ ++/* pci_save_state */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10)) ++#define pci_save_state(x,y) pci_save_state(x) ++#endif ++ ++/* pci_restore_state */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10)) ++#define pci_restore_state(x,y) pci_restore_state(x); ++#endif ++ ++/* synchronize_irq */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28)) ++#define s2io_synchronize_irq(x) synchronize_irq() ++#else ++#define s2io_synchronize_irq(x) synchronize_irq(x) ++#endif ++ ++/* pci_dev_put */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) ++#define pci_dev_put(x) ++#endif ++ ++/* Macros to ensure the code is backward compatible with 2.4.x kernels. */ ++#ifndef NET_IP_ALIGN ++#define NET_IP_ALIGN 2 ++#endif ++ ++#ifndef SET_NETDEV_DEV ++#define SET_NETDEV_DEV(a, b) do {} while(0) ++#endif ++ ++#ifndef HAVE_FREE_NETDEV ++#define free_netdev(x) kfree(x) ++#endif ++ ++#ifndef IRQ_RETVAL ++typedef void irqreturn_t; ++#define IRQ_NONE ++#define IRQ_HANDLED ++#define IRQ_RETVAL(x) ++#endif ++ ++#ifdef INIT_TQUEUE ++#define schedule_work schedule_task ++#define flush_scheduled_work flush_scheduled_tasks ++#define INIT_WORK INIT_TQUEUE ++#endif ++ ++#ifndef __iomem ++#define __iomem ++#endif ++ ++#ifndef DMA_64BIT_MASK ++#define DMA_64BIT_MASK 0xffffffffffffffffULL ++#define DMA_32BIT_MASK 0x00000000ffffffffULL ++#endif ++ ++#ifndef S2IO_ALIGN ++#define S2IO_ALIGN(x,a) (((x)+(a)-1)&~((a)-1)) ++#endif ++ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) ++#define GET_SOCK_SLEEP_CALLBACK(sk) sk->sleep ++#define GET_SOCK_SOCKET_DESC(sk) sk->socket ++#else ++#define GET_SOCK_SLEEP_CALLBACK(sk) sk->sk_sleep ++#define GET_SOCK_SOCKET_DESC(sk) sk->sk_socket ++#endif ++ ++#ifndef module_param ++#define S2IO_PARM_INT(X, def_val) \ ++ static unsigned int X = def_val;\ ++ MODULE_PARM(X, "i"); ++#endif ++ ++#ifndef SKB_GSO_TCPV4 ++#define SKB_GSO_TCPV4 0x1 ++#endif ++ ++#ifndef SKB_GSO_UDP ++#define SKB_GSO_UDP 0x2 ++#endif ++ ++#ifndef SKB_GSO_UDPV4 ++#define SKB_GSO_UDPV4 0x2 ++#endif ++ ++#ifndef SKB_GSO_TCPV6 ++#define SKB_GSO_TCPV6 0x10 ++#endif ++ ++#ifndef NETIF_F_GSO ++ ++#ifdef NETIF_F_TSO ++#define s2io_tcp_mss(skb) skb_shinfo(skb)->tso_size ++#else ++#define s2io_tcp_mss(skb) 0 ++#endif ++ ++#ifdef NETIF_F_UFO ++#define s2io_udp_mss(skb) skb_shinfo(skb)->ufo_size ++#else ++#define s2io_udp_mss(skb) 0 ++#endif ++ ++inline int s2io_offload_type(struct sk_buff *skb) ++{ ++#ifdef NETIF_F_TSO ++ if (skb_shinfo(skb)->tso_size) ++ return SKB_GSO_TCPV4; ++#endif ++#ifdef NETIF_F_UFO ++ else if(skb_shinfo(skb)->ufo_size) ++ return SKB_GSO_UDP; ++#endif ++ return 0; ++} ++#endif ++#ifndef NETIF_F_TSO6 ++#define s2io_ethtool_op_get_tso ethtool_op_get_tso ++#define s2io_ethtool_op_set_tso ethtool_op_set_tso ++#endif ++#ifndef IRQF_SHARED ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,15)) ++#undef CONFIG_PM ++#endif ++ ++#ifndef CHECKSUM_PARTIAL ++#define CHECKSUM_PARTIAL CHECKSUM_HW ++#endif ++ ++/* Macros to ensure the code is backward compatible with 2.6.5 kernels. */ ++#ifndef spin_trylock_irqsave ++#define spin_trylock_irqsave(lock, flags) \ ++({ \ ++ local_irq_save(flags); \ ++ spin_trylock(lock) ? \ ++ 1 : ({ local_irq_restore(flags); 0; }); \ ++}) ++ ++#ifndef NETDEV_TX_LOCKED ++#define NETDEV_TX_LOCKED -1 /* driver tx lock was already taken */ ++#endif ++#endif ++ ++#ifndef NETDEV_TX_BUSY ++#define NETDEV_TX_BUSY 1 ++#endif ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21) ++#define S2IO_SKB_INIT_TAIL(frag_list, val) \ ++ skb_reset_tail_pointer(frag_list) ++#else ++#define S2IO_SKB_INIT_TAIL(frag_list, val) \ ++ frag_list->tail = (void *) (unsigned long)val ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) ++#ifndef netdev_alloc_skb ++#define netdev_alloc_skb _s2io_netdev_alloc_skb ++static inline struct sk_buff *_s2io_netdev_alloc_skb(struct net_device *dev, ++ unsigned int length) ++{ ++ /* 16 == NET_PAD_SKB */ ++ struct sk_buff *skb; ++ skb = alloc_skb(length + 16, GFP_ATOMIC); ++ if (likely(skb != NULL)) { ++ skb_reserve(skb, 16); ++ skb->dev = dev; ++ } ++ return skb; ++} ++#endif ++#endif ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)) ++#define S2IO_PCI_FIND_DEVICE(_a, _b, _c) \ ++ pci_find_device(_a, _b, _c) ++#else ++#define S2IO_PCI_FIND_DEVICE(_a, _b, _c) \ ++ pci_get_device(_a, _b, _c) ++#endif ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)) ++#define S2IO_PCI_PUT_DEVICE(_a) ++#else ++#define S2IO_PCI_PUT_DEVICE(_a) \ ++ pci_dev_put(_a) ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)) ++#ifndef __be32 ++#define __be32 u32 ++#endif ++#endif ++ ++inline u16 s2io_get_tx_priority(struct sk_buff *skb, u16 vlan_tag) ++{ ++ u16 ret = 0; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) ++ ret = (skb->priority & 0x7); ++#else ++ if (vlan_tag) ++ ret = ((vlan_tag >> 13) & 0x7); ++ else if (skb->protocol == htons(ETH_P_IP)) { ++ struct iphdr *ip; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)) ++ ip = ip_hdr(skb); ++#else ++ ip = skb->nh.iph; ++#endif ++ ret = ((IPTOS_TOS(ip->tos) >> 1) >> 1); ++ } ++#endif ++ return ret; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) ++#define S2IO_NAPI_ENABLE(napi) napi_enable(napi) ++#define S2IO_NAPI_DISABLE(napi) napi_disable(napi) ++#else ++#define S2IO_NAPI_ENABLE(napi) ++#define S2IO_NAPI_DISABLE(napi) ++#endif ++ ++#ifndef pci_dma_mapping_error ++#define pci_dma_mapping_error s2io_pci_dma_mapping_error ++static inline int s2io_pci_dma_mapping_error(dma_addr_t dma_addr) ++{ ++ return dma_addr == 0; ++} ++#endif ++ ++#ifndef do_div ++#define do_div(n,base) ({ \ ++int __res; \ ++__res = ((unsigned long) n) % (unsigned) base; \ ++n = ((unsigned long) n) / (unsigned) base; \ ++__res; }) ++#endif ++ ++#define TX_PRIORITY_STEERING 0x1 ++#define TX_VLAN_STEERING 0x2 ++#define TX_MULTIQ_STEERING 0x3 ++#define TX_STEERING_DEFAULT 0x4 ++ ++static inline struct net_device *s2io_alloc_etherdev(size_t size, ++ int no_of_fifo, ++ int tx_steering_type) ++{ ++ struct net_device *ndev; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 23)) ++ ndev = alloc_etherdev(size); ++#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23)) && \ ++ (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26))) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ if (tx_steering_type == TX_MULTIQ_STEERING) ++ ndev = alloc_etherdev_mq(size, no_of_fifo); ++ else ++ ndev = alloc_etherdev(size); ++#else ++ ndev = alloc_etherdev(size); ++#endif ++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) ++ if (tx_steering_type == TX_MULTIQ_STEERING) ++ ndev = alloc_etherdev_mq(size, no_of_fifo); ++ else ++ ndev = alloc_etherdev(size); ++#endif ++ return ndev; ++} ++ ++static inline int s2io_netif_subqueue_stopped(struct net_device *dev, ++ struct sk_buff *skb, u16 queue_index) ++{ ++ int ret = 0; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 23)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ ret = netif_subqueue_stopped(dev, queue_index); ++#endif ++#else ++ ret = netif_subqueue_stopped(dev, skb); ++#endif ++ return ret; ++} ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)) ++static inline void *s2io_netdev_priv(struct net_device *dev) ++{ ++ return dev->priv; ++} ++#else ++static inline void *s2io_netdev_priv(struct net_device *dev) ++{ ++ return netdev_priv(dev); ++} ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ++static inline void s2io_netif_do_rx_complete(struct net_device *dev, ++ void *napi) ++{ ++ napi_complete((struct napi_struct *) napi); ++} ++static inline void s2io_netif_do_rx_schedule(struct net_device *dev, ++ void *napi) ++{ ++ napi_schedule((struct napi_struct *) napi); ++} ++#else ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) ++static inline void s2io_netif_do_rx_complete(struct net_device *dev, ++ void *napi) ++{ ++ netif_rx_complete(dev); ++} ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)) ++static inline void s2io_netif_do_rx_complete(struct net_device *dev, ++ void *napi) ++{ ++ netif_rx_complete(dev, (struct napi_struct *) napi); ++} ++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ++static inline void s2io_netif_do_rx_complete(struct net_device *dev, ++ void *napi) ++{ ++ netif_rx_complete((struct napi_struct *) napi); ++} ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) ++static inline void s2io_netif_do_rx_schedule(struct net_device *dev, ++void *napi) ++{ ++netif_rx_schedule(dev); ++} ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)) ++static inline void s2io_netif_do_rx_schedule(struct net_device *dev, ++ void *napi) ++{ ++ netif_rx_schedule(dev, (struct napi_struct *) napi); ++} ++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ++static inline void s2io_netif_do_rx_schedule(struct net_device *dev, ++ void *napi) ++{ ++ netif_rx_schedule((struct napi_struct *) napi); ++} ++#endif ++#endif ++ ++#endif /* _KCOMPAT_H_ */ +diff -r c9d7db01a94c drivers/net/s2io/spdm_cfg.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/s2io/spdm_cfg.h Tue Sep 01 16:19:08 2009 +0100 +@@ -0,0 +1,29 @@ ++/* A SPDM config structure to pass info the driver by user */ ++struct spdm_cfg { ++ unsigned int sip; /* Src IP addr */ ++ unsigned int dip; /* Dst IP addr */ ++ unsigned short sprt; /* Src TCP port */ ++ unsigned short dprt; /* Dst TCP port */ ++ unsigned int t_queue; /*Target Rx Queue for the packet */ ++ unsigned int hash; /* the hash as per jenkin's hash algorithm. */ ++#define SPDM_NO_DATA 0x1 ++#define SPDM_XENA_IF 0x2 ++#define SPDM_HW_UNINITIALIZED 0x3 ++#define SPDM_INCOMPLETE_SOCKET 0x4 ++#define SPDM_TABLE_ACCESS_FAILED 0x5 ++#define SPDM_TABLE_FULL 0x6 ++#define SPDM_TABLE_UNKNOWN_BAR 0x7 ++#define SPDM_TABLE_MALLOC_FAIL 0x8 ++#define SPDM_INVALID_DEVICE 0x9 ++#define SPDM_CONF_SUCCESS 0x0 ++#define SPDM_CLR_SUCCESS 0xA ++#define SPDM_CLR_FAIL 0xB ++#define SPDM_GET_CFG_DATA 0xAA55 ++#define SPDM_GET_CLR_DATA 0xAAA555 ++ int ret; ++#define MAX_SPDM_ENTRIES_SIZE (0x100 * 0x40) ++ unsigned char data[MAX_SPDM_ENTRIES_SIZE]; ++ int data_len; /* Number of entries retrieved */ ++ char dev_name[20]; /* Device name, e.g. eth0, eth1... */ ++}; ++ +diff -r c9d7db01a94c drivers/net/s2io/util.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/s2io/util.h Tue Sep 01 16:19:08 2009 +0100 +@@ -0,0 +1,53 @@ ++struct generalInfo { ++ unsigned long deviceid; ++ unsigned long vendorid; ++ char driver_version[20]; ++ char pci_type[30]; ++ char rth_steering_mask[30]; ++ int intr_type; ++ unsigned long long rx_intr_cnt; ++ unsigned long long tx_intr_cnt; ++ unsigned long rx_msix_intr_cnt[8]; ++ int tx_fifo_num; ++ unsigned long fifo_len[8]; ++ unsigned long long perm_addr; ++ int rx_ring_num; ++ int rxd_mode; ++ int rx_ring_size[8] ; ++ int rth_bucket_size; ++ int lro; ++ int lro_max_pkts; ++ int napi; ++ int rx_steering_type; ++ unsigned char rth_mask; ++ int vlan_tag_strip; ++ int device_type; ++ int mtu; ++ int latency_timer; ++ int rx_csum; ++ int tx_csum; ++ int ufo; ++ int tso; ++ int sg; ++ int pcix_cmd; ++ unsigned long long tx_urng; ++ unsigned long long rx_urng; ++ unsigned long long tx_ufc; ++ unsigned long long rx_ufc; ++}; ++struct ioctlInfo { ++ unsigned long long value; ++ unsigned long long txbytes; ++ unsigned long long rxbytes; ++ int offset; ++ unsigned char *buffer; ++ unsigned char *buffer1; ++ unsigned char *buffer2; ++ unsigned char *buffer3; ++ unsigned char *buffer4; ++ unsigned char *buffer5; ++ unsigned char *buffer6; ++ int size; ++ struct generalInfo ginfo; ++}; ++ diff --git a/master/s2io-2.1.37.18446.patch b/master/s2io-2.1.37.18446.patch new file mode 100644 index 0000000..9623cd9 --- /dev/null +++ b/master/s2io-2.1.37.18446.patch @@ -0,0 +1,12 @@ +diff -urpN a/drivers/net/s2io.c b/drivers/net/s2io.c +--- a/drivers/net/s2io.c 2009-09-04 01:44:57.000000000 +0530 ++++ b/drivers/net/s2io.c 2009-09-04 03:38:27.000000000 +0530 +@@ -153,7 +153,7 @@ + #include "s2io-regs.h" + #include "util.h" + +-#define DRV_VERSION "2.1.37.17590" ++#define DRV_VERSION "2.1.37.18446" + /* S2io Driver name & version. */ + static char s2io_driver_name[] = "Neterion"; + static char s2io_driver_version[] = DRV_VERSION; diff --git a/master/s2io-fix-paths.patch b/master/s2io-fix-paths.patch new file mode 100644 index 0000000..637c5e3 --- /dev/null +++ b/master/s2io-fix-paths.patch @@ -0,0 +1,20 @@ +diff -r fd6ad23a5f6c drivers/net/s2io.c +--- a/drivers/net/s2io.c Tue Sep 01 16:24:02 2009 +0100 ++++ b/drivers/net/s2io.c Tue Sep 01 16:25:04 2009 +0100 +@@ -146,12 +146,12 @@ + #include + + /* local include */ +-#include "spdm_cfg.h" +- +-#include "kcompat.h" ++#include "s2io/spdm_cfg.h" ++ ++#include "s2io/kcompat.h" + #include "s2io.h" + #include "s2io-regs.h" +-#include "util.h" ++#include "s2io/util.h" + + #define DRV_VERSION "2.1.37.17590" + /* S2io Driver name & version. */ diff --git a/master/series b/master/series index 630d3ec..b9c5a62 100644 --- a/master/series +++ b/master/series @@ -10,13 +10,14 @@ build-system-integration.patch # linux-2.6.27.19-5.1.patch linux-2.6.27.23-0.1.1.patch +linux-2.6.27.25-0.1.1.patch +linux-2.6.27.29-0.1.1.patch revert-vbd-cdrom-extensions.patch revert-vbd-packet-extensions.patch revert-vbd-protocol-hack.patch revert-configurable-nr-guest-devices.patch revert-netback-notify-multiple.patch revert-netback-dynirq-accounting.patch -revert-balloon-max-target.patch # # Resynchronise with base 2.6.18-xen tree @@ -46,45 +47,54 @@ revert-linux-2.6.18-xen.hg-582.b29a06ba7a5f # blktap: bugfix and support extende # # Patches which should go to OSS linux-2.6.18-xen tree. # - blktap-dont-count-to-infinity +clts-when-calling-math_state_restore +clear-ts_usedfpu-on-new-threads # # Patches from upstream Linux git tree. -# -git-235c4a59278eb07e61d909f1f0c233733034a8b3.patch # ACPI: EC: Limit workaround for ASUS notebooks even more -git-c6cb0e878446c79f42e7833d7bb69ed6bfbb381f.patch # ACPI: EC: Don't trust ECDT tables from ASUS -git-67fd1a731ff1a990d4da7689909317756e50cb4d.patch # net: Add debug info to track down GSO checksum bug -git-93ff68a55aa92180a765d6c51c3303f6200167a6.patch # PCI: make CPU list affinity visible -git-201de56eb22f1ff3f36804bc70cbff220b50f067.patch # PCI: centralize the capabilities code in probe.c -git-58c3a727cb73b75a9104d295f096cca12959a5a5.patch # PCI: support PCIe ARI capability -git-f19aeb1f3638b7bb4ca21eb361f004fac2bfe259.patch # PCI: Add ability to mmap legacy_io on some platforms -git-8dd7f8036c123296fc4214f9d8810eb485570422.patch # PCI: add support for function level reset -git-8113587c2d14d3be2414190845b2e2617c0aa33b.patch # PCI: fix ARI code to be compatible with mixed ARI/non-ARI systems -git-d3a54014e2a94bd37b7dee5e76e03f7bc4fab49a.patch # PCI: Add legacy_io/mem to all busses -git-6a49d8120021897e139641062236215aac5d220e.patch # PCI: enhance pci_ari_enabled() -git-14add80b5120966fe0659d61815b9e9b4b68fdc5.patch # PCI: remove unnecessary arg of pci_update_resource() +# Include output of "git describe " in second column and order based on this entry +# +git-93ff68a55aa92180a765d6c51c3303f6200167a6.patch # v2.6.27-6037-g93ff68a PCI: make CPU list affinity visible +git-201de56eb22f1ff3f36804bc70cbff220b50f067.patch # v2.6.27-6050-g201de56 PCI: centralize the capabilities code in probe.c +git-58c3a727cb73b75a9104d295f096cca12959a5a5.patch # v2.6.27-6051-g58c3a72 PCI: support PCIe ARI capability +git-f19aeb1f3638b7bb4ca21eb361f004fac2bfe259.patch # v2.6.27-6053-gf19aeb1 PCI: Add ability to mmap legacy_io on some platforms +git-8dd7f8036c123296fc4214f9d8810eb485570422.patch # v2.6.27-6516-g8dd7f80 PCI: add support for function level reset +git-8113587c2d14d3be2414190845b2e2617c0aa33b.patch # v2.6.27-7322-g8113587 PCI: fix ARI code to be compatible with mixed ARI/non-ARI systems + +git-d3a54014e2a94bd37b7dee5e76e03f7bc4fab49a.patch # v2.6.28-6867-gd3a5401 PCI: Add legacy_io/mem to all busses +git-6a49d8120021897e139641062236215aac5d220e.patch # v2.6.28-6909-g6a49d812 PCI: enhance pci_ari_enabled() +git-14add80b5120966fe0659d61815b9e9b4b68fdc5.patch # v2.6.28-6910-g14add80 PCI: remove unnecessary arg of pci_update_resource() git-14add80b5120966fe0659d61815b9e9b4b68fdc5-fixes.patch -git-fde09c6d8f92de0c9f75698a75f0989f2234c517.patch # PCI: define PCI resource names in an 'enum' -git-bc5f5a8277cb353161454b6704b3186ebcf3a2a3.patch # PCI: remove unnecessary condition check in pci_restore_bars() -git-0b400c7ed4d027e02f6231afa39852a2d48e6f25.patch # PCI: export __pci_read_base() -git-3789fa8a2e534523c896a32a9f27f78d52ad7d82.patch # PCI: allow pci_alloc_child_bus() to handle a NULL bridge -git-613e7ed6f72b1a115f7ece8ce1b66cf095de1348.patch # PCI: add a new function to map BAR offsets -git-3fa16fdb48e0d83c2acf46e357548c89891df58b.patch # PCI: cleanup pci_bus_add_devices() -git-876e501ab25dcd683574a5d3d56d8fe450083ed6.patch # PCI: factor pci_bus_add_child() from pci_bus_add_devices() -git-d1b054da8f599905f3c18a218961dcf17f9d5f13.patch # PCI: initialize and release SR-IOV capability -git-8c5cdb6adc6688b9b8fd82ea4a5cf4674dabad79.patch # PCI: restore saved SR-IOV state -git-a28724b0fb909d247229a70761c90bb37b13366a.patch # PCI: reserve bus range for SR-IOV device -git-480b93b7837fb3cf0579a42f4953ac463a5b9e1e.patch # PCI: centralize device setup code -git-dd7cc44d0bcec5e9c42fe52e88dc254ae62eac8d.patch # PCI: add SR-IOV API for Physical Function driver -git-74bb1bcc7dbbc9ddef773bf3395d7ff92aaaad2e.patch # PCI: handle SR-IOV Virtual Function Migration -git-01db4957179c92fda7d9a06e49b7ae56fb7c925b.patch # PCI: document SR-IOV sysfs entries -git-15b49bee3a2b228370194f1b3ebc3db427cc9c94.patch # PCI: manual for SR-IOV user and driver developer -git-898585172fa729513d8636257b44bd1cfd279096.patch # PCI: save and restore PCIe 2.0 registers -git-7eb93b175d4de9438a4b0af3a94a112cb5266944.patch # PCI: SR-IOV quirk for Intel 82576 NIC -git-1b6b8ce2ac372ea1f2065b89228ede105eb68dc5.patch # PCI: only save/restore existent registers in the PCIe capability -git-f79b1b146b52765ee38bfb91bb14eb850fa98017.patch # PCI: use fixed-up device class when configuring device -git-4d135dbee7b0a89e946f7ba284f2b957505a2c3a.patch # PCI: fix SR-IOV function dependency link problem +git-fde09c6d8f92de0c9f75698a75f0989f2234c517.patch # v2.6.28-6911-gfde09c6 PCI: define PCI resource names in an 'enum' +git-bc5f5a8277cb353161454b6704b3186ebcf3a2a3.patch # v2.6.28-6912-gbc5f5a8 PCI: remove unnecessary condition check in pci_restore_bars() +git-0b400c7ed4d027e02f6231afa39852a2d48e6f25.patch # v2.6.28-6913-g0b400c7 PCI: export __pci_read_base() +git-3789fa8a2e534523c896a32a9f27f78d52ad7d82.patch # v2.6.28-6914-g3789fa8 PCI: allow pci_alloc_child_bus() to handle a NULL bridge +git-613e7ed6f72b1a115f7ece8ce1b66cf095de1348.patch # v2.6.28-6915-g613e7ed PCI: add a new function to map BAR offsets +git-3fa16fdb48e0d83c2acf46e357548c89891df58b.patch # v2.6.28-6916-g3fa16fd PCI: cleanup pci_bus_add_devices() +git-876e501ab25dcd683574a5d3d56d8fe450083ed6.patch # v2.6.28-6917-g876e501 PCI: factor pci_bus_add_child() from pci_bus_add_devices() + +git-c6cb0e878446c79f42e7833d7bb69ed6bfbb381f.patch # v2.6.29-rc1-2-gc6cb0e8 ACPI: EC: Don't trust ECDT tables from ASUS +git-67fd1a731ff1a990d4da7689909317756e50cb4d.patch # v2.6.29-rc2-34-g67fd1a7 net: Add debug info to track down GSO checksum bug +git-641cd4cfcdc71ce01535b31cc4d57d59a1fae1fc.patch # v2.6.29-rc7-244-g641cd4c generic-ipi: eliminate WARN_ON()s during oops/panic +git-ffd71da4e3f323b7673b061e6f7e0d0c12dc2b49.patch # v2.6.29-rc7-1130-gffd71dapanic: decrease oops_in_progress only after having done the panic +git-d1b054da8f599905f3c18a218961dcf17f9d5f13.patch # v2.6.29-rc8-280-gd1b054d PCI: initialize and release SR-IOV capability +git-8c5cdb6adc6688b9b8fd82ea4a5cf4674dabad79.patch # v2.6.29-rc8-281-g8c5cdb6 PCI: restore saved SR-IOV state +git-a28724b0fb909d247229a70761c90bb37b13366a.patch # v2.6.29-rc8-282-ga28724b PCI: reserve bus range for SR-IOV device +git-480b93b7837fb3cf0579a42f4953ac463a5b9e1e.patch # v2.6.29-rc8-283-g480b93b PCI: centralize device setup code +git-dd7cc44d0bcec5e9c42fe52e88dc254ae62eac8d.patch # v2.6.29-rc8-284-gdd7cc44 PCI: add SR-IOV API for Physical Function driver +git-74bb1bcc7dbbc9ddef773bf3395d7ff92aaaad2e.patch # v2.6.29-rc8-285-g74bb1bc PCI: handle SR-IOV Virtual Function Migration +git-01db4957179c92fda7d9a06e49b7ae56fb7c925b.patch # v2.6.29-rc8-286-g01db495 PCI: document SR-IOV sysfs entries +git-15b49bee3a2b228370194f1b3ebc3db427cc9c94.patch # v2.6.29-rc8-287-g15b49be PCI: manual for SR-IOV user and driver developer +git-898585172fa729513d8636257b44bd1cfd279096.patch # v2.6.29-rc8-308-g8985851 PCI: save and restore PCIe 2.0 registers +git-7eb93b175d4de9438a4b0af3a94a112cb5266944.patch # v2.6.29-9517-g7eb93b1 PCI: SR-IOV quirk for Intel 82576 NIC + +git-1b6b8ce2ac372ea1f2065b89228ede105eb68dc5.patch # v2.6.30-rc3-8-g1b6b8ce PCI: only save/restore existent registers in the PCIe capability +git-3c598766a2bae1b208470e7cc934ac462561e3cb.patch # v2.6.30-rc5-3-g3c59876 x86: fix percpu_{to,from}_op() +git-f79b1b146b52765ee38bfb91bb14eb850fa98017.patch # v2.6.30-rc8-1-gf79b1b1 PCI: use fixed-up device class when configuring device +git-4d135dbee7b0a89e946f7ba284f2b957505a2c3a.patch # v2.6.30-26-g4d135db PCI: fix SR-IOV function dependency link problem + +git-6ff9c2e7fa8ca63a575792534b63c5092099c286.patch # v2.6.31-rc5-501-g6ff9c2e E100: fix interaction with swiotlb on X86. # # Marker to show that the queue is applied. @@ -112,6 +122,7 @@ pci-ignore CA-14360-loadavg-not-uninterruptible revert-xencons-behaviour kexec-define-vmcore_elf_check_arch_cross.patch +kexec-larger-max-pfn-for-oldmem.patch # # Interrupts and event channels @@ -122,44 +133,54 @@ kexec-define-vmcore_elf_check_arch_cross.patch # # ... Ethernet. -e1000-8.0.13.patch -e1000e-0.5.18.3.patch -igb-1.3.19.3.patch +# ... Intel drivers from http://e1000.sourceforge.net +e1000-8.0.16.patch +e1000e-1.0.2.5.patch +igb-1.3.28.4.patch +git-fa4a7ef36ec834fee1719636b30d2f28f4cb0166.patch # v2.6.29-rc7-1654-gfa4a7ef igb: allow tx of pre-formatted vlan tagged packets ixgb-1.0.135.patch -ixgbe-2.0.34.3.patch +ixgbe-2.0.38.2.patch intel-net-driver-kcompat.patch intel-net-driver-conflicting-names.patch +# ... Broadcom drivers from v12.2.3.1. tg3-3.99d tg3-tune-interrupt-load tg3-build-without-vlan-support.patch -bnx2-1.9.16b +# ... Broadcom drivers from B57BCMCD T5.0.4.2. +bnx2-1.9.20b.patch bnx2-cnic-over-bridge -bnx2x-1.50.8 +bnx2x-1.50.13.patch bnx2x-fix-paths -#cxgb3toe-1.2-xen XXX disabled for 2.6.27-xen port -s2io-2.0.31.12965 -forward-port-s2io.patch +# ... Other third party drivers. +cxgb3-1.3.1.7.patch +s2io-2.1.37.17590.patch +s2io-2-0-27-1.patch +s2io-2.1.37.18446.patch +s2io-fix-paths.patch solarflare-sfc-alternative-configuration-location +vxge-2.0.6.18061.patch +netxen_nic-4.0.50.patch +mlnx_en-1.4.1.patch +mlnx_en-fix-warnings.patch # ... Storage. -open-iscsi-2.0-870.3.patch -open-iscsi-2.0-870.3-2.6.27_compat.patch -open-iscsi-adjust-for-in-kernel-build open-iscsi-gfpkernel.patch -mptlinux-4.19.00.03.patch -mpt2sas-01.255.04.00.patch +mptlinux-4.20.00.01.patch +mpt2sas-02.00.00.00.patch mpt2sas-build-integration.patch +megaraid_sas-v00.00.04.12.patch +megaraid_sas-v00.00.04.12-compile-fix.patch fix-cfq-iscsi-live-lock.patch CA-8809-fix-aio-deadlock -#sata_nv-disable-adma-by-dflt XXX disabled for 2.6.27-xen port. underlying issue fixed in 2.6.27? -bnx2i-1.8.9k +bnx2i-1.8.9n.patch bnx2i-host-params nfs-allow-0-retransmits.patch +cifs-no-tcp-sharing.patch +ibft-find.patch # ... Other. cdrom-sysctl-info.patch export-mlock -intel-hda-2.6.30 # # ParaVirtual Memory Management @@ -183,7 +204,6 @@ CA-7672-blk-shutdown.patch CA-8806-blk-dont-reconnect-on-unplug CA-9002-blktap-plug CA-12483-fix-forced-shutdown-race -blk-fix-sysfs-remove-race CA-14804-fix-block-unplug-retries CA-15586-blkback-close-bdev CA-15999-blkback-pause-unpause @@ -194,6 +214,10 @@ CA-20346-blktap-vma-unmap CA-24267-blkback-unpause CA-24784-resource-leak blkback-pagemap +blkback-pagemap-cleanup.diff +linux-2.6.18-xen.hg-918.71a61b393cdf # blkback: pagemap bug fixes +cleanup-linux-2.6.18-xen.hg-918.71a61b393cdf.diff +CXD-99-gnterr-status.diff blktap2 CA-25742-force-shutdown-tapdisk.diff CA-24604-blktap-kthread-uevent.diff @@ -203,8 +227,16 @@ blkback_multi_page_ring blktap_multi_page_ring forward-port-block-drivers.patch blktap2-forward-port-sysfs.patch +CA-30778-backend-bound-sysfs.diff +blktap-initwait-fix +CA-30953-wild-ptr-deref.diff +CA-32943-wild-ptr-deref.diff +CA-32254-shutdown-closed-backends.diff # ... netback +netback-drop-xen-skb-members.patch +netback-call-skb_checksum_setup-at-receive.patch +netback-force-CHECKSUM_PARTIAL-for-GSO.patch netback-rx-offset netback-tcp-and-ip-in-different-fragments disconnect-netback-on-close @@ -217,13 +249,13 @@ netback-workaround-bad-csums netback-linearise-skbs netback-defensive.patch netback-thread -netback-fix-receive-checksum-setup.patch # ... pciback pciback-flr remove-release-flr flr-change-sbr-d3r-lists export-pci_walk_bus.patch +pciback-flr-82599 # # ParaVirtual Frontend Drivers. @@ -248,6 +280,7 @@ watch_online_node # Kernel Configuration. # config-create_config-script +increase-maximum-number-of-loop-devices utility-guest create_config.sh-x86_64-sane-default increase-nr-dynirq @@ -277,9 +310,8 @@ privcmd_memop # # Networking. # -vswitch-0.90.1.0.patch +vswitch.patch vswitch-build-integration.patch - bridge-locate-physical-device.patch bonding-balance-slb.patch bonding-default-slb.patch @@ -289,7 +321,6 @@ bonding-balance-slb-fixes.patch bonding-balance-slb-fixes2.patch bonding-balance-slb-fixes3.patch bonding-no-updelay-on-first-active-slave.patch -debug-dump-skb-info-when-invalid bonding-vlan-fixes.patch bridge-no-topology-change-when-no-stp.patch feature-gso-tcpv4-prefix @@ -316,7 +347,6 @@ netchannel2_vmq swiotlb-mem-limit xen-acpi-wmi pass2-driver -on-the-fly-cx-change bridge-carrier blktap2-pause-unpause blktap2-smp-map-unmap diff --git a/master/vswitch-build-integration.patch b/master/vswitch-build-integration.patch index 82c1cbd..baf7005 100644 --- a/master/vswitch-build-integration.patch +++ b/master/vswitch-build-integration.patch @@ -1,8 +1,8 @@ * * * -diff -r 65895242b988 net/Kconfig ---- a/net/Kconfig Wed Jul 01 11:16:09 2009 +0100 -+++ b/net/Kconfig Wed Jul 01 15:02:49 2009 +0100 +diff -r 9af08ce28b7b net/Kconfig +--- a/net/Kconfig Thu Sep 17 09:27:19 2009 +0100 ++++ b/net/Kconfig Thu Sep 17 09:43:07 2009 +0100 @@ -180,6 +180,7 @@ source "net/atm/Kconfig" source "net/802/Kconfig" @@ -11,9 +11,9 @@ diff -r 65895242b988 net/Kconfig source "net/8021q/Kconfig" source "net/decnet/Kconfig" source "net/llc/Kconfig" -diff -r 65895242b988 net/Makefile ---- a/net/Makefile Wed Jul 01 11:16:09 2009 +0100 -+++ b/net/Makefile Wed Jul 01 15:02:49 2009 +0100 +diff -r 9af08ce28b7b net/Makefile +--- a/net/Makefile Thu Sep 17 09:27:19 2009 +0100 ++++ b/net/Makefile Thu Sep 17 09:43:07 2009 +0100 @@ -26,6 +26,7 @@ obj-$(CONFIG_NET_KEY) += key/ obj-$(CONFIG_NET_SCHED) += sched/ @@ -22,40 +22,39 @@ diff -r 65895242b988 net/Makefile obj-$(CONFIG_IPX) += ipx/ obj-$(CONFIG_ATALK) += appletalk/ obj-$(CONFIG_WAN_ROUTER) += wanrouter/ -diff -r 65895242b988 net/vswitch/Kconfig +diff -r 9af08ce28b7b net/vswitch/Kconfig --- /dev/null Thu Jan 01 00:00:00 1970 +0000 -+++ b/net/vswitch/Kconfig Wed Jul 01 15:02:49 2009 +0100 ++++ b/net/vswitch/Kconfig Thu Sep 17 09:43:07 2009 +0100 @@ -0,0 +1,5 @@ +config VSWITCH + tristate "Nicira vSwitch" + depends on LLC + ---help--- + HELP GOES HERE -diff -r 65895242b988 net/vswitch/Makefile +diff -r 9af08ce28b7b net/vswitch/Makefile --- /dev/null Thu Jan 01 00:00:00 1970 +0000 -+++ b/net/vswitch/Makefile Wed Jul 01 15:02:49 2009 +0100 -@@ -0,0 +1,18 @@ -+EXTRA_CFLAGS += -DVERSION=\"0.90.1\" -+EXTRA_CFLAGS += -DBUILDNR=\"\" -+ ++++ b/net/vswitch/Makefile Thu Sep 17 09:43:07 2009 +0100 +@@ -0,0 +1,17 @@ +obj-$(CONFIG_VSWITCH) += openvswitch_mod.o + +obj-$(CONFIG_VSWITCH) += brcompat_mod.o + -+openvswitch_mod-objs += actions.o \ -+ datapath.o \ -+ dp_dev.o \ -+ dp_notify.o \ -+ flow.o \ -+ table.o ++openvswitch_mod-objs += \ ++ actions.o \ ++ datapath.o \ ++ dp_dev.o \ ++ dp_notify.o \ ++ dp_sysfs_dp.o \ ++ dp_sysfs_if.o \ ++ flow.o \ ++ table.o + -+brcompat_mod-objs += brcompat.o \ -+ brc_procfs.o \ -+ brc_sysfs_dp.o \ -+ brc_sysfs_if.o -diff -r 65895242b988 net/vswitch/brc_procfs.c ---- a/net/vswitch/brc_procfs.c Wed Jul 01 11:16:09 2009 +0100 -+++ b/net/vswitch/brc_procfs.c Wed Jul 01 15:02:49 2009 +0100 ++brcompat_mod-objs += \ ++ brcompat.o \ ++ brc_procfs.o +diff -r 9af08ce28b7b net/vswitch/brc_procfs.c +--- a/net/vswitch/brc_procfs.c Thu Sep 17 09:27:19 2009 +0100 ++++ b/net/vswitch/brc_procfs.c Thu Sep 17 09:43:07 2009 +0100 @@ -13,6 +13,8 @@ #include #include @@ -79,33 +78,9 @@ diff -r 65895242b988 net/vswitch/brc_procfs.c struct proc_dir_entry *brc_lookup_entry(struct proc_dir_entry *de, const char *name) { -diff -r 65895242b988 net/vswitch/brc_sysfs_dp.c ---- a/net/vswitch/brc_sysfs_dp.c Wed Jul 01 11:16:09 2009 +0100 -+++ b/net/vswitch/brc_sysfs_dp.c Wed Jul 01 15:02:49 2009 +0100 -@@ -27,6 +27,8 @@ - #include "brc_sysfs.h" - #include "datapath.h" - #include "dp_dev.h" -+ -+#define NETDEV_DEV_MEMBER dev - - #ifdef CONFIG_SYSFS - #define to_dev(obj) container_of(obj, struct device, kobj) -diff -r 65895242b988 net/vswitch/brc_sysfs_if.c ---- a/net/vswitch/brc_sysfs_if.c Wed Jul 01 11:16:09 2009 +0100 -+++ b/net/vswitch/brc_sysfs_if.c Wed Jul 01 15:02:49 2009 +0100 -@@ -20,6 +20,8 @@ - #include - #include "brc_sysfs.h" - #include "datapath.h" -+ -+#define NETDEV_DEV_MEMBER dev - - #ifdef CONFIG_SYSFS - -diff -r 65895242b988 net/vswitch/compat.h ---- a/net/vswitch/compat.h Wed Jul 01 11:16:09 2009 +0100 -+++ b/net/vswitch/compat.h Wed Jul 01 15:02:49 2009 +0100 +diff -r 9af08ce28b7b net/vswitch/compat.h +--- a/net/vswitch/compat.h Thu Sep 17 09:27:19 2009 +0100 ++++ b/net/vswitch/compat.h Thu Sep 17 09:43:07 2009 +0100 @@ -11,15 +11,4 @@ #include @@ -122,10 +97,22 @@ diff -r 65895242b988 net/vswitch/compat.h - - #endif /* compat.h */ -diff -r 65895242b988 net/vswitch/datapath.h ---- a/net/vswitch/datapath.h Wed Jul 01 11:16:09 2009 +0100 -+++ b/net/vswitch/datapath.h Wed Jul 01 15:02:49 2009 +0100 -@@ -140,13 +140,4 @@ +diff -r 9af08ce28b7b net/vswitch/datapath.c +--- a/net/vswitch/datapath.c Thu Sep 17 09:27:19 2009 +0100 ++++ b/net/vswitch/datapath.c Thu Sep 17 09:43:07 2009 +0100 +@@ -1640,8 +1640,6 @@ + { + int err; + +- printk("Open vSwitch %s, built "__DATE__" "__TIME__"\n", VERSION BUILDNR); +- + err = dp_avoid_bridge_init(); + if (err) + return err; +diff -r 9af08ce28b7b net/vswitch/datapath.h +--- a/net/vswitch/datapath.h Thu Sep 17 09:27:19 2009 +0100 ++++ b/net/vswitch/datapath.h Thu Sep 17 09:43:07 2009 +0100 +@@ -158,15 +158,6 @@ return dp->ports[ODPP_LOCAL]->dev->name; } @@ -138,4 +125,30 @@ diff -r 65895242b988 net/vswitch/datapath.h -} -#endif - + int vswitch_skb_checksum_setup(struct sk_buff *skb); + #endif /* datapath.h */ +diff -r 9af08ce28b7b net/vswitch/dp_sysfs_dp.c +--- a/net/vswitch/dp_sysfs_dp.c Thu Sep 17 09:27:19 2009 +0100 ++++ b/net/vswitch/dp_sysfs_dp.c Thu Sep 17 09:43:07 2009 +0100 +@@ -27,6 +27,8 @@ + #include "dp_sysfs.h" + #include "datapath.h" + #include "dp_dev.h" ++ ++#define NETDEV_DEV_MEMBER dev + + #ifdef CONFIG_SYSFS + #define to_dev(obj) container_of(obj, struct device, kobj) +diff -r 9af08ce28b7b net/vswitch/dp_sysfs_if.c +--- a/net/vswitch/dp_sysfs_if.c Thu Sep 17 09:27:19 2009 +0100 ++++ b/net/vswitch/dp_sysfs_if.c Thu Sep 17 09:43:07 2009 +0100 +@@ -20,6 +20,8 @@ + #include + #include "dp_sysfs.h" + #include "datapath.h" ++ ++#define NETDEV_DEV_MEMBER dev + + #ifdef CONFIG_SYSFS + diff --git a/master/vswitch.patch b/master/vswitch.patch new file mode 100644 index 0000000..42b7c10 --- /dev/null +++ b/master/vswitch.patch @@ -0,0 +1,6774 @@ + +Upstream repository: git://openvswitch.org/openvswitch + +cp -v ../openvswitch.git/include/openflow/*.h include/openflow/ +cp -v ../openvswitch.git/include/openvswitch/*.h include/openvswitch/ +cp -v ../openvswitch.git/datapath/*.[ch] net/vswitch/ +hg add|remove as appropriate. + +diff -r 9dfeb6b4054e include/openflow/nicira-ext.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/include/openflow/nicira-ext.h Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,120 @@ ++/* ++ * Copyright (c) 2008, 2009 Nicira Networks ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at: ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++#ifndef OPENFLOW_NICIRA_EXT_H ++#define OPENFLOW_NICIRA_EXT_H 1 ++ ++#include "openflow/openflow.h" ++ ++#define NICIRA_OUI_STR "002320" ++ ++/* The following vendor extensions, proposed by Nicira Networks, are not yet ++ * ready for standardization (and may never be), so they are not included in ++ * openflow.h. */ ++ ++#define NX_VENDOR_ID 0x00002320 ++ ++enum nicira_type { ++ /* Switch status request. The request body is an ASCII string that ++ * specifies a prefix of the key names to include in the output; if it is ++ * the null string, then all key-value pairs are included. */ ++ NXT_STATUS_REQUEST, ++ ++ /* Switch status reply. The reply body is an ASCII string of key-value ++ * pairs in the form "key=value\n". */ ++ NXT_STATUS_REPLY, ++ ++ /* Configure an action. Most actions do not require configuration ++ * beyond that supplied in the actual action call. */ ++ NXT_ACT_SET_CONFIG, ++ ++ /* Get configuration of action. */ ++ NXT_ACT_GET_CONFIG, ++ ++ /* Remote command execution. The request body is a sequence of strings ++ * delimited by null bytes. The first string is a command name. ++ * Subsequent strings are command arguments. */ ++ NXT_COMMAND_REQUEST, ++ ++ /* Remote command execution reply, sent when the command's execution ++ * completes. The reply body is struct nx_command_reply. */ ++ NXT_COMMAND_REPLY, ++ ++ /* No longer used. */ ++ NXT_FLOW_END_CONFIG__OBSOLETE, ++ ++ /* No longer used. */ ++ NXT_FLOW_END__OBSOLETE, ++ ++ /* Management protocol. See "openflow-mgmt.h". */ ++ NXT_MGMT, ++}; ++ ++struct nicira_header { ++ struct ofp_header header; ++ uint32_t vendor; /* NX_VENDOR_ID. */ ++ uint32_t subtype; /* One of NXT_* above. */ ++}; ++OFP_ASSERT(sizeof(struct nicira_header) == sizeof(struct ofp_vendor_header) + 4); ++ ++ ++enum nx_action_subtype { ++ NXAST_SNAT__OBSOLETE, /* No longer used. */ ++ NXAST_RESUBMIT /* Throw against flow table again. */ ++}; ++ ++/* Action structure for NXAST_RESUBMIT. */ ++struct nx_action_resubmit { ++ uint16_t type; /* OFPAT_VENDOR. */ ++ uint16_t len; /* Length is 8. */ ++ uint32_t vendor; /* NX_VENDOR_ID. */ ++ uint16_t subtype; /* NXAST_RESUBMIT. */ ++ uint16_t in_port; /* New in_port for checking flow table. */ ++ uint8_t pad[4]; ++}; ++OFP_ASSERT(sizeof(struct nx_action_resubmit) == 16); ++ ++/* Header for Nicira-defined actions. */ ++struct nx_action_header { ++ uint16_t type; /* OFPAT_VENDOR. */ ++ uint16_t len; /* Length is 8. */ ++ uint32_t vendor; /* NX_VENDOR_ID. */ ++ uint16_t subtype; /* NXAST_*. */ ++ uint8_t pad[6]; ++}; ++OFP_ASSERT(sizeof(struct nx_action_header) == 16); ++ ++/* Status bits for NXT_COMMAND_REPLY. */ ++enum { ++ NXT_STATUS_EXITED = 1 << 31, /* Exited normally. */ ++ NXT_STATUS_SIGNALED = 1 << 30, /* Exited due to signal. */ ++ NXT_STATUS_UNKNOWN = 1 << 29, /* Exited for unknown reason. */ ++ NXT_STATUS_COREDUMP = 1 << 28, /* Exited with core dump. */ ++ NXT_STATUS_ERROR = 1 << 27, /* Command could not be executed. */ ++ NXT_STATUS_STARTED = 1 << 26, /* Command was started. */ ++ NXT_STATUS_EXITSTATUS = 0xff, /* Exit code mask if NXT_STATUS_EXITED. */ ++ NXT_STATUS_TERMSIG = 0xff, /* Signal number if NXT_STATUS_SIGNALED. */ ++}; ++ ++/* NXT_COMMAND_REPLY. */ ++struct nx_command_reply { ++ struct nicira_header nxh; ++ uint32_t status; /* Status bits defined above. */ ++ /* Followed by any number of bytes of process output. */ ++}; ++OFP_ASSERT(sizeof(struct nx_command_reply) == 20); ++ ++#endif /* openflow/nicira-ext.h */ +diff -r 9dfeb6b4054e include/openflow/openflow-mgmt.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/include/openflow/openflow-mgmt.h Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,260 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at: ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++#ifndef OPENFLOW_OPENFLOW_MGMT_H ++#define OPENFLOW_OPENFLOW_MGMT_H 1 ++ ++#include "openflow/nicira-ext.h" ++ ++enum ofmp_type { ++ OFMPT_CAPABILITY_REQUEST, ++ OFMPT_CAPABILITY_REPLY, ++ OFMPT_RESOURCES_REQUEST, ++ OFMPT_RESOURCES_UPDATE, ++ OFMPT_CONFIG_REQUEST, ++ OFMPT_CONFIG_UPDATE, ++ OFMPT_CONFIG_UPDATE_ACK, ++ OFMPT_ERROR, ++ OFMPT_EXTENDED_DATA ++}; ++ ++/* Header on all OpenFlow management packets. */ ++struct ofmp_header { ++ struct nicira_header header; ++ uint16_t type; /* One of OFMPT_* above. */ ++ uint8_t pad[2]; ++}; ++OFP_ASSERT(sizeof(struct ofmp_header) == sizeof(struct nicira_header) + 4); ++ ++ ++/* Generic TLV header. */ ++struct ofmp_tlv { ++ uint16_t type; /* Type of value (one of OFMPTLV_*). */ ++ uint16_t len; /* Length of TLV (includes this header). */ ++ uint8_t data[0]; /* Value of data as defined by type and length. */ ++}; ++OFP_ASSERT(sizeof(struct ofmp_tlv) == 4); ++ ++/* Universal TLV terminator. Used to indicate end of TLV list. */ ++struct ofmp_tlv_end { ++ uint16_t type; /* Type is 0. */ ++ uint16_t len; /* Length is 4. */ ++}; ++OFP_ASSERT(sizeof(struct ofmp_tlv_end) == 4); ++ ++ ++/* Bitmask of capability description styles. */ ++enum ofmp_capability_format { ++ OFMPCAF_SIMPLE = 0 << 0, /* "ovs-vswitchd.conf" style. */ ++}; ++ ++/* Body of capbility request. ++ * ++ * OFMPT_CAPABILITY_REQUEST (controller -> switch) */ ++struct ofmp_capability_request { ++ struct ofmp_header header; ++ uint32_t format; /* One of OFMPCAF_*. */ ++}; ++OFP_ASSERT(sizeof(struct ofmp_capability_request) == 24); ++ ++/* Body of reply to capability request. ++ * ++ * OFMPT_CAPABILITY_REPLY (switch -> controller). */ ++struct ofmp_capability_reply { ++ struct ofmp_header header; ++ uint32_t format; /* One of OFMPCAF_*. */ ++ uint64_t mgmt_id; /* Management ID. */ ++ uint8_t data[0]; ++}; ++OFP_ASSERT(sizeof(struct ofmp_capability_reply) == 32); ++ ++ ++/* Resource TLV for datapath description. */ ++struct ofmptsr_dp { ++ uint16_t type; /* OFMPTSR_DP. */ ++ uint16_t len; /* 32. */ ++ uint8_t pad[4]; ++ uint64_t dp_id; /* Datapath ID. */ ++ uint8_t name[OFP_MAX_PORT_NAME_LEN]; /* Null-terminated name. */ ++}; ++OFP_ASSERT(sizeof(struct ofmptsr_dp) == 32); ++ ++/* UUIDs will be passed around as *non-terminated* strings in their ++ * canonical form (e.g., 550e8400-e29b-41d4-a716-446655440000). ++ */ ++#define OFMP_UUID_LEN 36 ++ ++/* Resource TLV for XenServer UUIDs associated with this datapath. */ ++struct ofmptsr_dp_uuid { ++ uint16_t type; /* OFMPTSR_DP_UUID. */ ++ uint16_t len; /* Length. */ ++ uint8_t pad[4]; ++ uint64_t dp_id; /* Datapath ID. */ ++ uint8_t uuid_list[0]; /* List of UUIDs associated with ++ * this datapath. */ ++}; ++OFP_ASSERT(sizeof(struct ofmptsr_dp_uuid) == 16); ++ ++/* Resource TLV for XenServer UUID associated with this managment ++ * instance. ++ */ ++struct ofmptsr_mgmt_uuid { ++ uint16_t type; /* OFMPTSR_MGMT_UUID. */ ++ uint16_t len; /* 52. */ ++ uint8_t pad[4]; ++ uint64_t mgmt_id; /* Management ID. */ ++ uint8_t uuid[OFMP_UUID_LEN]; /* System UUID. */ ++ uint8_t pad2[4]; /* Pad for 64-bit systems. */ ++}; ++OFP_ASSERT(sizeof(struct ofmptsr_mgmt_uuid) == 56); ++ ++/* Resource TLV for details about this XenServer vif. */ ++struct ofmptsr_vif { ++ uint16_t type; /* OFMPTSR_VIF. */ ++ uint16_t len; /* 136. */ ++ uint8_t name[OFP_MAX_PORT_NAME_LEN]; /* Null-terminated name. */ ++ uint8_t vif_uuid[OFMP_UUID_LEN]; /* VIF UUID. */ ++ uint8_t vm_uuid[OFMP_UUID_LEN]; /* VM UUID. */ ++ uint8_t net_uuid[OFMP_UUID_LEN]; /* Network UUID. */ ++ uint64_t vif_mac; /* Management ID. */ ++}; ++OFP_ASSERT(sizeof(struct ofmptsr_vif) == 136); ++ ++/* TLV types for switch resource descriptions. */ ++enum ofmp_switch_resources { ++ OFMPTSR_END = 0, /* Terminator. */ ++ OFMPTSR_DP, /* Datapath. */ ++ OFMPTSR_DP_UUID, /* Xen: datapath uuid's. */ ++ OFMPTSR_MGMT_UUID, /* Xen: management uuid. */ ++ OFMPTSR_VIF, /* Xen: vif details. */ ++}; ++ ++/* Body of resources request. ++ * ++ * OFMPT_RESOURCES_REQUEST (controller -> switch) */ ++struct ofmp_resources_request { ++ struct ofmp_header header; ++}; ++ ++/* Body of capbility update. Sent in response to a resources request or ++ * sent asynchronously when resources change on the switch. ++ * ++ * OFMPT_RESOURCES_UPDATE (switch -> controller) */ ++struct ofmp_resources_update { ++ struct ofmp_header header; ++ uint8_t data[0]; ++}; ++OFP_ASSERT(sizeof(struct ofmp_resources_update) == 20); ++ ++ ++/* Bitmask of capability description styles. */ ++enum ofmp_config_format { ++ OFMPCOF_SIMPLE = 0 << 0, /* "ovs-vswitchd.conf" style. */ ++}; ++ ++#define CONFIG_COOKIE_LEN 20 ++ ++/* Body of configuration request. ++ * ++ * OFMPT_CONFIG_REQUEST (controller -> switch) */ ++struct ofmp_config_request { ++ struct ofmp_header header; ++ uint32_t format; /* One of OFMPCOF_*. */ ++}; ++OFP_ASSERT(sizeof(struct ofmp_config_request) == 24); ++ ++/* Body of configuration update. Sent in response to a configuration ++ * request from the controller. May be sent asynchronously by either ++ * the controller or switch to modify configuration or notify of ++ * changes, respectively. If sent by the controller, the switch must ++ * respond with a OFMPT_CONFIG_UPDATE_ACK. ++ * ++ * OFMPT_CONFIG_UPDATE (switch <-> controller) */ ++struct ofmp_config_update { ++ struct ofmp_header header; ++ uint32_t format; /* One of OFMPCOF_*. */ ++ uint8_t cookie[CONFIG_COOKIE_LEN]; /* Cookie of config attempting to be ++ * replaced by this update. */ ++ uint8_t data[0]; ++}; ++OFP_ASSERT(sizeof(struct ofmp_config_update) == 44); ++ ++/* Bitmask of configuration update ack flags. */ ++enum ofmp_config_update_ack_flags { ++ OFMPCUAF_SUCCESS = 1 << 0, /* Config succeeded. */ ++}; ++ ++/* Body of configuration update ack. Sent in response to a configuration ++ * udpate request. ++ * ++ * OFMPT_CONFIG_UPDATE_ACK (switch -> controller) */ ++struct ofmp_config_update_ack { ++ struct ofmp_header header; ++ uint32_t format; /* One of OFMPCOF_*. */ ++ uint32_t flags; /* One of OFMPCUAF_*. */ ++ uint8_t cookie[CONFIG_COOKIE_LEN]; /* Cookie of current configuration ++ * being used in the switch. */ ++}; ++OFP_ASSERT(sizeof(struct ofmp_config_update_ack) == 48); ++ ++/* Values for 'type' in ofmp_error_msg. */ ++enum ofmp_error_type { ++ OFMPET_BAD_CONFIG /* Problem with configuration. */ ++}; ++ ++/* ofmp_error_msg 'code' values for OFMPET_BAD_CONFIG. 'data' contains ++ * at least the first 64 bytes of the failed request. */ ++enum ofmp_bad_config_code { ++ OFMPBCC_BUSY, /* Config updating, try again. */ ++ OFMPBCC_OLD_COOKIE, /* Config has changed. */ ++}; ++ ++/* Body of error message. May be sent by either the switch or the ++ * controller to indicate some error condition. ++ * ++ * OFMPT_ERROR (switch <-> controller) */ ++struct ofmp_error_msg { ++ struct ofmp_header header; ++ ++ uint16_t type; /* One of OFMPET_*. */ ++ uint16_t code; /* Code depending on 'type'. */ ++ uint8_t data[0]; /* Variable-length data. Interpreted based ++ on the type and code. */ ++}; ++OFP_ASSERT(sizeof(struct ofmp_error_msg) == 24); ++ ++/* Bitmask of extended data message flags. */ ++enum ofmp_extended_data_flags { ++ OFMPEDF_MORE_DATA = 1 << 0, /* More data follows. */ ++}; ++ ++/* Body of extended data message. May be sent by either the switch or the ++ * controller to send messages that are greater than 65535 bytes in ++ * length. The OpenFlow transaction id (xid) must be the same for all ++ * the individual OpenFlow messages that make up an extended message. ++ * ++ * OFMPT_EXTENDED_DATA (switch <-> controller) */ ++struct ofmp_extended_data { ++ struct ofmp_header header; ++ ++ uint16_t type; /* Type code of the encapsulated message. */ ++ uint8_t flags; /* One of OFMPEDF_*. */ ++ uint8_t pad; ++ uint8_t data[0]; /* Variable-length data. */ ++}; ++OFP_ASSERT(sizeof(struct ofmp_extended_data) == 24); ++ ++#endif /* openflow/openflow-mgmt.h */ +diff -r 9dfeb6b4054e include/openflow/openflow.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/include/openflow/openflow.h Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,796 @@ ++/* ++ * Copyright (c) 2008, 2009 Nicira Networks. ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at: ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++/* OpenFlow: protocol between controller and datapath. */ ++ ++#ifndef OPENFLOW_OPENFLOW_H ++#define OPENFLOW_OPENFLOW_H 1 ++ ++#ifdef __KERNEL__ ++#include ++#else ++#include ++#endif ++ ++#ifdef SWIG ++#define OFP_ASSERT(EXPR) /* SWIG can't handle OFP_ASSERT. */ ++#elif !defined(__cplusplus) ++/* Build-time assertion for use in a declaration context. */ ++#define OFP_ASSERT(EXPR) \ ++ extern int (*build_assert(void))[ sizeof(struct { \ ++ unsigned int build_assert_failed : (EXPR) ? 1 : -1; })] ++#else /* __cplusplus */ ++#include ++#define OFP_ASSERT BOOST_STATIC_ASSERT ++#endif /* __cplusplus */ ++ ++#ifndef SWIG ++#define OFP_PACKED __attribute__((packed)) ++#else ++#define OFP_PACKED /* SWIG doesn't understand __attribute. */ ++#endif ++ ++/* The most significant bit being set in the version field indicates an ++ * experimental OpenFlow version. ++ */ ++#define OFP_VERSION 0x97 ++ ++#define OFP_MAX_TABLE_NAME_LEN 32 ++#define OFP_MAX_PORT_NAME_LEN 16 ++ ++#define OFP_TCP_PORT 6633 ++#define OFP_SSL_PORT 6633 ++ ++#define OFP_ETH_ALEN 6 /* Bytes in an Ethernet address. */ ++ ++/* Port numbering. Physical ports are numbered starting from 0. */ ++enum ofp_port { ++ /* Maximum number of physical switch ports. */ ++ OFPP_MAX = 0xff00, ++ ++ /* Fake output "ports". */ ++ OFPP_IN_PORT = 0xfff8, /* Send the packet out the input port. This ++ virtual port must be explicitly used ++ in order to send back out of the input ++ port. */ ++ OFPP_TABLE = 0xfff9, /* Perform actions in flow table. ++ NB: This can only be the destination ++ port for packet-out messages. */ ++ OFPP_NORMAL = 0xfffa, /* Process with normal L2/L3 switching. */ ++ OFPP_FLOOD = 0xfffb, /* All physical ports except input port and ++ those disabled by STP. */ ++ OFPP_ALL = 0xfffc, /* All physical ports except input port. */ ++ OFPP_CONTROLLER = 0xfffd, /* Send to controller. */ ++ OFPP_LOCAL = 0xfffe, /* Local openflow "port". */ ++ OFPP_NONE = 0xffff /* Not associated with a physical port. */ ++}; ++ ++enum ofp_type { ++ /* Immutable messages. */ ++ OFPT_HELLO, /* Symmetric message */ ++ OFPT_ERROR, /* Symmetric message */ ++ OFPT_ECHO_REQUEST, /* Symmetric message */ ++ OFPT_ECHO_REPLY, /* Symmetric message */ ++ OFPT_VENDOR, /* Symmetric message */ ++ ++ /* Switch configuration messages. */ ++ OFPT_FEATURES_REQUEST, /* Controller/switch message */ ++ OFPT_FEATURES_REPLY, /* Controller/switch message */ ++ OFPT_GET_CONFIG_REQUEST, /* Controller/switch message */ ++ OFPT_GET_CONFIG_REPLY, /* Controller/switch message */ ++ OFPT_SET_CONFIG, /* Controller/switch message */ ++ ++ /* Asynchronous messages. */ ++ OFPT_PACKET_IN, /* Async message */ ++ OFPT_FLOW_EXPIRED, /* Async message */ ++ OFPT_PORT_STATUS, /* Async message */ ++ ++ /* Controller command messages. */ ++ OFPT_PACKET_OUT, /* Controller/switch message */ ++ OFPT_FLOW_MOD, /* Controller/switch message */ ++ OFPT_PORT_MOD, /* Controller/switch message */ ++ ++ /* Statistics messages. */ ++ OFPT_STATS_REQUEST, /* Controller/switch message */ ++ OFPT_STATS_REPLY /* Controller/switch message */ ++}; ++ ++/* Header on all OpenFlow packets. */ ++struct ofp_header { ++ uint8_t version; /* OFP_VERSION. */ ++ uint8_t type; /* One of the OFPT_ constants. */ ++ uint16_t length; /* Length including this ofp_header. */ ++ uint32_t xid; /* Transaction id associated with this packet. ++ Replies use the same id as was in the request ++ to facilitate pairing. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_header) == 8); ++ ++/* OFPT_HELLO. This message has an empty body, but implementations must ++ * ignore any data included in the body, to allow for future extensions. */ ++struct ofp_hello { ++ struct ofp_header header; ++}; ++ ++#define OFP_DEFAULT_MISS_SEND_LEN 128 ++ ++enum ofp_config_flags { ++ /* Tells datapath to notify the controller of expired flow entries. */ ++ OFPC_SEND_FLOW_EXP = 1 << 0, ++ ++ /* Handling of IP fragments. */ ++ OFPC_FRAG_NORMAL = 0 << 1, /* No special handling for fragments. */ ++ OFPC_FRAG_DROP = 1 << 1, /* Drop fragments. */ ++ OFPC_FRAG_REASM = 2 << 1, /* Reassemble (only if OFPC_IP_REASM set). */ ++ OFPC_FRAG_MASK = 3 << 1 ++}; ++ ++/* Switch configuration. */ ++struct ofp_switch_config { ++ struct ofp_header header; ++ uint16_t flags; /* OFPC_* flags. */ ++ uint16_t miss_send_len; /* Max bytes of new flow that datapath should ++ send to the controller. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_switch_config) == 12); ++ ++/* Capabilities supported by the datapath. */ ++enum ofp_capabilities { ++ OFPC_FLOW_STATS = 1 << 0, /* Flow statistics. */ ++ OFPC_TABLE_STATS = 1 << 1, /* Table statistics. */ ++ OFPC_PORT_STATS = 1 << 2, /* Port statistics. */ ++ OFPC_STP = 1 << 3, /* 802.1d spanning tree. */ ++ OFPC_MULTI_PHY_TX = 1 << 4, /* Supports transmitting through multiple ++ physical interfaces */ ++ OFPC_IP_REASM = 1 << 5 /* Can reassemble IP fragments. */ ++}; ++ ++/* Flags to indicate behavior of the physical port. These flags are ++ * used in ofp_phy_port to describe the current configuration. They are ++ * used in the ofp_port_mod message to configure the port's behavior. ++ */ ++enum ofp_port_config { ++ OFPPC_PORT_DOWN = 1 << 0, /* Port is administratively down. */ ++ ++ OFPPC_NO_STP = 1 << 1, /* Disable 802.1D spanning tree on port. */ ++ OFPPC_NO_RECV = 1 << 2, /* Drop most packets received on port. */ ++ OFPPC_NO_RECV_STP = 1 << 3, /* Drop received 802.1D STP packets. */ ++ OFPPC_NO_FLOOD = 1 << 4, /* Do not include this port when flooding. */ ++ OFPPC_NO_FWD = 1 << 5, /* Drop packets forwarded to port. */ ++ OFPPC_NO_PACKET_IN = 1 << 6 /* Do not send packet-in msgs for port. */ ++}; ++ ++/* Current state of the physical port. These are not configurable from ++ * the controller. ++ */ ++enum ofp_port_state { ++ OFPPS_LINK_DOWN = 1 << 0, /* No physical link present. */ ++ ++ /* The OFPPS_STP_* bits have no effect on switch operation. The ++ * controller must adjust OFPPC_NO_RECV, OFPPC_NO_FWD, and ++ * OFPPC_NO_PACKET_IN appropriately to fully implement an 802.1D spanning ++ * tree. */ ++ OFPPS_STP_LISTEN = 0 << 8, /* Not learning or relaying frames. */ ++ OFPPS_STP_LEARN = 1 << 8, /* Learning but not relaying frames. */ ++ OFPPS_STP_FORWARD = 2 << 8, /* Learning and relaying frames. */ ++ OFPPS_STP_BLOCK = 3 << 8, /* Not part of spanning tree. */ ++ OFPPS_STP_MASK = 3 << 8 /* Bit mask for OFPPS_STP_* values. */ ++}; ++ ++/* Features of physical ports available in a datapath. */ ++enum ofp_port_features { ++ OFPPF_10MB_HD = 1 << 0, /* 10 Mb half-duplex rate support. */ ++ OFPPF_10MB_FD = 1 << 1, /* 10 Mb full-duplex rate support. */ ++ OFPPF_100MB_HD = 1 << 2, /* 100 Mb half-duplex rate support. */ ++ OFPPF_100MB_FD = 1 << 3, /* 100 Mb full-duplex rate support. */ ++ OFPPF_1GB_HD = 1 << 4, /* 1 Gb half-duplex rate support. */ ++ OFPPF_1GB_FD = 1 << 5, /* 1 Gb full-duplex rate support. */ ++ OFPPF_10GB_FD = 1 << 6, /* 10 Gb full-duplex rate support. */ ++ OFPPF_COPPER = 1 << 7, /* Copper medium. */ ++ OFPPF_FIBER = 1 << 8, /* Fiber medium. */ ++ OFPPF_AUTONEG = 1 << 9, /* Auto-negotiation. */ ++ OFPPF_PAUSE = 1 << 10, /* Pause. */ ++ OFPPF_PAUSE_ASYM = 1 << 11 /* Asymmetric pause. */ ++}; ++ ++/* Description of a physical port */ ++struct ofp_phy_port { ++ uint16_t port_no; ++ uint8_t hw_addr[OFP_ETH_ALEN]; ++ uint8_t name[OFP_MAX_PORT_NAME_LEN]; /* Null-terminated */ ++ ++ uint32_t config; /* Bitmap of OFPPC_* flags. */ ++ uint32_t state; /* Bitmap of OFPPS_* flags. */ ++ ++ /* Bitmaps of OFPPF_* that describe features. All bits zeroed if ++ * unsupported or unavailable. */ ++ uint32_t curr; /* Current features. */ ++ uint32_t advertised; /* Features being advertised by the port. */ ++ uint32_t supported; /* Features supported by the port. */ ++ uint32_t peer; /* Features advertised by peer. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_phy_port) == 48); ++ ++/* Switch features. */ ++struct ofp_switch_features { ++ struct ofp_header header; ++ uint64_t datapath_id; /* Datapath unique ID. Only the lower 48-bits ++ are meaningful. */ ++ ++ uint32_t n_buffers; /* Max packets buffered at once. */ ++ ++ uint8_t n_tables; /* Number of tables supported by datapath. */ ++ uint8_t pad[3]; /* Align to 64-bits. */ ++ ++ /* Features. */ ++ uint32_t capabilities; /* Bitmap of support "ofp_capabilities". */ ++ uint32_t actions; /* Bitmap of supported "ofp_action_type"s. */ ++ ++ /* Port info.*/ ++ struct ofp_phy_port ports[0]; /* Port definitions. The number of ports ++ is inferred from the length field in ++ the header. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_switch_features) == 32); ++ ++/* What changed about the physical port */ ++enum ofp_port_reason { ++ OFPPR_ADD, /* The port was added. */ ++ OFPPR_DELETE, /* The port was removed. */ ++ OFPPR_MODIFY /* Some attribute of the port has changed. */ ++}; ++ ++/* A physical port has changed in the datapath */ ++struct ofp_port_status { ++ struct ofp_header header; ++ uint8_t reason; /* One of OFPPR_*. */ ++ uint8_t pad[7]; /* Align to 64-bits. */ ++ struct ofp_phy_port desc; ++}; ++OFP_ASSERT(sizeof(struct ofp_port_status) == 64); ++ ++/* Modify behavior of the physical port */ ++struct ofp_port_mod { ++ struct ofp_header header; ++ uint16_t port_no; ++ uint8_t hw_addr[OFP_ETH_ALEN]; /* The hardware address is not ++ configurable. This is used to ++ sanity-check the request, so it must ++ be the same as returned in an ++ ofp_phy_port struct. */ ++ ++ uint32_t config; /* Bitmap of OFPPC_* flags. */ ++ uint32_t mask; /* Bitmap of OFPPC_* flags to be changed. */ ++ ++ uint32_t advertise; /* Bitmap of "ofp_port_features"s. Zero all ++ bits to prevent any action taking place. */ ++ uint8_t pad[4]; /* Pad to 64-bits. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_port_mod) == 32); ++ ++/* Why is this packet being sent to the controller? */ ++enum ofp_packet_in_reason { ++ OFPR_NO_MATCH, /* No matching flow. */ ++ OFPR_ACTION /* Action explicitly output to controller. */ ++}; ++ ++/* Packet received on port (datapath -> controller). */ ++struct ofp_packet_in { ++ struct ofp_header header; ++ uint32_t buffer_id; /* ID assigned by datapath. */ ++ uint16_t total_len; /* Full length of frame. */ ++ uint16_t in_port; /* Port on which frame was received. */ ++ uint8_t reason; /* Reason packet is being sent (one of OFPR_*) */ ++ uint8_t pad; ++ uint8_t data[0]; /* Ethernet frame, halfway through 32-bit word, ++ so the IP header is 32-bit aligned. The ++ amount of data is inferred from the length ++ field in the header. Because of padding, ++ offsetof(struct ofp_packet_in, data) == ++ sizeof(struct ofp_packet_in) - 2. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_packet_in) == 20); ++ ++enum ofp_action_type { ++ OFPAT_OUTPUT, /* Output to switch port. */ ++ OFPAT_SET_VLAN_VID, /* Set the 802.1q VLAN id. */ ++ OFPAT_SET_VLAN_PCP, /* Set the 802.1q priority. */ ++ OFPAT_STRIP_VLAN, /* Strip the 802.1q header. */ ++ OFPAT_SET_DL_SRC, /* Ethernet source address. */ ++ OFPAT_SET_DL_DST, /* Ethernet destination address. */ ++ OFPAT_SET_NW_SRC, /* IP source address. */ ++ OFPAT_SET_NW_DST, /* IP destination address. */ ++ OFPAT_SET_TP_SRC, /* TCP/UDP source port. */ ++ OFPAT_SET_TP_DST, /* TCP/UDP destination port. */ ++ OFPAT_VENDOR = 0xffff ++}; ++ ++/* Action structure for OFPAT_OUTPUT, which sends packets out 'port'. ++ * When the 'port' is the OFPP_CONTROLLER, 'max_len' indicates the max ++ * number of bytes to send. A 'max_len' of zero means no bytes of the ++ * packet should be sent. */ ++struct ofp_action_output { ++ uint16_t type; /* OFPAT_OUTPUT. */ ++ uint16_t len; /* Length is 8. */ ++ uint16_t port; /* Output port. */ ++ uint16_t max_len; /* Max length to send to controller. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_action_output) == 8); ++ ++/* The VLAN id is 12 bits, so we can use the entire 16 bits to indicate ++ * special conditions. All ones is used to match that no VLAN id was ++ * set. */ ++#define OFP_VLAN_NONE 0xffff ++ ++/* Action structure for OFPAT_SET_VLAN_VID. */ ++struct ofp_action_vlan_vid { ++ uint16_t type; /* OFPAT_SET_VLAN_VID. */ ++ uint16_t len; /* Length is 8. */ ++ uint16_t vlan_vid; /* VLAN id. */ ++ uint8_t pad[2]; ++}; ++OFP_ASSERT(sizeof(struct ofp_action_vlan_vid) == 8); ++ ++/* Action structure for OFPAT_SET_VLAN_PCP. */ ++struct ofp_action_vlan_pcp { ++ uint16_t type; /* OFPAT_SET_VLAN_PCP. */ ++ uint16_t len; /* Length is 8. */ ++ uint8_t vlan_pcp; /* VLAN priority. */ ++ uint8_t pad[3]; ++}; ++OFP_ASSERT(sizeof(struct ofp_action_vlan_vid) == 8); ++ ++/* Action structure for OFPAT_SET_DL_SRC/DST. */ ++struct ofp_action_dl_addr { ++ uint16_t type; /* OFPAT_SET_DL_SRC/DST. */ ++ uint16_t len; /* Length is 16. */ ++ uint8_t dl_addr[OFP_ETH_ALEN]; /* Ethernet address. */ ++ uint8_t pad[6]; ++}; ++OFP_ASSERT(sizeof(struct ofp_action_dl_addr) == 16); ++ ++/* Action structure for OFPAT_SET_NW_SRC/DST. */ ++struct ofp_action_nw_addr { ++ uint16_t type; /* OFPAT_SET_TW_SRC/DST. */ ++ uint16_t len; /* Length is 8. */ ++ uint32_t nw_addr; /* IP address. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_action_nw_addr) == 8); ++ ++/* Action structure for OFPAT_SET_TP_SRC/DST. */ ++struct ofp_action_tp_port { ++ uint16_t type; /* OFPAT_SET_TP_SRC/DST. */ ++ uint16_t len; /* Length is 8. */ ++ uint16_t tp_port; /* TCP/UDP port. */ ++ uint8_t pad[2]; ++}; ++OFP_ASSERT(sizeof(struct ofp_action_tp_port) == 8); ++ ++/* Action header for OFPAT_VENDOR. The rest of the body is vendor-defined. */ ++struct ofp_action_vendor_header { ++ uint16_t type; /* OFPAT_VENDOR. */ ++ uint16_t len; /* Length is a multiple of 8. */ ++ uint32_t vendor; /* Vendor ID, which takes the same form ++ as in "struct ofp_vendor_header". */ ++}; ++OFP_ASSERT(sizeof(struct ofp_action_vendor_header) == 8); ++ ++/* Action header that is common to all actions. The length includes the ++ * header and any padding used to make the action 64-bit aligned. ++ * NB: The length of an action *must* always be a multiple of eight. */ ++struct ofp_action_header { ++ uint16_t type; /* One of OFPAT_*. */ ++ uint16_t len; /* Length of action, including this ++ header. This is the length of action, ++ including any padding to make it ++ 64-bit aligned. */ ++ uint8_t pad[4]; ++}; ++OFP_ASSERT(sizeof(struct ofp_action_header) == 8); ++ ++union ofp_action { ++ uint16_t type; ++ struct ofp_action_header header; ++ struct ofp_action_vendor_header vendor; ++ struct ofp_action_output output; ++ struct ofp_action_vlan_vid vlan_vid; ++ struct ofp_action_vlan_pcp vlan_pcp; ++ struct ofp_action_nw_addr nw_addr; ++ struct ofp_action_tp_port tp_port; ++}; ++OFP_ASSERT(sizeof(union ofp_action) == 8); ++ ++/* Send packet (controller -> datapath). */ ++struct ofp_packet_out { ++ struct ofp_header header; ++ uint32_t buffer_id; /* ID assigned by datapath (-1 if none). */ ++ uint16_t in_port; /* Packet's input port (OFPP_NONE if none). */ ++ uint16_t actions_len; /* Size of action array in bytes. */ ++ struct ofp_action_header actions[0]; /* Actions. */ ++ /* uint8_t data[0]; */ /* Packet data. The length is inferred ++ from the length field in the header. ++ (Only meaningful if buffer_id == -1.) */ ++}; ++OFP_ASSERT(sizeof(struct ofp_packet_out) == 16); ++ ++enum ofp_flow_mod_command { ++ OFPFC_ADD, /* New flow. */ ++ OFPFC_MODIFY, /* Modify all matching flows. */ ++ OFPFC_MODIFY_STRICT, /* Modify entry strictly matching wildcards */ ++ OFPFC_DELETE, /* Delete all matching flows. */ ++ OFPFC_DELETE_STRICT /* Strictly match wildcards and priority. */ ++}; ++ ++/* Flow wildcards. */ ++enum ofp_flow_wildcards { ++ OFPFW_IN_PORT = 1 << 0, /* Switch input port. */ ++ OFPFW_DL_VLAN = 1 << 1, /* VLAN. */ ++ OFPFW_DL_SRC = 1 << 2, /* Ethernet source address. */ ++ OFPFW_DL_DST = 1 << 3, /* Ethernet destination address. */ ++ OFPFW_DL_TYPE = 1 << 4, /* Ethernet frame type. */ ++ OFPFW_NW_PROTO = 1 << 5, /* IP protocol. */ ++ OFPFW_TP_SRC = 1 << 6, /* TCP/UDP source port. */ ++ OFPFW_TP_DST = 1 << 7, /* TCP/UDP destination port. */ ++ ++ /* IP source address wildcard bit count. 0 is exact match, 1 ignores the ++ * LSB, 2 ignores the 2 least-significant bits, ..., 32 and higher wildcard ++ * the entire field. This is the *opposite* of the usual convention where ++ * e.g. /24 indicates that 8 bits (not 24 bits) are wildcarded. */ ++ OFPFW_NW_SRC_SHIFT = 8, ++ OFPFW_NW_SRC_BITS = 6, ++ OFPFW_NW_SRC_MASK = ((1 << OFPFW_NW_SRC_BITS) - 1) << OFPFW_NW_SRC_SHIFT, ++ OFPFW_NW_SRC_ALL = 32 << OFPFW_NW_SRC_SHIFT, ++ ++ /* IP destination address wildcard bit count. Same format as source. */ ++ OFPFW_NW_DST_SHIFT = 14, ++ OFPFW_NW_DST_BITS = 6, ++ OFPFW_NW_DST_MASK = ((1 << OFPFW_NW_DST_BITS) - 1) << OFPFW_NW_DST_SHIFT, ++ OFPFW_NW_DST_ALL = 32 << OFPFW_NW_DST_SHIFT, ++ ++ /* Wildcard all fields. */ ++ OFPFW_ALL = ((1 << 20) - 1) ++}; ++ ++/* The wildcards for ICMP type and code fields use the transport source ++ * and destination port fields, respectively. */ ++#define OFPFW_ICMP_TYPE OFPFW_TP_SRC ++#define OFPFW_ICMP_CODE OFPFW_TP_DST ++ ++/* Values below this cutoff are 802.3 packets and the two bytes ++ * following MAC addresses are used as a frame length. Otherwise, the ++ * two bytes are used as the Ethernet type. ++ */ ++#define OFP_DL_TYPE_ETH2_CUTOFF 0x0600 ++ ++/* Value of dl_type to indicate that the frame does not include an ++ * Ethernet type. ++ */ ++#define OFP_DL_TYPE_NOT_ETH_TYPE 0x05ff ++ ++/* The VLAN id is 12-bits, so we can use the entire 16 bits to indicate ++ * special conditions. All ones indicates that no VLAN id was set. ++ */ ++#define OFP_VLAN_NONE 0xffff ++ ++/* Fields to match against flows */ ++struct ofp_match { ++ uint32_t wildcards; /* Wildcard fields. */ ++ uint16_t in_port; /* Input switch port. */ ++ uint8_t dl_src[OFP_ETH_ALEN]; /* Ethernet source address. */ ++ uint8_t dl_dst[OFP_ETH_ALEN]; /* Ethernet destination address. */ ++ uint16_t dl_vlan; /* Input VLAN. */ ++ uint16_t dl_type; /* Ethernet frame type. */ ++ uint8_t nw_proto; /* IP protocol. */ ++ uint8_t pad; /* Align to 32-bits. */ ++ uint32_t nw_src; /* IP source address. */ ++ uint32_t nw_dst; /* IP destination address. */ ++ uint16_t tp_src; /* TCP/UDP source port. */ ++ uint16_t tp_dst; /* TCP/UDP destination port. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_match) == 36); ++ ++/* The match fields for ICMP type and code use the transport source and ++ * destination port fields, respectively. */ ++#define icmp_type tp_src ++#define icmp_code tp_dst ++ ++/* Value used in "idle_timeout" and "hard_timeout" to indicate that the entry ++ * is permanent. */ ++#define OFP_FLOW_PERMANENT 0 ++ ++/* By default, choose a priority in the middle. */ ++#define OFP_DEFAULT_PRIORITY 0x8000 ++ ++/* Flow setup and teardown (controller -> datapath). */ ++struct ofp_flow_mod { ++ struct ofp_header header; ++ struct ofp_match match; /* Fields to match */ ++ ++ /* Flow actions. */ ++ uint16_t command; /* One of OFPFC_*. */ ++ uint16_t idle_timeout; /* Idle time before discarding (seconds). */ ++ uint16_t hard_timeout; /* Max time before discarding (seconds). */ ++ uint16_t priority; /* Priority level of flow entry. */ ++ uint32_t buffer_id; /* Buffered packet to apply to (or -1). ++ Not meaningful for OFPFC_DELETE*. */ ++ uint16_t out_port; /* For OFPFC_DELETE* commands, require ++ matching entries to include this as an ++ output port. A value of OFPP_NONE ++ indicates no restriction. */ ++ uint8_t pad[2]; /* Align to 32-bits. */ ++ uint32_t reserved; /* Reserved for future use. */ ++ struct ofp_action_header actions[0]; /* The action length is inferred ++ from the length field in the ++ header. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_flow_mod) == 64); ++ ++/* Why did this flow expire? */ ++enum ofp_flow_expired_reason { ++ OFPER_IDLE_TIMEOUT, /* Flow idle time exceeded idle_timeout. */ ++ OFPER_HARD_TIMEOUT /* Time exceeded hard_timeout. */ ++}; ++ ++/* Flow expiration (datapath -> controller). */ ++struct ofp_flow_expired { ++ struct ofp_header header; ++ struct ofp_match match; /* Description of fields. */ ++ ++ uint16_t priority; /* Priority level of flow entry. */ ++ uint8_t reason; /* One of OFPER_*. */ ++ uint8_t pad[1]; /* Align to 32-bits. */ ++ ++ uint32_t duration; /* Time flow was alive in seconds. */ ++ uint8_t pad2[4]; /* Align to 64-bits. */ ++ uint64_t packet_count; ++ uint64_t byte_count; ++}; ++OFP_ASSERT(sizeof(struct ofp_flow_expired) == 72); ++ ++/* Values for 'type' in ofp_error_message. These values are immutable: they ++ * will not change in future versions of the protocol (although new values may ++ * be added). */ ++enum ofp_error_type { ++ OFPET_HELLO_FAILED, /* Hello protocol failed. */ ++ OFPET_BAD_REQUEST, /* Request was not understood. */ ++ OFPET_BAD_ACTION, /* Error in action description. */ ++ OFPET_FLOW_MOD_FAILED, /* Problem modifying flow entry. */ ++ OFPET_PORT_MOD_FAILED /* OFPT_PORT_MOD failed. */ ++}; ++ ++/* ofp_error_msg 'code' values for OFPET_HELLO_FAILED. 'data' contains an ++ * ASCII text string that may give failure details. */ ++enum ofp_hello_failed_code { ++ OFPHFC_INCOMPATIBLE /* No compatible version. */ ++}; ++ ++/* ofp_error_msg 'code' values for OFPET_BAD_REQUEST. 'data' contains at least ++ * the first 64 bytes of the failed request. */ ++enum ofp_bad_request_code { ++ OFPBRC_BAD_VERSION, /* ofp_header.version not supported. */ ++ OFPBRC_BAD_TYPE, /* ofp_header.type not supported. */ ++ OFPBRC_BAD_STAT, /* ofp_stats_request.type not supported. */ ++ OFPBRC_BAD_VENDOR, /* Vendor not supported (in ofp_vendor_header ++ * or ofp_stats_request or ofp_stats_reply). */ ++ OFPBRC_BAD_SUBTYPE, /* Vendor subtype not supported. */ ++ OFPBRC_BAD_LENGTH, /* Wrong request length for type. */ ++ OFPBRC_BUFFER_EMPTY, /* Specified buffer has already been used. */ ++ OFPBRC_BAD_COOKIE /* Specified buffer does not exist. */ ++}; ++ ++/* ofp_error_msg 'code' values for OFPET_BAD_ACTION. 'data' contains at least ++ * the first 64 bytes of the failed request. */ ++enum ofp_bad_action_code { ++ OFPBAC_BAD_TYPE, /* Unknown action type. */ ++ OFPBAC_BAD_LEN, /* Length problem in actions. */ ++ OFPBAC_BAD_VENDOR, /* Unknown vendor id specified. */ ++ OFPBAC_BAD_VENDOR_TYPE, /* Unknown action type for vendor id. */ ++ OFPBAC_BAD_OUT_PORT, /* Problem validating output action. */ ++ OFPBAC_BAD_ARGUMENT, /* Bad action argument. */ ++ OFPBAC_TOO_MANY /* Can't handle this many actions. */ ++}; ++ ++/* ofp_error_msg 'code' values for OFPET_FLOW_MOD_FAILED. 'data' contains ++ * at least the first 64 bytes of the failed request. */ ++enum ofp_flow_mod_failed_code { ++ OFPFMFC_ALL_TABLES_FULL, /* Flow not added because of full tables. */ ++ OFPFMFC_BAD_COMMAND /* Unknown command. */ ++}; ++ ++/* ofp_error_msg 'code' values for OFPET_PORT_MOD_FAILED. 'data' contains ++ * at least the first 64 bytes of the failed request. */ ++enum ofp_port_mod_failed_code { ++ OFPPMFC_BAD_PORT, /* Specified port does not exist. */ ++ OFPPMFC_BAD_HW_ADDR, /* Specified hardware address is wrong. */ ++}; ++ ++/* OFPT_ERROR: Error message (datapath -> controller). */ ++struct ofp_error_msg { ++ struct ofp_header header; ++ ++ uint16_t type; ++ uint16_t code; ++ uint8_t data[0]; /* Variable-length data. Interpreted based ++ on the type and code. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_error_msg) == 12); ++ ++enum ofp_stats_types { ++ /* Description of this OpenFlow switch. ++ * The request body is empty. ++ * The reply body is struct ofp_desc_stats. */ ++ OFPST_DESC, ++ ++ /* Individual flow statistics. ++ * The request body is struct ofp_flow_stats_request. ++ * The reply body is an array of struct ofp_flow_stats. */ ++ OFPST_FLOW, ++ ++ /* Aggregate flow statistics. ++ * The request body is struct ofp_aggregate_stats_request. ++ * The reply body is struct ofp_aggregate_stats_reply. */ ++ OFPST_AGGREGATE, ++ ++ /* Flow table statistics. ++ * The request body is empty. ++ * The reply body is an array of struct ofp_table_stats. */ ++ OFPST_TABLE, ++ ++ /* Physical port statistics. ++ * The request body is empty. ++ * The reply body is an array of struct ofp_port_stats. */ ++ OFPST_PORT, ++ ++ /* Vendor extension. ++ * The request and reply bodies begin with a 32-bit vendor ID, which takes ++ * the same form as in "struct ofp_vendor_header". The request and reply ++ * bodies are otherwise vendor-defined. */ ++ OFPST_VENDOR = 0xffff ++}; ++ ++struct ofp_stats_request { ++ struct ofp_header header; ++ uint16_t type; /* One of the OFPST_* constants. */ ++ uint16_t flags; /* OFPSF_REQ_* flags (none yet defined). */ ++ uint8_t body[0]; /* Body of the request. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_stats_request) == 12); ++ ++enum ofp_stats_reply_flags { ++ OFPSF_REPLY_MORE = 1 << 0 /* More replies to follow. */ ++}; ++ ++struct ofp_stats_reply { ++ struct ofp_header header; ++ uint16_t type; /* One of the OFPST_* constants. */ ++ uint16_t flags; /* OFPSF_REPLY_* flags. */ ++ uint8_t body[0]; /* Body of the reply. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_stats_reply) == 12); ++ ++#define DESC_STR_LEN 256 ++#define SERIAL_NUM_LEN 32 ++/* Body of reply to OFPST_DESC request. Each entry is a NULL-terminated ++ * ASCII string. */ ++struct ofp_desc_stats { ++ char mfr_desc[DESC_STR_LEN]; /* Manufacturer description. */ ++ char hw_desc[DESC_STR_LEN]; /* Hardware description. */ ++ char sw_desc[DESC_STR_LEN]; /* Software description. */ ++ char serial_num[SERIAL_NUM_LEN]; /* Serial number. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_desc_stats) == 800); ++ ++/* Body for ofp_stats_request of type OFPST_FLOW. */ ++struct ofp_flow_stats_request { ++ struct ofp_match match; /* Fields to match. */ ++ uint8_t table_id; /* ID of table to read (from ofp_table_stats) ++ or 0xff for all tables. */ ++ uint8_t pad; /* Align to 32 bits. */ ++ uint16_t out_port; /* Require matching entries to include this ++ as an output port. A value of OFPP_NONE ++ indicates no restriction. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_flow_stats_request) == 40); ++ ++/* Body of reply to OFPST_FLOW request. */ ++struct ofp_flow_stats { ++ uint16_t length; /* Length of this entry. */ ++ uint8_t table_id; /* ID of table flow came from. */ ++ uint8_t pad; ++ struct ofp_match match; /* Description of fields. */ ++ uint32_t duration; /* Time flow has been alive in seconds. */ ++ uint16_t priority; /* Priority of the entry. Only meaningful ++ when this is not an exact-match entry. */ ++ uint16_t idle_timeout; /* Number of seconds idle before expiration. */ ++ uint16_t hard_timeout; /* Number of seconds before expiration. */ ++ uint16_t pad2[3]; /* Pad to 64 bits. */ ++ uint64_t packet_count; /* Number of packets in flow. */ ++ uint64_t byte_count; /* Number of bytes in flow. */ ++ struct ofp_action_header actions[0]; /* Actions. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_flow_stats) == 72); ++ ++/* Body for ofp_stats_request of type OFPST_AGGREGATE. */ ++struct ofp_aggregate_stats_request { ++ struct ofp_match match; /* Fields to match. */ ++ uint8_t table_id; /* ID of table to read (from ofp_table_stats) ++ or 0xff for all tables. */ ++ uint8_t pad; /* Align to 32 bits. */ ++ uint16_t out_port; /* Require matching entries to include this ++ as an output port. A value of OFPP_NONE ++ indicates no restriction. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_aggregate_stats_request) == 40); ++ ++/* Body of reply to OFPST_AGGREGATE request. */ ++struct ofp_aggregate_stats_reply { ++ uint64_t packet_count; /* Number of packets in flows. */ ++ uint64_t byte_count; /* Number of bytes in flows. */ ++ uint32_t flow_count; /* Number of flows. */ ++ uint8_t pad[4]; /* Align to 64 bits. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_aggregate_stats_reply) == 24); ++ ++/* Body of reply to OFPST_TABLE request. */ ++struct ofp_table_stats { ++ uint8_t table_id; /* Identifier of table. Lower numbered tables ++ are consulted first. */ ++ uint8_t pad[3]; /* Align to 32-bits. */ ++ char name[OFP_MAX_TABLE_NAME_LEN]; ++ uint32_t wildcards; /* Bitmap of OFPFW_* wildcards that are ++ supported by the table. */ ++ uint32_t max_entries; /* Max number of entries supported. */ ++ uint32_t active_count; /* Number of active entries. */ ++ uint64_t lookup_count; /* Number of packets looked up in table. */ ++ uint64_t matched_count; /* Number of packets that hit table. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_table_stats) == 64); ++ ++/* Body of reply to OFPST_PORT request. If a counter is unsupported, set ++ * the field to all ones. */ ++struct ofp_port_stats { ++ uint16_t port_no; ++ uint8_t pad[6]; /* Align to 64-bits. */ ++ uint64_t rx_packets; /* Number of received packets. */ ++ uint64_t tx_packets; /* Number of transmitted packets. */ ++ uint64_t rx_bytes; /* Number of received bytes. */ ++ uint64_t tx_bytes; /* Number of transmitted bytes. */ ++ uint64_t rx_dropped; /* Number of packets dropped by RX. */ ++ uint64_t tx_dropped; /* Number of packets dropped by TX. */ ++ uint64_t rx_errors; /* Number of receive errors. This is a super-set ++ of receive errors and should be great than or ++ equal to the sum of all rx_*_err values. */ ++ uint64_t tx_errors; /* Number of transmit errors. This is a super-set ++ of transmit errors. */ ++ uint64_t rx_frame_err; /* Number of frame alignment errors. */ ++ uint64_t rx_over_err; /* Number of packets with RX overrun. */ ++ uint64_t rx_crc_err; /* Number of CRC errors. */ ++ uint64_t collisions; /* Number of collisions. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_port_stats) == 104); ++ ++/* Vendor extension. */ ++struct ofp_vendor_header { ++ struct ofp_header header; /* Type OFPT_VENDOR. */ ++ uint32_t vendor; /* Vendor ID: ++ * - MSB 0: low-order bytes are IEEE OUI. ++ * - MSB != 0: defined by OpenFlow ++ * consortium. */ ++ /* Vendor-defined arbitrary additional data. */ ++}; ++OFP_ASSERT(sizeof(struct ofp_vendor_header) == 12); ++ ++#endif /* openflow/openflow.h */ +diff -r 9dfeb6b4054e include/openvswitch/brcompat-netlink.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/include/openvswitch/brcompat-netlink.h Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,106 @@ ++/* ++ * Copyright (c) 2008, 2009 Nicira Networks. ++ * ++ * This file is offered under your choice of two licenses: Apache 2.0 or GNU ++ * GPL 2.0 or later. The permission statements for each of these licenses is ++ * given below. You may license your modifications to this file under either ++ * of these licenses or both. If you wish to license your modifications under ++ * only one of these licenses, delete the permission text for the other ++ * license. ++ * ++ * ---------------------------------------------------------------------- ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at: ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ * ---------------------------------------------------------------------- ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ---------------------------------------------------------------------- ++ */ ++ ++#ifndef OPENVSWITCH_BRCOMPAT_NETLINK_H ++#define OPENVSWITCH_BRCOMPAT_NETLINK_H 1 ++ ++#define BRC_GENL_FAMILY_NAME "brcompat" ++ ++/* Attributes that can be attached to the datapath's netlink messages. */ ++enum { ++ BRC_GENL_A_UNSPEC, ++ ++ /* ++ * "K:" attributes appear in messages from the kernel to userspace. ++ * "U:" attributes appear in messages from userspace to the kernel. ++ */ ++ ++ /* BRC_GENL_C_DP_ADD, BRC_GENL_C_DP_DEL. */ ++ BRC_GENL_A_DP_NAME, /* K: Datapath name. */ ++ ++ /* BRC_GENL_C_DP_ADD, BRC_GENL_C_DP_DEL, ++ BRC_GENL_C_PORT_ADD, BRC_GENL_C_PORT_DEL. */ ++ BRC_GENL_A_PORT_NAME, /* K: Interface name. */ ++ ++ /* BRC_GENL_C_DP_RESULT. */ ++ BRC_GENL_A_ERR_CODE, /* U: Positive error code. */ ++ ++ /* BRC_GENL_C_QUERY_MC. */ ++ BRC_GENL_A_MC_GROUP, /* K: Generic netlink multicast group. */ ++ ++ /* BRC_GENL_C_SET_PROC. */ ++ BRC_GENL_A_PROC_DIR, /* U: Name of subdirectory in /proc. */ ++ BRC_GENL_A_PROC_NAME, /* U: Name of file in /proc. */ ++ BRC_GENL_A_PROC_DATA, /* U: Contents of file in /proc. */ ++ ++ /* BRC_GENL_C_FDB_QUERY. */ ++ BRC_GENL_A_FDB_COUNT, /* K: Number of FDB entries to read. */ ++ BRC_GENL_A_FDB_SKIP, /* K: Record offset into FDB to start reading. */ ++ ++ /* BRC_GENL_C_DP_RESULT. */ ++ BRC_GENL_A_FDB_DATA, /* U: FDB records. */ ++ BRC_GENL_A_IFINDEXES, /* U: "int" ifindexes of bridges or ports. */ ++ ++ __BRC_GENL_A_MAX, ++ BRC_GENL_A_MAX = __BRC_GENL_A_MAX - 1 ++}; ++ ++/* Commands that can be executed on the datapath's netlink interface. */ ++enum brc_genl_command { ++ BRC_GENL_C_UNSPEC, ++ ++ /* ++ * "K:" messages are sent by the kernel to userspace. ++ * "U:" messages are sent by userspace to the kernel. ++ */ ++ BRC_GENL_C_DP_ADD, /* K: Datapath created. */ ++ BRC_GENL_C_DP_DEL, /* K: Datapath destroyed. */ ++ BRC_GENL_C_DP_RESULT, /* U: Return code from ovs-brcompatd. */ ++ BRC_GENL_C_PORT_ADD, /* K: Port added to datapath. */ ++ BRC_GENL_C_PORT_DEL, /* K: Port removed from datapath. */ ++ BRC_GENL_C_QUERY_MC, /* U: Get multicast group for brcompat. */ ++ BRC_GENL_C_SET_PROC, /* U: Set contents of file in /proc. */ ++ BRC_GENL_C_FDB_QUERY, /* K: Read records from forwarding database. */ ++ BRC_GENL_C_GET_BRIDGES, /* K: Get ifindexes of all bridges. */ ++ BRC_GENL_C_GET_PORTS, /* K: Get ifindexes of all ports on a bridge. */ ++ ++ __BRC_GENL_C_MAX, ++ BRC_GENL_C_MAX = __BRC_GENL_C_MAX - 1 ++}; ++#endif /* openvswitch/brcompat-netlink.h */ +diff -r 9dfeb6b4054e include/openvswitch/datapath-protocol.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/include/openvswitch/datapath-protocol.h Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,309 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * ++ * This file is offered under your choice of two licenses: Apache 2.0 or GNU ++ * GPL 2.0 or later. The permission statements for each of these licenses is ++ * given below. You may license your modifications to this file under either ++ * of these licenses or both. If you wish to license your modifications under ++ * only one of these licenses, delete the permission text for the other ++ * license. ++ * ++ * ---------------------------------------------------------------------- ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at: ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ * ---------------------------------------------------------------------- ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ---------------------------------------------------------------------- ++ */ ++ ++/* Protocol between userspace and kernel datapath. */ ++ ++#ifndef OPENVSWITCH_DATAPATH_PROTOCOL_H ++#define OPENVSWITCH_DATAPATH_PROTOCOL_H 1 ++ ++#ifdef __KERNEL__ ++#include ++#else ++#include ++#endif ++#include ++ ++#define ODP_MAX 256 /* Maximum number of datapaths. */ ++ ++#define ODP_DP_CREATE _IO('O', 0) ++#define ODP_DP_DESTROY _IO('O', 1) ++#define ODP_DP_STATS _IOW('O', 2, struct odp_stats) ++ ++#define ODP_GET_DROP_FRAGS _IOW('O', 3, int) ++#define ODP_SET_DROP_FRAGS _IOR('O', 4, int) ++ ++#define ODP_GET_LISTEN_MASK _IOW('O', 5, int) ++#define ODP_SET_LISTEN_MASK _IOR('O', 6, int) ++ ++#define ODP_PORT_ADD _IOR('O', 7, struct odp_port) ++#define ODP_PORT_DEL _IOR('O', 8, int) ++#define ODP_PORT_QUERY _IOWR('O', 9, struct odp_port) ++#define ODP_PORT_LIST _IOWR('O', 10, struct odp_portvec) ++ ++#define ODP_PORT_GROUP_SET _IOR('O', 11, struct odp_port_group) ++#define ODP_PORT_GROUP_GET _IOWR('O', 12, struct odp_port_group) ++ ++#define ODP_FLOW_GET _IOWR('O', 13, struct odp_flow) ++#define ODP_FLOW_PUT _IOWR('O', 14, struct odp_flow) ++#define ODP_FLOW_LIST _IOWR('O', 15, struct odp_flowvec) ++#define ODP_FLOW_FLUSH _IO('O', 16) ++#define ODP_FLOW_DEL _IOWR('O', 17, struct odp_flow) ++ ++#define ODP_EXECUTE _IOR('O', 18, struct odp_execute) ++ ++struct odp_stats { ++ /* Flows. */ ++ __u32 n_flows; /* Number of flows in flow table. */ ++ __u32 cur_capacity; /* Current flow table capacity. */ ++ __u32 max_capacity; /* Maximum expansion of flow table capacity. */ ++ ++ /* Ports. */ ++ __u32 n_ports; /* Current number of ports. */ ++ __u32 max_ports; /* Maximum supported number of ports. */ ++ __u16 max_groups; /* Maximum number of port groups. */ ++ __u16 reserved; ++ ++ /* Lookups. */ ++ __u64 n_frags; /* Number of dropped IP fragments. */ ++ __u64 n_hit; /* Number of flow table matches. */ ++ __u64 n_missed; /* Number of flow table misses. */ ++ __u64 n_lost; /* Number of misses not sent to userspace. */ ++ ++ /* Queues. */ ++ __u16 max_miss_queue; /* Max length of ODPL_MISS queue. */ ++ __u16 max_action_queue; /* Max length of ODPL_ACTION queue. */ ++}; ++ ++/* Logical ports. */ ++#define ODPP_LOCAL ((__u16)0) ++#define ODPP_NONE ((__u16)-1) ++ ++/* Listening channels. */ ++#define _ODPL_MISS_NR 0 /* Packet missed in flow table. */ ++#define ODPL_MISS (1 << _ODPL_MISS_NR) ++#define _ODPL_ACTION_NR 1 /* Packet output to ODPP_CONTROLLER. */ ++#define ODPL_ACTION (1 << _ODPL_ACTION_NR) ++#define ODPL_ALL (ODPL_MISS | ODPL_ACTION) ++ ++/* Format of messages read from datapath fd. */ ++struct odp_msg { ++ __u32 type; /* _ODPL_MISS_NR or _ODPL_ACTION_NR. */ ++ __u32 length; /* Message length, including header. */ ++ __u16 port; /* Port on which frame was received. */ ++ __u16 reserved; ++ __u32 arg; /* Argument value specified in action. */ ++ /* Followed by packet data. */ ++}; ++ ++#define ODP_PORT_INTERNAL (1 << 0) /* This port is simulated. */ ++struct odp_port { ++ char devname[16]; /* IFNAMSIZ */ ++ __u16 port; ++ __u16 flags; ++ __u32 reserved2; ++}; ++ ++struct odp_portvec { ++ struct odp_port *ports; ++ int n_ports; ++}; ++ ++struct odp_port_group { ++ __u16 *ports; ++ __u16 n_ports; /* Number of ports. */ ++ __u16 group; /* Group number. */ ++}; ++ ++struct odp_flow_stats { ++ __u64 n_packets; /* Number of matched packets. */ ++ __u64 n_bytes; /* Number of matched bytes. */ ++ __u64 used_sec; /* Time last used. */ ++ __u32 used_nsec; ++ __u8 tcp_flags; ++ __u8 ip_tos; ++ __u16 error; /* Used by ODP_FLOW_GET. */ ++}; ++ ++struct odp_flow_key { ++ __be32 nw_src; /* IP source address. */ ++ __be32 nw_dst; /* IP destination address. */ ++ __u16 in_port; /* Input switch port. */ ++ __be16 dl_vlan; /* Input VLAN. */ ++ __be16 dl_type; /* Ethernet frame type. */ ++ __be16 tp_src; /* TCP/UDP source port. */ ++ __be16 tp_dst; /* TCP/UDP destination port. */ ++ __u8 dl_src[ETH_ALEN]; /* Ethernet source address. */ ++ __u8 dl_dst[ETH_ALEN]; /* Ethernet destination address. */ ++ __u8 nw_proto; /* IP protocol or lower 8 bits of ++ ARP opcode. */ ++ __u8 reserved; /* Pad to 64 bits. */ ++}; ++ ++struct odp_flow { ++ struct odp_flow_stats stats; ++ struct odp_flow_key key; ++ union odp_action *actions; ++ __u32 n_actions; ++}; ++ ++/* Flags for ODP_FLOW_PUT. */ ++#define ODPPF_CREATE (1 << 0) /* Allow creating a new flow. */ ++#define ODPPF_MODIFY (1 << 1) /* Allow modifying an existing flow. */ ++#define ODPPF_ZERO_STATS (1 << 2) /* Zero the stats of an existing flow. */ ++ ++/* ODP_FLOW_PUT argument. */ ++struct odp_flow_put { ++ struct odp_flow flow; ++ __u32 flags; ++}; ++ ++struct odp_flowvec { ++ struct odp_flow *flows; ++ int n_flows; ++}; ++ ++/* The VLAN id is 12 bits, so we can use the entire 16 bits to indicate ++ * special conditions. All ones is used to match that no VLAN id was ++ * set. */ ++#define ODP_VLAN_NONE 0xffff ++ ++/* Action types. */ ++#define ODPAT_OUTPUT 0 /* Output to switch port. */ ++#define ODPAT_OUTPUT_GROUP 1 /* Output to all ports in group. */ ++#define ODPAT_CONTROLLER 2 /* Send copy to controller. */ ++#define ODPAT_SET_VLAN_VID 3 /* Set the 802.1q VLAN id. */ ++#define ODPAT_SET_VLAN_PCP 4 /* Set the 802.1q priority. */ ++#define ODPAT_STRIP_VLAN 5 /* Strip the 802.1q header. */ ++#define ODPAT_SET_DL_SRC 6 /* Ethernet source address. */ ++#define ODPAT_SET_DL_DST 7 /* Ethernet destination address. */ ++#define ODPAT_SET_NW_SRC 8 /* IP source address. */ ++#define ODPAT_SET_NW_DST 9 /* IP destination address. */ ++#define ODPAT_SET_TP_SRC 10 /* TCP/UDP source port. */ ++#define ODPAT_SET_TP_DST 11 /* TCP/UDP destination port. */ ++#define ODPAT_N_ACTIONS 12 ++ ++struct odp_action_output { ++ __u16 type; /* ODPAT_OUTPUT. */ ++ __u16 port; /* Output port. */ ++ __u16 reserved1; ++ __u16 reserved2; ++}; ++ ++struct odp_action_output_group { ++ __u16 type; /* ODPAT_OUTPUT_GROUP. */ ++ __u16 group; /* Group number. */ ++ __u16 reserved1; ++ __u16 reserved2; ++}; ++ ++struct odp_action_controller { ++ __u16 type; /* ODPAT_OUTPUT_CONTROLLER. */ ++ __u16 reserved; ++ __u32 arg; /* Copied to struct odp_msg 'arg' member. */ ++}; ++ ++/* Action structure for ODPAT_SET_VLAN_VID. */ ++struct odp_action_vlan_vid { ++ __u16 type; /* ODPAT_SET_VLAN_VID. */ ++ __be16 vlan_vid; /* VLAN id. */ ++ __u16 reserved1; ++ __u16 reserved2; ++}; ++ ++/* Action structure for ODPAT_SET_VLAN_PCP. */ ++struct odp_action_vlan_pcp { ++ __u16 type; /* ODPAT_SET_VLAN_PCP. */ ++ __u8 vlan_pcp; /* VLAN priority. */ ++ __u8 reserved1; ++ __u16 reserved2; ++ __u16 reserved3; ++}; ++ ++/* Action structure for ODPAT_SET_DL_SRC/DST. */ ++struct odp_action_dl_addr { ++ __u16 type; /* ODPAT_SET_DL_SRC/DST. */ ++ __u8 dl_addr[ETH_ALEN]; /* Ethernet address. */ ++}; ++ ++/* Action structure for ODPAT_SET_NW_SRC/DST. */ ++struct odp_action_nw_addr { ++ __u16 type; /* ODPAT_SET_TW_SRC/DST. */ ++ __u16 reserved; ++ __be32 nw_addr; /* IP address. */ ++}; ++ ++/* Action structure for ODPAT_SET_TP_SRC/DST. */ ++struct odp_action_tp_port { ++ __u16 type; /* ODPAT_SET_TP_SRC/DST. */ ++ __be16 tp_port; /* TCP/UDP port. */ ++ __u16 reserved1; ++ __u16 reserved2; ++}; ++ ++union odp_action { ++ __u16 type; ++ struct odp_action_output output; ++ struct odp_action_output_group output_group; ++ struct odp_action_controller controller; ++ struct odp_action_vlan_vid vlan_vid; ++ struct odp_action_vlan_pcp vlan_pcp; ++ struct odp_action_dl_addr dl_addr; ++ struct odp_action_nw_addr nw_addr; ++ struct odp_action_tp_port tp_port; ++}; ++ ++struct odp_execute { ++ __u16 in_port; ++ __u16 reserved1; ++ __u32 reserved2; ++ ++ union odp_action *actions; ++ __u32 n_actions; ++ ++ const void *data; ++ __u32 length; ++}; ++ ++/* Values below this cutoff are 802.3 packets and the two bytes ++ * following MAC addresses are used as a frame length. Otherwise, the ++ * two bytes are used as the Ethernet type. ++ */ ++#define ODP_DL_TYPE_ETH2_CUTOFF 0x0600 ++ ++/* Value of dl_type to indicate that the frame does not include an ++ * Ethernet type. ++ */ ++#define ODP_DL_TYPE_NOT_ETH_TYPE 0x05ff ++ ++/* The VLAN id is 12-bits, so we can use the entire 16 bits to indicate ++ * special conditions. All ones indicates that no VLAN id was set. ++ */ ++#define ODP_VLAN_NONE 0xffff ++ ++#endif /* openvswitch/datapath-protocol.h */ +diff -r 9dfeb6b4054e net/vswitch/actions.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/actions.c Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,424 @@ ++/* ++ * Distributed under the terms of the GNU GPL version 2. ++ * Copyright (c) 2007, 2008, 2009 Nicira Networks. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++/* Functions for executing flow actions. */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "datapath.h" ++#include "dp_dev.h" ++#include "actions.h" ++#include "openvswitch/datapath-protocol.h" ++ ++struct sk_buff * ++make_writable(struct sk_buff *skb, gfp_t gfp) ++{ ++ if (skb_shared(skb) || skb_cloned(skb)) { ++ struct sk_buff *nskb = skb_copy(skb, gfp); ++ if (nskb) { ++ kfree_skb(skb); ++ return nskb; ++ } ++ } else { ++ unsigned int hdr_len = (skb_transport_offset(skb) ++ + sizeof(struct tcphdr)); ++ if (pskb_may_pull(skb, min(hdr_len, skb->len))) ++ return skb; ++ } ++ kfree_skb(skb); ++ return NULL; ++} ++ ++ ++static struct sk_buff * ++vlan_pull_tag(struct sk_buff *skb) ++{ ++ struct vlan_ethhdr *vh = vlan_eth_hdr(skb); ++ struct ethhdr *eh; ++ ++ ++ /* Verify we were given a vlan packet */ ++ if (vh->h_vlan_proto != htons(ETH_P_8021Q)) ++ return skb; ++ ++ memmove(skb->data + VLAN_HLEN, skb->data, 2 * VLAN_ETH_ALEN); ++ ++ eh = (struct ethhdr *)skb_pull(skb, VLAN_HLEN); ++ ++ skb->protocol = eh->h_proto; ++ skb->mac_header += VLAN_HLEN; ++ ++ return skb; ++} ++ ++ ++static struct sk_buff * ++modify_vlan_tci(struct datapath *dp, struct sk_buff *skb, ++ struct odp_flow_key *key, const union odp_action *a, ++ int n_actions, gfp_t gfp) ++{ ++ u16 tci, mask; ++ ++ if (a->type == ODPAT_SET_VLAN_VID) { ++ tci = ntohs(a->vlan_vid.vlan_vid); ++ mask = VLAN_VID_MASK; ++ key->dl_vlan = htons(tci & mask); ++ } else { ++ tci = a->vlan_pcp.vlan_pcp << 13; ++ mask = VLAN_PCP_MASK; ++ } ++ ++ skb = make_writable(skb, gfp); ++ if (!skb) ++ return ERR_PTR(-ENOMEM); ++ ++ if (skb->protocol == htons(ETH_P_8021Q)) { ++ /* Modify vlan id, but maintain other TCI values */ ++ struct vlan_ethhdr *vh = vlan_eth_hdr(skb); ++ vh->h_vlan_TCI = htons((ntohs(vh->h_vlan_TCI) & ~mask) | tci); ++ } else { ++ /* Add vlan header */ ++ ++ /* Set up checksumming pointers for checksum-deferred packets ++ * on Xen. Otherwise, dev_queue_xmit() will try to do this ++ * when we send the packet out on the wire, and it will fail at ++ * that point because skb_checksum_setup() will not look inside ++ * an 802.1Q header. */ ++ vswitch_skb_checksum_setup(skb); ++ ++ /* GSO is not implemented for packets with an 802.1Q header, so ++ * we have to do segmentation before we add that header. ++ * ++ * GSO does work with hardware-accelerated VLAN tagging, but we ++ * can't use hardware-accelerated VLAN tagging since it ++ * requires the device to have a VLAN group configured (with ++ * e.g. vconfig(8)) and we don't do that. ++ * ++ * Having to do this here may be a performance loss, since we ++ * can't take advantage of TSO hardware support, although it ++ * does not make a measurable network performance difference ++ * for 1G Ethernet. Fixing that would require patching the ++ * kernel (either to add GSO support to the VLAN protocol or to ++ * support hardware-accelerated VLAN tagging without VLAN ++ * groups configured). */ ++ if (skb_is_gso(skb)) { ++ struct sk_buff *segs; ++ ++ segs = skb_gso_segment(skb, 0); ++ kfree_skb(skb); ++ if (unlikely(IS_ERR(segs))) ++ return ERR_CAST(segs); ++ ++ do { ++ struct sk_buff *nskb = segs->next; ++ int err; ++ ++ segs->next = NULL; ++ ++ segs = __vlan_put_tag(segs, tci); ++ err = -ENOMEM; ++ if (segs) { ++ struct odp_flow_key segkey = *key; ++ err = execute_actions(dp, segs, ++ &segkey, a + 1, ++ n_actions - 1, ++ gfp); ++ } ++ ++ if (unlikely(err)) { ++ while ((segs = nskb)) { ++ nskb = segs->next; ++ segs->next = NULL; ++ kfree_skb(segs); ++ } ++ return ERR_PTR(err); ++ } ++ ++ segs = nskb; ++ } while (segs->next); ++ ++ skb = segs; ++ } ++ ++ /* The hardware-accelerated version of vlan_put_tag() works ++ * only for a device that has a VLAN group configured (with ++ * e.g. vconfig(8)), so call the software-only version ++ * __vlan_put_tag() directly instead. ++ */ ++ skb = __vlan_put_tag(skb, tci); ++ if (!skb) ++ return ERR_PTR(-ENOMEM); ++ } ++ ++ return skb; ++} ++ ++static struct sk_buff *strip_vlan(struct sk_buff *skb, ++ struct odp_flow_key *key, gfp_t gfp) ++{ ++ skb = make_writable(skb, gfp); ++ if (skb) { ++ vlan_pull_tag(skb); ++ key->dl_vlan = htons(ODP_VLAN_NONE); ++ } ++ return skb; ++} ++ ++static struct sk_buff *set_dl_addr(struct sk_buff *skb, ++ const struct odp_action_dl_addr *a, ++ gfp_t gfp) ++{ ++ skb = make_writable(skb, gfp); ++ if (skb) { ++ struct ethhdr *eh = eth_hdr(skb); ++ memcpy(a->type == ODPAT_SET_DL_SRC ? eh->h_source : eh->h_dest, ++ a->dl_addr, ETH_ALEN); ++ } ++ return skb; ++} ++ ++/* Updates 'sum', which is a field in 'skb''s data, given that a 4-byte field ++ * covered by the sum has been changed from 'from' to 'to'. If set, ++ * 'pseudohdr' indicates that the field is in the TCP or UDP pseudo-header. ++ * Based on nf_proto_csum_replace4. */ ++static void update_csum(__sum16 *sum, struct sk_buff *skb, ++ __be32 from, __be32 to, int pseudohdr) ++{ ++ __be32 diff[] = { ~from, to }; ++ if (skb->ip_summed != CHECKSUM_PARTIAL) { ++ *sum = csum_fold(csum_partial((char *)diff, sizeof(diff), ++ ~csum_unfold(*sum))); ++ if (skb->ip_summed == CHECKSUM_COMPLETE && pseudohdr) ++ skb->csum = ~csum_partial((char *)diff, sizeof(diff), ++ ~skb->csum); ++ } else if (pseudohdr) ++ *sum = ~csum_fold(csum_partial((char *)diff, sizeof(diff), ++ csum_unfold(*sum))); ++} ++ ++static struct sk_buff *set_nw_addr(struct sk_buff *skb, ++ struct odp_flow_key *key, ++ const struct odp_action_nw_addr *a, ++ gfp_t gfp) ++{ ++ if (key->dl_type != htons(ETH_P_IP)) ++ return skb; ++ ++ skb = make_writable(skb, gfp); ++ if (skb) { ++ struct iphdr *nh = ip_hdr(skb); ++ u32 *f = a->type == ODPAT_SET_NW_SRC ? &nh->saddr : &nh->daddr; ++ u32 old = *f; ++ u32 new = a->nw_addr; ++ ++ if (key->nw_proto == IPPROTO_TCP) { ++ struct tcphdr *th = tcp_hdr(skb); ++ update_csum(&th->check, skb, old, new, 1); ++ } else if (key->nw_proto == IPPROTO_UDP) { ++ struct udphdr *th = udp_hdr(skb); ++ update_csum(&th->check, skb, old, new, 1); ++ } ++ update_csum(&nh->check, skb, old, new, 0); ++ *f = new; ++ } ++ return skb; ++} ++ ++static struct sk_buff * ++set_tp_port(struct sk_buff *skb, struct odp_flow_key *key, ++ const struct odp_action_tp_port *a, ++ gfp_t gfp) ++{ ++ int check_ofs; ++ ++ if (key->dl_type != htons(ETH_P_IP)) ++ return skb; ++ ++ if (key->nw_proto == IPPROTO_TCP) ++ check_ofs = offsetof(struct tcphdr, check); ++ else if (key->nw_proto == IPPROTO_UDP) ++ check_ofs = offsetof(struct udphdr, check); ++ else ++ return skb; ++ ++ skb = make_writable(skb, gfp); ++ if (skb) { ++ struct udphdr *th = udp_hdr(skb); ++ u16 *f = a->type == ODPAT_SET_TP_SRC ? &th->source : &th->dest; ++ u16 old = *f; ++ u16 new = a->tp_port; ++ update_csum((u16*)((u8*)skb->data + check_ofs), ++ skb, old, new, 1); ++ *f = new; ++ } ++ return skb; ++} ++ ++static inline unsigned packet_length(const struct sk_buff *skb) ++{ ++ unsigned length = skb->len - ETH_HLEN; ++ if (skb->protocol == htons(ETH_P_8021Q)) ++ length -= VLAN_HLEN; ++ return length; ++} ++ ++int dp_xmit_skb(struct sk_buff *skb) ++{ ++ struct datapath *dp = skb->dev->br_port->dp; ++ int len = skb->len; ++ ++ if (packet_length(skb) > skb->dev->mtu && !skb_is_gso(skb)) { ++ printk(KERN_WARNING "%s: dropped over-mtu packet: %d > %d\n", ++ dp_name(dp), packet_length(skb), skb->dev->mtu); ++ kfree_skb(skb); ++ return -E2BIG; ++ } ++ ++ dev_queue_xmit(skb); ++ ++ return len; ++} ++ ++static void ++do_output(struct datapath *dp, struct sk_buff *skb, int out_port) ++{ ++ struct net_bridge_port *p; ++ struct net_device *dev; ++ ++ if (!skb) ++ goto error; ++ ++ p = dp->ports[out_port]; ++ if (!p) ++ goto error; ++ ++ dev = skb->dev = p->dev; ++ if (is_dp_dev(dev)) ++ dp_dev_recv(dev, skb); ++ else ++ dp_xmit_skb(skb); ++ return; ++ ++error: ++ kfree_skb(skb); ++} ++ ++/* Never consumes 'skb'. Returns a port that 'skb' should be sent to, -1 if ++ * none. */ ++static int output_group(struct datapath *dp, __u16 group, ++ struct sk_buff *skb, gfp_t gfp) ++{ ++ struct dp_port_group *g = rcu_dereference(dp->groups[group]); ++ int prev_port = -1; ++ int i; ++ ++ if (!g) ++ return -1; ++ for (i = 0; i < g->n_ports; i++) { ++ struct net_bridge_port *p = dp->ports[g->ports[i]]; ++ if (!p || skb->dev == p->dev) ++ continue; ++ if (prev_port != -1) { ++ struct sk_buff *clone = skb_clone(skb, gfp); ++ if (!clone) ++ return -1; ++ do_output(dp, clone, prev_port); ++ } ++ prev_port = p->port_no; ++ } ++ return prev_port; ++} ++ ++static int ++output_control(struct datapath *dp, struct sk_buff *skb, u32 arg, gfp_t gfp) ++{ ++ skb = skb_clone(skb, gfp); ++ if (!skb) ++ return -ENOMEM; ++ return dp_output_control(dp, skb, _ODPL_ACTION_NR, arg); ++} ++ ++/* Execute a list of actions against 'skb'. */ ++int execute_actions(struct datapath *dp, struct sk_buff *skb, ++ struct odp_flow_key *key, ++ const union odp_action *a, int n_actions, ++ gfp_t gfp) ++{ ++ /* Every output action needs a separate clone of 'skb', but the common ++ * case is just a single output action, so that doing a clone and ++ * then freeing the original skbuff is wasteful. So the following code ++ * is slightly obscure just to avoid that. */ ++ int prev_port = -1; ++ int err; ++ for (; n_actions > 0; a++, n_actions--) { ++ WARN_ON_ONCE(skb_shared(skb)); ++ if (prev_port != -1) { ++ do_output(dp, skb_clone(skb, gfp), prev_port); ++ prev_port = -1; ++ } ++ ++ switch (a->type) { ++ case ODPAT_OUTPUT: ++ prev_port = a->output.port; ++ break; ++ ++ case ODPAT_OUTPUT_GROUP: ++ prev_port = output_group(dp, a->output_group.group, ++ skb, gfp); ++ break; ++ ++ case ODPAT_CONTROLLER: ++ err = output_control(dp, skb, a->controller.arg, gfp); ++ if (err) { ++ kfree_skb(skb); ++ return err; ++ } ++ break; ++ ++ case ODPAT_SET_VLAN_VID: ++ case ODPAT_SET_VLAN_PCP: ++ skb = modify_vlan_tci(dp, skb, key, a, n_actions, gfp); ++ if (IS_ERR(skb)) ++ return PTR_ERR(skb); ++ break; ++ ++ case ODPAT_STRIP_VLAN: ++ skb = strip_vlan(skb, key, gfp); ++ break; ++ ++ case ODPAT_SET_DL_SRC: ++ case ODPAT_SET_DL_DST: ++ skb = set_dl_addr(skb, &a->dl_addr, gfp); ++ break; ++ ++ case ODPAT_SET_NW_SRC: ++ case ODPAT_SET_NW_DST: ++ skb = set_nw_addr(skb, key, &a->nw_addr, gfp); ++ break; ++ ++ case ODPAT_SET_TP_SRC: ++ case ODPAT_SET_TP_DST: ++ skb = set_tp_port(skb, key, &a->tp_port, gfp); ++ break; ++ } ++ if (!skb) ++ return -ENOMEM; ++ } ++ if (prev_port != -1) ++ do_output(dp, skb, prev_port); ++ else ++ kfree_skb(skb); ++ return 0; ++} +diff -r 9dfeb6b4054e net/vswitch/actions.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/actions.h Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,26 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++#ifndef ACTIONS_H ++#define ACTIONS_H 1 ++ ++#include ++ ++struct datapath; ++struct sk_buff; ++struct odp_flow_key; ++union odp_action; ++ ++struct sk_buff *make_writable(struct sk_buff *, gfp_t gfp); ++int dp_xmit_skb(struct sk_buff *); ++int execute_actions(struct datapath *dp, struct sk_buff *skb, ++ struct odp_flow_key *key, ++ const union odp_action *, int n_actions, ++ gfp_t gfp); ++ ++#endif /* actions.h */ +diff -r 9dfeb6b4054e net/vswitch/brc_procfs.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/brc_procfs.c Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,193 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "openvswitch/brcompat-netlink.h" ++ ++/* This code implements a Generic Netlink command BRC_GENL_C_SET_PROC that can ++ * be used to add, modify, and delete arbitrary files in selected ++ * subdirectories of /proc. It's a horrible kluge prompted by the need to ++ * simulate certain /proc/net/vlan and /proc/net/bonding files for software ++ * that wants to read them, and with any luck it will go away eventually. ++ * ++ * The implementation is a kluge too. In particular, we want to release the ++ * strings copied into the 'data' members of proc_dir_entry when the ++ * proc_dir_entry structures are freed, but there doesn't appear to be a way to ++ * hook that, so instead we have to rely on being the only entity modifying the ++ * directories in question. ++ */ ++ ++static int brc_seq_show(struct seq_file *seq, void *unused) ++{ ++ seq_puts(seq, seq->private); ++ return 0; ++} ++ ++static int brc_seq_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, brc_seq_show, PDE(inode)->data); ++} ++ ++static struct file_operations brc_fops = { ++ .owner = THIS_MODULE, ++ .open = brc_seq_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static struct proc_dir_entry *proc_vlan_dir; ++static struct proc_dir_entry *proc_bonding_dir; ++ ++struct proc_dir_entry *brc_lookup_entry(struct proc_dir_entry *de, const char *name) ++{ ++ int namelen = strlen(name); ++ for (de = de->subdir; de; de = de->next) { ++ if (de->namelen != namelen) ++ continue; ++ if (!memcmp(name, de->name, de->namelen)) ++ return de; ++ } ++ return NULL; ++} ++ ++static struct proc_dir_entry *brc_open_dir(const char *dir_name, ++ struct proc_dir_entry *parent, ++ struct proc_dir_entry **dirp) ++{ ++ if (!*dirp) { ++ struct proc_dir_entry *dir; ++ if (brc_lookup_entry(parent, dir_name)) { ++ printk(KERN_WARNING "%s proc directory exists, can't " ++ "simulate--probably its real module is " ++ "loaded\n", dir_name); ++ return NULL; ++ } ++ dir = *dirp = proc_mkdir(dir_name, parent); ++ } ++ return *dirp; ++} ++ ++/* Maximum length of the BRC_GENL_A_PROC_DIR and BRC_GENL_A_PROC_NAME strings. ++ * If we could depend on supporting NLA_NUL_STRING and the .len member in ++ * Generic Netlink policy, then we could just put this in brc_genl_policy (and ++ * simplify brc_genl_set_proc() below too), but upstream 2.6.18 does not have ++ * either. */ ++#define BRC_NAME_LEN_MAX 32 ++ ++int brc_genl_set_proc(struct sk_buff *skb, struct genl_info *info) ++{ ++ struct proc_dir_entry *dir, *entry; ++ const char *dir_name, *name; ++ char *data; ++ ++ if (!info->attrs[BRC_GENL_A_PROC_DIR] || ++ VERIFY_NUL_STRING(info->attrs[BRC_GENL_A_PROC_DIR]) || ++ !info->attrs[BRC_GENL_A_PROC_NAME] || ++ VERIFY_NUL_STRING(info->attrs[BRC_GENL_A_PROC_NAME]) || ++ (info->attrs[BRC_GENL_A_PROC_DATA] && ++ VERIFY_NUL_STRING(info->attrs[BRC_GENL_A_PROC_DATA]))) ++ return -EINVAL; ++ ++ dir_name = nla_data(info->attrs[BRC_GENL_A_PROC_DIR]); ++ name = nla_data(info->attrs[BRC_GENL_A_PROC_NAME]); ++ if (strlen(dir_name) > BRC_NAME_LEN_MAX || ++ strlen(name) > BRC_NAME_LEN_MAX) ++ return -EINVAL; ++ ++ if (!strcmp(dir_name, "net/vlan")) ++ dir = brc_open_dir("vlan", proc_net, &proc_vlan_dir); ++ else if (!strcmp(dir_name, "net/bonding")) ++ dir = brc_open_dir("bonding", proc_net, &proc_bonding_dir); ++ else ++ return -EINVAL; ++ if (!dir) { ++ /* Probably failed because the module that really implements ++ * the function in question is loaded and already owns the ++ * directory in question.*/ ++ return -EBUSY; ++ } ++ ++ entry = brc_lookup_entry(dir, name); ++ if (!info->attrs[BRC_GENL_A_PROC_DATA]) { ++ if (!entry) ++ return -ENOENT; ++ ++ data = entry->data; ++ remove_proc_entry(name, dir); ++ if (brc_lookup_entry(dir, name)) ++ return -EBUSY; /* Shouldn't happen */ ++ ++ kfree(data); ++ } else { ++ data = kstrdup(nla_data(info->attrs[BRC_GENL_A_PROC_DATA]), ++ GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ if (entry) { ++ char *old_data = entry->data; ++ entry->data = data; ++ kfree(old_data); ++ return 0; ++ } ++ ++ entry = create_proc_entry(name, S_IFREG|S_IRUSR|S_IWUSR, dir); ++ if (!entry) { ++ kfree(data); ++ return -ENOBUFS; ++ } ++ entry->proc_fops = &brc_fops; ++ entry->data = data; ++ } ++ return 0; ++} ++ ++static void kill_proc_dir(const char *dir_name, ++ struct proc_dir_entry *parent, ++ struct proc_dir_entry *dir) ++{ ++ if (!dir) ++ return; ++ for (;;) { ++ struct proc_dir_entry *e; ++ char *data; ++ char name[BRC_NAME_LEN_MAX + 1]; ++ ++ e = dir->subdir; ++ if (!e) ++ break; ++ ++ if (e->namelen >= sizeof name) { ++ /* Can't happen: we prevent adding names this long by ++ * limiting the BRC_GENL_A_PROC_NAME string to ++ * BRC_NAME_LEN_MAX bytes. */ ++ WARN_ON(1); ++ break; ++ } ++ strcpy(name, e->name); ++ ++ data = e->data; ++ e->data = NULL; ++ kfree(data); ++ ++ remove_proc_entry(name, dir); ++ } ++ remove_proc_entry(dir_name, parent); ++} ++ ++void brc_procfs_exit(void) ++{ ++ kill_proc_dir("vlan", proc_net, proc_vlan_dir); ++ kill_proc_dir("bonding", proc_net, proc_bonding_dir); ++} +diff -r 9dfeb6b4054e net/vswitch/brc_procfs.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/brc_procfs.h Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,19 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++#ifndef BRC_PROCFS_H ++#define BRC_PROCFS_H 1 ++ ++struct sk_buff; ++struct genl_info; ++ ++void brc_procfs_exit(void); ++int brc_genl_set_proc(struct sk_buff *skb, struct genl_info *info); ++ ++#endif /* brc_procfs.h */ ++ +diff -r 9dfeb6b4054e net/vswitch/brcompat.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/brcompat.c Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,578 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "compat.h" ++#include "openvswitch/brcompat-netlink.h" ++#include "brc_procfs.h" ++#include "datapath.h" ++ ++static struct genl_family brc_genl_family; ++static struct genl_multicast_group brc_mc_group; ++ ++/* Time to wait for ovs-vswitchd to respond to a datapath action, in ++ * jiffies. */ ++#define BRC_TIMEOUT (HZ * 5) ++ ++/* Mutex to serialize ovs-brcompatd callbacks. (Some callbacks naturally hold ++ * br_ioctl_mutex, others hold rtnl_lock, but we can't take the former ++ * ourselves and we don't want to hold the latter over a potentially long ++ * period of time.) */ ++static DEFINE_MUTEX(brc_serial); ++ ++/* Userspace communication. */ ++static DEFINE_SPINLOCK(brc_lock); /* Ensure atomic access to these vars. */ ++static DECLARE_COMPLETION(brc_done); /* Userspace signaled operation done? */ ++static struct sk_buff *brc_reply; /* Reply from userspace. */ ++static u32 brc_seq; /* Sequence number for current op. */ ++ ++static struct sk_buff *brc_send_command(struct sk_buff *, struct nlattr **attrs); ++static int brc_send_simple_command(struct sk_buff *); ++ ++static struct sk_buff * ++brc_make_request(int op, const char *bridge, const char *port) ++{ ++ struct sk_buff *skb = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); ++ if (!skb) ++ goto error; ++ ++ genlmsg_put(skb, 0, 0, &brc_genl_family, 0, op); ++ if (bridge) ++ NLA_PUT_STRING(skb, BRC_GENL_A_DP_NAME, bridge); ++ if (port) ++ NLA_PUT_STRING(skb, BRC_GENL_A_PORT_NAME, port); ++ return skb; ++ ++nla_put_failure: ++ kfree_skb(skb); ++error: ++ return NULL; ++} ++ ++static int brc_send_simple_command(struct sk_buff *request) ++{ ++ struct nlattr *attrs[BRC_GENL_A_MAX + 1]; ++ struct sk_buff *reply; ++ int error; ++ ++ reply = brc_send_command(request, attrs); ++ if (IS_ERR(reply)) ++ return PTR_ERR(reply); ++ ++ error = nla_get_u32(attrs[BRC_GENL_A_ERR_CODE]); ++ kfree_skb(reply); ++ return -error; ++} ++ ++static int brc_add_del_bridge(char __user *uname, int add) ++{ ++ struct sk_buff *request; ++ char name[IFNAMSIZ]; ++ ++ if (copy_from_user(name, uname, IFNAMSIZ)) ++ return -EFAULT; ++ ++ name[IFNAMSIZ - 1] = 0; ++ request = brc_make_request(add ? BRC_GENL_C_DP_ADD : BRC_GENL_C_DP_DEL, ++ name, NULL); ++ if (!request) ++ return -ENOMEM; ++ ++ return brc_send_simple_command(request); ++} ++ ++static int brc_get_indices(int op, const char *br_name, ++ int __user *uindices, int n) ++{ ++ struct nlattr *attrs[BRC_GENL_A_MAX + 1]; ++ struct sk_buff *request, *reply; ++ int *indices; ++ int ret; ++ int len; ++ ++ if (n < 0) ++ return -EINVAL; ++ if (n >= 2048) ++ return -ENOMEM; ++ ++ request = brc_make_request(op, br_name, NULL); ++ if (!request) ++ return -ENOMEM; ++ ++ reply = brc_send_command(request, attrs); ++ ret = PTR_ERR(reply); ++ if (IS_ERR(reply)) ++ goto exit; ++ ++ ret = -nla_get_u32(attrs[BRC_GENL_A_ERR_CODE]); ++ if (ret < 0) ++ goto exit_free_skb; ++ ++ ret = -EINVAL; ++ if (!attrs[BRC_GENL_A_IFINDEXES]) ++ goto exit_free_skb; ++ ++ len = nla_len(attrs[BRC_GENL_A_IFINDEXES]); ++ indices = nla_data(attrs[BRC_GENL_A_IFINDEXES]); ++ if (len % sizeof(int)) ++ goto exit_free_skb; ++ ++ n = min_t(int, n, len / sizeof(int)); ++ ret = copy_to_user(uindices, indices, n * sizeof(int)) ? -EFAULT : n; ++ ++exit_free_skb: ++ kfree_skb(reply); ++exit: ++ return ret; ++} ++ ++/* Called with br_ioctl_mutex. */ ++static int brc_get_bridges(int __user *uindices, int n) ++{ ++ return brc_get_indices(BRC_GENL_C_GET_BRIDGES, NULL, uindices, n); ++} ++ ++/* Legacy deviceless bridge ioctl's. Called with br_ioctl_mutex. */ ++static int ++old_deviceless(void __user *uarg) ++{ ++ unsigned long args[3]; ++ ++ if (copy_from_user(args, uarg, sizeof(args))) ++ return -EFAULT; ++ ++ switch (args[0]) { ++ case BRCTL_GET_BRIDGES: ++ return brc_get_bridges((int __user *)args[1], args[2]); ++ ++ case BRCTL_ADD_BRIDGE: ++ return brc_add_del_bridge((void __user *)args[1], 1); ++ case BRCTL_DEL_BRIDGE: ++ return brc_add_del_bridge((void __user *)args[1], 0); ++ } ++ ++ return -EOPNOTSUPP; ++} ++ ++/* Called with the br_ioctl_mutex. */ ++static int ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) ++brc_ioctl_deviceless_stub(unsigned int cmd, void __user *uarg) ++#else ++brc_ioctl_deviceless_stub(struct net *net, unsigned int cmd, void __user *uarg) ++#endif ++{ ++ switch (cmd) { ++ case SIOCGIFBR: ++ case SIOCSIFBR: ++ return old_deviceless(uarg); ++ ++ case SIOCBRADDBR: ++ return brc_add_del_bridge(uarg, 1); ++ case SIOCBRDELBR: ++ return brc_add_del_bridge(uarg, 0); ++ } ++ ++ return -EOPNOTSUPP; ++} ++ ++static int ++brc_add_del_port(struct net_device *dev, int port_ifindex, int add) ++{ ++ struct sk_buff *request; ++ struct net_device *port; ++ int err; ++ ++ port = __dev_get_by_index(&init_net, port_ifindex); ++ if (!port) ++ return -EINVAL; ++ ++ /* Save name of dev and port because there's a race between the ++ * rtnl_unlock() and the brc_send_simple_command(). */ ++ request = brc_make_request(add ? BRC_GENL_C_PORT_ADD : BRC_GENL_C_PORT_DEL, ++ dev->name, port->name); ++ if (!request) ++ return -ENOMEM; ++ ++ rtnl_unlock(); ++ err = brc_send_simple_command(request); ++ rtnl_lock(); ++ ++ return err; ++} ++ ++static int ++brc_get_bridge_info(struct net_device *dev, struct __bridge_info __user *ub) ++{ ++ struct __bridge_info b; ++ u64 id = 0; ++ int i; ++ ++ memset(&b, 0, sizeof(struct __bridge_info)); ++ ++ for (i=0; idev_addr[i] << (8*(ETH_ALEN-1 - i)); ++ b.bridge_id = cpu_to_be64(id); ++ b.stp_enabled = 0; ++ ++ if (copy_to_user(ub, &b, sizeof(struct __bridge_info))) ++ return -EFAULT; ++ ++ return 0; ++} ++ ++static int ++brc_get_port_list(struct net_device *dev, int __user *uindices, int num) ++{ ++ int retval; ++ ++ rtnl_unlock(); ++ retval = brc_get_indices(BRC_GENL_C_GET_PORTS, dev->name, ++ uindices, num); ++ rtnl_lock(); ++ ++ return retval; ++} ++ ++/* ++ * Format up to a page worth of forwarding table entries ++ * userbuf -- where to copy result ++ * maxnum -- maximum number of entries desired ++ * (limited to a page for sanity) ++ * offset -- number of records to skip ++ */ ++static int brc_get_fdb_entries(struct net_device *dev, void __user *userbuf, ++ unsigned long maxnum, unsigned long offset) ++{ ++ struct nlattr *attrs[BRC_GENL_A_MAX + 1]; ++ struct sk_buff *request, *reply; ++ int retval; ++ int len; ++ ++ /* Clamp size to PAGE_SIZE, test maxnum to avoid overflow */ ++ if (maxnum > PAGE_SIZE/sizeof(struct __fdb_entry)) ++ maxnum = PAGE_SIZE/sizeof(struct __fdb_entry); ++ ++ request = brc_make_request(BRC_GENL_C_FDB_QUERY, dev->name, NULL); ++ if (!request) ++ return -ENOMEM; ++ NLA_PUT_U64(request, BRC_GENL_A_FDB_COUNT, maxnum); ++ NLA_PUT_U64(request, BRC_GENL_A_FDB_SKIP, offset); ++ ++ rtnl_unlock(); ++ reply = brc_send_command(request, attrs); ++ retval = PTR_ERR(reply); ++ if (IS_ERR(reply)) ++ goto exit; ++ ++ retval = -nla_get_u32(attrs[BRC_GENL_A_ERR_CODE]); ++ if (retval < 0) ++ goto exit_free_skb; ++ ++ retval = -EINVAL; ++ if (!attrs[BRC_GENL_A_FDB_DATA]) ++ goto exit_free_skb; ++ len = nla_len(attrs[BRC_GENL_A_FDB_DATA]); ++ if (len % sizeof(struct __fdb_entry) || ++ len / sizeof(struct __fdb_entry) > maxnum) ++ goto exit_free_skb; ++ ++ retval = len / sizeof(struct __fdb_entry); ++ if (copy_to_user(userbuf, nla_data(attrs[BRC_GENL_A_FDB_DATA]), len)) ++ retval = -EFAULT; ++ ++exit_free_skb: ++ kfree_skb(reply); ++exit: ++ rtnl_lock(); ++ return retval; ++ ++nla_put_failure: ++ kfree_skb(request); ++ return -ENOMEM; ++} ++ ++/* Legacy ioctl's through SIOCDEVPRIVATE. Called with rtnl_lock. */ ++static int ++old_dev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ unsigned long args[4]; ++ ++ if (copy_from_user(args, rq->ifr_data, sizeof(args))) ++ return -EFAULT; ++ ++ switch (args[0]) { ++ case BRCTL_ADD_IF: ++ return brc_add_del_port(dev, args[1], 1); ++ case BRCTL_DEL_IF: ++ return brc_add_del_port(dev, args[1], 0); ++ ++ case BRCTL_GET_BRIDGE_INFO: ++ return brc_get_bridge_info(dev, (struct __bridge_info __user *)args[1]); ++ ++ case BRCTL_GET_PORT_LIST: ++ return brc_get_port_list(dev, (int __user *)args[1], args[2]); ++ ++ case BRCTL_GET_FDB_ENTRIES: ++ return brc_get_fdb_entries(dev, (void __user *)args[1], ++ args[2], args[3]); ++ } ++ ++ return -EOPNOTSUPP; ++} ++ ++/* Called with the rtnl_lock. */ ++static int ++brc_dev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ int err; ++ ++ switch (cmd) { ++ case SIOCDEVPRIVATE: ++ err = old_dev_ioctl(dev, rq, cmd); ++ break; ++ ++ case SIOCBRADDIF: ++ return brc_add_del_port(dev, rq->ifr_ifindex, 1); ++ case SIOCBRDELIF: ++ return brc_add_del_port(dev, rq->ifr_ifindex, 0); ++ ++ default: ++ err = -EOPNOTSUPP; ++ break; ++ } ++ ++ return err; ++} ++ ++ ++static struct genl_family brc_genl_family = { ++ .id = GENL_ID_GENERATE, ++ .hdrsize = 0, ++ .name = BRC_GENL_FAMILY_NAME, ++ .version = 1, ++ .maxattr = BRC_GENL_A_MAX, ++}; ++ ++static int brc_genl_query(struct sk_buff *skb, struct genl_info *info) ++{ ++ int err = -EINVAL; ++ struct sk_buff *ans_skb; ++ void *data; ++ ++ ans_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); ++ if (!ans_skb) ++ return -ENOMEM; ++ ++ data = genlmsg_put_reply(ans_skb, info, &brc_genl_family, ++ 0, BRC_GENL_C_QUERY_MC); ++ if (data == NULL) { ++ err = -ENOMEM; ++ goto err; ++ } ++ NLA_PUT_U32(ans_skb, BRC_GENL_A_MC_GROUP, brc_mc_group.id); ++ ++ genlmsg_end(ans_skb, data); ++ return genlmsg_reply(ans_skb, info); ++ ++err: ++nla_put_failure: ++ kfree_skb(ans_skb); ++ return err; ++} ++ ++static struct genl_ops brc_genl_ops_query_dp = { ++ .cmd = BRC_GENL_C_QUERY_MC, ++ .flags = GENL_ADMIN_PERM, /* Requires CAP_NET_ADMIN privelege. */ ++ .policy = NULL, ++ .doit = brc_genl_query, ++ .dumpit = NULL ++}; ++ ++/* Attribute policy: what each attribute may contain. */ ++static struct nla_policy brc_genl_policy[BRC_GENL_A_MAX + 1] = { ++ [BRC_GENL_A_ERR_CODE] = { .type = NLA_U32 }, ++ ++ [BRC_GENL_A_PROC_DIR] = { .type = NLA_NUL_STRING }, ++ [BRC_GENL_A_PROC_NAME] = { .type = NLA_NUL_STRING }, ++ [BRC_GENL_A_PROC_DATA] = { .type = NLA_NUL_STRING }, ++ ++ [BRC_GENL_A_FDB_DATA] = { .type = NLA_UNSPEC }, ++}; ++ ++static int ++brc_genl_dp_result(struct sk_buff *skb, struct genl_info *info) ++{ ++ unsigned long int flags; ++ int err; ++ ++ if (!info->attrs[BRC_GENL_A_ERR_CODE]) ++ return -EINVAL; ++ ++ skb = skb_clone(skb, GFP_KERNEL); ++ if (!skb) ++ return -ENOMEM; ++ ++ spin_lock_irqsave(&brc_lock, flags); ++ if (brc_seq == info->snd_seq) { ++ brc_seq++; ++ ++ if (brc_reply) ++ kfree_skb(brc_reply); ++ brc_reply = skb; ++ ++ complete(&brc_done); ++ err = 0; ++ } else { ++ kfree_skb(skb); ++ err = -ESTALE; ++ } ++ spin_unlock_irqrestore(&brc_lock, flags); ++ ++ return err; ++} ++ ++static struct genl_ops brc_genl_ops_dp_result = { ++ .cmd = BRC_GENL_C_DP_RESULT, ++ .flags = GENL_ADMIN_PERM, /* Requires CAP_NET_ADMIN privelege. */ ++ .policy = brc_genl_policy, ++ .doit = brc_genl_dp_result, ++ .dumpit = NULL ++}; ++ ++static struct genl_ops brc_genl_ops_set_proc = { ++ .cmd = BRC_GENL_C_SET_PROC, ++ .flags = GENL_ADMIN_PERM, /* Requires CAP_NET_ADMIN privelege. */ ++ .policy = brc_genl_policy, ++ .doit = brc_genl_set_proc, ++ .dumpit = NULL ++}; ++ ++static struct sk_buff *brc_send_command(struct sk_buff *request, struct nlattr **attrs) ++{ ++ unsigned long int flags; ++ struct sk_buff *reply; ++ int error; ++ ++ mutex_lock(&brc_serial); ++ ++ /* Increment sequence number first, so that we ignore any replies ++ * to stale requests. */ ++ spin_lock_irqsave(&brc_lock, flags); ++ nlmsg_hdr(request)->nlmsg_seq = ++brc_seq; ++ INIT_COMPLETION(brc_done); ++ spin_unlock_irqrestore(&brc_lock, flags); ++ ++ nlmsg_end(request, nlmsg_hdr(request)); ++ ++ /* Send message. */ ++ error = genlmsg_multicast(request, 0, brc_mc_group.id, GFP_KERNEL); ++ if (error < 0) ++ goto error; ++ ++ /* Wait for reply. */ ++ error = -ETIMEDOUT; ++ if (!wait_for_completion_timeout(&brc_done, BRC_TIMEOUT)) ++ goto error; ++ ++ /* Grab reply. */ ++ spin_lock_irqsave(&brc_lock, flags); ++ reply = brc_reply; ++ brc_reply = NULL; ++ spin_unlock_irqrestore(&brc_lock, flags); ++ ++ mutex_unlock(&brc_serial); ++ ++ /* Re-parse message. Can't fail, since it parsed correctly once ++ * already. */ ++ error = nlmsg_parse(nlmsg_hdr(reply), GENL_HDRLEN, ++ attrs, BRC_GENL_A_MAX, brc_genl_policy); ++ WARN_ON(error); ++ ++ return reply; ++ ++error: ++ mutex_unlock(&brc_serial); ++ return ERR_PTR(error); ++} ++ ++static int ++__init brc_init(void) ++{ ++ int err; ++ ++ printk("Open vSwitch Bridge Compatibility, built "__DATE__" "__TIME__"\n"); ++ ++ /* Set the bridge ioctl handler */ ++ brioctl_set(brc_ioctl_deviceless_stub); ++ ++ /* Set the openvswitch_mod device ioctl handler */ ++ dp_ioctl_hook = brc_dev_ioctl; ++ ++ /* Randomize the initial sequence number. This is not a security ++ * feature; it only helps avoid crossed wires between userspace and ++ * the kernel when the module is unloaded and reloaded. */ ++ brc_seq = net_random(); ++ ++ /* Register generic netlink family to communicate changes to ++ * userspace. */ ++ err = genl_register_family(&brc_genl_family); ++ if (err) ++ goto error; ++ ++ err = genl_register_ops(&brc_genl_family, &brc_genl_ops_query_dp); ++ if (err != 0) ++ goto err_unregister; ++ ++ err = genl_register_ops(&brc_genl_family, &brc_genl_ops_dp_result); ++ if (err != 0) ++ goto err_unregister; ++ ++ err = genl_register_ops(&brc_genl_family, &brc_genl_ops_set_proc); ++ if (err != 0) ++ goto err_unregister; ++ ++ strcpy(brc_mc_group.name, "brcompat"); ++ err = genl_register_mc_group(&brc_genl_family, &brc_mc_group); ++ if (err < 0) ++ goto err_unregister; ++ ++ return 0; ++ ++err_unregister: ++ genl_unregister_family(&brc_genl_family); ++error: ++ printk(KERN_EMERG "brcompat: failed to install!"); ++ return err; ++} ++ ++static void ++brc_cleanup(void) ++{ ++ /* Unregister ioctl hooks */ ++ dp_ioctl_hook = NULL; ++ brioctl_set(NULL); ++ ++ genl_unregister_family(&brc_genl_family); ++ brc_procfs_exit(); ++} ++ ++module_init(brc_init); ++module_exit(brc_cleanup); ++ ++MODULE_DESCRIPTION("Open vSwitch bridge compatibility"); ++MODULE_AUTHOR("Nicira Networks"); ++MODULE_LICENSE("GPL"); +diff -r 9dfeb6b4054e net/vswitch/compat.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/compat.h Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,25 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++#ifndef COMPAT_H ++#define COMPAT_H 1 ++ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ++ ++#include "compat26.h" ++ ++#else ++ ++#include "compat24.h" ++ ++#endif ++ ++ ++#endif /* compat.h */ +diff -r 9dfeb6b4054e net/vswitch/datapath.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/datapath.c Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,1689 @@ ++/* ++ * Copyright (c) 2007, 2008, 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++/* Functions for managing the dp interface/device. */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "openvswitch/datapath-protocol.h" ++#include "datapath.h" ++#include "actions.h" ++#include "dp_dev.h" ++#include "flow.h" ++ ++#include "compat.h" ++ ++ ++int (*dp_ioctl_hook)(struct net_device *dev, struct ifreq *rq, int cmd); ++EXPORT_SYMBOL(dp_ioctl_hook); ++ ++/* Datapaths. Protected on the read side by rcu_read_lock, on the write side ++ * by dp_mutex. ++ * ++ * dp_mutex nests inside the RTNL lock: if you need both you must take the RTNL ++ * lock first. ++ * ++ * It is safe to access the datapath and net_bridge_port structures with just ++ * dp_mutex. ++ */ ++static struct datapath *dps[ODP_MAX]; ++static DEFINE_MUTEX(dp_mutex); ++ ++/* Number of milliseconds between runs of the maintenance thread. */ ++#define MAINT_SLEEP_MSECS 1000 ++ ++static int new_nbp(struct datapath *, struct net_device *, int port_no); ++ ++/* Must be called with rcu_read_lock or dp_mutex. */ ++struct datapath *get_dp(int dp_idx) ++{ ++ if (dp_idx < 0 || dp_idx >= ODP_MAX) ++ return NULL; ++ return rcu_dereference(dps[dp_idx]); ++} ++EXPORT_SYMBOL_GPL(get_dp); ++ ++struct datapath *get_dp_locked(int dp_idx) ++{ ++ struct datapath *dp; ++ ++ mutex_lock(&dp_mutex); ++ dp = get_dp(dp_idx); ++ if (dp) ++ mutex_lock(&dp->mutex); ++ mutex_unlock(&dp_mutex); ++ return dp; ++} ++ ++static inline size_t br_nlmsg_size(void) ++{ ++ return NLMSG_ALIGN(sizeof(struct ifinfomsg)) ++ + nla_total_size(IFNAMSIZ) /* IFLA_IFNAME */ ++ + nla_total_size(MAX_ADDR_LEN) /* IFLA_ADDRESS */ ++ + nla_total_size(4) /* IFLA_MASTER */ ++ + nla_total_size(4) /* IFLA_MTU */ ++ + nla_total_size(4) /* IFLA_LINK */ ++ + nla_total_size(1); /* IFLA_OPERSTATE */ ++} ++ ++static int dp_fill_ifinfo(struct sk_buff *skb, ++ const struct net_bridge_port *port, ++ int event, unsigned int flags) ++{ ++ const struct datapath *dp = port->dp; ++ const struct net_device *dev = port->dev; ++ struct ifinfomsg *hdr; ++ struct nlmsghdr *nlh; ++ ++ nlh = nlmsg_put(skb, 0, 0, event, sizeof(*hdr), flags); ++ if (nlh == NULL) ++ return -EMSGSIZE; ++ ++ hdr = nlmsg_data(nlh); ++ hdr->ifi_family = AF_BRIDGE; ++ hdr->__ifi_pad = 0; ++ hdr->ifi_type = dev->type; ++ hdr->ifi_index = dev->ifindex; ++ hdr->ifi_flags = dev_get_flags(dev); ++ hdr->ifi_change = 0; ++ ++ NLA_PUT_STRING(skb, IFLA_IFNAME, dev->name); ++ NLA_PUT_U32(skb, IFLA_MASTER, dp->ports[ODPP_LOCAL]->dev->ifindex); ++ NLA_PUT_U32(skb, IFLA_MTU, dev->mtu); ++#ifdef IFLA_OPERSTATE ++ NLA_PUT_U8(skb, IFLA_OPERSTATE, ++ netif_running(dev) ? dev->operstate : IF_OPER_DOWN); ++#endif ++ ++ if (dev->addr_len) ++ NLA_PUT(skb, IFLA_ADDRESS, dev->addr_len, dev->dev_addr); ++ ++ if (dev->ifindex != dev->iflink) ++ NLA_PUT_U32(skb, IFLA_LINK, dev->iflink); ++ ++ return nlmsg_end(skb, nlh); ++ ++nla_put_failure: ++ nlmsg_cancel(skb, nlh); ++ return -EMSGSIZE; ++} ++ ++static void dp_ifinfo_notify(int event, struct net_bridge_port *port) ++{ ++ struct net *net = dev_net(port->dev); ++ struct sk_buff *skb; ++ int err = -ENOBUFS; ++ ++ skb = nlmsg_new(br_nlmsg_size(), GFP_KERNEL); ++ if (skb == NULL) ++ goto errout; ++ ++ err = dp_fill_ifinfo(skb, port, event, 0); ++ if (err < 0) { ++ /* -EMSGSIZE implies BUG in br_nlmsg_size() */ ++ WARN_ON(err == -EMSGSIZE); ++ kfree_skb(skb); ++ goto errout; ++ } ++ rtnl_notify(skb, net, 0, RTNLGRP_LINK, NULL, GFP_KERNEL); ++ return; ++errout: ++ if (err < 0) ++ rtnl_set_sk_err(net, RTNLGRP_LINK, err); ++} ++ ++static void release_dp(struct kobject *kobj) ++{ ++ struct datapath *dp = container_of(kobj, struct datapath, ifobj); ++ kfree(dp); ++} ++ ++struct kobj_type dp_ktype = { ++ .release = release_dp ++}; ++ ++static int create_dp(int dp_idx, const char __user *devnamep) ++{ ++ struct net_device *dp_dev; ++ char devname[IFNAMSIZ]; ++ struct datapath *dp; ++ int err; ++ int i; ++ ++ if (devnamep) { ++ err = -EFAULT; ++ if (strncpy_from_user(devname, devnamep, IFNAMSIZ - 1) < 0) ++ goto err; ++ devname[IFNAMSIZ - 1] = '\0'; ++ } else { ++ snprintf(devname, sizeof devname, "of%d", dp_idx); ++ } ++ ++ rtnl_lock(); ++ mutex_lock(&dp_mutex); ++ err = -ENODEV; ++ if (!try_module_get(THIS_MODULE)) ++ goto err_unlock; ++ ++ /* Exit early if a datapath with that number already exists. ++ * (We don't use -EEXIST because that's ambiguous with 'devname' ++ * conflicting with an existing network device name.) */ ++ err = -EBUSY; ++ if (get_dp(dp_idx)) ++ goto err_put_module; ++ ++ err = -ENOMEM; ++ dp = kzalloc(sizeof *dp, GFP_KERNEL); ++ if (dp == NULL) ++ goto err_put_module; ++ INIT_LIST_HEAD(&dp->port_list); ++ mutex_init(&dp->mutex); ++ dp->dp_idx = dp_idx; ++ for (i = 0; i < DP_N_QUEUES; i++) ++ skb_queue_head_init(&dp->queues[i]); ++ init_waitqueue_head(&dp->waitqueue); ++ ++ /* Initialize kobject for bridge. This will be added as ++ * /sys/class/net//brif later, if sysfs is enabled. */ ++ dp->ifobj.kset = NULL; ++ kobject_init(&dp->ifobj, &dp_ktype); ++ ++ /* Allocate table. */ ++ err = -ENOMEM; ++ rcu_assign_pointer(dp->table, dp_table_create(DP_L1_SIZE)); ++ if (!dp->table) ++ goto err_free_dp; ++ ++ /* Setup our datapath device */ ++ dp_dev = dp_dev_create(dp, devname, ODPP_LOCAL); ++ err = PTR_ERR(dp_dev); ++ if (IS_ERR(dp_dev)) ++ goto err_destroy_table; ++ ++ err = new_nbp(dp, dp_dev, ODPP_LOCAL); ++ if (err) { ++ dp_dev_destroy(dp_dev); ++ goto err_destroy_table; ++ } ++ ++ dp->drop_frags = 0; ++ dp->stats_percpu = alloc_percpu(struct dp_stats_percpu); ++ if (!dp->stats_percpu) ++ goto err_destroy_local_port; ++ ++ rcu_assign_pointer(dps[dp_idx], dp); ++ mutex_unlock(&dp_mutex); ++ rtnl_unlock(); ++ ++ dp_sysfs_add_dp(dp); ++ ++ return 0; ++ ++err_destroy_local_port: ++ dp_del_port(dp->ports[ODPP_LOCAL]); ++err_destroy_table: ++ dp_table_destroy(dp->table, 0); ++err_free_dp: ++ kfree(dp); ++err_put_module: ++ module_put(THIS_MODULE); ++err_unlock: ++ mutex_unlock(&dp_mutex); ++ rtnl_unlock(); ++err: ++ return err; ++} ++ ++static void do_destroy_dp(struct datapath *dp) ++{ ++ struct net_bridge_port *p, *n; ++ int i; ++ ++ list_for_each_entry_safe (p, n, &dp->port_list, node) ++ if (p->port_no != ODPP_LOCAL) ++ dp_del_port(p); ++ ++ dp_sysfs_del_dp(dp); ++ ++ rcu_assign_pointer(dps[dp->dp_idx], NULL); ++ ++ dp_del_port(dp->ports[ODPP_LOCAL]); ++ ++ dp_table_destroy(dp->table, 1); ++ ++ for (i = 0; i < DP_N_QUEUES; i++) ++ skb_queue_purge(&dp->queues[i]); ++ for (i = 0; i < DP_MAX_GROUPS; i++) ++ kfree(dp->groups[i]); ++ free_percpu(dp->stats_percpu); ++ kobject_put(&dp->ifobj); ++ module_put(THIS_MODULE); ++} ++ ++static int destroy_dp(int dp_idx) ++{ ++ struct datapath *dp; ++ int err; ++ ++ rtnl_lock(); ++ mutex_lock(&dp_mutex); ++ dp = get_dp(dp_idx); ++ err = -ENODEV; ++ if (!dp) ++ goto err_unlock; ++ ++ do_destroy_dp(dp); ++ err = 0; ++ ++err_unlock: ++ mutex_unlock(&dp_mutex); ++ rtnl_unlock(); ++ return err; ++} ++ ++static void release_nbp(struct kobject *kobj) ++{ ++ struct net_bridge_port *p = container_of(kobj, struct net_bridge_port, kobj); ++ kfree(p); ++} ++ ++struct kobj_type brport_ktype = { ++#ifdef CONFIG_SYSFS ++ .sysfs_ops = &brport_sysfs_ops, ++#endif ++ .release = release_nbp ++}; ++ ++/* Called with RTNL lock and dp_mutex. */ ++static int new_nbp(struct datapath *dp, struct net_device *dev, int port_no) ++{ ++ struct net_bridge_port *p; ++ ++ if (dev->br_port != NULL) ++ return -EBUSY; ++ ++ p = kzalloc(sizeof(*p), GFP_KERNEL); ++ if (!p) ++ return -ENOMEM; ++ ++ dev_set_promiscuity(dev, 1); ++ dev_hold(dev); ++ p->port_no = port_no; ++ p->dp = dp; ++ p->dev = dev; ++ if (!is_dp_dev(dev)) ++ rcu_assign_pointer(dev->br_port, p); ++ else { ++ /* It would make sense to assign dev->br_port here too, but ++ * that causes packets received on internal ports to get caught ++ * in dp_frame_hook(). In turn dp_frame_hook() can reject them ++ * back to network stack, but that's a waste of time. */ ++ } ++ rcu_assign_pointer(dp->ports[port_no], p); ++ list_add_rcu(&p->node, &dp->port_list); ++ dp->n_ports++; ++ ++ /* Initialize kobject for bridge. This will be added as ++ * /sys/class/net//brport later, if sysfs is enabled. */ ++ p->kobj.kset = NULL; ++ kobject_init(&p->kobj, &brport_ktype); ++ ++ dp_ifinfo_notify(RTM_NEWLINK, p); ++ ++ return 0; ++} ++ ++static int add_port(int dp_idx, struct odp_port __user *portp) ++{ ++ struct net_device *dev; ++ struct datapath *dp; ++ struct odp_port port; ++ int port_no; ++ int err; ++ ++ err = -EFAULT; ++ if (copy_from_user(&port, portp, sizeof port)) ++ goto out; ++ port.devname[IFNAMSIZ - 1] = '\0'; ++ ++ rtnl_lock(); ++ dp = get_dp_locked(dp_idx); ++ err = -ENODEV; ++ if (!dp) ++ goto out_unlock_rtnl; ++ ++ for (port_no = 1; port_no < DP_MAX_PORTS; port_no++) ++ if (!dp->ports[port_no]) ++ goto got_port_no; ++ err = -EFBIG; ++ goto out_unlock_dp; ++ ++got_port_no: ++ if (!(port.flags & ODP_PORT_INTERNAL)) { ++ err = -ENODEV; ++ dev = dev_get_by_name(&init_net, port.devname); ++ if (!dev) ++ goto out_unlock_dp; ++ ++ err = -EINVAL; ++ if (dev->flags & IFF_LOOPBACK || dev->type != ARPHRD_ETHER || ++ is_dp_dev(dev)) ++ goto out_put; ++ } else { ++ dev = dp_dev_create(dp, port.devname, port_no); ++ err = PTR_ERR(dev); ++ if (IS_ERR(dev)) ++ goto out_unlock_dp; ++ dev_hold(dev); ++ } ++ ++ err = new_nbp(dp, dev, port_no); ++ if (err) ++ goto out_put; ++ ++ dp_sysfs_add_if(dp->ports[port_no]); ++ ++ err = __put_user(port_no, &port.port); ++ ++out_put: ++ dev_put(dev); ++out_unlock_dp: ++ mutex_unlock(&dp->mutex); ++out_unlock_rtnl: ++ rtnl_unlock(); ++out: ++ return err; ++} ++ ++int dp_del_port(struct net_bridge_port *p) ++{ ++ ASSERT_RTNL(); ++ ++ if (p->port_no != ODPP_LOCAL) ++ dp_sysfs_del_if(p); ++ dp_ifinfo_notify(RTM_DELLINK, p); ++ ++ p->dp->n_ports--; ++ ++ if (is_dp_dev(p->dev)) { ++ /* Make sure that no packets arrive from now on, since ++ * dp_dev_xmit() will try to find itself through ++ * p->dp->ports[], and we're about to set that to null. */ ++ netif_tx_disable(p->dev); ++ } ++ ++ /* First drop references to device. */ ++ dev_set_promiscuity(p->dev, -1); ++ list_del_rcu(&p->node); ++ rcu_assign_pointer(p->dp->ports[p->port_no], NULL); ++ rcu_assign_pointer(p->dev->br_port, NULL); ++ ++ /* Then wait until no one is still using it, and destroy it. */ ++ synchronize_rcu(); ++ ++ if (is_dp_dev(p->dev)) ++ dp_dev_destroy(p->dev); ++ dev_put(p->dev); ++ kobject_put(&p->kobj); ++ ++ return 0; ++} ++ ++static int del_port(int dp_idx, int port_no) ++{ ++ struct net_bridge_port *p; ++ struct datapath *dp; ++ LIST_HEAD(dp_devs); ++ int err; ++ ++ err = -EINVAL; ++ if (port_no < 0 || port_no >= DP_MAX_PORTS || port_no == ODPP_LOCAL) ++ goto out; ++ ++ rtnl_lock(); ++ dp = get_dp_locked(dp_idx); ++ err = -ENODEV; ++ if (!dp) ++ goto out_unlock_rtnl; ++ ++ p = dp->ports[port_no]; ++ err = -ENOENT; ++ if (!p) ++ goto out_unlock_dp; ++ ++ err = dp_del_port(p); ++ ++out_unlock_dp: ++ mutex_unlock(&dp->mutex); ++out_unlock_rtnl: ++ rtnl_unlock(); ++out: ++ return err; ++} ++ ++/* Must be called with rcu_read_lock. */ ++static void ++do_port_input(struct net_bridge_port *p, struct sk_buff *skb) ++{ ++ /* Make our own copy of the packet. Otherwise we will mangle the ++ * packet for anyone who came before us (e.g. tcpdump via AF_PACKET). ++ * (No one comes after us, since we tell handle_bridge() that we took ++ * the packet.) */ ++ skb = skb_share_check(skb, GFP_ATOMIC); ++ if (!skb) ++ return; ++ ++ /* Push the Ethernet header back on. */ ++ skb_push(skb, ETH_HLEN); ++ skb_reset_mac_header(skb); ++ dp_process_received_packet(skb, p); ++} ++ ++/* Must be called with rcu_read_lock and with bottom-halves disabled. */ ++void dp_process_received_packet(struct sk_buff *skb, struct net_bridge_port *p) ++{ ++ struct datapath *dp = p->dp; ++ struct dp_stats_percpu *stats; ++ struct odp_flow_key key; ++ struct sw_flow *flow; ++ ++ WARN_ON_ONCE(skb_shared(skb)); ++ ++ /* BHs are off so we don't have to use get_cpu()/put_cpu() here. */ ++ stats = percpu_ptr(dp->stats_percpu, smp_processor_id()); ++ ++ if (flow_extract(skb, p ? p->port_no : ODPP_NONE, &key)) { ++ if (dp->drop_frags) { ++ kfree_skb(skb); ++ stats->n_frags++; ++ return; ++ } ++ } ++ ++ flow = dp_table_lookup(rcu_dereference(dp->table), &key); ++ if (flow) { ++ struct sw_flow_actions *acts = rcu_dereference(flow->sf_acts); ++ flow_used(flow, skb); ++ execute_actions(dp, skb, &key, acts->actions, acts->n_actions, ++ GFP_ATOMIC); ++ stats->n_hit++; ++ } else { ++ stats->n_missed++; ++ dp_output_control(dp, skb, _ODPL_MISS_NR, 0); ++ } ++} ++ ++/* ++ * Used as br_handle_frame_hook. (Cannot run bridge at the same time, even on ++ * different set of devices!) ++ */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) ++/* Called with rcu_read_lock and bottom-halves disabled. */ ++static struct sk_buff *dp_frame_hook(struct net_bridge_port *p, ++ struct sk_buff *skb) ++{ ++ do_port_input(p, skb); ++ return NULL; ++} ++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ++/* Called with rcu_read_lock and bottom-halves disabled. */ ++static int dp_frame_hook(struct net_bridge_port *p, struct sk_buff **pskb) ++{ ++ do_port_input(p, *pskb); ++ return 1; ++} ++#else ++#error ++#endif ++ ++#if defined(CONFIG_XEN) && LINUX_VERSION_CODE == KERNEL_VERSION(2,6,18) ++/* This code is copied verbatim from net/dev/core.c in Xen's ++ * linux-2.6.18-92.1.10.el5.xs5.0.0.394.644. We can't call those functions ++ * directly because they aren't exported. */ ++static int skb_pull_up_to(struct sk_buff *skb, void *ptr) ++{ ++ if (ptr < (void *)skb->tail) ++ return 1; ++ if (__pskb_pull_tail(skb, ++ ptr - (void *)skb->data - skb_headlen(skb))) { ++ return 1; ++ } else { ++ return 0; ++ } ++} ++ ++int vswitch_skb_checksum_setup(struct sk_buff *skb) ++{ ++ if (skb->proto_csum_blank) { ++ if (skb->protocol != htons(ETH_P_IP)) ++ goto out; ++ if (!skb_pull_up_to(skb, skb->nh.iph + 1)) ++ goto out; ++ skb->h.raw = (unsigned char *)skb->nh.iph + 4*skb->nh.iph->ihl; ++ switch (skb->nh.iph->protocol) { ++ case IPPROTO_TCP: ++ skb->csum = offsetof(struct tcphdr, check); ++ break; ++ case IPPROTO_UDP: ++ skb->csum = offsetof(struct udphdr, check); ++ break; ++ default: ++ if (net_ratelimit()) ++ printk(KERN_ERR "Attempting to checksum a non-" ++ "TCP/UDP packet, dropping a protocol" ++ " %d packet", skb->nh.iph->protocol); ++ goto out; ++ } ++ if (!skb_pull_up_to(skb, skb->h.raw + skb->csum + 2)) ++ goto out; ++ skb->ip_summed = CHECKSUM_HW; ++ skb->proto_csum_blank = 0; ++ } ++ return 0; ++out: ++ return -EPROTO; ++} ++#else ++int vswitch_skb_checksum_setup(struct sk_buff *skb) { return 0; } ++#endif /* CONFIG_XEN && linux == 2.6.18 */ ++ ++/* Append each packet in 'skb' list to 'queue'. There will be only one packet ++ * unless we broke up a GSO packet. */ ++static int ++queue_control_packets(struct sk_buff *skb, struct sk_buff_head *queue, ++ int queue_no, u32 arg) ++{ ++ struct sk_buff *nskb; ++ int port_no; ++ int err; ++ ++ port_no = ODPP_LOCAL; ++ if (skb->dev) { ++ if (skb->dev->br_port) ++ port_no = skb->dev->br_port->port_no; ++ else if (is_dp_dev(skb->dev)) ++ port_no = dp_dev_priv(skb->dev)->port_no; ++ } ++ ++ do { ++ struct odp_msg *header; ++ ++ nskb = skb->next; ++ skb->next = NULL; ++ ++ /* If a checksum-deferred packet is forwarded to the ++ * controller, correct the pointers and checksum. This happens ++ * on a regular basis only on Xen, on which VMs can pass up ++ * packets that do not have their checksum computed. ++ */ ++ err = vswitch_skb_checksum_setup(skb); ++ if (err) ++ goto err_kfree_skbs; ++#ifndef CHECKSUM_HW ++ if (skb->ip_summed == CHECKSUM_PARTIAL) { ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) ++ /* Until 2.6.22, the start of the transport header was ++ * also the start of data to be checksummed. Linux ++ * 2.6.22 introduced the csum_start field for this ++ * purpose, but we should point the transport header to ++ * it anyway for backward compatibility, as ++ * dev_queue_xmit() does even in 2.6.28. */ ++ skb_set_transport_header(skb, skb->csum_start - ++ skb_headroom(skb)); ++#endif ++ err = skb_checksum_help(skb); ++ if (err) ++ goto err_kfree_skbs; ++ } ++#else ++ if (skb->ip_summed == CHECKSUM_HW) { ++ err = skb_checksum_help(skb, 0); ++ if (err) ++ goto err_kfree_skbs; ++ } ++#endif ++ ++ err = skb_cow(skb, sizeof *header); ++ if (err) ++ goto err_kfree_skbs; ++ ++ header = (struct odp_msg*)__skb_push(skb, sizeof *header); ++ header->type = queue_no; ++ header->length = skb->len; ++ header->port = port_no; ++ header->reserved = 0; ++ header->arg = arg; ++ skb_queue_tail(queue, skb); ++ ++ skb = nskb; ++ } while (skb); ++ return 0; ++ ++err_kfree_skbs: ++ kfree_skb(skb); ++ while ((skb = nskb) != NULL) { ++ nskb = skb->next; ++ kfree_skb(skb); ++ } ++ return err; ++} ++ ++int ++dp_output_control(struct datapath *dp, struct sk_buff *skb, int queue_no, ++ u32 arg) ++{ ++ struct dp_stats_percpu *stats; ++ struct sk_buff_head *queue; ++ int err; ++ ++ WARN_ON_ONCE(skb_shared(skb)); ++ BUG_ON(queue_no != _ODPL_MISS_NR && queue_no != _ODPL_ACTION_NR); ++ ++ queue = &dp->queues[queue_no]; ++ err = -ENOBUFS; ++ if (skb_queue_len(queue) >= DP_MAX_QUEUE_LEN) ++ goto err_kfree_skb; ++ ++ /* Break apart GSO packets into their component pieces. Otherwise ++ * userspace may try to stuff a 64kB packet into a 1500-byte MTU. */ ++ if (skb_is_gso(skb)) { ++ struct sk_buff *nskb = skb_gso_segment(skb, 0); ++ if (nskb) { ++ kfree_skb(skb); ++ skb = nskb; ++ if (unlikely(IS_ERR(skb))) { ++ err = PTR_ERR(skb); ++ goto err; ++ } ++ } else { ++ /* XXX This case might not be possible. It's hard to ++ * tell from the skb_gso_segment() code and comment. */ ++ } ++ } ++ ++ err = queue_control_packets(skb, queue, queue_no, arg); ++ wake_up_interruptible(&dp->waitqueue); ++ return err; ++ ++err_kfree_skb: ++ kfree_skb(skb); ++err: ++ stats = percpu_ptr(dp->stats_percpu, get_cpu()); ++ stats->n_lost++; ++ put_cpu(); ++ ++ return err; ++} ++ ++static int flush_flows(struct datapath *dp) ++{ ++ dp->n_flows = 0; ++ return dp_table_flush(dp); ++} ++ ++static int validate_actions(const struct sw_flow_actions *actions) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < actions->n_actions; i++) { ++ const union odp_action *a = &actions->actions[i]; ++ switch (a->type) { ++ case ODPAT_OUTPUT: ++ if (a->output.port >= DP_MAX_PORTS) ++ return -EINVAL; ++ break; ++ ++ case ODPAT_OUTPUT_GROUP: ++ if (a->output_group.group >= DP_MAX_GROUPS) ++ return -EINVAL; ++ break; ++ ++ case ODPAT_SET_VLAN_VID: ++ if (a->vlan_vid.vlan_vid & htons(~VLAN_VID_MASK)) ++ return -EINVAL; ++ break; ++ ++ case ODPAT_SET_VLAN_PCP: ++ if (a->vlan_pcp.vlan_pcp & ~VLAN_PCP_MASK) ++ return -EINVAL; ++ break; ++ ++ default: ++ if (a->type >= ODPAT_N_ACTIONS) ++ return -EOPNOTSUPP; ++ break; ++ } ++ } ++ ++ return 0; ++} ++ ++static struct sw_flow_actions *get_actions(const struct odp_flow *flow) ++{ ++ struct sw_flow_actions *actions; ++ int error; ++ ++ actions = flow_actions_alloc(flow->n_actions); ++ error = PTR_ERR(actions); ++ if (IS_ERR(actions)) ++ goto error; ++ ++ error = -EFAULT; ++ if (copy_from_user(actions->actions, flow->actions, ++ flow->n_actions * sizeof(union odp_action))) ++ goto error_free_actions; ++ error = validate_actions(actions); ++ if (error) ++ goto error_free_actions; ++ ++ return actions; ++ ++error_free_actions: ++ kfree(actions); ++error: ++ return ERR_PTR(error); ++} ++ ++static void get_stats(struct sw_flow *flow, struct odp_flow_stats *stats) ++{ ++ if (flow->used.tv_sec) { ++ stats->used_sec = flow->used.tv_sec; ++ stats->used_nsec = flow->used.tv_nsec; ++ } else { ++ stats->used_sec = 0; ++ stats->used_nsec = 0; ++ } ++ stats->n_packets = flow->packet_count; ++ stats->n_bytes = flow->byte_count; ++ stats->ip_tos = flow->ip_tos; ++ stats->tcp_flags = flow->tcp_flags; ++ stats->error = 0; ++} ++ ++static void clear_stats(struct sw_flow *flow) ++{ ++ flow->used.tv_sec = flow->used.tv_nsec = 0; ++ flow->tcp_flags = 0; ++ flow->ip_tos = 0; ++ flow->packet_count = 0; ++ flow->byte_count = 0; ++} ++ ++static int put_flow(struct datapath *dp, struct odp_flow_put __user *ufp) ++{ ++ struct odp_flow_put uf; ++ struct sw_flow *flow; ++ struct dp_table *table; ++ struct odp_flow_stats stats; ++ int error; ++ ++ error = -EFAULT; ++ if (copy_from_user(&uf, ufp, sizeof(struct odp_flow_put))) ++ goto error; ++ uf.flow.key.reserved = 0; ++ ++ table = rcu_dereference(dp->table); ++ flow = dp_table_lookup(table, &uf.flow.key); ++ if (!flow) { ++ /* No such flow. */ ++ struct sw_flow_actions *acts; ++ ++ error = -ENOENT; ++ if (!(uf.flags & ODPPF_CREATE)) ++ goto error; ++ ++ /* Expand table, if necessary, to make room. */ ++ if (dp->n_flows >= table->n_buckets) { ++ error = -ENOSPC; ++ if (table->n_buckets >= DP_MAX_BUCKETS) ++ goto error; ++ ++ error = dp_table_expand(dp); ++ if (error) ++ goto error; ++ table = rcu_dereference(dp->table); ++ } ++ ++ /* Allocate flow. */ ++ error = -ENOMEM; ++ flow = kmem_cache_alloc(flow_cache, GFP_KERNEL); ++ if (flow == NULL) ++ goto error; ++ flow->key = uf.flow.key; ++ spin_lock_init(&flow->lock); ++ clear_stats(flow); ++ ++ /* Obtain actions. */ ++ acts = get_actions(&uf.flow); ++ error = PTR_ERR(acts); ++ if (IS_ERR(acts)) ++ goto error_free_flow; ++ rcu_assign_pointer(flow->sf_acts, acts); ++ ++ /* Put flow in bucket. */ ++ error = dp_table_insert(table, flow); ++ if (error) ++ goto error_free_flow_acts; ++ dp->n_flows++; ++ memset(&stats, 0, sizeof(struct odp_flow_stats)); ++ } else { ++ /* We found a matching flow. */ ++ struct sw_flow_actions *old_acts, *new_acts; ++ unsigned long int flags; ++ ++ /* Bail out if we're not allowed to modify an existing flow. */ ++ error = -EEXIST; ++ if (!(uf.flags & ODPPF_MODIFY)) ++ goto error; ++ ++ /* Swap actions. */ ++ new_acts = get_actions(&uf.flow); ++ error = PTR_ERR(new_acts); ++ if (IS_ERR(new_acts)) ++ goto error; ++ old_acts = rcu_dereference(flow->sf_acts); ++ if (old_acts->n_actions != new_acts->n_actions || ++ memcmp(old_acts->actions, new_acts->actions, ++ sizeof(union odp_action) * old_acts->n_actions)) { ++ rcu_assign_pointer(flow->sf_acts, new_acts); ++ flow_deferred_free_acts(old_acts); ++ } else { ++ kfree(new_acts); ++ } ++ ++ /* Fetch stats, then clear them if necessary. */ ++ spin_lock_irqsave(&flow->lock, flags); ++ get_stats(flow, &stats); ++ if (uf.flags & ODPPF_ZERO_STATS) ++ clear_stats(flow); ++ spin_unlock_irqrestore(&flow->lock, flags); ++ } ++ ++ /* Copy stats to userspace. */ ++ if (__copy_to_user(&ufp->flow.stats, &stats, ++ sizeof(struct odp_flow_stats))) ++ return -EFAULT; ++ return 0; ++ ++error_free_flow_acts: ++ kfree(flow->sf_acts); ++error_free_flow: ++ kmem_cache_free(flow_cache, flow); ++error: ++ return error; ++} ++ ++static int put_actions(const struct sw_flow *flow, struct odp_flow __user *ufp) ++{ ++ union odp_action __user *actions; ++ struct sw_flow_actions *sf_acts; ++ u32 n_actions; ++ ++ if (__get_user(actions, &ufp->actions) || ++ __get_user(n_actions, &ufp->n_actions)) ++ return -EFAULT; ++ ++ if (!n_actions) ++ return 0; ++ ++ sf_acts = rcu_dereference(flow->sf_acts); ++ if (__put_user(sf_acts->n_actions, &ufp->n_actions) || ++ (actions && copy_to_user(actions, sf_acts->actions, ++ sizeof(union odp_action) * ++ min(sf_acts->n_actions, n_actions)))) ++ return -EFAULT; ++ ++ return 0; ++} ++ ++static int answer_query(struct sw_flow *flow, struct odp_flow __user *ufp) ++{ ++ struct odp_flow_stats stats; ++ unsigned long int flags; ++ ++ spin_lock_irqsave(&flow->lock, flags); ++ get_stats(flow, &stats); ++ spin_unlock_irqrestore(&flow->lock, flags); ++ ++ if (__copy_to_user(&ufp->stats, &stats, sizeof(struct odp_flow_stats))) ++ return -EFAULT; ++ return put_actions(flow, ufp); ++} ++ ++static int del_flow(struct datapath *dp, struct odp_flow __user *ufp) ++{ ++ struct dp_table *table = rcu_dereference(dp->table); ++ struct odp_flow uf; ++ struct sw_flow *flow; ++ int error; ++ ++ error = -EFAULT; ++ if (copy_from_user(&uf, ufp, sizeof uf)) ++ goto error; ++ uf.key.reserved = 0; ++ ++ flow = dp_table_lookup(table, &uf.key); ++ error = -ENOENT; ++ if (!flow) ++ goto error; ++ ++ /* XXX redundant lookup */ ++ error = dp_table_delete(table, flow); ++ if (error) ++ goto error; ++ ++ /* XXX These statistics might lose a few packets, since other CPUs can ++ * be using this flow. We used to synchronize_rcu() to make sure that ++ * we get completely accurate stats, but that blows our performance, ++ * badly. */ ++ dp->n_flows--; ++ error = answer_query(flow, ufp); ++ flow_deferred_free(flow); ++ ++error: ++ return error; ++} ++ ++static int query_flows(struct datapath *dp, const struct odp_flowvec *flowvec) ++{ ++ struct dp_table *table = rcu_dereference(dp->table); ++ int i; ++ for (i = 0; i < flowvec->n_flows; i++) { ++ struct __user odp_flow *ufp = &flowvec->flows[i]; ++ struct odp_flow uf; ++ struct sw_flow *flow; ++ int error; ++ ++ if (__copy_from_user(&uf, ufp, sizeof uf)) ++ return -EFAULT; ++ uf.key.reserved = 0; ++ ++ flow = dp_table_lookup(table, &uf.key); ++ if (!flow) ++ error = __put_user(ENOENT, &ufp->stats.error); ++ else ++ error = answer_query(flow, ufp); ++ if (error) ++ return -EFAULT; ++ } ++ return flowvec->n_flows; ++} ++ ++struct list_flows_cbdata { ++ struct odp_flow __user *uflows; ++ int n_flows; ++ int listed_flows; ++}; ++ ++static int list_flow(struct sw_flow *flow, void *cbdata_) ++{ ++ struct list_flows_cbdata *cbdata = cbdata_; ++ struct odp_flow __user *ufp = &cbdata->uflows[cbdata->listed_flows++]; ++ int error; ++ ++ if (__copy_to_user(&ufp->key, &flow->key, sizeof flow->key)) ++ return -EFAULT; ++ error = answer_query(flow, ufp); ++ if (error) ++ return error; ++ ++ if (cbdata->listed_flows >= cbdata->n_flows) ++ return cbdata->listed_flows; ++ return 0; ++} ++ ++static int list_flows(struct datapath *dp, const struct odp_flowvec *flowvec) ++{ ++ struct list_flows_cbdata cbdata; ++ int error; ++ ++ if (!flowvec->n_flows) ++ return 0; ++ ++ cbdata.uflows = flowvec->flows; ++ cbdata.n_flows = flowvec->n_flows; ++ cbdata.listed_flows = 0; ++ error = dp_table_foreach(rcu_dereference(dp->table), ++ list_flow, &cbdata); ++ return error ? error : cbdata.listed_flows; ++} ++ ++static int do_flowvec_ioctl(struct datapath *dp, unsigned long argp, ++ int (*function)(struct datapath *, ++ const struct odp_flowvec *)) ++{ ++ struct odp_flowvec __user *uflowvec; ++ struct odp_flowvec flowvec; ++ int retval; ++ ++ uflowvec = (struct odp_flowvec __user *)argp; ++ if (!access_ok(VERIFY_WRITE, uflowvec, sizeof *uflowvec) || ++ copy_from_user(&flowvec, uflowvec, sizeof flowvec)) ++ return -EFAULT; ++ ++ if (flowvec.n_flows > INT_MAX / sizeof(struct odp_flow)) ++ return -EINVAL; ++ ++ if (!access_ok(VERIFY_WRITE, flowvec.flows, ++ flowvec.n_flows * sizeof(struct odp_flow))) ++ return -EFAULT; ++ ++ retval = function(dp, &flowvec); ++ return (retval < 0 ? retval ++ : retval == flowvec.n_flows ? 0 ++ : __put_user(retval, &uflowvec->n_flows)); ++} ++ ++static int do_execute(struct datapath *dp, const struct odp_execute *executep) ++{ ++ struct odp_execute execute; ++ struct odp_flow_key key; ++ struct sk_buff *skb; ++ struct sw_flow_actions *actions; ++ struct ethhdr *eth; ++ int err; ++ ++ err = -EFAULT; ++ if (copy_from_user(&execute, executep, sizeof execute)) ++ goto error; ++ ++ err = -EINVAL; ++ if (execute.length < ETH_HLEN || execute.length > 65535) ++ goto error; ++ ++ err = -ENOMEM; ++ actions = flow_actions_alloc(execute.n_actions); ++ if (!actions) ++ goto error; ++ ++ err = -EFAULT; ++ if (copy_from_user(actions->actions, execute.actions, ++ execute.n_actions * sizeof *execute.actions)) ++ goto error_free_actions; ++ ++ err = validate_actions(actions); ++ if (err) ++ goto error_free_actions; ++ ++ err = -ENOMEM; ++ skb = alloc_skb(execute.length, GFP_KERNEL); ++ if (!skb) ++ goto error_free_actions; ++ if (execute.in_port < DP_MAX_PORTS) { ++ struct net_bridge_port *p = dp->ports[execute.in_port]; ++ if (p) ++ skb->dev = p->dev; ++ } ++ ++ err = -EFAULT; ++ if (copy_from_user(skb_put(skb, execute.length), execute.data, ++ execute.length)) ++ goto error_free_skb; ++ ++ skb_reset_mac_header(skb); ++ eth = eth_hdr(skb); ++ ++ /* Normally, setting the skb 'protocol' field would be handled by a ++ * call to eth_type_trans(), but it assumes there's a sending ++ * device, which we may not have. */ ++ if (ntohs(eth->h_proto) >= 1536) ++ skb->protocol = eth->h_proto; ++ else ++ skb->protocol = htons(ETH_P_802_2); ++ ++ flow_extract(skb, execute.in_port, &key); ++ err = execute_actions(dp, skb, &key, actions->actions, ++ actions->n_actions, GFP_KERNEL); ++ kfree(actions); ++ return err; ++ ++error_free_skb: ++ kfree_skb(skb); ++error_free_actions: ++ kfree(actions); ++error: ++ return err; ++} ++ ++static int get_dp_stats(struct datapath *dp, struct odp_stats __user *statsp) ++{ ++ struct odp_stats stats; ++ int i; ++ ++ stats.n_flows = dp->n_flows; ++ stats.cur_capacity = rcu_dereference(dp->table)->n_buckets; ++ stats.max_capacity = DP_MAX_BUCKETS; ++ stats.n_ports = dp->n_ports; ++ stats.max_ports = DP_MAX_PORTS; ++ stats.max_groups = DP_MAX_GROUPS; ++ stats.n_frags = stats.n_hit = stats.n_missed = stats.n_lost = 0; ++ for_each_possible_cpu(i) { ++ const struct dp_stats_percpu *s; ++ s = percpu_ptr(dp->stats_percpu, i); ++ stats.n_frags += s->n_frags; ++ stats.n_hit += s->n_hit; ++ stats.n_missed += s->n_missed; ++ stats.n_lost += s->n_lost; ++ } ++ stats.max_miss_queue = DP_MAX_QUEUE_LEN; ++ stats.max_action_queue = DP_MAX_QUEUE_LEN; ++ return copy_to_user(statsp, &stats, sizeof stats) ? -EFAULT : 0; ++} ++ ++/* MTU of the dp pseudo-device: ETH_DATA_LEN or the minimum of the ports */ ++int dp_min_mtu(const struct datapath *dp) ++{ ++ struct net_bridge_port *p; ++ int mtu = 0; ++ ++ ASSERT_RTNL(); ++ ++ list_for_each_entry_rcu (p, &dp->port_list, node) { ++ struct net_device *dev = p->dev; ++ ++ /* Skip any internal ports, since that's what we're trying to ++ * set. */ ++ if (is_dp_dev(dev)) ++ continue; ++ ++ if (!mtu || dev->mtu < mtu) ++ mtu = dev->mtu; ++ } ++ ++ return mtu ? mtu : ETH_DATA_LEN; ++} ++ ++static int ++put_port(const struct net_bridge_port *p, struct odp_port __user *uop) ++{ ++ struct odp_port op; ++ memset(&op, 0, sizeof op); ++ strncpy(op.devname, p->dev->name, sizeof op.devname); ++ op.port = p->port_no; ++ op.flags = is_dp_dev(p->dev) ? ODP_PORT_INTERNAL : 0; ++ return copy_to_user(uop, &op, sizeof op) ? -EFAULT : 0; ++} ++ ++static int ++query_port(struct datapath *dp, struct odp_port __user *uport) ++{ ++ struct odp_port port; ++ ++ if (copy_from_user(&port, uport, sizeof port)) ++ return -EFAULT; ++ if (port.devname[0]) { ++ struct net_bridge_port *p; ++ struct net_device *dev; ++ int err; ++ ++ port.devname[IFNAMSIZ - 1] = '\0'; ++ ++ dev = dev_get_by_name(&init_net, port.devname); ++ if (!dev) ++ return -ENODEV; ++ ++ p = dev->br_port; ++ if (!p && is_dp_dev(dev)) { ++ struct dp_dev *dp_dev = dp_dev_priv(dev); ++ if (dp_dev->dp == dp) ++ p = dp->ports[dp_dev->port_no]; ++ } ++ err = p && p->dp == dp ? put_port(p, uport) : -ENOENT; ++ dev_put(dev); ++ ++ return err; ++ } else { ++ if (port.port >= DP_MAX_PORTS) ++ return -EINVAL; ++ if (!dp->ports[port.port]) ++ return -ENOENT; ++ return put_port(dp->ports[port.port], uport); ++ } ++} ++ ++static int ++list_ports(struct datapath *dp, struct odp_portvec __user *pvp) ++{ ++ struct odp_portvec pv; ++ struct net_bridge_port *p; ++ int idx; ++ ++ if (copy_from_user(&pv, pvp, sizeof pv)) ++ return -EFAULT; ++ ++ idx = 0; ++ if (pv.n_ports) { ++ list_for_each_entry_rcu (p, &dp->port_list, node) { ++ if (put_port(p, &pv.ports[idx])) ++ return -EFAULT; ++ if (idx++ >= pv.n_ports) ++ break; ++ } ++ } ++ return put_user(dp->n_ports, &pvp->n_ports); ++} ++ ++/* RCU callback for freeing a dp_port_group */ ++static void free_port_group(struct rcu_head *rcu) ++{ ++ struct dp_port_group *g = container_of(rcu, struct dp_port_group, rcu); ++ kfree(g); ++} ++ ++static int ++set_port_group(struct datapath *dp, const struct odp_port_group __user *upg) ++{ ++ struct odp_port_group pg; ++ struct dp_port_group *new_group, *old_group; ++ int error; ++ ++ error = -EFAULT; ++ if (copy_from_user(&pg, upg, sizeof pg)) ++ goto error; ++ ++ error = -EINVAL; ++ if (pg.n_ports > DP_MAX_PORTS || pg.group >= DP_MAX_GROUPS) ++ goto error; ++ ++ error = -ENOMEM; ++ new_group = kmalloc(sizeof *new_group + sizeof(u16) * pg.n_ports, ++ GFP_KERNEL); ++ if (!new_group) ++ goto error; ++ ++ new_group->n_ports = pg.n_ports; ++ error = -EFAULT; ++ if (copy_from_user(new_group->ports, pg.ports, ++ sizeof(u16) * pg.n_ports)) ++ goto error_free; ++ ++ old_group = rcu_dereference(dp->groups[pg.group]); ++ rcu_assign_pointer(dp->groups[pg.group], new_group); ++ if (old_group) ++ call_rcu(&old_group->rcu, free_port_group); ++ return 0; ++ ++error_free: ++ kfree(new_group); ++error: ++ return error; ++} ++ ++static int ++get_port_group(struct datapath *dp, struct odp_port_group *upg) ++{ ++ struct odp_port_group pg; ++ struct dp_port_group *g; ++ u16 n_copy; ++ ++ if (copy_from_user(&pg, upg, sizeof pg)) ++ return -EFAULT; ++ ++ if (pg.group >= DP_MAX_GROUPS) ++ return -EINVAL; ++ ++ g = dp->groups[pg.group]; ++ n_copy = g ? min_t(int, g->n_ports, pg.n_ports) : 0; ++ if (n_copy && copy_to_user(pg.ports, g->ports, n_copy * sizeof(u16))) ++ return -EFAULT; ++ ++ if (put_user(g ? g->n_ports : 0, &upg->n_ports)) ++ return -EFAULT; ++ ++ return 0; ++} ++ ++static long openvswitch_ioctl(struct file *f, unsigned int cmd, ++ unsigned long argp) ++{ ++ int dp_idx = iminor(f->f_dentry->d_inode); ++ struct datapath *dp; ++ int drop_frags, listeners, port_no; ++ int err; ++ ++ /* Handle commands with special locking requirements up front. */ ++ switch (cmd) { ++ case ODP_DP_CREATE: ++ err = create_dp(dp_idx, (char __user *)argp); ++ goto exit; ++ ++ case ODP_DP_DESTROY: ++ err = destroy_dp(dp_idx); ++ goto exit; ++ ++ case ODP_PORT_ADD: ++ err = add_port(dp_idx, (struct odp_port __user *)argp); ++ goto exit; ++ ++ case ODP_PORT_DEL: ++ err = get_user(port_no, (int __user *)argp); ++ if (!err) ++ err = del_port(dp_idx, port_no); ++ goto exit; ++ } ++ ++ dp = get_dp_locked(dp_idx); ++ err = -ENODEV; ++ if (!dp) ++ goto exit; ++ ++ switch (cmd) { ++ case ODP_DP_STATS: ++ err = get_dp_stats(dp, (struct odp_stats __user *)argp); ++ break; ++ ++ case ODP_GET_DROP_FRAGS: ++ err = put_user(dp->drop_frags, (int __user *)argp); ++ break; ++ ++ case ODP_SET_DROP_FRAGS: ++ err = get_user(drop_frags, (int __user *)argp); ++ if (err) ++ break; ++ err = -EINVAL; ++ if (drop_frags != 0 && drop_frags != 1) ++ break; ++ dp->drop_frags = drop_frags; ++ err = 0; ++ break; ++ ++ case ODP_GET_LISTEN_MASK: ++ err = put_user((int)f->private_data, (int __user *)argp); ++ break; ++ ++ case ODP_SET_LISTEN_MASK: ++ err = get_user(listeners, (int __user *)argp); ++ if (err) ++ break; ++ err = -EINVAL; ++ if (listeners & ~ODPL_ALL) ++ break; ++ err = 0; ++ f->private_data = (void*)listeners; ++ break; ++ ++ case ODP_PORT_QUERY: ++ err = query_port(dp, (struct odp_port __user *)argp); ++ break; ++ ++ case ODP_PORT_LIST: ++ err = list_ports(dp, (struct odp_portvec __user *)argp); ++ break; ++ ++ case ODP_PORT_GROUP_SET: ++ err = set_port_group(dp, (struct odp_port_group __user *)argp); ++ break; ++ ++ case ODP_PORT_GROUP_GET: ++ err = get_port_group(dp, (struct odp_port_group __user *)argp); ++ break; ++ ++ case ODP_FLOW_FLUSH: ++ err = flush_flows(dp); ++ break; ++ ++ case ODP_FLOW_PUT: ++ err = put_flow(dp, (struct odp_flow_put __user *)argp); ++ break; ++ ++ case ODP_FLOW_DEL: ++ err = del_flow(dp, (struct odp_flow __user *)argp); ++ break; ++ ++ case ODP_FLOW_GET: ++ err = do_flowvec_ioctl(dp, argp, query_flows); ++ break; ++ ++ case ODP_FLOW_LIST: ++ err = do_flowvec_ioctl(dp, argp, list_flows); ++ break; ++ ++ case ODP_EXECUTE: ++ err = do_execute(dp, (struct odp_execute __user *)argp); ++ break; ++ ++ default: ++ err = -ENOIOCTLCMD; ++ break; ++ } ++ mutex_unlock(&dp->mutex); ++exit: ++ return err; ++} ++ ++static int dp_has_packet_of_interest(struct datapath *dp, int listeners) ++{ ++ int i; ++ for (i = 0; i < DP_N_QUEUES; i++) { ++ if (listeners & (1 << i) && !skb_queue_empty(&dp->queues[i])) ++ return 1; ++ } ++ return 0; ++} ++ ++ssize_t openvswitch_read(struct file *f, char __user *buf, size_t nbytes, ++ loff_t *ppos) ++{ ++ /* XXX is there sufficient synchronization here? */ ++ int listeners = (int) f->private_data; ++ int dp_idx = iminor(f->f_dentry->d_inode); ++ struct datapath *dp = get_dp(dp_idx); ++ struct sk_buff *skb; ++ struct iovec __user iov; ++ size_t copy_bytes; ++ int retval; ++ ++ if (!dp) ++ return -ENODEV; ++ ++ if (nbytes == 0 || !listeners) ++ return 0; ++ ++ for (;;) { ++ int i; ++ ++ for (i = 0; i < DP_N_QUEUES; i++) { ++ if (listeners & (1 << i)) { ++ skb = skb_dequeue(&dp->queues[i]); ++ if (skb) ++ goto success; ++ } ++ } ++ ++ if (f->f_flags & O_NONBLOCK) { ++ retval = -EAGAIN; ++ goto error; ++ } ++ ++ wait_event_interruptible(dp->waitqueue, ++ dp_has_packet_of_interest(dp, ++ listeners)); ++ ++ if (signal_pending(current)) { ++ retval = -ERESTARTSYS; ++ goto error; ++ } ++ } ++success: ++ copy_bytes = min(skb->len, nbytes); ++ iov.iov_base = buf; ++ iov.iov_len = copy_bytes; ++ retval = skb_copy_datagram_iovec(skb, 0, &iov, iov.iov_len); ++ if (!retval) ++ retval = copy_bytes; ++ kfree_skb(skb); ++ ++error: ++ return retval; ++} ++ ++static unsigned int openvswitch_poll(struct file *file, poll_table *wait) ++{ ++ /* XXX is there sufficient synchronization here? */ ++ int dp_idx = iminor(file->f_dentry->d_inode); ++ struct datapath *dp = get_dp(dp_idx); ++ unsigned int mask; ++ ++ if (dp) { ++ mask = 0; ++ poll_wait(file, &dp->waitqueue, wait); ++ if (dp_has_packet_of_interest(dp, (int)file->private_data)) ++ mask |= POLLIN | POLLRDNORM; ++ } else { ++ mask = POLLIN | POLLRDNORM | POLLHUP; ++ } ++ return mask; ++} ++ ++struct file_operations openvswitch_fops = { ++ /* XXX .aio_read = openvswitch_aio_read, */ ++ .read = openvswitch_read, ++ .poll = openvswitch_poll, ++ .unlocked_ioctl = openvswitch_ioctl, ++ /* XXX .fasync = openvswitch_fasync, */ ++}; ++ ++static int major; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ++static struct llc_sap *dp_stp_sap; ++ ++static int dp_stp_rcv(struct sk_buff *skb, struct net_device *dev, ++ struct packet_type *pt, struct net_device *orig_dev) ++{ ++ /* We don't really care about STP packets, we just listen for them for ++ * mutual exclusion with the bridge module, so this just discards ++ * them. */ ++ kfree_skb(skb); ++ return 0; ++} ++ ++static int dp_avoid_bridge_init(void) ++{ ++ /* Register to receive STP packets because the bridge module also ++ * attempts to do so. Since there can only be a single listener for a ++ * given protocol, this provides mutual exclusion against the bridge ++ * module, preventing both of them from being loaded at the same ++ * time. */ ++ dp_stp_sap = llc_sap_open(LLC_SAP_BSPAN, dp_stp_rcv); ++ if (!dp_stp_sap) { ++ printk(KERN_ERR "openvswitch: can't register sap for STP (probably the bridge module is loaded)\n"); ++ return -EADDRINUSE; ++ } ++ return 0; ++} ++ ++static void dp_avoid_bridge_exit(void) ++{ ++ llc_sap_put(dp_stp_sap); ++} ++#else /* Linux 2.6.27 or later. */ ++static int dp_avoid_bridge_init(void) ++{ ++ /* Linux 2.6.27 introduces a way for multiple clients to register for ++ * STP packets, which interferes with what we try to do above. ++ * Instead, just check whether there's a bridge hook defined. This is ++ * not as safe--the bridge module is willing to load over the top of ++ * us--but it provides a little bit of protection. */ ++ if (br_handle_frame_hook) { ++ printk(KERN_ERR "openvswitch: bridge module is loaded, cannot load over it\n"); ++ return -EADDRINUSE; ++ } ++ return 0; ++} ++ ++static void dp_avoid_bridge_exit(void) ++{ ++ /* Nothing to do. */ ++} ++#endif /* Linux 2.6.27 or later */ ++ ++static int __init dp_init(void) ++{ ++ int err; ++ ++ printk("Open vSwitch %s, built "__DATE__" "__TIME__"\n", VERSION BUILDNR); ++ ++ err = dp_avoid_bridge_init(); ++ if (err) ++ return err; ++ ++ err = flow_init(); ++ if (err) ++ goto error; ++ ++ err = register_netdevice_notifier(&dp_device_notifier); ++ if (err) ++ goto error_flow_exit; ++ ++ major = register_chrdev(0, "openvswitch", &openvswitch_fops); ++ if (err < 0) ++ goto error_unreg_notifier; ++ ++ /* Hook into callback used by the bridge to intercept packets. ++ * Parasites we are. */ ++ br_handle_frame_hook = dp_frame_hook; ++ ++ return 0; ++ ++error_unreg_notifier: ++ unregister_netdevice_notifier(&dp_device_notifier); ++error_flow_exit: ++ flow_exit(); ++error: ++ return err; ++} ++ ++static void dp_cleanup(void) ++{ ++ rcu_barrier(); ++ unregister_chrdev(major, "openvswitch"); ++ unregister_netdevice_notifier(&dp_device_notifier); ++ flow_exit(); ++ br_handle_frame_hook = NULL; ++ dp_avoid_bridge_exit(); ++} ++ ++module_init(dp_init); ++module_exit(dp_cleanup); ++ ++MODULE_DESCRIPTION("Open vSwitch switching datapath"); ++MODULE_LICENSE("GPL"); +diff -r 9dfeb6b4054e net/vswitch/datapath.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/datapath.h Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,172 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++/* Interface exported by openvswitch_mod. */ ++ ++#ifndef DATAPATH_H ++#define DATAPATH_H 1 ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "flow.h" ++#include "dp_sysfs.h" ++ ++/* Mask for the priority bits in a vlan header. If we ever merge upstream ++ * then this should go into include/linux/if_vlan.h. */ ++#define VLAN_PCP_MASK 0xe000 ++ ++#define DP_MAX_PORTS 1024 ++#define DP_MAX_GROUPS 16 ++ ++#define DP_L2_BITS (PAGE_SHIFT - ilog2(sizeof(struct dp_bucket*))) ++#define DP_L2_SIZE (1 << DP_L2_BITS) ++#define DP_L2_SHIFT 0 ++ ++#define DP_L1_BITS (PAGE_SHIFT - ilog2(sizeof(struct dp_bucket**))) ++#define DP_L1_SIZE (1 << DP_L1_BITS) ++#define DP_L1_SHIFT DP_L2_BITS ++ ++/* For 4 kB pages, this is 1,048,576 on 32-bit or 262,144 on 64-bit. */ ++#define DP_MAX_BUCKETS (DP_L1_SIZE * DP_L2_SIZE) ++ ++/** ++ * struct dp_table - flow table ++ * @n_buckets: number of buckets (a power of 2 between %DP_L1_SIZE and ++ * %DP_MAX_BUCKETS) ++ * @buckets: pointer to @n_buckets/%DP_L1_SIZE pointers to %DP_L1_SIZE pointers ++ * to buckets ++ * @hash_seed: random number used for flow hashing, to make the hash ++ * distribution harder to predict ++ * @rcu: RCU callback structure ++ * ++ * The @buckets array is logically an array of pointers to buckets. It is ++ * broken into two levels to avoid the need to kmalloc() any object larger than ++ * a single page or to use vmalloc(). @buckets is always nonnull, as is each ++ * @buckets[i], but each @buckets[i][j] is nonnull only if the specified hash ++ * bucket is nonempty (for 0 <= i < @n_buckets/%DP_L1_SIZE, 0 <= j < ++ * %DP_L1_SIZE). ++ */ ++struct dp_table { ++ unsigned int n_buckets; ++ struct dp_bucket ***buckets; ++ unsigned int hash_seed; ++ struct rcu_head rcu; ++}; ++ ++/** ++ * struct dp_bucket - single bucket within datapath flow table ++ * @rcu: RCU callback structure ++ * @n_flows: number of flows in @flows[] array ++ * @flows: array of @n_flows pointers to flows ++ * ++ * The expected number of flows per bucket is 1, but this allows for an ++ * arbitrary number of collisions. ++ */ ++struct dp_bucket { ++ struct rcu_head rcu; ++ unsigned int n_flows; ++ struct sw_flow *flows[]; ++}; ++ ++#define DP_N_QUEUES 2 ++#define DP_MAX_QUEUE_LEN 100 ++ ++struct dp_stats_percpu { ++ u64 n_frags; ++ u64 n_hit; ++ u64 n_missed; ++ u64 n_lost; ++}; ++ ++struct dp_port_group { ++ struct rcu_head rcu; ++ int n_ports; ++ u16 ports[]; ++}; ++ ++struct datapath { ++ struct mutex mutex; ++ int dp_idx; ++ ++ struct kobject ifobj; ++ ++ int drop_frags; ++ ++ /* Queued data. */ ++ struct sk_buff_head queues[DP_N_QUEUES]; ++ wait_queue_head_t waitqueue; ++ ++ /* Flow table. */ ++ unsigned int n_flows; ++ struct dp_table *table; ++ ++ /* Port groups. */ ++ struct dp_port_group *groups[DP_MAX_GROUPS]; ++ ++ /* Switch ports. */ ++ unsigned int n_ports; ++ struct net_bridge_port *ports[DP_MAX_PORTS]; ++ struct list_head port_list; /* All ports, including local_port. */ ++ ++ /* Stats. */ ++ struct dp_stats_percpu *stats_percpu; ++}; ++ ++struct net_bridge_port { ++ u16 port_no; ++ struct datapath *dp; ++ struct net_device *dev; ++ struct kobject kobj; ++ char linkname[IFNAMSIZ]; ++ struct list_head node; /* Element in datapath.ports. */ ++}; ++ ++extern struct notifier_block dp_device_notifier; ++extern int (*dp_ioctl_hook)(struct net_device *dev, struct ifreq *rq, int cmd); ++ ++/* Flow table. */ ++struct dp_table *dp_table_create(unsigned int n_buckets); ++void dp_table_destroy(struct dp_table *, int free_flows); ++struct sw_flow *dp_table_lookup(struct dp_table *, const struct odp_flow_key *); ++int dp_table_insert(struct dp_table *, struct sw_flow *); ++int dp_table_delete(struct dp_table *, struct sw_flow *); ++int dp_table_expand(struct datapath *); ++int dp_table_flush(struct datapath *); ++int dp_table_foreach(struct dp_table *table, ++ int (*callback)(struct sw_flow *flow, void *aux), ++ void *aux); ++ ++void dp_process_received_packet(struct sk_buff *, struct net_bridge_port *); ++int dp_del_port(struct net_bridge_port *); ++int dp_output_control(struct datapath *, struct sk_buff *, int, u32 arg); ++int dp_min_mtu(const struct datapath *dp); ++ ++struct datapath *get_dp(int dp_idx); ++ ++static inline const char *dp_name(const struct datapath *dp) ++{ ++ return dp->ports[ODPP_LOCAL]->dev->name; ++} ++ ++#ifdef CONFIG_XEN ++int skb_checksum_setup(struct sk_buff *skb); ++#else ++static inline int skb_checksum_setup(struct sk_buff *skb) ++{ ++ return 0; ++} ++#endif ++ ++int vswitch_skb_checksum_setup(struct sk_buff *skb); ++ ++#endif /* datapath.h */ +diff -r 9dfeb6b4054e net/vswitch/dp_dev.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/dp_dev.c Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,237 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "datapath.h" ++#include "dp_dev.h" ++ ++struct pcpu_lstats { ++ unsigned long rx_packets; ++ unsigned long rx_bytes; ++ unsigned long tx_packets; ++ unsigned long tx_bytes; ++}; ++ ++struct datapath *dp_dev_get_dp(struct net_device *netdev) ++{ ++ return dp_dev_priv(netdev)->dp; ++} ++ ++static struct net_device_stats *dp_dev_get_stats(struct net_device *netdev) ++{ ++ struct dp_dev *dp_dev = dp_dev_priv(netdev); ++ struct net_device_stats *stats; ++ int i; ++ ++ stats = &dp_dev->stats; ++ memset(stats, 0, sizeof *stats); ++ for_each_possible_cpu(i) { ++ const struct pcpu_lstats *lb_stats; ++ ++ lb_stats = per_cpu_ptr(dp_dev->lstats, i); ++ stats->rx_bytes += lb_stats->rx_bytes; ++ stats->rx_packets += lb_stats->rx_packets; ++ stats->tx_bytes += lb_stats->tx_bytes; ++ stats->tx_packets += lb_stats->tx_packets; ++ } ++ return stats; ++} ++ ++int dp_dev_recv(struct net_device *netdev, struct sk_buff *skb) ++{ ++ struct dp_dev *dp_dev = dp_dev_priv(netdev); ++ struct pcpu_lstats *lb_stats; ++ int len; ++ len = skb->len; ++ skb->pkt_type = PACKET_HOST; ++ skb->protocol = eth_type_trans(skb, netdev); ++ if (in_interrupt()) ++ netif_rx(skb); ++ else ++ netif_rx_ni(skb); ++ netdev->last_rx = jiffies; ++ lb_stats = per_cpu_ptr(dp_dev->lstats, smp_processor_id()); ++ lb_stats->rx_packets++; ++ lb_stats->rx_bytes += len; ++ return len; ++} ++ ++static int dp_dev_mac_addr(struct net_device *dev, void *p) ++{ ++ struct sockaddr *addr = p; ++ ++ if (!is_valid_ether_addr(addr->sa_data)) ++ return -EADDRNOTAVAIL; ++ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); ++ return 0; ++} ++ ++/* Not reentrant (because it is called with BHs disabled), but may be called ++ * simultaneously on different CPUs. */ ++static int dp_dev_xmit(struct sk_buff *skb, struct net_device *netdev) ++{ ++ struct dp_dev *dp_dev = dp_dev_priv(netdev); ++ struct pcpu_lstats *lb_stats; ++ ++ /* dp_process_received_packet() needs its own clone. */ ++ skb = skb_share_check(skb, GFP_ATOMIC); ++ if (!skb) ++ return 0; ++ ++ lb_stats = per_cpu_ptr(dp_dev->lstats, smp_processor_id()); ++ lb_stats->tx_packets++; ++ lb_stats->tx_bytes += skb->len; ++ ++ skb_reset_mac_header(skb); ++ rcu_read_lock_bh(); ++ dp_process_received_packet(skb, dp_dev->dp->ports[dp_dev->port_no]); ++ rcu_read_unlock_bh(); ++ ++ return 0; ++} ++ ++static int dp_dev_open(struct net_device *netdev) ++{ ++ netif_start_queue(netdev); ++ return 0; ++} ++ ++static int dp_dev_stop(struct net_device *netdev) ++{ ++ netif_stop_queue(netdev); ++ return 0; ++} ++ ++static void dp_getinfo(struct net_device *netdev, struct ethtool_drvinfo *info) ++{ ++ struct dp_dev *dp_dev = dp_dev_priv(netdev); ++ strcpy(info->driver, "openvswitch"); ++ sprintf(info->bus_info, "%d.%d", dp_dev->dp->dp_idx, dp_dev->port_no); ++} ++ ++static struct ethtool_ops dp_ethtool_ops = { ++ .get_drvinfo = dp_getinfo, ++ .get_link = ethtool_op_get_link, ++ .get_sg = ethtool_op_get_sg, ++ .get_tx_csum = ethtool_op_get_tx_csum, ++ .get_tso = ethtool_op_get_tso, ++}; ++ ++static int dp_dev_change_mtu(struct net_device *dev, int new_mtu) ++{ ++ if (new_mtu < 68 || new_mtu > dp_min_mtu(dp_dev_get_dp(dev))) ++ return -EINVAL; ++ ++ dev->mtu = new_mtu; ++ return 0; ++} ++ ++static int dp_dev_init(struct net_device *netdev) ++{ ++ struct dp_dev *dp_dev = dp_dev_priv(netdev); ++ ++ dp_dev->lstats = alloc_percpu(struct pcpu_lstats); ++ if (!dp_dev->lstats) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++static void dp_dev_free(struct net_device *netdev) ++{ ++ struct dp_dev *dp_dev = dp_dev_priv(netdev); ++ ++ free_percpu(dp_dev->lstats); ++ free_netdev(netdev); ++} ++ ++static void ++do_setup(struct net_device *netdev) ++{ ++ ether_setup(netdev); ++ ++ netdev->do_ioctl = dp_ioctl_hook; ++ netdev->get_stats = dp_dev_get_stats; ++ netdev->hard_start_xmit = dp_dev_xmit; ++ netdev->open = dp_dev_open; ++ SET_ETHTOOL_OPS(netdev, &dp_ethtool_ops); ++ netdev->stop = dp_dev_stop; ++ netdev->tx_queue_len = 0; ++ netdev->set_mac_address = dp_dev_mac_addr; ++ netdev->change_mtu = dp_dev_change_mtu; ++ netdev->init = dp_dev_init; ++ netdev->destructor = dp_dev_free; ++ ++ netdev->flags = IFF_BROADCAST | IFF_MULTICAST; ++ netdev->features = NETIF_F_LLTX; /* XXX other features? */ ++ ++ random_ether_addr(netdev->dev_addr); ++ ++ /* Set the OUI to the Nicira one. */ ++ netdev->dev_addr[0] = 0x00; ++ netdev->dev_addr[1] = 0x23; ++ netdev->dev_addr[2] = 0x20; ++ ++ /* Set the top bits to indicate random Nicira address. */ ++ netdev->dev_addr[3] |= 0xc0; ++} ++ ++/* Create a datapath device associated with 'dp'. If 'dp_name' is null, ++ * the device name will be of the form 'of'. Returns the new device or ++ * an error code. ++ * ++ * Called with RTNL lock and dp_mutex. */ ++struct net_device *dp_dev_create(struct datapath *dp, const char *dp_name, int port_no) ++{ ++ struct dp_dev *dp_dev; ++ struct net_device *netdev; ++ char dev_name[IFNAMSIZ]; ++ int err; ++ ++ if (dp_name) { ++ if (strlen(dp_name) >= IFNAMSIZ) ++ return ERR_PTR(-EINVAL); ++ strncpy(dev_name, dp_name, sizeof(dev_name)); ++ } else ++ snprintf(dev_name, sizeof dev_name, "of%d", dp->dp_idx); ++ ++ netdev = alloc_netdev(sizeof(struct dp_dev), dev_name, do_setup); ++ if (!netdev) ++ return ERR_PTR(-ENOMEM); ++ ++ dp_dev = dp_dev_priv(netdev); ++ dp_dev->dp = dp; ++ dp_dev->port_no = port_no; ++ dp_dev->dev = netdev; ++ ++ err = register_netdevice(netdev); ++ if (err) { ++ free_netdev(netdev); ++ return ERR_PTR(err); ++ } ++ ++ return netdev; ++} ++ ++/* Called with RTNL lock and dp_mutex.*/ ++void dp_dev_destroy(struct net_device *netdev) ++{ ++ unregister_netdevice(netdev); ++} ++ ++int is_dp_dev(struct net_device *netdev) ++{ ++ return netdev->open == dp_dev_open; ++} +diff -r 9dfeb6b4054e net/vswitch/dp_dev.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/dp_dev.h Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,34 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++#ifndef DP_DEV_H ++#define DP_DEV_H 1 ++ ++#include ++ ++struct dp_dev { ++ struct datapath *dp; ++ int port_no; ++ ++ struct net_device *dev; ++ struct net_device_stats stats; ++ struct pcpu_lstats *lstats; ++}; ++ ++static inline struct dp_dev *dp_dev_priv(struct net_device *netdev) ++{ ++ return netdev_priv(netdev); ++} ++ ++struct net_device *dp_dev_create(struct datapath *, const char *, int port_no); ++void dp_dev_destroy(struct net_device *); ++int dp_dev_recv(struct net_device *, struct sk_buff *); ++int is_dp_dev(struct net_device *); ++struct datapath *dp_dev_get_dp(struct net_device *); ++ ++#endif /* dp_dev.h */ +diff -r 9dfeb6b4054e net/vswitch/dp_notify.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/dp_notify.c Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,54 @@ ++/* ++ * Distributed under the terms of the GNU GPL version 2. ++ * Copyright (c) 2007, 2008, 2009 Nicira Networks. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++/* Handle changes to managed devices */ ++ ++#include ++ ++#include "datapath.h" ++#include "dp_dev.h" ++ ++static int dp_device_event(struct notifier_block *unused, unsigned long event, ++ void *ptr) ++{ ++ struct net_device *dev = ptr; ++ struct net_bridge_port *p; ++ struct datapath *dp; ++ ++ if (is_dp_dev(dev)) { ++ struct dp_dev *dp_dev = dp_dev_priv(dev); ++ p = dp_dev->dp->ports[dp_dev->port_no]; ++ } else { ++ p = dev->br_port; ++ } ++ if (!p) ++ return NOTIFY_DONE; ++ dp = p->dp; ++ ++ switch (event) { ++ case NETDEV_UNREGISTER: ++ mutex_lock(&dp->mutex); ++ dp_del_port(p); ++ mutex_unlock(&dp->mutex); ++ break; ++ ++ case NETDEV_CHANGENAME: ++ if (p->port_no != ODPP_LOCAL) { ++ mutex_lock(&dp->mutex); ++ dp_sysfs_del_if(p); ++ dp_sysfs_add_if(p); ++ mutex_unlock(&dp->mutex); ++ } ++ break; ++ } ++ return NOTIFY_DONE; ++} ++ ++struct notifier_block dp_device_notifier = { ++ .notifier_call = dp_device_event ++}; +diff -r 9dfeb6b4054e net/vswitch/dp_sysfs.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/dp_sysfs.h Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,28 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++#ifndef DP_SYSFS_H ++#define DP_SYSFS_H 1 ++ ++struct datapath; ++struct net_bridge_port; ++ ++/* dp_sysfs_dp.c */ ++int dp_sysfs_add_dp(struct datapath *dp); ++int dp_sysfs_del_dp(struct datapath *dp); ++ ++/* dp_sysfs_if.c */ ++int dp_sysfs_add_if(struct net_bridge_port *p); ++int dp_sysfs_del_if(struct net_bridge_port *p); ++ ++#ifdef CONFIG_SYSFS ++extern struct sysfs_ops brport_sysfs_ops; ++#endif ++ ++#endif /* dp_sysfs.h */ ++ +diff -r 9dfeb6b4054e net/vswitch/dp_sysfs_dp.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/dp_sysfs_dp.c Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,508 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++#include ++ ++/* ++ * Sysfs attributes of bridge for Open vSwitch ++ * ++ * This has been shamelessly copied from the kernel sources. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "dp_sysfs.h" ++#include "datapath.h" ++#include "dp_dev.h" ++ ++#ifdef CONFIG_SYSFS ++#define to_dev(obj) container_of(obj, struct device, kobj) ++ ++/* Hack to attempt to build on more platforms. */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) ++#define DP_DEVICE_ATTR CLASS_DEVICE_ATTR ++#define DEVICE_PARAMS struct class_device *d ++#define DEVICE_ARGS d ++#define DEV_ATTR(NAME) class_device_attr_##NAME ++#else ++#define DP_DEVICE_ATTR DEVICE_ATTR ++#define DEVICE_PARAMS struct device *d, struct device_attribute *attr ++#define DEVICE_ARGS d, attr ++#define DEV_ATTR(NAME) dev_attr_##NAME ++#endif ++ ++/* ++ * Common code for storing bridge parameters. ++ */ ++static ssize_t store_bridge_parm(DEVICE_PARAMS, ++ const char *buf, size_t len, ++ void (*set)(struct datapath *, unsigned long)) ++{ ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++ char *endp; ++ unsigned long val; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++ val = simple_strtoul(buf, &endp, 0); ++ if (endp == buf) ++ return -EINVAL; ++ ++#if 0 ++ spin_lock_bh(&br->lock); ++ (*set)(br, val); ++ spin_unlock_bh(&br->lock); ++#else ++ /* xxx We use a default value of 0 for all fields. If the caller is ++ * xxx attempting to set the value to our default, just silently ++ * xxx ignore the request. ++ */ ++ if (val != 0) { ++ printk("%s: xxx writing dp parms not supported yet!\n", ++ dp_name(dp)); ++ } ++#endif ++ return len; ++} ++ ++ ++static ssize_t show_forward_delay(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++ return sprintf(buf, "%lu\n", jiffies_to_clock_t(br->forward_delay)); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++ ++static void set_forward_delay(struct datapath *dp, unsigned long val) ++{ ++#if 0 ++ unsigned long delay = clock_t_to_jiffies(val); ++ br->forward_delay = delay; ++ if (br_is_root_bridge(br)) ++ br->bridge_forward_delay = delay; ++#else ++ printk("%s: xxx attempt to set_forward_delay()\n", dp_name(dp)); ++#endif ++} ++ ++static ssize_t store_forward_delay(DEVICE_PARAMS, ++ const char *buf, size_t len) ++{ ++ return store_bridge_parm(DEVICE_ARGS, buf, len, set_forward_delay); ++} ++static DP_DEVICE_ATTR(forward_delay, S_IRUGO | S_IWUSR, ++ show_forward_delay, store_forward_delay); ++ ++static ssize_t show_hello_time(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%lu\n", ++ jiffies_to_clock_t(to_bridge(d)->hello_time)); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++ ++static void set_hello_time(struct datapath *dp, unsigned long val) ++{ ++#if 0 ++ unsigned long t = clock_t_to_jiffies(val); ++ br->hello_time = t; ++ if (br_is_root_bridge(br)) ++ br->bridge_hello_time = t; ++#else ++ printk("%s: xxx attempt to set_hello_time()\n", dp_name(dp)); ++#endif ++} ++ ++static ssize_t store_hello_time(DEVICE_PARAMS, ++ const char *buf, ++ size_t len) ++{ ++ return store_bridge_parm(DEVICE_ARGS, buf, len, set_hello_time); ++} ++static DP_DEVICE_ATTR(hello_time, S_IRUGO | S_IWUSR, show_hello_time, ++ store_hello_time); ++ ++static ssize_t show_max_age(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%lu\n", ++ jiffies_to_clock_t(to_bridge(d)->max_age)); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++ ++static void set_max_age(struct datapath *dp, unsigned long val) ++{ ++#if 0 ++ unsigned long t = clock_t_to_jiffies(val); ++ br->max_age = t; ++ if (br_is_root_bridge(br)) ++ br->bridge_max_age = t; ++#else ++ printk("%s: xxx attempt to set_max_age()\n", dp_name(dp)); ++#endif ++} ++ ++static ssize_t store_max_age(DEVICE_PARAMS, ++ const char *buf, size_t len) ++{ ++ return store_bridge_parm(DEVICE_ARGS, buf, len, set_max_age); ++} ++static DP_DEVICE_ATTR(max_age, S_IRUGO | S_IWUSR, show_max_age, store_max_age); ++ ++static ssize_t show_ageing_time(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++ return sprintf(buf, "%lu\n", jiffies_to_clock_t(br->ageing_time)); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++ ++static void set_ageing_time(struct datapath *dp, unsigned long val) ++{ ++#if 0 ++ br->ageing_time = clock_t_to_jiffies(val); ++#else ++ printk("%s: xxx attempt to set_ageing_time()\n", dp_name(dp)); ++#endif ++} ++ ++static ssize_t store_ageing_time(DEVICE_PARAMS, ++ const char *buf, size_t len) ++{ ++ return store_bridge_parm(DEVICE_ARGS, buf, len, set_ageing_time); ++} ++static DP_DEVICE_ATTR(ageing_time, S_IRUGO | S_IWUSR, show_ageing_time, ++ store_ageing_time); ++ ++static ssize_t show_stp_state(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++ return sprintf(buf, "%d\n", br->stp_enabled); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++ ++ ++static ssize_t store_stp_state(DEVICE_PARAMS, ++ const char *buf, ++ size_t len) ++{ ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++#if 0 ++ char *endp; ++ unsigned long val; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++ val = simple_strtoul(buf, &endp, 0); ++ if (endp == buf) ++ return -EINVAL; ++ ++ rtnl_lock(); ++ br_stp_set_enabled(br, val); ++ rtnl_unlock(); ++#else ++ printk("%s: xxx attempt to set_stp_state()\n", dp_name(dp)); ++#endif ++ ++ return len; ++} ++static DP_DEVICE_ATTR(stp_state, S_IRUGO | S_IWUSR, show_stp_state, ++ store_stp_state); ++ ++static ssize_t show_priority(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++ return sprintf(buf, "%d\n", ++ (br->bridge_id.prio[0] << 8) | br->bridge_id.prio[1]); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++ ++static void set_priority(struct datapath *dp, unsigned long val) ++{ ++#if 0 ++ br_stp_set_bridge_priority(br, (u16) val); ++#else ++ printk("%s: xxx attempt to set_priority()\n", dp_name(dp)); ++#endif ++} ++ ++static ssize_t store_priority(DEVICE_PARAMS, ++ const char *buf, size_t len) ++{ ++ return store_bridge_parm(DEVICE_ARGS, buf, len, set_priority); ++} ++static DP_DEVICE_ATTR(priority, S_IRUGO | S_IWUSR, show_priority, store_priority); ++ ++static ssize_t show_root_id(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ return br_show_bridge_id(buf, &to_bridge(d)->designated_root); ++#else ++ return sprintf(buf, "0000.010203040506\n"); ++#endif ++} ++static DP_DEVICE_ATTR(root_id, S_IRUGO, show_root_id, NULL); ++ ++static ssize_t show_bridge_id(DEVICE_PARAMS, char *buf) ++{ ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++ const unsigned char *addr = dp->ports[ODPP_LOCAL]->dev->dev_addr; ++ ++ /* xxx Do we need a lock of some sort? */ ++ return sprintf(buf, "%.2x%.2x.%.2x%.2x%.2x%.2x%.2x%.2x\n", ++ 0, 0, addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); ++} ++static DP_DEVICE_ATTR(bridge_id, S_IRUGO, show_bridge_id, NULL); ++ ++static ssize_t show_root_port(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%d\n", to_bridge(d)->root_port); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static DP_DEVICE_ATTR(root_port, S_IRUGO, show_root_port, NULL); ++ ++static ssize_t show_root_path_cost(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%d\n", to_bridge(d)->root_path_cost); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static DP_DEVICE_ATTR(root_path_cost, S_IRUGO, show_root_path_cost, NULL); ++ ++static ssize_t show_topology_change(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%d\n", to_bridge(d)->topology_change); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static DP_DEVICE_ATTR(topology_change, S_IRUGO, show_topology_change, NULL); ++ ++static ssize_t show_topology_change_detected(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++ return sprintf(buf, "%d\n", br->topology_change_detected); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static DP_DEVICE_ATTR(topology_change_detected, S_IRUGO, ++ show_topology_change_detected, NULL); ++ ++static ssize_t show_hello_timer(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++ return sprintf(buf, "%ld\n", br_timer_value(&br->hello_timer)); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static DP_DEVICE_ATTR(hello_timer, S_IRUGO, show_hello_timer, NULL); ++ ++static ssize_t show_tcn_timer(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++ return sprintf(buf, "%ld\n", br_timer_value(&br->tcn_timer)); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static DP_DEVICE_ATTR(tcn_timer, S_IRUGO, show_tcn_timer, NULL); ++ ++static ssize_t show_topology_change_timer(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++ return sprintf(buf, "%ld\n", br_timer_value(&br->topology_change_timer)); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static DP_DEVICE_ATTR(topology_change_timer, S_IRUGO, show_topology_change_timer, ++ NULL); ++ ++static ssize_t show_gc_timer(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++ return sprintf(buf, "%ld\n", br_timer_value(&br->gc_timer)); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static DP_DEVICE_ATTR(gc_timer, S_IRUGO, show_gc_timer, NULL); ++ ++static ssize_t show_group_addr(DEVICE_PARAMS, char *buf) ++{ ++#if 0 ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++ return sprintf(buf, "%x:%x:%x:%x:%x:%x\n", ++ br->group_addr[0], br->group_addr[1], ++ br->group_addr[2], br->group_addr[3], ++ br->group_addr[4], br->group_addr[5]); ++#else ++ return sprintf(buf, "00:01:02:03:04:05\n"); ++#endif ++} ++ ++static ssize_t store_group_addr(DEVICE_PARAMS, ++ const char *buf, size_t len) ++{ ++ struct datapath *dp = dp_dev_get_dp(to_net_dev(d)); ++#if 0 ++ unsigned new_addr[6]; ++ int i; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++ if (sscanf(buf, "%x:%x:%x:%x:%x:%x", ++ &new_addr[0], &new_addr[1], &new_addr[2], ++ &new_addr[3], &new_addr[4], &new_addr[5]) != 6) ++ return -EINVAL; ++ ++ /* Must be 01:80:c2:00:00:0X */ ++ for (i = 0; i < 5; i++) ++ if (new_addr[i] != br_group_address[i]) ++ return -EINVAL; ++ ++ if (new_addr[5] & ~0xf) ++ return -EINVAL; ++ ++ if (new_addr[5] == 1 /* 802.3x Pause address */ ++ || new_addr[5] == 2 /* 802.3ad Slow protocols */ ++ || new_addr[5] == 3) /* 802.1X PAE address */ ++ return -EINVAL; ++ ++ spin_lock_bh(&br->lock); ++ for (i = 0; i < 6; i++) ++ br->group_addr[i] = new_addr[i]; ++ spin_unlock_bh(&br->lock); ++#else ++ printk("%s: xxx attempt to store_group_addr()\n", dp_name(dp)); ++#endif ++ return len; ++} ++ ++static DP_DEVICE_ATTR(group_addr, S_IRUGO | S_IWUSR, ++ show_group_addr, store_group_addr); ++ ++static struct attribute *bridge_attrs[] = { ++ &DEV_ATTR(forward_delay).attr, ++ &DEV_ATTR(hello_time).attr, ++ &DEV_ATTR(max_age).attr, ++ &DEV_ATTR(ageing_time).attr, ++ &DEV_ATTR(stp_state).attr, ++ &DEV_ATTR(priority).attr, ++ &DEV_ATTR(bridge_id).attr, ++ &DEV_ATTR(root_id).attr, ++ &DEV_ATTR(root_path_cost).attr, ++ &DEV_ATTR(root_port).attr, ++ &DEV_ATTR(topology_change).attr, ++ &DEV_ATTR(topology_change_detected).attr, ++ &DEV_ATTR(hello_timer).attr, ++ &DEV_ATTR(tcn_timer).attr, ++ &DEV_ATTR(topology_change_timer).attr, ++ &DEV_ATTR(gc_timer).attr, ++ &DEV_ATTR(group_addr).attr, ++ NULL ++}; ++ ++static struct attribute_group bridge_group = { ++ .name = SYSFS_BRIDGE_ATTR, /* "bridge" */ ++ .attrs = bridge_attrs, ++}; ++ ++/* ++ * Add entries in sysfs onto the existing network class device ++ * for the bridge. ++ * Adds a attribute group "bridge" containing tuning parameters. ++ * Sub directory to hold links to interfaces. ++ * ++ * Note: the ifobj exists only to be a subdirectory ++ * to hold links. The ifobj exists in the same data structure ++ * as its parent the bridge so reference counting works. ++ */ ++int dp_sysfs_add_dp(struct datapath *dp) ++{ ++ struct kobject *kobj = &dp->ports[ODPP_LOCAL]->dev->NETDEV_DEV_MEMBER.kobj; ++ int err; ++ ++ /* Create /sys/class/net//bridge directory. */ ++ err = sysfs_create_group(kobj, &bridge_group); ++ if (err) { ++ pr_info("%s: can't create group %s/%s\n", ++ __func__, dp_name(dp), bridge_group.name); ++ goto out1; ++ } ++ ++ /* Create /sys/class/net//brif directory. */ ++ err = kobject_add(&dp->ifobj, kobj, SYSFS_BRIDGE_PORT_SUBDIR); ++ if (err) { ++ pr_info("%s: can't add kobject (directory) %s/%s\n", ++ __FUNCTION__, dp_name(dp), kobject_name(&dp->ifobj)); ++ goto out2; ++ } ++ kobject_uevent(&dp->ifobj, KOBJ_ADD); ++ return 0; ++ ++ out2: ++ sysfs_remove_group(kobj, &bridge_group); ++ out1: ++ return err; ++} ++ ++int dp_sysfs_del_dp(struct datapath *dp) ++{ ++ struct kobject *kobj = &dp->ports[ODPP_LOCAL]->dev->NETDEV_DEV_MEMBER.kobj; ++ ++ kobject_del(&dp->ifobj); ++ sysfs_remove_group(kobj, &bridge_group); ++ ++ return 0; ++} ++#else /* !CONFIG_SYSFS */ ++int dp_sysfs_add_dp(struct datapath *dp) { return 0; } ++int dp_sysfs_del_dp(struct datapath *dp) { return 0; } ++int dp_sysfs_add_if(struct net_bridge_port *p) { return 0; } ++int dp_sysfs_del_if(struct net_bridge_port *p) { return 0; } ++#endif /* !CONFIG_SYSFS */ +diff -r 9dfeb6b4054e net/vswitch/dp_sysfs_if.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/dp_sysfs_if.c Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,329 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++/* ++ * Sysfs attributes of bridge ports for Open vSwitch ++ * ++ * This has been shamelessly copied from the kernel sources. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "dp_sysfs.h" ++#include "datapath.h" ++ ++#ifdef CONFIG_SYSFS ++ ++struct brport_attribute { ++ struct attribute attr; ++ ssize_t (*show)(struct net_bridge_port *, char *); ++ ssize_t (*store)(struct net_bridge_port *, unsigned long); ++}; ++ ++#define BRPORT_ATTR(_name,_mode,_show,_store) \ ++struct brport_attribute brport_attr_##_name = { \ ++ .attr = {.name = __stringify(_name), \ ++ .mode = _mode, \ ++ .owner = THIS_MODULE, }, \ ++ .show = _show, \ ++ .store = _store, \ ++}; ++ ++static ssize_t show_path_cost(struct net_bridge_port *p, char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%d\n", p->path_cost); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static ssize_t store_path_cost(struct net_bridge_port *p, unsigned long v) ++{ ++#if 0 ++ br_stp_set_path_cost(p, v); ++#endif ++ return 0; ++} ++static BRPORT_ATTR(path_cost, S_IRUGO | S_IWUSR, ++ show_path_cost, store_path_cost); ++ ++static ssize_t show_priority(struct net_bridge_port *p, char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%d\n", p->priority); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static ssize_t store_priority(struct net_bridge_port *p, unsigned long v) ++{ ++#if 0 ++ if (v >= (1<<(16-BR_PORT_BITS))) ++ return -ERANGE; ++ br_stp_set_port_priority(p, v); ++#endif ++ return 0; ++} ++static BRPORT_ATTR(priority, S_IRUGO | S_IWUSR, ++ show_priority, store_priority); ++ ++static ssize_t show_designated_root(struct net_bridge_port *p, char *buf) ++{ ++#if 0 ++ return br_show_bridge_id(buf, &p->designated_root); ++#else ++ return sprintf(buf, "0000.010203040506\n"); ++#endif ++} ++static BRPORT_ATTR(designated_root, S_IRUGO, show_designated_root, NULL); ++ ++static ssize_t show_designated_bridge(struct net_bridge_port *p, char *buf) ++{ ++#if 0 ++ return br_show_bridge_id(buf, &p->designated_bridge); ++#else ++ return sprintf(buf, "0000.060504030201\n"); ++#endif ++} ++static BRPORT_ATTR(designated_bridge, S_IRUGO, show_designated_bridge, NULL); ++ ++static ssize_t show_designated_port(struct net_bridge_port *p, char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%d\n", p->designated_port); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static BRPORT_ATTR(designated_port, S_IRUGO, show_designated_port, NULL); ++ ++static ssize_t show_designated_cost(struct net_bridge_port *p, char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%d\n", p->designated_cost); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static BRPORT_ATTR(designated_cost, S_IRUGO, show_designated_cost, NULL); ++ ++static ssize_t show_port_id(struct net_bridge_port *p, char *buf) ++{ ++#if 0 ++ return sprintf(buf, "0x%x\n", p->port_id); ++#else ++ return sprintf(buf, "0x%x\n", 0); ++#endif ++} ++static BRPORT_ATTR(port_id, S_IRUGO, show_port_id, NULL); ++ ++static ssize_t show_port_no(struct net_bridge_port *p, char *buf) ++{ ++ return sprintf(buf, "0x%x\n", p->port_no); ++} ++ ++static BRPORT_ATTR(port_no, S_IRUGO, show_port_no, NULL); ++ ++static ssize_t show_change_ack(struct net_bridge_port *p, char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%d\n", p->topology_change_ack); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static BRPORT_ATTR(change_ack, S_IRUGO, show_change_ack, NULL); ++ ++static ssize_t show_config_pending(struct net_bridge_port *p, char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%d\n", p->config_pending); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static BRPORT_ATTR(config_pending, S_IRUGO, show_config_pending, NULL); ++ ++static ssize_t show_port_state(struct net_bridge_port *p, char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%d\n", p->state); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static BRPORT_ATTR(state, S_IRUGO, show_port_state, NULL); ++ ++static ssize_t show_message_age_timer(struct net_bridge_port *p, ++ char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%ld\n", br_timer_value(&p->message_age_timer)); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static BRPORT_ATTR(message_age_timer, S_IRUGO, show_message_age_timer, NULL); ++ ++static ssize_t show_forward_delay_timer(struct net_bridge_port *p, ++ char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%ld\n", br_timer_value(&p->forward_delay_timer)); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static BRPORT_ATTR(forward_delay_timer, S_IRUGO, show_forward_delay_timer, NULL); ++ ++static ssize_t show_hold_timer(struct net_bridge_port *p, ++ char *buf) ++{ ++#if 0 ++ return sprintf(buf, "%ld\n", br_timer_value(&p->hold_timer)); ++#else ++ return sprintf(buf, "%d\n", 0); ++#endif ++} ++static BRPORT_ATTR(hold_timer, S_IRUGO, show_hold_timer, NULL); ++ ++static struct brport_attribute *brport_attrs[] = { ++ &brport_attr_path_cost, ++ &brport_attr_priority, ++ &brport_attr_port_id, ++ &brport_attr_port_no, ++ &brport_attr_designated_root, ++ &brport_attr_designated_bridge, ++ &brport_attr_designated_port, ++ &brport_attr_designated_cost, ++ &brport_attr_state, ++ &brport_attr_change_ack, ++ &brport_attr_config_pending, ++ &brport_attr_message_age_timer, ++ &brport_attr_forward_delay_timer, ++ &brport_attr_hold_timer, ++ NULL ++}; ++ ++#define to_brport_attr(_at) container_of(_at, struct brport_attribute, attr) ++#define to_brport(obj) container_of(obj, struct net_bridge_port, kobj) ++ ++static ssize_t brport_show(struct kobject * kobj, ++ struct attribute * attr, char * buf) ++{ ++ struct brport_attribute * brport_attr = to_brport_attr(attr); ++ struct net_bridge_port * p = to_brport(kobj); ++ ++ return brport_attr->show(p, buf); ++} ++ ++static ssize_t brport_store(struct kobject * kobj, ++ struct attribute * attr, ++ const char * buf, size_t count) ++{ ++ struct net_bridge_port * p = to_brport(kobj); ++#if 0 ++ struct brport_attribute * brport_attr = to_brport_attr(attr); ++ char *endp; ++ unsigned long val; ++#endif ++ ssize_t ret = -EINVAL; ++ ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ ++#if 0 ++ val = simple_strtoul(buf, &endp, 0); ++ if (endp != buf) { ++ rtnl_lock(); ++ if (p->dev && p->br && brport_attr->store) { ++ spin_lock_bh(&p->br->lock); ++ ret = brport_attr->store(p, val); ++ spin_unlock_bh(&p->br->lock); ++ if (ret == 0) ++ ret = count; ++ } ++ rtnl_unlock(); ++ } ++#else ++ printk("%s: xxx writing port parms not supported yet!\n", ++ dp_name(p->dp)); ++#endif ++ return ret; ++} ++ ++struct sysfs_ops brport_sysfs_ops = { ++ .show = brport_show, ++ .store = brport_store, ++}; ++ ++/* ++ * Add sysfs entries to ethernet device added to a bridge. ++ * Creates a brport subdirectory with bridge attributes. ++ * Puts symlink in bridge's brport subdirectory ++ */ ++int dp_sysfs_add_if(struct net_bridge_port *p) ++{ ++ struct datapath *dp = p->dp; ++ struct brport_attribute **a; ++ int err; ++ ++ /* Create /sys/class/net//brport directory. */ ++ err = kobject_add(&p->kobj, &p->dev->NETDEV_DEV_MEMBER.kobj, ++ SYSFS_BRIDGE_PORT_ATTR); ++ if (err) ++ goto err; ++ ++ /* Create symlink from /sys/class/net//brport/bridge to ++ * /sys/class/net/. */ ++ err = sysfs_create_link(&p->kobj, ++ &dp->ports[ODPP_LOCAL]->dev->NETDEV_DEV_MEMBER.kobj, ++ SYSFS_BRIDGE_PORT_LINK); /* "bridge" */ ++ if (err) ++ goto err_del; ++ ++ /* Populate /sys/class/net//brport directory with files. */ ++ for (a = brport_attrs; *a; ++a) { ++ err = sysfs_create_file(&p->kobj, &((*a)->attr)); ++ if (err) ++ goto err_del; ++ } ++ ++ /* Create symlink from /sys/class/net//brif/ to ++ * /sys/class/net//brport. */ ++ err = sysfs_create_link(&dp->ifobj, &p->kobj, p->dev->name); ++ if (err) ++ goto err_del; ++ strcpy(p->linkname, p->dev->name); ++ ++ kobject_uevent(&p->kobj, KOBJ_ADD); ++ ++ return 0; ++ ++err_del: ++ kobject_del(&p->kobj); ++err: ++ p->linkname[0] = 0; ++ return err; ++} ++ ++int dp_sysfs_del_if(struct net_bridge_port *p) ++{ ++ if (p->linkname[0]) { ++ sysfs_remove_link(&p->dp->ifobj, p->linkname); ++ kobject_uevent(&p->kobj, KOBJ_REMOVE); ++ kobject_del(&p->kobj); ++ p->linkname[0] = '\0'; ++ } ++ return 0; ++} ++#endif /* CONFIG_SYSFS */ +diff -r 9dfeb6b4054e net/vswitch/flow.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/flow.c Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,347 @@ ++/* ++ * Distributed under the terms of the GNU GPL version 2. ++ * Copyright (c) 2007, 2008, 2009 Nicira Networks. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++#include "flow.h" ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "compat.h" ++ ++struct kmem_cache *flow_cache; ++ ++struct arp_eth_header ++{ ++ __be16 ar_hrd; /* format of hardware address */ ++ __be16 ar_pro; /* format of protocol address */ ++ unsigned char ar_hln; /* length of hardware address */ ++ unsigned char ar_pln; /* length of protocol address */ ++ __be16 ar_op; /* ARP opcode (command) */ ++ ++ /* Ethernet+IPv4 specific members. */ ++ unsigned char ar_sha[ETH_ALEN]; /* sender hardware address */ ++ unsigned char ar_sip[4]; /* sender IP address */ ++ unsigned char ar_tha[ETH_ALEN]; /* target hardware address */ ++ unsigned char ar_tip[4]; /* target IP address */ ++} __attribute__((packed)); ++ ++static inline int arphdr_ok(struct sk_buff *skb) ++{ ++ int nh_ofs = skb_network_offset(skb); ++ return pskb_may_pull(skb, nh_ofs + sizeof(struct arp_eth_header)); ++} ++ ++static inline int iphdr_ok(struct sk_buff *skb) ++{ ++ int nh_ofs = skb_network_offset(skb); ++ if (skb->len >= nh_ofs + sizeof(struct iphdr)) { ++ int ip_len = ip_hdrlen(skb); ++ return (ip_len >= sizeof(struct iphdr) ++ && pskb_may_pull(skb, nh_ofs + ip_len)); ++ } ++ return 0; ++} ++ ++static inline int tcphdr_ok(struct sk_buff *skb) ++{ ++ int th_ofs = skb_transport_offset(skb); ++ if (pskb_may_pull(skb, th_ofs + sizeof(struct tcphdr))) { ++ int tcp_len = tcp_hdrlen(skb); ++ return (tcp_len >= sizeof(struct tcphdr) ++ && skb->len >= th_ofs + tcp_len); ++ } ++ return 0; ++} ++ ++static inline int udphdr_ok(struct sk_buff *skb) ++{ ++ int th_ofs = skb_transport_offset(skb); ++ return pskb_may_pull(skb, th_ofs + sizeof(struct udphdr)); ++} ++ ++static inline int icmphdr_ok(struct sk_buff *skb) ++{ ++ int th_ofs = skb_transport_offset(skb); ++ return pskb_may_pull(skb, th_ofs + sizeof(struct icmphdr)); ++} ++ ++#define TCP_FLAGS_OFFSET 13 ++#define TCP_FLAG_MASK 0x3f ++ ++static inline struct ovs_tcphdr *ovs_tcp_hdr(const struct sk_buff *skb) ++{ ++ return (struct ovs_tcphdr *)skb_transport_header(skb); ++} ++ ++void flow_used(struct sw_flow *flow, struct sk_buff *skb) ++{ ++ unsigned long flags; ++ u8 tcp_flags = 0; ++ ++ if (flow->key.dl_type == htons(ETH_P_IP) && iphdr_ok(skb)) { ++ struct iphdr *nh = ip_hdr(skb); ++ flow->ip_tos = nh->tos; ++ if (flow->key.nw_proto == IPPROTO_TCP && tcphdr_ok(skb)) { ++ u8 *tcp = (u8 *)tcp_hdr(skb); ++ tcp_flags = *(tcp + TCP_FLAGS_OFFSET) & TCP_FLAG_MASK; ++ } ++ } ++ ++ spin_lock_irqsave(&flow->lock, flags); ++ getnstimeofday(&flow->used); ++ flow->packet_count++; ++ flow->byte_count += skb->len; ++ flow->tcp_flags |= tcp_flags; ++ spin_unlock_irqrestore(&flow->lock, flags); ++} ++ ++struct sw_flow_actions *flow_actions_alloc(size_t n_actions) ++{ ++ struct sw_flow_actions *sfa; ++ ++ if (n_actions > (PAGE_SIZE - sizeof *sfa) / sizeof(union odp_action)) ++ return ERR_PTR(-EINVAL); ++ ++ sfa = kmalloc(sizeof *sfa + n_actions * sizeof(union odp_action), ++ GFP_KERNEL); ++ if (!sfa) ++ return ERR_PTR(-ENOMEM); ++ ++ sfa->n_actions = n_actions; ++ return sfa; ++} ++ ++ ++/* Frees 'flow' immediately. */ ++void flow_free(struct sw_flow *flow) ++{ ++ if (unlikely(!flow)) ++ return; ++ kfree(flow->sf_acts); ++ kmem_cache_free(flow_cache, flow); ++} ++ ++/* RCU callback used by flow_deferred_free. */ ++static void rcu_free_flow_callback(struct rcu_head *rcu) ++{ ++ struct sw_flow *flow = container_of(rcu, struct sw_flow, rcu); ++ flow_free(flow); ++} ++ ++/* Schedules 'flow' to be freed after the next RCU grace period. ++ * The caller must hold rcu_read_lock for this to be sensible. */ ++void flow_deferred_free(struct sw_flow *flow) ++{ ++ call_rcu(&flow->rcu, rcu_free_flow_callback); ++} ++ ++/* RCU callback used by flow_deferred_free_acts. */ ++static void rcu_free_acts_callback(struct rcu_head *rcu) ++{ ++ struct sw_flow_actions *sf_acts = container_of(rcu, ++ struct sw_flow_actions, rcu); ++ kfree(sf_acts); ++} ++ ++/* Schedules 'sf_acts' to be freed after the next RCU grace period. ++ * The caller must hold rcu_read_lock for this to be sensible. */ ++void flow_deferred_free_acts(struct sw_flow_actions *sf_acts) ++{ ++ call_rcu(&sf_acts->rcu, rcu_free_acts_callback); ++} ++ ++#define SNAP_OUI_LEN 3 ++ ++struct eth_snap_hdr ++{ ++ struct ethhdr eth; ++ u8 dsap; /* Always 0xAA */ ++ u8 ssap; /* Always 0xAA */ ++ u8 ctrl; ++ u8 oui[SNAP_OUI_LEN]; ++ u16 ethertype; ++} __attribute__ ((packed)); ++ ++static int is_snap(const struct eth_snap_hdr *esh) ++{ ++ return (esh->dsap == LLC_SAP_SNAP ++ && esh->ssap == LLC_SAP_SNAP ++ && !memcmp(esh->oui, "\0\0\0", 3)); ++} ++ ++/* Parses the Ethernet frame in 'skb', which was received on 'in_port', ++ * and initializes 'key' to match. Returns 1 if 'skb' contains an IP ++ * fragment, 0 otherwise. */ ++int flow_extract(struct sk_buff *skb, u16 in_port, struct odp_flow_key *key) ++{ ++ struct ethhdr *eth; ++ struct eth_snap_hdr *esh; ++ int retval = 0; ++ int nh_ofs; ++ ++ memset(key, 0, sizeof *key); ++ key->dl_vlan = htons(ODP_VLAN_NONE); ++ key->in_port = in_port; ++ ++ if (skb->len < sizeof *eth) ++ return 0; ++ if (!pskb_may_pull(skb, skb->len >= 64 ? 64 : skb->len)) { ++ return 0; ++ } ++ ++ skb_reset_mac_header(skb); ++ eth = eth_hdr(skb); ++ esh = (struct eth_snap_hdr *) eth; ++ nh_ofs = sizeof *eth; ++ if (likely(ntohs(eth->h_proto) >= ODP_DL_TYPE_ETH2_CUTOFF)) ++ key->dl_type = eth->h_proto; ++ else if (skb->len >= sizeof *esh && is_snap(esh)) { ++ key->dl_type = esh->ethertype; ++ nh_ofs = sizeof *esh; ++ } else { ++ key->dl_type = htons(ODP_DL_TYPE_NOT_ETH_TYPE); ++ if (skb->len >= nh_ofs + sizeof(struct llc_pdu_un)) { ++ nh_ofs += sizeof(struct llc_pdu_un); ++ } ++ } ++ ++ /* Check for a VLAN tag */ ++ if (key->dl_type == htons(ETH_P_8021Q) && ++ skb->len >= nh_ofs + sizeof(struct vlan_hdr)) { ++ struct vlan_hdr *vh = (struct vlan_hdr*)(skb->data + nh_ofs); ++ key->dl_type = vh->h_vlan_encapsulated_proto; ++ key->dl_vlan = vh->h_vlan_TCI & htons(VLAN_VID_MASK); ++ nh_ofs += sizeof(struct vlan_hdr); ++ } ++ memcpy(key->dl_src, eth->h_source, ETH_ALEN); ++ memcpy(key->dl_dst, eth->h_dest, ETH_ALEN); ++ skb_set_network_header(skb, nh_ofs); ++ ++ /* Network layer. */ ++ if (key->dl_type == htons(ETH_P_IP) && iphdr_ok(skb)) { ++ struct iphdr *nh = ip_hdr(skb); ++ int th_ofs = nh_ofs + nh->ihl * 4; ++ key->nw_src = nh->saddr; ++ key->nw_dst = nh->daddr; ++ key->nw_proto = nh->protocol; ++ skb_set_transport_header(skb, th_ofs); ++ ++ /* Transport layer. */ ++ if (!(nh->frag_off & htons(IP_MF | IP_OFFSET))) { ++ if (key->nw_proto == IPPROTO_TCP) { ++ if (tcphdr_ok(skb)) { ++ struct tcphdr *tcp = tcp_hdr(skb); ++ key->tp_src = tcp->source; ++ key->tp_dst = tcp->dest; ++ } else { ++ /* Avoid tricking other code into ++ * thinking that this packet has an L4 ++ * header. */ ++ key->nw_proto = 0; ++ } ++ } else if (key->nw_proto == IPPROTO_UDP) { ++ if (udphdr_ok(skb)) { ++ struct udphdr *udp = udp_hdr(skb); ++ key->tp_src = udp->source; ++ key->tp_dst = udp->dest; ++ } else { ++ /* Avoid tricking other code into ++ * thinking that this packet has an L4 ++ * header. */ ++ key->nw_proto = 0; ++ } ++ } else if (key->nw_proto == IPPROTO_ICMP) { ++ if (icmphdr_ok(skb)) { ++ struct icmphdr *icmp = icmp_hdr(skb); ++ /* The ICMP type and code fields use the 16-bit ++ * transport port fields, so we need to store them ++ * in 16-bit network byte order. */ ++ key->tp_src = htons(icmp->type); ++ key->tp_dst = htons(icmp->code); ++ } else { ++ /* Avoid tricking other code into ++ * thinking that this packet has an L4 ++ * header. */ ++ key->nw_proto = 0; ++ } ++ } ++ } else { ++ retval = 1; ++ } ++ } else if (key->dl_type == htons(ETH_P_ARP) && arphdr_ok(skb)) { ++ struct arp_eth_header *arp; ++ ++ arp = (struct arp_eth_header *)skb_network_header(skb); ++ ++ if (arp->ar_hrd == htons(1) ++ && arp->ar_pro == htons(ETH_P_IP) ++ && arp->ar_hln == ETH_ALEN ++ && arp->ar_pln == 4) { ++ ++ /* We only match on the lower 8 bits of the opcode. */ ++ if (ntohs(arp->ar_op) <= 0xff) { ++ key->nw_proto = ntohs(arp->ar_op); ++ } ++ ++ if (key->nw_proto == ARPOP_REQUEST ++ || key->nw_proto == ARPOP_REPLY) { ++ memcpy(&key->nw_src, arp->ar_sip, sizeof(key->nw_src)); ++ memcpy(&key->nw_dst, arp->ar_tip, sizeof(key->nw_dst)); ++ } ++ } ++ } else { ++ skb_reset_transport_header(skb); ++ } ++ return retval; ++} ++ ++/* Initializes the flow module. ++ * Returns zero if successful or a negative error code. */ ++int flow_init(void) ++{ ++ flow_cache = kmem_cache_create("sw_flow", sizeof(struct sw_flow), 0, ++ 0, NULL); ++ if (flow_cache == NULL) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++/* Uninitializes the flow module. */ ++void flow_exit(void) ++{ ++ kmem_cache_destroy(flow_cache); ++} ++ ++void print_flow(const struct odp_flow_key *key) ++{ ++#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" ++#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] ++ printk("port%04x:vlan%d mac"MAC_FMT"->"MAC_FMT" " ++ "type%04x proto%d ip%x->%x port%d->%d\n", ++ key->in_port, ntohs(key->dl_vlan), ++ MAC_ARG(key->dl_src), MAC_ARG(key->dl_dst), ++ ntohs(key->dl_type), key->nw_proto, ++ key->nw_src, key->nw_dst, ++ ntohs(key->tp_src), ntohs(key->tp_dst)); ++} +diff -r 9dfeb6b4054e net/vswitch/flow.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/flow.h Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,57 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++#ifndef FLOW_H ++#define FLOW_H 1 ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "openvswitch/datapath-protocol.h" ++ ++struct sk_buff; ++ ++struct sw_flow_actions { ++ struct rcu_head rcu; ++ unsigned int n_actions; ++ union odp_action actions[]; ++}; ++ ++struct sw_flow { ++ struct rcu_head rcu; ++ struct odp_flow_key key; ++ struct sw_flow_actions *sf_acts; ++ ++ struct timespec used; /* Last used time. */ ++ ++ u8 ip_tos; /* IP TOS value. */ ++ ++ spinlock_t lock; /* Lock for values below. */ ++ u64 packet_count; /* Number of packets matched. */ ++ u64 byte_count; /* Number of bytes matched. */ ++ u8 tcp_flags; /* Union of seen TCP flags. */ ++}; ++ ++extern struct kmem_cache *flow_cache; ++ ++struct sw_flow_actions *flow_actions_alloc(size_t n_actions); ++void flow_free(struct sw_flow *); ++void flow_deferred_free(struct sw_flow *); ++void flow_deferred_free_acts(struct sw_flow_actions *); ++int flow_extract(struct sk_buff *, u16 in_port, struct odp_flow_key *); ++void flow_used(struct sw_flow *, struct sk_buff *); ++ ++void print_flow(const struct odp_flow_key *); ++ ++int flow_init(void); ++void flow_exit(void); ++ ++#endif /* flow.h */ +diff -r 9dfeb6b4054e net/vswitch/table.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/net/vswitch/table.c Fri Sep 25 08:17:55 2009 +0100 +@@ -0,0 +1,367 @@ ++/* ++ * Copyright (c) 2009 Nicira Networks. ++ * Distributed under the terms of the GNU GPL version 2. ++ * ++ * Significant portions of this file may be copied from parts of the Linux ++ * kernel, by Linus Torvalds and others. ++ */ ++ ++#include "flow.h" ++#include "datapath.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static inline int bucket_size(int n_flows) ++{ ++ return sizeof(struct dp_bucket) + sizeof(struct sw_flow*) * n_flows; ++} ++ ++static struct dp_bucket *dp_bucket_alloc(int n_flows) ++{ ++ return kmalloc(bucket_size(n_flows), GFP_KERNEL); ++} ++ ++static void free_buckets(struct dp_bucket ***l1, unsigned int n_buckets, ++ int free_flows) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < n_buckets >> DP_L1_BITS; i++) { ++ struct dp_bucket **l2 = l1[i]; ++ unsigned int j; ++ ++ for (j = 0; j < DP_L1_SIZE; j++) { ++ struct dp_bucket *bucket = l2[j]; ++ if (!bucket) ++ continue; ++ ++ if (free_flows) { ++ unsigned int k; ++ for (k = 0; k < bucket->n_flows; k++) ++ flow_free(bucket->flows[k]); ++ } ++ kfree(bucket); ++ } ++ free_page((unsigned long)l2); ++ } ++ kfree(l1); ++} ++ ++static struct dp_bucket ***alloc_buckets(unsigned int n_buckets) ++{ ++ struct dp_bucket ***l1; ++ unsigned int i; ++ ++ l1 = kmalloc((n_buckets >> DP_L1_BITS) * sizeof(struct dp_bucket**), ++ GFP_KERNEL); ++ if (!l1) ++ return NULL; ++ for (i = 0; i < n_buckets >> DP_L1_BITS; i++) { ++ l1[i] = (struct dp_bucket **)get_zeroed_page(GFP_KERNEL); ++ if (!l1[i]) { ++ free_buckets(l1, i << DP_L1_BITS, 0); ++ return NULL; ++ } ++ } ++ return l1; ++} ++ ++/** ++ * dp_table_create - create and return a new flow table ++ * @n_buckets: number of buckets in the new table ++ * ++ * Creates and returns a new flow table, or %NULL if memory cannot be ++ * allocated. @n_buckets must be a power of 2 in the range %DP_L1_SIZE to ++ * %DP_MAX_BUCKETS. ++ */ ++struct dp_table *dp_table_create(unsigned int n_buckets) ++{ ++ struct dp_table *table; ++ ++ table = kzalloc(sizeof *table, GFP_KERNEL); ++ if (!table) ++ goto err; ++ ++ table->n_buckets = n_buckets; ++ table->buckets = alloc_buckets(n_buckets); ++ if (!table->buckets) ++ goto err_free_table; ++ get_random_bytes(&table->hash_seed, sizeof table->hash_seed); ++ ++ return table; ++ ++err_free_table: ++ kfree(table); ++err: ++ return NULL; ++} ++ ++/** ++ * dp_table_destroy - destroy flow table and optionally the flows it contains ++ * @table: table to destroy (must not be %NULL) ++ * @free_flows: whether to destroy the flows ++ * ++ * If @free_flows is zero, then the buckets in @table are destroyed but not the ++ * flows within those buckets. This behavior is useful when a table is being ++ * replaced by a larger or smaller one without destroying the flows. ++ * ++ * If @free_flows is nonzero, then the flows in @table are destroyed as well as ++ * the buckets. ++ */ ++void dp_table_destroy(struct dp_table *table, int free_flows) ++{ ++ free_buckets(table->buckets, table->n_buckets, free_flows); ++ kfree(table); ++} ++ ++static struct dp_bucket **find_bucket(struct dp_table *table, u32 hash) ++{ ++ unsigned int l1 = (hash & (table->n_buckets - 1)) >> DP_L1_SHIFT; ++ unsigned int l2 = hash & ((1 << DP_L2_BITS) - 1); ++ return &table->buckets[l1][l2]; ++} ++ ++static int search_bucket(const struct dp_bucket *bucket, const struct odp_flow_key *key) ++{ ++ int i; ++ ++ for (i = 0; i < bucket->n_flows; i++) { ++ struct sw_flow *flow = rcu_dereference(bucket->flows[i]); ++ if (!memcmp(&flow->key, key, sizeof(struct odp_flow_key))) ++ return i; ++ } ++ ++ return -1; ++} ++ ++static struct sw_flow *lookup_flow(struct dp_table *table, u32 hash, ++ const struct odp_flow_key *key) ++{ ++ struct dp_bucket **bucketp = find_bucket(table, hash); ++ struct dp_bucket *bucket = rcu_dereference(*bucketp); ++ int index; ++ ++ if (!bucket) ++ return NULL; ++ ++ index = search_bucket(bucket, key); ++ if (index < 0) ++ return NULL; ++ ++ return bucket->flows[index]; ++} ++ ++static u32 flow_hash(const struct dp_table *table, ++ const struct odp_flow_key *key) ++{ ++ return jhash2((u32*)key, sizeof *key / sizeof(u32), table->hash_seed); ++} ++ ++/** ++ * dp_table_lookup - searches flow table for a matching flow ++ * @table: flow table to search ++ * @key: flow key for which to search ++ * ++ * Searches @table for a flow whose key is equal to @key. Returns the flow if ++ * successful, otherwise %NULL. ++ */ ++struct sw_flow *dp_table_lookup(struct dp_table *table, ++ const struct odp_flow_key *key) ++{ ++ return lookup_flow(table, flow_hash(table, key), key); ++} ++ ++/** ++ * dp_table_foreach - iterate through flow table ++ * @table: table to iterate ++ * @callback: function to call for each flow entry ++ * @aux: Extra data to pass to @callback ++ * ++ * Iterates through all of the flows in @table in hash order, passing each of ++ * them in turn to @callback. If @callback returns nonzero, this terminates ++ * the iteration and dp_table_foreach() returns the same value. Returns 0 if ++ * @callback never returns nonzero. ++ * ++ * This function does not try to intelligently handle the case where @callback ++ * adds or removes flows in @table. ++ */ ++int dp_table_foreach(struct dp_table *table, ++ int (*callback)(struct sw_flow *flow, void *aux), ++ void *aux) ++{ ++ unsigned int i, j, k; ++ for (i = 0; i < table->n_buckets >> DP_L1_BITS; i++) { ++ struct dp_bucket **l2 = table->buckets[i]; ++ for (j = 0; j < DP_L1_SIZE; j++) { ++ struct dp_bucket *bucket = rcu_dereference(l2[j]); ++ if (!bucket) ++ continue; ++ ++ for (k = 0; k < bucket->n_flows; k++) { ++ int error = (*callback)(bucket->flows[k], aux); ++ if (error) ++ return error; ++ } ++ } ++ } ++ return 0; ++} ++ ++static int insert_flow(struct sw_flow *flow, void *new_table_) ++{ ++ struct dp_table *new_table = new_table_; ++ return dp_table_insert(new_table, flow); ++} ++ ++static void dp_free_table_rcu(struct rcu_head *rcu) ++{ ++ struct dp_table *table = container_of(rcu, struct dp_table, rcu); ++ dp_table_destroy(table, 0); ++} ++ ++/** ++ * dp_table_expand - replace datapath's flow table by one with more buckets ++ * @dp: datapath to expand ++ * ++ * Replaces @dp's flow table by one that has twice as many buckets. All of the ++ * flows in @dp's flow table are moved to the new flow table. Returns 0 if ++ * successful, otherwise a negative error. ++ */ ++int dp_table_expand(struct datapath *dp) ++{ ++ struct dp_table *old_table = rcu_dereference(dp->table); ++ struct dp_table *new_table; ++ ++ new_table = dp_table_create(old_table->n_buckets * 2); ++ if (!new_table) ++ goto error; ++ ++ if (dp_table_foreach(old_table, insert_flow, new_table)) ++ goto error_free_new_table; ++ ++ rcu_assign_pointer(dp->table, new_table); ++ call_rcu(&old_table->rcu, dp_free_table_rcu); ++ return 0; ++ ++error_free_new_table: ++ dp_table_destroy(new_table, 0); ++error: ++ return -ENOMEM; ++} ++ ++static void dp_free_table_and_flows_rcu(struct rcu_head *rcu) ++{ ++ struct dp_table *table = container_of(rcu, struct dp_table, rcu); ++ dp_table_destroy(table, 1); ++} ++ ++/** ++ * dp_table_flush - clear datapath's flow table ++ * @dp: datapath to clear ++ * ++ * Replaces @dp's flow table by an empty flow table, destroying all the flows ++ * in the old table (after a suitable RCU grace period). ++ */ ++int dp_table_flush(struct datapath *dp) ++{ ++ struct dp_table *old_table = rcu_dereference(dp->table); ++ struct dp_table *new_table = dp_table_create(DP_L1_SIZE); ++ if (!new_table) ++ return -ENOMEM; ++ rcu_assign_pointer(dp->table, new_table); ++ call_rcu(&old_table->rcu, dp_free_table_and_flows_rcu); ++ return 0; ++} ++ ++static void dp_free_bucket_rcu(struct rcu_head *rcu) ++{ ++ struct dp_bucket *bucket = container_of(rcu, struct dp_bucket, rcu); ++ kfree(bucket); ++} ++ ++/** ++ * dp_table_insert - insert flow into table ++ * @table: table in which to insert flow ++ * @target: flow to insert ++ * ++ * The caller must ensure that no flow with key identical to @target->key ++ * already exists in @table. Returns 0 or a negative error (currently just ++ * -ENOMEM). ++ * ++ * The caller is responsible for updating &struct datapath's n_flows member. ++ */ ++int dp_table_insert(struct dp_table *table, struct sw_flow *target) ++{ ++ u32 hash = flow_hash(table, &target->key); ++ struct dp_bucket **oldp = find_bucket(table, hash); ++ struct dp_bucket *old = *rcu_dereference(oldp); ++ unsigned int n = old ? old->n_flows : 0; ++ struct dp_bucket *new = dp_bucket_alloc(n + 1); ++ ++ if (!new) ++ return -ENOMEM; ++ ++ new->n_flows = n + 1; ++ if (old) ++ memcpy(new->flows, old->flows, n * sizeof(struct sw_flow*)); ++ new->flows[n] = target; ++ ++ rcu_assign_pointer(*oldp, new); ++ if (old) ++ call_rcu(&old->rcu, dp_free_bucket_rcu); ++ ++ return 0; ++} ++ ++/** ++ * dp_table_delete - remove flow from table ++ * @table: table from which to remove flow ++ * @target: flow to remove ++ * ++ * The caller must ensure that @target itself is in @table. (It is not ++ * good enough for @table to contain a different flow with a key equal to ++ * @target's key.) ++ * ++ * Returns 0 or a negative error (currently just -ENOMEM). Yes, it *is* ++ * possible for a flow deletion to fail due to lack of memory. ++ * ++ * The caller is responsible for updating &struct datapath's n_flows member. ++ */ ++int dp_table_delete(struct dp_table *table, struct sw_flow *target) ++{ ++ u32 hash = flow_hash(table, &target->key); ++ struct dp_bucket **oldp = find_bucket(table, hash); ++ struct dp_bucket *old = *rcu_dereference(oldp); ++ unsigned int n = old->n_flows; ++ struct dp_bucket *new; ++ ++ if (n > 1) { ++ unsigned int i; ++ ++ new = dp_bucket_alloc(n - 1); ++ if (!new) ++ return -ENOMEM; ++ ++ new->n_flows = 0; ++ for (i = 0; i < n; i++) { ++ struct sw_flow *flow = old->flows[i]; ++ if (flow != target) ++ new->flows[new->n_flows++] = flow; ++ } ++ WARN_ON_ONCE(new->n_flows != n - 1); ++ } else { ++ new = NULL; ++ } ++ ++ rcu_assign_pointer(*oldp, new); ++ call_rcu(&old->rcu, dp_free_bucket_rcu); ++ ++ return 0; ++} diff --git a/master/vxge-2.0.6.18061.patch b/master/vxge-2.0.6.18061.patch new file mode 100644 index 0000000..c584def --- /dev/null +++ b/master/vxge-2.0.6.18061.patch @@ -0,0 +1,26814 @@ +diff -r 158b6e53275e drivers/net/Kconfig +--- a/drivers/net/Kconfig Wed Aug 05 11:35:14 2009 +0100 ++++ b/drivers/net/Kconfig Wed Aug 05 11:58:00 2009 +0100 +@@ -2457,6 +2457,23 @@ + More specific information on configuring the driver is in + . + ++config VXGE ++ tristate "Neterion X3100 Series 10GbE PCIe Server Adapter" ++ depends on PCI && INET ++ ---help--- ++ This driver supports Neterion Inc's X3100 Series 10 GbE PCIe ++ I/O Virtualized Server Adapter. ++ More specific information on configuring the driver is in ++ . ++ ++config VXGE_DEBUG_TRACE_ALL ++ bool "Enabling All Debug trace statments in driver" ++ default n ++ depends on VXGE ++ ---help--- ++ Say Y here if you want to enabling all the debug trace statements in ++ driver. By default only few debug trace statements are enabled. ++ + config MYRI10GE + tristate "Myricom Myri-10G Ethernet support" + depends on PCI && INET +diff -r 158b6e53275e drivers/net/Makefile +--- a/drivers/net/Makefile Wed Aug 05 11:35:14 2009 +0100 ++++ b/drivers/net/Makefile Wed Aug 05 11:58:00 2009 +0100 +@@ -217,6 +217,7 @@ + obj-$(CONFIG_AMD8111_ETH) += amd8111e.o + obj-$(CONFIG_IBMVETH) += ibmveth.o + obj-$(CONFIG_S2IO) += s2io.o ++obj-$(CONFIG_VXGE) += vxge/ + obj-$(CONFIG_MYRI10GE) += myri10ge/ + obj-$(CONFIG_SMC91X) += smc91x.o + obj-$(CONFIG_SMC911X) += smc911x.o +diff -r 158b6e53275e drivers/net/vxge/Makefile +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/vxge/Makefile Wed Aug 05 11:58:00 2009 +0100 +@@ -0,0 +1,7 @@ ++# ++# Makefile for Neterion Inc's X3100 Series 10 GbE PCIe # I/O ++# Virtualized Server Adapter linux driver ++ ++obj-$(CONFIG_VXGE) += vxge.o ++ ++vxge-objs := vxge-config.o vxge-traffic.o vxge-ethtool.o vxge-main.o +diff -r 158b6e53275e drivers/net/vxge/vxge-config.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/vxge/vxge-config.c Wed Aug 05 11:58:00 2009 +0100 +@@ -0,0 +1,5288 @@ ++/****************************************************************************** ++ * vxge-config.c: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O ++ * Virtualized Server Adapter. ++ * Copyright(c) 2002-2009 Neterion Inc. ++ ******************************************************************************/ ++#include ++#include ++#include ++#include ++#include ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ++#include ++#endif ++#include ++ ++#include "vxge-traffic.h" ++#include "vxge-config.h" ++ ++ ++/* ++ * __vxge_hw_set_bw_limit - Set the vpath tx/rx bw and priority ++ * @vp: Vpath handle. ++ * @data0: Get/Set operation ++ * @data1: Bandwidth and priority info ++ * Returns ++ * VXGE_HW_OK on success else ++ * VXGE_HW_FAIL or VXGE_HW_ERR_INVALID_HANDLE ++ */ ++enum vxge_hw_status ++__vxge_hw_set_bw_limit(struct __vxge_hw_virtualpath *vpath, u64 vp_id, ++ u32 bandwidth) ++{ ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ u64 val64 = 0; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ u32 action = VXGE_HW_BW_CONTROL; ++ u32 fw_memo = VXGE_HW_PRIV_FN_MEMO; ++ u64 data0, data1; ++ u32 min_bw = 0, max_bw = 0; ++ u64 vpath_or_func = 0, priority = 0; ++ ++ status = __vxge_hw_device_is_privilaged(vpath->hldev->host_type, ++ vpath->hldev->func_id); ++ if (status != VXGE_HW_OK) ++ return status; ++ ++ vp_reg = vpath->vp_reg; ++ ++ min_bw = max_bw = bandwidth; ++ ++ data0 = 0; /* Set */ ++ data0 |= vp_id << 32; ++ ++ data1 = vpath_or_func << 56; ++ ++ /* Tx priority and bandwidth (unused) */ ++ data1 |= priority << 40; /* priority */ ++ val64 = ( min_bw * 256 ) / 10000; ++ data1 |= val64 << 32; ++ val64 = ( max_bw * 256 ) / 10000; ++ data1 |= val64 << 24; ++ ++ /* Rx priority and bandwidth */ ++ data1 |= priority << 16; /* priority */ ++ val64 = ( min_bw * 256 ) / 10000; ++ data1 |= val64 << 8; ++ val64 = ( max_bw * 256 ) / 10000; ++ data1 |= val64; ++ ++ writeq(data0, &vp_reg->rts_access_steer_data0); ++ writeq(data1, &vp_reg->rts_access_steer_data1); ++ ++ wmb(); ++ ++ val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE; ++ ++ writeq(val64, &vp_reg->rts_access_steer_ctrl); ++ ++ wmb(); ++ ++ status = __vxge_hw_device_register_poll( ++ &vp_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ WAIT_FACTOR * ++ vpath->hldev->config.device_poll_millis); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = readq(&vp_reg->rts_access_steer_ctrl); ++ ++ if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) ++ status = VXGE_HW_OK; ++ else ++ status = VXGE_HW_FAIL; ++ ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_vpath_bandwidth_get - Get the bandwidth for a vpath. ++ * @hldev: HW device handle. ++ * @vp_id: Vpath Id. ++ * @tx_bw: Buffer to return Tx Bandwidth ++ * @rx_bw: Buffer to return Rx Bandwidth ++ * ++ * Get the bandwidth for a given vpath ++ * ++ */ ++enum vxge_hw_status vxge_hw_vpath_bandwidth_get( ++ struct __vxge_hw_device *hldev, ++ u32 vp_id, ++ u32 *tx_bw, u32 *rx_bw) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (vp_id >= VXGE_HW_MAX_VIRTUAL_PATHS) { ++ status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE; ++ goto exit; ++ } ++ ++ *tx_bw = hldev->config.vp_config[vp_id].tx_bw_limit; ++ *rx_bw = hldev->config.vp_config[vp_id].rx_bw_limit; ++ ++exit: ++ return status; ++} ++ ++ ++ ++/* __vxge_hw_udp_rth_en_dis: enable/disable UDP RTH hashing ++ * ++ * en_dis: 0 to disable UDP RTH hashing ++ * 1 to enbale UDP RTH hasing ++ */ ++enum vxge_hw_status ++__vxge_hw_udp_rth_en_dis(struct __vxge_hw_vpath_handle *vp, u64 en_dis) ++{ ++ u64 val64 = 0; ++ struct __vxge_hw_virtualpath *vpath; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ u32 action = VXGE_HW_EN_DIS_UDP_RTH; ++ u32 fw_memo = VXGE_HW_PRIV_FN_MEMO; ++ ++ if (vp == NULL) ++ return VXGE_HW_ERR_INVALID_HANDLE; ++ ++ vpath = vp->vpath; ++ vp_reg = vpath->vp_reg; ++ ++ /* only Privilaged driver can enable UDP RTH */ ++ if (en_dis) { ++ status = __vxge_hw_device_is_privilaged(vpath->hldev->host_type, ++ vpath->hldev->func_id); ++ if (status != VXGE_HW_OK) ++ return status; ++ } ++ ++ writeq(en_dis, &vp_reg->rts_access_steer_data0); ++ ++ val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE; ++ ++ writeq(val64, &vpath->vp_reg->rts_access_steer_ctrl); ++ ++ wmb(); ++ ++ status = __vxge_hw_device_register_poll( ++ &vpath->vp_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ WAIT_FACTOR * ++ vp->vpath->hldev->config.device_poll_millis); ++ ++ if (status != VXGE_HW_OK) ++ return status; ++ ++ val64 = readq(&vpath->vp_reg->rts_access_steer_ctrl); ++ ++ if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) ++ return VXGE_HW_OK; ++ else ++ return VXGE_HW_FAIL; ++} ++/* ++ * __vxge_hw_vpath_rts_table_set_vpn - Set the entries of RTS access tables ++ * to be used by the privilege driver ++ * XXX: Code to be merged after GA TODO ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_rts_table_set_vpn( ++ struct __vxge_hw_vpath_handle *vp, u32 action, u32 rts_table, ++ u32 offset, u64 data1, u64 data2, u32 vpn) ++{ ++ u64 val64; ++ struct __vxge_hw_virtualpath *vpath; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ vpath = vp->vpath; ++ vp_reg = vpath->vp_reg; ++ ++ writeq(data1, &vp_reg->rts_access_steer_data0); ++ wmb(); ++ ++ data2 |= VXGE_HW_RTS_ACCESS_STEER_DATA1_PRIV_MODE_EN | ++ VXGE_HW_RTS_ACCESS_STEER_DATA1_PRIV_MODE_VPN(vpn); ++ ++ if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) || ++ (rts_table == ++ VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) { ++ writeq(data2, &vp_reg->rts_access_steer_data1); ++ wmb(); ++ } ++ ++ val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset); ++ ++ status = __vxge_hw_pio_mem_write64(val64, ++ &vp_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ vpath->hldev->config.device_poll_millis); ++ ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = readq(&vp_reg->rts_access_steer_ctrl); ++ ++ if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) ++ status = VXGE_HW_OK; ++ else ++ status = VXGE_HW_FAIL; ++exit: ++ return status; ++} ++ ++/* ++ * __hw_vpath_rts_table_get_vpn - Get the entries from RTS access tables ++ * @vp: Vpath handle. ++ * @action: Identifies the action to take on the specified entry. The ++ * interpretation of this field depends on the DATA_STRUCT_SEL field ++ * DA, VID, ETYPE, PN, RANGE_PN: ++ * 8'd0 - ADD_ENTRY (Add an entry to the table. This command may be ++ * rejected by management/administration). ++ * 8'd1 - DELETE_ENTRY (Add an entry to the table. This command may ++ * be rejected by management/administration) ++ * 8'd2 - LIST_FIRST_ENTRY ++ * 8'd3 - LIST_NEXT_ENTRY ++ * RTH_GEN_CFG, RTH_IT, RTH_JHASH_CFG, RTH_MASK, RTH_KEY, QOS, DS: ++ * 8'd0 - READ_ENTRY ++ * 8'd1 - WRITE_ENTRY ++ * Note: This field is updated by the H/W during an operation and ++ * is used to report additional TBD status information back to the ++ * host. ++ * @rts_table: Identifies the RTS data structure (i.e. lookup table) to access. ++ * 0; DA; Destination Address 1; VID; VLAN ID 2; ETYPE; Ethertype ++ * 3; PN; Layer 4 Port Number 4; Reserved 5; RTH_GEN_CFG; Receive ++ * Traffic Hashing General Configuration 6; RTH_IT; Receive Traffic ++ * Hashing Indirection Table 7; RTH_JHASH_CFG; Receive-Traffic ++ * Hashing Jenkins Hash Configuration 8; RTH_MASK; Receive Traffic ++ * Hashing Mask 9; RTH_KEY; Receive-Traffic Hashing Key 10; QOS; ++ * VLAN Quality of Service 11; DS; IP Differentiated Services ++ * @offset: Applies to RTH_IT, RTH_MASK, RTH_KEY, QOS, DS structures only. ++ * The interpretation of this field depends on the DATA_STRUCT_SEL ++ * field: ++ * RTH_IT - {BUCKET_NUM[0:7]} (Bucket Number) ++ * RTH_MASK - {5'b0, ++ * INDEX_8BYTE} (8-byte Index) ++ * RTH_KEY - {5'b0, INDEX_8BYTE} (8-byte Index) ++ * QOS - {5'b0, PRI} (Priority) ++ * DS - {5'b0, CP} (Codepoint) ++ * @data1: Pointer to the data 1 to be read from the table ++ * @data2: Pointer to the data 2 to be read from the table ++ * @vpn: Vpath number whose MAC addresses are to be obtained ++ * ++ * Read from the RTS table ++ * XXX: Code to be merged after GA TODO ++ * ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_rts_table_get_vpn( ++ struct __vxge_hw_vpath_handle *vp, ++ u32 action, ++ u32 rts_table, ++ u32 offset, ++ u64 *data1, ++ u64 *data2, ++ u32 vpn) ++{ ++ u64 val64 = 0; ++ struct __vxge_hw_virtualpath *vpath; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ vpath = (struct __vxge_hw_virtualpath *)vp->vpath; ++ ++ val64 |= VXGE_HW_RTS_ACCESS_STEER_DATA1_PRIV_MODE_EN | ++ VXGE_HW_RTS_ACCESS_STEER_DATA1_PRIV_MODE_VPN(vpn); ++ ++ writeq(val64, &vpath->vp_reg->rts_access_steer_data1); ++ ++ val64 = 0; ++ ++ val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset); ++ ++ if ((rts_table == ++ VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) || ++ (rts_table == ++ VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) || ++ (rts_table == ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) || ++ (rts_table == ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) { ++ val64 = val64 | VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL; ++ } ++ ++ status = __vxge_hw_pio_mem_write64(val64, ++ &vpath->vp_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ vpath->hldev->config.device_poll_millis); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ /* Writing the value of 1 to bit 54 of RTS_ACCESS_STEER_DATA1_VPn ++ * and the vpath number to retrieve in bits 55:59 ++ */ ++ ++ status = __vxge_hw_device_register_poll( ++ &vpath->vp_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ WAIT_FACTOR * ++ vp->vpath->hldev->config.device_poll_millis); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = readq(&vpath->vp_reg->rts_access_steer_ctrl); ++ ++ if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { ++ ++ *data1 = readq(&vpath->vp_reg->rts_access_steer_data0); ++ ++ if ((rts_table == ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) || ++ (rts_table == ++ VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) { ++ *data2 = readq(&vpath->vp_reg->rts_access_steer_data1); ++ } ++ ++ status = VXGE_HW_OK; ++ ++ } else ++ status = VXGE_HW_FAIL; ++exit: ++ return status; ++} ++/* ++ * __vxge_hw_channel_allocate - Allocate memory for channel ++ * This function allocates required memory for the channel and various arrays ++ * in the channel ++ */ ++struct __vxge_hw_channel* ++__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph, ++ enum __vxge_hw_channel_type type, ++ u32 length, u32 per_dtr_space, void *userdata) ++{ ++ struct __vxge_hw_channel *channel; ++ struct __vxge_hw_device *hldev; ++ int size = 0; ++ u32 vp_id; ++ ++ hldev = vph->vpath->hldev; ++ vp_id = vph->vpath->vp_id; ++ ++ switch (type) { ++ case VXGE_HW_CHANNEL_TYPE_FIFO: ++ size = sizeof(struct __vxge_hw_fifo); ++ break; ++ case VXGE_HW_CHANNEL_TYPE_RING: ++ size = sizeof(struct __vxge_hw_ring); ++ break; ++ default: ++ break; ++ } ++ ++ channel = kzalloc(size, GFP_KERNEL); ++ if (channel == NULL) ++ goto exit0; ++ INIT_LIST_HEAD(&channel->item); ++ ++ channel->common_reg = hldev->common_reg; ++ channel->first_vp_id = hldev->first_vp_id; ++ channel->type = type; ++ channel->devh = hldev; ++ channel->vph = vph; ++ channel->userdata = userdata; ++ channel->per_dtr_space = per_dtr_space; ++ channel->length = length; ++ channel->vp_id = vp_id; ++ ++ channel->work_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL); ++ if (channel->work_arr == NULL) ++ goto exit1; ++ ++ channel->free_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL); ++ if (channel->free_arr == NULL) ++ goto exit1; ++ channel->free_ptr = length; ++ ++ channel->reserve_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL); ++ if (channel->reserve_arr == NULL) ++ goto exit1; ++ channel->reserve_ptr = length; ++ channel->reserve_top = 0; ++ ++ channel->orig_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL); ++ if (channel->orig_arr == NULL) ++ goto exit1; ++ ++ return channel; ++exit1: ++ __vxge_hw_channel_free(channel); ++ ++exit0: ++ return NULL; ++} ++ ++/* ++ * __vxge_hw_channel_free - Free memory allocated for channel ++ * This function deallocates memory from the channel and various arrays ++ * in the channel ++ */ ++void __vxge_hw_channel_free(struct __vxge_hw_channel *channel) ++{ ++ kfree(channel->work_arr); ++ kfree(channel->free_arr); ++ kfree(channel->reserve_arr); ++ kfree(channel->orig_arr); ++ kfree(channel); ++} ++ ++/* ++ * __vxge_hw_channel_initialize - Initialize a channel ++ * This function initializes a channel by properly setting the ++ * various references ++ */ ++enum vxge_hw_status ++__vxge_hw_channel_initialize(struct __vxge_hw_channel *channel) ++{ ++ u32 i; ++ struct __vxge_hw_virtualpath *vpath; ++ ++ vpath = channel->vph->vpath; ++ ++ if ((channel->reserve_arr != NULL) && (channel->orig_arr != NULL)) { ++ for (i = 0; i < channel->length; i++) ++ channel->orig_arr[i] = channel->reserve_arr[i]; ++ } ++ ++ switch (channel->type) { ++ case VXGE_HW_CHANNEL_TYPE_FIFO: ++ vpath->fifoh = (struct __vxge_hw_fifo *)channel; ++ channel->stats = &((struct __vxge_hw_fifo *) ++ channel)->stats->common_stats; ++ break; ++ case VXGE_HW_CHANNEL_TYPE_RING: ++ vpath->ringh = (struct __vxge_hw_ring *)channel; ++ channel->stats = &((struct __vxge_hw_ring *) ++ channel)->stats->common_stats; ++ break; ++ default: ++ break; ++ } ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * __vxge_hw_channel_reset - Resets a channel ++ * This function resets a channel by properly setting the various references ++ */ ++enum vxge_hw_status ++__vxge_hw_channel_reset(struct __vxge_hw_channel *channel) ++{ ++ u32 i; ++ ++ for (i = 0; i < channel->length; i++) { ++ if (channel->reserve_arr != NULL) ++ channel->reserve_arr[i] = channel->orig_arr[i]; ++ if (channel->free_arr != NULL) ++ channel->free_arr[i] = NULL; ++ if (channel->work_arr != NULL) ++ channel->work_arr[i] = NULL; ++ } ++ channel->free_ptr = channel->length; ++ channel->reserve_ptr = channel->length; ++ channel->reserve_top = 0; ++ channel->post_index = 0; ++ channel->compl_index = 0; ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * __vxge_hw_device_pci_e_init ++ * Initialize certain PCI/PCI-X configuration registers ++ * with recommended values. Save config space for future hw resets. ++ */ ++void ++__vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev) ++{ ++ u16 cmd = 0; ++ ++ /* Set the PErr Repconse bit and SERR in PCI command register. */ ++ pci_read_config_word(hldev->pdev, PCI_COMMAND, &cmd); ++ cmd |= 0x140; ++ pci_write_config_word(hldev->pdev, PCI_COMMAND, cmd); ++ ++ return; ++} ++ ++/* ++ * __vxge_hw_device_register_poll ++ * Will poll certain register for specified amount of time. ++ * Will poll until masked bit is not cleared. ++ */ ++enum vxge_hw_status ++__vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis) ++{ ++ u64 val64; ++ u32 i = 0; ++ enum vxge_hw_status ret = VXGE_HW_FAIL; ++ ++ udelay(10); ++ ++ do { ++ val64 = readq(reg); ++ if (!(val64 & mask)) ++ return VXGE_HW_OK; ++ udelay(100); ++ } while (++i <= 9); ++ ++ i = 0; ++ do { ++ val64 = readq(reg); ++ if (!(val64 & mask)) ++ return VXGE_HW_OK; ++ udelay(1000); ++ } while (++i <= max_millis); ++ ++ return ret; ++} ++ ++ /* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset ++ * in progress ++ * This routine checks the vpath reset in progress register is turned zero ++ */ ++enum vxge_hw_status ++__vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog) ++{ ++ enum vxge_hw_status status; ++ status = __vxge_hw_device_register_poll(vpath_rst_in_prog, ++ VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff), ++ VXGE_HW_DEF_DEVICE_POLL_MILLIS); ++ return status; ++} ++ ++/* ++ * __vxge_hw_device_toc_get ++ * This routine sets the swapper and reads the toc pointer and returns the ++ * memory mapped address of the toc ++ */ ++struct vxge_hw_toc_reg __iomem * ++__vxge_hw_device_toc_get(void __iomem *bar0) ++{ ++ u64 val64; ++ struct vxge_hw_toc_reg __iomem *toc = NULL; ++ enum vxge_hw_status status; ++ ++ struct vxge_hw_legacy_reg __iomem *legacy_reg = ++ (struct vxge_hw_legacy_reg __iomem *)bar0; ++ ++ status = __vxge_hw_legacy_swapper_set(legacy_reg); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = readq(&legacy_reg->toc_first_pointer); ++ toc = (struct vxge_hw_toc_reg __iomem *)(bar0+val64); ++exit: ++ return toc; ++} ++ ++/* ++ * __vxge_hw_device_reg_addr_get ++ * This routine sets the swapper and reads the toc pointer and initializes the ++ * register location pointers in the device object. It waits until the ric is ++ * completed initializing registers. ++ */ ++enum vxge_hw_status ++__vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev) ++{ ++ u64 val64; ++ u32 i; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ hldev->legacy_reg = (struct vxge_hw_legacy_reg __iomem *)hldev->bar0; ++ ++ hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0); ++ if (hldev->toc_reg == NULL) { ++ status = VXGE_HW_FAIL; ++ goto exit; ++ } ++ ++ val64 = readq(&hldev->toc_reg->toc_common_pointer); ++ hldev->common_reg = ++ (struct vxge_hw_common_reg __iomem *)(hldev->bar0 + val64); ++ ++ val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer); ++ hldev->mrpcim_reg = ++ (struct vxge_hw_mrpcim_reg __iomem *)(hldev->bar0 + val64); ++ ++ for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) { ++ val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]); ++ hldev->srpcim_reg[i] = ++ (struct vxge_hw_srpcim_reg __iomem *) ++ (hldev->bar0 + val64); ++ } ++ ++ for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) { ++ val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]); ++ hldev->vpmgmt_reg[i] = ++ (struct vxge_hw_vpmgmt_reg __iomem *)(hldev->bar0 + val64); ++ } ++ ++ for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) { ++ val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]); ++ hldev->vpath_reg[i] = ++ (struct vxge_hw_vpath_reg __iomem *) ++ (hldev->bar0 + val64); ++ } ++ ++ val64 = readq(&hldev->toc_reg->toc_kdfc); ++ ++ switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) { ++ case 0: ++ hldev->kdfc = (u8 __iomem *)(hldev->bar0 + ++ VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64)); ++ break; ++ default: ++ break; ++ } ++ ++ status = __vxge_hw_device_vpath_reset_in_prog_check( ++ (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog); ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_device_access_rights_get: Get Access Rights of the driver ++ * This routine returns the Access Rights of the driver ++ */ ++static u32 ++__vxge_hw_device_access_rights_get(u32 host_type, u32 func_id) ++{ ++ u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH; ++ ++ switch (host_type) { ++ case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION: ++ if (func_id == 0) { ++ access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM | ++ VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM; ++ } ++ break; ++ case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION: ++ access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM | ++ VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM; ++ break; ++ case VXGE_HW_NO_MR_SR_VH0_FUNCTION0: ++ access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM | ++ VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM; ++ break; ++ case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION: ++ case VXGE_HW_SR_VH_VIRTUAL_FUNCTION: ++ case VXGE_HW_MR_SR_VH0_INVALID_CONFIG: ++ break; ++ case VXGE_HW_SR_VH_FUNCTION0: ++ case VXGE_HW_VH_NORMAL_FUNCTION: ++ access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM; ++ break; ++ } ++ ++ return access_rights; ++} ++ ++/* ++ * __vxge_hw_device_is_privilaged ++ * This routine checks if the device function is privileged or not ++ */ ++enum vxge_hw_status ++__vxge_hw_device_is_privilaged(u32 host_type, u32 func_id) ++{ ++ if (__vxge_hw_device_access_rights_get(host_type, ++ func_id) & ++ VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) ++ return VXGE_HW_OK; ++ else ++ return VXGE_HW_ERR_PRIVILAGED_OPEARATION; ++} ++ ++/* ++ * __vxge_hw_device_host_info_get ++ * This routine returns the host type assignments ++ */ ++void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev) ++{ ++ u64 val64; ++ u32 i; ++ ++ val64 = readq(&hldev->common_reg->host_type_assignments); ++ ++ hldev->host_type = ++ (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64); ++ ++ hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments); ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ ++ if (!(hldev->vpath_assignments & vxge_mBIT(i))) ++ continue; ++ ++ hldev->func_id = ++ __vxge_hw_vpath_func_id_get(i, hldev->vpmgmt_reg[i]); ++ ++ hldev->access_rights = __vxge_hw_device_access_rights_get( ++ hldev->host_type, hldev->func_id); ++ ++ hldev->first_vp_id = i; ++ break; ++ } ++ ++ return; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ++/* ++ * __vxge_hw_verify_pci_e_info - Validate the pci-e link parameters such as ++ * link width and signalling rate. ++ */ ++static enum vxge_hw_status ++__vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev) ++{ ++ int exp_cap; ++ u16 lnk; ++ ++ /* Get the negotiated link width and speed from PCI config space */ ++ exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP); ++ pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk); ++ ++ if ((lnk & PCI_EXP_LNKSTA_CLS) != 1) ++ return VXGE_HW_ERR_INVALID_PCI_INFO; ++ ++ switch ((lnk & PCI_EXP_LNKSTA_NLW) >> 4) { ++ case PCIE_LNK_WIDTH_RESRV: ++ case PCIE_LNK_X1: ++ case PCIE_LNK_X2: ++ case PCIE_LNK_X4: ++ case PCIE_LNK_X8: ++ break; ++ default: ++ return VXGE_HW_ERR_INVALID_PCI_INFO; ++ } ++ ++ return VXGE_HW_OK; ++} ++#endif ++ ++/* ++ * __vxge_hw_device_initialize ++ * Initialize Titan-V hardware. ++ */ ++enum vxge_hw_status __vxge_hw_device_initialize(struct __vxge_hw_device *hldev) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ ++ if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type, ++ hldev->func_id)) { ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ++ /* Validate the pci-e link width and speed */ ++ status = __vxge_hw_verify_pci_e_info(hldev); ++ if (status != VXGE_HW_OK) ++ return status; ++ ++#endif ++ } ++ return status; ++} ++ ++/** ++ * vxge_hw_device_hw_info_get - Get the hw information ++ * Returns the vpath mask that has the bits set for each vpath allocated ++ * for the driver, FW version information and the first mac addresse for ++ * each vpath ++ */ ++enum vxge_hw_status __devinit ++vxge_hw_device_hw_info_get(void __iomem *bar0, ++ struct vxge_hw_device_hw_info *hw_info) ++{ ++ u32 i; ++ u64 val64; ++ struct vxge_hw_toc_reg __iomem *toc; ++ struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg; ++ struct vxge_hw_common_reg __iomem *common_reg; ++ struct vxge_hw_vpath_reg __iomem *vpath_reg; ++ struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg; ++ enum vxge_hw_status status; ++ ++ memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info)); ++ ++ toc = __vxge_hw_device_toc_get(bar0); ++ if (toc == NULL) { ++ status = VXGE_HW_ERR_CRITICAL; ++ goto exit; ++ } ++ ++ val64 = readq(&toc->toc_common_pointer); ++ common_reg = (struct vxge_hw_common_reg __iomem *)(bar0 + val64); ++ ++ status = __vxge_hw_device_vpath_reset_in_prog_check( ++ (u64 __iomem *)&common_reg->vpath_rst_in_prog); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ hw_info->vpath_mask = readq(&common_reg->vpath_assignments); ++ ++ val64 = readq(&common_reg->host_type_assignments); ++ ++ hw_info->host_type = ++ (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64); ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ ++ if (!((hw_info->vpath_mask) & vxge_mBIT(i))) ++ continue; ++ ++ val64 = readq(&toc->toc_vpmgmt_pointer[i]); ++ ++ vpmgmt_reg = (struct vxge_hw_vpmgmt_reg __iomem *) ++ (bar0 + val64); ++ ++ hw_info->func_id = __vxge_hw_vpath_func_id_get(i, vpmgmt_reg); ++ if (__vxge_hw_device_access_rights_get(hw_info->host_type, ++ hw_info->func_id) & ++ VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) { ++ ++ val64 = readq(&toc->toc_mrpcim_pointer); ++ ++ mrpcim_reg = (struct vxge_hw_mrpcim_reg __iomem *) ++ (bar0 + val64); ++ ++ writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask); ++ wmb(); ++ } ++ ++ val64 = readq(&toc->toc_vpath_pointer[i]); ++ ++ vpath_reg = (struct vxge_hw_vpath_reg __iomem *)(bar0 + val64); ++ ++ hw_info->function_mode = ++ __vxge_hw_vpath_pci_func_mode_get(i, vpath_reg); ++ ++ status = __vxge_hw_vpath_fw_ver_get(i, vpath_reg, hw_info); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ status = __vxge_hw_vpath_card_info_get(i, vpath_reg, hw_info); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ break; ++ } ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ ++ if (!((hw_info->vpath_mask) & vxge_mBIT(i))) ++ continue; ++ ++ val64 = readq(&toc->toc_vpath_pointer[i]); ++ vpath_reg = (struct vxge_hw_vpath_reg __iomem *)(bar0 + val64); ++ ++ status = __vxge_hw_vpath_addr_get(i, vpath_reg, ++ hw_info->mac_addrs[i], ++ hw_info->mac_addr_masks[i]); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ } ++exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_device_initialize - Initialize Titan device. ++ * Initialize Titan device. Note that all the arguments of this public API ++ * are 'IN', including @hldev. Driver cooperates with ++ * OS to find new Titan device, locate its PCI and memory spaces. ++ * ++ * When done, the driver allocates sizeof(struct __vxge_hw_device) bytes for HW ++ * to enable the latter to perform Titan hardware initialization. ++ */ ++enum vxge_hw_status __devinit ++vxge_hw_device_initialize( ++ struct __vxge_hw_device **devh, ++ struct vxge_hw_device_attr *attr, ++ struct vxge_hw_device_config *device_config, ++ u8 titan1) ++{ ++ u32 i; ++ u32 nblocks = 0; ++ struct __vxge_hw_device *hldev = NULL; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ status = __vxge_hw_device_config_check(device_config); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ hldev = (struct __vxge_hw_device *) ++ vmalloc(sizeof(struct __vxge_hw_device)); ++ if (hldev == NULL) { ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto exit; ++ } ++ ++ memset(hldev, 0, sizeof(struct __vxge_hw_device)); ++ hldev->magic = VXGE_HW_DEVICE_MAGIC; ++ ++ vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL); ++ ++ /* apply config */ ++ memcpy(&hldev->config, device_config, ++ sizeof(struct vxge_hw_device_config)); ++ ++ hldev->bar0 = attr->bar0; ++ hldev->pdev = attr->pdev; ++ hldev->titan1 = titan1; ++ ++ hldev->uld_callbacks.link_up = attr->uld_callbacks.link_up; ++ hldev->uld_callbacks.link_down = attr->uld_callbacks.link_down; ++ hldev->uld_callbacks.crit_err = attr->uld_callbacks.crit_err; ++ ++ __vxge_hw_device_pci_e_init(hldev); ++ ++ status = __vxge_hw_device_reg_addr_get(hldev); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ __vxge_hw_device_host_info_get(hldev); ++ ++ /* Incrementing for stats blocks */ ++ nblocks++; ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ ++ if (!(hldev->vpath_assignments & vxge_mBIT(i))) ++ continue; ++ ++ if (device_config->vp_config[i].ring.enable == ++ VXGE_HW_RING_ENABLE) ++ nblocks += device_config->vp_config[i].ring.ring_blocks; ++ ++ if (device_config->vp_config[i].fifo.enable == ++ VXGE_HW_FIFO_ENABLE) ++ nblocks += device_config->vp_config[i].fifo.fifo_blocks; ++ nblocks++; ++ } ++ ++ if (__vxge_hw_blockpool_create(hldev, ++ &hldev->block_pool, ++ nblocks) != VXGE_HW_OK) { ++ ++ vxge_hw_device_terminate(hldev); ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto exit; ++ } ++ ++ status = __vxge_hw_device_initialize(hldev); ++ ++ if (status != VXGE_HW_OK) { ++ vxge_hw_device_terminate(hldev); ++ goto exit; ++ } ++ ++ *devh = hldev; ++exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_device_terminate - Terminate Titan device. ++ * Terminate HW device. ++ */ ++void ++vxge_hw_device_terminate(struct __vxge_hw_device *hldev) ++{ ++ vxge_assert(hldev->magic == VXGE_HW_DEVICE_MAGIC); ++ ++ hldev->magic = VXGE_HW_DEVICE_DEAD; ++ ++ __vxge_hw_blockpool_destroy(&hldev->block_pool); ++ vfree(hldev); ++} ++ ++enum vxge_hw_status vxge_hw_device_hw_stats_enable( ++ struct __vxge_hw_device *hldev) ++{ ++ u32 i; ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ val64 = readq(&hldev->common_reg->stats_cfg0); ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ ++ if (!(hldev->vpaths_deployed & vxge_mBIT(i)) || ++ (hldev->virtual_paths[i].vp_open == ++ VXGE_HW_VP_NOT_OPEN)) ++ continue; ++ ++ memcpy(hldev->virtual_paths[i].hw_stats_sav, ++ hldev->virtual_paths[i].hw_stats, ++ sizeof(struct vxge_hw_vpath_stats_hw_info)); ++ ++ if (hldev->config.stats_read_method == ++ VXGE_HW_STATS_READ_METHOD_DMA) { ++ val64 |= VXGE_HW_STATS_CFG0_STATS_ENABLE( ++ (1 << (16 - i))); ++ } else { ++ status = __vxge_hw_vpath_stats_get( ++ &hldev->virtual_paths[i], ++ hldev->virtual_paths[i].hw_stats); ++ } ++ ++ } ++ ++ __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), ++ &hldev->common_reg->stats_cfg0); ++ ++ return status; ++} ++ ++/* ++ * vxge_hw_device_stats_get - Get the device hw statistics. ++ * Returns the vpath h/w stats for the device. ++ */ ++enum vxge_hw_status ++vxge_hw_device_stats_get(struct __vxge_hw_device *hldev, ++ struct vxge_hw_device_stats_hw_info *hw_stats) ++{ ++ u32 i; ++ u64 val64 = 0; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (hldev->config.stats_read_method == VXGE_HW_STATS_READ_METHOD_DMA) { ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ ++ if (!(hldev->vpaths_deployed & vxge_mBIT(i))) ++ continue; ++ ++ val64 |= VXGE_HW_STATS_CFG0_STATS_ENABLE( ++ (1 << (16 - i))); ++ ++ } ++ ++ status = __vxge_hw_device_register_poll( ++ &hldev->common_reg->stats_cfg0, ++ val64, ++ hldev->config.device_poll_millis); ++ ++ } ++ ++ if (status == VXGE_HW_OK) ++ memcpy(hw_stats, &hldev->stats.hw_dev_info_stats, ++ sizeof(struct vxge_hw_device_stats_hw_info)); ++ ++ return status; ++} ++ ++/* ++ * vxge_hw_driver_stats_get - Get the device sw statistics. ++ * Returns the vpath s/w stats for the device. ++ */ ++enum vxge_hw_status vxge_hw_driver_stats_get( ++ struct __vxge_hw_device *hldev, ++ struct vxge_hw_device_stats_sw_info *sw_stats) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ memcpy(sw_stats, &hldev->stats.sw_dev_info_stats, ++ sizeof(struct vxge_hw_device_stats_sw_info)); ++ ++ return status; ++} ++ ++/* ++ * vxge_hw_mrpcim_stats_access - Access the statistics from the given location ++ * and offset and perform an operation ++ * Get the statistics from the given location and offset. ++ */ ++enum vxge_hw_status ++vxge_hw_mrpcim_stats_access(struct __vxge_hw_device *hldev, ++ u32 operation, u32 location, u32 offset, u64 *stat) ++{ ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ status = __vxge_hw_device_is_privilaged(hldev->host_type, ++ hldev->func_id); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = VXGE_HW_XMAC_STATS_SYS_CMD_OP(operation) | ++ VXGE_HW_XMAC_STATS_SYS_CMD_STROBE | ++ VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(location) | ++ VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset); ++ ++ status = __vxge_hw_pio_mem_write64(val64, ++ &hldev->mrpcim_reg->xmac_stats_sys_cmd, ++ VXGE_HW_XMAC_STATS_SYS_CMD_STROBE, ++ hldev->config.device_poll_millis); ++ ++ if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ)) ++ *stat = readq(&hldev->mrpcim_reg->xmac_stats_sys_data); ++ else ++ *stat = 0; ++exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_device_xmac_aggr_stats_get - Get the Statistics on aggregate port ++ * Get the Statistics on aggregate port ++ */ ++enum vxge_hw_status ++vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *hldev, u32 port, ++ struct vxge_hw_xmac_aggr_stats *aggr_stats) ++{ ++ u64 *val64; ++ int i; ++ u32 offset = VXGE_HW_STATS_AGGRn_OFFSET; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ val64 = (u64 *)aggr_stats; ++ ++ status = __vxge_hw_device_is_privilaged(hldev->host_type, ++ hldev->func_id); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ for (i = 0; i < sizeof(struct vxge_hw_xmac_aggr_stats) / 8; i++) { ++ status = vxge_hw_mrpcim_stats_access(hldev, ++ VXGE_HW_STATS_OP_READ, ++ VXGE_HW_STATS_LOC_AGGR, ++ ((offset + (104 * port)) >> 3), val64); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ offset += 8; ++ val64++; ++ } ++exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_device_xmac_port_stats_get - Get the Statistics on a port ++ * Get the Statistics on port ++ */ ++enum vxge_hw_status ++vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *hldev, u32 port, ++ struct vxge_hw_xmac_port_stats *port_stats) ++{ ++ u64 *val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ int i; ++ u32 offset = 0x0; ++ val64 = (u64 *) port_stats; ++ ++ status = __vxge_hw_device_is_privilaged(hldev->host_type, ++ hldev->func_id); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ for (i = 0; i < sizeof(struct vxge_hw_xmac_port_stats) / 8; i++) { ++ status = vxge_hw_mrpcim_stats_access(hldev, ++ VXGE_HW_STATS_OP_READ, ++ VXGE_HW_STATS_LOC_AGGR, ++ ((offset + (608 * port)) >> 3), val64); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ offset += 8; ++ val64++; ++ } ++ ++exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_device_xmac_stats_get - Get the XMAC Statistics ++ * Get the XMAC Statistics ++ */ ++enum vxge_hw_status ++vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev, ++ struct vxge_hw_xmac_stats *xmac_stats) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ u32 i; ++ ++ status = vxge_hw_device_xmac_aggr_stats_get(hldev, ++ 0, &xmac_stats->aggr_stats[0]); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ status = vxge_hw_device_xmac_aggr_stats_get(hldev, ++ 1, &xmac_stats->aggr_stats[1]); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) { ++ ++ status = vxge_hw_device_xmac_port_stats_get(hldev, ++ i, &xmac_stats->port_stats[i]); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ } ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ ++ if (!(hldev->vpaths_deployed & vxge_mBIT(i))) ++ continue; ++ ++ status = __vxge_hw_vpath_xmac_tx_stats_get( ++ &hldev->virtual_paths[i], ++ &xmac_stats->vpath_tx_stats[i]); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ status = __vxge_hw_vpath_xmac_rx_stats_get( ++ &hldev->virtual_paths[i], ++ &xmac_stats->vpath_rx_stats[i]); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ } ++exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_device_debug_set - Set the debug module, level and timestamp ++ * This routine is used to dynamically change the debug output ++ */ ++void vxge_hw_device_debug_set(struct __vxge_hw_device *hldev, ++ enum vxge_debug_level level, u32 mask) ++{ ++ if (hldev == NULL) ++ return; ++ ++#if defined(VXGE_DEBUG_TRACE_MASK) || \ ++ defined(VXGE_DEBUG_ERR_MASK) ++ hldev->debug_module_mask = mask; ++ hldev->debug_level = level; ++#endif ++ ++#if defined(VXGE_DEBUG_ERR_MASK) ++ hldev->level_err = level & VXGE_ERR; ++#endif ++ ++#if defined(VXGE_DEBUG_TRACE_MASK) ++ hldev->level_trace = level & VXGE_TRACE; ++#endif ++} ++ ++/* ++ * vxge_hw_device_error_level_get - Get the error level ++ * This routine returns the current error level set ++ */ ++u32 vxge_hw_device_error_level_get(struct __vxge_hw_device *hldev) ++{ ++#if defined(VXGE_DEBUG_ERR_MASK) ++ if (hldev == NULL) ++ return VXGE_ERR; ++ else ++ return hldev->level_err; ++#else ++ return 0; ++#endif ++} ++ ++/* ++ * vxge_hw_device_trace_level_get - Get the trace level ++ * This routine returns the current trace level set ++ */ ++u32 vxge_hw_device_trace_level_get(struct __vxge_hw_device *hldev) ++{ ++#if defined(VXGE_DEBUG_TRACE_MASK) ++ if (hldev == NULL) ++ return VXGE_TRACE; ++ else ++ return hldev->level_trace; ++#else ++ return 0; ++#endif ++} ++/* ++ * vxge_hw_device_debug_mask_get - Get the debug mask ++ * This routine returns the current debug mask set ++ */ ++u32 vxge_hw_device_debug_mask_get(struct __vxge_hw_device *hldev) ++{ ++#if defined(VXGE_DEBUG_TRACE_MASK) || defined(VXGE_DEBUG_ERR_MASK) ++ if (hldev == NULL) ++ return 0; ++ return hldev->debug_module_mask; ++#else ++ return 0; ++#endif ++} ++ ++/* ++ * vxge_hw_getpause_data -Pause frame frame generation and reception. ++ * Returns the Pause frame generation and reception capability of the NIC. ++ */ ++enum vxge_hw_status vxge_hw_device_getpause_data(struct __vxge_hw_device *hldev, ++ u32 port, u32 *tx, u32 *rx) ++{ ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) { ++ status = VXGE_HW_ERR_INVALID_DEVICE; ++ goto exit; ++ } ++ ++ if (port >= VXGE_HW_MAC_MAX_MAC_PORT_ID) { ++ status = VXGE_HW_ERR_INVALID_PORT; ++ goto exit; ++ } ++ ++ if (!(hldev->access_rights & VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) { ++ status = VXGE_HW_ERR_PRIVILAGED_OPEARATION; ++ goto exit; ++ } ++ ++ val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]); ++ if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN) ++ *tx = 1; ++ if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN) ++ *rx = 1; ++exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_device_setpause_data - set/reset pause frame generation. ++ * It can be used to set or reset Pause frame generation or reception ++ * support of the NIC. ++ */ ++ ++enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev, ++ u32 port, u32 tx, u32 rx) ++{ ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) { ++ status = VXGE_HW_ERR_INVALID_DEVICE; ++ goto exit; ++ } ++ ++ if (port >= VXGE_HW_MAC_MAX_MAC_PORT_ID) { ++ status = VXGE_HW_ERR_INVALID_PORT; ++ goto exit; ++ } ++ ++ status = __vxge_hw_device_is_privilaged(hldev->host_type, ++ hldev->func_id); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]); ++ if (tx) ++ val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN; ++ else ++ val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN; ++ if (rx) ++ val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN; ++ else ++ val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN; ++ ++ writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]); ++exit: ++ return status; ++} ++ ++u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev) ++{ ++ int link_width, exp_cap; ++ u16 lnk; ++ ++ exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP); ++ pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk); ++ link_width = (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4; ++ return link_width; ++} ++ ++/* ++ * __vxge_hw_ring_block_memblock_idx - Return the memblock index ++ * This function returns the index of memory block ++ */ ++static inline u32 ++__vxge_hw_ring_block_memblock_idx(u8 *block) ++{ ++ return (u32)*((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)); ++} ++ ++/* ++ * __vxge_hw_ring_block_memblock_idx_set - Sets the memblock index ++ * This function sets index to a memory block ++ */ ++static inline void ++__vxge_hw_ring_block_memblock_idx_set(u8 *block, u32 memblock_idx) ++{ ++ *((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)) = memblock_idx; ++} ++ ++/* ++ * __vxge_hw_ring_block_next_pointer_set - Sets the next block pointer ++ * in RxD block ++ * Sets the next block pointer in RxD block ++ */ ++static inline void ++__vxge_hw_ring_block_next_pointer_set(u8 *block, dma_addr_t dma_next) ++{ ++ *((u64 *)(block + VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next; ++} ++ ++/* ++ * __vxge_hw_ring_first_block_address_get - Returns the dma address of the ++ * first block ++ * Returns the dma address of the first RxD block ++ */ ++u64 __vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring *ring) ++{ ++ struct vxge_hw_mempool_dma *dma_object; ++ ++ dma_object = ring->mempool->memblocks_dma_arr; ++ vxge_assert(dma_object != NULL); ++ ++ return dma_object->addr; ++} ++ ++/* ++ * __vxge_hw_ring_item_dma_addr - Return the dma address of an item ++ * This function returns the dma address of a given item ++ */ ++static dma_addr_t __vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool *mempoolh, ++ void *item) ++{ ++ u32 memblock_idx; ++ void *memblock; ++ struct vxge_hw_mempool_dma *memblock_dma_object; ++ ptrdiff_t dma_item_offset; ++ ++ /* get owner memblock index */ ++ memblock_idx = __vxge_hw_ring_block_memblock_idx(item); ++ ++ /* get owner memblock by memblock index */ ++ memblock = mempoolh->memblocks_arr[memblock_idx]; ++ ++ /* get memblock DMA object by memblock index */ ++ memblock_dma_object = mempoolh->memblocks_dma_arr + memblock_idx; ++ ++ /* calculate offset in the memblock of this item */ ++ dma_item_offset = (u8 *)item - (u8 *)memblock; ++ ++ return memblock_dma_object->addr + dma_item_offset; ++} ++ ++/* ++ * __vxge_hw_ring_rxdblock_link - Link the RxD blocks ++ * This function returns the dma address of a given item ++ */ ++static void __vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool *mempoolh, ++ struct __vxge_hw_ring *ring, u32 from, ++ u32 to) ++{ ++ u8 *to_item , *from_item; ++ dma_addr_t to_dma; ++ ++ /* get "from" RxD block */ ++ from_item = mempoolh->items_arr[from]; ++ vxge_assert(from_item); ++ ++ /* get "to" RxD block */ ++ to_item = mempoolh->items_arr[to]; ++ vxge_assert(to_item); ++ ++ /* return address of the beginning of previous RxD block */ ++ to_dma = __vxge_hw_ring_item_dma_addr(mempoolh, to_item); ++ ++ /* set next pointer for this RxD block to point on ++ * previous item's DMA start address */ ++ __vxge_hw_ring_block_next_pointer_set(from_item, to_dma); ++} ++ ++/* ++ * __vxge_hw_ring_mempool_item_alloc - Allocate List blocks for RxD ++ * block callback ++ * This function is callback passed to __vxge_hw_mempool_create to create memory ++ * pool for RxD block ++ */ ++static void ++__vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool *mempoolh, ++ u32 memblock_index, ++ struct vxge_hw_mempool_dma *dma_object, ++ u32 index, u32 is_last) ++{ ++ u32 i; ++ void *item = mempoolh->items_arr[index]; ++ struct __vxge_hw_ring *ring = ++ (struct __vxge_hw_ring *)mempoolh->userdata; ++ ++ /* format rxds array */ ++ for (i = 0; i < ring->rxds_per_block; i++) { ++ void *rxdblock_priv; ++ void *uld_priv; ++ struct vxge_hw_ring_rxd_1 *rxdp; ++ ++ u32 reserve_index = ring->channel.reserve_ptr - ++ (index * ring->rxds_per_block + i + 1); ++ u32 memblock_item_idx; ++ ++ ring->channel.reserve_arr[reserve_index] = ((u8 *)item) + ++ i * ring->rxd_size; ++ ++ /* Note: memblock_item_idx is index of the item within ++ * the memblock. For instance, in case of three RxD-blocks ++ * per memblock this value can be 0, 1 or 2. */ ++ rxdblock_priv = __vxge_hw_mempool_item_priv(mempoolh, ++ memblock_index, item, ++ &memblock_item_idx); ++ ++ rxdp = (struct vxge_hw_ring_rxd_1 *) ++ ring->channel.reserve_arr[reserve_index]; ++ ++ uld_priv = ((u8 *)rxdblock_priv + ring->rxd_priv_size * i); ++ ++ /* pre-format Host_Control */ ++ rxdp->host_control = (u64)(size_t)uld_priv; ++ } ++ ++ __vxge_hw_ring_block_memblock_idx_set(item, memblock_index); ++ ++ if (is_last) { ++ /* link last one with first one */ ++ __vxge_hw_ring_rxdblock_link(mempoolh, ring, index, 0); ++ } ++ ++ if (index > 0) { ++ /* link this RxD block with previous one */ ++ __vxge_hw_ring_rxdblock_link(mempoolh, ring, index - 1, index); ++ } ++ ++ return; ++} ++ ++/* ++ * __vxge_hw_ring_initial_replenish - Initial replenish of RxDs ++ * This function replenishes the RxDs from reserve array to work array ++ */ ++enum vxge_hw_status ++vxge_hw_ring_replenish(struct __vxge_hw_ring *ring, u16 min_flag) ++{ ++ void *rxd; ++ int i = 0; ++ struct __vxge_hw_channel *channel; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ channel = &ring->channel; ++ ++ while (vxge_hw_channel_dtr_count(channel) > 0) { ++ ++ status = vxge_hw_ring_rxd_reserve(ring, &rxd); ++ ++ vxge_assert(status == VXGE_HW_OK); ++ ++ if (ring->rxd_init) { ++ status = ring->rxd_init(rxd, channel->userdata); ++ if (status != VXGE_HW_OK) { ++ vxge_hw_ring_rxd_free(ring, rxd); ++ goto exit; ++ } ++ } ++ ++ vxge_hw_ring_rxd_post(ring, rxd); ++ if (min_flag) { ++ i++; ++ if (i == VXGE_HW_RING_MIN_BUFF_ALLOCATION) ++ break; ++ } ++ } ++ status = VXGE_HW_OK; ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_ring_create - Create a Ring ++ * This function creates Ring and initializes it. ++ * ++ */ ++enum vxge_hw_status ++__vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp, ++ struct vxge_hw_ring_attr *attr) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct __vxge_hw_ring *ring; ++ u32 ring_length; ++ struct vxge_hw_ring_config *config; ++ struct __vxge_hw_device *hldev; ++ u32 vp_id; ++ struct vxge_hw_mempool_cbs ring_mp_callback; ++ ++ if ((vp == NULL) || (attr == NULL)) { ++ status = VXGE_HW_FAIL; ++ goto exit; ++ } ++ ++ hldev = vp->vpath->hldev; ++ vp_id = vp->vpath->vp_id; ++ ++ config = &hldev->config.vp_config[vp_id].ring; ++ ++ ring_length = config->ring_blocks * ++ vxge_hw_ring_rxds_per_block_get(config->buffer_mode); ++ ++ ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp, ++ VXGE_HW_CHANNEL_TYPE_RING, ++ ring_length, ++ attr->per_rxd_space, ++ attr->userdata); ++ ++ if (ring == NULL) { ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto exit; ++ } ++ ++ vp->vpath->ringh = ring; ++ ring->rpa_strip_vlan_tag = vp->vpath->vp_config->rpa_strip_vlan_tag; ++ ring->lro_enable = hldev->config.lro_enable; ++ ring->aggr_ack = vp->vpath->vp_config->aggr_ack; ++ ring->vp_id = vp_id; ++ ring->vp_reg = vp->vpath->vp_reg; ++ ring->common_reg = hldev->common_reg; ++ ring->stats = &vp->vpath->sw_stats->ring_stats; ++ ring->config = config; ++ ring->callback = attr->callback; ++ ring->rxd_init = attr->rxd_init; ++ ring->rxd_term = attr->rxd_term; ++ ring->buffer_mode = config->buffer_mode; ++ ring->tim_rti_cfg1_saved = vp->vpath->tim_rti_cfg1_saved; ++ ring->tim_rti_cfg3_saved = vp->vpath->tim_rti_cfg3_saved; ++ if (config->doorbell_mode == VXGE_HW_DOORBELL_MODE_ENABLE) ++ ring->rxd_qword_limit = config->rxd_qword_limit; ++ ++ ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode); ++ ring->rxd_priv_size = ++ sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space; ++ ring->per_rxd_space = attr->per_rxd_space; ++ ++ ring->rxd_priv_size = ++ ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) / ++ VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE; ++ ++ /* how many RxDs can fit into one block. Depends on configured ++ * buffer_mode. */ ++ ring->rxds_per_block = ++ vxge_hw_ring_rxds_per_block_get(config->buffer_mode); ++ ++ /* calculate actual RxD block private size */ ++ ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block; ++ ring_mp_callback.item_func_alloc = __vxge_hw_ring_mempool_item_alloc; ++ ring->mempool = __vxge_hw_mempool_create(hldev, ++ VXGE_HW_BLOCK_SIZE, ++ VXGE_HW_BLOCK_SIZE, ++ ring->rxdblock_priv_size, ++ ring->config->ring_blocks, ++ ring->config->ring_blocks, ++ &ring_mp_callback, ++ ring); ++ ++ if (ring->mempool == NULL) { ++ __vxge_hw_ring_delete(vp); ++ return VXGE_HW_ERR_OUT_OF_MEMORY; ++ } ++ ++ status = __vxge_hw_channel_initialize(&ring->channel); ++ if (status != VXGE_HW_OK) { ++ __vxge_hw_ring_delete(vp); ++ goto exit; ++ } ++ ++ if ((vp->vpath->hldev->config.lro_enable) && ++ (vp->vpath->hldev->config.lro_enable != VXGE_HW_GRO_ENABLE)){ ++ status = __vxge_hw_sw_lro_init(ring); ++ if (status != VXGE_HW_OK) { ++ __vxge_hw_ring_delete(vp); ++ goto exit; ++ } ++ } ++ ++ /* Note: ++ * Specifying rxd_init callback means two things: ++ * 1) rxds need to be initialized by driver at channel-open time; ++ * 2) rxds need to be posted at channel-open time ++ * (that's what the initial_replenish() below does) ++ * Currently we don't have a case when the 1) is done without the 2). ++ */ ++ if (ring->rxd_init) { ++ status = vxge_hw_ring_replenish(ring, 1); ++ if (status != VXGE_HW_OK) { ++ __vxge_hw_ring_delete(vp); ++ goto exit; ++ } ++ } ++ ++ /* initial replenish will increment the counter in its post() routine, ++ * we have to reset it */ ++ ring->stats->common_stats.usage_cnt = 0; ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_ring_abort - Returns the RxD ++ * This function terminates the RxDs of ring ++ */ ++enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring) ++{ ++ void *rxdh; ++ struct __vxge_hw_channel *channel; ++ ++ channel = &ring->channel; ++ ++ for (;;) { ++ vxge_hw_channel_dtr_try_complete(channel, &rxdh); ++ ++ if (rxdh == NULL) ++ break; ++ ++ vxge_hw_channel_dtr_complete(channel); ++ ++ if (ring->rxd_term) ++ ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED, ++ channel->userdata); ++ ++ vxge_hw_channel_dtr_free(channel, rxdh); ++ } ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * __vxge_hw_ring_reset - Resets the ring ++ * This function resets the ring during vpath reset operation ++ */ ++enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct __vxge_hw_channel *channel; ++ ++ channel = &ring->channel; ++ ++ __vxge_hw_ring_abort(ring); ++ ++ status = __vxge_hw_channel_reset(channel); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ if ((ring->lro_enable) && (ring->lro_enable != VXGE_HW_GRO_ENABLE)){ ++ status = __vxge_hw_sw_lro_reset(ring); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ } ++ ++ if (ring->rxd_init) { ++ status = vxge_hw_ring_replenish(ring, 1); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ } ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_ring_delete - Removes the ring ++ * This function freeup the memory pool and removes the ring ++ */ ++enum vxge_hw_status __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp) ++{ ++ struct __vxge_hw_ring *ring = vp->vpath->ringh; ++ ++ __vxge_hw_ring_abort(ring); ++ ++ if ((ring->lro_enable) && (ring->lro_enable != VXGE_HW_GRO_ENABLE)) ++ __vxge_hw_sw_lro_terminate(ring); ++ ++ if (ring->mempool) ++ __vxge_hw_mempool_destroy(ring->mempool); ++ ++ vp->vpath->ringh = NULL; ++ __vxge_hw_channel_free(&ring->channel); ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * __vxge_hw_mempool_grow ++ * Will resize mempool up to %num_allocate value. ++ */ ++enum vxge_hw_status ++__vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate, ++ u32 *num_allocated) ++{ ++ u32 i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0; ++ u32 n_items = mempool->items_per_memblock; ++ u32 start_block_idx = mempool->memblocks_allocated; ++ u32 end_block_idx = mempool->memblocks_allocated + num_allocate; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ *num_allocated = 0; ++ ++ if (end_block_idx > mempool->memblocks_max) { ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto exit; ++ } ++ ++ for (i = start_block_idx; i < end_block_idx; i++) { ++ u32 j; ++ u32 is_last = ((end_block_idx - 1) == i); ++ struct vxge_hw_mempool_dma *dma_object = ++ mempool->memblocks_dma_arr + i; ++ void *the_memblock; ++ ++ /* allocate memblock's private part. Each DMA memblock ++ * has a space allocated for item's private usage upon ++ * mempool's user request. Each time mempool grows, it will ++ * allocate new memblock and its private part at once. ++ * This helps to minimize memory usage a lot. */ ++ mempool->memblocks_priv_arr[i] = ++ vmalloc(mempool->items_priv_size * n_items); ++ if (mempool->memblocks_priv_arr[i] == NULL) { ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto exit; ++ } ++ ++ memset(mempool->memblocks_priv_arr[i], 0, ++ mempool->items_priv_size * n_items); ++ ++ /* allocate DMA-capable memblock */ ++ mempool->memblocks_arr[i] = ++ __vxge_hw_blockpool_malloc(mempool->devh, ++ dma_object); ++ if (mempool->memblocks_arr[i] == NULL) { ++ vfree(mempool->memblocks_priv_arr[i]); ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto exit; ++ } ++ ++ (*num_allocated)++; ++ mempool->memblocks_allocated++; ++ ++ memset(mempool->memblocks_arr[i], 0, mempool->memblock_size); ++ ++ the_memblock = mempool->memblocks_arr[i]; ++ ++ /* fill the items hash array */ ++ for (j = 0; j < n_items; j++) { ++ u32 index = i * n_items + j; ++ ++ if (first_time && index >= mempool->items_initial) ++ break; ++ ++ mempool->items_arr[index] = ++ ((char *)the_memblock + j*mempool->item_size); ++ ++ /* let caller to do more job on each item */ ++ if (mempool->item_func_alloc != NULL) ++ mempool->item_func_alloc(mempool, i, ++ dma_object, index, is_last); ++ ++ mempool->items_current = index + 1; ++ } ++ ++ if (first_time && mempool->items_current == ++ mempool->items_initial) ++ break; ++ } ++exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_mempool_create ++ * This function will create memory pool object. Pool may grow but will ++ * never shrink. Pool consists of number of dynamically allocated blocks ++ * with size enough to hold %items_initial number of items. Memory is ++ * DMA-able but client must map/unmap before interoperating with the device. ++ */ ++struct vxge_hw_mempool* ++__vxge_hw_mempool_create( ++ struct __vxge_hw_device *devh, ++ u32 memblock_size, ++ u32 item_size, ++ u32 items_priv_size, ++ u32 items_initial, ++ u32 items_max, ++ struct vxge_hw_mempool_cbs *mp_callback, ++ void *userdata) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ u32 memblocks_to_allocate; ++ struct vxge_hw_mempool *mempool = NULL; ++ u32 allocated; ++ ++ if (memblock_size < item_size) { ++ status = VXGE_HW_FAIL; ++ goto exit; ++ } ++ ++ mempool = (struct vxge_hw_mempool *) ++ vmalloc(sizeof(struct vxge_hw_mempool)); ++ if (mempool == NULL) { ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto exit; ++ } ++ memset(mempool, 0, sizeof(struct vxge_hw_mempool)); ++ ++ mempool->devh = devh; ++ mempool->memblock_size = memblock_size; ++ mempool->items_max = items_max; ++ mempool->items_initial = items_initial; ++ mempool->item_size = item_size; ++ mempool->items_priv_size = items_priv_size; ++ mempool->item_func_alloc = mp_callback->item_func_alloc; ++ mempool->userdata = userdata; ++ ++ mempool->memblocks_allocated = 0; ++ ++ mempool->items_per_memblock = memblock_size / item_size; ++ ++ mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) / ++ mempool->items_per_memblock; ++ ++ /* allocate array of memblocks */ ++ mempool->memblocks_arr = ++ (void **) vmalloc(sizeof(void *) * mempool->memblocks_max); ++ if (mempool->memblocks_arr == NULL) { ++ __vxge_hw_mempool_destroy(mempool); ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ mempool = NULL; ++ goto exit; ++ } ++ memset(mempool->memblocks_arr, 0, ++ sizeof(void *) * mempool->memblocks_max); ++ ++ /* allocate array of private parts of items per memblocks */ ++ mempool->memblocks_priv_arr = ++ (void **) vmalloc(sizeof(void *) * mempool->memblocks_max); ++ if (mempool->memblocks_priv_arr == NULL) { ++ __vxge_hw_mempool_destroy(mempool); ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ mempool = NULL; ++ goto exit; ++ } ++ memset(mempool->memblocks_priv_arr, 0, ++ sizeof(void *) * mempool->memblocks_max); ++ ++ /* allocate array of memblocks DMA objects */ ++ mempool->memblocks_dma_arr = (struct vxge_hw_mempool_dma *) ++ vmalloc(sizeof(struct vxge_hw_mempool_dma) * ++ mempool->memblocks_max); ++ ++ if (mempool->memblocks_dma_arr == NULL) { ++ __vxge_hw_mempool_destroy(mempool); ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ mempool = NULL; ++ goto exit; ++ } ++ memset(mempool->memblocks_dma_arr, 0, ++ sizeof(struct vxge_hw_mempool_dma) * ++ mempool->memblocks_max); ++ ++ /* allocate hash array of items */ ++ mempool->items_arr = ++ (void **) vmalloc(sizeof(void *) * mempool->items_max); ++ if (mempool->items_arr == NULL) { ++ __vxge_hw_mempool_destroy(mempool); ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ mempool = NULL; ++ goto exit; ++ } ++ memset(mempool->items_arr, 0, sizeof(void *) * mempool->items_max); ++ ++ /* calculate initial number of memblocks */ ++ memblocks_to_allocate = (mempool->items_initial + ++ mempool->items_per_memblock - 1) / ++ mempool->items_per_memblock; ++ ++ /* pre-allocate the mempool */ ++ status = __vxge_hw_mempool_grow(mempool, memblocks_to_allocate, ++ &allocated); ++ if (status != VXGE_HW_OK) { ++ __vxge_hw_mempool_destroy(mempool); ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ mempool = NULL; ++ goto exit; ++ } ++ ++exit: ++ return mempool; ++} ++ ++/* ++ * vxge_hw_mempool_destroy ++ */ ++void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool) ++{ ++ u32 i, j; ++ struct __vxge_hw_device *devh = mempool->devh; ++ ++ for (i = 0; i < mempool->memblocks_allocated; i++) { ++ struct vxge_hw_mempool_dma *dma_object; ++ ++ vxge_assert(mempool->memblocks_arr[i]); ++ vxge_assert(mempool->memblocks_dma_arr + i); ++ ++ dma_object = mempool->memblocks_dma_arr + i; ++ ++ for (j = 0; j < mempool->items_per_memblock; j++) { ++ u32 index = i * mempool->items_per_memblock + j; ++ ++ /* to skip last partially filled(if any) memblock */ ++ if (index >= mempool->items_current) ++ break; ++ } ++ ++ vfree(mempool->memblocks_priv_arr[i]); ++ ++ __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i], ++ mempool->memblock_size, dma_object); ++ } ++ ++ if (mempool->items_arr) ++ vfree(mempool->items_arr); ++ ++ if (mempool->memblocks_dma_arr) ++ vfree(mempool->memblocks_dma_arr); ++ ++ if (mempool->memblocks_priv_arr) ++ vfree(mempool->memblocks_priv_arr); ++ ++ if (mempool->memblocks_arr) ++ vfree(mempool->memblocks_arr); ++ ++ vfree(mempool); ++} ++ ++/* ++ * __vxge_hw_device_fifo_config_check - Check fifo configuration. ++ * Check the fifo configuration ++ */ ++enum vxge_hw_status ++__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config) ++{ ++ if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) || ++ (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS)) ++ return VXGE_HW_BADCFG_FIFO_BLOCKS; ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * __vxge_hw_device_vpath_config_check - Check vpath configuration. ++ * Check the vpath configuration ++ */ ++enum vxge_hw_status ++__vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config) ++{ ++ enum vxge_hw_status status; ++ ++ if ((vp_config->rx_bw_limit < VXGE_HW_VPATH_RX_BANDWIDTH_LIMIT_MIN) || ++ (vp_config->rx_bw_limit > ++ VXGE_HW_VPATH_RX_BANDWIDTH_LIMIT_MAX)) ++ return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH; ++ ++ if ((vp_config->tx_bw_limit < VXGE_HW_VPATH_TX_BANDWIDTH_LIMIT_MIN) || ++ (vp_config->tx_bw_limit > ++ VXGE_HW_VPATH_TX_BANDWIDTH_LIMIT_MAX)) ++ return VXGE_HW_BADCFG_VPATH_BANDWIDTH_LIMIT; ++ ++ status = __vxge_hw_device_fifo_config_check(&vp_config->fifo); ++ if (status != VXGE_HW_OK) ++ return status; ++ ++ if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) && ++ ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) || ++ (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU))) ++ return VXGE_HW_BADCFG_VPATH_MTU; ++ ++ if ((vp_config->rpa_strip_vlan_tag != ++ VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) && ++ (vp_config->rpa_strip_vlan_tag != ++ VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) && ++ (vp_config->rpa_strip_vlan_tag != ++ VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE)) ++ return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG; ++ ++ if ((vp_config->aggr_ack != VXGE_HW_VPATH_AGGR_ACK_ENABLE) && ++ (vp_config->aggr_ack != VXGE_HW_VPATH_AGGR_ACK_DISABLE) && ++ (vp_config->aggr_ack != VXGE_HW_VPATH_AGGR_ACK_DEFAULT)) ++ return VXGE_HW_BADCFG_VPATH_AGGR_ACK; ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * __vxge_hw_device_config_check - Check device configuration. ++ * Check the device configuration ++ */ ++enum vxge_hw_status ++__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config) ++{ ++ u32 i; ++ enum vxge_hw_status status; ++ ++ if ( ++ ++ (new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) && ++ (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) && ++ (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) && ++ (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF)) ++ return VXGE_HW_BADCFG_INTR_MODE; ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ status = __vxge_hw_device_vpath_config_check( ++ &new_config->vp_config[i]); ++ if (status != VXGE_HW_OK) ++ return status; ++ } ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * vxge_hw_device_config_default_get - Initialize device config with defaults. ++ * Initialize Titan device config with default values. ++ */ ++enum vxge_hw_status __devinit ++vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config) ++{ ++ u32 i; ++ ++ device_config->intr_mode = VXGE_HW_INTR_MODE_DEF; ++ device_config->rth_en = VXGE_HW_RTH_DEFAULT; ++ device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_DEFAULT; ++ device_config->device_poll_millis = VXGE_HW_DEF_DEVICE_POLL_MILLIS; ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ ++ device_config->vp_config[i].vp_id = i; ++ ++ device_config->vp_config[i].rx_bw_limit = ++ VXGE_HW_VPATH_RX_BANDWIDTH_LIMIT_DEFAULT; ++ ++ device_config->vp_config[i].tx_bw_limit = ++ VXGE_HW_VPATH_TX_BANDWIDTH_LIMIT_DEFAULT; ++ ++ device_config->vp_config[i].ring.enable = VXGE_HW_RING_DEFAULT; ++ ++ device_config->vp_config[i].ring.ring_blocks = ++ VXGE_HW_DEF_RING_BLOCKS; ++ ++ device_config->vp_config[i].ring.buffer_mode = ++ VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT; ++ ++ device_config->vp_config[i].ring.scatter_mode = ++ VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT; ++ device_config->vp_config[i].ring.doorbell_mode = VXGE_HW_DOORBELL_MODE_DEFAULT; ++ if (device_config->vp_config[i].ring.doorbell_mode == ++ VXGE_HW_DOORBELL_MODE_ENABLE) ++ device_config->vp_config[i].ring.rxd_qword_limit = ++ VXGE_HW_DEF_RING_RXD_QWORD_LIMIT; ++ ++ device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE; ++ ++ device_config->vp_config[i].fifo.fifo_blocks = ++ VXGE_HW_MIN_FIFO_BLOCKS; ++ ++ device_config->vp_config[i].fifo.max_frags = ++ VXGE_HW_MAX_FIFO_FRAGS; ++ ++ device_config->vp_config[i].fifo.memblock_size = ++ VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE; ++ ++ device_config->vp_config[i].fifo.alignment_size = ++ VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE; ++ ++ device_config->vp_config[i].fifo.intr = ++ VXGE_HW_FIFO_QUEUE_INTR_DEFAULT; ++ ++ device_config->vp_config[i].fifo.no_snoop_bits = ++ VXGE_HW_FIFO_NO_SNOOP_DEFAULT; ++ device_config->vp_config[i].tti.intr_enable = ++ VXGE_HW_TIM_INTR_DEFAULT; ++ ++ device_config->vp_config[i].tti.btimer_val = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].tti.timer_ac_en = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].tti.timer_ci_en = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].tti.timer_ri_en = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].tti.rtimer_val = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].tti.util_sel = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].tti.ltimer_val = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].tti.urange_a = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].tti.uec_a = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].tti.urange_b = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].tti.uec_b = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].tti.urange_c = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].tti.uec_c = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].tti.uec_d = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.intr_enable = ++ VXGE_HW_TIM_INTR_DEFAULT; ++ ++ device_config->vp_config[i].rti.btimer_val = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.timer_ac_en = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.timer_ci_en = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.timer_ri_en = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.rtimer_val = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.util_sel = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.ltimer_val = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.urange_a = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.uec_a = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.urange_b = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.uec_b = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.urange_c = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.uec_c = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].rti.uec_d = ++ VXGE_HW_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].mtu = ++ VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU; ++ ++ device_config->vp_config[i].rpa_strip_vlan_tag = ++ VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT; ++ ++ device_config->vp_config[i].aggr_ack = ++ VXGE_HW_VPATH_AGGR_ACK_DEFAULT; ++ } ++ device_config->stats_read_method = VXGE_HW_STATS_READ_METHOD_DEFAULT; ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion. ++ * Set the swapper bits appropriately for the legacy section. ++ */ ++enum vxge_hw_status ++__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg) ++{ ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ val64 = readq(&legacy_reg->toc_swapper_fb); ++ ++ wmb(); ++ ++ switch (val64) { ++ ++ case VXGE_HW_SWAPPER_INITIAL_VALUE: ++ return status; ++ ++ case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED: ++ writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE, ++ &legacy_reg->pifm_rd_swap_en); ++ writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE, ++ &legacy_reg->pifm_rd_flip_en); ++ writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE, ++ &legacy_reg->pifm_wr_swap_en); ++ writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE, ++ &legacy_reg->pifm_wr_flip_en); ++ break; ++ ++ case VXGE_HW_SWAPPER_BYTE_SWAPPED: ++ writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE, ++ &legacy_reg->pifm_rd_swap_en); ++ writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE, ++ &legacy_reg->pifm_wr_swap_en); ++ break; ++ ++ case VXGE_HW_SWAPPER_BIT_FLIPPED: ++ writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE, ++ &legacy_reg->pifm_rd_flip_en); ++ writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE, ++ &legacy_reg->pifm_wr_flip_en); ++ break; ++ } ++ ++ wmb(); ++ ++ val64 = readq(&legacy_reg->toc_swapper_fb); ++ ++ if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE) ++ status = VXGE_HW_ERR_SWAPPER_CTRL; ++ ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath. ++ * Set the swapper bits appropriately for the vpath. ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg) ++{ ++#ifndef __BIG_ENDIAN ++ u64 val64; ++ ++ val64 = readq(&vpath_reg->vpath_general_cfg1); ++ wmb(); ++ val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN; ++ writeq(val64, &vpath_reg->vpath_general_cfg1); ++ wmb(); ++#endif ++ return VXGE_HW_OK; ++} ++ ++/* ++ * __vxge_hw_kdfc_swapper_set - Set the swapper bits for the kdfc. ++ * Set the swapper bits appropriately for the vpath. ++ */ ++enum vxge_hw_status ++__vxge_hw_kdfc_swapper_set( ++ struct vxge_hw_legacy_reg __iomem *legacy_reg, ++ struct vxge_hw_vpath_reg __iomem *vpath_reg) ++{ ++ u64 val64; ++ ++ val64 = readq(&legacy_reg->pifm_wr_swap_en); ++ ++ if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) { ++ val64 = readq(&vpath_reg->kdfcctl_cfg0); ++ wmb(); ++ ++ val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 | ++ VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 | ++ VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2; ++ ++ writeq(val64, &vpath_reg->kdfcctl_cfg0); ++ wmb(); ++ } ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * vxge_hw_mgmt_device_config - Retrieve device configuration. ++ * Get device configuration. Permits to retrieve at run-time configuration ++ * values that were used to initialize and configure the device. ++ */ ++enum vxge_hw_status ++vxge_hw_mgmt_device_config(struct __vxge_hw_device *hldev, ++ struct vxge_hw_device_config *dev_config, int size) ++{ ++ ++ if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) ++ return VXGE_HW_ERR_INVALID_DEVICE; ++ ++ if (size != sizeof(struct vxge_hw_device_config)) ++ return VXGE_HW_ERR_VERSION_CONFLICT; ++ ++ memcpy(dev_config, &hldev->config, ++ sizeof(struct vxge_hw_device_config)); ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * vxge_hw_mgmt_reg_read - Read Titan register. ++ */ ++enum vxge_hw_status ++vxge_hw_mgmt_reg_read(struct __vxge_hw_device *hldev, ++ enum vxge_hw_mgmt_reg_type type, ++ u32 index, u32 offset, u64 *value) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) { ++ status = VXGE_HW_ERR_INVALID_DEVICE; ++ goto exit; ++ } ++ ++ switch (type) { ++ case vxge_hw_mgmt_reg_type_legacy: ++ if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ *value = readq((void __iomem *)hldev->legacy_reg + offset); ++ break; ++ case vxge_hw_mgmt_reg_type_toc: ++ if (offset > sizeof(struct vxge_hw_toc_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ *value = readq((void __iomem *)hldev->toc_reg + offset); ++ break; ++ case vxge_hw_mgmt_reg_type_common: ++ if (offset > sizeof(struct vxge_hw_common_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ *value = readq((void __iomem *)hldev->common_reg + offset); ++ break; ++ case vxge_hw_mgmt_reg_type_mrpcim: ++ if (!(hldev->access_rights & ++ VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) { ++ status = VXGE_HW_ERR_PRIVILAGED_OPEARATION; ++ break; ++ } ++ if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ *value = readq((void __iomem *)hldev->mrpcim_reg + offset); ++ break; ++ case vxge_hw_mgmt_reg_type_srpcim: ++ if (!(hldev->access_rights & ++ VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) { ++ status = VXGE_HW_ERR_PRIVILAGED_OPEARATION; ++ break; ++ } ++ if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) { ++ status = VXGE_HW_ERR_INVALID_INDEX; ++ break; ++ } ++ if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ *value = readq((void __iomem *)hldev->srpcim_reg[index] + ++ offset); ++ break; ++ case vxge_hw_mgmt_reg_type_vpmgmt: ++ if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) || ++ (!(hldev->vpath_assignments & vxge_mBIT(index)))) { ++ status = VXGE_HW_ERR_INVALID_INDEX; ++ break; ++ } ++ if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ *value = readq((void __iomem *)hldev->vpmgmt_reg[index] + ++ offset); ++ break; ++ case vxge_hw_mgmt_reg_type_vpath: ++ if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) || ++ (!(hldev->vpath_assignments & vxge_mBIT(index)))) { ++ status = VXGE_HW_ERR_INVALID_INDEX; ++ break; ++ } ++ if (index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) { ++ status = VXGE_HW_ERR_INVALID_INDEX; ++ break; ++ } ++ if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ *value = readq((void __iomem *)hldev->vpath_reg[index] + ++ offset); ++ break; ++ default: ++ status = VXGE_HW_ERR_INVALID_TYPE; ++ break; ++ } ++ ++exit: ++ return status; ++} ++ ++ ++ ++/* ++ * vxge_hw_vpath_strip_fcs_check - Check for FCS strip. ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask) ++{ ++ struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ int i = 0, j = 0; ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ if (!((vpath_mask) & vxge_mBIT(i))) ++ continue; ++ vpmgmt_reg = hldev->vpmgmt_reg[i]; ++ for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) { ++ if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j]) ++ & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS) ++ return VXGE_HW_FAIL; ++ } ++ } ++ return status; ++} ++ ++/* ++ * vxge_hw_mgmt_reg_Write - Write Titan register. ++ */ ++enum vxge_hw_status ++vxge_hw_mgmt_reg_write(struct __vxge_hw_device *hldev, ++ enum vxge_hw_mgmt_reg_type type, ++ u32 index, u32 offset, u64 value) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) { ++ status = VXGE_HW_ERR_INVALID_DEVICE; ++ goto exit; ++ } ++ ++ switch (type) { ++ case vxge_hw_mgmt_reg_type_legacy: ++ if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ writeq(value, (void __iomem *)hldev->legacy_reg + offset); ++ break; ++ case vxge_hw_mgmt_reg_type_toc: ++ if (offset > sizeof(struct vxge_hw_toc_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ writeq(value, (void __iomem *)hldev->toc_reg + offset); ++ break; ++ case vxge_hw_mgmt_reg_type_common: ++ if (offset > sizeof(struct vxge_hw_common_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ writeq(value, (void __iomem *)hldev->common_reg + offset); ++ break; ++ case vxge_hw_mgmt_reg_type_mrpcim: ++ if (!(hldev->access_rights & ++ VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) { ++ status = VXGE_HW_ERR_PRIVILAGED_OPEARATION; ++ break; ++ } ++ if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ writeq(value, (void __iomem *)hldev->mrpcim_reg + offset); ++ break; ++ case vxge_hw_mgmt_reg_type_srpcim: ++ if (!(hldev->access_rights & ++ VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) { ++ status = VXGE_HW_ERR_PRIVILAGED_OPEARATION; ++ break; ++ } ++ if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) { ++ status = VXGE_HW_ERR_INVALID_INDEX; ++ break; ++ } ++ if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ writeq(value, (void __iomem *)hldev->srpcim_reg[index] + ++ offset); ++ ++ break; ++ case vxge_hw_mgmt_reg_type_vpmgmt: ++ if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) || ++ (!(hldev->vpath_assignments & vxge_mBIT(index)))) { ++ status = VXGE_HW_ERR_INVALID_INDEX; ++ break; ++ } ++ if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] + ++ offset); ++ break; ++ case vxge_hw_mgmt_reg_type_vpath: ++ if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES-1) || ++ (!(hldev->vpath_assignments & vxge_mBIT(index)))) { ++ status = VXGE_HW_ERR_INVALID_INDEX; ++ break; ++ } ++ if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) { ++ status = VXGE_HW_ERR_INVALID_OFFSET; ++ break; ++ } ++ writeq(value, (void __iomem *)hldev->vpath_reg[index] + ++ offset); ++ break; ++ default: ++ status = VXGE_HW_ERR_INVALID_TYPE; ++ break; ++ } ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD ++ * list callback ++ * This function is callback passed to __vxge_hw_mempool_create to create memory ++ * pool for TxD list ++ */ ++static void ++__vxge_hw_fifo_mempool_item_alloc( ++ struct vxge_hw_mempool *mempoolh, ++ u32 memblock_index, struct vxge_hw_mempool_dma *dma_object, ++ u32 index, u32 is_last) ++{ ++ u32 memblock_item_idx; ++ struct __vxge_hw_fifo_txdl_priv *txdl_priv; ++ struct vxge_hw_fifo_txd *txdp = ++ (struct vxge_hw_fifo_txd *)mempoolh->items_arr[index]; ++ struct __vxge_hw_fifo *fifo = ++ (struct __vxge_hw_fifo *)mempoolh->userdata; ++ void *memblock = mempoolh->memblocks_arr[memblock_index]; ++ ++ vxge_assert(txdp); ++ ++ txdp->host_control = (u64) (size_t) ++ __vxge_hw_mempool_item_priv(mempoolh, memblock_index, txdp, ++ &memblock_item_idx); ++ ++ txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp); ++ ++ vxge_assert(txdl_priv); ++ ++ fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp; ++ ++ /* pre-format HW's TxDL's private */ ++ txdl_priv->dma_offset = (char *)txdp - (char *)memblock; ++ txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset; ++ txdl_priv->dma_handle = dma_object->handle; ++ txdl_priv->memblock = memblock; ++ txdl_priv->first_txdp = txdp; ++ txdl_priv->next_txdl_priv = NULL; ++ txdl_priv->alloc_frags = 0; ++ ++ return; ++} ++ ++/* ++ * __vxge_hw_fifo_create - Create a FIFO ++ * This function creates FIFO and initializes it. ++ */ ++enum vxge_hw_status ++__vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp, ++ struct vxge_hw_fifo_attr *attr) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct __vxge_hw_fifo *fifo; ++ struct vxge_hw_fifo_config *config; ++ u32 txdl_size, txdl_per_memblock; ++ struct vxge_hw_mempool_cbs fifo_mp_callback; ++ struct __vxge_hw_virtualpath *vpath; ++ ++ if ((vp == NULL) || (attr == NULL)) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ vpath = vp->vpath; ++ config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo; ++ ++ txdl_size = config->max_frags * sizeof(struct vxge_hw_fifo_txd); ++ ++ txdl_per_memblock = config->memblock_size / txdl_size; ++ ++ fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp, ++ VXGE_HW_CHANNEL_TYPE_FIFO, ++ config->fifo_blocks * txdl_per_memblock, ++ attr->per_txdl_space, attr->userdata); ++ ++ if (fifo == NULL) { ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto exit; ++ } ++ ++ vpath->fifoh = fifo; ++ fifo->nofl_db = vpath->nofl_db; ++ ++ fifo->vp_id = vpath->vp_id; ++ fifo->vp_reg = vpath->vp_reg; ++ fifo->stats = &vpath->sw_stats->fifo_stats; ++ ++ fifo->config = config; ++ ++ /* apply "interrupts per txdl" attribute */ ++ fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ; ++ ++ if (fifo->config->intr) ++ fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST; ++ ++ fifo->no_snoop_bits = config->no_snoop_bits; ++ ++ /* ++ * FIFO memory management strategy: ++ * ++ * TxDL split into three independent parts: ++ * - set of TxD's ++ * - TxD HW private part ++ * - driver private part ++ * ++ * Adaptative memory allocation used. i.e. Memory allocated on ++ * demand with the size which will fit into one memory block. ++ * One memory block may contain more than one TxDL. ++ * ++ * During "reserve" operations more memory can be allocated on demand ++ * for example due to FIFO full condition. ++ * ++ * Pool of memory memblocks never shrinks except in __vxge_hw_fifo_close ++ * routine which will essentially stop the channel and free resources. ++ */ ++ ++ /* TxDL common private size == TxDL private + driver private */ ++ fifo->priv_size = ++ sizeof(struct __vxge_hw_fifo_txdl_priv) + attr->per_txdl_space; ++ fifo->priv_size = ((fifo->priv_size + VXGE_CACHE_LINE_SIZE - 1) / ++ VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE; ++ ++ fifo->per_txdl_space = attr->per_txdl_space; ++ ++ /* recompute txdl size to be cacheline aligned */ ++ fifo->txdl_size = txdl_size; ++ fifo->txdl_per_memblock = txdl_per_memblock; ++ ++ fifo->txdl_term = attr->txdl_term; ++ fifo->callback = attr->callback; ++ ++ if (fifo->txdl_per_memblock == 0) { ++ __vxge_hw_fifo_delete(vp); ++ status = VXGE_HW_ERR_INVALID_BLOCK_SIZE; ++ goto exit; ++ } ++ ++ fifo_mp_callback.item_func_alloc = __vxge_hw_fifo_mempool_item_alloc; ++ ++ fifo->mempool = ++ __vxge_hw_mempool_create(vpath->hldev, ++ fifo->config->memblock_size, ++ fifo->txdl_size, ++ fifo->priv_size, ++ (fifo->config->fifo_blocks * fifo->txdl_per_memblock), ++ (fifo->config->fifo_blocks * fifo->txdl_per_memblock), ++ &fifo_mp_callback, ++ fifo); ++ ++ if (fifo->mempool == NULL) { ++ __vxge_hw_fifo_delete(vp); ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto exit; ++ } ++ ++ status = __vxge_hw_channel_initialize(&fifo->channel); ++ if (status != VXGE_HW_OK) { ++ __vxge_hw_fifo_delete(vp); ++ goto exit; ++ } ++ ++ vxge_assert(fifo->channel.reserve_ptr); ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_fifo_abort - Returns the TxD ++ * This function terminates the TxDs of fifo ++ */ ++enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo) ++{ ++ void *txdlh; ++ ++ for (;;) { ++ vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh); ++ ++ if (txdlh == NULL) ++ break; ++ ++ vxge_hw_channel_dtr_complete(&fifo->channel); ++ ++ if (fifo->txdl_term) { ++ fifo->txdl_term(txdlh, ++ VXGE_HW_TXDL_STATE_POSTED, ++ fifo->channel.userdata); ++ } ++ ++ vxge_hw_channel_dtr_free(&fifo->channel, txdlh); ++ } ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * __vxge_hw_fifo_reset - Resets the fifo ++ * This function resets the fifo during vpath reset operation ++ */ ++enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ __vxge_hw_fifo_abort(fifo); ++ status = __vxge_hw_channel_reset(&fifo->channel); ++ ++ return status; ++} ++ ++/* ++ * __vxge_hw_fifo_delete - Removes the FIFO ++ * This function freeup the memory pool and removes the FIFO ++ */ ++enum vxge_hw_status __vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp) ++{ ++ struct __vxge_hw_fifo *fifo = vp->vpath->fifoh; ++ ++ __vxge_hw_fifo_abort(fifo); ++ ++ if (fifo->mempool) ++ __vxge_hw_mempool_destroy(fifo->mempool); ++ ++ vp->vpath->fifoh = NULL; ++ ++ __vxge_hw_channel_free(&fifo->channel); ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * __vxge_hw_vpath_pci_read - Read the content of given address ++ * in pci config space. ++ * Read from the vpath pci config space. ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath, ++ u32 phy_func_0, u32 offset, u32 *val) ++{ ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg; ++ ++ val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset); ++ ++ if (phy_func_0) ++ val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0; ++ ++ writeq(val64, &vp_reg->pci_config_access_cfg1); ++ wmb(); ++ writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ, ++ &vp_reg->pci_config_access_cfg2); ++ wmb(); ++ ++ status = __vxge_hw_device_register_poll( ++ &vp_reg->pci_config_access_cfg2, ++ VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = readq(&vp_reg->pci_config_access_status); ++ ++ if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) { ++ status = VXGE_HW_FAIL; ++ *val = 0; ++ } else ++ *val = (u32)vxge_bVALn(val64, 32, 32); ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_func_id_get - Get the function id of the vpath. ++ * Returns the function number of the vpath. ++ */ ++u32 ++__vxge_hw_vpath_func_id_get(u32 vp_id, ++ struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg) ++{ ++ u64 val64; ++ ++ val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1); ++ ++ return ++ (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64); ++} ++ ++/* ++ * __vxge_hw_read_rts_ds - Program RTS steering critieria ++ */ ++static inline void ++__vxge_hw_read_rts_ds(struct vxge_hw_vpath_reg __iomem *vpath_reg, ++ u64 dta_struct_sel) ++{ ++ writeq(0, &vpath_reg->rts_access_steer_ctrl); ++ wmb(); ++ writeq(dta_struct_sel, &vpath_reg->rts_access_steer_data0); ++ writeq(0, &vpath_reg->rts_access_steer_data1); ++ wmb(); ++ return; ++} ++ ++ ++/* ++ * __vxge_hw_vpath_card_info_get - Get the serial numbers, ++ * part number and product description. ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_card_info_get( ++ u32 vp_id, ++ struct vxge_hw_vpath_reg __iomem *vpath_reg, ++ struct vxge_hw_device_hw_info *hw_info) ++{ ++ u32 i, j; ++ u64 val64; ++ u64 data1 = 0ULL; ++ u64 data2 = 0ULL; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ u8 *serial_number = hw_info->serial_number; ++ u8 *part_number = hw_info->part_number; ++ u8 *product_desc = hw_info->product_desc; ++ ++ __vxge_hw_read_rts_ds(vpath_reg, ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER); ++ ++ val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); ++ ++ status = __vxge_hw_pio_mem_write64(val64, ++ &vpath_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ VXGE_HW_DEF_DEVICE_POLL_MILLIS); ++ ++ if (status != VXGE_HW_OK) ++ return status; ++ ++ val64 = readq(&vpath_reg->rts_access_steer_ctrl); ++ ++ if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { ++ data1 = readq(&vpath_reg->rts_access_steer_data0); ++ ((u64 *)serial_number)[0] = be64_to_cpu(data1); ++ ++ data2 = readq(&vpath_reg->rts_access_steer_data1); ++ ((u64 *)serial_number)[1] = be64_to_cpu(data2); ++ status = VXGE_HW_OK; ++ } else ++ *serial_number = 0; ++ ++ __vxge_hw_read_rts_ds(vpath_reg, ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER); ++ ++ val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); ++ ++ status = __vxge_hw_pio_mem_write64(val64, ++ &vpath_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ VXGE_HW_DEF_DEVICE_POLL_MILLIS); ++ ++ if (status != VXGE_HW_OK) ++ return status; ++ ++ val64 = readq(&vpath_reg->rts_access_steer_ctrl); ++ ++ if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { ++ ++ data1 = readq(&vpath_reg->rts_access_steer_data0); ++ ((u64 *)part_number)[0] = be64_to_cpu(data1); ++ ++ data2 = readq(&vpath_reg->rts_access_steer_data1); ++ ((u64 *)part_number)[1] = be64_to_cpu(data2); ++ ++ status = VXGE_HW_OK; ++ ++ } else ++ *part_number = 0; ++ ++ j = 0; ++ ++ for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0; ++ i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) { ++ ++ __vxge_hw_read_rts_ds(vpath_reg, i); ++ ++ val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); ++ ++ status = __vxge_hw_pio_mem_write64(val64, ++ &vpath_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ VXGE_HW_DEF_DEVICE_POLL_MILLIS); ++ ++ if (status != VXGE_HW_OK) ++ return status; ++ ++ val64 = readq(&vpath_reg->rts_access_steer_ctrl); ++ ++ if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { ++ ++ data1 = readq(&vpath_reg->rts_access_steer_data0); ++ ((u64 *)product_desc)[j++] = be64_to_cpu(data1); ++ ++ data2 = readq(&vpath_reg->rts_access_steer_data1); ++ ((u64 *)product_desc)[j++] = be64_to_cpu(data2); ++ ++ status = VXGE_HW_OK; ++ } else ++ *product_desc = 0; ++ } ++ ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_fw_ver_get - Get the fw version ++ * Returns FW Version ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_fw_ver_get( ++ u32 vp_id, ++ struct vxge_hw_vpath_reg __iomem *vpath_reg, ++ struct vxge_hw_device_hw_info *hw_info) ++{ ++ u64 val64; ++ u64 data1 = 0ULL; ++ u64 data2 = 0ULL; ++ struct vxge_hw_device_version *fw_version = &hw_info->fw_version; ++ struct vxge_hw_device_date *fw_date = &hw_info->fw_date; ++ struct vxge_hw_device_version *flash_version = &hw_info->flash_version; ++ struct vxge_hw_device_date *flash_date = &hw_info->flash_date; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); ++ ++ status = __vxge_hw_pio_mem_write64(val64, ++ &vpath_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ VXGE_HW_DEF_DEVICE_POLL_MILLIS); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = readq(&vpath_reg->rts_access_steer_ctrl); ++ ++ if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { ++ ++ data1 = readq(&vpath_reg->rts_access_steer_data0); ++ data2 = readq(&vpath_reg->rts_access_steer_data1); ++ ++ fw_date->day = ++ (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY( ++ data1); ++ fw_date->month = ++ (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH( ++ data1); ++ fw_date->year = ++ (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR( ++ data1); ++ ++ snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d", ++ fw_date->month, fw_date->day, fw_date->year); ++ ++ fw_version->major = ++ (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data1); ++ fw_version->minor = ++ (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data1); ++ fw_version->build = ++ (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data1); ++ ++ snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d", ++ fw_version->major, fw_version->minor, fw_version->build); ++ ++ flash_date->day = ++ (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data2); ++ flash_date->month = ++ (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data2); ++ flash_date->year = ++ (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data2); ++ ++ snprintf(flash_date->date, VXGE_HW_FW_STRLEN, ++ "%2.2d/%2.2d/%4.4d", ++ flash_date->month, flash_date->day, flash_date->year); ++ ++ flash_version->major = ++ (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data2); ++ flash_version->minor = ++ (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data2); ++ flash_version->build = ++ (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data2); ++ ++ snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d", ++ flash_version->major, flash_version->minor, ++ flash_version->build); ++ ++ status = VXGE_HW_OK; ++ ++ } else ++ status = VXGE_HW_FAIL; ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode ++ * Returns pci function mode ++ */ ++u64 ++__vxge_hw_vpath_pci_func_mode_get( ++ u32 vp_id, ++ struct vxge_hw_vpath_reg __iomem *vpath_reg) ++{ ++ u64 val64; ++ u64 data1 = 0ULL; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ __vxge_hw_read_rts_ds(vpath_reg, ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE); ++ ++ val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); ++ ++ status = __vxge_hw_pio_mem_write64(val64, ++ &vpath_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ VXGE_HW_DEF_DEVICE_POLL_MILLIS); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = readq(&vpath_reg->rts_access_steer_ctrl); ++ ++ if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { ++ data1 = readq(&vpath_reg->rts_access_steer_data0); ++ status = VXGE_HW_OK; ++ } else { ++ data1 = 0; ++ status = VXGE_HW_FAIL; ++ } ++exit: ++ return data1; ++} ++ ++/** ++ * vxge_hw_device_flick_link_led - Flick (blink) link LED. ++ * @hldev: HW device. ++ * @on_off: TRUE if flickering to be on, FALSE to be off ++ * ++ * Flicker the link LED. ++ */ ++enum vxge_hw_status ++vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev, ++ u64 on_off) ++{ ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ ++ if (hldev == NULL) { ++ status = VXGE_HW_ERR_INVALID_DEVICE; ++ goto exit; ++ } ++ ++ vp_reg = hldev->vpath_reg[hldev->first_vp_id]; ++ ++ writeq(0, &vp_reg->rts_access_steer_ctrl); ++ wmb(); ++ writeq(on_off, &vp_reg->rts_access_steer_data0); ++ writeq(0, &vp_reg->rts_access_steer_data1); ++ wmb(); ++ ++ val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); ++ ++ status = __vxge_hw_pio_mem_write64(val64, ++ &vp_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ VXGE_HW_DEF_DEVICE_POLL_MILLIS); ++exit: ++ return status; ++} ++/* ++ * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_rts_table_get( ++ struct __vxge_hw_vpath_handle *vp, ++ u32 action, u32 rts_table, u32 offset, u64 *data1, u64 *data2) ++{ ++ u64 val64; ++ struct __vxge_hw_virtualpath *vpath; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ vpath = vp->vpath; ++ vp_reg = vpath->vp_reg; ++ ++ val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset); ++ ++ if ((rts_table == ++ VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) || ++ (rts_table == ++ VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) || ++ (rts_table == ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) || ++ (rts_table == ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) { ++ val64 = val64 | VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL; ++ } ++ ++ status = __vxge_hw_pio_mem_write64(val64, ++ &vp_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ vpath->hldev->config.device_poll_millis); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = readq(&vp_reg->rts_access_steer_ctrl); ++ ++ if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { ++ ++ *data1 = readq(&vp_reg->rts_access_steer_data0); ++ ++ if ((rts_table == ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) || ++ (rts_table == ++ VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) { ++ *data2 = readq(&vp_reg->rts_access_steer_data1); ++ } ++ status = VXGE_HW_OK; ++ } else ++ status = VXGE_HW_FAIL; ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_rts_table_set( ++ struct __vxge_hw_vpath_handle *vp, u32 action, u32 rts_table, ++ u32 offset, u64 data1, u64 data2) ++{ ++ u64 val64; ++ struct __vxge_hw_virtualpath *vpath; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ vpath = vp->vpath; ++ vp_reg = vpath->vp_reg; ++ ++ writeq(data1, &vp_reg->rts_access_steer_data0); ++ wmb(); ++ ++ if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) || ++ (rts_table == ++ VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) { ++ writeq(data2, &vp_reg->rts_access_steer_data1); ++ wmb(); ++ } ++ ++ val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset); ++ ++ status = __vxge_hw_pio_mem_write64(val64, ++ &vp_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ vpath->hldev->config.device_poll_millis); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = readq(&vp_reg->rts_access_steer_ctrl); ++ ++ if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) ++ status = VXGE_HW_OK; ++ else ++ status = VXGE_HW_FAIL; ++exit: ++ return status; ++} ++/* ++ * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath ++ * from MAC address table. ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_addr_get( ++ u32 vp_id, struct vxge_hw_vpath_reg __iomem *vpath_reg, ++ u8 (macaddr)[ETH_ALEN], u8 (macaddr_mask)[ETH_ALEN]) ++{ ++ u32 i; ++ u64 val64; ++ u64 data1 = 0ULL; ++ u64 data2 = 0ULL; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); ++ ++ status = __vxge_hw_pio_mem_write64(val64, ++ &vpath_reg->rts_access_steer_ctrl, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, ++ VXGE_HW_DEF_DEVICE_POLL_MILLIS); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = readq(&vpath_reg->rts_access_steer_ctrl); ++ ++ if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { ++ ++ data1 = readq(&vpath_reg->rts_access_steer_data0); ++ data2 = readq(&vpath_reg->rts_access_steer_data1); ++ ++ data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1); ++ data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK( ++ data2); ++ ++ for (i = ETH_ALEN; i > 0; i--) { ++ macaddr[i-1] = (u8)(data1 & 0xFF); ++ data1 >>= 8; ++ ++ macaddr_mask[i-1] = (u8)(data2 & 0xFF); ++ data2 >>= 8; ++ } ++ status = VXGE_HW_OK; ++ } else ++ status = VXGE_HW_FAIL; ++exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_vpath_rts_rth_set - Set/configure RTS hashing. ++ */ ++enum vxge_hw_status vxge_hw_vpath_rts_rth_set( ++ struct __vxge_hw_vpath_handle *vp, ++ enum vxge_hw_rth_algoritms algorithm, ++ struct vxge_hw_rth_hash_types *hash_type, ++ u16 bucket_size) ++{ ++ u64 data0, data1; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ status = __vxge_hw_vpath_rts_table_get(vp, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG, ++ 0, &data0, &data1); ++ ++ data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) | ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3)); ++ ++ data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN | ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) | ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm); ++ ++ if (hash_type->hash_type_tcpipv4_en) ++ data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN; ++ ++ if (hash_type->hash_type_ipv4_en) ++ data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN; ++ ++ if (hash_type->hash_type_tcpipv6_en) ++ data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN; ++ ++ if (hash_type->hash_type_ipv6_en) ++ data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN; ++ ++ if (hash_type->hash_type_tcpipv6ex_en) ++ data0 |= ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN; ++ ++ if (hash_type->hash_type_ipv6ex_en) ++ data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN; ++ ++ if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0)) ++ data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE; ++ else ++ data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE; ++ ++ status = __vxge_hw_vpath_rts_table_set(vp, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG, ++ 0, data0, 0); ++exit: ++ return status; ++} ++ ++static void ++vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1, ++ u16 flag, u8 *itable) ++{ ++ switch (flag) { ++ case 1: ++ *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)| ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN | ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA( ++ itable[j]); ++ case 2: ++ *data0 |= ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j)| ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN | ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA( ++ itable[j]); ++ case 3: ++ *data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j)| ++ VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN | ++ VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA( ++ itable[j]); ++ case 4: ++ *data1 |= ++ VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j)| ++ VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN | ++ VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA( ++ itable[j]); ++ default: ++ return; ++ } ++} ++/* ++ * vxge_hw_vpath_rts_rth_itable_set - Set/configure indirection table (IT). ++ */ ++enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set( ++ struct __vxge_hw_vpath_handle **vpath_handles, ++ u32 vpath_count, ++ u8 *mtable, ++ u8 *itable, ++ u32 itable_size) ++{ ++ u32 i, j, action, rts_table; ++ u64 data0; ++ u64 data1; ++ u32 max_entries; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct __vxge_hw_vpath_handle *vp = vpath_handles[0]; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ max_entries = (((u32)1) << itable_size); ++ ++ action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY; ++ rts_table = ++ VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT; ++ for (i = 0; i < vpath_count; i++) { ++ ++ for (j = 0; j < max_entries;) { ++ ++ data0 = 0; ++ data1 = 0; ++ ++ while (j < max_entries) { ++ if (mtable[itable[j]] != i) { ++ j++; ++ continue; ++ } ++ vxge_hw_rts_rth_data0_data1_get(j, ++ &data0, &data1, 1, itable); ++ j++; ++ break; ++ } ++ ++ while (j < max_entries) { ++ if (mtable[itable[j]] != i) { ++ j++; ++ continue; ++ } ++ vxge_hw_rts_rth_data0_data1_get(j, ++ &data0, &data1, 2, itable); ++ j++; ++ break; ++ } ++ ++ while (j < max_entries) { ++ if (mtable[itable[j]] != i) { ++ j++; ++ continue; ++ } ++ vxge_hw_rts_rth_data0_data1_get(j, ++ &data0, &data1, 3, itable); ++ j++; ++ break; ++ } ++ ++ while (j < max_entries) { ++ if (mtable[itable[j]] != i) { ++ j++; ++ continue; ++ } ++ vxge_hw_rts_rth_data0_data1_get(j, ++ &data0, &data1, 4, itable); ++ j++; ++ break; ++ } ++ ++ if (data0 != 0) { ++ status = __vxge_hw_vpath_rts_table_set( ++ vpath_handles[i], ++ action, rts_table, ++ 0, data0, data1); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ } ++ } ++ } ++exit: ++ return status; ++} ++ ++ ++/** ++ * vxge_hw_vpath_check_leak - Check for memory leak ++ * @ringh: Handle to the ring object used for receive ++ * ++ * If PRC_RXD_DOORBELL_VPn.NEW_QW_CNT is larger or equal to ++ * PRC_CFG6_VPn.RXD_SPAT then a leak has occurred. ++ * Returns: VXGE_HW_FAIL, if leak has occurred. ++ * ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ring) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ u64 rxd_new_count, rxd_spat; ++ ++ if (ring == NULL) ++ return status; ++ ++ rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell); ++ rxd_spat = readq(&ring->vp_reg->prc_cfg6); ++ rxd_spat = VXGE_HW_PRC_CFG6_RXD_SPAT(rxd_spat); ++ ++ if (rxd_new_count >= rxd_spat) ++ status = VXGE_HW_FAIL; ++ ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_mgmt_read ++ * This routine reads the vpath_mgmt registers ++ */ ++static enum vxge_hw_status ++__vxge_hw_vpath_mgmt_read( ++ struct __vxge_hw_device *hldev, ++ struct __vxge_hw_virtualpath *vpath) ++{ ++ u32 i, mtu = 0, max_pyld = 0; ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) { ++ ++ val64 = readq(&vpath->vpmgmt_reg-> ++ rxmac_cfg0_port_vpmgmt_clone[i]); ++ max_pyld = ++ (u32) ++ VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN ++ (val64); ++ if (mtu < max_pyld) ++ mtu = max_pyld; ++ } ++ ++ vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE; ++ ++ val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone); ++ ++ if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK) ++ VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP); ++ else ++ VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN); ++ ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_reset_check - Check if resetting the vpath completed ++ * This routine checks the vpath_rst_in_prog register to see if ++ * adapter completed the reset process for the vpath ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath) ++{ ++ enum vxge_hw_status status; ++ ++ status = __vxge_hw_device_register_poll( ++ &vpath->hldev->common_reg->vpath_rst_in_prog, ++ VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG( ++ 1 << (16 - vpath->vp_id)), ++ vpath->hldev->config.device_poll_millis); ++ ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_reset ++ * This routine resets the vpath on the device ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id) ++{ ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id)); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), ++ &hldev->common_reg->cmn_rsthdlr_cfg0); ++ ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_sw_reset ++ * This routine resets the vpath structures ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_sw_reset(struct __vxge_hw_device *hldev, u32 vp_id) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct __vxge_hw_virtualpath *vpath; ++ ++ vpath = (struct __vxge_hw_virtualpath *)&hldev->virtual_paths[vp_id]; ++ ++ if (vpath->ringh) { ++ status = __vxge_hw_ring_reset(vpath->ringh); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ } ++ ++ if (vpath->fifoh) ++ status = __vxge_hw_fifo_reset(vpath->fifoh); ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_prc_configure ++ * This routine configures the prc registers of virtual path using the config ++ * passed ++ */ ++void ++__vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev, u32 vp_id) ++{ ++ u64 val64; ++ struct __vxge_hw_virtualpath *vpath; ++ struct vxge_hw_vp_config *vp_config; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ ++ vpath = &hldev->virtual_paths[vp_id]; ++ vp_reg = vpath->vp_reg; ++ vp_config = vpath->vp_config; ++ ++ if (vp_config->ring.enable == VXGE_HW_RING_DISABLE) ++ return; ++ ++ val64 = readq(&vp_reg->prc_cfg1); ++ val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE; ++ writeq(val64, &vp_reg->prc_cfg1); ++ if (vp_config->ring.doorbell_mode == VXGE_HW_DOORBELL_MODE_ENABLE) { ++ val64 = readq(&vpath->vp_reg->prc_cfg6); ++ val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN; ++ writeq(val64, &vpath->vp_reg->prc_cfg6); ++ } ++ val64 = readq(&vp_reg->prc_cfg7); ++ ++ if (vpath->vp_config->ring.scatter_mode != ++ VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT) { ++ ++ val64 &= ~VXGE_HW_PRC_CFG7_SCATTER_MODE(0x3); ++ ++ switch (vpath->vp_config->ring.scatter_mode) { ++ case VXGE_HW_RING_SCATTER_MODE_A: ++ val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE( ++ VXGE_HW_PRC_CFG7_SCATTER_MODE_A); ++ break; ++ case VXGE_HW_RING_SCATTER_MODE_B: ++ val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE( ++ VXGE_HW_PRC_CFG7_SCATTER_MODE_B); ++ break; ++ case VXGE_HW_RING_SCATTER_MODE_C: ++ val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE( ++ VXGE_HW_PRC_CFG7_SCATTER_MODE_C); ++ break; ++ } ++ } ++ ++ writeq(val64, &vp_reg->prc_cfg7); ++ ++ writeq(VXGE_HW_PRC_CFG5_RXD0_ADD( ++ __vxge_hw_ring_first_block_address_get( ++ vpath->ringh) >> 3), &vp_reg->prc_cfg5); ++ ++ val64 = readq(&vp_reg->prc_cfg4); ++ val64 |= VXGE_HW_PRC_CFG4_IN_SVC; ++ val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3); ++ ++ val64 |= VXGE_HW_PRC_CFG4_RING_MODE( ++ VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER); ++ ++ if (hldev->config.rth_en == VXGE_HW_RTH_DISABLE) ++ val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE; ++ else ++ val64 &= ~VXGE_HW_PRC_CFG4_RTH_DISABLE; ++ ++ writeq(val64, &vp_reg->prc_cfg4); ++ return; ++} ++ ++/* ++ * __vxge_hw_vpath_kdfc_configure ++ * This routine configures the kdfc registers of virtual path using the ++ * config passed ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id) ++{ ++ u64 val64; ++ u64 vpath_stride; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct __vxge_hw_virtualpath *vpath; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ ++ vpath = &hldev->virtual_paths[vp_id]; ++ vp_reg = vpath->vp_reg; ++ status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = readq(&vp_reg->kdfc_drbl_triplet_total); ++ ++ vpath->max_kdfc_db = ++ (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE( ++ val64+1)/2; ++ ++ if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) { ++ ++ vpath->max_nofl_db = vpath->max_kdfc_db; ++ ++ if (vpath->max_nofl_db < ++ ((vpath->vp_config->fifo.memblock_size / ++ (vpath->vp_config->fifo.max_frags * ++ sizeof(struct vxge_hw_fifo_txd))) * ++ vpath->vp_config->fifo.fifo_blocks)) { ++ ++ return VXGE_HW_BADCFG_FIFO_BLOCKS; ++ } ++ val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0( ++ (vpath->max_nofl_db*2)-1); ++ } ++ ++ writeq(val64, &vp_reg->kdfc_fifo_trpl_partition); ++ ++ writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE, ++ &vp_reg->kdfc_fifo_trpl_ctrl); ++ ++ val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl); ++ ++ val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) | ++ VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF)); ++ ++ val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE( ++ VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) | ++#ifndef __BIG_ENDIAN ++ VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN | ++#endif ++ VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0); ++ ++ writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl); ++ writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address); ++ wmb(); ++ vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride); ++ ++ vpath->nofl_db = ++ (struct __vxge_hw_non_offload_db_wrapper __iomem *) ++ (hldev->kdfc + (vp_id * ++ VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE( ++ vpath_stride))); ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_mac_configure ++ * This routine configures the mac of virtual path using the config passed ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev, u32 vp_id) ++{ ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct __vxge_hw_virtualpath *vpath; ++ struct vxge_hw_vp_config *vp_config; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ ++ vpath = &hldev->virtual_paths[vp_id]; ++ vp_reg = vpath->vp_reg; ++ vp_config = vpath->vp_config; ++ ++ writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER( ++ vpath->vsport_number), &vp_reg->xmac_vsport_choice); ++ ++ if (vp_config->ring.enable == VXGE_HW_RING_ENABLE) { ++ ++ val64 = readq(&vp_reg->xmac_rpa_vcfg); ++ ++ if (vp_config->rpa_strip_vlan_tag != ++ VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) { ++ if (vp_config->rpa_strip_vlan_tag) ++ val64 |= VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG; ++ else ++ val64 &= ~VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG; ++ } ++ ++ writeq(val64, &vp_reg->xmac_rpa_vcfg); ++ val64 = readq(&vp_reg->rxmac_vcfg0); ++ ++ if (vp_config->mtu != ++ VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) { ++ val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff); ++ if ((vp_config->mtu + ++ VXGE_HW_MAC_HEADER_MAX_SIZE) < vpath->max_mtu) ++ val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN( ++ vp_config->mtu + ++ VXGE_HW_MAC_HEADER_MAX_SIZE); ++ else ++ val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN( ++ vpath->max_mtu); ++ } ++ ++ writeq(val64, &vp_reg->rxmac_vcfg0); ++ ++ val64 = readq(&vp_reg->rxmac_vcfg1); ++ ++ val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) | ++ VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE); ++ ++ if (hldev->config.rth_it_type == ++ VXGE_HW_RTH_IT_TYPE_MULTI_IT) { ++ val64 |= VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE( ++ 0x2) | ++ VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE; ++ } ++ ++ writeq(val64, &vp_reg->rxmac_vcfg1); ++ } ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_tim_configure ++ * This routine configures the tim registers of virtual path using the config ++ * passed ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id) ++{ ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct __vxge_hw_virtualpath *vpath; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ struct vxge_hw_vp_config *config; ++ ++ vpath = &hldev->virtual_paths[vp_id]; ++ vp_reg = vpath->vp_reg; ++ config = vpath->vp_config; ++ ++ writeq((u64)0, &vp_reg->tim_dest_addr); ++ writeq((u64)0, &vp_reg->tim_vpath_map); ++ writeq((u64)0, &vp_reg->tim_bitmap); ++ writeq((u64)0, &vp_reg->tim_remap); ++ ++ if (config->ring.enable == VXGE_HW_RING_ENABLE) ++ writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM( ++ (vp_id * VXGE_HW_MAX_INTR_PER_VP) + ++ VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn); ++ ++ val64 = readq(&vp_reg->tim_pci_cfg); ++ val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD; ++ writeq(val64, &vp_reg->tim_pci_cfg); ++ ++ if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) { ++ ++ val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); ++ ++ if (config->tti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL( ++ 0x3ffffff); ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL( ++ config->tti.btimer_val); ++ } ++ ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN; ++ ++ if (config->tti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) { ++ if (config->tti.timer_ac_en) ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC; ++ else ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC; ++ } ++ ++ if (config->tti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) { ++ if (config->tti.timer_ci_en) ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; ++ else ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; ++ } ++ ++ if (config->tti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f); ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A( ++ config->tti.urange_a); ++ } ++ ++ if (config->tti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f); ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B( ++ config->tti.urange_b); ++ } ++ ++ if (config->tti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f); ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C( ++ config->tti.urange_c); ++ } ++ ++ writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); ++ val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]); ++ ++ if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff); ++ val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A( ++ config->tti.uec_a); ++ } ++ ++ if (config->tti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff); ++ val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B( ++ config->tti.uec_b); ++ } ++ ++ if (config->tti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff); ++ val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C( ++ config->tti.uec_c); ++ } ++ ++ if (config->tti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff); ++ val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D( ++ config->tti.uec_d); ++ } ++ ++ writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]); ++ val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]); ++ ++ if (config->tti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) { ++ if (config->tti.timer_ri_en) ++ val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI; ++ else ++ val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI; ++ } ++ ++ if (config->tti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL( ++ 0x3ffffff); ++ val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL( ++ config->tti.rtimer_val); ++ } ++ ++ if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f); ++ val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL( ++ config->tti.util_sel); ++ } ++ ++ if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL( ++ 0x3ffffff); ++ val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL( ++ config->tti.ltimer_val); ++ } ++ ++ writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]); ++ } ++ ++ if (config->ring.enable == VXGE_HW_RING_ENABLE) { ++ ++ val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]); ++ ++ if (config->rti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL( ++ 0x3ffffff); ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL( ++ config->rti.btimer_val); ++ } ++ ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN; ++ ++ if (config->rti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) { ++ if (config->rti.timer_ac_en) ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC; ++ else ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC; ++ } ++ ++ if (config->rti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) { ++ if (config->rti.timer_ci_en) ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; ++ else ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; ++ } ++ ++ if (config->rti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f); ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A( ++ config->rti.urange_a); ++ } ++ ++ if (config->rti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f); ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B( ++ config->rti.urange_b); ++ } ++ ++ if (config->rti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f); ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C( ++ config->rti.urange_c); ++ } ++ ++ writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]); ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL( ++ 0x3ffffff); ++ vpath->tim_rti_cfg1_saved = val64; ++ ++ val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]); ++ ++ if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff); ++ val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A( ++ config->rti.uec_a); ++ } ++ ++ if (config->rti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff); ++ val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B( ++ config->rti.uec_b); ++ } ++ ++ if (config->rti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff); ++ val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C( ++ config->rti.uec_c); ++ } ++ ++ if (config->rti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff); ++ val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D( ++ config->rti.uec_d); ++ } ++ ++ writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]); ++ val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]); ++ ++ if (config->rti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) { ++ if (config->rti.timer_ri_en) ++ val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI; ++ else ++ val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI; ++ } ++ ++ if (config->rti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL( ++ 0x3ffffff); ++ val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL( ++ config->rti.rtimer_val); ++ } ++ ++ if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f); ++ val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL( ++ config->rti.util_sel); ++ } ++ ++ if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) { ++ val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL( ++ 0x3ffffff); ++ val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL( ++ config->rti.ltimer_val); ++ } ++ ++ writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]); ++ vpath->tim_rti_cfg3_saved = val64; ++ } ++ ++ val64 = 0; ++ ++ writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]); ++ ++ writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]); ++ writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]); ++ writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]); ++ writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]); ++ writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]); ++ ++ return status; ++} ++ ++void ++vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id) ++{ ++ struct __vxge_hw_virtualpath *vpath; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ struct vxge_hw_vp_config *config; ++ u64 val64; ++ ++ vpath = &hldev->virtual_paths[vp_id]; ++ vp_reg = vpath->vp_reg; ++ config = vpath->vp_config; ++ ++ if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) { ++ val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); ++ ++ if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) { ++ config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE; ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; ++ writeq(val64, ++ &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); ++ } ++ } ++ return; ++} ++ ++/* ++ * __vxge_hw_vpath_initialize ++ * This routine is the final phase of init which initializes the ++ * registers of the vpath using the configuration passed. ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id) ++{ ++ u64 val64; ++ u32 val32; ++ int i; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct __vxge_hw_virtualpath *vpath; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ ++ vpath = &hldev->virtual_paths[vp_id]; ++ ++ if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) { ++ status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE; ++ goto exit; ++ } ++ vp_reg = vpath->vp_reg; ++ status = __vxge_hw_legacy_swapper_set(hldev->legacy_reg); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ status = __vxge_hw_vpath_swapper_set(vpath->vp_reg); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp); ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ if (val64 & vxge_mBIT(i)) ++ vpath->vsport_number = i; ++ } ++ ++ status = __vxge_hw_vpath_mac_configure(hldev, vp_id); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ status = __vxge_hw_vpath_kdfc_configure(hldev, vp_id); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ status = __vxge_hw_vpath_tim_configure(hldev, vp_id); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl); ++ ++ /* Get MRRS value from device control */ ++ status = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32); ++ ++ if (status == VXGE_HW_OK) { ++ val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12; ++ val64 &= ++ ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7)); ++ val64 |= ++ VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32); ++ ++ val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE; ++ } ++ ++ val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7)); ++ val64 |= ++ VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY( ++ VXGE_HW_MAX_PAYLOAD_SIZE_512); ++ ++ val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN; ++ writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl); ++ ++ /* rx bandwidth limit configuration */ ++ /* This would not work in the current scenario TODO ++ * __vxge_hw_set_bw_limit takes the privilege vpath. ++ * Here we pass the vpath that we receive which could be ++ * a non privilege vpath also ++ */ ++ if (vpath->vp_config->rx_bw_limit ++ != VXGE_HW_VPATH_RX_BANDWIDTH_LIMIT_DEFAULT) { ++ __vxge_hw_set_bw_limit(vpath, vp_id, ++ vpath->vp_config->rx_bw_limit); ++ } ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_vp_initialize - Initialize Virtual Path structure ++ * This routine is the initial phase of init which resets the vpath and ++ * initializes the software support structures. ++ */ ++enum vxge_hw_status ++__vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id, ++ struct vxge_hw_vp_config *config) ++{ ++ struct __vxge_hw_virtualpath *vpath; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) { ++ status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE; ++ goto exit; ++ } ++ ++ vpath = &hldev->virtual_paths[vp_id]; ++ ++ vpath->vp_id = vp_id; ++ vpath->vp_open = VXGE_HW_VP_OPEN; ++ vpath->hldev = hldev; ++ vpath->vp_config = config; ++ vpath->vp_reg = hldev->vpath_reg[vp_id]; ++ vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id]; ++ ++ __vxge_hw_vpath_reset(hldev, vp_id); ++ ++ status = __vxge_hw_vpath_reset_check(vpath); ++ ++ if (status != VXGE_HW_OK) { ++ memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath)); ++ goto exit; ++ } ++ ++ INIT_LIST_HEAD(&vpath->vpath_handles); ++ ++ vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id]; ++ ++ VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0, ++ hldev->tim_int_mask1, vp_id); ++ ++ status = __vxge_hw_vpath_initialize(hldev, vp_id); ++ ++ if (status != VXGE_HW_OK) ++ __vxge_hw_vp_terminate(hldev, vp_id); ++ ++ status = __vxge_hw_vpath_mgmt_read(hldev, vpath); ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_vp_terminate - Terminate Virtual Path structure ++ * This routine closes all channels it opened and freeup memory ++ */ ++void ++__vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id) ++{ ++ struct __vxge_hw_virtualpath *vpath; ++ ++ vpath = &hldev->virtual_paths[vp_id]; ++ ++ if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) ++ goto exit; ++ ++ VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0, ++ vpath->hldev->tim_int_mask1, vpath->vp_id); ++ hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL; ++ ++ memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath)); ++exit: ++ return; ++} ++ ++ ++/** ++ * vxge_hw_vpath_bandwidth_set - Set the bandwidth for a vpath. ++ * @hldev: HW device handle. ++ * @vp_id: Vpath Id. ++ * __vxge_hw_channel_type type: Bandwidth for Tx or Rx channel ++ * @bandwidth: Assigned Bandwidth in Mbps ++ * ++ * Set the bandwidth for a given vpath ++ * ++ */ ++enum vxge_hw_status vxge_hw_vpath_bandwidth_set( ++ struct __vxge_hw_device *hldev, ++ u32 vp_id, enum __vxge_hw_channel_type type, ++ u32 bandwidth, u32 pkt_size) ++{ ++ u32 prev_bandwidth; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ u64 val64 = 0, bw_limit = 0; ++ struct __vxge_hw_virtualpath *vpath; ++ struct __vxge_hw_virtualpath *priv_vpath; ++ u32 priv_vpath_num = 0; /* Currently hardcoded to 0 in hw */ ++ ++ ++ if (vp_id >= VXGE_HW_MAX_VIRTUAL_PATHS) { ++ status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE; ++ goto exit; ++ } ++ ++ vpath = &hldev->virtual_paths[vp_id]; ++ priv_vpath = &hldev->virtual_paths[priv_vpath_num]; ++ ++ if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { ++ status = VXGE_HW_ERR_VPATH_NOT_OPEN; ++ goto exit; ++ } ++ ++ if (type == VXGE_HW_CHANNEL_TYPE_FIFO) { ++ ++ if ((bandwidth < VXGE_HW_VPATH_TX_BANDWIDTH_LIMIT_MIN) || ++ (bandwidth > VXGE_HW_VPATH_TX_BANDWIDTH_LIMIT_MAX)) { ++ status = VXGE_HW_ERR_INVALID_MIN_BANDWIDTH; ++ goto exit; ++ } ++ ++ if (bandwidth == VXGE_HW_VPATH_TX_BANDWIDTH_LIMIT_DEFAULT) ++ goto exit; ++ ++ vpath->vp_config->tx_bw_limit = bandwidth; ++ ++ /* tx_bw_limit is in Gbps, convert it to microseconds */ ++ bw_limit = (pkt_size / (bandwidth / 8)); ++ val64 = VXGE_HW_RTDMA_BW_CTRL_BW_CTRL_EN | ++ VXGE_HW_RTDMA_BW_CTRL_DESIRED_BW(bw_limit); ++ ++ writeq(val64, &vpath->vp_reg->rtdma_bw_ctrl); ++ } else { ++ ++ if ((bandwidth < VXGE_HW_VPATH_RX_BANDWIDTH_LIMIT_MIN) || ++ (bandwidth > VXGE_HW_VPATH_RX_BANDWIDTH_LIMIT_MAX)) { ++ status = VXGE_HW_ERR_INVALID_MIN_BANDWIDTH; ++ goto exit; ++ } ++ ++ if (bandwidth == VXGE_HW_VPATH_RX_BANDWIDTH_LIMIT_DEFAULT) ++ goto exit; ++ ++ prev_bandwidth = vpath->vp_config->rx_bw_limit; ++ if (prev_bandwidth != bandwidth) { ++ ++ vpath->vp_config->rx_bw_limit = bandwidth; ++ status = __vxge_hw_set_bw_limit(priv_vpath, vp_id, bandwidth); ++ } ++ ++ if (status != VXGE_HW_OK) ++ vpath->vp_config->rx_bw_limit = prev_bandwidth; ++ } ++ ++exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_vpath_mtu_set - Set MTU. ++ * Set new MTU value. Example, to use jumbo frames: ++ * vxge_hw_vpath_mtu_set(my_device, 9600); ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle *vp, u32 new_mtu) ++{ ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct __vxge_hw_virtualpath *vpath; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ vpath = vp->vpath; ++ ++ new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE; ++ ++ if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu)) ++ status = VXGE_HW_ERR_INVALID_MTU_SIZE; ++ ++ val64 = readq(&vpath->vp_reg->rxmac_vcfg0); ++ ++ val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff); ++ val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu); ++ ++ writeq(val64, &vpath->vp_reg->rxmac_vcfg0); ++ ++ vpath->vp_config->mtu = new_mtu - VXGE_HW_MAC_HEADER_MAX_SIZE; ++ ++exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_vpath_open - Open a virtual path on a given adapter ++ * This function is used to open access to virtual path of an ++ * adapter for offload, GRO operations. This function returns ++ * synchronously. ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_open(struct __vxge_hw_device *hldev, ++ struct vxge_hw_vpath_attr *attr, ++ struct __vxge_hw_vpath_handle **vpath_handle) ++{ ++ struct __vxge_hw_virtualpath *vpath; ++ struct __vxge_hw_vpath_handle *vp; ++ enum vxge_hw_status status; ++ ++ vpath = &hldev->virtual_paths[attr->vp_id]; ++ ++ if (vpath->vp_open == VXGE_HW_VP_OPEN) { ++ status = VXGE_HW_ERR_INVALID_STATE; ++ goto vpath_open_exit1; ++ } ++ ++ status = __vxge_hw_vp_initialize(hldev, attr->vp_id, ++ &hldev->config.vp_config[attr->vp_id]); ++ ++ if (status != VXGE_HW_OK) ++ goto vpath_open_exit1; ++ ++ vp = (struct __vxge_hw_vpath_handle *) ++ vmalloc(sizeof(struct __vxge_hw_vpath_handle)); ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto vpath_open_exit2; ++ } ++ ++ memset(vp, 0, sizeof(struct __vxge_hw_vpath_handle)); ++ ++ vp->vpath = vpath; ++ ++ if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) { ++ status = __vxge_hw_fifo_create(vp, &attr->fifo_attr); ++ if (status != VXGE_HW_OK) ++ goto vpath_open_exit6; ++ } ++ ++ if (vpath->vp_config->ring.enable == VXGE_HW_RING_ENABLE) { ++ status = __vxge_hw_ring_create(vp, &attr->ring_attr); ++ if (status != VXGE_HW_OK) ++ goto vpath_open_exit7; ++ ++ __vxge_hw_vpath_prc_configure(hldev, attr->vp_id); ++ } ++ ++ vpath->fifoh->tx_intr_num = ++ (attr->vp_id * VXGE_HW_MAX_INTR_PER_VP) + ++ VXGE_HW_VPATH_INTR_TX; ++ ++ vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev, ++ VXGE_HW_BLOCK_SIZE); ++ ++ if (vpath->stats_block == NULL) { ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto vpath_open_exit8; ++ } ++ ++ vpath->hw_stats = (struct vxge_hw_vpath_stats_hw_info *)vpath-> ++ stats_block->memblock; ++ memset(vpath->hw_stats, 0, ++ sizeof(struct vxge_hw_vpath_stats_hw_info)); ++ ++ hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] = ++ vpath->hw_stats; ++ ++ vpath->hw_stats_sav = ++ &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id]; ++ memset(vpath->hw_stats_sav, 0, ++ sizeof(struct vxge_hw_vpath_stats_hw_info)); ++ ++ writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg); ++ ++ status = vxge_hw_vpath_stats_enable(vp); ++ if (status != VXGE_HW_OK) ++ goto vpath_open_exit8; ++ ++ list_add(&vp->item, &vpath->vpath_handles); ++ ++ hldev->vpaths_deployed |= vxge_mBIT(vpath->vp_id); ++ ++ *vpath_handle = vp; ++ ++ attr->fifo_attr.userdata = vpath->fifoh; ++ attr->ring_attr.userdata = vpath->ringh; ++ ++ return VXGE_HW_OK; ++ ++vpath_open_exit8: ++ if (vpath->ringh != NULL) ++ __vxge_hw_ring_delete(vp); ++vpath_open_exit7: ++ if (vpath->fifoh != NULL) ++ __vxge_hw_fifo_delete(vp); ++vpath_open_exit6: ++ vfree(vp); ++vpath_open_exit2: ++ __vxge_hw_vp_terminate(hldev, attr->vp_id); ++vpath_open_exit1: ++ ++ return status; ++} ++ ++/* ++ * vxge_hw_vpath_rx_doorbell_init - Post the count of the refreshed region ++ * of RxD list ++ * @vp: vpath handle ++ * ++ * This function decides on the Rxd replenish count depending on the ++ * descriptor memory that has been allocated to this VPath. ++ */ ++void ++vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp) ++{ ++ struct __vxge_hw_virtualpath *vpath = NULL; ++ u64 new_count, val64; ++ struct __vxge_hw_ring *ring; ++ ++ vpath = vp->vpath; ++ ring = vpath->ringh; ++ ++ if (vpath->hldev->titan1) { ++ new_count = readq(&vpath->vp_reg->rxdmem_size); ++ new_count &= 0x1fff; ++ } else ++ new_count = ring->config->ring_blocks * VXGE_HW_BLOCK_SIZE / 8; ++ ++ val64 = (VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count)); ++ ++ writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val64), ++ &vpath->vp_reg->prc_rxd_doorbell); ++ readl(&vpath->vp_reg->prc_rxd_doorbell); ++} ++ ++/* ++ * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open ++ * This function is used to close access to virtual path opened ++ * earlier. ++ */ ++enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp) ++{ ++ struct __vxge_hw_virtualpath *vpath = NULL; ++ struct __vxge_hw_device *devh = NULL; ++ u32 vp_id = vp->vpath->vp_id; ++ u32 is_empty = TRUE; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ vpath = vp->vpath; ++ devh = vpath->hldev; ++ ++ if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { ++ status = VXGE_HW_ERR_VPATH_NOT_OPEN; ++ goto vpath_close_exit; ++ } ++ ++ list_del(&vp->item); ++ ++ if (!list_empty(&vpath->vpath_handles)) { ++ list_add(&vp->item, &vpath->vpath_handles); ++ is_empty = FALSE; ++ } ++ ++ if (!is_empty) { ++ status = VXGE_HW_FAIL; ++ goto vpath_close_exit; ++ } ++ ++ devh->vpaths_deployed &= ~vxge_mBIT(vp_id); ++ ++ if (vpath->ringh != NULL) ++ __vxge_hw_ring_delete(vp); ++ ++ if (vpath->fifoh != NULL) ++ __vxge_hw_fifo_delete(vp); ++ ++ if (vpath->stats_block != NULL) ++ __vxge_hw_blockpool_block_free(devh, vpath->stats_block); ++ ++ vfree(vp); ++ ++ __vxge_hw_vp_terminate(devh, vp_id); ++ ++ vpath->vp_open = VXGE_HW_VP_NOT_OPEN; ++ ++vpath_close_exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_vpath_reset - Resets vpath ++ * This function is used to request a reset of vpath ++ */ ++enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle *vp) ++{ ++ enum vxge_hw_status status; ++ u32 vp_id; ++ struct __vxge_hw_virtualpath *vpath = vp->vpath; ++ ++ vp_id = vpath->vp_id; ++ ++ if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { ++ status = VXGE_HW_ERR_VPATH_NOT_OPEN; ++ goto exit; ++ } ++ ++ status = __vxge_hw_vpath_reset(vpath->hldev, vp_id); ++ if (status == VXGE_HW_OK) ++ vpath->sw_stats->soft_reset_cnt++; ++exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_vpath_recover_from_reset - Poll for reset complete and re-initialize. ++ * This function poll's for the vpath reset completion and re initializes ++ * the vpath. ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle *vp) ++{ ++ struct __vxge_hw_virtualpath *vpath = NULL; ++ enum vxge_hw_status status; ++ struct __vxge_hw_device *hldev; ++ u32 vp_id; ++ ++ vp_id = vp->vpath->vp_id; ++ vpath = vp->vpath; ++ hldev = vpath->hldev; ++ ++ if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { ++ status = VXGE_HW_ERR_VPATH_NOT_OPEN; ++ goto exit; ++ } ++ ++ status = __vxge_hw_vpath_reset_check(vpath); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ status = __vxge_hw_vpath_sw_reset(hldev, vp_id); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ status = __vxge_hw_vpath_initialize(hldev, vp_id); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ if (vpath->ringh != NULL) ++ __vxge_hw_vpath_prc_configure(hldev, vp_id); ++ ++ memset(vpath->hw_stats, 0, ++ sizeof(struct vxge_hw_vpath_stats_hw_info)); ++ ++ memset(vpath->hw_stats_sav, 0, ++ sizeof(struct vxge_hw_vpath_stats_hw_info)); ++ ++ writeq(vpath->stats_block->dma_addr, ++ &vpath->vp_reg->stats_cfg); ++ ++ status = vxge_hw_vpath_stats_enable(vp); ++ ++exit: ++ return status; ++} ++ ++/* ++ * vxge_hw_vpath_enable - Enable vpath. ++ * This routine clears the vpath reset thereby enabling a vpath ++ * to start forwarding frames and generating interrupts. ++ */ ++void ++vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp) ++{ ++ struct __vxge_hw_device *hldev; ++ u64 val64; ++ ++ hldev = vp->vpath->hldev; ++ ++ /* Increment the VPATH instance number before brining the vpath ++ into service */ ++ val64 = VXGE_HW_CMN_RSTHDLR_CFG8_INCR_VPATH_INST_NUM( ++ 1 << (16 - vp->vpath->vp_id)); ++ __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), ++ &hldev->common_reg->cmn_rsthdlr_cfg8); ++ ++ val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET( ++ 1 << (16 - vp->vpath->vp_id)); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), ++ &hldev->common_reg->cmn_rsthdlr_cfg1); ++} ++ ++/* ++ * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics. ++ * Enable the DMA vpath statistics. The function is to be called to re-enable ++ * the adapter to update stats into the host memory ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp) ++{ ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct __vxge_hw_virtualpath *vpath; ++ ++ vpath = vp->vpath; ++ ++ if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { ++ status = VXGE_HW_ERR_VPATH_NOT_OPEN; ++ goto exit; ++ } ++ ++ memcpy(vpath->hw_stats_sav, vpath->hw_stats, ++ sizeof(struct vxge_hw_vpath_stats_hw_info)); ++ if (vpath->hldev->config.stats_read_method == ++ VXGE_HW_STATS_READ_METHOD_DMA) { ++ val64 = readq(&vpath->hldev->common_reg->stats_cfg0); ++ val64 |= VXGE_HW_STATS_CFG0_STATS_ENABLE( ++ (1 << (16 - vpath->vp_id))); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), ++ &vpath->hldev->common_reg->stats_cfg0); ++ } else ++ status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats); ++ ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_stats_access - Get the statistics from the given location ++ * and offset and perform an operation ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath, ++ u32 operation, u32 offset, u64 *stat) ++{ ++ u64 val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ ++ if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { ++ status = VXGE_HW_ERR_VPATH_NOT_OPEN; ++ goto vpath_stats_access_exit; ++ } ++ ++ vp_reg = vpath->vp_reg; ++ ++ val64 = VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) | ++ VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE | ++ VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset); ++ ++ status = __vxge_hw_pio_mem_write64(val64, ++ &vp_reg->xmac_stats_access_cmd, ++ VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE, ++ vpath->hldev->config.device_poll_millis); ++ ++ if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ)) ++ *stat = readq(&vp_reg->xmac_stats_access_data); ++ else ++ *stat = 0; ++ ++vpath_stats_access_exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_xmac_tx_stats_get( ++ struct __vxge_hw_virtualpath *vpath, ++ struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats) ++{ ++ u64 *val64; ++ int i; ++ u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ val64 = (u64 *) vpath_tx_stats; ++ ++ if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { ++ status = VXGE_HW_ERR_VPATH_NOT_OPEN; ++ goto exit; ++ } ++ ++ for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) { ++ status = __vxge_hw_vpath_stats_access(vpath, ++ VXGE_HW_STATS_OP_READ, ++ offset, val64); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ offset++; ++ val64++; ++ } ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath ++ */ ++enum vxge_hw_status ++__vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath, ++ struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats) ++{ ++ u64 *val64; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ int i; ++ u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET; ++ val64 = (u64 *) vpath_rx_stats; ++ ++ if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { ++ status = VXGE_HW_ERR_VPATH_NOT_OPEN; ++ goto exit; ++ } ++ for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) { ++ status = __vxge_hw_vpath_stats_access(vpath, ++ VXGE_HW_STATS_OP_READ, ++ offset >> 3, val64); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ offset += 8; ++ val64++; ++ } ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_stats_get - Get the vpath hw statistics. ++ */ ++enum vxge_hw_status __vxge_hw_vpath_stats_get( ++ struct __vxge_hw_virtualpath *vpath, ++ struct vxge_hw_vpath_stats_hw_info *hw_stats) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ ++ if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { ++ status = VXGE_HW_ERR_VPATH_NOT_OPEN; ++ goto exit; ++ } ++ vp_reg = vpath->vp_reg; ++ ++ status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats); ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats); ++ if (status != VXGE_HW_OK) ++ goto exit; ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_blockpool_create - Create block pool ++ */ ++ ++enum vxge_hw_status ++__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev, ++ struct __vxge_hw_blockpool *blockpool, ++ u32 pool_size) ++{ ++ u32 i; ++ struct __vxge_hw_blockpool_entry *entry = NULL; ++ void *memblock; ++ dma_addr_t dma_addr; ++ struct pci_dev *dma_handle; ++ struct pci_dev *acc_handle; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (blockpool == NULL) { ++ status = VXGE_HW_FAIL; ++ goto blockpool_create_exit; ++ } ++ ++ blockpool->hldev = hldev; ++ blockpool->block_size = VXGE_HW_BLOCK_SIZE; ++ ++ INIT_LIST_HEAD(&blockpool->free_block_list); ++ INIT_LIST_HEAD(&blockpool->free_entry_list); ++ ++ for (i = 0; i < pool_size; i++) { ++ entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry), ++ GFP_KERNEL); ++ if (entry == NULL) { ++ __vxge_hw_blockpool_destroy(blockpool); ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto blockpool_create_exit; ++ } ++ list_add(&entry->item, &blockpool->free_entry_list); ++ } ++ ++ for (i = 0; i < pool_size; i++) { ++ ++ memblock = vxge_os_dma_malloc( ++ hldev->pdev, ++ VXGE_HW_BLOCK_SIZE, ++ &dma_handle, ++ &acc_handle); ++ ++ if (memblock == NULL) { ++ __vxge_hw_blockpool_destroy(blockpool); ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto blockpool_create_exit; ++ } ++ ++ dma_addr = vxge_dma_map(hldev->pdev, memblock, ++ VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL); ++ ++ if (unlikely(vxge_do_pci_dma_mapping_error(hldev->pdev, ++ dma_addr))) { ++ ++ vxge_os_dma_free(hldev->pdev, memblock, &acc_handle); ++ __vxge_hw_blockpool_destroy(blockpool); ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto blockpool_create_exit; ++ } ++ ++ if (!list_empty(&blockpool->free_entry_list)) ++ entry = (struct __vxge_hw_blockpool_entry *) ++ list_entry((&blockpool->free_entry_list)->next, ++ struct __vxge_hw_blockpool_entry, ++ item); ++ ++ if (entry == NULL) ++ entry = ++ kzalloc(sizeof(struct __vxge_hw_blockpool_entry), ++ GFP_KERNEL); ++ if (entry != NULL) { ++ list_del(&entry->item); ++ entry->length = VXGE_HW_BLOCK_SIZE; ++ entry->memblock = memblock; ++ entry->dma_addr = dma_addr; ++ entry->acc_handle = acc_handle; ++ entry->dma_handle = dma_handle; ++ list_add(&entry->item, ++ &blockpool->free_block_list); ++ } else { ++ __vxge_hw_blockpool_destroy(blockpool); ++ status = VXGE_HW_ERR_OUT_OF_MEMORY; ++ goto blockpool_create_exit; ++ } ++ } ++ ++blockpool_create_exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_blockpool_destroy - Deallocates the block pool ++ */ ++ ++void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool) ++{ ++ ++ struct __vxge_hw_device *hldev; ++ struct list_head *p, *n; ++ ++ if (blockpool == NULL) ++ goto exit; ++ ++ hldev = blockpool->hldev; ++ ++ list_for_each_safe(p, n, &blockpool->free_block_list) { ++ ++ vxge_dma_unmap(hldev->pdev, ++ ((struct __vxge_hw_blockpool_entry *)p)->dma_addr, ++ ((struct __vxge_hw_blockpool_entry *)p)->length, ++ PCI_DMA_BIDIRECTIONAL); ++ ++ vxge_os_dma_free(hldev->pdev, ++ ((struct __vxge_hw_blockpool_entry *)p)->memblock, ++ &((struct __vxge_hw_blockpool_entry *) p)->acc_handle); ++ ++ list_del( ++ &((struct __vxge_hw_blockpool_entry *)p)->item); ++ kfree(p); ++ } ++ ++ list_for_each_safe(p, n, &blockpool->free_entry_list) { ++ list_del( ++ &((struct __vxge_hw_blockpool_entry *)p)->item); ++ kfree((void *)p); ++ } ++exit: ++ return; ++} ++ ++/* ++ * __vxge_hw_blockpool_malloc - Allocate a memory block from pool ++ * Allocates a block of memory of given size, either from block pool ++ * or by calling vxge_os_dma_malloc() ++ */ ++void * ++__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, ++ struct vxge_hw_mempool_dma *dma_object) ++{ ++ struct __vxge_hw_blockpool_entry *entry = NULL; ++ struct __vxge_hw_blockpool *blockpool; ++ void *memblock = NULL; ++ ++ blockpool = &devh->block_pool; ++ ++ if (!list_empty(&blockpool->free_block_list)) ++ entry = (struct __vxge_hw_blockpool_entry *) ++ list_entry((&blockpool->free_block_list)->next, ++ struct __vxge_hw_blockpool_entry, ++ item); ++ if (entry != NULL) { ++ list_del(&entry->item); ++ dma_object->addr = entry->dma_addr; ++ dma_object->handle = entry->dma_handle; ++ dma_object->acc_handle = entry->acc_handle; ++ memblock = entry->memblock; ++ ++ list_add(&entry->item, ++ &blockpool->free_entry_list); ++ } ++ ++ return memblock; ++} ++ ++/* ++ * __vxge_hw_blockpool_free - Frees the memory allcoated with ++ __vxge_hw_blockpool_malloc ++ */ ++void ++__vxge_hw_blockpool_free(struct __vxge_hw_device *devh, ++ void *memblock, u32 size, ++ struct vxge_hw_mempool_dma *dma_object) ++{ ++ struct __vxge_hw_blockpool_entry *entry = NULL; ++ struct __vxge_hw_blockpool *blockpool; ++ ++ blockpool = &devh->block_pool; ++ ++ if (!list_empty(&blockpool->free_entry_list)) ++ entry = (struct __vxge_hw_blockpool_entry *) ++ list_entry((&blockpool->free_entry_list)->next, ++ struct __vxge_hw_blockpool_entry, ++ item); ++ ++ if (entry != NULL) { ++ list_del(&entry->item); ++ entry->length = size; ++ entry->memblock = memblock; ++ entry->dma_addr = dma_object->addr; ++ entry->acc_handle = dma_object->acc_handle; ++ entry->dma_handle = dma_object->handle; ++ list_add(&entry->item, ++ &blockpool->free_block_list); ++ } ++ ++ return; ++} ++ ++/* ++ * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool ++ * This function allocates a block from block pool or from the system ++ */ ++struct __vxge_hw_blockpool_entry * ++__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size) ++{ ++ struct __vxge_hw_blockpool_entry *entry = NULL; ++ struct __vxge_hw_blockpool *blockpool; ++ ++ blockpool = &devh->block_pool; ++ ++ if (size == blockpool->block_size) { ++ ++ if (!list_empty(&blockpool->free_block_list)) ++ entry = (struct __vxge_hw_blockpool_entry *) ++ list_entry((&blockpool->free_block_list)->next, ++ struct __vxge_hw_blockpool_entry, ++ item); ++ ++ if (entry != NULL) ++ list_del(&entry->item); ++ } ++ ++ return entry; ++} ++ ++/* ++ * __vxge_hw_blockpool_block_free - Frees a block from block pool ++ * @devh: Hal device ++ * @entry: Entry of block to be freed ++ * ++ * This function frees a block from block pool ++ */ ++void ++__vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh, ++ struct __vxge_hw_blockpool_entry *entry) ++{ ++ struct __vxge_hw_blockpool *blockpool; ++ ++ blockpool = &devh->block_pool; ++ ++ list_add(&entry->item, &blockpool->free_block_list); ++ ++ return; ++} +diff -r 158b6e53275e drivers/net/vxge/vxge-config.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/vxge/vxge-config.h Wed Aug 05 11:58:00 2009 +0100 +@@ -0,0 +1,2340 @@ ++/****************************************************************************** ++ * vxge-config.h: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O ++ * Virtualized Server Adapter. ++ * Copyright(c) 2002-2009 Neterion Inc. ++ ******************************************************************************/ ++#ifndef VXGE_CONFIG_H ++#define VXGE_CONFIG_H ++#include ++#include "vxge-kcompat.h" ++ ++#ifndef VXGE_CACHE_LINE_SIZE ++#define VXGE_CACHE_LINE_SIZE 128 ++#endif ++ ++#define vxge_os_vaprintf(level, mask, fmt, ...) { \ ++ char buff[255]; \ ++ snprintf(buff, 255, fmt, __VA_ARGS__); \ ++ printk(buff); \ ++ printk("\n"); \ ++} ++ ++#ifdef VXGE_HW_TITAN_EMULATION ++#define WAIT_FACTOR 10 ++#else ++#define WAIT_FACTOR 1 ++#endif ++ ++#ifndef VXGE_ALIGN ++#define VXGE_ALIGN(adrs, size) \ ++ (((size) - (((unsigned long)adrs) & ((size)-1))) & ((size)-1)) ++#endif ++ ++ ++ ++#define VXGE_HW_MIN_MTU 68 ++#define VXGE_HW_MAX_MTU 9600 ++#define VXGE_HW_DEFAULT_MTU 1500 ++ ++#ifdef VXGE_DEBUG_ASSERT ++ ++/** ++ * vxge_assert ++ * @test: C-condition to check ++ * @fmt: printf like format string ++ * ++ * This function implements traditional assert. By default assertions ++ * are enabled. It can be disabled by undefining VXGE_DEBUG_ASSERT macro in ++ * compilation ++ * time. ++ */ ++#define vxge_assert(test) { \ ++ if (!(test)) \ ++ vxge_os_bug("bad cond: "#test" at %s:%d\n", \ ++ __FILE__, __LINE__); } ++#else ++#define vxge_assert(test) ++#endif /* end of VXGE_DEBUG_ASSERT */ ++ ++/** ++ * enum enum vxge_debug_level ++ * @VXGE_NONE: debug disabled ++ * @VXGE_ERR: all errors going to be logged out ++ * @VXGE_TRACE: all errors plus all kind of verbose tracing print outs ++ * going to be logged out. Very noisy. ++ * ++ * This enumeration going to be used to switch between different ++ * debug levels during runtime if DEBUG macro defined during ++ * compilation. If DEBUG macro not defined than code will be ++ * compiled out. ++ */ ++enum vxge_debug_level { ++ VXGE_NONE = 0, ++ VXGE_TRACE = 1, ++ VXGE_ERR = 2 ++}; ++ ++#define NULL_VPID 0xFFFFFFFF ++#ifdef CONFIG_VXGE_DEBUG_TRACE_ALL ++#define VXGE_DEBUG_MODULE_MASK 0xffffffff ++#define VXGE_DEBUG_TRACE_MASK 0xffffffff ++#define VXGE_DEBUG_ERR_MASK 0xffffffff ++#define VXGE_DEBUG_MASK 0x000001ff ++#else ++#define VXGE_DEBUG_MODULE_MASK 0x20000000 ++#define VXGE_DEBUG_TRACE_MASK 0x20000000 ++#define VXGE_DEBUG_ERR_MASK 0x20000000 ++#define VXGE_DEBUG_MASK 0x00000001 ++#endif ++ ++/* ++ * @VXGE_COMPONENT_LL: do debug for vxge link layer module ++ * @VXGE_COMPONENT_ALL: activate debug for all modules with no exceptions ++ * ++ * This enumeration going to be used to distinguish modules ++ * or libraries during compilation and runtime. Makefile must declare ++ * VXGE_DEBUG_MODULE_MASK macro and set it to proper value. ++ */ ++#define VXGE_COMPONENT_LL 0x20000000 ++#define VXGE_COMPONENT_ALL 0xffffffff ++ ++#define VXGE_HW_EVENT_BASE 0 ++#define VXGE_LL_EVENT_BASE 100 ++ ++#define VXGE_HW_BASE_INF 100 ++#define VXGE_HW_BASE_ERR 200 ++#define VXGE_HW_BASE_BADCFG 300 ++ ++enum vxge_hw_status { ++ VXGE_HW_OK = 0, ++ VXGE_HW_FAIL = 1, ++ VXGE_HW_PENDING = 2, ++ VXGE_HW_COMPLETIONS_REMAIN = 3, ++ ++ VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS = VXGE_HW_BASE_INF + 1, ++ VXGE_HW_INF_OUT_OF_DESCRIPTORS = VXGE_HW_BASE_INF + 2, ++ VXGE_HW_INF_SW_LRO_BEGIN = VXGE_HW_BASE_INF + 3, ++ VXGE_HW_INF_SW_LRO_CONT = VXGE_HW_BASE_INF + 4, ++ VXGE_HW_INF_SW_LRO_UNCAPABLE = VXGE_HW_BASE_INF + 5, ++ VXGE_HW_INF_SW_LRO_FLUSH_SESSION = VXGE_HW_BASE_INF + 6, ++ VXGE_HW_INF_SW_LRO_FLUSH_BOTH = VXGE_HW_BASE_INF + 7, ++ ++ VXGE_HW_ERR_INVALID_HANDLE = VXGE_HW_BASE_ERR + 1, ++ VXGE_HW_ERR_OUT_OF_MEMORY = VXGE_HW_BASE_ERR + 2, ++ VXGE_HW_ERR_VPATH_NOT_AVAILABLE = VXGE_HW_BASE_ERR + 3, ++ VXGE_HW_ERR_VPATH_NOT_OPEN = VXGE_HW_BASE_ERR + 4, ++ VXGE_HW_ERR_WRONG_IRQ = VXGE_HW_BASE_ERR + 5, ++ VXGE_HW_ERR_SWAPPER_CTRL = VXGE_HW_BASE_ERR + 6, ++ VXGE_HW_ERR_INVALID_MTU_SIZE = VXGE_HW_BASE_ERR + 7, ++ VXGE_HW_ERR_INVALID_INDEX = VXGE_HW_BASE_ERR + 8, ++ VXGE_HW_ERR_INVALID_TYPE = VXGE_HW_BASE_ERR + 9, ++ VXGE_HW_ERR_INVALID_OFFSET = VXGE_HW_BASE_ERR + 10, ++ VXGE_HW_ERR_INVALID_DEVICE = VXGE_HW_BASE_ERR + 11, ++ VXGE_HW_ERR_VERSION_CONFLICT = VXGE_HW_BASE_ERR + 12, ++ VXGE_HW_ERR_INVALID_PCI_INFO = VXGE_HW_BASE_ERR + 13, ++ VXGE_HW_ERR_INVALID_TCODE = VXGE_HW_BASE_ERR + 14, ++ VXGE_HW_ERR_INVALID_BLOCK_SIZE = VXGE_HW_BASE_ERR + 15, ++ VXGE_HW_ERR_INVALID_STATE = VXGE_HW_BASE_ERR + 16, ++ VXGE_HW_ERR_PRIVILAGED_OPEARATION = VXGE_HW_BASE_ERR + 17, ++ VXGE_HW_ERR_INVALID_PORT = VXGE_HW_BASE_ERR + 18, ++ VXGE_HW_ERR_FIFO = VXGE_HW_BASE_ERR + 19, ++ VXGE_HW_ERR_VPATH = VXGE_HW_BASE_ERR + 20, ++ VXGE_HW_ERR_CRITICAL = VXGE_HW_BASE_ERR + 21, ++ VXGE_HW_ERR_SLOT_FREEZE = VXGE_HW_BASE_ERR + 22, ++ ++ VXGE_HW_ERR_INVALID_MIN_BANDWIDTH = VXGE_HW_BASE_ERR + 25, ++ VXGE_HW_ERR_INVALID_MAX_BANDWIDTH = VXGE_HW_BASE_ERR + 26, ++ VXGE_HW_ERR_INVALID_TOTAL_BANDWIDTH = VXGE_HW_BASE_ERR + 27, ++ VXGE_HW_ERR_INVALID_BANDWIDTH_LIMIT = VXGE_HW_BASE_ERR + 28, ++ VXGE_HW_ERR_RESET_IN_PROGRESS = VXGE_HW_BASE_ERR + 29, ++ VXGE_HW_ERR_OUT_OF_SPACE = VXGE_HW_BASE_ERR + 30, ++ ++ VXGE_HW_BADCFG_RING_INDICATE_MAX_PKTS = VXGE_HW_BASE_BADCFG + 1, ++ VXGE_HW_BADCFG_FIFO_BLOCKS = VXGE_HW_BASE_BADCFG + 2, ++ VXGE_HW_BADCFG_VPATH_MTU = VXGE_HW_BASE_BADCFG + 3, ++ VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG = VXGE_HW_BASE_BADCFG + 4, ++ VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH = VXGE_HW_BASE_BADCFG + 5, ++ VXGE_HW_BADCFG_VPATH_BANDWIDTH_LIMIT = VXGE_HW_BASE_BADCFG + 6, ++ VXGE_HW_BADCFG_INTR_MODE = VXGE_HW_BASE_BADCFG + 7, ++ VXGE_HW_BADCFG_RTS_MAC_EN = VXGE_HW_BASE_BADCFG + 8, ++ VXGE_HW_BADCFG_VPATH_AGGR_ACK = VXGE_HW_BASE_BADCFG + 9, ++ ++ ++ VXGE_HW_EOF_TRACE_BUF = -1 ++}; ++ ++/** ++ * enum enum vxge_hw_device_link_state - Link state enumeration. ++ * @VXGE_HW_LINK_NONE: Invalid link state. ++ * @VXGE_HW_LINK_DOWN: Link is down. ++ * @VXGE_HW_LINK_UP: Link is up. ++ * ++ */ ++enum vxge_hw_device_link_state { ++ VXGE_HW_LINK_NONE, ++ VXGE_HW_LINK_DOWN, ++ VXGE_HW_LINK_UP ++}; ++ ++/** ++ * struct vxge_hw_device_date - Date Format ++ * @day: Day ++ * @month: Month ++ * @year: Year ++ * @date: Date in string format ++ * ++ * Structure for returning date ++ */ ++ ++#define VXGE_HW_FW_STRLEN 32 ++struct vxge_hw_device_date { ++ u32 day; ++ u32 month; ++ u32 year; ++ char date[VXGE_HW_FW_STRLEN]; ++}; ++ ++struct vxge_hw_device_version { ++ u32 major; ++ u32 minor; ++ u32 build; ++ char version[VXGE_HW_FW_STRLEN]; ++}; ++ ++u64 ++__vxge_hw_vpath_pci_func_mode_get( ++ u32 vp_id, ++ struct vxge_hw_vpath_reg __iomem *vpath_reg); ++ ++/** ++ * struct vxge_hw_fifo_config - Configuration of fifo. ++ * @enable: Is this fifo to be commissioned ++ * @fifo_blocks: Numbers of TxDL (that is, lists of Tx descriptors) ++ * blocks per queue. ++ * @max_frags: Max number of Tx buffers per TxDL (that is, per single ++ * transmit operation). ++ * No more than 256 transmit buffers can be specified. ++ * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size ++ * bytes. Setting @memblock_size to page size ensures ++ * by-page allocation of descriptors. ++ * @alignment_size: per Tx fragment DMA-able memory used to align transmit data ++ * (e.g., to align on a cache line). ++ * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL. ++ * Use 0 otherwise. ++ * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, ++ * which generally improves latency of the host bridge operation ++ * (see PCI specification). For valid values please refer ++ * to struct vxge_hw_fifo_config{} in the driver sources. ++ * Configuration of all Titan fifos. ++ * Note: Valid (min, max) range for each attribute is specified in the body of ++ * the struct vxge_hw_fifo_config{} structure. ++ */ ++struct vxge_hw_fifo_config { ++ u32 enable; ++#define VXGE_HW_FIFO_ENABLE 1 ++#define VXGE_HW_FIFO_DISABLE 0 ++ ++ u32 fifo_blocks; ++#define VXGE_HW_MIN_FIFO_BLOCKS 2 ++#define VXGE_HW_MAX_FIFO_BLOCKS 128 ++ ++ u32 max_frags; ++#define VXGE_HW_MIN_FIFO_FRAGS 1 ++#define VXGE_HW_MAX_FIFO_FRAGS 256 ++ ++ u32 memblock_size; ++#define VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE VXGE_HW_BLOCK_SIZE ++#define VXGE_HW_MAX_FIFO_MEMBLOCK_SIZE VXGE_HW_BLOCK_SIZE ++#define VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE VXGE_HW_BLOCK_SIZE ++ ++ u32 alignment_size; ++#define VXGE_HW_MIN_FIFO_ALIGNMENT_SIZE 0 ++#define VXGE_HW_MAX_FIFO_ALIGNMENT_SIZE 65536 ++#define VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE VXGE_CACHE_LINE_SIZE ++ ++ u32 intr; ++#define VXGE_HW_FIFO_QUEUE_INTR_ENABLE 1 ++#define VXGE_HW_FIFO_QUEUE_INTR_DISABLE 0 ++#define VXGE_HW_FIFO_QUEUE_INTR_DEFAULT 0 ++ ++ u32 no_snoop_bits; ++#define VXGE_HW_FIFO_NO_SNOOP_DISABLED 0 ++#define VXGE_HW_FIFO_NO_SNOOP_TXD 1 ++#define VXGE_HW_FIFO_NO_SNOOP_FRM 2 ++#define VXGE_HW_FIFO_NO_SNOOP_ALL 3 ++#define VXGE_HW_FIFO_NO_SNOOP_DEFAULT 0 ++ ++}; ++/** ++ * struct vxge_hw_ring_config - Ring configurations. ++ * @enable: Is this ring to be commissioned ++ * @ring_blocks: Numbers of RxD blocks in the ring ++ * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer ++ * to Titan User Guide. ++ * @rxd_qword_limit: Number of quad words of descriptors received after which ++ * the posted rxds are fetched by the hw. Preferably set to a ++ * power-of-2 value so that doorbells will be posted in power-of-2 ++ * values also. A value of 16 (unit is qword) is 128 bytes. ++ * @scatter_mode: Titan supports two receive scatter modes: A and B. ++ * For details please refer to Titan User Guide. ++ * @rx_timer_val: The number of 32ns periods that would be counted between two ++ * timer interrupts. ++ * @greedy_return: If Set it forces the device to return absolutely all RxD ++ * that are consumed and still on board when a timer interrupt ++ * triggers. If Clear, then if the device has already returned ++ * RxD before current timer interrupt trigerred and after the ++ * previous timer interrupt triggered, then the device is not ++ * forced to returned the rest of the consumed RxD that it has ++ * on board which account for a byte count less than the one ++ * programmed into PRC_CFG6.RXD_CRXDT field ++ * @rx_timer_ci: TBD ++ * @backoff_interval_us: Time (in microseconds), after which Titan ++ * tries to download RxDs posted by the host. ++ * Note that the "backoff" does not happen if host posts receive ++ * descriptors in the timely fashion. ++ * Ring configuration. ++ */ ++struct vxge_hw_ring_config { ++ u32 enable; ++#define VXGE_HW_RING_ENABLE 1 ++#define VXGE_HW_RING_DISABLE 0 ++#define VXGE_HW_RING_DEFAULT 1 ++ ++ u32 ring_blocks; ++#define VXGE_HW_MIN_RING_BLOCKS 1 ++#define VXGE_HW_MAX_RING_BLOCKS 128 ++#define VXGE_HW_DEF_RING_BLOCKS 2 ++ ++ u32 buffer_mode; ++#define VXGE_HW_RING_RXD_BUFFER_MODE_1 1 ++#define VXGE_HW_RING_RXD_BUFFER_MODE_3 3 ++#define VXGE_HW_RING_RXD_BUFFER_MODE_5 5 ++#define VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT 1 ++ ++ u32 scatter_mode; ++#define VXGE_HW_RING_SCATTER_MODE_A 0 ++#define VXGE_HW_RING_SCATTER_MODE_B 1 ++#define VXGE_HW_RING_SCATTER_MODE_C 2 ++#define VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT 0xffffffff ++ ++ u64 rxd_qword_limit; ++#define VXGE_HW_DEF_RING_RXD_QWORD_LIMIT 16 ++#define VXGE_HW_MIN_RING_RXD_QWORD_LIMIT 4 ++ ++ int sw_lro_sessions; ++#define VXGE_HW_SW_LRO_MIN_SESSIONS 1 ++#define VXGE_HW_SW_LRO_MAX_SESSIONS 64 ++#define VXGE_HW_SW_LRO_DEFAULT_SESSIONS 32 ++ ++ int sw_lro_sg_size; ++#define VXGE_HW_SW_LRO_MIN_SG_SIZE 1 ++#define VXGE_HW_SW_LRO_MAX_SG_SIZE 64 ++#define VXGE_HW_SW_LRO_DEFAULT_SG_SIZE 10 ++ ++ int sw_lro_frm_len; ++#define VXGE_HW_SW_LRO_MIN_FRM_LEN 4096 ++#define VXGE_HW_SW_LRO_MAX_FRM_LEN 65536 ++#define VXGE_HW_SW_LRO_DEFAULT_FRM_LEN 65536 ++ ++ u32 doorbell_mode; ++#define VXGE_HW_DOORBELL_MODE_ENABLE 1 ++#define VXGE_HW_DOORBELL_MODE_DISABLE 0 ++#define VXGE_HW_DOORBELL_MODE_DEFAULT 2 ++}; ++ ++/** ++ * struct vxge_hw_vp_config - Configuration of virtual path ++ * @vp_id: Virtual Path Id ++ * @rx_bw_limit: Minimum Guaranteed rx bandwidth ++ * @tx_bw_limit: Minimum Guaranteed tx bandwidth ++ * @ring: See struct vxge_hw_ring_config{}. ++ * @fifo: See struct vxge_hw_fifo_config{}. ++ * @tti: Configuration of interrupt associated with Transmit. ++ * see struct vxge_hw_tim_intr_config(); ++ * @rti: Configuration of interrupt associated with Receive. ++ * see struct vxge_hw_tim_intr_config(); ++ * @mtu: mtu size used on this port. ++ * @rpa_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device to ++ * remove the VLAN tag from all received tagged frames that are not ++ * replicated at the internal L2 switch. ++ * 0 - Do not strip the VLAN tag. ++ * 1 - Strip the VLAN tag. Regardless of this setting, VLAN tags are ++ * always placed into the RxDMA descriptor. ++ * ++ * This structure is used by the driver to pass the configuration parameters to ++ * configure Virtual Path. ++ */ ++struct vxge_hw_vp_config { ++ u32 vp_id; ++ ++#define VXGE_HW_VPATH_PRIORITY_MIN 0 ++#define VXGE_HW_VPATH_PRIORITY_MAX 16 ++#define VXGE_HW_VPATH_PRIORITY_DEFAULT 0 ++ ++ u32 tx_bw_limit; ++#define VXGE_HW_VPATH_TX_BANDWIDTH_LIMIT_MAX 10000 ++#define VXGE_HW_VPATH_TX_BANDWIDTH_LIMIT_MIN 0 ++#define VXGE_HW_VPATH_TX_BANDWIDTH_LIMIT_DEFAULT 0 ++ ++ u32 rx_bw_limit; ++#define VXGE_HW_VPATH_RX_BANDWIDTH_LIMIT_MAX 10000 ++#define VXGE_HW_VPATH_RX_BANDWIDTH_LIMIT_MIN 0 ++#define VXGE_HW_VPATH_RX_BANDWIDTH_LIMIT_DEFAULT 0 ++ ++ struct vxge_hw_ring_config ring; ++ struct vxge_hw_fifo_config fifo; ++ struct vxge_hw_tim_intr_config tti; ++ struct vxge_hw_tim_intr_config rti; ++ ++ u32 mtu; ++#define VXGE_HW_VPATH_MIN_INITIAL_MTU VXGE_HW_MIN_MTU ++#define VXGE_HW_VPATH_MAX_INITIAL_MTU VXGE_HW_MAX_MTU ++#define VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU 0xffffffff ++ ++ u32 rpa_strip_vlan_tag; ++#define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE 1 ++#define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE 0 ++#define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT 0xffffffff ++ ++ u8 aggr_ack; ++#define VXGE_HW_VPATH_AGGR_ACK_ENABLE 1 ++#define VXGE_HW_VPATH_AGGR_ACK_DISABLE 0 ++#define VXGE_HW_VPATH_AGGR_ACK_DEFAULT 0 ++}; ++/** ++ * struct vxge_hw_device_config - Device configuration. ++ * @intr_mode: Line, or MSI-X interrupt. ++ * ++ * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table). ++ * @rth_it_type: RTH IT table programming type ++ * @vp_config: Configuration for virtual paths ++ * @device_poll_millis: Specify the interval (in mulliseconds) ++ * to wait for register reads ++ * ++ * Titan configuration. ++ * Contains per-device configuration parameters, including: ++ * - stats sampling interval, etc. ++ * ++ * In addition, struct vxge_hw_device_config{} includes "subordinate" ++ * configurations, including: ++ * - fifos and rings; ++ * - MAC (done at firmware level). ++ * ++ * See Titan User Guide for more details. ++ * Note: Valid (min, max) range for each attribute is specified in the body of ++ * the struct vxge_hw_device_config{} structure. Please refer to the ++ * corresponding include file. ++ * See also: struct vxge_hw_tim_intr_config{}. ++ */ ++struct vxge_hw_device_config { ++ ++ ++ ++#define VXGE_HW_MAX_PAYLOAD_SIZE_512 2 ++ ++ u32 intr_mode; ++#define VXGE_HW_INTR_MODE_IRQLINE 0 ++#define VXGE_HW_INTR_MODE_MSIX 1 ++#define VXGE_HW_INTR_MODE_MSIX_ONE_SHOT 2 ++ ++#define VXGE_HW_INTR_MODE_DEF 0 ++ ++ u32 rth_en; ++#define VXGE_HW_RTH_DISABLE 0 ++#define VXGE_HW_RTH_ENABLE 1 ++#define VXGE_HW_RTH_DEFAULT 0 ++ ++ u32 rth_it_type; ++#define VXGE_HW_RTH_IT_TYPE_MULTI_IT 1 ++#define VXGE_HW_RTH_IT_TYPE_DEFAULT 0 ++ ++ struct vxge_hw_vp_config vp_config[VXGE_HW_MAX_VIRTUAL_PATHS]; ++ ++ u32 device_poll_millis; ++#define VXGE_HW_MIN_DEVICE_POLL_MILLIS 1 ++#define VXGE_HW_MAX_DEVICE_POLL_MILLIS 100000 ++#define VXGE_HW_DEF_DEVICE_POLL_MILLIS 1000 ++ ++ u32 lro_enable; ++#define VXGE_HW_LRO_DONOT_AGGREGATE 0 ++#define VXGE_HW_LRO_ALWAYS_AGGREGATE 1 ++#define VXGE_HW_LRO_DONT_AGGR_FWD_PKTS 2 ++#define VXGE_HW_GRO_ENABLE 3 ++ ++ u32 stats_read_method; ++#define VXGE_HW_STATS_READ_METHOD_DMA 1 ++#define VXGE_HW_STATS_READ_METHOD_PIO 0 ++#define VXGE_HW_STATS_READ_METHOD_DEFAULT 1 ++ ++}; ++ ++/** ++ * function vxge_uld_link_up_f - Link-Up callback provided by driver. ++ * @devh: HW device handle. ++ * Link-up notification callback provided by the driver. ++ * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}. ++ * ++ * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_down_f{}, ++ * vxge_hw_driver_initialize(). ++ */ ++ ++/** ++ * function vxge_uld_link_down_f - Link-Down callback provided by ++ * driver. ++ * @devh: HW device handle. ++ * ++ * Link-Down notification callback provided by the driver. ++ * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}. ++ * ++ * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_up_f{}, ++ * vxge_hw_driver_initialize(). ++ */ ++ ++/** ++ * function vxge_uld_crit_err_f - Critical Error notification callback. ++ * @devh: HW device handle. ++ * (typically - at HW device iinitialization time). ++ * @type: Enumerated hw error, e.g.: double ECC. ++ * @serr_data: Titan status. ++ * @ext_data: Extended data. The contents depends on the @type. ++ * ++ * Link-Down notification callback provided by the driver. ++ * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}. ++ * ++ * See also: struct vxge_hw_uld_cbs{}, enum vxge_hw_event{}, ++ * vxge_hw_driver_initialize(). ++ */ ++ ++/** ++ * struct vxge_hw_uld_cbs - driver "slow-path" callbacks. ++ * @link_up: See vxge_uld_link_up_f{}. ++ * @link_down: See vxge_uld_link_down_f{}. ++ * @crit_err: See vxge_uld_crit_err_f{}. ++ * ++ * Driver slow-path (per-driver) callbacks. ++ * Implemented by driver and provided to HW via ++ * vxge_hw_driver_initialize(). ++ * Note that these callbacks are not mandatory: HW will not invoke ++ * a callback if NULL is specified. ++ * ++ * See also: vxge_hw_driver_initialize(). ++ */ ++struct vxge_hw_uld_cbs { ++ ++ void (*link_up)(struct __vxge_hw_device *devh); ++ void (*link_down)(struct __vxge_hw_device *devh); ++ void (*crit_err)(struct __vxge_hw_device *devh, ++ enum vxge_hw_event type, u64 ext_data); ++}; ++ ++/* ++ * struct __vxge_hw_blockpool_entry - Block private data structure ++ * @item: List header used to link. ++ * @length: Length of the block ++ * @memblock: Virtual address block ++ * @dma_addr: DMA Address of the block. ++ * @dma_handle: DMA handle of the block. ++ * @acc_handle: DMA acc handle ++ * ++ * Block is allocated with a header to put the blocks into list. ++ * ++ */ ++struct __vxge_hw_blockpool_entry { ++ struct list_head item; ++ u32 length; ++ void *memblock; ++ dma_addr_t dma_addr; ++ struct pci_dev *dma_handle; ++ struct pci_dev *acc_handle; ++}; ++ ++/* ++ * struct __vxge_hw_blockpool - Block Pool ++ * @hldev: HW device ++ * @block_size: size of each block. ++ * @free_block_list: List of free blocks ++ * ++ * Block pool contains the DMA blocks preallocated. ++ * ++ */ ++struct __vxge_hw_blockpool { ++ struct __vxge_hw_device *hldev; ++ u32 block_size; ++ struct list_head free_block_list; ++ struct list_head free_entry_list; ++}; ++ ++/* ++ * enum enum __vxge_hw_channel_type - Enumerated channel types. ++ * @VXGE_HW_CHANNEL_TYPE_UNKNOWN: Unknown channel. ++ * @VXGE_HW_CHANNEL_TYPE_FIFO: fifo. ++ * @VXGE_HW_CHANNEL_TYPE_RING: ring. ++ * @VXGE_HW_CHANNEL_TYPE_MAX: Maximum number of HW-supported ++ * (and recognized) channel types. Currently: 2. ++ * ++ * Enumerated channel types. Currently there are only two link-layer ++ * channels - Titan fifo and Titan ring. In the future the list will grow. ++ */ ++enum __vxge_hw_channel_type { ++ VXGE_HW_CHANNEL_TYPE_UNKNOWN = 0, ++ VXGE_HW_CHANNEL_TYPE_FIFO = 1, ++ VXGE_HW_CHANNEL_TYPE_RING = 2, ++ VXGE_HW_CHANNEL_TYPE_MAX = 3 ++}; ++ ++/* ++ * struct __vxge_hw_channel ++ * @item: List item; used to maintain a list of open channels. ++ * @type: Channel type. See enum vxge_hw_channel_type{}. ++ * @devh: Device handle. HW device object that contains _this_ channel. ++ * @vph: Virtual path handle. Virtual Path Object that contains _this_ channel. ++ * @length: Channel length. Currently allocated number of descriptors. ++ * The channel length "grows" when more descriptors get allocated. ++ * See _hw_mempool_grow. ++ * @reserve_arr: Reserve array. Contains descriptors that can be reserved ++ * by driver for the subsequent send or receive operation. ++ * See vxge_hw_fifo_txdl_reserve(), ++ * vxge_hw_ring_rxd_reserve(). ++ * @reserve_ptr: Current pointer in the resrve array ++ * @reserve_top: Reserve top gives the maximum number of dtrs available in ++ * reserve array. ++ * @work_arr: Work array. Contains descriptors posted to the channel. ++ * Note that at any point in time @work_arr contains 3 types of ++ * descriptors: ++ * 1) posted but not yet consumed by Titan device; ++ * 2) consumed but not yet completed; ++ * 3) completed but not yet freed ++ * (via vxge_hw_fifo_txdl_free() or vxge_hw_ring_rxd_free()) ++ * @post_index: Post index. At any point in time points on the ++ * position in the channel, which'll contain next to-be-posted ++ * descriptor. ++ * @compl_index: Completion index. At any point in time points on the ++ * position in the channel, which will contain next ++ * to-be-completed descriptor. ++ * @free_arr: Free array. Contains completed descriptors that were freed ++ * (i.e., handed over back to HW) by driver. ++ * See vxge_hw_fifo_txdl_free(), vxge_hw_ring_rxd_free(). ++ * @free_ptr: current pointer in free array ++ * @per_dtr_space: Per-descriptor space (in bytes) that channel user can utilize ++ * to store per-operation control information. ++ * @stats: Pointer to common statistics ++ * @userdata: Per-channel opaque (void*) user-defined context, which may be ++ * driver object, ULP connection, etc. ++ * Once channel is open, @userdata is passed back to user via ++ * vxge_hw_channel_callback_f. ++ * ++ * HW channel object. ++ * ++ * See also: enum vxge_hw_channel_type{}, enum vxge_hw_channel_flag ++ */ ++struct __vxge_hw_channel { ++ struct list_head item; ++ enum __vxge_hw_channel_type type; ++ struct __vxge_hw_device *devh; ++ struct __vxge_hw_vpath_handle *vph; ++ u32 length; ++ u32 vp_id; ++ void **reserve_arr; ++ u32 reserve_ptr; ++ u32 reserve_top; ++ void **work_arr; ++ u32 post_index ____cacheline_aligned; ++ u32 compl_index ____cacheline_aligned; ++ void **free_arr; ++ u32 free_ptr; ++ void **orig_arr; ++ u32 per_dtr_space; ++ void *userdata; ++ struct vxge_hw_common_reg __iomem *common_reg; ++ u32 first_vp_id; ++ struct vxge_hw_vpath_stats_sw_common_info *stats; ++ ++} ____cacheline_aligned; ++ ++/* ++ * struct __vxge_hw_virtualpath - Virtual Path ++ * ++ * @vp_id: Virtual path id ++ * @vp_open: This flag specifies if vxge_hw_vp_open is called from LL Driver ++ * @hldev: Hal device ++ * @vp_config: Virtual Path Config ++ * @vp_reg: VPATH Register map address in BAR0 ++ * @vpmgmt_reg: VPATH_MGMT register map address ++ * @max_mtu: Max mtu that can be supported ++ * @vsport_number: vsport attached to this vpath ++ * @max_kdfc_db: Maximum kernel mode doorbells ++ * @max_nofl_db: Maximum non offload doorbells ++ * @tx_intr_num: Interrupt Number associated with the TX ++ ++ * @ringh: Ring Queue ++ * @fifoh: FIFO Queue ++ * @vpath_handles: Virtual Path handles list ++ * @stats_block: Memory for DMAing stats ++ * @stats: Vpath statistics ++ * ++ * Virtual path structure to encapsulate the data related to a virtual path. ++ * Virtual paths are allocated by the HW upon getting configuration from the ++ * driver and inserted into the list of virtual paths. ++ */ ++struct __vxge_hw_virtualpath { ++ u32 vp_id; ++ ++ u32 vp_open; ++#define VXGE_HW_VP_NOT_OPEN 0 ++#define VXGE_HW_VP_OPEN 1 ++ ++ struct __vxge_hw_device *hldev; ++ struct vxge_hw_vp_config *vp_config; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg; ++ struct __vxge_hw_non_offload_db_wrapper __iomem *nofl_db; ++ ++ u32 max_mtu; ++ u32 vsport_number; ++ u32 max_kdfc_db; ++ u32 max_nofl_db; ++ u64 tim_rti_cfg1_saved; ++ u64 tim_rti_cfg3_saved; ++ ++ struct __vxge_hw_ring *____cacheline_aligned ringh; ++ struct __vxge_hw_fifo *____cacheline_aligned fifoh; ++ struct list_head vpath_handles; ++ struct __vxge_hw_blockpool_entry *stats_block; ++ struct vxge_hw_vpath_stats_hw_info *hw_stats; ++ struct vxge_hw_vpath_stats_hw_info *hw_stats_sav; ++ struct vxge_hw_vpath_stats_sw_info *sw_stats; ++}; ++ ++/* ++ * struct __vxge_hw_vpath_handle - List item to store callback information ++ * @item: List head to keep the item in linked list ++ * @vpath: Virtual path to which this item belongs ++ * ++ * This structure is used to store the callback information. ++ */ ++struct __vxge_hw_vpath_handle{ ++ struct list_head item; ++ struct __vxge_hw_virtualpath *vpath; ++}; ++ ++/* ++ * struct __vxge_hw_device ++ * ++ * HW device object. ++ */ ++/** ++ * struct __vxge_hw_device - Hal device object ++ * @magic: Magic Number ++ * @bar0: BAR0 virtual address. ++ * @pdev: Physical device handle ++ * @config: Confguration passed by the LL driver at initialization ++ * @link_state: Link state ++ * ++ * HW device object. Represents Titan adapter ++ */ ++struct __vxge_hw_device { ++ u32 magic; ++#define VXGE_HW_DEVICE_MAGIC 0x12345678 ++#define VXGE_HW_DEVICE_DEAD 0xDEADDEAD ++ void __iomem *bar0; ++ struct pci_dev *pdev; ++ struct net_device *ndev; ++ struct vxge_hw_device_config config; ++ enum vxge_hw_device_link_state link_state; ++ ++ struct vxge_hw_uld_cbs uld_callbacks; ++ ++ u32 host_type; ++ u32 func_id; ++ u8 titan1; ++ u32 access_rights; ++#define VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH 0x1 ++#define VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM 0x2 ++#define VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM 0x4 ++ struct vxge_hw_legacy_reg __iomem *legacy_reg; ++ struct vxge_hw_toc_reg __iomem *toc_reg; ++ struct vxge_hw_common_reg __iomem *common_reg; ++ struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg; ++ struct vxge_hw_srpcim_reg __iomem *srpcim_reg \ ++ [VXGE_HW_TITAN_SRPCIM_REG_SPACES]; ++ struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg \ ++ [VXGE_HW_TITAN_VPMGMT_REG_SPACES]; ++ struct vxge_hw_vpath_reg __iomem *vpath_reg \ ++ [VXGE_HW_TITAN_VPATH_REG_SPACES]; ++ u8 __iomem *kdfc; ++ u8 __iomem *usdc; ++ struct __vxge_hw_virtualpath virtual_paths \ ++ [VXGE_HW_MAX_VIRTUAL_PATHS]; ++ u64 vpath_assignments; ++ u64 vpaths_deployed; ++ u32 first_vp_id; ++ u64 tim_int_mask0[4]; ++ u32 tim_int_mask1[4]; ++ ++ ++ struct __vxge_hw_blockpool block_pool; ++ struct __vxge_hw_blockpool_entry *mrpcim_stats_block; ++ struct vxge_hw_device_stats_mrpcim_info *mrpcim_stats; ++ struct vxge_hw_device_stats_mrpcim_info *mrpcim_stats_sav; ++ struct vxge_hw_device_stats stats; ++ u32 debug_module_mask; ++ u32 debug_level; ++ u32 level_err; ++ u32 level_trace; ++}; ++ ++#define VXGE_HW_INFO_LEN 64 ++/** ++ * struct vxge_hw_device_hw_info - Device information ++ * @host_type: Host Type ++ * @func_id: Function Id ++ * @vpath_mask: vpath bit mask ++ * @fw_version: Firmware version ++ * @fw_date: Firmware Date ++ * @flash_version: Firmware version ++ * @flash_date: Firmware Date ++ * @mac_addrs: Mac addresses for each vpath ++ * @mac_addr_masks: Mac address masks for each vpath ++ * ++ * Returns the vpath mask that has the bits set for each vpath allocated ++ * for the driver and the first mac address for each vpath ++ */ ++struct vxge_hw_device_hw_info { ++ u32 host_type; ++#define VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION 0 ++#define VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION 1 ++#define VXGE_HW_NO_MR_SR_VH0_FUNCTION0 2 ++#define VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION 3 ++#define VXGE_HW_MR_SR_VH0_INVALID_CONFIG 4 ++#define VXGE_HW_SR_VH_FUNCTION0 5 ++#define VXGE_HW_SR_VH_VIRTUAL_FUNCTION 6 ++#define VXGE_HW_VH_NORMAL_FUNCTION 7 ++ u64 function_mode; ++#define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION 0 ++#define VXGE_HW_FUNCTION_MODE_SINGLE_FUNCTION 1 ++#define VXGE_HW_FUNCTION_MODE_SRIOV 2 ++#define VXGE_HW_FUNCTION_MODE_MRIOV 3 ++ u32 func_id; ++ u64 vpath_mask; ++ struct vxge_hw_device_version fw_version; ++ struct vxge_hw_device_date fw_date; ++ struct vxge_hw_device_version flash_version; ++ struct vxge_hw_device_date flash_date; ++ u8 serial_number[VXGE_HW_INFO_LEN]; ++ u8 part_number[VXGE_HW_INFO_LEN]; ++ u8 product_desc[VXGE_HW_INFO_LEN]; ++ u8 (mac_addrs)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN]; ++ u8 (mac_addr_masks)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN]; ++}; ++ ++/** ++ * struct vxge_hw_device_attr - Device memory spaces. ++ * @bar0: BAR0 virtual address. ++ * @pdev: PCI device object. ++ * ++ * Device memory spaces. Includes configuration, BAR0 etc. per device ++ * mapped memories. Also, includes a pointer to OS-specific PCI device object. ++ */ ++struct vxge_hw_device_attr { ++ void __iomem *bar0; ++ struct pci_dev *pdev; ++ struct vxge_hw_uld_cbs uld_callbacks; ++}; ++ ++#define VXGE_HW_DEVICE_LINK_STATE_SET(hldev, ls) (hldev->link_state = ls) ++ ++#define VXGE_HW_DEVICE_TIM_INT_MASK_SET(m0, m1, i) { \ ++ if (i < 16) { \ ++ m0[0] |= vxge_vBIT(0x8, (i*4), 4); \ ++ m0[1] |= vxge_vBIT(0x4, (i*4), 4); \ ++ } \ ++ else { \ ++ m1[0] = 0x80000000; \ ++ m1[1] = 0x40000000; \ ++ } \ ++} ++ ++#define VXGE_HW_DEVICE_TIM_INT_MASK_RESET(m0, m1, i) { \ ++ if (i < 16) { \ ++ m0[0] &= ~vxge_vBIT(0x8, (i*4), 4); \ ++ m0[1] &= ~vxge_vBIT(0x4, (i*4), 4); \ ++ } \ ++ else { \ ++ m1[0] = 0; \ ++ m1[1] = 0; \ ++ } \ ++} ++ ++#define VXGE_HW_DEVICE_STATS_PIO_READ(loc, offset) { \ ++ status = vxge_hw_mrpcim_stats_access(hldev, \ ++ VXGE_HW_STATS_OP_READ, \ ++ loc, \ ++ offset, \ ++ &val64); \ ++ \ ++ if (status != VXGE_HW_OK) \ ++ return status; \ ++} ++ ++#define VXGE_HW_VPATH_STATS_PIO_READ(offset) { \ ++ status = __vxge_hw_vpath_stats_access(vpath, \ ++ VXGE_HW_STATS_OP_READ, \ ++ offset, \ ++ &val64); \ ++ if (status != VXGE_HW_OK) \ ++ return status; \ ++} ++ ++/* ++ * struct __vxge_hw_ring - Ring channel. ++ * @channel: Channel "base" of this ring, the common part of all HW ++ * channels. ++ * @mempool: Memory pool, the pool from which descriptors get allocated. ++ * (See vxge_hw_mm.h). ++ * @config: Ring configuration, part of device configuration ++ * (see struct vxge_hw_device_config{}). ++ * @ring_length: Length of the ring ++ * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode, ++ * as per Titan User Guide. ++ * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Titan spec, ++ * 1-buffer mode descriptor is 32 byte long, etc. ++ * @rxd_priv_size: Per RxD size reserved (by HW) for driver to keep ++ * per-descriptor data (e.g., DMA handle for Solaris) ++ * @per_rxd_space: Per rxd space requested by driver ++ * @rxds_per_block: Number of descriptors per hardware-defined RxD ++ * block. Depends on the (1-, 3-, 5-) buffer mode. ++ * @rxdblock_priv_size: Reserved at the end of each RxD block. HW internal ++ * usage. Not to confuse with @rxd_priv_size. ++ * @callback: Channel completion callback. HW invokes the callback when there ++ * are new completions on that channel. In many implementations ++ * the @callback executes in the hw interrupt context. ++ * @rxd_init: Channel's descriptor-initialize callback. ++ * See vxge_hw_ring_rxd_init_f{}. ++ * If not NULL, HW invokes the callback when opening ++ * the ring. ++ * @rxd_term: Channel's descriptor-terminate callback. If not NULL, ++ * HW invokes the callback when closing the corresponding channel. ++ * See also vxge_hw_channel_rxd_term_f{}. ++ * @stats: Statistics for ring ++ * Ring channel. ++ * ++ * Note: The structure is cache line aligned to better utilize ++ * CPU cache performance. ++ */ ++struct __vxge_hw_ring { ++ struct __vxge_hw_channel channel; ++ struct vxge_hw_mempool *mempool; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ struct vxge_hw_common_reg __iomem *common_reg; ++ u32 ring_length; ++ u32 buffer_mode; ++ u32 rxd_size; ++ u32 rxd_priv_size; ++ u32 per_rxd_space; ++#define VXGE_HW_RING_RXD_QWORDS_MODE_1 4 ++ u32 rxds_per_block; ++ u32 rxdblock_priv_size; ++ u32 vp_id; ++ u32 doorbell_cnt; ++ u32 total_db_cnt; ++ u64 rxd_qword_limit; ++ u32 lro_enable; ++ u32 rpa_strip_vlan_tag; ++ u32 btimer; ++ u32 rtimer; ++ u64 tim_rti_cfg1_saved; ++ u64 tim_rti_cfg3_saved; ++ u8 aggr_ack; ++ u32 active_sw_lro_count; ++ u32 free_sw_lro_count; ++ struct list_head active_sw_lros; ++ struct list_head free_sw_lros; ++ ++ enum vxge_hw_status (*callback)( ++ struct __vxge_hw_ring *ringh, ++ void *rxdh, ++ u8 t_code, ++ void *userdata); ++ ++ enum vxge_hw_status (*rxd_init)( ++ void *rxdh, ++ void *userdata); ++ ++ void (*rxd_term)( ++ void *rxdh, ++ enum vxge_hw_rxd_state state, ++ void *userdata); ++ ++ struct vxge_hw_vpath_stats_sw_ring_info *stats ____cacheline_aligned; ++ struct vxge_hw_ring_config *config; ++} ____cacheline_aligned; ++ ++/** ++ * enum enum vxge_hw_txdl_state - Descriptor (TXDL) state. ++ * @VXGE_HW_TXDL_STATE_NONE: Invalid state. ++ * @VXGE_HW_TXDL_STATE_AVAIL: Descriptor is available for reservation. ++ * @VXGE_HW_TXDL_STATE_POSTED: Descriptor is posted for processing by the ++ * device. ++ * @VXGE_HW_TXDL_STATE_FREED: Descriptor is free and can be reused for ++ * filling-in and posting later. ++ * ++ * Titan/HW descriptor states. ++ * ++ */ ++enum vxge_hw_txdl_state { ++ VXGE_HW_TXDL_STATE_NONE = 0, ++ VXGE_HW_TXDL_STATE_AVAIL = 1, ++ VXGE_HW_TXDL_STATE_POSTED = 2, ++ VXGE_HW_TXDL_STATE_FREED = 3 ++}; ++/* ++ * struct __vxge_hw_fifo - Fifo. ++ * @channel: Channel "base" of this fifo, the common part of all HW ++ * channels. ++ * @mempool: Memory pool, from which descriptors get allocated. ++ * @config: Fifo configuration, part of device configuration ++ * (see struct vxge_hw_device_config{}). ++ * @interrupt_type: Interrupt type to be used ++ * @no_snoop_bits: See struct vxge_hw_fifo_config{}. ++ * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock. ++ * on TxDL please refer to Titan UG. ++ * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus ++ * per-TxDL HW private space (struct __vxge_hw_fifo_txdl_priv). ++ * @priv_size: Per-Tx descriptor space reserved for driver ++ * usage. ++ * @per_txdl_space: Per txdl private space for the driver ++ * @callback: Fifo completion callback. HW invokes the callback when there ++ * are new completions on that fifo. In many implementations ++ * the @callback executes in the hw interrupt context. ++ * @txdl_term: Fifo's descriptor-terminate callback. If not NULL, ++ * HW invokes the callback when closing the corresponding fifo. ++ * See also vxge_hw_fifo_txdl_term_f{}. ++ * @stats: Statistics of this fifo ++ * ++ * Fifo channel. ++ * Note: The structure is cache line aligned. ++ */ ++struct __vxge_hw_fifo { ++ struct __vxge_hw_channel channel; ++ struct vxge_hw_mempool *mempool; ++ struct vxge_hw_fifo_config *config; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ struct __vxge_hw_non_offload_db_wrapper __iomem *nofl_db; ++ u64 interrupt_type; ++ u32 no_snoop_bits; ++ u32 txdl_per_memblock; ++ u32 txdl_size; ++ u32 priv_size; ++ u32 per_txdl_space; ++ u32 vp_id; ++ u32 tx_intr_num; ++ ++ enum vxge_hw_status (*callback)( ++ struct __vxge_hw_fifo *fifo_handle, ++ void *txdlh, ++ enum vxge_hw_fifo_tcode t_code, ++ void *userdata, ++ struct sk_buff ***skb_ptr, ++ int nr_skb, ++ int *more); ++ ++ void (*txdl_term)( ++ void *txdlh, ++ enum vxge_hw_txdl_state state, ++ void *userdata); ++ ++ struct vxge_hw_vpath_stats_sw_fifo_info *stats ____cacheline_aligned; ++} ____cacheline_aligned; ++ ++ ++ ++/** ++ * vxge_hw_vpath_bandwidth_set - Set the bandwidth for a vpath. ++ * @hldev: HW device handle. ++ * @vp_id: Vpath Id. ++ * @bandwidth: Bandwidth (Valid values are 0 to 100%) ++ * ++ * Set the bandwidth for a given vpath ++ * ++ */ ++enum vxge_hw_status vxge_hw_vpath_bandwidth_set( ++ struct __vxge_hw_device *hldev, ++ u32 vp_id, enum __vxge_hw_channel_type type, ++ u32 bandwidth, u32 pkt_size); ++/* ++ * struct __vxge_hw_fifo_txdl_priv - Transmit descriptor HW-private data. ++ * @dma_addr: DMA (mapped) address of _this_ descriptor. ++ * @dma_handle: DMA handle used to map the descriptor onto device. ++ * @dma_offset: Descriptor's offset in the memory block. HW allocates ++ * descriptors in memory blocks (see struct vxge_hw_fifo_config{}) ++ * Each memblock is a contiguous block of DMA-able memory. ++ * @frags: Total number of fragments (that is, contiguous data buffers) ++ * carried by this TxDL. ++ * @align_vaddr_start: Aligned virtual address start ++ * @align_vaddr: Virtual address of the per-TxDL area in memory used for ++ * alignement. Used to place one or more mis-aligned fragments ++ * @align_dma_addr: DMA address translated from the @align_vaddr. ++ * @align_dma_handle: DMA handle that corresponds to @align_dma_addr. ++ * @align_dma_acch: DMA access handle corresponds to @align_dma_addr. ++ * @align_dma_offset: The current offset into the @align_vaddr area. ++ * Grows while filling the descriptor, gets reset. ++ * @align_used_frags: Number of fragments used. ++ * @alloc_frags: Total number of fragments allocated. ++ * @unused: TODO ++ * @next_txdl_priv: (TODO). ++ * @first_txdp: (TODO). ++ * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous ++ * TxDL list. ++ * @txdlh: Corresponding txdlh to this TxDL. ++ * @memblock: Pointer to the TxDL memory block or memory page. ++ * on the next send operation. ++ * @dma_object: DMA address and handle of the memory block that contains ++ * the descriptor. This member is used only in the "checked" ++ * version of the HW (to enforce certain assertions); ++ * otherwise it gets compiled out. ++ * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. ++ * ++ * Per-transmit decsriptor HW-private data. HW uses the space to keep DMA ++ * information associated with the descriptor. Note that driver can ask HW ++ * to allocate additional per-descriptor space for its own (driver-specific) ++ * purposes. ++ * ++ * See also: struct vxge_hw_ring_rxd_priv{}. ++ */ ++struct __vxge_hw_fifo_txdl_priv { ++ dma_addr_t dma_addr; ++ struct pci_dev *dma_handle; ++ ptrdiff_t dma_offset; ++ u32 frags; ++ u8 *align_vaddr_start; ++ u8 *align_vaddr; ++ dma_addr_t align_dma_addr; ++ struct pci_dev *align_dma_handle; ++ struct pci_dev *align_dma_acch; ++ ptrdiff_t align_dma_offset; ++ u32 align_used_frags; ++ u32 alloc_frags; ++ u32 unused; ++ struct __vxge_hw_fifo_txdl_priv *next_txdl_priv; ++ struct vxge_hw_fifo_txd *first_txdp; ++ void *memblock; ++}; ++ ++/* ++ * struct __vxge_hw_non_offload_db_wrapper - Non-offload Doorbell Wrapper ++ * @control_0: Bits 0 to 7 - Doorbell type. ++ * Bits 8 to 31 - Reserved. ++ * Bits 32 to 39 - The highest TxD in this TxDL. ++ * Bits 40 to 47 - Reserved. ++ * Bits 48 to 55 - Reserved. ++ * Bits 56 to 63 - No snoop flags. ++ * @txdl_ptr: The starting location of the TxDL in host memory. ++ * ++ * Created by the host and written to the adapter via PIO to a Kernel Doorbell ++ * FIFO. All non-offload doorbell wrapper fields must be written by the host as ++ * part of a doorbell write. Consumed by the adapter but is not written by the ++ * adapter. ++ */ ++struct __vxge_hw_non_offload_db_wrapper { ++ u64 control_0; ++#define VXGE_HW_NODBW_GET_TYPE(ctrl0) vxge_bVALn(ctrl0, 0, 8) ++#define VXGE_HW_NODBW_TYPE(val) vxge_vBIT(val, 0, 8) ++#define VXGE_HW_NODBW_TYPE_NODBW 0 ++ ++#define VXGE_HW_NODBW_GET_LAST_TXD_NUMBER(ctrl0) vxge_bVALn(ctrl0, 32, 8) ++#define VXGE_HW_NODBW_LAST_TXD_NUMBER(val) vxge_vBIT(val, 32, 8) ++ ++#define VXGE_HW_NODBW_GET_NO_SNOOP(ctrl0) vxge_bVALn(ctrl0, 56, 8) ++#define VXGE_HW_NODBW_LIST_NO_SNOOP(val) vxge_vBIT(val, 56, 8) ++#define VXGE_HW_NODBW_LIST_NO_SNOOP_TXD_READ_TXD0_WRITE 0x2 ++#define VXGE_HW_NODBW_LIST_NO_SNOOP_TX_FRAME_DATA_READ 0x1 ++ ++ u64 txdl_ptr; ++}; ++ ++/* ++ * TX Descriptor ++ */ ++ ++/** ++ * struct vxge_hw_fifo_txd - Transmit Descriptor ++ * @control_0: Bits 0 to 6 - Reserved. ++ * Bit 7 - List Ownership. This field should be initialized ++ * to '1' by the driver before the transmit list pointer is ++ * written to the adapter. This field will be set to '0' by the ++ * adapter once it has completed transmitting the frame or frames in ++ * the list. Note - This field is only valid in TxD0. Additionally, ++ * for multi-list sequences, the driver should not release any ++ * buffers until the ownership of the last list in the multi-list ++ * sequence has been returned to the host. ++ * Bits 8 to 11 - Reserved ++ * Bits 12 to 15 - Transfer_Code. This field is only valid in ++ * TxD0. It is used to describe the status of the transmit data ++ * buffer transfer. This field is always overwritten by the ++ * adapter, so this field may be initialized to any value. ++ * Bits 16 to 17 - Host steering. This field allows the host to ++ * override the selection of the physical transmit port. ++ * Attention: ++ * Normal sounds as if learned from the switch rather than from ++ * the aggregation algorythms. ++ * 00: Normal. Use Destination/MAC Address ++ * lookup to determine the transmit port. ++ * 01: Send on physical Port1. ++ * 10: Send on physical Port0. ++ * 11: Send on both ports. ++ * Bits 18 to 21 - Reserved ++ * Bits 22 to 23 - Gather_Code. This field is set by the host and ++ * is used to describe how individual buffers comprise a frame. ++ * 10: First descriptor of a frame. ++ * 00: Middle of a multi-descriptor frame. ++ * 01: Last descriptor of a frame. ++ * 11: First and last descriptor of a frame (the entire frame ++ * resides in a single buffer). ++ * For multi-descriptor frames, the only valid gather code sequence ++ * is {10, [00], 01}. In other words, the descriptors must be placed ++ * in the list in the correct order. ++ * Bits 24 to 27 - Reserved ++ * Bits 28 to 29 - LSO_Frm_Encap. LSO Frame Encapsulation ++ * definition. Only valid in TxD0. This field allows the host to ++ * indicate the Ethernet encapsulation of an outbound LSO packet. ++ * 00 - classic mode (best guess) ++ * 01 - LLC ++ * 10 - SNAP ++ * 11 - DIX ++ * If "classic mode" is selected, the adapter will attempt to ++ * decode the frame's Ethernet encapsulation by examining the L/T ++ * field as follows: ++ * <= 0x05DC LLC/SNAP encoding; must examine DSAP/SSAP to determine ++ * if packet is IPv4 or IPv6. ++ * 0x8870 Jumbo-SNAP encoding. ++ * 0x0800 IPv4 DIX encoding ++ * 0x86DD IPv6 DIX encoding ++ * others illegal encapsulation ++ * Bits 30 - LSO_ Flag. Large Send Offload (LSO) flag. ++ * Set to 1 to perform segmentation offload for TCP/UDP. ++ * This field is valid only in TxD0. ++ * Bits 31 to 33 - Reserved. ++ * Bits 34 to 47 - LSO_MSS. TCP/UDP LSO Maximum Segment Size ++ * This field is meaningful only when LSO_Control is non-zero. ++ * When LSO_Control is set to TCP_LSO, the single (possibly large) ++ * TCP segment described by this TxDL will be sent as a series of ++ * TCP segments each of which contains no more than LSO_MSS ++ * payload bytes. ++ * When LSO_Control is set to UDP_LSO, the single (possibly large) ++ * UDP datagram described by this TxDL will be sent as a series of ++ * UDP datagrams each of which contains no more than LSO_MSS ++ * payload bytes. ++ * All outgoing frames from this TxDL will have LSO_MSS bytes of UDP ++ * or TCP payload, with the exception of the last, which will have ++ * <= LSO_MSS bytes of payload. ++ * Bits 48 to 63 - Buffer_Size. Number of valid bytes in the ++ * buffer to be read by the adapter. This field is written by the ++ * host. A value of 0 is illegal. ++ * Bits 32 to 63 - This value is written by the adapter upon ++ * completion of a UDP or TCP LSO operation and indicates the number ++ * of UDP or TCP payload bytes that were transmitted. 0x0000 will be ++ * returned for any non-LSO operation. ++ * @control_1: Bits 0 to 4 - Reserved. ++ * Bit 5 - Tx_CKO_IPv4 Set to a '1' to enable IPv4 header checksum ++ * offload. This field is only valid in the first TxD of a frame. ++ * Bit 6 - Tx_CKO_TCP Set to a '1' to enable TCP checksum offload. ++ * This field is only valid in the first TxD of a frame (the TxD's ++ * gather code must be 10 or 11). The driver should only set this ++ * bit if it can guarantee that TCP is present. ++ * Bit 7 - Tx_CKO_UDP Set to a '1' to enable UDP checksum offload. ++ * This field is only valid in the first TxD of a frame (the TxD's ++ * gather code must be 10 or 11). The driver should only set this ++ * bit if it can guarantee that UDP is present. ++ * Bits 8 to 14 - Reserved. ++ * Bit 15 - Tx_VLAN_Enable VLAN tag insertion flag. Set to a '1' to ++ * instruct the adapter to insert the VLAN tag specified by the ++ * Tx_VLAN_Tag field. This field is only valid in the first TxD of ++ * a frame. ++ * Bits 16 to 31 - Tx_VLAN_Tag. Variable portion of the VLAN tag ++ * to be inserted into the frame by the adapter (the first two bytes ++ * of a VLAN tag are always 0x8100). This field is only valid if the ++ * Tx_VLAN_Enable field is set to '1'. ++ * Bits 32 to 33 - Reserved. ++ * Bits 34 to 39 - Tx_Int_Number. Indicates which Tx interrupt ++ * number the frame associated with. This field is written by the ++ * host. It is only valid in the first TxD of a frame. ++ * Bits 40 to 42 - Reserved. ++ * Bit 43 - Set to 1 to exclude the frame from bandwidth metering ++ * functions. This field is valid only in the first TxD ++ * of a frame. ++ * Bits 44 to 45 - Reserved. ++ * Bit 46 - Tx_Int_Per_List Set to a '1' to instruct the adapter to ++ * generate an interrupt as soon as all of the frames in the list ++ * have been transmitted. In order to have per-frame interrupts, ++ * the driver should place a maximum of one frame per list. This ++ * field is only valid in the first TxD of a frame. ++ * Bit 47 - Tx_Int_Utilization Set to a '1' to instruct the adapter ++ * to count the frame toward the utilization interrupt specified in ++ * the Tx_Int_Number field. This field is only valid in the first ++ * TxD of a frame. ++ * Bits 48 to 63 - Reserved. ++ * @buffer_pointer: Buffer start address. ++ * @host_control: Host_Control.Opaque 64bit data stored by driver inside the ++ * Titan descriptor prior to posting the latter on the fifo ++ * via vxge_hw_fifo_txdl_post().The %host_control is returned as is ++ * to the driver with each completed descriptor. ++ * ++ * Transmit descriptor (TxD).Fifo descriptor contains configured number ++ * (list) of TxDs. * For more details please refer to Titan User Guide, ++ * Section 5.4.2 "Transmit Descriptor (TxD) Format". ++ */ ++struct vxge_hw_fifo_txd { ++ u64 control_0; ++#define VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER vxge_mBIT(7) ++ ++#define VXGE_HW_FIFO_TXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4) ++#define VXGE_HW_FIFO_TXD_T_CODE(val) vxge_vBIT(val, 12, 4) ++#define VXGE_HW_FIFO_TXD_T_CODE_UNUSED VXGE_HW_FIFO_T_CODE_UNUSED ++ ++ ++#define VXGE_HW_FIFO_TXD_GATHER_CODE(val) vxge_vBIT(val, 22, 2) ++#define VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST VXGE_HW_FIFO_GATHER_CODE_FIRST ++#define VXGE_HW_FIFO_TXD_GATHER_CODE_LAST VXGE_HW_FIFO_GATHER_CODE_LAST ++ ++ ++#define VXGE_HW_FIFO_TXD_LSO_EN vxge_mBIT(30) ++ ++#define VXGE_HW_FIFO_TXD_LSO_MSS(val) vxge_vBIT(val, 34, 14) ++ ++#define VXGE_HW_FIFO_TXD_BUFFER_SIZE(val) vxge_vBIT(val, 48, 16) ++ ++ u64 control_1; ++#define VXGE_HW_FIFO_TXD_TX_CKO_IPV4_EN vxge_mBIT(5) ++#define VXGE_HW_FIFO_TXD_TX_CKO_TCP_EN vxge_mBIT(6) ++#define VXGE_HW_FIFO_TXD_TX_CKO_UDP_EN vxge_mBIT(7) ++#define VXGE_HW_FIFO_TXD_VLAN_ENABLE vxge_mBIT(15) ++ ++#define VXGE_HW_FIFO_TXD_VLAN_TAG(val) vxge_vBIT(val, 16, 16) ++#define VXGE_HW_FIFO_TXD_NO_BW_LIMIT vxge_mBIT(43) ++ ++#define VXGE_HW_FIFO_TXD_INT_NUMBER(val) vxge_vBIT(val, 34, 6) ++ ++#define VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST vxge_mBIT(46) ++#define VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ vxge_mBIT(47) ++ ++ u64 buffer_pointer; ++ ++ u64 host_control; ++}; ++ ++/** ++ * struct vxge_hw_ring_rxd_1 - One buffer mode RxD for ring ++ * @host_control: This field is exclusively for host use and is "readonly" ++ * from the adapter's perspective. ++ * @control_0:Bits 0 to 6 - RTH_Bucket get ++ * Bit 7 - Own Descriptor ownership bit. This bit is set to 1 ++ * by the host, and is set to 0 by the adapter. ++ * 0 - Host owns RxD and buffer. ++ * 1 - The adapter owns RxD and buffer. ++ * Bit 8 - Fast_Path_Eligible When set, indicates that the ++ * received frame meets all of the criteria for fast path processing. ++ * The required criteria are as follows: ++ * !SYN & ++ * (Transfer_Code == "Transfer OK") & ++ * (!Is_IP_Fragment) & ++ * ((Is_IPv4 & computed_L3_checksum == 0xFFFF) | ++ * (Is_IPv6)) & ++ * ((Is_TCP & computed_L4_checksum == 0xFFFF) | ++ * (Is_UDP & (computed_L4_checksum == 0xFFFF | ++ * computed _L4_checksum == 0x0000))) ++ * (same meaning for all RxD buffer modes) ++ * Bit 9 - L3 Checksum Correct ++ * Bit 10 - L4 Checksum Correct ++ * Bit 11 - Reserved ++ * Bit 12 to 15 - This field is written by the adapter. It is ++ * used to report the status of the frame transfer to the host. ++ * 0x0 - Transfer OK ++ * 0x4 - RDA Failure During Transfer ++ * 0x5 - Unparseable Packet, such as unknown IPv6 header. ++ * 0x6 - Frame integrity error (FCS or ECC). ++ * 0x7 - Buffer Size Error. The provided buffer(s) were not ++ * appropriately sized and data loss occurred. ++ * 0x8 - Internal ECC Error. RxD corrupted. ++ * 0x9 - IPv4 Checksum error ++ * 0xA - TCP/UDP Checksum error ++ * 0xF - Unknown Error or Multiple Error. Indicates an ++ * unknown problem or that more than one of transfer codes is set. ++ * Bit 16 - SYN The adapter sets this field to indicate that ++ * the incoming frame contained a TCP segment with its SYN bit ++ * set and its ACK bit NOT set. (same meaning for all RxD buffer ++ * modes) ++ * Bit 17 - Is ICMP ++ * Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the ++ * Socket Pair Direct Match Table and the frame was steered based ++ * on SPDM. ++ * Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the ++ * Indirection Table and the frame was steered based on hash ++ * indirection. ++ * Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash ++ * type) that was used to calculate the hash. ++ * Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN ++ * tagged. ++ * Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation ++ * of the received frame. ++ * 0x0 - Ethernet DIX ++ * 0x1 - LLC ++ * 0x2 - SNAP (includes Jumbo-SNAP) ++ * 0x3 - IPX ++ * Bit 27 - IS_IPV4 Set to '1' if the frame contains an IPv4 packet. ++ * Bit 28 - IS_IPV6 Set to '1' if the frame contains an IPv6 packet. ++ * Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a fragmented ++ * IP packet. ++ * Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment. ++ * Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message. ++ * Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that ++ * arrived with the frame. If the resulting computed IPv4 header ++ * checksum for the frame did not produce the expected 0xFFFF value, ++ * then the transfer code would be set to 0x9. ++ * Bit 48 to 63 - L4_Checksum[0:15] The TCP/UDP checksum value that ++ * arrived with the frame. If the resulting computed TCP/UDP checksum ++ * for the frame did not produce the expected 0xFFFF value, then the ++ * transfer code would be set to 0xA. ++ * @control_1:Bits 0 to 1 - Reserved ++ * Bits 2 to 15 - Buffer0_Size.This field is set by the host and ++ * eventually overwritten by the adapter. The host writes the ++ * available buffer size in bytes when it passes the descriptor to ++ * the adapter. When a frame is delivered the host, the adapter ++ * populates this field with the number of bytes written into the ++ * buffer. The largest supported buffer is 16, 383 bytes. ++ * Bit 16 to 47 - RTH Hash Value 32-bit RTH hash value. Only valid if ++ * RTH_HASH_TYPE (Control_0, bits 20:23) is nonzero. ++ * Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable portion ++ * of the VLAN tag, if one was detected by the adapter. This field is ++ * populated even if VLAN-tag stripping is enabled. ++ * @buffer0_ptr: Pointer to buffer. This field is populated by the driver. ++ * ++ * One buffer mode RxD for ring structure ++ */ ++struct vxge_hw_ring_rxd_1 { ++ u64 host_control; ++ u64 control_0; ++#define VXGE_HW_RING_RXD_RTH_BUCKET_GET(ctrl0) vxge_bVALn(ctrl0, 0, 7) ++ ++#define VXGE_HW_RING_RXD_LIST_OWN_ADAPTER vxge_mBIT(7) ++ ++#define VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0) vxge_bVALn(ctrl0, 8, 1) ++ ++#define VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 9, 1) ++ ++#define VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 10, 1) ++ ++#define VXGE_HW_RING_RXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4) ++#define VXGE_HW_RING_RXD_T_CODE(val) vxge_vBIT(val, 12, 4) ++ ++#define VXGE_HW_RING_RXD_T_CODE_UNUSED VXGE_HW_RING_T_CODE_UNUSED ++ ++#define VXGE_HW_RING_RXD_SYN_GET(ctrl0) vxge_bVALn(ctrl0, 16, 1) ++ ++#define VXGE_HW_RING_RXD_IS_ICMP_GET(ctrl0) vxge_bVALn(ctrl0, 17, 1) ++ ++#define VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 18, 1) ++ ++#define VXGE_HW_RING_RXD_RTH_IT_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 19, 1) ++ ++#define VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(ctrl0) vxge_bVALn(ctrl0, 20, 4) ++ ++#define VXGE_HW_RING_RXD_IS_VLAN_GET(ctrl0) vxge_bVALn(ctrl0, 24, 1) ++ ++#define VXGE_HW_RING_RXD_ETHER_ENCAP_GET(ctrl0) vxge_bVALn(ctrl0, 25, 2) ++ ++#define VXGE_HW_RING_RXD_FRAME_PROTO_GET(ctrl0) vxge_bVALn(ctrl0, 27, 5) ++ ++#define VXGE_HW_RING_RXD_L3_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 32, 16) ++ ++#define VXGE_HW_RING_RXD_L4_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 48, 16) ++ ++ u64 control_1; ++ ++#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(ctrl1) vxge_bVALn(ctrl1, 2, 14) ++#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE(val) vxge_vBIT(val, 2, 14) ++#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK vxge_vBIT(0x3FFF, 2, 14) ++ ++#define VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(ctrl1) vxge_bVALn(ctrl1, 16, 32) ++ ++#define VXGE_HW_RING_RXD_VLAN_TAG_GET(ctrl1) vxge_bVALn(ctrl1, 48, 16) ++ ++ u64 buffer0_ptr; ++}; ++ ++enum vxge_hw_rth_algoritms { ++ RTH_ALG_JENKINS = 0, ++ RTH_ALG_MS_RSS = 1, ++ RTH_ALG_CRC32C = 2 ++}; ++ ++/** ++ * struct vxge_hw_rth_hash_types - RTH hash types. ++ * @hash_type_tcpipv4_en: Enables RTH field type HashTypeTcpIPv4 ++ * @hash_type_ipv4_en: Enables RTH field type HashTypeIPv4 ++ * @hash_type_tcpipv6_en: Enables RTH field type HashTypeTcpIPv6 ++ * @hash_type_ipv6_en: Enables RTH field type HashTypeIPv6 ++ * @hash_type_tcpipv6ex_en: Enables RTH field type HashTypeTcpIPv6Ex ++ * @hash_type_ipv6ex_en: Enables RTH field type HashTypeIPv6Ex ++ * ++ * Used to pass RTH hash types to rts_rts_set. ++ * ++ * See also: vxge_hw_vpath_rts_rth_set(), vxge_hw_vpath_rts_rth_get(). ++ */ ++struct vxge_hw_rth_hash_types { ++ u8 hash_type_tcpipv4_en; ++ u8 hash_type_ipv4_en; ++ u8 hash_type_tcpipv6_en; ++ u8 hash_type_ipv6_en; ++ u8 hash_type_tcpipv6ex_en; ++ u8 hash_type_ipv6ex_en; ++}; ++ ++u32 ++vxge_hw_device_debug_mask_get(struct __vxge_hw_device *devh); ++ ++void vxge_hw_device_debug_set( ++ struct __vxge_hw_device *devh, ++ enum vxge_debug_level level, ++ u32 mask); ++ ++u32 ++vxge_hw_device_error_level_get(struct __vxge_hw_device *devh); ++ ++u32 ++vxge_hw_device_trace_level_get(struct __vxge_hw_device *devh); ++ ++u32 ++vxge_hw_device_debug_mask_get(struct __vxge_hw_device *devh); ++ ++/** ++ * vxge_hw_ring_rxd_size_get - Get the size of ring descriptor. ++ * @buf_mode: Buffer mode (1, 3 or 5) ++ * ++ * This function returns the size of RxD for given buffer mode ++ */ ++static inline u32 vxge_hw_ring_rxd_size_get(u32 buf_mode) ++{ ++ return sizeof(struct vxge_hw_ring_rxd_1); ++} ++ ++/** ++ * vxge_hw_ring_rxds_per_block_get - Get the number of rxds per block. ++ * @buf_mode: Buffer mode (1 buffer mode only) ++ * ++ * This function returns the number of RxD for RxD block for given buffer mode ++ */ ++static inline u32 vxge_hw_ring_rxds_per_block_get(u32 buf_mode) ++{ ++ return (u32)((VXGE_HW_BLOCK_SIZE-16) / ++ sizeof(struct vxge_hw_ring_rxd_1)); ++} ++ ++/** ++ * vxge_hw_ring_rxd_1b_set - Prepare 1-buffer-mode descriptor. ++ * @rxdh: Descriptor handle. ++ * @dma_pointer: DMA address of a single receive buffer this descriptor ++ * should carry. Note that by the time vxge_hw_ring_rxd_1b_set is called, ++ * the receive buffer should be already mapped to the device ++ * @size: Size of the receive @dma_pointer buffer. ++ * ++ * Prepare 1-buffer-mode Rx descriptor for posting ++ * (via vxge_hw_ring_rxd_post()). ++ * ++ * This inline helper-function does not return any parameters and always ++ * succeeds. ++ * ++ */ ++static inline ++void vxge_hw_ring_rxd_1b_set( ++ void *rxdh, ++ dma_addr_t dma_pointer, ++ u32 size) ++{ ++ struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; ++ rxdp->buffer0_ptr = dma_pointer; ++ rxdp->control_1 &= ~VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK; ++ rxdp->control_1 |= VXGE_HW_RING_RXD_1_BUFFER0_SIZE(size); ++} ++ ++/** ++ * vxge_hw_ring_rxd_1b_get - Get data from the completed 1-buf ++ * descriptor. ++ * @vpath_handle: Virtual Path handle. ++ * @rxdh: Descriptor handle. ++ * @dma_pointer: DMA address of a single receive buffer this descriptor ++ * carries. Returned by HW. ++ * @pkt_length: Length (in bytes) of the data in the buffer pointed by ++ * ++ * Retrieve protocol data from the completed 1-buffer-mode Rx descriptor. ++ * This inline helper-function uses completed descriptor to populate receive ++ * buffer pointer and other "out" parameters. The function always succeeds. ++ * ++ */ ++static inline ++void vxge_hw_ring_rxd_1b_get( ++ struct __vxge_hw_ring *ring_handle, ++ void *rxdh, ++ u32 *pkt_length) ++{ ++ struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; ++ ++ *pkt_length = ++ (u32)VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(rxdp->control_1); ++} ++ ++/** ++ * vxge_hw_ring_rxd_1b_info_get - Get extended information associated with ++ * a completed receive descriptor for 1b mode. ++ * @vpath_handle: Virtual Path handle. ++ * @rxdh: Descriptor handle. ++ * @rxd_info: Descriptor information ++ * ++ * Retrieve extended information associated with a completed receive descriptor. ++ * ++ */ ++static inline ++void vxge_hw_ring_rxd_1b_info_get( ++ struct __vxge_hw_ring *ring_handle, ++ void *rxdh, ++ struct vxge_hw_ring_rxd_info *rxd_info) ++{ ++ ++ struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; ++ rxd_info->syn_flag = ++ (u32)VXGE_HW_RING_RXD_SYN_GET(rxdp->control_0); ++ rxd_info->is_icmp = ++ (u32)VXGE_HW_RING_RXD_IS_ICMP_GET(rxdp->control_0); ++ rxd_info->fast_path_eligible = ++ (u32)VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(rxdp->control_0); ++ rxd_info->l3_cksum_valid = ++ (u32)VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(rxdp->control_0); ++ rxd_info->l3_cksum = ++ (u32)VXGE_HW_RING_RXD_L3_CKSUM_GET(rxdp->control_0); ++ rxd_info->l4_cksum_valid = ++ (u32)VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(rxdp->control_0); ++ rxd_info->l4_cksum = ++ (u32)VXGE_HW_RING_RXD_L4_CKSUM_GET(rxdp->control_0);; ++ rxd_info->frame = ++ (u32)VXGE_HW_RING_RXD_ETHER_ENCAP_GET(rxdp->control_0); ++ rxd_info->proto = ++ (u32)VXGE_HW_RING_RXD_FRAME_PROTO_GET(rxdp->control_0); ++ rxd_info->is_vlan = ++ (u32)VXGE_HW_RING_RXD_IS_VLAN_GET(rxdp->control_0); ++ rxd_info->vlan = ++ (u32)VXGE_HW_RING_RXD_VLAN_TAG_GET(rxdp->control_1); ++ rxd_info->rth_bucket = ++ (u32)VXGE_HW_RING_RXD_RTH_BUCKET_GET(rxdp->control_0); ++ rxd_info->rth_it_hit = ++ (u32)VXGE_HW_RING_RXD_RTH_IT_HIT_GET(rxdp->control_0); ++ rxd_info->rth_spdm_hit = ++ (u32)VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(rxdp->control_0); ++ rxd_info->rth_hash_type = ++ (u32)VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(rxdp->control_0); ++ rxd_info->rth_value = ++ (u32)VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(rxdp->control_1); ++} ++ ++/** ++ * vxge_hw_ring_rxd_private_get - Get driver private per-descriptor data ++ * of 1b mode 3b mode ring. ++ * @rxdh: Descriptor handle. ++ * ++ * Returns: private driver info associated with the descriptor. ++ * driver requests per-descriptor space via vxge_hw_ring_attr. ++ * ++ */ ++static inline void *vxge_hw_ring_rxd_private_get(void *rxdh) ++{ ++ struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; ++ return (void *)(size_t)rxdp->host_control; ++} ++ ++ ++ ++/** ++ * vxge_hw_fifo_txdl_cksum_set_bits - Offload checksum. ++ * @txdlh: Descriptor handle. ++ * @cksum_bits: Specifies which checksums are to be offloaded: IPv4, ++ * and/or TCP and/or UDP. ++ * ++ * Ask Titan to calculate IPv4 & transport checksums for _this_ transmit ++ * descriptor. ++ * This API is part of the preparation of the transmit descriptor for posting ++ * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include ++ * vxge_hw_fifo_txdl_mss_set(), vxge_hw_fifo_txdl_buffer_set_aligned(), ++ * and vxge_hw_fifo_txdl_buffer_set(). ++ * All these APIs fill in the fields of the fifo descriptor, ++ * in accordance with the Titan specification. ++ * ++ */ ++static inline void vxge_hw_fifo_txdl_cksum_set_bits(void *txdlh, u64 cksum_bits) ++{ ++ struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh; ++ txdp->control_1 |= cksum_bits; ++} ++ ++/** ++ * vxge_hw_fifo_txdl_mss_set - Set MSS. ++ * @txdlh: Descriptor handle. ++ * @mss: MSS size for _this_ TCP connection. Passed by TCP stack down to the ++ * driver, which in turn inserts the MSS into the @txdlh. ++ * ++ * This API is part of the preparation of the transmit descriptor for posting ++ * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include ++ * vxge_hw_fifo_txdl_buffer_set(), vxge_hw_fifo_txdl_buffer_set_aligned(), ++ * and vxge_hw_fifo_txdl_cksum_set_bits(). ++ * All these APIs fill in the fields of the fifo descriptor, ++ * in accordance with the Titan specification. ++ * ++ */ ++static inline void vxge_hw_fifo_txdl_mss_set(void *txdlh, int mss) ++{ ++ struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh; ++ ++ txdp->control_0 |= VXGE_HW_FIFO_TXD_LSO_EN; ++ txdp->control_0 |= VXGE_HW_FIFO_TXD_LSO_MSS(mss); ++} ++ ++/** ++ * vxge_hw_fifo_txdl_vlan_set - Set VLAN tag. ++ * @txdlh: Descriptor handle. ++ * @vlan_tag: 16bit VLAN tag. ++ * ++ * Insert VLAN tag into specified transmit descriptor. ++ * The actual insertion of the tag into outgoing frame is done by the hardware. ++ */ ++static inline void vxge_hw_fifo_txdl_vlan_set(void *txdlh, u16 vlan_tag) ++{ ++ struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh; ++ ++ txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_ENABLE; ++ txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_TAG(vlan_tag); ++} ++ ++/** ++ * vxge_hw_fifo_txdl_private_get - Retrieve per-descriptor private data. ++ * @txdlh: Descriptor handle. ++ * ++ * Retrieve per-descriptor private data. ++ * Note that driver requests per-descriptor space via ++ * struct vxge_hw_fifo_attr passed to ++ * vxge_hw_vpath_open(). ++ * ++ * Returns: private driver data associated with the descriptor. ++ */ ++static inline void *vxge_hw_fifo_txdl_private_get(void *txdlh) ++{ ++ struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh; ++ ++ return (void *)(size_t)txdp->host_control; ++} ++ ++/** ++ * struct vxge_hw_ring_attr - Ring open "template". ++ * @callback: Ring completion callback. HW invokes the callback when there ++ * are new completions on that ring. In many implementations ++ * the @callback executes in the hw interrupt context. ++ * @rxd_init: Ring's descriptor-initialize callback. ++ * See vxge_hw_ring_rxd_init_f{}. ++ * If not NULL, HW invokes the callback when opening ++ * the ring. ++ * @rxd_term: Ring's descriptor-terminate callback. If not NULL, ++ * HW invokes the callback when closing the corresponding ring. ++ * See also vxge_hw_ring_rxd_term_f{}. ++ * @userdata: User-defined "context" of _that_ ring. Passed back to the ++ * user as one of the @callback, @rxd_init, and @rxd_term arguments. ++ * @per_rxd_space: If specified (i.e., greater than zero): extra space ++ * reserved by HW per each receive descriptor. ++ * Can be used to store ++ * and retrieve on completion, information specific ++ * to the driver. ++ * ++ * Ring open "template". User fills the structure with ring ++ * attributes and passes it to vxge_hw_vpath_open(). ++ */ ++struct vxge_hw_ring_attr { ++ enum vxge_hw_status (*callback)( ++ struct __vxge_hw_ring *ringh, ++ void *rxdh, ++ u8 t_code, ++ void *userdata); ++ ++ enum vxge_hw_status (*rxd_init)( ++ void *rxdh, ++ void *userdata); ++ ++ void (*rxd_term)( ++ void *rxdh, ++ enum vxge_hw_rxd_state state, ++ void *userdata); ++ ++ void *userdata; ++ u32 per_rxd_space; ++}; ++ ++/** ++ * function vxge_hw_fifo_callback_f - FIFO callback. ++ * @vpath_handle: Virtual path whose Fifo "containing" 1 or more completed ++ * descriptors. ++ * @txdlh: First completed descriptor. ++ * @txdl_priv: Pointer to per txdl space allocated ++ * @t_code: Transfer code, as per Titan User Guide. ++ * Returned by HW. ++ * @host_control: Opaque 64bit data stored by driver inside the Titan ++ * descriptor prior to posting the latter on the fifo ++ * via vxge_hw_fifo_txdl_post(). The @host_control is returned ++ * as is to the driver with each completed descriptor. ++ * @userdata: Opaque per-fifo data specified at fifo open ++ * time, via vxge_hw_vpath_open(). ++ * ++ * Fifo completion callback (type declaration). A single per-fifo ++ * callback is specified at fifo open time, via ++ * vxge_hw_vpath_open(). Typically gets called as part of the processing ++ * of the Interrupt Service Routine. ++ * ++ * Fifo callback gets called by HW if, and only if, there is at least ++ * one new completion on a given fifo. Upon processing the first @txdlh driver ++ * is _supposed_ to continue consuming completions using: ++ * - vxge_hw_fifo_txdl_next_completed() ++ * ++ * Note that failure to process new completions in a timely fashion ++ * leads to VXGE_HW_INF_OUT_OF_DESCRIPTORS condition. ++ * ++ * Non-zero @t_code means failure to process transmit descriptor. ++ * ++ * In the "transmit" case the failure could happen, for instance, when the ++ * link is down, in which case Titan completes the descriptor because it ++ * is not able to send the data out. ++ * ++ * For details please refer to Titan User Guide. ++ * ++ * See also: vxge_hw_fifo_txdl_next_completed(), vxge_hw_fifo_txdl_term_f{}. ++ */ ++/** ++ * function vxge_hw_fifo_txdl_term_f - Terminate descriptor callback. ++ * @txdlh: First completed descriptor. ++ * @txdl_priv: Pointer to per txdl space allocated ++ * @state: One of the enum vxge_hw_txdl_state{} enumerated states. ++ * @userdata: Per-fifo user data (a.k.a. context) specified at ++ * fifo open time, via vxge_hw_vpath_open(). ++ * ++ * Terminate descriptor callback. Unless NULL is specified in the ++ * struct vxge_hw_fifo_attr{} structure passed to vxge_hw_vpath_open()), ++ * HW invokes the callback as part of closing fifo, prior to ++ * de-allocating the ring and associated data structures ++ * (including descriptors). ++ * driver should utilize the callback to (for instance) unmap ++ * and free DMA data buffers associated with the posted (state = ++ * VXGE_HW_TXDL_STATE_POSTED) descriptors, ++ * as well as other relevant cleanup functions. ++ * ++ * See also: struct vxge_hw_fifo_attr{} ++ */ ++/** ++ * struct vxge_hw_fifo_attr - Fifo open "template". ++ * @callback: Fifo completion callback. HW invokes the callback when there ++ * are new completions on that fifo. In many implementations ++ * the @callback executes in the hw interrupt context. ++ * @txdl_term: Fifo's descriptor-terminate callback. If not NULL, ++ * HW invokes the callback when closing the corresponding fifo. ++ * See also vxge_hw_fifo_txdl_term_f{}. ++ * @userdata: User-defined "context" of _that_ fifo. Passed back to the ++ * user as one of the @callback, and @txdl_term arguments. ++ * @per_txdl_space: If specified (i.e., greater than zero): extra space ++ * reserved by HW per each transmit descriptor. Can be used to ++ * store, and retrieve on completion, information specific ++ * to the driver. ++ * ++ * Fifo open "template". User fills the structure with fifo ++ * attributes and passes it to vxge_hw_vpath_open(). ++ */ ++struct vxge_hw_fifo_attr { ++ ++ enum vxge_hw_status (*callback)( ++ struct __vxge_hw_fifo *fifo_handle, ++ void *txdlh, ++ enum vxge_hw_fifo_tcode t_code, ++ void *userdata, ++ struct sk_buff ***skb_ptr, ++ int nr_skb, int *more); ++ ++ void (*txdl_term)( ++ void *txdlh, ++ enum vxge_hw_txdl_state state, ++ void *userdata); ++ ++ void *userdata; ++ u32 per_txdl_space; ++}; ++ ++/** ++ * struct vxge_hw_vpath_attr - Attributes of virtual path ++ * @vp_id: Identifier of Virtual Path ++ * @ring_attr: Attributes of ring for non-offload receive ++ * @fifo_attr: Attributes of fifo for non-offload transmit ++ * ++ * Attributes of virtual path. This structure is passed as parameter ++ * to the vxge_hw_vpath_open() routine to set the attributes of ring and fifo. ++ */ ++struct vxge_hw_vpath_attr { ++ u32 vp_id; ++ struct vxge_hw_ring_attr ring_attr; ++ struct vxge_hw_fifo_attr fifo_attr; ++}; ++ ++enum vxge_hw_status ++__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev, ++ struct __vxge_hw_blockpool *blockpool, ++ u32 pool_size); ++ ++void ++__vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool); ++ ++struct __vxge_hw_blockpool_entry * ++__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *hldev, ++ u32 size); ++ ++void ++__vxge_hw_blockpool_block_free(struct __vxge_hw_device *hldev, ++ struct __vxge_hw_blockpool_entry *entry); ++ ++void * ++__vxge_hw_blockpool_malloc(struct __vxge_hw_device *hldev, ++ struct vxge_hw_mempool_dma *dma_object); ++ ++void ++__vxge_hw_blockpool_free(struct __vxge_hw_device *hldev, ++ void *memblock, ++ u32 size, ++ struct vxge_hw_mempool_dma *dma_object); ++ ++enum vxge_hw_status ++__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config); ++ ++enum vxge_hw_status ++__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config); ++ ++enum vxge_hw_status ++vxge_hw_mgmt_device_config(struct __vxge_hw_device *devh, ++ struct vxge_hw_device_config *dev_config, int size); ++ ++enum vxge_hw_status __devinit vxge_hw_device_hw_info_get( ++ void __iomem *bar0, ++ struct vxge_hw_device_hw_info *hw_info); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_fw_ver_get( ++ u32 vp_id, ++ struct vxge_hw_vpath_reg __iomem *vpath_reg, ++ struct vxge_hw_device_hw_info *hw_info); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_card_info_get( ++ u32 vp_id, ++ struct vxge_hw_vpath_reg __iomem *vpath_reg, ++ struct vxge_hw_device_hw_info *hw_info); ++ ++enum vxge_hw_status __devinit vxge_hw_device_config_default_get( ++ struct vxge_hw_device_config *device_config); ++ ++/** ++ * vxge_hw_device_link_state_get - Get link state. ++ * @devh: HW device handle. ++ * ++ * Get link state. ++ * Returns: link state. ++ */ ++static inline ++enum vxge_hw_device_link_state vxge_hw_device_link_state_get( ++ struct __vxge_hw_device *devh) ++{ ++ return devh->link_state; ++} ++ ++void vxge_hw_device_terminate(struct __vxge_hw_device *devh); ++ ++const u8 * ++vxge_hw_device_serial_number_get(struct __vxge_hw_device *devh); ++ ++u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *devh); ++ ++const u8 * ++vxge_hw_device_product_name_get(struct __vxge_hw_device *devh); ++ ++enum vxge_hw_status __devinit vxge_hw_device_initialize( ++ struct __vxge_hw_device **devh, ++ struct vxge_hw_device_attr *attr, ++ struct vxge_hw_device_config *device_config, ++ u8 titan1); ++ ++enum vxge_hw_status vxge_hw_device_getpause_data( ++ struct __vxge_hw_device *devh, ++ u32 port, ++ u32 *tx, ++ u32 *rx); ++ ++enum vxge_hw_status vxge_hw_device_setpause_data( ++ struct __vxge_hw_device *devh, ++ u32 port, ++ u32 tx, ++ u32 rx); ++ ++ ++ ++static inline void *vxge_os_dma_malloc(struct pci_dev *pdev, ++ unsigned long size, ++ struct pci_dev **p_dmah, ++ struct pci_dev **p_dma_acch) ++{ ++ gfp_t flags; ++ void *vaddr; ++ unsigned long misaligned = 0; ++ *p_dma_acch = *p_dmah = NULL; ++ ++ flags = in_interrupt() ? GFP_ATOMIC : GFP_KERNEL; ++ ++ size += VXGE_CACHE_LINE_SIZE; ++ ++ vaddr = kmalloc((size), flags); ++ if (vaddr == NULL) ++ return vaddr; ++ misaligned = (unsigned long)VXGE_ALIGN((unsigned long)vaddr, ++ VXGE_CACHE_LINE_SIZE); ++ *(unsigned long *)p_dma_acch = misaligned; ++ vaddr = (void *)((u8 *)vaddr + misaligned); ++ return vaddr; ++} ++ ++static inline void vxge_os_dma_free(struct pci_dev *pdev, const void *vaddr, ++ struct pci_dev **p_dma_acch) ++{ ++ unsigned long misaligned = *(unsigned long *)p_dma_acch; ++ u8 *tmp = (u8 *)vaddr; ++ tmp -= misaligned; ++ kfree((void *)tmp); ++} ++ ++static inline int vxge_do_pci_dma_mapping_error(struct pci_dev *pdev, ++ dma_addr_t dma_addr) ++{ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 17)) ++ return dma_addr == 0; ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)) ++ return pci_dma_mapping_error(dma_addr); ++#else ++ return pci_dma_mapping_error(pdev, dma_addr); ++#endif ++} ++ ++/* ++ * __vxge_hw_mempool_item_priv - will return pointer on per item private space ++ */ ++static inline void* ++__vxge_hw_mempool_item_priv( ++ struct vxge_hw_mempool *mempool, ++ u32 memblock_idx, ++ void *item, ++ u32 *memblock_item_idx) ++{ ++ ptrdiff_t offset; ++ void *memblock = mempool->memblocks_arr[memblock_idx]; ++ ++ ++ offset = (u32)((u8 *)item - (u8 *)memblock); ++ vxge_assert(offset >= 0 && (u32)offset < mempool->memblock_size); ++ ++ (*memblock_item_idx) = (u32) offset / mempool->item_size; ++ vxge_assert((*memblock_item_idx) < mempool->items_per_memblock); ++ ++ return (u8 *)mempool->memblocks_priv_arr[memblock_idx] + ++ (*memblock_item_idx) * mempool->items_priv_size; ++} ++ ++enum vxge_hw_status ++__vxge_hw_mempool_grow( ++ struct vxge_hw_mempool *mempool, ++ u32 num_allocate, ++ u32 *num_allocated); ++ ++struct vxge_hw_mempool* ++__vxge_hw_mempool_create( ++ struct __vxge_hw_device *devh, ++ u32 memblock_size, ++ u32 item_size, ++ u32 private_size, ++ u32 items_initial, ++ u32 items_max, ++ struct vxge_hw_mempool_cbs *mp_callback, ++ void *userdata); ++ ++struct __vxge_hw_channel* ++__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph, ++ enum __vxge_hw_channel_type type, u32 length, ++ u32 per_dtr_space, void *userdata); ++ ++void ++__vxge_hw_channel_free( ++ struct __vxge_hw_channel *channel); ++ ++enum vxge_hw_status ++__vxge_hw_channel_initialize( ++ struct __vxge_hw_channel *channel); ++ ++enum vxge_hw_status ++__vxge_hw_channel_reset( ++ struct __vxge_hw_channel *channel); ++ ++/* ++ * __vxge_hw_fifo_txdl_priv - Return the max fragments allocated ++ * for the fifo. ++ * @fifo: Fifo ++ * @txdp: Poniter to a TxD ++ */ ++static inline struct __vxge_hw_fifo_txdl_priv * ++__vxge_hw_fifo_txdl_priv( ++ struct __vxge_hw_fifo *fifo, ++ struct vxge_hw_fifo_txd *txdp) ++{ ++ return (struct __vxge_hw_fifo_txdl_priv *) ++ (((char *)((ulong)txdp->host_control)) + ++ fifo->per_txdl_space); ++} ++ ++enum vxge_hw_status vxge_hw_vpath_open( ++ struct __vxge_hw_device *devh, ++ struct vxge_hw_vpath_attr *attr, ++ struct __vxge_hw_vpath_handle **vpath_handle); ++ ++void vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id); ++ ++enum vxge_hw_status ++__vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog); ++ ++enum vxge_hw_status vxge_hw_vpath_close( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++enum vxge_hw_status ++vxge_hw_vpath_reset( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++enum vxge_hw_status ++vxge_hw_vpath_recover_from_reset( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++void ++vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp); ++ ++enum vxge_hw_status ++vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ringh); ++ ++enum vxge_hw_status vxge_hw_vpath_mtu_set( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u32 new_mtu); ++ ++enum vxge_hw_status vxge_hw_vpath_stats_enable( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_stats_access( ++ struct __vxge_hw_virtualpath *vpath, ++ u32 operation, ++ u32 offset, ++ u64 *stat); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_xmac_tx_stats_get( ++ struct __vxge_hw_virtualpath *vpath, ++ struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_xmac_rx_stats_get( ++ struct __vxge_hw_virtualpath *vpath, ++ struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_stats_get( ++ struct __vxge_hw_virtualpath *vpath, ++ struct vxge_hw_vpath_stats_hw_info *hw_stats); ++ ++void ++vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp); ++ ++enum vxge_hw_status ++__vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config); ++ ++void ++__vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev); ++ ++enum vxge_hw_status ++__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg); ++ ++enum vxge_hw_status ++__vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg, ++ struct vxge_hw_vpath_reg __iomem *vpath_reg); ++ ++enum vxge_hw_status ++__vxge_hw_device_register_poll( ++ void __iomem *reg, ++ u64 mask, u32 max_millis); ++ ++#ifndef readq ++static inline u64 readq(void __iomem *addr) ++{ ++ u64 ret = 0; ++ ret = readl(addr + 4); ++ ret <<= 32; ++ ret |= readl(addr); ++ ++ return ret; ++} ++#endif ++ ++#ifndef writeq ++static inline void writeq(u64 val, void __iomem *addr) ++{ ++ writel((u32) (val), addr); ++ writel((u32) (val >> 32), (addr + 4)); ++} ++#endif ++ ++static inline void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr) ++{ ++ writel(val, addr + 4); ++} ++ ++static inline void __vxge_hw_pio_mem_write32_lower(u32 val, void __iomem *addr) ++{ ++ writel(val, addr); ++} ++ ++static inline enum vxge_hw_status ++__vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr, ++ u64 mask, u32 max_millis) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr); ++ wmb(); ++ __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr); ++ wmb(); ++ ++ status = __vxge_hw_device_register_poll(addr, mask, max_millis); ++ return status; ++} ++ ++struct vxge_hw_toc_reg __iomem * ++__vxge_hw_device_toc_get(void __iomem *bar0); ++ ++enum vxge_hw_status ++__vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev); ++ ++void ++__vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev); ++ ++enum vxge_hw_status ++vxge_hw_device_flick_link_led(struct __vxge_hw_device *devh, u64 on_off); ++ ++enum vxge_hw_status ++__vxge_hw_device_initialize(struct __vxge_hw_device *hldev); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_pci_read( ++ struct __vxge_hw_virtualpath *vpath, ++ u32 phy_func_0, ++ u32 offset, ++ u32 *val); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_addr_get( ++ u32 vp_id, ++ struct vxge_hw_vpath_reg __iomem *vpath_reg, ++ u8 (macaddr)[ETH_ALEN], ++ u8 (macaddr_mask)[ETH_ALEN]); ++ ++u32 ++__vxge_hw_vpath_func_id_get( ++ u32 vp_id, struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath); ++ ++enum vxge_hw_status ++vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask); ++ ++/** ++ * vxge_debug ++ * @level: level of debug verbosity. ++ * @mask: mask for the debug ++ * @buf: Circular buffer for tracing ++ * @fmt: printf like format string ++ * ++ * Provides logging facilities. Can be customized on per-module ++ * basis or/and with debug levels. Input parameters, except ++ * module and level, are the same as posix printf. This function ++ * may be compiled out if DEBUG macro was never defined. ++ * See also: enum vxge_debug_level{}. ++ */ ++ ++#define vxge_trace_aux(level, mask, fmt, ...) \ ++{\ ++ vxge_os_vaprintf(level, mask, fmt, __VA_ARGS__);\ ++} ++ ++#define vxge_debug(module, level, mask, fmt, ...) { \ ++if ((level >= VXGE_TRACE && ((module & VXGE_DEBUG_TRACE_MASK) == module)) || \ ++ (level >= VXGE_ERR && ((module & VXGE_DEBUG_ERR_MASK) == module))) {\ ++ if ((mask & VXGE_DEBUG_MASK) == mask)\ ++ vxge_trace_aux(level, mask, fmt, __VA_ARGS__); \ ++} \ ++} ++ ++#if (VXGE_COMPONENT_LL & VXGE_DEBUG_MODULE_MASK) ++#define vxge_debug_ll(level, mask, fmt, ...) \ ++{\ ++ vxge_debug(VXGE_COMPONENT_LL, level, mask, fmt, __VA_ARGS__);\ ++} ++ ++#else ++#define vxge_debug_ll(level, mask, fmt, ...) ++#endif ++ ++enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set( ++ struct __vxge_hw_vpath_handle **vpath_handles, ++ u32 vpath_count, ++ u8 *mtable, ++ u8 *itable, ++ u32 itable_size); ++ ++enum vxge_hw_status vxge_hw_vpath_rts_rth_set( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ enum vxge_hw_rth_algoritms algorithm, ++ struct vxge_hw_rth_hash_types *hash_type, ++ u16 bucket_size); ++ ++enum vxge_hw_status ++__vxge_hw_device_is_privilaged(u32 host_type, u32 func_id); ++ ++/** ++ * vxge_hw_vpath_stats_clear - Clear all the statistics of vpath ++ * @vpath_handle: Virtual path handle. ++ * ++ * Clear the statistics of the given vpath. ++ * ++ */ ++static inline ++enum vxge_hw_status vxge_hw_vpath_stats_clear( ++ struct __vxge_hw_vpath_handle *vpath_handle) ++{ ++ u64 stat; ++ ++ return __vxge_hw_vpath_stats_access( ++ vpath_handle->vpath, ++ VXGE_HW_STATS_OP_CLEAR_ALL_VPATH_STATS, ++ 0, ++ &stat); ++} ++ ++#endif +diff -r 158b6e53275e drivers/net/vxge/vxge-ethtool.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/vxge/vxge-ethtool.c Wed Aug 05 11:58:00 2009 +0100 +@@ -0,0 +1,1412 @@ ++/****************************************************************************** ++ * vxge-ethtool.c: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O ++ * Virtualized Server Adapter. ++ * Copyright(c) 2002-2009 Neterion Inc. ++ ******************************************************************************/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vxge-main.h" ++#include "vxge-kcompat.h" ++#include "vxge-ethtool.h" ++ ++/** ++ * vxge_ethtool_sset - Sets different link parameters. ++ * @dev: device pointer. ++ * @info: pointer to the structure with parameters given by ethtool to set ++ * link information. ++ * ++ * The function sets different link parameters provided by the user onto ++ * the NIC. ++ * Return value: ++ * 0 on success. ++ */ ++ ++static int vxge_ethtool_sset(struct net_device *dev, struct ethtool_cmd *info) ++{ ++ /* We currently only support 10Gb/FULL */ ++ if ((info->autoneg == AUTONEG_ENABLE) || ++ (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL)) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++/** ++ * vxge_ethtool_gset - Return link specific information. ++ * @dev: device pointer. ++ * @info: pointer to the structure with parameters given by ethtool ++ * to return link information. ++ * ++ * Returns link specific information like speed, duplex etc.. to ethtool. ++ * Return value : ++ * return 0 on success. ++ */ ++static int vxge_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info) ++{ ++ info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); ++ info->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE); ++ info->port = PORT_FIBRE; ++ ++ info->transceiver = XCVR_EXTERNAL; ++ ++ if (netif_carrier_ok(dev)) { ++ info->speed = SPEED_10000; ++ info->duplex = DUPLEX_FULL; ++ } else { ++ info->speed = -1; ++ info->duplex = -1; ++ } ++ ++ info->autoneg = AUTONEG_DISABLE; ++ return 0; ++} ++ ++/** ++ * vxge_ethtool_gdrvinfo - Returns driver specific information. ++ * @dev: device pointer. ++ * @info: pointer to the structure with parameters given by ethtool to ++ * return driver information. ++ * ++ * Returns driver specefic information like name, version etc.. to ethtool. ++ */ ++static void vxge_ethtool_gdrvinfo(struct net_device *dev, ++ struct ethtool_drvinfo *info) ++{ ++ struct vxgedev *vdev; ++ vdev = (struct vxgedev *)netdev_priv(dev); ++ strlcpy(info->driver, VXGE_DRIVER_NAME, sizeof(VXGE_DRIVER_NAME)); ++ strlcpy(info->version, DRV_VERSION, sizeof(DRV_VERSION)); ++ strlcpy(info->fw_version, vdev->fw_version, VXGE_HW_FW_STRLEN); ++ strlcpy(info->bus_info, pci_name(vdev->pdev), sizeof(info->bus_info)); ++ info->regdump_len = sizeof(struct vxge_hw_vpath_reg) ++ * vdev->no_of_vpath; ++ ++ info->n_stats = STAT_LEN; ++} ++ ++/** ++ * vxge_ethtool_idnic - To physically identify the nic on the system. ++ * @dev : device pointer. ++ * @id : pointer to the structure with identification parameters given by ++ * ethtool. ++ * ++ * Used to physically identify the NIC on the system. ++ * The Link LED will blink for a time specified by the user. ++ * Return value: ++ * 0 on success ++ */ ++static int vxge_ethtool_idnic(struct net_device *dev, u32 data) ++{ ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ struct __vxge_hw_device *hldev = (struct __vxge_hw_device *) ++ pci_get_drvdata(vdev->pdev); ++ ++ vxge_hw_device_flick_link_led(hldev, VXGE_FLICKER_ON); ++ msleep_interruptible(data ? (data * HZ) : VXGE_MAX_FLICKER_TIME); ++ vxge_hw_device_flick_link_led(hldev, VXGE_FLICKER_OFF); ++ ++ return 0; ++} ++ ++/** ++ * vxge_ethtool_getpause_data - Pause frame frame generation and reception. ++ * @dev : device pointer. ++ * @ep : pointer to the structure with pause parameters given by ethtool. ++ * Description: ++ * Returns the Pause frame generation and reception capability of the NIC. ++ * Return value: ++ * void ++ */ ++static void vxge_ethtool_getpause_data(struct net_device *dev, ++ struct ethtool_pauseparam *ep) ++{ ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ struct __vxge_hw_device *hldev = (struct __vxge_hw_device *) ++ pci_get_drvdata(vdev->pdev); ++ ++ vxge_hw_device_getpause_data(hldev, 0, &ep->tx_pause, &ep->rx_pause); ++} ++ ++/** ++ * vxge_ethtool_setpause_data - set/reset pause frame generation. ++ * @dev : device pointer. ++ * @ep : pointer to the structure with pause parameters given by ethtool. ++ * Description: ++ * It can be used to set or reset Pause frame generation or reception ++ * support of the NIC. ++ * Return value: ++ * int, returns 0 on Success ++ */ ++static int vxge_ethtool_setpause_data(struct net_device *dev, ++ struct ethtool_pauseparam *ep) ++{ ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ struct __vxge_hw_device *hldev = (struct __vxge_hw_device *) ++ pci_get_drvdata(vdev->pdev); ++ ++ vxge_hw_device_setpause_data(hldev, 0, ep->tx_pause, ep->rx_pause); ++ ++ vdev->config.tx_pause_enable = ep->tx_pause; ++ vdev->config.rx_pause_enable = ep->rx_pause; ++ ++ return 0; ++} ++ ++static int vxge_ethtool_get_stats_count(struct net_device *dev) ++{ ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ ++ int soft_stat_cnt = VXGE_SW_STATS_LEN; ++ ++ if (!vdev->config.lro_enable || ++ (vdev->config.lro_enable == VXGE_HW_GRO_ENABLE)) ++ soft_stat_cnt -= SOFT_LRO_STAT_CNT; ++ ++ ++ return VXGE_TITLE_LEN + ++ (vdev->max_config_port * VXGE_HW_AGGR_STATS_LEN) + ++ (vdev->max_config_port * VXGE_HW_PORT_STATS_LEN) + ++ (vdev->no_of_vpath * VXGE_HW_VPATH_TX_STATS_LEN) + ++ (vdev->no_of_vpath * VXGE_HW_VPATH_RX_STATS_LEN) + ++ ++ (vdev->no_of_vpath * soft_stat_cnt) + ++ DRIVER_STAT_LEN; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) ++static int vxge_ethtool_get_sset_count(struct net_device *dev, int sset) ++{ ++ switch (sset) { ++ case ETH_SS_STATS: ++ return vxge_ethtool_get_stats_count(dev); ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++#endif ++ ++static void vxge_get_ethtool_stats(struct net_device *dev, ++ struct ethtool_stats *estats, u64 *tmp_stats) ++{ ++ int j, k, count; ++ enum vxge_hw_status status; ++ enum vxge_hw_status swstatus; ++ struct vxge_vpath *vpath = NULL; ++ ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ struct __vxge_hw_device *hldev = vdev->devh; ++ struct vxge_hw_xmac_stats *xmac_stats; ++ struct vxge_hw_device_stats_sw_info *sw_stats; ++ struct vxge_hw_device_stats_hw_info *hw_stats; ++ ++ ++ u64 *ptr = tmp_stats; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) ++ count = vxge_ethtool_get_stats_count(dev); ++#else ++ count = vxge_ethtool_get_sset_count(dev, ETH_SS_STATS); ++#endif ++ memset(tmp_stats, 0, count * sizeof(u64)); ++ ++ ++ ++ xmac_stats = kzalloc(sizeof(struct vxge_hw_xmac_stats), GFP_KERNEL); ++ if (xmac_stats == NULL) { ++ vxge_debug_init(VXGE_ERR, ++ "%s : %d Memory Allocation failed for xmac_stats", ++ __func__, __LINE__); ++ return; ++ } ++ ++ sw_stats = kzalloc(sizeof(struct vxge_hw_device_stats_sw_info), ++ GFP_KERNEL); ++ if (sw_stats == NULL) { ++ kfree(xmac_stats); ++ vxge_debug_init(VXGE_ERR, ++ "%s : %d Memory Allocation failed for sw_stats", ++ __func__, __LINE__); ++ return; ++ } ++ ++ hw_stats = kzalloc(sizeof(struct vxge_hw_device_stats_hw_info), ++ GFP_KERNEL); ++ if (hw_stats == NULL) { ++ kfree(xmac_stats); ++ kfree(sw_stats); ++ vxge_debug_init(VXGE_ERR, ++ "%s : %d Memory Allocation failed for hw_stats", ++ __func__, __LINE__); ++ return; ++ } ++ ++ *ptr++ = 0; ++ status = vxge_hw_device_xmac_stats_get(hldev, xmac_stats); ++ if (status != VXGE_HW_OK) { ++ if (status != VXGE_HW_ERR_PRIVILAGED_OPEARATION) { ++ vxge_debug_init(VXGE_ERR, ++ "%s : %d Failure in getting xmac stats", ++ __func__, __LINE__); ++ } ++ } ++ swstatus = vxge_hw_driver_stats_get(hldev, sw_stats); ++ if (swstatus != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s : %d Failure in getting sw stats", ++ __func__, __LINE__); ++ } ++ if (vxge_hw_device_hw_stats_enable(hldev) != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s : %d hw_stats_get error\n", ++ __func__, __LINE__); ++ } else { ++ status = vxge_hw_device_stats_get(hldev, hw_stats); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s : %d hw_stats_get error", ++ __func__, __LINE__); ++ } ++ } ++ ++ ++ ++ for (k = 0; k < vdev->no_of_vpath; k++) { ++ struct vxge_hw_vpath_stats_hw_info *vpath_info; ++ ++ vpath = &vdev->vpaths[k]; ++ j = vpath->device_id; ++ vpath_info = hw_stats->vpath_info[j]; ++ if (!vpath_info) { ++ memset(ptr, 0, (VXGE_HW_VPATH_TX_STATS_LEN + ++ VXGE_HW_VPATH_RX_STATS_LEN) * sizeof(u64)); ++ ptr += (VXGE_HW_VPATH_TX_STATS_LEN + ++ VXGE_HW_VPATH_RX_STATS_LEN); ++ continue; ++ } ++ ++ *ptr++ = vpath_info->tx_stats.tx_ttl_eth_frms; ++ *ptr++ = vpath_info->tx_stats.tx_ttl_eth_octets; ++ *ptr++ = vpath_info->tx_stats.tx_data_octets; ++ *ptr++ = vpath_info->tx_stats.tx_mcast_frms; ++ *ptr++ = vpath_info->tx_stats.tx_bcast_frms; ++ *ptr++ = vpath_info->tx_stats.tx_ucast_frms; ++ *ptr++ = vpath_info->tx_stats.tx_tagged_frms; ++ *ptr++ = vpath_info->tx_stats.tx_vld_ip; ++ *ptr++ = vpath_info->tx_stats.tx_vld_ip_octets; ++ *ptr++ = vpath_info->tx_stats.tx_icmp; ++ *ptr++ = vpath_info->tx_stats.tx_tcp; ++ *ptr++ = vpath_info->tx_stats.tx_rst_tcp; ++ *ptr++ = vpath_info->tx_stats.tx_udp; ++ *ptr++ = vpath_info->tx_stats.tx_unknown_protocol; ++ *ptr++ = vpath_info->tx_stats.tx_lost_ip; ++ *ptr++ = vpath_info->tx_stats.tx_parse_error; ++ *ptr++ = vpath_info->tx_stats.tx_tcp_offload; ++ *ptr++ = vpath_info->tx_stats.tx_retx_tcp_offload; ++ *ptr++ = vpath_info->tx_stats.tx_lost_ip_offload; ++ *ptr++ = vpath_info->rx_stats.rx_ttl_eth_frms; ++ *ptr++ = vpath_info->rx_stats.rx_vld_frms; ++ *ptr++ = vpath_info->rx_stats.rx_offload_frms; ++ *ptr++ = vpath_info->rx_stats.rx_ttl_eth_octets; ++ *ptr++ = vpath_info->rx_stats.rx_data_octets; ++ *ptr++ = vpath_info->rx_stats.rx_offload_octets; ++ *ptr++ = vpath_info->rx_stats.rx_vld_mcast_frms; ++ *ptr++ = vpath_info->rx_stats.rx_vld_bcast_frms; ++ *ptr++ = vpath_info->rx_stats.rx_accepted_ucast_frms; ++ *ptr++ = vpath_info->rx_stats.rx_accepted_nucast_frms; ++ *ptr++ = vpath_info->rx_stats.rx_tagged_frms; ++ *ptr++ = vpath_info->rx_stats.rx_long_frms; ++ *ptr++ = vpath_info->rx_stats.rx_usized_frms; ++ *ptr++ = vpath_info->rx_stats.rx_osized_frms; ++ *ptr++ = vpath_info->rx_stats.rx_frag_frms; ++ *ptr++ = vpath_info->rx_stats.rx_jabber_frms; ++ *ptr++ = vpath_info->rx_stats.rx_ttl_64_frms; ++ *ptr++ = vpath_info->rx_stats.rx_ttl_65_127_frms; ++ *ptr++ = vpath_info->rx_stats.rx_ttl_128_255_frms; ++ *ptr++ = vpath_info->rx_stats.rx_ttl_256_511_frms; ++ *ptr++ = vpath_info->rx_stats.rx_ttl_512_1023_frms; ++ *ptr++ = vpath_info->rx_stats.rx_ttl_1024_1518_frms; ++ *ptr++ = vpath_info->rx_stats.rx_ttl_1519_4095_frms; ++ *ptr++ = vpath_info->rx_stats.rx_ttl_4096_8191_frms; ++ *ptr++ = vpath_info->rx_stats.rx_ttl_8192_max_frms; ++ *ptr++ = vpath_info->rx_stats.rx_ttl_gt_max_frms; ++ *ptr++ = vpath_info->rx_stats.rx_ip; ++ *ptr++ = vpath_info->rx_stats.rx_accepted_ip; ++ *ptr++ = vpath_info->rx_stats.rx_ip_octets; ++ *ptr++ = vpath_info->rx_stats.rx_err_ip; ++ *ptr++ = vpath_info->rx_stats.rx_icmp; ++ *ptr++ = vpath_info->rx_stats.rx_tcp; ++ *ptr++ = vpath_info->rx_stats.rx_udp; ++ *ptr++ = vpath_info->rx_stats.rx_err_tcp; ++ *ptr++ = vpath_info->rx_stats.rx_lost_frms; ++ *ptr++ = vpath_info->rx_stats.rx_lost_ip; ++ *ptr++ = vpath_info->rx_stats.rx_lost_ip_offload; ++ *ptr++ = vpath_info->rx_stats.rx_various_discard; ++ *ptr++ = vpath_info->rx_stats.rx_sleep_discard; ++ *ptr++ = vpath_info->rx_stats.rx_red_discard; ++ *ptr++ = vpath_info->rx_stats.rx_queue_full_discard; ++ *ptr++ = vpath_info->rx_stats.rx_mpa_ok_frms; ++ } ++ *ptr++ = 0; ++ for (k = 0; k < vdev->max_config_port; k++) { ++ *ptr++ = xmac_stats->aggr_stats[k].tx_frms; ++ *ptr++ = xmac_stats->aggr_stats[k].tx_data_octets; ++ *ptr++ = xmac_stats->aggr_stats[k].tx_mcast_frms; ++ *ptr++ = xmac_stats->aggr_stats[k].tx_bcast_frms; ++ *ptr++ = xmac_stats->aggr_stats[k].tx_discarded_frms; ++ *ptr++ = xmac_stats->aggr_stats[k].tx_errored_frms; ++ *ptr++ = xmac_stats->aggr_stats[k].rx_frms; ++ *ptr++ = xmac_stats->aggr_stats[k].rx_data_octets; ++ *ptr++ = xmac_stats->aggr_stats[k].rx_mcast_frms; ++ *ptr++ = xmac_stats->aggr_stats[k].rx_bcast_frms; ++ *ptr++ = xmac_stats->aggr_stats[k].rx_discarded_frms; ++ *ptr++ = xmac_stats->aggr_stats[k].rx_errored_frms; ++ *ptr++ = xmac_stats->aggr_stats[k].rx_unknown_slow_proto_frms; ++ } ++ *ptr++ = 0; ++ for (k = 0; k < vdev->max_config_port; k++) { ++ *ptr++ = xmac_stats->port_stats[k].tx_ttl_frms; ++ *ptr++ = xmac_stats->port_stats[k].tx_ttl_octets; ++ *ptr++ = xmac_stats->port_stats[k].tx_data_octets; ++ *ptr++ = xmac_stats->port_stats[k].tx_mcast_frms; ++ *ptr++ = xmac_stats->port_stats[k].tx_bcast_frms; ++ *ptr++ = xmac_stats->port_stats[k].tx_ucast_frms; ++ *ptr++ = xmac_stats->port_stats[k].tx_tagged_frms; ++ *ptr++ = xmac_stats->port_stats[k].tx_vld_ip; ++ *ptr++ = xmac_stats->port_stats[k].tx_vld_ip_octets; ++ *ptr++ = xmac_stats->port_stats[k].tx_icmp; ++ *ptr++ = xmac_stats->port_stats[k].tx_tcp; ++ *ptr++ = xmac_stats->port_stats[k].tx_rst_tcp; ++ *ptr++ = xmac_stats->port_stats[k].tx_udp; ++ *ptr++ = xmac_stats->port_stats[k].tx_parse_error; ++ *ptr++ = xmac_stats->port_stats[k].tx_unknown_protocol; ++ *ptr++ = xmac_stats->port_stats[k].tx_pause_ctrl_frms; ++ *ptr++ = xmac_stats->port_stats[k].tx_marker_pdu_frms; ++ *ptr++ = xmac_stats->port_stats[k].tx_lacpdu_frms; ++ *ptr++ = xmac_stats->port_stats[k].tx_drop_ip; ++ *ptr++ = xmac_stats->port_stats[k].tx_marker_resp_pdu_frms; ++ *ptr++ = xmac_stats->port_stats[k].tx_xgmii_char2_match; ++ *ptr++ = xmac_stats->port_stats[k].tx_xgmii_char1_match; ++ *ptr++ = xmac_stats->port_stats[k].tx_xgmii_column2_match; ++ *ptr++ = xmac_stats->port_stats[k].tx_xgmii_column1_match; ++ *ptr++ = xmac_stats->port_stats[k].tx_any_err_frms; ++ *ptr++ = xmac_stats->port_stats[k].tx_drop_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_ttl_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_vld_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_offload_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_ttl_octets; ++ *ptr++ = xmac_stats->port_stats[k].rx_data_octets; ++ *ptr++ = xmac_stats->port_stats[k].rx_offload_octets; ++ *ptr++ = xmac_stats->port_stats[k].rx_vld_mcast_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_vld_bcast_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_accepted_ucast_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_accepted_nucast_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_tagged_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_long_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_usized_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_osized_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_frag_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_jabber_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_ttl_64_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_ttl_65_127_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_ttl_128_255_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_ttl_256_511_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_ttl_512_1023_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_ttl_1024_1518_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_ttl_1519_4095_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_ttl_4096_8191_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_ttl_8192_max_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_ttl_gt_max_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_ip; ++ *ptr++ = xmac_stats->port_stats[k].rx_accepted_ip; ++ *ptr++ = xmac_stats->port_stats[k].rx_ip_octets; ++ *ptr++ = xmac_stats->port_stats[k].rx_err_ip; ++ *ptr++ = xmac_stats->port_stats[k].rx_icmp; ++ *ptr++ = xmac_stats->port_stats[k].rx_tcp; ++ *ptr++ = xmac_stats->port_stats[k].rx_udp; ++ *ptr++ = xmac_stats->port_stats[k].rx_err_tcp; ++ *ptr++ = xmac_stats->port_stats[k].rx_pause_count; ++ *ptr++ = xmac_stats->port_stats[k].rx_pause_ctrl_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_unsup_ctrl_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_fcs_err_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_in_rng_len_err_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_out_rng_len_err_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_drop_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_discarded_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_drop_ip; ++ *ptr++ = xmac_stats->port_stats[k].rx_drop_udp; ++ *ptr++ = xmac_stats->port_stats[k].rx_marker_pdu_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_lacpdu_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_unknown_pdu_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_marker_resp_pdu_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_fcs_discard; ++ *ptr++ = xmac_stats->port_stats[k].rx_illegal_pdu_frms; ++ *ptr++ = xmac_stats->port_stats[k].rx_switch_discard; ++ *ptr++ = xmac_stats->port_stats[k].rx_len_discard; ++ *ptr++ = xmac_stats->port_stats[k].rx_rpa_discard; ++ *ptr++ = xmac_stats->port_stats[k].rx_l2_mgmt_discard; ++ *ptr++ = xmac_stats->port_stats[k].rx_rts_discard; ++ *ptr++ = xmac_stats->port_stats[k].rx_trash_discard; ++ *ptr++ = xmac_stats->port_stats[k].rx_buff_full_discard; ++ *ptr++ = xmac_stats->port_stats[k].rx_red_discard; ++ *ptr++ = xmac_stats->port_stats[k].rx_xgmii_ctrl_err_cnt; ++ *ptr++ = xmac_stats->port_stats[k].rx_xgmii_data_err_cnt; ++ *ptr++ = xmac_stats->port_stats[k].rx_xgmii_char1_match; ++ *ptr++ = xmac_stats->port_stats[k].rx_xgmii_err_sym; ++ *ptr++ = xmac_stats->port_stats[k].rx_xgmii_column1_match; ++ *ptr++ = xmac_stats->port_stats[k].rx_xgmii_char2_match; ++ *ptr++ = xmac_stats->port_stats[k].rx_local_fault; ++ *ptr++ = xmac_stats->port_stats[k].rx_xgmii_column2_match; ++ *ptr++ = xmac_stats->port_stats[k].rx_jettison; ++ *ptr++ = xmac_stats->port_stats[k].rx_remote_fault; ++ } ++ ++ *ptr++ = 0; ++ for (k = 0; k < vdev->no_of_vpath; k++) { ++ struct vxge_hw_vpath_stats_sw_info *vpath_info; ++ ++ vpath = &vdev->vpaths[k]; ++ j = vpath->device_id; ++ vpath_info = (struct vxge_hw_vpath_stats_sw_info *) ++ &sw_stats->vpath_info[j]; ++ *ptr++ = vpath_info->soft_reset_cnt; ++ *ptr++ = vpath_info->error_stats.unknown_alarms; ++ *ptr++ = vpath_info->error_stats.network_sustained_fault; ++ *ptr++ = vpath_info->error_stats.network_sustained_ok; ++ *ptr++ = vpath_info->error_stats.kdfcctl_fifo0_overwrite; ++ *ptr++ = vpath_info->error_stats.kdfcctl_fifo0_poison; ++ *ptr++ = vpath_info->error_stats.kdfcctl_fifo0_dma_error; ++ *ptr++ = vpath_info->error_stats.dblgen_fifo0_overflow; ++ *ptr++ = vpath_info->error_stats.statsb_pif_chain_error; ++ *ptr++ = vpath_info->error_stats.statsb_drop_timeout; ++ *ptr++ = vpath_info->error_stats.target_illegal_access; ++ *ptr++ = vpath_info->error_stats.ini_serr_det; ++ *ptr++ = vpath_info->error_stats.prc_ring_bumps; ++ *ptr++ = vpath_info->error_stats.prc_rxdcm_sc_err; ++ *ptr++ = vpath_info->error_stats.prc_rxdcm_sc_abort; ++ *ptr++ = vpath_info->error_stats.prc_quanta_size_err; ++ *ptr++ = vpath_info->ring_stats.common_stats.full_cnt; ++ *ptr++ = vpath_info->ring_stats.common_stats.usage_cnt; ++ *ptr++ = vpath_info->ring_stats.common_stats.usage_max; ++ *ptr++ = vpath_info->ring_stats.common_stats. ++ reserve_free_swaps_cnt; ++ *ptr++ = vpath_info->ring_stats.common_stats.total_compl_cnt; ++ for (j = 0; j < VXGE_HW_DTR_MAX_T_CODE; j++) ++ *ptr++ = vpath_info->ring_stats.rxd_t_code_err_cnt[j]; ++ ++ if ((vdev->config.lro_enable) && ++ vdev->config.lro_enable != VXGE_HW_GRO_ENABLE) { ++ *ptr++ = vpath_info->ring_stats.lro_clubbed_frms_cnt; ++ *ptr++ = vpath_info->ring_stats.lro_sending_both; ++ *ptr++ = vpath_info->ring_stats.lro_outof_sequence_pkts; ++ *ptr++ = vpath_info->ring_stats.lro_flush_max_pkts; ++ *ptr++ = vpath_info->ring_stats.lro_avg_agr_pkts; ++ *ptr++ = vpath_info->ring_stats.lro_max_pkts_aggr; ++ } ++ ++ *ptr++ = vpath_info->fifo_stats.common_stats.full_cnt; ++ *ptr++ = vpath_info->fifo_stats.common_stats.usage_cnt; ++ *ptr++ = vpath_info->fifo_stats.common_stats.usage_max; ++ *ptr++ = vpath_info->fifo_stats.common_stats. ++ reserve_free_swaps_cnt; ++ *ptr++ = vpath_info->fifo_stats.common_stats.total_compl_cnt; ++ *ptr++ = vpath_info->fifo_stats.total_posts; ++ *ptr++ = vpath_info->fifo_stats.total_buffers; ++ for (j = 0; j < VXGE_HW_DTR_MAX_T_CODE; j++) ++ *ptr++ = vpath_info->fifo_stats.txd_t_code_err_cnt[j]; ++ } ++ ++ *ptr++ = 0; ++ *ptr++ = vdev->stats.vpaths_open; ++ *ptr++ = vdev->stats.vpath_open_fail; ++ *ptr++ = vdev->stats.link_up; ++ *ptr++ = vdev->stats.link_down; ++ ++ for (k = 0; k < vdev->no_of_vpath; k++) { ++ *ptr += vdev->vpaths[k].fifo.stats.tx_frms; ++ *(ptr + 1) += vdev->vpaths[k].fifo.stats.tx_errors; ++ *(ptr + 2) += vdev->vpaths[k].fifo.stats.tx_bytes; ++ *(ptr + 3) += vdev->vpaths[k].fifo.stats.txd_not_free; ++ *(ptr + 4) += vdev->vpaths[k].fifo.stats.txd_out_of_desc; ++ *(ptr + 5) += vdev->vpaths[k].ring.stats.rx_frms; ++ *(ptr + 6) += vdev->vpaths[k].ring.stats.rx_errors; ++ *(ptr + 7) += vdev->vpaths[k].ring.stats.rx_bytes; ++ *(ptr + 8) += vdev->vpaths[k].ring.stats.rx_mcast; ++ *(ptr + 9) += vdev->vpaths[k].fifo.stats.pci_map_fail + ++ vdev->vpaths[k].ring.stats.pci_map_fail; ++ *(ptr + 10) += vdev->vpaths[k].ring.stats.skb_alloc_fail; ++ } ++ ++ ptr += 12; ++ ++ ++ kfree(xmac_stats); ++ kfree(sw_stats); ++ kfree(hw_stats); ++} ++ ++static void vxge_ethtool_get_strings(struct net_device *dev, ++ u32 stringset, u8 *data) ++{ ++ int stat_size = 0; ++ int i, j; ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ ++ ++ switch (stringset) { ++ case ETH_SS_STATS: ++ vxge_add_string("VPATH STATISTICS%s\t\t\t", ++ &stat_size, data, ""); ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ vxge_add_string("tx_ttl_eth_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_ttl_eth_octects_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_data_octects_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_mcast_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_bcast_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_ucast_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_tagged_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_vld_ip_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_vld_ip_octects_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_icmp_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_tcp_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_rst_tcp_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_udp_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_unknown_proto_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_lost_ip_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_parse_error_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_tcp_offload_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_retx_tcp_offload_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_lost_ip_offload_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_eth_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_vld_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_offload_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_eth_octects_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_data_octects_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_offload_octects_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_vld_mcast_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_vld_bcast_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_accepted_ucast_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_accepted_nucast_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_tagged_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_long_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_usized_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_osized_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_frag_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_jabber_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_64_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_65_127_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_128_255_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_256_511_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_512_1023_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_1024_1518_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_1519_4095_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_4096_8191_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_8192_max_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_gt_max_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ip%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_accepted_ip_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ip_octects_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_err_ip_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_icmp_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_tcp_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_udp_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_err_tcp_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_lost_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_lost_ip_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_lost_ip_offload_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_various_discard_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_sleep_discard_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_red_discard_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_queue_full_discard_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_mpa_ok_frms_%d\t\t\t", ++ &stat_size, data, i); ++ } ++ ++ vxge_add_string("\nAGGR STATISTICS%s\t\t\t\t", ++ &stat_size, data, ""); ++ for (i = 0; i < vdev->max_config_port; i++) { ++ vxge_add_string("tx_frms_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_data_octects_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_mcast_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_bcast_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_discarded_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_errored_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_frms_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_data_octects_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_mcast_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_bcast_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_discarded_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_errored_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_unknown_slow_proto_frms_%d\t", ++ &stat_size, data, i); ++ } ++ ++ vxge_add_string("\nPORT STATISTICS%s\t\t\t\t", ++ &stat_size, data, ""); ++ for (i = 0; i < vdev->max_config_port; i++) { ++ vxge_add_string("tx_ttl_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_ttl_octects_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_data_octects_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_mcast_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_bcast_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_ucast_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_tagged_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_vld_ip_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_vld_ip_octects_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_icmp_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_tcp_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_rst_tcp_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_udp_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_parse_error_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_unknown_protocol_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_pause_ctrl_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_marker_pdu_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_lacpdu_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_drop_ip_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_marker_resp_pdu_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_xgmii_char2_match_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_xgmii_char1_match_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_xgmii_column2_match_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_xgmii_column1_match_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_any_err_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("tx_drop_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_vld_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_offload_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_octects_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_data_octects_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_offload_octects_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_vld_mcast_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_vld_bcast_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_accepted_ucast_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_accepted_nucast_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_tagged_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_long_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_usized_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_osized_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_frag_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_jabber_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_64_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_65_127_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_128_255_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_256_511_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_512_1023_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_1024_1518_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_1519_4095_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_4096_8191_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_8192_max_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ttl_gt_max_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ip_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_accepted_ip_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_ip_octets_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_err_ip_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_icmp_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_tcp_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_udp_%d\t\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_err_tcp_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_pause_count_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_pause_ctrl_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_unsup_ctrl_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_fcs_err_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_in_rng_len_err_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_out_rng_len_err_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_drop_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_discard_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_drop_ip_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_drop_udp_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_marker_pdu_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_lacpdu_frms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_unknown_pdu_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_marker_resp_pdu_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_fcs_discard_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_illegal_pdu_frms_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_switch_discard_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_len_discard_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_rpa_discard_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_l2_mgmt_discard_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_rts_discard_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_trash_discard_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_buff_full_discard_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_red_discard_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_xgmii_ctrl_err_cnt_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_xgmii_data_err_cnt_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_xgmii_char1_match_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_xgmii_err_sym_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_xgmii_column1_match_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_xgmii_char2_match_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_local_fault_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_xgmii_column2_match_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_jettison_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("rx_remote_fault_%d\t\t\t", ++ &stat_size, data, i); ++ } ++ ++ vxge_add_string("\n SOFTWARE STATISTICS%s\t\t\t", ++ &stat_size, data, ""); ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ vxge_add_string("soft_reset_cnt_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("unknown_alarms_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("network_sustained_fault_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("network_sustained_ok_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("kdfcctl_fifo0_overwrite_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("kdfcctl_fifo0_poison_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("kdfcctl_fifo0_dma_error_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("dblgen_fifo0_overflow_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("statsb_pif_chain_error_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("statsb_drop_timeout_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("target_illegal_access_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("ini_serr_det_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("prc_ring_bumps_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("prc_rxdcm_sc_err_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("prc_rxdcm_sc_abort_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("prc_quanta_size_err_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("ring_full_cnt_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("ring_usage_cnt_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("ring_usage_max_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("ring_reserve_free_swaps_cnt_%d\t", ++ &stat_size, data, i); ++ vxge_add_string("ring_total_compl_cnt_%d\t\t", ++ &stat_size, data, i); ++ for (j = 0; j < VXGE_HW_DTR_MAX_T_CODE; j++) ++ vxge_add_string("rxd_t_code_err_cnt%d_%d\t\t", ++ &stat_size, data, j, i); ++ ++ if ((vdev->config.lro_enable) && ++ vdev->config.lro_enable != VXGE_HW_GRO_ENABLE) { ++ vxge_add_string("lro_aggregated_pkts_%d\t\t", ++ &stat_size, data ,i); ++ vxge_add_string("lro_flush_both_count_%d\t\t", ++ &stat_size, data ,i); ++ vxge_add_string( "lro_out_of_sequence_pkts_%d\t\t", ++ &stat_size, data ,i); ++ vxge_add_string("lro_flush_due_to_max_pkts_%d\t", ++ &stat_size, data ,i); ++ vxge_add_string("lro_avg_aggr_pkts_%d\t\t", ++ &stat_size, data ,i); ++ vxge_add_string("lro_max_pkts_aggr_%d\t\t", ++ &stat_size, data ,i); ++ } ++ ++ vxge_add_string("fifo_full_cnt_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("fifo_usage_cnt_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("fifo_usage_max_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("fifo_reserve_free_swaps_cnt_%d\t", ++ &stat_size, data, i); ++ vxge_add_string("fifo_total_compl_cnt_%d\t\t", ++ &stat_size, data, i); ++ vxge_add_string("fifo_total_posts_%d\t\t\t", ++ &stat_size, data, i); ++ vxge_add_string("fifo_total_buffers_%d\t\t", ++ &stat_size, data, i); ++ for (j = 0; j < VXGE_HW_DTR_MAX_T_CODE; j++) ++ vxge_add_string("txd_t_code_err_cnt%d_%d\t\t", ++ &stat_size, data, j, i); ++ } ++ ++ memcpy(data + stat_size, ðtool_driver_stats_keys, ++ sizeof(ethtool_driver_stats_keys)); ++ stat_size += sizeof(ethtool_driver_stats_keys); ++ ++ ++ } ++} ++ ++#ifdef NETIF_F_TSO ++static int vxge_ethtool_op_set_tso(struct net_device *dev, u32 data) ++{ ++ if (data) { ++ dev->features |= NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 ++ dev->features |= NETIF_F_TSO6; ++#endif ++ } ++ else { ++ dev->features &= ~NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 ++ dev->features &= ~NETIF_F_TSO6; ++#endif ++ } ++ ++ return 0; ++} ++#endif ++ ++#ifndef SET_ETHTOOL_OPS ++/* ++ * vxge_ethtool - to support all ethtool features . ++ * @dev: device pointer. ++ * @ifr: An IOCTL specefic structure, that can contain a pointer to ++ * a proprietary structure used to pass information to the driver. ++ * ++ * Function used to support all ethtool features except dumping Device stats ++ * as it can be obtained from the util tool for now. ++ * ++ * 0 on success and an appropriate (-)ve integer as defined in errno.h ++ * file on failure. ++ */ ++int vxge_ethtool(struct net_device *dev, struct ifreq *rq) ++{ ++ void *data = rq->ifr_data; ++ u32 ecmd; ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ ++ if (get_user(ecmd, (u32 *)data)) ++ return -EFAULT; ++ ++ switch (ecmd) { ++ case ETHTOOL_GSET: ++ { ++ struct ethtool_cmd info = { ETHTOOL_GSET }; ++ vxge_ethtool_gset(dev, &info); ++ if (copy_to_user(data, &info, sizeof(info))) ++ return -EFAULT; ++ break; ++ } ++ case ETHTOOL_SSET: ++ { ++ struct ethtool_cmd info; ++ ++ if (copy_from_user(&info, data, sizeof(info))) ++ return -EFAULT; ++ if (vxge_ethtool_sset(dev, &info)) ++ return -EFAULT; ++ break; ++ } ++ case ETHTOOL_GDRVINFO: ++ { ++ struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO }; ++ ++ vxge_ethtool_gdrvinfo(dev, &info); ++ if (copy_to_user(data, &info, sizeof(info))) ++ return -EFAULT; ++ break; ++ } ++ case ETHTOOL_GLINK: ++ { ++ struct ethtool_value link = { ETHTOOL_GLINK }; ++ ++ link.data = netif_carrier_ok(dev); ++ if (copy_to_user(data, &link, sizeof(link))) ++ return -EFAULT; ++ break; ++ } ++ case ETHTOOL_PHYS_ID: ++ { ++ struct ethtool_value id; ++ ++ if (copy_from_user(&id, data, sizeof(id))) ++ return -EFAULT; ++ vxge_ethtool_idnic(dev, id.data); ++ break; ++ } ++ case ETHTOOL_GPAUSEPARAM: ++ { ++ struct ethtool_pauseparam ep = { ETHTOOL_GPAUSEPARAM }; ++ int tx = 0, rx = 0; ++ ++ vxge_ethtool_getpause_data(dev, &ep); ++ ep.tx_pause = tx; ++ ep.rx_pause = rx; ++ ep.autoneg = 0; ++ if (copy_to_user(data, &ep, sizeof(ep))) ++ return -EFAULT; ++ break; ++ ++ } ++ case ETHTOOL_SPAUSEPARAM: ++ { ++ struct ethtool_pauseparam ep; ++ int tx = 0, rx = 0; ++ ++ if (copy_from_user(&ep, data, sizeof(ep))) ++ return -EFAULT; ++ tx = ep.tx_pause; ++ rx = ep.rx_pause; ++ vxge_ethtool_setpause_data(dev, &ep); ++ break; ++ } ++ case ETHTOOL_GRXCSUM: ++ { ++ struct ethtool_value ev = { ETHTOOL_GRXCSUM }; ++ ++ ev.data = vdev->rx_csum; ++ if (copy_to_user(data, &ev, sizeof(ev))) ++ return -EFAULT; ++ break; ++ } ++ case ETHTOOL_GTXCSUM: ++ { ++ struct ethtool_value ev = { ETHTOOL_GTXCSUM }; ++ ev.data = (dev->features & NETIF_F_HW_CSUM); ++ ++ if (copy_to_user(data, &ev, sizeof(ev))) ++ return -EFAULT; ++ break; ++ } ++ case ETHTOOL_GSG: ++ { ++ struct ethtool_value ev = { ETHTOOL_GSG }; ++ ev.data = (dev->features & NETIF_F_SG); ++ ++ if (copy_to_user(data, &ev, sizeof(ev))) ++ return -EFAULT; ++ break; ++ } ++#ifdef NETIF_F_TSO ++ case ETHTOOL_GTSO: ++ { ++ struct ethtool_value ev = { ETHTOOL_GTSO }; ++ ev.data = (dev->features & NETIF_F_TSO); ++ ++ if (copy_to_user(data, &ev, sizeof(ev))) ++ return -EFAULT; ++ break; ++ } ++#endif ++ case ETHTOOL_STXCSUM: ++ { ++ struct ethtool_value ev; ++ ++ if (copy_from_user(&ev, data, sizeof(ev))) ++ return -EFAULT; ++ ++ if (ev.data) ++ dev->features |= NETIF_F_HW_CSUM; ++ else ++ dev->features &= ~NETIF_F_HW_CSUM; ++ break; ++ } ++ case ETHTOOL_SRXCSUM: ++ { ++ struct ethtool_value ev; ++ int i; ++ ++ if (copy_from_user(&ev, data, sizeof(ev))) ++ return -EFAULT; ++ ++ if (ev.data) ++ vdev->rx_csum = 1; ++ else ++ vdev->rx_csum = 0; ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ if(vdev->vpaths[i].is_configured) ++ vdev->vpaths[i].ring.rx_csum = ++ vdev->rx_csum; ++ } ++ break; ++ } ++ case ETHTOOL_SSG: ++ { ++ struct ethtool_value ev; ++ ++ if (copy_from_user(&ev, data, sizeof(ev))) ++ return -EFAULT; ++ ++ if (ev.data) ++ dev->features |= NETIF_F_SG; ++ else ++ dev->features &= ~NETIF_F_SG; ++ break; ++ } ++#ifdef NETIF_F_TSO ++ case ETHTOOL_STSO: ++ { ++ struct ethtool_value ev; ++ ++ if (copy_from_user(&ev, data, sizeof(ev))) ++ return -EFAULT; ++ ++ if (ev.data) ++ dev->features |= NETIF_F_TSO; ++ else ++ dev->features &= ~NETIF_F_TSO; ++ break; ++ } ++#endif ++ case ETHTOOL_GEEPROM: ++ { ++ break; ++ } ++ case ETHTOOL_GSTRINGS: ++ { ++ struct ethtool_gstrings gstrings = { ETHTOOL_GSTRINGS }; ++ char *strings = NULL; ++ int ret = 0, mem_sz = 0; ++ ++ if (copy_from_user ++ (&gstrings, data, sizeof(gstrings))) ++ return -EFAULT; ++ ++ switch (gstrings.string_set) { ++#ifdef ETHTOOL_GSTATS ++ case ETH_SS_STATS: ++ vxge_ethtool_get_strings(dev, ++ gstrings.string_set, data); ++ break; ++#endif ++ ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ if (copy_to_user ++ (data, &gstrings, sizeof(gstrings))) ++ ret = -EFAULT; ++ if (!ret) { ++ data += ++ offsetof(struct ethtool_gstrings, ++ data); ++ if (copy_to_user(data, strings, mem_sz)) ++ ret = -EFAULT; ++ } ++ kfree(strings); ++ if (ret) ++ return ret; ++ break; ++ } ++#ifdef ETHTOOL_GSTATS ++ case ETHTOOL_GSTATS: ++ { ++ struct ethtool_stats stats; ++ int ret; ++ u64 *stat_mem; ++ ++ if (copy_from_user(&stats, data, sizeof(stats))) ++ return -EFAULT; ++ stats.n_stats = STAT_LEN; ++ stat_mem = ++ kmalloc(stats.n_stats * sizeof(u64), GFP_USER); ++ if (!stat_mem) ++ return -ENOMEM; ++ ++ vxge_get_ethtool_stats(dev, &stats, stat_mem); ++ ret = 0; ++ if (copy_to_user(data, &stats, sizeof(stats))) ++ ret = -EFAULT; ++ data += sizeof(stats); ++ if (copy_to_user(data, stat_mem, ++ stats.n_stats * sizeof(u64))) ++ ret = -EFAULT; ++ kfree(stat_mem); ++ return ret; ++ } ++#endif ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return 0; ++} ++#else ++ ++static int vxge_ethtool_get_regs_len(struct net_device *dev) ++{ ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ ++ int vpath_max = VXGE_LEN_128_K / sizeof(struct vxge_hw_vpath_reg); ++ if (vdev->no_of_vpath < vpath_max) ++ vpath_max = vdev->no_of_vpath; ++ return sizeof (struct vxge_hw_vpath_reg) * vpath_max; ++} ++ ++/** ++ * vxge_ethtool_gregs - dumps the entire space of Titan into the buffer. ++ * @dev: device pointer. ++ * @regs: pointer to the structure with parameters given by ethtool for ++ * dumping the registers. ++ * @reg_space: The input argumnet into which all the registers are dumped. ++ * ++ * Dumps the vpath register space of Titan NIC into the user given ++ * buffer area. ++ */ ++static void vxge_ethtool_gregs(struct net_device *dev, ++ struct ethtool_regs *regs, void *space) ++{ ++ int index, offset, vpath_max = 0; ++ enum vxge_hw_status status; ++ u64 reg; ++ u8 *reg_space = (u8 *) space; ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ struct __vxge_hw_device *hldev = (struct __vxge_hw_device *) ++ pci_get_drvdata(vdev->pdev); ++ ++ /* maximum len supported by ethtool is 128K, calculate number of vpaths ++ for which we can dump registers */ ++ vpath_max = VXGE_LEN_128_K / sizeof(struct vxge_hw_vpath_reg); ++ if (vdev->no_of_vpath < vpath_max) ++ vpath_max = vdev->no_of_vpath; ++ ++ regs->len = sizeof(struct vxge_hw_vpath_reg) * vpath_max; ++ regs->version = vdev->pdev->subsystem_device; ++ for (index = 0; index < vpath_max; index++) { ++ for (offset = 0; offset < sizeof(struct vxge_hw_vpath_reg); ++ offset += 8) { ++ status = vxge_hw_mgmt_reg_read(hldev, ++ vxge_hw_mgmt_reg_type_vpath, ++ vdev->vpaths[index].device_id, ++ offset, ®); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s:%d Getting reg dump Failed", ++ __func__, __LINE__); ++ return; ++ } ++ ++ memcpy((reg_space + offset), ®, 8); ++ } ++ } ++} ++ ++static u32 vxge_get_rx_csum(struct net_device *dev) ++{ ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ ++ return vdev->rx_csum; ++} ++ ++static int vxge_set_rx_csum(struct net_device *dev, u32 data) ++{ ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ ++ if (data) ++ vdev->rx_csum = 1; ++ else ++ vdev->rx_csum = 0; ++ ++ return 0; ++} ++ ++ ++ ++static struct ethtool_ops vxge_ethtool_ops = { ++ .get_settings = vxge_ethtool_gset, ++ .set_settings = vxge_ethtool_sset, ++ .get_drvinfo = vxge_ethtool_gdrvinfo, ++ .get_regs_len = vxge_ethtool_get_regs_len, ++ .get_regs = vxge_ethtool_gregs, ++ .get_link = ethtool_op_get_link, ++ .get_pauseparam = vxge_ethtool_getpause_data, ++ .set_pauseparam = vxge_ethtool_setpause_data, ++ .get_rx_csum = vxge_get_rx_csum, ++ .set_rx_csum = vxge_set_rx_csum, ++ .get_tx_csum = ethtool_op_get_tx_csum, ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) ++ .set_tx_csum = ethtool_op_set_tx_hw_csum, ++#endif ++ ++ .get_sg = ethtool_op_get_sg, ++ .set_sg = ethtool_op_set_sg, ++ ++#ifdef NETIF_F_TSO ++ .get_tso = ethtool_op_get_tso, ++ .set_tso = vxge_ethtool_op_set_tso, ++ ++#endif ++ .get_strings = vxge_ethtool_get_strings, ++ .phys_id = vxge_ethtool_idnic, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) ++ .get_stats_count = vxge_ethtool_get_stats_count, ++#else ++ .get_sset_count = vxge_ethtool_get_sset_count, ++#endif ++ .get_ethtool_stats = vxge_get_ethtool_stats, ++}; ++ ++void initialize_ethtool_ops(struct net_device *ndev) ++{ ++ SET_ETHTOOL_OPS(ndev, &vxge_ethtool_ops); ++} ++ ++#endif +diff -r 158b6e53275e drivers/net/vxge/vxge-ethtool.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/vxge/vxge-ethtool.h Wed Aug 05 11:58:00 2009 +0100 +@@ -0,0 +1,59 @@ ++/****************************************************************************** ++ * vxge-ethtool.h: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O ++ * Virtualized Server Adapter. ++ * Copyright(c) 2002-2009 Neterion Inc. ++ ******************************************************************************/ ++#ifndef _VXGE_ETHTOOL_H ++#define _VXGE_ETHTOOL_H ++ ++#include "vxge-main.h" ++ ++/* Ethtool related variables and Macros. */ ++ ++static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = { ++ {"\n DRIVER STATISTICS"}, ++ {"vpaths_opened"}, ++ {"vpath_open_fail_cnt"}, ++ {"link_up_cnt"}, ++ {"link_down_cnt"}, ++ {"tx_frms"}, ++ {"tx_errors"}, ++ {"tx_bytes"}, ++ {"txd_not_free"}, ++ {"txd_out_of_desc"}, ++ {"rx_frms"}, ++ {"rx_errors"}, ++ {"rx_bytes"}, ++ {"rx_mcast"}, ++ {"pci_map_fail_cnt"}, ++ {"skb_alloc_fail_cnt"} ++}; ++ ++/* The following macros represent the number of lines in the output */ ++#define VXGE_TITLE_LEN 4 ++#define VXGE_HW_VPATH_TX_STATS_LEN 19 ++#define VXGE_HW_VPATH_RX_STATS_LEN 42 ++#define VXGE_HW_AGGR_STATS_LEN 13 ++#define VXGE_HW_PORT_STATS_LEN 94 ++#define VXGE_SW_STATS_LEN 66 ++#define SOFT_LRO_STAT_CNT 6 ++#define VXGE_HW_STATS_LEN (VXGE_HW_AGGR_STATS_LEN +\ ++ VXGE_HW_PORT_STATS_LEN +\ ++ VXGE_HW_VPATH_TX_STATS_LEN +\ ++ VXGE_HW_VPATH_RX_STATS_LEN) ++ ++ ++#define DRIVER_STAT_LEN (sizeof(ethtool_driver_stats_keys)/ETH_GSTRING_LEN) ++#define STAT_LEN (VXGE_HW_STATS_LEN + DRIVER_STAT_LEN + VXGE_SW_STATS_LEN) ++ ++/* Maximum flicker time of adapter LED */ ++#define VXGE_MAX_FLICKER_TIME (60 * HZ) /* 60 seconds */ ++#define VXGE_FLICKER_ON 1 ++#define VXGE_FLICKER_OFF 0 ++ ++#define vxge_add_string(fmt, size, buf, ...) {\ ++ snprintf(buf + *size, ETH_GSTRING_LEN, fmt, __VA_ARGS__); \ ++ *size += ETH_GSTRING_LEN; \ ++} ++#define VXGE_LEN_128_K (128 * 1024) ++#endif /*_VXGE_ETHTOOL_H*/ +diff -r 158b6e53275e drivers/net/vxge/vxge-kcompat.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/vxge/vxge-kcompat.h Wed Aug 05 11:58:00 2009 +0100 +@@ -0,0 +1,405 @@ ++#ifndef VXGE_KCOMPAT_H ++#define VXGE_KCOMPAT_H ++ ++ ++ ++#ifndef CHECKSUM_PARTIAL ++#define CHECKSUM_PARTIAL CHECKSUM_HW ++#endif ++ ++#ifndef IRQ_RETVAL ++typedef void irqreturn_t; ++#define IRQ_NONE ++#define IRQ_HANDLED ++#define IRQ_RETVAL(x) ++#endif ++ ++#ifndef gfp_t ++#define gfp_t int ++#endif ++ ++#ifndef ETH_FCS_LEN ++#define ETH_FCS_LEN 4 ++#endif ++ ++#ifndef PCI_CAP_ID_EXP ++#define PCI_CAP_ID_EXP 0x10 ++#endif ++ ++#ifndef PCI_EXP_LNKSTA ++#define PCI_EXP_LNKSTA 18 ++#endif ++ ++#ifndef PCI_MSIX_FLAGS ++#define PCI_MSIX_FLAGS 2 ++#define PCI_CAP_ID_MSIX 0x11 ++#define PCI_MSIX_FLAGS_ENABLE 0x8000 ++#endif ++ ++#ifndef NETDEV_TX_OK ++#define NETDEV_TX_OK 0 ++#endif ++ ++#ifndef NETDEV_TX_BUSY ++#define NETDEV_TX_BUSY 1 ++#endif ++ ++#ifndef NETDEV_TX_LOCKED ++#define NETDEV_TX_LOCKED -1 ++#endif ++ ++#ifndef SET_NETDEV_DEV ++#define SET_NETDEV_DEV(net, pdev) ++#endif ++ ++#ifndef HAVE_FREE_NETDEV ++#define free_netdev(x) kfree(x) ++#endif ++ ++#ifndef module_param ++#define VXGE_MODULE_PARAM_INT(p, val) \ ++ static int p = val; \ ++ MODULE_PARM(p, "i"); ++#endif ++ ++#ifndef SKB_GSO_UDP ++#define SKB_GSO_UDP 0x2 ++#endif ++ ++#ifndef SKB_GSO_TCPV4 ++#define SKB_GSO_TCPV4 0x1 ++#endif ++ ++#ifndef SKB_GSO_TCPV6 ++#define SKB_GSO_TCPV6 0x10 ++#endif ++ ++#ifndef NETIF_F_GSO ++#define gso_size tso_size ++#endif ++ ++#ifndef SET_ETHTOOL_OPS ++#define SPEED_10000 10000 ++#define SUPPORTED_10000baseT_Full (1 << 12) ++#define ADVERTISED_10000baseT_Full (1 << 12) ++#endif ++ ++#ifndef strlcpy ++#define strlcpy vxge_strlcpy ++static inline size_t vxge_strlcpy(char *dest, const char *src, size_t size) ++{ ++ size_t ret = strlen(src); ++ ++ if (size) { ++ size_t len = (ret >= size) ? size - 1 : ret; ++ memcpy(dest, src, len); ++ dest[len] = '\0'; ++ } ++ return ret; ++} ++#endif ++ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) ) ++#define pci_name(x) ((x)->slot_name) ++#endif /* < 2.4.22 */ ++ ++#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \ ++ (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \ ++ ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) ))) ++#define netdev_priv(x) x->priv ++#endif ++ ++#ifndef spin_trylock_irqsave ++#define spin_trylock_irqsave(lock, flags) \ ++({ \ ++ local_irq_save(flags); \ ++ spin_trylock(lock) ? \ ++ 1 : ({ local_irq_restore(flags); 0; }); \ ++}) ++#endif ++ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ) ++#undef pci_register_driver ++#define pci_register_driver pci_module_init ++ ++#define list_for_each_entry_safe(pos, n, head, member) \ ++ for (pos = list_entry((head)->next, typeof(*pos), member), \ ++ n = list_entry(pos->member.next, typeof(*pos), member); \ ++ &pos->member != (head); \ ++ pos = n, n = list_entry(n->member.next, typeof(*n), member)) ++ ++#endif /* < 2.5.0 */ ++ ++/* synchronize_irq */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28)) ++ ++#define vxge_synchronize_irq(x) synchronize_irq() ++ ++#define flush_scheduled_work flush_scheduled_tasks ++#else ++#define vxge_synchronize_irq(x) synchronize_irq(x) ++#endif /* < 2,5,28 */ ++ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) ++#define pci_dma_sync_single_for_cpu pci_dma_sync_single ++#define pci_dma_sync_single_for_device pci_dma_sync_single_for_cpu ++#endif /* < 2.6.5 */ ++ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) ) ++#define msleep(x) do { set_current_state(TASK_UNINTERRUPTIBLE); \ ++ schedule_timeout((x * HZ)/1000 + 2); \ ++ } while (0) ++#endif /* < 2.6.8 */ ++ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)) ++ ++#define __iomem ++ ++#ifndef __be32 ++#define __be32 u32 ++#endif ++ ++#define msleep_interruptible(x) do {set_current_state(TASK_INTERRUPTIBLE); \ ++ schedule_timeout((x * HZ)/1000); \ ++ } while(0) ++#endif /* < 2.6.9 */ ++ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) ) ++ ++#ifndef kzalloc ++#define kzalloc _vxge_kzalloc ++static inline void * _vxge_kzalloc(size_t size, int flags) ++{ ++ void *ret = kmalloc(size, flags); ++ if (ret) ++ memset(ret, 0, size); ++ return ret; ++ ++} ++#endif ++ ++#endif /* < 2.6.14 */ ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,15)) ++#undef CONFIG_PM ++#endif /* < 2.6.15 */ ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) ++#define VXGE_NAPI_ENABLE(napi) napi_enable(napi) ++#define VXGE_NAPI_DISABLE(napi) napi_disable(napi) ++#else ++#define VXGE_NAPI_ENABLE(napi) ++#define VXGE_NAPI_DISABLE(napi) ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) ++#ifndef netdev_alloc_skb ++#define netdev_alloc_skb _vxge_netdev_alloc_skb ++static inline struct sk_buff *_vxge_netdev_alloc_skb(struct net_device *dev, ++ unsigned int length) ++{ ++ /* 16 == NET_PAD_SKB */ ++ struct sk_buff *skb; ++ skb = alloc_skb(length + 16, GFP_ATOMIC); ++ if (likely(skb != NULL)) { ++ skb_reserve(skb, 16); ++ skb->dev = dev; ++ } ++ return skb; ++} ++#endif ++ ++#ifndef IRQF_SHARED ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#ifndef skb_is_gso ++#ifdef NETIF_F_TSO ++#define skb_is_gso _vxge_skb_is_gso ++static inline int _vxge_skb_is_gso(const struct sk_buff *skb) ++{ ++ return skb_shinfo(skb)->gso_size; ++} ++#else ++#define skb_is_gso(a) 0 ++#endif ++#endif ++ ++#endif /* < 2.6.18 */ ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) ++#define VXGE_CHECK_PCI_CHANNEL_OFFLINE(pdev) { \ ++ if (pci_channel_offline(pdev)) \ ++ return IRQ_NONE; \ ++} ++#else ++#define VXGE_CHECK_PCI_CHANNEL_OFFLINE(pdev) ++#endif /* > 2.6.21 */ ++ ++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) ) ++#define ip_hdr(skb) (skb->nh.iph) ++#endif /* < 2.6.22 */ ++ ++static inline void vxge_netif_do_rx_complete(struct net_device *dev, ++ void *napi) ++{ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) ++ netif_rx_complete(dev); ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)) ++ netif_rx_complete(dev, (struct napi_struct *) napi); ++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ++ napi_complete((struct napi_struct *) napi); ++#endif ++} ++ ++static inline int vxge_netif_subqueue_stopped(struct net_device *dev, ++ struct sk_buff *skb, u16 queue_index) ++{ ++ int ret = 0; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 23)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ ret = netif_subqueue_stopped(dev, queue_index); ++#endif ++#else ++ ret = netif_subqueue_stopped(dev, skb); ++#endif ++ return ret; ++} ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 23)) ++#define alloc_etherdev_mq(size, no_of_vpath) alloc_etherdev(size) ++#endif /* < 2.6.23 */ ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) ++#define vxge_tx_queues_set(dev, count) (ndev->real_num_tx_queues = no_of_vpath) ++#else ++#define vxge_tx_queues_set(dev, count) ++#endif /* > 2.6.30 */ ++ ++static inline void __iomem *vxge_pci_ioremap_bar(struct pci_dev *pdev, int bar) ++{ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) ++ return pci_ioremap_bar(pdev, bar); ++#else ++ return ioremap(pci_resource_start(pdev, bar), ++ pci_resource_len(pdev, bar)); ++#endif /* >= 2.6.28 */ ++} ++ ++static inline void vxge_netif_do_rx_schedule(struct net_device *dev, void *napi) ++{ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) ++ netif_rx_schedule(dev); ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)) ++ netif_rx_schedule(dev, (struct napi_struct *) napi); ++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ++ napi_schedule((struct napi_struct *) napi); ++#endif ++} ++ ++extern irqreturn_t vxge_do_isr_napi(int irq, void *dev_id); ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++static inline irqreturn_t vxge_isr_napi(int irq, void *dev_id, ++ struct pt_regs *regs) ++#else ++static inline irqreturn_t vxge_isr_napi(int irq, void *dev_id) ++#endif ++{ ++ return vxge_do_isr_napi(irq, dev_id); ++} ++ ++extern irqreturn_t vxge_do_isr(int irq, void *dev_id); ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++static inline irqreturn_t vxge_isr(int irq, void *dev_id, struct pt_regs *regs) ++#else ++static inline irqreturn_t vxge_isr(int irq, void *dev_id) ++#endif ++{ ++ return vxge_do_isr(irq, dev_id); ++} ++ ++extern irqreturn_t vxge_do_rx_msix_handle(int irq, void *dev_id); ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++static inline irqreturn_t vxge_rx_msix_handle(int irq, void *dev_id, ++ struct pt_regs *regs) ++#else ++static inline irqreturn_t vxge_rx_msix_handle(int irq, void *dev_id) ++#endif ++{ ++ return vxge_do_rx_msix_handle(irq, dev_id); ++} ++ ++extern irqreturn_t vxge_do_tx_msix_handle(int irq, void *dev_id); ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++static inline irqreturn_t vxge_tx_msix_handle(int irq, void *dev_id, ++ struct pt_regs *regs) ++#else ++static inline irqreturn_t vxge_tx_msix_handle(int irq, void *dev_id) ++#endif ++{ ++ return vxge_do_tx_msix_handle(irq, dev_id); ++} ++ ++extern irqreturn_t vxge_do_rx_msix_napi_handle(int irq, void *dev_id); ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++static inline irqreturn_t vxge_rx_msix_napi_handle(int irq, void *dev_id, ++ struct pt_regs *regs) ++#else ++static inline irqreturn_t vxge_rx_msix_napi_handle(int irq, void *dev_id) ++#endif ++{ ++ return vxge_do_rx_msix_napi_handle(irq, dev_id); ++} ++ ++extern irqreturn_t vxge_do_alarm_msix_handle(int irq, void *dev_id); ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 19)) ++static inline irqreturn_t vxge_alarm_msix_handle(int irq, void *dev_id, ++ struct pt_regs *regs) ++#else ++static inline irqreturn_t vxge_alarm_msix_handle(int irq, void *dev_id) ++#endif ++{ ++ return vxge_do_alarm_msix_handle(irq, dev_id); ++} ++ ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 21)) ++#define vlan_group_get_device(vg, id) (vg->vlan_devices[id]) ++#define vlan_group_set_device(vg, id, dev) if (vg) vg->vlan_devices[id] = dev; ++#endif ++ ++#ifndef IN_MULTICAST ++#define IN_MULTICAST(a) ((((long int) (a)) & 0xf0000000) == 0xe0000000) ++#endif ++ ++#ifndef INADDR_BROADCAST ++#define INADDR_BROADCAST ((unsigned long int) 0xffffffff) ++#endif ++ ++static inline dma_addr_t vxge_dma_map(struct pci_dev *pdev, ++ void *vaddr, size_t size, int dir) ++{ ++ ++ return pci_map_single(pdev, vaddr, size, dir); ++ ++} ++ ++static inline void vxge_dma_unmap(struct pci_dev *pdev, ++ dma_addr_t dma_addr, size_t size, int dir) ++{ ++ ++ pci_unmap_single(pdev, dma_addr, size, dir); ++ ++} ++ ++ ++ ++ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ++#define mmiowb() barrier() ++#endif ++ ++#endif +diff -r 158b6e53275e drivers/net/vxge/vxge-main.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/vxge/vxge-main.c Wed Aug 05 11:58:00 2009 +0100 +@@ -0,0 +1,5767 @@ ++/****************************************************************************** ++* vxge-main.c: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O ++* Virtualized Server Adapter. ++* Copyright(c) 2002-2009 Neterion Inc. ++* ++* The module loadable parameters that are supported by the driver and a brief ++* explanation of all the variables: ++* intr_type: ++* This configures the type of interrupt. ++* 0 - INTA ++* 1 - Reserved ++* 2 - MSIX ++* vlan_tag_strip: ++* Strip VLAN Tag enable/disable. Instructs the device to remove ++* the VLAN tag from all received tagged frames that are not ++* replicated at the internal L2 switch. ++* 0 - Do not strip the VLAN tag. ++* 1 - Strip the VLAN tag. ++* ++* promisc_en: ++* Enable promisous mode for privileged function ++* 0 - DISABLE ++* 1 - ENABLE ++* ++* promisc_all_en: ++* Enable promisous mode for all functions ++* 0 - DISABLE ++* 1 - ENABLE ++* ++* max_config_port: ++* Maximum number of port to be supported. ++* MIN -1 and MAX - 2 ++* ++* max_config_vpath: ++* This configures the maximum no of VPATH configures for each ++* device function. ++* MIN - 1 and MAX - 17 ++* ++* max_config_dev: ++* This configures maximum no of Device function to be enabled. ++* MIN - 1 and MAX - 17 ++* ++* napi: ++* Enable NAPI support. ++* 0 - DISABLE ++* 1 - ENABLE ++* ++* lro: ++* Enable Large Receive Offload (LRO) / GRO ++* 0 - VXGE_HW_LRO_DONOT_AGGREGATE ++* 1 - VXGE_HW_LRO_ALWAYS_AGGREGATE ++* 2 - VXGE_HW_LRO_DONT_AGGR_FWD_PKTS ++* 3 - VXGE_HW_GRO_ENABLE ++* ++* rx_steering_type: ++* This parameter is for configuring the receive side steering. ++* 0 - No steering ++* 1 - Reserved ++* 2 - RTH_TCP_UDP steering (default) ++* 3 - RTH_IPV4 steering ++* 4 - RTH_IPV6_EX steering ++* ++* tx_steering_type: ++* This parameter is for configuring the transmit steering. ++* 0 - No steering ++* 1 - Priority steering ++* 2 - Vlan steering ++* 3 - Multiqueue steering ++* 4 - Port steering (default) ++* ++* tx_pause_enable: ++* This parameter enables pause frame generation. ++* 0 - Disable ++* 1 - Enable ++* ++* rx_pause_enable: ++* This parameter enables response to received pause frames ++* 0 - Disable ++* 1 - Enable ++* exec_mode: ++* This is set make enable the debug mode by default. ++* 0 - DISABLE ++* 1 - ENABLE ++* ++* stats_read_method: ++* This parameter sets the stats read method. ++* 0 - VXGE_HW_STATS_READ_METHOD_PIO ++* 1 - VXGE_HW_STATS_READ_METHOD_DMA ++* ++* doorbell_mode: ++* This parameter enables door_bell_mode. ++* 0 - Disable ++* 1 - Enable ++* 2 - Default (Enable) ++* ++* intr_adapt: ++* This parameter enables adaptive interrupt coalescing. ++* 0 - Disable ++* 1 - Enable (default) ++* tx_bw_limit: ++* Desired max transmit bandwidth,in Mbps ++* ++* rx_bw_limit: ++* Desired max receive bandwidth,in Mbps ++******************************************************************************/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "vxge-main.h" ++#include "vxge-reg.h" ++#include "vxge-kcompat.h" ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++ ++#ifdef MODULE_VERSION ++MODULE_VERSION(DRV_VERSION); ++#endif ++ ++MODULE_DESCRIPTION("Neterion's X3100 Series 10GbE PCIe I/O" ++ "Virtualized Server Adapter"); ++ ++static struct pci_device_id vxge_id_table[] __devinitdata = { ++ {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_TITAN_WIN, PCI_ANY_ID, ++ PCI_ANY_ID}, ++ {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_TITAN_UNI, PCI_ANY_ID, ++ PCI_ANY_ID}, ++ {0,} ++}; ++ ++MODULE_DEVICE_TABLE(pci, vxge_id_table); ++ ++VXGE_MODULE_PARAM_INT(intr_type, MSI_X); ++VXGE_MODULE_PARAM_INT(vlan_tag_strip, VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE); ++VXGE_MODULE_PARAM_INT(promisc_en, VXGE_HW_PROM_MODE_DISABLE); ++VXGE_MODULE_PARAM_INT(promisc_all_en, VXGE_HW_PROM_MODE_DISABLE); ++VXGE_MODULE_PARAM_INT(rec_all_vid, VXGE_ALL_VID_DISABLE); ++VXGE_MODULE_PARAM_INT(max_config_port, VXGE_MAX_CONFIG_PORT); ++VXGE_MODULE_PARAM_INT(max_config_vpath, VXGE_USE_DEFAULT); ++VXGE_MODULE_PARAM_INT(max_mac_vpath, VXGE_MAX_MAC_ADDR_COUNT); ++VXGE_MODULE_PARAM_INT(max_config_dev, VXGE_MAX_CONFIG_DEV); ++ ++ ++VXGE_MODULE_PARAM_INT(napi, VXGE_ENABLE_NAPI); ++ ++ ++ ++VXGE_MODULE_PARAM_INT(lro, VXGE_HW_LRO_DONT_AGGR_FWD_PKTS); ++VXGE_MODULE_PARAM_INT(rx_steering_type, RTH_TCP_UDP_STEERING); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 26)) ++VXGE_MODULE_PARAM_INT(tx_steering_type, TX_MULTIQ_STEERING); ++#else ++VXGE_MODULE_PARAM_INT(tx_steering_type, TX_PORT_STEERING); ++#endif ++ ++ ++VXGE_MODULE_PARAM_INT(tx_pause_enable, VXGE_PAUSE_CTRL_ENABLE); ++VXGE_MODULE_PARAM_INT(rx_pause_enable, VXGE_PAUSE_CTRL_ENABLE); ++VXGE_MODULE_PARAM_INT(exec_mode, VXGE_EXEC_MODE_DISABLE); ++VXGE_MODULE_PARAM_INT(stats_read_method, VXGE_HW_STATS_READ_METHOD_PIO); ++VXGE_MODULE_PARAM_INT(doorbell_mode, VXGE_HW_DOORBELL_MODE_DEFAULT); ++VXGE_MODULE_PARAM_INT(intr_adapt, VXGE_ADAPTIVE_INTR_COALESCING_ON); ++VXGE_MODULE_PARAM_INT(tx_bw_limit, VXGE_HW_VPATH_TX_BANDWIDTH_LIMIT_DEFAULT); ++VXGE_MODULE_PARAM_INT(rx_bw_limit, VXGE_HW_VPATH_RX_BANDWIDTH_LIMIT_DEFAULT); ++ ++ ++ ++static u16 vpath_selector[VXGE_HW_MAX_VIRTUAL_PATHS] = ++ {0, 1, 3, 3, 7, 7, 7, 7, 15, 15, 15, 15, 15, 15, 15, 15, 31}; ++ ++static struct vxge_drv_config *driver_config; ++ ++ ++ ++#ifdef VXGE_LOOPBACK_TEST ++static int vxge_xmit(struct sk_buff *skb, struct net_device *dev); ++#endif ++ ++static inline int is_vxge_card_up(struct vxgedev *vdev) ++{ ++ return test_bit(__VXGE_STATE_CARD_UP, &vdev->state); ++} ++ ++static inline void VXGE_COMPLETE_VPATH_TX(struct vxge_fifo *fifo) ++{ ++ unsigned long flags = 0; ++ struct sk_buff **skb_ptr = NULL; ++ struct sk_buff **temp; ++#define NR_SKB_COMPLETED 128 ++ struct sk_buff *completed[NR_SKB_COMPLETED]; ++ int more; ++ ++ do { ++ more = 0; ++ skb_ptr = completed; ++ ++ if (vxge_spin_trylock(&fifo->tx_lock, flags)) { ++ vxge_hw_vpath_poll_tx(fifo->handle, &skb_ptr, ++ NR_SKB_COMPLETED, &more); ++ vxge_spin_unlock(&fifo->tx_lock, flags); ++ } ++ /* free SKBs */ ++ for (temp = completed; temp != skb_ptr; temp++) { ++ struct sk_buff *skb = *temp; ++ if (fifo->addr_learn_en) ++ vxge_learn_mac(fifo, skb->data + ETH_ALEN); ++ dev_kfree_skb_irq(skb); ++ } ++ } while (more) ; ++} ++ ++static inline void VXGE_COMPLETE_ALL_TX(struct vxgedev *vdev) ++{ ++ int i; ++ ++ /* Complete all transmits */ ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ VXGE_COMPLETE_VPATH_TX(&vdev->vpaths[i].fifo); ++} ++ ++static inline void VXGE_COMPLETE_ALL_RX(struct vxgedev *vdev) ++{ ++ int i; ++ struct vxge_ring *ring; ++ ++ /* Complete all receives*/ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ ring = &vdev->vpaths[i].ring; ++ vxge_hw_vpath_poll_rx(ring->handle); ++ } ++} ++ ++/* ++ * MultiQ manipulation helper functions ++ */ ++void vxge_stop_all_tx_queue(struct vxgedev *vdev) ++{ ++ int i; ++ struct net_device *dev = vdev->ndev; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ if (vdev->config.tx_steering_type == TX_MULTIQ_STEERING) { ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ netif_stop_subqueue(dev, i); ++ } else ++#endif ++ { ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ vdev->vpaths[i].fifo.queue_state = VPATH_QUEUE_STOP; ++ netif_stop_queue(dev); ++ } ++#else ++ if (vdev->config.tx_steering_type != TX_MULTIQ_STEERING) { ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ vdev->vpaths[i].fifo.queue_state = VPATH_QUEUE_STOP; ++ } ++ netif_tx_stop_all_queues(dev); ++#endif ++} ++ ++void vxge_stop_tx_queue(struct vxge_fifo *fifo) ++{ ++ struct net_device *dev = fifo->ndev; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ if (vdev->config.tx_steering_type == TX_MULTIQ_STEERING) ++ netif_stop_subqueue(dev, fifo->driver_id); ++ else ++#endif ++ { ++ fifo->queue_state = VPATH_QUEUE_STOP; ++ netif_stop_queue(dev); ++ } ++#else ++ struct netdev_queue *txq = NULL; ++ if (fifo->tx_steering_type == TX_MULTIQ_STEERING) ++ txq = netdev_get_tx_queue(dev, fifo->driver_id); ++ else { ++ txq = netdev_get_tx_queue(dev, 0); ++ fifo->queue_state = VPATH_QUEUE_STOP; ++ } ++ ++ netif_tx_stop_queue(txq); ++#endif ++} ++ ++void vxge_start_all_tx_queue(struct vxgedev *vdev) ++{ ++ int i; ++ struct net_device *dev = vdev->ndev; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ if (vdev->config.tx_steering_type == TX_MULTIQ_STEERING) ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ netif_start_subqueue(dev, i); ++ else ++#endif ++ { ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ vdev->vpaths[i].fifo.queue_state = VPATH_QUEUE_START; ++ netif_start_queue(dev); ++ } ++#else ++ if (vdev->config.tx_steering_type != TX_MULTIQ_STEERING) { ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ vdev->vpaths[i].fifo.queue_state = VPATH_QUEUE_START; ++ } ++ netif_tx_start_all_queues(dev); ++#endif ++} ++ ++static void vxge_wake_all_tx_queue(struct vxgedev *vdev) ++{ ++ int i; ++ struct net_device *dev = vdev->ndev; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ if (vdev->config.tx_steering_type == TX_MULTIQ_STEERING) ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ netif_wake_subqueue(dev, i); ++ else ++#endif ++ { ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ vdev->vpaths[i].fifo.queue_state = VPATH_QUEUE_START; ++ netif_wake_queue(dev); ++ } ++#else ++ if (vdev->config.tx_steering_type != TX_MULTIQ_STEERING) { ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ vdev->vpaths[i].fifo.queue_state = VPATH_QUEUE_START; ++ } ++ netif_tx_wake_all_queues(dev); ++#endif ++} ++ ++void vxge_wake_tx_queue(struct vxge_fifo *fifo, struct sk_buff *skb) ++{ ++ struct net_device *dev = fifo->ndev; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26)) ++#ifdef CONFIG_NETDEVICES_MULTIQUEUE ++ int vpath_no = fifo->driver_id; ++ if (fifo->tx_steering_type == TX_MULTIQ_STEERING) { ++ if ((skb == NULL) || ++ vxge_netif_subqueue_stopped(dev, skb, vpath_no)) ++ netif_wake_subqueue(dev, vpath_no); ++ } else ++#endif ++ if (fifo->queue_state == VPATH_QUEUE_STOP) { ++ if (netif_queue_stopped(dev)) { ++ fifo->queue_state = VPATH_QUEUE_START; ++ netif_wake_queue(dev); ++ } ++ } ++#else ++ int vpath_no = fifo->driver_id; ++ struct netdev_queue *txq = NULL; ++ if (fifo->tx_steering_type == TX_MULTIQ_STEERING) { ++ txq = netdev_get_tx_queue(dev, vpath_no); ++ if (netif_tx_queue_stopped(txq)) ++ netif_tx_wake_queue(txq); ++ } else { ++ txq = netdev_get_tx_queue(dev, 0); ++ if (fifo->queue_state == VPATH_QUEUE_STOP) ++ if (netif_tx_queue_stopped(txq)) { ++ fifo->queue_state = VPATH_QUEUE_START; ++ netif_tx_wake_queue(txq); ++ } ++ } ++#endif ++} ++ ++/* ++ * vxge_callback_link_up ++ * ++ * This function is called during interrupt context to notify link up state ++ * change. ++ */ ++void ++vxge_callback_link_up(struct __vxge_hw_device *hldev) ++{ ++ struct net_device *dev = hldev->ndev; ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d", ++ vdev->ndev->name, __func__, __LINE__); ++ printk(KERN_NOTICE "%s: Link Up\n", vdev->ndev->name); ++ vdev->stats.link_up++; ++ ++ netif_carrier_on(vdev->ndev); ++ vxge_wake_all_tx_queue(vdev); ++ ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s: %s:%d Exiting...", vdev->ndev->name, __func__, __LINE__); ++} ++ ++/* ++ * vxge_callback_link_down ++ * ++ * This function is called during interrupt context to notify link down state ++ * change. ++ */ ++void ++vxge_callback_link_down(struct __vxge_hw_device *hldev) ++{ ++ struct net_device *dev = hldev->ndev; ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s: %s:%d", vdev->ndev->name, __func__, __LINE__); ++ printk(KERN_NOTICE "%s: Link Down\n", vdev->ndev->name); ++ ++ vdev->stats.link_down++; ++ netif_carrier_off(vdev->ndev); ++ vxge_stop_all_tx_queue(vdev); ++ ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s: %s:%d Exiting...", vdev->ndev->name, __func__, __LINE__); ++} ++ ++/* ++ * vxge_rx_alloc ++ * ++ * Allocate SKB. ++ */ ++static struct sk_buff* ++vxge_rx_alloc(void *dtrh, struct vxge_ring *ring, const int skb_size) ++{ ++ struct net_device *dev; ++ struct sk_buff *skb; ++ struct vxge_rx_priv *rx_priv; ++ ++ dev = ring->ndev; ++ vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d", ++ ring->ndev->name, __func__, __LINE__); ++ ++ rx_priv = vxge_hw_ring_rxd_private_get(dtrh); ++ ++ /* try to allocate skb first. this one may fail */ ++ skb = netdev_alloc_skb(dev, skb_size + ++ VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN); ++ if (skb == NULL) { ++ vxge_debug_mem(VXGE_ERR, ++ "%s: out of memory to allocate SKB", dev->name); ++ ring->stats.skb_alloc_fail++; ++ return NULL; ++ } ++ ++ vxge_debug_mem(VXGE_TRACE, ++ "%s: %s:%d Skb : 0x%p", ring->ndev->name, ++ __func__, __LINE__, skb); ++ ++ skb_reserve(skb, VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN); ++ ++ rx_priv->skb = skb; ++ rx_priv->skb_data = NULL; ++ rx_priv->data_size = skb_size; ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s: %s:%d Exiting...", ring->ndev->name, __func__, __LINE__); ++ ++ return skb; ++} ++ ++/* ++ * vxge_rx_map ++ */ ++static int vxge_rx_map(void *dtrh, struct vxge_ring *ring) ++{ ++ struct vxge_rx_priv *rx_priv; ++ dma_addr_t dma_addr; ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d", ++ ring->ndev->name, __func__, __LINE__); ++ rx_priv = vxge_hw_ring_rxd_private_get(dtrh); ++ ++ dma_addr = ++ ++ pci_map_single(ring->pdev, rx_priv->skb->data, ++ rx_priv->data_size, PCI_DMA_FROMDEVICE); ++ ++ rx_priv->skb_data = rx_priv->skb->data; ++ ++ if (dma_addr == 0) { ++ ring->stats.pci_map_fail++; ++ return -EIO; ++ } ++ vxge_debug_mem(VXGE_TRACE, ++ "%s: %s:%d 1 buffer mode dma_addr = 0x%llx", ++ ring->ndev->name, __func__, __LINE__, ++ (unsigned long long)dma_addr); ++ vxge_hw_ring_rxd_1b_set(dtrh, dma_addr, rx_priv->data_size); ++ ++ rx_priv->data_dma = dma_addr; ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s: %s:%d Exiting...", ring->ndev->name, __func__, __LINE__); ++ ++ return 0; ++} ++ ++/* ++ * vxge_rx_initial_replenish ++ * Allocation of RxD as an initial replenish procedure. ++ */ ++static enum vxge_hw_status ++vxge_rx_initial_replenish(void *dtrh, void *userdata) ++{ ++ struct vxge_ring *ring = (struct vxge_ring *)userdata; ++ struct vxge_rx_priv *rx_priv; ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d", ++ ring->ndev->name, __func__, __LINE__); ++ if (vxge_rx_alloc(dtrh, ring, ++ VXGE_LL_MAX_FRAME_SIZE(ring->ndev)) == NULL) ++ return VXGE_HW_FAIL; ++ ++ if (vxge_rx_map(dtrh, ring)) { ++ rx_priv = vxge_hw_ring_rxd_private_get(dtrh); ++ dev_kfree_skb(rx_priv->skb); ++ ++ return VXGE_HW_FAIL; ++ } ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s: %s:%d Exiting...", ring->ndev->name, __func__, __LINE__); ++ ++ return VXGE_HW_OK; ++} ++ ++static inline void ++vxge_rx_complete(struct vxge_ring *ring, struct sk_buff *skb, u16 vlan, ++ int pkt_length, struct vxge_hw_ring_rxd_info *ext_info) ++{ ++#ifdef VXGE_LOOPBACK_TEST ++ u8 *mac_address = NULL; ++ u64 mac_addr = 0; ++#endif ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d", ++ ring->ndev->name, __func__, __LINE__); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 29)) ++ skb_record_rx_queue(skb, ring->driver_id); ++#endif ++ skb->protocol = eth_type_trans(skb, ring->ndev); ++ ++ ring->stats.rx_frms++; ++ ring->stats.rx_bytes += pkt_length; ++ ++ ++ if (skb->pkt_type == PACKET_MULTICAST) ++ ring->stats.rx_mcast++; ++ ++ ++ ++ ++ vxge_debug_rx(VXGE_TRACE, ++ "%s: %s:%d skb protocol = %d", ++ ring->ndev->name, __func__, __LINE__, skb->protocol); ++#ifdef VXGE_LOOPBACK_TEST ++ if (skb->protocol != ntohs(ETH_P_ARP)) { ++ /* Store the vpath id in the skb ++ * control buffer, this is used in the ++ * transmit to get the vpath to ++ * route the packet from */ ++ snprintf(skb->cb, sizeof(int), "%d", ring->driver_id); ++ ++ /* point data back to mac header */ ++ skb_push(skb, ETH_HLEN); ++ ++ mac_address = (u8 *)&mac_addr; ++ /* swap the source and destination mac ++ * addresses ++ */ ++ memcpy(mac_address, &skb->data[ETH_ALEN], ETH_ALEN); ++ memcpy(&skb->data[ETH_ALEN], &skb->data[0], ETH_ALEN); ++ memcpy(&skb->data[0], mac_address, ETH_ALEN); ++ ++ vxge_xmit(skb, ring->ndev); ++ return; ++ } else { ++ /* It is an ARP packet, send it to ++ * the Linux stack */ ++ memset(skb->cb, 0, sizeof(skb->cb)); ++ ++ if (ring->napi_enable) ++ netif_receive_skb(skb); ++ else ++ netif_rx(skb); ++ } ++#else ++ if (ring->lro_enable == VXGE_HW_GRO_ENABLE) { ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ++ if (ring->rx_vlan_stripped && ext_info->vlan) ++ if (ext_info->fast_path_eligible) ++ vlan_gro_receive(ring->napi_p, ring->vlgrp, ++ ext_info->vlan, skb); ++ else ++ vlan_hwaccel_receive_skb(skb, ring->vlgrp,vlan); ++ else ++ if (ext_info->fast_path_eligible) ++ napi_gro_receive(ring->napi_p, skb); ++ else ++ netif_receive_skb(skb); ++#endif ++ } else { ++ if (ring->rx_vlan_stripped && vlan) { ++ if (ring->napi_enable) ++ vlan_hwaccel_receive_skb(skb, ring->vlgrp, vlan); ++ else ++ vlan_hwaccel_rx(skb, ring->vlgrp, vlan); ++ } else { ++ if (ring->napi_enable) ++ netif_receive_skb(skb); ++ else ++ netif_rx(skb); ++ } ++ } ++#endif ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s: %s:%d Exiting...", ring->ndev->name, __func__, __LINE__); ++} ++ ++static inline void vxge_re_pre_post(void *dtr, struct vxge_ring *ring, ++ struct vxge_rx_priv *rx_priv) ++{ ++ pci_dma_sync_single_for_device(ring->pdev, ++ rx_priv->data_dma, rx_priv->data_size, PCI_DMA_FROMDEVICE); ++ ++ vxge_hw_ring_rxd_1b_set(dtr, rx_priv->data_dma, rx_priv->data_size); ++ vxge_hw_ring_rxd_pre_post(ring->handle, dtr); ++} ++ ++static inline void ++vxge_lro_flush_sessions(struct vxge_hw_sw_lro *lro, ++ struct vxge_ring *ring) ++{ ++ while (NULL != (lro = (struct vxge_hw_sw_lro *) ++ vxge_hw_sw_lro_next_session_get(ring->handle, lro))) { ++ vxge_hw_update_L3L4_header(ring->handle, lro); ++ vxge_rx_complete(ring, lro->os_buf, lro->vlan_tag, ++ lro->os_buf->len, NULL); ++ vxge_hw_sw_lro_session_close(ring->handle, lro); ++ lro = NULL; ++ } ++} ++ ++static inline void vxge_post(struct vxge_ring *ring, int *dtr_cnt, ++ void **first_dtr, void *post_dtr, ++ struct __vxge_hw_ring *ringh) ++{ ++ int dtr_count = *dtr_cnt; ++ ++ /* There is no need to avoid race condition in the RxD ++ * replenishment process when the doorbell mode is employed. ++ * This is because the doorbell write is made after the host ++ * ownership bit of an RxD is set, and there will be at ++ * least 2 usec interval before the read from the adapter to ++ * fetch this RxD arrives. ++ * The noticeable improvement in throughput at smaller MTU sizes ++ * can likely be attributed to this modification. ++ */ ++ if (ring->doorbell_mode == VXGE_HW_DOORBELL_MODE_ENABLE) { ++ vxge_hw_ring_rxd_post_post(ringh, post_dtr); ++ ++ /* Instead of sending the doorbell write at the end of the ++ * RxD replenishment process, we need to do this as soon as ++ * rxds_limit is reached. Therefore, we need to evaluate ++ * rxds_limit condition after each RxD is replenished. ++ * The noticeable improvement in throughput at larger MTU sizes ++ * can likely be attributed to this step. ++ */ ++ vxge_hw_vpath_doorbell_rx(ringh); ++ } ++ else { ++ if ((*dtr_cnt % VXGE_HW_RXSYNC_FREQ_CNT) == 0) { ++ if (*first_dtr) ++ vxge_hw_ring_rxd_post_post_wmb(ringh, ++ *first_dtr); ++ *first_dtr = post_dtr; ++ } else ++ vxge_hw_ring_rxd_post_post(ringh, post_dtr); ++ dtr_count++; ++ *dtr_cnt = dtr_count; ++ } ++} ++ ++/* ++ * vxge_rx_1b_compl ++ * ++ * If the interrupt is because of a received frame or if the receive ring ++ * contains fresh as yet un-processed frames, this function is called. ++ */ ++enum vxge_hw_status ++vxge_rx_1b_compl(struct __vxge_hw_ring *ringh, void *dtr, ++ u8 t_code, void *userdata) ++{ ++ struct vxge_ring *ring = (struct vxge_ring *)userdata; ++ struct net_device *dev = ring->ndev; ++ unsigned int dma_sizes; ++ void *first_dtr = NULL; ++ int dtr_cnt = 0; ++ int data_size; ++ dma_addr_t data_dma; ++ int pkt_length; ++ struct sk_buff *skb; ++ struct vxge_rx_priv *rx_priv; ++ struct vxge_hw_ring_rxd_info ext_info; ++ struct vxge_hw_sw_lro *lro = NULL; ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(ring->ndev); ++ vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d", ++ ring->ndev->name, __func__, __LINE__); ++ ring->pkts_processed = 0; ++ ++ vxge_hw_ring_replenish(ringh, 0); ++ ++ do { ++ prefetch((char *)dtr + L1_CACHE_BYTES); ++ rx_priv = vxge_hw_ring_rxd_private_get(dtr); ++ skb = rx_priv->skb; ++ data_size = rx_priv->data_size; ++ data_dma = rx_priv->data_dma; ++ prefetch(rx_priv->skb_data); ++ ++ vxge_debug_rx(VXGE_TRACE, ++ "%s: %s:%d skb = 0x%p", ++ ring->ndev->name, __func__, __LINE__, skb); ++ ++ vxge_hw_ring_rxd_1b_get(ringh, dtr, &dma_sizes); ++ pkt_length = dma_sizes; ++ ++ pkt_length -= ETH_FCS_LEN; ++ ++ vxge_debug_rx(VXGE_TRACE, ++ "%s: %s:%d Packet Length = %d", ++ ring->ndev->name, __func__, __LINE__, pkt_length); ++ ++ vxge_hw_ring_rxd_1b_info_get(ringh, dtr, &ext_info); ++ ++ /* check skb validity */ ++ vxge_assert(skb); ++ ++ prefetch((char *)skb + L1_CACHE_BYTES); ++ if (unlikely(t_code)) { ++ ++ ++ if (vxge_hw_ring_handle_tcode(ringh, dtr, t_code) != ++ VXGE_HW_OK) { ++ ++ ring->stats.rx_errors++; ++ vxge_debug_rx(VXGE_TRACE, ++ "%s: %s :%d Rx T_code is %d", ++ ring->ndev->name, __func__, ++ __LINE__, t_code); ++ ++ /* If the t_code is not supported and if the ++ * t_code is other than 0x5 (unparseable packet ++ * such as unknown UPV6 header), Drop it !!! ++ */ ++ vxge_re_pre_post(dtr, ring, rx_priv); ++ vxge_post(ring, &dtr_cnt, &first_dtr, ++ dtr, ringh); ++ ring->stats.rx_dropped++; ++ continue; ++ } ++ } ++ ++ if (pkt_length > VXGE_LL_RX_COPY_THRESHOLD) { ++ ++ if (vxge_rx_alloc(dtr, ring, data_size) != NULL) { ++ ++ if (!vxge_rx_map(dtr, ring)) { ++ skb_put(skb, pkt_length); ++ ++ vxge_dma_unmap(ring->pdev, data_dma, ++ data_size, PCI_DMA_FROMDEVICE); ++ ++ vxge_hw_ring_rxd_pre_post(ringh, dtr); ++ vxge_post(ring, &dtr_cnt, &first_dtr, ++ dtr, ringh); ++ } else { ++ dev_kfree_skb(rx_priv->skb); ++ rx_priv->skb = skb; ++ rx_priv->data_size = data_size; ++ vxge_re_pre_post(dtr, ring, rx_priv); ++ vxge_post(ring, &dtr_cnt, &first_dtr, ++ dtr, ringh); ++ ring->stats.rx_dropped++; ++ break; ++ } ++ } else { ++ vxge_re_pre_post(dtr, ring, rx_priv); ++ vxge_post(ring, &dtr_cnt, &first_dtr, ++ dtr, ringh); ++ ring->stats.rx_dropped++; ++ break; ++ } ++ } else { ++ struct sk_buff *skb_up; ++ ++ skb_up = netdev_alloc_skb(dev, pkt_length + ++ VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN); ++ if (skb_up != NULL) { ++ skb_reserve(skb_up, ++ VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN); ++ ++ pci_dma_sync_single_for_cpu(ring->pdev, ++ data_dma, data_size, ++ PCI_DMA_FROMDEVICE); ++ ++ vxge_debug_mem(VXGE_TRACE, ++ "%s: %s:%d skb_up = %p", ++ ring->ndev->name, __func__, ++ __LINE__, skb); ++ memcpy(skb_up->data, skb->data, pkt_length); ++ ++ vxge_re_pre_post(dtr, ring, rx_priv); ++ vxge_post(ring, &dtr_cnt, &first_dtr, ++ dtr, ringh); ++ /* will netif_rx small SKB instead */ ++ skb = skb_up; ++ skb_put(skb, pkt_length); ++ } else { ++ vxge_re_pre_post(dtr, ring, rx_priv); ++ vxge_post(ring, &dtr_cnt, &first_dtr, ++ dtr, ringh); ++ ++ vxge_debug_rx(VXGE_ERR, ++ "%s: vxge_rx_1b_compl: out of " ++ "memory", dev->name); ++ ring->stats.skb_alloc_fail++; ++ break; ++ } ++ } ++ ++ if ((vdev->rx_csum) && (ext_info.fast_path_eligible)) { ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ ++ if ((ring->lro_enable) && ++ (ring->lro_enable != VXGE_HW_GRO_ENABLE)) { ++ u32 tcpp_len; ++ enum vxge_hw_status ret; ++ ext_info.dev = ring->ndev; ++ ext_info.vlgrp = ring->vlgrp; ++ ret = vxge_hw_sw_lro_rx_process(ringh, ++ &ext_info, skb->data, ++ &tcpp_len, &lro); ++ ++ if (VXGE_HW_INF_SW_LRO_CONT == ret) { ++ struct sk_buff *first, *tmp; ++ first = lro->os_buf; ++ lro->os_buf->len += tcpp_len; ++ lro->os_buf->data_len = lro->frags_len; ++ if ((ring->aggr_ack) && ++ (tcpp_len == 0)) { ++ dev_kfree_skb_any(skb); ++ continue; ++ } ++ skb_pull(skb, (skb->len - tcpp_len)); ++ ++ if (skb_shinfo(first)->frag_list) { ++ tmp = ++ skb_shinfo(first)->frag_list; ++ while (tmp->next) ++ tmp = tmp->next; ++ tmp->next = skb; ++ } else ++ skb_shinfo(first)->frag_list ++ = skb; ++ ++ lro->os_buf->truesize += skb->truesize; ++ ++ continue; ++ } else if (VXGE_HW_INF_SW_LRO_BEGIN == ret) { ++ lro->os_buf = skb; ++ continue; ++ } else if (VXGE_HW_INF_SW_LRO_FLUSH_SESSION ++ == ret) { ++ struct sk_buff *first, *tmp; ++ lro->os_buf->len += tcpp_len; ++ lro->os_buf->data_len = lro->frags_len; ++ if ((ring->aggr_ack) && ++ (tcpp_len == 0)) { ++ dev_kfree_skb_any(skb); ++ continue; ++ } ++ skb_pull(skb, (skb->len - tcpp_len)); ++ first = lro->os_buf; ++ if (skb_shinfo(first)->frag_list) { ++ tmp = ++ skb_shinfo(first)->frag_list; ++ while (tmp->next) ++ tmp = tmp->next; ++ tmp->next = skb; ++ } else ++ skb_shinfo(first)->frag_list ++ = skb; ++ ++ lro->os_buf->truesize += skb->truesize; ++ ++ vxge_rx_complete(ring, lro->os_buf, ++ lro->vlan_tag, ++ lro->os_buf->len, ++ NULL); ++ vxge_hw_sw_lro_session_close(ringh, ++ lro); ++ lro = NULL; ++ continue; ++ } else if (VXGE_HW_INF_SW_LRO_FLUSH_BOTH == ++ ret) { ++ lro->os_buf->data_len = lro->frags_len; ++ vxge_rx_complete(ring, lro->os_buf, ++ lro->vlan_tag, ++ lro->os_buf->len, ++ NULL); ++ vxge_hw_sw_lro_session_close(ringh, ++ lro); ++ lro = NULL; ++ } ++ } ++ } else ++ skb->ip_summed = CHECKSUM_NONE; ++ ++ vxge_rx_complete(ring, skb, ext_info.vlan, ++ pkt_length, &ext_info); ++ if (ring->napi_enable) { ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) ++ /* NEW NAPI */ ++ ring->budget--; ++ ring->pkts_processed++; ++ if (!ring->budget) ++ break; ++#else ++ /* OLD NAPI */ ++ ring->pkts_to_process -= 1; ++ if (!ring->pkts_to_process) ++ break; ++#endif ++ } ++ } while (vxge_hw_ring_rxd_next_completed(ringh, &dtr, ++ &t_code) == VXGE_HW_OK); ++ ++ /* The first_dtr pointer is initialized for the non doorbel case only. */ ++ if (first_dtr) ++ vxge_hw_ring_rxd_post_post_wmb(ringh, first_dtr); ++ dev->last_rx = jiffies; ++ ++ if ((ring->lro_enable) && (ring->lro_enable != VXGE_HW_GRO_ENABLE)) { ++ if (lro != NULL) { ++ vxge_hw_update_L3L4_header(ringh, lro); ++ vxge_rx_complete(ring, lro->os_buf, ++ lro->vlan_tag, lro->os_buf->len, ++ NULL); ++ vxge_hw_sw_lro_session_close(ringh, lro); ++ lro = NULL; ++ } ++ ++ /* Flush all pending LRO session */ ++ vxge_lro_flush_sessions(lro, ring); ++ } ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s:%d Exiting...", ++ __func__, __LINE__); ++ return VXGE_HW_OK; ++} ++ ++/* ++ * vxge_xmit_compl ++ * ++ * If an interrupt was raised to indicate DMA complete of the Tx packet, ++ * this function is called. It identifies the last TxD whose buffer was ++ * freed and frees all skbs whose data have already DMA'ed into the NICs ++ * internal memory. ++ */ ++enum vxge_hw_status ++vxge_xmit_compl(struct __vxge_hw_fifo *fifo_hw, void *dtr, ++ enum vxge_hw_fifo_tcode t_code, void *userdata, ++ struct sk_buff ***skb_ptr, int nr_skb, int *more) ++{ ++ struct vxge_fifo *fifo = (struct vxge_fifo *)userdata; ++ struct sk_buff *skb, **done_skb = *skb_ptr; ++ int pkt_cnt = 0; ++ ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s:%d Entered....", __func__, __LINE__); ++ ++ do { ++ int frg_cnt; ++ skb_frag_t *frag; ++ int i = 0, j; ++ struct vxge_tx_priv *txd_priv = ++ vxge_hw_fifo_txdl_private_get(dtr); ++ ++ skb = txd_priv->skb; ++ frg_cnt = skb_shinfo(skb)->nr_frags; ++ frag = &skb_shinfo(skb)->frags[0]; ++ ++ vxge_debug_tx(VXGE_TRACE, ++ "%s: %s:%d fifo_hw = %p dtr = %p " ++ "tcode = 0x%x", fifo->ndev->name, __func__, ++ __LINE__, fifo_hw, dtr, t_code); ++ /* check skb validity */ ++ vxge_assert(skb); ++ vxge_debug_tx(VXGE_TRACE, ++ "%s: %s:%d skb = %p itxd_priv = %p frg_cnt = %d", ++ fifo->ndev->name, __func__, __LINE__, ++ skb, txd_priv, frg_cnt); ++ if (unlikely(t_code)) { ++ fifo->stats.tx_errors++; ++ vxge_debug_tx(VXGE_ERR, ++ "%s: tx: dtr %p completed due to " ++ "error t_code %01x", fifo->ndev->name, ++ dtr, t_code); ++ vxge_hw_fifo_handle_tcode(fifo_hw, dtr, t_code); ++ } ++ ++ ++ /* for unfragmented skb */ ++ vxge_dma_unmap(fifo->pdev, txd_priv->dma_buffers[i++], ++ skb_headlen(skb), PCI_DMA_TODEVICE); ++ ++ for (j = 0; j < frg_cnt; j++) { ++ pci_unmap_page(fifo->pdev, ++ txd_priv->dma_buffers[i++], ++ frag->size, PCI_DMA_TODEVICE); ++ frag += 1; ++ } ++ ++ ++ vxge_hw_fifo_txdl_free(fifo_hw, dtr); ++ ++ /* Updating the statistics block */ ++ fifo->stats.tx_frms++; ++ fifo->stats.tx_bytes += skb->len; ++ ++ *done_skb++ = skb; ++ ++ if (--nr_skb <= 0) { ++ *more = 1; ++ break; ++ } ++ ++ pkt_cnt++; ++ if (pkt_cnt > fifo->indicate_max_pkts) ++ break; ++ ++ } while (vxge_hw_fifo_txdl_next_completed(fifo_hw, ++ &dtr, &t_code) == VXGE_HW_OK); ++ ++ *skb_ptr = done_skb; ++ vxge_wake_tx_queue(fifo, skb); ++ ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s: %s:%d Exiting...", ++ fifo->ndev->name, __func__, __LINE__); ++ return VXGE_HW_OK; ++} ++ ++#ifndef VXGE_LOOPBACK_TEST ++ ++/* select a vpath to trasmit the packet */ ++static u32 vxge_get_vpath_no(struct vxgedev *vdev, struct sk_buff *skb, ++ int *do_lock) ++{ ++ u16 queue_len, counter = 0; ++ if (skb->protocol == htons(ETH_P_IP)) { ++ struct iphdr *ip; ++ struct tcphdr *th; ++ ++ ip = ip_hdr(skb); ++ ++ if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) { ++ th = (struct tcphdr *)(((unsigned char *)ip) + ++ ip->ihl*4); ++ ++ queue_len = vdev->no_of_vpath; ++ counter = (ntohs(th->source) + ++ ntohs(th->dest)) & ++ vdev->vpath_selector[queue_len - 1]; ++ if (counter >= queue_len) ++ counter = queue_len - 1; ++ ++ if (ip->protocol == IPPROTO_UDP) { ++#ifdef NETIF_F_LLTX ++ *do_lock = 0; ++#endif ++ } ++ } ++ } ++ return counter; ++} ++ ++#endif ++static enum vxge_hw_status vxge_search_mac_addr_in_list( ++ struct vxge_vpath *vpath, u64 del_mac) ++{ ++ struct list_head *entry, *next; ++ list_for_each_safe(entry, next, &vpath->mac_addr_list) { ++ if (((struct vxge_mac_addrs *)entry)->macaddr == del_mac) ++ return TRUE; ++ } ++ return FALSE; ++} ++ ++int vxge_learn_mac(struct vxge_fifo *fifo, u8 *mac_header) ++{ ++ struct macInfo mac_info; ++ u8 *mac_address = NULL; ++ u64 mac_addr = 0, vpath_vector = 0; ++ int vpath_idx = 0; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct vxge_vpath *vpath = NULL; ++ struct __vxge_hw_device *hldev; ++ int ret = 0; ++ unsigned long flags = 0; ++ ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(fifo->ndev); ++ ++ hldev = (struct __vxge_hw_device *) pci_get_drvdata(vdev->pdev); ++ ++ mac_address = (u8 *)&mac_addr; ++ memcpy(mac_address, mac_header, ETH_ALEN); ++ ++ if (unlikely(!vxge_spin_trylock(&vdev->addr_learn_lock, flags))) ++ return ret; ++ ++ /* Is this mac address already in the list? */ ++ for (vpath_idx = 0; vpath_idx < vdev->no_of_vpath; vpath_idx++) { ++ vpath = &vdev->vpaths[vpath_idx]; ++ if (vxge_search_mac_addr_in_list(vpath, mac_addr)) { ++ ret = vpath_idx; ++ goto out; ++ } ++ } ++ ++ memset(&mac_info, 0, sizeof(struct macInfo)); ++ memcpy(mac_info.macaddr, mac_header, ETH_ALEN); ++ ++ /* Any vpath has room to add mac address to its da table? */ ++ for (vpath_idx = 0; vpath_idx < vdev->no_of_vpath; vpath_idx++) { ++ vpath = &vdev->vpaths[vpath_idx]; ++ if (vpath->mac_addr_cnt < vpath->max_mac_addr_cnt) { ++ /* Add this mac address to this vpath */ ++ mac_info.vpath_no = vpath_idx; ++ mac_info.state = VXGE_LL_MAC_ADDR_IN_DA_TABLE; ++ status = vxge_add_mac_addr(vdev, &mac_info); ++ if (status != VXGE_HW_OK) ++ ret = -EPERM; ++ else ++ ret = vpath_idx; ++ goto out; ++ } ++ } ++ ++ mac_info.state = VXGE_LL_MAC_ADDR_IN_LIST; ++ vpath_idx = 0; ++ mac_info.vpath_no = vpath_idx; ++ /* Is the first vpath already selected as catch-basin ? */ ++ vpath = &vdev->vpaths[vpath_idx]; ++ if (vpath->mac_addr_cnt > vpath->max_mac_addr_cnt) { ++ /* Add this mac address to this vpath */ ++ if (FALSE == vxge_mac_list_add(vpath, &mac_info)) ++ ret = -EPERM; ++ else ++ ret = vpath_idx; ++ goto out; ++ } ++ ++ /* Select first vpath as catch-basin */ ++ vpath_vector = vxge_mBIT(vpath->device_id); ++ status = vxge_hw_mgmt_reg_write(vpath->vdev->devh, ++ vxge_hw_mgmt_reg_type_mrpcim, ++ 0, ++ (ulong)offsetof( ++ struct vxge_hw_mrpcim_reg, ++ rts_mgr_cbasin_cfg), ++ vpath_vector); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_tx(VXGE_ERR, ++ "%s: Unable to set the vpath-%d in catch-basin mode", ++ VXGE_DRIVER_NAME, vpath->device_id); ++ ret = -EPERM; ++ goto out; ++ } ++ ++ if (FALSE == vxge_mac_list_add(vpath, &mac_info)) { ++ ret = -EPERM; ++ goto out; ++ } ++ ++ ret = vpath_idx; ++out: ++ vxge_spin_unlock(&vdev->addr_learn_lock, flags); ++ return ret; ++} ++ ++ ++ ++/** ++ * vxge_xmit ++ * @skb : the socket buffer containing the Tx data. ++ * @dev : device pointer. ++ * ++ * This function is the Tx entry point of the driver. Neterion NIC supports ++ * certain protocol assist features on Tx side, namely CSO, S/G, LSO. ++ * NOTE: when device cant queue the pkt, just the trans_start variable will ++ * not be upadted. ++*/ ++static int ++vxge_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct vxge_fifo *fifo = NULL; ++ void *dtr_priv; ++ void *dtr = NULL; ++ struct vxgedev *vdev = NULL; ++ enum vxge_hw_status status; ++ int frg_cnt, first_frg_len; ++ skb_frag_t *frag; ++ int i = 0, j = 0, avail, mss = 0; ++ u64 dma_pointer; ++ struct vxge_tx_priv *txdl_priv = NULL; ++ struct __vxge_hw_fifo *fifo_hw; ++#if (defined(NETIF_F_TSO) || defined(NETIF_F_UFO)) ++ int offload_type; ++#endif ++ unsigned long flags = 0; ++ int vpath_no = 0; ++ int do_spin_tx_lock = 1; ++ struct __vxge_hw_device *hldev; ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d", ++ dev->name, __func__, __LINE__); ++ ++ /* A buffer with no data will be dropped */ ++ if (unlikely(skb->len <= 0)) { ++ vxge_debug_tx(VXGE_ERR, ++ "%s: Buffer has no data..", dev->name); ++ dev_kfree_skb(skb); ++ return NETDEV_TX_OK; ++ } ++ ++ vdev = (struct vxgedev *)netdev_priv(dev); ++ hldev = (struct __vxge_hw_device *)pci_get_drvdata(vdev->pdev); ++ ++ if (unlikely(!is_vxge_card_up(vdev))) { ++ vxge_debug_tx(VXGE_ERR, ++ "%s: vdev not initialized", dev->name); ++ dev_kfree_skb(skb); ++ return NETDEV_TX_OK; ++ } ++ ++#ifdef VXGE_LOOPBACK_TEST ++ vpath_no = simple_strtol(skb->cb, NULL, 0); ++#else ++ ++ if (vdev->config.tx_steering_type == TX_MULTIQ_STEERING) ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 26)) ++ vpath_no = skb_get_queue_mapping(skb); ++#else ++ vpath_no = vxge_get_vpath_no(vdev, skb, &do_spin_tx_lock); ++#endif ++ else if (vdev->config.tx_steering_type == TX_PORT_STEERING) ++ vpath_no = vxge_get_vpath_no(vdev, skb, &do_spin_tx_lock); ++ ++ ++ vxge_debug_tx(VXGE_TRACE, "%s: vpath_no= %d", dev->name, vpath_no); ++#endif ++ ++ if (vpath_no >= vdev->no_of_vpath) ++ vpath_no = 0; ++ ++ fifo = &vdev->vpaths[vpath_no].fifo; ++ fifo_hw = fifo->handle; ++ ++ if (do_spin_tx_lock) ++ spin_lock_irqsave(&fifo->tx_lock, flags); ++ else { ++ if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags))) ++ return NETDEV_TX_LOCKED; ++ } ++ ++ if (vdev->config.tx_steering_type == TX_MULTIQ_STEERING) { ++ if (vxge_netif_subqueue_stopped(dev, skb, fifo->driver_id)) { ++ spin_unlock_irqrestore(&fifo->tx_lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ } else if (unlikely(fifo->queue_state == VPATH_QUEUE_STOP)) { ++ if (netif_queue_stopped(dev)) { ++ spin_unlock_irqrestore(&fifo->tx_lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ } ++ avail = vxge_hw_fifo_free_txdl_count_get(fifo_hw); ++ if (avail == 0) { ++ spin_unlock_irqrestore(&fifo->tx_lock, flags); ++ VXGE_COMPLETE_VPATH_TX(fifo); ++ if (do_spin_tx_lock) ++ spin_lock_irqsave(&fifo->tx_lock, flags); ++ else { ++ if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, ++ flags))) ++ return NETDEV_TX_LOCKED; ++ } ++ avail = vxge_hw_fifo_free_txdl_count_get(fifo_hw); ++ if (avail == 0) { ++ vxge_debug_tx(VXGE_ERR, ++ "%s: No free TXDs available", dev->name); ++ fifo->stats.txd_not_free++; ++ vxge_stop_tx_queue(fifo); ++ goto _exit2; ++ } ++ } ++ ++ /* Last TXD? Stop tx queue to avoid dropping packets. TX ++ * completion will resume the queue. ++ */ ++ if (avail == 1) ++ vxge_stop_tx_queue(fifo); ++ ++ status = vxge_hw_fifo_txdl_reserve(fifo_hw, &dtr, &dtr_priv); ++ if (unlikely(status != VXGE_HW_OK)) { ++ vxge_debug_tx(VXGE_ERR, ++ "%s: Out of descriptors .", dev->name); ++ fifo->stats.txd_out_of_desc++; ++ vxge_stop_tx_queue(fifo); ++ goto _exit2; ++ } ++ ++ vxge_debug_tx(VXGE_TRACE, ++ "%s: %s:%d fifo_hw = %p dtr = %p dtr_priv = %p", ++ dev->name, __func__, __LINE__, ++ fifo_hw, dtr, dtr_priv); ++ ++ if (vdev->vlgrp && vlan_tx_tag_present(skb)) { ++ u16 vlan_tag = vlan_tx_tag_get(skb); ++ vxge_hw_fifo_txdl_vlan_set(dtr, vlan_tag); ++ } ++ ++ first_frg_len = skb_headlen(skb); ++ ++ dma_pointer = ++ ++ pci_map_single(fifo->pdev, ++ skb->data, first_frg_len, PCI_DMA_TODEVICE); ++ ++ ++ if (unlikely(vxge_do_pci_dma_mapping_error(fifo->pdev, dma_pointer))) { ++ vxge_hw_fifo_txdl_free(fifo_hw, dtr); ++ vxge_stop_tx_queue(fifo); ++ fifo->stats.pci_map_fail++; ++ goto _exit2; ++ } ++ ++ txdl_priv = vxge_hw_fifo_txdl_private_get(dtr); ++ txdl_priv->skb = skb; ++ txdl_priv->dma_buffers[j] = dma_pointer; ++ ++ frg_cnt = skb_shinfo(skb)->nr_frags; ++ vxge_debug_tx(VXGE_TRACE, ++ "%s: %s:%d skb = %p txdl_priv = %p " ++ "frag_cnt = %d dma_pointer = 0x%llx", dev->name, ++ __func__, __LINE__, skb, txdl_priv, ++ frg_cnt, (unsigned long long)dma_pointer); ++ ++ vxge_hw_fifo_txdl_buffer_set(fifo_hw, dtr, j++, dma_pointer, ++ first_frg_len); ++ ++ frag = &skb_shinfo(skb)->frags[0]; ++ for (i = 0; i < frg_cnt; i++) { ++ /* ignore 0 length fragment */ ++ if (!frag->size) ++ continue; ++ ++ dma_pointer = ++ ++ (u64)pci_map_page( ++ fifo->pdev, frag->page, ++ frag->page_offset, frag->size, ++ PCI_DMA_TODEVICE); ++ ++ ++ if (unlikely(vxge_do_pci_dma_mapping_error(fifo->pdev, dma_pointer))) ++ goto _exit0; ++ vxge_debug_tx(VXGE_TRACE, ++ "%s: %s:%d frag = %d dma_pointer = 0x%llx", ++ dev->name, __func__, __LINE__, i, ++ (unsigned long long)dma_pointer); ++ ++ txdl_priv->dma_buffers[j] = dma_pointer; ++ vxge_hw_fifo_txdl_buffer_set(fifo_hw, dtr, j++, dma_pointer, ++ frag->size); ++ frag += 1; ++ } ++#ifdef NETIF_F_TSO ++ offload_type = vxge_offload_type(skb); ++ ++ if (offload_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4)) { ++ ++ mss = skb_is_gso(skb); ++ if (mss) { ++ vxge_debug_tx(VXGE_TRACE, ++ "%s: %s:%d mss = %d", ++ dev->name, __func__, __LINE__, mss); ++ vxge_hw_fifo_txdl_mss_set(dtr, mss); ++ } else { ++ vxge_assert(skb->len <= ++ dev->mtu + VXGE_HW_MAC_HEADER_MAX_SIZE); ++ vxge_assert(0); ++ goto _exit1; ++ } ++ } ++#endif ++#ifdef NETIF_F_UFO ++ offload_type = vxge_offload_type(skb); ++ ++ if (offload_type == SKB_GSO_UDP) { ++ ++ struct iphdr *ip; ++ mss = vxge_udp_mss(skb); ++ ++ mss &= ~7; /* MSS must be a multiple of 8 bytes */ ++ if (mss) { ++ vxge_debug_tx(VXGE_TRACE, ++ "%s: %s:%d mss = %d", ++ dev->name, __func__, __LINE__, mss); ++ vxge_hw_fifo_txdl_mss_set(dtr, mss); ++ if (skb->protocol == htons(ETH_P_IP)) { ++ /* hw will spilt the packet in to multiple ++ * mss sized packets, adjust the ip->id */ ++ ip = ip_hdr(skb); ++ ip->id = ip->id * ((skb->len / mss) + 1); ++ } ++ } else { ++ vxge_assert(skb->len <= ++ dev->mtu + VXGE_HW_MAC_HEADER_MAX_SIZE); ++ vxge_assert(0); ++ goto _exit1; ++ } ++ } ++#endif ++ ++ /* configure tx_bw_limit based on mss/mtu */ ++ if (((mss) && (vdev->prev_mss != mss)) || (!mss)) { ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ int vp_id = vdev->vpaths[i].device_id; ++ status = vxge_hw_vpath_bandwidth_set(vdev->devh, ++ vp_id, ++ VXGE_HW_CHANNEL_TYPE_FIFO, ++ hldev->config.vp_config[vp_id].tx_bw_limit, ++ /* if mss=0, configure mtu value */ ++ (mss) ? mss : vdev->mtu); ++ ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: fatal: tx_bw_limit_set failed", dev->name); ++ goto _exit1; ++ } ++ } ++ vdev->prev_mss = mss; ++ } ++ ++ if (skb->ip_summed == CHECKSUM_PARTIAL) ++ vxge_hw_fifo_txdl_cksum_set_bits(dtr, ++ VXGE_HW_FIFO_TXD_TX_CKO_IPV4_EN | ++ VXGE_HW_FIFO_TXD_TX_CKO_TCP_EN | ++ VXGE_HW_FIFO_TXD_TX_CKO_UDP_EN); ++ ++ i = vdev->vpaths[vpath_no].device_id; ++ vxge_hw_fifo_txdl_post(fifo_hw, ++ dtr, ++ hldev->config.vp_config[i].tx_bw_limit); ++ ++ dev->trans_start = jiffies; ++ spin_unlock_irqrestore(&fifo->tx_lock, flags); ++ ++ VXGE_COMPLETE_VPATH_TX(fifo); ++ vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d Exiting...", ++ dev->name, __func__, __LINE__); ++ return 0; ++ ++_exit0: ++ vxge_debug_tx(VXGE_TRACE, "%s: pci_map_page failed", dev->name); ++ ++_exit1: ++ j = 0; ++ frag = &skb_shinfo(skb)->frags[0]; ++ ++ ++ pci_unmap_single(fifo->pdev, txdl_priv->dma_buffers[j++], ++ skb_headlen(skb), PCI_DMA_TODEVICE); ++ ++ for (; j < i; j++) { ++ pci_unmap_page(fifo->pdev, ++ txdl_priv->dma_buffers[j], ++ frag->size, ++ PCI_DMA_TODEVICE); ++ frag += 1; ++ } ++ ++ ++ vxge_hw_fifo_txdl_free(fifo_hw, dtr); ++_exit2: ++ dev_kfree_skb(skb); ++ spin_unlock_irqrestore(&fifo->tx_lock, flags); ++ VXGE_COMPLETE_VPATH_TX(fifo); ++ ++ return 0; ++} ++ ++/* ++ * vxge_rx_term ++ * ++ * Function will be called by hw function to abort all outstanding receive ++ * descriptors. ++ */ ++static void ++vxge_rx_term(void *dtrh, enum vxge_hw_rxd_state state, void *userdata) ++{ ++ struct vxge_ring *ring = (struct vxge_ring *)userdata; ++ struct vxge_rx_priv *rx_priv = ++ vxge_hw_ring_rxd_private_get(dtrh); ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d", ++ ring->ndev->name, __func__, __LINE__); ++ if (state != VXGE_HW_RXD_STATE_POSTED) ++ return; ++ ++ vxge_dma_unmap(ring->pdev, rx_priv->data_dma, ++ rx_priv->data_size, PCI_DMA_FROMDEVICE); ++ ++ dev_kfree_skb(rx_priv->skb); ++ rx_priv->skb_data = NULL; ++ ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s: %s:%d Exiting...", ++ ring->ndev->name, __func__, __LINE__); ++} ++ ++/* ++ * vxge_tx_term ++ * ++ * Function will be called to abort all outstanding tx descriptors ++ */ ++static void ++vxge_tx_term(void *dtrh, enum vxge_hw_txdl_state state, void *userdata) ++{ ++ struct vxge_fifo *fifo = (struct vxge_fifo *)userdata; ++ skb_frag_t *frag; ++ int i = 0, j, frg_cnt; ++ struct vxge_tx_priv *txd_priv = vxge_hw_fifo_txdl_private_get(dtrh); ++ struct sk_buff *skb = txd_priv->skb; ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s:%d", __func__, __LINE__); ++ ++ if (state != VXGE_HW_TXDL_STATE_POSTED) ++ return; ++ ++ /* check skb validity */ ++ vxge_assert(skb); ++ frg_cnt = skb_shinfo(skb)->nr_frags; ++ frag = &skb_shinfo(skb)->frags[0]; ++ ++ ++ /* for unfragmented skb */ ++ pci_unmap_single(fifo->pdev, txd_priv->dma_buffers[i++], ++ skb_headlen(skb), PCI_DMA_TODEVICE); ++ ++ for (j = 0; j < frg_cnt; j++) { ++ pci_unmap_page(fifo->pdev, txd_priv->dma_buffers[i++], ++ frag->size, PCI_DMA_TODEVICE); ++ frag += 1; ++ } ++ ++ ++ dev_kfree_skb(skb); ++ ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s:%d Exiting...", __func__, __LINE__); ++} ++ ++/** ++ * vxge_set_multicast ++ * @dev: pointer to the device structure ++ * ++ * Entry point for multicast address enable/disable ++ * This function is a driver entry point which gets called by the kernel ++ * whenever multicast addresses must be enabled/disabled. This also gets ++ * called to set/reset promiscuous mode. Depending on the deivce flag, we ++ * determine, if multicast address must be enabled or if promiscuous mode ++ * is to be disabled etc. ++ */ ++static void vxge_set_multicast(struct net_device *dev) ++{ ++ struct dev_mc_list *mclist; ++ struct vxgedev *vdev; ++ int i, mcast_cnt = 0; ++ struct __vxge_hw_device *hldev; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct macInfo mac_info; ++ int vpath_idx = 0; ++ struct vxge_mac_addrs *mac_entry; ++ struct list_head *list_head; ++ struct list_head *entry, *next; ++ u8 *mac_address = NULL; ++ ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s:%d", __func__, __LINE__); ++ ++ vdev = (struct vxgedev *)netdev_priv(dev); ++ hldev = (struct __vxge_hw_device *)vdev->devh; ++ ++ if (unlikely(!is_vxge_card_up(vdev))) ++ return; ++ ++ if ((dev->flags & IFF_ALLMULTI) && (!vdev->all_multi_flg)) { ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ vxge_assert(vdev->vpaths[i].is_open); ++ status = vxge_hw_vpath_mcast_enable( ++ vdev->vpaths[i].handle); ++ vdev->all_multi_flg = 1; ++ } ++ } else if ((dev->flags & IFF_ALLMULTI) && (vdev->all_multi_flg)) { ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ vxge_assert(vdev->vpaths[i].is_open); ++ status = vxge_hw_vpath_mcast_disable( ++ vdev->vpaths[i].handle); ++ vdev->all_multi_flg = 1; ++ } ++ } ++ ++ if (status != VXGE_HW_OK) ++ vxge_debug_init(VXGE_ERR, ++ "failed to %s multicast, status %d", ++ dev->flags & IFF_ALLMULTI ? ++ "enable" : "disable", status); ++ ++ if (dev->flags & IFF_PROMISC) { ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ vxge_assert(vdev->vpaths[i].is_open); ++ ++ if (vdev->config.promisc_all_en) ++ vxge_hw_vpath_promisc_enable( ++ vdev->vpaths[i].handle); ++ else if (vdev->config.promisc_en && ++ (vdev->devh->access_rights & ++ VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) ++ vxge_hw_vpath_promisc_enable( ++ vdev->vpaths[i].handle); ++ else { ++ status = vxge_hw_vpath_mcast_enable( ++ vdev->vpaths[i].handle); ++ vdev->vpaths[i].fifo.addr_learn_en++; ++ } ++ } ++ } else { ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ vxge_assert(vdev->vpaths[i].is_open); ++ ++ if (vdev->config.promisc_all_en) ++ vxge_hw_vpath_promisc_disable( ++ vdev->vpaths[i].handle); ++ else if (vdev->config.promisc_en && ++ (vdev->devh->access_rights & ++ VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) ++ vxge_hw_vpath_promisc_disable( ++ vdev->vpaths[i].handle); ++ ++ if (vdev->vpaths[i].fifo.addr_learn_en) { ++ vdev->vpaths[i].fifo.addr_learn_en--; ++ if (!vdev->vpaths[i].fifo.addr_learn_en) ++ status = vxge_hw_vpath_mcast_disable( ++ vdev->vpaths[i].handle); ++ } ++ } ++ } ++ ++ memset(&mac_info, 0, sizeof(struct macInfo)); ++ /* Update individual M_CAST address list */ ++ if ((!vdev->all_multi_flg) && dev->mc_count) { ++ ++ mcast_cnt = vdev->vpaths[0].mcast_addr_cnt; ++ list_head = &vdev->vpaths[0].mac_addr_list; ++ if ((dev->mc_count + ++ (vdev->vpaths[0].mac_addr_cnt - mcast_cnt)) > ++ vdev->vpaths[0].max_mac_addr_cnt) ++ goto _set_all_mcast; ++ ++ /* Delete previous MC's */ ++ for (i = 0; i < mcast_cnt; i++) { ++ if (!list_empty(list_head)) ++ mac_entry = (struct vxge_mac_addrs *) ++ list_entry(list_head->next, ++ struct vxge_mac_addrs, ++ item); ++ ++ list_for_each_safe(entry, next, list_head) { ++ ++ mac_entry = (struct vxge_mac_addrs *) entry; ++ /* Copy the mac address to delete */ ++ mac_address = (u8 *)&mac_entry->macaddr; ++ memcpy(mac_info.macaddr, mac_address, ETH_ALEN); ++ ++ /* Is this a multicast address */ ++ if (0x01 & mac_info.macaddr[0]) { ++ for (vpath_idx = 0; vpath_idx < ++ vdev->no_of_vpath; ++ vpath_idx++) { ++ mac_info.vpath_no = vpath_idx; ++ status = vxge_del_mac_addr( ++ vdev, ++ &mac_info); ++ } ++ } ++ } ++ } ++ ++ /* Add new ones */ ++ for (i = 0, mclist = dev->mc_list; i < dev->mc_count; ++ i++, mclist = mclist->next) { ++ ++ memcpy(mac_info.macaddr, mclist->dmi_addr, ETH_ALEN); ++ for (vpath_idx = 0; vpath_idx < vdev->no_of_vpath; ++ vpath_idx++) { ++ mac_info.vpath_no = vpath_idx; ++ mac_info.state = VXGE_LL_MAC_ADDR_IN_DA_TABLE; ++ status = vxge_add_mac_addr(vdev, &mac_info); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s:%d Setting individual" ++ "multicast address failed", ++ __func__, __LINE__); ++ goto _set_all_mcast; ++ } ++ } ++ } ++ ++ return; ++_set_all_mcast: ++ mcast_cnt = vdev->vpaths[0].mcast_addr_cnt; ++ /* Delete previous MC's */ ++ for (i = 0; i < mcast_cnt; i++) { ++ ++ list_for_each_safe(entry, next, list_head) { ++ ++ mac_entry = (struct vxge_mac_addrs *) entry; ++ /* Copy the mac address to delete */ ++ mac_address = (u8 *)&mac_entry->macaddr; ++ memcpy(mac_info.macaddr, mac_address, ETH_ALEN); ++ ++ /* Is this a multicast address */ ++ if (0x01 & mac_info.macaddr[0]) ++ break; ++ } ++ ++ for (vpath_idx = 0; vpath_idx < vdev->no_of_vpath; ++ vpath_idx++) { ++ mac_info.vpath_no = vpath_idx; ++ status = vxge_del_mac_addr(vdev, &mac_info); ++ } ++ } ++ ++ /* Enable all multicast */ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ vxge_assert(vdev->vpaths[i].is_open); ++ status = vxge_hw_vpath_mcast_enable( ++ vdev->vpaths[i].handle); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s:%d Enabling all multicasts failed", ++ __func__, __LINE__); ++ } ++ vdev->all_multi_flg = 1; ++ } ++ dev->flags |= IFF_ALLMULTI; ++ } ++ ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s:%d Exiting...", __func__, __LINE__); ++} ++ ++/** ++ * vxge_set_mac_addr ++ * @dev: pointer to the device structure ++ * ++ * Update entry "0" (default MAC addr) ++ */ ++static int vxge_set_mac_addr(struct net_device *dev, void *p) ++{ ++ struct sockaddr *addr = p; ++ struct vxgedev *vdev; ++ struct __vxge_hw_device *hldev; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct macInfo mac_info_new, mac_info_old; ++ int vpath_idx = 0; ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s:%d", __func__, __LINE__); ++ ++ vdev = (struct vxgedev *)netdev_priv(dev); ++ hldev = vdev->devh; ++ ++ if (!is_valid_ether_addr(addr->sa_data)) ++ return -EINVAL; ++ ++ memset(&mac_info_new, 0, sizeof(struct macInfo)); ++ memset(&mac_info_old, 0, sizeof(struct macInfo)); ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s:%d Exiting...", ++ __func__, __LINE__); ++ ++ /* Get the old address */ ++ memcpy(mac_info_old.macaddr, dev->dev_addr, dev->addr_len); ++ ++ /* Copy the new address */ ++ memcpy(mac_info_new.macaddr, addr->sa_data, dev->addr_len); ++ ++ /* First delete the old mac address from all the vpaths ++ as we can't specify the index while adding new mac address */ ++ for (vpath_idx = 0; vpath_idx < vdev->no_of_vpath; vpath_idx++) { ++ struct vxge_vpath *vpath = &vdev->vpaths[vpath_idx]; ++ if (!vpath->is_open) { ++ /* This can happen when this interface is added/removed ++ to the bonding interface. Delete this station address ++ from the linked list */ ++ vxge_mac_list_del(vpath, &mac_info_old); ++ ++ /* Add this new address to the linked list ++ for later restoring */ ++ vxge_mac_list_add(vpath, &mac_info_new); ++ ++ continue; ++ } ++ /* Delete the station address */ ++ mac_info_old.vpath_no = vpath_idx; ++ status = vxge_del_mac_addr(vdev, &mac_info_old); ++ } ++ ++ if (unlikely(!is_vxge_card_up(vdev))) { ++ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); ++ return VXGE_HW_OK; ++ } ++ ++ /* Set this mac address to all the vpaths */ ++ for (vpath_idx = 0; vpath_idx < vdev->no_of_vpath; vpath_idx++) { ++ mac_info_new.vpath_no = vpath_idx; ++ mac_info_new.state = VXGE_LL_MAC_ADDR_IN_DA_TABLE; ++ status = vxge_add_mac_addr(vdev, &mac_info_new); ++ if (status != VXGE_HW_OK) ++ return -EINVAL; ++ } ++ ++ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); ++ ++ return status; ++} ++ ++/* ++ * vxge_vpath_intr_enable ++ * @vdev: pointer to vdev ++ * @vp_id: vpath for which to enable the interrupts ++ * ++ * Enables the interrupts for the vpath ++*/ ++void vxge_vpath_intr_enable(struct vxgedev *vdev, int vp_id) ++{ ++ struct vxge_vpath *vpath = &vdev->vpaths[vp_id]; ++ int msix_id = 0; ++ int tim_msix_id[4] = {0, 1, 0, 0}; ++ ++ vxge_hw_vpath_intr_enable(vpath->handle); ++ ++ ++ ++ if (vdev->config.intr_type == INTA) ++ vxge_hw_vpath_inta_unmask_tx_rx(vpath->handle); ++ else { ++ vxge_hw_vpath_msix_set(vpath->handle, tim_msix_id, ++ VXGE_ALARM_MSIX_ID); ++ ++ msix_id = vpath->device_id * VXGE_HW_VPATH_MSIX_ACTIVE; ++ ++ vxge_hw_vpath_msix_unmask(vpath->handle, msix_id); ++ vxge_hw_vpath_msix_unmask(vpath->handle, msix_id + 1); ++ ++ /* enable the alarm vector */ ++ msix_id = (vpath->handle->vpath->hldev->first_vp_id * ++ VXGE_HW_VPATH_MSIX_ACTIVE) + VXGE_ALARM_MSIX_ID; ++ vxge_hw_vpath_msix_unmask(vpath->handle, msix_id); ++ } ++} ++ ++/* ++ * vxge_vpath_intr_disable ++ * @vdev: pointer to vdev ++ * @vp_id: vpath for which to disable the interrupts ++ * ++ * Disables the interrupts for the vpath ++*/ ++void vxge_vpath_intr_disable(struct vxgedev *vdev, int vp_id) ++{ ++ struct vxge_vpath *vpath = &vdev->vpaths[vp_id]; ++ int msix_id; ++ ++ ++ vxge_hw_vpath_intr_disable(vpath->handle); ++ ++ if (vdev->config.intr_type == INTA) ++ vxge_hw_vpath_inta_mask_tx_rx(vpath->handle); ++ else { ++ msix_id = vpath->device_id * VXGE_HW_VPATH_MSIX_ACTIVE; ++ vxge_hw_vpath_msix_mask(vpath->handle, msix_id); ++ vxge_hw_vpath_msix_mask(vpath->handle, msix_id + 1); ++ ++ /* disable the alarm vector */ ++ msix_id = (vpath->handle->vpath->hldev->first_vp_id * ++ VXGE_HW_VPATH_MSIX_ACTIVE) + VXGE_ALARM_MSIX_ID; ++ vxge_hw_vpath_msix_mask(vpath->handle, msix_id); ++ } ++} ++ ++/* ++ * vxge_reset_vpath ++ * @vdev: pointer to vdev ++ * @vp_id: vpath to reset ++ * ++ * Resets the vpath ++*/ ++static int vxge_reset_vpath(struct vxgedev *vdev, int vp_id) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ int ret = 0; ++ ++ /* check if device is down already */ ++ if (unlikely(!is_vxge_card_up(vdev))) ++ return 0; ++ ++ /* is device reset already scheduled */ ++ if (test_bit(__VXGE_STATE_RESET_CARD, &vdev->state)) ++ return 0; ++ ++ ++ ++ ++ if (vdev->vpaths[vp_id].handle) { ++ if (vxge_hw_vpath_reset(vdev->vpaths[vp_id].handle) ++ == VXGE_HW_OK) { ++ if (is_vxge_card_up(vdev) && ++ vxge_hw_vpath_recover_from_reset( ++ vdev->vpaths[vp_id].handle) ++ != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "vxge_hw_vpath_recover_from_reset" ++ "failed for vpath:%d", vp_id); ++ return status; ++ } ++ } else { ++ vxge_debug_init(VXGE_ERR, ++ "vxge_hw_vpath_reset failed for" ++ "vpath:%d", vp_id); ++ return status; ++ } ++ } else ++ return VXGE_HW_FAIL; ++ ++ vxge_restore_vpath_mac_addr(&vdev->vpaths[vp_id]); ++ vxge_restore_vpath_vid_table(&vdev->vpaths[vp_id]); ++ ++ /* Enable all broadcast */ ++ vxge_hw_vpath_bcast_enable(vdev->vpaths[vp_id].handle); ++ ++ ++ ++ /* Enable the interrupts */ ++ vxge_vpath_intr_enable(vdev, vp_id); ++ ++ smp_wmb(); ++ ++ /* Enable the flow of traffic through the vpath */ ++ vxge_hw_vpath_enable(vdev->vpaths[vp_id].handle); ++ ++ if (vdev->config.doorbell_mode == VXGE_HW_DOORBELL_MODE_ENABLE) { ++ smp_wmb(); ++ vxge_hw_vpath_rx_doorbell_init(vdev->vpaths[vp_id].handle); ++ vdev->vpaths[vp_id].ring.last_status = VXGE_HW_OK; ++ } ++ ++ /* Vpath reset done */ ++ clear_bit(vp_id, &vdev->vp_reset); ++ ++ ++ ++ /* Start the vpath queue */ ++ vxge_wake_tx_queue(&vdev->vpaths[vp_id].fifo, NULL); ++ ++ return ret; ++} ++ ++static int do_vxge_reset(struct vxgedev *vdev, int event) ++{ ++ enum vxge_hw_status status; ++ int ret = 0, vp_id, i; ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s:%d", __func__, __LINE__); ++ ++ if ((event == VXGE_LL_FULL_RESET) || (event == VXGE_LL_START_RESET)) { ++ /* check if device is down already */ ++ if (unlikely(!is_vxge_card_up(vdev))) ++ return 0; ++ ++ /* is reset already scheduled */ ++ if (test_and_set_bit(__VXGE_STATE_RESET_CARD, &vdev->state)) ++ return 0; ++ } ++ ++ if (event == VXGE_LL_FULL_RESET) { ++ /* wait for all the vpath reset to complete */ ++ for (vp_id = 0; vp_id < vdev->no_of_vpath; vp_id++) { ++ while (test_bit(vp_id, &vdev->vp_reset)) ++ msleep(50); ++ } ++ ++ /* if execution mode is set to debug, don't reset the adapter */ ++ if (unlikely(vdev->exec_mode)) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: execution mode is debug, returning..", ++ vdev->ndev->name); ++ clear_bit(__VXGE_STATE_CARD_UP, &vdev->state); ++ vxge_stop_all_tx_queue(vdev); ++ return 0; ++ } ++ } ++ ++ if (event == VXGE_LL_FULL_RESET) { ++ vxge_hw_device_intr_disable(vdev->devh); ++ ++ switch (vdev->cric_err_event) { ++ case VXGE_HW_EVENT_UNKNOWN: ++ vxge_stop_all_tx_queue(vdev); ++ vxge_debug_init(VXGE_ERR, ++ "fatal: %s: Disabling device due to" ++ "unknown error", ++ vdev->ndev->name); ++ ret = -EPERM; ++ goto out; ++ case VXGE_HW_EVENT_RESET_START: ++ break; ++ case VXGE_HW_EVENT_RESET_COMPLETE: ++ case VXGE_HW_EVENT_LINK_DOWN: ++ case VXGE_HW_EVENT_LINK_UP: ++ case VXGE_HW_EVENT_ALARM_CLEARED: ++ case VXGE_HW_EVENT_ECCERR: ++ case VXGE_HW_EVENT_MRPCIM_ECCERR: ++ ret = -EPERM; ++ goto out; ++ case VXGE_HW_EVENT_FIFO_ERR: ++ case VXGE_HW_EVENT_VPATH_ERR: ++ break; ++ case VXGE_HW_EVENT_CRITICAL_ERR: ++ vxge_stop_all_tx_queue(vdev); ++ vxge_debug_init(VXGE_ERR, ++ "fatal: %s: Disabling device due to" ++ "serious error", ++ vdev->ndev->name); ++ /* SOP or device reset required */ ++ /* This event is not currently used */ ++ ret = -EPERM; ++ goto out; ++ case VXGE_HW_EVENT_SERR: ++ vxge_stop_all_tx_queue(vdev); ++ vxge_debug_init(VXGE_ERR, ++ "fatal: %s: Disabling device due to" ++ "serious error", ++ vdev->ndev->name); ++ ret = -EPERM; ++ goto out; ++ case VXGE_HW_EVENT_SRPCIM_SERR: ++ case VXGE_HW_EVENT_MRPCIM_SERR: ++ ret = -EPERM; ++ goto out; ++ case VXGE_HW_EVENT_SLOT_FREEZE: ++ vxge_stop_all_tx_queue(vdev); ++ vxge_debug_init(VXGE_ERR, ++ "fatal: %s: Disabling device due to" ++ "slot freeze", ++ vdev->ndev->name); ++ ret = -EPERM; ++ goto out; ++ default: ++ break; ++ ++ } ++ } ++ ++ if ((event == VXGE_LL_FULL_RESET) || (event == VXGE_LL_START_RESET)) ++ vxge_stop_all_tx_queue(vdev); ++ ++ if (event == VXGE_LL_FULL_RESET) { ++ status = vxge_reset_all_vpaths(vdev); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "fatal: %s: can not reset vpaths", ++ vdev->ndev->name); ++ ret = -EPERM; ++ goto out; ++ } ++ } ++ ++ if (event == VXGE_LL_COMPL_RESET) { ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ if (vdev->vpaths[i].handle) { ++ if (vxge_hw_vpath_recover_from_reset( ++ vdev->vpaths[i].handle) ++ != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "vxge_hw_vpath_recover_" ++ "from_reset failed for vpath: " ++ "%d", i); ++ ret = -EPERM; ++ goto out; ++ } ++ } else { ++ vxge_debug_init(VXGE_ERR, ++ "vxge_hw_vpath_reset failed for " ++ "vpath:%d", i); ++ ret = -EPERM; ++ goto out; ++ } ++ } ++ ++ if ((event == VXGE_LL_FULL_RESET) || (event == VXGE_LL_COMPL_RESET)) { ++ /* Reprogram the DA table with populated mac addresses */ ++ for (vp_id = 0; vp_id < vdev->no_of_vpath; vp_id++) { ++ vxge_restore_vpath_mac_addr(&vdev->vpaths[vp_id]); ++ vxge_restore_vpath_vid_table(&vdev->vpaths[vp_id]); ++ } ++ ++ /* enable vpath interrupts */ ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ vxge_vpath_intr_enable(vdev, i); ++ ++ vxge_hw_device_intr_enable(vdev->devh); ++ ++ smp_wmb(); ++ ++ /* Indicate card up */ ++ set_bit(__VXGE_STATE_CARD_UP, &vdev->state); ++ ++ /* Get the traffic to flow through the vpaths */ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ vxge_hw_vpath_enable(vdev->vpaths[i].handle); ++ if (vdev->config.doorbell_mode == VXGE_HW_DOORBELL_MODE_ENABLE) { ++ smp_wmb(); ++ vxge_hw_vpath_rx_doorbell_init( ++ vdev->vpaths[i].handle); ++ } ++ } ++ ++ ++ ++ vxge_wake_all_tx_queue(vdev); ++ } ++ ++out: ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s:%d Exiting...", __func__, __LINE__); ++ ++ /* Indicate reset done */ ++ if ((event == VXGE_LL_FULL_RESET) || (event == VXGE_LL_COMPL_RESET)) ++ clear_bit(__VXGE_STATE_RESET_CARD, &vdev->state); ++ return ret; ++} ++ ++/* ++ * vxge_reset ++ * @vdev: pointer to ll device ++ * ++ * driver may reset the chip on events of serr, eccerr, etc ++ */ ++int vxge_reset(struct vxgedev *vdev) ++{ ++ do_vxge_reset(vdev, VXGE_LL_FULL_RESET); ++ return 0; ++} ++ ++/** ++ * vxge_poll - Receive handler when Receive Polling is used. ++ * @dev: pointer to the device structure. ++ * @budget: Number of packets budgeted to be processed in this iteration. ++ * ++ * This function comes into picture only if Receive side is being handled ++ * through polling (called NAPI in linux). It mostly does what the normal ++ * Rx interrupt handler does in terms of descriptor and packet processing ++ * but not in an interrupt context. Also it will process a specified number ++ * of packets at most in one iteration. This value is passed down by the ++ * kernel as the function argument 'budget'. ++ */ ++#if defined(HAVE_NETDEV_POLL) ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) ++static int vxge_poll_msix(struct net_device *dev, int *budget) ++{ ++ int i; ++ struct __vxge_hw_device *hldev; ++ struct vxgedev *vdev; ++ struct vxge_ring *ring; ++ int org_pkts_to_process, pkt_cnt = 0; ++ vdev = (struct vxgedev *)netdev_priv(dev); ++ hldev = (struct __vxge_hw_device *)pci_get_drvdata(vdev->pdev); ++ ++ vxge_debug_entryexit(VXGE_TRACE, NULL, ++ "%s:%d\n", __func__, __LINE__); ++ ++ org_pkts_to_process = *budget; ++ if (org_pkts_to_process > dev->quota) ++ org_pkts_to_process = dev->quota; ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ ring = &vdev->vpaths[i].ring; ++ ring->pkts_to_process = org_pkts_to_process - pkt_cnt; ++ vxge_hw_vpath_poll_rx(ring->handle); ++ pkt_cnt = org_pkts_to_process - ring->pkts_to_process; ++ if (!ring->pkts_to_process) { ++ /* Quota for the current iteration has been met */ ++ goto no_rx; ++ } ++ } ++ ++ if (!pkt_cnt) ++ pkt_cnt = 1; ++ ++ dev->quota -= pkt_cnt; ++ *budget -= pkt_cnt; ++ ++ vxge_netif_do_rx_complete(dev, NULL); ++ ++ vxge_debug_entryexit(VXGE_TRACE, NULL, ++ "%s:%d Exiting...\n", __func__, __LINE__); ++ ++ /* Re enable the Rx interrupts */ ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ if ((i == 0) || (vdev->config.rx_steering_type)) ++ vxge_hw_vpath_msix_unmask(vdev->vpaths[i].handle, ++ vdev->vpaths[i].ring.rx_vector_no); ++ return 0; ++ ++no_rx: ++ dev->quota -= pkt_cnt; ++ *budget -= pkt_cnt; ++ ++ vxge_debug_entryexit(VXGE_TRACE, NULL, ++ "%s:%d Exiting...\n", __func__, __LINE__); ++ ++ return 1; ++} ++ ++static int vxge_poll_inta(struct net_device *dev, int *budget) ++{ ++ int i; ++ struct __vxge_hw_device *hldev; ++ struct vxgedev *vdev; ++ struct vxge_ring *ring; ++ int org_pkts_to_process, pkt_cnt = 0; ++ vdev = (struct vxgedev *)netdev_priv(dev); ++ hldev = (struct __vxge_hw_device *)pci_get_drvdata(vdev->pdev); ++ ++ vxge_debug_entryexit(VXGE_TRACE, NULL, ++ "%s:%d\n", __func__, __LINE__); ++ ++ org_pkts_to_process = *budget; ++ if (org_pkts_to_process > dev->quota) ++ org_pkts_to_process = dev->quota; ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ ring = &vdev->vpaths[i].ring; ++ ring->pkts_to_process = org_pkts_to_process - pkt_cnt; ++ vxge_hw_vpath_poll_rx(ring->handle); ++ pkt_cnt = org_pkts_to_process - ring->pkts_to_process; ++ if (!ring->pkts_to_process) { ++ /* Quota for the current iteration has been met */ ++ goto no_rx; ++ } ++ } ++ ++ if (!pkt_cnt) ++ pkt_cnt = 1; ++ ++ dev->quota -= pkt_cnt; ++ *budget -= pkt_cnt; ++ ++ vxge_netif_do_rx_complete(dev, NULL); ++ ++ VXGE_COMPLETE_ALL_TX(vdev); ++ ++ vxge_debug_entryexit(VXGE_TRACE, NULL, ++ "%s:%d Exiting...\n", __func__, __LINE__); ++ ++ ++ vxge_hw_device_unmask_all(hldev); ++ ++ ++ return 0; ++no_rx: ++ VXGE_COMPLETE_ALL_TX(vdev); ++ ++ dev->quota -= pkt_cnt; ++ *budget -= pkt_cnt; ++ ++ vxge_debug_entryexit(VXGE_TRACE, NULL, ++ "%s:%d Exiting...\n", __func__, __LINE__); ++ return 1; ++} ++ ++#else ++/** ++ * vxge_poll - Receive handler when Receive Polling is used. ++ * @dev: pointer to the device structure. ++ * @budget: Number of packets budgeted to be processed in this iteration. ++ * ++ * This function comes into picture only if Receive side is being handled ++ * through polling (called NAPI in linux). It mostly does what the normal ++ * Rx interrupt handler does in terms of descriptor and packet processing ++ * but not in an interrupt context. Also it will process a specified number ++ * of packets at most in one iteration. This value is passed down by the ++ * kernel as the function argument 'budget'. ++ */ ++static int vxge_poll_msix(struct napi_struct *napi, int budget) ++{ ++ struct vxge_ring *ring = ++ container_of(napi, struct vxge_ring, napi); ++ int budget_org = budget; ++ ring->budget = budget; ++ ++ vxge_hw_vpath_poll_rx(ring->handle); ++ ++ if (ring->pkts_processed < budget_org) { ++ napi_complete(napi); ++ /* Re enable the Rx interrupts for the vpath */ ++ vxge_hw_channel_msix_unmask( ++ (struct __vxge_hw_channel *)ring->handle, ++ ring->rx_vector_no); ++ } ++ ++ return ring->pkts_processed; ++} ++ ++static int vxge_poll_inta(struct napi_struct *napi, int budget) ++{ ++ struct vxgedev *vdev = container_of(napi, struct vxgedev, napi); ++ int pkts_processed = 0; ++ int i; ++ int budget_org = budget; ++ struct vxge_ring *ring; ++ ++ struct __vxge_hw_device *hldev = (struct __vxge_hw_device *) ++ pci_get_drvdata(vdev->pdev); ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ ring = &vdev->vpaths[i].ring; ++ ring->budget = budget; ++ vxge_hw_vpath_poll_rx(ring->handle); ++ pkts_processed += ring->pkts_processed; ++ budget -= ring->pkts_processed; ++ if (budget <= 0) ++ break; ++ } ++ ++ VXGE_COMPLETE_ALL_TX(vdev); ++ ++ if (pkts_processed < budget_org) { ++ vxge_netif_do_rx_complete(vdev->ndev, napi); ++ /* Re enable the Rx interrupts for the ring */ ++ ++ ++ vxge_hw_device_unmask_all(hldev); ++ ++ } ++ ++ return pkts_processed; ++} ++#endif ++#endif ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++/** ++ * vxge_netpoll - netpoll event handler entry point ++ * @dev : pointer to the device structure. ++ * Description: ++ * This function will be called by upper layer to check for events on the ++ * interface in situations where interrupts are disabled. It is used for ++ * specific in-kernel networking tasks, such as remote consoles and kernel ++ * debugging over the network (example netdump in RedHat). ++ */ ++static void vxge_netpoll(struct net_device *dev) ++{ ++ struct __vxge_hw_device *hldev; ++ struct vxgedev *vdev; ++ ++ vdev = (struct vxgedev *)netdev_priv(dev); ++ hldev = (struct __vxge_hw_device *)pci_get_drvdata(vdev->pdev); ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s:%d", __func__, __LINE__); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) ++ if (pci_channel_offline(vdev->pdev)) ++ return; ++#endif ++ disable_irq(dev->irq); ++ vxge_hw_device_clear_tx_rx(hldev); ++ ++ VXGE_COMPLETE_ALL_RX(vdev); ++ VXGE_COMPLETE_ALL_TX(vdev); ++ ++ enable_irq(dev->irq); ++ ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s:%d Exiting...", __func__, __LINE__); ++ return; ++} ++#endif ++ ++/* RTH configuration */ ++static enum vxge_hw_status vxge_rth_configure(struct vxgedev *vdev) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct vxge_hw_rth_hash_types hash_types; ++ u8 itable[256] = {0}; /* indirection table */ ++ u8 mtable[256] = {0}; /* CPU to vpath mapping */ ++ int index; ++ ++ /* ++ * Filling ++ * - itable with bucket numbers ++ * - mtable with bucket-to-vpath mapping ++ */ ++ for (index = 0; index < (1 << vdev->config.rth_bkt_sz); index++) { ++ itable[index] = index; ++ mtable[index] = index % vdev->no_of_vpath; ++ } ++ ++ /* Fill RTH hash types */ ++ hash_types.hash_type_tcpipv4_en = vdev->config.rth_hash_type_tcpipv4; ++ hash_types.hash_type_ipv4_en = vdev->config.rth_hash_type_ipv4; ++ hash_types.hash_type_tcpipv6_en = vdev->config.rth_hash_type_tcpipv6; ++ hash_types.hash_type_ipv6_en = vdev->config.rth_hash_type_ipv6; ++ hash_types.hash_type_tcpipv6ex_en = ++ vdev->config.rth_hash_type_tcpipv6ex; ++ hash_types.hash_type_ipv6ex_en = vdev->config.rth_hash_type_ipv6ex; ++ ++ /* set indirection table, bucket-to-vpath mapping */ ++ status = vxge_hw_vpath_rts_rth_itable_set(vdev->vp_handles, ++ vdev->no_of_vpath, ++ mtable, itable, ++ vdev->config.rth_bkt_sz); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "RTH indirection table configuration failed " ++ "for vpath:%d", vdev->vpaths[0].device_id); ++ return status; ++ } ++ ++ /* ++ * Because the itable_set() method uses the active_table field ++ * for the target virtual path the RTH config should be updated ++ * for all VPATHs. The h/w only uses the lowest numbered VPATH ++ * when steering frames. ++ */ ++ for (index = 0; index < vdev->no_of_vpath; index++) { ++ status = vxge_hw_vpath_rts_rth_set( ++ vdev->vpaths[index].handle, ++ vdev->config.rth_algorithm, ++ &hash_types, ++ vdev->config.rth_bkt_sz); ++ ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "RTH configuration failed for vpath:%d", ++ vdev->vpaths[index].device_id); ++ return status; ++ } ++ } ++ ++ return status; ++} ++ ++int vxge_mac_list_add(struct vxge_vpath *vpath, struct macInfo *mac) ++{ ++ struct vxge_mac_addrs *new_mac_entry; ++ u8 *mac_address = NULL; ++ ++ if (vpath->mac_addr_cnt >= VXGE_MAX_LEARN_MAC_ADDR_CNT) ++ return TRUE; ++ ++ new_mac_entry = kzalloc(sizeof(struct vxge_mac_addrs), GFP_ATOMIC); ++ if (!new_mac_entry) { ++ vxge_debug_mem(VXGE_ERR, ++ "%s: memory allocation failed", ++ VXGE_DRIVER_NAME); ++ return FALSE; ++ } ++ ++ list_add(&new_mac_entry->item, &vpath->mac_addr_list); ++ ++ /* Copy the new mac address to the list */ ++ mac_address = (u8 *)&new_mac_entry->macaddr; ++ memcpy(mac_address, mac->macaddr, ETH_ALEN); ++ ++ new_mac_entry->state = mac->state; ++ vpath->mac_addr_cnt++; ++ ++ /* Is this a multicast address */ ++ if (0x01 & mac->macaddr[0]) ++ vpath->mcast_addr_cnt++; ++ ++ return TRUE; ++} ++ ++/* Add a mac address to DA table */ ++enum vxge_hw_status vxge_add_mac_addr(struct vxgedev *vdev, struct macInfo *mac) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct vxge_vpath *vpath; ++ enum vxge_hw_vpath_mac_addr_add_mode duplicate_mode; ++ ++ if (0x01 & mac->macaddr[0]) /* multicast address */ ++ duplicate_mode = VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE; ++ else ++ duplicate_mode = VXGE_HW_VPATH_MAC_ADDR_REPLACE_DUPLICATE; ++ ++ vpath = &vdev->vpaths[mac->vpath_no]; ++ status = vxge_hw_vpath_mac_addr_add_vpn(vpath->handle, mac->macaddr, ++ mac->macmask, duplicate_mode, ++ vpath->handle->vpath->vp_id); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "DA config add entry failed for vpath:%d", ++ vpath->device_id); ++ } else ++ if (FALSE == vxge_mac_list_add(vpath, mac)) ++ status = -EPERM; ++ ++ return status; ++} ++ ++int vxge_mac_list_del(struct vxge_vpath *vpath, struct macInfo *mac) ++{ ++ struct list_head *entry, *next; ++ u64 del_mac = 0; ++ u8 *mac_address = (u8 *) (&del_mac); ++ ++ /* Copy the mac address to delete from the list */ ++ memcpy(mac_address, mac->macaddr, ETH_ALEN); ++ ++ list_for_each_safe(entry, next, &vpath->mac_addr_list) { ++ if (((struct vxge_mac_addrs *)entry)->macaddr == del_mac) { ++ list_del(entry); ++ kfree((struct vxge_mac_addrs *)entry); ++ vpath->mac_addr_cnt--; ++ ++ /* Is this a multicast address */ ++ if (0x01 & mac->macaddr[0]) ++ vpath->mcast_addr_cnt--; ++ return TRUE; ++ } ++ } ++ ++ return FALSE; ++} ++/* delete a mac address from DA table */ ++enum vxge_hw_status vxge_del_mac_addr(struct vxgedev *vdev, struct macInfo *mac) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct vxge_vpath *vpath; ++ ++ vpath = &vdev->vpaths[mac->vpath_no]; ++ status = vxge_hw_vpath_mac_addr_del_vpn(vpath->handle, mac->macaddr, ++ mac->macmask, ++ vpath->handle->vpath->vp_id); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "DA config delete entry failed for vpath:%d", ++ vpath->device_id); ++ } else ++ vxge_mac_list_del(vpath, mac); ++ return status; ++} ++ ++/* list all mac addresses from DA table */ ++enum vxge_hw_status ++static vxge_search_mac_addr_in_da_table(struct vxge_vpath *vpath, ++ struct macInfo *mac) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ unsigned char macmask[ETH_ALEN]; ++ unsigned char macaddr[ETH_ALEN]; ++ ++ status = vxge_hw_vpath_mac_addr_get_vpn(vpath->handle, ++ macaddr, macmask, ++ vpath->handle->vpath->vp_id); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "DA config list entry failed for vpath:%d", ++ vpath->device_id); ++ return status; ++ } ++ ++ while (memcmp(mac->macaddr, macaddr, ETH_ALEN)) { ++ ++ status = vxge_hw_vpath_mac_addr_get_next_vpn(vpath->handle, ++ macaddr, macmask, ++ vpath->handle->vpath->vp_id); ++ if (status != VXGE_HW_OK) ++ break; ++ } ++ ++ return status; ++} ++ ++/* Store all vlan ids from the list to the vid table */ ++enum vxge_hw_status vxge_restore_vpath_vid_table(struct vxge_vpath *vpath) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct vxgedev *vdev = vpath->vdev; ++ u16 vid; ++ ++ if (vdev->vlgrp && vpath->is_open) { ++ ++ for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { ++ if (!vlan_group_get_device(vdev->vlgrp, vid)) ++ continue; ++ /* Add these vlan to the vid table */ ++ status = vxge_hw_vpath_vid_add_vpn(vpath->handle, vid, ++ vpath->handle->vpath->vp_id); ++ } ++ } ++ ++ return status; ++} ++ ++/* Store all mac addresses from the list to the DA table */ ++enum vxge_hw_status vxge_restore_vpath_mac_addr(struct vxge_vpath *vpath) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct macInfo mac_info; ++ u8 *mac_address = NULL; ++ struct list_head *entry, *next; ++ ++ memset(&mac_info, 0, sizeof(struct macInfo)); ++ ++ if (vpath->is_open) { ++ ++ list_for_each_safe(entry, next, &vpath->mac_addr_list) { ++ mac_address = ++ (u8 *)& ++ ((struct vxge_mac_addrs *)entry)->macaddr; ++ memcpy(mac_info.macaddr, mac_address, ETH_ALEN); ++ ((struct vxge_mac_addrs *)entry)->state = ++ VXGE_LL_MAC_ADDR_IN_DA_TABLE; ++ /* does this mac address already exist in da table? */ ++ status = vxge_search_mac_addr_in_da_table(vpath, ++ &mac_info); ++ if (status != VXGE_HW_OK) { ++ /* Add this mac address to the DA table */ ++ status = vxge_hw_vpath_mac_addr_add_vpn( ++ vpath->handle, mac_info.macaddr, ++ mac_info.macmask, ++ VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE, ++ vpath->handle->vpath->vp_id); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "DA add entry failed for vpath:%d", ++ vpath->device_id); ++ ((struct vxge_mac_addrs *)entry)->state ++ = VXGE_LL_MAC_ADDR_IN_LIST; ++ } ++ } ++ } ++ } ++ ++ return status; ++} ++ ++/* reset vpaths */ ++enum vxge_hw_status vxge_reset_all_vpaths(struct vxgedev *vdev) ++{ ++ int i; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ if (vdev->vpaths[i].handle) { ++ if (vxge_hw_vpath_reset(vdev->vpaths[i].handle) ++ == VXGE_HW_OK) { ++ if (is_vxge_card_up(vdev) && ++ vxge_hw_vpath_recover_from_reset( ++ vdev->vpaths[i].handle) ++ != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "vxge_hw_vpath_recover_" ++ "from_reset failed for vpath: " ++ "%d", i); ++ return status; ++ } ++ } else { ++ vxge_debug_init(VXGE_ERR, ++ "vxge_hw_vpath_reset failed for " ++ "vpath:%d", i); ++ return status; ++ } ++ } ++ return status; ++} ++ ++/* close vpaths */ ++void vxge_close_vpaths(struct vxgedev *vdev, int index) ++{ ++ int i; ++ for (i = index; i < vdev->no_of_vpath; i++) { ++ if (vdev->vpaths[i].handle && vdev->vpaths[i].is_open) { ++ vxge_hw_vpath_close(vdev->vpaths[i].handle); ++ vdev->stats.vpaths_open--; ++ } ++ vdev->vpaths[i].is_open = 0; ++ vdev->vpaths[i].handle = NULL; ++ } ++} ++ ++/* open vpaths */ ++int vxge_open_vpaths(struct vxgedev *vdev) ++{ ++ enum vxge_hw_status status; ++ int i; ++ u32 vp_id = 0; ++ struct vxge_hw_vpath_attr attr; ++ struct vxge_hw_vp_config *vcfg; ++ struct __vxge_hw_device *hldev; ++ ++ hldev = (struct __vxge_hw_device *)pci_get_drvdata(vdev->pdev); ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ vcfg = &hldev->config.vp_config[vdev->vpaths[i].device_id]; ++ if (!vdev->titan1 || ++ (vdev->config.doorbell_mode == ++ VXGE_HW_DOORBELL_MODE_DISABLE)) { ++ vcfg->tti.uec_a = TTI_T1A_TX_UFC_A; ++ vcfg->tti.uec_b = TTI_T1A_TX_UFC_B; ++ vcfg->tti.uec_c = TTI_T1A_TX_UFC_C(vdev->mtu); ++ vcfg->tti.uec_d = TTI_T1A_TX_UFC_D(vdev->mtu); ++ vcfg->tti.ltimer_val = VXGE_T1A_TTI_LTIMER_VAL; ++ vcfg->tti.rtimer_val = VXGE_T1A_TTI_RTIMER_VAL; ++ vcfg->rti.urange_a = RTI_T1A_RX_URANGE_A; ++ vcfg->rti.urange_b = RTI_T1A_RX_URANGE_B; ++ vcfg->rti.urange_c = RTI_T1A_RX_URANGE_C; ++ vcfg->rti.uec_b = RTI_T1A_RX_UFC_B; ++ vcfg->rti.uec_c = RTI_T1A_RX_UFC_C; ++ vcfg->rti.uec_d = RTI_T1A_RX_UFC_D; ++ } ++ } ++ ++ if ((vdev->config.lro_enable) && ++ (vdev->config.lro_enable != VXGE_HW_GRO_ENABLE)) { ++ int size; ++ ++ if (vdev->titan1) ++ size = MAX_LRO_PACKETS; ++ else ++ size = MAX_T1A_LRO_PACKETS; ++ ++ /* Initialize max aggregatable pkts per session based on MTU */ ++ vdev->config.lro_max_aggr_per_sess = ++ (vdev->config.lro_max_bytes - 1) / vdev->mtu; ++ ++ if (vdev->config.lro_max_aggr_per_sess < MIN_LRO_PACKETS) ++ vdev->config.lro_max_aggr_per_sess = MIN_LRO_PACKETS; ++ ++ if (vdev->config.lro_max_aggr_per_sess > size) ++ vdev->config.lro_max_aggr_per_sess = size; ++ } ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ vcfg = &hldev->config.vp_config[vdev->vpaths[i].device_id]; ++ vxge_assert(vdev->vpaths[i].is_configured); ++ attr.vp_id = vdev->vpaths[i].device_id; ++ attr.fifo_attr.callback = vxge_xmit_compl; ++ attr.fifo_attr.txdl_term = vxge_tx_term; ++ attr.fifo_attr.per_txdl_space = sizeof(struct vxge_tx_priv); ++ attr.fifo_attr.userdata = (void *)&vdev->vpaths[i].fifo; ++ ++ attr.ring_attr.callback = vxge_rx_1b_compl; ++ attr.ring_attr.rxd_init = vxge_rx_initial_replenish; ++ attr.ring_attr.rxd_term = vxge_rx_term; ++ attr.ring_attr.per_rxd_space = sizeof(struct vxge_rx_priv); ++ attr.ring_attr.userdata = (void *)&vdev->vpaths[i].ring; ++ ++ vdev->vpaths[i].ring.ndev = vdev->ndev; ++ vdev->vpaths[i].ring.pdev = vdev->pdev; ++ status = vxge_hw_vpath_open(vdev->devh, &attr, ++ &(vdev->vpaths[i].handle)); ++ if (status == VXGE_HW_OK) { ++ vdev->vpaths[i].fifo.handle = ++ (struct __vxge_hw_fifo *)attr.fifo_attr.userdata; ++ vdev->vpaths[i].ring.handle = ++ (struct __vxge_hw_ring *)attr.ring_attr.userdata; ++ ++ vdev->vpaths[i].fifo.tx_steering_type = ++ vdev->config.tx_steering_type; ++ vdev->vpaths[i].fifo.ndev = vdev->ndev; ++ vdev->vpaths[i].fifo.pdev = vdev->pdev; ++ vdev->vpaths[i].fifo.indicate_max_pkts = ++ vdev->config.fifo_indicate_max_pkts; ++ vdev->vpaths[i].fifo.addr_learn_en = 0; ++ ++ vdev->vpaths[i].ring.aggr_ack = ++ vdev->config.aggr_ack; ++ vdev->vpaths[i].ring.rx_vector_no = 0; ++ vdev->vpaths[i].ring.rx_csum = vdev->rx_csum; ++ vdev->vpaths[i].ring.napi_enable = ++ vdev->config.napi_enable; ++ vdev->vpaths[i].is_open = 1; ++ vdev->vp_handles[i] = vdev->vpaths[i].handle; ++ vdev->vpaths[i].ring.lro_enable = ++ vdev->config.lro_enable; ++ vdev->vpaths[i].ring.doorbell_mode = ++ vdev->config.doorbell_mode; ++ vdev->vpaths[i].ring.rx_vlan_stripped = FALSE; ++ vdev->vpaths[i].ring.handle->btimer = ++ (vcfg->rti.btimer_val * 272)/1000; ++ vdev->vpaths[i].ring.interrupt_count = 0; ++ vdev->vpaths[i].ring.jiffies = jiffies; ++ vdev->vpaths[i].ring.rti_ci = 0; ++ if (!vdev->titan1 || ++ (vdev->config.doorbell_mode == ++ VXGE_HW_DOORBELL_MODE_DISABLE)) ++ vdev->vpaths[i].ring.adaptive_intr_coalescing = ++ intr_adapt; ++ vdev->vpaths[i].ring.handle->rxd_qword_limit = ++ (vdev->mtu > 8000) ? 4: ++ ((vdev->mtu > 4000) ? 8: 16); ++ vdev->stats.vpaths_open++; ++ } else { ++ vdev->stats.vpath_open_fail++; ++ vxge_debug_init(VXGE_ERR, ++ "%s: vpath: %d failed to open " ++ "with status: %d", ++ vdev->ndev->name, vdev->vpaths[i].device_id, ++ status); ++ vxge_close_vpaths(vdev, 0); ++ return -EPERM; ++ } ++ ++ if ((vdev->config.lro_enable) && (vdev->config.lro_enable != ++ VXGE_HW_GRO_ENABLE)) ++ vxge_hw_vpath_set_lro_sg_size(vdev->vpaths[i].handle, ++ vdev->config.lro_max_aggr_per_sess); ++ vp_id = ++ ((struct __vxge_hw_vpath_handle *)vdev->vpaths[i].handle)-> ++ vpath->vp_id; ++ vdev->vpaths_deployed |= vxge_mBIT(vp_id); ++ } ++ return VXGE_HW_OK; ++} ++ ++/** ++ * adaptive_coalesce_rx_interrupts - Changes the interrupt coalescing ++ * if the interrupts are not within a range ++ * @ring: pointer to receive ring structure ++ * Description: The function increases of decreases the packet counts within ++ * the ranges of traffic utilization, if the interrupts due to this ring are ++ * not within a fixed range. ++ * Return Value: Nothing ++ */ ++static void adaptive_coalesce_rx_interrupts(struct vxge_ring *ring) ++{ ++ if (!ring->adaptive_intr_coalescing) ++ return; ++ ++ ring->interrupt_count++; ++ if (jiffies > ring->jiffies + HZ/100) { ++ struct __vxge_hw_ring *hw_ring = ring->handle; ++ u32 timer = hw_ring->rtimer; ++ ++ ring->jiffies = jiffies; ++ if (ring->interrupt_count > VXGE_T1A_MAX_INTERRUPT_COUNT){ ++ if (timer != 40){ ++ hw_ring->rtimer = 40; ++ vxge_hw_vpath_dynamic_rti_rtimer_set(hw_ring); ++ if (!ring->rti_ci) { ++ vxge_hw_vpath_dynamic_rti_ci_set(hw_ring); ++ ring->rti_ci = 1; ++ hw_ring->btimer = (VXGE_RTI_BTIMER_VAL << 4); ++ vxge_hw_vpath_dynamic_rti_btimer_set(hw_ring); ++ } ++ } ++ } else { ++ if (timer != 0){ ++ hw_ring->rtimer = 0; ++ vxge_hw_vpath_dynamic_rti_rtimer_set(hw_ring); ++ vxge_hw_vpath_dynamic_rti_ci_reset( ++ hw_ring); ++ ring->rti_ci = 0; ++ hw_ring->btimer = VXGE_RTI_BTIMER_VAL; ++ vxge_hw_vpath_dynamic_rti_btimer_set(hw_ring); ++ } ++ } ++ ring->interrupt_count = 0; ++ } ++} ++ ++/* ++ * vxge_do_isr_napi ++ * @irq: the irq of the device. ++ * @dev_id: a void pointer to the hldev structure of the Titan device ++ * @ptregs: pointer to the registers pushed on the stack. ++ * ++ * This function is the ISR handler of the device when napi is enabled. It ++ * identifies the reason for the interrupt and calls the relevant service ++ * routines. ++ */ ++irqreturn_t vxge_do_isr_napi(int irq, void *dev_id) ++{ ++ struct vxgedev *vdev = (struct vxgedev *) dev_id; ++ struct net_device *dev; ++ struct __vxge_hw_device *hldev; ++ u64 reason; ++ enum vxge_hw_status status; ++ ++ vxge_debug_intr(VXGE_TRACE, "%s:%d", __func__, __LINE__); ++ ++ dev = vdev->ndev; ++ hldev = (struct __vxge_hw_device *) pci_get_drvdata(vdev->pdev); ++ ++ VXGE_CHECK_PCI_CHANNEL_OFFLINE(vdev->pdev); ++ ++ if (unlikely(!is_vxge_card_up(vdev))) ++ return IRQ_NONE; ++ ++ status = vxge_hw_device_begin_irq(hldev, vdev->exec_mode, ++ &reason); ++ if (status == VXGE_HW_OK) { ++ int i; ++ ++ vxge_hw_device_mask_all(hldev); ++ ++ if (reason & ++ VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT( ++ vdev->vpaths_deployed >> ++ (64 - VXGE_HW_MAX_VIRTUAL_PATHS))) { ++ ++ vxge_hw_device_clear_tx_rx(hldev); ++ vxge_netif_do_rx_schedule(dev, &vdev->napi); ++ for (i=0; i < vdev->no_of_vpath; i++) ++ adaptive_coalesce_rx_interrupts( ++ &vdev->vpaths[i].ring); ++ vxge_debug_intr(VXGE_TRACE, ++ "%s:%d Exiting...", __func__, __LINE__); ++ return IRQ_HANDLED; ++ } else ++ vxge_hw_device_unmask_all(hldev); ++ } else if (unlikely((status == VXGE_HW_ERR_VPATH) || ++ (status == VXGE_HW_ERR_CRITICAL) || ++ (status == VXGE_HW_ERR_FIFO))) { ++ vxge_hw_device_mask_all(hldev); ++ vxge_hw_device_flush_io(hldev); ++ return IRQ_HANDLED; ++ } else if (unlikely(status == VXGE_HW_ERR_SLOT_FREEZE)) ++ return IRQ_HANDLED; ++ ++ vxge_debug_intr(VXGE_TRACE, "%s:%d Exiting...", __func__, __LINE__); ++ return IRQ_NONE; ++} ++/* ++ * vxge_do_isr ++ * @irq: the irq of the device. ++ * @dev_id: a void pointer to the hldev structure of the Titan device ++ * @ptregs: pointer to the registers pushed on the stack. ++ * ++ * This function is the ISR handler of the device. It identifies the reason ++ * for the interrupt and calls the relevant service routines. ++ */ ++irqreturn_t vxge_do_isr(int irq, void *dev_id) ++{ ++ struct __vxge_hw_device *hldev; ++ struct vxgedev *vdev = (struct vxgedev *) dev_id; ++ struct net_device *dev; ++ enum vxge_hw_status status; ++ u64 reason; ++ ++ vxge_debug_intr(VXGE_TRACE, ++ "%s:%d\n", __func__, __LINE__); ++ dev = vdev->ndev; ++ hldev = (struct __vxge_hw_device *) pci_get_drvdata(vdev->pdev); ++ ++ VXGE_CHECK_PCI_CHANNEL_OFFLINE(vdev->pdev); ++ ++ if (unlikely(!is_vxge_card_up(vdev))) ++ return IRQ_NONE; ++ ++ status = vxge_hw_device_begin_irq(hldev, vdev->exec_mode, ++ &reason); ++ if (status == VXGE_HW_OK) { ++ int i; ++ ++ vxge_hw_device_mask_all(hldev); ++ ++ if (reason & ++ VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT( ++ vdev->vpaths_deployed >> ++ (64 - VXGE_HW_MAX_VIRTUAL_PATHS))) { ++ ++ vxge_hw_device_clear_tx_rx(hldev); ++ VXGE_COMPLETE_ALL_RX(vdev); ++ VXGE_COMPLETE_ALL_TX(vdev); ++ for (i=0; i < vdev->no_of_vpath; i++) ++ adaptive_coalesce_rx_interrupts( ++ &vdev->vpaths[i].ring); ++ vxge_hw_device_unmask_all(hldev); ++ vxge_debug_intr(VXGE_TRACE, ++ "%s:%d Exiting...\n", __func__, __LINE__); ++ return IRQ_HANDLED; ++ } else ++ vxge_hw_device_unmask_all(hldev); ++ } else if (unlikely((status == VXGE_HW_ERR_VPATH) || ++ (status == VXGE_HW_ERR_CRITICAL) || ++ (status == VXGE_HW_ERR_FIFO))) { ++ vxge_hw_device_mask_all(hldev); ++ vxge_hw_device_flush_io(hldev); ++ return IRQ_HANDLED; ++ } else if (unlikely(status == VXGE_HW_ERR_SLOT_FREEZE)) ++ return IRQ_HANDLED; ++ ++ vxge_debug_intr(VXGE_TRACE, "%s:%d Exiting...\n", __func__, __LINE__); ++ return IRQ_NONE; ++} ++ ++ ++ ++#ifdef CONFIG_PCI_MSI ++ ++irqreturn_t ++vxge_do_tx_msix_handle(int irq, void *dev_id) ++{ ++ struct vxge_fifo *fifo = (struct vxge_fifo *)dev_id; ++ ++ if (VXGE_CAN_CONT_ISR(dev_id, VXGE_HW_CHANNEL_TYPE_FIFO)) ++ return IRQ_HANDLED; ++ ++ VXGE_COMPLETE_VPATH_TX(fifo); ++ ++ VXGE_POLL_ISR_DONE(dev_id, VXGE_HW_CHANNEL_TYPE_FIFO); ++ ++ return IRQ_HANDLED; ++} ++ ++irqreturn_t ++vxge_do_rx_msix_handle(int irq, void *dev_id) ++{ ++ struct vxge_ring *ring = (struct vxge_ring *)dev_id; ++ ++ if (VXGE_CAN_CONT_ISR(dev_id, VXGE_HW_CHANNEL_TYPE_RING)) ++ return IRQ_HANDLED; ++ ++ adaptive_coalesce_rx_interrupts(ring); ++ ++ vxge_hw_vpath_poll_rx(ring->handle); ++ ++ VXGE_POLL_ISR_DONE(dev_id, VXGE_HW_CHANNEL_TYPE_RING); ++ ++ return IRQ_HANDLED; ++} ++ ++irqreturn_t ++vxge_do_rx_msix_napi_handle(int irq, void *dev_id) ++{ ++ struct vxge_ring *ring = (struct vxge_ring *)dev_id; ++ ++ vxge_hw_channel_msix_mask((struct __vxge_hw_channel *)ring->handle, ++ ring->rx_vector_no); ++ ++ adaptive_coalesce_rx_interrupts(ring); ++ ++ vxge_netif_do_rx_schedule(ring->ndev, &ring->napi); ++ return IRQ_HANDLED; ++} ++ ++irqreturn_t ++vxge_do_alarm_msix_handle(int irq, void *dev_id) ++{ ++ int i; ++ enum vxge_hw_status status; ++ struct vxge_vpath *vpath = (struct vxge_vpath *)dev_id; ++ struct vxgedev *vdev = vpath->vdev; ++ int msix_id = (vpath->handle->vpath->vp_id * ++ VXGE_HW_VPATH_MSIX_ACTIVE) + VXGE_ALARM_MSIX_ID; ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ ++ vxge_hw_vpath_msix_mask(vdev->vpaths[i].handle, msix_id); ++ status = vxge_hw_vpath_alarm_process(vdev->vpaths[i].handle, ++ vdev->exec_mode); ++ if (status == VXGE_HW_OK) { ++ vxge_hw_vpath_msix_unmask(vdev->vpaths[i].handle, msix_id); ++ continue; ++ } ++ ++ vxge_debug_intr(VXGE_ERR, ++ "%s: vxge_hw_vpath_alarm_process failed %x ", ++ VXGE_DRIVER_NAME, status); ++ } ++ return IRQ_HANDLED; ++} ++ ++static int vxge_alloc_msix(struct vxgedev *vdev) ++{ ++ int j, i, ret = 0; ++ int intr_cnt = 0; ++ int msix_intr_vect = 0; ++ vdev->intr_cnt = 0; ++ ++ /* Tx/Rx MSIX Vectors count */ ++ vdev->intr_cnt = vdev->no_of_vpath * 2; ++ ++ /* Alarm MSIX Vectors count */ ++ vdev->intr_cnt++; ++ ++ intr_cnt = (vdev->no_of_vpath * 2) + 1; ++ vdev->entries = kzalloc(intr_cnt * sizeof(struct msix_entry), ++ GFP_KERNEL); ++ if (!vdev->entries) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: memory allocation failed", ++ VXGE_DRIVER_NAME); ++ return -ENOMEM; ++ } ++ ++ vdev->vxge_entries = kzalloc(intr_cnt * sizeof(struct vxge_msix_entry), ++ GFP_KERNEL); ++ if (!vdev->vxge_entries) { ++ vxge_debug_init(VXGE_ERR, "%s: memory allocation failed", ++ VXGE_DRIVER_NAME); ++ kfree(vdev->entries); ++ return -ENOMEM; ++ } ++ ++ for (i = 0, j = 0; i < vdev->no_of_vpath; i++) { ++ ++ msix_intr_vect = i * VXGE_HW_VPATH_MSIX_ACTIVE; ++ ++ /* Initialize the fifo vector */ ++ vdev->entries[j].entry = msix_intr_vect; ++ vdev->vxge_entries[j].entry = msix_intr_vect; ++ vdev->vxge_entries[j].in_use = 0; ++ j++; ++ ++ /* Initialize the ring vector */ ++ vdev->entries[j].entry = msix_intr_vect + 1; ++ vdev->vxge_entries[j].entry = msix_intr_vect + 1; ++ vdev->vxge_entries[j].in_use = 0; ++ j++; ++ } ++ ++ /* Initialize the alarm vector */ ++ vdev->entries[j].entry = VXGE_ALARM_MSIX_ID; ++ vdev->vxge_entries[j].entry = VXGE_ALARM_MSIX_ID; ++ vdev->vxge_entries[j].in_use = 0; ++ ++ ret = pci_enable_msix(vdev->pdev, vdev->entries, intr_cnt); ++ ++ if (ret) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: MSI-X enable failed for %d vectors, ret: %d", ++ VXGE_DRIVER_NAME, intr_cnt, ret); ++ kfree(vdev->entries); ++ kfree(vdev->vxge_entries); ++ vdev->entries = NULL; ++ vdev->vxge_entries = NULL; ++ return -ENODEV; ++ } ++ return 0; ++} ++ ++ ++ ++static int vxge_enable_msix(struct vxgedev *vdev) ++{ ++ ++ int i, ret = 0; ++ /* 0 - Tx, 1 - Rx */ ++ int tim_msix_id[4] = {0, 1, 0, 0}; ++ ++ vdev->intr_cnt = 0; ++ ++ /* allocate msix vectors */ ++ ret = vxge_alloc_msix(vdev); ++ if (!ret) { ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ ++ /* If fifo or ring are not enabled ++ the MSIX vector for that should be set to 0 ++ Hence initializing this array to all 0s. ++ */ ++ vdev->vpaths[i].ring.rx_vector_no = ++ (vdev->vpaths[i].device_id * ++ VXGE_HW_VPATH_MSIX_ACTIVE) + 1; ++ ++ vxge_hw_vpath_msix_set( ++ vdev->vpaths[i].handle, ++ tim_msix_id, VXGE_ALARM_MSIX_ID); ++ } ++ } ++ ++ return ret; ++} ++ ++static void vxge_rem_msix_isr(struct vxgedev *vdev) ++{ ++ int intr_cnt; ++ ++ ++ for (intr_cnt = 0; intr_cnt < (vdev->no_of_vpath * 2 + 1); ++ intr_cnt++) { ++ if (vdev->vxge_entries[intr_cnt].in_use) { ++ vxge_synchronize_irq(vdev->entries[intr_cnt].vector); ++ free_irq(vdev->entries[intr_cnt].vector, ++ vdev->vxge_entries[intr_cnt].arg); ++ vdev->vxge_entries[intr_cnt].in_use = 0; ++ } ++ } ++ ++ kfree(vdev->entries); ++ kfree(vdev->vxge_entries); ++ vdev->entries = NULL; ++ vdev->vxge_entries = NULL; ++ ++ if (vdev->config.intr_type == MSI_X) { ++ pci_disable_msix(vdev->pdev); ++ ++ } ++} ++#endif ++ ++ ++ ++static void vxge_rem_isr(struct vxgedev *vdev) ++{ ++ struct __vxge_hw_device *hldev; ++ hldev = (struct __vxge_hw_device *) pci_get_drvdata(vdev->pdev); ++ ++#ifdef CONFIG_PCI_MSI ++ if (vdev->config.intr_type == MSI_X) { ++ vxge_rem_msix_isr(vdev); ++ } else ++#endif ++ if ( ++ ++ (vdev->config.intr_type == INTA)) { ++ vxge_synchronize_irq(vdev->pdev->irq); ++ free_irq(vdev->pdev->irq, vdev); ++ } ++} ++ ++static int vxge_add_isr(struct vxgedev *vdev) ++{ ++ int ret = 0; ++ ++ ++#ifdef CONFIG_PCI_MSI ++ int vp_idx = 0, intr_idx = 0, intr_cnt = 0, msix_idx = 0, irq_req = 0; ++ int pci_fun = PCI_FUNC(vdev->pdev->devfn); ++ ++ if (vdev->config.intr_type == MSI_X) ++ ret = vxge_enable_msix(vdev); ++ ++ if (ret) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: Enabling MSI-X Failed", VXGE_DRIVER_NAME); ++ vxge_debug_init(VXGE_ERR, ++ "%s: Defaulting to INTA", VXGE_DRIVER_NAME); ++ vdev->config.intr_type = INTA; ++ } ++ ++ if (vdev->config.intr_type == MSI_X) { ++ for (intr_idx = 0; ++ intr_idx < (vdev->no_of_vpath * ++ VXGE_HW_VPATH_MSIX_ACTIVE); intr_idx++) { ++ ++ msix_idx = intr_idx % VXGE_HW_VPATH_MSIX_ACTIVE; ++ irq_req = 0; ++ ++ switch (msix_idx) { ++ case 0: ++ snprintf(vdev->desc[intr_cnt], VXGE_INTR_STRLEN, ++ "%s:vxge:MSI-X %d - Tx - fn:%d vpath:%d", ++ vdev->ndev->name, ++ vdev->entries[intr_cnt].entry, ++ pci_fun, vp_idx); ++ ret = request_irq( ++ vdev->entries[intr_cnt].vector, ++ vxge_tx_msix_handle, 0, ++ vdev->desc[intr_cnt], ++ &vdev->vpaths[vp_idx].fifo); ++ vdev->vxge_entries[intr_cnt].arg = ++ &vdev->vpaths[vp_idx].fifo; ++ irq_req = 1; ++ break; ++ case 1: ++ snprintf(vdev->desc[intr_cnt], VXGE_INTR_STRLEN, ++ "%s:vxge:MSI-X %d - Rx - fn:%d vpath:%d", ++ vdev->ndev->name, ++ vdev->entries[intr_cnt].entry, ++ pci_fun, vp_idx); ++ ret = request_irq( ++ vdev->entries[intr_cnt].vector, ++ vdev->config.napi_enable ? ++ vxge_rx_msix_napi_handle: ++ vxge_rx_msix_handle, 0, ++ vdev->desc[intr_cnt], ++ &vdev->vpaths[vp_idx].ring); ++ vdev->vxge_entries[intr_cnt].arg = ++ &vdev->vpaths[vp_idx].ring; ++ irq_req = 1; ++ break; ++ } ++ ++ if (ret) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: vxge:" ++ "MSIX - %d Registration failed", ++ vdev->ndev->name, intr_cnt); ++ vxge_rem_msix_isr(vdev); ++ vdev->config.intr_type = INTA; ++ vxge_debug_init(VXGE_ERR, ++ "%s: vxge: Defaulting to INTA", ++ vdev->ndev->name); ++ goto INTA_MODE; ++ } ++ ++ if (irq_req) { ++ /* We requested for this msix interrupt */ ++ vdev->vxge_entries[intr_cnt].in_use = 1; ++ msix_idx += vdev->vpaths[vp_idx].device_id * ++ VXGE_HW_VPATH_MSIX_ACTIVE; ++ vxge_hw_vpath_msix_unmask( ++ vdev->vpaths[vp_idx].handle, ++ msix_idx); ++ intr_cnt++; ++ } ++ ++ /* Point to the next vpath handler */ ++ if (((intr_idx + 1) % VXGE_HW_VPATH_MSIX_ACTIVE == 0) ++ && (vp_idx < (vdev->no_of_vpath - 1))) ++ vp_idx++; ++ } ++ ++ intr_cnt = vdev->no_of_vpath * 2; ++ snprintf(vdev->desc[intr_cnt], VXGE_INTR_STRLEN, ++ "%s:vxge:MSI-X %d - Alarm - fn:%d", ++ vdev->ndev->name, ++ vdev->entries[intr_cnt].entry, ++ pci_fun); ++ /* For Alarm interrupts */ ++ ret = request_irq(vdev->entries[intr_cnt].vector, ++ vxge_alarm_msix_handle, 0, ++ vdev->desc[intr_cnt], ++ &vdev->vpaths[vp_idx]); ++ if (ret) { ++ vxge_debug_init(VXGE_ERR, ++ "%s:vxge:MSIX - %d Registration failed", ++ vdev->ndev->name, intr_cnt); ++ vxge_rem_msix_isr(vdev); ++ vdev->config.intr_type = INTA; ++ vxge_debug_init(VXGE_ERR, ++ "%s: Defaulting to INTA", ++ vdev->ndev->name); ++ goto INTA_MODE; ++ } ++ ++ msix_idx += (vdev->vpaths[0].handle->vpath->vp_id * ++ VXGE_HW_VPATH_MSIX_ACTIVE) + VXGE_ALARM_MSIX_ID; ++ ++ vxge_hw_vpath_msix_unmask(vdev->vpaths[0].handle, ++ msix_idx); ++ ++ vdev->vxge_entries[intr_cnt].in_use = 1; ++ vdev->vxge_entries[intr_cnt].arg = &vdev->vpaths[vp_idx]; ++ } ++INTA_MODE: ++#endif ++ ++ ++ ++ ++ if (vdev->config.intr_type == INTA) { ++ vxge_hw_device_set_intr_type(vdev->devh, ++ VXGE_HW_INTR_MODE_IRQLINE); ++ vxge_hw_vpath_tti_ci_set(vdev->devh, vdev->vpaths[0].device_id); ++ ++ snprintf(vdev->desc[0], VXGE_INTR_STRLEN, ++ "%s:vxge:INTA", vdev->ndev->name); ++ ret = request_irq((int) vdev->pdev->irq, ++ vdev->config.napi_enable ? vxge_isr_napi : vxge_isr, ++ IRQF_SHARED, vdev->desc[0], vdev); ++ if (ret) { ++ vxge_debug_init(VXGE_ERR, ++ "%s %s-%d: ISR registration failed", ++ VXGE_DRIVER_NAME, "IRQ", vdev->pdev->irq); ++ return -ENODEV; ++ } ++ vxge_debug_init(VXGE_TRACE, ++ "new %s-%d line allocated", ++ "IRQ", vdev->pdev->irq); ++ } ++ ++ return VXGE_HW_OK; ++} ++ ++static void vxge_poll_vp_reset(unsigned long data) ++{ ++ struct vxgedev *vdev = (struct vxgedev *)data; ++ int i, j = 0; ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ if (test_bit(i, &vdev->vp_reset)) { ++ vxge_reset_vpath(vdev, i); ++ j++; ++ } ++ } ++ if (j && (vdev->config.intr_type != MSI_X)) { ++ vxge_hw_device_unmask_all(vdev->devh); ++ vxge_hw_device_flush_io(vdev->devh); ++ } ++ ++ mod_timer(&vdev->vp_reset_timer, jiffies + HZ / 2); ++} ++ ++static void vxge_poll_vp_lockup(unsigned long data) ++{ ++ struct vxgedev *vdev = (struct vxgedev *)data; ++ int i; ++ struct vxge_ring *ring; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ ring = &vdev->vpaths[i].ring; ++ /* Did this vpath received any packets */ ++ if (ring->stats.prev_rx_frms == ring->stats.rx_frms) { ++ status = vxge_hw_vpath_check_leak(ring->handle); ++ ++ /* Did it received any packets last time */ ++ if ((VXGE_HW_FAIL == status) && ++ (VXGE_HW_FAIL == ring->last_status)) { ++ ++ /* schedule vpath reset */ ++ if (!test_and_set_bit(i, &vdev->vp_reset)) { ++ ++ /* disable interrupts for this vpath */ ++ vxge_vpath_intr_disable(vdev, i); ++ ++ /* stop the queue for this vpath */ ++ vxge_stop_tx_queue(&vdev->vpaths[i]. ++ fifo); ++ continue; ++ } ++ } ++ } ++ ring->stats.prev_rx_frms = ring->stats.rx_frms; ++ ring->last_status = status; ++ } ++ ++ /* Check every 1 milli second */ ++ mod_timer(&vdev->vp_lockup_timer, jiffies + HZ / 1000); ++} ++ ++/** ++ * vxge_open ++ * @dev: pointer to the device structure. ++ * ++ * This function is the open entry point of the driver. It mainly calls a ++ * function to allocate Rx buffers and inserts them into the buffer ++ * descriptors and then enables the Rx part of the NIC. ++ * Return value: '0' on success and an appropriate (-)ve integer as ++ * defined in errno.h file on failure. ++ */ ++int ++vxge_open(struct net_device *dev) ++{ ++ enum vxge_hw_status status; ++ struct vxgedev *vdev; ++ struct __vxge_hw_device *hldev; ++ int ret = 0; ++ int i; ++ u64 val64, function_mode; ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s: %s:%d", dev->name, __func__, __LINE__); ++ ++ vdev = (struct vxgedev *)netdev_priv(dev); ++ hldev = (struct __vxge_hw_device *) pci_get_drvdata(vdev->pdev); ++ function_mode = vdev->config.device_hw_info.function_mode; ++ ++ /* make sure you have link off by default every time Nic is ++ * initialized */ ++ netif_carrier_off(dev); ++ ++ /* Open VPATHs */ ++ status = vxge_open_vpaths(vdev); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: fatal: Vpath open failed", vdev->ndev->name); ++ ret = -EPERM; ++ goto out0; ++ } ++ ++ vdev->mtu = dev->mtu; ++ ++ status = vxge_add_isr(vdev); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: fatal: ISR add failed", dev->name); ++ ret = -EPERM; ++ goto out1; ++ } ++ ++#if defined(HAVE_NETDEV_POLL) ++ /* Initialize napi */ ++ if (vdev->config.napi_enable) { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) ++ if (vdev->config.intr_type != MSI_X) ++ dev->poll = vxge_poll_inta; ++ else ++ dev->poll = vxge_poll_msix; ++ dev->weight = vdev->config.napi_weight; ++#else ++ if (vdev->config.intr_type != MSI_X) { ++ netif_napi_add(dev, &vdev->napi, vxge_poll_inta, ++ vdev->config.napi_weight); ++ VXGE_NAPI_ENABLE(&vdev->napi); ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ vdev->vpaths[i].ring.napi_p = &vdev->napi; ++ } else { ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ netif_napi_add(dev, &vdev->vpaths[i].ring.napi, ++ vxge_poll_msix, vdev->config.napi_weight); ++ VXGE_NAPI_ENABLE(&vdev->vpaths[i].ring.napi); ++ vdev->vpaths[i].ring.napi_p = ++ &vdev->vpaths[i].ring.napi; ++ } ++ } ++#endif ++ } ++#endif ++ ++ /* configure RTH */ ++ if (vdev->config.rx_steering_type) { ++ status = vxge_rth_configure(vdev); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: fatal: RTH configuration failed", ++ dev->name); ++ ret = -EPERM; ++ goto out2; ++ } ++ } ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ /* set initial mtu before enabling the device */ ++ status = vxge_hw_vpath_mtu_set(vdev->vpaths[i].handle, ++ vdev->mtu); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: fatal: can not set new MTU", dev->name); ++ ret = -EPERM; ++ goto out2; ++ } ++ } ++ ++ /* configure tx_bw_limit */ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ int vp_id = vdev->vpaths[i].device_id; ++ status = vxge_hw_vpath_bandwidth_set(vdev->devh, ++ vp_id, ++ VXGE_HW_CHANNEL_TYPE_FIFO, ++ hldev->config.vp_config[vp_id].tx_bw_limit, ++ vdev->mtu); ++ ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: fatal: tx_bw_limit_set failed", dev->name); ++ ret = -EPERM; ++ goto out2; ++ } ++ } ++ ++ VXGE_DEVICE_DEBUG_LEVEL_SET(VXGE_TRACE, VXGE_COMPONENT_LL, vdev); ++ vxge_debug_init(vdev->level_trace, ++ "%s: MTU is %d", vdev->ndev->name, vdev->mtu); ++ VXGE_DEVICE_DEBUG_LEVEL_SET(VXGE_ERR, VXGE_COMPONENT_LL, vdev); ++ ++ /* Reprogram the DA table with populated mac addresses */ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ vxge_restore_vpath_mac_addr(&vdev->vpaths[i]); ++ vxge_restore_vpath_vid_table(&vdev->vpaths[i]); ++ } ++ ++ ++ ++ /* Enable vpath to sniff all unicast/multicast traffic that's not ++ * addressed to them. We allow promiscuous mode for the PF only ++ */ ++ ++ val64 = 0; ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) ++ val64 |= VXGE_HW_RXMAC_AUTHORIZE_ALL_ADDR_VP(i); ++ ++ vxge_hw_mgmt_reg_write(vdev->devh, ++ vxge_hw_mgmt_reg_type_mrpcim, ++ 0, ++ (ulong)offsetof(struct vxge_hw_mrpcim_reg, ++ rxmac_authorize_all_addr), ++ val64); ++ ++ vxge_hw_mgmt_reg_write(vdev->devh, ++ vxge_hw_mgmt_reg_type_mrpcim, ++ 0, ++ (ulong)offsetof(struct vxge_hw_mrpcim_reg, ++ rxmac_authorize_all_vid), ++ val64); ++ ++ vxge_set_multicast(dev); ++ ++ /* Enabling Bcast and mcast for all vpath */ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ status = vxge_hw_vpath_bcast_enable(vdev->vpaths[i].handle); ++ if (status != VXGE_HW_OK) ++ vxge_debug_init(VXGE_ERR, ++ "%s : Can not enable bcast for vpath " ++ "id %d", dev->name, i); ++ ++ if (vdev->config.rec_all_vid) { ++ status = ++ vxge_hw_vpath_all_vid_enable(vdev->vpaths[i].handle); ++ if (status != VXGE_HW_OK) ++ vxge_debug_init(VXGE_ERR, ++ "%s : Can not enable all vid for vpath\ ++ id %d \n", dev->name, i); ++ } ++ } ++ ++ vxge_hw_device_setpause_data(vdev->devh, 0, ++ vdev->config.tx_pause_enable, ++ vdev->config.rx_pause_enable); ++ ++ if (vdev->vp_reset_timer.function == NULL) ++ vxge_os_timer(vdev->vp_reset_timer, ++ vxge_poll_vp_reset, vdev, (HZ/2)); ++ ++ /* ++ * There is no need to check for RxD leak and RxD lookup due to ++ * bug3618 if Titan 1A is used. ++ */ ++ if (vdev->titan1 && ++ vdev->config.doorbell_mode == VXGE_HW_DOORBELL_MODE_ENABLE) { ++ if (vdev->vp_lockup_timer.function == NULL) ++ vxge_os_timer(vdev->vp_lockup_timer, ++ vxge_poll_vp_lockup, vdev, (HZ/2)); ++ } ++ ++ ++ ++ set_bit(__VXGE_STATE_CARD_UP, &vdev->state); ++ ++ smp_wmb(); ++ ++ if (vxge_hw_device_link_state_get(vdev->devh) == VXGE_HW_LINK_UP) { ++ netif_carrier_on(vdev->ndev); ++ printk(KERN_NOTICE "%s: Link Up\n", vdev->ndev->name); ++ vdev->stats.link_up++; ++ } ++ ++ vxge_hw_device_intr_enable(vdev->devh); ++ ++ smp_wmb(); ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ vxge_hw_vpath_enable(vdev->vpaths[i].handle); ++ if (vdev->config.doorbell_mode == VXGE_HW_DOORBELL_MODE_ENABLE) { ++ smp_wmb(); ++ vxge_hw_vpath_rx_doorbell_init(vdev->vpaths[i].handle); ++ } ++ } ++ ++ vxge_start_all_tx_queue(vdev); ++ goto out0; ++ ++out2: ++ vxge_rem_isr(vdev); ++ ++ /* Disable napi */ ++ if (vdev->config.napi_enable) { ++ if (vdev->config.intr_type != MSI_X) ++ VXGE_NAPI_DISABLE(&vdev->napi); ++ else { ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ VXGE_NAPI_DISABLE(&vdev->vpaths[i].ring.napi); ++ } ++ } ++ ++out1: ++ vxge_close_vpaths(vdev, 0); ++out0: ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s: %s:%d Exiting...", ++ dev->name, __func__, __LINE__); ++ return ret; ++} ++ ++/* Loop throught the mac address list and delete all the entries */ ++void vxge_free_mac_add_list(struct vxge_vpath *vpath) ++{ ++ ++ struct list_head *entry, *next; ++ if (list_empty(&vpath->mac_addr_list)) ++ return; ++ ++ list_for_each_safe(entry, next, &vpath->mac_addr_list) { ++ list_del(entry); ++ kfree((struct vxge_mac_addrs *)entry); ++ } ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) ++static void vxge_napi_del_all(struct vxgedev *vdev) ++{ ++ int i; ++ if (vdev->config.intr_type != MSI_X) ++ netif_napi_del(&vdev->napi); ++ else { ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ netif_napi_del(&vdev->vpaths[i].ring.napi); ++ } ++ return; ++} ++#endif ++ ++int do_vxge_close(struct net_device *dev, int do_io) ++{ ++ enum vxge_hw_status status; ++ struct vxgedev *vdev; ++ struct __vxge_hw_device *hldev; ++ int i; ++ u64 val64, vpath_vector; ++ vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d", ++ dev->name, __func__, __LINE__); ++ ++ vdev = (struct vxgedev *)netdev_priv(dev); ++ hldev = (struct __vxge_hw_device *) pci_get_drvdata(vdev->pdev); ++ ++ if (unlikely(!is_vxge_card_up(vdev))) ++ return 0; ++ ++ /* If vxge_handle_crit_err task is executing, ++ * wait till it completes. */ ++ while (test_and_set_bit(__VXGE_STATE_RESET_CARD, &vdev->state)) ++ msleep(50); ++ ++ clear_bit(__VXGE_STATE_CARD_UP, &vdev->state); ++ if (do_io) { ++ /* Put the vpath back in normal mode */ ++ vpath_vector = vxge_mBIT(vdev->vpaths[0].device_id); ++ status = vxge_hw_mgmt_reg_read(vdev->devh, ++ vxge_hw_mgmt_reg_type_mrpcim, ++ 0, ++ (ulong)offsetof( ++ struct vxge_hw_mrpcim_reg, ++ rts_mgr_cbasin_cfg), ++ &val64); ++ ++ if (status == VXGE_HW_OK) { ++ val64 &= ~vpath_vector; ++ status = vxge_hw_mgmt_reg_write(vdev->devh, ++ vxge_hw_mgmt_reg_type_mrpcim, ++ 0, ++ (ulong)offsetof( ++ struct vxge_hw_mrpcim_reg, ++ rts_mgr_cbasin_cfg), ++ val64); ++ } ++ ++ /* Remove the function 0 from promiscous mode */ ++ vxge_hw_mgmt_reg_write(vdev->devh, ++ vxge_hw_mgmt_reg_type_mrpcim, ++ 0, ++ (ulong)offsetof(struct vxge_hw_mrpcim_reg, ++ rxmac_authorize_all_addr), ++ 0); ++ ++ vxge_hw_mgmt_reg_write(vdev->devh, ++ vxge_hw_mgmt_reg_type_mrpcim, ++ 0, ++ (ulong)offsetof(struct vxge_hw_mrpcim_reg, ++ rxmac_authorize_all_vid), ++ 0); ++ ++ smp_wmb(); ++ } ++ ++ /* ++ * There is no need to check for RxD leak and RxD lookup due to ++ * bug3618 if Titan 1A is used. ++ */ ++ if (vdev->titan1 && ++ vdev->config.doorbell_mode == VXGE_HW_DOORBELL_MODE_ENABLE) ++ del_timer_sync(&vdev->vp_lockup_timer); ++ ++ del_timer_sync(&vdev->vp_reset_timer); ++ ++ /* Disable napi */ ++ if (vdev->config.napi_enable) { ++ if (vdev->config.intr_type != MSI_X) ++ VXGE_NAPI_DISABLE(&vdev->napi); ++ else { ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ VXGE_NAPI_DISABLE(&vdev->vpaths[i].ring.napi); ++ } ++ } ++ ++ netif_carrier_off(vdev->ndev); ++ printk(KERN_NOTICE "%s: Link Down\n", vdev->ndev->name); ++ vxge_stop_all_tx_queue(vdev); ++ ++ /* Note that at this point xmit() is stopped by upper layer */ ++ if (do_io) ++ vxge_hw_device_intr_disable(vdev->devh); ++ ++ mdelay(1000); ++ ++ vxge_rem_isr(vdev); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) ++ if (vdev->config.napi_enable) ++ vxge_napi_del_all(vdev); ++#endif ++ ++ if (do_io) ++ vxge_reset_all_vpaths(vdev); ++ ++ vxge_close_vpaths(vdev, 0); ++ ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s: %s:%d Exiting...", dev->name, __func__, __LINE__); ++ ++ clear_bit(__VXGE_STATE_RESET_CARD, &vdev->state); ++ ++ return 0; ++} ++ ++/** ++ * vxge_close ++ * @dev: device pointer. ++ * ++ * This is the stop entry point of the driver. It needs to undo exactly ++ * whatever was done by the open entry point, thus it's usually referred to ++ * as the close function.Among other things this function mainly stops the ++ * Rx side of the NIC and frees all the Rx buffers in the Rx rings. ++ * Return value: '0' on success and an appropriate (-)ve integer as ++ * defined in errno.h file on failure. ++ */ ++int ++vxge_close(struct net_device *dev) ++{ ++ do_vxge_close(dev, 1); ++ return 0; ++} ++ ++/** ++ * vxge_change_mtu ++ * @dev: net device pointer. ++ * @new_mtu :the new MTU size for the device. ++ * ++ * A driver entry point to change MTU size for the device. Before changing ++ * the MTU the device must be stopped. ++ */ ++static int vxge_change_mtu(struct net_device *dev, int new_mtu) ++{ ++ struct vxgedev *vdev = netdev_priv(dev); ++ ++ vxge_debug_entryexit(vdev->level_trace, ++ "%s:%d", __func__, __LINE__); ++ if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > VXGE_HW_MAX_MTU)) { ++ vxge_debug_init(vdev->level_err, ++ "%s: mtu size is invalid", dev->name); ++ return -EPERM; ++ } ++ ++ /* check if device is down already */ ++ if (unlikely(!is_vxge_card_up(vdev))) { ++ /* just store new value, will use later on open() */ ++ dev->mtu = new_mtu; ++ vxge_debug_init(vdev->level_err, ++ "%s", "device is down on MTU change"); ++ return 0; ++ } ++ ++ vxge_debug_init(vdev->level_trace, ++ "trying to apply new MTU %d", new_mtu); ++ ++ if (vxge_close(dev)) ++ return -EIO; ++ ++ dev->mtu = new_mtu; ++ vdev->mtu = new_mtu; ++ ++ if (vxge_open(dev)) ++ return -EIO; ++ ++ vxge_debug_init(vdev->level_trace, ++ "%s: MTU changed to %d", vdev->ndev->name, new_mtu); ++ ++ vxge_debug_entryexit(vdev->level_trace, ++ "%s:%d Exiting...", __func__, __LINE__); ++ ++ return 0; ++} ++ ++/** ++ * vxge_get_stats ++ * @dev: pointer to the device structure ++ * ++ * Updates the device statistics structure. This function updates the device ++ * statistics structure in the net_device structure and returns a pointer ++ * to the same. ++ */ ++static struct net_device_stats * ++vxge_get_stats(struct net_device *dev) ++{ ++ struct vxgedev *vdev; ++ struct net_device_stats *net_stats; ++ int k; ++ ++ vdev = netdev_priv(dev); ++ ++ net_stats = &vdev->stats.net_stats; ++ ++ memset(net_stats, 0, sizeof(struct net_device_stats)); ++ ++ for (k = 0; k < vdev->no_of_vpath; k++) { ++ net_stats->rx_packets += vdev->vpaths[k].ring.stats.rx_frms; ++ net_stats->rx_bytes += vdev->vpaths[k].ring.stats.rx_bytes; ++ net_stats->rx_errors += vdev->vpaths[k].ring.stats.rx_errors; ++ net_stats->multicast += vdev->vpaths[k].ring.stats.rx_mcast; ++ net_stats->rx_dropped += ++ vdev->vpaths[k].ring.stats.rx_dropped; ++ ++ net_stats->tx_packets += vdev->vpaths[k].fifo.stats.tx_frms; ++ net_stats->tx_bytes += vdev->vpaths[k].fifo.stats.tx_bytes; ++ net_stats->tx_errors += vdev->vpaths[k].fifo.stats.tx_errors; ++ } ++ ++ return net_stats; ++} ++ ++ ++/* ++ * vxge_ioctl ++ * @dev: Device pointer. ++ * @ifr: An IOCTL specefic structure, that can contain a pointer to ++ * a proprietary structure used to pass information to the driver. ++ * @cmd: This is used to distinguish between the different commands that ++ * can be passed to the IOCTL functions. ++ * ++ * Entry point for the Ioctl. ++ * This function has support for ethtool, adding multiple MAC addresses on ++ * the NIC and some DBG commands for the util tool. ++ */ ++static int vxge_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ ++ ++ ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s:%d\n", __func__, __LINE__); ++ switch (cmd) { ++#ifndef SET_ETHTOOL_OPS ++ case SIOCETHTOOL: ++ return vxge_ethtool(dev, rq); ++#endif ++ /* Private IOCTLs used by the privilege mode app */ ++ ++ ++ /* Other utility ioctls that can be used */ ++#ifdef VXGE_TRACE_INTO_CIRCULAR_ARR ++ /* Dumping the Trace buffer */ ++ case SIOCDEVPRIVATE + 15: ++ { ++ struct vxgedev *vdev = netdev_priv(dev); ++ vxge_hw_device_trace_dump(vdev->devh); ++ return 0; ++ } ++ /* Reading the Trace buffer */ ++ case SIOCDEVPRIVATE + 2: ++ { ++ struct vxgedev *vdev = netdev_priv(dev); ++ char *buffer; ++ unsigned buf_size = VXGE_HW_DEF_CIRCULAR_ARR; ++ unsigned read_length = 0; ++ struct tracebufInfo *tbufinfo = (struct tracebufInfo *) ++ rq->ifr_data; ++ buffer = kmalloc(buf_size, GFP_KERNEL); ++ if (buffer == NULL) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: memory allocation failed", ++ VXGE_DRIVER_NAME); ++ return -ENOMEM; ++ } ++ vxge_hw_device_trace_read(vdev->devh, ++ buffer, buf_size, ++ &read_length); ++ ++ memcpy(tbufinfo->buffer, buffer, read_length); ++ tbufinfo->read_length = read_length; ++ ++ if (copy_to_user((void *) tbufinfo->buffer, ++ (void *) buffer, read_length)) ++ return -EFAULT; ++ ++ kfree(buffer); ++ return 0; ++ } ++#endif ++ ++ default: ++ return -EOPNOTSUPP; ++ } ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s:%d Exiting...\n", __func__, __LINE__); ++ return 0; ++ ++} ++ ++ ++/** ++ * vxge_tx_watchdog ++ * @dev: pointer to net device structure ++ * ++ * Watchdog for transmit side. ++ * This function is triggered if the Tx Queue is stopped ++ * for a pre-defined amount of time when the Interface is still up. ++ */ ++static void ++vxge_tx_watchdog(struct net_device *dev) ++{ ++ struct vxgedev *vdev; ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s:%d", __func__, __LINE__); ++ ++ vdev = (struct vxgedev *)netdev_priv(dev); ++ ++ vdev->cric_err_event = VXGE_HW_EVENT_RESET_START; ++ ++ vxge_reset(vdev); ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s:%d Exiting...", __func__, __LINE__); ++} ++ ++/** ++ * vxge_vlan_rx_register ++ * @dev: net device pointer. ++ * @grp: vlan group ++ * ++ * Vlan group registration ++ */ ++static void ++vxge_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) ++{ ++ struct vxgedev *vdev; ++ struct vxge_vpath *vpath; ++ int vp; ++ u64 vid; ++ enum vxge_hw_status status; ++ int i; ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s:%d", __func__, __LINE__); ++ ++ vdev = (struct vxgedev *)netdev_priv(dev); ++ ++ vpath = &vdev->vpaths[0]; ++ if ((NULL == grp) && (vpath->is_open)) { ++ /* Get the first vlan */ ++ status = vxge_hw_vpath_vid_get_vpn(vpath->handle, &vid, ++ vpath->handle->vpath->vp_id); ++ ++ while (status == VXGE_HW_OK) { ++ ++ /* Delete this vlan from the vid table */ ++ for (vp = 0; vp < vdev->no_of_vpath; vp++) { ++ vpath = &vdev->vpaths[vp]; ++ if (!vpath->is_open) ++ continue; ++ ++ vxge_hw_vpath_vid_delete_vpn(vpath->handle, vid, ++ vpath->handle->vpath->vp_id); ++ } ++ ++ /* Get the next vlan to be deleted */ ++ vpath = &vdev->vpaths[0]; ++ status = vxge_hw_vpath_vid_get_vpn(vpath->handle, &vid, ++ vpath->handle->vpath->vp_id); ++ } ++ } ++ ++ vdev->vlgrp = grp; ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ if (vdev->vpaths[i].is_configured) ++ vdev->vpaths[i].ring.vlgrp = grp; ++ ++ if (grp && (vdev->vlan_tag_strip == ++ VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE)) ++ vdev->vpaths[i].ring.rx_vlan_stripped = TRUE; ++ else ++ vdev->vpaths[i].ring.rx_vlan_stripped = FALSE; ++ } ++ ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s:%d Exiting...", __func__, __LINE__); ++} ++ ++/** ++ * vxge_vlan_rx_add_vid ++ * @dev: net device pointer. ++ * @vid: vid ++ * ++ * Add the vlan id to the devices vlan id table ++ */ ++static void ++vxge_vlan_rx_add_vid(struct net_device *dev, unsigned short vid) ++{ ++ struct vxgedev *vdev; ++ struct vxge_vpath *vpath; ++ int vp_id; ++ ++ vdev = (struct vxgedev *)netdev_priv(dev); ++ ++ /* Add these vlan to the vid table */ ++ for (vp_id = 0; vp_id < vdev->no_of_vpath; vp_id++) { ++ vpath = &vdev->vpaths[vp_id]; ++ if (!vpath->is_open) ++ continue; ++ vxge_hw_vpath_vid_add_vpn(vpath->handle, vid, ++ vpath->handle->vpath->vp_id); ++ } ++} ++ ++/** ++ * vxge_vlan_rx_add_vid ++ * @dev: net device pointer. ++ * @vid: vid ++ * ++ * Remove the vlan id from the device's vlan id table ++ */ ++static void ++vxge_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) ++{ ++ struct vxgedev *vdev; ++ struct vxge_vpath *vpath; ++ int vp_id; ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s:%d", __func__, __LINE__); ++ ++ vdev = (struct vxgedev *)netdev_priv(dev); ++ ++ vlan_group_set_device(vdev->vlgrp, vid, NULL); ++ ++ /* Delete this vlan from the vid table */ ++ for (vp_id = 0; vp_id < vdev->no_of_vpath; vp_id++) { ++ vpath = &vdev->vpaths[vp_id]; ++ if (!vpath->is_open) ++ continue; ++ vxge_hw_vpath_vid_delete_vpn(vpath->handle, vid, ++ vpath->handle->vpath->vp_id); ++ } ++ vxge_debug_entryexit(VXGE_TRACE, ++ "%s:%d Exiting...", __func__, __LINE__); ++} ++ ++ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 28)) ++static const struct net_device_ops vxge_netdev_ops = { ++ .ndo_open = vxge_open, ++ .ndo_stop = vxge_close, ++ .ndo_get_stats = vxge_get_stats, ++ .ndo_start_xmit = vxge_xmit, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_set_multicast_list = vxge_set_multicast, ++ ++ .ndo_do_ioctl = vxge_ioctl, ++ ++ .ndo_set_mac_address = vxge_set_mac_addr, ++ .ndo_change_mtu = vxge_change_mtu, ++ .ndo_vlan_rx_register = vxge_vlan_rx_register, ++ .ndo_vlan_rx_kill_vid = vxge_vlan_rx_kill_vid, ++ .ndo_vlan_rx_add_vid = vxge_vlan_rx_add_vid, ++ ++ .ndo_tx_timeout = vxge_tx_watchdog, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = vxge_netpoll, ++#endif ++}; ++#endif ++ ++int __devinit vxge_device_register(struct __vxge_hw_device *hldev, ++ struct vxge_config *config, ++ int high_dma, int no_of_vpath, ++ struct vxgedev **vdev_out) ++{ ++ struct net_device *ndev; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct vxgedev *vdev; ++ int i, ret = 0; ++ u64 stat; ++ ++ *vdev_out = NULL; ++ ++ if (config->tx_steering_type == TX_MULTIQ_STEERING) ++ ndev = alloc_etherdev_mq(sizeof(struct vxgedev), no_of_vpath); ++ else ++ ndev = alloc_etherdev_mq(sizeof(struct vxgedev), 1); ++ ++ if (ndev == NULL) { ++ vxge_debug_init( ++ vxge_hw_device_trace_level_get(hldev), ++ "%s : device allocation failed", __func__); ++ ret = -ENODEV; ++ goto _out0; ++ } ++ ++ vxge_debug_entryexit( ++ vxge_hw_device_trace_level_get(hldev), ++ "%s: %s:%d Entering...", ++ ndev->name, __func__, __LINE__); ++ ++ vdev = netdev_priv(ndev); ++ memset(vdev, 0, sizeof(struct vxgedev)); ++ ++ vdev->ndev = ndev; ++ vdev->devh = hldev; ++ vdev->pdev = hldev->pdev; ++ memcpy(&vdev->config, config, sizeof(struct vxge_config)); ++ vdev->rx_csum = 1; /* Enable Rx CSUM by default. */ ++ ++ SET_NETDEV_DEV(ndev, &vdev->pdev->dev); ++ ++ ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX | ++ NETIF_F_HW_VLAN_FILTER; ++ /* Driver entry points */ ++ ndev->irq = vdev->pdev->irq; ++ ndev->base_addr = (unsigned long) hldev->bar0; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)) ++ ndev->open = &vxge_open; ++ ndev->stop = &vxge_close; ++ ndev->hard_start_xmit = &vxge_xmit; ++ ndev->get_stats = &vxge_get_stats; ++ ndev->set_multicast_list = &vxge_set_multicast; ++ ndev->set_mac_address = &vxge_set_mac_addr; ++ ++ ndev->do_ioctl = &vxge_ioctl; ++ ++ ndev->change_mtu = &vxge_change_mtu; ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ ndev->poll_controller = vxge_netpoll; ++#endif ++ ndev->vlan_rx_register = vxge_vlan_rx_register; ++ ndev->vlan_rx_add_vid = vxge_vlan_rx_add_vid; ++ ndev->vlan_rx_kill_vid = vxge_vlan_rx_kill_vid; ++ ++#ifndef VXGE_HW_TITAN_EMULATION ++ ndev->tx_timeout = &vxge_tx_watchdog; ++#endif ++#else ++ ndev->netdev_ops = &vxge_netdev_ops; ++#endif ++ ++ ndev->watchdog_timeo = VXGE_LL_WATCH_DOG_TIMEOUT; ++ ++#ifdef SET_ETHTOOL_OPS ++ initialize_ethtool_ops(ndev); ++#endif ++ ++ /* Allocate memory for vpath */ ++ vdev->vpaths = kzalloc((sizeof(struct vxge_vpath)) * ++ no_of_vpath, GFP_KERNEL); ++ if (!vdev->vpaths) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: vpath memory allocation failed", ++ vdev->ndev->name); ++ ret = -ENODEV; ++ goto _out1; ++ } ++ ++ ndev->features |= NETIF_F_SG; ++ ++ ndev->features |= NETIF_F_HW_CSUM; ++ vxge_debug_init(vxge_hw_device_trace_level_get(hldev), ++ "%s : checksuming enabled", __func__); ++ ++ if (high_dma) { ++ ndev->features |= NETIF_F_HIGHDMA; ++ vxge_debug_init(vxge_hw_device_trace_level_get(hldev), ++ "%s : using High DMA", __func__); ++ } ++ ++#ifdef NETIF_F_TSO ++ ndev->features |= NETIF_F_TSO; ++#ifdef NETIF_F_TSO6 ++ ndev->features |= NETIF_F_TSO6; ++#endif ++#endif ++ ++#ifdef NETIF_F_UFO ++ ndev->features |= NETIF_F_UFO; ++#endif ++ ++ if (vdev->config.lro_enable == VXGE_HW_GRO_ENABLE) { ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ++ ndev->features |= NETIF_F_GRO; ++#endif ++ } ++ ++ ++ if (vdev->config.tx_steering_type == TX_MULTIQ_STEERING) ++ vxge_tx_queues_set(ndev, no_of_vpath); ++ ++ ++#ifdef NETIF_F_LLTX ++ ndev->features |= NETIF_F_LLTX; ++#endif ++ ++ for (i = 0; i < no_of_vpath; i++) ++ spin_lock_init(&vdev->vpaths[i].fifo.tx_lock); ++ ++ if (register_netdev(ndev)) { ++ vxge_debug_init(vxge_hw_device_trace_level_get(hldev), ++ "%s: %s : device registration failed!", ++ ndev->name, __func__); ++ ret = -ENODEV; ++ goto _out2; ++ } ++ ++ /* Set the factory defined MAC address initially */ ++ ndev->addr_len = ETH_ALEN; ++ ++ /* Make Link state as off at this point, when the Link change ++ * interrupt comes the state will be automatically changed to ++ * the right state. ++ */ ++ netif_carrier_off(ndev); ++ ++ vxge_debug_init(vxge_hw_device_trace_level_get(hldev), ++ "%s: Ethernet device registered", ++ ndev->name); ++ ++ *vdev_out = vdev; ++ ++ /* Resetting the Device stats */ ++ status = vxge_hw_mrpcim_stats_access( ++ hldev, ++ VXGE_HW_STATS_OP_CLEAR_ALL_STATS, ++ 0, ++ 0, ++ &stat); ++ ++ if (status == VXGE_HW_ERR_PRIVILAGED_OPEARATION) ++ vxge_debug_init( ++ vxge_hw_device_trace_level_get(hldev), ++ "%s: device stats clear returns" ++ "VXGE_HW_ERR_PRIVILAGED_OPEARATION", ndev->name); ++ ++ vxge_debug_entryexit(vxge_hw_device_trace_level_get(hldev), ++ "%s: %s:%d Exiting...", ++ ndev->name, __func__, __LINE__); ++ ++ return ret; ++_out2: ++ kfree(vdev->vpaths); ++_out1: ++ free_netdev(ndev); ++_out0: ++ return ret; ++} ++ ++/* ++ * vxge_device_unregister ++ * ++ * This function will unregister and free network device ++ */ ++void ++vxge_device_unregister(struct __vxge_hw_device *hldev) ++{ ++ struct vxgedev *vdev; ++ struct net_device *dev; ++ char buf[IFNAMSIZ]; ++#if ((VXGE_DEBUG_INIT & VXGE_DEBUG_MASK) || \ ++ (VXGE_DEBUG_ENTRYEXIT & VXGE_DEBUG_MASK)) ++ u32 level_trace; ++#endif ++ ++ dev = hldev->ndev; ++ vdev = netdev_priv(dev); ++#if ((VXGE_DEBUG_INIT & VXGE_DEBUG_MASK) || \ ++ (VXGE_DEBUG_ENTRYEXIT & VXGE_DEBUG_MASK)) ++ level_trace = vdev->level_trace; ++#endif ++ vxge_debug_entryexit(level_trace, ++ "%s: %s:%d", vdev->ndev->name, __func__, __LINE__); ++ ++ memcpy(buf, vdev->ndev->name, IFNAMSIZ); ++ ++ /* in 2.6 will call stop() if device is up */ ++ unregister_netdev(dev); ++ ++ flush_scheduled_work(); ++ ++ vxge_debug_init(level_trace, "%s: ethernet device unregistered", buf); ++ vxge_debug_entryexit(level_trace, ++ "%s: %s:%d Exiting...", buf, __func__, __LINE__); ++} ++ ++/* ++ * vxge_callback_crit_err ++ * ++ * This function is called by the alarm handler in interrupt context. ++ * Driver must analyze it based on the event type. ++ */ ++static void ++vxge_callback_crit_err(struct __vxge_hw_device *hldev, ++ enum vxge_hw_event type, u64 vp_id) ++{ ++ struct net_device *dev = hldev->ndev; ++ struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev); ++ int vpath_idx; ++ ++ vxge_debug_entryexit(vdev->level_trace, ++ "%s: %s:%d", vdev->ndev->name, __func__, __LINE__); ++ ++ /* Note: This event type should be used for device wide ++ * indications only - Serious errors, Slot freeze and critical errors ++ */ ++ vdev->cric_err_event = type; ++ ++ for (vpath_idx = 0; vpath_idx < vdev->no_of_vpath; vpath_idx++) ++ if (vdev->vpaths[vpath_idx].device_id == vp_id) ++ break; ++ ++ if (!test_bit(__VXGE_STATE_RESET_CARD, &vdev->state)) { ++ if (type == VXGE_HW_EVENT_SLOT_FREEZE) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: Slot is frozen", vdev->ndev->name); ++ } else if (type == VXGE_HW_EVENT_SERR) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: Encountered Serious Error", ++ vdev->ndev->name); ++ } else if (type == VXGE_HW_EVENT_CRITICAL_ERR) ++ vxge_debug_init(VXGE_ERR, ++ "%s: Encountered Critical Error", ++ vdev->ndev->name); ++ } ++ ++ if ((type == VXGE_HW_EVENT_SERR) || ++ (type == VXGE_HW_EVENT_SLOT_FREEZE)) { ++ if (unlikely(vdev->exec_mode)) ++ clear_bit(__VXGE_STATE_CARD_UP, &vdev->state); ++ } else if (type == VXGE_HW_EVENT_CRITICAL_ERR) { ++ vxge_hw_device_mask_all(hldev); ++ if (unlikely(vdev->exec_mode)) ++ clear_bit(__VXGE_STATE_CARD_UP, &vdev->state); ++ } else if ((type == VXGE_HW_EVENT_FIFO_ERR) || ++ (type == VXGE_HW_EVENT_VPATH_ERR)) { ++ ++ if (unlikely(vdev->exec_mode)) ++ clear_bit(__VXGE_STATE_CARD_UP, &vdev->state); ++ else { ++ /* check if this vpath is already set for reset */ ++ if (!test_and_set_bit(vpath_idx, &vdev->vp_reset)) { ++ ++ /* disable interrupts for this vpath */ ++ vxge_vpath_intr_disable(vdev, vpath_idx); ++ ++ /* stop the queue for this vpath */ ++ vxge_stop_tx_queue(&vdev->vpaths[vpath_idx]. ++ fifo); ++ } ++ } ++ } ++ ++ vxge_debug_entryexit(vdev->level_trace, ++ "%s: %s:%d Exiting...", ++ vdev->ndev->name, __func__, __LINE__); ++} ++ ++/* ++ * Vpath configuration ++ */ ++static int __devinit vxge_config_vpaths( ++ struct vxge_hw_device_config *device_config, ++ u64 vpath_mask, struct vxge_config *config_param) ++{ ++ int i, no_of_vpaths = 0, default_no_vpath = 0, temp; ++ u32 txdl_size, txdl_per_memblock; ++ ++ temp = driver_config->vpath_per_dev; ++ if ((driver_config->vpath_per_dev == VXGE_USE_DEFAULT)) { ++ ++ ++ { ++ ++ ++ /* No more CPU. Return vpath number as zero.*/ ++ if (driver_config->g_no_cpus == -1) ++ return 0; ++ ++ if (!driver_config->g_no_cpus) ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 67)) ++ { ++ int no_online_cpus = 0; ++ for (i = 0; i < NR_CPUS; i++) { ++ if (cpu_online_map & (1<g_no_cpus = no_online_cpus; ++ } ++#else ++ driver_config->g_no_cpus = num_online_cpus(); ++#endif ++ ++ driver_config->vpath_per_dev = driver_config->g_no_cpus >> 1; ++ if (!driver_config->vpath_per_dev) ++ driver_config->vpath_per_dev = 1; ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) ++ if (!vxge_bVALn(vpath_mask, i, 1)) ++ continue; ++ else ++ default_no_vpath++; ++ if (default_no_vpath < driver_config->vpath_per_dev) ++ driver_config->vpath_per_dev = default_no_vpath; ++ ++ /* If both tx_steering and Rx_steering are ++ disabled, enable only one Vpath */ ++ if ((!config_param->tx_steering_type && ++ (config_param->rx_steering_type == NO_STEERING) ++ ++ )) { ++ driver_config->vpath_per_dev = 1; ++ vxge_debug_ll_config(VXGE_TRACE, NULL, ++ "%s: Configuring single vpath,\ ++ as transmit and receive \ ++ steering is disabled", ++ VXGE_DRIVER_NAME); ++ } ++ ++ driver_config->g_no_cpus = driver_config->g_no_cpus - ++ (driver_config->vpath_per_dev * 2); ++ if (driver_config->g_no_cpus <= 0) ++ driver_config->g_no_cpus = -1; ++ ++ /* Reset the cpu count for next device */ ++ if (max_config_dev != VXGE_MAX_CONFIG_DEV) ++ driver_config->g_no_cpus = 0; ++ ++ ++ ++ } ++ } ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ device_config->vp_config[i].tx_bw_limit = tx_bw_limit; ++ device_config->vp_config[i].rx_bw_limit = rx_bw_limit; ++ } ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ device_config->vp_config[i].vp_id = i; ++ device_config->vp_config[i].mtu = VXGE_HW_DEFAULT_MTU; ++ if (no_of_vpaths < driver_config->vpath_per_dev) { ++ if (!vxge_bVALn(vpath_mask, i, 1)) { ++ vxge_debug_ll_config(VXGE_TRACE, ++ "%s: vpath: %d is not available", ++ VXGE_DRIVER_NAME, i); ++ continue; ++ } else { ++ vxge_debug_ll_config(VXGE_TRACE, ++ "%s: vpath: %d available", ++ VXGE_DRIVER_NAME, i); ++ no_of_vpaths++; ++ } ++ } else { ++ vxge_debug_ll_config(VXGE_TRACE, ++ "%s: vpath: %d is not configured, " ++ "max_config_vpath exceeded", ++ VXGE_DRIVER_NAME, i); ++ break; ++ } ++ ++ /* Configure Tx fifo's */ ++ device_config->vp_config[i].fifo.enable = ++ VXGE_HW_FIFO_ENABLE; ++ device_config->vp_config[i].fifo.max_frags = ++ MAX_SKB_FRAGS; ++ device_config->vp_config[i].fifo.memblock_size = ++ VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE; ++ ++ txdl_size = MAX_SKB_FRAGS * sizeof(struct vxge_hw_fifo_txd); ++ txdl_per_memblock = VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE / txdl_size; ++ ++ device_config->vp_config[i].fifo.fifo_blocks = ++ ((VXGE_DEF_FIFO_LENGTH - 1) / txdl_per_memblock) + 1; ++ ++ device_config->vp_config[i].fifo.intr = ++ VXGE_HW_FIFO_QUEUE_INTR_DISABLE; ++ ++ /* Configure tti properties */ ++ device_config->vp_config[i].tti.intr_enable = ++ VXGE_HW_TIM_INTR_ENABLE; ++ ++ device_config->vp_config[i].tti.btimer_val = ++ (VXGE_TTI_BTIMER_VAL * 1000) / 272; ++ ++ device_config->vp_config[i].tti.timer_ac_en = ++ VXGE_HW_TIM_TIMER_AC_ENABLE; ++ ++ ++ device_config->vp_config[i].tti.timer_ci_en = ++ VXGE_HW_TIM_TIMER_CI_DISABLE; ++ ++ /* For Inta (with or without napi), ++ Set CI ON for only one vpath. ++ (Have only one free running timer) ++ */ ++ if (config_param->intr_type == INTA) { ++ if (i == 0) ++ device_config->vp_config[i].tti.timer_ci_en = ++ VXGE_HW_TIM_TIMER_CI_ENABLE; ++ } ++ ++ device_config->vp_config[i].tti.timer_ri_en = ++ VXGE_HW_TIM_TIMER_RI_DISABLE; ++ ++ device_config->vp_config[i].tti.util_sel = ++ VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL; ++ ++ device_config->vp_config[i].tti.ltimer_val = ++ (VXGE_TTI_LTIMER_VAL * 1000) / 272; ++ ++ device_config->vp_config[i].tti.rtimer_val = ++ (VXGE_TTI_RTIMER_VAL * 1000) / 272; ++ ++ device_config->vp_config[i].tti.urange_a = TTI_TX_URANGE_A; ++ device_config->vp_config[i].tti.urange_b = TTI_TX_URANGE_B; ++ device_config->vp_config[i].tti.urange_c = TTI_TX_URANGE_C; ++ device_config->vp_config[i].tti.uec_a = TTI_TX_UFC_A; ++ device_config->vp_config[i].tti.uec_b = TTI_TX_UFC_B; ++ device_config->vp_config[i].tti.uec_c = TTI_TX_UFC_C; ++ device_config->vp_config[i].tti.uec_d = TTI_TX_UFC_D; ++ ++ /* Configure Rx rings */ ++ device_config->vp_config[i].ring.enable = ++ VXGE_HW_RING_ENABLE; ++ ++ device_config->vp_config[i].ring.ring_blocks = ++ VXGE_HW_DEF_RING_BLOCKS; ++ device_config->vp_config[i].ring.buffer_mode = ++ VXGE_HW_RING_RXD_BUFFER_MODE_1; ++ ++ if ((device_config->lro_enable) && ++ (device_config->lro_enable != VXGE_HW_GRO_ENABLE)) { ++ device_config->vp_config[i].ring.sw_lro_sessions = ++ VXGE_HW_SW_LRO_DEFAULT_SESSIONS; ++ device_config->vp_config[i].ring.sw_lro_sg_size = ++ VXGE_HW_SW_LRO_MAX_SG_SIZE; ++ device_config->vp_config[i].ring.sw_lro_frm_len = ++ VXGE_HW_SW_LRO_MAX_FRM_LEN; ++ } ++ ++ device_config->vp_config[i].ring.rxd_qword_limit = ++ VXGE_HW_DEF_RING_RXD_QWORD_LIMIT; ++ device_config->vp_config[i].ring.doorbell_mode = ++ config_param->doorbell_mode; ++ ++ device_config->vp_config[i].ring.scatter_mode = ++ VXGE_HW_RING_SCATTER_MODE_A; ++ ++ /* Configure rti properties */ ++ device_config->vp_config[i].rti.intr_enable = ++ VXGE_HW_TIM_INTR_ENABLE; ++ ++ device_config->vp_config[i].rti.btimer_val = ++ (VXGE_RTI_BTIMER_VAL * 1000)/272; ++ ++ device_config->vp_config[i].rti.timer_ac_en = ++ VXGE_HW_TIM_TIMER_AC_ENABLE; ++ ++ device_config->vp_config[i].rti.timer_ci_en = ++ VXGE_HW_TIM_TIMER_CI_DISABLE; ++ ++ device_config->vp_config[i].rti.timer_ri_en = ++ VXGE_HW_TIM_TIMER_RI_DISABLE; ++ ++ device_config->vp_config[i].rti.util_sel = ++ VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL; ++ ++ device_config->vp_config[i].rti.urange_a = ++ RTI_RX_URANGE_A; ++ device_config->vp_config[i].rti.urange_b = ++ RTI_RX_URANGE_B; ++ device_config->vp_config[i].rti.urange_c = ++ RTI_RX_URANGE_C; ++ device_config->vp_config[i].rti.uec_a = RTI_RX_UFC_A; ++ device_config->vp_config[i].rti.uec_b = RTI_RX_UFC_B; ++ device_config->vp_config[i].rti.uec_c = RTI_RX_UFC_C; ++ device_config->vp_config[i].rti.uec_d = RTI_RX_UFC_D; ++ ++ device_config->vp_config[i].rti.rtimer_val = ++ (VXGE_RTI_RTIMER_VAL * 1000) / 272; ++ ++ device_config->vp_config[i].rti.ltimer_val = ++ (VXGE_RTI_LTIMER_VAL * 1000) / 272; ++ ++ device_config->vp_config[i].rpa_strip_vlan_tag = ++ vlan_tag_strip; ++ } ++ ++ driver_config->vpath_per_dev = temp; ++ return no_of_vpaths; ++} ++ ++/* initialize device configuratrions */ ++static void __devinit vxge_device_config_init( ++ struct vxge_hw_device_config *device_config, ++ int *intr_type) ++{ ++ device_config->stats_read_method = stats_read_method; ++ ++ if (max_mac_vpath > VXGE_MAX_MAC_ADDR_COUNT) ++ max_mac_vpath = VXGE_MAX_MAC_ADDR_COUNT; ++ ++#ifndef CONFIG_PCI_MSI ++ if (*intr_type == MSI_X) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: This Kernel does not support " ++ "MSI-X. Defaulting to INTA", VXGE_DRIVER_NAME); ++ *intr_type = INTA; ++ } ++#endif ++ ++ /* Configure whether MSI-X or IRQL. */ ++ switch (*intr_type) { ++ case INTA: ++ device_config->intr_mode = VXGE_HW_INTR_MODE_IRQLINE; ++ break; ++ ++ case MSI_X: ++ device_config->intr_mode = VXGE_HW_INTR_MODE_MSIX; ++ break; ++ } ++ ++ device_config->lro_enable = lro; ++ /* Timer period between device poll */ ++ device_config->device_poll_millis = VXGE_TIMER_DELAY; ++ ++ /* Configure Vpaths */ ++ device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_MULTI_IT; ++ ++ vxge_debug_ll_config(VXGE_TRACE, "%s : Device Config Params ", ++ __func__); ++ vxge_debug_ll_config(VXGE_TRACE, "intr_mode : %d", ++ device_config->intr_mode); ++ vxge_debug_ll_config(VXGE_TRACE, "device_poll_millis : %d", ++ device_config->device_poll_millis); ++ vxge_debug_ll_config(VXGE_TRACE, "rth_en : %d", ++ device_config->rth_en); ++ vxge_debug_ll_config(VXGE_TRACE, "rth_it_type : %d", ++ device_config->rth_it_type); ++} ++ ++static void __devinit vxge_print_parm(struct vxgedev *vdev, u64 vpath_mask) ++{ ++ int i; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ vxge_debug_init(VXGE_TRACE, ++ "%s: %d Vpath(s) opened", ++ vdev->ndev->name, vdev->no_of_vpath); ++ ++ switch (vdev->config.intr_type) { ++ case INTA: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Interrupt type INTA", vdev->ndev->name); ++ break; ++ ++ case MSI_X: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Interrupt type MSI-X", vdev->ndev->name); ++ break; ++ ++ ++ } ++ ++ ++ switch (vdev->config.rx_steering_type) { ++ case RTH_TCP_UDP_STEERING: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: RTH steering enabled for TCP_IPV4", ++ vdev->ndev->name); ++ break; ++ case RTH_IPV4_STEERING: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: RTH steering enabled for IPV4", ++ vdev->ndev->name); ++ break; ++ case RTH_IPV6_EX_STEERING: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: RTH steering enabled for IPV6 with extention header", ++ vdev->ndev->name); ++ break; ++ default: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: RTH steering disabled", vdev->ndev->name); ++ } ++ ++ switch (vdev->config.tx_steering_type) { ++ case NO_STEERING: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Tx steering disabled", vdev->ndev->name); ++ break; ++ case TX_PRIORITY_STEERING: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Unsupported tx steering option", ++ vdev->ndev->name); ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Tx steering disabled", vdev->ndev->name); ++ vdev->config.tx_steering_type = 0; ++ break; ++ case TX_VLAN_STEERING: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Unsupported tx steering option", ++ vdev->ndev->name); ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Tx steering disabled", vdev->ndev->name); ++ vdev->config.tx_steering_type = 0; ++ break; ++ case TX_MULTIQ_STEERING: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Tx multiqueue steering enabled", ++ vdev->ndev->name); ++ break; ++ case TX_PORT_STEERING: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Tx port steering enabled", ++ vdev->ndev->name); ++ break; ++ default: ++ vxge_debug_init(VXGE_ERR, ++ "%s: Unsupported tx steering type", ++ vdev->ndev->name); ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Tx steering disabled", vdev->ndev->name); ++ vdev->config.tx_steering_type = 0; ++ } ++ ++ if (vdev->config.lro_enable == VXGE_HW_GRO_ENABLE) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: Generic receive offload enabled", ++ vdev->ndev->name); ++ } else if (vdev->config.lro_enable) { ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Large receive offload enabled", ++ vdev->ndev->name); ++ } else ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Large receive offload disabled", ++ vdev->ndev->name); ++ ++ ++ ++ if (vdev->config.napi_enable) { ++ vxge_debug_init(VXGE_TRACE, ++ "%s: NAPI enabled", vdev->ndev->name); ++ } else ++ vxge_debug_init(VXGE_TRACE, ++ "%s: NAPI disabled", vdev->ndev->name); ++ ++ ++ ++ ++ if (vdev->config.promisc_en) ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Promiscuous mode enabled on privileged function", ++ vdev->ndev->name); ++ ++ if (vdev->config.promisc_all_en) ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Promiscuous mode enabled on all functions", ++ vdev->ndev->name); ++ ++ if (vdev->config.doorbell_mode == VXGE_HW_DOORBELL_MODE_ENABLE) ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Rx doorbell mode enabled", vdev->ndev->name); ++ ++ if (vdev->exec_mode == VXGE_EXEC_MODE_ENABLE) ++ vxge_debug_init (VXGE_ERR, "%s: Exec debug mode enabled", ++ vdev->ndev->name); ++ ++ if (!vdev->titan1 ||(vdev->config.doorbell_mode == ++ VXGE_HW_DOORBELL_MODE_DISABLE)) ++ if (intr_adapt) ++ vxge_debug_init (VXGE_ERR, "%s: Adaptive interrupt " ++ "coalescing enabled", vdev->ndev->name); ++ ++ status = __vxge_hw_device_is_privilaged(vdev->devh->host_type, ++ vdev->devh->func_id); ++ if (status == VXGE_HW_OK) { ++ if (rx_bw_limit != VXGE_HW_VPATH_RX_BANDWIDTH_LIMIT_DEFAULT) { ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Receive bandwidth limit set to %d Gbps", ++ vdev->ndev->name, rx_bw_limit); ++ } ++ } ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ if (!vxge_bVALn(vpath_mask, i, 1)) ++ continue; ++ vxge_debug_ll_config(VXGE_TRACE, ++ "%s: MTU size - %d", vdev->ndev->name, ++ ((struct __vxge_hw_device *)(vdev->devh))-> ++ config.vp_config[i].mtu); ++ vxge_debug_init(VXGE_TRACE, ++ "%s: VLAN tag stripping %s", vdev->ndev->name, ++ ((struct __vxge_hw_device *)(vdev->devh))-> ++ config.vp_config[i].rpa_strip_vlan_tag ++ ? "enabled" : "disabled"); ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Ring blocks : %d", vdev->ndev->name, ++ ((struct __vxge_hw_device *)(vdev->devh))-> ++ config.vp_config[i].ring.ring_blocks); ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Fifo blocks : %d", vdev->ndev->name, ++ ((struct __vxge_hw_device *)(vdev->devh))-> ++ config.vp_config[i].fifo.fifo_blocks); ++ vxge_debug_ll_config(VXGE_TRACE, ++ "%s: Max frags : %d", vdev->ndev->name, ++ ((struct __vxge_hw_device *)(vdev->devh))-> ++ config.vp_config[i].fifo.max_frags); ++ break; ++ } ++} ++ ++#ifdef CONFIG_PM ++/** ++ * vxge_pm_suspend - vxge power management suspend entry point ++ * ++ */ ++static int vxge_pm_suspend(struct pci_dev *pdev, pm_message_t state) ++{ ++ int ret = 0; ++ struct __vxge_hw_device *hldev = ++ (struct __vxge_hw_device *) pci_get_drvdata(pdev); ++ struct net_device *netdev = hldev->ndev; ++ ++ pci_save_state(pdev); ++ if (netif_running(netdev)) { ++ do_vxge_close(netdev, 1); ++ netif_device_detach(netdev); ++ } ++ ret = pci_set_power_state(pdev, pci_choose_state(pdev, state)); ++ if (ret) ++ vxge_debug_init(VXGE_ERR, ++ "%s: Error %d setting power state\n", ++ netdev->name, ret); ++ pci_disable_device(pdev); ++ return ret; ++} ++/** ++ * vxge_pm_resume - vxge power management resume entry point ++ * ++ */ ++static int vxge_pm_resume(struct pci_dev *pdev) ++{ ++ int ret = 0; ++ struct __vxge_hw_device *hldev = ++ (struct __vxge_hw_device *) pci_get_drvdata(pdev); ++ struct net_device *netdev = hldev->ndev; ++ ++ ret = pci_set_power_state(pdev, PCI_D0); ++ if (ret) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: Error %d setting power state\n", ++ netdev->name, ret); ++ return ret; ++ } ++ ret = pci_enable_device(pdev); ++ pci_set_master(pdev); ++ pci_restore_state(pdev); ++ if (netif_running(netdev)) { ++ ret = vxge_open(netdev); ++ if (ret) ++ vxge_debug_init(VXGE_ERR, ++ "%s: H/W Init failed with err : %d\n", ++ netdev->name, ret); ++ } ++ netif_device_attach(netdev); ++ ++ return ret; ++} ++ ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) ++/** ++ * vxge_io_error_detected - called when PCI error is detected ++ * @pdev: Pointer to PCI device ++ * @state: The current pci connection state ++ * ++ * This function is called after a PCI bus error affecting ++ * this device has been detected. ++ */ ++static pci_ers_result_t vxge_io_error_detected(struct pci_dev *pdev, ++ pci_channel_state_t state) ++{ ++ struct __vxge_hw_device *hldev = ++ (struct __vxge_hw_device *) pci_get_drvdata(pdev); ++ struct net_device *netdev = hldev->ndev; ++ ++ netif_device_detach(netdev); ++ ++ if (netif_running(netdev)) { ++ /* Bring down the card, while avoiding PCI I/O */ ++ do_vxge_close(netdev, 0); ++ } ++ ++ pci_disable_device(pdev); ++ ++ return PCI_ERS_RESULT_NEED_RESET; ++} ++ ++/** ++ * vxge_io_slot_reset - called after the pci bus has been reset. ++ * @pdev: Pointer to PCI device ++ * ++ * Restart the card from scratch, as if from a cold-boot. ++ * At this point, the card has exprienced a hard reset, ++ * followed by fixups by BIOS, and has its config space ++ * set up identically to what it was at cold boot. ++ */ ++static pci_ers_result_t vxge_io_slot_reset(struct pci_dev *pdev) ++{ ++ struct __vxge_hw_device *hldev = ++ (struct __vxge_hw_device *) pci_get_drvdata(pdev); ++ struct net_device *netdev = hldev->ndev; ++ ++ struct vxgedev *vdev = netdev_priv(netdev); ++ ++ if (pci_enable_device(pdev)) { ++ printk(KERN_ERR "%s: " ++ "Cannot re-enable device after reset\n", ++ VXGE_DRIVER_NAME); ++ return PCI_ERS_RESULT_DISCONNECT; ++ } ++ ++ pci_set_master(pdev); ++ vxge_reset(vdev); ++ ++ return PCI_ERS_RESULT_RECOVERED; ++} ++ ++/** ++ * vxge_io_resume - called when traffic can start flowing again. ++ * @pdev: Pointer to PCI device ++ * ++ * This callback is called when the error recovery driver tells ++ * us that its OK to resume normal operation. ++ */ ++static void vxge_io_resume(struct pci_dev *pdev) ++{ ++ struct __vxge_hw_device *hldev = ++ (struct __vxge_hw_device *) pci_get_drvdata(pdev); ++ struct net_device *netdev = hldev->ndev; ++ ++ if (netif_running(netdev)) { ++ if (vxge_open(netdev)) { ++ printk(KERN_ERR "%s: " ++ "Can't bring device back up after reset\n", ++ VXGE_DRIVER_NAME); ++ return; ++ } ++ } ++ ++ netif_device_attach(netdev); ++} ++#endif ++ ++ ++ ++/** ++ * vxge_probe ++ * @pdev : structure containing the PCI related information of the device. ++ * @pre: List of PCI devices supported by the driver listed in vxge_id_table. ++ * Description: ++ * This function is called when a new PCI device gets detected and initializes ++ * it. ++ * Return value: ++ * returns 0 on success and negative on failure. ++ * ++ */ ++static int __devinit ++vxge_probe(struct pci_dev *pdev, const struct pci_device_id *pre) ++{ ++ struct __vxge_hw_device *hldev; ++ enum vxge_hw_status status; ++ int ret; ++ int high_dma = 0; ++ u64 vpath_mask = 0; ++ struct vxgedev *vdev; ++ struct vxge_config ll_config; ++ struct vxge_hw_device_config *device_config = NULL; ++ struct vxge_hw_device_attr attr; ++ int i, j, no_of_vpath = 0, max_vpath_supported = 0; ++ u8 *macaddr, revision, titan1; ++ struct vxge_mac_addrs *entry; ++ static int bus = -1, device = -1; ++ u8 new_device = 0; ++ u32 host_type; ++ vxge_debug_entryexit(VXGE_TRACE, "%s:%d", __func__, __LINE__); ++ attr.pdev = pdev; ++ ++ if (bus != pdev->bus->number) ++ new_device = 1; ++ if (device != PCI_SLOT(pdev->devfn)) ++ new_device = 1; ++ ++ bus = pdev->bus->number; ++ device = PCI_SLOT(pdev->devfn); ++ ++ if (new_device) { ++ if (driver_config->config_dev_cnt && ++ (driver_config->config_dev_cnt != ++ driver_config->total_dev_cnt)) ++ vxge_debug_init(VXGE_ERR, ++ "%s: Configured %d of %d devices", ++ VXGE_DRIVER_NAME, ++ driver_config->config_dev_cnt, ++ driver_config->total_dev_cnt); ++ driver_config->config_dev_cnt = 0; ++ driver_config->total_dev_cnt = 0; ++ driver_config->g_no_cpus = 0; ++ } ++ ++ driver_config->vpath_per_dev = max_config_vpath; ++ ++ driver_config->total_dev_cnt++; ++ if (++driver_config->config_dev_cnt > max_config_dev) { ++ ++ ret = 0; ++ ++ goto _exit0; ++ } ++ ++ device_config = kzalloc(sizeof(struct vxge_hw_device_config), ++ GFP_KERNEL); ++ if (!device_config) { ++ ret = -ENOMEM; ++ vxge_debug_init(VXGE_ERR, ++ "device_config : malloc failed %s %d", ++ __FILE__, __LINE__); ++ goto _exit0; ++ } ++ ++ memset(&ll_config, 0, sizeof(struct vxge_config)); ++ ll_config.tx_steering_type = tx_steering_type; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 23)) ++ if (ll_config.tx_steering_type == TX_MULTIQ_STEERING) { ++ vxge_debug_init(VXGE_ERR, ++ "%s : MultiQ is not supported on this kernel", ++ __func__); ++ ll_config.tx_steering_type = TX_PORT_STEERING; ++ } ++#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 26)) ++#ifndef CONFIG_NETDEVICES_MULTIQUEUE ++ if (ll_config.tx_steering_type == TX_MULTIQ_STEERING) { ++ vxge_debug_init(VXGE_ERR, ++ "%s : MultiQ is not supported on this kernel", ++ __func__); ++ ll_config.tx_steering_type = TX_PORT_STEERING; ++ } ++#endif ++#endif ++ ++ if (lro == VXGE_HW_GRO_ENABLE) { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)) ++ lro = VXGE_HW_LRO_DONT_AGGR_FWD_PKTS; ++#endif ++ } ++ ll_config.intr_type = intr_type; ++ ll_config.doorbell_mode = doorbell_mode; ++ ++ ++ ++ pci_read_config_byte(pdev, PCI_REVISION_ID, &revision); ++ ++ titan1 = is_titan1(pdev->device, revision); ++ if (doorbell_mode == VXGE_HW_DOORBELL_MODE_DEFAULT) ++ ll_config.doorbell_mode = VXGE_HW_DOORBELL_MODE_ENABLE; ++ ++ ll_config.rx_steering_type = rx_steering_type; ++ ++ ll_config.promisc_en = promisc_en; ++ ll_config.promisc_all_en = promisc_all_en; ++ ++ /* get the default configuration parameters */ ++ vxge_hw_device_config_default_get(device_config); ++ ++ /* initialize configuration parameters */ ++ vxge_device_config_init(device_config, &ll_config.intr_type); ++ ++ ret = pci_enable_device(pdev); ++ if (ret) { ++ vxge_debug_init(VXGE_ERR, ++ "%s : can not enable PCI device", __func__); ++ goto _exit0; ++ } ++ ++ if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) { ++ vxge_debug_ll_config(VXGE_TRACE, ++ "%s : using 64bit DMA", __func__); ++ ++ high_dma = 1; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)) ++ if (pci_set_consistent_dma_mask(pdev, ++ 0xffffffffffffffffULL)) { ++ vxge_debug_init(VXGE_ERR, ++ "%s : unable to obtain 64bit DMA for " ++ "consistent allocations", __func__); ++ ret = -ENOMEM; ++ goto _exit1; ++ } ++#endif ++ } else if (!pci_set_dma_mask(pdev, 0xffffffffUL)) { ++ vxge_debug_ll_config(VXGE_TRACE, ++ "%s : using 32bit DMA", __func__); ++ } else { ++ ret = -ENOMEM; ++ goto _exit1; ++ } ++ ++ if (pci_request_regions(pdev, VXGE_DRIVER_NAME)) { ++ vxge_debug_init(VXGE_ERR, ++ "%s : request regions failed", __func__); ++ ret = -ENODEV; ++ goto _exit1; ++ } ++ ++ pci_set_master(pdev); ++ ++ attr.bar0 = vxge_pci_ioremap_bar(pdev, 0); ++ if (!attr.bar0) { ++ vxge_debug_init(VXGE_ERR, ++ "%s : cannot remap io memory bar0", __func__); ++ ret = -ENODEV; ++ goto _exit2; ++ } ++ vxge_debug_ll_config(VXGE_TRACE, ++ "pci ioremap bar0: %p:0x%llx", ++ attr.bar0, ++ (unsigned long long)pci_resource_start(pdev, 0)); ++ ++ status = vxge_hw_device_hw_info_get(attr.bar0, ++ &ll_config.device_hw_info); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: Reading of hardware info failed." ++ "Please try upgrading the firmware.", VXGE_DRIVER_NAME); ++ ret = -EINVAL; ++ goto _exit3; ++ } ++ ++ if (ll_config.device_hw_info.fw_version.major != 1) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: Incorrect firmware version." ++ "Please upgrade the firmware to version 1.x.x", VXGE_DRIVER_NAME); ++ ret = -EINVAL; ++ goto _exit3; ++ } ++ ++ /* from major >=1 fcs disable is enabled by default in firmware */ ++ ++ vpath_mask = ll_config.device_hw_info.vpath_mask; ++ if (vpath_mask == 0) { ++ vxge_debug_ll_config(VXGE_TRACE, ++ "%s: No vpaths available in device", VXGE_DRIVER_NAME); ++ ret = -EINVAL; ++ goto _exit3; ++ } ++ ++ vxge_debug_ll_config(VXGE_TRACE, ++ "%s:%d Vpath mask = %llx", __func__, __LINE__, ++ (unsigned long long)vpath_mask); ++ ++ /* Check how many vpaths are available */ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ if (!((vpath_mask) & vxge_mBIT(i))) ++ continue; ++ max_vpath_supported++; ++ } ++ ++ if ((driver_config->vpath_per_dev != VXGE_USE_DEFAULT) && ++ (max_vpath_supported < driver_config->vpath_per_dev)) { ++ driver_config->vpath_per_dev = max_vpath_supported; ++ vxge_debug_ll_config(VXGE_ERR, NULL, ++ "Restricting no of vpath to %d \n", ++ driver_config->vpath_per_dev); ++ } ++ host_type = ll_config.device_hw_info.host_type; ++#ifdef CONFIG_PCI_IOV ++ /* Enable SRIOV mode, if firmware support and if it is a PF */ ++ if (is_sriov(ll_config.device_hw_info.function_mode) && ++ (max_config_dev > 1)&& ++ (VXGE_HW_OK == __vxge_hw_device_is_privilaged(host_type, ++ ll_config.device_hw_info.func_id))) { ++ ret = pci_enable_sriov(pdev, max_config_dev - 1); ++ if (ret) ++ vxge_debug_ll_config(VXGE_ERR, ++ "Failed in enabling SRIOV mode \n"); ++ } ++#endif ++ /* ++ * Configure vpaths and get driver configured number of vpaths ++ * which is less than or equal to the maximum vpaths per function. ++ */ ++ no_of_vpath = vxge_config_vpaths(device_config, vpath_mask, &ll_config); ++ if (!no_of_vpath) { ++ vxge_debug_ll_config(VXGE_ERR, ++ "%s: No more vpaths to configure", VXGE_DRIVER_NAME); ++ ++ ret = 0; ++ ++ goto _exit3; ++ } ++ ++ if (no_of_vpath == 1) { ++ vxge_debug_ll_config(VXGE_TRACE, ++ "%s: Disable tx and rx steering, " ++ "as single vpath is configured", VXGE_DRIVER_NAME); ++ ll_config.tx_steering_type = NO_STEERING; ++ ll_config.rx_steering_type = NO_STEERING; ++ } ++ ++ ll_config.napi_enable = napi; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) ++ /* NAPI doesn't work well with MSI(X) & more than 1 VPATH */ ++ if (ll_config.intr_type != INTA) ++ if (ll_config.napi_enable) ++ if (no_of_vpath > 1) ++ ll_config.napi_enable = 0; ++#endif ++ ++ /* GRO and NAPI are tied together. If GRO is enabled and NAPI is ++ * disabled switch to SW-LRO */ ++ if (lro && (lro == VXGE_HW_GRO_ENABLE) && (!ll_config.napi_enable)) ++ lro = VXGE_HW_LRO_DONT_AGGR_FWD_PKTS; ++ ++ if ((no_of_vpath == 1) && ll_config.napi_enable && lro && ++ (lro != VXGE_HW_GRO_ENABLE)) ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) ++ device_config->vp_config[i].aggr_ack = ++ VXGE_HW_VPATH_AGGR_ACK_ENABLE; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) ++ else if ((ll_config.intr_type == MSI_X) && ll_config.napi_enable && ++ lro && (lro != VXGE_HW_GRO_ENABLE)) ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) ++ device_config->vp_config[i].aggr_ack = ++ VXGE_HW_VPATH_AGGR_ACK_ENABLE; ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) ++ ll_config.napi_weight = OLD_NAPI_WEIGHT; ++#else ++ ll_config.napi_weight = NEW_NAPI_WEIGHT; ++#endif ++ /* Setting driver callbacks */ ++ attr.uld_callbacks.link_up = vxge_callback_link_up; ++ attr.uld_callbacks.link_down = vxge_callback_link_down; ++ attr.uld_callbacks.crit_err = vxge_callback_crit_err; ++ ++ status = vxge_hw_device_initialize(&hldev, &attr, ++ device_config, titan1); ++ if (status != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "Failed to initialize device (%d)", status); ++ ret = -EINVAL; ++ goto _exit3; ++ } ++ ++ /* if FCS stripping is not disabled in MAC fail driver load */ ++ if (vxge_hw_vpath_strip_fcs_check(hldev, vpath_mask) != VXGE_HW_OK) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: FCS stripping is not disabled in MAC" ++ " failing driver load", VXGE_DRIVER_NAME); ++ ret = -EINVAL; ++ goto _exit4; ++ } ++ vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_LL); ++ ++ /* set private device info */ ++ pci_set_drvdata(pdev, hldev); ++ ++ ++ ++ ll_config.lro_enable = lro; ++ if (titan1) ++ ll_config.lro_max_bytes = VXGE_LRO_MAX_BYTES; ++ else ++ ll_config.lro_max_bytes = VXGE_T1A_LRO_MAX_BYTES; ++ ++ ll_config.fifo_indicate_max_pkts = VXGE_FIFO_INDICATE_MAX_PKTS; ++ ll_config.rec_all_vid = rec_all_vid; ++ ll_config.rth_algorithm = RTH_ALG_JENKINS; ++ ++ switch (ll_config.rx_steering_type) { ++ case RTH_TCP_UDP_STEERING: ++ ll_config.rth_hash_type_tcpipv4 = ++ VXGE_HW_RING_HASH_TYPE_TCP_IPV4; ++ break; ++ case RTH_IPV4_STEERING: ++ ll_config.rth_hash_type_ipv4 = VXGE_HW_RING_HASH_TYPE_IPV4; ++ break; ++ case RTH_IPV6_EX_STEERING: ++ ll_config.rth_hash_type_ipv6ex = VXGE_HW_RING_HASH_TYPE_IPV6_EX; ++ break; ++ } ++ ++ ll_config.rth_hash_type_tcpipv6 = VXGE_HW_RING_HASH_TYPE_NONE; ++ ll_config.rth_hash_type_ipv6 = VXGE_HW_RING_HASH_TYPE_NONE; ++ ll_config.rth_hash_type_tcpipv6ex = VXGE_HW_RING_HASH_TYPE_NONE; ++ ++ ll_config.rth_bkt_sz = RTH_BUCKET_SIZE; ++ ll_config.tx_pause_enable = tx_pause_enable; ++ ll_config.rx_pause_enable = rx_pause_enable; ++ ++ if (vxge_device_register(hldev, &ll_config, high_dma, no_of_vpath, ++ &vdev)) { ++ ret = -EINVAL; ++ goto _exit4; ++ } ++ ++ vxge_hw_device_debug_set(hldev, VXGE_TRACE, VXGE_COMPONENT_LL); ++ VXGE_COPY_DEBUG_INFO_TO_LL(vdev, vxge_hw_device_error_level_get(hldev), ++ vxge_hw_device_trace_level_get(hldev)); ++ ++ /* set private HW device info */ ++ hldev->ndev = vdev->ndev; ++ vdev->mtu = VXGE_HW_DEFAULT_MTU; ++ vdev->bar0 = attr.bar0; ++ vdev->no_of_vpath = no_of_vpath; ++ vdev->titan1 = titan1; ++ ++ /* Virtual Path count */ ++ for (i = 0, j = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ if (!vxge_bVALn(vpath_mask, i, 1)) ++ continue; ++ if (j >= vdev->no_of_vpath) ++ break; ++ ++ vdev->vpaths[j].is_configured = 1; ++ vdev->vpaths[j].device_id = i; ++ vdev->vpaths[j].fifo.driver_id = j; ++ vdev->vpaths[j].ring.driver_id = j; ++ vdev->vpaths[j].vdev = vdev; ++ vdev->vpaths[j].max_mac_addr_cnt = max_mac_vpath; ++ memcpy((u8 *)vdev->vpaths[j].macaddr, ++ (u8 *)ll_config.device_hw_info.mac_addrs[i], ++ ETH_ALEN); ++ ++ /* Initialize the mac address list header */ ++ INIT_LIST_HEAD(&vdev->vpaths[j].mac_addr_list); ++ ++ vdev->vpaths[j].mac_addr_cnt = 0; ++ vdev->vpaths[j].mcast_addr_cnt = 0; ++ j++; ++ } ++ vdev->exec_mode = exec_mode; ++ vdev->max_config_port = max_config_port; ++ ++ vdev->vlan_tag_strip = vlan_tag_strip; ++ ++ /* map the hashing selector table to the configured vpaths */ ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ vdev->vpath_selector[i] = vpath_selector[i]; ++ ++ macaddr = (u8 *)vdev->vpaths[0].macaddr; ++ ++ ll_config.device_hw_info.serial_number[VXGE_HW_INFO_LEN - 1] = '\0'; ++ ll_config.device_hw_info.product_desc[VXGE_HW_INFO_LEN - 1] = '\0'; ++ ll_config.device_hw_info.part_number[VXGE_HW_INFO_LEN - 1] = '\0'; ++ ++ vxge_debug_init(VXGE_TRACE, "%s: SERIAL NUMBER: %s", ++ vdev->ndev->name, ll_config.device_hw_info.serial_number); ++ ++ vxge_debug_init(VXGE_TRACE, "%s: PART NUMBER: %s", ++ vdev->ndev->name, ll_config.device_hw_info.part_number); ++ ++ vxge_debug_init(VXGE_TRACE, "%s: Neterion %s Server Adapter", ++ vdev->ndev->name, ll_config.device_hw_info.product_desc); ++ ++ vxge_debug_init(VXGE_TRACE, ++ "%s: MAC ADDR: %02X:%02X:%02X:%02X:%02X:%02X", ++ vdev->ndev->name, macaddr[0], macaddr[1], macaddr[2], ++ macaddr[3], macaddr[4], macaddr[5]); ++ ++ vxge_debug_init(VXGE_TRACE, "%s: Link Width x%d", ++ vdev->ndev->name, vxge_hw_device_link_width_get(hldev)); ++ ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Firmware version : %s Date : %s", vdev->ndev->name, ++ ll_config.device_hw_info.fw_version.version, ++ ll_config.device_hw_info.fw_date.date); ++ ++ if (new_device) { ++ switch (ll_config.device_hw_info.function_mode) { ++ case VXGE_HW_FUNCTION_MODE_SINGLE_FUNCTION: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Single Function Mode Enabled", vdev->ndev->name); ++ break; ++ case VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Multi Function Mode Enabled", vdev->ndev->name); ++ break; ++ case VXGE_HW_FUNCTION_MODE_SRIOV: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Single Root IOV Mode Enabled", vdev->ndev->name); ++ break; ++ case VXGE_HW_FUNCTION_MODE_MRIOV: ++ vxge_debug_init(VXGE_TRACE, ++ "%s: Multi Root IOV Mode Enabled", vdev->ndev->name); ++ break; ++ } ++ ++ } ++ vxge_print_parm(vdev, vpath_mask); ++ ++ /* Store the fw version for ethttool option */ ++ strcpy(vdev->fw_version, ll_config.device_hw_info.fw_version.version); ++ memcpy(vdev->ndev->dev_addr, (u8 *)vdev->vpaths[0].macaddr, ETH_ALEN); ++#ifdef ETHTOOL_GPERMADDR ++ memcpy(vdev->ndev->perm_addr, vdev->ndev->dev_addr, ETH_ALEN); ++#endif ++ /* Copy the station mac address to the list */ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ entry = (struct vxge_mac_addrs *) ++ kzalloc(sizeof(struct vxge_mac_addrs), ++ GFP_KERNEL); ++ if (NULL == entry) { ++ vxge_debug_init(VXGE_ERR, ++ "%s: mac_addr_list : memory allocation failed", ++ vdev->ndev->name); ++ ret = -EPERM; ++ goto _exit5; ++ } ++ macaddr = (u8 *)&entry->macaddr; ++ memcpy(macaddr, vdev->ndev->dev_addr, ETH_ALEN); ++ list_add(&entry->item, &vdev->vpaths[i].mac_addr_list); ++ vdev->vpaths[i].mac_addr_cnt = 1; ++ } ++ ++ spin_lock_init(&vdev->addr_learn_lock); ++ ++ ++ vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_LL); ++ VXGE_COPY_DEBUG_INFO_TO_LL(vdev, vxge_hw_device_error_level_get(hldev), ++ vxge_hw_device_trace_level_get(hldev)); ++ ++ ++ kfree(device_config); ++ ++ /* ++ * INTA is shared in multi-function mode. This is unlike the INTA ++ * implementation in MR mode, where each VH has its own INTA message. ++ * - INTA is masked (disabled) as long as at least one function sets ++ * its TITAN_MASK_ALL_INT.ALARM bit. ++ * - INTA is unmasked (enabled) when all enabled functions have cleared ++ * their own TITAN_MASK_ALL_INT.ALARM bit. ++ * The TITAN_MASK_ALL_INT ALARM & TRAFFIC bits are cleared on power up. ++ * Though this driver leaves the top level interrupts unmasked while ++ * leaving the required module interrupt bits masked on exit, there ++ * could be a rougue driver around that does not follow this procedure ++ * resulting in a failure to generate interrupts. The following code is ++ * present to prevent such a failure. ++ */ ++ ++ if (ll_config.device_hw_info.function_mode == ++ VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION) ++ if (vdev->config.intr_type == INTA) ++ vxge_hw_device_unmask_all(hldev); ++ ++ vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d Exiting...", ++ vdev->ndev->name, __func__, __LINE__); ++ ++ return 0; ++ ++_exit5: ++ for (i = 0; i < vdev->no_of_vpath; i++) ++ vxge_free_mac_add_list(&vdev->vpaths[i]); ++ ++ vxge_device_unregister(hldev); ++_exit4: ++ vxge_hw_device_terminate(hldev); ++_exit3: ++ iounmap(attr.bar0); ++#ifdef CONFIG_PCI_IOV ++ pci_disable_sriov(pdev); ++#endif ++ ++_exit2: ++ pci_release_regions(pdev); ++_exit1: ++ pci_disable_device(pdev); ++_exit0: ++ kfree(device_config); ++ driver_config->config_dev_cnt--; ++ pci_set_drvdata(pdev, NULL); ++ return ret; ++} ++ ++/** ++ * vxge_rem_nic - Free the PCI device ++ * @pdev: structure containing the PCI related information of the device. ++ * Description: This function is called by the Pci subsystem to release a ++ * PCI device and free up all resource held up by the device. ++ */ ++static void __devexit ++vxge_remove(struct pci_dev *pdev) ++{ ++ struct __vxge_hw_device *hldev; ++ struct vxgedev *vdev = NULL; ++ struct net_device *dev; ++ int i = 0; ++#if ((VXGE_DEBUG_INIT & VXGE_DEBUG_MASK) || \ ++ (VXGE_DEBUG_ENTRYEXIT & VXGE_DEBUG_MASK)) ++ u32 level_trace; ++#endif ++ ++ hldev = (struct __vxge_hw_device *) pci_get_drvdata(pdev); ++ ++ if (hldev == NULL) ++ return; ++ dev = hldev->ndev; ++ vdev = netdev_priv(dev); ++ ++#if ((VXGE_DEBUG_INIT & VXGE_DEBUG_MASK) || \ ++ (VXGE_DEBUG_ENTRYEXIT & VXGE_DEBUG_MASK)) ++ level_trace = vdev->level_trace; ++#endif ++ vxge_debug_entryexit(level_trace, ++ "%s:%d", __func__, __LINE__); ++ ++ vxge_debug_init(level_trace, ++ "%s : removing PCI device...", __func__); ++ vxge_device_unregister(hldev); ++ ++ for (i = 0; i < vdev->no_of_vpath; i++) { ++ vxge_free_mac_add_list(&vdev->vpaths[i]); ++ vdev->vpaths[i].mcast_addr_cnt = 0; ++ vdev->vpaths[i].mac_addr_cnt = 0; ++ } ++ ++ kfree(vdev->vpaths); ++ ++ iounmap(vdev->bar0); ++#ifdef CONFIG_PCI_IOV ++ pci_disable_sriov(pdev); ++#endif ++ ++ ++ ++ /* we are safe to free it now */ ++ free_netdev(dev); ++ ++ vxge_debug_init(level_trace, ++ "%s:%d Device unregistered", __func__, __LINE__); ++ ++ vxge_hw_device_terminate(hldev); ++ ++ pci_disable_device(pdev); ++ pci_release_regions(pdev); ++ pci_set_drvdata(pdev, NULL); ++ vxge_debug_entryexit(level_trace, ++ "%s:%d Exiting...", __func__, __LINE__); ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) ++static struct pci_error_handlers vxge_err_handler = { ++ .error_detected = vxge_io_error_detected, ++ .slot_reset = vxge_io_slot_reset, ++ .resume = vxge_io_resume, ++}; ++#endif ++ ++static struct pci_driver vxge_driver = { ++ .name = VXGE_DRIVER_NAME, ++ .id_table = vxge_id_table, ++ .probe = vxge_probe, ++ .remove = __devexit_p(vxge_remove), ++#ifdef CONFIG_PM ++ .suspend = vxge_pm_suspend, ++ .resume = vxge_pm_resume, ++#endif ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) ++ .err_handler = &vxge_err_handler, ++#endif ++}; ++ ++static int __init ++vxge_starter(void) ++{ ++ int ret = 0; ++ char version[32]; ++ snprintf(version, 32, "%s", DRV_VERSION); ++ ++ printk(KERN_CRIT "%s: Copyright(c) 2002-2009 Neterion Inc\n", ++ VXGE_DRIVER_NAME); ++ printk(KERN_CRIT "%s: Driver version: %s\n", ++ VXGE_DRIVER_NAME, version); ++ ++ ++ ++ driver_config = kzalloc(sizeof(struct vxge_drv_config), GFP_KERNEL); ++ if (!driver_config) ++ return -ENOMEM; ++ ++ ret = pci_register_driver(&vxge_driver); ++ ++ if (driver_config->config_dev_cnt && ++ (driver_config->config_dev_cnt != driver_config->total_dev_cnt)) ++ vxge_debug_init(VXGE_ERR, ++ "%s: Configured %d of %d devices", ++ VXGE_DRIVER_NAME, driver_config->config_dev_cnt, ++ driver_config->total_dev_cnt); ++ ++ if (ret) ++ kfree(driver_config); ++ ++ return ret; ++} ++ ++static void __exit ++vxge_closer(void) ++{ ++ pci_unregister_driver(&vxge_driver); ++ kfree(driver_config); ++} ++module_init(vxge_starter); ++module_exit(vxge_closer); +diff -r 158b6e53275e drivers/net/vxge/vxge-main.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/vxge/vxge-main.h Wed Aug 05 11:58:00 2009 +0100 +@@ -0,0 +1,781 @@ ++/****************************************************************************** ++ * vxge-main.h: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O ++ * Virtualized Server Adapter. ++ * Copyright(c) 2002-2009 Neterion Inc. ++ ******************************************************************************/ ++#ifndef VXGE_MAIN_H ++#define VXGE_MAIN_H ++#include "vxge-traffic.h" ++#include "vxge-config.h" ++#include "vxge-version.h" ++#include ++ ++#define VXGE_DRIVER_NAME "vxge" ++#define VXGE_DRIVER_VENDOR "Neterion, Inc" ++#define VXGE_DRIVER_VERSION_MAJOR 0 ++ ++#define DRV_VERSION VXGE_VERSION_MAJOR"."VXGE_VERSION_MINOR"."\ ++ VXGE_VERSION_FIX"."VXGE_VERSION_BUILD"-"\ ++ VXGE_VERSION_FOR ++ ++#ifndef PCI_VENDOR_ID_S2IO ++#define PCI_VENDOR_ID_S2IO 0x17D5 ++#endif ++ ++#ifndef PCI_DEVICE_ID_TITAN_WIN ++#define PCI_DEVICE_ID_TITAN_WIN 0x5733 ++#endif ++ ++#ifndef PCI_DEVICE_ID_TITAN_UNI ++#define PCI_DEVICE_ID_TITAN_UNI 0x5833 ++#endif ++ ++#define VXGE_HW_TITAN1_PCI_REVISION 1 ++#define VXGE_HW_TITAN1A_PCI_REVISION 2 ++ ++#define VXGE_HP_ISS_SUBSYS_VENDORID 0x103C ++#define VXGE_HP_ISS_SUBSYS_DEVICEID_1 0x323B ++#define VXGE_HP_ISS_SUBSYS_DEVICEID_2 0x323C ++ ++#define VXGE_USE_DEFAULT 0xffffffff ++#define VXGE_HW_VPATH_MSIX_ACTIVE 4 ++#define VXGE_ALARM_MSIX_ID 2 ++#define VXGE_HW_RXSYNC_FREQ_CNT 4 ++#define VXGE_LL_WATCH_DOG_TIMEOUT (15 * HZ) ++#define VXGE_LL_RX_COPY_THRESHOLD 256 ++#define VXGE_DEF_FIFO_LENGTH 84 ++ ++#define NO_STEERING 0 ++#define PORT_STEERING 0x1 ++#define RTH_TCP_UDP_STEERING 0x2 ++#define RTH_IPV4_STEERING 0x3 ++#define RTH_IPV6_EX_STEERING 0x4 ++#define RTH_BUCKET_SIZE 8 ++ ++#define TX_PRIORITY_STEERING 1 ++#define TX_VLAN_STEERING 2 ++#define TX_PORT_STEERING 3 ++#define TX_MULTIQ_STEERING 4 ++ ++#define VXGE_HW_PROM_MODE_ENABLE 1 ++#define VXGE_HW_PROM_MODE_DISABLE 0 ++ ++#define VXGE_TTI_BTIMER_VAL 250000 ++#define VXGE_T1A_TTI_LTIMER_VAL 80 ++#define VXGE_T1A_TTI_RTIMER_VAL 400 ++ ++#define VXGE_TTI_LTIMER_VAL 1000 ++#define VXGE_TTI_RTIMER_VAL 0 ++#define VXGE_RTI_BTIMER_VAL 250 ++#define VXGE_RTI_LTIMER_VAL 100 ++#define VXGE_RTI_RTIMER_VAL 0 ++#define VXGE_FIFO_INDICATE_MAX_PKTS VXGE_DEF_FIFO_LENGTH ++#define VXGE_ISR_POLLING_CNT 8 ++#define VXGE_MAX_CONFIG_DEV 0xFF ++#define VXGE_EXEC_MODE_DISABLE 0 ++#define VXGE_EXEC_MODE_ENABLE 1 ++#define VXGE_MAX_CONFIG_PORT 1 ++ ++#define VXGE_ALL_VID_DISABLE 0 ++#define VXGE_ALL_VID_ENABLE 1 ++#define VXGE_PAUSE_CTRL_DISABLE 0 ++#define VXGE_PAUSE_CTRL_ENABLE 1 ++ ++#define TTI_TX_URANGE_A 5 ++#define TTI_TX_URANGE_B 15 ++#define TTI_TX_URANGE_C 40 ++#define TTI_TX_UFC_A 5 ++#define TTI_TX_UFC_B 40 ++#define TTI_TX_UFC_C 60 ++#define TTI_TX_UFC_D 100 ++#define TTI_T1A_TX_UFC_A 30 ++#define TTI_T1A_TX_UFC_B 80 ++ ++/* Slope - (max_mtu - min_mtu)/(max_mtu_ufc - min_mtu_ufc) */ ++/* Slope - 93 */ ++/* 60 - 9k Mtu, 140 - 1.5k mtu */ ++#define TTI_T1A_TX_UFC_C(mtu) (60 + ((VXGE_HW_MAX_MTU - mtu)/93)) ++ ++/* Slope - 37 */ ++/* 100 - 9k Mtu, 300 - 1.5k mtu */ ++#define TTI_T1A_TX_UFC_D(mtu) (100 + ((VXGE_HW_MAX_MTU - mtu)/37)) ++ ++#define RTI_RX_URANGE_A 5 ++#define RTI_RX_URANGE_B 15 ++#define RTI_RX_URANGE_C 40 ++#define RTI_T1A_RX_URANGE_A 1 ++#define RTI_T1A_RX_URANGE_B 20 ++#define RTI_T1A_RX_URANGE_C 50 ++#define RTI_RX_UFC_A 1 ++#define RTI_RX_UFC_B 5 ++#define RTI_RX_UFC_C 10 ++#define RTI_RX_UFC_D 15 ++#define RTI_T1A_RX_UFC_B 20 ++#define RTI_T1A_RX_UFC_C 50 ++#define RTI_T1A_RX_UFC_D 60 ++ ++/* ++ * The interrupt rate is maintained at 3k per second with the moderation ++ * parameters for most traffics but not all. This is the maximum interrupt ++ * count per allowed per function with INTA or per vector in the case of in a ++ * MSI-X 10 millisecond time period. Enabled only for Titan 1A. ++ */ ++#define VXGE_T1A_MAX_INTERRUPT_COUNT 100 ++ ++#define VXGE_ENABLE_NAPI 1 ++#define VXGE_DISABLE_NAPI 0 ++#define VXGE_LRO_MAX_BYTES 0x4000 ++#define VXGE_T1A_LRO_MAX_BYTES 0xC000 ++ ++/* Milli secs timer period */ ++#define VXGE_TIMER_DELAY 10000 ++ ++#define VXGE_LL_MAX_FRAME_SIZE(dev) ((dev)->mtu + VXGE_HW_MAC_HEADER_MAX_SIZE) ++ ++/* ++ * default the size of buffers allocated for dumping stats/buffers ++ * These are allocated via vmalloc and include the preformatting ++ * thats returned by the HW layer ++ */ ++#define VXGE_MRPCIM_STATS_BUFSIZE 65000 ++#define VXGE_VPATH_STATS_BUFSIZE (32 * 1024) ++#define VXGE_DEVCONF_BUFSIZE (32 * 2048) ++#define VXGE_REG_DUMP_BUFSIZE 65000 ++ ++#define is_titan1(dev_id, rev) (((dev_id == PCI_DEVICE_ID_TITAN_UNI) || \ ++ (dev_id == PCI_DEVICE_ID_TITAN_WIN)) && \ ++ (rev == VXGE_HW_TITAN1_PCI_REVISION)) ++ ++#define is_sriov(function_mode) (function_mode == VXGE_HW_FUNCTION_MODE_SRIOV) ++#define is_sf(function_mode) (function_mode == VXGE_HW_FUNCTION_MODE_SINGLE_FUNCTION) ++ ++#define vxge_spin_lock(l, f) { \ ++ if (in_interrupt()) \ ++ spin_lock(l); \ ++ else \ ++ spin_lock_irqsave(l, f); \ ++} ++ ++#define vxge_spin_trylock(l, f) \ ++({ \ ++ in_interrupt() ? \ ++ spin_trylock(l): spin_trylock_irqsave(l, f); \ ++}) ++ ++#define vxge_spin_unlock(l, f) { \ ++ if (in_interrupt()) \ ++ spin_unlock(l); \ ++ else \ ++ spin_unlock_irqrestore(l, f); \ ++} ++ ++enum vxge_reset_event { ++ /* reset events */ ++ VXGE_LL_VPATH_RESET = 0, ++ VXGE_LL_DEVICE_RESET = 1, ++ VXGE_LL_FULL_RESET = 2, ++ VXGE_LL_START_RESET = 3, ++ VXGE_LL_COMPL_RESET = 4 ++}; ++/* These flags represent the devices temporary state */ ++enum vxge_device_state_t { ++__VXGE_STATE_RESET_CARD = 0, ++__VXGE_STATE_CARD_UP ++}; ++ ++enum vxge_mac_addr_state { ++ /* mac address states */ ++ VXGE_LL_MAC_ADDR_IN_LIST = 0, ++ VXGE_LL_MAC_ADDR_IN_DA_TABLE = 1 ++}; ++ ++struct vxge_drv_config { ++ int config_dev_cnt; ++ int total_dev_cnt; ++ int g_no_cpus; ++ unsigned int vpath_per_dev; ++}; ++ ++struct macInfo { ++ unsigned char macaddr[ETH_ALEN]; ++ unsigned char macmask[ETH_ALEN]; ++ unsigned int vpath_no; ++ enum vxge_mac_addr_state state; ++}; ++struct macList { ++ unsigned int vpath_no; ++ unsigned int macaddr_no; ++ struct macInfo mac_info[128]; ++}; ++ ++ ++struct vxge_config { ++ int tx_pause_enable; ++ int rx_pause_enable; ++ int napi_enable; ++#define OLD_NAPI_WEIGHT 32 ++#define NEW_NAPI_WEIGHT 64 ++ int napi_weight; ++ int lro_enable; ++ int aggr_ack; ++#define MIN_LRO_PACKETS 1 ++#define MAX_LRO_PACKETS 10 ++#define MAX_T1A_LRO_PACKETS 30 ++ int lro_max_aggr_per_sess; ++ int lro_max_bytes; ++ int intr_type; ++ int doorbell_mode; ++#define INTA 0 ++#define MSI 1 ++#define MSI_X 2 ++ ++ int promisc_en; ++ int promisc_all_en; ++ int addr_learn_en; ++ int rec_all_vid; ++ ++ ++ int rth_algorithm; ++ int rth_hash_type_tcpipv4; ++ int rth_hash_type_ipv4; ++ int rth_hash_type_tcpipv6; ++ int rth_hash_type_ipv6; ++ int rth_hash_type_tcpipv6ex; ++ int rth_hash_type_ipv6ex; ++ int rth_bkt_sz; ++ int rth_jhash_golden_ratio; ++ int tx_steering_type; ++ int rx_steering_type; ++ int fifo_indicate_max_pkts; ++ struct vxge_hw_device_hw_info device_hw_info; ++}; ++ ++struct vxge_msix_entry { ++ /* Mimicing the msix_entry struct of Kernel. */ ++ u16 vector; ++ u16 entry; ++ u16 in_use; ++ void *arg; ++}; ++ ++/* Software Statistics */ ++ ++struct vxge_sw_stats { ++ /* Network Stats (interface stats) */ ++ struct net_device_stats net_stats; ++ ++ /* Tx */ ++ u64 tx_frms; ++ u64 tx_errors; ++ u64 tx_bytes; ++ u64 txd_not_free; ++ u64 txd_out_of_desc; ++ ++ /* Virtual Path */ ++ u64 vpaths_open; ++ u64 vpath_open_fail; ++ ++ /* Rx */ ++ u64 rx_frms; ++ u64 rx_errors; ++ u64 rx_bytes; ++ u64 rx_mcast; ++ ++ /* Misc. */ ++ u64 link_up; ++ u64 link_down; ++ u64 pci_map_fail; ++ u64 skb_alloc_fail; ++}; ++ ++ ++ ++struct vxge_mac_addrs { ++ struct list_head item; ++ u64 macaddr; ++ u64 macmask; ++ enum vxge_mac_addr_state state; ++}; ++ ++struct vxgedev; ++ ++struct vxge_fifo_stats { ++ u64 tx_frms; ++ u64 tx_errors; ++ u64 tx_bytes; ++ u64 txd_not_free; ++ u64 txd_out_of_desc; ++ u64 pci_map_fail; ++}; ++ ++struct vxge_fifo { ++ struct net_device *ndev; ++ struct pci_dev *pdev; ++ struct __vxge_hw_fifo *handle; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ volatile unsigned long tx_napi_cnt; ++#endif ++ /* The vpath id maintained in the driver - ++ * 0 to 'maximum_vpaths_in_function - 1' ++ */ ++ int driver_id; ++ int tx_steering_type; ++ int indicate_max_pkts; ++ spinlock_t tx_lock; ++ /* flag used to maintain queue state when MULTIQ is not enabled */ ++#define VPATH_QUEUE_START 0 ++#define VPATH_QUEUE_STOP 1 ++ int queue_state; ++ int addr_learn_en; ++ ++ ++ /* Tx stats */ ++ struct vxge_fifo_stats stats; ++} ____cacheline_aligned; ++ ++struct vxge_ring_stats { ++ u64 prev_rx_frms; ++ u64 rx_frms; ++ u64 rx_errors; ++ u64 rx_dropped; ++ u64 rx_bytes; ++ u64 rx_mcast; ++ u64 pci_map_fail; ++ u64 skb_alloc_fail; ++}; ++ ++struct vxge_ring { ++ struct net_device *ndev; ++ struct pci_dev *pdev; ++ struct __vxge_hw_ring *handle; ++ /* The vpath id maintained in the driver - ++ * 0 to 'maximum_vpaths_in_function - 1' ++ */ ++ int driver_id; ++ ++#define VXGE_ADAPTIVE_INTR_COALESCING_OFF 0 ++#define VXGE_ADAPTIVE_INTR_COALESCING_ON 1 ++ int adaptive_intr_coalescing; ++ /* Adaptive interrupt moderation parameters used in T1A */ ++ unsigned long interrupt_count; ++ unsigned long jiffies; ++ int rti_ci; ++ ++ /* copy of the flag indicating whether rx_csum is to be used */ ++ u32 rx_csum; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ volatile unsigned long rx_napi_cnt; ++#endif ++ ++ int pkts_processed; ++ int budget; ++ int lro_enable; ++ int doorbell_mode; ++ int aggr_ack; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) ++ struct napi_struct napi; ++ struct napi_struct *napi_p; ++#else ++ /* Adding dummy variable to avoid compilation error */ ++ int napi; ++ int pkts_to_process; ++#endif ++ int napi_enable; ++ ++#define VXGE_MAX_MAC_ADDR_COUNT 30 ++ ++ ++ ++ int rx_vlan_stripped; ++ struct vlan_group *vlgrp; ++ int rx_vector_no; ++ enum vxge_hw_status last_status; ++ ++ /* Rx stats */ ++ struct vxge_ring_stats stats; ++} ____cacheline_aligned; ++ ++struct vxge_vpath { ++ ++ struct vxge_fifo fifo; ++ struct vxge_ring ring; ++ ++ struct __vxge_hw_vpath_handle *handle; ++ ++ /* Actual vpath id for this vpath in the device - 0 to 16 */ ++ int device_id; ++ int max_mac_addr_cnt; ++ int is_configured; ++ int is_open; ++ struct vxgedev *vdev; ++ u8 (macaddr)[ETH_ALEN]; ++ u8 (macmask)[ETH_ALEN]; ++ ++#define VXGE_MAX_LEARN_MAC_ADDR_CNT 2048 ++ /* mac addresses currently programmed into NIC */ ++ u16 mac_addr_cnt; ++ u16 mcast_addr_cnt; ++ struct list_head mac_addr_list; ++ ++ u32 level_err; ++ u32 level_trace; ++}; ++#define VXGE_COPY_DEBUG_INFO_TO_LL(vdev, err, trace) { \ ++ for (i = 0; i < vdev->no_of_vpath; i++) { \ ++ vdev->vpaths[i].level_err = err; \ ++ vdev->vpaths[i].level_trace = trace; \ ++ } \ ++ vdev->level_err = err; \ ++ vdev->level_trace = trace; \ ++} ++ ++struct vxgedev { ++ struct net_device *ndev; ++ struct pci_dev *pdev; ++ struct __vxge_hw_device *devh; ++ u8 titan1; ++ struct vlan_group *vlgrp; ++ int vlan_tag_strip; ++ struct vxge_config config; ++ unsigned long state; ++ ++ /* Indicates which vpath to reset */ ++ unsigned long vp_reset; ++ ++ /* Timer used for polling vpath resets */ ++ struct timer_list vp_reset_timer; ++ ++ /* Timer used for polling vpath lockup */ ++ struct timer_list vp_lockup_timer; ++ ++ /* ++ * Flags to track whether device is in All Multicast ++ * or in promiscuous mode. ++ */ ++ u16 all_multi_flg; ++ ++ /* A flag indicating whether rx_csum is to be used or not. */ ++ u32 rx_csum; ++ ++ struct vxge_msix_entry *vxge_entries; ++ struct msix_entry *entries; ++ /* ++ * 4 for each vpath * 17; ++ * total is 68 ++ */ ++#define VXGE_MAX_REQUESTED_MSIX 68 ++#define VXGE_INTR_STRLEN 80 ++ char desc[VXGE_MAX_REQUESTED_MSIX][VXGE_INTR_STRLEN]; ++ ++ enum vxge_hw_event cric_err_event; ++ ++ int no_of_vpath; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) ++ struct napi_struct napi; ++#else ++ /* Adding dummy variable to avoid compilation error */ ++ int napi; ++#endif ++ ++ spinlock_t addr_learn_lock; /* address learn serialization lock */ ++ ++ ++ /* A debug option, when enabled and if error condition occurs, ++ * the driver will do following steps: ++ * - mask all interrupts ++ * - Not clear the source of the alarm ++ * - gracefully stop all I/O ++ * A diagnostic dump of register and stats at this point ++ * reveals very useful information. ++ */ ++ int exec_mode; ++ int max_config_port; ++ struct vxge_vpath *vpaths; ++ ++ struct __vxge_hw_vpath_handle *vp_handles[VXGE_HW_MAX_VIRTUAL_PATHS]; ++ void __iomem *bar0; ++ struct vxge_sw_stats stats; ++ int mtu; ++ int prev_mss; ++ /* Below variables are used for vpath selection to transmit a packet */ ++ u8 vpath_selector[VXGE_HW_MAX_VIRTUAL_PATHS]; ++ u64 vpaths_deployed; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ volatile unsigned long napi_cnt; ++#endif ++ u32 intr_cnt; ++ u32 level_err; ++ u32 level_trace; ++ char fw_version[VXGE_HW_FW_STRLEN]; ++ ++ ++}; ++ ++struct vxge_rx_priv { ++ struct sk_buff *skb; ++ unsigned char *skb_data; ++ dma_addr_t data_dma; ++ dma_addr_t data_size; ++}; ++ ++struct vxge_tx_priv { ++ struct sk_buff *skb; ++ dma_addr_t dma_buffers[MAX_SKB_FRAGS+1]; ++}; ++ ++ ++ ++ ++ ++ ++#ifdef module_param ++#define VXGE_MODULE_PARAM_INT(p, val) \ ++ static int p = val; \ ++ module_param(p, int, 0); ++#endif ++ ++#define vxge_os_bug(fmt...) { printk(fmt); BUG(); } ++ ++#define vxge_os_timer(timer, handle, arg, exp) do { \ ++ init_timer(&timer); \ ++ timer.function = handle; \ ++ timer.data = (unsigned long) arg; \ ++ mod_timer(&timer, (jiffies + exp)); \ ++ } while (0); ++ ++int __devinit vxge_device_register(struct __vxge_hw_device *devh, ++ struct vxge_config *config, ++ int high_dma, int no_of_vpath, ++ struct vxgedev **vdev); ++ ++void vxge_device_unregister(struct __vxge_hw_device *devh); ++ ++void vxge_vpath_intr_enable(struct vxgedev *vdev, int vp_id); ++ ++void vxge_vpath_intr_disable(struct vxgedev *vdev, int vp_id); ++ ++void vxge_callback_link_up(struct __vxge_hw_device *devh); ++ ++void vxge_callback_link_down(struct __vxge_hw_device *devh); ++ ++enum vxge_hw_status vxge_add_mac_addr(struct vxgedev *vdev, ++ struct macInfo *mac); ++ ++int vxge_mac_list_del(struct vxge_vpath *vpath, struct macInfo *mac); ++ ++int vxge_reset(struct vxgedev *vdev); ++ ++enum vxge_hw_status ++vxge_rx_1b_compl(struct __vxge_hw_ring *ringh, void *dtr, ++ u8 t_code, void *userdata); ++ ++enum vxge_hw_status ++vxge_xmit_compl(struct __vxge_hw_fifo *fifo_hw, void *dtr, ++ enum vxge_hw_fifo_tcode t_code, void *userdata, ++ struct sk_buff ***skb_ptr, int nr_skbs, int *more); ++ ++int vxge_close(struct net_device *dev); ++ ++int vxge_open(struct net_device *dev); ++ ++void vxge_close_vpaths(struct vxgedev *vdev, int index); ++ ++int vxge_open_vpaths(struct vxgedev *vdev); ++ ++enum vxge_hw_status vxge_reset_all_vpaths(struct vxgedev *vdev); ++ ++void vxge_stop_all_tx_queue(struct vxgedev *vdev); ++ ++void vxge_stop_tx_queue(struct vxge_fifo *fifo); ++ ++void vxge_start_all_tx_queue(struct vxgedev *vdev); ++ ++void vxge_wake_tx_queue(struct vxge_fifo *fifo, struct sk_buff *skb); ++ ++enum vxge_hw_status vxge_add_mac_addr(struct vxgedev *vdev, ++ struct macInfo *mac); ++ ++enum vxge_hw_status vxge_del_mac_addr(struct vxgedev *vdev, ++ struct macInfo *mac); ++ ++int vxge_mac_list_add(struct vxge_vpath *vpath, ++ struct macInfo *mac); ++ ++void vxge_free_mac_add_list(struct vxge_vpath *vpath); ++ ++int vxge_learn_mac(struct vxge_fifo *fifo, u8 *mac_header); ++ ++enum vxge_hw_status vxge_restore_vpath_mac_addr(struct vxge_vpath *vpath); ++ ++enum vxge_hw_status vxge_restore_vpath_vid_table(struct vxge_vpath *vpath); ++ ++int do_vxge_close(struct net_device *dev, int do_io); ++extern void initialize_ethtool_ops(struct net_device *ndev); ++extern int vxge_ethtool(struct net_device *dev, struct ifreq *rq); ++ ++ ++ ++/** ++ * #define VXGE_DEBUG_INIT: debug for initialization functions ++ * #define VXGE_DEBUG_TX : debug transmit related functions ++ * #define VXGE_DEBUG_RX : debug recevice related functions ++ * #define VXGE_DEBUG_MEM : debug memory module ++ * #define VXGE_DEBUG_LOCK: debug locks ++ * #define VXGE_DEBUG_SEM : debug semaphore ++ * #define VXGE_DEBUG_ENTRYEXIT: debug functions by adding entry exit statements ++*/ ++#define VXGE_DEBUG_INIT 0x00000001 ++#define VXGE_DEBUG_TX 0x00000002 ++#define VXGE_DEBUG_RX 0x00000004 ++#define VXGE_DEBUG_MEM 0x00000008 ++#define VXGE_DEBUG_LOCK 0x00000010 ++#define VXGE_DEBUG_SEM 0x00000020 ++#define VXGE_DEBUG_ENTRYEXIT 0x00000040 ++#define VXGE_DEBUG_INTR 0x00000080 ++#define VXGE_DEBUG_LL_CONFIG 0x00000100 ++ ++/* Debug tracing for VXGE driver */ ++#ifndef VXGE_DEBUG_MASK ++#define VXGE_DEBUG_MASK 0x0 ++#endif ++ ++#if (VXGE_DEBUG_LL_CONFIG & VXGE_DEBUG_MASK) ++#define vxge_debug_ll_config(level, fmt, ...) \ ++ vxge_debug_ll(level, VXGE_DEBUG_LL_CONFIG, fmt, __VA_ARGS__) ++#else ++#define vxge_debug_ll_config(level, fmt, ...) ++#endif ++ ++#if (VXGE_DEBUG_INIT & VXGE_DEBUG_MASK) ++#define vxge_debug_init(level, fmt, ...) \ ++ vxge_debug_ll(level, VXGE_DEBUG_INIT, fmt, __VA_ARGS__) ++#else ++#define vxge_debug_init(level, fmt, ...) ++#endif ++ ++#if (VXGE_DEBUG_TX & VXGE_DEBUG_MASK) ++#define vxge_debug_tx(level, fmt, ...) \ ++ vxge_debug_ll(level, VXGE_DEBUG_TX, fmt, __VA_ARGS__) ++#else ++#define vxge_debug_tx(level, fmt, ...) ++#endif ++ ++#if (VXGE_DEBUG_RX & VXGE_DEBUG_MASK) ++#define vxge_debug_rx(level, fmt, ...) \ ++ vxge_debug_ll(level, VXGE_DEBUG_RX, fmt, __VA_ARGS__) ++#else ++#define vxge_debug_rx(level, fmt, ...) ++#endif ++ ++#if (VXGE_DEBUG_MEM & VXGE_DEBUG_MASK) ++#define vxge_debug_mem(level, fmt, ...) \ ++ vxge_debug_ll(level, VXGE_DEBUG_MEM, fmt, __VA_ARGS__) ++#else ++#define vxge_debug_mem(level, fmt, ...) ++#endif ++ ++#if (VXGE_DEBUG_ENTRYEXIT & VXGE_DEBUG_MASK) ++#define vxge_debug_entryexit(level, fmt, ...) \ ++ vxge_debug_ll(level, VXGE_DEBUG_ENTRYEXIT, fmt, __VA_ARGS__) ++#else ++#define vxge_debug_entryexit(level, fmt, ...) ++#endif ++ ++#if (VXGE_DEBUG_INTR & VXGE_DEBUG_MASK) ++#define vxge_debug_intr(level, fmt, ...) \ ++ vxge_debug_ll(level, VXGE_DEBUG_INTR, fmt, __VA_ARGS__) ++#else ++#define vxge_debug_intr(level, fmt, ...) ++#endif ++ ++#define VXGE_DEVICE_DEBUG_LEVEL_SET(level, mask, vdev) {\ ++ vxge_hw_device_debug_set((struct __vxge_hw_device *)vdev->devh, \ ++ level, mask);\ ++ VXGE_COPY_DEBUG_INFO_TO_LL(vdev, \ ++ vxge_hw_device_error_level_get((struct __vxge_hw_device *) \ ++ vdev->devh), \ ++ vxge_hw_device_trace_level_get((struct __vxge_hw_device *) \ ++ vdev->devh));\ ++} ++ ++#ifndef NETIF_F_GSO ++#ifdef NETIF_F_UFO ++#define vxge_udp_mss(skb) skb_shinfo(skb)->ufo_size ++#else ++#define vxge_udp_mss(skb) 0 ++#endif ++#else ++#define vxge_udp_mss(skb) skb_shinfo(skb)->gso_size ++#endif ++ ++static inline int vxge_offload_type(struct sk_buff *skb) ++{ ++#ifdef NETIF_F_GSO ++ return skb_shinfo(skb)->gso_type; ++#else ++#ifdef NETIF_F_TSO ++ if (skb_shinfo(skb)->gso_size) ++ return SKB_GSO_TCPV4; ++#else ++#ifdef NETIF_F_UFO ++ else if(skb_shinfo(skb)->ufo_size) ++ return SKB_GSO_UDP; ++#endif ++#endif ++#endif ++ return 0; ++} ++ ++static inline int VXGE_IS_POLLER_RUNNING(struct vxgedev *vdev) ++{ ++ int ret = 0; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ return test_bit(0, &vdev->napi_cnt); ++#endif ++ return ret; ++} ++ ++static inline void VXGE_POLLER_RUNNING(struct vxgedev *vdev) ++{ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ set_bit(0, &vdev->napi_cnt); ++#endif ++ return; ++} ++ ++static inline int VXGE_CAN_CONT_ISR(void *dev_id, ++ enum __vxge_hw_channel_type type) ++{ ++ int ret = 0; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ volatile unsigned long *napi_cnt = NULL; ++ if (type == VXGE_HW_CHANNEL_TYPE_RING) ++ napi_cnt = &((struct vxge_ring *)dev_id)->rx_napi_cnt; ++ else ++ if (type == VXGE_HW_CHANNEL_TYPE_FIFO) ++ napi_cnt = &((struct vxge_fifo *)dev_id)->tx_napi_cnt; ++ if (napi_cnt) ++ ret = test_and_set_bit(0, napi_cnt); ++#endif ++ return ret; ++} ++ ++static inline void VXGE_POLL_ISR_DONE(void *dev_id, enum __vxge_hw_channel_type type) ++{ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 20)) ++ volatile unsigned long *napi_cnt; ++ if (type == VXGE_HW_CHANNEL_TYPE_RING) ++ napi_cnt = &((struct vxge_ring *)dev_id)->rx_napi_cnt; ++ else ++ if (type == VXGE_HW_CHANNEL_TYPE_FIFO) ++ napi_cnt = &((struct vxge_fifo *)dev_id)->tx_napi_cnt; ++ else ++ napi_cnt = &((struct vxgedev *)dev_id)->napi_cnt; ++ ++ clear_bit(0, napi_cnt); ++#endif ++ return; ++} ++ ++#endif +diff -r 158b6e53275e drivers/net/vxge/vxge-reg.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/vxge/vxge-reg.h Wed Aug 05 11:58:00 2009 +0100 +@@ -0,0 +1,4621 @@ ++/****************************************************************************** ++ * vxge-reg.h: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O Virtualized ++ * Server Adapter. ++ * Copyright(c) 2002-2009 Neterion Inc. ++ ******************************************************************************/ ++#ifndef VXGE_REG_H ++#define VXGE_REG_H ++ ++/* ++ * vxge_mBIT(loc) - set bit at offset ++ */ ++#define vxge_mBIT(loc) (0x8000000000000000ULL >> (loc)) ++ ++/* ++ * vxge_vBIT(val, loc, sz) - set bits at offset ++ */ ++#define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) ++#define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) ++ ++/* ++ * vxge_bVALn(bits, loc, n) - Get the value of n bits at location ++ */ ++#define vxge_bVALn(bits, loc, n) \ ++ ((((u64)bits) >> (64-(loc+n))) & ((0x1ULL << n) - 1)) ++ ++#define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits) \ ++ vxge_bVALn(bits, 0, 16) ++#define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits) \ ++ vxge_bVALn(bits, 48, 8) ++#define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits) \ ++ vxge_bVALn(bits, 56, 8) ++ ++#define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(bits) \ ++ vxge_bVALn(bits, 3, 5) ++#define VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(bits) \ ++ vxge_bVALn(bits, 5, 3) ++#define VXGE_HW_PF_SW_RESET_COMMAND 0xA5 ++ ++#define VXGE_HW_TITAN_PCICFGMGMT_REG_SPACES 17 ++#define VXGE_HW_TITAN_SRPCIM_REG_SPACES 17 ++#define VXGE_HW_TITAN_VPMGMT_REG_SPACES 17 ++#define VXGE_HW_TITAN_VPATH_REG_SPACES 17 ++ ++/* Refers to the bitmap indicating vpath assignment to VFs */ ++#define VXGE_HW_VPATH_BMAP_START 47 ++#define VXGE_HW_VPATH_BMAP_END 63 ++ ++#define VXGE_HW_PRIV_FN_ACTION 8 ++#define VXGE_HW_PRIV_VP_ACTION 5 ++#define VXGE_HW_PRIV_FN_MEMO 13 ++#define VXGE_HW_EN_DIS_UDP_RTH 10 ++#define VXGE_HW_BW_CONTROL 12 ++ ++#define VXGE_HW_ASIC_MODE_RESERVED 0 ++#define VXGE_HW_ASIC_MODE_NO_IOV 1 ++#define VXGE_HW_ASIC_MODE_SR_IOV 2 ++#define VXGE_HW_ASIC_MODE_MR_IOV 3 ++ ++#define VXGE_HW_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN vxge_mBIT(3) ++#define VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE vxge_mBIT(19) ++#define VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH vxge_mBIT(23) ++#define VXGE_HW_TXMAC_GEN_CFG1_HOST_APPEND_FCS vxge_mBIT(31) ++ ++#define VXGE_HW_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(bits) vxge_bVALn(bits, 3, 1) ++ ++#define VXGE_HW_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(bits) \ ++ vxge_bVALn(bits, 0, 32) ++ ++#define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(bits) \ ++ vxge_bVALn(bits, 50, 14) ++ ++#define VXGE_HW_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(bits) \ ++ vxge_bVALn(bits, 0, 17) ++ ++#define VXGE_HW_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER(bits) \ ++ vxge_bVALn(bits, 3, 5) ++ ++#define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(bits) \ ++ vxge_bVALn(bits, 17, 15) ++ ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_LEGACY_MODE 0 ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY 1 ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_MULTI_OP_MODE 2 ++ ++#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE_MESSAGES_ONLY 0 ++#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE_MULTI_OP_MODE 1 ++ ++#define VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val) \ ++ (val&~VXGE_HW_TOC_KDFC_INITIAL_BIR(7)) ++#define VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val) \ ++ vxge_bVALn(val, 61, 3) ++#define VXGE_HW_TOC_GET_USDC_INITIAL_OFFSET(val) \ ++ (val&~VXGE_HW_TOC_USDC_INITIAL_BIR(7)) ++#define VXGE_HW_TOC_GET_USDC_INITIAL_BIR(val) \ ++ vxge_bVALn(val, 61, 3) ++ ++#define VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(bits) bits ++#define VXGE_HW_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(bits) bits ++ ++#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR0(bits) \ ++ vxge_bVALn(bits, 1, 15) ++#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR1(bits) \ ++ vxge_bVALn(bits, 17, 15) ++#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR2(bits) \ ++ vxge_bVALn(bits, 33, 15) ++ ++#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM(val) vxge_vBIT(val, 42, 5) ++#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM(val) vxge_vBIT(val, 47, 2) ++#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET(val) \ ++ vxge_vBIT(val, 49, 15) ++ ++#define VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER 0 ++#define VXGE_HW_PRC_CFG4_RING_MODE_THREE_BUFFER 1 ++#define VXGE_HW_PRC_CFG4_RING_MODE_FIVE_BUFFER 2 ++ ++#define VXGE_HW_PRC_CFG7_SCATTER_MODE_A 0 ++#define VXGE_HW_PRC_CFG7_SCATTER_MODE_B 2 ++#define VXGE_HW_PRC_CFG7_SCATTER_MODE_C 1 ++ ++#define VXGE_HW_RTS_MGR_STEER_CTRL_WE_READ 0 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_WE_WRITE 1 ++ ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA 0 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_VID 1 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_ETYPE 2 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_PN 3 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RANGE_PN 4 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG 5 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT 6 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG 7 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK 8 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY 9 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_QOS 10 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DS 11 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12 ++#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_FW_VERSION 13 ++ ++#define VXGE_HW_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(bits) \ ++ vxge_bVALn(bits, 0, 48) ++#define VXGE_HW_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(val) vxge_vBIT(val, 0, 48) ++ ++#define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \ ++ vxge_bVALn(bits, 0, 48) ++#define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(val) vxge_vBIT(val, 0, 48) ++#define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_PRIVILEGED_MODE \ ++ vxge_mBIT(54) ++#define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits) \ ++ vxge_bVALn(bits, 55, 5) ++#define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val) \ ++ vxge_vBIT(val, 55, 5) ++#define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits) \ ++ vxge_bVALn(bits, 62, 2) ++#define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(val) vxge_vBIT(val, 62, 2) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY 0 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY 1 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY 2 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY 3 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY 0 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY 1 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY 3 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL 4 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ALL_CLEAR 172 ++ ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA 0 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID 1 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE 2 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN 3 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG 5 ++#define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT 6 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG 7 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK 8 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY 9 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_QOS 10 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DS 11 ++#define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12 ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO 13 ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) \ ++ vxge_bVALn(bits, 0, 48) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(val) vxge_vBIT(val, 0, 48) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(bits) vxge_bVALn(bits, 0, 12) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(val) vxge_vBIT(val, 0, 12) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_ETYPE(bits) vxge_bVALn(bits, 0, 11) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_ETYPE(val) vxge_vBIT(val, 0, 16) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(bits) \ ++ vxge_bVALn(bits, 3, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL vxge_mBIT(3) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(bits) \ ++ vxge_bVALn(bits, 7, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL vxge_mBIT(7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(bits) \ ++ vxge_bVALn(bits, 8, 16) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(val) vxge_vBIT(val, 8, 16) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_EN(bits) \ ++ vxge_bVALn(bits, 3, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN vxge_mBIT(3) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(bits) \ ++ vxge_bVALn(bits, 4, 4) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(val) \ ++ vxge_vBIT(val, 4, 4) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(bits) \ ++ vxge_bVALn(bits, 10, 2) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(val) \ ++ vxge_vBIT(val, 10, 2) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_JENKINS 0 ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_MS_RSS 1 ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_CRC32C 2 ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(bits) \ ++ vxge_bVALn(bits, 15, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN vxge_mBIT(15) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(bits) \ ++ vxge_bVALn(bits, 19, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN vxge_mBIT(19) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(bits) \ ++ vxge_bVALn(bits, 23, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN vxge_mBIT(23) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(bits) \ ++ vxge_bVALn(bits, 27, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN vxge_mBIT(27) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(bits) \ ++ vxge_bVALn(bits, 31, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN vxge_mBIT(31) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(bits) \ ++ vxge_bVALn(bits, 35, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN vxge_mBIT(35) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(bits) \ ++ vxge_bVALn(bits, 39, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE vxge_mBIT(39) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_REPL_ENTRY_EN(bits) \ ++ vxge_bVALn(bits, 43, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_REPL_ENTRY_EN vxge_mBIT(43) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(bits) \ ++ vxge_bVALn(bits, 3, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN vxge_mBIT(3) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_BUCKET_DATA(bits) \ ++ vxge_bVALn(bits, 9, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(val) \ ++ vxge_vBIT(val, 9, 7) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_NUM(bits) \ ++ vxge_bVALn(bits, 0, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(val) \ ++ vxge_vBIT(val, 0, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(bits) \ ++ vxge_bVALn(bits, 8, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN vxge_mBIT(8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_DATA(bits) \ ++ vxge_bVALn(bits, 9, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(val) \ ++ vxge_vBIT(val, 9, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_NUM(bits) \ ++ vxge_bVALn(bits, 16, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(val) \ ++ vxge_vBIT(val, 16, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(bits) \ ++ vxge_bVALn(bits, 24, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN vxge_mBIT(24) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_DATA(bits) \ ++ vxge_bVALn(bits, 25, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(val) \ ++ vxge_vBIT(val, 25, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_NUM(bits) \ ++ vxge_bVALn(bits, 0, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(val) \ ++ vxge_vBIT(val, 0, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(bits) \ ++ vxge_bVALn(bits, 8, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN vxge_mBIT(8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_DATA(bits) \ ++ vxge_bVALn(bits, 9, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(val) \ ++ vxge_vBIT(val, 9, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_NUM(bits) \ ++ vxge_bVALn(bits, 16, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(val) \ ++ vxge_vBIT(val, 16, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(bits) \ ++ vxge_bVALn(bits, 24, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN vxge_mBIT(24) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_DATA(bits) \ ++ vxge_bVALn(bits, 25, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(val) \ ++ vxge_vBIT(val, 25, 7) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(bits) \ ++ vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO(val) \ ++ vxge_vBIT(val, 0, 32) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(bits) \ ++ vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE(val) \ ++ vxge_vBIT(val, 32, 32) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(bits) \ ++ vxge_bVALn(bits, 0, 16) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK(val) \ ++ vxge_vBIT(val, 0, 16) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_DA_MASK(bits) \ ++ vxge_bVALn(bits, 16, 16) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(val) \ ++ vxge_vBIT(val, 16, 16) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_SA_MASK(bits) \ ++ vxge_bVALn(bits, 32, 4) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(val) \ ++ vxge_vBIT(val, 32, 4) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_DA_MASK(bits) \ ++ vxge_bVALn(bits, 36, 4) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(val) \ ++ vxge_vBIT(val, 36, 4) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4SP_MASK(bits) \ ++ vxge_bVALn(bits, 40, 2) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val) \ ++ vxge_vBIT(val, 40, 2) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4DP_MASK(bits) \ ++ vxge_bVALn(bits, 42, 2) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val) \ ++ vxge_vBIT(val, 42, 2) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_KEY_KEY(bits) \ ++ vxge_bVALn(bits, 0, 64) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_KEY_KEY vxge_vBIT(val, 0, 64) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_QOS_ENTRY_EN(bits) \ ++ vxge_bVALn(bits, 3, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_QOS_ENTRY_EN vxge_mBIT(3) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DS_ENTRY_EN(bits) \ ++ vxge_bVALn(bits, 3, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_DS_ENTRY_EN vxge_mBIT(3) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \ ++ vxge_bVALn(bits, 0, 48) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(val) \ ++ vxge_vBIT(val, 0, 48) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(val) \ ++ vxge_vBIT(val, 62, 2) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_NUM(bits) \ ++ vxge_bVALn(bits, 0, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_NUM(val) \ ++ vxge_vBIT(val, 0, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_ENTRY_EN(bits) \ ++ vxge_bVALn(bits, 8, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_ENTRY_EN vxge_mBIT(8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_DATA(bits) \ ++ vxge_bVALn(bits, 9, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_DATA(val) \ ++ vxge_vBIT(val, 9, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_NUM(bits) \ ++ vxge_bVALn(bits, 16, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_NUM(val) \ ++ vxge_vBIT(val, 16, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_ENTRY_EN(bits) \ ++ vxge_bVALn(bits, 24, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_ENTRY_EN vxge_mBIT(24) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_DATA(bits) \ ++ vxge_bVALn(bits, 25, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_DATA(val) \ ++ vxge_vBIT(val, 25, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_NUM(bits) \ ++ vxge_bVALn(bits, 32, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_NUM(val) \ ++ vxge_vBIT(val, 32, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_ENTRY_EN(bits) \ ++ vxge_bVALn(bits, 40, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_ENTRY_EN vxge_mBIT(40) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_DATA(bits) \ ++ vxge_bVALn(bits, 41, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_DATA(val) \ ++ vxge_vBIT(val, 41, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_NUM(bits) \ ++ vxge_bVALn(bits, 48, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_NUM(val) \ ++ vxge_vBIT(val, 48, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_ENTRY_EN(bits) \ ++ vxge_bVALn(bits, 56, 1) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_ENTRY_EN vxge_mBIT(56) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_DATA(bits) \ ++ vxge_bVALn(bits, 57, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_DATA(val) \ ++ vxge_vBIT(val, 57, 7) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER 0 ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER 1 ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_VERSION 2 ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE 3 ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0 4 ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_1 5 ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_2 6 ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3 7 ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_LED_CONTROL_ON 1 ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_LED_CONTROL_OFF 0 ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(bits) \ ++ vxge_bVALn(bits, 0, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_DAY(val) vxge_vBIT(val, 0, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(bits) \ ++ vxge_bVALn(bits, 8, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MONTH(val) vxge_vBIT(val, 8, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(bits) \ ++ vxge_bVALn(bits, 16, 16) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_YEAR(val) \ ++ vxge_vBIT(val, 16, 16) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(bits) \ ++ vxge_bVALn(bits, 32, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MAJOR vxge_vBIT(val, 32, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(bits) \ ++ vxge_bVALn(bits, 40, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MINOR vxge_vBIT(val, 40, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(bits) \ ++ vxge_bVALn(bits, 48, 16) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_BUILD vxge_vBIT(val, 48, 16) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(bits) \ ++ vxge_bVALn(bits, 0, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_DAY(val) vxge_vBIT(val, 0, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(bits) \ ++ vxge_bVALn(bits, 8, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MONTH(val) vxge_vBIT(val, 8, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(bits) \ ++ vxge_bVALn(bits, 16, 16) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_YEAR(val) \ ++ vxge_vBIT(val, 16, 16) ++ ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(bits) \ ++ vxge_bVALn(bits, 32, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MAJOR vxge_vBIT(val, 32, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(bits) \ ++ vxge_bVALn(bits, 40, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MINOR vxge_vBIT(val, 40, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(bits) \ ++ vxge_bVALn(bits, 48, 16) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_BUILD vxge_vBIT(val, 48, 16) ++ ++#define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_GET_PPIF_SRPCIM_TO_VPATH_ALARM(bits)\ ++ vxge_bVALn(bits, 0, 18) ++ ++#define VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(bits) \ ++ vxge_bVALn(bits, 48, 16) ++#define VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(bits) \ ++ vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(bits) vxge_bVALn(bits, 48, 16) ++#define VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(bits) \ ++ vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(bits) \ ++ vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(bits) \ ++ vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(bits) (bits) ++#define VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(bits) (bits) ++#define VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(bits) \ ++ vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(bits) \ ++ vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(bits) \ ++ vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(bits) \ ++ vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(bits) \ ++ vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(bits) \ ++ vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(bits) \ ++ vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(bits) \ ++ vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(bits\ ++) vxge_bVALn(bits, 48, 16) ++#define VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(bits) vxge_bVALn(bits, 0, 16) ++#define VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(bits) \ ++ vxge_bVALn(bits, 16, 16) ++#define VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(bits) \ ++ vxge_bVALn(bits, 32, 16) ++#define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(bits) vxge_bVALn(bits, 0, 16) ++#define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(bits) \ ++ vxge_bVALn(bits, 16, 16) ++#define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(bits) \ ++ vxge_bVALn(bits, 32, 16) ++ ++#define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(bits) \ ++ vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(bits) \ ++ vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(bits\ ++) vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(bits\ ++) vxge_bVALn(bits, 32, 32) ++#define \ ++VXGE_HW_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(bits) \ ++ vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(bits) \ ++ vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(bits) \ ++ vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(bits) \ ++ vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(bits) \ ++ vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(bits) \ ++ vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(bits) \ ++ vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(bits) \ ++ vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(bits) \ ++ vxge_bVALn(bits, 32, 32) ++ ++#define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_MSG(bits) vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_CPL(bits) vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT0(bits) vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT1(bits) vxge_bVALn(bits, 32, 32) ++#define VXGE_HW_DEBUG_STATS2_GET_RSTDROP_CLIENT2(bits) vxge_bVALn(bits, 0, 32) ++#define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_PH(bits) vxge_bVALn(bits, 0, 16) ++#define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(bits) vxge_bVALn(bits, 16, 16) ++#define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(bits) vxge_bVALn(bits, 32, 16) ++#define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_PD(bits) vxge_bVALn(bits, 0, 16) ++#define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(bits) vxge_bVALn(bits, 16, 16) ++#define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(bits) vxge_bVALn(bits, 32, 16) ++ ++#define VXGE_HW_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(bits) \ ++ vxge_bVALn(bits, 32, 32) ++ ++#define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(bits) \ ++ vxge_bVALn(bits, 0, 8) ++#define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(bits) \ ++ vxge_bVALn(bits, 8, 8) ++#define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(bits) \ ++ vxge_bVALn(bits, 16, 8) ++ ++#define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(bits) \ ++ vxge_bVALn(bits, 0, 8) ++#define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(bits) \ ++ vxge_bVALn(bits, 8, 8) ++#define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(bits) \ ++ vxge_bVALn(bits, 16, 8) ++ ++#define VXGE_HW_CONFIG_PRIV_H ++ ++#define VXGE_HW_SWAPPER_INITIAL_VALUE 0x0123456789abcdefULL ++#define VXGE_HW_SWAPPER_BYTE_SWAPPED 0xefcdab8967452301ULL ++#define VXGE_HW_SWAPPER_BIT_FLIPPED 0x80c4a2e691d5b3f7ULL ++#define VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED 0xf7b3d591e6a2c480ULL ++ ++#define VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE 0xFFFFFFFFFFFFFFFFULL ++#define VXGE_HW_SWAPPER_READ_BYTE_SWAP_DISABLE 0x0000000000000000ULL ++ ++#define VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE 0xFFFFFFFFFFFFFFFFULL ++#define VXGE_HW_SWAPPER_READ_BIT_FLAP_DISABLE 0x0000000000000000ULL ++ ++#define VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE 0xFFFFFFFFFFFFFFFFULL ++#define VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_DISABLE 0x0000000000000000ULL ++ ++#define VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE 0xFFFFFFFFFFFFFFFFULL ++#define VXGE_HW_SWAPPER_WRITE_BIT_FLAP_DISABLE 0x0000000000000000ULL ++ ++/* ++ * The registers are memory mapped and are native big-endian byte order. The ++ * little-endian hosts are handled by enabling hardware byte-swapping for ++ * register and dma operations. ++ */ ++struct vxge_hw_legacy_reg { ++ ++ u8 unused00010[0x00010]; ++ ++/*0x00010*/ u64 toc_swapper_fb; ++#define VXGE_HW_TOC_SWAPPER_FB_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) ++/*0x00018*/ u64 pifm_rd_swap_en; ++#define VXGE_HW_PIFM_RD_SWAP_EN_PIFM_RD_SWAP_EN(val) vxge_vBIT(val, 0, 64) ++/*0x00020*/ u64 pifm_rd_flip_en; ++#define VXGE_HW_PIFM_RD_FLIP_EN_PIFM_RD_FLIP_EN(val) vxge_vBIT(val, 0, 64) ++/*0x00028*/ u64 pifm_wr_swap_en; ++#define VXGE_HW_PIFM_WR_SWAP_EN_PIFM_WR_SWAP_EN(val) vxge_vBIT(val, 0, 64) ++/*0x00030*/ u64 pifm_wr_flip_en; ++#define VXGE_HW_PIFM_WR_FLIP_EN_PIFM_WR_FLIP_EN(val) vxge_vBIT(val, 0, 64) ++/*0x00038*/ u64 toc_first_pointer; ++#define VXGE_HW_TOC_FIRST_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) ++/*0x00040*/ u64 host_access_en; ++#define VXGE_HW_HOST_ACCESS_EN_HOST_ACCESS_EN(val) vxge_vBIT(val, 0, 64) ++ ++} __attribute((packed)); ++ ++struct vxge_hw_toc_reg { ++ ++ u8 unused00050[0x00050]; ++ ++/*0x00050*/ u64 toc_common_pointer; ++#define VXGE_HW_TOC_COMMON_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) ++/*0x00058*/ u64 toc_memrepair_pointer; ++#define VXGE_HW_TOC_MEMREPAIR_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) ++/*0x00060*/ u64 toc_pcicfgmgmt_pointer[17]; ++#define VXGE_HW_TOC_PCICFGMGMT_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) ++ u8 unused001e0[0x001e0-0x000e8]; ++ ++/*0x001e0*/ u64 toc_mrpcim_pointer; ++#define VXGE_HW_TOC_MRPCIM_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) ++/*0x001e8*/ u64 toc_srpcim_pointer[17]; ++#define VXGE_HW_TOC_SRPCIM_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) ++ u8 unused00278[0x00278-0x00270]; ++ ++/*0x00278*/ u64 toc_vpmgmt_pointer[17]; ++#define VXGE_HW_TOC_VPMGMT_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) ++ u8 unused00390[0x00390-0x00300]; ++ ++/*0x00390*/ u64 toc_vpath_pointer[17]; ++#define VXGE_HW_TOC_VPATH_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) ++ u8 unused004a0[0x004a0-0x00418]; ++ ++/*0x004a0*/ u64 toc_kdfc; ++#define VXGE_HW_TOC_KDFC_INITIAL_OFFSET(val) vxge_vBIT(val, 0, 61) ++#define VXGE_HW_TOC_KDFC_INITIAL_BIR(val) vxge_vBIT(val, 61, 3) ++/*0x004a8*/ u64 toc_usdc; ++#define VXGE_HW_TOC_USDC_INITIAL_OFFSET(val) vxge_vBIT(val, 0, 61) ++#define VXGE_HW_TOC_USDC_INITIAL_BIR(val) vxge_vBIT(val, 61, 3) ++/*0x004b0*/ u64 toc_kdfc_vpath_stride; ++#define VXGE_HW_TOC_KDFC_VPATH_STRIDE_INITIAL_TOC_KDFC_VPATH_STRIDE(val) \ ++ vxge_vBIT(val, 0, 64) ++/*0x004b8*/ u64 toc_kdfc_fifo_stride; ++#define VXGE_HW_TOC_KDFC_FIFO_STRIDE_INITIAL_TOC_KDFC_FIFO_STRIDE(val) \ ++ vxge_vBIT(val, 0, 64) ++ ++} __attribute((packed)); ++ ++struct vxge_hw_common_reg { ++ ++ u8 unused00a00[0x00a00]; ++ ++/*0x00a00*/ u64 prc_status1; ++#define VXGE_HW_PRC_STATUS1_PRC_VP_QUIESCENT(n) vxge_mBIT(n) ++/*0x00a08*/ u64 rxdcm_reset_in_progress; ++#define VXGE_HW_RXDCM_RESET_IN_PROGRESS_PRC_VP(n) vxge_mBIT(n) ++/*0x00a10*/ u64 replicq_flush_in_progress; ++#define VXGE_HW_REPLICQ_FLUSH_IN_PROGRESS_NOA_VP(n) vxge_mBIT(n) ++/*0x00a18*/ u64 rxpe_cmds_reset_in_progress; ++#define VXGE_HW_RXPE_CMDS_RESET_IN_PROGRESS_NOA_VP(n) vxge_mBIT(n) ++/*0x00a20*/ u64 mxp_cmds_reset_in_progress; ++#define VXGE_HW_MXP_CMDS_RESET_IN_PROGRESS_NOA_VP(n) vxge_mBIT(n) ++/*0x00a28*/ u64 noffload_reset_in_progress; ++#define VXGE_HW_NOFFLOAD_RESET_IN_PROGRESS_PRC_VP(n) vxge_mBIT(n) ++/*0x00a30*/ u64 rd_req_in_progress; ++#define VXGE_HW_RD_REQ_IN_PROGRESS_VP(n) vxge_mBIT(n) ++/*0x00a38*/ u64 rd_req_outstanding; ++#define VXGE_HW_RD_REQ_OUTSTANDING_VP(n) vxge_mBIT(n) ++/*0x00a40*/ u64 kdfc_reset_in_progress; ++#define VXGE_HW_KDFC_RESET_IN_PROGRESS_NOA_VP(n) vxge_mBIT(n) ++ u8 unused00b00[0x00b00-0x00a48]; ++ ++/*0x00b00*/ u64 one_cfg_vp; ++#define VXGE_HW_ONE_CFG_VP_RDY(n) vxge_mBIT(n) ++/*0x00b08*/ u64 one_common; ++#define VXGE_HW_ONE_COMMON_PET_VPATH_RESET_IN_PROGRESS(n) vxge_mBIT(n) ++ u8 unused00b80[0x00b80-0x00b10]; ++ ++/*0x00b80*/ u64 tim_int_en; ++#define VXGE_HW_TIM_INT_EN_TIM_VP(n) vxge_mBIT(n) ++/*0x00b88*/ u64 tim_set_int_en; ++#define VXGE_HW_TIM_SET_INT_EN_VP(n) vxge_mBIT(n) ++/*0x00b90*/ u64 tim_clr_int_en; ++#define VXGE_HW_TIM_CLR_INT_EN_VP(n) vxge_mBIT(n) ++/*0x00b98*/ u64 tim_mask_int_during_reset; ++#define VXGE_HW_TIM_MASK_INT_DURING_RESET_VPATH(n) vxge_mBIT(n) ++/*0x00ba0*/ u64 tim_reset_in_progress; ++#define VXGE_HW_TIM_RESET_IN_PROGRESS_TIM_VPATH(n) vxge_mBIT(n) ++/*0x00ba8*/ u64 tim_outstanding_bmap; ++#define VXGE_HW_TIM_OUTSTANDING_BMAP_TIM_VPATH(n) vxge_mBIT(n) ++ u8 unused00c00[0x00c00-0x00bb0]; ++ ++/*0x00c00*/ u64 msg_reset_in_progress; ++#define VXGE_HW_MSG_RESET_IN_PROGRESS_MSG_COMPOSITE(val) vxge_vBIT(val, 0, 17) ++/*0x00c08*/ u64 msg_mxp_mr_ready; ++#define VXGE_HW_MSG_MXP_MR_READY_MP_BOOTED(n) vxge_mBIT(n) ++/*0x00c10*/ u64 msg_uxp_mr_ready; ++#define VXGE_HW_MSG_UXP_MR_READY_UP_BOOTED(n) vxge_mBIT(n) ++/*0x00c18*/ u64 msg_dmq_noni_rtl_prefetch; ++#define VXGE_HW_MSG_DMQ_NONI_RTL_PREFETCH_BYPASS_ENABLE(n) vxge_mBIT(n) ++/*0x00c20*/ u64 msg_umq_rtl_bwr; ++#define VXGE_HW_MSG_UMQ_RTL_BWR_PREFETCH_DISABLE(n) vxge_mBIT(n) ++ u8 unused00d00[0x00d00-0x00c28]; ++ ++/*0x00d00*/ u64 cmn_rsthdlr_cfg0; ++#define VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(val) vxge_vBIT(val, 0, 17) ++/*0x00d08*/ u64 cmn_rsthdlr_cfg1; ++#define VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(val) vxge_vBIT(val, 0, 17) ++/*0x00d10*/ u64 cmn_rsthdlr_cfg2; ++#define VXGE_HW_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(val) vxge_vBIT(val, 0, 17) ++/*0x00d18*/ u64 cmn_rsthdlr_cfg3; ++#define VXGE_HW_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(val) vxge_vBIT(val, 0, 17) ++/*0x00d20*/ u64 cmn_rsthdlr_cfg4; ++#define VXGE_HW_CMN_RSTHDLR_CFG4_SW_RESET_FIFO2(val) vxge_vBIT(val, 0, 17) ++ u8 unused00d40[0x00d40-0x00d28]; ++ ++/*0x00d40*/ u64 cmn_rsthdlr_cfg8; ++#define VXGE_HW_CMN_RSTHDLR_CFG8_INCR_VPATH_INST_NUM(val) vxge_vBIT(val, 0, 17) ++/*0x00d48*/ u64 stats_cfg0; ++#define VXGE_HW_STATS_CFG0_STATS_ENABLE(val) vxge_vBIT(val, 0, 17) ++ u8 unused00da8[0x00da8-0x00d50]; ++ ++/*0x00da8*/ u64 clear_msix_mask_vect[4]; ++#define VXGE_HW_CLEAR_MSIX_MASK_VECT_CLEAR_MSIX_MASK_VECT(val) \ ++ vxge_vBIT(val, 0, 17) ++/*0x00dc8*/ u64 set_msix_mask_vect[4]; ++#define VXGE_HW_SET_MSIX_MASK_VECT_SET_MSIX_MASK_VECT(val) vxge_vBIT(val, 0, 17) ++/*0x00de8*/ u64 clear_msix_mask_all_vect; ++#define VXGE_HW_CLEAR_MSIX_MASK_ALL_VECT_CLEAR_MSIX_MASK_ALL_VECT(val) \ ++ vxge_vBIT(val, 0, 17) ++/*0x00df0*/ u64 set_msix_mask_all_vect; ++#define VXGE_HW_SET_MSIX_MASK_ALL_VECT_SET_MSIX_MASK_ALL_VECT(val) \ ++ vxge_vBIT(val, 0, 17) ++/*0x00df8*/ u64 mask_vector[4]; ++#define VXGE_HW_MASK_VECTOR_MASK_VECTOR(val) vxge_vBIT(val, 0, 17) ++/*0x00e18*/ u64 msix_pending_vector[4]; ++#define VXGE_HW_MSIX_PENDING_VECTOR_MSIX_PENDING_VECTOR(val) \ ++ vxge_vBIT(val, 0, 17) ++/*0x00e38*/ u64 clr_msix_one_shot_vec[4]; ++#define VXGE_HW_CLR_MSIX_ONE_SHOT_VEC_CLR_MSIX_ONE_SHOT_VEC(val) \ ++ vxge_vBIT(val, 0, 17) ++/*0x00e58*/ u64 titan_asic_id; ++#define VXGE_HW_TITAN_ASIC_ID_INITIAL_DEVICE_ID(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_TITAN_ASIC_ID_INITIAL_MAJOR_REVISION(val) vxge_vBIT(val, 48, 8) ++#define VXGE_HW_TITAN_ASIC_ID_INITIAL_MINOR_REVISION(val) vxge_vBIT(val, 56, 8) ++/*0x00e60*/ u64 titan_general_int_status; ++#define VXGE_HW_TITAN_GENERAL_INT_STATUS_MRPCIM_ALARM_INT vxge_mBIT(0) ++#define VXGE_HW_TITAN_GENERAL_INT_STATUS_SRPCIM_ALARM_INT vxge_mBIT(1) ++#define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT vxge_mBIT(2) ++#define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(val) \ ++ vxge_vBIT(val, 3, 17) ++ u8 unused00e70[0x00e70-0x00e68]; ++ ++/*0x00e70*/ u64 titan_mask_all_int; ++#define VXGE_HW_TITAN_MASK_ALL_INT_ALARM vxge_mBIT(7) ++#define VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC vxge_mBIT(15) ++ u8 unused00e80[0x00e80-0x00e78]; ++ ++/*0x00e80*/ u64 tim_int_status0; ++#define VXGE_HW_TIM_INT_STATUS0_TIM_INT_STATUS0(val) vxge_vBIT(val, 0, 64) ++/*0x00e88*/ u64 tim_int_mask0; ++#define VXGE_HW_TIM_INT_MASK0_TIM_INT_MASK0(val) vxge_vBIT(val, 0, 64) ++/*0x00e90*/ u64 tim_int_status1; ++#define VXGE_HW_TIM_INT_STATUS1_TIM_INT_STATUS1(val) vxge_vBIT(val, 0, 4) ++/*0x00e98*/ u64 tim_int_mask1; ++#define VXGE_HW_TIM_INT_MASK1_TIM_INT_MASK1(val) vxge_vBIT(val, 0, 4) ++/*0x00ea0*/ u64 rti_int_status; ++#define VXGE_HW_RTI_INT_STATUS_RTI_INT_STATUS(val) vxge_vBIT(val, 0, 17) ++/*0x00ea8*/ u64 rti_int_mask; ++#define VXGE_HW_RTI_INT_MASK_RTI_INT_MASK(val) vxge_vBIT(val, 0, 17) ++/*0x00eb0*/ u64 adapter_status; ++#define VXGE_HW_ADAPTER_STATUS_RTDMA_RTDMA_READY vxge_mBIT(0) ++#define VXGE_HW_ADAPTER_STATUS_WRDMA_WRDMA_READY vxge_mBIT(1) ++#define VXGE_HW_ADAPTER_STATUS_KDFC_KDFC_READY vxge_mBIT(2) ++#define VXGE_HW_ADAPTER_STATUS_TPA_TMAC_BUF_EMPTY vxge_mBIT(3) ++#define VXGE_HW_ADAPTER_STATUS_RDCTL_PIC_QUIESCENT vxge_mBIT(4) ++#define VXGE_HW_ADAPTER_STATUS_XGMAC_NETWORK_FAULT vxge_mBIT(5) ++#define VXGE_HW_ADAPTER_STATUS_ROCRC_OFFLOAD_QUIESCENT vxge_mBIT(6) ++#define VXGE_HW_ADAPTER_STATUS_G3IF_FB_G3IF_FB_GDDR3_READY vxge_mBIT(7) ++#define VXGE_HW_ADAPTER_STATUS_G3IF_CM_G3IF_CM_GDDR3_READY vxge_mBIT(8) ++#define VXGE_HW_ADAPTER_STATUS_RIC_RIC_RUNNING vxge_mBIT(9) ++#define VXGE_HW_ADAPTER_STATUS_CMG_C_PLL_IN_LOCK vxge_mBIT(10) ++#define VXGE_HW_ADAPTER_STATUS_XGMAC_X_PLL_IN_LOCK vxge_mBIT(11) ++#define VXGE_HW_ADAPTER_STATUS_FBIF_M_PLL_IN_LOCK vxge_mBIT(12) ++#define VXGE_HW_ADAPTER_STATUS_PCC_PCC_IDLE(val) vxge_vBIT(val, 24, 8) ++#define VXGE_HW_ADAPTER_STATUS_ROCRC_RC_PRC_QUIESCENT(val) vxge_vBIT(val, 44, 8) ++/*0x00eb8*/ u64 gen_ctrl; ++#define VXGE_HW_GEN_CTRL_SPI_MRPCIM_WR_DIS vxge_mBIT(0) ++#define VXGE_HW_GEN_CTRL_SPI_MRPCIM_RD_DIS vxge_mBIT(1) ++#define VXGE_HW_GEN_CTRL_SPI_SRPCIM_WR_DIS vxge_mBIT(2) ++#define VXGE_HW_GEN_CTRL_SPI_SRPCIM_RD_DIS vxge_mBIT(3) ++#define VXGE_HW_GEN_CTRL_SPI_DEBUG_DIS vxge_mBIT(4) ++#define VXGE_HW_GEN_CTRL_SPI_APP_LTSSM_TIMER_DIS vxge_mBIT(5) ++#define VXGE_HW_GEN_CTRL_SPI_NOT_USED(val) vxge_vBIT(val, 6, 4) ++ u8 unused00ed0[0x00ed0-0x00ec0]; ++ ++/*0x00ed0*/ u64 adapter_ready; ++#define VXGE_HW_ADAPTER_READY_ADAPTER_READY vxge_mBIT(63) ++/*0x00ed8*/ u64 outstanding_read; ++#define VXGE_HW_OUTSTANDING_READ_OUTSTANDING_READ(val) vxge_vBIT(val, 0, 17) ++/*0x00ee0*/ u64 vpath_rst_in_prog; ++#define VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(val) vxge_vBIT(val, 0, 17) ++/*0x00ee8*/ u64 vpath_reg_modified; ++#define VXGE_HW_VPATH_REG_MODIFIED_VPATH_REG_MODIFIED(val) vxge_vBIT(val, 0, 17) ++ u8 unused00fc0[0x00fc0-0x00ef0]; ++ ++/*0x00fc0*/ u64 cp_reset_in_progress; ++#define VXGE_HW_CP_RESET_IN_PROGRESS_CP_VPATH(n) vxge_mBIT(n) ++ u8 unused01080[0x01080-0x00fc8]; ++ ++/*0x01080*/ u64 xgmac_ready; ++#define VXGE_HW_XGMAC_READY_XMACJ_READY(val) vxge_vBIT(val, 0, 17) ++ u8 unused010c0[0x010c0-0x01088]; ++ ++/*0x010c0*/ u64 fbif_ready; ++#define VXGE_HW_FBIF_READY_FAU_READY(val) vxge_vBIT(val, 0, 17) ++ u8 unused01100[0x01100-0x010c8]; ++ ++/*0x01100*/ u64 vplane_assignments; ++#define VXGE_HW_VPLANE_ASSIGNMENTS_VPLANE_ASSIGNMENTS(val) vxge_vBIT(val, 3, 5) ++/*0x01108*/ u64 vpath_assignments; ++#define VXGE_HW_VPATH_ASSIGNMENTS_VPATH_ASSIGNMENTS(val) vxge_vBIT(val, 0, 17) ++/*0x01110*/ u64 resource_assignments; ++#define VXGE_HW_RESOURCE_ASSIGNMENTS_RESOURCE_ASSIGNMENTS(val) \ ++ vxge_vBIT(val, 0, 17) ++/*0x01118*/ u64 host_type_assignments; ++#define VXGE_HW_HOST_TYPE_ASSIGNMENTS_HOST_TYPE_ASSIGNMENTS(val) \ ++ vxge_vBIT(val, 5, 3) ++ u8 unused01128[0x01128-0x01120]; ++ ++/*0x01128*/ u64 max_resource_assignments; ++#define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPLANE(val) \ ++ vxge_vBIT(val, 3, 5) ++#define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPATHS(val) \ ++ vxge_vBIT(val, 11, 5) ++/*0x01130*/ u64 pf_vpath_assignments; ++#define VXGE_HW_PF_VPATH_ASSIGNMENTS_PF_VPATH_ASSIGNMENTS(val) \ ++ vxge_vBIT(val, 0, 17) ++ u8 unused01200[0x01200-0x01138]; ++ ++/*0x01200*/ u64 rts_access_icmp; ++#define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17) ++/*0x01208*/ u64 rts_access_tcpsyn; ++#define VXGE_HW_RTS_ACCESS_TCPSYN_EN(val) vxge_vBIT(val, 0, 17) ++/*0x01210*/ u64 rts_access_zl4pyld; ++#define VXGE_HW_RTS_ACCESS_ZL4PYLD_EN(val) vxge_vBIT(val, 0, 17) ++/*0x01218*/ u64 rts_access_l4prtcl_tcp; ++#define VXGE_HW_RTS_ACCESS_L4PRTCL_TCP_EN(val) vxge_vBIT(val, 0, 17) ++/*0x01220*/ u64 rts_access_l4prtcl_udp; ++#define VXGE_HW_RTS_ACCESS_L4PRTCL_UDP_EN(val) vxge_vBIT(val, 0, 17) ++/*0x01228*/ u64 rts_access_l4prtcl_flex; ++#define VXGE_HW_RTS_ACCESS_L4PRTCL_FLEX_EN(val) vxge_vBIT(val, 0, 17) ++/*0x01230*/ u64 rts_access_ipfrag; ++#define VXGE_HW_RTS_ACCESS_IPFRAG_EN(val) vxge_vBIT(val, 0, 17) ++ ++} __attribute((packed)); ++ ++struct vxge_hw_memrepair_reg { ++ u64 unused1; ++ u64 unused2; ++} __attribute((packed)); ++ ++struct vxge_hw_pcicfgmgmt_reg { ++ ++/*0x00000*/ u64 resource_no; ++#define VXGE_HW_RESOURCE_NO_PFN_OR_VF BIT(3) ++/*0x00008*/ u64 bargrp_pf_or_vf_bar0_mask; ++#define VXGE_HW_BARGRP_PF_OR_VF_BAR0_MASK_BARGRP_PF_OR_VF_BAR0_MASK(val) \ ++ vxge_vBIT(val, 2, 6) ++/*0x00010*/ u64 bargrp_pf_or_vf_bar1_mask; ++#define VXGE_HW_BARGRP_PF_OR_VF_BAR1_MASK_BARGRP_PF_OR_VF_BAR1_MASK(val) \ ++ vxge_vBIT(val, 2, 6) ++/*0x00018*/ u64 bargrp_pf_or_vf_bar2_mask; ++#define VXGE_HW_BARGRP_PF_OR_VF_BAR2_MASK_BARGRP_PF_OR_VF_BAR2_MASK(val) \ ++ vxge_vBIT(val, 2, 6) ++/*0x00020*/ u64 msixgrp_no; ++#define VXGE_HW_MSIXGRP_NO_TABLE_SIZE(val) vxge_vBIT(val, 5, 11) ++ ++} __attribute((packed)); ++ ++struct vxge_hw_mrpcim_reg { ++/*0x00000*/ u64 g3fbct_int_status; ++#define VXGE_HW_G3FBCT_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) ++/*0x00008*/ u64 g3fbct_int_mask; ++/*0x00010*/ u64 g3fbct_err_reg; ++#define VXGE_HW_G3FBCT_ERR_REG_G3IF_SM_ERR vxge_mBIT(4) ++#define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_DECC vxge_mBIT(5) ++#define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_U_DECC vxge_mBIT(6) ++#define VXGE_HW_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_DECC vxge_mBIT(7) ++#define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_SECC vxge_mBIT(29) ++#define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_U_SECC vxge_mBIT(30) ++#define VXGE_HW_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_SECC vxge_mBIT(31) ++/*0x00018*/ u64 g3fbct_err_mask; ++/*0x00020*/ u64 g3fbct_err_alarm; ++ ++ u8 unused00a00[0x00a00-0x00028]; ++ ++/*0x00a00*/ u64 wrdma_int_status; ++#define VXGE_HW_WRDMA_INT_STATUS_RC_ALARM_RC_INT vxge_mBIT(0) ++#define VXGE_HW_WRDMA_INT_STATUS_RXDRM_SM_ERR_RXDRM_INT vxge_mBIT(1) ++#define VXGE_HW_WRDMA_INT_STATUS_RXDCM_SM_ERR_RXDCM_SM_INT vxge_mBIT(2) ++#define VXGE_HW_WRDMA_INT_STATUS_RXDWM_SM_ERR_RXDWM_INT vxge_mBIT(3) ++#define VXGE_HW_WRDMA_INT_STATUS_RDA_ERR_RDA_INT vxge_mBIT(6) ++#define VXGE_HW_WRDMA_INT_STATUS_RDA_ECC_DB_RDA_ECC_DB_INT vxge_mBIT(8) ++#define VXGE_HW_WRDMA_INT_STATUS_RDA_ECC_SG_RDA_ECC_SG_INT vxge_mBIT(9) ++#define VXGE_HW_WRDMA_INT_STATUS_FRF_ALARM_FRF_INT vxge_mBIT(12) ++#define VXGE_HW_WRDMA_INT_STATUS_ROCRC_ALARM_ROCRC_INT vxge_mBIT(13) ++#define VXGE_HW_WRDMA_INT_STATUS_WDE0_ALARM_WDE0_INT vxge_mBIT(14) ++#define VXGE_HW_WRDMA_INT_STATUS_WDE1_ALARM_WDE1_INT vxge_mBIT(15) ++#define VXGE_HW_WRDMA_INT_STATUS_WDE2_ALARM_WDE2_INT vxge_mBIT(16) ++#define VXGE_HW_WRDMA_INT_STATUS_WDE3_ALARM_WDE3_INT vxge_mBIT(17) ++/*0x00a08*/ u64 wrdma_int_mask; ++/*0x00a10*/ u64 rc_alarm_reg; ++#define VXGE_HW_RC_ALARM_REG_FTC_SM_ERR vxge_mBIT(0) ++#define VXGE_HW_RC_ALARM_REG_FTC_SM_PHASE_ERR vxge_mBIT(1) ++#define VXGE_HW_RC_ALARM_REG_BTDWM_SM_ERR vxge_mBIT(2) ++#define VXGE_HW_RC_ALARM_REG_BTC_SM_ERR vxge_mBIT(3) ++#define VXGE_HW_RC_ALARM_REG_BTDCM_SM_ERR vxge_mBIT(4) ++#define VXGE_HW_RC_ALARM_REG_BTDRM_SM_ERR vxge_mBIT(5) ++#define VXGE_HW_RC_ALARM_REG_RMM_RXD_RC_ECC_DB_ERR vxge_mBIT(6) ++#define VXGE_HW_RC_ALARM_REG_RMM_RXD_RC_ECC_SG_ERR vxge_mBIT(7) ++#define VXGE_HW_RC_ALARM_REG_RHS_RXD_RHS_ECC_DB_ERR vxge_mBIT(8) ++#define VXGE_HW_RC_ALARM_REG_RHS_RXD_RHS_ECC_SG_ERR vxge_mBIT(9) ++#define VXGE_HW_RC_ALARM_REG_RMM_SM_ERR vxge_mBIT(10) ++#define VXGE_HW_RC_ALARM_REG_BTC_VPATH_MISMATCH_ERR vxge_mBIT(12) ++/*0x00a18*/ u64 rc_alarm_mask; ++/*0x00a20*/ u64 rc_alarm_alarm; ++/*0x00a28*/ u64 rxdrm_sm_err_reg; ++#define VXGE_HW_RXDRM_SM_ERR_REG_PRC_VP(n) vxge_mBIT(n) ++/*0x00a30*/ u64 rxdrm_sm_err_mask; ++/*0x00a38*/ u64 rxdrm_sm_err_alarm; ++/*0x00a40*/ u64 rxdcm_sm_err_reg; ++#define VXGE_HW_RXDCM_SM_ERR_REG_PRC_VP(n) vxge_mBIT(n) ++/*0x00a48*/ u64 rxdcm_sm_err_mask; ++/*0x00a50*/ u64 rxdcm_sm_err_alarm; ++/*0x00a58*/ u64 rxdwm_sm_err_reg; ++#define VXGE_HW_RXDWM_SM_ERR_REG_PRC_VP(n) vxge_mBIT(n) ++/*0x00a60*/ u64 rxdwm_sm_err_mask; ++/*0x00a68*/ u64 rxdwm_sm_err_alarm; ++/*0x00a70*/ u64 rda_err_reg; ++#define VXGE_HW_RDA_ERR_REG_RDA_SM0_ERR_ALARM vxge_mBIT(0) ++#define VXGE_HW_RDA_ERR_REG_RDA_MISC_ERR vxge_mBIT(1) ++#define VXGE_HW_RDA_ERR_REG_RDA_PCIX_ERR vxge_mBIT(2) ++#define VXGE_HW_RDA_ERR_REG_RDA_RXD_ECC_DB_ERR vxge_mBIT(3) ++#define VXGE_HW_RDA_ERR_REG_RDA_FRM_ECC_DB_ERR vxge_mBIT(4) ++#define VXGE_HW_RDA_ERR_REG_RDA_UQM_ECC_DB_ERR vxge_mBIT(5) ++#define VXGE_HW_RDA_ERR_REG_RDA_IMM_ECC_DB_ERR vxge_mBIT(6) ++#define VXGE_HW_RDA_ERR_REG_RDA_TIM_ECC_DB_ERR vxge_mBIT(7) ++/*0x00a78*/ u64 rda_err_mask; ++/*0x00a80*/ u64 rda_err_alarm; ++/*0x00a88*/ u64 rda_ecc_db_reg; ++#define VXGE_HW_RDA_ECC_DB_REG_RDA_RXD_ERR(n) vxge_mBIT(n) ++/*0x00a90*/ u64 rda_ecc_db_mask; ++/*0x00a98*/ u64 rda_ecc_db_alarm; ++/*0x00aa0*/ u64 rda_ecc_sg_reg; ++#define VXGE_HW_RDA_ECC_SG_REG_RDA_RXD_ERR(n) vxge_mBIT(n) ++/*0x00aa8*/ u64 rda_ecc_sg_mask; ++/*0x00ab0*/ u64 rda_ecc_sg_alarm; ++/*0x00ab8*/ u64 rqa_err_reg; ++#define VXGE_HW_RQA_ERR_REG_RQA_SM_ERR_ALARM vxge_mBIT(0) ++/*0x00ac0*/ u64 rqa_err_mask; ++/*0x00ac8*/ u64 rqa_err_alarm; ++/*0x00ad0*/ u64 frf_alarm_reg; ++#define VXGE_HW_FRF_ALARM_REG_PRC_VP_FRF_SM_ERR(n) vxge_mBIT(n) ++/*0x00ad8*/ u64 frf_alarm_mask; ++/*0x00ae0*/ u64 frf_alarm_alarm; ++/*0x00ae8*/ u64 rocrc_alarm_reg; ++#define VXGE_HW_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_DB vxge_mBIT(0) ++#define VXGE_HW_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_SG vxge_mBIT(1) ++#define VXGE_HW_ROCRC_ALARM_REG_NOA_NMA_SM_ERR vxge_mBIT(2) ++#define VXGE_HW_ROCRC_ALARM_REG_NOA_IMMM_ECC_DB vxge_mBIT(3) ++#define VXGE_HW_ROCRC_ALARM_REG_NOA_IMMM_ECC_SG vxge_mBIT(4) ++#define VXGE_HW_ROCRC_ALARM_REG_UDQ_UMQM_ECC_DB vxge_mBIT(5) ++#define VXGE_HW_ROCRC_ALARM_REG_UDQ_UMQM_ECC_SG vxge_mBIT(6) ++#define VXGE_HW_ROCRC_ALARM_REG_NOA_RCBM_ECC_DB vxge_mBIT(11) ++#define VXGE_HW_ROCRC_ALARM_REG_NOA_RCBM_ECC_SG vxge_mBIT(12) ++#define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_EGB_RSVD_ERR vxge_mBIT(13) ++#define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_EGB_OWN_ERR vxge_mBIT(14) ++#define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_BYP_OWN_ERR vxge_mBIT(15) ++#define VXGE_HW_ROCRC_ALARM_REG_QCQ_OWN_NOT_ASSIGNED_ERR vxge_mBIT(16) ++#define VXGE_HW_ROCRC_ALARM_REG_QCQ_OWN_RSVD_SYNC_ERR vxge_mBIT(17) ++#define VXGE_HW_ROCRC_ALARM_REG_QCQ_LOST_EGB_ERR vxge_mBIT(18) ++#define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ0_OVERFLOW vxge_mBIT(19) ++#define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ1_OVERFLOW vxge_mBIT(20) ++#define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ2_OVERFLOW vxge_mBIT(21) ++#define VXGE_HW_ROCRC_ALARM_REG_NOA_WCT_CMD_FIFO_ERR vxge_mBIT(22) ++/*0x00af0*/ u64 rocrc_alarm_mask; ++/*0x00af8*/ u64 rocrc_alarm_alarm; ++/*0x00b00*/ u64 wde0_alarm_reg; ++#define VXGE_HW_WDE0_ALARM_REG_WDE0_DCC_SM_ERR vxge_mBIT(0) ++#define VXGE_HW_WDE0_ALARM_REG_WDE0_PRM_SM_ERR vxge_mBIT(1) ++#define VXGE_HW_WDE0_ALARM_REG_WDE0_CP_SM_ERR vxge_mBIT(2) ++#define VXGE_HW_WDE0_ALARM_REG_WDE0_CP_CMD_ERR vxge_mBIT(3) ++#define VXGE_HW_WDE0_ALARM_REG_WDE0_PCR_SM_ERR vxge_mBIT(4) ++/*0x00b08*/ u64 wde0_alarm_mask; ++/*0x00b10*/ u64 wde0_alarm_alarm; ++/*0x00b18*/ u64 wde1_alarm_reg; ++#define VXGE_HW_WDE1_ALARM_REG_WDE1_DCC_SM_ERR vxge_mBIT(0) ++#define VXGE_HW_WDE1_ALARM_REG_WDE1_PRM_SM_ERR vxge_mBIT(1) ++#define VXGE_HW_WDE1_ALARM_REG_WDE1_CP_SM_ERR vxge_mBIT(2) ++#define VXGE_HW_WDE1_ALARM_REG_WDE1_CP_CMD_ERR vxge_mBIT(3) ++#define VXGE_HW_WDE1_ALARM_REG_WDE1_PCR_SM_ERR vxge_mBIT(4) ++/*0x00b20*/ u64 wde1_alarm_mask; ++/*0x00b28*/ u64 wde1_alarm_alarm; ++/*0x00b30*/ u64 wde2_alarm_reg; ++#define VXGE_HW_WDE2_ALARM_REG_WDE2_DCC_SM_ERR vxge_mBIT(0) ++#define VXGE_HW_WDE2_ALARM_REG_WDE2_PRM_SM_ERR vxge_mBIT(1) ++#define VXGE_HW_WDE2_ALARM_REG_WDE2_CP_SM_ERR vxge_mBIT(2) ++#define VXGE_HW_WDE2_ALARM_REG_WDE2_CP_CMD_ERR vxge_mBIT(3) ++#define VXGE_HW_WDE2_ALARM_REG_WDE2_PCR_SM_ERR vxge_mBIT(4) ++/*0x00b38*/ u64 wde2_alarm_mask; ++/*0x00b40*/ u64 wde2_alarm_alarm; ++/*0x00b48*/ u64 wde3_alarm_reg; ++#define VXGE_HW_WDE3_ALARM_REG_WDE3_DCC_SM_ERR vxge_mBIT(0) ++#define VXGE_HW_WDE3_ALARM_REG_WDE3_PRM_SM_ERR vxge_mBIT(1) ++#define VXGE_HW_WDE3_ALARM_REG_WDE3_CP_SM_ERR vxge_mBIT(2) ++#define VXGE_HW_WDE3_ALARM_REG_WDE3_CP_CMD_ERR vxge_mBIT(3) ++#define VXGE_HW_WDE3_ALARM_REG_WDE3_PCR_SM_ERR vxge_mBIT(4) ++/*0x00b50*/ u64 wde3_alarm_mask; ++/*0x00b58*/ u64 wde3_alarm_alarm; ++ ++ u8 unused00be8[0x00be8-0x00b60]; ++ ++/*0x00be8*/ u64 rx_w_round_robin_0; ++#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(val) vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2(val) vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3(val) vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4(val) vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5(val) vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6(val) vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7(val) vxge_vBIT(val, 59, 5) ++/*0x00bf0*/ u64 rx_w_round_robin_1; ++#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_8(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_9(val) vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_10(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_11(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_12(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_13(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_14(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_15(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00bf8*/ u64 rx_w_round_robin_2; ++#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_16(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_17(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_18(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_19(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_20(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_21(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_22(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_23(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c00*/ u64 rx_w_round_robin_3; ++#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_24(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_25(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_26(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_27(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_28(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_29(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_30(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_31(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c08*/ u64 rx_w_round_robin_4; ++#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_32(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_33(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_34(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_35(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_36(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_37(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_38(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_39(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c10*/ u64 rx_w_round_robin_5; ++#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_40(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_41(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_42(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_43(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_44(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_45(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_46(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_47(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c18*/ u64 rx_w_round_robin_6; ++#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_48(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_49(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_50(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_51(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_52(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_53(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_54(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_55(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c20*/ u64 rx_w_round_robin_7; ++#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_56(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_57(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_58(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_59(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_60(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_61(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_62(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_63(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c28*/ u64 rx_w_round_robin_8; ++#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_64(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_65(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_66(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_67(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_68(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_69(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_70(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_71(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c30*/ u64 rx_w_round_robin_9; ++#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_72(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_73(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_74(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_75(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_76(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_77(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_78(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_79(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c38*/ u64 rx_w_round_robin_10; ++#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_80(val) \ ++ vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_81(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_82(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_83(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_84(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_85(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_86(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_87(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c40*/ u64 rx_w_round_robin_11; ++#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_88(val) \ ++ vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_89(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_90(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_91(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_92(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_93(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_94(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_95(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c48*/ u64 rx_w_round_robin_12; ++#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_96(val) \ ++ vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_97(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_98(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_99(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_100(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_101(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_102(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_103(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c50*/ u64 rx_w_round_robin_13; ++#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_104(val) \ ++ vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_105(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_106(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_107(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_108(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_109(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_110(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_111(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c58*/ u64 rx_w_round_robin_14; ++#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_112(val) \ ++ vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_113(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_114(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_115(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_116(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_117(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_118(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_119(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c60*/ u64 rx_w_round_robin_15; ++#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_120(val) \ ++ vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_121(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_122(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_123(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_124(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_125(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_126(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_127(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c68*/ u64 rx_w_round_robin_16; ++#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_128(val) \ ++ vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_129(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_130(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_131(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_132(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_133(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_134(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_135(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c70*/ u64 rx_w_round_robin_17; ++#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_136(val) \ ++ vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_137(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_138(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_139(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_140(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_141(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_142(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_143(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c78*/ u64 rx_w_round_robin_18; ++#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_144(val) \ ++ vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_145(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_146(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_147(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_148(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_149(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_150(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_151(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c80*/ u64 rx_w_round_robin_19; ++#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_152(val) \ ++ vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_153(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_154(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_155(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_156(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_157(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_158(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_159(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c88*/ u64 rx_w_round_robin_20; ++#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_160(val) \ ++ vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_161(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_162(val) \ ++ vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_163(val) \ ++ vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_164(val) \ ++ vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_165(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_166(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_167(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00c90*/ u64 rx_w_round_robin_21; ++#define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_168(val) \ ++ vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_169(val) \ ++ vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_170(val) \ ++ vxge_vBIT(val, 19, 5) ++ ++#define VXGE_HW_WRR_RING_SERVICE_STATES 171 ++#define VXGE_HW_WRR_RING_COUNT 22 ++ ++/*0x00c98*/ u64 rx_queue_priority_0; ++#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(val) vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2(val) vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3(val) vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4(val) vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5(val) vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6(val) vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7(val) vxge_vBIT(val, 59, 5) ++/*0x00ca0*/ u64 rx_queue_priority_1; ++#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(val) vxge_vBIT(val, 11, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10(val) vxge_vBIT(val, 19, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11(val) vxge_vBIT(val, 27, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12(val) vxge_vBIT(val, 35, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13(val) vxge_vBIT(val, 43, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14(val) vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15(val) vxge_vBIT(val, 59, 5) ++/*0x00ca8*/ u64 rx_queue_priority_2; ++#define VXGE_HW_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16(val) vxge_vBIT(val, 3, 5) ++ u8 unused00cc8[0x00cc8-0x00cb0]; ++ ++/*0x00cc8*/ u64 replication_queue_priority; ++#define VXGE_HW_REPLICATION_QUEUE_PRIORITY_REPLICATION_QUEUE_PRIORITY(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00cd0*/ u64 rx_queue_select; ++#define VXGE_HW_RX_QUEUE_SELECT_NUMBER(n) vxge_mBIT(n) ++#define VXGE_HW_RX_QUEUE_SELECT_ENABLE_CODE vxge_mBIT(15) ++#define VXGE_HW_RX_QUEUE_SELECT_ENABLE_HIERARCHICAL_PRTY vxge_mBIT(23) ++/*0x00cd8*/ u64 rqa_vpbp_ctrl; ++#define VXGE_HW_RQA_VPBP_CTRL_WR_XON_DIS vxge_mBIT(15) ++#define VXGE_HW_RQA_VPBP_CTRL_ROCRC_DIS vxge_mBIT(23) ++#define VXGE_HW_RQA_VPBP_CTRL_TXPE_DIS vxge_mBIT(31) ++/*0x00ce0*/ u64 rx_multi_cast_ctrl; ++#define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_DIS vxge_mBIT(0) ++#define VXGE_HW_RX_MULTI_CAST_CTRL_FRM_DROP_DIS vxge_mBIT(1) ++#define VXGE_HW_RX_MULTI_CAST_CTRL_NO_RXD_TIME_OUT_CNT(val) \ ++ vxge_vBIT(val, 2, 30) ++#define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val) vxge_vBIT(val, 32, 32) ++/*0x00ce8*/ u64 wde_prm_ctrl; ++#define VXGE_HW_WDE_PRM_CTRL_SPAV_THRESHOLD(val) vxge_vBIT(val, 2, 10) ++#define VXGE_HW_WDE_PRM_CTRL_SPLIT_THRESHOLD(val) vxge_vBIT(val, 18, 14) ++#define VXGE_HW_WDE_PRM_CTRL_SPLIT_ON_1ST_ROW vxge_mBIT(32) ++#define VXGE_HW_WDE_PRM_CTRL_SPLIT_ON_ROW_BNDRY vxge_mBIT(33) ++#define VXGE_HW_WDE_PRM_CTRL_FB_ROW_SIZE(val) vxge_vBIT(val, 46, 2) ++/*0x00cf0*/ u64 noa_ctrl; ++#define VXGE_HW_NOA_CTRL_FRM_PRTY_QUOTA(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_NOA_CTRL_NON_FRM_PRTY_QUOTA(val) vxge_vBIT(val, 11, 5) ++#define VXGE_HW_NOA_CTRL_IGNORE_KDFC_IF_STATUS vxge_mBIT(16) ++#define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE0(val) vxge_vBIT(val, 37, 4) ++#define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE1(val) vxge_vBIT(val, 45, 4) ++#define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE2(val) vxge_vBIT(val, 53, 4) ++#define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE3(val) vxge_vBIT(val, 60, 4) ++/*0x00cf8*/ u64 phase_cfg; ++#define VXGE_HW_PHASE_CFG_QCC_WR_PHASE_EN vxge_mBIT(0) ++#define VXGE_HW_PHASE_CFG_QCC_RD_PHASE_EN vxge_mBIT(3) ++#define VXGE_HW_PHASE_CFG_IMMM_WR_PHASE_EN vxge_mBIT(7) ++#define VXGE_HW_PHASE_CFG_IMMM_RD_PHASE_EN vxge_mBIT(11) ++#define VXGE_HW_PHASE_CFG_UMQM_WR_PHASE_EN vxge_mBIT(15) ++#define VXGE_HW_PHASE_CFG_UMQM_RD_PHASE_EN vxge_mBIT(19) ++#define VXGE_HW_PHASE_CFG_RCBM_WR_PHASE_EN vxge_mBIT(23) ++#define VXGE_HW_PHASE_CFG_RCBM_RD_PHASE_EN vxge_mBIT(27) ++#define VXGE_HW_PHASE_CFG_RXD_RC_WR_PHASE_EN vxge_mBIT(31) ++#define VXGE_HW_PHASE_CFG_RXD_RC_RD_PHASE_EN vxge_mBIT(35) ++#define VXGE_HW_PHASE_CFG_RXD_RHS_WR_PHASE_EN vxge_mBIT(39) ++#define VXGE_HW_PHASE_CFG_RXD_RHS_RD_PHASE_EN vxge_mBIT(43) ++/*0x00d00*/ u64 rcq_bypq_cfg; ++#define VXGE_HW_RCQ_BYPQ_CFG_OVERFLOW_THRESHOLD(val) vxge_vBIT(val, 10, 22) ++#define VXGE_HW_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD(val) vxge_vBIT(val, 39, 9) ++#define VXGE_HW_RCQ_BYPQ_CFG_BYP_OFF_THRESHOLD(val) vxge_vBIT(val, 55, 9) ++ u8 unused00e00[0x00e00-0x00d08]; ++ ++/*0x00e00*/ u64 doorbell_int_status; ++#define VXGE_HW_DOORBELL_INT_STATUS_KDFC_ERR_REG_TXDMA_KDFC_INT vxge_mBIT(7) ++#define VXGE_HW_DOORBELL_INT_STATUS_USDC_ERR_REG_TXDMA_USDC_INT vxge_mBIT(15) ++/*0x00e08*/ u64 doorbell_int_mask; ++/*0x00e10*/ u64 kdfc_err_reg; ++#define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_ECC_SG_ERR vxge_mBIT(7) ++#define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_ECC_DB_ERR vxge_mBIT(15) ++#define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_SM_ERR_ALARM vxge_mBIT(23) ++#define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_MISC_ERR_1 vxge_mBIT(32) ++#define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_PCIX_ERR vxge_mBIT(39) ++/*0x00e18*/ u64 kdfc_err_mask; ++/*0x00e20*/ u64 kdfc_err_reg_alarm; ++#define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_SG_ERR vxge_mBIT(7) ++#define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_DB_ERR vxge_mBIT(15) ++#define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_SM_ERR_ALARM vxge_mBIT(23) ++#define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_MISC_ERR_1 vxge_mBIT(32) ++#define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_PCIX_ERR vxge_mBIT(39) ++ u8 unused00e40[0x00e40-0x00e28]; ++/*0x00e40*/ u64 kdfc_vp_partition_0; ++#define VXGE_HW_KDFC_VP_PARTITION_0_ENABLE vxge_mBIT(0) ++#define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_0(val) vxge_vBIT(val, 5, 3) ++#define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_0(val) vxge_vBIT(val, 17, 15) ++#define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_1(val) vxge_vBIT(val, 37, 3) ++#define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_1(val) vxge_vBIT(val, 49, 15) ++/*0x00e48*/ u64 kdfc_vp_partition_1; ++#define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_2(val) vxge_vBIT(val, 5, 3) ++#define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_2(val) vxge_vBIT(val, 17, 15) ++#define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_3(val) vxge_vBIT(val, 37, 3) ++#define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_3(val) vxge_vBIT(val, 49, 15) ++/*0x00e50*/ u64 kdfc_vp_partition_2; ++#define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_4(val) vxge_vBIT(val, 5, 3) ++#define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_4(val) vxge_vBIT(val, 17, 15) ++#define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_5(val) vxge_vBIT(val, 37, 3) ++#define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_5(val) vxge_vBIT(val, 49, 15) ++/*0x00e58*/ u64 kdfc_vp_partition_3; ++#define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_6(val) vxge_vBIT(val, 5, 3) ++#define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_6(val) vxge_vBIT(val, 17, 15) ++#define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_7(val) vxge_vBIT(val, 37, 3) ++#define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_7(val) vxge_vBIT(val, 49, 15) ++/*0x00e60*/ u64 kdfc_vp_partition_4; ++#define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_8(val) vxge_vBIT(val, 17, 15) ++#define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_9(val) vxge_vBIT(val, 49, 15) ++/*0x00e68*/ u64 kdfc_vp_partition_5; ++#define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_10(val) vxge_vBIT(val, 17, 15) ++#define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_11(val) vxge_vBIT(val, 49, 15) ++/*0x00e70*/ u64 kdfc_vp_partition_6; ++#define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_12(val) vxge_vBIT(val, 17, 15) ++#define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_13(val) vxge_vBIT(val, 49, 15) ++/*0x00e78*/ u64 kdfc_vp_partition_7; ++#define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_14(val) vxge_vBIT(val, 17, 15) ++#define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_15(val) vxge_vBIT(val, 49, 15) ++/*0x00e80*/ u64 kdfc_vp_partition_8; ++#define VXGE_HW_KDFC_VP_PARTITION_8_LENGTH_16(val) vxge_vBIT(val, 17, 15) ++/*0x00e88*/ u64 kdfc_w_round_robin_0; ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_0(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_1(val) vxge_vBIT(val, 11, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_2(val) vxge_vBIT(val, 19, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_3(val) vxge_vBIT(val, 27, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_4(val) vxge_vBIT(val, 35, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_5(val) vxge_vBIT(val, 43, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_6(val) vxge_vBIT(val, 51, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_7(val) vxge_vBIT(val, 59, 5) ++ ++ u8 unused0f28[0x0f28-0x0e90]; ++ ++/*0x00f28*/ u64 kdfc_w_round_robin_20; ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_0(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_1(val) vxge_vBIT(val, 11, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_2(val) vxge_vBIT(val, 19, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_3(val) vxge_vBIT(val, 27, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_4(val) vxge_vBIT(val, 35, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_5(val) vxge_vBIT(val, 43, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_6(val) vxge_vBIT(val, 51, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_7(val) vxge_vBIT(val, 59, 5) ++ ++#define VXGE_HW_WRR_FIFO_COUNT 20 ++ ++ u8 unused0fc8[0x0fc8-0x0f30]; ++ ++/*0x00fc8*/ u64 kdfc_w_round_robin_40; ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_0(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_1(val) vxge_vBIT(val, 11, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_2(val) vxge_vBIT(val, 19, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_3(val) vxge_vBIT(val, 27, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_4(val) vxge_vBIT(val, 35, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_5(val) vxge_vBIT(val, 43, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_6(val) vxge_vBIT(val, 51, 5) ++#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_7(val) vxge_vBIT(val, 59, 5) ++ ++ u8 unused1068[0x01068-0x0fd0]; ++ ++/*0x01068*/ u64 kdfc_entry_type_sel_0; ++#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0(val) vxge_vBIT(val, 6, 2) ++#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(val) vxge_vBIT(val, 14, 2) ++#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2(val) vxge_vBIT(val, 22, 2) ++#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3(val) vxge_vBIT(val, 30, 2) ++#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4(val) vxge_vBIT(val, 38, 2) ++#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5(val) vxge_vBIT(val, 46, 2) ++#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6(val) vxge_vBIT(val, 54, 2) ++#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7(val) vxge_vBIT(val, 62, 2) ++/*0x01070*/ u64 kdfc_entry_type_sel_1; ++#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8(val) vxge_vBIT(val, 6, 2) ++/*0x01078*/ u64 kdfc_fifo_0_ctrl; ++#define VXGE_HW_KDFC_FIFO_0_CTRL_WRR_NUMBER(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_WEIGHTED_RR_SERVICE_STATES 176 ++#define VXGE_HW_WRR_FIFO_SERVICE_STATES 153 ++ ++ u8 unused1100[0x01100-0x1080]; ++ ++/*0x01100*/ u64 kdfc_fifo_17_ctrl; ++#define VXGE_HW_KDFC_FIFO_17_CTRL_WRR_NUMBER(val) vxge_vBIT(val, 3, 5) ++ ++ u8 unused1600[0x01600-0x1108]; ++ ++/*0x01600*/ u64 rxmac_int_status; ++#define VXGE_HW_RXMAC_INT_STATUS_RXMAC_GEN_ERR_RXMAC_GEN_INT vxge_mBIT(3) ++#define VXGE_HW_RXMAC_INT_STATUS_RXMAC_ECC_ERR_RXMAC_ECC_INT vxge_mBIT(7) ++#define VXGE_HW_RXMAC_INT_STATUS_RXMAC_VARIOUS_ERR_RXMAC_VARIOUS_INT \ ++ vxge_mBIT(11) ++/*0x01608*/ u64 rxmac_int_mask; ++ u8 unused01618[0x01618-0x01610]; ++ ++/*0x01618*/ u64 rxmac_gen_err_reg; ++/*0x01620*/ u64 rxmac_gen_err_mask; ++/*0x01628*/ u64 rxmac_gen_err_alarm; ++/*0x01630*/ u64 rxmac_ecc_err_reg; ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_SG_ERR(val) \ ++ vxge_vBIT(val, 0, 4) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(val) \ ++ vxge_vBIT(val, 4, 4) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_SG_ERR(val) \ ++ vxge_vBIT(val, 8, 4) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(val) \ ++ vxge_vBIT(val, 12, 4) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_SG_ERR(val) \ ++ vxge_vBIT(val, 16, 4) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(val) \ ++ vxge_vBIT(val, 20, 4) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_SG_ERR(val) \ ++ vxge_vBIT(val, 24, 2) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(val) \ ++ vxge_vBIT(val, 26, 2) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_SG_ERR(val) \ ++ vxge_vBIT(val, 28, 2) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(val) \ ++ vxge_vBIT(val, 30, 2) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_SG_ERR vxge_mBIT(32) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_DB_ERR vxge_mBIT(33) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_SG_ERR vxge_mBIT(34) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_DB_ERR vxge_mBIT(35) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_SG_ERR vxge_mBIT(36) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_DB_ERR vxge_mBIT(37) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_SG_ERR vxge_mBIT(38) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_DB_ERR vxge_mBIT(39) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_SG_ERR(val) \ ++ vxge_vBIT(val, 40, 7) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(val) \ ++ vxge_vBIT(val, 47, 7) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_SG_ERR(val) \ ++ vxge_vBIT(val, 54, 3) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(val) \ ++ vxge_vBIT(val, 57, 3) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_SG_ERR \ ++ vxge_mBIT(60) ++#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_DB_ERR \ ++ vxge_mBIT(61) ++/*0x01638*/ u64 rxmac_ecc_err_mask; ++/*0x01640*/ u64 rxmac_ecc_err_alarm; ++/*0x01648*/ u64 rxmac_various_err_reg; ++#define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT0_FSM_ERR vxge_mBIT(0) ++#define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT1_FSM_ERR vxge_mBIT(1) ++#define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT2_FSM_ERR vxge_mBIT(2) ++#define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMACJ_RMACJ_FSM_ERR vxge_mBIT(3) ++/*0x01650*/ u64 rxmac_various_err_mask; ++/*0x01658*/ u64 rxmac_various_err_alarm; ++/*0x01660*/ u64 rxmac_gen_cfg; ++#define VXGE_HW_RXMAC_GEN_CFG_SCALE_RMAC_UTIL vxge_mBIT(11) ++/*0x01668*/ u64 rxmac_authorize_all_addr; ++#define VXGE_HW_RXMAC_AUTHORIZE_ALL_ADDR_VP(n) vxge_mBIT(n) ++/*0x01670*/ u64 rxmac_authorize_all_vid; ++#define VXGE_HW_RXMAC_AUTHORIZE_ALL_VID_VP(n) vxge_mBIT(n) ++ u8 unused016c0[0x016c0-0x01678]; ++ ++/*0x016c0*/ u64 rxmac_red_rate_repl_queue; ++#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR0(val) vxge_vBIT(val, 0, 4) ++#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR1(val) vxge_vBIT(val, 4, 4) ++#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR2(val) vxge_vBIT(val, 8, 4) ++#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR3(val) vxge_vBIT(val, 12, 4) ++#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR0(val) vxge_vBIT(val, 16, 4) ++#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR1(val) vxge_vBIT(val, 20, 4) ++#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR2(val) vxge_vBIT(val, 24, 4) ++#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR3(val) vxge_vBIT(val, 28, 4) ++#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_TRICKLE_EN vxge_mBIT(35) ++ u8 unused016e0[0x016e0-0x016c8]; ++ ++/*0x016e0*/ u64 rxmac_cfg0_port[3]; ++#define VXGE_HW_RXMAC_CFG0_PORT_RMAC_EN vxge_mBIT(3) ++#define VXGE_HW_RXMAC_CFG0_PORT_STRIP_FCS vxge_mBIT(7) ++#define VXGE_HW_RXMAC_CFG0_PORT_DISCARD_PFRM vxge_mBIT(11) ++#define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_FCS_ERR vxge_mBIT(15) ++#define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_LONG_ERR vxge_mBIT(19) ++#define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_USIZED_ERR vxge_mBIT(23) ++#define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_LEN_MISMATCH vxge_mBIT(27) ++#define VXGE_HW_RXMAC_CFG0_PORT_MAX_PYLD_LEN(val) vxge_vBIT(val, 50, 14) ++ u8 unused01710[0x01710-0x016f8]; ++ ++/*0x01710*/ u64 rxmac_cfg2_port[3]; ++#define VXGE_HW_RXMAC_CFG2_PORT_PROM_EN vxge_mBIT(3) ++/*0x01728*/ u64 rxmac_pause_cfg_port[3]; ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN vxge_mBIT(3) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN vxge_mBIT(7) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_ACCEL_SEND(val) vxge_vBIT(val, 9, 3) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_DUAL_THR vxge_mBIT(15) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(val) vxge_vBIT(val, 20, 16) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_FCS_ERR vxge_mBIT(39) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_LEN_ERR vxge_mBIT(43) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_LIMITER_EN vxge_mBIT(47) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(val) vxge_vBIT(val, 48, 8) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_PERMIT_RATEMGMT_CTRL vxge_mBIT(59) ++ u8 unused01758[0x01758-0x01740]; ++ ++/*0x01758*/ u64 rxmac_red_cfg0_port[3]; ++#define VXGE_HW_RXMAC_RED_CFG0_PORT_RED_EN_VP(n) vxge_mBIT(n) ++/*0x01770*/ u64 rxmac_red_cfg1_port[3]; ++#define VXGE_HW_RXMAC_RED_CFG1_PORT_FINE_EN vxge_mBIT(3) ++#define VXGE_HW_RXMAC_RED_CFG1_PORT_RED_EN_REPL_QUEUE vxge_mBIT(11) ++/*0x01788*/ u64 rxmac_red_cfg2_port[3]; ++#define VXGE_HW_RXMAC_RED_CFG2_PORT_TRICKLE_EN_VP(n) vxge_mBIT(n) ++/*0x017a0*/ u64 rxmac_link_util_port[3]; ++#define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_UTILIZATION(val) \ ++ vxge_vBIT(val, 1, 7) ++#define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(val) vxge_vBIT(val, 8, 4) ++#define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_FRAC_UTIL(val) \ ++ vxge_vBIT(val, 12, 4) ++#define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_PKT_WEIGHT(val) vxge_vBIT(val, 16, 4) ++#define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_SCALE_FACTOR vxge_mBIT(23) ++ u8 unused017d0[0x017d0-0x017b8]; ++ ++/*0x017d0*/ u64 rxmac_status_port[3]; ++#define VXGE_HW_RXMAC_STATUS_PORT_RMAC_RX_FRM_RCVD vxge_mBIT(3) ++ u8 unused01800[0x01800-0x017e8]; ++ ++/*0x01800*/ u64 rxmac_rx_pa_cfg0; ++#define VXGE_HW_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR vxge_mBIT(3) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N vxge_mBIT(7) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO vxge_mBIT(18) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS vxge_mBIT(19) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING vxge_mBIT(23) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN vxge_mBIT(27) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE vxge_mBIT(35) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L3_CSUM_ERR vxge_mBIT(39) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR vxge_mBIT(43) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L4_CSUM_ERR vxge_mBIT(47) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR vxge_mBIT(51) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_RPA_ERR vxge_mBIT(55) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_RPA_ERR vxge_mBIT(59) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_JUMBO_SNAP_EN vxge_mBIT(63) ++/*0x01808*/ u64 rxmac_rx_pa_cfg1; ++#define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH vxge_mBIT(3) ++#define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH vxge_mBIT(7) ++#define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH vxge_mBIT(11) ++#define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH vxge_mBIT(15) ++#define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF vxge_mBIT(19) ++#define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG vxge_mBIT(23) ++ u8 unused01828[0x01828-0x01810]; ++ ++/*0x01828*/ u64 rts_mgr_cfg0; ++#define VXGE_HW_RTS_MGR_CFG0_RTS_DP_SP_PRIORITY vxge_mBIT(3) ++#define VXGE_HW_RTS_MGR_CFG0_FLEX_L4PRTCL_VALUE(val) vxge_vBIT(val, 24, 8) ++#define VXGE_HW_RTS_MGR_CFG0_ICMP_TRASH vxge_mBIT(35) ++#define VXGE_HW_RTS_MGR_CFG0_TCPSYN_TRASH vxge_mBIT(39) ++#define VXGE_HW_RTS_MGR_CFG0_ZL4PYLD_TRASH vxge_mBIT(43) ++#define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_TCP_TRASH vxge_mBIT(47) ++#define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_UDP_TRASH vxge_mBIT(51) ++#define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_FLEX_TRASH vxge_mBIT(55) ++#define VXGE_HW_RTS_MGR_CFG0_IPFRAG_TRASH vxge_mBIT(59) ++/*0x01830*/ u64 rts_mgr_cfg1; ++#define VXGE_HW_RTS_MGR_CFG1_DA_ACTIVE_TABLE vxge_mBIT(3) ++#define VXGE_HW_RTS_MGR_CFG1_PN_ACTIVE_TABLE vxge_mBIT(7) ++/*0x01838*/ u64 rts_mgr_criteria_priority; ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ETYPE(val) vxge_vBIT(val, 5, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN(val) vxge_vBIT(val, 9, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PN(val) vxge_vBIT(val, 13, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RANGE_L4PN(val) vxge_vBIT(val, 17, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RTH_IT(val) vxge_vBIT(val, 21, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_DS(val) vxge_vBIT(val, 25, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_QOS(val) vxge_vBIT(val, 29, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ZL4PYLD(val) vxge_vBIT(val, 33, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PRTCL(val) vxge_vBIT(val, 37, 3) ++/*0x01840*/ u64 rts_mgr_da_pause_cfg; ++#define VXGE_HW_RTS_MGR_DA_PAUSE_CFG_VPATH_VECTOR(val) vxge_vBIT(val, 0, 17) ++/*0x01848*/ u64 rts_mgr_da_slow_proto_cfg; ++#define VXGE_HW_RTS_MGR_DA_SLOW_PROTO_CFG_VPATH_VECTOR(val) \ ++ vxge_vBIT(val, 0, 17) ++ u8 unused01890[0x01890-0x01850]; ++/*0x01890*/ u64 rts_mgr_cbasin_cfg; ++ u8 unused01968[0x01968-0x01898]; ++ ++/*0x01968*/ u64 dbg_stat_rx_any_frms; ++#define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT0_RX_ANY_FRMS(val) vxge_vBIT(val, 0, 8) ++#define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT1_RX_ANY_FRMS(val) vxge_vBIT(val, 8, 8) ++#define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT2_RX_ANY_FRMS(val) \ ++ vxge_vBIT(val, 16, 8) ++ u8 unused01a00[0x01a00-0x01970]; ++ ++/*0x01a00*/ u64 rxmac_red_rate_vp[17]; ++#define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR0(val) vxge_vBIT(val, 0, 4) ++#define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR1(val) vxge_vBIT(val, 4, 4) ++#define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR2(val) vxge_vBIT(val, 8, 4) ++#define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR3(val) vxge_vBIT(val, 12, 4) ++#define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR0(val) vxge_vBIT(val, 16, 4) ++#define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR1(val) vxge_vBIT(val, 20, 4) ++#define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR2(val) vxge_vBIT(val, 24, 4) ++#define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR3(val) vxge_vBIT(val, 28, 4) ++ u8 unused01e00[0x01e00-0x01a88]; ++ ++/*0x01e00*/ u64 xgmac_int_status; ++#define VXGE_HW_XGMAC_INT_STATUS_XMAC_GEN_ERR_XMAC_GEN_INT vxge_mBIT(3) ++#define VXGE_HW_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT0_XMAC_LINK_INT_PORT0 \ ++ vxge_mBIT(7) ++#define VXGE_HW_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT1_XMAC_LINK_INT_PORT1 \ ++ vxge_mBIT(11) ++#define VXGE_HW_XGMAC_INT_STATUS_XGXS_GEN_ERR_XGXS_GEN_INT vxge_mBIT(15) ++#define VXGE_HW_XGMAC_INT_STATUS_ASIC_NTWK_ERR_ASIC_NTWK_INT vxge_mBIT(19) ++#define VXGE_HW_XGMAC_INT_STATUS_ASIC_GPIO_ERR_ASIC_GPIO_INT vxge_mBIT(23) ++/*0x01e08*/ u64 xgmac_int_mask; ++/*0x01e10*/ u64 xmac_gen_err_reg; ++#define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_ACTOR_CHURN_DETECTED \ ++ vxge_mBIT(7) ++#define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_PARTNER_CHURN_DETECTED \ ++ vxge_mBIT(11) ++#define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_RECEIVED_LACPDU vxge_mBIT(15) ++#define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_ACTOR_CHURN_DETECTED \ ++ vxge_mBIT(19) ++#define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_PARTNER_CHURN_DETECTED \ ++ vxge_mBIT(23) ++#define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_RECEIVED_LACPDU vxge_mBIT(27) ++#define VXGE_HW_XMAC_GEN_ERR_REG_XLCM_LAG_FAILOVER_DETECTED vxge_mBIT(31) ++#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_SG_ERR(val) \ ++ vxge_vBIT(val, 40, 2) ++#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(val) \ ++ vxge_vBIT(val, 42, 2) ++#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_SG_ERR(val) \ ++ vxge_vBIT(val, 44, 2) ++#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(val) \ ++ vxge_vBIT(val, 46, 2) ++#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_SG_ERR(val) \ ++ vxge_vBIT(val, 48, 2) ++#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(val) \ ++ vxge_vBIT(val, 50, 2) ++#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_SG_ERR(val) \ ++ vxge_vBIT(val, 52, 2) ++#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(val) \ ++ vxge_vBIT(val, 54, 2) ++#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_SG_ERR(val) \ ++ vxge_vBIT(val, 56, 2) ++#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(val) \ ++ vxge_vBIT(val, 58, 2) ++#define VXGE_HW_XMAC_GEN_ERR_REG_XMACJ_XMAC_FSM_ERR vxge_mBIT(63) ++/*0x01e18*/ u64 xmac_gen_err_mask; ++/*0x01e20*/ u64 xmac_gen_err_alarm; ++/*0x01e28*/ u64 xmac_link_err_port0_reg; ++#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_DOWN vxge_mBIT(3) ++#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_UP vxge_mBIT(7) ++#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_DOWN vxge_mBIT(11) ++#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_UP vxge_mBIT(15) ++#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_FAULT \ ++ vxge_mBIT(19) ++#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_OK vxge_mBIT(23) ++#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_DOWN vxge_mBIT(27) ++#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_UP vxge_mBIT(31) ++#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_RATEMGMT_RATE_CHANGE vxge_mBIT(35) ++#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_RATEMGMT_LASI_INV vxge_mBIT(39) ++#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMDIO_MDIO_MGR_ACCESS_COMPLETE \ ++ vxge_mBIT(47) ++/*0x01e30*/ u64 xmac_link_err_port0_mask; ++/*0x01e38*/ u64 xmac_link_err_port0_alarm; ++/*0x01e40*/ u64 xmac_link_err_port1_reg; ++/*0x01e48*/ u64 xmac_link_err_port1_mask; ++/*0x01e50*/ u64 xmac_link_err_port1_alarm; ++/*0x01e58*/ u64 xgxs_gen_err_reg; ++#define VXGE_HW_XGXS_GEN_ERR_REG_XGXS_XGXS_FSM_ERR vxge_mBIT(63) ++/*0x01e60*/ u64 xgxs_gen_err_mask; ++/*0x01e68*/ u64 xgxs_gen_err_alarm; ++/*0x01e70*/ u64 asic_ntwk_err_reg; ++#define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_DOWN vxge_mBIT(3) ++#define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_UP vxge_mBIT(7) ++#define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_DOWN vxge_mBIT(11) ++#define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_UP vxge_mBIT(15) ++#define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT vxge_mBIT(19) ++#define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK vxge_mBIT(23) ++/*0x01e78*/ u64 asic_ntwk_err_mask; ++/*0x01e80*/ u64 asic_ntwk_err_alarm; ++/*0x01e88*/ u64 asic_gpio_err_reg; ++#define VXGE_HW_ASIC_GPIO_ERR_REG_XMACJ_GPIO_INT(n) vxge_mBIT(n) ++/*0x01e90*/ u64 asic_gpio_err_mask; ++/*0x01e98*/ u64 asic_gpio_err_alarm; ++/*0x01ea0*/ u64 xgmac_gen_status; ++#define VXGE_HW_XGMAC_GEN_STATUS_XMACJ_NTWK_OK vxge_mBIT(3) ++#define VXGE_HW_XGMAC_GEN_STATUS_XMACJ_NTWK_DATA_RATE vxge_mBIT(11) ++/*0x01ea8*/ u64 xgmac_gen_fw_memo_status; ++#define VXGE_HW_XGMAC_GEN_FW_MEMO_STATUS_XMACJ_EVENTS_PENDING(val) \ ++ vxge_vBIT(val, 0, 17) ++/*0x01eb0*/ u64 xgmac_gen_fw_memo_mask; ++#define VXGE_HW_XGMAC_GEN_FW_MEMO_MASK_MASK(val) vxge_vBIT(val, 0, 64) ++/*0x01eb8*/ u64 xgmac_gen_fw_vpath_to_vsport_status; ++#define VXGE_HW_XGMAC_GEN_FW_VPATH_TO_VSPORT_STATUS_XMACJ_EVENTS_PENDING(val) \ ++ vxge_vBIT(val, 0, 17) ++/*0x01ec0*/ u64 xgmac_main_cfg_port[2]; ++#define VXGE_HW_XGMAC_MAIN_CFG_PORT_PORT_EN vxge_mBIT(3) ++ u8 unused01f40[0x01f40-0x01ed0]; ++ ++/*0x01f40*/ u64 xmac_gen_cfg; ++#define VXGE_HW_XMAC_GEN_CFG_RATEMGMT_MAC_RATE_SEL(val) vxge_vBIT(val, 2, 2) ++#define VXGE_HW_XMAC_GEN_CFG_TX_HEAD_DROP_WHEN_FAULT vxge_mBIT(7) ++#define VXGE_HW_XMAC_GEN_CFG_FAULT_BEHAVIOUR vxge_mBIT(27) ++#define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_UP(val) vxge_vBIT(val, 28, 4) ++#define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(val) vxge_vBIT(val, 32, 4) ++/*0x01f48*/ u64 xmac_timestamp; ++#define VXGE_HW_XMAC_TIMESTAMP_EN vxge_mBIT(3) ++#define VXGE_HW_XMAC_TIMESTAMP_USE_LINK_ID(val) vxge_vBIT(val, 6, 2) ++#define VXGE_HW_XMAC_TIMESTAMP_INTERVAL(val) vxge_vBIT(val, 12, 4) ++#define VXGE_HW_XMAC_TIMESTAMP_TIMER_RESTART vxge_mBIT(19) ++#define VXGE_HW_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT(val) vxge_vBIT(val, 32, 16) ++/*0x01f50*/ u64 xmac_stats_gen_cfg; ++#define VXGE_HW_XMAC_STATS_GEN_CFG_PRTAGGR_CUM_TIMER(val) vxge_vBIT(val, 4, 4) ++#define VXGE_HW_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER(val) vxge_vBIT(val, 8, 4) ++#define VXGE_HW_XMAC_STATS_GEN_CFG_VLAN_HANDLING vxge_mBIT(15) ++/*0x01f58*/ u64 xmac_stats_sys_cmd; ++#define VXGE_HW_XMAC_STATS_SYS_CMD_OP(val) vxge_vBIT(val, 5, 3) ++#define VXGE_HW_XMAC_STATS_SYS_CMD_STROBE vxge_mBIT(15) ++#define VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(val) vxge_vBIT(val, 27, 5) ++#define VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8) ++/*0x01f60*/ u64 xmac_stats_sys_data; ++#define VXGE_HW_XMAC_STATS_SYS_DATA_XSMGR_DATA(val) vxge_vBIT(val, 0, 64) ++ u8 unused01f80[0x01f80-0x01f68]; ++ ++/*0x01f80*/ u64 asic_ntwk_ctrl; ++#define VXGE_HW_ASIC_NTWK_CTRL_REQ_TEST_NTWK vxge_mBIT(3) ++#define VXGE_HW_ASIC_NTWK_CTRL_PORT0_REQ_TEST_PORT vxge_mBIT(11) ++#define VXGE_HW_ASIC_NTWK_CTRL_PORT1_REQ_TEST_PORT vxge_mBIT(15) ++/*0x01f88*/ u64 asic_ntwk_cfg_show_port_info; ++#define VXGE_HW_ASIC_NTWK_CFG_SHOW_PORT_INFO_VP(n) vxge_mBIT(n) ++/*0x01f90*/ u64 asic_ntwk_cfg_port_num; ++#define VXGE_HW_ASIC_NTWK_CFG_PORT_NUM_VP(n) vxge_mBIT(n) ++/*0x01f98*/ u64 xmac_cfg_port[3]; ++#define VXGE_HW_XMAC_CFG_PORT_XGMII_LOOPBACK vxge_mBIT(3) ++#define VXGE_HW_XMAC_CFG_PORT_XGMII_REVERSE_LOOPBACK vxge_mBIT(7) ++#define VXGE_HW_XMAC_CFG_PORT_XGMII_TX_BEHAV vxge_mBIT(11) ++#define VXGE_HW_XMAC_CFG_PORT_XGMII_RX_BEHAV vxge_mBIT(15) ++/*0x01fb0*/ u64 xmac_station_addr_port[2]; ++#define VXGE_HW_XMAC_STATION_ADDR_PORT_MAC_ADDR(val) vxge_vBIT(val, 0, 48) ++ u8 unused02020[0x02020-0x01fc0]; ++ ++/*0x02020*/ u64 lag_cfg; ++#define VXGE_HW_LAG_CFG_EN vxge_mBIT(3) ++#define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2) ++#define VXGE_HW_LAG_CFG_TX_DISCARD_BEHAV vxge_mBIT(11) ++#define VXGE_HW_LAG_CFG_RX_DISCARD_BEHAV vxge_mBIT(15) ++#define VXGE_HW_LAG_CFG_PREF_INDIV_PORT_NUM vxge_mBIT(19) ++/*0x02028*/ u64 lag_status; ++#define VXGE_HW_LAG_STATUS_XLCM_WAITING_TO_FAILBACK vxge_mBIT(3) ++#define VXGE_HW_LAG_STATUS_XLCM_TIMER_VAL_COLD_FAILOVER(val) \ ++ vxge_vBIT(val, 8, 8) ++/*0x02030*/ u64 lag_active_passive_cfg; ++#define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY vxge_mBIT(3) ++#define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES vxge_mBIT(7) ++#define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM vxge_mBIT(11) ++#define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK vxge_mBIT(15) ++#define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN vxge_mBIT(19) ++#define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(val) \ ++ vxge_vBIT(val, 32, 16) ++ u8 unused02040[0x02040-0x02038]; ++ ++/*0x02040*/ u64 lag_lacp_cfg; ++#define VXGE_HW_LAG_LACP_CFG_EN vxge_mBIT(3) ++#define VXGE_HW_LAG_LACP_CFG_LACP_BEGIN vxge_mBIT(7) ++#define VXGE_HW_LAG_LACP_CFG_DISCARD_LACP vxge_mBIT(11) ++#define VXGE_HW_LAG_LACP_CFG_LIBERAL_LEN_CHK vxge_mBIT(15) ++/*0x02048*/ u64 lag_timer_cfg_1; ++#define VXGE_HW_LAG_TIMER_CFG_1_FAST_PER(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_LAG_TIMER_CFG_1_SLOW_PER(val) vxge_vBIT(val, 16, 16) ++#define VXGE_HW_LAG_TIMER_CFG_1_SHORT_TIMEOUT(val) vxge_vBIT(val, 32, 16) ++#define VXGE_HW_LAG_TIMER_CFG_1_LONG_TIMEOUT(val) vxge_vBIT(val, 48, 16) ++/*0x02050*/ u64 lag_timer_cfg_2; ++#define VXGE_HW_LAG_TIMER_CFG_2_CHURN_DET(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_LAG_TIMER_CFG_2_AGGR_WAIT(val) vxge_vBIT(val, 16, 16) ++#define VXGE_HW_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(val) vxge_vBIT(val, 32, 16) ++#define VXGE_HW_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(val) vxge_vBIT(val, 48, 16) ++/*0x02058*/ u64 lag_sys_id; ++#define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) ++#define VXGE_HW_LAG_SYS_ID_USE_PORT_ADDR vxge_mBIT(51) ++#define VXGE_HW_LAG_SYS_ID_ADDR_SEL vxge_mBIT(55) ++/*0x02060*/ u64 lag_sys_cfg; ++#define VXGE_HW_LAG_SYS_CFG_SYS_PRI(val) vxge_vBIT(val, 0, 16) ++ u8 unused02070[0x02070-0x02068]; ++ ++/*0x02070*/ u64 lag_aggr_addr_cfg[2]; ++#define VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR(val) vxge_vBIT(val, 0, 48) ++#define VXGE_HW_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR vxge_mBIT(51) ++#define VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR_SEL vxge_mBIT(55) ++/*0x02080*/ u64 lag_aggr_id_cfg[2]; ++#define VXGE_HW_LAG_AGGR_ID_CFG_ID(val) vxge_vBIT(val, 0, 16) ++/*0x02090*/ u64 lag_aggr_admin_key[2]; ++#define VXGE_HW_LAG_AGGR_ADMIN_KEY_KEY(val) vxge_vBIT(val, 0, 16) ++/*0x020a0*/ u64 lag_aggr_alt_admin_key; ++#define VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_KEY(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR vxge_mBIT(19) ++/*0x020a8*/ u64 lag_aggr_oper_key[2]; ++#define VXGE_HW_LAG_AGGR_OPER_KEY_LAGC_KEY(val) vxge_vBIT(val, 0, 16) ++/*0x020b8*/ u64 lag_aggr_partner_sys_id[2]; ++#define VXGE_HW_LAG_AGGR_PARTNER_SYS_ID_LAGC_ADDR(val) vxge_vBIT(val, 0, 48) ++/*0x020c8*/ u64 lag_aggr_partner_info[2]; ++#define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_SYS_PRI(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY(val) \ ++ vxge_vBIT(val, 16, 16) ++/*0x020d8*/ u64 lag_aggr_state[2]; ++#define VXGE_HW_LAG_AGGR_STATE_LAGC_TX vxge_mBIT(3) ++#define VXGE_HW_LAG_AGGR_STATE_LAGC_RX vxge_mBIT(7) ++#define VXGE_HW_LAG_AGGR_STATE_LAGC_READY vxge_mBIT(11) ++#define VXGE_HW_LAG_AGGR_STATE_LAGC_INDIVIDUAL vxge_mBIT(15) ++ u8 unused020f0[0x020f0-0x020e8]; ++ ++/*0x020f0*/ u64 lag_port_cfg[2]; ++#define VXGE_HW_LAG_PORT_CFG_EN vxge_mBIT(3) ++#define VXGE_HW_LAG_PORT_CFG_DISCARD_SLOW_PROTO vxge_mBIT(7) ++#define VXGE_HW_LAG_PORT_CFG_HOST_CHOSEN_AGGR vxge_mBIT(11) ++#define VXGE_HW_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO vxge_mBIT(15) ++/*0x02100*/ u64 lag_port_actor_admin_cfg[2]; ++#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(val) vxge_vBIT(val, 16, 16) ++#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(val) vxge_vBIT(val, 32, 16) ++#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(val) vxge_vBIT(val, 48, 16) ++/*0x02110*/ u64 lag_port_actor_admin_state[2]; ++#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY vxge_mBIT(3) ++#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT vxge_mBIT(7) ++#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION vxge_mBIT(11) ++#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION vxge_mBIT(15) ++#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING vxge_mBIT(19) ++#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING vxge_mBIT(23) ++#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED vxge_mBIT(27) ++#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED vxge_mBIT(31) ++/*0x02120*/ u64 lag_port_partner_admin_sys_id[2]; ++#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) ++/*0x02130*/ u64 lag_port_partner_admin_cfg[2]; ++#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_KEY(val) vxge_vBIT(val, 16, 16) ++#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(val) \ ++ vxge_vBIT(val, 32, 16) ++#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(val) \ ++ vxge_vBIT(val, 48, 16) ++/*0x02140*/ u64 lag_port_partner_admin_state[2]; ++#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY vxge_mBIT(3) ++#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT vxge_mBIT(7) ++#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION vxge_mBIT(11) ++#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION vxge_mBIT(15) ++#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING vxge_mBIT(19) ++#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING vxge_mBIT(23) ++#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED vxge_mBIT(27) ++#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED vxge_mBIT(31) ++/*0x02150*/ u64 lag_port_to_aggr[2]; ++#define VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_ID(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_VLD_ID vxge_mBIT(19) ++/*0x02160*/ u64 lag_port_actor_oper_key[2]; ++#define VXGE_HW_LAG_PORT_ACTOR_OPER_KEY_LAGC_KEY(val) vxge_vBIT(val, 0, 16) ++/*0x02170*/ u64 lag_port_actor_oper_state[2]; ++#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_ACTIVITY vxge_mBIT(3) ++#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_TIMEOUT vxge_mBIT(7) ++#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_AGGREGATION vxge_mBIT(11) ++#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_SYNCHRONIZATION vxge_mBIT(15) ++#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_COLLECTING vxge_mBIT(19) ++#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_DISTRIBUTING vxge_mBIT(23) ++#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_DEFAULTED vxge_mBIT(27) ++#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_EXPIRED vxge_mBIT(31) ++/*0x02180*/ u64 lag_port_partner_oper_sys_id[2]; ++#define VXGE_HW_LAG_PORT_PARTNER_OPER_SYS_ID_LAGC_ADDR(val) \ ++ vxge_vBIT(val, 0, 48) ++/*0x02190*/ u64 lag_port_partner_oper_info[2]; ++#define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_SYS_PRI(val) \ ++ vxge_vBIT(val, 0, 16) ++#define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY(val) \ ++ vxge_vBIT(val, 16, 16) ++#define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_NUM(val) \ ++ vxge_vBIT(val, 32, 16) ++#define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_PRI(val) \ ++ vxge_vBIT(val, 48, 16) ++/*0x021a0*/ u64 lag_port_partner_oper_state[2]; ++#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_ACTIVITY vxge_mBIT(3) ++#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_TIMEOUT vxge_mBIT(7) ++#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_AGGREGATION vxge_mBIT(11) ++#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_SYNCHRONIZATION \ ++ vxge_mBIT(15) ++#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_COLLECTING vxge_mBIT(19) ++#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_DISTRIBUTING vxge_mBIT(23) ++#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_DEFAULTED vxge_mBIT(27) ++#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_EXPIRED vxge_mBIT(31) ++/*0x021b0*/ u64 lag_port_state_vars[2]; ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_READY vxge_mBIT(3) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_SELECTED(val) vxge_vBIT(val, 6, 2) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_AGGR_NUM vxge_mBIT(11) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_MOVED vxge_mBIT(15) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_ENABLED vxge_mBIT(18) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_DISABLED vxge_mBIT(19) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_NTT vxge_mBIT(23) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN vxge_mBIT(27) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN vxge_mBIT(31) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_INFO_LEN_MISMATCH \ ++ vxge_mBIT(32) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_INFO_LEN_MISMATCH \ ++ vxge_mBIT(33) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_COLL_INFO_LEN_MISMATCH vxge_mBIT(34) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_TERM_INFO_LEN_MISMATCH vxge_mBIT(35) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_RX_FSM_STATE(val) vxge_vBIT(val, 37, 3) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_FSM_STATE(val) \ ++ vxge_vBIT(val, 41, 3) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_REASON(val) vxge_vBIT(val, 44, 4) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_STATE vxge_mBIT(54) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_STATE vxge_mBIT(55) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_COUNT(val) \ ++ vxge_vBIT(val, 56, 4) ++#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_COUNT(val) \ ++ vxge_vBIT(val, 60, 4) ++/*0x021c0*/ u64 lag_port_timer_cntr[2]; ++#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_CURRENT_WHILE(val) vxge_vBIT(val, 0, 8) ++#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PERIODIC_WHILE(val) \ ++ vxge_vBIT(val, 8, 8) ++#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_WAIT_WHILE(val) vxge_vBIT(val, 16, 8) ++#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_TX_LACP(val) vxge_vBIT(val, 24, 8) ++#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_SYNC_TRANSITION_COUNT(val) \ ++ vxge_vBIT(val, 32, 8) ++#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_SYNC_TRANSITION_COUNT(val) \ ++ vxge_vBIT(val, 40, 8) ++#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_CHANGE_COUNT(val) \ ++ vxge_vBIT(val, 48, 8) ++#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_CHANGE_COUNT(val) \ ++ vxge_vBIT(val, 56, 8) ++ u8 unused02208[0x02700-0x021d0]; ++ ++/*0x02700*/ u64 rtdma_int_status; ++#define VXGE_HW_RTDMA_INT_STATUS_PDA_ALARM_PDA_INT vxge_mBIT(1) ++#define VXGE_HW_RTDMA_INT_STATUS_PCC_ERROR_PCC_INT vxge_mBIT(2) ++#define VXGE_HW_RTDMA_INT_STATUS_LSO_ERROR_LSO_INT vxge_mBIT(4) ++#define VXGE_HW_RTDMA_INT_STATUS_SM_ERROR_SM_INT vxge_mBIT(5) ++/*0x02708*/ u64 rtdma_int_mask; ++/*0x02710*/ u64 pda_alarm_reg; ++#define VXGE_HW_PDA_ALARM_REG_PDA_HSC_FIFO_ERR vxge_mBIT(0) ++#define VXGE_HW_PDA_ALARM_REG_PDA_SM_ERR vxge_mBIT(1) ++/*0x02718*/ u64 pda_alarm_mask; ++/*0x02720*/ u64 pda_alarm_alarm; ++/*0x02728*/ u64 pcc_error_reg; ++#define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FRM_BUF_SBE(n) vxge_mBIT(n) ++#define VXGE_HW_PCC_ERROR_REG_PCC_PCC_TXDO_SBE(n) vxge_mBIT(n) ++#define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FRM_BUF_DBE(n) vxge_mBIT(n) ++#define VXGE_HW_PCC_ERROR_REG_PCC_PCC_TXDO_DBE(n) vxge_mBIT(n) ++#define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FSM_ERR_ALARM(n) vxge_mBIT(n) ++#define VXGE_HW_PCC_ERROR_REG_PCC_PCC_SERR(n) vxge_mBIT(n) ++/*0x02730*/ u64 pcc_error_mask; ++/*0x02738*/ u64 pcc_error_alarm; ++/*0x02740*/ u64 lso_error_reg; ++#define VXGE_HW_LSO_ERROR_REG_PCC_LSO_ABORT(n) vxge_mBIT(n) ++#define VXGE_HW_LSO_ERROR_REG_PCC_LSO_FSM_ERR_ALARM(n) vxge_mBIT(n) ++/*0x02748*/ u64 lso_error_mask; ++/*0x02750*/ u64 lso_error_alarm; ++/*0x02758*/ u64 sm_error_reg; ++#define VXGE_HW_SM_ERROR_REG_SM_FSM_ERR_ALARM vxge_mBIT(15) ++/*0x02760*/ u64 sm_error_mask; ++/*0x02768*/ u64 sm_error_alarm; ++ ++ u8 unused027a8[0x027a8-0x02770]; ++ ++/*0x027a8*/ u64 txd_ownership_ctrl; ++#define VXGE_HW_TXD_OWNERSHIP_CTRL_KEEP_OWNERSHIP vxge_mBIT(7) ++/*0x027b0*/ u64 pcc_cfg; ++#define VXGE_HW_PCC_CFG_PCC_ENABLE(n) vxge_mBIT(n) ++#define VXGE_HW_PCC_CFG_PCC_ECC_ENABLE_N(n) vxge_mBIT(n) ++/*0x027b8*/ u64 pcc_control; ++#define VXGE_HW_PCC_CONTROL_FE_ENABLE(val) vxge_vBIT(val, 6, 2) ++#define VXGE_HW_PCC_CONTROL_EARLY_ASSIGN_EN vxge_mBIT(15) ++#define VXGE_HW_PCC_CONTROL_UNBLOCK_DB_ERR vxge_mBIT(31) ++/*0x027c0*/ u64 pda_status1; ++#define VXGE_HW_PDA_STATUS1_PDA_WRAP_0_CTR(val) vxge_vBIT(val, 4, 4) ++#define VXGE_HW_PDA_STATUS1_PDA_WRAP_1_CTR(val) vxge_vBIT(val, 12, 4) ++#define VXGE_HW_PDA_STATUS1_PDA_WRAP_2_CTR(val) vxge_vBIT(val, 20, 4) ++#define VXGE_HW_PDA_STATUS1_PDA_WRAP_3_CTR(val) vxge_vBIT(val, 28, 4) ++#define VXGE_HW_PDA_STATUS1_PDA_WRAP_4_CTR(val) vxge_vBIT(val, 36, 4) ++#define VXGE_HW_PDA_STATUS1_PDA_WRAP_5_CTR(val) vxge_vBIT(val, 44, 4) ++#define VXGE_HW_PDA_STATUS1_PDA_WRAP_6_CTR(val) vxge_vBIT(val, 52, 4) ++#define VXGE_HW_PDA_STATUS1_PDA_WRAP_7_CTR(val) vxge_vBIT(val, 60, 4) ++/*0x027c8*/ u64 rtdma_bw_timer; ++#define VXGE_HW_RTDMA_BW_TIMER_TIMER_CTRL(val) vxge_vBIT(val, 12, 4) ++ ++ u8 unused02900[0x02900-0x027d0]; ++/*0x02900*/ u64 g3cmct_int_status; ++#define VXGE_HW_G3CMCT_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) ++/*0x02908*/ u64 g3cmct_int_mask; ++/*0x02910*/ u64 g3cmct_err_reg; ++#define VXGE_HW_G3CMCT_ERR_REG_G3IF_SM_ERR vxge_mBIT(4) ++#define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_DECC vxge_mBIT(5) ++#define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_U_DECC vxge_mBIT(6) ++#define VXGE_HW_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_DECC vxge_mBIT(7) ++#define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_SECC vxge_mBIT(29) ++#define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_U_SECC vxge_mBIT(30) ++#define VXGE_HW_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_SECC vxge_mBIT(31) ++/*0x02918*/ u64 g3cmct_err_mask; ++/*0x02920*/ u64 g3cmct_err_alarm; ++ u8 unused03000[0x03000-0x02928]; ++ ++/*0x03000*/ u64 mc_int_status; ++#define VXGE_HW_MC_INT_STATUS_MC_ERR_MC_INT vxge_mBIT(3) ++#define VXGE_HW_MC_INT_STATUS_GROCRC_ALARM_ROCRC_INT vxge_mBIT(7) ++#define VXGE_HW_MC_INT_STATUS_FAU_GEN_ERR_FAU_GEN_INT vxge_mBIT(11) ++#define VXGE_HW_MC_INT_STATUS_FAU_ECC_ERR_FAU_ECC_INT vxge_mBIT(15) ++/*0x03008*/ u64 mc_int_mask; ++/*0x03010*/ u64 mc_err_reg; ++#define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_A vxge_mBIT(3) ++#define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_B vxge_mBIT(4) ++#define VXGE_HW_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_SG_ERR vxge_mBIT(5) ++#define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_0 vxge_mBIT(6) ++#define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_1 vxge_mBIT(7) ++#define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_A vxge_mBIT(10) ++#define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_B vxge_mBIT(11) ++#define VXGE_HW_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_DB_ERR vxge_mBIT(12) ++#define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_0 vxge_mBIT(13) ++#define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_1 vxge_mBIT(14) ++#define VXGE_HW_MC_ERR_REG_MC_SM_ERR vxge_mBIT(15) ++/*0x03018*/ u64 mc_err_mask; ++/*0x03020*/ u64 mc_err_alarm; ++/*0x03028*/ u64 grocrc_alarm_reg; ++#define VXGE_HW_GROCRC_ALARM_REG_XFMD_WR_FIFO_ERR vxge_mBIT(3) ++#define VXGE_HW_GROCRC_ALARM_REG_WDE2MSR_RD_FIFO_ERR vxge_mBIT(7) ++/*0x03030*/ u64 grocrc_alarm_mask; ++/*0x03038*/ u64 grocrc_alarm_alarm; ++ u8 unused03100[0x03100-0x03040]; ++ ++/*0x03100*/ u64 rx_thresh_cfg_repl; ++#define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_LOW_THR(val) vxge_vBIT(val, 0, 8) ++#define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR(val) vxge_vBIT(val, 8, 8) ++#define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_0(val) vxge_vBIT(val, 16, 8) ++#define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_1(val) vxge_vBIT(val, 24, 8) ++#define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_2(val) vxge_vBIT(val, 32, 8) ++#define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_3(val) vxge_vBIT(val, 40, 8) ++#define VXGE_HW_RX_THRESH_CFG_REPL_GLOBAL_WOL_EN vxge_mBIT(62) ++#define VXGE_HW_RX_THRESH_CFG_REPL_EXACT_VP_MATCH_REQ vxge_mBIT(63) ++ u8 unused033b8[0x033b8-0x03108]; ++ ++/*0x033b8*/ u64 fbmc_ecc_cfg; ++#define VXGE_HW_FBMC_ECC_CFG_ENABLE(val) vxge_vBIT(val, 3, 5) ++ u8 unused03400[0x03400-0x033c0]; ++ ++/*0x03400*/ u64 pcipif_int_status; ++#define VXGE_HW_PCIPIF_INT_STATUS_DBECC_ERR_DBECC_ERR_INT vxge_mBIT(3) ++#define VXGE_HW_PCIPIF_INT_STATUS_SBECC_ERR_SBECC_ERR_INT vxge_mBIT(7) ++#define VXGE_HW_PCIPIF_INT_STATUS_GENERAL_ERR_GENERAL_ERR_INT vxge_mBIT(11) ++#define VXGE_HW_PCIPIF_INT_STATUS_SRPCIM_MSG_SRPCIM_MSG_INT vxge_mBIT(15) ++#define VXGE_HW_PCIPIF_INT_STATUS_MRPCIM_SPARE_R1_MRPCIM_SPARE_R1_INT \ ++ vxge_mBIT(19) ++/*0x03408*/ u64 pcipif_int_mask; ++/*0x03410*/ u64 dbecc_err_reg; ++#define VXGE_HW_DBECC_ERR_REG_PCI_RETRY_BUF_DB_ERR vxge_mBIT(3) ++#define VXGE_HW_DBECC_ERR_REG_PCI_RETRY_SOT_DB_ERR vxge_mBIT(7) ++#define VXGE_HW_DBECC_ERR_REG_PCI_P_HDR_DB_ERR vxge_mBIT(11) ++#define VXGE_HW_DBECC_ERR_REG_PCI_P_DATA_DB_ERR vxge_mBIT(15) ++#define VXGE_HW_DBECC_ERR_REG_PCI_NP_HDR_DB_ERR vxge_mBIT(19) ++#define VXGE_HW_DBECC_ERR_REG_PCI_NP_DATA_DB_ERR vxge_mBIT(23) ++/*0x03418*/ u64 dbecc_err_mask; ++/*0x03420*/ u64 dbecc_err_alarm; ++/*0x03428*/ u64 sbecc_err_reg; ++#define VXGE_HW_SBECC_ERR_REG_PCI_RETRY_BUF_SG_ERR vxge_mBIT(3) ++#define VXGE_HW_SBECC_ERR_REG_PCI_RETRY_SOT_SG_ERR vxge_mBIT(7) ++#define VXGE_HW_SBECC_ERR_REG_PCI_P_HDR_SG_ERR vxge_mBIT(11) ++#define VXGE_HW_SBECC_ERR_REG_PCI_P_DATA_SG_ERR vxge_mBIT(15) ++#define VXGE_HW_SBECC_ERR_REG_PCI_NP_HDR_SG_ERR vxge_mBIT(19) ++#define VXGE_HW_SBECC_ERR_REG_PCI_NP_DATA_SG_ERR vxge_mBIT(23) ++/*0x03430*/ u64 sbecc_err_mask; ++/*0x03438*/ u64 sbecc_err_alarm; ++/*0x03440*/ u64 general_err_reg; ++#define VXGE_HW_GENERAL_ERR_REG_PCI_DROPPED_ILLEGAL_CFG vxge_mBIT(3) ++#define VXGE_HW_GENERAL_ERR_REG_PCI_ILLEGAL_MEM_MAP_PROG vxge_mBIT(7) ++#define VXGE_HW_GENERAL_ERR_REG_PCI_LINK_RST_FSM_ERR vxge_mBIT(11) ++#define VXGE_HW_GENERAL_ERR_REG_PCI_RX_ILLEGAL_TLP_VPLANE vxge_mBIT(15) ++#define VXGE_HW_GENERAL_ERR_REG_PCI_TRAINING_RESET_DET vxge_mBIT(19) ++#define VXGE_HW_GENERAL_ERR_REG_PCI_PCI_LINK_DOWN_DET vxge_mBIT(23) ++#define VXGE_HW_GENERAL_ERR_REG_PCI_RESET_ACK_DLLP vxge_mBIT(27) ++/*0x03448*/ u64 general_err_mask; ++/*0x03450*/ u64 general_err_alarm; ++/*0x03458*/ u64 srpcim_msg_reg; ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE0_RMSG_INT \ ++ vxge_mBIT(0) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE1_RMSG_INT \ ++ vxge_mBIT(1) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE2_RMSG_INT \ ++ vxge_mBIT(2) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE3_RMSG_INT \ ++ vxge_mBIT(3) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE4_RMSG_INT \ ++ vxge_mBIT(4) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE5_RMSG_INT \ ++ vxge_mBIT(5) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE6_RMSG_INT \ ++ vxge_mBIT(6) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE7_RMSG_INT \ ++ vxge_mBIT(7) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE8_RMSG_INT \ ++ vxge_mBIT(8) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE9_RMSG_INT \ ++ vxge_mBIT(9) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE10_RMSG_INT \ ++ vxge_mBIT(10) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE11_RMSG_INT \ ++ vxge_mBIT(11) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE12_RMSG_INT \ ++ vxge_mBIT(12) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE13_RMSG_INT \ ++ vxge_mBIT(13) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE14_RMSG_INT \ ++ vxge_mBIT(14) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE15_RMSG_INT \ ++ vxge_mBIT(15) ++#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE16_RMSG_INT \ ++ vxge_mBIT(16) ++/*0x03460*/ u64 srpcim_msg_mask; ++/*0x03468*/ u64 srpcim_msg_alarm; ++ u8 unused03600[0x03600-0x03470]; ++ ++/*0x03600*/ u64 gcmg1_int_status; ++#define VXGE_HW_GCMG1_INT_STATUS_GSSCC_ERR_GSSCC_INT vxge_mBIT(0) ++#define VXGE_HW_GCMG1_INT_STATUS_GSSC0_ERR0_GSSC0_0_INT vxge_mBIT(1) ++#define VXGE_HW_GCMG1_INT_STATUS_GSSC0_ERR1_GSSC0_1_INT vxge_mBIT(2) ++#define VXGE_HW_GCMG1_INT_STATUS_GSSC1_ERR0_GSSC1_0_INT vxge_mBIT(3) ++#define VXGE_HW_GCMG1_INT_STATUS_GSSC1_ERR1_GSSC1_1_INT vxge_mBIT(4) ++#define VXGE_HW_GCMG1_INT_STATUS_GSSC2_ERR0_GSSC2_0_INT vxge_mBIT(5) ++#define VXGE_HW_GCMG1_INT_STATUS_GSSC2_ERR1_GSSC2_1_INT vxge_mBIT(6) ++#define VXGE_HW_GCMG1_INT_STATUS_UQM_ERR_UQM_INT vxge_mBIT(7) ++#define VXGE_HW_GCMG1_INT_STATUS_GQCC_ERR_GQCC_INT vxge_mBIT(8) ++/*0x03608*/ u64 gcmg1_int_mask; ++ u8 unused03a00[0x03a00-0x03610]; ++ ++/*0x03a00*/ u64 pcmg1_int_status; ++#define VXGE_HW_PCMG1_INT_STATUS_PSSCC_ERR_PSSCC_INT vxge_mBIT(0) ++#define VXGE_HW_PCMG1_INT_STATUS_PQCC_ERR_PQCC_INT vxge_mBIT(1) ++#define VXGE_HW_PCMG1_INT_STATUS_PQCC_CQM_ERR_PQCC_CQM_INT vxge_mBIT(2) ++#define VXGE_HW_PCMG1_INT_STATUS_PQCC_SQM_ERR_PQCC_SQM_INT vxge_mBIT(3) ++/*0x03a08*/ u64 pcmg1_int_mask; ++ u8 unused04000[0x04000-0x03a10]; ++ ++/*0x04000*/ u64 one_int_status; ++#define VXGE_HW_ONE_INT_STATUS_RXPE_ERR_RXPE_INT vxge_mBIT(7) ++#define VXGE_HW_ONE_INT_STATUS_TXPE_BCC_MEM_SG_ECC_ERR_TXPE_BCC_MEM_SG_ECC_INT \ ++ vxge_mBIT(13) ++#define VXGE_HW_ONE_INT_STATUS_TXPE_BCC_MEM_DB_ECC_ERR_TXPE_BCC_MEM_DB_ECC_INT \ ++ vxge_mBIT(14) ++#define VXGE_HW_ONE_INT_STATUS_TXPE_ERR_TXPE_INT vxge_mBIT(15) ++#define VXGE_HW_ONE_INT_STATUS_DLM_ERR_DLM_INT vxge_mBIT(23) ++#define VXGE_HW_ONE_INT_STATUS_PE_ERR_PE_INT vxge_mBIT(31) ++#define VXGE_HW_ONE_INT_STATUS_RPE_ERR_RPE_INT vxge_mBIT(39) ++#define VXGE_HW_ONE_INT_STATUS_RPE_FSM_ERR_RPE_FSM_INT vxge_mBIT(47) ++#define VXGE_HW_ONE_INT_STATUS_OES_ERR_OES_INT vxge_mBIT(55) ++/*0x04008*/ u64 one_int_mask; ++ u8 unused04818[0x04818-0x04010]; ++ ++/*0x04818*/ u64 noa_wct_ctrl; ++#define VXGE_HW_NOA_WCT_CTRL_VP_INT_NUM vxge_mBIT(0) ++/*0x04820*/ u64 rc_cfg2; ++#define VXGE_HW_RC_CFG2_BUFF1_SIZE(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_RC_CFG2_BUFF2_SIZE(val) vxge_vBIT(val, 16, 16) ++#define VXGE_HW_RC_CFG2_BUFF3_SIZE(val) vxge_vBIT(val, 32, 16) ++#define VXGE_HW_RC_CFG2_BUFF4_SIZE(val) vxge_vBIT(val, 48, 16) ++/*0x04828*/ u64 rc_cfg3; ++#define VXGE_HW_RC_CFG3_BUFF5_SIZE(val) vxge_vBIT(val, 0, 16) ++/*0x04830*/ u64 rx_multi_cast_ctrl1; ++#define VXGE_HW_RX_MULTI_CAST_CTRL1_ENABLE vxge_mBIT(7) ++#define VXGE_HW_RX_MULTI_CAST_CTRL1_DELAY_COUNT(val) vxge_vBIT(val, 11, 5) ++/*0x04838*/ u64 rxdm_dbg_rd; ++#define VXGE_HW_RXDM_DBG_RD_ADDR(val) vxge_vBIT(val, 0, 12) ++#define VXGE_HW_RXDM_DBG_RD_ENABLE vxge_mBIT(31) ++/*0x04840*/ u64 rxdm_dbg_rd_data; ++#define VXGE_HW_RXDM_DBG_RD_DATA_RMC_RXDM_DBG_RD_DATA(val) vxge_vBIT(val, 0, 64) ++/*0x04848*/ u64 rqa_top_prty_for_vh[17]; ++#define VXGE_HW_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) \ ++ vxge_vBIT(val, 59, 5) ++ u8 unused04900[0x04900-0x048d0]; ++ ++/*0x04900*/ u64 tim_status; ++#define VXGE_HW_TIM_STATUS_TIM_RESET_IN_PROGRESS vxge_mBIT(0) ++/*0x04908*/ u64 tim_ecc_enable; ++#define VXGE_HW_TIM_ECC_ENABLE_VBLS_N vxge_mBIT(7) ++#define VXGE_HW_TIM_ECC_ENABLE_BMAP_N vxge_mBIT(15) ++#define VXGE_HW_TIM_ECC_ENABLE_BMAP_MSG_N vxge_mBIT(23) ++/*0x04910*/ u64 tim_bp_ctrl; ++#define VXGE_HW_TIM_BP_CTRL_RD_XON vxge_mBIT(7) ++#define VXGE_HW_TIM_BP_CTRL_WR_XON vxge_mBIT(15) ++#define VXGE_HW_TIM_BP_CTRL_ROCRC_BYP vxge_mBIT(23) ++/*0x04918*/ u64 tim_resource_assignment_vh[17]; ++#define VXGE_HW_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) vxge_vBIT(val, 0, 32) ++/*0x049a0*/ u64 tim_bmap_mapping_vp_err[17]; ++#define VXGE_HW_TIM_BMAP_MAPPING_VP_ERR_TIM_DEST_VPATH(val) vxge_vBIT(val, 3, 5) ++ u8 unused04b00[0x04b00-0x04a28]; ++ ++/*0x04b00*/ u64 gcmg2_int_status; ++#define VXGE_HW_GCMG2_INT_STATUS_GXTMC_ERR_GXTMC_INT vxge_mBIT(7) ++#define VXGE_HW_GCMG2_INT_STATUS_GCP_ERR_GCP_INT vxge_mBIT(15) ++#define VXGE_HW_GCMG2_INT_STATUS_CMC_ERR_CMC_INT vxge_mBIT(23) ++/*0x04b08*/ u64 gcmg2_int_mask; ++/*0x04b10*/ u64 gxtmc_err_reg; ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(val) vxge_vBIT(val, 0, 4) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_SG_ERR(val) vxge_vBIT(val, 4, 4) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMC_RD_DATA_DB_ERR vxge_mBIT(8) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_REQ_FIFO_ERR vxge_mBIT(9) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR vxge_mBIT(10) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR vxge_mBIT(11) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR vxge_mBIT(12) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_WRP_FIFO_ERR vxge_mBIT(13) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_WRP_ERR vxge_mBIT(14) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_RRP_FIFO_ERR vxge_mBIT(15) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_RRP_ERR vxge_mBIT(16) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_DATA_SM_ERR vxge_mBIT(17) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_CMC0_IF_ERR vxge_mBIT(18) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_ARB_SM_ERR vxge_mBIT(19) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_CFC_SM_ERR vxge_mBIT(20) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_OVERFLOW \ ++ vxge_mBIT(21) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_UNDERFLOW \ ++ vxge_mBIT(22) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_SM_ERR vxge_mBIT(23) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_OVERFLOW \ ++ vxge_mBIT(24) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_UNDERFLOW \ ++ vxge_mBIT(25) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_SM_ERR vxge_mBIT(26) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_SM_ERR vxge_mBIT(27) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_TAG_ERR vxge_mBIT(28) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_SM_ERR vxge_mBIT(29) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_FIFO_ERR vxge_mBIT(30) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_POP_ERR vxge_mBIT(31) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_CMI_OP_ERR vxge_mBIT(32) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFETCH_OP_ERR vxge_mBIT(33) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFIFO_ERR vxge_mBIT(34) ++#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_ARB_SM_ERR vxge_mBIT(35) ++/*0x04b18*/ u64 gxtmc_err_mask; ++/*0x04b20*/ u64 gxtmc_err_alarm; ++/*0x04b28*/ u64 cmc_err_reg; ++#define VXGE_HW_CMC_ERR_REG_CMC_CMC_SM_ERR vxge_mBIT(0) ++/*0x04b30*/ u64 cmc_err_mask; ++/*0x04b38*/ u64 cmc_err_alarm; ++/*0x04b40*/ u64 gcp_err_reg; ++#define VXGE_HW_GCP_ERR_REG_CP_H2L2CP_FIFO_ERR vxge_mBIT(0) ++#define VXGE_HW_GCP_ERR_REG_CP_STC2CP_FIFO_ERR vxge_mBIT(1) ++#define VXGE_HW_GCP_ERR_REG_CP_STE2CP_FIFO_ERR vxge_mBIT(2) ++#define VXGE_HW_GCP_ERR_REG_CP_TTE2CP_FIFO_ERR vxge_mBIT(3) ++/*0x04b48*/ u64 gcp_err_mask; ++/*0x04b50*/ u64 gcp_err_alarm; ++ u8 unused04f00[0x04f00-0x04b58]; ++ ++/*0x04f00*/ u64 pcmg2_int_status; ++#define VXGE_HW_PCMG2_INT_STATUS_PXTMC_ERR_PXTMC_INT vxge_mBIT(7) ++#define VXGE_HW_PCMG2_INT_STATUS_CP_EXC_CP_XT_EXC_INT vxge_mBIT(15) ++#define VXGE_HW_PCMG2_INT_STATUS_CP_ERR_CP_ERR_INT vxge_mBIT(23) ++/*0x04f08*/ u64 pcmg2_int_mask; ++/*0x04f10*/ u64 pxtmc_err_reg; ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(val) vxge_vBIT(val, 0, 2) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_FIFO_ERR vxge_mBIT(2) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_PRSP_FIFO_ERR vxge_mBIT(3) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_WRSP_FIFO_ERR vxge_mBIT(4) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_FIFO_ERR vxge_mBIT(5) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_PRSP_FIFO_ERR vxge_mBIT(6) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_WRSP_FIFO_ERR vxge_mBIT(7) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_FIFO_ERR vxge_mBIT(8) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_PRSP_FIFO_ERR vxge_mBIT(9) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_WRSP_FIFO_ERR vxge_mBIT(10) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_REQ_FIFO_ERR vxge_mBIT(11) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR vxge_mBIT(12) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR vxge_mBIT(13) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR vxge_mBIT(14) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_SHADOW_ERR vxge_mBIT(15) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_RSP_SHADOW_ERR vxge_mBIT(16) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_SHADOW_ERR vxge_mBIT(17) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_RSP_SHADOW_ERR vxge_mBIT(18) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_SHADOW_ERR vxge_mBIT(19) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_RSP_SHADOW_ERR vxge_mBIT(20) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_XIL_SHADOW_ERR vxge_mBIT(21) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_ARB_SHADOW_ERR vxge_mBIT(22) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_RAM_SHADOW_ERR vxge_mBIT(23) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CMW_SHADOW_ERR vxge_mBIT(24) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CMR_SHADOW_ERR vxge_mBIT(25) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_FSM_ERR vxge_mBIT(26) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_RSP_FSM_ERR vxge_mBIT(27) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_FSM_ERR vxge_mBIT(28) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_RSP_FSM_ERR vxge_mBIT(29) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_FSM_ERR vxge_mBIT(30) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_RSP_FSM_ERR vxge_mBIT(31) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_XIL_FSM_ERR vxge_mBIT(32) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_ARB_FSM_ERR vxge_mBIT(33) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CMW_FSM_ERR vxge_mBIT(34) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CMR_FSM_ERR vxge_mBIT(35) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_ERR vxge_mBIT(36) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_ERR vxge_mBIT(37) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_ERR vxge_mBIT(38) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_ERR vxge_mBIT(39) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_ERR vxge_mBIT(40) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_ERR vxge_mBIT(41) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_ERR vxge_mBIT(42) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_ERR vxge_mBIT(43) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_ERR vxge_mBIT(44) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_INFO_ERR vxge_mBIT(45) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_INFO_ERR vxge_mBIT(46) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_INFO_ERR vxge_mBIT(47) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_INFO_ERR vxge_mBIT(48) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_INFO_ERR vxge_mBIT(49) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_INFO_ERR vxge_mBIT(50) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_INFO_ERR vxge_mBIT(51) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_INFO_ERR vxge_mBIT(52) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_INFO_ERR vxge_mBIT(53) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_SG_ERR(val) vxge_vBIT(val, 54, 2) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CP2BDT_DFIFO_PUSH_ERR vxge_mBIT(56) ++#define VXGE_HW_PXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_PUSH_ERR vxge_mBIT(57) ++/*0x04f18*/ u64 pxtmc_err_mask; ++/*0x04f20*/ u64 pxtmc_err_alarm; ++/*0x04f28*/ u64 cp_err_reg; ++#define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_SG_ERR(val) vxge_vBIT(val, 0, 8) ++#define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_SG_ERR(val) vxge_vBIT(val, 8, 2) ++#define VXGE_HW_CP_ERR_REG_CP_CP_DTAG_SG_ERR vxge_mBIT(10) ++#define VXGE_HW_CP_ERR_REG_CP_CP_ITAG_SG_ERR vxge_mBIT(11) ++#define VXGE_HW_CP_ERR_REG_CP_CP_TRACE_SG_ERR vxge_mBIT(12) ++#define VXGE_HW_CP_ERR_REG_CP_DMA2CP_SG_ERR vxge_mBIT(13) ++#define VXGE_HW_CP_ERR_REG_CP_MP2CP_SG_ERR vxge_mBIT(14) ++#define VXGE_HW_CP_ERR_REG_CP_QCC2CP_SG_ERR vxge_mBIT(15) ++#define VXGE_HW_CP_ERR_REG_CP_STC2CP_SG_ERR(val) vxge_vBIT(val, 16, 2) ++#define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(val) vxge_vBIT(val, 24, 8) ++#define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(val) vxge_vBIT(val, 32, 2) ++#define VXGE_HW_CP_ERR_REG_CP_CP_DTAG_DB_ERR vxge_mBIT(34) ++#define VXGE_HW_CP_ERR_REG_CP_CP_ITAG_DB_ERR vxge_mBIT(35) ++#define VXGE_HW_CP_ERR_REG_CP_CP_TRACE_DB_ERR vxge_mBIT(36) ++#define VXGE_HW_CP_ERR_REG_CP_DMA2CP_DB_ERR vxge_mBIT(37) ++#define VXGE_HW_CP_ERR_REG_CP_MP2CP_DB_ERR vxge_mBIT(38) ++#define VXGE_HW_CP_ERR_REG_CP_QCC2CP_DB_ERR vxge_mBIT(39) ++#define VXGE_HW_CP_ERR_REG_CP_STC2CP_DB_ERR(val) vxge_vBIT(val, 40, 2) ++#define VXGE_HW_CP_ERR_REG_CP_H2L2CP_FIFO_ERR vxge_mBIT(48) ++#define VXGE_HW_CP_ERR_REG_CP_STC2CP_FIFO_ERR vxge_mBIT(49) ++#define VXGE_HW_CP_ERR_REG_CP_STE2CP_FIFO_ERR vxge_mBIT(50) ++#define VXGE_HW_CP_ERR_REG_CP_TTE2CP_FIFO_ERR vxge_mBIT(51) ++#define VXGE_HW_CP_ERR_REG_CP_SWIF2CP_FIFO_ERR vxge_mBIT(52) ++#define VXGE_HW_CP_ERR_REG_CP_CP2DMA_FIFO_ERR vxge_mBIT(53) ++#define VXGE_HW_CP_ERR_REG_CP_DAM2CP_FIFO_ERR vxge_mBIT(54) ++#define VXGE_HW_CP_ERR_REG_CP_MP2CP_FIFO_ERR vxge_mBIT(55) ++#define VXGE_HW_CP_ERR_REG_CP_QCC2CP_FIFO_ERR vxge_mBIT(56) ++#define VXGE_HW_CP_ERR_REG_CP_DMA2CP_FIFO_ERR vxge_mBIT(57) ++#define VXGE_HW_CP_ERR_REG_CP_CP_WAKE_FSM_INTEGRITY_ERR vxge_mBIT(60) ++#define VXGE_HW_CP_ERR_REG_CP_CP_PMON_FSM_INTEGRITY_ERR vxge_mBIT(61) ++#define VXGE_HW_CP_ERR_REG_CP_DMA_RD_SHADOW_ERR vxge_mBIT(62) ++#define VXGE_HW_CP_ERR_REG_CP_PIFT_CREDIT_ERR vxge_mBIT(63) ++/*0x04f30*/ u64 cp_err_mask; ++/*0x04f38*/ u64 cp_err_alarm; ++ u8 unused04fe8[0x04f50-0x04f40]; ++ ++/*0x04f50*/ u64 cp_exc_reg; ++#define VXGE_HW_CP_EXC_REG_CP_CP_CAUSE_INFO_INT vxge_mBIT(47) ++#define VXGE_HW_CP_EXC_REG_CP_CP_CAUSE_CRIT_INT vxge_mBIT(55) ++#define VXGE_HW_CP_EXC_REG_CP_CP_SERR vxge_mBIT(63) ++/*0x04f58*/ u64 cp_exc_mask; ++/*0x04f60*/ u64 cp_exc_alarm; ++/*0x04f68*/ u64 cp_exc_cause; ++#define VXGE_HW_CP_EXC_CAUSE_CP_CP_CAUSE(val) vxge_vBIT(val, 32, 32) ++ u8 unused05200[0x05200-0x04f70]; ++ ++/*0x05200*/ u64 msg_int_status; ++#define VXGE_HW_MSG_INT_STATUS_TIM_ERR_TIM_INT vxge_mBIT(7) ++#define VXGE_HW_MSG_INT_STATUS_MSG_EXC_MSG_XT_EXC_INT vxge_mBIT(60) ++#define VXGE_HW_MSG_INT_STATUS_MSG_ERR3_MSG_ERR3_INT vxge_mBIT(61) ++#define VXGE_HW_MSG_INT_STATUS_MSG_ERR2_MSG_ERR2_INT vxge_mBIT(62) ++#define VXGE_HW_MSG_INT_STATUS_MSG_ERR_MSG_ERR_INT vxge_mBIT(63) ++/*0x05208*/ u64 msg_int_mask; ++/*0x05210*/ u64 tim_err_reg; ++#define VXGE_HW_TIM_ERR_REG_TIM_VBLS_SG_ERR vxge_mBIT(4) ++#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PA_SG_ERR vxge_mBIT(5) ++#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PB_SG_ERR vxge_mBIT(6) ++#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_SG_ERR vxge_mBIT(7) ++#define VXGE_HW_TIM_ERR_REG_TIM_VBLS_DB_ERR vxge_mBIT(12) ++#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PA_DB_ERR vxge_mBIT(13) ++#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PB_DB_ERR vxge_mBIT(14) ++#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_DB_ERR vxge_mBIT(15) ++#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MEM_CNTRL_SM_ERR vxge_mBIT(18) ++#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_MEM_CNTRL_SM_ERR vxge_mBIT(19) ++#define VXGE_HW_TIM_ERR_REG_TIM_MPIF_PCIWR_ERR vxge_mBIT(20) ++#define VXGE_HW_TIM_ERR_REG_TIM_ROCRC_BMAP_UPDT_FIFO_ERR vxge_mBIT(22) ++#define VXGE_HW_TIM_ERR_REG_TIM_CREATE_BMAPMSG_FIFO_ERR vxge_mBIT(23) ++#define VXGE_HW_TIM_ERR_REG_TIM_ROCRCIF_MISMATCH vxge_mBIT(46) ++#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MAPPING_VP_ERR(n) vxge_mBIT(n) ++/*0x05218*/ u64 tim_err_mask; ++/*0x05220*/ u64 tim_err_alarm; ++/*0x05228*/ u64 msg_err_reg; ++#define VXGE_HW_MSG_ERR_REG_UP_UXP_WAKE_FSM_INTEGRITY_ERR vxge_mBIT(0) ++#define VXGE_HW_MSG_ERR_REG_MP_MXP_WAKE_FSM_INTEGRITY_ERR vxge_mBIT(1) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_DMA_READ_CMD_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(2) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_DMA_RESP_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(3) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_OWN_FSM_INTEGRITY_ERR vxge_mBIT(4) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_PDA_ACC_FSM_INTEGRITY_ERR vxge_mBIT(5) ++#define VXGE_HW_MSG_ERR_REG_MP_MXP_PMON_FSM_INTEGRITY_ERR vxge_mBIT(6) ++#define VXGE_HW_MSG_ERR_REG_UP_UXP_PMON_FSM_INTEGRITY_ERR vxge_mBIT(7) ++#define VXGE_HW_MSG_ERR_REG_UP_UXP_DTAG_SG_ERR vxge_mBIT(8) ++#define VXGE_HW_MSG_ERR_REG_UP_UXP_ITAG_SG_ERR vxge_mBIT(10) ++#define VXGE_HW_MSG_ERR_REG_MP_MXP_DTAG_SG_ERR vxge_mBIT(12) ++#define VXGE_HW_MSG_ERR_REG_MP_MXP_ITAG_SG_ERR vxge_mBIT(14) ++#define VXGE_HW_MSG_ERR_REG_UP_UXP_TRACE_SG_ERR vxge_mBIT(16) ++#define VXGE_HW_MSG_ERR_REG_MP_MXP_TRACE_SG_ERR vxge_mBIT(17) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_CMG2MSG_SG_ERR vxge_mBIT(18) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_TXPE2MSG_SG_ERR vxge_mBIT(19) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_RXPE2MSG_SG_ERR vxge_mBIT(20) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_RPE2MSG_SG_ERR vxge_mBIT(21) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_SG_ERR vxge_mBIT(26) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_PF_SG_ERR vxge_mBIT(27) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_ECC_SG_ERR vxge_mBIT(29) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_SG_ERR vxge_mBIT(31) ++#define VXGE_HW_MSG_ERR_REG_MSG_XFMDQRY_FSM_INTEGRITY_ERR vxge_mBIT(33) ++#define VXGE_HW_MSG_ERR_REG_MSG_FRMQRY_FSM_INTEGRITY_ERR vxge_mBIT(34) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_WRITE_FSM_INTEGRITY_ERR vxge_mBIT(35) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_BWR_PF_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(36) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_REG_RESP_FIFO_ERR vxge_mBIT(38) ++#define VXGE_HW_MSG_ERR_REG_UP_UXP_DTAG_DB_ERR vxge_mBIT(39) ++#define VXGE_HW_MSG_ERR_REG_UP_UXP_ITAG_DB_ERR vxge_mBIT(41) ++#define VXGE_HW_MSG_ERR_REG_MP_MXP_DTAG_DB_ERR vxge_mBIT(43) ++#define VXGE_HW_MSG_ERR_REG_MP_MXP_ITAG_DB_ERR vxge_mBIT(45) ++#define VXGE_HW_MSG_ERR_REG_UP_UXP_TRACE_DB_ERR vxge_mBIT(47) ++#define VXGE_HW_MSG_ERR_REG_MP_MXP_TRACE_DB_ERR vxge_mBIT(48) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_CMG2MSG_DB_ERR vxge_mBIT(49) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_TXPE2MSG_DB_ERR vxge_mBIT(50) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_RXPE2MSG_DB_ERR vxge_mBIT(51) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_RPE2MSG_DB_ERR vxge_mBIT(52) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_REG_READ_FIFO_ERR vxge_mBIT(53) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_MXP2UXP_FIFO_ERR vxge_mBIT(54) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_KDFC_SIF_FIFO_ERR vxge_mBIT(55) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_CXP2SWIF_FIFO_ERR vxge_mBIT(56) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_DB_ERR vxge_mBIT(57) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_PF_DB_ERR vxge_mBIT(58) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_SIF_FIFO_ERR vxge_mBIT(59) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_ECC_DB_ERR vxge_mBIT(60) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_READ_FIFO_ERR vxge_mBIT(61) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_DB_ERR vxge_mBIT(62) ++#define VXGE_HW_MSG_ERR_REG_MSG_QUE_UXP2MXP_FIFO_ERR vxge_mBIT(63) ++/*0x05230*/ u64 msg_err_mask; ++/*0x05238*/ u64 msg_err_alarm; ++ u8 unused05340[0x05340-0x05240]; ++ ++/*0x05340*/ u64 msg_exc_reg; ++#define VXGE_HW_MSG_EXC_REG_MP_MXP_CAUSE_INFO_INT vxge_mBIT(50) ++#define VXGE_HW_MSG_EXC_REG_MP_MXP_CAUSE_CRIT_INT vxge_mBIT(51) ++#define VXGE_HW_MSG_EXC_REG_UP_UXP_CAUSE_INFO_INT vxge_mBIT(54) ++#define VXGE_HW_MSG_EXC_REG_UP_UXP_CAUSE_CRIT_INT vxge_mBIT(55) ++#define VXGE_HW_MSG_EXC_REG_MP_MXP_SERR vxge_mBIT(62) ++#define VXGE_HW_MSG_EXC_REG_UP_UXP_SERR vxge_mBIT(63) ++/*0x05348*/ u64 msg_exc_mask; ++/*0x05350*/ u64 msg_exc_alarm; ++/*0x05358*/ u64 msg_exc_cause; ++#define VXGE_HW_MSG_EXC_CAUSE_MP_MXP(val) vxge_vBIT(val, 0, 32) ++#define VXGE_HW_MSG_EXC_CAUSE_UP_UXP(val) vxge_vBIT(val, 32, 32) ++ u8 unused05368[0x05380-0x05360]; ++ ++/*0x05380*/ u64 msg_err2_reg; ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_CMG2MSG_DISPATCH_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(0) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_DMQ_DISPATCH_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(1) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIF_DISPATCH_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(2) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_PIC_WRITE_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(3) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIFREG_FSM_INTEGRITY_ERR vxge_mBIT(4) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TIM_WRITE_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(5) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_UMQ_TA_FSM_INTEGRITY_ERR vxge_mBIT(6) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TXPE_TA_FSM_INTEGRITY_ERR vxge_mBIT(7) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RXPE_TA_FSM_INTEGRITY_ERR vxge_mBIT(8) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIF_TA_FSM_INTEGRITY_ERR vxge_mBIT(9) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_DMA_TA_FSM_INTEGRITY_ERR vxge_mBIT(10) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_CP_TA_FSM_INTEGRITY_ERR vxge_mBIT(11) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA16_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(12) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA15_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(13) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA14_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(14) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA13_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(15) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA12_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(16) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA11_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(17) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA10_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(18) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA9_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(19) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA8_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(20) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA7_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(21) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA6_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(22) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA5_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(23) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA4_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(24) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA3_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(25) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA2_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(26) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA1_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(27) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA0_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(28) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_FBMC_OWN_FSM_INTEGRITY_ERR vxge_mBIT(29) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(30) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(31) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RPE2MSG_DISPATCH_FSM_INTEGRITY_ERR \ ++ vxge_mBIT(32) ++#define VXGE_HW_MSG_ERR2_REG_MP_MP_PIFT_IF_CREDIT_CNT_ERR vxge_mBIT(33) ++#define VXGE_HW_MSG_ERR2_REG_UP_UP_PIFT_IF_CREDIT_CNT_ERR vxge_mBIT(34) ++#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_UMQ2PIC_CMD_FIFO_ERR vxge_mBIT(62) ++#define VXGE_HW_MSG_ERR2_REG_TIM_TIM2MSG_CMD_FIFO_ERR vxge_mBIT(63) ++/*0x05388*/ u64 msg_err2_mask; ++/*0x05390*/ u64 msg_err2_alarm; ++/*0x05398*/ u64 msg_err3_reg; ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR0 vxge_mBIT(0) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR1 vxge_mBIT(1) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR2 vxge_mBIT(2) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR3 vxge_mBIT(3) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR4 vxge_mBIT(4) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR5 vxge_mBIT(5) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR6 vxge_mBIT(6) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR7 vxge_mBIT(7) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR0 vxge_mBIT(8) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR1 vxge_mBIT(9) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR0 vxge_mBIT(16) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR1 vxge_mBIT(17) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR2 vxge_mBIT(18) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR3 vxge_mBIT(19) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR4 vxge_mBIT(20) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR5 vxge_mBIT(21) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR6 vxge_mBIT(22) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR7 vxge_mBIT(23) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR0 vxge_mBIT(24) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR1 vxge_mBIT(25) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0 vxge_mBIT(32) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR1 vxge_mBIT(33) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR2 vxge_mBIT(34) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR3 vxge_mBIT(35) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR4 vxge_mBIT(36) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR5 vxge_mBIT(37) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR6 vxge_mBIT(38) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR7 vxge_mBIT(39) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR0 vxge_mBIT(40) ++#define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR1 vxge_mBIT(41) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR0 vxge_mBIT(48) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR1 vxge_mBIT(49) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR2 vxge_mBIT(50) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR3 vxge_mBIT(51) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR4 vxge_mBIT(52) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR5 vxge_mBIT(53) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR6 vxge_mBIT(54) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR7 vxge_mBIT(55) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR0 vxge_mBIT(56) ++#define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR1 vxge_mBIT(57) ++/*0x053a0*/ u64 msg_err3_mask; ++/*0x053a8*/ u64 msg_err3_alarm; ++ u8 unused05600[0x05600-0x053b0]; ++ ++/*0x05600*/ u64 fau_gen_err_reg; ++#define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT0_PERMANENT_STOP vxge_mBIT(3) ++#define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT1_PERMANENT_STOP vxge_mBIT(7) ++#define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT2_PERMANENT_STOP vxge_mBIT(11) ++#define VXGE_HW_FAU_GEN_ERR_REG_FALR_AUTO_LRO_NOTIFICATION vxge_mBIT(15) ++/*0x05608*/ u64 fau_gen_err_mask; ++/*0x05610*/ u64 fau_gen_err_alarm; ++/*0x05618*/ u64 fau_ecc_err_reg; ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_SG_ERR vxge_mBIT(0) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_DB_ERR vxge_mBIT(1) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_SG_ERR(val) \ ++ vxge_vBIT(val, 2, 2) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(val) \ ++ vxge_vBIT(val, 4, 2) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_SG_ERR vxge_mBIT(6) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_DB_ERR vxge_mBIT(7) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_SG_ERR(val) \ ++ vxge_vBIT(val, 8, 2) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(val) \ ++ vxge_vBIT(val, 10, 2) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_SG_ERR vxge_mBIT(12) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_DB_ERR vxge_mBIT(13) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_SG_ERR(val) \ ++ vxge_vBIT(val, 14, 2) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(val) \ ++ vxge_vBIT(val, 16, 2) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_SG_ERR(val) \ ++ vxge_vBIT(val, 18, 2) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(val) \ ++ vxge_vBIT(val, 20, 2) ++#define VXGE_HW_FAU_ECC_ERR_REG_FAUJ_FAU_FSM_ERR vxge_mBIT(31) ++/*0x05620*/ u64 fau_ecc_err_mask; ++/*0x05628*/ u64 fau_ecc_err_alarm; ++ u8 unused05658[0x05658-0x05630]; ++/*0x05658*/ u64 fau_pa_cfg; ++#define VXGE_HW_FAU_PA_CFG_REPL_L4_COMP_CSUM vxge_mBIT(3) ++#define VXGE_HW_FAU_PA_CFG_REPL_L3_INCL_CF vxge_mBIT(7) ++#define VXGE_HW_FAU_PA_CFG_REPL_L3_COMP_CSUM vxge_mBIT(11) ++ u8 unused05668[0x05668-0x05660]; ++ ++/*0x05668*/ u64 dbg_stats_fau_rx_path; ++#define VXGE_HW_DBG_STATS_FAU_RX_PATH_RX_PERMITTED_FRMS(val) \ ++ vxge_vBIT(val, 32, 32) ++ u8 unused056c0[0x056c0-0x05670]; ++ ++/*0x056c0*/ u64 fau_lag_cfg; ++#define VXGE_HW_FAU_LAG_CFG_COLL_ALG(val) vxge_vBIT(val, 2, 2) ++#define VXGE_HW_FAU_LAG_CFG_INCR_RX_AGGR_STATS vxge_mBIT(7) ++ u8 unused05800[0x05800-0x056c8]; ++ ++/*0x05800*/ u64 tpa_int_status; ++#define VXGE_HW_TPA_INT_STATUS_ORP_ERR_ORP_INT vxge_mBIT(15) ++#define VXGE_HW_TPA_INT_STATUS_PTM_ALARM_PTM_INT vxge_mBIT(23) ++#define VXGE_HW_TPA_INT_STATUS_TPA_ERROR_TPA_INT vxge_mBIT(31) ++/*0x05808*/ u64 tpa_int_mask; ++/*0x05810*/ u64 orp_err_reg; ++#define VXGE_HW_ORP_ERR_REG_ORP_FIFO_SG_ERR vxge_mBIT(3) ++#define VXGE_HW_ORP_ERR_REG_ORP_FIFO_DB_ERR vxge_mBIT(7) ++#define VXGE_HW_ORP_ERR_REG_ORP_XFMD_FIFO_UFLOW_ERR vxge_mBIT(11) ++#define VXGE_HW_ORP_ERR_REG_ORP_FRM_FIFO_UFLOW_ERR vxge_mBIT(15) ++#define VXGE_HW_ORP_ERR_REG_ORP_XFMD_RCV_FSM_ERR vxge_mBIT(19) ++#define VXGE_HW_ORP_ERR_REG_ORP_OUTREAD_FSM_ERR vxge_mBIT(23) ++#define VXGE_HW_ORP_ERR_REG_ORP_OUTQEM_FSM_ERR vxge_mBIT(27) ++#define VXGE_HW_ORP_ERR_REG_ORP_XFMD_RCV_SHADOW_ERR vxge_mBIT(31) ++#define VXGE_HW_ORP_ERR_REG_ORP_OUTREAD_SHADOW_ERR vxge_mBIT(35) ++#define VXGE_HW_ORP_ERR_REG_ORP_OUTQEM_SHADOW_ERR vxge_mBIT(39) ++#define VXGE_HW_ORP_ERR_REG_ORP_OUTFRM_SHADOW_ERR vxge_mBIT(43) ++#define VXGE_HW_ORP_ERR_REG_ORP_OPTPRS_SHADOW_ERR vxge_mBIT(47) ++/*0x05818*/ u64 orp_err_mask; ++/*0x05820*/ u64 orp_err_alarm; ++/*0x05828*/ u64 ptm_alarm_reg; ++#define VXGE_HW_PTM_ALARM_REG_PTM_RDCTRL_SYNC_ERR vxge_mBIT(3) ++#define VXGE_HW_PTM_ALARM_REG_PTM_RDCTRL_FIFO_ERR vxge_mBIT(7) ++#define VXGE_HW_PTM_ALARM_REG_XFMD_RD_FIFO_ERR vxge_mBIT(11) ++#define VXGE_HW_PTM_ALARM_REG_WDE2MSR_WR_FIFO_ERR vxge_mBIT(15) ++#define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(val) vxge_vBIT(val, 18, 2) ++#define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_SG_ERR(val) vxge_vBIT(val, 22, 2) ++/*0x05830*/ u64 ptm_alarm_mask; ++/*0x05838*/ u64 ptm_alarm_alarm; ++/*0x05840*/ u64 tpa_error_reg; ++#define VXGE_HW_TPA_ERROR_REG_TPA_FSM_ERR_ALARM vxge_mBIT(3) ++#define VXGE_HW_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_DB_ERR vxge_mBIT(7) ++#define VXGE_HW_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_SG_ERR vxge_mBIT(11) ++/*0x05848*/ u64 tpa_error_mask; ++/*0x05850*/ u64 tpa_error_alarm; ++/*0x05858*/ u64 tpa_global_cfg; ++#define VXGE_HW_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N vxge_mBIT(7) ++#define VXGE_HW_TPA_GLOBAL_CFG_ECC_ENABLE_N vxge_mBIT(35) ++ u8 unused05868[0x05870-0x05860]; ++ ++/*0x05870*/ u64 ptm_ecc_cfg; ++#define VXGE_HW_PTM_ECC_CFG_PTM_FRMM_ECC_EN_N vxge_mBIT(3) ++/*0x05878*/ u64 ptm_phase_cfg; ++#define VXGE_HW_PTM_PHASE_CFG_FRMM_WR_PHASE_EN vxge_mBIT(3) ++#define VXGE_HW_PTM_PHASE_CFG_FRMM_RD_PHASE_EN vxge_mBIT(7) ++ u8 unused05898[0x05898-0x05880]; ++ ++/*0x05898*/ u64 dbg_stats_tpa_tx_path; ++#define VXGE_HW_DBG_STATS_TPA_TX_PATH_TX_PERMITTED_FRMS(val) \ ++ vxge_vBIT(val, 32, 32) ++ u8 unused05900[0x05900-0x058a0]; ++ ++/*0x05900*/ u64 tmac_int_status; ++#define VXGE_HW_TMAC_INT_STATUS_TXMAC_GEN_ERR_TXMAC_GEN_INT vxge_mBIT(3) ++#define VXGE_HW_TMAC_INT_STATUS_TXMAC_ECC_ERR_TXMAC_ECC_INT vxge_mBIT(7) ++/*0x05908*/ u64 tmac_int_mask; ++/*0x05910*/ u64 txmac_gen_err_reg; ++#define VXGE_HW_TXMAC_GEN_ERR_REG_TMACJ_PERMANENT_STOP vxge_mBIT(3) ++#define VXGE_HW_TXMAC_GEN_ERR_REG_TMACJ_NO_VALID_VSPORT vxge_mBIT(7) ++/*0x05918*/ u64 txmac_gen_err_mask; ++/*0x05920*/ u64 txmac_gen_err_alarm; ++/*0x05928*/ u64 txmac_ecc_err_reg; ++#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_SG_ERR vxge_mBIT(3) ++#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_DB_ERR vxge_mBIT(7) ++#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_SG_ERR vxge_mBIT(11) ++#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_DB_ERR vxge_mBIT(15) ++#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_SG_ERR vxge_mBIT(19) ++#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_DB_ERR vxge_mBIT(23) ++#define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT0_FSM_ERR vxge_mBIT(27) ++#define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT1_FSM_ERR vxge_mBIT(31) ++#define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT2_FSM_ERR vxge_mBIT(35) ++#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMACJ_FSM_ERR vxge_mBIT(39) ++/*0x05930*/ u64 txmac_ecc_err_mask; ++/*0x05938*/ u64 txmac_ecc_err_alarm; ++ u8 unused05978[0x05978-0x05940]; ++ ++/*0x05978*/ u64 dbg_stat_tx_any_frms; ++#define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT0_TX_ANY_FRMS(val) vxge_vBIT(val, 0, 8) ++#define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT1_TX_ANY_FRMS(val) vxge_vBIT(val, 8, 8) ++#define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT2_TX_ANY_FRMS(val) \ ++ vxge_vBIT(val, 16, 8) ++ u8 unused059a0[0x059a0-0x05980]; ++ ++/*0x059a0*/ u64 txmac_link_util_port[3]; ++#define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_UTILIZATION(val) \ ++ vxge_vBIT(val, 1, 7) ++#define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(val) vxge_vBIT(val, 8, 4) ++#define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_FRAC_UTIL(val) \ ++ vxge_vBIT(val, 12, 4) ++#define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_PKT_WEIGHT(val) vxge_vBIT(val, 16, 4) ++#define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_SCALE_FACTOR vxge_mBIT(23) ++/*0x059b8*/ u64 txmac_cfg0_port[3]; ++#define VXGE_HW_TXMAC_CFG0_PORT_TMAC_EN vxge_mBIT(3) ++#define VXGE_HW_TXMAC_CFG0_PORT_APPEND_PAD vxge_mBIT(7) ++#define VXGE_HW_TXMAC_CFG0_PORT_PAD_BYTE(val) vxge_vBIT(val, 8, 8) ++/*0x059d0*/ u64 txmac_cfg1_port[3]; ++#define VXGE_HW_TXMAC_CFG1_PORT_AVG_IPG(val) vxge_vBIT(val, 40, 8) ++/*0x059e8*/ u64 txmac_status_port[3]; ++#define VXGE_HW_TXMAC_STATUS_PORT_TMAC_TX_FRM_SENT vxge_mBIT(3) ++ u8 unused05a20[0x05a20-0x05a00]; ++ ++/*0x05a20*/ u64 lag_distrib_dest; ++#define VXGE_HW_LAG_DISTRIB_DEST_MAP_VPATH(n) vxge_mBIT(n) ++/*0x05a28*/ u64 lag_marker_cfg; ++#define VXGE_HW_LAG_MARKER_CFG_GEN_RCVR_EN vxge_mBIT(3) ++#define VXGE_HW_LAG_MARKER_CFG_RESP_EN vxge_mBIT(7) ++#define VXGE_HW_LAG_MARKER_CFG_RESP_TIMEOUT(val) vxge_vBIT(val, 16, 16) ++#define VXGE_HW_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(val) \ ++ vxge_vBIT(val, 32, 16) ++#define VXGE_HW_LAG_MARKER_CFG_THROTTLE_MRKR_RESP vxge_mBIT(51) ++/*0x05a30*/ u64 lag_tx_cfg; ++#define VXGE_HW_LAG_TX_CFG_INCR_TX_AGGR_STATS vxge_mBIT(3) ++#define VXGE_HW_LAG_TX_CFG_DISTRIB_ALG_SEL(val) vxge_vBIT(val, 6, 2) ++#define VXGE_HW_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL vxge_mBIT(11) ++#define VXGE_HW_LAG_TX_CFG_COLL_MAX_DELAY(val) vxge_vBIT(val, 16, 16) ++/*0x05a38*/ u64 lag_tx_status; ++#define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_EMPTIED_LINK(val) \ ++ vxge_vBIT(val, 0, 8) ++#define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKR(val) \ ++ vxge_vBIT(val, 8, 8) ++#define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKRRESP(val) \ ++ vxge_vBIT(val, 16, 8) ++ u8 unused05d48[0x05d48-0x05a40]; ++ ++/*0x05d48*/ u64 srpcim_to_mrpcim_vplane_rmsg[17]; ++#define \ ++VXGE_HAL_SRPCIM_TO_MRPCIM_VPLANE_RMSG_SWIF_SRPCIM_TO_MRPCIM_VPLANE_RMSG(val)\ ++ vxge_vBIT(val, 0, 64) ++ u8 unused06420[0x06420-0x05dd0]; ++ ++/*0x06420*/ u64 mrpcim_to_srpcim_vplane_wmsg[17]; ++#define VXGE_HW_MRPCIM_TO_SRPCIM_VPLANE_WMSG_MRPCIM_TO_SRPCIM_VPLANE_WMSG(val) \ ++ vxge_vBIT(val, 0, 64) ++/*0x064a8*/ u64 mrpcim_to_srpcim_vplane_wmsg_trig[17]; ++ ++/*0x06530*/ u64 debug_stats0; ++#define VXGE_HW_DEBUG_STATS0_RSTDROP_MSG(val) vxge_vBIT(val, 0, 32) ++#define VXGE_HW_DEBUG_STATS0_RSTDROP_CPL(val) vxge_vBIT(val, 32, 32) ++/*0x06538*/ u64 debug_stats1; ++#define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT0(val) vxge_vBIT(val, 0, 32) ++#define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT1(val) vxge_vBIT(val, 32, 32) ++/*0x06540*/ u64 debug_stats2; ++#define VXGE_HW_DEBUG_STATS2_RSTDROP_CLIENT2(val) vxge_vBIT(val, 0, 32) ++/*0x06548*/ u64 debug_stats3_vplane[17]; ++#define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_PH(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_NPH(val) vxge_vBIT(val, 16, 16) ++#define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_CPLH(val) vxge_vBIT(val, 32, 16) ++/*0x065d0*/ u64 debug_stats4_vplane[17]; ++#define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_PD(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_NPD(val) vxge_vBIT(val, 16, 16) ++#define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_CPLD(val) vxge_vBIT(val, 32, 16) ++ ++ u8 unused07000[0x07000-0x06658]; ++ ++/*0x07000*/ u64 mrpcim_general_int_status; ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PIC_INT vxge_mBIT(0) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCI_INT vxge_mBIT(1) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_RTDMA_INT vxge_mBIT(2) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_WRDMA_INT vxge_mBIT(3) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMCT_INT vxge_mBIT(4) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG1_INT vxge_mBIT(5) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG2_INT vxge_mBIT(6) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG3_INT vxge_mBIT(7) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMIFL_INT vxge_mBIT(8) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMIFU_INT vxge_mBIT(9) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG1_INT vxge_mBIT(10) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG2_INT vxge_mBIT(11) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG3_INT vxge_mBIT(12) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_XMAC_INT vxge_mBIT(13) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_RXMAC_INT vxge_mBIT(14) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_TMAC_INT vxge_mBIT(15) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3FBIF_INT vxge_mBIT(16) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_FBMC_INT vxge_mBIT(17) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3FBCT_INT vxge_mBIT(18) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_TPA_INT vxge_mBIT(19) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_DRBELL_INT vxge_mBIT(20) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_ONE_INT vxge_mBIT(21) ++#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_MSG_INT vxge_mBIT(22) ++/*0x07008*/ u64 mrpcim_general_int_mask; ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PIC_INT vxge_mBIT(0) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCI_INT vxge_mBIT(1) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_RTDMA_INT vxge_mBIT(2) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_WRDMA_INT vxge_mBIT(3) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMCT_INT vxge_mBIT(4) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG1_INT vxge_mBIT(5) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG2_INT vxge_mBIT(6) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG3_INT vxge_mBIT(7) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMIFL_INT vxge_mBIT(8) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMIFU_INT vxge_mBIT(9) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG1_INT vxge_mBIT(10) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG2_INT vxge_mBIT(11) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG3_INT vxge_mBIT(12) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_XMAC_INT vxge_mBIT(13) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_RXMAC_INT vxge_mBIT(14) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_TMAC_INT vxge_mBIT(15) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3FBIF_INT vxge_mBIT(16) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_FBMC_INT vxge_mBIT(17) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3FBCT_INT vxge_mBIT(18) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_TPA_INT vxge_mBIT(19) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_DRBELL_INT vxge_mBIT(20) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_ONE_INT vxge_mBIT(21) ++#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_MSG_INT vxge_mBIT(22) ++/*0x07010*/ u64 mrpcim_ppif_int_status; ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_INI_ERRORS_INI_INT vxge_mBIT(3) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_DMA_ERRORS_DMA_INT vxge_mBIT(7) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_TGT_ERRORS_TGT_INT vxge_mBIT(11) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CONFIG_ERRORS_CONFIG_INT vxge_mBIT(15) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_CRDT_INT vxge_mBIT(19) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_PLL_ERRORS_PLL_INT vxge_mBIT(27) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE0_CRD_INT_VPLANE0_INT\ ++ vxge_mBIT(31) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE1_CRD_INT_VPLANE1_INT\ ++ vxge_mBIT(32) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE2_CRD_INT_VPLANE2_INT\ ++ vxge_mBIT(33) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE3_CRD_INT_VPLANE3_INT\ ++ vxge_mBIT(34) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE4_CRD_INT_VPLANE4_INT\ ++ vxge_mBIT(35) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE5_CRD_INT_VPLANE5_INT\ ++ vxge_mBIT(36) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE6_CRD_INT_VPLANE6_INT\ ++ vxge_mBIT(37) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE7_CRD_INT_VPLANE7_INT\ ++ vxge_mBIT(38) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE8_CRD_INT_VPLANE8_INT\ ++ vxge_mBIT(39) ++#define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE9_CRD_INT_VPLANE9_INT\ ++ vxge_mBIT(40) ++#define \ ++VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE10_CRD_INT_VPLANE10_INT \ ++ vxge_mBIT(41) ++#define \ ++VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE11_CRD_INT_VPLANE11_INT \ ++ vxge_mBIT(42) ++#define \ ++VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE12_CRD_INT_VPLANE12_INT \ ++ vxge_mBIT(43) ++#define \ ++VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE13_CRD_INT_VPLANE13_INT \ ++ vxge_mBIT(44) ++#define \ ++VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE14_CRD_INT_VPLANE14_INT \ ++ vxge_mBIT(45) ++#define \ ++VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE15_CRD_INT_VPLANE15_INT \ ++ vxge_mBIT(46) ++#define \ ++VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE16_CRD_INT_VPLANE16_INT \ ++ vxge_mBIT(47) ++#define \ ++VXGE_HW_MRPCIM_PPIF_INT_STATUS_VPATH_TO_MRPCIM_ALARM_VPATH_TO_MRPCIM_ALARM_INT \ ++ vxge_mBIT(55) ++/*0x07018*/ u64 mrpcim_ppif_int_mask; ++ u8 unused07028[0x07028-0x07020]; ++ ++/*0x07028*/ u64 ini_errors_reg; ++#define VXGE_HW_INI_ERRORS_REG_SCPL_CPL_TIMEOUT_UNUSED_TAG vxge_mBIT(3) ++#define VXGE_HW_INI_ERRORS_REG_SCPL_CPL_TIMEOUT vxge_mBIT(7) ++#define VXGE_HW_INI_ERRORS_REG_DCPL_FSM_ERR vxge_mBIT(11) ++#define VXGE_HW_INI_ERRORS_REG_DCPL_POISON vxge_mBIT(12) ++#define VXGE_HW_INI_ERRORS_REG_DCPL_UNSUPPORTED vxge_mBIT(15) ++#define VXGE_HW_INI_ERRORS_REG_DCPL_ABORT vxge_mBIT(19) ++#define VXGE_HW_INI_ERRORS_REG_INI_TLP_ABORT vxge_mBIT(23) ++#define VXGE_HW_INI_ERRORS_REG_INI_DLLP_ABORT vxge_mBIT(27) ++#define VXGE_HW_INI_ERRORS_REG_INI_ECRC_ERR vxge_mBIT(31) ++#define VXGE_HW_INI_ERRORS_REG_INI_BUF_DB_ERR vxge_mBIT(35) ++#define VXGE_HW_INI_ERRORS_REG_INI_BUF_SG_ERR vxge_mBIT(39) ++#define VXGE_HW_INI_ERRORS_REG_INI_DATA_OVERFLOW vxge_mBIT(43) ++#define VXGE_HW_INI_ERRORS_REG_INI_HDR_OVERFLOW vxge_mBIT(47) ++#define VXGE_HW_INI_ERRORS_REG_INI_MRD_SYS_DROP vxge_mBIT(51) ++#define VXGE_HW_INI_ERRORS_REG_INI_MWR_SYS_DROP vxge_mBIT(55) ++#define VXGE_HW_INI_ERRORS_REG_INI_MRD_CLIENT_DROP vxge_mBIT(59) ++#define VXGE_HW_INI_ERRORS_REG_INI_MWR_CLIENT_DROP vxge_mBIT(63) ++/*0x07030*/ u64 ini_errors_mask; ++/*0x07038*/ u64 ini_errors_alarm; ++/*0x07040*/ u64 dma_errors_reg; ++#define VXGE_HW_DMA_ERRORS_REG_RDARB_FSM_ERR vxge_mBIT(3) ++#define VXGE_HW_DMA_ERRORS_REG_WRARB_FSM_ERR vxge_mBIT(7) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_OVERFLOW vxge_mBIT(8) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_UNDERFLOW vxge_mBIT(9) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_OVERFLOW vxge_mBIT(10) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_UNDERFLOW vxge_mBIT(11) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_HDR_OVERFLOW vxge_mBIT(12) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_HDR_UNDERFLOW vxge_mBIT(13) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_DATA_OVERFLOW vxge_mBIT(14) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_DATA_UNDERFLOW vxge_mBIT(15) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_HDR_OVERFLOW vxge_mBIT(16) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_HDR_UNDERFLOW vxge_mBIT(17) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_DATA_OVERFLOW vxge_mBIT(18) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_DATA_UNDERFLOW vxge_mBIT(19) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_OVERFLOW vxge_mBIT(20) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_UNDERFLOW vxge_mBIT(21) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_OVERFLOW vxge_mBIT(22) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_UNDERFLOW vxge_mBIT(23) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_OVERFLOW vxge_mBIT(24) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_UNDERFLOW vxge_mBIT(25) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_OVERFLOW vxge_mBIT(28) ++#define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_UNDERFLOW vxge_mBIT(29) ++#define VXGE_HW_DMA_ERRORS_REG_DBLGEN_FSM_ERR vxge_mBIT(32) ++#define VXGE_HW_DMA_ERRORS_REG_DBLGEN_CREDIT_FSM_ERR vxge_mBIT(33) ++#define VXGE_HW_DMA_ERRORS_REG_DBLGEN_DMA_WRR_SM_ERR vxge_mBIT(34) ++/*0x07048*/ u64 dma_errors_mask; ++/*0x07050*/ u64 dma_errors_alarm; ++/*0x07058*/ u64 tgt_errors_reg; ++#define VXGE_HW_TGT_ERRORS_REG_TGT_VENDOR_MSG vxge_mBIT(0) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_MSG_UNLOCK vxge_mBIT(1) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_ILLEGAL_TLP_BE vxge_mBIT(2) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_BOOT_WRITE vxge_mBIT(3) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_PIF_WR_CROSS_QWRANGE vxge_mBIT(4) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_PIF_READ_CROSS_QWRANGE vxge_mBIT(5) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_KDFC_READ vxge_mBIT(6) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_USDC_READ vxge_mBIT(7) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_USDC_WR_CROSS_QWRANGE vxge_mBIT(8) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_MSIX_BEYOND_RANGE vxge_mBIT(9) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_KDFC_POISON vxge_mBIT(10) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_USDC_POISON vxge_mBIT(11) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_PIF_POISON vxge_mBIT(12) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_MSIX_POISON vxge_mBIT(13) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_MRIOV_POISON vxge_mBIT(14) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_NOT_MEM_TLP vxge_mBIT(15) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_UNKNOWN_MEM_TLP vxge_mBIT(16) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_REQ_FSM_ERR vxge_mBIT(17) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_CPL_FSM_ERR vxge_mBIT(18) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_KDFC_PROT_ERR vxge_mBIT(19) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_SWIF_PROT_ERR vxge_mBIT(20) ++#define VXGE_HW_TGT_ERRORS_REG_TGT_MRIOV_MEM_MAP_CFG_ERR vxge_mBIT(21) ++/*0x07060*/ u64 tgt_errors_mask; ++/*0x07068*/ u64 tgt_errors_alarm; ++/*0x07070*/ u64 config_errors_reg; ++#define VXGE_HW_CONFIG_ERRORS_REG_I2C_ILLEGAL_STOP_COND vxge_mBIT(3) ++#define VXGE_HW_CONFIG_ERRORS_REG_I2C_ILLEGAL_START_COND vxge_mBIT(7) ++#define VXGE_HW_CONFIG_ERRORS_REG_I2C_EXP_RD_CNT vxge_mBIT(11) ++#define VXGE_HW_CONFIG_ERRORS_REG_I2C_EXTRA_CYCLE vxge_mBIT(15) ++#define VXGE_HW_CONFIG_ERRORS_REG_I2C_MAIN_FSM_ERR vxge_mBIT(19) ++#define VXGE_HW_CONFIG_ERRORS_REG_I2C_REQ_COLLISION vxge_mBIT(23) ++#define VXGE_HW_CONFIG_ERRORS_REG_I2C_REG_FSM_ERR vxge_mBIT(27) ++#define VXGE_HW_CONFIG_ERRORS_REG_CFGM_I2C_TIMEOUT vxge_mBIT(31) ++#define VXGE_HW_CONFIG_ERRORS_REG_RIC_I2C_TIMEOUT vxge_mBIT(35) ++#define VXGE_HW_CONFIG_ERRORS_REG_CFGM_FSM_ERR vxge_mBIT(39) ++#define VXGE_HW_CONFIG_ERRORS_REG_RIC_FSM_ERR vxge_mBIT(43) ++#define VXGE_HW_CONFIG_ERRORS_REG_PIFM_ILLEGAL_ACCESS vxge_mBIT(47) ++#define VXGE_HW_CONFIG_ERRORS_REG_PIFM_TIMEOUT vxge_mBIT(51) ++#define VXGE_HW_CONFIG_ERRORS_REG_PIFM_FSM_ERR vxge_mBIT(55) ++#define VXGE_HW_CONFIG_ERRORS_REG_PIFM_TO_FSM_ERR vxge_mBIT(59) ++#define VXGE_HW_CONFIG_ERRORS_REG_RIC_RIC_RD_TIMEOUT vxge_mBIT(63) ++/*0x07078*/ u64 config_errors_mask; ++/*0x07080*/ u64 config_errors_alarm; ++ u8 unused07090[0x07090-0x07088]; ++ ++/*0x07090*/ u64 crdt_errors_reg; ++#define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_FSM_ERR vxge_mBIT(11) ++#define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_INTCTL_ILLEGAL_CRD_DEAL \ ++ vxge_mBIT(15) ++#define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_PDA_ILLEGAL_CRD_DEAL vxge_mBIT(19) ++#define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_PCI_MSG_ILLEGAL_CRD_DEAL \ ++ vxge_mBIT(23) ++#define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_FSM_ERR vxge_mBIT(35) ++#define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_RDA_ILLEGAL_CRD_DEAL vxge_mBIT(39) ++#define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_PDA_ILLEGAL_CRD_DEAL vxge_mBIT(43) ++#define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_DBLGEN_ILLEGAL_CRD_DEAL \ ++ vxge_mBIT(47) ++/*0x07098*/ u64 crdt_errors_mask; ++/*0x070a0*/ u64 crdt_errors_alarm; ++ u8 unused070b0[0x070b0-0x070a8]; ++ ++/*0x070b0*/ u64 mrpcim_general_errors_reg; ++#define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_STATSB_FSM_ERR vxge_mBIT(3) ++#define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_XGEN_FSM_ERR vxge_mBIT(7) ++#define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_XMEM_FSM_ERR vxge_mBIT(11) ++#define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_KDFCCTL_FSM_ERR vxge_mBIT(15) ++#define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_MRIOVCTL_FSM_ERR vxge_mBIT(19) ++#define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_FLSH_ERR vxge_mBIT(23) ++#define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_ACK_ERR vxge_mBIT(27) ++#define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_CHKSUM_ERR vxge_mBIT(31) ++#define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INI_SERR_DET vxge_mBIT(35) ++#define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSIX_FSM_ERR vxge_mBIT(39) ++#define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSI_OVERFLOW vxge_mBIT(43) ++#define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_PPIF_PCI_NOT_FLUSH_DURING_SW_RESET \ ++ vxge_mBIT(47) ++#define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_PPIF_SW_RESET_FSM_ERR vxge_mBIT(51) ++/*0x070b8*/ u64 mrpcim_general_errors_mask; ++/*0x070c0*/ u64 mrpcim_general_errors_alarm; ++ u8 unused070d0[0x070d0-0x070c8]; ++ ++/*0x070d0*/ u64 pll_errors_reg; ++#define VXGE_HW_PLL_ERRORS_REG_CORE_CMG_PLL_OOL vxge_mBIT(3) ++#define VXGE_HW_PLL_ERRORS_REG_CORE_FB_PLL_OOL vxge_mBIT(7) ++#define VXGE_HW_PLL_ERRORS_REG_CORE_X_PLL_OOL vxge_mBIT(11) ++/*0x070d8*/ u64 pll_errors_mask; ++/*0x070e0*/ u64 pll_errors_alarm; ++/*0x070e8*/ u64 srpcim_to_mrpcim_alarm_reg; ++#define VXGE_HW_SRPCIM_TO_MRPCIM_ALARM_REG_PPIF_SRPCIM_TO_MRPCIM_ALARM(val) \ ++ vxge_vBIT(val, 0, 17) ++/*0x070f0*/ u64 srpcim_to_mrpcim_alarm_mask; ++/*0x070f8*/ u64 srpcim_to_mrpcim_alarm_alarm; ++/*0x07100*/ u64 vpath_to_mrpcim_alarm_reg; ++#define VXGE_HW_VPATH_TO_MRPCIM_ALARM_REG_PPIF_VPATH_TO_MRPCIM_ALARM(val) \ ++ vxge_vBIT(val, 0, 17) ++/*0x07108*/ u64 vpath_to_mrpcim_alarm_mask; ++/*0x07110*/ u64 vpath_to_mrpcim_alarm_alarm; ++ u8 unused07128[0x07128-0x07118]; ++ ++/*0x07128*/ u64 crdt_errors_vplane_reg[17]; ++#define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_CONSUME_CRDT_ERR \ ++ vxge_mBIT(3) ++#define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_CONSUME_CRDT_ERR \ ++ vxge_mBIT(7) ++#define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_RETURN_CRDT_ERR \ ++ vxge_mBIT(11) ++#define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_RETURN_CRDT_ERR \ ++ vxge_mBIT(15) ++#define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_CONSUME_CRDT_ERR \ ++ vxge_mBIT(19) ++#define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_RETURN_CRDT_ERR \ ++ vxge_mBIT(23) ++#define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_CONSUME_TAG_ERR \ ++ vxge_mBIT(27) ++#define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_RETURN_TAG_ERR \ ++ vxge_mBIT(31) ++/*0x07130*/ u64 crdt_errors_vplane_mask[17]; ++/*0x07138*/ u64 crdt_errors_vplane_alarm[17]; ++ u8 unused072f0[0x072f0-0x072c0]; ++ ++/*0x072f0*/ u64 mrpcim_rst_in_prog; ++#define VXGE_HW_MRPCIM_RST_IN_PROG_MRPCIM_RST_IN_PROG vxge_mBIT(7) ++/*0x072f8*/ u64 mrpcim_reg_modified; ++#define VXGE_HW_MRPCIM_REG_MODIFIED_MRPCIM_REG_MODIFIED vxge_mBIT(7) ++ ++ u8 unused07378[0x07378-0x07300]; ++ ++/*0x07378*/ u64 write_arb_pending; ++#define VXGE_HW_WRITE_ARB_PENDING_WRARB_WRDMA vxge_mBIT(3) ++#define VXGE_HW_WRITE_ARB_PENDING_WRARB_RTDMA vxge_mBIT(7) ++#define VXGE_HW_WRITE_ARB_PENDING_WRARB_MSG vxge_mBIT(11) ++#define VXGE_HW_WRITE_ARB_PENDING_WRARB_STATSB vxge_mBIT(15) ++#define VXGE_HW_WRITE_ARB_PENDING_WRARB_INTCTL vxge_mBIT(19) ++/*0x07380*/ u64 read_arb_pending; ++#define VXGE_HW_READ_ARB_PENDING_RDARB_WRDMA vxge_mBIT(3) ++#define VXGE_HW_READ_ARB_PENDING_RDARB_RTDMA vxge_mBIT(7) ++#define VXGE_HW_READ_ARB_PENDING_RDARB_DBLGEN vxge_mBIT(11) ++/*0x07388*/ u64 dmaif_dmadbl_pending; ++#define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_WR vxge_mBIT(0) ++#define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_RD vxge_mBIT(1) ++#define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_WR vxge_mBIT(2) ++#define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_RD vxge_mBIT(3) ++#define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_MSG_WR vxge_mBIT(4) ++#define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_STATS_WR vxge_mBIT(5) ++#define VXGE_HW_DMAIF_DMADBL_PENDING_DBLGEN_IN_PROG(val) \ ++ vxge_vBIT(val, 13, 51) ++/*0x07390*/ u64 wrcrdtarb_status0_vplane[17]; ++#define VXGE_HW_WRCRDTARB_STATUS0_VPLANE_WRCRDTARB_ABS_AVAIL_P_H(val) \ ++ vxge_vBIT(val, 0, 8) ++/*0x07418*/ u64 wrcrdtarb_status1_vplane[17]; ++#define VXGE_HW_WRCRDTARB_STATUS1_VPLANE_WRCRDTARB_ABS_AVAIL_P_D(val) \ ++ vxge_vBIT(val, 4, 12) ++ u8 unused07500[0x07500-0x074a0]; ++ ++/*0x07500*/ u64 mrpcim_general_cfg1; ++#define VXGE_HW_MRPCIM_GENERAL_CFG1_CLEAR_SERR vxge_mBIT(7) ++/*0x07508*/ u64 mrpcim_general_cfg2; ++#define VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_WR_TD vxge_mBIT(3) ++#define VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_RD_TD vxge_mBIT(7) ++#define VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_CPL_TD vxge_mBIT(11) ++#define VXGE_HW_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MWR vxge_mBIT(15) ++#define VXGE_HW_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MRD vxge_mBIT(19) ++#define VXGE_HW_MRPCIM_GENERAL_CFG2_IGNORE_VPATH_RST_FOR_MSIX vxge_mBIT(23) ++#define VXGE_HW_MRPCIM_GENERAL_CFG2_FLASH_READ_MSB vxge_mBIT(27) ++#define VXGE_HW_MRPCIM_GENERAL_CFG2_DIS_HOST_PIPELINE_WR vxge_mBIT(31) ++#define VXGE_HW_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE vxge_mBIT(43) ++#define VXGE_HW_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(val) \ ++ vxge_vBIT(val, 47, 5) ++#define VXGE_HW_MRPCIM_GENERAL_CFG2_EN_BLOCK_MSIX_DUE_TO_SERR vxge_mBIT(55) ++#define VXGE_HW_MRPCIM_GENERAL_CFG2_FORCE_SENDING_INTA vxge_mBIT(59) ++#define VXGE_HW_MRPCIM_GENERAL_CFG2_DIS_SWIF_PROT_ON_RDS vxge_mBIT(63) ++/*0x07510*/ u64 mrpcim_general_cfg3; ++#define VXGE_HW_MRPCIM_GENERAL_CFG3_PROTECTION_CA_OR_UNSUPN vxge_mBIT(0) ++#define VXGE_HW_MRPCIM_GENERAL_CFG3_ILLEGAL_RD_CA_OR_UNSUPN vxge_mBIT(3) ++#define VXGE_HW_MRPCIM_GENERAL_CFG3_RD_BYTE_SWAPEN vxge_mBIT(7) ++#define VXGE_HW_MRPCIM_GENERAL_CFG3_RD_BIT_FLIPEN vxge_mBIT(11) ++#define VXGE_HW_MRPCIM_GENERAL_CFG3_WR_BYTE_SWAPEN vxge_mBIT(15) ++#define VXGE_HW_MRPCIM_GENERAL_CFG3_WR_BIT_FLIPEN vxge_mBIT(19) ++#define VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MAX_MVFS(val) vxge_vBIT(val, 20, 16) ++#define VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MVF_TBL_SIZE(val) \ ++ vxge_vBIT(val, 36, 16) ++#define VXGE_HW_MRPCIM_GENERAL_CFG3_PF0_SW_RESET_EN vxge_mBIT(55) ++#define VXGE_HW_MRPCIM_GENERAL_CFG3_REG_MODIFIED_CFG(val) vxge_vBIT(val, 56, 2) ++#define VXGE_HW_MRPCIM_GENERAL_CFG3_CPL_ECC_ENABLE_N vxge_mBIT(59) ++#define VXGE_HW_MRPCIM_GENERAL_CFG3_BYPASS_DAISY_CHAIN vxge_mBIT(63) ++/*0x07518*/ u64 mrpcim_stats_start_host_addr; ++#define VXGE_HW_MRPCIM_STATS_START_HOST_ADDR_MRPCIM_STATS_START_HOST_ADDR(val)\ ++ vxge_vBIT(val, 0, 57) ++ ++ u8 unused07950[0x07950-0x07520]; ++ ++/*0x07950*/ u64 rdcrdtarb_cfg0; ++#define VXGE_HW_RDCRDTARB_CFG0_RDA_MAX_OUTSTANDING_RDS(val) \ ++ vxge_vBIT(val, 18, 6) ++#define VXGE_HW_RDCRDTARB_CFG0_PDA_MAX_OUTSTANDING_RDS(val) \ ++ vxge_vBIT(val, 26, 6) ++#define VXGE_HW_RDCRDTARB_CFG0_DBLGEN_MAX_OUTSTANDING_RDS(val) \ ++ vxge_vBIT(val, 34, 6) ++#define VXGE_HW_RDCRDTARB_CFG0_WAIT_CNT(val) vxge_vBIT(val, 48, 4) ++#define VXGE_HW_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val) vxge_vBIT(val, 54, 6) ++#define VXGE_HW_RDCRDTARB_CFG0_EN_XON vxge_mBIT(63) ++ u8 unused07be8[0x07be8-0x07958]; ++ ++/*0x07be8*/ u64 bf_sw_reset; ++#define VXGE_HW_BF_SW_RESET_BF_SW_RESET(val) vxge_vBIT(val, 0, 8) ++/*0x07bf0*/ u64 sw_reset_status; ++#define VXGE_HW_SW_RESET_STATUS_RESET_CMPLT vxge_mBIT(7) ++#define VXGE_HW_SW_RESET_STATUS_INIT_CMPLT vxge_mBIT(15) ++ u8 unused07c20[0x07c20-0x07bf8]; ++ ++/* 0x07c20 */ u64 sw_reset_cfg1; ++#define VXGE_HW_SW_RESET_CFG1_TYPE vxge_mBIT(0) ++#define VXGE_HW_SW_RESET_CFG1_WAIT_TIME_FOR_FLUSH_PCI(val) vxge_vBIT(val, 7, 25) ++#define VXGE_HW_SW_RESET_CFG1_SOPR_ASSERT_TIME(val) vxge_vBIT(val, 32, 4) ++#define VXGE_HW_SW_RESET_CFG1_WAIT_TIME_AFTER_RESET(val) vxge_vBIT(val, 38, 25) ++ u8 unused07d30[0x07d30-0x07c28]; ++ ++/*0x07d30*/ u64 mrpcim_debug_stats0; ++#define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_WR_DROP(val) vxge_vBIT(val, 0, 32) ++#define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_RD_DROP(val) vxge_vBIT(val, 32, 32) ++/*0x07d38*/ u64 mrpcim_debug_stats1_vplane[17]; ++#define VXGE_HW_MRPCIM_DEBUG_STATS1_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(val) \ ++ vxge_vBIT(val, 32, 32) ++/*0x07dc0*/ u64 mrpcim_debug_stats2_vplane[17]; ++#define VXGE_HW_MRPCIM_DEBUG_STATS2_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(val) \ ++ vxge_vBIT(val, 32, 32) ++/*0x07e48*/ u64 mrpcim_debug_stats3_vplane[17]; ++#define VXGE_HW_MRPCIM_DEBUG_STATS3_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(val) \ ++ vxge_vBIT(val, 32, 32) ++/*0x07ed0*/ u64 mrpcim_debug_stats4; ++#define VXGE_HW_MRPCIM_DEBUG_STATS4_INI_WR_VPIN_DROP(val) vxge_vBIT(val, 0, 32) ++#define VXGE_HW_MRPCIM_DEBUG_STATS4_INI_RD_VPIN_DROP(val) \ ++ vxge_vBIT(val, 32, 32) ++/*0x07ed8*/ u64 genstats_count01; ++#define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT1(val) vxge_vBIT(val, 0, 32) ++#define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT0(val) vxge_vBIT(val, 32, 32) ++/*0x07ee0*/ u64 genstats_count23; ++#define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT3(val) vxge_vBIT(val, 0, 32) ++#define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT2(val) vxge_vBIT(val, 32, 32) ++/*0x07ee8*/ u64 genstats_count4; ++#define VXGE_HW_GENSTATS_COUNT4_GENSTATS_COUNT4(val) vxge_vBIT(val, 32, 32) ++/*0x07ef0*/ u64 genstats_count5; ++#define VXGE_HW_GENSTATS_COUNT5_GENSTATS_COUNT5(val) vxge_vBIT(val, 32, 32) ++ ++ u8 unused07f08[0x07f08-0x07ef8]; ++ ++/*0x07f08*/ u64 genstats_cfg[6]; ++#define VXGE_HW_GENSTATS_CFG_DTYPE_SEL(val) vxge_vBIT(val, 3, 5) ++#define VXGE_HW_GENSTATS_CFG_CLIENT_NO_SEL(val) vxge_vBIT(val, 9, 3) ++#define VXGE_HW_GENSTATS_CFG_WR_RD_CPL_SEL(val) vxge_vBIT(val, 14, 2) ++#define VXGE_HW_GENSTATS_CFG_VPATH_SEL(val) vxge_vBIT(val, 31, 17) ++/*0x07f38*/ u64 genstat_64bit_cfg; ++#define VXGE_HW_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS0 vxge_mBIT(3) ++#define VXGE_HW_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS2 vxge_mBIT(7) ++ u8 unused08000[0x08000-0x07f40]; ++/*0x08000*/ u64 gcmg3_int_status; ++#define VXGE_HW_GCMG3_INT_STATUS_GSTC_ERR0_GSTC0_INT vxge_mBIT(0) ++#define VXGE_HW_GCMG3_INT_STATUS_GSTC_ERR1_GSTC1_INT vxge_mBIT(1) ++#define VXGE_HW_GCMG3_INT_STATUS_GH2L_ERR0_GH2L0_INT vxge_mBIT(2) ++#define VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR_GH2L1_INT vxge_mBIT(3) ++#define VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR2_GH2L2_INT vxge_mBIT(4) ++#define VXGE_HW_GCMG3_INT_STATUS_GH2L_SMERR0_GH2L3_INT vxge_mBIT(5) ++#define VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR3_GH2L4_INT vxge_mBIT(6) ++/*0x08008*/ u64 gcmg3_int_mask; ++ u8 unused09000[0x09000-0x8010]; ++ ++/*0x09000*/ u64 g3ifcmd_fb_int_status; ++#define VXGE_HW_G3IFCMD_FB_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) ++/*0x09008*/ u64 g3ifcmd_fb_int_mask; ++/*0x09010*/ u64 g3ifcmd_fb_err_reg; ++#define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_CK_DLL_LOCK vxge_mBIT(6) ++#define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_SM_ERR vxge_mBIT(7) ++#define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \ ++ vxge_vBIT(val, 24, 8) ++#define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_IOCAL_FAULT vxge_mBIT(55) ++/*0x09018*/ u64 g3ifcmd_fb_err_mask; ++/*0x09020*/ u64 g3ifcmd_fb_err_alarm; ++ ++ u8 unused09400[0x09400-0x09028]; ++ ++/*0x09400*/ u64 g3ifcmd_cmu_int_status; ++#define VXGE_HW_G3IFCMD_CMU_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) ++/*0x09408*/ u64 g3ifcmd_cmu_int_mask; ++/*0x09410*/ u64 g3ifcmd_cmu_err_reg; ++#define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_CK_DLL_LOCK vxge_mBIT(6) ++#define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_SM_ERR vxge_mBIT(7) ++#define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \ ++ vxge_vBIT(val, 24, 8) ++#define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_IOCAL_FAULT vxge_mBIT(55) ++/*0x09418*/ u64 g3ifcmd_cmu_err_mask; ++/*0x09420*/ u64 g3ifcmd_cmu_err_alarm; ++ ++ u8 unused09800[0x09800-0x09428]; ++ ++/*0x09800*/ u64 g3ifcmd_cml_int_status; ++#define VXGE_HW_G3IFCMD_CML_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) ++/*0x09808*/ u64 g3ifcmd_cml_int_mask; ++/*0x09810*/ u64 g3ifcmd_cml_err_reg; ++#define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_CK_DLL_LOCK vxge_mBIT(6) ++#define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_SM_ERR vxge_mBIT(7) ++#define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \ ++ vxge_vBIT(val, 24, 8) ++#define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_IOCAL_FAULT vxge_mBIT(55) ++/*0x09818*/ u64 g3ifcmd_cml_err_mask; ++/*0x09820*/ u64 g3ifcmd_cml_err_alarm; ++ u8 unused09b00[0x09b00-0x09828]; ++ ++/*0x09b00*/ u64 vpath_to_vplane_map[17]; ++#define VXGE_HW_VPATH_TO_VPLANE_MAP_VPATH_TO_VPLANE_MAP(val) \ ++ vxge_vBIT(val, 3, 5) ++ u8 unused09c30[0x09c30-0x09b88]; ++ ++/*0x09c30*/ u64 xgxs_cfg_port[2]; ++#define VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_LOS(val) vxge_vBIT(val, 16, 4) ++#define VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_VALID(val) vxge_vBIT(val, 20, 4) ++#define VXGE_HW_XGXS_CFG_PORT_SEL_INFO_0 vxge_mBIT(27) ++#define VXGE_HW_XGXS_CFG_PORT_SEL_INFO_1(val) vxge_vBIT(val, 29, 3) ++#define VXGE_HW_XGXS_CFG_PORT_TX_LANE0_SKEW(val) vxge_vBIT(val, 32, 4) ++#define VXGE_HW_XGXS_CFG_PORT_TX_LANE1_SKEW(val) vxge_vBIT(val, 36, 4) ++#define VXGE_HW_XGXS_CFG_PORT_TX_LANE2_SKEW(val) vxge_vBIT(val, 40, 4) ++#define VXGE_HW_XGXS_CFG_PORT_TX_LANE3_SKEW(val) vxge_vBIT(val, 44, 4) ++/*0x09c40*/ u64 xgxs_rxber_cfg_port[2]; ++#define VXGE_HW_XGXS_RXBER_CFG_PORT_INTERVAL_DUR(val) vxge_vBIT(val, 0, 4) ++#define VXGE_HW_XGXS_RXBER_CFG_PORT_RXGXS_INTERVAL_CNT(val) \ ++ vxge_vBIT(val, 16, 48) ++/*0x09c50*/ u64 xgxs_rxber_status_port[2]; ++#define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_A_ERR_CNT(val) \ ++ vxge_vBIT(val, 0, 16) ++#define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_B_ERR_CNT(val) \ ++ vxge_vBIT(val, 16, 16) ++#define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_C_ERR_CNT(val) \ ++ vxge_vBIT(val, 32, 16) ++#define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_D_ERR_CNT(val) \ ++ vxge_vBIT(val, 48, 16) ++/*0x09c60*/ u64 xgxs_status_port[2]; ++#define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_TX_ACTIVITY(val) vxge_vBIT(val, 0, 4) ++#define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_RX_ACTIVITY(val) vxge_vBIT(val, 4, 4) ++#define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_FIFO_ERR BIT(11) ++#define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_BYTE_SYNC_LOST(val) \ ++ vxge_vBIT(val, 12, 4) ++#define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_ERR(val) vxge_vBIT(val, 16, 4) ++#define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_ALIGNMENT_ERR vxge_mBIT(23) ++#define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_DEC_ERR(val) vxge_vBIT(val, 24, 8) ++#define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_INS_REQ(val) \ ++ vxge_vBIT(val, 32, 4) ++#define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_DEL_REQ(val) \ ++ vxge_vBIT(val, 36, 4) ++/*0x09c70*/ u64 xgxs_pma_reset_port[2]; ++#define VXGE_HW_XGXS_PMA_RESET_PORT_SERDES_RESET(val) vxge_vBIT(val, 0, 8) ++ u8 unused09c90[0x09c90-0x09c80]; ++ ++/*0x09c90*/ u64 xgxs_static_cfg_port[2]; ++#define VXGE_HW_XGXS_STATIC_CFG_PORT_FW_CTRL_SERDES vxge_mBIT(3) ++ u8 unused09d40[0x09d40-0x09ca0]; ++ ++/*0x09d40*/ u64 xgxs_info_port[2]; ++#define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_0(val) vxge_vBIT(val, 0, 32) ++#define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_1(val) vxge_vBIT(val, 32, 32) ++/*0x09d50*/ u64 ratemgmt_cfg_port[2]; ++#define VXGE_HW_RATEMGMT_CFG_PORT_MODE(val) vxge_vBIT(val, 2, 2) ++#define VXGE_HW_RATEMGMT_CFG_PORT_RATE vxge_mBIT(7) ++#define VXGE_HW_RATEMGMT_CFG_PORT_FIXED_USE_FSM vxge_mBIT(11) ++#define VXGE_HW_RATEMGMT_CFG_PORT_ANTP_USE_FSM vxge_mBIT(15) ++#define VXGE_HW_RATEMGMT_CFG_PORT_ANBE_USE_FSM vxge_mBIT(19) ++/*0x09d60*/ u64 ratemgmt_status_port[2]; ++#define VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_COMPLETE vxge_mBIT(3) ++#define VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_RATE vxge_mBIT(7) ++#define VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_MAC_MATCHES_PHY vxge_mBIT(11) ++ u8 unused09d80[0x09d80-0x09d70]; ++ ++/*0x09d80*/ u64 ratemgmt_fixed_cfg_port[2]; ++#define VXGE_HW_RATEMGMT_FIXED_CFG_PORT_RESTART vxge_mBIT(7) ++/*0x09d90*/ u64 ratemgmt_antp_cfg_port[2]; ++#define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_RESTART vxge_mBIT(7) ++#define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_USE_PREAMBLE_EXT_PHY vxge_mBIT(11) ++#define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_USE_ACT_SEL vxge_mBIT(15) ++#define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_RETRY_PHY_QUERY(val) \ ++ vxge_vBIT(val, 16, 4) ++#define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_WAIT_MDIO_RESPONSE(val) \ ++ vxge_vBIT(val, 20, 4) ++#define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_LDOWN_REAUTO_RESPONSE(val) \ ++ vxge_vBIT(val, 24, 4) ++#define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_10G vxge_mBIT(31) ++#define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_1G vxge_mBIT(35) ++/*0x09da0*/ u64 ratemgmt_anbe_cfg_port[2]; ++#define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_RESTART vxge_mBIT(7) ++#define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_10G_KX4_ENABLE \ ++ vxge_mBIT(11) ++#define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_1G_KX_ENABLE \ ++ vxge_mBIT(15) ++#define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_10G_KX4(val) vxge_vBIT(val, 16, 4) ++#define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_1G_KX(val) vxge_vBIT(val, 20, 4) ++#define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_DME_EXCHANGE(val) vxge_vBIT(val, 24, 4) ++#define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_10G_KX4 vxge_mBIT(31) ++#define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_1G_KX vxge_mBIT(35) ++/*0x09db0*/ u64 anbe_cfg_port[2]; ++#define VXGE_HW_ANBE_CFG_PORT_RESET_CFG_REGS(val) vxge_vBIT(val, 0, 8) ++#define VXGE_HW_ANBE_CFG_PORT_ALIGN_10G_KX4_OVERRIDE(val) vxge_vBIT(val, 10, 2) ++#define VXGE_HW_ANBE_CFG_PORT_SYNC_1G_KX_OVERRIDE(val) vxge_vBIT(val, 14, 2) ++/*0x09dc0*/ u64 anbe_mgr_ctrl_port[2]; ++#define VXGE_HW_ANBE_MGR_CTRL_PORT_WE vxge_mBIT(3) ++#define VXGE_HW_ANBE_MGR_CTRL_PORT_STROBE vxge_mBIT(7) ++#define VXGE_HW_ANBE_MGR_CTRL_PORT_ADDR(val) vxge_vBIT(val, 15, 9) ++#define VXGE_HW_ANBE_MGR_CTRL_PORT_DATA(val) vxge_vBIT(val, 32, 32) ++ u8 unused09de0[0x09de0-0x09dd0]; ++ ++/*0x09de0*/ u64 anbe_fw_mstr_port[2]; ++#define VXGE_HW_ANBE_FW_MSTR_PORT_CONNECT_BEAN_TO_SERDES vxge_mBIT(3) ++#define VXGE_HW_ANBE_FW_MSTR_PORT_TX_ZEROES_TO_SERDES vxge_mBIT(7) ++/*0x09df0*/ u64 anbe_hwfsm_gen_status_port[2]; ++#define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_PD \ ++ vxge_mBIT(3) ++#define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_DME \ ++ vxge_mBIT(7) ++#define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_PD \ ++ vxge_mBIT(11) ++#define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_DME \ ++ vxge_mBIT(15) ++#define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANBEFSM_STATE(val) \ ++ vxge_vBIT(val, 18, 6) ++#define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_NEXT_PAGE_RECEIVED \ ++ vxge_mBIT(27) ++#define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_BASE_PAGE_RECEIVED \ ++ vxge_mBIT(35) ++#define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_AUTONEG_COMPLETE \ ++ vxge_mBIT(39) ++#define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NP_BEFORE_BP \ ++ vxge_mBIT(43) ++#define \ ++VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_AN_COMPLETE_BEFORE_BP \ ++ vxge_mBIT(47) ++#define \ ++VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_AN_COMPLETE_BEFORE_NP \ ++vxge_mBIT(51) ++#define \ ++VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_MODE_WHEN_AN_COMPLETE \ ++ vxge_mBIT(55) ++#define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_BP(val) \ ++ vxge_vBIT(val, 56, 4) ++#define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_NP(val) \ ++ vxge_vBIT(val, 60, 4) ++/*0x09e00*/ u64 anbe_hwfsm_bp_status_port[2]; ++#define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ENABLE \ ++ vxge_mBIT(32) ++#define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ABILITY \ ++ vxge_mBIT(33) ++#define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KR_CAPABLE \ ++ vxge_mBIT(40) ++#define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KX4_CAPABLE \ ++ vxge_mBIT(41) ++#define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_1G_KX_CAPABLE \ ++ vxge_mBIT(42) ++#define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_TX_NONCE(val) \ ++ vxge_vBIT(val, 43, 5) ++#define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP vxge_mBIT(48) ++#define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK vxge_mBIT(49) ++#define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_REMOTE_FAULT \ ++ vxge_mBIT(50) ++#define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ASM_DIR vxge_mBIT(51) ++#define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_PAUSE vxge_mBIT(53) ++#define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ECHOED_NONCE(val) \ ++ vxge_vBIT(val, 54, 5) ++#define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x09e10*/ u64 anbe_hwfsm_np_status_port[2]; ++#define VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_47_TO_32(val) \ ++ vxge_vBIT(val, 16, 16) ++#define VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_31_TO_0(val) \ ++ vxge_vBIT(val, 32, 32) ++ u8 unused09e30[0x09e30-0x09e20]; ++ ++/*0x09e30*/ u64 antp_gen_cfg_port[2]; ++/*0x09e40*/ u64 antp_hwfsm_gen_status_port[2]; ++#define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G vxge_mBIT(3) ++#define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G vxge_mBIT(7) ++#define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANTPFSM_STATE(val) \ ++ vxge_vBIT(val, 10, 6) ++#define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_AUTONEG_COMPLETE \ ++ vxge_mBIT(23) ++#define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_LP_XNP \ ++ vxge_mBIT(27) ++#define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_GOT_LP_XNP vxge_mBIT(31) ++#define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_MESSAGE_CODE \ ++ vxge_mBIT(35) ++#define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_HCD \ ++ vxge_mBIT(43) ++#define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_FOUND_HCD vxge_mBIT(47) ++#define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_INVALID_RATE \ ++ vxge_mBIT(51) ++#define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_VALID_RATE vxge_mBIT(55) ++#define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_PERSISTENT_LDOWN \ ++ vxge_mBIT(59) ++/*0x09e50*/ u64 antp_hwfsm_bp_status_port[2]; ++#define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP vxge_mBIT(0) ++#define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK vxge_mBIT(1) ++#define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_RF vxge_mBIT(2) ++#define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_XNP vxge_mBIT(3) ++#define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ABILITY_FIELD(val) \ ++ vxge_vBIT(val, 4, 7) ++#define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val) \ ++ vxge_vBIT(val, 11, 5) ++/*0x09e60*/ u64 antp_hwfsm_xnp_status_port[2]; ++#define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_NP vxge_mBIT(0) ++#define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK vxge_mBIT(1) ++#define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MP vxge_mBIT(2) ++#define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK2 vxge_mBIT(3) ++#define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_TOGGLE vxge_mBIT(4) ++#define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MESSAGE_CODE(val) \ ++ vxge_vBIT(val, 5, 11) ++#define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD1(val) \ ++ vxge_vBIT(val, 16, 16) ++#define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD2(val) \ ++ vxge_vBIT(val, 32, 16) ++/*0x09e70*/ u64 mdio_mgr_access_port[2]; ++#define VXGE_HW_MDIO_MGR_ACCESS_PORT_STROBE_ONE BIT(3) ++#define VXGE_HW_MDIO_MGR_ACCESS_PORT_OP_TYPE(val) vxge_vBIT(val, 5, 3) ++#define VXGE_HW_MDIO_MGR_ACCESS_PORT_DEVAD(val) vxge_vBIT(val, 11, 5) ++#define VXGE_HW_MDIO_MGR_ACCESS_PORT_ADDR(val) vxge_vBIT(val, 16, 16) ++#define VXGE_HW_MDIO_MGR_ACCESS_PORT_DATA(val) vxge_vBIT(val, 32, 16) ++#define VXGE_HW_MDIO_MGR_ACCESS_PORT_ST_PATTERN(val) vxge_vBIT(val, 49, 2) ++#define VXGE_HW_MDIO_MGR_ACCESS_PORT_PREAMBLE vxge_mBIT(51) ++#define VXGE_HW_MDIO_MGR_ACCESS_PORT_PRTAD(val) vxge_vBIT(val, 55, 5) ++#define VXGE_HW_MDIO_MGR_ACCESS_PORT_STROBE_TWO vxge_mBIT(63) ++ u8 unused0a200[0x0a200-0x09e80]; ++/*0x0a200*/ u64 xmac_vsport_choices_vh[17]; ++#define VXGE_HW_XMAC_VSPORT_CHOICES_VH_VSPORT_VECTOR(val) vxge_vBIT(val, 0, 17) ++ u8 unused0a400[0x0a400-0x0a288]; ++ ++/*0x0a400*/ u64 rx_thresh_cfg_vp[17]; ++#define VXGE_HW_RX_THRESH_CFG_VP_PAUSE_LOW_THR(val) vxge_vBIT(val, 0, 8) ++#define VXGE_HW_RX_THRESH_CFG_VP_PAUSE_HIGH_THR(val) vxge_vBIT(val, 8, 8) ++#define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_0(val) vxge_vBIT(val, 16, 8) ++#define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_1(val) vxge_vBIT(val, 24, 8) ++#define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_2(val) vxge_vBIT(val, 32, 8) ++#define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_3(val) vxge_vBIT(val, 40, 8) ++ u8 unused0ac90[0x0ac90-0x0a488]; ++} __attribute((packed)); ++ ++/*VXGE_HW_SRPCIM_REGS_H*/ ++struct vxge_hw_srpcim_reg { ++ ++/*0x00000*/ u64 tim_mr2sr_resource_assignment_vh; ++#define VXGE_HW_TIM_MR2SR_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) \ ++ vxge_vBIT(val, 0, 32) ++ u8 unused00100[0x00100-0x00008]; ++ ++/*0x00100*/ u64 srpcim_pcipif_int_status; ++#define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_MRPCIM_MSG_INT BIT(3) ++#define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT BIT(7) ++#define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_SRPCIM_SPARE_R1_SRPCIM_SPARE_R1_INT \ ++ BIT(11) ++/*0x00108*/ u64 srpcim_pcipif_int_mask; ++/*0x00110*/ u64 mrpcim_msg_reg; ++#define VXGE_HW_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT BIT(3) ++/*0x00118*/ u64 mrpcim_msg_mask; ++/*0x00120*/ u64 mrpcim_msg_alarm; ++/*0x00128*/ u64 vpath_msg_reg; ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT BIT(0) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT BIT(1) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT BIT(2) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH3_TO_SRPCIM_RMSG_INT BIT(3) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH4_TO_SRPCIM_RMSG_INT BIT(4) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH5_TO_SRPCIM_RMSG_INT BIT(5) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH6_TO_SRPCIM_RMSG_INT BIT(6) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH7_TO_SRPCIM_RMSG_INT BIT(7) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH8_TO_SRPCIM_RMSG_INT BIT(8) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH9_TO_SRPCIM_RMSG_INT BIT(9) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH10_TO_SRPCIM_RMSG_INT BIT(10) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH11_TO_SRPCIM_RMSG_INT BIT(11) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH12_TO_SRPCIM_RMSG_INT BIT(12) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH13_TO_SRPCIM_RMSG_INT BIT(13) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH14_TO_SRPCIM_RMSG_INT BIT(14) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH15_TO_SRPCIM_RMSG_INT BIT(15) ++#define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH16_TO_SRPCIM_RMSG_INT BIT(16) ++/*0x00130*/ u64 vpath_msg_mask; ++/*0x00138*/ u64 vpath_msg_alarm; ++ u8 unused00160[0x00160-0x00140]; ++ ++/*0x00160*/ u64 srpcim_to_mrpcim_wmsg; ++#define VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_SRPCIM_TO_MRPCIM_WMSG(val) \ ++ vxge_vBIT(val, 0, 64) ++/*0x00168*/ u64 srpcim_to_mrpcim_wmsg_trig; ++#define VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_TRIG_SRPCIM_TO_MRPCIM_WMSG_TRIG BIT(0) ++/*0x00170*/ u64 mrpcim_to_srpcim_rmsg; ++#define VXGE_HW_MRPCIM_TO_SRPCIM_RMSG_SWIF_MRPCIM_TO_SRPCIM_RMSG(val) \ ++ vxge_vBIT(val, 0, 64) ++/*0x00178*/ u64 vpath_to_srpcim_rmsg_sel; ++#define VXGE_HW_VPATH_TO_SRPCIM_RMSG_SEL_VPATH_TO_SRPCIM_RMSG_SEL(val) \ ++ vxge_vBIT(val, 0, 5) ++/*0x00180*/ u64 vpath_to_srpcim_rmsg; ++#define VXGE_HW_VPATH_TO_SRPCIM_RMSG_SWIF_VPATH_TO_SRPCIM_RMSG(val) \ ++ vxge_vBIT(val, 0, 64) ++ u8 unused00200[0x00200-0x00188]; ++ ++/*0x00200*/ u64 srpcim_general_int_status; ++#define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PIC_INT BIT(0) ++#define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PCI_INT BIT(3) ++#define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_XMAC_INT BIT(7) ++ u8 unused00210[0x00210-0x00208]; ++ ++/*0x00210*/ u64 srpcim_general_int_mask; ++#define VXGE_HW_SRPCIM_GENERAL_INT_MASK_PIC_INT BIT(0) ++#define VXGE_HW_SRPCIM_GENERAL_INT_MASK_PCI_INT BIT(3) ++#define VXGE_HW_SRPCIM_GENERAL_INT_MASK_XMAC_INT BIT(7) ++ u8 unused00220[0x00220-0x00218]; ++ ++/*0x00220*/ u64 srpcim_ppif_int_status; ++ ++/*0x00228*/ u64 srpcim_ppif_int_mask; ++/*0x00230*/ u64 srpcim_gen_errors_reg; ++#define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_STATUS_ERR BIT(3) ++#define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_UNCOR_ERR BIT(7) ++#define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_COR_ERR BIT(11) ++#define VXGE_HW_SRPCIM_GEN_ERRORS_REG_INTCTRL_SCHED_INT BIT(15) ++#define VXGE_HW_SRPCIM_GEN_ERRORS_REG_INI_SERR_DET BIT(19) ++#define VXGE_HW_SRPCIM_GEN_ERRORS_REG_TGT_PF_ILLEGAL_ACCESS BIT(23) ++/*0x00238*/ u64 srpcim_gen_errors_mask; ++/*0x00240*/ u64 srpcim_gen_errors_alarm; ++/*0x00248*/ u64 mrpcim_to_srpcim_alarm_reg; ++#define VXGE_HW_MRPCIM_TO_SRPCIM_ALARM_REG_PPIF_MRPCIM_TO_SRPCIM_ALARM BIT(3) ++/*0x00250*/ u64 mrpcim_to_srpcim_alarm_mask; ++/*0x00258*/ u64 mrpcim_to_srpcim_alarm_alarm; ++/*0x00260*/ u64 vpath_to_srpcim_alarm_reg; ++ ++/*0x00268*/ u64 vpath_to_srpcim_alarm_mask; ++/*0x00270*/ u64 vpath_to_srpcim_alarm_alarm; ++ u8 unused00280[0x00280-0x00278]; ++ ++/*0x00280*/ u64 pf_sw_reset; ++#define VXGE_HW_PF_SW_RESET_PF_SW_RESET(val) vxge_vBIT(val, 0, 8) ++/*0x00288*/ u64 srpcim_general_cfg1; ++#define VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BYTE_SWAPEN BIT(19) ++#define VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BIT_FLIPEN BIT(23) ++#define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_SWAPEN BIT(27) ++#define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_FLIPEN BIT(31) ++#define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_SWAPEN BIT(35) ++#define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_FLIPEN BIT(39) ++/*0x00290*/ u64 srpcim_interrupt_cfg1; ++#define VXGE_HW_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(val) vxge_vBIT(val, 1, 7) ++#define VXGE_HW_SRPCIM_INTERRUPT_CFG1_TRAFFIC_CLASS(val) vxge_vBIT(val, 9, 3) ++ u8 unused002a8[0x002a8-0x00298]; ++ ++/*0x002a8*/ u64 srpcim_clear_msix_mask; ++#define VXGE_HW_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK BIT(0) ++/*0x002b0*/ u64 srpcim_set_msix_mask; ++#define VXGE_HW_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK BIT(0) ++/*0x002b8*/ u64 srpcim_clr_msix_one_shot; ++#define VXGE_HW_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT BIT(0) ++/*0x002c0*/ u64 srpcim_rst_in_prog; ++#define VXGE_HW_SRPCIM_RST_IN_PROG_SRPCIM_RST_IN_PROG BIT(7) ++/*0x002c8*/ u64 srpcim_reg_modified; ++#define VXGE_HW_SRPCIM_REG_MODIFIED_SRPCIM_REG_MODIFIED BIT(7) ++/*0x002d0*/ u64 tgt_pf_illegal_access; ++#define VXGE_HW_TGT_PF_ILLEGAL_ACCESS_SWIF_REGION(val) vxge_vBIT(val, 1, 7) ++/*0x002d8*/ u64 srpcim_msix_status; ++#define VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_MASK BIT(3) ++#define VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_PENDING_VECTOR BIT(7) ++ u8 unused00880[0x00880-0x002e0]; ++ ++/*0x00880*/ u64 xgmac_sr_int_status; ++#define VXGE_HW_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_ASIC_NTWK_SR_INT BIT(3) ++/*0x00888*/ u64 xgmac_sr_int_mask; ++/*0x00890*/ u64 asic_ntwk_sr_err_reg; ++#define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT BIT(3) ++#define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK BIT(7) ++#define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT_OCCURRED \ ++ BIT(11) ++#define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK_OCCURRED BIT(15) ++/*0x00898*/ u64 asic_ntwk_sr_err_mask; ++/*0x008a0*/ u64 asic_ntwk_sr_err_alarm; ++ u8 unused008c0[0x008c0-0x008a8]; ++ ++/*0x008c0*/ u64 xmac_vsport_choices_sr_clone; ++#define VXGE_HW_XMAC_VSPORT_CHOICES_SR_CLONE_VSPORT_VECTOR(val) \ ++ vxge_vBIT(val, 0, 17) ++ u8 unused00900[0x00900-0x008c8]; ++ ++/*0x00900*/ u64 mr_rqa_top_prty_for_vh; ++#define VXGE_HW_MR_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00908*/ u64 umq_vh_data_list_empty; ++#define VXGE_HW_UMQ_VH_DATA_LIST_EMPTY_ROCRC_UMQ_VH_DATA_LIST_EMPTY \ ++ BIT(0) ++/*0x00910*/ u64 wde_cfg; ++#define VXGE_HW_WDE_CFG_NS0_FORCE_MWB_START BIT(0) ++#define VXGE_HW_WDE_CFG_NS0_FORCE_MWB_END BIT(1) ++#define VXGE_HW_WDE_CFG_NS0_FORCE_QB_START BIT(2) ++#define VXGE_HW_WDE_CFG_NS0_FORCE_QB_END BIT(3) ++#define VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_START BIT(4) ++#define VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_END BIT(5) ++#define VXGE_HW_WDE_CFG_NS0_MWB_OPT_EN BIT(6) ++#define VXGE_HW_WDE_CFG_NS0_QB_OPT_EN BIT(7) ++#define VXGE_HW_WDE_CFG_NS0_MPSB_OPT_EN BIT(8) ++#define VXGE_HW_WDE_CFG_NS1_FORCE_MWB_START BIT(9) ++#define VXGE_HW_WDE_CFG_NS1_FORCE_MWB_END BIT(10) ++#define VXGE_HW_WDE_CFG_NS1_FORCE_QB_START BIT(11) ++#define VXGE_HW_WDE_CFG_NS1_FORCE_QB_END BIT(12) ++#define VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_START BIT(13) ++#define VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_END BIT(14) ++#define VXGE_HW_WDE_CFG_NS1_MWB_OPT_EN BIT(15) ++#define VXGE_HW_WDE_CFG_NS1_QB_OPT_EN BIT(16) ++#define VXGE_HW_WDE_CFG_NS1_MPSB_OPT_EN BIT(17) ++#define VXGE_HW_WDE_CFG_DISABLE_QPAD_FOR_UNALIGNED_ADDR BIT(19) ++#define VXGE_HW_WDE_CFG_ALIGNMENT_PREFERENCE(val) vxge_vBIT(val, 30, 2) ++#define VXGE_HW_WDE_CFG_MEM_WORD_SIZE(val) vxge_vBIT(val, 46, 2) ++ ++} __attribute((packed)); ++ ++/*VXGE_HW_VPMGMT_REGS_H*/ ++struct vxge_hw_vpmgmt_reg { ++ ++ u8 unused00040[0x00040-0x00000]; ++ ++/*0x00040*/ u64 vpath_to_func_map_cfg1; ++#define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_VPATH_TO_FUNC_MAP_CFG1(val) \ ++ vxge_vBIT(val, 3, 5) ++/*0x00048*/ u64 vpath_is_first; ++#define VXGE_HW_VPATH_IS_FIRST_VPATH_IS_FIRST vxge_mBIT(3) ++/*0x00050*/ u64 srpcim_to_vpath_wmsg; ++#define VXGE_HW_SRPCIM_TO_VPATH_WMSG_SRPCIM_TO_VPATH_WMSG(val) \ ++ vxge_vBIT(val, 0, 64) ++/*0x00058*/ u64 srpcim_to_vpath_wmsg_trig; ++#define VXGE_HW_SRPCIM_TO_VPATH_WMSG_TRIG_SRPCIM_TO_VPATH_WMSG_TRIG \ ++ vxge_mBIT(0) ++ u8 unused00100[0x00100-0x00060]; ++ ++/*0x00100*/ u64 tim_vpath_assignment; ++#define VXGE_HW_TIM_VPATH_ASSIGNMENT_BMAP_ROOT(val) vxge_vBIT(val, 0, 32) ++ u8 unused00140[0x00140-0x00108]; ++ ++/*0x00140*/ u64 rqa_top_prty_for_vp; ++#define VXGE_HW_RQA_TOP_PRTY_FOR_VP_RQA_TOP_PRTY_FOR_VP(val) \ ++ vxge_vBIT(val, 59, 5) ++ u8 unused001c0[0x001c0-0x00148]; ++ ++/*0x001c0*/ u64 rxmac_rx_pa_cfg0_vpmgmt_clone; ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IGNORE_FRAME_ERR vxge_mBIT(3) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_SNAP_AB_N vxge_mBIT(7) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_HAO vxge_mBIT(18) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_MOBILE_IPV6_HDRS \ ++ vxge_mBIT(19) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IPV6_STOP_SEARCHING \ ++ vxge_mBIT(23) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_NO_PS_IF_UNKNOWN vxge_mBIT(27) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_ETYPE vxge_mBIT(35) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L3_CSUM_ERR \ ++ vxge_mBIT(39) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR \ ++ vxge_mBIT(43) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L4_CSUM_ERR \ ++ vxge_mBIT(47) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR \ ++ vxge_mBIT(51) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_RPA_ERR \ ++ vxge_mBIT(55) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_RPA_ERR \ ++ vxge_mBIT(59) ++#define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_JUMBO_SNAP_EN vxge_mBIT(63) ++/*0x001c8*/ u64 rts_mgr_cfg0_vpmgmt_clone; ++#define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_RTS_DP_SP_PRIORITY vxge_mBIT(3) ++#define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_FLEX_L4PRTCL_VALUE(val) \ ++ vxge_vBIT(val, 24, 8) ++#define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_ICMP_TRASH vxge_mBIT(35) ++#define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_TCPSYN_TRASH vxge_mBIT(39) ++#define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_ZL4PYLD_TRASH vxge_mBIT(43) ++#define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_TCP_TRASH vxge_mBIT(47) ++#define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_UDP_TRASH vxge_mBIT(51) ++#define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_FLEX_TRASH vxge_mBIT(55) ++#define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_IPFRAG_TRASH vxge_mBIT(59) ++/*0x001d0*/ u64 rts_mgr_criteria_priority_vpmgmt_clone; ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ETYPE(val) \ ++ vxge_vBIT(val, 5, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ICMP_TCPSYN(val) \ ++ vxge_vBIT(val, 9, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PN(val) \ ++ vxge_vBIT(val, 13, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RANGE_L4PN(val) \ ++ vxge_vBIT(val, 17, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RTH_IT(val) \ ++ vxge_vBIT(val, 21, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_DS(val) \ ++ vxge_vBIT(val, 25, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_QOS(val) \ ++ vxge_vBIT(val, 29, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ZL4PYLD(val) \ ++ vxge_vBIT(val, 33, 3) ++#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PRTCL(val) \ ++ vxge_vBIT(val, 37, 3) ++/*0x001d8*/ u64 rxmac_cfg0_port_vpmgmt_clone[3]; ++#define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_RMAC_EN vxge_mBIT(3) ++#define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS vxge_mBIT(7) ++#define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_DISCARD_PFRM vxge_mBIT(11) ++#define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_FCS_ERR vxge_mBIT(15) ++#define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LONG_ERR vxge_mBIT(19) ++#define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_USIZED_ERR vxge_mBIT(23) ++#define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LEN_MISMATCH \ ++ vxge_mBIT(27) ++#define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_MAX_PYLD_LEN(val) \ ++ vxge_vBIT(val, 50, 14) ++/*0x001f0*/ u64 rxmac_pause_cfg_port_vpmgmt_clone[3]; ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_GEN_EN vxge_mBIT(3) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_RCV_EN vxge_mBIT(7) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_ACCEL_SEND(val) \ ++ vxge_vBIT(val, 9, 3) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_DUAL_THR vxge_mBIT(15) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_HIGH_PTIME(val) \ ++ vxge_vBIT(val, 20, 16) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_FCS_ERR \ ++ vxge_mBIT(39) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_LEN_ERR \ ++ vxge_mBIT(43) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_LIMITER_EN vxge_mBIT(47) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_MAX_LIMIT(val) \ ++ vxge_vBIT(val, 48, 8) ++#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_PERMIT_RATEMGMT_CTRL \ ++ vxge_mBIT(59) ++ u8 unused00240[0x00240-0x00208]; ++ ++/*0x00240*/ u64 xmac_vsport_choices_vp; ++#define VXGE_HW_XMAC_VSPORT_CHOICES_VP_VSPORT_VECTOR(val) vxge_vBIT(val, 0, 17) ++ u8 unused00260[0x00260-0x00248]; ++ ++/*0x00260*/ u64 xgmac_gen_status_vpmgmt_clone; ++#define VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK vxge_mBIT(3) ++#define VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_DATA_RATE \ ++ vxge_mBIT(11) ++/*0x00268*/ u64 xgmac_status_port_vpmgmt_clone[2]; ++#define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_REMOTE_FAULT \ ++ vxge_mBIT(3) ++#define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_LOCAL_FAULT vxge_mBIT(7) ++#define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_MAC_PHY_LAYER_AVAIL \ ++ vxge_mBIT(11) ++#define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_PORT_OK vxge_mBIT(15) ++/*0x00278*/ u64 xmac_gen_cfg_vpmgmt_clone; ++#define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_RATEMGMT_MAC_RATE_SEL(val) \ ++ vxge_vBIT(val, 2, 2) ++#define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_TX_HEAD_DROP_WHEN_FAULT \ ++ vxge_mBIT(7) ++#define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_FAULT_BEHAVIOUR vxge_mBIT(27) ++#define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_UP(val) \ ++ vxge_vBIT(val, 28, 4) ++#define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_DOWN(val) \ ++ vxge_vBIT(val, 32, 4) ++/*0x00280*/ u64 xmac_timestamp_vpmgmt_clone; ++#define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_EN vxge_mBIT(3) ++#define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_USE_LINK_ID(val) \ ++ vxge_vBIT(val, 6, 2) ++#define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_INTERVAL(val) vxge_vBIT(val, 12, 4) ++#define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_TIMER_RESTART vxge_mBIT(19) ++#define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_XMACJ_ROLLOVER_CNT(val) \ ++ vxge_vBIT(val, 32, 16) ++/*0x00288*/ u64 xmac_stats_gen_cfg_vpmgmt_clone; ++#define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_PRTAGGR_CUM_TIMER(val) \ ++ vxge_vBIT(val, 4, 4) ++#define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VPATH_CUM_TIMER(val) \ ++ vxge_vBIT(val, 8, 4) ++#define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VLAN_HANDLING vxge_mBIT(15) ++/*0x00290*/ u64 xmac_cfg_port_vpmgmt_clone[3]; ++#define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_LOOPBACK vxge_mBIT(3) ++#define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_REVERSE_LOOPBACK \ ++ vxge_mBIT(7) ++#define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_TX_BEHAV vxge_mBIT(11) ++#define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_RX_BEHAV vxge_mBIT(15) ++ u8 unused002c0[0x002c0-0x002a8]; ++ ++/*0x002c0*/ u64 txmac_gen_cfg0_vpmgmt_clone; ++#define VXGE_HW_TXMAC_GEN_CFG0_VPMGMT_CLONE_CHOSEN_TX_PORT vxge_mBIT(7) ++/*0x002c8*/ u64 txmac_cfg0_port_vpmgmt_clone[3]; ++#define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_TMAC_EN vxge_mBIT(3) ++#define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_APPEND_PAD vxge_mBIT(7) ++#define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_PAD_BYTE(val) vxge_vBIT(val, 8, 8) ++ u8 unused00300[0x00300-0x002e0]; ++ ++/*0x00300*/ u64 wol_mp_crc; ++#define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32) ++#define VXGE_HW_WOL_MP_CRC_RC_EN vxge_mBIT(63) ++/*0x00308*/ u64 wol_mp_mask_a; ++#define VXGE_HW_WOL_MP_MASK_A_MASK(val) vxge_vBIT(val, 0, 64) ++/*0x00310*/ u64 wol_mp_mask_b; ++#define VXGE_HW_WOL_MP_MASK_B_MASK(val) vxge_vBIT(val, 0, 64) ++ u8 unused00360[0x00360-0x00318]; ++ ++/*0x00360*/ u64 fau_pa_cfg_vpmgmt_clone; ++#define VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L4_COMP_CSUM vxge_mBIT(3) ++#define VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_INCL_CF vxge_mBIT(7) ++#define VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_COMP_CSUM vxge_mBIT(11) ++/*0x00368*/ u64 rx_datapath_util_vp_clone; ++#define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_UTILIZATION(val) \ ++ vxge_vBIT(val, 7, 9) ++#define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_UTIL_CFG(val) \ ++ vxge_vBIT(val, 16, 4) ++#define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_FRAC_UTIL(val) \ ++ vxge_vBIT(val, 20, 4) ++#define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_PKT_WEIGHT(val) \ ++ vxge_vBIT(val, 24, 4) ++ u8 unused00380[0x00380-0x00370]; ++ ++/*0x00380*/ u64 tx_datapath_util_vp_clone; ++#define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_UTILIZATION(val) \ ++ vxge_vBIT(val, 7, 9) ++#define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_UTIL_CFG(val) \ ++ vxge_vBIT(val, 16, 4) ++#define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_FRAC_UTIL(val) \ ++ vxge_vBIT(val, 20, 4) ++#define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_PKT_WEIGHT(val) \ ++ vxge_vBIT(val, 24, 4) ++ ++} __attribute((packed)); ++ ++struct vxge_hw_vpath_reg { ++ ++ u8 unused00300[0x00300]; ++ ++/*0x00300*/ u64 usdc_vpath; ++#define VXGE_HW_USDC_VPATH_SGRP_ASSIGN(val) vxge_vBIT(val, 0, 32) ++ u8 unused00a00[0x00a00-0x00308]; ++ ++/*0x00a00*/ u64 wrdma_alarm_status; ++#define VXGE_HW_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT vxge_mBIT(1) ++/*0x00a08*/ u64 wrdma_alarm_mask; ++ u8 unused00a30[0x00a30-0x00a10]; ++ ++/*0x00a30*/ u64 prc_alarm_reg; ++#define VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP vxge_mBIT(0) ++#define VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ERR vxge_mBIT(1) ++#define VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT vxge_mBIT(2) ++#define VXGE_HW_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR vxge_mBIT(3) ++/*0x00a38*/ u64 prc_alarm_mask; ++/*0x00a40*/ u64 prc_alarm_alarm; ++/*0x00a48*/ u64 prc_cfg1; ++#define VXGE_HW_PRC_CFG1_RX_TIMER_VAL(val) vxge_vBIT(val, 3, 29) ++#define VXGE_HW_PRC_CFG1_TIM_RING_BUMP_INT_ENABLE vxge_mBIT(34) ++#define VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE vxge_mBIT(35) ++#define VXGE_HW_PRC_CFG1_GREEDY_RETURN vxge_mBIT(36) ++#define VXGE_HW_PRC_CFG1_QUICK_SHOT vxge_mBIT(37) ++#define VXGE_HW_PRC_CFG1_RX_TIMER_CI vxge_mBIT(39) ++#define VXGE_HW_PRC_CFG1_RESET_TIMER_ON_RXD_RET(val) vxge_vBIT(val, 40, 2) ++ u8 unused00a60[0x00a60-0x00a50]; ++ ++/*0x00a60*/ u64 prc_cfg4; ++#define VXGE_HW_PRC_CFG4_IN_SVC vxge_mBIT(7) ++#define VXGE_HW_PRC_CFG4_RING_MODE(val) vxge_vBIT(val, 14, 2) ++#define VXGE_HW_PRC_CFG4_RXD_NO_SNOOP vxge_mBIT(22) ++#define VXGE_HW_PRC_CFG4_FRM_NO_SNOOP vxge_mBIT(23) ++#define VXGE_HW_PRC_CFG4_RTH_DISABLE vxge_mBIT(31) ++#define VXGE_HW_PRC_CFG4_IGNORE_OWNERSHIP vxge_mBIT(32) ++#define VXGE_HW_PRC_CFG4_SIGNAL_BENIGN_OVFLW vxge_mBIT(36) ++#define VXGE_HW_PRC_CFG4_BIMODAL_INTERRUPT vxge_mBIT(37) ++#define VXGE_HW_PRC_CFG4_BACKOFF_INTERVAL(val) vxge_vBIT(val, 40, 24) ++/*0x00a68*/ u64 prc_cfg5; ++#define VXGE_HW_PRC_CFG5_RXD0_ADD(val) vxge_vBIT(val, 0, 61) ++/*0x00a70*/ u64 prc_cfg6; ++#define VXGE_HW_PRC_CFG6_FRM_PAD_EN vxge_mBIT(0) ++#define VXGE_HW_PRC_CFG6_QSIZE_ALIGNED_RXD vxge_mBIT(2) ++#define VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN vxge_mBIT(5) ++#define VXGE_HW_PRC_CFG6_L3_CPC_TRSFR_CODE_EN vxge_mBIT(8) ++#define VXGE_HW_PRC_CFG6_L4_CPC_TRSFR_CODE_EN vxge_mBIT(9) ++#define VXGE_HW_PRC_CFG6_RXD_CRXDT(val) vxge_vBIT(val, 23, 9) ++#define VXGE_HW_PRC_CFG6_RXD_SPAT(val) vxge_vBIT(val, 36, 9) ++/*0x00a78*/ u64 prc_cfg7; ++#define VXGE_HW_PRC_CFG7_SCATTER_MODE(val) vxge_vBIT(val, 6, 2) ++#define VXGE_HW_PRC_CFG7_SMART_SCAT_EN vxge_mBIT(11) ++#define VXGE_HW_PRC_CFG7_RXD_NS_CHG_EN vxge_mBIT(12) ++#define VXGE_HW_PRC_CFG7_NO_HDR_SEPARATION vxge_mBIT(14) ++#define VXGE_HW_PRC_CFG7_RXD_BUFF_SIZE_MASK(val) vxge_vBIT(val, 20, 4) ++#define VXGE_HW_PRC_CFG7_BUFF_SIZE0_MASK(val) vxge_vBIT(val, 27, 5) ++/*0x00a80*/ u64 tim_dest_addr; ++#define VXGE_HW_TIM_DEST_ADDR_TIM_DEST_ADDR(val) vxge_vBIT(val, 0, 64) ++/*0x00a88*/ u64 prc_rxd_doorbell; ++#define VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val) vxge_vBIT(val, 48, 16) ++/*0x00a90*/ u64 rqa_prty_for_vp; ++#define VXGE_HW_RQA_PRTY_FOR_VP_RQA_PRTY_FOR_VP(val) vxge_vBIT(val, 59, 5) ++/*0x00a98*/ u64 rxdmem_size; ++#define VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val) vxge_vBIT(val, 51, 13) ++/*0x00aa0*/ u64 frm_in_progress_cnt; ++#define VXGE_HW_FRM_IN_PROGRESS_CNT_PRC_FRM_IN_PROGRESS_CNT(val) \ ++ vxge_vBIT(val, 59, 5) ++/*0x00aa8*/ u64 rx_multi_cast_stats; ++#define VXGE_HW_RX_MULTI_CAST_STATS_FRAME_DISCARD(val) vxge_vBIT(val, 48, 16) ++/*0x00ab0*/ u64 rx_frm_transferred; ++#define VXGE_HW_RX_FRM_TRANSFERRED_RX_FRM_TRANSFERRED(val) \ ++ vxge_vBIT(val, 32, 32) ++/*0x00ab8*/ u64 rxd_returned; ++#define VXGE_HW_RXD_RETURNED_RXD_RETURNED(val) vxge_vBIT(val, 48, 16) ++ u8 unused00c00[0x00c00-0x00ac0]; ++ ++/*0x00c00*/ u64 kdfc_fifo_trpl_partition; ++#define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(val) vxge_vBIT(val, 17, 15) ++#define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(val) vxge_vBIT(val, 33, 15) ++#define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_2(val) vxge_vBIT(val, 49, 15) ++/*0x00c08*/ u64 kdfc_fifo_trpl_ctrl; ++#define VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE vxge_mBIT(7) ++/*0x00c10*/ u64 kdfc_trpl_fifo_0_ctrl; ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(val) vxge_vBIT(val, 14, 2) ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_FLIP_EN vxge_mBIT(22) ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN vxge_mBIT(23) ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2) ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_CTRL_STRUC vxge_mBIT(28) ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_ADD_PAD vxge_mBIT(29) ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_NO_SNOOP vxge_mBIT(30) ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_RLX_ORD vxge_mBIT(31) ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(val) vxge_vBIT(val, 32, 8) ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7) ++#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16) ++/*0x00c18*/ u64 kdfc_trpl_fifo_1_ctrl; ++#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE(val) vxge_vBIT(val, 14, 2) ++#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_FLIP_EN vxge_mBIT(22) ++#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SWAP_EN vxge_mBIT(23) ++#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2) ++#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_CTRL_STRUC vxge_mBIT(28) ++#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_ADD_PAD vxge_mBIT(29) ++#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_NO_SNOOP vxge_mBIT(30) ++#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_RLX_ORD vxge_mBIT(31) ++#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SELECT(val) vxge_vBIT(val, 32, 8) ++#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7) ++#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16) ++/*0x00c20*/ u64 kdfc_trpl_fifo_2_ctrl; ++#define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_FLIP_EN vxge_mBIT(22) ++#define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_SWAP_EN vxge_mBIT(23) ++#define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2) ++#define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_CTRL_STRUC vxge_mBIT(28) ++#define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_ADD_PAD vxge_mBIT(29) ++#define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_NO_SNOOP vxge_mBIT(30) ++#define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_RLX_ORD vxge_mBIT(31) ++#define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_SELECT(val) vxge_vBIT(val, 32, 8) ++#define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7) ++#define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16) ++/*0x00c28*/ u64 kdfc_trpl_fifo_0_wb_address; ++#define VXGE_HW_KDFC_TRPL_FIFO_0_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64) ++/*0x00c30*/ u64 kdfc_trpl_fifo_1_wb_address; ++#define VXGE_HW_KDFC_TRPL_FIFO_1_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64) ++/*0x00c38*/ u64 kdfc_trpl_fifo_2_wb_address; ++#define VXGE_HW_KDFC_TRPL_FIFO_2_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64) ++/*0x00c40*/ u64 kdfc_trpl_fifo_offset; ++#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR0(val) vxge_vBIT(val, 1, 15) ++#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR1(val) vxge_vBIT(val, 17, 15) ++#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR2(val) vxge_vBIT(val, 33, 15) ++/*0x00c48*/ u64 kdfc_drbl_triplet_total; ++#define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_KDFC_MAX_SIZE(val) \ ++ vxge_vBIT(val, 17, 15) ++ u8 unused00c60[0x00c60-0x00c50]; ++ ++/*0x00c60*/ u64 usdc_drbl_ctrl; ++#define VXGE_HW_USDC_DRBL_CTRL_FLIP_EN vxge_mBIT(22) ++#define VXGE_HW_USDC_DRBL_CTRL_SWAP_EN vxge_mBIT(23) ++/*0x00c68*/ u64 usdc_vp_ready; ++#define VXGE_HW_USDC_VP_READY_USDC_HTN_READY vxge_mBIT(7) ++#define VXGE_HW_USDC_VP_READY_USDC_SRQ_READY vxge_mBIT(15) ++#define VXGE_HW_USDC_VP_READY_USDC_CQRQ_READY vxge_mBIT(23) ++/*0x00c70*/ u64 kdfc_status; ++#define VXGE_HW_KDFC_STATUS_KDFC_WRR_0_READY vxge_mBIT(0) ++#define VXGE_HW_KDFC_STATUS_KDFC_WRR_1_READY vxge_mBIT(1) ++#define VXGE_HW_KDFC_STATUS_KDFC_WRR_2_READY vxge_mBIT(2) ++ u8 unused00c80[0x00c80-0x00c78]; ++ ++/*0x00c80*/ u64 xmac_rpa_vcfg; ++#define VXGE_HW_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH vxge_mBIT(3) ++#define VXGE_HW_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH vxge_mBIT(7) ++#define VXGE_HW_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH vxge_mBIT(11) ++#define VXGE_HW_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH vxge_mBIT(15) ++#define VXGE_HW_XMAC_RPA_VCFG_L4_INCL_CF vxge_mBIT(19) ++#define VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG vxge_mBIT(23) ++/*0x00c88*/ u64 rxmac_vcfg0; ++#define VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(val) vxge_vBIT(val, 2, 14) ++#define VXGE_HW_RXMAC_VCFG0_RTS_USE_MIN_LEN vxge_mBIT(19) ++#define VXGE_HW_RXMAC_VCFG0_RTS_MIN_FRM_LEN(val) vxge_vBIT(val, 26, 14) ++#define VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN vxge_mBIT(43) ++#define VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN vxge_mBIT(47) ++#define VXGE_HW_RXMAC_VCFG0_BCAST_EN vxge_mBIT(51) ++#define VXGE_HW_RXMAC_VCFG0_ALL_VID_EN vxge_mBIT(55) ++/*0x00c90*/ u64 rxmac_vcfg1; ++#define VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(val) vxge_vBIT(val, 42, 2) ++#define VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE vxge_mBIT(47) ++#define VXGE_HW_RXMAC_VCFG1_CONTRIB_L2_FLOW vxge_mBIT(51) ++/*0x00c98*/ u64 rts_access_steer_ctrl; ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(val) vxge_vBIT(val, 1, 7) ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(val) vxge_vBIT(val, 8, 4) ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE vxge_mBIT(15) ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_BEHAV_TBL_SEL vxge_mBIT(23) ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL vxge_mBIT(27) ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS vxge_mBIT(0) ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(val) vxge_vBIT(val, 40, 8) ++/* To be used by the privileged driver */ ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_VHN(val) vxge_vBIT(val, 48, 8) ++#define VXGE_HW_RTS_ACCESS_STEER_CTRL_VFID(val) vxge_vBIT(val, 56, 8) ++/*0x00ca0*/ u64 rts_access_steer_data0; ++#define VXGE_HW_RTS_ACCESS_STEER_DATA0_DATA(val) vxge_vBIT(val, 0, 64) ++/*0x00ca8*/ u64 rts_access_steer_data1; ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_DATA(val) vxge_vBIT(val, 0, 64) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_PRIV_MODE_EN vxge_mBIT(54) ++#define VXGE_HW_RTS_ACCESS_STEER_DATA1_PRIV_MODE_VPN(val) vxge_vBIT(val, 55, 5) ++ u8 unused00d00[0x00d00-0x00cb0]; ++ ++/*0x00d00*/ u64 xmac_vsport_choice; ++#define VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(val) vxge_vBIT(val, 3, 5) ++/*0x00d08*/ u64 xmac_stats_cfg; ++/*0x00d10*/ u64 xmac_stats_access_cmd; ++#define VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(val) vxge_vBIT(val, 6, 2) ++#define VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE vxge_mBIT(15) ++#define VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8) ++/*0x00d18*/ u64 xmac_stats_access_data; ++#define VXGE_HW_XMAC_STATS_ACCESS_DATA_XSMGR_DATA(val) vxge_vBIT(val, 0, 64) ++/*0x00d20*/ u64 asic_ntwk_vp_ctrl; ++#define VXGE_HW_ASIC_NTWK_VP_CTRL_REQ_TEST_NTWK vxge_mBIT(3) ++#define VXGE_HW_ASIC_NTWK_VP_CTRL_XMACJ_SHOW_PORT_INFO vxge_mBIT(55) ++#define VXGE_HW_ASIC_NTWK_VP_CTRL_XMACJ_PORT_NUM vxge_mBIT(63) ++ u8 unused00d30[0x00d30-0x00d28]; ++ ++/*0x00d30*/ u64 xgmac_vp_int_status; ++#define VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT \ ++ vxge_mBIT(3) ++/*0x00d38*/ u64 xgmac_vp_int_mask; ++/*0x00d40*/ u64 asic_ntwk_vp_err_reg; ++#define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT vxge_mBIT(3) ++#define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK vxge_mBIT(7) ++#define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR \ ++ vxge_mBIT(11) ++#define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR \ ++ vxge_mBIT(15) ++#define VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT \ ++ vxge_mBIT(19) ++#define VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK vxge_mBIT(23) ++/*0x00d48*/ u64 asic_ntwk_vp_err_mask; ++/*0x00d50*/ u64 asic_ntwk_vp_err_alarm; ++ u8 unused00d80[0x00d80-0x00d58]; ++ ++/*0x00d80*/ u64 rtdma_bw_ctrl; ++#define VXGE_HW_RTDMA_BW_CTRL_BW_CTRL_EN vxge_mBIT(39) ++#define VXGE_HW_RTDMA_BW_CTRL_DESIRED_BW(val) vxge_vBIT(val, 46, 18) ++/*0x00d88*/ u64 rtdma_rd_optimization_ctrl; ++#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_GEN_INT_AFTER_ABORT vxge_mBIT(3) ++#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_MODE(val) vxge_vBIT(val, 6, 2) ++#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_PATTERN(val) vxge_vBIT(val, 8, 8) ++#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE vxge_mBIT(19) ++#define VXGE_HW_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ ++#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val) \ ++ vxge_vBIT(val, 21, 3) ++#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK_EN vxge_mBIT(28) ++#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK(val) \ ++ vxge_vBIT(val, 29, 3) ++#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN vxge_mBIT(35) ++#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(val) \ ++ vxge_vBIT(val, 37, 3) ++#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_WAIT_FOR_SPACE vxge_mBIT(43) ++#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_FILL_THRESH(val) \ ++ vxge_vBIT(val, 51, 5) ++#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY_EN vxge_mBIT(59) ++#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY(val) \ ++ vxge_vBIT(val, 61, 3) ++/*0x00d90*/ u64 pda_pcc_job_monitor; ++#define VXGE_HW_PDA_PCC_JOB_MONITOR_PDA_PCC_JOB_STATUS vxge_mBIT(7) ++/*0x00d98*/ u64 tx_protocol_assist_cfg; ++#define VXGE_HW_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN vxge_mBIT(6) ++#define VXGE_HW_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING vxge_mBIT(7) ++ u8 unused01000[0x01000-0x00da0]; ++ ++/*0x01000*/ u64 tim_cfg1_int_num[4]; ++#define VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(val) vxge_vBIT(val, 6, 26) ++#define VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN vxge_mBIT(35) ++#define VXGE_HW_TIM_CFG1_INT_NUM_TXFRM_CNT_EN vxge_mBIT(36) ++#define VXGE_HW_TIM_CFG1_INT_NUM_TXD_CNT_EN vxge_mBIT(37) ++#define VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC vxge_mBIT(38) ++#define VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI vxge_mBIT(39) ++#define VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(val) vxge_vBIT(val, 41, 7) ++#define VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(val) vxge_vBIT(val, 49, 7) ++#define VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(val) vxge_vBIT(val, 57, 7) ++/*0x01020*/ u64 tim_cfg2_int_num[4]; ++#define VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(val) vxge_vBIT(val, 16, 16) ++#define VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(val) vxge_vBIT(val, 32, 16) ++#define VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(val) vxge_vBIT(val, 48, 16) ++/*0x01040*/ u64 tim_cfg3_int_num[4]; ++#define VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI vxge_mBIT(0) ++#define VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(val) vxge_vBIT(val, 1, 4) ++#define VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(val) vxge_vBIT(val, 6, 26) ++#define VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(val) vxge_vBIT(val, 32, 6) ++#define VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(val) vxge_vBIT(val, 38, 26) ++/*0x01060*/ u64 tim_wrkld_clc; ++#define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(val) vxge_vBIT(val, 0, 32) ++#define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(val) vxge_vBIT(val, 35, 5) ++#define VXGE_HW_TIM_WRKLD_CLC_CNT_FRM_BYTE vxge_mBIT(40) ++#define VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(val) vxge_vBIT(val, 41, 2) ++#define VXGE_HW_TIM_WRKLD_CLC_CNT_LNK_EN vxge_mBIT(43) ++#define VXGE_HW_TIM_WRKLD_CLC_HOST_UTIL(val) vxge_vBIT(val, 57, 7) ++/*0x01068*/ u64 tim_bitmap; ++#define VXGE_HW_TIM_BITMAP_MASK(val) vxge_vBIT(val, 0, 32) ++#define VXGE_HW_TIM_BITMAP_LLROOT_RXD_EN vxge_mBIT(32) ++#define VXGE_HW_TIM_BITMAP_LLROOT_TXD_EN vxge_mBIT(33) ++/*0x01070*/ u64 tim_ring_assn; ++#define VXGE_HW_TIM_RING_ASSN_INT_NUM(val) vxge_vBIT(val, 6, 2) ++/*0x01078*/ u64 tim_remap; ++#define VXGE_HW_TIM_REMAP_TX_EN vxge_mBIT(5) ++#define VXGE_HW_TIM_REMAP_RX_EN vxge_mBIT(6) ++#define VXGE_HW_TIM_REMAP_OFFLOAD_EN vxge_mBIT(7) ++#define VXGE_HW_TIM_REMAP_TO_VPATH_NUM(val) vxge_vBIT(val, 11, 5) ++/*0x01080*/ u64 tim_vpath_map; ++#define VXGE_HW_TIM_VPATH_MAP_BMAP_ROOT(val) vxge_vBIT(val, 0, 32) ++/*0x01088*/ u64 tim_pci_cfg; ++#define VXGE_HW_TIM_PCI_CFG_ADD_PAD vxge_mBIT(7) ++#define VXGE_HW_TIM_PCI_CFG_NO_SNOOP vxge_mBIT(15) ++#define VXGE_HW_TIM_PCI_CFG_RELAXED vxge_mBIT(23) ++#define VXGE_HW_TIM_PCI_CFG_CTL_STR vxge_mBIT(31) ++ u8 unused01100[0x01100-0x01090]; ++ ++/*0x01100*/ u64 sgrp_assign; ++#define VXGE_HW_SGRP_ASSIGN_SGRP_ASSIGN(val) vxge_vBIT(val, 0, 64) ++/*0x01108*/ u64 sgrp_aoa_and_result; ++#define VXGE_HW_SGRP_AOA_AND_RESULT_PET_SGRP_AOA_AND_RESULT(val) \ ++ vxge_vBIT(val, 0, 64) ++/*0x01110*/ u64 rpe_pci_cfg; ++#define VXGE_HW_RPE_PCI_CFG_PAD_LRO_DATA_ENABLE vxge_mBIT(7) ++#define VXGE_HW_RPE_PCI_CFG_PAD_LRO_HDR_ENABLE vxge_mBIT(8) ++#define VXGE_HW_RPE_PCI_CFG_PAD_LRO_CQE_ENABLE vxge_mBIT(9) ++#define VXGE_HW_RPE_PCI_CFG_PAD_NONLL_CQE_ENABLE vxge_mBIT(10) ++#define VXGE_HW_RPE_PCI_CFG_PAD_BASE_LL_CQE_ENABLE vxge_mBIT(11) ++#define VXGE_HW_RPE_PCI_CFG_PAD_LL_CQE_IDATA_ENABLE vxge_mBIT(12) ++#define VXGE_HW_RPE_PCI_CFG_PAD_CQRQ_IR_ENABLE vxge_mBIT(13) ++#define VXGE_HW_RPE_PCI_CFG_PAD_CQSQ_IR_ENABLE vxge_mBIT(14) ++#define VXGE_HW_RPE_PCI_CFG_PAD_CQRR_IR_ENABLE vxge_mBIT(15) ++#define VXGE_HW_RPE_PCI_CFG_NOSNOOP_DATA vxge_mBIT(18) ++#define VXGE_HW_RPE_PCI_CFG_NOSNOOP_NONLL_CQE vxge_mBIT(19) ++#define VXGE_HW_RPE_PCI_CFG_NOSNOOP_LL_CQE vxge_mBIT(20) ++#define VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQRQ_IR vxge_mBIT(21) ++#define VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQSQ_IR vxge_mBIT(22) ++#define VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQRR_IR vxge_mBIT(23) ++#define VXGE_HW_RPE_PCI_CFG_RELAXED_DATA vxge_mBIT(26) ++#define VXGE_HW_RPE_PCI_CFG_RELAXED_NONLL_CQE vxge_mBIT(27) ++#define VXGE_HW_RPE_PCI_CFG_RELAXED_LL_CQE vxge_mBIT(28) ++#define VXGE_HW_RPE_PCI_CFG_RELAXED_CQRQ_IR vxge_mBIT(29) ++#define VXGE_HW_RPE_PCI_CFG_RELAXED_CQSQ_IR vxge_mBIT(30) ++#define VXGE_HW_RPE_PCI_CFG_RELAXED_CQRR_IR vxge_mBIT(31) ++/*0x01118*/ u64 rpe_lro_cfg; ++#define VXGE_HW_RPE_LRO_CFG_SUPPRESS_LRO_ETH_TRLR vxge_mBIT(7) ++#define VXGE_HW_RPE_LRO_CFG_ALLOW_LRO_SNAP_SNAPJUMBO_MRG vxge_mBIT(11) ++#define VXGE_HW_RPE_LRO_CFG_ALLOW_LRO_LLC_LLCJUMBO_MRG vxge_mBIT(15) ++#define VXGE_HW_RPE_LRO_CFG_INCL_ACK_CNT_IN_CQE vxge_mBIT(23) ++/*0x01120*/ u64 pe_mr2vp_ack_blk_limit; ++#define VXGE_HW_PE_MR2VP_ACK_BLK_LIMIT_BLK_LIMIT(val) vxge_vBIT(val, 32, 32) ++/*0x01128*/ u64 pe_mr2vp_rirr_lirr_blk_limit; ++#define VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_RIRR_BLK_LIMIT(val) \ ++ vxge_vBIT(val, 0, 32) ++#define VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_LIRR_BLK_LIMIT(val) \ ++ vxge_vBIT(val, 32, 32) ++/*0x01130*/ u64 txpe_pci_nce_cfg; ++#define VXGE_HW_TXPE_PCI_NCE_CFG_NCE_THRESH(val) vxge_vBIT(val, 0, 32) ++#define VXGE_HW_TXPE_PCI_NCE_CFG_PAD_TOWI_ENABLE vxge_mBIT(55) ++#define VXGE_HW_TXPE_PCI_NCE_CFG_NOSNOOP_TOWI vxge_mBIT(63) ++ u8 unused01180[0x01180-0x01138]; ++ ++/*0x01180*/ u64 msg_qpad_en_cfg; ++#define VXGE_HW_MSG_QPAD_EN_CFG_UMQ_BWR_READ vxge_mBIT(3) ++#define VXGE_HW_MSG_QPAD_EN_CFG_DMQ_BWR_READ vxge_mBIT(7) ++#define VXGE_HW_MSG_QPAD_EN_CFG_MXP_GENDMA_READ vxge_mBIT(11) ++#define VXGE_HW_MSG_QPAD_EN_CFG_UXP_GENDMA_READ vxge_mBIT(15) ++#define VXGE_HW_MSG_QPAD_EN_CFG_UMQ_MSG_WRITE vxge_mBIT(19) ++#define VXGE_HW_MSG_QPAD_EN_CFG_UMQDMQ_IR_WRITE vxge_mBIT(23) ++#define VXGE_HW_MSG_QPAD_EN_CFG_MXP_GENDMA_WRITE vxge_mBIT(27) ++#define VXGE_HW_MSG_QPAD_EN_CFG_UXP_GENDMA_WRITE vxge_mBIT(31) ++/*0x01188*/ u64 msg_pci_cfg; ++#define VXGE_HW_MSG_PCI_CFG_GENDMA_NO_SNOOP vxge_mBIT(3) ++#define VXGE_HW_MSG_PCI_CFG_UMQDMQ_IR_NO_SNOOP vxge_mBIT(7) ++#define VXGE_HW_MSG_PCI_CFG_UMQ_NO_SNOOP vxge_mBIT(11) ++#define VXGE_HW_MSG_PCI_CFG_DMQ_NO_SNOOP vxge_mBIT(15) ++/*0x01190*/ u64 umqdmq_ir_init; ++#define VXGE_HW_UMQDMQ_IR_INIT_HOST_WRITE_ADD(val) vxge_vBIT(val, 0, 64) ++/*0x01198*/ u64 dmq_ir_int; ++#define VXGE_HW_DMQ_IR_INT_IMMED_ENABLE vxge_mBIT(6) ++#define VXGE_HW_DMQ_IR_INT_EVENT_ENABLE vxge_mBIT(7) ++#define VXGE_HW_DMQ_IR_INT_NUMBER(val) vxge_vBIT(val, 9, 7) ++#define VXGE_HW_DMQ_IR_INT_BITMAP(val) vxge_vBIT(val, 16, 16) ++/*0x011a0*/ u64 dmq_bwr_init_add; ++#define VXGE_HW_DMQ_BWR_INIT_ADD_HOST(val) vxge_vBIT(val, 0, 64) ++/*0x011a8*/ u64 dmq_bwr_init_byte; ++#define VXGE_HW_DMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32) ++/*0x011b0*/ u64 dmq_ir; ++#define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8) ++/*0x011b8*/ u64 umq_int; ++#define VXGE_HW_UMQ_INT_IMMED_ENABLE vxge_mBIT(6) ++#define VXGE_HW_UMQ_INT_EVENT_ENABLE vxge_mBIT(7) ++#define VXGE_HW_UMQ_INT_NUMBER(val) vxge_vBIT(val, 9, 7) ++#define VXGE_HW_UMQ_INT_BITMAP(val) vxge_vBIT(val, 16, 16) ++/*0x011c0*/ u64 umq_mr2vp_bwr_pfch_init; ++#define VXGE_HW_UMQ_MR2VP_BWR_PFCH_INIT_NUMBER(val) vxge_vBIT(val, 0, 8) ++/*0x011c8*/ u64 umq_bwr_pfch_ctrl; ++#define VXGE_HW_UMQ_BWR_PFCH_CTRL_POLL_EN vxge_mBIT(3) ++/*0x011d0*/ u64 umq_mr2vp_bwr_eol; ++#define VXGE_HW_UMQ_MR2VP_BWR_EOL_POLL_LATENCY(val) vxge_vBIT(val, 32, 32) ++/*0x011d8*/ u64 umq_bwr_init_add; ++#define VXGE_HW_UMQ_BWR_INIT_ADD_HOST(val) vxge_vBIT(val, 0, 64) ++/*0x011e0*/ u64 umq_bwr_init_byte; ++#define VXGE_HW_UMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32) ++/*0x011e8*/ u64 gendma_int; ++/*0x011f0*/ u64 umqdmq_ir_init_notify; ++#define VXGE_HW_UMQDMQ_IR_INIT_NOTIFY_PULSE vxge_mBIT(3) ++/*0x011f8*/ u64 dmq_init_notify; ++#define VXGE_HW_DMQ_INIT_NOTIFY_PULSE vxge_mBIT(3) ++/*0x01200*/ u64 umq_init_notify; ++#define VXGE_HW_UMQ_INIT_NOTIFY_PULSE vxge_mBIT(3) ++ u8 unused01380[0x01380-0x01208]; ++ ++/*0x01380*/ u64 tpa_cfg; ++#define VXGE_HW_TPA_CFG_IGNORE_FRAME_ERR vxge_mBIT(3) ++#define VXGE_HW_TPA_CFG_IPV6_STOP_SEARCHING vxge_mBIT(7) ++#define VXGE_HW_TPA_CFG_L4_PSHDR_PRESENT vxge_mBIT(11) ++#define VXGE_HW_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS vxge_mBIT(15) ++ u8 unused01400[0x01400-0x01388]; ++ ++/*0x01400*/ u64 tx_vp_reset_discarded_frms; ++#define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_TX_VP_RESET_DISCARDED_FRMS(val) \ ++ vxge_vBIT(val, 48, 16) ++ u8 unused01480[0x01480-0x01408]; ++ ++/*0x01480*/ u64 fau_rpa_vcfg; ++#define VXGE_HW_FAU_RPA_VCFG_L4_COMP_CSUM vxge_mBIT(7) ++#define VXGE_HW_FAU_RPA_VCFG_L3_INCL_CF vxge_mBIT(11) ++#define VXGE_HW_FAU_RPA_VCFG_L3_COMP_CSUM vxge_mBIT(15) ++ u8 unused014d0[0x014d0-0x01488]; ++ ++/*0x014d0*/ u64 dbg_stats_rx_mpa; ++#define VXGE_HW_DBG_STATS_RX_MPA_CRC_FAIL_FRMS(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_DBG_STATS_RX_MPA_MRK_FAIL_FRMS(val) vxge_vBIT(val, 16, 16) ++#define VXGE_HW_DBG_STATS_RX_MPA_LEN_FAIL_FRMS(val) vxge_vBIT(val, 32, 16) ++/*0x014d8*/ u64 dbg_stats_rx_fau; ++#define VXGE_HW_DBG_STATS_RX_FAU_RX_WOL_FRMS(val) vxge_vBIT(val, 0, 16) ++#define VXGE_HW_DBG_STATS_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val) \ ++ vxge_vBIT(val, 16, 16) ++#define VXGE_HW_DBG_STATS_RX_FAU_RX_PERMITTED_FRMS(val) \ ++ vxge_vBIT(val, 32, 32) ++ u8 unused014f0[0x014f0-0x014e0]; ++ ++/*0x014f0*/ u64 fbmc_vp_rdy; ++#define VXGE_HW_FBMC_VP_RDY_QUEUE_SPAV_FM vxge_mBIT(0) ++ u8 unused01e00[0x01e00-0x014f8]; ++ ++/*0x01e00*/ u64 vpath_pcipif_int_status; ++#define \ ++VXGE_HW_VPATH_PCIPIF_INT_STATUS_SRPCIM_MSG_TO_VPATH_SRPCIM_MSG_TO_VPATH_INT \ ++ vxge_mBIT(3) ++#define VXGE_HW_VPATH_PCIPIF_INT_STATUS_VPATH_SPARE_R1_VPATH_SPARE_R1_INT \ ++ vxge_mBIT(7) ++/*0x01e08*/ u64 vpath_pcipif_int_mask; ++ u8 unused01e20[0x01e20-0x01e10]; ++ ++/*0x01e20*/ u64 srpcim_msg_to_vpath_reg; ++#define VXGE_HW_SRPCIM_MSG_TO_VPATH_REG_SWIF_SRPCIM_TO_VPATH_RMSG_INT \ ++ vxge_mBIT(3) ++/*0x01e28*/ u64 srpcim_msg_to_vpath_mask; ++/*0x01e30*/ u64 srpcim_msg_to_vpath_alarm; ++ u8 unused01ea0[0x01ea0-0x01e38]; ++ ++/*0x01ea0*/ u64 vpath_to_srpcim_wmsg; ++#define VXGE_HW_VPATH_TO_SRPCIM_WMSG_VPATH_TO_SRPCIM_WMSG(val) \ ++ vxge_vBIT(val, 0, 64) ++/*0x01ea8*/ u64 vpath_to_srpcim_wmsg_trig; ++#define VXGE_HW_VPATH_TO_SRPCIM_WMSG_TRIG_VPATH_TO_SRPCIM_WMSG_TRIG \ ++ vxge_mBIT(0) ++ u8 unused02000[0x02000-0x01eb0]; ++ ++/*0x02000*/ u64 vpath_general_int_status; ++#define VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT vxge_mBIT(3) ++#define VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT vxge_mBIT(7) ++#define VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT vxge_mBIT(15) ++#define VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT vxge_mBIT(19) ++/*0x02008*/ u64 vpath_general_int_mask; ++#define VXGE_HW_VPATH_GENERAL_INT_MASK_PIC_INT vxge_mBIT(3) ++#define VXGE_HW_VPATH_GENERAL_INT_MASK_PCI_INT vxge_mBIT(7) ++#define VXGE_HW_VPATH_GENERAL_INT_MASK_WRDMA_INT vxge_mBIT(15) ++#define VXGE_HW_VPATH_GENERAL_INT_MASK_XMAC_INT vxge_mBIT(19) ++/*0x02010*/ u64 vpath_ppif_int_status; ++#define VXGE_HW_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_KDFCCTL_INT \ ++ vxge_mBIT(3) ++#define VXGE_HW_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_GENERAL_INT \ ++ vxge_mBIT(7) ++#define VXGE_HW_VPATH_PPIF_INT_STATUS_PCI_CONFIG_ERRORS_PCI_CONFIG_INT \ ++ vxge_mBIT(11) ++#define \ ++VXGE_HW_VPATH_PPIF_INT_STATUS_MRPCIM_TO_VPATH_ALARM_MRPCIM_TO_VPATH_ALARM_INT \ ++ vxge_mBIT(15) ++#define \ ++VXGE_HW_VPATH_PPIF_INT_STATUS_SRPCIM_TO_VPATH_ALARM_SRPCIM_TO_VPATH_ALARM_INT \ ++ vxge_mBIT(19) ++/*0x02018*/ u64 vpath_ppif_int_mask; ++/*0x02020*/ u64 kdfcctl_errors_reg; ++#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR vxge_mBIT(3) ++#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR vxge_mBIT(7) ++#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR vxge_mBIT(11) ++#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON vxge_mBIT(15) ++#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON vxge_mBIT(19) ++#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON vxge_mBIT(23) ++#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR vxge_mBIT(31) ++#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR vxge_mBIT(35) ++#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR vxge_mBIT(39) ++/*0x02028*/ u64 kdfcctl_errors_mask; ++/*0x02030*/ u64 kdfcctl_errors_alarm; ++ u8 unused02040[0x02040-0x02038]; ++ ++/*0x02040*/ u64 general_errors_reg; ++#define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW vxge_mBIT(3) ++#define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW vxge_mBIT(7) ++#define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW vxge_mBIT(11) ++#define VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR vxge_mBIT(15) ++#define VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ vxge_mBIT(19) ++#define VXGE_HW_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS vxge_mBIT(27) ++#define VXGE_HW_GENERAL_ERRORS_REG_INI_SERR_DET vxge_mBIT(31) ++/*0x02048*/ u64 general_errors_mask; ++/*0x02050*/ u64 general_errors_alarm; ++/*0x02058*/ u64 pci_config_errors_reg; ++#define VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_STATUS_ERR vxge_mBIT(3) ++#define VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_UNCOR_ERR vxge_mBIT(7) ++#define VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_COR_ERR vxge_mBIT(11) ++/*0x02060*/ u64 pci_config_errors_mask; ++/*0x02068*/ u64 pci_config_errors_alarm; ++/*0x02070*/ u64 mrpcim_to_vpath_alarm_reg; ++#define VXGE_HW_MRPCIM_TO_VPATH_ALARM_REG_PPIF_MRPCIM_TO_VPATH_ALARM \ ++ vxge_mBIT(3) ++/*0x02078*/ u64 mrpcim_to_vpath_alarm_mask; ++/*0x02080*/ u64 mrpcim_to_vpath_alarm_alarm; ++/*0x02088*/ u64 srpcim_to_vpath_alarm_reg; ++#define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_PPIF_SRPCIM_TO_VPATH_ALARM(val) \ ++ vxge_vBIT(val, 0, 17) ++/*0x02090*/ u64 srpcim_to_vpath_alarm_mask; ++/*0x02098*/ u64 srpcim_to_vpath_alarm_alarm; ++ u8 unused02108[0x02108-0x020a0]; ++ ++/*0x02108*/ u64 kdfcctl_status; ++#define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_PRES(val) vxge_vBIT(val, 0, 8) ++#define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_PRES(val) vxge_vBIT(val, 8, 8) ++#define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_PRES(val) vxge_vBIT(val, 16, 8) ++#define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_OVRWR(val) vxge_vBIT(val, 24, 8) ++#define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_OVRWR(val) vxge_vBIT(val, 32, 8) ++#define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_OVRWR(val) vxge_vBIT(val, 40, 8) ++/*0x02110*/ u64 rsthdlr_status; ++#define VXGE_HW_RSTHDLR_STATUS_RSTHDLR_CURRENT_RESET vxge_mBIT(3) ++#define VXGE_HW_RSTHDLR_STATUS_RSTHDLR_CURRENT_VPIN(val) vxge_vBIT(val, 6, 2) ++/*0x02118*/ u64 fifo0_status; ++#define VXGE_HW_FIFO0_STATUS_DBLGEN_FIFO0_RDIDX(val) vxge_vBIT(val, 0, 12) ++/*0x02120*/ u64 fifo1_status; ++#define VXGE_HW_FIFO1_STATUS_DBLGEN_FIFO1_RDIDX(val) vxge_vBIT(val, 0, 12) ++/*0x02128*/ u64 fifo2_status; ++#define VXGE_HW_FIFO2_STATUS_DBLGEN_FIFO2_RDIDX(val) vxge_vBIT(val, 0, 12) ++ u8 unused02158[0x02158-0x02130]; ++ ++/*0x02158*/ u64 tgt_illegal_access; ++#define VXGE_HW_TGT_ILLEGAL_ACCESS_SWIF_REGION(val) vxge_vBIT(val, 1, 7) ++ u8 unused02200[0x02200-0x02160]; ++ ++/*0x02200*/ u64 vpath_general_cfg1; ++#define VXGE_HW_VPATH_GENERAL_CFG1_TC_VALUE(val) vxge_vBIT(val, 1, 3) ++#define VXGE_HW_VPATH_GENERAL_CFG1_DATA_BYTE_SWAPEN vxge_mBIT(7) ++#define VXGE_HW_VPATH_GENERAL_CFG1_DATA_FLIPEN vxge_mBIT(11) ++#define VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN vxge_mBIT(15) ++#define VXGE_HW_VPATH_GENERAL_CFG1_CTL_FLIPEN vxge_mBIT(23) ++#define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_ADDR_SWAPEN vxge_mBIT(51) ++#define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_ADDR_FLIPEN vxge_mBIT(55) ++#define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_DATA_SWAPEN vxge_mBIT(59) ++#define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_DATA_FLIPEN vxge_mBIT(63) ++/*0x02208*/ u64 vpath_general_cfg2; ++#define VXGE_HW_VPATH_GENERAL_CFG2_SIZE_QUANTUM(val) vxge_vBIT(val, 1, 3) ++/*0x02210*/ u64 vpath_general_cfg3; ++#define VXGE_HW_VPATH_GENERAL_CFG3_IGNORE_VPATH_RST_FOR_INTA vxge_mBIT(3) ++ u8 unused02220[0x02220-0x02218]; ++ ++/*0x02220*/ u64 kdfcctl_cfg0; ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 vxge_mBIT(1) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 vxge_mBIT(2) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2 vxge_mBIT(3) ++#define VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO0 vxge_mBIT(5) ++#define VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO1 vxge_mBIT(6) ++#define VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO2 vxge_mBIT(7) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO0 vxge_mBIT(9) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO1 vxge_mBIT(10) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO2 vxge_mBIT(11) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO0 vxge_mBIT(13) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO1 vxge_mBIT(14) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO2 vxge_mBIT(15) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO0 vxge_mBIT(17) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO1 vxge_mBIT(18) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO2 vxge_mBIT(19) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO0 vxge_mBIT(21) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO1 vxge_mBIT(22) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO2 vxge_mBIT(23) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO0 vxge_mBIT(25) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO1 vxge_mBIT(26) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO2 vxge_mBIT(27) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO0 vxge_mBIT(29) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO1 vxge_mBIT(30) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO2 vxge_mBIT(31) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO0 vxge_mBIT(33) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO1 vxge_mBIT(34) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO2 vxge_mBIT(35) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO0 vxge_mBIT(37) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO1 vxge_mBIT(38) ++#define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO2 vxge_mBIT(39) ++ ++ u8 unused02268[0x02268-0x02228]; ++ ++/*0x02268*/ u64 stats_cfg; ++#define VXGE_HW_STATS_CFG_START_HOST_ADDR(val) vxge_vBIT(val, 0, 57) ++/*0x02270*/ u64 interrupt_cfg0; ++#define VXGE_HW_INTERRUPT_CFG0_MSIX_FOR_RXTI(val) vxge_vBIT(val, 1, 7) ++#define VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(val) vxge_vBIT(val, 9, 7) ++#define VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(val) vxge_vBIT(val, 17, 7) ++#define VXGE_HW_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(val) vxge_vBIT(val, 25, 7) ++#define VXGE_HW_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(val) vxge_vBIT(val, 33, 7) ++ u8 unused02280[0x02280-0x02278]; ++ ++/*0x02280*/ u64 interrupt_cfg2; ++#define VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(val) vxge_vBIT(val, 1, 7) ++/*0x02288*/ u64 one_shot_vect0_en; ++#define VXGE_HW_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN vxge_mBIT(3) ++/*0x02290*/ u64 one_shot_vect1_en; ++#define VXGE_HW_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN vxge_mBIT(3) ++/*0x02298*/ u64 one_shot_vect2_en; ++#define VXGE_HW_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN vxge_mBIT(3) ++/*0x022a0*/ u64 one_shot_vect3_en; ++#define VXGE_HW_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN vxge_mBIT(3) ++ u8 unused022b0[0x022b0-0x022a8]; ++ ++/*0x022b0*/ u64 pci_config_access_cfg1; ++#define VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val) vxge_vBIT(val, 0, 12) ++#define VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0 vxge_mBIT(15) ++/*0x022b8*/ u64 pci_config_access_cfg2; ++#define VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ vxge_mBIT(0) ++/*0x022c0*/ u64 pci_config_access_status; ++#define VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR vxge_mBIT(0) ++#define VXGE_HW_PCI_CONFIG_ACCESS_STATUS_DATA(val) vxge_vBIT(val, 32, 32) ++ u8 unused02300[0x02300-0x022c8]; ++ ++/*0x02300*/ u64 vpath_debug_stats0; ++#define VXGE_HW_VPATH_DEBUG_STATS0_INI_NUM_MWR_SENT(val) vxge_vBIT(val, 0, 32) ++/*0x02308*/ u64 vpath_debug_stats1; ++#define VXGE_HW_VPATH_DEBUG_STATS1_INI_NUM_MRD_SENT(val) vxge_vBIT(val, 0, 32) ++/*0x02310*/ u64 vpath_debug_stats2; ++#define VXGE_HW_VPATH_DEBUG_STATS2_INI_NUM_CPL_RCVD(val) vxge_vBIT(val, 0, 32) ++/*0x02318*/ u64 vpath_debug_stats3; ++#define VXGE_HW_VPATH_DEBUG_STATS3_INI_NUM_MWR_BYTE_SENT(val) \ ++ vxge_vBIT(val, 0, 64) ++/*0x02320*/ u64 vpath_debug_stats4; ++#define VXGE_HW_VPATH_DEBUG_STATS4_INI_NUM_CPL_BYTE_RCVD(val) \ ++ vxge_vBIT(val, 0, 64) ++/*0x02328*/ u64 vpath_debug_stats5; ++#define VXGE_HW_VPATH_DEBUG_STATS5_WRCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32) ++/*0x02330*/ u64 vpath_debug_stats6; ++#define VXGE_HW_VPATH_DEBUG_STATS6_RDCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32) ++/*0x02338*/ u64 vpath_genstats_count01; ++#define VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT1(val) \ ++ vxge_vBIT(val, 0, 32) ++#define VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT0(val) \ ++ vxge_vBIT(val, 32, 32) ++/*0x02340*/ u64 vpath_genstats_count23; ++#define VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT3(val) \ ++ vxge_vBIT(val, 0, 32) ++#define VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT2(val) \ ++ vxge_vBIT(val, 32, 32) ++/*0x02348*/ u64 vpath_genstats_count4; ++#define VXGE_HW_VPATH_GENSTATS_COUNT4_PPIF_VPATH_GENSTATS_COUNT4(val) \ ++ vxge_vBIT(val, 32, 32) ++/*0x02350*/ u64 vpath_genstats_count5; ++#define VXGE_HW_VPATH_GENSTATS_COUNT5_PPIF_VPATH_GENSTATS_COUNT5(val) \ ++ vxge_vBIT(val, 32, 32) ++ u8 unused02648[0x02648-0x02358]; ++} __attribute((packed)); ++ ++#define VXGE_HW_EEPROM_SIZE (0x01 << 11) ++ ++/* Capability lists */ ++#define VXGE_HW_PCI_EXP_LNKCAP_LNK_SPEED 0xf /* Supported Link speeds */ ++#define VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0 /* Supported Link speeds. */ ++#define VXGE_HW_PCI_EXP_LNKCAP_LW_RES 0x0 /* Reserved. */ ++ ++#endif +diff -r 158b6e53275e drivers/net/vxge/vxge-traffic.c +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/vxge/vxge-traffic.c Wed Aug 05 11:58:00 2009 +0100 +@@ -0,0 +1,3444 @@ ++/****************************************************************************** ++ * vxge-traffic.c: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O ++ * Virtualized Server Adapter. ++ * Copyright(c) 2002-2009 Neterion Inc. ++ ******************************************************************************/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++ ++ ++#include "vxge-traffic.h" ++#include "vxge-config.h" ++#include "vxge-main.h" ++ ++/* ++ * vxge_hw_vpath_intr_enable - Enable vpath interrupts. ++ * @vp: Virtual Path handle. ++ * ++ * Enable vpath interrupts. The function is to be executed the last in ++ * vpath initialization sequence. ++ * ++ * See also: vxge_hw_vpath_intr_disable() ++ */ ++enum vxge_hw_status vxge_hw_vpath_intr_enable(struct __vxge_hw_vpath_handle *vp) ++{ ++ u64 val64; ++ ++ struct __vxge_hw_virtualpath *vpath; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ vpath = vp->vpath; ++ ++ if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { ++ status = VXGE_HW_ERR_VPATH_NOT_OPEN; ++ goto exit; ++ } ++ ++ vp_reg = vpath->vp_reg; ++ ++ writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_reg); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->general_errors_reg); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->pci_config_errors_reg); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->mrpcim_to_vpath_alarm_reg); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->srpcim_to_vpath_alarm_reg); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->vpath_ppif_int_status); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->srpcim_msg_to_vpath_reg); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->vpath_pcipif_int_status); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->prc_alarm_reg); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->wrdma_alarm_status); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->asic_ntwk_vp_err_reg); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->xgmac_vp_int_status); ++ ++ val64 = readq(&vp_reg->vpath_general_int_status); ++ ++ /* Mask unwanted interrupts */ ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->vpath_pcipif_int_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->srpcim_msg_to_vpath_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->srpcim_to_vpath_alarm_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->mrpcim_to_vpath_alarm_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->pci_config_errors_mask); ++ ++ /* Unmask the individual interrupts */ ++ ++ writeq((u32)vxge_bVALn((VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW| ++ VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW| ++ VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ| ++ VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR), 0, 32), ++ &vp_reg->general_errors_mask); ++ ++ __vxge_hw_pio_mem_write32_upper( ++ (u32)vxge_bVALn((VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR| ++ VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR| ++ VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON| ++ VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON| ++ VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR| ++ VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR), 0, 32), ++ &vp_reg->kdfcctl_errors_mask); ++ ++ __vxge_hw_pio_mem_write32_upper(0, &vp_reg->vpath_ppif_int_mask); ++ ++ __vxge_hw_pio_mem_write32_upper( ++ (u32)vxge_bVALn(VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP, 0, 32), ++ &vp_reg->prc_alarm_mask); ++ ++ __vxge_hw_pio_mem_write32_upper(0, &vp_reg->wrdma_alarm_mask); ++ __vxge_hw_pio_mem_write32_upper(0, &vp_reg->xgmac_vp_int_mask); ++ ++ if (vpath->hldev->first_vp_id != vpath->vp_id) ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->asic_ntwk_vp_err_mask); ++ else ++ __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(( ++ VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT | ++ VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK), 0, 32), ++ &vp_reg->asic_ntwk_vp_err_mask); ++ ++ __vxge_hw_pio_mem_write32_upper(0, ++ &vp_reg->vpath_general_int_mask); ++exit: ++ return status; ++ ++} ++ ++/* ++ * vxge_hw_vpath_intr_disable - Disable vpath interrupts. ++ * @vp: Virtual Path handle. ++ * ++ * Disable vpath interrupts. The function is to be executed the last in ++ * vpath initialization sequence. ++ * ++ * See also: vxge_hw_vpath_intr_enable() ++ */ ++enum vxge_hw_status vxge_hw_vpath_intr_disable( ++ struct __vxge_hw_vpath_handle *vp) ++{ ++ u64 val64; ++ ++ struct __vxge_hw_virtualpath *vpath; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ vpath = vp->vpath; ++ ++ if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { ++ status = VXGE_HW_ERR_VPATH_NOT_OPEN; ++ goto exit; ++ } ++ vp_reg = vpath->vp_reg; ++ ++ __vxge_hw_pio_mem_write32_upper( ++ (u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->vpath_general_int_mask); ++ ++ val64 = VXGE_HW_TIM_CLR_INT_EN_VP(1 << (16 - vpath->vp_id)); ++ ++ writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->general_errors_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->pci_config_errors_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->mrpcim_to_vpath_alarm_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->srpcim_to_vpath_alarm_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->vpath_ppif_int_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->srpcim_msg_to_vpath_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->vpath_pcipif_int_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->wrdma_alarm_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->prc_alarm_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->xgmac_vp_int_mask); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->asic_ntwk_vp_err_mask); ++ ++exit: ++ return status; ++} ++ ++void ++vxge_hw_vpath_dynamic_rti_ci_set(struct __vxge_hw_ring *ring) ++{ ++ u64 val64 = ring->tim_rti_cfg1_saved; ++ ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; ++ ring->tim_rti_cfg1_saved = val64; ++ writeq(val64, &ring->vp_reg->tim_cfg1_int_num[ ++ VXGE_HW_VPATH_INTR_RX]); ++ ++ return; ++} ++ ++void ++vxge_hw_vpath_dynamic_rti_ci_reset(struct __vxge_hw_ring *ring) ++{ ++ u64 val64 = ring->tim_rti_cfg1_saved; ++ ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; ++ ring->tim_rti_cfg1_saved = val64; ++ writeq(val64, &ring->vp_reg->tim_cfg1_int_num[ ++ VXGE_HW_VPATH_INTR_RX]); ++ ++ return; ++} ++ ++void ++vxge_hw_vpath_dynamic_rti_btimer_set(struct __vxge_hw_ring *ring) ++{ ++ u64 val64 = ring->tim_rti_cfg1_saved; ++ u64 timer = (ring->btimer * 1000)/272; ++ ++ val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(0x3ffffff); ++ val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(timer); ++ ring->tim_rti_cfg1_saved = val64; ++ writeq(val64, &ring->vp_reg->tim_cfg1_int_num[ ++ VXGE_HW_VPATH_INTR_RX]); ++ return; ++} ++ ++void ++vxge_hw_vpath_dynamic_rti_rtimer_set(struct __vxge_hw_ring *ring) ++{ ++ u64 val64 = ring->tim_rti_cfg3_saved; ++ u64 timer = (ring->rtimer * 1000)/272; ++ ++ if (timer) { ++ val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL( ++ 0x3ffffff); ++ val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) | ++ VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(3); ++ } ++ else { ++ val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL( ++ 0x3ffffff); ++ val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(0); ++ } ++ ++ writeq(val64, &ring->vp_reg->tim_cfg3_int_num[ ++ VXGE_HW_VPATH_INTR_RX]); ++ return; ++} ++ ++/** ++ * vxge_hw_channel_msix_mask - Mask MSIX Vector. ++ * @channeh: Channel for rx or tx handle ++ * @msix_id: MSIX ID ++ * ++ * The function masks the msix interrupt for the given msix_id ++ * ++ * Returns: 0 ++ */ ++void vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channel, int msix_id) ++{ ++ ++ __vxge_hw_pio_mem_write32_upper( ++ (u32)vxge_bVALn(vxge_mBIT(channel->first_vp_id+(msix_id/4)), ++ 0, 32), ++ &channel->common_reg->set_msix_mask_vect[msix_id%4]); ++ ++ return; ++} ++ ++/** ++ * vxge_hw_channel_msix_unmask - Unmask the MSIX Vector. ++ * @channeh: Channel for rx or tx handle ++ * @msix_id: MSI ID ++ * ++ * The function unmasks the msix interrupt for the given msix_id ++ * ++ * Returns: 0 ++ */ ++void ++vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channel, int msix_id) ++{ ++ ++ __vxge_hw_pio_mem_write32_upper( ++ (u32)vxge_bVALn(vxge_mBIT(channel->first_vp_id+(msix_id/4)), ++ 0, 32), ++ &channel->common_reg->clear_msix_mask_vect[msix_id%4]); ++ ++ return; ++} ++ ++/** ++ * vxge_hw_device_set_intr_type - Updates the configuration ++ * with new interrupt type. ++ * @hldev: HW device handle. ++ * @intr_mode: New interrupt type ++ */ ++u32 vxge_hw_device_set_intr_type(struct __vxge_hw_device *hldev, u32 intr_mode) ++{ ++ ++ if ( ++ ++ (intr_mode != VXGE_HW_INTR_MODE_IRQLINE) && ++ (intr_mode != VXGE_HW_INTR_MODE_MSIX) && ++ (intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) && ++ (intr_mode != VXGE_HW_INTR_MODE_DEF)) ++ intr_mode = VXGE_HW_INTR_MODE_IRQLINE; ++ ++ hldev->config.intr_mode = intr_mode; ++ return intr_mode; ++} ++ ++/** ++ * vxge_hw_device_intr_enable - Enable interrupts. ++ * @hldev: HW device handle. ++ * @op: One of the enum vxge_hw_device_intr enumerated values specifying ++ * the type(s) of interrupts to enable. ++ * ++ * Enable Titan interrupts. The function is to be executed the last in ++ * Titan initialization sequence. ++ * ++ * See also: vxge_hw_device_intr_disable() ++ */ ++void vxge_hw_device_intr_enable(struct __vxge_hw_device *hldev) ++{ ++ u32 i; ++ u64 val64; ++ u32 val32; ++ ++ vxge_hw_device_mask_all(hldev); ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ ++ if (!(hldev->vpaths_deployed & vxge_mBIT(i))) ++ continue; ++ ++ vxge_hw_vpath_intr_enable( ++ VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i])); ++ } ++ ++ if ( ++ ++ (hldev->config.intr_mode == VXGE_HW_INTR_MODE_IRQLINE)) { ++ val64 = hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] | ++ hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX]; ++ ++ if (val64 != 0) { ++ writeq(val64, &hldev->common_reg->tim_int_status0); ++ ++ writeq(~val64, &hldev->common_reg->tim_int_mask0); ++ } ++ ++ val32 = hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] | ++ hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX]; ++ ++ if (val32 != 0) { ++ __vxge_hw_pio_mem_write32_upper(val32, ++ &hldev->common_reg->tim_int_status1); ++ ++ __vxge_hw_pio_mem_write32_upper(~val32, ++ &hldev->common_reg->tim_int_mask1); ++ } ++ } ++ ++ val64 = readq(&hldev->common_reg->titan_general_int_status); ++ ++ vxge_hw_device_unmask_all(hldev); ++ ++ return; ++} ++ ++/** ++ * vxge_hw_device_intr_disable - Disable Titan interrupts. ++ * @hldev: HW device handle. ++ * @op: One of the enum vxge_hw_device_intr enumerated values specifying ++ * the type(s) of interrupts to disable. ++ * ++ * Disable Titan interrupts. ++ * ++ * See also: vxge_hw_device_intr_enable() ++ */ ++void vxge_hw_device_intr_disable(struct __vxge_hw_device *hldev) ++{ ++ u32 i; ++ ++ vxge_hw_device_mask_all(hldev); ++ ++ /* mask all the tim interrupts */ ++ writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0); ++ __vxge_hw_pio_mem_write32_upper(VXGE_HW_DEFAULT_32, ++ &hldev->common_reg->tim_int_mask1); ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ ++ if (!(hldev->vpaths_deployed & vxge_mBIT(i))) ++ continue; ++ ++ vxge_hw_vpath_intr_disable( ++ VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i])); ++ } ++ ++ vxge_hw_device_unmask_all(hldev); ++ ++ return; ++} ++ ++/** ++ * vxge_hw_device_mask_all - Mask all device interrupts. ++ * @hldev: HW device handle. ++ * ++ * Mask all device interrupts. ++ * ++ * See also: vxge_hw_device_unmask_all() ++ */ ++void vxge_hw_device_mask_all(struct __vxge_hw_device *hldev) ++{ ++ u64 val64; ++ ++ val64 = VXGE_HW_TITAN_MASK_ALL_INT_ALARM | ++ VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC; ++ ++ __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), ++ &hldev->common_reg->titan_mask_all_int); ++ ++ return; ++} ++ ++/** ++ * vxge_hw_device_unmask_all - Unmask all device interrupts. ++ * @hldev: HW device handle. ++ * ++ * Unmask all device interrupts. ++ * ++ * See also: vxge_hw_device_mask_all() ++ */ ++void vxge_hw_device_unmask_all(struct __vxge_hw_device *hldev) ++{ ++ u64 val64 = 0; ++ ++ if (hldev->config.intr_mode == VXGE_HW_INTR_MODE_IRQLINE) ++ val64 = VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC; ++ ++ __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), ++ &hldev->common_reg->titan_mask_all_int); ++ ++ return; ++} ++ ++/** ++ * vxge_hw_device_flush_io - Flush io writes. ++ * @hldev: HW device handle. ++ * ++ * The function performs a read operation to flush io writes. ++ * ++ * Returns: void ++ */ ++void vxge_hw_device_flush_io(struct __vxge_hw_device *hldev) ++{ ++ u32 val32; ++ ++ val32 = readl(&hldev->common_reg->titan_general_int_status); ++} ++ ++/** ++ * vxge_hw_device_begin_irq - Begin IRQ processing. ++ * @hldev: HW device handle. ++ * @skip_alarms: Do not clear the alarms ++ * @reason: "Reason" for the interrupt, the value of Titan's ++ * general_int_status register. ++ * ++ * The function performs two actions, It first checks whether (shared IRQ) the ++ * interrupt was raised by the device. Next, it masks the device interrupts. ++ * ++ * Note: ++ * vxge_hw_device_begin_irq() does not flush MMIO writes through the ++ * bridge. Therefore, two back-to-back interrupts are potentially possible. ++ * ++ * Returns: 0, if the interrupt is not "ours" (note that in this case the ++ * device remain enabled). ++ * Otherwise, vxge_hw_device_begin_irq() returns 64bit general adapter ++ * status. ++ */ ++enum vxge_hw_status vxge_hw_device_begin_irq(struct __vxge_hw_device *hldev, ++ u32 skip_alarms, u64 *reason) ++{ ++ u32 i; ++ u64 val64; ++ u64 adapter_status; ++ u64 vpath_mask; ++ enum vxge_hw_status ret = VXGE_HW_OK; ++ ++ val64 = readq(&hldev->common_reg->titan_general_int_status); ++ ++ if (unlikely(!val64)) { ++ /* not Titan interrupt */ ++ *reason = 0; ++ ret = VXGE_HW_ERR_WRONG_IRQ; ++ goto exit; ++ } ++ ++ if (unlikely(val64 == VXGE_HW_ALL_FOXES)) { ++ ++ adapter_status = readq(&hldev->common_reg->adapter_status); ++ ++ if (adapter_status == VXGE_HW_ALL_FOXES) { ++ ++ __vxge_hw_device_handle_error(hldev, ++ NULL_VPID, VXGE_HW_EVENT_SLOT_FREEZE); ++ *reason = 0; ++ ret = VXGE_HW_ERR_SLOT_FREEZE; ++ goto exit; ++ } ++ } ++ ++ hldev->stats.sw_dev_info_stats.total_intr_cnt++; ++ ++ *reason = val64; ++ ++ vpath_mask = hldev->vpaths_deployed >> ++ (64 - VXGE_HW_MAX_VIRTUAL_PATHS); ++ ++ if (val64 & ++ VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(vpath_mask)) { ++ hldev->stats.sw_dev_info_stats.traffic_intr_cnt++; ++ ++ return VXGE_HW_OK; ++ } ++ ++ hldev->stats.sw_dev_info_stats.not_traffic_intr_cnt++; ++ ++ if (unlikely(val64 & ++ VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT)) { ++ ++ enum vxge_hw_status error_level = VXGE_HW_OK; ++ ++ hldev->stats.sw_dev_err_stats.vpath_alarms++; ++ ++ for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { ++ ++ if (!(hldev->vpaths_deployed & vxge_mBIT(i))) ++ continue; ++ ++ ret = __vxge_hw_vpath_alarm_process( ++ &hldev->virtual_paths[i], skip_alarms); ++ ++ error_level = max(ret, error_level); ++ ++ if (unlikely((ret == VXGE_HW_ERR_CRITICAL) || ++ (ret == VXGE_HW_ERR_SLOT_FREEZE))) ++ break; ++ } ++ ++ ret = error_level; ++ } ++exit: ++ return ret; ++} ++ ++/* ++ * __vxge_hw_device_handle_link_up_ind ++ * @hldev: HW device handle. ++ * ++ * Link up indication handler. The function is invoked by HW when ++ * Titan indicates that the link is up for programmable amount of time. ++ */ ++enum vxge_hw_status ++__vxge_hw_device_handle_link_up_ind(struct __vxge_hw_device *hldev) ++{ ++ /* ++ * If the previous link state is not down, return. ++ */ ++ if (hldev->link_state == VXGE_HW_LINK_UP) ++ goto exit; ++ ++ hldev->link_state = VXGE_HW_LINK_UP; ++ ++ /* notify driver */ ++ if (hldev->uld_callbacks.link_up) ++ hldev->uld_callbacks.link_up(hldev); ++exit: ++ return VXGE_HW_OK; ++} ++ ++/* ++ * __vxge_hw_device_handle_link_down_ind ++ * @hldev: HW device handle. ++ * ++ * Link down indication handler. The function is invoked by HW when ++ * Titan indicates that the link is down. ++ */ ++enum vxge_hw_status ++__vxge_hw_device_handle_link_down_ind(struct __vxge_hw_device *hldev) ++{ ++ /* ++ * If the previous link state is not down, return. ++ */ ++ if (hldev->link_state == VXGE_HW_LINK_DOWN) ++ goto exit; ++ ++ hldev->link_state = VXGE_HW_LINK_DOWN; ++ ++ /* notify driver */ ++ if (hldev->uld_callbacks.link_down) ++ hldev->uld_callbacks.link_down(hldev); ++exit: ++ return VXGE_HW_OK; ++} ++ ++/** ++ * __vxge_hw_device_handle_error - Handle error ++ * @hldev: HW device ++ * @vp_id: Vpath Id ++ * @type: Error type. Please see enum vxge_hw_event{} ++ * ++ * Handle error. ++ */ ++enum vxge_hw_status ++__vxge_hw_device_handle_error( ++ struct __vxge_hw_device *hldev, ++ u32 vp_id, ++ enum vxge_hw_event type) ++{ ++ switch (type) { ++ case VXGE_HW_EVENT_UNKNOWN: ++ break; ++ case VXGE_HW_EVENT_RESET_START: ++ case VXGE_HW_EVENT_RESET_COMPLETE: ++ case VXGE_HW_EVENT_LINK_DOWN: ++ case VXGE_HW_EVENT_LINK_UP: ++ goto out; ++ case VXGE_HW_EVENT_ALARM_CLEARED: ++ goto out; ++ case VXGE_HW_EVENT_ECCERR: ++ case VXGE_HW_EVENT_MRPCIM_ECCERR: ++ goto out; ++ case VXGE_HW_EVENT_FIFO_ERR: ++ case VXGE_HW_EVENT_VPATH_ERR: ++ case VXGE_HW_EVENT_CRITICAL_ERR: ++ case VXGE_HW_EVENT_SERR: ++ break; ++ case VXGE_HW_EVENT_SRPCIM_SERR: ++ case VXGE_HW_EVENT_MRPCIM_SERR: ++ goto out; ++ case VXGE_HW_EVENT_SLOT_FREEZE: ++ break; ++ default: ++ vxge_assert(0); ++ goto out; ++ } ++ ++ /* notify driver */ ++ if (hldev->uld_callbacks.crit_err) ++ hldev->uld_callbacks.crit_err( ++ (struct __vxge_hw_device *)hldev, ++ type, vp_id); ++out: ++ ++ return VXGE_HW_OK; ++} ++ ++/** ++ * vxge_hw_device_clear_tx_rx - Acknowledge (that is, clear) the ++ * condition that has caused the Tx and RX interrupt. ++ * @hldev: HW device. ++ * ++ * Acknowledge (that is, clear) the condition that has caused ++ * the Tx and Rx interrupt. ++ * See also: vxge_hw_device_begin_irq(), ++ * vxge_hw_device_mask_tx_rx(), vxge_hw_device_unmask_tx_rx(). ++ */ ++void vxge_hw_device_clear_tx_rx(struct __vxge_hw_device *hldev) ++{ ++ ++ if ((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) || ++ (hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) { ++ writeq((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] | ++ hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX]), ++ &hldev->common_reg->tim_int_status0); ++ } ++ ++ if ((hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) || ++ (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) { ++ __vxge_hw_pio_mem_write32_upper( ++ (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] | ++ hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX]), ++ &hldev->common_reg->tim_int_status1); ++ } ++ ++ return; ++} ++ ++/* ++ * vxge_hw_channel_dtr_alloc - Allocate a dtr from the channel ++ * @channel: Channel ++ * @dtrh: Buffer to return the DTR pointer ++ * ++ * Allocates a dtr from the reserve array. If the reserve array is empty, ++ * it swaps the reserve and free arrays. ++ * ++ */ ++enum vxge_hw_status ++vxge_hw_channel_dtr_alloc(struct __vxge_hw_channel *channel, void **dtrh) ++{ ++ void **tmp_arr; ++ ++ if (channel->reserve_ptr - channel->reserve_top > 0) { ++_alloc_after_swap: ++ *dtrh = channel->reserve_arr[--channel->reserve_ptr]; ++ ++ return VXGE_HW_OK; ++ } ++ ++ /* switch between empty and full arrays */ ++ ++ /* the idea behind such a design is that by having free and reserved ++ * arrays separated we basically separated irq and non-irq parts. ++ * i.e. no additional lock need to be done when we free a resource */ ++ ++ if (channel->length - channel->free_ptr > 0) { ++ ++ tmp_arr = channel->reserve_arr; ++ channel->reserve_arr = channel->free_arr; ++ channel->free_arr = tmp_arr; ++ channel->reserve_ptr = channel->length; ++ channel->reserve_top = channel->free_ptr; ++ channel->free_ptr = channel->length; ++ ++ channel->stats->reserve_free_swaps_cnt++; ++ ++ goto _alloc_after_swap; ++ } ++ ++ channel->stats->full_cnt++; ++ ++ *dtrh = NULL; ++ return VXGE_HW_INF_OUT_OF_DESCRIPTORS; ++} ++ ++/* ++ * vxge_hw_channel_dtr_post - Post a dtr to the channel ++ * @channelh: Channel ++ * @dtrh: DTR pointer ++ * ++ * Posts a dtr to work array. ++ * ++ */ ++void vxge_hw_channel_dtr_post(struct __vxge_hw_channel *channel, void *dtrh) ++{ ++ vxge_assert(channel->work_arr[channel->post_index] == NULL); ++ ++ channel->work_arr[channel->post_index++] = dtrh; ++ ++ /* wrap-around */ ++ if (channel->post_index == channel->length) ++ channel->post_index = 0; ++} ++ ++/* ++ * vxge_hw_channel_dtr_try_complete - Returns next completed dtr ++ * @channel: Channel ++ * @dtr: Buffer to return the next completed DTR pointer ++ * ++ * Returns the next completed dtr with out removing it from work array ++ * ++ */ ++void ++vxge_hw_channel_dtr_try_complete(struct __vxge_hw_channel *channel, void **dtrh) ++{ ++ vxge_assert(channel->compl_index < channel->length); ++ ++ *dtrh = channel->work_arr[channel->compl_index]; ++ prefetch(*dtrh); ++} ++ ++/* ++ * vxge_hw_channel_dtr_complete - Removes next completed dtr from the work array ++ * @channel: Channel handle ++ * ++ * Removes the next completed dtr from work array ++ * ++ */ ++void vxge_hw_channel_dtr_complete(struct __vxge_hw_channel *channel) ++{ ++ channel->work_arr[channel->compl_index] = NULL; ++ ++ /* wrap-around */ ++ if (++channel->compl_index == channel->length) ++ channel->compl_index = 0; ++ ++ channel->stats->total_compl_cnt++; ++} ++ ++/* ++ * vxge_hw_channel_dtr_free - Frees a dtr ++ * @channel: Channel handle ++ * @dtr: DTR pointer ++ * ++ * Returns the dtr to free array ++ * ++ */ ++void vxge_hw_channel_dtr_free(struct __vxge_hw_channel *channel, void *dtrh) ++{ ++ channel->free_arr[--channel->free_ptr] = dtrh; ++} ++ ++/* ++ * vxge_hw_channel_dtr_count ++ * @channel: Channel handle. Obtained via vxge_hw_channel_open(). ++ * ++ * Retreive number of DTRs available. This function can not be called ++ * from data path. ring_initial_replenishi() is the only user. ++ */ ++int vxge_hw_channel_dtr_count(struct __vxge_hw_channel *channel) ++{ ++ return (channel->reserve_ptr - channel->reserve_top) + ++ (channel->length - channel->free_ptr); ++} ++ ++/** ++ * vxge_hw_ring_rxd_reserve - Reserve ring descriptor. ++ * @ring: Handle to the ring object used for receive ++ * @rxdh: Reserved descriptor. On success HW fills this "out" parameter ++ * with a valid handle. ++ * ++ * Reserve Rx descriptor for the subsequent filling-in driver ++ * and posting on the corresponding channel (@channelh) ++ * via vxge_hw_ring_rxd_post(). ++ * ++ * Returns: VXGE_HW_OK - success. ++ * VXGE_HW_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available. ++ * ++ */ ++enum vxge_hw_status vxge_hw_ring_rxd_reserve(struct __vxge_hw_ring *ring, ++ void **rxdh) ++{ ++ enum vxge_hw_status status; ++ ++ status = vxge_hw_channel_dtr_alloc(&ring->channel, rxdh); ++ ++ if (status == VXGE_HW_OK) { ++ struct vxge_hw_ring_rxd_1 *rxdp = ++ (struct vxge_hw_ring_rxd_1 *)*rxdh; ++ ++ rxdp->control_0 = rxdp->control_1 = 0; ++ } ++ ++ return status; ++} ++ ++/** ++ * vxge_hw_ring_rxd_free - Free descriptor. ++ * @ring: Handle to the ring object used for receive ++ * @rxdh: Descriptor handle. ++ * ++ * Free the reserved descriptor. This operation is "symmetrical" to ++ * vxge_hw_ring_rxd_reserve. The "free-ing" completes the descriptor's ++ * lifecycle. ++ * ++ * After free-ing (see vxge_hw_ring_rxd_free()) the descriptor again can ++ * be: ++ * ++ * - reserved (vxge_hw_ring_rxd_reserve); ++ * ++ * - posted (vxge_hw_ring_rxd_post); ++ * ++ * - completed (vxge_hw_ring_rxd_next_completed); ++ * ++ * - and recycled again (vxge_hw_ring_rxd_free). ++ * ++ * For alternative state transitions and more details please refer to ++ * the design doc. ++ * ++ */ ++void vxge_hw_ring_rxd_free(struct __vxge_hw_ring *ring, void *rxdh) ++{ ++ vxge_hw_channel_dtr_free(&ring->channel, rxdh); ++} ++ ++/** ++ * vxge_hw_ring_rxd_pre_post - Prepare rxd and post ++ * @ring: Handle to the ring object used for receive ++ * @rxdh: Descriptor handle. ++ * ++ * This routine prepares a rxd and posts ++ */ ++void vxge_hw_ring_rxd_pre_post(struct __vxge_hw_ring *ring, void *rxdh) ++{ ++ vxge_hw_channel_dtr_post(&ring->channel, rxdh); ++} ++ ++/** ++ * vxge_hw_ring_rxd_post_post - Process rxd after post. ++ * @ring: Handle to the ring object used for receive ++ * @rxdh: Descriptor handle. ++ * ++ * Processes rxd after post ++ */ ++void vxge_hw_ring_rxd_post_post(struct __vxge_hw_ring *ring, void *rxdh) ++{ ++ struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; ++ ++ rxdp->control_0 |= VXGE_HW_RING_RXD_LIST_OWN_ADAPTER; ++ ++ if (ring->stats->common_stats.usage_cnt > 0) ++ ring->stats->common_stats.usage_cnt--; ++} ++ ++/** ++ * vxge_hw_ring_rxd_post - Post descriptor on the ring. ++ * @ring: Handle to the ring object used for receive ++ * @rxdh: Descriptor obtained via vxge_hw_ring_rxd_reserve(). ++ * ++ * Post descriptor on the ring. ++ * Prior to posting the descriptor should be filled in accordance with ++ * Host/Titan interface specification for a given service (LL, etc.). ++ * ++ */ ++void vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring, void *rxdh) ++{ ++ struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; ++ ++ wmb(); ++ rxdp->control_0 |= VXGE_HW_RING_RXD_LIST_OWN_ADAPTER; ++ ++ vxge_hw_channel_dtr_post(&ring->channel, rxdh); ++ ++ if (ring->stats->common_stats.usage_cnt > 0) ++ ring->stats->common_stats.usage_cnt--; ++} ++ ++/** ++ * vxge_hw_ring_rxd_post_post_wmb - Process rxd after post with memory barrier. ++ * @ring: Handle to the ring object used for receive ++ * @rxdh: Descriptor handle. ++ * ++ * Processes rxd after post with memory barrier. ++ */ ++void vxge_hw_ring_rxd_post_post_wmb(struct __vxge_hw_ring *ring, void *rxdh) ++{ ++ wmb(); ++ vxge_hw_ring_rxd_post_post(ring, rxdh); ++} ++ ++/** ++ * vxge_hw_ring_rxd_next_completed - Get the _next_ completed descriptor. ++ * @ring: Handle to the ring object used for receive ++ * @rxdh: Descriptor handle. Returned by HW. ++ * @t_code: Transfer code, as per Titan User Guide, ++ * Receive Descriptor Format. Returned by HW. ++ * ++ * Retrieve the _next_ completed descriptor. ++ * HW uses ring callback (*vxge_hw_ring_callback_f) to notifiy ++ * driver of new completed descriptors. After that ++ * the driver can use vxge_hw_ring_rxd_next_completed to retrieve the rest ++ * completions (the very first completion is passed by HW via ++ * vxge_hw_ring_callback_f). ++ * ++ * Implementation-wise, the driver is free to call ++ * vxge_hw_ring_rxd_next_completed either immediately from inside the ++ * ring callback, or in a deferred fashion and separate (from HW) ++ * context. ++ * ++ * Non-zero @t_code means failure to fill-in receive buffer(s) ++ * of the descriptor. ++ * For instance, parity error detected during the data transfer. ++ * In this case Titan will complete the descriptor and indicate ++ * for the host that the received data is not to be used. ++ * For details please refer to Titan User Guide. ++ * ++ * Returns: VXGE_HW_OK - success. ++ * VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors ++ * are currently available for processing. ++ * ++ * See also: vxge_hw_ring_callback_f{}, ++ * vxge_hw_fifo_rxd_next_completed(), enum vxge_hw_status{}. ++ */ ++enum vxge_hw_status vxge_hw_ring_rxd_next_completed( ++ struct __vxge_hw_ring *ring, void **rxdh, u8 *t_code) ++{ ++ struct __vxge_hw_channel *channel; ++ struct vxge_hw_ring_rxd_1 *rxdp; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ channel = &ring->channel; ++ ++ vxge_hw_channel_dtr_try_complete(channel, rxdh); ++ ++ rxdp = (struct vxge_hw_ring_rxd_1 *)*rxdh; ++ if (rxdp == NULL) { ++ status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS; ++ goto exit; ++ } ++ ++ /* check whether it is not the end */ ++ if (!(rxdp->control_0 & VXGE_HW_RING_RXD_LIST_OWN_ADAPTER)) { ++ ++ vxge_assert(((struct vxge_hw_ring_rxd_1 *)rxdp)->host_control != ++ 0); ++ ++ vxge_hw_channel_dtr_complete(channel); ++ ++ *t_code = (u8)VXGE_HW_RING_RXD_T_CODE_GET(rxdp->control_0); ++ ++ vxge_assert(*t_code != VXGE_HW_RING_RXD_T_CODE_UNUSED); ++ ++ ring->stats->common_stats.usage_cnt++; ++ if (ring->stats->common_stats.usage_max < ++ ring->stats->common_stats.usage_cnt) ++ ring->stats->common_stats.usage_max = ++ ring->stats->common_stats.usage_cnt; ++ ++ status = VXGE_HW_OK; ++ goto exit; ++ } ++ ++ /* reset it. since we don't want to return ++ * garbage to the driver */ ++ *rxdh = NULL; ++ status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS; ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_ring_handle_tcode - Handle transfer code. ++ * @ring: Handle to the ring object used for receive ++ * @rxdh: Descriptor handle. ++ * @t_code: One of the enumerated (and documented in the Titan user guide) ++ * "transfer codes". ++ * ++ * Handle descriptor's transfer code. The latter comes with each completed ++ * descriptor. ++ * ++ * Returns: one of the enum vxge_hw_status{} enumerated types. ++ * VXGE_HW_OK - for success. ++ * VXGE_HW_ERR_CRITICAL - when encounters critical error. ++ */ ++enum vxge_hw_status vxge_hw_ring_handle_tcode( ++ struct __vxge_hw_ring *ring, void *rxdh, u8 t_code) ++{ ++ enum vxge_hw_status status = VXGE_HW_ERR_CRITICAL; ++ ++ /* If the t_code is not supported and if the ++ * t_code is other than 0x5 (unparseable packet ++ * such as unknown UPV6 header), Drop it !!! ++ */ ++ ++ if (t_code == 0 || t_code == 5) { ++ status = VXGE_HW_OK; ++ goto exit; ++ } ++ ++ if (t_code > 0xF) { ++ status = VXGE_HW_ERR_INVALID_TCODE; ++ goto exit; ++ } ++ ++ ring->stats->rxd_t_code_err_cnt[t_code]++; ++exit: ++ return status; ++} ++ ++/** ++ * __vxge_hw_non_offload_db_post - Post non offload doorbell ++ * ++ * @fifo: fifohandle ++ * @txdl_ptr: The starting location of the TxDL in host memory ++ * @num_txds: The highest TxD in this TxDL (0 to 255 means 1 to 256) ++ * @no_snoop: No snoop flags ++ * ++ * This function posts a non-offload doorbell to doorbell FIFO ++ * ++ */ ++static void __vxge_hw_non_offload_db_post(struct __vxge_hw_fifo *fifo, ++ u64 txdl_ptr, u32 num_txds, u32 no_snoop) ++{ ++ writeq(VXGE_HW_NODBW_TYPE(VXGE_HW_NODBW_TYPE_NODBW) | ++ VXGE_HW_NODBW_LAST_TXD_NUMBER(num_txds) | ++ VXGE_HW_NODBW_GET_NO_SNOOP(no_snoop), ++ &fifo->nofl_db->control_0); ++ ++ mmiowb(); ++ ++ writeq(txdl_ptr, &fifo->nofl_db->txdl_ptr); ++ ++ mmiowb(); ++} ++ ++/** ++ * vxge_hw_fifo_free_txdl_count_get - returns the number of txdls available in ++ * the fifo ++ * @fifoh: Handle to the fifo object used for non offload send ++ */ ++u32 vxge_hw_fifo_free_txdl_count_get(struct __vxge_hw_fifo *fifoh) ++{ ++ return vxge_hw_channel_dtr_count(&fifoh->channel); ++} ++ ++/** ++ * vxge_hw_fifo_txdl_reserve - Reserve fifo descriptor. ++ * @fifoh: Handle to the fifo object used for non offload send ++ * @txdlh: Reserved descriptor. On success HW fills this "out" parameter ++ * with a valid handle. ++ * @txdl_priv: Buffer to return the pointer to per txdl space ++ * ++ * Reserve a single TxDL (that is, fifo descriptor) ++ * for the subsequent filling-in by driver) ++ * and posting on the corresponding channel (@channelh) ++ * via vxge_hw_fifo_txdl_post(). ++ * ++ * Note: it is the responsibility of driver to reserve multiple descriptors ++ * for lengthy (e.g., LSO) transmit operation. A single fifo descriptor ++ * carries up to configured number (fifo.max_frags) of contiguous buffers. ++ * ++ * Returns: VXGE_HW_OK - success; ++ * VXGE_HW_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available ++ * ++ */ ++enum vxge_hw_status vxge_hw_fifo_txdl_reserve( ++ struct __vxge_hw_fifo *fifo, ++ void **txdlh, void **txdl_priv) ++{ ++ enum vxge_hw_status status; ++ int i; ++ ++ status = vxge_hw_channel_dtr_alloc(&fifo->channel, txdlh); ++ ++ if (status == VXGE_HW_OK) { ++ struct vxge_hw_fifo_txd *txdp = ++ (struct vxge_hw_fifo_txd *)*txdlh; ++ struct __vxge_hw_fifo_txdl_priv *priv; ++ ++ priv = __vxge_hw_fifo_txdl_priv(fifo, txdp); ++ ++ /* reset the TxDL's private */ ++ priv->align_dma_offset = 0; ++ priv->align_vaddr_start = priv->align_vaddr; ++ priv->align_used_frags = 0; ++ priv->frags = 0; ++ priv->alloc_frags = fifo->config->max_frags; ++ priv->next_txdl_priv = NULL; ++ ++ *txdl_priv = (void *)(size_t)txdp->host_control; ++ ++ for (i = 0; i < fifo->config->max_frags; i++) { ++ txdp = ((struct vxge_hw_fifo_txd *)*txdlh) + i; ++ txdp->control_0 = txdp->control_1 = 0; ++ } ++ } ++ ++ return status; ++} ++ ++/** ++ * vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the ++ * descriptor. ++ * @fifo: Handle to the fifo object used for non offload send ++ * @txdlh: Descriptor handle. ++ * @frag_idx: Index of the data buffer in the caller's scatter-gather list ++ * (of buffers). ++ * @dma_pointer: DMA address of the data buffer referenced by @frag_idx. ++ * @size: Size of the data buffer (in bytes). ++ * ++ * This API is part of the preparation of the transmit descriptor for posting ++ * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include ++ * vxge_hw_fifo_txdl_mss_set() and vxge_hw_fifo_txdl_cksum_set_bits(). ++ * All three APIs fill in the fields of the fifo descriptor, ++ * in accordance with the Titan specification. ++ * ++ */ ++void vxge_hw_fifo_txdl_buffer_set(struct __vxge_hw_fifo *fifo, ++ void *txdlh, u32 frag_idx, ++ dma_addr_t dma_pointer, u32 size) ++{ ++ struct __vxge_hw_fifo_txdl_priv *txdl_priv; ++ struct vxge_hw_fifo_txd *txdp, *txdp_last; ++ struct __vxge_hw_channel *channel; ++ ++ channel = &fifo->channel; ++ ++ txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdlh); ++ txdp = (struct vxge_hw_fifo_txd *)txdlh + txdl_priv->frags; ++ ++ if (frag_idx != 0) ++ txdp->control_0 = txdp->control_1 = 0; ++ else { ++ txdp->control_0 |= VXGE_HW_FIFO_TXD_GATHER_CODE( ++ VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST); ++ txdp->control_1 |= fifo->interrupt_type; ++ txdp->control_1 |= VXGE_HW_FIFO_TXD_INT_NUMBER( ++ fifo->tx_intr_num); ++ if (txdl_priv->frags) { ++ txdp_last = (struct vxge_hw_fifo_txd *)txdlh + ++ (txdl_priv->frags - 1); ++ txdp_last->control_0 |= VXGE_HW_FIFO_TXD_GATHER_CODE( ++ VXGE_HW_FIFO_TXD_GATHER_CODE_LAST); ++ } ++ } ++ ++ vxge_assert(frag_idx < txdl_priv->alloc_frags); ++ ++ txdp->buffer_pointer = (u64)dma_pointer; ++ txdp->control_0 |= VXGE_HW_FIFO_TXD_BUFFER_SIZE(size); ++ fifo->stats->total_buffers++; ++ txdl_priv->frags++; ++} ++ ++/** ++ * vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel. ++ * @fifo: Handle to the fifo object used for non offload send ++ * @txdlh: Descriptor obtained via vxge_hw_fifo_txdl_reserve() ++ * @tagged: Is the frame tagged ++ * ++ * Post descriptor on the 'fifo' type channel for transmission. ++ * Prior to posting the descriptor should be filled in accordance with ++ * Host/Titan interface specification for a given service (LL, etc.). ++ * ++ */ ++void vxge_hw_fifo_txdl_post(struct __vxge_hw_fifo *fifo, void *txdlh, u32 tagged) ++{ ++ struct __vxge_hw_fifo_txdl_priv *txdl_priv; ++ struct vxge_hw_fifo_txd *txdp_last; ++ struct vxge_hw_fifo_txd *txdp_first; ++ struct __vxge_hw_channel *channel; ++ u64 list_ptr; ++ ++ channel = &fifo->channel; ++ ++ txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdlh); ++ txdp_first = (struct vxge_hw_fifo_txd *)txdlh; ++ ++ txdp_last = (struct vxge_hw_fifo_txd *)txdlh + (txdl_priv->frags - 1); ++ txdp_last->control_0 |= ++ VXGE_HW_FIFO_TXD_GATHER_CODE(VXGE_HW_FIFO_TXD_GATHER_CODE_LAST); ++ ++ list_ptr = (u64)txdl_priv->dma_addr; ++ if (tagged) { ++ txdp_first->control_1 |= VXGE_HW_FIFO_TXD_NO_BW_LIMIT; ++ list_ptr |= 0x1; ++ } ++ txdp_first->control_0 |= VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER; ++ ++ vxge_hw_channel_dtr_post(&fifo->channel, txdlh); ++ ++ __vxge_hw_non_offload_db_post(fifo, ++ list_ptr, ++ txdl_priv->frags - 1, ++ fifo->no_snoop_bits); ++ ++ fifo->stats->total_posts++; ++ fifo->stats->common_stats.usage_cnt++; ++ if (fifo->stats->common_stats.usage_max < ++ fifo->stats->common_stats.usage_cnt) ++ fifo->stats->common_stats.usage_max = ++ fifo->stats->common_stats.usage_cnt; ++} ++ ++/** ++ * vxge_hw_fifo_txdl_next_completed - Retrieve next completed descriptor. ++ * @fifo: Handle to the fifo object used for non offload send ++ * @txdlh: Descriptor handle. Returned by HW. ++ * @t_code: Transfer code, as per Titan User Guide, ++ * Transmit Descriptor Format. ++ * Returned by HW. ++ * ++ * Retrieve the _next_ completed descriptor. ++ * HW uses channel callback (*vxge_hw_channel_callback_f) to notifiy ++ * driver of new completed descriptors. After that ++ * the driver can use vxge_hw_fifo_txdl_next_completed to retrieve the rest ++ * completions (the very first completion is passed by HW via ++ * vxge_hw_channel_callback_f). ++ * ++ * Implementation-wise, the driver is free to call ++ * vxge_hw_fifo_txdl_next_completed either immediately from inside the ++ * channel callback, or in a deferred fashion and separate (from HW) ++ * context. ++ * ++ * Non-zero @t_code means failure to process the descriptor. ++ * The failure could happen, for instance, when the link is ++ * down, in which case Titan completes the descriptor because it ++ * is not able to send the data out. ++ * ++ * For details please refer to Titan User Guide. ++ * ++ * Returns: VXGE_HW_OK - success. ++ * VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors ++ * are currently available for processing. ++ * ++ */ ++enum vxge_hw_status vxge_hw_fifo_txdl_next_completed( ++ struct __vxge_hw_fifo *fifo, void **txdlh, ++ enum vxge_hw_fifo_tcode *t_code) ++{ ++ struct __vxge_hw_channel *channel; ++ struct vxge_hw_fifo_txd *txdp; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ channel = &fifo->channel; ++ ++ vxge_hw_channel_dtr_try_complete(channel, txdlh); ++ ++ txdp = (struct vxge_hw_fifo_txd *)*txdlh; ++ if (txdp == NULL) { ++ status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS; ++ goto exit; ++ } ++ ++ /* check whether host owns it */ ++ if (!(txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER)) { ++ ++ vxge_assert(txdp->host_control != 0); ++ ++ vxge_hw_channel_dtr_complete(channel); ++ ++ *t_code = (u8)VXGE_HW_FIFO_TXD_T_CODE_GET(txdp->control_0); ++ ++ if (fifo->stats->common_stats.usage_cnt > 0) ++ fifo->stats->common_stats.usage_cnt--; ++ ++ status = VXGE_HW_OK; ++ goto exit; ++ } ++ ++ /* no more completions */ ++ *txdlh = NULL; ++ status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS; ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_fifo_handle_tcode - Handle transfer code. ++ * @fifo: Handle to the fifo object used for non offload send ++ * @txdlh: Descriptor handle. ++ * @t_code: One of the enumerated (and documented in the Titan user guide) ++ * "transfer codes". ++ * ++ * Handle descriptor's transfer code. The latter comes with each completed ++ * descriptor. ++ * ++ * Returns: one of the enum vxge_hw_status{} enumerated types. ++ * VXGE_HW_OK - for success. ++ * VXGE_HW_ERR_CRITICAL - when encounters critical error. ++ */ ++enum vxge_hw_status vxge_hw_fifo_handle_tcode(struct __vxge_hw_fifo *fifo, ++ void *txdlh, ++ enum vxge_hw_fifo_tcode t_code) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (((t_code & 0x7) < 0) || ((t_code & 0x7) > 0x4)) { ++ status = VXGE_HW_ERR_INVALID_TCODE; ++ goto exit; ++ } ++ ++ fifo->stats->txd_t_code_err_cnt[t_code]++; ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_fifo_txdl_free - Free descriptor. ++ * @fifo: Handle to the fifo object used for non offload send ++ * @txdlh: Descriptor handle. ++ * ++ * Free the reserved descriptor. This operation is "symmetrical" to ++ * vxge_hw_fifo_txdl_reserve. The "free-ing" completes the descriptor's ++ * lifecycle. ++ * ++ * After free-ing (see vxge_hw_fifo_txdl_free()) the descriptor again can ++ * be: ++ * ++ * - reserved (vxge_hw_fifo_txdl_reserve); ++ * ++ * - posted (vxge_hw_fifo_txdl_post); ++ * ++ * - completed (vxge_hw_fifo_txdl_next_completed); ++ * ++ * - and recycled again (vxge_hw_fifo_txdl_free). ++ * ++ * For alternative state transitions and more details please refer to ++ * the design doc. ++ * ++ */ ++void vxge_hw_fifo_txdl_free(struct __vxge_hw_fifo *fifo, void *txdlh) ++{ ++ struct __vxge_hw_fifo_txdl_priv *txdl_priv; ++ u32 max_frags; ++ ++ txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, ++ (struct vxge_hw_fifo_txd *)txdlh); ++ ++ max_frags = fifo->config->max_frags; ++ ++ vxge_hw_channel_dtr_free(&fifo->channel, txdlh); ++} ++ ++/** ++ * vxge_hw_vpath_vid_add_vpn - Add the vlan id entry for this vpath ++ * to vlan id table. ++ * @vp: Vpath handle. ++ * @vid: vlan id to be added for this vpath into the list ++ * ++ * Adds the given vlan id into the list for this vpath. ++ * see also: vxge_hw_vpath_vid_delete, vxge_hw_vpath_vid_get and ++ * vxge_hw_vpath_vid_get_next ++ * ++ * XXX: Code to be merged after GA TODO ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_vid_add_vpn(struct __vxge_hw_vpath_handle *vp, u64 vid, ++ u32 vpn) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ status = __vxge_hw_vpath_rts_table_set_vpn(vp, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID, ++ 0, VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid), 0, vpn); ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_vpath_vid_delete_vpn - Delete the vlan id entry for this vpath ++ * to vlan id table. ++ * @vp: Vpath handle. ++ * @vid: vlan id to be deleted for this vpath into the list ++ * @vpn: Vpath number ++ * ++ * Adds the given vlan id into the list for this vpath. ++ * see also: vxge_hw_vpath_vid_add_vpn, vxge_hw_vpath_vid_get_vpn and ++ * vxge_hw_vpath_vid_get_next_vpn ++ * ++ * XXX: Code to be merged after GA TODO ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_vid_delete_vpn(struct __vxge_hw_vpath_handle *vp, u64 vid, ++ u32 vpn) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ status = __vxge_hw_vpath_rts_table_set_vpn(vp, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID, ++ 0, VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid), 0, vpn); ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_vpath_vid_get_vpn - Get the first vid entry for this vpath ++ * from vlan id table. ++ * @vp: Vpath handle. ++ * @vid: Buffer to return vlan id ++ * @vpn: ++ * ++ * Returns the first vlan id in the list for this vpath. ++ * see also: vxge_hw_vpath_vid_get_next_vpn ++ * ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_vid_get_vpn(struct __vxge_hw_vpath_handle *vp, u64 *vid, u32 vpn) ++{ ++ u64 data; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ status = __vxge_hw_vpath_rts_table_get_vpn(vp, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID, ++ 0, vid, &data, vpn); ++ ++ *vid = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(*vid); ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_vpath_vid_get_next_vpn - Get the next vid entry for this vpath ++ * from vlan id table. ++ * @vp: Vpath handle. ++ * @vid: Buffer to return vlan id ++ * ++ * Returns the next vlan id in the list for this vpath. ++ * see also: vxge_hw_vpath_vid_get_vpn ++ * ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_vid_get_next_vpn(struct __vxge_hw_vpath_handle *vp, u64 *vid, u32 vpn) ++{ ++ u64 data; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ status = __vxge_hw_vpath_rts_table_get_vpn(vp, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID, ++ 0, vid, &data, vpn); ++ ++ *vid = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(*vid); ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_vpath_mac_addr_del_vpn - Delete the mac address entry for this vpath ++ * to MAC address table. ++ * @vp: Vpath handle. ++ * @macaddr: MAC address to be added for this vpath into the list ++ * @macaddr_mask: MAC address mask for macaddr ++ * @vpn : Vpath number ++ * Delete the given mac address and mac address mask for the vpath ++ * ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_mac_addr_del_vpn( ++ struct __vxge_hw_vpath_handle *vp, ++ u8 (macaddr)[ETH_ALEN], ++ u8 (macaddr_mask)[ETH_ALEN], ++ u32 vpn) ++{ ++ u32 i; ++ u64 data1 = 0ULL; ++ u64 data2 = 0ULL; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ for (i = 0; i < ETH_ALEN; i++) { ++ data1 <<= 8; ++ data1 |= (u8)macaddr[i]; ++ ++ data2 <<= 8; ++ data2 |= (u8)macaddr_mask[i]; ++ } ++ ++ status = __vxge_hw_vpath_rts_table_set_vpn(vp, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA, ++ 0, ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1), ++ VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2), ++ vpn); ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_vpath_mac_addr_add_vpn - Add the mac address entry for this vpath ++ * to MAC address table. ++ * @vp: Vpath handle. ++ * @macaddr: MAC address to be added for this vpath into the list ++ * @macaddr_mask: MAC address mask for macaddr ++ * @duplicate_mode: Duplicate MAC address add mode. Please see ++ * enum vxge_hw_vpath_mac_addr_add_mode{} ++ * @vpn: Vpath number ++ * ++ * Deletes the given mac address and mac address mask into the list for this ++ * vpath. This is to be used by the privilege driver ++ * see also: vxge_hw_vpath_mac_addr_delete_vpn, vxge_hw_vpath_mac_addr_get_vpn and ++ * vxge_hw_vpath_mac_addr_get_next_vpn ++ * ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_mac_addr_add_vpn( ++ struct __vxge_hw_vpath_handle *vp, ++ u8 (macaddr)[ETH_ALEN], ++ u8 (macaddr_mask)[ETH_ALEN], ++ enum vxge_hw_vpath_mac_addr_add_mode duplicate_mode, ++ u32 vpn) ++{ ++ u32 i; ++ u64 data1 = 0ULL; ++ u64 data2 = 0ULL; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ for (i = 0; i < ETH_ALEN; i++) { ++ data1 <<= 8; ++ data1 |= (u8)macaddr[i]; ++ ++ data2 <<= 8; ++ data2 |= (u8)macaddr_mask[i]; ++ } ++ ++ switch (duplicate_mode) { ++ case VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE: ++ i = 0; ++ break; ++ case VXGE_HW_VPATH_MAC_ADDR_DISCARD_DUPLICATE: ++ i = 1; ++ break; ++ case VXGE_HW_VPATH_MAC_ADDR_REPLACE_DUPLICATE: ++ i = 2; ++ break; ++ default: ++ i = 0; ++ break; ++ } ++ ++ status = __vxge_hw_vpath_rts_table_set_vpn(vp, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA, ++ 0, ++ VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1), ++ VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2)| ++ VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(i), ++ vpn); ++exit: ++ return status; ++} ++/** ++ * vxge_hw_vpath_mac_addr_get_vpn - Get the first mac address entry ++ * from MAC address table. ++ * @vp: Vpath handle: Privileged vpath only. ++ * @macaddr: First MAC address entry for vpath specified in the list ++ * @macaddr_mask: MAC address mask for macaddr ++ * @vpn: Vpath number: vpath number for which the mac address has ++ * to be retrieved ++ * ++ * Returns the first mac address and mac address mask in the list for the ++ * vpath. ++ * see also: vxge_hw_vpath_mac_addr_get_next_vpn ++ * ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_mac_addr_get_vpn( ++ struct __vxge_hw_vpath_handle *vp, ++ u8 (macaddr)[ETH_ALEN], ++ u8 (macaddr_mask)[ETH_ALEN], ++ u32 vpn) ++{ ++ u32 i; ++ u64 data1 = 0ULL; ++ u64 data2 = 0ULL; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ vxge_assert(vp != NULL); ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ status = __vxge_hw_vpath_rts_table_get_vpn(vp, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA, ++ 0, ++ &data1, ++ &data2, ++ vpn); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1); ++ ++ data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2); ++ ++ for (i = ETH_ALEN; i > 0; i--) { ++ macaddr[i-1] = (u8)(data1 & 0xFF); ++ data1 >>= 8; ++ ++ macaddr_mask[i-1] = (u8)(data2 & 0xFF); ++ data2 >>= 8; ++ } ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_vpath_mac_addr_get_next_vpn - Get the next mac address entry ++ * from MAC address table. ++ * @vp: Vpath handle: Privileged vpath ++ * @macaddr: Next MAC address entry for this vpath in the list ++ * @macaddr_mask: MAC address mask for macaddr ++ * @vpn: Vpath number: vpath number for which the mac address has ++ * to be retrieved ++ * ++ * Returns the next mac address and mac address mask in the list for this ++ * vpath. ++ * see also: vxge_hw_vpath_mac_addr_get_vpn ++ * ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_mac_addr_get_next_vpn( ++ struct __vxge_hw_vpath_handle *vp, ++ u8 (macaddr)[ETH_ALEN], ++ u8 (macaddr_mask)[ETH_ALEN], ++ u32 vpn) ++{ ++ u32 i; ++ u64 data1 = 0ULL; ++ u64 data2 = 0ULL; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ vxge_assert(vp != NULL); ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ status = __vxge_hw_vpath_rts_table_get_vpn(vp, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY, ++ VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA, ++ 0, ++ &data1, ++ &data2, ++ vpn); ++ ++ if (status != VXGE_HW_OK) ++ goto exit; ++ ++ data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1); ++ ++ data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2); ++ ++ for (i = ETH_ALEN; i > 0; i--) { ++ macaddr[i-1] = (u8)(data1 & 0xFF); ++ data1 >>= 8; ++ ++ macaddr_mask[i-1] = (u8)(data2 & 0xFF); ++ data2 >>= 8; ++ } ++ ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_vpath_promisc_enable - Enable promiscuous mode. ++ * @vp: Vpath handle. ++ * ++ * Enable promiscuous mode of Titan-e operation. ++ * ++ * See also: vxge_hw_vpath_promisc_disable(). ++ */ ++void vxge_hw_vpath_promisc_enable( ++ struct __vxge_hw_vpath_handle *vp) ++{ ++ u64 val64; ++ struct __vxge_hw_virtualpath *vpath; ++ ++ vpath = vp->vpath; ++ ++ val64 = readq(&vpath->vp_reg->rxmac_vcfg0); ++ ++ if (!(val64 & VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN)) { ++ ++ val64 |= VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN | ++ VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN | ++ VXGE_HW_RXMAC_VCFG0_ALL_VID_EN; ++ ++ writeq(val64, &vpath->vp_reg->rxmac_vcfg0); ++ } ++ ++ return; ++} ++ ++/** ++ * vxge_hw_vpath_promisc_disable - Disable promiscuous mode. ++ * @vp: Vpath handle. ++ * ++ * Disable promiscuous mode of Titan-e operation. ++ * ++ * See also: vxge_hw_vpath_promisc_enable(). ++ */ ++void vxge_hw_vpath_promisc_disable( ++ struct __vxge_hw_vpath_handle *vp) ++{ ++ u64 val64; ++ struct __vxge_hw_virtualpath *vpath; ++ ++ vpath = vp->vpath; ++ ++ val64 = readq(&vpath->vp_reg->rxmac_vcfg0); ++ ++ if (val64 & VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN) { ++ ++ val64 &= ~(VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN | ++ VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN | ++ VXGE_HW_RXMAC_VCFG0_ALL_VID_EN); ++ ++ writeq(val64, &vpath->vp_reg->rxmac_vcfg0); ++ } ++ ++ return; ++} ++ ++/* ++ * vxge_hw_vpath_bcast_enable - Enable broadcast ++ * @vp: Vpath handle. ++ * ++ * Enable receiving broadcasts. ++ */ ++enum vxge_hw_status vxge_hw_vpath_bcast_enable( ++ struct __vxge_hw_vpath_handle *vp) ++{ ++ u64 val64; ++ struct __vxge_hw_virtualpath *vpath; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if ((vp == NULL) || (vp->vpath->ringh == NULL)) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ vpath = vp->vpath; ++ ++ val64 = readq(&vpath->vp_reg->rxmac_vcfg0); ++ ++ if (!(val64 & VXGE_HW_RXMAC_VCFG0_BCAST_EN)) { ++ val64 |= VXGE_HW_RXMAC_VCFG0_BCAST_EN; ++ writeq(val64, &vpath->vp_reg->rxmac_vcfg0); ++ } ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_vpath_mcast_enable - Enable multicast addresses. ++ * @vp: Vpath handle. ++ * ++ * Enable Titan-e multicast addresses. ++ * Returns: VXGE_HW_OK on success. ++ * ++ */ ++enum vxge_hw_status vxge_hw_vpath_mcast_enable( ++ struct __vxge_hw_vpath_handle *vp) ++{ ++ u64 val64; ++ struct __vxge_hw_virtualpath *vpath; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if ((vp == NULL) || (vp->vpath->ringh == NULL)) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ vpath = vp->vpath; ++ ++ val64 = readq(&vpath->vp_reg->rxmac_vcfg0); ++ ++ if (!(val64 & VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN)) { ++ val64 |= VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN; ++ writeq(val64, &vpath->vp_reg->rxmac_vcfg0); ++ } ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_vpath_mcast_disable - Disable multicast addresses. ++ * @vp: Vpath handle. ++ * ++ * Disable Titan-e multicast addresses. ++ * Returns: VXGE_HW_OK - success. ++ * VXGE_HW_ERR_INVALID_HANDLE - Invalid handle ++ * ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_mcast_disable(struct __vxge_hw_vpath_handle *vp) ++{ ++ u64 val64; ++ struct __vxge_hw_virtualpath *vpath; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if ((vp == NULL) || (vp->vpath->ringh == NULL)) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ vpath = vp->vpath; ++ ++ val64 = readq(&vpath->vp_reg->rxmac_vcfg0); ++ ++ if (val64 & VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN) { ++ val64 &= ~VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN; ++ writeq(val64, &vpath->vp_reg->rxmac_vcfg0); ++ } ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_vpath_all_vid_enable - Enable all Vlan Ids. ++ * @vp: Vpath handle. ++ * ++ * Enable all vlan ids. ++ * Returns: VXGE_HAL_OK on success. ++ * ++ */ ++enum vxge_hw_status ++vxge_hw_vpath_all_vid_enable(struct __vxge_hw_vpath_handle *vp) ++{ u64 val64; ++ struct __vxge_hw_virtualpath *vpath; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if ((vp == NULL) || (vp->vpath->ringh == NULL)) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ vpath = vp->vpath; ++ ++ val64 = readq(&vpath->vp_reg->rxmac_vcfg0); ++ if (!(val64 & VXGE_HW_RXMAC_VCFG0_ALL_VID_EN)) { ++ val64 |= VXGE_HW_RXMAC_VCFG0_ALL_VID_EN; ++ writeq(val64, &vpath->vp_reg->rxmac_vcfg0); ++ } ++exit: ++ return status; ++} ++ ++/* ++ * __vxge_hw_vpath_alarm_process - Process Alarms. ++ * @vpath: Virtual Path. ++ * @skip_alarms: Do not clear the alarms ++ * ++ * Process vpath alarms. ++ * ++ */ ++enum vxge_hw_status __vxge_hw_vpath_alarm_process( ++ struct __vxge_hw_virtualpath *vpath, ++ u32 skip_alarms) ++{ ++ u64 val64; ++ u64 alarm_status; ++ u64 pic_status; ++ struct __vxge_hw_device *hldev = NULL; ++ enum vxge_hw_event alarm_event = VXGE_HW_EVENT_UNKNOWN; ++ u64 mask64; ++ struct vxge_hw_vpath_stats_sw_info *sw_stats; ++ struct vxge_hw_vpath_reg __iomem *vp_reg; ++ ++ if (vpath == NULL) ++ goto out2; ++ ++ hldev = vpath->hldev; ++ vp_reg = vpath->vp_reg; ++ alarm_status = readq(&vp_reg->vpath_general_int_status); ++ ++ if (alarm_status == VXGE_HW_ALL_FOXES) { ++ alarm_event = max((enum vxge_hw_event)VXGE_HW_EVENT_SLOT_FREEZE, ++ alarm_event); ++ goto out; ++ } ++ ++ sw_stats = vpath->sw_stats; ++ ++ if (alarm_status & ~( ++ VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT | ++ VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT | ++ VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT | ++ VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT)) { ++ sw_stats->error_stats.unknown_alarms++; ++ ++ alarm_event = max((enum vxge_hw_event)VXGE_HW_EVENT_UNKNOWN, ++ alarm_event); ++ goto out; ++ } ++ ++ if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT) { ++ ++ val64 = readq(&vp_reg->xgmac_vp_int_status); ++ ++ if (val64 & ++ VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT) { ++ ++ val64 = readq(&vp_reg->asic_ntwk_vp_err_reg); ++ ++ if (((val64 & ++ VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT) && ++ (!(val64 & ++ VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK))) || ++ ((val64 & ++ VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR) ++ && (!(val64 & ++ VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR) ++ ))) { ++ sw_stats->error_stats.network_sustained_fault++; ++ ++ writeq( ++ VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT, ++ &vp_reg->asic_ntwk_vp_err_mask); ++ ++ __vxge_hw_device_handle_link_down_ind(hldev); ++ alarm_event = max( ++ (enum vxge_hw_event)VXGE_HW_EVENT_LINK_DOWN, ++ alarm_event); ++ } ++ ++ if (((val64 & ++ VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK) && ++ (!(val64 & ++ VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT))) || ++ ((val64 & ++ VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR) ++ && (!(val64 & ++ VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR) ++ ))) { ++ ++ sw_stats->error_stats.network_sustained_ok++; ++ ++ writeq( ++ VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK, ++ &vp_reg->asic_ntwk_vp_err_mask); ++ ++ __vxge_hw_device_handle_link_up_ind(hldev); ++ alarm_event = max( ++ (enum vxge_hw_event) ++ VXGE_HW_EVENT_LINK_UP, ++ alarm_event); ++ } ++ ++ writeq(VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->asic_ntwk_vp_err_reg); ++ ++ alarm_event = max( ++ (enum vxge_hw_event)VXGE_HW_EVENT_ALARM_CLEARED, ++ alarm_event); ++ ++ if (skip_alarms) ++ return VXGE_HW_OK; ++ } ++ } ++ ++ if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT) { ++ ++ pic_status = readq(&vp_reg->vpath_ppif_int_status); ++ ++ if (pic_status & ++ VXGE_HW_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_GENERAL_INT) { ++ ++ val64 = readq(&vp_reg->general_errors_reg); ++ mask64 = readq(&vp_reg->general_errors_mask); ++ ++ if ((val64 & ++ VXGE_HW_GENERAL_ERRORS_REG_INI_SERR_DET) & ++ ~mask64) { ++ sw_stats->error_stats.ini_serr_det++; ++ ++ alarm_event = max( ++ (enum vxge_hw_event)VXGE_HW_EVENT_SERR, ++ alarm_event); ++ } ++ ++ if ((val64 & ++ VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW) & ++ ~mask64) { ++ sw_stats->error_stats.dblgen_fifo0_overflow++; ++ ++ alarm_event = max( ++ (enum vxge_hw_event) ++ VXGE_HW_EVENT_FIFO_ERR, ++ alarm_event); ++ } ++ ++ if ((val64 & ++ VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR) & ++ ~mask64) ++ sw_stats->error_stats.statsb_pif_chain_error++; ++ ++ if ((val64 & ++ VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ) & ++ ~mask64) ++ sw_stats->error_stats.statsb_drop_timeout++; ++ ++ if ((val64 & ++ VXGE_HW_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS) & ++ ~mask64) ++ sw_stats->error_stats.target_illegal_access++; ++ ++ if (!skip_alarms) { ++ writeq(VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->general_errors_reg); ++ alarm_event = max( ++ (enum vxge_hw_event) ++ VXGE_HW_EVENT_ALARM_CLEARED, ++ alarm_event); ++ } ++ } ++ ++ if (pic_status & ++ VXGE_HW_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_KDFCCTL_INT) { ++ ++ val64 = readq(&vp_reg->kdfcctl_errors_reg); ++ mask64 = readq(&vp_reg->kdfcctl_errors_mask); ++ ++ if ((val64 & ++ VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR) & ++ ~mask64) { ++ sw_stats->error_stats.kdfcctl_fifo0_overwrite++; ++ ++ alarm_event = max( ++ (enum vxge_hw_event) ++ VXGE_HW_EVENT_FIFO_ERR, ++ alarm_event); ++ } ++ ++ if ((val64 & ++ VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON) & ++ ~mask64) { ++ sw_stats->error_stats.kdfcctl_fifo0_poison++; ++ ++ alarm_event = max( ++ (enum vxge_hw_event) ++ VXGE_HW_EVENT_FIFO_ERR, ++ alarm_event); ++ } ++ ++ if ((val64 & ++ VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR) & ++ ~mask64) { ++ sw_stats->error_stats.kdfcctl_fifo0_dma_error++; ++ ++ alarm_event = max( ++ (enum vxge_hw_event) ++ VXGE_HW_EVENT_FIFO_ERR, ++ alarm_event); ++ } ++ ++ if (!skip_alarms) { ++ writeq(VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->kdfcctl_errors_reg); ++ alarm_event = max( ++ (enum vxge_hw_event) ++ VXGE_HW_EVENT_ALARM_CLEARED, ++ alarm_event); ++ } ++ } ++ ++ } ++ ++ if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT) { ++ ++ val64 = readq(&vp_reg->wrdma_alarm_status); ++ ++ if (val64 & VXGE_HW_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT) { ++ ++ val64 = readq(&vp_reg->prc_alarm_reg); ++ mask64 = readq(&vp_reg->prc_alarm_mask); ++ ++ if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP)& ++ ~mask64) ++ sw_stats->error_stats.prc_ring_bumps++; ++ ++ if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ERR) & ++ ~mask64) { ++ sw_stats->error_stats.prc_rxdcm_sc_err++; ++ ++ alarm_event = max( ++ (enum vxge_hw_event) ++ VXGE_HW_EVENT_VPATH_ERR, ++ alarm_event); ++ } ++ ++ if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT) ++ & ~mask64) { ++ sw_stats->error_stats.prc_rxdcm_sc_abort++; ++ ++ alarm_event = max( ++ (enum vxge_hw_event) ++ VXGE_HW_EVENT_VPATH_ERR, ++ alarm_event); ++ } ++ ++ if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR) ++ & ~mask64) { ++ sw_stats->error_stats.prc_quanta_size_err++; ++ ++ alarm_event = max( ++ (enum vxge_hw_event) ++ VXGE_HW_EVENT_VPATH_ERR, ++ alarm_event); ++ } ++ ++ if (!skip_alarms) { ++ writeq(VXGE_HW_INTR_MASK_ALL, ++ &vp_reg->prc_alarm_reg); ++ alarm_event = max( ++ (enum vxge_hw_event) ++ VXGE_HW_EVENT_ALARM_CLEARED, ++ alarm_event); ++ } ++ } ++ } ++out: ++ hldev->stats.sw_dev_err_stats.vpath_alarms++; ++ ++out2: ++ if ((alarm_event == VXGE_HW_EVENT_ALARM_CLEARED) || ++ (alarm_event == VXGE_HW_EVENT_UNKNOWN)) ++ return VXGE_HW_OK; ++ ++ __vxge_hw_device_handle_error(hldev, vpath->vp_id, alarm_event); ++ ++ if (alarm_event == VXGE_HW_EVENT_SERR) ++ return VXGE_HW_ERR_CRITICAL; ++ ++ return (alarm_event == VXGE_HW_EVENT_SLOT_FREEZE) ? ++ VXGE_HW_ERR_SLOT_FREEZE : ++ (alarm_event == VXGE_HW_EVENT_FIFO_ERR) ? VXGE_HW_ERR_FIFO : ++ VXGE_HW_ERR_VPATH; ++} ++ ++/* ++ * vxge_hw_vpath_alarm_process - Process Alarms. ++ * @vpath: Virtual Path. ++ * @skip_alarms: Do not clear the alarms ++ * ++ * Process vpath alarms. ++ * ++ */ ++enum vxge_hw_status vxge_hw_vpath_alarm_process( ++ struct __vxge_hw_vpath_handle *vp, ++ u32 skip_alarms) ++{ ++ enum vxge_hw_status status = VXGE_HW_OK; ++ ++ if (vp == NULL) { ++ status = VXGE_HW_ERR_INVALID_HANDLE; ++ goto exit; ++ } ++ ++ status = __vxge_hw_vpath_alarm_process(vp->vpath, skip_alarms); ++exit: ++ return status; ++} ++ ++/** ++ * vxge_hw_vpath_msix_set - Associate MSIX vectors with TIM interrupts and ++ * alrms ++ * @vp: Virtual Path handle. ++ * @tim_msix_id: MSIX vectors associated with VXGE_HW_MAX_INTR_PER_VP number of ++ * interrupts(Can be repeated). If fifo or ring are not enabled ++ * the MSIX vector for that should be set to 0 ++ * @alarm_msix_id: MSIX vector for alarm. ++ * ++ * This API will associate a given MSIX vector numbers with the four TIM ++ * interrupts and alarm interrupt. ++ */ ++void ++vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id, ++ int alarm_msix_id) ++{ ++ u64 val64; ++ struct __vxge_hw_virtualpath *vpath = vp->vpath; ++ struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg; ++ u32 vp_id = vp->vpath->vp_id; ++ ++ /* Write the internal msi-x vectors numbers */ ++ val64 = VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI( ++ (vp_id * 4) + tim_msix_id[0]) | ++ VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI( ++ (vp_id * 4) + tim_msix_id[1]); ++ ++ writeq(val64, &vp_reg->interrupt_cfg0); ++ ++ writeq(VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG( ++ (vpath->hldev->first_vp_id * 4) + alarm_msix_id), ++ &vp_reg->interrupt_cfg2); ++ ++ if ( ++ ++ (vpath->hldev->config.intr_mode == ++ VXGE_HW_INTR_MODE_MSIX_ONE_SHOT)) { ++ __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn( ++ VXGE_HW_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN, ++ 0, 32), &vp_reg->one_shot_vect1_en); ++ } ++ ++ if (vpath->hldev->config.intr_mode == ++ VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) { ++ __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn( ++ VXGE_HW_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN, ++ 0, 32), &vp_reg->one_shot_vect2_en); ++ ++ __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn( ++ VXGE_HW_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN, ++ 0, 32), &vp_reg->one_shot_vect3_en); ++ } ++ ++ return; ++} ++ ++/** ++ * vxge_hw_vpath_msix_mask - Mask MSIX Vector. ++ * @vp: Virtual Path handle. ++ * @msix_id: MSIX ID ++ * ++ * The function masks the msix interrupt for the given msix_id ++ * ++ * Returns: 0, ++ * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range ++ * status. ++ * See also: ++ */ ++void ++vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vp, int msix_id) ++{ ++ struct __vxge_hw_device *hldev = vp->vpath->hldev; ++ __vxge_hw_pio_mem_write32_upper( ++ (u32) vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32), ++ &hldev->common_reg->set_msix_mask_vect[msix_id % 4]); ++ ++ return; ++} ++ ++/** ++ * vxge_hw_vpath_msix_clear - Clear MSIX Vector. ++ * @vp: Virtual Path handle. ++ * @msix_id: MSI ID ++ * ++ * The function clears the msix interrupt for the given msix_id ++ * ++ * Returns: 0, ++ * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range ++ * status. ++ * See also: ++ */ ++void ++vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id) ++{ ++ struct __vxge_hw_device *hldev = vp->vpath->hldev; ++ ++ if ( ++ ++ (hldev->config.intr_mode == ++ VXGE_HW_INTR_MODE_MSIX_ONE_SHOT)) { ++ __vxge_hw_pio_mem_write32_upper( ++ (u32)vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32), ++ &hldev->common_reg-> ++ clr_msix_one_shot_vec[msix_id%4]); ++ } else { ++ __vxge_hw_pio_mem_write32_upper( ++ (u32)vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32), ++ &hldev->common_reg-> ++ clear_msix_mask_vect[msix_id%4]); ++ } ++ ++ return; ++} ++ ++/** ++ * vxge_hw_vpath_msix_unmask - Unmask the MSIX Vector. ++ * @vp: Virtual Path handle. ++ * @msix_id: MSI ID ++ * ++ * The function unmasks the msix interrupt for the given msix_id ++ * ++ * Returns: 0, ++ * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range ++ * status. ++ * See also: ++ */ ++void ++vxge_hw_vpath_msix_unmask(struct __vxge_hw_vpath_handle *vp, int msix_id) ++{ ++ __vxge_hw_pio_mem_write32_upper( ++ (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32), ++ &vp->vpath->hldev->common_reg->clear_msix_mask_vect[msix_id%4]); ++ ++ return; ++} ++ ++/** ++ * vxge_hw_vpath_msix_mask_all - Mask all MSIX vectors for the vpath. ++ * @vp: Virtual Path handle. ++ * ++ * The function masks all msix interrupt for the given vpath ++ * ++ */ ++void ++vxge_hw_vpath_msix_mask_all(struct __vxge_hw_vpath_handle *vp) ++{ ++ __vxge_hw_pio_mem_write32_upper( ++ (u32)vxge_bVALn(vxge_mBIT(vp->vpath->vp_id), 0, 32), ++ &vp->vpath->hldev->common_reg->set_msix_mask_all_vect); ++ ++ return; ++} ++ ++/** ++ * vxge_hw_vpath_inta_mask_tx_rx - Mask Tx and Rx interrupts. ++ * @vp: Virtual Path handle. ++ * ++ * Mask Tx and Rx vpath interrupts. ++ * ++ * See also: vxge_hw_vpath_inta_mask_tx_rx() ++ */ ++void vxge_hw_vpath_inta_mask_tx_rx(struct __vxge_hw_vpath_handle *vp) ++{ ++ u64 tim_int_mask0[4] = {[0 ...3] = 0}; ++ u32 tim_int_mask1[4] = {[0 ...3] = 0}; ++ u64 val64; ++ struct __vxge_hw_device *hldev = vp->vpath->hldev; ++ ++ VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0, ++ tim_int_mask1, vp->vpath->vp_id); ++ ++ val64 = readq(&hldev->common_reg->tim_int_mask0); ++ ++ if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) || ++ (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) { ++ writeq((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] | ++ tim_int_mask0[VXGE_HW_VPATH_INTR_RX] | val64), ++ &hldev->common_reg->tim_int_mask0); ++ } ++ ++ val64 = readl(&hldev->common_reg->tim_int_mask1); ++ ++ if ((tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) || ++ (tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) { ++ __vxge_hw_pio_mem_write32_upper( ++ (tim_int_mask1[VXGE_HW_VPATH_INTR_TX] | ++ tim_int_mask1[VXGE_HW_VPATH_INTR_RX] | val64), ++ &hldev->common_reg->tim_int_mask1); ++ } ++ ++ return; ++} ++ ++/** ++ * vxge_hw_vpath_inta_unmask_tx_rx - Unmask Tx and Rx interrupts. ++ * @vp: Virtual Path handle. ++ * ++ * Unmask Tx and Rx vpath interrupts. ++ * ++ * See also: vxge_hw_vpath_inta_mask_tx_rx() ++ */ ++void vxge_hw_vpath_inta_unmask_tx_rx(struct __vxge_hw_vpath_handle *vp) ++{ ++ u64 tim_int_mask0[4] = {[0 ...3] = 0}; ++ u32 tim_int_mask1[4] = {[0 ...3] = 0}; ++ u64 val64; ++ struct __vxge_hw_device *hldev = vp->vpath->hldev; ++ ++ VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0, ++ tim_int_mask1, vp->vpath->vp_id); ++ ++ val64 = readq(&hldev->common_reg->tim_int_mask0); ++ ++ if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) || ++ (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) { ++ writeq((~(tim_int_mask0[VXGE_HW_VPATH_INTR_TX] | ++ tim_int_mask0[VXGE_HW_VPATH_INTR_RX])) & val64, ++ &hldev->common_reg->tim_int_mask0); ++ } ++ ++ if ((tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) || ++ (tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) { ++ __vxge_hw_pio_mem_write32_upper( ++ (~(tim_int_mask1[VXGE_HW_VPATH_INTR_TX] | ++ tim_int_mask1[VXGE_HW_VPATH_INTR_RX])) & val64, ++ &hldev->common_reg->tim_int_mask1); ++ } ++ ++ return; ++} ++ ++/** ++ * vxge_hw_vpath_doorbell_rx - Indicates to hw the qwords of receive ++ * descriptors posted. ++ * @ring: Handle to the ring object used for receive ++ * ++ * The function writes the number of qwords of rxds posted during replishment. ++ * Since the function is called frequently, a flush is not required to post the ++ * write transaction. At the very least, the previous write will be flushed ++ * once the subsequent write is made. ++ * ++ * Returns: None. ++ */ ++void vxge_hw_vpath_doorbell_rx(struct __vxge_hw_ring *ring) ++{ ++ int rxds_qw_per_block = ring->rxds_per_block * ++ VXGE_HW_RING_RXD_QWORDS_MODE_1; ++ ++ ring->doorbell_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1; ++ ++ ring->total_db_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1; ++ ++ if (ring->total_db_cnt >= rxds_qw_per_block) { ++ /* For each block add 4 more qwords */ ++ ring->doorbell_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1; ++ ++ /* Reset total count */ ++ ring->total_db_cnt -= rxds_qw_per_block; ++ } ++ ++ if (ring->doorbell_cnt >= ring->rxd_qword_limit) { ++ mmiowb(); ++ writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT( ++ ring->doorbell_cnt), ++ &ring->vp_reg->prc_rxd_doorbell); ++ ring->doorbell_cnt = 0; ++ } ++} ++ ++/** ++ * vxge_hw_vpath_poll_rx - Poll Rx Virtual Path for completed ++ * descriptors and process the same. ++ * @ring: Handle to the ring object used for receive ++ * ++ * The function polls the Rx for the completed descriptors and calls ++ * the driver via supplied completion callback. ++ * ++ * Returns: VXGE_HW_OK, if the polling is completed successful. ++ * VXGE_HW_COMPLETIONS_REMAIN: There are still more completed ++ * descriptors available which are yet to be processed. ++ * ++ * See also: vxge_hw_vpath_poll_rx() ++ */ ++enum vxge_hw_status vxge_hw_vpath_poll_rx(struct __vxge_hw_ring *ring) ++{ ++ u8 t_code; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ void *first_rxdh; ++ ++ status = vxge_hw_ring_rxd_next_completed(ring, &first_rxdh, &t_code); ++ if (status == VXGE_HW_OK) ++ ring->callback(ring, first_rxdh, ++ t_code, ring->channel.userdata); ++ ++ return status; ++} ++ ++/** ++ * vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process ++ * the same. ++ * @fifo: Handle to the fifo object used for non offload send ++ * ++ * The function polls the Tx for the completed descriptors and calls ++ * the driver via supplied completion callback. ++ * ++ * Returns: VXGE_HW_OK, if the polling is completed successful. ++ * VXGE_HW_COMPLETIONS_REMAIN: There are still more completed ++ * descriptors available which are yet to be processed. ++ * ++ * See also: vxge_hw_vpath_poll_tx(). ++ */ ++enum vxge_hw_status vxge_hw_vpath_poll_tx(struct __vxge_hw_fifo *fifo, ++ struct sk_buff ***skb_ptr, int nr_skb, ++ int *more) ++{ ++ enum vxge_hw_fifo_tcode t_code; ++ void *first_txdlh; ++ enum vxge_hw_status status = VXGE_HW_OK; ++ struct __vxge_hw_channel *channel; ++ ++ channel = &fifo->channel; ++ ++ status = vxge_hw_fifo_txdl_next_completed(fifo, ++ &first_txdlh, &t_code); ++ if (status == VXGE_HW_OK) ++ if (fifo->callback(fifo, first_txdlh, t_code, ++ channel->userdata, skb_ptr, nr_skb, more) != VXGE_HW_OK) ++ status = VXGE_HW_COMPLETIONS_REMAIN; ++ ++ return status; ++} ++ ++static inline int vxge_os_is_my_packet(struct __vxge_hw_device *devh, u32 daddr) ++{ ++ struct in_device *in_dev = NULL; ++ struct in_ifaddr *ifa = NULL; ++ struct net_device *dev = devh->ndev; ++ ++ in_dev = dev->ip_ptr; ++ ++ if (in_dev != NULL) { ++ ifa = (struct in_ifaddr *) in_dev->ifa_list; ++ while (ifa != NULL) { ++ if (daddr == ifa->ifa_local) ++ return 0; ++ ifa = ifa->ifa_next; ++ } ++ } ++ return 1; ++ ++} ++ ++/** ++ * vxge_hw_vpath_set_lro_sg_size - Set the new s. ++ * @vp: Vpath handle ++ * @lro_sg_size: Max aggregatable pkts per session ++ */ ++void vxge_hw_vpath_set_lro_sg_size( ++ struct __vxge_hw_vpath_handle *vp, int lro_sg_size) ++{ ++ struct __vxge_hw_virtualpath *vpath; ++ struct __vxge_hw_ring *ring; ++ ++ vxge_assert(vp != NULL); ++ vpath = vp->vpath; ++ ring = vpath->ringh; ++ if (ring) /* Did user configured this ring? */ ++ ring->config->sw_lro_sg_size = lro_sg_size; ++} ++ ++/* ++ * __hw_l4_pyld_length_get : Find the tcp seg len. ++ * @tcp: tcp header. ++ * @ip: ip header. ++ * ++ * Finds the tcp seg len. ++ */ ++static inline u32 ++__hw_l4_pyld_length_get(struct tcphdr *tcp, struct iphdr *ip) ++{ ++ u32 ret; ++ ret = (ntohs(ip->tot_len) - (ip->ihl << 2) - ++ (tcp->doff << 2)); ++ return ret; ++} ++ ++enum vxge_hw_status ++__vxge_hw_sw_lro_capable( ++ struct __vxge_hw_ring *ring, u8 *buffer, ++ struct iphdr **ip, struct tcphdr **tcp, ++ struct vxge_hw_ring_rxd_info *ext_info) ++{ ++ u8 ip_off, ip_length; ++ u32 daddr; ++ u16 vlan_id = 0; ++ ++ /* Check whether it is a TCP Packet Non TCP packets can not be LROed */ ++ if (!(ext_info->proto & VXGE_HW_FRAME_PROTO_TCP)) ++ return VXGE_HW_FAIL; ++ ++ if (!*ip) { ++ ++ if ((ext_info->frame == VXGE_HW_FRAME_TYPE_DIX) || ++ (ext_info->is_vlan == 1)) { ++ ++ ip_off = ETH_HLEN; ++ /* Get the Vlan ID of the frame */ ++ vlan_id = VXGE_HW_VLAN_VID_MASK & ext_info->vlan; ++ /* ++ * If vlan stripping is disabled and the frame is VLAN ++ * tagged, shift the offset by the VLAN header size ++ * bytes. ++ */ ++ if ((ring->rpa_strip_vlan_tag == ++ VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE) && ++ vlan_id) ++ ip_off += VXGE_HW_HEADER_VLAN_SIZE; ++ ++ } else { ++ /* LLC, SNAP etc are considered non-mergeable */ ++ return VXGE_HW_FAIL; ++ } ++ ++ /* Grab ip headers */ ++ *ip = (struct iphdr *)((char *)buffer + ip_off); ++ } /* !*ip */ ++ ++ ip_length = (u8)(*ip)->ihl; ++ ip_length = ip_length << 2; ++ ++ /* Grab the tcp header */ ++ *tcp = (struct tcphdr *)((char *)*ip + ip_length); ++ ++ if (ring->lro_enable == VXGE_HW_LRO_DONT_AGGR_FWD_PKTS) { ++ daddr = (*ip)->daddr; ++ /* Check if it is a broadcast or multicast ip */ ++ if (!vxge_os_in_multicast(daddr) && ++ (VXGE_OS_INADDR_BROADCAST != daddr)) { ++ ++ /* ++ * Does this packets destined for this interface? ++ */ ++ if (!vxge_os_is_my_packet(ring->channel.devh, ++ daddr)) ++ return VXGE_HW_OK; ++ ++ /* Check if it is a vlan packet */ ++ if (ext_info->vlgrp && vlan_id) { ++ struct net_device *vlan_dev = NULL; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)) ++ struct vlan_dev_info *vlan_info = NULL; ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) ++ vlan_dev = vlan_group_get_device( ++ ext_info->vlgrp, vlan_id); ++#else ++ vlan_dev = ++ ext_info->vlgrp->vlan_devices[vlan_id]; ++#endif ++ if (!vlan_dev) ++ return VXGE_HW_FAIL; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)) ++ vlan_info = (struct vlan_dev_info *) ++ netdev_priv(vlan_dev); ++ if (!vlan_info) ++ return VXGE_HW_FAIL; ++ ++ /* Is this a registered vlan? */ ++ if (vlan_info->real_dev == ext_info->dev) ++#else ++ if (vlan_dev_real_dev(vlan_dev) == ++ ext_info->dev) ++#endif ++ return VXGE_HW_OK; ++ } ++ ++ return VXGE_HW_FAIL; ++ ++ } ++ ++ } ++ return VXGE_HW_OK; ++ ++} ++ ++static int __hw_update_tcp_timestamp_slow(struct tcphdr *th, ++ struct vxge_hw_sw_lro *lro, int save) ++{ ++ unsigned char *ptr; ++ int opt_cnt = 0; ++ int length = ((th->doff<< 2) - sizeof(struct tcphdr)); ++ ++ ptr = (unsigned char *)(th + 1); ++ ++ while (length > 0) { ++ int opcode = *ptr++; ++ int opsize; ++ ++ switch (opcode) { ++ case VXGE_HW_TCPOPT_EOL: ++ return 1; ++ case VXGE_HW_TCPOPT_NOP: ++ length--; ++ continue; ++ default: ++ /* Not sure about this check, but not taking a chance */ ++ if ((opcode == VXGE_HW_TCPOPT_SACK_PERM) || ++ (opcode == VXGE_HW_TCPOPT_SACK)) ++ return 1; ++ opsize = *ptr++; ++ if (opsize < 2) ++ return 1; ++ /* don't parse partial options */ ++ if (opsize > length) ++ return 1; ++ if (++opt_cnt > 3) ++ return 1; ++ if (opcode == VXGE_HW_TCPOPT_TIMESTAMP) { ++ if (opsize == VXGE_HW_TCPOLEN_TIMESTAMP) { ++ if (save == VXGE_HW_TS_SAVE) { ++ lro->cur_tsval = ++ ntohl( ++ *(__be32 *)ptr); ++ lro->cur_tsecr = ++ *(__be32 *) ++ (ptr + 4); ++ } else if (save == VXGE_HW_TS_VERIFY) { ++ /* Ensure timestamp value ++ * increases monotonically ++ */ ++ if (lro->cur_tsval > ++ ntohl( ++ *((__be32 *)ptr))) ++ return -1; ++ /* timestamp echo reply should ++ * be non-zero ++ */ ++ if (*((__be32 *) ++ (ptr + 4)) == 0) ++ return -1; ++ } else { ++ __be32 *tmp_ptr = ++ (__be32 *) ++ (ptr + 4); ++ *tmp_ptr = lro->cur_tsecr; ++ } ++ return 0; ++ } ++ } ++ ptr += opsize-2; ++ length -= opsize; ++ } ++ } ++ return 1; ++} ++ ++static int __hw_update_tcp_timestamp(struct tcphdr *tcph, ++ struct vxge_hw_sw_lro *lro, int save) ++{ ++ if (tcph->doff == (sizeof(struct tcphdr) >> 2)) { ++ return VXGE_HW_FAIL; ++ ++ } else if (tcph->doff == ((sizeof(struct tcphdr) >> 2) ++ + (VXGE_HW_TCPOLEN_TSTAMP_ALIGNED >> 2))) { ++ ++ __be32 *ptr = (__be32 *)(tcph + 1); ++ ++ if (*ptr == htonl((VXGE_HW_TCPOPT_NOP << 24) | ++ (VXGE_HW_TCPOPT_NOP << 16) | ++ (VXGE_HW_TCPOPT_TIMESTAMP << 8) | ++ VXGE_HW_TCPOLEN_TIMESTAMP)) { ++ ++ ++ptr; ++ if (save == VXGE_HW_TS_SAVE) { ++ lro->cur_tsval = ntohl( ++ *(__be32 *)ptr); ++ lro->cur_tsecr = *(__be32 *)(ptr + 1); ++ } else if (save == VXGE_HW_TS_VERIFY) { ++ /* Ensure timestamp value increases ++ monotonically */ ++ if (lro->cur_tsval > ++ ntohl(*((__be32 *)ptr))) ++ return VXGE_HW_FAIL; ++ ++ /* timestamp echo reply should be non-zero */ ++ if (*((__be32 *)(ptr + 1)) == 0) ++ return VXGE_HW_FAIL; ++ } else ++ *(ptr + 1) = lro->cur_tsecr; ++ ++ return VXGE_HW_OK; ++ } ++ } ++ return __hw_update_tcp_timestamp_slow(tcph, lro, save); ++} ++ ++static enum vxge_hw_status ++__hw_lro_l3_l4_lro_capable(struct iphdr *ip, ++ struct vxge_hw_ring_rxd_info *rxd_info, ++ struct vxge_hw_sw_lro *lro, ++ struct tcphdr *tcp, u32 tcp_pyld_len, ++ u8 aggr_ack) ++{ ++ u8 ip_length; ++ if (!aggr_ack && !tcp_pyld_len) { ++ /* Pure ACK */ ++ return VXGE_HW_FAIL; ++ } ++ ++ /* Ensure there are no IP options */ ++ ip_length = (u8)ip->ihl; ++ ip_length = ip_length << 2; ++ if (ip_length != sizeof(*ip)) ++ return VXGE_HW_FAIL; ++ ++ /* IP packet is not fragmented */ ++ if (rxd_info->proto & VXGE_HW_FRAME_PROTO_IP_FRAG) ++ return VXGE_HW_FAIL; ++ ++ /* If we see CE codepoint in IP header, packet is not mergeable */ ++ if ((ip->tos & VXGE_HW_INET_ECN_MASK) == VXGE_HW_INET_ECN_CE) ++ return VXGE_HW_FAIL; ++ ++ /* If we see ECE or CWR flags or CTRL flags in TCP header, ++ * packet is not mergeable */ ++ if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || ++ tcp->fin || tcp->ece || tcp->cwr || !tcp->ack) { ++ /* ++ * Currently recognize only the ack control word and ++ * any other control field being set would result in ++ * flushing the LRO session ++ */ ++ return VXGE_HW_FAIL; ++ } ++ ++ if (lro) ++ if (__hw_update_tcp_timestamp(tcp, lro, VXGE_HW_TS_VERIFY) ++ == -1) ++ return VXGE_HW_FAIL; ++ ++ return VXGE_HW_OK; ++} ++/* ++ * __hw_append_lro: Appends new frame to existing LRO session. ++ * @lro: lro pointer ++ * @tcp: IN tcp header, OUT tcp payload. ++ * @ip: ip header. ++ * @seg_len: tcp payload length. ++ * ++ * Appends new frame to existing LRO session. ++ */ ++static inline enum vxge_hw_status ++__hw_append_lro(struct vxge_hw_sw_lro *lro, ++ struct tcphdr **tcp, ++ struct iphdr *ip, ++ u32 *tcp_seg_len) ++{ ++ *tcp_seg_len = __hw_l4_pyld_length_get(*tcp, ip); ++ lro->total_length += *tcp_seg_len; ++ lro->frags_len += *tcp_seg_len; ++ lro->tcp_next_seq_num += *tcp_seg_len; ++ lro->window = (*tcp)->window; ++ if (lro->saw_ts) ++ __hw_update_tcp_timestamp((*tcp), lro, VXGE_HW_TS_SAVE); ++ /* ++ * Update mbuf chain will be done in ll driver. ++ * xge_hw_accumulate_large_rx on success of appending new frame to ++ * lro will return to ll driver tcpdata pointer, and tcp payload length. ++ * along with return code lro frame appended. ++ */ ++ lro->tcp_seq_num = (*tcp)->seq; ++ lro->tcp_ack_num = (*tcp)->ack_seq; ++ ++ lro->sg_num++; ++ *tcp = (struct tcphdr *)((char *)*tcp + ((*tcp)->doff << 2)); ++ ++ return VXGE_HW_OK; ++} ++ ++void vxge_hw_update_L3L4_header( ++ struct __vxge_hw_ring *ring, ++ struct vxge_hw_sw_lro *lro) ++{ ++ struct tcphdr *tcp = lro->tcph; ++ struct iphdr *ip = lro->iph; ++ u16 nchk; ++ ++ vxge_assert(ring != NULL); ++ ++ /* Update L3 Header */ ++ ip->tot_len = htons(lro->total_length); ++ ip->check = 0; ++ nchk = ip_fast_csum((u8 *)ip, ip->ihl); ++ ip->check = nchk; ++ ++ /* Update L4 Header */ ++ tcp->ack_seq = lro->tcp_ack_num; ++ tcp->window = lro->window; ++ ++ /* Update tsecr field if this session has timestamps enabled */ ++ if (lro->saw_ts) ++ __hw_update_tcp_timestamp(tcp, lro, VXGE_HW_TS_UPDATE); ++ ++ ring->stats->lro_num_aggregations++; ++ ring->stats->lro_sum_avg_pkts_aggregated += lro->sg_num; ++} ++ ++/* ++ * __hw_lro_check_for_session_match: Check if frame belongs to given lro. ++ * @lro: LRO session ++ * @tcp: tcp header. ++ * @ip: ip header. ++ * ++ * Check if frame belongs to given lro. ++ */ ++static inline enum vxge_hw_status ++__hw_lro_check_for_session_match(struct vxge_hw_sw_lro *lro, ++ struct tcphdr *tcp, struct iphdr *ip) ++{ ++ if ((lro->iph->saddr != ip->saddr) || ++ (lro->iph->daddr != ip->daddr) || ++ (lro->tcph->source != tcp->source) || ++ (lro->tcph->dest != tcp->dest)) ++ return VXGE_HW_FAIL; ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * __hw_lro_under_optimal_thresh: Finds whether combined session is optimal. ++ * @ring: Handle to the ring object used for receive ++ * @lro: lro pointer ++ * @tcp: tcp header. ++ * @ip: ip header. ++ * ++ * Finds whether combined session is optimal. ++ */ ++static inline enum vxge_hw_status ++__hw_lro_under_optimal_thresh(struct __vxge_hw_ring *ring, ++ struct vxge_hw_sw_lro *lro, ++ struct tcphdr *tcp, struct iphdr *ip) ++{ ++ if (!lro) ++ return VXGE_HW_FAIL; ++ ++ if ((lro->total_length + __hw_l4_pyld_length_get(tcp, ip)) > ++ ring->config->sw_lro_frm_len) { ++ return VXGE_HW_FAIL; ++ } ++ ++ if (lro->sg_num == ring->config->sw_lro_sg_size) ++ return VXGE_HW_FAIL; ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * __hw_open_lro_session: Open a new LRO session. ++ * @ring: Handle to the ring object used for receive ++ * @buffer: Ethernet frame. ++ * @tcp: tcp header. ++ * @ip: ip header. ++ * @lro: lro pointer ++ * @tcp_seg_len: Length of tcp segment. ++ * ++ * Opens a new LRO session. ++ */ ++static inline enum vxge_hw_status ++__hw_open_lro_session( ++ struct __vxge_hw_ring *ring, u8 *buffer, ++ struct tcphdr *tcp, ++ struct iphdr *ip, ++ struct vxge_hw_sw_lro **lro, ++ u32 tcp_seg_len) ++{ ++ if (!list_empty(&ring->free_sw_lros)) { ++ *lro = list_entry(ring->free_sw_lros.next, ++ struct vxge_hw_sw_lro, lro_node); ++ list_del(&(*lro)->lro_node); ++ list_add(&(*lro)->lro_node, &ring->active_sw_lros); ++ } else { ++ *lro = NULL; ++ return VXGE_HW_INF_SW_LRO_UNCAPABLE; ++ } ++ ++ (*lro)->iph = ip; ++ (*lro)->tcph = tcp; ++ (*lro)->window = tcp->window; ++ (*lro)->tcp_next_seq_num = tcp_seg_len + ++ ntohl(tcp->seq); ++ (*lro)->tcp_seq_num = tcp->seq; ++ (*lro)->tcp_ack_num = tcp->ack_seq; ++ (*lro)->sg_num = 1; ++ (*lro)->total_length = ntohs(ip->tot_len); ++ (*lro)->frags_len = 0; ++ ++ /* ++ * check if we saw TCP timestamp. Other consistency checks have ++ * already been done. ++ */ ++ if (!__hw_update_tcp_timestamp(tcp, *lro, VXGE_HW_TS_SAVE)) ++ (*lro)->saw_ts = 1; ++ ++ return VXGE_HW_OK; ++ ++} ++ ++/* ++ * __hw_get_lro_session: Gets matching LRO session or creates one. ++ * @ring: Handle to the ring object used for receive ++ * @rxd_info: Descriptor info. ++ * @eth_hdr: Ethernet header. ++ * @tcp: tcp header. ++ * @ip: ip header. ++ * @lro: lro pointer ++ * ++ * Gets matching LRO session or creates one. ++ */ ++static inline enum vxge_hw_status ++__hw_get_lro_session( ++ struct __vxge_hw_ring *ring, ++ struct vxge_hw_ring_rxd_info *rxd_info, ++ u8 *eth_hdr, ++ struct tcphdr *tcp, ++ struct iphdr *ip, ++ struct vxge_hw_sw_lro **lro) ++{ ++ struct vxge_hw_sw_lro *lro_desc; ++ u32 tcp_seg_len; ++ ++ *lro = NULL; ++ ++ /* ++ * Search in the pool of LROs for the session that matches ++ * the incoming frame. ++ */ ++ list_for_each_entry(lro_desc, &ring->active_sw_lros, lro_node) { ++ if (__hw_lro_check_for_session_match(lro_desc, tcp, ip) == ++ VXGE_HW_OK) { ++ *lro = lro_desc; ++ break; ++ } ++ } ++ ++ tcp_seg_len = __hw_l4_pyld_length_get(tcp, ip); ++ if (*lro) { ++ /* ++ * Matching LRO Session found ++ */ ++ if ((*lro)->tcp_next_seq_num != ntohl(tcp->seq)) { ++ /* Out of Order Packets */ ++ ring->stats->lro_outof_sequence_pkts++; ++ return VXGE_HW_INF_SW_LRO_FLUSH_BOTH; ++ } ++ if (__hw_lro_l3_l4_lro_capable(ip, rxd_info, *lro, tcp, ++ tcp_seg_len, ++ ring->aggr_ack)) ++ return VXGE_HW_INF_SW_LRO_FLUSH_BOTH; ++ ++ /* ++ * The frame is good, in-sequence, can be LRO-ed; ++ * take its (latest) ACK - unless it is a dupack. ++ * Note: to be exact need to check window size as well.. ++ */ ++ if ((*lro)->tcp_ack_num == tcp->ack_seq && ++ (*lro)->tcp_seq_num == tcp->seq) { ++ return VXGE_HW_INF_SW_LRO_FLUSH_BOTH; ++ } ++ ++ return VXGE_HW_INF_SW_LRO_CONT; ++ } ++ ++ /*********** New Session ***************/ ++ ++ if (__hw_lro_l3_l4_lro_capable(ip, rxd_info, *lro, tcp, ++ tcp_seg_len, ++ ring->aggr_ack)) ++ return VXGE_HW_INF_SW_LRO_UNCAPABLE; ++ ++ if (__hw_open_lro_session(ring, eth_hdr, tcp, ip, lro, tcp_seg_len) ++ != VXGE_HW_OK) ++ return VXGE_HW_INF_SW_LRO_UNCAPABLE; ++ ++ return VXGE_HW_INF_SW_LRO_BEGIN; ++} ++ ++static void ++vxge_hw_sw_lro_reset_node(struct vxge_hw_sw_lro *sw_lro) ++{ ++ /* Need better way to reset */ ++ sw_lro->os_buf = NULL; ++ sw_lro->iph = NULL; ++ sw_lro->tcph = NULL; ++ sw_lro->tcp_next_seq_num = 0; ++ sw_lro->tcp_seq_num = 0; ++ sw_lro->tcp_ack_num = 0; ++ sw_lro->sg_num = 0; ++ sw_lro->total_length = 0; ++ sw_lro->frags_len = 0; ++ sw_lro->cur_tsval = 0; ++ sw_lro->cur_tsecr = 0; ++ sw_lro->saw_ts = 0; ++ sw_lro->window = 0; ++ sw_lro->vlan_tag = 0; ++} ++ ++/** ++ * vxge_hw_sw_lro_session_close: Close LRO session ++ * @ring: Handle to the ring object used for receive ++ * @sw_lro: LRO Session. Please see struct vxge_hw_sw_lro{} ++ * ++ * Closes the LRO session ++ */ ++void ++vxge_hw_sw_lro_session_close( ++ struct __vxge_hw_ring *ring, ++ struct vxge_hw_sw_lro *sw_lro) ++{ ++ vxge_assert(ring != NULL); ++ ++ list_del(&sw_lro->lro_node); ++ ++ ring->active_sw_lro_count--; ++ ++ vxge_hw_sw_lro_reset_node(sw_lro); ++ ++ list_add(&sw_lro->lro_node, &ring->free_sw_lros); ++ ring->free_sw_lro_count++; ++} ++ ++/** ++ * xge_hw_sw_lro_next_session_get: get the next LRO session ++ * @ring: Handle to the ring object used for receive ++ * @sw_lro: Current LRO Session. If zero, the function will return the ++ * first LRO session ++ * ++ * Returns the next LRO session ++ */ ++struct vxge_hw_sw_lro * ++vxge_hw_sw_lro_next_session_get( ++ struct __vxge_hw_ring *ring, ++ struct vxge_hw_sw_lro *sw_lro) ++{ ++ struct vxge_hw_sw_lro *next_lro = NULL; ++ ++ vxge_assert(ring != NULL); ++ ++ if (sw_lro == NULL) { ++ if (!list_empty(&ring->active_sw_lros)) ++ next_lro = list_entry(ring->active_sw_lros.next, ++ struct vxge_hw_sw_lro, lro_node); ++ } else { ++ if (!list_empty(&sw_lro->lro_node)) ++ next_lro = list_entry(sw_lro->lro_node.next, ++ struct vxge_hw_sw_lro, lro_node); ++ } ++ ++ if (next_lro != NULL) { ++ next_lro->iph->tot_len = htons( ++ next_lro->total_length); ++ next_lro->iph->check = htons(0); ++ next_lro->iph->check = ip_fast_csum( ++ (u8 *)(next_lro->iph), ++ next_lro->iph->ihl); ++ } ++ ++ return next_lro; ++} ++ ++/** ++ * __vxge_hw_sw_lro_terminate - Terminate lro resources. ++ * @ring: Handle to the ring object used for receive ++ * ++ * Terminate lro resources. ++ */ ++enum vxge_hw_status ++__vxge_hw_sw_lro_terminate(struct __vxge_hw_ring *ring) ++{ ++ struct vxge_hw_sw_lro *lro_desc, *lro_desc_next; ++ ++ vxge_assert(ring != NULL); ++ ++ if (ring->active_sw_lro_count > 0) { ++ ++ list_for_each_entry_safe(lro_desc, lro_desc_next, ++ &ring->active_sw_lros, lro_node) { ++ ++ list_del(&lro_desc->lro_node); ++ vfree(lro_desc); ++ ring->active_sw_lro_count--; ++ } ++ } ++ ++ if (ring->free_sw_lro_count > 0) { ++ ++ list_for_each_entry_safe(lro_desc, lro_desc_next, ++ &ring->free_sw_lros, lro_node) { ++ list_del(&lro_desc->lro_node); ++ vfree(lro_desc); ++ ring->free_sw_lro_count--; ++ } ++ } ++ ++ return VXGE_HW_OK; ++} ++ ++/* ++ * __vxge_hw_sw_lro_init - Initiate lro resources. ++ * @ring: Handle to the ring object used for receive ++ * ++ * Initiate lro resources. ++ */ ++ ++enum vxge_hw_status ++__vxge_hw_sw_lro_init(struct __vxge_hw_ring *ring) ++{ ++ u32 i; ++ struct vxge_hw_sw_lro *lro_session; ++ ++ vxge_assert(ring != NULL); ++ ++ INIT_LIST_HEAD(&ring->active_sw_lros); ++ ++ ring->active_sw_lro_count = 0; ++ ++ INIT_LIST_HEAD(&ring->free_sw_lros); ++ ++ ring->free_sw_lro_count = 0; ++ ++ for (i = 0; i < ring->config->sw_lro_sessions; i++) { ++ lro_session = (struct vxge_hw_sw_lro *)\ ++ vmalloc(sizeof(struct vxge_hw_sw_lro)); ++ if (lro_session == NULL) { ++ __vxge_hw_sw_lro_terminate(ring); ++ ++ return VXGE_HW_ERR_OUT_OF_MEMORY; ++ } ++ ++ vxge_hw_sw_lro_reset_node(lro_session); ++ lro_session->lro_node.next = NULL; ++ lro_session->lro_node.prev = NULL; ++ list_add(&lro_session->lro_node, &ring->free_sw_lros); ++ ring->free_sw_lro_count++; ++ } ++ ++ return VXGE_HW_OK; ++} ++ ++/** ++ * __vxge_hw_sw_lro_reset - Reset lro resources. ++ * @ring: Handle to the ring object used for receive ++ * ++ * Reset lro resources. ++ */ ++enum vxge_hw_status ++__vxge_hw_sw_lro_reset(struct __vxge_hw_ring *ring) ++{ ++ struct vxge_hw_sw_lro *lro_desc; ++ ++ vxge_assert(ring != NULL); ++ ++ if (ring->active_sw_lro_count > 0) { ++ ++ list_for_each_entry(lro_desc, &ring->active_sw_lros, lro_node) { ++ ++ list_del(&lro_desc->lro_node); ++ ++ ring->active_sw_lro_count--; ++ vxge_hw_sw_lro_reset_node(lro_desc); ++ ++ list_add(&lro_desc->lro_node, &ring->free_sw_lros); ++ ring->free_sw_lro_count++; ++ } ++ } ++ ++ return VXGE_HW_OK; ++} ++ ++/** ++ * vxge_hw_sw_lro_rx_process: Process Rx Buffer ++ * @ring: Handle to the ring object used for receive ++ * @rxd_info: Please see struct vxge_hw_ring_rxd_info{} ++ * @eth_hdr: Ethernet header (start of frame buffer) ++ * @ip: Ip Header. Please see struct iphdr{} ++ * @tcp: Buffer to return pointer to struct tcphdr{} ++ * @sw_lro: Buffer to return pointer to struct vxge_hw_sw_lro{} ++ * ++ * Processes the rx buffer and either creates new lro session or ++ * appends to the existing lro session ++ */ ++enum vxge_hw_status ++vxge_hw_sw_lro_rx_process( ++ struct __vxge_hw_ring *ring, ++ struct vxge_hw_ring_rxd_info *rxd_info, ++ u8 *eth_hdr, ++ u32 *seglen, ++ struct vxge_hw_sw_lro **sw_lro) ++{ ++ enum vxge_hw_status status; ++ struct iphdr *ip = NULL; ++ struct tcphdr *tcp = NULL; ++ ++ vxge_assert(ring != NULL); ++ ++ if (__vxge_hw_sw_lro_capable(ring, eth_hdr, &ip, &tcp, rxd_info) != ++ VXGE_HW_OK) { ++ return VXGE_HW_INF_SW_LRO_UNCAPABLE; ++ } ++ ++ /* ++ * This function shall get matching LRO or else ++ * create one and return it ++ */ ++ status = __hw_get_lro_session(ring, rxd_info, eth_hdr, ++ tcp, ip, sw_lro); ++ ++ if (status == VXGE_HW_INF_SW_LRO_CONT) { ++ if (__hw_lro_under_optimal_thresh(ring, *sw_lro, tcp, ip) ++ == VXGE_HW_OK) { ++ (void) __hw_append_lro(*sw_lro, &tcp, ip, seglen); ++ ring->stats->lro_clubbed_frms_cnt++; ++ ++ if ((*sw_lro)->sg_num >= ring->config->sw_lro_sg_size) ++ status = VXGE_HW_INF_SW_LRO_FLUSH_SESSION; ++ ++ } else ++ status = VXGE_HW_INF_SW_LRO_FLUSH_BOTH; ++ } ++ ++ /* ++ * Since its time to flush, ++ * update ip header so that it can be sent up ++ */ ++ if (status == VXGE_HW_INF_SW_LRO_FLUSH_SESSION) { ++ vxge_hw_update_L3L4_header(ring, *sw_lro); ++ ring->stats->lro_flush_max_pkts++; ++ } else if (status == VXGE_HW_INF_SW_LRO_FLUSH_BOTH) { ++ vxge_hw_update_L3L4_header(ring, *sw_lro); ++ ring->stats->lro_sending_both++; ++ } ++ ++ ++ if (*sw_lro) { ++ if (rxd_info->is_vlan == 1) ++ (*sw_lro)->vlan_tag = rxd_info->vlan; ++ if ((*sw_lro)->sg_num > ring->stats->lro_max_pkts_aggr) ++ ring->stats->lro_max_pkts_aggr = (*sw_lro)->sg_num; ++ } ++ ++ return status; ++} +diff -r 158b6e53275e drivers/net/vxge/vxge-traffic.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/vxge/vxge-traffic.h Wed Aug 05 11:58:00 2009 +0100 +@@ -0,0 +1,2589 @@ ++/****************************************************************************** ++ * vxge-traffic.h: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O ++ * Virtualized Server Adapter. ++ * Copyright(c) 2002-2009 Neterion Inc. ++ ******************************************************************************/ ++#ifndef VXGE_TRAFFIC_H ++#define VXGE_TRAFFIC_H ++ ++#include ++#include ++ ++#include "vxge-reg.h" ++#include "vxge-version.h" ++#include "vxge-kcompat.h" ++ ++#define VXGE_HW_DTR_MAX_T_CODE 16 ++#define VXGE_HW_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL ++#define VXGE_HW_INTR_MASK_ALL 0xFFFFFFFFFFFFFFFFULL ++#define VXGE_HW_MAX_VIRTUAL_PATHS 17 ++ ++#define VXGE_HW_MAC_MAX_MAC_PORT_ID 3 ++ ++#define VXGE_HW_DEFAULT_32 0xffffffff ++/* frames sizes */ ++#define VXGE_HW_HEADER_802_2_SIZE 3 ++#define VXGE_HW_HEADER_SNAP_SIZE 5 ++#define VXGE_HW_HEADER_VLAN_SIZE 4 ++#define VXGE_HW_MAC_HEADER_MAX_SIZE \ ++ (ETH_HLEN + \ ++ VXGE_HW_HEADER_802_2_SIZE + \ ++ VXGE_HW_HEADER_VLAN_SIZE + \ ++ VXGE_HW_HEADER_SNAP_SIZE) ++ ++/* 32bit alignments */ ++#define VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN 2 ++#define VXGE_HW_HEADER_802_2_SNAP_ALIGN 2 ++#define VXGE_HW_HEADER_802_2_ALIGN 3 ++#define VXGE_HW_HEADER_SNAP_ALIGN 1 ++ ++#define VXGE_HW_L3_CKSUM_OK 0xFFFF ++#define VXGE_HW_L4_CKSUM_OK 0xFFFF ++ ++/* Forward declarations */ ++struct __vxge_hw_device; ++struct __vxge_hw_vpath_handle; ++struct vxge_hw_vp_config; ++struct __vxge_hw_virtualpath; ++struct __vxge_hw_channel; ++struct __vxge_hw_fifo; ++struct __vxge_hw_ring; ++struct vxge_hw_ring_attr; ++struct vxge_hw_mempool; ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++/*VXGE_HW_STATUS_H*/ ++#define VXGE_HW_EVENT_BASE 0 ++#define VXGE_LL_EVENT_BASE 100 ++ ++/** ++ * enum vxge_hw_event- Enumerates slow-path HW events. ++ * @VXGE_HW_EVENT_UNKNOWN: Unknown (and invalid) event. ++ * @VXGE_HW_EVENT_SERR: Serious vpath hardware error event. ++ * @VXGE_HW_EVENT_ECCERR: vpath ECC error event. ++ * @VXGE_HW_EVENT_VPATH_ERR: Error local to the respective vpath ++ * @VXGE_HW_EVENT_FIFO_ERR: FIFO Doorbell fifo error. ++ * @VXGE_HW_EVENT_SRPCIM_SERR: srpcim hardware error event. ++ * @VXGE_HW_EVENT_MRPCIM_SERR: mrpcim hardware error event. ++ * @VXGE_HW_EVENT_MRPCIM_ECCERR: mrpcim ecc error event. ++ * @VXGE_HW_EVENT_RESET_START: Privileged entity is starting device reset ++ * @VXGE_HW_EVENT_RESET_COMPLETE: Device reset has been completed ++ * @VXGE_HW_EVENT_SLOT_FREEZE: Slot-freeze event. Driver tries to distinguish ++ * slot-freeze from the rest critical events (e.g. ECC) when it is ++ * impossible to PIO read "through" the bus, i.e. when getting all-foxes. ++ * ++ * enum vxge_hw_event enumerates slow-path HW eventis. ++ * ++ * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_up_f{}, ++ * vxge_uld_link_down_f{}. ++ */ ++enum vxge_hw_event { ++ VXGE_HW_EVENT_UNKNOWN = 0, ++ /* HW events */ ++ VXGE_HW_EVENT_RESET_START = VXGE_HW_EVENT_BASE + 1, ++ VXGE_HW_EVENT_RESET_COMPLETE = VXGE_HW_EVENT_BASE + 2, ++ VXGE_HW_EVENT_LINK_DOWN = VXGE_HW_EVENT_BASE + 3, ++ VXGE_HW_EVENT_LINK_UP = VXGE_HW_EVENT_BASE + 4, ++ VXGE_HW_EVENT_ALARM_CLEARED = VXGE_HW_EVENT_BASE + 5, ++ VXGE_HW_EVENT_ECCERR = VXGE_HW_EVENT_BASE + 6, ++ VXGE_HW_EVENT_MRPCIM_ECCERR = VXGE_HW_EVENT_BASE + 7, ++ VXGE_HW_EVENT_FIFO_ERR = VXGE_HW_EVENT_BASE + 8, ++ VXGE_HW_EVENT_VPATH_ERR = VXGE_HW_EVENT_BASE + 9, ++ VXGE_HW_EVENT_CRITICAL_ERR = VXGE_HW_EVENT_BASE + 10, ++ VXGE_HW_EVENT_SERR = VXGE_HW_EVENT_BASE + 11, ++ VXGE_HW_EVENT_SRPCIM_SERR = VXGE_HW_EVENT_BASE + 12, ++ VXGE_HW_EVENT_MRPCIM_SERR = VXGE_HW_EVENT_BASE + 13, ++ VXGE_HW_EVENT_SLOT_FREEZE = VXGE_HW_EVENT_BASE + 14, ++ ++}; ++ ++/* ++ * struct vxge_hw_mempool_dma - Represents DMA objects passed to the ++ caller. ++ */ ++struct vxge_hw_mempool_dma { ++ dma_addr_t addr; ++ struct pci_dev *handle; ++ struct pci_dev *acc_handle; ++}; ++ ++/* ++ * vxge_hw_mempool_item_f - Mempool item alloc/free callback ++ * @mempoolh: Memory pool handle. ++ * @memblock: Address of memory block ++ * @memblock_index: Index of memory block ++ * @item: Item that gets allocated or freed. ++ * @index: Item's index in the memory pool. ++ * @is_last: True, if this item is the last one in the pool; false - otherwise. ++ * userdata: Per-pool user context. ++ * ++ * Memory pool allocation/deallocation callback. ++ */ ++ ++/* ++ * struct vxge_hw_mempool - Memory pool. ++ */ ++struct vxge_hw_mempool { ++ ++ void (*item_func_alloc)( ++ struct vxge_hw_mempool *mempoolh, ++ u32 memblock_index, ++ struct vxge_hw_mempool_dma *dma_object, ++ u32 index, ++ u32 is_last); ++ ++ void *userdata; ++ void **memblocks_arr; ++ void **memblocks_priv_arr; ++ struct vxge_hw_mempool_dma *memblocks_dma_arr; ++ struct __vxge_hw_device *devh; ++ u32 memblock_size; ++ u32 memblocks_max; ++ u32 memblocks_allocated; ++ u32 item_size; ++ u32 items_max; ++ u32 items_initial; ++ u32 items_current; ++ u32 items_per_memblock; ++ void **items_arr; ++ u32 items_priv_size; ++}; ++ ++#define VXGE_HW_MAX_INTR_PER_VP 4 ++#define VXGE_HW_VPATH_INTR_TX 0 ++#define VXGE_HW_VPATH_INTR_RX 1 ++#define VXGE_HW_VPATH_INTR_EINTA 2 ++#define VXGE_HW_VPATH_INTR_BMAP 3 ++ ++#define VXGE_HW_BLOCK_SIZE 4096 ++ ++/** ++ * struct vxge_hw_tim_intr_config - Titan Tim interrupt configuration. ++ * @intr_enable: Set to 1, if interrupt is enabled. ++ * @btimer_val: Boundary Timer Initialization value in units of 272 ns. ++ * @timer_ac_en: Timer Automatic Cancel. 1 : Automatic Canceling Enable: when ++ * asserted, other interrupt-generating entities will cancel the ++ * scheduled timer interrupt. ++ * @timer_ci_en: Timer Continuous Interrupt. 1 : Continuous Interrupting Enable: ++ * When asserted, an interrupt will be generated every time the ++ * boundary timer expires, even if no traffic has been transmitted ++ * on this interrupt. ++ * @timer_ri_en: Timer Consecutive (Re-) Interrupt 1 : Consecutive ++ * (Re-) Interrupt Enable: When asserted, an interrupt will be ++ * generated the next time the timer expires, even if no traffic has ++ * been transmitted on this interrupt. (This will only happen once ++ * each time that this value is written to the TIM.) This bit is ++ * cleared by H/W at the end of the current-timer-interval when ++ * the interrupt is triggered. ++ * @rtimer_val: Restriction Timer Initialization value in units of 272 ns. ++ * @util_sel: Utilization Selector. Selects which of the workload approximations ++ * to use (e.g. legacy Tx utilization, Tx/Rx utilization, host ++ * specified utilization etc.), selects one of ++ * the 17 host configured values. ++ * 0-Virtual Path 0 ++ * 1-Virtual Path 1 ++ * ... ++ * 16-Virtual Path 17 ++ * 17-Legacy Tx network utilization, provided by TPA ++ * 18-Legacy Rx network utilization, provided by FAU ++ * 19-Average of legacy Rx and Tx utilization calculated from link ++ * utilization values. ++ * 20-31-Invalid configurations ++ * 32-Host utilization for Virtual Path 0 ++ * 33-Host utilization for Virtual Path 1 ++ * ... ++ * 48-Host utilization for Virtual Path 17 ++ * 49-Legacy Tx network utilization, provided by TPA ++ * 50-Legacy Rx network utilization, provided by FAU ++ * 51-Average of legacy Rx and Tx utilization calculated from ++ * link utilization values. ++ * 52-63-Invalid configurations ++ * @ltimer_val: Latency Timer Initialization Value in units of 272 ns. ++ * @txd_cnt_en: TxD Return Event Count Enable. This configuration bit when set ++ * to 1 enables counting of TxD0 returns (signalled by PCC's), ++ * towards utilization event count values. ++ * @urange_a: Defines the upper limit (in percent) for this utilization range ++ * to be active. This range is considered active ++ * if 0 = UTIL = URNG_A ++ * and the UEC_A field (below) is non-zero. ++ * @uec_a: Utilization Event Count A. If this range is active, the adapter will ++ * wait until UEC_A events have occurred on the interrupt before ++ * generating an interrupt. ++ * @urange_b: Link utilization range B. ++ * @uec_b: Utilization Event Count B. ++ * @urange_c: Link utilization range C. ++ * @uec_c: Utilization Event Count C. ++ * @urange_d: Link utilization range D. ++ * @uec_d: Utilization Event Count D. ++ * Traffic Interrupt Controller Module interrupt configuration. ++ */ ++struct vxge_hw_tim_intr_config { ++ ++ u32 intr_enable; ++#define VXGE_HW_TIM_INTR_ENABLE 1 ++#define VXGE_HW_TIM_INTR_DISABLE 0 ++#define VXGE_HW_TIM_INTR_DEFAULT 0 ++ ++ u32 btimer_val; ++#define VXGE_HW_MIN_TIM_BTIMER_VAL 0 ++#define VXGE_HW_MAX_TIM_BTIMER_VAL 67108864 ++#define VXGE_HW_USE_FLASH_DEFAULT 0xffffffff ++ ++ u32 timer_ac_en; ++#define VXGE_HW_TIM_TIMER_AC_ENABLE 1 ++#define VXGE_HW_TIM_TIMER_AC_DISABLE 0 ++ ++ u32 timer_ci_en; ++#define VXGE_HW_TIM_TIMER_CI_ENABLE 1 ++#define VXGE_HW_TIM_TIMER_CI_DISABLE 0 ++ ++ u32 timer_ri_en; ++#define VXGE_HW_TIM_TIMER_RI_ENABLE 1 ++#define VXGE_HW_TIM_TIMER_RI_DISABLE 0 ++ ++ u32 rtimer_val; ++#define VXGE_HW_MIN_TIM_RTIMER_VAL 0 ++#define VXGE_HW_MAX_TIM_RTIMER_VAL 67108864 ++ ++ u32 util_sel; ++#define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL 17 ++#define VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL 18 ++#define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL 19 ++#define VXGE_HW_TIM_UTIL_SEL_PER_VPATH 63 ++ ++ u32 ltimer_val; ++#define VXGE_HW_MIN_TIM_LTIMER_VAL 0 ++#define VXGE_HW_MAX_TIM_LTIMER_VAL 67108864 ++ ++ /* Line utilization interrupts */ ++ u32 urange_a; ++#define VXGE_HW_MIN_TIM_URANGE_A 0 ++#define VXGE_HW_MAX_TIM_URANGE_A 100 ++ ++ u32 uec_a; ++#define VXGE_HW_MIN_TIM_UEC_A 0 ++#define VXGE_HW_MAX_TIM_UEC_A 65535 ++ ++ u32 urange_b; ++#define VXGE_HW_MIN_TIM_URANGE_B 0 ++#define VXGE_HW_MAX_TIM_URANGE_B 100 ++ ++ u32 uec_b; ++#define VXGE_HW_MIN_TIM_UEC_B 0 ++#define VXGE_HW_MAX_TIM_UEC_B 65535 ++ ++ u32 urange_c; ++#define VXGE_HW_MIN_TIM_URANGE_C 0 ++#define VXGE_HW_MAX_TIM_URANGE_C 100 ++ ++ u32 uec_c; ++#define VXGE_HW_MIN_TIM_UEC_C 0 ++#define VXGE_HW_MAX_TIM_UEC_C 65535 ++ ++ u32 uec_d; ++#define VXGE_HW_MIN_TIM_UEC_D 0 ++#define VXGE_HW_MAX_TIM_UEC_D 65535 ++}; ++ ++#define VXGE_HW_STATS_OP_READ 0 ++#define VXGE_HW_STATS_OP_CLEAR_STAT 1 ++#define VXGE_HW_STATS_OP_CLEAR_ALL_VPATH_STATS 2 ++#define VXGE_HW_STATS_OP_CLEAR_ALL_STATS_OF_LOC 2 ++#define VXGE_HW_STATS_OP_CLEAR_ALL_STATS 3 ++ ++#define VXGE_HW_STATS_LOC_AGGR 17 ++#define VXGE_HW_STATS_AGGRn_OFFSET 0x00720 ++ ++#define VXGE_HW_STATS_VPATH_TX_OFFSET 0x0 ++#define VXGE_HW_STATS_VPATH_RX_OFFSET 0x00090 ++ ++/** ++ * struct vxge_hw_xmac_aggr_stats - Per-Aggregator XMAC Statistics ++ * ++ * @tx_frms: Count of data frames transmitted on this Aggregator on all ++ * its Aggregation ports. Does not include LACPDUs or Marker PDUs. ++ * However, does include frames discarded by the Distribution ++ * function. ++ * @tx_data_octets: Count of data and padding octets of frames transmitted ++ * on this Aggregator on all its Aggregation ports. Does not include ++ * octets of LACPDUs or Marker PDUs. However, does include octets of ++ * frames discarded by the Distribution function. ++ * @tx_mcast_frms: Count of data frames transmitted (to a group destination ++ * address other than the broadcast address) on this Aggregator on ++ * all its Aggregation ports. Does not include LACPDUs or Marker ++ * PDUs. However, does include frames discarded by the Distribution ++ * function. ++ * @tx_bcast_frms: Count of broadcast data frames transmitted on this Aggregator ++ * on all its Aggregation ports. Does not include LACPDUs or Marker ++ * PDUs. However, does include frames discarded by the Distribution ++ * function. ++ * @tx_discarded_frms: Count of data frames to be transmitted on this Aggregator ++ * that are discarded by the Distribution function. This occurs when ++ * conversation are allocated to different ports and have to be ++ * flushed on old ports ++ * @tx_errored_frms: Count of data frames transmitted on this Aggregator that ++ * experience transmission errors on its Aggregation ports. ++ * @rx_frms: Count of data frames received on this Aggregator on all its ++ * Aggregation ports. Does not include LACPDUs or Marker PDUs. ++ * Also, does not include frames discarded by the Collection ++ * function. ++ * @rx_data_octets: Count of data and padding octets of frames received on this ++ * Aggregator on all its Aggregation ports. Does not include octets ++ * of LACPDUs or Marker PDUs. Also, does not include ++ * octets of frames ++ * discarded by the Collection function. ++ * @rx_mcast_frms: Count of data frames received (from a group destination ++ * address other than the broadcast address) on this Aggregator on ++ * all its Aggregation ports. Does not include LACPDUs or Marker ++ * PDUs. Also, does not include frames discarded by the Collection ++ * function. ++ * @rx_bcast_frms: Count of broadcast data frames received on this Aggregator on ++ * all its Aggregation ports. Does not include LACPDUs or Marker ++ * PDUs. Also, does not include frames discarded by the Collection ++ * function. ++ * @rx_discarded_frms: Count of data frames received on this Aggregator that are ++ * discarded by the Collection function because the Collection ++ * function was disabled on the port which the frames are received. ++ * @rx_errored_frms: Count of data frames received on this Aggregator that are ++ * discarded by its Aggregation ports, or are discarded by the ++ * Collection function of the Aggregator, or that are discarded by ++ * the Aggregator due to detection of an illegal Slow Protocols PDU. ++ * @rx_unknown_slow_proto_frms: Count of data frames received on this Aggregator ++ * that are discarded by its Aggregation ports due to detection of ++ * an unknown Slow Protocols PDU. ++ * ++ * Per aggregator XMAC RX statistics. ++ */ ++struct vxge_hw_xmac_aggr_stats { ++/*0x000*/ u64 tx_frms; ++/*0x008*/ u64 tx_data_octets; ++/*0x010*/ u64 tx_mcast_frms; ++/*0x018*/ u64 tx_bcast_frms; ++/*0x020*/ u64 tx_discarded_frms; ++/*0x028*/ u64 tx_errored_frms; ++/*0x030*/ u64 rx_frms; ++/*0x038*/ u64 rx_data_octets; ++/*0x040*/ u64 rx_mcast_frms; ++/*0x048*/ u64 rx_bcast_frms; ++/*0x050*/ u64 rx_discarded_frms; ++/*0x058*/ u64 rx_errored_frms; ++/*0x060*/ u64 rx_unknown_slow_proto_frms; ++} __attribute((packed)); ++ ++/** ++ * struct vxge_hw_xmac_port_stats - XMAC Port Statistics ++ * ++ * @tx_ttl_frms: Count of successfully transmitted MAC frames ++ * @tx_ttl_octets: Count of total octets of transmitted frames, not including ++ * framing characters (i.e. less framing bits). To determine the ++ * total octets of transmitted frames, including framing characters, ++ * multiply PORTn_TX_TTL_FRMS by 8 and add it to this stat (unless ++ * otherwise configured, this stat only counts frames that have ++ * 8 bytes of preamble for each frame). This stat can be configured ++ * (see XMAC_STATS_GLOBAL_CFG.TTL_FRMS_HANDLING) to count everything ++ * including the preamble octets. ++ * @tx_data_octets: Count of data and padding octets of successfully transmitted ++ * frames. ++ * @tx_mcast_frms: Count of successfully transmitted frames to a group address ++ * other than the broadcast address. ++ * @tx_bcast_frms: Count of successfully transmitted frames to the broadcast ++ * group address. ++ * @tx_ucast_frms: Count of transmitted frames containing a unicast address. ++ * Includes discarded frames that are not sent to the network. ++ * @tx_tagged_frms: Count of transmitted frames containing a VLAN tag. ++ * @tx_vld_ip: Count of transmitted IP datagrams that are passed to the network. ++ * @tx_vld_ip_octets: Count of total octets of transmitted IP datagrams that ++ * are passed to the network. ++ * @tx_icmp: Count of transmitted ICMP messages. Includes messages not sent ++ * due to problems within ICMP. ++ * @tx_tcp: Count of transmitted TCP segments. Does not include segments ++ * containing retransmitted octets. ++ * @tx_rst_tcp: Count of transmitted TCP segments containing the RST flag. ++ * @tx_udp: Count of transmitted UDP datagrams. ++ * @tx_parse_error: Increments when the TPA is unable to parse a packet. This ++ * generally occurs when a packet is corrupt somehow, including ++ * packets that have IP version mismatches, invalid Layer 2 control ++ * fields, etc. L3/L4 checksums are not offloaded, but the packet ++ * is still be transmitted. ++ * @tx_unknown_protocol: Increments when the TPA encounters an unknown ++ * protocol, such as a new IPv6 extension header, or an unsupported ++ * Routing Type. The packet still has a checksum calculated but it ++ * may be incorrect. ++ * @tx_pause_ctrl_frms: Count of MAC PAUSE control frames that are transmitted. ++ * Since, the only control frames supported by this device are ++ * PAUSE frames, this register is a count of all transmitted MAC ++ * control frames. ++ * @tx_marker_pdu_frms: Count of Marker PDUs transmitted ++ * on this Aggregation port. ++ * @tx_lacpdu_frms: Count of LACPDUs transmitted on this Aggregation port. ++ * @tx_drop_ip: Count of transmitted IP datagrams that could not be passed to ++ * the network. Increments because of: ++ * 1) An internal processing error ++ * (such as an uncorrectable ECC error). 2) A frame parsing error ++ * during IP checksum calculation. ++ * @tx_marker_resp_pdu_frms: Count of Marker Response PDUs transmitted on this ++ * Aggregation port. ++ * @tx_xgmii_char2_match: Maintains a count of the number of transmitted XGMII ++ * characters that match a pattern that is programmable through ++ * register XMAC_STATS_TX_XGMII_CHAR_PORTn. By default, the pattern ++ * is set to /T/ (i.e. the terminate character), thus the statistic ++ * tracks the number of transmitted Terminate characters. ++ * @tx_xgmii_char1_match: Maintains a count of the number of transmitted XGMII ++ * characters that match a pattern that is programmable through ++ * register XMAC_STATS_TX_XGMII_CHAR_PORTn. By default, the pattern ++ * is set to /S/ (i.e. the start character), ++ * thus the statistic tracks ++ * the number of transmitted Start characters. ++ * @tx_xgmii_column2_match: Maintains a count of the number of transmitted XGMII ++ * columns that match a pattern that is programmable through register ++ * XMAC_STATS_TX_XGMII_COLUMN2_PORTn. By default, the pattern is set ++ * to 4 x /E/ (i.e. a column containing all error characters), thus ++ * the statistic tracks the number of Error columns transmitted at ++ * any time. If XMAC_STATS_TX_XGMII_BEHAV_COLUMN2_PORTn.NEAR_COL1 is ++ * set to 1, then this stat increments when COLUMN2 is found within ++ * 'n' clocks after COLUMN1. Here, 'n' is defined by ++ * XMAC_STATS_TX_XGMII_BEHAV_COLUMN2_PORTn.NUM_COL (if 'n' is set ++ * to 0, then it means to search anywhere for COLUMN2). ++ * @tx_xgmii_column1_match: Maintains a count of the number of transmitted XGMII ++ * columns that match a pattern that is programmable through register ++ * XMAC_STATS_TX_XGMII_COLUMN1_PORTn. By default, the pattern is set ++ * to 4 x /I/ (i.e. a column containing all idle characters), ++ * thus the statistic tracks the number of transmitted Idle columns. ++ * @tx_any_err_frms: Count of transmitted frames containing any error that ++ * prevents them from being passed to the network. Increments if ++ * there is an ECC while reading the frame out of the transmit ++ * buffer. Also increments if the transmit protocol assist (TPA) ++ * block determines that the frame should not be sent. ++ * @tx_drop_frms: Count of frames that could not be sent for no other reason ++ * than internal MAC processing. Increments once whenever the ++ * transmit buffer is flushed (due to an ECC error on a memory ++ * descriptor). ++ * @rx_ttl_frms: Count of total received MAC frames, including frames received ++ * with frame-too-long, FCS, or length errors. This stat can be ++ * configured (see XMAC_STATS_GLOBAL_CFG.TTL_FRMS_HANDLING) to count ++ * everything, even "frames" as small one byte of preamble. ++ * @rx_vld_frms: Count of successfully received MAC frames. Does not include ++ * frames received with frame-too-long, FCS, or length errors. ++ * @rx_offload_frms: Count of offloaded received frames that are passed to ++ * the host. ++ * @rx_ttl_octets: Count of total octets of received frames, not including ++ * framing characters (i.e. less framing bits). To determine the ++ * total octets of received frames, including framing characters, ++ * multiply PORTn_RX_TTL_FRMS by 8 and add it to this stat (unless ++ * otherwise configured, this stat only counts frames that have 8 ++ * bytes of preamble for each frame). This stat can be configured ++ * (see XMAC_STATS_GLOBAL_CFG.TTL_FRMS_HANDLING) to count everything, ++ * even the preamble octets of "frames" as small one byte of preamble ++ * @rx_data_octets: Count of data and padding octets of successfully received ++ * frames. Does not include frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_offload_octets: Count of total octets, not including framing ++ * characters, of offloaded received frames that are passed ++ * to the host. ++ * @rx_vld_mcast_frms: Count of successfully received MAC frames containing a ++ * nonbroadcast group address. Does not include frames received ++ * with frame-too-long, FCS, or length errors. ++ * @rx_vld_bcast_frms: Count of successfully received MAC frames containing ++ * the broadcast group address. Does not include frames received ++ * with frame-too-long, FCS, or length errors. ++ * @rx_accepted_ucast_frms: Count of successfully received frames containing ++ * a unicast address. Only includes frames that are passed to ++ * the system. ++ * @rx_accepted_nucast_frms: Count of successfully received frames containing ++ * a non-unicast (broadcast or multicast) address. Only includes ++ * frames that are passed to the system. Could include, for instance, ++ * non-unicast frames that contain FCS errors if the MAC_ERROR_CFG ++ * register is set to pass FCS-errored frames to the host. ++ * @rx_tagged_frms: Count of received frames containing a VLAN tag. ++ * @rx_long_frms: Count of received frames that are longer than RX_MAX_PYLD_LEN ++ * + 18 bytes (+ 22 bytes if VLAN-tagged). ++ * @rx_usized_frms: Count of received frames of length (including FCS, but not ++ * framing bits) less than 64 octets, that are otherwise well-formed. ++ * In other words, counts runts. ++ * @rx_osized_frms: Count of received frames of length (including FCS, but not ++ * framing bits) more than 1518 octets, that are otherwise ++ * well-formed. Note: If register XMAC_STATS_GLOBAL_CFG.VLAN_HANDLING ++ * is set to 1, then "more than 1518 octets" becomes "more than 1518 ++ * (1522 if VLAN-tagged) octets". ++ * @rx_frag_frms: Count of received frames of length (including FCS, but not ++ * framing bits) less than 64 octets that had bad FCS. In other ++ * words, counts fragments. ++ * @rx_jabber_frms: Count of received frames of length (including FCS, but not ++ * framing bits) more than 1518 octets that had bad FCS. In other ++ * words, counts jabbers. Note: If register ++ * XMAC_STATS_GLOBAL_CFG.VLAN_HANDLING is set to 1, then "more than ++ * 1518 octets" becomes "more than 1518 (1522 if VLAN-tagged) ++ * octets". ++ * @rx_ttl_64_frms: Count of total received MAC frames with length (including ++ * FCS, but not framing bits) of exactly 64 octets. Includes frames ++ * received with frame-too-long, FCS, or length errors. ++ * @rx_ttl_65_127_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) of between 65 and 127 ++ * octets inclusive. Includes frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_ttl_128_255_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) of between 128 and 255 ++ * octets inclusive. Includes frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_ttl_256_511_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) of between 256 and 511 ++ * octets inclusive. Includes frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_ttl_512_1023_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) of between 512 and 1023 ++ * octets inclusive. Includes frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_ttl_1024_1518_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) of between 1024 and 1518 ++ * octets inclusive. Includes frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_ttl_1519_4095_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) of between 1519 and 4095 ++ * octets inclusive. Includes frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_ttl_4096_8191_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) of between 4096 and 8191 ++ * octets inclusive. Includes frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_ttl_8192_max_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) of between 8192 and ++ * RX_MAX_PYLD_LEN+18 octets inclusive. Includes frames received ++ * with frame-too-long, FCS, or length errors. ++ * @rx_ttl_gt_max_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) exceeding ++ * RX_MAX_PYLD_LEN+18 (+22 bytes if VLAN-tagged) octets inclusive. ++ * Includes frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_ip: Count of received IP datagrams. Includes errored IP datagrams. ++ * @rx_accepted_ip: Count of received IP datagrams that ++ * are passed to the system. ++ * @rx_ip_octets: Count of number of octets in received IP datagrams. Includes ++ * errored IP datagrams. ++ * @rx_err_ip: Count of received IP datagrams containing errors. For example, ++ * bad IP checksum. ++ * @rx_icmp: Count of received ICMP messages. Includes errored ICMP messages. ++ * @rx_tcp: Count of received TCP segments. Includes errored TCP segments. ++ * Note: This stat contains a count of all received TCP segments, ++ * regardless of whether or not they pertain to an established ++ * connection. ++ * @rx_udp: Count of received UDP datagrams. ++ * @rx_err_tcp: Count of received TCP segments containing errors. For example, ++ * bad TCP checksum. ++ * @rx_pause_count: Count of number of pause quanta that the MAC has been in ++ * the paused state. Recall, one pause quantum equates to 512 ++ * bit times. ++ * @rx_pause_ctrl_frms: Count of received MAC PAUSE control frames. ++ * @rx_unsup_ctrl_frms: Count of received MAC control frames that do not ++ * contain the PAUSE opcode. The sum of RX_PAUSE_CTRL_FRMS and ++ * this register is a count of all received MAC control frames. ++ * Note: This stat may be configured to count all layer 2 errors ++ * (i.e. length errors and FCS errors). ++ * @rx_fcs_err_frms: Count of received MAC frames that do not pass FCS. Does ++ * not include frames received with frame-too-long or ++ * frame-too-short error. ++ * @rx_in_rng_len_err_frms: Count of received frames with a length/type field ++ * value between 46 (42 for VLAN-tagged frames) and 1500 (also 1500 ++ * for VLAN-tagged frames), inclusive, that does not match the ++ * number of data octets (including pad) received. Also contains ++ * a count of received frames with a length/type field less than ++ * 46 (42 for VLAN-tagged frames) and the number of data octets ++ * (including pad) received is greater than 46 (42 for VLAN-tagged ++ * frames). ++ * @rx_out_rng_len_err_frms: Count of received frames with length/type field ++ * between 1501 and 1535 decimal, inclusive. ++ * @rx_drop_frms: Count of received frames that could not be passed to the host. ++ * See PORTn_RX_L2_MGMT_DISCARD, PORTn_RX_RPA_DISCARD, ++ * PORTn_RX_TRASH_DISCARD, PORTn_RX_RTS_DISCARD, PORTn_RX_RED_DISCARD ++ * for a list of reasons. Because the RMAC drops one frame at a time, ++ * this stat also indicates the number of drop events. ++ * @rx_discarded_frms: Count of received frames containing ++ * any error that prevents ++ * them from being passed to the system. See PORTn_RX_FCS_DISCARD, ++ * PORTn_RX_LEN_DISCARD, and PORTn_RX_SWITCH_DISCARD for a list of ++ * reasons. ++ * @rx_drop_ip: Count of received IP datagrams that could not be passed to the ++ * host. See PORTn_RX_DROP_FRMS for a list of reasons. ++ * @rx_drop_udp: Count of received UDP datagrams that are not delivered to the ++ * host. See PORTn_RX_DROP_FRMS for a list of reasons. ++ * @rx_marker_pdu_frms: Count of valid Marker PDUs received on this Aggregation ++ * port. ++ * @rx_lacpdu_frms: Count of valid LACPDUs received on this Aggregation port. ++ * @rx_unknown_pdu_frms: Count of received frames (on this Aggregation port) ++ * that carry the Slow Protocols EtherType, but contain an unknown ++ * PDU. Or frames that contain the Slow Protocols group MAC address, ++ * but do not carry the Slow Protocols EtherType. ++ * @rx_marker_resp_pdu_frms: Count of valid Marker Response PDUs received on ++ * this Aggregation port. ++ * @rx_fcs_discard: Count of received frames that are discarded because the ++ * FCS check failed. ++ * @rx_illegal_pdu_frms: Count of received frames (on this Aggregation port) ++ * that carry the Slow Protocols EtherType, but contain a badly ++ * formed PDU. Or frames that carry the Slow Protocols EtherType, ++ * but contain an illegal value of Protocol Subtype. ++ * @rx_switch_discard: Count of received frames that are discarded by the ++ * internal switch because they did not have an entry in the ++ * Filtering Database. This includes frames that had an invalid ++ * destination MAC address or VLAN ID. It also includes frames are ++ * discarded because they did not satisfy the length requirements ++ * of the target VPATH. ++ * @rx_len_discard: Count of received frames that are discarded because of an ++ * invalid frame length (includes fragments, oversized frames and ++ * mismatch between frame length and length/type field). This stat ++ * can be configured ++ * (see XMAC_STATS_GLOBAL_CFG.LEN_DISCARD_HANDLING). ++ * @rx_rpa_discard: Count of received frames that were discarded because the ++ * receive protocol assist (RPA) discovered and error in the frame ++ * or was unable to parse the frame. ++ * @rx_l2_mgmt_discard: Count of Layer 2 management frames (eg. pause frames, ++ * Link Aggregation Control Protocol (LACP) frames, etc.) that are ++ * discarded. ++ * @rx_rts_discard: Count of received frames that are discarded by the receive ++ * traffic steering (RTS) logic. Includes those frame discarded ++ * because the SSC response contradicted the switch table, because ++ * the SSC timed out, or because the target queue could not fit the ++ * frame. ++ * @rx_trash_discard: Count of received frames that are discarded because ++ * receive traffic steering (RTS) steered the frame to the trash ++ * queue. ++ * @rx_buff_full_discard: Count of received frames that are discarded because ++ * internal buffers are full. Includes frames discarded because the ++ * RTS logic is waiting for an SSC lookup that has no timeout bound. ++ * Also, includes frames that are dropped because the MAC2FAU buffer ++ * is nearly full -- this can happen if the external receive buffer ++ * is full and the receive path is backing up. ++ * @rx_red_discard: Count of received frames that are discarded because of RED ++ * (Random Early Discard). ++ * @rx_xgmii_ctrl_err_cnt: Maintains a count of unexpected or misplaced control ++ * characters occuring between times of normal data transmission ++ * (i.e. not included in RX_XGMII_DATA_ERR_CNT). This counter is ++ * incremented when either - ++ * 1) The Reconciliation Sublayer (RS) is expecting one control ++ * character and gets another (i.e. is expecting a Start ++ * character, but gets another control character). ++ * 2) Start control character is not in lane 0 ++ * Only increments the count by one for each XGMII column. ++ * @rx_xgmii_data_err_cnt: Maintains a count of unexpected control characters ++ * during normal data transmission. If the Reconciliation Sublayer ++ * (RS) receives a control character, other than a terminate control ++ * character, during receipt of data octets then this register is ++ * incremented. Also increments if the start frame delimiter is not ++ * found in the correct location. Only increments the count by one ++ * for each XGMII column. ++ * @rx_xgmii_char1_match: Maintains a count of the number of XGMII characters ++ * that match a pattern that is programmable through register ++ * XMAC_STATS_RX_XGMII_CHAR_PORTn. By default, the pattern is set ++ * to /E/ (i.e. the error character), thus the statistic tracks the ++ * number of Error characters received at any time. ++ * @rx_xgmii_err_sym: Count of the number of symbol errors in the received ++ * XGMII data (i.e. PHY indicates "Receive Error" on the XGMII). ++ * Only includes symbol errors that are observed between the XGMII ++ * Start Frame Delimiter and End Frame Delimiter, inclusive. And ++ * only increments the count by one for each frame. ++ * @rx_xgmii_column1_match: Maintains a count of the number of XGMII columns ++ * that match a pattern that is programmable through register ++ * XMAC_STATS_RX_XGMII_COLUMN1_PORTn. By default, the pattern is set ++ * to 4 x /E/ (i.e. a column containing all error characters), thus ++ * the statistic tracks the number of Error columns received at any ++ * time. ++ * @rx_xgmii_char2_match: Maintains a count of the number of XGMII characters ++ * that match a pattern that is programmable through register ++ * XMAC_STATS_RX_XGMII_CHAR_PORTn. By default, the pattern is set ++ * to /E/ (i.e. the error character), thus the statistic tracks the ++ * number of Error characters received at any time. ++ * @rx_local_fault: Maintains a count of the number of times that link ++ * transitioned from "up" to "down" due to a local fault. ++ * @rx_xgmii_column2_match: Maintains a count of the number of XGMII columns ++ * that match a pattern that is programmable through register ++ * XMAC_STATS_RX_XGMII_COLUMN2_PORTn. By default, the pattern is set ++ * to 4 x /E/ (i.e. a column containing all error characters), thus ++ * the statistic tracks the number of Error columns received at any ++ * time. If XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_PORTn.NEAR_COL1 is set ++ * to 1, then this stat increments when COLUMN2 is found within 'n' ++ * clocks after COLUMN1. Here, 'n' is defined by ++ * XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_PORTn.NUM_COL (if 'n' is set to ++ * 0, then it means to search anywhere for COLUMN2). ++ * @rx_jettison: Count of received frames that are jettisoned because internal ++ * buffers are full. ++ * @rx_remote_fault: Maintains a count of the number of times that link ++ * transitioned from "up" to "down" due to a remote fault. ++ * ++ * XMAC Port Statistics. ++ */ ++struct vxge_hw_xmac_port_stats { ++/*0x000*/ u64 tx_ttl_frms; ++/*0x008*/ u64 tx_ttl_octets; ++/*0x010*/ u64 tx_data_octets; ++/*0x018*/ u64 tx_mcast_frms; ++/*0x020*/ u64 tx_bcast_frms; ++/*0x028*/ u64 tx_ucast_frms; ++/*0x030*/ u64 tx_tagged_frms; ++/*0x038*/ u64 tx_vld_ip; ++/*0x040*/ u64 tx_vld_ip_octets; ++/*0x048*/ u64 tx_icmp; ++/*0x050*/ u64 tx_tcp; ++/*0x058*/ u64 tx_rst_tcp; ++/*0x060*/ u64 tx_udp; ++/*0x068*/ u32 tx_parse_error; ++/*0x06c*/ u32 tx_unknown_protocol; ++/*0x070*/ u64 tx_pause_ctrl_frms; ++/*0x078*/ u32 tx_marker_pdu_frms; ++/*0x07c*/ u32 tx_lacpdu_frms; ++/*0x080*/ u32 tx_drop_ip; ++/*0x084*/ u32 tx_marker_resp_pdu_frms; ++/*0x088*/ u32 tx_xgmii_char2_match; ++/*0x08c*/ u32 tx_xgmii_char1_match; ++/*0x090*/ u32 tx_xgmii_column2_match; ++/*0x094*/ u32 tx_xgmii_column1_match; ++/*0x098*/ u32 unused1; ++/*0x09c*/ u16 tx_any_err_frms; ++/*0x09e*/ u16 tx_drop_frms; ++/*0x0a0*/ u64 rx_ttl_frms; ++/*0x0a8*/ u64 rx_vld_frms; ++/*0x0b0*/ u64 rx_offload_frms; ++/*0x0b8*/ u64 rx_ttl_octets; ++/*0x0c0*/ u64 rx_data_octets; ++/*0x0c8*/ u64 rx_offload_octets; ++/*0x0d0*/ u64 rx_vld_mcast_frms; ++/*0x0d8*/ u64 rx_vld_bcast_frms; ++/*0x0e0*/ u64 rx_accepted_ucast_frms; ++/*0x0e8*/ u64 rx_accepted_nucast_frms; ++/*0x0f0*/ u64 rx_tagged_frms; ++/*0x0f8*/ u64 rx_long_frms; ++/*0x100*/ u64 rx_usized_frms; ++/*0x108*/ u64 rx_osized_frms; ++/*0x110*/ u64 rx_frag_frms; ++/*0x118*/ u64 rx_jabber_frms; ++/*0x120*/ u64 rx_ttl_64_frms; ++/*0x128*/ u64 rx_ttl_65_127_frms; ++/*0x130*/ u64 rx_ttl_128_255_frms; ++/*0x138*/ u64 rx_ttl_256_511_frms; ++/*0x140*/ u64 rx_ttl_512_1023_frms; ++/*0x148*/ u64 rx_ttl_1024_1518_frms; ++/*0x150*/ u64 rx_ttl_1519_4095_frms; ++/*0x158*/ u64 rx_ttl_4096_8191_frms; ++/*0x160*/ u64 rx_ttl_8192_max_frms; ++/*0x168*/ u64 rx_ttl_gt_max_frms; ++/*0x170*/ u64 rx_ip; ++/*0x178*/ u64 rx_accepted_ip; ++/*0x180*/ u64 rx_ip_octets; ++/*0x188*/ u64 rx_err_ip; ++/*0x190*/ u64 rx_icmp; ++/*0x198*/ u64 rx_tcp; ++/*0x1a0*/ u64 rx_udp; ++/*0x1a8*/ u64 rx_err_tcp; ++/*0x1b0*/ u64 rx_pause_count; ++/*0x1b8*/ u64 rx_pause_ctrl_frms; ++/*0x1c0*/ u64 rx_unsup_ctrl_frms; ++/*0x1c8*/ u64 rx_fcs_err_frms; ++/*0x1d0*/ u64 rx_in_rng_len_err_frms; ++/*0x1d8*/ u64 rx_out_rng_len_err_frms; ++/*0x1e0*/ u64 rx_drop_frms; ++/*0x1e8*/ u64 rx_discarded_frms; ++/*0x1f0*/ u64 rx_drop_ip; ++/*0x1f8*/ u64 rx_drop_udp; ++/*0x200*/ u32 rx_marker_pdu_frms; ++/*0x204*/ u32 rx_lacpdu_frms; ++/*0x208*/ u32 rx_unknown_pdu_frms; ++/*0x20c*/ u32 rx_marker_resp_pdu_frms; ++/*0x210*/ u32 rx_fcs_discard; ++/*0x214*/ u32 rx_illegal_pdu_frms; ++/*0x218*/ u32 rx_switch_discard; ++/*0x21c*/ u32 rx_len_discard; ++/*0x220*/ u32 rx_rpa_discard; ++/*0x224*/ u32 rx_l2_mgmt_discard; ++/*0x228*/ u32 rx_rts_discard; ++/*0x22c*/ u32 rx_trash_discard; ++/*0x230*/ u32 rx_buff_full_discard; ++/*0x234*/ u32 rx_red_discard; ++/*0x238*/ u32 rx_xgmii_ctrl_err_cnt; ++/*0x23c*/ u32 rx_xgmii_data_err_cnt; ++/*0x240*/ u32 rx_xgmii_char1_match; ++/*0x244*/ u32 rx_xgmii_err_sym; ++/*0x248*/ u32 rx_xgmii_column1_match; ++/*0x24c*/ u32 rx_xgmii_char2_match; ++/*0x250*/ u32 rx_local_fault; ++/*0x254*/ u32 rx_xgmii_column2_match; ++/*0x258*/ u32 rx_jettison; ++/*0x25c*/ u32 rx_remote_fault; ++} __attribute((packed)); ++ ++/** ++ * struct vxge_hw_xmac_vpath_tx_stats - XMAC Vpath Tx Statistics ++ * ++ * @tx_ttl_eth_frms: Count of successfully transmitted MAC frames. ++ * @tx_ttl_eth_octets: Count of total octets of transmitted frames, ++ * not including framing characters (i.e. less framing bits). ++ * To determine the total octets of transmitted frames, including ++ * framing characters, multiply TX_TTL_ETH_FRMS by 8 and add it to ++ * this stat (the device always prepends 8 bytes of preamble for ++ * each frame) ++ * @tx_data_octets: Count of data and padding octets of successfully transmitted ++ * frames. ++ * @tx_mcast_frms: Count of successfully transmitted frames to a group address ++ * other than the broadcast address. ++ * @tx_bcast_frms: Count of successfully transmitted frames to the broadcast ++ * group address. ++ * @tx_ucast_frms: Count of transmitted frames containing a unicast address. ++ * Includes discarded frames that are not sent to the network. ++ * @tx_tagged_frms: Count of transmitted frames containing a VLAN tag. ++ * @tx_vld_ip: Count of transmitted IP datagrams that are passed to the network. ++ * @tx_vld_ip_octets: Count of total octets of transmitted IP datagrams that ++ * are passed to the network. ++ * @tx_icmp: Count of transmitted ICMP messages. Includes messages not sent due ++ * to problems within ICMP. ++ * @tx_tcp: Count of transmitted TCP segments. Does not include segments ++ * containing retransmitted octets. ++ * @tx_rst_tcp: Count of transmitted TCP segments containing the RST flag. ++ * @tx_udp: Count of transmitted UDP datagrams. ++ * @tx_unknown_protocol: Increments when the TPA encounters an unknown protocol, ++ * such as a new IPv6 extension header, or an unsupported Routing ++ * Type. The packet still has a checksum calculated but it may be ++ * incorrect. ++ * @tx_lost_ip: Count of transmitted IP datagrams that could not be passed ++ * to the network. Increments because of: 1) An internal processing ++ * error (such as an uncorrectable ECC error). 2) A frame parsing ++ * error during IP checksum calculation. ++ * @tx_parse_error: Increments when the TPA is unable to parse a packet. This ++ * generally occurs when a packet is corrupt somehow, including ++ * packets that have IP version mismatches, invalid Layer 2 control ++ * fields, etc. L3/L4 checksums are not offloaded, but the packet ++ * is still be transmitted. ++ * @tx_tcp_offload: For frames belonging to offloaded sessions only, a count ++ * of transmitted TCP segments. Does not include segments containing ++ * retransmitted octets. ++ * @tx_retx_tcp_offload: For frames belonging to offloaded sessions only, the ++ * total number of segments retransmitted. Retransmitted segments ++ * that are sourced by the host are counted by the host. ++ * @tx_lost_ip_offload: For frames belonging to offloaded sessions only, a count ++ * of transmitted IP datagrams that could not be passed to the ++ * network. ++ * ++ * XMAC Vpath TX Statistics. ++ */ ++struct vxge_hw_xmac_vpath_tx_stats { ++ u64 tx_ttl_eth_frms; ++ u64 tx_ttl_eth_octets; ++ u64 tx_data_octets; ++ u64 tx_mcast_frms; ++ u64 tx_bcast_frms; ++ u64 tx_ucast_frms; ++ u64 tx_tagged_frms; ++ u64 tx_vld_ip; ++ u64 tx_vld_ip_octets; ++ u64 tx_icmp; ++ u64 tx_tcp; ++ u64 tx_rst_tcp; ++ u64 tx_udp; ++ u32 tx_unknown_protocol; ++ u32 tx_lost_ip; ++ u32 unused1; ++ u32 tx_parse_error; ++ u64 tx_tcp_offload; ++ u64 tx_retx_tcp_offload; ++ u64 tx_lost_ip_offload; ++} __attribute((packed)); ++ ++/** ++ * struct vxge_hw_xmac_vpath_rx_stats - XMAC Vpath RX Statistics ++ * ++ * @rx_ttl_eth_frms: Count of successfully received MAC frames. ++ * @rx_vld_frms: Count of successfully received MAC frames. Does not include ++ * frames received with frame-too-long, FCS, or length errors. ++ * @rx_offload_frms: Count of offloaded received frames that are passed to ++ * the host. ++ * @rx_ttl_eth_octets: Count of total octets of received frames, not including ++ * framing characters (i.e. less framing bits). Only counts octets ++ * of frames that are at least 14 bytes (18 bytes for VLAN-tagged) ++ * before FCS. To determine the total octets of received frames, ++ * including framing characters, multiply RX_TTL_ETH_FRMS by 8 and ++ * add it to this stat (the stat RX_TTL_ETH_FRMS only counts frames ++ * that have the required 8 bytes of preamble). ++ * @rx_data_octets: Count of data and padding octets of successfully received ++ * frames. Does not include frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_offload_octets: Count of total octets, not including framing characters, ++ * of offloaded received frames that are passed to the host. ++ * @rx_vld_mcast_frms: Count of successfully received MAC frames containing a ++ * nonbroadcast group address. Does not include frames received with ++ * frame-too-long, FCS, or length errors. ++ * @rx_vld_bcast_frms: Count of successfully received MAC frames containing the ++ * broadcast group address. Does not include frames received with ++ * frame-too-long, FCS, or length errors. ++ * @rx_accepted_ucast_frms: Count of successfully received frames containing ++ * a unicast address. Only includes frames that are passed to the ++ * system. ++ * @rx_accepted_nucast_frms: Count of successfully received frames containing ++ * a non-unicast (broadcast or multicast) address. Only includes ++ * frames that are passed to the system. Could include, for instance, ++ * non-unicast frames that contain FCS errors if the MAC_ERROR_CFG ++ * register is set to pass FCS-errored frames to the host. ++ * @rx_tagged_frms: Count of received frames containing a VLAN tag. ++ * @rx_long_frms: Count of received frames that are longer than RX_MAX_PYLD_LEN ++ * + 18 bytes (+ 22 bytes if VLAN-tagged). ++ * @rx_usized_frms: Count of received frames of length (including FCS, but not ++ * framing bits) less than 64 octets, that are otherwise well-formed. ++ * In other words, counts runts. ++ * @rx_osized_frms: Count of received frames of length (including FCS, but not ++ * framing bits) more than 1518 octets, that are otherwise ++ * well-formed. ++ * @rx_frag_frms: Count of received frames of length (including FCS, but not ++ * framing bits) less than 64 octets that had bad FCS. ++ * In other words, counts fragments. ++ * @rx_jabber_frms: Count of received frames of length (including FCS, but not ++ * framing bits) more than 1518 octets that had bad FCS. In other ++ * words, counts jabbers. ++ * @rx_ttl_64_frms: Count of total received MAC frames with length (including ++ * FCS, but not framing bits) of exactly 64 octets. Includes frames ++ * received with frame-too-long, FCS, or length errors. ++ * @rx_ttl_65_127_frms: Count of total received MAC frames ++ * with length (including ++ * FCS, but not framing bits) of between 65 and 127 octets inclusive. ++ * Includes frames received with frame-too-long, FCS, ++ * or length errors. ++ * @rx_ttl_128_255_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) ++ * of between 128 and 255 octets ++ * inclusive. Includes frames received with frame-too-long, FCS, ++ * or length errors. ++ * @rx_ttl_256_511_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) ++ * of between 256 and 511 octets ++ * inclusive. Includes frames received with frame-too-long, FCS, or ++ * length errors. ++ * @rx_ttl_512_1023_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) of between 512 and 1023 ++ * octets inclusive. Includes frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_ttl_1024_1518_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) of between 1024 and 1518 ++ * octets inclusive. Includes frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_ttl_1519_4095_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) of between 1519 and 4095 ++ * octets inclusive. Includes frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_ttl_4096_8191_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) of between 4096 and 8191 ++ * octets inclusive. Includes frames received with frame-too-long, ++ * FCS, or length errors. ++ * @rx_ttl_8192_max_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) of between 8192 and ++ * RX_MAX_PYLD_LEN+18 octets inclusive. Includes frames received ++ * with frame-too-long, FCS, or length errors. ++ * @rx_ttl_gt_max_frms: Count of total received MAC frames with length ++ * (including FCS, but not framing bits) exceeding RX_MAX_PYLD_LEN+18 ++ * (+22 bytes if VLAN-tagged) octets inclusive. Includes frames ++ * received with frame-too-long, FCS, or length errors. ++ * @rx_ip: Count of received IP datagrams. Includes errored IP datagrams. ++ * @rx_accepted_ip: Count of received IP datagrams that ++ * are passed to the system. ++ * @rx_ip_octets: Count of number of octets in received IP datagrams. ++ * Includes errored IP datagrams. ++ * @rx_err_ip: Count of received IP datagrams containing errors. For example, ++ * bad IP checksum. ++ * @rx_icmp: Count of received ICMP messages. Includes errored ICMP messages. ++ * @rx_tcp: Count of received TCP segments. Includes errored TCP segments. ++ * Note: This stat contains a count of all received TCP segments, ++ * regardless of whether or not they pertain to an established ++ * connection. ++ * @rx_udp: Count of received UDP datagrams. ++ * @rx_err_tcp: Count of received TCP segments containing errors. For example, ++ * bad TCP checksum. ++ * @rx_lost_frms: Count of received frames that could not be passed to the host. ++ * See RX_QUEUE_FULL_DISCARD and RX_RED_DISCARD ++ * for a list of reasons. ++ * @rx_lost_ip: Count of received IP datagrams that could not be passed to ++ * the host. See RX_LOST_FRMS for a list of reasons. ++ * @rx_lost_ip_offload: For frames belonging to offloaded sessions only, a count ++ * of received IP datagrams that could not be passed to the host. ++ * See RX_LOST_FRMS for a list of reasons. ++ * @rx_various_discard: Count of received frames that are discarded because ++ * the target receive queue is full. ++ * @rx_sleep_discard: Count of received frames that are discarded because the ++ * target VPATH is asleep (a Wake-on-LAN magic packet can be used ++ * to awaken the VPATH). ++ * @rx_red_discard: Count of received frames that are discarded because of RED ++ * (Random Early Discard). ++ * @rx_queue_full_discard: Count of received frames that are discarded because ++ * the target receive queue is full. ++ * @rx_mpa_ok_frms: Count of received frames that pass the MPA checks. ++ * ++ * XMAC Vpath RX Statistics. ++ */ ++struct vxge_hw_xmac_vpath_rx_stats { ++ u64 rx_ttl_eth_frms; ++ u64 rx_vld_frms; ++ u64 rx_offload_frms; ++ u64 rx_ttl_eth_octets; ++ u64 rx_data_octets; ++ u64 rx_offload_octets; ++ u64 rx_vld_mcast_frms; ++ u64 rx_vld_bcast_frms; ++ u64 rx_accepted_ucast_frms; ++ u64 rx_accepted_nucast_frms; ++ u64 rx_tagged_frms; ++ u64 rx_long_frms; ++ u64 rx_usized_frms; ++ u64 rx_osized_frms; ++ u64 rx_frag_frms; ++ u64 rx_jabber_frms; ++ u64 rx_ttl_64_frms; ++ u64 rx_ttl_65_127_frms; ++ u64 rx_ttl_128_255_frms; ++ u64 rx_ttl_256_511_frms; ++ u64 rx_ttl_512_1023_frms; ++ u64 rx_ttl_1024_1518_frms; ++ u64 rx_ttl_1519_4095_frms; ++ u64 rx_ttl_4096_8191_frms; ++ u64 rx_ttl_8192_max_frms; ++ u64 rx_ttl_gt_max_frms; ++ u64 rx_ip; ++ u64 rx_accepted_ip; ++ u64 rx_ip_octets; ++ u64 rx_err_ip; ++ u64 rx_icmp; ++ u64 rx_tcp; ++ u64 rx_udp; ++ u64 rx_err_tcp; ++ u64 rx_lost_frms; ++ u64 rx_lost_ip; ++ u64 rx_lost_ip_offload; ++ u16 rx_various_discard; ++ u16 rx_sleep_discard; ++ u16 rx_red_discard; ++ u16 rx_queue_full_discard; ++ u64 rx_mpa_ok_frms; ++} __attribute((packed)); ++ ++/** ++ * struct vxge_hw_xmac_stats - XMAC Statistics ++ * ++ * @aggr_stats: Statistics on aggregate port(port 0, port 1) ++ * @port_stats: Staticstics on ports(wire 0, wire 1, lag) ++ * @vpath_tx_stats: Per vpath XMAC TX stats ++ * @vpath_rx_stats: Per vpath XMAC RX stats ++ * ++ * XMAC Statistics. ++ */ ++struct vxge_hw_xmac_stats { ++ struct vxge_hw_xmac_aggr_stats ++ aggr_stats[VXGE_HW_MAC_MAX_MAC_PORT_ID]; ++ struct vxge_hw_xmac_port_stats ++ port_stats[VXGE_HW_MAC_MAX_MAC_PORT_ID]; ++ struct vxge_hw_xmac_vpath_tx_stats ++ vpath_tx_stats[VXGE_HW_MAX_VIRTUAL_PATHS]; ++ struct vxge_hw_xmac_vpath_rx_stats ++ vpath_rx_stats[VXGE_HW_MAX_VIRTUAL_PATHS]; ++}; ++ ++/** ++ * struct vxge_hw_vp_xmac_stats - XMAC Statistics ++ * ++ * @vpath_tx_stats: Per vpath XMAC TX stats ++ * @vpath_rx_stats: Per vpath XMAC RX stats ++ * ++ * XMAC Statistics per vpath, to be used only by the ++ * privilege adapter ++ */ ++struct vxge_hw_vp_xmac_stats { ++ struct vxge_hw_xmac_vpath_tx_stats tx_stats; ++ struct vxge_hw_xmac_vpath_rx_stats rx_stats; ++}; ++ ++/** ++ * struct vxge_hw_vpath_stats_hw_info - Titan vpath hardware statistics. ++ * @ini_num_mwr_sent: The number of PCI memory writes initiated by the PIC block ++ * for the given VPATH ++ * @ini_num_mrd_sent: The number of PCI memory reads initiated by the PIC block ++ * @ini_num_cpl_rcvd: The number of PCI read completions received by the ++ * PIC block ++ * @ini_num_mwr_byte_sent: The number of PCI memory write bytes sent by the PIC ++ * block to the host ++ * @ini_num_cpl_byte_rcvd: The number of PCI read completion bytes received by ++ * the PIC block ++ * @wrcrdtarb_xoff: TBD ++ * @rdcrdtarb_xoff: TBD ++ * @vpath_genstats_count0: TBD ++ * @vpath_genstats_count1: TBD ++ * @vpath_genstats_count2: TBD ++ * @vpath_genstats_count3: TBD ++ * @vpath_genstats_count4: TBD ++ * @vpath_gennstats_count5: TBD ++ * @tx_stats: Transmit stats ++ * @rx_stats: Receive stats ++ * @prog_event_vnum1: Programmable statistic. Increments when internal logic ++ * detects a certain event. See register ++ * XMAC_STATS_CFG.EVENT_VNUM1_CFG for more information. ++ * @prog_event_vnum0: Programmable statistic. Increments when internal logic ++ * detects a certain event. See register ++ * XMAC_STATS_CFG.EVENT_VNUM0_CFG for more information. ++ * @prog_event_vnum3: Programmable statistic. Increments when internal logic ++ * detects a certain event. See register ++ * XMAC_STATS_CFG.EVENT_VNUM3_CFG for more information. ++ * @prog_event_vnum2: Programmable statistic. Increments when internal logic ++ * detects a certain event. See register ++ * XMAC_STATS_CFG.EVENT_VNUM2_CFG for more information. ++ * @rx_multi_cast_frame_discard: TBD ++ * @rx_frm_transferred: TBD ++ * @rxd_returned: TBD ++ * @rx_mpa_len_fail_frms: Count of received frames ++ * that fail the MPA length check ++ * @rx_mpa_mrk_fail_frms: Count of received frames ++ * that fail the MPA marker check ++ * @rx_mpa_crc_fail_frms: Count of received frames that fail the MPA CRC check ++ * @rx_permitted_frms: Count of frames that pass through the FAU and on to the ++ * frame buffer (and subsequently to the host). ++ * @rx_vp_reset_discarded_frms: Count of receive frames that are discarded ++ * because the VPATH is in reset ++ * @rx_wol_frms: Count of received "magic packet" frames. Stat increments ++ * whenever the received frame matches the VPATH's Wake-on-LAN ++ * signature(s) CRC. ++ * @tx_vp_reset_discarded_frms: Count of transmit frames that are discarded ++ * because the VPATH is in reset. Includes frames that are discarded ++ * because the current VPIN does not match that VPIN of the frame ++ * ++ * Titan vpath hardware statistics. ++ */ ++struct vxge_hw_vpath_stats_hw_info { ++/*0x000*/ u32 ini_num_mwr_sent; ++/*0x004*/ u32 unused1; ++/*0x008*/ u32 ini_num_mrd_sent; ++/*0x00c*/ u32 unused2; ++/*0x010*/ u32 ini_num_cpl_rcvd; ++/*0x014*/ u32 unused3; ++/*0x018*/ u64 ini_num_mwr_byte_sent; ++/*0x020*/ u64 ini_num_cpl_byte_rcvd; ++/*0x028*/ u32 wrcrdtarb_xoff; ++/*0x02c*/ u32 unused4; ++/*0x030*/ u32 rdcrdtarb_xoff; ++/*0x034*/ u32 unused5; ++/*0x038*/ u32 vpath_genstats_count0; ++/*0x03c*/ u32 vpath_genstats_count1; ++/*0x040*/ u32 vpath_genstats_count2; ++/*0x044*/ u32 vpath_genstats_count3; ++/*0x048*/ u32 vpath_genstats_count4; ++/*0x04c*/ u32 unused6; ++/*0x050*/ u32 vpath_genstats_count5; ++/*0x054*/ u32 unused7; ++/*0x058*/ struct vxge_hw_xmac_vpath_tx_stats tx_stats; ++/*0x0e8*/ struct vxge_hw_xmac_vpath_rx_stats rx_stats; ++/*0x220*/ u64 unused9; ++/*0x228*/ u32 prog_event_vnum1; ++/*0x22c*/ u32 prog_event_vnum0; ++/*0x230*/ u32 prog_event_vnum3; ++/*0x234*/ u32 prog_event_vnum2; ++/*0x238*/ u16 rx_multi_cast_frame_discard; ++/*0x23a*/ u8 unused10[6]; ++/*0x240*/ u32 rx_frm_transferred; ++/*0x244*/ u32 unused11; ++/*0x248*/ u16 rxd_returned; ++/*0x24a*/ u8 unused12[6]; ++/*0x252*/ u16 rx_mpa_len_fail_frms; ++/*0x254*/ u16 rx_mpa_mrk_fail_frms; ++/*0x256*/ u16 rx_mpa_crc_fail_frms; ++/*0x258*/ u16 rx_permitted_frms; ++/*0x25c*/ u64 rx_vp_reset_discarded_frms; ++/*0x25e*/ u64 rx_wol_frms; ++/*0x260*/ u64 tx_vp_reset_discarded_frms; ++} __attribute((packed)); ++ ++ ++/** ++ * struct vxge_hw_device_stats_mrpcim_info - Titan mrpcim hardware statistics. ++ * @pic.ini_rd_drop 0x0000 4 Number of DMA reads initiated ++ * by the adapter that were discarded because the VPATH is out of service ++ * @pic.ini_wr_drop 0x0004 4 Number of DMA writes initiated by the ++ * adapter that were discared because the VPATH is out of service ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane0] 0x0008 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane1] 0x0010 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane2] 0x0018 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane3] 0x0020 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane4] 0x0028 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane5] 0x0030 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane6] 0x0038 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane7] 0x0040 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane8] 0x0048 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane9] 0x0050 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane10] 0x0058 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane11] 0x0060 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane12] 0x0068 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane13] 0x0070 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane14] 0x0078 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane15] 0x0080 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_ph_crdt_depleted[vplane16] 0x0088 4 Number of times ++ * the posted header credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane0] 0x0090 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane1] 0x0098 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane2] 0x00a0 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane3] 0x00a8 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane4] 0x00b0 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane5] 0x00b8 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane6] 0x00c0 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane7] 0x00c8 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane8] 0x00d0 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane9] 0x00d8 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane10] 0x00e0 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane11] 0x00e8 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane12] 0x00f0 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane13] 0x00f8 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane14] 0x0100 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane15] 0x0108 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.wrcrdtarb_pd_crdt_depleted[vplane16] 0x0110 4 Number of times ++ * the posted data credits for upstream PCI writes were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane0] 0x0118 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane1] 0x0120 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane2] 0x0128 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane3] 0x0130 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane4] 0x0138 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane5] 0x0140 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane6] 0x0148 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane7] 0x0150 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane8] 0x0158 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane9] 0x0160 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane10] 0x0168 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane11] 0x0170 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane12] 0x0178 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane13] 0x0180 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane14] 0x0188 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane15] 0x0190 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.rdcrdtarb_nph_crdt_depleted[vplane16] 0x0198 4 Number of times ++ * the non-posted header credits for upstream PCI reads were depleted ++ * @pic.ini_rd_vpin_drop 0x01a0 4 Number of DMA reads initiated by ++ * the adapter that were discarded because the VPATH instance number does ++ * not match ++ * @pic.ini_wr_vpin_drop 0x01a4 4 Number of DMA writes initiated ++ * by the adapter that were discarded because the VPATH instance number ++ * does not match ++ * @pic.genstats_count0 0x01a8 4 Configurable statistic #1. Refer ++ * to the GENSTATS0_CFG for information on configuring this statistic ++ * @pic.genstats_count1 0x01ac 4 Configurable statistic #2. Refer ++ * to the GENSTATS1_CFG for information on configuring this statistic ++ * @pic.genstats_count2 0x01b0 4 Configurable statistic #3. Refer ++ * to the GENSTATS2_CFG for information on configuring this statistic ++ * @pic.genstats_count3 0x01b4 4 Configurable statistic #4. Refer ++ * to the GENSTATS3_CFG for information on configuring this statistic ++ * @pic.genstats_count4 0x01b8 4 Configurable statistic #5. Refer ++ * to the GENSTATS4_CFG for information on configuring this statistic ++ * @pic.genstats_count5 0x01c0 4 Configurable statistic #6. Refer ++ * to the GENSTATS5_CFG for information on configuring this statistic ++ * @pci.rstdrop_cpl 0x01c8 4 ++ * @pci.rstdrop_msg 0x01cc 4 ++ * @pci.rstdrop_client1 0x01d0 4 ++ * @pci.rstdrop_client0 0x01d4 4 ++ * @pci.rstdrop_client2 0x01d8 4 ++ * @pci.depl_cplh[vplane0] 0x01e2 2 Number of times completion ++ * header credits were depleted ++ * @pci.depl_nph[vplane0] 0x01e4 2 Number of times non posted ++ * header credits were depleted ++ * @pci.depl_ph[vplane0] 0x01e6 2 Number of times the posted ++ * header credits were depleted ++ * @pci.depl_cplh[vplane1] 0x01ea 2 ++ * @pci.depl_nph[vplane1] 0x01ec 2 ++ * @pci.depl_ph[vplane1] 0x01ee 2 ++ * @pci.depl_cplh[vplane2] 0x01f2 2 ++ * @pci.depl_nph[vplane2] 0x01f4 2 ++ * @pci.depl_ph[vplane2] 0x01f6 2 ++ * @pci.depl_cplh[vplane3] 0x01fa 2 ++ * @pci.depl_nph[vplane3] 0x01fc 2 ++ * @pci.depl_ph[vplane3] 0x01fe 2 ++ * @pci.depl_cplh[vplane4] 0x0202 2 ++ * @pci.depl_nph[vplane4] 0x0204 2 ++ * @pci.depl_ph[vplane4] 0x0206 2 ++ * @pci.depl_cplh[vplane5] 0x020a 2 ++ * @pci.depl_nph[vplane5] 0x020c 2 ++ * @pci.depl_ph[vplane5] 0x020e 2 ++ * @pci.depl_cplh[vplane6] 0x0212 2 ++ * @pci.depl_nph[vplane6] 0x0214 2 ++ * @pci.depl_ph[vplane6] 0x0216 2 ++ * @pci.depl_cplh[vplane7] 0x021a 2 ++ * @pci.depl_nph[vplane7] 0x021c 2 ++ * @pci.depl_ph[vplane7] 0x021e 2 ++ * @pci.depl_cplh[vplane8] 0x0222 2 ++ * @pci.depl_nph[vplane8] 0x0224 2 ++ * @pci.depl_ph[vplane8] 0x0226 2 ++ * @pci.depl_cplh[vplane9] 0x022a 2 ++ * @pci.depl_nph[vplane9] 0x022c 2 ++ * @pci.depl_ph[vplane9] 0x022e 2 ++ * @pci.depl_cplh[vplane10] 0x0232 2 ++ * @pci.depl_nph[vplane10] 0x0234 2 ++ * @pci.depl_ph[vplane10] 0x0236 2 ++ * @pci.depl_cplh[vplane11] 0x023a 2 ++ * @pci.depl_nph[vplane11] 0x023c 2 ++ * @pci.depl_ph[vplane11] 0x023e 2 ++ * @pci.depl_cplh[vplane12] 0x0242 2 ++ * @pci.depl_nph[vplane12] 0x0244 2 ++ * @pci.depl_ph[vplane12] 0x0246 2 ++ * @pci.depl_cplh[vplane13] 0x024a 2 ++ * @pci.depl_nph[vplane13] 0x024c 2 ++ * @pci.depl_ph[vplane13] 0x024e 2 ++ * @pci.depl_cplh[vplane14] 0x0252 2 ++ * @pci.depl_nph[vplane14] 0x0254 2 ++ * @pci.depl_ph[vplane14] 0x0256 2 ++ * @pci.depl_cplh[vplane15] 0x025a 2 ++ * @pci.depl_nph[vplane15] 0x025c 2 ++ * @pci.depl_ph[vplane15] 0x025e 2 ++ * @pci.depl_cplh[vplane16] 0x0262 2 ++ * @pci.depl_nph[vplane16] 0x0264 2 ++ * @pci.depl_ph[vplane16] 0x0266 2 ++ * @pci.depl_cpld[vplane0] 0x026a 2 Number of times completion data ++ * credits were depleted ++ * @pci.depl_npd[vplane0] 0x026c 2 Number of times non posted data ++ * credits were depleted ++ * @pci.depl_pd[vplane0] 0x026e 2 Number of times the posted data ++ * credits were depleted ++ * @pci.depl_cpld[vplane1] 0x0272 2 ++ * @pci.depl_npd[vplane1] 0x0274 2 ++ * @pci.depl_pd[vplane1] 0x0276 2 ++ * @pci.depl_cpld[vplane2] 0x027a 2 ++ * @pci.depl_npd[vplane2] 0x027c 2 ++ * @pci.depl_pd[vplane2] 0x027e 2 ++ * @pci.depl_cpld[vplane3] 0x0282 2 ++ * @pci.depl_npd[vplane3] 0x0284 2 ++ * @pci.depl_pd[vplane3] 0x0286 2 ++ * @pci.depl_cpld[vplane4] 0x028a 2 ++ * @pci.depl_npd[vplane4] 0x028c 2 ++ * @pci.depl_pd[vplane4] 0x028e 2 ++ * @pci.depl_cpld[vplane5] 0x0292 2 ++ * @pci.depl_npd[vplane5] 0x0294 2 ++ * @pci.depl_pd[vplane5] 0x0296 2 ++ * @pci.depl_cpld[vplane6] 0x029a 2 ++ * @pci.depl_npd[vplane6] 0x029c 2 ++ * @pci.depl_pd[vplane6] 0x029e 2 ++ * @pci.depl_cpld[vplane7] 0x02a2 2 ++ * @pci.depl_npd[vplane7] 0x02a4 2 ++ * @pci.depl_pd[vplane7] 0x02a6 2 ++ * @pci.depl_cpld[vplane8] 0x02aa 2 ++ * @pci.depl_npd[vplane8] 0x02ac 2 ++ * @pci.depl_pd[vplane8] 0x02ae 2 ++ * @pci.depl_cpld[vplane9] 0x02b2 2 ++ * @pci.depl_npd[vplane9] 0x02b4 2 ++ * @pci.depl_pd[vplane9] 0x02b6 2 ++ * @pci.depl_cpld[vplane10] 0x02ba 2 ++ * @pci.depl_npd[vplane10] 0x02bc 2 ++ * @pci.depl_pd[vplane10] 0x02be 2 ++ * @pci.depl_cpld[vplane11] 0x02c2 2 ++ * @pci.depl_npd[vplane11] 0x02c4 2 ++ * @pci.depl_pd[vplane11] 0x02c6 2 ++ * @pci.depl_cpld[vplane12] 0x02ca 2 ++ * @pci.depl_npd[vplane12] 0x02cc 2 ++ * @pci.depl_pd[vplane12] 0x02ce 2 ++ * @pci.depl_cpld[vplane13] 0x02d2 2 ++ * @pci.depl_npd[vplane13] 0x02d4 2 ++ * @pci.depl_pd[vplane13] 0x02d6 2 ++ * @pci.depl_cpld[vplane14] 0x02da 2 ++ * @pci.depl_npd[vplane14] 0x02dc 2 ++ * @pci.depl_pd[vplane14] 0x02de 2 ++ * @pci.depl_cpld[vplane15] 0x02e2 2 ++ * @pci.depl_npd[vplane15] 0x02e4 2 ++ * @pci.depl_pd[vplane15] 0x02e6 2 ++ * @pci.depl_cpld[vplane16] 0x02ea 2 ++ * @pci.depl_npd[vplane16] 0x02ec 2 ++ * @pci.depl_pd[vplane16] 0x02ee 2 ++ * @xgmac_port[3]; ++ * @xgmac_aggr[2]; ++ * @xgmac.global_prog_event_gnum0 0x0ae0 8 Programmable statistic. ++ * Increments when internal logic detects a certain event. See register ++ * XMAC_STATS_GLOBAL_CFG.EVENT_GNUM0_CFG for more information. ++ * @xgmac.global_prog_event_gnum1 0x0ae8 8 Programmable statistic. ++ * Increments when internal logic detects a certain event. See register ++ * XMAC_STATS_GLOBAL_CFG.EVENT_GNUM1_CFG for more information. ++ * @xgmac.orp_lro_events 0x0af8 8 ++ * @xgmac.orp_bs_events 0x0b00 8 ++ * @xgmac.orp_iwarp_events 0x0b08 8 ++ * @xgmac.tx_permitted_frms 0x0b14 4 ++ * @xgmac.port2_tx_any_frms 0x0b1d 1 ++ * @xgmac.port1_tx_any_frms 0x0b1e 1 ++ * @xgmac.port0_tx_any_frms 0x0b1f 1 ++ * @xgmac.port2_rx_any_frms 0x0b25 1 ++ * @xgmac.port1_rx_any_frms 0x0b26 1 ++ * @xgmac.port0_rx_any_frms 0x0b27 1 ++ * ++ * Titan mrpcim hardware statistics. ++ */ ++struct vxge_hw_device_stats_mrpcim_info { ++/*0x0000*/ u32 pic_ini_rd_drop; ++/*0x0004*/ u32 pic_ini_wr_drop; ++/*0x0008*/ struct { ++ /*0x0000*/ u32 pic_wrcrdtarb_ph_crdt_depleted; ++ /*0x0004*/ u32 unused1; ++ } pic_wrcrdtarb_ph_crdt_depleted_vplane[17]; ++/*0x0090*/ struct { ++ /*0x0000*/ u32 pic_wrcrdtarb_pd_crdt_depleted; ++ /*0x0004*/ u32 unused2; ++ } pic_wrcrdtarb_pd_crdt_depleted_vplane[17]; ++/*0x0118*/ struct { ++ /*0x0000*/ u32 pic_rdcrdtarb_nph_crdt_depleted; ++ /*0x0004*/ u32 unused3; ++ } pic_rdcrdtarb_nph_crdt_depleted_vplane[17]; ++/*0x01a0*/ u32 pic_ini_rd_vpin_drop; ++/*0x01a4*/ u32 pic_ini_wr_vpin_drop; ++/*0x01a8*/ u32 pic_genstats_count0; ++/*0x01ac*/ u32 pic_genstats_count1; ++/*0x01b0*/ u32 pic_genstats_count2; ++/*0x01b4*/ u32 pic_genstats_count3; ++/*0x01b8*/ u32 pic_genstats_count4; ++/*0x01bc*/ u32 unused4; ++/*0x01c0*/ u32 pic_genstats_count5; ++/*0x01c4*/ u32 unused5; ++/*0x01c8*/ u32 pci_rstdrop_cpl; ++/*0x01cc*/ u32 pci_rstdrop_msg; ++/*0x01d0*/ u32 pci_rstdrop_client1; ++/*0x01d4*/ u32 pci_rstdrop_client0; ++/*0x01d8*/ u32 pci_rstdrop_client2; ++/*0x01dc*/ u32 unused6; ++/*0x01e0*/ struct { ++ /*0x0000*/ u16 unused7; ++ /*0x0002*/ u16 pci_depl_cplh; ++ /*0x0004*/ u16 pci_depl_nph; ++ /*0x0006*/ u16 pci_depl_ph; ++ } pci_depl_h_vplane[17]; ++/*0x0268*/ struct { ++ /*0x0000*/ u16 unused8; ++ /*0x0002*/ u16 pci_depl_cpld; ++ /*0x0004*/ u16 pci_depl_npd; ++ /*0x0006*/ u16 pci_depl_pd; ++ } pci_depl_d_vplane[17]; ++/*0x02f0*/ struct vxge_hw_xmac_port_stats xgmac_port[3]; ++/*0x0a10*/ struct vxge_hw_xmac_aggr_stats xgmac_aggr[2]; ++/*0x0ae0*/ u64 xgmac_global_prog_event_gnum0; ++/*0x0ae8*/ u64 xgmac_global_prog_event_gnum1; ++/*0x0af0*/ u64 unused7; ++/*0x0af8*/ u64 unused8; ++/*0x0b00*/ u64 unused9; ++/*0x0b08*/ u64 unused10; ++/*0x0b10*/ u32 unused11; ++/*0x0b14*/ u32 xgmac_tx_permitted_frms; ++/*0x0b18*/ u32 unused12; ++/*0x0b1c*/ u8 unused13; ++/*0x0b1d*/ u8 xgmac_port2_tx_any_frms; ++/*0x0b1e*/ u8 xgmac_port1_tx_any_frms; ++/*0x0b1f*/ u8 xgmac_port0_tx_any_frms; ++/*0x0b20*/ u32 unused14; ++/*0x0b24*/ u8 unused15; ++/*0x0b25*/ u8 xgmac_port2_rx_any_frms; ++/*0x0b26*/ u8 xgmac_port1_rx_any_frms; ++/*0x0b27*/ u8 xgmac_port0_rx_any_frms; ++} __attribute((packed)); ++ ++/** ++ * struct vxge_hw_device_stats_hw_info - Titan hardware statistics. ++ * @vpath_info: VPath statistics ++ * @vpath_info_sav: Vpath statistics saved ++ * ++ * Titan hardware statistics. ++ */ ++struct vxge_hw_device_stats_hw_info { ++ struct vxge_hw_device_stats_mrpcim_info *mrpcim_info; ++ struct vxge_hw_device_stats_mrpcim_info mrpcim_info_sav; ++ struct vxge_hw_vpath_stats_hw_info ++ *vpath_info[VXGE_HW_MAX_VIRTUAL_PATHS]; ++ struct vxge_hw_vpath_stats_hw_info ++ vpath_info_sav[VXGE_HW_MAX_VIRTUAL_PATHS]; ++}; ++ ++/** ++ * struct vxge_hw_vpath_stats_sw_common_info - HW common ++ * statistics for queues. ++ * @full_cnt: Number of times the queue was full ++ * @usage_cnt: usage count. ++ * @usage_max: Maximum usage ++ * @reserve_free_swaps_cnt: Reserve/free swap counter. Internal usage. ++ * @total_compl_cnt: Total descriptor completion count. ++ * ++ * Hw queue counters ++ * See also: struct vxge_hw_vpath_stats_sw_fifo_info{}, ++ * struct vxge_hw_vpath_stats_sw_ring_info{}, ++ */ ++struct vxge_hw_vpath_stats_sw_common_info { ++ u32 full_cnt; ++ u32 usage_cnt; ++ u32 usage_max; ++ u32 reserve_free_swaps_cnt; ++ u32 total_compl_cnt; ++}; ++ ++/** ++ * struct vxge_hw_vpath_stats_sw_fifo_info - HW fifo statistics ++ * @common_stats: Common counters for all queues ++ * @total_posts: Total number of postings on the queue. ++ * @total_buffers: Total number of buffers posted. ++ * @txd_t_code_err_cnt: Array of transmit transfer codes. The position ++ * (index) in this array reflects the transfer code type, for instance ++ * 0xA - "loss of link". ++ * Value txd_t_code_err_cnt[i] reflects the ++ * number of times the corresponding transfer code was encountered. ++ * ++ * HW fifo counters ++ * See also: struct vxge_hw_vpath_stats_sw_common_info{}, ++ * struct vxge_hw_vpath_stats_sw_ring_info{}, ++ */ ++struct vxge_hw_vpath_stats_sw_fifo_info { ++ struct vxge_hw_vpath_stats_sw_common_info common_stats; ++ u32 total_posts; ++ u32 total_buffers; ++ u32 txd_t_code_err_cnt[VXGE_HW_DTR_MAX_T_CODE]; ++}; ++ ++/** ++ * struct vxge_hw_vpath_stats_sw_ring_info - HW ring statistics ++ * @common_stats: Common counters for all queues ++ * @rxd_t_code_err_cnt: Array of receive transfer codes. The position ++ * (index) in this array reflects the transfer code type, ++ * for instance ++ * 0x7 - for "invalid receive buffer size", or 0x8 - for ECC. ++ * Value rxd_t_code_err_cnt[i] reflects the ++ * number of times the corresponding transfer code was encountered. ++ * ++ * HW ring counters ++ * See also: struct vxge_hw_vpath_stats_sw_common_info{}, ++ * struct vxge_hw_vpath_stats_sw_fifo_info{}, ++ */ ++struct vxge_hw_vpath_stats_sw_ring_info { ++ struct vxge_hw_vpath_stats_sw_common_info common_stats; ++ u32 rxd_t_code_err_cnt[VXGE_HW_DTR_MAX_T_CODE]; ++ /* LRO statistics */ ++ /* total no of Aggregated packets */ ++ u64 lro_clubbed_frms_cnt; ++ /* Number of times the aggregation of packets broken */ ++ u64 lro_sending_both; ++ /* Number of out of order packets */ ++ u64 lro_outof_sequence_pkts; ++ /* Number of times we reached upper packet limit ++ * for aggregation per session */ ++ u64 lro_flush_max_pkts; ++ /* Total number of packets considered for aggregation */ ++ u64 lro_sum_avg_pkts_aggregated; ++ /* Number of packets sent to the stack */ ++ u64 lro_num_aggregations; ++ /* Max number of aggr packet per ring */ ++ u64 lro_max_pkts_aggr; ++ /* Average Aggregate packet */ ++ u64 lro_avg_agr_pkts; ++}; ++ ++/** ++ * struct vxge_hw_vpath_stats_sw_err - HW vpath error statistics ++ * @unknown_alarms: ++ * @network_sustained_fault: ++ * @network_sustained_ok: ++ * @kdfcctl_fifo0_overwrite: ++ * @kdfcctl_fifo0_poison: ++ * @kdfcctl_fifo0_dma_error: ++ * @dblgen_fifo0_overflow: ++ * @statsb_pif_chain_error: ++ * @statsb_drop_timeout: ++ * @target_illegal_access: ++ * @ini_serr_det: ++ * @prc_ring_bumps: ++ * @prc_rxdcm_sc_err: ++ * @prc_rxdcm_sc_abort: ++ * @prc_quanta_size_err: ++ * ++ * HW vpath error statistics ++ */ ++struct vxge_hw_vpath_stats_sw_err { ++ u32 unknown_alarms; ++ u32 network_sustained_fault; ++ u32 network_sustained_ok; ++ u32 kdfcctl_fifo0_overwrite; ++ u32 kdfcctl_fifo0_poison; ++ u32 kdfcctl_fifo0_dma_error; ++ u32 dblgen_fifo0_overflow; ++ u32 statsb_pif_chain_error; ++ u32 statsb_drop_timeout; ++ u32 target_illegal_access; ++ u32 ini_serr_det; ++ u32 prc_ring_bumps; ++ u32 prc_rxdcm_sc_err; ++ u32 prc_rxdcm_sc_abort; ++ u32 prc_quanta_size_err; ++}; ++ ++/** ++ * struct vxge_hw_vpath_stats_sw_info - HW vpath sw statistics ++ * @soft_reset_cnt: Number of times soft reset is done on this vpath. ++ * @error_stats: error counters for the vpath ++ * @ring_stats: counters for ring belonging to the vpath ++ * @fifo_stats: counters for fifo belonging to the vpath ++ * ++ * HW vpath sw statistics ++ * See also: struct vxge_hw_device_info{} }. ++ */ ++struct vxge_hw_vpath_stats_sw_info { ++ u32 soft_reset_cnt; ++ struct vxge_hw_vpath_stats_sw_err error_stats; ++ struct vxge_hw_vpath_stats_sw_ring_info ring_stats; ++ struct vxge_hw_vpath_stats_sw_fifo_info fifo_stats; ++}; ++ ++/** ++ * struct vxge_hw_device_stats_sw_info - HW own per-device statistics. ++ * ++ * @not_traffic_intr_cnt: Number of times the host was interrupted ++ * without new completions. ++ * "Non-traffic interrupt counter". ++ * @traffic_intr_cnt: Number of traffic interrupts for the device. ++ * @total_intr_cnt: Total number of traffic interrupts for the device. ++ * @total_intr_cnt == @traffic_intr_cnt + ++ * @not_traffic_intr_cnt ++ * @soft_reset_cnt: Number of times soft reset is done on this device. ++ * @vpath_info: please see struct vxge_hw_vpath_stats_sw_info{} ++ * HW per-device statistics. ++ */ ++struct vxge_hw_device_stats_sw_info { ++ u32 not_traffic_intr_cnt; ++ u32 traffic_intr_cnt; ++ u32 total_intr_cnt; ++ u32 soft_reset_cnt; ++ struct vxge_hw_vpath_stats_sw_info ++ vpath_info[VXGE_HW_MAX_VIRTUAL_PATHS]; ++}; ++ ++/** ++ * struct vxge_hw_device_stats_sw_err - HW device error statistics. ++ * @vpath_alarms: Number of vpath alarms ++ * ++ * HW Device error stats ++ */ ++struct vxge_hw_device_stats_sw_err { ++ u32 vpath_alarms; ++}; ++ ++/** ++ * struct vxge_hw_device_stats - Contains HW per-device statistics, ++ * including hw. ++ * @devh: HW device handle. ++ * @dma_addr: DMA addres of the %hw_info. Given to device to fill-in the stats. ++ * @hw_info_dmah: DMA handle used to map hw statistics onto the device memory ++ * space. ++ * @hw_info_dma_acch: One more DMA handle used subsequently to free the ++ * DMA object. Note that this and the previous handle have ++ * physical meaning for Solaris; on Windows and Linux the ++ * corresponding value will be simply pointer to PCI device. ++ * ++ * @hw_dev_info_stats: Titan statistics maintained by the hardware. ++ * @sw_dev_info_stats: HW's "soft" device informational statistics, e.g. number ++ * of completions per interrupt. ++ * @sw_dev_err_stats: HW's "soft" device error statistics. ++ * ++ * Structure-container of HW per-device statistics. Note that per-channel ++ * statistics are kept in separate structures under HW's fifo and ring ++ * channels. ++ */ ++struct vxge_hw_device_stats { ++ /* handles */ ++ struct __vxge_hw_device *devh; ++ ++ /* HW device hardware statistics */ ++ struct vxge_hw_device_stats_hw_info hw_dev_info_stats; ++ ++ /* HW device "soft" stats */ ++ struct vxge_hw_device_stats_sw_err sw_dev_err_stats; ++ struct vxge_hw_device_stats_sw_info sw_dev_info_stats; ++ ++}; ++ ++enum vxge_hw_status vxge_hw_device_hw_stats_enable( ++ struct __vxge_hw_device *devh); ++ ++enum vxge_hw_status vxge_hw_device_stats_get( ++ struct __vxge_hw_device *devh, ++ struct vxge_hw_device_stats_hw_info *hw_stats); ++ ++enum vxge_hw_status vxge_hw_driver_stats_get( ++ struct __vxge_hw_device *devh, ++ struct vxge_hw_device_stats_sw_info *sw_stats); ++ ++enum vxge_hw_status vxge_hw_mrpcim_stats_enable(struct __vxge_hw_device *devh); ++ ++enum vxge_hw_status vxge_hw_mrpcim_stats_disable(struct __vxge_hw_device *devh); ++ ++enum vxge_hw_status ++vxge_hw_mrpcim_stats_access( ++ struct __vxge_hw_device *devh, ++ u32 operation, ++ u32 location, ++ u32 offset, ++ u64 *stat); ++ ++enum vxge_hw_status ++vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *devh, u32 port, ++ struct vxge_hw_xmac_aggr_stats *aggr_stats); ++ ++enum vxge_hw_status ++vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *devh, u32 port, ++ struct vxge_hw_xmac_port_stats *port_stats); ++ ++enum vxge_hw_status ++vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *devh, ++ struct vxge_hw_xmac_stats *xmac_stats); ++ ++/** ++ * enum enum vxge_hw_mgmt_reg_type - Register types. ++ * ++ * @vxge_hw_mgmt_reg_type_legacy: Legacy registers ++ * @vxge_hw_mgmt_reg_type_toc: TOC Registers ++ * @vxge_hw_mgmt_reg_type_common: Common Registers ++ * @vxge_hw_mgmt_reg_type_mrpcim: mrpcim registers ++ * @vxge_hw_mgmt_reg_type_srpcim: srpcim registers ++ * @vxge_hw_mgmt_reg_type_vpmgmt: vpath management registers ++ * @vxge_hw_mgmt_reg_type_vpath: vpath registers ++ * ++ * Register type enumaration ++ */ ++enum vxge_hw_mgmt_reg_type { ++ vxge_hw_mgmt_reg_type_legacy = 0, ++ vxge_hw_mgmt_reg_type_toc = 1, ++ vxge_hw_mgmt_reg_type_common = 2, ++ vxge_hw_mgmt_reg_type_mrpcim = 3, ++ vxge_hw_mgmt_reg_type_srpcim = 4, ++ vxge_hw_mgmt_reg_type_vpmgmt = 5, ++ vxge_hw_mgmt_reg_type_vpath = 6 ++}; ++ ++enum vxge_hw_status ++vxge_hw_mgmt_reg_read(struct __vxge_hw_device *devh, ++ enum vxge_hw_mgmt_reg_type type, ++ u32 index, ++ u32 offset, ++ u64 *value); ++ ++enum vxge_hw_status ++vxge_hw_mgmt_reg_write(struct __vxge_hw_device *devh, ++ enum vxge_hw_mgmt_reg_type type, ++ u32 index, ++ u32 offset, ++ u64 value); ++ ++/** ++ * enum enum vxge_hw_rxd_state - Descriptor (RXD) state. ++ * @VXGE_HW_RXD_STATE_NONE: Invalid state. ++ * @VXGE_HW_RXD_STATE_AVAIL: Descriptor is available for reservation. ++ * @VXGE_HW_RXD_STATE_POSTED: Descriptor is posted for processing by the ++ * device. ++ * @VXGE_HW_RXD_STATE_FREED: Descriptor is free and can be reused for ++ * filling-in and posting later. ++ * ++ * Titan/HW descriptor states. ++ * ++ */ ++enum vxge_hw_rxd_state { ++ VXGE_HW_RXD_STATE_NONE = 0, ++ VXGE_HW_RXD_STATE_AVAIL = 1, ++ VXGE_HW_RXD_STATE_POSTED = 2, ++ VXGE_HW_RXD_STATE_FREED = 3 ++}; ++ ++/** ++ * struct vxge_hw_ring_rxd_info - Extended information associated with a ++ * completed ring descriptor. ++ * @syn_flag: SYN flag ++ * @is_icmp: Is ICMP ++ * @fast_path_eligible: Fast Path Eligible flag ++ * @l3_cksum: in L3 checksum is valid ++ * @l3_cksum: Result of IP checksum check (by Titan hardware). ++ * This field containing VXGE_HW_L3_CKSUM_OK would mean that ++ * the checksum is correct, otherwise - the datagram is ++ * corrupted. ++ * @l4_cksum: in L4 checksum is valid ++ * @l4_cksum: Result of TCP/UDP checksum check (by Titan hardware). ++ * This field containing VXGE_HW_L4_CKSUM_OK would mean that ++ * the checksum is correct. Otherwise - the packet is ++ * corrupted. ++ * @frame: Zero or more of enum vxge_hw_frame_type flags. ++ * See enum vxge_hw_frame_type{}. ++ * @proto: zero or more of enum vxge_hw_frame_proto flags. Reporting bits for ++ * various higher-layer protocols, including (but note restricted to) ++ * TCP and UDP. See enum vxge_hw_frame_proto{}. ++ * @is_vlan: If vlan tag is valid ++ * @vlan: VLAN tag extracted from the received frame. ++ * @rth_bucket: RTH bucket ++ * @rth_it_hit: Set, If RTH hash value calculated by the Titan hardware ++ * has a matching entry in the Indirection table. ++ * @rth_spdm_hit: Set, If RTH hash value calculated by the Titan hardware ++ * has a matching entry in the Socket Pair Direct Match table. ++ * @rth_hash_type: RTH hash code of the function used to calculate the hash. ++ * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by Titan ++ * hardware if RTH is enabled. ++ */ ++struct vxge_hw_ring_rxd_info { ++ u32 syn_flag; ++ u32 is_icmp; ++ u32 fast_path_eligible; ++ u32 l3_cksum_valid; ++ u32 l3_cksum; ++ u32 l4_cksum_valid; ++ u32 l4_cksum; ++ u32 frame; ++ u32 proto; ++ u32 is_vlan; ++#define VXGE_HW_VLAN_VID_MASK 0xfff ++ u32 vlan; ++ struct vlan_group *vlgrp; ++ struct net_device *dev; ++ u32 rth_bucket; ++ u32 rth_it_hit; ++ u32 rth_spdm_hit; ++ u32 rth_hash_type; ++ u32 rth_value; ++}; ++ ++/** ++ * enum enum vxge_hw_ring_hash_type - RTH hash types ++ * @VXGE_HW_RING_HASH_TYPE_NONE: No Hash ++ * @VXGE_HW_RING_HASH_TYPE_TCP_IPV4: TCP IPv4 ++ * @VXGE_HW_RING_HASH_TYPE_UDP_IPV4: UDP IPv4 ++ * @VXGE_HW_RING_HASH_TYPE_IPV4: IPv4 ++ * @VXGE_HW_RING_HASH_TYPE_TCP_IPV6: TCP IPv6 ++ * @VXGE_HW_RING_HASH_TYPE_UDP_IPV6: UDP IPv6 ++ * @VXGE_HW_RING_HASH_TYPE_IPV6: IPv6 ++ * @VXGE_HW_RING_HASH_TYPE_TCP_IPV6_EX: TCP IPv6 extension ++ * @VXGE_HW_RING_HASH_TYPE_UDP_IPV6_EX: UDP IPv6 extension ++ * @VXGE_HW_RING_HASH_TYPE_IPV6_EX: IPv6 extension ++ * ++ * RTH hash types ++ */ ++enum vxge_hw_ring_hash_type { ++ VXGE_HW_RING_HASH_TYPE_NONE = 0x0, ++ VXGE_HW_RING_HASH_TYPE_TCP_IPV4 = 0x1, ++ VXGE_HW_RING_HASH_TYPE_UDP_IPV4 = 0x2, ++ VXGE_HW_RING_HASH_TYPE_IPV4 = 0x3, ++ VXGE_HW_RING_HASH_TYPE_TCP_IPV6 = 0x4, ++ VXGE_HW_RING_HASH_TYPE_UDP_IPV6 = 0x5, ++ VXGE_HW_RING_HASH_TYPE_IPV6 = 0x6, ++ VXGE_HW_RING_HASH_TYPE_TCP_IPV6_EX = 0x7, ++ VXGE_HW_RING_HASH_TYPE_UDP_IPV6_EX = 0x8, ++ VXGE_HW_RING_HASH_TYPE_IPV6_EX = 0x9 ++}; ++ ++enum vxge_hw_status vxge_hw_ring_rxd_reserve( ++ struct __vxge_hw_ring *ring_handle, ++ void **rxdh); ++ ++void ++vxge_hw_ring_rxd_pre_post( ++ struct __vxge_hw_ring *ring_handle, ++ void *rxdh); ++ ++void ++vxge_hw_ring_rxd_post_post( ++ struct __vxge_hw_ring *ring_handle, ++ void *rxdh); ++ ++enum vxge_hw_status ++vxge_hw_ring_replenish(struct __vxge_hw_ring *ring_handle, u16 min_flag); ++ ++void ++vxge_hw_ring_rxd_post_post_wmb( ++ struct __vxge_hw_ring *ring_handle, ++ void *rxdh); ++ ++void vxge_hw_ring_rxd_post( ++ struct __vxge_hw_ring *ring_handle, ++ void *rxdh); ++ ++enum vxge_hw_status vxge_hw_ring_rxd_next_completed( ++ struct __vxge_hw_ring *ring_handle, ++ void **rxdh, ++ u8 *t_code); ++ ++enum vxge_hw_status vxge_hw_ring_handle_tcode( ++ struct __vxge_hw_ring *ring_handle, ++ void *rxdh, ++ u8 t_code); ++ ++void vxge_hw_ring_rxd_free( ++ struct __vxge_hw_ring *ring_handle, ++ void *rxdh); ++ ++/** ++ * enum enum vxge_hw_frame_proto - Higher-layer ethernet protocols. ++ * @VXGE_HW_FRAME_PROTO_VLAN_TAGGED: VLAN. ++ * @VXGE_HW_FRAME_PROTO_IPV4: IPv4. ++ * @VXGE_HW_FRAME_PROTO_IPV6: IPv6. ++ * @VXGE_HW_FRAME_PROTO_IP_FRAG: IP fragmented. ++ * @VXGE_HW_FRAME_PROTO_TCP: TCP. ++ * @VXGE_HW_FRAME_PROTO_UDP: UDP. ++ * @VXGE_HW_FRAME_PROTO_TCP_OR_UDP: TCP or UDP. ++ * ++ * Higher layer ethernet protocols and options. ++ */ ++enum vxge_hw_frame_proto { ++ VXGE_HW_FRAME_PROTO_VLAN_TAGGED = 0x80, ++ VXGE_HW_FRAME_PROTO_IPV4 = 0x10, ++ VXGE_HW_FRAME_PROTO_IPV6 = 0x08, ++ VXGE_HW_FRAME_PROTO_IP_FRAG = 0x04, ++ VXGE_HW_FRAME_PROTO_TCP = 0x02, ++ VXGE_HW_FRAME_PROTO_UDP = 0x01, ++ VXGE_HW_FRAME_PROTO_TCP_OR_UDP = (VXGE_HW_FRAME_PROTO_TCP | \ ++ VXGE_HW_FRAME_PROTO_UDP) ++}; ++ ++/** ++ * enum enum vxge_hw_fifo_gather_code - Gather codes used in fifo TxD ++ * @VXGE_HW_FIFO_GATHER_CODE_FIRST: First TxDL ++ * @VXGE_HW_FIFO_GATHER_CODE_MIDDLE: Middle TxDL ++ * @VXGE_HW_FIFO_GATHER_CODE_LAST: Last TxDL ++ * @VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST: First and Last TxDL. ++ * ++ * These gather codes are used to indicate the position of a TxD in a TxD list ++ */ ++enum vxge_hw_fifo_gather_code { ++ VXGE_HW_FIFO_GATHER_CODE_FIRST = 0x2, ++ VXGE_HW_FIFO_GATHER_CODE_MIDDLE = 0x0, ++ VXGE_HW_FIFO_GATHER_CODE_LAST = 0x1, ++ VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST = 0x3 ++}; ++ ++/** ++ * enum enum vxge_hw_fifo_tcode - tcodes used in fifo ++ * @VXGE_HW_FIFO_T_CODE_OK: Transfer OK ++ * @VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT: PCI read transaction (either TxD or ++ * frame data) returned with corrupt data. ++ * @VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL:PCI read transaction was returned ++ * with no data. ++ * @VXGE_HW_FIFO_T_CODE_INVALID_MSS: The host attempted to send either a ++ * frame or LSO MSS that was too long (>9800B). ++ * @VXGE_HW_FIFO_T_CODE_LSO_ERROR: Error detected during TCP/UDP Large Send ++ * Offload operation, due to improper header template, ++ * unsupported protocol, etc. ++ * @VXGE_HW_FIFO_T_CODE_UNUSED: Unused ++ * @VXGE_HW_FIFO_T_CODE_MULTI_ERROR: Set to 1 by the adapter if multiple ++ * data buffer transfer errors are encountered (see below). ++ * Otherwise it is set to 0. ++ * ++ * These tcodes are returned in various API for TxD status ++ */ ++enum vxge_hw_fifo_tcode { ++ VXGE_HW_FIFO_T_CODE_OK = 0x0, ++ VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT = 0x1, ++ VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL = 0x2, ++ VXGE_HW_FIFO_T_CODE_INVALID_MSS = 0x3, ++ VXGE_HW_FIFO_T_CODE_LSO_ERROR = 0x4, ++ VXGE_HW_FIFO_T_CODE_UNUSED = 0x7, ++ VXGE_HW_FIFO_T_CODE_MULTI_ERROR = 0x8 ++}; ++ ++enum vxge_hw_status vxge_hw_fifo_txdl_reserve( ++ struct __vxge_hw_fifo *fifoh, ++ void **txdlh, ++ void **txdl_priv); ++ ++void vxge_hw_fifo_txdl_buffer_set( ++ struct __vxge_hw_fifo *fifo_handle, ++ void *txdlh, ++ u32 frag_idx, ++ dma_addr_t dma_pointer, ++ u32 size); ++ ++void vxge_hw_fifo_txdl_post( ++ struct __vxge_hw_fifo *fifo_handle, ++ void *txdlh, ++ u32 tagged); ++ ++u32 vxge_hw_fifo_free_txdl_count_get( ++ struct __vxge_hw_fifo *fifo_handle); ++ ++enum vxge_hw_status vxge_hw_fifo_txdl_next_completed( ++ struct __vxge_hw_fifo *fifoh, ++ void **txdlh, ++ enum vxge_hw_fifo_tcode *t_code); ++ ++enum vxge_hw_status vxge_hw_fifo_handle_tcode( ++ struct __vxge_hw_fifo *fifoh, ++ void *txdlh, ++ enum vxge_hw_fifo_tcode t_code); ++ ++void vxge_hw_fifo_txdl_free( ++ struct __vxge_hw_fifo *fifoh, ++ void *txdlh); ++ ++/* ++ * Device ++ */ ++ ++#define VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET (VXGE_HW_BLOCK_SIZE-8) ++#define VXGE_HW_RING_MEMBLOCK_IDX_OFFSET (VXGE_HW_BLOCK_SIZE-16) ++#define VXGE_HW_RING_MIN_BUFF_ALLOCATION 64 ++ ++/* ++ * struct __vxge_hw_ring_rxd_priv - Receive descriptor HW-private data. ++ * @dma_addr: DMA (mapped) address of _this_ descriptor. ++ * @dma_handle: DMA handle used to map the descriptor onto device. ++ * @dma_offset: Descriptor's offset in the memory block. HW allocates ++ * descriptors in memory blocks of %VXGE_HW_BLOCK_SIZE ++ * bytes. Each memblock is contiguous DMA-able memory. Each ++ * memblock contains 1 or more 4KB RxD blocks visible to the ++ * Titan hardware. ++ * @dma_object: DMA address and handle of the memory block that contains ++ * the descriptor. This member is used only in the "checked" ++ * version of the HW (to enforce certain assertions); ++ * otherwise it gets compiled out. ++ * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. ++ * ++ * Per-receive decsriptor HW-private data. HW uses the space to keep DMA ++ * information associated with the descriptor. Note that driver can ask HW ++ * to allocate additional per-descriptor space for its own (driver-specific) ++ * purposes. ++ */ ++struct __vxge_hw_ring_rxd_priv { ++ dma_addr_t dma_addr; ++ struct pci_dev *dma_handle; ++ ptrdiff_t dma_offset; ++#ifdef VXGE_DEBUG_ASSERT ++ struct vxge_hw_mempool_dma *dma_object; ++#endif ++}; ++ ++/* ========================= RING PRIVATE API ============================= */ ++u64 ++__vxge_hw_ring_first_block_address_get( ++ struct __vxge_hw_ring *ringh); ++ ++enum vxge_hw_status ++__vxge_hw_ring_create( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ struct vxge_hw_ring_attr *attr); ++ ++enum vxge_hw_status ++__vxge_hw_ring_abort( ++ struct __vxge_hw_ring *ringh); ++ ++enum vxge_hw_status ++__vxge_hw_ring_reset( ++ struct __vxge_hw_ring *ringh); ++ ++enum vxge_hw_status ++__vxge_hw_ring_delete( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++/* ========================= FIFO PRIVATE API ============================= */ ++ ++struct vxge_hw_fifo_attr; ++ ++enum vxge_hw_status ++__vxge_hw_fifo_create( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ struct vxge_hw_fifo_attr *attr); ++ ++enum vxge_hw_status ++__vxge_hw_fifo_abort( ++ struct __vxge_hw_fifo *fifoh); ++ ++enum vxge_hw_status ++__vxge_hw_fifo_reset( ++ struct __vxge_hw_fifo *ringh); ++ ++enum vxge_hw_status ++__vxge_hw_fifo_delete( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++struct vxge_hw_mempool_cbs { ++ void (*item_func_alloc)( ++ struct vxge_hw_mempool *mempoolh, ++ u32 memblock_index, ++ struct vxge_hw_mempool_dma *dma_object, ++ u32 index, ++ u32 is_last); ++}; ++ ++void ++__vxge_hw_mempool_destroy( ++ struct vxge_hw_mempool *mempool); ++ ++#define VXGE_HW_VIRTUAL_PATH_HANDLE(vpath) \ ++ ((struct __vxge_hw_vpath_handle *)(vpath)->vpath_handles.next) ++ ++enum vxge_hw_status ++__vxge_hw_vpath_rts_table_get( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u32 action, ++ u32 rts_table, ++ u32 offset, ++ u64 *data1, ++ u64 *data2); ++enum vxge_hw_status ++__vxge_hw_vpath_rts_table_get_vpn( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u32 action, ++ u32 rts_table, ++ u32 offset, ++ u64 *data1, ++ u64 *data2, ++ u32 vpn); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_rts_table_set_vpn( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u32 action, ++ u32 rts_table, ++ u32 offset, ++ u64 data1, ++ u64 data2, ++ u32 vpn); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_rts_table_set( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u32 action, ++ u32 rts_table, ++ u32 offset, ++ u64 data1, ++ u64 data2); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_reset( ++ struct __vxge_hw_device *devh, ++ u32 vp_id); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_sw_reset( ++ struct __vxge_hw_device *devh, ++ u32 vp_id); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_enable( ++ struct __vxge_hw_device *devh, ++ u32 vp_id); ++ ++void ++__vxge_hw_vpath_prc_configure( ++ struct __vxge_hw_device *devh, ++ u32 vp_id); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_kdfc_configure( ++ struct __vxge_hw_device *devh, ++ u32 vp_id); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_mac_configure( ++ struct __vxge_hw_device *devh, ++ u32 vp_id); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_tim_configure( ++ struct __vxge_hw_device *devh, ++ u32 vp_id); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_initialize( ++ struct __vxge_hw_device *devh, ++ u32 vp_id); ++ ++enum vxge_hw_status ++__vxge_hw_vp_initialize( ++ struct __vxge_hw_device *devh, ++ u32 vp_id, ++ struct vxge_hw_vp_config *config); ++ ++void ++__vxge_hw_vp_terminate( ++ struct __vxge_hw_device *devh, ++ u32 vp_id); ++ ++enum vxge_hw_status ++__vxge_hw_vpath_alarm_process( ++ struct __vxge_hw_virtualpath *vpath, ++ u32 skip_alarms); ++ ++void vxge_hw_device_intr_enable( ++ struct __vxge_hw_device *devh); ++ ++u32 vxge_hw_device_set_intr_type(struct __vxge_hw_device *devh, u32 intr_mode); ++ ++void vxge_hw_device_intr_disable( ++ struct __vxge_hw_device *devh); ++ ++void vxge_hw_device_mask_all( ++ struct __vxge_hw_device *devh); ++ ++void vxge_hw_device_unmask_all( ++ struct __vxge_hw_device *devh); ++ ++enum vxge_hw_status vxge_hw_device_begin_irq( ++ struct __vxge_hw_device *devh, ++ u32 skip_alarms, ++ u64 *reason); ++ ++void vxge_hw_device_clear_tx_rx( ++ struct __vxge_hw_device *devh); ++ ++/* ++ * Virtual Paths ++ */ ++ ++void ++vxge_hw_vpath_dynamic_rti_ci_set(struct __vxge_hw_ring *ring); ++ ++void ++vxge_hw_vpath_dynamic_rti_ci_reset(struct __vxge_hw_ring *ring); ++ ++void ++vxge_hw_vpath_dynamic_rti_btimer_set(struct __vxge_hw_ring *ring); ++ ++void ++vxge_hw_vpath_dynamic_rti_rtimer_set(struct __vxge_hw_ring *ring); ++ ++u32 vxge_hw_vpath_id( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++enum vxge_hw_vpath_mac_addr_add_mode { ++ VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE = 0, ++ VXGE_HW_VPATH_MAC_ADDR_DISCARD_DUPLICATE = 1, ++ VXGE_HW_VPATH_MAC_ADDR_REPLACE_DUPLICATE = 2 ++}; ++ ++enum vxge_hw_status ++vxge_hw_vpath_mac_addr_get_vpn( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u8 (macaddr)[ETH_ALEN], ++ u8 (macaddr_mask)[ETH_ALEN], ++ u32 vpn); ++ ++enum vxge_hw_status ++vxge_hw_vpath_mac_addr_get_next_vpn( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u8 (macaddr)[ETH_ALEN], ++ u8 (macaddr_mask)[ETH_ALEN], ++ u32 vpn); ++ ++enum vxge_hw_status ++vxge_hw_vpath_mac_addr_add_vpn( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u8 (macaddr)[ETH_ALEN], ++ u8 (macaddr_mask)[ETH_ALEN], ++ enum vxge_hw_vpath_mac_addr_add_mode duplicate_mode, ++ u32 vpn); ++ ++enum vxge_hw_status ++vxge_hw_vpath_mac_addr_del_vpn( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u8 (macaddr)[ETH_ALEN], ++ u8 (macaddr_mask)[ETH_ALEN], ++ u32 vpn); ++ ++enum vxge_hw_status ++vxge_hw_vpath_vid_get_vpn( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u64 *vid, ++ u32 vpn); ++ ++enum vxge_hw_status ++vxge_hw_vpath_vid_get_next_vpn( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u64 *vid, ++ u32 vpn); ++ ++enum vxge_hw_status ++vxge_hw_vpath_vid_add_vpn( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u64 vid, ++ u32 vpn); ++ ++enum vxge_hw_status ++vxge_hw_vpath_vid_delete_vpn( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u64 vid, ++ u32 vpn); ++ ++void ++vxge_hw_vpath_doorbell_rx( ++ struct __vxge_hw_ring *ringh); ++ ++enum vxge_hw_status ++vxge_hw_vpath_etype_add( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u64 etype); ++ ++enum vxge_hw_status ++vxge_hw_vpath_etype_get( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u64 *etype); ++ ++enum vxge_hw_status ++vxge_hw_vpath_etype_get_next( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u64 *etype); ++ ++enum vxge_hw_status ++vxge_hw_vpath_etype_delete( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u64 etype); ++ ++void vxge_hw_vpath_promisc_enable( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++void vxge_hw_vpath_promisc_disable( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++enum vxge_hw_status vxge_hw_vpath_bcast_enable( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++enum vxge_hw_status vxge_hw_vpath_mcast_enable( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++enum vxge_hw_status vxge_hw_vpath_mcast_disable( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++enum vxge_hw_status vxge_hw_vpath_all_vid_enable( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++enum vxge_hw_status vxge_hw_vpath_poll_rx( ++ struct __vxge_hw_ring *ringh); ++ ++enum vxge_hw_status vxge_hw_vpath_poll_tx( ++ struct __vxge_hw_fifo *fifoh, ++ struct sk_buff ***skb_ptr, int nr_skb, int *more); ++ ++enum vxge_hw_status vxge_hw_vpath_alarm_process( ++ struct __vxge_hw_vpath_handle *vpath_handle, ++ u32 skip_alarms); ++ ++void ++vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vpath_handle, ++ int *tim_msix_id, int alarm_msix_id); ++ ++void ++vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vpath_handle, ++ int msix_id); ++ ++void vxge_hw_device_flush_io(struct __vxge_hw_device *devh); ++ ++void ++vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vpath_handle, ++ int msix_id); ++ ++void ++vxge_hw_vpath_msix_unmask(struct __vxge_hw_vpath_handle *vpath_handle, ++ int msix_id); ++ ++void ++vxge_hw_vpath_msix_mask_all(struct __vxge_hw_vpath_handle *vpath_handle); ++ ++enum vxge_hw_status vxge_hw_vpath_intr_enable( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++enum vxge_hw_status vxge_hw_vpath_intr_disable( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++void vxge_hw_vpath_inta_mask_tx_rx( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++void vxge_hw_vpath_inta_unmask_tx_rx( ++ struct __vxge_hw_vpath_handle *vpath_handle); ++ ++void ++vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channelh, int msix_id); ++ ++void ++vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channelh, int msix_id); ++ ++enum vxge_hw_status ++vxge_hw_channel_dtr_alloc(struct __vxge_hw_channel *channel, void **dtrh); ++ ++void ++vxge_hw_channel_dtr_post(struct __vxge_hw_channel *channel, void *dtrh); ++ ++void ++vxge_hw_channel_dtr_try_complete(struct __vxge_hw_channel *channel, ++ void **dtrh); ++ ++void ++vxge_hw_channel_dtr_complete(struct __vxge_hw_channel *channel); ++ ++void ++vxge_hw_channel_dtr_free(struct __vxge_hw_channel *channel, void *dtrh); ++ ++int ++vxge_hw_channel_dtr_count(struct __vxge_hw_channel *channel); ++ ++/* ========================== PRIVATE API ================================= */ ++ ++enum vxge_hw_status ++__vxge_hw_device_handle_link_up_ind(struct __vxge_hw_device *hldev); ++ ++enum vxge_hw_status ++__vxge_hw_device_handle_link_down_ind(struct __vxge_hw_device *hldev); ++ ++enum vxge_hw_status ++__vxge_hw_device_handle_error( ++ struct __vxge_hw_device *hldev, ++ u32 vp_id, ++ enum vxge_hw_event type); ++ ++#if !defined(VXGE_KERNEL_GRO) ++ ++#define CONFIG_LRO_PUSH_TIMEOUT 100 /* micro seconds. */ ++#define CONFIG_LRO_MAX_SG_NUM 5 /* For time being lets just take 2 */ ++#define CONFIG_LRO_MAX_ACCUM_LENGTH (64 * 1024) ++#define OS_NETSTACK_BUF struct sk_buff* ++#define vxge_os_in_multicast(addr) IN_MULTICAST(addr) ++#define VXGE_OS_INADDR_BROADCAST INADDR_BROADCAST ++ ++/** ++ * enum enum vxge_hw_frame_type - Ethernet frame format. ++ * @VXGE_HW_FRAME_TYPE_DIX: DIX (Ethernet II) format. ++ * @VXGE_HW_FRAME_TYPE_LLC: LLC format. ++ * @VXGE_HW_FRAME_TYPE_SNAP: SNAP format. ++ * @VXGE_HW_FRAME_TYPE_IPX: IPX format. ++ * ++ * Ethernet frame format. ++ */ ++enum vxge_hw_frame_type { ++ VXGE_HW_FRAME_TYPE_DIX = 0x0, ++ VXGE_HW_FRAME_TYPE_LLC = 0x1, ++ VXGE_HW_FRAME_TYPE_SNAP = 0x2, ++ VXGE_HW_FRAME_TYPE_IPX = 0x3, ++}; ++enum vxge_hw_tcp_option { ++ ++ VXGE_HW_TCPOPT_NOP = 1, /* Padding */ ++ VXGE_HW_TCPOPT_EOL = 0, /* End of options */ ++ VXGE_HW_TCPOPT_MSS = 2, /* Segment size negotiating */ ++ VXGE_HW_TCPOPT_WINDOW = 3, /* Window scaling */ ++ VXGE_HW_TCPOPT_SACK_PERM = 4, /* SACK Permitted */ ++ VXGE_HW_TCPOPT_SACK = 5, /* SACK Block */ ++ VXGE_HW_TCPOPT_TIMESTAMP = 8, /* Better RTT estimations/PAWS */ ++ VXGE_HW_TCPOPT_MD5SIG = 19, /* MD5 Signature (RFC2385) */ ++ VXGE_HW_TCPOLEN_TIMESTAMP = 10, ++ VXGE_HW_TCPOLEN_TSTAMP_ALIGNED = 12 ++ ++}; ++ ++/** ++ * struct vxge_hw_sw_lro - Software LRO Structure ++ * ++ * @os_buf: Contains scatter-gather list of xframe-mapped received buffers ++ * @ll_hdr: link layer header of the first frame; remains intack throughout ++ * the processing ++ * @ip_hdr: IP header - gets _collapsed_ ++ * @tcp_hdr: Transport header - gets _collapsed_ ++ * @tcp_next_seq_num: Next tcp sequence number ++ * @tcp_seq_num: Current tcp seq ++ * @tcp_ack_num: Current tcp ack ++ * @sg_num: Total number of accumulated (so far) frames ++ * @total_length: Total data length ++ * @frags_len: Total length of the fragments clubbed with the inital frame ++ * @ts_off: LRO frame contains time stamp, if (ts_off != -1) ++ */ ++struct vxge_hw_sw_lro { ++ struct list_head lro_node; ++ OS_NETSTACK_BUF os_buf; ++ struct iphdr *iph; ++ struct tcphdr *tcph; ++ u32 tcp_next_seq_num; ++ u32 tcp_seq_num; ++ u32 tcp_ack_num; ++ int sg_num; ++ int total_length; ++ u32 frags_len; ++ u32 cur_tsval; ++ __be32 cur_tsecr; ++ u32 saw_ts; ++ u16 window; ++ u16 vlan_tag; ++}; ++ ++#define VXGE_HW_TS_SAVE 2 ++#define VXGE_HW_TS_VERIFY 1 ++#define VXGE_HW_TS_UPDATE 0 ++ ++#define VXGE_HW_INET_ECN_MASK 3 ++#define VXGE_HW_INET_ECN_CE 3 ++ ++enum vxge_hw_status ++__vxge_hw_sw_lro_init(struct __vxge_hw_ring *ring); ++enum vxge_hw_status ++__vxge_hw_sw_lro_reset(struct __vxge_hw_ring *ring); ++enum vxge_hw_status ++__vxge_hw_sw_lro_terminate(struct __vxge_hw_ring *ring); ++ ++enum vxge_hw_status ++__vxge_hw_sw_lro_capable(struct __vxge_hw_ring *ring, u8 *buffer, ++ struct iphdr **ip, ++ struct tcphdr **tcp, ++ struct vxge_hw_ring_rxd_info *ext_info); ++ ++void vxge_hw_vpath_set_lro_sg_size( ++ struct __vxge_hw_vpath_handle *vpath_handle, int lro_sg_size); ++ ++enum vxge_hw_status ++vxge_hw_sw_lro_rx_process( ++ struct __vxge_hw_ring *ringh, ++ struct vxge_hw_ring_rxd_info *rxd_info, ++ u8 *eth_hdr, ++ u32 *seglen, ++ struct vxge_hw_sw_lro **sw_lro); ++ ++void vxge_hw_update_L3L4_header( ++ struct __vxge_hw_ring *ringh, ++ struct vxge_hw_sw_lro *lro); ++ ++struct vxge_hw_sw_lro * ++vxge_hw_sw_lro_next_session_get ( ++ struct __vxge_hw_ring *ringh, ++ struct vxge_hw_sw_lro *sw_lro); ++ ++void ++vxge_hw_sw_lro_session_close( ++ struct __vxge_hw_ring *ringh, ++ struct vxge_hw_sw_lro *sw_lro); ++ ++#endif ++#endif +diff -r 158b6e53275e drivers/net/vxge/vxge-version.h +--- /dev/null Thu Jan 01 00:00:00 1970 +0000 ++++ b/drivers/net/vxge/vxge-version.h Wed Aug 05 11:58:00 2009 +0100 +@@ -0,0 +1,15 @@ ++/****************************************************************************** ++ * vxge-version.h: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O ++ * Virtualized Server Adapter. ++ * Copyright(c) 2002-2009 Neterion Inc. ++ ******************************************************************************/ ++#ifndef VXGE_VERSION_H ++ ++#define VXGE_VERSION_H ++ ++#define VXGE_VERSION_MAJOR "2" ++#define VXGE_VERSION_MINOR "0" ++#define VXGE_VERSION_FIX "6" ++#define VXGE_VERSION_BUILD "18061" ++#define VXGE_VERSION_FOR "noSYSFS" ++#endif -- 2.39.5